From 50dbcfe02a74b67663e834fa23bfeaea6c1043a5 Mon Sep 17 00:00:00 2001 From: Mikhail Anikin Date: Wed, 14 Aug 2024 15:08:43 +0300 Subject: [PATCH] Hailo BSP v1.4.0 Bump to v1.4.0 Add WiFi support Add HB IIoT carrier support --- .github/workflows/build.yml | 5 +- conf/docker/Dockerfile | 8 +- conf/includes/ci.conf | 2 + conf/includes/hailo_demo.conf | 4 +- conf/includes/sr_image.conf | 3 + conf/machine/hailo15-solidrun.conf | 4 + kas/hailo15-solidrun.yaml | 1 - kas/meta-hailo-soc.yaml | 5 +- .../brcmfmac43455-sdio.hailo,hailo15.txt | 115 + .../linux-firmware/linux-firmware_%.bbappend | 13 + recipes-bsp/scu-bl/scu-bl.bbappend | 1 + ...03-Hailo-15-SolidRun-initial-support.patch | 29 + .../u-boot/files/0003-u-boot-wget.patch | 1827 + ...ix-eMMC-drive-strength-in-the-u-boot.patch | 27 - .../0004-Hailo-15-SolidRun-support.patch | 794 + recipes-bsp/u-boot/u-boot_%.bbappend | 4 +- .../linux/linux-yocto-hailo.bbappend | 3 +- .../0001-Fix-kernel-symlinks.patch | 1218274 ++++++++++++++ ...02-Hailo-15-SolidRun-initial-support.patch | 308 - .../0002-Hailo-15-SolidRun-support.patch | 1079 + .../linux-yocto-hailo/solidrun-H15-SOM.cfg | 16 + 21 files changed, 1222173 insertions(+), 349 deletions(-) create mode 100644 recipes-bsp/linux-firmware/files/brcmfmac43455-sdio.hailo,hailo15.txt create mode 100644 recipes-bsp/linux-firmware/linux-firmware_%.bbappend create mode 100644 recipes-bsp/scu-bl/scu-bl.bbappend create mode 100644 recipes-bsp/u-boot/files/0003-u-boot-wget.patch delete mode 100644 recipes-bsp/u-boot/files/0004-Fix-eMMC-drive-strength-in-the-u-boot.patch create mode 100644 recipes-bsp/u-boot/files/0004-Hailo-15-SolidRun-support.patch create mode 100644 recipes-kernel/linux/linux-yocto-hailo/0001-Fix-kernel-symlinks.patch delete mode 100644 recipes-kernel/linux/linux-yocto-hailo/0002-Hailo-15-SolidRun-initial-support.patch create mode 100644 recipes-kernel/linux/linux-yocto-hailo/0002-Hailo-15-SolidRun-support.patch diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index f545ab4..ec08380 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -111,6 +111,7 @@ jobs: export BB_ENV_PASSTHROUGH_ADDITIONS="$BB_ENV_PASSTHROUGH_ADDITIONS CACHE_DIR" echo "require conf/includes/ci.conf" >> conf/local.conf cat conf/local.conf + bitbake core-image-minimal --runall=fetch bitbake core-image-minimal - name: Update cache on the server @@ -139,6 +140,8 @@ jobs: cp $BUILD_PATH/fitImage deploy/ cp $BUILD_PATH/hailo15_scu_bl.bin deploy/ cp $BUILD_PATH/hailo15_scu_fw.bin deploy/ + cp $BUILD_PATH/scu_bl_cfg_a.bin deploy/ + cp $BUILD_PATH/scu_bl_cfg_b.bin deploy/ cp $BUILD_PATH/u-boot.dtb.signed deploy/ cp $BUILD_PATH/u-boot-initial-env deploy/ cp $BUILD_PATH/u-boot-spl.bin deploy/ @@ -178,7 +181,7 @@ jobs: run: | mkdir -p s3 tar cJf s3/solidrun-hailo15_${{ needs.build_images.outputs.build_tag }}.tar.xz \ - deploy/* + -C deploy/ . - name: Upload to S3 uses: shallwefootball/upload-s3-action@v1.3.3 diff --git a/conf/docker/Dockerfile b/conf/docker/Dockerfile index 92fcfd0..9524b88 100644 --- a/conf/docker/Dockerfile +++ b/conf/docker/Dockerfile @@ -22,7 +22,7 @@ RUN apt-get update && apt-get install -y apt-transport-https \ python3-subunit mesa-common-dev patchelf \ zstd liblz4-tool file locales libacl1 \ tree sudo locales ca-certificates \ - bash icecc + bash icecc tmux RUN locale-gen en_US.UTF-8 @@ -32,9 +32,9 @@ RUN update-ca-certificates RUN python3 -m pip install kas # Set environment variables -ENV LANG=en_US.UTF-8 \ - LANGUAGE=en_US:en \ - LC_ALL=en_US.UTF-8 +ENV LANG en_US.UTF-8 +ENV LANGUAGE en_US:en +ENV LC_ALL en_US.UTF-8 # Arguments to pass host user's UID and GID ARG USER_ID=1000 diff --git a/conf/includes/ci.conf b/conf/includes/ci.conf index 42fbab1..5a01e7b 100644 --- a/conf/includes/ci.conf +++ b/conf/includes/ci.conf @@ -15,3 +15,5 @@ INHERIT += "icecc" INHERIT += "rm_work" +ICECC_RECIPE_DISABLE += "libgsthailo" +CCACHE_DISABLE:pn-libgsthailo = "1" diff --git a/conf/includes/hailo_demo.conf b/conf/includes/hailo_demo.conf index 6dfbdf2..5496741 100644 --- a/conf/includes/hailo_demo.conf +++ b/conf/includes/hailo_demo.conf @@ -12,7 +12,7 @@ PACKAGECONFIG:append:pn-gstreamer1.0 = " gst-tracer-hooks tracer-hooks coretrace ADD_GSTREAMER_TO_IMAGE = "true" # hailo-integrated-nnc -CORE_IMAGE_EXTRA_INSTALL:append = " hailo-integrated-nnc" +CORE_IMAGE_EXTRA_INSTALL:append = " hailo-integrated-nnc" # hailo15-nnc-fw CORE_IMAGE_EXTRA_INSTALL:append = " hailo15-nnc-fw" @@ -25,7 +25,7 @@ CORE_IMAGE_EXTRA_INSTALL:append = " libhailort" CORE_IMAGE_EXTRA_INSTALL:append = " hailortcli" # media-library -CORE_IMAGE_EXTRA_INSTALL:append = " libgstmedialib libencoderosd" +CORE_IMAGE_EXTRA_INSTALL:append = " libgstmedialib" # opencv CORE_IMAGE_EXTRA_INSTALL:append = " opencv" diff --git a/conf/includes/sr_image.conf b/conf/includes/sr_image.conf index 332497c..72fc66d 100644 --- a/conf/includes/sr_image.conf +++ b/conf/includes/sr_image.conf @@ -1,3 +1,6 @@ # Image settings IMAGE_INSTALL:append = " bmap-tools" IMAGE_FSTYPES:append = " wic.bmap wic.xz" + +IMAGE_INSTALL:append = " bluez5" +IMAGE_INSTALL:append = " connman connman-client" \ No newline at end of file diff --git a/conf/machine/hailo15-solidrun.conf b/conf/machine/hailo15-solidrun.conf index e06c59d..e298365 100644 --- a/conf/machine/hailo15-solidrun.conf +++ b/conf/machine/hailo15-solidrun.conf @@ -10,3 +10,7 @@ MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "kernel-module-brcmfmac \ linux-firmware-bcm43455 \ " MACHINE_FEATURES += "bluetooth wifi" + +KERNEL_DEVICETREE:append = " \ + ${LINUX_YOCTO_HAILO_BOARD_VENDOR}/hailo15-solidrun-hb-pro.dtb \ +" diff --git a/kas/hailo15-solidrun.yaml b/kas/hailo15-solidrun.yaml index 8abf5cd..eaa3155 100644 --- a/kas/hailo15-solidrun.yaml +++ b/kas/hailo15-solidrun.yaml @@ -15,7 +15,6 @@ local_conf_header: meta-solidrun-arm-hailo: | require conf/includes/sr_image.conf require conf/includes/hailo_demo.conf - MACHINE_FEATURES += "imx334" repos: meta-solidrun-arm-hailo: diff --git a/kas/meta-hailo-soc.yaml b/kas/meta-hailo-soc.yaml index 4f19b1c..4005b75 100644 --- a/kas/meta-hailo-soc.yaml +++ b/kas/meta-hailo-soc.yaml @@ -4,7 +4,7 @@ header: repos: meta-hailo-soc: url: https://github.com/hailo-ai/meta-hailo-soc/ - commit: 860c3728b3d2e8ae09e5b35a012bb64ef7750cdb + commit: a3784cced763ea7e17f05acfb9912682e570a327 layers: meta-hailo-bsp-examples: excluded meta-hailo-bsp: @@ -15,9 +15,8 @@ repos: meta-hailo: url: "https://github.com/hailo-ai/meta-hailo.git" - commit: ee95e0594a860177511ab492fd275c4727f6c52f + commit: 5d52200a54ede32230e5edc68d42ac402beeabb4 layers: meta-hailo-libhailort: meta-hailo-vpu: meta-hailo-tappas: - diff --git a/recipes-bsp/linux-firmware/files/brcmfmac43455-sdio.hailo,hailo15.txt b/recipes-bsp/linux-firmware/files/brcmfmac43455-sdio.hailo,hailo15.txt new file mode 100644 index 0000000..a380e41 --- /dev/null +++ b/recipes-bsp/linux-firmware/files/brcmfmac43455-sdio.hailo,hailo15.txt @@ -0,0 +1,115 @@ +# Cloned from bcm94345wlpagb.txt +NVRAMRev=$Rev: 498373 $ +sromrev=11 +vendid=0x14e4 +devid=0x43ab +manfid=0x2d0 +prodid=0x06e4 +macaddr=00:90:4c:c5:12:38 +nocrc=1 +boardtype=0x6e4 + +##boardrev - superseded by the one in OTP +boardrev=0x1100 +xtalfreq=37400 +## tune where necessary +#xtal_swcapio=0x6644 +boardflags=0x00080201 +boardflags2=0x40000000 +boardflags3=0x44200100 +rxchain=1 +txchain=1 +aa2g=1 +aa5g=1 +tssipos5g=1 +tssipos2g=1 +AvVmid_c0=0,157,1,126,1,126,1,126,1,126 +pa2ga0=-152,5969,-666 +pa2ga1=-143,4076,-546 +pa5ga0=-165,5736,-689,-169,5710,-692,-171,5713,-688,-173,5732,-689 +#pa5ga1=-161,3672,-510,-166,3671,-508,-169,3697,-508,-171,3854,-520 +itrsw=1 +pdoffset40ma0=0x9999 +pdoffset80ma0=0x8888 +extpagain5g=2 +extpagain2g=2 +maxp2ga0=74 +cckbw202gpo=0x0000 +ofdmlrbw202gpo=0x0022 +dot11agofdmhrbw202gpo=0x8888 +mcsbw202gpo=0xaaaaa666 +maxp5ga0=76,76,76,76 +mcsbw205glpo=0x99999955 +mcsbw205gmpo=0x99999955 +mcsbw205ghpo=0x99999955 +mcsbw405glpo=0xff999555 +mcsbw405gmpo=0xff999555 +mcsbw405ghpo=0xff999555 +mcsbw805glpo=0xfffffbbb +mcsbw805gmpo=0xfffffbbb +mcsbw805ghpo=0xfffffbbb +swctrlmap_2g=0x00040004,0x00020002,0x00040004,0x010a02,0x1ff +swctrlmap_5g=0x00100010,0x00200020,0x00200020,0x010a02,0x2f4 +swctrlmapext_5g=0x00000000,0x00000000,0x00000000,0x000000,0x000 +swctrlmapext_2g=0x00000000,0x00000000,0x00000000,0x000000,0x000 +vcodivmode=1 +##filter parameters -- tune where necessary +cckdigfilttype=6 +fdss_level_2g=2 +fdss_level_5g=2 +## added by apps +aga0=0x1 +agbg0=0x1 +ccode=0 +ed_thresh2g=-65 +ed_thresh5g=-65 +ltecxmux=0 +ltecxpadnum=0x0504 +ltecxfnsel=0x22 +ltecxgcigpio=0x32 +pdoffsetcckma0=0x0000 +powoffs2gtna0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 +tempthresh=120 +temps_hysteresis=15 +rawtempsense=0x1ff +tworangetssi2g=1 +tworangetssi5g=0 +lowpowerrange2g=0 +lowpowerrange5g=0 +ag0=1 +ag1=1 +#subband5gver=0x4 +mcslr5glpo=0x0000 +mcslr5gmpo=0x0000 +mcslr5ghpo=0x0000 +sb20in40hrpo=0x0 +sb20in80and160hr5glpo=0x0 +sb40and80hr5glpo=0x0 +sb20in80and160hr5gmpo=0x0 +sb40and80hr5gmpo=0x0 +sb20in80and160hr5ghpo=0x0 +sb40and80hr5ghpo=0x0 +sb20in40lrpo=0x0 +sb20in80and160lr5glpo=0x0 +sb40and80lr5glpo=0x0 +sb20in80and160lr5gmpo=0x0 +sb40and80lr5gmpo=0x0 +sb20in80and160lr5ghpo=0x0 +sb40and80lr5ghpo=0x0 +dot11agduphrpo=0x0 +dot11agduplrpo=0x0 +phycal_tempdelta=25 +temps_period=15 +btc_mode=1 +sbpowoffs5g20mtna0=0,0,0,0 +sbpowoffs5g40mtna0=0,0,0,0 +sbpowoffs5g80mtna0=0,0,0,0 +powoffs5g20mtna0=0,0,0,0,0,0,0 +powoffs5g40mtna0=0,0,0,0,0 +powoffs5g80mtna0=0,0,0,0,0 +ldo1=5 +cbfilttype=2 +xtal_swcapio=0x8855 +fdss_level_ch13=1,1 +# muxenab defined to enable OOB IRQ. Level sensitive interrupt via WL_HOST_WAKE line. +muxenab=0x10 diff --git a/recipes-bsp/linux-firmware/linux-firmware_%.bbappend b/recipes-bsp/linux-firmware/linux-firmware_%.bbappend new file mode 100644 index 0000000..ebbaae9 --- /dev/null +++ b/recipes-bsp/linux-firmware/linux-firmware_%.bbappend @@ -0,0 +1,13 @@ +# Solidrun hailo15 SOM WiFi settings + +FILESEXTRAPATHS:prepend := "${THISDIR}/files:" + +SRC_URI:append = " \ + file://brcmfmac43455-sdio.hailo,hailo15.txt \ +" + +do_install:append() { + cp ${WORKDIR}/brcmfmac43455-sdio.hailo,hailo15.txt ${D}${nonarch_base_libdir}/firmware/brcm + cd ${D}${nonarch_base_libdir}/firmware/brcm + ln -s brcmfmac43455-sdio.bin brcmfmac43455-sdio.hailo,hailo15.bin +} diff --git a/recipes-bsp/scu-bl/scu-bl.bbappend b/recipes-bsp/scu-bl/scu-bl.bbappend new file mode 100644 index 0000000..7f773b6 --- /dev/null +++ b/recipes-bsp/scu-bl/scu-bl.bbappend @@ -0,0 +1 @@ +addtask deploy after do_install diff --git a/recipes-bsp/u-boot/files/0003-Hailo-15-SolidRun-initial-support.patch b/recipes-bsp/u-boot/files/0003-Hailo-15-SolidRun-initial-support.patch index 4e554f6..1eb0038 100644 --- a/recipes-bsp/u-boot/files/0003-Hailo-15-SolidRun-initial-support.patch +++ b/recipes-bsp/u-boot/files/0003-Hailo-15-SolidRun-initial-support.patch @@ -362,3 +362,32 @@ index 0000000000..318226cba4 -- 2.45.0 +From 5b9daecc179a1f8ae422ca15f61bb105a4c248fe Mon Sep 17 00:00:00 2001 +From: Mikhail Anikin +Date: Wed, 22 May 2024 15:57:59 +0300 +Subject: [PATCH] Update DDR binding + +--- + arch/arm/dts/hailo15-solidrun.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/dts/hailo15-solidrun.dts b/arch/arm/dts/hailo15-solidrun.dts +index 0dca2f137e..e9322f5254 100644 +--- a/arch/arm/dts/hailo15-solidrun.dts ++++ b/arch/arm/dts/hailo15-solidrun.dts +@@ -5,8 +5,8 @@ + */ + + #include "hailo15-base.dtsi" +-#include "hailo15_ddr_MT53E1G32D2FW-046_configuration.dtsi" +-#include "hailo15_ddr_MT53E1G32D2FW-046_regconfig_ca_odtb_pd.dtsi" ++#include "hailo15_ddr_configuration.dtsi" ++#include "hailo15_ddr_MT53E1G32D2FW-046_regconfig_ca_odtb_pd_4GB.dtsi" + #include + + / { +-- +2.43.2 + + + diff --git a/recipes-bsp/u-boot/files/0003-u-boot-wget.patch b/recipes-bsp/u-boot/files/0003-u-boot-wget.patch new file mode 100644 index 0000000..96a5004 --- /dev/null +++ b/recipes-bsp/u-boot/files/0003-u-boot-wget.patch @@ -0,0 +1,1827 @@ +From 317aeaa67bf481d24b99268c4b24b0c3a96b9bf3 Mon Sep 17 00:00:00 2001 +From: "Ying-Chun Liu (PaulLiu)" +Date: Tue, 8 Nov 2022 14:17:28 +0800 +Subject: [PATCH 1/2] net: Add TCP protocol + +Currently file transfers are done using tftp or NFS both +over udp. This requires a request to be sent from client +(u-boot) to the boot server. + +The current standard is TCP with selective acknowledgment. + +Signed-off-by: Duncan Hare +Signed-off-by: Duncan Hare +Signed-off-by: Ying-Chun Liu (PaulLiu) +Reviewed-by: Simon Glass +Cc: Christian Gmeiner +Cc: Joe Hershberger +Cc: Michal Simek +Cc: Ramon Fried +Reviewed-by: Ramon Fried +--- + include/net.h | 36 ++- + include/net/tcp.h | 299 +++++++++++++++++++ + net/Kconfig | 16 ++ + net/Makefile | 1 + + net/net.c | 30 ++ + net/tcp.c | 720 ++++++++++++++++++++++++++++++++++++++++++++++ + 6 files changed, 1093 insertions(+), 9 deletions(-) + create mode 100644 include/net/tcp.h + create mode 100644 net/tcp.c + +diff --git a/include/net.h b/include/net.h +index 09d7e9b9e8..859ebae04b 100644 +--- a/include/net.h ++++ b/include/net.h +@@ -371,6 +371,7 @@ struct vlan_ethernet_hdr { + #define PROT_NCSI 0x88f8 /* NC-SI control packets */ + + #define IPPROTO_ICMP 1 /* Internet Control Message Protocol */ ++#define IPPROTO_TCP 6 /* Transmission Control Protocol */ + #define IPPROTO_UDP 17 /* User Datagram Protocol */ + + /* +@@ -694,19 +695,36 @@ static inline void net_send_packet(uchar *pkt, int len) + (void) eth_send(pkt, len); + } + +-/* +- * Transmit "net_tx_packet" as UDP packet, performing ARP request if needed +- * (ether will be populated) +- * +- * @param ether Raw packet buffer +- * @param dest IP address to send the datagram to +- * @param dport Destination UDP port +- * @param sport Source UDP port +- * @param payload_len Length of data after the UDP header ++/** ++ * net_send_ip_packet() - Transmit "net_tx_packet" as UDP or TCP packet, ++ * send ARP request if needed (ether will be populated) ++ * @ether: Raw packet buffer ++ * @dest: IP address to send the datagram to ++ * @dport: Destination UDP port ++ * @sport: Source UDP port ++ * @payload_len: Length of data after the UDP header ++ * @action: TCP action to be performed ++ * @tcp_seq_num: TCP sequence number of this transmission ++ * @tcp_ack_num: TCP stream acknolegement number ++ * ++ * Return: 0 on success, other value on failure + */ + int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int sport, + int payload_len, int proto, u8 action, u32 tcp_seq_num, + u32 tcp_ack_num); ++/** ++ * net_send_tcp_packet() - Transmit TCP packet. ++ * @payload_len: length of payload ++ * @dport: Destination TCP port ++ * @sport: Source TCP port ++ * @action: TCP action to be performed ++ * @tcp_seq_num: TCP sequence number of this transmission ++ * @tcp_ack_num: TCP stream acknolegement number ++ * ++ * Return: 0 on success, other value on failure ++ */ ++int net_send_tcp_packet(int payload_len, int dport, int sport, u8 action, ++ u32 tcp_seq_num, u32 tcp_ack_num); + int net_send_udp_packet(uchar *ether, struct in_addr dest, int dport, + int sport, int payload_len); + +diff --git a/include/net/tcp.h b/include/net/tcp.h +new file mode 100644 +index 0000000000..322551694f +--- /dev/null ++++ b/include/net/tcp.h +@@ -0,0 +1,299 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * TCP Support with SACK for file transfer. ++ * ++ * Copyright 2017 Duncan Hare, All rights reserved. ++ */ ++ ++#define TCP_ACTIVITY 127 /* Number of packets received */ ++ /* before console progress mark */ ++/** ++ * struct ip_tcp_hdr - IP and TCP header ++ * @ip_hl_v: header length and version ++ * @ip_tos: type of service ++ * @ip_len: total length ++ * @ip_id: identification ++ * @ip_off: fragment offset field ++ * @ip_ttl: time to live ++ * @ip_p: protocol ++ * @ip_sum: checksum ++ * @ip_src: Source IP address ++ * @ip_dst: Destination IP address ++ * @tcp_src: TCP source port ++ * @tcp_dst: TCP destination port ++ * @tcp_seq: TCP sequence number ++ * @tcp_ack: TCP Acknowledgment number ++ * @tcp_hlen: 4 bits TCP header Length/4, 4 bits reserved, 2 more bits reserved ++ * @tcp_flag: flags of TCP ++ * @tcp_win: TCP windows size ++ * @tcp_xsum: Checksum ++ * @tcp_ugr: Pointer to urgent data ++ */ ++struct ip_tcp_hdr { ++ u8 ip_hl_v; ++ u8 ip_tos; ++ u16 ip_len; ++ u16 ip_id; ++ u16 ip_off; ++ u8 ip_ttl; ++ u8 ip_p; ++ u16 ip_sum; ++ struct in_addr ip_src; ++ struct in_addr ip_dst; ++ u16 tcp_src; ++ u16 tcp_dst; ++ u32 tcp_seq; ++ u32 tcp_ack; ++ u8 tcp_hlen; ++ u8 tcp_flags; ++ u16 tcp_win; ++ u16 tcp_xsum; ++ u16 tcp_ugr; ++} __packed; ++ ++#define IP_TCP_HDR_SIZE (sizeof(struct ip_tcp_hdr)) ++#define TCP_HDR_SIZE (IP_TCP_HDR_SIZE - IP_HDR_SIZE) ++ ++#define TCP_DATA 0x00 /* Data Packet - internal use only */ ++#define TCP_FIN 0x01 /* Finish flag */ ++#define TCP_SYN 0x02 /* Synch (start) flag */ ++#define TCP_RST 0x04 /* reset flag */ ++#define TCP_PUSH 0x08 /* Push - Notify app */ ++#define TCP_ACK 0x10 /* Acknowledgment of data received */ ++#define TCP_URG 0x20 /* Urgent */ ++#define TCP_ECE 0x40 /* Congestion control */ ++#define TCP_CWR 0x80 /* Congestion Control */ ++ ++/* ++ * TCP header options, Seq, MSS, and SACK ++ */ ++ ++#define TCP_SACK 32 /* Number of packets analyzed */ ++ /* on leading edge of stream */ ++ ++#define TCP_O_END 0x00 /* End of option list */ ++#define TCP_1_NOP 0x01 /* Single padding NOP */ ++#define TCP_O_NOP 0x01010101 /* NOPs pad to 32 bit boundary */ ++#define TCP_O_MSS 0x02 /* MSS Size option */ ++#define TCP_O_SCL 0x03 /* Window Scale option */ ++#define TCP_P_SACK 0x04 /* SACK permitted */ ++#define TCP_V_SACK 0x05 /* SACK values */ ++#define TCP_O_TS 0x08 /* Timestamp option */ ++#define TCP_OPT_LEN_2 0x02 ++#define TCP_OPT_LEN_3 0x03 ++#define TCP_OPT_LEN_4 0x04 ++#define TCP_OPT_LEN_6 0x06 ++#define TCP_OPT_LEN_8 0x08 ++#define TCP_OPT_LEN_A 0x0a /* Timestamp Length */ ++#define TCP_MSS 1460 /* Max segment size */ ++#define TCP_SCALE 0x01 /* Scale */ ++ ++/** ++ * struct tcp_mss - TCP option structure for MSS (Max segment size) ++ * @kind: Field ID ++ * @len: Field length ++ * @mss: Segment size value ++ */ ++struct tcp_mss { ++ u8 kind; ++ u8 len; ++ u16 mss; ++} __packed; ++ ++/** ++ * struct tcp_scale - TCP option structure for Windows scale ++ * @kind: Field ID ++ * @len: Field length ++ * @scale: windows shift value used for networks with many hops. ++ * Typically 4 or more hops ++ */ ++struct tcp_scale { ++ u8 kind; ++ u8 len; ++ u8 scale; ++} __packed; ++ ++/** ++ * struct tcp_sack_p - TCP option structure for SACK permitted ++ * @kind: Field ID ++ * @len: Field length ++ */ ++struct tcp_sack_p { ++ u8 kind; ++ u8 len; ++} __packed; ++ ++/** ++ * struct sack_edges - structure for SACK edges ++ * @l: Left edge of stream ++ * @r: right edge of stream ++ */ ++struct sack_edges { ++ u32 l; ++ u32 r; ++} __packed; ++ ++#define TCP_SACK_SIZE (sizeof(struct sack_edges)) ++ ++/* ++ * A TCP stream has holes when packets are missing or disordered. ++ * A hill is the inverse of a hole, and is data received. ++ * TCP received hills (a sequence of data), and inferrs Holes ++ * from the "hills" or packets received. ++ */ ++ ++#define TCP_SACK_HILLS 4 ++ ++/** ++ * struct tcp_sack_v - TCP option structure for SACK ++ * @kind: Field ID ++ * @len: Field length ++ * @hill: L & R window edges ++ */ ++struct tcp_sack_v { ++ u8 kind; ++ u8 len; ++ struct sack_edges hill[TCP_SACK_HILLS]; ++} __packed; ++ ++/** ++ * struct tcp_t_opt - TCP option structure for time stamps ++ * @kind: Field ID ++ * @len: Field length ++ * @t_snd: Sender timestamp ++ * @t_rcv: Receiver timestamp ++ */ ++struct tcp_t_opt { ++ u8 kind; ++ u8 len; ++ u32 t_snd; ++ u32 t_rcv; ++} __packed; ++ ++#define TCP_TSOPT_SIZE (sizeof(struct tcp_t_opt)) ++ ++/* ++ * ip tcp structure with options ++ */ ++ ++/** ++ * struct ip_tcp_hdr_o - IP + TCP header + TCP options ++ * @hdr: IP + TCP header ++ * @mss: TCP MSS Option ++ * @scale: TCP Windows Scale Option ++ * @sack_p: TCP Sack-Permitted Option ++ * @t_opt: TCP Timestamp Option ++ * @end: end of options ++ */ ++struct ip_tcp_hdr_o { ++ struct ip_tcp_hdr hdr; ++ struct tcp_mss mss; ++ struct tcp_scale scale; ++ struct tcp_sack_p sack_p; ++ struct tcp_t_opt t_opt; ++ u8 end; ++} __packed; ++ ++#define IP_TCP_O_SIZE (sizeof(struct ip_tcp_hdr_o)) ++ ++/** ++ * struct ip_tcp_hdr_s - IP + TCP header + TCP options ++ * @hdr: IP + TCP header ++ * @t_opt: TCP Timestamp Option ++ * @sack_v: TCP SACK Option ++ * @end: end of options ++ */ ++struct ip_tcp_hdr_s { ++ struct ip_tcp_hdr hdr; ++ struct tcp_t_opt t_opt; ++ struct tcp_sack_v sack_v; ++ u8 end; ++} __packed; ++ ++#define IP_TCP_SACK_SIZE (sizeof(struct ip_tcp_hdr_s)) ++ ++/* ++ * TCP pseudo header definitions ++ */ ++#define PSEUDO_PAD_SIZE 8 ++ ++/** ++ * struct pseudo_hdr - Pseudo Header ++ * @padding: pseudo hdr size = ip_tcp hdr size ++ * @p_src: Source IP address ++ * @p_dst: Destination IP address ++ * @rsvd: reserved ++ * @p: protocol ++ * @len: length of header ++ */ ++struct pseudo_hdr { ++ u8 padding[PSEUDO_PAD_SIZE]; ++ struct in_addr p_src; ++ struct in_addr p_dst; ++ u8 rsvd; ++ u8 p; ++ u16 len; ++} __packed; ++ ++#define PSEUDO_HDR_SIZE (sizeof(struct pseudo_hdr)) - PSEUDO_PAD_SIZE ++ ++/** ++ * union tcp_build_pkt - union for building TCP/IP packet. ++ * @ph: pseudo header ++ * @ip: IP and TCP header plus TCP options ++ * @sack: IP and TCP header plus SACK options ++ * @raw: buffer ++ * ++ * Build Pseudo header in packed buffer ++ * first, calculate TCP checksum, then build IP header in packed buffer. ++ * ++ */ ++union tcp_build_pkt { ++ struct pseudo_hdr ph; ++ struct ip_tcp_hdr_o ip; ++ struct ip_tcp_hdr_s sack; ++ uchar raw[1600]; ++} __packed; ++ ++/** ++ * enum tcp_state - TCP State machine states for connection ++ * @TCP_CLOSED: Need to send SYN to connect ++ * @TCP_SYN_SENT: Trying to connect, waiting for SYN ACK ++ * @TCP_ESTABLISHED: both server & client have a connection ++ * @TCP_CLOSE_WAIT: Rec FIN, passed to app for FIN, ACK rsp ++ * @TCP_CLOSING: Rec FIN, sent FIN, ACK waiting for ACK ++ * @TCP_FIN_WAIT_1: Sent FIN waiting for response ++ * @TCP_FIN_WAIT_2: Rec ACK from FIN sent, waiting for FIN ++ */ ++enum tcp_state { ++ TCP_CLOSED, ++ TCP_SYN_SENT, ++ TCP_ESTABLISHED, ++ TCP_CLOSE_WAIT, ++ TCP_CLOSING, ++ TCP_FIN_WAIT_1, ++ TCP_FIN_WAIT_2 ++}; ++ ++enum tcp_state tcp_get_tcp_state(void); ++void tcp_set_tcp_state(enum tcp_state new_state); ++int tcp_set_tcp_header(uchar *pkt, int dport, int sport, int payload_len, ++ u8 action, u32 tcp_seq_num, u32 tcp_ack_num); ++ ++/** ++ * rxhand_tcp() - An incoming packet handler. ++ * @pkt: pointer to the application packet ++ * @dport: destination UDP port ++ * @sip: source IP address ++ * @sport: source UDP port ++ * @len: packet length ++ */ ++typedef void rxhand_tcp(uchar *pkt, unsigned int dport, ++ struct in_addr sip, unsigned int sport, ++ unsigned int len); ++void tcp_set_tcp_handler(rxhand_tcp *f); ++ ++void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int len); ++ ++u16 tcp_set_pseudo_header(uchar *pkt, struct in_addr src, struct in_addr dest, ++ int tcp_len, int pkt_len); +diff --git a/net/Kconfig b/net/Kconfig +index ba0ca813ce..fed88b52dc 100644 +--- a/net/Kconfig ++++ b/net/Kconfig +@@ -99,4 +99,20 @@ config SERVERIP_FROM_PROXYDHCP_DELAY_MS + receiving response from main DHCP server. Has no effect if + SERVERIP_FROM_PROXYDHCP is false. + ++config PROT_TCP ++ bool "TCP stack" ++ help ++ Enable a generic tcp framework that allows defining a custom ++ handler for tcp protocol. ++ ++config PROT_TCP_SACK ++ bool "TCP SACK support" ++ depends on PROT_TCP ++ help ++ TCP protocol with SACK. SACK means selective acknowledgements. ++ By turning this option on TCP will learn what segments are already ++ received. So that it improves TCP's retransmission efficiency. ++ This option should be turn on if you want to achieve the fastest ++ file transfer possible. ++ + endif # if NET +diff --git a/net/Makefile b/net/Makefile +index fb3eba840f..f68ad94767 100644 +--- a/net/Makefile ++++ b/net/Makefile +@@ -29,6 +29,7 @@ obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o + obj-$(CONFIG_UDP_FUNCTION_FASTBOOT) += fastboot.o + obj-$(CONFIG_CMD_WOL) += wol.o + obj-$(CONFIG_PROT_UDP) += udp.o ++obj-$(CONFIG_PROT_TCP) += tcp.o + + # Disable this warning as it is triggered by: + # sprintf(buf, index ? "foo%d" : "foo", index) +diff --git a/net/net.c b/net/net.c +index f5400e6dbc..5f11dcac84 100644 +--- a/net/net.c ++++ b/net/net.c +@@ -116,6 +116,7 @@ + #if defined(CONFIG_CMD_WOL) + #include "wol.h" + #endif ++#include + + /** BOOTP EXTENTIONS **/ + +@@ -386,6 +387,8 @@ int net_init(void) + + /* Only need to setup buffer pointers once. */ + first_call = 0; ++ if (IS_ENABLED(CONFIG_PROT_TCP)) ++ tcp_set_tcp_state(TCP_CLOSED); + } + + return net_init_loop(); +@@ -816,6 +819,16 @@ int net_send_udp_packet(uchar *ether, struct in_addr dest, int dport, int sport, + IPPROTO_UDP, 0, 0, 0); + } + ++#if defined(CONFIG_PROT_TCP) ++int net_send_tcp_packet(int payload_len, int dport, int sport, u8 action, ++ u32 tcp_seq_num, u32 tcp_ack_num) ++{ ++ return net_send_ip_packet(net_server_ethaddr, net_server_ip, dport, ++ sport, payload_len, IPPROTO_TCP, action, ++ tcp_seq_num, tcp_ack_num); ++} ++#endif ++ + int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int sport, + int payload_len, int proto, u8 action, u32 tcp_seq_num, + u32 tcp_ack_num) +@@ -847,6 +860,14 @@ int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int sport, + payload_len); + pkt_hdr_size = eth_hdr_size + IP_UDP_HDR_SIZE; + break; ++#if defined(CONFIG_PROT_TCP) ++ case IPPROTO_TCP: ++ pkt_hdr_size = eth_hdr_size ++ + tcp_set_tcp_header(pkt + eth_hdr_size, dport, sport, ++ payload_len, action, tcp_seq_num, ++ tcp_ack_num); ++ break; ++#endif + default: + return -EINVAL; + } +@@ -1256,6 +1277,15 @@ void net_process_received_packet(uchar *in_packet, int len) + if (ip->ip_p == IPPROTO_ICMP) { + receive_icmp(ip, len, src_ip, et); + return; ++#if defined(CONFIG_PROT_TCP) ++ } else if (ip->ip_p == IPPROTO_TCP) { ++ debug_cond(DEBUG_DEV_PKT, ++ "TCP PH (to=%pI4, from=%pI4, len=%d)\n", ++ &dst_ip, &src_ip, len); ++ ++ rxhand_tcp_f((union tcp_build_pkt *)ip, len); ++ return; ++#endif + } else if (ip->ip_p != IPPROTO_UDP) { /* Only UDP packets */ + return; + } +diff --git a/net/tcp.c b/net/tcp.c +new file mode 100644 +index 0000000000..8d338c72e8 +--- /dev/null ++++ b/net/tcp.c +@@ -0,0 +1,720 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright 2017 Duncan Hare, all rights reserved. ++ */ ++ ++/* ++ * General Desription: ++ * ++ * TCP support for the wget command, for fast file downloading. ++ * ++ * HTTP/TCP Receiver: ++ * ++ * Prerequisites: - own ethernet address ++ * - own IP address ++ * - Server IP address ++ * - Server with TCP ++ * - TCP application (eg wget) ++ * Next Step HTTPS? ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * TCP sliding window control used by us to request re-TX ++ */ ++static struct tcp_sack_v tcp_lost; ++ ++/* TCP option timestamp */ ++static u32 loc_timestamp; ++static u32 rmt_timestamp; ++ ++static u32 tcp_seq_init; ++static u32 tcp_ack_edge; ++static u32 tcp_seq_max; ++ ++static int tcp_activity_count; ++ ++/* ++ * Search for TCP_SACK and review the comments before the code section ++ * TCP_SACK is the number of packets at the front of the stream ++ */ ++ ++enum pkt_state {PKT, NOPKT}; ++struct sack_r { ++ struct sack_edges se; ++ enum pkt_state st; ++}; ++ ++static struct sack_r edge_a[TCP_SACK]; ++static unsigned int sack_idx; ++static unsigned int prev_len; ++ ++/* ++ * TCP lengths are stored as a rounded up number of 32 bit words. ++ * Add 3 to length round up, rounded, then divided into the ++ * length in 32 bit words. ++ */ ++#define LEN_B_TO_DW(x) ((x) >> 2) ++#define ROUND_TCPHDR_LEN(x) (LEN_B_TO_DW((x) + 3)) ++#define SHIFT_TO_TCPHDRLEN_FIELD(x) ((x) << 4) ++#define GET_TCP_HDR_LEN_IN_BYTES(x) ((x) >> 2) ++ ++/* TCP connection state */ ++static enum tcp_state current_tcp_state; ++ ++/* Current TCP RX packet handler */ ++static rxhand_tcp *tcp_packet_handler; ++ ++/** ++ * tcp_get_tcp_state() - get current TCP state ++ * ++ * Return: Current TCP state ++ */ ++enum tcp_state tcp_get_tcp_state(void) ++{ ++ return current_tcp_state; ++} ++ ++/** ++ * tcp_set_tcp_state() - set current TCP state ++ * @new_state: new TCP state ++ */ ++void tcp_set_tcp_state(enum tcp_state new_state) ++{ ++ current_tcp_state = new_state; ++} ++ ++static void dummy_handler(uchar *pkt, unsigned int dport, ++ struct in_addr sip, unsigned int sport, ++ unsigned int len) ++{ ++} ++ ++/** ++ * tcp_set_tcp_handler() - set a handler to receive data ++ * @f: handler ++ */ ++void tcp_set_tcp_handler(rxhand_tcp *f) ++{ ++ debug_cond(DEBUG_INT_STATE, "--- net_loop TCP handler set (%p)\n", f); ++ if (!f) ++ tcp_packet_handler = dummy_handler; ++ else ++ tcp_packet_handler = f; ++} ++ ++/** ++ * tcp_set_pseudo_header() - set TCP pseudo header ++ * @pkt: the packet ++ * @src: source IP address ++ * @dest: destinaion IP address ++ * @tcp_len: tcp length ++ * @pkt_len: packet length ++ * ++ * Return: the checksum of the packet ++ */ ++u16 tcp_set_pseudo_header(uchar *pkt, struct in_addr src, struct in_addr dest, ++ int tcp_len, int pkt_len) ++{ ++ union tcp_build_pkt *b = (union tcp_build_pkt *)pkt; ++ int checksum_len; ++ ++ /* ++ * Pseudo header ++ * ++ * Zero the byte after the last byte so that the header checksum ++ * will always work. ++ */ ++ pkt[pkt_len] = 0; ++ ++ net_copy_ip((void *)&b->ph.p_src, &src); ++ net_copy_ip((void *)&b->ph.p_dst, &dest); ++ b->ph.rsvd = 0; ++ b->ph.p = IPPROTO_TCP; ++ b->ph.len = htons(tcp_len); ++ checksum_len = tcp_len + PSEUDO_HDR_SIZE; ++ ++ debug_cond(DEBUG_DEV_PKT, ++ "TCP Pesudo Header (to=%pI4, from=%pI4, Len=%d)\n", ++ &b->ph.p_dst, &b->ph.p_src, checksum_len); ++ ++ return compute_ip_checksum(pkt + PSEUDO_PAD_SIZE, checksum_len); ++} ++ ++/** ++ * net_set_ack_options() - set TCP options in acknowledge packets ++ * @b: the packet ++ * ++ * Return: TCP header length ++ */ ++int net_set_ack_options(union tcp_build_pkt *b) ++{ ++ b->sack.hdr.tcp_hlen = SHIFT_TO_TCPHDRLEN_FIELD(LEN_B_TO_DW(TCP_HDR_SIZE)); ++ ++ b->sack.t_opt.kind = TCP_O_TS; ++ b->sack.t_opt.len = TCP_OPT_LEN_A; ++ b->sack.t_opt.t_snd = htons(loc_timestamp); ++ b->sack.t_opt.t_rcv = rmt_timestamp; ++ b->sack.sack_v.kind = TCP_1_NOP; ++ b->sack.sack_v.len = 0; ++ ++ if (IS_ENABLED(CONFIG_PROT_TCP_SACK)) { ++ if (tcp_lost.len > TCP_OPT_LEN_2) { ++ debug_cond(DEBUG_DEV_PKT, "TCP ack opt lost.len %x\n", ++ tcp_lost.len); ++ b->sack.sack_v.len = tcp_lost.len; ++ b->sack.sack_v.kind = TCP_V_SACK; ++ b->sack.sack_v.hill[0].l = htonl(tcp_lost.hill[0].l); ++ b->sack.sack_v.hill[0].r = htonl(tcp_lost.hill[0].r); ++ ++ /* ++ * These SACK structures are initialized with NOPs to ++ * provide TCP header alignment padding. There are 4 ++ * SACK structures used for both header padding and ++ * internally. ++ */ ++ b->sack.sack_v.hill[1].l = htonl(tcp_lost.hill[1].l); ++ b->sack.sack_v.hill[1].r = htonl(tcp_lost.hill[1].r); ++ b->sack.sack_v.hill[2].l = htonl(tcp_lost.hill[2].l); ++ b->sack.sack_v.hill[2].r = htonl(tcp_lost.hill[2].r); ++ b->sack.sack_v.hill[3].l = TCP_O_NOP; ++ b->sack.sack_v.hill[3].r = TCP_O_NOP; ++ } ++ ++ b->sack.hdr.tcp_hlen = SHIFT_TO_TCPHDRLEN_FIELD(ROUND_TCPHDR_LEN(TCP_HDR_SIZE + ++ TCP_TSOPT_SIZE + ++ tcp_lost.len)); ++ } else { ++ b->sack.sack_v.kind = 0; ++ b->sack.hdr.tcp_hlen = SHIFT_TO_TCPHDRLEN_FIELD(ROUND_TCPHDR_LEN(TCP_HDR_SIZE + ++ TCP_TSOPT_SIZE)); ++ } ++ ++ /* ++ * This returns the actual rounded up length of the ++ * TCP header to add to the total packet length ++ */ ++ ++ return GET_TCP_HDR_LEN_IN_BYTES(b->sack.hdr.tcp_hlen); ++} ++ ++/** ++ * net_set_ack_options() - set TCP options in SYN packets ++ * @b: the packet ++ */ ++void net_set_syn_options(union tcp_build_pkt *b) ++{ ++ if (IS_ENABLED(CONFIG_PROT_TCP_SACK)) ++ tcp_lost.len = 0; ++ ++ b->ip.hdr.tcp_hlen = 0xa0; ++ ++ b->ip.mss.kind = TCP_O_MSS; ++ b->ip.mss.len = TCP_OPT_LEN_4; ++ b->ip.mss.mss = htons(TCP_MSS); ++ b->ip.scale.kind = TCP_O_SCL; ++ b->ip.scale.scale = TCP_SCALE; ++ b->ip.scale.len = TCP_OPT_LEN_3; ++ if (IS_ENABLED(CONFIG_PROT_TCP_SACK)) { ++ b->ip.sack_p.kind = TCP_P_SACK; ++ b->ip.sack_p.len = TCP_OPT_LEN_2; ++ } else { ++ b->ip.sack_p.kind = TCP_1_NOP; ++ b->ip.sack_p.len = TCP_1_NOP; ++ } ++ b->ip.t_opt.kind = TCP_O_TS; ++ b->ip.t_opt.len = TCP_OPT_LEN_A; ++ loc_timestamp = get_ticks(); ++ rmt_timestamp = 0; ++ b->ip.t_opt.t_snd = 0; ++ b->ip.t_opt.t_rcv = 0; ++ b->ip.end = TCP_O_END; ++} ++ ++int tcp_set_tcp_header(uchar *pkt, int dport, int sport, int payload_len, ++ u8 action, u32 tcp_seq_num, u32 tcp_ack_num) ++{ ++ union tcp_build_pkt *b = (union tcp_build_pkt *)pkt; ++ int pkt_hdr_len; ++ int pkt_len; ++ int tcp_len; ++ ++ /* ++ * Header: 5 32 bit words. 4 bits TCP header Length, ++ * 4 bits reserved options ++ */ ++ b->ip.hdr.tcp_flags = action; ++ pkt_hdr_len = IP_TCP_HDR_SIZE; ++ b->ip.hdr.tcp_hlen = SHIFT_TO_TCPHDRLEN_FIELD(LEN_B_TO_DW(TCP_HDR_SIZE)); ++ ++ switch (action) { ++ case TCP_SYN: ++ debug_cond(DEBUG_DEV_PKT, ++ "TCP Hdr:SYN (%pI4, %pI4, sq=%d, ak=%d)\n", ++ &net_server_ip, &net_ip, ++ tcp_seq_num, tcp_ack_num); ++ tcp_activity_count = 0; ++ net_set_syn_options(b); ++ tcp_seq_num = 0; ++ tcp_ack_num = 0; ++ pkt_hdr_len = IP_TCP_O_SIZE; ++ if (current_tcp_state == TCP_SYN_SENT) { /* Too many SYNs */ ++ action = TCP_FIN; ++ current_tcp_state = TCP_FIN_WAIT_1; ++ } else { ++ current_tcp_state = TCP_SYN_SENT; ++ } ++ break; ++ case TCP_ACK: ++ pkt_hdr_len = IP_HDR_SIZE + net_set_ack_options(b); ++ b->ip.hdr.tcp_flags = action; ++ debug_cond(DEBUG_DEV_PKT, ++ "TCP Hdr:ACK (%pI4, %pI4, s=%d, a=%d, A=%x)\n", ++ &net_server_ip, &net_ip, tcp_seq_num, tcp_ack_num, ++ action); ++ break; ++ case TCP_FIN: ++ debug_cond(DEBUG_DEV_PKT, ++ "TCP Hdr:FIN (%pI4, %pI4, s=%d, a=%d)\n", ++ &net_server_ip, &net_ip, tcp_seq_num, tcp_ack_num); ++ payload_len = 0; ++ pkt_hdr_len = IP_TCP_HDR_SIZE; ++ current_tcp_state = TCP_FIN_WAIT_1; ++ break; ++ ++ /* Notify connection closing */ ++ ++ case (TCP_FIN | TCP_ACK): ++ case (TCP_FIN | TCP_ACK | TCP_PUSH): ++ if (current_tcp_state == TCP_CLOSE_WAIT) ++ current_tcp_state = TCP_CLOSING; ++ ++ tcp_ack_edge++; ++ debug_cond(DEBUG_DEV_PKT, ++ "TCP Hdr:FIN ACK PSH(%pI4, %pI4, s=%d, a=%d, A=%x)\n", ++ &net_server_ip, &net_ip, ++ tcp_seq_num, tcp_ack_edge, action); ++ fallthrough; ++ default: ++ pkt_hdr_len = IP_HDR_SIZE + net_set_ack_options(b); ++ b->ip.hdr.tcp_flags = action | TCP_PUSH | TCP_ACK; ++ debug_cond(DEBUG_DEV_PKT, ++ "TCP Hdr:dft (%pI4, %pI4, s=%d, a=%d, A=%x)\n", ++ &net_server_ip, &net_ip, ++ tcp_seq_num, tcp_ack_num, action); ++ } ++ ++ pkt_len = pkt_hdr_len + payload_len; ++ tcp_len = pkt_len - IP_HDR_SIZE; ++ ++ /* TCP Header */ ++ b->ip.hdr.tcp_ack = htonl(tcp_ack_edge); ++ b->ip.hdr.tcp_src = htons(sport); ++ b->ip.hdr.tcp_dst = htons(dport); ++ b->ip.hdr.tcp_seq = htonl(tcp_seq_num); ++ tcp_seq_num = tcp_seq_num + payload_len; ++ ++ /* ++ * TCP window size - TCP header variable tcp_win. ++ * Change tcp_win only if you have an understanding of network ++ * overrun, congestion, TCP segment sizes, TCP windows, TCP scale, ++ * queuing theory and packet buffering. If there are too few buffers, ++ * there will be data loss, recovery may work or the sending TCP, ++ * the server, could abort the stream transmission. ++ * MSS is governed by maximum Ethernet frame length. ++ * The number of buffers is governed by the desire to have a queue of ++ * full buffers to be processed at the destination to maximize ++ * throughput. Temporary memory use for the boot phase on modern ++ * SOCs is may not be considered a constraint to buffer space, if ++ * it is, then the u-boot tftp or nfs kernel netboot should be ++ * considered. ++ */ ++ b->ip.hdr.tcp_win = htons(PKTBUFSRX * TCP_MSS >> TCP_SCALE); ++ ++ b->ip.hdr.tcp_xsum = 0; ++ b->ip.hdr.tcp_ugr = 0; ++ ++ b->ip.hdr.tcp_xsum = tcp_set_pseudo_header(pkt, net_ip, net_server_ip, ++ tcp_len, pkt_len); ++ ++ net_set_ip_header((uchar *)&b->ip, net_server_ip, net_ip, ++ pkt_len, IPPROTO_TCP); ++ ++ return pkt_hdr_len; ++} ++ ++/** ++ * tcp_hole() - Selective Acknowledgment (Essential for fast stream transfer) ++ * @tcp_seq_num: TCP sequence start number ++ * @len: the length of sequence numbers ++ * @tcp_seq_max: maximum of sequence numbers ++ */ ++void tcp_hole(u32 tcp_seq_num, u32 len, u32 tcp_seq_max) ++{ ++ u32 idx_sack, sack_in; ++ u32 sack_end = TCP_SACK - 1; ++ u32 hill = 0; ++ enum pkt_state expect = PKT; ++ u32 seq = tcp_seq_num - tcp_seq_init; ++ u32 hol_l = tcp_ack_edge - tcp_seq_init; ++ u32 hol_r = 0; ++ ++ /* Place new seq number in correct place in receive array */ ++ if (prev_len == 0) ++ prev_len = len; ++ ++ idx_sack = sack_idx + ((tcp_seq_num - tcp_ack_edge) / prev_len); ++ if (idx_sack < TCP_SACK) { ++ edge_a[idx_sack].se.l = tcp_seq_num; ++ edge_a[idx_sack].se.r = tcp_seq_num + len; ++ edge_a[idx_sack].st = PKT; ++ ++ /* ++ * The fin (last) packet is not the same length as data ++ * packets, and if it's length is recorded and used for ++ * array index calculation, calculation breaks. ++ */ ++ if (prev_len < len) ++ prev_len = len; ++ } ++ ++ debug_cond(DEBUG_DEV_PKT, ++ "TCP 1 seq %d, edg %d, len %d, sack_idx %d, sack_end %d\n", ++ seq, hol_l, len, sack_idx, sack_end); ++ ++ /* Right edge of contiguous stream, is the left edge of first hill */ ++ hol_l = tcp_seq_num - tcp_seq_init; ++ hol_r = hol_l + len; ++ ++ if (IS_ENABLED(CONFIG_PROT_TCP_SACK)) ++ tcp_lost.len = TCP_OPT_LEN_2; ++ ++ debug_cond(DEBUG_DEV_PKT, ++ "TCP 1 in %d, seq %d, pkt_l %d, pkt_r %d, sack_idx %d, sack_end %d\n", ++ idx_sack, seq, hol_l, hol_r, sack_idx, sack_end); ++ ++ for (sack_in = sack_idx; sack_in < sack_end && hill < TCP_SACK_HILLS; ++ sack_in++) { ++ switch (expect) { ++ case NOPKT: ++ switch (edge_a[sack_in].st) { ++ case NOPKT: ++ debug_cond(DEBUG_INT_STATE, "N"); ++ break; ++ case PKT: ++ debug_cond(DEBUG_INT_STATE, "n"); ++ if (IS_ENABLED(CONFIG_PROT_TCP_SACK)) { ++ tcp_lost.hill[hill].l = ++ edge_a[sack_in].se.l; ++ tcp_lost.hill[hill].r = ++ edge_a[sack_in].se.r; ++ } ++ expect = PKT; ++ break; ++ } ++ break; ++ case PKT: ++ switch (edge_a[sack_in].st) { ++ case NOPKT: ++ debug_cond(DEBUG_INT_STATE, "p"); ++ if (sack_in > sack_idx && ++ hill < TCP_SACK_HILLS) { ++ hill++; ++ if (IS_ENABLED(CONFIG_PROT_TCP_SACK)) ++ tcp_lost.len += TCP_OPT_LEN_8; ++ } ++ expect = NOPKT; ++ break; ++ case PKT: ++ debug_cond(DEBUG_INT_STATE, "P"); ++ ++ if (tcp_ack_edge == edge_a[sack_in].se.l) { ++ tcp_ack_edge = edge_a[sack_in].se.r; ++ edge_a[sack_in].st = NOPKT; ++ sack_idx++; ++ } else { ++ if (IS_ENABLED(CONFIG_PROT_TCP_SACK) && ++ hill < TCP_SACK_HILLS) ++ tcp_lost.hill[hill].r = ++ edge_a[sack_in].se.r; ++ if (IS_ENABLED(CONFIG_PROT_TCP_SACK) && ++ sack_in == sack_end - 1) ++ tcp_lost.hill[hill].r = ++ edge_a[sack_in].se.r; ++ } ++ break; ++ } ++ break; ++ } ++ } ++ debug_cond(DEBUG_INT_STATE, "\n"); ++ if (!IS_ENABLED(CONFIG_PROT_TCP_SACK) || tcp_lost.len <= TCP_OPT_LEN_2) ++ sack_idx = 0; ++} ++ ++/** ++ * tcp_parse_options() - parsing TCP options ++ * @o: pointer to the option field. ++ * @o_len: length of the option field. ++ */ ++void tcp_parse_options(uchar *o, int o_len) ++{ ++ struct tcp_t_opt *tsopt; ++ uchar *p = o; ++ ++ /* ++ * NOPs are options with a zero length, and thus are special. ++ * All other options have length fields. ++ */ ++ for (p = o; p < (o + o_len); p = p + p[1]) { ++ if (!p[1]) ++ return; /* Finished processing options */ ++ ++ switch (p[0]) { ++ case TCP_O_END: ++ return; ++ case TCP_O_MSS: ++ case TCP_O_SCL: ++ case TCP_P_SACK: ++ case TCP_V_SACK: ++ break; ++ case TCP_O_TS: ++ tsopt = (struct tcp_t_opt *)p; ++ rmt_timestamp = tsopt->t_snd; ++ return; ++ } ++ ++ /* Process optional NOPs */ ++ if (p[0] == TCP_O_NOP) ++ p++; ++ } ++} ++ ++static u8 tcp_state_machine(u8 tcp_flags, u32 *tcp_seq_num, int payload_len) ++{ ++ u8 tcp_fin = tcp_flags & TCP_FIN; ++ u8 tcp_syn = tcp_flags & TCP_SYN; ++ u8 tcp_rst = tcp_flags & TCP_RST; ++ u8 tcp_push = tcp_flags & TCP_PUSH; ++ u8 tcp_ack = tcp_flags & TCP_ACK; ++ u8 action = TCP_DATA; ++ int i; ++ ++ /* ++ * tcp_flags are examined to determine TX action in a given state ++ * tcp_push is interpreted to mean "inform the app" ++ * urg, ece, cer and nonce flags are not supported. ++ * ++ * exe and crw are use to signal and confirm knowledge of congestion. ++ * This TCP only sends a file request and acks. If it generates ++ * congestion, the network is broken. ++ */ ++ debug_cond(DEBUG_INT_STATE, "TCP STATE ENTRY %x\n", action); ++ if (tcp_rst) { ++ action = TCP_DATA; ++ current_tcp_state = TCP_CLOSED; ++ net_set_state(NETLOOP_FAIL); ++ debug_cond(DEBUG_INT_STATE, "TCP Reset %x\n", tcp_flags); ++ return TCP_RST; ++ } ++ ++ switch (current_tcp_state) { ++ case TCP_CLOSED: ++ debug_cond(DEBUG_INT_STATE, "TCP CLOSED %x\n", tcp_flags); ++ if (tcp_ack) ++ action = TCP_DATA; ++ else if (tcp_syn) ++ action = TCP_RST; ++ else if (tcp_fin) ++ action = TCP_DATA; ++ break; ++ case TCP_SYN_SENT: ++ debug_cond(DEBUG_INT_STATE, "TCP_SYN_SENT %x, %d\n", ++ tcp_flags, *tcp_seq_num); ++ if (tcp_fin) { ++ action = action | TCP_PUSH; ++ current_tcp_state = TCP_CLOSE_WAIT; ++ } ++ if (tcp_syn) { ++ action = action | TCP_ACK | TCP_PUSH; ++ if (tcp_ack) { ++ tcp_seq_init = *tcp_seq_num; ++ *tcp_seq_num = *tcp_seq_num + 1; ++ tcp_seq_max = *tcp_seq_num; ++ tcp_ack_edge = *tcp_seq_num; ++ sack_idx = 0; ++ edge_a[sack_idx].se.l = *tcp_seq_num; ++ edge_a[sack_idx].se.r = *tcp_seq_num; ++ prev_len = 0; ++ current_tcp_state = TCP_ESTABLISHED; ++ for (i = 0; i < TCP_SACK; i++) ++ edge_a[i].st = NOPKT; ++ } ++ } else if (tcp_ack) { ++ action = TCP_DATA; ++ } ++ ++ break; ++ case TCP_ESTABLISHED: ++ debug_cond(DEBUG_INT_STATE, "TCP_ESTABLISHED %x\n", tcp_flags); ++ if (*tcp_seq_num > tcp_seq_max) ++ tcp_seq_max = *tcp_seq_num; ++ if (payload_len > 0) { ++ tcp_hole(*tcp_seq_num, payload_len, tcp_seq_max); ++ tcp_fin = TCP_DATA; /* cause standalone FIN */ ++ } ++ ++ if ((tcp_fin) && ++ (!IS_ENABLED(CONFIG_PROT_TCP_SACK) || ++ tcp_lost.len <= TCP_OPT_LEN_2)) { ++ action = action | TCP_FIN | TCP_PUSH | TCP_ACK; ++ current_tcp_state = TCP_CLOSE_WAIT; ++ } else if (tcp_ack) { ++ action = TCP_DATA; ++ } ++ ++ if (tcp_syn) ++ action = TCP_ACK + TCP_RST; ++ else if (tcp_push) ++ action = action | TCP_PUSH; ++ break; ++ case TCP_CLOSE_WAIT: ++ debug_cond(DEBUG_INT_STATE, "TCP_CLOSE_WAIT (%x)\n", tcp_flags); ++ action = TCP_DATA; ++ break; ++ case TCP_FIN_WAIT_2: ++ debug_cond(DEBUG_INT_STATE, "TCP_FIN_WAIT_2 (%x)\n", tcp_flags); ++ if (tcp_ack) { ++ action = TCP_PUSH | TCP_ACK; ++ current_tcp_state = TCP_CLOSED; ++ puts("\n"); ++ } else if (tcp_syn) { ++ action = TCP_DATA; ++ } else if (tcp_fin) { ++ action = TCP_DATA; ++ } ++ break; ++ case TCP_FIN_WAIT_1: ++ debug_cond(DEBUG_INT_STATE, "TCP_FIN_WAIT_1 (%x)\n", tcp_flags); ++ if (tcp_fin) { ++ action = TCP_ACK | TCP_FIN; ++ current_tcp_state = TCP_FIN_WAIT_2; ++ } ++ if (tcp_syn) ++ action = TCP_RST; ++ if (tcp_ack) { ++ current_tcp_state = TCP_CLOSED; ++ tcp_seq_num = tcp_seq_num + 1; ++ } ++ break; ++ case TCP_CLOSING: ++ debug_cond(DEBUG_INT_STATE, "TCP_CLOSING (%x)\n", tcp_flags); ++ if (tcp_ack) { ++ action = TCP_PUSH; ++ current_tcp_state = TCP_CLOSED; ++ puts("\n"); ++ } else if (tcp_syn) { ++ action = TCP_RST; ++ } else if (tcp_fin) { ++ action = TCP_DATA; ++ } ++ break; ++ } ++ return action; ++} ++ ++/** ++ * rxhand_tcp_f() - process receiving data and call data handler. ++ * @b: the packet ++ * @pkt_len: the length of packet. ++ */ ++void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int pkt_len) ++{ ++ int tcp_len = pkt_len - IP_HDR_SIZE; ++ u16 tcp_rx_xsum = b->ip.hdr.ip_sum; ++ u8 tcp_action = TCP_DATA; ++ u32 tcp_seq_num, tcp_ack_num; ++ struct in_addr action_and_state; ++ int tcp_hdr_len, payload_len; ++ ++ /* Verify IP header */ ++ debug_cond(DEBUG_DEV_PKT, ++ "TCP RX in RX Sum (to=%pI4, from=%pI4, len=%d)\n", ++ &b->ip.hdr.ip_src, &b->ip.hdr.ip_dst, pkt_len); ++ ++ b->ip.hdr.ip_src = net_server_ip; ++ b->ip.hdr.ip_dst = net_ip; ++ b->ip.hdr.ip_sum = 0; ++ if (tcp_rx_xsum != compute_ip_checksum(b, IP_HDR_SIZE)) { ++ debug_cond(DEBUG_DEV_PKT, ++ "TCP RX IP xSum Error (%pI4, =%pI4, len=%d)\n", ++ &net_ip, &net_server_ip, pkt_len); ++ return; ++ } ++ ++ /* Build pseudo header and verify TCP header */ ++ tcp_rx_xsum = b->ip.hdr.tcp_xsum; ++ b->ip.hdr.tcp_xsum = 0; ++ if (tcp_rx_xsum != tcp_set_pseudo_header((uchar *)b, b->ip.hdr.ip_src, ++ b->ip.hdr.ip_dst, tcp_len, ++ pkt_len)) { ++ debug_cond(DEBUG_DEV_PKT, ++ "TCP RX TCP xSum Error (%pI4, %pI4, len=%d)\n", ++ &net_ip, &net_server_ip, tcp_len); ++ return; ++ } ++ ++ tcp_hdr_len = GET_TCP_HDR_LEN_IN_BYTES(b->ip.hdr.tcp_hlen); ++ payload_len = tcp_len - tcp_hdr_len; ++ ++ if (tcp_hdr_len > TCP_HDR_SIZE) ++ tcp_parse_options((uchar *)b + IP_TCP_HDR_SIZE, ++ tcp_hdr_len - TCP_HDR_SIZE); ++ /* ++ * Incoming sequence and ack numbers are server's view of the numbers. ++ * The app must swap the numbers when responding. ++ */ ++ tcp_seq_num = ntohl(b->ip.hdr.tcp_seq); ++ tcp_ack_num = ntohl(b->ip.hdr.tcp_ack); ++ ++ /* Packets are not ordered. Send to app as received. */ ++ tcp_action = tcp_state_machine(b->ip.hdr.tcp_flags, ++ &tcp_seq_num, payload_len); ++ ++ tcp_activity_count++; ++ if (tcp_activity_count > TCP_ACTIVITY) { ++ puts("| "); ++ tcp_activity_count = 0; ++ } ++ ++ if ((tcp_action & TCP_PUSH) || payload_len > 0) { ++ debug_cond(DEBUG_DEV_PKT, ++ "TCP Notify (action=%x, Seq=%d,Ack=%d,Pay%d)\n", ++ tcp_action, tcp_seq_num, tcp_ack_num, payload_len); ++ ++ action_and_state.s_addr = tcp_action; ++ (*tcp_packet_handler) ((uchar *)b + pkt_len - payload_len, ++ tcp_seq_num, action_and_state, ++ tcp_ack_num, payload_len); ++ ++ } else if (tcp_action != TCP_DATA) { ++ debug_cond(DEBUG_DEV_PKT, ++ "TCP Action (action=%x,Seq=%d,Ack=%d,Pay=%d)\n", ++ tcp_action, tcp_seq_num, tcp_ack_num, payload_len); ++ ++ /* ++ * Warning: Incoming Ack & Seq sequence numbers are transposed ++ * here to outgoing Seq & Ack sequence numbers ++ */ ++ net_send_tcp_packet(0, ntohs(b->ip.hdr.tcp_src), ++ ntohs(b->ip.hdr.tcp_dst), ++ (tcp_action & (~TCP_PUSH)), ++ tcp_seq_num, tcp_ack_num); ++ } ++} +-- +2.45.2 + + +From 6a1f189424b6435be0e14ecbfcfd7dd8bc3f4a37 Mon Sep 17 00:00:00 2001 +From: "Ying-Chun Liu (PaulLiu)" +Date: Tue, 8 Nov 2022 14:17:29 +0800 +Subject: [PATCH 2/2] net: Add wget application + +This commit adds a simple wget command that can download files +from http server. + +The command syntax is +wget ${loadaddr} + +Signed-off-by: Duncan Hare +Signed-off-by: Ying-Chun Liu (PaulLiu) +Reviewed-by: Simon Glass +Cc: Christian Gmeiner +Cc: Joe Hershberger +Cc: Michal Simek +Cc: Ramon Fried +Reviewed-by: Ramon Fried +--- + cmd/Kconfig | 7 + + cmd/net.c | 13 ++ + include/net.h | 2 +- + include/net/wget.h | 22 +++ + net/Makefile | 1 + + net/net.c | 6 + + net/wget.c | 438 +++++++++++++++++++++++++++++++++++++++++++++ + 7 files changed, 488 insertions(+), 1 deletion(-) + create mode 100644 include/net/wget.h + create mode 100644 net/wget.c + +diff --git a/cmd/Kconfig b/cmd/Kconfig +index aafd5cccc3..11cef1ae37 100644 +--- a/cmd/Kconfig ++++ b/cmd/Kconfig +@@ -1587,6 +1587,13 @@ config CMD_NFS + help + Boot image via network using NFS protocol. + ++config CMD_WGET ++ bool "wget" ++ select TCP ++ help ++ wget is a simple command to download kernel, or other files, ++ from a http server over TCP. ++ + config CMD_MII + bool "mii" + imply CMD_MDIO +diff --git a/cmd/net.c b/cmd/net.c +index 651c1411f4..9a97bd3908 100644 +--- a/cmd/net.c ++++ b/cmd/net.c +@@ -124,6 +124,19 @@ U_BOOT_CMD( + ); + #endif + ++#if defined(CONFIG_CMD_WGET) ++static int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ return netboot_common(WGET, cmdtp, argc, argv); ++} ++ ++U_BOOT_CMD( ++ wget, 3, 1, do_wget, ++ "boot image via network using HTTP protocol", ++ "[loadAddress] [[hostIPaddr:]path and image name]" ++); ++#endif ++ + static void netboot_update_env(void) + { + char tmp[22]; +diff --git a/include/net.h b/include/net.h +index 859ebae04b..2d330fd78b 100644 +--- a/include/net.h ++++ b/include/net.h +@@ -565,7 +565,7 @@ extern int net_restart_wrap; /* Tried all network devices */ + + enum proto_t { + BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP, +- TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP ++ TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP, WGET + }; + + extern char net_boot_file_name[1024];/* Boot File name */ +diff --git a/include/net/wget.h b/include/net/wget.h +new file mode 100644 +index 0000000000..da0920de11 +--- /dev/null ++++ b/include/net/wget.h +@@ -0,0 +1,22 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Duncan Hare Copyright 2017 ++ */ ++ ++/** ++ * wget_start() - begin wget ++ */ ++void wget_start(void); ++ ++enum wget_state { ++ WGET_CLOSED, ++ WGET_CONNECTING, ++ WGET_CONNECTED, ++ WGET_TRANSFERRING, ++ WGET_TRANSFERRED ++}; ++ ++#define DEBUG_WGET 0 /* Set to 1 for debug messages */ ++#define SERVER_PORT 80 ++#define WGET_RETRY_COUNT 30 ++#define WGET_TIMEOUT 2000UL +diff --git a/net/Makefile b/net/Makefile +index f68ad94767..54ef337e80 100644 +--- a/net/Makefile ++++ b/net/Makefile +@@ -30,6 +30,7 @@ obj-$(CONFIG_UDP_FUNCTION_FASTBOOT) += fastboot.o + obj-$(CONFIG_CMD_WOL) += wol.o + obj-$(CONFIG_PROT_UDP) += udp.o + obj-$(CONFIG_PROT_TCP) += tcp.o ++obj-$(CONFIG_CMD_WGET) += wget.o + + # Disable this warning as it is triggered by: + # sprintf(buf, index ? "foo%d" : "foo", index) +diff --git a/net/net.c b/net/net.c +index 5f11dcac84..38cda2e47f 100644 +--- a/net/net.c ++++ b/net/net.c +@@ -117,6 +117,7 @@ + #include "wol.h" + #endif + #include ++#include + + /** BOOTP EXTENTIONS **/ + +@@ -505,6 +506,11 @@ restart: + nfs_start(); + break; + #endif ++#if defined(CONFIG_CMD_WGET) ++ case WGET: ++ wget_start(); ++ break; ++#endif + #if defined(CONFIG_CMD_CDP) + case CDP: + cdp_start(); +diff --git a/net/wget.c b/net/wget.c +new file mode 100644 +index 0000000000..3826c4b364 +--- /dev/null ++++ b/net/wget.c +@@ -0,0 +1,438 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * WGET/HTTP support driver based on U-BOOT's nfs.c ++ * Copyright Duncan Hare 2017 ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static const char bootfile1[] = "GET "; ++static const char bootfile3[] = " HTTP/1.0\r\n\r\n"; ++static const char http_eom[] = "\r\n\r\n"; ++static const char http_ok[] = "200"; ++static const char content_len[] = "Content-Length"; ++static const char linefeed[] = "\r\n"; ++static struct in_addr web_server_ip; ++static int our_port; ++static int wget_timeout_count; ++ ++struct pkt_qd { ++ uchar *pkt; ++ unsigned int tcp_seq_num; ++ unsigned int len; ++}; ++ ++/* ++ * This is a control structure for out of order packets received. ++ * The actual packet bufers are in the kernel space, and are ++ * expected to be overwritten by the downloaded image. ++ */ ++static struct pkt_qd pkt_q[PKTBUFSRX / 4]; ++static int pkt_q_idx; ++static unsigned long content_length; ++static unsigned int packets; ++ ++static unsigned int initial_data_seq_num; ++ ++static enum wget_state current_wget_state; ++ ++static char *image_url; ++static unsigned int wget_timeout = WGET_TIMEOUT; ++ ++static enum net_loop_state wget_loop_state; ++ ++/* Timeout retry parameters */ ++static u8 retry_action; /* actions for TCP retry */ ++static unsigned int retry_tcp_ack_num; /* TCP retry acknowledge number*/ ++static unsigned int retry_tcp_seq_num; /* TCP retry sequence number */ ++static int retry_len; /* TCP retry length */ ++ ++/** ++ * store_block() - store block in memory ++ * @src: source of data ++ * @offset: offset ++ * @len: length ++ */ ++static inline int store_block(uchar *src, unsigned int offset, unsigned int len) ++{ ++ ulong newsize = offset + len; ++ uchar *ptr; ++ ++ ptr = map_sysmem(image_load_addr + offset, len); ++ memcpy(ptr, src, len); ++ unmap_sysmem(ptr); ++ ++ if (net_boot_file_size < (offset + len)) ++ net_boot_file_size = newsize; ++ ++ return 0; ++} ++ ++/** ++ * wget_send_stored() - wget response dispatcher ++ * ++ * WARNING, This, and only this, is the place in wget.c where ++ * SEQUENCE NUMBERS are swapped between incoming (RX) ++ * and outgoing (TX). ++ * Procedure wget_handler() is correct for RX traffic. ++ */ ++static void wget_send_stored(void) ++{ ++ u8 action = retry_action; ++ int len = retry_len; ++ unsigned int tcp_ack_num = retry_tcp_ack_num + len; ++ unsigned int tcp_seq_num = retry_tcp_seq_num; ++ uchar *ptr, *offset; ++ ++ switch (current_wget_state) { ++ case WGET_CLOSED: ++ debug_cond(DEBUG_WGET, "wget: send SYN\n"); ++ current_wget_state = WGET_CONNECTING; ++ net_send_tcp_packet(0, SERVER_PORT, our_port, action, ++ tcp_seq_num, tcp_ack_num); ++ packets = 0; ++ break; ++ case WGET_CONNECTING: ++ pkt_q_idx = 0; ++ net_send_tcp_packet(0, SERVER_PORT, our_port, action, ++ tcp_seq_num, tcp_ack_num); ++ ++ ptr = net_tx_packet + net_eth_hdr_size() + ++ IP_TCP_HDR_SIZE + TCP_TSOPT_SIZE + 2; ++ offset = ptr; ++ ++ memcpy(offset, &bootfile1, strlen(bootfile1)); ++ offset += strlen(bootfile1); ++ ++ memcpy(offset, image_url, strlen(image_url)); ++ offset += strlen(image_url); ++ ++ memcpy(offset, &bootfile3, strlen(bootfile3)); ++ offset += strlen(bootfile3); ++ net_send_tcp_packet((offset - ptr), SERVER_PORT, our_port, ++ TCP_PUSH, tcp_seq_num, tcp_ack_num); ++ current_wget_state = WGET_CONNECTED; ++ break; ++ case WGET_CONNECTED: ++ case WGET_TRANSFERRING: ++ case WGET_TRANSFERRED: ++ net_send_tcp_packet(0, SERVER_PORT, our_port, action, ++ tcp_seq_num, tcp_ack_num); ++ break; ++ } ++} ++ ++static void wget_send(u8 action, unsigned int tcp_ack_num, ++ unsigned int tcp_seq_num, int len) ++{ ++ retry_action = action; ++ retry_tcp_ack_num = tcp_ack_num; ++ retry_tcp_seq_num = tcp_seq_num; ++ retry_len = len; ++ ++ wget_send_stored(); ++} ++ ++void wget_fail(char *error_message, unsigned int tcp_seq_num, ++ unsigned int tcp_ack_num, u8 action) ++{ ++ printf("wget: Transfer Fail - %s\n", error_message); ++ net_set_timeout_handler(0, NULL); ++ wget_send(action, tcp_seq_num, tcp_ack_num, 0); ++} ++ ++void wget_success(u8 action, unsigned int tcp_seq_num, ++ unsigned int tcp_ack_num, int len, int packets) ++{ ++ printf("Packets received %d, Transfer Successful\n", packets); ++ wget_send(action, tcp_seq_num, tcp_ack_num, len); ++} ++ ++/* ++ * Interfaces of U-BOOT ++ */ ++static void wget_timeout_handler(void) ++{ ++ if (++wget_timeout_count > WGET_RETRY_COUNT) { ++ puts("\nRetry count exceeded; starting again\n"); ++ wget_send(TCP_RST, 0, 0, 0); ++ net_start_again(); ++ } else { ++ puts("T "); ++ net_set_timeout_handler(wget_timeout + ++ WGET_TIMEOUT * wget_timeout_count, ++ wget_timeout_handler); ++ wget_send_stored(); ++ } ++} ++ ++#define PKT_QUEUE_OFFSET 0x20000 ++#define PKT_QUEUE_PACKET_SIZE 0x800 ++ ++static void wget_connected(uchar *pkt, unsigned int tcp_seq_num, ++ struct in_addr action_and_state, ++ unsigned int tcp_ack_num, unsigned int len) ++{ ++ u8 action = action_and_state.s_addr; ++ uchar *pkt_in_q; ++ char *pos; ++ int hlen, i; ++ uchar *ptr1; ++ ++ pkt[len] = '\0'; ++ pos = strstr((char *)pkt, http_eom); ++ ++ if (!pos) { ++ debug_cond(DEBUG_WGET, ++ "wget: Connected, data before Header %p\n", pkt); ++ pkt_in_q = (void *)image_load_addr + PKT_QUEUE_OFFSET + ++ (pkt_q_idx * PKT_QUEUE_PACKET_SIZE); ++ ++ ptr1 = map_sysmem((phys_addr_t)pkt_in_q, len); ++ memcpy(ptr1, pkt, len); ++ unmap_sysmem(ptr1); ++ ++ pkt_q[pkt_q_idx].pkt = pkt_in_q; ++ pkt_q[pkt_q_idx].tcp_seq_num = tcp_seq_num; ++ pkt_q[pkt_q_idx].len = len; ++ pkt_q_idx++; ++ } else { ++ debug_cond(DEBUG_WGET, "wget: Connected HTTP Header %p\n", pkt); ++ /* sizeof(http_eom) - 1 is the string length of (http_eom) */ ++ hlen = pos - (char *)pkt + sizeof(http_eom) - 1; ++ pos = strstr((char *)pkt, linefeed); ++ if (pos > 0) ++ i = pos - (char *)pkt; ++ else ++ i = hlen; ++ printf("%.*s", i, pkt); ++ ++ current_wget_state = WGET_TRANSFERRING; ++ ++ if (strstr((char *)pkt, http_ok) == 0) { ++ debug_cond(DEBUG_WGET, ++ "wget: Connected Bad Xfer\n"); ++ initial_data_seq_num = tcp_seq_num + hlen; ++ wget_loop_state = NETLOOP_FAIL; ++ wget_send(action, tcp_seq_num, tcp_ack_num, len); ++ } else { ++ debug_cond(DEBUG_WGET, ++ "wget: Connctd pkt %p hlen %x\n", ++ pkt, hlen); ++ initial_data_seq_num = tcp_seq_num + hlen; ++ ++ pos = strstr((char *)pkt, content_len); ++ if (!pos) { ++ content_length = -1; ++ } else { ++ pos += sizeof(content_len) + 2; ++ strict_strtoul(pos, 10, &content_length); ++ debug_cond(DEBUG_WGET, ++ "wget: Connected Len %lu\n", ++ content_length); ++ } ++ ++ net_boot_file_size = 0; ++ ++ if (len > hlen) ++ store_block(pkt + hlen, 0, len - hlen); ++ ++ debug_cond(DEBUG_WGET, ++ "wget: Connected Pkt %p hlen %x\n", ++ pkt, hlen); ++ ++ for (i = 0; i < pkt_q_idx; i++) { ++ ptr1 = map_sysmem( ++ (phys_addr_t)(pkt_q[i].pkt), ++ pkt_q[i].len); ++ store_block(ptr1, ++ pkt_q[i].tcp_seq_num - ++ initial_data_seq_num, ++ pkt_q[i].len); ++ unmap_sysmem(ptr1); ++ debug_cond(DEBUG_WGET, ++ "wget: Connctd pkt Q %p len %x\n", ++ pkt_q[i].pkt, pkt_q[i].len); ++ } ++ } ++ } ++ wget_send(action, tcp_seq_num, tcp_ack_num, len); ++} ++ ++/** ++ * wget_handler() - handler of wget ++ * @pkt: the pointer to the payload ++ * @tcp_seq_num: tcp sequence number ++ * @action_and_state: TCP state ++ * @tcp_ack_num: tcp acknowledge number ++ * @len: length of the payload ++ * ++ * In the "application push" invocation, the TCP header with all ++ * its information is pointed to by the packet pointer. ++ */ ++static void wget_handler(uchar *pkt, unsigned int tcp_seq_num, ++ struct in_addr action_and_state, ++ unsigned int tcp_ack_num, unsigned int len) ++{ ++ enum tcp_state wget_tcp_state = tcp_get_tcp_state(); ++ u8 action = action_and_state.s_addr; ++ ++ net_set_timeout_handler(wget_timeout, wget_timeout_handler); ++ packets++; ++ ++ switch (current_wget_state) { ++ case WGET_CLOSED: ++ debug_cond(DEBUG_WGET, "wget: Handler: Error!, State wrong\n"); ++ break; ++ case WGET_CONNECTING: ++ debug_cond(DEBUG_WGET, ++ "wget: Connecting In len=%x, Seq=%x, Ack=%x\n", ++ len, tcp_seq_num, tcp_ack_num); ++ if (!len) { ++ if (wget_tcp_state == TCP_ESTABLISHED) { ++ debug_cond(DEBUG_WGET, ++ "wget: Cting, send, len=%x\n", len); ++ wget_send(action, tcp_seq_num, tcp_ack_num, ++ len); ++ } else { ++ printf("%.*s", len, pkt); ++ wget_fail("wget: Handler Connected Fail\n", ++ tcp_seq_num, tcp_ack_num, action); ++ } ++ } ++ break; ++ case WGET_CONNECTED: ++ debug_cond(DEBUG_WGET, "wget: Connected seq=%x, len=%x\n", ++ tcp_seq_num, len); ++ if (!len) { ++ wget_fail("Image not found, no data returned\n", ++ tcp_seq_num, tcp_ack_num, action); ++ } else { ++ wget_connected(pkt, tcp_seq_num, action_and_state, ++ tcp_ack_num, len); ++ } ++ break; ++ case WGET_TRANSFERRING: ++ debug_cond(DEBUG_WGET, ++ "wget: Transferring, seq=%x, ack=%x,len=%x\n", ++ tcp_seq_num, tcp_ack_num, len); ++ ++ if (tcp_seq_num >= initial_data_seq_num && ++ store_block(pkt, tcp_seq_num - initial_data_seq_num, ++ len) != 0) { ++ wget_fail("wget: store error\n", ++ tcp_seq_num, tcp_ack_num, action); ++ return; ++ } ++ ++ switch (wget_tcp_state) { ++ case TCP_FIN_WAIT_2: ++ wget_send(TCP_ACK, tcp_seq_num, tcp_ack_num, len); ++ fallthrough; ++ case TCP_SYN_SENT: ++ case TCP_CLOSING: ++ case TCP_FIN_WAIT_1: ++ case TCP_CLOSED: ++ net_set_state(NETLOOP_FAIL); ++ break; ++ case TCP_ESTABLISHED: ++ wget_send(TCP_ACK, tcp_seq_num, tcp_ack_num, ++ len); ++ wget_loop_state = NETLOOP_SUCCESS; ++ break; ++ case TCP_CLOSE_WAIT: /* End of transfer */ ++ current_wget_state = WGET_TRANSFERRED; ++ wget_send(action | TCP_ACK | TCP_FIN, ++ tcp_seq_num, tcp_ack_num, len); ++ break; ++ } ++ break; ++ case WGET_TRANSFERRED: ++ printf("Packets received %d, Transfer Successful\n", packets); ++ net_set_state(wget_loop_state); ++ break; ++ } ++} ++ ++#define RANDOM_PORT_START 1024 ++#define RANDOM_PORT_RANGE 0x4000 ++ ++/** ++ * random_port() - make port a little random (1024-17407) ++ * ++ * Return: random port number from 1024 to 17407 ++ * ++ * This keeps the math somewhat trivial to compute, and seems to work with ++ * all supported protocols/clients/servers ++ */ ++static unsigned int random_port(void) ++{ ++ return RANDOM_PORT_START + (get_timer(0) % RANDOM_PORT_RANGE); ++} ++ ++#define BLOCKSIZE 512 ++ ++void wget_start(void) ++{ ++ image_url = strchr(net_boot_file_name, ':'); ++ if (image_url > 0) { ++ web_server_ip = string_to_ip(net_boot_file_name); ++ ++image_url; ++ net_server_ip = web_server_ip; ++ } else { ++ web_server_ip = net_server_ip; ++ image_url = net_boot_file_name; ++ } ++ ++ debug_cond(DEBUG_WGET, ++ "wget: Transfer HTTP Server %pI4; our IP %pI4\n", ++ &web_server_ip, &net_ip); ++ ++ /* Check if we need to send across this subnet */ ++ if (net_gateway.s_addr && net_netmask.s_addr) { ++ struct in_addr our_net; ++ struct in_addr server_net; ++ ++ our_net.s_addr = net_ip.s_addr & net_netmask.s_addr; ++ server_net.s_addr = net_server_ip.s_addr & net_netmask.s_addr; ++ if (our_net.s_addr != server_net.s_addr) ++ debug_cond(DEBUG_WGET, ++ "wget: sending through gateway %pI4", ++ &net_gateway); ++ } ++ debug_cond(DEBUG_WGET, "URL '%s'\n", image_url); ++ ++ if (net_boot_file_expected_size_in_blocks) { ++ debug_cond(DEBUG_WGET, "wget: Size is 0x%x Bytes = ", ++ net_boot_file_expected_size_in_blocks * BLOCKSIZE); ++ print_size(net_boot_file_expected_size_in_blocks * BLOCKSIZE, ++ ""); ++ } ++ debug_cond(DEBUG_WGET, ++ "\nwget:Load address: 0x%lx\nLoading: *\b", image_load_addr); ++ ++ net_set_timeout_handler(wget_timeout, wget_timeout_handler); ++ tcp_set_tcp_handler(wget_handler); ++ ++ wget_timeout_count = 0; ++ current_wget_state = WGET_CLOSED; ++ ++ our_port = random_port(); ++ ++ /* ++ * Zero out server ether to force arp resolution in case ++ * the server ip for the previous u-boot command, for example dns ++ * is not the same as the web server ip. ++ */ ++ ++ memset(net_server_ethaddr, 0, 6); ++ ++ wget_send(TCP_SYN, 0, 0, 0); ++} +-- +2.45.2 + diff --git a/recipes-bsp/u-boot/files/0004-Fix-eMMC-drive-strength-in-the-u-boot.patch b/recipes-bsp/u-boot/files/0004-Fix-eMMC-drive-strength-in-the-u-boot.patch deleted file mode 100644 index bdf9e22..0000000 --- a/recipes-bsp/u-boot/files/0004-Fix-eMMC-drive-strength-in-the-u-boot.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 421cfebfc53dde5e072385e5190a752245f2a5f4 Mon Sep 17 00:00:00 2001 -From: Mikhail Anikin -Date: Sun, 23 Jun 2024 16:28:54 +0300 -Subject: [PATCH] Fix eMMC drive strength in the u-boot - ---- - arch/arm/dts/hailo15-solidrun.dts | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/dts/hailo15-solidrun.dts b/arch/arm/dts/hailo15-solidrun.dts -index e9322f5254..d9018ce5bd 100644 ---- a/arch/arm/dts/hailo15-solidrun.dts -+++ b/arch/arm/dts/hailo15-solidrun.dts -@@ -28,8 +28,8 @@ - dat-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel - rst-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel - clk-pad-values = <0x2 0x2 0x0 0x0>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel -- sdclkdl-cnfg = <0x1 0x59>; //extdly_en, cckdl_dc -- drive-strength = <0x9 0x8>; //pad_sp, pad_sn -+ sdclkdl-cnfg = <0x0 0x32>; //extdly_en, cckdl_dc -+ drive-strength = <0xC 0xC>; //pad_sp, pad_sn - u-boot,dm-spl; - }; - }; --- -2.45.1 - diff --git a/recipes-bsp/u-boot/files/0004-Hailo-15-SolidRun-support.patch b/recipes-bsp/u-boot/files/0004-Hailo-15-SolidRun-support.patch new file mode 100644 index 0000000..f499c0f --- /dev/null +++ b/recipes-bsp/u-boot/files/0004-Hailo-15-SolidRun-support.patch @@ -0,0 +1,794 @@ +From f72a269096d65bf96e6a579eb5505e2cb5201030 Mon Sep 17 00:00:00 2001 +From: Mikhail Anikin +Date: Tue, 7 May 2024 14:49:25 +0300 +Subject: [PATCH 1/4] Hailo 15 SolidRun initial support + +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/hailo15-solidrun.dts | 105 ++++++++++++++++++++++++++ + arch/arm/mach-hailo/Kconfig | 5 ++ + board/hailo/common/hailo15_spl.c | 5 ++ + board/hailo/hailo15-solidrun/Kconfig | 12 +++ + board/hailo/hailo15-solidrun/Makefile | 3 + + configs/hailo15_solidrun_defconfig | 23 ++++++ + drivers/net/macb.c | 2 +- + include/configs/hailo15-solidrun.h | 58 ++++++++++++++ + 9 files changed, 213 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/dts/hailo15-solidrun.dts + create mode 100644 board/hailo/hailo15-solidrun/Kconfig + create mode 100644 board/hailo/hailo15-solidrun/Makefile + create mode 100644 configs/hailo15_solidrun_defconfig + create mode 100644 include/configs/hailo15-solidrun.h + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 152e070d41..22b57a030b 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -1163,6 +1163,7 @@ dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb + + dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb + ++dtb-$(CONFIG_TARGET_HAILO15_SOLIDRUN) += hailo15-solidrun.dtb + dtb-$(CONFIG_TARGET_HAILO15_GINGER_SOC) += hailo15-ginger-soc.dtb + dtb-$(CONFIG_TARGET_HAILO15_GINGER_SOC_SDIO0) += hailo15-ginger-soc-sdio0.dtb + dtb-$(CONFIG_TARGET_HAILO15_LAVENDER) += hailo15-lavender.dtb +diff --git a/arch/arm/dts/hailo15-solidrun.dts b/arch/arm/dts/hailo15-solidrun.dts +new file mode 100644 +index 0000000000..1e17890f24 +--- /dev/null ++++ b/arch/arm/dts/hailo15-solidrun.dts +@@ -0,0 +1,105 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * dts file for Hailo15 SolidRun SOM. ++ * Copyright (c) 2024 SolidRun Ltd. ++ */ ++ ++#include "hailo15-base.dtsi" ++#include "hailo15_ddr_MT53E1G32D2FW-046_configuration.dtsi" ++#include "hailo15_ddr_MT53E1G32D2FW-046_regconfig_ca_odtb_pd.dtsi" ++#include ++ ++/ { ++ model = "Hailo15 SolidRun SOM"; ++ compatible = "solidrun,hailo15"; ++ ++ aliases { ++ eeprom_som = &eeprom_som; ++ }; ++}; ++ ++ ++&sdio1 { ++ status = "okay"; ++ non-removable; ++ phy-config { ++ card-is-emmc = <0x1>; ++ cmd-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel ++ dat-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel ++ rst-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel ++ clk-pad-values = <0x2 0x2 0x0 0x0>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel ++ sdclkdl-cnfg = <0x1 0x59>; //extdly_en, cckdl_dc ++ drive-strength = <0x9 0x8>; //pad_sp, pad_sn ++ u-boot,dm-spl; ++ }; ++}; ++ ++&macb { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_eth>; ++ phy-mode = "rgmii-id"; ++ phy-handle = <&phy0>; ++ ++ phy0: ethernet-phy@0 { ++ reg = <0>; ++ mxl-8611x,rx-internal-delay-ps = <1650>; ++ mxl-8611x,tx-internal-delay-ps-100m = <2250>; ++ mxl-8611x,tx-internal-delay-ps-1g = <1200>; ++ }; ++}; ++ ++&pinctrl { ++ pinctrl_eth: eth { ++ pins = "eth_rgmii_tx_clk", ++ "eth_rgmii_tx_ctl", ++ "eth_rgmii_txd_0", ++ "eth_rgmii_txd_1", ++ "eth_rgmii_txd_2", ++ "eth_rgmii_txd_3"; ++ drive-strength = <2>; ++ }; ++}; ++ ++&i2c_0 { ++ status = "okay"; ++ ++ eeprom_som: m24c02@50 { ++ compatible = "atmel,24c02"; ++ reg = <0x50>; ++ }; ++ ++ pca9539: pca9539@74 { ++ compatible = "nxp,pca9539"; ++ reg = <0x74>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-line-names = ++ "pca_0_WL_REG_ON", ++ "pca_1_BT_REG_ON", ++ "pca_2_ETH_RST", ++ "pca_3_ENET_nINT", ++ "pca_4", ++ "pca_8_H_PCIE_PERST_N", ++ "pca_9_H_PCIE_CLKREQ_N", ++ "pca_10_H_PCIE_WAKE_N", ++ "pca_11_PCIE_nCLK_N", ++ "pca_12", ++ "pca_13", ++ "pca_14", ++ "pca_15"; ++ ++ WIFI_HOG { ++ gpio-hog; ++ gpios = <0 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "WL_REG_ON"; ++ }; ++ BT_HOG { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "WL_REG_ON"; ++ }; ++ }; ++}; +\ No newline at end of file +diff --git a/arch/arm/mach-hailo/Kconfig b/arch/arm/mach-hailo/Kconfig +index 27bfc5a380..01b7424182 100644 +--- a/arch/arm/mach-hailo/Kconfig ++++ b/arch/arm/mach-hailo/Kconfig +@@ -260,6 +260,10 @@ config SPL_LOAD_FIT_ADDRESS + + endif + ++config TARGET_HAILO15_SOLIDRUN ++ bool "Hailo15 SBC" ++ select MACH_HAILO15 ++ + config TARGET_HAILO15_VP + bool "Hailo15 VP" + select MACH_HAILO15 +@@ -314,6 +318,7 @@ config TARGET_HAILO10_M2_DEVEL + bool "Hailo10 M.2 development" + select MACH_HAILO10 + ++source "board/hailo/hailo15-solidrun/Kconfig" + source "board/hailo/hailo15-vp/Kconfig" + source "board/hailo/hailo15-ginger-soc/Kconfig" + source "board/hailo/hailo15-ginger-soc-sdio0/Kconfig" +diff --git a/board/hailo/common/hailo15_spl.c b/board/hailo/common/hailo15_spl.c +index c21aedc121..ca5c509723 100644 +--- a/board/hailo/common/hailo15_spl.c ++++ b/board/hailo/common/hailo15_spl.c +@@ -41,6 +41,11 @@ void board_boot_order(u32 *spl_boot_list) + #endif /* CONFIG_TARGET_HAILO15L_OREGANO */ + } else if (!strcmp(s, "mmc2")) { + spl_boot_list[0] = BOOT_DEVICE_MMC2; ++#ifdef CONFIG_TARGET_HAILO15_SOLIDRUN ++ /* Fallback to the uart if eMMC is empty */ ++ spl_boot_list[1] = BOOT_DEVICE_UART; ++#endif ++ + } else if (!strcmp(s, "mmc12")) { + spl_boot_list[0] = BOOT_DEVICE_MMC1; + spl_boot_list[1] = BOOT_DEVICE_MMC2; +diff --git a/board/hailo/hailo15-solidrun/Kconfig b/board/hailo/hailo15-solidrun/Kconfig +new file mode 100644 +index 0000000000..c886e471b6 +--- /dev/null ++++ b/board/hailo/hailo15-solidrun/Kconfig +@@ -0,0 +1,12 @@ ++if TARGET_HAILO15_SOLIDRUN ++ ++config SYS_BOARD ++ default "hailo15-solidrun" ++ ++config SYS_VENDOR ++ default "hailo" ++ ++config SYS_CONFIG_NAME ++ default "hailo15-solidrun" ++ ++endif +diff --git a/board/hailo/hailo15-solidrun/Makefile b/board/hailo/hailo15-solidrun/Makefile +new file mode 100644 +index 0000000000..4cf1706f85 +--- /dev/null ++++ b/board/hailo/hailo15-solidrun/Makefile +@@ -0,0 +1,3 @@ ++# SPDX-License-Identifier: GPL-2.0 ++ ++obj- += dummy.o +\ No newline at end of file +diff --git a/configs/hailo15_solidrun_defconfig b/configs/hailo15_solidrun_defconfig +new file mode 100644 +index 0000000000..2380242e63 +--- /dev/null ++++ b/configs/hailo15_solidrun_defconfig +@@ -0,0 +1,23 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_HAILO=y ++CONFIG_TARGET_HAILO15_SOLIDRUN=y ++CONFIG_DEFAULT_DEVICE_TREE="hailo15-solidrun" ++CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_DW=y ++CONFIG_CMD_I2C=y ++CONFIG_SPI_FLASH_ISSI=y ++CONFIG_DM_ETH_PHY=y ++CONFIG_DM_MDIO=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_PHY_MXL8611X=y ++CONFIG_CMD_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_DM_GPIO_LOOKUP_LABEL=y ++CONFIG_DM_PCA953X=y ++ ++CONFIG_MISC=y ++CONFIG_I2C_EEPROM=y ++CONFIG_CMD_EEPROM=y ++CONFIG_CMD_TLV_EEPROM=y ++CONFIG_EEPROM_TLV_LIB=y ++CONFIG_MAC_ADDR_IN_SPIFLASH=y +diff --git a/drivers/net/macb.c b/drivers/net/macb.c +index c9bb9aa1de..b6efdecfa1 100644 +--- a/drivers/net/macb.c ++++ b/drivers/net/macb.c +@@ -64,7 +64,7 @@ DECLARE_GLOBAL_DATA_PTR; + #define MACB_TX_RING_SIZE 16 + + #define MACB_TX_TIMEOUT 1000 +-#define MACB_AUTONEG_TIMEOUT 5000000 ++#define MACB_AUTONEG_TIMEOUT 15000000 + + #ifdef CONFIG_MACB_ZYNQ + /* INCR4 AHB bursts */ +diff --git a/include/configs/hailo15-solidrun.h b/include/configs/hailo15-solidrun.h +new file mode 100644 +index 0000000000..c609a3cb92 +--- /dev/null ++++ b/include/configs/hailo15-solidrun.h +@@ -0,0 +1,58 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (c) 2019-2023 Hailo Technologies Ltd. All rights reserved. ++ * ++ * Configuration for Hailo15. ++ */ ++ ++#ifndef __HAILO15_SOLIDRUN_H ++#define __HAILO15_SOLIDRUN_H ++ ++#define SWUPDATE_MMC_INDEX "1" ++ ++#define BOOTMENU \ ++ /* Try all boot options by order */ \ ++ "bootmenu_0=Autodetect=" \ ++ "if test \"${auto_uboot_update_enable}\" = \"yes\"; then run auto_uboot_update; exit 1; fi; " \ ++ "echo Trying Boot from eMMC; run boot_mmc1;" \ ++ "echo Trying Boot from NFS; run bootnfs;" \ ++ "echo ERROR: All boot options failed\0" \ ++ "bootmenu_1=Boot from eMMC=run boot_mmc1\0" \ ++ "bootmenu_2=Update eMMC (wic) from TFTP=run update_wic_mmc1 && bootmenu -1\0" \ ++ "bootmenu_3=Update eMMC (partitions) from TFTP=run update_partitions_mmc1 && bootmenu -1\0" \ ++ "bootmenu_4=Boot from NFS=run bootnfs\0" \ ++ "default_spl_boot_source=mmc2\0" \ ++ "spl_boot_source=mmc2\0" ++ ++#include "hailo15_common.h" ++ ++/*! @note: lpddr4 inline ecc located at the top 1/8 of the referred CS. ++ * In regards of using LPDDR4 setup of: ++ * - 2 ranks (Also refered as CS) ++ * - 2 channels per rank ++ * - Each channel is 16 bits wide => each rank is 32 bits bide ++ * - Rank size: 2G bytes ++ * If __not__ using ECC, then memory access are located in a single region: ++ * - 0x80000000 - 0x17fffffff: Bank #0 (4G = 0x100000000) ++ * If using ECC, then memory region is spilted to 2 ranges: ++ * - 0x080000000 - 0x0efffffff: Bank #0 (1.75G = 0x70000000) ++ * - 0x0f0000000 - 0x0ffffffff: Bank #0 ECC (0.25G = 0x10000000) ++ * - 0x100000000 - 0x16fffffff: Bank #1 (1.75G = 0x70000000) ++ * - 0x170000000 - 0x17fffffff: Bank #1 ECC (0.25G = 0x10000000) ++ */ ++#ifdef CONFIG_HAILO15_DDR_ENABLE_ECC ++ ++/* Bank 0 size using ECC */ ++#define PHYS_SDRAM_1_SIZE (0x70000000) ++/* Bank 1 address/size using ECC */ ++#define PHYS_SDRAM_2 (0x100000000) ++#define PHYS_SDRAM_2_SIZE (0x70000000) ++ ++#else ++ ++/* Bank 0 size not using ECC */ ++#define PHYS_SDRAM_1_SIZE (0x100000000) ++ ++#endif ++ ++#endif /* __HAILO15_SOLIDRUN_H */ +\ No newline at end of file +-- +2.45.2 + + +From 27ebd20655256c07fd4b81bcbd6629eb1837482b Mon Sep 17 00:00:00 2001 +From: Mikhail Anikin +Date: Wed, 8 May 2024 15:07:41 +0300 +Subject: [PATCH 2/4] Read macs from tlv on boot + +--- + board/hailo/hailo15-solidrun/Makefile | 2 +- + board/hailo/hailo15-solidrun/hailo15_solidrun.c | 10 ++++++++++ + 2 files changed, 11 insertions(+), 1 deletion(-) + create mode 100644 board/hailo/hailo15-solidrun/hailo15_solidrun.c + +diff --git a/board/hailo/hailo15-solidrun/Makefile b/board/hailo/hailo15-solidrun/Makefile +index 4cf1706f85..a4a927ab73 100644 +--- a/board/hailo/hailo15-solidrun/Makefile ++++ b/board/hailo/hailo15-solidrun/Makefile +@@ -1,3 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 + +-obj- += dummy.o +\ No newline at end of file ++obj-$(CONFIG_TARGET_HAILO15_SOLIDRUN) += hailo15_solidrun.o +\ No newline at end of file +diff --git a/board/hailo/hailo15-solidrun/hailo15_solidrun.c b/board/hailo/hailo15-solidrun/hailo15_solidrun.c +new file mode 100644 +index 0000000000..318226cba4 +--- /dev/null ++++ b/board/hailo/hailo15-solidrun/hailo15_solidrun.c +@@ -0,0 +1,10 @@ ++#include ++ ++void set_mac_addr(void) ++{ ++ int ret = mac_read_from_eeprom(); ++ if (ret) ++ { ++ puts("Failed to read MAC from TLV\n"); ++ } ++} +-- +2.45.2 + + +From 849df751a820a403ed1fcce0e80c25ce0c5a238d Mon Sep 17 00:00:00 2001 +From: Mikhail Anikin +Date: Wed, 22 May 2024 15:57:59 +0300 +Subject: [PATCH 3/4] Update DDR binding + +--- + arch/arm/dts/hailo15-solidrun.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/dts/hailo15-solidrun.dts b/arch/arm/dts/hailo15-solidrun.dts +index 1e17890f24..9fd41f7461 100644 +--- a/arch/arm/dts/hailo15-solidrun.dts ++++ b/arch/arm/dts/hailo15-solidrun.dts +@@ -5,8 +5,8 @@ + */ + + #include "hailo15-base.dtsi" +-#include "hailo15_ddr_MT53E1G32D2FW-046_configuration.dtsi" +-#include "hailo15_ddr_MT53E1G32D2FW-046_regconfig_ca_odtb_pd.dtsi" ++#include "hailo15_ddr_configuration.dtsi" ++#include "hailo15_ddr_MT53E1G32D2FW-046_regconfig_ca_odtb_pd_4GB.dtsi" + #include + + / { +-- +2.45.2 + + +From c69bcee8c9df7efd38543421dba3774feb35b198 Mon Sep 17 00:00:00 2001 +From: Mikhail Anikin +Date: Sun, 23 Jun 2024 16:28:54 +0300 +Subject: [PATCH 4/4] Fix eMMC drive strength in the u-boot + +--- + arch/arm/dts/hailo15-solidrun.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/dts/hailo15-solidrun.dts b/arch/arm/dts/hailo15-solidrun.dts +index 9fd41f7461..7db9765237 100644 +--- a/arch/arm/dts/hailo15-solidrun.dts ++++ b/arch/arm/dts/hailo15-solidrun.dts +@@ -28,8 +28,8 @@ + dat-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel + rst-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel + clk-pad-values = <0x2 0x2 0x0 0x0>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- sdclkdl-cnfg = <0x1 0x59>; //extdly_en, cckdl_dc +- drive-strength = <0x9 0x8>; //pad_sp, pad_sn ++ sdclkdl-cnfg = <0x0 0x32>; //extdly_en, cckdl_dc ++ drive-strength = <0xC 0xC>; //pad_sp, pad_sn + u-boot,dm-spl; + }; + }; +-- +2.45.2 + +From 08a3afefa505bc9b217624355c5d6b5e1da38025 Mon Sep 17 00:00:00 2001 +From: Mikhail Anikin +Date: Tue, 6 Aug 2024 15:23:59 +0300 +Subject: [PATCH] SR carrier selection support + +--- + arch/arm/dts/hailo15-solidrun.dts | 22 ++- + .../hailo/hailo15-solidrun/hailo15_solidrun.c | 150 ++++++++++++++++++ + configs/hailo15_solidrun_defconfig | 7 + + include/configs/hailo15-solidrun.h | 61 ++++++- + 4 files changed, 236 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/dts/hailo15-solidrun.dts b/arch/arm/dts/hailo15-solidrun.dts +index 7db9765237..0823ee0180 100644 +--- a/arch/arm/dts/hailo15-solidrun.dts ++++ b/arch/arm/dts/hailo15-solidrun.dts +@@ -15,6 +15,7 @@ + + aliases { + eeprom_som = &eeprom_som; ++ eeprom_carrier = &eeprom_carrier; + }; + }; + +@@ -59,6 +60,12 @@ + "eth_rgmii_txd_3"; + drive-strength = <2>; + }; ++ ++ pinctrl_i2c2: i2c2 { ++ function = "i2c2"; ++ groups = "i2c2_1_grp"; ++ }; ++ + }; + + &i2c_0 { +@@ -74,6 +81,7 @@ + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; ++ reset-gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + gpio-line-names = + "pca_0_WL_REG_ON", + "pca_1_BT_REG_ON", +@@ -102,4 +110,16 @@ + line-name = "WL_REG_ON"; + }; + }; +-}; +\ No newline at end of file ++}; ++ ++&i2c_2 { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2>; ++ ++ eeprom_carrier: at24c02@57 { ++ compatible = "atmel,24c02"; ++ reg = <0x57>; ++ pagesize = <16>; ++ }; ++}; +diff --git a/board/hailo/hailo15-solidrun/hailo15_solidrun.c b/board/hailo/hailo15-solidrun/hailo15_solidrun.c +index 318226cba4..8fd5c700e2 100644 +--- a/board/hailo/hailo15-solidrun/hailo15_solidrun.c ++++ b/board/hailo/hailo15-solidrun/hailo15_solidrun.c +@@ -1,4 +1,149 @@ + #include ++#include ++#include ++#include ++#include ++ ++ ++#define CARRIER_SKU_MAX_SIZE 25 ++#define FIT_CONF_ENV "fit_image_conf" ++ ++/* '#' in the beginning of the configuration name is a part of bootm syntax */ ++#define FIT_CONF_HB_IIOT "#conf-hailo_hailo15-solidrun.dtb" // default ++#define FIT_CONF_HB_PRO "#conf-hailo_hailo15-solidrun-hb-pro.dtb" ++ ++enum carrier_boards ++{ ++ CARRIER_UNRECOGNIZED = 0, ++ CARRIER_HB_MATE, ++ CARRIER_HB_RIPPLE, ++ CARRIER_HB_PULSE, ++ CARRIER_HB_PRO, ++ CARRIER_HB_IIOT, ++}; ++ ++static int get_tlv_udevice_by_alias(struct udevice **dev, const char *alias) ++{ ++ int node, ret; ++ const char *path; ++ path = fdt_get_alias(gd->fdt_blob, alias); ++ if (!path) ++ { ++ pr_err("Cannot find the path for label %s.\n", alias); ++ return -ENODEV; ++ } ++ /* Get the node offset using the path */ ++ node = fdt_path_offset(gd->fdt_blob, path); ++ if (node < 0) ++ { ++ pr_err("Cannot find the node for path %s.\n", path); ++ return -ENODEV; ++ } ++ ++ /* Get the udevice using the node offset */ ++ ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, node, dev); ++ if (ret) ++ { ++ pr_err("Failed to find eeprom device, ret=%d\n", ret); ++ return ret; ++ } ++ return 0; ++} ++ ++int get_sku_from_tlv_dev(struct udevice *dev, char *sku) ++{ ++ int ret = 0; ++ char eeprom[2048]; ++ struct tlvinfo_priv *tlv, *entry; ++ ++ tlv = tlv_eeprom_read(dev, 0, eeprom, ARRAY_SIZE(eeprom)); ++ if (IS_ERR(tlv)) ++ { ++ pr_err("Can't parse the tlv: %d\n", tlv); ++ return tlv; ++ } ++ entry = tlv_entry_next_by_code(tlv, NULL, TLV_CODE_PART_NUMBER); ++ if (IS_ERR(entry)) ++ { ++ pr_err("Bad entry, ret: %d\n", entry); ++ return entry; ++ } ++ ret = tlv_entry_get_string(entry, sku, CARRIER_SKU_MAX_SIZE); ++ if (ret) ++ { ++ pr_err("Can't get tlv_entry_get_string, ret: %d\n", ret); ++ return ret; ++ } ++ return 0; ++} ++ ++int get_carrier(void) ++{ ++ int board, ret = 0; ++ struct udevice *dev; ++ char sku[CARRIER_SKU_MAX_SIZE]; ++ ++ ret = get_tlv_udevice_by_alias(&dev, "eeprom_carrier"); ++ if (ret) ++ return ret; ++ ++ ret = get_sku_from_tlv_dev(dev, sku); ++ if (ret) ++ return ret; ++ ++ switch (sku[5]) ++ { ++ case 'M': // Mate ++ board = CARRIER_HB_MATE; ++ break; ++ case 'R': // Ripple ++ board = CARRIER_HB_RIPPLE; ++ break; ++ case 'U': // Pulse or Extended or Pro ++ board = CARRIER_HB_PULSE; ++ if (sku[6] == 'E' || sku[6] == 'P') ++ board = CARRIER_HB_PRO; ++ break; ++ case 'I': // IIoT ++ board = CARRIER_HB_IIOT; ++ break; ++ default: ++ board = CARRIER_UNRECOGNIZED; ++ pr_warn("Did not recognise board variant in sku \"%s\"\n", sku); ++ } ++ ++ return board; ++} ++ ++void set_fit_image_configurations(void) ++{ ++ int carrier; ++ char *fit_conf = env_get(FIT_CONF_ENV); ++ if (fit_conf != NULL) ++ { ++ printf("Keeping predefined fit config \n"); ++ return; ++ } ++ ++ carrier = get_carrier(); ++ printf("Selecting fdt file for board %d...\n", carrier); ++ switch (carrier) ++ { ++ case CARRIER_HB_MATE: ++ case CARRIER_HB_RIPPLE: ++ case CARRIER_HB_PULSE: ++ case CARRIER_HB_PRO: ++ env_set(FIT_CONF_ENV, FIT_CONF_HB_PRO); ++ break; ++ case CARRIER_HB_IIOT: ++ env_set(FIT_CONF_ENV, FIT_CONF_HB_IIOT); ++ break; ++ default: ++ pr_warn("Leaving default fit configuration \n"); ++ break; ++ } ++} ++ + + void set_mac_addr(void) + { +@@ -8,3 +153,8 @@ void set_mac_addr(void) + puts("Failed to read MAC from TLV\n"); + } + } ++ ++int board_late_init(void) { ++ set_fit_image_configurations(); ++ return 0; ++} +\ No newline at end of file +diff --git a/configs/hailo15_solidrun_defconfig b/configs/hailo15_solidrun_defconfig +index 2380242e63..b02099a571 100644 +--- a/configs/hailo15_solidrun_defconfig ++++ b/configs/hailo15_solidrun_defconfig +@@ -21,3 +21,10 @@ CONFIG_CMD_EEPROM=y + CONFIG_CMD_TLV_EEPROM=y + CONFIG_EEPROM_TLV_LIB=y + CONFIG_MAC_ADDR_IN_SPIFLASH=y ++ ++CONFIG_PROT_TCP=y ++CONFIG_PROT_TCP_SACK=y ++CONFIG_CMD_WGET=y ++ ++CONFIG_CMD_ERASEENV=y ++CONFIG_BOARD_LATE_INIT=y +diff --git a/include/configs/hailo15-solidrun.h b/include/configs/hailo15-solidrun.h +index c609a3cb92..bdcaac6b43 100644 +--- a/include/configs/hailo15-solidrun.h ++++ b/include/configs/hailo15-solidrun.h +@@ -10,6 +10,13 @@ + + #define SWUPDATE_MMC_INDEX "1" + ++#include "hailo15_common.h" ++ ++#ifndef CONFIG_SPL_BUILD ++ ++#undef BOOTMENU ++#undef CONFIG_EXTRA_ENV_SETTINGS ++ + #define BOOTMENU \ + /* Try all boot options by order */ \ + "bootmenu_0=Autodetect=" \ +@@ -18,13 +25,61 @@ + "echo Trying Boot from NFS; run bootnfs;" \ + "echo ERROR: All boot options failed\0" \ + "bootmenu_1=Boot from eMMC=run boot_mmc1\0" \ +- "bootmenu_2=Update eMMC (wic) from TFTP=run update_wic_mmc1 && bootmenu -1\0" \ +- "bootmenu_3=Update eMMC (partitions) from TFTP=run update_partitions_mmc1 && bootmenu -1\0" \ ++ "bootmenu_2=Update eMMC (wic) from HTTP=run update_wic_mmc1 && bootmenu -1\0" \ ++ "bootmenu_3=Update eMMC (partitions) from HTTP=run update_partitions_mmc1 && bootmenu -1\0" \ + "bootmenu_4=Boot from NFS=run bootnfs\0" \ + "default_spl_boot_source=mmc2\0" \ + "spl_boot_source=mmc2\0" + +-#include "hailo15_common.h" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "bootargs_base=setenv bootargs console=ttyS1,${baudrate}n8 earlycon rootwait rw && run bootargs_board\0" \ ++ "bootargs_board=setenv bootargs ${bootargs} ${bootargs_board_options}\0" \ ++ "bootargs_ram=setenv bootargs ${bootargs} root=/dev/ram0 ramdisk_size=${ramdisk_size}\0" \ ++ "bootargs_mmc=setenv bootargs ${bootargs} root=/dev/mmcblk${device_num}p${mmc_rootfs_partition}\0" \ ++ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs rootfstype=nfs ip=${ipaddr} nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ ++ "ramdisk_size=0x8000000\0" \ ++ "far_ram_addr=0x85000000\0" \ ++ "get_rootfs_partition_start_offset=part start mmc ${device_num} ${mmc_rootfs_partition} rootfs_partition_start_offset\0" \ ++ "sd_block_size=200\0" /* in hex, taken from running mmcinfo */\ ++ "serverip=10.0.0.2\0" \ ++ "ipaddr=10.0.0.1\0" \ ++ "set_mmc0_device_num= setenv device_num 0 && mmc dev ${device_num}\0" \ ++ "set_mmc1_device_num= setenv device_num 1 && mmc dev ${device_num}\0" \ ++ "load_fitimage_from_mmc=" UNNEEDED_MMCINFO_HACK " fatload mmc ${device_num}:${mmc_boot_partition} ${far_ram_addr} fitImage\0" \ ++ "write_fitimage_to_mmc=" UNNEEDED_MMCINFO_HACK " fatwrite mmc ${device_num}:${mmc_boot_partition} ${far_ram_addr} fitImage ${filesize}\0" \ ++ "write_uboot_to_mmc=" UNNEEDED_MMCINFO_HACK " fatwrite mmc ${device_num}:${mmc_boot_partition} ${far_ram_addr} " CONFIG_SPL_FS_LOAD_PAYLOAD_NAME " ${filesize}\0" \ ++ "write_uboot_to_mmc0_mmc1=run set_mmc0_device_num && run write_uboot_to_mmc; run set_mmc1_device_num && run write_uboot_to_mmc\0" \ ++ /* "mmc write" writes in blocks, so we first calculate the number of blocks we read into wic_sdblock_count. */\ ++ /* we assume this is called after 'tftpboot' - so filesize is populated */\ ++ "write_wic_to_mmc=setexpr wic_sdblock_count ${filesize} / ${sd_block_size} && setexpr wic_sdblock_count ${wic_sdblock_count} + 1; " UNNEEDED_MMCINFO_HACK " mmc write ${far_ram_addr} 0 ${wic_sdblock_count}\0" \ ++ "write_rootfs_to_mmc=setexpr rootfs_sdblock_count ${filesize} / ${sd_block_size} && setexpr rootfs_sdblock_count ${rootfs_sdblock_count} + 1; " UNNEEDED_MMCINFO_HACK " run get_rootfs_partition_start_offset && mmc write ${far_ram_addr} ${rootfs_partition_start_offset} ${rootfs_sdblock_count}\0" \ ++ /* tftpboot sets filesize to the size it loaded */\ ++ "download_wic_to_ram=wget ${far_ram_addr} ${serverip}/:core-image-minimal-" CONFIG_SYS_BOARD ".wic\0" \ ++ "download_rootfs_to_ram=wget ${far_ram_addr} ${serverip}/:core-image-minimal-" CONFIG_SYS_BOARD ".ext4\0" \ ++ "download_fitimage_to_ram=wget ${far_ram_addr} ${serverip}/:fitImage\0" \ ++ "download_uboot_to_ram=wget ${far_ram_addr} ${serverip}/:" CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "\0" \ ++ "boot_mmc=run bootargs_base bootargs_mmc && run load_fitimage_from_mmc && bootm ${far_ram_addr}${fit_image_conf}\0" \ ++ "boot_mmc0=run set_mmc0_device_num && run boot_mmc\0"\ ++ "boot_mmc1=run set_mmc1_device_num && run boot_mmc\0"\ ++ "update_wic=run download_wic_to_ram && run write_wic_to_mmc\0" \ ++ "update_wic_mmc0=run set_mmc0_device_num && run update_wic\0" \ ++ "update_wic_mmc1=run set_mmc1_device_num && run update_wic\0" \ ++ "update_rootfs=run download_rootfs_to_ram && run write_rootfs_to_mmc\0" \ ++ "update_fitimage=run download_fitimage_to_ram && run write_fitimage_to_mmc\0" \ ++ "update_uboot=run download_uboot_to_ram && run write_uboot_to_mmc\0" \ ++ "update_uboot_mmc0_mmc1=run download_uboot_to_ram && run write_uboot_to_mmc0_mmc1\0" \ ++ "update_partitions_mmc0=run set_mmc0_device_num && run update_partitions\0"\ ++ "update_partitions_mmc1=run set_mmc1_device_num && run update_partitions\0"\ ++ "nfsroot=/mnt/hailo15_nfs/\0"\ ++ "bootnfs=run download_fitimage_to_ram && run bootargs_base bootargs_nfs && bootm ${far_ram_addr}${fit_image_conf}\0" \ ++ "auto_uboot_update=run update_uboot_mmc0_mmc1; env set auto_uboot_update_enable no && env set spl_boot_source ${default_spl_boot_source} && env set bootdelay ${default_bootdelay} && saveenv\0" \ ++ "auto_uboot_update_enable=no\0" \ ++ "default_bootdelay=2\0" \ ++ BOOTMENU \ ++ UPDATE_PARTITIONS_COMMAND ++ ++#endif + + /*! @note: lpddr4 inline ecc located at the top 1/8 of the referred CS. + * In regards of using LPDDR4 setup of: +-- +2.45.2 + +From d8f0059b116428b9d784b72e3c5f22d3eebc4d6e Mon Sep 17 00:00:00 2001 +From: Mikhail Anikin +Date: Mon, 12 Aug 2024 14:52:30 +0300 +Subject: [PATCH] Wifi Support + +--- + arch/arm/dts/hailo15-solidrun.dts | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/arch/arm/dts/hailo15-solidrun.dts b/arch/arm/dts/hailo15-solidrun.dts +index 0823ee0180..1e7deb6615 100644 +--- a/arch/arm/dts/hailo15-solidrun.dts ++++ b/arch/arm/dts/hailo15-solidrun.dts +@@ -20,6 +20,27 @@ + }; + + ++// &hailo_boot_info { ++// uart-0-reverse-rts; ++// uart-0-reverse-cts; ++// }; ++ ++ ++/* SDIO0 should be enabled in u-boot in order to work in Linux */ ++&sdio0 { ++ status = "okay"; ++ non-removable; ++ phy-config { ++ card-is-emmc = <0x1>; ++ cmd-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel ++ dat-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel ++ rst-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel ++ clk-pad-values = <0x2 0x2 0x0 0x0>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel ++ sdclkdl-cnfg = <0x0 0x32>; //extdly_en, cckdl_dc ++ drive-strength = <0xC 0xC>; //pad_sp, pad_sn ++ }; ++}; ++ + &sdio1 { + status = "okay"; + non-removable; +-- +2.45.2 + diff --git a/recipes-bsp/u-boot/u-boot_%.bbappend b/recipes-bsp/u-boot/u-boot_%.bbappend index 2bb2880..b8d00fc 100644 --- a/recipes-bsp/u-boot/u-boot_%.bbappend +++ b/recipes-bsp/u-boot/u-boot_%.bbappend @@ -3,6 +3,6 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/files:" SRC_URI:append = " \ file://0001-MXL8611X-support.patch \ file://0002-tlv-lib.patch \ - file://0003-Hailo-15-SolidRun-initial-support.patch \ - file://0004-Fix-eMMC-drive-strength-in-the-u-boot.patch \ + file://0003-u-boot-wget.patch \ + file://0004-Hailo-15-SolidRun-support.patch \ " diff --git a/recipes-kernel/linux/linux-yocto-hailo.bbappend b/recipes-kernel/linux/linux-yocto-hailo.bbappend index ecf5d14..2b40c26 100644 --- a/recipes-kernel/linux/linux-yocto-hailo.bbappend +++ b/recipes-kernel/linux/linux-yocto-hailo.bbappend @@ -1,8 +1,9 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" SRC_URI:append = " \ + file://0001-Fix-kernel-symlinks.patch \ file://0001-MXL8611X-support.patch \ - file://0002-Hailo-15-SolidRun-initial-support.patch \ + file://0002-Hailo-15-SolidRun-support.patch \ " # defconfig diff --git a/recipes-kernel/linux/linux-yocto-hailo/0001-Fix-kernel-symlinks.patch b/recipes-kernel/linux/linux-yocto-hailo/0001-Fix-kernel-symlinks.patch new file mode 100644 index 0000000..da5c2f0 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto-hailo/0001-Fix-kernel-symlinks.patch @@ -0,0 +1,1218274 @@ +From 9e638e90a4745948cbbfa6bac979453c3f6cdfd5 Mon Sep 17 00:00:00 2001 +From: Mikhail Anikin +Date: Mon, 29 Jul 2024 19:17:14 +0300 +Subject: [PATCH] Restore kernel tree + +--- + scripts/dtc/include-prefixes/arc | 1 + + scripts/dtc/include-prefixes/arc/Makefile | 17 - + .../include-prefixes/arc/abilis_tb100.dtsi | 336 - + .../include-prefixes/arc/abilis_tb100_dvk.dts | 116 - + .../include-prefixes/arc/abilis_tb101.dtsi | 345 - + .../include-prefixes/arc/abilis_tb101_dvk.dts | 116 - + .../include-prefixes/arc/abilis_tb10x.dtsi | 243 - + scripts/dtc/include-prefixes/arc/axc001.dtsi | 126 - + scripts/dtc/include-prefixes/arc/axc003.dtsi | 161 - + .../dtc/include-prefixes/arc/axc003_idu.dtsi | 167 - + scripts/dtc/include-prefixes/arc/axs101.dts | 19 - + scripts/dtc/include-prefixes/arc/axs103.dts | 22 - + .../dtc/include-prefixes/arc/axs103_idu.dts | 22 - + .../dtc/include-prefixes/arc/axs10x_mb.dtsi | 330 - + scripts/dtc/include-prefixes/arc/haps_hs.dts | 99 - + .../dtc/include-prefixes/arc/haps_hs_idu.dts | 74 - + scripts/dtc/include-prefixes/arc/hsdk.dts | 351 - + scripts/dtc/include-prefixes/arc/nsim_700.dts | 59 - + scripts/dtc/include-prefixes/arc/nsimosci.dts | 88 - + .../dtc/include-prefixes/arc/nsimosci_hs.dts | 90 - + .../include-prefixes/arc/nsimosci_hs_idu.dts | 98 - + .../dtc/include-prefixes/arc/skeleton.dtsi | 48 - + .../dtc/include-prefixes/arc/skeleton_hs.dtsi | 49 - + .../include-prefixes/arc/skeleton_hs_idu.dtsi | 61 - + .../dtc/include-prefixes/arc/vdk_axc003.dtsi | 65 - + .../include-prefixes/arc/vdk_axc003_idu.dtsi | 73 - + .../include-prefixes/arc/vdk_axs10x_mb.dtsi | 126 - + scripts/dtc/include-prefixes/arc/vdk_hs38.dts | 19 - + .../dtc/include-prefixes/arc/vdk_hs38_smp.dts | 19 - + scripts/dtc/include-prefixes/arm | 1 + + scripts/dtc/include-prefixes/arm/Makefile | 1501 ---- + scripts/dtc/include-prefixes/arm/aks-cdu.dts | 122 - + .../arm/alphascale-asm9260-devkit.dts | 13 - + .../arm/alphascale-asm9260.dtsi | 64 - + .../dtc/include-prefixes/arm/alpine-db.dts | 35 - + scripts/dtc/include-prefixes/arm/alpine.dtsi | 176 - + .../arm/am335x-baltos-ir2110.dts | 83 - + .../arm/am335x-baltos-ir3220.dts | 125 - + .../arm/am335x-baltos-ir5221.dts | 149 - + .../arm/am335x-baltos-leds.dtsi | 47 - + .../include-prefixes/arm/am335x-baltos.dtsi | 401 - + .../include-prefixes/arm/am335x-base0033.dts | 92 - + .../arm/am335x-bone-common.dtsi | 406 - + .../dtc/include-prefixes/arm/am335x-bone.dts | 23 - + .../arm/am335x-boneblack-common.dtsi | 34 - + .../arm/am335x-boneblack-hdmi.dtsi | 141 - + .../arm/am335x-boneblack-wireless.dts | 111 - + .../include-prefixes/arm/am335x-boneblack.dts | 170 - + .../include-prefixes/arm/am335x-boneblue.dts | 616 -- + .../arm/am335x-bonegreen-common.dtsi | 41 - + .../arm/am335x-bonegreen-wireless.dts | 127 - + .../include-prefixes/arm/am335x-bonegreen.dts | 14 - + .../arm/am335x-chiliboard.dts | 186 - + .../include-prefixes/arm/am335x-chilisom.dtsi | 175 - + .../include-prefixes/arm/am335x-cm-t335.dts | 516 -- + .../dtc/include-prefixes/arm/am335x-evm.dts | 784 -- + .../dtc/include-prefixes/arm/am335x-evmsk.dts | 721 -- + .../include-prefixes/arm/am335x-guardian.dts | 490 -- + .../dtc/include-prefixes/arm/am335x-icev2.dts | 514 -- + .../include-prefixes/arm/am335x-igep0033.dtsi | 300 - + .../dtc/include-prefixes/arm/am335x-lxm.dts | 347 - + .../arm/am335x-moxa-uc-2100-common.dtsi | 227 - + .../arm/am335x-moxa-uc-2101.dts | 68 - + .../arm/am335x-moxa-uc-8100-common.dtsi | 423 -- + .../arm/am335x-moxa-uc-8100-me-t.dts | 101 - + .../arm/am335x-myirtech-myc.dtsi | 270 - + .../arm/am335x-myirtech-myd.dts | 538 -- + .../dtc/include-prefixes/arm/am335x-nano.dts | 472 -- + .../arm/am335x-netcan-plus-1xx.dts | 87 - + .../arm/am335x-netcom-plus-2xx.dts | 95 - + .../arm/am335x-netcom-plus-8xx.dts | 115 - + .../arm/am335x-osd3358-sm-red.dts | 434 -- + .../arm/am335x-osd335x-common.dtsi | 124 - + .../include-prefixes/arm/am335x-pcm-953.dtsi | 240 - + .../include-prefixes/arm/am335x-pdu001.dts | 573 -- + .../include-prefixes/arm/am335x-pepper.dts | 639 -- + .../arm/am335x-phycore-rdk.dts | 28 - + .../arm/am335x-phycore-som.dtsi | 343 - + .../arm/am335x-pocketbeagle.dts | 483 -- + .../include-prefixes/arm/am335x-regor-rdk.dts | 24 - + .../include-prefixes/arm/am335x-regor.dtsi | 201 - + .../arm/am335x-sancloud-bbe-common.dtsi | 67 - + .../arm/am335x-sancloud-bbe-lite.dts | 50 - + .../arm/am335x-sancloud-bbe.dts | 53 - + .../include-prefixes/arm/am335x-sbc-t335.dts | 176 - + .../dtc/include-prefixes/arm/am335x-shc.dts | 559 -- + .../dtc/include-prefixes/arm/am335x-sl50.dts | 721 -- + .../include-prefixes/arm/am335x-wega-rdk.dts | 23 - + .../dtc/include-prefixes/arm/am335x-wega.dtsi | 195 - + .../include-prefixes/arm/am33xx-clocks.dtsi | 676 -- + .../dtc/include-prefixes/arm/am33xx-l4.dtsi | 2321 ------ + scripts/dtc/include-prefixes/arm/am33xx.dtsi | 714 -- + .../arm/am3517-craneboard.dts | 171 - + .../include-prefixes/arm/am3517-evm-ui.dtsi | 217 - + .../dtc/include-prefixes/arm/am3517-evm.dts | 322 - + .../dtc/include-prefixes/arm/am3517-som.dtsi | 234 - + scripts/dtc/include-prefixes/arm/am3517.dtsi | 197 - + .../arm/am3517_mt_ventoux.dts | 24 - + .../include-prefixes/arm/am35xx-clocks.dtsi | 125 - + scripts/dtc/include-prefixes/arm/am3703.dtsi | 14 - + scripts/dtc/include-prefixes/arm/am3715.dtsi | 10 - + .../include-prefixes/arm/am3874-iceboard.dts | 489 -- + scripts/dtc/include-prefixes/arm/am4372.dtsi | 804 -- + .../include-prefixes/arm/am437x-cm-t43.dts | 422 -- + .../include-prefixes/arm/am437x-gp-evm.dts | 1124 --- + .../include-prefixes/arm/am437x-idk-evm.dts | 543 -- + .../dtc/include-prefixes/arm/am437x-l4.dtsi | 2557 ------- + .../include-prefixes/arm/am437x-sbc-t43.dts | 177 - + .../include-prefixes/arm/am437x-sk-evm.dts | 898 --- + .../include-prefixes/arm/am43x-epos-evm.dts | 1024 --- + .../include-prefixes/arm/am43xx-clocks.dtsi | 883 --- + .../dtc/include-prefixes/arm/am57-pruss.dtsi | 226 - + scripts/dtc/include-prefixes/arm/am5718.dtsi | 29 - + .../dtc/include-prefixes/arm/am571x-idk.dts | 218 - + scripts/dtc/include-prefixes/arm/am5728.dtsi | 34 - + .../arm/am5729-beagleboneai.dts | 704 -- + .../arm/am572x-idk-common.dtsi | 203 - + .../dtc/include-prefixes/arm/am572x-idk.dts | 37 - + scripts/dtc/include-prefixes/arm/am5748.dtsi | 30 - + .../dtc/include-prefixes/arm/am574x-idk.dts | 49 - + .../arm/am57xx-beagle-x15-common.dtsi | 647 -- + .../arm/am57xx-beagle-x15-revb1.dts | 36 - + .../arm/am57xx-beagle-x15-revc.dts | 31 - + .../arm/am57xx-beagle-x15.dts | 38 - + .../arm/am57xx-cl-som-am57x.dts | 628 -- + .../arm/am57xx-commercial-grade.dtsi | 24 - + .../arm/am57xx-idk-common.dtsi | 608 -- + .../arm/am57xx-industrial-grade.dtsi | 24 - + .../include-prefixes/arm/am57xx-sbc-am57x.dts | 176 - + .../dtc/include-prefixes/arm/animeo_ip.dts | 197 - + .../arm-realview-eb-11mp-bbrevd-ctrevb.dts | 32 - + .../arm/arm-realview-eb-11mp-bbrevd.dts | 28 - + .../arm/arm-realview-eb-11mp-ctrevb.dts | 93 - + .../arm/arm-realview-eb-11mp.dts | 74 - + .../arm/arm-realview-eb-a9mp-bbrevd.dts | 28 - + .../arm/arm-realview-eb-a9mp.dts | 70 - + .../arm/arm-realview-eb-bbrevd.dts | 29 - + .../arm/arm-realview-eb-bbrevd.dtsi | 45 - + .../arm/arm-realview-eb-mp.dtsi | 220 - + .../include-prefixes/arm/arm-realview-eb.dts | 166 - + .../include-prefixes/arm/arm-realview-eb.dtsi | 468 -- + .../arm/arm-realview-pb1176.dts | 592 -- + .../arm/arm-realview-pb11mp.dts | 718 -- + .../arm/arm-realview-pba8.dts | 178 - + .../arm/arm-realview-pbx-a9.dts | 228 - + .../arm/arm-realview-pbx.dtsi | 577 -- + .../include-prefixes/arm/armada-370-db.dts | 244 - + .../arm/armada-370-dlink-dns327l.dts | 330 - + .../arm/armada-370-mirabox.dts | 184 - + .../arm/armada-370-netgear-rn102.dts | 276 - + .../arm/armada-370-netgear-rn104.dts | 302 - + .../include-prefixes/arm/armada-370-rd.dts | 258 - + .../arm/armada-370-seagate-nas-2bay.dts | 33 - + .../arm/armada-370-seagate-nas-4bay.dts | 131 - + .../arm/armada-370-seagate-nas-xbay.dtsi | 239 - + ...armada-370-seagate-personal-cloud-2bay.dts | 48 - + .../arm/armada-370-seagate-personal-cloud.dts | 34 - + .../armada-370-seagate-personal-cloud.dtsi | 175 - + .../arm/armada-370-synology-ds213j.dts | 312 - + .../include-prefixes/arm/armada-370-xp.dtsi | 313 - + .../dtc/include-prefixes/arm/armada-370.dtsi | 419 -- + .../include-prefixes/arm/armada-375-db.dts | 182 - + .../dtc/include-prefixes/arm/armada-375.dtsi | 621 -- + .../dtc/include-prefixes/arm/armada-380.dtsi | 118 - + .../arm/armada-382-rd-ac3x-48g4x2xl.dts | 112 - + .../arm/armada-385-atl-x530.dts | 235 - + .../arm/armada-385-clearfog-gtr-l8.dts | 115 - + .../arm/armada-385-clearfog-gtr-s4.dts | 79 - + .../arm/armada-385-clearfog-gtr.dtsi | 450 -- + .../arm/armada-385-db-88f6820-amc.dts | 155 - + .../include-prefixes/arm/armada-385-db-ap.dts | 238 - + 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.../include-prefixes/arm/nuvoton-npcm730.dtsi | 44 - + .../arm/nuvoton-npcm750-evb.dts | 404 - + .../arm/nuvoton-npcm750-pincfg-evb.dtsi | 157 - + ...nuvoton-npcm750-runbmc-olympus-pincfg.dtsi | 517 -- + .../arm/nuvoton-npcm750-runbmc-olympus.dts | 1052 --- + .../include-prefixes/arm/nuvoton-npcm750.dtsi | 62 - + .../nuvoton-wpcm450-supermicro-x9sci-ln4f.dts | 40 - + .../include-prefixes/arm/nuvoton-wpcm450.dtsi | 76 - + .../arm/omap-gpmc-smsc911x.dtsi | 55 - + .../arm/omap-gpmc-smsc9221.dtsi | 59 - + .../arm/omap-zoom-common.dtsi | 92 - + scripts/dtc/include-prefixes/arm/omap2.dtsi | 337 - + .../include-prefixes/arm/omap2420-clocks.dtsi | 267 - + .../dtc/include-prefixes/arm/omap2420-h4.dts | 63 - + .../include-prefixes/arm/omap2420-n800.dts | 9 - + .../arm/omap2420-n810-wimax.dts | 9 - + .../include-prefixes/arm/omap2420-n810.dts | 75 - + .../arm/omap2420-n8x0-common.dtsi | 111 - + .../dtc/include-prefixes/arm/omap2420.dtsi | 265 - + .../include-prefixes/arm/omap2430-clocks.dtsi | 341 - + .../dtc/include-prefixes/arm/omap2430-sdp.dts | 70 - + .../dtc/include-prefixes/arm/omap2430.dtsi | 369 - + .../include-prefixes/arm/omap24xx-clocks.dtsi | 1241 --- + .../include-prefixes/arm/omap3-beagle-ab4.dts | 47 - + .../arm/omap3-beagle-xm-ab.dts | 13 - + .../include-prefixes/arm/omap3-beagle-xm.dts | 419 -- + .../dtc/include-prefixes/arm/omap3-beagle.dts | 436 -- + .../include-prefixes/arm/omap3-cm-t3517.dts | 158 - + .../include-prefixes/arm/omap3-cm-t3530.dts | 60 - + .../include-prefixes/arm/omap3-cm-t3730.dts | 98 - + .../include-prefixes/arm/omap3-cm-t3x.dtsi | 326 - + .../include-prefixes/arm/omap3-cm-t3x30.dtsi | 131 - + .../arm/omap3-cpu-thermal.dtsi | 41 - + .../arm/omap3-devkit8000-common.dtsi | 392 - + .../arm/omap3-devkit8000-lcd-common.dtsi | 73 - + .../arm/omap3-devkit8000-lcd43.dts | 34 - + .../arm/omap3-devkit8000-lcd70.dts | 34 - + .../include-prefixes/arm/omap3-devkit8000.dts | 16 - + .../dtc/include-prefixes/arm/omap3-echo.dts | 724 -- + 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.../dtc/include-prefixes/arm/omap3-ldp.dts | 305 - + .../arm/omap3-lilly-a83x.dtsi | 459 -- + .../arm/omap3-lilly-dbb056.dts | 166 - + scripts/dtc/include-prefixes/arm/omap3-n9.dts | 84 - + .../dtc/include-prefixes/arm/omap3-n900.dts | 1194 --- + .../include-prefixes/arm/omap3-n950-n9.dtsi | 504 -- + .../dtc/include-prefixes/arm/omap3-n950.dts | 273 - + .../arm/omap3-overo-alto35-common.dtsi | 75 - + .../arm/omap3-overo-alto35.dts | 19 - + .../arm/omap3-overo-base.dtsi | 274 - + .../arm/omap3-overo-chestnut43-common.dtsi | 65 - + .../arm/omap3-overo-chestnut43.dts | 35 - + .../arm/omap3-overo-common-dvi.dtsi | 108 - + .../arm/omap3-overo-common-lcd35.dtsi | 163 - + .../arm/omap3-overo-common-lcd43.dtsi | 175 - + .../arm/omap3-overo-common-peripherals.dtsi | 92 - + .../arm/omap3-overo-gallop43-common.dtsi | 55 - + .../arm/omap3-overo-gallop43.dts | 35 - + .../arm/omap3-overo-palo35-common.dtsi | 50 - + .../arm/omap3-overo-palo35.dts | 34 - + .../arm/omap3-overo-palo43-common.dtsi | 51 - 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.../include-prefixes/arm/omap3-sb-t35.dtsi | 138 - + .../include-prefixes/arm/omap3-sbc-t3517.dts | 76 - + .../include-prefixes/arm/omap3-sbc-t3530.dts | 48 - + .../include-prefixes/arm/omap3-sbc-t3730.dts | 44 - + .../dtc/include-prefixes/arm/omap3-sniper.dts | 251 - + .../include-prefixes/arm/omap3-tao3530.dtsi | 350 - + .../include-prefixes/arm/omap3-thunder.dts | 126 - + .../dtc/include-prefixes/arm/omap3-zoom3.dts | 231 - + scripts/dtc/include-prefixes/arm/omap3.dtsi | 1020 --- + .../dtc/include-prefixes/arm/omap3430-sdp.dts | 195 - + .../arm/omap3430es1-clocks.dtsi | 205 - + .../arm/omap34xx-omap36xx-clocks.dtsi | 265 - + .../dtc/include-prefixes/arm/omap34xx.dtsi | 197 - + ...map36xx-am35xx-omap3430es2plus-clocks.dtsi | 239 - + .../include-prefixes/arm/omap36xx-clocks.dtsi | 111 - + .../arm/omap36xx-omap3430es2plus-clocks.dtsi | 195 - + .../dtc/include-prefixes/arm/omap36xx.dtsi | 249 - + .../include-prefixes/arm/omap3xxx-clocks.dtsi | 1662 ---- + .../arm/omap4-cpu-thermal.dtsi | 41 - + .../arm/omap4-droid-bionic-xt875.dts | 55 - + .../arm/omap4-droid4-xt894.dts | 157 - + .../arm/omap4-duovero-parlor.dts | 194 - + .../include-prefixes/arm/omap4-duovero.dtsi | 249 - + .../dtc/include-prefixes/arm/omap4-kc1.dts | 179 - + .../include-prefixes/arm/omap4-l4-abe.dtsi | 497 -- + .../dtc/include-prefixes/arm/omap4-l4.dtsi | 2483 ------ + .../dtc/include-prefixes/arm/omap4-mcpdm.dtsi | 44 - + .../include-prefixes/arm/omap4-panda-a4.dts | 17 - + .../arm/omap4-panda-common.dtsi | 607 -- + .../include-prefixes/arm/omap4-panda-es.dts | 114 - + .../dtc/include-prefixes/arm/omap4-panda.dts | 13 - + .../arm/omap4-sdp-es23plus.dts | 14 - + .../dtc/include-prefixes/arm/omap4-sdp.dts | 717 -- + .../arm/omap4-var-dvk-om44.dts | 68 - + .../arm/omap4-var-om44customboard.dtsi | 232 - + .../arm/omap4-var-som-om44-wlan.dtsi | 75 - + .../arm/omap4-var-som-om44.dtsi | 325 - + .../arm/omap4-var-stk-om44.dts | 14 - + scripts/dtc/include-prefixes/arm/omap4.dtsi | 868 --- + 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+ .../dt-bindings/clock/rk3568-cru.h | 926 --- + .../dt-bindings/clock/rockchip,rk808.h | 12 - + .../dt-bindings/clock/rv1108-cru.h | 353 - + .../dt-bindings/clock/s3c2410.h | 59 - + .../dt-bindings/clock/s3c2412.h | 70 - + .../dt-bindings/clock/s3c2443.h | 91 - + .../dt-bindings/clock/s5pv210-audss.h | 31 - + .../dt-bindings/clock/s5pv210.h | 236 - + .../dt-bindings/clock/samsung,s2mps11.h | 20 - + .../dt-bindings/clock/samsung,s3c64xx-clock.h | 175 - + .../dt-bindings/clock/sh73a0-clock.h | 82 - + .../dt-bindings/clock/sifive-fu540-prci.h | 18 - + .../dt-bindings/clock/sifive-fu740-prci.h | 24 - + .../dt-bindings/clock/sprd,sc9860-clk.h | 423 -- + .../dt-bindings/clock/sprd,sc9863a-clk.h | 339 - + .../dt-bindings/clock/ste-ab8500.h | 12 - + .../dt-bindings/clock/stih407-clks.h | 91 - + .../dt-bindings/clock/stih410-clks.h | 26 - + .../dt-bindings/clock/stih416-clks.h | 17 - + .../dt-bindings/clock/stih418-clks.h | 35 - + .../dt-bindings/clock/stm32fx-clock.h | 63 - + .../dt-bindings/clock/stm32h7-clks.h | 165 - + .../dt-bindings/clock/stm32mp1-clks.h | 278 - + .../dt-bindings/clock/stratix10-clock.h | 86 - + .../dt-bindings/clock/sun4i-a10-ccu.h | 202 - + .../dt-bindings/clock/sun4i-a10-pll2.h | 53 - + .../dt-bindings/clock/sun50i-a100-ccu.h | 116 - + .../dt-bindings/clock/sun50i-a100-r-ccu.h | 23 - + .../dt-bindings/clock/sun50i-a64-ccu.h | 138 - + .../dt-bindings/clock/sun50i-h6-ccu.h | 125 - + .../dt-bindings/clock/sun50i-h6-r-ccu.h | 26 - + .../dt-bindings/clock/sun50i-h616-ccu.h | 115 - + .../dt-bindings/clock/sun5i-ccu.h | 97 - + .../dt-bindings/clock/sun6i-a31-ccu.h | 193 - + .../dt-bindings/clock/sun7i-a20-ccu.h | 53 - + .../dt-bindings/clock/sun8i-a23-a33-ccu.h | 129 - + .../dt-bindings/clock/sun8i-a83t-ccu.h | 140 - + .../dt-bindings/clock/sun8i-de2.h | 21 - + .../dt-bindings/clock/sun8i-h3-ccu.h | 152 - + .../dt-bindings/clock/sun8i-r-ccu.h | 59 - + .../dt-bindings/clock/sun8i-r40-ccu.h | 191 - + .../dt-bindings/clock/sun8i-tcon-top.h | 11 - + .../dt-bindings/clock/sun8i-v3s-ccu.h | 111 - + .../dt-bindings/clock/sun9i-a80-ccu.h | 162 - + .../dt-bindings/clock/sun9i-a80-de.h | 80 - + .../dt-bindings/clock/sun9i-a80-usb.h | 59 - + .../dt-bindings/clock/suniv-ccu-f1c100s.h | 70 - + .../dt-bindings/clock/tegra114-car.h | 346 - + .../dt-bindings/clock/tegra124-car-common.h | 349 - + .../dt-bindings/clock/tegra124-car.h | 20 - + .../dt-bindings/clock/tegra186-clock.h | 941 --- + .../dt-bindings/clock/tegra194-clock.h | 321 - + .../dt-bindings/clock/tegra20-car.h | 159 - + .../dt-bindings/clock/tegra210-car.h | 414 - + .../dt-bindings/clock/tegra234-clock.h | 14 - + .../dt-bindings/clock/tegra30-car.h | 276 - + .../dt-bindings/clock/ti-dra7-atl.h | 40 - + .../dt-bindings/clock/vf610-clock.h | 202 - + .../dt-bindings/clock/x1000-cgu.h | 54 - + .../dt-bindings/clock/x1830-cgu.h | 57 - + .../dt-bindings/clock/xlnx-vcu.h | 15 - + .../dt-bindings/clock/xlnx-versal-clk.h | 123 - + .../dt-bindings/clock/xlnx-zynqmp-clk.h | 126 - + .../dt-bindings/display/sdtv-standards.h | 76 - + .../dt-bindings/display/tda998x.h | 8 - + .../include-prefixes/dt-bindings/dma/at91.h | 51 - + .../dt-bindings/dma/axi-dmac.h | 48 - + .../dt-bindings/dma/dw-dmac.h | 14 - + .../dt-bindings/dma/jz4775-dma.h | 44 - + .../dt-bindings/dma/jz4780-dma.h | 49 - + .../dt-bindings/dma/nbpfaxi.h | 17 - + .../dt-bindings/dma/qcom-gpi.h | 11 - + .../dt-bindings/dma/sun4i-a10.h | 56 - + .../dt-bindings/dma/x1000-dma.h | 40 - + .../dt-bindings/dma/x1830-dma.h | 39 - + .../dt-bindings/dma/x2000-dma.h | 54 - + .../dt-bindings/dma/xlnx-zynqmp-dpdma.h | 16 - + .../dt-bindings/firmware/imx/rsrc.h | 635 -- + .../dt-bindings/gce/mt6779-gce.h | 222 - + .../dt-bindings/gce/mt8173-gce.h | 44 - + .../dt-bindings/gce/mt8183-gce.h | 175 - + .../dt-bindings/gce/mt8192-gce.h | 335 - + .../dt-bindings/gce/mt8195-gce.h | 812 -- + .../dt-bindings/gpio/aspeed-gpio.h | 49 - + .../include-prefixes/dt-bindings/gpio/gpio.h | 42 - + .../dt-bindings/gpio/meson-a1-gpio.h | 73 - + .../dt-bindings/gpio/meson-axg-gpio.h | 116 - + .../dt-bindings/gpio/meson-g12a-gpio.h | 114 - + .../dt-bindings/gpio/meson-gxbb-gpio.h | 148 - + .../dt-bindings/gpio/meson-gxl-gpio.h | 125 - + .../dt-bindings/gpio/meson8-gpio.h | 151 - + .../dt-bindings/gpio/meson8b-gpio.h | 121 - + .../dt-bindings/gpio/msc313-gpio.h | 53 - + .../dt-bindings/gpio/tegra-gpio.h | 52 - + .../dt-bindings/gpio/tegra186-gpio.h | 57 - + .../dt-bindings/gpio/tegra194-gpio.h | 61 - + .../dt-bindings/gpio/uniphier-gpio.h | 18 - + .../include-prefixes/dt-bindings/i2c/i2c.h | 17 - + .../dt-bindings/iio/adc/at91-sama5d2_adc.h | 16 - + .../dt-bindings/iio/adc/fsl-imx25-gcq.h | 19 - + .../dt-bindings/iio/adc/ingenic,adc.h | 18 - + .../dt-bindings/iio/adi,ad5592r.h | 17 - + .../dt-bindings/iio/qcom,spmi-adc7-pm8350.h | 67 - + .../dt-bindings/iio/qcom,spmi-adc7-pm8350b.h | 88 - + .../dt-bindings/iio/qcom,spmi-adc7-pmk8350.h | 46 - + .../dt-bindings/iio/qcom,spmi-adc7-pmr735a.h | 28 - + .../dt-bindings/iio/qcom,spmi-adc7-pmr735b.h | 28 - + .../dt-bindings/iio/qcom,spmi-vadc.h | 300 - + .../iio/temperature/thermocouple.h | 16 - + .../dt-bindings/input/atmel-maxtouch.h | 10 - + .../dt-bindings/input/cros-ec-keyboard.h | 103 - + .../dt-bindings/input/gpio-keys.h | 13 - + .../dt-bindings/input/input.h | 18 - + .../dt-bindings/input/linux-event-codes.h | 952 --- + .../dt-bindings/input/ti-drv260x.h | 28 - + .../dt-bindings/interconnect/imx8mm.h | 50 - + .../dt-bindings/interconnect/imx8mn.h | 41 - + .../dt-bindings/interconnect/imx8mq.h | 48 - + .../dt-bindings/interconnect/qcom,icc.h | 26 - + .../dt-bindings/interconnect/qcom,msm8916.h | 100 - + .../dt-bindings/interconnect/qcom,msm8939.h | 105 - + .../dt-bindings/interconnect/qcom,msm8974.h | 146 - + .../dt-bindings/interconnect/qcom,osm-l3.h | 15 - + .../dt-bindings/interconnect/qcom,qcs404.h | 88 - + .../dt-bindings/interconnect/qcom,sc7180.h | 161 - + .../dt-bindings/interconnect/qcom,sc7280.h | 165 - + .../dt-bindings/interconnect/qcom,sc8180x.h | 185 - + .../dt-bindings/interconnect/qcom,sdm660.h | 116 - + .../dt-bindings/interconnect/qcom,sdm845.h | 150 - + .../dt-bindings/interconnect/qcom,sdx55.h | 76 - + .../dt-bindings/interconnect/qcom,sm8150.h | 162 - + .../dt-bindings/interconnect/qcom,sm8250.h | 172 - + .../dt-bindings/interconnect/qcom,sm8350.h | 172 - + .../interrupt-controller/apple-aic.h | 15 - + .../interrupt-controller/arm-gic.h | 23 - + .../interrupt-controller/aspeed-scu-ic.h | 23 - + .../dt-bindings/interrupt-controller/irq-st.h | 27 - + .../dt-bindings/interrupt-controller/irq.h | 20 - + .../interrupt-controller/mips-gic.h | 10 - + .../interrupt-controller/mvebu-icu.h | 16 - + .../dt-bindings/leds/common.h | 94 - + .../dt-bindings/leds/leds-netxbig.h | 18 - + .../dt-bindings/leds/leds-ns2.h | 9 - + .../dt-bindings/leds/leds-pca9532.h | 18 - + .../dt-bindings/leds/leds-pca955x.h | 16 - + .../dt-bindings/leds/rt4831-backlight.h | 23 - + .../dt-bindings/mailbox/pl320-mailbox.h | 14 - + .../dt-bindings/mailbox/qcom-ipcc.h | 34 - + .../dt-bindings/mailbox/tegra186-hsp.h | 36 - + .../dt-bindings/media/c8sectpfe.h | 13 - + .../dt-bindings/media/omap3-isp.h | 14 - + .../dt-bindings/media/tda1997x.h | 74 - + .../dt-bindings/media/tvp5150.h | 21 - + .../dt-bindings/media/xilinx-vip.h | 36 - + .../dt-bindings/memory/mt2701-larb-port.h | 77 - + .../dt-bindings/memory/mt2712-larb-port.h | 95 - + .../dt-bindings/memory/mt6779-larb-port.h | 206 - + .../dt-bindings/memory/mt8167-larb-port.h | 51 - + .../dt-bindings/memory/mt8173-larb-port.h | 99 - + .../dt-bindings/memory/mt8183-larb-port.h | 130 - + .../dt-bindings/memory/mt8192-larb-port.h | 243 - + .../dt-bindings/memory/mtk-memory-port.h | 15 - + .../dt-bindings/memory/tegra114-mc.h | 43 - + .../dt-bindings/memory/tegra124-mc.h | 125 - + .../dt-bindings/memory/tegra186-mc.h | 250 - + .../dt-bindings/memory/tegra194-mc.h | 410 - + .../dt-bindings/memory/tegra20-mc.h | 74 - + .../dt-bindings/memory/tegra210-mc.h | 78 - + .../dt-bindings/memory/tegra30-mc.h | 111 - + .../dt-bindings/mfd/arizona.h | 115 - + .../include-prefixes/dt-bindings/mfd/as3722.h | 53 - + .../dt-bindings/mfd/at91-usart.h | 17 - + .../dt-bindings/mfd/atmel-flexcom.h | 15 - + .../dt-bindings/mfd/dbx500-prcmu.h | 84 - + .../dt-bindings/mfd/max77620.h | 40 - + .../include-prefixes/dt-bindings/mfd/palmas.h | 19 - + .../dt-bindings/mfd/qcom-pm8008.h | 19 - + .../dt-bindings/mfd/qcom-rpm.h | 183 - + .../dt-bindings/mfd/st,stpmic1.h | 50 - + .../include-prefixes/dt-bindings/mfd/st-lpc.h | 17 - + .../dt-bindings/mfd/stm32f4-rcc.h | 109 - + .../dt-bindings/mfd/stm32f7-rcc.h | 114 - + .../dt-bindings/mfd/stm32h7-rcc.h | 136 - + .../dt-bindings/mips/lantiq_rcu_gphy.h | 13 - + .../include-prefixes/dt-bindings/mux/mux.h | 17 - + .../dt-bindings/mux/ti-serdes.h | 98 - + .../dt-bindings/net/microchip-lan78xx.h | 21 - + .../dt-bindings/net/mscc-phy-vsc8531.h | 31 - + .../dt-bindings/net/qca-ar803x.h | 13 - + .../dt-bindings/net/ti-dp83867.h | 53 - + .../dt-bindings/net/ti-dp83869.h | 42 - + .../dt-bindings/phy/phy-am654-serdes.h | 13 - + .../dt-bindings/phy/phy-cadence.h | 20 - + .../dt-bindings/phy/phy-lantiq-vrx200-pcie.h | 11 - + .../dt-bindings/phy/phy-ocelot-serdes.h | 12 - + .../dt-bindings/phy/phy-pistachio-usb.h | 13 - + .../dt-bindings/phy/phy-qcom-qusb2.h | 37 - + .../include-prefixes/dt-bindings/phy/phy-ti.h | 21 - + .../include-prefixes/dt-bindings/phy/phy.h | 26 - + .../dt-bindings/pinctrl/am33xx.h | 172 - + .../dt-bindings/pinctrl/am43xx.h | 55 - + .../dt-bindings/pinctrl/apple.h | 13 - + .../dt-bindings/pinctrl/at91.h | 49 - + .../dt-bindings/pinctrl/bcm2835.h | 26 - + .../pinctrl/brcm,pinctrl-stingray.h | 68 - + .../dt-bindings/pinctrl/dm814x.h | 49 - + .../dt-bindings/pinctrl/dra.h | 77 - + .../dt-bindings/pinctrl/hailo15_cpld.h | 25 - + .../dt-bindings/pinctrl/hisi.h | 74 - + .../dt-bindings/pinctrl/k210-fpioa.h | 276 - + .../include-prefixes/dt-bindings/pinctrl/k3.h | 41 - + .../dt-bindings/pinctrl/keystone.h | 39 - + .../dt-bindings/pinctrl/lochnagar.h | 132 - + .../dt-bindings/pinctrl/mt6397-pinfunc.h | 257 - + .../dt-bindings/pinctrl/mt65xx.h | 32 - + .../dt-bindings/pinctrl/mt6779-pinfunc.h | 1242 --- + .../dt-bindings/pinctrl/mt6797-pinfunc.h | 1368 ---- + .../dt-bindings/pinctrl/mt7623-pinfunc.h | 651 -- + .../dt-bindings/pinctrl/mt8135-pinfunc.h | 1294 ---- + .../dt-bindings/pinctrl/mt8183-pinfunc.h | 1120 --- + .../dt-bindings/pinctrl/mt8192-pinfunc.h | 1344 ---- + .../dt-bindings/pinctrl/mt8195-pinfunc.h | 962 --- + .../dt-bindings/pinctrl/mt8365-pinfunc.h | 858 --- + .../dt-bindings/pinctrl/nomadik.h | 36 - + .../dt-bindings/pinctrl/omap.h | 92 - + .../dt-bindings/pinctrl/pads-imx8dxl.h | 639 -- + .../dt-bindings/pinctrl/pads-imx8qm.h | 960 --- + .../dt-bindings/pinctrl/pads-imx8qxp.h | 751 -- + .../pinctrl/pinctrl-tegra-io-pad.h | 18 - + .../dt-bindings/pinctrl/pinctrl-tegra-xusb.h | 8 - + .../dt-bindings/pinctrl/pinctrl-tegra.h | 37 - + .../dt-bindings/pinctrl/pinctrl-zynq.h | 17 - + .../dt-bindings/pinctrl/pinctrl-zynqmp.h | 19 - + .../dt-bindings/pinctrl/qcom,pmic-gpio.h | 164 - + .../dt-bindings/pinctrl/qcom,pmic-mpp.h | 106 - + .../dt-bindings/pinctrl/r7s72100-pinctrl.h | 17 - + .../dt-bindings/pinctrl/r7s9210-pinctrl.h | 47 - + .../dt-bindings/pinctrl/rockchip.h | 47 - + .../dt-bindings/pinctrl/rzg2l-pinctrl.h | 23 - + .../dt-bindings/pinctrl/rzn1-pinctrl.h | 141 - + .../dt-bindings/pinctrl/samsung.h | 77 - + .../dt-bindings/pinctrl/stm32-pinfunc.h | 42 - + .../dt-bindings/pinctrl/sun4i-a10.h | 62 - + .../dt-bindings/pmu/exynos_ppmu.h | 25 - + .../dt-bindings/power/imx7-power.h | 13 - + .../dt-bindings/power/imx8mm-power.h | 22 - + .../dt-bindings/power/imx8mn-power.h | 15 - + .../dt-bindings/power/imx8mq-power.h | 21 - + .../dt-bindings/power/marvell,mmp2.h | 11 - + .../dt-bindings/power/meson-a1-power.h | 32 - + .../dt-bindings/power/meson-axg-power.h | 14 - + .../dt-bindings/power/meson-g12a-power.h | 13 - + .../dt-bindings/power/meson-gxbb-power.h | 13 - + .../dt-bindings/power/meson-sm1-power.h | 18 - + .../dt-bindings/power/meson8-power.h | 13 - + .../dt-bindings/power/mt2701-power.h | 19 - + .../dt-bindings/power/mt2712-power.h | 21 - + .../dt-bindings/power/mt6765-power.h | 14 - + .../dt-bindings/power/mt6797-power.h | 30 - + .../dt-bindings/power/mt7622-power.h | 14 - + .../dt-bindings/power/mt7623a-power.h | 10 - + .../dt-bindings/power/mt8167-power.h | 17 - + .../dt-bindings/power/mt8173-power.h | 16 - + .../dt-bindings/power/mt8183-power.h | 26 - + .../dt-bindings/power/mt8192-power.h | 32 - + .../dt-bindings/power/owl-s500-powergate.h | 19 - + .../dt-bindings/power/owl-s700-powergate.h | 19 - + .../dt-bindings/power/owl-s900-powergate.h | 23 - + .../dt-bindings/power/px30-power.h | 27 - + .../dt-bindings/power/qcom-aoss-qmp.h | 14 - + .../dt-bindings/power/qcom-rpmpd.h | 219 - + .../dt-bindings/power/r8a7742-sysc.h | 29 - + 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scripts/dtc/include-prefixes/powerpc/socrates.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/storcenter.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/stx_gp3_8560.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/stxssa8555.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/taishan.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/tqm5200.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/tqm8540.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/tqm8541.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/tqm8548-bigflash.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/tqm8548.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/tqm8555.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/tqm8560.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/tqm8xx.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/uc101.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/warp.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/wii.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/xcalibur1501.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/xpedite5200.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/xpedite5200_xmon.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/xpedite5301.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/xpedite5330.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/xpedite5370.dts + delete mode 100644 scripts/dtc/include-prefixes/powerpc/yosemite.dts + create mode 120000 scripts/dtc/include-prefixes/sh + delete mode 100644 scripts/dtc/include-prefixes/sh/Makefile + delete mode 100644 scripts/dtc/include-prefixes/sh/j2_mimas_v2.dts + create mode 120000 scripts/dtc/include-prefixes/xtensa + delete mode 100644 scripts/dtc/include-prefixes/xtensa/Makefile + delete mode 100644 scripts/dtc/include-prefixes/xtensa/csp.dts + delete mode 100644 scripts/dtc/include-prefixes/xtensa/kc705.dts + delete mode 100644 scripts/dtc/include-prefixes/xtensa/kc705_nommu.dts + delete mode 100644 scripts/dtc/include-prefixes/xtensa/lx200mx.dts + delete mode 100644 scripts/dtc/include-prefixes/xtensa/lx60.dts + delete mode 100644 scripts/dtc/include-prefixes/xtensa/ml605.dts + delete mode 100644 scripts/dtc/include-prefixes/xtensa/virt.dts + delete mode 100644 scripts/dtc/include-prefixes/xtensa/xtfpga-flash-128m.dtsi + delete mode 100644 scripts/dtc/include-prefixes/xtensa/xtfpga-flash-16m.dtsi + delete mode 100644 scripts/dtc/include-prefixes/xtensa/xtfpga-flash-4m.dtsi + delete mode 100644 scripts/dtc/include-prefixes/xtensa/xtfpga.dtsi + +diff --git a/scripts/dtc/include-prefixes/arc b/scripts/dtc/include-prefixes/arc +new file mode 120000 +index 000000000000..5d21b5a69a11 +--- /dev/null ++++ b/scripts/dtc/include-prefixes/arc +@@ -0,0 +1 @@ ++../../../arch/arc/boot/dts +\ No newline at end of file +diff --git a/scripts/dtc/include-prefixes/arc/Makefile b/scripts/dtc/include-prefixes/arc/Makefile +deleted file mode 100644 +index 8483a86c743d..000000000000 +--- a/scripts/dtc/include-prefixes/arc/Makefile ++++ /dev/null +@@ -1,17 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-# Built-in dtb +-builtindtb-y := nsim_700 +- +-ifneq ($(CONFIG_ARC_BUILTIN_DTB_NAME),"") +- builtindtb-y := $(patsubst "%",%,$(CONFIG_ARC_BUILTIN_DTB_NAME)) +-endif +- +-obj-y += $(builtindtb-y).dtb.o +-dtb-y := $(builtindtb-y).dtb +- +-# for CONFIG_OF_ALL_DTBS test +-dtstree := $(srctree)/$(src) +-dtb- := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts)) +- +-# board-specific dtc flags +-DTC_FLAGS_hsdk += --pad 20 +diff --git a/scripts/dtc/include-prefixes/arc/abilis_tb100.dtsi b/scripts/dtc/include-prefixes/arc/abilis_tb100.dtsi +deleted file mode 100644 +index 41026a3bfa37..000000000000 +--- a/scripts/dtc/include-prefixes/arc/abilis_tb100.dtsi ++++ /dev/null +@@ -1,336 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Abilis Systems TB100 SOC device tree +- * +- * Copyright (C) Abilis Systems 2013 +- * +- * Author: Christian Ruppert +- */ +- +-/include/ "abilis_tb10x.dtsi" +- +- +-/ { +- soc100 { +- bus-frequency = <166666666>; +- +- pll0: oscillator { +- clock-frequency = <1000000000>; +- }; +- cpu_clk: clkdiv_cpu { +- clock-mult = <1>; +- clock-div = <2>; +- }; +- ahb_clk: clkdiv_ahb { +- clock-mult = <1>; +- clock-div = <6>; +- }; +- +- iomux: iomux@ff10601c { +- /* Port 1 */ +- pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */ +- abilis,function = "mis0"; +- }; +- pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */ +- abilis,function = "mis1"; +- }; +- pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */ +- abilis,function = "gpioa"; +- }; +- pctl_tsin_p1: pctl-tsin-p1 { /* Parallel TS-in 1 */ +- abilis,function = "mip1"; +- }; +- /* Port 2 */ +- pctl_tsin_s2: pctl-tsin-s2 { /* Serial TS-in 2 */ +- abilis,function = "mis2"; +- }; +- pctl_tsin_s3: pctl-tsin-s3 { /* Serial TS-in 3 */ +- abilis,function = "mis3"; +- }; +- pctl_gpio_c: pctl-gpio-c { /* GPIO bank C */ +- abilis,function = "gpioc"; +- }; +- pctl_tsin_p3: pctl-tsin-p3 { /* Parallel TS-in 3 */ +- abilis,function = "mip3"; +- }; +- /* Port 3 */ +- pctl_tsin_s4: pctl-tsin-s4 { /* Serial TS-in 4 */ +- abilis,function = "mis4"; +- }; +- pctl_tsin_s5: pctl-tsin-s5 { /* Serial TS-in 5 */ +- abilis,function = "mis5"; +- }; +- pctl_gpio_e: pctl-gpio-e { /* GPIO bank E */ +- abilis,function = "gpioe"; +- }; +- pctl_tsin_p5: pctl-tsin-p5 { /* Parallel TS-in 5 */ +- abilis,function = "mip5"; +- }; +- /* Port 4 */ +- pctl_tsin_s6: pctl-tsin-s6 { /* Serial TS-in 6 */ +- abilis,function = "mis6"; +- }; +- pctl_tsin_s7: pctl-tsin-s7 { /* Serial TS-in 7 */ +- abilis,function = "mis7"; +- }; +- pctl_gpio_g: pctl-gpio-g { /* GPIO bank G */ +- abilis,function = "gpiog"; +- }; +- pctl_tsin_p7: pctl-tsin-p7 { /* Parallel TS-in 7 */ +- abilis,function = "mip7"; +- }; +- /* Port 5 */ +- pctl_gpio_j: pctl-gpio-j { /* GPIO bank J */ +- abilis,function = "gpioj"; +- }; +- pctl_gpio_k: pctl-gpio-k { /* GPIO bank K */ +- abilis,function = "gpiok"; +- }; +- pctl_ciplus: pctl-ciplus { /* CI+ interface */ +- abilis,function = "ciplus"; +- }; +- pctl_mcard: pctl-mcard { /* M-Card interface */ +- abilis,function = "mcard"; +- }; +- /* Port 6 */ +- pctl_tsout_p: pctl-tsout-p { /* Parallel TS-out */ +- abilis,function = "mop"; +- }; +- pctl_tsout_s0: pctl-tsout-s0 { /* Serial TS-out 0 */ +- abilis,function = "mos0"; +- }; +- pctl_tsout_s1: pctl-tsout-s1 { /* Serial TS-out 1 */ +- abilis,function = "mos1"; +- }; +- pctl_tsout_s2: pctl-tsout-s2 { /* Serial TS-out 2 */ +- abilis,function = "mos2"; +- }; +- pctl_tsout_s3: pctl-tsout-s3 { /* Serial TS-out 3 */ +- abilis,function = "mos3"; +- }; +- /* Port 7 */ +- pctl_uart0: pctl-uart0 { /* UART 0 */ +- abilis,function = "uart0"; +- }; +- pctl_uart1: pctl-uart1 { /* UART 1 */ +- abilis,function = "uart1"; +- }; +- pctl_gpio_l: pctl-gpio-l { /* GPIO bank L */ +- abilis,function = "gpiol"; +- }; +- pctl_gpio_m: pctl-gpio-m { /* GPIO bank M */ +- abilis,function = "gpiom"; +- }; +- /* Port 8 */ +- pctl_spi3: pctl-spi3 { +- abilis,function = "spi3"; +- }; +- /* Port 9 */ +- pctl_spi1: pctl-spi1 { +- abilis,function = "spi1"; +- }; +- pctl_gpio_n: pctl-gpio-n { +- abilis,function = "gpion"; +- }; +- /* Unmuxed GPIOs */ +- pctl_gpio_b: pctl-gpio-b { +- abilis,function = "gpiob"; +- }; +- pctl_gpio_d: pctl-gpio-d { +- abilis,function = "gpiod"; +- }; +- pctl_gpio_f: pctl-gpio-f { +- abilis,function = "gpiof"; +- }; +- pctl_gpio_h: pctl-gpio-h { +- abilis,function = "gpioh"; +- }; +- pctl_gpio_i: pctl-gpio-i { +- abilis,function = "gpioi"; +- }; +- }; +- +- gpioa: gpio@ff140000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff140000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <3>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpioa"; +- }; +- gpiob: gpio@ff141000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff141000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <2>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpiob"; +- }; +- gpioc: gpio@ff142000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff142000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <3>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpioc"; +- }; +- gpiod: gpio@ff143000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff143000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <2>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpiod"; +- }; +- gpioe: gpio@ff144000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff144000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <3>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpioe"; +- }; +- gpiof: gpio@ff145000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff145000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <2>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpiof"; +- }; +- gpiog: gpio@ff146000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff146000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <3>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpiog"; +- }; +- gpioh: gpio@ff147000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff147000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <2>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpioh"; +- }; +- gpioi: gpio@ff148000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff148000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <12>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpioi"; +- }; +- gpioj: gpio@ff149000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff149000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <32>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpioj"; +- }; +- gpiok: gpio@ff14a000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff14a000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <22>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpiok"; +- }; +- gpiol: gpio@ff14b000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff14b000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <4>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpiol"; +- }; +- gpiom: gpio@ff14c000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff14c000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <4>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpiom"; +- }; +- gpion: gpio@ff14d000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff14d000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <5>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpion"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/abilis_tb100_dvk.dts b/scripts/dtc/include-prefixes/arc/abilis_tb100_dvk.dts +deleted file mode 100644 +index 6d346de5e359..000000000000 +--- a/scripts/dtc/include-prefixes/arc/abilis_tb100_dvk.dts ++++ /dev/null +@@ -1,116 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Abilis Systems TB100 Development Kit PCB device tree +- * +- * Copyright (C) Abilis Systems 2013 +- * +- * Author: Christian Ruppert +- */ +- +-/dts-v1/; +- +-/include/ "abilis_tb100.dtsi" +- +-/ { +- model = "abilis,tb100"; +- chosen { +- bootargs = "earlycon=uart8250,mmio32,0xff100000,9600n8 console=ttyS0,9600n8"; +- }; +- +- aliases { }; +- +- memory { +- device_type = "memory"; +- reg = <0x80000000 0x08000000>; /* 128M */ +- }; +- +- soc100 { +- uart@ff100000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pctl_uart0>; +- }; +- ethernet@fe100000 { +- phy-mode = "rgmii"; +- }; +- +- i2c0: i2c@ff120000 { +- i2c-sda-hold-time-ns = <432>; +- }; +- i2c1: i2c@ff121000 { +- i2c-sda-hold-time-ns = <432>; +- }; +- i2c2: i2c@ff122000 { +- i2c-sda-hold-time-ns = <432>; +- }; +- i2c3: i2c@ff123000 { +- i2c-sda-hold-time-ns = <432>; +- }; +- i2c4: i2c@ff124000 { +- i2c-sda-hold-time-ns = <432>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- power { +- label = "Power"; +- gpios = <&gpioi 0 0>; +- linux,default-trigger = "default-on"; +- }; +- heartbeat { +- label = "Heartbeat"; +- gpios = <&gpioi 1 0>; +- linux,default-trigger = "heartbeat"; +- }; +- led2 { +- label = "LED2"; +- gpios = <&gpioi 2 0>; +- default-state = "off"; +- }; +- led3 { +- label = "LED3"; +- gpios = <&gpioi 3 0>; +- default-state = "off"; +- }; +- led4 { +- label = "LED4"; +- gpios = <&gpioi 4 0>; +- default-state = "off"; +- }; +- led5 { +- label = "LED5"; +- gpios = <&gpioi 5 0>; +- default-state = "off"; +- }; +- led6 { +- label = "LED6"; +- gpios = <&gpioi 6 0>; +- default-state = "off"; +- }; +- led7 { +- label = "LED7"; +- gpios = <&gpioi 7 0>; +- default-state = "off"; +- }; +- led8 { +- label = "LED8"; +- gpios = <&gpioi 8 0>; +- default-state = "off"; +- }; +- led9 { +- label = "LED9"; +- gpios = <&gpioi 9 0>; +- default-state = "off"; +- }; +- led10 { +- label = "LED10"; +- gpios = <&gpioi 10 0>; +- default-state = "off"; +- }; +- led11 { +- label = "LED11"; +- gpios = <&gpioi 11 0>; +- default-state = "off"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/abilis_tb101.dtsi b/scripts/dtc/include-prefixes/arc/abilis_tb101.dtsi +deleted file mode 100644 +index 041ab1ba0221..000000000000 +--- a/scripts/dtc/include-prefixes/arc/abilis_tb101.dtsi ++++ /dev/null +@@ -1,345 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Abilis Systems TB101 SOC device tree +- * +- * Copyright (C) Abilis Systems 2013 +- * +- * Author: Christian Ruppert +- */ +- +-/include/ "abilis_tb10x.dtsi" +- +- +-/ { +- soc100 { +- bus-frequency = <166666666>; +- +- pll0: oscillator { +- clock-frequency = <1000000000>; +- }; +- cpu_clk: clkdiv_cpu { +- clock-mult = <1>; +- clock-div = <2>; +- }; +- ahb_clk: clkdiv_ahb { +- clock-mult = <1>; +- clock-div = <6>; +- }; +- +- iomux: iomux@ff10601c { +- /* Port 1 */ +- pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */ +- abilis,function = "mis0"; +- }; +- pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */ +- abilis,function = "mis1"; +- }; +- pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */ +- abilis,function = "gpioa"; +- }; +- pctl_tsin_p1: pctl-tsin-p1 { /* Parallel TS-in 1 */ +- abilis,function = "mip1"; +- }; +- /* Port 2 */ +- pctl_tsin_s2: pctl-tsin-s2 { /* Serial TS-in 2 */ +- abilis,function = "mis2"; +- }; +- pctl_tsin_s3: pctl-tsin-s3 { /* Serial TS-in 3 */ +- abilis,function = "mis3"; +- }; +- pctl_gpio_c: pctl-gpio-c { /* GPIO bank C */ +- abilis,function = "gpioc"; +- }; +- pctl_tsin_p3: pctl-tsin-p3 { /* Parallel TS-in 3 */ +- abilis,function = "mip3"; +- }; +- /* Port 3 */ +- pctl_tsin_s4: pctl-tsin-s4 { /* Serial TS-in 4 */ +- abilis,function = "mis4"; +- }; +- pctl_tsin_s5: pctl-tsin-s5 { /* Serial TS-in 5 */ +- abilis,function = "mis5"; +- }; +- pctl_gpio_e: pctl-gpio-e { /* GPIO bank E */ +- abilis,function = "gpioe"; +- }; +- pctl_tsin_p5: pctl-tsin-p5 { /* Parallel TS-in 5 */ +- abilis,function = "mip5"; +- }; +- /* Port 4 */ +- pctl_tsin_s6: pctl-tsin-s6 { /* Serial TS-in 6 */ +- abilis,function = "mis6"; +- }; +- pctl_tsin_s7: pctl-tsin-s7 { /* Serial TS-in 7 */ +- abilis,function = "mis7"; +- }; +- pctl_gpio_g: pctl-gpio-g { /* GPIO bank G */ +- abilis,function = "gpiog"; +- }; +- pctl_tsin_p7: pctl-tsin-p7 { /* Parallel TS-in 7 */ +- abilis,function = "mip7"; +- }; +- /* Port 5 */ +- pctl_gpio_j: pctl-gpio-j { /* GPIO bank J */ +- abilis,function = "gpioj"; +- }; +- pctl_gpio_k: pctl-gpio-k { /* GPIO bank K */ +- abilis,function = "gpiok"; +- }; +- pctl_ciplus: pctl-ciplus { /* CI+ interface */ +- abilis,function = "ciplus"; +- }; +- pctl_mcard: pctl-mcard { /* M-Card interface */ +- abilis,function = "mcard"; +- }; +- pctl_stc0: pctl-stc0 { /* Smart card I/F 0 */ +- abilis,function = "stc0"; +- }; +- pctl_stc1: pctl-stc1 { /* Smart card I/F 1 */ +- abilis,function = "stc1"; +- }; +- /* Port 6 */ +- pctl_tsout_p: pctl-tsout-p { /* Parallel TS-out */ +- abilis,function = "mop"; +- }; +- pctl_tsout_s0: pctl-tsout-s0 { /* Serial TS-out 0 */ +- abilis,function = "mos0"; +- }; +- pctl_tsout_s1: pctl-tsout-s1 { /* Serial TS-out 1 */ +- abilis,function = "mos1"; +- }; +- pctl_tsout_s2: pctl-tsout-s2 { /* Serial TS-out 2 */ +- abilis,function = "mos2"; +- }; +- pctl_tsout_s3: pctl-tsout-s3 { /* Serial TS-out 3 */ +- abilis,function = "mos3"; +- }; +- /* Port 7 */ +- pctl_uart0: pctl-uart0 { /* UART 0 */ +- abilis,function = "uart0"; +- }; +- pctl_uart1: pctl-uart1 { /* UART 1 */ +- abilis,function = "uart1"; +- }; +- pctl_gpio_l: pctl-gpio-l { /* GPIO bank L */ +- abilis,function = "gpiol"; +- }; +- pctl_gpio_m: pctl-gpio-m { /* GPIO bank M */ +- abilis,function = "gpiom"; +- }; +- /* Port 8 */ +- pctl_spi3: pctl-spi3 { +- abilis,function = "spi3"; +- }; +- pctl_jtag: pctl-jtag { +- abilis,function = "jtag"; +- }; +- /* Port 9 */ +- pctl_spi1: pctl-spi1 { +- abilis,function = "spi1"; +- }; +- pctl_gpio_n: pctl-gpio-n { +- abilis,function = "gpion"; +- }; +- /* Unmuxed GPIOs */ +- pctl_gpio_b: pctl-gpio-b { +- abilis,function = "gpiob"; +- }; +- pctl_gpio_d: pctl-gpio-d { +- abilis,function = "gpiod"; +- }; +- pctl_gpio_f: pctl-gpio-f { +- abilis,function = "gpiof"; +- }; +- pctl_gpio_h: pctl-gpio-h { +- abilis,function = "gpioh"; +- }; +- pctl_gpio_i: pctl-gpio-i { +- abilis,function = "gpioi"; +- }; +- }; +- +- gpioa: gpio@ff140000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff140000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <3>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpioa"; +- }; +- gpiob: gpio@ff141000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff141000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <2>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpiob"; +- }; +- gpioc: gpio@ff142000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff142000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <3>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpioc"; +- }; +- gpiod: gpio@ff143000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff143000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <2>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpiod"; +- }; +- gpioe: gpio@ff144000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff144000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <3>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpioe"; +- }; +- gpiof: gpio@ff145000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff145000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <2>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpiof"; +- }; +- gpiog: gpio@ff146000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff146000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <3>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpiog"; +- }; +- gpioh: gpio@ff147000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff147000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <2>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpioh"; +- }; +- gpioi: gpio@ff148000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff148000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <12>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpioi"; +- }; +- gpioj: gpio@ff149000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff149000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <32>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpioj"; +- }; +- gpiok: gpio@ff14a000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff14a000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <22>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpiok"; +- }; +- gpiol: gpio@ff14b000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff14b000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <4>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpiol"; +- }; +- gpiom: gpio@ff14c000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff14c000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <4>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpiom"; +- }; +- gpion: gpio@ff14d000 { +- compatible = "abilis,tb10x-gpio"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <27 2>; +- reg = <0xff14d000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- abilis,ngpio = <5>; +- gpio-ranges = <&iomux 0 0 0>; +- gpio-ranges-group-names = "gpion"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/abilis_tb101_dvk.dts b/scripts/dtc/include-prefixes/arc/abilis_tb101_dvk.dts +deleted file mode 100644 +index d11b790f8bd6..000000000000 +--- a/scripts/dtc/include-prefixes/arc/abilis_tb101_dvk.dts ++++ /dev/null +@@ -1,116 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Abilis Systems TB101 Development Kit PCB device tree +- * +- * Copyright (C) Abilis Systems 2013 +- * +- * Author: Christian Ruppert +- */ +- +-/dts-v1/; +- +-/include/ "abilis_tb101.dtsi" +- +-/ { +- model = "abilis,tb101"; +- chosen { +- bootargs = "earlycon=uart8250,mmio32,0xff100000,9600n8 console=ttyS0,9600n8"; +- }; +- +- aliases { }; +- +- memory { +- device_type = "memory"; +- reg = <0x80000000 0x08000000>; /* 128M */ +- }; +- +- soc100 { +- uart@ff100000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pctl_uart0>; +- }; +- ethernet@fe100000 { +- phy-mode = "rgmii"; +- }; +- +- i2c0: i2c@ff120000 { +- i2c-sda-hold-time-ns = <432>; +- }; +- i2c1: i2c@ff121000 { +- i2c-sda-hold-time-ns = <432>; +- }; +- i2c2: i2c@ff122000 { +- i2c-sda-hold-time-ns = <432>; +- }; +- i2c3: i2c@ff123000 { +- i2c-sda-hold-time-ns = <432>; +- }; +- i2c4: i2c@ff124000 { +- i2c-sda-hold-time-ns = <432>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- power { +- label = "Power"; +- gpios = <&gpioi 0 0>; +- linux,default-trigger = "default-on"; +- }; +- heartbeat { +- label = "Heartbeat"; +- gpios = <&gpioi 1 0>; +- linux,default-trigger = "heartbeat"; +- }; +- led2 { +- label = "LED2"; +- gpios = <&gpioi 2 0>; +- default-state = "off"; +- }; +- led3 { +- label = "LED3"; +- gpios = <&gpioi 3 0>; +- default-state = "off"; +- }; +- led4 { +- label = "LED4"; +- gpios = <&gpioi 4 0>; +- default-state = "off"; +- }; +- led5 { +- label = "LED5"; +- gpios = <&gpioi 5 0>; +- default-state = "off"; +- }; +- led6 { +- label = "LED6"; +- gpios = <&gpioi 6 0>; +- default-state = "off"; +- }; +- led7 { +- label = "LED7"; +- gpios = <&gpioi 7 0>; +- default-state = "off"; +- }; +- led8 { +- label = "LED8"; +- gpios = <&gpioi 8 0>; +- default-state = "off"; +- }; +- led9 { +- label = "LED9"; +- gpios = <&gpioi 9 0>; +- default-state = "off"; +- }; +- led10 { +- label = "LED10"; +- gpios = <&gpioi 10 0>; +- default-state = "off"; +- }; +- led11 { +- label = "LED11"; +- gpios = <&gpioi 11 0>; +- default-state = "off"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/abilis_tb10x.dtsi b/scripts/dtc/include-prefixes/arc/abilis_tb10x.dtsi +deleted file mode 100644 +index aa62619f213d..000000000000 +--- a/scripts/dtc/include-prefixes/arc/abilis_tb10x.dtsi ++++ /dev/null +@@ -1,243 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Abilis Systems TB10X SOC device tree +- * +- * Copyright (C) Abilis Systems 2013 +- * +- * Author: Christian Ruppert +- */ +- +- +-/ { +- compatible = "abilis,arc-tb10x"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- device_type = "cpu"; +- compatible = "snps,arc770d"; +- reg = <0>; +- }; +- }; +- +- /* TIMER0 with interrupt for clockevent */ +- timer0 { +- compatible = "snps,arc-timer"; +- interrupts = <3>; +- interrupt-parent = <&intc>; +- clocks = <&cpu_clk>; +- }; +- +- /* TIMER1 for free running clocksource */ +- timer1 { +- compatible = "snps,arc-timer"; +- clocks = <&cpu_clk>; +- }; +- +- soc100 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- ranges = <0xfe000000 0xfe000000 0x02000000 +- 0x000f0000 0x000f0000 0x00010000>; +- compatible = "abilis,tb10x", "simple-bus"; +- +- pll0: oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-output-names = "pll0"; +- }; +- cpu_clk: clkdiv_cpu { +- compatible = "fixed-factor-clock"; +- #clock-cells = <0>; +- clocks = <&pll0>; +- clock-output-names = "cpu_clk"; +- }; +- ahb_clk: clkdiv_ahb { +- compatible = "fixed-factor-clock"; +- #clock-cells = <0>; +- clocks = <&pll0>; +- clock-output-names = "ahb_clk"; +- }; +- +- iomux: iomux@ff10601c { +- compatible = "abilis,tb10x-iomux"; +- #gpio-range-cells = <3>; +- reg = <0xff10601c 0x4>; +- }; +- +- intc: interrupt-controller { +- compatible = "snps,arc700-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- tb10x_ictl: pic@fe002000 { +- compatible = "abilis,tb10x-ictl"; +- reg = <0xfe002000 0x20>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupt-parent = <&intc>; +- interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 30 31>; +- }; +- +- uart@ff100000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0xff100000 0x100>; +- clock-frequency = <166666666>; +- interrupts = <25 8>; +- reg-shift = <2>; +- reg-io-width = <4>; +- interrupt-parent = <&tb10x_ictl>; +- }; +- ethernet@fe100000 { +- compatible = "snps,dwmac-3.70a","snps,dwmac"; +- reg = <0xfe100000 0x1058>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <6 8>; +- interrupt-names = "macirq"; +- clocks = <&ahb_clk>; +- clock-names = "stmmaceth"; +- }; +- dma@fe000000 { +- compatible = "snps,dma-spear1340"; +- reg = <0xfe000000 0x400>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <14 8>; +- dma-channels = <6>; +- dma-requests = <0>; +- dma-masters = <1>; +- #dma-cells = <3>; +- chan_allocation_order = <0>; +- chan_priority = <1>; +- block_size = <0x7ff>; +- data-width = <4>; +- clocks = <&ahb_clk>; +- clock-names = "hclk"; +- multi-block = <1 1 1 1 1 1>; +- }; +- +- i2c0: i2c@ff120000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xff120000 0x1000>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <12 8>; +- clocks = <&ahb_clk>; +- }; +- i2c1: i2c@ff121000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xff121000 0x1000>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <12 8>; +- clocks = <&ahb_clk>; +- }; +- i2c2: i2c@ff122000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xff122000 0x1000>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <12 8>; +- clocks = <&ahb_clk>; +- }; +- i2c3: i2c@ff123000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xff123000 0x1000>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <12 8>; +- clocks = <&ahb_clk>; +- }; +- i2c4: i2c@ff124000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xff124000 0x1000>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <12 8>; +- clocks = <&ahb_clk>; +- }; +- +- spi0: spi@fe010000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "abilis,tb100-spi"; +- num-cs = <1>; +- reg = <0xfe010000 0x20>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <26 8>; +- clocks = <&ahb_clk>; +- }; +- spi1: spi@fe011000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "abilis,tb100-spi"; +- num-cs = <2>; +- reg = <0xfe011000 0x20>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <10 8>; +- clocks = <&ahb_clk>; +- }; +- +- tb10x_tsm: tb10x-tsm@ff316000 { +- compatible = "abilis,tb100-tsm"; +- reg = <0xff316000 0x400>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <17 8>; +- output-clkdiv = <4>; +- global-packet-delay = <0x21>; +- port-packet-delay = <0>; +- }; +- tb10x_stream_proc: tb10x-stream-proc { +- compatible = "abilis,tb100-streamproc"; +- reg = <0xfff00000 0x200>, +- <0x000f0000 0x10000>, +- <0xfff00200 0x105>, +- <0xff10600c 0x1>, +- <0xfe001018 0x1>; +- reg-names = "mbox", +- "sp_iccm", +- "mbox_irq", +- "cpuctrl", +- "a6it_int_force"; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <20 2>, <19 2>; +- interrupt-names = "cmd_irq", "event_irq"; +- }; +- tb10x_mdsc0: tb10x-mdscr@ff300000 { +- compatible = "abilis,tb100-mdscr"; +- reg = <0xff300000 0x7000>; +- tb100-mdscr-manage-tsin; +- }; +- tb10x_mscr0: tb10x-mdscr@ff307000 { +- compatible = "abilis,tb100-mdscr"; +- reg = <0xff307000 0x7000>; +- }; +- tb10x_scr0: tb10x-mdscr@ff30e000 { +- compatible = "abilis,tb100-mdscr"; +- reg = <0xff30e000 0x4000>; +- tb100-mdscr-manage-tsin; +- }; +- tb10x_scr1: tb10x-mdscr@ff312000 { +- compatible = "abilis,tb100-mdscr"; +- reg = <0xff312000 0x4000>; +- tb100-mdscr-manage-tsin; +- }; +- tb10x_wfb: tb10x-wfb@ff319000 { +- compatible = "abilis,tb100-wfb"; +- reg = <0xff319000 0x1000>; +- interrupt-parent = <&tb10x_ictl>; +- interrupts = <16 8>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/axc001.dtsi b/scripts/dtc/include-prefixes/arc/axc001.dtsi +deleted file mode 100644 +index 2a151607b080..000000000000 +--- a/scripts/dtc/include-prefixes/arc/axc001.dtsi ++++ /dev/null +@@ -1,126 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) +- */ +- +-/* +- * Device tree for AXC001 770D/EM6/AS221 CPU card +- * Note that this file only supports the 770D CPU +- */ +- +-/include/ "skeleton.dtsi" +- +-/ { +- compatible = "snps,arc"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpu_card { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0x00000000 0x0 0xf0000000 0x10000000>; +- +- core_clk: core_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <750000000>; +- }; +- +- input_clk: input-clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <33333333>; +- }; +- +- core_intc: arc700-intc@cpu { +- compatible = "snps,arc700-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- /* +- * this GPIO block ORs all interrupts on CPU card (creg,..) +- * to uplink only 1 IRQ to ARC core intc +- */ +- dw-apb-gpio@2000 { +- compatible = "snps,dw-apb-gpio"; +- reg = < 0x2000 0x80 >; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ictl_intc: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <30>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupt-parent = <&core_intc>; +- interrupts = <15>; +- }; +- }; +- +- debug_uart: dw-apb-uart@5000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x5000 0x100>; +- clock-frequency = <33333000>; +- interrupt-parent = <&ictl_intc>; +- interrupts = <19 4>; +- baud = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- arcpct0: pct { +- compatible = "snps,arc700-pct"; +- }; +- }; +- +- /* +- * This INTC is actually connected to DW APB GPIO +- * which acts as a wire between MB INTC and CPU INTC. +- * GPIO INTC is configured in platform init code +- * and here we mimic direct connection from MB INTC to +- * CPU INTC, thus we set "interrupts = <7>" instead of +- * "interrupts = <12>" +- * +- * This intc actually resides on MB, but we move it here to +- * avoid duplicating the MB dtsi file given that IRQ from +- * this intc to cpu intc are different for axs101 and axs103 +- */ +- mb_intc: interrupt-controller@e0012000 { +- #interrupt-cells = <1>; +- compatible = "snps,dw-apb-ictl"; +- reg = < 0x0 0xe0012000 0x0 0x200 >; +- interrupt-controller; +- interrupt-parent = <&core_intc>; +- interrupts = < 7 >; +- }; +- +- memory { +- device_type = "memory"; +- /* CONFIG_LINUX_RAM_BASE needs to match low mem start */ +- reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */ +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- /* +- * We just move frame buffer area to the very end of +- * available DDR. And even though in case of ARC770 there's +- * no strict requirement for a frame-buffer to be in any +- * particular location it allows us to use the same +- * base board's DT node for ARC PGU as for ARc HS38. +- */ +- frame_buffer: frame_buffer@9e000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x9e000000 0x0 0x2000000>; +- no-map; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/axc003.dtsi b/scripts/dtc/include-prefixes/arc/axc003.dtsi +deleted file mode 100644 +index cd1edcf4f95e..000000000000 +--- a/scripts/dtc/include-prefixes/arc/axc003.dtsi ++++ /dev/null +@@ -1,161 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) +- */ +- +-/* +- * Device tree for AXC003 CPU card: HS38x UP configuration +- */ +- +-/include/ "skeleton_hs.dtsi" +- +-/ { +- compatible = "snps,arc"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpu_card { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0x00000000 0x0 0xf0000000 0x10000000>; +- +- input_clk: input-clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <33333333>; +- }; +- +- core_clk: core-clk@80 { +- compatible = "snps,axs10x-arc-pll-clock"; +- reg = <0x80 0x10>, <0x100 0x10>; +- #clock-cells = <0>; +- clocks = <&input_clk>; +- +- /* +- * Set initial core pll output frequency to 90MHz. +- * It will be applied at the core pll driver probing +- * on early boot. +- */ +- assigned-clocks = <&core_clk>; +- assigned-clock-rates = <90000000>; +- }; +- +- core_intc: archs-intc@cpu { +- compatible = "snps,archs-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- /* +- * this GPIO block ORs all interrupts on CPU card (creg,..) +- * to uplink only 1 IRQ to ARC core intc +- */ +- dw-apb-gpio@2000 { +- compatible = "snps,dw-apb-gpio"; +- reg = < 0x2000 0x80 >; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ictl_intc: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <30>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupt-parent = <&core_intc>; +- interrupts = <25>; +- }; +- }; +- +- debug_uart: dw-apb-uart@5000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x5000 0x100>; +- clock-frequency = <33333000>; +- interrupt-parent = <&ictl_intc>; +- interrupts = <2 4>; +- baud = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- arcpct0: pct { +- compatible = "snps,archs-pct"; +- #interrupt-cells = <1>; +- interrupt-parent = <&core_intc>; +- interrupts = <20>; +- }; +- }; +- +- /* +- * Mark DMA peripherals connected via IOC port as dma-coherent. We do +- * it via overlay because peripherals defined in axs10x_mb.dtsi are +- * used for both AXS101 and AXS103 boards and only AXS103 has IOC (so +- * only AXS103 board has HW-coherent DMA peripherals) +- * We don't need to mark pgu@17000 as dma-coherent because it uses +- * external DMA buffer located outside of IOC aperture. +- */ +- axs10x_mb { +- ethernet@18000 { +- dma-coherent; +- }; +- +- ehci@40000 { +- dma-coherent; +- }; +- +- ohci@60000 { +- dma-coherent; +- }; +- +- mmc@15000 { +- dma-coherent; +- }; +- }; +- +- /* +- * The DW APB ICTL intc on MB is connected to CPU intc via a +- * DT "invisible" DW APB GPIO block, configured to simply pass thru +- * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c) +- * +- * So here we mimic a direct connection betwen them, ignoring the +- * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core) +- * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO) +- * +- * This intc actually resides on MB, but we move it here to +- * avoid duplicating the MB dtsi file given that IRQ from +- * this intc to cpu intc are different for axs101 and axs103 +- */ +- mb_intc: interrupt-controller@e0012000 { +- #interrupt-cells = <1>; +- compatible = "snps,dw-apb-ictl"; +- reg = < 0x0 0xe0012000 0x0 0x200 >; +- interrupt-controller; +- interrupt-parent = <&core_intc>; +- interrupts = < 24 >; +- }; +- +- memory { +- device_type = "memory"; +- /* CONFIG_LINUX_RAM_BASE needs to match low mem start */ +- reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */ +- 0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */ +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- /* +- * Move frame buffer out of IOC aperture (0x8z-0xaz). +- */ +- frame_buffer: frame_buffer@be000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0xbe000000 0x0 0x2000000>; +- no-map; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/axc003_idu.dtsi b/scripts/dtc/include-prefixes/arc/axc003_idu.dtsi +deleted file mode 100644 +index 70779386ca79..000000000000 +--- a/scripts/dtc/include-prefixes/arc/axc003_idu.dtsi ++++ /dev/null +@@ -1,167 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com) +- */ +- +-/* +- * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc +- */ +- +-/include/ "skeleton_hs_idu.dtsi" +- +-/ { +- compatible = "snps,arc"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpu_card { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0x00000000 0x0 0xf0000000 0x10000000>; +- +- input_clk: input-clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <33333333>; +- }; +- +- core_clk: core-clk@80 { +- compatible = "snps,axs10x-arc-pll-clock"; +- reg = <0x80 0x10>, <0x100 0x10>; +- #clock-cells = <0>; +- clocks = <&input_clk>; +- +- /* +- * Set initial core pll output frequency to 100MHz. +- * It will be applied at the core pll driver probing +- * on early boot. +- */ +- assigned-clocks = <&core_clk>; +- assigned-clock-rates = <100000000>; +- }; +- +- core_intc: archs-intc@cpu { +- compatible = "snps,archs-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- idu_intc: idu-interrupt-controller { +- compatible = "snps,archs-idu-intc"; +- interrupt-controller; +- interrupt-parent = <&core_intc>; +- #interrupt-cells = <1>; +- }; +- +- /* +- * this GPIO block ORs all interrupts on CPU card (creg,..) +- * to uplink only 1 IRQ to ARC core intc +- */ +- dw-apb-gpio@2000 { +- compatible = "snps,dw-apb-gpio"; +- reg = < 0x2000 0x80 >; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ictl_intc: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <30>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupt-parent = <&idu_intc>; +- interrupts = <1>; +- }; +- }; +- +- debug_uart: dw-apb-uart@5000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x5000 0x100>; +- clock-frequency = <33333000>; +- interrupt-parent = <&ictl_intc>; +- interrupts = <2 4>; +- baud = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- arcpct0: pct { +- compatible = "snps,archs-pct"; +- #interrupt-cells = <1>; +- interrupt-parent = <&core_intc>; +- interrupts = <20>; +- }; +- }; +- +- /* +- * Mark DMA peripherals connected via IOC port as dma-coherent. We do +- * it via overlay because peripherals defined in axs10x_mb.dtsi are +- * used for both AXS101 and AXS103 boards and only AXS103 has IOC (so +- * only AXS103 board has HW-coherent DMA peripherals) +- * We don't need to mark pgu@17000 as dma-coherent because it uses +- * external DMA buffer located outside of IOC aperture. +- */ +- axs10x_mb { +- ethernet@18000 { +- dma-coherent; +- }; +- +- ehci@40000 { +- dma-coherent; +- }; +- +- ohci@60000 { +- dma-coherent; +- }; +- +- mmc@15000 { +- dma-coherent; +- }; +- }; +- +- /* +- * This INTC is actually connected to DW APB GPIO +- * which acts as a wire between MB INTC and CPU INTC. +- * GPIO INTC is configured in platform init code +- * and here we mimic direct connection from MB INTC to +- * CPU INTC, thus we set "interrupts = <0 1>" instead of +- * "interrupts = <12>" +- * +- * This intc actually resides on MB, but we move it here to +- * avoid duplicating the MB dtsi file given that IRQ from +- * this intc to cpu intc are different for axs101 and axs103 +- */ +- mb_intc: interrupt-controller@e0012000 { +- #interrupt-cells = <1>; +- compatible = "snps,dw-apb-ictl"; +- reg = < 0x0 0xe0012000 0x0 0x200 >; +- interrupt-controller; +- interrupt-parent = <&idu_intc>; +- interrupts = <0>; +- }; +- +- memory { +- device_type = "memory"; +- /* CONFIG_LINUX_RAM_BASE needs to match low mem start */ +- reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */ +- 0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */ +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- /* +- * Move frame buffer out of IOC aperture (0x8z-0xaz). +- */ +- frame_buffer: frame_buffer@be000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0xbe000000 0x0 0x2000000>; +- no-map; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/axs101.dts b/scripts/dtc/include-prefixes/arc/axs101.dts +deleted file mode 100644 +index c4cfc5f4f427..000000000000 +--- a/scripts/dtc/include-prefixes/arc/axs101.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) +- * +- * ARC AXS101 S/W development platform +- */ +-/dts-v1/; +- +-/include/ "axc001.dtsi" +-/include/ "axs10x_mb.dtsi" +- +-/ { +- model = "snps,axs101"; +- compatible = "snps,axs101", "snps,arc-sdp"; +- +- chosen { +- bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0 print-fatal-signals=1"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/axs103.dts b/scripts/dtc/include-prefixes/arc/axs103.dts +deleted file mode 100644 +index 16ccb7ba7a00..000000000000 +--- a/scripts/dtc/include-prefixes/arc/axs103.dts ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) +- */ +- +-/* +- * Device Tree for AXS103 SDP with AXS10X Main Board and +- * AXC003 FPGA Card (with UP bitfile) +- */ +-/dts-v1/; +- +-/include/ "axc003.dtsi" +-/include/ "axs10x_mb.dtsi" +- +-/ { +- model = "snps,axs103"; +- compatible = "snps,axs103", "snps,arc-sdp"; +- +- chosen { +- bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=ttyS3,115200n8 debug print-fatal-signals=1"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/axs103_idu.dts b/scripts/dtc/include-prefixes/arc/axs103_idu.dts +deleted file mode 100644 +index a934b92a8c30..000000000000 +--- a/scripts/dtc/include-prefixes/arc/axs103_idu.dts ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) +- */ +- +-/* +- * Device Tree for AXS103 SDP with AXS10X Main Board and +- * AXC003 FPGA Card (with SMP bitfile) +- */ +-/dts-v1/; +- +-/include/ "axc003_idu.dtsi" +-/include/ "axs10x_mb.dtsi" +- +-/ { +- model = "snps,axs103-smp"; +- compatible = "snps,axs103", "snps,arc-sdp"; +- +- chosen { +- bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 print-fatal-signals=1 consoleblank=0"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/axs10x_mb.dtsi b/scripts/dtc/include-prefixes/arc/axs10x_mb.dtsi +deleted file mode 100644 +index 99d3e7175bf7..000000000000 +--- a/scripts/dtc/include-prefixes/arc/axs10x_mb.dtsi ++++ /dev/null +@@ -1,330 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Support for peripherals on the AXS10x mainboard +- * +- * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) +- */ +- +-/ { +- aliases { +- ethernet = &gmac; +- }; +- +- axs10x_mb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x0 0xe0000000 0x10000000>; +- interrupt-parent = <&mb_intc>; +- +- creg_rst: reset-controller@11220 { +- compatible = "snps,axs10x-reset"; +- #reset-cells = <1>; +- reg = <0x11220 0x4>; +- }; +- +- i2sclk: i2sclk@100a0 { +- compatible = "snps,axs10x-i2s-pll-clock"; +- reg = <0x100a0 0x10>; +- clocks = <&i2spll_clk>; +- #clock-cells = <0>; +- }; +- +- clocks { +- i2spll_clk: i2spll_clk { +- compatible = "fixed-clock"; +- clock-frequency = <27000000>; +- #clock-cells = <0>; +- }; +- +- i2cclk: i2cclk { +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- #clock-cells = <0>; +- }; +- +- apbclk: apbclk { +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- #clock-cells = <0>; +- }; +- +- mmcclk: mmcclk { +- compatible = "fixed-clock"; +- /* +- * DW sdio controller has external ciu clock divider +- * controlled via register in SDIO IP. It divides +- * sdio_ref_clk (which comes from CGU) by 16 for +- * default. So default mmcclk clock (which comes +- * to sdk_in) is 25000000 Hz. +- */ +- clock-frequency = <25000000>; +- #clock-cells = <0>; +- }; +- }; +- +- pguclk: pguclk@10080 { +- compatible = "snps,axs10x-pgu-pll-clock"; +- reg = <0x10080 0x10>, <0x110 0x10>; +- #clock-cells = <0>; +- clocks = <&input_clk>; +- }; +- +- gmac: ethernet@18000 { +- #interrupt-cells = <1>; +- compatible = "snps,dwmac"; +- reg = < 0x18000 0x2000 >; +- interrupts = < 4 >; +- interrupt-names = "macirq"; +- phy-mode = "rgmii"; +- snps,pbl = < 32 >; +- snps,multicast-filter-bins = <256>; +- clocks = <&apbclk>; +- clock-names = "stmmaceth"; +- max-speed = <100>; +- resets = <&creg_rst 5>; +- reset-names = "stmmaceth"; +- mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */ +- }; +- +- ehci@40000 { +- compatible = "generic-ehci"; +- reg = < 0x40000 0x100 >; +- interrupts = < 8 >; +- }; +- +- ohci@60000 { +- compatible = "generic-ohci"; +- reg = < 0x60000 0x100 >; +- interrupts = < 8 >; +- }; +- +- /* +- * According to DW Mobile Storage databook it is required +- * to use "Hold Register" if card is enumerated in SDR12 or +- * SDR25 modes. +- * +- * Utilization of "Hold Register" is already implemented via +- * dw_mci_pltfm_prepare_command() which in its turn gets +- * used through dw_mci_drv_data->prepare_command call-back. +- * This call-back is used in Altera Socfpga platform and so +- * we may reuse it saying that we're compatible with their +- * "altr,socfpga-dw-mshc". +- * +- * Most probably "Hold Register" utilization is platform- +- * independent requirement which means that single unified +- * "snps,dw-mshc" should be enough for all users of DW MMC once +- * dw_mci_pltfm_prepare_command() is used in generic platform +- * code. +- */ +- mmc@15000 { +- compatible = "altr,socfpga-dw-mshc"; +- reg = < 0x15000 0x400 >; +- fifo-depth = < 16 >; +- card-detect-delay = < 200 >; +- clocks = <&apbclk>, <&mmcclk>; +- clock-names = "biu", "ciu"; +- interrupts = < 7 >; +- bus-width = < 4 >; +- }; +- +- uart@20000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x20000 0x100>; +- clock-frequency = <33333333>; +- interrupts = <17>; +- baud = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- uart@21000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x21000 0x100>; +- clock-frequency = <33333333>; +- interrupts = <18>; +- baud = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- /* UART muxed with USB data port (ttyS3) */ +- uart@22000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x22000 0x100>; +- clock-frequency = <33333333>; +- interrupts = <19>; +- baud = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- i2c@1d000 { +- compatible = "snps,designware-i2c"; +- reg = <0x1d000 0x100>; +- clock-frequency = <400000>; +- clocks = <&i2cclk>; +- interrupts = <14>; +- }; +- +- i2s: i2s@1e000 { +- compatible = "snps,designware-i2s"; +- reg = <0x1e000 0x100>; +- clocks = <&i2sclk 0>; +- clock-names = "i2sclk"; +- interrupts = <15>; +- #sound-dai-cells = <0>; +- }; +- +- i2c@1f000 { +- compatible = "snps,designware-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x1f000 0x100>; +- clock-frequency = <400000>; +- clocks = <&i2cclk>; +- interrupts = <16>; +- +- adv7511:adv7511@39{ +- compatible="adi,adv7511"; +- reg = <0x39>; +- interrupts = <23>; +- adi,input-depth = <8>; +- adi,input-colorspace = "rgb"; +- adi,input-clock = "1x"; +- adi,clock-delay = <0x03>; +- #sound-dai-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* RGB/YUV input */ +- port@0 { +- reg = <0>; +- adv7511_input:endpoint { +- remote-endpoint = <&pgu_output>; +- }; +- }; +- +- /* HDMI output */ +- port@1 { +- reg = <1>; +- adv7511_output: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +- }; +- }; +- }; +- +- eeprom@54{ +- compatible = "atmel,24c01"; +- reg = <0x54>; +- pagesize = <0x8>; +- }; +- +- eeprom@57{ +- compatible = "atmel,24c04"; +- reg = <0x57>; +- pagesize = <0x8>; +- }; +- }; +- +- hdmi0: connector { +- compatible = "hdmi-connector"; +- type = "a"; +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&adv7511_output>; +- }; +- }; +- }; +- +- gpio0:gpio@13000 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x13000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio0_banka: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <32>; +- reg = <0>; +- }; +- +- gpio0_bankb: gpio-controller@1 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <8>; +- reg = <1>; +- }; +- +- gpio0_bankc: gpio-controller@2 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <8>; +- reg = <2>; +- }; +- }; +- +- gpio1:gpio@14000 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x14000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio1_banka: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <30>; +- reg = <0>; +- }; +- +- gpio1_bankb: gpio-controller@1 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <10>; +- reg = <1>; +- }; +- +- gpio1_bankc: gpio-controller@2 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <8>; +- reg = <2>; +- }; +- }; +- +- pgu@17000 { +- compatible = "snps,arcpgu"; +- reg = <0x17000 0x400>; +- clocks = <&pguclk>; +- clock-names = "pxlclk"; +- memory-region = <&frame_buffer>; +- port { +- pgu_output: endpoint { +- remote-endpoint = <&adv7511_input>; +- }; +- }; +- }; +- +- sound_playback { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "AXS10x HDMI Audio"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,cpu { +- sound-dai = <&i2s>; +- }; +- simple-audio-card,codec { +- sound-dai = <&adv7511>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/haps_hs.dts b/scripts/dtc/include-prefixes/arc/haps_hs.dts +deleted file mode 100644 +index 76ad527a0847..000000000000 +--- a/scripts/dtc/include-prefixes/arc/haps_hs.dts ++++ /dev/null +@@ -1,99 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) +- */ +-/dts-v1/; +- +-/include/ "skeleton_hs.dtsi" +- +-/ { +- model = "snps,zebu_hs"; +- compatible = "snps,zebu_hs"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&core_intc>; +- +- memory { +- device_type = "memory"; +- /* CONFIG_LINUX_RAM_BASE needs to match low mem start */ +- reg = <0x0 0x80000000 0x0 0x40000000 /* 1 GB low mem */ +- 0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */ +- }; +- +- chosen { +- bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- fpga { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* only perip space at end of low mem accessible +- bus addr, parent bus addr, size */ +- ranges = <0x80000000 0x0 0x80000000 0x80000000>; +- +- core_clk: core_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- }; +- +- core_intc: interrupt-controller { +- compatible = "snps,archs-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- uart0: serial@f0000000 { +- compatible = "ns16550a"; +- reg = <0xf0000000 0x2000>; +- interrupts = <24>; +- clock-frequency = <50000000>; +- baud = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- no-loopback-test = <1>; +- }; +- +- arcpct0: pct { +- compatible = "snps,archs-pct"; +- #interrupt-cells = <1>; +- interrupts = <20>; +- }; +- +- virtio0: virtio@f0100000 { +- compatible = "virtio,mmio"; +- reg = <0xf0100000 0x2000>; +- interrupts = <31>; +- }; +- +- virtio1: virtio@f0102000 { +- compatible = "virtio,mmio"; +- reg = <0xf0102000 0x2000>; +- interrupts = <32>; +- }; +- +- virtio2: virtio@f0104000 { +- compatible = "virtio,mmio"; +- reg = <0xf0104000 0x2000>; +- interrupts = <33>; +- }; +- +- virtio3: virtio@f0106000 { +- compatible = "virtio,mmio"; +- reg = <0xf0106000 0x2000>; +- interrupts = <34>; +- }; +- +- virtio4: virtio@f0108000 { +- compatible = "virtio,mmio"; +- reg = <0xf0108000 0x2000>; +- interrupts = <35>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/haps_hs_idu.dts b/scripts/dtc/include-prefixes/arc/haps_hs_idu.dts +deleted file mode 100644 +index 738c76cd07b3..000000000000 +--- a/scripts/dtc/include-prefixes/arc/haps_hs_idu.dts ++++ /dev/null +@@ -1,74 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) +- */ +-/dts-v1/; +- +-/include/ "skeleton_hs_idu.dtsi" +- +-/ { +- model = "snps,zebu_hs-smp"; +- compatible = "snps,zebu_hs"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&core_intc>; +- +- memory { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512 */ +- }; +- +- chosen { +- bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- fpga { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* child and parent address space 1:1 mapped */ +- ranges; +- +- core_clk: core_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; /* 50 MHZ */ +- }; +- +- core_intc: interrupt-controller { +- compatible = "snps,archs-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- idu_intc: idu-interrupt-controller { +- compatible = "snps,archs-idu-intc"; +- interrupt-controller; +- interrupt-parent = <&core_intc>; +- #interrupt-cells = <1>; +- }; +- +- uart0: serial@f0000000 { +- compatible = "ns16550a"; +- reg = <0xf0000000 0x2000>; +- interrupt-parent = <&idu_intc>; +- interrupts = <0>; +- clock-frequency = <50000000>; +- baud = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- no-loopback-test = <1>; +- }; +- +- arcpct0: pct { +- compatible = "snps,archs-pct"; +- #interrupt-cells = <1>; +- interrupts = <20>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/hsdk.dts b/scripts/dtc/include-prefixes/arc/hsdk.dts +deleted file mode 100644 +index dcaa44e408ac..000000000000 +--- a/scripts/dtc/include-prefixes/arc/hsdk.dts ++++ /dev/null +@@ -1,351 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com) +- */ +- +-/* +- * Device Tree for ARC HS Development Kit +- */ +-/dts-v1/; +- +-#include +-#include +- +-/ { +- model = "snps,hsdk"; +- compatible = "snps,hsdk"; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- chosen { +- bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; +- }; +- +- aliases { +- ethernet = &gmac; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "snps,archs38"; +- reg = <0>; +- clocks = <&core_clk>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "snps,archs38"; +- reg = <1>; +- clocks = <&core_clk>; +- }; +- +- cpu@2 { +- device_type = "cpu"; +- compatible = "snps,archs38"; +- reg = <2>; +- clocks = <&core_clk>; +- }; +- +- cpu@3 { +- device_type = "cpu"; +- compatible = "snps,archs38"; +- reg = <3>; +- clocks = <&core_clk>; +- }; +- }; +- +- input_clk: input-clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <33333333>; +- }; +- +- reg_5v0: regulator-5v0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "5v0-supply"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- cpu_intc: cpu-interrupt-controller { +- compatible = "snps,archs-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- idu_intc: idu-interrupt-controller { +- compatible = "snps,archs-idu-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&cpu_intc>; +- }; +- +- arcpct: pct { +- compatible = "snps,archs-pct"; +- interrupt-parent = <&cpu_intc>; +- interrupts = <20>; +- }; +- +- /* TIMER0 with interrupt for clockevent */ +- timer { +- compatible = "snps,arc-timer"; +- interrupts = <16>; +- interrupt-parent = <&cpu_intc>; +- clocks = <&core_clk>; +- }; +- +- /* 64-bit Global Free Running Counter */ +- gfrc { +- compatible = "snps,archs-timer-gfrc"; +- clocks = <&core_clk>; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&idu_intc>; +- +- ranges = <0x00000000 0x0 0xf0000000 0x10000000>; +- +- cgu_rst: reset-controller@8a0 { +- compatible = "snps,hsdk-reset"; +- #reset-cells = <1>; +- reg = <0x8a0 0x4>, <0xff0 0x4>; +- }; +- +- core_clk: core-clk@0 { +- compatible = "snps,hsdk-core-pll-clock"; +- reg = <0x00 0x10>, <0x14b8 0x4>; +- #clock-cells = <0>; +- clocks = <&input_clk>; +- +- /* +- * Set initial core pll output frequency to 1GHz. +- * It will be applied at the core pll driver probing +- * on early boot. +- */ +- assigned-clocks = <&core_clk>; +- assigned-clock-rates = <1000000000>; +- }; +- +- serial: serial@5000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x5000 0x100>; +- clock-frequency = <33330000>; +- interrupts = <6>; +- baud = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- gmacclk: gmacclk { +- compatible = "fixed-clock"; +- clock-frequency = <400000000>; +- #clock-cells = <0>; +- }; +- +- mmcclk_ciu: mmcclk-ciu { +- compatible = "fixed-clock"; +- /* +- * DW sdio controller has external ciu clock divider +- * controlled via register in SDIO IP. Due to its +- * unexpected default value (it should divide by 1 +- * but it divides by 8) SDIO IP uses wrong clock and +- * works unstable (see STAR 9001204800) +- * We switched to the minimum possible value of the +- * divisor (div-by-2) in HSDK platform code. +- * So add temporary fix and change clock frequency +- * to 50000000 Hz until we fix dw sdio driver itself. +- */ +- clock-frequency = <50000000>; +- #clock-cells = <0>; +- }; +- +- mmcclk_biu: mmcclk-biu { +- compatible = "fixed-clock"; +- clock-frequency = <400000000>; +- #clock-cells = <0>; +- }; +- +- gpu_core_clk: gpu-core-clk { +- compatible = "fixed-clock"; +- clock-frequency = <400000000>; +- #clock-cells = <0>; +- }; +- +- gpu_dma_clk: gpu-dma-clk { +- compatible = "fixed-clock"; +- clock-frequency = <400000000>; +- #clock-cells = <0>; +- }; +- +- gpu_cfg_clk: gpu-cfg-clk { +- compatible = "fixed-clock"; +- clock-frequency = <200000000>; +- #clock-cells = <0>; +- }; +- +- dmac_core_clk: dmac-core-clk { +- compatible = "fixed-clock"; +- clock-frequency = <400000000>; +- #clock-cells = <0>; +- }; +- +- dmac_cfg_clk: dmac-gpu-cfg-clk { +- compatible = "fixed-clock"; +- clock-frequency = <200000000>; +- #clock-cells = <0>; +- }; +- +- gmac: ethernet@8000 { +- #interrupt-cells = <1>; +- compatible = "snps,dwmac"; +- reg = <0x8000 0x2000>; +- interrupts = <10>; +- interrupt-names = "macirq"; +- phy-mode = "rgmii-id"; +- snps,pbl = <32>; +- snps,multicast-filter-bins = <256>; +- clocks = <&gmacclk>; +- clock-names = "stmmaceth"; +- phy-handle = <&phy0>; +- resets = <&cgu_rst HSDK_ETH_RESET>; +- reset-names = "stmmaceth"; +- mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */ +- dma-coherent; +- +- tx-fifo-depth = <4096>; +- rx-fifo-depth = <4096>; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy0: ethernet-phy@0 { /* Micrel KSZ9031 */ +- reg = <0>; +- }; +- }; +- }; +- +- ohci@60000 { +- compatible = "snps,hsdk-v1.0-ohci", "generic-ohci"; +- reg = <0x60000 0x100>; +- interrupts = <15>; +- resets = <&cgu_rst HSDK_USB_RESET>; +- dma-coherent; +- }; +- +- ehci@40000 { +- compatible = "snps,hsdk-v1.0-ehci", "generic-ehci"; +- reg = <0x40000 0x100>; +- interrupts = <15>; +- resets = <&cgu_rst HSDK_USB_RESET>; +- dma-coherent; +- }; +- +- mmc@a000 { +- compatible = "altr,socfpga-dw-mshc"; +- reg = <0xa000 0x400>; +- num-slots = <1>; +- fifo-depth = <16>; +- card-detect-delay = <200>; +- clocks = <&mmcclk_biu>, <&mmcclk_ciu>; +- clock-names = "biu", "ciu"; +- interrupts = <12>; +- bus-width = <4>; +- dma-coherent; +- }; +- +- spi0: spi@20000 { +- compatible = "snps,dw-apb-ssi"; +- reg = <0x20000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <16>; +- num-cs = <2>; +- reg-io-width = <4>; +- clocks = <&input_clk>; +- cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>, +- <&creg_gpio 1 GPIO_ACTIVE_LOW>; +- +- spi-flash@0 { +- compatible = "sst26wf016b", "jedec,spi-nor"; +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <4000000>; +- }; +- +- adc@1 { +- compatible = "ti,adc108s102"; +- reg = <1>; +- vref-supply = <®_5v0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- creg_gpio: gpio@14b0 { +- compatible = "snps,creg-gpio-hsdk"; +- reg = <0x14b0 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <2>; +- }; +- +- gpio: gpio@3000 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x3000 0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio_port_a: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <24>; +- reg = <0>; +- }; +- }; +- +- gpu_3d: gpu@90000 { +- compatible = "vivante,gc"; +- reg = <0x90000 0x4000>; +- clocks = <&gpu_dma_clk>, +- <&gpu_cfg_clk>, +- <&gpu_core_clk>, +- <&gpu_core_clk>; +- clock-names = "bus", "reg", "core", "shader"; +- interrupts = <28>; +- }; +- +- dmac: dmac@80000 { +- compatible = "snps,axi-dma-1.01a"; +- reg = <0x80000 0x400>; +- interrupts = <27>; +- clocks = <&dmac_core_clk>, <&dmac_cfg_clk>; +- clock-names = "core-clk", "cfgr-clk"; +- +- dma-channels = <4>; +- snps,dma-masters = <2>; +- snps,data-width = <3>; +- snps,block-size = <4096 4096 4096 4096>; +- snps,priority = <0 1 2 3>; +- snps,axi-max-burst-len = <16>; +- }; +- }; +- +- memory@80000000 { +- #address-cells = <2>; +- #size-cells = <2>; +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0x40000000>; /* 1 GB lowmem */ +- /* 0x1 0x00000000 0x0 0x40000000>; 1 GB highmem */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/nsim_700.dts b/scripts/dtc/include-prefixes/arc/nsim_700.dts +deleted file mode 100644 +index f8832a15e174..000000000000 +--- a/scripts/dtc/include-prefixes/arc/nsim_700.dts ++++ /dev/null +@@ -1,59 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com) +- */ +-/dts-v1/; +- +-/include/ "skeleton.dtsi" +- +-/ { +- model = "snps,nsim"; +- compatible = "snps,nsim"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&core_intc>; +- +- chosen { +- bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 print-fatal-signals=1"; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- fpga { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* child and parent address space 1:1 mapped */ +- ranges; +- +- core_clk: core_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <80000000>; +- }; +- +- core_intc: interrupt-controller { +- compatible = "snps,arc700-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- uart0: serial@f0000000 { +- compatible = "ns16550a"; +- reg = <0xf0000000 0x2000>; +- interrupts = <24>; +- clock-frequency = <50000000>; +- baud = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- no-loopback-test = <1>; +- }; +- +- arcpct0: pct { +- compatible = "snps,arc700-pct"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/nsimosci.dts b/scripts/dtc/include-prefixes/arc/nsimosci.dts +deleted file mode 100644 +index fc207c4a4eb2..000000000000 +--- a/scripts/dtc/include-prefixes/arc/nsimosci.dts ++++ /dev/null +@@ -1,88 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) +- */ +-/dts-v1/; +- +-/include/ "skeleton.dtsi" +- +-/ { +- model = "snps,nsimosci"; +- compatible = "snps,nsimosci"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&core_intc>; +- +- chosen { +- /* this is for console on PGU */ +- /* bootargs = "console=tty0 consoleblank=0"; */ +- /* this is for console on serial */ +- bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1"; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- fpga { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* child and parent address space 1:1 mapped */ +- ranges; +- +- core_clk: core_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <20000000>; +- }; +- +- core_intc: interrupt-controller { +- compatible = "snps,arc700-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- uart0: serial@f0000000 { +- compatible = "ns8250"; +- reg = <0xf0000000 0x2000>; +- interrupts = <11>; +- clock-frequency = <3686400>; +- baud = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- no-loopback-test = <1>; +- }; +- +- pguclk: pguclk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25175000>; +- }; +- +- pgu@f9000000 { +- compatible = "snps,arcpgu"; +- reg = <0xf9000000 0x400>; +- clocks = <&pguclk>; +- clock-names = "pxlclk"; +- }; +- +- ps2: ps2@f9001000 { +- compatible = "snps,arc_ps2"; +- reg = <0xf9000400 0x14>; +- interrupts = <13>; +- interrupt-names = "arc_ps2_irq"; +- }; +- +- eth0: ethernet@f0003000 { +- compatible = "ezchip,nps-mgt-enet"; +- reg = <0xf0003000 0x44>; +- interrupts = <7>; +- }; +- +- arcpct0: pct { +- compatible = "snps,arc700-pct"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/nsimosci_hs.dts b/scripts/dtc/include-prefixes/arc/nsimosci_hs.dts +deleted file mode 100644 +index 71f1f8416179..000000000000 +--- a/scripts/dtc/include-prefixes/arc/nsimosci_hs.dts ++++ /dev/null +@@ -1,90 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) +- */ +-/dts-v1/; +- +-/include/ "skeleton_hs.dtsi" +- +-/ { +- model = "snps,nsimosci_hs"; +- compatible = "snps,nsimosci_hs"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&core_intc>; +- +- chosen { +- /* this is for console on PGU */ +- /* bootargs = "console=tty0 consoleblank=0"; */ +- /* this is for console on serial */ +- bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1"; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- fpga { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* child and parent address space 1:1 mapped */ +- ranges; +- +- core_clk: core_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <20000000>; +- }; +- +- core_intc: core-interrupt-controller { +- compatible = "snps,archs-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- uart0: serial@f0000000 { +- compatible = "ns8250"; +- reg = <0xf0000000 0x2000>; +- interrupts = <24>; +- clock-frequency = <3686400>; +- baud = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- no-loopback-test = <1>; +- }; +- +- pguclk: pguclk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25175000>; +- }; +- +- pgu@f9000000 { +- compatible = "snps,arcpgu"; +- reg = <0xf9000000 0x400>; +- clocks = <&pguclk>; +- clock-names = "pxlclk"; +- }; +- +- ps2: ps2@f9001000 { +- compatible = "snps,arc_ps2"; +- reg = <0xf9000400 0x14>; +- interrupts = <27>; +- interrupt-names = "arc_ps2_irq"; +- }; +- +- eth0: ethernet@f0003000 { +- compatible = "ezchip,nps-mgt-enet"; +- reg = <0xf0003000 0x44>; +- interrupts = <25>; +- }; +- +- arcpct0: pct { +- compatible = "snps,archs-pct"; +- #interrupt-cells = <1>; +- interrupts = <20>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/nsimosci_hs_idu.dts b/scripts/dtc/include-prefixes/arc/nsimosci_hs_idu.dts +deleted file mode 100644 +index 69d794c59d44..000000000000 +--- a/scripts/dtc/include-prefixes/arc/nsimosci_hs_idu.dts ++++ /dev/null +@@ -1,98 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) +- */ +-/dts-v1/; +- +-/include/ "skeleton_hs_idu.dtsi" +- +-/ { +- model = "snps,nsimosci_hs-smp"; +- compatible = "snps,nsimosci_hs"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&core_intc>; +- +- chosen { +- /* this is for console on serial */ +- bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24 print-fatal-signals=1"; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- fpga { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* child and parent address space 1:1 mapped */ +- ranges; +- +- core_clk: core_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <5000000>; +- }; +- +- core_intc: core-interrupt-controller { +- compatible = "snps,archs-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- idu_intc: idu-interrupt-controller { +- compatible = "snps,archs-idu-intc"; +- interrupt-controller; +- interrupt-parent = <&core_intc>; +- #interrupt-cells = <1>; +- }; +- +- uart0: serial@f0000000 { +- compatible = "ns8250"; +- reg = <0xf0000000 0x2000>; +- interrupt-parent = <&idu_intc>; +- interrupts = <0>; +- clock-frequency = <3686400>; +- baud = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- no-loopback-test = <1>; +- }; +- +- pguclk: pguclk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25175000>; +- }; +- +- pgu@f9000000 { +- compatible = "snps,arcpgu"; +- reg = <0xf9000000 0x400>; +- clocks = <&pguclk>; +- clock-names = "pxlclk"; +- }; +- +- ps2: ps2@f9001000 { +- compatible = "snps,arc_ps2"; +- reg = <0xf9000400 0x14>; +- interrupts = <3>; +- interrupt-parent = <&idu_intc>; +- interrupt-names = "arc_ps2_irq"; +- }; +- +- eth0: ethernet@f0003000 { +- compatible = "ezchip,nps-mgt-enet"; +- reg = <0xf0003000 0x44>; +- interrupt-parent = <&idu_intc>; +- interrupts = <1>; +- }; +- +- arcpct0: pct { +- compatible = "snps,archs-pct"; +- #interrupt-cells = <1>; +- interrupts = <20>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/skeleton.dtsi b/scripts/dtc/include-prefixes/arc/skeleton.dtsi +deleted file mode 100644 +index ba86b8036a84..000000000000 +--- a/scripts/dtc/include-prefixes/arc/skeleton.dtsi ++++ /dev/null +@@ -1,48 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com) +- */ +- +-/* +- * Skeleton device tree; the bare minimum needed to boot; just include and +- * add a compatible value. +- */ +- +-/ { +- compatible = "snps,arc"; +- #address-cells = <1>; +- #size-cells = <1>; +- chosen { }; +- aliases { }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "snps,arc770d"; +- reg = <0>; +- clocks = <&core_clk>; +- }; +- }; +- +- /* TIMER0 with interrupt for clockevent */ +- timer0 { +- compatible = "snps,arc-timer"; +- interrupts = <3>; +- interrupt-parent = <&core_intc>; +- clocks = <&core_clk>; +- }; +- +- /* TIMER1 for free running clocksource */ +- timer1 { +- compatible = "snps,arc-timer"; +- clocks = <&core_clk>; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256M */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/skeleton_hs.dtsi b/scripts/dtc/include-prefixes/arc/skeleton_hs.dtsi +deleted file mode 100644 +index 8fb49890e8a6..000000000000 +--- a/scripts/dtc/include-prefixes/arc/skeleton_hs.dtsi ++++ /dev/null +@@ -1,49 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com) +- */ +- +-/ { +- compatible = "snps,arc"; +- #address-cells = <1>; +- #size-cells = <1>; +- chosen { }; +- aliases { }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "snps,archs38"; +- reg = <0>; +- clocks = <&core_clk>; +- }; +- }; +- +- /* TIMER0 with interrupt for clockevent */ +- timer0 { +- compatible = "snps,arc-timer"; +- interrupts = <16>; +- interrupt-parent = <&core_intc>; +- clocks = <&core_clk>; +- }; +- +- /* 64-bit Local RTC: preferred clocksource for UP */ +- rtc { +- compatible = "snps,archs-timer-rtc"; +- clocks = <&core_clk>; +- }; +- +- /* TIMER1 for free running clocksource: Fallback if rtc not found */ +- timer1 { +- compatible = "snps,arc-timer"; +- clocks = <&core_clk>; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256M */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/skeleton_hs_idu.dtsi b/scripts/dtc/include-prefixes/arc/skeleton_hs_idu.dtsi +deleted file mode 100644 +index 75f5c9ecb5bf..000000000000 +--- a/scripts/dtc/include-prefixes/arc/skeleton_hs_idu.dtsi ++++ /dev/null +@@ -1,61 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com) +- */ +- +-/ { +- compatible = "snps,arc"; +- #address-cells = <1>; +- #size-cells = <1>; +- chosen { }; +- aliases { }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "snps,archs38"; +- reg = <0>; +- clocks = <&core_clk>; +- }; +- cpu@1 { +- device_type = "cpu"; +- compatible = "snps,archs38"; +- reg = <1>; +- clocks = <&core_clk>; +- }; +- cpu@2 { +- device_type = "cpu"; +- compatible = "snps,archs38"; +- reg = <2>; +- clocks = <&core_clk>; +- }; +- cpu@3 { +- device_type = "cpu"; +- compatible = "snps,archs38"; +- reg = <3>; +- clocks = <&core_clk>; +- }; +- }; +- +- /* TIMER0 with interrupt for clockevent */ +- timer0 { +- compatible = "snps,arc-timer"; +- interrupts = <16>; +- interrupt-parent = <&core_intc>; +- clocks = <&core_clk>; +- }; +- +- /* 64-bit Global Free Running Counter */ +- gfrc { +- compatible = "snps,archs-timer-gfrc"; +- clocks = <&core_clk>; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256M */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/vdk_axc003.dtsi b/scripts/dtc/include-prefixes/arc/vdk_axc003.dtsi +deleted file mode 100644 +index c21d0eb07bf6..000000000000 +--- a/scripts/dtc/include-prefixes/arc/vdk_axc003.dtsi ++++ /dev/null +@@ -1,65 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013, 2014 Synopsys, Inc. (www.synopsys.com) +- */ +- +-/* +- * Device tree for AXC003 CPU card: HS38x UP configuration (VDK version) +- */ +- +-/include/ "skeleton_hs.dtsi" +- +-/ { +- compatible = "snps,arc"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpu_card { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0x00000000 0xf0000000 0x10000000>; +- +- core_clk: core_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- }; +- +- core_intc: archs-intc@cpu { +- compatible = "snps,archs-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- debug_uart: dw-apb-uart@5000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x5000 0x100>; +- clock-frequency = <2403200>; +- interrupt-parent = <&core_intc>; +- interrupts = <19>; +- baud = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- }; +- +- mb_intc: interrupt-controller@e0012000 { +- #interrupt-cells = <1>; +- compatible = "snps,dw-apb-ictl"; +- reg = < 0xe0012000 0x200 >; +- interrupt-controller; +- interrupt-parent = <&core_intc>; +- interrupts = < 18 >; +- }; +- +- memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x80000000 0x40000000>; +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512MiB */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/vdk_axc003_idu.dtsi b/scripts/dtc/include-prefixes/arc/vdk_axc003_idu.dtsi +deleted file mode 100644 +index 4d348853ac7c..000000000000 +--- a/scripts/dtc/include-prefixes/arc/vdk_axc003_idu.dtsi ++++ /dev/null +@@ -1,73 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com) +- */ +- +-/* +- * Device tree for AXC003 CPU card: +- * HS38x2 (Dual Core) with IDU intc (VDK version) +- */ +- +-/include/ "skeleton_hs_idu.dtsi" +- +-/ { +- compatible = "snps,arc"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpu_card { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0x00000000 0xf0000000 0x10000000>; +- +- core_clk: core_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- }; +- +- core_intc: archs-intc@cpu { +- compatible = "snps,archs-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- idu_intc: idu-interrupt-controller { +- compatible = "snps,archs-idu-intc"; +- interrupt-controller; +- interrupt-parent = <&core_intc>; +- #interrupt-cells = <1>; +- }; +- +- debug_uart: dw-apb-uart@5000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x5000 0x100>; +- clock-frequency = <2403200>; +- interrupt-parent = <&idu_intc>; +- interrupts = <2>; +- baud = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- }; +- +- mb_intc: interrupt-controller@e0012000 { +- #interrupt-cells = <1>; +- compatible = "snps,dw-apb-ictl"; +- reg = < 0xe0012000 0x200 >; +- interrupt-controller; +- interrupt-parent = <&idu_intc>; +- interrupts = <0>; +- }; +- +- memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x80000000 0x40000000>; +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512MiB */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/vdk_axs10x_mb.dtsi b/scripts/dtc/include-prefixes/arc/vdk_axs10x_mb.dtsi +deleted file mode 100644 +index cbb179770293..000000000000 +--- a/scripts/dtc/include-prefixes/arc/vdk_axs10x_mb.dtsi ++++ /dev/null +@@ -1,126 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Support for peripherals on the AXS10x mainboard (VDK version) +- * +- * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) +- */ +- +-/ { +- axs10x_mb_vdk { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0xe0000000 0x10000000>; +- interrupt-parent = <&mb_intc>; +- +- clocks { +- apbclk: apbclk { +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- #clock-cells = <0>; +- }; +- +- mmcclk: mmcclk { +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- #clock-cells = <0>; +- }; +- +- pguclk: pguclk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25175000>; +- }; +- }; +- +- ethernet@18000 { +- #interrupt-cells = <1>; +- compatible = "snps,dwmac"; +- reg = < 0x18000 0x2000 >; +- interrupts = < 4 >; +- interrupt-names = "macirq"; +- phy-mode = "rgmii"; +- snps,phy-addr = < 0 >; // VDK model phy address is 0 +- snps,pbl = < 32 >; +- clocks = <&apbclk>; +- clock-names = "stmmaceth"; +- }; +- +- ehci@40000 { +- compatible = "generic-ehci"; +- reg = < 0x40000 0x100 >; +- interrupts = < 8 >; +- }; +- +- uart@20000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x20000 0x100>; +- clock-frequency = <2403200>; +- interrupts = <17>; +- baud = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- uart@21000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x21000 0x100>; +- clock-frequency = <2403200>; +- interrupts = <18>; +- baud = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- uart@22000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x22000 0x100>; +- clock-frequency = <2403200>; +- interrupts = <19>; +- baud = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +-/* PGU output directly sent to virtual LCD screen; hdmi controller not modelled */ +- pgu@17000 { +- compatible = "snps,arcpgu"; +- reg = <0x17000 0x400>; +- clocks = <&pguclk>; +- clock-names = "pxlclk"; +- }; +- +-/* VDK has additional ps2 keyboard/mouse interface integrated in LCD screen model */ +- ps2: ps2@e0017400 { +- compatible = "snps,arc_ps2"; +- reg = <0x17400 0x14>; +- interrupts = <5>; +- interrupt-names = "arc_ps2_irq"; +- }; +- +- mmc@15000 { +- compatible = "snps,dw-mshc"; +- reg = <0x15000 0x400>; +- fifo-depth = <1024>; +- card-detect-delay = <200>; +- clocks = <&apbclk>, <&mmcclk>; +- clock-names = "biu", "ciu"; +- interrupts = <7>; +- bus-width = <4>; +- }; +- }; +- +- /* +- * Embedded Vision subsystem UIO mappings; only relevant for EV VDK +- * +- * This node is intentionally put outside of MB above becase +- * it maps areas outside of MB's 0xez-0xfz. +- */ +- uio_ev: uio@d0000000 { +- compatible = "generic-uio"; +- reg = <0xd0000000 0x2000 0xd1000000 0x2000 0x90000000 0x10000000 0xc0000000 0x10000000>; +- reg-names = "ev_gsa", "ev_ctrl", "ev_shared_mem", "ev_code_mem"; +- interrupt-parent = <&mb_intc>; +- interrupts = <23>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/vdk_hs38.dts b/scripts/dtc/include-prefixes/arc/vdk_hs38.dts +deleted file mode 100644 +index cddea7eaca32..000000000000 +--- a/scripts/dtc/include-prefixes/arc/vdk_hs38.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) +- * +- * ARC HS38 Virtual Development Kit (VDK) +- */ +-/dts-v1/; +- +-/include/ "vdk_axc003.dtsi" +-/include/ "vdk_axs10x_mb.dtsi" +- +-/ { +- model = "snps,vdk_archs"; +- compatible = "snps,axs103"; +- +- chosen { +- bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arc/vdk_hs38_smp.dts b/scripts/dtc/include-prefixes/arc/vdk_hs38_smp.dts +deleted file mode 100644 +index f57d1922ee99..000000000000 +--- a/scripts/dtc/include-prefixes/arc/vdk_hs38_smp.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) +- * +- * ARC HS38 Virtual Development Kit, SMP version (VDK) +- */ +-/dts-v1/; +- +-/include/ "vdk_axc003_idu.dtsi" +-/include/ "vdk_axs10x_mb.dtsi" +- +-/ { +- model = "snps,vdk_archs-smp"; +- compatible = "snps,axs103"; +- +- chosen { +- bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0 video=640x480-24"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm b/scripts/dtc/include-prefixes/arm +new file mode 120000 +index 000000000000..eb14d4515a57 +--- /dev/null ++++ b/scripts/dtc/include-prefixes/arm +@@ -0,0 +1 @@ ++../../../arch/arm/boot/dts +\ No newline at end of file +diff --git a/scripts/dtc/include-prefixes/arm/Makefile b/scripts/dtc/include-prefixes/arm/Makefile +deleted file mode 100644 +index 27ca1ca6e827..000000000000 +--- a/scripts/dtc/include-prefixes/arm/Makefile ++++ /dev/null +@@ -1,1501 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_ALPINE) += \ +- alpine-db.dtb +-dtb-$(CONFIG_MACH_ARTPEC6) += \ +- artpec6-devboard.dtb +-dtb-$(CONFIG_MACH_ASM9260) += \ +- alphascale-asm9260-devkit.dtb +-# Keep at91 dtb files sorted alphabetically for each SoC +-dtb-$(CONFIG_SOC_AT91RM9200) += \ +- at91rm9200ek.dtb \ +- mpa1600.dtb +-dtb-$(CONFIG_SOC_AT91SAM9) += \ +- animeo_ip.dtb \ +- at91-qil_a9260.dtb \ +- aks-cdu.dtb \ +- ethernut5.dtb \ +- evk-pro3.dtb \ +- tny_a9260.dtb \ +- usb_a9260.dtb \ +- at91sam9260ek.dtb \ +- at91sam9261ek.dtb \ +- at91sam9263ek.dtb \ +- at91-sam9_l9260.dtb \ +- tny_a9263.dtb \ +- usb_a9263.dtb \ +- at91-foxg20.dtb \ +- at91-kizbox.dtb \ +- at91sam9g20ek.dtb \ +- at91sam9g20ek_2mmc.dtb \ +- tny_a9g20.dtb \ +- usb_a9g20.dtb \ +- usb_a9g20_lpw.dtb \ +- at91sam9m10g45ek.dtb \ +- pm9g45.dtb \ +- at91sam9n12ek.dtb \ +- at91sam9rlek.dtb \ +- at91-ariag25.dtb \ +- at91-ariettag25.dtb \ +- at91-cosino_mega2560.dtb \ +- at91-kizboxmini-base.dtb \ +- at91-kizboxmini-mb.dtb \ +- at91-kizboxmini-rd.dtb \ +- at91-smartkiz.dtb \ +- at91-wb45n.dtb \ +- at91sam9g15ek.dtb \ +- at91sam9g25-gardena-smart-gateway.dtb \ +- at91sam9g25ek.dtb \ +- at91sam9g35ek.dtb \ +- at91sam9x25ek.dtb \ +- at91sam9x35ek.dtb +-dtb-$(CONFIG_SOC_SAM9X60) += \ +- at91-sam9x60ek.dtb +-dtb-$(CONFIG_SOC_SAM_V7) += \ +- at91-kizbox2-2.dtb \ +- at91-kizbox3-hs.dtb \ +- at91-nattis-2-natte-2.dtb \ +- at91-sama5d27_som1_ek.dtb \ +- at91-sama5d27_wlsom1_ek.dtb \ +- at91-sama5d2_icp.dtb \ +- at91-sama5d2_ptc_ek.dtb \ +- at91-sama5d2_xplained.dtb \ +- at91-sama5d3_xplained.dtb \ +- at91-dvk_som60.dtb \ +- at91-gatwick.dtb \ +- at91-tse850-3.dtb \ +- at91-wb50n.dtb \ +- sama5d31ek.dtb \ +- sama5d33ek.dtb \ +- sama5d34ek.dtb \ +- sama5d35ek.dtb \ +- sama5d36ek.dtb \ +- sama5d36ek_cmp.dtb \ +- at91-sama5d4_ma5d4evk.dtb \ +- at91-sama5d4_xplained.dtb \ +- at91-sama5d4ek.dtb \ +- at91-vinco.dtb +-dtb-$(CONFIG_SOC_SAMA7G5) += \ +- at91-sama7g5ek.dtb +-dtb-$(CONFIG_ARCH_AXXIA) += \ +- axm5516-amarillo.dtb +-dtb-$(CONFIG_ARCH_BCM2835) += \ +- bcm2835-rpi-b.dtb \ +- bcm2835-rpi-a.dtb \ +- bcm2835-rpi-b-rev2.dtb \ +- bcm2835-rpi-b-plus.dtb \ +- bcm2835-rpi-a-plus.dtb \ +- bcm2835-rpi-cm1-io1.dtb \ +- bcm2836-rpi-2-b.dtb \ +- bcm2837-rpi-3-a-plus.dtb \ +- bcm2837-rpi-3-b.dtb \ +- bcm2837-rpi-3-b-plus.dtb \ +- bcm2837-rpi-cm3-io3.dtb \ +- bcm2711-rpi-400.dtb \ +- bcm2711-rpi-4-b.dtb \ +- bcm2835-rpi-zero.dtb \ +- bcm2835-rpi-zero-w.dtb +-dtb-$(CONFIG_ARCH_BCM_5301X) += \ +- bcm4708-asus-rt-ac56u.dtb \ +- bcm4708-asus-rt-ac68u.dtb \ +- bcm4708-buffalo-wzr-1750dhp.dtb \ +- bcm4708-linksys-ea6300-v1.dtb \ +- bcm4708-linksys-ea6500-v2.dtb \ +- bcm4708-luxul-xap-1510.dtb \ +- bcm4708-luxul-xwc-1000.dtb \ +- bcm4708-netgear-r6250.dtb \ +- bcm4708-netgear-r6300-v2.dtb \ +- bcm4708-smartrg-sr400ac.dtb \ +- bcm47081-asus-rt-n18u.dtb \ +- bcm47081-buffalo-wzr-600dhp2.dtb \ +- bcm47081-buffalo-wzr-900dhp.dtb \ +- bcm47081-luxul-xap-1410.dtb \ +- bcm47081-luxul-xwr-1200.dtb \ +- bcm47081-tplink-archer-c5-v2.dtb \ +- bcm4709-asus-rt-ac87u.dtb \ +- bcm4709-buffalo-wxr-1900dhp.dtb \ +- bcm4709-linksys-ea9200.dtb \ +- bcm4709-netgear-r7000.dtb \ +- bcm4709-netgear-r8000.dtb \ +- bcm4709-tplink-archer-c9-v1.dtb \ +- bcm47094-dlink-dir-885l.dtb \ +- bcm47094-linksys-panamera.dtb \ +- bcm47094-luxul-abr-4500.dtb \ +- bcm47094-luxul-xap-1610.dtb \ +- bcm47094-luxul-xbr-4500.dtb \ +- bcm47094-luxul-xwc-2000.dtb \ +- bcm47094-luxul-xwr-3100.dtb \ +- bcm47094-luxul-xwr-3150-v1.dtb \ +- bcm47094-netgear-r8500.dtb \ +- bcm47094-phicomm-k3.dtb \ +- bcm53016-meraki-mr32.dtb \ +- bcm94708.dtb \ +- bcm94709.dtb \ +- bcm953012er.dtb \ +- bcm953012hr.dtb \ +- bcm953012k.dtb +-dtb-$(CONFIG_ARCH_BCM_53573) += \ +- bcm47189-luxul-xap-1440.dtb \ +- bcm47189-luxul-xap-810.dtb \ +- bcm47189-tenda-ac9.dtb \ +- bcm947189acdbmr.dtb +-dtb-$(CONFIG_ARCH_BCM_63XX) += \ +- bcm963138dvt.dtb +-dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ +- bcm911360_entphn.dtb \ +- bcm911360k.dtb \ +- bcm958300k.dtb \ +- bcm958305k.dtb +-dtb-$(CONFIG_ARCH_BCM_HR2) += \ +- bcm53340-ubnt-unifi-switch8.dtb +-dtb-$(CONFIG_ARCH_BCM_MOBILE) += \ +- bcm28155-ap.dtb \ +- bcm21664-garnet.dtb \ +- bcm23550-sparrow.dtb +-dtb-$(CONFIG_ARCH_BCM_NSP) += \ +- bcm958522er.dtb \ +- bcm958525er.dtb \ +- bcm958525xmc.dtb \ +- bcm958622hr.dtb \ +- bcm958623hr.dtb \ +- bcm958625hr.dtb \ +- bcm988312hr.dtb \ +- bcm958625k.dtb +-dtb-$(CONFIG_ARCH_BERLIN) += \ +- berlin2-sony-nsz-gs7.dtb \ +- berlin2cd-google-chromecast.dtb \ +- berlin2cd-valve-steamlink.dtb \ +- berlin2q-marvell-dmp.dtb +-dtb-$(CONFIG_ARCH_BRCMSTB) += \ +- bcm7445-bcm97445svmb.dtb +-dtb-$(CONFIG_ARCH_CLPS711X) += \ +- ep7211-edb7211.dtb +-dtb-$(CONFIG_ARCH_DAVINCI) += \ +- da850-lcdk.dtb \ +- da850-enbw-cmc.dtb \ +- da850-evm.dtb \ +- da850-lego-ev3.dtb +-dtb-$(CONFIG_ARCH_DIGICOLOR) += \ +- cx92755_equinox.dtb +-dtb-$(CONFIG_ARCH_EXYNOS3) += \ +- exynos3250-artik5-eval.dtb \ +- exynos3250-monk.dtb \ +- exynos3250-rinato.dtb +-dtb-$(CONFIG_ARCH_EXYNOS4) += \ +- exynos4210-i9100.dtb \ +- exynos4210-origen.dtb \ +- exynos4210-smdkv310.dtb \ +- exynos4210-trats.dtb \ +- exynos4210-universal_c210.dtb \ +- exynos4412-i9300.dtb \ +- exynos4412-i9305.dtb \ +- exynos4412-itop-elite.dtb \ +- exynos4412-n710x.dtb \ +- exynos4412-odroidu3.dtb \ +- exynos4412-odroidx.dtb \ +- exynos4412-odroidx2.dtb \ +- exynos4412-origen.dtb \ +- exynos4412-p4note-n8010.dtb \ +- exynos4412-smdk4412.dtb \ +- exynos4412-tiny4412.dtb \ +- exynos4412-trats2.dtb +-dtb-$(CONFIG_ARCH_EXYNOS5) += \ +- exynos5250-arndale.dtb \ +- exynos5250-smdk5250.dtb \ +- exynos5250-snow.dtb \ +- exynos5250-snow-rev5.dtb \ +- exynos5250-spring.dtb \ +- exynos5260-xyref5260.dtb \ +- exynos5410-odroidxu.dtb \ +- exynos5410-smdk5410.dtb \ +- exynos5420-arndale-octa.dtb \ +- exynos5420-peach-pit.dtb \ +- exynos5420-smdk5420.dtb \ +- exynos5422-odroidhc1.dtb \ +- exynos5422-odroidxu3.dtb \ +- exynos5422-odroidxu3-lite.dtb \ +- exynos5422-odroidxu4.dtb \ +- exynos5800-peach-pi.dtb +-dtb-$(CONFIG_ARCH_GEMINI) += \ +- gemini-dlink-dir-685.dtb \ +- gemini-dlink-dns-313.dtb \ +- gemini-nas4220b.dtb \ +- gemini-rut1xx.dtb \ +- gemini-sl93512r.dtb \ +- gemini-sq201.dtb \ +- gemini-wbd111.dtb \ +- gemini-wbd222.dtb +-dtb-$(CONFIG_ARCH_HI3xxx) += \ +- hi3620-hi4511.dtb +-dtb-$(CONFIG_ARCH_HIGHBANK) += \ +- highbank.dtb \ +- ecx-2000.dtb +-dtb-$(CONFIG_ARCH_HIP01) += \ +- hip01-ca9x2.dtb +-dtb-$(CONFIG_ARCH_HIP04) += \ +- hip04-d01.dtb +-dtb-$(CONFIG_ARCH_HISI) += \ +- hi3519-demb.dtb +-dtb-$(CONFIG_ARCH_HIX5HD2) += \ +- hisi-x5hd2-dkb.dtb +-dtb-$(CONFIG_ARCH_INTEGRATOR) += \ +- integratorap.dtb \ +- integratorap-im-pd1.dtb \ +- integratorcp.dtb +-dtb-$(CONFIG_ARCH_IXP4XX) += \ +- intel-ixp42x-linksys-nslu2.dtb \ +- intel-ixp42x-linksys-wrv54g.dtb \ +- intel-ixp42x-freecom-fsg-3.dtb \ +- intel-ixp42x-welltech-epbx100.dtb \ +- intel-ixp42x-ixdp425.dtb \ +- intel-ixp43x-kixrp435.dtb \ +- intel-ixp46x-ixdp465.dtb \ +- intel-ixp42x-adi-coyote.dtb \ +- intel-ixp42x-ixdpg425.dtb \ +- intel-ixp42x-iomega-nas100d.dtb \ +- intel-ixp42x-dlink-dsm-g600.dtb \ +- intel-ixp42x-gateworks-gw2348.dtb \ +- intel-ixp43x-gateworks-gw2358.dtb \ +- intel-ixp42x-netgear-wg302v2.dtb \ +- intel-ixp42x-arcom-vulcan.dtb +-dtb-$(CONFIG_ARCH_KEYSTONE) += \ +- keystone-k2hk-evm.dtb \ +- keystone-k2l-evm.dtb \ +- keystone-k2e-evm.dtb \ +- keystone-k2g-evm.dtb \ +- keystone-k2g-ice.dtb +-dtb-$(CONFIG_MACH_KIRKWOOD) += \ +- kirkwood-b3.dtb \ +- kirkwood-blackarmor-nas220.dtb \ +- kirkwood-cloudbox.dtb \ +- kirkwood-d2net.dtb \ +- kirkwood-db-88f6281.dtb \ +- kirkwood-db-88f6282.dtb \ +- kirkwood-dir665.dtb \ +- kirkwood-dns320.dtb \ +- kirkwood-dns325.dtb \ +- kirkwood-dockstar.dtb \ +- kirkwood-dreamplug.dtb \ +- kirkwood-ds109.dtb \ +- kirkwood-ds110jv10.dtb \ +- kirkwood-ds111.dtb \ +- kirkwood-ds112.dtb \ +- kirkwood-ds209.dtb \ +- kirkwood-ds210.dtb \ +- kirkwood-ds212.dtb \ +- kirkwood-ds212j.dtb \ +- kirkwood-ds409.dtb \ +- kirkwood-ds409slim.dtb \ +- kirkwood-ds411.dtb \ +- kirkwood-ds411j.dtb \ +- kirkwood-ds411slim.dtb \ +- kirkwood-goflexnet.dtb \ +- kirkwood-guruplug-server-plus.dtb \ +- kirkwood-ib62x0.dtb \ +- kirkwood-iconnect.dtb \ +- kirkwood-iomega_ix2_200.dtb \ +- kirkwood-is2.dtb \ +- kirkwood-km_kirkwood.dtb \ +- kirkwood-l-50.dtb \ +- kirkwood-laplug.dtb \ +- kirkwood-linkstation-lsqvl.dtb \ +- kirkwood-linkstation-lsvl.dtb \ +- kirkwood-linkstation-lswsxl.dtb \ +- kirkwood-linkstation-lswvl.dtb \ +- kirkwood-linkstation-lswxl.dtb \ +- kirkwood-linksys-viper.dtb \ +- kirkwood-lschlv2.dtb \ +- kirkwood-lsxhl.dtb \ +- kirkwood-mplcec4.dtb \ +- kirkwood-mv88f6281gtw-ge.dtb \ +- kirkwood-nas2big.dtb \ +- kirkwood-net2big.dtb \ +- kirkwood-net5big.dtb \ +- kirkwood-netgear_readynas_duo_v2.dtb \ +- kirkwood-netgear_readynas_nv+_v2.dtb \ +- kirkwood-ns2.dtb \ +- kirkwood-ns2lite.dtb \ +- kirkwood-ns2max.dtb \ +- kirkwood-ns2mini.dtb \ +- kirkwood-nsa310.dtb \ +- kirkwood-nsa310a.dtb \ +- kirkwood-nsa320.dtb \ +- kirkwood-nsa325.dtb \ +- kirkwood-openblocks_a6.dtb \ +- kirkwood-openblocks_a7.dtb \ +- kirkwood-openrd-base.dtb \ +- kirkwood-openrd-client.dtb \ +- kirkwood-openrd-ultimate.dtb \ +- kirkwood-pogo_e02.dtb \ +- kirkwood-pogoplug-series-4.dtb \ +- kirkwood-rd88f6192.dtb \ +- kirkwood-rd88f6281-z0.dtb \ +- kirkwood-rd88f6281-a.dtb \ +- kirkwood-rs212.dtb \ +- kirkwood-rs409.dtb \ +- kirkwood-rs411.dtb \ +- kirkwood-sheevaplug.dtb \ +- kirkwood-sheevaplug-esata.dtb \ +- kirkwood-t5325.dtb \ +- kirkwood-topkick.dtb \ +- kirkwood-ts219-6281.dtb \ +- kirkwood-ts219-6282.dtb \ +- kirkwood-ts419-6281.dtb \ +- kirkwood-ts419-6282.dtb +-dtb-$(CONFIG_ARCH_LPC18XX) += \ +- lpc4337-ciaa.dtb \ +- lpc4350-hitex-eval.dtb \ +- lpc4357-ea4357-devkit.dtb \ +- lpc4357-myd-lpc4357.dtb +-dtb-$(CONFIG_ARCH_LPC32XX) += \ +- lpc3250-ea3250.dtb \ +- lpc3250-phy3250.dtb +-dtb-$(CONFIG_ARCH_WPCM450) += \ +- nuvoton-wpcm450-supermicro-x9sci-ln4f.dtb +-dtb-$(CONFIG_ARCH_NPCM7XX) += \ +- nuvoton-npcm730-gsj.dtb \ +- nuvoton-npcm730-gbs.dtb \ +- nuvoton-npcm730-kudo.dtb \ +- nuvoton-npcm750-evb.dtb \ +- nuvoton-npcm750-runbmc-olympus.dtb +-dtb-$(CONFIG_MACH_MESON6) += \ +- meson6-atv1200.dtb +-dtb-$(CONFIG_MACH_MESON8) += \ +- meson8-minix-neo-x8.dtb \ +- meson8b-ec100.dtb \ +- meson8b-mxq.dtb \ +- meson8b-odroidc1.dtb \ +- meson8m2-mxiii-plus.dtb +-dtb-$(CONFIG_ARCH_MMP) += \ +- pxa168-aspenite.dtb \ +- pxa910-dkb.dtb \ +- mmp2-brownstone.dtb \ +- mmp2-olpc-xo-1-75.dtb \ +- mmp3-dell-ariel.dtb +-dtb-$(CONFIG_ARCH_MPS2) += \ +- mps2-an385.dtb \ +- mps2-an399.dtb +-dtb-$(CONFIG_ARCH_MOXART) += \ +- moxart-uc7112lx.dtb +-dtb-$(CONFIG_ARCH_SD5203) += \ +- sd5203.dtb +-dtb-$(CONFIG_SOC_IMX1) += \ +- imx1-ads.dtb \ +- imx1-apf9328.dtb +-dtb-$(CONFIG_SOC_IMX25) += \ +- imx25-eukrea-mbimxsd25-baseboard.dtb \ +- imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \ +- imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \ +- imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dtb \ +- imx25-karo-tx25.dtb \ +- imx25-pdk.dtb +-dtb-$(CONFIG_SOC_IMX27) += \ +- imx27-apf27.dtb \ +- imx27-apf27dev.dtb \ +- imx27-eukrea-mbimxsd27-baseboard.dtb \ +- imx27-pdk.dtb \ +- imx27-phytec-phycore-rdk.dtb \ +- imx27-phytec-phycard-s-rdk.dtb +-dtb-$(CONFIG_SOC_IMX31) += \ +- imx31-bug.dtb \ +- imx31-lite.dtb +-dtb-$(CONFIG_SOC_IMX35) += \ +- imx35-eukrea-mbimxsd35-baseboard.dtb \ +- imx35-pdk.dtb +-dtb-$(CONFIG_SOC_IMX50) += \ +- imx50-evk.dtb \ +- imx50-kobo-aura.dtb +-dtb-$(CONFIG_SOC_IMX51) += \ +- imx51-apf51.dtb \ +- imx51-apf51dev.dtb \ +- imx51-babbage.dtb \ +- imx51-digi-connectcore-jsk.dtb \ +- imx51-eukrea-mbimxsd51-baseboard.dtb \ +- imx51-ts4800.dtb \ +- imx51-zii-rdu1.dtb \ +- imx51-zii-scu2-mezz.dtb \ +- imx51-zii-scu3-esb.dtb +-dtb-$(CONFIG_SOC_IMX53) += \ +- imx53-ard.dtb \ +- imx53-cx9020.dtb \ +- imx53-kp-ddc.dtb \ +- imx53-kp-hsc.dtb \ +- imx53-m53evk.dtb \ +- imx53-m53menlo.dtb \ +- imx53-mba53.dtb \ +- imx53-ppd.dtb \ +- imx53-qsb.dtb \ +- imx53-qsrb.dtb \ +- imx53-smd.dtb \ +- imx53-tx53-x03x.dtb \ +- imx53-tx53-x13x.dtb \ +- imx53-usbarmory.dtb \ +- imx53-voipac-bsb.dtb +-dtb-$(CONFIG_SOC_IMX6Q) += \ +- imx6dl-alti6p.dtb \ +- imx6dl-apf6dev.dtb \ +- imx6dl-aristainetos_4.dtb \ +- imx6dl-aristainetos_7.dtb \ +- imx6dl-aristainetos2_4.dtb \ +- imx6dl-aristainetos2_7.dtb \ +- imx6dl-colibri-eval-v3.dtb \ +- imx6dl-colibri-v1_1-eval-v3.dtb \ +- imx6dl-cubox-i.dtb \ +- imx6dl-cubox-i-emmc-som-v15.dtb \ +- imx6dl-cubox-i-som-v15.dtb \ +- imx6dl-dfi-fs700-m60.dtb \ +- imx6dl-dhcom-picoitx.dtb \ +- imx6dl-eckelmann-ci4x10.dtb \ +- imx6dl-emcon-avari.dtb \ +- imx6dl-gw51xx.dtb \ +- imx6dl-gw52xx.dtb \ +- imx6dl-gw53xx.dtb \ +- imx6dl-gw54xx.dtb \ +- imx6dl-gw551x.dtb \ +- imx6dl-gw552x.dtb \ +- imx6dl-gw553x.dtb \ +- imx6dl-gw560x.dtb \ +- imx6dl-gw5903.dtb \ +- imx6dl-gw5904.dtb \ +- imx6dl-gw5907.dtb \ +- imx6dl-gw5910.dtb \ +- imx6dl-gw5912.dtb \ +- imx6dl-gw5913.dtb \ +- imx6dl-hummingboard.dtb \ +- imx6dl-hummingboard-emmc-som-v15.dtb \ +- imx6dl-hummingboard-som-v15.dtb \ +- imx6dl-hummingboard2.dtb \ +- imx6dl-hummingboard2-emmc-som-v15.dtb \ +- imx6dl-hummingboard2-som-v15.dtb \ +- imx6dl-icore.dtb \ +- imx6dl-icore-mipi.dtb \ +- imx6dl-icore-rqs.dtb \ +- imx6dl-lanmcu.dtb \ +- imx6dl-mamoj.dtb \ +- imx6dl-nit6xlite.dtb \ +- imx6dl-nitrogen6x.dtb \ +- imx6dl-phytec-mira-rdk-nand.dtb \ +- imx6dl-phytec-pbab01.dtb \ +- imx6dl-pico-dwarf.dtb \ +- imx6dl-pico-hobbit.dtb \ +- imx6dl-pico-nymph.dtb \ +- imx6dl-pico-pi.dtb \ +- imx6dl-plybas.dtb \ +- imx6dl-plym2m.dtb \ +- imx6dl-prtmvt.dtb \ +- imx6dl-prtrvt.dtb \ +- imx6dl-prtvt7.dtb \ +- imx6dl-rex-basic.dtb \ +- imx6dl-riotboard.dtb \ +- imx6dl-sabreauto.dtb \ +- imx6dl-sabrelite.dtb \ +- imx6dl-sabresd.dtb \ +- imx6dl-savageboard.dtb \ +- imx6dl-skov-revc-lt2.dtb \ +- imx6dl-skov-revc-lt6.dtb \ +- imx6dl-solidsense.dtb \ +- imx6dl-ts4900.dtb \ +- imx6dl-ts7970.dtb \ +- imx6dl-tx6dl-comtft.dtb \ +- imx6dl-tx6s-8034.dtb \ +- imx6dl-tx6s-8034-mb7.dtb \ +- imx6dl-tx6s-8035.dtb \ +- imx6dl-tx6s-8035-mb7.dtb \ +- imx6dl-tx6u-801x.dtb \ +- imx6dl-tx6u-80xx-mb7.dtb \ +- imx6dl-tx6u-8033.dtb \ +- imx6dl-tx6u-8033-mb7.dtb \ +- imx6dl-tx6u-811x.dtb \ +- imx6dl-tx6u-81xx-mb7.dtb \ +- imx6dl-udoo.dtb \ +- imx6dl-victgo.dtb \ +- imx6dl-vicut1.dtb \ +- imx6dl-wandboard.dtb \ +- imx6dl-wandboard-revb1.dtb \ +- imx6dl-wandboard-revd1.dtb \ +- imx6dl-yapp4-draco.dtb \ +- imx6dl-yapp4-hydra.dtb \ +- imx6dl-yapp4-orion.dtb \ +- imx6dl-yapp4-ursa.dtb \ +- imx6q-apalis-eval.dtb \ +- imx6q-apalis-ixora.dtb \ +- imx6q-apalis-ixora-v1.1.dtb \ +- imx6q-apf6dev.dtb \ +- imx6q-arm2.dtb \ +- imx6q-b450v3.dtb \ +- imx6q-b650v3.dtb \ +- imx6q-b850v3.dtb \ +- imx6q-cm-fx6.dtb \ +- imx6q-cubox-i.dtb \ +- imx6q-cubox-i-emmc-som-v15.dtb \ +- imx6q-cubox-i-som-v15.dtb \ +- imx6q-dfi-fs700-m60.dtb \ +- imx6q-dhcom-pdk2.dtb \ +- imx6q-display5-tianma-tm070-1280x768.dtb \ +- imx6q-dmo-edmqmx6.dtb \ +- imx6q-dms-ba16.dtb \ +- imx6q-ds.dtb \ +- imx6q-emcon-avari.dtb \ +- imx6q-evi.dtb \ +- imx6dl-b105pv2.dtb \ +- imx6dl-b105v2.dtb \ +- imx6dl-b125v2.dtb \ +- imx6dl-b125pv2.dtb \ +- imx6dl-b155v2.dtb \ +- imx6q-gk802.dtb \ +- imx6q-gw51xx.dtb \ +- imx6q-gw52xx.dtb \ +- imx6q-gw53xx.dtb \ +- imx6q-gw5400-a.dtb \ +- imx6q-gw54xx.dtb \ +- imx6q-gw551x.dtb \ +- imx6q-gw552x.dtb \ +- imx6q-gw553x.dtb \ +- imx6q-gw560x.dtb \ +- imx6q-gw5903.dtb \ +- imx6q-gw5904.dtb \ +- imx6q-gw5907.dtb \ +- imx6q-gw5910.dtb \ +- imx6q-gw5912.dtb \ +- imx6q-gw5913.dtb \ +- imx6q-h100.dtb \ +- imx6q-hummingboard.dtb \ +- imx6q-hummingboard-emmc-som-v15.dtb \ +- imx6q-hummingboard-som-v15.dtb \ +- imx6q-hummingboard2.dtb \ +- imx6q-hummingboard2-emmc-som-v15.dtb \ +- imx6q-hummingboard2-som-v15.dtb \ +- imx6q-icore.dtb \ +- imx6q-icore-mipi.dtb \ +- imx6q-icore-ofcap10.dtb \ +- imx6q-icore-ofcap12.dtb \ +- imx6q-icore-rqs.dtb \ +- imx6q-kp-tpc.dtb \ +- imx6q-logicpd.dtb \ +- imx6q-marsboard.dtb \ +- imx6q-mccmon6.dtb \ +- imx6q-nitrogen6x.dtb \ +- imx6q-nitrogen6_max.dtb \ +- imx6q-nitrogen6_som2.dtb \ +- imx6q-novena.dtb \ +- imx6q-phytec-mira-rdk-emmc.dtb \ +- imx6q-phytec-mira-rdk-nand.dtb \ +- imx6q-phytec-pbab01.dtb \ +- imx6q-pico-dwarf.dtb \ +- imx6q-pico-hobbit.dtb \ +- imx6q-pico-nymph.dtb \ +- imx6q-pico-pi.dtb \ +- imx6q-pistachio.dtb \ +- imx6q-prti6q.dtb \ +- imx6q-prtwd2.dtb \ +- imx6q-rex-pro.dtb \ +- imx6q-sabreauto.dtb \ +- imx6q-sabrelite.dtb \ +- imx6q-sabresd.dtb \ +- imx6q-savageboard.dtb \ +- imx6q-sbc6x.dtb \ +- imx6q-skov-revc-lt2.dtb \ +- imx6q-skov-revc-lt6.dtb \ +- imx6q-skov-reve-mi1010ait-1cp1.dtb \ +- imx6q-solidsense.dtb \ +- imx6q-tbs2910.dtb \ +- imx6q-ts4900.dtb \ +- imx6q-ts7970.dtb \ +- imx6q-tx6q-1010.dtb \ +- imx6q-tx6q-1010-comtft.dtb \ +- imx6q-tx6q-1020.dtb \ +- imx6q-tx6q-1020-comtft.dtb \ +- imx6q-tx6q-1036.dtb \ +- imx6q-tx6q-1036-mb7.dtb \ +- imx6q-tx6q-10x0-mb7.dtb \ +- imx6q-tx6q-1110.dtb \ +- imx6q-tx6q-11x0-mb7.dtb \ +- imx6q-udoo.dtb \ +- imx6q-utilite-pro.dtb \ +- imx6q-var-dt6customboard.dtb \ +- imx6q-vicut1.dtb \ +- imx6q-wandboard.dtb \ +- imx6q-wandboard-revb1.dtb \ +- imx6q-wandboard-revd1.dtb \ +- imx6q-zii-rdu2.dtb \ +- imx6qp-nitrogen6_max.dtb \ +- imx6qp-nitrogen6_som2.dtb \ +- imx6qp-phytec-mira-rdk-nand.dtb \ +- imx6qp-prtwd3.dtb \ +- imx6qp-sabreauto.dtb \ +- imx6qp-sabresd.dtb \ +- imx6qp-tx6qp-8037.dtb \ +- imx6qp-tx6qp-8037-mb7.dtb \ +- imx6qp-tx6qp-8137.dtb \ +- imx6qp-tx6qp-8137-mb7.dtb \ +- imx6qp-vicutp.dtb \ +- imx6qp-wandboard-revd1.dtb \ +- imx6qp-zii-rdu2.dtb \ +- imx6s-dhcom-drc02.dtb +-dtb-$(CONFIG_SOC_IMX6SL) += \ +- imx6sl-evk.dtb \ +- imx6sl-tolino-shine2hd.dtb \ +- imx6sl-tolino-shine3.dtb \ +- imx6sl-warp.dtb +-dtb-$(CONFIG_SOC_IMX6SLL) += \ +- imx6sll-evk.dtb \ +- imx6sll-kobo-clarahd.dtb +-dtb-$(CONFIG_SOC_IMX6SX) += \ +- imx6sx-nitrogen6sx.dtb \ +- imx6sx-sabreauto.dtb \ +- imx6sx-sdb-reva.dtb \ +- imx6sx-sdb-sai.dtb \ +- imx6sx-sdb.dtb \ +- imx6sx-sdb-mqs.dtb \ +- imx6sx-softing-vining-2000.dtb \ +- imx6sx-udoo-neo-basic.dtb \ +- imx6sx-udoo-neo-extended.dtb \ +- imx6sx-udoo-neo-full.dtb +-dtb-$(CONFIG_SOC_IMX6UL) += \ +- imx6ul-14x14-evk.dtb \ +- imx6ul-ccimx6ulsbcexpress.dtb \ +- imx6ul-ccimx6ulsbcpro.dtb \ +- imx6ul-geam.dtb \ +- imx6ul-isiot-emmc.dtb \ +- imx6ul-isiot-nand.dtb \ +- imx6ul-kontron-n6310-s.dtb \ +- imx6ul-kontron-n6310-s-43.dtb \ +- imx6ul-liteboard.dtb \ +- imx6ul-opos6uldev.dtb \ +- imx6ul-pico-dwarf.dtb \ +- imx6ul-pico-hobbit.dtb \ +- imx6ul-pico-pi.dtb \ +- imx6ul-phytec-segin-ff-rdk-emmc.dtb \ +- imx6ul-phytec-segin-ff-rdk-nand.dtb \ +- imx6ul-prti6g.dtb \ +- imx6ul-tx6ul-0010.dtb \ +- imx6ul-tx6ul-0011.dtb \ +- imx6ul-tx6ul-mainboard.dtb \ +- imx6ull-14x14-evk.dtb \ +- imx6ull-colibri-eval-v3.dtb \ +- imx6ull-colibri-wifi-eval-v3.dtb \ +- imx6ull-myir-mys-6ulx-eval.dtb \ +- imx6ull-opos6uldev.dtb \ +- imx6ull-phytec-segin-ff-rdk-nand.dtb \ +- imx6ull-phytec-segin-ff-rdk-emmc.dtb \ +- imx6ull-phytec-segin-lc-rdk-nand.dtb \ +- imx6ulz-14x14-evk.dtb +-dtb-$(CONFIG_SOC_IMX7D) += \ +- imx7d-cl-som-imx7.dtb \ +- imx7d-colibri-aster.dtb \ +- imx7d-colibri-emmc-aster.dtb \ +- imx7d-colibri-emmc-eval-v3.dtb \ +- imx7d-colibri-eval-v3.dtb \ +- imx7d-flex-concentrator.dtb \ +- imx7d-flex-concentrator-mfg.dtb \ +- imx7d-mba7.dtb \ +- imx7d-meerkat96.dtb \ +- imx7d-nitrogen7.dtb \ +- imx7d-pico-dwarf.dtb \ +- imx7d-pico-hobbit.dtb \ +- imx7d-pico-nymph.dtb \ +- imx7d-pico-pi.dtb \ +- imx7d-remarkable2.dtb \ +- imx7d-sbc-imx7.dtb \ +- imx7d-sdb.dtb \ +- imx7d-sdb-reva.dtb \ +- imx7d-sdb-sht11.dtb \ +- imx7d-zii-rmu2.dtb \ +- imx7d-zii-rpu2.dtb \ +- imx7s-colibri-aster.dtb \ +- imx7s-colibri-eval-v3.dtb \ +- imx7s-mba7.dtb \ +- imx7s-warp.dtb +-dtb-$(CONFIG_SOC_IMX7ULP) += \ +- imx7ulp-com.dtb \ +- imx7ulp-evk.dtb +-dtb-$(CONFIG_SOC_LS1021A) += \ +- ls1021a-moxa-uc-8410a.dtb \ +- ls1021a-qds.dtb \ +- ls1021a-tsn.dtb \ +- ls1021a-twr.dtb +-dtb-$(CONFIG_SOC_VF610) += \ +- vf500-colibri-eval-v3.dtb \ +- vf610-bk4.dtb \ +- vf610-colibri-eval-v3.dtb \ +- vf610m4-colibri.dtb \ +- vf610-cosmic.dtb \ +- vf610m4-cosmic.dtb \ +- vf610-twr.dtb \ +- vf610-zii-cfu1.dtb \ +- vf610-zii-dev-rev-b.dtb \ +- vf610-zii-dev-rev-c.dtb \ +- vf610-zii-scu4-aib.dtb \ +- vf610-zii-spb4.dtb \ +- vf610-zii-ssmb-dtu.dtb \ +- vf610-zii-ssmb-spu3.dtb +-dtb-$(CONFIG_ARCH_MXS) += \ +- imx23-evk.dtb \ +- imx23-olinuxino.dtb \ +- imx23-sansa.dtb \ +- imx23-stmp378x_devb.dtb \ +- imx23-xfi3.dtb \ +- imx28-apf28.dtb \ +- imx28-apf28dev.dtb \ +- imx28-apx4devkit.dtb \ +- imx28-cfa10036.dtb \ +- imx28-cfa10037.dtb \ +- imx28-cfa10049.dtb \ +- imx28-cfa10055.dtb \ +- imx28-cfa10056.dtb \ +- imx28-cfa10057.dtb \ +- imx28-cfa10058.dtb \ +- imx28-duckbill-2-485.dtb \ +- imx28-duckbill-2.dtb \ +- imx28-duckbill-2-enocean.dtb \ +- imx28-duckbill-2-spi.dtb \ +- imx28-duckbill.dtb \ +- imx28-eukrea-mbmx283lc.dtb \ +- imx28-eukrea-mbmx287lc.dtb \ +- imx28-evk.dtb \ +- imx28-m28cu3.dtb \ +- imx28-m28evk.dtb \ +- imx28-sps1.dtb \ +- imx28-ts4600.dtb \ +- imx28-tx28.dtb \ +- imx28-xea.dtb +-dtb-$(CONFIG_ARCH_NOMADIK) += \ +- ste-nomadik-s8815.dtb \ +- ste-nomadik-nhk15.dtb +-dtb-$(CONFIG_ARCH_NSPIRE) += \ +- nspire-cx.dtb \ +- nspire-tp.dtb \ +- nspire-clp.dtb +-dtb-$(CONFIG_ARCH_OMAP2) += \ +- omap2420-h4.dtb \ +- omap2420-n800.dtb \ +- omap2420-n810.dtb \ +- omap2420-n810-wimax.dtb \ +- omap2430-sdp.dtb +-dtb-$(CONFIG_ARCH_OMAP3) += \ +- am3517-craneboard.dtb \ +- am3517-evm.dtb \ +- am3517_mt_ventoux.dtb \ +- logicpd-torpedo-37xx-devkit.dtb \ +- logicpd-som-lv-37xx-devkit.dtb \ +- omap3430-sdp.dtb \ +- omap3-beagle.dtb \ +- omap3-beagle-ab4.dtb \ +- omap3-beagle-xm.dtb \ +- omap3-beagle-xm-ab.dtb \ +- omap3-cm-t3517.dtb \ +- omap3-cm-t3530.dtb \ +- omap3-cm-t3730.dtb \ +- omap3-devkit8000.dtb \ +- omap3-devkit8000-lcd43.dtb \ +- omap3-devkit8000-lcd70.dtb \ +- omap3-echo.dtb \ +- omap3-evm.dtb \ +- omap3-evm-37xx.dtb \ +- omap3-gta04a3.dtb \ +- omap3-gta04a4.dtb \ +- omap3-gta04a5.dtb \ +- omap3-gta04a5one.dtb \ +- omap3-ha.dtb \ +- omap3-ha-lcd.dtb \ +- omap3-igep0020.dtb \ +- omap3-igep0020-rev-f.dtb \ +- omap3-igep0030.dtb \ +- omap3-igep0030-rev-g.dtb \ +- omap3-ldp.dtb \ +- omap3-lilly-dbb056.dtb \ +- omap3-n900.dtb \ +- omap3-n9.dtb \ +- omap3-n950.dtb \ +- omap3-overo-alto35.dtb \ +- omap3-overo-chestnut43.dtb \ +- omap3-overo-gallop43.dtb \ +- omap3-overo-palo35.dtb \ +- omap3-overo-palo43.dtb \ +- omap3-overo-storm-alto35.dtb \ +- omap3-overo-storm-chestnut43.dtb \ +- omap3-overo-storm-gallop43.dtb \ +- omap3-overo-storm-palo35.dtb \ +- omap3-overo-storm-palo43.dtb \ +- omap3-overo-storm-summit.dtb \ +- omap3-overo-storm-tobi.dtb \ +- omap3-overo-storm-tobiduo.dtb \ +- omap3-overo-summit.dtb \ +- omap3-overo-tobi.dtb \ +- omap3-overo-tobiduo.dtb \ +- omap3-pandora-600mhz.dtb \ +- omap3-pandora-1ghz.dtb \ +- omap3-sbc-t3517.dtb \ +- omap3-sbc-t3530.dtb \ +- omap3-sbc-t3730.dtb \ +- omap3-sniper.dtb \ +- omap3-thunder.dtb \ +- omap3-zoom3.dtb +-dtb-$(CONFIG_SOC_TI81XX) += \ +- am3874-iceboard.dtb \ +- dm8148-evm.dtb \ +- dm8148-t410.dtb \ +- dm8168-evm.dtb \ +- dra62x-j5eco-evm.dtb +-dtb-$(CONFIG_SOC_AM33XX) += \ +- am335x-baltos-ir2110.dtb \ +- am335x-baltos-ir3220.dtb \ +- am335x-baltos-ir5221.dtb \ +- am335x-base0033.dtb \ +- am335x-bone.dtb \ +- am335x-boneblack.dtb \ +- am335x-boneblack-wireless.dtb \ +- am335x-boneblue.dtb \ +- am335x-bonegreen.dtb \ +- am335x-bonegreen-wireless.dtb \ +- am335x-chiliboard.dtb \ +- am335x-cm-t335.dtb \ +- am335x-evm.dtb \ +- am335x-evmsk.dtb \ +- am335x-guardian.dtb \ +- am335x-icev2.dtb \ +- am335x-lxm.dtb \ +- am335x-moxa-uc-2101.dtb \ +- am335x-moxa-uc-8100-me-t.dtb \ +- am335x-myirtech-myd.dtb \ +- am335x-nano.dtb \ +- am335x-netcan-plus-1xx.dtb \ +- am335x-netcom-plus-2xx.dtb \ +- am335x-netcom-plus-8xx.dtb \ +- am335x-pdu001.dtb \ +- am335x-pepper.dtb \ +- am335x-phycore-rdk.dtb \ +- am335x-pocketbeagle.dtb \ +- am335x-regor-rdk.dtb \ +- am335x-sancloud-bbe.dtb \ +- am335x-sancloud-bbe-lite.dtb \ +- am335x-shc.dtb \ +- am335x-sbc-t335.dtb \ +- am335x-sl50.dtb \ +- am335x-wega-rdk.dtb \ +- am335x-osd3358-sm-red.dtb +-dtb-$(CONFIG_ARCH_OMAP4) += \ +- omap4-droid-bionic-xt875.dtb \ +- omap4-droid4-xt894.dtb \ +- omap4-duovero-parlor.dtb \ +- omap4-kc1.dtb \ +- omap4-panda.dtb \ +- omap4-panda-a4.dtb \ +- omap4-panda-es.dtb \ +- omap4-sdp.dtb \ +- omap4-sdp-es23plus.dtb \ +- omap4-var-dvk-om44.dtb \ +- omap4-var-stk-om44.dtb +-dtb-$(CONFIG_SOC_AM43XX) += \ +- am43x-epos-evm.dtb \ +- am437x-cm-t43.dtb \ +- am437x-gp-evm.dtb \ +- am437x-idk-evm.dtb \ +- am437x-sbc-t43.dtb \ +- am437x-sk-evm.dtb +-dtb-$(CONFIG_SOC_OMAP5) += \ +- omap5-cm-t54.dtb \ +- omap5-igep0050.dtb \ +- omap5-sbc-t54.dtb \ +- omap5-uevm.dtb +-dtb-$(CONFIG_SOC_DRA7XX) += \ +- am57xx-beagle-x15.dtb \ +- am57xx-beagle-x15-revb1.dtb \ +- am57xx-beagle-x15-revc.dtb \ +- am5729-beagleboneai.dtb \ +- am57xx-cl-som-am57x.dtb \ +- am57xx-sbc-am57x.dtb \ +- am572x-idk.dtb \ +- am571x-idk.dtb \ +- am574x-idk.dtb \ +- dra7-evm.dtb \ +- dra72-evm.dtb \ +- dra72-evm-revc.dtb \ +- dra71-evm.dtb \ +- dra76-evm.dtb +-dtb-$(CONFIG_ARCH_ORION5X) += \ +- orion5x-kuroboxpro.dtb \ +- orion5x-lacie-d2-network.dtb \ +- orion5x-lacie-ethernet-disk-mini-v2.dtb \ +- orion5x-linkstation-lsgl.dtb \ +- orion5x-linkstation-lswtgl.dtb \ +- orion5x-linkstation-lschl.dtb \ +- orion5x-lswsgl.dtb \ +- orion5x-maxtor-shared-storage-2.dtb \ +- orion5x-netgear-wnr854t.dtb \ +- orion5x-rd88f5182-nas.dtb +-dtb-$(CONFIG_ARCH_ACTIONS) += \ +- owl-s500-cubieboard6.dtb \ +- owl-s500-guitar-bb-rev-b.dtb \ +- owl-s500-labrador-base-m.dtb \ +- owl-s500-roseapplepi.dtb \ +- owl-s500-sparky.dtb +-dtb-$(CONFIG_ARCH_PXA) += \ +- pxa300-raumfeld-connector.dtb \ +- pxa300-raumfeld-controller.dtb \ +- pxa300-raumfeld-speaker-l.dtb \ +- pxa300-raumfeld-speaker-m.dtb \ +- pxa300-raumfeld-speaker-one.dtb \ +- pxa300-raumfeld-speaker-s.dtb +-dtb-$(CONFIG_ARCH_OXNAS) += \ +- ox810se-wd-mbwe.dtb \ +- ox820-cloudengines-pogoplug-series-3.dtb +-dtb-$(CONFIG_ARCH_QCOM) += \ +- qcom-apq8060-dragonboard.dtb \ +- qcom-apq8064-cm-qs600.dtb \ +- qcom-apq8064-ifc6410.dtb \ +- qcom-apq8064-sony-xperia-yuga.dtb \ +- qcom-apq8064-asus-nexus7-flo.dtb \ +- qcom-apq8074-dragonboard.dtb \ +- qcom-apq8084-ifc6540.dtb \ +- qcom-apq8084-mtp.dtb \ +- qcom-ipq4018-ap120c-ac.dtb \ +- qcom-ipq4018-ap120c-ac-bit.dtb \ +- qcom-ipq4018-jalapeno.dtb \ +- qcom-ipq4019-ap.dk01.1-c1.dtb \ +- qcom-ipq4019-ap.dk04.1-c1.dtb \ +- qcom-ipq4019-ap.dk04.1-c3.dtb \ +- qcom-ipq4019-ap.dk07.1-c1.dtb \ +- qcom-ipq4019-ap.dk07.1-c2.dtb \ +- qcom-ipq8064-ap148.dtb \ +- qcom-ipq8064-rb3011.dtb \ +- qcom-msm8226-samsung-s3ve3g.dtb \ +- qcom-msm8660-surf.dtb \ +- qcom-msm8960-cdp.dtb \ +- qcom-msm8974-fairphone-fp2.dtb \ +- qcom-msm8974-lge-nexus5-hammerhead.dtb \ +- qcom-msm8974-samsung-klte.dtb \ +- qcom-msm8974-sony-xperia-amami.dtb \ +- qcom-msm8974-sony-xperia-castor.dtb \ +- qcom-msm8974-sony-xperia-honami.dtb \ +- qcom-mdm9615-wp8548-mangoh-green.dtb \ +- qcom-sdx55-mtp.dtb \ +- qcom-sdx55-t55.dtb \ +- qcom-sdx55-telit-fn980-tlb.dtb +-dtb-$(CONFIG_ARCH_RDA) += \ +- rda8810pl-orangepi-2g-iot.dtb \ +- rda8810pl-orangepi-i96.dtb +-dtb-$(CONFIG_ARCH_REALTEK) += \ +- rtd1195-horseradish.dtb \ +- rtd1195-mele-x1000.dtb +-dtb-$(CONFIG_ARCH_REALVIEW) += \ +- arm-realview-pb1176.dtb \ +- arm-realview-pb11mp.dtb \ +- arm-realview-eb.dtb \ +- arm-realview-eb-bbrevd.dtb \ +- arm-realview-eb-11mp.dtb \ +- arm-realview-eb-11mp-bbrevd.dtb \ +- arm-realview-eb-11mp-ctrevb.dtb \ +- arm-realview-eb-11mp-bbrevd-ctrevb.dtb \ +- arm-realview-eb-a9mp.dtb \ +- arm-realview-eb-a9mp-bbrevd.dtb \ +- arm-realview-pba8.dtb \ +- arm-realview-pbx-a9.dtb +-dtb-$(CONFIG_ARCH_RENESAS) += \ +- emev2-kzm9d.dtb \ +- r7s72100-genmai.dtb \ +- r7s72100-gr-peach.dtb \ +- r7s72100-rskrza1.dtb \ +- r7s9210-rza2mevb.dtb \ +- r8a73a4-ape6evm.dtb \ +- r8a7740-armadillo800eva.dtb \ +- r8a7742-iwg21d-q7.dtb \ +- r8a7742-iwg21d-q7-dbcm-ca.dtb \ +- r8a7743-iwg20d-q7.dtb \ +- r8a7743-iwg20d-q7-dbcm-ca.dtb \ +- r8a7743-sk-rzg1m.dtb \ +- r8a7744-iwg20d-q7.dtb \ +- r8a7744-iwg20d-q7-dbcm-ca.dtb \ +- r8a7745-iwg22d-sodimm.dtb \ +- r8a7745-iwg22d-sodimm-dbhd-ca.dtb \ +- r8a7745-sk-rzg1e.dtb \ +- r8a77470-iwg23s-sbc.dtb \ +- r8a7778-bockw.dtb \ +- r8a7779-marzen.dtb \ +- r8a7790-lager.dtb \ +- r8a7790-stout.dtb \ +- r8a7791-koelsch.dtb \ +- r8a7791-porter.dtb \ +- r8a7792-blanche.dtb \ +- r8a7792-wheat.dtb \ +- r8a7793-gose.dtb \ +- r8a7794-alt.dtb \ +- r8a7794-silk.dtb \ +- r9a06g032-rzn1d400-db.dtb \ +- sh73a0-kzm9g.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += \ +- rv1108-elgin-r1.dtb \ +- rv1108-evb.dtb \ +- rk3036-evb.dtb \ +- rk3036-kylin.dtb \ +- rk3066a-bqcurie2.dtb \ +- rk3066a-marsboard.dtb \ +- rk3066a-mk808.dtb \ +- rk3066a-rayeager.dtb \ +- rk3188-bqedison2qc.dtb \ +- rk3188-px3-evb.dtb \ +- rk3188-radxarock.dtb \ +- rk3228-evb.dtb \ +- rk3229-evb.dtb \ +- rk3229-xms6.dtb \ +- rk3288-evb-act8846.dtb \ +- rk3288-evb-rk808.dtb \ +- rk3288-firefly-beta.dtb \ +- rk3288-firefly.dtb \ +- rk3288-firefly-reload.dtb \ +- rk3288-miqi.dtb \ +- rk3288-phycore-rdk.dtb \ +- rk3288-popmetal.dtb \ +- rk3288-r89.dtb \ +- rk3288-rock2-square.dtb \ +- rk3288-rock-pi-n8.dtb \ +- rk3288-tinker.dtb \ +- rk3288-tinker-s.dtb \ +- rk3288-veyron-brain.dtb \ +- rk3288-veyron-fievel.dtb \ +- rk3288-veyron-jaq.dtb \ +- rk3288-veyron-jerry.dtb \ +- rk3288-veyron-mickey.dtb \ +- rk3288-veyron-mighty.dtb \ +- rk3288-veyron-minnie.dtb \ +- rk3288-veyron-pinky.dtb \ +- rk3288-veyron-speedy.dtb \ +- rk3288-veyron-tiger.dtb \ +- rk3288-vyasa.dtb +-dtb-$(CONFIG_ARCH_S3C24XX) += \ +- s3c2416-smdk2416.dtb +-dtb-$(CONFIG_ARCH_S3C64XX) += \ +- s3c6410-mini6410.dtb \ +- s3c6410-smdk6410.dtb +-dtb-$(CONFIG_ARCH_S5PV210) += \ +- s5pv210-aquila.dtb \ +- s5pv210-fascinate4g.dtb \ +- s5pv210-galaxys.dtb \ +- s5pv210-goni.dtb \ +- s5pv210-smdkc110.dtb \ +- s5pv210-smdkv210.dtb \ +- s5pv210-torbreck.dtb +-dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ +- socfpga_arria5_socdk.dtb \ +- socfpga_arria10_socdk_nand.dtb \ +- socfpga_arria10_socdk_qspi.dtb \ +- socfpga_arria10_socdk_sdmmc.dtb \ +- socfpga_cyclone5_chameleon96.dtb \ +- socfpga_cyclone5_mcvevk.dtb \ +- socfpga_cyclone5_socdk.dtb \ +- socfpga_cyclone5_de0_nano_soc.dtb \ +- socfpga_cyclone5_sockit.dtb \ +- socfpga_cyclone5_socrates.dtb \ +- socfpga_cyclone5_sodia.dtb \ +- socfpga_cyclone5_vining_fpga.dtb \ +- socfpga_vt.dtb +-dtb-$(CONFIG_ARCH_SPEAR13XX) += \ +- spear1310-evb.dtb \ +- spear1340-evb.dtb +-dtb-$(CONFIG_ARCH_SPEAR3XX) += \ +- spear300-evb.dtb \ +- spear310-evb.dtb \ +- spear320-evb.dtb \ +- spear320-hmi.dtb +-dtb-$(CONFIG_ARCH_SPEAR6XX) += \ +- spear600-evb.dtb +-dtb-$(CONFIG_ARCH_STI) += \ +- stih407-b2120.dtb \ +- stih410-b2120.dtb \ +- stih410-b2260.dtb \ +- stih418-b2199.dtb \ +- stih418-b2264.dtb +-dtb-$(CONFIG_ARCH_STM32) += \ +- stm32f429-disco.dtb \ +- stm32f469-disco.dtb \ +- stm32f746-disco.dtb \ +- stm32f769-disco.dtb \ +- stm32429i-eval.dtb \ +- stm32746g-eval.dtb \ +- stm32h743i-eval.dtb \ +- stm32h743i-disco.dtb \ +- stm32h750i-art-pi.dtb \ +- stm32mp153c-dhcom-drc02.dtb \ +- stm32mp157a-avenger96.dtb \ +- stm32mp157a-dhcor-avenger96.dtb \ +- stm32mp157a-dk1.dtb \ +- stm32mp157a-iot-box.dtb \ +- stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ +- stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ +- stm32mp157a-icore-stm32mp1-ctouch2.dtb \ +- stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ +- stm32mp157a-stinger96.dtb \ +- stm32mp157c-dhcom-pdk2.dtb \ +- stm32mp157c-dhcom-picoitx.dtb \ +- stm32mp157c-dk2.dtb \ +- stm32mp157c-ed1.dtb \ +- stm32mp157c-ev1.dtb \ +- stm32mp157c-lxa-mc1.dtb \ +- stm32mp157c-odyssey.dtb +-dtb-$(CONFIG_MACH_SUN4I) += \ +- sun4i-a10-a1000.dtb \ +- sun4i-a10-ba10-tvbox.dtb \ +- sun4i-a10-chuwi-v7-cw0825.dtb \ +- sun4i-a10-cubieboard.dtb \ +- sun4i-a10-dserve-dsrv9703c.dtb \ +- sun4i-a10-gemei-g9.dtb \ +- sun4i-a10-hackberry.dtb \ +- sun4i-a10-hyundai-a7hd.dtb \ +- sun4i-a10-inet1.dtb \ +- sun4i-a10-inet97fv2.dtb \ +- sun4i-a10-inet9f-rev03.dtb \ +- sun4i-a10-itead-iteaduino-plus.dtb \ +- sun4i-a10-jesurun-q5.dtb \ +- sun4i-a10-marsboard.dtb \ +- sun4i-a10-mini-xplus.dtb \ +- sun4i-a10-mk802.dtb \ +- sun4i-a10-mk802ii.dtb \ +- sun4i-a10-olinuxino-lime.dtb \ +- sun4i-a10-pcduino.dtb \ +- sun4i-a10-pcduino2.dtb \ +- sun4i-a10-pov-protab2-ips9.dtb \ +- sun4i-a10-topwise-a721.dtb +-dtb-$(CONFIG_MACH_SUN5I) += \ +- sun5i-a10s-auxtek-t003.dtb \ +- sun5i-a10s-auxtek-t004.dtb \ +- sun5i-a10s-mk802.dtb \ +- sun5i-a10s-olinuxino-micro.dtb \ +- sun5i-a10s-r7-tv-dongle.dtb \ +- sun5i-a10s-wobo-i5.dtb \ +- sun5i-a13-difrnce-dit4350.dtb \ +- sun5i-a13-empire-electronix-d709.dtb \ +- sun5i-a13-empire-electronix-m712.dtb \ +- sun5i-a13-hsg-h702.dtb \ +- sun5i-a13-inet-98v-rev2.dtb \ +- sun5i-a13-licheepi-one.dtb \ +- sun5i-a13-olinuxino.dtb \ +- sun5i-a13-olinuxino-micro.dtb \ +- sun5i-a13-pocketbook-touch-lux-3.dtb \ +- sun5i-a13-q8-tablet.dtb \ +- sun5i-a13-utoo-p66.dtb \ +- sun5i-gr8-chip-pro.dtb \ +- sun5i-gr8-evb.dtb \ +- sun5i-r8-chip.dtb +-dtb-$(CONFIG_MACH_SUN6I) += \ +- sun6i-a31-app4-evb1.dtb \ +- sun6i-a31-colombus.dtb \ +- sun6i-a31-hummingbird.dtb \ +- sun6i-a31-i7.dtb \ +- sun6i-a31-m9.dtb \ +- sun6i-a31-mele-a1000g-quad.dtb \ +- sun6i-a31s-colorfly-e708-q1.dtb \ +- sun6i-a31s-cs908.dtb \ +- sun6i-a31s-inet-q972.dtb \ +- sun6i-a31s-primo81.dtb \ +- sun6i-a31s-sina31s.dtb \ +- sun6i-a31s-sinovoip-bpi-m2.dtb \ +- sun6i-a31s-yones-toptech-bs1078-v2.dtb +-dtb-$(CONFIG_MACH_SUN7I) += \ +- sun7i-a20-bananapi.dtb \ +- sun7i-a20-bananapi-m1-plus.dtb \ +- sun7i-a20-bananapro.dtb \ +- sun7i-a20-cubieboard2.dtb \ +- sun7i-a20-cubietruck.dtb \ +- sun7i-a20-hummingbird.dtb \ +- sun7i-a20-itead-ibox.dtb \ +- sun7i-a20-i12-tvbox.dtb \ +- sun7i-a20-icnova-swac.dtb \ +- sun7i-a20-lamobo-r1.dtb \ +- sun7i-a20-linutronix-testbox-v2.dtb \ +- sun7i-a20-m3.dtb \ +- sun7i-a20-mk808c.dtb \ +- sun7i-a20-olimex-som-evb.dtb \ +- sun7i-a20-olimex-som-evb-emmc.dtb \ +- sun7i-a20-olimex-som204-evb.dtb \ +- sun7i-a20-olimex-som204-evb-emmc.dtb \ +- sun7i-a20-olinuxino-lime.dtb \ +- sun7i-a20-olinuxino-lime-emmc.dtb \ +- sun7i-a20-olinuxino-lime2.dtb \ +- sun7i-a20-olinuxino-lime2-emmc.dtb \ +- sun7i-a20-olinuxino-micro.dtb \ +- sun7i-a20-olinuxino-micro-emmc.dtb \ +- sun7i-a20-orangepi.dtb \ +- sun7i-a20-orangepi-mini.dtb \ +- sun7i-a20-pcduino3.dtb \ +- sun7i-a20-pcduino3-nano.dtb \ +- sun7i-a20-wexler-tab7200.dtb \ +- sun7i-a20-wits-pro-a20-dkt.dtb +-dtb-$(CONFIG_MACH_SUN8I) += \ +- sun8i-a23-evb.dtb \ +- sun8i-a23-gt90h-v4.dtb \ +- sun8i-a23-inet86dz.dtb \ +- sun8i-a23-ippo-q8h-v5.dtb \ +- sun8i-a23-ippo-q8h-v1.2.dtb \ +- sun8i-a23-polaroid-mid2407pxe03.dtb \ +- sun8i-a23-polaroid-mid2809pxe04.dtb \ +- sun8i-a23-q8-tablet.dtb \ +- sun8i-a33-et-q8-v1.6.dtb \ +- sun8i-a33-ga10h-v1.1.dtb \ +- sun8i-a33-inet-d978-rev2.dtb \ +- sun8i-a33-ippo-q8h-v1.2.dtb \ +- sun8i-a33-olinuxino.dtb \ +- sun8i-a33-q8-tablet.dtb \ +- sun8i-a33-sinlinx-sina33.dtb \ +- sun8i-a83t-allwinner-h8homlet-v2.dtb \ +- sun8i-a83t-bananapi-m3.dtb \ +- sun8i-a83t-cubietruck-plus.dtb \ +- sun8i-a83t-tbs-a711.dtb \ +- sun8i-h2-plus-bananapi-m2-zero.dtb \ +- sun8i-h2-plus-libretech-all-h3-cc.dtb \ +- sun8i-h2-plus-orangepi-r1.dtb \ +- sun8i-h2-plus-orangepi-zero.dtb \ +- sun8i-h3-bananapi-m2-plus.dtb \ +- sun8i-h3-bananapi-m2-plus-v1.2.dtb \ +- sun8i-h3-beelink-x2.dtb \ +- sun8i-h3-libretech-all-h3-cc.dtb \ +- sun8i-h3-mapleboard-mp130.dtb \ +- sun8i-h3-nanopi-duo2.dtb \ +- sun8i-h3-nanopi-m1.dtb \ +- sun8i-h3-nanopi-m1-plus.dtb \ +- sun8i-h3-nanopi-neo.dtb \ +- sun8i-h3-nanopi-neo-air.dtb \ +- sun8i-h3-nanopi-r1.dtb \ +- sun8i-h3-orangepi-2.dtb \ +- sun8i-h3-orangepi-lite.dtb \ +- sun8i-h3-orangepi-one.dtb \ +- sun8i-h3-orangepi-pc.dtb \ +- sun8i-h3-orangepi-pc-plus.dtb \ +- sun8i-h3-orangepi-plus.dtb \ +- sun8i-h3-orangepi-plus2e.dtb \ +- sun8i-h3-orangepi-zero-plus2.dtb \ +- sun8i-h3-rervision-dvk.dtb \ +- sun8i-h3-zeropi.dtb \ +- sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ +- sun8i-r16-bananapi-m2m.dtb \ +- sun8i-r16-nintendo-nes-classic.dtb \ +- sun8i-r16-nintendo-super-nes-classic.dtb \ +- sun8i-r16-parrot.dtb \ +- sun8i-r40-bananapi-m2-ultra.dtb \ +- sun8i-r40-oka40i-c.dtb \ +- sun8i-s3-elimo-initium.dtb \ +- sun8i-s3-lichee-zero-plus.dtb \ +- sun8i-s3-pinecube.dtb \ +- sun8i-t3-cqa3t-bv3.dtb \ +- sun8i-v3-sl631-imx179.dtb \ +- sun8i-v3s-licheepi-zero.dtb \ +- sun8i-v3s-licheepi-zero-dock.dtb \ +- sun8i-v40-bananapi-m2-berry.dtb +-dtb-$(CONFIG_MACH_SUN9I) += \ +- sun9i-a80-optimus.dtb \ +- sun9i-a80-cubieboard4.dtb +-dtb-$(CONFIG_MACH_SUNIV) += \ +- suniv-f1c100s-licheepi-nano.dtb +-dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ +- tegra20-acer-a500-picasso.dtb \ +- tegra20-harmony.dtb \ +- tegra20-colibri-eval-v3.dtb \ +- tegra20-colibri-iris.dtb \ +- tegra20-medcom-wide.dtb \ +- tegra20-paz00.dtb \ +- tegra20-plutux.dtb \ +- tegra20-seaboard.dtb \ +- tegra20-tec.dtb \ +- tegra20-trimslice.dtb \ +- tegra20-ventana.dtb +-dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ +- tegra30-apalis-eval.dtb \ +- tegra30-apalis-v1.1-eval.dtb \ +- tegra30-asus-nexus7-grouper-PM269.dtb \ +- tegra30-asus-nexus7-grouper-E1565.dtb \ +- tegra30-asus-nexus7-tilapia-E1565.dtb \ +- tegra30-beaver.dtb \ +- tegra30-cardhu-a02.dtb \ +- tegra30-cardhu-a04.dtb \ +- tegra30-colibri-eval-v3.dtb \ +- tegra30-ouya.dtb +-dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ +- tegra114-dalmore.dtb \ +- tegra114-roth.dtb \ +- tegra114-tn7.dtb +-dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ +- tegra124-apalis-eval.dtb \ +- tegra124-apalis-v1.2-eval.dtb \ +- tegra124-jetson-tk1.dtb \ +- tegra124-nyan-big.dtb \ +- tegra124-nyan-blaze.dtb \ +- tegra124-venice2.dtb +-dtb-$(CONFIG_ARCH_U8500) += \ +- ste-snowball.dtb \ +- ste-hrefprev60-stuib.dtb \ +- ste-hrefprev60-tvk.dtb \ +- ste-hrefv60plus-stuib.dtb \ +- ste-hrefv60plus-tvk.dtb \ +- ste-href520-tvk.dtb \ +- ste-ux500-samsung-golden.dtb \ +- ste-ux500-samsung-janice.dtb \ +- ste-ux500-samsung-gavini.dtb \ +- ste-ux500-samsung-codina.dtb \ +- ste-ux500-samsung-skomer.dtb \ +- ste-ux500-samsung-kyle.dtb +-dtb-$(CONFIG_ARCH_UNIPHIER) += \ +- uniphier-ld4-ref.dtb \ +- uniphier-ld6b-ref.dtb \ +- uniphier-pro4-ace.dtb \ +- uniphier-pro4-ref.dtb \ +- uniphier-pro4-sanji.dtb \ +- uniphier-pxs2-gentil.dtb \ +- uniphier-pxs2-vodka.dtb \ +- uniphier-sld8-ref.dtb +-dtb-$(CONFIG_ARCH_VERSATILE) += \ +- versatile-ab.dtb \ +- versatile-ab-ib2.dtb \ +- versatile-pb.dtb +-dtb-$(CONFIG_ARCH_VEXPRESS) += \ +- vexpress-v2p-ca5s.dtb \ +- vexpress-v2p-ca9.dtb \ +- vexpress-v2p-ca15-tc1.dtb \ +- vexpress-v2p-ca15_a7.dtb +-dtb-$(CONFIG_ARCH_VIRT) += \ +- xenvm-4.2.dtb +-dtb-$(CONFIG_ARCH_VT8500) += \ +- vt8500-bv07.dtb \ +- wm8505-ref.dtb \ +- wm8650-mid.dtb \ +- wm8750-apc8750.dtb \ +- wm8850-w70v2.dtb +-dtb-$(CONFIG_ARCH_ZYNQ) += \ +- zynq-cc108.dtb \ +- zynq-ebaz4205.dtb \ +- zynq-microzed.dtb \ +- zynq-parallella.dtb \ +- zynq-zc702.dtb \ +- zynq-zc706.dtb \ +- zynq-zc770-xm010.dtb \ +- zynq-zc770-xm011.dtb \ +- zynq-zc770-xm012.dtb \ +- zynq-zc770-xm013.dtb \ +- zynq-zed.dtb \ +- zynq-zturn.dtb \ +- zynq-zturn-v5.dtb \ +- zynq-zybo.dtb \ +- zynq-zybo-z7.dtb +-dtb-$(CONFIG_MACH_ARMADA_370) += \ +- armada-370-db.dtb \ +- armada-370-dlink-dns327l.dtb \ +- armada-370-mirabox.dtb \ +- armada-370-netgear-rn102.dtb \ +- armada-370-netgear-rn104.dtb \ +- armada-370-rd.dtb \ +- armada-370-seagate-nas-2bay.dtb \ +- armada-370-seagate-nas-4bay.dtb \ +- armada-370-seagate-personal-cloud.dtb \ +- armada-370-seagate-personal-cloud-2bay.dtb \ +- armada-370-synology-ds213j.dtb +-dtb-$(CONFIG_MACH_ARMADA_375) += \ +- armada-375-db.dtb +-dtb-$(CONFIG_MACH_ARMADA_38X) += \ +- armada-382-rd-ac3x-48g4x2xl.dtb \ +- armada-385-atl-x530.dtb\ +- armada-385-clearfog-gtr-s4.dtb \ +- armada-385-clearfog-gtr-l8.dtb \ +- armada-385-db-88f6820-amc.dtb \ +- armada-385-db-ap.dtb \ +- armada-385-linksys-caiman.dtb \ +- armada-385-linksys-cobra.dtb \ +- armada-385-linksys-rango.dtb \ +- armada-385-linksys-shelby.dtb \ +- armada-385-synology-ds116.dtb \ +- armada-385-turris-omnia.dtb \ +- armada-388-clearfog.dtb \ +- armada-388-clearfog-base.dtb \ +- armada-388-clearfog-pro.dtb \ +- armada-388-db.dtb \ +- armada-388-gp.dtb \ +- armada-388-helios4.dtb \ +- armada-388-rd.dtb +-dtb-$(CONFIG_MACH_ARMADA_39X) += \ +- armada-398-db.dtb +-dtb-$(CONFIG_MACH_ARMADA_XP) += \ +- armada-xp-axpwifiap.dtb \ +- armada-xp-crs305-1g-4s.dtb \ +- armada-xp-crs305-1g-4s-bit.dtb \ +- armada-xp-crs326-24g-2s.dtb \ +- armada-xp-crs326-24g-2s-bit.dtb \ +- armada-xp-crs328-4c-20s-4s.dtb \ +- armada-xp-crs328-4c-20s-4s-bit.dtb \ +- armada-xp-db.dtb \ +- armada-xp-db-dxbc2.dtb \ +- armada-xp-db-xc3-24g4xg.dtb \ +- armada-xp-gp.dtb \ +- armada-xp-lenovo-ix4-300d.dtb \ +- armada-xp-linksys-mamba.dtb \ +- armada-xp-matrix.dtb \ +- armada-xp-netgear-rn2120.dtb \ +- armada-xp-openblocks-ax3-4.dtb \ +- armada-xp-synology-ds414.dtb +-dtb-$(CONFIG_MACH_DOVE) += \ +- dove-cubox.dtb \ +- dove-cubox-es.dtb \ +- dove-d2plug.dtb \ +- dove-d3plug.dtb \ +- dove-dove-db.dtb \ +- dove-sbc-a510.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += \ +- mt2701-evb.dtb \ +- mt6580-evbp1.dtb \ +- mt6589-aquaris5.dtb \ +- mt6592-evb.dtb \ +- mt7623a-rfb-emmc.dtb \ +- mt7623a-rfb-nand.dtb \ +- mt7623n-rfb-emmc.dtb \ +- mt7623n-bananapi-bpi-r2.dtb \ +- mt7629-rfb.dtb \ +- mt8127-moose.dtb \ +- mt8135-evbp1.dtb +-dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb +-dtb-$(CONFIG_ARCH_MSTARV7) += \ +- mstar-infinity-msc313-breadbee_crust.dtb \ +- mstar-infinity2m-ssd202d-ssd201htv2.dtb \ +- mstar-infinity2m-ssd202d-unitv2.dtb \ +- mstar-infinity3-msc313e-breadbee.dtb \ +- mstar-mercury5-ssc8336n-midrived08.dtb +-dtb-$(CONFIG_ARCH_ASPEED) += \ +- aspeed-ast2500-evb.dtb \ +- aspeed-ast2600-evb-a1.dtb \ +- aspeed-ast2600-evb.dtb \ +- aspeed-bmc-amd-ethanolx.dtb \ +- aspeed-bmc-ampere-mtjade.dtb \ +- aspeed-bmc-arm-centriq2400-rep.dtb \ +- aspeed-bmc-arm-stardragon4800-rep2.dtb \ +- aspeed-bmc-asrock-e3c246d4i.dtb \ +- aspeed-bmc-bytedance-g220a.dtb \ +- aspeed-bmc-facebook-cloudripper.dtb \ +- aspeed-bmc-facebook-cmm.dtb \ +- aspeed-bmc-facebook-elbert.dtb \ +- aspeed-bmc-facebook-fuji.dtb \ +- aspeed-bmc-facebook-galaxy100.dtb \ +- aspeed-bmc-facebook-minipack.dtb \ +- aspeed-bmc-facebook-tiogapass.dtb \ +- aspeed-bmc-facebook-wedge40.dtb \ +- aspeed-bmc-facebook-wedge100.dtb \ +- aspeed-bmc-facebook-wedge400.dtb \ +- aspeed-bmc-facebook-yamp.dtb \ +- aspeed-bmc-facebook-yosemitev2.dtb \ +- aspeed-bmc-ibm-everest.dtb \ +- aspeed-bmc-ibm-rainier.dtb \ +- aspeed-bmc-ibm-rainier-1s4u.dtb \ +- aspeed-bmc-ibm-rainier-4u.dtb \ +- aspeed-bmc-intel-s2600wf.dtb \ +- aspeed-bmc-inspur-fp5280g2.dtb \ +- aspeed-bmc-inspur-nf5280m6.dtb \ +- aspeed-bmc-lenovo-hr630.dtb \ +- aspeed-bmc-lenovo-hr855xg2.dtb \ +- aspeed-bmc-microsoft-olympus.dtb \ +- aspeed-bmc-opp-lanyang.dtb \ +- aspeed-bmc-opp-mihawk.dtb \ +- aspeed-bmc-opp-mowgli.dtb \ +- aspeed-bmc-opp-nicole.dtb \ +- aspeed-bmc-opp-palmetto.dtb \ +- aspeed-bmc-opp-romulus.dtb \ +- aspeed-bmc-opp-swift.dtb \ +- aspeed-bmc-opp-tacoma.dtb \ +- aspeed-bmc-opp-vesnin.dtb \ +- aspeed-bmc-opp-witherspoon.dtb \ +- aspeed-bmc-opp-zaius.dtb \ +- aspeed-bmc-portwell-neptune.dtb \ +- aspeed-bmc-quanta-q71l.dtb \ +- aspeed-bmc-supermicro-x11spi.dtb +diff --git a/scripts/dtc/include-prefixes/arm/aks-cdu.dts b/scripts/dtc/include-prefixes/arm/aks-cdu.dts +deleted file mode 100644 +index 742fcf525e1b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aks-cdu.dts ++++ /dev/null +@@ -1,122 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * aks-cdu.dts - Device Tree file for AK signal CDU +- * +- * Copyright (C) 2012 AK signal Brno a.s. +- * 2012 Jiri Prchal +- */ +- +-/dts-v1/; +- +-#include "ge863-pro3.dtsi" +- +-/ { +- chosen { +- bootargs = "console=ttyS0,115200 ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs"; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- }; +- +- ahb { +- apb { +- usart0: serial@fffb0000 { +- status = "okay"; +- }; +- +- usart1: serial@fffb4000 { +- status = "okay"; +- linux,rs485-enabled-at-boot-time; +- rs485-rts-delay = <0 0>; +- }; +- +- usart2: serial@fffb8000 { +- status = "okay"; +- linux,rs485-enabled-at-boot-time; +- rs485-rts-delay = <0 0>; +- }; +- +- usart3: serial@fffd0000 { +- status = "okay"; +- linux,rs485-enabled-at-boot-time; +- rs485-rts-delay = <0 0>; +- }; +- +- macb0: ethernet@fffc4000 { +- phy-mode = "rmii"; +- status = "okay"; +- }; +- +- usb1: gadget@fffa4000 { +- atmel,vbus-gpio = <&pioC 15 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- }; +- +- usb0: ohci@500000 { +- num-ports = <2>; +- status = "okay"; +- }; +- +- ebi: ebi@10000000 { +- nand_controller: nand-controller { +- nand: nand@3 { +- partitions { +- bootstrap@0 { +- label = "bootstrap"; +- reg = <0x0 0x40000>; +- }; +- +- uboot@40000 { +- label = "uboot"; +- reg = <0x40000 0x80000>; +- }; +- +- ubootenv@c0000 { +- label = "ubootenv"; +- reg = <0xc0000 0x40000>; +- }; +- +- kernel@100000 { +- label = "kernel"; +- reg = <0x100000 0x400000>; +- }; +- +- rootfs@500000 { +- label = "rootfs"; +- reg = <0x500000 0x7b00000>; +- }; +- }; +- }; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- red { +- gpios = <&pioC 10 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "none"; +- }; +- +- green { +- gpios = <&pioA 5 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "none"; +- default-state = "on"; +- }; +- +- yellow { +- gpios = <&pioB 20 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "none"; +- }; +- +- blue { +- gpios = <&pioB 21 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "none"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/alphascale-asm9260-devkit.dts b/scripts/dtc/include-prefixes/arm/alphascale-asm9260-devkit.dts +deleted file mode 100644 +index c77e2c902fb6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/alphascale-asm9260-devkit.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* +- * Copyright 2014 Oleksij Rempel +- * +- * Licensed under the X11 license or the GPL v2 (or later) +- */ +- +-/dts-v1/; +-#include "alphascale-asm9260.dtsi" +- +-/ { +- model = "Alphascale asm9260 Development Kit"; +- compatible = "alphascale,asm9260devkit", "alphascale,asm9260"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/alphascale-asm9260.dtsi b/scripts/dtc/include-prefixes/arm/alphascale-asm9260.dtsi +deleted file mode 100644 +index 2ce6038536fd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/alphascale-asm9260.dtsi ++++ /dev/null +@@ -1,64 +0,0 @@ +-/* +- * Copyright 2014 Oleksij Rempel +- * +- * Licensed under the X11 license or the GPL v2 (or later) +- */ +- +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&icoll>; +- +- memory { +- device_type = "memory"; +- reg = <0x20000000 0x2000000>; +- }; +- +- cpus { +- #address-cells = <0>; +- #size-cells = <0>; +- +- cpu { +- compatible = "arm,arm926ej-s"; +- device_type = "cpu"; +- clocks = <&acc CLKID_SYS_CPU>; +- }; +- }; +- +- osc24m: oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-accuracy = <30000>; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges; +- +- acc: clock-controller@80040000 { +- compatible = "alphascale,asm9260-clock-controller"; +- #clock-cells = <1>; +- clocks = <&osc24m>; +- reg = <0x80040000 0x204>; +- }; +- +- icoll: interrupt-controller@80054000 { +- compatible = "alphascale,asm9260-icoll"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x80054000 0x200>; +- }; +- +- timer0: timer@80088000 { +- compatible = "alphascale,asm9260-timer"; +- reg = <0x80088000 0x4000>; +- clocks = <&acc CLKID_AHB_TIMER0>; +- interrupts = <29>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/alpine-db.dts b/scripts/dtc/include-prefixes/arm/alpine-db.dts +deleted file mode 100644 +index dfb5a0802273..000000000000 +--- a/scripts/dtc/include-prefixes/arm/alpine-db.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-/* +- * Copyright 2015 Annapurna Labs Ltd. +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms and conditions of the GNU General Public License, +- * version 2, as published by the Free Software Foundation. +- * +- * Alternatively, redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright notice, +- * this list of conditions and the following disclaimer. +- * +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * +- * This program is distributed in the hope it will be useful, but WITHOUT +- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +- * more details. +- * +- */ +- +-/dts-v1/; +- +-#include "alpine.dtsi" +- +-/ { +- model = "Annapurna Labs Alpine Dev Board"; +- /* no need for anything outside SOC */ +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/alpine.dtsi b/scripts/dtc/include-prefixes/arm/alpine.dtsi +deleted file mode 100644 +index 3b0675a1c460..000000000000 +--- a/scripts/dtc/include-prefixes/arm/alpine.dtsi ++++ /dev/null +@@ -1,176 +0,0 @@ +-/* +- * Copyright 2015 Annapurna Labs Ltd. +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms and conditions of the GNU General Public License, +- * version 2, as published by the Free Software Foundation. +- * +- * Alternatively, redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright notice, +- * this list of conditions and the following disclaimer. +- * +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * +- * This program is distributed in the hope it will be useful, but WITHOUT +- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +- * more details. +- * +- */ +- +-#include +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- /* SOC compatibility */ +- compatible = "al,alpine"; +- +- memory { +- device_type = "memory"; +- reg = <0 0 0 0>; +- }; +- +- /* CPU Configuration */ +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "al,alpine-smp"; +- +- cpu@0 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- reg = <0>; +- clock-frequency = <1700000000>; +- }; +- +- cpu@1 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- reg = <1>; +- clock-frequency = <1700000000>; +- }; +- +- cpu@2 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- reg = <2>; +- clock-frequency = <1700000000>; +- }; +- +- cpu@3 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- reg = <3>; +- clock-frequency = <1700000000>; +- }; +- }; +- +- soc { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- ranges; +- +- arch-timer { +- compatible = "arm,cortex-a15-timer", +- "arm,armv7-timer"; +- interrupts = +- , +- , +- , +- ; +- clock-frequency = <50000000>; +- }; +- +- /* Interrupt Controller */ +- gic: interrupt-controller@fb001000 { +- compatible = "arm,cortex-a15-gic"; +- #interrupt-cells = <3>; +- #size-cells = <0>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x0 0xfb001000 0x0 0x1000>, +- <0x0 0xfb002000 0x0 0x2000>, +- <0x0 0xfb004000 0x0 0x2000>, +- <0x0 0xfb006000 0x0 0x2000>; +- interrupts = +- ; +- }; +- +- /* CPU Resume registers */ +- cpu-resume@fbff5ec0 { +- compatible = "al,alpine-cpu-resume"; +- reg = <0x0 0xfbff5ec0 0x0 0x30>; +- }; +- +- /* North Bridge Service Registers */ +- sysfabric-service@fb070000 { +- compatible = "al,alpine-sysfabric-service", "syscon"; +- reg = <0x0 0xfb070000 0x0 0x10000>; +- }; +- +- /* Performance Monitor Unit */ +- pmu { +- compatible = "arm,cortex-a15-pmu"; +- interrupts = , +- , +- , +- ; +- }; +- +- uart0: uart@fd883000 { +- compatible = "ns16550a"; +- reg = <0x0 0xfd883000 0x0 0x1000>; +- clock-frequency = <375000000>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- uart1: uart@fd884000 { +- compatible = "ns16550a"; +- reg = <0x0 0xfd884000 0x0 0x1000>; +- clock-frequency = <375000000>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- /* Internal PCIe Controller */ +- pcie@fbc00000 { +- compatible = "pci-host-ecam-generic"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- #interrupt-cells = <1>; +- reg = <0x0 0xfbc00000 0x0 0x100000>; +- interrupt-map-mask = <0xf800 0 0 7>; +- /* Add legacy interrupts for SATA devices only */ +- interrupt-map = <0x4000 0 0 1 &gic 0 43 4>, +- <0x4800 0 0 1 &gic 0 44 4>; +- +- /* 32 bit non prefetchable memory space */ +- ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>; +- +- bus-range = <0x00 0x00>; +- msi-parent = <&msix>; +- }; +- +- msix: msix@fbe00000 { +- compatible = "al,alpine-msix"; +- reg = <0x0 0xfbe00000 0x0 0x100000>; +- interrupt-controller; +- msi-controller; +- al,msi-base-spi = <96>; +- al,msi-num-spis = <64>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-baltos-ir2110.dts b/scripts/dtc/include-prefixes/arm/am335x-baltos-ir2110.dts +deleted file mode 100644 +index daf4cb398070..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-baltos-ir2110.dts ++++ /dev/null +@@ -1,83 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/* +- * VScom OnRISC +- * http://www.vscom.de +- */ +- +-/dts-v1/; +- +-#include "am335x-baltos.dtsi" +-#include "am335x-baltos-leds.dtsi" +- +-/ { +- model = "OnRISC Baltos iR 2110"; +-}; +- +-&am33xx_pinmux { +- uart1_pins: pinmux_uart1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ +- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ +- >; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; +- dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; +- dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; +- rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; +- +- status = "okay"; +-}; +- +-&usb0_phy { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&davinci_mdio_sw { +- phy0: ethernet-phy@0 { +- reg = <1>; +- }; +-}; +- +-&cpsw_port1 { +- phy-mode = "rmii"; +- ti,dual-emac-pvid = <1>; +- phy-handle = <&phy0>; +-}; +- +-&cpsw_port2 { +- phy-mode = "rgmii-id"; +- ti,dual-emac-pvid = <2>; +- phy-handle = <&phy1>; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-baltos-ir3220.dts b/scripts/dtc/include-prefixes/arm/am335x-baltos-ir3220.dts +deleted file mode 100644 +index 2123bd589484..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-baltos-ir3220.dts ++++ /dev/null +@@ -1,125 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/* +- * VScom OnRISC +- * http://www.vscom.de +- */ +- +-/dts-v1/; +- +-#include "am335x-baltos.dtsi" +-#include "am335x-baltos-leds.dtsi" +- +-/ { +- model = "OnRISC Baltos iR 3220"; +-}; +- +-&am33xx_pinmux { +- tca6416_pins: pinmux_tca6416_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ +- >; +- }; +- +- uart1_pins: pinmux_uart1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ +- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ +- >; +- }; +- +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ +- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */ +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */ +- +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ +- >; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; +- dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; +- dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; +- rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; +- +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; +- dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; +- dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +- +- status = "okay"; +-}; +- +-&i2c1 { +- tca6416: gpio@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gpio0>; +- interrupts = <20 IRQ_TYPE_EDGE_RISING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tca6416_pins>; +- }; +-}; +- +-&usb0_phy { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&cpsw_port1 { +- phy-mode = "rmii"; +- ti,dual-emac-pvid = <1>; +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +-}; +- +-&cpsw_port2 { +- phy-mode = "rgmii-id"; +- ti,dual-emac-pvid = <2>; +- phy-handle = <&phy1>; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-baltos-ir5221.dts b/scripts/dtc/include-prefixes/arm/am335x-baltos-ir5221.dts +deleted file mode 100644 +index 2f3872dbf4f4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-baltos-ir5221.dts ++++ /dev/null +@@ -1,149 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/* +- * VScom OnRISC +- * http://www.vscom.de +- */ +- +-/dts-v1/; +- +-#include "am335x-baltos.dtsi" +-#include "am335x-baltos-leds.dtsi" +- +-/ { +- model = "OnRISC Baltos iR 5221"; +-}; +- +-&am33xx_pinmux { +- tca6416_pins: pinmux_tca6416_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ +- >; +- }; +- +- +- dcan1_pins: pinmux_dcan1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.dcan1_tx_mux0 */ +- AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* uart0_rtsn.dcan1_rx_mux0 */ +- >; +- }; +- +- uart1_pins: pinmux_uart1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ +- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ +- >; +- }; +- +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ +- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */ +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */ +- +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ +- >; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; +- dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; +- dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; +- rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; +- +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; +- dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; +- dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +- +- status = "okay"; +-}; +- +-&i2c1 { +- tca6416: gpio@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gpio0>; +- interrupts = <20 IRQ_TYPE_EDGE_RISING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tca6416_pins>; +- }; +-}; +- +-&usb0_phy { +- status = "okay"; +-}; +- +-&usb1_phy { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&usb1 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&cpsw_port1 { +- phy-mode = "rmii"; +- ti,dual-emac-pvid = <1>; +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +-}; +- +-&cpsw_port2 { +- phy-mode = "rgmii-id"; +- ti,dual-emac-pvid = <2>; +- phy-handle = <&phy1>; +-}; +- +-&dcan1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&dcan1_pins>; +- +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-baltos-leds.dtsi b/scripts/dtc/include-prefixes/arm/am335x-baltos-leds.dtsi +deleted file mode 100644 +index 9a79f727baf6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-baltos-leds.dtsi ++++ /dev/null +@@ -1,47 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/* +- * VScom OnRISC +- * http://www.vscom.de +- */ +- +-/*#include "am33xx.dtsi"*/ +- +-/ { +- leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&user_leds>; +- +- compatible = "gpio-leds"; +- +- power { +- label = "onrisc:red:power"; +- linux,default-trigger = "default-on"; +- gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- wlan { +- label = "onrisc:blue:wlan"; +- gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- app { +- label = "onrisc:green:app"; +- gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +-}; +- +-&am33xx_pinmux { +- user_leds: pinmux_user_leds { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 PWR LED */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mii1_txd3.gpio0_16 WLAN LED */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mii1_txd2.gpio0_17 APP LED */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-baltos.dtsi b/scripts/dtc/include-prefixes/arm/am335x-baltos.dtsi +deleted file mode 100644 +index 366702630290..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-baltos.dtsi ++++ /dev/null +@@ -1,401 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/* +- * VScom OnRISC +- * http://www.vscom.de +- */ +- +-#include "am33xx.dtsi" +-#include +-#include +- +-/ { +- compatible = "vscom,onrisc", "ti,am33xx"; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&vdd1_reg>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +- +- vbat: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vbat"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- }; +- +- wl12xx_vmmc: fixedregulator2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&wl12xx_gpio>; +- compatible = "regulator-fixed"; +- regulator-name = "vwl1271"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 8 0>; +- startup-delay-us = <70000>; +- enable-active-high; +- }; +-}; +- +-&am33xx_pinmux { +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */ +- AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLUP, MUX_MODE7) /* emu0.gpio3[7] */ +- >; +- }; +- +- wl12xx_gpio: pinmux_wl12xx_gpio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */ +- >; +- }; +- +- tps65910_pins: pinmux_tps65910_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ben1.gpio1[28] */ +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */ +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */ +- >; +- }; +- +- uart0_pins: pinmux_uart0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- cpsw_default: cpsw_default { +- pinctrl-single,pins = < +- /* Slave 1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_tx_en.rmii1_txen */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ +- +- +- /* Slave 2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ +- >; +- }; +- +- cpsw_sleep: cpsw_sleep { +- pinctrl-single,pins = < +- /* Slave 1 reset value */ +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- +- /* Slave 2 reset value*/ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- davinci_mdio_default: davinci_mdio_default { +- pinctrl-single,pins = < +- /* MDIO */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data.mdio_data */ +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* mdio_clk.mdio_clk */ +- >; +- }; +- +- davinci_mdio_sleep: davinci_mdio_sleep { +- pinctrl-single,pins = < +- /* MDIO reset value */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- nandflash_pins_s0: nandflash_pins_s0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) /* gpmc_wen.gpmc_wen */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ +- >; +- }; +-}; +- +-&elm { +- status = "okay"; +-}; +- +-&gpmc { +- pinctrl-names = "default"; +- pinctrl-0 = <&nandflash_pins_s0>; +- ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ +- status = "okay"; +- +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ +- nand-bus-width = <8>; +- ti,nand-ecc-opt = "bch8"; +- ti,nand-xfer-type = "polled"; +- +- gpmc,device-nand = "true"; +- gpmc,device-width = <1>; +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-on-ns = <0>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ti,elm-id = <&elm>; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- tps: tps@2d { +- reg = <0x2d>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gpio1>; +- interrupts = <28 IRQ_TYPE_EDGE_RISING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tps65910_pins>; +- }; +- +- at24@50 { +- compatible = "atmel,24c02"; +- pagesize = <8>; +- reg = <0x50>; +- }; +-}; +- +-#include "tps65910.dtsi" +- +-&tps { +- vcc1-supply = <&vbat>; +- vcc2-supply = <&vbat>; +- vcc3-supply = <&vbat>; +- vcc4-supply = <&vbat>; +- vcc5-supply = <&vbat>; +- vcc6-supply = <&vbat>; +- vcc7-supply = <&vbat>; +- vccio-supply = <&vbat>; +- +- ti,en-ck32k-xtal = <1>; +- +- regulators { +- vrtc_reg: regulator@0 { +- regulator-always-on; +- }; +- +- vio_reg: regulator@1 { +- regulator-always-on; +- }; +- +- vdd1_reg: regulator@2 { +- /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <912500>; +- regulator-max-microvolt = <1312500>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd2_reg: regulator@3 { +- /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <912500>; +- regulator-max-microvolt = <1150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd3_reg: regulator@4 { +- regulator-always-on; +- }; +- +- vdig1_reg: regulator@5 { +- regulator-always-on; +- }; +- +- vdig2_reg: regulator@6 { +- regulator-always-on; +- }; +- +- vpll_reg: regulator@7 { +- regulator-always-on; +- }; +- +- vdac_reg: regulator@8 { +- regulator-always-on; +- }; +- +- vaux1_reg: regulator@9 { +- regulator-always-on; +- }; +- +- vaux2_reg: regulator@10 { +- regulator-always-on; +- }; +- +- vaux33_reg: regulator@11 { +- regulator-always-on; +- }; +- +- vmmc_reg: regulator@12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +-}; +- +-&mac_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&cpsw_default>; +- pinctrl-1 = <&cpsw_sleep>; +- +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&davinci_mdio_default>; +- pinctrl-1 = <&davinci_mdio_sleep>; +- +- phy1: ethernet-phy@1 { +- reg = <7>; +- eee-broken-100tx; +- eee-broken-1000t; +- }; +-}; +- +-&mmc1 { +- vmmc-supply = <&vmmc_reg>; +- status = "okay"; +-}; +- +-&mmc2 { +- status = "okay"; +- vmmc-supply = <&wl12xx_vmmc>; +- non-removable; +- bus-width = <4>; +- cap-power-off-card; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1835"; +- reg = <2>; +- interrupt-parent = <&gpio3>; +- interrupts = <7 IRQ_TYPE_EDGE_RISING>; +- }; +-}; +- +-&sham { +- status = "okay"; +-}; +- +-&aes { +- status = "okay"; +-}; +- +-&gpio0_target { +- ti,no-reset-on-init; +-}; +- +-&gpio3_target { +- ti,no-reset-on-init; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-base0033.dts b/scripts/dtc/include-prefixes/arm/am335x-base0033.dts +deleted file mode 100644 +index 89c00ce42c26..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-base0033.dts ++++ /dev/null +@@ -1,92 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION +- * +- * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz +- */ +- +-#include "am335x-igep0033.dtsi" +- +-/ { +- model = "IGEP COM AM335x on AQUILA Expansion"; +- compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx"; +- +- hdmi { +- compatible = "ti,tilcdc,slave"; +- i2c = <&i2c0>; +- pinctrl-names = "default", "off"; +- pinctrl-0 = <&nxp_hdmi_pins>; +- pinctrl-1 = <&nxp_hdmi_off_pins>; +- status = "okay"; +- }; +- +- leds_base { +- pinctrl-names = "default"; +- pinctrl-0 = <&leds_base_pins>; +- +- compatible = "gpio-leds"; +- +- led0 { +- label = "base:red:user"; +- gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */ +- default-state = "off"; +- }; +- +- led1 { +- label = "base:green:user"; +- gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */ +- default-state = "off"; +- }; +- }; +-}; +- +-&am33xx_pinmux { +- nxp_hdmi_pins: pinmux_nxp_hdmi_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) +- >; +- }; +- nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ +- >; +- }; +- +- leds_base_pins: pinmux_leds_base_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn3.gpio2_0 */ +- >; +- }; +-}; +- +-&lcdc { +- status = "okay"; +-}; +- +-&i2c0 { +- eeprom: eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-bone-common.dtsi b/scripts/dtc/include-prefixes/arm/am335x-bone-common.dtsi +deleted file mode 100644 +index 0ccdc7cd463b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-bone-common.dtsi ++++ /dev/null +@@ -1,406 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/ { +- cpus { +- cpu@0 { +- cpu0-supply = <&dcdc2_reg>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&user_leds_s0>; +- +- compatible = "gpio-leds"; +- +- led2 { +- label = "beaglebone:green:heartbeat"; +- gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- +- led3 { +- label = "beaglebone:green:mmc0"; +- gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- +- led4 { +- label = "beaglebone:green:usr2"; +- gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "cpu0"; +- default-state = "off"; +- }; +- +- led5 { +- label = "beaglebone:green:usr3"; +- gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc1"; +- default-state = "off"; +- }; +- }; +- +- vmmcsd_fixed: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsd_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&am33xx_pinmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&clkout2_pin>; +- +- user_leds_s0: user_leds_s0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ +- >; +- }; +- +- i2c0_pins: pinmux_i2c0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ +- >; +- }; +- +- i2c2_pins: pinmux_i2c2_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ +- >; +- }; +- +- uart0_pins: pinmux_uart0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- clkout2_pin: pinmux_clkout2_pin { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ +- >; +- }; +- +- cpsw_default: cpsw_default { +- pinctrl-single,pins = < +- /* Slave 1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- cpsw_sleep: cpsw_sleep { +- pinctrl-single,pins = < +- /* Slave 1 reset value */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- davinci_mdio_default: davinci_mdio_default { +- pinctrl-single,pins = < +- /* MDIO */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- davinci_mdio_sleep: davinci_mdio_sleep { +- pinctrl-single,pins = < +- /* MDIO reset value */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spio0_cs1.gpio0_6 */ +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- emmc_pins: pinmux_emmc_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ +- >; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- +- status = "okay"; +-}; +- +-&usb0 { +- dr_mode = "peripheral"; +- interrupts-extended = <&intc 18 &tps 0>; +- interrupt-names = "mc", "vbus"; +-}; +- +-&usb1 { +- dr_mode = "host"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- tps: tps@24 { +- reg = <0x24>; +- }; +- +- baseboard_eeprom: baseboard_eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- baseboard_data: baseboard_data@0 { +- reg = <0 0x100>; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- +- status = "okay"; +- clock-frequency = <100000>; +- +- cape_eeprom0: cape_eeprom0@54 { +- compatible = "atmel,24c256"; +- reg = <0x54>; +- #address-cells = <1>; +- #size-cells = <1>; +- cape0_data: cape_data@0 { +- reg = <0 0x100>; +- }; +- }; +- +- cape_eeprom1: cape_eeprom1@55 { +- compatible = "atmel,24c256"; +- reg = <0x55>; +- #address-cells = <1>; +- #size-cells = <1>; +- cape1_data: cape_data@0 { +- reg = <0 0x100>; +- }; +- }; +- +- cape_eeprom2: cape_eeprom2@56 { +- compatible = "atmel,24c256"; +- reg = <0x56>; +- #address-cells = <1>; +- #size-cells = <1>; +- cape2_data: cape_data@0 { +- reg = <0 0x100>; +- }; +- }; +- +- cape_eeprom3: cape_eeprom3@57 { +- compatible = "atmel,24c256"; +- reg = <0x57>; +- #address-cells = <1>; +- #size-cells = <1>; +- cape3_data: cape_data@0 { +- reg = <0 0x100>; +- }; +- }; +-}; +- +- +-/include/ "tps65217.dtsi" +- +-&tps { +- /* +- * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only +- * mode") at poweroff. Most BeagleBone versions do not support RTC-only +- * mode and risk hardware damage if this mode is entered. +- * +- * For details, see linux-omap mailing list May 2015 thread +- * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller +- * In particular, messages: +- * http://www.spinics.net/lists/linux-omap/msg118585.html +- * http://www.spinics.net/lists/linux-omap/msg118615.html +- * +- * You can override this later with +- * &tps { /delete-property/ ti,pmic-shutdown-controller; } +- * if you want to use RTC-only mode and made sure you are not affected +- * by the hardware problems. (Tip: double-check by performing a current +- * measurement after shutdown: it should be less than 1 mA.) +- */ +- +- interrupts = <7>; /* NMI */ +- interrupt-parent = <&intc>; +- +- ti,pmic-shutdown-controller; +- +- charger { +- status = "okay"; +- }; +- +- pwrbutton { +- status = "okay"; +- }; +- +- regulators { +- dcdc1_reg: regulator@0 { +- regulator-name = "vdds_dpr"; +- regulator-always-on; +- }; +- +- dcdc2_reg: regulator@1 { +- /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <1351500>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc3_reg: regulator@2 { +- /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <1150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1_reg: regulator@3 { +- regulator-name = "vio,vrtc,vdds"; +- regulator-always-on; +- }; +- +- ldo2_reg: regulator@4 { +- regulator-name = "vdd_3v3aux"; +- regulator-always-on; +- }; +- +- ldo3_reg: regulator@5 { +- regulator-name = "vdd_1v8"; +- regulator-always-on; +- }; +- +- ldo4_reg: regulator@6 { +- regulator-name = "vdd_3v3a"; +- regulator-always-on; +- }; +- }; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "mii"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- status = "disabled"; +-}; +- +-&mac_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&cpsw_default>; +- pinctrl-1 = <&cpsw_sleep>; +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&davinci_mdio_default>; +- pinctrl-1 = <&davinci_mdio_sleep>; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&mmc1 { +- status = "okay"; +- bus-width = <0x4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +-}; +- +-&aes { +- status = "okay"; +-}; +- +-&sham { +- status = "okay"; +-}; +- +-&rtc { +- clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; +- clock-names = "ext-clk", "int-clk"; +-}; +- +-&pruss_tm { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-bone.dts b/scripts/dtc/include-prefixes/arm/am335x-bone.dts +deleted file mode 100644 +index b5d85ef51a02..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-bone.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "am33xx.dtsi" +-#include "am335x-bone-common.dtsi" +- +-/ { +- model = "TI AM335x BeagleBone"; +- compatible = "ti,am335x-bone", "ti,am33xx"; +-}; +- +-&ldo3_reg { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +-}; +- +-&mmc1 { +- vmmc-supply = <&ldo3_reg>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-boneblack-common.dtsi b/scripts/dtc/include-prefixes/arm/am335x-boneblack-common.dtsi +deleted file mode 100644 +index 10494c4431b9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-boneblack-common.dtsi ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-&ldo3_reg { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +-}; +- +-&mmc1 { +- vmmc-supply = <&vmmcsd_fixed>; +-}; +- +-&mmc2 { +- vmmc-supply = <&vmmcsd_fixed>; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_pins>; +- bus-width = <8>; +- status = "okay"; +- non-removable; +-}; +- +-&rtc { +- system-power-controller; +-}; +- +-/ { +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512 MB */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-boneblack-hdmi.dtsi b/scripts/dtc/include-prefixes/arm/am335x-boneblack-hdmi.dtsi +deleted file mode 100644 +index 7cfddada9348..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-boneblack-hdmi.dtsi ++++ /dev/null +@@ -1,141 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include +-#include +- +-&am33xx_pinmux { +- nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) +- >; +- }; +- +- mcasp0_pins: mcasp0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ +- AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ +- >; +- }; +-}; +- +-&lcdc { +- status = "okay"; +- +- /* If you want to get 24 bit RGB and 16 BGR mode instead of +- * current 16 bit RGB and 24 BGR modes, set the propety +- * below to "crossed" and uncomment the video-ports -property +- * in tda19988 node. +- */ +- blue-and-red-wiring = "straight"; +- +- port { +- lcdc_0: endpoint@0 { +- remote-endpoint = <&hdmi_0>; +- }; +- }; +-}; +- +-&i2c0 { +- tda19988: tda19988@70 { +- compatible = "nxp,tda998x"; +- reg = <0x70>; +- nxp,calib-gpios = <&gpio1 25 0>; +- interrupts-extended = <&gpio1 25 IRQ_TYPE_LEVEL_LOW>; +- +- pinctrl-names = "default", "off"; +- pinctrl-0 = <&nxp_hdmi_bonelt_pins>; +- pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; +- +- /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ +- /* video-ports = <0x234501>; */ +- +- #sound-dai-cells = <0>; +- audio-ports = < TDA998x_I2S 0x03>; +- +- ports { +- port@0 { +- hdmi_0: endpoint@0 { +- remote-endpoint = <&lcdc_0>; +- }; +- }; +- }; +- }; +-}; +- +-&mcasp0 { +- #sound-dai-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mcasp0_pins>; +- status = "okay"; +- op-mode = <0>; /* MCASP_IIS_MODE */ +- tdm-slots = <2>; +- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ +- 0 0 1 0 +- >; +- tx-num-evt = <32>; +- rx-num-evt = <32>; +-}; +- +-/ { +- clk_mcasp0_fixed: clk_mcasp0_fixed { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24576000>; +- }; +- +- clk_mcasp0: clk_mcasp0 { +- #clock-cells = <0>; +- compatible = "gpio-gate-clock"; +- clocks = <&clk_mcasp0_fixed>; +- enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "TI BeagleBone Black"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&dailink0_master>; +- simple-audio-card,frame-master = <&dailink0_master>; +- +- dailink0_master: simple-audio-card,cpu { +- sound-dai = <&mcasp0>; +- clocks = <&clk_mcasp0>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&tda19988>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-boneblack-wireless.dts b/scripts/dtc/include-prefixes/arm/am335x-boneblack-wireless.dts +deleted file mode 100644 +index c72b09ab8da0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-boneblack-wireless.dts ++++ /dev/null +@@ -1,111 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "am33xx.dtsi" +-#include "am335x-bone-common.dtsi" +-#include "am335x-boneblack-common.dtsi" +-#include "am335x-boneblack-hdmi.dtsi" +-#include +- +-/ { +- model = "TI AM335x BeagleBone Black Wireless"; +- compatible = "ti,am335x-bone-black-wireless", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +- +- wlan_en_reg: fixedregulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "wlan-en-regulator"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- startup-delay-us= <70000>; +- +- /* WL_EN */ +- gpio = <&gpio3 9 0>; +- enable-active-high; +- }; +-}; +- +-&am33xx_pinmux { +- bt_pins: pinmux_bt_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gmii1_txd0.gpio0_28 - BT_EN */ +- >; +- }; +- +- mmc3_pins: pinmux_mmc3_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (L15) gmii1_rxd1.mmc2_clk */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (J16) gmii1_txen.mmc2_cmd */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J17) gmii1_rxdv.mmc2_dat0 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J18) gmii1_txd3.mmc2_dat1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (K15) gmii1_txd2.mmc2_dat2 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (H16) gmii1_col.mmc2_dat3 */ +- >; +- }; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* gmii1_rxd2.uart3_txd */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* mdio_data.uart3_ctsn */ +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* mdio_clk.uart3_rtsn */ +- >; +- }; +- +- wl18xx_pins: pinmux_wl18xx_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gmii1_txclk.gpio3_9 WL_EN */ +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk.gpio0_29 WL_IRQ */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gmii1_rxclk.gpio3_10 LS_BUF_EN */ +- >; +- }; +-}; +- +-&mac_sw { +- status = "disabled"; +-}; +- +-&mmc3 { +- dmas = <&edma_xbar 12 0 1 +- &edma_xbar 13 0 2>; +- dma-names = "tx", "rx"; +- status = "okay"; +- vmmc-supply = <&wlan_en_reg>; +- bus-width = <4>; +- non-removable; +- cap-power-off-card; +- keep-power-in-suspend; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc3_pins &wl18xx_pins>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1835"; +- reg = <2>; +- interrupt-parent = <&gpio0>; +- interrupts = <29 IRQ_TYPE_EDGE_RISING>; +- }; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins &bt_pins>; +- status = "okay"; +- +- bluetooth { +- compatible = "ti,wl1835-st"; +- enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&gpio3 { +- ls-buf-en-hog { +- gpio-hog; +- gpios = <10 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "LS_BUF_EN"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-boneblack.dts b/scripts/dtc/include-prefixes/arm/am335x-boneblack.dts +deleted file mode 100644 +index 9312197316f0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-boneblack.dts ++++ /dev/null +@@ -1,170 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "am33xx.dtsi" +-#include "am335x-bone-common.dtsi" +-#include "am335x-boneblack-common.dtsi" +-#include "am335x-boneblack-hdmi.dtsi" +- +-/ { +- model = "TI AM335x BeagleBone Black"; +- compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +-}; +- +-&cpu0_opp_table { +- /* +- * All PG 2.0 silicon may not support 1GHz but some of the early +- * BeagleBone Blacks have PG 2.0 silicon which is guaranteed +- * to support 1GHz OPP so enable it for PG 2.0 on this board. +- */ +- oppnitro-1000000000 { +- opp-supported-hw = <0x06 0x0100>; +- }; +-}; +- +-&gpio0 { +- gpio-line-names = +- "[mdio_data]", +- "[mdio_clk]", +- "P9_22 [spi0_sclk]", +- "P9_21 [spi0_d0]", +- "P9_18 [spi0_d1]", +- "P9_17 [spi0_cs0]", +- "[mmc0_cd]", +- "P8_42A [ecappwm0]", +- "P8_35 [lcd d12]", +- "P8_33 [lcd d13]", +- "P8_31 [lcd d14]", +- "P8_32 [lcd d15]", +- "P9_20 [i2c2_sda]", +- "P9_19 [i2c2_scl]", +- "P9_26 [uart1_rxd]", +- "P9_24 [uart1_txd]", +- "[rmii1_txd3]", +- "[rmii1_txd2]", +- "[usb0_drvvbus]", +- "[hdmi cec]", +- "P9_41B", +- "[rmii1_txd1]", +- "P8_19 [ehrpwm2a]", +- "P8_13 [ehrpwm2b]", +- "NC", +- "NC", +- "P8_14", +- "P8_17", +- "[rmii1_txd0]", +- "[rmii1_refclk]", +- "P9_11 [uart4_rxd]", +- "P9_13 [uart4_txd]"; +-}; +- +-&gpio1 { +- gpio-line-names = +- "P8_25 [mmc1_dat0]", +- "[mmc1_dat1]", +- "P8_5 [mmc1_dat2]", +- "P8_6 [mmc1_dat3]", +- "P8_23 [mmc1_dat4]", +- "P8_22 [mmc1_dat5]", +- "P8_3 [mmc1_dat6]", +- "P8_4 [mmc1_dat7]", +- "NC", +- "NC", +- "NC", +- "NC", +- "P8_12", +- "P8_11", +- "P8_16", +- "P8_15", +- "P9_15A", +- "P9_23", +- "P9_14 [ehrpwm1a]", +- "P9_16 [ehrpwm1b]", +- "[emmc rst]", +- "[usr0 led]", +- "[usr1 led]", +- "[usr2 led]", +- "[usr3 led]", +- "[hdmi irq]", +- "[usb vbus oc]", +- "[hdmi audio]", +- "P9_12", +- "P8_26", +- "P8_21 [emmc]", +- "P8_20 [emmc]"; +-}; +- +-&gpio2 { +- gpio-line-names = +- "P9_15B", +- "P8_18", +- "P8_7", +- "P8_8", +- "P8_10", +- "P8_9", +- "P8_45 [hdmi]", +- "P8_46 [hdmi]", +- "P8_43 [hdmi]", +- "P8_44 [hdmi]", +- "P8_41 [hdmi]", +- "P8_42 [hdmi]", +- "P8_39 [hdmi]", +- "P8_40 [hdmi]", +- "P8_37 [hdmi]", +- "P8_38 [hdmi]", +- "P8_36 [hdmi]", +- "P8_34 [hdmi]", +- "[rmii1_rxd3]", +- "[rmii1_rxd2]", +- "[rmii1_rxd1]", +- "[rmii1_rxd0]", +- "P8_27 [hdmi]", +- "P8_29 [hdmi]", +- "P8_28 [hdmi]", +- "P8_30 [hdmi]", +- "[mmc0_dat3]", +- "[mmc0_dat2]", +- "[mmc0_dat1]", +- "[mmc0_dat0]", +- "[mmc0_clk]", +- "[mmc0_cmd]"; +-}; +- +-&gpio3 { +- gpio-line-names = +- "[mii col]", +- "[mii crs]", +- "[mii rx err]", +- "[mii tx en]", +- "[mii rx dv]", +- "[i2c0 sda]", +- "[i2c0 scl]", +- "[jtag emu0]", +- "[jtag emu1]", +- "[mii tx clk]", +- "[mii rx clk]", +- "NC", +- "NC", +- "[usb vbus en]", +- "P9_31 [spi1_sclk]", +- "P9_29 [spi1_d0]", +- "P9_30 [spi1_d1]", +- "P9_28 [spi1_cs0]", +- "P9_42B [ecappwm0]", +- "P9_27", +- "P9_41A", +- "P9_25", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-boneblue.dts b/scripts/dtc/include-prefixes/arm/am335x-boneblue.dts +deleted file mode 100644 +index c6bb325ead33..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-boneblue.dts ++++ /dev/null +@@ -1,616 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "am33xx.dtsi" +-#include "am335x-osd335x-common.dtsi" +-#include +- +-/ { +- model = "TI AM335x BeagleBone Blue"; +- compatible = "ti,am335x-bone-blue", "ti,am33xx"; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&user_leds_s0>; +- +- compatible = "gpio-leds"; +- +- usr_0_led { +- label = "beaglebone:green:usr0"; +- gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- +- usr_1_led { +- label = "beaglebone:green:usr1"; +- gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- +- usr_2_led { +- label = "beaglebone:green:usr2"; +- gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "cpu0"; +- default-state = "off"; +- }; +- +- usr_3_led { +- label = "beaglebone:green:usr3"; +- gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc1"; +- default-state = "off"; +- }; +- +- wifi_led { +- label = "wifi"; +- gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "phy0assoc"; +- }; +- +- red_led { +- label = "red"; +- gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- green_led { +- label = "green"; +- gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- batt_1_led { +- label = "bat25"; +- gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- batt_2_led { +- label = "bat50"; +- gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- batt_3_led { +- label = "bat75"; +- gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- batt_4_led { +- label = "bat100"; +- gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- vmmcsd_fixed: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsd_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- wlan_en_reg: fixedregulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "wlan-en-regulator"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- startup-delay-us= <70000>; +- +- /* WL_EN */ +- gpio = <&gpio3 9 0>; +- enable-active-high; +- }; +-}; +- +-&am33xx_pinmux { +- user_leds_s0: user_leds_s0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] - WIFI_LED */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7) /* (R7) gpmc_advn_ale.gpio2[2] - P8.7, LED_RED, GP1_PIN_5 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE7) /* (T7) gpmc_oen_ren.gpio2[3] - P8.8, LED_GREEN, GP1_PIN_6 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* (U12) gpmc_ad11.gpio0[27] - P8.17, BATT_LED_1 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7) /* (T5) lcd_data15.gpio0[11] - P8.32, BATT_LED_2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE7) /* (V6) gpmc_csn0.gpio1[29] - P8.26, BATT_LED_3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* (T11) gpmc_ad10.gpio0[26] - P8.14, BATT_LED_4 */ +- +- >; +- }; +- +- i2c2_pins: pinmux_i2c2_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ +- >; +- }; +- +- /* UT0 */ +- uart0_pins: pinmux_uart0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- /* UT1 */ +- uart1_pins: pinmux_uart1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- /* GPS */ +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE1) /* (A17) spi0_sclk.uart2_rxd */ +- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (B17) spi0_d0.uart2_txd */ +- >; +- }; +- +- /* DSM2 */ +- uart4_pins: pinmux_uart4_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ +- >; +- }; +- +- /* UT5 */ +- uart5_pins: pinmux_uart5_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* (U2) lcd_data9.uart5_rxd */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* (U1) lcd_data8.uart5_txd */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ +- >; +- }; +- +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* (U9) gpmc_csn1.mmc1_clk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* (V9) gpmc_csn2.mmc1_cmd */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* (U7) gpmc_ad0.mmc1_dat0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* (V7) gpmc_ad1.mmc1_dat1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* (R8) gpmc_ad2.mmc1_dat2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (T8) gpmc_ad3.mmc1_dat3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* (U8) gpmc_ad4.mmc1_dat4 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* (V8) gpmc_ad5.mmc1_dat5 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* (R9) gpmc_ad6.mmc1_dat6 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* (T9) gpmc_ad7.mmc1_dat7 */ +- >; +- }; +- +- mmc3_pins: pinmux_mmc3_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6) /* (L15) gmii1_rxd1.mmc2_clk */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6) /* (J16) gmii1_txen.mmc2_cmd */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5) /* (J17) gmii1_rxdv.mmc2_dat0 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5) /* (J18) gmii1_txd3.mmc2_dat1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5) /* (K15) gmii1_txd2.mmc2_dat2 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5) /* (H16) gmii1_col.mmc2_dat3 */ +- >; +- }; +- +- bt_pins: pinmux_bt_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* (K17) gmii1_txd0.gpio0[28] - BT_EN */ +- >; +- }; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* (M17) mdio_data.uart3_ctsn */ +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* (M18) mdio_clk.uart3_rtsn */ +- >; +- }; +- +- wl18xx_pins: pinmux_wl18xx_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] - WL_EN */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* (K16) gmii1_txd1.gpio0[21] - WL_IRQ */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* (L18) gmii1_rxclk.gpio3[10] - LS_BUF_EN */ +- >; +- }; +- +- /* DCAN */ +- dcan1_pins: pinmux_dcan1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* (E17) uart0_rtsn.dcan1_rx */ +- AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* (E18) uart0_ctsn.dcan1_tx */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_OUTPUT, MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ +- >; +- }; +- +- /* E1 */ +- eqep0_pins: pinmux_eqep0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT, MUX_MODE1) /* (B12) mcasp0_aclkr.eQEP0A_in */ +- AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_INPUT, MUX_MODE1) /* (C13) mcasp0_fsr.eQEP0B_in */ +- >; +- }; +- +- /* E2 */ +- eqep1_pins: pinmux_eqep1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT, MUX_MODE2) /* (V2) lcd_data12.eQEP1A_in */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_INPUT, MUX_MODE2) /* (V3) lcd_data13.eQEP1B_in */ +- >; +- }; +- +- /* E3 */ +- eqep2_pins: pinmux_eqep2_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE4) /* (T12) gpmc_ad12.eQEP2A_in */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE4) /* (R12) gpmc_ad13.eQEP2B_in */ +- >; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pins>; +- +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart5_pins>; +- +- status = "okay"; +-}; +- +-&usb0 { +- dr_mode = "peripheral"; +- interrupts-extended = <&intc 18 &tps 0>; +- interrupt-names = "mc", "vbus"; +-}; +- +-&usb1 { +- dr_mode = "host"; +-}; +- +-&i2c0 { +- baseboard_eeprom: baseboard_eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- baseboard_data: baseboard_data@0 { +- reg = <0 0x100>; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- mpu9250@68 { +- compatible = "invensense,mpu9250"; +- reg = <0x68>; +- interrupt-parent = <&gpio3>; +- interrupts = <21 IRQ_TYPE_EDGE_RISING>; +- i2c-gate { +- #address-cells = <1>; +- #size-cells = <0>; +- ax8975@c { +- compatible = "ak,ak8975"; +- reg = <0x0c>; +- }; +- }; +- }; +- +- pressure@76 { +- compatible = "bosch,bmp280"; +- reg = <0x76>; +- }; +-}; +- +-/include/ "tps65217.dtsi" +- +-&tps { +- /delete-property/ ti,pmic-shutdown-controller; +- +- charger { +- interrupts = <0>, <1>; +- interrupt-names = "USB", "AC"; +- status = "okay"; +- }; +-}; +- +-&mmc1 { +- status = "okay"; +- vmmc-supply = <&vmmcsd_fixed>; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +-}; +- +-&mmc2 { +- status = "okay"; +- vmmc-supply = <&vmmcsd_fixed>; +- bus-width = <8>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +-}; +- +-&mmc3 { +- dmas = <&edma_xbar 12 0 1 +- &edma_xbar 13 0 2>; +- dma-names = "tx", "rx"; +- status = "okay"; +- vmmc-supply = <&wlan_en_reg>; +- bus-width = <4>; +- non-removable; +- cap-power-off-card; +- keep-power-in-suspend; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc3_pins &wl18xx_pins>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1835"; +- reg = <2>; +- interrupt-parent = <&gpio0>; +- interrupts = <21 IRQ_TYPE_EDGE_RISING>; +- }; +-}; +- +-&tscadc { +- status = "okay"; +- adc { +- ti,adc-channels = <0 1 2 3 4 5 6 7>; +- }; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins &bt_pins>; +- status = "okay"; +- +- bluetooth { +- compatible = "ti,wl1835-st"; +- enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&rtc { +- system-power-controller; +- clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; +- clock-names = "ext-clk", "int-clk"; +-}; +- +-&dcan1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&dcan1_pins>; +- status = "okay"; +-}; +- +-&gpio0 { +- gpio-line-names = +- "UART3_CTS", /* M17 */ +- "UART3_RTS", /* M18 */ +- "UART2_RX", /* A17 */ +- "UART2_TX", /* B17 */ +- "I2C1_SDA", /* B16 */ +- "I2C1_SCL", /* A16 */ +- "MMC0_CD", /* C15 */ +- "SPI1_SS2", /* C18 */ +- "EQEP_1A", /* V2 */ +- "EQEP_1B", /* V3 */ +- "MDIR_2B", /* V4 */ +- "BATT_LED_2", /* T5 */ +- "I2C2_SDA", /* D18 */ +- "I2C2_SCL", /* D17 */ +- "UART1_RX", /* D16 */ +- "UART1_TX", /* D15 */ +- "MMC2_DAT1", /* J18 */ +- "MMC2_DAT2", /* K15 */ +- "NC", /* F16 */ +- "WIFI_LED", /* A15 */ +- "MOT_STBY", /* D14 */ +- "WLAN_IRQ", /* K16 */ +- "PWM_2A", /* U10 */ +- "PWM_2B", /* T10 */ +- "", +- "", +- "BATT_LED_4", /* T11 */ +- "BATT_LED_1", /* U12 */ +- "BT_EN", /* K17 */ +- "SPI1_SS1", /* H18 */ +- "UART4_RX", /* T17 */ +- "MDIR_1B"; /* U17 */ +-}; +- +-&gpio1 { +- gpio-line-names = +- "MMC1_DAT0", /* U7 */ +- "MMC1_DAT1", /* V7 */ +- "MMC1_DAT2", /* R8 */ +- "MMC1_DAT3", /* T8 */ +- "MMC1_DAT4", /* U8 */ +- "MMC1_DAT5", /* V8 */ +- "MMC1_DAT6", /* R9 */ +- "MMC1_DAT7", /* T9 */ +- "DCAN1_TX", /* E18 */ +- "DCAN1_RX", /* E17 */ +- "UART0_RX", /* E15 */ +- "UART0_TX", /* E16 */ +- "EQEP_2A", /* T12 */ +- "EQEP_2B", /* R12 */ +- "PRU_E_A", /* V13 */ +- "PRU_E_B", /* U13 */ +- "MDIR_2A", /* R13 */ +- "GPIO1_17", /* V14 */ +- "PWM_1A", /* U14 */ +- "PWM_1B", /* T14 */ +- "EMMC_RST", /* R14 */ +- "USR_LED_0", /* V15 */ +- "USR_LED_1", /* U15 */ +- "USR_LED_2", /* T15 */ +- "USR_LED_3", /* V16 */ +- "GPIO1_25", /* U16 */ +- "MCASP0_AXR0", /* T16 */ +- "MCASP0_AXR1", /* V17 */ +- "MCASP0_ACLKR", /* U18 */ +- "BATT_LED_3", /* V6 */ +- "MMC1_CLK", /* U9 */ +- "MMC1_CMD"; /* V9 */ +-}; +- +-&gpio2 { +- gpio-line-names = +- "MDIR_1A", /* T13 */ +- "MCASP0_FSR", /* V12 */ +- "LED_RED", /* R7 */ +- "LED_GREEN", /* T7 */ +- "MODE_BTN", /* U6 */ +- "PAUSE_BTN", /* T6 */ +- "MDIR_4A", /* R1 */ +- "MDIR_4B", /* R2 */ +- "MDIR_3B", /* R3 */ +- "MDIR_3A", /* R4 */ +- "SVO7", /* T1 */ +- "SVO8", /* T2 */ +- "SVO5", /* T3 */ +- "SVO6", /* T4 */ +- "UART5_TX", /* U1 */ +- "UART5_RX", /* U2 */ +- "SERVO_EN", /* U3 */ +- "NC", /* U4 */ +- "UART3_RX", /* L17 */ +- "UART3_TX", /* L16 */ +- "MMC2_CLK", /* L15 */ +- "DCAN1_SILENT", /* M16 */ +- "SVO1", /* U5 */ +- "SVO3", /* R5 */ +- "SVO2", /* V5 */ +- "SVO4", /* R6 */ +- "MMC0_DAT3", /* F17 */ +- "MMC0_DAT2", /* F18 */ +- "MMC0_DAT1", /* G15 */ +- "MMC0_DAT0", /* G16 */ +- "MMC0_CLK", /* G17 */ +- "MMC0_CMD"; /* G18 */ +-}; +- +-&gpio3 { +- gpio-line-names = +- "MMC2_DAT3", /* H16 */ +- "GPIO3_1", /* H17 */ +- "GPIO3_2", /* J15 */ +- "MMC2_CMD", /* J16 */ +- "MMC2_DAT0", /* J17 */ +- "I2C0_SDA", /* C17 */ +- "I2C0_SCL", /* C16 */ +- "EMU1", /* C14 */ +- "EMU0", /* B14 */ +- "WL_EN", /* K18 */ +- "WL_BT_OE", /* L18 */ +- "", +- "", +- "NC", /* F15 */ +- "SPI1_SCK", /* A13 */ +- "SPI1_MISO", /* B13 */ +- "SPI1_MOSI", /* D12 */ +- "GPIO3_17", /* C12 */ +- "EQEP_0A", /* B12 */ +- "EQEP_0B", /* C13 */ +- "GPIO3_20", /* D13 */ +- "IMU_INT", /* A14 */ +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- ""; +- +- ls-buf-en-hog { +- gpio-hog; +- gpios = <10 GPIO_ACTIVE_HIGH>; +- output-high; +- }; +-}; +- +-&epwmss0 { +- status = "okay"; +-}; +- +-&eqep0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&eqep0_pins>; +- status = "okay"; +-}; +- +-&epwmss1 { +- status = "okay"; +-}; +- +-&eqep1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&eqep1_pins>; +- status = "okay"; +-}; +- +-&epwmss2 { +- status = "okay"; +-}; +- +-&eqep2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&eqep2_pins>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-bonegreen-common.dtsi b/scripts/dtc/include-prefixes/arm/am335x-bonegreen-common.dtsi +deleted file mode 100644 +index 9f7fb63744d0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-bonegreen-common.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-&ldo3_reg { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +-}; +- +-&mmc1 { +- vmmc-supply = <&vmmcsd_fixed>; +-}; +- +-&mmc2 { +- vmmc-supply = <&vmmcsd_fixed>; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_pins>; +- bus-width = <8>; +- status = "okay"; +-}; +- +-&am33xx_pinmux { +- uart2_pins: uart2_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd */ +- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd */ +- >; +- }; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "okay"; +-}; +- +-&rtc { +- system-power-controller; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-bonegreen-wireless.dts b/scripts/dtc/include-prefixes/arm/am335x-bonegreen-wireless.dts +deleted file mode 100644 +index 215f279e476b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-bonegreen-wireless.dts ++++ /dev/null +@@ -1,127 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "am33xx.dtsi" +-#include "am335x-bone-common.dtsi" +-#include "am335x-bonegreen-common.dtsi" +-#include +- +-/ { +- model = "TI AM335x BeagleBone Green Wireless"; +- compatible = "ti,am335x-bone-green-wireless", "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +- +- wlan_en_reg: fixedregulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "wlan-en-regulator"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- startup-delay-us= <70000>; +- +- /* WL_EN */ +- gpio = <&gpio0 26 0>; +- enable-active-high; +- }; +-}; +- +-&am33xx_pinmux { +- bt_pins: pinmux_bt_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_ad12.gpio1_28 BT_EN */ +- >; +- }; +- +- mmc3_pins: pinmux_mmc3_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */ +- >; +- }; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* gmii1_rxd2.uart3_txd */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* mdio_data.uart3_ctsn */ +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* mdio_clk.uart3_rtsn */ +- >; +- }; +- +- wl18xx_pins: pinmux_wl18xx_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad10.gpio0_26 WL_EN */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad11.gpio0_27 WL_IRQ */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 LS_BUF_EN */ +- >; +- }; +-}; +- +-&mac_sw { +- status = "disabled"; +-}; +- +-&mmc3 { +- dmas = <&edma_xbar 12 0 1 +- &edma_xbar 13 0 2>; +- dma-names = "tx", "rx"; +- status = "okay"; +- vmmc-supply = <&wlan_en_reg>; +- bus-width = <4>; +- non-removable; +- cap-power-off-card; +- keep-power-in-suspend; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc3_pins &wl18xx_pins>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1835"; +- reg = <2>; +- interrupt-parent = <&gpio0>; +- interrupts = <27 IRQ_TYPE_EDGE_RISING>; +- }; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins &bt_pins>; +- status = "okay"; +- +- bluetooth { +- compatible = "ti,wl1835-st"; +- enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&gpio1 { +- ls-buf-en-hog { +- gpio-hog; +- gpios = <29 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "LS_BUF_EN"; +- }; +-}; +- +-/* BT_AUD_OUT from wl1835 has to be pulled low when WL_EN is activated.*/ +-/* in case it isn't, wilink8 ends up in one of the test modes that */ +-/* intruces various issues (elp wkaeup timeouts etc.) */ +-/* On the BBGW this pin is routed through the level shifter (U21) that */ +-/* introduces a pullup on the line and wilink8 ends up in a bad state. */ +-/* use a gpio hog to force this pin low. An alternative may be adding */ +-/* an external pulldown on U21 pin 4. */ +- +-&gpio3 { +- bt-aud-in-hog { +- gpio-hog; +- gpios = <16 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "MCASP0_AHCLKR"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-bonegreen.dts b/scripts/dtc/include-prefixes/arm/am335x-bonegreen.dts +deleted file mode 100644 +index 18cc0f49e999..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-bonegreen.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "am33xx.dtsi" +-#include "am335x-bone-common.dtsi" +-#include "am335x-bonegreen-common.dtsi" +- +-/ { +- model = "TI AM335x BeagleBone Green"; +- compatible = "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-chiliboard.dts b/scripts/dtc/include-prefixes/arm/am335x-chiliboard.dts +deleted file mode 100644 +index a223cdd3e30e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-chiliboard.dts ++++ /dev/null +@@ -1,186 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/ +- * Author: Rostislav Lisovy +- */ +-/dts-v1/; +-#include "am335x-chilisom.dtsi" +- +-/ { +- model = "AM335x Chiliboard"; +- compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom", +- "ti,am33xx"; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_gpio_pins>; +- +- led0 { +- label = "led0"; +- gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led1 { +- label = "led1"; +- gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- }; +-}; +- +-&am33xx_pinmux { +- uart0_pins: pinmux_uart0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- cpsw_default: cpsw_default { +- pinctrl-single,pins = < +- /* Slave 1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- cpsw_sleep: cpsw_sleep { +- pinctrl-single,pins = < +- /* Slave 1 reset value */ +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- davinci_mdio_default: davinci_mdio_default { +- pinctrl-single,pins = < +- /* mdio_data.mdio_data */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) +- /* mdio_clk.mdio_clk */ +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- davinci_mdio_sleep: davinci_mdio_sleep { +- pinctrl-single,pins = < +- /* MDIO reset value */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- usb1_drvvbus: usb1_drvvbus { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- sd_pins: pinmux_sd_card { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ +- >; +- }; +- +- led_gpio_pins: led_gpio_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_OUTPUT, MUX_MODE7) /* emu0.gpio3_7 */ +- AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT, MUX_MODE7) /* emu1.gpio3_8 */ +- >; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- +- status = "okay"; +-}; +- +-&ldo4_reg { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +-}; +- +-/* Ethernet */ +-&mac_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&cpsw_default>; +- pinctrl-1 = <&cpsw_sleep>; +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&davinci_mdio_default>; +- pinctrl-1 = <&davinci_mdio_sleep>; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "rmii"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- status = "disabled"; +-}; +- +-/* USB */ +-&usb1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb1_drvvbus>; +- dr_mode = "host"; +-}; +- +-/* microSD */ +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sd_pins>; +- vmmc-supply = <&ldo4_reg>; +- bus-width = <0x4>; +- cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&tps { +- interrupt-parent = <&intc>; +- interrupts = <7>; /* NNMI */ +- +- charger { +- status = "okay"; +- }; +- +- pwrbutton { +- status = "okay"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-chilisom.dtsi b/scripts/dtc/include-prefixes/arm/am335x-chilisom.dtsi +deleted file mode 100644 +index 43b61e43ed1e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-chilisom.dtsi ++++ /dev/null +@@ -1,175 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/ +- * Author: Rostislav Lisovy +- */ +-#include "am33xx.dtsi" +-#include +- +-/ { +- model = "Grinn AM335x ChiliSOM"; +- compatible = "grinn,am335x-chilisom", "ti,am33xx"; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&dcdc2_reg>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512 MB */ +- }; +-}; +- +-&am33xx_pinmux { +- pinctrl-names = "default"; +- +- i2c0_pins: pinmux_i2c0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- nandflash_pins: nandflash_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE0) +- +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT_PULLUP, MUX_MODE0) +- >; +- }; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- tps: tps@24 { +- reg = <0x24>; +- }; +- +-}; +- +-/include/ "tps65217.dtsi" +- +-&tps { +- regulators { +- dcdc1_reg: regulator@0 { +- regulator-name = "vdds_dpr"; +- regulator-always-on; +- }; +- +- dcdc2_reg: regulator@1 { +- /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <1325000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc3_reg: regulator@2 { +- /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <1150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1_reg: regulator@3 { +- regulator-name = "vio,vrtc,vdds"; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo2_reg: regulator@4 { +- regulator-name = "vdd_3v3aux"; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo3_reg: regulator@5 { +- regulator-name = "vdd_1v8"; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo4_reg: regulator@6 { +- regulator-name = "vdd_3v3d"; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +-}; +- +-&rtc { +- system-power-controller; +- +- pinctrl-0 = <&ext_wakeup>; +- pinctrl-names = "default"; +- +- ext_wakeup: ext-wakeup { +- pins = "ext_wakeup0"; +- input-enable; +- }; +-}; +- +-/* NAND Flash */ +-&elm { +- status = "okay"; +-}; +- +-&gpmc { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&nandflash_pins>; +- ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */ +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ +- ti,nand-ecc-opt = "bch8"; +- ti,elm-id = <&elm>; +- nand-bus-width = <8>; +- gpmc,device-width = <1>; +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-on-ns = <0>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-cm-t335.dts b/scripts/dtc/include-prefixes/arm/am335x-cm-t335.dts +deleted file mode 100644 +index d9f003d886bf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-cm-t335.dts ++++ /dev/null +@@ -1,516 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * am335x-cm-t335.dts - Device Tree file for Compulab CM-T335 +- * +- * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/ +- */ +- +-/dts-v1/; +- +-#include "am33xx.dtsi" +-#include +- +-/ { +- model = "CompuLab CM-T335"; +- compatible = "compulab,cm-t335", "ti,am33xx"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x8000000>; /* 128 MB */ +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_led_pins>; +- led0 { +- label = "cm_t335:green"; +- gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* gpio2_0 */ +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- /* regulator for mmc */ +- vmmc_fixed: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmc_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- /* Regulator for WiFi */ +- vwlan_fixed: fixedregulator2 { +- compatible = "regulator-fixed"; +- regulator-name = "vwlan_fixed"; +- gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; /* gpio0_20 */ +- enable-active-high; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&ecap0 0 50000 0>; +- brightness-levels = <0 51 53 56 62 75 101 152 255>; +- default-brightness-level = <8>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "cm-t335"; +- +- simple-audio-card,widgets = +- "Microphone", "Mic Jack", +- "Line", "Line In", +- "Headphone", "Headphone Jack"; +- +- simple-audio-card,routing = +- "Headphone Jack", "LHPOUT", +- "Headphone Jack", "RHPOUT", +- "LLINEIN", "Line In", +- "RLINEIN", "Line In", +- "MICIN", "Mic Jack"; +- +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sound_master>; +- simple-audio-card,frame-master = <&sound_master>; +- +- simple-audio-card,cpu { +- sound-dai = <&mcasp1>; +- }; +- +- sound_master: simple-audio-card,codec { +- sound-dai = <&tlv320aic23>; +- system-clock-frequency = <12000000>; +- }; +- }; +-}; +- +-&am33xx_pinmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&bluetooth_pins>; +- +- i2c0_pins: pinmux_i2c0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- /* uart0_ctsn.i2c1_sda */ +- AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE2) +- /* uart0_rtsn.i2c1_scl */ +- AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) +- >; +- }; +- +- gpio_led_pins: pinmux_gpio_led_pins { +- pinctrl-single,pins = < +- /* gpmc_csn3.gpio2_0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE7) +- >; +- }; +- +- nandflash_pins: pinmux_nandflash_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) +- /* gpmc_wpn.gpio0_31 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) +- >; +- }; +- +- uart0_pins: pinmux_uart0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- uart1_pins: pinmux_uart1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- dcan0_pins: pinmux_dcan0_pins { +- pinctrl-single,pins = < +- /* uart1_ctsn.dcan0_tx */ +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) +- /* uart1_rtsn.dcan0_rx */ +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT, MUX_MODE2) +- >; +- }; +- +- dcan1_pins: pinmux_dcan1_pins { +- pinctrl-single,pins = < +- /* uart1_rxd.dcan1_tx */ +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT, MUX_MODE2) +- /* uart1_txd.dcan1_rx */ +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE2) +- >; +- }; +- +- ecap0_pins: pinmux_ecap0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) +- >; +- }; +- +- cpsw_default: cpsw_default { +- pinctrl-single,pins = < +- /* Slave 1 */ +- /* mii1_tx_en.rgmii1_tctl */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) +- /* mii1_rxdv.rgmii1_rctl */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) +- /* mii1_txd3.rgmii1_td3 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) +- /* mii1_txd2.rgmii1_td2 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) +- /* mii1_txd1.rgmii1_td1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) +- /* mii1_txd0.rgmii1_td0 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) +- /* mii1_txclk.rgmii1_tclk */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) +- /* mii1_rxclk.rgmii1_rclk */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) +- /* mii1_rxd3.rgmii1_rd3 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) +- /* mii1_rxd2.rgmii1_rd2 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) +- /* mii1_rxd1.rgmii1_rd1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) +- /* mii1_rxd0.rgmii1_rd0 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) +- >; +- }; +- +- cpsw_sleep: cpsw_sleep { +- pinctrl-single,pins = < +- /* Slave 1 reset value */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- davinci_mdio_default: davinci_mdio_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- davinci_mdio_sleep: davinci_mdio_sleep { +- pinctrl-single,pins = < +- /* MDIO reset value */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- spi0_pins: pinmux_spi0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_OUTPUT, MUX_MODE0) +- >; +- }; +- +- /* wl1271 bluetooth */ +- bluetooth_pins: pinmux_bluetooth_pins { +- pinctrl-single,pins = < +- /* XDMA_EVENT_INTR0.gpio0_19 - bluetooth enable */ +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLUP, MUX_MODE7) +- >; +- }; +- +- /* TLV320AIC23B codec */ +- mcasp1_pins: pinmux_mcasp1_pins { +- pinctrl-single,pins = < +- /* MII1_CRS.mcasp1_aclkx */ +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) +- /* MII1_RX_ER.mcasp1_fsx */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) +- /* MII1_COL.mcasp1_axr2 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE4) +- /* RMII1_REF_CLK.mcasp1_axr3 */ +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) +- >; +- }; +- +- /* wl1271 WiFi */ +- wifi_pins: pinmux_wifi_pins { +- pinctrl-single,pins = < +- /* EMU1.gpio3_8 - WiFi IRQ */ +- AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7) +- /* XDMA_EVENT_INTR1.gpio0_20 - WiFi enable */ +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) +- >; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- +- status = "okay"; +-}; +- +-/* WLS1271 bluetooth */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- +-status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- +- status = "okay"; +- clock-frequency = <400000>; +- /* CM-T335 board EEPROM */ +- eeprom: 24c02@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- /* Real Time Clock */ +- ext_rtc: em3027@56 { +- compatible = "emmicro,em3027"; +- reg = <0x56>; +- }; +- /* Audio codec */ +- tlv320aic23: codec@1a { +- compatible = "ti,tlv320aic23"; +- reg = <0x1a>; +- #sound-dai-cells= <0>; +- status = "okay"; +- }; +-}; +- +-&epwmss0 { +- status = "okay"; +- +- ecap0: pwm@100 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ecap0_pins>; +- }; +-}; +- +-&gpmc { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&nandflash_pins>; +- ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ +- ti,nand-ecc-opt = "bch8"; +- ti,elm-id = <&elm>; +- nand-bus-width = <8>; +- gpmc,device-width = <1>; +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-on-ns = <0>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- /* MTD partition table */ +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "spl"; +- reg = <0x00000000 0x00200000>; +- }; +- partition@1 { +- label = "uboot"; +- reg = <0x00200000 0x00100000>; +- }; +- partition@2 { +- label = "uboot environment"; +- reg = <0x00300000 0x00100000>; +- }; +- partition@3 { +- label = "dtb"; +- reg = <0x00400000 0x00100000>; +- }; +- partition@4 { +- label = "splash"; +- reg = <0x00500000 0x00400000>; +- }; +- partition@5 { +- label = "linux"; +- reg = <0x00900000 0x00600000>; +- }; +- partition@6 { +- label = "rootfs"; +- reg = <0x00F00000 0>; +- }; +- }; +-}; +- +-&elm { +- status = "okay"; +-}; +- +-&mac_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&cpsw_default>; +- pinctrl-1 = <&cpsw_sleep>; +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&davinci_mdio_default>; +- pinctrl-1 = <&davinci_mdio_sleep>; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "rgmii-txid"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- status = "disabled"; +-}; +- +-&mmc1 { +- status = "okay"; +- vmmc-supply = <&vmmc_fixed>; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +-}; +- +-&dcan0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dcan0_pins>; +-}; +- +-&dcan1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dcan1_pins>; +-}; +- +-/* Touschscreen and analog digital converter */ +-&tscadc { +- status = "okay"; +- tsc { +- ti,wires = <4>; +- ti,x-plate-resistance = <200>; +- ti,coordinate-readouts = <5>; +- ti,wire-config = <0x01 0x10 0x23 0x32>; +- ti,charge-delay = <0x400>; +- }; +- +- adc { +- ti,adc-channels = <4 5 6 7>; +- }; +-}; +- +-/* CPU audio */ +-&mcasp1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcasp1_pins>; +- +- op-mode = <0>; /* MCASP_IIS_MODE */ +- tdm-slots = <2>; +- /* 16 serializers */ +- num-serializer = <16>; +- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ +- 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 +- >; +- tx-num-evt = <1>; +- rx-num-evt = <1>; +- +- #sound-dai-cells= <0>; +- status = "okay"; +-}; +- +-&spi0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins>; +- ti,pindir-d0-out-d1-in; +- /* WLS1271 WiFi */ +- wlcore: wlcore@1 { +- compatible = "ti,wl1271"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_pins>; +- reg = <1>; +- spi-max-frequency = <48000000>; +- clock-xtal; +- ref-clock-frequency = <38400000>; +- interrupt-parent = <&gpio3>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; +- vwlan-supply = <&vwlan_fixed>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-evm.dts b/scripts/dtc/include-prefixes/arm/am335x-evm.dts +deleted file mode 100644 +index 659e99eabe66..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-evm.dts ++++ /dev/null +@@ -1,784 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "am33xx.dtsi" +-#include +- +-/ { +- model = "TI AM335x EVM"; +- compatible = "ti,am335x-evm", "ti,am33xx"; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&vdd1_reg>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- vbat: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vbat"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- }; +- +- lis3_reg: fixedregulator1 { +- compatible = "regulator-fixed"; +- regulator-name = "lis3_reg"; +- regulator-boot-on; +- }; +- +- wlan_en_reg: fixedregulator2 { +- compatible = "regulator-fixed"; +- regulator-name = "wlan-en-regulator"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- /* WLAN_EN GPIO for this board - Bank1, pin16 */ +- gpio = <&gpio1 16 0>; +- +- /* WLAN card specific delay */ +- startup-delay-us = <70000>; +- enable-active-high; +- }; +- +- /* TPS79501 */ +- v1_8d_reg: fixedregulator-v1_8d { +- compatible = "regulator-fixed"; +- regulator-name = "v1_8d"; +- vin-supply = <&vbat>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- /* TPS79501 */ +- v3_3d_reg: fixedregulator-v3_3d { +- compatible = "regulator-fixed"; +- regulator-name = "v3_3d"; +- vin-supply = <&vbat>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- matrix_keypad: matrix_keypad0 { +- compatible = "gpio-matrix-keypad"; +- debounce-delay-ms = <5>; +- col-scan-delay-us = <2>; +- +- row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */ +- &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */ +- &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */ +- +- col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */ +- &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */ +- +- linux,keymap = <0x0000008b /* MENU */ +- 0x0100009e /* BACK */ +- 0x02000069 /* LEFT */ +- 0x0001006a /* RIGHT */ +- 0x0101001c /* ENTER */ +- 0x0201006c>; /* DOWN */ +- }; +- +- gpio_keys: volume_keys0 { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- autorepeat; +- +- switch9 { +- label = "volume-up"; +- linux,code = <115>; +- gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; +- wakeup-source; +- }; +- +- switch10 { +- label = "volume-down"; +- linux,code = <114>; +- gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; +- wakeup-source; +- }; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&ecap0 0 50000 0>; +- brightness-levels = <0 51 53 56 62 75 101 152 255>; +- default-brightness-level = <8>; +- }; +- +- panel { +- compatible = "tfc,s9700rtwv43tr-01b"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_pins_s0>; +- backlight = <&backlight>; +- +- port { +- panel_0: endpoint@0 { +- remote-endpoint = <&lcdc_0>; +- }; +- }; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "AM335x-EVM"; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack", +- "Line", "Line In"; +- simple-audio-card,routing = +- "Headphone Jack", "HPLOUT", +- "Headphone Jack", "HPROUT", +- "LINE1L", "Line In", +- "LINE1R", "Line In"; +- simple-audio-card,format = "dsp_b"; +- simple-audio-card,bitclock-master = <&sound_master>; +- simple-audio-card,frame-master = <&sound_master>; +- simple-audio-card,bitclock-inversion; +- +- simple-audio-card,cpu { +- sound-dai = <&mcasp1>; +- }; +- +- sound_master: simple-audio-card,codec { +- sound-dai = <&tlv320aic3106>; +- system-clock-frequency = <12000000>; +- }; +- }; +-}; +- +-&am33xx_pinmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; +- +- matrix_keypad_s0: matrix_keypad_s0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a6.gpio1_22 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a9.gpio1_25 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a10.gpio1_26 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */ +- >; +- }; +- +- volume_keys_s0: volume_keys_s0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_sclk.gpio0_2 */ +- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_d0.gpio0_3 */ +- >; +- }; +- +- i2c0_pins: pinmux_i2c0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ +- >; +- }; +- +- uart0_pins: pinmux_uart0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- uart1_pins: pinmux_uart1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- clkout2_pin: pinmux_clkout2_pin { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ +- >; +- }; +- +- nandflash_pins_s0: nandflash_pins_s0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) +- >; +- }; +- +- ecap0_pins: backlight_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) +- >; +- }; +- +- cpsw_default: cpsw_default { +- pinctrl-single,pins = < +- /* Slave 1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ +- >; +- }; +- +- cpsw_sleep: cpsw_sleep { +- pinctrl-single,pins = < +- /* Slave 1 reset value */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- davinci_mdio_default: davinci_mdio_default { +- pinctrl-single,pins = < +- /* MDIO */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- davinci_mdio_sleep: davinci_mdio_sleep { +- pinctrl-single,pins = < +- /* MDIO reset value */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */ +- >; +- }; +- +- mmc3_pins: pinmux_mmc3_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */ +- >; +- }; +- +- wlan_pins: pinmux_wlan_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a0.gpio1_16 */ +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */ +- >; +- }; +- +- lcd_pins_s0: lcd_pins_s0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) +- >; +- }; +- +- mcasp1_pins: mcasp1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ +- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */ +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ +- >; +- }; +- +- mcasp1_pins_sleep: mcasp1_pins_sleep { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- dcan1_pins_default: dcan1_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ +- AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ +- >; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- tps: tps@2d { +- reg = <0x2d>; +- }; +-}; +- +-&usb1 { +- dr_mode = "host"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- +- status = "okay"; +- clock-frequency = <100000>; +- +- lis331dlh: lis331dlh@18 { +- compatible = "st,lis331dlh", "st,lis3lv02d"; +- reg = <0x18>; +- Vdd-supply = <&lis3_reg>; +- Vdd_IO-supply = <&lis3_reg>; +- +- st,click-single-x; +- st,click-single-y; +- st,click-single-z; +- st,click-thresh-x = <10>; +- st,click-thresh-y = <10>; +- st,click-thresh-z = <10>; +- st,irq1-click; +- st,irq2-click; +- st,wakeup-x-lo; +- st,wakeup-x-hi; +- st,wakeup-y-lo; +- st,wakeup-y-hi; +- st,wakeup-z-lo; +- st,wakeup-z-hi; +- st,min-limit-x = <120>; +- st,min-limit-y = <120>; +- st,min-limit-z = <140>; +- st,max-limit-x = <550>; +- st,max-limit-y = <550>; +- st,max-limit-z = <750>; +- }; +- +- tsl2550: tsl2550@39 { +- compatible = "taos,tsl2550"; +- reg = <0x39>; +- }; +- +- tmp275: tmp275@48 { +- compatible = "ti,tmp275"; +- reg = <0x48>; +- }; +- +- tlv320aic3106: tlv320aic3106@1b { +- #sound-dai-cells = <0>; +- compatible = "ti,tlv320aic3106"; +- reg = <0x1b>; +- status = "okay"; +- +- /* Regulators */ +- AVDD-supply = <&v3_3d_reg>; +- IOVDD-supply = <&v3_3d_reg>; +- DRVDD-supply = <&v3_3d_reg>; +- DVDD-supply = <&v1_8d_reg>; +- }; +-}; +- +-&lcdc { +- status = "okay"; +- +- blue-and-red-wiring = "crossed"; +- +- port { +- lcdc_0: endpoint@0 { +- remote-endpoint = <&panel_0>; +- }; +- }; +-}; +- +-&elm { +- status = "okay"; +-}; +- +-&epwmss0 { +- status = "okay"; +- +- ecap0: pwm@100 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ecap0_pins>; +- }; +-}; +- +-&gpmc { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&nandflash_pins_s0>; +- ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ +- ti,nand-xfer-type = "prefetch-dma"; +- ti,nand-ecc-opt = "bch8"; +- ti,elm-id = <&elm>; +- nand-bus-width = <8>; +- gpmc,device-width = <1>; +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-on-ns = <0>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- /* MTD partition table */ +- /* All SPL-* partitions are sized to minimal length +- * which can be independently programmable. For +- * NAND flash this is equal to size of erase-block */ +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "NAND.SPL"; +- reg = <0x00000000 0x000020000>; +- }; +- partition@1 { +- label = "NAND.SPL.backup1"; +- reg = <0x00020000 0x00020000>; +- }; +- partition@2 { +- label = "NAND.SPL.backup2"; +- reg = <0x00040000 0x00020000>; +- }; +- partition@3 { +- label = "NAND.SPL.backup3"; +- reg = <0x00060000 0x00020000>; +- }; +- partition@4 { +- label = "NAND.u-boot-spl-os"; +- reg = <0x00080000 0x00040000>; +- }; +- partition@5 { +- label = "NAND.u-boot"; +- reg = <0x000C0000 0x00100000>; +- }; +- partition@6 { +- label = "NAND.u-boot-env"; +- reg = <0x001C0000 0x00020000>; +- }; +- partition@7 { +- label = "NAND.u-boot-env.backup1"; +- reg = <0x001E0000 0x00020000>; +- }; +- partition@8 { +- label = "NAND.kernel"; +- reg = <0x00200000 0x00800000>; +- }; +- partition@9 { +- label = "NAND.file-system"; +- reg = <0x00A00000 0x0F600000>; +- }; +- }; +-}; +- +-#include "tps65910.dtsi" +- +-&mcasp1 { +- #sound-dai-cells = <0>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mcasp1_pins>; +- pinctrl-1 = <&mcasp1_pins_sleep>; +- +- status = "okay"; +- +- op-mode = <0>; /* MCASP_IIS_MODE */ +- tdm-slots = <2>; +- /* 4 serializers */ +- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ +- 0 0 1 2 +- >; +- tx-num-evt = <32>; +- rx-num-evt = <32>; +-}; +- +-&tps { +- vcc1-supply = <&vbat>; +- vcc2-supply = <&vbat>; +- vcc3-supply = <&vbat>; +- vcc4-supply = <&vbat>; +- vcc5-supply = <&vbat>; +- vcc6-supply = <&vbat>; +- vcc7-supply = <&vbat>; +- vccio-supply = <&vbat>; +- +- regulators { +- vrtc_reg: regulator@0 { +- regulator-always-on; +- }; +- +- vio_reg: regulator@1 { +- regulator-always-on; +- }; +- +- vdd1_reg: regulator@2 { +- /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <912500>; +- regulator-max-microvolt = <1351500>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd2_reg: regulator@3 { +- /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <912500>; +- regulator-max-microvolt = <1150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd3_reg: regulator@4 { +- regulator-always-on; +- }; +- +- vdig1_reg: regulator@5 { +- regulator-always-on; +- }; +- +- vdig2_reg: regulator@6 { +- regulator-always-on; +- }; +- +- vpll_reg: regulator@7 { +- regulator-always-on; +- }; +- +- vdac_reg: regulator@8 { +- regulator-always-on; +- }; +- +- vaux1_reg: regulator@9 { +- regulator-always-on; +- }; +- +- vaux2_reg: regulator@10 { +- regulator-always-on; +- }; +- +- vaux33_reg: regulator@11 { +- regulator-always-on; +- }; +- +- vmmc_reg: regulator@12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +-}; +- +-&mac_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&cpsw_default>; +- pinctrl-1 = <&cpsw_sleep>; +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&davinci_mdio_default>; +- pinctrl-1 = <&davinci_mdio_sleep>; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "rgmii-id"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- status = "disabled"; +-}; +- +-&tscadc { +- status = "okay"; +- tsc { +- ti,wires = <4>; +- ti,x-plate-resistance = <200>; +- ti,coordinate-readouts = <5>; +- ti,wire-config = <0x00 0x11 0x22 0x33>; +- ti,charge-delay = <0x400>; +- }; +- +- adc { +- ti,adc-channels = <4 5 6 7>; +- }; +-}; +- +-&mmc1 { +- status = "okay"; +- vmmc-supply = <&vmmc_reg>; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +-}; +- +-&mmc3 { +- /* these are on the crossbar and are outlined in the +- xbar-event-map element */ +- dmas = <&edma_xbar 12 0 1 +- &edma_xbar 13 0 2>; +- dma-names = "tx", "rx"; +- status = "okay"; +- vmmc-supply = <&wlan_en_reg>; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc3_pins &wlan_pins>; +- non-removable; +- cap-power-off-card; +- keep-power-in-suspend; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@0 { +- compatible = "ti,wl1835"; +- reg = <2>; +- interrupt-parent = <&gpio3>; +- interrupts = <17 IRQ_TYPE_EDGE_RISING>; +- }; +-}; +- +-&sham { +- status = "okay"; +-}; +- +-&aes { +- status = "okay"; +-}; +- +-&dcan1 { +- status = "disabled"; /* Enable only if Profile 1 is selected */ +- pinctrl-names = "default"; +- pinctrl-0 = <&dcan1_pins_default>; +-}; +- +-&rtc { +- clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; +- clock-names = "ext-clk", "int-clk"; +-}; +- +-&pruss_tm { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-evmsk.dts b/scripts/dtc/include-prefixes/arm/am335x-evmsk.dts +deleted file mode 100644 +index a2db65538e51..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-evmsk.dts ++++ /dev/null +@@ -1,721 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/* +- * AM335x Starter Kit +- * http://www.ti.com/tool/tmdssk3358 +- */ +- +-/dts-v1/; +- +-#include "am33xx.dtsi" +-#include +-#include +- +-/ { +- model = "TI AM335x EVM-SK"; +- compatible = "ti,am335x-evmsk", "ti,am33xx"; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&vdd1_reg>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- vbat: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vbat"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- }; +- +- lis3_reg: fixedregulator1 { +- compatible = "regulator-fixed"; +- regulator-name = "lis3_reg"; +- regulator-boot-on; +- }; +- +- wl12xx_vmmc: fixedregulator2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&wl12xx_gpio>; +- compatible = "regulator-fixed"; +- regulator-name = "vwl1271"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio1 29 0>; +- startup-delay-us = <70000>; +- enable-active-high; +- }; +- +- vtt_fixed: fixedregulator3 { +- compatible = "regulator-fixed"; +- regulator-name = "vtt"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- }; +- +- /* TPS79518 */ +- v1_8d_reg: fixedregulator-v1_8d { +- compatible = "regulator-fixed"; +- regulator-name = "v1_8d"; +- vin-supply = <&vbat>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- /* TPS78633 */ +- v3_3d_reg: fixedregulator-v3_3d { +- compatible = "regulator-fixed"; +- regulator-name = "v3_3d"; +- vin-supply = <&vbat>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&user_leds_s0>; +- +- compatible = "gpio-leds"; +- +- led1 { +- label = "evmsk:green:usr0"; +- gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led2 { +- label = "evmsk:green:usr1"; +- gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led3 { +- label = "evmsk:green:mmc0"; +- gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- +- led4 { +- label = "evmsk:green:heartbeat"; +- gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- }; +- +- gpio_buttons: gpio_buttons0 { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch1 { +- label = "button0"; +- linux,code = <0x100>; +- gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; +- }; +- +- switch2 { +- label = "button1"; +- linux,code = <0x101>; +- gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; +- }; +- +- switch3 { +- label = "button2"; +- linux,code = <0x102>; +- gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; +- wakeup-source; +- }; +- +- switch4 { +- label = "button3"; +- linux,code = <0x103>; +- gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- lcd_bl: backlight { +- compatible = "pwm-backlight"; +- pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>; +- brightness-levels = <0 58 61 66 75 90 125 170 255>; +- default-brightness-level = <8>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "AM335x-EVMSK"; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "Headphone Jack", "HPLOUT", +- "Headphone Jack", "HPROUT"; +- simple-audio-card,format = "dsp_b"; +- simple-audio-card,bitclock-master = <&sound_master>; +- simple-audio-card,frame-master = <&sound_master>; +- simple-audio-card,bitclock-inversion; +- +- simple-audio-card,cpu { +- sound-dai = <&mcasp1>; +- }; +- +- sound_master: simple-audio-card,codec { +- sound-dai = <&tlv320aic3106>; +- system-clock-frequency = <24000000>; +- }; +- }; +- +- panel { +- compatible = "newhaven,nhd-4.3-480272ef-atxl"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&lcd_pins_default>; +- pinctrl-1 = <&lcd_pins_sleep>; +- backlight = <&lcd_bl>; +- +- port { +- panel_0: endpoint@0 { +- remote-endpoint = <&lcdc_0>; +- }; +- }; +- }; +-}; +- +-&am33xx_pinmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; +- +- lcd_pins_default: lcd_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) +- >; +- }; +- +- lcd_pins_sleep: lcd_pins_sleep { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad8.lcd_data23 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad9.lcd_data22 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad10.lcd_data21 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad11.lcd_data20 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.lcd_data19 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.lcd_data18 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.lcd_data17 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.lcd_data16 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- +- user_leds_s0: user_leds_s0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad4.gpio1_4 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad5.gpio1_5 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad6.gpio1_6 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad7.gpio1_7 */ +- >; +- }; +- +- gpio_keys_s0: gpio_keys_s0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_wait0.gpio0_30 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ +- >; +- }; +- +- i2c0_pins: pinmux_i2c0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- uart0_pins: pinmux_uart0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- clkout2_pin: pinmux_clkout2_pin { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ +- >; +- }; +- +- ecap2_pins: backlight_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, 0x0, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */ +- >; +- }; +- +- cpsw_default: cpsw_default { +- pinctrl-single,pins = < +- /* Slave 1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ +- +- /* Slave 2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ +- >; +- }; +- +- cpsw_sleep: cpsw_sleep { +- pinctrl-single,pins = < +- /* Slave 1 reset value */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- +- /* Slave 2 reset value*/ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- davinci_mdio_default: davinci_mdio_default { +- pinctrl-single,pins = < +- /* MDIO */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- davinci_mdio_sleep: davinci_mdio_sleep { +- pinctrl-single,pins = < +- /* MDIO reset value */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */ +- >; +- }; +- +- mcasp1_pins: mcasp1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ +- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */ +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ +- >; +- }; +- +- mcasp1_pins_sleep: mcasp1_pins_sleep { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ +- >; +- }; +- +- wl12xx_gpio: pinmux_wl12xx_gpio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */ +- >; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- tps: tps@2d { +- reg = <0x2d>; +- }; +- +- lis331dlh: lis331dlh@18 { +- compatible = "st,lis331dlh", "st,lis3lv02d"; +- reg = <0x18>; +- Vdd-supply = <&lis3_reg>; +- Vdd_IO-supply = <&lis3_reg>; +- +- st,click-single-x; +- st,click-single-y; +- st,click-single-z; +- st,click-thresh-x = <10>; +- st,click-thresh-y = <10>; +- st,click-thresh-z = <10>; +- st,irq1-click; +- st,irq2-click; +- st,wakeup-x-lo; +- st,wakeup-x-hi; +- st,wakeup-y-lo; +- st,wakeup-y-hi; +- st,wakeup-z-lo; +- st,wakeup-z-hi; +- st,min-limit-x = <120>; +- st,min-limit-y = <120>; +- st,min-limit-z = <140>; +- st,max-limit-x = <550>; +- st,max-limit-y = <550>; +- st,max-limit-z = <750>; +- }; +- +- tlv320aic3106: tlv320aic3106@1b { +- #sound-dai-cells = <0>; +- compatible = "ti,tlv320aic3106"; +- reg = <0x1b>; +- status = "okay"; +- +- /* Regulators */ +- AVDD-supply = <&v3_3d_reg>; +- IOVDD-supply = <&v3_3d_reg>; +- DRVDD-supply = <&v3_3d_reg>; +- DVDD-supply = <&v1_8d_reg>; +- }; +-}; +- +-&usb1 { +- dr_mode = "host"; +-}; +- +-&epwmss2 { +- status = "okay"; +- +- ecap2: pwm@100 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ecap2_pins>; +- }; +-}; +- +-#include "tps65910.dtsi" +- +-&tps { +- vcc1-supply = <&vbat>; +- vcc2-supply = <&vbat>; +- vcc3-supply = <&vbat>; +- vcc4-supply = <&vbat>; +- vcc5-supply = <&vbat>; +- vcc6-supply = <&vbat>; +- vcc7-supply = <&vbat>; +- vccio-supply = <&vbat>; +- +- regulators { +- vrtc_reg: regulator@0 { +- regulator-always-on; +- }; +- +- vio_reg: regulator@1 { +- regulator-always-on; +- }; +- +- vdd1_reg: regulator@2 { +- /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <912500>; +- regulator-max-microvolt = <1351500>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd2_reg: regulator@3 { +- /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <912500>; +- regulator-max-microvolt = <1150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd3_reg: regulator@4 { +- regulator-always-on; +- }; +- +- vdig1_reg: regulator@5 { +- regulator-always-on; +- }; +- +- vdig2_reg: regulator@6 { +- regulator-always-on; +- }; +- +- vpll_reg: regulator@7 { +- regulator-always-on; +- }; +- +- vdac_reg: regulator@8 { +- regulator-always-on; +- }; +- +- vaux1_reg: regulator@9 { +- regulator-always-on; +- }; +- +- vaux2_reg: regulator@10 { +- regulator-always-on; +- }; +- +- vaux33_reg: regulator@11 { +- regulator-always-on; +- }; +- +- vmmc_reg: regulator@12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +-}; +- +-&mac_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&cpsw_default>; +- pinctrl-1 = <&cpsw_sleep>; +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&davinci_mdio_default>; +- pinctrl-1 = <&davinci_mdio_sleep>; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "rgmii-id"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- phy-handle = <ðphy1>; +- phy-mode = "rgmii-id"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&mmc1 { +- status = "okay"; +- vmmc-supply = <&vmmc_reg>; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +-}; +- +-&sham { +- status = "okay"; +-}; +- +-&aes { +- status = "okay"; +-}; +- +-&gpio0_target { +- ti,no-reset-on-init; +-}; +- +-&mmc2 { +- status = "okay"; +- vmmc-supply = <&wl12xx_vmmc>; +- non-removable; +- bus-width = <4>; +- cap-power-off-card; +- keep-power-in-suspend; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1271"; +- reg = <2>; +- interrupt-parent = <&gpio0>; +- interrupts = <31 IRQ_TYPE_EDGE_RISING>; /* gpio 31 */ +- ref-clock-frequency = <38400000>; +- }; +-}; +- +-&mcasp1 { +- #sound-dai-cells = <0>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mcasp1_pins>; +- pinctrl-1 = <&mcasp1_pins_sleep>; +- +- status = "okay"; +- +- op-mode = <0>; /* MCASP_IIS_MODE */ +- tdm-slots = <2>; +- /* 4 serializers */ +- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ +- 0 0 1 2 +- >; +- tx-num-evt = <32>; +- rx-num-evt = <32>; +-}; +- +-&tscadc { +- status = "okay"; +- tsc { +- ti,wires = <4>; +- ti,x-plate-resistance = <200>; +- ti,coordinate-readouts = <5>; +- ti,wire-config = <0x00 0x11 0x22 0x33>; +- }; +-}; +- +-&lcdc { +- status = "okay"; +- +- blue-and-red-wiring = "crossed"; +- +- port { +- lcdc_0: endpoint@0 { +- remote-endpoint = <&panel_0>; +- }; +- }; +-}; +- +-&rtc { +- clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; +- clock-names = "ext-clk", "int-clk"; +-}; +- +-&pruss_tm { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-guardian.dts b/scripts/dtc/include-prefixes/arm/am335x-guardian.dts +deleted file mode 100644 +index 1918766c1f80..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-guardian.dts ++++ /dev/null +@@ -1,490 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- * Copyright (C) 2018 Robert Bosch Power Tools GmbH +- */ +-/dts-v1/; +- +-#include "am33xx.dtsi" +-#include +-#include +- +-/ { +- model = "Bosch AM335x Guardian"; +- compatible = "bosch,am335x-guardian", "ti,am33xx"; +- +- chosen { +- stdout-path = &uart0; +- tick-timer = &timer2; +- }; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&dcdc2_reg>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_pins>; +- +- button21 { +- label = "guardian-power-button"; +- linux,code = ; +- gpios = <&gpio2 21 0>; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&leds_pins>; +- +- led1 { +- label = "green:heartbeat"; +- gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- +- led2 { +- label = "green:mmc0"; +- gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- }; +- +- panel { +- compatible = "ti,tilcdc,panel"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&lcd_pins_default &lcd_disen_pins>; +- pinctrl-1 = <&lcd_pins_sleep>; +- +- display-timings { +- 320x240 { +- hactive = <320>; +- vactive = <240>; +- hback-porch = <68>; +- hfront-porch = <20>; +- hsync-len = <1>; +- vback-porch = <18>; +- vfront-porch = <4>; +- vsync-len = <1>; +- clock-frequency = <9000000>; +- hsync-active = <0>; +- vsync-active = <0>; +- }; +- }; +- panel-info { +- ac-bias = <255>; +- ac-bias-intrpt = <0>; +- dma-burst-sz = <16>; +- bpp = <24>; +- bus-width = <16>; +- fdd = <0x80>; +- sync-edge = <0>; +- sync-ctrl = <1>; +- raster-order = <0>; +- fifo-th = <0>; +- }; +- +- }; +- +- pwm7: dmtimer-pwm { +- compatible = "ti,omap-dmtimer-pwm"; +- ti,timers = <&timer7>; +- pinctrl-names = "default"; +- pinctrl-0 = <&dmtimer7_pins>; +- ti,clock-source = <0x01>; +- }; +- +- vmmcsd_fixed: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsd_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&elm { +- status = "okay"; +-}; +- +-&gpmc { +- pinctrl-names = "default"; +- pinctrl-0 = <&nandflash_pins>; +- ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ +- status = "okay"; +- +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ +- ti,nand-ecc-opt = "bch16"; +- ti,elm-id = <&elm>; +- nand-bus-width = <8>; +- gpmc,device-width = <1>; +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-on-ns = <0>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- +- /* +- * MTD partition table +- * +- * All SPL-* partitions are sized to minimal length which can +- * be independently programmable. For NAND flash this is equal +- * to size of erase-block. +- */ +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "SPL"; +- reg = <0x0 0x40000>; +- }; +- +- partition@1 { +- label = "SPL.backup1"; +- reg = <0x40000 0x40000>; +- }; +- +- partition@2 { +- label = "SPL.backup2"; +- reg = <0x80000 0x40000>; +- }; +- +- partition@3 { +- label = "SPL.backup3"; +- reg = <0xc0000 0x40000>; +- }; +- +- partition@4 { +- label = "u-boot"; +- reg = <0x100000 0x100000>; +- }; +- +- partition@5 { +- label = "u-boot.backup1"; +- reg = <0x200000 0x100000>; +- }; +- +- partition@6 { +- label = "u-boot-env"; +- reg = <0x300000 0x40000>; +- }; +- +- partition@7 { +- label = "u-boot-env.backup1"; +- reg = <0x340000 0x40000>; +- }; +- +- partition@8 { +- label = "UBI"; +- reg = <0x380000 0x1fc80000>; +- }; +- }; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- clock-frequency = <400000>; +- status = "okay"; +- +- tps: tps@24 { +- reg = <0x24>; +- }; +-}; +- +-&lcdc { +- blue-and-red-wiring = "crossed"; +- status = "okay"; +-}; +- +-&mmc1 { +- bus-width = <0x4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +- vmmc-supply = <&vmmcsd_fixed>; +- status = "okay"; +-}; +- +-&rtc { +- clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; +- clock-names = "ext-clk", "int-clk"; +- system-power-controller; +-}; +- +-&spi0 { +- ti,pindir-d0-out-d1-in; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins>; +- status = "okay"; +-}; +- +-#include "tps65217.dtsi" +- +-&tps { +- ti,pmic-shutdown-controller; +- interrupt-parent = <&intc>; +- interrupts = <7>; /* NMI */ +- +- backlight { +- isel = <1>; /* 1 - ISET1, 2 ISET2 */ +- fdim = <100>; /* TPS65217_BL_FDIM_100HZ */ +- default-brightness = <100>; +- }; +- +- regulators { +- dcdc1_reg: regulator@0 { +- regulator-name = "vdds_dpr"; +- regulator-always-on; +- }; +- +- dcdc2_reg: regulator@1 { +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <1351500>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc3_reg: regulator@2 { +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <1150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1_reg: regulator@3 { +- regulator-name = "vio,vrtc,vdds"; +- regulator-always-on; +- }; +- +- ldo2_reg: regulator@4 { +- regulator-name = "vdd_3v3aux"; +- regulator-always-on; +- }; +- +- ldo3_reg: regulator@5 { +- regulator-name = "vdd_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo4_reg: regulator@6 { +- regulator-name = "vdd_3v3a"; +- regulator-always-on; +- }; +- }; +-}; +- +-&tscadc { +- status = "okay"; +- +- adc { +- ti,adc-channels = <0 1 2 3 4 5 6>; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +-&usb0 { +- dr_mode = "peripheral"; +-}; +- +-&usb1 { +- dr_mode = "host"; +-}; +- +-&am33xx_pinmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&clkout2_pin &gpio_pins>; +- +- clkout2_pin: pinmux_clkout2_pin { +- pinctrl-single,pins = < +- AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) +- >; +- }; +- +- dmtimer7_pins: pinmux_dmtimer7_pins { +- pinctrl-single,pins = < +- AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) +- >; +- }; +- +- gpio_keys_pins: pinmux_gpio_keys_pins { +- pinctrl-single,pins = < +- AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) +- >; +- }; +- +- gpio_pins: pinmux_gpio_pins { +- pinctrl-single,pins = < +- AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7) +- AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7) +- >; +- }; +- +- i2c0_pins: pinmux_i2c0_pins { +- pinctrl-single,pins = < +- AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) +- AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) +- >; +- }; +- +- lcd_disen_pins: pinmux_lcd_disen_pins { +- pinctrl-single,pins = < +- AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7) +- >; +- }; +- +- lcd_pins_default: pinmux_lcd_pins_default { +- pinctrl-single,pins = < +- AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) +- AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) +- AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) +- AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) +- AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) +- AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) +- AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) +- AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) +- AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) +- >; +- }; +- +- lcd_pins_sleep: pinmux_lcd_pins_sleep { +- pinctrl-single,pins = < +- AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) +- AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) +- AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) +- AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) +- AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) +- AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) +- AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) +- AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) +- AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) +- AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) +- AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) +- AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) +- AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) +- AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) +- AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) +- AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) +- AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) +- AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) +- AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) +- AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) +- >; +- }; +- +- leds_pins: pinmux_leds_pins { +- pinctrl-single,pins = < +- AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) +- AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7) +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) +- AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) +- AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) +- AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) +- AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) +- AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) +- AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) +- >; +- }; +- +- spi0_pins: pinmux_spi0_pins { +- pinctrl-single,pins = < +- AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0) +- AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) +- AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0) +- >; +- }; +- +- uart0_pins: pinmux_uart0_pins { +- pinctrl-single,pins = < +- AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) +- AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) +- >; +- }; +- +- nandflash_pins: pinmux_nandflash_pins { +- pinctrl-single,pins = < +- AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0) +- AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0) +- AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0) +- AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) +- AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0) +- AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0) +- AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0) +- AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) +- AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0) +- AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0) +- AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) +- AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) +- AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) +- AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) +- AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-icev2.dts b/scripts/dtc/include-prefixes/arm/am335x-icev2.dts +deleted file mode 100644 +index e5ce89c8f54d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-icev2.dts ++++ /dev/null +@@ -1,514 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/* +- * AM335x ICE V2 board +- * http://www.ti.com/tool/tmdsice3359 +- */ +- +-/dts-v1/; +- +-#include "am33xx.dtsi" +- +-/ { +- model = "TI AM3359 ICE-V2"; +- compatible = "ti,am3359-icev2", "ti,am33xx"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +- +- chosen { +- stdout-path = &uart3; +- }; +- +- vbat: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vbat"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- }; +- +- vtt_fixed: fixedregulator1 { +- compatible = "regulator-fixed"; +- regulator-name = "vtt"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- }; +- +- leds-iio { +- status = "disabled"; +- compatible = "gpio-leds"; +- led-out0 { +- label = "out0"; +- gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out1 { +- label = "out1"; +- gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out2 { +- label = "out2"; +- gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out3 { +- label = "out3"; +- gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out4 { +- label = "out4"; +- gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out5 { +- label = "out5"; +- gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out6 { +- label = "out6"; +- gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out7 { +- label = "out7"; +- gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- /* Tricolor status LEDs */ +- leds1 { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&user_leds>; +- +- led0 { +- label = "status0:red:cpu0"; +- gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "cpu0"; +- }; +- +- led1 { +- label = "status0:green:usr"; +- gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led2 { +- label = "status0:yellow:usr"; +- gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led3 { +- label = "status1:red:mmc0"; +- gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "mmc0"; +- }; +- +- led4 { +- label = "status1:green:usr"; +- gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led5 { +- label = "status1:yellow:usr"; +- gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- gpio-decoder { +- compatible = "gpio-decoder"; +- gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>, +- <&pca9536 2 GPIO_ACTIVE_HIGH>, +- <&pca9536 1 GPIO_ACTIVE_HIGH>, +- <&pca9536 0 GPIO_ACTIVE_HIGH>; +- linux,axis = <0>; /* ABS_X */ +- decoder-max-value = <9>; +- }; +-}; +- +-&am33xx_pinmux { +- user_leds: user_leds { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */ +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */ +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */ +- >; +- }; +- +- mmc0_pins_default: mmc0_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- i2c0_pins_default: i2c0_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) +- >; +- }; +- +- spi0_pins_default: spi0_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */ +- >; +- }; +- +- uart3_pins_default: uart3_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ +- >; +- }; +- +- cpsw_default: cpsw_default { +- pinctrl-single,pins = < +- /* Slave 1, RMII mode */ +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txen.rmii1_txen */ +- /* Slave 2, RMII mode */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_wait0.rmii2_crs_dv */ +- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_col.rmii2_refclk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a11.rmii2_rxd0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a10.rmii2_rxd1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_wpn.rmii2_rxerr */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a5.rmii2_txd0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a4.rmii2_txd1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a0.rmii2_txen */ +- >; +- }; +- +- cpsw_sleep: cpsw_sleep { +- pinctrl-single,pins = < +- /* Slave 1 reset value */ +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- +- /* Slave 2 reset value */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- davinci_mdio_default: davinci_mdio_default { +- pinctrl-single,pins = < +- /* MDIO */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- davinci_mdio_sleep: davinci_mdio_sleep { +- pinctrl-single,pins = < +- /* MDIO reset value */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_default>; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- tps: power-controller@2d { +- reg = <0x2d>; +- }; +- +- tpic2810: gpio@60 { +- compatible = "ti,tpic2810"; +- reg = <0x60>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- pca9536: gpio@41 { +- compatible = "ti,pca9536"; +- reg = <0x41>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- /* osd9616p0899-10 */ +- display@3c { +- compatible = "solomon,ssd1306fb-i2c"; +- reg = <0x3c>; +- solomon,height = <16>; +- solomon,width = <96>; +- solomon,com-seq; +- solomon,com-invdir; +- solomon,page-offset = <0>; +- solomon,prechargep1 = <2>; +- solomon,prechargep2 = <13>; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins_default>; +- +- sn65hvs882@1 { +- compatible = "pisosr-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- +- load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; +- +- reg = <1>; +- spi-max-frequency = <1000000>; +- spi-cpol; +- }; +- +- spi_nor: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "winbond,w25q64", "jedec,spi-nor"; +- spi-max-frequency = <80000000>; +- m25p,fast-read; +- reg = <0>; +- +- partition@0 { +- label = "u-boot-spl"; +- reg = <0x0 0x80000>; +- read-only; +- }; +- +- partition@1 { +- label = "u-boot"; +- reg = <0x80000 0x100000>; +- read-only; +- }; +- +- partition@2 { +- label = "u-boot-env"; +- reg = <0x180000 0x20000>; +- read-only; +- }; +- +- partition@3 { +- label = "misc"; +- reg = <0x1A0000 0x660000>; +- }; +- }; +- +-}; +- +-&tscadc { +- status = "okay"; +- adc { +- ti,adc-channels = <1 2 3 4 5 6 7>; +- }; +-}; +- +-#include "tps65910.dtsi" +- +-&tps { +- vcc1-supply = <&vbat>; +- vcc2-supply = <&vbat>; +- vcc3-supply = <&vbat>; +- vcc4-supply = <&vbat>; +- vcc5-supply = <&vbat>; +- vcc6-supply = <&vbat>; +- vcc7-supply = <&vbat>; +- vccio-supply = <&vbat>; +- +- regulators { +- vrtc_reg: regulator@0 { +- regulator-always-on; +- }; +- +- vio_reg: regulator@1 { +- regulator-always-on; +- }; +- +- vdd1_reg: regulator@2 { +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <912500>; +- regulator-max-microvolt = <1326000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd2_reg: regulator@3 { +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <912500>; +- regulator-max-microvolt = <1144000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd3_reg: regulator@4 { +- regulator-always-on; +- }; +- +- vdig1_reg: regulator@5 { +- regulator-always-on; +- }; +- +- vdig2_reg: regulator@6 { +- regulator-always-on; +- }; +- +- vpll_reg: regulator@7 { +- regulator-always-on; +- }; +- +- vdac_reg: regulator@8 { +- regulator-always-on; +- }; +- +- vaux1_reg: regulator@9 { +- regulator-always-on; +- }; +- +- vaux2_reg: regulator@10 { +- regulator-always-on; +- }; +- +- vaux33_reg: regulator@11 { +- regulator-always-on; +- }; +- +- vmmc_reg: regulator@12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +-}; +- +-&mmc1 { +- status = "okay"; +- vmmc-supply = <&vmmc_reg>; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins_default>; +-}; +- +-&gpio0_target { +- /* Do not idle the GPIO used for holding the VTT regulator */ +- ti,no-reset-on-init; +- ti,no-idle-on-init; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins_default>; +- status = "okay"; +-}; +- +-&gpio3 { +- pr1-mii-ctl-hog { +- gpio-hog; +- gpios = <4 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "PR1_MII_CTRL"; +- }; +- +- mux-mii-hog { +- gpio-hog; +- gpios = <10 GPIO_ACTIVE_HIGH>; +- /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */ +- output-high; +- line-name = "MUX_MII_CTL1"; +- }; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "rmii"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- phy-handle = <ðphy1>; +- phy-mode = "rmii"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&mac_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&cpsw_default>; +- pinctrl-1 = <&cpsw_sleep>; +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&davinci_mdio_default>; +- pinctrl-1 = <&davinci_mdio_sleep>; +- reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; +- reset-delay-us = <2>; /* PHY datasheet states 1uS min */ +- +- ethphy0: ethernet-phy@1 { +- reg = <1>; +- }; +- +- ethphy1: ethernet-phy@3 { +- reg = <3>; +- }; +-}; +- +-&pruss_tm { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-igep0033.dtsi b/scripts/dtc/include-prefixes/arm/am335x-igep0033.dtsi +deleted file mode 100644 +index cc14415a4eb9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-igep0033.dtsi ++++ /dev/null +@@ -1,300 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x +- * +- * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz +- */ +- +-/dts-v1/; +- +-#include "am33xx.dtsi" +-#include +- +-/ { +- cpus { +- cpu@0 { +- cpu0-supply = <&vdd1_reg>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +- +- leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&leds_pins>; +- +- compatible = "gpio-leds"; +- +- led0 { +- label = "com:green:user"; +- gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- vbat: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vbat"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- }; +- +- vmmc: fixedregulator1 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&am33xx_pinmux { +- i2c0_pins: pinmux_i2c0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- nandflash_pins: pinmux_nandflash_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) +- >; +- }; +- +- uart0_pins: pinmux_uart0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- leds_pins: pinmux_leds_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ +- >; +- }; +-}; +- +-&mac_sw { +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "rmii"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- phy-handle = <ðphy1>; +- phy-mode = "rmii"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&elm { +- status = "okay"; +-}; +- +-&gpmc { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&nandflash_pins>; +- +- ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ +- +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ +- nand-bus-width = <8>; +- ti,nand-ecc-opt = "bch8"; +- gpmc,device-width = <1>; +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-on-ns = <0>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ti,elm-id = <&elm>; +- +- /* MTD partition table */ +- partition@0 { +- label = "SPL"; +- reg = <0x00000000 0x000080000>; +- }; +- +- partition@1 { +- label = "U-boot"; +- reg = <0x00080000 0x001e0000>; +- }; +- +- partition@2 { +- label = "U-Boot Env"; +- reg = <0x00260000 0x00020000>; +- }; +- +- partition@3 { +- label = "Kernel"; +- reg = <0x00280000 0x00500000>; +- }; +- +- partition@4 { +- label = "File System"; +- reg = <0x00780000 0x007880000>; +- }; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- +- clock-frequency = <400000>; +- +- tps: tps@2d { +- reg = <0x2d>; +- }; +-}; +- +-&mmc1 { +- status = "okay"; +- vmmc-supply = <&vmmc>; +- bus-width = <4>; +-}; +- +-&uart0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +-}; +- +-&usb1 { +- dr_mode = "host"; +-}; +- +-#include "tps65910.dtsi" +- +-&tps { +- vcc1-supply = <&vbat>; +- vcc2-supply = <&vbat>; +- vcc3-supply = <&vbat>; +- vcc4-supply = <&vbat>; +- vcc5-supply = <&vbat>; +- vcc6-supply = <&vbat>; +- vcc7-supply = <&vbat>; +- vccio-supply = <&vbat>; +- +- regulators { +- vrtc_reg: regulator@0 { +- regulator-always-on; +- }; +- +- vio_reg: regulator@1 { +- regulator-always-on; +- }; +- +- vdd1_reg: regulator@2 { +- /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <912500>; +- regulator-max-microvolt = <1312500>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd2_reg: regulator@3 { +- /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <912500>; +- regulator-max-microvolt = <1150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd3_reg: regulator@4 { +- regulator-always-on; +- }; +- +- vdig1_reg: regulator@5 { +- regulator-always-on; +- }; +- +- vdig2_reg: regulator@6 { +- regulator-always-on; +- }; +- +- vpll_reg: regulator@7 { +- regulator-always-on; +- }; +- +- vdac_reg: regulator@8 { +- regulator-always-on; +- }; +- +- vaux1_reg: regulator@9 { +- regulator-always-on; +- }; +- +- vaux2_reg: regulator@10 { +- regulator-always-on; +- }; +- +- vaux33_reg: regulator@11 { +- regulator-always-on; +- }; +- +- vmmc_reg: regulator@12 { +- regulator-always-on; +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/am335x-lxm.dts b/scripts/dtc/include-prefixes/arm/am335x-lxm.dts +deleted file mode 100644 +index 1282dae144dd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-lxm.dts ++++ /dev/null +@@ -1,347 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 NovaTech LLC - https://www.novatechweb.com +- */ +-/dts-v1/; +- +-#include "am33xx.dtsi" +- +-/ { +- model = "NovaTech OrionLXm"; +- compatible = "novatech,am335x-lxm", "ti,am33xx"; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&vdd1_reg>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512 MB */ +- }; +- +- /* Power supply provides a fixed 5V @2A */ +- vbat: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vbat"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- }; +- +- /* Power supply provides a fixed 3.3V @3A */ +- vmmcsd_fixed: fixedregulator1 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsd_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +-}; +- +-&am33xx_pinmux { +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- i2c0_pins: pinmux_i2c0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) +- >; +- }; +- +- cpsw_default: cpsw_default { +- pinctrl-single,pins = < +- /* Slave 1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */ +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_crs_dv */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rxer */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_txen */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td0 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd0 */ +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) +- +- /* Slave 2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */ +- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */ +- >; +- }; +- +- cpsw_sleep: cpsw_sleep { +- pinctrl-single,pins = < +- /* Slave 1 reset value */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */ +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_crs_dv */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rxer */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_txen */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td0 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd0 */ +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk */ +- +- /* Slave 2 reset value*/ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_txen */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_crs_dv */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rxer */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */ +- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_refclk */ +- >; +- }; +- +- davinci_mdio_default: davinci_mdio_default { +- pinctrl-single,pins = < +- /* MDIO */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- davinci_mdio_sleep: davinci_mdio_sleep { +- pinctrl-single,pins = < +- /* MDIO reset value */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- emmc_pins: pinmux_emmc_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ +- >; +- }; +- +- uart0_pins: pinmux_uart0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- serial_config1: serial_config1@20 { +- compatible = "nxp,pca9539"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- serial_config2: serial_config2@21 { +- compatible = "nxp,pca9539"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- tps: tps@2d { +- compatible = "ti,tps65910"; +- reg = <0x2d>; +- }; +-}; +- +-/include/ "tps65910.dtsi" +- +-&tps { +- vcc1-supply = <&vbat>; +- vcc2-supply = <&vbat>; +- vcc3-supply = <&vbat>; +- vcc4-supply = <&vbat>; +- vcc5-supply = <&vbat>; +- vcc6-supply = <&vbat>; +- vcc7-supply = <&vbat>; +- vccio-supply = <&vbat>; +- +- regulators { +- /* vrtc - unused */ +- +- vio_reg: regulator@1 { +- regulator-name = "vio_1v5,ddr"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd1_reg: regulator@2 { +- regulator-name = "vdd1,mpu"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd2_reg: regulator@3 { +- regulator-name = "vdd2_1v1,core"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdd3 - unused */ +- +- /* vdig1 - unused */ +- +- vdig2_reg: regulator@6 { +- regulator-name = "vdig2_1v8,vdds_pll"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vpll - unused */ +- +- vdac_reg: regulator@8 { +- regulator-name = "vdac_1v8,vdds"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vaux1_reg: regulator@9 { +- regulator-name = "vaux1_1v8,usb"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vaux2_reg: regulator@10 { +- regulator-name = "vaux2_3v3,io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vaux33_reg: regulator@11 { +- regulator-name = "vaux33_3v3,usb"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vmmc_reg: regulator@12 { +- regulator-name = "vmmc_3v3,io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +-}; +- +-&sham { +- status = "okay"; +-}; +- +-&aes { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- +- status = "okay"; +-}; +- +-&usb0 { +- dr_mode = "host"; +-}; +- +-&usb1 { +- dr_mode = "host"; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "rmii"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&cpsw_port2 { +- phy-handle = <ðphy1>; +- phy-mode = "rmii"; +- ti,dual-emac-pvid = <3>; +-}; +- +-&mac_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&cpsw_default>; +- pinctrl-1 = <&cpsw_sleep>; +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&davinci_mdio_default>; +- pinctrl-1 = <&davinci_mdio_sleep>; +- +- ethphy0: ethernet-phy@5 { +- reg = <5>; +- }; +- +- ethphy1: ethernet-phy@4 { +- reg = <4>; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <&vmmcsd_fixed>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_pins>; +- vmmc-supply = <&vmmcsd_fixed>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/am335x-moxa-uc-2100-common.dtsi b/scripts/dtc/include-prefixes/arm/am335x-moxa-uc-2100-common.dtsi +deleted file mode 100644 +index 11e8f64b6606..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-moxa-uc-2100-common.dtsi ++++ /dev/null +@@ -1,227 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2018 MOXA Inc. - https://www.moxa.com/ +- * +- * Authors: SZ Lin (林上智) +- * Wes Huang (黃淵河) +- * Fero JD Zhou (周俊達) +- */ +- +-#include "am33xx.dtsi" +- +-/ { +- vbat: vbat-regulator { +- compatible = "regulator-fixed"; +- }; +- +- /* Power supply provides a fixed 3.3V @3A */ +- vmmcsd_fixed: vmmcsd-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsd_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- +- buttons: push_button { +- compatible = "gpio-keys"; +- }; +-}; +- +-&am33xx_pinmux { +- pinctrl-names = "default"; +- +- i2c0_pins: pinmux_i2c0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- push_button_pins: pinmux_push_button { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_23 */ +- >; +- }; +- +- uart0_pins: pinmux_uart0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- davinci_mdio_default: davinci_mdio_default { +- pinctrl-single,pins = < +- /* MDIO */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- mmc1_pins_default: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- /* eMMC */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad12.mmc1_dat0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad13.mmc1_dat1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad14.mmc1_dat2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad15.mmc1_dat3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad8.mmc1_dat4 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad9.mmc1_dat5 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad10.mmc1_dat6 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad11.mmc1_dat7 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ +- >; +- }; +- +- spi0_pins: pinmux_spi0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +-}; +- +-&uart0 { +- /* Console */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c16"; +- pagesize = <16>; +- reg = <0x50>; +- }; +- +- rtc_wdt: rtc_wdt@68 { +- compatible = "dallas,ds1374"; +- reg = <0x68>; +- }; +-}; +- +-&usb0 { +- dr_mode = "host"; +-}; +- +-/* Power */ +-&vbat { +- regulator-name = "vbat"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +-}; +- +-&mac_sw { +- pinctrl-names = "default"; +- pinctrl-0 = <&cpsw_default>; +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default"; +- pinctrl-0 = <&davinci_mdio_default>; +- status = "okay"; +-}; +- +-&cpsw_port1 { +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- ti,dual-emac-pvid = <2>; +-}; +- +-&sham { +- status = "okay"; +-}; +- +-&aes { +- status = "okay"; +-}; +- +-&gpio0_target { +- ti,no-reset-on-init; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- vmmc-supply = <&vmmcsd_fixed>; +- bus-width = <8>; +- pinctrl-0 = <&mmc1_pins_default>; +- non-removable; +- status = "okay"; +-}; +- +-&buttons { +- pinctrl-names = "default"; +- pinctrl-0 = <&push_button_pins>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- button@0 { +- label = "push_button"; +- linux,code = <0x100>; +- gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-/* SPI Busses */ +-&spi0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins>; +- +- m25p80@0 { +- compatible = "mx25l6405d"; +- spi-max-frequency = <40000000>; +- +- reg = <0>; +- spi-cpol; +- spi-cpha; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* reg : The partition's offset and size within the mtd bank. */ +- partitions@0 { +- label = "MLO"; +- reg = <0x0 0x80000>; +- }; +- +- partitions@1 { +- label = "U-Boot"; +- reg = <0x80000 0x100000>; +- }; +- +- partitions@2 { +- label = "U-Boot Env"; +- reg = <0x180000 0x40000>; +- }; +- }; +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins>; +- +- tpm_spi_tis@0 { +- compatible = "tcg,tpm_tis-spi"; +- reg = <0>; +- spi-max-frequency = <500000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-moxa-uc-2101.dts b/scripts/dtc/include-prefixes/arm/am335x-moxa-uc-2101.dts +deleted file mode 100644 +index 1cc513ed92cc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-moxa-uc-2101.dts ++++ /dev/null +@@ -1,68 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2018 MOXA Inc. - https://www.moxa.com/ +- * +- * Authors: SZ Lin (林上智) +- * Wes Huang (黃淵河) +- * Fero JD Zhou (周俊達) +- */ +- +-/dts-v1/; +- +-#include "am335x-moxa-uc-2100-common.dtsi" +- +-/ { +- model = "Moxa UC-2101"; +- compatible = "moxa,uc-2101", "ti,am33xx"; +- +- leds { +- compatible = "gpio-leds"; +- led1 { +- label = "UC2100:GREEN:USER"; +- gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +-}; +- +-&am33xx_pinmux { +- pinctrl-names = "default"; +- +- cpsw_default: cpsw_default { +- pinctrl-single,pins = < +- /* Slave 1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txen.rmii1_txen */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- spi1_pins: pinmux_spi1 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* ecap0_in_pwm0_out.spi1_sclk */ +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart1_ctsn.spi1_cs0 */ +- AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart0_ctsn.spi1_d0 */ +- AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart0_rtsn.spi1_d1 */ +- >; +- }; +-}; +- +-&davinci_mdio_sw { +- phy0: ethernet-phy@4 { +- reg = <4>; +- }; +-}; +- +-&cpsw_port1 { +- phy-handle = <&phy0>; +- phy-mode = "rmii"; +-}; +- +-&cpsw_port2 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-moxa-uc-8100-common.dtsi b/scripts/dtc/include-prefixes/arm/am335x-moxa-uc-8100-common.dtsi +deleted file mode 100644 +index a7269b90d795..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-moxa-uc-8100-common.dtsi ++++ /dev/null +@@ -1,423 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2020 MOXA Inc. - https://www.moxa.com/ +- * +- * Author: Johnson Chen +- */ +- +-#include "am33xx.dtsi" +- +-/ { +- +- cpus { +- cpu@0 { +- cpu0-supply = <&vdd1_reg>; +- }; +- }; +- +- vbat: vbat-regulator { +- compatible = "regulator-fixed"; +- }; +- +- /* Power supply provides a fixed 3.3V @3A */ +- vmmcsd_fixed: vmmcsd-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsd_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- +- buttons: push_button { +- compatible = "gpio-keys"; +- }; +- +-}; +- +-&am33xx_pinmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&minipcie_pins>; +- +- minipcie_pins: pinmux_minipcie { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2_24 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/ +- >; +- }; +- +- push_button_pins: pinmux_push_button { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */ +- >; +- }; +- +- i2c0_pins: pinmux_i2c0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_ctsn.i2c1_sda */ +- AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_rtsn.i2c1_scl */ +- >; +- }; +- +- uart0_pins: pinmux_uart0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- uart1_pins: pinmux_uart1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) +- >; +- }; +- +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE6) /* lcd_data14.uart5_ctsn */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* lcd_data15.uart5_rtsn */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* lcd_data9.uart5_rxd */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE4) /* lcd_data8.uart5_txd */ +- >; +- }; +- +- cpsw_default: cpsw_default { +- pinctrl-single,pins = < +- /* Slave 1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) +- +- /* Slave 2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */ +- +- >; +- }; +- +- davinci_mdio_default: davinci_mdio_default { +- pinctrl-single,pins = < +- /* MDIO */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- mmc0_pins_default: pinmux_mmc0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */ +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */ +- >; +- }; +- +- mmc2_pins_default: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- /* eMMC */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */ +- >; +- }; +- +- spi0_pins: pinmux_spi0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +-}; +- +-&uart0 { +- /* Console */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +-}; +- +-&uart1 { +- /* UART 1 setting */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +-}; +- +-&uart5 { +- /* UART 2 setting */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- tps: tps@2d { +- compatible = "ti,tps65910"; +- reg = <0x2d>; +- }; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c16"; +- pagesize = <16>; +- reg = <0x50>; +- }; +- +- rtc_wdt: rtc_wdt@68 { +- compatible = "dallas,ds1374"; +- reg = <0x68>; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- +- status = "okay"; +- clock-frequency = <400000>; +- gpio_xten: gpio_xten@27 { +- compatible = "nxp,pca9535"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x27>; +- }; +-}; +- +-&usb0 { +- dr_mode = "host"; +-}; +- +-&usb1 { +- dr_mode = "host"; +-}; +- +- +-#include "tps65910.dtsi" +-&tps { +- vcc1-supply = <&vbat>; +- vcc2-supply = <&vbat>; +- vcc3-supply = <&vbat>; +- vcc4-supply = <&vbat>; +- vcc5-supply = <&vbat>; +- vcc6-supply = <&vbat>; +- vcc7-supply = <&vbat>; +- vccio-supply = <&vbat>; +- +- regulators { +- vrtc_reg: regulator@0 { +- regulator-always-on; +- }; +- +- vio_reg: regulator@1 { +- regulator-always-on; +- }; +- +- vdd1_reg: regulator@2 { +- regulator-always-on; +- }; +- +- vdd2_reg: regulator@3 { +- regulator-always-on; +- }; +- +- vdd3_reg: regulator@4 { +- regulator-always-on; +- }; +- +- vdig1_reg: regulator@5 { +- regulator-always-on; +- }; +- +- vdig2_reg: regulator@6 { +- regulator-always-on; +- }; +- +- vpll_reg: regulator@7 { +- regulator-always-on; +- }; +- +- vdac_reg: regulator@8 { +- regulator-always-on; +- }; +- +- vaux1_reg: regulator@9 { +- regulator-always-on; +- }; +- +- vaux2_reg: regulator@10 { +- regulator-always-on; +- }; +- +- vaux33_reg: regulator@11 { +- regulator-always-on; +- }; +- +- vmmc_reg: regulator@12 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmc_reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +-}; +- +-/* Power */ +-&vbat { +- regulator-name = "vbat"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +-}; +- +-&mac_sw { +- pinctrl-names = "default"; +- pinctrl-0 = <&cpsw_default>; +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default"; +- pinctrl-0 = <&davinci_mdio_default>; +- +- ethphy0: ethernet-phy@4 { +- reg = <4>; +- }; +- +- ethphy1: ethernet-phy@5 { +- reg = <5>; +- }; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "rmii"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- phy-handle = <ðphy1>; +- phy-mode = "rmii"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&sham { +- status = "okay"; +-}; +- +-&aes { +- status = "okay"; +-}; +- +-&gpio0_target { +- ti,no-reset-on-init; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- vmmc-supply = <&vmmcsd_fixed>; +- bus-width = <4>; +- pinctrl-0 = <&mmc0_pins_default>; +- cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; +- wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&mmc3 { +- dmas = <&edma_xbar 12 0 1 +- &edma_xbar 13 0 2>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- vmmc-supply = <&vmmcsd_fixed>; +- bus-width = <8>; +- pinctrl-0 = <&mmc2_pins_default>; +- ti,non-removable; +- status = "okay"; +-}; +- +-&buttons { +- pinctrl-names = "default"; +- pinctrl-0 = <&push_button_pins>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- button@0 { +- label = "push_button"; +- linux,code = <0x100>; +- gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-/* SPI Busses */ +-&spi0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins>; +- +- m25p80@0 { +- compatible = "mx25l6405d"; +- spi-max-frequency = <40000000>; +- +- reg = <0>; +- spi-cpol; +- spi-cpha; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* reg : The partition's offset and size within the mtd bank. */ +- partitions@0 { +- label = "MLO"; +- reg = <0x0 0x80000>; +- }; +- +- partitions@1 { +- label = "U-Boot"; +- reg = <0x80000 0x100000>; +- }; +- +- partitions@2 { +- label = "U-Boot Env"; +- reg = <0x180000 0x20000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-moxa-uc-8100-me-t.dts b/scripts/dtc/include-prefixes/arm/am335x-moxa-uc-8100-me-t.dts +deleted file mode 100644 +index 0c7949d21bd9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-moxa-uc-8100-me-t.dts ++++ /dev/null +@@ -1,101 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2017 MOXA Inc. - https://www.moxa.com/ +- * +- * Author: SZ Lin (林上智) +- */ +-/dts-v1/; +- +-#include "am335x-moxa-uc-8100-common.dtsi" +- +-/ { +- model = "Moxa UC-8100-ME-T"; +- compatible = "moxa,uc-8100-me-t", "ti,am33xx"; +- +- memory { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512 MB */ +- }; +- +- leds { +- compatible = "gpio-leds"; +- led1 { +- label = "uc8100me:CEL1"; +- gpios = <&gpio_xten 8 0>; +- default-state = "off"; +- }; +- +- led2 { +- label = "uc8100me:CEL2"; +- gpios = <&gpio_xten 9 0>; +- default-state = "off"; +- }; +- +- led3 { +- label = "uc8100me:CEL3"; +- gpios = <&gpio_xten 10 0>; +- default-state = "off"; +- }; +- +- led4 { +- label = "uc8100me:DIA1"; +- gpios = <&gpio_xten 11 0>; +- default-state = "off"; +- }; +- led5 { +- label = "uc8100me:DIA2"; +- gpios = <&gpio_xten 12 0>; +- default-state = "off"; +- }; +- led6 { +- label = "uc8100me:DIA3"; +- gpios = <&gpio_xten 13 0>; +- default-state = "off"; +- }; +- led7 { +- label = "uc8100me:SD"; +- gpios = <&gpio_xten 14 0>; +- default-state = "off"; +- }; +- led8 { +- label = "uc8100me:USB"; +- gpios = <&gpio_xten 15 0>; +- default-state = "off"; +- }; +- led9 { +- label = "uc8100me:USER"; +- gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +-}; +- +-&i2c0 { +- tpm: tpm@20 { +- compatible = "infineon,slb9645tt"; +- reg = <0x20>; +- }; +-}; +- +-&tps { +- regulators { +- vdd1_reg: regulator@2 { +- /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <912500>; +- regulator-max-microvolt = <1378000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd2_reg: regulator@3 { +- /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <912500>; +- regulator-max-microvolt = <1150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/am335x-myirtech-myc.dtsi b/scripts/dtc/include-prefixes/arm/am335x-myirtech-myc.dtsi +deleted file mode 100644 +index 245c35f41cdf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-myirtech-myc.dtsi ++++ /dev/null +@@ -1,270 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* SPDX-FileCopyrightText: Alexander Shiyan, */ +- +-/* Based on code by myc_c335x.dts, MYiRtech.com */ +-/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ +- +-/dts-v1/; +- +-#include "am33xx.dtsi" +- +-#include +-#include +- +-/ { +- model = "MYIR MYC-AM335X"; +- compatible = "myir,myc-am335x", "ti,am33xx"; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&vdd_core>; +- voltage-tolerance = <2>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; +- }; +- +- vdd_mod: vdd_mod_reg { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-mod"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_core: vdd_core_reg { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-core"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_mod>; +- }; +- +- leds: leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_mod_pins>; +- +- led_mod: led_mod { +- label = "module:user"; +- gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; +- color = ; +- default-state = "off"; +- panic-indicator; +- }; +- }; +-}; +- +-&mac_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <ð_slave1_pins_default>; +- pinctrl-1 = <ð_slave1_pins_sleep>; +- status = "okay"; +-}; +- +-&cpsw_port1 { +- phy-handle = <&phy0>; +- phy-mode = "rgmii-id"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- status = "disabled"; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mdio_pins_default>; +- pinctrl-1 = <&mdio_pins_sleep>; +- +- phy0: ethernet-phy@4 { +- reg = <4>; +- }; +-}; +- +-&elm { +- status = "okay"; +-}; +- +-&gpmc { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&nand_pins_default>; +- pinctrl-1 = <&nand_pins_sleep>; +- ranges = <0 0 0x8000000 0x1000000>; +- status = "okay"; +- +- nand0: nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE_NONE>; +- nand-bus-width = <8>; +- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; +- gpmc,device-width = <1>; +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-on-ns = <0>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- ti,elm-id = <&elm>; +- ti,nand-ecc-opt = "bch8"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&i2c0 { +- pinctrl-names = "default", "gpio", "sleep"; +- pinctrl-0 = <&i2c0_pins_default>; +- pinctrl-1 = <&i2c0_pins_gpio>; +- pinctrl-2 = <&i2c0_pins_sleep>; +- clock-frequency = <400000>; +- scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c32"; +- reg = <0x50>; +- pagesize = <32>; +- vcc-supply = <&vdd_mod>; +- }; +-}; +- +-&rtc { +- system-power-controller; +-}; +- +-&am33xx_pinmux { +- mdio_pins_default: pinmux_mdio_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data */ +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* mdio_clk */ +- >; +- }; +- +- mdio_pins_sleep: pinmux_mdio_pins_sleep { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- eth_slave1_pins_default: pinmux_eth_slave1_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_tctl */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rctl */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td3 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td2 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td0 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_tclk */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rclk */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd3 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd2 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd0 */ +- >; +- }; +- +- eth_slave1_pins_sleep: pinmux_eth_slave1_pins_sleep { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- i2c0_pins_default: pinmux_i2c0_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0) /* I2C0_SDA */ +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0) /* I2C0_SCL */ +- >; +- }; +- +- i2c0_pins_gpio: pinmux_i2c0_pins_gpio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE7) /* gpio3[5] */ +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE7) /* gpio3[6] */ +- >; +- }; +- +- i2c0_pins_sleep: pinmux_i2c0_pins_sleep { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- led_mod_pins: pinmux_led_mod_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpio3[18] */ +- >; +- }; +- +- nand_pins_default: pinmux_nand_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad4 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad5 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad6 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad7 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wait0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpio0[31] */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) /* gpmc_csn0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) /* gpmc_advn_ale */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) /* gpmc_oen_ren */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) /* gpmc_wen */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) /* gpmc_be0n_cle */ +- >; +- }; +- +- nand_pins_sleep: pinmux_nand_pins_sleep { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-myirtech-myd.dts b/scripts/dtc/include-prefixes/arm/am335x-myirtech-myd.dts +deleted file mode 100644 +index 1479fd95dec2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-myirtech-myd.dts ++++ /dev/null +@@ -1,538 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* SPDX-FileCopyrightText: Alexander Shiyan, */ +-/* Based on code by myd_c335x.dts, MYiRtech.com */ +-/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ +- +-/dts-v1/; +- +-#include "am335x-myirtech-myc.dtsi" +- +-#include +-#include +- +-/ { +- model = "MYIR MYD-AM335X"; +- compatible = "myir,myd-am335x", "myir,myc-am335x", "ti,am33xx"; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- clk12m: clk12m { +- compatible = "fixed-clock"; +- clock-frequency = <12000000>; +- +- #clock-cells = <0>; +- }; +- +- gpio_buttons: gpio_buttons { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_buttons_pins>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- button1: button@0 { +- reg = <0>; +- label = "button1"; +- linux,code = ; +- gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; +- }; +- +- button2: button@1 { +- reg = <1>; +- label = "button2"; +- linux,code = ; +- gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- sound: sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&master_codec>; +- simple-audio-card,frame-master = <&master_codec>; +- +- simple-audio-card,cpu { +- sound-dai = <&mcasp0>; +- }; +- +- master_codec: simple-audio-card,codec@1 { +- sound-dai = <&sgtl5000>; +- }; +- +- simple-audio-card,codec@2 { +- sound-dai = <&tda9988>; +- }; +- }; +- +- vdd_5v0: vdd_5v0_reg { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_3v3: vdd_3v3_reg { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_5v0>; +- }; +-}; +- +-&cpsw_port2 { +- status = "okay"; +- phy-handle = <&phy1>; +- phy-mode = "rgmii-id"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&davinci_mdio_sw { +- phy1: ethernet-phy@6 { +- reg = <6>; +- eee-broken-1000t; +- }; +-}; +- +-&mac_sw { +- pinctrl-0 = <ð_slave1_pins_default>, <ð_slave2_pins_default>; +- pinctrl-1 = <ð_slave1_pins_sleep>, <ð_slave2_pins_sleep>; +- slaves = <2>; +-}; +- +-&dcan0 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&dcan0_pins_default>; +- pinctrl-1 = <&dcan0_pins_sleep>; +- status = "okay"; +-}; +- +-&dcan1 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&dcan1_pins_default>; +- pinctrl-1 = <&dcan1_pins_sleep>; +- status = "okay"; +-}; +- +-&ehrpwm0 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&ehrpwm0_pins_default>; +- pinctrl-1 = <&ehrpwm0_pins_sleep>; +- status = "okay"; +-}; +- +-&epwmss0 { +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default", "gpio", "sleep"; +- pinctrl-0 = <&i2c1_pins_default>; +- pinctrl-1 = <&i2c1_pins_gpio>; +- pinctrl-2 = <&i2c1_pins_sleep>; +- clock-frequency = <400000>; +- scl-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio0 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +- +- sgtl5000: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- reg =<0xa>; +- clocks = <&clk12m>; +- micbias-resistor-k-ohms = <4>; +- micbias-voltage-m-volts = <2250>; +- VDDA-supply = <&vdd_3v3>; +- VDDIO-supply = <&vdd_3v3>; +- +- #sound-dai-cells = <0>; +- }; +- +- tda9988: tda9988@70 { +- compatible = "nxp,tda998x"; +- reg =<0x70>; +- audio-ports = ; +- +- #sound-dai-cells = <0>; +- +- ports { +- port@0 { +- hdmi_0: endpoint@0 { +- remote-endpoint = <&lcdc_0>; +- }; +- }; +- }; +- }; +-}; +- +-&lcdc { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&lcdc_pins_default>; +- pinctrl-1 = <&lcdc_pins_sleep>; +- blue-and-red-wiring = "straight"; +- status = "okay"; +- +- port { +- lcdc_0: endpoint@0 { +- remote-endpoint = <&hdmi_0>; +- }; +- }; +-}; +- +-&leds { +- pinctrl-0 = <&led_mod_pins &leds_pins>; +- +- led1: led1 { +- label = "base:user1"; +- gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; +- color = ; +- default-state = "off"; +- }; +- +- led2: led2 { +- label = "base:user2"; +- gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; +- color = ; +- default-state = "off"; +- }; +-}; +- +-&mcasp0 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mcasp0_pins_default>; +- pinctrl-1 = <&mcasp0_pins_sleep>; +- op-mode = <0>; +- tdm-slots = <2>; +- serial-dir = <0 1 2 0>; +- tx-num-evt = <32>; +- rx-num-evt = <32>; +- status = "okay"; +- +- #sound-dai-cells = <0>; +-}; +- +-&mmc1 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mmc1_pins_default>; +- pinctrl-1 = <&mmc1_pins_sleep>; +- cd-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- vmmc-supply = <&vdd_3v3>; +- status = "okay"; +-}; +- +-&nand0 { +- partition@0 { +- label = "MLO"; +- reg = <0x00000 0x20000>; +- }; +- +- partition@20000 { +- label = "boot"; +- reg = <0x20000 0x80000>; +- }; +-}; +- +-&tscadc { +- status = "okay"; +- +- adc: adc { +- ti,adc-channels = <0 1 2 3 4 5 6>; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&uart1_pins_default>; +- pinctrl-1 = <&uart1_pins_sleep>; +- linux,rs485-enabled-at-boot-time; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&uart2_pins_default>; +- pinctrl-1 = <&uart2_pins_sleep>; +- status = "okay"; +-}; +- +-&usb { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_pins>; +-}; +- +-&usb0 { +- dr_mode = "otg"; +-}; +- +-&usb0_phy { +- vcc-supply = <&vdd_5v0>; +-}; +- +-&usb1 { +- dr_mode = "host"; +-}; +- +-&usb1_phy { +- vcc-supply = <&vdd_5v0>; +-}; +- +-&vdd_mod { +- vin-supply = <&vdd_3v3>; +-}; +- +-&am33xx_pinmux { +- dcan0_pins_default: pinmux_dcan0_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* dcan0_tx_mux2 */ +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT, MUX_MODE2) /* dcan0_rx_mux2 */ +- >; +- }; +- +- dcan0_pins_sleep: pinmux_dcan0_pins_sleep { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- dcan1_pins_default: pinmux_dcan1_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* dcan1_tx_mux0 */ +- AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* dcan1_rx_mux0 */ +- >; +- }; +- +- dcan1_pins_sleep: pinmux_dcan1_pins_sleep { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- ehrpwm0_pins_default: pinmux_ehrpwm0_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_OUTPUT, MUX_MODE3) /* ehrpwm0A_mux1 */ +- >; +- }; +- +- ehrpwm0_pins_sleep: pinmux_ehrpwm0_pins_sleep { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- eth_slave2_pins_default: pinmux_eth_slave2_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_tctl */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rctl */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_tclk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rclk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rd3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rd2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2 /* rgmii2_rd1 */) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2 /* rgmii2_rd0 */) +- >; +- }; +- +- eth_slave2_pins_sleep: pinmux_eth_slave2_pins_sleep { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- gpio_buttons_pins: pinmux_gpio_buttons_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpio3[0] */ +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT, MUX_MODE7) /* gpio0[29] */ +- >; +- }; +- +- i2c1_pins_default: pinmux_i2c1_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE2) /* I2C1_SDA_mux3 */ +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE2) /* I2C1_SCL_mux3 */ +- >; +- }; +- +- i2c1_pins_gpio: pinmux_i2c1_pins_gpio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE7) /* gpio0[4] */ +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE7) /* gpio0[5] */ +- >; +- }; +- +- i2c1_pins_sleep: pinmux_i2c1_pins_sleep { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- lcdc_pins_default: pinmux_lcdc_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) /* lcd_data0 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) /* lcd_data1 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) /* lcd_data2 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) /* lcd_data3 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) /* lcd_data4 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) /* lcd_data5 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) /* lcd_data6 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) /* lcd_data7 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) /* lcd_data8 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) /* lcd_data9 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) /* lcd_data10 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) /* lcd_data11 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) /* lcd_data12 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) /* lcd_data13 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) /* lcd_data14 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) /* lcd_data15 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) /* lcd_vsync */ +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) /* lcd_hsync */ +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) /* lcd_pclk */ +- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) /* lcd_ac_bias_en */ +- >; +- }; +- +- lcdc_pins_sleep: pinmux_lcdc_pins_sleep { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- leds_pins: pinmux_leds_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* gpio0[27] */ +- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE7) /* gpio0[3] */ +- >; +- }; +- +- mcasp0_pins_default: pinmux_mcasp0_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_aclkx_mux0 */ +- AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_fsx_mux0 */ +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mcasp0_axr2_mux0 */ +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_axr1_mux0 */ +- >; +- }; +- +- mcasp0_pins_sleep: pinmux_mcasp0_pins_sleep { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- mmc1_pins_default: pinmux_mmc1_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat3 */ +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat2 */ +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat1 */ +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat0 */ +- AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_clk */ +- AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_cmd */ +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* gpio3[21] */ +- >; +- }; +- +- mmc1_pins_sleep: pinmux_mmc1_pins_sleep { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- uart0_pins: pinmux_uart0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) /* uart0_rxd */ +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* uart0_txd */ +- >; +- }; +- +- uart1_pins_default: pinmux_uart1_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) /* uart1_rxd */ +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* uart1_txd */ +- >; +- }; +- +- uart1_pins_sleep: pinmux_uart1_pins_sleep { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- uart2_pins_default: pinmux_uart2_pins_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE6) /* uart2_rxd_mux1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_OUTPUT, MUX_MODE6) /* uart2_txd_mux1 */ +- >; +- }; +- +- uart2_pins_sleep: pinmux_uart2_pins_sleep { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- usb_pins: pinmux_usb_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_USB0_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* USB0_DRVVBUS */ +- AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* USB1_DRVVBUS */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-nano.dts b/scripts/dtc/include-prefixes/arm/am335x-nano.dts +deleted file mode 100644 +index b6f2567bd65a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-nano.dts ++++ /dev/null +@@ -1,472 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/ +- */ +-/dts-v1/; +- +-#include "am33xx.dtsi" +- +-/ { +- model = "Newflow AM335x NanoBone"; +- compatible = "ti,am33xx"; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&dcdc2_reg>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led0 { +- label = "nanobone:green:usr1"; +- gpios = <&gpio1 5 0>; +- default-state = "off"; +- }; +- }; +-}; +- +-&am33xx_pinmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&misc_pins>; +- +- misc_pins: misc_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7) /* spi0_cs0.gpio0_5 */ +- >; +- }; +- +- gpmc_pins: gpmc_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE0) +- +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE0) +- +- AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) +- +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE1) /* lcd_data1.gpmc_a1 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE1) /* lcd_data2.gpmc_a2 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE1) /* lcd_data3.gpmc_a3 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE1) /* lcd_data4.gpmc_a4 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE1) /* lcd_data5.gpmc_a5 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE1) /* lcd_data6.gpmc_a6 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE1) /* lcd_data7.gpmc_a7 */ +- +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_vsync.gpmc_a8 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_hsync.gpmc_a9 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE1) /* lcd_pclk.gpmc_a10 */ +- >; +- }; +- +- i2c0_pins: i2c0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- uart0_pins: uart0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0) +- >; +- }; +- +- uart1_pins: uart1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) +- >; +- }; +- +- uart2_pins: uart2_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data8.gpio2[14] */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7) /* lcd_data9.gpio2[15] */ +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd */ +- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd */ +- >; +- }; +- +- uart3_pins: uart3_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data10.uart3_ctsn */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE6) /* lcd_data11.uart3_rtsn */ +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE1) /* spi0_cs1.uart3_rxd */ +- AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ +- >; +- }; +- +- uart4_pins: uart4_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data12.uart4_ctsn */ +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE6) /* lcd_data13.uart4_rtsn */ +- AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE1) /* uart0_ctsn.uart4_rxd */ +- AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE1) /* uart0_rtsn.uart4_txd */ +- >; +- }; +- +- uart5_pins: uart5_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE4) /* lcd_data14.uart5_rxd */ +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT, MUX_MODE3) /* rmiii1_refclk.uart5_txd */ +- >; +- }; +- +- mmc1_pins: mmc1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_clk.mmc0_clk */ +- AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ +- AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */ +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */ +- >; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- status = "okay"; +- rts-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; +- rs485-rts-active-high; +- rs485-rx-during-tx; +- rs485-rts-delay = <1 1>; +- linux,rs485-enabled-at-boot-time; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "okay"; +- rts-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; +- rs485-rts-active-high; +- rs485-rts-delay = <1 1>; +- linux,rs485-enabled-at-boot-time; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pins>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart5_pins>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- pinctrl-names = "default"; +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- +- gpio@20 { +- compatible = "microchip,mcp23017"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x20>; +- }; +- +- tps: tps@24 { +- reg = <0x24>; +- }; +- +- eeprom@53 { +- compatible = "microchip,24c02", "atmel,24c02"; +- reg = <0x53>; +- pagesize = <8>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1307"; +- reg = <0x68>; +- }; +-}; +- +-&elm { +- status = "okay"; +-}; +- +-&gpmc { +- compatible = "ti,am3352-gpmc"; +- status = "okay"; +- gpmc,num-waitpins = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpmc_pins>; +- +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0 0x08000000 0x08000000>, /* CS0: NOR 128M */ +- <1 0 0x1c000000 0x01000000>; /* CS1: FRAM 16M */ +- +- nor@0,0 { +- reg = <0 0x00000000 0x08000000>; +- compatible = "cfi-flash"; +- linux,mtd-name = "spansion,s29gl010p11t"; +- bank-width = <2>; +- +- gpmc,mux-add-data = <2>; +- +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <160>; +- gpmc,cs-wr-off-ns = <160>; +- gpmc,adv-on-ns = <10>; +- gpmc,adv-rd-off-ns = <30>; +- gpmc,adv-wr-off-ns = <30>; +- gpmc,oe-on-ns = <40>; +- gpmc,oe-off-ns = <160>; +- gpmc,we-on-ns = <40>; +- gpmc,we-off-ns = <160>; +- gpmc,rd-cycle-ns = <160>; +- gpmc,wr-cycle-ns = <160>; +- gpmc,access-ns = <150>; +- gpmc,page-burst-access-ns = <10>; +- gpmc,cycle2cycle-samecsen; +- gpmc,cycle2cycle-delay-ns = <20>; +- gpmc,wr-data-mux-bus-ns = <70>; +- gpmc,wr-access-ns = <80>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* +- MTD partition table +- =================== +- +------------+-->0x00000000-> U-Boot start +- | | +- | |-->0x000BFFFF-> U-Boot end +- | |-->0x000C0000-> ENV1 start +- | | +- | |-->0x000DFFFF-> ENV1 end +- | |-->0x000E0000-> ENV2 start +- | | +- | |-->0x000FFFFF-> ENV2 end +- | |-->0x00100000-> Kernel start +- | | +- | |-->0x004FFFFF-> Kernel end +- | |-->0x00500000-> File system start +- | | +- | |-->0x01FFFFFF-> File system end +- | |-->0x02000000-> User data start +- | | +- | |-->0x03FFFFFF-> User data end +- | |-->0x04000000-> Data storage start +- | | +- +------------+-->0x08000000-> NOR end (Free end) +- */ +- partition@0 { +- label = "boot"; +- reg = <0x00000000 0x000c0000>; /* 768KB */ +- }; +- +- partition@1 { +- label = "env1"; +- reg = <0x000c0000 0x00020000>; /* 128KB */ +- }; +- +- partition@2 { +- label = "env2"; +- reg = <0x000e0000 0x00020000>; /* 128KB */ +- }; +- +- partition@3 { +- label = "kernel"; +- reg = <0x00100000 0x00400000>; /* 4MB */ +- }; +- +- partition@4 { +- label = "rootfs"; +- reg = <0x00500000 0x01b00000>; /* 27MB */ +- }; +- +- partition@5 { +- label = "user"; +- reg = <0x02000000 0x02000000>; /* 32MB */ +- }; +- +- partition@6 { +- label = "data"; +- reg = <0x04000000 0x04000000>; /* 64MB */ +- }; +- }; +- +- fram@1,0 { +- reg = <1 0x00000000 0x01000000>; +- bank-width = <2>; +- +- gpmc,mux-add-data = <2>; +- +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <160>; +- gpmc,cs-wr-off-ns = <160>; +- gpmc,adv-on-ns = <10>; +- gpmc,adv-rd-off-ns = <20>; +- gpmc,adv-wr-off-ns = <20>; +- gpmc,oe-on-ns = <30>; +- gpmc,oe-off-ns = <150>; +- gpmc,we-on-ns = <30>; +- gpmc,we-off-ns = <150>; +- gpmc,rd-cycle-ns = <160>; +- gpmc,wr-cycle-ns = <160>; +- gpmc,access-ns = <130>; +- gpmc,page-burst-access-ns = <10>; +- gpmc,cycle2cycle-samecsen; +- gpmc,cycle2cycle-diffcsen; +- gpmc,cycle2cycle-delay-ns = <10>; +- gpmc,wr-data-mux-bus-ns = <30>; +- gpmc,wr-access-ns = <0>; +- }; +-}; +- +-&mac_sw { +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "mii"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- phy-handle = <ðphy1>; +- phy-mode = "mii"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&mmc1 { +- status = "okay"; +- vmmc-supply = <&ldo4_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- bus-width = <4>; +- cd-gpios = <&gpio3 8 0>; +- wp-gpios = <&gpio3 18 0>; +-}; +- +-#include "tps65217.dtsi" +- +-&tps { +- regulators { +- dcdc1_reg: regulator@0 { +- /* +1.5V voltage with ±4% tolerance */ +- regulator-min-microvolt = <1450000>; +- regulator-max-microvolt = <1550000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc2_reg: regulator@1 { +- /* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */ +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <915000>; +- regulator-max-microvolt = <1140000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc3_reg: regulator@2 { +- /* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */ +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <915000>; +- regulator-max-microvolt = <1140000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1_reg: regulator@3 { +- /* +1.8V voltage with ±4% tolerance */ +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <1870000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo2_reg: regulator@4 { +- /* +3.3V voltage with ±4% tolerance */ +- regulator-min-microvolt = <3175000>; +- regulator-max-microvolt = <3430000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo3_reg: regulator@5 { +- /* +1.8V voltage with ±4% tolerance */ +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <1870000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo4_reg: regulator@6 { +- /* +3.3V voltage with ±4% tolerance */ +- regulator-min-microvolt = <3175000>; +- regulator-max-microvolt = <3430000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-netcan-plus-1xx.dts b/scripts/dtc/include-prefixes/arm/am335x-netcan-plus-1xx.dts +deleted file mode 100644 +index 57e756b0f192..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-netcan-plus-1xx.dts ++++ /dev/null +@@ -1,87 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/* +- * VScom OnRISC +- * http://www.vscom.de +- */ +- +-/dts-v1/; +- +-#include "am335x-baltos.dtsi" +-#include "am335x-baltos-leds.dtsi" +- +-/ { +- model = "NetCAN"; +- +- leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&user_leds_s0>; +- +- compatible = "gpio-leds"; +- +- led@1 { +- label = "can_data"; +- linux,default-trigger = "netdev"; +- gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- led@2 { +- label = "can_error"; +- gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +-}; +- +-&am33xx_pinmux { +- user_leds_s0: user_leds_s0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* CAN Data LED */ +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* CAN Error LED */ +- >; +- }; +- +- dcan1_pins: pinmux_dcan1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* CAN TX */ +- AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* CAN RX */ +- >; +- }; +-}; +- +-&usb0_phy { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&davinci_mdio_sw { +- phy0: ethernet-phy@0 { +- reg = <1>; +- }; +-}; +- +-&cpsw_port1 { +- phy-mode = "rmii"; +- ti,dual-emac-pvid = <1>; +- phy-handle = <&phy0>; +-}; +- +-&cpsw_port2 { +- phy-mode = "rgmii-id"; +- ti,dual-emac-pvid = <2>; +- phy-handle = <&phy1>; +-}; +- +-&dcan1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&dcan1_pins>; +- +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-netcom-plus-2xx.dts b/scripts/dtc/include-prefixes/arm/am335x-netcom-plus-2xx.dts +deleted file mode 100644 +index c6cc1c6218a9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-netcom-plus-2xx.dts ++++ /dev/null +@@ -1,95 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/* +- * VScom OnRISC +- * http://www.vscom.de +- */ +- +-/dts-v1/; +- +-#include "am335x-baltos.dtsi" +-#include "am335x-baltos-leds.dtsi" +- +-/ { +- model = "NetCom Plus"; +-}; +- +-&am33xx_pinmux { +- uart1_pins: pinmux_uart1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) /* RX */ +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) /* TX */ +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) /* CTS */ +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* RTS */ +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */ +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */ +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */ +- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */ +- >; +- }; +- +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* RX */ +- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* TX */ +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* CTS */ +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* RTS */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */ +- >; +- }; +-}; +- +-&usb0_phy { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; +- dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; +- dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; +- rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; +- +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; +- dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; +- dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +- +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- phy0: ethernet-phy@0 { +- reg = <1>; +- }; +-}; +- +-&cpsw_port1 { +- phy-mode = "rmii"; +- ti,dual-emac-pvid = <1>; +- phy-handle = <&phy0>; +-}; +- +-&cpsw_port2 { +- phy-mode = "rgmii-id"; +- ti,dual-emac-pvid = <2>; +- phy-handle = <&phy1>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-netcom-plus-8xx.dts b/scripts/dtc/include-prefixes/arm/am335x-netcom-plus-8xx.dts +deleted file mode 100644 +index 96dffd3ffd85..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-netcom-plus-8xx.dts ++++ /dev/null +@@ -1,115 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/* +- * VScom OnRISC +- * http://www.vscom.de +- */ +- +-/dts-v1/; +- +-#include "am335x-baltos.dtsi" +- +-/ { +- model = "NetCom Plus"; +-}; +- +-&am33xx_pinmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&dip_switches>; +- +- dip_switches: pinmux_dip_switches { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- tca6416_pins: pinmux_tca6416_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) +- >; +- }; +- +- i2c2_pins: pinmux_i2c2_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE3) +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE3) +- >; +- }; +-}; +- +-&usb0_phy { +- status = "okay"; +-}; +- +-&usb1_phy { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&usb1 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&i2c1 { +- tca6416a: gpio@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gpio0>; +- interrupts = <20 IRQ_TYPE_EDGE_RISING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tca6416_pins>; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- tca6416b: gpio@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- tca6416c: gpio@21 { +- compatible = "ti,tca6416"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&davinci_mdio_sw { +- phy0: ethernet-phy@0 { +- reg = <1>; +- }; +-}; +- +-&cpsw_port1 { +- phy-mode = "rmii"; +- ti,dual-emac-pvid = <1>; +- phy-handle = <&phy0>; +-}; +- +-&cpsw_port2 { +- phy-mode = "rgmii-id"; +- ti,dual-emac-pvid = <2>; +- phy-handle = <&phy1>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-osd3358-sm-red.dts b/scripts/dtc/include-prefixes/arm/am335x-osd3358-sm-red.dts +deleted file mode 100644 +index 605b2a436edf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-osd3358-sm-red.dts ++++ /dev/null +@@ -1,434 +0,0 @@ +-//SPDX-License-Identifier: GPL-2.0 +-/* Copyright (C) 2018 Octavo Systems LLC - https://www.octavosystems.com/ +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License version 2 as +- * published by the Free Software Foundation. +- */ +- +-/dts-v1/; +- +-#include "am33xx.dtsi" +-#include "am335x-osd335x-common.dtsi" +-#include +- +-#include +- +-/ { +- model = "Octavo Systems OSD3358-SM-RED"; +- compatible = "oct,osd3358-sm-refdesign", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +-}; +- +-&ldo3_reg { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +-}; +- +-&mmc2 { +- vmmc-supply = <&vmmcsd_fixed>; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_pins>; +- bus-width = <8>; +- status = "okay"; +-}; +- +-&lcdc { +- status = "okay"; +- +- /* If you want to get 24 bit RGB and 16 BGR mode instead of +- * current 16 bit RGB and 24 BGR modes, set the propety +- * below to "crossed" and uncomment the video-ports -property +- * in tda19988 node. +- * AM335x errata for wiring: +- * https://www.ti.com/lit/er/sprz360i/sprz360i.pdf +- */ +- +- blue-and-red-wiring = "straight"; +- +- port { +- lcdc_0: endpoint { +- remote-endpoint = <&hdmi_0>; +- }; +- }; +-}; +- +-&i2c0 { +- tda19988: hdmi-encoder@70 { +- compatible = "nxp,tda998x"; +- reg = <0x70>; +- +- pinctrl-names = "default", "off"; +- pinctrl-0 = <&nxp_hdmi_bonelt_pins>; +- pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; +- +- /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ +- /* video-ports = <0x234501>; */ +- +- #sound-dai-cells = <0>; +- audio-ports = < TDA998x_I2S 0x03>; +- +- port { +- hdmi_0: endpoint { +- remote-endpoint = <&lcdc_0>; +- }; +- }; +- }; +- +- mpu9250: imu@68 { +- compatible = "invensense,mpu6050"; +- reg = <0x68>; +- interrupt-parent = <&gpio3>; +- interrupts = <21 IRQ_TYPE_EDGE_RISING>; +- i2c-gate { +- #address-cells = <1>; +- #size-cells = <0>; +- ax8975@c { +- compatible = "ak,ak8975"; +- reg = <0x0c>; +- }; +- }; +- /*invensense,int_config = <0x10>; +- invensense,level_shifter = <0>; +- invensense,orientation = [01 00 00 00 01 00 00 00 01]; +- invensense,sec_slave_type = <0>; +- invensense,key = [4e cc 7e eb f6 1e 35 22 00 34 0d 65 32 e9 94 89];*/ +- }; +- +- bmp280: pressure@76 { +- compatible = "bosch,bmp280"; +- reg = <0x76>; +- }; +-}; +- +-&mcasp0 { +- #sound-dai-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mcasp0_pins>; +- status = "okay"; +- op-mode = <0>; /* MCASP_IIS_MODE */ +- tdm-slots = <2>; +- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ +- 0 0 1 0 +- >; +- tx-num-evt = <32>; +- rx-num-evt = <32>; +-}; +- +-/ { +- clk_mcasp0_fixed: clk-mcasp0-fixed { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24576000>; +- }; +- +- clk_mcasp0: clk-mcasp0 { +- #clock-cells = <0>; +- compatible = "gpio-gate-clock"; +- clocks = <&clk_mcasp0_fixed>; +- enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "TI BeagleBone Black"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&dailink0_master>; +- simple-audio-card,frame-master = <&dailink0_master>; +- +- dailink0_master: simple-audio-card,cpu { +- sound-dai = <&mcasp0>; +- clocks = <&clk_mcasp0>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&tda19988>; +- }; +- }; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&user_leds_s0>; +- +- compatible = "gpio-leds"; +- +- led2 { +- label = "beaglebone:green:usr0"; +- gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- +- led3 { +- label = "beaglebone:green:usr1"; +- gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- +- led4 { +- label = "beaglebone:green:usr2"; +- gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "cpu0"; +- default-state = "off"; +- }; +- +- led5 { +- label = "beaglebone:green:usr3"; +- gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc1"; +- default-state = "off"; +- }; +- }; +- +- vmmcsd_fixed: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsd_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&am33xx_pinmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&clkout2_pin>; +- +- nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) +- >; +- }; +- +- mcasp0_pins: mcasp0-pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ +- AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ +- >; +- }; +- +- flash_enable: flash-enable { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */ +- >; +- }; +- +- imu_interrupt: imu-interrupt { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */ +- >; +- }; +- +- ethernet_interrupt: ethernet-interrupt{ +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */ +- >; +- }; +- +- user_leds_s0: user-leds-s0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ +- >; +- }; +- +- i2c2_pins: pinmux-i2c2-pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ +- >; +- }; +- +- uart0_pins: pinmux-uart0-pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- clkout2_pin: pinmux-clkout2-pin { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ +- >; +- }; +- +- cpsw_default: cpsw-default { +- pinctrl-single,pins = < +- /* Slave 1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) +- >; +- }; +- +- cpsw_sleep: cpsw-sleep { +- pinctrl-single,pins = < +- /* Slave 1 reset value */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- davinci_mdio_default: davinci-mdio-default { +- pinctrl-single,pins = < +- /* MDIO */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- davinci_mdio_sleep: davinci-mdio-sleep { +- pinctrl-single,pins = < +- /* MDIO reset value */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- mmc1_pins: pinmux-mmc1-pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- emmc_pins: pinmux-emmc-pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ +- >; +- }; +-}; +- +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- +- status = "okay"; +-}; +- +-&usb0 { +- dr_mode = "peripheral"; +- interrupts-extended = <&intc 18 &tps 0>; +- interrupt-names = "mc", "vbus"; +-}; +- +-&usb1 { +- dr_mode = "host"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "rgmii-txid"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- status = "disabled"; +-}; +- +-&mac_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&cpsw_default>; +- pinctrl-1 = <&cpsw_sleep>; +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&davinci_mdio_default>; +- pinctrl-1 = <&davinci_mdio_sleep>; +- +- ethphy0: ethernet-phy@4 { +- reg = <4>; +- }; +-}; +- +-&mmc1 { +- status = "okay"; +- vmmc-supply = <&vmmcsd_fixed>; +- bus-width = <0x4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +-}; +- +-&rtc { +- system-power-controller; +- clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; +- clock-names = "ext-clk", "int-clk"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-osd335x-common.dtsi b/scripts/dtc/include-prefixes/arm/am335x-osd335x-common.dtsi +deleted file mode 100644 +index 2888b15999ee..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-osd335x-common.dtsi ++++ /dev/null +@@ -1,124 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * Author: Robert Nelson +- */ +- +-/ { +- cpus { +- cpu@0 { +- cpu0-supply = <&dcdc2_reg>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512 MB */ +- }; +-}; +- +-&cpu0_opp_table { +- /* +- * Octavo Systems: +- * The EFUSE_SMA register is not programmed for any of the AM335x wafers +- * we get and we are not programming them during our production test. +- * Therefore, from a DEVICE_ID revision point of view, the silicon looks +- * like it is Revision 2.1. However, from an EFUSE_SMA point of view for +- * the HW OPP table, the silicon looks like it is Revision 1.0 (ie the +- * EFUSE_SMA register reads as all zeros). +- */ +- oppnitro-1000000000 { +- opp-supported-hw = <0x06 0x0100>; +- }; +-}; +- +-&am33xx_pinmux { +- i2c0_pins: pinmux-i2c0-pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- tps: tps@24 { +- reg = <0x24>; +- }; +-}; +- +-/include/ "tps65217.dtsi" +- +-&tps { +- interrupts = <7>; /* NMI */ +- interrupt-parent = <&intc>; +- +- ti,pmic-shutdown-controller; +- +- pwrbutton { +- interrupts = <2>; +- status = "okay"; +- }; +- +- regulators { +- dcdc1_reg: regulator@0 { +- regulator-name = "vdds_dpr"; +- regulator-always-on; +- }; +- +- dcdc2_reg: regulator@1 { +- /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <1351500>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc3_reg: regulator@2 { +- /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <1150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1_reg: regulator@3 { +- regulator-name = "vio,vrtc,vdds"; +- regulator-always-on; +- }; +- +- ldo2_reg: regulator@4 { +- regulator-name = "vdd_3v3aux"; +- regulator-always-on; +- }; +- +- ldo3_reg: regulator@5 { +- regulator-name = "vdd_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo4_reg: regulator@6 { +- regulator-name = "vdd_3v3a"; +- regulator-always-on; +- }; +- }; +-}; +- +-&aes { +- status = "okay"; +-}; +- +-&sham { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-pcm-953.dtsi b/scripts/dtc/include-prefixes/arm/am335x-pcm-953.dtsi +deleted file mode 100644 +index 124026fa0d09..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-pcm-953.dtsi ++++ /dev/null +@@ -1,240 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014-2017 Phytec Messtechnik GmbH +- * Author: Wadim Egorov +- * Teresa Remmet +- */ +- +-#include +- +-/ { +- model = "Phytec AM335x PCM-953"; +- compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx"; +- +- /* Power */ +- regulators { +- vcc3v3: fixedregulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- +- vcc1v8: fixedregulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- }; +- }; +- +- /* User IO */ +- user_leds: user_leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&user_leds_pins>; +- +- user-led0 { +- gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "gpio"; +- default-state = "on"; +- }; +- +- user-led1 { +- gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "gpio"; +- default-state = "on"; +- }; +- }; +- +- user_buttons: user_buttons { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&user_buttons_pins>; +- +- button@0 { +- label = "home"; +- linux,code = ; +- gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; +- wakeup-source; +- }; +- +- button@1 { +- label = "menu"; +- linux,code = ; +- gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; +- wakeup-source; +- }; +- +- }; +-}; +- +-&am33xx_pinmux { +- user_buttons_pins: pinmux_user_buttons { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu0.gpio3_7 */ +- AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu1.gpio3_8 */ +- >; +- }; +- +- user_leds_pins: pinmux_user_leds { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn1.gpio1_30 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn2.gpio1_31 */ +- >; +- }; +-}; +- +-/* CAN */ +-&am33xx_pinmux { +- dcan1_pins: pinmux_dcan1 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart1_rxd.dcan1_tx_mux2 */ +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLUP, MUX_MODE2) /* uart1_txd.dcan1_rx_mux2 */ +- >; +- }; +-}; +- +-&dcan1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&dcan1_pins>; +- status = "okay"; +-}; +- +-/* Ethernet */ +-&am33xx_pinmux { +- ethernet1_pins: pinmux_ethernet1 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ +- >; +- }; +-}; +- +-&cpsw_port2 { +- phy-handle = <&phy1>; +- phy-mode = "rgmii-id"; +- ti,dual-emac-pvid = <2>; +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- phy1: ethernet-phy@2 { +- reg = <2>; +- }; +-}; +- +-&mac_sw { +- pinctrl-names = "default"; +- pinctrl-0 = <ðernet0_pins ðernet1_pins>; +-}; +- +-/* Misc */ +-&am33xx_pinmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&cb_gpio_pins>; +- +- cb_gpio_pins: pinmux_cb_gpio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ +- AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_rtsn.gpio1_9 */ +- >; +- }; +-}; +- +-/* MMC */ +-&am33xx_pinmux { +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ +- >; +- }; +-}; +- +-&mmc1 { +- vmmc-supply = <&vcc3v3>; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-/* UARTs */ +-&am33xx_pinmux { +- uart0_pins: pinmux_uart0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- uart1_pins: pinmux_uart1 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- uart2_pins: pinmux_uart2 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */ +- >; +- }; +- +- uart3_pins: pinmux_uart3 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd3.uart3_rxd */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd2.uart3_txd */ +- >; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- status = "okay"; +-}; +- +-/* USB */ +-&usb1 { +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-pdu001.dts b/scripts/dtc/include-prefixes/arm/am335x-pdu001.dts +deleted file mode 100644 +index b793beeab245..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-pdu001.dts ++++ /dev/null +@@ -1,573 +0,0 @@ +-/* +- * pdu001.dts +- * +- * EETS GmbH PDU001 board device tree file +- * +- * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ +- * +- * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ +- * +- * SPDX-License-Identifier: GPL-2.0+ +- */ +- +-/dts-v1/; +- +-#include "am33xx.dtsi" +-#include +-#include +- +-/ { +- model = "EETS,PDU001"; +- compatible = "ti,am33xx"; +- +- chosen { +- stdout-path = &uart3; +- }; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&vdd1_reg>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +- +- vbat: fixedregulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "vbat"; +- regulator-min-microvolt = <3600000>; +- regulator-max-microvolt = <3600000>; +- regulator-boot-on; +- }; +- +- lis3_reg: fixedregulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "lis3_reg"; +- regulator-boot-on; +- }; +- +- panel { +- compatible = "ti,tilcdc,panel"; +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_pins_s0>; +- panel-info { +- ac-bias = <255>; +- ac-bias-intrpt = <0>; +- dma-burst-sz = <16>; +- bpp = <16>; +- fdd = <0x80>; +- sync-edge = <0>; +- sync-ctrl = <1>; +- raster-order = <0>; +- fifo-th = <0>; +- }; +- +- display-timings { +- 240x320p16 { +- clock-frequency = <6500000>; +- hactive = <240>; +- vactive = <320>; +- hfront-porch = <6>; +- hback-porch = <6>; +- hsync-len = <1>; +- vback-porch = <6>; +- vfront-porch = <6>; +- vsync-len = <1>; +- hsync-active = <0>; +- vsync-active = <0>; +- pixelclk-active = <1>; +- de-active = <0>; +- }; +- }; +- }; +-}; +- +-&am33xx_pinmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&clkout2_pin>; +- +- i2c0_pins: pinmux_i2c0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ +- >; +- }; +- +- i2c2_pins: pinmux_i2c2_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_clk.i2c2_sda */ +- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d0.i2c2_scl */ +- >; +- }; +- +- spi1_pins: pinmux_spi1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */ +- AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ +- >; +- }; +- +- uart0_pins: pinmux_uart0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- uart1_pins: pinmux_uart1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1) /* spi0_cs1.uart3_rxd */ +- AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ +- >; +- }; +- +- clkout2_pin: pinmux_clkout2_pin { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ +- >; +- }; +- +- cpsw_default: cpsw_default { +- pinctrl-single,pins = < +- /* Port 1 (emac0) */ +- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT, MUX_MODE0) +- +- /* Port 2 (emac1) */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* mii2_txen.gpmc_a0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT, MUX_MODE1) /* mii2_rxdv.gpmc_a1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* mii2_txd3.gpmc_a2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* mii2_txd2.gpmc_a3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* mii2_txd1.gpmc_a4 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* mii2_txd0.gpmc_a5 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT, MUX_MODE1) /* mii2_txclk.gpmc_a6 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT, MUX_MODE1) /* mii2_rxclk.gpmc_a7 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE1) /* mii2_rxd3.gpmc_a8 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE1) /* mii2_rxd2.gpmc_a9 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE1) /* mii2_rxd1.gpmc_a10 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE1) /* mii2_rxd0.gpmc_a11 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT, MUX_MODE1) /* mii2_crs.gpmc_wait0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT, MUX_MODE1) /* mii2_rxer.gpmc_wpn */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT, MUX_MODE1) /* mii2_col.gpmc_ben1 */ +- >; +- }; +- +- davinci_mdio_default: davinci_mdio_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- /* eMMC */ +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- mmc2_pins: pinmux_mmc2_pins { +- /* SD cardcage */ +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ +- /* card change signal for frontpanel SD cardcage */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ +- >; +- }; +- +- lcd_pins_s0: lcd_pins_s0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) +- >; +- }; +- +- dcan0_pins: pinmux_dcan0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart1_ctsn.d_can0_tx */ +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart1_rtsn.d_can0_rx */ +- >; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- +- rts-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- rs485-rts-active-high; +- rs485-rts-delay = <0 0>; +- linux,rs485-enabled-at-boot-time; +- +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- tps: tps@2d { +- reg = <0x2d>; +- }; +- +- m2_eeprom: m2_eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- status = "okay"; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- +- status = "okay"; +- clock-frequency = <100000>; +- +- board_24aa025e48: board_24aa025e48@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- }; +- +- backplane_24aa025e48: backplane_24aa025e48@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- }; +- +- pca9532: pca9532@60 { +- compatible = "nxp,pca9532"; +- reg = <0x60>; +- psc0 = <0x97>; +- pwm0 = <0x80>; +- psc1 = <0x97>; +- pwm1 = <0x10>; +- +- run.red@0 { +- type = ; +- }; +- run.green@1 { +- type = ; +- default-state = "on"; +- }; +- s2.red@2 { +- type = ; +- }; +- s2.green@3 { +- type = ; +- }; +- s1.yellow@4 { +- type = ; +- }; +- s1.green@5 { +- type = ; +- }; +- }; +- +- pca9530: pca9530@61 { +- compatible = "nxp,pca9530"; +- reg = <0x61>; +- +- tft-panel@0 { +- type = ; +- linux,default-trigger = "backlight"; +- default-state = "on"; +- }; +- }; +- +- mcp79400: mcp79400@6f { +- compatible = "microchip,mcp7940x"; +- reg = <0x6f>; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins>; +- ti,pindir-d0-out-d1-in; +- status = "okay"; +- +- display-controller@0 { +- compatible = "orisetech,otm3225a"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- // SPI mode 3 +- spi-cpol; +- spi-cpha; +- status = "okay"; +- }; +-}; +- +-/* +- * Disable soc's rtc as we have no VBAT for it. This makes the board +- * rtc (Microchip MCP79400) the default rtc device 'rtc0'. +- */ +-&rtc { +- status = "disabled"; +-}; +- +-&lcdc { +- status = "okay"; +-}; +- +-&elm { +- status = "okay"; +-}; +- +-#include "tps65910.dtsi" +- +-&tps { +- vcc1-supply = <&vbat>; +- vcc2-supply = <&vbat>; +- vcc3-supply = <&vbat>; +- vcc4-supply = <&vbat>; +- vcc5-supply = <&vbat>; +- vcc6-supply = <&vbat>; +- vcc7-supply = <&vbat>; +- vccio-supply = <&vbat>; +- +- regulators { +- vrtc_reg: regulator@0 { +- regulator-name = "ldo_vrtc"; +- regulator-always-on; +- }; +- +- vio_reg: regulator@1 { +- regulator-name = "buck_vdd_ddr"; +- regulator-always-on; +- }; +- +- vdd1_reg: regulator@2 { +- /* VDD_MPU voltage limits */ +- regulator-name = "buck_vdd_mpu"; +- regulator-min-microvolt = <912500>; +- regulator-max-microvolt = <1312500>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd2_reg: regulator@3 { +- /* VDD_CORE voltage limits */ +- regulator-name = "buck_vdd_core"; +- regulator-min-microvolt = <912500>; +- regulator-max-microvolt = <1150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd3_reg: regulator@4 { +- regulator-name = "boost_res"; +- regulator-always-on; +- }; +- +- vdig1_reg: regulator@5 { +- regulator-name = "ldo_vdig1"; +- regulator-always-on; +- }; +- +- vdig2_reg: regulator@6 { +- regulator-name = "ldo_vdig2"; +- regulator-always-on; +- }; +- +- vpll_reg: regulator@7 { +- regulator-name = "ldo_vpll"; +- regulator-always-on; +- }; +- +- vdac_reg: regulator@8 { +- regulator-name = "ldo_vdac"; +- regulator-always-on; +- }; +- +- vaux1_reg: regulator@9 { +- regulator-name = "ldo_vaux1"; +- regulator-always-on; +- }; +- +- vaux2_reg: regulator@10 { +- regulator-name = "ldo_vaux2"; +- regulator-always-on; +- }; +- +- vaux33_reg: regulator@11 { +- regulator-name = "ldo_vaux33"; +- regulator-always-on; +- }; +- +- vmmc_reg: regulator@12 { +- regulator-name = "ldo_vmmc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vbb_reg: regulator@13 { +- regulator-name = "bat_vbb"; +- }; +- }; +-}; +- +-&mac_sw { +- pinctrl-names = "default"; +- pinctrl-0 = <&cpsw_default>; +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default"; +- pinctrl-0 = <&davinci_mdio_default>; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "mii"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- phy-handle = <ðphy1>; +- phy-mode = "mii"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&tscadc { +- status = "okay"; +- tsc { +- ti,wires = <4>; +- ti,x-plate-resistance = <200>; +- ti,coordinate-readouts = <5>; +- ti,wire-config = <0x01 0x10 0x22 0x33>; +- ti,charge-delay = <0x400>; +- }; +- +- adc { +- ti,adc-channels = <4 5 6 7>; +- }; +-}; +- +-&mmc1 { +- status = "okay"; +- vmmc-supply = <&vmmc_reg>; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- non-removable; +-}; +- +-&mmc2 { +- status = "okay"; +- vmmc-supply = <&vmmc_reg>; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; +-}; +- +-&sham { +- status = "okay"; +-}; +- +-&aes { +- status = "okay"; +-}; +- +-&dcan0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dcan0_pins>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-pepper.dts b/scripts/dtc/include-prefixes/arm/am335x-pepper.dts +deleted file mode 100644 +index b5e88e627bc1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-pepper.dts ++++ /dev/null +@@ -1,639 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Gumstix, Inc. - https://www.gumstix.com/ +- */ +-/dts-v1/; +- +-#include +-#include "am33xx.dtsi" +- +-/ { +- model = "Gumstix Pepper"; +- compatible = "gumstix,am335x-pepper", "ti,am33xx"; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&dcdc3_reg>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512 MB */ +- }; +- +- buttons: user_buttons { +- compatible = "gpio-keys"; +- }; +- +- leds: user_leds { +- compatible = "gpio-leds"; +- }; +- +- panel: lcd_panel { +- compatible = "ti,tilcdc,panel"; +- }; +- +- sound: sound_iface { +- compatible = "ti,da830-evm-audio"; +- }; +- +- vbat: fixedregulator0 { +- compatible = "regulator-fixed"; +- }; +- +- v3v3c_reg: fixedregulator1 { +- compatible = "regulator-fixed"; +- }; +- +- vdd5_reg: fixedregulator2 { +- compatible = "regulator-fixed"; +- }; +-}; +- +-/* I2C Busses */ +-&i2c0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- +- clock-frequency = <400000>; +- +- tps: tps@24 { +- reg = <0x24>; +- }; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- }; +- +- audio_codec: tlv320aic3106@1b { +- compatible = "ti,tlv320aic3106"; +- reg = <0x1b>; +- ai3x-micbias-vg = <0x2>; +- }; +- +- accel: lis331dlh@1d { +- compatible = "st,lis3lv02d"; +- reg = <0x1d>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- clock-frequency = <400000>; +-}; +- +-&am33xx_pinmux { +- i2c0_pins: pinmux_i2c0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- i2c1_pins: pinmux_i2c1 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE3) /* mii1_crs,i2c1_sda */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE3) /* mii1_rxerr,i2c1_scl */ +- >; +- }; +-}; +- +-/* Accelerometer */ +-&accel { +- pinctrl-names = "default"; +- pinctrl-0 = <&accel_pins>; +- +- Vdd-supply = <&ldo3_reg>; +- Vdd_IO-supply = <&ldo3_reg>; +- st,irq1-click; +- st,wakeup-x-lo; +- st,wakeup-x-hi; +- st,wakeup-y-lo; +- st,wakeup-y-hi; +- st,wakeup-z-lo; +- st,wakeup-z-hi; +- st,min-limit-x = <92>; +- st,max-limit-x = <14>; +- st,min-limit-y = <14>; +- st,max-limit-y = <92>; +- st,min-limit-z = <92>; +- st,max-limit-z = <14>; +-}; +- +-&am33xx_pinmux { +- accel_pins: pinmux_accel { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT, MUX_MODE7) /* gpmc_wen.gpio2_4 */ +- >; +- }; +-}; +- +-/* Audio */ +-&audio_codec { +- status = "okay"; +- +- reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +- AVDD-supply = <&ldo3_reg>; +- IOVDD-supply = <&ldo3_reg>; +- DRVDD-supply = <&ldo3_reg>; +- DVDD-supply = <&dcdc1_reg>; +-}; +- +-&sound { +- ti,model = "AM335x-EVM"; +- ti,audio-codec = <&audio_codec>; +- ti,mcasp-controller = <&mcasp0>; +- ti,codec-clock-rate = <12000000>; +- ti,audio-routing = +- "Headphone Jack", "HPLOUT", +- "Headphone Jack", "HPROUT", +- "MIC3L", "Mic3L Switch"; +-}; +- +-&mcasp0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&audio_pins>; +- +- op-mode = <0>; /* MCASP_ISS_MODE */ +- tdm-slots = <2>; +- serial-dir = < +- 1 2 0 0 +- 0 0 0 0 +- 0 0 0 0 +- 0 0 0 0 +- >; +- tx-num-evt = <1>; +- rx-num-evt = <1>; +-}; +- +-&am33xx_pinmux { +- audio_pins: pinmux_audio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7) /* gpmc_a0.gpio1_16 */ +- >; +- }; +-}; +- +-/* Display: 24-bit LCD Screen */ +-&panel { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_pins>; +- panel-info { +- ac-bias = <255>; +- ac-bias-intrpt = <0>; +- dma-burst-sz = <16>; +- bpp = <32>; +- fdd = <0x80>; +- sync-edge = <0>; +- sync-ctrl = <1>; +- raster-order = <0>; +- fifo-th = <0>; +- }; +- display-timings { +- native-mode = <&timing0>; +- timing0: 480x272 { +- clock-frequency = <18400000>; +- hactive = <480>; +- vactive = <272>; +- hfront-porch = <8>; +- hback-porch = <4>; +- hsync-len = <41>; +- vfront-porch = <4>; +- vback-porch = <2>; +- vsync-len = <10>; +- hsync-active = <1>; +- vsync-active = <1>; +- }; +- }; +-}; +- +-&lcdc { +- status = "okay"; +-}; +- +-&am33xx_pinmux { +- lcd_pins: pinmux_lcd { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data16 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data17 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data18 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data19 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data20 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data21 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data22 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data23 */ +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) +- /* Display Enable */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a11.gpio1_27 */ +- >; +- }; +-}; +- +-/* Ethernet */ +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "rgmii"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- phy-handle = <ðphy1>; +- phy-mode = "rgmii"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default"; +- pinctrl-0 = <&mdio_pins>; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mac_sw { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <ðernet_pins>; +-}; +- +-&am33xx_pinmux { +- ethernet_pins: pinmux_ethernet { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE2) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE2) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE2) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE2) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE2) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE2) +- /* ethernet interrupt */ +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE7) /* rmii2_refclk.gpio0_29 */ +- /* ethernet PHY nReset */ +- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLUP, MUX_MODE7) /* mii1_col.gpio3_0 */ +- >; +- }; +- +- mdio_pins: pinmux_mdio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) +- >; +- }; +-}; +- +-/* MMC */ +-&mmc1 { +- /* Bootable SD card slot */ +- status = "okay"; +- vmmc-supply = <&ldo3_reg>; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd_pins>; +- cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +-}; +- +-&mmc2 { +- /* eMMC (not populated) on MMC #2 */ +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_pins>; +- vmmc-supply = <&ldo3_reg>; +- bus-width = <8>; +- non-removable; +-}; +- +-&mmc3 { +- /* Wifi & Bluetooth on MMC #3 */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wireless_pins>; +- vmmmc-supply = <&v3v3c_reg>; +- bus-width = <4>; +- non-removable; +- dmas = <&edma_xbar 12 0 1 +- &edma_xbar 13 0 2>; +- dma-names = "tx", "rx"; +-}; +- +- +-&am33xx_pinmux { +- sd_pins: pinmux_sd_card { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ +- >; +- }; +- emmc_pins: pinmux_emmc { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ +- /* EMMC nReset */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ +- >; +- }; +- wireless_pins: pinmux_wireless { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ben1.mmc2_dat3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc1_clk */ +- /* WLAN nReset */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ +- /* WLAN nPower down */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_wait0.gpio0_30 */ +- /* 32kHz Clock */ +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ +- >; +- }; +-}; +- +-/* Power */ +-&vbat { +- regulator-name = "vbat"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +-}; +- +-&v3v3c_reg { +- regulator-name = "v3v3c_reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vbat>; +-}; +- +-&vdd5_reg { +- regulator-name = "vdd5_reg"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vbat>; +-}; +- +-/include/ "tps65217.dtsi" +- +-&tps { +- backlight { +- isel = <1>; /* ISET1 */ +- fdim = <200>; /* TPS65217_BL_FDIM_200HZ */ +- default-brightness = <80>; +- }; +- +- regulators { +- dcdc1_reg: regulator@0 { +- /* VDD_1V8 system supply */ +- regulator-always-on; +- }; +- +- dcdc2_reg: regulator@1 { +- /* VDD_CORE voltage limits 0.95V - 1.26V with +/-4% tolerance */ +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <1150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc3_reg: regulator@2 { +- /* VDD_MPU voltage limits 0.95V - 1.1V with +/-4% tolerance */ +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <1325000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1_reg: regulator@3 { +- /* VRTC 1.8V always-on supply */ +- regulator-name = "vrtc,vdds"; +- regulator-always-on; +- }; +- +- ldo2_reg: regulator@4 { +- /* 3.3V rail */ +- regulator-name = "vdd_3v3aux"; +- regulator-always-on; +- }; +- +- ldo3_reg: regulator@5 { +- /* VDD_3V3A 3.3V rail */ +- regulator-name = "vdd_3v3a"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo4_reg: regulator@6 { +- /* VDD_3V3B 3.3V rail */ +- regulator-name = "vdd_3v3b"; +- regulator-always-on; +- }; +- }; +-}; +- +-/* SPI Busses */ +-&spi0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins>; +-}; +- +-&am33xx_pinmux { +- spi0_pins: pinmux_spi0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +-}; +- +-/* Touch Screen */ +-&tscadc { +- status = "okay"; +- tsc { +- ti,wires = <4>; +- ti,x-plate-resistance = <200>; +- ti,coordinate-readouts = <5>; +- ti,wire-config = <0x00 0x11 0x22 0x33>; +- }; +- +- adc { +- ti,adc-channels = <4 5 6 7>; +- }; +-}; +- +-/* UARTs */ +-&uart0 { +- /* Serial Console */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +-}; +- +-&uart1 { +- /* Broken out to J6 header */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +-}; +- +-&am33xx_pinmux { +- uart0_pins: pinmux_uart0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- uart1_pins: pinmux_uart1 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +-}; +- +-/* USB */ +-&usb { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_pins>; +-}; +- +-&usb0 { +- dr_mode = "host"; +-}; +- +-&usb1 { +- dr_mode = "host"; +-}; +- +-&am33xx_pinmux { +- usb_pins: pinmux_usb { +- pinctrl-single,pins = < +- /* USB0 Over-Current (active low) */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7) /* gpmc_a9.gpio1_25 */ +- /* USB1 Over-Current (active low) */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_26 */ +- >; +- }; +-}; +- +-/* User IO */ +-&leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&user_leds_pins>; +- +- led0 { +- label = "pepper:user0:blue"; +- gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "none"; +- default-state = "off"; +- }; +- +- led1 { +- label = "pepper:user1:red"; +- gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "none"; +- default-state = "off"; +- }; +-}; +- +-&buttons { +- pinctrl-names = "default"; +- pinctrl-0 = <&user_buttons_pins>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- button0 { +- label = "home"; +- linux,code = ; +- gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; +- wakeup-source; +- }; +- +- button1 { +- label = "menu"; +- linux,code = ; +- gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; +- wakeup-source; +- }; +- +- buttons2 { +- label = "power"; +- linux,code = ; +- gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; +- wakeup-source; +- }; +-}; +- +-&am33xx_pinmux { +- user_leds_pins: pinmux_user_leds { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE7) /* gpmc_a4.gpio1_20 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* gpmc_a5.gpio1_21 */ +- >; +- }; +- +- user_buttons_pins: pinmux_user_buttons { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a7.gpio1_21 */ +- AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio0_7 */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-phycore-rdk.dts b/scripts/dtc/include-prefixes/arm/am335x-phycore-rdk.dts +deleted file mode 100644 +index 43907d03e675..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-phycore-rdk.dts ++++ /dev/null +@@ -1,28 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 PHYTEC Messtechnik GmbH +- * Author: Wadim Egorov +- */ +- +-/dts-v1/; +- +-#include "am335x-phycore-som.dtsi" +-#include "am335x-pcm-953.dtsi" +- +-/* SoM */ +-&gpmc { +- status = "okay"; +-}; +- +-&i2c_eeprom { +- status = "okay"; +-}; +- +-&i2c_rtc { +- status = "okay"; +-}; +- +-&serial_flash { +- status = "okay"; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-phycore-som.dtsi b/scripts/dtc/include-prefixes/arm/am335x-phycore-som.dtsi +deleted file mode 100644 +index f65cd1331315..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-phycore-som.dtsi ++++ /dev/null +@@ -1,343 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 Phytec Messtechnik GmbH +- * Author: Teresa Remmet +- */ +- +-#include "am33xx.dtsi" +-#include +- +-/ { +- model = "Phytec AM335x phyCORE"; +- compatible = "phytec,am335x-phycore-som", "ti,am33xx"; +- +- aliases { +- rtc0 = &i2c_rtc; +- rtc1 = &rtc; +- }; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&vdd1_reg>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +- +- vcc5v: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-/* Crypto Module */ +-&aes { +- status = "okay"; +-}; +- +-&sham { +- status = "okay"; +-}; +- +-/* EMMC */ +-&am33xx_pinmux { +- emmc_pins: pinmux_emmc_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ +- >; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_pins>; +- vmmc-supply = <&vmmc_reg>; +- bus-width = <8>; +- non-removable; +- status = "disabled"; +-}; +- +-/* Ethernet */ +-&am33xx_pinmux { +- ethernet0_pins: pinmux_ethernet0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- mdio_pins: pinmux_mdio { +- pinctrl-single,pins = < +- /* MDIO */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) +- >; +- }; +-}; +- +-&cpsw_port1 { +- phy-handle = <&phy0>; +- phy-mode = "rmii"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- status = "disabled"; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default"; +- pinctrl-0 = <&mdio_pins>; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&mac_sw { +- pinctrl-names = "default"; +- pinctrl-0 = <ðernet0_pins>; +- status = "okay"; +-}; +- +-/* I2C Busses */ +-&am33xx_pinmux { +- i2c0_pins: pinmux_i2c0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) +- >; +- }; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- clock-frequency = <400000>; +- status = "okay"; +- +- tps: pmic@2d { +- reg = <0x2d>; +- }; +- +- i2c_tmp102: temp@4b { +- compatible = "ti,tmp102"; +- reg = <0x4b>; +- status = "disabled"; +- }; +- +- i2c_eeprom: eeprom@52 { +- compatible = "atmel,24c32"; +- pagesize = <32>; +- reg = <0x52>; +- status = "disabled"; +- }; +- +- i2c_rtc: rtc@68 { +- compatible = "microcrystal,rv4162"; +- reg = <0x68>; +- status = "disabled"; +- }; +-}; +- +-/* NAND memory */ +-&am33xx_pinmux { +- nandflash_pins: pinmux_nandflash { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) +- >; +- }; +-}; +- +-&elm { +- status = "okay"; +-}; +- +-&gpmc { +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&nandflash_pins>; +- ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */ +- nandflash: nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ +- nand-bus-width = <8>; +- ti,nand-ecc-opt = "bch8"; +- gpmc,device-nand = "true"; +- gpmc,device-width = <1>; +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <30>; +- gpmc,cs-wr-off-ns = <30>; +- gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <30>; +- gpmc,adv-wr-off-ns = <30>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <20>; +- gpmc,oe-on-ns = <10>; +- gpmc,oe-off-ns = <30>; +- gpmc,access-ns = <30>; +- gpmc,rd-cycle-ns = <30>; +- gpmc,wr-cycle-ns = <30>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <50>; +- gpmc,cycle2cycle-diffcsen; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-access-ns = <30>; +- gpmc,wr-data-mux-bus-ns = <0>; +- +- ti,elm-id = <&elm>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-/* Power */ +-#include "tps65910.dtsi" +- +-&tps { +- vcc1-supply = <&vcc5v>; +- vcc2-supply = <&vcc5v>; +- vcc3-supply = <&vcc5v>; +- vcc4-supply = <&vcc5v>; +- vcc5-supply = <&vcc5v>; +- vcc6-supply = <&vcc5v>; +- vcc7-supply = <&vcc5v>; +- vccio-supply = <&vcc5v>; +- +- regulators { +- vrtc_reg: regulator@0 { +- regulator-always-on; +- }; +- +- vio_reg: regulator@1 { +- regulator-always-on; +- }; +- +- vdd1_reg: regulator@2 { +- /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */ +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <912500>; +- regulator-max-microvolt = <1378000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd2_reg: regulator@3 { +- /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <912500>; +- regulator-max-microvolt = <1150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd3_reg: regulator@4 { +- regulator-always-on; +- }; +- +- vdig1_reg: regulator@5 { +- regulator-name = "vdig1_1p8v"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vdig2_reg: regulator@6 { +- regulator-always-on; +- }; +- +- vpll_reg: regulator@7 { +- regulator-always-on; +- }; +- +- vdac_reg: regulator@8 { +- regulator-always-on; +- }; +- +- vaux1_reg: regulator@9 { +- regulator-always-on; +- }; +- +- vaux2_reg: regulator@10 { +- regulator-always-on; +- }; +- +- vaux33_reg: regulator@11 { +- regulator-always-on; +- }; +- +- vmmc_reg: regulator@12 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +-}; +- +-/* SPI Busses */ +-&am33xx_pinmux { +- spi0_pins: pinmux_spi0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins>; +- status = "okay"; +- +- serial_flash: m25p80@0 { +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <48000000>; +- reg = <0x0>; +- m25p,fast-read; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-pocketbeagle.dts b/scripts/dtc/include-prefixes/arm/am335x-pocketbeagle.dts +deleted file mode 100644 +index 209cdd17dc1e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-pocketbeagle.dts ++++ /dev/null +@@ -1,483 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * Author: Robert Nelson +- */ +-/dts-v1/; +- +-#include "am33xx.dtsi" +-#include "am335x-osd335x-common.dtsi" +- +-/ { +- model = "TI AM335x PocketBeagle"; +- compatible = "ti,am335x-pocketbeagle", "ti,am335x-bone", "ti,am33xx"; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&usr_leds_pins>; +- +- compatible = "gpio-leds"; +- +- usr0 { +- label = "beaglebone:green:usr0"; +- gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- +- usr1 { +- label = "beaglebone:green:usr1"; +- gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- +- usr2 { +- label = "beaglebone:green:usr2"; +- gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "cpu0"; +- default-state = "off"; +- }; +- +- usr3 { +- label = "beaglebone:green:usr3"; +- gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- vmmcsd_fixed: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsd_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&gpio0 { +- gpio-line-names = +- "NC", +- "NC", +- "P1.08 [SPI0_CLK]", +- "P1.10 [SPI0_MISO]", +- "P1.12 [SPI0_MOSI]", +- "P1.06 [SPI0_CS]", +- "[MMC0_CD]", +- "P2.29 [SPI1_CLK]", +- "[SYSBOOT 12]", +- "[SYSBOOT 13]", +- "[SYSBOOT 14]", +- "[SYSBOOT 15]", +- "P1.26 [I2C2_SDA]", +- "P1.28 [I2C2_SCL]", +- "P2.11 [I2C1_SDA]", +- "P2.09 [I2C1_SCL]", +- "NC", +- "NC", +- "NC", +- "P2.31 [SPI1_CS]", +- "P1.20 [PRU0.16]", +- "NC", +- "NC", +- "P2.03", +- "NC", +- "NC", +- "P1.34", +- "P2.19", +- "NC", +- "NC", +- "P2.05 [UART4_RX]", +- "P2.07 [UART4_TX]"; +-}; +- +-&gpio1 { +- gpio-line-names = +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "P2.25 [SPI1_MOSI]", +- "P1.32 [UART0_RX]", +- "P1.30 [UART0_TX]", +- "P2.24", +- "P2.33", +- "P2.22", +- "P2.18", +- "NC", +- "NC", +- "P2.01 [PWM1A]", +- "NC", +- "P2.10", +- "[USR LED 0]", +- "[USR LED 1]", +- "[USR LED 2]", +- "[USR LED 3]", +- "P2.06", +- "P2.04", +- "P2.02", +- "P2.08", +- "NC", +- "NC", +- "NC"; +-}; +- +-&gpio2 { +- gpio-line-names = +- "P2.20", +- "P2.17", +- "NC", +- "NC", +- "NC", +- "[EEPROM_WP]", +- "[SYSBOOT 0]", +- "[SYSBOOT 1]", +- "[SYSBOOT 2]", +- "[SYSBOOT 3]", +- "[SYSBOOT 4]", +- "[SYSBOOT 5]", +- "[SYSBOOT 6]", +- "[SYSBOOT 7]", +- "[SYSBOOT 8]", +- "[SYSBOOT 9]", +- "[SYSBOOT 10]", +- "[SYSBOOT 11]", +- "NC", +- "NC", +- "NC", +- "NC", +- "P2.35 [AIN5]", +- "P1.02 [AIN6]", +- "P1.35 [PRU1.10]", +- "P1.04 [PRU1.11]", +- "[MMC0_DAT3]", +- "[MMC0_DAT2]", +- "[MMC0_DAT1]", +- "[MMC0_DAT0]", +- "[MMC0_CLK]", +- "[MMC0_CMD]"; +-}; +- +-&gpio3 { +- gpio-line-names = +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "[I2C0_SDA]", +- "[I2C0_SCL]", +- "[JTAG EMU0]", +- "[JTAG EMU1]", +- "NC", +- "NC", +- "NC", +- "NC", +- "P1.03 [USB1]", +- "P1.36 [PWM0A]", +- "P1.33 [PRU0.1]", +- "P2.32 [PRU0.2]", +- "P2.30 [PRU0.3]", +- "P1.31 [PRU0.4]", +- "P2.34 [PRU0.5]", +- "P2.28 [PRU0.6]", +- "P1.29 [PRU0.7]", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC"; +-}; +- +-&am33xx_pinmux { +- +- pinctrl-names = "default"; +- +- pinctrl-0 = < &P2_03_gpio &P1_34_gpio &P2_19_gpio &P2_24_gpio +- &P2_33_gpio &P2_22_gpio &P2_18_gpio &P2_10_gpio +- &P2_06_gpio &P2_04_gpio &P2_02_gpio &P2_08_gpio +- &P2_17_gpio >; +- +- /* P2_03 (ZCZ ball T10) gpio0_23 0x824 PIN 9 */ +- P2_03_gpio: pinmux_P2_03_gpio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7) +- >; +- pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; +- pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; +- }; +- +- /* P1_34 (ZCZ ball T11) gpio0_26 0x828 PIN 10 */ +- P1_34_gpio: pinmux_P1_34_gpio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE7) +- >; +- pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; +- pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; +- }; +- +- /* P2_19 (ZCZ ball U12) gpio0_27 0x82c PIN 11 */ +- P2_19_gpio: pinmux_P2_19_gpio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE7) +- >; +- pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; +- pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; +- }; +- +- /* P2_24 (ZCZ ball T12) gpio1_12 0x830 PIN 12 */ +- P2_24_gpio: pinmux_P2_24_gpio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) +- >; +- pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; +- pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; +- }; +- +- /* P2_33 (ZCZ ball R12) gpio1_13 0x834 PIN 13 */ +- P2_33_gpio: pinmux_P2_33_gpio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) +- >; +- pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; +- pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; +- }; +- +- /* P2_22 (ZCZ ball V13) gpio1_14 0x838 PIN 14 */ +- P2_22_gpio: pinmux_P2_22_gpio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7) +- >; +- pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; +- pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; +- }; +- +- /* P2_18 (ZCZ ball U13) gpio1_15 0x83c PIN 15 */ +- P2_18_gpio: pinmux_P2_18_gpio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7) +- >; +- pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; +- pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; +- }; +- +- /* P2_10 (ZCZ ball R14) gpio1_20 0x850 PIN 20 */ +- P2_10_gpio: pinmux_P2_10_gpio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLUP, MUX_MODE7) +- >; +- pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; +- pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; +- }; +- +- /* P2_06 (ZCZ ball U16) gpio1_25 0x864 PIN 25 */ +- P2_06_gpio: pinmux_P2_06_gpio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7) +- >; +- pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; +- pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; +- }; +- +- /* P2_04 (ZCZ ball T16) gpio1_26 0x868 PIN 26 */ +- P2_04_gpio: pinmux_P2_04_gpio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE7) +- >; +- pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; +- pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; +- }; +- +- /* P2_02 (ZCZ ball V17) gpio1_27 0x86c PIN 27 */ +- P2_02_gpio: pinmux_P2_02_gpio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE7) +- >; +- pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; +- pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; +- }; +- +- /* P2_08 (ZCZ ball U18) gpio1_28 0x878 PIN 30 */ +- P2_08_gpio: pinmux_P2_08_gpio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- pinctrl-single,bias-pullup = < 0x00 0x10 0x00 0x18>; +- pinctrl-single,bias-pulldown = < 0x00 0x00 0x10 0x18>; +- }; +- +- /* P2_17 (ZCZ ball V12) gpio2_1 0x88c PIN 35 */ +- P2_17_gpio: pinmux_P2_17_gpio { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE7) +- >; +- pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; +- pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; +- }; +- +- i2c2_pins: pinmux-i2c2-pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ +- >; +- }; +- +- ehrpwm0_pins: pinmux-ehrpwm0-pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (A13) mcasp0_aclkx.ehrpwm0A */ +- >; +- }; +- +- ehrpwm1_pins: pinmux-ehrpwm1-pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* (U14) gpmc_a2.ehrpwm1A */ +- >; +- }; +- +- mmc0_pins: pinmux-mmc0-pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- spi0_pins: pinmux-spi0-pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- spi1_pins: pinmux-spi1-pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* (C18) eCAP0_in_PWM0_out.spi1_sclk */ +- AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* (E18) uart0_ctsn.spi1_d0 */ +- AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* (E17) uart0_rtsn.spi1_d1 */ +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE4) /* (A15) xdma_event_intr0.spi1_cs1 */ +- >; +- }; +- +- usr_leds_pins: pinmux-usr-leds-pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ +- >; +- }; +- +- uart0_pins: pinmux-uart0-pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- uart4_pins: pinmux-uart4-pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* (U17) gpmc_wpn.uart4_txd */ +- >; +- }; +-}; +- +-&epwmss0 { +- status = "okay"; +-}; +- +-&ehrpwm0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ehrpwm0_pins>; +-}; +- +-&epwmss1 { +- status = "okay"; +-}; +- +-&ehrpwm1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ehrpwm1_pins>; +-}; +- +-&i2c0 { +- eeprom: eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- +- status = "okay"; +- clock-frequency = <400000>; +-}; +- +-&mmc1 { +- status = "okay"; +- vmmc-supply = <&vmmcsd_fixed>; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +-}; +- +-&rtc { +- system-power-controller; +-}; +- +-&tscadc { +- status = "okay"; +- adc { +- ti,adc-channels = <0 1 2 3 4 5 6 7>; +- ti,chan-step-avg = <16 16 16 16 16 16 16 16>; +- ti,chan-step-opendelay = <0x98 0x98 0x98 0x98 0x98 0x98 0x98 0x98>; +- ti,chan-step-sampledelay = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pins>; +- +- status = "okay"; +-}; +- +-&usb0 { +- dr_mode = "otg"; +-}; +- +-&usb1 { +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-regor-rdk.dts b/scripts/dtc/include-prefixes/arm/am335x-regor-rdk.dts +deleted file mode 100644 +index 66a1360b83d5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-regor-rdk.dts ++++ /dev/null +@@ -1,24 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2019 Phytec Messtechnik GmbH +- * Author: Teresa Remmet +- * +- */ +- +-/dts-v1/; +- +-#include "am335x-phycore-som.dtsi" +-#include "am335x-regor.dtsi" +- +-/* SoM */ +-&gpmc { +- status = "okay"; +-}; +- +-&i2c_eeprom { +- status = "okay"; +-}; +- +-&serial_flash { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-regor.dtsi b/scripts/dtc/include-prefixes/arm/am335x-regor.dtsi +deleted file mode 100644 +index 7b3966ee51b9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-regor.dtsi ++++ /dev/null +@@ -1,201 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2019 Phytec Messtechnik GmbH +- * Author: Teresa Remmet +- * +- */ +- +-/ { +- model = "Phytec AM335x phyBOARD-REGOR"; +- compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx"; +- +- vcc3v3: fixedregulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- +- /* User IO */ +- user_leds: user_leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&user_leds_pins>; +- +- run_stop-led { +- gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "gpio"; +- default-state = "off"; +- }; +- +- error-led { +- gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "gpio"; +- default-state = "off"; +- }; +- }; +-}; +- +-/* User Leds */ +-&am33xx_pinmux { +- user_leds_pins: pinmux_user_leds { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_22 */ +- AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_fsx.gpio3_15 */ +- >; +- }; +-}; +- +-/* CAN Busses */ +-&am33xx_pinmux { +- dcan1_pins: pinmux_dcan1 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ +- AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ +- >; +- }; +-}; +- +-&dcan1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&dcan1_pins>; +- status = "okay"; +-}; +- +-/* Ethernet */ +-&am33xx_pinmux { +- ethernet1_pins: pinmux_ethernet1 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */ +- >; +- }; +-}; +- +-&cpsw_port2 { +- status = "okay"; +- phy-handle = <&phy1>; +- phy-mode = "mii"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&davinci_mdio_sw { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mac_sw { +- pinctrl-names = "default"; +- pinctrl-0 = <ðernet0_pins ðernet1_pins>; +-}; +- +-/* GPIOs */ +-&am33xx_pinmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&user_gpios_pins>; +- +- user_gpios_pins: pinmux_user_gpios { +- pinctrl-single,pins = < +- /* DIGIN 1-4 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT, MUX_MODE7) /* gpmc_ad11.gpio0_27 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT, MUX_MODE7) /* gpmc_ad9.gpio0_23 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT, MUX_MODE7) /* gpmc_ad8.gpio0_22 */ +- /* DIGOUT 1-4 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad15.gpio1_15 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad14.gpio1_14 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad13.gpio1_13 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad12.gpio1_12 */ +- >; +- }; +-}; +- +-/* MMC */ +-&am33xx_pinmux { +- mmc1_pins: pinmux_mmc1 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ +- >; +- }; +-}; +- +-&mmc1 { +- vmmc-supply = <&vcc3v3>; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-/* RTC */ +-&i2c_rtc { +- status = "okay"; +-}; +- +-/* UARTs */ +-&am33xx_pinmux { +- uart0_pins: pinmux_uart0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- uart2_pins: pinmux_uart2 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */ +- >; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "okay"; +-}; +- +-/* RS485 - UART1 */ +-&am33xx_pinmux { +- uart1_rs485_pins: pinmux_uart1_rs485_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLUP, MUX_MODE0) +- >; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_rs485_pins>; +- status = "okay"; +- linux,rs485-enabled-at-boot-time; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-sancloud-bbe-common.dtsi b/scripts/dtc/include-prefixes/arm/am335x-sancloud-bbe-common.dtsi +deleted file mode 100644 +index f9b7e774ac48..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-sancloud-bbe-common.dtsi ++++ /dev/null +@@ -1,67 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-&am33xx_pinmux { +- cpsw_default: cpsw_default { +- pinctrl-single,pins = < +- /* Slave 1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ +- >; +- }; +- +- cpsw_sleep: cpsw_sleep { +- pinctrl-single,pins = < +- /* Slave 1 reset value */ +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- usb_hub_ctrl: usb_hub_ctrl { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* rmii1_refclk.gpio0_29 */ +- >; +- }; +-}; +- +-&mac_sw { +- pinctrl-0 = <&cpsw_default>; +- pinctrl-1 = <&cpsw_sleep>; +-}; +- +-&cpsw_port1 { +- phy-mode = "rgmii-id"; +-}; +- +-&i2c0 { +- usb2512b: usb-hub@2c { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_hub_ctrl>; +- compatible = "microchip,usb2512b"; +- reg = <0x2c>; +- reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-sancloud-bbe-lite.dts b/scripts/dtc/include-prefixes/arm/am335x-sancloud-bbe-lite.dts +deleted file mode 100644 +index d6ef19311a91..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-sancloud-bbe-lite.dts ++++ /dev/null +@@ -1,50 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ +- * Copyright (C) 2021 SanCloud Ltd +- */ +-/dts-v1/; +- +-#include "am33xx.dtsi" +-#include "am335x-bone-common.dtsi" +-#include "am335x-boneblack-common.dtsi" +-#include "am335x-sancloud-bbe-common.dtsi" +- +-/ { +- model = "SanCloud BeagleBone Enhanced Lite"; +- compatible = "sancloud,am335x-boneenhanced", +- "ti,am335x-bone-black", +- "ti,am335x-bone", +- "ti,am33xx"; +-}; +- +-&am33xx_pinmux { +- bb_spi0_pins: pinmux_bb_spi0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE0) +- >; +- }; +-}; +- +-&spi0 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&bb_spi0_pins>; +- +- channel@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- compatible = "micron,spi-authenta"; +- +- reg = <0>; +- spi-max-frequency = <16000000>; +- spi-cpha; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-sancloud-bbe.dts b/scripts/dtc/include-prefixes/arm/am335x-sancloud-bbe.dts +deleted file mode 100644 +index efbe93135dbe..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-sancloud-bbe.dts ++++ /dev/null +@@ -1,53 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "am33xx.dtsi" +-#include "am335x-bone-common.dtsi" +-#include "am335x-boneblack-common.dtsi" +-#include "am335x-boneblack-hdmi.dtsi" +-#include "am335x-sancloud-bbe-common.dtsi" +-#include +- +-/ { +- model = "SanCloud BeagleBone Enhanced"; +- compatible = "sancloud,am335x-boneenhanced", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +-}; +- +-&am33xx_pinmux { +- mpu6050_pins: pinmux_mpu6050_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ +- >; +- }; +- +- lps3331ap_pins: pinmux_lps3331ap_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_26 */ +- >; +- }; +-}; +- +-&i2c0 { +- lps331ap: barometer@5c { +- pinctrl-names = "default"; +- pinctrl-0 = <&lps3331ap_pins>; +- compatible = "st,lps331ap-press"; +- st,drdy-int-pin = <1>; +- reg = <0x5c>; +- interrupt-parent = <&gpio1>; +- interrupts = <26 IRQ_TYPE_EDGE_RISING>; +- }; +- +- mpu6050: accelerometer@68 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mpu6050_pins>; +- compatible = "invensense,mpu6050"; +- reg = <0x68>; +- interrupt-parent = <&gpio0>; +- interrupts = <2 IRQ_TYPE_EDGE_RISING>; +- orientation = <0xff 0 0 0 1 0 0 0 0xff>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-sbc-t335.dts b/scripts/dtc/include-prefixes/arm/am335x-sbc-t335.dts +deleted file mode 100644 +index 81e4453687ba..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-sbc-t335.dts ++++ /dev/null +@@ -1,176 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * am335x-sbc-t335.dts - Device Tree file for Compulab SBC-T335 +- * +- * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/ +- */ +- +-#include "am335x-cm-t335.dts" +- +-/ { +- model = "CompuLab CM-T335 on SB-T335"; +- compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx"; +- +- /* DRM display driver */ +- panel { +- compatible = "ti,tilcdc,panel"; +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&lcd_pins_default>; +- pinctrl-1 = <&lcd_pins_sleep>; +- +- panel-info { +- ac-bias = <255>; +- ac-bias-intrpt = <0>; +- dma-burst-sz = <16>; +- bpp = <32>; +- fdd = <0x80>; +- sync-edge = <0>; +- sync-ctrl = <1>; +- raster-order = <0>; +- fifo-th = <0>; +- }; +- display-timings { +- /* Timing selection performed by U-Boot */ +- timing0: lcd {/* 800x480p62 */ +- clock-frequency = <30000000>; +- hactive = <800>; +- vactive = <480>; +- hfront-porch = <39>; +- hback-porch = <39>; +- hsync-len = <47>; +- vback-porch = <29>; +- vfront-porch = <13>; +- vsync-len = <2>; +- hsync-active = <1>; +- vsync-active = <1>; +- }; +- timing1: dvi { /* 1024x768p60 */ +- clock-frequency = <65000000>; +- hactive = <1024>; +- hfront-porch = <24>; +- hback-porch = <160>; +- hsync-len = <136>; +- vactive = <768>; +- vfront-porch = <3>; +- vback-porch = <29>; +- vsync-len = <6>; +- hsync-active = <0>; +- vsync-active = <0>; +- }; +- }; +- }; +-}; +- +-&am33xx_pinmux { +- /* Display */ +- lcd_pins_default: lcd_pins_default { +- pinctrl-single,pins = < +- /* gpmc_ad8.lcd_data23 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) +- /* gpmc_ad9.lcd_data22 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) +- /* gpmc_ad10.lcd_data21 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) +- /* gpmc_ad11.lcd_data20 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) +- /* gpmc_ad12.lcd_data19 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) +- /* gpmc_ad13.lcd_data18 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) +- /* gpmc_ad14.lcd_data17 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) +- /* gpmc_ad15.lcd_data16 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) +- >; +- }; +- +- lcd_pins_sleep: lcd_pins_sleep { +- pinctrl-single,pins = < +- /* gpmc_ad8.lcd_data23 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7) +- /* gpmc_ad9.lcd_data22 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7) +- /* gpmc_ad10.lcd_data21 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7) +- /* gpmc_ad11.lcd_data20 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) +- /* gpmc_ad12.lcd_data19 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) +- /* gpmc_ad13.lcd_data18 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) +- /* gpmc_ad14.lcd_data17 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) +- /* gpmc_ad15.lcd_data16 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +-}; +- +-&i2c0 { +- /* GPIO extender */ +- gpio_ext: pca9555@26 { +- compatible = "nxp,pca9555"; +- pinctrl-names = "default"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x26>; +- dvi-ena-hog { +- gpio-hog; +- gpios = <13 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "dvi-enable"; +- }; +- lcd-ena-hog { +- gpio-hog; +- gpios = <11 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "lcd-enable"; +- }; +- }; +-}; +- +-/* Display */ +-&lcdc { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-shc.dts b/scripts/dtc/include-prefixes/arm/am335x-shc.dts +deleted file mode 100644 +index 6b9877560741..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-shc.dts ++++ /dev/null +@@ -1,559 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * support for the bosch am335x based shc c3 board +- * +- * Copyright, C) 2015 Heiko Schocher +- * +- */ +-/dts-v1/; +- +-#include "am33xx.dtsi" +-#include +- +-/ { +- model = "Bosch SHC"; +- compatible = "ti,am335x-shc", "ti,am335x-bone", "ti,am33xx"; +- +- aliases { +- mmcblk0 = &mmc1; +- mmcblk1 = &mmc2; +- }; +- +- cpus { +- cpu@0 { +- /* +- * To consider voltage drop between PMIC and SoC, +- * tolerance value is reduced to 2% from 4% and +- * voltage value is increased as a precaution. +- */ +- operating-points = < +- /* kHz uV */ +- 594000 1225000 +- 294000 1125000 +- >; +- voltage-tolerance = <2>; /* 2 percentage */ +- cpu0-supply = <&dcdc2_reg>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- back_button { +- label = "Back Button"; +- gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- debounce-interval = <1000>; +- wakeup-source; +- }; +- +- front_button { +- label = "Front Button"; +- gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- debounce-interval = <1000>; +- wakeup-source; +- }; +- }; +- +- leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&user_leds_s0>; +- +- compatible = "gpio-leds"; +- +- led1 { +- label = "shc:power:red"; +- gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led2 { +- label = "shc:power:bl"; +- gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "timer"; +- default-state = "on"; +- }; +- +- led3 { +- label = "shc:lan:red"; +- gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led4 { +- label = "shc:lan:bl"; +- gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led5 { +- label = "shc:cloud:red"; +- gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led6 { +- label = "shc:cloud:bl"; +- gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512 MB */ +- }; +- +- vmmcsd_fixed: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsd_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&aes { +- status = "okay"; +-}; +- +-&epwmss1 { +- status = "okay"; +- +- ehrpwm1: pwm@200 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ehrpwm1_pins>; +- status = "okay"; +- }; +-}; +- +-&gpio1 { +- hmtc-rst-hog { +- gpio-hog; +- gpios = <24 GPIO_ACTIVE_LOW>; +- output-high; +- line-name = "homematic_reset"; +- }; +- +- hmtc-prog-hog { +- gpio-hog; +- gpios = <27 GPIO_ACTIVE_LOW>; +- output-high; +- line-name = "homematic_program"; +- }; +-}; +- +-&gpio3 { +- zgb-rst-hog { +- gpio-hog; +- gpios = <18 GPIO_ACTIVE_LOW>; +- output-low; +- line-name = "zigbee_reset"; +- }; +- +- zgb-boot-hog { +- gpio-hog; +- gpios = <19 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "zigbee_boot"; +- }; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +- clock-frequency = <400000>; +- +- tps: tps@24 { +- reg = <0x24>; +- }; +- +- at24@50 { +- compatible = "atmel,24c32"; +- pagesize = <32>; +- reg = <0x50>; +- }; +- +- pcf8563@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +-}; +- +-&mac_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&cpsw_default>; +- pinctrl-1 = <&cpsw_sleep>; +- status = "okay"; +-}; +- +-&cpsw_port1 { +- phy-mode = "mii"; +- phy-handle = <ðernetphy0>; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- status = "disabled"; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&davinci_mdio_default>; +- pinctrl-1 = <&davinci_mdio_sleep>; +- +- ethernetphy0: ethernet-phy@0 { +- reg = <0>; +- smsc,disable-energy-detect; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- bus-width = <0x4>; +- cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +- cd-inverted; +- max-frequency = <26000000>; +- vmmc-supply = <&vmmcsd_fixed>; +- status = "okay"; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_pins>; +- bus-width = <8>; +- max-frequency = <26000000>; +- sd-uhs-sdr25; +- vmmc-supply = <&vmmcsd_fixed>; +- status = "okay"; +-}; +- +-&mmc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc3_pins>; +- bus-width = <4>; +- cap-power-off-card; +- max-frequency = <26000000>; +- sd-uhs-sdr25; +- vmmc-supply = <&vmmcsd_fixed>; +- status = "okay"; +-}; +- +-&rtc { +- ti,no-init; +-}; +- +-&sham { +- status = "okay"; +-}; +- +-&tps { +- compatible = "ti,tps65217"; +- ti,pmic-shutdown-controller; +- +- regulators { +- #address-cells = <1>; +- #size-cells = <0>; +- +- dcdc1_reg: regulator@0 { +- reg = <0>; +- regulator-name = "vdds_dpr"; +- regulator-compatible = "dcdc1"; +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1450000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc2_reg: regulator@1 { +- reg = <1>; +- /* +- * VDD_MPU voltage limits 0.95V - 1.26V with +- * +/-4% tolerance +- */ +- regulator-compatible = "dcdc2"; +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <1375000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <70000>; +- }; +- +- dcdc3_reg: regulator@2 { +- reg = <2>; +- /* +- * VDD_CORE voltage limits 0.95V - 1.1V with +- * +/-4% tolerance +- */ +- regulator-name = "vdd_core"; +- regulator-compatible = "dcdc3"; +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <1125000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1_reg: regulator@3 { +- reg = <3>; +- regulator-name = "vio,vrtc,vdds"; +- regulator-compatible = "ldo1"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo2_reg: regulator@4 { +- reg = <4>; +- regulator-name = "vdd_3v3aux"; +- regulator-compatible = "ldo2"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo3_reg: regulator@5 { +- reg = <5>; +- regulator-name = "vdd_1v8"; +- regulator-compatible = "ldo3"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo4_reg: regulator@6 { +- reg = <6>; +- regulator-name = "vdd_3v3a"; +- regulator-compatible = "ldo4"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pins>; +- status = "okay"; +-}; +- +-&usb1 { +- dr_mode = "host"; +-}; +- +-&am33xx_pinmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&clkout2_pin>; +- +- clkout2_pin: pinmux_clkout2_pin { +- pinctrl-single,pins = < +- /* xdma_event_intr1.clkout2 */ +- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT, MUX_MODE6) +- >; +- }; +- +- cpsw_default: cpsw_default { +- pinctrl-single,pins = < +- /* Slave 1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- cpsw_sleep: cpsw_sleep { +- pinctrl-single,pins = < +- /* Slave 1 reset value */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- davinci_mdio_default: davinci_mdio_default { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- davinci_mdio_sleep: davinci_mdio_sleep { +- pinctrl-single,pins = < +- /* MDIO reset value */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- ehrpwm1_pins: pinmux_ehrpwm1 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.gpio1_19 */ +- >; +- }; +- +- emmc_pins: pinmux_emmc_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT, MUX_MODE2) +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) +- >; +- }; +- +- i2c0_pins: pinmux_i2c0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE5) +- >; +- }; +- +- mmc3_pins: pinmux_mmc3_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE3) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE3) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT, MUX_MODE3) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE3) +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT, MUX_MODE3) +- AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT, MUX_MODE3) +- >; +- }; +- +- uart0_pins: pinmux_uart0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0) +- >; +- }; +- +- uart1_pins: pinmux_uart1 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) +- >; +- }; +- +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) +- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) +- >; +- }; +- +- uart4_pins: pinmux_uart4_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) +- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE6) +- >; +- }; +- +- user_leds_s0: user_leds_s0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLUP, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLUP, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7) +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-sl50.dts b/scripts/dtc/include-prefixes/arm/am335x-sl50.dts +deleted file mode 100644 +index 6516907ed579..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-sl50.dts ++++ /dev/null +@@ -1,721 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/ +- */ +-/dts-v1/; +- +-#include "am33xx.dtsi" +-#include +-#include +- +-/ { +- model = "Toby Churchill SL50 Series"; +- compatible = "tcl,am335x-sl50", "ti,am33xx"; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&dcdc2_reg>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512 MB */ +- }; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins>; +- +- led0 { +- label = "sl50:red:usr0"; +- gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led1 { +- label = "sl50:green:usr1"; +- gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led2 { +- label = "sl50:red:usr2"; +- gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led3 { +- label = "sl50:green:usr3"; +- gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- backlight0: disp0 { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&backlight0_pins>; +- pwms = <&ehrpwm1 0 500000 PWM_POLARITY_INVERTED>; +- brightness-levels = < 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100>; +- default-brightness-level = <50>; +- enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; +- power-supply = <&vdd_sys_reg>; +- }; +- +- backlight1: disp1 { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&backlight1_pins>; +- pwms = <&ehrpwm1 1 500000 PWM_POLARITY_INVERTED>; +- brightness-levels = < 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100>; +- default-brightness-level = <50>; +- enable-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; +- power-supply = <&vdd_sys_reg>; +- }; +- +- clocks { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* audio external oscillator */ +- audio_mclk_fixed: oscillator@0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; /* 24.576MHz */ +- }; +- +- audio_mclk: audio_mclk_gate@0 { +- compatible = "gpio-gate-clock"; +- #clock-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&audio_mclk_pins>; +- clocks = <&audio_mclk_fixed>; +- enable-gpios = <&gpio1 27 0>; +- }; +- }; +- +- panel: lcd_panel { +- compatible = "ti,tilcdc,panel"; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_pins>; +- +- panel-info { +- ac-bias = <255>; +- ac-bias-intrpt = <0>; +- dma-burst-sz = <16>; +- bpp = <16>; +- fdd = <0x80>; +- tft-alt-mode = <0>; +- mono-8bit-mode = <0>; +- sync-edge = <0>; +- sync-ctrl = <1>; +- raster-order = <0>; +- fifo-th = <0>; +- }; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: 960x128 { +- clock-frequency = <18000000>; +- hactive = <960>; +- vactive = <272>; +- +- hback-porch = <40>; +- hfront-porch = <16>; +- hsync-len = <24>; +- hsync-active = <0>; +- +- vback-porch = <3>; +- vfront-porch = <8>; +- vsync-len = <4>; +- vsync-active = <0>; +- }; +- }; +- }; +- +- sound { +- compatible = "audio-graph-card"; +- label = "sound-card"; +- pinctrl-names = "default"; +- pinctrl-0 = <&audio_pa_pins>; +- +- widgets = "Headphone", "Headphone Jack", +- "Speaker", "Speaker External", +- "Line", "Line In", +- "Microphone", "Microphone Jack"; +- +- routing = "Headphone Jack", "HPLOUT", +- "Headphone Jack", "HPROUT", +- "Amplifier", "MONO_LOUT", +- "Speaker External", "Amplifier", +- "LINE1R", "Line In", +- "LINE1L", "Line In", +- "MIC3L", "Microphone Jack", +- "MIC3R", "Microphone Jack", +- "Microphone Jack", "Mic Bias"; +- +- dais = <&cpu_port>; +- +- pa-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; +- }; +- +- emmc_pwrseq: pwrseq@0 { +- compatible = "mmc-pwrseq-emmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_pwrseq_pins>; +- reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; +- }; +- +- vdd_sys_reg: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_sys_reg"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- vmmcsd_fixed: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsd_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&am33xx_pinmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&lwb_pins>; +- +- audio_pins: pinmux_audio_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) +- >; +- }; +- +- audio_pa_pins: pinmux_audio_pa_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLDOWN, MUX_MODE7) /* SoundPA_en - mcasp0_aclkr.gpio3_18 */ +- >; +- }; +- +- audio_mclk_pins: pinmux_audio_mclk_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */ +- >; +- }; +- +- backlight0_pins: pinmux_backlight0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7) /* gpmc_wen.gpio2_4 */ +- >; +- }; +- +- backlight1_pins: pinmux_backlight1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */ +- >; +- }; +- +- lcd_pins: pinmux_lcd_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- led_pins: pinmux_led_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* gpmc_a5.gpio1_21 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* gpmc_a6.gpio1_22 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* gpmc_a7.gpio1_23 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* gpmc_a8.gpio1_24 */ +- >; +- }; +- +- uart0_pins: pinmux_uart0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- uart1_pins: pinmux_uart1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- uart4_pins: pinmux_uart4_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* gpmc_wait0.uart4_rxd */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* gpmc_wpn.uart4_txd */ +- >; +- }; +- +- i2c0_pins: pinmux_i2c0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- i2c2_pins: pinmux_i2c2_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ +- >; +- }; +- +- cpsw_default: cpsw_default { +- pinctrl-single,pins = < +- /* Slave 1 */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) +- >; +- }; +- +- cpsw_sleep: cpsw_sleep { +- pinctrl-single,pins = < +- /* Slave 1 reset value */ +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- davinci_mdio_default: davinci_mdio_default { +- pinctrl-single,pins = < +- /* MDIO */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) +- /* Ethernet */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7) /* Ethernet_nRST - gpmc_ad14.gpio1_14 */ +- >; +- }; +- +- davinci_mdio_sleep: davinci_mdio_sleep { +- pinctrl-single,pins = < +- /* MDIO reset value */ +- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) +- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE7) /* uart0_rtsn.gpio1_9 */ +- >; +- }; +- +- emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a4.gpio1_20 */ +- >; +- }; +- +- emmc_pins: pinmux_emmc_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ +- >; +- }; +- +- ehrpwm1_pins: pinmux_ehrpwm1a_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE6) /* gpmc_a2.ehrpwm1a */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.ehrpwm1b */ +- >; +- }; +- +- rtc0_irq_pins: pinmux_rtc0_irq_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ad9.gpio0_23 */ +- >; +- }; +- +- spi0_pins: pinmux_spi0_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MOSI */ +- AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MISO */ +- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_CS0 (NBATTSS) */ +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_CS1 (FPGA_FLASH_NCS) */ +- >; +- }; +- +- lwb_pins: pinmux_lwb_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */ +- /* PDI Bus - Battery system */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */ +- /* FPGA */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE7) /* FPGA_DONE - gpmc_ad8.gpio0_22 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* FPGA_NRST - gpmc_a0.gpio1_16 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* FPGA_RUN - gpmc_a1.gpio1_17 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7) /* ENFPGA - gpmc_a9.gpio1_25 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* FPGA_PROGRAM - gpmc_a10.gpio1_26 */ +- >; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- +- clock-frequency = <400000>; +- +- tps: tps@24 { +- reg = <0x24>; +- }; +- +- rtc0: rtc@68 { +- compatible = "dallas,ds1339"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rtc0_irq_pins>; +- interrupt-parent = <&gpio0>; +- interrupts = <23 IRQ_TYPE_EDGE_FALLING>; /* gpio 23 */ +- wakeup-source; +- trickle-resistor-ohms = <2000>; +- reg = <0x68>; +- }; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- }; +- +- gpio_exp: mcp23017@20 { +- compatible = "microchip,mcp23017"; +- reg = <0x20>; +- }; +- +-}; +- +-&i2c2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- +- clock-frequency = <400000>; +- +- audio_codec: tlv320aic3106@1b { +- status = "okay"; +- compatible = "ti,tlv320aic3106"; +- #sound-dai-cells = <0>; +- reg = <0x1b>; +- ai3x-micbias-vg = <2>; /* 2.5V */ +- +- AVDD-supply = <&ldo4_reg>; +- IOVDD-supply = <&ldo4_reg>; +- DRVDD-supply = <&ldo4_reg>; +- DVDD-supply = <&ldo3_reg>; +- +- codec_port: port { +- codec_endpoint: endpoint { +- remote-endpoint = <&cpu_endpoint>; +- clocks = <&audio_mclk>; +- }; +- }; +- }; +- +- /* Ambient Light Sensor */ +- als: isl29023@44 { +- compatible = "isil,isl29023"; +- reg = <0x44>; +- }; +-}; +- +-&rtc { +- status = "disabled"; +-}; +- +-&usb0 { +- dr_mode = "otg"; +-}; +- +-&usb1 { +- dr_mode = "host"; +-}; +- +-&mmc1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- bus-width = <4>; +- cd-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- vmmc-supply = <&vmmcsd_fixed>; +-}; +- +-&mmc2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_pins>; +- bus-width = <8>; +- vmmc-supply = <&vmmcsd_fixed>; +- mmc-pwrseq = <&emmc_pwrseq>; +-}; +- +-&mcasp0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&audio_pins>; +- #sound-dai-cells = <0>; +- op-mode = <0>; /* MCASP_ISS_MODE */ +- tdm-slots = <2>; +- /* 4 serializers */ +- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ +- 0 0 1 2 +- >; +- tx-num-evt = <32>; +- rx-num-evt = <32>; +- +- cpu_port: port { +- cpu_endpoint: endpoint { +- remote-endpoint = <&codec_endpoint>; +- +- dai-format = "dsp_b"; +- bitclock-master = <&codec_port>; +- frame-master = <&codec_port>; +- bitclock-inversion; +- clocks = <&audio_mclk>; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +-}; +- +-&uart1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +-}; +- +-&uart4 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pins>; +-}; +- +-&spi0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins>; +- +- flash: n25q032@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q032"; +- reg = <1>; +- spi-max-frequency = <5000000>; +- }; +-}; +- +-#include "tps65217.dtsi" +- +-&tps { +- ti,pmic-shutdown-controller; +- +- interrupt-parent = <&intc>; +- interrupts = <7>; /* NNMI */ +- +- regulators { +- dcdc1_reg: regulator@0 { +- /* VDDS_DDR */ +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- +- dcdc2_reg: regulator@1 { +- /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <1325000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc3_reg: regulator@2 { +- /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <1150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1_reg: regulator@3 { +- /* VRTC / VIO / VDDS*/ +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo2_reg: regulator@4 { +- /* VDD_3V3AUX */ +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo3_reg: regulator@5 { +- /* VDD_1V8 */ +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo4_reg: regulator@6 { +- /* VDD_3V3A */ +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +-}; +- +-&cpsw_port1 { +- phy-mode = "mii"; +- phy-handle = <ðphy0>; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- status = "disabled"; +-}; +- +-&mac_sw { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&cpsw_default>; +- pinctrl-1 = <&cpsw_sleep>; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&davinci_mdio_default>; +- pinctrl-1 = <&davinci_mdio_sleep>; +- reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- reset-delay-us = <100>; /* PHY datasheet states 100us min */ +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&sham { +- status = "okay"; +-}; +- +-&aes { +- status = "okay"; +-}; +- +-&epwmss1 { +- status = "okay"; +-}; +- +-&ehrpwm1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ehrpwm1_pins>; +-}; +- +-&lcdc { +- status = "okay"; +-}; +- +-&tscadc { +- status = "okay"; +-}; +- +-&am335x_adc { +- ti,adc-channels = <0 1 2 3 4 5 6 7>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-wega-rdk.dts b/scripts/dtc/include-prefixes/arm/am335x-wega-rdk.dts +deleted file mode 100644 +index 866b5f0cbfbc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-wega-rdk.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 Phytec Messtechnik GmbH +- * Author: Teresa Remmet +- */ +- +-/dts-v1/; +- +-#include "am335x-phycore-som.dtsi" +-#include "am335x-wega.dtsi" +- +-/* SoM */ +-&gpmc { +- status = "okay"; +-}; +- +-&i2c_eeprom { +- status = "okay"; +-}; +- +-&i2c_rtc { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am335x-wega.dtsi b/scripts/dtc/include-prefixes/arm/am335x-wega.dtsi +deleted file mode 100644 +index 673159d93a6a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am335x-wega.dtsi ++++ /dev/null +@@ -1,195 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 Phytec Messtechnik GmbH +- * Author: Teresa Remmet +- */ +- +-/ { +- model = "Phytec AM335x phyBOARD-WEGA"; +- compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"; +- +- sound: sound_iface { +- compatible = "ti,da830-evm-audio"; +- }; +- +- vcc3v3: fixedregulator1 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +-}; +- +-/* Audio */ +-&am33xx_pinmux { +- mcasp0_pins: pinmux_mcasp0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +-}; +- +-&i2c0 { +- tlv320aic3007: tlv320aic3007@18 { +- compatible = "ti,tlv320aic3007"; +- reg = <0x18>; +- AVDD-supply = <&vcc3v3>; +- IOVDD-supply = <&vcc3v3>; +- DRVDD-supply = <&vcc3v3>; +- DVDD-supply = <&vdig1_reg>; +- status = "okay"; +- }; +-}; +- +-&mcasp0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcasp0_pins>; +- op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ +- tdm-slots = <2>; +- serial-dir = < +- 2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */ +- >; +- tx-num-evt = <16>; +- rt-num-evt = <16>; +- status = "okay"; +-}; +- +-&sound { +- ti,model = "AM335x-Wega"; +- ti,audio-codec = <&tlv320aic3007>; +- ti,mcasp-controller = <&mcasp0>; +- ti,audio-routing = +- "Line Out", "LLOUT", +- "Line Out", "RLOUT", +- "LINE1L", "Line In", +- "LINE1R", "Line In"; +- clocks = <&mcasp0_fck>; +- clock-names = "mclk"; +- status = "okay"; +-}; +- +-/* CAN Busses */ +-&am33xx_pinmux { +- dcan1_pins: pinmux_dcan1 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ +- AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ +- >; +- }; +-}; +- +-&dcan1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&dcan1_pins>; +- status = "okay"; +-}; +- +-/* Ethernet */ +-&am33xx_pinmux { +- ethernet1_pins: pinmux_ethernet1 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ +- AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */ +- >; +- }; +-}; +- +-&cpsw_port2 { +- status = "okay"; +- phy-handle = <&phy1>; +- phy-mode = "mii"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&davinci_mdio_sw { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mac_sw { +- pinctrl-names = "default"; +- pinctrl-0 = <ðernet0_pins ðernet1_pins>; +-}; +- +-/* MMC */ +-&am33xx_pinmux { +- mmc1_pins: pinmux_mmc1 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ +- >; +- }; +-}; +- +-&mmc1 { +- vmmc-supply = <&vcc3v3>; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-/* Power */ +-&vdig1_reg { +- regulator-boot-on; +- regulator-always-on; +-}; +- +-/* UARTs */ +-&am33xx_pinmux { +- uart0_pins: pinmux_uart0 { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +- +- uart1_pins: pinmux_uart1_pins { +- pinctrl-single,pins = < +- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) +- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) +- >; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- status = "okay"; +-}; +- +-&usb1 { +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am33xx-clocks.dtsi b/scripts/dtc/include-prefixes/arm/am33xx-clocks.dtsi +deleted file mode 100644 +index b7b7106f2dee..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am33xx-clocks.dtsi ++++ /dev/null +@@ -1,676 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for AM33xx clock data +- * +- * Copyright (C) 2013 Texas Instruments, Inc. +- */ +-&scm_clocks { +- sys_clkin_ck: sys_clkin_ck@40 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; +- ti,bit-shift = <22>; +- reg = <0x0040>; +- }; +- +- adc_tsc_fck: adc_tsc_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dcan0_fck: dcan0_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dcan1_fck: dcan1_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- mcasp0_fck: mcasp0_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- mcasp1_fck: mcasp1_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- smartreflex0_fck: smartreflex0_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- smartreflex1_fck: smartreflex1_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- sha0_fck: sha0_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- aes0_fck: aes0_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- rng_fck: rng_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&l4ls_gclk>; +- ti,bit-shift = <0>; +- reg = <0x0664>; +- }; +- +- ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&l4ls_gclk>; +- ti,bit-shift = <1>; +- reg = <0x0664>; +- }; +- +- ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&l4ls_gclk>; +- ti,bit-shift = <2>; +- reg = <0x0664>; +- }; +-}; +-&prcm_clocks { +- clk_32768_ck: clk_32768_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- clk_rc32k_ck: clk_rc32k_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32000>; +- }; +- +- virt_19200000_ck: virt_19200000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <19200000>; +- }; +- +- virt_24000000_ck: virt_24000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- virt_25000000_ck: virt_25000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25000000>; +- }; +- +- virt_26000000_ck: virt_26000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- }; +- +- tclkin_ck: tclkin_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <12000000>; +- }; +- +- dpll_core_ck: dpll_core_ck@490 { +- #clock-cells = <0>; +- compatible = "ti,am3-dpll-core-clock"; +- clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; +- reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>; +- }; +- +- dpll_core_x2_ck: dpll_core_x2_ck { +- #clock-cells = <0>; +- compatible = "ti,am3-dpll-x2-clock"; +- clocks = <&dpll_core_ck>; +- }; +- +- dpll_core_m4_ck: dpll_core_m4_ck@480 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <31>; +- reg = <0x0480>; +- ti,index-starts-at-one; +- }; +- +- dpll_core_m5_ck: dpll_core_m5_ck@484 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <31>; +- reg = <0x0484>; +- ti,index-starts-at-one; +- }; +- +- dpll_core_m6_ck: dpll_core_m6_ck@4d8 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <31>; +- reg = <0x04d8>; +- ti,index-starts-at-one; +- }; +- +- dpll_mpu_ck: dpll_mpu_ck@488 { +- #clock-cells = <0>; +- compatible = "ti,am3-dpll-clock"; +- clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; +- reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>; +- }; +- +- dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_mpu_ck>; +- ti,max-div = <31>; +- reg = <0x04a8>; +- ti,index-starts-at-one; +- }; +- +- dpll_ddr_ck: dpll_ddr_ck@494 { +- #clock-cells = <0>; +- compatible = "ti,am3-dpll-no-gate-clock"; +- clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; +- reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>; +- }; +- +- dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_ddr_ck>; +- ti,max-div = <31>; +- reg = <0x04a0>; +- ti,index-starts-at-one; +- }; +- +- dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_ddr_m2_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- dpll_disp_ck: dpll_disp_ck@498 { +- #clock-cells = <0>; +- compatible = "ti,am3-dpll-no-gate-clock"; +- clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; +- reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; +- }; +- +- dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_disp_ck>; +- ti,max-div = <31>; +- reg = <0x04a4>; +- ti,index-starts-at-one; +- ti,set-rate-parent; +- }; +- +- dpll_per_ck: dpll_per_ck@48c { +- #clock-cells = <0>; +- compatible = "ti,am3-dpll-no-gate-j-type-clock"; +- clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; +- reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>; +- }; +- +- dpll_per_m2_ck: dpll_per_m2_ck@4ac { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_ck>; +- ti,max-div = <31>; +- reg = <0x04ac>; +- ti,index-starts-at-one; +- }; +- +- dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2_ck>; +- clock-mult = <1>; +- clock-div = <4>; +- }; +- +- dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2_ck>; +- clock-mult = <1>; +- clock-div = <4>; +- }; +- +- clk_24mhz: clk_24mhz { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2_ck>; +- clock-mult = <1>; +- clock-div = <8>; +- }; +- +- clkdiv32k_ck: clkdiv32k_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&clk_24mhz>; +- clock-mult = <1>; +- clock-div = <732>; +- }; +- +- l3_gclk: l3_gclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_m4_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- pruss_ocp_gclk: pruss_ocp_gclk@530 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; +- reg = <0x0530>; +- }; +- +- mmu_fck: mmu_fck@914 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&dpll_core_m4_ck>; +- ti,bit-shift = <1>; +- reg = <0x0914>; +- }; +- +- timer1_fck: timer1_fck@528 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; +- reg = <0x0528>; +- }; +- +- timer2_fck: timer2_fck@508 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; +- reg = <0x0508>; +- }; +- +- timer3_fck: timer3_fck@50c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; +- reg = <0x050c>; +- }; +- +- timer4_fck: timer4_fck@510 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; +- reg = <0x0510>; +- }; +- +- timer5_fck: timer5_fck@518 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; +- reg = <0x0518>; +- }; +- +- timer6_fck: timer6_fck@51c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; +- reg = <0x051c>; +- }; +- +- timer7_fck: timer7_fck@504 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; +- reg = <0x0504>; +- }; +- +- usbotg_fck: usbotg_fck@47c { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&dpll_per_ck>; +- ti,bit-shift = <8>; +- reg = <0x047c>; +- }; +- +- dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_m4_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- ieee5000_fck: ieee5000_fck@e4 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&dpll_core_m4_div2_ck>; +- ti,bit-shift = <1>; +- reg = <0x00e4>; +- }; +- +- wdt1_fck: wdt1_fck@538 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; +- reg = <0x0538>; +- }; +- +- l4_rtc_gclk: l4_rtc_gclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_m4_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- l4hs_gclk: l4hs_gclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_m4_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- l3s_gclk: l3s_gclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_m4_div2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- l4fw_gclk: l4fw_gclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_m4_div2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- l4ls_gclk: l4ls_gclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_m4_div2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- sysclk_div_ck: sysclk_div_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_m4_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- cpsw_125mhz_gclk: cpsw_125mhz_gclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_m5_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; +- reg = <0x0520>; +- }; +- +- gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; +- reg = <0x053c>; +- }; +- +- lcd_gclk: lcd_gclk@534 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; +- reg = <0x0534>; +- ti,set-rate-parent; +- }; +- +- mmc_clk: mmc_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; +- ti,bit-shift = <1>; +- reg = <0x052c>; +- }; +- +- gfx_fck_div_ck: gfx_fck_div_ck@52c { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&gfx_fclk_clksel_ck>; +- reg = <0x052c>; +- ti,max-div = <2>; +- }; +- +- sysclkout_pre_ck: sysclkout_pre_ck@700 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; +- reg = <0x0700>; +- }; +- +- clkout2_div_ck: clkout2_div_ck@700 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&sysclkout_pre_ck>; +- ti,bit-shift = <3>; +- ti,max-div = <8>; +- reg = <0x0700>; +- }; +- +- clkout2_ck: clkout2_ck@700 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&clkout2_div_ck>; +- ti,bit-shift = <7>; +- reg = <0x0700>; +- }; +-}; +- +-&prcm { +- per_cm: per-cm@0 { +- compatible = "ti,omap4-cm"; +- reg = <0x0 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x0 0x400>; +- +- l4ls_clkctrl: l4ls-clkctrl@38 { +- compatible = "ti,clkctrl"; +- reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>; +- #clock-cells = <2>; +- }; +- +- l3s_clkctrl: l3s-clkctrl@1c { +- compatible = "ti,clkctrl"; +- reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>; +- #clock-cells = <2>; +- }; +- +- l3_clkctrl: l3-clkctrl@24 { +- compatible = "ti,clkctrl"; +- reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>; +- #clock-cells = <2>; +- }; +- +- l4hs_clkctrl: l4hs-clkctrl@120 { +- compatible = "ti,clkctrl"; +- reg = <0x120 0x4>; +- #clock-cells = <2>; +- }; +- +- pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 { +- compatible = "ti,clkctrl"; +- reg = <0xe8 0x4>; +- #clock-cells = <2>; +- }; +- +- cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 { +- compatible = "ti,clkctrl"; +- reg = <0x0 0x18>; +- #clock-cells = <2>; +- }; +- +- lcdc_clkctrl: lcdc-clkctrl@18 { +- compatible = "ti,clkctrl"; +- reg = <0x18 0x4>; +- #clock-cells = <2>; +- }; +- +- clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c { +- compatible = "ti,clkctrl"; +- reg = <0x14c 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- wkup_cm: wkup-cm@400 { +- compatible = "ti,omap4-cm"; +- reg = <0x400 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x400 0x100>; +- +- l4_wkup_clkctrl: l4-wkup-clkctrl@0 { +- compatible = "ti,clkctrl"; +- reg = <0x0 0x10>, <0xb4 0x24>; +- #clock-cells = <2>; +- }; +- +- l3_aon_clkctrl: l3-aon-clkctrl@14 { +- compatible = "ti,clkctrl"; +- reg = <0x14 0x4>; +- #clock-cells = <2>; +- }; +- +- l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 { +- compatible = "ti,clkctrl"; +- reg = <0xb0 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- mpu_cm: mpu-cm@600 { +- compatible = "ti,omap4-cm"; +- reg = <0x600 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x600 0x100>; +- +- mpu_clkctrl: mpu-clkctrl@0 { +- compatible = "ti,clkctrl"; +- reg = <0x0 0x8>; +- #clock-cells = <2>; +- }; +- }; +- +- l4_rtc_cm: l4-rtc-cm@800 { +- compatible = "ti,omap4-cm"; +- reg = <0x800 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x800 0x100>; +- +- l4_rtc_clkctrl: l4-rtc-clkctrl@0 { +- compatible = "ti,clkctrl"; +- reg = <0x0 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- gfx_l3_cm: gfx-l3-cm@900 { +- compatible = "ti,omap4-cm"; +- reg = <0x900 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x900 0x100>; +- +- gfx_l3_clkctrl: gfx-l3-clkctrl@0 { +- compatible = "ti,clkctrl"; +- reg = <0x0 0x8>; +- #clock-cells = <2>; +- }; +- }; +- +- l4_cefuse_cm: l4-cefuse-cm@a00 { +- compatible = "ti,omap4-cm"; +- reg = <0xa00 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xa00 0x100>; +- +- l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 { +- compatible = "ti,clkctrl"; +- reg = <0x0 0x24>; +- #clock-cells = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am33xx-l4.dtsi b/scripts/dtc/include-prefixes/arm/am33xx-l4.dtsi +deleted file mode 100644 +index c9629cb5ccd1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am33xx-l4.dtsi ++++ /dev/null +@@ -1,2321 +0,0 @@ +-&l4_wkup { /* 0x44c00000 */ +- compatible = "ti,am33xx-l4-wkup", "simple-pm-bus"; +- power-domains = <&prm_wkup>; +- clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>; +- clock-names = "fck"; +- reg = <0x44c00000 0x800>, +- <0x44c00800 0x800>, +- <0x44c01000 0x400>, +- <0x44c01400 0x400>; +- reg-names = "ap", "la", "ia0", "ia1"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ +- <0x00100000 0x44d00000 0x100000>, /* segment 1 */ +- <0x00200000 0x44e00000 0x100000>; /* segment 2 */ +- +- segment@0 { /* 0x44c00000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ +- <0x00000800 0x00000800 0x000800>, /* ap 1 */ +- <0x00001000 0x00001000 0x000400>, /* ap 2 */ +- <0x00001400 0x00001400 0x000400>; /* ap 3 */ +- }; +- +- segment@100000 { /* 0x44d00000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ +- <0x00004000 0x00104000 0x001000>, /* ap 5 */ +- <0x00080000 0x00180000 0x002000>, /* ap 6 */ +- <0x00082000 0x00182000 0x001000>; /* ap 7 */ +- +- target-module@0 { /* 0x44d00000, ap 4 28.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x0 0x4>; +- reg-names = "rev"; +- clocks = <&l4_wkup_aon_clkctrl AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x4000>, +- <0x00080000 0x00080000 0x2000>; +- +- wkup_m3: cpu@0 { +- compatible = "ti,am3352-wkup-m3"; +- reg = <0x00000000 0x4000>, +- <0x00080000 0x2000>; +- reg-names = "umem", "dmem"; +- resets = <&prm_wkup 3>; +- reset-names = "rstctrl"; +- ti,pm-firmware = "am335x-pm-firmware.elf"; +- }; +- }; +- }; +- +- segment@200000 { /* 0x44e00000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */ +- <0x00002000 0x00202000 0x001000>, /* ap 9 */ +- <0x00003000 0x00203000 0x001000>, /* ap 10 */ +- <0x00004000 0x00204000 0x001000>, /* ap 11 */ +- <0x00005000 0x00205000 0x001000>, /* ap 12 */ +- <0x00006000 0x00206000 0x001000>, /* ap 13 */ +- <0x00007000 0x00207000 0x001000>, /* ap 14 */ +- <0x00008000 0x00208000 0x001000>, /* ap 15 */ +- <0x00009000 0x00209000 0x001000>, /* ap 16 */ +- <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ +- <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ +- <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ +- <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ +- <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ +- <0x00010000 0x00210000 0x010000>, /* ap 22 */ +- <0x00020000 0x00220000 0x010000>, /* ap 23 */ +- <0x00030000 0x00230000 0x001000>, /* ap 24 */ +- <0x00031000 0x00231000 0x001000>, /* ap 25 */ +- <0x00032000 0x00232000 0x001000>, /* ap 26 */ +- <0x00033000 0x00233000 0x001000>, /* ap 27 */ +- <0x00034000 0x00234000 0x001000>, /* ap 28 */ +- <0x00035000 0x00235000 0x001000>, /* ap 29 */ +- <0x00036000 0x00236000 0x001000>, /* ap 30 */ +- <0x00037000 0x00237000 0x001000>, /* ap 31 */ +- <0x00038000 0x00238000 0x001000>, /* ap 32 */ +- <0x00039000 0x00239000 0x001000>, /* ap 33 */ +- <0x0003a000 0x0023a000 0x001000>, /* ap 34 */ +- <0x0003e000 0x0023e000 0x001000>, /* ap 35 */ +- <0x0003f000 0x0023f000 0x001000>, /* ap 36 */ +- <0x0000e000 0x0020e000 0x001000>, /* ap 37 */ +- <0x00040000 0x00240000 0x040000>, /* ap 38 */ +- <0x00080000 0x00280000 0x001000>; /* ap 39 */ +- +- target-module@0 { /* 0x44e00000, ap 8 58.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0 0x4>; +- reg-names = "rev"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x2000>; +- +- prcm: prcm@0 { +- compatible = "ti,am3-prcm", "simple-bus"; +- reg = <0 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x2000>; +- +- prcm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- prcm_clockdomains: clockdomains { +- }; +- }; +- }; +- +- target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3000 0x1000>; +- }; +- +- target-module@5000 { /* 0x44e05000, ap 12 30.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5000 0x1000>; +- }; +- +- gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x7000 0x4>, +- <0x7010 0x4>, +- <0x7114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ +- clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>, +- <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x7000 0x1000>; +- +- gpio0: gpio@0 { +- compatible = "ti,omap4-gpio"; +- gpio-ranges = <&am33xx_pinmux 0 82 8>, +- <&am33xx_pinmux 8 52 4>, +- <&am33xx_pinmux 12 94 4>, +- <&am33xx_pinmux 16 71 2>, +- <&am33xx_pinmux 18 135 1>, +- <&am33xx_pinmux 19 108 2>, +- <&am33xx_pinmux 21 73 1>, +- <&am33xx_pinmux 22 8 2>, +- <&am33xx_pinmux 26 10 2>, +- <&am33xx_pinmux 28 74 1>, +- <&am33xx_pinmux 29 81 1>, +- <&am33xx_pinmux 30 28 2>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x0 0x1000>; +- interrupts = <96>; +- }; +- }; +- +- target-module@9000 { /* 0x44e09000, ap 16 04.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x9050 0x4>, +- <0x9054 0x4>, +- <0x9058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ +- clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x9000 0x1000>; +- +- uart0: serial@0 { +- compatible = "ti,am3352-uart", "ti,omap3-uart"; +- clock-frequency = <48000000>; +- reg = <0x0 0x1000>; +- interrupts = <72>; +- status = "disabled"; +- dmas = <&edma 26 0>, <&edma 27 0>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xb000 0x8>, +- <0xb010 0x8>, +- <0xb090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ +- clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xb000 0x1000>; +- +- i2c0: i2c@0 { +- compatible = "ti,omap4-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x1000>; +- interrupts = <70>; +- status = "disabled"; +- }; +- }; +- +- target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xd000 0x4>, +- <0xd010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ +- clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x0000d000 0x00001000>, +- <0x00001000 0x0000e000 0x00001000>; +- +- tscadc: tscadc@0 { +- compatible = "ti,am3359-tscadc"; +- reg = <0x0 0x1000>; +- interrupts = <16>; +- status = "disabled"; +- dmas = <&edma 53 0>, <&edma 57 0>; +- dma-names = "fifo0", "fifo1"; +- +- tsc { +- compatible = "ti,am3359-tsc"; +- }; +- am335x_adc: adc { +- #io-channel-cells = <1>; +- compatible = "ti,am3359-adc"; +- }; +- }; +- }; +- +- target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x10000 0x4>; +- reg-names = "rev"; +- clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_CONTROL_CLKCTRL 0>; +- clock-names = "fck"; +- ti,no-idle; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00010000 0x00010000>, +- <0x00010000 0x00020000 0x00010000>; +- +- scm: scm@0 { +- compatible = "ti,am3-scm", "simple-bus"; +- reg = <0x0 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- #pinctrl-cells = <1>; +- ranges = <0 0 0x2000>; +- +- am33xx_pinmux: pinmux@800 { +- compatible = "pinctrl-single"; +- reg = <0x800 0x238>; +- #pinctrl-cells = <2>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0x7f>; +- }; +- +- scm_conf: scm_conf@0 { +- compatible = "syscon", "simple-bus"; +- reg = <0x0 0x800>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x800>; +- +- phy_gmii_sel: phy-gmii-sel { +- compatible = "ti,am3352-phy-gmii-sel"; +- reg = <0x650 0x4>; +- #phy-cells = <2>; +- }; +- +- scm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- usb_ctrl_mod: control@620 { +- compatible = "ti,am335x-usb-ctrl-module"; +- reg = <0x620 0x10>, +- <0x648 0x4>; +- reg-names = "phy_ctrl", "wakeup"; +- }; +- +- wkup_m3_ipc: wkup_m3_ipc@1324 { +- compatible = "ti,am3352-wkup-m3-ipc"; +- reg = <0x1324 0x24>; +- interrupts = <78>; +- ti,rproc = <&wkup_m3>; +- mboxes = <&mailbox &mbox_wkupm3>; +- }; +- +- edma_xbar: dma-router@f90 { +- compatible = "ti,am335x-edma-crossbar"; +- reg = <0xf90 0x40>; +- #dma-cells = <3>; +- dma-requests = <32>; +- dma-masters = <&edma>; +- }; +- +- scm_clockdomains: clockdomains { +- }; +- }; +- }; +- +- timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */ +- compatible = "ti,sysc-omap2-timer", "ti,sysc"; +- reg = <0x31000 0x4>, +- <0x31010 0x4>, +- <0x31014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ +- clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x31000 0x1000>; +- +- timer1: timer@0 { +- compatible = "ti,am335x-timer-1ms"; +- reg = <0x0 0x400>; +- interrupts = <67>; +- ti,timer-alwon; +- clocks = <&timer1_fck>; +- clock-names = "fck"; +- }; +- }; +- +- target-module@33000 { /* 0x44e33000, ap 27 18.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x33000 0x1000>; +- }; +- +- target-module@35000 { /* 0x44e35000, ap 29 50.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x35000 0x4>, +- <0x35010 0x4>, +- <0x35014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ +- clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x35000 0x1000>; +- +- wdt2: wdt@0 { +- compatible = "ti,omap3-wdt"; +- reg = <0x0 0x1000>; +- interrupts = <91>; +- }; +- }; +- +- target-module@37000 { /* 0x44e37000, ap 31 08.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x37000 0x1000>; +- }; +- +- target-module@39000 { /* 0x44e39000, ap 33 02.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x39000 0x1000>; +- }; +- +- target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */ +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- reg = <0x3e074 0x4>, +- <0x3e078 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ +- power-domains = <&prm_rtc>; +- clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3e000 0x1000>; +- +- rtc: rtc@0 { +- compatible = "ti,am3352-rtc", "ti,da830-rtc"; +- reg = <0x0 0x1000>; +- interrupts = <75 +- 76>; +- }; +- }; +- +- target-module@40000 { /* 0x44e40000, ap 38 68.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x40000 0x40000>; +- }; +- }; +-}; +- +-&l4_fw { /* 0x47c00000 */ +- compatible = "ti,am33xx-l4-fw", "simple-bus"; +- reg = <0x47c00000 0x800>, +- <0x47c00800 0x800>, +- <0x47c01000 0x400>; +- reg-names = "ap", "la", "ia0"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */ +- +- segment@0 { /* 0x47c00000 */ +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ +- <0x00000800 0x00000800 0x000800>, /* ap 1 */ +- <0x00001000 0x00001000 0x000400>, /* ap 2 */ +- <0x0000c000 0x0000c000 0x001000>, /* ap 3 */ +- <0x0000d000 0x0000d000 0x001000>, /* ap 4 */ +- <0x0000e000 0x0000e000 0x001000>, /* ap 5 */ +- <0x0000f000 0x0000f000 0x001000>, /* ap 6 */ +- <0x00010000 0x00010000 0x001000>, /* ap 7 */ +- <0x00011000 0x00011000 0x001000>, /* ap 8 */ +- <0x0001a000 0x0001a000 0x001000>, /* ap 9 */ +- <0x0001b000 0x0001b000 0x001000>, /* ap 10 */ +- <0x00024000 0x00024000 0x001000>, /* ap 11 */ +- <0x00025000 0x00025000 0x001000>, /* ap 12 */ +- <0x00026000 0x00026000 0x001000>, /* ap 13 */ +- <0x00027000 0x00027000 0x001000>, /* ap 14 */ +- <0x00030000 0x00030000 0x001000>, /* ap 15 */ +- <0x00031000 0x00031000 0x001000>, /* ap 16 */ +- <0x00038000 0x00038000 0x001000>, /* ap 17 */ +- <0x00039000 0x00039000 0x001000>, /* ap 18 */ +- <0x0003a000 0x0003a000 0x001000>, /* ap 19 */ +- <0x0003b000 0x0003b000 0x001000>, /* ap 20 */ +- <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ +- <0x0003f000 0x0003f000 0x001000>, /* ap 22 */ +- <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ +- <0x00040000 0x00040000 0x001000>, /* ap 24 */ +- <0x00046000 0x00046000 0x001000>, /* ap 25 */ +- <0x00047000 0x00047000 0x001000>, /* ap 26 */ +- <0x00044000 0x00044000 0x001000>, /* ap 27 */ +- <0x00045000 0x00045000 0x001000>, /* ap 28 */ +- <0x00028000 0x00028000 0x001000>, /* ap 29 */ +- <0x00029000 0x00029000 0x001000>, /* ap 30 */ +- <0x00032000 0x00032000 0x001000>, /* ap 31 */ +- <0x00033000 0x00033000 0x001000>, /* ap 32 */ +- <0x0003d000 0x0003d000 0x001000>, /* ap 33 */ +- <0x00041000 0x00041000 0x001000>, /* ap 34 */ +- <0x00042000 0x00042000 0x001000>, /* ap 35 */ +- <0x00043000 0x00043000 0x001000>, /* ap 36 */ +- <0x00014000 0x00014000 0x001000>, /* ap 37 */ +- <0x00015000 0x00015000 0x001000>; /* ap 38 */ +- +- target-module@c000 { /* 0x47c0c000, ap 3 04.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc000 0x1000>; +- }; +- +- target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xe000 0x1000>; +- }; +- +- target-module@10000 { /* 0x47c10000, ap 7 20.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10000 0x1000>; +- }; +- +- target-module@14000 { /* 0x47c14000, ap 37 3c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x14000 0x1000>; +- }; +- +- target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1a000 0x1000>; +- }; +- +- target-module@24000 { /* 0x47c24000, ap 11 28.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x24000 0x1000>; +- }; +- +- target-module@26000 { /* 0x47c26000, ap 13 30.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x26000 0x1000>; +- }; +- +- target-module@28000 { /* 0x47c28000, ap 29 40.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x28000 0x1000>; +- }; +- +- target-module@30000 { /* 0x47c30000, ap 15 14.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x30000 0x1000>; +- }; +- +- target-module@32000 { /* 0x47c32000, ap 31 06.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x32000 0x1000>; +- }; +- +- target-module@38000 { /* 0x47c38000, ap 17 18.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x38000 0x1000>; +- }; +- +- target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3a000 0x1000>; +- }; +- +- target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3c000 0x1000>; +- }; +- +- target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3e000 0x1000>; +- }; +- +- target-module@40000 { /* 0x47c40000, ap 24 02.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x40000 0x1000>; +- }; +- +- target-module@42000 { /* 0x47c42000, ap 35 34.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x42000 0x1000>; +- }; +- +- target-module@44000 { /* 0x47c44000, ap 27 24.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x44000 0x1000>; +- }; +- +- target-module@46000 { /* 0x47c46000, ap 25 2c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x46000 0x1000>; +- }; +- }; +-}; +- +-&l4_fast { /* 0x4a000000 */ +- compatible = "ti,am33xx-l4-fast", "simple-pm-bus"; +- power-domains = <&prm_per>; +- clocks = <&l4hs_clkctrl AM3_L4HS_L4_HS_CLKCTRL 0>; +- clock-names = "fck"; +- reg = <0x4a000000 0x800>, +- <0x4a000800 0x800>, +- <0x4a001000 0x400>; +- reg-names = "ap", "la", "ia0"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ +- +- segment@0 { /* 0x4a000000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ +- <0x00000800 0x00000800 0x000800>, /* ap 1 */ +- <0x00001000 0x00001000 0x000400>, /* ap 2 */ +- <0x00100000 0x00100000 0x008000>, /* ap 3 */ +- <0x00108000 0x00108000 0x001000>, /* ap 4 */ +- <0x00180000 0x00180000 0x020000>, /* ap 5 */ +- <0x001a0000 0x001a0000 0x001000>, /* ap 6 */ +- <0x00200000 0x00200000 0x080000>, /* ap 7 */ +- <0x00280000 0x00280000 0x001000>, /* ap 8 */ +- <0x00300000 0x00300000 0x080000>, /* ap 9 */ +- <0x00380000 0x00380000 0x001000>; /* ap 10 */ +- +- target-module@100000 { /* 0x4a100000, ap 3 08.0 */ +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- reg = <0x101200 0x4>, +- <0x101208 0x4>, +- <0x101204 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <0>; +- ti,sysc-midle = , +- ; +- ti,sysc-sidle = , +- ; +- ti,syss-mask = <1>; +- clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x100000 0x8000>; +- +- mac: ethernet@0 { +- compatible = "ti,am335x-cpsw","ti,cpsw"; +- clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; +- clock-names = "fck", "cpts"; +- cpdma_channels = <8>; +- ale_entries = <1024>; +- bd_ram_size = <0x2000>; +- mac_control = <0x20>; +- slaves = <2>; +- active_slave = <0>; +- cpts_clock_mult = <0x80000000>; +- cpts_clock_shift = <29>; +- reg = <0x0 0x800 +- 0x1200 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * c0_rx_thresh_pend +- * c0_rx_pend +- * c0_tx_pend +- * c0_misc_pend +- */ +- interrupts = <40 41 42 43>; +- ranges = <0 0 0x8000>; +- syscon = <&scm_conf>; +- status = "disabled"; +- +- davinci_mdio: mdio@1000 { +- compatible = "ti,cpsw-mdio","ti,davinci_mdio"; +- clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <0>; +- bus_freq = <1000000>; +- reg = <0x1000 0x100>; +- status = "disabled"; +- }; +- +- cpsw_emac0: slave@200 { +- /* Filled in by U-Boot */ +- mac-address = [ 00 00 00 00 00 00 ]; +- phys = <&phy_gmii_sel 1 1>; +- }; +- +- cpsw_emac1: slave@300 { +- /* Filled in by U-Boot */ +- mac-address = [ 00 00 00 00 00 00 ]; +- phys = <&phy_gmii_sel 2 1>; +- }; +- }; +- +- mac_sw: switch@0 { +- compatible = "ti,am335x-cpsw-switch", "ti,cpsw-switch"; +- reg = <0x0 0x4000>; +- ranges = <0 0 0x4000>; +- clocks = <&cpsw_125mhz_gclk>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- syscon = <&scm_conf>; +- status = "disabled"; +- +- interrupts = <40 41 42 43>; +- interrupt-names = "rx_thresh", "rx", "tx", "misc"; +- +- ethernet-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpsw_port1: port@1 { +- reg = <1>; +- label = "port1"; +- mac-address = [ 00 00 00 00 00 00 ]; +- phys = <&phy_gmii_sel 1 1>; +- }; +- +- cpsw_port2: port@2 { +- reg = <2>; +- label = "port2"; +- mac-address = [ 00 00 00 00 00 00 ]; +- phys = <&phy_gmii_sel 2 1>; +- }; +- }; +- +- davinci_mdio_sw: mdio@1000 { +- compatible = "ti,cpsw-mdio","ti,davinci_mdio"; +- clocks = <&cpsw_125mhz_gclk>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <0>; +- bus_freq = <1000000>; +- reg = <0x1000 0x100>; +- }; +- +- cpts { +- clocks = <&cpsw_cpts_rft_clk>; +- clock-names = "cpts"; +- }; +- }; +- }; +- +- target-module@180000 { /* 0x4a180000, ap 5 10.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x180000 0x20000>; +- }; +- +- target-module@200000 { /* 0x4a200000, ap 7 02.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x200000 0x80000>; +- }; +- +- pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */ +- compatible = "ti,sysc-pruss", "ti,sysc"; +- reg = <0x326000 0x4>, +- <0x326004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | +- SYSC_PRUSS_SUB_MWAIT)>; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>; +- clock-names = "fck"; +- resets = <&prm_per 1>; +- reset-names = "rstctrl"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x300000 0x80000>; +- status = "disabled"; +- +- pruss: pruss@0 { +- compatible = "ti,am3356-pruss"; +- reg = <0x0 0x80000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- pruss_mem: memories@0 { +- reg = <0x0 0x2000>, +- <0x2000 0x2000>, +- <0x10000 0x3000>; +- reg-names = "dram0", "dram1", +- "shrdram2"; +- }; +- +- pruss_cfg: cfg@26000 { +- compatible = "ti,pruss-cfg", "syscon"; +- reg = <0x26000 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x26000 0x2000>; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- pruss_iepclk_mux: iepclk-mux@30 { +- reg = <0x30>; +- #clock-cells = <0>; +- clocks = <&l3_gclk>, /* icss_iep_gclk */ +- <&pruss_ocp_gclk>; /* icss_ocp_gclk */ +- }; +- }; +- }; +- +- pruss_mii_rt: mii-rt@32000 { +- compatible = "ti,pruss-mii", "syscon"; +- reg = <0x32000 0x58>; +- }; +- +- pruss_intc: interrupt-controller@20000 { +- compatible = "ti,pruss-intc"; +- reg = <0x20000 0x2000>; +- interrupts = <20 21 22 23 24 25 26 27>; +- interrupt-names = "host_intr0", "host_intr1", +- "host_intr2", "host_intr3", +- "host_intr4", "host_intr5", +- "host_intr6", "host_intr7"; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- +- pru0: pru@34000 { +- compatible = "ti,am3356-pru"; +- reg = <0x34000 0x2000>, +- <0x22000 0x400>, +- <0x22400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am335x-pru0-fw"; +- }; +- +- pru1: pru@38000 { +- compatible = "ti,am3356-pru"; +- reg = <0x38000 0x2000>, +- <0x24000 0x400>, +- <0x24400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am335x-pru1-fw"; +- }; +- +- pruss_mdio: mdio@32400 { +- compatible = "ti,davinci_mdio"; +- reg = <0x32400 0x90>; +- clocks = <&dpll_core_m4_ck>; +- clock-names = "fck"; +- bus_freq = <1000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- }; +- }; +-}; +- +-&l4_mpuss { /* 0x4b140000 */ +- compatible = "ti,am33xx-l4-mpuss", "simple-bus"; +- reg = <0x4b144400 0x100>, +- <0x4b144800 0x400>; +- reg-names = "la", "ap"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */ +- +- segment@0 { /* 0x4b140000 */ +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */ +- <0x00001000 0x00001000 0x001000>, /* ap 1 */ +- <0x00002000 0x00002000 0x001000>, /* ap 2 */ +- <0x00004000 0x00004000 0x000400>, /* ap 3 */ +- <0x00005000 0x00005000 0x000400>, /* ap 4 */ +- <0x00000000 0x00000000 0x001000>, /* ap 5 */ +- <0x00003000 0x00003000 0x001000>, /* ap 6 */ +- <0x00000800 0x00000800 0x000800>; /* ap 7 */ +- +- target-module@0 { /* 0x4b140000, ap 5 02.2 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x00001000>, +- <0x00001000 0x00001000 0x00001000>, +- <0x00002000 0x00002000 0x00001000>; +- }; +- +- target-module@3000 { /* 0x4b143000, ap 6 04.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3000 0x1000>; +- }; +- }; +-}; +- +-&l4_per { /* 0x48000000 */ +- compatible = "ti,am33xx-l4-per", "simple-pm-bus"; +- power-domains = <&prm_per>; +- clocks = <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>; +- clock-names = "fck"; +- reg = <0x48000000 0x800>, +- <0x48000800 0x800>, +- <0x48001000 0x400>, +- <0x48001400 0x400>, +- <0x48001800 0x400>, +- <0x48001c00 0x400>; +- reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ +- <0x00100000 0x48100000 0x100000>, /* segment 1 */ +- <0x00200000 0x48200000 0x100000>, /* segment 2 */ +- <0x00300000 0x48300000 0x100000>, /* segment 3 */ +- <0x46000000 0x46000000 0x400000>, /* l3 data port */ +- <0x46400000 0x46400000 0x400000>; /* l3 data port */ +- +- segment@0 { /* 0x48000000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ +- <0x00000800 0x00000800 0x000800>, /* ap 1 */ +- <0x00001000 0x00001000 0x000400>, /* ap 2 */ +- <0x00001400 0x00001400 0x000400>, /* ap 3 */ +- <0x00001800 0x00001800 0x000400>, /* ap 4 */ +- <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ +- <0x00008000 0x00008000 0x001000>, /* ap 6 */ +- <0x00009000 0x00009000 0x001000>, /* ap 7 */ +- <0x00016000 0x00016000 0x001000>, /* ap 8 */ +- <0x00017000 0x00017000 0x001000>, /* ap 9 */ +- <0x00022000 0x00022000 0x001000>, /* ap 10 */ +- <0x00023000 0x00023000 0x001000>, /* ap 11 */ +- <0x00024000 0x00024000 0x001000>, /* ap 12 */ +- <0x00025000 0x00025000 0x001000>, /* ap 13 */ +- <0x0002a000 0x0002a000 0x001000>, /* ap 14 */ +- <0x0002b000 0x0002b000 0x001000>, /* ap 15 */ +- <0x00038000 0x00038000 0x002000>, /* ap 16 */ +- <0x0003a000 0x0003a000 0x001000>, /* ap 17 */ +- <0x00014000 0x00014000 0x001000>, /* ap 18 */ +- <0x00015000 0x00015000 0x001000>, /* ap 19 */ +- <0x0003c000 0x0003c000 0x002000>, /* ap 20 */ +- <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ +- <0x00040000 0x00040000 0x001000>, /* ap 22 */ +- <0x00041000 0x00041000 0x001000>, /* ap 23 */ +- <0x00042000 0x00042000 0x001000>, /* ap 24 */ +- <0x00043000 0x00043000 0x001000>, /* ap 25 */ +- <0x00044000 0x00044000 0x001000>, /* ap 26 */ +- <0x00045000 0x00045000 0x001000>, /* ap 27 */ +- <0x00046000 0x00046000 0x001000>, /* ap 28 */ +- <0x00047000 0x00047000 0x001000>, /* ap 29 */ +- <0x00048000 0x00048000 0x001000>, /* ap 30 */ +- <0x00049000 0x00049000 0x001000>, /* ap 31 */ +- <0x0004c000 0x0004c000 0x001000>, /* ap 32 */ +- <0x0004d000 0x0004d000 0x001000>, /* ap 33 */ +- <0x00050000 0x00050000 0x002000>, /* ap 34 */ +- <0x00052000 0x00052000 0x001000>, /* ap 35 */ +- <0x00060000 0x00060000 0x001000>, /* ap 36 */ +- <0x00061000 0x00061000 0x001000>, /* ap 37 */ +- <0x00080000 0x00080000 0x010000>, /* ap 38 */ +- <0x00090000 0x00090000 0x001000>, /* ap 39 */ +- <0x000a0000 0x000a0000 0x010000>, /* ap 40 */ +- <0x000b0000 0x000b0000 0x001000>, /* ap 41 */ +- <0x00030000 0x00030000 0x001000>, /* ap 77 */ +- <0x00031000 0x00031000 0x001000>, /* ap 78 */ +- <0x0004a000 0x0004a000 0x001000>, /* ap 85 */ +- <0x0004b000 0x0004b000 0x001000>, /* ap 86 */ +- <0x000c8000 0x000c8000 0x001000>, /* ap 87 */ +- <0x000c9000 0x000c9000 0x001000>, /* ap 88 */ +- <0x000cc000 0x000cc000 0x001000>, /* ap 89 */ +- <0x000cd000 0x000cd000 0x001000>, /* ap 90 */ +- <0x000ca000 0x000ca000 0x001000>, /* ap 91 */ +- <0x000cb000 0x000cb000 0x001000>, /* ap 92 */ +- <0x46000000 0x46000000 0x400000>, /* l3 data port */ +- <0x46400000 0x46400000 0x400000>; /* l3 data port */ +- +- target-module@8000 { /* 0x48008000, ap 6 10.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x8000 0x1000>; +- }; +- +- target-module@14000 { /* 0x48014000, ap 18 58.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x14000 0x1000>; +- }; +- +- target-module@16000 { /* 0x48016000, ap 8 3c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x16000 0x1000>; +- }; +- +- target-module@22000 { /* 0x48022000, ap 10 12.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x22050 0x4>, +- <0x22054 0x4>, +- <0x22058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x22000 0x1000>; +- +- uart1: serial@0 { +- compatible = "ti,am3352-uart", "ti,omap3-uart"; +- clock-frequency = <48000000>; +- reg = <0x0 0x1000>; +- interrupts = <73>; +- status = "disabled"; +- dmas = <&edma 28 0>, <&edma 29 0>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@24000 { /* 0x48024000, ap 12 14.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x24050 0x4>, +- <0x24054 0x4>, +- <0x24058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x24000 0x1000>; +- +- uart2: serial@0 { +- compatible = "ti,am3352-uart", "ti,omap3-uart"; +- clock-frequency = <48000000>; +- reg = <0x0 0x1000>; +- interrupts = <74>; +- status = "disabled"; +- dmas = <&edma 30 0>, <&edma 31 0>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x2a000 0x8>, +- <0x2a010 0x8>, +- <0x2a090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2a000 0x1000>; +- +- i2c1: i2c@0 { +- compatible = "ti,omap4-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x1000>; +- interrupts = <71>; +- status = "disabled"; +- }; +- }; +- +- target-module@30000 { /* 0x48030000, ap 77 08.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x30000 0x4>, +- <0x30110 0x4>, +- <0x30114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x30000 0x1000>; +- +- spi0: spi@0 { +- compatible = "ti,omap4-mcspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x400>; +- interrupts = <65>; +- ti,spi-num-cs = <2>; +- dmas = <&edma 16 0 +- &edma 17 0 +- &edma 18 0 +- &edma 19 0>; +- dma-names = "tx0", "rx0", "tx1", "rx1"; +- status = "disabled"; +- }; +- }; +- +- target-module@38000 { /* 0x48038000, ap 16 02.0 */ +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- reg = <0x38000 0x4>, +- <0x38004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): per_pwrdm, l3s_clkdm */ +- clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x38000 0x2000>, +- <0x46000000 0x46000000 0x400000>; +- +- mcasp0: mcasp@0 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x0 0x2000>, +- <0x46000000 0x400000>; +- reg-names = "mpu", "dat"; +- interrupts = <80>, <81>; +- interrupt-names = "tx", "rx"; +- status = "disabled"; +- dmas = <&edma 8 2>, +- <&edma 9 2>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@3c000 { /* 0x4803c000, ap 20 32.0 */ +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- reg = <0x3c000 0x4>, +- <0x3c004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): per_pwrdm, l3s_clkdm */ +- clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3c000 0x2000>, +- <0x46400000 0x46400000 0x400000>; +- +- mcasp1: mcasp@0 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x0 0x2000>, +- <0x46400000 0x400000>; +- reg-names = "mpu", "dat"; +- interrupts = <82>, <83>; +- interrupt-names = "tx", "rx"; +- status = "disabled"; +- dmas = <&edma 10 2>, +- <&edma 11 2>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x40000 0x4>, +- <0x40010 0x4>, +- <0x40014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x40000 0x1000>; +- +- timer2: timer@0 { +- compatible = "ti,am335x-timer"; +- reg = <0x0 0x400>; +- interrupts = <68>; +- clocks = <&timer2_fck>; +- clock-names = "fck"; +- }; +- }; +- +- target-module@42000 { /* 0x48042000, ap 24 1c.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x42000 0x4>, +- <0x42010 0x4>, +- <0x42014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x42000 0x1000>; +- +- timer3: timer@0 { +- compatible = "ti,am335x-timer"; +- reg = <0x0 0x400>; +- interrupts = <69>; +- }; +- }; +- +- target-module@44000 { /* 0x48044000, ap 26 26.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x44000 0x4>, +- <0x44010 0x4>, +- <0x44014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x44000 0x1000>; +- +- timer4: timer@0 { +- compatible = "ti,am335x-timer"; +- reg = <0x0 0x400>; +- interrupts = <92>; +- ti,timer-pwm; +- }; +- }; +- +- target-module@46000 { /* 0x48046000, ap 28 28.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x46000 0x4>, +- <0x46010 0x4>, +- <0x46014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x46000 0x1000>; +- +- timer5: timer@0 { +- compatible = "ti,am335x-timer"; +- reg = <0x0 0x400>; +- interrupts = <93>; +- ti,timer-pwm; +- }; +- }; +- +- target-module@48000 { /* 0x48048000, ap 30 22.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x48000 0x4>, +- <0x48010 0x4>, +- <0x48014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x48000 0x1000>; +- +- timer6: timer@0 { +- compatible = "ti,am335x-timer"; +- reg = <0x0 0x400>; +- interrupts = <94>; +- ti,timer-pwm; +- }; +- }; +- +- target-module@4a000 { /* 0x4804a000, ap 85 60.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x4a000 0x4>, +- <0x4a010 0x4>, +- <0x4a014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4a000 0x1000>; +- +- timer7: timer@0 { +- compatible = "ti,am335x-timer"; +- reg = <0x0 0x400>; +- interrupts = <95>; +- ti,timer-pwm; +- }; +- }; +- +- target-module@4c000 { /* 0x4804c000, ap 32 36.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4c000 0x4>, +- <0x4c010 0x4>, +- <0x4c114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>, +- <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4c000 0x1000>; +- +- gpio1: gpio@0 { +- compatible = "ti,omap4-gpio"; +- gpio-ranges = <&am33xx_pinmux 0 0 8>, +- <&am33xx_pinmux 8 90 4>, +- <&am33xx_pinmux 12 12 16>, +- <&am33xx_pinmux 28 30 4>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x0 0x1000>; +- interrupts = <98>; +- }; +- }; +- +- target-module@50000 { /* 0x48050000, ap 34 2c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x50000 0x2000>; +- }; +- +- target-module@60000 { /* 0x48060000, ap 36 0c.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x602fc 0x4>, +- <0x60110 0x4>, +- <0x60114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x60000 0x1000>; +- +- mmc1: mmc@0 { +- compatible = "ti,am335-sdhci"; +- ti,needs-special-reset; +- dmas = <&edma_xbar 24 0 0 +- &edma_xbar 25 0 0>; +- dma-names = "tx", "rx"; +- interrupts = <64>; +- reg = <0x0 0x1000>; +- status = "disabled"; +- }; +- }; +- +- target-module@80000 { /* 0x48080000, ap 38 18.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x80000 0x4>, +- <0x80010 0x4>, +- <0x80014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x80000 0x10000>; +- +- elm: elm@0 { +- compatible = "ti,am3352-elm"; +- reg = <0x0 0x2000>; +- interrupts = <4>; +- status = "disabled"; +- }; +- }; +- +- target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa0000 0x10000>; +- }; +- +- target-module@c8000 { /* 0x480c8000, ap 87 06.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xc8000 0x4>, +- <0xc8010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc8000 0x1000>; +- +- mailbox: mailbox@0 { +- compatible = "ti,omap4-mailbox"; +- reg = <0x0 0x200>; +- interrupts = <77>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <8>; +- mbox_wkupm3: mbox-wkup-m3 { +- ti,mbox-send-noirq; +- ti,mbox-tx = <0 0 0>; +- ti,mbox-rx = <0 0 3>; +- }; +- }; +- }; +- +- target-module@ca000 { /* 0x480ca000, ap 91 40.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xca000 0x4>, +- <0xca010 0x4>, +- <0xca014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xca000 0x1000>; +- +- hwspinlock: spinlock@0 { +- compatible = "ti,omap4-hwspinlock"; +- reg = <0x0 0x1000>; +- #hwlock-cells = <1>; +- }; +- }; +- +- target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xcc000 0x1000>; +- }; +- }; +- +- segment@100000 { /* 0x48100000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */ +- <0x0008d000 0x0018d000 0x001000>, /* ap 43 */ +- <0x0008e000 0x0018e000 0x001000>, /* ap 44 */ +- <0x0008f000 0x0018f000 0x001000>, /* ap 45 */ +- <0x0009c000 0x0019c000 0x001000>, /* ap 46 */ +- <0x0009d000 0x0019d000 0x001000>, /* ap 47 */ +- <0x000a6000 0x001a6000 0x001000>, /* ap 48 */ +- <0x000a7000 0x001a7000 0x001000>, /* ap 49 */ +- <0x000a8000 0x001a8000 0x001000>, /* ap 50 */ +- <0x000a9000 0x001a9000 0x001000>, /* ap 51 */ +- <0x000aa000 0x001aa000 0x001000>, /* ap 52 */ +- <0x000ab000 0x001ab000 0x001000>, /* ap 53 */ +- <0x000ac000 0x001ac000 0x001000>, /* ap 54 */ +- <0x000ad000 0x001ad000 0x001000>, /* ap 55 */ +- <0x000ae000 0x001ae000 0x001000>, /* ap 56 */ +- <0x000af000 0x001af000 0x001000>, /* ap 57 */ +- <0x000b0000 0x001b0000 0x010000>, /* ap 58 */ +- <0x000c0000 0x001c0000 0x001000>, /* ap 59 */ +- <0x000cc000 0x001cc000 0x002000>, /* ap 60 */ +- <0x000ce000 0x001ce000 0x002000>, /* ap 61 */ +- <0x000d0000 0x001d0000 0x002000>, /* ap 62 */ +- <0x000d2000 0x001d2000 0x002000>, /* ap 63 */ +- <0x000d8000 0x001d8000 0x001000>, /* ap 64 */ +- <0x000d9000 0x001d9000 0x001000>, /* ap 65 */ +- <0x000a0000 0x001a0000 0x001000>, /* ap 79 */ +- <0x000a1000 0x001a1000 0x001000>, /* ap 80 */ +- <0x000a2000 0x001a2000 0x001000>, /* ap 81 */ +- <0x000a3000 0x001a3000 0x001000>, /* ap 82 */ +- <0x000a4000 0x001a4000 0x001000>, /* ap 83 */ +- <0x000a5000 0x001a5000 0x001000>; /* ap 84 */ +- +- target-module@8c000 { /* 0x4818c000, ap 42 04.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x8c000 0x1000>; +- }; +- +- target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x8e000 0x1000>; +- }; +- +- target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x9c000 0x8>, +- <0x9c010 0x8>, +- <0x9c090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x9c000 0x1000>; +- +- i2c2: i2c@0 { +- compatible = "ti,omap4-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x1000>; +- interrupts = <30>; +- status = "disabled"; +- }; +- }; +- +- target-module@a0000 { /* 0x481a0000, ap 79 24.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xa0000 0x4>, +- <0xa0110 0x4>, +- <0xa0114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa0000 0x1000>; +- +- spi1: spi@0 { +- compatible = "ti,omap4-mcspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x400>; +- interrupts = <125>; +- ti,spi-num-cs = <2>; +- dmas = <&edma 42 0 +- &edma 43 0 +- &edma 44 0 +- &edma 45 0>; +- dma-names = "tx0", "rx0", "tx1", "rx1"; +- status = "disabled"; +- }; +- }; +- +- target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa2000 0x1000>; +- }; +- +- target-module@a4000 { /* 0x481a4000, ap 83 30.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa4000 0x1000>; +- }; +- +- target-module@a6000 { /* 0x481a6000, ap 48 16.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xa6050 0x4>, +- <0xa6054 0x4>, +- <0xa6058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa6000 0x1000>; +- +- uart3: serial@0 { +- compatible = "ti,am3352-uart", "ti,omap3-uart"; +- clock-frequency = <48000000>; +- reg = <0x0 0x1000>; +- interrupts = <44>; +- status = "disabled"; +- }; +- }; +- +- target-module@a8000 { /* 0x481a8000, ap 50 20.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xa8050 0x4>, +- <0xa8054 0x4>, +- <0xa8058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa8000 0x1000>; +- +- uart4: serial@0 { +- compatible = "ti,am3352-uart", "ti,omap3-uart"; +- clock-frequency = <48000000>; +- reg = <0x0 0x1000>; +- interrupts = <45>; +- status = "disabled"; +- }; +- }; +- +- target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xaa050 0x4>, +- <0xaa054 0x4>, +- <0xaa058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xaa000 0x1000>; +- +- uart5: serial@0 { +- compatible = "ti,am3352-uart", "ti,omap3-uart"; +- clock-frequency = <48000000>; +- reg = <0x0 0x1000>; +- interrupts = <46>; +- status = "disabled"; +- }; +- }; +- +- target-module@ac000 { /* 0x481ac000, ap 54 38.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xac000 0x4>, +- <0xac010 0x4>, +- <0xac114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>, +- <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xac000 0x1000>; +- +- gpio2: gpio@0 { +- compatible = "ti,omap4-gpio"; +- gpio-ranges = <&am33xx_pinmux 0 34 18>, +- <&am33xx_pinmux 18 77 4>, +- <&am33xx_pinmux 22 56 10>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x0 0x1000>; +- interrupts = <32>; +- }; +- }; +- +- gpio3_target: target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xae000 0x4>, +- <0xae010 0x4>, +- <0xae114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>, +- <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xae000 0x1000>; +- +- gpio3: gpio@0 { +- compatible = "ti,omap4-gpio"; +- gpio-ranges = <&am33xx_pinmux 0 66 5>, +- <&am33xx_pinmux 5 98 2>, +- <&am33xx_pinmux 7 75 2>, +- <&am33xx_pinmux 13 141 1>, +- <&am33xx_pinmux 14 100 8>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x0 0x1000>; +- interrupts = <62>; +- }; +- }; +- +- target-module@b0000 { /* 0x481b0000, ap 58 50.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xb0000 0x10000>; +- }; +- +- target-module@cc000 { /* 0x481cc000, ap 60 46.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xcc020 0x4>; +- reg-names = "rev"; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>, +- <&dcan0_fck>; +- clock-names = "fck", "osc"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xcc000 0x2000>; +- +- dcan0: can@0 { +- compatible = "ti,am3352-d_can"; +- reg = <0x0 0x2000>; +- clocks = <&dcan0_fck>; +- clock-names = "fck"; +- syscon-raminit = <&scm_conf 0x644 0>; +- interrupts = <52>; +- status = "disabled"; +- }; +- }; +- +- target-module@d0000 { /* 0x481d0000, ap 62 42.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xd0020 0x4>; +- reg-names = "rev"; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>, +- <&dcan1_fck>; +- clock-names = "fck", "osc"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xd0000 0x2000>; +- +- dcan1: can@0 { +- compatible = "ti,am3352-d_can"; +- reg = <0x0 0x2000>; +- clocks = <&dcan1_fck>; +- clock-names = "fck"; +- syscon-raminit = <&scm_conf 0x644 1>; +- interrupts = <55>; +- status = "disabled"; +- }; +- }; +- +- target-module@d8000 { /* 0x481d8000, ap 64 66.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xd82fc 0x4>, +- <0xd8110 0x4>, +- <0xd8114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xd8000 0x1000>; +- +- mmc2: mmc@0 { +- compatible = "ti,am335-sdhci"; +- ti,needs-special-reset; +- dmas = <&edma 2 0 +- &edma 3 0>; +- dma-names = "tx", "rx"; +- interrupts = <28>; +- reg = <0x0 0x1000>; +- status = "disabled"; +- }; +- }; +- }; +- +- segment@200000 { /* 0x48200000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00200000 0x010000>; +- +- target-module@0 { +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- power-domains = <&prm_mpu>; +- clocks = <&mpu_clkctrl AM3_MPU_MPU_CLKCTRL 0>; +- clock-names = "fck"; +- ti,no-idle; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x10000>; +- +- mpu@0 { +- compatible = "ti,omap3-mpu"; +- pm-sram = <&pm_sram_code +- &pm_sram_data>; +- }; +- }; +- }; +- +- segment@300000 { /* 0x48300000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */ +- <0x00001000 0x00301000 0x001000>, /* ap 67 */ +- <0x00002000 0x00302000 0x001000>, /* ap 68 */ +- <0x00003000 0x00303000 0x001000>, /* ap 69 */ +- <0x00004000 0x00304000 0x001000>, /* ap 70 */ +- <0x00005000 0x00305000 0x001000>, /* ap 71 */ +- <0x0000e000 0x0030e000 0x001000>, /* ap 72 */ +- <0x0000f000 0x0030f000 0x001000>, /* ap 73 */ +- <0x00018000 0x00318000 0x004000>, /* ap 74 */ +- <0x0001c000 0x0031c000 0x001000>, /* ap 75 */ +- <0x00010000 0x00310000 0x002000>, /* ap 76 */ +- <0x00012000 0x00312000 0x001000>, /* ap 93 */ +- <0x00015000 0x00315000 0x001000>, /* ap 94 */ +- <0x00016000 0x00316000 0x001000>, /* ap 95 */ +- <0x00017000 0x00317000 0x001000>, /* ap 96 */ +- <0x00013000 0x00313000 0x001000>, /* ap 97 */ +- <0x00014000 0x00314000 0x001000>, /* ap 98 */ +- <0x00020000 0x00320000 0x001000>, /* ap 99 */ +- <0x00021000 0x00321000 0x001000>, /* ap 100 */ +- <0x00022000 0x00322000 0x001000>, /* ap 101 */ +- <0x00023000 0x00323000 0x001000>, /* ap 102 */ +- <0x00024000 0x00324000 0x001000>, /* ap 103 */ +- <0x00025000 0x00325000 0x001000>; /* ap 104 */ +- +- target-module@0 { /* 0x48300000, ap 66 48.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x0 0x4>, +- <0x4 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1000>; +- +- epwmss0: epwmss@0 { +- compatible = "ti,am33xx-pwmss"; +- reg = <0x0 0x10>; +- #address-cells = <1>; +- #size-cells = <1>; +- status = "disabled"; +- ranges = <0 0 0x1000>; +- +- ecap0: pwm@100 { +- compatible = "ti,am3352-ecap"; +- #pwm-cells = <3>; +- reg = <0x100 0x80>; +- clocks = <&l4ls_gclk>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- +- eqep0: counter@180 { +- compatible = "ti,am3352-eqep"; +- reg = <0x180 0x80>; +- clocks = <&l4ls_gclk>; +- clock-names = "sysclkout"; +- interrupts = <79>; +- status = "disabled"; +- }; +- +- ehrpwm0: pwm@200 { +- compatible = "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x200 0x80>; +- clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; +- clock-names = "tbclk", "fck"; +- status = "disabled"; +- }; +- }; +- }; +- +- target-module@2000 { /* 0x48302000, ap 68 52.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x2000 0x4>, +- <0x2004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2000 0x1000>; +- +- epwmss1: epwmss@0 { +- compatible = "ti,am33xx-pwmss"; +- reg = <0x0 0x10>; +- #address-cells = <1>; +- #size-cells = <1>; +- status = "disabled"; +- ranges = <0 0 0x1000>; +- +- ecap1: pwm@100 { +- compatible = "ti,am3352-ecap"; +- #pwm-cells = <3>; +- reg = <0x100 0x80>; +- clocks = <&l4ls_gclk>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- +- eqep1: counter@180 { +- compatible = "ti,am3352-eqep"; +- reg = <0x180 0x80>; +- clocks = <&l4ls_gclk>; +- clock-names = "sysclkout"; +- interrupts = <88>; +- status = "disabled"; +- }; +- +- ehrpwm1: pwm@200 { +- compatible = "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x200 0x80>; +- clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; +- clock-names = "tbclk", "fck"; +- status = "disabled"; +- }; +- }; +- }; +- +- target-module@4000 { /* 0x48304000, ap 70 44.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x4000 0x4>, +- <0x4004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4000 0x1000>; +- +- epwmss2: epwmss@0 { +- compatible = "ti,am33xx-pwmss"; +- reg = <0x0 0x10>; +- #address-cells = <1>; +- #size-cells = <1>; +- status = "disabled"; +- ranges = <0 0 0x1000>; +- +- ecap2: pwm@100 { +- compatible = "ti,am3352-ecap"; +- #pwm-cells = <3>; +- reg = <0x100 0x80>; +- clocks = <&l4ls_gclk>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- +- eqep2: counter@180 { +- compatible = "ti,am3352-eqep"; +- reg = <0x180 0x80>; +- clocks = <&l4ls_gclk>; +- clock-names = "sysclkout"; +- interrupts = <89>; +- status = "disabled"; +- }; +- +- ehrpwm2: pwm@200 { +- compatible = "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x200 0x80>; +- clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; +- clock-names = "tbclk", "fck"; +- status = "disabled"; +- }; +- }; +- }; +- +- target-module@e000 { /* 0x4830e000, ap 72 4a.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xe000 0x4>, +- <0xe054 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): per_pwrdm, lcdc_clkdm */ +- clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xe000 0x1000>; +- +- lcdc: lcdc@0 { +- compatible = "ti,am33xx-tilcdc"; +- reg = <0x0 0x1000>; +- interrupts = <36>; +- status = "disabled"; +- }; +- }; +- +- target-module@10000 { /* 0x48310000, ap 76 4e.1 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x11fe0 0x4>, +- <0x11fe4 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10000 0x2000>; +- +- rng: rng@0 { +- compatible = "ti,omap4-rng"; +- reg = <0x0 0x2000>; +- interrupts = <111>; +- }; +- }; +- +- target-module@13000 { /* 0x48313000, ap 97 62.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x13000 0x1000>; +- }; +- +- target-module@15000 { /* 0x48315000, ap 94 56.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00015000 0x00001000>, +- <0x00001000 0x00016000 0x00001000>; +- }; +- +- target-module@18000 { /* 0x48318000, ap 74 4c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x18000 0x4000>; +- }; +- +- target-module@20000 { /* 0x48320000, ap 99 34.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x20000 0x1000>; +- }; +- +- target-module@22000 { /* 0x48322000, ap 101 3e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x22000 0x1000>; +- }; +- +- target-module@24000 { /* 0x48324000, ap 103 68.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x24000 0x1000>; +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/am33xx.dtsi b/scripts/dtc/include-prefixes/arm/am33xx.dtsi +deleted file mode 100644 +index f6ec85d58dd1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am33xx.dtsi ++++ /dev/null +@@ -1,714 +0,0 @@ +-/* +- * Device Tree Source for AM33XX SoC +- * +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "ti,am33xx"; +- interrupt-parent = <&intc>; +- #address-cells = <1>; +- #size-cells = <1>; +- chosen { }; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- serial5 = &uart5; +- d-can0 = &dcan0; +- d-can1 = &dcan1; +- usb0 = &usb0; +- usb1 = &usb1; +- phy0 = &usb0_phy; +- phy1 = &usb1_phy; +- ethernet0 = &cpsw_port1; +- ethernet1 = &cpsw_port2; +- spi0 = &spi0; +- spi1 = &spi1; +- mmc0 = &mmc1; +- mmc1 = &mmc2; +- mmc2 = &mmc3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- compatible = "arm,cortex-a8"; +- enable-method = "ti,am3352"; +- device_type = "cpu"; +- reg = <0>; +- +- operating-points-v2 = <&cpu0_opp_table>; +- +- clocks = <&dpll_mpu_ck>; +- clock-names = "cpu"; +- +- clock-latency = <300000>; /* From omap-cpufreq driver */ +- cpu-idle-states = <&mpu_gate>; +- }; +- +- idle-states { +- mpu_gate: mpu_gate { +- compatible = "arm,idle-state"; +- entry-latency-us = <40>; +- exit-latency-us = <90>; +- min-residency-us = <300>; +- ti,idle-wkup-m3; +- }; +- }; +- }; +- +- cpu0_opp_table: opp-table { +- compatible = "operating-points-v2-ti-cpu"; +- syscon = <&scm_conf>; +- +- /* +- * The three following nodes are marked with opp-suspend +- * because the can not be enabled simultaneously on a +- * single SoC. +- */ +- opp50-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <950000 931000 969000>; +- opp-supported-hw = <0x06 0x0010>; +- opp-suspend; +- }; +- +- opp100-275000000 { +- opp-hz = /bits/ 64 <275000000>; +- opp-microvolt = <1100000 1078000 1122000>; +- opp-supported-hw = <0x01 0x00FF>; +- opp-suspend; +- }; +- +- opp100-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <1100000 1078000 1122000>; +- opp-supported-hw = <0x06 0x0020>; +- opp-suspend; +- }; +- +- opp100-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <1100000 1078000 1122000>; +- opp-supported-hw = <0x01 0xFFFF>; +- }; +- +- opp100-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <1100000 1078000 1122000>; +- opp-supported-hw = <0x06 0x0040>; +- }; +- +- opp120-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <1200000 1176000 1224000>; +- opp-supported-hw = <0x01 0xFFFF>; +- }; +- +- opp120-720000000 { +- opp-hz = /bits/ 64 <720000000>; +- opp-microvolt = <1200000 1176000 1224000>; +- opp-supported-hw = <0x06 0x0080>; +- }; +- +- oppturbo-720000000 { +- opp-hz = /bits/ 64 <720000000>; +- opp-microvolt = <1260000 1234800 1285200>; +- opp-supported-hw = <0x01 0xFFFF>; +- }; +- +- oppturbo-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <1260000 1234800 1285200>; +- opp-supported-hw = <0x06 0x0100>; +- }; +- +- oppnitro-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <1325000 1298500 1351500>; +- opp-supported-hw = <0x04 0x0200>; +- }; +- }; +- +- target-module@4b000000 { +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>; +- clock-names = "fck"; +- ti,no-idle; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4b000000 0x1000000>; +- +- target-module@140000 { +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x140000 0xec0000>; +- +- pmu@0 { +- compatible = "arm,cortex-a8-pmu"; +- interrupts = <3>; +- }; +- }; +- }; +- +- /* +- * The soc node represents the soc top level view. It is used for IPs +- * that are not memory mapped in the MPU view or for the MPU itself. +- */ +- soc { +- compatible = "ti,omap-infra"; +- }; +- +- /* +- * XXX: Use a flat representation of the AM33XX interconnect. +- * The real AM33XX interconnect network is quite complex. Since +- * it will not bring real advantage to represent that in DT +- * for the moment, just use a fake OCP bus entry to represent +- * the whole bus hierarchy. +- */ +- ocp: ocp { +- compatible = "simple-pm-bus"; +- power-domains = <&prm_per>; +- clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- l4_wkup: interconnect@44c00000 { +- }; +- l4_per: interconnect@48000000 { +- }; +- l4_fw: interconnect@47c00000 { +- }; +- l4_fast: interconnect@4a000000 { +- }; +- l4_mpuss: interconnect@4b140000 { +- }; +- +- intc: interrupt-controller@48200000 { +- compatible = "ti,am33xx-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x48200000 0x1000>; +- }; +- +- target-module@49000000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x49000000 0x4>; +- reg-names = "rev"; +- clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49000000 0x10000>; +- +- edma: dma@0 { +- compatible = "ti,edma3-tpcc"; +- reg = <0 0x10000>; +- reg-names = "edma3_cc"; +- interrupts = <12 13 14>; +- interrupt-names = "edma3_ccint", "edma3_mperr", +- "edma3_ccerrint"; +- dma-requests = <64>; +- #dma-cells = <2>; +- +- ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, +- <&edma_tptc2 0>; +- +- ti,edma-memcpy-channels = <20 21>; +- }; +- }; +- +- target-module@49800000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x49800000 0x4>, +- <0x49800010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = ; +- ti,sysc-sidle = , +- ; +- clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49800000 0x100000>; +- +- edma_tptc0: dma@0 { +- compatible = "ti,edma3-tptc"; +- reg = <0 0x100000>; +- interrupts = <112>; +- interrupt-names = "edma3_tcerrint"; +- }; +- }; +- +- target-module@49900000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x49900000 0x4>, +- <0x49900010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = ; +- ti,sysc-sidle = , +- ; +- clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49900000 0x100000>; +- +- edma_tptc1: dma@0 { +- compatible = "ti,edma3-tptc"; +- reg = <0 0x100000>; +- interrupts = <113>; +- interrupt-names = "edma3_tcerrint"; +- }; +- }; +- +- target-module@49a00000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x49a00000 0x4>, +- <0x49a00010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = ; +- ti,sysc-sidle = , +- ; +- clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49a00000 0x100000>; +- +- edma_tptc2: dma@0 { +- compatible = "ti,edma3-tptc"; +- reg = <0 0x100000>; +- interrupts = <114>; +- interrupt-names = "edma3_tcerrint"; +- }; +- }; +- +- target-module@47810000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x478102fc 0x4>, +- <0x47810110 0x4>, +- <0x47810114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x47810000 0x1000>; +- +- mmc3: mmc@0 { +- compatible = "ti,am335-sdhci"; +- ti,needs-special-reset; +- interrupts = <29>; +- reg = <0x0 0x1000>; +- status = "disabled"; +- }; +- }; +- +- usb: target-module@47400000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x47400000 0x4>, +- <0x47400010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x47400000 0x8000>; +- +- usb0_phy: usb-phy@1300 { +- compatible = "ti,am335x-usb-phy"; +- reg = <0x1300 0x100>; +- reg-names = "phy"; +- ti,ctrl_mod = <&usb_ctrl_mod>; +- #phy-cells = <0>; +- }; +- +- usb0: usb@1400 { +- compatible = "ti,musb-am33xx"; +- reg = <0x1400 0x400>, +- <0x1000 0x200>; +- reg-names = "mc", "control"; +- +- interrupts = <18>; +- interrupt-names = "mc"; +- dr_mode = "otg"; +- mentor,multipoint = <1>; +- mentor,num-eps = <16>; +- mentor,ram-bits = <12>; +- mentor,power = <500>; +- phys = <&usb0_phy>; +- +- dmas = <&cppi41dma 0 0 &cppi41dma 1 0 +- &cppi41dma 2 0 &cppi41dma 3 0 +- &cppi41dma 4 0 &cppi41dma 5 0 +- &cppi41dma 6 0 &cppi41dma 7 0 +- &cppi41dma 8 0 &cppi41dma 9 0 +- &cppi41dma 10 0 &cppi41dma 11 0 +- &cppi41dma 12 0 &cppi41dma 13 0 +- &cppi41dma 14 0 &cppi41dma 0 1 +- &cppi41dma 1 1 &cppi41dma 2 1 +- &cppi41dma 3 1 &cppi41dma 4 1 +- &cppi41dma 5 1 &cppi41dma 6 1 +- &cppi41dma 7 1 &cppi41dma 8 1 +- &cppi41dma 9 1 &cppi41dma 10 1 +- &cppi41dma 11 1 &cppi41dma 12 1 +- &cppi41dma 13 1 &cppi41dma 14 1>; +- dma-names = +- "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", +- "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", +- "rx14", "rx15", +- "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", +- "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", +- "tx14", "tx15"; +- }; +- +- usb1_phy: usb-phy@1b00 { +- compatible = "ti,am335x-usb-phy"; +- reg = <0x1b00 0x100>; +- reg-names = "phy"; +- ti,ctrl_mod = <&usb_ctrl_mod>; +- #phy-cells = <0>; +- }; +- +- usb1: usb@1800 { +- compatible = "ti,musb-am33xx"; +- reg = <0x1c00 0x400>, +- <0x1800 0x200>; +- reg-names = "mc", "control"; +- interrupts = <19>; +- interrupt-names = "mc"; +- dr_mode = "otg"; +- mentor,multipoint = <1>; +- mentor,num-eps = <16>; +- mentor,ram-bits = <12>; +- mentor,power = <500>; +- phys = <&usb1_phy>; +- +- dmas = <&cppi41dma 15 0 &cppi41dma 16 0 +- &cppi41dma 17 0 &cppi41dma 18 0 +- &cppi41dma 19 0 &cppi41dma 20 0 +- &cppi41dma 21 0 &cppi41dma 22 0 +- &cppi41dma 23 0 &cppi41dma 24 0 +- &cppi41dma 25 0 &cppi41dma 26 0 +- &cppi41dma 27 0 &cppi41dma 28 0 +- &cppi41dma 29 0 &cppi41dma 15 1 +- &cppi41dma 16 1 &cppi41dma 17 1 +- &cppi41dma 18 1 &cppi41dma 19 1 +- &cppi41dma 20 1 &cppi41dma 21 1 +- &cppi41dma 22 1 &cppi41dma 23 1 +- &cppi41dma 24 1 &cppi41dma 25 1 +- &cppi41dma 26 1 &cppi41dma 27 1 +- &cppi41dma 28 1 &cppi41dma 29 1>; +- dma-names = +- "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", +- "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", +- "rx14", "rx15", +- "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", +- "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", +- "tx14", "tx15"; +- }; +- +- cppi41dma: dma-controller@2000 { +- compatible = "ti,am3359-cppi41"; +- reg = <0x0000 0x1000>, +- <0x2000 0x1000>, +- <0x3000 0x1000>, +- <0x4000 0x4000>; +- reg-names = "glue", "controller", "scheduler", "queuemgr"; +- interrupts = <17>; +- interrupt-names = "glue"; +- #dma-cells = <2>; +- #dma-channels = <30>; +- #dma-requests = <256>; +- }; +- }; +- +- target-module@40300000 { +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- clocks = <&l3_clkctrl AM3_L3_OCMCRAM_CLKCTRL 0>; +- clock-names = "fck"; +- ti,no-idle; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x40300000 0x10000>; +- +- ocmcram: sram@0 { +- compatible = "mmio-sram"; +- reg = <0 0x10000>; /* 64k */ +- ranges = <0 0 0x10000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- pm_sram_code: pm-code-sram@0 { +- compatible = "ti,sram"; +- reg = <0x0 0x1000>; +- protect-exec; +- }; +- +- pm_sram_data: pm-data-sram@1000 { +- compatible = "ti,sram"; +- reg = <0x1000 0x1000>; +- pool; +- }; +- }; +- }; +- +- target-module@4c000000 { +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- reg = <0x4c000000 0x4>; +- reg-names = "rev"; +- clocks = <&l3_clkctrl AM3_L3_EMIF_CLKCTRL 0>; +- clock-names = "fck"; +- ti,no-idle; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4c000000 0x1000000>; +- +- emif: emif@0 { +- compatible = "ti,emif-am3352"; +- reg = <0 0x1000000>; +- interrupts = <101>; +- sram = <&pm_sram_code +- &pm_sram_data>; +- }; +- }; +- +- target-module@50000000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x50000000 4>, +- <0x50000010 4>, +- <0x50000014 4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ +- <0x00000000 0x00000000 0x40000000>; /* data */ +- +- gpmc: gpmc@50000000 { +- compatible = "ti,am3352-gpmc"; +- reg = <0x50000000 0x2000>; +- interrupts = <100>; +- dmas = <&edma 52 0>; +- dma-names = "rxtx"; +- gpmc,num-cs = <7>; +- gpmc,num-waitpins = <2>; +- #address-cells = <2>; +- #size-cells = <1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- status = "disabled"; +- }; +- }; +- +- sham_target: target-module@53100000 { +- compatible = "ti,sysc-omap3-sham", "ti,sysc"; +- reg = <0x53100100 0x4>, +- <0x53100110 0x4>, +- <0x53100114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l3_clkdm */ +- clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x53100000 0x1000>; +- +- sham: sham@0 { +- compatible = "ti,omap4-sham"; +- reg = <0 0x200>; +- interrupts = <109>; +- dmas = <&edma 36 0>; +- dma-names = "rx"; +- }; +- }; +- +- aes_target: target-module@53500000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x53500080 0x4>, +- <0x53500084 0x4>, +- <0x53500088 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l3_clkdm */ +- clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x53500000 0x1000>; +- +- aes: aes@0 { +- compatible = "ti,omap4-aes"; +- reg = <0 0xa0>; +- interrupts = <103>; +- dmas = <&edma 6 0>, +- <&edma 5 0>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@56000000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x5600fe00 0x4>, +- <0x5600fe10 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>; +- clock-names = "fck"; +- power-domains = <&prm_gfx>; +- resets = <&prm_gfx 0>; +- reset-names = "rstctrl"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x56000000 0x1000000>; +- +- /* +- * Closed source PowerVR driver, no child device +- * binding or driver in mainline +- */ +- }; +- }; +-}; +- +-#include "am33xx-l4.dtsi" +-#include "am33xx-clocks.dtsi" +- +-&prcm { +- prm_per: prm@c00 { +- compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; +- reg = <0xc00 0x100>; +- #reset-cells = <1>; +- #power-domain-cells = <0>; +- }; +- +- prm_wkup: prm@d00 { +- compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; +- reg = <0xd00 0x100>; +- #reset-cells = <1>; +- #power-domain-cells = <0>; +- }; +- +- prm_mpu: prm@e00 { +- compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; +- reg = <0xe00 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_device: prm@f00 { +- compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; +- reg = <0xf00 0x100>; +- #reset-cells = <1>; +- }; +- +- prm_rtc: prm@1000 { +- compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1000 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_gfx: prm@1100 { +- compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1100 0x100>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- prm_cefuse: prm@1200 { +- compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1200 0x100>; +- #power-domain-cells = <0>; +- }; +-}; +- +-/* Preferred always-on timer for clocksource */ +-&timer1_target { +- clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>, +- <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>; +- clock-names = "fck", "ick"; +- ti,no-reset-on-init; +- ti,no-idle; +- timer@0 { +- assigned-clocks = <&timer1_fck>; +- assigned-clock-parents = <&sys_clkin_ck>; +- }; +-}; +- +-/* Preferred timer for clockevent */ +-&timer2_target { +- clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>, +- <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>; +- clock-names = "fck", "ick"; +- ti,no-reset-on-init; +- ti,no-idle; +- timer@0 { +- assigned-clocks = <&timer2_fck>; +- assigned-clock-parents = <&sys_clkin_ck>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am3517-craneboard.dts b/scripts/dtc/include-prefixes/arm/am3517-craneboard.dts +deleted file mode 100644 +index 3642cfc80194..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am3517-craneboard.dts ++++ /dev/null +@@ -1,171 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * See craneboard.org for more details +- * +- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "am3517.dtsi" +- +-/ { +- model = "TI AM3517 CraneBoard (TMDSEVM3517)"; +- compatible = "ti,am3517-craneboard", "ti,am3517", "ti,omap3"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +- +- vbat: fixedregulator { +- compatible = "regulator-fixed"; +- regulator-name = "vbat"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- }; +-}; +- +-&davinci_emac { +- status = "okay"; +-}; +- +-&davinci_mdio { +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <2600000>; +- +- tps: tps@2d { +- reg = <0x2d>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- /* goes to expansion connector */ +- status = "disabled"; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +- /* goes to expansion connector */ +- status = "disabled"; +-}; +- +-&mmc1 { +- vmmc-supply = <&vdd2_reg>; +- bus-width = <8>; +-}; +- +-&mmc2 { +- /* goes to expansion connector */ +- status = "disabled"; +-}; +- +-&mmc3 { +- /* goes to expansion connector */ +- status = "disabled"; +-}; +- +-#include "tps65910.dtsi" +- +-&omap3_pmx_core { +- tps_pins: pinmux_tps_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq.sys_nirq */ +- >; +- }; +-}; +- +-&tps { +- pinctrl-names = "default"; +- pinctrl-0 = <&tps_pins>; +- +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- interrupt-parent = <&intc>; +- +- ti,en-ck32k-xtal; +- +- vcc1-supply = <&vbat>; +- vcc2-supply = <&vbat>; +- vcc3-supply = <&vbat>; +- vcc4-supply = <&vbat>; +- vcc5-supply = <&vbat>; +- vcc6-supply = <&vbat>; +- vcc7-supply = <&vbat>; +- vccio-supply = <&vbat>; +- +- regulators { +- vrtc_reg: regulator@0 { +- regulator-always-on; +- }; +- +- vio_reg: regulator@1 { +- regulator-always-on; +- }; +- +- /* +- * Unused: +- * VDIG1=2.7V,300mA max +- * VDIG2=1.8V,300mA max +- */ +- +- vpll_reg: regulator@7 { +- /* VDDS_DPLL_1V8 */ +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vaux1_reg: regulator@9 { +- /* VDDS_SRAM_1V8 */ +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vaux2_reg: regulator@10 { +- /* VDDA1P8V_USBPHY */ +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- /* VAUX33 unused */ +- +- vdac_reg: regulator@8 { +- /* VDDA_DAC_1V8 */ +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vmmc_reg: regulator@12 { +- /* VDDA3P3V_USBPHY */ +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd1_reg: regulator@2 { +- /* VDD_CORE */ +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd2_reg: regulator@3 { +- /* VDDSHV_3V3 */ +- regulator-name = "vdd_shv"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- /* VDD3 unused */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am3517-evm-ui.dtsi b/scripts/dtc/include-prefixes/arm/am3517-evm-ui.dtsi +deleted file mode 100644 +index 7d8f32bf70db..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am3517-evm-ui.dtsi ++++ /dev/null +@@ -1,217 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2018 Logic PD, Inc - https://www.logicpd.com/ +- */ +- +-#include +- +-/ { +- codec1 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "tlv320aic23-hifi"; +- +- simple-audio-card,widgets = +- "Microphone", "Mic In", +- "Line", "Line In", +- "Line", "Line Out"; +- +- simple-audio-card,routing = +- "Line Out", "LOUT", +- "Line Out", "ROUT", +- "LLINEIN", "Line In", +- "RLINEIN", "Line In", +- "MICIN", "Mic In"; +- +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sound_master>; +- simple-audio-card,frame-master = <&sound_master>; +- +- simple-audio-card,cpu { +- sound-dai = <&mcbsp1>; +- }; +- +- sound_master: simple-audio-card,codec { +- sound-dai = <&tlv320aic23_1>; +- system-clock-frequency = <12000000>; +- }; +- }; +- +- codec2 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "tlv320aic23-hifi"; +- +- simple-audio-card,widgets = +- "Microphone", "Mic In", +- "Line", "Line In", +- "Line", "Line Out"; +- +- simple-audio-card,routing = +- "Line Out", "LOUT", +- "Line Out", "ROUT", +- "LLINEIN", "Line In", +- "RLINEIN", "Line In", +- "MICIN", "Mic In"; +- +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sound_master2>; +- simple-audio-card,frame-master = <&sound_master2>; +- +- simple-audio-card,cpu { +- sound-dai = <&mcbsp2>; +- }; +- +- sound_master2: simple-audio-card,codec { +- sound-dai = <&tlv320aic23_2>; +- system-clock-frequency = <12000000>; +- }; +- }; +- +- expander-keys { +- compatible = "gpio-keys-polled"; +- poll-interval = <100>; +- +- record { +- label = "Record"; +- /* linux,code = ; */ +- gpios = <&tca6416_2 15 GPIO_ACTIVE_LOW>; +- }; +- +- play { +- label = "Play"; +- linux,code = ; +- gpios = <&tca6416_2 14 GPIO_ACTIVE_LOW>; +- }; +- +- Stop { +- label = "Stop"; +- linux,code = ; +- gpios = <&tca6416_2 13 GPIO_ACTIVE_LOW>; +- }; +- +- fwd { +- label = "FWD"; +- linux,code = ; +- gpios = <&tca6416_2 12 GPIO_ACTIVE_LOW>; +- }; +- +- rwd { +- label = "RWD"; +- linux,code = ; +- gpios = <&tca6416_2 11 GPIO_ACTIVE_LOW>; +- }; +- +- shift { +- label = "Shift"; +- linux,code = ; +- gpios = <&tca6416_2 10 GPIO_ACTIVE_LOW>; +- }; +- +- Mode { +- label = "Mode"; +- linux,code = ; +- gpios = <&tca6416_2 9 GPIO_ACTIVE_LOW>; +- }; +- +- Menu { +- label = "Menu"; +- linux,code = ; +- gpios = <&tca6416_2 8 GPIO_ACTIVE_LOW>; +- }; +- +- Up { +- label = "Up"; +- linux,code = ; +- gpios = <&tca6416_2 7 GPIO_ACTIVE_LOW>; +- }; +- +- Down { +- label = "Down"; +- linux,code = ; +- gpios = <&tca6416_2 6 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&i2c2 { +- /* Audio codecs */ +- tlv320aic23_1: codec@1a { +- compatible = "ti,tlv320aic23"; +- reg = <0x1a>; +- #sound-dai-cells= <0>; +- status = "okay"; +- }; +- +- tlv320aic23_2: codec@1b { +- compatible = "ti,tlv320aic23"; +- reg = <0x1b>; +- #sound-dai-cells= <0>; +- status = "okay"; +- }; +-}; +- +-&i2c3 { +- /* Audio codecs */ +- tlv320aic23_3: codec@1a { +- compatible = "ti,tlv320aic23"; +- reg = <0x1a>; +- #sound-dai-cells= <0>; +- status = "okay"; +- }; +- +- /* GPIO Expanders */ +- tca6416_2: gpio@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- vcc-supply = <&vdd_io_reg>; +- }; +- +- tca6416_3: gpio@21 { +- compatible = "ti,tca6416"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- vcc-supply = <&vdd_io_reg>; +- }; +- +- /* TVP5146 Analog Video decoder input */ +- tvp5146@5c { +- compatible = "ti,tvp5146m2"; +- reg = <0x5c>; +- }; +-}; +- +-&mcbsp1 { +- status = "okay"; +- #sound-dai-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp1_pins>; +-}; +- +-&mcbsp2 { +- status = "okay"; +- #sound-dai-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp2_pins>; +-}; +- +-&omap3_pmx_core { +- mcbsp1_pins: pinmux_mcbsp1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dx */ +- OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dr */ +- OMAP3_CORE1_IOPAD(0x2196, PIN_INPUT | MUX_MODE0) /* mcbsp_clks.mcbsp1_fsx */ +- OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE0) /* mcbsp1_clkx.mcbsp1_clkx */ +- >; +- }; +- +- mcbsp2_pins: pinmux_mcbsp2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ +- OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ +- OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */ +- OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am3517-evm.dts b/scripts/dtc/include-prefixes/arm/am3517-evm.dts +deleted file mode 100644 +index 0d2fac98ce7d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am3517-evm.dts ++++ /dev/null +@@ -1,322 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "am3517.dtsi" +-#include "am3517-som.dtsi" +-#include "am3517-evm-ui.dtsi" +-#include +- +-/ { +- model = "TI AM3517 EVM (AM3517/05 TMDSEVM3517)"; +- compatible = "ti,am3517-evm", "ti,am3517", "ti,omap3"; +- +- aliases { +- display0 = &lcd0; +- }; +- +- chosen { +- stdout-path = &uart3; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +- +- vmmc_fixed: vmmc { +- compatible = "regulator-fixed"; +- regulator-name = "vmmc_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys-polled"; +- poll-interval = <100>; +- +- user_pb { +- label = "User Push Button"; +- linux,code = ; +- gpios = <&tca6416 5 GPIO_ACTIVE_LOW>; +- }; +- +- user_sw_1 { +- label = "User Switch 1"; +- linux,code = ; +- gpios = <&tca6416 8 GPIO_ACTIVE_LOW>; +- }; +- +- user_sw_2 { +- label = "User Switch 2"; +- linux,code = ; +- gpios = <&tca6416 9 GPIO_ACTIVE_LOW>; +- }; +- +- user_sw_3 { +- label = "User Switch 3"; +- linux,code = ; +- gpios = <&tca6416 10 GPIO_ACTIVE_LOW>; +- }; +- +- user_sw_4 { +- label = "User Switch 4"; +- linux,code = ; +- gpios = <&tca6416 11 GPIO_ACTIVE_LOW>; +- }; +- +- user_sw_5 { +- label = "User Switch 5"; +- linux,code = ; +- gpios = <&tca6416 12 GPIO_ACTIVE_LOW>; +- }; +- +- user_sw_6 { +- label = "User Switch 6"; +- linux,code = ; +- gpios = <&tca6416 13 GPIO_ACTIVE_LOW>; +- }; +- +- user_sw_7 { +- label = "User Switch 7"; +- linux,code = ; +- gpios = <&tca6416 14 GPIO_ACTIVE_LOW>; +- }; +- +- user_sw_8 { +- label = "User Switch 8"; +- linux,code = ; +- gpios = <&tca6416 15 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&leds_pins>; +- +- user_led_1 { +- label = "am3517evm:green:user_led_1"; +- gpios = <&tca6416 7 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- +- user_led_2 { +- label = "am3517evm:green:user_led_2"; +- gpios = <&tca6416 6 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- +- user_led_3 { +- label = "am3517evm:green:user_led_3"; +- gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; /* SD/MMC card activity */ +- }; +- +- user_led_4 { +- label = "am3517evm:green:user_led_4"; +- gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- lcd0: display@0 { +- /* This isn't the exact LCD, but the timings meet spec */ +- /* To make it work, set CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 */ +- compatible = "newhaven,nhd-4.3-480272ef-atxl"; +- label = "15"; +- backlight = <&bl>; +- enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; /* gpio176, lcd INI */ +- vcc-supply = <&vdd_io_reg>; +- +- port { +- lcd_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- }; +- +- bl: backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- power-supply = <&vdd_io_reg>; +- pinctrl-0 = <&backlight_pins>; +- pwms = <&pwm11 0 5000000 0>; +- brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; +- default-brightness-level = <7>; +- enable-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* gpio_182 */ +- }; +- +- pwm11: dmtimer-pwm@11 { +- compatible = "ti,omap-dmtimer-pwm"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm_pins>; +- ti,timers = <&timer11>; +- #pwm-cells = <3>; +- ti,clock-source = <0x01>; +- }; +- +- /* HS USB Host PHY on PORT 1 */ +- hsusb1_phy: hsusb1_phy { +- compatible = "usb-nop-xceiv"; +- reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */ +- #phy-cells = <0>; +- }; +-}; +- +-&davinci_emac { +- status = "okay"; +-}; +- +-&davinci_mdio { +- status = "okay"; +-}; +- +-&dss { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_dpi_pins>; +- +- vdds_dsi-supply = <&vdd_io_reg>; +- vdda_video-supply = <&vdd_io_reg>; +- +- port { +- dpi_out: endpoint { +- remote-endpoint = <&lcd_in>; +- data-lines = <16>; +- }; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- /* User DIP swithes [1:8] / User LEDS [1:2] */ +- tca6416: gpio@21 { +- compatible = "ti,tca6416"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- vcc-supply = <&vdd_io_reg>; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +-}; +- +-&mmc1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <&vmmc_fixed>; +- bus-width = <4>; +- wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */ +- cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio_127 */ +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-&usbhshost { +- port1-mode = "ehci-phy"; +-}; +- +-&usbhsehci { +- phys = <&hsusb1_phy>; +-}; +- +-&omap3_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = <&hsusb1_rst_pins>; +- +- leds_pins: pinmux_leds_pins { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 */ +- OMAP3_WKUP_IOPAD(0x2a26, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu1.gpio_31 */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ +- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ +- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ +- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ +- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ +- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ +- OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat4.gpio_126 */ +- OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat5.gpio_127 */ +- >; +- }; +- +- pwm_pins: pinmux_pwm_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE1) /* mcspi2_cs0.gpt11_pwm */ +- >; +- }; +- +- backlight_pins: pinmux_backlight_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT | MUX_MODE4) /* mcspi2_cs1.gpio_182 */ +- >; +- }; +- +- dss_dpi_pins: pinmux_dss_dpi_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21d2, PIN_OUTPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ +- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ +- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ +- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ +- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ +- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ +- OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ +- OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ +- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ +- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ +- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ +- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ +- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ +- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ +- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ +- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ +- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ +- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ +- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ +- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ +- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ +- >; +- }; +- +- hsusb1_rst_pins: pinmux_hsusb1_rst_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ +- >; +- }; +-}; +- +-&omap3_pmx_core2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hsusb1_pins>; +- +- hsusb1_pins: pinmux_hsusb1_pins { +- pinctrl-single,pins = < +- OMAP3430_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ +- OMAP3430_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ +- OMAP3430_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */ +- OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */ +- OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */ +- OMAP3430_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */ +- OMAP3430_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */ +- OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */ +- OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */ +- OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */ +- OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */ +- OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am3517-som.dtsi b/scripts/dtc/include-prefixes/arm/am3517-som.dtsi +deleted file mode 100644 +index 8b669e2eafec..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am3517-som.dtsi ++++ /dev/null +@@ -1,234 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2016 Derald D. Woods +- * +- * Based on am3517-evm.dts +- */ +- +-/ { +- cpus { +- cpu@0 { +- cpu0-supply = <&vdd_core_reg>; +- }; +- }; +- +- wl12xx_buffer: wl12xx_buf { +- compatible = "regulator-fixed"; +- regulator-name = "wl1271_buf"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&wl12xx_buffer_pins>; +- gpio = <&gpio5 1 GPIO_ACTIVE_LOW>; /* gpio 129 */ +- regulator-always-on; +- vin-supply = <&vdd_1v8_reg>; +- }; +- +- wl12xx_vmmc2: wl12xx_vmmc2 { +- compatible = "regulator-fixed"; +- regulator-name = "vwl1271"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&wl12xx_wkup_pins>; +- gpio = <&gpio1 3 GPIO_ACTIVE_HIGH >; /* gpio 3 */ +- startup-delay-us = <70000>; +- enable-active-high; +- regulator-always-on; +- vin-supply = <&wl12xx_buffer>; +- }; +-}; +- +-&gpmc { +- ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ +- +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- linux,mtd-name = "micron,mt29f4g16abchch"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- nand-bus-width = <16>; +- ti,nand-ecc-opt = "bch8"; +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- gpmc,device-width = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- +- s35390a: s35390a@30 { +- compatible = "sii,s35390a"; +- reg = <0x30>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&rtc_pins>; +- interrupts-extended = <&gpio2 23 IRQ_TYPE_EDGE_FALLING>; /* gpio_55 */ +- }; +- +- tps: tps65023@48 { +- compatible = "ti,tps65023"; +- reg = <0x48>; +- +- regulators { +- vdd_core_reg: VDCDC1 { +- regulator-name = "vdd_core"; +- regulator-always-on; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- vdd_io_reg: VDCDC2 { +- regulator-name = "vdd_io"; +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vdd_1v8_reg: VDCDC3 { +- regulator-name = "vdd_1v8"; +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vdd_usb18_reg: LDO1 { +- regulator-name = "vdd_usb18"; +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vdd_usb33_reg: LDO2 { +- regulator-name = "vdd_usb33"; +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +- }; +- +- touchscreen: tsc2004@4b { +- compatible = "ti,tsc2004"; +- reg = <0x4b>; +- +- vio-supply = <&vdd_io_reg>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&tsc2004_pins>; +- interrupts-extended = <&gpio3 1 IRQ_TYPE_EDGE_RISING>; /* gpio_65 */ +- +- touchscreen-fuzz-x = <4>; +- touchscreen-fuzz-y = <7>; +- touchscreen-fuzz-pressure = <2>; +- touchscreen-size-x = <480>; +- touchscreen-size-y = <272>; +- touchscreen-max-pressure = <2048>; +- +- ti,x-plate-ohms = <280>; +- ti,esd-recovery-timeout-ms = <8000>; +- }; +-}; +- +-&mmc2 { +- interrupts-extended = <&intc 86 /* &omap3_pmx_core 0x12c */>; +- +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- vmmc-supply = <&wl12xx_vmmc2>; +- non-removable; +- bus-width = <4>; +- cap-power-off-card; +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1271"; +- reg = <2>; +- interrupt-parent = <&gpio6>; +- interrupts = <10 IRQ_TYPE_EDGE_RISING>; /* gpio_170 */ +- ref-clock-frequency = <26000000>; +- tcxo-clock-frequency = <26000000>; +- }; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- +- bluetooth { +- compatible = "ti,wl1271-st"; +- enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio 56 */ +- max-speed = <3000000>; +- }; +-}; +- +-&omap3_pmx_core { +- +- wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */ +- >; +- }; +- +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_clk.mmc2_clk */ +- OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_cmd.mmc2_cmd */ +- OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat0.mmc2_dat0 */ +- OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat1.mmc2_dat1 */ +- OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat2.mmc2_dat2 */ +- OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat3.mmc2_dat3 */ +- OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat4.mmc2_dir_dat0 */ +- OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat5.mmc2_dir_dat1 */ +- OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat6.mmc2_dir_cmd */ +- OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* mmc2_dat7.mmc2_clkin */ +- OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE4) /* hdq_sio.gpio_170 */ +- >; +- }; +- +- rtc_pins: pinmux_rtc_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20b6, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs4.gpio_55 */ +- >; +- }; +- +- tsc2004_pins: pinmux_tsc2004_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT | MUX_MODE4) /* gpmc_wait3.gpio_65 */ +- >; +- }; +- +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ +- OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLUP | MUX_MODE0) /* uart2_rts */ +- OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ +- OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ +- OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT | MUX_MODE0) /* gpio_56 */ +- >; +- }; +-}; +- +-&omap3_pmx_wkup { +- +- wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am3517.dtsi b/scripts/dtc/include-prefixes/arm/am3517.dtsi +deleted file mode 100644 +index de33c4f89f33..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am3517.dtsi ++++ /dev/null +@@ -1,197 +0,0 @@ +-/* +- * Device Tree Source for am3517 SoC +- * +- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-#include "omap3.dtsi" +- +-/* AM3517 doesn't appear to have the crypto engines defined in omap3.dtsi */ +-/delete-node/ &aes1_target; +-/delete-node/ &aes2_target; +- +-/ { +- aliases { +- serial3 = &uart4; +- can = &hecc; +- }; +- +- cpus { +- cpu: cpu@0 { +- /* Based on OMAP3630 variants OPP50 and OPP100 */ +- operating-points-v2 = <&cpu0_opp_table>; +- +- clock-latency = <300000>; /* From legacy driver */ +- }; +- }; +- +- cpu0_opp_table: opp-table { +- compatible = "operating-points-v2-ti-cpu"; +- syscon = <&scm_conf>; +- /* +- * AM3517 TRM only lists 600MHz @ 1.2V, but omap36xx +- * appear to operate at 300MHz as well. Since AM3517 only +- * lists one operating voltage, it will remain fixed at 1.2V +- */ +- opp50-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <1200000>; +- opp-supported-hw = <0xffffffff 0xffffffff>; +- opp-suspend; +- }; +- +- opp100-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <1200000>; +- opp-supported-hw = <0xffffffff 0xffffffff>; +- }; +- }; +- +- ocp@68000000 { +- am35x_otg_hs: am35x_otg_hs@5c040000 { +- compatible = "ti,omap3-musb"; +- ti,hwmods = "am35x_otg_hs"; +- status = "disabled"; +- reg = <0x5c040000 0x1000>; +- interrupts = <71>; +- interrupt-names = "mc"; +- }; +- +- davinci_emac: ethernet@5c000000 { +- compatible = "ti,am3517-emac"; +- ti,hwmods = "davinci_emac"; +- status = "disabled"; +- reg = <0x5c000000 0x30000>; +- interrupts = <67 68 69 70>; +- syscon = <&scm_conf>; +- ti,davinci-ctrl-reg-offset = <0x10000>; +- ti,davinci-ctrl-mod-reg-offset = <0>; +- ti,davinci-ctrl-ram-offset = <0x20000>; +- ti,davinci-ctrl-ram-size = <0x2000>; +- ti,davinci-rmii-en = /bits/ 8 <1>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- clocks = <&emac_ick>; +- clock-names = "ick"; +- }; +- +- davinci_mdio: mdio@5c030000 { +- compatible = "ti,davinci_mdio"; +- ti,hwmods = "davinci_mdio"; +- status = "disabled"; +- reg = <0x5c030000 0x1000>; +- bus_freq = <1000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&emac_fck>; +- clock-names = "fck"; +- }; +- +- uart4: serial@4809e000 { +- compatible = "ti,omap3-uart"; +- ti,hwmods = "uart4"; +- status = "disabled"; +- reg = <0x4809e000 0x400>; +- interrupts = <84>; +- dmas = <&sdma 55 &sdma 54>; +- dma-names = "tx", "rx"; +- clock-frequency = <48000000>; +- }; +- +- omap3_pmx_core2: pinmux@480025d8 { +- compatible = "ti,omap3-padconf", "pinctrl-single"; +- reg = <0x480025d8 0x24>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <1>; +- #interrupt-cells = <1>; +- interrupt-controller; +- pinctrl-single,register-width = <16>; +- pinctrl-single,function-mask = <0xff1f>; +- }; +- +- hecc: can@5c050000 { +- compatible = "ti,am3517-hecc"; +- status = "disabled"; +- reg = <0x5c050000 0x80>, +- <0x5c053000 0x180>, +- <0x5c052000 0x200>; +- reg-names = "hecc", "hecc-ram", "mbx"; +- interrupts = <24>; +- clocks = <&hecc_ck>; +- }; +- +- /* +- * On am3517 the OCP registers do not seem to be accessible +- * similar to the omap34xx. Maybe SGX is permanently set to +- * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is +- * write-only at 0x50000e10. We detect SGX based on the SGX +- * revision register instead of the unreadable OCP revision +- * register. +- */ +- sgx_module: target-module@50000000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x50000014 0x4>; +- reg-names = "rev"; +- clocks = <&sgx_fck>, <&sgx_ick>; +- clock-names = "fck", "ick"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x50000000 0x4000>; +- +- /* +- * Closed source PowerVR driver, no child device +- * binding or driver in mainline +- */ +- }; +- }; +-}; +- +-/* Not currently working, probably needs at least different clocks */ +-&rng_target { +- status = "disabled"; +- /delete-property/ clocks; +-}; +- +-/* Table Table 5-79 of the TRM shows 480ab000 is reserved */ +-&usb_otg_hs { +- status = "disabled"; +-}; +- +-&iva { +- status = "disabled"; +-}; +- +-&mailbox { +- status = "disabled"; +-}; +- +-&mmu_isp { +- status = "disabled"; +-}; +- +-#include "am35xx-clocks.dtsi" +-#include "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" +- +-/* Preferred always-on timer for clocksource */ +-&timer1_target { +- ti,no-reset-on-init; +- ti,no-idle; +- timer@0 { +- assigned-clocks = <&gpt1_fck>; +- assigned-clock-parents = <&sys_ck>; +- }; +-}; +- +-/* Preferred timer for clockevent */ +-&timer2_target { +- ti,no-reset-on-init; +- ti,no-idle; +- timer@0 { +- assigned-clocks = <&gpt2_fck>; +- assigned-clock-parents = <&sys_ck>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am3517_mt_ventoux.dts b/scripts/dtc/include-prefixes/arm/am3517_mt_ventoux.dts +deleted file mode 100644 +index e7d7124a34ba..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am3517_mt_ventoux.dts ++++ /dev/null +@@ -1,24 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2011 Ilya Yanok, EmCraft Systems +- */ +-/dts-v1/; +- +-#include "omap34xx.dtsi" +- +-/ { +- model = "TeeJet Mt.Ventoux"; +- compatible = "teejet,mt_ventoux", "ti,am3517", "ti,omap3"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +- +- /* AM35xx doesn't have IVA */ +- soc { +- iva { +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am35xx-clocks.dtsi b/scripts/dtc/include-prefixes/arm/am35xx-clocks.dtsi +deleted file mode 100644 +index 220d0a52797e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am35xx-clocks.dtsi ++++ /dev/null +@@ -1,125 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for OMAP3 clock data +- * +- * Copyright (C) 2013 Texas Instruments, Inc. +- */ +-&scm_clocks { +- emac_ick: emac_ick@32c { +- #clock-cells = <0>; +- compatible = "ti,am35xx-gate-clock"; +- clocks = <&ipss_ick>; +- reg = <0x032c>; +- ti,bit-shift = <1>; +- }; +- +- emac_fck: emac_fck@32c { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&rmii_ck>; +- reg = <0x032c>; +- ti,bit-shift = <9>; +- }; +- +- vpfe_ick: vpfe_ick@32c { +- #clock-cells = <0>; +- compatible = "ti,am35xx-gate-clock"; +- clocks = <&ipss_ick>; +- reg = <0x032c>; +- ti,bit-shift = <2>; +- }; +- +- vpfe_fck: vpfe_fck@32c { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&pclk_ck>; +- reg = <0x032c>; +- ti,bit-shift = <10>; +- }; +- +- hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c { +- #clock-cells = <0>; +- compatible = "ti,am35xx-gate-clock"; +- clocks = <&ipss_ick>; +- reg = <0x032c>; +- ti,bit-shift = <0>; +- }; +- +- hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&sys_ck>; +- reg = <0x032c>; +- ti,bit-shift = <8>; +- }; +- +- hecc_ck: hecc_ck@32c { +- #clock-cells = <0>; +- compatible = "ti,am35xx-gate-clock"; +- clocks = <&sys_ck>; +- reg = <0x032c>; +- ti,bit-shift = <3>; +- }; +-}; +-&cm_clocks { +- ipss_ick: ipss_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,am35xx-interface-clock"; +- clocks = <&core_l3_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <4>; +- }; +- +- rmii_ck: rmii_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- }; +- +- pclk_ck: pclk_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <27000000>; +- }; +- +- uart4_ick_am35xx: uart4_ick_am35xx@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <23>; +- }; +- +- uart4_fck_am35xx: uart4_fck_am35xx@a00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&core_48m_fck>; +- reg = <0x0a00>; +- ti,bit-shift = <23>; +- }; +-}; +- +-&cm_clockdomains { +- core_l3_clkdm: core_l3_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>, +- <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>, +- <&hecc_ck>; +- }; +- +- core_l4_clkdm: core_l4_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, +- <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>, +- <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, +- <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, +- <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, +- <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, +- <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, +- <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, +- <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, +- <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, +- <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, +- <&uart4_ick_am35xx>, <&uart4_fck_am35xx>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am3703.dtsi b/scripts/dtc/include-prefixes/arm/am3703.dtsi +deleted file mode 100644 +index 2b994ae790c9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am3703.dtsi ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2020 André Hentschel +- */ +- +-#include "omap36xx.dtsi" +- +-&iva { +- status = "disabled"; +-}; +- +-&sgx_module { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am3715.dtsi b/scripts/dtc/include-prefixes/arm/am3715.dtsi +deleted file mode 100644 +index ab328e8c0bd8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am3715.dtsi ++++ /dev/null +@@ -1,10 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2020 André Hentschel +- */ +- +-#include "omap36xx.dtsi" +- +-&iva { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am3874-iceboard.dts b/scripts/dtc/include-prefixes/arm/am3874-iceboard.dts +deleted file mode 100644 +index 9423e9feaa10..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am3874-iceboard.dts ++++ /dev/null +@@ -1,489 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device tree for Winterland IceBoard +- * +- * https://mcgillcosmology.com +- * https://threespeedlogic.com +- * +- * This is an ARM + FPGA instrumentation board used at telescopes in +- * Antarctica (the South Pole Telescope), Chile (POLARBEAR), and at the DRAO +- * observatory in British Columbia (CHIME). +- * +- * Copyright (c) 2019 Three-Speed Logic, Inc. +- */ +- +-/dts-v1/; +- +-#include "dm814x.dtsi" +-#include +- +-/ { +- model = "Winterland IceBoard"; +- compatible = "ti,dm8148", "ti,dm814"; +- +- chosen { +- stdout-path = "serial1:115200n8"; +- bootargs = "earlycon"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; /* 1 GB */ +- }; +- +- vmmcsd_fixed: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsd_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +-}; +- +-/* The MAC provides internal delay for the transmit path ONLY, which is enabled +- * provided no -id/-txid/-rxid suffix is provided to "phy-mode". +- * +- * The receive path is delayed at the PHY. The recommended register settings +- * are 0xf0 for the control bits, and 0x7777 for the data bits. However, the +- * conversion code in the kernel lies: the PHY's registers are 120 ps per tap, +- * and the kernel assumes 200 ps per tap. So we have fudged the numbers here to +- * obtain the correct register settings. +- */ +-&mac { dual_emac = <1>; }; +-&cpsw_emac0 { +- phy-handle = <ðphy0>; +- phy-mode = "rgmii"; +- dual_emac_res_vlan = <1>; +-}; +-&cpsw_emac1 { +- phy-handle = <ðphy1>; +- phy-mode = "rgmii"; +- dual_emac_res_vlan = <2>; +-}; +- +-&davinci_mdio { +- ethphy0: ethernet-phy@0 { +- reg = <0x2>; +- +- rxc-skew-ps = <3000>; +- rxdv-skew-ps = <0>; +- +- rxd3-skew-ps = <0>; +- rxd2-skew-ps = <0>; +- rxd1-skew-ps = <0>; +- rxd0-skew-ps = <0>; +- +- phy-reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; +- }; +- +- ethphy1: ethernet-phy@1 { +- reg = <0x1>; +- +- rxc-skew-ps = <3000>; +- rxdv-skew-ps = <0>; +- +- rxd3-skew-ps = <0>; +- rxd2-skew-ps = <0>; +- rxd1-skew-ps = <0>; +- rxd0-skew-ps = <0>; +- +- phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&mmc1 { status = "disabled"; }; +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- vmmc-supply = <&vmmcsd_fixed>; +- bus-width = <4>; +-}; +-&mmc3 { status = "disabled"; }; +- +-&i2c1 { +- /* Most I2C activity happens through this port, with the sole exception +- * of the backplane. Since there are multiply assigned addresses, the +- * "i2c-mux-idle-disconnect" is important. +- */ +- +- pca9548@70 { +- compatible = "nxp,pca9548"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-mux-idle-disconnect; +- +- i2c@0 { +- /* FMC A */ +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c@1 { +- /* FMC B */ +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- i2c@2 { +- /* QSFP A */ +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c@3 { +- /* QSFP B */ +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- i2c@4 { +- /* SFP */ +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- +- ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; }; +- ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; }; +- ina230@42 { compatible = "ti,ina230"; reg = <0x42>; shunt-resistor = <5000>; }; +- +- ina230@44 { compatible = "ti,ina230"; reg = <0x44>; shunt-resistor = <5000>; }; +- ina230@45 { compatible = "ti,ina230"; reg = <0x45>; shunt-resistor = <5000>; }; +- ina230@46 { compatible = "ti,ina230"; reg = <0x46>; shunt-resistor = <5000>; }; +- +- ina230@47 { compatible = "ti,ina230"; reg = <0x47>; shunt-resistor = <5500>; }; +- ina230@48 { compatible = "ti,ina230"; reg = <0x48>; shunt-resistor = <2360>; }; +- ina230@49 { compatible = "ti,ina230"; reg = <0x49>; shunt-resistor = <2360>; }; +- ina230@43 { compatible = "ti,ina230"; reg = <0x43>; shunt-resistor = <2360>; }; +- ina230@4b { compatible = "ti,ina230"; reg = <0x4b>; shunt-resistor = <5500>; }; +- ina230@4c { compatible = "ti,ina230"; reg = <0x4c>; shunt-resistor = <2360>; }; +- ina230@4d { compatible = "ti,ina230"; reg = <0x4d>; shunt-resistor = <770>; }; +- ina230@4e { compatible = "ti,ina230"; reg = <0x4e>; shunt-resistor = <770>; }; +- ina230@4f { compatible = "ti,ina230"; reg = <0x4f>; shunt-resistor = <770>; }; +- }; +- +- i2c@6 { +- /* Backplane */ +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- +- u41: pca9575@20 { +- compatible = "nxp,pca9575"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio-line-names = +- "FMCA_EN_12V0", "FMCA_EN_3V3", "FMCA_EN_VADJ", "FMCA_PG_M2C", +- "FMCA_PG_C2M", "FMCA_PRSNT_M2C_L", "FMCA_CLK_DIR", "SFP_LOS", +- "FMCB_EN_12V0", "FMCB_EN_3V3", "FMCB_EN_VADJ", "FMCB_PG_M2C", +- "FMCB_PG_C2M", "FMCB_PRSNT_M2C_L", "FMCB_CLK_DIR", "SFP_ModPrsL"; +- reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; +- }; +- +- u42: pca9575@21 { +- compatible = "nxp,pca9575"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-line-names = +- "QSFPA_ModPrsL", "QSFPA_IntL", "QSFPA_ResetL", "QSFPA_ModSelL", +- "QSFPA_LPMode", "QSFPB_ModPrsL", "QSFPB_IntL", "QSFPB_ResetL", +- "SFP_TxFault", "SFP_TxDisable", "SFP_RS0", "SFP_RS1", +- "QSFPB_ModSelL", "QSFPB_LPMode", "SEL_SFP", "ARM_MR"; +- reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; +- }; +- +- u48: pca9575@22 { +- compatible = "nxp,pca9575"; +- reg=<0x22>; +- gpio-controller; +- #gpio-cells = <2>; +- +- sw-gpios = <&u48 0 0>, <&u48 1 0>, <&u48 2 0>, <&u48 3 0>, +- <&u48 4 0>, <&u48 5 0>, <&u48 6 0>, <&u48 7 0>; +- led-gpios = <&u48 7 0>, <&u48 6 0>, <&u48 5 0>, <&u48 4 0>, +- <&u48 3 0>, <&u48 2 0>, <&u48 1 0>, <&u48 0 0>; +- +- gpio-line-names = +- "GP_SW1", "GP_SW2", "GP_SW3", "GP_SW4", +- "GP_SW5", "GP_SW6", "GP_SW7", "GP_SW8", +- "GP_LED8", "GP_LED7", "GP_LED6", "GP_LED5", +- "GP_LED4", "GP_LED3", "GP_LED2", "GP_LED1"; +- reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; +- }; +- +- u59: pca9575@23 { +- compatible = "nxp,pca9575"; +- reg=<0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-line-names = +- "GP_LED9", "GP_LED10", "GP_LED11", "GP_LED12", +- "GTX1V8PowerFault", "PHYAPowerFault", "PHYBPowerFault", "ArmPowerFault", +- "BP_SLOW_GPIO0", "BP_SLOW_GPIO1", "BP_SLOW_GPIO2", "BP_SLOW_GPIO3", +- "BP_SLOW_GPIO4", "BP_SLOW_GPIO5", "__unused_u59_p16", "__unused_u59_p17"; +- reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; +- }; +- +- tmp100@48 { compatible = "ti,tmp100"; reg = <0x48>; }; +- tmp100@4a { compatible = "ti,tmp100"; reg = <0x4a>; }; +- tmp100@4b { compatible = "ti,tmp100"; reg = <0x4b>; }; +- tmp100@4c { compatible = "ti,tmp100"; reg = <0x4c>; }; +- +- /* EEPROM bank and serial number are treated as separate devices */ +- at24c01@57 { compatible = "atmel,24c01"; reg = <0x57>; }; +- at24cs01@5f { compatible = "atmel,24cs01"; reg = <0x5f>; }; +- }; +- }; +-}; +- +-&i2c2 { +- pca9548@71 { +- compatible = "nxp,pca9548"; +- reg = <0x71>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@6 { +- /* Backplane */ +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- multi-master; +- +- /* All backplanes should have this -- it's how we know they're there. */ +- at24c08@54 { compatible="atmel,24c08"; reg=<0x54>; }; +- at24cs08@5c { compatible="atmel,24cs08"; reg=<0x5c>; }; +- +- /* 16 slot backplane */ +- tmp421@4d { compatible="ti,tmp421"; reg=<0x4d>; }; +- tmp421@4e { compatible="ti,tmp421"; reg=<0x4e>; }; +- ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <2360>; }; +- amc6821@18 { compatible = "ti,amc6821"; reg = <0x18>; }; +- +- /* Single slot backplane */ +- }; +- }; +-}; +- +-&pincntl { +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ +- DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ +- DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ +- DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ +- DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ +- DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ +- DM814X_IOPAD(0x0924, PIN_INPUT_PULLUP | 0x40) /* SD1_POW */ +- DM814X_IOPAD(0x0928, PIN_INPUT | 0x40) /* SD1_SDWP */ +- DM814X_IOPAD(0x093C, PIN_INPUT | 0x2) /* SD1_SDCD */ +- >; +- }; +- +- usb0_pins: pinmux_usb0_pins { +- pinctrl-single,pins = < +- DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ +- >; +- }; +- +- usb1_pins: pinmux_usb1_pins { +- pinctrl-single,pins = < +- DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ +- >; +- }; +- +- gpio1_pins: pinmux_gpio1_pins { +- pinctrl-single,pins = < +- DM814X_IOPAD(0x081c, PIN_OUTPUT | 0x80) /* PROGRAM_B */ +- DM814X_IOPAD(0x0820, PIN_INPUT | 0x80) /* INIT_B */ +- DM814X_IOPAD(0x0824, PIN_INPUT | 0x80) /* DONE */ +- +- DM814X_IOPAD(0x0838, PIN_INPUT_PULLUP | 0x80) /* FMCA_TMS */ +- DM814X_IOPAD(0x083c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TCK */ +- DM814X_IOPAD(0x0898, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDO */ +- DM814X_IOPAD(0x089c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDI */ +- DM814X_IOPAD(0x08ac, PIN_INPUT_PULLUP | 0x80) /* FMCA_TRST */ +- +- DM814X_IOPAD(0x08b0, PIN_INPUT_PULLUP | 0x80) /* FMCB_TMS */ +- DM814X_IOPAD(0x0a88, PIN_INPUT_PULLUP | 0x80) /* FMCB_TCK */ +- DM814X_IOPAD(0x0a8c, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDO */ +- DM814X_IOPAD(0x08bc, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDI */ +- DM814X_IOPAD(0x0a94, PIN_INPUT_PULLUP | 0x80) /* FMCB_TRST */ +- +- DM814X_IOPAD(0x08d4, PIN_INPUT_PULLUP | 0x80) /* FPGA_TMS */ +- DM814X_IOPAD(0x0aa8, PIN_INPUT_PULLUP | 0x80) /* FPGA_TCK */ +- DM814X_IOPAD(0x0adc, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDO */ +- DM814X_IOPAD(0x0ab0, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDI */ +- >; +- }; +- +- gpio2_pins: pinmux_gpio2_pins { +- pinctrl-single,pins = < +- DM814X_IOPAD(0x090c, PIN_INPUT_PULLUP | 0x80) /* PHY A IRQ */ +- DM814X_IOPAD(0x0910, PIN_INPUT_PULLUP | 0x80) /* PHY A RESET */ +- DM814X_IOPAD(0x08f4, PIN_INPUT_PULLUP | 0x80) /* PHY B IRQ */ +- DM814X_IOPAD(0x08f8, PIN_INPUT_PULLUP | 0x80) /* PHY B RESET */ +- +- //DM814X_IOPAD(0x0a14, PIN_INPUT_PULLUP | 0x80) /* ARM IRQ */ +- //DM814X_IOPAD(0x0900, PIN_INPUT | 0x80) /* GPIO IRQ */ +- DM814X_IOPAD(0x0a2c, PIN_INPUT_PULLUP | 0x80) /* GPIO RESET */ +- >; +- }; +- +- gpio4_pins: pinmux_gpio4_pins { +- pinctrl-single,pins = < +- /* The PLL doesn't react well to the SPI controller reset, so +- * we force the CS lines to pull up as GPIOs until we're ready. +- * See https://e2e.ti.com/support/processors/f/791/t/276011?Linux-support-for-AM3874-DM8148-in-Arago-linux-omap3 +- */ +- DM814X_IOPAD(0x0b3c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO0 */ +- DM814X_IOPAD(0x0b40, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO1 */ +- DM814X_IOPAD(0x0b44, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO2 */ +- DM814X_IOPAD(0x0b48, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO3 */ +- DM814X_IOPAD(0x0b4c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO4 */ +- DM814X_IOPAD(0x0b50, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO5 */ +- >; +- }; +- +- spi2_pins: pinmux_spi2_pins { +- pinctrl-single,pins = < +- DM814X_IOPAD(0x0950, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS1 as GPIO */ +- DM814X_IOPAD(0x0818, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS2 as GPIO */ +- >; +- }; +- +- spi4_pins: pinmux_spi4_pins { +- pinctrl-single,pins = < +- DM814X_IOPAD(0x0a7c, 0x20) +- DM814X_IOPAD(0x0b74, 0x20) +- DM814X_IOPAD(0x0b78, PIN_OUTPUT | 0x20) +- DM814X_IOPAD(0x0b7c, PIN_OUTPUT_PULLDOWN | 0x20) +- DM814X_IOPAD(0x0b80, PIN_INPUT | 0x20) +- >; +- }; +-}; +- +-&gpio1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio1_pins>; +- gpio-line-names = +- "", "PROGRAM_B", "INIT_B", "DONE", /* 0-3 */ +- "", "", "", "", /* 4-7 */ +- "FMCA_TMS", "FMCA_TCK", "FMCA_TDO", "FMCA_TDI", /* 8-11 */ +- "", "", "", "FMCA_TRST", /* 12-15 */ +- "FMCB_TMS", "FMCB_TCK", "FMCB_TDO", "FMCB_TDI", /* 16-19 */ +- "FMCB_TRST", "", "", "", /* 20-23 */ +- "FPGA_TMS", "FPGA_TCK", "FPGA_TDO", "FPGA_TDI", /* 24-27 */ +- "", "", "", ""; /* 28-31 */ +-}; +- +-&gpio2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio2_pins>; +- gpio-line-names = +- "PHYA_IRQ_N", "PHYA_RESET_N", "", "", /* 0-3 */ +- "", "", "", "PHYB_IRQ_N", /* 4-7 */ +- "PHYB_RESET_N", "ARM_IRQ", "GPIO_IRQ", ""; /* 8-11 */ +-}; +- +-&gpio3 { +- pinctrl-names = "default"; +- /*pinctrl-0 = <&gpio3_pins>;*/ +- gpio-line-names = +- "", "", "ARMClkSel0", "", /* 0-3 */ +- "EnFPGARef", "", "", "ARMClkSel1"; /* 4-7 */ +-}; +- +-&gpio4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio4_pins>; +- gpio-line-names = +- "BP_ARM_GPIO0", "BP_ARM_GPIO1", "BP_ARM_GPIO2", "BP_ARM_GPIO3", +- "BP_ARM_GPIO4", "BP_ARM_GPIO5"; +-}; +- +-&usb0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb0_pins>; +- dr_mode = "host"; +-}; +- +-&usb1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb1_pins>; +- dr_mode = "host"; +-}; +- +-&mcspi1 { +- s25fl256@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; +- +- fsbl@0 { +- /* 256 kB */ +- label = "U-Boot-min"; +- reg = <0 0x40000>; +- }; +- ssbl@1 { +- /* 512 kB */ +- label = "U-Boot"; +- reg = <0x40000 0x80000>; +- }; +- bootenv@2 { +- /* 256 kB */ +- label = "U-Boot Env"; +- reg = <0xc0000 0x40000>; +- }; +- kernel@3 { +- /* 4 MB */ +- label = "Kernel"; +- reg = <0x100000 0x400000>; +- }; +- ipmi@4 { +- label = "IPMI FRU"; +- reg = <0x500000 0x40000>; +- }; +- fs@5 { +- label = "File System"; +- reg = <0x540000 0x1ac0000>; +- }; +- }; +-}; +- +-&mcspi3 { +- /* DMA event numbers stolen from MCASP */ +- dmas = <&edma_xbar 8 0 16 &edma_xbar 9 0 17 +- &edma_xbar 10 0 18 &edma_xbar 11 0 19>; +- dma-names = "tx0", "rx0", "tx1", "rx1"; +-}; +- +-&mcspi4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi4_pins>; +- +- /* DMA event numbers stolen from MCASP, MCBSP */ +- dmas = <&edma_xbar 12 0 20 &edma_xbar 13 0 21>; +- dma-names = "tx0", "rx0"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am4372.dtsi b/scripts/dtc/include-prefixes/arm/am4372.dtsi +deleted file mode 100644 +index 61a1d88f9df6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am4372.dtsi ++++ /dev/null +@@ -1,804 +0,0 @@ +-/* +- * Device Tree Source for AM4372 SoC +- * +- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "ti,am4372", "ti,am43"; +- interrupt-parent = <&wakeupgen>; +- #address-cells = <1>; +- #size-cells = <1>; +- chosen { }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0>; +- }; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- serial5 = &uart5; +- ethernet0 = &cpsw_port1; +- ethernet1 = &cpsw_port2; +- spi0 = &qspi; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu: cpu@0 { +- compatible = "arm,cortex-a9"; +- enable-method = "ti,am4372"; +- device_type = "cpu"; +- reg = <0>; +- +- clocks = <&dpll_mpu_ck>; +- clock-names = "cpu"; +- +- operating-points-v2 = <&cpu0_opp_table>; +- +- clock-latency = <300000>; /* From omap-cpufreq driver */ +- cpu-idle-states = <&mpu_gate>; +- }; +- +- idle-states { +- mpu_gate: mpu_gate { +- compatible = "arm,idle-state"; +- entry-latency-us = <40>; +- exit-latency-us = <100>; +- min-residency-us = <300>; +- local-timer-stop; +- }; +- }; +- }; +- +- cpu0_opp_table: opp-table { +- compatible = "operating-points-v2-ti-cpu"; +- syscon = <&scm_conf>; +- +- opp50-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <950000 931000 969000>; +- opp-supported-hw = <0xFF 0x01>; +- opp-suspend; +- }; +- +- opp100-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <1100000 1078000 1122000>; +- opp-supported-hw = <0xFF 0x04>; +- }; +- +- opp120-720000000 { +- opp-hz = /bits/ 64 <720000000>; +- opp-microvolt = <1200000 1176000 1224000>; +- opp-supported-hw = <0xFF 0x08>; +- }; +- +- oppturbo-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <1260000 1234800 1285200>; +- opp-supported-hw = <0xFF 0x10>; +- }; +- +- oppnitro-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <1325000 1298500 1351500>; +- opp-supported-hw = <0xFF 0x20>; +- }; +- }; +- +- soc { +- compatible = "ti,omap-infra"; +- }; +- +- gic: interrupt-controller@48241000 { +- compatible = "arm,cortex-a9-gic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x48241000 0x1000>, +- <0x48240100 0x0100>; +- interrupt-parent = <&gic>; +- }; +- +- wakeupgen: interrupt-controller@48281000 { +- compatible = "ti,omap4-wugen-mpu"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x48281000 0x1000>; +- interrupt-parent = <&gic>; +- }; +- +- scu: scu@48240000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0x48240000 0x100>; +- }; +- +- global_timer: timer@48240200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0x48240200 0x100>; +- interrupts = ; +- interrupt-parent = <&gic>; +- clocks = <&mpu_periphclk>; +- }; +- +- local_timer: timer@48240600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x48240600 0x100>; +- interrupts = ; +- interrupt-parent = <&gic>; +- clocks = <&mpu_periphclk>; +- }; +- +- cache-controller@48242000 { +- compatible = "arm,pl310-cache"; +- reg = <0x48242000 0x1000>; +- cache-unified; +- cache-level = <2>; +- }; +- +- ocp@44000000 { +- compatible = "simple-pm-bus"; +- power-domains = <&prm_per>; +- clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- ti,no-idle; +- +- l3-noc@44000000 { +- compatible = "ti,am4372-l3-noc"; +- reg = <0x44000000 0x400000>, +- <0x44800000 0x400000>; +- interrupts = , +- ; +- }; +- +- l4_wkup: interconnect@44c00000 { +- }; +- l4_per: interconnect@48000000 { +- }; +- l4_fast: interconnect@4a000000 { +- }; +- +- target-module@4c000000 { +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- reg = <0x4c000000 0x4>; +- reg-names = "rev"; +- clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>; +- clock-names = "fck"; +- ti,no-idle; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4c000000 0x1000000>; +- +- emif: emif@0 { +- compatible = "ti,emif-am4372"; +- reg = <0 0x1000000>; +- interrupts = ; +- sram = <&pm_sram_code +- &pm_sram_data>; +- }; +- }; +- +- target-module@49000000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x49000000 0x4>; +- reg-names = "rev"; +- clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49000000 0x10000>; +- +- edma: dma@0 { +- compatible = "ti,edma3-tpcc"; +- reg = <0 0x10000>; +- reg-names = "edma3_cc"; +- interrupts = , +- , +- ; +- interrupt-names = "edma3_ccint", "edma3_mperr", +- "edma3_ccerrint"; +- dma-requests = <64>; +- #dma-cells = <2>; +- +- ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, +- <&edma_tptc2 0>; +- +- ti,edma-memcpy-channels = <58 59>; +- }; +- }; +- +- target-module@49800000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x49800000 0x4>, +- <0x49800010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = ; +- ti,sysc-sidle = , +- ; +- clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49800000 0x100000>; +- +- edma_tptc0: dma@0 { +- compatible = "ti,edma3-tptc"; +- reg = <0 0x100000>; +- interrupts = ; +- interrupt-names = "edma3_tcerrint"; +- }; +- }; +- +- target-module@49900000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x49900000 0x4>, +- <0x49900010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = ; +- ti,sysc-sidle = , +- ; +- clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49900000 0x100000>; +- +- edma_tptc1: dma@0 { +- compatible = "ti,edma3-tptc"; +- reg = <0 0x100000>; +- interrupts = ; +- interrupt-names = "edma3_tcerrint"; +- }; +- }; +- +- target-module@49a00000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x49a00000 0x4>, +- <0x49a00010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = ; +- ti,sysc-sidle = , +- ; +- clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49a00000 0x100000>; +- +- edma_tptc2: dma@0 { +- compatible = "ti,edma3-tptc"; +- reg = <0 0x100000>; +- interrupts = ; +- interrupt-names = "edma3_tcerrint"; +- }; +- }; +- +- target-module@47810000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x478102fc 0x4>, +- <0x47810110 0x4>, +- <0x47810114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x47810000 0x1000>; +- +- mmc3: mmc@0 { +- compatible = "ti,am437-sdhci"; +- ti,needs-special-reset; +- interrupts = ; +- reg = <0x0 0x1000>; +- status = "disabled"; +- }; +- }; +- +- sham_target: target-module@53100000 { +- compatible = "ti,sysc-omap3-sham", "ti,sysc"; +- reg = <0x53100100 0x4>, +- <0x53100110 0x4>, +- <0x53100114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l3_clkdm */ +- clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x53100000 0x1000>; +- +- sham: sham@0 { +- compatible = "ti,omap5-sham"; +- reg = <0 0x300>; +- dmas = <&edma 36 0>; +- dma-names = "rx"; +- interrupts = ; +- }; +- }; +- +- aes_target: target-module@53501000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x53501080 0x4>, +- <0x53501084 0x4>, +- <0x53501088 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l3_clkdm */ +- clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x53501000 0x1000>; +- +- aes: aes@0 { +- compatible = "ti,omap4-aes"; +- reg = <0 0xa0>; +- interrupts = ; +- dmas = <&edma 6 0>, +- <&edma 5 0>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- des_target: target-module@53701000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x53701030 0x4>, +- <0x53701034 0x4>, +- <0x53701038 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l3_clkdm */ +- clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x53701000 0x1000>; +- +- des: des@0 { +- compatible = "ti,omap4-des"; +- reg = <0 0xa0>; +- interrupts = ; +- dmas = <&edma 34 0>, +- <&edma 33 0>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- pruss_tm: target-module@54400000 { +- compatible = "ti,sysc-pruss", "ti,sysc"; +- reg = <0x54426000 0x4>, +- <0x54426004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | +- SYSC_PRUSS_SUB_MWAIT)>; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>; +- clock-names = "fck"; +- resets = <&prm_per 1>; +- reset-names = "rstctrl"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x54400000 0x80000>; +- +- pruss1: pruss@0 { +- compatible = "ti,am4376-pruss1"; +- reg = <0x0 0x40000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- pruss1_mem: memories@0 { +- reg = <0x0 0x2000>, +- <0x2000 0x2000>, +- <0x10000 0x8000>; +- reg-names = "dram0", "dram1", +- "shrdram2"; +- }; +- +- pruss1_cfg: cfg@26000 { +- compatible = "ti,pruss-cfg", "syscon"; +- reg = <0x26000 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x26000 0x2000>; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- pruss1_iepclk_mux: iepclk-mux@30 { +- reg = <0x30>; +- #clock-cells = <0>; +- clocks = <&sysclk_div>, /* icss_iep_gclk */ +- <&pruss_ocp_gclk>; /* icss_ocp_gclk */ +- }; +- }; +- }; +- +- pruss1_mii_rt: mii-rt@32000 { +- compatible = "ti,pruss-mii", "syscon"; +- reg = <0x32000 0x58>; +- }; +- +- pruss1_intc: interrupt-controller@20000 { +- compatible = "ti,pruss-intc"; +- reg = <0x20000 0x2000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "host_intr0", "host_intr1", +- "host_intr2", "host_intr3", +- "host_intr4", +- "host_intr6", "host_intr7"; +- ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ +- }; +- +- pru1_0: pru@34000 { +- compatible = "ti,am4376-pru"; +- reg = <0x34000 0x3000>, +- <0x22000 0x400>, +- <0x22400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am437x-pru1_0-fw"; +- }; +- +- pru1_1: pru@38000 { +- compatible = "ti,am4376-pru"; +- reg = <0x38000 0x3000>, +- <0x24000 0x400>, +- <0x24400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am437x-pru1_1-fw"; +- }; +- +- pruss1_mdio: mdio@32400 { +- compatible = "ti,davinci_mdio"; +- reg = <0x32400 0x90>; +- clocks = <&dpll_core_m4_ck>; +- clock-names = "fck"; +- bus_freq = <1000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- pruss0: pruss@40000 { +- compatible = "ti,am4376-pruss0"; +- reg = <0x40000 0x40000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- pruss0_mem: memories@40000 { +- reg = <0x40000 0x1000>, +- <0x42000 0x1000>; +- reg-names = "dram0", "dram1"; +- }; +- +- pruss0_cfg: cfg@66000 { +- compatible = "ti,pruss-cfg", "syscon"; +- reg = <0x66000 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x66000 0x2000>; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- pruss0_iepclk_mux: iepclk-mux@30 { +- reg = <0x30>; +- #clock-cells = <0>; +- clocks = <&sysclk_div>, /* icss_iep_gclk */ +- <&pruss_ocp_gclk>; /* icss_ocp_gclk */ +- }; +- }; +- }; +- +- pruss0_mii_rt: mii-rt@72000 { +- compatible = "ti,pruss-mii", "syscon"; +- reg = <0x72000 0x58>; +- status = "disabled"; +- }; +- +- pruss0_intc: interrupt-controller@60000 { +- compatible = "ti,pruss-intc"; +- reg = <0x60000 0x2000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "host_intr0", "host_intr1", +- "host_intr2", "host_intr3", +- "host_intr4", +- "host_intr6", "host_intr7"; +- ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ +- }; +- +- pru0_0: pru@74000 { +- compatible = "ti,am4376-pru"; +- reg = <0x74000 0x1000>, +- <0x62000 0x400>, +- <0x62400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am437x-pru0_0-fw"; +- }; +- +- pru0_1: pru@78000 { +- compatible = "ti,am4376-pru"; +- reg = <0x78000 0x1000>, +- <0x64000 0x400>, +- <0x64400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am437x-pru0_1-fw"; +- }; +- }; +- }; +- +- target-module@50000000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x50000000 4>, +- <0x50000010 4>, +- <0x50000014 4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ +- <0x00000000 0x00000000 0x40000000>; /* data */ +- +- gpmc: gpmc@50000000 { +- compatible = "ti,am3352-gpmc"; +- dmas = <&edma 52 0>; +- dma-names = "rxtx"; +- clocks = <&l3s_gclk>; +- clock-names = "fck"; +- reg = <0x50000000 0x2000>; +- interrupts = ; +- gpmc,num-cs = <7>; +- gpmc,num-waitpins = <2>; +- #address-cells = <2>; +- #size-cells = <1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- status = "disabled"; +- }; +- }; +- +- target-module@47900000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x47900000 0x4>, +- <0x47900010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- , +- ; +- clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x47900000 0x1000>, +- <0x30000000 0x30000000 0x4000000>; +- +- qspi: spi@0 { +- compatible = "ti,am4372-qspi"; +- reg = <0 0x100>, +- <0x30000000 0x4000000>; +- reg-names = "qspi_base", "qspi_mmap"; +- clocks = <&dpll_per_m2_div4_ck>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 138 0x4>; +- num-cs = <4>; +- }; +- }; +- +- target-module@40300000 { +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>; +- clock-names = "fck"; +- ti,no-idle; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x40300000 0x40000>; +- +- ocmcram: sram@0 { +- compatible = "mmio-sram"; +- reg = <0 0x40000>; /* 256k */ +- ranges = <0 0 0x40000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- pm_sram_code: pm-code-sram@0 { +- compatible = "ti,sram"; +- reg = <0x0 0x1000>; +- protect-exec; +- }; +- +- pm_sram_data: pm-data-sram@1000 { +- compatible = "ti,sram"; +- reg = <0x1000 0x1000>; +- pool; +- }; +- }; +- }; +- +- target-module@56000000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x5600fe00 0x4>, +- <0x5600fe10 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>; +- clock-names = "fck"; +- power-domains = <&prm_gfx>; +- resets = <&prm_gfx 0>; +- reset-names = "rstctrl"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x56000000 0x1000000>; +- }; +- }; +-}; +- +-#include "am437x-l4.dtsi" +-#include "am43xx-clocks.dtsi" +- +-&prcm { +- prm_mpu: prm@300 { +- compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x300 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_gfx: prm@400 { +- compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x400 0x100>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- prm_rtc: prm@500 { +- compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x500 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_tamper: prm@600 { +- compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x600 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_cefuse: prm@700 { +- compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x700 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_per: prm@800 { +- compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x800 0x100>; +- #reset-cells = <1>; +- #power-domain-cells = <0>; +- }; +- +- prm_wkup: prm@2000 { +- compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x2000 0x100>; +- #reset-cells = <1>; +- #power-domain-cells = <0>; +- }; +- +- prm_device: prm@4000 { +- compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x4000 0x100>; +- #reset-cells = <1>; +- }; +-}; +- +-/* Preferred always-on timer for clocksource */ +-&timer1_target { +- ti,no-reset-on-init; +- ti,no-idle; +- clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>, +- <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>; +- clock-names = "fck", "ick"; +- timer@0 { +- assigned-clocks = <&timer1_fck>; +- assigned-clock-parents = <&sys_clkin_ck>; +- }; +-}; +- +-/* Preferred timer for clockevent */ +-&timer2_target { +- ti,no-reset-on-init; +- ti,no-idle; +- clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>, +- <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>; +- clock-names = "fck", "ick"; +- timer@0 { +- assigned-clocks = <&timer2_fck>; +- assigned-clock-parents = <&sys_clkin_ck>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am437x-cm-t43.dts b/scripts/dtc/include-prefixes/arm/am437x-cm-t43.dts +deleted file mode 100644 +index 5ce8e684e7d3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am437x-cm-t43.dts ++++ /dev/null +@@ -1,422 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include "am4372.dtsi" +- +-/ { +- model = "CompuLab CM-T43"; +- compatible = "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"; +- +- leds { +- compatible = "gpio-leds"; +- +- ledb { +- label = "cm-t43:green"; +- gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- vmmc_3v3: fixedregulator-v3_3 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmc_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- enable-active-high; +- }; +-}; +- +-&am43xx_pinmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&cm_t43_led_pins>; +- +- cm_t43_led_pins: cm_t43_led_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0xa78, MUX_MODE7) +- >; +- }; +- +- i2c0_pins: i2c0_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ +- AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ +- >; +- }; +- +- emmc_pins: emmc_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0 */ +- AM4372_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1 */ +- AM4372_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2 */ +- AM4372_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3 */ +- AM4372_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad12.mmc1_dat4 */ +- AM4372_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad13.mmc1_dat5 */ +- AM4372_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad14.mmc1_dat6 */ +- AM4372_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad15.mmc1_dat7 */ +- AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ +- AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ +- >; +- }; +- +- spi0_pins: pinmux_spi0_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_sclk.spi0_sclk */ +- AM4372_IOPAD(0x954, PIN_INPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ +- AM4372_IOPAD(0x958, PIN_OUTPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ +- AM4372_IOPAD(0x95C, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ +- >; +- }; +- +- nand_flash_x8: nand_flash_x8 { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x800, PIN_INPUT | PULL_DISABLE | MUX_MODE0) +- AM4372_IOPAD(0x804, PIN_INPUT | PULL_DISABLE | MUX_MODE0) +- AM4372_IOPAD(0x808, PIN_INPUT | PULL_DISABLE | MUX_MODE0) +- AM4372_IOPAD(0x80c, PIN_INPUT | PULL_DISABLE | MUX_MODE0) +- AM4372_IOPAD(0x810, PIN_INPUT | PULL_DISABLE | MUX_MODE0) +- AM4372_IOPAD(0x814, PIN_INPUT | PULL_DISABLE | MUX_MODE0) +- AM4372_IOPAD(0x818, PIN_INPUT | PULL_DISABLE | MUX_MODE0) +- AM4372_IOPAD(0x81c, PIN_INPUT | PULL_DISABLE | MUX_MODE0) +- AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x898, PIN_OUTPUT_PULLDOWN | MUX_MODE0) +- AM4372_IOPAD(0x894, PIN_OUTPUT_PULLDOWN | MUX_MODE0) +- AM4372_IOPAD(0x890, PIN_OUTPUT_PULLDOWN | MUX_MODE0) +- AM4372_IOPAD(0x89c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) +- >; +- }; +- +- cpsw_default: cpsw_default { +- pinctrl-single,pins = < +- /* Slave 1 */ +- AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ +- AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ +- AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ +- AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ +- AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ +- AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ +- AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ +- AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ +- AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ +- AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ +- AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ +- AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ +- AM4372_IOPAD(0xa74, MUX_MODE3) +- /* Slave 2 */ +- AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.txen */ +- AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rxctl */ +- AM4372_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.txd3 */ +- AM4372_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.txd2 */ +- AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.txd1 */ +- AM4372_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.txd0 */ +- AM4372_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.tclk */ +- AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rclk */ +- AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rxd3 */ +- AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rxd2 */ +- AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rxd1 */ +- AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rxd0 */ +- AM4372_IOPAD(0xa38, MUX_MODE7) +- >; +- }; +- +- davinci_mdio_default: davinci_mdio_default { +- pinctrl-single,pins = < +- /* MDIO */ +- AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ +- AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ +- >; +- }; +-}; +- +-&gpmc { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&nand_flash_x8>; +- ranges = <0 0 0x08000000 0x1000000>; +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- ti,nand-ecc-opt = "bch8"; +- ti,elm-id = <&elm>; +- +- nand-bus-width = <8>; +- gpmc,device-width = <1>; +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-on-ns = <0>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- /* MTD partition table */ +- partition@0 { +- label = "kernel"; +- reg = <0x0 0x00980000>; +- }; +- partition@980000 { +- label = "dtb"; +- reg = <0x00980000 0x00080000>; +- }; +- partition@a00000 { +- label = "rootfs"; +- reg = <0x00a00000 0x0>; +- }; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- clock-frequency = <100000>; +- +- tps65218: tps65218@24 { +- compatible = "ti,tps65218"; +- reg = <0x24>; +- interrupts = ; /* NMIn */ +- interrupt-parent = <&gic>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- dcdc1: regulator-dcdc1 { +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <912000>; +- regulator-max-microvolt = <1144000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc2: regulator-dcdc2 { +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <912000>; +- regulator-max-microvolt = <1378000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc3: regulator-dcdc3 { +- regulator-name = "vdcdc3"; +- regulator-suspend-enable; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc5: regulator-dcdc5 { +- regulator-name = "v1_0bat"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc6: regulator-dcdc6 { +- regulator-name = "v1_8bat"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1: regulator-ldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- +- eeprom_module: at24@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +-}; +- +-&gpio0 { +- status = "okay"; +-}; +- +-&gpio1 { +- status = "okay"; +-}; +- +-&gpio2 { +- status = "okay"; +-}; +- +-&gpio3 { +- status = "okay"; +-}; +- +-&gpio4 { +- status = "okay"; +-}; +- +-&gpio5 { +- status = "okay"; +-}; +- +-&mmc2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_pins>; +- vmmc-supply = <&vmmc_3v3>; +- bus-width = <8>; +- non-removable; +-}; +- +-&spi0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins>; +- dmas = <&edma 16 0 +- &edma 17 0>; +- dma-names = "tx0", "rx0"; +- +- flash: w25q64cvzpig@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- partition@0 { +- label = "uboot"; +- reg = <0x0 0xc0000>; +- }; +- +- partition@c0000 { +- label = "uboot environment"; +- reg = <0xc0000 0x40000>; +- }; +- +- partition@100000 { +- label = "reserved"; +- reg = <0x100000 0x100000>; +- }; +- }; +-}; +- +-&mac_sw { +- pinctrl-names = "default"; +- pinctrl-0 = <&cpsw_default>; +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default"; +- pinctrl-0 = <&davinci_mdio_default>; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "rgmii-txid"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- phy-handle = <ðphy1>; +- phy-mode = "rgmii-txid"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&dwc3_1 { +- status = "okay"; +-}; +- +-&usb2_phy1 { +- status = "okay"; +-}; +- +-&usb1 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&dwc3_2 { +- status = "okay"; +-}; +- +-&usb2_phy2 { +- status = "okay"; +-}; +- +-&usb2 { +- dr_mode = "host"; +- status = "okay"; +- interrupts = , +- , +- ; +- interrupt-names = "peripheral", "host", "otg"; +-}; +- +-&elm { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&tscadc { +- status = "okay"; +- tsc { +- ti,wires = <4>; +- ti,x-plate-resistance = <200>; +- ti,coordiante-readouts = <5>; +- ti,wire-config = <0x00 0x11 0x22 0x33>; +- }; +- +- adc { +- ti,adc-channels = <4 5 6 7>; +- }; +-}; +- +-&cpu { +- cpu0-supply = <&dcdc2>; +- operating-points = <1000000 1330000>, +- <800000 1260000>, +- <720000 1200000>, +- <600000 1100000>, +- <300000 950000>; +-}; +- +-&pruss1_mdio { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am437x-gp-evm.dts b/scripts/dtc/include-prefixes/arm/am437x-gp-evm.dts +deleted file mode 100644 +index c2e4896076e7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am437x-gp-evm.dts ++++ /dev/null +@@ -1,1124 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/* AM437x GP EVM */ +- +-/dts-v1/; +- +-#include "am4372.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "TI AM437x GP EVM"; +- compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43"; +- +- aliases { +- display0 = &lcd0; +- }; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- evm_v3_3d: fixedregulator-v3_3d { +- compatible = "regulator-fixed"; +- regulator-name = "evm_v3_3d"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- }; +- +- vtt_fixed: fixedregulator-vtt { +- compatible = "regulator-fixed"; +- regulator-name = "vtt_fixed"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; +- }; +- +- vmmcwl_fixed: fixedregulator-mmcwl { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcwl_fixed"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- lcd_bl: backlight { +- compatible = "pwm-backlight"; +- pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; +- brightness-levels = <0 51 53 56 62 75 101 152 255>; +- default-brightness-level = <8>; +- }; +- +- matrix_keypad: matrix_keypad0 { +- compatible = "gpio-matrix-keypad"; +- debounce-delay-ms = <5>; +- col-scan-delay-us = <2>; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&matrix_keypad_default>; +- pinctrl-1 = <&matrix_keypad_sleep>; +- +- wakeup-source; +- +- row-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH /* Bank0, pin3 */ +- &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */ +- &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */ +- +- col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */ +- &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */ +- +- linux,keymap = <0x00000201 /* P1 */ +- 0x00010202 /* P2 */ +- 0x01000067 /* UP */ +- 0x0101006a /* RIGHT */ +- 0x02000069 /* LEFT */ +- 0x0201006c>; /* DOWN */ +- }; +- +- lcd0: display { +- compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; +- label = "lcd"; +- +- backlight = <&lcd_bl>; +- +- port { +- lcd_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- }; +- +- /* fixed 12MHz oscillator */ +- refclk: oscillator { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <12000000>; +- }; +- +- /* fixed 32k external oscillator clock */ +- clk_32k_rtc: clk_32k_rtc { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- sound0: sound0 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "AM437x-GP-EVM"; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack", +- "Line", "Line In"; +- simple-audio-card,routing = +- "Headphone Jack", "HPLOUT", +- "Headphone Jack", "HPROUT", +- "LINE1L", "Line In", +- "LINE1R", "Line In"; +- simple-audio-card,format = "dsp_b"; +- simple-audio-card,bitclock-master = <&sound0_master>; +- simple-audio-card,frame-master = <&sound0_master>; +- simple-audio-card,bitclock-inversion; +- +- simple-audio-card,cpu { +- sound-dai = <&mcasp1>; +- system-clock-frequency = <12000000>; +- }; +- +- sound0_master: simple-audio-card,codec { +- sound-dai = <&tlv320aic3106>; +- system-clock-frequency = <12000000>; +- }; +- }; +- +- beeper: beeper { +- compatible = "gpio-beeper"; +- pinctrl-names = "default"; +- pinctrl-0 = <&beeper_pins_default>; +- pinctrl-1 = <&beeper_pins_sleep>; +- gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&am43xx_pinmux { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default &unused_pins &debugss_pins>; +- pinctrl-1 = <&wlan_pins_sleep>; +- +- ddr3_vtt_toggle_default: ddr_vtt_toggle_default { +- pinctrl-single,pins = < +- 0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) /* spi0_cs0.gpio5_7 */ +- >; +- }; +- +- i2c0_pins: i2c0_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ +- AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ +- >; +- }; +- +- i2c1_pins: i2c1_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ +- AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ +- >; +- }; +- +- ecap0_pins: backlight_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ +- >; +- }; +- +- pixcir_ts_pins: pixcir_ts_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */ +- >; +- }; +- +- cpsw_default: cpsw_default { +- pinctrl-single,pins = < +- /* Slave 1 */ +- AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ +- AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ +- AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ +- AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ +- AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ +- AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ +- AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ +- AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ +- AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ +- AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ +- AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ +- AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ +- >; +- }; +- +- cpsw_sleep: cpsw_sleep { +- pinctrl-single,pins = < +- /* Slave 1 reset value */ +- AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- davinci_mdio_default: davinci_mdio_default { +- pinctrl-single,pins = < +- /* MDIO */ +- AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ +- AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ +- >; +- }; +- +- davinci_mdio_sleep: davinci_mdio_sleep { +- pinctrl-single,pins = < +- /* MDIO reset value */ +- AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- nand_flash_x8: nand_flash_x8 { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ +- AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ +- AM4372_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ +- AM4372_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ +- AM4372_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ +- AM4372_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ +- AM4372_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ +- AM4372_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ +- AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ +- AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ +- AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ +- AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ +- AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ +- AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ +- AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ +- >; +- }; +- +- dss_pins: dss_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ +- AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) +- AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) +- AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) +- AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) +- AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) +- AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) +- AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ +- AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ +- AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ +- AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ +- AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ +- AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ +- AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ +- +- >; +- }; +- +- display_mux_pins: display_mux_pins { +- pinctrl-single,pins = < +- /* GPIO 5_8 to select LCD / HDMI */ +- AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7) +- >; +- }; +- +- dcan0_default: dcan0_default_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ +- AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ +- >; +- }; +- +- dcan0_sleep: dcan0_sleep_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ +- AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ +- >; +- }; +- +- dcan1_default: dcan1_default_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */ +- AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */ +- >; +- }; +- +- dcan1_sleep: dcan1_sleep_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */ +- AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */ +- >; +- }; +- +- vpfe0_pins_default: vpfe0_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ +- AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ +- AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ +- AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ +- AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ +- AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ +- AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ +- AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ +- AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ +- AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ +- AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ +- AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ +- AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ +- >; +- }; +- +- vpfe0_pins_sleep: vpfe0_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/ +- AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/ +- AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/ +- AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/ +- AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/ +- AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/ +- AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/ +- AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/ +- AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/ +- AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/ +- AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/ +- AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/ +- AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/ +- >; +- }; +- +- vpfe1_pins_default: vpfe1_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/ +- AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/ +- AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/ +- AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/ +- AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/ +- AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/ +- AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/ +- AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/ +- AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/ +- AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/ +- AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/ +- AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/ +- AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/ +- >; +- }; +- +- vpfe1_pins_sleep: vpfe1_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/ +- AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/ +- AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/ +- AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/ +- AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/ +- AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/ +- AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/ +- AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/ +- AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/ +- AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/ +- AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/ +- AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/ +- AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/ +- >; +- }; +- +- mmc3_pins_default: pinmux_mmc3_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ +- AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ +- AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ +- AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ +- AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ +- AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */ +- >; +- }; +- +- mmc3_pins_sleep: pinmux_mmc3_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */ +- AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */ +- AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */ +- AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */ +- AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */ +- AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */ +- >; +- }; +- +- wlan_pins_default: pinmux_wlan_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ +- AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ +- AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ +- >; +- }; +- +- wlan_pins_sleep: pinmux_wlan_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ +- AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ +- AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ +- >; +- }; +- +- uart3_pins: uart3_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */ +- AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */ +- AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */ +- AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */ +- >; +- }; +- +- mcasp1_pins: mcasp1_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ +- AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ +- AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ +- AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ +- >; +- }; +- +- mcasp1_sleep_pins: mcasp1_sleep_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- gpio0_pins: gpio0_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */ +- >; +- }; +- +- emmc_pins_default: emmc_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ +- AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ +- AM4372_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ +- AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ +- AM4372_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ +- AM4372_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ +- AM4372_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ +- AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ +- AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ +- AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ +- >; +- }; +- +- emmc_pins_sleep: emmc_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */ +- AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */ +- AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */ +- AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */ +- AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ +- AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ +- AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ +- AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ +- AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */ +- AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */ +- >; +- }; +- +- beeper_pins_default: beeper_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */ +- >; +- }; +- +- beeper_pins_sleep: beeper_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam1_field.gpio4_12 */ +- >; +- }; +- +- unused_pins: unused_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xa3c, PIN_INPUT | PULL_DISABLE | MUX_MODE7) +- AM4372_IOPAD(0xa40, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xa44, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xa48, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xa4c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xa50, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xa54, PIN_INPUT | PULL_DISABLE | MUX_MODE7) +- AM4372_IOPAD(0xa58, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xa60, PIN_INPUT | PULL_DISABLE | MUX_MODE7) +- AM4372_IOPAD(0xa68, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xa70, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xa78, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xa7c, PIN_INPUT | PULL_DISABLE) +- AM4372_IOPAD(0xac8, PIN_INPUT_PULLDOWN) +- AM4372_IOPAD(0xad4, PIN_INPUT_PULLDOWN) +- AM4372_IOPAD(0xad8, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xadc, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xae0, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xae4, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xae8, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xaec, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xaf0, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xaf4, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xaf8, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xafc, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xb00, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xb04, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xb08, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xb0c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xb10, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xb14, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xb18, PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- debugss_pins: pinmux_debugss_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0xa90, PIN_INPUT_PULLDOWN) +- AM4372_IOPAD(0xa94, PIN_INPUT_PULLDOWN) +- AM4372_IOPAD(0xa98, PIN_INPUT_PULLDOWN) +- AM4372_IOPAD(0xa9c, PIN_INPUT_PULLDOWN) +- AM4372_IOPAD(0xaa0, PIN_INPUT_PULLDOWN) +- AM4372_IOPAD(0xaa4, PIN_INPUT_PULLDOWN) +- AM4372_IOPAD(0xaa8, PIN_INPUT_PULLDOWN) +- >; +- }; +- +- uart0_pins_default: uart0_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ +- AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ +- AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ +- AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ +- >; +- }; +- +- uart0_pins_sleep: uart0_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_ctsn.uart0_ctsn */ +- AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_rtsn.uart0_rtsn */ +- AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ +- AM4372_IOPAD(0x974, PIN_INPUT_PULLDOWN | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ +- >; +- }; +- +- matrix_keypad_default: matrix_keypad_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) +- AM4372_IOPAD(0x9a8, PIN_OUTPUT | MUX_MODE7) +- AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9) +- AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) +- >; +- }; +- +- matrix_keypad_sleep: matrix_keypad_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9a4, PULL_UP | MUX_MODE7) +- AM4372_IOPAD(0x9a8, PULL_UP | MUX_MODE7) +- AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9) +- AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) +- >; +- }; +-}; +- +-&uart0 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&uart0_pins_default>; +- pinctrl-1 = <&uart0_pins_sleep>; +-}; +- +-&i2c0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- clock-frequency = <100000>; +- +- tps65218: tps65218@24 { +- reg = <0x24>; +- compatible = "ti,tps65218"; +- interrupts = ; /* NMIn */ +- interrupt-controller; +- #interrupt-cells = <2>; +- +- dcdc1: regulator-dcdc1 { +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <912000>; +- regulator-max-microvolt = <1144000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc2: regulator-dcdc2 { +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <912000>; +- regulator-max-microvolt = <1378000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc3: regulator-dcdc3 { +- regulator-name = "vdcdc3"; +- regulator-boot-on; +- regulator-always-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- regulator-state-disk { +- regulator-off-in-suspend; +- }; +- }; +- +- dcdc5: regulator-dcdc5 { +- regulator-name = "v1_0bat"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- dcdc6: regulator-dcdc6 { +- regulator-name = "v1_8bat"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo1: regulator-ldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- +- ov2659@30 { +- compatible = "ovti,ov2659"; +- reg = <0x30>; +- +- clocks = <&refclk 0>; +- clock-names = "xvclk"; +- +- port { +- ov2659_0: endpoint { +- remote-endpoint = <&vpfe1_ep>; +- link-frequencies = /bits/ 64 <70000000>; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- pixcir_ts@5c { +- compatible = "pixcir,pixcir_tangoc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pixcir_ts_pins>; +- reg = <0x5c>; +- +- attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- +- /* +- * 0x264 represents the offset of padconf register of +- * gpio3_22 from am43xx_pinmux base. +- */ +- interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>, +- <&am43xx_pinmux 0x264>; +- interrupt-names = "tsc", "wakeup"; +- +- touchscreen-size-x = <1024>; +- touchscreen-size-y = <600>; +- wakeup-source; +- }; +- +- ov2659@30 { +- compatible = "ovti,ov2659"; +- reg = <0x30>; +- +- clocks = <&refclk 0>; +- clock-names = "xvclk"; +- +- port { +- ov2659_1: endpoint { +- remote-endpoint = <&vpfe0_ep>; +- link-frequencies = /bits/ 64 <70000000>; +- }; +- }; +- }; +- +- tlv320aic3106: tlv320aic3106@1b { +- #sound-dai-cells = <0>; +- compatible = "ti,tlv320aic3106"; +- reg = <0x1b>; +- status = "okay"; +- +- /* Regulators */ +- IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> EN: V1_8D -> VBAT */ +- AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ +- DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ +- DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */ +- }; +-}; +- +-&epwmss0 { +- status = "okay"; +-}; +- +-&tscadc { +- status = "okay"; +- +- adc { +- ti,adc-channels = <0 1 2 3 4 5 6 7>; +- }; +-}; +- +-&ecap0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ecap0_pins>; +-}; +- +-&gpio0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio0_pins>; +- status = "okay"; +- +- sel-emmc-nand-hog { +- gpio-hog; +- gpios = <23 GPIO_ACTIVE_HIGH>; +- /* SelEMMCorNAND selects between eMMC and NAND: +- * Low: NAND +- * High: eMMC +- * When changing this line make sure the newly +- * selected device node is enabled and the previously +- * selected device node is disabled. +- */ +- output-low; +- line-name = "SelEMMCorNAND"; +- }; +-}; +- +-&gpio1 { +- status = "okay"; +-}; +- +-&gpio3 { +- status = "okay"; +-}; +- +-&gpio4 { +- status = "okay"; +-}; +- +-&gpio5_target { +- ti,no-reset-on-init; +-}; +- +-&gpio5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&display_mux_pins>; +- status = "okay"; +- +- sel-lcd-hdmi-hog { +- /* +- * SelLCDorHDMI selects between display and audio paths: +- * Low: HDMI display with audio via HDMI +- * High: LCD display with analog audio via aic3111 codec +- */ +- gpio-hog; +- gpios = <8 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "SelLCDorHDMI"; +- }; +-}; +- +-&mmc1 { +- status = "okay"; +- vmmc-supply = <&evm_v3_3d>; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +-}; +- +-/* eMMC sits on mmc2 */ +-&mmc2 { +- /* +- * When enabling eMMC, disable GPMC/NAND and set +- * SelEMMCorNAND to output-high +- */ +- status = "disabled"; +- vmmc-supply = <&evm_v3_3d>; +- bus-width = <8>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&emmc_pins_default>; +- pinctrl-1 = <&emmc_pins_sleep>; +- non-removable; +-}; +- +-&mmc3 { +- status = "okay"; +- /* these are on the crossbar and are outlined in the +- xbar-event-map element */ +- dmas = <&edma_xbar 30 0 1>, +- <&edma_xbar 31 0 2>; +- dma-names = "tx", "rx"; +- vmmc-supply = <&vmmcwl_fixed>; +- bus-width = <4>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mmc3_pins_default>; +- pinctrl-1 = <&mmc3_pins_sleep>; +- cap-power-off-card; +- keep-power-in-suspend; +- non-removable; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@0 { +- compatible = "ti,wl1835"; +- reg = <2>; +- interrupt-parent = <&gpio1>; +- interrupts = <23 IRQ_TYPE_EDGE_RISING>; +- }; +-}; +- +-&uart3 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +-}; +- +-&usb2_phy1 { +- status = "okay"; +-}; +- +-&usb1 { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb2_phy2 { +- status = "okay"; +-}; +- +-&usb2 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&mac_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&cpsw_default>; +- pinctrl-1 = <&cpsw_sleep>; +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&davinci_mdio_default>; +- pinctrl-1 = <&davinci_mdio_sleep>; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "rgmii-rxid"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- status = "disabled"; +-}; +- +-&elm { +- status = "okay"; +-}; +- +-&gpmc { +- /* +- * When enabling GPMC, disable eMMC and set +- * SelEMMCorNAND to output-low +- */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&nand_flash_x8>; +- ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* device IO registers */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ +- ti,nand-xfer-type = "prefetch-dma"; +- ti,nand-ecc-opt = "bch16"; +- ti,elm-id = <&elm>; +- nand-bus-width = <8>; +- gpmc,device-width = <1>; +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <40>; +- gpmc,cs-wr-off-ns = <40>; +- gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <25>; +- gpmc,adv-wr-off-ns = <25>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <20>; +- gpmc,oe-on-ns = <3>; +- gpmc,oe-off-ns = <30>; +- gpmc,access-ns = <30>; +- gpmc,rd-cycle-ns = <40>; +- gpmc,wr-cycle-ns = <40>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- /* MTD partition table */ +- /* All SPL-* partitions are sized to minimal length +- * which can be independently programmable. For +- * NAND flash this is equal to size of erase-block */ +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "NAND.SPL"; +- reg = <0x00000000 0x00040000>; +- }; +- partition@1 { +- label = "NAND.SPL.backup1"; +- reg = <0x00040000 0x00040000>; +- }; +- partition@2 { +- label = "NAND.SPL.backup2"; +- reg = <0x00080000 0x00040000>; +- }; +- partition@3 { +- label = "NAND.SPL.backup3"; +- reg = <0x000c0000 0x00040000>; +- }; +- partition@4 { +- label = "NAND.u-boot-spl-os"; +- reg = <0x00100000 0x00080000>; +- }; +- partition@5 { +- label = "NAND.u-boot"; +- reg = <0x00180000 0x00100000>; +- }; +- partition@6 { +- label = "NAND.u-boot-env"; +- reg = <0x00280000 0x00040000>; +- }; +- partition@7 { +- label = "NAND.u-boot-env.backup1"; +- reg = <0x002c0000 0x00040000>; +- }; +- partition@8 { +- label = "NAND.kernel"; +- reg = <0x00300000 0x00700000>; +- }; +- partition@9 { +- label = "NAND.file-system"; +- reg = <0x00a00000 0x1f600000>; +- }; +- }; +-}; +- +-&dss { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_pins>; +- +- port { +- dpi_out: endpoint { +- remote-endpoint = <&lcd_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-&dcan0 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&dcan0_default>; +- pinctrl-1 = <&dcan0_sleep>; +- status = "okay"; +-}; +- +-&dcan1 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&dcan1_default>; +- pinctrl-1 = <&dcan1_sleep>; +- status = "okay"; +-}; +- +-&vpfe0 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&vpfe0_pins_default>; +- pinctrl-1 = <&vpfe0_pins_sleep>; +- +- port { +- vpfe0_ep: endpoint { +- remote-endpoint = <&ov2659_1>; +- ti,am437x-vpfe-interface = <0>; +- bus-width = <8>; +- hsync-active = <0>; +- vsync-active = <0>; +- }; +- }; +-}; +- +-&vpfe1 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&vpfe1_pins_default>; +- pinctrl-1 = <&vpfe1_pins_sleep>; +- +- port { +- vpfe1_ep: endpoint { +- remote-endpoint = <&ov2659_0>; +- ti,am437x-vpfe-interface = <0>; +- bus-width = <8>; +- hsync-active = <0>; +- vsync-active = <0>; +- }; +- }; +-}; +- +-&mcasp1 { +- #sound-dai-cells = <0>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mcasp1_pins>; +- pinctrl-1 = <&mcasp1_sleep_pins>; +- +- status = "okay"; +- +- op-mode = <0>; /* MCASP_IIS_MODE */ +- tdm-slots = <2>; +- /* 4 serializers */ +- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ +- 0 0 1 2 +- >; +- tx-num-evt = <32>; +- rx-num-evt = <32>; +-}; +- +-&rtc { +- clocks = <&clk_32k_rtc>, <&clk_32768_ck>; +- clock-names = "ext-clk", "int-clk"; +- status = "okay"; +-}; +- +-&cpu { +- cpu0-supply = <&dcdc2>; +-}; +- +-&pruss1_mdio { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am437x-idk-evm.dts b/scripts/dtc/include-prefixes/arm/am437x-idk-evm.dts +deleted file mode 100644 +index 53f64e3ce735..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am437x-idk-evm.dts ++++ /dev/null +@@ -1,543 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/dts-v1/; +- +-#include "am4372.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "TI AM437x Industrial Development Kit"; +- compatible = "ti,am437x-idk-evm","ti,am4372","ti,am43"; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- v24_0d: fixed-regulator-v24_0d { +- compatible = "regulator-fixed"; +- regulator-name = "V24_0D"; +- regulator-min-microvolt = <24000000>; +- regulator-max-microvolt = <24000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- v3_3d: fixed-regulator-v3_3d { +- compatible = "regulator-fixed"; +- regulator-name = "V3_3D"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&v24_0d>; +- }; +- +- vdd_corereg: fixed-regulator-vdd_corereg { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_COREREG"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&v24_0d>; +- }; +- +- vdd_core: fixed-regulator-vdd_core { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_CORE"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_corereg>; +- }; +- +- v1_8dreg: fixed-regulator-v1_8dreg{ +- compatible = "regulator-fixed"; +- regulator-name = "V1_8DREG"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&v24_0d>; +- }; +- +- v1_8d: fixed-regulator-v1_8d{ +- compatible = "regulator-fixed"; +- regulator-name = "V1_8D"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&v1_8dreg>; +- }; +- +- v1_5dreg: fixed-regulator-v1_5dreg{ +- compatible = "regulator-fixed"; +- regulator-name = "V1_5DREG"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&v24_0d>; +- }; +- +- v1_5d: fixed-regulator-v1_5d{ +- compatible = "regulator-fixed"; +- regulator-name = "V1_5D"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&v1_5dreg>; +- }; +- +- gpio_keys: gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_pins_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch0 { +- label = "power-button"; +- linux,code = ; +- gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- /* fixed 32k external oscillator clock */ +- clk_32k_rtc: clk_32k_rtc { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- leds-iio { +- status = "disabled"; +- compatible = "gpio-leds"; +- led-out0 { +- label = "out0"; +- gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out1 { +- label = "out1"; +- gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out2 { +- label = "out2"; +- gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out3 { +- label = "out3"; +- gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out4 { +- label = "out4"; +- gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out5 { +- label = "out5"; +- gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out6 { +- label = "out6"; +- gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out7 { +- label = "out7"; +- gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +-}; +- +-&am43xx_pinmux { +- gpio_keys_pins_default: gpio_keys_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9b8, PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */ +- >; +- }; +- +- i2c0_pins_default: i2c0_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ +- AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ +- >; +- }; +- +- i2c0_pins_sleep: i2c0_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- i2c2_pins_default: i2c2_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9e8, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */ +- AM4372_IOPAD(0x9ec, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */ +- >; +- }; +- +- i2c2_pins_sleep: i2c2_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9e8, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x9ec, PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- mmc1_pins_default: pinmux_mmc1_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ +- AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ +- AM4372_IOPAD(0x9f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ +- AM4372_IOPAD(0x9f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ +- AM4372_IOPAD(0x9f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ +- AM4372_IOPAD(0x9fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ +- AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ +- >; +- }; +- +- mmc1_pins_sleep: pinmux_mmc1_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x900, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x904, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x960, PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- spi1_pins_default: spi1_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x908, PIN_INPUT | MUX_MODE2) /* mii1_col.spi1_sclk */ +- AM4372_IOPAD(0x910, PIN_INPUT | MUX_MODE2) /* mii1_rx_er.spi1_d1 */ +- AM4372_IOPAD(0x944, PIN_OUTPUT | MUX_MODE2) /* rmii1_ref_clk.spi1_cs0 */ +- AM4372_IOPAD(0x90c, PIN_OUTPUT | MUX_MODE7) /* mii1_crs.gpio3_1 */ +- >; +- }; +- +- spi1_pins_sleep: spi1_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- ecap0_pins_default: backlight_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */ +- >; +- }; +- +- cpsw_default: cpsw_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ +- AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ +- AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ +- AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ +- AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ +- AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ +- AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ +- AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ +- AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ +- AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ +- AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ +- AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ +- >; +- }; +- +- cpsw_sleep: cpsw_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- davinci_mdio_default: davinci_mdio_default { +- pinctrl-single,pins = < +- /* MDIO */ +- AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ +- AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ +- >; +- }; +- +- davinci_mdio_sleep: davinci_mdio_sleep { +- pinctrl-single,pins = < +- /* MDIO reset value */ +- AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- qspi_pins_default: qspi_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */ +- AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ +- AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ +- AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ +- AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */ +- AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ +- >; +- }; +- +- qspi_pins_sleep: qspi_pins_sleep{ +- pinctrl-single,pins = < +- AM4372_IOPAD(0x87c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x898, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c0_pins_default>; +- pinctrl-1 = <&i2c0_pins_sleep>; +- clock-frequency = <400000>; +- +- at24@50 { +- compatible = "atmel,24c256"; +- pagesize = <64>; +- reg = <0x50>; +- }; +- +- tps: tps62362@60 { +- compatible = "ti,tps62362"; +- reg = <0x60>; +- regulator-name = "VDD_MPU"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1330000>; +- regulator-boot-on; +- regulator-always-on; +- ti,vsel0-state-high; +- ti,vsel1-state-high; +- vin-supply = <&v3_3d>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c2_pins_default>; +- pinctrl-1 = <&i2c2_pins_sleep>; +- clock-frequency = <100000>; +- +- tpic2810: tpic2810@60 { +- compatible = "ti,tpic2810"; +- reg = <0x60>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&spi1_pins_default>; +- pinctrl-1 = <&spi1_pins_sleep>; +- ti,pindir-d0-out-d1-in; +- +- sn65hvs882: sn65hvs882@0 { +- compatible = "pisosr-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- +- load-gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; +- +- reg = <0>; +- spi-max-frequency = <1000000>; +- spi-cpol; +- }; +-}; +- +-&epwmss0 { +- status = "okay"; +-}; +- +-&ecap0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ecap0_pins_default>; +-}; +- +-&gpio0 { +- status = "okay"; +-}; +- +-&gpio1 { +- status = "okay"; +-}; +- +-&gpio3 { +- status = "okay"; +-}; +- +-&gpio4 { +- status = "okay"; +-}; +- +-&gpio5 { +- status = "okay"; +-}; +- +-&mmc1 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mmc1_pins_default>; +- pinctrl-1 = <&mmc1_pins_sleep>; +- vmmc-supply = <&v3_3d>; +- bus-width = <4>; +- cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +-}; +- +-&qspi { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&qspi_pins_default>; +- pinctrl-1 = <&qspi_pins_sleep>; +- +- spi-max-frequency = <48000000>; +- m25p80@0 { +- compatible = "mx66l51235l"; +- spi-max-frequency = <48000000>; +- reg = <0>; +- spi-cpol; +- spi-cpha; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* +- * MTD partition table. The ROM checks the first 512KiB for a +- * valid file to boot(XIP). +- */ +- partition@0 { +- label = "QSPI.U_BOOT"; +- reg = <0x00000000 0x000080000>; +- }; +- partition@1 { +- label = "QSPI.U_BOOT.backup"; +- reg = <0x00080000 0x00080000>; +- }; +- partition@2 { +- label = "QSPI.U-BOOT-SPL_OS"; +- reg = <0x00100000 0x00010000>; +- }; +- partition@3 { +- label = "QSPI.U_BOOT_ENV"; +- reg = <0x00110000 0x00010000>; +- }; +- partition@4 { +- label = "QSPI.U-BOOT-ENV.backup"; +- reg = <0x00120000 0x00010000>; +- }; +- partition@5 { +- label = "QSPI.KERNEL"; +- reg = <0x00130000 0x0800000>; +- }; +- partition@6 { +- label = "QSPI.FILESYSTEM"; +- reg = <0x00930000 0x36D0000>; +- }; +- }; +-}; +- +-&mac_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&cpsw_default>; +- pinctrl-1 = <&cpsw_sleep>; +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&davinci_mdio_default>; +- pinctrl-1 = <&davinci_mdio_sleep>; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "rgmii-rxid"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- status = "disabled"; +-}; +- +-&rtc { +- clocks = <&clk_32k_rtc>, <&clk_32768_ck>; +- clock-names = "ext-clk", "int-clk"; +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +- +-&cpu { +- cpu0-supply = <&tps>; +-}; +- +-&cpu0_opp_table { +- /* +- * Supply voltage supervisor on board will not allow opp50 so +- * disable it and set opp100 as suspend OPP. +- */ +- opp50-300000000 { +- status = "disabled"; +- }; +- +- opp100-600000000 { +- opp-suspend; +- }; +-}; +- +-&pruss1_mdio { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am437x-l4.dtsi b/scripts/dtc/include-prefixes/arm/am437x-l4.dtsi +deleted file mode 100644 +index ba58e6b0da1d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am437x-l4.dtsi ++++ /dev/null +@@ -1,2557 +0,0 @@ +-&l4_wkup { /* 0x44c00000 */ +- compatible = "ti,am4-l4-wkup", "simple-pm-bus"; +- power-domains = <&prm_wkup>; +- clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>; +- clock-names = "fck"; +- reg = <0x44c00000 0x800>, +- <0x44c00800 0x800>, +- <0x44c01000 0x400>, +- <0x44c01400 0x400>; +- reg-names = "ap", "la", "ia0", "ia1"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ +- <0x00100000 0x44d00000 0x100000>, /* segment 1 */ +- <0x00200000 0x44e00000 0x100000>; /* segment 2 */ +- +- segment@0 { /* 0x44c00000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ +- <0x00000800 0x00000800 0x000800>, /* ap 1 */ +- <0x00001000 0x00001000 0x000400>, /* ap 2 */ +- <0x00001400 0x00001400 0x000400>; /* ap 3 */ +- }; +- +- segment@100000 { /* 0x44d00000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ +- <0x00004000 0x00104000 0x001000>, /* ap 5 */ +- <0x00080000 0x00180000 0x002000>, /* ap 6 */ +- <0x00082000 0x00182000 0x001000>, /* ap 7 */ +- <0x000f0000 0x001f0000 0x010000>; /* ap 8 */ +- +- target-module@0 { /* 0x44d00000, ap 4 28.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x0 0x4>; +- reg-names = "rev"; +- clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x4000>, +- <0x00080000 0x00080000 0x2000>; +- +- wkup_m3: cpu@0 { +- compatible = "ti,am4372-wkup-m3"; +- reg = <0x00000000 0x4000>, +- <0x00080000 0x2000>; +- reg-names = "umem", "dmem"; +- resets = <&prm_wkup 3>; +- reset-names = "rstctrl"; +- ti,pm-firmware = "am335x-pm-firmware.elf"; +- }; +- }; +- +- target-module@f0000 { /* 0x44df0000, ap 8 58.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xf0000 0x4>; +- reg-names = "rev"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf0000 0x10000>; +- +- prcm: prcm@0 { +- compatible = "ti,am4-prcm", "simple-bus"; +- reg = <0x0 0x11000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x11000>; +- +- prcm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- prcm_clockdomains: clockdomains { +- }; +- }; +- }; +- }; +- +- segment@200000 { /* 0x44e00000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00200000 0x001000>, /* ap 9 */ +- <0x00003000 0x00203000 0x001000>, /* ap 10 */ +- <0x00004000 0x00204000 0x001000>, /* ap 11 */ +- <0x00005000 0x00205000 0x001000>, /* ap 12 */ +- <0x00006000 0x00206000 0x001000>, /* ap 13 */ +- <0x00007000 0x00207000 0x001000>, /* ap 14 */ +- <0x00008000 0x00208000 0x001000>, /* ap 15 */ +- <0x00009000 0x00209000 0x001000>, /* ap 16 */ +- <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ +- <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ +- <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ +- <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ +- <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ +- <0x00010000 0x00210000 0x010000>, /* ap 22 */ +- <0x00030000 0x00230000 0x001000>, /* ap 23 */ +- <0x00031000 0x00231000 0x001000>, /* ap 24 */ +- <0x00032000 0x00232000 0x001000>, /* ap 25 */ +- <0x00033000 0x00233000 0x001000>, /* ap 26 */ +- <0x00034000 0x00234000 0x001000>, /* ap 27 */ +- <0x00035000 0x00235000 0x001000>, /* ap 28 */ +- <0x00036000 0x00236000 0x001000>, /* ap 29 */ +- <0x00037000 0x00237000 0x001000>, /* ap 30 */ +- <0x00038000 0x00238000 0x001000>, /* ap 31 */ +- <0x00039000 0x00239000 0x001000>, /* ap 32 */ +- <0x0003a000 0x0023a000 0x001000>, /* ap 33 */ +- <0x0003e000 0x0023e000 0x001000>, /* ap 34 */ +- <0x0003f000 0x0023f000 0x001000>, /* ap 35 */ +- <0x00040000 0x00240000 0x040000>, /* ap 36 */ +- <0x00080000 0x00280000 0x001000>, /* ap 37 */ +- <0x00088000 0x00288000 0x008000>, /* ap 38 */ +- <0x00092000 0x00292000 0x001000>, /* ap 39 */ +- <0x00086000 0x00286000 0x001000>, /* ap 40 */ +- <0x00087000 0x00287000 0x001000>, /* ap 41 */ +- <0x00090000 0x00290000 0x001000>, /* ap 42 */ +- <0x00091000 0x00291000 0x001000>; /* ap 43 */ +- +- target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3000 0x1000>; +- }; +- +- target-module@5000 { /* 0x44e05000, ap 12 30.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5000 0x1000>; +- }; +- +- target-module@7000 { /* 0x44e07000, ap 14 20.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x7000 0x4>, +- <0x7010 0x4>, +- <0x7114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ +- clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 0>, +- <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x7000 0x1000>; +- +- gpio0: gpio@0 { +- compatible = "ti,am4372-gpio","ti,omap4-gpio"; +- reg = <0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- }; +- +- target-module@9000 { /* 0x44e09000, ap 16 04.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x9050 0x4>, +- <0x9054 0x4>, +- <0x9058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ +- clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_UART1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x9000 0x1000>; +- +- uart0: serial@0 { +- compatible = "ti,am4372-uart"; +- reg = <0x0 0x2000>; +- interrupts = ; +- }; +- }; +- +- target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xb000 0x8>, +- <0xb010 0x8>, +- <0xb090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ +- clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_I2C1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xb000 0x1000>; +- +- i2c0: i2c@0 { +- compatible = "ti,am4372-i2c","ti,omap4-i2c"; +- reg = <0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xd000 0x4>, +- <0xd010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): wkup_pwrdm, l3s_tsc_clkdm */ +- clocks = <&l3s_tsc_clkctrl AM4_L3S_TSC_ADC_TSC_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xd000 0x1000>; +- +- tscadc: tscadc@0 { +- compatible = "ti,am3359-tscadc"; +- reg = <0x0 0x1000>; +- interrupts = ; +- clocks = <&adc_tsc_fck>; +- clock-names = "fck"; +- status = "disabled"; +- dmas = <&edma 53 0>, <&edma 57 0>; +- dma-names = "fifo0", "fifo1"; +- +- tsc { +- compatible = "ti,am3359-tsc"; +- }; +- +- adc { +- #io-channel-cells = <1>; +- compatible = "ti,am3359-adc"; +- }; +- +- }; +- }; +- +- target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x10000 0x4>; +- reg-names = "rev"; +- clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_CONTROL_CLKCTRL 0>; +- clock-names = "fck"; +- ti,no-idle; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10000 0x10000>; +- +- scm: scm@0 { +- compatible = "ti,am4-scm", "simple-bus"; +- reg = <0x0 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x4000>; +- +- am43xx_pinmux: pinmux@800 { +- compatible = "ti,am437-padconf", +- "pinctrl-single"; +- reg = <0x800 0x31c>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <1>; +- #interrupt-cells = <1>; +- interrupt-controller; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0xffffffff>; +- }; +- +- scm_conf: scm_conf@0 { +- compatible = "syscon", "simple-bus"; +- reg = <0x0 0x800>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- phy_gmii_sel: phy-gmii-sel { +- compatible = "ti,am43xx-phy-gmii-sel"; +- reg = <0x650 0x4>; +- #phy-cells = <2>; +- }; +- +- scm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- wkup_m3_ipc: wkup_m3_ipc@1324 { +- compatible = "ti,am4372-wkup-m3-ipc"; +- reg = <0x1324 0x44>; +- interrupts = ; +- ti,rproc = <&wkup_m3>; +- mboxes = <&mailbox &mbox_wkupm3>; +- }; +- +- edma_xbar: dma-router@f90 { +- compatible = "ti,am335x-edma-crossbar"; +- reg = <0xf90 0x40>; +- #dma-cells = <3>; +- dma-requests = <64>; +- dma-masters = <&edma>; +- }; +- +- scm_clockdomains: clockdomains { +- }; +- }; +- }; +- +- timer1_target: target-module@31000 { /* 0x44e31000, ap 24 40.0 */ +- compatible = "ti,sysc-omap2-timer", "ti,sysc"; +- reg = <0x31000 0x4>, +- <0x31010 0x4>, +- <0x31014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ +- clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x31000 0x1000>; +- +- timer1: timer@0 { +- compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms"; +- reg = <0x0 0x400>; +- interrupts = ; +- ti,timer-alwon; +- clocks = <&timer1_fck>; +- clock-names = "fck"; +- }; +- }; +- +- target-module@33000 { /* 0x44e33000, ap 26 18.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x33000 0x1000>; +- }; +- +- target-module@35000 { /* 0x44e35000, ap 28 50.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x35000 0x4>, +- <0x35010 0x4>, +- <0x35014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ +- clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_WD_TIMER2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x35000 0x1000>; +- +- wdt: wdt@0 { +- compatible = "ti,am4372-wdt","ti,omap3-wdt"; +- reg = <0x0 0x1000>; +- interrupts = ; +- }; +- }; +- +- target-module@37000 { /* 0x44e37000, ap 30 08.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x37000 0x1000>; +- }; +- +- target-module@39000 { /* 0x44e39000, ap 32 02.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x39000 0x1000>; +- }; +- +- rtc_target: target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */ +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- reg = <0x3e074 0x4>, +- <0x3e078 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ +- power-domains = <&prm_rtc>; +- clocks = <&l4_rtc_clkctrl AM4_L4_RTC_RTC_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3e000 0x1000>; +- +- rtc: rtc@0 { +- compatible = "ti,am4372-rtc", "ti,am3352-rtc", +- "ti,da830-rtc"; +- reg = <0x0 0x1000>; +- interrupts = ; +- clocks = <&clk_32768_ck>; +- clock-names = "int-clk"; +- system-power-controller; +- status = "disabled"; +- }; +- }; +- +- target-module@40000 { /* 0x44e40000, ap 36 68.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x40000 0x40000>; +- }; +- +- target-module@86000 { /* 0x44e86000, ap 40 70.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x86000 0x4>, +- <0x86004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- ; +- /* Domains (P, C): wkup_pwrdm, l4_wkup_aon_clkdm */ +- clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x86000 0x1000>; +- +- counter32k: counter@0 { +- compatible = "ti,am4372-counter32k","ti,omap-counter32k"; +- reg = <0x0 0x40>; +- }; +- }; +- +- target-module@88000 { /* 0x44e88000, ap 38 12.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00088000 0x00008000>, +- <0x00008000 0x00090000 0x00001000>, +- <0x00009000 0x00091000 0x00001000>; +- }; +- }; +-}; +- +-&l4_fast { /* 0x4a000000 */ +- compatible = "ti,am4-l4-fast", "simple-pm-bus"; +- power-domains = <&prm_per>; +- clocks = <&l3_clkctrl AM4_L3_L4_HS_CLKCTRL 0>; +- clock-names = "fck"; +- reg = <0x4a000000 0x800>, +- <0x4a000800 0x800>, +- <0x4a001000 0x400>; +- reg-names = "ap", "la", "ia0"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ +- +- segment@0 { /* 0x4a000000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ +- <0x00000800 0x00000800 0x000800>, /* ap 1 */ +- <0x00001000 0x00001000 0x000400>, /* ap 2 */ +- <0x00100000 0x00100000 0x008000>, /* ap 3 */ +- <0x00108000 0x00108000 0x001000>, /* ap 4 */ +- <0x00400000 0x00400000 0x002000>, /* ap 5 */ +- <0x00402000 0x00402000 0x001000>, /* ap 6 */ +- <0x00200000 0x00200000 0x080000>, /* ap 7 */ +- <0x00280000 0x00280000 0x001000>; /* ap 8 */ +- +- target-module@100000 { /* 0x4a100000, ap 3 04.0 */ +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- reg = <0x101200 0x4>, +- <0x101208 0x4>, +- <0x101204 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <0>; +- ti,sysc-midle = , +- ; +- ti,sysc-sidle = , +- ; +- ti,syss-mask = <1>; +- clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x100000 0x8000>; +- +- mac_sw: switch@0 { +- compatible = "ti,am4372-cpsw-switch", "ti,cpsw-switch"; +- reg = <0x0 0x4000>; +- ranges = <0 0 0x4000>; +- clocks = <&cpsw_125mhz_gclk>, <&dpll_clksel_mac_clk>; +- clock-names = "fck", "50mclk"; +- assigned-clocks = <&dpll_clksel_mac_clk>; +- assigned-clock-rates = <50000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- syscon = <&scm_conf>; +- status = "disabled"; +- +- interrupts = ; +- interrupt-names = "rx_thresh", "rx", "tx", "misc"; +- +- ethernet-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpsw_port1: port@1 { +- reg = <1>; +- label = "port1"; +- mac-address = [ 00 00 00 00 00 00 ]; +- phys = <&phy_gmii_sel 1 0>; +- }; +- +- cpsw_port2: port@2 { +- reg = <2>; +- label = "port2"; +- mac-address = [ 00 00 00 00 00 00 ]; +- phys = <&phy_gmii_sel 2 0>; +- }; +- }; +- +- davinci_mdio_sw: mdio@1000 { +- compatible = "ti,am4372-mdio", "ti,cpsw-mdio","ti,davinci_mdio"; +- clocks = <&cpsw_125mhz_gclk>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <0>; +- bus_freq = <1000000>; +- reg = <0x1000 0x100>; +- }; +- +- cpts { +- clocks = <&cpsw_cpts_rft_clk>; +- clock-names = "cpts"; +- }; +- }; +- }; +- +- target-module@200000 { /* 0x4a200000, ap 7 02.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x200000 0x80000>; +- }; +- +- target-module@400000 { /* 0x4a400000, ap 5 08.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x400000 0x2000>; +- }; +- }; +-}; +- +-&l4_per { /* 0x48000000 */ +- compatible = "ti,am4-l4-per", "simple-pm-bus"; +- power-domains = <&prm_per>; +- clocks = <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>; +- clock-names = "fck"; +- reg = <0x48000000 0x800>, +- <0x48000800 0x800>, +- <0x48001000 0x400>, +- <0x48001400 0x400>, +- <0x48001800 0x400>, +- <0x48001c00 0x400>; +- reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ +- <0x00100000 0x48100000 0x100000>, /* segment 1 */ +- <0x00200000 0x48200000 0x100000>, /* segment 2 */ +- <0x00300000 0x48300000 0x100000>, /* segment 3 */ +- <0x46000000 0x46000000 0x400000>, /* l3 data port */ +- <0x46400000 0x46400000 0x400000>; /* l3 data port */ +- +- segment@0 { /* 0x48000000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ +- <0x00000800 0x00000800 0x000800>, /* ap 1 */ +- <0x00001000 0x00001000 0x000400>, /* ap 2 */ +- <0x00001400 0x00001400 0x000400>, /* ap 3 */ +- <0x00001800 0x00001800 0x000400>, /* ap 4 */ +- <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ +- <0x00008000 0x00008000 0x001000>, /* ap 6 */ +- <0x00009000 0x00009000 0x001000>, /* ap 7 */ +- <0x00022000 0x00022000 0x001000>, /* ap 8 */ +- <0x00023000 0x00023000 0x001000>, /* ap 9 */ +- <0x00024000 0x00024000 0x001000>, /* ap 10 */ +- <0x00025000 0x00025000 0x001000>, /* ap 11 */ +- <0x0002a000 0x0002a000 0x001000>, /* ap 12 */ +- <0x0002b000 0x0002b000 0x001000>, /* ap 13 */ +- <0x00038000 0x00038000 0x002000>, /* ap 14 */ +- <0x0003a000 0x0003a000 0x001000>, /* ap 15 */ +- <0x0003c000 0x0003c000 0x002000>, /* ap 16 */ +- <0x0003e000 0x0003e000 0x001000>, /* ap 17 */ +- <0x00040000 0x00040000 0x001000>, /* ap 18 */ +- <0x00041000 0x00041000 0x001000>, /* ap 19 */ +- <0x00042000 0x00042000 0x001000>, /* ap 20 */ +- <0x00043000 0x00043000 0x001000>, /* ap 21 */ +- <0x00044000 0x00044000 0x001000>, /* ap 22 */ +- <0x00045000 0x00045000 0x001000>, /* ap 23 */ +- <0x00046000 0x00046000 0x001000>, /* ap 24 */ +- <0x00047000 0x00047000 0x001000>, /* ap 25 */ +- <0x00048000 0x00048000 0x001000>, /* ap 26 */ +- <0x00049000 0x00049000 0x001000>, /* ap 27 */ +- <0x0004c000 0x0004c000 0x001000>, /* ap 28 */ +- <0x0004d000 0x0004d000 0x001000>, /* ap 29 */ +- <0x00060000 0x00060000 0x001000>, /* ap 30 */ +- <0x00061000 0x00061000 0x001000>, /* ap 31 */ +- <0x00080000 0x00080000 0x010000>, /* ap 32 */ +- <0x00090000 0x00090000 0x001000>, /* ap 33 */ +- <0x00030000 0x00030000 0x001000>, /* ap 65 */ +- <0x00031000 0x00031000 0x001000>, /* ap 66 */ +- <0x0004a000 0x0004a000 0x001000>, /* ap 71 */ +- <0x0004b000 0x0004b000 0x001000>, /* ap 72 */ +- <0x000c8000 0x000c8000 0x001000>, /* ap 73 */ +- <0x000c9000 0x000c9000 0x001000>, /* ap 74 */ +- <0x000ca000 0x000ca000 0x001000>, /* ap 77 */ +- <0x000cb000 0x000cb000 0x001000>, /* ap 78 */ +- <0x00034000 0x00034000 0x001000>, /* ap 80 */ +- <0x00035000 0x00035000 0x001000>, /* ap 81 */ +- <0x00036000 0x00036000 0x001000>, /* ap 84 */ +- <0x00037000 0x00037000 0x001000>, /* ap 85 */ +- <0x46000000 0x46000000 0x400000>, /* l3 data port */ +- <0x46400000 0x46400000 0x400000>; /* l3 data port */ +- +- target-module@8000 { /* 0x48008000, ap 6 10.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x8000 0x1000>; +- }; +- +- target-module@22000 { /* 0x48022000, ap 8 0a.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x22050 0x4>, +- <0x22054 0x4>, +- <0x22058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_UART2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x22000 0x1000>; +- +- uart1: serial@0 { +- compatible = "ti,am4372-uart"; +- reg = <0x0 0x2000>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- target-module@24000 { /* 0x48024000, ap 10 1c.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x24050 0x4>, +- <0x24054 0x4>, +- <0x24058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_UART3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x24000 0x1000>; +- +- uart2: serial@0 { +- compatible = "ti,am4372-uart"; +- reg = <0x0 0x2000>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- target-module@2a000 { /* 0x4802a000, ap 12 22.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x2a000 0x8>, +- <0x2a010 0x8>, +- <0x2a090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_I2C2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2a000 0x1000>; +- +- i2c1: i2c@0 { +- compatible = "ti,am4372-i2c","ti,omap4-i2c"; +- reg = <0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- target-module@30000 { /* 0x48030000, ap 65 08.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x30000 0x4>, +- <0x30110 0x4>, +- <0x30114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_SPI0_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x30000 0x1000>; +- +- spi0: spi@0 { +- compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; +- reg = <0x0 0x400>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- target-module@34000 { /* 0x48034000, ap 80 56.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x34000 0x1000>; +- }; +- +- target-module@36000 { /* 0x48036000, ap 84 3e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x36000 0x1000>; +- }; +- +- target-module@38000 { /* 0x48038000, ap 14 04.0 */ +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- reg = <0x38000 0x4>, +- <0x38004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): per_pwrdm, l3s_clkdm */ +- clocks = <&l3s_clkctrl AM4_L3S_MCASP0_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x38000 0x2000>, +- <0x46000000 0x46000000 0x400000>; +- +- mcasp0: mcasp@0 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x0 0x2000>, +- <0x46000000 0x400000>; +- reg-names = "mpu", "dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- status = "disabled"; +- dmas = <&edma 8 2>, +- <&edma 9 2>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@3c000 { /* 0x4803c000, ap 16 2a.0 */ +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- reg = <0x3c000 0x4>, +- <0x3c004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): per_pwrdm, l3s_clkdm */ +- clocks = <&l3s_clkctrl AM4_L3S_MCASP1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3c000 0x2000>, +- <0x46400000 0x46400000 0x400000>; +- +- mcasp1: mcasp@0 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x0 0x2000>, +- <0x46400000 0x400000>; +- reg-names = "mpu", "dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- status = "disabled"; +- dmas = <&edma 10 2>, +- <&edma 11 2>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- timer2_target: target-module@40000 { /* 0x48040000, ap 18 1e.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x40000 0x4>, +- <0x40010 0x4>, +- <0x40014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x40000 0x1000>; +- +- timer2: timer@0 { +- compatible = "ti,am4372-timer","ti,am335x-timer"; +- reg = <0x0 0x400>; +- interrupts = ; +- clocks = <&timer2_fck>; +- clock-names = "fck"; +- }; +- }; +- +- target-module@42000 { /* 0x48042000, ap 20 24.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x42000 0x4>, +- <0x42010 0x4>, +- <0x42014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_TIMER3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x42000 0x1000>; +- +- timer3: timer@0 { +- compatible = "ti,am4372-timer","ti,am335x-timer"; +- reg = <0x0 0x400>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- target-module@44000 { /* 0x48044000, ap 22 26.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x44000 0x4>, +- <0x44010 0x4>, +- <0x44014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_TIMER4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x44000 0x1000>; +- +- timer4: timer@0 { +- compatible = "ti,am4372-timer","ti,am335x-timer"; +- reg = <0x0 0x400>; +- interrupts = ; +- ti,timer-pwm; +- status = "disabled"; +- }; +- }; +- +- target-module@46000 { /* 0x48046000, ap 24 28.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x46000 0x4>, +- <0x46010 0x4>, +- <0x46014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_TIMER5_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x46000 0x1000>; +- +- timer5: timer@0 { +- compatible = "ti,am4372-timer","ti,am335x-timer"; +- reg = <0x0 0x400>; +- interrupts = ; +- ti,timer-pwm; +- status = "disabled"; +- }; +- }; +- +- target-module@48000 { /* 0x48048000, ap 26 1a.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x48000 0x4>, +- <0x48010 0x4>, +- <0x48014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_TIMER6_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x48000 0x1000>; +- +- timer6: timer@0 { +- compatible = "ti,am4372-timer","ti,am335x-timer"; +- reg = <0x0 0x400>; +- interrupts = ; +- ti,timer-pwm; +- status = "disabled"; +- }; +- }; +- +- target-module@4a000 { /* 0x4804a000, ap 71 48.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x4a000 0x4>, +- <0x4a010 0x4>, +- <0x4a014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_TIMER7_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4a000 0x1000>; +- +- timer7: timer@0 { +- compatible = "ti,am4372-timer","ti,am335x-timer"; +- reg = <0x0 0x400>; +- interrupts = ; +- ti,timer-pwm; +- status = "disabled"; +- }; +- }; +- +- target-module@4c000 { /* 0x4804c000, ap 28 36.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4c000 0x4>, +- <0x4c010 0x4>, +- <0x4c114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 0>, +- <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4c000 0x1000>; +- +- gpio1: gpio@0 { +- compatible = "ti,am4372-gpio","ti,omap4-gpio"; +- reg = <0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- }; +- +- target-module@60000 { /* 0x48060000, ap 30 14.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x602fc 0x4>, +- <0x60110 0x4>, +- <0x60114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_MMC1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x60000 0x1000>; +- +- mmc1: mmc@0 { +- compatible = "ti,am437-sdhci"; +- reg = <0x0 0x1000>; +- ti,needs-special-reset; +- dmas = <&edma 24 0>, +- <&edma 25 0>; +- dma-names = "tx", "rx"; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- target-module@80000 { /* 0x48080000, ap 32 18.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x80000 0x4>, +- <0x80010 0x4>, +- <0x80014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_ELM_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x80000 0x10000>; +- +- elm: elm@0 { +- compatible = "ti,am3352-elm"; +- reg = <0x0 0x2000>; +- interrupts = ; +- clocks = <&l4ls_gclk>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- }; +- +- target-module@c8000 { /* 0x480c8000, ap 73 06.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xc8000 0x4>, +- <0xc8010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_MAILBOX_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc8000 0x1000>; +- +- mailbox: mailbox@0 { +- compatible = "ti,omap4-mailbox"; +- reg = <0x0 0x200>; +- interrupts = ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <8>; +- mbox_wkupm3: mbox-wkup-m3 { +- ti,mbox-send-noirq; +- ti,mbox-tx = <0 0 0>; +- ti,mbox-rx = <0 0 3>; +- }; +- }; +- }; +- +- target-module@ca000 { /* 0x480ca000, ap 77 38.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xca000 0x4>, +- <0xca010 0x4>, +- <0xca014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_SPINLOCK_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xca000 0x1000>; +- +- hwspinlock: spinlock@0 { +- compatible = "ti,omap4-hwspinlock"; +- reg = <0x0 0x1000>; +- #hwlock-cells = <1>; +- }; +- }; +- }; +- +- segment@100000 { /* 0x48100000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 34 */ +- <0x0008d000 0x0018d000 0x001000>, /* ap 35 */ +- <0x0008e000 0x0018e000 0x001000>, /* ap 36 */ +- <0x0008f000 0x0018f000 0x001000>, /* ap 37 */ +- <0x0009c000 0x0019c000 0x001000>, /* ap 38 */ +- <0x0009d000 0x0019d000 0x001000>, /* ap 39 */ +- <0x000a6000 0x001a6000 0x001000>, /* ap 40 */ +- <0x000a7000 0x001a7000 0x001000>, /* ap 41 */ +- <0x000a8000 0x001a8000 0x001000>, /* ap 42 */ +- <0x000a9000 0x001a9000 0x001000>, /* ap 43 */ +- <0x000aa000 0x001aa000 0x001000>, /* ap 44 */ +- <0x000ab000 0x001ab000 0x001000>, /* ap 45 */ +- <0x000ac000 0x001ac000 0x001000>, /* ap 46 */ +- <0x000ad000 0x001ad000 0x001000>, /* ap 47 */ +- <0x000ae000 0x001ae000 0x001000>, /* ap 48 */ +- <0x000af000 0x001af000 0x001000>, /* ap 49 */ +- <0x000cc000 0x001cc000 0x002000>, /* ap 50 */ +- <0x000ce000 0x001ce000 0x002000>, /* ap 51 */ +- <0x000d0000 0x001d0000 0x002000>, /* ap 52 */ +- <0x000d2000 0x001d2000 0x002000>, /* ap 53 */ +- <0x000d8000 0x001d8000 0x001000>, /* ap 54 */ +- <0x000d9000 0x001d9000 0x001000>, /* ap 55 */ +- <0x000a0000 0x001a0000 0x001000>, /* ap 67 */ +- <0x000a1000 0x001a1000 0x001000>, /* ap 68 */ +- <0x000a2000 0x001a2000 0x001000>, /* ap 69 */ +- <0x000a3000 0x001a3000 0x001000>, /* ap 70 */ +- <0x000a4000 0x001a4000 0x001000>, /* ap 92 */ +- <0x000a5000 0x001a5000 0x001000>, /* ap 93 */ +- <0x000c1000 0x001c1000 0x001000>, /* ap 94 */ +- <0x000c2000 0x001c2000 0x001000>; /* ap 95 */ +- +- target-module@8c000 { /* 0x4818c000, ap 34 0c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x8c000 0x1000>; +- }; +- +- target-module@8e000 { /* 0x4818e000, ap 36 02.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x8e000 0x1000>; +- }; +- +- target-module@9c000 { /* 0x4819c000, ap 38 52.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x9c000 0x8>, +- <0x9c010 0x8>, +- <0x9c090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_I2C3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x9c000 0x1000>; +- +- i2c2: i2c@0 { +- compatible = "ti,am4372-i2c","ti,omap4-i2c"; +- reg = <0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xa0000 0x4>, +- <0xa0110 0x4>, +- <0xa0114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_SPI1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa0000 0x1000>; +- +- spi1: spi@0 { +- compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; +- reg = <0x0 0x400>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xa2000 0x4>, +- <0xa2110 0x4>, +- <0xa2114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_SPI2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa2000 0x1000>; +- +- spi2: spi@0 { +- compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; +- reg = <0x0 0x400>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- target-module@a4000 { /* 0x481a4000, ap 92 62.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xa4000 0x4>, +- <0xa4110 0x4>, +- <0xa4114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_SPI3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa4000 0x1000>; +- +- spi3: spi@0 { +- compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; +- reg = <0x0 0x400>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- target-module@a6000 { /* 0x481a6000, ap 40 16.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xa6050 0x4>, +- <0xa6054 0x4>, +- <0xa6058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_UART4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa6000 0x1000>; +- +- uart3: serial@0 { +- compatible = "ti,am4372-uart"; +- reg = <0x0 0x2000>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- target-module@a8000 { /* 0x481a8000, ap 42 20.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xa8050 0x4>, +- <0xa8054 0x4>, +- <0xa8058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_UART5_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa8000 0x1000>; +- +- uart4: serial@0 { +- compatible = "ti,am4372-uart"; +- reg = <0x0 0x2000>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- target-module@aa000 { /* 0x481aa000, ap 44 12.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xaa050 0x4>, +- <0xaa054 0x4>, +- <0xaa058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_UART6_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xaa000 0x1000>; +- +- uart5: serial@0 { +- compatible = "ti,am4372-uart"; +- reg = <0x0 0x2000>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- target-module@ac000 { /* 0x481ac000, ap 46 30.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xac000 0x4>, +- <0xac010 0x4>, +- <0xac114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 0>, +- <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xac000 0x1000>; +- +- gpio2: gpio@0 { +- compatible = "ti,am4372-gpio","ti,omap4-gpio"; +- reg = <0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- }; +- +- target-module@ae000 { /* 0x481ae000, ap 48 32.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xae000 0x4>, +- <0xae010 0x4>, +- <0xae114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 0>, +- <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xae000 0x1000>; +- +- gpio3: gpio@0 { +- compatible = "ti,am4372-gpio","ti,omap4-gpio"; +- reg = <0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- }; +- +- target-module@c1000 { /* 0x481c1000, ap 94 68.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0xc1000 0x4>, +- <0xc1010 0x4>, +- <0xc1014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_TIMER8_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc1000 0x1000>; +- +- timer8: timer@0 { +- compatible = "ti,am4372-timer","ti,am335x-timer"; +- reg = <0x0 0x400>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- target-module@cc000 { /* 0x481cc000, ap 50 46.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xcc020 0x4>; +- reg-names = "rev"; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>, +- <&dcan0_fck>; +- clock-names = "fck", "osc"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xcc000 0x2000>; +- +- dcan0: can@0 { +- compatible = "ti,am4372-d_can", "ti,am3352-d_can"; +- reg = <0x0 0x2000>; +- clocks = <&dcan0_fck>; +- clock-names = "fck"; +- syscon-raminit = <&scm_conf 0x644 0>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xd0020 0x4>; +- reg-names = "rev"; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>, +- <&dcan1_fck>; +- clock-names = "fck", "osc"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xd0000 0x2000>; +- +- dcan1: can@0 { +- compatible = "ti,am4372-d_can", "ti,am3352-d_can"; +- reg = <0x0 0x2000>; +- clocks = <&dcan1_fck>; +- clock-names = "fck"; +- syscon-raminit = <&scm_conf 0x644 1>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- target-module@d8000 { /* 0x481d8000, ap 54 5e.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xd82fc 0x4>, +- <0xd8110 0x4>, +- <0xd8114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_MMC2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xd8000 0x1000>; +- +- mmc2: mmc@0 { +- compatible = "ti,am437-sdhci"; +- reg = <0x0 0x1000>; +- ti,needs-special-reset; +- dmas = <&edma 2 0>, +- <&edma 3 0>; +- dma-names = "tx", "rx"; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- }; +- +- segment@200000 { /* 0x48200000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00200000 0x010000>; +- +- target-module@0 { +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- power-domains = <&prm_mpu>; +- clocks = <&mpu_clkctrl AM4_MPU_MPU_CLKCTRL 0>; +- clock-names = "fck"; +- ti,no-idle; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x10000>; +- +- mpu@0 { +- compatible = "ti,omap4-mpu"; +- pm-sram = <&pm_sram_code +- &pm_sram_data>; +- }; +- }; +- }; +- +- segment@300000 { /* 0x48300000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00300000 0x001000>, /* ap 56 */ +- <0x00001000 0x00301000 0x001000>, /* ap 57 */ +- <0x00002000 0x00302000 0x001000>, /* ap 58 */ +- <0x00003000 0x00303000 0x001000>, /* ap 59 */ +- <0x00004000 0x00304000 0x001000>, /* ap 60 */ +- <0x00005000 0x00305000 0x001000>, /* ap 61 */ +- <0x00018000 0x00318000 0x004000>, /* ap 62 */ +- <0x0001c000 0x0031c000 0x001000>, /* ap 63 */ +- <0x00010000 0x00310000 0x002000>, /* ap 64 */ +- <0x00028000 0x00328000 0x001000>, /* ap 75 */ +- <0x00029000 0x00329000 0x001000>, /* ap 76 */ +- <0x00012000 0x00312000 0x001000>, /* ap 79 */ +- <0x00020000 0x00320000 0x001000>, /* ap 82 */ +- <0x00021000 0x00321000 0x001000>, /* ap 83 */ +- <0x00026000 0x00326000 0x001000>, /* ap 86 */ +- <0x00027000 0x00327000 0x001000>, /* ap 87 */ +- <0x0002a000 0x0032a000 0x000400>, /* ap 88 */ +- <0x0002c000 0x0032c000 0x001000>, /* ap 89 */ +- <0x00013000 0x00313000 0x001000>, /* ap 90 */ +- <0x00014000 0x00314000 0x001000>, /* ap 91 */ +- <0x00006000 0x00306000 0x001000>, /* ap 96 */ +- <0x00007000 0x00307000 0x001000>, /* ap 97 */ +- <0x00008000 0x00308000 0x001000>, /* ap 98 */ +- <0x00009000 0x00309000 0x001000>, /* ap 99 */ +- <0x0000a000 0x0030a000 0x001000>, /* ap 100 */ +- <0x0000b000 0x0030b000 0x001000>, /* ap 101 */ +- <0x0003d000 0x0033d000 0x001000>, /* ap 102 */ +- <0x0003e000 0x0033e000 0x001000>, /* ap 103 */ +- <0x0003f000 0x0033f000 0x001000>, /* ap 104 */ +- <0x00040000 0x00340000 0x001000>, /* ap 105 */ +- <0x00041000 0x00341000 0x001000>, /* ap 106 */ +- <0x00042000 0x00342000 0x001000>, /* ap 107 */ +- <0x00045000 0x00345000 0x001000>, /* ap 108 */ +- <0x00046000 0x00346000 0x001000>, /* ap 109 */ +- <0x00047000 0x00347000 0x001000>, /* ap 110 */ +- <0x00048000 0x00348000 0x001000>, /* ap 111 */ +- <0x000f2000 0x003f2000 0x002000>, /* ap 112 */ +- <0x000f4000 0x003f4000 0x001000>, /* ap 113 */ +- <0x0004c000 0x0034c000 0x002000>, /* ap 114 */ +- <0x0004e000 0x0034e000 0x001000>, /* ap 115 */ +- <0x00022000 0x00322000 0x001000>, /* ap 116 */ +- <0x00023000 0x00323000 0x001000>, /* ap 117 */ +- <0x000f0000 0x003f0000 0x001000>, /* ap 118 */ +- <0x0002a400 0x0032a400 0x000400>, /* ap 119 */ +- <0x0002a800 0x0032a800 0x000400>, /* ap 120 */ +- <0x0002ac00 0x0032ac00 0x000400>, /* ap 121 */ +- <0x0002b000 0x0032b000 0x001000>, /* ap 122 */ +- <0x00080000 0x00380000 0x020000>, /* ap 123 */ +- <0x000a0000 0x003a0000 0x001000>, /* ap 124 */ +- <0x000a8000 0x003a8000 0x008000>, /* ap 125 */ +- <0x000b0000 0x003b0000 0x001000>, /* ap 126 */ +- <0x000c0000 0x003c0000 0x020000>, /* ap 127 */ +- <0x000e0000 0x003e0000 0x001000>, /* ap 128 */ +- <0x000e8000 0x003e8000 0x008000>; /* ap 129 */ +- +- target-module@0 { /* 0x48300000, ap 56 40.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x0 0x4>, +- <0x4 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS0_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1000>; +- +- epwmss0: epwmss@0 { +- compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; +- reg = <0x0 0x10>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x1000>; +- status = "disabled"; +- +- ecap0: pwm@100 { +- compatible = "ti,am4372-ecap", +- "ti,am3352-ecap"; +- #pwm-cells = <3>; +- reg = <0x100 0x80>; +- clocks = <&l4ls_gclk>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- +- ehrpwm0: pwm@200 { +- compatible = "ti,am4372-ehrpwm", +- "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x200 0x80>; +- clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; +- clock-names = "tbclk", "fck"; +- status = "disabled"; +- }; +- }; +- }; +- +- target-module@2000 { /* 0x48302000, ap 58 4a.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x2000 0x4>, +- <0x2004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2000 0x1000>; +- +- epwmss1: epwmss@0 { +- compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; +- reg = <0x0 0x10>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x1000>; +- status = "disabled"; +- +- ecap1: pwm@100 { +- compatible = "ti,am4372-ecap", +- "ti,am3352-ecap"; +- #pwm-cells = <3>; +- reg = <0x100 0x80>; +- clocks = <&l4ls_gclk>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- +- ehrpwm1: pwm@200 { +- compatible = "ti,am4372-ehrpwm", +- "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x200 0x80>; +- clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; +- clock-names = "tbclk", "fck"; +- status = "disabled"; +- }; +- }; +- }; +- +- target-module@4000 { /* 0x48304000, ap 60 44.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x4000 0x4>, +- <0x4004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4000 0x1000>; +- +- epwmss2: epwmss@0 { +- compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; +- reg = <0x0 0x10>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x1000>; +- status = "disabled"; +- +- ecap2: pwm@100 { +- compatible = "ti,am4372-ecap", +- "ti,am3352-ecap"; +- #pwm-cells = <3>; +- reg = <0x100 0x80>; +- clocks = <&l4ls_gclk>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- +- ehrpwm2: pwm@200 { +- compatible = "ti,am4372-ehrpwm", +- "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x200 0x80>; +- clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; +- clock-names = "tbclk", "fck"; +- status = "disabled"; +- }; +- }; +- }; +- +- target-module@6000 { /* 0x48306000, ap 96 58.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x6000 0x4>, +- <0x6004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6000 0x1000>; +- +- epwmss3: epwmss@0 { +- compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; +- reg = <0x0 0x10>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x1000>; +- status = "disabled"; +- +- ehrpwm3: pwm@200 { +- compatible = "ti,am4372-ehrpwm", +- "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x200 0x80>; +- clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>; +- clock-names = "tbclk", "fck"; +- status = "disabled"; +- }; +- }; +- }; +- +- target-module@8000 { /* 0x48308000, ap 98 54.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x8000 0x4>, +- <0x8004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x8000 0x1000>; +- +- epwmss4: epwmss@0 { +- compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; +- reg = <0x0 0x10>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x1000>; +- status = "disabled"; +- +- ehrpwm4: pwm@48308200 { +- compatible = "ti,am4372-ehrpwm", +- "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x200 0x80>; +- clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>; +- clock-names = "tbclk", "fck"; +- status = "disabled"; +- }; +- }; +- }; +- +- target-module@a000 { /* 0x4830a000, ap 100 60.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xa000 0x4>, +- <0xa004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS5_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa000 0x1000>; +- +- epwmss5: epwmss@0 { +- compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; +- reg = <0x0 0x10>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x1000>; +- status = "disabled"; +- +- ehrpwm5: pwm@200 { +- compatible = "ti,am4372-ehrpwm", +- "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x200 0x80>; +- clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>; +- clock-names = "tbclk", "fck"; +- status = "disabled"; +- }; +- }; +- }; +- +- target-module@10000 { /* 0x48310000, ap 64 4e.1 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x11fe0 0x4>, +- <0x11fe4 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_RNG_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10000 0x2000>; +- +- rng: rng@0 { +- compatible = "ti,omap4-rng"; +- reg = <0x0 0x2000>; +- interrupts = ; +- }; +- }; +- +- target-module@13000 { /* 0x48313000, ap 90 50.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x13000 0x1000>; +- }; +- +- target-module@18000 { /* 0x48318000, ap 62 4c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x18000 0x4000>; +- }; +- +- target-module@20000 { /* 0x48320000, ap 82 34.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x20000 0x4>, +- <0x20010 0x4>, +- <0x20114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 0>, +- <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x20000 0x1000>; +- +- gpio4: gpio@0 { +- compatible = "ti,am4372-gpio","ti,omap4-gpio"; +- reg = <0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- }; +- +- gpio5_target: target-module@22000 { /* 0x48322000, ap 116 64.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x22000 0x4>, +- <0x22010 0x4>, +- <0x22114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 0>, +- <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x22000 0x1000>; +- +- gpio5: gpio@0 { +- compatible = "ti,am4372-gpio","ti,omap4-gpio"; +- reg = <0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- }; +- +- target-module@26000 { /* 0x48326000, ap 86 66.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x26000 0x4>, +- <0x26104 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): per_pwrdm, l3s_clkdm */ +- clocks = <&l3s_clkctrl AM4_L3S_VPFE0_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x26000 0x1000>; +- +- vpfe0: vpfe@0 { +- compatible = "ti,am437x-vpfe"; +- reg = <0x0 0x2000>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- target-module@28000 { /* 0x48328000, ap 75 0e.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x28000 0x4>, +- <0x28104 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): per_pwrdm, l3s_clkdm */ +- clocks = <&l3s_clkctrl AM4_L3S_VPFE1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x28000 0x1000>; +- +- vpfe1: vpfe@0 { +- compatible = "ti,am437x-vpfe"; +- reg = <0x0 0x2000>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x2a000 0x4>, +- <0x2a010 0x4>, +- <0x2a014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, dss_clkdm */ +- clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x0002a000 0x00000400>, +- <0x00000400 0x0002a400 0x00000400>, +- <0x00000800 0x0002a800 0x00000400>, +- <0x00000c00 0x0002ac00 0x00000400>, +- <0x00001000 0x0002b000 0x00001000>; +- +- dss: dss@0 { +- compatible = "ti,omap3-dss"; +- reg = <0 0x200>; +- status = "disabled"; +- clocks = <&disp_clk>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x00000400>, +- <0x00000400 0x00000400 0x00000400>, +- <0x00000800 0x00000800 0x00000400>, +- <0x00000c00 0x00000c00 0x00000400>, +- <0x00001000 0x00001000 0x00001000>; +- +- target-module@400 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x400 0x4>, +- <0x410 0x4>, +- <0x414 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,syss-mask = <1>; +- clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x400 0x400>; +- +- dispc: dispc@0 { +- compatible = "ti,omap3-dispc"; +- reg = <0 0x400>; +- interrupts = ; +- clocks = <&disp_clk>; +- clock-names = "fck"; +- +- max-memory-bandwidth = <230000000>; +- }; +- }; +- +- target-module@800 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x800 0x4>, +- <0x810 0x4>, +- <0x814 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,syss-mask = <1>; +- clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x800 0x400>; +- +- rfbi: rfbi@0 { +- compatible = "ti,omap3-rfbi"; +- reg = <0 0x100>; +- clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- }; +- }; +- }; +- +- target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x3d000 0x4>, +- <0x3d010 0x4>, +- <0x3d014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_TIMER9_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3d000 0x1000>; +- +- timer9: timer@0 { +- compatible = "ti,am4372-timer","ti,am335x-timer"; +- reg = <0x0 0x400>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x3f000 0x4>, +- <0x3f010 0x4>, +- <0x3f014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_TIMER10_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3f000 0x1000>; +- +- timer10: timer@0 { +- compatible = "ti,am4372-timer","ti,am335x-timer"; +- reg = <0x0 0x400>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- target-module@41000 { /* 0x48341000, ap 106 76.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x41000 0x4>, +- <0x41010 0x4>, +- <0x41014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_TIMER11_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x41000 0x1000>; +- +- timer11: timer@0 { +- compatible = "ti,am4372-timer","ti,am335x-timer"; +- reg = <0x0 0x400>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- target-module@45000 { /* 0x48345000, ap 108 6a.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x45000 0x4>, +- <0x45110 0x4>, +- <0x45114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_SPI4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x45000 0x1000>; +- +- spi4: spi@0 { +- compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; +- reg = <0x0 0x400>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- target-module@47000 { /* 0x48347000, ap 110 70.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x47000 0x4>, +- <0x47014 0x4>, +- <0x47018 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_HDQ1W_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x47000 0x1000>; +- +- hdq: hdq@0 { +- compatible = "ti,am4372-hdq"; +- reg = <0x0 0x1000>; +- interrupts = ; +- clocks = <&func_12m_clk>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- }; +- +- target-module@4c000 { /* 0x4834c000, ap 114 72.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4c000 0x2000>; +- }; +- +- target-module@80000 { /* 0x48380000, ap 123 42.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x80000 0x4>, +- <0x80010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l3s_clkdm */ +- clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x80000 0x20000>; +- +- dwc3_1: omap_dwc3@0 { +- compatible = "ti,am437x-dwc3"; +- reg = <0x0 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <1>; +- utmi-mode = <1>; +- ranges = <0 0 0x20000>; +- +- usb1: usb@10000 { +- compatible = "snps,dwc3"; +- reg = <0x10000 0x10000>; +- interrupts = , +- , +- ; +- interrupt-names = "peripheral", +- "host", +- "otg"; +- phys = <&usb2_phy1>; +- phy-names = "usb2-phy"; +- maximum-speed = "high-speed"; +- dr_mode = "otg"; +- status = "disabled"; +- snps,dis_u3_susphy_quirk; +- snps,dis_u2_susphy_quirk; +- }; +- }; +- }; +- +- target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xa8000 0x4>; +- reg-names = "rev"; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP0_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa8000 0x8000>; +- +- ocp2scp0: ocp2scp@0 { +- compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x8000>; +- +- usb2_phy1: phy@8000 { +- compatible = "ti,am437x-usb2"; +- reg = <0x0 0x8000>; +- syscon-phy-power = <&scm_conf 0x620>; +- clocks = <&usb_phy0_always_on_clk32k>, +- <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 8>; +- clock-names = "wkupclk", "refclk"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- }; +- +- target-module@c0000 { /* 0x483c0000, ap 127 7a.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xc0000 0x4>, +- <0xc0010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): per_pwrdm, l3s_clkdm */ +- clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc0000 0x20000>; +- +- dwc3_2: omap_dwc3@0 { +- compatible = "ti,am437x-dwc3"; +- reg = <0x0 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <1>; +- utmi-mode = <1>; +- ranges = <0 0 0x20000>; +- +- usb2: usb@10000 { +- compatible = "snps,dwc3"; +- reg = <0x10000 0x10000>; +- interrupts = , +- , +- ; +- interrupt-names = "peripheral", +- "host", +- "otg"; +- phys = <&usb2_phy2>; +- phy-names = "usb2-phy"; +- maximum-speed = "high-speed"; +- dr_mode = "otg"; +- status = "disabled"; +- snps,dis_u3_susphy_quirk; +- snps,dis_u2_susphy_quirk; +- }; +- }; +- }; +- +- target-module@e8000 { /* 0x483e8000, ap 129 78.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xe8000 0x4>; +- reg-names = "rev"; +- /* Domains (P, C): per_pwrdm, l4ls_clkdm */ +- clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xe8000 0x8000>; +- +- ocp2scp1: ocp2scp@0 { +- compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x8000>; +- +- usb2_phy2: phy@8000 { +- compatible = "ti,am437x-usb2"; +- reg = <0x0 0x8000>; +- syscon-phy-power = <&scm_conf 0x628>; +- clocks = <&usb_phy1_always_on_clk32k>, +- <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 8>; +- clock-names = "wkupclk", "refclk"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- }; +- +- target-module@f2000 { /* 0x483f2000, ap 112 5a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf2000 0x2000>; +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/am437x-sbc-t43.dts b/scripts/dtc/include-prefixes/arm/am437x-sbc-t43.dts +deleted file mode 100644 +index 8ea3780f939d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am437x-sbc-t43.dts ++++ /dev/null +@@ -1,177 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ +- */ +- +-#include "am437x-cm-t43.dts" +-#include "compulab-sb-som.dtsi" +- +-/ { +- model = "CompuLab CM-T43 on SB-SOM-T43"; +- compatible = "compulab,am437x-sbc-t43", "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"; +- +- aliases { +- display0 = &lcd0; +- }; +-}; +- +-&am43xx_pinmux { +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ +- AM4372_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ +- AM4372_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ +- AM4372_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ +- AM4372_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ +- AM4372_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ +- AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ +- AM4372_IOPAD(0x964, PIN_INPUT | MUX_MODE7) /* ecap0_in_pwm0_out.gpio0_7 */ +- >; +- }; +- +- dss_pinctrl_default: dss_pinctrl_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9b0, PIN_OUTPUT_PULLUP | MUX_MODE2) /* cam0 hd -> DSS DATA 23 */ +- AM4372_IOPAD(0x9b4, PIN_OUTPUT_PULLUP | MUX_MODE2) +- AM4372_IOPAD(0x9b8, PIN_OUTPUT_PULLUP | MUX_MODE2) +- AM4372_IOPAD(0x9bc, PIN_OUTPUT_PULLUP | MUX_MODE2) +- AM4372_IOPAD(0x9c0, PIN_OUTPUT_PULLUP | MUX_MODE2) +- AM4372_IOPAD(0x9c4, PIN_OUTPUT_PULLUP | MUX_MODE2) +- AM4372_IOPAD(0x9c8, PIN_OUTPUT_PULLUP | MUX_MODE2) +- AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLUP | MUX_MODE2) /* cam1 data 9 -> DSS DATA 16 */ +- +- AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ +- AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ +- AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ +- AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ +- AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ +- AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ +- AM4372_IOPAD(0xa20, PIN_OUTPUT_PULLUP | MUX_MODE7) +- >; +- }; +- +- uart0_pins_default: uart0_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) +- AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) +- AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ +- AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ +- >; +- }; +- +- i2c1_pins: i2c1_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0xa6c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1) /* spi2_cs0.i2c1_sda */ +- AM4372_IOPAD(0xa60, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1) /* spi2_sclk.i2c1_scl */ +- >; +- }; +- +- i2c2_pins: i2c2_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ +- AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ +- >; +- }; +- +- usb2_phy1_default: usb2_phy1_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE0) +- >; +- }; +- +- usb2_phy2_default: usb2_phy2_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE0) +- >; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- +- pca9555: pca9555@20 { +- compatible = "nxp,pca9555"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- eeprom_base: at24@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +-}; +- +-&mmc1 { +- status = "okay"; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <&vsb_3v3>; +- cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; +- wp-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; +-}; +- +-&dss { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_pinctrl_default>; +- +- port { +- dpi_lcd_out: endpoint { +- remote-endpoint = <&lcd_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins_default>; +-}; +- +-&dwc3_1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb2_phy1_default>; +-}; +- +-&dwc3_2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb2_phy2_default>; +-}; +- +-&lcd0 { +- enable-gpios = <&pca9555 14 GPIO_ACTIVE_HIGH +- &gpio4 28 GPIO_ACTIVE_HIGH>; +- +- port { +- lcd_in: endpoint { +- remote-endpoint = <&dpi_lcd_out>; +- data-lines = <24>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am437x-sk-evm.dts b/scripts/dtc/include-prefixes/arm/am437x-sk-evm.dts +deleted file mode 100644 +index 20a34d2d85df..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am437x-sk-evm.dts ++++ /dev/null +@@ -1,898 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/* AM437x SK EVM */ +- +-/dts-v1/; +- +-#include "am4372.dtsi" +-#include +-#include +-#include +-#include +-#include +- +-/ { +- model = "TI AM437x SK EVM"; +- compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43"; +- +- aliases { +- display0 = &lcd0; +- }; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- /* fixed 32k external oscillator clock */ +- clk_32k_rtc: clk_32k_rtc { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- lcd_bl: backlight { +- compatible = "pwm-backlight"; +- pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; +- brightness-levels = <0 51 53 56 62 75 101 152 255>; +- default-brightness-level = <8>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "AM437x-SK-EVM"; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack", +- "Line", "Line In"; +- simple-audio-card,routing = +- "Headphone Jack", "HPLOUT", +- "Headphone Jack", "HPROUT", +- "LINE1L", "Line In", +- "LINE1R", "Line In"; +- simple-audio-card,format = "dsp_b"; +- simple-audio-card,bitclock-master = <&sound_master>; +- simple-audio-card,frame-master = <&sound_master>; +- simple-audio-card,bitclock-inversion; +- +- simple-audio-card,cpu { +- sound-dai = <&mcasp1>; +- }; +- +- sound_master: simple-audio-card,codec { +- sound-dai = <&tlv320aic3106>; +- system-clock-frequency = <24000000>; +- }; +- }; +- +- matrix_keypad: matrix_keypad0 { +- compatible = "gpio-matrix-keypad"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&matrix_keypad_pins>; +- +- debounce-delay-ms = <5>; +- col-scan-delay-us = <5>; +- +- row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */ +- &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */ +- +- col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */ +- &gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */ +- +- linux,keymap = < +- MATRIX_KEY(0, 0, KEY_DOWN) +- MATRIX_KEY(0, 1, KEY_RIGHT) +- MATRIX_KEY(1, 0, KEY_LEFT) +- MATRIX_KEY(1, 1, KEY_UP) +- >; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&leds_pins>; +- +- led0 { +- label = "am437x-sk:red:heartbeat"; +- gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */ +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- +- led1 { +- label = "am437x-sk:green:mmc1"; +- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */ +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- +- led2 { +- label = "am437x-sk:blue:cpu0"; +- gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */ +- linux,default-trigger = "cpu0"; +- default-state = "off"; +- }; +- +- led3 { +- label = "am437x-sk:blue:usr3"; +- gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */ +- default-state = "off"; +- }; +- }; +- +- lcd0: display { +- compatible = "newhaven,nhd-4.3-480272ef-atxl", "panel-dpi"; +- label = "lcd"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_pins>; +- +- backlight = <&lcd_bl>; +- +- enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- +- port { +- lcd_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- }; +- +- vmmcwl_fixed: fixedregulator-mmcwl { +- /* +- * WL_EN is not SDIO standard compliant. It is an out of band +- * signal and hard to be dealt with in a standard way by the +- * SDIO core driver. +- * So modelling the WL_EN line as a regulator was a natural +- * choice as the MMC core already deals with MMC supplies. +- */ +- compatible = "regulator-fixed"; +- regulator-name = "vmmcwl_fixed"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&am43xx_pinmux { +- matrix_keypad_pins: matrix_keypad_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0xa4c, PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */ +- AM4372_IOPAD(0xa50, PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */ +- AM4372_IOPAD(0xa54, PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */ +- AM4372_IOPAD(0xa58, PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */ +- >; +- }; +- +- leds_pins: leds_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0xa28, PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */ +- AM4372_IOPAD(0xa2c, PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */ +- AM4372_IOPAD(0xa30, PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */ +- AM4372_IOPAD(0xa34, PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */ +- >; +- }; +- +- i2c0_pins: i2c0_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ +- AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ +- >; +- }; +- +- i2c1_pins: i2c1_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x95c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ +- AM4372_IOPAD(0x958, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ +- AM4372_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ +- AM4372_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ +- AM4372_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ +- AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ +- AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ +- AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ +- >; +- }; +- +- ecap0_pins: backlight_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ +- >; +- }; +- +- edt_ft5306_ts_pins: edt_ft5306_ts_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x874, PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ +- AM4372_IOPAD(0x878, PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ +- >; +- }; +- +- vpfe0_pins_default: vpfe0_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ +- AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ +- AM4372_IOPAD(0x9b8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/ +- AM4372_IOPAD(0x9bc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/ +- AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ +- AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ +- AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ +- AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ +- AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ +- AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ +- AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ +- AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ +- AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ +- AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ +- AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ +- >; +- }; +- +- vpfe0_pins_sleep: vpfe0_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0x9b8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0x9bc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- >; +- }; +- +- clkout1_pin: pinmux_clkout1_pin { +- pinctrl-single,pins = < +- 0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */ +- >; +- }; +- +- cpsw_default: cpsw_default { +- pinctrl-single,pins = < +- /* Slave 1 */ +- AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ +- AM4372_IOPAD(0x914, PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ +- AM4372_IOPAD(0x928, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ +- AM4372_IOPAD(0x924, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ +- AM4372_IOPAD(0x920, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ +- AM4372_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ +- AM4372_IOPAD(0x930, PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ +- AM4372_IOPAD(0x918, PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ +- AM4372_IOPAD(0x940, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ +- AM4372_IOPAD(0x93c, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ +- AM4372_IOPAD(0x938, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ +- AM4372_IOPAD(0x934, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ +- +- /* Slave 2 */ +- AM4372_IOPAD(0x858, PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ +- AM4372_IOPAD(0x840, PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ +- AM4372_IOPAD(0x854, PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ +- AM4372_IOPAD(0x850, PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ +- AM4372_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ +- AM4372_IOPAD(0x848, PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ +- AM4372_IOPAD(0x85c, PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ +- AM4372_IOPAD(0x844, PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ +- AM4372_IOPAD(0x86c, PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ +- AM4372_IOPAD(0x868, PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ +- AM4372_IOPAD(0x864, PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ +- AM4372_IOPAD(0x860, PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ +- >; +- }; +- +- cpsw_sleep: cpsw_sleep { +- pinctrl-single,pins = < +- /* Slave 1 reset value */ +- AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) +- +- /* Slave 2 reset value */ +- AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- davinci_mdio_default: davinci_mdio_default { +- pinctrl-single,pins = < +- /* MDIO */ +- AM4372_IOPAD(0x948, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ +- AM4372_IOPAD(0x94c, PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */ +- >; +- }; +- +- davinci_mdio_sleep: davinci_mdio_sleep { +- pinctrl-single,pins = < +- /* MDIO reset value */ +- AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- dss_pins: dss_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */ +- AM4372_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) +- AM4372_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) +- AM4372_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) +- AM4372_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) +- AM4372_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) +- AM4372_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) +- AM4372_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */ +- AM4372_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */ +- AM4372_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) +- AM4372_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) +- AM4372_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) +- AM4372_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) +- AM4372_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) +- AM4372_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) +- AM4372_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) +- AM4372_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) +- AM4372_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) +- AM4372_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) +- AM4372_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) +- AM4372_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) +- AM4372_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) +- AM4372_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) +- AM4372_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */ +- AM4372_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */ +- AM4372_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */ +- AM4372_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */ +- AM4372_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */ +- +- >; +- }; +- +- qspi_pins: qspi_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */ +- AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ +- AM4372_IOPAD(0x890, PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ +- AM4372_IOPAD(0x894, PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ +- AM4372_IOPAD(0x898, PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */ +- AM4372_IOPAD(0x89c, PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ +- >; +- }; +- +- mcasp1_pins: mcasp1_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ +- AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ +- AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ +- AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ +- >; +- }; +- +- mcasp1_pins_sleep: mcasp1_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- lcd_pins: lcd_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */ +- >; +- }; +- +- usb1_pins: usb1_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0xac0, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ +- >; +- }; +- +- usb2_pins: usb2_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0xac4, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ +- >; +- }; +- +- mmc3_pins_default: pinmux_mmc3_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD21) cam1_data2.mmc2_clk */ +- AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE22) cam1_data3.mmc2_cmd */ +- AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD22) cam1_data4.mmc2_dat0 */ +- AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE23) cam1_data5.mmc2_dat1 */ +- AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD23) cam1_data6.mmc2_dat2 */ +- AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE24) cam1_data7.mmc2_dat3 */ +- >; +- }; +- +- mmc3_pins_sleep: pinmux_mmc3_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD21) cam1_data2.mmc2_clk */ +- AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE22) cam1_data3.mmc2_cmd */ +- AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD22) cam1_data4.mmc2_dat0 */ +- AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE23) cam1_data5.mmc2_dat1 */ +- AM4372_IOPAD(0xa00, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD23) cam1_data6.mmc2_dat2 */ +- AM4372_IOPAD(0xa04, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE24) cam1_data7.mmc2_dat3 */ +- >; +- }; +- +- wlan_pins_default: pinmux_wlan_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9d0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */ +- AM4372_IOPAD(0x9e4, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */ +- >; +- }; +- +- wlan_pins_sleep: pinmux_wlan_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9d0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */ +- AM4372_IOPAD(0x9e4, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */ +- >; +- }; +- +- uart1_bt_pins_default: pinmux_uart1_bt_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd.uart1_rxd */ +- AM4372_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ +- AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ +- AM4372_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ +- AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data9.gpio4_7 BT_EN */ +- >; +- }; +- +- uart1_bt_pins_sleep: pinmux_uart1_bt_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x980, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.uart1_rxd */ +- AM4372_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.uart1_txd */ +- AM4372_IOPAD(0x978, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */ +- AM4372_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */ +- AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_data9.gpio4_7 BT_EN */ +- >; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- clock-frequency = <100000>; +- +- tps@24 { +- compatible = "ti,tps65218"; +- reg = <0x24>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- dcdc1: regulator-dcdc1 { +- /* VDD_CORE limits min of OPP50 and max of OPP100 */ +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <912000>; +- regulator-max-microvolt = <1144000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc2: regulator-dcdc2 { +- /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <912000>; +- regulator-max-microvolt = <1378000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc3: regulator-dcdc3 { +- regulator-name = "vdds_ddr"; +- regulator-boot-on; +- regulator-always-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- regulator-state-disk { +- regulator-off-in-suspend; +- }; +- }; +- +- dcdc4: regulator-dcdc4 { +- regulator-name = "v3_3d"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc5: regulator-dcdc5 { +- compatible = "ti,tps65218-dcdc5"; +- regulator-name = "v1_0bat"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- dcdc6: regulator-dcdc6 { +- compatible = "ti,tps65218-dcdc6"; +- regulator-name = "v1_8bat"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo1: regulator-ldo1 { +- regulator-name = "v1_8d"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- power-button { +- compatible = "ti,tps65218-pwrbutton"; +- status = "okay"; +- interrupts = <3 IRQ_TYPE_EDGE_BOTH>; +- }; +- }; +- +- at24@50 { +- compatible = "atmel,24c256"; +- pagesize = <64>; +- reg = <0x50>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- clock-frequency = <400000>; +- +- ov2659@30 { +- compatible = "ovti,ov2659"; +- reg = <0x30>; +- pinctrl-names = "default"; +- pinctrl-0 = <&clkout1_pin>; +- +- clocks = <&clkout1_mux_ck>; +- clock-names = "xvclk"; +- assigned-clocks = <&clkout1_mux_ck>; +- assigned-clock-parents = <&clkout1_osc_div_ck>; +- +- port { +- ov2659_1: endpoint { +- remote-endpoint = <&vpfe0_ep>; +- link-frequencies = /bits/ 64 <70000000>; +- }; +- }; +- }; +- +- edt-ft5306@38 { +- status = "okay"; +- compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; +- pinctrl-names = "default"; +- pinctrl-0 = <&edt_ft5306_ts_pins>; +- +- reg = <0x38>; +- interrupt-parent = <&gpio0>; +- interrupts = <31 IRQ_TYPE_EDGE_FALLING>; +- +- reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; +- +- touchscreen-size-x = <480>; +- touchscreen-size-y = <272>; +- +- wakeup-source; +- }; +- +- tlv320aic3106: tlv320aic3106@1b { +- #sound-dai-cells = <0>; +- compatible = "ti,tlv320aic3106"; +- reg = <0x1b>; +- status = "okay"; +- +- /* Regulators */ +- AVDD-supply = <&dcdc4>; +- IOVDD-supply = <&dcdc4>; +- DRVDD-supply = <&dcdc4>; +- DVDD-supply = <&ldo1>; +- }; +- +- lis331dlh@18 { +- compatible = "st,lis331dlh"; +- reg = <0x18>; +- status = "okay"; +- +- Vdd-supply = <&dcdc4>; +- Vdd_IO-supply = <&dcdc4>; +- interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>; +- }; +-}; +- +-&epwmss0 { +- status = "okay"; +-}; +- +-&ecap0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ecap0_pins>; +-}; +- +-&gpio0 { +- status = "okay"; +-}; +- +-&gpio1 { +- status = "okay"; +-}; +- +-&gpio4 { +- status = "okay"; +-}; +- +-&gpio5 { +- status = "okay"; +-}; +- +-&mmc1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- +- vmmc-supply = <&dcdc4>; +- bus-width = <4>; +- cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +-}; +- +-&uart1 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&uart1_bt_pins_default>; +- pinctrl-1 = <&uart1_bt_pins_sleep>; +-}; +- +-&mmc3 { +- status = "okay"; +- /* +- * these are on the crossbar and are outlined in the +- * xbar-event-map element +- */ +- dmas = <&edma_xbar 30 0 1>, +- <&edma_xbar 31 0 2>; +- dma-names = "tx", "rx"; +- vmmc-supply = <&vmmcwl_fixed>; +- bus-width = <4>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mmc3_pins_default>; +- pinctrl-1 = <&mmc3_pins_sleep>; +- cap-power-off-card; +- keep-power-in-suspend; +- non-removable; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1835"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&wlan_pins_default>; +- pinctrl-1 = <&wlan_pins_sleep>; +- reg = <2>; +- interrupt-parent = <&gpio4>; +- interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; +- }; +-}; +- +-&usb2_phy1 { +- status = "okay"; +-}; +- +-&usb1 { +- dr_mode = "otg"; +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb1_pins>; +-}; +- +-&usb2_phy2 { +- status = "okay"; +-}; +- +-&usb2 { +- dr_mode = "host"; +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb2_pins>; +-}; +- +-&qspi { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&qspi_pins>; +- +- spi-max-frequency = <48000000>; +- m25p80@0 { +- compatible = "mx66l51235l"; +- spi-max-frequency = <48000000>; +- reg = <0>; +- spi-cpol; +- spi-cpha; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* MTD partition table. +- * The ROM checks the first 512KiB +- * for a valid file to boot(XIP). +- */ +- partition@0 { +- label = "QSPI.U_BOOT"; +- reg = <0x00000000 0x000080000>; +- }; +- partition@1 { +- label = "QSPI.U_BOOT.backup"; +- reg = <0x00080000 0x00080000>; +- }; +- partition@2 { +- label = "QSPI.U-BOOT-SPL_OS"; +- reg = <0x00100000 0x00010000>; +- }; +- partition@3 { +- label = "QSPI.U_BOOT_ENV"; +- reg = <0x00110000 0x00010000>; +- }; +- partition@4 { +- label = "QSPI.U-BOOT-ENV.backup"; +- reg = <0x00120000 0x00010000>; +- }; +- partition@5 { +- label = "QSPI.KERNEL"; +- reg = <0x00130000 0x0800000>; +- }; +- partition@6 { +- label = "QSPI.FILESYSTEM"; +- reg = <0x00930000 0x36D0000>; +- }; +- }; +-}; +- +-&mac_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&cpsw_default>; +- pinctrl-1 = <&cpsw_sleep>; +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&davinci_mdio_default>; +- pinctrl-1 = <&davinci_mdio_sleep>; +- +- ethphy0: ethernet-phy@4 { +- reg = <4>; +- }; +- +- ethphy1: ethernet-phy@5 { +- reg = <5>; +- }; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "rgmii-rxid"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- phy-handle = <ðphy1>; +- phy-mode = "rgmii-rxid"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&elm { +- status = "okay"; +-}; +- +-&mcasp1 { +- #sound-dai-cells = <0>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mcasp1_pins>; +- pinctrl-1 = <&mcasp1_pins_sleep>; +- +- status = "okay"; +- +- op-mode = <0>; +- tdm-slots = <2>; +- serial-dir = < +- 0 0 1 2 +- >; +- +- tx-num-evt = <1>; +- rx-num-evt = <1>; +-}; +- +-&dss { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_pins>; +- +- port { +- dpi_out: endpoint@0 { +- remote-endpoint = <&lcd_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-&rtc { +- clocks = <&clk_32k_rtc>, <&clk_32768_ck>; +- clock-names = "ext-clk", "int-clk"; +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +- +-&cpu { +- cpu0-supply = <&dcdc2>; +-}; +- +-&vpfe0 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&vpfe0_pins_default>; +- pinctrl-1 = <&vpfe0_pins_sleep>; +- +- /* Camera port */ +- port { +- vpfe0_ep: endpoint { +- remote-endpoint = <&ov2659_1>; +- ti,am437x-vpfe-interface = <0>; +- bus-width = <8>; +- hsync-active = <0>; +- vsync-active = <0>; +- }; +- }; +-}; +- +-&pruss1_mdio { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am43x-epos-evm.dts b/scripts/dtc/include-prefixes/arm/am43x-epos-evm.dts +deleted file mode 100644 +index 2f4d2e4e9b3e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am43x-epos-evm.dts ++++ /dev/null +@@ -1,1024 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/* AM43x EPOS EVM */ +- +-/dts-v1/; +- +-#include "am4372.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "TI AM43x EPOS EVM"; +- compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43"; +- +- aliases { +- display0 = &lcd0; +- }; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- vmmcsd_fixed: fixedregulator-sd { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsd_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- }; +- +- vbat: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vbat"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- }; +- +- lcd0: display { +- compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; +- label = "lcd"; +- +- backlight = <&lcd_bl>; +- +- port { +- lcd_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- }; +- +- matrix_keypad: matrix_keypad0 { +- compatible = "gpio-matrix-keypad"; +- debounce-delay-ms = <5>; +- col-scan-delay-us = <2>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&matrix_keypad_default>; +- pinctrl-1 = <&matrix_keypad_sleep>; +- wakeup-source; +- +- row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ +- &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ +- &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ +- &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ +- +- col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ +- &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ +- &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ +- &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ +- +- linux,keymap = <0x00000201 /* P1 */ +- 0x01000204 /* P4 */ +- 0x02000207 /* P7 */ +- 0x0300020a /* NUMERIC_STAR */ +- 0x00010202 /* P2 */ +- 0x01010205 /* P5 */ +- 0x02010208 /* P8 */ +- 0x03010200 /* P0 */ +- 0x00020203 /* P3 */ +- 0x01020206 /* P6 */ +- 0x02020209 /* P9 */ +- 0x0302020b /* NUMERIC_POUND */ +- 0x00030067 /* UP */ +- 0x0103006a /* RIGHT */ +- 0x0203006c /* DOWN */ +- 0x03030069>; /* LEFT */ +- }; +- +- lcd_bl: backlight { +- compatible = "pwm-backlight"; +- pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; +- brightness-levels = <0 51 53 56 62 75 101 152 255>; +- default-brightness-level = <8>; +- }; +- +- sound0: sound0 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "AM43-EPOS-EVM"; +- simple-audio-card,widgets = +- "Microphone", "Microphone Jack", +- "Headphone", "Headphone Jack", +- "Speaker", "Speaker"; +- simple-audio-card,routing = +- "MIC1LP", "Microphone Jack", +- "MIC1RP", "Microphone Jack", +- "MIC1LP", "MICBIAS", +- "MIC1RP", "MICBIAS", +- "Headphone Jack", "HPL", +- "Headphone Jack", "HPR", +- "Speaker", "SPL", +- "Speaker", "SPR"; +- simple-audio-card,format = "dsp_b"; +- simple-audio-card,bitclock-master = <&sound0_master>; +- simple-audio-card,frame-master = <&sound0_master>; +- simple-audio-card,bitclock-inversion; +- +- simple-audio-card,cpu { +- sound-dai = <&mcasp1>; +- system-clock-frequency = <12000000>; +- }; +- +- sound0_master: simple-audio-card,codec { +- sound-dai = <&tlv320aic3111>; +- system-clock-frequency = <12000000>; +- }; +- }; +- +- audio_mstrclk: clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <12000000>; +- }; +-}; +- +-&am43xx_pinmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&unused_pins>; +- +- unused_pins: unused_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x848, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x850, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x858, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x860, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x864, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x868, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x86c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x878, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x908, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x91c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x920, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x9e0, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xA0c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xA38, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xA3c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xA40, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xA44, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xA48, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xA4c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xA50, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xA54, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xA58, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xA5c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xA60, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xA64, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0xA68, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xA6C, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xA74, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0xA78, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- cpsw_default: cpsw_default { +- pinctrl-single,pins = < +- /* Slave 1 */ +- AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ +- AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ +- AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ +- AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */ +- AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ +- AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ +- AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ +- AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ +- AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ +- >; +- }; +- +- cpsw_sleep: cpsw_sleep { +- pinctrl-single,pins = < +- /* Slave 1 reset value */ +- AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- davinci_mdio_default: davinci_mdio_default { +- pinctrl-single,pins = < +- /* MDIO */ +- AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ +- AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ +- >; +- }; +- +- davinci_mdio_sleep: davinci_mdio_sleep { +- pinctrl-single,pins = < +- /* MDIO reset value */ +- AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- i2c0_pins: pinmux_i2c0_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ +- AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ +- >; +- }; +- +- nand_flash_x8_default: nand_flash_x8_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ +- AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ +- AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ +- AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ +- AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ +- AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ +- AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ +- AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ +- AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ +- AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ +- AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ +- AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ +- AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ +- AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ +- AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ +- AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ +- >; +- }; +- +- nand_flash_x8_sleep: nand_flash_x8_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x840, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x800, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x804, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x808, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x80c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x810, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x814, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x818, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x81c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x870, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x874, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) +- >; +- }; +- +- ecap0_pins_default: backlight_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ +- >; +- }; +- +- ecap0_pins_sleep: backlight_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x964, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) +- >; +- }; +- +- i2c2_pins: pinmux_i2c2_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ +- AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ +- >; +- }; +- +- spi0_pins_default: pinmux_spi0_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ +- AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ +- AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ +- AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ +- >; +- }; +- +- spi0_pins_sleep: pinmux_spi0_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x950, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x954, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x958, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x95c, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) +- >; +- }; +- +- spi1_pins_default: pinmux_spi1_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ +- AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ +- AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ +- AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ +- >; +- }; +- +- spi1_pins_sleep: pinmux_spi1_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x990, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x994, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x998, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x99c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- mmc1_pins_default: pinmux_mmc1_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ +- >; +- }; +- +- mmc1_pins_sleep: pinmux_mmc1_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x960, DS0_PIN_OUTPUT_PULLUP | PIN_INPUT | MUX_MODE7) +- >; +- }; +- +- matrix_keypad_default: matrix_keypad_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* mii1_tx_clk.gpio3_9 */ +- AM4372_IOPAD(0x930, PIN_OUTPUT | MUX_MODE7) /* mii1_rx_clk.gpio3_10 */ +- AM4372_IOPAD(0x934, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd3.gpio2_18 */ +- AM4372_IOPAD(0x938, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd2.gpio2_19 */ +- AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ +- AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ +- AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.gpio0_14 */ +- AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.gpio0_15 */ +- >; +- }; +- +- matrix_keypad_sleep: matrix_keypad_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- qspi1_pins_default: qspi1_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3) +- AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2) +- AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) +- AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) +- AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) +- AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) +- >; +- }; +- +- qspi1_pins_sleep: qspi1_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x888, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) +- AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) +- >; +- }; +- +- pixcir_ts_pins_default: pixcir_ts_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ +- >; +- }; +- +- pixcir_ts_pins_sleep: pixcir_ts_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x844, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ +- >; +- }; +- +- hdq_pins: pinmux_hdq_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ +- >; +- }; +- +- dss_pins: dss_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ +- AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) +- AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) +- AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) +- AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) +- AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) +- AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) +- AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ +- AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ +- AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) +- AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ +- AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ +- AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ +- AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ +- AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ +- >; +- }; +- +- display_mux_pins: display_mux_pins { +- pinctrl-single,pins = < +- /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ +- AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7) +- >; +- }; +- +- vpfe1_pins_default: vpfe1_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */ +- AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */ +- AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */ +- AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */ +- AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */ +- AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */ +- AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */ +- AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */ +- AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */ +- AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */ +- AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */ +- AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */ +- AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */ +- >; +- }; +- +- vpfe1_pins_sleep: vpfe1_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- >; +- }; +- +- uart0_pins_default: uart0_pins_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ +- AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ +- AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ +- AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ +- >; +- }; +- +- uart0_pins_sleep: uart0_pins_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) +- AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) +- AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) +- >; +- }; +- +- usb2_phy1_default: usb2_phy1_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0xac0, PIN_INPUT_PULLDOWN | MUX_MODE0) +- >; +- }; +- +- usb2_phy1_sleep: usb2_phy1_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- usb2_phy2_default: usb2_phy2_default { +- pinctrl-single,pins = < +- AM4372_IOPAD(0xac4, PIN_INPUT_PULLDOWN | MUX_MODE0) +- >; +- }; +- +- usb2_phy2_sleep: usb2_phy2_sleep { +- pinctrl-single,pins = < +- AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +- +- mcasp1_pins: mcasp1_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */ +- AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */ +- AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */ +- AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */ +- >; +- }; +- +- mcasp1_sleep_pins: mcasp1_sleep_pins { +- pinctrl-single,pins = < +- AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7) +- AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7) +- >; +- }; +-}; +- +-&mmc1 { +- status = "okay"; +- vmmc-supply = <&vmmcsd_fixed>; +- bus-width = <4>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mmc1_pins_default>; +- pinctrl-1 = <&mmc1_pins_sleep>; +- cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +-}; +- +-&mac_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&cpsw_default>; +- pinctrl-1 = <&cpsw_sleep>; +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&davinci_mdio_default>; +- pinctrl-1 = <&davinci_mdio_sleep>; +- +- ethphy0: ethernet-phy@16 { +- reg = <16>; +- }; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "rmii"; +- phys = <&phy_gmii_sel 1 1>; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- status = "disabled"; +-}; +- +-&i2c0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- clock-frequency = <100000>; +- +- tps65218: tps65218@24 { +- reg = <0x24>; +- compatible = "ti,tps65218"; +- interrupts = ; /* NMIn */ +- interrupt-controller; +- #interrupt-cells = <2>; +- +- dcdc1: regulator-dcdc1 { +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <912000>; +- regulator-max-microvolt = <1144000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc2: regulator-dcdc2 { +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <912000>; +- regulator-max-microvolt = <1378000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc3: regulator-dcdc3 { +- regulator-name = "vdcdc3"; +- regulator-boot-on; +- regulator-always-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- regulator-state-disk { +- regulator-off-in-suspend; +- }; +- }; +- +- dcdc4: regulator-dcdc4 { +- regulator-name = "vdcdc4"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc5: regulator-dcdc5 { +- regulator-name = "v1_0bat"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- dcdc6: regulator-dcdc6 { +- regulator-name = "v1_8bat"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1: regulator-ldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- +- at24@50 { +- compatible = "atmel,24c256"; +- pagesize = <64>; +- reg = <0x50>; +- }; +- +- pixcir_ts@5c { +- compatible = "pixcir,pixcir_tangoc"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&pixcir_ts_pins_default>; +- pinctrl-1 = <&pixcir_ts_pins_sleep>; +- +- reg = <0x5c>; +- interrupt-parent = <&gpio1>; +- interrupts = <17 IRQ_TYPE_EDGE_FALLING>; +- +- attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; +- +- touchscreen-size-x = <1024>; +- touchscreen-size-y = <600>; +- }; +- +- tlv320aic3111: tlv320aic3111@18 { +- #sound-dai-cells = <0>; +- compatible = "ti,tlv320aic3111"; +- reg = <0x18>; +- status = "okay"; +- +- ai31xx-micbias-vg = ; +- +- /* Regulators */ +- HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ +- SPRVDD-supply = <&vbat>; /* vbat */ +- SPLVDD-supply = <&vbat>; /* vbat */ +- AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ +- IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */ +- DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */ +- }; +- +- ov2659@30 { +- compatible = "ovti,ov2659"; +- reg = <0x30>; +- +- clocks = <&audio_mstrclk>; +- clock-names = "xvclk"; +- +- port { +- ov2659_1: endpoint { +- remote-endpoint = <&vpfe1_ep>; +- link-frequencies = /bits/ 64 <70000000>; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "okay"; +-}; +- +-&gpio0 { +- status = "okay"; +-}; +- +-&gpio1 { +- status = "okay"; +-}; +- +-&gpio2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&display_mux_pins>; +- status = "okay"; +- +- sel-lcd-hdmi-hog { +- /* +- * SelLCDorHDMI selects between display and audio paths: +- * Low: HDMI display with audio via HDMI +- * High: LCD display with analog audio via aic3111 codec +- */ +- gpio-hog; +- gpios = <1 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "SelLCDorHDMI"; +- }; +-}; +- +-&gpio3 { +- status = "okay"; +-}; +- +-&elm { +- status = "okay"; +-}; +- +-&gpmc { +- status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&nand_flash_x8_default>; +- pinctrl-1 = <&nand_flash_x8_sleep>; +- ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ +- ti,nand-xfer-type = "prefetch-dma"; +- ti,nand-ecc-opt = "bch16"; +- ti,elm-id = <&elm>; +- nand-bus-width = <8>; +- gpmc,device-width = <1>; +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */ +- gpmc,cs-wr-off-ns = <40>; +- gpmc,adv-on-ns = <0>; /* cs-on-ns */ +- gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */ +- gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */ +- gpmc,we-on-ns = <0>; /* cs-on-ns */ +- gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */ +- gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */ +- gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */ +- gpmc,access-ns = <30>; /* tCEA + 4*/ +- gpmc,rd-cycle-ns = <40>; +- gpmc,wr-cycle-ns = <40>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- /* MTD partition table */ +- /* All SPL-* partitions are sized to minimal length +- * which can be independently programmable. For +- * NAND flash this is equal to size of erase-block */ +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "NAND.SPL"; +- reg = <0x00000000 0x00040000>; +- }; +- partition@1 { +- label = "NAND.SPL.backup1"; +- reg = <0x00040000 0x00040000>; +- }; +- partition@2 { +- label = "NAND.SPL.backup2"; +- reg = <0x00080000 0x00040000>; +- }; +- partition@3 { +- label = "NAND.SPL.backup3"; +- reg = <0x000C0000 0x00040000>; +- }; +- partition@4 { +- label = "NAND.u-boot-spl-os"; +- reg = <0x00100000 0x00080000>; +- }; +- partition@5 { +- label = "NAND.u-boot"; +- reg = <0x00180000 0x00100000>; +- }; +- partition@6 { +- label = "NAND.u-boot-env"; +- reg = <0x00280000 0x00040000>; +- }; +- partition@7 { +- label = "NAND.u-boot-env.backup1"; +- reg = <0x002C0000 0x00040000>; +- }; +- partition@8 { +- label = "NAND.kernel"; +- reg = <0x00300000 0x00700000>; +- }; +- partition@9 { +- label = "NAND.file-system"; +- reg = <0x00a00000 0x1f600000>; +- }; +- }; +-}; +- +-&epwmss0 { +- status = "okay"; +-}; +- +-&rtc_target { +- status = "disabled"; +-}; +- +-&tscadc { +- status = "okay"; +- +- adc { +- ti,adc-channels = <0 1 2 3 4 5 6 7>; +- }; +-}; +- +-&ecap0 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&ecap0_pins_default>; +- pinctrl-1 = <&ecap0_pins_sleep>; +-}; +- +-&spi0 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&spi0_pins_default>; +- pinctrl-1 = <&spi0_pins_sleep>; +- ti,pindir-d0-out-d1-in; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&spi1_pins_default>; +- pinctrl-1 = <&spi1_pins_sleep>; +- ti,pindir-d0-out-d1-in; +-}; +- +-&usb2_phy1 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&usb2_phy1_default>; +- pinctrl-1 = <&usb2_phy1_sleep>; +-}; +- +-&usb1 { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb2_phy2 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&usb2_phy2_default>; +- pinctrl-1 = <&usb2_phy2_sleep>; +-}; +- +-&usb2 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&qspi { +- status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */ +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&qspi1_pins_default>; +- pinctrl-1 = <&qspi1_pins_sleep>; +- +- spi-max-frequency = <48000000>; +- m25p80@0 { +- compatible = "mx66l51235l"; +- spi-max-frequency = <48000000>; +- reg = <0>; +- spi-cpol; +- spi-cpha; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* MTD partition table. +- * The ROM checks the first 512KiB +- * for a valid file to boot(XIP). +- */ +- partition@0 { +- label = "QSPI.U_BOOT"; +- reg = <0x00000000 0x000080000>; +- }; +- partition@1 { +- label = "QSPI.U_BOOT.backup"; +- reg = <0x00080000 0x00080000>; +- }; +- partition@2 { +- label = "QSPI.U-BOOT-SPL_OS"; +- reg = <0x00100000 0x00010000>; +- }; +- partition@3 { +- label = "QSPI.U_BOOT_ENV"; +- reg = <0x00110000 0x00010000>; +- }; +- partition@4 { +- label = "QSPI.U-BOOT-ENV.backup"; +- reg = <0x00120000 0x00010000>; +- }; +- partition@5 { +- label = "QSPI.KERNEL"; +- reg = <0x00130000 0x0800000>; +- }; +- partition@6 { +- label = "QSPI.FILESYSTEM"; +- reg = <0x00930000 0x36D0000>; +- }; +- }; +-}; +- +-&hdq { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdq_pins>; +-}; +- +-&dss { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_pins>; +- +- port { +- dpi_out: endpoint { +- remote-endpoint = <&lcd_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-&vpfe1 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&vpfe1_pins_default>; +- pinctrl-1 = <&vpfe1_pins_sleep>; +- +- port { +- vpfe1_ep: endpoint { +- remote-endpoint = <&ov2659_1>; +- ti,am437x-vpfe-interface = <0>; +- bus-width = <8>; +- hsync-active = <0>; +- vsync-active = <0>; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&uart0_pins_default>; +- pinctrl-1 = <&uart0_pins_sleep>; +-}; +- +-&mcasp1 { +- #sound-dai-cells = <0>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mcasp1_pins>; +- pinctrl-1 = <&mcasp1_sleep_pins>; +- +- status = "okay"; +- +- op-mode = <0>; /* MCASP_IIS_MODE */ +- tdm-slots = <2>; +- /* 4 serializer */ +- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ +- 1 2 0 0 +- >; +- tx-num-evt = <32>; +- rx-num-evt = <32>; +-}; +- +-&mux_synctimer32k_ck { +- assigned-clocks = <&mux_synctimer32k_ck>; +- assigned-clock-parents = <&clkdiv32k_ick>; +-}; +- +-&cpu { +- cpu0-supply = <&dcdc2>; +-}; +- +-&pruss1_mdio { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am43xx-clocks.dtsi b/scripts/dtc/include-prefixes/arm/am43xx-clocks.dtsi +deleted file mode 100644 +index 314fc5975acb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am43xx-clocks.dtsi ++++ /dev/null +@@ -1,883 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for AM43xx clock data +- * +- * Copyright (C) 2013 Texas Instruments, Inc. +- */ +-&scm_clocks { +- sys_clkin_ck: sys_clkin_ck@40 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; +- ti,bit-shift = <31>; +- reg = <0x0040>; +- }; +- +- crystal_freq_sel_ck: crystal_freq_sel_ck@40 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; +- ti,bit-shift = <29>; +- reg = <0x0040>; +- }; +- +- sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; +- ti,bit-shift = <22>; +- reg = <0x0040>; +- }; +- +- adc_tsc_fck: adc_tsc_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dcan0_fck: dcan0_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dcan1_fck: dcan1_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- mcasp0_fck: mcasp0_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- mcasp1_fck: mcasp1_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- smartreflex0_fck: smartreflex0_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- smartreflex1_fck: smartreflex1_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- sha0_fck: sha0_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- aes0_fck: aes0_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- rng_fck: rng_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- ehrpwm0_tbclk: ehrpwm0_tbclk@664 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&l4ls_gclk>; +- ti,bit-shift = <0>; +- reg = <0x0664>; +- }; +- +- ehrpwm1_tbclk: ehrpwm1_tbclk@664 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&l4ls_gclk>; +- ti,bit-shift = <1>; +- reg = <0x0664>; +- }; +- +- ehrpwm2_tbclk: ehrpwm2_tbclk@664 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&l4ls_gclk>; +- ti,bit-shift = <2>; +- reg = <0x0664>; +- }; +- +- ehrpwm3_tbclk: ehrpwm3_tbclk@664 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&l4ls_gclk>; +- ti,bit-shift = <4>; +- reg = <0x0664>; +- }; +- +- ehrpwm4_tbclk: ehrpwm4_tbclk@664 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&l4ls_gclk>; +- ti,bit-shift = <5>; +- reg = <0x0664>; +- }; +- +- ehrpwm5_tbclk: ehrpwm5_tbclk@664 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&l4ls_gclk>; +- ti,bit-shift = <6>; +- reg = <0x0664>; +- }; +-}; +-&prcm_clocks { +- clk_32768_ck: clk_32768_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- clk_rc32k_ck: clk_rc32k_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- virt_19200000_ck: virt_19200000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <19200000>; +- }; +- +- virt_24000000_ck: virt_24000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- virt_25000000_ck: virt_25000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25000000>; +- }; +- +- virt_26000000_ck: virt_26000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- }; +- +- tclkin_ck: tclkin_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- }; +- +- dpll_core_ck: dpll_core_ck@2d20 { +- #clock-cells = <0>; +- compatible = "ti,am3-dpll-core-clock"; +- clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; +- reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>; +- }; +- +- dpll_core_x2_ck: dpll_core_x2_ck { +- #clock-cells = <0>; +- compatible = "ti,am3-dpll-x2-clock"; +- clocks = <&dpll_core_ck>; +- }; +- +- dpll_core_m4_ck: dpll_core_m4_ck@2d38 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x2d38>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_core_m5_ck: dpll_core_m5_ck@2d3c { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x2d3c>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_core_m6_ck: dpll_core_m6_ck@2d40 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x2d40>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_mpu_ck: dpll_mpu_ck@2d60 { +- #clock-cells = <0>; +- compatible = "ti,am3-dpll-clock"; +- clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; +- reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>; +- }; +- +- dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_mpu_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x2d70>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- mpu_periphclk: mpu_periphclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_mpu_m2_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- dpll_ddr_ck: dpll_ddr_ck@2da0 { +- #clock-cells = <0>; +- compatible = "ti,am3-dpll-clock"; +- clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; +- reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>; +- }; +- +- dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_ddr_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x2db0>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_disp_ck: dpll_disp_ck@2e20 { +- #clock-cells = <0>; +- compatible = "ti,am3-dpll-clock"; +- clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; +- reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>; +- }; +- +- dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_disp_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x2e30>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- ti,set-rate-parent; +- }; +- +- dpll_per_ck: dpll_per_ck@2de0 { +- #clock-cells = <0>; +- compatible = "ti,am3-dpll-j-type-clock"; +- clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; +- reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>; +- }; +- +- dpll_per_m2_ck: dpll_per_m2_ck@2df0 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_ck>; +- ti,max-div = <127>; +- ti,autoidle-shift = <8>; +- reg = <0x2df0>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2_ck>; +- clock-mult = <1>; +- clock-div = <4>; +- }; +- +- dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2_ck>; +- clock-mult = <1>; +- clock-div = <4>; +- }; +- +- clk_24mhz: clk_24mhz { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2_ck>; +- clock-mult = <1>; +- clock-div = <8>; +- }; +- +- clkdiv32k_ck: clkdiv32k_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&clk_24mhz>; +- clock-mult = <1>; +- clock-div = <732>; +- }; +- +- clkdiv32k_ick: clkdiv32k_ick@2a38 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&clkdiv32k_ck>; +- ti,bit-shift = <8>; +- reg = <0x2a38>; +- }; +- +- sysclk_div: sysclk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_m4_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- pruss_ocp_gclk: pruss_ocp_gclk@4248 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; +- reg = <0x4248>; +- }; +- +- clk_32k_tpm_ck: clk_32k_tpm_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- timer1_fck: timer1_fck@4200 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; +- reg = <0x4200>; +- }; +- +- timer2_fck: timer2_fck@4204 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; +- reg = <0x4204>; +- }; +- +- timer3_fck: timer3_fck@4208 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; +- reg = <0x4208>; +- }; +- +- timer4_fck: timer4_fck@420c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; +- reg = <0x420c>; +- }; +- +- timer5_fck: timer5_fck@4210 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; +- reg = <0x4210>; +- }; +- +- timer6_fck: timer6_fck@4214 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; +- reg = <0x4214>; +- }; +- +- timer7_fck: timer7_fck@4218 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; +- reg = <0x4218>; +- }; +- +- wdt1_fck: wdt1_fck@422c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; +- reg = <0x422c>; +- }; +- +- l3_gclk: l3_gclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_m4_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sysclk_div>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- l4hs_gclk: l4hs_gclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_m4_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- l3s_gclk: l3s_gclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_m4_div2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- l4ls_gclk: l4ls_gclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_m4_div2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- cpsw_125mhz_gclk: cpsw_125mhz_gclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_m5_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; +- reg = <0x4238>; +- }; +- +- dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_m5_ck>; +- reg = <0x4234>; +- ti,bit-shift = <2>; +- ti,dividers = <2>, <5>; +- }; +- +- clk_32k_mosc_ck: clk_32k_mosc_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; +- reg = <0x4240>; +- }; +- +- mmc_clk: mmc_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sysclk_div>, <&dpll_per_m2_ck>; +- ti,bit-shift = <1>; +- reg = <0x423c>; +- }; +- +- gfx_fck_div_ck: gfx_fck_div_ck@423c { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&gfx_fclk_clksel_ck>; +- reg = <0x423c>; +- ti,max-div = <2>; +- }; +- +- disp_clk: disp_clk@4244 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; +- reg = <0x4244>; +- ti,set-rate-parent; +- }; +- +- dpll_extdev_ck: dpll_extdev_ck@2e60 { +- #clock-cells = <0>; +- compatible = "ti,am3-dpll-clock"; +- clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; +- reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>; +- }; +- +- dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_extdev_ck>; +- ti,max-div = <127>; +- ti,autoidle-shift = <8>; +- reg = <0x2e70>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- mux_synctimer32k_ck: mux_synctimer32k_ck@4230 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; +- reg = <0x4230>; +- }; +- +- timer8_fck: timer8_fck@421c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; +- reg = <0x421c>; +- }; +- +- timer9_fck: timer9_fck@4220 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; +- reg = <0x4220>; +- }; +- +- timer10_fck: timer10_fck@4224 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; +- reg = <0x4224>; +- }; +- +- timer11_fck: timer11_fck@4228 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; +- reg = <0x4228>; +- }; +- +- cpsw_50m_clkdiv: cpsw_50m_clkdiv { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_m5_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- cpsw_5m_clkdiv: cpsw_5m_clkdiv { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&cpsw_50m_clkdiv>; +- clock-mult = <1>; +- clock-div = <10>; +- }; +- +- dpll_ddr_x2_ck: dpll_ddr_x2_ck { +- #clock-cells = <0>; +- compatible = "ti,am3-dpll-x2-clock"; +- clocks = <&dpll_ddr_ck>; +- }; +- +- dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_ddr_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x2db8>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 { +- #clock-cells = <0>; +- compatible = "ti,fixed-factor-clock"; +- clocks = <&dpll_per_ck>; +- ti,clock-mult = <1>; +- ti,clock-div = <1>; +- ti,autoidle-shift = <8>; +- reg = <0x2e14>; +- ti,invert-autoidle-bit; +- }; +- +- dll_aging_clk_div: dll_aging_clk_div@4250 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&sys_clkin_ck>; +- reg = <0x4250>; +- ti,dividers = <8>, <16>, <32>; +- }; +- +- div_core_25m_ck: div_core_25m_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sysclk_div>; +- clock-mult = <1>; +- clock-div = <8>; +- }; +- +- func_12m_clk: func_12m_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2_ck>; +- clock-mult = <1>; +- clock-div = <16>; +- }; +- +- vtp_clk_div: vtp_clk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; +- reg = <0x4260>; +- }; +- +- usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&usbphy_32khz_clkmux>; +- ti,bit-shift = <8>; +- reg = <0x2a40>; +- }; +- +- usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&usbphy_32khz_clkmux>; +- ti,bit-shift = <8>; +- reg = <0x2a48>; +- }; +- +- clkout1_osc_div_ck: clkout1-osc-div-ck { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&sys_clkin_ck>; +- ti,bit-shift = <20>; +- ti,max-div = <4>; +- reg = <0x4100>; +- }; +- +- clkout1_src2_mux_ck: clkout1-src2-mux-ck { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, +- <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, +- <&dpll_mpu_m2_ck>; +- reg = <0x4100>; +- }; +- +- clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&clkout1_src2_mux_ck>; +- ti,bit-shift = <4>; +- ti,max-div = <8>; +- reg = <0x4100>; +- }; +- +- clkout1_src2_post_div_ck: clkout1-src2-post-div-ck { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&clkout1_src2_pre_div_ck>; +- ti,bit-shift = <8>; +- ti,max-div = <32>; +- ti,index-power-of-two; +- reg = <0x4100>; +- }; +- +- clkout1_mux_ck: clkout1-mux-ck { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>, +- <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>; +- ti,bit-shift = <16>; +- reg = <0x4100>; +- }; +- +- clkout1_ck: clkout1-ck { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&clkout1_mux_ck>; +- ti,bit-shift = <23>; +- reg = <0x4100>; +- }; +-}; +- +-&prcm { +- wkup_cm: wkup-cm@2800 { +- compatible = "ti,omap4-cm"; +- reg = <0x2800 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x2800 0x400>; +- +- l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 { +- compatible = "ti,clkctrl"; +- reg = <0x120 0x4>; +- #clock-cells = <2>; +- }; +- +- l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 { +- compatible = "ti,clkctrl"; +- reg = <0x228 0xc>; +- #clock-cells = <2>; +- }; +- +- l4_wkup_clkctrl: l4-wkup-clkctrl@220 { +- compatible = "ti,clkctrl"; +- reg = <0x220 0x4>, <0x328 0x44>; +- #clock-cells = <2>; +- }; +- +- }; +- +- mpu_cm: mpu-cm@8300 { +- compatible = "ti,omap4-cm"; +- reg = <0x8300 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x8300 0x100>; +- +- mpu_clkctrl: mpu-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- gfx_l3_cm: gfx-l3-cm@8400 { +- compatible = "ti,omap4-cm"; +- reg = <0x8400 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x8400 0x100>; +- +- gfx_l3_clkctrl: gfx-l3-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- l4_rtc_cm: l4-rtc-cm@8500 { +- compatible = "ti,omap4-cm"; +- reg = <0x8500 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x8500 0x100>; +- +- l4_rtc_clkctrl: l4-rtc-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- per_cm: per-cm@8800 { +- compatible = "ti,omap4-cm"; +- reg = <0x8800 0xc00>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x8800 0xc00>; +- +- l3_clkctrl: l3-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x3c>, <0x78 0x2c>; +- #clock-cells = <2>; +- }; +- +- l3s_clkctrl: l3s-clkctrl@68 { +- compatible = "ti,clkctrl"; +- reg = <0x68 0xc>, <0x220 0x4c>; +- #clock-cells = <2>; +- }; +- +- pruss_ocp_clkctrl: pruss-ocp-clkctrl@320 { +- compatible = "ti,clkctrl"; +- reg = <0x320 0x4>; +- #clock-cells = <2>; +- }; +- +- l4ls_clkctrl: l4ls-clkctrl@420 { +- compatible = "ti,clkctrl"; +- reg = <0x420 0x1a4>; +- #clock-cells = <2>; +- }; +- +- emif_clkctrl: emif-clkctrl@720 { +- compatible = "ti,clkctrl"; +- reg = <0x720 0x4>; +- #clock-cells = <2>; +- }; +- +- dss_clkctrl: dss-clkctrl@a20 { +- compatible = "ti,clkctrl"; +- reg = <0xa20 0x4>; +- #clock-cells = <2>; +- }; +- +- cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@b20 { +- compatible = "ti,clkctrl"; +- reg = <0xb20 0x4>; +- #clock-cells = <2>; +- }; +- +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am57-pruss.dtsi b/scripts/dtc/include-prefixes/arm/am57-pruss.dtsi +deleted file mode 100644 +index 46c5383f0eee..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am57-pruss.dtsi ++++ /dev/null +@@ -1,226 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * Common PRUSS data for TI AM57xx platforms +- */ +- +-&ocp { +- pruss1_tm: target-module@4b226000 { +- compatible = "ti,sysc-pruss", "ti,sysc"; +- reg = <0x4b226000 0x4>, +- <0x4b226004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | +- SYSC_PRUSS_SUB_MWAIT)>; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */ +- clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x4b200000 0x80000>; +- +- pruss1: pruss@0 { +- compatible = "ti,am5728-pruss"; +- reg = <0x0 0x80000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- pruss1_mem: memories@0 { +- reg = <0x0 0x2000>, +- <0x2000 0x2000>, +- <0x10000 0x8000>; +- reg-names = "dram0", "dram1", +- "shrdram2"; +- }; +- +- pruss1_cfg: cfg@26000 { +- compatible = "ti,pruss-cfg", "syscon"; +- reg = <0x26000 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x26000 0x2000>; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- pruss1_iepclk_mux: iepclk-mux@30 { +- reg = <0x30>; +- #clock-cells = <0>; +- clocks = <&dpll_gmac_m3x2_ck>, /* icss_iep_clk */ +- <&dpll_gmac_h13x2_ck>; /* icss_clk */ +- }; +- }; +- }; +- +- pruss1_mii_rt: mii-rt@32000 { +- compatible = "ti,pruss-mii", "syscon"; +- reg = <0x32000 0x58>; +- }; +- +- pruss1_intc: interrupt-controller@20000 { +- compatible = "ti,pruss-intc"; +- reg = <0x20000 0x2000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "host_intr0", "host_intr1", +- "host_intr2", "host_intr3", +- "host_intr4", "host_intr5", +- "host_intr6", "host_intr7"; +- }; +- +- pru1_0: pru@34000 { +- compatible = "ti,am5728-pru"; +- reg = <0x34000 0x3000>, +- <0x22000 0x400>, +- <0x22400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am57xx-pru1_0-fw"; +- }; +- +- pru1_1: pru@38000 { +- compatible = "ti,am5728-pru"; +- reg = <0x38000 0x3000>, +- <0x24000 0x400>, +- <0x24400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am57xx-pru1_1-fw"; +- }; +- +- pruss1_mdio: mdio@32400 { +- compatible = "ti,davinci_mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&dpll_gmac_h13x2_ck>; +- clock-names = "fck"; +- bus_freq = <1000000>; +- reg = <0x32400 0x90>; +- }; +- }; +- }; +- +- pruss2_tm: target-module@4b2a6000 { +- compatible = "ti,sysc-pruss", "ti,sysc"; +- reg = <0x4b2a6000 0x4>, +- <0x4b2a6004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | +- SYSC_PRUSS_SUB_MWAIT)>; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */ +- clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x4b280000 0x80000>; +- +- pruss2: pruss@0 { +- compatible = "ti,am5728-pruss"; +- reg = <0x0 0x80000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- pruss2_mem: memories@0 { +- reg = <0x0 0x2000>, +- <0x2000 0x2000>, +- <0x10000 0x8000>; +- reg-names = "dram0", "dram1", +- "shrdram2"; +- }; +- +- pruss2_cfg: cfg@26000 { +- compatible = "ti,pruss-cfg", "syscon"; +- reg = <0x26000 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x26000 0x2000>; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- pruss2_iepclk_mux: iepclk-mux@30 { +- reg = <0x30>; +- #clock-cells = <0>; +- clocks = <&dpll_gmac_m3x2_ck>, /* icss_iep_clk */ +- <&dpll_gmac_h13x2_ck>; /* icss_clk */ +- }; +- }; +- }; +- +- pruss2_mii_rt: mii-rt@32000 { +- compatible = "ti,pruss-mii", "syscon"; +- reg = <0x32000 0x58>; +- }; +- +- pruss2_intc: interrupt-controller@20000 { +- compatible = "ti,pruss-intc"; +- reg = <0x20000 0x2000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "host_intr0", "host_intr1", +- "host_intr2", "host_intr3", +- "host_intr4", "host_intr5", +- "host_intr6", "host_intr7"; +- }; +- +- pru2_0: pru@34000 { +- compatible = "ti,am5728-pru"; +- reg = <0x34000 0x3000>, +- <0x22000 0x400>, +- <0x22400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am57xx-pru2_0-fw"; +- }; +- +- pru2_1: pru@38000 { +- compatible = "ti,am5728-pru"; +- reg = <0x38000 0x3000>, +- <0x24000 0x400>, +- <0x24400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am57xx-pru2_1-fw"; +- }; +- +- pruss2_mdio: mdio@32400 { +- compatible = "ti,davinci_mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&dpll_gmac_h13x2_ck>; +- clock-names = "fck"; +- bus_freq = <1000000>; +- reg = <0x32400 0x90>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am5718.dtsi b/scripts/dtc/include-prefixes/arm/am5718.dtsi +deleted file mode 100644 +index 6d7530a48c73..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am5718.dtsi ++++ /dev/null +@@ -1,29 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include "dra72x.dtsi" +-#include "am57-pruss.dtsi" +- +-/ { +- compatible = "ti,am5718", "ti,dra7"; +-}; +- +-/* +- * These modules are not present on AM5718 +- * +- * ATL +- * VCP1, VCP2 +- * MLB +- * ISS +- * USB3 +- */ +- +-&usb3_tm { +- status = "disabled"; +-}; +- +-&atl_tm { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am571x-idk.dts b/scripts/dtc/include-prefixes/arm/am571x-idk.dts +deleted file mode 100644 +index 48425020281a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am571x-idk.dts ++++ /dev/null +@@ -1,218 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "am5718.dtsi" +-#include +-#include +-#include "dra7-mmc-iodelay.dtsi" +-#include "dra72x-mmc-iodelay.dtsi" +-#include "am57xx-idk-common.dtsi" +-#include "dra7-ipu-dsp-common.dtsi" +- +-/ { +- model = "TI AM5718 IDK"; +- compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0x40000000>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ipu2_memory_region: ipu2-memory@95800000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x95800000 0x0 0x3800000>; +- reusable; +- status = "okay"; +- }; +- +- dsp1_memory_region: dsp1-memory@99000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x99000000 0x0 0x4000000>; +- reusable; +- status = "okay"; +- }; +- +- ipu1_memory_region: ipu1-memory@9d000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x9d000000 0x0 0x2000000>; +- reusable; +- status = "okay"; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- cpu0-led { +- label = "status0:red:cpu0"; +- gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "cpu0"; +- }; +- +- usr0-led { +- label = "status0:green:usr"; +- gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- heartbeat-led { +- label = "status0:blue:heartbeat"; +- gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "heartbeat"; +- }; +- +- usr1-led { +- label = "status1:red:usr"; +- gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- usr2-led { +- label = "status1:green:usr"; +- gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- mmc0-led { +- label = "status1:blue:mmc0"; +- gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "mmc0"; +- }; +- }; +- +- idk-leds { +- status = "disabled"; +- compatible = "gpio-leds"; +- red0-led { +- label = "idk:red0"; +- gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- green0-led { +- label = "idk:green0"; +- gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- blue0-led { +- label = "idk:blue0"; +- gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- red1-led { +- label = "idk:red1"; +- gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- green1-led { +- label = "idk:green1"; +- gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- blue1-led { +- label = "idk:blue1"; +- gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- red2-led { +- label = "idk:red2"; +- gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- green2-led { +- label = "idk:green2"; +- gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- blue2-led { +- label = "idk:blue2"; +- gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- red3-led { +- label = "idk:red3"; +- gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- green3-led { +- label = "idk:green3"; +- gpios = <&gpio7 25 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- blue3-led { +- label = "idk:blue3"; +- gpios = <&gpio7 24 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +-}; +- +-&extcon_usb2 { +- id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; +- vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>; +-}; +- +-&sn65hvs882 { +- load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; +-}; +- +-&ipu2 { +- status = "okay"; +- memory-region = <&ipu2_memory_region>; +-}; +- +-&ipu1 { +- status = "okay"; +- memory-region = <&ipu1_memory_region>; +-}; +- +-&dsp1 { +- status = "okay"; +- memory-region = <&dsp1_memory_region>; +-}; +- +-&pcie1_rc { +- status = "okay"; +- gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; +-}; +- +-&mmc1 { +- pinctrl-names = "default", "hs"; +- pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; +- pinctrl-1 = <&mmc1_pins_hs>; +-}; +- +-&mmc2 { +- pinctrl-names = "default", "hs", "ddr_3_3v"; +- pinctrl-0 = <&mmc2_pins_default>; +- pinctrl-1 = <&mmc2_pins_hs>; +- pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; +-}; +- +-&pruss1_mdio { +- status = "disabled"; +-}; +- +-&pruss2_mdio { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am5728.dtsi b/scripts/dtc/include-prefixes/arm/am5728.dtsi +deleted file mode 100644 +index 5e0bdf16d485..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am5728.dtsi ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include "dra74x.dtsi" +-#include "am57-pruss.dtsi" +- +-/ { +- compatible = "ti,am5728", "ti,dra7"; +-}; +- +-/* +- * These modules are not present on AM5728 +- * +- * EVE1, EVE2 +- * ATL +- * VCP1, VCP2 +- * MLB +- * ISS +- * USB3, USB4 +- */ +- +-&usb3_tm { +- status = "disabled"; +-}; +- +-&usb4_tm { +- status = "disabled"; +-}; +- +-&atl_tm { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am5729-beagleboneai.dts b/scripts/dtc/include-prefixes/arm/am5729-beagleboneai.dts +deleted file mode 100644 +index 149cfafb90bf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am5729-beagleboneai.dts ++++ /dev/null +@@ -1,704 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2014-2019 Texas Instruments Incorporated - http://www.ti.com/ +- */ +- +-/dts-v1/; +- +-#include "dra74x.dtsi" +-#include "am57xx-commercial-grade.dtsi" +-#include "dra74x-mmc-iodelay.dtsi" +-#include "dra74-ipu-dsp-common.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "BeagleBoard.org BeagleBone AI"; +- compatible = "beagle,am5729-beagleboneai", "ti,am5728", +- "ti,dra742", "ti,dra74", "ti,dra7"; +- +- aliases { +- rtc0 = &tps659038_rtc; +- rtc1 = &rtc; +- display0 = &hdmi_conn; +- }; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0x40000000>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ipu2_memory_region: ipu2-memory@95800000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x95800000 0x0 0x3800000>; +- reusable; +- status = "okay"; +- }; +- +- dsp1_memory_region: dsp1-memory@99000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x99000000 0x0 0x4000000>; +- reusable; +- status = "okay"; +- }; +- +- ipu1_memory_region: ipu1-memory@9d000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x9d000000 0x0 0x2000000>; +- reusable; +- status = "okay"; +- }; +- +- dsp2_memory_region: dsp2-memory@9f000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x9f000000 0x0 0x800000>; +- reusable; +- status = "okay"; +- }; +- +- }; +- +- vdd_adc: gpioregulator-vdd_adc { +- compatible = "regulator-gpio"; +- regulator-name = "vdd_adc"; +- vin-supply = <&vdd_5v>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; +- states = <1800000 0 +- 3300000 1>; +- }; +- +- vdd_5v: fixedregulator-vdd_5v { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vtt_fixed: fixedregulator-vtt { +- /* TPS51200 */ +- compatible = "regulator-fixed"; +- regulator-name = "vtt_fixed"; +- vin-supply = <&vdd_ddr>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led0 { +- label = "beaglebone:green:usr0"; +- gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- +- led1 { +- label = "beaglebone:green:usr1"; +- gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- +- led2 { +- label = "beaglebone:green:usr2"; +- gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "cpu"; +- default-state = "off"; +- }; +- +- led3 { +- label = "beaglebone:green:usr3"; +- gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc1"; +- default-state = "off"; +- }; +- +- led4 { +- label = "beaglebone:green:usr4"; +- gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "netdev"; +- default-state = "off"; +- }; +- }; +- +- hdmi_conn: connector@0 { +- compatible = "hdmi-connector"; +- label = "hdmi"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_encoder_out>; +- }; +- }; +- }; +- +- hdmi_enc: encoder@0 { +- /* "ti,tpd12s016" software compatible with "ti,tpd12s015" +- * no need for individual driver +- */ +- compatible = "ti,tpd12s015"; +- gpios = <0>, +- <0>, +- <&gpio7 12 GPIO_ACTIVE_HIGH>; +- +- ports { +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- +- port@0 { +- reg = <0x0>; +- +- hdmi_encoder_in: endpoint@0 { +- remote-endpoint = <&hdmi_out>; +- }; +- }; +- +- port@1 { +- reg = <0x1>; +- +- hdmi_encoder_out: endpoint@0 { +- remote-endpoint = <&hdmi_connector_in>; +- }; +- }; +- }; +- }; +- +- emmc_pwrseq: emmc_pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; +- }; +- +- brcmf_pwrseq: brcmf_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>, /* BT-REG-ON */ +- <&gpio3 18 GPIO_ACTIVE_LOW>; /* WL-REG-ON */ +- }; +- +- extcon_usb1: extcon_usb1 { +- compatible = "linux,extcon-usb-gpio"; +- ti,enable-id-detection; +- id-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- tps659038: tps659038@58 { +- compatible = "ti,tps659038"; +- reg = <0x58>; +- interrupt-parent = <&gpio6>; +- interrupts = <16 IRQ_TYPE_LEVEL_LOW>; +- +- #interrupt-cells = <2>; +- interrupt-controller; +- +- ti,system-power-controller; +- ti,palmas-override-powerhold; +- +- tps659038_pmic { +- compatible = "ti,tps659038-pmic"; +- +- smps12-in-supply = <&vdd_5v>; +- smps3-in-supply = <&vdd_5v>; +- smps45-in-supply = <&vdd_5v>; +- smps6-in-supply = <&vdd_5v>; +- smps7-in-supply = <&vdd_5v>; +- mps3-in-supply = <&vdd_5v>; +- smps8-in-supply = <&vdd_5v>; +- smps9-in-supply = <&vdd_5v>; +- ldo1-in-supply = <&vdd_5v>; +- ldo2-in-supply = <&vdd_5v>; +- ldo3-in-supply = <&vdd_5v>; +- ldo4-in-supply = <&vdd_5v>; +- ldo9-in-supply = <&vdd_5v>; +- ldoln-in-supply = <&vdd_5v>; +- ldousb-in-supply = <&vdd_5v>; +- ldortc-in-supply = <&vdd_5v>; +- +- regulators { +- vdd_mpu: smps12 { +- /* VDD_MPU */ +- regulator-name = "smps12"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_ddr: smps3 { +- /* VDD_DDR EMIF1 EMIF2 */ +- regulator-name = "smps3"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_dspeve: smps45 { +- /* VDD_DSPEVE on AM572 */ +- regulator-name = "smps45"; +- regulator-min-microvolt = < 850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_gpu: smps6 { +- /* VDD_GPU */ +- regulator-name = "smps6"; +- regulator-min-microvolt = < 850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_core: smps7 { +- /* VDD_CORE */ +- regulator-name = "smps7"; +- regulator-min-microvolt = < 850000>; /*** 1.15V */ +- regulator-max-microvolt = <1150000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_iva: smps8 { +- /* VDD_IVAHD */ /*** 1.06V */ +- regulator-name = "smps8"; +- }; +- +- vdd_3v3: smps9 { +- /* VDD_3V3 */ +- regulator-name = "smps9"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_sd: ldo1 { +- /* VDDSHV8 - VSDMMC */ +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd_1v8: ldo2 { +- /* VDDSH18V */ +- regulator-name = "ldo2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v8_phy_ldo3: ldo3 { +- /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */ +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v8_phy_ldo4: ldo4 { +- /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/ +- regulator-name = "ldo4"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* LDO5-8 unused */ +- +- vdd_rtc: ldo9 { +- /* VDD_RTC */ +- regulator-name = "ldo9"; +- regulator-min-microvolt = < 840000>; +- regulator-max-microvolt = <1160000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v8_pll: ldoln { +- /* VDDA_1V8_PLL */ +- regulator-name = "ldoln"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldousb_reg: ldousb { +- /* VDDA_3V_USB: VDDA_USBHS33 */ +- regulator-name = "ldousb"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldortc_reg: ldortc { +- /* VDDA_RTC */ +- regulator-name = "ldortc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- regen1: regen1 { +- /* VDD_3V3_ON */ +- regulator-name = "regen1"; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- regen2: regen2 { +- /* Needed for PMIC internal resource */ +- regulator-name = "regen2"; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +- +- tps659038_rtc: tps659038_rtc { +- compatible = "ti,palmas-rtc"; +- interrupt-parent = <&tps659038>; +- interrupts = <8 IRQ_TYPE_EDGE_FALLING>; +- wakeup-source; +- }; +- +- tps659038_pwr_button: tps659038_pwr_button { +- compatible = "ti,palmas-pwrbutton"; +- interrupt-parent = <&tps659038>; +- interrupts = <1 IRQ_TYPE_EDGE_FALLING>; +- wakeup-source; +- ti,palmas-long-press-seconds = <12>; +- }; +- +- tps659038_gpio: tps659038_gpio { +- compatible = "ti,palmas-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +- +- /* STMPE811 touch screen controller */ +- stmpe811@41 { +- compatible = "st,stmpe811"; +- reg = <0x41>; +- interrupts = <30 IRQ_TYPE_LEVEL_LOW>; +- interrupt-parent = <&gpio2>; +- interrupt-controller; +- id = <0>; +- blocks = <0x5>; +- irq-trigger = <0x1>; +- st,mod-12b = <1>; /* 12-bit ADC */ +- st,ref-sel = <0>; /* internal ADC reference */ +- st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */ +- st,sample-time = <4>; /* ADC converstion time: 80 clocks */ +- +- stmpe_adc { +- compatible = "st,stmpe-adc"; +- st,norequest-mask = <0x00>; /* mask any channels to be used by touchscreen */ +- adc0: iio-device@0 { +- #io-channel-cells = <1>; +- iio-channels = <&adc0 4>, <&adc0 1>, <&adc0 2>, <&adc0 3>, <&adc0 4>, <&adc0 5>, <&adc0 6>; +- iio-channel-names = "AIN0_P9_39", "AIN1_P9_40", "AIN2_P9_37", "AIN3_P9_38", +- "AIN4_P9_33", "AIN5_P9_36", "AIN6_P9_35"; +- }; +- }; +- +- stmpe_touchscreen { +- status = "disabled"; +- compatible = "st,stmpe-ts"; +- /* 8 sample average control */ +- st,ave-ctrl = <3>; +- /* 7 length fractional part in z */ +- st,fraction-z = <7>; +- /* +- * 50 mA typical 80 mA max touchscreen drivers +- * current limit value +- */ +- st,i-drive = <1>; +- /* 1 ms panel driver settling time */ +- st,settling = <3>; +- /* 5 ms touch detect interrupt delay */ +- st,touch-det-delay = <5>; +- }; +- +- stmpe_gpio { +- compatible = "st,stmpe-gpio"; +- }; +- +- stmpe_pwm { +- compatible = "st,stmpe-pwm"; +- #pwm-cells = <2>; +- }; +- }; +-}; +- +-&mcspi3 { +- status = "okay"; +- ti,pindir-d0-out-d1-in; +- +- sn65hvs882: sn65hvs882@0 { +- compatible = "pisosr-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- +- reg = <0>; +- spi-max-frequency = <1000000>; +- spi-cpol; +- }; +-}; +- +-&cpu0 { +- vdd-supply = <&vdd_mpu>; +- voltage-tolerance = <1>; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&davinci_mdio_sw { +- reset-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; +- reset-delay-us = <2>; +- +- phy0: ethernet-phy@4 { +- reg = <4>; +- eee-broken-100tx; +- eee-broken-1000t; +- }; +-}; +- +-&mac_sw { +- status = "okay"; +-}; +- +-&cpsw_port1 { +- phy-handle = <&phy0>; +- phy-mode = "rgmii-rxid"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- status = "disabled"; +-}; +- +-&ocp { +- pruss1_shmem: pruss_shmem@4b200000 { +- status = "okay"; +- compatible = "ti,pruss-shmem"; +- reg = <0x4b200000 0x020000>; +- }; +- +- pruss2_shmem: pruss_shmem@4b280000 { +- status = "okay"; +- compatible = "ti,pruss-shmem"; +- reg = <0x4b280000 0x020000>; +- }; +-}; +- +-&mmc1 { +- status = "okay"; +- vmmc-supply = <&vdd_3v3>; +- vqmmc-supply = <&vdd_sd>; +- bus-width = <4>; +- cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ +- +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins_default>; +-}; +- +-&mmc2 { +- status = "okay"; +- vmmc-supply = <&vdd_1v8>; +- vqmmc-supply = <&vdd_1v8>; +- bus-width = <8>; +- ti,non-removable; +- non-removable; +- mmc-pwrseq = <&emmc_pwrseq>; +- +- ti,needs-special-reset; +- dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; +- dma-names = "tx", "rx"; +- +-}; +- +-&mmc4 { +- /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */ +- /* HS: High speed up to 50 MHz (3.3 V signaling). */ +- /* SDR12: SDR up to 25 MHz (1.8 V signaling). */ +- /* SDR25: SDR up to 50 MHz (1.8 V signaling). */ +- /* SDR50: SDR up to 100 MHz (1.8 V signaling). */ +- /* SDR104: SDR up to 208 MHz (1.8 V signaling) */ +- /* DDR50: DDR up to 50 MHz (1.8 V signaling). */ +- status = "okay"; +- +- ti,needs-special-reset; +- vmmc-supply = <&vdd_3v3>; +- cap-power-off-card; +- keep-power-in-suspend; +- bus-width = <4>; +- ti,non-removable; +- non-removable; +- no-1-8-v; +- max-frequency = <24000000>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- mmc-pwrseq = <&brcmf_pwrseq>; +- +- brcmf: wifi@1 { +- status = "okay"; +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- +- brcm,sd-head-align = <4>; +- brcm,sd_head_align = <4>; +- brcm,sd_sgentry_align = <512>; +- +- interrupt-parent = <&gpio3>; +- interrupts = <23 IRQ_TYPE_LEVEL_LOW>; +- interrupt-names = "host-wake"; +- }; +-}; +- +-&usb2_phy1 { +- phy-supply = <&ldousb_reg>; +-}; +- +-&usb2_phy2 { +- phy-supply = <&ldousb_reg>; +-}; +- +-&usb1 { +- status = "okay"; +- dr_mode = "otg"; +-}; +- +-&omap_dwc3_1 { +- extcon = <&extcon_usb1>; +-}; +- +-&usb2 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&dss { +- status = "okay"; +- vdda_video-supply = <&vdd_1v8_pll>; +-}; +- +-&hdmi { +- status = "okay"; +- vdda-supply = <&vdd_1v8_phy_ldo4>; +- +- port { +- hdmi_out: endpoint { +- remote-endpoint = <&hdmi_encoder_in>; +- }; +- }; +-}; +- +-&bandgap { +- status = "okay"; +-}; +- +-&cpu_alert0 { +- temperature = <55000>; /* milliCelsius */ +-}; +- +-&cpu_crit { +- temperature = <85000>; /* milliCelsius */ +-}; +- +-&gpu_crit { +- temperature = <85000>; /* milliCelsius */ +-}; +- +-&core_crit { +- temperature = <85000>; /* milliCelsius */ +-}; +- +-&dspeve_crit { +- temperature = <85000>; /* milliCelsius */ +-}; +- +-&iva_crit { +- temperature = <85000>; /* milliCelsius */ +-}; +- +-&sata { +- status = "disabled"; +-}; +- +-&sata_phy { +- status = "disabled"; +-}; +- +-/* bluetooth */ +-&uart6 { +- status = "okay"; +-}; +- +-/* cape header stuff */ +-&i2c4 { +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&cpu0_opp_table { +- opp_slow-500000000 { +- opp-shared; +- }; +-}; +- +-&ipu2 { +- status = "okay"; +- memory-region = <&ipu2_memory_region>; +-}; +- +-&ipu1 { +- status = "okay"; +- memory-region = <&ipu1_memory_region>; +-}; +- +-&dsp1 { +- status = "okay"; +- memory-region = <&dsp1_memory_region>; +-}; +- +-&dsp2 { +- status = "okay"; +- memory-region = <&dsp2_memory_region>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am572x-idk-common.dtsi b/scripts/dtc/include-prefixes/arm/am572x-idk-common.dtsi +deleted file mode 100644 +index 1d66278c3a72..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am572x-idk-common.dtsi ++++ /dev/null +@@ -1,203 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include +-#include +-#include "am57xx-idk-common.dtsi" +-#include "dra74-ipu-dsp-common.dtsi" +- +-/ { +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0x80000000>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ipu2_memory_region: ipu2-memory@95800000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x95800000 0x0 0x3800000>; +- reusable; +- status = "okay"; +- }; +- +- dsp1_memory_region: dsp1-memory@99000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x99000000 0x0 0x4000000>; +- reusable; +- status = "okay"; +- }; +- +- ipu1_memory_region: ipu1-memory@9d000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x9d000000 0x0 0x2000000>; +- reusable; +- status = "okay"; +- }; +- +- dsp2_memory_region: dsp2-memory@9f000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x9f000000 0x0 0x800000>; +- reusable; +- status = "okay"; +- }; +- }; +- +- status-leds { +- compatible = "gpio-leds"; +- cpu0-led { +- label = "status0:red:cpu0"; +- gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "cpu0"; +- }; +- +- usr0-led { +- label = "status0:green:usr"; +- gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- heartbeat-led { +- label = "status0:blue:heartbeat"; +- gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "heartbeat"; +- }; +- +- cpu1-led { +- label = "status1:red:cpu1"; +- gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "cpu1"; +- }; +- +- usr1-led { +- label = "status1:green:usr"; +- gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- mmc0-led { +- label = "status1:blue:mmc0"; +- gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "mmc0"; +- }; +- }; +- +- idk-leds { +- status = "disabled"; +- compatible = "gpio-leds"; +- red0-led { +- label = "idk:red0"; +- gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- green0-led { +- label = "idk:green0"; +- gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- blue0-led { +- label = "idk:blue0"; +- gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- red1-led { +- label = "idk:red1"; +- gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- green1-led { +- label = "idk:green1"; +- gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- blue1-led { +- label = "idk:blue1"; +- gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- red2-led { +- label = "idk:red2"; +- gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- green2-led { +- label = "idk:green2"; +- gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- blue2-led { +- label = "idk:blue2"; +- gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- red3-led { +- label = "idk:red3"; +- gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- green3-led { +- label = "idk:green3"; +- gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- blue3-led { +- label = "idk:blue3"; +- gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +-}; +- +-&extcon_usb2 { +- id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; +- vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; +-}; +- +-&sn65hvs882 { +- load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +-}; +- +-&pcie1_rc { +- status = "okay"; +- gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; +-}; +- +-&ipu2 { +- status = "okay"; +- memory-region = <&ipu2_memory_region>; +-}; +- +-&ipu1 { +- status = "okay"; +- memory-region = <&ipu1_memory_region>; +-}; +- +-&dsp1 { +- status = "okay"; +- memory-region = <&dsp1_memory_region>; +-}; +- +-&dsp2 { +- status = "okay"; +- memory-region = <&dsp2_memory_region>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am572x-idk.dts b/scripts/dtc/include-prefixes/arm/am572x-idk.dts +deleted file mode 100644 +index 94a738cb0a4d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am572x-idk.dts ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/dts-v1/; +- +-#include "am5728.dtsi" +-#include "dra7-mmc-iodelay.dtsi" +-#include "dra74x-mmc-iodelay.dtsi" +-#include "am572x-idk-common.dtsi" +- +-/ { +- model = "TI AM5728 IDK"; +- compatible = "ti,am5728-idk", "ti,am5728", "ti,dra7"; +-}; +- +-&mmc1 { +- pinctrl-names = "default", "hs"; +- pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; +- pinctrl-1 = <&mmc1_pins_hs>; +-}; +- +-&mmc2 { +- pinctrl-names = "default", "hs", "ddr_3_3v"; +- pinctrl-0 = <&mmc2_pins_default>; +- pinctrl-1 = <&mmc2_pins_hs>; +- pinctrl-2 = <&mmc2_pins_ddr_rev20>; +-}; +- +-&pruss1_mdio { +- status = "disabled"; +-}; +- +-&pruss2_mdio { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am5748.dtsi b/scripts/dtc/include-prefixes/arm/am5748.dtsi +deleted file mode 100644 +index c260aa1a85bd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am5748.dtsi ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include "dra74x-p.dtsi" +-#include "am57-pruss.dtsi" +- +-/ { +- compatible = "ti,am5748", "ti,dra762", "ti,dra7"; +-}; +- +-/* +- * These modules are not present on AM5748 +- * +- * EVE1, EVE2 +- * ATL +- * VCP1, VCP2 +- * MLB +- * ISS +- * USB3, USB4 +- */ +- +-&usb3_tm { +- status = "disabled"; +-}; +- +-&atl_tm { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am574x-idk.dts b/scripts/dtc/include-prefixes/arm/am574x-idk.dts +deleted file mode 100644 +index 6dff3660bf09..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am574x-idk.dts ++++ /dev/null +@@ -1,49 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +- +-/dts-v1/; +- +-#include "am5748.dtsi" +-#include "dra7-mmc-iodelay.dtsi" +-#include "dra76x-mmc-iodelay.dtsi" +-#include "am572x-idk-common.dtsi" +- +-/ { +- model = "TI AM5748 IDK"; +- compatible = "ti,am5748-idk", "ti,am5748", "ti,dra762", "ti,dra7"; +-}; +- +-&qspi { +- spi-max-frequency = <96000000>; +- m25p80@0 { +- spi-max-frequency = <96000000>; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default", "hs"; +- pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; +- pinctrl-1 = <&mmc1_pins_hs>; +-}; +- +-&mmc2 { +- pinctrl-names = "default", "hs", "ddr_3_3v"; +- pinctrl-0 = <&mmc2_pins_default>; +- pinctrl-1 = <&mmc2_pins_default>; +- pinctrl-2 = <&mmc2_pins_default>; +-}; +- +-&emif1 { +- status = "okay"; +-}; +- +-&pruss1_mdio { +- status = "disabled"; +-}; +- +-&pruss2_mdio { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am57xx-beagle-x15-common.dtsi b/scripts/dtc/include-prefixes/arm/am57xx-beagle-x15-common.dtsi +deleted file mode 100644 +index 994e69ab38d7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am57xx-beagle-x15-common.dtsi ++++ /dev/null +@@ -1,647 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "am5728.dtsi" +-#include "am57xx-commercial-grade.dtsi" +-#include "dra74x-mmc-iodelay.dtsi" +-#include "dra74-ipu-dsp-common.dtsi" +-#include +-#include +- +-/ { +- compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; +- +- aliases { +- rtc0 = &mcp_rtc; +- rtc1 = &tps659038_rtc; +- rtc2 = &rtc; +- display0 = &hdmi0; +- }; +- +- chosen { +- stdout-path = &uart3; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0x80000000>; +- }; +- +- main_12v0: fixedregulator-main_12v0 { +- /* main supply */ +- compatible = "regulator-fixed"; +- regulator-name = "main_12v0"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- evm_5v0: fixedregulator-evm_5v0 { +- /* Output of TPS54531D */ +- compatible = "regulator-fixed"; +- regulator-name = "evm_5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&main_12v0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ipu2_memory_region: ipu2-memory@95800000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x95800000 0x0 0x3800000>; +- reusable; +- status = "okay"; +- }; +- +- dsp1_memory_region: dsp1-memory@99000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x99000000 0x0 0x4000000>; +- reusable; +- status = "okay"; +- }; +- +- ipu1_memory_region: ipu1-memory@9d000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x9d000000 0x0 0x2000000>; +- reusable; +- status = "okay"; +- }; +- +- dsp2_memory_region: dsp2-memory@9f000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x9f000000 0x0 0x800000>; +- reusable; +- status = "okay"; +- }; +- }; +- +- vdd_3v3: fixedregulator-vdd_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_3v3"; +- vin-supply = <®en1>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- aic_dvdd: fixedregulator-aic_dvdd { +- compatible = "regulator-fixed"; +- regulator-name = "aic_dvdd_fixed"; +- vin-supply = <&vdd_3v3>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vtt_fixed: fixedregulator-vtt { +- /* TPS51200 */ +- compatible = "regulator-fixed"; +- regulator-name = "vtt_fixed"; +- vin-supply = <&smps3_reg>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led0 { +- label = "beagle-x15:usr0"; +- gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- +- led1 { +- label = "beagle-x15:usr1"; +- gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "cpu0"; +- default-state = "off"; +- }; +- +- led2 { +- label = "beagle-x15:usr2"; +- gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- +- led3 { +- label = "beagle-x15:usr3"; +- gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "disk-activity"; +- default-state = "off"; +- }; +- }; +- +- gpio_fan: gpio_fan { +- /* Based on 5v 500mA AFB02505HHB */ +- compatible = "gpio-fan"; +- gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; +- gpio-fan,speed-map = <0 0>, +- <13000 1>; +- #cooling-cells = <2>; +- }; +- +- hdmi0: connector { +- compatible = "hdmi-connector"; +- label = "hdmi"; +- +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&tpd12s015_out>; +- }; +- }; +- }; +- +- tpd12s015: encoder { +- compatible = "ti,tpd12s015"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tpd12s015_in: endpoint { +- remote-endpoint = <&hdmi_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- tpd12s015_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +- }; +- }; +- }; +- +- sound0: sound0 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "BeagleBoard-X15"; +- simple-audio-card,widgets = +- "Line", "Line Out", +- "Line", "Line In"; +- simple-audio-card,routing = +- "Line Out", "LLOUT", +- "Line Out", "RLOUT", +- "MIC2L", "Line In", +- "MIC2R", "Line In"; +- simple-audio-card,format = "dsp_b"; +- simple-audio-card,bitclock-master = <&sound0_master>; +- simple-audio-card,frame-master = <&sound0_master>; +- simple-audio-card,bitclock-inversion; +- +- simple-audio-card,cpu { +- sound-dai = <&mcasp3>; +- }; +- +- sound0_master: simple-audio-card,codec { +- sound-dai = <&tlv320aic3104>; +- clocks = <&clkout2_clk>; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- tps659038: tps659038@58 { +- compatible = "ti,tps659038"; +- reg = <0x58>; +- interrupt-parent = <&gpio1>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- +- #interrupt-cells = <2>; +- interrupt-controller; +- +- ti,system-power-controller; +- ti,palmas-override-powerhold; +- +- tps659038_pmic { +- compatible = "ti,tps659038-pmic"; +- +- regulators { +- smps12_reg: smps12 { +- /* VDD_MPU */ +- regulator-name = "smps12"; +- regulator-min-microvolt = < 850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps3_reg: smps3 { +- /* VDD_DDR */ +- regulator-name = "smps3"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps45_reg: smps45 { +- /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ +- regulator-name = "smps45"; +- regulator-min-microvolt = < 850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps6_reg: smps6 { +- /* VDD_CORE */ +- regulator-name = "smps6"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1150000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* SMPS7 unused */ +- +- smps8_reg: smps8 { +- /* VDD_1V8 */ +- regulator-name = "smps8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* SMPS9 unused */ +- +- ldo1_reg: ldo1 { +- /* VDD_SD / VDDSHV8 */ +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo2_reg: ldo2 { +- /* VDD_SHV5 */ +- regulator-name = "ldo2"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo3_reg: ldo3 { +- /* VDDA_1V8_PHYA */ +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo4_reg: ldo4 { +- /* VDDA_1V8_PHYB */ +- regulator-name = "ldo4"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo9_reg: ldo9 { +- /* VDD_RTC */ +- regulator-name = "ldo9"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldoln_reg: ldoln { +- /* VDDA_1V8_PLL */ +- regulator-name = "ldoln"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldousb_reg: ldousb { +- /* VDDA_3V_USB: VDDA_USBHS33 */ +- regulator-name = "ldousb"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- +- regen1: regen1 { +- /* VDD_3V3_ON */ +- regulator-name = "regen1"; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +- +- tps659038_rtc: tps659038_rtc { +- compatible = "ti,palmas-rtc"; +- interrupt-parent = <&tps659038>; +- interrupts = <8 IRQ_TYPE_EDGE_FALLING>; +- wakeup-source; +- }; +- +- tps659038_pwr_button: tps659038_pwr_button { +- compatible = "ti,palmas-pwrbutton"; +- interrupt-parent = <&tps659038>; +- interrupts = <1 IRQ_TYPE_EDGE_FALLING>; +- wakeup-source; +- ti,palmas-long-press-seconds = <12>; +- }; +- +- tps659038_gpio: tps659038_gpio { +- compatible = "ti,palmas-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- extcon_usb2: tps659038_usb { +- compatible = "ti,palmas-usb-vid"; +- ti,enable-vbus-detection; +- vbus-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; +- }; +- +- }; +- +- tmp102: tmp102@48 { +- compatible = "ti,tmp102"; +- reg = <0x48>; +- interrupt-parent = <&gpio7>; +- interrupts = <16 IRQ_TYPE_LEVEL_LOW>; +- #thermal-sensor-cells = <1>; +- }; +- +- tlv320aic3104: tlv320aic3104@18 { +- #sound-dai-cells = <0>; +- compatible = "ti,tlv320aic3104"; +- reg = <0x18>; +- assigned-clocks = <&clkoutmux2_clk_mux>; +- assigned-clock-parents = <&sys_clk2_dclk_div>; +- +- status = "okay"; +- adc-settle-ms = <40>; +- +- AVDD-supply = <&vdd_3v3>; +- IOVDD-supply = <&vdd_3v3>; +- DRVDD-supply = <&vdd_3v3>; +- DVDD-supply = <&aic_dvdd>; +- }; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c32"; +- reg = <0x50>; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +- clock-frequency = <400000>; +- +- mcp_rtc: rtc@6f { +- compatible = "microchip,mcp7941x"; +- reg = <0x6f>; +- interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>, +- <&dra7_pmx_core 0x424>; +- interrupt-names = "irq", "wakeup"; +- +- vcc-supply = <&vdd_3v3>; +- wakeup-source; +- }; +-}; +- +-&gpio7_target { +- ti,no-reset-on-init; +- ti,no-idle-on-init; +-}; +- +-&cpu0 { +- vdd-supply = <&smps12_reg>; +- voltage-tolerance = <1>; +-}; +- +-&uart3 { +- status = "okay"; +- interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, +- <&dra7_pmx_core 0x3f8>; +-}; +- +-&davinci_mdio_sw { +- phy0: ethernet-phy@1 { +- reg = <1>; +- }; +- +- phy1: ethernet-phy@2 { +- reg = <2>; +- }; +-}; +- +-&mac_sw { +- status = "okay"; +-}; +- +-&cpsw_port1 { +- phy-handle = <&phy0>; +- phy-mode = "rgmii-rxid"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- phy-handle = <&phy1>; +- phy-mode = "rgmii-rxid"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&mmc1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins_default>; +- +- bus-width = <4>; +- cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ +- no-1-8-v; +-}; +- +-&mmc2 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins_default>; +- +- vmmc-supply = <&vdd_3v3>; +- vqmmc-supply = <&vdd_3v3>; +- bus-width = <8>; +- non-removable; +- no-1-8-v; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&usb2_phy1 { +- phy-supply = <&ldousb_reg>; +-}; +- +-&usb2_phy2 { +- phy-supply = <&ldousb_reg>; +-}; +- +-&usb1 { +- dr_mode = "host"; +-}; +- +-&omap_dwc3_2 { +- extcon = <&extcon_usb2>; +-}; +- +-&usb2 { +- /* +- * Stand alone usage is peripheral only. +- * However, with some resistor modifications +- * this port can be used via expansion connectors +- * as "host" or "dual-role". If so, provide +- * the necessary dr_mode override in the expansion +- * board's DT. +- */ +- dr_mode = "peripheral"; +-}; +- +-&cpu_trips { +- cpu_alert1: cpu_alert1 { +- temperature = <50000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "active"; +- }; +-}; +- +-&cpu_cooling_maps { +- map1 { +- trip = <&cpu_alert1>; +- cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +-}; +- +-&thermal_zones { +- board_thermal: board_thermal { +- polling-delay-passive = <1250>; /* milliseconds */ +- polling-delay = <1500>; /* milliseconds */ +- +- /* sensor ID */ +- thermal-sensors = <&tmp102 0>; +- +- board_trips: trips { +- board_alert0: board_alert { +- temperature = <40000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "active"; +- }; +- +- board_crit: board_crit { +- temperature = <105000>; /* millicelsius */ +- hysteresis = <0>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- +- board_cooling_maps: cooling-maps { +- map0 { +- trip = <&board_alert0>; +- cooling-device = +- <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +-}; +- +-&dss { +- status = "okay"; +- +- vdda_video-supply = <&ldoln_reg>; +-}; +- +-&hdmi { +- status = "okay"; +- vdda-supply = <&ldo4_reg>; +- +- port { +- hdmi_out: endpoint { +- remote-endpoint = <&tpd12s015_in>; +- }; +- }; +-}; +- +-&pcie1_rc { +- status = "okay"; +- gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; +-}; +- +-&mcasp3 { +- #sound-dai-cells = <0>; +- assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; +- assigned-clock-parents = <&sys_clkin2>; +- status = "okay"; +- +- op-mode = <0>; /* MCASP_IIS_MODE */ +- tdm-slots = <2>; +- /* 4 serializers */ +- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ +- 1 2 0 0 +- >; +- tx-num-evt = <32>; +- rx-num-evt = <32>; +-}; +- +-&ipu2 { +- status = "okay"; +- memory-region = <&ipu2_memory_region>; +-}; +- +-&ipu1 { +- status = "okay"; +- memory-region = <&ipu1_memory_region>; +-}; +- +-&dsp1 { +- status = "okay"; +- memory-region = <&dsp1_memory_region>; +-}; +- +-&dsp2 { +- status = "okay"; +- memory-region = <&dsp2_memory_region>; +-}; +- +-&pruss1_mdio { +- status = "disabled"; +-}; +- +-&pruss2_mdio { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am57xx-beagle-x15-revb1.dts b/scripts/dtc/include-prefixes/arm/am57xx-beagle-x15-revb1.dts +deleted file mode 100644 +index 83e174e053c7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am57xx-beagle-x15-revb1.dts ++++ /dev/null +@@ -1,36 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include "am57xx-beagle-x15-common.dtsi" +- +-/ { +- model = "TI AM5728 BeagleBoard-X15 rev B1"; +-}; +- +-&tpd12s015 { +- gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ +- <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */ +- <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ +-}; +- +-&mmc1 { +- pinctrl-names = "default", "hs"; +- pinctrl-0 = <&mmc1_pins_default>; +- pinctrl-1 = <&mmc1_pins_hs>; +- vmmc-supply = <&vdd_3v3>; +- vqmmc-supply = <&ldo1_reg>; +-}; +- +-&mmc2 { +- pinctrl-names = "default", "hs", "ddr_3_3v"; +- pinctrl-0 = <&mmc2_pins_default>; +- pinctrl-1 = <&mmc2_pins_hs>; +- pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>; +-}; +- +-/* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */ +-&phy1 { +- max-speed = <100>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am57xx-beagle-x15-revc.dts b/scripts/dtc/include-prefixes/arm/am57xx-beagle-x15-revc.dts +deleted file mode 100644 +index 656dd84460d2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am57xx-beagle-x15-revc.dts ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include "am57xx-beagle-x15-common.dtsi" +- +-/ { +- model = "TI AM5728 BeagleBoard-X15 rev C"; +-}; +- +-&tpd12s015 { +- gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ +- <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */ +- <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ +-}; +- +-&mmc1 { +- pinctrl-names = "default", "hs"; +- pinctrl-0 = <&mmc1_pins_default>; +- pinctrl-1 = <&mmc1_pins_hs>; +- vmmc-supply = <&vdd_3v3>; +- vqmmc-supply = <&ldo1_reg>; +-}; +- +-&mmc2 { +- pinctrl-names = "default", "hs", "ddr_3_3v"; +- pinctrl-0 = <&mmc2_pins_default>; +- pinctrl-1 = <&mmc2_pins_hs>; +- pinctrl-2 = <&mmc2_pins_ddr_rev20>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am57xx-beagle-x15.dts b/scripts/dtc/include-prefixes/arm/am57xx-beagle-x15.dts +deleted file mode 100644 +index 0a8b16505ed9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am57xx-beagle-x15.dts ++++ /dev/null +@@ -1,38 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include "am57xx-beagle-x15-common.dtsi" +- +-/ { +- /* NOTE: This describes the "original" pre-production A2 revision */ +- model = "TI AM5728 BeagleBoard-X15"; +-}; +- +-&tpd12s015 { +- gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ +- <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ +- <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ +-}; +- +-&mmc1 { +- pinctrl-names = "default", "hs"; +- pinctrl-0 = <&mmc1_pins_default>; +- pinctrl-1 = <&mmc1_pins_hs>; +- +- vmmc-supply = <&ldo1_reg>; +- no-1-8-v; +-}; +- +-&mmc2 { +- pinctrl-names = "default", "hs", "ddr_3_3v"; +- pinctrl-0 = <&mmc2_pins_default>; +- pinctrl-1 = <&mmc2_pins_hs>; +- pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>; +-}; +- +-/* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */ +-&phy1 { +- max-speed = <100>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am57xx-cl-som-am57x.dts b/scripts/dtc/include-prefixes/arm/am57xx-cl-som-am57x.dts +deleted file mode 100644 +index 2e94f32d9dfc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am57xx-cl-som-am57x.dts ++++ /dev/null +@@ -1,628 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Support for CompuLab CL-SOM-AM57x System-on-Module +- * +- * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ +- * Author: Dmitry Lifshitz +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "am5728.dtsi" +- +-/ { +- model = "CompuLab CL-SOM-AM57x"; +- compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB - minimal configuration */ +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&leds_pins_default>; +- +- led0 { +- label = "cl-som-am57x:green"; +- gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- }; +- +- vdd_3v3: fixedregulator-vdd_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ads7846reg: fixedregulator-ads7846-reg { +- compatible = "regulator-fixed"; +- regulator-name = "ads7846-reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- sound0: sound0 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "CL-SOM-AM57x-Sound-Card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&dailink0_master>; +- simple-audio-card,frame-master = <&dailink0_master>; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack", +- "Microphone", "Microphone Jack", +- "Line", "Line Jack"; +- simple-audio-card,routing = +- "Headphone Jack", "RHPOUT", +- "Headphone Jack", "LHPOUT", +- "LLINEIN", "Line Jack", +- "MICIN", "Mic Bias", +- "Mic Bias", "Microphone Jack"; +- +- dailink0_master: simple-audio-card,cpu { +- sound-dai = <&mcasp3>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&wm8731>; +- system-clock-frequency = <12000000>; +- }; +- }; +-}; +- +-&dra7_pmx_core { +- leds_pins_default: leds_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x347c, PIN_OUTPUT | MUX_MODE14) /* gpmc_a15.gpio2_5 */ +- >; +- }; +- +- i2c1_pins_default: i2c1_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */ +- DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */ +- >; +- }; +- +- i2c3_pins_default: i2c3_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */ +- DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */ +- >; +- }; +- +- i2c4_pins_default: i2c4_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x36ac, PIN_INPUT| MUX_MODE10) /* mcasp1_acl.i2c4_sda */ +- DRA7XX_CORE_IOPAD(0x36b0, PIN_INPUT| MUX_MODE10) /* mcasp1_fsr.i2c4_scl */ +- >; +- }; +- +- tps659038_pins_default: tps659038_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */ +- >; +- }; +- +- mmc2_pins_default: mmc2_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ +- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ +- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ +- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ +- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ +- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ +- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ +- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ +- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ +- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ +- >; +- }; +- +- qspi1_pins: pinmux_qspi1_pins { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ +- DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d0 */ +- DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d1 */ +- DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ +- DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ +- DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */ +- >; +- }; +- +- cpsw_pins_default: cpsw_pins_default { +- pinctrl-single,pins = < +- /* Slave at addr 0x0 */ +- DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tclk */ +- DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tctl */ +- DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3 */ +- DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td2 */ +- DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td1 */ +- DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td0 */ +- DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rclk */ +- DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rctl */ +- DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd3 */ +- DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd2 */ +- DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd1 */ +- DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd0 */ +- +- /* Slave at addr 0x1 */ +- DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_tclk */ +- DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ +- DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ +- DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ +- DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ +- DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ +- DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ +- DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ +- DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ +- DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ +- DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ +- DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ +- >; +- }; +- +- cpsw_pins_sleep: cpsw_pins_sleep { +- pinctrl-single,pins = < +- /* Slave 1 */ +- DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15) +- +- /* Slave 2 */ +- DRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x359c, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x35a0, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x35a4, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x35a8, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x35ac, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE15) +- >; +- }; +- +- davinci_mdio_pins_default: davinci_mdio_pins_default { +- pinctrl-single,pins = < +- /* MDIO */ +- DRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT_PULLUP | MUX_MODE3)/* vin2a_d10.mdio_mclk */ +- DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT_PULLUP | MUX_MODE3) /* vin2a_d11.mdio_d */ +- >; +- }; +- +- davinci_mdio_pins_sleep: davinci_mdio_pins_sleep { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3590, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT | MUX_MODE15) +- >; +- }; +- +- ads7846_pins: pinmux_ads7846_pins { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3464, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpmc_a9.gpio1_31 */ +- >; +- }; +- +- mcasp3_pins_default: mcasp3_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */ +- DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */ +- DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */ +- DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */ +- >; +- }; +- +- mcasp3_pins_sleep: mcasp3_pins_sleep { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15) +- DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15) +- >; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins_default>; +- clock-frequency = <400000>; +-}; +- +-&i2c3 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins_default>; +- clock-frequency = <400000>; +-}; +- +-&i2c4 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pins_default>; +- clock-frequency = <400000>; +- +- tps659038: tps659038@58 { +- compatible = "ti,tps659038"; +- reg = <0x58>; +- interrupt-parent = <&gpio1>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&tps659038_pins_default>; +- +- #interrupt-cells = <2>; +- interrupt-controller; +- +- ti,system-power-controller; +- +- tps659038_pmic { +- compatible = "ti,tps659038-pmic"; +- +- regulators { +- smps12_reg: smps12 { +- /* VDD_MPU */ +- regulator-name = "smps12"; +- regulator-min-microvolt = < 850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps3_reg: smps3 { +- /* VDD_DDR */ +- regulator-name = "smps3"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps45_reg: smps45 { +- /* VDD_DSPEVE */ +- regulator-name = "smps45"; +- regulator-min-microvolt = < 850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps6_reg: smps6 { +- /* VDD_GPU */ +- regulator-name = "smps6"; +- regulator-min-microvolt = < 850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps7_reg: smps7 { +- /* VDD_CORE */ +- regulator-name = "smps7"; +- regulator-min-microvolt = < 850000>; +- regulator-max-microvolt = <1160000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps8_reg: smps8 { +- /* VDD_IVA */ +- regulator-name = "smps8"; +- regulator-min-microvolt = < 850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps9_reg: smps9 { +- /* PMIC_3V3 */ +- regulator-name = "smps9"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- +- ldo1_reg: ldo1 { +- /* VDD_SD / VDDSHV8 */ +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo2_reg: ldo2 { +- /* VDD_1V8 */ +- regulator-name = "ldo2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo3_reg: ldo3 { +- /* VDDA_1V8_PHYA - supplies VDDA_SATA, VDDA_USB1/2/3 */ +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo4_reg: ldo4 { +- /* VDDA_1V8_PHYB - supplies VDDA_HDMI, VDDA_PCIE/0/1 */ +- regulator-name = "ldo4"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo9_reg: ldo9 { +- /* VDD_RTC */ +- regulator-name = "ldo9"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldoln_reg: ldoln { +- /* VDDA_1V8_PLL */ +- regulator-name = "ldoln"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldousb_reg: ldousb { +- /* VDDA_3V_USB: VDDA_USBHS33 */ +- regulator-name = "ldousb"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* regen1 not used */ +- }; +- }; +- +- tps659038_pwr_button: tps659038_pwr_button { +- compatible = "ti,palmas-pwrbutton"; +- interrupt-parent = <&tps659038>; +- interrupts = <1 IRQ_TYPE_EDGE_FALLING>; +- wakeup-source; +- ti,palmas-long-press-seconds = <12>; +- }; +- +- tps659038_gpio: tps659038_gpio { +- compatible = "ti,palmas-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +- +- rtc0: rtc@56 { +- compatible = "emmicro,em3027"; +- reg = <0x56>; +- }; +- +- eeprom_module: atmel@50 { +- compatible = "atmel,24c08"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- wm8731: wm8731@1a { +- #sound-dai-cells = <0>; +- compatible = "wlf,wm8731"; +- reg = <0x1a>; +- status = "okay"; +- }; +-}; +- +-&cpu0 { +- cpu0-supply = <&smps12_reg>; +- voltage-tolerance = <1>; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&mailbox5 { +- status = "okay"; +- mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { +- status = "okay"; +- }; +- mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { +- status = "okay"; +- }; +-}; +- +-&mailbox6 { +- status = "okay"; +- mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { +- status = "okay"; +- }; +- mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { +- status = "okay"; +- }; +-}; +- +-&mmc2 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins_default>; +- +- vmmc-supply = <&vdd_3v3>; +- bus-width = <8>; +- ti,non-removable; +- cap-mmc-dual-data-rate; +-}; +- +-&qspi { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&qspi1_pins>; +- +- spi-max-frequency = <48000000>; +- +- spi_flash: spi_flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,m25p80", "jedec,spi-nor"; +- reg = <0>; /* CS0 */ +- spi-max-frequency = <48000000>; +- +- partition@0 { +- label = "uboot"; +- reg = <0x0 0xc0000>; +- }; +- +- partition@c0000 { +- label = "uboot environment"; +- reg = <0xc0000 0x40000>; +- }; +- +- partition@100000 { +- label = "reserved"; +- reg = <0x100000 0x0>; +- }; +- }; +- +- /* touch controller */ +- touchscreen@1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ads7846_pins>; +- +- compatible = "ti,ads7846"; +- vcc-supply = <&ads7846reg>; +- +- reg = <1>; /* CS1 */ +- spi-max-frequency = <1500000>; +- +- interrupt-parent = <&gpio1>; +- interrupts = <31 0>; +- pendown-gpio = <&gpio1 31 0>; +- +- +- ti,x-min = /bits/ 16 <0x0>; +- ti,x-max = /bits/ 16 <0x0fff>; +- ti,y-min = /bits/ 16 <0x0>; +- ti,y-max = /bits/ 16 <0x0fff>; +- +- ti,x-plate-ohms = /bits/ 16 <180>; +- ti,pressure-max = /bits/ 16 <255>; +- +- ti,debounce-max = /bits/ 16 <30>; +- ti,debounce-tol = /bits/ 16 <10>; +- ti,debounce-rep = /bits/ 16 <1>; +- +- wakeup-source; +- }; +-}; +- +-&mac_sw { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&cpsw_pins_default>; +- pinctrl-1 = <&cpsw_pins_sleep>; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "rgmii-txid"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- phy-handle = <ðphy1>; +- phy-mode = "rgmii-txid"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&davinci_mdio_sw { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&davinci_mdio_pins_default>; +- pinctrl-1 = <&davinci_mdio_pins_sleep>; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&usb2_phy1 { +- phy-supply = <&ldousb_reg>; +-}; +- +-&usb2_phy2 { +- phy-supply = <&ldousb_reg>; +-}; +- +-&usb1 { +- dr_mode = "host"; +-}; +- +-&usb2 { +- dr_mode = "host"; +-}; +- +-&mcasp3 { +- #sound-dai-cells = <0>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mcasp3_pins_default>; +- pinctrl-1 = <&mcasp3_pins_sleep>; +- status = "okay"; +- +- op-mode = <0>; /* MCASP_IIS_MODE */ +- tdm-slots = <2>; +- /* 4 serializers */ +- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ +- 1 2 0 0 +- >; +-}; +- +-&gpio3_target { +- ti,no-reset-on-init; +-}; +- +-&gpio2_target { +- status = "okay"; +- ti,no-reset-on-init; +-}; +- +-&pruss1_mdio { +- status = "disabled"; +-}; +- +-&pruss2_mdio { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am57xx-commercial-grade.dtsi b/scripts/dtc/include-prefixes/arm/am57xx-commercial-grade.dtsi +deleted file mode 100644 +index 3eed6e09c884..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am57xx-commercial-grade.dtsi ++++ /dev/null +@@ -1,24 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-&cpu_alert0 { +- temperature = <80000>; /* milliCelsius */ +-}; +- +-&cpu_crit { +- temperature = <90000>; /* milliCelsius */ +-}; +- +-&gpu_crit { +- temperature = <90000>; /* milliCelsius */ +-}; +- +-&core_crit { +- temperature = <90000>; /* milliCelsius */ +-}; +- +-&dspeve_crit { +- temperature = <90000>; /* milliCelsius */ +-}; +- +-&iva_crit { +- temperature = <90000>; /* milliCelsius */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am57xx-idk-common.dtsi b/scripts/dtc/include-prefixes/arm/am57xx-idk-common.dtsi +deleted file mode 100644 +index 9fcb8944aa3e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am57xx-idk-common.dtsi ++++ /dev/null +@@ -1,608 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include "am57xx-industrial-grade.dtsi" +- +-/ { +- aliases { +- rtc0 = &tps659038_rtc; +- rtc1 = &rtc; +- display0 = &hdmi0; +- }; +- +- chosen { +- stdout-path = &uart3; +- }; +- +- vmain: fixedregulator-vmain { +- compatible = "regulator-fixed"; +- regulator-name = "VMAIN"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- v3_3d: fixedregulator-v3_3d { +- compatible = "regulator-fixed"; +- regulator-name = "V3_3D"; +- vin-supply = <&smps9_reg>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- v1_2d: fixedregulator-v1_2d { +- compatible = "regulator-fixed"; +- regulator-name = "V1_2D"; +- vin-supply = <&vmain>; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vtt_fixed: fixedregulator-vtt { +- /* TPS51200 */ +- compatible = "regulator-fixed"; +- regulator-name = "vtt_fixed"; +- vin-supply = <&v3_3d>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- leds-iio { +- status = "disabled"; +- compatible = "gpio-leds"; +- led-out0 { +- label = "out0"; +- gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out1 { +- label = "out1"; +- gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out2 { +- label = "out2"; +- gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out3 { +- label = "out3"; +- gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out4 { +- label = "out4"; +- gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out5 { +- label = "out5"; +- gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out6 { +- label = "out6"; +- gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-out7 { +- label = "out7"; +- gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- hdmi0: connector@0 { +- compatible = "hdmi-connector"; +- label = "hdmi"; +- +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&tpd12s015_out>; +- }; +- }; +- }; +- +- tpd12s015: encoder@0 { +- compatible = "ti,tpd12s016", "ti,tpd12s015"; +- +- gpios = <0>, /* optional CT_CP_HPD */ +- <0>, /* optional LS_OE */ +- <&gpio7 12 GPIO_ACTIVE_HIGH>; /* HPD */ +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tpd12s015_in: endpoint@0 { +- remote-endpoint = <&hdmi_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- tpd12s015_out: endpoint@0 { +- remote-endpoint = <&hdmi_connector_in>; +- }; +- }; +- }; +- }; +- +- src_clk_x1: src_clk_x1 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <20000000>; +- }; +-}; +- +-&dra7_pmx_core { +- dcan1_pins_default: dcan1_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ +- DRA7XX_CORE_IOPAD(0x37d4, PIN_INPUT_PULLUP | MUX_MODE0) /* dcan1_rx */ +- >; +- }; +- +- dcan1_pins_sleep: dcan1_pins_sleep { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ +- DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */ +- >; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- tps659038: tps659038@58 { +- compatible = "ti,tps659038"; +- reg = <0x58>; +- interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_HIGH +- &dra7_pmx_core 0x418>; +- #interrupt-cells = <2>; +- interrupt-controller; +- ti,system-power-controller; +- ti,palmas-override-powerhold; +- +- tps659038_pmic { +- compatible = "ti,tps659038-pmic"; +- +- smps12-in-supply = <&vmain>; +- smps3-in-supply = <&vmain>; +- smps45-in-supply = <&vmain>; +- smps6-in-supply = <&vmain>; +- smps7-in-supply = <&vmain>; +- smps8-in-supply = <&vmain>; +- smps9-in-supply = <&vmain>; +- ldo1-in-supply = <&vmain>; +- ldo2-in-supply = <&vmain>; +- ldo3-in-supply = <&vmain>; +- ldo4-in-supply = <&vmain>; +- ldo9-in-supply = <&vmain>; +- ldoln-in-supply = <&vmain>; +- ldousb-in-supply = <&vmain>; +- ldortc-in-supply = <&vmain>; +- +- regulators { +- smps12_reg: smps12 { +- /* VDD_MPU */ +- regulator-name = "smps12"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps3_reg: smps3 { +- /* VDD_DDR EMIF1 EMIF2 */ +- regulator-name = "smps3"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps45_reg: smps45 { +- /* VDD_DSPEVE on AM572 */ +- /* VDD_IVA + VDD_DSP on AM571 */ +- regulator-name = "smps45"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps6_reg: smps6 { +- /* VDD_GPU */ +- regulator-name = "smps6"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps7_reg: smps7 { +- /* VDD_CORE */ +- regulator-name = "smps7"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1150000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps8_reg: smps8 { +- /* 5728 - VDD_IVAHD */ +- /* 5718 - N.C. test point */ +- regulator-name = "smps8"; +- }; +- +- smps9_reg: smps9 { +- /* VDD_3_3D */ +- regulator-name = "smps9"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo1_reg: ldo1 { +- /* VDDSHV8 - VSDMMC */ +- /* NOTE: on rev 1.3a, data supply */ +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo2_reg: ldo2 { +- /* VDDSH18V */ +- regulator-name = "ldo2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo3_reg: ldo3 { +- /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */ +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo4_reg: ldo4 { +- /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/ +- regulator-name = "ldo4"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* LDO5-8 unused */ +- +- ldo9_reg: ldo9 { +- /* VDD_RTC */ +- regulator-name = "ldo9"; +- regulator-min-microvolt = <840000>; +- regulator-max-microvolt = <1160000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldoln_reg: ldoln { +- /* VDDA_1V8_PLL */ +- regulator-name = "ldoln"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldousb_reg: ldousb { +- /* VDDA_3V_USB: VDDA_USBHS33 */ +- regulator-name = "ldousb"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldortc_reg: ldortc { +- /* VDDA_RTC */ +- regulator-name = "ldortc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- regen1: regen1 { +- /* VDD_3V3_ON */ +- regulator-name = "regen1"; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- regen2: regen2 { +- /* Needed for PMIC internal resource */ +- regulator-name = "regen2"; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +- +- tps659038_rtc: tps659038_rtc { +- compatible = "ti,palmas-rtc"; +- interrupt-parent = <&tps659038>; +- interrupts = <8 IRQ_TYPE_EDGE_FALLING>; +- wakeup-source; +- }; +- +- tps659038_pwr_button: tps659038_pwr_button { +- compatible = "ti,palmas-pwrbutton"; +- interrupt-parent = <&tps659038>; +- interrupts = <1 IRQ_TYPE_EDGE_FALLING>; +- wakeup-source; +- ti,palmas-long-press-seconds = <12>; +- }; +- +- tps659038_gpio: tps659038_gpio { +- compatible = "ti,palmas-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- extcon_usb2: tps659038_usb { +- compatible = "ti,palmas-usb-vid"; +- ti,enable-vbus-detection; +- ti,enable-id-detection; +- /* ID & VBUS GPIOs provided in board dts */ +- }; +- }; +- +- tpic2810: tpic2810@60 { +- compatible = "ti,tpic2810"; +- reg = <0x60>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- dsi_bridge: tc358778@e { +- compatible = "toshiba,tc358778", "toshiba,tc358768"; +- reg = <0xe>; +- status = "disabled"; +- +- clocks = <&src_clk_x1>; +- clock-names = "refclk"; +- +- vddc-supply = <&v1_2d>; +- vddmipi-supply = <&v1_2d>; +- vddio-supply = <&v3_3d>; +- +- dsi_bridge_ports: ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- rgb_in: endpoint { +- remote-endpoint = <&dpi_out>; +- data-lines = <24>; +- }; +- }; +- }; +- }; +-}; +- +-&mcspi3 { +- status = "okay"; +- ti,pindir-d0-out-d1-in; +- +- sn65hvs882: sn65hvs882@0 { +- compatible = "pisosr-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- +- reg = <0>; +- spi-max-frequency = <1000000>; +- spi-cpol; +- }; +-}; +- +-&uart3 { +- status = "okay"; +- interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH +- &dra7_pmx_core 0x248>; +-}; +- +-&rtc { +- status = "okay"; +- ext-clk-src; +-}; +- +-&mac_sw { +- status = "okay"; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "rgmii-rxid"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- phy-handle = <ðphy1>; +- phy-mode = "rgmii-rxid"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&davinci_mdio_sw { +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&usb2_phy1 { +- phy-supply = <&ldousb_reg>; +-}; +- +-&usb2_phy2 { +- phy-supply = <&ldousb_reg>; +-}; +- +-&usb1 { +- dr_mode = "host"; +-}; +- +-&omap_dwc3_2 { +- extcon = <&extcon_usb2>; +-}; +- +-&usb2 { +- extcon = <&extcon_usb2>; +- dr_mode = "otg"; +-}; +- +-&mmc1 { +- status = "okay"; +- vmmc-supply = <&v3_3d>; +- vqmmc-supply = <&ldo1_reg>; +- bus-width = <4>; +- cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ +- no-1-8-v; +-}; +- +-&mmc2 { +- status = "okay"; +- vmmc-supply = <&v3_3d>; +- vqmmc-supply = <&v3_3d>; +- bus-width = <8>; +- non-removable; +- max-frequency = <96000000>; +- no-1-8-v; +-}; +- +-&dcan1 { +- status = "okay"; +- pinctrl-names = "default", "sleep", "active"; +- pinctrl-0 = <&dcan1_pins_sleep>; +- pinctrl-1 = <&dcan1_pins_sleep>; +- pinctrl-2 = <&dcan1_pins_default>; +-}; +- +-&qspi { +- status = "okay"; +- +- spi-max-frequency = <76800000>; +- m25p80@0 { +- compatible = "s25fl256s1", "jedec,spi-nor"; +- spi-max-frequency = <76800000>; +- reg = <0>; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* MTD partition table. +- * The ROM checks the first four physical blocks +- * for a valid file to boot and the flash here is +- * 64KiB block size. +- */ +- partition@0 { +- label = "QSPI.SPL"; +- reg = <0x00000000 0x000040000>; +- }; +- partition@1 { +- label = "QSPI.u-boot"; +- reg = <0x00040000 0x00100000>; +- }; +- partition@2 { +- label = "QSPI.u-boot-spl-os"; +- reg = <0x00140000 0x00080000>; +- }; +- partition@3 { +- label = "QSPI.u-boot-env"; +- reg = <0x001c0000 0x00010000>; +- }; +- partition@4 { +- label = "QSPI.u-boot-env.backup1"; +- reg = <0x001d0000 0x0010000>; +- }; +- partition@5 { +- label = "QSPI.kernel"; +- reg = <0x001e0000 0x0800000>; +- }; +- partition@6 { +- label = "QSPI.file-system"; +- reg = <0x009e0000 0x01620000>; +- }; +- }; +-}; +- +-&cpu0 { +- vdd-supply = <&smps12_reg>; +-}; +- +-&hdmi { +- status = "okay"; +- +- vdda-supply = <&ldo4_reg>; +- +- port { +- hdmi_out: endpoint { +- remote-endpoint = <&tpd12s015_in>; +- }; +- }; +-}; +- +-&dss { +- status = "okay"; +- +- vdda_video-supply = <&ldoln_reg>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- dpi_out: endpoint { +- remote-endpoint = <&rgb_in>; +- data-lines = <24>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am57xx-industrial-grade.dtsi b/scripts/dtc/include-prefixes/arm/am57xx-industrial-grade.dtsi +deleted file mode 100644 +index 422f953fc8d8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am57xx-industrial-grade.dtsi ++++ /dev/null +@@ -1,24 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-&cpu_alert0 { +- temperature = <90000>; /* milliCelsius */ +-}; +- +-&cpu_crit { +- temperature = <105000>; /* milliCelsius */ +-}; +- +-&gpu_crit { +- temperature = <105000>; /* milliCelsius */ +-}; +- +-&core_crit { +- temperature = <105000>; /* milliCelsius */ +-}; +- +-&dspeve_crit { +- temperature = <105000>; /* milliCelsius */ +-}; +- +-&iva_crit { +- temperature = <105000>; /* milliCelsius */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm/am57xx-sbc-am57x.dts b/scripts/dtc/include-prefixes/arm/am57xx-sbc-am57x.dts +deleted file mode 100644 +index beef63e8a005..000000000000 +--- a/scripts/dtc/include-prefixes/arm/am57xx-sbc-am57x.dts ++++ /dev/null +@@ -1,176 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Support for CompuLab SBC-AM57x single board computer +- * +- * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ +- * Author: Dmitry Lifshitz +- */ +- +-#include "am57xx-cl-som-am57x.dts" +-#include "compulab-sb-som.dtsi" +- +-/ { +- model = "CompuLab CL-SOM-AM57x on SB-SOM-AM57x"; +- compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; +- +- aliases { +- display0 = &lcd0; +- display1 = &hdmi; +- }; +-}; +- +-&dra7_pmx_core { +- uart3_pins_default: uart3_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ +- DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ +- >; +- }; +- +- mmc1_pins_default: mmc1_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ +- DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1_sdcd.gpio6_27 */ +- DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT | MUX_MODE14) /* mmc1_sdwp.gpio6_28 */ +- >; +- }; +- +- usb1_pins: pinmux_usb1_pins { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ +- >; +- }; +- +- i2c5_pins_default: i2c5_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT| MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ +- DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT| MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ +- >; +- }; +- +- lcd_pins_default: lcd_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3564, PIN_OUTPUT | MUX_MODE14) /* vin2a_vsync0.gpio4_0 */ +- >; +- }; +- +- hdmi_pins: pinmux_hdmi_pins { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ +- DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ +- >; +- }; +- +- hdmi_conn_pins: pinmux_hdmi_conn_pins { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT | MUX_MODE14) /* spi1_cs2.gpio7_12 */ +- >; +- }; +-}; +- +-&uart3 { +- status = "okay"; +- interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, +- <&dra7_pmx_core 0x3f8>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins_default>; +-}; +- +-&mmc1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins_default>; +- +- vmmc-supply = <&ldo1_reg>; +- bus-width = <4>; +- cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; +-}; +- +-&usb1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb1_pins>; +-}; +- +-&i2c5 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_pins_default>; +- clock-frequency = <400000>; +- +- eeprom_base: atmel@54 { +- compatible = "atmel,24c08"; +- reg = <0x54>; +- pagesize = <16>; +- }; +- +- pca9555: pca9555@20 { +- compatible = "nxp,pca9555"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&dss { +- status = "okay"; +- +- vdda_video-supply = <&ldoln_reg>; +- +- port { +- dpi_lcd_out: endpoint { +- remote-endpoint = <&lcd_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-&lcd0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_pins_default>; +- +- enable-gpios = <&pca9555 14 GPIO_ACTIVE_HIGH +- &gpio4 0 GPIO_ACTIVE_HIGH>; +- +- port { +- lcd_in: endpoint { +- remote-endpoint = <&dpi_lcd_out>; +- data-lines = <24>; +- }; +- }; +-}; +- +-&hdmi { +- status = "okay"; +- vdda-supply = <&ldo4_reg>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_pins>; +- +- port { +- hdmi_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- lanes = <1 0 3 2 5 4 7 6>; +- }; +- }; +-}; +- +-&hdmi_conn { +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_conn_pins>; +- +- hpd-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_out>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/animeo_ip.dts b/scripts/dtc/include-prefixes/arm/animeo_ip.dts +deleted file mode 100644 +index 7da718abbd85..000000000000 +--- a/scripts/dtc/include-prefixes/arm/animeo_ip.dts ++++ /dev/null +@@ -1,197 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * animeo_ip.dts - Device Tree file for Somfy Animeo IP Boards +- * +- * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +- +-/dts-v1/; +-#include "at91sam9260.dtsi" +- +-/ { +- model = "Somfy Animeo IP"; +- compatible = "somfy,animeo-ip", "atmel,at91sam9260", "atmel,at91sam9"; +- +- aliases { +- serial0 = &usart1; +- serial1 = &usart2; +- serial2 = &usart0; +- serial3 = &dbgu; +- serial4 = &usart3; +- serial5 = &uart0; +- serial6 = &uart1; +- }; +- +- chosen { +- stdout-path = &usart2; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <18432000>; +- }; +- }; +- +- ahb { +- apb { +- tcb0: timer@fffa0000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +- }; +- +- usart0: serial@fffb0000 { +- pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts>; +- linux,rs485-enabled-at-boot-time; +- status = "okay"; +- }; +- +- usart1: serial@fffb4000 { +- pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts>; +- linux,rs485-enabled-at-boot-time; +- status = "okay"; +- }; +- +- usart2: serial@fffb8000 { +- pinctrl-0 = <&pinctrl_usart2>; +- status = "okay"; +- }; +- +- macb0: ethernet@fffc4000 { +- pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_rmii_mii>; +- phy-mode = "mii"; +- status = "okay"; +- }; +- +- mmc0: mmc@fffa8000 { +- pinctrl-0 = <&pinctrl_mmc0_clk +- &pinctrl_mmc0_slot1_cmd_dat0 +- &pinctrl_mmc0_slot1_dat1_3>; +- pinctrl-names = "default"; +- status = "okay"; +- +- slot@1 { +- reg = <1>; +- bus-width = <4>; +- }; +- }; +- +- watchdog@fffffd40 { +- status = "okay"; +- }; +- }; +- +- ebi: ebi@10000000 { +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; +- pinctrl-names = "default"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "soft"; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- barebox@0 { +- label = "barebox"; +- reg = <0x0 0x58000>; +- }; +- +- u_boot_env@58000 { +- label = "u_boot_env"; +- reg = <0x58000 0x8000>; +- }; +- +- ubi@60000 { +- label = "ubi"; +- reg = <0x60000 0x1FA0000>; +- }; +- }; +- }; +- }; +- }; +- +- usb0: ohci@500000 { +- num-ports = <2>; +- atmel,vbus-gpio = <&pioB 15 GPIO_ACTIVE_LOW>; +- status = "okay"; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- power_green { +- label = "power_green"; +- gpios = <&pioC 17 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- power_red { +- label = "power_red"; +- gpios = <&pioA 2 GPIO_ACTIVE_HIGH>; +- }; +- +- tx_green { +- label = "tx_green"; +- gpios = <&pioC 19 GPIO_ACTIVE_HIGH>; +- }; +- +- tx_red { +- label = "tx_red"; +- gpios = <&pioC 18 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- keyswitch_in { +- label = "keyswitch_in"; +- gpios = <&pioB 1 GPIO_ACTIVE_HIGH>; +- linux,code = <28>; +- wakeup-source; +- }; +- +- error_in { +- label = "error_in"; +- gpios = <&pioB 2 GPIO_ACTIVE_HIGH>; +- linux,code = <29>; +- wakeup-source; +- }; +- +- btn { +- label = "btn"; +- gpios = <&pioC 23 GPIO_ACTIVE_HIGH>; +- linux,code = <31>; +- wakeup-source; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/arm-realview-eb-11mp-bbrevd-ctrevb.dts b/scripts/dtc/include-prefixes/arm/arm-realview-eb-11mp-bbrevd-ctrevb.dts +deleted file mode 100644 +index e18769df9fd9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/arm-realview-eb-11mp-bbrevd-ctrevb.dts ++++ /dev/null +@@ -1,32 +0,0 @@ +-/* +- * Copyright 2016 Linaro Ltd +- * +- * Permission is hereby granted, free of charge, to any person obtaining a copy +- * of this software and associated documentation files (the "Software"), to deal +- * in the Software without restriction, including without limitation the rights +- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +- * copies of the Software, and to permit persons to whom the Software is +- * furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +- * THE SOFTWARE. +- */ +- +-#include "arm-realview-eb-11mp-ctrevb.dts" +-#include "arm-realview-eb-bbrevd.dtsi" +- +-/* +- * This is the EB with the new Revision D baseboard with SMSC9118 ethernet and +- * the Rev B core tile. +- */ +-/ { +- model = "ARM RealView Emulation Baseboard Rev D with ARM11MPCore Core Tile Rev B"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/arm-realview-eb-11mp-bbrevd.dts b/scripts/dtc/include-prefixes/arm/arm-realview-eb-11mp-bbrevd.dts +deleted file mode 100644 +index 26b1c69e9f43..000000000000 +--- a/scripts/dtc/include-prefixes/arm/arm-realview-eb-11mp-bbrevd.dts ++++ /dev/null +@@ -1,28 +0,0 @@ +-/* +- * Copyright 2016 Linaro Ltd +- * +- * Permission is hereby granted, free of charge, to any person obtaining a copy +- * of this software and associated documentation files (the "Software"), to deal +- * in the Software without restriction, including without limitation the rights +- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +- * copies of the Software, and to permit persons to whom the Software is +- * furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +- * THE SOFTWARE. +- */ +- +-#include "arm-realview-eb-11mp.dts" +-#include "arm-realview-eb-bbrevd.dtsi" +- +-/ { +- model = "ARM RealView Emulation Baseboard Rev D with ARM11MPCore Rev C Core Tile"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/arm-realview-eb-11mp-ctrevb.dts b/scripts/dtc/include-prefixes/arm/arm-realview-eb-11mp-ctrevb.dts +deleted file mode 100644 +index e68527b0d552..000000000000 +--- a/scripts/dtc/include-prefixes/arm/arm-realview-eb-11mp-ctrevb.dts ++++ /dev/null +@@ -1,93 +0,0 @@ +-/* +- * Copyright 2016 Linaro Ltd +- * +- * Permission is hereby granted, free of charge, to any person obtaining a copy +- * of this software and associated documentation files (the "Software"), to deal +- * in the Software without restriction, including without limitation the rights +- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +- * copies of the Software, and to permit persons to whom the Software is +- * furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +- * THE SOFTWARE. +- */ +- +-#include "arm-realview-eb-11mp.dts" +- +-/ { +- model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev B"; +-}; +- +-/* +- * The revision B has a distinctly different layout of the syscon, so +- * append a specific compatible-string. +- */ +-&syscon { +- compatible = "arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon", "simple-mfd"; +-}; +- +-&intc { +- reg = <0x10101000 0x1000>, +- <0x10100100 0x100>; +-}; +- +-&L2 { +- reg = <0x10102000 0x1000>; +-}; +- +-&scu { +- reg = <0x10100000 0x100>; +-}; +- +-&twd_timer { +- reg = <0x10100600 0x20>; +-}; +- +-&twd_wdog { +- reg = <0x10100620 0x20>; +-}; +- +-/* +- * On revision B, we cannot reach the secondary interrupt +- * controller, as a result, some peripherals that are dependent +- * on their IRQ cannot be reached, so disable them. +- */ +-&intc_second { +- status = "disabled"; +-}; +- +-&gpio0 { +- status = "disabled"; +-}; +- +-&gpio1 { +- status = "disabled"; +-}; +- +-&gpio2 { +- status = "disabled"; +-}; +- +-&serial2 { +- status = "disabled"; +-}; +- +-&serial3 { +- status = "disabled"; +-}; +- +-&ssp { +- status = "disabled"; +-}; +- +-&wdog { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/arm-realview-eb-11mp.dts b/scripts/dtc/include-prefixes/arm/arm-realview-eb-11mp.dts +deleted file mode 100644 +index aac1edd4b227..000000000000 +--- a/scripts/dtc/include-prefixes/arm/arm-realview-eb-11mp.dts ++++ /dev/null +@@ -1,74 +0,0 @@ +-/* +- * Copyright 2016 Linaro Ltd +- * +- * Permission is hereby granted, free of charge, to any person obtaining a copy +- * of this software and associated documentation files (the "Software"), to deal +- * in the Software without restriction, including without limitation the rights +- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +- * copies of the Software, and to permit persons to whom the Software is +- * furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +- * THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "arm-realview-eb-mp.dtsi" +- +-/ { +- model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C Core Tile"; +- arm,hbi = <0x146>; +- +- /* +- * This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB. +- * Reference: ARM DUI 0318F +- * +- * To run this machine with QEMU, specify the following: +- * qemu-system-arm -M realview-eb-mpcore -smp cpus=4 +- */ +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "arm,realview-smp"; +- +- MP11_0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,arm11mpcore"; +- reg = <0>; +- next-level-cache = <&L2>; +- }; +- +- MP11_1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,arm11mpcore"; +- reg = <1>; +- next-level-cache = <&L2>; +- }; +- +- MP11_2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,arm11mpcore"; +- reg = <2>; +- next-level-cache = <&L2>; +- }; +- +- MP11_3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,arm11mpcore"; +- reg = <3>; +- next-level-cache = <&L2>; +- }; +- }; +-}; +- +-&pmu { +- interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/arm-realview-eb-a9mp-bbrevd.dts b/scripts/dtc/include-prefixes/arm/arm-realview-eb-a9mp-bbrevd.dts +deleted file mode 100644 +index 42efac7496ef..000000000000 +--- a/scripts/dtc/include-prefixes/arm/arm-realview-eb-a9mp-bbrevd.dts ++++ /dev/null +@@ -1,28 +0,0 @@ +-/* +- * Copyright 2016 Linaro Ltd +- * +- * Permission is hereby granted, free of charge, to any person obtaining a copy +- * of this software and associated documentation files (the "Software"), to deal +- * in the Software without restriction, including without limitation the rights +- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +- * copies of the Software, and to permit persons to whom the Software is +- * furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +- * THE SOFTWARE. +- */ +- +-#include "arm-realview-eb-a9mp.dts" +-#include "arm-realview-eb-bbrevd.dtsi" +- +-/ { +- model = "ARM RealView EB Baseboard Rev D Cortex A9 MPCore"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/arm-realview-eb-a9mp.dts b/scripts/dtc/include-prefixes/arm/arm-realview-eb-a9mp.dts +deleted file mode 100644 +index 967684b3636c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/arm-realview-eb-a9mp.dts ++++ /dev/null +@@ -1,70 +0,0 @@ +-/* +- * Copyright 2016 Linaro Ltd +- * +- * Permission is hereby granted, free of charge, to any person obtaining a copy +- * of this software and associated documentation files (the "Software"), to deal +- * in the Software without restriction, including without limitation the rights +- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +- * copies of the Software, and to permit persons to whom the Software is +- * furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +- * THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "arm-realview-eb-mp.dtsi" +- +-/ { +- model = "ARM RealView EB Cortex A9 MPCore"; +- +- /* +- * This is the Cortex A9 MPCore tile used with the +- * RealView EB. +- */ +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "arm,realview-smp"; +- +- A9_0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- next-level-cache = <&L2>; +- }; +- +- A9_1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <1>; +- next-level-cache = <&L2>; +- }; +- +- A9_2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <2>; +- next-level-cache = <&L2>; +- }; +- +- A9_3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <3>; +- next-level-cache = <&L2>; +- }; +- }; +-}; +- +-&pmu { +- interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/arm-realview-eb-bbrevd.dts b/scripts/dtc/include-prefixes/arm/arm-realview-eb-bbrevd.dts +deleted file mode 100644 +index f533c8b49d97..000000000000 +--- a/scripts/dtc/include-prefixes/arm/arm-realview-eb-bbrevd.dts ++++ /dev/null +@@ -1,29 +0,0 @@ +-/* +- * Copyright 2016 Linaro Ltd +- * +- * Permission is hereby granted, free of charge, to any person obtaining a copy +- * of this software and associated documentation files (the "Software"), to deal +- * in the Software without restriction, including without limitation the rights +- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +- * copies of the Software, and to permit persons to whom the Software is +- * furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +- * THE SOFTWARE. +- */ +- +-/* This derives from the Realview Baseboard, and overlays the new ethernet */ +-#include "arm-realview-eb.dts" +-#include "arm-realview-eb-bbrevd.dtsi" +- +-/ { +- model = "ARM RealView Emulation Baseboard Rev D"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/arm-realview-eb-bbrevd.dtsi b/scripts/dtc/include-prefixes/arm/arm-realview-eb-bbrevd.dtsi +deleted file mode 100644 +index a79e1d1d30a7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/arm-realview-eb-bbrevd.dtsi ++++ /dev/null +@@ -1,45 +0,0 @@ +-/* +- * Copyright 2016 Linaro Ltd +- * +- * Permission is hereby granted, free of charge, to any person obtaining a copy +- * of this software and associated documentation files (the "Software"), to deal +- * in the Software without restriction, including without limitation the rights +- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +- * copies of the Software, and to permit persons to whom the Software is +- * furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +- * THE SOFTWARE. +- */ +- +-/ { +- /* Introduce a fixed regulator for the new ethernet controller */ +- veth: fixedregulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "veth"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +-}; +- +-/* +- * The revision D has a different ethernet controller that the elder boards: +- * the older board uses LAN91C111 but the new one uses LAN9118. +- */ +-ðernet { +- compatible = "smsc,lan9118", "smsc,lan9115"; +- phy-mode = "mii"; +- smsc,irq-active-high; +- smsc,irq-push-pull; +- vdd33a-supply = <&veth>; +- vddvario-supply = <&veth>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/arm-realview-eb-mp.dtsi b/scripts/dtc/include-prefixes/arm/arm-realview-eb-mp.dtsi +deleted file mode 100644 +index 26783d053ac7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/arm-realview-eb-mp.dtsi ++++ /dev/null +@@ -1,220 +0,0 @@ +-/* +- * Copyright 2016 Linaro Ltd +- * +- * Permission is hereby granted, free of charge, to any person obtaining a copy +- * of this software and associated documentation files (the "Software"), to deal +- * in the Software without restriction, including without limitation the rights +- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +- * copies of the Software, and to permit persons to whom the Software is +- * furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +- * THE SOFTWARE. +- */ +- +-#include +-#include +-#include "arm-realview-eb.dtsi" +- +-/* +- * This is the common include file for all MPCore variants of the +- * Evaluation Baseboard, i.e. ARM11MPCore, ARM11MPCore Revision B +- * and Cortex-A9 MPCore. +- */ +-/ { +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "arm,realview-eb-soc", "simple-bus"; +- regmap = <&syscon>; +- ranges; +- +- /* Primary interrupt controller in the test chip */ +- intc: interrupt-controller@1f000100 { +- compatible = "arm,eb11mp-gic"; +- #interrupt-cells = <3>; +- #address-cells = <1>; +- interrupt-controller; +- reg = <0x1f001000 0x1000>, +- <0x1f000100 0x100>; +- }; +- +- /* Secondary interrupt controller on the FPGA */ +- intc_second: interrupt-controller@10040000 { +- compatible = "arm,pl390"; +- #interrupt-cells = <3>; +- #address-cells = <1>; +- interrupt-controller; +- reg = <0x10041000 0x1000>, +- <0x10040000 0x100>; +- interrupt-parent = <&intc>; +- interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- L2: cache-controller { +- compatible = "arm,l220-cache"; +- reg = <0x1f002000 0x1000>; +- interrupt-parent = <&intc>; +- interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, +- <0 30 IRQ_TYPE_LEVEL_HIGH>, +- <0 31 IRQ_TYPE_LEVEL_HIGH>; +- cache-unified; +- cache-level = <2>; +- /* +- * Override default cache size, sets and +- * associativity as these may be erroneously set +- * up by boot loader(s), probably for safety +- * since th outer sync operation can cause the +- * cache to hang unless disabled. +- */ +- cache-size = <1048576>; // 1MB +- cache-sets = <4096>; +- cache-line-size = <32>; +- arm,shared-override; +- arm,parity-enable; +- arm,outer-sync-disable; +- }; +- +- scu: scu@1f000000 { +- compatible = "arm,arm11mp-scu"; +- reg = <0x1f000000 0x100>; +- }; +- +- twd_timer: timer@1f000600 { +- compatible = "arm,arm11mp-twd-timer"; +- reg = <0x1f000600 0x20>; +- interrupt-parent = <&intc>; +- interrupts = <1 13 0xf04>; +- }; +- +- twd_wdog: watchdog@1f000620 { +- compatible = "arm,arm11mp-twd-wdt"; +- reg = <0x1f000620 0x20>; +- interrupt-parent = <&intc>; +- interrupts = <1 14 0xf04>; +- }; +- +- /* PMU with one IRQ line per core */ +- pmu: pmu@0 { +- compatible = "arm,arm11mpcore-pmu"; +- interrupt-parent = <&intc>; +- interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, +- <0 18 IRQ_TYPE_LEVEL_HIGH>, +- <0 19 IRQ_TYPE_LEVEL_HIGH>, +- <0 20 IRQ_TYPE_LEVEL_HIGH>; +- }; +- }; +-}; +- +-/* +- * This adapts all the peripherals to the interrupt routing +- * to the GIC on the core tile. +- */ +- +-ðernet { +- interrupt-parent = <&intc>; +- interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&usb { +- interrupt-parent = <&intc>; +- interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&aaci { +- interrupt-parent = <&intc>; +- interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&mmc { +- interrupt-parent = <&intc>; +- interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>, +- <0 15 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&kmi0 { +- interrupt-parent = <&intc>; +- interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&kmi1 { +- interrupt-parent = <&intc>; +- interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&serial0 { +- interrupt-parent = <&intc>; +- interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&serial1 { +- interrupt-parent = <&intc>; +- interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&timer01 { +- interrupt-parent = <&intc>; +- interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&timer23 { +- interrupt-parent = <&intc>; +- interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&rtc { +- interrupt-parent = <&intc>; +- interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-/* +- * On revision A, these peripherals does not have their IRQ lines +- * routed to the core tile, but they can be reached on the secondary +- * GIC. +- */ +-&gpio0 { +- interrupt-parent = <&intc_second>; +- interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&gpio1 { +- interrupt-parent = <&intc_second>; +- interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&gpio2 { +- interrupt-parent = <&intc_second>; +- interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&serial2 { +- interrupt-parent = <&intc_second>; +- interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; +- status = "okay"; +-}; +- +-&serial3 { +- interrupt-parent = <&intc_second>; +- interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; +- status = "okay"; +-}; +- +-&ssp { +- interrupt-parent = <&intc_second>; +- interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; +- status = "okay"; +-}; +- +-&wdog { +- interrupt-parent = <&intc_second>; +- interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/arm-realview-eb.dts b/scripts/dtc/include-prefixes/arm/arm-realview-eb.dts +deleted file mode 100644 +index 15431077f00c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/arm-realview-eb.dts ++++ /dev/null +@@ -1,166 +0,0 @@ +-/* +- * Copyright 2016 Linaro Ltd +- * +- * Permission is hereby granted, free of charge, to any person obtaining a copy +- * of this software and associated documentation files (the "Software"), to deal +- * in the Software without restriction, including without limitation the rights +- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +- * copies of the Software, and to permit persons to whom the Software is +- * furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +- * THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include +-#include +-#include "arm-realview-eb.dtsi" +- +-/ { +- model = "ARM RealView Emulation Baseboard"; +- compatible = "arm,realview-eb"; +- arm,hbi = <0x140>; +- +- /* +- * This is the core tile with the CPU and GIC etc for the +- * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache +- * or PMU. +- * +- * To run this machine with QEMU, specify the following: +- * qemu-system-arm -M realview-eb +- * Unless specified, QEMU will emulate an ARM926EJ-S core tile. +- * Switches -cpu arm1136 or -cpu arm1176 emulates the other +- * core tiles. +- */ +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "arm,realview-eb-soc", "simple-bus"; +- regmap = <&syscon>; +- ranges; +- +- intc: interrupt-controller@10040000 { +- compatible = "arm,pl390"; +- #interrupt-cells = <3>; +- #address-cells = <1>; +- interrupt-controller; +- reg = <0x10041000 0x1000>, +- <0x10040000 0x100>; +- }; +- }; +-}; +- +-/* +- * This adapts all the peripherals to the interrupt routing +- * to the GIC on the core tile. +- */ +- +-ðernet { +- interrupt-parent = <&intc>; +- interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&usb { +- interrupt-parent = <&intc>; +- interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&aaci { +- interrupt-parent = <&intc>; +- interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&mmc { +- interrupt-parent = <&intc>; +- interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, +- <0 18 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&kmi0 { +- interrupt-parent = <&intc>; +- interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&kmi1 { +- interrupt-parent = <&intc>; +- interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&charlcd { +- interrupt-parent = <&intc>; +- interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&serial0 { +- interrupt-parent = <&intc>; +- interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&serial1 { +- interrupt-parent = <&intc>; +- interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&serial2 { +- interrupt-parent = <&intc>; +- interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&serial3 { +- interrupt-parent = <&intc>; +- interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&ssp { +- interrupt-parent = <&intc>; +- interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&wdog { +- interrupt-parent = <&intc>; +- interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&timer01 { +- interrupt-parent = <&intc>; +- interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&timer23 { +- interrupt-parent = <&intc>; +- interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&gpio0 { +- interrupt-parent = <&intc>; +- interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&gpio1 { +- interrupt-parent = <&intc>; +- interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&gpio2 { +- interrupt-parent = <&intc>; +- interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&rtc { +- interrupt-parent = <&intc>; +- interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&clcd { +- interrupt-parent = <&intc>; +- interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/arm-realview-eb.dtsi b/scripts/dtc/include-prefixes/arm/arm-realview-eb.dtsi +deleted file mode 100644 +index 04e8a27ba1eb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/arm-realview-eb.dtsi ++++ /dev/null +@@ -1,468 +0,0 @@ +-/* +- * Copyright 2016 Linaro Ltd +- * +- * Permission is hereby granted, free of charge, to any person obtaining a copy +- * of this software and associated documentation files (the "Software"), to deal +- * in the Software without restriction, including without limitation the rights +- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +- * copies of the Software, and to permit persons to whom the Software is +- * furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +- * THE SOFTWARE. +- */ +- +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "arm,realview-eb"; +- +- chosen { }; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- i2c0 = &i2c; +- }; +- +- memory { +- device_type = "memory"; +- /* 128 MiB memory @ 0x0 */ +- reg = <0x00000000 0x08000000>; +- }; +- +- /* The voltage to the MMC card is hardwired at 3.3V */ +- vmmc: fixedregulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- +- xtal24mhz: xtal24mhz@24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- timclk: timclk@1M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <24>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- mclk: mclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- kmiclk: kmiclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- sspclk: sspclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- uartclk: uartclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- wdogclk: wdogclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- /* FIXME: this actually hangs off the PLL clocks */ +- pclk: pclk@0 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- flash0@40000000 { +- /* 2 * 32MiB NOR Flash memory */ +- compatible = "arm,versatile-flash", "cfi-flash"; +- reg = <0x40000000 0x04000000>; +- bank-width = <4>; +- partitions { +- compatible = "arm,arm-firmware-suite"; +- }; +- }; +- +- flash1@44000000 { +- /* 2 * 32MiB NOR Flash memory */ +- compatible = "arm,versatile-flash", "cfi-flash"; +- reg = <0x44000000 0x04000000>; +- bank-width = <4>; +- partitions { +- compatible = "arm,arm-firmware-suite"; +- }; +- }; +- +- /* SMSC LAN91C111 ethernet with PHY and EEPROM */ +- ethernet: ethernet@4e000000 { +- compatible = "smsc,lan91c111"; +- reg = <0x4e000000 0x10000>; +- /* +- * This means the adapter can be accessed with 8, 16 or +- * 32 bit reads/writes. +- */ +- reg-io-width = <7>; +- }; +- +- usb: usb@4f000000 { +- compatible = "nxp,usb-isp1761"; +- reg = <0x4f000000 0x20000>; +- dr_mode = "peripheral"; +- }; +- +- bridge { +- compatible = "ti,ths8134a", "ti,ths8134"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- vga_bridge_in: endpoint { +- remote-endpoint = <&clcd_pads>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- vga_bridge_out: endpoint { +- remote-endpoint = <&vga_con_in>; +- }; +- }; +- }; +- }; +- +- vga { +- compatible = "vga-connector"; +- +- port { +- vga_con_in: endpoint { +- remote-endpoint = <&vga_bridge_out>; +- }; +- }; +- }; +- +- /* These peripherals are inside the FPGA */ +- fpga { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges; +- +- syscon: syscon@10000000 { +- compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd"; +- reg = <0x10000000 0x1000>; +- +- led@08.0 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x01>; +- label = "versatile:0"; +- linux,default-trigger = "heartbeat"; +- default-state = "on"; +- }; +- led@08.1 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x02>; +- label = "versatile:1"; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- led@08.2 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x04>; +- label = "versatile:2"; +- linux,default-trigger = "cpu0"; +- default-state = "off"; +- }; +- led@08.3 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x08>; +- label = "versatile:3"; +- default-state = "off"; +- }; +- led@08.4 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x10>; +- label = "versatile:4"; +- default-state = "off"; +- }; +- led@08.5 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x20>; +- label = "versatile:5"; +- default-state = "off"; +- }; +- led@08.6 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x40>; +- label = "versatile:6"; +- default-state = "off"; +- }; +- led@08.7 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x80>; +- label = "versatile:7"; +- default-state = "off"; +- }; +- oscclk0: osc0@0c { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x0C>; +- clocks = <&xtal24mhz>; +- }; +- oscclk1: osc1@10 { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x10>; +- clocks = <&xtal24mhz>; +- }; +- oscclk2: osc2@14 { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x14>; +- clocks = <&xtal24mhz>; +- }; +- oscclk3: osc3@18 { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x18>; +- clocks = <&xtal24mhz>; +- }; +- oscclk4: osc4@1c { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x1c>; +- clocks = <&xtal24mhz>; +- }; +- }; +- +- i2c: i2c@10002000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "arm,versatile-i2c"; +- reg = <0x10002000 0x1000>; +- +- rtc@68 { +- compatible = "dallas,ds1338"; +- reg = <0x68>; +- }; +- }; +- +- aaci: aaci@10004000 { +- compatible = "arm,pl041", "arm,primecell"; +- reg = <0x10004000 0x1000>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- mmc: mmcsd@10005000 { +- compatible = "arm,pl18x", "arm,primecell"; +- reg = <0x10005000 0x1000>; +- +- /* Due to frequent FIFO overruns, use just 500 kHz */ +- max-frequency = <500000>; +- bus-width = <4>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- clocks = <&mclk>, <&pclk>; +- clock-names = "mclk", "apb_pclk"; +- vmmc-supply = <&vmmc>; +- cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; +- }; +- +- kmi0: kmi@10006000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x10006000 0x1000>; +- clocks = <&kmiclk>, <&pclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- kmi1: kmi@10007000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x10007000 0x1000>; +- clocks = <&kmiclk>, <&pclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- charlcd: fpga_charlcd: charlcd@10008000 { +- compatible = "arm,versatile-lcd"; +- reg = <0x10008000 0x1000>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- serial0: serial@10009000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x10009000 0x1000>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- serial1: serial@1000a000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x1000a000 0x1000>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- serial2: serial@1000b000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x1000b000 0x1000>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- serial3: serial@1000c000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x1000c000 0x1000>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- ssp: spi@1000d000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x1000d000 0x1000>; +- clocks = <&sspclk>, <&pclk>; +- clock-names = "SSPCLK", "apb_pclk"; +- }; +- +- wdog: watchdog@10010000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x10010000 0x1000>; +- clocks = <&wdogclk>, <&pclk>; +- clock-names = "wdog_clk", "apb_pclk"; +- status = "disabled"; +- }; +- +- timer01: timer@10011000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x10011000 0x1000>; +- clocks = <&timclk>, <&timclk>, <&pclk>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- }; +- +- timer23: timer@10012000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x10012000 0x1000>; +- clocks = <&timclk>, <&timclk>, <&pclk>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- }; +- +- gpio0: gpio@10013000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x10013000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- gpio1: gpio@10014000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x10014000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- gpio2: gpio@10015000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x10015000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- rtc: rtc@10017000 { +- compatible = "arm,pl031", "arm,primecell"; +- reg = <0x10017000 0x1000>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- clcd: clcd@10020000 { +- compatible = "arm,pl111", "arm,primecell"; +- reg = <0x10020000 0x1000>; +- interrupt-names = "combined"; +- clocks = <&oscclk0>, <&pclk>; +- clock-names = "clcdclk", "apb_pclk"; +- /* 1024x768 16bpp @65MHz works fine */ +- max-memory-bandwidth = <95000000>; +- +- port { +- clcd_pads: endpoint { +- remote-endpoint = <&vga_bridge_in>; +- arm,pl11x,tft-r0g0b0-pads = <0 8 16>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/arm-realview-pb1176.dts b/scripts/dtc/include-prefixes/arm/arm-realview-pb1176.dts +deleted file mode 100644 +index 366687fb1ee3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/arm-realview-pb1176.dts ++++ /dev/null +@@ -1,592 +0,0 @@ +-/* +- * Copyright 2014 Linaro Ltd +- * +- * Permission is hereby granted, free of charge, to any person obtaining a copy +- * of this software and associated documentation files (the "Software"), to deal +- * in the Software without restriction, including without limitation the rights +- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +- * copies of the Software, and to permit persons to whom the Software is +- * furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +- * THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "ARM RealView PB1176"; +- compatible = "arm,realview-pb1176"; +- +- chosen { }; +- +- aliases { +- serial0 = &pb1176_serial0; +- serial1 = &pb1176_serial1; +- serial2 = &pb1176_serial2; +- serial3 = &pb1176_serial3; +- serial4 = &fpga_serial; +- }; +- +- memory { +- device_type = "memory"; +- /* 128 MiB memory @ 0x0 */ +- reg = <0x00000000 0x08000000>; +- }; +- +- /* The voltage to the MMC card is hardwired at 3.3V */ +- vmmc: regulator-vmmc { +- compatible = "regulator-fixed"; +- regulator-name = "vmmc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- +- veth: regulator-veth { +- compatible = "regulator-fixed"; +- regulator-name = "veth"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- +- xtal24mhz: xtal24mhz@24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- timclk: timclk@1M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <24>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- mclk: mclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- kmiclk: kmiclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- sspclk: sspclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- uartclk: uartclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- /* FIXME: this actually hangs off the PLL clocks */ +- pclk: pclk@0 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- flash@30000000 { +- compatible = "arm,versatile-flash", "cfi-flash"; +- reg = <0x30000000 0x4000000>; +- bank-width = <4>; +- partitions { +- compatible = "arm,arm-firmware-suite"; +- }; +- }; +- +- fpga_flash@38000000 { +- compatible = "arm,versatile-flash", "cfi-flash"; +- reg = <0x38000000 0x800000>; +- bank-width = <4>; +- partitions { +- compatible = "arm,arm-firmware-suite"; +- }; +- }; +- +- /* +- * The "secure flash" contains things like the boot +- * monitor so we don't want people to accidentally +- * screw this up. Mark the device tree node disabled +- * by default. +- */ +- secflash@3c000000 { +- compatible = "arm,versatile-flash", "cfi-flash"; +- reg = <0x3c000000 0x4000000>; +- bank-width = <4>; +- status = "disabled"; +- }; +- +- /* SMSC 9118 ethernet with PHY and EEPROM */ +- ethernet@3a000000 { +- compatible = "smsc,lan9118", "smsc,lan9115"; +- reg = <0x3a000000 0x10000>; +- interrupt-parent = <&intc_fpga1176>; +- interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; +- phy-mode = "mii"; +- reg-io-width = <4>; +- smsc,irq-active-high; +- smsc,irq-push-pull; +- vdd33a-supply = <&veth>; +- vddvario-supply = <&veth>; +- }; +- +- usb@3b000000 { +- compatible = "nxp,usb-isp1761"; +- reg = <0x3b000000 0x20000>; +- interrupt-parent = <&intc_fpga1176>; +- interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; +- dr_mode = "peripheral"; +- }; +- +- bridge { +- compatible = "ti,ths8134a", "ti,ths8134"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- vga_bridge_in: endpoint { +- remote-endpoint = <&clcd_pads>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- vga_bridge_out: endpoint { +- remote-endpoint = <&vga_con_in>; +- }; +- }; +- }; +- }; +- +- vga { +- compatible = "vga-connector"; +- +- port { +- vga_con_in: endpoint { +- remote-endpoint = <&vga_bridge_out>; +- }; +- }; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "arm,realview-pb1176-soc", "simple-bus"; +- regmap = <&syscon>; +- ranges; +- +- syscon: syscon@10000000 { +- compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd"; +- reg = <0x10000000 0x1000>; +- +- led@08.0 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x01>; +- label = "versatile:0"; +- linux,default-trigger = "heartbeat"; +- default-state = "on"; +- }; +- led@08.1 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x02>; +- label = "versatile:1"; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- led@08.2 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x04>; +- label = "versatile:2"; +- linux,default-trigger = "cpu0"; +- default-state = "off"; +- }; +- led@08.3 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x08>; +- label = "versatile:3"; +- default-state = "off"; +- }; +- led@08.4 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x10>; +- label = "versatile:4"; +- default-state = "off"; +- }; +- led@08.5 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x20>; +- label = "versatile:5"; +- default-state = "off"; +- }; +- led@08.6 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x40>; +- label = "versatile:6"; +- default-state = "off"; +- }; +- led@08.7 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x80>; +- label = "versatile:7"; +- default-state = "off"; +- }; +- oscclk0: osc0@0c { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x0C>; +- clocks = <&xtal24mhz>; +- }; +- oscclk1: osc1@10 { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x10>; +- clocks = <&xtal24mhz>; +- }; +- oscclk2: osc2@14 { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x14>; +- clocks = <&xtal24mhz>; +- }; +- oscclk3: osc3@18 { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x18>; +- clocks = <&xtal24mhz>; +- }; +- oscclk4: osc4@1c { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x1c>; +- clocks = <&xtal24mhz>; +- }; +- }; +- +- /* Primary DevChip GIC synthesized with the CPU */ +- intc_dc1176: interrupt-controller@10120000 { +- compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; +- #interrupt-cells = <3>; +- #address-cells = <1>; +- interrupt-controller; +- reg = <0x10121000 0x1000>, +- <0x10120000 0x100>; +- }; +- +- L2: cache-controller { +- compatible = "arm,l220-cache"; +- reg = <0x10110000 0x1000>; +- interrupt-parent = <&intc_dc1176>; +- interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; +- cache-unified; +- cache-level = <2>; +- /* +- * Override default cache size, sets and +- * associativity as these may be erroneously set +- * up by boot loader(s). +- */ +- arm,override-auxreg; +- cache-size = <131072>; // 128kB +- cache-sets = <512>; +- cache-line-size = <32>; +- }; +- +- pmu { +- compatible = "arm,arm1176-pmu"; +- interrupt-parent = <&intc_dc1176>; +- interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- timer01: timer@10104000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x10104000 0x1000>; +- interrupt-parent = <&intc_dc1176>; +- interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&timclk>, <&timclk>, <&pclk>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- }; +- +- timer23: timer@10105000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x10105000 0x1000>; +- interrupt-parent = <&intc_dc1176>; +- interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; +- arm,sp804-has-irq = <1>; +- clocks = <&timclk>, <&timclk>, <&pclk>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- }; +- +- pb1176_rtc: rtc@10108000 { +- compatible = "arm,pl031", "arm,primecell"; +- reg = <0x10108000 0x1000>; +- interrupt-parent = <&intc_dc1176>; +- interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- pb1176_gpio0: gpio@1010a000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x1010a000 0x1000>; +- gpio-controller; +- interrupt-parent = <&intc_dc1176>; +- interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- pb1176_ssp: spi@1010b000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x1010b000 0x1000>; +- interrupt-parent = <&intc_dc1176>; +- interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&sspclk>, <&pclk>; +- clock-names = "SSPCLK", "apb_pclk"; +- }; +- +- pb1176_serial0: serial@1010c000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x1010c000 0x1000>; +- interrupt-parent = <&intc_dc1176>; +- interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- pb1176_serial1: serial@1010d000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x1010d000 0x1000>; +- interrupt-parent = <&intc_dc1176>; +- interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- pb1176_serial2: serial@1010e000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x1010e000 0x1000>; +- interrupt-parent = <&intc_dc1176>; +- interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- pb1176_serial3: serial@1010f000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x1010f000 0x1000>; +- interrupt-parent = <&intc_dc1176>; +- interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- /* Direct-mapped development chip ROM */ +- pb1176_rom@10200000 { +- compatible = "direct-mapped"; +- reg = <0x10200000 0x4000>; +- bank-width = <1>; +- }; +- +- clcd@10112000 { +- compatible = "arm,pl111", "arm,primecell"; +- reg = <0x10112000 0x1000>; +- interrupt-parent = <&intc_dc1176>; +- interrupt-names = "combined"; +- interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&oscclk0>, <&pclk>; +- clock-names = "clcdclk", "apb_pclk"; +- /* 1024x768 16bpp @65MHz works fine */ +- max-memory-bandwidth = <95000000>; +- +- port { +- clcd_pads: endpoint { +- remote-endpoint = <&vga_bridge_in>; +- arm,pl11x,tft-r0g0b0-pads = <0 8 16>; +- }; +- }; +- }; +- }; +- +- /* These peripherals are inside the FPGA rather than the DevChip */ +- fpga { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges; +- +- i2c0: i2c@10002000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "arm,versatile-i2c"; +- reg = <0x10002000 0x1000>; +- +- rtc@68 { +- compatible = "dallas,ds1338"; +- reg = <0x68>; +- }; +- }; +- +- fpga_aaci: aaci@10004000 { +- compatible = "arm,pl041", "arm,primecell"; +- reg = <0x10004000 0x1000>; +- interrupt-parent = <&intc_fpga1176>; +- interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- fpga_mci: mmcsd@10005000 { +- compatible = "arm,pl18x", "arm,primecell"; +- reg = <0x10005000 0x1000>; +- interrupt-parent = <&intc_fpga1176>; +- interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>, +- <0 2 IRQ_TYPE_LEVEL_HIGH>; +- /* Due to frequent FIFO overruns, use just 500 kHz */ +- max-frequency = <500000>; +- bus-width = <4>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- clocks = <&mclk>, <&pclk>; +- clock-names = "mclk", "apb_pclk"; +- vmmc-supply = <&vmmc>; +- cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>; +- wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>; +- }; +- +- fpga_kmi0: kmi@10006000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x10006000 0x1000>; +- interrupt-parent = <&intc_fpga1176>; +- interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&kmiclk>, <&pclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- fpga_kmi1: kmi@10007000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x10007000 0x1000>; +- interrupt-parent = <&intc_fpga1176>; +- interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&kmiclk>, <&pclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- fpga_charlcd: charlcd@10008000 { +- compatible = "arm,versatile-lcd"; +- reg = <0x10008000 0x1000>; +- interrupt-parent = <&intc_fpga1176>; +- interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- fpga_serial: serial@10009000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x10009000 0x1000>; +- interrupt-parent = <&intc_fpga1176>; +- interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- /* This GIC on the board is cascaded off the DevChip GIC */ +- intc_fpga1176: interrupt-controller@10040000 { +- compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; +- #interrupt-cells = <3>; +- #address-cells = <1>; +- interrupt-controller; +- reg = <0x10041000 0x1000>, +- <0x10040000 0x100>; +- interrupt-parent = <&intc_dc1176>; +- interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- fpga_gpio0: gpio@10014000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x10014000 0x1000>; +- gpio-controller; +- interrupt-parent = <&intc_fpga1176>; +- interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- fpga_gpio1: gpio@10015000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x10015000 0x1000>; +- gpio-controller; +- interrupt-parent = <&intc_fpga1176>; +- interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- fpga_rtc: rtc@10017000 { +- compatible = "arm,pl031", "arm,primecell"; +- reg = <0x10017000 0x1000>; +- interrupt-parent = <&intc_fpga1176>; +- interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/arm-realview-pb11mp.dts b/scripts/dtc/include-prefixes/arm/arm-realview-pb11mp.dts +deleted file mode 100644 +index 228a51a38f95..000000000000 +--- a/scripts/dtc/include-prefixes/arm/arm-realview-pb11mp.dts ++++ /dev/null +@@ -1,718 +0,0 @@ +-/* +- * Copyright 2015 Linaro Ltd +- * +- * Permission is hereby granted, free of charge, to any person obtaining a copy +- * of this software and associated documentation files (the "Software"), to deal +- * in the Software without restriction, including without limitation the rights +- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +- * copies of the Software, and to permit persons to whom the Software is +- * furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +- * THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "ARM RealView PB11MPcore"; +- compatible = "arm,realview-pb11mp"; +- +- chosen { }; +- +- aliases { +- serial0 = &pb11mp_serial0; +- serial1 = &pb11mp_serial1; +- serial2 = &pb11mp_serial2; +- serial3 = &pb11mp_serial3; +- }; +- +- memory { +- device_type = "memory"; +- /* +- * The PB11MPCore has 512 MiB memory @ 0x70000000 +- * and the first 256 are also remapped @ 0x00000000 +- */ +- reg = <0x70000000 0x20000000>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "arm,realview-smp"; +- +- MP11_0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,arm11mpcore"; +- reg = <0>; +- next-level-cache = <&L2>; +- }; +- +- MP11_1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,arm11mpcore"; +- reg = <1>; +- next-level-cache = <&L2>; +- }; +- +- MP11_2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,arm11mpcore"; +- reg = <2>; +- next-level-cache = <&L2>; +- }; +- +- MP11_3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,arm11mpcore"; +- reg = <3>; +- next-level-cache = <&L2>; +- }; +- }; +- +- /* Primary TestChip GIC synthesized with the CPU */ +- intc_tc11mp: interrupt-controller@1f000100 { +- compatible = "arm,tc11mp-gic"; +- #interrupt-cells = <3>; +- #address-cells = <1>; +- interrupt-controller; +- reg = <0x1f001000 0x1000>, +- <0x1f000100 0x100>; +- }; +- +- L2: cache-controller { +- compatible = "arm,l220-cache"; +- reg = <0x1f002000 0x1000>; +- interrupt-parent = <&intc_tc11mp>; +- interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, +- <0 30 IRQ_TYPE_LEVEL_HIGH>, +- <0 31 IRQ_TYPE_LEVEL_HIGH>; +- cache-unified; +- cache-level = <2>; +- /* +- * Override default cache size, sets and +- * associativity as these may be erroneously set +- * up by boot loader(s), probably for safety +- * since th outer sync operation can cause the +- * cache to hang unless disabled. +- */ +- cache-size = <1048576>; // 1MB +- cache-sets = <4096>; +- cache-line-size = <32>; +- arm,shared-override; +- arm,parity-enable; +- arm,outer-sync-disable; +- }; +- +- scu@1f000000 { +- compatible = "arm,arm11mp-scu"; +- reg = <0x1f000000 0x100>; +- }; +- +- timer@1f000600 { +- compatible = "arm,arm11mp-twd-timer"; +- reg = <0x1f000600 0x20>; +- interrupt-parent = <&intc_tc11mp>; +- interrupts = <1 13 0xf04>; +- }; +- +- watchdog@1f000620 { +- compatible = "arm,arm11mp-twd-wdt"; +- reg = <0x1f000620 0x20>; +- interrupt-parent = <&intc_tc11mp>; +- interrupts = <1 14 0xf04>; +- }; +- +- /* PMU with one IRQ line per core */ +- pmu { +- compatible = "arm,arm11mpcore-pmu"; +- interrupt-parent = <&intc_tc11mp>; +- interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, +- <0 18 IRQ_TYPE_LEVEL_HIGH>, +- <0 19 IRQ_TYPE_LEVEL_HIGH>, +- <0 20 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>; +- }; +- +- /* The voltage to the MMC card is hardwired at 3.3V */ +- vmmc: regulator-vmmc { +- compatible = "regulator-fixed"; +- regulator-name = "vmmc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- +- veth: regulator-veth { +- compatible = "regulator-fixed"; +- regulator-name = "veth"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- +- xtal24mhz: xtal24mhz@24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- refclk32khz: refclk32khz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- timclk: timclk@1M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <24>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- mclk: mclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- kmiclk: kmiclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- sspclk: sspclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- uartclk: uartclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- wdogclk: wdogclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- /* FIXME: this actually hangs off the PLL clocks */ +- pclk: pclk@0 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- flash0@40000000 { +- /* 2 * 32MiB NOR Flash memory */ +- compatible = "arm,versatile-flash", "cfi-flash"; +- reg = <0x40000000 0x04000000>; +- bank-width = <4>; +- partitions { +- compatible = "arm,arm-firmware-suite"; +- }; +- }; +- +- flash1@44000000 { +- // 2 * 32MiB NOR Flash memory +- compatible = "arm,versatile-flash", "cfi-flash"; +- reg = <0x44000000 0x04000000>; +- bank-width = <4>; +- partitions { +- compatible = "arm,arm-firmware-suite"; +- }; +- }; +- +- bridge { +- compatible = "ti,ths8134a", "ti,ths8134"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- vga_bridge_in: endpoint { +- remote-endpoint = <&clcd_pads>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- vga_bridge_out: endpoint { +- remote-endpoint = <&vga_con_in>; +- }; +- }; +- }; +- }; +- +- vga { +- /* +- * This DDC I2C is connected directly to the DVI portions +- * of the connector, so it's not really working when the +- * monitor is connected to the VGA connector. +- */ +- compatible = "vga-connector"; +- ddc-i2c-bus = <&i2c1>; +- +- port { +- vga_con_in: endpoint { +- remote-endpoint = <&vga_bridge_out>; +- }; +- }; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "arm,realview-pb11mp-soc", "simple-bus"; +- regmap = <&pb11mp_syscon>; +- ranges; +- +- pb11mp_syscon: syscon@10000000 { +- compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd"; +- reg = <0x10000000 0x1000>; +- +- led@08.0 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x01>; +- label = "versatile:0"; +- linux,default-trigger = "heartbeat"; +- default-state = "on"; +- }; +- led@08.1 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x02>; +- label = "versatile:1"; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- led@08.2 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x04>; +- label = "versatile:2"; +- linux,default-trigger = "cpu0"; +- default-state = "off"; +- }; +- led@08.3 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x08>; +- label = "versatile:3"; +- linux,default-trigger = "cpu1"; +- default-state = "off"; +- }; +- led@08.4 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x10>; +- label = "versatile:4"; +- linux,default-trigger = "cpu2"; +- default-state = "off"; +- }; +- led@08.5 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x20>; +- label = "versatile:5"; +- linux,default-trigger = "cpu3"; +- default-state = "off"; +- }; +- led@08.6 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x40>; +- label = "versatile:6"; +- default-state = "off"; +- }; +- led@08.7 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x80>; +- label = "versatile:7"; +- default-state = "off"; +- }; +- +- oscclk0: osc0@0c { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x0C>; +- clocks = <&xtal24mhz>; +- }; +- oscclk1: osc1@10 { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x10>; +- clocks = <&xtal24mhz>; +- }; +- oscclk2: osc2@14 { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x14>; +- clocks = <&xtal24mhz>; +- }; +- oscclk3: osc3@18 { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x18>; +- clocks = <&xtal24mhz>; +- }; +- oscclk4: osc4@1c { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x1c>; +- clocks = <&xtal24mhz>; +- }; +- oscclk5: osc5@d4 { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0xd4>; +- clocks = <&xtal24mhz>; +- }; +- oscclk6: osc6@d8 { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0xd8>; +- clocks = <&xtal24mhz>; +- }; +- }; +- +- sp810_syscon: sysctl@10001000 { +- compatible = "arm,sp810", "arm,primecell"; +- reg = <0x10001000 0x1000>; +- clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; +- clock-names = "refclk", "timclk", "apb_pclk"; +- #clock-cells = <1>; +- clock-output-names = "timerclk0", +- "timerclk1", +- "timerclk2", +- "timerclk3"; +- assigned-clocks = <&sp810_syscon 0>, +- <&sp810_syscon 1>, +- <&sp810_syscon 2>, +- <&sp810_syscon 3>; +- assigned-clock-parents = <&timclk>, +- <&timclk>, +- <&timclk>, +- <&timclk>; +- }; +- +- i2c0: i2c@10002000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "arm,versatile-i2c"; +- reg = <0x10002000 0x1000>; +- +- rtc@68 { +- compatible = "dallas,ds1338"; +- reg = <0x68>; +- }; +- }; +- +- aaci: aaci@10004000 { +- compatible = "arm,pl041", "arm,primecell"; +- reg = <0x10004000 0x1000>; +- interrupt-parent = <&intc_tc11mp>; +- interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- mci: mmcsd@10005000 { +- compatible = "arm,pl18x", "arm,primecell"; +- reg = <0x10005000 0x1000>; +- interrupt-parent = <&intc_tc11mp>; +- interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>, +- <0 15 IRQ_TYPE_LEVEL_HIGH>; +- /* Due to frequent FIFO overruns, use just 500 kHz */ +- max-frequency = <500000>; +- bus-width = <4>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- clocks = <&mclk>, <&pclk>; +- clock-names = "mclk", "apb_pclk"; +- vmmc-supply = <&vmmc>; +- cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; +- }; +- +- kmi0: kmi@10006000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x10006000 0x1000>; +- interrupt-parent = <&intc_tc11mp>; +- interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&kmiclk>, <&pclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- kmi1: kmi@10007000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x10007000 0x1000>; +- interrupt-parent = <&intc_tc11mp>; +- interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&kmiclk>, <&pclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- pb11mp_serial0: serial@10009000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x10009000 0x1000>; +- interrupt-parent = <&intc_tc11mp>; +- interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- pb11mp_serial1: serial@1000a000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x1000a000 0x1000>; +- interrupt-parent = <&intc_tc11mp>; +- interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- pb11mp_serial2: serial@1000b000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x1000b000 0x1000>; +- interrupt-parent = <&intc_pb11mp>; +- interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- pb11mp_serial3: serial@1000c000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x1000c000 0x1000>; +- interrupt-parent = <&intc_pb11mp>; +- interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- spi@1000d000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x1000d000 0x1000>; +- interrupt-parent = <&intc_pb11mp>; +- interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&sspclk>, <&pclk>; +- clock-names = "SSPCLK", "apb_pclk"; +- }; +- +- watchdog@1000f000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x1000f000 0x1000>; +- interrupt-parent = <&intc_pb11mp>; +- interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&wdogclk>, <&pclk>; +- clock-names = "wdog_clk", "apb_pclk"; +- status = "disabled"; +- }; +- +- watchdog@10010000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x10010000 0x1000>; +- interrupt-parent = <&intc_pb11mp>; +- interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&wdogclk>, <&pclk>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- timer01: timer@10011000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x10011000 0x1000>; +- interrupt-parent = <&intc_tc11mp>; +- interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; +- arm,sp804-has-irq = <1>; +- clocks = <&sp810_syscon 0>, +- <&sp810_syscon 1>, +- <&pclk>; +- clock-names = "timer0clk", +- "timer1clk", +- "apb_pclk"; +- }; +- +- timer23: timer@10012000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x10012000 0x1000>; +- interrupt-parent = <&intc_tc11mp>; +- interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; +- arm,sp804-has-irq = <1>; +- clocks = <&sp810_syscon 2>, +- <&sp810_syscon 3>, +- <&pclk>; +- clock-names = "timer0clk", +- "timer1clk", +- "apb_pclk"; +- }; +- +- gpio0: gpio@10013000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x10013000 0x1000>; +- gpio-controller; +- interrupt-parent = <&intc_pb11mp>; +- interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- gpio1: gpio@10014000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x10014000 0x1000>; +- gpio-controller; +- interrupt-parent = <&intc_pb11mp>; +- interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- gpio2: gpio@10015000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x10015000 0x1000>; +- gpio-controller; +- interrupt-parent = <&intc_pb11mp>; +- interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- i2c1: i2c@10016000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "arm,versatile-i2c"; +- reg = <0x10016000 0x1000>; +- }; +- +- rtc: rtc@10017000 { +- compatible = "arm,pl031", "arm,primecell"; +- reg = <0x10017000 0x1000>; +- interrupt-parent = <&intc_tc11mp>; +- interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- timer45: timer@10018000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x10018000 0x1000>; +- clocks = <&timclk>, <&timclk>, <&pclk>; +- clock-names = "timer0clk", "timer1clk", "apb_pclk"; +- status = "disabled"; +- }; +- +- timer67: timer@10019000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x10019000 0x1000>; +- clocks = <&timclk>, <&timclk>, <&pclk>; +- clock-names = "timer0clk", "timer1clk", "apb_pclk"; +- status = "disabled"; +- }; +- +- +- clcd@10020000 { +- compatible = "arm,pl111", "arm,primecell"; +- reg = <0x10020000 0x1000>; +- interrupt-parent = <&intc_pb11mp>; +- interrupt-names = "combined"; +- interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&oscclk4>, <&pclk>; +- clock-names = "clcdclk", "apb_pclk"; +- /* 1024x768 16bpp @65MHz works fine */ +- max-memory-bandwidth = <95000000>; +- +- port { +- clcd_pads: endpoint { +- remote-endpoint = <&vga_bridge_in>; +- arm,pl11x,tft-r0g0b0-pads = <0 8 16>; +- }; +- }; +- }; +- +- /* +- * This GIC on the Platform Baseboard is cascaded off the +- * TestChip GIC +- */ +- intc_pb11mp: interrupt-controller@1e000000 { +- compatible = "arm,arm11mp-gic"; +- #interrupt-cells = <3>; +- #address-cells = <1>; +- interrupt-controller; +- reg = <0x1e001000 0x1000>, +- <0x1e000000 0x100>; +- interrupt-parent = <&intc_tc11mp>; +- interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- /* SMSC 9118 ethernet with PHY and EEPROM */ +- ethernet@4e000000 { +- compatible = "smsc,lan9118", "smsc,lan9115"; +- reg = <0x4e000000 0x10000>; +- interrupt-parent = <&intc_tc11mp>; +- interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; +- phy-mode = "mii"; +- reg-io-width = <4>; +- smsc,irq-active-high; +- smsc,irq-push-pull; +- vdd33a-supply = <&veth>; +- vddvario-supply = <&veth>; +- }; +- +- usb@4f000000 { +- compatible = "nxp,usb-isp1761"; +- reg = <0x4f000000 0x20000>; +- interrupt-parent = <&intc_tc11mp>; +- interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; +- dr_mode = "peripheral"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/arm-realview-pba8.dts b/scripts/dtc/include-prefixes/arm/arm-realview-pba8.dts +deleted file mode 100644 +index d3238c252b59..000000000000 +--- a/scripts/dtc/include-prefixes/arm/arm-realview-pba8.dts ++++ /dev/null +@@ -1,178 +0,0 @@ +-/* +- * Copyright 2016 Linaro Ltd +- * +- * Permission is hereby granted, free of charge, to any person obtaining a copy +- * of this software and associated documentation files (the "Software"), to deal +- * in the Software without restriction, including without limitation the rights +- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +- * copies of the Software, and to permit persons to whom the Software is +- * furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +- * THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "arm-realview-pbx.dtsi" +- +-/ { +- model = "ARM RealView Platform Baseboard for Cortex-A8"; +- compatible = "arm,realview-pba8"; +- arm,hbi = <0x178>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "arm,realview-smp"; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a8"; +- reg = <0>; +- }; +- }; +- +- pmu: pmu@0 { +- compatible = "arm,cortex-a8-pmu"; +- interrupt-parent = <&intc>; +- interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&cpu0>; +- }; +- +- /* Primary GIC PL390 interrupt controller in the test chip */ +- intc: interrupt-controller@1e000000 { +- compatible = "arm,pl390"; +- #interrupt-cells = <3>; +- #address-cells = <1>; +- interrupt-controller; +- reg = <0x1e001000 0x1000>, +- <0x1e000000 0x100>; +- }; +-}; +- +-ðernet { +- interrupt-parent = <&intc>; +- interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&usb { +- interrupt-parent = <&intc>; +- interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&soc { +- compatible = "arm,realview-pba8-soc", "simple-bus"; +-}; +- +-&syscon { +- compatible = "arm,realview-pba8-syscon", "syscon", "simple-mfd"; +-}; +- +-&serial0 { +- interrupt-parent = <&intc>; +- interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&serial1 { +- interrupt-parent = <&intc>; +- interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&serial2 { +- interrupt-parent = <&intc>; +- interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&serial3 { +- interrupt-parent = <&intc>; +- interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&ssp { +- interrupt-parent = <&intc>; +- interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&wdog0 { +- interrupt-parent = <&intc>; +- interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&wdog1 { +- interrupt-parent = <&intc>; +- interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&timer01 { +- interrupt-parent = <&intc>; +- interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&timer23 { +- interrupt-parent = <&intc>; +- interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&gpio0 { +- interrupt-parent = <&intc>; +- interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&gpio1 { +- interrupt-parent = <&intc>; +- interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&gpio2 { +- interrupt-parent = <&intc>; +- interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&rtc { +- interrupt-parent = <&intc>; +- interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&timer45 { +- interrupt-parent = <&intc>; +- interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&timer67 { +- interrupt-parent = <&intc>; +- interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&aaci { +- interrupt-parent = <&intc>; +- interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&mmc { +- interrupt-parent = <&intc>; +- interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, +- <0 18 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&kmi0 { +- interrupt-parent = <&intc>; +- interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&kmi1 { +- interrupt-parent = <&intc>; +- interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&clcd { +- interrupt-parent = <&intc>; +- interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/arm-realview-pbx-a9.dts b/scripts/dtc/include-prefixes/arm/arm-realview-pbx-a9.dts +deleted file mode 100644 +index 85d3968fbb91..000000000000 +--- a/scripts/dtc/include-prefixes/arm/arm-realview-pbx-a9.dts ++++ /dev/null +@@ -1,228 +0,0 @@ +-/* +- * Copyright 2016 Linaro Ltd +- * +- * Permission is hereby granted, free of charge, to any person obtaining a copy +- * of this software and associated documentation files (the "Software"), to deal +- * in the Software without restriction, including without limitation the rights +- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +- * copies of the Software, and to permit persons to whom the Software is +- * furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +- * THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "arm-realview-pbx.dtsi" +- +-/ { +- /* +- * This is the RealView Platform Baseboard Explore for Cortex-A9 +- * (HBI0182 + HBI0183) as described in ARM DUI 0440B +- */ +- model = "ARM RealView Platform Baseboard Explore for Cortex-A9"; +- arm,hbi = <0x182>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "arm,realview-smp"; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&CPU0>; +- }; +- core1 { +- cpu = <&CPU1>; +- }; +- }; +- }; +- CPU0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0x0>; +- next-level-cache = <&L2>; +- }; +- CPU1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0x1>; +- next-level-cache = <&L2>; +- }; +- }; +- +- L2: cache-controller { +- compatible = "arm,pl310-cache"; +- reg = <0x1f002000 0x1000>; +- cache-unified; +- cache-level = <2>; +- /* +- * Override default cache size, sets and +- * associativity as these may be erroneously set +- * up by boot loader(s). +- */ +- cache-size = <131072>; // 128KB +- cache-sets = <512>; +- cache-line-size = <32>; +- arm,parity-disable; +- arm,tag-latency = <1 1 1>; +- arm,data-latency = <1 1 1>; +- }; +- +- scu: scu@1f000000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0x1f000000 0x100>; +- }; +- +- twd_timer: timer@1f000600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x1f000600 0x20>; +- interrupt-parent = <&intc>; +- interrupts = <1 13 0xf04>; +- }; +- +- twd_wdog: watchdog@1f000620 { +- compatible = "arm,cortex-a9-twd-wdt"; +- reg = <0x1f000620 0x20>; +- interrupt-parent = <&intc>; +- interrupts = <1 14 0xf04>; +- }; +- +- pmu: pmu@0 { +- compatible = "arm,cortex-a9-pmu"; +- interrupt-parent = <&intc>; +- interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>, +- <0 45 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&CPU0>, <&CPU1>; +- }; +- +- /* Primary GIC PL390 interrupt controller in the test chip */ +- intc: interrupt-controller@1f000000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #address-cells = <1>; +- interrupt-controller; +- reg = <0x1f001000 0x1000>, +- <0x1f000100 0x100>; +- }; +-}; +- +-ðernet { +- interrupt-parent = <&intc>; +- interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&usb { +- interrupt-parent = <&intc>; +- interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&serial0 { +- interrupt-parent = <&intc>; +- interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&serial1 { +- interrupt-parent = <&intc>; +- interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&serial2 { +- interrupt-parent = <&intc>; +- interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&serial3 { +- interrupt-parent = <&intc>; +- interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&ssp { +- interrupt-parent = <&intc>; +- interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&wdog0 { +- interrupt-parent = <&intc>; +- interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&wdog1 { +- interrupt-parent = <&intc>; +- interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&timer01 { +- interrupt-parent = <&intc>; +- interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&timer23 { +- interrupt-parent = <&intc>; +- interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&gpio0 { +- interrupt-parent = <&intc>; +- interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&gpio1 { +- interrupt-parent = <&intc>; +- interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&gpio2 { +- interrupt-parent = <&intc>; +- interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&rtc { +- interrupt-parent = <&intc>; +- interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&timer45 { +- interrupt-parent = <&intc>; +- interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&timer67 { +- interrupt-parent = <&intc>; +- interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&aaci { +- interrupt-parent = <&intc>; +- interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&mmc { +- interrupt-parent = <&intc>; +- interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, +- <0 18 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&kmi0 { +- interrupt-parent = <&intc>; +- interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&kmi1 { +- interrupt-parent = <&intc>; +- interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&clcd { +- interrupt-parent = <&intc>; +- interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/arm-realview-pbx.dtsi b/scripts/dtc/include-prefixes/arm/arm-realview-pbx.dtsi +deleted file mode 100644 +index ccf6f756b6ed..000000000000 +--- a/scripts/dtc/include-prefixes/arm/arm-realview-pbx.dtsi ++++ /dev/null +@@ -1,577 +0,0 @@ +-/* +- * Copyright 2016 Linaro Ltd +- * +- * Permission is hereby granted, free of charge, to any person obtaining a copy +- * of this software and associated documentation files (the "Software"), to deal +- * in the Software without restriction, including without limitation the rights +- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +- * copies of the Software, and to permit persons to whom the Software is +- * furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +- * THE SOFTWARE. +- */ +- +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "arm,realview-pbx"; +- +- chosen { }; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- }; +- +- memory { +- device_type = "memory"; +- /* 128 MiB memory @ 0x0 */ +- reg = <0x00000000 0x08000000>; +- }; +- +- /* The voltage to the MMC card is hardwired at 3.3V */ +- vmmc: regulator-vmmc { +- compatible = "regulator-fixed"; +- regulator-name = "vmmc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- +- veth: regulator-veth { +- compatible = "regulator-fixed"; +- regulator-name = "veth"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- +- xtal24mhz: xtal24mhz@24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- refclk32khz: refclk32khz { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- timclk: timclk@1M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <24>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- mclk: mclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- kmiclk: kmiclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- sspclk: sspclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- uartclk: uartclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- wdogclk: wdogclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- /* FIXME: this actually hangs off the PLL clocks */ +- pclk: pclk@0 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- flash0@40000000 { +- /* 2 * 32MiB NOR Flash memory */ +- compatible = "arm,versatile-flash", "cfi-flash"; +- reg = <0x40000000 0x04000000>; +- bank-width = <4>; +- partitions { +- compatible = "arm,arm-firmware-suite"; +- }; +- }; +- +- flash1@44000000 { +- /* 2 * 32MiB NOR Flash memory */ +- compatible = "arm,versatile-flash", "cfi-flash"; +- reg = <0x44000000 0x04000000>; +- bank-width = <4>; +- partitions { +- compatible = "arm,arm-firmware-suite"; +- }; +- }; +- +- /* SMSC 9118 ethernet with PHY and EEPROM */ +- ethernet: ethernet@4e000000 { +- compatible = "smsc,lan9118", "smsc,lan9115"; +- reg = <0x4e000000 0x10000>; +- phy-mode = "mii"; +- reg-io-width = <4>; +- smsc,irq-active-high; +- smsc,irq-push-pull; +- vdd33a-supply = <&veth>; +- vddvario-supply = <&veth>; +- }; +- +- usb: usb@4f000000 { +- compatible = "nxp,usb-isp1761"; +- reg = <0x4f000000 0x20000>; +- dr_mode = "peripheral"; +- }; +- +- bridge { +- compatible = "ti,ths8134a", "ti,ths8134"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- vga_bridge_in: endpoint { +- remote-endpoint = <&clcd_pads>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- vga_bridge_out: endpoint { +- remote-endpoint = <&vga_con_in>; +- }; +- }; +- }; +- }; +- +- vga { +- /* +- * This DDC I2C is connected directly to the DVI portions +- * of the connector, so it's not really working when the +- * monitor is connected to the VGA connector. +- */ +- compatible = "vga-connector"; +- ddc-i2c-bus = <&i2c1>; +- +- port { +- vga_con_in: endpoint { +- remote-endpoint = <&vga_bridge_out>; +- }; +- }; +- }; +- +- soc: soc { +- compatible = "arm,realview-pbx-soc", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- regmap = <&syscon>; +- ranges; +- +- syscon: syscon@10000000 { +- compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd"; +- reg = <0x10000000 0x1000>; +- +- led@08.0 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x01>; +- label = "versatile:0"; +- linux,default-trigger = "heartbeat"; +- default-state = "on"; +- }; +- led@08.1 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x02>; +- label = "versatile:1"; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- led@08.2 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x04>; +- label = "versatile:2"; +- linux,default-trigger = "cpu0"; +- default-state = "off"; +- }; +- led@08.3 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x08>; +- label = "versatile:3"; +- default-state = "off"; +- }; +- led@08.4 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x10>; +- label = "versatile:4"; +- default-state = "off"; +- }; +- led@08.5 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x20>; +- label = "versatile:5"; +- default-state = "off"; +- }; +- led@08.6 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x40>; +- label = "versatile:6"; +- default-state = "off"; +- }; +- led@08.7 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x80>; +- label = "versatile:7"; +- default-state = "off"; +- }; +- oscclk0: osc0@0c { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x0C>; +- clocks = <&xtal24mhz>; +- }; +- oscclk1: osc1@10 { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x10>; +- clocks = <&xtal24mhz>; +- }; +- oscclk2: osc2@14 { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x14>; +- clocks = <&xtal24mhz>; +- }; +- oscclk3: osc3@18 { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x18>; +- clocks = <&xtal24mhz>; +- }; +- oscclk4: osc4@1c { +- compatible = "arm,syscon-icst307"; +- #clock-cells = <0>; +- lock-offset = <0x20>; +- vco-offset = <0x1c>; +- clocks = <&xtal24mhz>; +- }; +- }; +- +- sp810_syscon0: sysctl@10001000 { +- compatible = "arm,sp810", "arm,primecell"; +- reg = <0x10001000 0x1000>; +- clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; +- clock-names = "refclk", "timclk", "apb_pclk"; +- #clock-cells = <1>; +- clock-output-names = "timerclk0", +- "timerclk1", +- "timerclk2", +- "timerclk3"; +- assigned-clocks = <&sp810_syscon0 0>, +- <&sp810_syscon0 1>, +- <&sp810_syscon0 2>, +- <&sp810_syscon0 3>; +- assigned-clock-parents = <&timclk>, +- <&timclk>, +- <&timclk>, +- <&timclk>; +- }; +- +- i2c0: i2c@10002000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "arm,versatile-i2c"; +- reg = <0x10002000 0x1000>; +- +- rtc@68 { +- compatible = "dallas,ds1338"; +- reg = <0x68>; +- }; +- }; +- +- serial0: serial@10009000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x10009000 0x1000>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- serial1: serial@1000a000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x1000a000 0x1000>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- serial2: serial@1000b000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x1000b000 0x1000>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- ssp: spi@1000d000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x1000d000 0x1000>; +- clocks = <&sspclk>, <&pclk>; +- clock-names = "SSPCLK", "apb_pclk"; +- }; +- +- wdog0: watchdog@1000f000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x1000f000 0x1000>; +- clocks = <&wdogclk>, <&pclk>; +- clock-names = "wdog_clk", "apb_pclk"; +- status = "disabled"; +- }; +- +- wdog1: watchdog@10010000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x10010000 0x1000>; +- clocks = <&wdogclk>, <&pclk>; +- clock-names = "wdog_clk", "apb_pclk"; +- status = "disabled"; +- }; +- +- timer01: timer@10011000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x10011000 0x1000>; +- clocks = <&sp810_syscon0 0>, +- <&sp810_syscon0 1>, +- <&pclk>; +- clock-names = "timerclk0", +- "timerclk1", +- "apb_pclk"; +- }; +- +- timer23: timer@10012000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x10012000 0x1000>; +- clocks = <&sp810_syscon0 2>, +- <&sp810_syscon0 3>, +- <&pclk>; +- clock-names = "timerclk2", +- "timerclk3", +- "apb_pclk"; +- }; +- +- gpio0: gpio@10013000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x10013000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- gpio1: gpio@10014000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x10014000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- gpio2: gpio@10015000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x10015000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- i2c1: i2c@10016000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "arm,versatile-i2c"; +- reg = <0x10016000 0x1000>; +- }; +- +- rtc: rtc@10017000 { +- compatible = "arm,pl031", "arm,primecell"; +- reg = <0x10017000 0x1000>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- timer45: timer@10018000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x10018000 0x1000>; +- clocks = <&timclk>, <&timclk>, <&pclk>; +- clock-names = "timerclk4", "timerclk5", "apb_pclk"; +- }; +- +- timer67: timer@10019000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x10019000 0x1000>; +- clocks = <&timclk>, <&timclk>, <&pclk>; +- clock-names = "timerclk6", "timerclk7", "apb_pclk"; +- }; +- +- sp810_syscon1: sysctl@1001a000 { +- compatible = "arm,sp810", "arm,primecell"; +- reg = <0x1001a000 0x1000>; +- clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; +- clock-names = "refclk", "timclk", "apb_pclk"; +- #clock-cells = <1>; +- clock-output-names = "timerclk4", +- "timerclk5", +- "timerclk6", +- "timerclk7"; +- assigned-clocks = <&sp810_syscon1 0>, +- <&sp810_syscon1 1>, +- <&sp810_syscon1 2>, +- <&sp810_syscon1 3>; +- assigned-clock-parents = <&timclk>, +- <&timclk>, +- <&timclk>, +- <&timclk>; +- }; +- }; +- +- +- /* These peripherals are inside the FPGA */ +- fpga { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges; +- +- aaci: aaci@10004000 { +- compatible = "arm,pl041", "arm,primecell"; +- reg = <0x10004000 0x1000>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- mmc: mmcsd@10005000 { +- compatible = "arm,pl18x", "arm,primecell"; +- reg = <0x10005000 0x1000>; +- +- /* Due to frequent FIFO overruns, use just 500 kHz */ +- max-frequency = <500000>; +- bus-width = <4>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- clocks = <&mclk>, <&pclk>; +- clock-names = "mclk", "apb_pclk"; +- vmmc-supply = <&vmmc>; +- cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; +- }; +- +- kmi0: kmi@10006000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x10006000 0x1000>; +- clocks = <&kmiclk>, <&pclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- kmi1: kmi@10007000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x10007000 0x1000>; +- clocks = <&kmiclk>, <&pclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- serial3: serial@1000c000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x1000c000 0x1000>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- }; +- +- /* These peripherals are inside the NEC ISSP */ +- issp { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges; +- +- clcd: clcd@10020000 { +- compatible = "arm,pl111", "arm,primecell"; +- reg = <0x10020000 0x1000>; +- interrupt-names = "combined"; +- clocks = <&oscclk4>, <&pclk>; +- clock-names = "clcdclk", "apb_pclk"; +- /* 1024x768 16bpp @65MHz works fine */ +- max-memory-bandwidth = <95000000>; +- +- port { +- clcd_pads: endpoint { +- remote-endpoint = <&vga_bridge_in>; +- arm,pl11x,tft-r0g0b0-pads = <0 8 16>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-370-db.dts b/scripts/dtc/include-prefixes/arm/armada-370-db.dts +deleted file mode 100644 +index 77261a2fb949..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-370-db.dts ++++ /dev/null +@@ -1,244 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Marvell Armada 370 evaluation board +- * (DB-88F6710-BP-DDR3) +- * +- * Copyright (C) 2012 Marvell +- * +- * Lior Amsalem +- * Gregory CLEMENT +- * Thomas Petazzoni +- * +- * Note: this Device Tree assumes that the bootloader has remapped the +- * internal registers to 0xf1000000 (instead of the default +- * 0xd0000000). The 0xf1000000 is the default used by the recent, +- * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier +- * boards were delivered with an older version of the bootloader that +- * left internal registers mapped at 0xd0000000. If you are in this +- * situation, you should either update your bootloader (preferred +- * solution) or the below Device Tree should be adjusted. +- */ +- +-/dts-v1/; +-#include "armada-370.dtsi" +- +-/ { +- model = "Marvell Armada 370 Evaluation Board"; +- compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x40000000>; /* 1 GB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- serial@12000 { +- status = "okay"; +- }; +- sata@a0000 { +- nr-ports = <2>; +- status = "okay"; +- }; +- +- ethernet@70000 { +- pinctrl-0 = <&ge0_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +- }; +- ethernet@74000 { +- pinctrl-0 = <&ge1_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy = <&phy1>; +- phy-mode = "rgmii-id"; +- }; +- +- i2c@11000 { +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +- clock-frequency = <100000>; +- status = "okay"; +- audio_codec: audio-codec@4a { +- #sound-dai-cells = <0>; +- compatible = "cirrus,cs42l51"; +- reg = <0x4a>; +- }; +- }; +- +- audio-controller@30000 { +- pinctrl-0 = <&i2s_pins2>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- +- mvsdio@d4000 { +- pinctrl-0 = <&sdio_pins1>; +- pinctrl-names = "default"; +- /* +- * This device is disabled by default, because +- * using the SD card connector requires +- * changing the default CON40 connector +- * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a +- * different connector +- * "DB-88F6710_MPP_RGMII_SD_Jumper". +- */ +- status = "disabled"; +- /* No CD or WP GPIOs */ +- broken-cd; +- }; +- +- usb@50000 { +- status = "okay"; +- }; +- +- usb@51000 { +- status = "okay"; +- }; +- }; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "Armada 370 DB Audio"; +- simple-audio-card,mclk-fs = <256>; +- simple-audio-card,widgets = +- "Headphone", "Out Jack", +- "Line", "In Jack"; +- simple-audio-card,routing = +- "Out Jack", "HPL", +- "Out Jack", "HPR", +- "AIN1L", "In Jack", +- "AIN1L", "In Jack"; +- status = "okay"; +- +- simple-audio-card,dai-link@0 { +- format = "i2s"; +- cpu { +- sound-dai = <&audio_controller 0>; +- }; +- +- codec { +- sound-dai = <&audio_codec>; +- }; +- }; +- +- simple-audio-card,dai-link@1 { +- format = "i2s"; +- cpu { +- sound-dai = <&audio_controller 1>; +- }; +- +- codec { +- sound-dai = <&spdif_out>; +- }; +- }; +- +- simple-audio-card,dai-link@2 { +- format = "i2s"; +- cpu { +- sound-dai = <&audio_controller 1>; +- }; +- +- codec { +- sound-dai = <&spdif_in>; +- }; +- }; +- }; +- +- spdif_out: spdif-out { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- }; +- +- spdif_in: spdif-in { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dir"; +- }; +-}; +- +-&pciec { +- status = "okay"; +- /* +- * The two PCIe units are accessible through +- * both standard PCIe slots and mini-PCIe +- * slots on the board. +- */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- +- pcie@2,0 { +- /* Port 1, Lane 0 */ +- status = "okay"; +- }; +-}; +- +-&mdio { +- pinctrl-0 = <&mdio_pins>; +- pinctrl-names = "default"; +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +- +-&spi0 { +- pinctrl-0 = <&spi0_pins2>; +- pinctrl-names = "default"; +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mx25l25635e", "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <50000000>; +- }; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- marvell,nand-keep-config; +- nand-on-flash-bbt; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0 0x800000>; +- }; +- partition@800000 { +- label = "Linux"; +- reg = <0x800000 0x800000>; +- }; +- partition@1000000 { +- label = "Filesystem"; +- reg = <0x1000000 0x3f000000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-370-dlink-dns327l.dts b/scripts/dtc/include-prefixes/arm/armada-370-dlink-dns327l.dts +deleted file mode 100644 +index 2008c6eaaa52..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-370-dlink-dns327l.dts ++++ /dev/null +@@ -1,330 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for D-Link DNS-327L +- * +- * Copyright (C) 2015, Andrew Andrianov +- */ +- +-/* Remaining unsolved: +- * There's still some unknown device on i2c address 0x13 +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "armada-370.dtsi" +- +-/ { +- model = "D-Link DNS-327L"; +- compatible = "dlink,dns327l", +- "marvell,armada370", +- "marvell,armada-370-xp"; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; /* 512 MiB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- sata@a0000 { +- nr-ports = <2>; +- status = "okay"; +- }; +- +- usb@50000 { +- status = "okay"; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = < +- &backup_button_pin +- &power_button_pin +- &reset_button_pin>; +- pinctrl-names = "default"; +- +- power-button { +- label = "Power Button"; +- linux,code = ; +- gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +- }; +- +- backup-button { +- label = "Backup Button"; +- linux,code = ; +- gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; +- }; +- +- reset-button { +- label = "Reset Button"; +- linux,code = ; +- gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = < +- &sata_l_amber_pin +- &sata_r_amber_pin +- &backup_led_pin +- /* Ensure these are managed by hardware */ +- &sata_l_white_pin +- &sata_r_white_pin>; +- +- pinctrl-names = "default"; +- +- sata-r-amber-pin { +- label = "dns327l:amber:sata-r"; +- gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; +- }; +- +- sata-l-amber-pin { +- label = "dns327l:amber:sata-l"; +- gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; +- }; +- +- backup-led-pin { +- label = "dns327l:white:usb"; +- gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- usb_power: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- pinctrl-0 = <&xhci_pwr_pin>; +- pinctrl-names = "default"; +- regulator-name = "USB3.0 Port Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-boot-on; +- regulator-always-on; +- gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; +- }; +- +- sata_r_power: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- pinctrl-0 = <&sata_r_pwr_pin>; +- pinctrl-names = "default"; +- regulator-name = "SATA-R Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- startup-delay-us = <2000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; +- }; +- +- sata_l_power: regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- pinctrl-0 = <&sata_l_pwr_pin>; +- pinctrl-names = "default"; +- regulator-name = "SATA-L Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- startup-delay-us = <4000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&pciec { +- status = "okay"; +- +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- +- pcie@2,0 { +- /* Port 1, Lane 0 */ +- status = "okay"; +- }; +-}; +- +-&pinctrl { +- sata_l_white_pin: sata-l-white-pin { +- marvell,pins = "mpp57"; +- marvell,function = "sata0"; +- }; +- +- sata_r_white_pin: sata-r-white-pin { +- marvell,pins = "mpp55"; +- marvell,function = "sata1"; +- }; +- +- sata_r_amber_pin: sata-r-amber-pin { +- marvell,pins = "mpp52"; +- marvell,function = "gpio"; +- }; +- +- sata_l_amber_pin: sata-l-amber-pin { +- marvell,pins = "mpp53"; +- marvell,function = "gpio"; +- }; +- +- backup_led_pin: backup-led-pin { +- marvell,pins = "mpp61"; +- marvell,function = "gpo"; +- }; +- +- xhci_pwr_pin: xhci-pwr-pin { +- marvell,pins = "mpp13"; +- marvell,function = "gpio"; +- }; +- +- sata_r_pwr_pin: sata-r-pwr-pin { +- marvell,pins = "mpp54"; +- marvell,function = "gpio"; +- }; +- +- sata_l_pwr_pin: sata-l-pwr-pin { +- marvell,pins = "mpp56"; +- marvell,function = "gpio"; +- }; +- +- uart1_pins: uart1-pins { +- marvell,pins = "mpp60", "mpp61"; +- marvell,function = "uart1"; +- }; +- +- power_button_pin: power-button-pin { +- marvell,pins = "mpp65"; +- marvell,function = "gpio"; +- }; +- +- backup_button_pin: backup-button-pin { +- marvell,pins = "mpp63"; +- marvell,function = "gpio"; +- }; +- +- reset_button_pin: reset-button-pin { +- marvell,pins = "mpp64"; +- marvell,function = "gpio"; +- }; +-}; +- +-/* Serial console */ +-&uart0 { +- status = "okay"; +-}; +- +-/* Connected to Weltrend MCU */ +-&uart1 { +- pinctrl-0 = <&uart1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&mdio { +- phy0: ethernet-phy@0 { /* Marvell 88E1318 */ +- reg = <0>; +- marvell,reg-init = <0x2 0x19 0x0 0x0077>, +- <0x2 0x18 0x0 0x5747>; +- }; +-}; +- +-ð1 { +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&i2c0 { +- compatible = "marvell,mv64xxx-i2c"; +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- marvell,nand-keep-config; +- nand-on-flash-bbt; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- /* 1.0 MiB */ +- reg = <0x0000000 0x100000>; +- read-only; +- }; +- +- partition@100000 { +- label = "u-boot-env"; +- /* 128 KiB */ +- reg = <0x100000 0x20000>; +- read-only; +- }; +- +- partition@120000 { +- label = "uImage"; +- /* 7 MiB */ +- reg = <0x120000 0x700000>; +- }; +- +- partition@820000 { +- label = "ubifs"; +- /* ~ 84 MiB */ +- reg = <0x820000 0x54e0000>; +- }; +- +- /* Hardcoded into stock bootloader */ +- partition@5d00000 { +- label = "failsafe-uImage"; +- /* 5 MiB */ +- reg = <0x5d00000 0x500000>; +- }; +- +- partition@6200000 { +- label = "failsafe-fs"; +- /* 29 MiB */ +- reg = <0x6200000 0x1d00000>; +- }; +- +- partition@7f00000 { +- label = "bbt"; +- /* 1 MiB for BBT */ +- reg = <0x7f00000 0x100000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-370-mirabox.dts b/scripts/dtc/include-prefixes/arm/armada-370-mirabox.dts +deleted file mode 100644 +index 7c2f5a79b50d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-370-mirabox.dts ++++ /dev/null +@@ -1,184 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Globalscale Mirabox +- * +- * Gregory CLEMENT +- */ +- +-/dts-v1/; +-#include +-#include "armada-370.dtsi" +- +-/ { +- model = "Globalscale Mirabox"; +- compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; /* 512 MB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- serial@12000 { +- status = "okay"; +- }; +- timer@20300 { +- clock-frequency = <600000000>; +- status = "okay"; +- }; +- +- gpio_leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_led_pin &stat_led_pins>; +- +- green_pwr_led { +- label = "mirabox:green:pwr"; +- gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- +- blue_stat_led { +- label = "mirabox:blue:stat"; +- gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- green_stat_led { +- label = "mirabox:green:stat"; +- gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- ethernet@70000 { +- pinctrl-0 = <&ge0_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +- }; +- ethernet@74000 { +- pinctrl-0 = <&ge1_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy = <&phy1>; +- phy-mode = "rgmii-id"; +- }; +- +- crypto@90000 { +- status = "okay"; +- }; +- +- mvsdio@d4000 { +- pinctrl-0 = <&sdio_pins3>; +- pinctrl-names = "default"; +- status = "okay"; +- /* +- * No CD or WP GPIOs: SDIO interface used for +- * Wifi/Bluetooth chip +- */ +- broken-cd; +- }; +- +- usb@50000 { +- status = "okay"; +- }; +- +- usb@51000 { +- status = "okay"; +- }; +- +- i2c@11000 { +- status = "okay"; +- clock-frequency = <100000>; +- pca9505: pca9505@25 { +- compatible = "nxp,pca9505"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x25>; +- }; +- }; +- }; +- }; +-}; +- +-&pciec { +- status = "okay"; +- +- /* Internal mini-PCIe connector */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- +- /* Connected on the PCB to a USB 3.0 XHCI controller */ +- pcie@2,0 { +- /* Port 1, Lane 0 */ +- status = "okay"; +- }; +-}; +- +-&mdio { +- pinctrl-0 = <&mdio_pins>; +- pinctrl-names = "default"; +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&pinctrl { +- pwr_led_pin: pwr-led-pin { +- marvell,pins = "mpp63"; +- marvell,function = "gpio"; +- }; +- +- stat_led_pins: stat-led-pins { +- marvell,pins = "mpp64", "mpp65"; +- marvell,function = "gpio"; +- }; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- marvell,nand-keep-config; +- nand-on-flash-bbt; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0 0x400000>; +- }; +- partition@400000 { +- label = "Linux"; +- reg = <0x400000 0x400000>; +- }; +- partition@800000 { +- label = "Filesystem"; +- reg = <0x800000 0x3f800000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-370-netgear-rn102.dts b/scripts/dtc/include-prefixes/arm/armada-370-netgear-rn102.dts +deleted file mode 100644 +index b0b640b7de40..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-370-netgear-rn102.dts ++++ /dev/null +@@ -1,276 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for NETGEAR ReadyNAS 102 +- * +- * Copyright (C) 2013, Arnaud EBALARD +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "armada-370.dtsi" +- +-/ { +- model = "NETGEAR ReadyNAS 102"; +- compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; /* 512 MB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- +- /* RTC is provided by Intersil ISL12057 I2C RTC chip */ +- rtc@10300 { +- status = "disabled"; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- /* eSATA interface */ +- sata@a0000 { +- nr-ports = <1>; +- status = "okay"; +- }; +- +- ethernet@74000 { +- pinctrl-0 = <&ge1_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +- }; +- +- usb@50000 { +- status = "okay"; +- }; +- +- i2c@11000 { +- clock-frequency = <100000>; +- +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- isl12057: rtc@68 { +- compatible = "isil,isl12057"; +- reg = <0x68>; +- wakeup-source; +- }; +- +- g762: g762@3e { +- compatible = "gmt,g762"; +- reg = <0x3e>; +- clocks = <&g762_clk>; /* input clock */ +- fan_gear_mode = <0>; +- fan_startv = <1>; +- pwm_polarity = <0>; +- }; +- }; +- }; +- }; +- +- clocks { +- g762_clk: g762-oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <8192>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&power_led_pin +- &sata1_led_pin +- &sata2_led_pin +- &backup_led_pin>; +- pinctrl-names = "default"; +- +- blue-power-led { +- label = "rn102:blue:pwr"; +- gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- +- blue-sata1-led { +- label = "rn102:blue:sata1"; +- gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- +- blue-sata2-led { +- label = "rn102:blue:sata2"; +- gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- +- blue-backup-led { +- label = "rn102:blue:backup"; +- gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&power_button_pin +- &reset_button_pin +- &backup_button_pin>; +- pinctrl-names = "default"; +- +- power-button { +- label = "Power Button"; +- linux,code = ; +- gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; +- }; +- +- reset-button { +- label = "Reset Button"; +- linux,code = ; +- gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +- }; +- +- backup-button { +- label = "Backup Button"; +- linux,code = ; +- gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- pinctrl-0 = <&poweroff>; +- pinctrl-names = "default"; +- gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&pciec { +- status = "okay"; +- +- /* Connected to Marvell 88SE9170 SATA controller */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- +- /* Connected to FL1009 USB 3.0 controller */ +- pcie@2,0 { +- /* Port 1, Lane 0 */ +- status = "okay"; +- }; +-}; +- +-&mdio { +- pinctrl-0 = <&mdio_pins>; +- pinctrl-names = "default"; +- phy0: ethernet-phy@0 { /* Marvell 88E1318 */ +- reg = <0>; +- }; +-}; +- +-&pinctrl { +- power_led_pin: power-led-pin { +- marvell,pins = "mpp57"; +- marvell,function = "gpio"; +- }; +- +- sata1_led_pin: sata1-led-pin { +- marvell,pins = "mpp15"; +- marvell,function = "gpio"; +- }; +- +- sata2_led_pin: sata2-led-pin { +- marvell,pins = "mpp14"; +- marvell,function = "gpio"; +- }; +- +- backup_led_pin: backup-led-pin { +- marvell,pins = "mpp56"; +- marvell,function = "gpio"; +- }; +- +- backup_button_pin: backup-button-pin { +- marvell,pins = "mpp58"; +- marvell,function = "gpio"; +- }; +- +- power_button_pin: power-button-pin { +- marvell,pins = "mpp62"; +- marvell,function = "gpio"; +- }; +- +- reset_button_pin: reset-button-pin { +- marvell,pins = "mpp6"; +- marvell,function = "gpio"; +- }; +- +- poweroff: poweroff { +- marvell,pins = "mpp8"; +- marvell,function = "gpio"; +- }; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- marvell,nand-keep-config; +- nand-on-flash-bbt; +- +- /* Use Hardware BCH ECC */ +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x180000>; /* 1.5MB */ +- read-only; +- }; +- +- partition@180000 { +- label = "u-boot-env"; +- reg = <0x180000 0x20000>; /* 128KB */ +- read-only; +- }; +- +- partition@200000 { +- label = "uImage"; +- reg = <0x0200000 0x600000>; /* 6MB */ +- }; +- +- partition@800000 { +- label = "minirootfs"; +- reg = <0x0800000 0x400000>; /* 4MB */ +- }; +- +- /* Last MB is for the BBT, i.e. not writable */ +- partition@c00000 { +- label = "ubifs"; +- reg = <0x0c00000 0x7400000>; /* 116MB */ +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-370-netgear-rn104.dts b/scripts/dtc/include-prefixes/arm/armada-370-netgear-rn104.dts +deleted file mode 100644 +index 85e2e9e27a9f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-370-netgear-rn104.dts ++++ /dev/null +@@ -1,302 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for NETGEAR ReadyNAS 104 +- * +- * Copyright (C) 2013, Arnaud EBALARD +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "armada-370.dtsi" +- +-/ { +- model = "NETGEAR ReadyNAS 104"; +- compatible = "netgear,readynas-104", "marvell,armada370", "marvell,armada-370-xp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; /* 512 MB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- +- /* RTC is provided by Intersil ISL12057 I2C RTC chip */ +- rtc@10300 { +- status = "disabled"; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- ethernet@70000 { +- pinctrl-0 = <&ge0_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +- }; +- +- ethernet@74000 { +- pinctrl-0 = <&ge1_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy = <&phy1>; +- phy-mode = "rgmii-id"; +- }; +- +- usb@50000 { +- status = "okay"; +- }; +- +- i2c@11000 { +- clock-frequency = <100000>; +- +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- isl12057: rtc@68 { +- compatible = "isil,isl12057"; +- reg = <0x68>; +- wakeup-source; +- }; +- +- g762: g762@3e { +- compatible = "gmt,g762"; +- reg = <0x3e>; +- clocks = <&g762_clk>; /* input clock */ +- fan_gear_mode = <0>; +- fan_startv = <1>; +- pwm_polarity = <0>; +- }; +- +- pca9554: pca9554@23 { +- compatible = "nxp,pca9554"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x23>; +- }; +- }; +- }; +- }; +- +- clocks { +- g762_clk: g762-oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <8192>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&backup_led_pin &power_led_pin>; +- pinctrl-names = "default"; +- +- blue-backup-led { +- label = "rn104:blue:backup"; +- gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- blue-power-led { +- label = "rn104:blue:pwr"; +- gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "keep"; +- }; +- +- blue-sata1-led { +- label = "rn104:blue:sata1"; +- gpios = <&pca9554 0 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- blue-sata2-led { +- label = "rn104:blue:sata2"; +- gpios = <&pca9554 1 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- blue-sata3-led { +- label = "rn104:blue:sata3"; +- gpios = <&pca9554 2 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- blue-sata4-led { +- label = "rn104:blue:sata4"; +- gpios = <&pca9554 3 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- auxdisplay { +- compatible = "hit,hd44780"; +- data-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>, +- <&gpio1 26 GPIO_ACTIVE_HIGH>, +- <&gpio1 27 GPIO_ACTIVE_HIGH>, +- <&gpio1 29 GPIO_ACTIVE_HIGH>; +- enable-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; +- rs-gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; +- rw-gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; +- backlight-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; +- display-height-chars = <2>; +- display-width-chars = <16>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&backup_button_pin +- &power_button_pin +- &reset_button_pin>; +- pinctrl-names = "default"; +- +- backup-button { +- label = "Backup Button"; +- linux,code = ; +- gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; +- }; +- +- power-button { +- label = "Power Button"; +- linux,code = ; +- gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; +- }; +- +- reset-button { +- label = "Reset Button"; +- linux,code = ; +- gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- pinctrl-0 = <&poweroff>; +- pinctrl-names = "default"; +- gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&pciec { +- status = "okay"; +- +- /* Connected to FL1009 USB 3.0 controller */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- +- /* Connected to Marvell 88SE9215 SATA controller */ +- pcie@2,0 { +- /* Port 1, Lane 0 */ +- status = "okay"; +- }; +-}; +- +-&mdio { +- pinctrl-0 = <&mdio_pins>; +- pinctrl-names = "default"; +- phy0: ethernet-phy@0 { /* Marvell 88E1318 */ +- reg = <0>; +- }; +- +- phy1: ethernet-phy@1 { /* Marvell 88E1318 */ +- reg = <1>; +- }; +-}; +- +-&pinctrl { +- poweroff: poweroff { +- marvell,pins = "mpp60"; +- marvell,function = "gpio"; +- }; +- +- backup_button_pin: backup-button-pin { +- marvell,pins = "mpp52"; +- marvell,function = "gpio"; +- }; +- +- power_button_pin: power-button-pin { +- marvell,pins = "mpp62"; +- marvell,function = "gpio"; +- }; +- +- backup_led_pin: backup-led-pin { +- marvell,pins = "mpp63"; +- marvell,function = "gpio"; +- }; +- +- power_led_pin: power-led-pin { +- marvell,pins = "mpp64"; +- marvell,function = "gpio"; +- }; +- +- reset_button_pin: reset-button-pin { +- marvell,pins = "mpp65"; +- marvell,function = "gpio"; +- }; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- marvell,nand-keep-config; +- nand-on-flash-bbt; +- +- /* Use Hardware BCH ECC */ +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x180000>; /* 1.5MB */ +- read-only; +- }; +- +- partition@180000 { +- label = "u-boot-env"; +- reg = <0x180000 0x20000>; /* 128KB */ +- read-only; +- }; +- +- partition@200000 { +- label = "uImage"; +- reg = <0x0200000 0x600000>; /* 6MB */ +- }; +- +- partition@800000 { +- label = "minirootfs"; +- reg = <0x0800000 0x400000>; /* 4MB */ +- }; +- +- /* Last MB is for the BBT, i.e. not writable */ +- partition@c00000 { +- label = "ubifs"; +- reg = <0x0c00000 0x7400000>; /* 116MB */ +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-370-rd.dts b/scripts/dtc/include-prefixes/arm/armada-370-rd.dts +deleted file mode 100644 +index c910d157a686..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-370-rd.dts ++++ /dev/null +@@ -1,258 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Marvell Armada 370 Reference Design board +- * (RD-88F6710-A1) +- * +- * Copied from arch/arm/boot/dts/armada-370-db.dts +- * +- * Copyright (C) 2013 Florian Fainelli +- * +- * Note: this Device Tree assumes that the bootloader has remapped the +- * internal registers to 0xf1000000 (instead of the default +- * 0xd0000000). The 0xf1000000 is the default used by the recent, +- * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier +- * boards were delivered with an older version of the bootloader that +- * left internal registers mapped at 0xd0000000. If you are in this +- * situation, you should either update your bootloader (preferred +- * solution) or the below Device Tree should be adjusted. +- */ +- +-/dts-v1/; +-#include +-#include +-#include +-#include "armada-370.dtsi" +- +-/ { +- model = "Marvell Armada 370 Reference Design"; +- compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; /* 512 MB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- serial@12000 { +- status = "okay"; +- }; +- sata@a0000 { +- nr-ports = <2>; +- status = "okay"; +- }; +- +- ethernet@70000 { +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "sgmii"; +- }; +- ethernet@74000 { +- pinctrl-0 = <&ge1_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy-mode = "rgmii-id"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- mvsdio@d4000 { +- pinctrl-0 = <&sdio_pins1>; +- pinctrl-names = "default"; +- status = "okay"; +- /* No CD or WP GPIOs */ +- broken-cd; +- }; +- +- usb@50000 { +- status = "okay"; +- }; +- +- usb@51000 { +- status = "okay"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- button { +- label = "Software Button"; +- linux,code = ; +- gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-fan { +- compatible = "gpio-fan"; +- gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; +- gpio-fan,speed-map = <0 0 3000 1>; +- pinctrl-0 = <&fan_pins>; +- pinctrl-names = "default"; +- }; +- +- gpio_leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins>; +- +- sw_led { +- label = "370rd:green:sw"; +- gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- }; +- }; +- }; +-}; +- +-&pciec { +- status = "okay"; +- +- /* Internal mini-PCIe connector */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- +- /* Internal mini-PCIe connector */ +- pcie@2,0 { +- /* Port 1, Lane 0 */ +- status = "okay"; +- }; +-}; +- +-&mdio { +- pinctrl-0 = <&mdio_pins>; +- pinctrl-names = "default"; +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- switch: switch@10 { +- compatible = "marvell,mv88e6085"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x10>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan0"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan1"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan3"; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <ð1>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switchphy0: switchphy@0 { +- reg = <0>; +- interrupt-parent = <&switch>; +- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switchphy1: switchphy@1 { +- reg = <1>; +- interrupt-parent = <&switch>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switchphy2: switchphy@2 { +- reg = <2>; +- interrupt-parent = <&switch>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switchphy3: switchphy@3 { +- reg = <3>; +- interrupt-parent = <&switch>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; +- }; +- }; +- }; +-}; +- +- +-&pinctrl { +- fan_pins: fan-pins { +- marvell,pins = "mpp8"; +- marvell,function = "gpio"; +- }; +- +- led_pins: led-pins { +- marvell,pins = "mpp32"; +- marvell,function = "gpio"; +- }; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- marvell,nand-keep-config; +- nand-on-flash-bbt; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0 0x800000>; +- }; +- partition@800000 { +- label = "Linux"; +- reg = <0x800000 0x800000>; +- }; +- partition@1000000 { +- label = "Filesystem"; +- reg = <0x1000000 0x3f000000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-370-seagate-nas-2bay.dts b/scripts/dtc/include-prefixes/arm/armada-370-seagate-nas-2bay.dts +deleted file mode 100644 +index 8dd242e668e6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-370-seagate-nas-2bay.dts ++++ /dev/null +@@ -1,33 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree file for Seagate NAS 2-Bay (Armada 370 SoC). +- * +- * Copyright (C) 2015 Seagate +- * +- * Author: Vincent Donnefort +- */ +- +-/* +- * Here are some information allowing to identify the device: +- * +- * Product name : Seagate NAS 2-Bay +- * Code name (board/PCB) : Dart 2-Bay +- * Model name (case sticker) : SRPD20 +- * Material desc (product spec) : STCTxxxxxxx +- */ +- +-/dts-v1/; +-#include "armada-370-seagate-nas-xbay.dtsi" +- +-/ { +- model = "Seagate NAS 2-Bay (Dart, SRPD20)"; +- compatible = "seagate,dart-2", "marvell,armada370", "marvell,armada-370-xp"; +- +- gpio-fan { +- gpio-fan,speed-map = +- < 0 3 +- 950 2 +- 1400 1 +- 1800 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-370-seagate-nas-4bay.dts b/scripts/dtc/include-prefixes/arm/armada-370-seagate-nas-4bay.dts +deleted file mode 100644 +index 3cf70c72c5ca..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-370-seagate-nas-4bay.dts ++++ /dev/null +@@ -1,131 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree file for Seagate NAS 4-Bay (Armada 370 SoC). +- * +- * Copyright (C) 2015 Seagate +- * +- * Author: Vincent Donnefort +- */ +- +-/* +- * Here are some information allowing to identify the device: +- * +- * Product name : Seagate NAS 4-Bay +- * Code name (board/PCB) : Dart 4-Bay +- * Model name (case sticker) : SRPD40 +- * Material desc (product spec) : STCUxxxxxxx +- */ +- +-/dts-v1/; +-#include "armada-370-seagate-nas-xbay.dtsi" +-#include +- +-/ { +- model = "Seagate NAS 4-Bay (Dart, SRPD40)"; +- compatible = "seagate,dart-4", "marvell,armada370", "marvell,armada-370-xp"; +- +- soc { +- internal-regs { +- ethernet@74000 { +- status = "okay"; +- pinctrl-0 = <&ge1_rgmii_pins>; +- pinctrl-names = "default"; +- phy = <&phy1>; +- phy-mode = "rgmii-id"; +- }; +- +- i2c@11000 { +- /* I2C GPIO expander (PCA9554A) */ +- pca9554: pca9554@21 { +- compatible = "nxp,pca9554"; +- reg = <0x21>; +- #gpio-cells = <2>; +- gpio-controller; +- }; +- }; +- }; +- }; +- +- regulators { +- regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- regulator-name = "SATA2 power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&pca9554 6 GPIO_ACTIVE_HIGH>; +- }; +- regulator@4 { +- compatible = "regulator-fixed"; +- reg = <4>; +- regulator-name = "SATA3 power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&pca9554 7 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-leds { +- red-sata2 { +- label = "dart:red:sata2"; +- gpios = <&pca9554 0 GPIO_ACTIVE_LOW>; +- }; +- red-sata3 { +- label = "dart:red:sata3"; +- gpios = <&pca9554 3 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds-ns2 { +- compatible = "lacie,ns2-leds"; +- +- white-sata2 { +- label = "dart:white:sata2"; +- cmd-gpio = <&pca9554 1 GPIO_ACTIVE_HIGH>; +- slow-gpio = <&pca9554 2 GPIO_ACTIVE_HIGH>; +- num-modes = <4>; +- modes-map = ; +- }; +- white-sata3 { +- label = "dart:white:sata3"; +- cmd-gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>; +- slow-gpio = <&pca9554 5 GPIO_ACTIVE_HIGH>; +- num-modes = <4>; +- modes-map = ; +- }; +- }; +- +- gpio-fan { +- gpio-fan,speed-map = +- < 0 3 +- 800 2 +- 1050 1 +- 1300 0>; +- }; +-}; +- +-&pciec { +- /* SATA AHCI controller 88SE9170 */ +- pcie@1,0 { +- status = "okay"; +- }; +-}; +- +-&mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/armada-370-seagate-nas-xbay.dtsi b/scripts/dtc/include-prefixes/arm/armada-370-seagate-nas-xbay.dtsi +deleted file mode 100644 +index b52634ecf1d9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-370-seagate-nas-xbay.dtsi ++++ /dev/null +@@ -1,239 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree common file for the Seagate NAS 2 and 4-bay (Armada 370 SoC). +- * +- * Copyright (C) 2015 Seagate +- * +- * Author: Vincent Donnefort +- */ +- +-/* +- * TODO: add support for the white SATA LEDs associated with HDD 0 and 1. +- */ +- +-#include "armada-370.dtsi" +-#include +-#include +- +-/ { +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; /* 512 MB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- serial@12000 { +- status = "okay"; +- }; +- +- sata@a0000 { +- nr-ports = <2>; +- status = "okay"; +- }; +- +- ethernet@70000 { +- status = "okay"; +- pinctrl-0 = <&ge0_rgmii_pins>; +- pinctrl-names = "default"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +- }; +- +- i2c@11000 { +- status = "okay"; +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +- clock-frequency = <100000>; +- +- /* RTC - NXP 8563T (second source) */ +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- interrupts = <110>; +- }; +- /* RTC - MCP7940NT */ +- rtc@6f { +- compatible = "microchip,mcp7941x"; +- reg = <0x6f>; +- interrupts = <110>; +- }; +- }; +- }; +- +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- +- regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "SATA0 power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; +- }; +- regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "SATA1 power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-fan { +- compatible = "gpio-fan"; +- gpios = <&gpio2 0 GPIO_ACTIVE_HIGH +- &gpio2 1 GPIO_ACTIVE_HIGH>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- power { +- label = "Power button"; +- linux,code = ; +- gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; +- debounce-interval = <100>; +- }; +- backup { +- label = "Backup button"; +- linux,code = ; +- gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; +- debounce-interval = <100>; +- }; +- reset { +- label = "Reset Button"; +- linux,code = ; +- gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; +- debounce-interval = <100>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- white-power { +- label = "dart:white:power"; +- gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "timer"; +- +- }; +- red-power { +- label = "dart:red:power"; +- gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; +- }; +- red-sata0 { +- label = "dart:red:sata0"; +- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +- }; +- red-sata1 { +- label = "dart:red:sata1"; +- gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio_poweroff { +- compatible = "gpio-poweroff"; +- gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&pciec { +- status = "okay"; +- +- /* USB 3.0 bridge ASM1042A */ +- pcie@2,0 { +- status = "okay"; +- }; +-}; +- +- +-&mdio { +- pinctrl-0 = <&mdio_pins>; +- pinctrl-names = "default"; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&pinctrl { +- pinctrl-0 = <&hdd0_led_sata_pin>, <&hdd1_led_sata_pin>; +- pinctrl-names = "default"; +- +- hdd0_led_sata_pin: hdd0-led-sata-pin { +- marvell,pins = "mpp48"; +- marvell,function = "sata1"; +- }; +- hdd0_led_gpio_pin: hdd0-led-gpio-pin { +- marvell,pins = "mpp48"; +- marvell,function = "gpio"; +- }; +- hdd1_led_sata_pin: hdd1-led-sata-pin { +- marvell,pins = "mpp57"; +- marvell,function = "sata0"; +- }; +- hdd1_led_gpio_pin: hdd1-led-gpio-pin { +- marvell,pins = "mpp57"; +- marvell,function = "gpio"; +- }; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- marvell,nand-keep-config; +- nand-on-flash-bbt; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0 0x300000>; +- }; +- partition@300000 { +- label = "device-tree"; +- reg = <0x300000 0x20000>; +- }; +- partition@320000 { +- label = "linux"; +- reg = <0x320000 0x2000000>; +- }; +- partition@2320000 { +- label = "rootfs"; +- reg = <0x2320000 0xdce0000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-370-seagate-personal-cloud-2bay.dts b/scripts/dtc/include-prefixes/arm/armada-370-seagate-personal-cloud-2bay.dts +deleted file mode 100644 +index 5ee572dc9242..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-370-seagate-personal-cloud-2bay.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree file for Seagate Personal Cloud NAS 2-Bay (Armada 370 SoC). +- * +- * Copyright (C) 2015 Seagate +- * +- * Author: Simon Guinot +- */ +- +-/* +- * Here are some information allowing to identify the device: +- * +- * Product name : Seagate Personal Cloud 2-Bay +- * Code name (board/PCB) : Cumulus Max +- * Model name (case sticker) : SRN22C +- * Material desc (product spec) : STCSxxxxxxx +- */ +- +-/dts-v1/; +-#include "armada-370-seagate-personal-cloud.dtsi" +- +-/ { +- model = "Seagate Personal Cloud 2-Bay (Cumulus, SRN22C)"; +- compatible = "seagate,cumulus-max", "marvell,armada370", "marvell,armada-370-xp"; +- +- soc { +- internal-regs { +- sata@a0000 { +- status = "okay"; +- nr-ports = <2>; +- }; +- }; +- }; +- +- regulators { +- regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "SATA1 power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-370-seagate-personal-cloud.dts b/scripts/dtc/include-prefixes/arm/armada-370-seagate-personal-cloud.dts +deleted file mode 100644 +index 578b54b39c8f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-370-seagate-personal-cloud.dts ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree file for Seagate Personal Cloud NAS (Armada 370 SoC). +- * +- * Copyright (C) 2015 Seagate +- * +- * Author: Simon Guinot +- */ +- +-/* +- * Here are some information allowing to identify the device: +- * +- * Product name : Seagate Personal Cloud +- * Code name (board/PCB) : Cumulus +- * Model name (case sticker) : SRN21C +- * Material desc (product spec) : STCRxxxxxxx +- */ +- +-/dts-v1/; +-#include "armada-370-seagate-personal-cloud.dtsi" +- +-/ { +- model = "Seagate Personal Cloud (Cumulus, SRN21C)"; +- compatible = "seagate,cumulus", "marvell,armada370", "marvell,armada-370-xp"; +- +- soc { +- internal-regs { +- sata@a0000 { +- status = "okay"; +- nr-ports = <1>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-370-seagate-personal-cloud.dtsi b/scripts/dtc/include-prefixes/arm/armada-370-seagate-personal-cloud.dtsi +deleted file mode 100644 +index a624b2371fb6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-370-seagate-personal-cloud.dtsi ++++ /dev/null +@@ -1,175 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree common file for the Seagate Personal Cloud NAS 1 and 2-Bay +- * (Armada 370 SoC). +- * +- * Copyright (C) 2015 Seagate +- * +- * Author: Simon Guinot +- */ +- +-/* +- * TODO: add support for the white SATA LED. +- */ +- +-#include "armada-370.dtsi" +-#include +-#include +- +-/ { +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; /* 512 MB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- coherency-fabric@20200 { +- broken-idle; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- ethernet@74000 { +- status = "okay"; +- pinctrl-0 = <&ge1_rgmii_pins>; +- pinctrl-names = "default"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +- }; +- +- usb@50000 { +- status = "okay"; +- }; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "USB Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 27 GPIO_ACTIVE_LOW>; +- }; +- regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "SATA0 power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- power { +- label = "Power button"; +- linux,code = ; +- gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; +- debounce-interval = <100>; +- }; +- reset { +- label = "Reset Button"; +- linux,code = ; +- gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; +- debounce-interval = <100>; +- }; +- button { +- label = "USB VBUS error"; +- linux,code = ; +- gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; +- debounce-interval = <100>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- red-sata0 { +- label = "cumulus:red:sata0"; +- gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- gpio_poweroff { +- compatible = "gpio-poweroff"; +- gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&pciec { +- status = "okay"; +- +- /* USB 3.0 Bridge ASM1042A */ +- pcie@1,0 { +- status = "okay"; +- }; +-}; +- +-&mdio { +- pinctrl-0 = <&mdio_pins>; +- pinctrl-names = "default"; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&pinctrl { +- pinctrl-0 = <&sata_led_pin>; +- pinctrl-names = "default"; +- +- sata_led_pin: sata-led-pin { +- marvell,pins = "mpp60"; +- marvell,function = "sata0"; +- }; +- gpio_led_pin: gpio-led-pin { +- marvell,pins = "mpp60"; +- marvell,function = "gpio"; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- pinctrl-0 = <&spi0_pins2>; +- pinctrl-names = "default"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- /* MX25L8006E */ +- compatible = "mxicy,mx25l8005", "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <50000000>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0 0x100000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-370-synology-ds213j.dts b/scripts/dtc/include-prefixes/arm/armada-370-synology-ds213j.dts +deleted file mode 100644 +index 64f2ce254fb6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-370-synology-ds213j.dts ++++ /dev/null +@@ -1,312 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Synology DS213j +- * +- * Copyright (C) 2014, Arnaud EBALARD +- * +- * Note: this Device Tree assumes that the bootloader has remapped the +- * internal registers to 0xf1000000 (instead of the old 0xd0000000). +- * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot +- * bootloaders provided by Marvell. It is used in recent versions of +- * DSM software provided by Synology. Nonetheless, some earlier boards +- * were delivered with an older version of u-boot that left internal +- * registers mapped at 0xd0000000. If you have such a device you will +- * not be able to directly boot a kernel based on this Device Tree. In +- * that case, the preferred solution is to update your bootloader (e.g. +- * by upgrading to latest version of DSM, or building a new one and +- * installing it from u-boot prompt) or adjust the Devive Tree +- * (s/0xf1000000/0xd0000000/ in 'ranges' below). +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "armada-370.dtsi" +- +-/ { +- model = "Synology DS213j"; +- compatible = "synology,ds213j", "marvell,armada370", +- "marvell,armada-370-xp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; /* 512 MB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- +- /* RTC provided by Seiko S-35390A I2C RTC chip below */ +- rtc@10300 { +- status = "disabled"; +- }; +- +- i2c@11000 { +- compatible = "marvell,mv64xxx-i2c"; +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +- clock-frequency = <400000>; +- status = "okay"; +- +- /* Main device RTC chip */ +- s35390a: s35390a@30 { +- compatible = "sii,s35390a"; +- reg = <0x30>; +- }; +- }; +- +- /* Connected to a header on device's PCB */ +- serial@12000 { +- status = "okay"; +- }; +- +- /* Connected to a TI MSP430F2111 for power control */ +- serial@12100 { +- status = "okay"; +- }; +- +- poweroff@12100 { +- compatible = "synology,power-off"; +- reg = <0x12100 0x100>; +- clocks = <&coreclk 0>; +- }; +- +- /* rear USB port, near reset button */ +- usb@50000 { +- status = "okay"; +- }; +- +- /* rear USB port, near RJ45 port */ +- usb@51000 { +- status = "okay"; +- }; +- +- ethernet@70000 { +- status = "okay"; +- phy = <&phy1>; +- phy-mode = "sgmii"; +- }; +- +- sata@a0000 { +- nr-ports = <2>; +- status = "okay"; +- }; +- }; +- }; +- +- gpio-fan-32-38 { +- status = "okay"; +- compatible = "gpio-fan"; +- pinctrl-0 = <&fan_ctrl_low_pin &fan_ctrl_mid_pin +- &fan_ctrl_high_pin &fan_alarm_pin>; +- pinctrl-names = "default"; +- gpios = <&gpio1 31 GPIO_ACTIVE_HIGH +- &gpio2 0 GPIO_ACTIVE_HIGH +- &gpio2 1 GPIO_ACTIVE_HIGH>; +- alarm-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; +- gpio-fan,speed-map = < 0 0 +- 1000 1 +- 1150 2 +- 1350 4 +- 1500 3 +- 1650 5 +- 1750 6 +- 1900 7 >; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&disk1_led_pin +- &disk2_led_pin>; +- pinctrl-names = "default"; +- +- disk1-led-amber { +- label = "synology:amber:disk1"; +- gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- +- disk2-led-amber { +- label = "synology:amber:disk2"; +- gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin>; +- pinctrl-names = "default"; +- +- sata1_regulator: sata1-regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "SATA1 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- startup-delay-us = <2000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- }; +- +- sata2_regulator: sata2-regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "SATA2 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- startup-delay-us = <4000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&mdio { +- phy1: ethernet-phy@1 { /* Marvell 88E1512 */ +- reg = <1>; +- }; +-}; +- +-&pinctrl { +- disk1_led_pin: disk1-led-pin { +- marvell,pins = "mpp31"; +- marvell,function = "gpio"; +- }; +- +- disk2_led_pin: disk2-led-pin { +- marvell,pins = "mpp32"; +- marvell,function = "gpio"; +- }; +- +- sata1_pwr_pin: sata1-pwr-pin { +- marvell,pins = "mpp37"; +- marvell,function = "gpio"; +- }; +- +- sata2_pwr_pin: sata2-pwr-pin { +- marvell,pins = "mpp62"; +- marvell,function = "gpio"; +- }; +- +- sata1_pres_pin: sata1-pres-pin { +- marvell,pins = "mpp60"; +- marvell,function = "gpio"; +- }; +- +- sata2_pres_pin: sata2-pres-pin { +- marvell,pins = "mpp48"; +- marvell,function = "gpio"; +- }; +- +- syno_id_bit0_pin: syno-id-bit0-pin { +- marvell,pins = "mpp55"; +- marvell,function = "gpio"; +- }; +- +- syno_id_bit1_pin: syno-id-bit1-pin { +- marvell,pins = "mpp56"; +- marvell,function = "gpio"; +- }; +- +- syno_id_bit2_pin: syno-id-bit2-pin { +- marvell,pins = "mpp57"; +- marvell,function = "gpio"; +- }; +- +- syno_id_bit3_pin: syno-id-bit3-pin { +- marvell,pins = "mpp58"; +- marvell,function = "gpio"; +- }; +- +- fan_ctrl_low_pin: fan-ctrl-low-pin { +- marvell,pins = "mpp65"; +- marvell,function = "gpio"; +- }; +- +- fan_ctrl_mid_pin: fan-ctrl-mid-pin { +- marvell,pins = "mpp64"; +- marvell,function = "gpio"; +- }; +- +- fan_ctrl_high_pin: fan-ctrl-high-pin { +- marvell,pins = "mpp63"; +- marvell,function = "gpio"; +- }; +- +- fan_alarm_pin: fan-alarm-pin { +- marvell,pins = "mpp38"; +- marvell,function = "gpio"; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q064", "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <20000000>; +- +- /* +- * Warning! +- * +- * Synology u-boot uses its compiled-in environment +- * and it seems Synology did not care to change u-boot +- * default configuration in order to allow saving a +- * modified environment at a sensible location. So, +- * if you do a 'saveenv' under u-boot, your modified +- * environment will be saved at 1MB after the start +- * of the flash, i.e. in the middle of the uImage. +- * For that reason, it is strongly advised not to +- * change the default environment, unless you know +- * what you are doing. +- */ +- partition@0 { /* u-boot */ +- label = "RedBoot"; +- reg = <0x00000000 0x000c0000>; /* 768KB */ +- }; +- +- partition@c0000 { /* uImage */ +- label = "zImage"; +- reg = <0x000c0000 0x002d0000>; /* 2880KB */ +- }; +- +- partition@390000 { /* uInitramfs */ +- label = "rd.gz"; +- reg = <0x00390000 0x00440000>; /* 4250KB */ +- }; +- +- partition@7d0000 { /* MAC address and serial number */ +- label = "vendor"; +- reg = <0x007d0000 0x00010000>; /* 64KB */ +- }; +- +- partition@7e0000 { +- label = "RedBoot config"; +- reg = <0x007e0000 0x00010000>; /* 64KB */ +- }; +- +- partition@7f0000 { +- label = "FIS directory"; +- reg = <0x007f0000 0x00010000>; /* 64KB */ +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-370-xp.dtsi b/scripts/dtc/include-prefixes/arm/armada-370-xp.dtsi +deleted file mode 100644 +index 0b8c2a64b36f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-370-xp.dtsi ++++ /dev/null +@@ -1,313 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell Armada 370 and Armada XP SoC +- * +- * Copyright (C) 2012 Marvell +- * +- * Lior Amsalem +- * Gregory CLEMENT +- * Thomas Petazzoni +- * Ben Dooks +- * +- * This file contains the definitions that are common to the Armada +- * 370 and Armada XP SoC. +- */ +- +-#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) +- +-/ { +- model = "Marvell Armada 370 and XP SoC"; +- compatible = "marvell,armada-370-xp"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- compatible = "marvell,sheeva-v7"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts-extended = <&mpic 3>; +- }; +- +- soc { +- #address-cells = <2>; +- #size-cells = <1>; +- controller = <&mbusc>; +- interrupt-parent = <&mpic>; +- pcie-mem-aperture = <0xf8000000 0x7e00000>; +- pcie-io-aperture = <0xffe00000 0x100000>; +- +- devbus_bootcs: devbus-bootcs { +- compatible = "marvell,mvebu-devbus"; +- reg = ; +- ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- devbus_cs0: devbus-cs0 { +- compatible = "marvell,mvebu-devbus"; +- reg = ; +- ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- devbus_cs1: devbus-cs1 { +- compatible = "marvell,mvebu-devbus"; +- reg = ; +- ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- devbus_cs2: devbus-cs2 { +- compatible = "marvell,mvebu-devbus"; +- reg = ; +- ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- devbus_cs3: devbus-cs3 { +- compatible = "marvell,mvebu-devbus"; +- reg = ; +- ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- internal-regs { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; +- +- rtc: rtc@10300 { +- compatible = "marvell,orion-rtc"; +- reg = <0x10300 0x20>; +- interrupts = <50>; +- }; +- +- i2c0: i2c@11000 { +- compatible = "marvell,mv64xxx-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <31>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@11100 { +- compatible = "marvell,mv64xxx-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <32>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- uart0: serial@12000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x12000 0x100>; +- reg-shift = <2>; +- interrupts = <41>; +- reg-io-width = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- uart1: serial@12100 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x12100 0x100>; +- reg-shift = <2>; +- interrupts = <42>; +- reg-io-width = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- pinctrl: pin-ctrl@18000 { +- reg = <0x18000 0x38>; +- }; +- +- coredivclk: corediv-clock@18740 { +- compatible = "marvell,armada-370-corediv-clock"; +- reg = <0x18740 0xc>; +- #clock-cells = <1>; +- clocks = <&mainpll>; +- clock-output-names = "nand"; +- }; +- +- mbusc: mbus-controller@20000 { +- compatible = "marvell,mbus-controller"; +- reg = <0x20000 0x100>, <0x20180 0x20>, +- <0x20250 0x8>; +- }; +- +- mpic: interrupt-controller@20a00 { +- compatible = "marvell,mpic"; +- #interrupt-cells = <1>; +- #size-cells = <1>; +- interrupt-controller; +- msi-controller; +- }; +- +- coherencyfab: coherency-fabric@20200 { +- compatible = "marvell,coherency-fabric"; +- reg = <0x20200 0xb0>, <0x21010 0x1c>; +- }; +- +- timer: timer@20300 { +- reg = <0x20300 0x30>, <0x21040 0x30>; +- interrupts = <37>, <38>, <39>, <40>, <5>, <6>; +- }; +- +- watchdog: watchdog@20300 { +- reg = <0x20300 0x34>, <0x20704 0x4>; +- }; +- +- cpurst: cpurst@20800 { +- compatible = "marvell,armada-370-cpu-reset"; +- reg = <0x20800 0x8>; +- }; +- +- pmsu: pmsu@22000 { +- compatible = "marvell,armada-370-pmsu"; +- reg = <0x22000 0x1000>; +- }; +- +- usb0: usb@50000 { +- compatible = "marvell,orion-ehci"; +- reg = <0x50000 0x500>; +- interrupts = <45>; +- status = "disabled"; +- }; +- +- usb1: usb@51000 { +- compatible = "marvell,orion-ehci"; +- reg = <0x51000 0x500>; +- interrupts = <46>; +- status = "disabled"; +- }; +- +- eth0: ethernet@70000 { +- reg = <0x70000 0x4000>; +- interrupts = <8>; +- clocks = <&gateclk 4>; +- status = "disabled"; +- }; +- +- mdio: mdio@72004 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "marvell,orion-mdio"; +- reg = <0x72004 0x4>; +- clocks = <&gateclk 4>; +- }; +- +- eth1: ethernet@74000 { +- reg = <0x74000 0x4000>; +- interrupts = <10>; +- clocks = <&gateclk 3>; +- status = "disabled"; +- }; +- +- sata: sata@a0000 { +- compatible = "marvell,armada-370-sata"; +- reg = <0xa0000 0x5000>; +- interrupts = <55>; +- clocks = <&gateclk 15>, <&gateclk 30>; +- clock-names = "0", "1"; +- status = "disabled"; +- }; +- +- nand_controller: nand-controller@d0000 { +- compatible = "marvell,armada370-nand-controller"; +- reg = <0xd0000 0x54>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <113>; +- clocks = <&coredivclk 0>; +- status = "disabled"; +- }; +- +- sdio: mvsdio@d4000 { +- compatible = "marvell,orion-sdio"; +- reg = <0xd4000 0x200>; +- interrupts = <54>; +- clocks = <&gateclk 17>; +- bus-width = <4>; +- cap-sdio-irq; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- status = "disabled"; +- }; +- }; +- +- spi0: spi@10600 { +- reg = , /* control */ +- , /* CS0 */ +- , /* CS1 */ +- , /* CS2 */ +- , /* CS3 */ +- , /* CS4 */ +- , /* CS5 */ +- , /* CS6 */ +- ; /* CS7 */ +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- interrupts = <30>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- spi1: spi@10680 { +- reg = , /* control */ +- , /* CS0 */ +- , /* CS1 */ +- , /* CS2 */ +- , /* CS3 */ +- , /* CS4 */ +- , /* CS5 */ +- , /* CS6 */ +- ; /* CS7 */ +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- interrupts = <92>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- }; +- +- clocks { +- /* 2 GHz fixed main PLL */ +- mainpll: mainpll { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <2000000000>; +- }; +- }; +- }; +diff --git a/scripts/dtc/include-prefixes/arm/armada-370.dtsi b/scripts/dtc/include-prefixes/arm/armada-370.dtsi +deleted file mode 100644 +index 46e6d3ed8f35..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-370.dtsi ++++ /dev/null +@@ -1,419 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell Armada 370 family SoC +- * +- * Copyright (C) 2012 Marvell +- * +- * Lior Amsalem +- * Gregory CLEMENT +- * Thomas Petazzoni +- * +- * Contains definitions specific to the Armada 370 SoC that are not +- * common to all Armada SoCs. +- */ +- +-#include "armada-370-xp.dtsi" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- model = "Marvell Armada 370 family SoC"; +- compatible = "marvell,armada370", "marvell,armada-370-xp"; +- +- aliases { +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- gpio2 = &gpio2; +- }; +- +- soc { +- compatible = "marvell,armada370-mbus", "simple-bus"; +- +- bootrom { +- compatible = "marvell,bootrom"; +- reg = ; +- }; +- +- pciec: pcie@82000000 { +- compatible = "marvell,armada-370-pcie"; +- status = "disabled"; +- device_type = "pci"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- msi-parent = <&mpic>; +- bus-range = <0x00 0xff>; +- +- ranges = +- <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 +- 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 +- 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ +- 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ +- 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ +- 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; +- +- pcie0: pcie@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 +- 0x81000000 0 0 0x81000000 0x1 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 58>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 5>; +- status = "disabled"; +- }; +- +- pcie2: pcie@2,0 { +- device_type = "pci"; +- assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; +- reg = <0x1000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 +- 0x81000000 0 0 0x81000000 0x2 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 62>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 9>; +- status = "disabled"; +- }; +- }; +- +- internal-regs { +- L2: l2-cache@8000 { +- compatible = "marvell,aurora-outer-cache"; +- reg = <0x08000 0x1000>; +- cache-id-part = <0x100>; +- cache-level = <2>; +- cache-unified; +- wt-override; +- }; +- +- gpio0: gpio@18100 { +- compatible = "marvell,armada-370-gpio", +- "marvell,orion-gpio"; +- reg = <0x18100 0x40>, <0x181c0 0x08>; +- reg-names = "gpio", "pwm"; +- ngpios = <32>; +- gpio-controller; +- #gpio-cells = <2>; +- #pwm-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <82>, <83>, <84>, <85>; +- clocks = <&coreclk 0>; +- }; +- +- gpio1: gpio@18140 { +- compatible = "marvell,armada-370-gpio", +- "marvell,orion-gpio"; +- reg = <0x18140 0x40>, <0x181c8 0x08>; +- reg-names = "gpio", "pwm"; +- ngpios = <32>; +- gpio-controller; +- #gpio-cells = <2>; +- #pwm-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <87>, <88>, <89>, <90>; +- clocks = <&coreclk 0>; +- }; +- +- gpio2: gpio@18180 { +- compatible = "marvell,armada-370-gpio", +- "marvell,orion-gpio"; +- reg = <0x18180 0x40>; +- ngpios = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <91>; +- }; +- +- +- systemc: system-controller@18200 { +- compatible = "marvell,armada-370-xp-system-controller"; +- reg = <0x18200 0x100>; +- }; +- +- gateclk: clock-gating-control@18220 { +- compatible = "marvell,armada-370-gating-clock"; +- reg = <0x18220 0x4>; +- clocks = <&coreclk 0>; +- #clock-cells = <1>; +- }; +- +- coreclk: mvebu-sar@18230 { +- compatible = "marvell,armada-370-core-clock"; +- reg = <0x18230 0x08>; +- #clock-cells = <1>; +- }; +- +- thermal: thermal@18300 { +- compatible = "marvell,armada370-thermal"; +- reg = <0x18300 0x4 +- 0x18304 0x4>; +- status = "okay"; +- }; +- +- sscg: sscg@18330 { +- reg = <0x18330 0x4>; +- }; +- +- cpuconf: cpu-config@21000 { +- compatible = "marvell,armada-370-cpu-config"; +- reg = <0x21000 0x8>; +- }; +- +- audio_controller: audio-controller@30000 { +- #sound-dai-cells = <1>; +- compatible = "marvell,armada370-audio"; +- reg = <0x30000 0x4000>; +- interrupts = <93>; +- clocks = <&gateclk 0>; +- clock-names = "internal"; +- status = "disabled"; +- }; +- +- xor0: xor@60800 { +- compatible = "marvell,orion-xor"; +- reg = <0x60800 0x100 +- 0x60A00 0x100>; +- status = "okay"; +- +- xor00 { +- interrupts = <51>; +- dmacap,memcpy; +- dmacap,xor; +- }; +- xor01 { +- interrupts = <52>; +- dmacap,memcpy; +- dmacap,xor; +- dmacap,memset; +- }; +- }; +- +- xor1: xor@60900 { +- compatible = "marvell,orion-xor"; +- reg = <0x60900 0x100 +- 0x60b00 0x100>; +- status = "okay"; +- +- xor10 { +- interrupts = <94>; +- dmacap,memcpy; +- dmacap,xor; +- }; +- xor11 { +- interrupts = <95>; +- dmacap,memcpy; +- dmacap,xor; +- dmacap,memset; +- }; +- }; +- +- cesa: crypto@90000 { +- compatible = "marvell,armada-370-crypto"; +- reg = <0x90000 0x10000>; +- reg-names = "regs"; +- interrupts = <48>; +- clocks = <&gateclk 23>; +- clock-names = "cesa0"; +- marvell,crypto-srams = <&crypto_sram>; +- marvell,crypto-sram-size = <0x7e0>; +- }; +- }; +- +- crypto_sram: sa-sram { +- compatible = "mmio-sram"; +- reg = ; +- reg-names = "sram"; +- clocks = <&gateclk 23>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>; +- +- /* +- * The Armada 370 has an erratum preventing the use of +- * the standard workflow for CPU idle support (relying +- * on the BootROM code to enter/exit idle state). +- * Reserve some amount of the crypto SRAM to put the +- * cpuidle workaround. +- */ +- idle-sram@0 { +- reg = <0x0 0x20>; +- }; +- }; +- }; +-}; +- +-/* +- * Default UART pinctrl setting without RTS/CTS, can be overwritten on +- * board level if a different configuration is used. +- */ +- +-&uart0 { +- pinctrl-0 = <&uart0_pins>; +- pinctrl-names = "default"; +-}; +- +-&uart1 { +- pinctrl-0 = <&uart1_pins>; +- pinctrl-names = "default"; +-}; +- +-&i2c0 { +- reg = <0x11000 0x20>; +-}; +- +-&i2c1 { +- reg = <0x11100 0x20>; +-}; +- +-&mpic { +- reg = <0x20a00 0x1d0>, <0x21870 0x58>; +-}; +- +-&timer { +- compatible = "marvell,armada-370-timer"; +- clocks = <&coreclk 2>; +-}; +- +-&watchdog { +- compatible = "marvell,armada-370-wdt"; +- clocks = <&coreclk 2>; +-}; +- +-&usb0 { +- clocks = <&coreclk 0>; +-}; +- +-&usb1 { +- clocks = <&coreclk 0>; +-}; +- +-ð0 { +- compatible = "marvell,armada-370-neta"; +-}; +- +-ð1 { +- compatible = "marvell,armada-370-neta"; +-}; +- +-&pinctrl { +- compatible = "marvell,mv88f6710-pinctrl"; +- +- spi0_pins1: spi0-pins1 { +- marvell,pins = "mpp33", "mpp34", +- "mpp35", "mpp36"; +- marvell,function = "spi0"; +- }; +- +- spi0_pins2: spi0_pins2 { +- marvell,pins = "mpp32", "mpp63", +- "mpp64", "mpp65"; +- marvell,function = "spi0"; +- }; +- +- spi1_pins: spi1-pins { +- marvell,pins = "mpp49", "mpp50", +- "mpp51", "mpp52"; +- marvell,function = "spi1"; +- }; +- +- uart0_pins: uart0-pins { +- marvell,pins = "mpp0", "mpp1"; +- marvell,function = "uart0"; +- }; +- +- uart1_pins: uart1-pins { +- marvell,pins = "mpp41", "mpp42"; +- marvell,function = "uart1"; +- }; +- +- sdio_pins1: sdio-pins1 { +- marvell,pins = "mpp9", "mpp11", "mpp12", +- "mpp13", "mpp14", "mpp15"; +- marvell,function = "sd0"; +- }; +- +- sdio_pins2: sdio-pins2 { +- marvell,pins = "mpp47", "mpp48", "mpp49", +- "mpp50", "mpp51", "mpp52"; +- marvell,function = "sd0"; +- }; +- +- sdio_pins3: sdio-pins3 { +- marvell,pins = "mpp48", "mpp49", "mpp50", +- "mpp51", "mpp52", "mpp53"; +- marvell,function = "sd0"; +- }; +- +- i2c0_pins: i2c0-pins { +- marvell,pins = "mpp2", "mpp3"; +- marvell,function = "i2c0"; +- }; +- +- i2s_pins1: i2s-pins1 { +- marvell,pins = "mpp5", "mpp6", "mpp7", +- "mpp8", "mpp9", "mpp10", +- "mpp12", "mpp13"; +- marvell,function = "audio"; +- }; +- +- i2s_pins2: i2s-pins2 { +- marvell,pins = "mpp49", "mpp47", "mpp50", +- "mpp59", "mpp57", "mpp61", +- "mpp62", "mpp60", "mpp58"; +- marvell,function = "audio"; +- }; +- +- mdio_pins: mdio-pins { +- marvell,pins = "mpp17", "mpp18"; +- marvell,function = "ge"; +- }; +- +- ge0_rgmii_pins: ge0-rgmii-pins { +- marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8", +- "mpp9", "mpp10", "mpp11", "mpp12", +- "mpp13", "mpp14", "mpp15", "mpp16"; +- marvell,function = "ge0"; +- }; +- +- ge1_rgmii_pins: ge1-rgmii-pins { +- marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22", +- "mpp23", "mpp24", "mpp25", "mpp26", +- "mpp27", "mpp28", "mpp29", "mpp30"; +- marvell,function = "ge1"; +- }; +-}; +- +-/* +- * Default SPI pinctrl setting, can be overwritten on +- * board level if a different configuration is used. +- */ +-&spi0 { +- compatible = "marvell,armada-370-spi", "marvell,orion-spi"; +- pinctrl-0 = <&spi0_pins1>; +- pinctrl-names = "default"; +-}; +- +-&spi1 { +- compatible = "marvell,armada-370-spi", "marvell,orion-spi"; +- pinctrl-0 = <&spi1_pins>; +- pinctrl-names = "default"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-375-db.dts b/scripts/dtc/include-prefixes/arm/armada-375-db.dts +deleted file mode 100644 +index 0e679465cbb5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-375-db.dts ++++ /dev/null +@@ -1,182 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Marvell Armada 375 evaluation board +- * (DB-88F6720) +- * +- * Copyright (C) 2014 Marvell +- * +- * Gregory CLEMENT +- * Thomas Petazzoni +- */ +- +-/dts-v1/; +-#include +-#include "armada-375.dtsi" +- +-/ { +- model = "Marvell Armada 375 Development Board"; +- compatible = "marvell,a375-db", "marvell,armada375"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x40000000>; /* 1 GB */ +- }; +- +- soc { +- ranges = ; +- +- }; +-}; +-&pciec { +- status = "okay"; +-}; +- +-/* +- * The two PCIe units are accessible through +- * standard PCIe slots on the board. +- */ +-&pcie0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +-}; +- +-&pcie1 { +- /* Port 1, Lane 0 */ +- status = "okay"; +-}; +- +- +-&spi0 { +- pinctrl-0 = <&spi0_pins>; +- pinctrl-names = "default"; +- +- /* +- * SPI conflicts with NAND, so we disable it here, and +- * select NAND as the enabled device by default. +- */ +- +- status = "disabled"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "n25q128a13", "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <108000000>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <100000>; +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <100000>; +- pinctrl-0 = <&i2c1_pins>; +- pinctrl-names = "default"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&pinctrl { +- sdio_st_pins: sdio-st-pins { +- marvell,pins = "mpp44", "mpp45"; +- marvell,function = "gpio"; +- }; +-}; +- +-&sata { +- status = "okay"; +- nr-ports = <2>; +-}; +- +-&nand_controller { +- status = "okay"; +- pinctrl-0 = <&nand_pins>; +- pinctrl-names = "default"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- marvell,nand-keep-config; +- nand-on-flash-bbt; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0 0x800000>; +- }; +- partition@800000 { +- label = "Linux"; +- reg = <0x800000 0x800000>; +- }; +- partition@1000000 { +- label = "Filesystem"; +- reg = <0x1000000 0x3f000000>; +- }; +- }; +- }; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&usb2 { +- status = "okay"; +-}; +- +-&sdio { +- pinctrl-0 = <&sdio_pins &sdio_st_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; +- wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; +-}; +- +-&mdio { +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- phy3: ethernet-phy@3 { +- reg = <3>; +- }; +-}; +- +-ðernet { +- status = "okay"; +-}; +- +- +-ð0 { +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +-}; +- +-ð1 { +- status = "okay"; +- phy = <&phy3>; +- phy-mode = "gmii"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-375.dtsi b/scripts/dtc/include-prefixes/arm/armada-375.dtsi +deleted file mode 100644 +index 7f2f24a29e6c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-375.dtsi ++++ /dev/null +@@ -1,621 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell Armada 375 family SoC +- * +- * Copyright (C) 2014 Marvell +- * +- * Gregory CLEMENT +- * Thomas Petazzoni +- */ +- +-#include +-#include +-#include +- +-#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- model = "Marvell Armada 375 family SoC"; +- compatible = "marvell,armada375"; +- +- aliases { +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- gpio2 = &gpio2; +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- clocks { +- /* 1 GHz fixed main PLL */ +- mainpll: mainpll { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <1000000000>; +- }; +- /* 25 MHz reference crystal */ +- refclk: oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "marvell,armada-375-smp"; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- }; +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <1>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts-extended = <&mpic 3>; +- }; +- +- soc { +- compatible = "marvell,armada375-mbus", "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- controller = <&mbusc>; +- interrupt-parent = <&gic>; +- pcie-mem-aperture = <0xe0000000 0x8000000>; +- pcie-io-aperture = <0xe8000000 0x100000>; +- +- bootrom { +- compatible = "marvell,bootrom"; +- reg = ; +- }; +- +- devbus_bootcs: devbus-bootcs { +- compatible = "marvell,mvebu-devbus"; +- reg = ; +- ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- devbus_cs0: devbus-cs0 { +- compatible = "marvell,mvebu-devbus"; +- reg = ; +- ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- devbus_cs1: devbus-cs1 { +- compatible = "marvell,mvebu-devbus"; +- reg = ; +- ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- devbus_cs2: devbus-cs2 { +- compatible = "marvell,mvebu-devbus"; +- reg = ; +- ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- devbus_cs3: devbus-cs3 { +- compatible = "marvell,mvebu-devbus"; +- reg = ; +- ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- internal-regs { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; +- +- L2: cache-controller@8000 { +- compatible = "arm,pl310-cache"; +- reg = <0x8000 0x1000>; +- cache-unified; +- cache-level = <2>; +- arm,double-linefill-incr = <0>; +- arm,double-linefill-wrap = <0>; +- arm,double-linefill = <0>; +- prefetch-data = <1>; +- }; +- +- scu: scu@c000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0xc000 0x58>; +- }; +- +- timer0: timer@c600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0xc600 0x20>; +- interrupts = ; +- clocks = <&coreclk 2>; +- }; +- +- gic: interrupt-controller@d000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #size-cells = <0>; +- interrupt-controller; +- reg = <0xd000 0x1000>, +- <0xc100 0x100>; +- }; +- +- mdio: mdio@c0054 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "marvell,orion-mdio"; +- reg = <0xc0054 0x4>; +- clocks = <&gateclk 19>; +- }; +- +- /* Network controller */ +- ethernet: ethernet@f0000 { +- compatible = "marvell,armada-375-pp2"; +- reg = <0xf0000 0xa000>, /* Packet Processor regs */ +- <0xc0000 0x3060>, /* LMS regs */ +- <0xc4000 0x100>, /* eth0 regs */ +- <0xc5000 0x100>; /* eth1 regs */ +- clocks = <&gateclk 3>, <&gateclk 19>; +- clock-names = "pp_clk", "gop_clk"; +- status = "disabled"; +- +- eth0: eth0 { +- interrupts = ; +- port-id = <0>; +- status = "disabled"; +- }; +- +- eth1: eth1 { +- interrupts = ; +- port-id = <1>; +- status = "disabled"; +- }; +- }; +- +- rtc: rtc@10300 { +- compatible = "marvell,orion-rtc"; +- reg = <0x10300 0x20>; +- interrupts = ; +- }; +- +- spi0: spi@10600 { +- compatible = "marvell,armada-375-spi", +- "marvell,orion-spi"; +- reg = <0x10600 0x50>; +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- interrupts = ; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- spi1: spi@10680 { +- compatible = "marvell,armada-375-spi", +- "marvell,orion-spi"; +- reg = <0x10680 0x50>; +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- interrupts = ; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- i2c0: i2c@11000 { +- compatible = "marvell,mv64xxx-i2c"; +- reg = <0x11000 0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@11100 { +- compatible = "marvell,mv64xxx-i2c"; +- reg = <0x11100 0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- uart0: serial@12000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x12000 0x100>; +- reg-shift = <2>; +- interrupts = ; +- reg-io-width = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- uart1: serial@12100 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x12100 0x100>; +- reg-shift = <2>; +- interrupts = ; +- reg-io-width = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- pinctrl: pinctrl@18000 { +- compatible = "marvell,mv88f6720-pinctrl"; +- reg = <0x18000 0x24>; +- +- i2c0_pins: i2c0-pins { +- marvell,pins = "mpp14", "mpp15"; +- marvell,function = "i2c0"; +- }; +- +- i2c1_pins: i2c1-pins { +- marvell,pins = "mpp61", "mpp62"; +- marvell,function = "i2c1"; +- }; +- +- nand_pins: nand-pins { +- marvell,pins = "mpp0", "mpp1", "mpp2", +- "mpp3", "mpp4", "mpp5", +- "mpp6", "mpp7", "mpp8", +- "mpp9", "mpp10", "mpp11", +- "mpp12", "mpp13"; +- marvell,function = "nand"; +- }; +- +- sdio_pins: sdio-pins { +- marvell,pins = "mpp24", "mpp25", "mpp26", +- "mpp27", "mpp28", "mpp29"; +- marvell,function = "sd"; +- }; +- +- spi0_pins: spi0-pins { +- marvell,pins = "mpp0", "mpp1", "mpp4", +- "mpp5", "mpp8", "mpp9"; +- marvell,function = "spi0"; +- }; +- }; +- +- gpio0: gpio@18100 { +- compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; +- ngpios = <32>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = , +- , +- , +- ; +- }; +- +- gpio1: gpio@18140 { +- compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; +- ngpios = <32>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = , +- , +- , +- ; +- }; +- +- gpio2: gpio@18180 { +- compatible = "marvell,orion-gpio"; +- reg = <0x18180 0x40>; +- ngpios = <3>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- +- systemc: system-controller@18200 { +- compatible = "marvell,armada-375-system-controller"; +- reg = <0x18200 0x100>; +- }; +- +- gateclk: clock-gating-control@18220 { +- compatible = "marvell,armada-375-gating-clock"; +- reg = <0x18220 0x4>; +- clocks = <&coreclk 0>; +- #clock-cells = <1>; +- }; +- +- usbcluster: usb-cluster@18400 { +- compatible = "marvell,armada-375-usb-cluster"; +- reg = <0x18400 0x4>; +- #phy-cells = <1>; +- }; +- +- mbusc: mbus-controller@20000 { +- compatible = "marvell,mbus-controller"; +- reg = <0x20000 0x100>, <0x20180 0x20>; +- }; +- +- mpic: interrupt-controller@20a00 { +- compatible = "marvell,mpic"; +- reg = <0x20a00 0x2d0>, <0x21070 0x58>; +- #interrupt-cells = <1>; +- #size-cells = <1>; +- interrupt-controller; +- msi-controller; +- interrupts = ; +- }; +- +- timer1: timer@20300 { +- compatible = "marvell,armada-375-timer", "marvell,armada-370-timer"; +- reg = <0x20300 0x30>, <0x21040 0x30>; +- interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, +- <&mpic 5>, +- <&mpic 6>; +- clocks = <&coreclk 0>, <&refclk>; +- clock-names = "nbclk", "fixed"; +- }; +- +- watchdog: watchdog@20300 { +- compatible = "marvell,armada-375-wdt"; +- reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>; +- clocks = <&coreclk 0>, <&refclk>; +- clock-names = "nbclk", "fixed"; +- }; +- +- cpurst: cpurst@20800 { +- compatible = "marvell,armada-370-cpu-reset"; +- reg = <0x20800 0x10>; +- }; +- +- coherencyfab: coherency-fabric@21010 { +- compatible = "marvell,armada-375-coherency-fabric"; +- reg = <0x21010 0x1c>; +- }; +- +- usb0: usb@50000 { +- compatible = "marvell,orion-ehci"; +- reg = <0x50000 0x500>; +- interrupts = ; +- clocks = <&gateclk 18>; +- phys = <&usbcluster PHY_TYPE_USB2>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usb1: usb@54000 { +- compatible = "marvell,orion-ehci"; +- reg = <0x54000 0x500>; +- interrupts = ; +- clocks = <&gateclk 26>; +- status = "disabled"; +- }; +- +- usb2: usb@58000 { +- compatible = "marvell,armada-375-xhci"; +- reg = <0x58000 0x20000>,<0x5b880 0x80>; +- interrupts = ; +- clocks = <&gateclk 16>; +- phys = <&usbcluster PHY_TYPE_USB3>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- xor0: xor@60800 { +- compatible = "marvell,orion-xor"; +- reg = <0x60800 0x100 +- 0x60A00 0x100>; +- clocks = <&gateclk 22>; +- status = "okay"; +- +- xor00 { +- interrupts = ; +- dmacap,memcpy; +- dmacap,xor; +- }; +- xor01 { +- interrupts = ; +- dmacap,memcpy; +- dmacap,xor; +- dmacap,memset; +- }; +- }; +- +- xor1: xor@60900 { +- compatible = "marvell,orion-xor"; +- reg = <0x60900 0x100 +- 0x60b00 0x100>; +- clocks = <&gateclk 23>; +- status = "okay"; +- +- xor10 { +- interrupts = ; +- dmacap,memcpy; +- dmacap,xor; +- }; +- xor11 { +- interrupts = ; +- dmacap,memcpy; +- dmacap,xor; +- dmacap,memset; +- }; +- }; +- +- cesa: crypto@90000 { +- compatible = "marvell,armada-375-crypto"; +- reg = <0x90000 0x10000>; +- reg-names = "regs"; +- interrupts = , +- ; +- clocks = <&gateclk 30>, <&gateclk 31>, +- <&gateclk 28>, <&gateclk 29>; +- clock-names = "cesa0", "cesa1", +- "cesaz0", "cesaz1"; +- marvell,crypto-srams = <&crypto_sram0>, +- <&crypto_sram1>; +- marvell,crypto-sram-size = <0x800>; +- }; +- +- sata: sata@a0000 { +- compatible = "marvell,armada-370-sata"; +- reg = <0xa0000 0x5000>; +- interrupts = ; +- clocks = <&gateclk 14>, <&gateclk 20>; +- clock-names = "0", "1"; +- status = "disabled"; +- }; +- +- nand_controller: nand-controller@d0000 { +- compatible = "marvell,armada370-nand-controller"; +- reg = <0xd0000 0x54>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&gateclk 11>; +- status = "disabled"; +- }; +- +- sdio: mvsdio@d4000 { +- compatible = "marvell,orion-sdio"; +- reg = <0xd4000 0x200>; +- interrupts = ; +- clocks = <&gateclk 17>; +- bus-width = <4>; +- cap-sdio-irq; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- status = "disabled"; +- }; +- +- thermal: thermal@e8078 { +- compatible = "marvell,armada375-thermal"; +- reg = <0xe8078 0x4>, <0xe807c 0x8>; +- status = "okay"; +- }; +- +- coreclk: mvebu-sar@e8204 { +- compatible = "marvell,armada-375-core-clock"; +- reg = <0xe8204 0x04>; +- #clock-cells = <1>; +- }; +- +- coredivclk: corediv-clock@e8250 { +- compatible = "marvell,armada-375-corediv-clock"; +- reg = <0xe8250 0xc>; +- #clock-cells = <1>; +- clocks = <&mainpll>; +- clock-output-names = "nand"; +- }; +- }; +- +- pciec: pcie@82000000 { +- compatible = "marvell,armada-370-pcie"; +- status = "disabled"; +- device_type = "pci"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- msi-parent = <&mpic>; +- bus-range = <0x00 0xff>; +- +- ranges = +- <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 +- 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 +- 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */ +- 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */ +- 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */ +- 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>; +- +- pcie0: pcie@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 +- 0x81000000 0 0 0x81000000 0x1 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 5>; +- status = "disabled"; +- }; +- +- pcie1: pcie@2,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; +- reg = <0x1000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 +- 0x81000000 0 0 0x81000000 0x2 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <1>; +- clocks = <&gateclk 6>; +- status = "disabled"; +- }; +- +- }; +- +- crypto_sram0: sa-sram0 { +- compatible = "mmio-sram"; +- reg = ; +- clocks = <&gateclk 30>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>; +- }; +- +- crypto_sram1: sa-sram1 { +- compatible = "mmio-sram"; +- reg = ; +- clocks = <&gateclk 31>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-380.dtsi b/scripts/dtc/include-prefixes/arm/armada-380.dtsi +deleted file mode 100644 +index cff1269f3fbf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-380.dtsi ++++ /dev/null +@@ -1,118 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell Armada 380 SoC. +- * +- * Copyright (C) 2014 Marvell +- * +- * Lior Amsalem +- * Gregory CLEMENT +- * Thomas Petazzoni +- */ +- +-#include "armada-38x.dtsi" +- +-/ { +- model = "Marvell Armada 380 family SoC"; +- compatible = "marvell,armada380"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "marvell,armada-380-smp"; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- }; +- }; +- +- soc { +- internal-regs { +- pinctrl@18000 { +- compatible = "marvell,mv88f6810-pinctrl"; +- }; +- }; +- +- pcie { +- compatible = "marvell,armada-370-pcie"; +- status = "disabled"; +- device_type = "pci"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- msi-parent = <&mpic>; +- bus-range = <0x00 0xff>; +- +- ranges = +- <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 +- 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 +- 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 +- 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 +- 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ +- 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ +- 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ +- 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ +- 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ +- 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; +- +- /* x1 port */ +- pcie@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 +- 0x81000000 0 0 0x81000000 0x1 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 8>; +- status = "disabled"; +- }; +- +- /* x1 port */ +- pcie@2,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; +- reg = <0x1000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 +- 0x81000000 0 0 0x81000000 0x2 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 5>; +- status = "disabled"; +- }; +- +- /* x1 port */ +- pcie@3,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; +- reg = <0x1800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 +- 0x81000000 0 0 0x81000000 0x3 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; +- marvell,pcie-port = <2>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 6>; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-382-rd-ac3x-48g4x2xl.dts b/scripts/dtc/include-prefixes/arm/armada-382-rd-ac3x-48g4x2xl.dts +deleted file mode 100644 +index 584f0d0398a5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-382-rd-ac3x-48g4x2xl.dts ++++ /dev/null +@@ -1,112 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for Marvell Armada 382 reference board +- * (RD-AC3X-48G4X2XL) +- * +- * Copyright (C) 2020 Allied Telesis Labs +- */ +- +-/dts-v1/; +-#include "armada-385.dtsi" +- +-#include +- +-/ { +- model = "Marvell Armada 382 RD-AC3X"; +- compatible = "marvell,rd-ac3x-48g4x2xl", "marvell,rd-ac3x", +- "marvell,armada385", "marvell,armada380"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- ethernet0 = ð1; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; /* 512MB */ +- }; +- +- soc { +- ranges = ; +- }; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +- +- eeprom@53{ +- compatible = "atmel,24c64"; +- reg = <0x53>; +- }; +- +- /* CPLD device present at 0x3c. Function unknown */ +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +-ð1 { +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +-}; +- +-&mdio { +- pinctrl-names = "default"; +- pinctrl-0 = <&mdio_pins>; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie1 { +- /* Port 0, Lane 0 */ +- status = "okay"; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- nand-on-flash-bbt; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- reg = <0x00000000 0x00500000>; +- label = "u-boot"; +- }; +- partition@500000{ +- reg = <0x00500000 0x00400000>; +- label = "u-boot env"; +- }; +- partition@900000{ +- reg = <0x00900000 0x3F700000>; +- label = "user"; +- }; +- }; +- }; +-}; +- +-&refclk { +- clock-frequency = <200000000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-385-atl-x530.dts b/scripts/dtc/include-prefixes/arm/armada-385-atl-x530.dts +deleted file mode 100644 +index ed3f41c7df71..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-385-atl-x530.dts ++++ /dev/null +@@ -1,235 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for Armada 385 Allied Telesis x530/GS980MX Board. +- (x530/AT-GS980MX) +- * +- Copyright (C) 2020 Allied Telesis Labs +- */ +- +-/dts-v1/; +-#include "armada-385.dtsi" +- +-#include +- +-/ { +- model = "x530/AT-GS980MX"; +- compatible = "alliedtelesis,gs980mx", "alliedtelesis,x530", "marvell,armada385", "marvell,armada380"; +- +- chosen { +- stdout-path = "serial1:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x40000000>; /* 1GB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- i2c0: i2c@11000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +- }; +- +- uart0: serial@12000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +- }; +- }; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +- reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; +- reset-delay-us = <400000>; +-}; +- +-&pcie2 { +- status = "okay"; +-}; +- +-&devbus_cs1 { +- compatible = "marvell,mvebu-devbus"; +- status = "okay"; +- +- devbus,bus-width = <8>; +- devbus,turn-off-ps = <60000>; +- devbus,badr-skew-ps = <0>; +- devbus,acc-first-ps = <124000>; +- devbus,acc-next-ps = <248000>; +- devbus,rd-setup-ps = <0>; +- devbus,rd-hold-ps = <0>; +- +- /* Write parameters */ +- devbus,sync-enable = <0>; +- devbus,wr-high-ps = <60000>; +- devbus,wr-low-ps = <60000>; +- devbus,ale-wr-ps = <60000>; +- +- nvs@0 { +- status = "okay"; +- +- compatible = "mtd-ram"; +- reg = <0 0x00080000>; +- bank-width = <1>; +- label = "nvs"; +- }; +-}; +- +-&pinctrl { +- i2c0_gpio_pins: i2c-gpio-pins-0 { +- marvell,pins = "mpp2", "mpp3"; +- marvell,function = "gpio"; +- }; +-}; +- +-&i2c0 { +- clock-frequency = <100000>; +- status = "okay"; +- +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-1 = <&i2c0_gpio_pins>; +- scl-gpio = <&gpio0 2 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- sda-gpio = <&gpio0 3 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- +- i2c0mux: mux@71 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "nxp,pca9544"; +- reg = <0x71>; +- i2c-mux-idle-disconnect; +- +- i2c@0 { /* POE devices MUX */ +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- adt7476_2e: hwmon@2e { +- compatible = "adi,adt7476"; +- reg = <0x2e>; +- }; +- +- adt7476_2d: hwmon@2d { +- compatible = "adi,adt7476"; +- reg = <0x2d>; +- }; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- rtc@68 { +- compatible = "dallas,ds1340"; +- reg = <0x68>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- gpio@20 { +- compatible = "nxp,pca9554"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x20>; +- }; +- }; +- }; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins>; +- status = "okay"; +- +- spi-flash@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <1>; /* Chip select 1 */ +- spi-max-frequency = <54000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@u-boot { +- reg = <0x00000000 0x00100000>; +- label = "u-boot"; +- }; +- partition@u-boot-env { +- reg = <0x00100000 0x00040000>; +- label = "u-boot-env"; +- }; +- partition@unused { +- reg = <0x00140000 0x00e80000>; +- label = "unused"; +- }; +- partition@idprom { +- reg = <0x00fc0000 0x00040000>; +- label = "idprom"; +- }; +- }; +- }; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- nand-on-flash-bbt; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- +- marvell,nand-enable-arbiter; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@user { +- reg = <0x00000000 0x0f000000>; +- label = "user"; +- }; +- partition@errlog { +- /* Maximum mtdoops size is 8MB, so set to that. */ +- reg = <0x0f000000 0x00800000>; +- label = "errlog"; +- }; +- partition@nand-bbt { +- reg = <0x0f800000 0x00800000>; +- label = "nand-bbt"; +- }; +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/armada-385-clearfog-gtr-l8.dts b/scripts/dtc/include-prefixes/arm/armada-385-clearfog-gtr-l8.dts +deleted file mode 100644 +index c9ac630e5874..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-385-clearfog-gtr-l8.dts ++++ /dev/null +@@ -1,115 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +- +-#include "armada-385-clearfog-gtr.dtsi" +- +-/ { +- model = "SolidRun Clearfog GTR L8"; +-}; +- +-&mdio { +- switch0: switch0@4 { +- compatible = "marvell,mv88e6190"; +- reg = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cf_gtr_switch_reset_pins>; +- reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <1>; +- label = "lan8"; +- phy-handle = <&switch0phy0>; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan7"; +- phy-handle = <&switch0phy1>; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan6"; +- phy-handle = <&switch0phy2>; +- }; +- +- port@4 { +- reg = <4>; +- label = "lan5"; +- phy-handle = <&switch0phy3>; +- }; +- +- port@5 { +- reg = <5>; +- label = "lan4"; +- phy-handle = <&switch0phy4>; +- }; +- +- port@6 { +- reg = <6>; +- label = "lan3"; +- phy-handle = <&switch0phy5>; +- }; +- +- port@7 { +- reg = <7>; +- label = "lan2"; +- phy-handle = <&switch0phy6>; +- }; +- +- port@8 { +- reg = <8>; +- label = "lan1"; +- phy-handle = <&switch0phy7>; +- }; +- +- port@10 { +- reg = <10>; +- label = "cpu"; +- ethernet = <ð1>; +- }; +- +- }; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch0phy0: switch0phy0@1 { +- reg = <0x1>; +- }; +- +- switch0phy1: switch0phy1@2 { +- reg = <0x2>; +- }; +- +- switch0phy2: switch0phy2@3 { +- reg = <0x3>; +- }; +- +- switch0phy3: switch0phy3@4 { +- reg = <0x4>; +- }; +- +- switch0phy4: switch0phy4@5 { +- reg = <0x5>; +- }; +- +- switch0phy5: switch0phy5@6 { +- reg = <0x6>; +- }; +- +- switch0phy6: switch0phy6@7 { +- reg = <0x7>; +- }; +- +- switch0phy7: switch0phy7@8 { +- reg = <0x8>; +- }; +- }; +- +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-385-clearfog-gtr-s4.dts b/scripts/dtc/include-prefixes/arm/armada-385-clearfog-gtr-s4.dts +deleted file mode 100644 +index fa653b379490..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-385-clearfog-gtr-s4.dts ++++ /dev/null +@@ -1,79 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +- +-#include "armada-385-clearfog-gtr.dtsi" +- +-/ { +- model = "SolidRun Clearfog GTR S4"; +-}; +- +-&sfp0 { +- tx-fault-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>; +-}; +- +-&mdio { +- switch0: switch0@4 { +- compatible = "marvell,mv88e6085"; +- reg = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cf_gtr_switch_reset_pins>; +- reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <1>; +- label = "lan2"; +- phy-handle = <&switch0phy0>; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan1"; +- phy-handle = <&switch0phy1>; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan4"; +- phy-handle = <&switch0phy2>; +- }; +- +- port@4 { +- reg = <4>; +- label = "lan3"; +- phy-handle = <&switch0phy3>; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <ð1>; +- }; +- +- }; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch0phy0: switch0phy0@11 { +- reg = <0x11>; +- }; +- +- switch0phy1: switch0phy1@12 { +- reg = <0x12>; +- }; +- +- switch0phy2: switch0phy2@13 { +- reg = <0x13>; +- }; +- +- switch0phy3: switch0phy3@14 { +- reg = <0x14>; +- }; +- }; +- +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-385-clearfog-gtr.dtsi b/scripts/dtc/include-prefixes/arm/armada-385-clearfog-gtr.dtsi +deleted file mode 100644 +index 624bbcae68c0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-385-clearfog-gtr.dtsi ++++ /dev/null +@@ -1,450 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for Clearfog GTR machines rev 1.0 (88F6825) +- * +- * Rabeeh Khoury , based on Russell King clearfog work +- */ +- +-/* +- SERDES mapping - +- 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0 +- 1. 6141 switch (2.5Gbps capable) +- 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1 +- 3. USB 3.0 Host +- 4. mini PCIe CON2 - PCIe2 +- 5. SFP connector, or optionally SGMII Ethernet 1512 PHY +- +- USB 2.0 mapping - +- 0. USB 2.0 - 0 USB pins header CON12 +- 1. USB 2.0 - 1 mini PCIe CON2 +- 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3) +- +- Pin mapping - +- 0,1 - console UART +- 2,3 - I2C0 - connected to I2C EEPROM, two temperature sensors, +- front panel and PSE controller +- 4,5 - MDC/MDIO +- 6..17 - RGMII +- 18 - Topaz switch reset (active low) +- 19 - 1512 phy reset +- 20 - 1512 phy reset (eth2, optional) +- 21,28,37,38,39,40 - SD0 +- 22 - USB 3.0 current limiter enable (active high) +- 24 - SFP TX fault (input active high) +- 25 - SFP present (input active low) +- 26,27 - I2C1 - connected to SFP +- 29 - Fan PWM +- 30 - CON4 mini PCIe wifi disable +- 31 - CON3 mini PCIe wifi disable +- 32 - Fuse programming power toggle (1.8v) +- 33 - CON4 mini PCIe reset +- 34 - CON2 mini PCIe wifi disable +- 35 - CON3 mini PCIe reset +- 36 - Rear button (GPIO active low) +- 41 - CON1 front panel connector +- 42 - Front LED1, or front panel CON1 +- 43 - Micron L-PBGA 24 ball SPI (1Gb) CS, or TPM SPI CS +- 44 - CON2 mini PCIe reset +- 45 - TPM PIRQ signal, or front panel CON1 +- 46 - SFP TX disable +- 47 - Control isolation of boot sensitive SAR signals +- 48 - PSE reset +- 49 - PSE OSS signal +- 50 - PSE interrupt +- 52 - Front LED2, or front panel +- 53 - Front button +- 54 - SFP LOS (input active high) +- 55 - Fan sense +- 56(mosi),57(clk),58(miso) - SPI interface - 32Mb SPI, 1Gb SPI and TPM +- 59 - SPI 32Mb W25Q32BVZPIG CS0 chip select (bootable) +-*/ +- +-/dts-v1/; +-#include +-#include +-#include +-#include "armada-385.dtsi" +- +-/ { +- compatible = "marvell,armada385", "marvell,armada380"; +- +- aliases { +- /* So that mvebu u-boot can update the MAC addresses */ +- ethernet1 = ð0; +- ethernet2 = ð1; +- ethernet3 = ð2; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; /* 256 MB */ +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_5p0v: regulator-5p0v { +- compatible = "regulator-fixed"; +- regulator-name = "5P0V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- v_usb3_con: regulator-v-usb3-con { +- compatible = "regulator-fixed"; +- gpio = <&gpio0 22 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cf_gtr_usb3_con_vbus>; +- regulator-max-microvolt = <5000000>; +- regulator-min-microvolt = <5000000>; +- regulator-name = "v_usb3_con"; +- vin-supply = <®_5p0v>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- +- rtc@a3800 { +- status = "okay"; +- }; +- +- i2c@11000 { /* ROM, temp sensor and front panel */ +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- +- i2c@11100 { /* SFP (CON5/CON6) */ +- pinctrl-0 = <&cf_gtr_i2c1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- +- pinctrl@18000 { +- cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins { +- marvell,pins = "mpp18"; +- marvell,function = "gpio"; +- }; +- +- cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus { +- marvell,pins = "mpp22"; +- marvell,function = "gpio"; +- }; +- +- cf_gtr_fan_pwm: cf-gtr-fan-pwm { +- marvell,pins = "mpp23"; +- marvell,function = "gpio"; +- }; +- +- cf_gtr_i2c1_pins: i2c1-pins { +- /* SFP */ +- marvell,pins = "mpp26", "mpp27"; +- marvell,function = "i2c1"; +- }; +- +- cf_gtr_sdhci_pins: cf-gtr-sdhci-pins { +- marvell,pins = "mpp21", "mpp28", +- "mpp37", "mpp38", +- "mpp39", "mpp40"; +- marvell,function = "sd0"; +- }; +- +- cf_gtr_isolation_pins: cf-gtr-isolation-pins { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- +- cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins { +- marvell,pins = "mpp48"; +- marvell,function = "gpio"; +- }; +- +- cf_gtr_spi1_cs_pins: spi1-cs-pins { +- marvell,pins = "mpp59"; +- marvell,function = "spi1"; +- }; +- +- cf_gtr_front_button_pins: cf-gtr-front-button-pins { +- marvell,pins = "mpp53"; +- marvell,function = "gpio"; +- }; +- +- cf_gtr_rear_button_pins: cf-gtr-rear-button-pins { +- marvell,pins = "mpp36"; +- marvell,function = "gpio"; +- }; +- }; +- +- sdhci@d8000 { +- bus-width = <4>; +- no-1-8-v; +- non-removable; +- pinctrl-0 = <&cf_gtr_sdhci_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- vmmc = <®_3p3v>; +- wp-inverted; +- }; +- +- usb@58000 { +- status = "okay"; +- }; +- +- usb3@f0000 { +- status = "okay"; +- }; +- +- usb3@f8000 { +- vbus-supply = <&v_usb3_con>; +- status = "okay"; +- }; +- }; +- +- pcie { +- status = "okay"; +- /* +- * The PCIe units are accessible through +- * the mini-PCIe connectors on the board. +- */ +- pcie@1,0 { +- reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; +- status = "okay"; +- }; +- +- pcie@2,0 { +- reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; +- status = "okay"; +- }; +- +- pcie@3,0 { +- reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; +- status = "okay"; +- }; +- }; +- }; +- +- sfp0: sfp { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c1>; +- los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; +- mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>; +- tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>; +- pinctrl-names = "default"; +- +- button_0 { +- label = "Rear Button"; +- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- linux,can-disable; +- linux,code = ; +- }; +- +- button_1 { +- label = "Front Button"; +- gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; +- linux,can-disable; +- linux,code = ; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- led1 { +- function = LED_FUNCTION_CPU; +- color = ; +- gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; +- }; +- +- led2 { +- function = LED_FUNCTION_HEARTBEAT; +- color = ; +- gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&bm { +- status = "okay"; +-}; +- +-&bm_bppi { +- status = "okay"; +-}; +- +-ð0 { +- /* ethernet@70000 */ +- pinctrl-0 = <&ge0_rgmii_pins>; +- pinctrl-names = "default"; +- phy = <&phy_dedicated>; +- phy-mode = "rgmii-id"; +- buffer-manager = <&bm>; +- bm,pool-long = <0>; +- bm,pool-short = <1>; +- status = "okay"; +-}; +- +-ð1 { +- /* ethernet@30000 */ +- bm,pool-long = <2>; +- bm,pool-short = <1>; +- buffer-manager = <&bm>; +- phys = <&comphy1 1>; +- phy-mode = "2500base-x"; +- status = "okay"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- }; +-}; +- +-ð2 { +- /* ethernet@34000 */ +- bm,pool-long = <3>; +- bm,pool-short = <1>; +- buffer-manager = <&bm>; +- managed = "in-band-status"; +- phys = <&comphy5 1>; +- phy-mode = "sgmii"; +- sfp = <&sfp0>; +- status = "okay"; +-}; +- +-&mdio { +- pinctrl-names = "default"; +- pinctrl-0 = <&mdio_pins>; +- status = "okay"; +- +- phy_dedicated: ethernet-phy@0 { +- /* +- * Annoyingly, the marvell phy driver configures the LED +- * register, rather than preserving reset-loaded setting. +- * We undo that rubbish here. +- */ +- marvell,reg-init = <3 16 0 0x1017>; +- reg = <0>; +- }; +-}; +- +-&uart0 { +- pinctrl-0 = <&uart0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&spi1 { +- /* +- * CS0: W25Q32 flash +- */ +- pinctrl-0 = <&spi1_pins &cf_gtr_spi1_cs_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "w25q32", "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <3000000>; +- status = "okay"; +- }; +-}; +- +-&i2c0 { +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- /* U26 temperature sensor placed near SoC */ +- temp1: nct75@4c { +- compatible = "lm75"; +- reg = <0x4c>; +- }; +- +- /* U27 temperature sensor placed near RTC battery */ +- temp2: nct75@4d { +- compatible = "lm75"; +- reg = <0x4d>; +- }; +- +- /* 2Kb eeprom */ +- eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- }; +-}; +- +-&ahci0 { +- status = "okay"; +-}; +- +-&ahci1 { +- status = "okay"; +-}; +- +-&gpio0 { +- pinctrl-0 = <&cf_gtr_fan_pwm>; +- pinctrl-names = "default"; +- +- wifi-disable { +- gpio-hog; +- gpios = <30 GPIO_ACTIVE_LOW>, <31 GPIO_ACTIVE_LOW>; +- output-low; +- line-name = "wifi-disable"; +- }; +-}; +- +-&gpio1 { +- pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>; +- pinctrl-names = "default"; +- +- lte-disable { +- gpio-hog; +- gpios = <2 GPIO_ACTIVE_LOW>; +- output-low; +- line-name = "lte-disable"; +- }; +- +- /* +- * This signal, when asserted, isolates Armada 38x sample at reset pins +- * from control of external devices. Should be de-asserted after reset. +- */ +- sar-isolation { +- gpio-hog; +- gpios = <15 GPIO_ACTIVE_LOW>; +- output-low; +- line-name = "sar-isolation"; +- }; +- +- poe-reset { +- gpio-hog; +- gpios = <16 GPIO_ACTIVE_LOW>; +- output-low; +- line-name = "poe-reset"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-385-db-88f6820-amc.dts b/scripts/dtc/include-prefixes/arm/armada-385-db-88f6820-amc.dts +deleted file mode 100644 +index 7881df3b28a0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-385-db-88f6820-amc.dts ++++ /dev/null +@@ -1,155 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for Marvell Armada 385 AMC board +- * (DB-88F6820-AMC) +- * +- * Copyright (C) 2017 Allied Telesis Labs +- */ +- +-/dts-v1/; +-#include "armada-385.dtsi" +- +-#include +- +-/ { +- model = "Marvell Armada 385 AMC"; +- compatible = "marvell,a385-db-amc", "marvell,armada385", "marvell,armada380"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- ethernet0 = ð0; +- ethernet1 = ð1; +- spi1 = &spi1; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x80000000>; /* 2GB */ +- }; +- +- soc { +- ranges = ; +- }; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +-}; +- +-&uart0 { +- /* +- * Exported on the micro USB connector CON3 +- * through an FTDI +- */ +- +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +- +-ð0 { +- pinctrl-names = "default"; +- /* +- * The Reference Clock 0 is used to provide a +- * clock to the PHY +- */ +- pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +-}; +- +-ð2 { +- status = "okay"; +- phy = <&phy1>; +- phy-mode = "sgmii"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +- +- +-&mdio { +- pinctrl-names = "default"; +- pinctrl-0 = <&mdio_pins>; +- +- phy0: ethernet-phy@1 { +- reg = <1>; +- }; +- +- phy1: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- nand-on-flash-bbt; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- reg = <0x00000000 0x40000000>; +- label = "user"; +- }; +- }; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie1 { +- /* Port 0, Lane 0 */ +- status = "okay"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins>; +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <50000000>; +- m25p,fast-read; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- reg = <0x00000000 0x00100000>; +- label = "u-boot"; +- }; +- partition@100000 { +- reg = <0x00100000 0x00040000>; +- label = "u-boot-env"; +- }; +- }; +- }; +-}; +- +-&refclk { +- clock-frequency = <20000000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-385-db-ap.dts b/scripts/dtc/include-prefixes/arm/armada-385-db-ap.dts +deleted file mode 100644 +index 0e4613bb56ee..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-385-db-ap.dts ++++ /dev/null +@@ -1,238 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for Marvell Armada 385 Access Point Development board +- * (DB-88F6820-AP) +- * +- * Copyright (C) 2014 Marvell +- * +- * Nadav Haklai +- */ +- +-/dts-v1/; +-#include "armada-385.dtsi" +- +-#include +- +-/ { +- model = "Marvell Armada 385 Access Point Development Board"; +- compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380"; +- +- chosen { +- stdout-path = "serial1:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x80000000>; /* 2GB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- i2c0: i2c@11000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +- +- /* +- * This bus is wired to two EEPROM +- * sockets, one of which holding the +- * board ID used by the bootloader. +- * Erasing this EEPROM's content will +- * brick the board. +- * Use this bus with caution. +- */ +- }; +- +- mdio@72004 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mdio_pins>; +- +- phy0: ethernet-phy@1 { +- reg = <1>; +- }; +- +- phy1: ethernet-phy@4 { +- reg = <4>; +- }; +- +- phy2: ethernet-phy@6 { +- reg = <6>; +- }; +- }; +- +- /* UART0 is exposed through the JP8 connector */ +- uart0: serial@12000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +- }; +- +- /* +- * UART1 is exposed through a FTDI chip +- * wired to the mini-USB connector +- */ +- uart1: serial@12100 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- status = "okay"; +- }; +- +- pinctrl@18000 { +- xhci0_vbus_pins: xhci0-vbus-pins { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- }; +- +- /* CON3 */ +- ethernet@30000 { +- status = "okay"; +- phy = <&phy2>; +- phy-mode = "sgmii"; +- buffer-manager = <&bm>; +- bm,pool-long = <1>; +- bm,pool-short = <3>; +- }; +- +- /* CON2 */ +- ethernet@34000 { +- status = "okay"; +- phy = <&phy1>; +- phy-mode = "sgmii"; +- buffer-manager = <&bm>; +- bm,pool-long = <2>; +- bm,pool-short = <3>; +- }; +- +- usb@58000 { +- status = "okay"; +- }; +- +- /* CON4 */ +- ethernet@70000 { +- pinctrl-names = "default"; +- +- /* +- * The Reference Clock 0 is used to +- * provide a clock to the PHY +- */ +- pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +- buffer-manager = <&bm>; +- bm,pool-long = <0>; +- bm,pool-short = <3>; +- }; +- +- bm@c8000 { +- status = "okay"; +- }; +- +- usb3@f0000 { +- status = "okay"; +- usb-phy = <&usb3_phy>; +- }; +- }; +- +- bm-bppi { +- status = "okay"; +- }; +- +- pcie { +- status = "okay"; +- +- /* +- * The three PCIe units are accessible through +- * standard mini-PCIe slots on the board. +- */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- +- pcie@2,0 { +- /* Port 1, Lane 0 */ +- status = "okay"; +- }; +- +- pcie@3,0 { +- /* Port 2, Lane 0 */ +- status = "okay"; +- }; +- }; +- }; +- +- usb3_phy: usb3_phy { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <®_xhci0_vbus>; +- #phy-cells = <0>; +- }; +- +- reg_xhci0_vbus: xhci0-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&xhci0_vbus_pins>; +- regulator-name = "xhci0-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins>; +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p128", "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <54000000>; +- }; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- nand-on-flash-bbt; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0x00000000 0x00800000>; +- read-only; +- }; +- +- partition@800000 { +- label = "uImage"; +- reg = <0x00800000 0x00400000>; +- read-only; +- }; +- +- partition@c00000 { +- label = "Root"; +- reg = <0x00c00000 0x3f400000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-385-linksys-caiman.dts b/scripts/dtc/include-prefixes/arm/armada-385-linksys-caiman.dts +deleted file mode 100644 +index a03050c97084..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-385-linksys-caiman.dts ++++ /dev/null +@@ -1,144 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree include for the Linksys WRT1200AC (Caiman) +- * +- * Copyright (C) 2015 Imre Kaloz +- */ +- +-/dts-v1/; +-#include "armada-385-linksys.dtsi" +- +-/ { +- model = "Linksys WRT1200AC"; +- compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385", +- "marvell,armada380"; +-}; +- +-&expander0 { +- wan_amber@0 { +- label = "caiman:amber:wan"; +- reg = <0x0>; +- }; +- +- wan_white@1 { +- label = "caiman:white:wan"; +- reg = <0x1>; +- }; +- +- wlan_2g@2 { +- label = "caiman:white:wlan_2g"; +- reg = <0x2>; +- }; +- +- wlan_5g@3 { +- label = "caiman:white:wlan_5g"; +- reg = <0x3>; +- }; +- +- usb2@5 { +- label = "caiman:white:usb2"; +- reg = <0x5>; +- }; +- +- usb3_1@6 { +- label = "caiman:white:usb3_1"; +- reg = <0x6>; +- }; +- +- usb3_2@7 { +- label = "caiman:white:usb3_2"; +- reg = <0x7>; +- }; +- +- wps_white@8 { +- label = "caiman:white:wps"; +- reg = <0x8>; +- }; +- +- wps_amber@9 { +- label = "caiman:amber:wps"; +- reg = <0x9>; +- }; +-}; +- +-&gpio_leds { +- power { +- label = "caiman:white:power"; +- }; +- +- sata { +- label = "caiman:white:sata"; +- }; +-}; +- +-&nand { +- /* 128MiB */ +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x200000>; /* 2MiB */ +- read-only; +- }; +- +- partition@100000 { +- label = "u_env"; +- reg = <0x200000 0x40000>; /* 256KiB */ +- }; +- +- partition@140000 { +- label = "s_env"; +- reg = <0x240000 0x40000>; /* 256KiB */ +- }; +- +- partition@900000 { +- label = "devinfo"; +- reg = <0x900000 0x100000>; /* 1MiB */ +- read-only; +- }; +- +- /* kernel1 overlaps with rootfs1 by design */ +- partition@a00000 { +- label = "kernel1"; +- reg = <0xa00000 0x2800000>; /* 40MiB */ +- }; +- +- partition@1000000 { +- label = "rootfs1"; +- reg = <0x1000000 0x2200000>; /* 34MiB */ +- }; +- +- /* kernel2 overlaps with rootfs2 by design */ +- partition@3200000 { +- label = "kernel2"; +- reg = <0x3200000 0x2800000>; /* 40MiB */ +- }; +- +- partition@3800000 { +- label = "rootfs2"; +- reg = <0x3800000 0x2200000>; /* 34MiB */ +- }; +- +- /* +- * 38MiB, last MiB is for the BBT, not writable +- */ +- partition@5a00000 { +- label = "syscfg"; +- reg = <0x5a00000 0x2600000>; +- }; +- +- /* +- * Unused area between "s_env" and "devinfo". +- * Moved here because otherwise the renumbered +- * partitions would break the bootloader +- * supplied bootargs +- */ +- partition@180000 { +- label = "unused_area"; +- reg = <0x280000 0x680000>; /* 6.5MiB */ +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-385-linksys-cobra.dts b/scripts/dtc/include-prefixes/arm/armada-385-linksys-cobra.dts +deleted file mode 100644 +index e3e4877a6f49..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-385-linksys-cobra.dts ++++ /dev/null +@@ -1,144 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for the Linksys WRT1900ACv2 (Cobra) +- * +- * Copyright (C) 2015 Imre Kaloz +- */ +- +-/dts-v1/; +-#include "armada-385-linksys.dtsi" +- +-/ { +- model = "Linksys WRT1900ACv2"; +- compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385", +- "marvell,armada380"; +-}; +- +-&expander0 { +- wan_amber@0 { +- label = "cobra:amber:wan"; +- reg = <0x0>; +- }; +- +- wan_white@1 { +- label = "cobra:white:wan"; +- reg = <0x1>; +- }; +- +- wlan_2g@2 { +- label = "cobra:white:wlan_2g"; +- reg = <0x2>; +- }; +- +- wlan_5g@3 { +- label = "cobra:white:wlan_5g"; +- reg = <0x3>; +- }; +- +- usb2@5 { +- label = "cobra:white:usb2"; +- reg = <0x5>; +- }; +- +- usb3_1@6 { +- label = "cobra:white:usb3_1"; +- reg = <0x6>; +- }; +- +- usb3_2@7 { +- label = "cobra:white:usb3_2"; +- reg = <0x7>; +- }; +- +- wps_white@8 { +- label = "cobra:white:wps"; +- reg = <0x8>; +- }; +- +- wps_amber@9 { +- label = "cobra:amber:wps"; +- reg = <0x9>; +- }; +-}; +- +-&gpio_leds { +- power { +- label = "cobra:white:power"; +- }; +- +- sata { +- label = "cobra:white:sata"; +- }; +-}; +- +-&nand { +- /* 128MiB */ +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x200000>; /* 2MiB */ +- read-only; +- }; +- +- partition@100000 { +- label = "u_env"; +- reg = <0x200000 0x40000>; /* 256KiB */ +- }; +- +- partition@140000 { +- label = "s_env"; +- reg = <0x240000 0x40000>; /* 256KiB */ +- }; +- +- partition@900000 { +- label = "devinfo"; +- reg = <0x900000 0x100000>; /* 1MiB */ +- read-only; +- }; +- +- /* kernel1 overlaps with rootfs1 by design */ +- partition@a00000 { +- label = "kernel1"; +- reg = <0xa00000 0x2800000>; /* 40MiB */ +- }; +- +- partition@1000000 { +- label = "rootfs1"; +- reg = <0x1000000 0x2200000>; /* 34MiB */ +- }; +- +- /* kernel2 overlaps with rootfs2 by design */ +- partition@3200000 { +- label = "kernel2"; +- reg = <0x3200000 0x2800000>; /* 40MiB */ +- }; +- +- partition@3800000 { +- label = "rootfs2"; +- reg = <0x3800000 0x2200000>; /* 34MiB */ +- }; +- +- /* +- * 38MiB, last MiB is for the BBT, not writable +- */ +- partition@5a00000 { +- label = "syscfg"; +- reg = <0x5a00000 0x2600000>; +- }; +- +- /* +- * Unused area between "s_env" and "devinfo". +- * Moved here because otherwise the renumbered +- * partitions would break the bootloader +- * supplied bootargs +- */ +- partition@180000 { +- label = "unused_area"; +- reg = <0x280000 0x680000>; /* 6.5MiB */ +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-385-linksys-rango.dts b/scripts/dtc/include-prefixes/arm/armada-385-linksys-rango.dts +deleted file mode 100644 +index 3c4af57ec2b9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-385-linksys-rango.dts ++++ /dev/null +@@ -1,176 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for the Linksys WRT3200ACM (Rango) +- * +- * Copyright (C) 2016 Imre Kaloz +- */ +- +-/dts-v1/; +-#include +-#include +-#include "armada-385-linksys.dtsi" +- +-/ { +- model = "Linksys WRT3200ACM"; +- compatible = "linksys,rango", "linksys,armada385", "marvell,armada385", +- "marvell,armada380"; +-}; +- +-&expander0 { +- wan_amber@0 { +- label = "rango:amber:wan"; +- reg = <0x0>; +- }; +- +- wan_white@1 { +- label = "rango:white:wan"; +- reg = <0x1>; +- }; +- +- usb2@5 { +- label = "rango:white:usb2"; +- reg = <0x5>; +- }; +- +- usb3_1@6 { +- label = "rango:white:usb3_1"; +- reg = <0x6>; +- }; +- +- usb3_2@7 { +- label = "rango:white:usb3_2"; +- reg = <0x7>; +- }; +- +- wps_white@8 { +- label = "rango:white:wps"; +- reg = <0x8>; +- }; +- +- wps_amber@9 { +- label = "rango:amber:wps"; +- reg = <0x9>; +- }; +-}; +- +-&gpio_leds { +- power { +- gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; +- label = "rango:white:power"; +- }; +- +- sata { +- gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; +- label = "rango:white:sata"; +- }; +- +- wlan_2g { +- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; +- label = "rango:white:wlan_2g"; +- }; +- +- wlan_5g { +- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- label = "rango:white:wlan_5g"; +- }; +-}; +- +-&gpio_leds_pins { +- marvell,pins = "mpp21", "mpp45", "mpp46", "mpp56"; +-}; +- +-&nand { +- /* AMD/Spansion S34ML02G2 256MiB, OEM Layout */ +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x200000>; /* 2MiB */ +- read-only; +- }; +- +- partition@200000 { +- label = "u_env"; +- reg = <0x200000 0x20000>; /* 128KiB */ +- }; +- +- partition@220000 { +- label = "s_env"; +- reg = <0x220000 0x40000>; /* 256KiB */ +- }; +- +- partition@7e0000 { +- label = "devinfo"; +- reg = <0x7e0000 0x40000>; /* 256KiB */ +- read-only; +- }; +- +- partition@820000 { +- label = "sysdiag"; +- reg = <0x820000 0x1e0000>; /* 1920KiB */ +- read-only; +- }; +- +- /* kernel1 overlaps with rootfs1 by design */ +- partition@a00000 { +- label = "kernel1"; +- reg = <0xa00000 0x5000000>; /* 80MiB */ +- }; +- +- partition@1000000 { +- label = "rootfs1"; +- reg = <0x1000000 0x4a00000>; /* 74MiB */ +- }; +- +- /* kernel2 overlaps with rootfs2 by design */ +- partition@5a00000 { +- label = "kernel2"; +- reg = <0x5a00000 0x5000000>; /* 80MiB */ +- }; +- +- partition@6000000 { +- label = "rootfs2"; +- reg = <0x6000000 0x4a00000>; /* 74MiB */ +- }; +- +- /* +- * 86MiB, last MiB is for the BBT, not writable +- */ +- partition@aa00000 { +- label = "syscfg"; +- reg = <0xaa00000 0x5600000>; +- }; +- +- /* +- * Unused area between "s_env" and "devinfo". +- * Moved here because otherwise the renumbered +- * partitions would break the bootloader +- * supplied bootargs +- */ +- partition@180000 { +- label = "unused_area"; +- reg = <0x260000 0x5c0000>; /* 5.75MiB */ +- }; +- }; +-}; +- +-&sdhci { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhci_pins>; +- no-1-8-v; +- non-removable; +- wp-inverted; +- bus-width = <8>; +- status = "okay"; +-}; +- +-&usb3_1_vbus { +- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; +-}; +- +-&usb3_1_vbus_pins { +- marvell,pins = "mpp44"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-385-linksys-shelby.dts b/scripts/dtc/include-prefixes/arm/armada-385-linksys-shelby.dts +deleted file mode 100644 +index 3451cd3e5dff..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-385-linksys-shelby.dts ++++ /dev/null +@@ -1,144 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for the Linksys WRT1900ACS (Shelby) +- * +- * Copyright (C) 2015 Imre Kaloz +- */ +- +-/dts-v1/; +-#include "armada-385-linksys.dtsi" +- +-/ { +- model = "Linksys WRT1900ACS"; +- compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385", +- "marvell,armada380"; +-}; +- +-&expander0 { +- wan_amber@0 { +- label = "shelby:amber:wan"; +- reg = <0x0>; +- }; +- +- wan_white@1 { +- label = "shelby:white:wan"; +- reg = <0x1>; +- }; +- +- wlan_2g@2 { +- label = "shelby:white:wlan_2g"; +- reg = <0x2>; +- }; +- +- wlan_5g@3 { +- label = "shelby:white:wlan_5g"; +- reg = <0x3>; +- }; +- +- usb2@5 { +- label = "shelby:white:usb2"; +- reg = <0x5>; +- }; +- +- usb3_1@6 { +- label = "shelby:white:usb3_1"; +- reg = <0x6>; +- }; +- +- usb3_2@7 { +- label = "shelby:white:usb3_2"; +- reg = <0x7>; +- }; +- +- wps_white@8 { +- label = "shelby:white:wps"; +- reg = <0x8>; +- }; +- +- wps_amber@9 { +- label = "shelby:amber:wps"; +- reg = <0x9>; +- }; +-}; +- +-&gpio_leds { +- power { +- label = "shelby:white:power"; +- }; +- +- sata { +- label = "shelby:white:sata"; +- }; +-}; +- +-&nand { +- /* 128MiB */ +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x200000>; /* 2MiB */ +- read-only; +- }; +- +- partition@100000 { +- label = "u_env"; +- reg = <0x200000 0x40000>; /* 256KiB */ +- }; +- +- partition@140000 { +- label = "s_env"; +- reg = <0x240000 0x40000>; /* 256KiB */ +- }; +- +- partition@900000 { +- label = "devinfo"; +- reg = <0x900000 0x100000>; /* 1MiB */ +- read-only; +- }; +- +- /* kernel1 overlaps with rootfs1 by design */ +- partition@a00000 { +- label = "kernel1"; +- reg = <0xa00000 0x2800000>; /* 40MiB */ +- }; +- +- partition@1000000 { +- label = "rootfs1"; +- reg = <0x1000000 0x2200000>; /* 34MiB */ +- }; +- +- /* kernel2 overlaps with rootfs2 by design */ +- partition@3200000 { +- label = "kernel2"; +- reg = <0x3200000 0x2800000>; /* 40MiB */ +- }; +- +- partition@3800000 { +- label = "rootfs2"; +- reg = <0x3800000 0x2200000>; /* 34MiB */ +- }; +- +- /* +- * 38MiB, last MiB is for the BBT, not writable +- */ +- partition@5a00000 { +- label = "syscfg"; +- reg = <0x5a00000 0x2600000>; +- }; +- +- /* +- * Unused area between "s_env" and "devinfo". +- * Moved here because otherwise the renumbered +- * partitions would break the bootloader +- * supplied bootargs +- */ +- partition@180000 { +- label = "unused_area"; +- reg = <0x280000 0x680000>; /* 6.5MiB */ +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-385-linksys.dtsi b/scripts/dtc/include-prefixes/arm/armada-385-linksys.dtsi +deleted file mode 100644 +index fb9c8a0b241c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-385-linksys.dtsi ++++ /dev/null +@@ -1,265 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree include file for Armada 385 based Linksys boards +- * +- * Copyright (C) 2015 Imre Kaloz +- */ +- +-#include +-#include +-#include "armada-385.dtsi" +- +-/ { +- model = "Linksys boards based on Armada 385"; +- compatible = "linksys,armada385", "marvell,armada385", +- "marvell,armada380"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; /* 512 MiB */ +- }; +- +- soc { +- ranges = ; +- }; +- +- usb3_1_phy: usb3_1-phy { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <&usb3_1_vbus>; +- #phy-cells = <0>; +- }; +- +- usb3_1_vbus: usb3_1-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb3_1_vbus_pins>; +- regulator-name = "usb3_1-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; +- }; +- +- gpio_keys: gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&gpio_keys_pins>; +- pinctrl-names = "default"; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; +- }; +- +- reset { +- label = "Factory Reset Button"; +- linux,code = ; +- gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio_leds: gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&gpio_leds_pins>; +- pinctrl-names = "default"; +- +- power { +- gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- sata { +- gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- linux,default-trigger = "disk-activity"; +- }; +- }; +-}; +- +-&ahci0 { +- status = "okay"; +-}; +- +-&bm { +- status = "okay"; +-}; +- +-&bm_bppi { +- status = "okay"; +-}; +- +-ð0 { +- status = "okay"; +- phy-mode = "rgmii-id"; +- buffer-manager = <&bm>; +- bm,pool-long = <0>; +- bm,pool-short = <1>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +-}; +- +-ð2 { +- status = "okay"; +- phy-mode = "sgmii"; +- buffer-manager = <&bm>; +- bm,pool-long = <2>; +- bm,pool-short = <3>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +- +- tmp421@4c { +- compatible = "ti,tmp421"; +- reg = <0x4c>; +- }; +- +- expander0: pca9635@68 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "nxp,pca9635"; +- reg = <0x68>; +- }; +-}; +- +-&nand_controller { +- /* 128MiB or 256MiB */ +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- nand: nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- marvell,nand-keep-config; +- nand-on-flash-bbt; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- switch@0 { +- compatible = "marvell,mv88e6085"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan4"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan3"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan1"; +- }; +- +- port@4 { +- reg = <4>; +- label = "wan"; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <ð2>; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie1 { +- /* Marvell 88W8864, 5GHz-only */ +- status = "okay"; +-}; +- +-&pcie2 { +- /* Marvell 88W8864, 2GHz-only */ +- status = "okay"; +-}; +- +-&pinctrl { +- gpio_keys_pins: gpio-keys-pins { +- /* mpp24: wps, mpp29: reset */ +- marvell,pins = "mpp24", "mpp29"; +- marvell,function = "gpio"; +- }; +- +- gpio_leds_pins: gpio-leds-pins { +- /* mpp54: sata, mpp55: power */ +- marvell,pins = "mpp54", "mpp55"; +- marvell,function = "gpio"; +- }; +- +- usb3_1_vbus_pins: usb3_1-vbus-pins { +- marvell,pins = "mpp50"; +- marvell,function = "gpio"; +- }; +-}; +- +-&spi0 { +- status = "disabled"; +-}; +- +-&uart0 { +- /* J10: VCC, NC, RX, NC, TX, GND */ +- status = "okay"; +-}; +- +-&usb0 { +- /* USB part of the eSATA/USB 2.0 port */ +- status = "okay"; +-}; +- +-&usb3_1 { +- status = "okay"; +- usb-phy = <&usb3_1_phy>; +-}; +- +-&rtc { +- /* No crystal connected to the internal RTC */ +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-385-synology-ds116.dts b/scripts/dtc/include-prefixes/arm/armada-385-synology-ds116.dts +deleted file mode 100644 +index d8769956cbfc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-385-synology-ds116.dts ++++ /dev/null +@@ -1,292 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for Synology DS116 NAS +- * +- * Copyright (C) 2017 Willy Tarreau +- */ +- +-/dts-v1/; +-#include "armada-385.dtsi" +-#include +- +-/ { +- model = "Synology DS116"; +- compatible = "marvell,a385-gp", "marvell,armada385", "marvell,armada380"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x40000000>; /* 1 GB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- i2c@11000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +- clock-frequency = <100000>; +- +- eeprom@57 { +- compatible = "atmel,24c64"; +- reg = <0x57>; +- }; +- }; +- +- serial@12000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +- }; +- +- serial@12100 { +- /* A PIC16F1829 is connected to uart1 at 9600 bps, +- * and takes single-character orders : +- * "1" : power off // already handled by the poweroff node +- * "2" : short beep +- * "3" : long beep +- * "4" : turn the power LED ON +- * "5" : flash the power LED +- * "6" : turn the power LED OFF +- * "7" : turn the status LED OFF +- * "8" : turn the status LED ON +- * "9" : flash the status LED +- * "A" : flash the motherboard LED (D8) +- * "B" : turn the motherboard LED OFF +- * "C" : hard reset +- */ +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- status = "okay"; +- }; +- +- poweroff@12100 { +- compatible = "synology,power-off"; +- reg = <0x12100 0x100>; +- clocks = <&coreclk 0>; +- }; +- +- ethernet@70000 { +- pinctrl-names = "default"; +- phy = <&phy0>; +- phy-mode = "sgmii"; +- buffer-manager = <&bm>; +- bm,pool-long = <0>; +- status = "okay"; +- }; +- +- +- mdio@72004 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mdio_pins>; +- +- phy0: ethernet-phy@1 { +- reg = <1>; +- }; +- }; +- +- sata@a8000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sata0_pins>; +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- sata0: sata-port@0 { +- reg = <0>; +- target-supply = <®_5v_sata0>; +- }; +- }; +- +- bm@c8000 { +- status = "okay"; +- }; +- +- usb3@f0000 { +- usb-phy = <&usb3_0_phy>; +- status = "okay"; +- }; +- +- usb3@f8000 { +- usb-phy = <&usb3_1_phy>; +- status = "okay"; +- }; +- }; +- +- bm-bppi { +- status = "okay"; +- }; +- +- gpio-fan { +- compatible = "gpio-fan"; +- gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>, +- <&gpio1 17 GPIO_ACTIVE_HIGH>, +- <&gpio1 16 GPIO_ACTIVE_HIGH>; +- gpio-fan,speed-map = < 0 0 +- 1500 1 +- 2500 2 +- 3000 3 +- 3400 4 +- 3700 5 +- 3900 6 +- 4000 7>; +- #cooling-cells = <2>; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- /* The green part is on gpio0.20 which is also used by +- * sata0, and accesses to SATA disk 0 make it blink so it +- * doesn't need to be declared here. +- */ +- orange { +- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; +- label = "ds116:orange:disk"; +- default-state = "off"; +- }; +- }; +- }; +- +- usb3_0_phy: usb3_0_phy { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <®_usb3_0_vbus>; +- #phy-cells = <0>; +- }; +- +- usb3_1_phy: usb3_1_phy { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <®_usb3_1_vbus>; +- #phy-cells = <0>; +- }; +- +- reg_usb3_0_vbus: usb3-vbus0 { +- compatible = "regulator-fixed"; +- regulator-name = "usb3-vbus0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&xhci0_vbus_pins>; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_usb3_1_vbus: usb3-vbus1 { +- compatible = "regulator-fixed"; +- regulator-name = "usb3-vbus1"; +- pinctrl-names = "default"; +- pinctrl-0 = <&xhci1_vbus_pins>; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_sata0: pwr-sata0 { +- compatible = "regulator-fixed"; +- regulator-name = "pwr_en_sata0"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- enable-active-high; +- regulator-boot-on; +- gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_5v_sata0: v5-sata0 { +- compatible = "regulator-fixed"; +- regulator-name = "v5.0-sata0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <®_sata0>; +- }; +- +- reg_12v_sata0: v12-sata0 { +- compatible = "regulator-fixed"; +- regulator-name = "v12.0-sata0"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- vin-supply = <®_sata0>; +- }; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins>; +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "macronix,mx25l6405d", "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <50000000>; +- m25p,fast-read; +- +- /* Note: there is a redboot partition table despite u-boot +- * being used. The names presented here are the same as those +- * found in the FIS directory. There is also a small device +- * tree in the last 64kB of the RedBoot partition which is not +- * enumerated. The MAC address and the serial number are listed +- * in the "vendor" partition. +- */ +- partition@0 { +- label = "RedBoot"; +- reg = <0x00000000 0x000f0000>; +- read-only; +- }; +- +- partition@c0000 { +- label = "zImage"; +- reg = <0x000f0000 0x002d0000>; +- }; +- +- partition@390000 { +- label = "rd.gz"; +- reg = <0x003c0000 0x00410000>; +- }; +- +- partition@7d0000 { +- label = "vendor"; +- reg = <0x007d0000 0x00010000>; +- read-only; +- }; +- +- partition@7e0000 { +- label = "RedBoot config"; +- reg = <0x007e0000 0x00010000>; +- read-only; +- }; +- +- partition@7f0000 { +- label = "FIS directory"; +- reg = <0x007f0000 0x00010000>; +- read-only; +- }; +- }; +-}; +- +-&pinctrl { +- /* use only one pin for UART1, as mpp20 is used by sata0 */ +- uart1_pins: uart-pins-1 { +- marvell,pins = "mpp19"; +- marvell,function = "ua1"; +- }; +- +- xhci0_vbus_pins: xhci0_vbus_pins { +- marvell,pins = "mpp58"; +- marvell,function = "gpio"; +- }; +- xhci1_vbus_pins: xhci1_vbus_pins { +- marvell,pins = "mpp59"; +- marvell,function = "gpio"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-385-turris-omnia.dts b/scripts/dtc/include-prefixes/arm/armada-385-turris-omnia.dts +deleted file mode 100644 +index 5bd6a66d2c2b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-385-turris-omnia.dts ++++ /dev/null +@@ -1,524 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for the Turris Omnia +- * +- * Copyright (C) 2016 Uwe Kleine-König +- * Copyright (C) 2016 Tomas Hlavacek +- * +- * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include "armada-385.dtsi" +- +-/ { +- model = "Turris Omnia"; +- compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380"; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x40000000>; /* 1024 MB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- +- /* USB part of the PCIe2/USB 2.0 port */ +- usb@58000 { +- status = "okay"; +- }; +- +- sata@a8000 { +- status = "okay"; +- }; +- +- sdhci@d8000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhci_pins>; +- status = "okay"; +- +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- }; +- +- usb3@f0000 { +- status = "okay"; +- }; +- +- usb3@f8000 { +- status = "okay"; +- }; +- }; +- +- pcie { +- status = "okay"; +- +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- +- pcie@2,0 { +- /* Port 1, Lane 0 */ +- status = "okay"; +- }; +- +- pcie@3,0 { +- /* Port 2, Lane 0 */ +- status = "okay"; +- }; +- }; +- }; +- +- sfp: sfp { +- compatible = "sff,sfp"; +- i2c-bus = <&sfp_i2c>; +- tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>; +- tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>; +- rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>; +- los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>; +- maximum-power-milliwatt = <3000>; +- +- /* +- * For now this has to be enabled at boot time by U-Boot when +- * a SFP module is present. Read more in the comment in the +- * eth2 node below. +- */ +- status = "disabled"; +- }; +-}; +- +-&bm { +- status = "okay"; +-}; +- +-&bm_bppi { +- status = "okay"; +-}; +- +-/* Connected to 88E6176 switch, port 6 */ +-ð0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ge0_rgmii_pins>; +- status = "okay"; +- phy-mode = "rgmii"; +- buffer-manager = <&bm>; +- bm,pool-long = <0>; +- bm,pool-short = <3>; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +-}; +- +-/* Connected to 88E6176 switch, port 5 */ +-ð1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ge1_rgmii_pins>; +- status = "okay"; +- phy-mode = "rgmii"; +- buffer-manager = <&bm>; +- bm,pool-long = <1>; +- bm,pool-short = <3>; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +-}; +- +-/* WAN port */ +-ð2 { +- /* +- * eth2 is connected via a multiplexor to both the SFP cage and to +- * ethernet-phy@1. The multiplexor switches the signal to SFP cage when +- * a SFP module is present, as determined by the mode-def0 GPIO. +- * +- * Until kernel supports this configuration properly, in case SFP module +- * is present, U-Boot has to enable the sfp node above, remove phy +- * handle and add managed = "in-band-status" property. +- */ +- status = "okay"; +- phy-mode = "sgmii"; +- phy-handle = <&phy1>; +- phys = <&comphy5 2>; +- sfp = <&sfp>; +- buffer-manager = <&bm>; +- bm,pool-long = <2>; +- bm,pool-short = <3>; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +- +- i2cmux@70 { +- compatible = "nxp,pca9547"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- /* STM32F0 command interface at address 0x2a */ +- +- led-controller@2b { +- compatible = "cznic,turris-omnia-leds"; +- reg = <0x2b>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* +- * LEDs are controlled by MCU (STM32F0) at +- * address 0x2b. +- * +- * The driver does not support HW control mode +- * for the LEDs yet. Disable the LEDs for now. +- * +- * Also LED functions are not stable yet: +- * - there are 3 LEDs connected via MCU to PCIe +- * ports. One of these ports supports mSATA. +- * There is no mSATA nor PCIe function. +- * For now we use LED_FUNCTION_WLAN, since +- * in most cases users have wifi cards in +- * these slots +- * - there are 2 LEDs dedicated for user: A and +- * B. Again there is no such function defined. +- * For now we use LED_FUNCTION_INDICATOR +- */ +- status = "disabled"; +- +- multi-led@0 { +- reg = <0x0>; +- color = ; +- function = LED_FUNCTION_INDICATOR; +- function-enumerator = <2>; +- }; +- +- multi-led@1 { +- reg = <0x1>; +- color = ; +- function = LED_FUNCTION_INDICATOR; +- function-enumerator = <1>; +- }; +- +- multi-led@2 { +- reg = <0x2>; +- color = ; +- function = LED_FUNCTION_WLAN; +- function-enumerator = <3>; +- }; +- +- multi-led@3 { +- reg = <0x3>; +- color = ; +- function = LED_FUNCTION_WLAN; +- function-enumerator = <2>; +- }; +- +- multi-led@4 { +- reg = <0x4>; +- color = ; +- function = LED_FUNCTION_WLAN; +- function-enumerator = <1>; +- }; +- +- multi-led@5 { +- reg = <0x5>; +- color = ; +- function = LED_FUNCTION_WAN; +- }; +- +- multi-led@6 { +- reg = <0x6>; +- color = ; +- function = LED_FUNCTION_LAN; +- function-enumerator = <4>; +- }; +- +- multi-led@7 { +- reg = <0x7>; +- color = ; +- function = LED_FUNCTION_LAN; +- function-enumerator = <3>; +- }; +- +- multi-led@8 { +- reg = <0x8>; +- color = ; +- function = LED_FUNCTION_LAN; +- function-enumerator = <2>; +- }; +- +- multi-led@9 { +- reg = <0x9>; +- color = ; +- function = LED_FUNCTION_LAN; +- function-enumerator = <1>; +- }; +- +- multi-led@a { +- reg = <0xa>; +- color = ; +- function = LED_FUNCTION_LAN; +- function-enumerator = <0>; +- }; +- +- multi-led@b { +- reg = <0xb>; +- color = ; +- function = LED_FUNCTION_POWER; +- }; +- }; +- +- eeprom@54 { +- compatible = "atmel,24c64"; +- reg = <0x54>; +- +- /* The EEPROM contains data for bootloader. +- * Contents: +- * struct omnia_eeprom { +- * u32 magic; (=0x0341a034 in LE) +- * u32 ramsize; (in GiB) +- * char regdomain[4]; +- * u32 crc32; +- * }; +- */ +- }; +- }; +- +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- /* routed to PCIe0/mSATA connector (CN7A) */ +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- /* routed to PCIe1/USB2 connector (CN61A) */ +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- /* routed to PCIe2 connector (CN62A) */ +- }; +- +- sfp_i2c: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- +- /* routed to SFP+ */ +- }; +- +- i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- +- /* ATSHA204A at address 0x64 */ +- }; +- +- i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- +- /* exposed on pin header */ +- }; +- +- i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- +- pcawan: gpio@71 { +- /* +- * GPIO expander for SFP+ signals and +- * and phy irq +- */ +- compatible = "nxp,pca9538"; +- reg = <0x71>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pcawan_pins>; +- +- interrupt-parent = <&gpio1>; +- interrupts = <14 IRQ_TYPE_LEVEL_LOW>; +- +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +- }; +-}; +- +-&mdio { +- pinctrl-names = "default"; +- pinctrl-0 = <&mdio_pins>; +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- marvell,reg-init = <3 18 0 0x4985>; +- +- /* irq is connected to &pcawan pin 7 */ +- }; +- +- /* Switch MV88E6176 at address 0x10 */ +- switch@10 { +- pinctrl-names = "default"; +- pinctrl-0 = <&swint_pins>; +- compatible = "marvell,mv88e6085"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- dsa,member = <0 0>; +- reg = <0x10>; +- +- interrupt-parent = <&gpio1>; +- interrupts = <13 IRQ_TYPE_LEVEL_LOW>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports@0 { +- reg = <0>; +- label = "lan0"; +- }; +- +- ports@1 { +- reg = <1>; +- label = "lan1"; +- }; +- +- ports@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- ports@3 { +- reg = <3>; +- label = "lan3"; +- }; +- +- ports@4 { +- reg = <4>; +- label = "lan4"; +- }; +- +- ports@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <ð1>; +- phy-mode = "rgmii-id"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- /* port 6 is connected to eth0 */ +- }; +- }; +-}; +- +-&pinctrl { +- pcawan_pins: pcawan-pins { +- marvell,pins = "mpp46"; +- marvell,function = "gpio"; +- }; +- +- swint_pins: swint-pins { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- +- spi0cs0_pins: spi0cs0-pins { +- marvell,pins = "mpp25"; +- marvell,function = "spi0"; +- }; +- +- spi0cs1_pins: spi0cs1-pins { +- marvell,pins = "mpp26"; +- marvell,function = "spi0"; +- }; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins &spi0cs0_pins>; +- status = "okay"; +- +- spi-nor@0 { +- compatible = "spansion,s25fl164k", "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- spi-max-frequency = <40000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- reg = <0x0 0x00100000>; +- label = "U-Boot"; +- }; +- +- partition@100000 { +- reg = <0x00100000 0x00700000>; +- label = "Rescue system"; +- }; +- }; +- }; +- +- /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */ +-}; +- +-&uart0 { +- /* Pin header CN10 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- /* Pin header CN11 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-385.dtsi b/scripts/dtc/include-prefixes/arm/armada-385.dtsi +deleted file mode 100644 +index f0022d10c715..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-385.dtsi ++++ /dev/null +@@ -1,149 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell Armada 385 SoC. +- * +- * Copyright (C) 2014 Marvell +- * +- * Lior Amsalem +- * Gregory CLEMENT +- * Thomas Petazzoni +- */ +- +-#include "armada-38x.dtsi" +- +-/ { +- model = "Marvell Armada 385 family SoC"; +- compatible = "marvell,armada385", "marvell,armada380"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "marvell,armada-380-smp"; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- }; +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <1>; +- }; +- }; +- +- soc { +- pciec: pcie { +- compatible = "marvell,armada-370-pcie"; +- status = "disabled"; +- device_type = "pci"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- msi-parent = <&mpic>; +- bus-range = <0x00 0xff>; +- +- ranges = +- <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 +- 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 +- 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 +- 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 +- 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ +- 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ +- 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ +- 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ +- 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ +- 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ +- 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ +- 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; +- +- /* +- * This port can be either x4 or x1. When +- * configured in x4 by the bootloader, then +- * pcie@4,0 is not available. +- */ +- pcie1: pcie@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 +- 0x81000000 0 0 0x81000000 0x1 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 8>; +- status = "disabled"; +- }; +- +- /* x1 port */ +- pcie2: pcie@2,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; +- reg = <0x1000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 +- 0x81000000 0 0 0x81000000 0x2 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 5>; +- status = "disabled"; +- }; +- +- /* x1 port */ +- pcie3: pcie@3,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; +- reg = <0x1800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 +- 0x81000000 0 0 0x81000000 0x3 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; +- marvell,pcie-port = <2>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 6>; +- status = "disabled"; +- }; +- +- /* +- * x1 port only available when pcie@1,0 is +- * configured as a x1 port +- */ +- pcie4: pcie@4,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; +- reg = <0x2000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 +- 0x81000000 0 0 0x81000000 0x4 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; +- marvell,pcie-port = <3>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 7>; +- status = "disabled"; +- }; +- }; +- }; +-}; +- +-&pinctrl { +- compatible = "marvell,mv88f6820-pinctrl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-388-clearfog-base.dts b/scripts/dtc/include-prefixes/arm/armada-388-clearfog-base.dts +deleted file mode 100644 +index 53b4bd35522a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-388-clearfog-base.dts ++++ /dev/null +@@ -1,68 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828) +- * +- * Copyright (C) 2015 Russell King +- */ +- +-/dts-v1/; +-#include "armada-388-clearfog.dtsi" +- +-/ { +- model = "SolidRun Clearfog Base A1"; +- compatible = "solidrun,clearfog-base-a1", +- "solidrun,clearfog-a1", "marvell,armada388", +- "marvell,armada385", "marvell,armada380"; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&rear_button_pins>; +- pinctrl-names = "default"; +- +- button_0 { +- /* The rear SW3 button */ +- label = "Rear Button"; +- gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; +- linux,can-disable; +- linux,code = ; +- }; +- }; +-}; +- +-ð1 { +- phy = <&phy1>; +-}; +- +-&gpio0 { +- phy1_reset { +- gpio-hog; +- gpios = <19 GPIO_ACTIVE_LOW>; +- output-low; +- line-name = "phy1-reset"; +- }; +-}; +- +-&mdio { +- pinctrl-0 = <&mdio_pins µsom_phy_clk_pins &clearfog_phy_pins>; +- phy1: ethernet-phy@1 { +- /* +- * Annoyingly, the marvell phy driver configures the LED +- * register, rather than preserving reset-loaded setting. +- * We undo that rubbish here. +- */ +- marvell,reg-init = <3 16 0 0x101e>; +- reg = <1>; +- }; +-}; +- +-&pinctrl { +- /* phy1 reset */ +- clearfog_phy_pins: clearfog-phy-pins { +- marvell,pins = "mpp19"; +- marvell,function = "gpio"; +- }; +- rear_button_pins: rear-button-pins { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-388-clearfog-pro.dts b/scripts/dtc/include-prefixes/arm/armada-388-clearfog-pro.dts +deleted file mode 100644 +index ff890c09c3ed..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-388-clearfog-pro.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828) +- * +- * Copyright (C) 2015 Russell King +- */ +-#include "armada-388-clearfog.dts" +- +-/ { +- model = "SolidRun Clearfog Pro A1"; +- compatible = "solidrun,clearfog-pro-a1", +- "solidrun,clearfog-a1", "marvell,armada388", +- "marvell,armada385", "marvell,armada380"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-388-clearfog.dts b/scripts/dtc/include-prefixes/arm/armada-388-clearfog.dts +deleted file mode 100644 +index 4140a5303b48..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-388-clearfog.dts ++++ /dev/null +@@ -1,180 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828) +- * +- * Copyright (C) 2015 Russell King +- */ +- +-/dts-v1/; +-#include "armada-388-clearfog.dtsi" +- +-/ { +- model = "SolidRun Clearfog A1"; +- compatible = "solidrun,clearfog-a1", "marvell,armada388", +- "marvell,armada385", "marvell,armada380"; +- +- soc { +- internal-regs { +- usb3@f0000 { +- /* CON2, nearest CPU, USB2 only. */ +- status = "okay"; +- }; +- }; +- +- pcie { +- pcie@3,0 { +- /* Port 2, Lane 0. CON2, nearest CPU. */ +- reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>; +- status = "okay"; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&rear_button_pins>; +- pinctrl-names = "default"; +- +- button_0 { +- /* The rear SW3 button */ +- label = "Rear Button"; +- gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; +- linux,can-disable; +- linux,code = ; +- }; +- }; +-}; +- +-ð1 { +- /* ethernet@30000 */ +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +-}; +- +-&expander0 { +- /* +- * PCA9655 GPIO expander: +- * 0-CON3 CLKREQ# +- * 1-CON3 PERST# +- * 2-CON2 PERST# +- * 3-CON3 W_DISABLE +- * 4-CON2 CLKREQ# +- * 5-USB3 overcurrent +- * 6-USB3 power +- * 7-CON2 W_DISABLE +- * 8-JP4 P1 +- * 9-JP4 P4 +- * 10-JP4 P5 +- * 11-m.2 DEVSLP +- * 12-SFP_LOS +- * 13-SFP_TX_FAULT +- * 14-SFP_TX_DISABLE +- * 15-SFP_MOD_DEF0 +- */ +- pcie2-0-clkreq-hog { +- gpio-hog; +- gpios = <4 GPIO_ACTIVE_LOW>; +- input; +- line-name = "pcie2.0-clkreq"; +- }; +- pcie2-0-w-disable-hog { +- gpio-hog; +- gpios = <7 GPIO_ACTIVE_LOW>; +- output-low; +- line-name = "pcie2.0-w-disable"; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- switch@4 { +- compatible = "marvell,mv88e6085"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>; +- pinctrl-names = "default"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan5"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan4"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan3"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan2"; +- }; +- +- port@4 { +- reg = <4>; +- label = "lan1"; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <ð1>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- port@6 { +- /* 88E1512 external phy */ +- reg = <6>; +- label = "lan6"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; +-}; +- +-&pinctrl { +- clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins { +- marvell,pins = "mpp46"; +- marvell,function = "ref"; +- }; +- clearfog_dsa0_pins: clearfog-dsa0-pins { +- marvell,pins = "mpp23", "mpp41"; +- marvell,function = "gpio"; +- }; +- clearfog_spi1_cs_pins: spi1-cs-pins { +- marvell,pins = "mpp55"; +- marvell,function = "spi1"; +- }; +- rear_button_pins: rear-button-pins { +- marvell,pins = "mpp34"; +- marvell,function = "gpio"; +- }; +-}; +- +-&spi1 { +- /* +- * Add SPI CS pins for clearfog: +- * CS0: W25Q32 +- * CS1: +- * CS2: mikrobus +- */ +- pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-388-clearfog.dtsi b/scripts/dtc/include-prefixes/arm/armada-388-clearfog.dtsi +deleted file mode 100644 +index f8a06ae4a3c9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-388-clearfog.dtsi ++++ /dev/null +@@ -1,245 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree include file for SolidRun Clearfog 88F6828 based boards +- * +- * Copyright (C) 2015 Russell King +- */ +- +-#include "armada-388.dtsi" +-#include "armada-38x-solidrun-microsom.dtsi" +- +-/ { +- aliases { +- /* So that mvebu u-boot can update the MAC addresses */ +- ethernet1 = ð0; +- ethernet2 = ð1; +- ethernet3 = ð2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- soc { +- internal-regs { +- sata@a8000 { +- /* pinctrl? */ +- status = "okay"; +- }; +- +- sata@e0000 { +- /* pinctrl? */ +- status = "okay"; +- }; +- +- sdhci@d8000 { +- bus-width = <4>; +- cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- pinctrl-0 = <µsom_sdhci_pins +- &clearfog_sdhci_cd_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- vmmc-supply = <®_3p3v>; +- wp-inverted; +- }; +- +- usb@58000 { +- /* CON3, nearest power. */ +- status = "okay"; +- }; +- +- usb3@f8000 { +- /* CON7 */ +- status = "okay"; +- }; +- }; +- +- pcie { +- status = "okay"; +- /* +- * The two PCIe units are accessible through +- * the mini-PCIe connectors on the board. +- */ +- pcie@2,0 { +- /* Port 1, Lane 0. CON3, nearest power. */ +- reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>; +- status = "okay"; +- }; +- }; +- }; +- +- sfp: sfp { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c1>; +- los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; +- mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>; +- tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; +- tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; +- maximum-power-milliwatt = <2000>; +- }; +-}; +- +-ð1 { +- /* ethernet@30000 */ +- bm,pool-long = <2>; +- bm,pool-short = <1>; +- buffer-manager = <&bm>; +- phys = <&comphy1 1>; +- phy-mode = "sgmii"; +- status = "okay"; +-}; +- +-ð2 { +- /* ethernet@34000 */ +- bm,pool-long = <3>; +- bm,pool-short = <1>; +- buffer-manager = <&bm>; +- managed = "in-band-status"; +- phys = <&comphy5 2>; +- phy-mode = "sgmii"; +- sfp = <&sfp>; +- status = "okay"; +-}; +- +-&i2c0 { +- /* +- * PCA9655 GPIO expander, up to 1MHz clock. +- * 0-CON3 CLKREQ# +- * 1-CON3 PERST# +- * 2- +- * 3-CON3 W_DISABLE +- * 4- +- * 5-USB3 overcurrent +- * 6-USB3 power +- * 7- +- * 8-JP4 P1 +- * 9-JP4 P4 +- * 10-JP4 P5 +- * 11-m.2 DEVSLP +- * 12-SFP_LOS +- * 13-SFP_TX_FAULT +- * 14-SFP_TX_DISABLE +- * 15-SFP_MOD_DEF0 +- */ +- expander0: gpio-expander@20 { +- /* +- * This is how it should be: +- * compatible = "onnn,pca9655", "nxp,pca9555"; +- * but you can't do this because of the way I2C works. +- */ +- compatible = "nxp,pca9555"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x20>; +- +- pcie1-0-clkreq-hog { +- gpio-hog; +- gpios = <0 GPIO_ACTIVE_LOW>; +- input; +- line-name = "pcie1.0-clkreq"; +- }; +- pcie1-0-w-disable-hog { +- gpio-hog; +- gpios = <3 GPIO_ACTIVE_LOW>; +- output-low; +- line-name = "pcie1.0-w-disable"; +- }; +- usb3-ilimit-hog { +- gpio-hog; +- gpios = <5 GPIO_ACTIVE_LOW>; +- input; +- line-name = "usb3-current-limit"; +- }; +- usb3-power-hog { +- gpio-hog; +- gpios = <6 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "usb3-power"; +- }; +- m2-devslp-hog { +- gpio-hog; +- gpios = <11 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "m.2 devslp"; +- }; +- }; +- +- /* The MCP3021 supports standard and fast modes */ +- mikrobus_adc: mcp3021@4c { +- compatible = "microchip,mcp3021"; +- reg = <0x4c>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +-}; +- +-&i2c1 { +- /* +- * Routed to SFP, mikrobus, and PCIe. +- * SFP limits this to 100kHz, and requires an AT24C01A/02/04 with +- * address pins tied low, which takes addresses 0x50 and 0x51. +- * Mikrobus doesn't specify beyond an I2C bus being present. +- * PCIe uses ARP to assign addresses, or 0x63-0x64. +- */ +- clock-frequency = <100000>; +- pinctrl-0 = <&clearfog_i2c1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&pinctrl { +- clearfog_i2c1_pins: i2c1-pins { +- /* SFP, PCIe, mSATA, mikrobus */ +- marvell,pins = "mpp26", "mpp27"; +- marvell,function = "i2c1"; +- }; +- clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins { +- marvell,pins = "mpp20"; +- marvell,function = "gpio"; +- }; +- mikro_pins: mikro-pins { +- /* int: mpp22 rst: mpp29 */ +- marvell,pins = "mpp22", "mpp29"; +- marvell,function = "gpio"; +- }; +- mikro_spi_pins: mikro-spi-pins { +- marvell,pins = "mpp43"; +- marvell,function = "spi1"; +- }; +- mikro_uart_pins: mikro-uart-pins { +- marvell,pins = "mpp24", "mpp25"; +- marvell,function = "ua1"; +- }; +-}; +- +-&spi1 { +- /* +- * Add SPI CS pins for clearfog: +- * CS0: W25Q32 +- * CS1: PIC microcontroller (Pro models) +- * CS2: mikrobus +- */ +- pinctrl-0 = <&spi1_pins &mikro_spi_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&uart1 { +- /* mikrobus uart */ +- pinctrl-0 = <&mikro_uart_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-388-db.dts b/scripts/dtc/include-prefixes/arm/armada-388-db.dts +deleted file mode 100644 +index a2bec07bf4c5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-388-db.dts ++++ /dev/null +@@ -1,176 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Marvell Armada 388 evaluation board +- * (DB-88F6820) +- * +- * Copyright (C) 2014 Marvell +- * +- * Thomas Petazzoni +- */ +- +-/dts-v1/; +-#include "armada-388.dtsi" +- +-/ { +- model = "Marvell Armada 385 Development Board"; +- compatible = "marvell,a385-db", "marvell,armada388", +- "marvell,armada385", "marvell,armada380"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; /* 256 MB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- i2c@11000 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- i2c@11100 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- ethernet@30000 { +- status = "okay"; +- phy = <&phy1>; +- phy-mode = "rgmii-id"; +- buffer-manager = <&bm>; +- bm,pool-long = <2>; +- bm,pool-short = <3>; +- }; +- +- usb@58000 { +- status = "ok"; +- }; +- +- ethernet@70000 { +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +- buffer-manager = <&bm>; +- bm,pool-long = <0>; +- bm,pool-short = <1>; +- }; +- +- mdio@72004 { +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +- }; +- +- sata@a8000 { +- status = "okay"; +- }; +- +- sata@e0000 { +- status = "okay"; +- }; +- +- bm@c8000 { +- status = "okay"; +- }; +- +- sdhci@d8000 { +- broken-cd; +- wp-inverted; +- bus-width = <8>; +- status = "okay"; +- no-1-8-v; +- }; +- +- usb3@f0000 { +- status = "okay"; +- }; +- +- usb3@f8000 { +- status = "okay"; +- }; +- }; +- +- bm-bppi { +- status = "okay"; +- }; +- +- pcie { +- status = "okay"; +- /* +- * The two PCIe units are accessible through +- * standard PCIe slots on the board. +- */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- pcie@2,0 { +- /* Port 1, Lane 0 */ +- status = "okay"; +- }; +- }; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "w25q32", "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <108000000>; +- }; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- marvell,nand-keep-config; +- nand-on-flash-bbt; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0 0x800000>; +- }; +- partition@800000 { +- label = "Linux"; +- reg = <0x800000 0x800000>; +- }; +- partition@1000000 { +- label = "Filesystem"; +- reg = <0x1000000 0x3f000000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-388-gp.dts b/scripts/dtc/include-prefixes/arm/armada-388-gp.dts +deleted file mode 100644 +index 9d873257ac45..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-388-gp.dts ++++ /dev/null +@@ -1,406 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for Marvell Armada 385 development board +- * (RD-88F6820-GP) +- * +- * Copyright (C) 2014 Marvell +- * +- * Gregory CLEMENT +- */ +- +-/dts-v1/; +-#include "armada-388.dtsi" +-#include +- +-/ { +- model = "Marvell Armada 388 DB-88F6820-GP"; +- compatible = "marvell,a388-gp", "marvell,armada388", "marvell,armada380"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x80000000>; /* 2 GB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- i2c@11000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +- clock-frequency = <100000>; +- +- expander0: pca9555@20 { +- compatible = "nxp,pca9555"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pca0_pins>; +- interrupt-parent = <&gpio0>; +- interrupts = <18 IRQ_TYPE_LEVEL_LOW>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x20>; +- }; +- +- expander1: pca9555@21 { +- compatible = "nxp,pca9555"; +- pinctrl-names = "default"; +- interrupt-parent = <&gpio0>; +- interrupts = <18 IRQ_TYPE_LEVEL_LOW>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x21>; +- }; +- +- eeprom@57 { +- compatible = "atmel,24c64"; +- reg = <0x57>; +- }; +- }; +- +- serial@12000 { +- /* +- * Exported on the micro USB connector CON16 +- * through an FTDI +- */ +- +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +- }; +- +- /* GE1 CON15 */ +- ethernet@30000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ge1_rgmii_pins>; +- status = "okay"; +- phy = <&phy1>; +- phy-mode = "rgmii-id"; +- buffer-manager = <&bm>; +- bm,pool-long = <2>; +- bm,pool-short = <3>; +- }; +- +- /* CON4 */ +- usb@58000 { +- vcc-supply = <®_usb2_0_vbus>; +- status = "okay"; +- }; +- +- /* GE0 CON1 */ +- ethernet@70000 { +- pinctrl-names = "default"; +- /* +- * The Reference Clock 0 is used to provide a +- * clock to the PHY +- */ +- pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +- buffer-manager = <&bm>; +- bm,pool-long = <0>; +- bm,pool-short = <1>; +- }; +- +- +- mdio@72004 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mdio_pins>; +- +- phy0: ethernet-phy@1 { +- reg = <1>; +- }; +- +- phy1: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- sata@a8000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sata0_pins>, <&sata1_pins>; +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- sata0: sata-port@0 { +- reg = <0>; +- target-supply = <®_5v_sata0>; +- }; +- +- sata1: sata-port@1 { +- reg = <1>; +- target-supply = <®_5v_sata1>; +- }; +- }; +- +- bm@c8000 { +- status = "okay"; +- }; +- +- sata@e0000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sata2_pins>, <&sata3_pins>; +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- sata2: sata-port@0 { +- reg = <0>; +- target-supply = <®_5v_sata2>; +- }; +- +- sata3: sata-port@1 { +- reg = <1>; +- target-supply = <®_5v_sata3>; +- }; +- }; +- +- sdhci@d8000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhci_pins>; +- no-1-8-v; +- /* +- * A388-GP board v1.5 and higher replace +- * hitherto card detection method based on GPIO +- * with the one using DAT3 pin. As they are +- * incompatible, software-based polling is +- * enabled with 'broken-cd' property. For boards +- * older than v1.5 it can be replaced with: +- * 'cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;', +- * whereas for the newer ones following can be +- * used instead: +- * 'dat3-cd;' +- * 'cd-inverted;' +- */ +- broken-cd; +- wp-inverted; +- bus-width = <8>; +- status = "okay"; +- }; +- +- /* CON5 */ +- usb3@f0000 { +- usb-phy = <&usb2_1_phy>; +- status = "okay"; +- }; +- +- /* CON7 */ +- usb3@f8000 { +- usb-phy = <&usb3_phy>; +- status = "okay"; +- }; +- }; +- +- bm-bppi { +- status = "okay"; +- }; +- +- pcie { +- status = "okay"; +- /* +- * One PCIe units is accessible through +- * standard PCIe slot on the board. +- */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- +- /* +- * The two other PCIe units are accessible +- * through mini PCIe slot on the board. +- */ +- pcie@2,0 { +- /* Port 1, Lane 0 */ +- status = "okay"; +- }; +- pcie@3,0 { +- /* Port 2, Lane 0 */ +- status = "okay"; +- }; +- }; +- +- gpio-fan { +- compatible = "gpio-fan"; +- gpios = <&expander1 3 GPIO_ACTIVE_HIGH>; +- gpio-fan,speed-map = < 0 0 +- 3000 1>; +- }; +- }; +- +- usb2_1_phy: usb2_1_phy { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <®_usb2_1_vbus>; +- #phy-cells = <0>; +- }; +- +- usb3_phy: usb3_phy { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <®_usb3_vbus>; +- #phy-cells = <0>; +- }; +- +- reg_usb3_vbus: usb3-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb3-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&expander1 15 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_usb2_0_vbus: v5-vbus0 { +- compatible = "regulator-fixed"; +- regulator-name = "v5.0-vbus0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_usb2_1_vbus: v5-vbus1 { +- compatible = "regulator-fixed"; +- regulator-name = "v5.0-vbus1"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_sata0: pwr-sata0 { +- compatible = "regulator-fixed"; +- regulator-name = "pwr_en_sata0"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- enable-active-high; +- regulator-boot-on; +- gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_5v_sata0: v5-sata0 { +- compatible = "regulator-fixed"; +- regulator-name = "v5.0-sata0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <®_sata0>; +- }; +- +- reg_12v_sata0: v12-sata0 { +- compatible = "regulator-fixed"; +- regulator-name = "v12.0-sata0"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- vin-supply = <®_sata0>; +- }; +- +- reg_sata1: pwr-sata1 { +- regulator-name = "pwr_en_sata1"; +- compatible = "regulator-fixed"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- enable-active-high; +- regulator-boot-on; +- gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_5v_sata1: v5-sata1 { +- compatible = "regulator-fixed"; +- regulator-name = "v5.0-sata1"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <®_sata1>; +- }; +- +- reg_12v_sata1: v12-sata1 { +- compatible = "regulator-fixed"; +- regulator-name = "v12.0-sata1"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- vin-supply = <®_sata1>; +- }; +- +- reg_sata2: pwr-sata2 { +- compatible = "regulator-fixed"; +- regulator-name = "pwr_en_sata2"; +- enable-active-high; +- regulator-boot-on; +- gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_5v_sata2: v5-sata2 { +- compatible = "regulator-fixed"; +- regulator-name = "v5.0-sata2"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <®_sata2>; +- }; +- +- reg_12v_sata2: v12-sata2 { +- compatible = "regulator-fixed"; +- regulator-name = "v12.0-sata2"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- vin-supply = <®_sata2>; +- }; +- +- reg_sata3: pwr-sata3 { +- compatible = "regulator-fixed"; +- regulator-name = "pwr_en_sata3"; +- enable-active-high; +- regulator-boot-on; +- gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_5v_sata3: v5-sata3 { +- compatible = "regulator-fixed"; +- regulator-name = "v5.0-sata3"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <®_sata3>; +- }; +- +- reg_12v_sata3: v12-sata3 { +- compatible = "regulator-fixed"; +- regulator-name = "v12.0-sata3"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- vin-supply = <®_sata3>; +- }; +-}; +- +-&pinctrl { +- pca0_pins: pca0_pins { +- marvell,pins = "mpp18"; +- marvell,function = "gpio"; +- }; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins>; +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p128", "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <50000000>; +- m25p,fast-read; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-388-helios4.dts b/scripts/dtc/include-prefixes/arm/armada-388-helios4.dts +deleted file mode 100644 +index ec134e22bae3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-388-helios4.dts ++++ /dev/null +@@ -1,324 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for Helios4 +- * based on SolidRun Clearfog revision A1 rev 2.0 (88F6828) +- * +- * Copyright (C) 2017 Aditya Prayoga +- * +- */ +- +-/dts-v1/; +-#include "armada-388.dtsi" +-#include "armada-38x-solidrun-microsom.dtsi" +- +-/ { +- model = "Helios4"; +- compatible = "kobol,helios4", "marvell,armada388", +- "marvell,armada385", "marvell,armada380"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x80000000>; /* 2 GB */ +- }; +- +- aliases { +- /* So that mvebu u-boot can update the MAC addresses */ +- ethernet1 = ð0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- reg_12v: regulator-12v { +- compatible = "regulator-fixed"; +- regulator-name = "power_brick_12V"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- vin-supply = <®_12v>; +- }; +- +- reg_5p0v_hdd: regulator-5v-hdd { +- compatible = "regulator-fixed"; +- regulator-name = "5V_HDD"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- vin-supply = <®_12v>; +- }; +- +- reg_5p0v_usb: regulator-5v-usb { +- compatible = "regulator-fixed"; +- regulator-name = "USB-PWR"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- enable-active-high; +- gpio = <&expander0 6 GPIO_ACTIVE_HIGH>; +- vin-supply = <®_12v>; +- }; +- +- system-leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&helios_system_led_pins>; +- +- status-led { +- label = "helios4:green:status"; +- gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- default-state = "on"; +- }; +- +- fault-led { +- label = "helios4:red:fault"; +- gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- }; +- +- io-leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&helios_io_led_pins>; +- +- sata1-led { +- label = "helios4:green:ata1"; +- gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "ata1"; +- default-state = "off"; +- }; +- sata2-led { +- label = "helios4:green:ata2"; +- gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "ata2"; +- default-state = "off"; +- }; +- sata3-led { +- label = "helios4:green:ata3"; +- gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "ata3"; +- default-state = "off"; +- }; +- sata4-led { +- label = "helios4:green:ata4"; +- gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "ata4"; +- default-state = "off"; +- }; +- usb-led { +- label = "helios4:green:usb"; +- gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "usb-host"; +- default-state = "off"; +- }; +- }; +- +- fan1: j10-pwm { +- compatible = "pwm-fan"; +- pwms = <&gpio1 9 40000>; /* Target freq:25 kHz */ +- pinctrl-names = "default"; +- pinctrl-0 = <&helios_fan1_pins>; +- }; +- +- fan2: j17-pwm { +- compatible = "pwm-fan"; +- pwms = <&gpio1 23 40000>; /* Target freq:25 kHz */ +- pinctrl-names = "default"; +- pinctrl-0 = <&helios_fan2_pins>; +- }; +- +- usb2_phy: usb2-phy { +- compatible = "usb-nop-xceiv"; +- vbus-regulator = <®_5p0v_usb>; +- }; +- +- usb3_phy: usb3-phy { +- compatible = "usb-nop-xceiv"; +- }; +- +- soc { +- internal-regs { +- i2c@11000 { +- /* +- * PCA9655 GPIO expander, up to 1MHz clock. +- * 0-Board Revision bit 0 # +- * 1-Board Revision bit 1 # +- * 5-USB3 overcurrent +- * 6-USB3 power +- */ +- expander0: gpio-expander@20 { +- /* +- * This is how it should be: +- * compatible = "onnn,pca9655", +- * "nxp,pca9555"; +- * but you can't do this because of +- * the way I2C works. +- */ +- compatible = "nxp,pca9555"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x20>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pca0_pins>; +- interrupt-parent = <&gpio0>; +- interrupts = <23 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- board-rev-bit-0-hog { +- gpio-hog; +- gpios = <0 GPIO_ACTIVE_LOW>; +- input; +- line-name = "board-rev-0"; +- }; +- board-rev-bit-1-hog { +- gpio-hog; +- gpios = <1 GPIO_ACTIVE_LOW>; +- input; +- line-name = "board-rev-1"; +- }; +- usb3-ilimit-hog { +- gpio-hog; +- gpios = <5 GPIO_ACTIVE_HIGH>; +- input; +- line-name = "usb-overcurrent-status"; +- }; +- }; +- +- temp_sensor: temp@4c { +- compatible = "ti,lm75"; +- reg = <0x4c>; +- vcc-supply = <®_3p3v>; +- }; +- }; +- +- i2c@11100 { +- /* +- * External I2C Bus for user peripheral +- */ +- clock-frequency = <400000>; +- pinctrl-0 = <&helios_i2c1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- +- sata@a8000 { +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- sata0: sata-port@0 { +- reg = <0>; +- }; +- +- sata1: sata-port@1 { +- reg = <1>; +- }; +- }; +- +- sata@e0000 { +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- sata2: sata-port@0 { +- reg = <0>; +- }; +- +- sata3: sata-port@1 { +- reg = <1>; +- }; +- }; +- +- spi@10680 { +- pinctrl-0 = <&spi1_pins +- µsom_spi1_cs_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- +- sdhci@d8000 { +- bus-width = <4>; +- cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- pinctrl-0 = <&helios_sdhci_pins +- &helios_sdhci_cd_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- vmmc = <®_3p3v>; +- wp-inverted; +- }; +- +- usb@58000 { +- usb-phy = <&usb2_phy>; +- status = "okay"; +- }; +- +- usb3@f0000 { +- status = "okay"; +- }; +- +- usb3@f8000 { +- status = "okay"; +- }; +- +- pinctrl@18000 { +- pca0_pins: pca0-pins { +- marvell,pins = "mpp23"; +- marvell,function = "gpio"; +- }; +- microsom_phy0_int_pins: microsom-phy0-int-pins { +- marvell,pins = "mpp18"; +- marvell,function = "gpio"; +- }; +- helios_i2c1_pins: i2c1-pins { +- marvell,pins = "mpp26", "mpp27"; +- marvell,function = "i2c1"; +- }; +- helios_sdhci_cd_pins: helios-sdhci-cd-pins { +- marvell,pins = "mpp20"; +- marvell,function = "gpio"; +- }; +- helios_sdhci_pins: helios-sdhci-pins { +- marvell,pins = "mpp21", "mpp28", +- "mpp37", "mpp38", +- "mpp39", "mpp40"; +- marvell,function = "sd0"; +- }; +- helios_system_led_pins: helios-system-led-pins { +- marvell,pins = "mpp24", "mpp25"; +- marvell,function = "gpio"; +- }; +- helios_io_led_pins: helios-io-led-pins { +- marvell,pins = "mpp49", "mpp50", +- "mpp52", "mpp53", +- "mpp54"; +- marvell,function = "gpio"; +- }; +- helios_fan1_pins: helios_fan1_pins { +- marvell,pins = "mpp41", "mpp43"; +- marvell,function = "gpio"; +- }; +- helios_fan2_pins: helios_fan2_pins { +- marvell,pins = "mpp48", "mpp55"; +- marvell,function = "gpio"; +- }; +- microsom_spi1_cs_pins: spi1-cs-pins { +- marvell,pins = "mpp59"; +- marvell,function = "spi1"; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-388-rd.dts b/scripts/dtc/include-prefixes/arm/armada-388-rd.dts +deleted file mode 100644 +index 328a4d6afd2c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-388-rd.dts ++++ /dev/null +@@ -1,108 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Marvell Armada 388 Reference Design board +- * (RD-88F6820-AP) +- * +- * Copyright (C) 2014 Marvell +- * +- * Gregory CLEMENT +- * Thomas Petazzoni +- */ +- +-/dts-v1/; +-#include "armada-388.dtsi" +- +-/ { +- model = "Marvell Armada 385 Reference Design"; +- compatible = "marvell,a385-rd", "marvell,armada388", +- "marvell,armada385","marvell,armada380"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; /* 256 MB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- i2c@11000 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- sdhci@d8000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhci_pins>; +- broken-cd; +- no-1-8-v; +- wp-inverted; +- bus-width = <8>; +- status = "okay"; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- ethernet@30000 { +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +- }; +- +- ethernet@70000 { +- status = "okay"; +- phy = <&phy1>; +- phy-mode = "rgmii-id"; +- }; +- +- +- mdio@72004 { +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +- }; +- +- usb3@f0000 { +- status = "okay"; +- }; +- }; +- +- pcie { +- status = "okay"; +- /* +- * One PCIe units is accessible through +- * standard PCIe slot on the board. +- */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- }; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p128", "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <108000000>; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/armada-388.dtsi b/scripts/dtc/include-prefixes/arm/armada-388.dtsi +deleted file mode 100644 +index f3a020ff577e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-388.dtsi ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell Armada 388 SoC. +- * +- * Copyright (C) 2015 Marvell +- * +- * Gregory CLEMENT +- * +- * The main difference with the Armada 385 is that the 388 can handle two more +- * SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl +- * property and the name of the SoC, and add the second SATA host which control +- * the 2 other ports. +- */ +- +-#include "armada-385.dtsi" +- +-/ { +- model = "Marvell Armada 388 family SoC"; +- compatible = "marvell,armada388", "marvell,armada385", +- "marvell,armada380"; +- soc { +- internal-regs { +- sata@e0000 { +- compatible = "marvell,armada-380-ahci"; +- reg = <0xe0000 0x2000>; +- interrupts = ; +- clocks = <&gateclk 30>; +- status = "disabled"; +- }; +- +- }; +- }; +-}; +- +-&pinctrl { +- compatible = "marvell,mv88f6828-pinctrl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-38x-solidrun-microsom.dtsi b/scripts/dtc/include-prefixes/arm/armada-38x-solidrun-microsom.dtsi +deleted file mode 100644 +index 363ac4238859..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-38x-solidrun-microsom.dtsi ++++ /dev/null +@@ -1,117 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for SolidRun Armada 38x Microsom +- * +- * Copyright (C) 2015 Russell King +- */ +-#include +-#include +- +-/ { +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; /* 256 MB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- rtc@a3800 { +- /* +- * If the rtc doesn't work, run "date reset" +- * twice in u-boot. +- */ +- status = "okay"; +- }; +- }; +- }; +-}; +- +-&bm { +- status = "okay"; +-}; +- +-&bm_bppi { +- status = "okay"; +-}; +- +-ð0 { +- /* ethernet@70000 */ +- pinctrl-0 = <&ge0_rgmii_pins>; +- pinctrl-names = "default"; +- phy = <&phy_dedicated>; +- phy-mode = "rgmii-id"; +- buffer-manager = <&bm>; +- bm,pool-long = <0>; +- bm,pool-short = <1>; +- status = "okay"; +-}; +- +-&mdio { +- /* +- * Add the phy clock here, so the phy can be accessed to read its +- * IDs prior to binding with the driver. +- */ +- pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>; +- pinctrl-names = "default"; +- +- phy_dedicated: ethernet-phy@0 { +- /* +- * Annoyingly, the marvell phy driver configures the LED +- * register, rather than preserving reset-loaded setting. +- * We undo that rubbish here. +- */ +- marvell,reg-init = <3 16 0 0x101e>; +- reg = <0>; +- }; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +-}; +- +-&pinctrl { +- microsom_phy_clk_pins: microsom-phy-clk-pins { +- marvell,pins = "mpp45"; +- marvell,function = "ref"; +- }; +- /* Optional eMMC */ +- microsom_sdhci_pins: microsom-sdhci-pins { +- marvell,pins = "mpp21", "mpp28", "mpp37", +- "mpp38", "mpp39", "mpp40"; +- marvell,function = "sd0"; +- }; +-}; +- +-&spi1 { +- /* The microsom has an optional W25Q32 on board, connected to CS0 */ +- pinctrl-0 = <&spi1_pins>; +- +- w25q32: spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "w25q32", "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <3000000>; +- }; +-}; +- +-&uart0 { +- pinctrl-0 = <&uart0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-38x.dtsi b/scripts/dtc/include-prefixes/arm/armada-38x.dtsi +deleted file mode 100644 +index df3c8d1d8f64..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-38x.dtsi ++++ /dev/null +@@ -1,707 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell Armada 38x family of SoCs. +- * +- * Copyright (C) 2014 Marvell +- * +- * Lior Amsalem +- * Gregory CLEMENT +- * Thomas Petazzoni +- */ +- +-#include +-#include +- +-#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- model = "Marvell Armada 38x family SoC"; +- compatible = "marvell,armada380"; +- +- aliases { +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts-extended = <&mpic 3>; +- }; +- +- soc { +- compatible = "marvell,armada380-mbus", "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- controller = <&mbusc>; +- interrupt-parent = <&gic>; +- pcie-mem-aperture = <0xe0000000 0x8000000>; +- pcie-io-aperture = <0xe8000000 0x100000>; +- +- bootrom { +- compatible = "marvell,bootrom"; +- reg = ; +- }; +- +- devbus_bootcs: devbus-bootcs { +- compatible = "marvell,mvebu-devbus"; +- reg = ; +- ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- devbus_cs0: devbus-cs0 { +- compatible = "marvell,mvebu-devbus"; +- reg = ; +- ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- devbus_cs1: devbus-cs1 { +- compatible = "marvell,mvebu-devbus"; +- reg = ; +- ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- devbus_cs2: devbus-cs2 { +- compatible = "marvell,mvebu-devbus"; +- reg = ; +- ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- devbus_cs3: devbus-cs3 { +- compatible = "marvell,mvebu-devbus"; +- reg = ; +- ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- internal-regs { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; +- +- sdramc: sdramc@1400 { +- compatible = "marvell,armada-xp-sdram-controller"; +- reg = <0x1400 0x500>; +- }; +- +- L2: cache-controller@8000 { +- compatible = "arm,pl310-cache"; +- reg = <0x8000 0x1000>; +- cache-unified; +- cache-level = <2>; +- arm,double-linefill-incr = <0>; +- arm,double-linefill-wrap = <0>; +- arm,double-linefill = <0>; +- prefetch-data = <1>; +- }; +- +- scu@c000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0xc000 0x58>; +- }; +- +- timer@c200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0xc200 0x20>; +- interrupts = ; +- clocks = <&coreclk 2>; +- }; +- +- timer@c600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0xc600 0x20>; +- interrupts = ; +- clocks = <&coreclk 2>; +- }; +- +- gic: interrupt-controller@d000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #size-cells = <0>; +- interrupt-controller; +- reg = <0xd000 0x1000>, +- <0xc100 0x100>; +- }; +- +- i2c0: i2c@11000 { +- compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; +- reg = <0x11000 0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@11100 { +- compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; +- reg = <0x11100 0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- uart0: serial@12000 { +- compatible = "marvell,armada-38x-uart", "ns16550a"; +- reg = <0x12000 0x100>; +- reg-shift = <2>; +- interrupts = ; +- reg-io-width = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- uart1: serial@12100 { +- compatible = "marvell,armada-38x-uart", "ns16550a"; +- reg = <0x12100 0x100>; +- reg-shift = <2>; +- interrupts = ; +- reg-io-width = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- pinctrl: pinctrl@18000 { +- reg = <0x18000 0x20>; +- +- ge0_rgmii_pins: ge-rgmii-pins-0 { +- marvell,pins = "mpp6", "mpp7", "mpp8", +- "mpp9", "mpp10", "mpp11", +- "mpp12", "mpp13", "mpp14", +- "mpp15", "mpp16", "mpp17"; +- marvell,function = "ge0"; +- }; +- +- ge1_rgmii_pins: ge-rgmii-pins-1 { +- marvell,pins = "mpp21", "mpp27", "mpp28", +- "mpp29", "mpp30", "mpp31", +- "mpp32", "mpp37", "mpp38", +- "mpp39", "mpp40", "mpp41"; +- marvell,function = "ge1"; +- }; +- +- i2c0_pins: i2c-pins-0 { +- marvell,pins = "mpp2", "mpp3"; +- marvell,function = "i2c0"; +- }; +- +- mdio_pins: mdio-pins { +- marvell,pins = "mpp4", "mpp5"; +- marvell,function = "ge"; +- }; +- +- ref_clk0_pins: ref-clk-pins-0 { +- marvell,pins = "mpp45"; +- marvell,function = "ref"; +- }; +- +- ref_clk1_pins: ref-clk-pins-1 { +- marvell,pins = "mpp46"; +- marvell,function = "ref"; +- }; +- +- spi0_pins: spi-pins-0 { +- marvell,pins = "mpp22", "mpp23", "mpp24", +- "mpp25"; +- marvell,function = "spi0"; +- }; +- +- spi1_pins: spi-pins-1 { +- marvell,pins = "mpp56", "mpp57", "mpp58", +- "mpp59"; +- marvell,function = "spi1"; +- }; +- +- nand_pins: nand-pins { +- marvell,pins = "mpp22", "mpp34", "mpp23", +- "mpp33", "mpp38", "mpp28", +- "mpp40", "mpp42", "mpp35", +- "mpp36", "mpp25", "mpp30", +- "mpp32"; +- marvell,function = "dev"; +- }; +- +- nand_rb: nand-rb { +- marvell,pins = "mpp41"; +- marvell,function = "nand"; +- }; +- +- uart0_pins: uart-pins-0 { +- marvell,pins = "mpp0", "mpp1"; +- marvell,function = "ua0"; +- }; +- +- uart1_pins: uart-pins-1 { +- marvell,pins = "mpp19", "mpp20"; +- marvell,function = "ua1"; +- }; +- +- sdhci_pins: sdhci-pins { +- marvell,pins = "mpp48", "mpp49", "mpp50", +- "mpp52", "mpp53", "mpp54", +- "mpp55", "mpp57", "mpp58", +- "mpp59"; +- marvell,function = "sd0"; +- }; +- +- sata0_pins: sata-pins-0 { +- marvell,pins = "mpp20"; +- marvell,function = "sata0"; +- }; +- +- sata1_pins: sata-pins-1 { +- marvell,pins = "mpp19"; +- marvell,function = "sata1"; +- }; +- +- sata2_pins: sata-pins-2 { +- marvell,pins = "mpp47"; +- marvell,function = "sata2"; +- }; +- +- sata3_pins: sata-pins-3 { +- marvell,pins = "mpp44"; +- marvell,function = "sata3"; +- }; +- }; +- +- gpio0: gpio@18100 { +- compatible = "marvell,armada-370-gpio", +- "marvell,orion-gpio"; +- reg = <0x18100 0x40>, <0x181c0 0x08>; +- reg-names = "gpio", "pwm"; +- ngpios = <32>; +- gpio-controller; +- #gpio-cells = <2>; +- #pwm-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = , +- , +- , +- ; +- clocks = <&coreclk 0>; +- }; +- +- gpio1: gpio@18140 { +- compatible = "marvell,armada-370-gpio", +- "marvell,orion-gpio"; +- reg = <0x18140 0x40>, <0x181c8 0x08>; +- reg-names = "gpio", "pwm"; +- ngpios = <28>; +- gpio-controller; +- #gpio-cells = <2>; +- #pwm-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = , +- , +- , +- ; +- clocks = <&coreclk 0>; +- }; +- +- systemc: system-controller@18200 { +- compatible = "marvell,armada-380-system-controller", +- "marvell,armada-370-xp-system-controller"; +- reg = <0x18200 0x100>; +- }; +- +- gateclk: clock-gating-control@18220 { +- compatible = "marvell,armada-380-gating-clock"; +- reg = <0x18220 0x4>; +- clocks = <&coreclk 0>; +- #clock-cells = <1>; +- }; +- +- comphy: phy@18300 { +- compatible = "marvell,armada-380-comphy"; +- reg-names = "comphy", "conf"; +- reg = <0x18300 0x100>, <0x18460 4>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- comphy0: phy@0 { +- reg = <0>; +- #phy-cells = <1>; +- }; +- +- comphy1: phy@1 { +- reg = <1>; +- #phy-cells = <1>; +- }; +- +- comphy2: phy@2 { +- reg = <2>; +- #phy-cells = <1>; +- }; +- +- comphy3: phy@3 { +- reg = <3>; +- #phy-cells = <1>; +- }; +- +- comphy4: phy@4 { +- reg = <4>; +- #phy-cells = <1>; +- }; +- +- comphy5: phy@5 { +- reg = <5>; +- #phy-cells = <1>; +- }; +- }; +- +- coreclk: mvebu-sar@18600 { +- compatible = "marvell,armada-380-core-clock"; +- reg = <0x18600 0x04>; +- #clock-cells = <1>; +- }; +- +- mbusc: mbus-controller@20000 { +- compatible = "marvell,mbus-controller"; +- reg = <0x20000 0x100>, <0x20180 0x20>, +- <0x20250 0x8>; +- }; +- +- mpic: interrupt-controller@20a00 { +- compatible = "marvell,mpic"; +- reg = <0x20a00 0x2d0>, <0x21070 0x58>; +- #interrupt-cells = <1>; +- #size-cells = <1>; +- interrupt-controller; +- msi-controller; +- interrupts = ; +- }; +- +- timer: timer@20300 { +- compatible = "marvell,armada-380-timer", +- "marvell,armada-xp-timer"; +- reg = <0x20300 0x30>, <0x21040 0x30>; +- interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, +- <&mpic 5>, +- <&mpic 6>; +- clocks = <&coreclk 2>, <&refclk>; +- clock-names = "nbclk", "fixed"; +- }; +- +- watchdog: watchdog@20300 { +- compatible = "marvell,armada-380-wdt"; +- reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; +- clocks = <&coreclk 2>, <&refclk>; +- clock-names = "nbclk", "fixed"; +- interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- cpurst: cpurst@20800 { +- compatible = "marvell,armada-370-cpu-reset"; +- reg = <0x20800 0x10>; +- }; +- +- mpcore-soc-ctrl@20d20 { +- compatible = "marvell,armada-380-mpcore-soc-ctrl"; +- reg = <0x20d20 0x6c>; +- }; +- +- coherencyfab: coherency-fabric@21010 { +- compatible = "marvell,armada-380-coherency-fabric"; +- reg = <0x21010 0x1c>; +- }; +- +- pmsu: pmsu@22000 { +- compatible = "marvell,armada-380-pmsu"; +- reg = <0x22000 0x1000>; +- }; +- +- /* +- * As a special exception to the "order by +- * register address" rule, the eth0 node is +- * placed here to ensure that it gets +- * registered as the first interface, since +- * the network subsystem doesn't allow naming +- * interfaces using DT aliases. Without this, +- * the ordering of interfaces is different +- * from the one used in U-Boot and the +- * labeling of interfaces on the boards, which +- * is very confusing for users. +- */ +- eth0: ethernet@70000 { +- compatible = "marvell,armada-370-neta"; +- reg = <0x70000 0x4000>; +- interrupts-extended = <&mpic 8>; +- clocks = <&gateclk 4>; +- tx-csum-limit = <9800>; +- status = "disabled"; +- }; +- +- eth1: ethernet@30000 { +- compatible = "marvell,armada-370-neta"; +- reg = <0x30000 0x4000>; +- interrupts-extended = <&mpic 10>; +- clocks = <&gateclk 3>; +- status = "disabled"; +- }; +- +- eth2: ethernet@34000 { +- compatible = "marvell,armada-370-neta"; +- reg = <0x34000 0x4000>; +- interrupts-extended = <&mpic 12>; +- clocks = <&gateclk 2>; +- status = "disabled"; +- }; +- +- usb0: usb@58000 { +- compatible = "marvell,orion-ehci"; +- reg = <0x58000 0x500>; +- interrupts = ; +- clocks = <&gateclk 18>; +- status = "disabled"; +- }; +- +- xor0: xor@60800 { +- compatible = "marvell,armada-380-xor", "marvell,orion-xor"; +- reg = <0x60800 0x100 +- 0x60a00 0x100>; +- clocks = <&gateclk 22>; +- status = "okay"; +- +- xor00 { +- interrupts = ; +- dmacap,memcpy; +- dmacap,xor; +- }; +- xor01 { +- interrupts = ; +- dmacap,memcpy; +- dmacap,xor; +- dmacap,memset; +- }; +- }; +- +- xor1: xor@60900 { +- compatible = "marvell,armada-380-xor", "marvell,orion-xor"; +- reg = <0x60900 0x100 +- 0x60b00 0x100>; +- clocks = <&gateclk 28>; +- status = "okay"; +- +- xor10 { +- interrupts = ; +- dmacap,memcpy; +- dmacap,xor; +- }; +- xor11 { +- interrupts = ; +- dmacap,memcpy; +- dmacap,xor; +- dmacap,memset; +- }; +- }; +- +- mdio: mdio@72004 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "marvell,orion-mdio"; +- reg = <0x72004 0x4>; +- clocks = <&gateclk 4>; +- }; +- +- cesa: crypto@90000 { +- compatible = "marvell,armada-38x-crypto"; +- reg = <0x90000 0x10000>; +- reg-names = "regs"; +- interrupts = , +- ; +- clocks = <&gateclk 23>, <&gateclk 21>, +- <&gateclk 14>, <&gateclk 16>; +- clock-names = "cesa0", "cesa1", +- "cesaz0", "cesaz1"; +- marvell,crypto-srams = <&crypto_sram0>, +- <&crypto_sram1>; +- marvell,crypto-sram-size = <0x800>; +- }; +- +- rtc: rtc@a3800 { +- compatible = "marvell,armada-380-rtc"; +- reg = <0xa3800 0x20>, <0x184a0 0x0c>; +- reg-names = "rtc", "rtc-soc"; +- interrupts = ; +- }; +- +- ahci0: sata@a8000 { +- compatible = "marvell,armada-380-ahci"; +- reg = <0xa8000 0x2000>; +- interrupts = ; +- clocks = <&gateclk 15>; +- status = "disabled"; +- }; +- +- bm: bm@c8000 { +- compatible = "marvell,armada-380-neta-bm"; +- reg = <0xc8000 0xac>; +- clocks = <&gateclk 13>; +- internal-mem = <&bm_bppi>; +- status = "disabled"; +- }; +- +- ahci1: sata@e0000 { +- compatible = "marvell,armada-380-ahci"; +- reg = <0xe0000 0x2000>; +- interrupts = ; +- clocks = <&gateclk 30>; +- status = "disabled"; +- }; +- +- coredivclk: clock@e4250 { +- compatible = "marvell,armada-380-corediv-clock"; +- reg = <0xe4250 0xc>; +- #clock-cells = <1>; +- clocks = <&mainpll>; +- clock-output-names = "nand"; +- }; +- +- thermal: thermal@e8078 { +- compatible = "marvell,armada380-thermal"; +- reg = <0xe4078 0x4>, <0xe4070 0x8>; +- status = "okay"; +- }; +- +- nand_controller: nand-controller@d0000 { +- compatible = "marvell,armada370-nand-controller"; +- reg = <0xd0000 0x54>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&coredivclk 0>; +- status = "disabled"; +- }; +- +- sdhci: sdhci@d8000 { +- compatible = "marvell,armada-380-sdhci"; +- reg-names = "sdhci", "mbus", "conf-sdio3"; +- reg = <0xd8000 0x1000>, +- <0xdc000 0x100>, +- <0x18454 0x4>; +- interrupts = ; +- clocks = <&gateclk 17>; +- mrvl,clk-delay-cycles = <0x1F>; +- status = "disabled"; +- }; +- +- usb3_0: usb3@f0000 { +- compatible = "marvell,armada-380-xhci"; +- reg = <0xf0000 0x4000>,<0xf4000 0x4000>; +- interrupts = ; +- clocks = <&gateclk 9>; +- status = "disabled"; +- }; +- +- usb3_1: usb3@f8000 { +- compatible = "marvell,armada-380-xhci"; +- reg = <0xf8000 0x4000>,<0xfc000 0x4000>; +- interrupts = ; +- clocks = <&gateclk 10>; +- status = "disabled"; +- }; +- }; +- +- crypto_sram0: sa-sram0 { +- compatible = "mmio-sram"; +- reg = ; +- clocks = <&gateclk 23>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>; +- }; +- +- crypto_sram1: sa-sram1 { +- compatible = "mmio-sram"; +- reg = ; +- clocks = <&gateclk 21>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>; +- }; +- +- bm_bppi: bm-bppi { +- compatible = "mmio-sram"; +- reg = ; +- ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&gateclk 13>; +- no-memory-wc; +- status = "disabled"; +- }; +- +- spi0: spi@10600 { +- compatible = "marvell,armada-380-spi", +- "marvell,orion-spi"; +- reg = ; +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- interrupts = ; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- spi1: spi@10680 { +- compatible = "marvell,armada-380-spi", +- "marvell,orion-spi"; +- reg = ; +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- interrupts = ; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- }; +- +- clocks { +- /* 1 GHz fixed main PLL */ +- mainpll: mainpll { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <1000000000>; +- }; +- +- /* 25 MHz reference crystal */ +- refclk: oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-390-db.dts b/scripts/dtc/include-prefixes/arm/armada-390-db.dts +deleted file mode 100644 +index 0e29474ae9a2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-390-db.dts ++++ /dev/null +@@ -1,142 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Marvell Armada 390 Development Board +- * (DB-88F6920) +- * +- * Copyright (C) 2016 Marvell +- * +- * Grzegorz Jaszczyk +- */ +- +-/dts-v1/; +-#include "armada-390.dtsi" +- +-/ { +- model = "Marvell Armada 390 Development Board"; +- compatible = "marvell,a390-db", "marvell,armada390"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x80000000>; /* 2 GB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- i2c@11000 { +- status = "okay"; +- clock-frequency = <100000>; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- }; +- +- /* CON104 */ +- serial@12000 { +- status = "okay"; +- }; +- +- /* CON97 */ +- usb@58000 { +- status = "okay"; +- }; +- +- /* CON98 */ +- usb3@f8000 { +- status = "okay"; +- }; +- }; +- +- pcie { +- status = "okay"; +- +- /* CON30 */ +- pcie@1,0 { +- status = "okay"; +- }; +- +- /* CON44 */ +- pcie@2,0 { +- status = "okay"; +- }; +- +- /* CON61 */ +- pcie@3,0 { +- status = "okay"; +- }; +- }; +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-0 = <&spi1_pins>; +- pinctrl-names = "default"; +- +- spi-flash@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "n25q128a13", +- "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <108000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0 0x400000>; +- }; +- partition@400000 { +- label = "Filesystem"; +- reg = <0x400000 0xc00000>; +- }; +- }; +- }; +-}; +- +-&nand_controller { +- status = "okay"; +- pinctrl-0 = <&nand_pins>; +- pinctrl-names = "default"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- marvell,nand-keep-config; +- nand-on-flash-bbt; +- nand-ecc-strength = <8>; +- nand-ecc-step-size = <512>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0 0x800000>; +- }; +- partition@800000 { +- label = "Linux"; +- reg = <0x800000 0x800000>; +- }; +- partition@1000000 { +- label = "Filesystem"; +- reg = <0x1000000 0x3f000000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-390.dtsi b/scripts/dtc/include-prefixes/arm/armada-390.dtsi +deleted file mode 100644 +index aa2057d4d6f8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-390.dtsi ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell Armada 390 SoC. +- * +- * Copyright (C) 2015 Marvell +- * +- * Thomas Petazzoni +- */ +- +-#include "armada-39x.dtsi" +- +-/ { +- compatible = "marvell,armada390"; +- +- soc { +- internal-regs { +- pinctrl@18000 { +- compatible = "marvell,mv88f6920-pinctrl"; +- reg = <0x18000 0x20>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-395-gp.dts b/scripts/dtc/include-prefixes/arm/armada-395-gp.dts +deleted file mode 100644 +index 6dd9e9077f84..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-395-gp.dts ++++ /dev/null +@@ -1,136 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for Marvell Armada 395 GP board +- * +- * Copyright (C) 2016 Marvell +- * +- * Grzegorz Jaszczyk +- */ +- +-/dts-v1/; +-#include "armada-395.dtsi" +- +-/ { +- model = "Marvell Armada 395 GP Board"; +- compatible = "marvell,a395-gp", "marvell,armada395", +- "marvell,armada390"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x40000000>; /* 1 GB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- i2c@11000 { +- status = "okay"; +- clock-frequency = <100000>; +- +- eeprom@57 { +- compatible = "atmel,24c64"; +- reg = <0x57>; +- }; +- }; +- +- serial@12000 { +- /* +- * Exported on the micro USB connector CON17 +- * through an FTDI +- */ +- status = "okay"; +- }; +- +- /* CON1 */ +- usb@58000 { +- status = "okay"; +- }; +- +- /* CON2 */ +- sata@a8000 { +- status = "okay"; +- }; +- +- /* CON18 */ +- sdhci@d8000 { +- clock-frequency = <200000000>; +- broken-cd; +- wp-inverted; +- bus-width = <8>; +- status = "okay"; +- no-1-8-v; +- }; +- +- /* CON4 */ +- usb3@f0000 { +- status = "okay"; +- }; +- }; +- +- pcie { +- status = "okay"; +- +- /* +- * The two PCIe units are accessible through +- * mini PCIe slot on the board. +- */ +- +- /* CON7 */ +- pcie@2,0 { +- /* Port 1, Lane 0 */ +- status = "okay"; +- }; +- +- /* CON8 */ +- pcie@4,0 { +- /* Port 3, Lane 0 */ +- status = "okay"; +- }; +- }; +- }; +-}; +- +-&nand_controller { +- status = "okay"; +- pinctrl-0 = <&nand_pins>; +- pinctrl-names = "default"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- marvell,nand-keep-config; +- nand-on-flash-bbt; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0x00000000 0x00600000>; +- read-only; +- }; +- +- partition@800000 { +- label = "uImage"; +- reg = <0x00600000 0x00400000>; +- read-only; +- }; +- +- partition@1000000 { +- label = "Root"; +- reg = <0x00a00000 0x3f600000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-395.dtsi b/scripts/dtc/include-prefixes/arm/armada-395.dtsi +deleted file mode 100644 +index e18a7d9cd7d4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-395.dtsi ++++ /dev/null +@@ -1,39 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell Armada 395 SoC. +- * +- * Copyright (C) 2016 Marvell +- * +- * Grzegorz Jaszczyk +- */ +- +-#include "armada-39x.dtsi" +- +-/ { +- compatible = "marvell,armada395", "marvell,armada390"; +- +- soc { +- internal-regs { +- pinctrl@18000 { +- compatible = "marvell,mv88f6925-pinctrl"; +- reg = <0x18000 0x20>; +- }; +- +- sata@a8000 { +- compatible = "marvell,armada-380-ahci"; +- reg = <0xa8000 0x2000>; +- interrupts = ; +- clocks = <&gateclk 15>; +- status = "disabled"; +- }; +- +- usb3@f0000 { +- compatible = "marvell,armada-380-xhci"; +- reg = <0xf0000 0x4000>,<0xf4000 0x4000>; +- interrupts = ; +- clocks = <&gateclk 9>; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-398-db.dts b/scripts/dtc/include-prefixes/arm/armada-398-db.dts +deleted file mode 100644 +index fc28308e5bc5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-398-db.dts ++++ /dev/null +@@ -1,134 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell Armada 398 Development Board +- * +- * Copyright (C) 2015 Marvell +- * +- * Thomas Petazzoni +- */ +- +-/dts-v1/; +-#include "armada-398.dtsi" +- +-/ { +- model = "Marvell Armada 398 Development Board"; +- compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x80000000>; /* 2 GB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- i2c@11000 { +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- serial@12000 { +- pinctrl-0 = <&uart0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- +- serial@12100 { +- pinctrl-0 = <&uart1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- +- usb@58000 { +- status = "okay"; +- }; +- +- usb3@f8000 { +- status = "okay"; +- }; +- }; +- +- pcie { +- status = "okay"; +- +- pcie@1,0 { +- status = "okay"; +- }; +- +- pcie@2,0 { +- status = "okay"; +- }; +- +- pcie@3,0 { +- status = "okay"; +- }; +- }; +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-0 = <&spi1_pins>; +- pinctrl-names = "default"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "n25q128a13", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <108000000>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0 0x400000>; +- }; +- +- partition@400000 { +- label = "Filesystem"; +- reg = <0x400000 0x1000000>; +- }; +- }; +-}; +- +-&nand_controller { +- status = "okay"; +- pinctrl-0 = <&nand_pins>; +- pinctrl-names = "default"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- marvell,nand-keep-config; +- nand-on-flash-bbt; +- nand-ecc-strength = <8>; +- nand-ecc-step-size = <512>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0 0x800000>; +- }; +- partition@800000 { +- label = "Linux"; +- reg = <0x800000 0x800000>; +- }; +- partition@1000000 { +- label = "Filesystem"; +- reg = <0x1000000 0x3f000000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-398.dtsi b/scripts/dtc/include-prefixes/arm/armada-398.dtsi +deleted file mode 100644 +index c5ac89399ce1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-398.dtsi ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell Armada 398 SoC. +- * +- * Copyright (C) 2015 Marvell +- * +- * Thomas Petazzoni +- */ +- +-#include "armada-395.dtsi" +- +-/ { +- compatible = "marvell,armada398", "marvell,armada390"; +- +- soc { +- internal-regs { +- pinctrl@18000 { +- compatible = "marvell,mv88f6928-pinctrl"; +- reg = <0x18000 0x20>; +- }; +- +- sata@e0000 { +- compatible = "marvell,armada-380-ahci"; +- reg = <0xe0000 0x2000>; +- interrupts = ; +- clocks = <&gateclk 30>; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-39x.dtsi b/scripts/dtc/include-prefixes/arm/armada-39x.dtsi +deleted file mode 100644 +index e0b7c2099831..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-39x.dtsi ++++ /dev/null +@@ -1,554 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell Armada 39x family of SoCs. +- * +- * Copyright (C) 2015 Marvell +- * +- * Thomas Petazzoni +- */ +- +-#include +-#include +- +-#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Marvell Armada 39x family SoC"; +- compatible = "marvell,armada390"; +- +- aliases { +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "marvell,armada-390-smp"; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- }; +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <1>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts-extended = <&mpic 3>; +- }; +- +- soc { +- compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus", +- "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- controller = <&mbusc>; +- interrupt-parent = <&gic>; +- pcie-mem-aperture = <0xe0000000 0x8000000>; +- pcie-io-aperture = <0xe8000000 0x100000>; +- +- bootrom { +- compatible = "marvell,bootrom"; +- reg = ; +- }; +- +- internal-regs { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; +- +- L2: cache-controller@8000 { +- compatible = "arm,pl310-cache"; +- reg = <0x8000 0x1000>; +- cache-unified; +- cache-level = <2>; +- arm,double-linefill-incr = <0>; +- arm,double-linefill-wrap = <0>; +- arm,double-linefill = <0>; +- prefetch-data = <1>; +- }; +- +- scu@c000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0xc000 0x100>; +- }; +- +- timer@c600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0xc600 0x20>; +- interrupts = ; +- clocks = <&coreclk 2>; +- }; +- +- gic: interrupt-controller@d000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #size-cells = <0>; +- interrupt-controller; +- reg = <0xd000 0x1000>, +- <0xc100 0x100>; +- }; +- +- i2c0: i2c@11000 { +- compatible = "marvell,mv64xxx-i2c"; +- reg = <0x11000 0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@11100 { +- compatible = "marvell,mv64xxx-i2c"; +- reg = <0x11100 0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@11200 { +- compatible = "marvell,mv64xxx-i2c"; +- reg = <0x11200 0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@11300 { +- compatible = "marvell,mv64xxx-i2c"; +- reg = <0x11300 0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- uart0: serial@12000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x12000 0x100>; +- reg-shift = <2>; +- interrupts = ; +- reg-io-width = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- uart1: serial@12100 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x12100 0x100>; +- reg-shift = <2>; +- interrupts = ; +- reg-io-width = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- uart2: serial@12200 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x12200 0x100>; +- reg-shift = <2>; +- interrupts = ; +- reg-io-width = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- uart3: serial@12300 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x12300 0x100>; +- reg-shift = <2>; +- interrupts = ; +- reg-io-width = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- pinctrl@18000 { +- i2c0_pins: i2c0-pins { +- marvell,pins = "mpp2", "mpp3"; +- marvell,function = "i2c0"; +- }; +- +- uart0_pins: uart0-pins { +- marvell,pins = "mpp0", "mpp1"; +- marvell,function = "ua0"; +- }; +- +- uart1_pins: uart1-pins { +- marvell,pins = "mpp19", "mpp20"; +- marvell,function = "ua1"; +- }; +- +- spi1_pins: spi1-pins { +- marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59"; +- marvell,function = "spi1"; +- }; +- +- nand_pins: nand-pins { +- marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33", +- "mpp38", "mpp28", "mpp40", "mpp42", +- "mpp35", "mpp36", "mpp25", "mpp30", +- "mpp32"; +- marvell,function = "dev"; +- }; +- }; +- +- gpio0: gpio@18100 { +- compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; +- ngpios = <32>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = , +- , +- , +- ; +- }; +- +- gpio1: gpio@18140 { +- compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; +- ngpios = <28>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = , +- , +- , +- ; +- }; +- +- system-controller@18200 { +- compatible = "marvell,armada-390-system-controller", +- "marvell,armada-370-xp-system-controller"; +- reg = <0x18200 0x100>; +- }; +- +- gateclk: clock-gating-control@18220 { +- compatible = "marvell,armada-390-gating-clock"; +- reg = <0x18220 0x4>; +- clocks = <&coreclk 0>; +- #clock-cells = <1>; +- }; +- +- coreclk: mvebu-sar@18600 { +- compatible = "marvell,armada-390-core-clock"; +- reg = <0x18600 0x04>; +- #clock-cells = <1>; +- }; +- +- mbusc: mbus-controller@20000 { +- compatible = "marvell,mbus-controller"; +- reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; +- }; +- +- mpic: interrupt-controller@20a00 { +- compatible = "marvell,mpic"; +- reg = <0x20a00 0x2d0>, <0x21070 0x58>; +- #interrupt-cells = <1>; +- #size-cells = <1>; +- interrupt-controller; +- msi-controller; +- interrupts = ; +- }; +- +- timer@20300 { +- compatible = "marvell,armada-380-timer", +- "marvell,armada-xp-timer"; +- reg = <0x20300 0x30>, <0x21040 0x30>; +- interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, +- <&mpic 5>, +- <&mpic 6>; +- clocks = <&coreclk 2>, <&coreclk 5>; +- clock-names = "nbclk", "fixed"; +- }; +- +- watchdog@20300 { +- compatible = "marvell,armada-380-wdt"; +- reg = <0x20300 0x34>, <0x20704 0x4>, +- <0x18260 0x4>; +- clocks = <&coreclk 2>, <&refclk>; +- clock-names = "nbclk", "fixed"; +- }; +- +- cpurst@20800 { +- compatible = "marvell,armada-370-cpu-reset"; +- reg = <0x20800 0x10>; +- }; +- +- mpcore-soc-ctrl@20d20 { +- compatible = "marvell,armada-380-mpcore-soc-ctrl"; +- reg = <0x20d20 0x6c>; +- }; +- +- coherency-fabric@21010 { +- compatible = "marvell,armada-380-coherency-fabric"; +- reg = <0x21010 0x1c>; +- }; +- +- pmsu@22000 { +- compatible = "marvell,armada-390-pmsu", +- "marvell,armada-380-pmsu"; +- reg = <0x22000 0x1000>; +- }; +- +- xor@60800 { +- compatible = "marvell,armada-380-xor", "marvell,orion-xor"; +- reg = <0x60800 0x100 +- 0x60a00 0x100>; +- clocks = <&gateclk 22>; +- status = "okay"; +- +- xor00 { +- interrupts = ; +- dmacap,memcpy; +- dmacap,xor; +- }; +- xor01 { +- interrupts = ; +- dmacap,memcpy; +- dmacap,xor; +- dmacap,memset; +- }; +- }; +- +- xor@60900 { +- compatible = "marvell,armada-380-xor", "marvell,orion-xor"; +- reg = <0x60900 0x100 +- 0x60b00 0x100>; +- clocks = <&gateclk 28>; +- status = "okay"; +- +- xor10 { +- interrupts = ; +- dmacap,memcpy; +- dmacap,xor; +- }; +- xor11 { +- interrupts = ; +- dmacap,memcpy; +- dmacap,xor; +- dmacap,memset; +- }; +- }; +- +- rtc@a3800 { +- compatible = "marvell,armada-380-rtc"; +- reg = <0xa3800 0x20>, <0x184a0 0x0c>; +- reg-names = "rtc", "rtc-soc"; +- interrupts = ; +- }; +- +- nand_controller: nand-controller@d0000 { +- compatible = "marvell,armada370-nand-controller"; +- reg = <0xd0000 0x54>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&coredivclk 0>; +- status = "disabled"; +- }; +- +- sdhci@d8000 { +- compatible = "marvell,armada-380-sdhci"; +- reg-names = "sdhci", "mbus", "conf-sdio3"; +- reg = <0xd8000 0x1000>, +- <0xdc000 0x100>, +- <0x18454 0x4>; +- interrupts = ; +- clocks = <&gateclk 17>; +- mrvl,clk-delay-cycles = <0x1F>; +- status = "disabled"; +- }; +- +- coredivclk: clock@e4250 { +- compatible = "marvell,armada-390-corediv-clock", +- "marvell,armada-380-corediv-clock"; +- reg = <0xe4250 0xc>; +- #clock-cells = <1>; +- clocks = <&mainpll>; +- clock-output-names = "nand"; +- }; +- +- thermal@e8078 { +- compatible = "marvell,armada380-thermal"; +- reg = <0xe4078 0x4>, <0xe4074 0x4>; +- status = "okay"; +- }; +- }; +- +- pcie { +- compatible = "marvell,armada-370-pcie"; +- status = "disabled"; +- device_type = "pci"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- msi-parent = <&mpic>; +- bus-range = <0x00 0xff>; +- +- ranges = +- <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 +- 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 +- 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 +- 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 +- 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ +- 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ +- 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ +- 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ +- 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ +- 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ +- 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ +- 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; +- +- /* +- * This port can be either x4 or x1. When +- * configured in x4 by the bootloader, then +- * pcie@4,0 is not available. +- */ +- pcie@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 +- 0x81000000 0 0 0x81000000 0x1 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 8>; +- status = "disabled"; +- }; +- +- /* x1 port */ +- pcie@2,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; +- reg = <0x1000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 +- 0x81000000 0 0 0x81000000 0x2 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 5>; +- status = "disabled"; +- }; +- +- /* x1 port */ +- pcie@3,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; +- reg = <0x1800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 +- 0x81000000 0 0 0x81000000 0x3 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; +- marvell,pcie-port = <2>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 6>; +- status = "disabled"; +- }; +- +- /* +- * x1 port only available when pcie@1,0 is +- * configured as a x1 port +- */ +- pcie@4,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; +- reg = <0x2000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 +- 0x81000000 0 0 0x81000000 0x4 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; +- marvell,pcie-port = <3>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 7>; +- status = "disabled"; +- }; +- }; +- +- spi0: spi@10600 { +- compatible = "marvell,armada-390-spi", +- "marvell,orion-spi"; +- reg = ; +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- interrupts = ; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- spi1: spi@10680 { +- compatible = "marvell,armada-390-spi", +- "marvell,orion-spi"; +- reg = ; +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- interrupts = ; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- }; +- +- clocks { +- /* 1 GHz fixed main PLL */ +- mainpll: mainpll { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <1000000000>; +- }; +- +- /* 25 MHz reference crystal */ +- refclk: oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-98dx3236.dtsi b/scripts/dtc/include-prefixes/arm/armada-xp-98dx3236.dtsi +deleted file mode 100644 +index 38a052a0312d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-98dx3236.dtsi ++++ /dev/null +@@ -1,348 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell 98dx3236 family SoC +- * +- * Copyright (C) 2016 Allied Telesis Labs +- * +- * Contains definitions specific to the 98dx3236 SoC that are not +- * common to all Armada XP SoCs. +- */ +- +-#include "armada-370-xp.dtsi" +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- +- model = "Marvell 98DX3236 SoC"; +- compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; +- +- aliases { +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- gpio2 = &gpio2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "marvell,98dx3236-smp"; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "marvell,sheeva-v7"; +- reg = <0>; +- clocks = <&cpuclk 0>; +- clock-latency = <1000000>; +- }; +- }; +- +- soc { +- compatible = "marvell,armadaxp-mbus", "simple-bus"; +- +- ranges = ; +- +- bootrom { +- compatible = "marvell,bootrom"; +- reg = ; +- }; +- +- /* +- * 98DX3236 has 1 x1 PCIe unit Gen2.0 +- */ +- pciec: pcie@82000000 { +- compatible = "marvell,armada-xp-pcie"; +- status = "disabled"; +- device_type = "pci"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- msi-parent = <&mpic>; +- bus-range = <0x00 0xff>; +- +- ranges = +- <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ +- 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ +- 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; +- +- pcie1: pcie@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 +- 0x81000000 0 0 0x81000000 0x1 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 58>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 5>; +- status = "disabled"; +- }; +- }; +- +- internal-regs { +- sdramc: sdramc@1400 { +- compatible = "marvell,armada-xp-sdram-controller"; +- reg = <0x1400 0x500>; +- }; +- +- L2: l2-cache@8000 { +- compatible = "marvell,aurora-system-cache"; +- reg = <0x08000 0x1000>; +- cache-id-part = <0x100>; +- cache-level = <2>; +- cache-unified; +- wt-override; +- }; +- +- gpio0: gpio@18100 { +- compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; +- ngpios = <32>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <82>, <83>, <84>, <85>; +- }; +- +- /* does not exist */ +- gpio1: gpio@18140 { +- compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; +- status = "disabled"; +- }; +- +- gpio2: gpio@18180 { /* rework some properties */ +- compatible = "marvell,orion-gpio"; +- reg = <0x18180 0x40>; +- ngpios = <1>; /* only gpio #32 */ +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <87>; +- }; +- +- systemc: system-controller@18200 { +- compatible = "marvell,armada-370-xp-system-controller"; +- reg = <0x18200 0x500>; +- }; +- +- gateclk: clock-gating-control@18220 { +- compatible = "marvell,mv98dx3236-gating-clock"; +- reg = <0x18220 0x4>; +- clocks = <&coreclk 0>; +- #clock-cells = <1>; +- }; +- +- cpuclk: clock-complex@18700 { +- #clock-cells = <1>; +- compatible = "marvell,mv98dx3236-cpu-clock"; +- reg = <0x18700 0x24>, <0x1c054 0x10>; +- clocks = <&coreclk 1>; +- }; +- +- corediv-clock@18740 { +- status = "disabled"; +- }; +- +- cpu-config@21000 { +- compatible = "marvell,armada-xp-cpu-config"; +- reg = <0x21000 0x8>; +- }; +- +- ethernet@70000 { +- compatible = "marvell,armada-xp-neta"; +- }; +- +- ethernet@74000 { +- compatible = "marvell,armada-xp-neta"; +- }; +- +- xor1: xor@f0800 { +- compatible = "marvell,orion-xor"; +- reg = <0xf0800 0x100 +- 0xf0a00 0x100>; +- clocks = <&gateclk 22>; +- status = "okay"; +- +- xor10 { +- interrupts = <51>; +- dmacap,memcpy; +- dmacap,xor; +- }; +- xor11 { +- interrupts = <52>; +- dmacap,memcpy; +- dmacap,xor; +- dmacap,memset; +- }; +- }; +- +- nand_controller: nand-controller@d0000 { +- clocks = <&dfx_coredivclk 0>; +- }; +- +- xor0: xor@f0900 { +- compatible = "marvell,orion-xor"; +- reg = <0xF0900 0x100 +- 0xF0B00 0x100>; +- clocks = <&gateclk 28>; +- status = "okay"; +- +- xor00 { +- interrupts = <94>; +- dmacap,memcpy; +- dmacap,xor; +- }; +- xor01 { +- interrupts = <95>; +- dmacap,memcpy; +- dmacap,xor; +- dmacap,memset; +- }; +- }; +- }; +- +- dfx: dfx-server@ac000000 { +- compatible = "marvell,dfx-server", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; +- reg = ; +- +- coreclk: mvebu-sar@f8204 { +- compatible = "marvell,mv98dx3236-core-clock"; +- reg = <0xf8204 0x4>; +- #clock-cells = <1>; +- }; +- +- dfx_coredivclk: corediv-clock@f8268 { +- compatible = "marvell,mv98dx3236-corediv-clock"; +- reg = <0xf8268 0xc>; +- #clock-cells = <1>; +- clocks = <&mainpll>; +- clock-output-names = "nand"; +- }; +- }; +- +- switch: switch@a8000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>; +- +- pp0: packet-processor@0 { +- compatible = "marvell,prestera-98dx3236", "marvell,prestera"; +- reg = <0 0x4000000>; +- interrupts = <33>, <34>, <35>; +- dfx = <&dfx>; +- }; +- }; +- }; +- +- clocks { +- /* 25 MHz reference crystal */ +- refclk: oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- }; +-}; +- +-&i2c0 { +- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; +- reg = <0x11000 0x100>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +-}; +- +-&mpic { +- reg = <0x20a00 0x2d0>, <0x21070 0x58>; +-}; +- +-&rtc { +- status = "disabled"; +-}; +- +-&timer { +- compatible = "marvell,armada-xp-timer"; +- clocks = <&coreclk 2>, <&refclk>; +- clock-names = "nbclk", "fixed"; +-}; +- +-&watchdog { +- compatible = "marvell,armada-xp-wdt"; +- clocks = <&coreclk 2>, <&refclk>; +- clock-names = "nbclk", "fixed"; +-}; +- +-&cpurst { +- reg = <0x20800 0x20>; +-}; +- +-&usb0 { +- clocks = <&gateclk 18>; +-}; +- +-&usb1 { +- clocks = <&gateclk 19>; +-}; +- +-&pinctrl { +- compatible = "marvell,98dx3236-pinctrl"; +- +- nand_pins: nand-pins { +- marvell,pins = "mpp20", "mpp21", "mpp22", +- "mpp23", "mpp24", "mpp25", +- "mpp26", "mpp27", "mpp28", +- "mpp29", "mpp30"; +- marvell,function = "dev"; +- }; +- +- nand_rb: nand-rb { +- marvell,pins = "mpp19"; +- marvell,function = "nand"; +- }; +- +- spi0_pins: spi0-pins { +- marvell,pins = "mpp0", "mpp1", +- "mpp2", "mpp3"; +- marvell,function = "spi0"; +- }; +- +- i2c0_pins: i2c-pins-0 { +- marvell,pins = "mpp14", "mpp15"; +- marvell,function = "i2c0"; +- }; +-}; +- +-&spi0 { +- compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; +- pinctrl-0 = <&spi0_pins>; +- pinctrl-names = "default"; +-}; +- +-&sdio { +- status = "disabled"; +-}; +- +-&uart0 { +- compatible = "marvell,armada-38x-uart"; +-}; +- +-&uart1 { +- compatible = "marvell,armada-38x-uart"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-98dx3336.dtsi b/scripts/dtc/include-prefixes/arm/armada-xp-98dx3336.dtsi +deleted file mode 100644 +index 1d9d8a8ea60c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-98dx3336.dtsi ++++ /dev/null +@@ -1,39 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell 98dx3336 family SoC +- * +- * Copyright (C) 2016 Allied Telesis Labs +- * +- * Contains definitions specific to the 98dx3236 SoC that are not +- * common to all Armada XP SoCs. +- */ +- +-#include "armada-xp-98dx3236.dtsi" +- +-/ { +- model = "Marvell 98DX3336 SoC"; +- compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; +- +- cpus { +- cpu@1 { +- device_type = "cpu"; +- compatible = "marvell,sheeva-v7"; +- reg = <1>; +- clocks = <&cpuclk 1>; +- clock-latency = <1000000>; +- }; +- }; +- +- soc { +- internal-regs { +- resume@20980 { +- compatible = "marvell,98dx3336-resume-ctrl"; +- reg = <0x20980 0x10>; +- }; +- }; +- }; +-}; +- +-&pp0 { +- compatible = "marvell,prestera-98dx3336", "marvell,prestera"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-98dx4251.dtsi b/scripts/dtc/include-prefixes/arm/armada-xp-98dx4251.dtsi +deleted file mode 100644 +index 48ffdc72bfc7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-98dx4251.dtsi ++++ /dev/null +@@ -1,54 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell 98dx4521 family SoC +- * +- * Copyright (C) 2016 Allied Telesis Labs +- * +- * Contains definitions specific to the 98dx4521 SoC that are not +- * common to all Armada XP SoCs. +- */ +- +-#include "armada-xp-98dx3236.dtsi" +- +-/ { +- model = "Marvell 98DX4251 SoC"; +- compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; +- +- cpus { +- cpu@1 { +- device_type = "cpu"; +- compatible = "marvell,sheeva-v7"; +- reg = <1>; +- clocks = <&cpuclk 1>; +- clock-latency = <1000000>; +- }; +- }; +- +- soc { +- internal-regs { +- resume@20980 { +- compatible = "marvell,98dx3336-resume-ctrl"; +- reg = <0x20980 0x10>; +- }; +- }; +- }; +-}; +- +-&sdio { +- status = "okay"; +-}; +- +-&pinctrl { +- compatible = "marvell,98dx4251-pinctrl"; +- +- sdio_pins: sdio-pins { +- marvell,pins = "mpp5", "mpp6", "mpp7", +- "mpp8", "mpp9", "mpp10"; +- marvell,function = "sd0"; +- }; +-}; +- +-&pp0 { +- compatible = "marvell,prestera-98dx4251", "marvell,prestera"; +- interrupts = <33>, <34>, <35>, <36>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-axpwifiap.dts b/scripts/dtc/include-prefixes/arm/armada-xp-axpwifiap.dts +deleted file mode 100644 +index 606fd3476a59..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-axpwifiap.dts ++++ /dev/null +@@ -1,144 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Marvell RD-AXPWiFiAP. +- * +- * Note: this board is shipped with a new generation boot loader that +- * remaps internal registers at 0xf1000000. Therefore, if earlyprintk +- * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option or the +- * CONFIG_DEBUG_MVEBU_UART1_ALTERNATE option should be used. +- * +- * Copyright (C) 2013 Marvell +- * +- * Thomas Petazzoni +- */ +- +-/dts-v1/; +-#include +-#include +-#include "armada-xp-mv78230.dtsi" +- +-/ { +- model = "Marvell RD-AXPWiFiAP"; +- compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- /* UART0 */ +- serial@12000 { +- status = "okay"; +- }; +- +- /* UART1 */ +- serial@12100 { +- status = "okay"; +- }; +- +- sata@a0000 { +- nr-ports = <1>; +- status = "okay"; +- }; +- +- ethernet@70000 { +- pinctrl-0 = <&ge0_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +- }; +- ethernet@74000 { +- pinctrl-0 = <&ge1_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy = <&phy1>; +- phy-mode = "rgmii-id"; +- }; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&keys_pin>; +- pinctrl-names = "default"; +- +- reset { +- label = "Factory Reset Button"; +- linux,code = ; +- gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&mdio { +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&pciec { +- status = "okay"; +- +- /* First mini-PCIe port */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- +- /* Second mini-PCIe port */ +- pcie@2,0 { +- /* Port 0, Lane 1 */ +- status = "okay"; +- }; +- +- /* Renesas uPD720202 USB 3.0 controller */ +- pcie@3,0 { +- /* Port 0, Lane 3 */ +- status = "okay"; +- }; +-}; +- +-&pinctrl { +- pinctrl-0 = <&phy_int_pin>; +- pinctrl-names = "default"; +- +- keys_pin: keys-pin { +- marvell,pins = "mpp33"; +- marvell,function = "gpio"; +- }; +- +- phy_int_pin: phy-int-pin { +- marvell,pins = "mpp32"; +- marvell,function = "gpio"; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "n25q128a13", "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <108000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-crs305-1g-4s-bit.dts b/scripts/dtc/include-prefixes/arm/armada-xp-crs305-1g-4s-bit.dts +deleted file mode 100644 +index a022c68dc943..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-crs305-1g-4s-bit.dts ++++ /dev/null +@@ -1,43 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for MikroTik CRS305-1G-4S+ Bit board +- * +- * Copyright (C) 2020 Sartura Ltd. +- * Author: Luka Kovacic +- */ +- +-#include "armada-xp-crs305-1g-4s.dtsi" +- +-/ { +- model = "MikroTik CRS305-1G-4S+ Bit"; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <108000000>; +- m25p,fast-read; +- +- partition@u-boot { +- reg = <0x00000000 0x001f0000>; +- label = "u-boot"; +- }; +- partition@u-boot-env { +- reg = <0x001f0000 0x00010000>; +- label = "u-boot-env"; +- }; +- partition@ubi1 { +- reg = <0x00200000 0x03f00000>; +- label = "ubi1"; +- }; +- partition@ubi2 { +- reg = <0x04100000 0x03f00000>; +- label = "ubi2"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-crs305-1g-4s.dts b/scripts/dtc/include-prefixes/arm/armada-xp-crs305-1g-4s.dts +deleted file mode 100644 +index 010b83b54212..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-crs305-1g-4s.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for MikroTik CRS305-1G-4S+ board +- * +- * Copyright (C) 2020 Sartura Ltd. +- * Author: Luka Kovacic +- */ +- +-#include "armada-xp-crs305-1g-4s.dtsi" +- +-/ { +- model = "MikroTik CRS305-1G-4S+"; +-}; +- +-&spi0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-crs305-1g-4s.dtsi b/scripts/dtc/include-prefixes/arm/armada-xp-crs305-1g-4s.dtsi +deleted file mode 100644 +index 32fb21b2bf6a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-crs305-1g-4s.dtsi ++++ /dev/null +@@ -1,104 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for CRS305-1G-4S board +- * +- * Copyright (C) 2016 Allied Telesis Labs +- * Copyright (C) 2020 Sartura Ltd. +- * +- * Based on armada-xp-db.dts +- * +- * Note: this Device Tree assumes that the bootloader has remapped the +- * internal registers to 0xf1000000 (instead of the default +- * 0xd0000000). The 0xf1000000 is the default used by the recent, +- * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier +- * boards were delivered with an older version of the bootloader that +- * left internal registers mapped at 0xd0000000. If you are in this +- * situation, you should either update your bootloader (preferred +- * solution) or the below Device Tree should be adjusted. +- */ +- +-/dts-v1/; +-#include "armada-xp-98dx3236.dtsi" +- +-/ { +- model = "CRS305-1G-4S+"; +- compatible = "mikrotik,crs305-1g-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; +- +- chosen { +- bootargs = "console=ttyS0,115200 earlyprintk"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ +- }; +-}; +- +-&L2 { +- arm,parity-enable; +- marvell,ecc-enable; +-}; +- +-&devbus_bootcs { +- status = "okay"; +- +- /* Device Bus parameters are required */ +- +- /* Read parameters */ +- devbus,bus-width = <16>; +- devbus,turn-off-ps = <60000>; +- devbus,badr-skew-ps = <0>; +- devbus,acc-first-ps = <124000>; +- devbus,acc-next-ps = <248000>; +- devbus,rd-setup-ps = <0>; +- devbus,rd-hold-ps = <0>; +- +- /* Write parameters */ +- devbus,sync-enable = <0>; +- devbus,wr-high-ps = <60000>; +- devbus,wr-low-ps = <60000>; +- devbus,ale-wr-ps = <60000>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <108000000>; +- m25p,fast-read; +- +- partition@u-boot { +- reg = <0x00000000 0x001f0000>; +- label = "u-boot"; +- }; +- partition@u-boot-env { +- reg = <0x001f0000 0x00010000>; +- label = "u-boot-env"; +- }; +- partition@ubi1 { +- reg = <0x00200000 0x00e00000>; +- label = "ubi1"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-crs326-24g-2s-bit.dts b/scripts/dtc/include-prefixes/arm/armada-xp-crs326-24g-2s-bit.dts +deleted file mode 100644 +index 21f442afab1f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-crs326-24g-2s-bit.dts ++++ /dev/null +@@ -1,43 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for MikroTik CRS326-24G-2S+ Bit board +- * +- * Copyright (C) 2020 Sartura Ltd. +- * Author: Luka Kovacic +- */ +- +-#include "armada-xp-crs326-24g-2s.dtsi" +- +-/ { +- model = "MikroTik CRS326-24G-2S+ Bit"; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <108000000>; +- m25p,fast-read; +- +- partition@u-boot { +- reg = <0x00000000 0x001f0000>; +- label = "u-boot"; +- }; +- partition@u-boot-env { +- reg = <0x001f0000 0x00010000>; +- label = "u-boot-env"; +- }; +- partition@ubi1 { +- reg = <0x00200000 0x03f00000>; +- label = "ubi1"; +- }; +- partition@ubi2 { +- reg = <0x04100000 0x03f00000>; +- label = "ubi2"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-crs326-24g-2s.dts b/scripts/dtc/include-prefixes/arm/armada-xp-crs326-24g-2s.dts +deleted file mode 100644 +index 83aef43f66d5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-crs326-24g-2s.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for MikroTik CRS326-24G-2S+ board +- * +- * Copyright (C) 2020 Sartura Ltd. +- * Author: Luka Kovacic +- */ +- +-#include "armada-xp-crs326-24g-2s.dtsi" +- +-/ { +- model = "MikroTik CRS326-24G-2S+"; +-}; +- +-&spi0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-crs326-24g-2s.dtsi b/scripts/dtc/include-prefixes/arm/armada-xp-crs326-24g-2s.dtsi +deleted file mode 100644 +index f3e1a25ca5f2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-crs326-24g-2s.dtsi ++++ /dev/null +@@ -1,104 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for CRS326-24G-2S board +- * +- * Copyright (C) 2016 Allied Telesis Labs +- * Copyright (C) 2020 Sartura Ltd. +- * +- * Based on armada-xp-db.dts +- * +- * Note: this Device Tree assumes that the bootloader has remapped the +- * internal registers to 0xf1000000 (instead of the default +- * 0xd0000000). The 0xf1000000 is the default used by the recent, +- * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier +- * boards were delivered with an older version of the bootloader that +- * left internal registers mapped at 0xd0000000. If you are in this +- * situation, you should either update your bootloader (preferred +- * solution) or the below Device Tree should be adjusted. +- */ +- +-/dts-v1/; +-#include "armada-xp-98dx3236.dtsi" +- +-/ { +- model = "CRS326-24G-2S+"; +- compatible = "mikrotik,crs326-24g-2s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; +- +- chosen { +- bootargs = "console=ttyS0,115200 earlyprintk"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ +- }; +-}; +- +-&L2 { +- arm,parity-enable; +- marvell,ecc-enable; +-}; +- +-&devbus_bootcs { +- status = "okay"; +- +- /* Device Bus parameters are required */ +- +- /* Read parameters */ +- devbus,bus-width = <16>; +- devbus,turn-off-ps = <60000>; +- devbus,badr-skew-ps = <0>; +- devbus,acc-first-ps = <124000>; +- devbus,acc-next-ps = <248000>; +- devbus,rd-setup-ps = <0>; +- devbus,rd-hold-ps = <0>; +- +- /* Write parameters */ +- devbus,sync-enable = <0>; +- devbus,wr-high-ps = <60000>; +- devbus,wr-low-ps = <60000>; +- devbus,ale-wr-ps = <60000>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <108000000>; +- m25p,fast-read; +- +- partition@u-boot { +- reg = <0x00000000 0x001f0000>; +- label = "u-boot"; +- }; +- partition@u-boot-env { +- reg = <0x001f0000 0x00010000>; +- label = "u-boot-env"; +- }; +- partition@ubi1 { +- reg = <0x00200000 0x00e00000>; +- label = "ubi1"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-crs328-4c-20s-4s-bit.dts b/scripts/dtc/include-prefixes/arm/armada-xp-crs328-4c-20s-4s-bit.dts +deleted file mode 100644 +index e05aee6cdc04..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-crs328-4c-20s-4s-bit.dts ++++ /dev/null +@@ -1,43 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for MikroTik CRS328-4C-20S-4S+ Bit board +- * +- * Copyright (C) 2020 Sartura Ltd. +- * Author: Luka Kovacic +- */ +- +-#include "armada-xp-crs328-4c-20s-4s.dtsi" +- +-/ { +- model = "MikroTik CRS328-4C-20S-4S+ Bit"; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <108000000>; +- m25p,fast-read; +- +- partition@u-boot { +- reg = <0x00000000 0x001f0000>; +- label = "u-boot"; +- }; +- partition@u-boot-env { +- reg = <0x001f0000 0x00010000>; +- label = "u-boot-env"; +- }; +- partition@ubi1 { +- reg = <0x00200000 0x03f00000>; +- label = "ubi1"; +- }; +- partition@ubi2 { +- reg = <0x04100000 0x03f00000>; +- label = "ubi2"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-crs328-4c-20s-4s.dts b/scripts/dtc/include-prefixes/arm/armada-xp-crs328-4c-20s-4s.dts +deleted file mode 100644 +index 665757f6e18e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-crs328-4c-20s-4s.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for MikroTik CRS328-4C-20S-4S+ board +- * +- * Copyright (C) 2020 Sartura Ltd. +- * Author: Luka Kovacic +- */ +- +-#include "armada-xp-crs328-4c-20s-4s.dtsi" +- +-/ { +- model = "MikroTik CRS328-4C-20S-4S+"; +-}; +- +-&spi0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-crs328-4c-20s-4s.dtsi b/scripts/dtc/include-prefixes/arm/armada-xp-crs328-4c-20s-4s.dtsi +deleted file mode 100644 +index c8b1355ce15e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-crs328-4c-20s-4s.dtsi ++++ /dev/null +@@ -1,104 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for CRS328-4C-20S-4S+ board +- * +- * Copyright (C) 2016 Allied Telesis Labs +- * Copyright (C) 2020 Sartura Ltd. +- * +- * Based on armada-xp-db.dts +- * +- * Note: this Device Tree assumes that the bootloader has remapped the +- * internal registers to 0xf1000000 (instead of the default +- * 0xd0000000). The 0xf1000000 is the default used by the recent, +- * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier +- * boards were delivered with an older version of the bootloader that +- * left internal registers mapped at 0xd0000000. If you are in this +- * situation, you should either update your bootloader (preferred +- * solution) or the below Device Tree should be adjusted. +- */ +- +-/dts-v1/; +-#include "armada-xp-98dx3236.dtsi" +- +-/ { +- model = "CRS328-4C-20S-4S+"; +- compatible = "mikrotik,crs328-4c-20s-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; +- +- chosen { +- bootargs = "console=ttyS0,115200 earlyprintk"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ +- }; +-}; +- +-&L2 { +- arm,parity-enable; +- marvell,ecc-enable; +-}; +- +-&devbus_bootcs { +- status = "okay"; +- +- /* Device Bus parameters are required */ +- +- /* Read parameters */ +- devbus,bus-width = <16>; +- devbus,turn-off-ps = <60000>; +- devbus,badr-skew-ps = <0>; +- devbus,acc-first-ps = <124000>; +- devbus,acc-next-ps = <248000>; +- devbus,rd-setup-ps = <0>; +- devbus,rd-hold-ps = <0>; +- +- /* Write parameters */ +- devbus,sync-enable = <0>; +- devbus,wr-high-ps = <60000>; +- devbus,wr-low-ps = <60000>; +- devbus,ale-wr-ps = <60000>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <108000000>; +- m25p,fast-read; +- +- partition@u-boot { +- reg = <0x00000000 0x001f0000>; +- label = "u-boot"; +- }; +- partition@u-boot-env { +- reg = <0x001f0000 0x00010000>; +- label = "u-boot-env"; +- }; +- partition@ubi1 { +- reg = <0x00200000 0x00e00000>; +- label = "ubi1"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-db-dxbc2.dts b/scripts/dtc/include-prefixes/arm/armada-xp-db-dxbc2.dts +deleted file mode 100644 +index 8a3aa616bbd0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-db-dxbc2.dts ++++ /dev/null +@@ -1,118 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for DB-DXBC2 board +- * +- * Copyright (C) 2016 Allied Telesis Labs +- * +- * Based on armada-xp-db.dts +- * +- * Note: this Device Tree assumes that the bootloader has remapped the +- * internal registers to 0xf1000000 (instead of the default +- * 0xd0000000). The 0xf1000000 is the default used by the recent, +- * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier +- * boards were delivered with an older version of the bootloader that +- * left internal registers mapped at 0xd0000000. If you are in this +- * situation, you should either update your bootloader (preferred +- * solution) or the below Device Tree should be adjusted. +- */ +- +-/dts-v1/; +-#include "armada-xp-98dx4251.dtsi" +- +-/ { +- model = "Marvell Bobcat2 Evaluation Board"; +- compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp"; +- +- chosen { +- bootargs = "console=ttyS0,115200 earlyprintk"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ +- }; +- +-}; +- +-&devbus_bootcs { +- status = "okay"; +- +- /* Device Bus parameters are required */ +- +- /* Read parameters */ +- devbus,bus-width = <16>; +- devbus,turn-off-ps = <60000>; +- devbus,badr-skew-ps = <0>; +- devbus,acc-first-ps = <124000>; +- devbus,acc-next-ps = <248000>; +- devbus,rd-setup-ps = <0>; +- devbus,rd-hold-ps = <0>; +- +- /* Write parameters */ +- devbus,sync-enable = <0>; +- devbus,wr-high-ps = <60000>; +- devbus,wr-low-ps = <60000>; +- devbus,ale-wr-ps = <60000>; +-}; +- +-&i2c0 { +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- marvell,nand-keep-config; +- nand-on-flash-bbt; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- }; +-}; +- +-&sdio { +- pinctrl-0 = <&sdio_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- /* No CD or WP GPIOs */ +- broken-cd; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p64"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <20000000>; +- m25p,fast-read; +- +- partition@u-boot { +- reg = <0x00000000 0x00100000>; +- label = "u-boot"; +- }; +- partition@u-boot-env { +- reg = <0x00100000 0x00040000>; +- label = "u-boot-env"; +- }; +- partition@unused { +- reg = <0x00140000 0x00ec0000>; +- label = "unused"; +- }; +- +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-db-xc3-24g4xg.dts b/scripts/dtc/include-prefixes/arm/armada-xp-db-xc3-24g4xg.dts +deleted file mode 100644 +index 4ec0ae01b61d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-db-xc3-24g4xg.dts ++++ /dev/null +@@ -1,114 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for DB-XC3-24G4XG board +- * +- * Copyright (C) 2016 Allied Telesis Labs +- * +- * Based on armada-xp-db.dts +- * +- * Note: this Device Tree assumes that the bootloader has remapped the +- * internal registers to 0xf1000000 (instead of the default +- * 0xd0000000). The 0xf1000000 is the default used by the recent, +- * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier +- * boards were delivered with an older version of the bootloader that +- * left internal registers mapped at 0xd0000000. If you are in this +- * situation, you should either update your bootloader (preferred +- * solution) or the below Device Tree should be adjusted. +- */ +- +-/dts-v1/; +-#include "armada-xp-98dx3336.dtsi" +- +-/ { +- model = "DB-XC3-24G4XG"; +- compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp"; +- +- chosen { +- bootargs = "console=ttyS0,115200 earlyprintk"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0 0x00000000 0 0x40000000>; /* 1 GB */ +- }; +-}; +- +-&L2 { +- arm,parity-enable; +- marvell,ecc-enable; +-}; +- +-&devbus_bootcs { +- status = "okay"; +- +- /* Device Bus parameters are required */ +- +- /* Read parameters */ +- devbus,bus-width = <16>; +- devbus,turn-off-ps = <60000>; +- devbus,badr-skew-ps = <0>; +- devbus,acc-first-ps = <124000>; +- devbus,acc-next-ps = <248000>; +- devbus,rd-setup-ps = <0>; +- devbus,rd-hold-ps = <0>; +- +- /* Write parameters */ +- devbus,sync-enable = <0>; +- devbus,wr-high-ps = <60000>; +- devbus,wr-low-ps = <60000>; +- devbus,ale-wr-ps = <60000>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- marvell,nand-keep-config; +- nand-on-flash-bbt; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p64"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <20000000>; +- m25p,fast-read; +- +- partition@u-boot { +- reg = <0x00000000 0x00100000>; +- label = "u-boot"; +- }; +- partition@u-boot-env { +- reg = <0x00100000 0x00040000>; +- label = "u-boot-env"; +- }; +- partition@unused { +- reg = <0x00140000 0x00ec0000>; +- label = "unused"; +- }; +- +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-db.dts b/scripts/dtc/include-prefixes/arm/armada-xp-db.dts +deleted file mode 100644 +index 5d04dc68cf57..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-db.dts ++++ /dev/null +@@ -1,245 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Marvell Armada XP evaluation board +- * (DB-78460-BP) +- * +- * Copyright (C) 2012-2014 Marvell +- * +- * Lior Amsalem +- * Gregory CLEMENT +- * Thomas Petazzoni +- * +- * +- * Note: this Device Tree assumes that the bootloader has remapped the +- * internal registers to 0xf1000000 (instead of the default +- * 0xd0000000). The 0xf1000000 is the default used by the recent, +- * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier +- * boards were delivered with an older version of the bootloader that +- * left internal registers mapped at 0xd0000000. If you are in this +- * situation, you should either update your bootloader (preferred +- * solution) or the below Device Tree should be adjusted. +- */ +- +-/dts-v1/; +-#include "armada-xp-mv78460.dtsi" +- +-/ { +- model = "Marvell Armada XP Evaluation Board"; +- compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ +- }; +- +- soc { +- ranges = ; +- +- devbus-bootcs { +- status = "okay"; +- +- /* Device Bus parameters are required */ +- +- /* Read parameters */ +- devbus,bus-width = <16>; +- devbus,turn-off-ps = <60000>; +- devbus,badr-skew-ps = <0>; +- devbus,acc-first-ps = <124000>; +- devbus,acc-next-ps = <248000>; +- devbus,rd-setup-ps = <0>; +- devbus,rd-hold-ps = <0>; +- +- /* Write parameters */ +- devbus,sync-enable = <0>; +- devbus,wr-high-ps = <60000>; +- devbus,wr-low-ps = <60000>; +- devbus,ale-wr-ps = <60000>; +- +- /* NOR 16 MiB */ +- nor@0 { +- compatible = "cfi-flash"; +- reg = <0 0x1000000>; +- bank-width = <2>; +- }; +- }; +- +- internal-regs { +- serial@12000 { +- status = "okay"; +- }; +- serial@12100 { +- status = "okay"; +- }; +- serial@12200 { +- status = "okay"; +- }; +- serial@12300 { +- status = "okay"; +- }; +- +- sata@a0000 { +- nr-ports = <2>; +- status = "okay"; +- }; +- +- ethernet@70000 { +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +- buffer-manager = <&bm>; +- bm,pool-long = <0>; +- }; +- ethernet@74000 { +- status = "okay"; +- phy = <&phy1>; +- phy-mode = "rgmii-id"; +- buffer-manager = <&bm>; +- bm,pool-long = <1>; +- }; +- ethernet@30000 { +- status = "okay"; +- phy = <&phy2>; +- phy-mode = "sgmii"; +- buffer-manager = <&bm>; +- bm,pool-long = <2>; +- }; +- ethernet@34000 { +- status = "okay"; +- phy = <&phy3>; +- phy-mode = "sgmii"; +- buffer-manager = <&bm>; +- bm,pool-long = <3>; +- }; +- +- bm@c0000 { +- status = "okay"; +- }; +- +- mvsdio@d4000 { +- pinctrl-0 = <&sdio_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- /* No CD or WP GPIOs */ +- broken-cd; +- }; +- +- usb@50000 { +- status = "okay"; +- }; +- +- usb@51000 { +- status = "okay"; +- }; +- +- usb@52000 { +- status = "okay"; +- }; +- +- nand-controller@d0000 { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- nand-on-flash-bbt; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0 0x800000>; +- }; +- partition@800000 { +- label = "Linux"; +- reg = <0x800000 0x800000>; +- }; +- partition@1000000 { +- label = "Filesystem"; +- reg = <0x1000000 0x3f000000>; +- }; +- }; +- }; +- }; +- }; +- +- bm-bppi { +- status = "okay"; +- }; +- }; +-}; +- +-&pciec { +- status = "okay"; +- +- /* +- * All 6 slots are physically present as +- * standard PCIe slots on the board. +- */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- pcie@2,0 { +- /* Port 0, Lane 1 */ +- status = "okay"; +- }; +- pcie@3,0 { +- /* Port 0, Lane 2 */ +- status = "okay"; +- }; +- pcie@4,0 { +- /* Port 0, Lane 3 */ +- status = "okay"; +- }; +- pcie@9,0 { +- /* Port 2, Lane 0 */ +- status = "okay"; +- }; +- pcie@a,0 { +- /* Port 3, Lane 0 */ +- status = "okay"; +- }; +-}; +- +-&mdio { +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +- +- phy2: ethernet-phy@2 { +- reg = <25>; +- }; +- +- phy3: ethernet-phy@3 { +- reg = <27>; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p64", "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <20000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-gp.dts b/scripts/dtc/include-prefixes/arm/armada-xp-gp.dts +deleted file mode 100644 +index b4cca507cf13..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-gp.dts ++++ /dev/null +@@ -1,230 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Marvell Armada XP development board +- * (DB-MV784MP-GP) +- * +- * Copyright (C) 2013-2014 Marvell +- * +- * Lior Amsalem +- * Gregory CLEMENT +- * Thomas Petazzoni +- * +- * Note: this Device Tree assumes that the bootloader has remapped the +- * internal registers to 0xf1000000 (instead of the default +- * 0xd0000000). The 0xf1000000 is the default used by the recent, +- * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier +- * boards were delivered with an older version of the bootloader that +- * left internal registers mapped at 0xd0000000. If you are in this +- * situation, you should either update your bootloader (preferred +- * solution) or the below Device Tree should be adjusted. +- */ +- +-/dts-v1/; +-#include +-#include "armada-xp-mv78460.dtsi" +- +-/ { +- model = "Marvell Armada XP Development Board DB-MV784MP-GP"; +- compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- /* +- * 8 GB of plug-in RAM modules by default.The amount +- * of memory available can be changed by the +- * bootloader according the size of the module +- * actually plugged. However, memory between +- * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is +- * the address range used for I/O (internal registers, +- * MBus windows). +- */ +- reg = <0x00000000 0x00000000 0x00000000 0xf0000000>, +- <0x00000001 0x00000000 0x00000001 0x00000000>; +- }; +- +- cpus { +- pm_pic { +- ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>, +- <&gpio0 17 GPIO_ACTIVE_LOW>, +- <&gpio0 18 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- soc { +- ranges = ; +- +- devbus-bootcs { +- status = "okay"; +- +- /* Device Bus parameters are required */ +- +- /* Read parameters */ +- devbus,bus-width = <16>; +- devbus,turn-off-ps = <60000>; +- devbus,badr-skew-ps = <0>; +- devbus,acc-first-ps = <124000>; +- devbus,acc-next-ps = <248000>; +- devbus,rd-setup-ps = <0>; +- devbus,rd-hold-ps = <0>; +- +- /* Write parameters */ +- devbus,sync-enable = <0>; +- devbus,wr-high-ps = <60000>; +- devbus,wr-low-ps = <60000>; +- devbus,ale-wr-ps = <60000>; +- +- /* NOR 16 MiB */ +- nor@0 { +- compatible = "cfi-flash"; +- reg = <0 0x1000000>; +- bank-width = <2>; +- }; +- }; +- +- internal-regs { +- serial@12000 { +- status = "okay"; +- }; +- serial@12100 { +- status = "okay"; +- }; +- serial@12200 { +- status = "okay"; +- }; +- serial@12300 { +- status = "okay"; +- }; +- pinctrl { +- pinctrl-0 = <&pic_pins>; +- pinctrl-names = "default"; +- pic_pins: pic-pins-0 { +- marvell,pins = "mpp16", "mpp17", +- "mpp18"; +- marvell,function = "gpio"; +- }; +- }; +- sata@a0000 { +- nr-ports = <2>; +- status = "okay"; +- }; +- +- ethernet@70000 { +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "qsgmii"; +- buffer-manager = <&bm>; +- bm,pool-long = <0>; +- }; +- ethernet@74000 { +- status = "okay"; +- phy = <&phy1>; +- phy-mode = "qsgmii"; +- buffer-manager = <&bm>; +- bm,pool-long = <1>; +- }; +- ethernet@30000 { +- status = "okay"; +- phy = <&phy2>; +- phy-mode = "qsgmii"; +- buffer-manager = <&bm>; +- bm,pool-long = <2>; +- }; +- ethernet@34000 { +- status = "okay"; +- phy = <&phy3>; +- phy-mode = "qsgmii"; +- buffer-manager = <&bm>; +- bm,pool-long = <3>; +- }; +- +- /* Front-side USB slot */ +- usb@50000 { +- status = "okay"; +- }; +- +- /* Back-side USB slot */ +- usb@51000 { +- status = "okay"; +- }; +- +- bm@c0000 { +- status = "okay"; +- }; +- +- nand-controller@d0000 { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- nand-on-flash-bbt; +- }; +- }; +- }; +- +- bm-bppi { +- status = "okay"; +- }; +- }; +-}; +- +-&pciec { +- status = "okay"; +- +- /* +- * The 3 slots are physically present as +- * standard PCIe slots on the board. +- */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- pcie@9,0 { +- /* Port 2, Lane 0 */ +- status = "okay"; +- }; +- pcie@a,0 { +- /* Port 3, Lane 0 */ +- status = "okay"; +- }; +-}; +- +-&mdio { +- phy0: ethernet-phy@0 { +- reg = <16>; +- }; +- +- phy1: ethernet-phy@1 { +- reg = <17>; +- }; +- +- phy2: ethernet-phy@2 { +- reg = <18>; +- }; +- +- phy3: ethernet-phy@3 { +- reg = <19>; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "n25q128a13", "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <108000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-lenovo-ix4-300d.dts b/scripts/dtc/include-prefixes/arm/armada-xp-lenovo-ix4-300d.dts +deleted file mode 100644 +index 87dcb502f72d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-lenovo-ix4-300d.dts ++++ /dev/null +@@ -1,293 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Lenovo Iomega ix4-300d +- * +- * Copyright (C) 2014, Benoit Masson +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "armada-xp-mv78230.dtsi" +- +-/ { +- model = "Lenovo Iomega ix4-300d"; +- compatible = "lenovo,ix4-300d", "marvell,armadaxp-mv78230", +- "marvell,armadaxp", "marvell,armada-370-xp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0x00000000 0 0x20000000>; /* 512MB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- serial@12000 { +- status = "okay"; +- }; +- +- ethernet@70000 { +- pinctrl-0 = <&ge0_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +- }; +- +- ethernet@74000 { +- pinctrl-0 = <&ge1_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy = <&phy1>; +- phy-mode = "rgmii-id"; +- }; +- +- usb@50000 { +- status = "okay"; +- }; +- +- usb@51000 { +- status = "okay"; +- }; +- +- i2c@11000 { +- clock-frequency = <400000>; +- status = "okay"; +- +- adt7473@2e { +- compatible = "adi,adt7473"; +- reg = <0x2e>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- +- pcf8563@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- +- }; +- +- nand-controller@d0000 { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- nand-on-flash-bbt; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x00000000 0x000e0000>; +- read-only; +- }; +- +- partition@e0000 { +- label = "u-boot-env"; +- reg = <0x000e0000 0x00020000>; +- read-only; +- }; +- +- partition@100000 { +- label = "u-boot-env2"; +- reg = <0x00100000 0x00020000>; +- read-only; +- }; +- +- partition@120000 { +- label = "zImage"; +- reg = <0x00120000 0x00400000>; +- }; +- +- partition@520000 { +- label = "initrd"; +- reg = <0x00520000 0x00400000>; +- }; +- +- partition@e00000 { +- label = "boot"; +- reg = <0x00e00000 0x3f200000>; +- }; +- }; +- }; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&power_button_pin &reset_button_pin +- &select_button_pin &scroll_button_pin>; +- pinctrl-names = "default"; +- +- power-button { +- label = "Power Button"; +- linux,code = ; +- gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; +- }; +- +- reset-button { +- label = "Reset Button"; +- linux,code = ; +- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; +- }; +- +- select-button { +- label = "Select Button"; +- linux,code = ; +- gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- }; +- +- scroll-button { +- label = "Scroll Button"; +- linux,code = ; +- gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- spi3 { +- compatible = "spi-gpio"; +- status = "okay"; +- gpio-sck = <&gpio0 25 GPIO_ACTIVE_LOW>; +- gpio-mosi = <&gpio1 15 GPIO_ACTIVE_LOW>; /*gpio 47*/ +- cs-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; +- num-chipselects = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio_spi: gpio_spi@0 { +- compatible = "fairchild,74hc595"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0>; +- registers-number = <1>; +- spi-max-frequency = <100000>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&hdd_led_pin>; +- pinctrl-names = "default"; +- +- hdd-led { +- label = "ix4-300d:hdd:blue"; +- gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- power-led { +- label = "ix4-300d:power:white"; +- gpios = <&gpio_spi 1 GPIO_ACTIVE_LOW>; +- /* init blinking while booting */ +- linux,default-trigger = "timer"; +- default-state = "on"; +- }; +- +- sysfail-led { +- label = "ix4-300d:sysfail:red"; +- gpios = <&gpio_spi 2 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- sys-led { +- label = "ix4-300d:sys:blue"; +- gpios = <&gpio_spi 3 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- hddfail-led { +- label = "ix4-300d:hddfail:red"; +- gpios = <&gpio_spi 4 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- }; +- +- /* +- * Warning: you need both eth1 & 0 PHY initialized (i.e having +- * them up does the tweak) for poweroff to shutdown otherwise it +- * reboots +- */ +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- pinctrl-0 = <&poweroff_pin>; +- pinctrl-names = "default"; +- gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; +- }; +-}; +-&pciec { +- status = "okay"; +- +- /* Quad port sata: Marvell 88SX7042 */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- +- /* USB 3.0 xHCI controller: NEC D720200F1 */ +- pcie@5,0 { +- /* Port 1, Lane 0 */ +- status = "okay"; +- }; +-}; +- +-&mdio { +- phy0: ethernet-phy@0 { /* Marvell 88E1318 */ +- reg = <0>; +- }; +- +- phy1: ethernet-phy@1 { /* Marvell 88E1318 */ +- reg = <1>; +- }; +-}; +- +-&pinctrl { +- poweroff_pin: poweroff-pin { +- marvell,pins = "mpp24"; +- marvell,function = "gpio"; +- }; +- +- power_button_pin: power-button-pin { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- +- reset_button_pin: reset-button-pin { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- select_button_pin: select-button-pin { +- marvell,pins = "mpp41"; +- marvell,function = "gpio"; +- }; +- +- scroll_button_pin: scroll-button-pin { +- marvell,pins = "mpp42"; +- marvell,function = "gpio"; +- }; +- +- hdd_led_pin: hdd-led-pin { +- marvell,pins = "mpp26"; +- marvell,function = "gpio"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-linksys-mamba.dts b/scripts/dtc/include-prefixes/arm/armada-xp-linksys-mamba.dts +deleted file mode 100644 +index 8480a16919a0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-linksys-mamba.dts ++++ /dev/null +@@ -1,399 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for the Linksys WRT1900AC (Mamba). +- * +- * Note: this board is shipped with a new generation boot loader that +- * remaps internal registers at 0xf1000000. Therefore, if earlyprintk +- * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option should be +- * used. +- * +- * Copyright (C) 2014 Imre Kaloz +- * +- * Based on armada-xp-axpwifiap.dts: +- * +- * Copyright (C) 2013 Marvell +- * +- * Thomas Petazzoni +- */ +- +-/dts-v1/; +-#include +-#include +-#include "armada-xp-mv78230.dtsi" +- +-/ { +- model = "Linksys WRT1900AC"; +- compatible = "linksys,mamba", "marvell,armadaxp-mv78230", +- "marvell,armadaxp", "marvell,armada-370-xp"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- +- rtc@10300 { +- /* No crystal connected to the internal RTC */ +- status = "disabled"; +- }; +- +- /* J10: VCC, NC, RX, NC, TX, GND */ +- serial@12000 { +- status = "okay"; +- }; +- +- sata@a0000 { +- nr-ports = <1>; +- status = "okay"; +- }; +- +- ethernet@70000 { +- pinctrl-0 = <&ge0_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy-mode = "rgmii-id"; +- buffer-manager = <&bm>; +- bm,pool-long = <0>; +- bm,pool-short = <1>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- ethernet@74000 { +- pinctrl-0 = <&ge1_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy-mode = "rgmii-id"; +- buffer-manager = <&bm>; +- bm,pool-long = <2>; +- bm,pool-short = <3>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- /* USB part of the eSATA/USB 2.0 port */ +- usb@50000 { +- status = "okay"; +- }; +- +- i2c@11000 { +- status = "okay"; +- clock-frequency = <100000>; +- +- tmp421@4c { +- compatible = "ti,tmp421"; +- reg = <0x4c>; +- }; +- +- tlc59116@68 { +- #address-cells = <1>; +- #size-cells = <0>; +- #gpio-cells = <2>; +- compatible = "ti,tlc59116"; +- reg = <0x68>; +- +- wan_amber@0 { +- label = "mamba:amber:wan"; +- reg = <0x0>; +- }; +- +- wan_white@1 { +- label = "mamba:white:wan"; +- reg = <0x1>; +- }; +- +- wlan_2g@2 { +- label = "mamba:white:wlan_2g"; +- reg = <0x2>; +- }; +- +- wlan_5g@3 { +- label = "mamba:white:wlan_5g"; +- reg = <0x3>; +- }; +- +- esata@4 { +- label = "mamba:white:esata"; +- reg = <0x4>; +- linux,default-trigger = "disk-activity"; +- }; +- +- usb2@5 { +- label = "mamba:white:usb2"; +- reg = <0x5>; +- }; +- +- usb3_1@6 { +- label = "mamba:white:usb3_1"; +- reg = <0x6>; +- }; +- +- usb3_2@7 { +- label = "mamba:white:usb3_2"; +- reg = <0x7>; +- }; +- +- wps_white@8 { +- label = "mamba:white:wps"; +- reg = <0x8>; +- }; +- +- wps_amber@9 { +- label = "mamba:amber:wps"; +- reg = <0x9>; +- }; +- }; +- }; +- +- bm@c8000 { +- status = "okay"; +- }; +- }; +- +- bm-bppi { +- status = "okay"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&keys_pin>; +- pinctrl-names = "default"; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; +- }; +- +- reset { +- label = "Factory Reset Button"; +- linux,code = ; +- gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&power_led_pin>; +- pinctrl-names = "default"; +- +- power { +- label = "mamba:white:power"; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- pwm_fan { +- /* SUNON HA4010V4-0000-C99 */ +- +- compatible = "pwm-fan"; +- pwms = <&gpio0 24 4000>; +- }; +-}; +- +-&pciec { +- status = "okay"; +- +- /* Etron EJ168 USB 3.0 controller */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- +- /* First mini-PCIe port */ +- pcie@2,0 { +- /* Port 0, Lane 1 */ +- status = "okay"; +- }; +- +- /* Second mini-PCIe port */ +- pcie@3,0 { +- /* Port 0, Lane 3 */ +- status = "okay"; +- }; +-}; +- +-&pinctrl { +- +- keys_pin: keys-pin { +- marvell,pins = "mpp32", "mpp33"; +- marvell,function = "gpio"; +- }; +- +- power_led_pin: power-led-pin { +- marvell,pins = "mpp40"; +- marvell,function = "gpio"; +- }; +- +- gpio_fan_pin: gpio-fan-pin { +- marvell,pins = "mpp24"; +- marvell,function = "gpio"; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "everspin,mr25h256"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <40000000>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- switch@0 { +- compatible = "marvell,mv88e6085"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan4"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan3"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan1"; +- }; +- +- port@4 { +- reg = <4>; +- label = "internet"; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <ð0>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- marvell,nand-keep-config; +- nand-on-flash-bbt; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x100000>; /* 1MB */ +- read-only; +- }; +- +- partition@100000 { +- label = "u_env"; +- reg = <0x100000 0x40000>; /* 256KB */ +- }; +- +- partition@140000 { +- label = "s_env"; +- reg = <0x140000 0x40000>; /* 256KB */ +- }; +- +- partition@900000 { +- label = "devinfo"; +- reg = <0x900000 0x100000>; /* 1MB */ +- read-only; +- }; +- +- /* kernel1 overlaps with rootfs1 by design */ +- partition@a00000 { +- label = "kernel1"; +- reg = <0xa00000 0x2800000>; /* 40MB */ +- }; +- +- partition@d00000 { +- label = "rootfs1"; +- reg = <0xd00000 0x2500000>; /* 37MB */ +- }; +- +- /* kernel2 overlaps with rootfs2 by design */ +- partition@3200000 { +- label = "kernel2"; +- reg = <0x3200000 0x2800000>; /* 40MB */ +- }; +- +- partition@3500000 { +- label = "rootfs2"; +- reg = <0x3500000 0x2500000>; /* 37MB */ +- }; +- +- /* +- * 38MB, last MB is for the BBT, not writable +- */ +- partition@5a00000 { +- label = "syscfg"; +- reg = <0x5a00000 0x2600000>; +- }; +- +- /* +- * Unused area between "s_env" and "devinfo". +- * Moved here because otherwise the renumbered +- * partitions would break the bootloader +- * supplied bootargs +- */ +- partition@180000 { +- label = "unused_area"; +- reg = <0x180000 0x780000>; /* 7.5MB */ +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-matrix.dts b/scripts/dtc/include-prefixes/arm/armada-xp-matrix.dts +deleted file mode 100644 +index 1395cea12759..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-matrix.dts ++++ /dev/null +@@ -1,79 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Marvell Armada XP Matrix board +- * +- * Copyright (C) 2013 Marvell +- * +- * Lior Amsalem +- */ +- +-/dts-v1/; +-#include "armada-xp-mv78460.dtsi" +- +-/ { +- model = "Marvell Armada XP Matrix Board"; +- compatible = "marvell,axp-matrix", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- /* +- * This board has 4 GB of RAM, but the last 256 MB of +- * RAM are not usable due to the overlap with the MBus +- * Window address range +- */ +- reg = <0 0x00000000 0 0xf0000000>; +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- serial@12000 { +- status = "okay"; +- }; +- serial@12100 { +- status = "okay"; +- }; +- serial@12200 { +- status = "okay"; +- }; +- serial@12300 { +- status = "okay"; +- }; +- +- sata@a0000 { +- nr-ports = <2>; +- status = "okay"; +- }; +- +- ethernet@30000 { +- status = "okay"; +- phy-mode = "sgmii"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- usb@50000 { +- status = "okay"; +- }; +- }; +- }; +-}; +- +-&pciec { +- status = "okay"; +- +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-mv78230.dtsi b/scripts/dtc/include-prefixes/arm/armada-xp-mv78230.dtsi +deleted file mode 100644 +index 8558bf6bb54c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-mv78230.dtsi ++++ /dev/null +@@ -1,207 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell Armada XP family SoC +- * +- * Copyright (C) 2012 Marvell +- * +- * Thomas Petazzoni +- * +- * Contains definitions specific to the Armada XP MV78230 SoC that are not +- * common to all Armada XP SoCs. +- */ +- +-#include "armada-xp.dtsi" +- +-/ { +- model = "Marvell Armada XP MV78230 SoC"; +- compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; +- +- aliases { +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "marvell,armada-xp-smp"; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "marvell,sheeva-v7"; +- reg = <0>; +- clocks = <&cpuclk 0>; +- clock-latency = <1000000>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "marvell,sheeva-v7"; +- reg = <1>; +- clocks = <&cpuclk 1>; +- clock-latency = <1000000>; +- }; +- }; +- +- soc { +- /* +- * MV78230 has 2 PCIe units Gen2.0: One unit can be +- * configured as x4 or quad x1 lanes. One unit is +- * x1 only. +- */ +- pciec: pcie@82000000 { +- compatible = "marvell,armada-xp-pcie"; +- status = "disabled"; +- device_type = "pci"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- msi-parent = <&mpic>; +- bus-range = <0x00 0xff>; +- +- ranges = +- <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ +- 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ +- 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ +- 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ +- 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ +- 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ +- 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ +- 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ +- 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ +- 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ +- 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ +- 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ +- 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ +- 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ +- 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; +- +- pcie1: pcie@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 +- 0x81000000 0 0 0x81000000 0x1 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 58>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 5>; +- status = "disabled"; +- }; +- +- pcie2: pcie@2,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; +- reg = <0x1000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 +- 0x81000000 0 0 0x81000000 0x2 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 59>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <1>; +- clocks = <&gateclk 6>; +- status = "disabled"; +- }; +- +- pcie3: pcie@3,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; +- reg = <0x1800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 +- 0x81000000 0 0 0x81000000 0x3 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 60>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <2>; +- clocks = <&gateclk 7>; +- status = "disabled"; +- }; +- +- pcie4: pcie@4,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; +- reg = <0x2000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 +- 0x81000000 0 0 0x81000000 0x4 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 61>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <3>; +- clocks = <&gateclk 8>; +- status = "disabled"; +- }; +- +- pcie5: pcie@5,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; +- reg = <0x2800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 +- 0x81000000 0 0 0x81000000 0x5 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 62>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 9>; +- status = "disabled"; +- }; +- }; +- +- internal-regs { +- gpio0: gpio@18100 { +- compatible = "marvell,armada-370-gpio", +- "marvell,orion-gpio"; +- reg = <0x18100 0x40>, <0x181c0 0x08>; +- reg-names = "gpio", "pwm"; +- ngpios = <32>; +- gpio-controller; +- #gpio-cells = <2>; +- #pwm-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <82>, <83>, <84>, <85>; +- clocks = <&coreclk 0>; +- }; +- +- gpio1: gpio@18140 { +- compatible = "marvell,armada-370-gpio", +- "marvell,orion-gpio"; +- reg = <0x18140 0x40>, <0x181c8 0x08>; +- reg-names = "gpio", "pwm"; +- ngpios = <17>; +- gpio-controller; +- #gpio-cells = <2>; +- #pwm-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <87>, <88>, <89>; +- clocks = <&coreclk 0>; +- }; +- }; +- }; +-}; +- +-&pinctrl { +- compatible = "marvell,mv78230-pinctrl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-mv78260.dtsi b/scripts/dtc/include-prefixes/arm/armada-xp-mv78260.dtsi +deleted file mode 100644 +index 2d85fe8ac327..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-mv78260.dtsi ++++ /dev/null +@@ -1,314 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell Armada XP family SoC +- * +- * Copyright (C) 2012 Marvell +- * +- * Thomas Petazzoni +- * +- * Contains definitions specific to the Armada XP MV78260 SoC that are not +- * common to all Armada XP SoCs. +- */ +- +-#include "armada-xp.dtsi" +- +-/ { +- model = "Marvell Armada XP MV78260 SoC"; +- compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; +- +- aliases { +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- gpio2 = &gpio2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "marvell,armada-xp-smp"; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "marvell,sheeva-v7"; +- reg = <0>; +- clocks = <&cpuclk 0>; +- clock-latency = <1000000>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "marvell,sheeva-v7"; +- reg = <1>; +- clocks = <&cpuclk 1>; +- clock-latency = <1000000>; +- }; +- }; +- +- soc { +- /* +- * MV78260 has 3 PCIe units Gen2.0: Two units can be +- * configured as x4 or quad x1 lanes. One unit is +- * x4 only. +- */ +- pciec: pcie@82000000 { +- compatible = "marvell,armada-xp-pcie"; +- status = "disabled"; +- device_type = "pci"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- msi-parent = <&mpic>; +- bus-range = <0x00 0xff>; +- +- ranges = +- <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ +- 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ +- 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ +- 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ +- 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ +- 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ +- 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ +- 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ +- 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ +- 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ +- 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ +- 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ +- 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ +- 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ +- 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ +- 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ +- 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ +- +- 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ +- 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ +- 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ +- 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ +- 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ +- 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ +- 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ +- 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ +- +- 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ +- 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; +- +- pcie1: pcie@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 +- 0x81000000 0 0 0x81000000 0x1 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 58>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 5>; +- status = "disabled"; +- }; +- +- pcie2: pcie@2,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; +- reg = <0x1000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 +- 0x81000000 0 0 0x81000000 0x2 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 59>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <1>; +- clocks = <&gateclk 6>; +- status = "disabled"; +- }; +- +- pcie3: pcie@3,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; +- reg = <0x1800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 +- 0x81000000 0 0 0x81000000 0x3 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 60>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <2>; +- clocks = <&gateclk 7>; +- status = "disabled"; +- }; +- +- pcie4: pcie@4,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; +- reg = <0x2000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 +- 0x81000000 0 0 0x81000000 0x4 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 61>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <3>; +- clocks = <&gateclk 8>; +- status = "disabled"; +- }; +- +- pcie5: pcie@5,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; +- reg = <0x2800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 +- 0x81000000 0 0 0x81000000 0x5 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 62>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 9>; +- status = "disabled"; +- }; +- +- pcie6: pcie@6,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x84000 0 0x2000>; +- reg = <0x3000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 +- 0x81000000 0 0 0x81000000 0x6 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 63>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <1>; +- clocks = <&gateclk 10>; +- status = "disabled"; +- }; +- +- pcie7: pcie@7,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x88000 0 0x2000>; +- reg = <0x3800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 +- 0x81000000 0 0 0x81000000 0x7 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 64>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <2>; +- clocks = <&gateclk 11>; +- status = "disabled"; +- }; +- +- pcie8: pcie@8,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>; +- reg = <0x4000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 +- 0x81000000 0 0 0x81000000 0x8 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 65>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <3>; +- clocks = <&gateclk 12>; +- status = "disabled"; +- }; +- +- pcie9: pcie@9,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; +- reg = <0x4800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 +- 0x81000000 0 0 0x81000000 0x9 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 99>; +- marvell,pcie-port = <2>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 26>; +- status = "disabled"; +- }; +- }; +- +- internal-regs { +- gpio0: gpio@18100 { +- compatible = "marvell,armada-370-gpio", +- "marvell,orion-gpio"; +- reg = <0x18100 0x40>, <0x181c0 0x08>; +- reg-names = "gpio", "pwm"; +- ngpios = <32>; +- gpio-controller; +- #gpio-cells = <2>; +- #pwm-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <82>, <83>, <84>, <85>; +- clocks = <&coreclk 0>; +- }; +- +- gpio1: gpio@18140 { +- compatible = "marvell,armada-370-gpio", +- "marvell,orion-gpio"; +- reg = <0x18140 0x40>, <0x181c8 0x08>; +- reg-names = "gpio", "pwm"; +- ngpios = <32>; +- gpio-controller; +- #gpio-cells = <2>; +- #pwm-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <87>, <88>, <89>, <90>; +- clocks = <&coreclk 0>; +- }; +- +- gpio2: gpio@18180 { +- compatible = "marvell,armada-370-gpio", +- "marvell,orion-gpio"; +- reg = <0x18180 0x40>; +- ngpios = <3>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <91>; +- }; +- +- eth3: ethernet@34000 { +- compatible = "marvell,armada-xp-neta"; +- reg = <0x34000 0x4000>; +- interrupts = <14>; +- clocks = <&gateclk 1>; +- status = "disabled"; +- }; +- }; +- }; +-}; +- +-&pinctrl { +- compatible = "marvell,mv78260-pinctrl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-mv78460.dtsi b/scripts/dtc/include-prefixes/arm/armada-xp-mv78460.dtsi +deleted file mode 100644 +index 230a3fd36b30..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-mv78460.dtsi ++++ /dev/null +@@ -1,353 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell Armada XP family SoC +- * +- * Copyright (C) 2012 Marvell +- * +- * Thomas Petazzoni +- * +- * Contains definitions specific to the Armada XP MV78460 SoC that are not +- * common to all Armada XP SoCs. +- */ +- +-#include "armada-xp.dtsi" +- +-/ { +- model = "Marvell Armada XP MV78460 SoC"; +- compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; +- +- aliases { +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- gpio2 = &gpio2; +- }; +- +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "marvell,armada-xp-smp"; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "marvell,sheeva-v7"; +- reg = <0>; +- clocks = <&cpuclk 0>; +- clock-latency = <1000000>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "marvell,sheeva-v7"; +- reg = <1>; +- clocks = <&cpuclk 1>; +- clock-latency = <1000000>; +- }; +- +- cpu@2 { +- device_type = "cpu"; +- compatible = "marvell,sheeva-v7"; +- reg = <2>; +- clocks = <&cpuclk 2>; +- clock-latency = <1000000>; +- }; +- +- cpu@3 { +- device_type = "cpu"; +- compatible = "marvell,sheeva-v7"; +- reg = <3>; +- clocks = <&cpuclk 3>; +- clock-latency = <1000000>; +- }; +- }; +- +- soc { +- /* +- * MV78460 has 4 PCIe units Gen2.0: Two units can be +- * configured as x4 or quad x1 lanes. Two units are +- * x4/x1. +- */ +- pciec: pcie@82000000 { +- compatible = "marvell,armada-xp-pcie"; +- status = "disabled"; +- device_type = "pci"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- msi-parent = <&mpic>; +- bus-range = <0x00 0xff>; +- +- ranges = +- <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ +- 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ +- 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ +- 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ +- 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ +- 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ +- 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ +- 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ +- 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ +- 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ +- 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ +- 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ +- 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ +- 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ +- 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ +- 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ +- 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ +- 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ +- +- 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ +- 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ +- 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ +- 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ +- 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ +- 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ +- 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ +- 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ +- +- 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ +- 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ +- +- 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ +- 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; +- +- pcie1: pcie@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 +- 0x81000000 0 0 0x81000000 0x1 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 58>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 5>; +- status = "disabled"; +- }; +- +- pcie2: pcie@2,0 { +- device_type = "pci"; +- assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; +- reg = <0x1000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 +- 0x81000000 0 0 0x81000000 0x2 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 59>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <1>; +- clocks = <&gateclk 6>; +- status = "disabled"; +- }; +- +- pcie3: pcie@3,0 { +- device_type = "pci"; +- assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; +- reg = <0x1800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 +- 0x81000000 0 0 0x81000000 0x3 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 60>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <2>; +- clocks = <&gateclk 7>; +- status = "disabled"; +- }; +- +- pcie4: pcie@4,0 { +- device_type = "pci"; +- assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; +- reg = <0x2000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 +- 0x81000000 0 0 0x81000000 0x4 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 61>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <3>; +- clocks = <&gateclk 8>; +- status = "disabled"; +- }; +- +- pcie5: pcie@5,0 { +- device_type = "pci"; +- assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; +- reg = <0x2800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 +- 0x81000000 0 0 0x81000000 0x5 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 62>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 9>; +- status = "disabled"; +- }; +- +- pcie6: pcie@6,0 { +- device_type = "pci"; +- assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; +- reg = <0x3000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 +- 0x81000000 0 0 0x81000000 0x6 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 63>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <1>; +- clocks = <&gateclk 10>; +- status = "disabled"; +- }; +- +- pcie7: pcie@7,0 { +- device_type = "pci"; +- assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; +- reg = <0x3800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 +- 0x81000000 0 0 0x81000000 0x7 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 64>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <2>; +- clocks = <&gateclk 11>; +- status = "disabled"; +- }; +- +- pcie8: pcie@8,0 { +- device_type = "pci"; +- assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; +- reg = <0x4000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 +- 0x81000000 0 0 0x81000000 0x8 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 65>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <3>; +- clocks = <&gateclk 12>; +- status = "disabled"; +- }; +- +- pcie9: pcie@9,0 { +- device_type = "pci"; +- assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; +- reg = <0x4800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 +- 0x81000000 0 0 0x81000000 0x9 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 99>; +- marvell,pcie-port = <2>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 26>; +- status = "disabled"; +- }; +- +- pcie10: pcie@a,0 { +- device_type = "pci"; +- assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; +- reg = <0x5000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 +- 0x81000000 0 0 0x81000000 0xa 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 103>; +- marvell,pcie-port = <3>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 27>; +- status = "disabled"; +- }; +- }; +- +- internal-regs { +- gpio0: gpio@18100 { +- compatible = "marvell,armada-370-gpio", +- "marvell,orion-gpio"; +- reg = <0x18100 0x40>, <0x181c0 0x08>; +- reg-names = "gpio", "pwm"; +- ngpios = <32>; +- gpio-controller; +- #gpio-cells = <2>; +- #pwm-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <82>, <83>, <84>, <85>; +- clocks = <&coreclk 0>; +- }; +- +- gpio1: gpio@18140 { +- compatible = "marvell,armada-370-gpio", +- "marvell,orion-gpio"; +- reg = <0x18140 0x40>, <0x181c8 0x08>; +- reg-names = "gpio", "pwm"; +- ngpios = <32>; +- gpio-controller; +- #gpio-cells = <2>; +- #pwm-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <87>, <88>, <89>, <90>; +- clocks = <&coreclk 0>; +- }; +- +- gpio2: gpio@18180 { +- compatible = "marvell,armada-370-gpio", +- "marvell,orion-gpio"; +- reg = <0x18180 0x40>; +- ngpios = <3>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <91>; +- }; +- +- eth3: ethernet@34000 { +- compatible = "marvell,armada-xp-neta"; +- reg = <0x34000 0x4000>; +- interrupts = <14>; +- clocks = <&gateclk 1>; +- status = "disabled"; +- }; +- }; +- }; +-}; +- +-&pinctrl { +- compatible = "marvell,mv78460-pinctrl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-netgear-rn2120.dts b/scripts/dtc/include-prefixes/arm/armada-xp-netgear-rn2120.dts +deleted file mode 100644 +index 8ea73587db81..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-netgear-rn2120.dts ++++ /dev/null +@@ -1,357 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for NETGEAR ReadyNAS 2120 +- * +- * Copyright (C) 2013, Arnaud EBALARD +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "armada-xp-mv78230.dtsi" +- +-/ { +- model = "NETGEAR ReadyNAS 2120"; +- compatible = "netgear,readynas-2120", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0x00000000 0 0x80000000>; /* 2GB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- +- /* RTC is provided by Intersil ISL12057 I2C RTC chip */ +- rtc@10300 { +- status = "disabled"; +- }; +- +- i2c@11000 { +- clock-frequency = <400000>; +- status = "okay"; +- +- /* Controller for rear fan #1 of 3 (Protechnic +- * MGT4012XB-O20, 8000RPM) near eSATA port */ +- g762_fan1: g762@3e { +- compatible = "gmt,g762"; +- reg = <0x3e>; +- clocks = <&g762_clk>; /* input clock */ +- fan_gear_mode = <0>; +- fan_startv = <1>; +- pwm_polarity = <0>; +- }; +- +- /* Controller for rear (center) fan #2 of 3 */ +- g762_fan2: g762@48 { +- compatible = "gmt,g762"; +- reg = <0x48>; +- clocks = <&g762_clk>; /* input clock */ +- fan_gear_mode = <0>; +- fan_startv = <1>; +- pwm_polarity = <0>; +- }; +- +- /* Controller for rear fan #3 of 3 */ +- g762_fan3: g762@49 { +- compatible = "gmt,g762"; +- reg = <0x49>; +- clocks = <&g762_clk>; /* input clock */ +- fan_gear_mode = <0>; +- fan_startv = <1>; +- pwm_polarity = <0>; +- }; +- +- /* Temperature sensor */ +- g751: g751@4c { +- compatible = "gmt,g751"; +- reg = <0x4c>; +- }; +- +- isl12057: rtc@68 { +- compatible = "isil,isl12057"; +- reg = <0x68>; +- wakeup-source; +- }; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- /* Front USB 2.0 port */ +- usb@50000 { +- status = "okay"; +- }; +- +- ethernet@70000 { +- pinctrl-0 = <&ge0_rgmii_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +- }; +- +- ethernet@74000 { +- pinctrl-0 = <&ge1_rgmii_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- phy = <&phy1>; +- phy-mode = "rgmii-id"; +- }; +- +- /* Two rear eSATA ports */ +- sata@a0000 { +- nr-ports = <2>; +- status = "okay"; +- }; +- }; +- }; +- +- clocks { +- g762_clk: g762-oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&sata1_led_pin &sata2_led_pin &err_led_pin +- &sata3_led_pin &sata4_led_pin>; +- pinctrl-names = "default"; +- +- red-sata1-led { +- label = "rn2120:red:sata1"; +- gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- red-sata2-led { +- label = "rn2120:red:sata2"; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- red-sata3-led { +- label = "rn2120:red:sata3"; +- gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- red-sata4-led { +- label = "rn2120:red:sata4"; +- gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- red-err-led { +- label = "rn2120:red:err"; +- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&power_button_pin &reset_button_pin>; +- pinctrl-names = "default"; +- +- power-button { +- label = "Power Button"; +- linux,code = ; +- gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; +- }; +- +- reset-button { +- label = "Reset Button"; +- linux,code = ; +- gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- pinctrl-0 = <&poweroff>; +- pinctrl-names = "default"; +- gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&pciec { +- status = "okay"; +- +- /* Connected to first Marvell 88SE9170 SATA controller */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- +- /* Connected to second Marvell 88SE9170 SATA controller */ +- pcie@2,0 { +- /* Port 0, Lane 1 */ +- status = "okay"; +- }; +- +- /* Connected to Fresco Logic FL1009 USB 3.0 controller */ +- pcie@5,0 { +- /* Port 1, Lane 0 */ +- status = "okay"; +- }; +-}; +- +-&mdio { +- phy0: ethernet-phy@0 { /* Marvell 88E1318 */ +- reg = <0>; +- }; +- +- phy1: ethernet-phy@1 { /* Marvell 88E1318 */ +- reg = <1>; +- }; +-}; +- +- +-&pinctrl { +- poweroff: poweroff { +- marvell,pins = "mpp42"; +- marvell,function = "gpio"; +- }; +- +- power_button_pin: power-button-pin { +- marvell,pins = "mpp27"; +- marvell,function = "gpio"; +- }; +- +- reset_button_pin: reset-button-pin { +- marvell,pins = "mpp41"; +- marvell,function = "gpio"; +- }; +- +- sata1_led_pin: sata1-led-pin { +- marvell,pins = "mpp31"; +- marvell,function = "gpio"; +- }; +- +- sata2_led_pin: sata2-led-pin { +- marvell,pins = "mpp40"; +- marvell,function = "gpio"; +- }; +- +- sata3_led_pin: sata3-led-pin { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- +- sata4_led_pin: sata4-led-pin { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- +- sata1_power_pin: sata1-power-pin { +- marvell,pins = "mpp24"; +- marvell,function = "gpio"; +- }; +- +- sata2_power_pin: sata2-power-pin { +- marvell,pins = "mpp25"; +- marvell,function = "gpio"; +- }; +- +- sata3_power_pin: sata3-power-pin { +- marvell,pins = "mpp26"; +- marvell,function = "gpio"; +- }; +- +- sata4_power_pin: sata4-power-pin { +- marvell,pins = "mpp28"; +- marvell,function = "gpio"; +- }; +- +- sata1_pres_pin: sata1-pres-pin { +- marvell,pins = "mpp32"; +- marvell,function = "gpio"; +- }; +- +- sata2_pres_pin: sata2-pres-pin { +- marvell,pins = "mpp33"; +- marvell,function = "gpio"; +- }; +- +- sata3_pres_pin: sata3-pres-pin { +- marvell,pins = "mpp34"; +- marvell,function = "gpio"; +- }; +- +- sata4_pres_pin: sata4-pres-pin { +- marvell,pins = "mpp35"; +- marvell,function = "gpio"; +- }; +- +- err_led_pin: err-led-pin { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- marvell,nand-keep-config; +- nand-on-flash-bbt; +- +- /* Use Hardware BCH ECC */ +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x180000>; /* 1.5MB */ +- read-only; +- }; +- +- partition@180000 { +- label = "u-boot-env"; +- reg = <0x180000 0x20000>; /* 128KB */ +- read-only; +- }; +- +- partition@200000 { +- label = "uImage"; +- reg = <0x0200000 0x600000>; /* 6MB */ +- }; +- +- partition@800000 { +- label = "minirootfs"; +- reg = <0x0800000 0x400000>; /* 4MB */ +- }; +- +- /* Last MB is for the BBT, i.e. not writable */ +- partition@c00000 { +- label = "ubifs"; +- reg = <0x0c00000 0x7400000>; /* 116MB */ +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-openblocks-ax3-4.dts b/scripts/dtc/include-prefixes/arm/armada-xp-openblocks-ax3-4.dts +deleted file mode 100644 +index 0efcc166dabf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-openblocks-ax3-4.dts ++++ /dev/null +@@ -1,211 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for OpenBlocks AX3-4 board +- * +- * Copyright (C) 2012 Marvell +- * +- * Thomas Petazzoni +- */ +- +-/dts-v1/; +-#include +-#include +-#include "armada-xp-mv78260.dtsi" +- +-/ { +- model = "PlatHome OpenBlocks AX3-4 board"; +- compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0x00000000 0 0x40000000>; /* 1 GB soldered on */ +- }; +- +- soc { +- ranges = ; +- +- devbus-bootcs { +- status = "okay"; +- +- /* Device Bus parameters are required */ +- +- /* Read parameters */ +- devbus,bus-width = <16>; +- devbus,turn-off-ps = <60000>; +- devbus,badr-skew-ps = <0>; +- devbus,acc-first-ps = <124000>; +- devbus,acc-next-ps = <248000>; +- devbus,rd-setup-ps = <0>; +- devbus,rd-hold-ps = <0>; +- +- /* Write parameters */ +- devbus,sync-enable = <0>; +- devbus,wr-high-ps = <60000>; +- devbus,wr-low-ps = <60000>; +- devbus,ale-wr-ps = <60000>; +- +- /* NOR 128 MiB */ +- nor@0 { +- compatible = "cfi-flash"; +- reg = <0 0x8000000>; +- bank-width = <2>; +- }; +- }; +- +- internal-regs { +- rtc@10300 { +- /* No crystal connected to the internal RTC */ +- status = "disabled"; +- }; +- serial@12000 { +- status = "okay"; +- }; +- serial@12100 { +- status = "okay"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins>; +- +- red_led { +- label = "red_led"; +- gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- yellow_led { +- label = "yellow_led"; +- gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- green_led { +- label = "green_led"; +- gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- init { +- label = "Init Button"; +- linux,code = ; +- gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- ethernet@70000 { +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "sgmii"; +- buffer-manager = <&bm>; +- bm,pool-long = <0>; +- }; +- ethernet@74000 { +- status = "okay"; +- phy = <&phy1>; +- phy-mode = "sgmii"; +- buffer-manager = <&bm>; +- bm,pool-long = <1>; +- }; +- ethernet@30000 { +- status = "okay"; +- phy = <&phy2>; +- phy-mode = "sgmii"; +- buffer-manager = <&bm>; +- bm,pool-long = <2>; +- }; +- ethernet@34000 { +- status = "okay"; +- phy = <&phy3>; +- phy-mode = "sgmii"; +- buffer-manager = <&bm>; +- bm,pool-long = <3>; +- }; +- i2c@11000 { +- status = "okay"; +- clock-frequency = <400000>; +- }; +- i2c@11100 { +- status = "okay"; +- clock-frequency = <400000>; +- +- s35390a: s35390a@30 { +- compatible = "s35390a"; +- reg = <0x30>; +- }; +- }; +- sata@a0000 { +- nr-ports = <2>; +- status = "okay"; +- }; +- +- /* Front side USB 0 */ +- usb@50000 { +- status = "okay"; +- }; +- +- /* Front side USB 1 */ +- usb@51000 { +- status = "okay"; +- }; +- +- bm@c0000 { +- status = "okay"; +- }; +- }; +- +- bm-bppi { +- status = "okay"; +- }; +- }; +-}; +- +-&pciec { +- status = "okay"; +- /* Internal mini-PCIe connector */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +-}; +- +-&mdio { +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +- +- phy2: ethernet-phy@2 { +- reg = <2>; +- }; +- +- phy3: ethernet-phy@3 { +- reg = <3>; +- }; +-}; +- +-&pinctrl { +- led_pins: led-pins-0 { +- marvell,pins = "mpp49", "mpp51", "mpp53"; +- marvell,function = "gpio"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp-synology-ds414.dts b/scripts/dtc/include-prefixes/arm/armada-xp-synology-ds414.dts +deleted file mode 100644 +index 809e821d7399..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp-synology-ds414.dts ++++ /dev/null +@@ -1,328 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Synology DS414 +- * +- * Copyright (C) 2014, Arnaud EBALARD +- * +- * Note: this Device Tree assumes that the bootloader has remapped the +- * internal registers to 0xf1000000 (instead of the old 0xd0000000). +- * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot +- * bootloaders provided by Marvell. It is used in recent versions of +- * DSM software provided by Synology. Nonetheless, some earlier boards +- * were delivered with an older version of u-boot that left internal +- * registers mapped at 0xd0000000. If you have such a device you will +- * not be able to directly boot a kernel based on this Device Tree. In +- * that case, the preferred solution is to update your bootloader (e.g. +- * by upgrading to latest version of DSM, or building a new one and +- * installing it from u-boot prompt) or adjust the Devive Tree +- * (s/0xf1000000/0xd0000000/ in 'ranges' below). +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "armada-xp-mv78230.dtsi" +- +-/ { +- model = "Synology DS414"; +- compatible = "synology,ds414", "marvell,armadaxp-mv78230", +- "marvell,armadaxp", "marvell,armada-370-xp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0x00000000 0 0x40000000>; /* 1GB */ +- }; +- +- soc { +- ranges = ; +- +- internal-regs { +- +- /* RTC is provided by Seiko S-35390A below */ +- rtc@10300 { +- status = "disabled"; +- }; +- +- i2c@11000 { +- clock-frequency = <400000>; +- status = "okay"; +- +- s35390a: s35390a@30 { +- compatible = "sii,s35390a"; +- reg = <0x30>; +- }; +- }; +- +- /* Connected to a header on device's PCB. This +- * provides the main console for the device. +- * +- * Warning: the device may not boot with a 3.3V +- * USB-serial converter connected when the power +- * button is pressed. The converter needs to be +- * connected a few seconds after pressing the +- * power button. This is possibly due to UART0_TXD +- * pin being sampled at reset (bit 0 of SAR). +- */ +- serial@12000 { +- status = "okay"; +- }; +- +- /* Connected to a Microchip PIC16F883 for power control */ +- serial@12100 { +- status = "okay"; +- }; +- +- poweroff@12100 { +- compatible = "synology,power-off"; +- reg = <0x12100 0x100>; +- clocks = <&coreclk 0>; +- }; +- +- /* Front USB 2.0 port */ +- usb@50000 { +- status = "okay"; +- }; +- +- ethernet@70000 { +- status = "okay"; +- pinctrl-0 = <&ge0_rgmii_pins>; +- pinctrl-names = "default"; +- phy = <&phy1>; +- phy-mode = "rgmii-id"; +- }; +- +- ethernet@74000 { +- pinctrl-0 = <&ge1_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +- }; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin +- &sata3_pwr_pin &sata4_pwr_pin>; +- pinctrl-names = "default"; +- +- sata1_regulator: sata1-regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "SATA1 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- startup-delay-us = <2000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; +- }; +- +- sata2_regulator: sata2-regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "SATA2 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- startup-delay-us = <4000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; +- }; +- +- sata3_regulator: sata3-regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- regulator-name = "SATA3 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- startup-delay-us = <6000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; +- }; +- +- sata4_regulator: sata4-regulator@4 { +- compatible = "regulator-fixed"; +- reg = <4>; +- regulator-name = "SATA4 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- startup-delay-us = <8000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&pciec { +- status = "okay"; +- +- /* +- * Connected to Marvell 88SX7042 SATA-II controller +- * handling the four disks. +- */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- +- /* +- * Connected to EtronTech EJ168A XHCI controller +- * providing the two rear USB 3.0 ports. +- */ +- pcie@5,0 { +- /* Port 1, Lane 0 */ +- status = "okay"; +- }; +-}; +- +- +-&mdio { +- phy0: ethernet-phy@0 { /* Marvell 88E1512 */ +- reg = <0>; +- }; +- +- phy1: ethernet-phy@1 { /* Marvell 88E1512 */ +- reg = <1>; +- }; +-}; +- +-&pinctrl { +- sata1_pwr_pin: sata1-pwr-pin { +- marvell,pins = "mpp42"; +- marvell,function = "gpio"; +- }; +- +- sata2_pwr_pin: sata2-pwr-pin { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- +- sata3_pwr_pin: sata3-pwr-pin { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- +- sata4_pwr_pin: sata4-pwr-pin { +- marvell,pins = "mpp46"; +- marvell,function = "gpio"; +- }; +- +- sata1_pres_pin: sata1-pres-pin { +- marvell,pins = "mpp34"; +- marvell,function = "gpio"; +- }; +- +- sata2_pres_pin: sata2-pres-pin { +- marvell,pins = "mpp35"; +- marvell,function = "gpio"; +- }; +- +- sata3_pres_pin: sata3-pres-pin { +- marvell,pins = "mpp40"; +- marvell,function = "gpio"; +- }; +- +- sata4_pres_pin: sata4-pres-pin { +- marvell,pins = "mpp41"; +- marvell,function = "gpio"; +- }; +- +- syno_id_bit0_pin: syno-id-bit0-pin { +- marvell,pins = "mpp26"; +- marvell,function = "gpio"; +- }; +- +- syno_id_bit1_pin: syno-id-bit1-pin { +- marvell,pins = "mpp28"; +- marvell,function = "gpio"; +- }; +- +- syno_id_bit2_pin: syno-id-bit2-pin { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- +- fan1_alarm_pin: fan1-alarm-pin { +- marvell,pins = "mpp33"; +- marvell,function = "gpio"; +- }; +- +- fan2_alarm_pin: fan2-alarm-pin { +- marvell,pins = "mpp32"; +- marvell,function = "gpio"; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q064", "jedec,spi-nor"; +- reg = <0>; /* Chip select 0 */ +- spi-max-frequency = <20000000>; +- +- /* +- * Warning! +- * +- * Synology u-boot uses its compiled-in environment +- * and it seems Synology did not care to change u-boot +- * default configuration in order to allow saving a +- * modified environment at a sensible location. So, +- * if you do a 'saveenv' under u-boot, your modified +- * environment will be saved at 1MB after the start +- * of the flash, i.e. in the middle of the uImage. +- * For that reason, it is strongly advised not to +- * change the default environment, unless you know +- * what you are doing. +- */ +- partition@0 { /* u-boot */ +- label = "RedBoot"; +- reg = <0x00000000 0x000d0000>; /* 832KB */ +- }; +- +- partition@c0000 { /* uImage */ +- label = "zImage"; +- reg = <0x000d0000 0x002d0000>; /* 2880KB */ +- }; +- +- partition@3a0000 { /* uInitramfs */ +- label = "rd.gz"; +- reg = <0x003a0000 0x00430000>; /* 4250KB */ +- }; +- +- partition@7d0000 { /* MAC address and serial number */ +- label = "vendor"; +- reg = <0x007d0000 0x00010000>; /* 64KB */ +- }; +- +- partition@7e0000 { +- label = "RedBoot config"; +- reg = <0x007e0000 0x00010000>; /* 64KB */ +- }; +- +- partition@7f0000 { +- label = "FIS directory"; +- reg = <0x007f0000 0x00010000>; /* 64KB */ +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armada-xp.dtsi b/scripts/dtc/include-prefixes/arm/armada-xp.dtsi +deleted file mode 100644 +index 6c19984d668e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armada-xp.dtsi ++++ /dev/null +@@ -1,344 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell Armada XP family SoC +- * +- * Copyright (C) 2012 Marvell +- * +- * Lior Amsalem +- * Gregory CLEMENT +- * Thomas Petazzoni +- * Ben Dooks +- * +- * Contains definitions specific to the Armada XP SoC that are not +- * common to all Armada SoCs. +- */ +- +-#include "armada-370-xp.dtsi" +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- +- model = "Marvell Armada XP family SoC"; +- compatible = "marvell,armadaxp", "marvell,armada-370-xp"; +- +- aliases { +- serial2 = &uart2; +- serial3 = &uart3; +- }; +- +- soc { +- compatible = "marvell,armadaxp-mbus", "simple-bus"; +- +- bootrom { +- compatible = "marvell,bootrom"; +- reg = ; +- }; +- +- internal-regs { +- sdramc: sdramc@1400 { +- compatible = "marvell,armada-xp-sdram-controller"; +- reg = <0x1400 0x500>; +- }; +- +- L2: l2-cache@8000 { +- compatible = "marvell,aurora-system-cache"; +- reg = <0x08000 0x1000>; +- cache-id-part = <0x100>; +- cache-level = <2>; +- cache-unified; +- wt-override; +- }; +- +- uart2: serial@12200 { +- compatible = "snps,dw-apb-uart"; +- pinctrl-0 = <&uart2_pins>; +- pinctrl-names = "default"; +- reg = <0x12200 0x100>; +- reg-shift = <2>; +- interrupts = <43>; +- reg-io-width = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- uart3: serial@12300 { +- compatible = "snps,dw-apb-uart"; +- pinctrl-0 = <&uart3_pins>; +- pinctrl-names = "default"; +- reg = <0x12300 0x100>; +- reg-shift = <2>; +- interrupts = <44>; +- reg-io-width = <1>; +- clocks = <&coreclk 0>; +- status = "disabled"; +- }; +- +- systemc: system-controller@18200 { +- compatible = "marvell,armada-370-xp-system-controller"; +- reg = <0x18200 0x500>; +- }; +- +- gateclk: clock-gating-control@18220 { +- compatible = "marvell,armada-xp-gating-clock"; +- reg = <0x18220 0x4>; +- clocks = <&coreclk 0>; +- #clock-cells = <1>; +- }; +- +- coreclk: mvebu-sar@18230 { +- compatible = "marvell,armada-xp-core-clock"; +- reg = <0x18230 0x08>; +- #clock-cells = <1>; +- }; +- +- thermal: thermal@182b0 { +- compatible = "marvell,armadaxp-thermal"; +- reg = <0x182b0 0x4 +- 0x184d0 0x4>; +- status = "okay"; +- }; +- +- cpuclk: clock-complex@18700 { +- #clock-cells = <1>; +- compatible = "marvell,armada-xp-cpu-clock"; +- reg = <0x18700 0x24>, <0x1c054 0x10>; +- clocks = <&coreclk 1>; +- }; +- +- cpu-config@21000 { +- compatible = "marvell,armada-xp-cpu-config"; +- reg = <0x21000 0x8>; +- }; +- +- eth2: ethernet@30000 { +- compatible = "marvell,armada-xp-neta"; +- reg = <0x30000 0x4000>; +- interrupts = <12>; +- clocks = <&gateclk 2>; +- status = "disabled"; +- }; +- +- usb2: usb@52000 { +- compatible = "marvell,orion-ehci"; +- reg = <0x52000 0x500>; +- interrupts = <47>; +- clocks = <&gateclk 20>; +- status = "disabled"; +- }; +- +- xor1: xor@60900 { +- compatible = "marvell,orion-xor"; +- reg = <0x60900 0x100 +- 0x60b00 0x100>; +- clocks = <&gateclk 22>; +- status = "okay"; +- +- xor10 { +- interrupts = <51>; +- dmacap,memcpy; +- dmacap,xor; +- }; +- xor11 { +- interrupts = <52>; +- dmacap,memcpy; +- dmacap,xor; +- dmacap,memset; +- }; +- }; +- +- ethernet@70000 { +- compatible = "marvell,armada-xp-neta"; +- }; +- +- ethernet@74000 { +- compatible = "marvell,armada-xp-neta"; +- }; +- +- cesa: crypto@90000 { +- compatible = "marvell,armada-xp-crypto"; +- reg = <0x90000 0x10000>; +- reg-names = "regs"; +- interrupts = <48>, <49>; +- clocks = <&gateclk 23>, <&gateclk 23>; +- clock-names = "cesa0", "cesa1"; +- marvell,crypto-srams = <&crypto_sram0>, +- <&crypto_sram1>; +- marvell,crypto-sram-size = <0x800>; +- }; +- +- bm: bm@c0000 { +- compatible = "marvell,armada-380-neta-bm"; +- reg = <0xc0000 0xac>; +- clocks = <&gateclk 13>; +- internal-mem = <&bm_bppi>; +- status = "disabled"; +- }; +- +- xor0: xor@f0900 { +- compatible = "marvell,orion-xor"; +- reg = <0xF0900 0x100 +- 0xF0B00 0x100>; +- clocks = <&gateclk 28>; +- status = "okay"; +- +- xor00 { +- interrupts = <94>; +- dmacap,memcpy; +- dmacap,xor; +- }; +- xor01 { +- interrupts = <95>; +- dmacap,memcpy; +- dmacap,xor; +- dmacap,memset; +- }; +- }; +- }; +- +- crypto_sram0: sa-sram0 { +- compatible = "mmio-sram"; +- reg = ; +- clocks = <&gateclk 23>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>; +- }; +- +- crypto_sram1: sa-sram1 { +- compatible = "mmio-sram"; +- reg = ; +- clocks = <&gateclk 23>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; +- }; +- +- bm_bppi: bm-bppi { +- compatible = "mmio-sram"; +- reg = ; +- ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&gateclk 13>; +- no-memory-wc; +- status = "disabled"; +- }; +- }; +- +- clocks { +- /* 25 MHz reference crystal */ +- refclk: oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- }; +-}; +- +-&i2c0 { +- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; +- reg = <0x11000 0x100>; +-}; +- +-&i2c1 { +- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; +- reg = <0x11100 0x100>; +-}; +- +-&mpic { +- reg = <0x20a00 0x2d0>, <0x21070 0x58>; +-}; +- +-&timer { +- compatible = "marvell,armada-xp-timer"; +- clocks = <&coreclk 2>, <&refclk>; +- clock-names = "nbclk", "fixed"; +-}; +- +-&watchdog { +- compatible = "marvell,armada-xp-wdt"; +- clocks = <&coreclk 2>, <&refclk>; +- clock-names = "nbclk", "fixed"; +-}; +- +-&cpurst { +- reg = <0x20800 0x20>; +-}; +- +-&usb0 { +- clocks = <&gateclk 18>; +-}; +- +-&usb1 { +- clocks = <&gateclk 19>; +-}; +- +-&pinctrl { +- ge0_gmii_pins: ge0-gmii-pins { +- marvell,pins = +- "mpp0", "mpp1", "mpp2", "mpp3", +- "mpp4", "mpp5", "mpp6", "mpp7", +- "mpp8", "mpp9", "mpp10", "mpp11", +- "mpp12", "mpp13", "mpp14", "mpp15", +- "mpp16", "mpp17", "mpp18", "mpp19", +- "mpp20", "mpp21", "mpp22", "mpp23"; +- marvell,function = "ge0"; +- }; +- +- ge0_rgmii_pins: ge0-rgmii-pins { +- marvell,pins = +- "mpp0", "mpp1", "mpp2", "mpp3", +- "mpp4", "mpp5", "mpp6", "mpp7", +- "mpp8", "mpp9", "mpp10", "mpp11"; +- marvell,function = "ge0"; +- }; +- +- ge1_rgmii_pins: ge1-rgmii-pins { +- marvell,pins = +- "mpp12", "mpp13", "mpp14", "mpp15", +- "mpp16", "mpp17", "mpp18", "mpp19", +- "mpp20", "mpp21", "mpp22", "mpp23"; +- marvell,function = "ge1"; +- }; +- +- sdio_pins: sdio-pins { +- marvell,pins = "mpp30", "mpp31", "mpp32", +- "mpp33", "mpp34", "mpp35"; +- marvell,function = "sd0"; +- }; +- +- spi0_pins: spi0-pins { +- marvell,pins = "mpp36", "mpp37", +- "mpp38", "mpp39"; +- marvell,function = "spi0"; +- }; +- +- spi1_pins: spi1-pins { +- marvell,pins = "mpp13", "mpp14", +- "mpp16", "mpp17"; +- marvell,function = "spi1"; +- }; +- +- uart2_pins: uart2-pins { +- marvell,pins = "mpp42", "mpp43"; +- marvell,function = "uart2"; +- }; +- +- uart3_pins: uart3-pins { +- marvell,pins = "mpp44", "mpp45"; +- marvell,function = "uart3"; +- }; +-}; +- +-&spi0 { +- compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; +- pinctrl-0 = <&spi0_pins>; +- pinctrl-names = "default"; +-}; +- +-&spi1 { +- compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; +- pinctrl-0 = <&spi1_pins>; +- pinctrl-names = "default"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/armv7-m.dtsi b/scripts/dtc/include-prefixes/arm/armv7-m.dtsi +deleted file mode 100644 +index 26f5443d85e1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/armv7-m.dtsi ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- nvic: interrupt-controller@e000e100 { +- compatible = "arm,armv7m-nvic"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0xe000e100 0xc00>; +- }; +- +- systick: timer@e000e010 { +- compatible = "arm,armv7m-systick"; +- reg = <0xe000e010 0x10>; +- status = "disabled"; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&nvic>; +- ranges; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/artpec6-devboard.dts b/scripts/dtc/include-prefixes/arm/artpec6-devboard.dts +deleted file mode 100644 +index d20d95359b28..000000000000 +--- a/scripts/dtc/include-prefixes/arm/artpec6-devboard.dts ++++ /dev/null +@@ -1,69 +0,0 @@ +-/* +- * Axis ARTPEC-6 development board. +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-/dts-v1/; +-#include "artpec6.dtsi" +- +-/ { +- model = "ARTPEC-6 development board"; +- compatible = "axis,artpec6-dev-board", "axis,artpec6"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial3:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x40000000>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-ðernet { +- status = "okay"; +- +- phy-handle = <&phy1>; +- phy-mode = "gmii"; +- +- mdio { +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- compatible = "snps,dwmac-mdio"; +- phy1: phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- device_type = "ethernet-phy"; +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/artpec6.dtsi b/scripts/dtc/include-prefixes/arm/artpec6.dtsi +deleted file mode 100644 +index 037157e6c5ee..000000000000 +--- a/scripts/dtc/include-prefixes/arm/artpec6.dtsi ++++ /dev/null +@@ -1,388 +0,0 @@ +-/* +- * Device Tree Source for the Axis ARTPEC-6 SoC +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "axis,artpec6"; +- interrupt-parent = <&intc>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- next-level-cache = <&pl310>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <1>; +- next-level-cache = <&pl310>; +- }; +- }; +- +- syscon: syscon@f8000000 { +- compatible = "axis,artpec6-syscon", "syscon"; +- reg = <0xf8000000 0x48>; +- }; +- +- psci { +- compatible = "arm,psci-0.2", "arm,psci"; +- method = "smc"; +- psci_version = <0x84000000>; +- cpu_on = <0x84000003>; +- system_reset = <0x84000009>; +- }; +- +- scu@faf00000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0xfaf00000 0x58>; +- }; +- +- /* Main external clock driving CPU and peripherals */ +- ext_clk: ext_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- }; +- +- eth_phy_ref_clk: eth_phy_ref_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- }; +- +- clkctrl: clkctrl@f8000000 { +- #clock-cells = <1>; +- compatible = "axis,artpec6-clkctrl"; +- reg = <0xf8000000 0x48>; +- clocks = <&ext_clk>; +- clock-names = "sys_refclk"; +- }; +- +- gtimer@faf00200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0xfaf00200 0x20>; +- interrupts = ; +- clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>; +- }; +- +- timer@faf00600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0xfaf00600 0x20>; +- interrupts = ; +- clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>; +- status = "disabled"; +- }; +- +- intc: interrupt-controller@faf01000 { +- interrupt-controller; +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >; +- }; +- +- pl310: cache-controller@faf10000 { +- compatible = "arm,pl310-cache"; +- cache-unified; +- cache-level = <2>; +- reg = <0xfaf10000 0x1000>; +- interrupts = ; +- arm,data-latency = <1 1 1>; +- arm,tag-latency = <1 1 1>; +- arm,filter-ranges = <0x0 0x80000000>; +- arm,double-linefill = <1>; +- arm,double-linefill-incr = <0>; +- arm,double-linefill-wrap = <0>; +- prefetch-data = <1>; +- prefetch-instr = <1>; +- arm,prefetch-offset = <0>; +- arm,prefetch-drop = <1>; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- /* +- * Both pci nodes cannot be enabled at the same time, +- * leave the unwanted node as disabled. +- */ +- pcie: pcie@f8050000 { +- compatible = "axis,artpec6-pcie", "snps,dw-pcie"; +- reg = <0xf8050000 0x2000 +- 0xf8040000 0x1000 +- 0xc0000000 0x2000>; +- reg-names = "dbi", "phy", "config"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- /* downstream I/O */ +- ranges = <0x81000000 0 0 0xc0002000 0 0x00010000 +- /* non-prefetchable memory */ +- 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>; +- num-lanes = <2>; +- bus-range = <0x00 0xff>; +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; +- axis,syscon-pcie = <&syscon>; +- status = "disabled"; +- }; +- +- pcie_ep: pcie_ep@f8050000 { +- compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie"; +- reg = <0xf8050000 0x2000 +- 0xf8051000 0x2000 +- 0xf8040000 0x1000 +- 0xc0000000 0x20000000>; +- reg-names = "dbi", "dbi2", "phy", "addr_space"; +- num-ib-windows = <6>; +- num-ob-windows = <2>; +- num-lanes = <2>; +- axis,syscon-pcie = <&syscon>; +- status = "disabled"; +- }; +- +- pinctrl: pinctrl@f801d000 { +- compatible = "axis,artpec6-pinctrl"; +- reg = <0xf801d000 0x400>; +- +- pinctrl_uart0: uart0grp { +- function = "uart0"; +- groups = "uart0grp2"; +- bias-pull-up; +- }; +- pinctrl_uart1: uart1grp { +- function = "uart1"; +- groups = "uart1grp0"; +- bias-pull-up; +- }; +- pinctrl_uart2: uart2grp { +- function = "uart2"; +- groups = "uart2grp1"; +- bias-pull-up; +- }; +- pinctrl_uart3: uart3grp { +- function = "uart3"; +- groups = "uart3grp0"; +- bias-pull-up; +- }; +- }; +- +- amba@0 { +- compatible = "simple-bus"; +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- ranges; +- dma-ranges; +- +- crypto@f4264000 { +- compatible = "axis,artpec6-crypto"; +- reg = <0xf4264000 0x4000>; +- interrupts = ; +- }; +- +- dma0: dma@f8019000 { +- compatible = "renesas,nbpfaxi64dmac8b16"; +- reg = <0xf8019000 0x400>; +- interrupts = , /* error */ +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch12", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>; +- #dma-cells = <2>; +- dma-channels = <8>; +- dma-requests = <8>; +- }; +- dma1: dma@f8019400 { +- compatible = "renesas,nbpfaxi64dmac8b16"; +- reg = <0xf8019400 0x400>; +- interrupts = , /* error */ +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch12", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>; +- #dma-cells = <2>; +- dma-channels = <8>; +- dma-requests = <8>; +- }; +- +- ethernet: ethernet@f8010000 { +- clock-names = "stmmaceth", "ptp_ref"; +- clocks = <&clkctrl ARTPEC6_CLK_ETH_ACLK>, +- <&clkctrl ARTPEC6_CLK_PTP_REF>; +- compatible = "snps,dwmac-4.10a", "snps,dwmac"; +- interrupts = , +- ; +- interrupt-names = "macirq", "eth_lpi"; +- reg = <0xf8010000 0x4000>; +- +- snps,axi-config = <&stmmac_axi_setup>; +- snps,mtl-rx-config = <&mtl_rx_setup>; +- snps,mtl-tx-config = <&mtl_tx_setup>; +- +- snps,txpbl = <8>; +- snps,rxpbl = <2>; +- snps,aal; +- snps,tso; +- +- status = "disabled"; +- +- stmmac_axi_setup: stmmac-axi-config { +- snps,wr_osr_lmt = <1>; +- snps,rd_osr_lmt = <15>; +- /* If FB is disabled, the AXI master chooses +- * a burst length of any value less than the +- * maximum enabled burst length +- * (all lesser burst length enables are redundant). +- */ +- snps,blen = <0 0 0 0 16 0 0>; +- }; +- +- mtl_rx_setup: rx-queues-config { +- snps,rx-queues-to-use = <1>; +- queue0 {}; +- }; +- +- mtl_tx_setup: tx-queues-config { +- snps,tx-queues-to-use = <2>; +- queue0 {}; +- queue1 {}; +- }; +- }; +- +- uart0: serial@f8036000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xf8036000 0x1000>; +- interrupts = ; +- clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, +- <&clkctrl ARTPEC6_CLK_UART_PCLK>; +- clock-names = "uart_clk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- dmas = <&dma0 4 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, +- <&dma0 5 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- uart1: serial@f8037000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xf8037000 0x1000>; +- interrupts = ; +- clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, +- <&clkctrl ARTPEC6_CLK_UART_PCLK>; +- clock-names = "uart_clk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- dmas = <&dma0 6 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, +- <&dma0 7 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- uart2: serial@f8038000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xf8038000 0x1000>; +- interrupts = ; +- clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, +- <&clkctrl ARTPEC6_CLK_UART_PCLK>; +- clock-names = "uart_clk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- dmas = <&dma1 0 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, +- <&dma1 1 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- uart3: serial@f8039000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xf8039000 0x1000>; +- interrupts = ; +- clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, +- <&clkctrl ARTPEC6_CLK_UART_PCLK>; +- clock-names = "uart_clk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- dmas = <&dma1 2 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, +- <&dma1 3 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-ast2500-evb.dts b/scripts/dtc/include-prefixes/arm/aspeed-ast2500-evb.dts +deleted file mode 100644 +index 1d24b394ea4c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-ast2500-evb.dts ++++ /dev/null +@@ -1,135 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/dts-v1/; +- +-#include "aspeed-g5.dtsi" +- +-/ { +- model = "AST2500 EVB"; +- compatible = "aspeed,ast2500"; +- +- aliases { +- serial4 = &uart5; +- }; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=tty0 console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gfx_memory: framebuffer { +- size = <0x01000000>; +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- }; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +- spi-max-frequency = <50000000>; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&spi1 { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "pnor"; +- spi-max-frequency = <100000000>; +- }; +-}; +- +-&spi2 { +- status = "okay"; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; +-}; +- +-&mac1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +-}; +- +-&i2c3 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c08"; +- reg = <0x50>; +- pagesize = <16>; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +- +- lm75@4d { +- compatible = "national,lm75"; +- reg = <0x4d>; +- }; +-}; +- +-&sdmmc { +- status = "okay"; +-}; +- +-&sdhci0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sd1_default>; +-}; +- +-/* +- * Enable port A as device (via the virtual hub) and port B as +- * host by default on the eval board. This can be easily changed +- * by replacing the override below with &ehci0 { ... } to enable +- * host on both ports. +- */ +-&vhub { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&uhci { +- status = "okay"; +-}; +- +-&gfx { +- status = "okay"; +- memory-region = <&gfx_memory>; +-}; +- +-&rtc { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-ast2600-evb-a1.dts b/scripts/dtc/include-prefixes/arm/aspeed-ast2600-evb-a1.dts +deleted file mode 100644 +index dd7148060c4a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-ast2600-evb-a1.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-// Copyright 2021 IBM Corp. +- +-#include "aspeed-ast2600-evb.dts" +- +-/ { +- model = "AST2600 A1 EVB"; +- +- /delete-node/regulator-vcc-sdhci0; +- /delete-node/regulator-vcc-sdhci1; +- /delete-node/regulator-vccq-sdhci0; +- /delete-node/regulator-vccq-sdhci1; +-}; +- +-/delete-node/ &sdc; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-ast2600-evb.dts b/scripts/dtc/include-prefixes/arm/aspeed-ast2600-evb.dts +deleted file mode 100644 +index b7eb552640cb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-ast2600-evb.dts ++++ /dev/null +@@ -1,302 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-// Copyright 2019 IBM Corp. +- +-/dts-v1/; +- +-#include "aspeed-g6.dtsi" +-#include +- +-/ { +- model = "AST2600 EVB"; +- compatible = "aspeed,ast2600"; +- +- aliases { +- serial4 = &uart5; +- }; +- +- chosen { +- bootargs = "console=ttyS4,115200n8"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x80000000>; +- }; +- +- vcc_sdhci0: regulator-vcc-sdhci0 { +- compatible = "regulator-fixed"; +- regulator-name = "SDHCI0 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhci0: regulator-vccq-sdhci0 { +- compatible = "regulator-gpio"; +- regulator-name = "SDHCI0 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, +- <1800000 0>; +- }; +- +- vcc_sdhci1: regulator-vcc-sdhci1 { +- compatible = "regulator-fixed"; +- regulator-name = "SDHCI1 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhci1: regulator-vccq-sdhci1 { +- compatible = "regulator-gpio"; +- regulator-name = "SDHCI1 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, +- <1800000 0>; +- }; +-}; +- +-&mdio0 { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +-}; +- +-&mdio1 { +- status = "okay"; +- +- ethphy1: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +-}; +- +-&mdio2 { +- status = "okay"; +- +- ethphy2: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +-}; +- +-&mdio3 { +- status = "okay"; +- +- ethphy3: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +-}; +- +-&mac0 { +- status = "okay"; +- +- phy-mode = "rgmii"; +- phy-handle = <ðphy0>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii1_default>; +-}; +- +- +-&mac1 { +- status = "okay"; +- +- phy-mode = "rgmii"; +- phy-handle = <ðphy1>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii2_default>; +-}; +- +-&mac2 { +- status = "okay"; +- +- phy-mode = "rgmii"; +- phy-handle = <ðphy2>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii3_default>; +-}; +- +-&mac3 { +- status = "okay"; +- +- phy-mode = "rgmii"; +- phy-handle = <ðphy3>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii4_default>; +-}; +- +-&emmc_controller { +- status = "okay"; +-}; +- +-&emmc { +- non-removable; +- bus-width = <4>; +- max-frequency = <100000000>; +- clk-phase-mmc-hs200 = <9>, <225>; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +- spi-max-frequency = <50000000>; +-#include "openbmc-flash-layout-64.dtsi" +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "pnor"; +- spi-max-frequency = <100000000>; +- }; +-}; +- +-&uart5 { +- // Workaround for A0 +- compatible = "snps,dw-apb-uart"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- temp@2e { +- compatible = "adi,adt7490"; +- reg = <0x2e>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- status = "okay"; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&i2c8 { +- status = "okay"; +-}; +- +-&i2c9 { +- status = "okay"; +-}; +- +-&i2c12 { +- status = "okay"; +-}; +- +-&i2c13 { +- status = "okay"; +-}; +- +-&i2c14 { +- status = "okay"; +-}; +- +-&i2c15 { +- status = "okay"; +-}; +- +-&fsim0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&uhci { +- status = "okay"; +-}; +- +-&sdc { +- status = "okay"; +-}; +- +-/* +- * The signal voltage of sdhci0 and sdhci1 on AST2600-A2 EVB is able to be +- * toggled by GPIO pins. +- * In the reference design, GPIOV0 of AST2600-A2 EVB is connected to the +- * power load switch that provides 3.3v to sdhci0 vdd, GPIOV1 is connected to +- * a 1.8v and a 3.3v power load switch that provides signal voltage to +- * sdhci0 bus. +- * If GPIOV0 is active high, sdhci0 is enabled, otherwise, sdhci0 is disabled. +- * If GPIOV1 is active high, 3.3v power load switch is enabled, sdhci0 signal +- * voltage is 3.3v, otherwise, 1.8v power load switch will be enabled, +- * sdhci0 signal voltage becomes 1.8v. +- * AST2600-A2 EVB also supports toggling signal voltage for sdhci1. +- * The design is the same as sdhci0, it uses GPIOV2 as power-gpio and GPIOV3 +- * as power-switch-gpio. +- */ +-&sdhci0 { +- status = "okay"; +- bus-width = <4>; +- max-frequency = <100000000>; +- sdhci-drive-type = /bits/ 8 <3>; +- sdhci-caps-mask = <0x7 0x0>; +- sdhci,wp-inverted; +- vmmc-supply = <&vcc_sdhci0>; +- vqmmc-supply = <&vccq_sdhci0>; +- clk-phase-sd-hs = <7>, <200>; +-}; +- +-&sdhci1 { +- status = "okay"; +- bus-width = <4>; +- max-frequency = <100000000>; +- sdhci-drive-type = /bits/ 8 <3>; +- sdhci-caps-mask = <0x7 0x0>; +- sdhci,wp-inverted; +- vmmc-supply = <&vcc_sdhci1>; +- vqmmc-supply = <&vccq_sdhci1>; +- clk-phase-sd-hs = <7>, <200>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-amd-ethanolx.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-amd-ethanolx.dts +deleted file mode 100644 +index 79d17841b3d7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-amd-ethanolx.dts ++++ /dev/null +@@ -1,320 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2020 AMD Inc. +-// Author: Supreeth Venkatesh +-/dts-v1/; +- +-#include "aspeed-g5.dtsi" +-#include +- +-/ { +- model = "AMD EthanolX BMC"; +- compatible = "amd,ethanolx-bmc", "aspeed,ast2500"; +- +- memory@80000000 { +- reg = <0x80000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- video_engine_memory: jpegbuffer { +- size = <0x02000000>; /* 32M */ +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- }; +- +- +- aliases { +- serial0 = &uart1; +- serial4 = &uart5; +- }; +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- leds { +- compatible = "gpio-leds"; +- +- fault { +- gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; +- }; +- +- identify { +- gpios = <&gpio ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>; +- }; +- }; +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>; +- }; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- #include "openbmc-flash-layout.dtsi" +- }; +-}; +- +- +-&mac0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +-}; +- +-&uart1 { +- //Host Console +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default>; +-}; +- +-&uart5 { +- //BMC Console +- status = "okay"; +-}; +- +-&adc { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc0_default +- &pinctrl_adc1_default +- &pinctrl_adc2_default +- &pinctrl_adc3_default +- &pinctrl_adc4_default>; +-}; +- +-&gpio { +- status = "okay"; +- gpio-line-names = +- /*A0-A7*/ "","","FAULT_LED","CHASSIS_ID_LED","","","","", +- /*B0-B7*/ "","","","","","","","", +- /*C0-C7*/ "CHASSIS_ID_BTN","INTRUDER","AC_LOSS","","","","","", +- /*D0-D7*/ "HDT_DBREQ","LOCAL_SPI_ROM_SEL","FPGA_SPI_ROM_SEL","JTAG_MUX_S", +- "JTAG_MUX_OE","HDT_SEL","ASERT_WARM_RST_BTN","FPGA_RSVD", +- /*E0-E7*/ "","","MON_P0_PWR_BTN","MON_P0_RST_BTN","MON_P0_NMI_BTN", +- "MON_P0_PWR_GOOD","MON_PWROK","MON_RESET", +- /*F0-F7*/ "MON_P0_PROCHOT","MON_P1_PROCHOT","MON_P0_THERMTRIP", +- "MON_P1_THERMTRIP","P0_PRESENT","P1_PRESENT","MON_ATX_PWR_OK","", +- /*G0-G7*/ "BRD_REV_ID_3","BRD_REV_ID_2","BRD_REV_ID_1","BRD_REV_ID_0", +- "P0_APML_ALERT","P1_APML_ALERT","FPGA ALERT","", +- /*H0-H7*/ "BRD_ID_0","BRD_ID_1","BRD_ID_2","BRD_ID_3", +- "PCIE_DISCONNECTED","USB_DISCONNECTED","SPARE_0","SPARE_1", +- /*I0-I7*/ "","","","","","","","", +- /*J0-J7*/ "","","","","","","","", +- /*K0-K7*/ "","","","","","","","", +- /*L0-L7*/ "","","","","","","","", +- /*M0-M7*/ "ASSERT_PWR_BTN","ASSERT_RST_BTN","ASSERT_NMI_BTN", +- "ASSERT_LOCAL_LOCK","ASSERT_P0_PROCHOT","ASSERT_P1_PROCHOT", +- "ASSERT_CLR_CMOS","ASSERT_BMC_READY", +- /*N0-N7*/ "","","","","","","","", +- /*O0-O7*/ "","","","","","","","", +- /*P0-P7*/ "P0_VDD_CORE_RUN_VRHOT","P0_VDD_SOC_RUN_VRHOT", +- "P0_VDD_MEM_ABCD_SUS_VRHOT","P0_VDD_MEM_EFGH_SUS_VRHOT", +- "P1_VDD_CORE_RUN_VRHOT","P1_VDD_SOC_RUN_VRHOT", +- "P1_VDD_MEM_ABCD_SUS_VRHOT","P1_VDD_MEM_EFGH_SUS_VRHOT", +- /*Q0-Q7*/ "","","","","","","","", +- /*R0-R7*/ "","","","","","","","", +- /*S0-S7*/ "","","","","","","","", +- /*T0-T7*/ "","","","","","","","", +- /*U0-U7*/ "","","","","","","","", +- /*V0-V7*/ "","","","","","","","", +- /*W0-W7*/ "","","","","","","","", +- /*X0-X7*/ "","","","","","","","", +- /*Y0-Y7*/ "","","","","","","","", +- /*Z0-Z7*/ "","","","","","","","", +- /*AA0-AA7*/ "","SENSOR THERM","","","","","","", +- /*AB0-AB7*/ "","","","","","","","", +- /*AC0-AC7*/ "","","","","","","",""; +-}; +- +-//APML for P0 +-&i2c0 { +- status = "okay"; +-}; +- +-//APML for P1 +-&i2c1 { +- status = "okay"; +-}; +- +-//FPGA +-&i2c2 { +- status = "okay"; +-}; +- +-//24LC128 EEPROM +-&i2c3 { +- status = "okay"; +-}; +- +-//P0 Power regulators +-&i2c4 { +- status = "okay"; +-}; +- +-//P1 Power regulators +-&i2c5 { +- status = "okay"; +-}; +- +-//P0/P1 Thermal diode +-&i2c6 { +- status = "okay"; +-}; +- +-// Thermal Sensors +-&i2c7 { +- status = "okay"; +- +- lm75a@48 { +- compatible = "national,lm75a"; +- reg = <0x48>; +- }; +- +- lm75a@49 { +- compatible = "national,lm75a"; +- reg = <0x49>; +- }; +- +- lm75a@4a { +- compatible = "national,lm75a"; +- reg = <0x4a>; +- }; +- +- lm75a@4b { +- compatible = "national,lm75a"; +- reg = <0x4b>; +- }; +- +- lm75a@4c { +- compatible = "national,lm75a"; +- reg = <0x4c>; +- }; +- +- lm75a@4d { +- compatible = "national,lm75a"; +- reg = <0x4d>; +- }; +- +- lm75a@4e { +- compatible = "national,lm75a"; +- reg = <0x4e>; +- }; +- +- lm75a@4f { +- compatible = "national,lm75a"; +- reg = <0x4f>; +- }; +-}; +- +-//BMC I2C +-&i2c8 { +- status = "okay"; +-}; +- +-&kcs1 { +- status = "okay"; +- aspeed,lpc-io-reg = <0x60>; +-}; +- +-&kcs2 { +- status = "okay"; +- aspeed,lpc-io-reg = <0x62>; +-}; +- +-&kcs3 { +- status = "okay"; +- aspeed,lpc-io-reg = <0xCA2>; +-}; +- +-&kcs4 { +- status = "okay"; +- aspeed,lpc-io-reg = <0x97DE>; +-}; +- +-&lpc_snoop { +- status = "okay"; +- snoop-ports = <0x80>, <0x81>; +-}; +- +-&lpc_ctrl { +- //Enable lpc clock +- status = "okay"; +-}; +- +-&pwm_tacho { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default +- &pinctrl_pwm1_default +- &pinctrl_pwm2_default +- &pinctrl_pwm3_default +- &pinctrl_pwm4_default +- &pinctrl_pwm5_default +- &pinctrl_pwm6_default +- &pinctrl_pwm7_default>; +- +- fan@0 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x00>; +- }; +- +- fan@1 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x01>; +- }; +- +- fan@2 { +- reg = <0x02>; +- aspeed,fan-tach-ch = /bits/ 8 <0x02>; +- }; +- +- fan@3 { +- reg = <0x03>; +- aspeed,fan-tach-ch = /bits/ 8 <0x03>; +- }; +- +- fan@4 { +- reg = <0x04>; +- aspeed,fan-tach-ch = /bits/ 8 <0x04>; +- }; +- +- fan@5 { +- reg = <0x05>; +- aspeed,fan-tach-ch = /bits/ 8 <0x05>; +- }; +- +- fan@6 { +- reg = <0x06>; +- aspeed,fan-tach-ch = /bits/ 8 <0x06>; +- }; +- +- fan@7 { +- reg = <0x07>; +- aspeed,fan-tach-ch = /bits/ 8 <0x07>; +- }; +-}; +- +-&video { +- status = "okay"; +- memory-region = <&video_engine_memory>; +-}; +- +-&vhub { +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-ampere-mtjade.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-ampere-mtjade.dts +deleted file mode 100644 +index 57b0c45a2298..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-ampere-mtjade.dts ++++ /dev/null +@@ -1,607 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/dts-v1/; +-#include "aspeed-g5.dtsi" +-#include +- +-/ { +- model = "Ampere Mt. Jade BMC"; +- compatible = "ampere,mtjade-bmc", "aspeed,ast2500"; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- vga_memory: framebuffer@9f000000 { +- no-map; +- reg = <0x9f000000 0x01000000>; /* 16M */ +- }; +- +- gfx_memory: framebuffer { +- size = <0x01000000>; +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- +- video_engine_memory: jpegbuffer { +- size = <0x02000000>; /* 32M */ +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- fault { +- gpios = <&gpio ASPEED_GPIO(B, 6) GPIO_ACTIVE_HIGH>; +- }; +- +- identify { +- gpios = <&gpio ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- shutdown_ack { +- label = "SHUTDOWN_ACK"; +- gpios = <&gpio ASPEED_GPIO(G, 2) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- reboot_ack { +- label = "REBOOT_ACK"; +- gpios = <&gpio ASPEED_GPIO(J, 3) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- S0_overtemp { +- label = "S0_OVERTEMP"; +- gpios = <&gpio ASPEED_GPIO(G, 3) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- S0_hightemp { +- label = "S0_HIGHTEMP"; +- gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- S0_cpu_fault { +- label = "S0_CPU_FAULT"; +- gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>; +- linux,code = ; +- }; +- +- S1_overtemp { +- label = "S1_OVERTEMP"; +- gpios = <&gpio ASPEED_GPIO(Z, 6) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- S1_hightemp { +- label = "S1_HIGHTEMP"; +- gpios = <&gpio ASPEED_GPIO(AB, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- S1_cpu_fault { +- label = "S1_CPU_FAULT"; +- gpios = <&gpio ASPEED_GPIO(Z, 1) GPIO_ACTIVE_HIGH>; +- linux,code = ; +- }; +- +- id_button { +- label = "ID_BUTTON"; +- gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- psu1_vin_good { +- label = "PSU1_VIN_GOOD"; +- gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- psu2_vin_good { +- label = "PSU2_VIN_GOOD"; +- gpios = <&gpio ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- psu1_present { +- label = "PSU1_PRESENT"; +- gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- psu2_present { +- label = "PSU2_PRESENT"; +- gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- }; +- +- gpioA0mux: mux-controller { +- compatible = "gpio-mux"; +- #mux-control-cells = <0>; +- mux-gpios = <&gpio ASPEED_GPIO(A, 0) GPIO_ACTIVE_LOW>; +- }; +- +- adc0mux: adc0mux { +- compatible = "io-channel-mux"; +- io-channels = <&adc 0>; +- #io-channel-cells = <1>; +- io-channel-names = "parent"; +- mux-controls = <&gpioA0mux>; +- channels = "s0", "s1"; +- }; +- +- adc1mux: adc1mux { +- compatible = "io-channel-mux"; +- io-channels = <&adc 1>; +- #io-channel-cells = <1>; +- io-channel-names = "parent"; +- mux-controls = <&gpioA0mux>; +- channels = "s0", "s1"; +- }; +- +- adc2mux: adc2mux { +- compatible = "io-channel-mux"; +- io-channels = <&adc 2>; +- #io-channel-cells = <1>; +- io-channel-names = "parent"; +- mux-controls = <&gpioA0mux>; +- channels = "s0", "s1"; +- }; +- +- adc3mux: adc3mux { +- compatible = "io-channel-mux"; +- io-channels = <&adc 3>; +- #io-channel-cells = <1>; +- io-channel-names = "parent"; +- mux-controls = <&gpioA0mux>; +- channels = "s0", "s1"; +- }; +- +- adc4mux: adc4mux { +- compatible = "io-channel-mux"; +- io-channels = <&adc 4>; +- #io-channel-cells = <1>; +- io-channel-names = "parent"; +- mux-controls = <&gpioA0mux>; +- channels = "s0", "s1"; +- }; +- +- adc5mux: adc5mux { +- compatible = "io-channel-mux"; +- io-channels = <&adc 5>; +- #io-channel-cells = <1>; +- io-channel-names = "parent"; +- mux-controls = <&gpioA0mux>; +- channels = "s0", "s1"; +- }; +- +- adc6mux: adc6mux { +- compatible = "io-channel-mux"; +- io-channels = <&adc 6>; +- #io-channel-cells = <1>; +- io-channel-names = "parent"; +- mux-controls = <&gpioA0mux>; +- channels = "s0", "s1"; +- }; +- +- adc7mux: adc7mux { +- compatible = "io-channel-mux"; +- io-channels = <&adc 7>; +- #io-channel-cells = <1>; +- io-channel-names = "parent"; +- mux-controls = <&gpioA0mux>; +- channels = "s0", "s1"; +- }; +- +- adc8mux: adc8mux { +- compatible = "io-channel-mux"; +- io-channels = <&adc 8>; +- #io-channel-cells = <1>; +- io-channel-names = "parent"; +- mux-controls = <&gpioA0mux>; +- channels = "s0", "s1"; +- }; +- +- adc9mux: adc9mux { +- compatible = "io-channel-mux"; +- io-channels = <&adc 9>; +- #io-channel-cells = <1>; +- io-channel-names = "parent"; +- mux-controls = <&gpioA0mux>; +- channels = "s0", "s1"; +- }; +- +- adc10mux: adc10mux { +- compatible = "io-channel-mux"; +- io-channels = <&adc 10>; +- #io-channel-cells = <1>; +- io-channel-names = "parent"; +- mux-controls = <&gpioA0mux>; +- channels = "s0", "s1"; +- }; +- +- adc11mux: adc11mux { +- compatible = "io-channel-mux"; +- io-channels = <&adc 11>; +- #io-channel-cells = <1>; +- io-channel-names = "parent"; +- mux-controls = <&gpioA0mux>; +- channels = "s0", "s1"; +- }; +- +- adc12mux: adc12mux { +- compatible = "io-channel-mux"; +- io-channels = <&adc 12>; +- #io-channel-cells = <1>; +- io-channel-names = "parent"; +- mux-controls = <&gpioA0mux>; +- channels = "s0", "s1"; +- }; +- +- adc13mux: adc13mux { +- compatible = "io-channel-mux"; +- io-channels = <&adc 13>; +- #io-channel-cells = <1>; +- io-channel-names = "parent"; +- mux-controls = <&gpioA0mux>; +- channels = "s0", "s1"; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc0mux 0>, <&adc0mux 1>, +- <&adc1mux 0>, <&adc1mux 1>, +- <&adc2mux 0>, <&adc2mux 1>, +- <&adc3mux 0>, <&adc3mux 1>, +- <&adc4mux 0>, <&adc4mux 1>, +- <&adc5mux 0>, <&adc5mux 1>, +- <&adc6mux 0>, <&adc6mux 1>, +- <&adc7mux 0>, <&adc7mux 1>, +- <&adc8mux 0>, <&adc8mux 1>, +- <&adc9mux 0>, <&adc9mux 1>, +- <&adc10mux 0>, <&adc10mux 1>, +- <&adc11mux 0>, <&adc11mux 1>, +- <&adc12mux 0>, <&adc12mux 1>, +- <&adc13mux 0>, <&adc13mux 1>; +- }; +- +- iio-hwmon-adc14 { +- compatible = "iio-hwmon"; +- io-channels = <&adc 14>; +- }; +- +- iio-hwmon-battery { +- compatible = "iio-hwmon"; +- io-channels = <&adc 15>; +- }; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +- /* spi-max-frequency = <50000000>; */ +-#include "openbmc-flash-layout-64.dtsi" +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "pnor"; +- /* spi-max-frequency = <100000000>; */ +- }; +-}; +- +-&uart1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default +- &pinctrl_ncts1_default +- &pinctrl_nrts1_default>; +-}; +- +-&uart2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd2_default +- &pinctrl_rxd2_default>; +-}; +- +-&uart3 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd3_default +- &pinctrl_rxd3_default>; +-}; +- +-&uart4 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd4_default +- &pinctrl_rxd4_default>; +-}; +- +-/* The BMC's uart */ +-&uart5 { +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&mac1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +- eeprom@50 { +- compatible = "microchip,24c64", "atmel,24c64"; +- reg = <0x50>; +- pagesize = <32>; +- }; +- +- inlet_mem2: tmp175@28 { +- compatible = "ti,tmp175"; +- reg = <0x28>; +- }; +- +- inlet_cpu: tmp175@29 { +- compatible = "ti,tmp175"; +- reg = <0x29>; +- }; +- +- inlet_mem1: tmp175@2a { +- compatible = "ti,tmp175"; +- reg = <0x2a>; +- }; +- +- outlet_cpu: tmp175@2b { +- compatible = "ti,tmp175"; +- reg = <0x2b>; +- }; +- +- outlet1: tmp175@2c { +- compatible = "ti,tmp175"; +- reg = <0x2c>; +- }; +- +- outlet2: tmp175@2d { +- compatible = "ti,tmp175"; +- reg = <0x2d>; +- }; +-}; +- +-&i2c4 { +- status = "okay"; +- rtc@51 { +- compatible = "nxp,pcf85063a"; +- reg = <0x51>; +- }; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- status = "okay"; +- psu@58 { +- compatible = "pmbus"; +- reg = <0x58>; +- }; +- +- psu@59 { +- compatible = "pmbus"; +- reg = <0x59>; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&i2c8 { +- status = "okay"; +-}; +- +-&i2c9 { +- status = "okay"; +-}; +- +-&i2c10 { +- status = "okay"; +- adm1278@10 { +- compatible = "adi,adm1278"; +- reg = <0x10>; +- }; +- +- adm1278@11 { +- compatible = "adi,adm1278"; +- reg = <0x11>; +- }; +-}; +- +-&gfx { +- status = "okay"; +- memory-region = <&gfx_memory>; +-}; +- +-&pinctrl { +- aspeed,external-nodes = <&gfx &lhc>; +-}; +- +-&pwm_tacho { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2_default &pinctrl_pwm3_default +- &pinctrl_pwm4_default &pinctrl_pwm5_default +- &pinctrl_pwm6_default &pinctrl_pwm7_default>; +- +- fan@0 { +- reg = <0x02>; +- aspeed,fan-tach-ch = /bits/ 8 <0x04>; +- }; +- +- fan@1 { +- reg = <0x02>; +- aspeed,fan-tach-ch = /bits/ 8 <0x05>; +- }; +- +- fan@2 { +- reg = <0x03>; +- aspeed,fan-tach-ch = /bits/ 8 <0x06>; +- }; +- +- fan@3 { +- reg = <0x03>; +- aspeed,fan-tach-ch = /bits/ 8 <0x07>; +- }; +- +- fan@4 { +- reg = <0x04>; +- aspeed,fan-tach-ch = /bits/ 8 <0x08>; +- }; +- +- fan@5 { +- reg = <0x04>; +- aspeed,fan-tach-ch = /bits/ 8 <0x09>; +- }; +- +- fan@6 { +- reg = <0x05>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0a>; +- }; +- +- fan@7 { +- reg = <0x05>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0b>; +- }; +- +- fan@8 { +- reg = <0x06>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0c>; +- }; +- +- fan@9 { +- reg = <0x06>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0d>; +- }; +- +- fan@10 { +- reg = <0x07>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0e>; +- }; +- +- fan@11 { +- reg = <0x07>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0f>; +- }; +- +-}; +- +-&vhub { +- status = "okay"; +-}; +- +-&adc { +- status = "okay"; +-}; +- +-&video { +- status = "okay"; +- memory-region = <&video_engine_memory>; +-}; +- +-&gpio { +- gpio-line-names = +- /*A0-A7*/ "","","","S0_BMC_SPECIAL_BOOT","","","","", +- /*B0-B7*/ "BMC_SELECT_EEPROM","","","", +- "POWER_BUTTON","","","", +- /*C0-C7*/ "","","","","","","","", +- /*D0-D7*/ "","","","","","","","", +- /*E0-E7*/ "","","","","","","","", +- /*F0-F7*/ "","","BMC_SYS_PSON_L","S0_DDR_SAVE","PGOOD", +- "S1_DDR_SAVE","","", +- /*G0-G7*/ "S0_FW_BOOT_OK","SHD_REQ_L","","S0_OVERTEMP_L","","", +- "","", +- /*H0-H7*/ "","","","","PSU1_VIN_GOOD","PSU2_VIN_GOOD","","", +- /*I0-I7*/ "PSU1_PRESENT","PSU2_PRESENT","S1_BMC_SPECIAL_BOOT", +- "","","","","", +- /*J0-J7*/ "S0_HIGHTEMP_L","S0_FAULT_L","S0_SCP_AUTH_FAIL_L","", +- "","","","", +- /*K0-K7*/ "","","","","","","","", +- /*L0-L7*/ "","","","BMC_SYSRESET_L","SPI_AUTH_FAIL_L","","","", +- /*M0-M7*/ "","","","","","","","", +- /*N0-N7*/ "","","","","","","","", +- /*O0-O7*/ "","","","","","","","", +- /*P0-P7*/ "","","","","","","","", +- /*Q0-Q7*/ "","","","","","UID_BUTTON","","", +- /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN", +- "OCP_MAIN_PWREN","RESET_BUTTON","","", +- /*S0-S7*/ "","","","","","","","", +- /*T0-T7*/ "","","","","","","","", +- /*U0-U7*/ "","","","","","","","", +- /*V0-V7*/ "","","","","","","","", +- /*W0-W7*/ "","","","","","","","", +- /*X0-X7*/ "","","","","","","","", +- /*Y0-Y7*/ "","","","","","","","", +- /*Z0-Z7*/ "S0_BMC_PLIMIT","S1_FAULT_L","S1_FW_BOOT_OK","","", +- "S1_SCP_AUTH_FAIL_L","S1_OVERTEMP_L","", +- /*AA0-AA7*/ "","","","","","","","", +- /*AB0-AB7*/ "S1_HIGHTEMP_L","S1_BMC_PLIMIT","S0_BMC_DDR_ADDR", +- "S1_BMC_DDR_ADR","","","","", +- /*AC0-AC7*/ "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L", +- "BMC_OCP_PG"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-arm-centriq2400-rep.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-arm-centriq2400-rep.dts +deleted file mode 100644 +index 3395de96ee11..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-arm-centriq2400-rep.dts ++++ /dev/null +@@ -1,225 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/dts-v1/; +- +-#include "aspeed-g5.dtsi" +-#include +- +-/ { +- model = "Qualcomm Centriq 2400 REP AST2520"; +- compatible = "qualcomm,centriq2400-rep-bmc", "aspeed,ast2500"; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x40000000>; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, +- <&adc 4>, <&adc 5>, <&adc 6>, <&adc 8>; +- }; +- +- iio-hwmon-battery { +- compatible = "iio-hwmon"; +- io-channels = <&adc 7>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- uid_led { +- label = "UID_LED"; +- gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>; +- }; +- +- ras_error_led { +- label = "RAS_ERROR_LED"; +- gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; +- }; +- +- system_fault { +- label = "System_fault"; +- gpios = <&gpio ASPEED_GPIO(A, 1) GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- flash@0 { +- status = "okay"; +- }; +-}; +- +-&spi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi2ck_default +- &pinctrl_spi2miso_default +- &pinctrl_spi2mosi_default +- &pinctrl_spi2cs0_default>; +-}; +- +-&uart3 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; +- current-speed = <115200>; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- +- tmp421@1e { +- compatible = "ti,tmp421"; +- reg = <0x1e>; +- }; +- tmp421@2a { +- compatible = "ti,tmp421"; +- reg = <0x2a>; +- }; +- tmp421@4e { +- compatible = "ti,tmp421"; +- reg = <0x4e>; +- }; +- tmp421@1c { +- compatible = "ti,tmp421"; +- reg = <0x1c>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- status = "okay"; +- +- tmp421@1d { +- compatible = "ti,tmp421"; +- reg = <0x1d>; +- }; +- tmp421@1f { +- compatible = "ti,tmp421"; +- reg = <0x1f>; +- }; +- tmp421@4d { +- compatible = "ti,tmp421"; +- reg = <0x4d>; +- }; +- tmp421@4f { +- compatible = "ti,tmp421"; +- reg = <0x4f>; +- }; +- nvt210@4c { +- compatible = "nvt210"; +- reg = <0x4c>; +- }; +- eeprom@50 { +- compatible = "atmel,24c128"; +- reg = <0x50>; +- pagesize = <128>; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&i2c8 { +- status = "okay"; +- +- pca9641@70 { +- compatible = "nxp,pca9641"; +- reg = <0x70>; +- i2c-arb { +- #address-cells = <1>; +- #size-cells = <0>; +- tmp421@1d { +- compatible = "tmp421"; +- reg = <0x1d>; +- }; +- adm1278@12 { +- compatible = "adi,adm1278"; +- reg = <0x12>; +- Rsense = <500>; +- }; +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- }; +- ds1100@58 { +- compatible = "ds1100"; +- reg = <0x58>; +- }; +- }; +- }; +-}; +- +-&i2c9 { +- status = "okay"; +-}; +- +-&vuart { +- status = "okay"; +-}; +- +-&gfx { +- status = "okay"; +-}; +- +-&pinctrl { +- aspeed,external-nodes = <&gfx &lhc>; +-}; +- +-&gpio { +- pin_gpio_c7 { +- gpio-hog; +- gpios = ; +- output; +- line-name = "BIOS_SPI_MUX_S"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-arm-stardragon4800-rep2.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-arm-stardragon4800-rep2.dts +deleted file mode 100644 +index 7c6af7f226e7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-arm-stardragon4800-rep2.dts ++++ /dev/null +@@ -1,220 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/dts-v1/; +- +-#include "aspeed-g5.dtsi" +-#include +- +-/ { +- model = "HXT StarDragon 4800 REP2 AST2520"; +- compatible = "hxt,stardragon4800-rep2-bmc", "aspeed,ast2500"; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x40000000>; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, +- <&adc 4>, <&adc 5>, <&adc 6>, <&adc 8>; +- }; +- +- iio-hwmon-battery { +- compatible = "iio-hwmon"; +- io-channels = <&adc 7>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- system_fault1 { +- label = "System_fault1"; +- gpios = <&gpio ASPEED_GPIO(I, 3) GPIO_ACTIVE_LOW>; +- }; +- +- system_fault2 { +- label = "System_fault2"; +- gpios = <&gpio ASPEED_GPIO(I, 2) GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- flash@0 { +- status = "okay"; +- }; +-}; +- +-&spi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi2ck_default +- &pinctrl_spi2miso_default +- &pinctrl_spi2mosi_default +- &pinctrl_spi2cs0_default>; +-}; +- +-&uart3 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; +- current-speed = <115200>; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; +-}; +- +-&mac1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii2_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>, +- <&syscon ASPEED_CLK_MAC2RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- +- tmp421@1e { +- compatible = "ti,tmp421"; +- reg = <0x1e>; +- }; +- tmp421@2a { +- compatible = "ti,tmp421"; +- reg = <0x2a>; +- }; +- tmp421@1c { +- compatible = "ti,tmp421"; +- reg = <0x1c>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- status = "okay"; +- +- tmp421@1f { +- compatible = "ti,tmp421"; +- reg = <0x1f>; +- }; +- nvt210@4c { +- compatible = "nvt210"; +- reg = <0x4c>; +- }; +- eeprom@50 { +- compatible = "atmel,24c128"; +- reg = <0x50>; +- pagesize = <128>; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&i2c8 { +- status = "okay"; +- +- pca9641@70 { +- compatible = "nxp,pca9641"; +- reg = <0x70>; +- i2c-arb { +- #address-cells = <1>; +- #size-cells = <0>; +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- }; +- dps650ab@58 { +- compatible = "dps650ab"; +- reg = <0x58>; +- }; +- }; +- }; +- +- dps650ab@58 { +- compatible = "delta,dps650ab"; +- reg = <0x58>; +- }; +- +- dps650ab@59 { +- compatible = "delta,dps650ab"; +- reg = <0x59>; +- }; +-}; +- +-&i2c9 { +- status = "okay"; +-}; +- +-&vuart { +- status = "okay"; +-}; +- +-&gfx { +- status = "okay"; +-}; +- +-&pinctrl { +- aspeed,external-nodes = <&gfx &lhc>; +-}; +- +-&gpio { +- pin_gpio_c7 { +- gpio-hog; +- gpios = ; +- output-low; +- line-name = "BIOS_SPI_MUX_S"; +- }; +- pin_gpio_d1 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "PHY2_RESET_N"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-asrock-e3c246d4i.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-asrock-e3c246d4i.dts +deleted file mode 100644 +index 9b4cf5ebe6d5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-asrock-e3c246d4i.dts ++++ /dev/null +@@ -1,204 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/dts-v1/; +- +-#include "aspeed-g5.dtsi" +-#include +-#include +-#include +- +-/{ +- model = "ASRock E3C246D4I BMC"; +- compatible = "asrock,e3c246d4i-bmc", "aspeed,ast2500"; +- +- aliases { +- serial4 = &uart5; +- }; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=tty0 console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x20000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- heartbeat { +- /* BMC_HB_LED_N */ +- gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>; +- linux,default-trigger = "timer"; +- }; +- +- system-fault { +- /* SYSTEM_FAULT_LED_N */ +- gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; +- panic-indicator; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- uid-button { +- label = "uid-button"; +- gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, +- <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>, +- <&adc 10>, <&adc 11>, <&adc 12>; +- }; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +- spi-max-frequency = <100000000>; /* 100 MHz */ +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&vuart { +- status = "okay"; +- aspeed,lpc-io-reg = <0x2f8>; +- aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&mac0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; +-}; +- +-&i2c1 { +- status = "okay"; +- +- /* thermal sensor, one diode run to a disconnected header */ +- w83773g@4c { +- compatible = "nuvoton,w83773g"; +- reg = <0x4c>; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +- +- /* FRU EEPROM */ +- eeprom@57 { +- compatible = "st,24c128", "atmel,24c128"; +- reg = <0x57>; +- pagesize = <16>; +- }; +-}; +- +-&video { +- status = "okay"; +-}; +- +-&vhub { +- status = "okay"; +-}; +- +-&lpc_ctrl { +- status = "okay"; +-}; +- +-&lpc_snoop { +- status = "okay"; +- snoop-ports = <0x80>; +-}; +- +-&gpio { +- status = "okay"; +- gpio-line-names = +- /* A */ "BMC_MAC1_INTB", "BMC_MAC2_INTB", "NMI_BTN_N", "BMC_NMI", +- "", "", "", "", +- /* B */ "", "", "", "", "", "IRQ_BMC_PCH_SMI_LPC_N", "", "", +- /* C */ "", "", "", "", "", "", "", "", +- /* D */ "BMC_PSIN", "BMC_PSOUT", "BMC_RESETCON", "RESETCON", +- "", "", "", "", +- /* E */ "", "", "", "", "", "", "", "", +- /* F */ "LOCATORLED_STATUS_N", "LOCATORBTN", "", "", +- "", "", "BMC_PCH_SCI_LPC", "BMC_NCSI_MUX_CTL", +- /* G */ "HWM_BAT_EN", "CHASSIS_ID0", "CHASSIS_ID1", "CHASSIS_ID2", +- "BMC_ALERT1_N_R", "BMC_ALERT2_N_R", "BMC_ALERT3_N", "SML0ALERT", +- /* H */ "FM_ME_RCVR_N", "O_PWROK", "SKL_CNL_R", "D4_DIMM_EVENT_3V_N", +- "MFG_MODE_N", "BMC_RTCRST", "BMC_HB_LED_N", "BMC_CASEOPEN", +- /* I */ "", "", "", "", "", "", "", "", +- /* J */ "BMC_READY", "BMC_PCH_BIOS_CS_N", "BMC_SMI", "", +- "", "", "", "", +- /* K */ "", "", "", "", "", "", "", "", +- /* L */ "BMC_CTS1", "BMC_DCD1", "BMC_DSR1", "BMC_RI1", +- "BMC_DTR1", "BMC_RTS1", "BMC_TXD1", "BMC_RXD1", +- /* M */ "BMC_LAN0_DIS_N", "BMC_LAN1_DIS_N", "", "", +- "", "", "", "", +- /* N */ "", "", "", "", "", "", "", "", +- /* O */ "", "", "", "", "", "", "", "", +- /* P */ "", "", "", "", "", "", "", "", +- /* Q */ "", "", "", "", +- "BMC_SBM_PRESENT_1_N", "BMC_SBM_PRESENT_2_N", +- "BMC_SBM_PRESENT_3_N", "BMC_PCIE_WAKE_N", +- /* R */ "", "", "", "", "", "", "", "", +- /* S */ "PCHHOT_BMC_N", "", "RSMRST", +- "", "", "", "", "", +- /* T */ "", "", "", "", "", "", "", "", +- /* U */ "", "", "", "", "", "", "", "", +- /* V */ "", "", "", "", "", "", "", "", +- /* W */ "PS_PWROK", /* dummy always-high signal */ +- "", "", "", "", "", "", "", +- /* X */ "", "", "", "", "", "", "", "", +- /* Y */ "SLP_S3", "SLP_S5", "", "", "", "", "", "", +- /* Z */ "CPU_CATERR_BMC_PCH_N", "", "SYSTEM_FAULT_LED_N", "BMC_THROTTLE_N", +- "", "", "", "", +- /* AA */ "CPU1_THERMTRIP_LATCH_N", "", "CPU1_PROCHOT_N", "", +- "", "", "IRQ_SMI_ACTIVE_N", "FM_BIOS_POST_CMPLT_N", +- /* AB */ "", "", "ME_OVERRIDE", "BMC_DMI_MODIFY", +- "", "", "", "", +- /* AC */ "LAD0", "LAD1", "LAD2", "LAD3", +- "CK_33M_BMC", "LFRAME", "SERIRQ", "S_PLTRST"; +- +- /* Assert BMC_READY so BIOS doesn't sit around waiting for it */ +- bmc-ready { +- gpio-hog; +- gpios = ; +- output-high; +- }; +-}; +- +-&adc { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc0_default +- &pinctrl_adc1_default +- &pinctrl_adc2_default +- &pinctrl_adc3_default +- &pinctrl_adc4_default +- &pinctrl_adc5_default +- &pinctrl_adc6_default +- &pinctrl_adc7_default +- &pinctrl_adc8_default +- &pinctrl_adc9_default +- &pinctrl_adc10_default +- &pinctrl_adc11_default +- &pinctrl_adc12_default>; +-}; +- +-&kcs3 { +- status = "okay"; +- aspeed,lpc-io-reg = <0xca2>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-bytedance-g220a.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-bytedance-g220a.dts +deleted file mode 100644 +index 01dace8f5e5f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-bytedance-g220a.dts ++++ /dev/null +@@ -1,928 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright (C) 2020 Bytedance. +-/dts-v1/; +- +-#include "aspeed-g5.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "Bytedance G220A BMC"; +- compatible = "bytedance,g220a-bmc", "aspeed,ast2500"; +- +- aliases { +- serial4 = &uart5; +- i2c14 = &channel_3_0; +- i2c15 = &channel_3_1; +- i2c16 = &channel_3_2; +- i2c17 = &channel_3_3; +- i2c18 = &channel_6_0; +- i2c19 = &channel_6_1; +- i2c20 = &channel_6_2; +- i2c21 = &channel_6_3; +- i2c22 = &channel_6_4; +- i2c23 = &channel_6_5; +- i2c24 = &channel_6_6; +- i2c25 = &channel_6_7; +- i2c26 = &channel_6_8; +- i2c27 = &channel_6_9; +- i2c28 = &channel_6_10; +- i2c29 = &channel_6_11; +- i2c30 = &channel_6_12; +- i2c31 = &channel_6_13; +- i2c32 = &channel_6_14; +- i2c33 = &channel_6_15; +- i2c34 = &channel_6_16; +- i2c35 = &channel_6_17; +- i2c36 = &channel_6_18; +- i2c37 = &channel_6_19; +- i2c38 = &channel_6_20; +- i2c39 = &channel_6_21; +- i2c40 = &channel_6_22; +- i2c41 = &channel_6_23; +- i2c42 = &channel_6_24; +- i2c43 = &channel_6_25; +- i2c44 = &channel_10_0; +- i2c45 = &channel_10_1; +- i2c46 = &channel_10_2; +- i2c47 = &channel_10_3; +- i2c48 = &channel_10_4; +- i2c49 = &channel_10_5; +- i2c50 = &channel_10_6; +- i2c51 = &channel_10_7; +- }; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x40000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- vga_memory: framebuffer@bc000000 { +- no-map; +- reg = <0xbc000000 0x04000000>; /* 64M */ +- }; +- +- video_engine_memory: jpegbuffer { +- size = <0x02000000>; /* 32M */ +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, +- <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, +- <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, +- <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- bmc_alive { +- label = "bmc_alive"; +- gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>; +- linux,default-trigger = "timer"; +- led-pattern = <1000 1000>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- burn-in-signal { +- label = "burn-in"; +- gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- poll-interval = <1000>; +- +- rear-riser1-presence { +- label = "rear-riser1-presence"; +- gpios = <&pca0 1 GPIO_ACTIVE_LOW>; +- linux,code = <1>; +- }; +- +- alrt-pvddq-cpu0 { +- label = "alrt-pvddq-cpu0"; +- gpios = <&pca0 8 GPIO_ACTIVE_LOW>; +- linux,code = <2>; +- }; +- +- rear-riser0-presence { +- label = "rear-riser0-presence"; +- gpios = <&pca0 9 GPIO_ACTIVE_LOW>; +- linux,code = <3>; +- }; +- +- fault-pvddq-cpu0 { +- label = "fault-pvddq-cpu0"; +- gpios = <&pca0 10 GPIO_ACTIVE_LOW>; +- linux,code = <4>; +- }; +- +- alrt-pvddq-cpu1 { +- label = "alrt-pvddq-cpu1"; +- gpios = <&pca0 11 GPIO_ACTIVE_LOW>; +- linux,code = <5>; +- }; +- +- fault-pvddq-cpu1 { +- label = "alrt-pvddq-cpu1"; +- gpios = <&pca0 12 GPIO_ACTIVE_LOW>; +- linux,code = <6>; +- }; +- +- fault-pvccin-cpu1 { +- label = "fault-pvccin-cpuq"; +- gpios = <&pca0 13 GPIO_ACTIVE_LOW>; +- linux,code = <7>; +- }; +- +- bmc-rom0-wp { +- label = "bmc-rom0-wp"; +- gpios = <&pca1 0 GPIO_ACTIVE_LOW>; +- linux,code = <8>; +- }; +- +- bmc-rom1-wp { +- label = "bmc-rom1-wp"; +- gpios = <&pca1 1 GPIO_ACTIVE_LOW>; +- linux,code = <9>; +- }; +- +- fan0-presence { +- label = "fan0-presence"; +- gpios = <&pca1 2 GPIO_ACTIVE_LOW>; +- linux,code = <10>; +- }; +- +- fan1-presence { +- label = "fan1-presence"; +- gpios = <&pca1 3 GPIO_ACTIVE_LOW>; +- linux,code = <11>; +- }; +- +- fan2-presence { +- label = "fan2-presence"; +- gpios = <&pca1 4 GPIO_ACTIVE_LOW>; +- linux,code = <12>; +- }; +- +- fan3-presence { +- label = "fan3-presence"; +- gpios = <&pca1 5 GPIO_ACTIVE_LOW>; +- linux,code = <13>; +- }; +- +- fan4-presence { +- label = "fan4-presence"; +- gpios = <&pca1 6 GPIO_ACTIVE_LOW>; +- linux,code = <14>; +- }; +- +- fan5-presence { +- label = "fan5-presence"; +- gpios = <&pca1 7 GPIO_ACTIVE_LOW>; +- linux,code = <15>; +- }; +- +- front-bp1-presence { +- label = "front-bp1-presence"; +- gpios = <&pca1 8 GPIO_ACTIVE_LOW>; +- linux,code = <16>; +- }; +- +- rear-bp-presence { +- label = "rear-bp-presence"; +- gpios = <&pca1 9 GPIO_ACTIVE_LOW>; +- linux,code = <17>; +- }; +- +- fault-pvccin-cpu0 { +- label = "fault-pvccin-cpu0"; +- gpios = <&pca1 10 GPIO_ACTIVE_LOW>; +- linux,code = <18>; +- }; +- +- alrt-p1v05-pvcc { +- label = "alrt-p1v05-pvcc1"; +- gpios = <&pca1 11 GPIO_ACTIVE_LOW>; +- linux,code = <19>; +- }; +- +- fault-p1v05-pvccio { +- label = "alrt-p1v05-pvcc1"; +- gpios = <&pca1 12 GPIO_ACTIVE_LOW>; +- linux,code = <20>; +- }; +- +- alrt-p1v8-pvccio { +- label = "alrt-p1v8-pvccio"; +- gpios = <&pca1 13 GPIO_ACTIVE_LOW>; +- linux,code = <21>; +- }; +- +- fault-p1v8-pvccio { +- label = "fault-p1v8-pvccio"; +- gpios = <&pca1 14 GPIO_ACTIVE_LOW>; +- linux,code = <22>; +- }; +- +- front-bp0-presence { +- label = "front-bp0-presence"; +- gpios = <&pca1 15 GPIO_ACTIVE_LOW>; +- linux,code = <23>; +- }; +- }; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- label = "bmc"; +- m25p,fast-read; +- spi-max-frequency = <50000000>; +-#include "openbmc-flash-layout-64.dtsi" +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bios"; +- spi-max-frequency = <100000000>; +- }; +-}; +- +-&adc { +- status = "okay"; +-}; +- +-&gpio { +- status = "okay"; +- gpio-line-names = +- /*A0-A7*/ "SMRST_OCP_N","MAC2_LINK","BMC_CPLD_SMB_RST_R_N","BMC_CPLD_GPIO0", +- "","","","", +- /*B0-B7*/ "BMC_INIT_R_OK","FM_BOARD_REV_ID2","FM_PROJECT_ID7","FAULT_P12V_STBY_N", +- "","CPU0_PROCHOT_LVT3_N","","BIOS_LOAD_DEFAULT_R_N", +- /*C0-C7*/ "","","","","","","","", +- /*D0-D7*/ "","","","","","","","", +- /*E0-E7*/ "FM_PROJECT_ID0","FM_PROJECT_ID1","FM_PROJECT_ID2","FM_PROJECT_ID3", +- "FM_PROJECT_ID4","FM_PROJECT_ID5","","", +- /*F0-F7*/ "PSU0_PRSNT_N","PSU1_PRSNT_N","","FAULT_P12V_NVME_N", +- "BIOS_DEBUG_MODE_R_N","DISABLE_CPU_DDR_R_SPD","COOLING_STRATEGY", +- "PCH_GLB_RST_N", +- /*G0-G7*/ "P12V_PMBUS_ALERT_N","CPLD_ALERT_N","BMC_RELOAD_N", +- "P12V_PVDDQ_PMBUS_ALERT_N","BMC_JTAG_TCK_MUX_R_SEL","","NMI_OUT", +- "NMI_BUTTON", +- /*H0-H7*/ "BMC_CPLD_JTAG_TDI","BMC_CPLD_JTAG_TDO","BMC_CPLD_JTAG_TCK", +- "BMC_CPLD_JTAG_TMS","FM_PROJECT_ID6","FM_BOARD_REV_ID0", +- "PCA9546_U70_RST_N","IRQ_SML0_ALERT_N", +- /*I0-I7*/ "FAULT_FRONT_RISER_P12V_N","FAULT_OCP_P12V_N","FM_BMC_PCH_SCI_R_N", +- "","","","","", +- /*J0-J7*/ "FM_CPU0_SKTOCC_N","FM_CPU1_SKTOCC_N","FM_CPU1_DISABLE_COD_N", +- "","","","","", +- /*K0-K7*/ "","","","","","","","", +- /*L0-L7*/ "P12V_FAULT_N","PWRGD_P12V_PCIE_RISER","","LEAKAGE_DETECT_INPUT_N", +- "","IRQ_SML1_PMBUS_ALERT_N","","", +- /*M0-M7*/ "","","","","","","","", +- /*N0-N7*/ "","","","","","","","", +- /*O0-O7*/ "","","","","","","","", +- /*P0-P7*/ "","","","","","","","", +- /*Q0-Q7*/ "","","","","","","FM_PCH_THERMTRIP_N","CHASSIS_INTRUSION", +- /*R0-R7*/ "","PVCCIN_CPU1_SMBALERT_N","BMC_PREQ_R_N","FAULT_P12V_PCIE_RISER_N", +- "ALT_P12V_PCIE_RISER_N","BURN_BOARD_N","PVCCIN_CPU0_SMBALERT_N","", +- /*S0-S7*/ "BMC_PRDY_N","SIO_POWER_GOOD","FM_BMC_PWR_DEBUG_R_N", +- "FM_BMC_XDP_DEBUG_EN","","STRAP_BMC_BATTERY_GPIOS5","","", +- /*T0-T7*/ "","","","","","","","", +- /*U0-U7*/ "","","","","","","","", +- /*V0-V7*/ "","","","","","","","", +- /*W0-W7*/ "","","","","","","","", +- /*X0-X7*/ "","","","","","","","", +- /*Y0-Y7*/ "","PWRGD_PSU0_PWROK","CPU1_PROCHOT_LVT3_N","IRQ_BMC_PCH_SMI_LPC_N", +- "","","","", +- /*Z0-Z7*/ "XDP_PRSNT_N","BMC_XDP_SYS_PWROK","BMC_XDP_JTAG_SEL", +- "PCH_BMC_SMI_ACTIVE_R_N","","","","", +- /*AA0-AA7*/ "PWRGD_P12V_STBY_OCP","PS_PWROK","RST_PLTRST_BMC_R_N","HDA_SDO_R", +- "FM_SLPS4_R_N","PWRGD_PSU1_PWROK","POWER_BUTTON","POWER_OUT", +- /*AB0-AB7*/ "","RESET_OUT","SPI_BIOS_MODE_SELECT","POST_COMPLETE","","","","", +- /*AC0-AC7*/ "","","","","","","","CPLD_PLTRST_B_N"; +-}; +- +-&kcs3 { +- aspeed,lpc-io-reg = <0xCA2>; +- status = "okay"; +-}; +- +-&kcs4 { +- aspeed,lpc-io-reg = <0xCA4>; +- status = "okay"; +-}; +- +-&lpc_snoop { +- snoop-ports = <0x80>; +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default +- &pinctrl_nrts1_default +- &pinctrl_ndtr1_default +- &pinctrl_ndsr1_default +- &pinctrl_ncts1_default +- &pinctrl_ndcd1_default +- &pinctrl_nri1_default>; +-}; +- +-&uart2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd2_default +- &pinctrl_rxd2_default +- &pinctrl_nrts2_default +- &pinctrl_ndtr2_default +- &pinctrl_ndsr2_default +- &pinctrl_ncts2_default +- &pinctrl_ndcd2_default +- &pinctrl_nri2_default>; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&uart4 { +- status = "okay"; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&mac1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +- i2c-switch@70 { +- compatible = "nxp,pca9546"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel_3_0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- channel_3_1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- channel_3_2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- channel_3_3: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +-}; +- +-&i2c4 { +- status = "okay"; +- ipmb0@10 { +- compatible = "ipmb-dev"; +- reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; +- i2c-protocol; +- }; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- status = "okay"; +- i2c-switch@72 { +- compatible = "nxp,pca9548"; +- reg = <0x72>; +- #address-cells = <1>; +- #size-cells = <0>; +- channel_6_0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- channel_6_1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- channel_6_2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- channel_6_3: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- channel_6_4: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- channel_6_5: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- channel_6_6: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- channel_6_7: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- i2c-switch@70 { +- compatible = "nxp,pca9546"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- channel_6_8: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- i2c-switch@71 { +- compatible = "nxp,pca9546"; +- reg = <0x71>; +- #address-cells = <1>; +- #size-cells = <0>; +- channel_6_12: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- }; +- +- channel_6_13: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- channel_6_14: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- channel_6_15: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +- }; +- +- channel_6_9: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- i2c-switch@71 { +- compatible = "nxp,pca9546"; +- reg = <0x71>; +- #address-cells = <1>; +- #size-cells = <0>; +- channel_6_16: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- }; +- +- channel_6_17: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- channel_6_18: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- channel_6_19: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +- }; +- +- channel_6_10: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- i2c-switch@71 { +- compatible = "nxp,pca9546"; +- reg = <0x71>; +- #address-cells = <1>; +- #size-cells = <0>; +- channel_6_20: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- channel_6_21: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- channel_6_22: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- channel_6_23: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +- }; +- +- channel_6_11: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- i2c-switch@71 { +- compatible = "nxp,pca9546"; +- reg = <0x71>; +- #address-cells = <1>; +- #size-cells = <0>; +- channel_6_24: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- channel_6_25: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- }; +- }; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&i2c8 { +- status = "okay"; +- pca0:pca9555@24 { +- compatible = "nxp,pca9555"; +- reg = <0x24>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@8 { +- reg = <8>; +- type = ; +- }; +- +- gpio@9 { +- reg = <9>; +- type = ; +- }; +- +- gpio@10 { +- reg = <10>; +- type = ; +- }; +- +- gpio@11 { +- reg = <11>; +- type = ; +- }; +- +- gpio@12 { +- reg = <12>; +- type = ; +- }; +- +- gpio@13 { +- reg = <13>; +- type = ; +- }; +- }; +- +- pca1:pca9555@25 { +- compatible = "nxp,pca9555"; +- reg = <0x25>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- gpio@8 { +- reg = <8>; +- type = ; +- }; +- +- gpio@9 { +- reg = <9>; +- type = ; +- }; +- +- gpio@10 { +- reg = <10>; +- type = ; +- }; +- +- gpio@11 { +- reg = <11>; +- type = ; +- }; +- +- gpio@12 { +- reg = <12>; +- type = ; +- }; +- +- gpio@13 { +- reg = <13>; +- type = ; +- }; +- +- gpio@14 { +- reg = <14>; +- type = ; +- }; +- +- gpio@15 { +- reg = <15>; +- type = ; +- }; +- }; +-}; +- +-&i2c9 { +- status = "okay"; +-}; +- +-&i2c10 { +- status = "okay"; +- i2c-switch@70 { +- compatible = "nxp,pca9546"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- channel_10_0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- channel_10_1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- channel_10_2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- channel_10_3: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +- +- i2c-switch@71 { +- compatible = "nxp,pca9546"; +- reg = <0x71>; +- #address-cells = <1>; +- #size-cells = <0>; +- channel_10_4: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- channel_10_5: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- channel_10_6: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- channel_10_7: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +-}; +- +-&i2c11 { +- status = "okay"; +-}; +- +-&i2c12 { +- status = "okay"; +-}; +- +-&i2c13 { +- status = "okay"; +-}; +- +-&pwm_tacho { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default +- &pinctrl_pwm2_default &pinctrl_pwm3_default +- &pinctrl_pwm4_default &pinctrl_pwm5_default>; +- +- fan@0 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; +- }; +- fan@1 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; +- }; +- fan@2 { +- reg = <0x02>; +- aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>; +- }; +- fan@3 { +- reg = <0x03>; +- aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>; +- }; +- fan@4 { +- reg = <0x04>; +- aspeed,fan-tach-ch = /bits/ 8 <0x08 0x09>; +- }; +- fan@5 { +- reg = <0x05>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0a 0x0b>; +- }; +-}; +- +-&gpio { +- pin_gpio_i3 { +- gpio-hog; +- gpios = ; +- output-low; +- line-name = "NCSI_BMC_R_SEL"; +- }; +- +- pin_gpio_b6 { +- gpio-hog; +- gpios = ; +- output-low; +- line-name = "EN_NCSI_SWITCH_N"; +- }; +-}; +- +-&video { +- status = "okay"; +- memory-region = <&video_engine_memory>; +-}; +- +-&vhub { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-cloudripper.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-cloudripper.dts +deleted file mode 100644 +index 9c6271a17ae8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-cloudripper.dts ++++ /dev/null +@@ -1,544 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright (c) 2020 Facebook Inc. +- +-/dts-v1/; +- +-#include +-#include "ast2600-facebook-netbmc-common.dtsi" +- +-/ { +- model = "Facebook Cloudripper BMC"; +- compatible = "facebook,cloudripper-bmc", "aspeed,ast2600"; +- +- aliases { +- /* +- * PCA9548 (1-0070) provides 8 channels connecting to +- * SMB (Switch Main Board). +- */ +- i2c16 = &imux16; +- i2c17 = &imux17; +- i2c18 = &imux18; +- i2c19 = &imux19; +- i2c20 = &imux20; +- i2c21 = &imux21; +- i2c22 = &imux22; +- i2c23 = &imux23; +- +- /* +- * PCA9548 (2-0070) provides 8 channels connecting to +- * SCM (System Controller Module). +- */ +- i2c24 = &imux24; +- i2c25 = &imux25; +- i2c26 = &imux26; +- i2c27 = &imux27; +- i2c28 = &imux28; +- i2c29 = &imux29; +- i2c30 = &imux30; +- i2c31 = &imux31; +- +- /* +- * PCA9548 (3-0070) provides 8 channels connecting to +- * SMB (Switch Main Board). +- */ +- i2c32 = &imux32; +- i2c33 = &imux33; +- i2c34 = &imux34; +- i2c35 = &imux35; +- i2c36 = &imux36; +- i2c37 = &imux37; +- i2c38 = &imux38; +- i2c39 = &imux39; +- +- /* +- * PCA9548 (8-0070) provides 8 channels connecting to +- * PDB (Power Delivery Board). +- */ +- i2c40 = &imux40; +- i2c41 = &imux41; +- i2c42 = &imux42; +- i2c43 = &imux43; +- i2c44 = &imux44; +- i2c45 = &imux45; +- i2c46 = &imux46; +- i2c47 = &imux47; +- +- /* +- * PCA9548 (15-0076) provides 8 channels connecting to +- * FCM (Fan Controller Module). +- */ +- i2c48 = &imux48; +- i2c49 = &imux49; +- i2c50 = &imux50; +- i2c51 = &imux51; +- i2c52 = &imux52; +- i2c53 = &imux53; +- i2c54 = &imux54; +- i2c55 = &imux55; +- }; +- +- spi_gpio: spi-gpio { +- num-chipselects = <2>; +- cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>, +- <&gpio0 ASPEED_GPIO(X, 1) GPIO_ACTIVE_HIGH>; +- +- eeprom@1 { +- compatible = "atmel,at93c46d"; +- spi-max-frequency = <250000>; +- data-size = <16>; +- spi-cs-high; +- reg = <1>; +- }; +- }; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-/* +- * "mdio1" is connected to the MDC/MDIO interface of the on-board +- * management switch (whose ports are connected to BMC, Host and front +- * panel ethernet port). +- */ +-&mdio1 { +- status = "okay"; +-}; +- +-&mdio3 { +- status = "okay"; +- +- ethphy1: ethernet-phy@13 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0x0d>; +- }; +-}; +- +-&mac3 { +- status = "okay"; +- phy-mode = "rgmii"; +- phy-handle = <ðphy1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii4_default>; +-}; +- +-&i2c0 { +- multi-master; +- bus-frequency = <1000000>; +-}; +- +-&i2c1 { +- /* +- * PCA9548 (1-0070) provides 8 channels connecting to SMB (Switch +- * Main Board). +- */ +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux16: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux17: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux18: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux19: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux20: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux21: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux22: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux23: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +-}; +- +-&i2c2 { +- /* +- * PCA9548 (2-0070) provides 8 channels connecting to SCM (System +- * Controller Module). +- */ +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux24: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux25: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux26: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux27: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux28: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux29: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux30: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux31: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +-}; +- +-&i2c3 { +- /* +- * PCA9548 (3-0070) provides 8 channels connecting to SMB (Switch +- * Main Board). +- */ +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux32: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux33: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux34: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux35: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux36: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux37: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux38: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux39: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +-}; +- +-&i2c6 { +- lp5012@14 { +- compatible = "ti,lp5012"; +- reg = <0x14>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- multi-led@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- color = ; +- function = LED_FUNCTION_ACTIVITY; +- label = "sys"; +- +- led@0 { +- reg = <0>; +- color = ; +- }; +- +- led@1 { +- reg = <1>; +- color = ; +- }; +- +- led@2 { +- reg = <2>; +- color = ; +- }; +- }; +- +- multi-led@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- color = ; +- function = LED_FUNCTION_ACTIVITY; +- label = "fan"; +- +- led@0 { +- reg = <0>; +- color = ; +- }; +- +- led@1 { +- reg = <1>; +- color = ; +- }; +- +- led@2 { +- reg = <2>; +- color = ; +- }; +- }; +- +- multi-led@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- color = ; +- function = LED_FUNCTION_ACTIVITY; +- label = "psu"; +- +- led@0 { +- reg = <0>; +- color = ; +- }; +- +- led@1 { +- reg = <1>; +- color = ; +- }; +- +- led@2 { +- reg = <2>; +- color = ; +- }; +- }; +- +- multi-led@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- color = ; +- function = LED_FUNCTION_ACTIVITY; +- label = "scm"; +- +- led@0 { +- reg = <0>; +- color = ; +- }; +- +- led@1 { +- reg = <1>; +- color = ; +- }; +- +- led@2 { +- reg = <2>; +- color = ; +- }; +- }; +- }; +-}; +- +-&i2c8 { +- /* +- * PCA9548 (8-0070) provides 8 channels connecting to PDB (Power +- * Delivery Board). +- */ +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux40: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux41: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux42: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux43: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux44: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux45: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux46: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux47: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- +- }; +-}; +- +-&i2c15 { +- /* +- * PCA9548 (15-0076) provides 8 channels connecting to FCM (Fan +- * Controller Module). +- */ +- i2c-switch@76 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x76>; +- i2c-mux-idle-disconnect; +- +- imux48: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux49: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux50: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux51: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux52: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux53: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux54: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux55: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-cmm.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-cmm.dts +deleted file mode 100644 +index 90a3f485c67a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-cmm.dts ++++ /dev/null +@@ -1,1590 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright (c) 2018 Facebook Inc. +-/dts-v1/; +- +-#include "ast2500-facebook-netbmc-common.dtsi" +- +-/ { +- model = "Facebook Backpack CMM BMC"; +- compatible = "facebook,cmm-bmc", "aspeed,ast2500"; +- +- aliases { +- /* +- * Override the default uart aliases to avoid breaking +- * the legacy applications. +- */ +- serial0 = &uart5; +- serial1 = &uart1; +- serial2 = &uart3; +- serial3 = &uart4; +- +- /* +- * PCA9548 (1-0077) provides 8 channels for connecting to +- * 4 Line Cards and 4 Fabric Cards. +- */ +- i2c16 = &imux16; +- i2c17 = &imux17; +- i2c18 = &imux18; +- i2c19 = &imux19; +- i2c20 = &imux20; +- i2c21 = &imux21; +- i2c22 = &imux22; +- i2c23 = &imux23; +- +- /* +- * PCA9548 (2-0071) provides 8 channels for connecting to +- * Power Distribution Board. +- */ +- i2c24 = &imux24; +- i2c25 = &imux25; +- i2c26 = &imux26; +- i2c27 = &imux27; +- i2c28 = &imux28; +- i2c29 = &imux29; +- i2c30 = &imux30; +- i2c31 = &imux31; +- +- /* +- * PCA9548 (8-0077) provides 8 channels and the first 4 +- * channels are connecting to 4 Fan Control Boards. +- */ +- i2c32 = &imux32; +- i2c33 = &imux33; +- i2c34 = &imux34; +- i2c35 = &imux35; +- i2c36 = &imux36; +- i2c37 = &imux37; +- i2c38 = &imux38; +- i2c39 = &imux39; +- +- /* +- * 2 PCA9548 (18-0070 & 18-0073), 16 channels connecting +- * to Line Card #1. +- */ +- i2c40 = &imux40; +- i2c41 = &imux41; +- i2c42 = &imux42; +- i2c43 = &imux43; +- i2c44 = &imux44; +- i2c45 = &imux45; +- i2c46 = &imux46; +- i2c47 = &imux47; +- i2c48 = &imux48; +- i2c49 = &imux49; +- i2c50 = &imux50; +- i2c51 = &imux51; +- i2c52 = &imux52; +- i2c53 = &imux53; +- i2c54 = &imux54; +- i2c55 = &imux55; +- +- /* +- * 2 PCA9548 (19-0070 & 19-0073), 16 channels connecting +- * to Line Card #2. +- */ +- i2c56 = &imux56; +- i2c57 = &imux57; +- i2c58 = &imux58; +- i2c59 = &imux59; +- i2c60 = &imux60; +- i2c61 = &imux61; +- i2c62 = &imux62; +- i2c63 = &imux63; +- i2c64 = &imux64; +- i2c65 = &imux65; +- i2c66 = &imux66; +- i2c67 = &imux67; +- i2c68 = &imux68; +- i2c69 = &imux69; +- i2c70 = &imux70; +- i2c71 = &imux71; +- +- /* +- * 2 PCA9548 (20-0070 & 20-0073), 16 channels connecting +- * to Line Card #3. +- */ +- i2c72 = &imux72; +- i2c73 = &imux73; +- i2c74 = &imux74; +- i2c75 = &imux75; +- i2c76 = &imux76; +- i2c77 = &imux77; +- i2c78 = &imux78; +- i2c79 = &imux79; +- i2c80 = &imux80; +- i2c81 = &imux81; +- i2c82 = &imux82; +- i2c83 = &imux83; +- i2c84 = &imux84; +- i2c85 = &imux85; +- i2c86 = &imux86; +- i2c87 = &imux87; +- +- /* +- * 2 PCA9548 (21-0070 & 21-0073), 16 channels connecting +- * to Line Card #4. +- */ +- i2c88 = &imux88; +- i2c89 = &imux89; +- i2c90 = &imux90; +- i2c91 = &imux91; +- i2c92 = &imux92; +- i2c93 = &imux93; +- i2c94 = &imux94; +- i2c95 = &imux95; +- i2c96 = &imux96; +- i2c97 = &imux97; +- i2c98 = &imux98; +- i2c99 = &imux99; +- i2c100 = &imux100; +- i2c101 = &imux101; +- i2c102 = &imux102; +- i2c103 = &imux103; +- +- /* +- * 2 PCA9548 (16-0070 & 16-0073), 16 channels connecting +- * to Fabric Card #1. +- */ +- i2c104 = &imux104; +- i2c105 = &imux105; +- i2c106 = &imux106; +- i2c107 = &imux107; +- i2c108 = &imux108; +- i2c109 = &imux109; +- i2c110 = &imux110; +- i2c111 = &imux111; +- i2c112 = &imux112; +- i2c113 = &imux113; +- i2c114 = &imux114; +- i2c115 = &imux115; +- i2c116 = &imux116; +- i2c117 = &imux117; +- i2c118 = &imux118; +- i2c119 = &imux119; +- +- /* +- * 2 PCA9548 (17-0070 & 17-0073), 16 channels connecting +- * to Fabric Card #2. +- */ +- i2c120 = &imux120; +- i2c121 = &imux121; +- i2c122 = &imux122; +- i2c123 = &imux123; +- i2c124 = &imux124; +- i2c125 = &imux125; +- i2c126 = &imux126; +- i2c127 = &imux127; +- i2c128 = &imux128; +- i2c129 = &imux129; +- i2c130 = &imux130; +- i2c131 = &imux131; +- i2c132 = &imux132; +- i2c133 = &imux133; +- i2c134 = &imux134; +- i2c135 = &imux135; +- +- /* +- * 2 PCA9548 (22-0070 & 22-0073), 16 channels connecting +- * to Fabric Card #3. +- */ +- i2c136 = &imux136; +- i2c137 = &imux137; +- i2c138 = &imux138; +- i2c139 = &imux139; +- i2c140 = &imux140; +- i2c141 = &imux141; +- i2c142 = &imux142; +- i2c143 = &imux143; +- i2c144 = &imux144; +- i2c145 = &imux145; +- i2c146 = &imux146; +- i2c147 = &imux147; +- i2c148 = &imux148; +- i2c149 = &imux149; +- i2c150 = &imux150; +- i2c151 = &imux151; +- +- /* +- * 2 PCA9548 (23-0070 & 23-0073), 16 channels connecting +- * to Fabric Card #4. +- */ +- i2c152 = &imux152; +- i2c153 = &imux153; +- i2c154 = &imux154; +- i2c155 = &imux155; +- i2c156 = &imux156; +- i2c157 = &imux157; +- i2c158 = &imux158; +- i2c159 = &imux159; +- i2c160 = &imux160; +- i2c161 = &imux161; +- i2c162 = &imux162; +- i2c163 = &imux163; +- i2c164 = &imux164; +- i2c165 = &imux165; +- i2c166 = &imux166; +- i2c167 = &imux167; +- +- /* +- * PCA9548 (32-0070), 8 channels connecting to Fan Control +- # Board #1. +- */ +- i2c168 = &imux168; +- i2c169 = &imux169; +- i2c170 = &imux170; +- i2c171 = &imux171; +- i2c172 = &imux172; +- i2c173 = &imux173; +- i2c174 = &imux174; +- i2c175 = &imux175; +- +- /* +- * PCA9548 (33-0070), 8 channels connecting to Fan Control +- # Board #2. +- */ +- i2c176 = &imux176; +- i2c177 = &imux177; +- i2c178 = &imux178; +- i2c179 = &imux179; +- i2c180 = &imux180; +- i2c181 = &imux181; +- i2c182 = &imux182; +- i2c183 = &imux183; +- +- /* +- * PCA9548 (34-0070), 8 channels connecting to Fan Control +- # Board #3. +- */ +- i2c184 = &imux184; +- i2c185 = &imux185; +- i2c186 = &imux186; +- i2c187 = &imux187; +- i2c188 = &imux188; +- i2c189 = &imux189; +- i2c190 = &imux190; +- i2c191 = &imux191; +- +- /* +- * PCA9548 (35-0070), 8 channels connecting to Fan Control +- # Board #4. +- */ +- i2c192 = &imux192; +- i2c193 = &imux193; +- i2c194 = &imux194; +- i2c195 = &imux195; +- i2c196 = &imux196; +- i2c197 = &imux197; +- i2c198 = &imux198; +- i2c199 = &imux199; +- }; +- +- chosen { +- stdout-path = &uart1; +- bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlycon"; +- }; +- +- ast-adc-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, +- <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; +- }; +-}; +- +-&uart1 { +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default +- &pinctrl_ncts1_default +- &pinctrl_ndcd1_default +- &pinctrl_ndsr1_default +- &pinctrl_ndtr1_default +- &pinctrl_nrts1_default>; +-}; +- +-&uart3 { +- pinctrl-0 = <&pinctrl_txd3_default +- &pinctrl_rxd3_default +- &pinctrl_ncts3_default +- &pinctrl_ndcd3_default +- &pinctrl_nri3_default>; +-}; +- +-&uart4 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd4_default +- &pinctrl_rxd4_default>; +-}; +- +-/* +- * I2C bus reserved for communication with COM-E. +- */ +-&i2c0 { +- status = "okay"; +-}; +- +-/* +- * I2C bus to Line Cards and Fabric Cards. +- */ +-&i2c1 { +- status = "okay"; +- +- i2c-switch@77 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x77>; +- i2c-mux-idle-disconnect; +- +- /* To Fabric Card #1 */ +- imux16: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux104: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux105: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux106: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux107: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux108: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux109: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux110: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux111: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- i2c-switch@73 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- i2c-mux-idle-disconnect; +- +- imux112: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux113: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux114: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux115: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux116: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux117: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux118: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux119: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* To Fabric Card #2 */ +- imux17: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux120: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux121: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux122: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux123: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux124: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux125: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux126: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux127: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- i2c-switch@73 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- i2c-mux-idle-disconnect; +- +- imux128: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux129: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux130: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux131: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux132: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux133: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux134: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux135: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* To Line Card #1 */ +- imux18: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux40: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux41: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux42: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux43: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux44: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux45: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux46: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux47: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- i2c-switch@73 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- i2c-mux-idle-disconnect; +- +- imux48: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux49: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux50: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux51: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux52: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux53: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux54: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux55: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* To Line Card #2 */ +- imux19: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux56: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux57: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux58: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux59: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux60: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux61: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux62: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux63: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- i2c-switch@73 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- i2c-mux-idle-disconnect; +- +- imux64: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux65: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux66: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux67: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux68: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux69: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux70: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux71: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* To LC3 SCM */ +- imux20: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux72: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux73: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux74: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux75: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux76: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux77: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux78: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux79: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- i2c-switch@73 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- i2c-mux-idle-disconnect; +- +- imux80: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux81: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux82: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux83: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux84: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux85: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux86: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux87: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* To Line Card #4 */ +- imux21: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux88: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux89: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux90: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux91: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux92: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux93: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux94: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux95: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- i2c-switch@73 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- i2c-mux-idle-disconnect; +- +- imux96: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux97: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux98: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux99: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux100: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux101: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux102: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux103: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* To Fabric Card #3 */ +- imux22: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux136: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux137: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux138: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux139: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux140: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux141: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux142: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux143: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- i2c-switch@73 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- i2c-mux-idle-disconnect; +- +- imux144: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux145: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux146: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux147: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux148: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux149: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux150: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux151: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* To Fabric Card #4 */ +- imux23: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux152: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux153: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux154: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux155: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux156: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux157: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux158: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux159: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- i2c-switch@73 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- i2c-mux-idle-disconnect; +- +- imux160: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux161: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux162: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux163: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux164: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux165: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux166: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux167: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- }; +-}; +- +-/* +- * I2C bus to Power Distribution Board. +- */ +-&i2c2 { +- status = "okay"; +- +- i2c-switch@71 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x71>; +- i2c-mux-idle-disconnect; +- +- imux24: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux25: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux26: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux27: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux28: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux29: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux30: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux31: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +-}; +- +-/* +- * I2c bus connected with temperature sensors on CMM. +- */ +-&i2c3 { +- status = "okay"; +-}; +- +-/* +- * I2C bus reserved for communication with COM-E. +- */ +-&i2c4 { +- status = "okay"; +-}; +- +-/* +- * I2c bus connected with ADM1278. +- */ +-&i2c5 { +- status = "okay"; +-}; +- +-/* +- * I2c bus connected with I/O Expander. +- */ +-&i2c6 { +- status = "okay"; +-}; +- +-/* +- * I2c bus connected with I/O Expander and EPROMs. +- */ +-&i2c7 { +- status = "okay"; +-}; +- +-/* +- * I2C bus to Fan Control Boards. +- */ +-&i2c8 { +- status = "okay"; +- +- i2c-switch@77 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x77>; +- i2c-mux-idle-disconnect; +- +- /* To Fan Control Board #1 */ +- imux32: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux168: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux169: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux170: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux171: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux172: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux173: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux174: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux175: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* To Fan Control Board #2 */ +- imux33: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux176: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux177: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux178: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux179: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux180: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux181: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux182: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux183: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* To Fan Control Board #3 */ +- imux34: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux184: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux185: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux186: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux187: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux188: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux189: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux190: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux191: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* To Fan Control Board #4 */ +- imux35: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux192: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- imux193: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- imux194: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- imux195: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- imux196: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- imux197: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- imux198: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- imux199: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- imux36: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux37: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux38: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux39: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +-}; +- +-/* +- * I2C bus to CMM CPLD. +- */ +-&i2c13 { +- status = "okay"; +-}; +- +-&adc { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&vhub { +- status = "disabled"; +-}; +- +-&sdhci0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sd1_default>; +-}; +- +-&sdhci1 { +- status = "disabled"; +-}; +- +-&fmc_flash0 { +-#include "facebook-bmc-flash-layout.dtsi" +-}; +- +-&fmc_flash1 { +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- flash1@0 { +- reg = <0x0 0x2000000>; +- label = "flash1"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-elbert.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-elbert.dts +deleted file mode 100644 +index 27b43fe099f1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-elbert.dts ++++ /dev/null +@@ -1,185 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright (c) 2020 Facebook Inc. +- +-/dts-v1/; +- +-#include "ast2600-facebook-netbmc-common.dtsi" +- +-/ { +- model = "Facebook Elbert BMC"; +- compatible = "facebook,elbert-bmc", "aspeed,ast2600"; +- +- aliases { +- serial0 = &uart5; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- +- /* +- * 8 child channels of PCA9548 2-0075. +- */ +- i2c16 = &imux16; +- i2c17 = &imux17; +- i2c18 = &imux18; +- i2c19 = &imux19; +- i2c20 = &imux20; +- i2c21 = &imux21; +- i2c22 = &imux22; +- i2c23 = &imux23; +- +- /* +- * 8 child channels of PCA9548 5-0075. +- */ +- i2c24 = &imux24; +- i2c25 = &imux25; +- i2c26 = &imux26; +- i2c27 = &imux27; +- i2c28 = &imux28; +- i2c29 = &imux29; +- i2c30 = &imux30; +- i2c31 = &imux31; +- }; +- +- chosen { +- stdout-path = &uart5; +- }; +- +- spi_gpio: spi-gpio { +- num-chipselects = <1>; +- cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&lpc_ctrl { +- status = "okay"; +-}; +- +-&kcs2 { +- status = "okay"; +- aspeed,lpc-io-reg = <0xca8>; +-}; +- +-&kcs3 { +- status = "okay"; +- aspeed,lpc-io-reg = <0xca2>; +-}; +- +-&i2c2 { +- i2c-switch@75 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x75>; +- i2c-mux-idle-disconnect; +- +- imux16: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux17: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux18: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux19: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux20: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux21: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux22: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux23: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +-}; +- +-&i2c5 { +- i2c-switch@75 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x75>; +- i2c-mux-idle-disconnect; +- +- imux24: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux25: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux26: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux27: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux28: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux29: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux30: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux31: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +-}; +- +-&i2c11 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-fuji.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-fuji.dts +deleted file mode 100644 +index af58a73bbc49..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-fuji.dts ++++ /dev/null +@@ -1,1251 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright (c) 2020 Facebook Inc. +- +-/dts-v1/; +- +-#include +-#include "ast2600-facebook-netbmc-common.dtsi" +- +-/ { +- model = "Facebook Fuji BMC"; +- compatible = "facebook,fuji-bmc", "aspeed,ast2600"; +- +- aliases { +- /* +- * PCA9548 (2-0070) provides 8 channels connecting to +- * SCM (System Controller Module). +- */ +- i2c16 = &imux16; +- i2c17 = &imux17; +- i2c18 = &imux18; +- i2c19 = &imux19; +- i2c20 = &imux20; +- i2c21 = &imux21; +- i2c22 = &imux22; +- i2c23 = &imux23; +- +- /* +- * PCA9548 (8-0070) provides 8 channels connecting to +- * SMB (Switch Main Board). +- */ +- i2c24 = &imux24; +- i2c25 = &imux25; +- i2c26 = &imux26; +- i2c27 = &imux27; +- i2c28 = &imux28; +- i2c29 = &imux29; +- i2c30 = &imux30; +- i2c31 = &imux31; +- +- /* +- * PCA9548 (11-0077) provides 8 channels connecting to +- * SMB (Switch Main Board). +- */ +- i2c40 = &imux40; +- i2c41 = &imux41; +- i2c42 = &imux42; +- i2c43 = &imux43; +- i2c44 = &imux44; +- i2c45 = &imux45; +- i2c46 = &imux46; +- i2c47 = &imux47; +- +- /* +- * PCA9548 (24-0071) provides 8 channels connecting to +- * PDB-Left. +- */ +- i2c48 = &imux48; +- i2c49 = &imux49; +- i2c50 = &imux50; +- i2c51 = &imux51; +- i2c52 = &imux52; +- i2c53 = &imux53; +- i2c54 = &imux54; +- i2c55 = &imux55; +- +- /* +- * PCA9548 (25-0072) provides 8 channels connecting to +- * PDB-Right. +- */ +- i2c56 = &imux56; +- i2c57 = &imux57; +- i2c58 = &imux58; +- i2c59 = &imux59; +- i2c60 = &imux60; +- i2c61 = &imux61; +- i2c62 = &imux62; +- i2c63 = &imux63; +- +- /* +- * PCA9548 (26-0076) provides 8 channels connecting to +- * FCM1. +- */ +- i2c64 = &imux64; +- i2c65 = &imux65; +- i2c66 = &imux66; +- i2c67 = &imux67; +- i2c68 = &imux68; +- i2c69 = &imux69; +- i2c70 = &imux70; +- i2c71 = &imux71; +- +- /* +- * PCA9548 (27-0076) provides 8 channels connecting to +- * FCM2. +- */ +- i2c72 = &imux72; +- i2c73 = &imux73; +- i2c74 = &imux74; +- i2c75 = &imux75; +- i2c76 = &imux76; +- i2c77 = &imux77; +- i2c78 = &imux78; +- i2c79 = &imux79; +- +- /* +- * PCA9548 (40-0076) provides 8 channels connecting to +- * PIM1. +- */ +- i2c80 = &imux80; +- i2c81 = &imux81; +- i2c82 = &imux82; +- i2c83 = &imux83; +- i2c84 = &imux84; +- i2c85 = &imux85; +- i2c86 = &imux86; +- i2c87 = &imux87; +- +- /* +- * PCA9548 (41-0076) provides 8 channels connecting to +- * PIM2. +- */ +- i2c88 = &imux88; +- i2c89 = &imux89; +- i2c90 = &imux90; +- i2c91 = &imux91; +- i2c92 = &imux92; +- i2c93 = &imux93; +- i2c94 = &imux94; +- i2c95 = &imux95; +- +- /* +- * PCA9548 (42-0076) provides 8 channels connecting to +- * PIM3. +- */ +- i2c96 = &imux96; +- i2c97 = &imux97; +- i2c98 = &imux98; +- i2c99 = &imux99; +- i2c100 = &imux100; +- i2c101 = &imux101; +- i2c102 = &imux102; +- i2c103 = &imux103; +- +- /* +- * PCA9548 (43-0076) provides 8 channels connecting to +- * PIM4. +- */ +- i2c104 = &imux104; +- i2c105 = &imux105; +- i2c106 = &imux106; +- i2c107 = &imux107; +- i2c108 = &imux108; +- i2c109 = &imux109; +- i2c110 = &imux110; +- i2c111 = &imux111; +- +- /* +- * PCA9548 (44-0076) provides 8 channels connecting to +- * PIM5. +- */ +- i2c112 = &imux112; +- i2c113 = &imux113; +- i2c114 = &imux114; +- i2c115 = &imux115; +- i2c116 = &imux116; +- i2c117 = &imux117; +- i2c118 = &imux118; +- i2c119 = &imux119; +- +- /* +- * PCA9548 (45-0076) provides 8 channels connecting to +- * PIM6. +- */ +- i2c120 = &imux120; +- i2c121 = &imux121; +- i2c122 = &imux122; +- i2c123 = &imux123; +- i2c124 = &imux124; +- i2c125 = &imux125; +- i2c126 = &imux126; +- i2c127 = &imux127; +- +- /* +- * PCA9548 (46-0076) provides 8 channels connecting to +- * PIM7. +- */ +- i2c128 = &imux128; +- i2c129 = &imux129; +- i2c130 = &imux130; +- i2c131 = &imux131; +- i2c132 = &imux132; +- i2c133 = &imux133; +- i2c134 = &imux134; +- i2c135 = &imux135; +- +- /* +- * PCA9548 (47-0076) provides 8 channels connecting to +- * PIM8. +- */ +- i2c136 = &imux136; +- i2c137 = &imux137; +- i2c138 = &imux138; +- i2c139 = &imux139; +- i2c140 = &imux140; +- i2c141 = &imux141; +- i2c142 = &imux142; +- i2c143 = &imux143; +- }; +- +- spi_gpio: spi-gpio { +- num-chipselects = <3>; +- cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>, +- <0>, /* device reg=<1> does not exist */ +- <&gpio0 ASPEED_GPIO(X, 2) GPIO_ACTIVE_HIGH>; +- +- eeprom@2 { +- compatible = "atmel,at93c46d"; +- spi-max-frequency = <250000>; +- data-size = <16>; +- spi-cs-high; +- reg = <2>; +- }; +- }; +-}; +- +-&i2c0 { +- multi-master; +- bus-frequency = <1000000>; +-}; +- +-&i2c2 { +- /* +- * PCA9548 (2-0070) provides 8 channels connecting to SCM (System +- * Controller Module). +- */ +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux16: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- adm1278@10 { +- compatible = "adi,adm1278"; +- reg = <0x10>; +- #address-cells = <1>; +- #size-cells = <0>; +- shunt-resistor-micro-ohms = <1500>; +- }; +- }; +- +- imux17: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux18: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux19: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux20: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux21: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux22: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux23: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +-}; +- +-&i2c8 { +- /* +- * PCA9548 (8-0070) provides 8 channels connecting to SMB (Switch +- * Main Board). +- */ +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux24: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- i2c-switch@71 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x71>; +- i2c-mux-idle-disconnect; +- +- imux48: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux49: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux50: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- lp5012@14 { +- compatible = "ti,lp5012"; +- reg = <0x14>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- multi-led@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- color = ; +- function = LED_FUNCTION_ACTIVITY; +- label = "sys"; +- +- led@0 { +- reg = <0>; +- color = ; +- }; +- +- led@1 { +- reg = <1>; +- color = ; +- }; +- +- led@2 { +- reg = <2>; +- color = ; +- }; +- }; +- +- multi-led@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- color = ; +- function = LED_FUNCTION_ACTIVITY; +- label = "fan"; +- +- led@0 { +- reg = <0>; +- color = ; +- }; +- +- led@1 { +- reg = <1>; +- color = ; +- }; +- +- led@2 { +- reg = <2>; +- color = ; +- }; +- }; +- +- multi-led@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- color = ; +- function = LED_FUNCTION_ACTIVITY; +- label = "psu"; +- +- led@0 { +- reg = <0>; +- color = ; +- }; +- +- led@1 { +- reg = <1>; +- color = ; +- }; +- +- led@2 { +- reg = <2>; +- color = ; +- }; +- }; +- +- multi-led@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- color = ; +- function = LED_FUNCTION_ACTIVITY; +- label = "smb"; +- +- led@0 { +- reg = <0>; +- color = ; +- }; +- +- led@1 { +- reg = <1>; +- color = ; +- }; +- +- led@2 { +- reg = <2>; +- color = ; +- }; +- }; +- }; +- }; +- +- imux51: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux52: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux53: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux54: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux55: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- }; +- +- imux25: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- i2c-switch@72 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x72>; +- i2c-mux-idle-disconnect; +- +- imux56: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux57: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux58: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux59: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux60: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux61: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux62: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux63: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- }; +- +- imux26: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- i2c-switch@76 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x76>; +- i2c-mux-idle-disconnect; +- +- imux64: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux65: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux66: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux67: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- adm1278@10 { +- compatible = "adi,adm1278"; +- reg = <0x10>; +- #address-cells = <1>; +- #size-cells = <0>; +- shunt-resistor-micro-ohms = <250>; +- }; +- }; +- +- imux68: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux69: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux70: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux71: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- }; +- +- imux27: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- i2c-switch@76 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x76>; +- i2c-mux-idle-disconnect; +- +- imux72: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux73: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux74: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux75: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- adm1278@10 { +- compatible = "adi,adm1278"; +- reg = <0x10>; +- #address-cells = <1>; +- #size-cells = <0>; +- shunt-resistor-micro-ohms = <250>; +- }; +- }; +- +- imux76: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux77: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux78: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux79: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- }; +- +- imux28: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux29: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux30: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux31: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- +- }; +-}; +- +-&i2c11 { +- status = "okay"; +- +- /* +- * PCA9548 (11-0077) provides 8 channels connecting to SMB (Switch +- * Main Board). +- */ +- i2c-switch@77 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x77>; +- i2c-mux-idle-disconnect; +- +- imux40: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- i2c-switch@76 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x76>; +- i2c-mux-idle-disconnect; +- +- imux80: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux81: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux82: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux83: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux84: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux85: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux86: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux87: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- }; +- +- imux41: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- i2c-switch@76 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x76>; +- i2c-mux-idle-disconnect; +- +- imux88: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux89: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux90: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux91: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux92: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux93: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux94: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux95: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- }; +- +- imux42: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- i2c-switch@76 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x76>; +- i2c-mux-idle-disconnect; +- +- imux96: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux97: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux98: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux99: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux100: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux101: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux102: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux103: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- }; +- +- imux43: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- i2c-switch@76 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x76>; +- i2c-mux-idle-disconnect; +- +- imux104: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux105: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux106: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux107: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux108: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux109: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux110: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux111: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- }; +- +- imux44: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- +- i2c-switch@76 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x76>; +- i2c-mux-idle-disconnect; +- +- imux112: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux113: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux114: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux115: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux116: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux117: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux118: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux119: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- }; +- +- imux45: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- +- i2c-switch@76 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x76>; +- i2c-mux-idle-disconnect; +- +- imux120: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux121: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux122: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux123: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux124: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux125: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux126: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux127: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- }; +- +- imux46: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- +- i2c-switch@76 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x76>; +- i2c-mux-idle-disconnect; +- +- imux128: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux129: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux130: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux131: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux132: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux133: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux134: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux135: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- }; +- +- imux47: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- +- i2c-switch@76 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x76>; +- i2c-mux-idle-disconnect; +- +- imux136: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux137: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux138: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux139: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux140: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux141: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux142: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux143: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +- }; +- +- }; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&mdio1 { +- status = "okay"; +- +- ethphy3: ethernet-phy@13 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0x0d>; +- }; +-}; +- +-&mac3 { +- status = "okay"; +- phy-mode = "rgmii"; +- phy-handle = <ðphy3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii4_default>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-galaxy100.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-galaxy100.dts +deleted file mode 100644 +index 60e875ac2461..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-galaxy100.dts ++++ /dev/null +@@ -1,53 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright (c) 2020 Facebook Inc. +-/dts-v1/; +- +-#include "ast2400-facebook-netbmc-common.dtsi" +- +-/ { +- model = "Facebook Galaxy 100 BMC"; +- compatible = "facebook,galaxy100-bmc", "aspeed,ast2400"; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS0,9600n8 root=/dev/ram rw"; +- }; +- +- ast-adc-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 3>, <&adc 4>, <&adc 8>, <&adc 9>; +- }; +-}; +- +-&wdt2 { +- status = "okay"; +- aspeed,reset-type = "system"; +-}; +- +-&fmc { +- flash@1 { +- status = "okay"; +- m25p,fast-read; +- label = "spi0.1"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- flash1@0 { +- reg = <0x0 0x2000000>; +- label = "flash1"; +- }; +- }; +- }; +-}; +- +- +-&i2c9 { +- status = "okay"; +-}; +- +-&vhub { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-minipack.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-minipack.dts +deleted file mode 100644 +index 230d16cd9967..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-minipack.dts ++++ /dev/null +@@ -1,1339 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright (c) 2018 Facebook Inc. +-/dts-v1/; +- +-#include "ast2500-facebook-netbmc-common.dtsi" +- +-/ { +- model = "Facebook Minipack 100 BMC"; +- compatible = "facebook,minipack-bmc", "aspeed,ast2500"; +- +- aliases { +- /* +- * Override the default serial aliases to avoid breaking +- * the legacy applications. +- */ +- serial0 = &uart5; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- +- /* +- * i2c switch 2-0070, pca9548, 8 child channels assigned +- * with bus number 16-23. +- */ +- i2c16 = &imux16; +- i2c17 = &imux17; +- i2c18 = &imux18; +- i2c19 = &imux19; +- i2c20 = &imux20; +- i2c21 = &imux21; +- i2c22 = &imux22; +- i2c23 = &imux23; +- +- /* +- * i2c switch 8-0070, pca9548, 8 child channels assigned +- * with bus number 24-31. +- */ +- i2c24 = &imux24; +- i2c25 = &imux25; +- i2c26 = &imux26; +- i2c27 = &imux27; +- i2c28 = &imux28; +- i2c29 = &imux29; +- i2c30 = &imux30; +- i2c31 = &imux31; +- +- /* +- * i2c switch 9-0070, pca9548, 8 child channels assigned +- * with bus number 32-39. +- */ +- i2c32 = &imux32; +- i2c33 = &imux33; +- i2c34 = &imux34; +- i2c35 = &imux35; +- i2c36 = &imux36; +- i2c37 = &imux37; +- i2c38 = &imux38; +- i2c39 = &imux39; +- +- /* +- * i2c switch 11-0070, pca9548, 8 child channels assigned +- * with bus number 40-47. +- */ +- i2c40 = &imux40; +- i2c41 = &imux41; +- i2c42 = &imux42; +- i2c43 = &imux43; +- i2c44 = &imux44; +- i2c45 = &imux45; +- i2c46 = &imux46; +- i2c47 = &imux47; +- +- /* +- * I2C Switch 24-0071 (channel #0 of 8-0070): 8 channels for +- * connecting to left PDB (Power Distribution Board). +- */ +- i2c48 = &imux48; +- i2c49 = &imux49; +- i2c50 = &imux50; +- i2c51 = &imux51; +- i2c52 = &imux52; +- i2c53 = &imux53; +- i2c54 = &imux54; +- i2c55 = &imux55; +- +- /* +- * I2C Switch 25-0072 (channel #1 of 8-0070): 8 channels for +- * connecting to right PDB (Power Distribution Board). +- */ +- i2c56 = &imux56; +- i2c57 = &imux57; +- i2c58 = &imux58; +- i2c59 = &imux59; +- i2c60 = &imux60; +- i2c61 = &imux61; +- i2c62 = &imux62; +- i2c63 = &imux63; +- +- /* +- * I2C Switch 26-0076 (channel #2 of 8-0070): 8 channels for +- * connecting to top FCM (Fan Control Module). +- */ +- i2c64 = &imux64; +- i2c65 = &imux65; +- i2c66 = &imux66; +- i2c67 = &imux67; +- i2c68 = &imux68; +- i2c69 = &imux69; +- i2c70 = &imux70; +- i2c71 = &imux71; +- +- /* +- * I2C Switch 27-0076 (channel #3 of 8-0070): 8 channels for +- * connecting to bottom FCM (Fan Control Module). +- */ +- i2c72 = &imux72; +- i2c73 = &imux73; +- i2c74 = &imux74; +- i2c75 = &imux75; +- i2c76 = &imux76; +- i2c77 = &imux77; +- i2c78 = &imux78; +- i2c79 = &imux79; +- +- /* +- * I2C Switch 40-0073 (channel #0 of 11-0070): connecting +- * to PIM (Port Interface Module) #1 (1-based). +- */ +- i2c80 = &imux80; +- i2c81 = &imux81; +- i2c82 = &imux82; +- i2c83 = &imux83; +- i2c84 = &imux84; +- i2c85 = &imux85; +- i2c86 = &imux86; +- i2c87 = &imux87; +- +- /* +- * I2C Switch 41-0073 (channel #1 of 11-0070): connecting +- * to PIM (Port Interface Module) #2 (1-based). +- */ +- i2c88 = &imux88; +- i2c89 = &imux89; +- i2c90 = &imux90; +- i2c91 = &imux91; +- i2c92 = &imux92; +- i2c93 = &imux93; +- i2c94 = &imux94; +- i2c95 = &imux95; +- +- /* +- * I2C Switch 42-0073 (channel #2 of 11-0070): connecting +- * to PIM (Port Interface Module) #3 (1-based). +- */ +- i2c96 = &imux96; +- i2c97 = &imux97; +- i2c98 = &imux98; +- i2c99 = &imux99; +- i2c100 = &imux100; +- i2c101 = &imux101; +- i2c102 = &imux102; +- i2c103 = &imux103; +- +- /* +- * I2C Switch 43-0073 (channel #3 of 11-0070): connecting +- * to PIM (Port Interface Module) #4 (1-based). +- */ +- i2c104 = &imux104; +- i2c105 = &imux105; +- i2c106 = &imux106; +- i2c107 = &imux107; +- i2c108 = &imux108; +- i2c109 = &imux109; +- i2c110 = &imux110; +- i2c111 = &imux111; +- +- /* +- * I2C Switch 44-0073 (channel #4 of 11-0070): connecting +- * to PIM (Port Interface Module) #5 (1-based). +- */ +- i2c112 = &imux112; +- i2c113 = &imux113; +- i2c114 = &imux114; +- i2c115 = &imux115; +- i2c116 = &imux116; +- i2c117 = &imux117; +- i2c118 = &imux118; +- i2c119 = &imux119; +- +- /* +- * I2C Switch 45-0073 (channel #5 of 11-0070): connecting +- * to PIM (Port Interface Module) #6 (1-based). +- */ +- i2c120 = &imux120; +- i2c121 = &imux121; +- i2c122 = &imux122; +- i2c123 = &imux123; +- i2c124 = &imux124; +- i2c125 = &imux125; +- i2c126 = &imux126; +- i2c127 = &imux127; +- +- /* +- * I2C Switch 46-0073 (channel #6 of 11-0070): connecting +- * to PIM (Port Interface Module) #7 (1-based). +- */ +- i2c128 = &imux128; +- i2c129 = &imux129; +- i2c130 = &imux130; +- i2c131 = &imux131; +- i2c132 = &imux132; +- i2c133 = &imux133; +- i2c134 = &imux134; +- i2c135 = &imux135; +- +- /* +- * I2C Switch 47-0073 (channel #7 of 11-0070): connecting +- * to PIM (Port Interface Module) #8 (1-based). +- */ +- i2c136 = &imux136; +- i2c137 = &imux137; +- i2c138 = &imux138; +- i2c139 = &imux139; +- i2c140 = &imux140; +- i2c141 = &imux141; +- i2c142 = &imux142; +- i2c143 = &imux143; +- }; +- +- chosen { +- stdout-path = &uart1; +- bootargs = "debug console=ttyS1,9600n8 root=/dev/ram rw"; +- }; +-}; +- +-&wdt2 { +- status = "okay"; +- aspeed,reset-type = "system"; +-}; +- +-/* +- * Both firmware flashes are 64MB on Minipack BMC. +- */ +-&fmc_flash0 { +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* +- * u-boot partition: 384KB. +- */ +- u-boot@0 { +- reg = <0x0 0x60000>; +- label = "u-boot"; +- }; +- +- /* +- * u-boot environment variables: 128KB. +- */ +- u-boot-env@60000 { +- reg = <0x60000 0x20000>; +- label = "env"; +- }; +- +- /* +- * FIT image: 55.5 MB. +- */ +- fit@80000 { +- reg = <0x80000 0x3780000>; +- label = "fit"; +- }; +- +- /* +- * "data0" partition (8MB) is reserved for persistent +- * data store. +- */ +- data0@3800000 { +- reg = <0x3800000 0x800000>; +- label = "data0"; +- }; +- +- /* +- * "flash0" partition (covering the entire flash) is +- * explicitly created to avoid breaking legacy applications. +- */ +- flash0@0 { +- reg = <0x0 0x4000000>; +- label = "flash0"; +- }; +- }; +-}; +- +-&fmc_flash1 { +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- flash1@0 { +- reg = <0x0 0x4000000>; +- }; +- }; +-}; +- +-&uart1 { +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default +- &pinctrl_ncts1_default +- &pinctrl_ndsr1_default +- &pinctrl_ndtr1_default +- &pinctrl_nrts1_default>; +-}; +- +-&uart2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd2_default +- &pinctrl_rxd2_default>; +-}; +- +-&uart4 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd4_default +- &pinctrl_rxd4_default>; +-}; +- +-&i2c0 { +- status = "okay"; +- bus-frequency = <400000>; +- multi-master; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +- +- /* +- * I2C Switch 2-0070 is connecting to SCM (System Controller +- * Module). +- */ +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux16: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux17: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux18: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux19: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux20: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux21: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux22: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux23: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +- multi-master; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- status = "okay"; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&i2c8 { +- status = "okay"; +- +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- /* +- * I2C Switch 8-0070 channel #0: connecting to left PDB +- * (Power Distribution Board). +- */ +- imux24: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- i2c-switch@71 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x71>; +- i2c-mux-idle-disconnect; +- +- imux48: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux49: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux50: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux51: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux52: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux53: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux54: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux55: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* +- * I2C Switch 8-0070 channel #1: connecting to right PDB +- * (Power Distribution Board). +- */ +- imux25: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- i2c-switch@72 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x72>; +- i2c-mux-idle-disconnect; +- +- imux56: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux57: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux58: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux59: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux60: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux61: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux62: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux63: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* +- * I2C Switch 8-0070 channel #2: connecting to top FCM +- * (Fan Control Module). +- */ +- imux26: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- i2c-switch@76 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x76>; +- i2c-mux-idle-disconnect; +- +- imux64: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux65: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux66: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux67: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux68: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux69: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux70: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux71: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* +- * I2C Switch 8-0070 channel #3: connecting to bottom +- * FCM (Fan Control Module). +- */ +- imux27: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- i2c-switch@76 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x76>; +- i2c-mux-idle-disconnect; +- +- imux72: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux73: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux74: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux75: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux76: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux77: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux78: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux79: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- imux28: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux29: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux30: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux31: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +-}; +- +-&i2c9 { +- status = "okay"; +- +- /* +- * I2C Switch 9-0070 is connecting to MAC/PHY EEPROMs on SMB +- * (Switch Main Board). +- */ +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux32: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux33: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux34: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux35: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux36: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux37: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux38: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux39: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +-}; +- +-&i2c10 { +- status = "okay"; +-}; +- +-&i2c11 { +- status = "okay"; +- +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- /* +- * I2C Switch 11-0070 channel #0: connecting to PIM +- * (Port Interface Module) #1 (1-based). +- */ +- imux40: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- i2c-switch@73 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- i2c-mux-idle-disconnect; +- +- imux80: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux81: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux82: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux83: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux84: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux85: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux86: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux87: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* +- * I2C Switch 11-0070 channel #1: connecting to PIM +- * (Port Interface Module) #2 (1-based). +- */ +- imux41: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- i2c-switch@73 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- i2c-mux-idle-disconnect; +- +- imux88: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux89: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux90: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux91: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux92: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux93: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux94: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux95: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* +- * I2C Switch 11-0070 channel #2: connecting to PIM +- * (Port Interface Module) #3 (1-based). +- */ +- imux42: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- i2c-switch@73 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- i2c-mux-idle-disconnect; +- +- imux96: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux97: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux98: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux99: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux100: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux101: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux102: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux103: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* +- * I2C Switch 11-0070 channel #3: connecting to PIM +- * (Port Interface Module) #4 (1-based). +- */ +- imux43: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- i2c-switch@73 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- i2c-mux-idle-disconnect; +- +- imux104: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux105: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux106: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux107: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux108: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux109: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux110: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux111: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* +- * I2C Switch 11-0070 channel #4: connecting to PIM +- * (Port Interface Module) #5 (1-based). +- */ +- imux44: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- +- i2c-switch@73 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- i2c-mux-idle-disconnect; +- +- imux112: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux113: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux114: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux115: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux116: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux117: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux118: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux119: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* +- * I2C Switch 11-0070 channel #5: connecting to PIM +- * (Port Interface Module) #6 (1-based). +- */ +- imux45: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- +- i2c-switch@73 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- i2c-mux-idle-disconnect; +- +- imux120: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux121: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux122: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux123: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux124: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux125: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux126: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux127: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* +- * I2C Switch 11-0070 channel #6: connecting to PIM +- * (Port Interface Module) #7 (1-based). +- */ +- imux46: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- +- i2c-switch@73 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- i2c-mux-idle-disconnect; +- +- imux128: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux129: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux130: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux131: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux132: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux133: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux134: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux135: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- +- /* +- * I2C Switch 11-0070 channel #7: connecting to PIM +- * (Port Interface Module) #8 (1-based). +- */ +- imux47: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- +- i2c-switch@73 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- i2c-mux-idle-disconnect; +- +- imux136: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux137: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux138: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux139: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux140: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux141: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux142: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux143: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- }; +- }; +-}; +- +-&i2c12 { +- status = "okay"; +-}; +- +-&i2c13 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-tiogapass.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-tiogapass.dts +deleted file mode 100644 +index b6b16356f571..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-tiogapass.dts ++++ /dev/null +@@ -1,549 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright (c) 2018 Facebook Inc. +-// Author: Vijay Khemka +-/dts-v1/; +- +-#include "aspeed-g5.dtsi" +-#include +-#include +- +-/ { +- model = "Facebook TiogaPass BMC"; +- compatible = "facebook,tiogapass-bmc", "aspeed,ast2500"; +- aliases { +- serial0 = &uart1; +- serial4 = &uart5; +- +- /* +- * Hardcode the bus number of i2c switches' channels to +- * avoid breaking the legacy applications. +- */ +- i2c16 = &imux16; +- i2c17 = &imux17; +- i2c18 = &imux18; +- i2c19 = &imux19; +- i2c20 = &imux20; +- i2c21 = &imux21; +- i2c22 = &imux22; +- i2c23 = &imux23; +- i2c24 = &imux24; +- i2c25 = &imux25; +- i2c26 = &imux26; +- i2c27 = &imux27; +- i2c28 = &imux28; +- i2c29 = &imux29; +- i2c30 = &imux30; +- i2c31 = &imux31; +- }; +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x20000000>; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, +- <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; +- }; +- +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "pnor"; +- }; +-}; +- +-&lpc_snoop { +- status = "okay"; +- snoop-ports = <0x80>; +-}; +- +-&lpc_ctrl { +- // Enable lpc clock +- status = "okay"; +-}; +- +-&uart1 { +- // Host Console +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default>; +-}; +- +-&uart2 { +- // SoL Host Console +- status = "okay"; +-}; +- +-&uart3 { +- // SoL BMC Console +- status = "okay"; +-}; +- +-&uart5 { +- // BMC Console +- status = "okay"; +-}; +- +-&kcs2 { +- // BMC KCS channel 2 +- status = "okay"; +- aspeed,lpc-io-reg = <0xca8>; +-}; +- +-&kcs3 { +- // BMC KCS channel 3 +- status = "okay"; +- aspeed,lpc-io-reg = <0xca2>; +-}; +- +-&gpio { +- status = "okay"; +- gpio-line-names = +- /*A0-A7*/ "BMC_CPLD_FPGA_SEL","","","","","","","", +- /*B0-B7*/ "","BMC_DEBUG_EN","","","","BMC_PPIN","PS_PWROK", +- "IRQ_PVDDQ_GHJ_VRHOT_LVT3", +- /*C0-C7*/ "","","","","","","","", +- /*D0-D7*/ "BIOS_MRC_DEBUG_MSG_DIS","BOARD_REV_ID0","", +- "BOARD_REV_ID1","IRQ_DIMM_SAVE_LVT3","BOARD_REV_ID2", +- "CPU_ERR0_LVT3_BMC","CPU_ERR1_LVT3_BMC", +- /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON", +- "POWER_OUT","NMI_BUTTON","","CPU0_PROCHOT_LVT3_ BMC", +- "CPU1_PROCHOT_LVT3_ BMC", +- /*F0-F7*/ "IRQ_PVDDQ_ABC_VRHOT_LVT3","", +- "IRQ_PVCCIN_CPU0_VRHOT_LVC3", +- "IRQ_PVCCIN_CPU1_VRHOT_LVC3", +- "IRQ_PVDDQ_KLM_VRHOT_LVT3","","P3VBAT_BRIDGE_EN","", +- /*G0-G7*/ "CPU_ERR2_LVT3","CPU_CATERR_LVT3","PCH_BMC_THERMTRIP", +- "CPU0_SKTOCC_LVT3","","","","BIOS_SMI_ACTIVE", +- /*H0-H7*/ "LED_POST_CODE_0","LED_POST_CODE_1","LED_POST_CODE_2", +- "LED_POST_CODE_3","LED_POST_CODE_4","LED_POST_CODE_5", +- "LED_POST_CODE_6","LED_POST_CODE_7", +- /*I0-I7*/ "CPU0_FIVR_FAULT_LVT3","CPU1_FIVR_FAULT_LVT3", +- "FORCE_ADR","UV_ADR_TRIGGER_EN","","","","", +- /*J0-J7*/ "","","","","","","","", +- /*K0-K7*/ "","","","","","","","", +- /*L0-L7*/ "IRQ_UV_DETECT","IRQ_OC_DETECT","HSC_TIMER_EXP","", +- "MEM_THERM_EVENT_PCH","PMBUS_ALERT_BUF_EN","","", +- /*M0-M7*/ "CPU0_RC_ERROR","CPU1_RC_ERROR","","OC_DETECT_EN", +- "CPU0_THERMTRIP_LATCH_LVT3", +- "CPU1_THERMTRIP_LATCH_LVT3","","", +- /*N0-N7*/ "","","","CPU_MSMI_LVT3","","BIOS_SPI_BMC_CTRL","","", +- /*O0-O7*/ "","","","","","","","", +- /*P0-P7*/ "BOARD_SKU_ID0","BOARD_SKU_ID1","BOARD_SKU_ID2", +- "BOARD_SKU_ID3","BOARD_SKU_ID4","BMC_PREQ", +- "BMC_PWR_DEBUG","RST_RSMRST", +- /*Q0-Q7*/ "","","","","UARTSW_LSB","UARTSW_MSB", +- "POST_CARD_PRES_BMC","PE_BMC_WAKE", +- /*R0-R7*/ "","","BMC_TCK_MUX_SEL","BMC_PRDY", +- "BMC_XDP_PRSNT_IN","RST_BMC_PLTRST_BUF","SLT_CFG0", +- "SLT_CFG1", +- /*S0-S7*/ "THROTTLE","BMC_READY","","HSC_SMBUS_SWITCH_EN","", +- "","","", +- /*T0-T7*/ "","","","","","","","", +- /*U0-U7*/ "","","","","","BMC_FAULT","","", +- /*V0-V7*/ "","","","FAST_PROCHOT_EN","","","","", +- /*W0-W7*/ "","","","","","","","", +- /*X0-X7*/ "","","","GLOBAL_RST_WARN", +- "CPU0_MEMABC_MEMHOT_LVT3_BMC", +- "CPU0_MEMDEF_MEMHOT_LVT3_BMC", +- "CPU1_MEMGHJ_MEMHOT_LVT3_BMC", +- "CPU1_MEMKLM_MEMHOT_LVT3_BMC", +- /*Y0-Y7*/ "SIO_S3","SIO_S5","BMC_JTAG_SEL","SIO_ONCONTROL","", +- "","","", +- /*Z0-Z7*/ "","SIO_POWER_GOOD","IRQ_PVDDQ_DEF_VRHOT_LVT3","", +- "","","","", +- /*AA0-AA7*/ "CPU1_SKTOCC_LVT3","IRQ_SML1_PMBUS_ALERT", +- "SERVER_POWER_LED","","PECI_MUX_SELECT","UV_HIGH_SET", +- "","POST_COMPLETE", +- /*AB0-AB7*/ "IRQ_HSC_FAULT","OCP_MEZZA_PRES","","","","","","", +- /*AC0-AC7*/ "","","","","","","",""; +-}; +- +-&mac0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&mac1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii2_default>; +- use-ncsi; +-}; +- +-&adc { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- //Airmax Conn B, CPU0 PIROM, CPU1 PIROM +-}; +- +-&i2c1 { +- status = "okay"; +- //X24 Riser +- i2c-switch@71 { +- compatible = "nxp,pca9544"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x71>; +- +- imux16: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- ina230@45 { +- compatible = "ti,ina230"; +- reg = <0x45>; +- }; +- +- tmp75@48 { +- compatible = "ti,tmp75"; +- reg = <0x48>; +- }; +- +- tmp421@49 { +- compatible = "ti,tmp75"; +- reg = <0x49>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- pagesize = <32>; +- }; +- +- i2c-switch@73 { +- compatible = "nxp,pca9546"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- +- imux20: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux21: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux22: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux23: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- }; +- +- }; +- +- imux17: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- ina230@45 { +- compatible = "ti,ina230"; +- reg = <0x45>; +- }; +- +- tmp421@48 { +- compatible = "ti,tmp75"; +- reg = <0x48>; +- }; +- +- tmp421@49 { +- compatible = "ti,tmp75"; +- reg = <0x49>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- pagesize = <32>; +- }; +- +- i2c-switch@73 { +- compatible = "nxp,pca9546"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- +- imux24: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux25: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux26: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux27: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- }; +- +- }; +- +- imux18: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- ina230@45 { +- compatible = "ti,ina230"; +- reg = <0x45>; +- }; +- +- tmp421@48 { +- compatible = "ti,tmp75"; +- reg = <0x48>; +- }; +- +- tmp421@49 { +- compatible = "ti,tmp75"; +- reg = <0x49>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- pagesize = <32>; +- }; +- +- i2c-switch@73 { +- compatible = "nxp,pca9546"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- +- imux28: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux29: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux30: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux31: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- }; +- +- }; +- +- imux19: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- i2c-switch@40 { +- compatible = "ti,ina230"; +- reg = <0x40>; +- }; +- +- i2c-switch@41 { +- compatible = "ti,ina230"; +- reg = <0x41>; +- }; +- +- i2c-switch@45 { +- compatible = "ti,ina230"; +- reg = <0x45>; +- }; +- +- }; +- +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- // Mezz Management SMBus +-}; +- +-&i2c3 { +- status = "okay"; +- // SMBus to Board ID EEPROM +-}; +- +-&i2c4 { +- status = "okay"; +- // BMC Debug Header +- ipmb0@10 { +- compatible = "ipmb-dev"; +- reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; +- i2c-protocol; +- }; +-}; +- +-&i2c5 { +- status = "okay"; +- // CPU Voltage regulators +- regulator@48 { +- compatible = "infineon,pxe1610"; +- reg = <0x48>; +- }; +- regulator@4a { +- compatible = "infineon,pxe1610"; +- reg = <0x4a>; +- }; +- regulator@50 { +- compatible = "infineon,pxe1610"; +- reg = <0x50>; +- }; +- regulator@52 { +- compatible = "infineon,pxe1610"; +- reg = <0x52>; +- }; +- regulator@58 { +- compatible = "infineon,pxe1610"; +- reg = <0x58>; +- }; +- regulator@5a { +- compatible = "infineon,pxe1610"; +- reg = <0x5a>; +- }; +- regulator@68 { +- compatible = "infineon,pxe1610"; +- reg = <0x68>; +- }; +- regulator@70 { +- compatible = "infineon,pxe1610"; +- reg = <0x70>; +- }; +- regulator@72 { +- compatible = "infineon,pxe1610"; +- reg = <0x72>; +- }; +-}; +- +-&i2c6 { +- status = "okay"; +- tpm@20 { +- compatible = "infineon,slb9645tt"; +- reg = <0x20>; +- }; +- tmp421@4e { +- compatible = "ti,tmp421"; +- reg = <0x4e>; +- }; +- tmp421@4f { +- compatible = "ti,tmp421"; +- reg = <0x4f>; +- }; +- eeprom@54 { +- compatible = "atmel,24c64"; +- reg = <0x54>; +- pagesize = <32>; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +- //HSC, AirMax Conn A +- adm1278@45 { +- compatible = "adm1275"; +- reg = <0x45>; +- shunt-resistor-micro-ohms = <250>; +- }; +-}; +- +-&i2c8 { +- status = "okay"; +- tmp421@1f { +- compatible = "ti,tmp421"; +- reg = <0x1f>; +- }; +- //Mezz Sensor SMBus +-}; +- +-&i2c9 { +- status = "okay"; +- //USB Debug Connector +- ipmb0@10 { +- compatible = "ipmb-dev"; +- reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; +- i2c-protocol; +- }; +-}; +- +-&pwm_tacho { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; +- fan@0 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x00>; +- }; +- +- fan@1 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x02>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-wedge100.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-wedge100.dts +deleted file mode 100644 +index 584efa528450..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-wedge100.dts ++++ /dev/null +@@ -1,63 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright (c) 2018 Facebook Inc. +-/dts-v1/; +- +-#include "ast2400-facebook-netbmc-common.dtsi" +- +-/ { +- model = "Facebook Wedge 100 BMC"; +- compatible = "facebook,wedge100-bmc", "aspeed,ast2400"; +- +- chosen { +- stdout-path = &uart3; +- bootargs = "console=ttyS2,9600n8 root=/dev/ram rw"; +- }; +- +- ast-adc-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>; +- }; +-}; +- +-&wdt2 { +- status = "okay"; +- aspeed,reset-type = "system"; +-}; +- +-&fmc { +- flash@1 { +- status = "okay"; +- m25p,fast-read; +- label = "spi0.1"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- flash1@0 { +- reg = <0x0 0x2000000>; +- label = "flash1"; +- }; +- }; +- }; +-}; +- +-&i2c7 { +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- }; +-}; +- +-&i2c9 { +- status = "okay"; +-}; +- +- +-&vhub { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-wedge40.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-wedge40.dts +deleted file mode 100644 +index 6624855d8ebd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-wedge40.dts ++++ /dev/null +@@ -1,53 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright (c) 2018 Facebook Inc. +-/dts-v1/; +- +-#include "ast2400-facebook-netbmc-common.dtsi" +- +-/ { +- model = "Facebook Wedge 40 BMC"; +- compatible = "facebook,wedge40-bmc", "aspeed,ast2400"; +- +- chosen { +- stdout-path = &uart3; +- bootargs = "console=ttyS2,9600n8 root=/dev/ram rw"; +- }; +- +- ast-adc-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>; +- }; +-}; +- +-&wdt2 { +- status = "disabled"; +-}; +- +-&pwm_tacho { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default +- &pinctrl_pwm1_default +- &pinctrl_pwm6_default +- &pinctrl_pwm7_default>; +- +- fan@0 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; +- }; +- +- fan@1 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; +- }; +- +- fan@6 { +- reg = <0x06>; +- aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>; +- }; +- +- fan@7 { +- reg = <0x07>; +- aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-wedge400.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-wedge400.dts +deleted file mode 100644 +index a901c8be49b9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-wedge400.dts ++++ /dev/null +@@ -1,374 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright (c) 2019 Facebook Inc. +-/dts-v1/; +- +-#include +-#include "ast2500-facebook-netbmc-common.dtsi" +- +-/ { +- model = "Facebook Wedge 400 BMC"; +- compatible = "facebook,wedge400-bmc", "aspeed,ast2500"; +- +- aliases { +- /* +- * PCA9548 (2-0070) provides 8 channels connecting to +- * SCM (System Controller Module). +- */ +- i2c16 = &imux16; +- i2c17 = &imux17; +- i2c18 = &imux18; +- i2c19 = &imux19; +- i2c20 = &imux20; +- i2c21 = &imux21; +- i2c22 = &imux22; +- i2c23 = &imux23; +- +- /* +- * PCA9548 (8-0070) provides 8 channels connecting to +- * SMB (Switch Main Board). +- */ +- i2c24 = &imux24; +- i2c25 = &imux25; +- i2c26 = &imux26; +- i2c27 = &imux27; +- i2c28 = &imux28; +- i2c29 = &imux29; +- i2c30 = &imux30; +- i2c31 = &imux31; +- +- /* +- * PCA9548 (11-0076) provides 8 channels connecting to +- * FCM (Fan Controller Module). +- */ +- i2c32 = &imux32; +- i2c33 = &imux33; +- i2c34 = &imux34; +- i2c35 = &imux35; +- i2c36 = &imux36; +- i2c37 = &imux37; +- i2c38 = &imux38; +- i2c39 = &imux39; +- +- spi2 = &spi_gpio; +- }; +- +- chosen { +- stdout-path = &uart1; +- bootargs = "console=ttyS0,9600n8 root=/dev/ram rw"; +- }; +- +- ast-adc-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>; +- }; +- +- /* +- * GPIO-based SPI Master is required to access SPI TPM, because +- * full-duplex SPI transactions are not supported by ASPEED SPI +- * Controllers. +- */ +- spi_gpio: spi-gpio { +- status = "okay"; +- compatible = "spi-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cs-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_LOW>; +- gpio-sck = <&gpio ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>; +- gpio-mosi = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>; +- gpio-miso = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>; +- num-chipselects = <1>; +- +- tpmdev@0 { +- compatible = "tcg,tpm_tis-spi"; +- spi-max-frequency = <33000000>; +- reg = <0>; +- }; +- }; +-}; +- +-/* +- * Both firmware flashes are 128MB on Wedge400 BMC. +- */ +-&fmc_flash0 { +-#include "facebook-bmc-flash-layout-128.dtsi" +-}; +- +-&fmc_flash1 { +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- flash1@0 { +- reg = <0x0 0x8000000>; +- label = "flash1"; +- }; +- }; +-}; +- +-&uart2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd2_default +- &pinctrl_rxd2_default>; +-}; +- +-&uart4 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd4_default +- &pinctrl_rxd4_default>; +-}; +- +-/* +- * I2C bus #0 is multi-master environment dedicated for BMC and Bridge IC +- * communication. +- */ +-&i2c0 { +- status = "okay"; +- multi-master; +- bus-frequency = <1000000>; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +- +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux16: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux17: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux18: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux19: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux20: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux21: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux22: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux23: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- status = "okay"; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&i2c8 { +- status = "okay"; +- +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- imux24: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux25: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux26: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux27: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux28: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux29: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux30: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux31: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- +- }; +-}; +- +-&i2c9 { +- status = "okay"; +-}; +- +-&i2c10 { +- status = "okay"; +-}; +- +-&i2c11 { +- status = "okay"; +- +- i2c-switch@76 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x76>; +- i2c-mux-idle-disconnect; +- +- imux32: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- imux33: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- imux34: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- imux35: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- imux36: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- imux37: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- imux38: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- imux39: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- +- }; +-}; +- +-&i2c12 { +- status = "okay"; +-}; +- +-&i2c13 { +- status = "okay"; +-}; +- +-&adc { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&uhci { +- status = "okay"; +-}; +- +-&sdhci1 { +- /* +- * DMA mode needs to be disabled to avoid conflicts with UHCI +- * Controller in AST2500 SoC. +- */ +- sdhci-caps-mask = <0x0 0x580000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-yamp.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-yamp.dts +deleted file mode 100644 +index 5e6105874217..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-yamp.dts ++++ /dev/null +@@ -1,127 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright (c) 2018 Facebook Inc. +-/dts-v1/; +- +-#include "ast2500-facebook-netbmc-common.dtsi" +- +-/ { +- model = "Facebook YAMP 100 BMC"; +- compatible = "facebook,yamp-bmc", "aspeed,ast2500"; +- +- aliases { +- /* +- * Override the default uart aliases to avoid breaking +- * the legacy applications. +- */ +- serial0 = &uart5; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- }; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS0,9600n8 root=/dev/ram rw"; +- }; +-}; +- +-&uart2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd2_default +- &pinctrl_rxd2_default>; +-}; +- +-&mac0 { +- status = "okay"; +- use-ncsi; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +-}; +- +-&mac1 { +- status = "disabled"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +- +- i2c-switch@75 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x75>; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- status = "okay"; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&i2c8 { +- status = "okay"; +-}; +- +-&i2c9 { +- status = "okay"; +-}; +- +-&i2c10 { +- status = "okay"; +-}; +- +-&i2c11 { +- status = "okay"; +-}; +- +-&i2c12 { +- status = "okay"; +-}; +- +-&i2c13 { +- status = "okay"; +-}; +- +-&fmc_flash0 { +-#include "facebook-bmc-flash-layout.dtsi" +-}; +- +-&fmc_flash1 { +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- flash1@0 { +- reg = <0x0 0x2000000>; +- label = "flash1"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-yosemitev2.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-yosemitev2.dts +deleted file mode 100644 +index 8864e9c312a8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-facebook-yosemitev2.dts ++++ /dev/null +@@ -1,231 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-// Copyright (c) 2018 Facebook Inc. +-/dts-v1/; +-#include "aspeed-g5.dtsi" +-#include +- +-/ { +- model = "Facebook Yosemitev2 BMC"; +- compatible = "facebook,yosemitev2-bmc", "aspeed,ast2500"; +- aliases { +- serial4 = &uart5; +- }; +- chosen { +- stdout-path = &uart5; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x20000000>; +- }; +- +- iio-hwmon { +- // VOLATAGE SENSOR +- compatible = "iio-hwmon"; +- io-channels = <&adc 0> , <&adc 1> , <&adc 2> , <&adc 3> , +- <&adc 4> , <&adc 5> , <&adc 6> , <&adc 7> , +- <&adc 8> , <&adc 9> , <&adc 10>, <&adc 11> , +- <&adc 12> , <&adc 13> , <&adc 14> , <&adc 15> ; +- }; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "pnor"; +- }; +-}; +-&uart1 { +- // Host1 Console +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default>; +-}; +- +-&uart2 { +- // Host2 Console +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd2_default +- &pinctrl_rxd2_default>; +- +-}; +- +-&uart3 { +- // Host3 Console +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd3_default +- &pinctrl_rxd3_default>; +-}; +- +-&uart4 { +- // Host4 Console +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd4_default +- &pinctrl_rxd4_default>; +-}; +- +-&uart5 { +- // BMC Console +- status = "okay"; +-}; +- +-&vuart { +- // Virtual UART +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- use-ncsi; +- mlx,multi-host; +-}; +- +-&adc { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc0_default +- &pinctrl_adc1_default +- &pinctrl_adc2_default +- &pinctrl_adc3_default +- &pinctrl_adc4_default +- &pinctrl_adc5_default +- &pinctrl_adc6_default +- &pinctrl_adc7_default +- &pinctrl_adc8_default +- &pinctrl_adc9_default +- &pinctrl_adc10_default +- &pinctrl_adc11_default +- &pinctrl_adc12_default +- &pinctrl_adc13_default +- &pinctrl_adc14_default +- &pinctrl_adc15_default>; +-}; +- +-&i2c1 { +- //Host1 IPMB bus +- status = "okay"; +- multi-master; +- ipmb1@10 { +- compatible = "ipmb-dev"; +- reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; +- i2c-protocol; +- }; +-}; +- +-&i2c3 { +- //Host2 IPMB bus +- status = "okay"; +- multi-master; +- ipmb3@10 { +- compatible = "ipmb-dev"; +- reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; +- i2c-protocol; +- }; +-}; +- +-&i2c5 { +- //Host3 IPMB bus +- status = "okay"; +- multi-master; +- ipmb5@10 { +- compatible = "ipmb-dev"; +- reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; +- i2c-protocol; +- }; +-}; +- +-&i2c7 { +- //Host4 IPMB bus +- status = "okay"; +- multi-master; +- ipmb7@10 { +- compatible = "ipmb-dev"; +- reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; +- i2c-protocol; +- }; +-}; +- +-&i2c8 { +- status = "okay"; +- //FRU EEPROM +- eeprom@51 { +- compatible = "atmel,24c64"; +- reg = <0x51>; +- pagesize = <32>; +- }; +-}; +- +-&i2c9 { +- status = "okay"; +- tmp421@4e { +- //INLET TEMP +- compatible = "ti,tmp421"; +- reg = <0x4e>; +- }; +- //OUTLET TEMP +- tmp421@4f { +- compatible = "ti,tmp421"; +- reg = <0x4f>; +- }; +-}; +- +-&i2c10 { +- status = "okay"; +- //HSC +- adm1278@40 { +- compatible = "adi,adm1278"; +- reg = <0x40>; +- }; +-}; +- +-&i2c11 { +- status = "okay"; +- //MEZZ_TEMP_SENSOR +- tmp421@1f { +- compatible = "ti,tmp421"; +- reg = <0x1f>; +- }; +-}; +- +-&i2c12 { +- status = "okay"; +- //MEZZ_FRU +- eeprom@51 { +- compatible = "atmel,24c64"; +- reg = <0x51>; +- pagesize = <32>; +- }; +-}; +- +-&pwm_tacho { +- status = "okay"; +- //FSC +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; +- fan@0 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x00>; +- }; +- fan@1 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x01>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-ibm-everest.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-ibm-everest.dts +deleted file mode 100644 +index 2efd70666738..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-ibm-everest.dts ++++ /dev/null +@@ -1,4095 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-// Copyright 2020 IBM Corp. +-/dts-v1/; +- +-#include "aspeed-g6.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "Everest"; +- compatible = "ibm,everest-bmc", "aspeed,ast2600"; +- +- aliases { +- i2c100 = &cfam0_i2c0; +- i2c101 = &cfam0_i2c1; +- i2c110 = &cfam0_i2c10; +- i2c111 = &cfam0_i2c11; +- i2c112 = &cfam0_i2c12; +- i2c113 = &cfam0_i2c13; +- i2c114 = &cfam0_i2c14; +- i2c115 = &cfam0_i2c15; +- i2c202 = &cfam1_i2c2; +- i2c203 = &cfam1_i2c3; +- i2c210 = &cfam1_i2c10; +- i2c211 = &cfam1_i2c11; +- i2c214 = &cfam1_i2c14; +- i2c215 = &cfam1_i2c15; +- i2c216 = &cfam1_i2c16; +- i2c217 = &cfam1_i2c17; +- i2c300 = &cfam2_i2c0; +- i2c301 = &cfam2_i2c1; +- i2c310 = &cfam2_i2c10; +- i2c311 = &cfam2_i2c11; +- i2c312 = &cfam2_i2c12; +- i2c313 = &cfam2_i2c13; +- i2c314 = &cfam2_i2c14; +- i2c315 = &cfam2_i2c15; +- i2c402 = &cfam3_i2c2; +- i2c403 = &cfam3_i2c3; +- i2c410 = &cfam3_i2c10; +- i2c411 = &cfam3_i2c11; +- i2c414 = &cfam3_i2c14; +- i2c415 = &cfam3_i2c15; +- i2c416 = &cfam3_i2c16; +- i2c417 = &cfam3_i2c17; +- i2c500 = &cfam4_i2c0; +- i2c501 = &cfam4_i2c1; +- i2c510 = &cfam4_i2c10; +- i2c511 = &cfam4_i2c11; +- i2c512 = &cfam4_i2c12; +- i2c513 = &cfam4_i2c13; +- i2c514 = &cfam4_i2c14; +- i2c515 = &cfam4_i2c15; +- i2c602 = &cfam5_i2c2; +- i2c603 = &cfam5_i2c3; +- i2c610 = &cfam5_i2c10; +- i2c611 = &cfam5_i2c11; +- i2c614 = &cfam5_i2c14; +- i2c615 = &cfam5_i2c15; +- i2c616 = &cfam5_i2c16; +- i2c617 = &cfam5_i2c17; +- i2c700 = &cfam6_i2c0; +- i2c701 = &cfam6_i2c1; +- i2c710 = &cfam6_i2c10; +- i2c711 = &cfam6_i2c11; +- i2c712 = &cfam6_i2c12; +- i2c713 = &cfam6_i2c13; +- i2c714 = &cfam6_i2c14; +- i2c715 = &cfam6_i2c15; +- i2c802 = &cfam7_i2c2; +- i2c803 = &cfam7_i2c3; +- i2c810 = &cfam7_i2c10; +- i2c811 = &cfam7_i2c11; +- i2c814 = &cfam7_i2c14; +- i2c815 = &cfam7_i2c15; +- i2c816 = &cfam7_i2c16; +- i2c817 = &cfam7_i2c17; +- +- i2c16 = &i2c4mux0chn0; +- i2c17 = &i2c4mux0chn1; +- i2c18 = &i2c4mux0chn2; +- i2c19 = &i2c5mux0chn0; +- i2c20 = &i2c5mux0chn1; +- i2c21 = &i2c5mux0chn2; +- i2c22 = &i2c5mux0chn3; +- i2c23 = &i2c6mux0chn0; +- i2c24 = &i2c6mux0chn1; +- i2c25 = &i2c6mux0chn2; +- i2c26 = &i2c6mux0chn3; +- i2c27 = &i2c14mux0chn0; +- i2c28 = &i2c14mux0chn1; +- i2c29 = &i2c14mux0chn2; +- i2c30 = &i2c14mux0chn3; +- i2c31 = &i2c14mux1chn0; +- i2c32 = &i2c14mux1chn1; +- i2c33 = &i2c14mux1chn2; +- i2c34 = &i2c14mux1chn3; +- +- serial4 = &uart5; +- +- spi10 = &cfam0_spi0; +- spi11 = &cfam0_spi1; +- spi12 = &cfam0_spi2; +- spi13 = &cfam0_spi3; +- spi20 = &cfam1_spi0; +- spi21 = &cfam1_spi1; +- spi22 = &cfam1_spi2; +- spi23 = &cfam1_spi3; +- spi30 = &cfam2_spi0; +- spi31 = &cfam2_spi1; +- spi32 = &cfam2_spi2; +- spi33 = &cfam2_spi3; +- spi40 = &cfam3_spi0; +- spi41 = &cfam3_spi1; +- spi42 = &cfam3_spi2; +- spi43 = &cfam3_spi3; +- spi50 = &cfam4_spi0; +- spi51 = &cfam4_spi1; +- spi52 = &cfam4_spi2; +- spi53 = &cfam4_spi3; +- spi60 = &cfam5_spi0; +- spi61 = &cfam5_spi1; +- spi62 = &cfam5_spi2; +- spi63 = &cfam5_spi3; +- spi70 = &cfam6_spi0; +- spi71 = &cfam6_spi1; +- spi72 = &cfam6_spi2; +- spi73 = &cfam6_spi3; +- spi80 = &cfam7_spi0; +- spi81 = &cfam7_spi1; +- spi82 = &cfam7_spi2; +- spi83 = &cfam7_spi3; +- }; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200n8"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* LPC FW cycle bridge region requires natural alignment */ +- flash_memory: region@b8000000 { +- no-map; +- reg = <0xb8000000 0x04000000>; /* 64M */ +- }; +- +- /* 48MB region from the end of flash to start of vga memory */ +- ramoops@bc000000 { +- compatible = "ramoops"; +- reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */ +- record-size = <0x8000>; +- console-size = <0x8000>; +- pmsg-size = <0x8000>; +- max-reason = <3>; /* KMSG_DUMP_EMERG */ +- }; +- +- /* VGA region is dictated by hardware strapping */ +- vga_memory: region@bf000000 { +- no-map; +- compatible = "shared-dma-pool"; +- reg = <0xbf000000 0x01000000>; /* 16M */ +- }; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- #address-cells = <1>; +- #size-cells = <0>; +- poll-interval = <1000>; +- +- fan0-presence { +- label = "fan0-presence"; +- gpios = <&pca0 15 GPIO_ACTIVE_LOW>; +- linux,code = <15>; +- }; +- +- fan1-presence { +- label = "fan1-presence"; +- gpios = <&pca0 14 GPIO_ACTIVE_LOW>; +- linux,code = <14>; +- }; +- +- fan2-presence { +- label = "fan2-presence"; +- gpios = <&pca0 13 GPIO_ACTIVE_LOW>; +- linux,code = <13>; +- }; +- +- fan3-presence { +- label = "fan3-presence"; +- gpios = <&pca0 12 GPIO_ACTIVE_LOW>; +- linux,code = <12>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- /* RTC battery fault LED at the back */ +- led-rtc-battery { +- gpios = <&gpio0 ASPEED_GPIO(H, 0) GPIO_ACTIVE_LOW>; +- }; +- +- /* BMC Card fault LED at the back */ +- led-bmc { +- gpios = <&gpio0 ASPEED_GPIO(H, 1) GPIO_ACTIVE_LOW>; +- }; +- +- /* Enclosure Identify LED at the back */ +- led-rear-enc-id0 { +- gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; +- }; +- +- /* Enclosure fault LED at the back */ +- led-rear-enc-fault0 { +- gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; +- }; +- +- /* PCIE slot power LED */ +- led-pcieslot-power { +- gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&gpio0 { +- gpio-line-names = +- /*A0-A7*/ "","","","","","","","", +- /*B0-B7*/ "USERSPACE_RSTIND_BUFF","","","","","","","", +- /*C0-C7*/ "","","","","","","","", +- /*D0-D7*/ "","","","","","","","", +- /*E0-E7*/ "","","","","","","","", +- /*F0-F7*/ "PIN_HOLE_RESET_IN_N","","", +- "PIN_HOLE_RESET_OUT_N","","","","", +- /*G0-G7*/ "","","","","","","","", +- /*H0-H7*/ "led-rtc-battery","led-bmc","led-rear-enc-id0","led-rear-enc-fault0","","","","", +- /*I0-I7*/ "","","","","","","","", +- /*J0-J7*/ "","","","","","","","", +- /*K0-K7*/ "","","","","","","","", +- /*L0-L7*/ "","","","","","","","", +- /*M0-M7*/ "","","","","","","","", +- /*N0-N7*/ "","","","","","","","", +- /*O0-O7*/ "","","","","","","","", +- /*P0-P7*/ "","","","","led-pcieslot-power","","","", +- /*Q0-Q7*/ "","","","","","","","", +- /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","I2C_FLASH_MICRO_N","","", +- /*S0-S7*/ "","","","","","","","", +- /*T0-T7*/ "","","","","","","","", +- /*U0-U7*/ "","","","","","","","", +- /*V0-V7*/ "","BMC_3RESTART_ATTEMPT_P","","","","","","", +- /*W0-W7*/ "","","","","","","","", +- /*X0-X7*/ "","","","","","","","", +- /*Y0-Y7*/ "","","","","","","","", +- /*Z0-Z7*/ "","","","","","","",""; +-}; +- +-&i2c0 { +- status = "okay"; +- +- eeprom@51 { +- compatible = "atmel,24c64"; +- reg = <0x51>; +- }; +- +- pca1: pca9552@62 { +- compatible = "nxp,pca9552"; +- reg = <0x62>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio-line-names = +- "presence-ps0", +- "presence-ps1", +- "presence-ps2", +- "presence-ps3", +- "presence-pdb", +- "presence-tpm", +- "", "", +- "presence-cp0", +- "presence-cp1", +- "presence-cp2", +- "presence-cp3", +- "presence-dasd", +- "presence-lcd-op", +- "presence-base-op", +- ""; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- +- gpio@8 { +- reg = <8>; +- type = ; +- }; +- +- gpio@9 { +- reg = <9>; +- type = ; +- }; +- +- gpio@10 { +- reg = <10>; +- type = ; +- }; +- +- gpio@11 { +- reg = <11>; +- type = ; +- }; +- +- gpio@12 { +- reg = <12>; +- type = ; +- }; +- +- gpio@13 { +- reg = <13>; +- type = ; +- }; +- +- gpio@14 { +- reg = <14>; +- type = ; +- }; +- +- gpio@15 { +- reg = <15>; +- type = ; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +- +- eeprom@54 { +- compatible = "atmel,24c128"; +- reg = <0x54>; +- }; +- +- power-supply@68 { +- compatible = "ibm,cffps"; +- reg = <0x68>; +- }; +- +- power-supply@69 { +- compatible = "ibm,cffps"; +- reg = <0x69>; +- }; +- +- power-supply@6b { +- compatible = "ibm,cffps"; +- reg = <0x6b>; +- }; +- +- power-supply@6d { +- compatible = "ibm,cffps"; +- reg = <0x6d>; +- }; +-}; +- +-&i2c4 { +- status = "okay"; +- +- pca2: pca9552@65 { +- compatible = "nxp,pca9552"; +- reg = <0x65>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio-line-names = +- "presence-cable-card1", +- "presence-cable-card2", +- "presence-cable-card3", +- "presence-cable-card4", +- "presence-cable-card5", +- "expander-cable-card1", +- "expander-cable-card2", +- "expander-cable-card3", +- "expander-cable-card4", +- "expander-cable-card5"; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- +- gpio@8 { +- reg = <8>; +- type = ; +- }; +- +- gpio@9 { +- reg = <9>; +- type = ; +- }; +- }; +- +- i2c-switch@70 { +- compatible = "nxp,pca9546"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- i2c-mux-idle-disconnect; +- +- i2c4mux0chn0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- eeprom@52 { +- compatible = "atmel,24c64"; +- reg = <0x52>; +- }; +- +- pca_cable_card_c01: pca9551@62 { +- compatible = "nxp,pca9551"; +- reg = <0x62>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- led@0 { +- label = "cablecard-c01-cxp-top"; +- reg = <0>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@1 { +- label = "cablecard-c01-cxp-bot"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +- }; +- +- i2c4mux0chn1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- +- pca_cable_card_c02: pca9551@60 { +- compatible = "nxp,pca9551"; +- reg = <0x60>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- led@0 { +- label = "cablecard-c02-cxp-top"; +- reg = <0>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@1 { +- label = "cablecard-c02-cxp-bot"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +- }; +- +- i2c4mux0chn2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- eeprom@51 { +- compatible = "atmel,24c64"; +- reg = <0x51>; +- }; +- +- pca_cable_card_c03: pca9551@61 { +- compatible = "nxp,pca9551"; +- reg = <0x61>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- led@0 { +- label = "cablecard-c03-cxp-top"; +- reg = <0>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@1 { +- label = "cablecard-c03-cxp-bot"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +- }; +- }; +-}; +- +-&i2c5 { +- status = "okay"; +- +- pca3: pca9552@66 { +- compatible = "nxp,pca9552"; +- reg = <0x66>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio-line-names = +- "presence-cable-card6", +- "presence-cable-card7", +- "presence-cable-card8", +- "presence-cable-card9", +- "presence-cable-card10", +- "presence-cable-card11", +- "expander-cable-card6", +- "expander-cable-card7", +- "expander-cable-card8", +- "expander-cable-card9", +- "expander-cable-card10", +- "expander-cable-card11"; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- +- gpio@8 { +- reg = <8>; +- type = ; +- }; +- +- gpio@9 { +- reg = <9>; +- type = ; +- }; +- +- gpio@10 { +- reg = <10>; +- type = ; +- }; +- +- gpio@11 { +- reg = <11>; +- type = ; +- }; +- +- }; +- +- i2c-switch@70 { +- compatible = "nxp,pca9546"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- i2c-mux-idle-disconnect; +- +- i2c5mux0chn0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- +- pca_cable_card_c04: pca9551@60 { +- compatible = "nxp,pca9551"; +- reg = <0x60>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- led@0 { +- label = "cablecard-c04-cxp-top"; +- reg = <0>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@1 { +- label = "cablecard-c04-cxp-bot"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +- }; +- +- i2c5mux0chn1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- eeprom@51 { +- compatible = "atmel,24c64"; +- reg = <0x51>; +- }; +- +- pca_cable_card_c05: pca9551@61 { +- compatible = "nxp,pca9551"; +- reg = <0x61>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- led@0 { +- label = "cablecard-c05-cxp-top"; +- reg = <0>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@1 { +- label = "cablecard-c05-cxp-bot"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +- }; +- +- i2c5mux0chn2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- eeprom@52 { +- compatible = "atmel,24c64"; +- reg = <0x52>; +- }; +- +- pca_cable_card_c06: pca9551@62 { +- compatible = "nxp,pca9551"; +- reg = <0x62>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- led@0 { +- label = "cablecard-c06-cxp-top"; +- reg = <0>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@1 { +- label = "cablecard-c06-cxp-bot"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +- }; +- +- i2c5mux0chn3: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- eeprom@53 { +- compatible = "atmel,24c64"; +- reg = <0x53>; +- }; +- +- pca_cable_card_c07: pca9551@63 { +- compatible = "nxp,pca9551"; +- reg = <0x63>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- led@0 { +- label = "cablecard-c07-cxp-top"; +- reg = <0>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@1 { +- label = "cablecard-c07-cxp-bot"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +- }; +- }; +-}; +- +-&i2c6 { +- status = "okay"; +- +- i2c-switch@70 { +- compatible = "nxp,pca9546"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- i2c-mux-idle-disconnect; +- +- i2c6mux0chn0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- +- pca_cable_card_c08: pca9551@60 { +- compatible = "nxp,pca9551"; +- reg = <0x60>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- led@0 { +- label = "cablecard-c08-cxp-top"; +- reg = <0>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@1 { +- label = "cablecard-c08-cxp-bot"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +- }; +- +- i2c6mux0chn1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- eeprom@52 { +- compatible = "atmel,24c64"; +- reg = <0x52>; +- }; +- +- pca_cable_card_c09: pca9551@62 { +- compatible = "nxp,pca9551"; +- reg = <0x62>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- led@0 { +- label = "cablecard-c09-cxp-top"; +- reg = <0>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@1 { +- label = "cablecard-c09-cxp-bot"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +- }; +- +- i2c6mux0chn2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- eeprom@53 { +- compatible = "atmel,24c64"; +- reg = <0x53>; +- }; +- +- pca_cable_card_c10: pca9551@63 { +- compatible = "nxp,pca9551"; +- reg = <0x63>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- led@0 { +- label = "cablecard-c10-cxp-top"; +- reg = <0>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@1 { +- label = "cablecard-c10-cxp-bot"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +- }; +- +- i2c6mux0chn3: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- eeprom@51 { +- compatible = "atmel,24c64"; +- reg = <0x51>; +- }; +- +- pca_cable_card_c11: pca9551@61 { +- compatible = "nxp,pca9551"; +- reg = <0x61>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- led@0 { +- label = "cablecard-c11-cxp-top"; +- reg = <0>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@1 { +- label = "cablecard-c11-cxp-bot"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +- }; +- }; +- +- pca_pcie_slot: pca9552@65 { +- compatible = "nxp,pca9552"; +- reg = <0x65>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- led@1 { +- label = "pcieslot-c01"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@2 { +- label = "pcieslot-c02"; +- reg = <2>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@3 { +- label = "pcieslot-c03"; +- reg = <3>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@4 { +- label = "pcieslot-c04"; +- reg = <4>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@5 { +- label = "pcieslot-c05"; +- reg = <5>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@6 { +- label = "pcieslot-c06"; +- reg = <6>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@7 { +- label = "pcieslot-c07"; +- reg = <7>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@8 { +- label = "pcieslot-c08"; +- reg = <8>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@9 { +- label = "pcieslot-c09"; +- reg = <9>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@10 { +- label = "pcieslot-c10"; +- reg = <10>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@11 { +- label = "pcieslot-c11"; +- reg = <11>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- gpio@12 { +- reg = <12>; +- type = ; +- }; +- +- gpio@13 { +- reg = <13>; +- type = ; +- }; +- +- gpio@14 { +- reg = <14>; +- type = ; +- }; +- +- gpio@15 { +- reg = <15>; +- type = ; +- }; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +- +- pic0_dimm: pca9552@31 { +- compatible = "ibm,pca9552"; +- reg = <0x31>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- led@0 { +- label = "ddimm0"; +- reg = <0>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@1 { +- label = "ddimm1"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@2 { +- label = "ddimm2"; +- reg = <2>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@3 { +- label = "ddimm3"; +- reg = <3>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@4 { +- label = "ddimm4"; +- reg = <4>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@5 { +- label = "ddimm5"; +- reg = <5>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@6 { +- label = "ddimm6"; +- reg = <6>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@7 { +- label = "ddimm7"; +- reg = <7>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@8 { +- label = "ddimm8"; +- reg = <8>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@9 { +- label = "ddimm9"; +- reg = <9>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@10 { +- label = "ddimm10"; +- reg = <10>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@11 { +- label = "ddimm11"; +- reg = <11>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@12 { +- label = "ddimm12"; +- reg = <12>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@13 { +- label = "ddimm13"; +- reg = <13>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@14 { +- label = "ddimm14"; +- reg = <14>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@15 { +- label = "ddimm15"; +- reg = <15>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- }; +- +- pic1_dimm: pca9552@32 { +- compatible = "ibm,pca9552"; +- reg = <0x32>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- led@0 { +- label = "ddimm16"; +- reg = <0>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@1 { +- label = "ddimm17"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@2 { +- label = "ddimm18"; +- reg = <2>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@3 { +- label = "ddimm19"; +- reg = <3>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@4 { +- label = "ddimm20"; +- reg = <4>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@5 { +- label = "ddimm21"; +- reg = <5>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@6 { +- label = "ddimm22"; +- reg = <6>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@7 { +- label = "ddimm23"; +- reg = <7>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@8 { +- label = "ddimm24"; +- reg = <8>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@9 { +- label = "ddimm25"; +- reg = <9>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@10 { +- label = "ddimm26"; +- reg = <10>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@11 { +- label = "ddimm27"; +- reg = <11>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@12 { +- label = "ddimm28"; +- reg = <12>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@13 { +- label = "ddimm29"; +- reg = <13>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@14 { +- label = "ddimm30"; +- reg = <14>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@15 { +- label = "ddimm31"; +- reg = <15>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- }; +- +- pic2_dimm: pca9552@33 { +- compatible = "ibm,pca9552"; +- reg = <0x33>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- led@0 { +- label = "ddimm32"; +- reg = <0>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@1 { +- label = "ddimm33"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@2 { +- label = "ddimm34"; +- reg = <2>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@3 { +- label = "ddimm35"; +- reg = <3>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@4 { +- label = "ddimm36"; +- reg = <4>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@5 { +- label = "ddimm37"; +- reg = <5>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@6 { +- label = "ddimm38"; +- reg = <6>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@7 { +- label = "ddimm39"; +- reg = <7>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@8 { +- label = "ddimm40"; +- reg = <8>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@9 { +- label = "ddimm41"; +- reg = <9>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@10 { +- label = "ddimm42"; +- reg = <10>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@11 { +- label = "ddimm43"; +- reg = <11>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@12 { +- label = "ddimm44"; +- reg = <12>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@13 { +- label = "ddimm45"; +- reg = <13>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@14 { +- label = "ddimm46"; +- reg = <14>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@15 { +- label = "ddimm47"; +- reg = <15>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- }; +- +- pic3_dimm: pca9552@30 { +- compatible = "ibm,pca9552"; +- reg = <0x30>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- led@0 { +- label = "ddimm48"; +- reg = <0>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@1 { +- label = "ddimm49"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@2 { +- label = "ddimm50"; +- reg = <2>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@3 { +- label = "ddimm51"; +- reg = <3>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@4 { +- label = "ddimm52"; +- reg = <4>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@5 { +- label = "ddimm53"; +- reg = <5>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@6 { +- label = "ddimm54"; +- reg = <6>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@7 { +- label = "ddimm55"; +- reg = <7>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@8 { +- label = "ddimm56"; +- reg = <8>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@9 { +- label = "ddimm57"; +- reg = <9>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@10 { +- label = "ddimm58"; +- reg = <10>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@11 { +- label = "ddimm59"; +- reg = <11>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@12 { +- label = "ddimm60"; +- reg = <12>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@13 { +- label = "ddimm61"; +- reg = <13>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@14 { +- label = "ddimm62"; +- reg = <14>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@15 { +- label = "ddimm63"; +- reg = <15>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- }; +- +- pic0_vrm_misc: pca9552@34 { +- compatible = "ibm,pca9552"; +- reg = <0x34>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- led@0 { +- label = "planar"; +- reg = <0>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@1 { +- label = "tpm"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@2 { +- label = "cpu3-c61"; +- reg = <2>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@3 { +- label = "cpu0-c14"; +- reg = <3>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@4 { +- label = "opencapi-connector3"; +- reg = <4>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@5 { +- label = "opencapi-connector4"; +- reg = <5>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@6 { +- label = "opencapi-connector5"; +- reg = <6>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- +- led@8 { +- label = "vrm4"; +- reg = <8>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@9 { +- label = "vrm5"; +- reg = <9>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@10 { +- label = "vrm6"; +- reg = <10>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@11 { +- label = "vrm7"; +- reg = <11>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@12 { +- label = "vrm12"; +- reg = <12>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@13 { +- label = "vrm13"; +- reg = <13>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@14 { +- label = "vrm14"; +- reg = <14>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@15 { +- label = "vrm15"; +- reg = <15>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- }; +- +- pic1_vrm_misc: pca9552@35 { +- compatible = "ibm,pca9552"; +- reg = <0x35>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- led@0 { +- label = "dasd-backplane"; +- reg = <0>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@1 { +- label = "power-distribution"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@2 { +- label = "cpu1-c19"; +- reg = <2>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@3 { +- label = "cpu2-c56"; +- reg = <3>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@4 { +- label = "opencapi-connector0"; +- reg = <4>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@5 { +- label = "opencapi-connector1"; +- reg = <5>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@6 { +- label = "opencapi-connector2"; +- reg = <6>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- +- led@8 { +- label = "vrm0"; +- reg = <8>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@9 { +- label = "vrm1"; +- reg = <9>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@10 { +- label = "vrm2"; +- reg = <10>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@11 { +- label = "vrm3"; +- reg = <11>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@12 { +- label = "vrm8"; +- reg = <12>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@13 { +- label = "vrm9"; +- reg = <13>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@14 { +- label = "vrm10"; +- reg = <14>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@15 { +- label = "vrm11"; +- reg = <15>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- }; +-}; +- +-&i2c8 { +- status = "okay"; +- +- ucd90320@11 { +- compatible = "ti,ucd90320"; +- reg = <0x11>; +- }; +- +- rtc@32 { +- compatible = "epson,rx8900"; +- reg = <0x32>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c64"; +- reg = <0x51>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c128"; +- reg = <0x50>; +- }; +-}; +- +-&i2c9 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c128"; +- reg = <0x50>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c128"; +- reg = <0x51>; +- }; +- +- eeprom@53 { +- compatible = "atmel,24c128"; +- reg = <0x53>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c128"; +- reg = <0x52>; +- }; +-}; +- +-&i2c10 { +- status = "okay"; +- +- eeprom@51 { +- compatible = "atmel,24c128"; +- reg = <0x51>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c128"; +- reg = <0x50>; +- }; +- +- eeprom@53 { +- compatible = "atmel,24c128"; +- reg = <0x53>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c128"; +- reg = <0x52>; +- }; +-}; +- +-&i2c11 { +- status = "okay"; +- +- eeprom@51 { +- compatible = "atmel,24c128"; +- reg = <0x51>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c128"; +- reg = <0x50>; +- }; +- +- eeprom@53 { +- compatible = "atmel,24c128"; +- reg = <0x53>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c128"; +- reg = <0x52>; +- }; +-}; +- +-&i2c12 { +- status = "okay"; +-}; +- +-&i2c13 { +- status = "okay"; +- +- eeprom@51 { +- compatible = "atmel,24c128"; +- reg = <0x51>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c128"; +- reg = <0x50>; +- }; +- +- eeprom@53 { +- compatible = "atmel,24c128"; +- reg = <0x53>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c128"; +- reg = <0x52>; +- }; +-}; +- +-&i2c14 { +- status = "okay"; +- +- i2c-switch@70 { +- compatible = "nxp,pca9546"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- i2c-mux-idle-disconnect; +- +- i2c14mux0chn0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- }; +- +- i2c14mux0chn1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- eeprom@51 { +- compatible = "atmel,24c32"; +- reg = <0x51>; +- }; +- }; +- +- i2c14mux0chn2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- eeprom@50 { +- compatible = "atmel,24c32"; +- reg = <0x50>; +- }; +- +- pca_oppanel: pca9551@60 { +- compatible = "nxp,pca9551"; +- reg = <0x60>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- led@0 { +- label = "front-sys-id0"; +- reg = <0>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@1 { +- label = "front-check-log0"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@2 { +- label = "front-enc-fault1"; +- reg = <2>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@3 { +- label = "front-sys-pwron0"; +- reg = <3>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- }; +- }; +- +- i2c14mux0chn3: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- max31785@52 { +- compatible = "maxim,max31785a"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x52>; +- +- fan@0 { +- compatible = "pmbus-fan"; +- reg = <0>; +- tach-pulses = <2>; +- }; +- +- fan@1 { +- compatible = "pmbus-fan"; +- reg = <1>; +- tach-pulses = <2>; +- }; +- +- fan@2 { +- compatible = "pmbus-fan"; +- reg = <2>; +- tach-pulses = <2>; +- }; +- +- fan@3 { +- compatible = "pmbus-fan"; +- reg = <3>; +- tach-pulses = <2>; +- }; +- }; +- +- pca_fan_nvme: pca9552@60 { +- compatible = "nxp,pca9552"; +- reg = <0x60>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- led@0 { +- label = "nvme0"; +- reg = <0>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@1 { +- label = "nvme1"; +- reg = <1>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@2 { +- label = "nvme2"; +- reg = <2>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@3 { +- label = "nvme3"; +- reg = <3>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@4 { +- label = "nvme4"; +- reg = <4>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@5 { +- label = "nvme5"; +- reg = <5>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@6 { +- label = "nvme6"; +- reg = <6>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@7 { +- label = "nvme7"; +- reg = <7>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@8 { +- label = "nvme8"; +- reg = <8>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@9 { +- label = "nvme9"; +- reg = <9>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@10 { +- label = "fan0"; +- reg = <10>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@11 { +- label = "fan1"; +- reg = <11>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@12 { +- label = "fan2"; +- reg = <12>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- led@13 { +- label = "fan3"; +- reg = <13>; +- retain-state-shutdown; +- default-state = "keep"; +- type = ; +- }; +- +- gpio@14 { +- reg = <14>; +- type = ; +- }; +- +- gpio@15 { +- reg = <15>; +- type = ; +- }; +- }; +- +- pca0: pca9552@61 { +- compatible = "nxp,pca9552"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x61>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio-line-names = +- "","","","", +- "","","","", +- "","","","", +- "presence-fan3", +- "presence-fan2", +- "presence-fan1", +- "presence-fan0"; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- +- gpio@8 { +- reg = <8>; +- type = ; +- }; +- +- gpio@9 { +- reg = <9>; +- type = ; +- }; +- +- gpio@10 { +- reg = <10>; +- type = ; +- }; +- +- gpio@11 { +- reg = <11>; +- type = ; +- }; +- +- gpio@12 { +- reg = <12>; +- type = ; +- }; +- +- gpio@13 { +- reg = <13>; +- type = ; +- }; +- +- gpio@14 { +- reg = <14>; +- type = ; +- }; +- +- gpio@15 { +- reg = <15>; +- type = ; +- }; +- }; +- }; +- }; +- +- i2c-switch@71 { +- compatible = "nxp,pca9546"; +- reg = <0x71>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- i2c-mux-idle-disconnect; +- +- i2c14mux1chn0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- eeprom@50 { +- compatible = "atmel,24c32"; +- reg = <0x50>; +- }; +- }; +- +- i2c14mux1chn1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- eeprom@50 { +- compatible = "atmel,24c32"; +- reg = <0x50>; +- }; +- }; +- +- i2c14mux1chn2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- eeprom@50 { +- compatible = "atmel,24c32"; +- reg = <0x50>; +- }; +- }; +- +- i2c14mux1chn3: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- eeprom@50 { +- compatible = "atmel,24c32"; +- reg = <0x50>; +- }; +- }; +- }; +-}; +- +-&i2c15 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emmc_controller { +- status = "okay"; +-}; +- +-&pinctrl_emmc_default { +- bias-disable; +-}; +- +-&emmc { +- status = "okay"; +- clk-phase-mmc-hs200 = <210>, <228>; +-}; +- +-&fsim0 { +- status = "okay"; +- +- #address-cells = <2>; +- #size-cells = <0>; +- +- /* +- * CFAM Reset is supposed to be active low but pass1 hardware is wired +- * active high. +- */ +- cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; +- +- cfam@0,0 { /* DCM0_C0 */ +- reg = <0 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- chip-id = <0>; +- +- scom@1000 { +- compatible = "ibm,fsi2pib"; +- reg = <0x1000 0x400>; +- }; +- +- i2c@1800 { +- compatible = "ibm,fsi-i2c-master"; +- reg = <0x1800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam0_i2c0: i2c-bus@0 { +- reg = <0>; /* OMI01 */ +- }; +- +- cfam0_i2c1: i2c-bus@1 { +- reg = <1>; /* OMI23 */ +- }; +- +- cfam0_i2c10: i2c-bus@a { +- reg = <10>; /* OP3A */ +- }; +- +- cfam0_i2c11: i2c-bus@b { +- reg = <11>; /* OP3B */ +- }; +- +- cfam0_i2c12: i2c-bus@c { +- reg = <12>; /* OP4A */ +- }; +- +- cfam0_i2c13: i2c-bus@d { +- reg = <13>; /* OP4B */ +- }; +- +- cfam0_i2c14: i2c-bus@e { +- reg = <14>; /* OP5A */ +- }; +- +- cfam0_i2c15: i2c-bus@f { +- reg = <15>; /* OP5B */ +- }; +- }; +- +- fsi2spi@1c00 { +- compatible = "ibm,fsi2spi"; +- reg = <0x1c00 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam0_spi0: spi@0 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam0_spi1: spi@20 { +- reg = <0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam0_spi2: spi@40 { +- reg = <0x40>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam0_spi3: spi@60 { +- reg = <0x60>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- }; +- +- sbefifo@2400 { +- compatible = "ibm,p9-sbefifo"; +- reg = <0x2400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fsi_occ0: occ { +- compatible = "ibm,p10-occ"; +- }; +- }; +- +- fsi_hub0: hub@3400 { +- compatible = "fsi-master-hub"; +- reg = <0x3400 0x400>; +- #address-cells = <2>; +- #size-cells = <0>; +- }; +- }; +-}; +- +-&fsi_hub0 { +- cfam@1,0 { /* DCM0_C1 */ +- reg = <1 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- chip-id = <1>; +- +- scom@1000 { +- compatible = "ibm,fsi2pib"; +- reg = <0x1000 0x400>; +- }; +- +- i2c@1800 { +- compatible = "ibm,fsi-i2c-master"; +- reg = <0x1800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam1_i2c2: i2c-bus@2 { +- reg = <2>; /* OMI45 */ +- }; +- +- cfam1_i2c3: i2c-bus@3 { +- reg = <3>; /* OMI67 */ +- }; +- +- cfam1_i2c10: i2c-bus@a { +- reg = <10>; /* OP3A */ +- }; +- +- cfam1_i2c11: i2c-bus@b { +- reg = <11>; /* OP3B */ +- }; +- +- cfam1_i2c14: i2c-bus@e { +- reg = <14>; /* OP5A */ +- }; +- +- cfam1_i2c15: i2c-bus@f { +- reg = <15>; /* OP5B */ +- }; +- +- cfam1_i2c16: i2c-bus@10 { +- reg = <16>; /* OP6A */ +- }; +- +- cfam1_i2c17: i2c-bus@11 { +- reg = <17>; /* OP6B */ +- }; +- }; +- +- fsi2spi@1c00 { +- compatible = "ibm,fsi2spi"; +- reg = <0x1c00 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam1_spi0: spi@0 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam1_spi1: spi@20 { +- reg = <0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam1_spi2: spi@40 { +- reg = <0x40>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam1_spi3: spi@60 { +- reg = <0x60>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- }; +- +- sbefifo@2400 { +- compatible = "ibm,p9-sbefifo"; +- reg = <0x2400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fsi_occ1: occ { +- compatible = "ibm,p10-occ"; +- }; +- }; +- +- fsi_hub1: hub@3400 { +- compatible = "fsi-master-hub"; +- reg = <0x3400 0x400>; +- #address-cells = <2>; +- #size-cells = <0>; +- +- no-scan-on-init; +- }; +- }; +- +- cfam@2,0 { /* DCM1_C0 */ +- reg = <2 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- chip-id = <2>; +- +- scom@1000 { +- compatible = "ibm,fsi2pib"; +- reg = <0x1000 0x400>; +- }; +- +- i2c@1800 { +- compatible = "ibm,fsi-i2c-master"; +- reg = <0x1800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam2_i2c0: i2c-bus@0 { +- reg = <0>; /* OM01 */ +- }; +- +- cfam2_i2c1: i2c-bus@1 { +- reg = <1>; /* OM23 */ +- }; +- +- cfam2_i2c10: i2c-bus@a { +- reg = <10>; /* OP3A */ +- }; +- +- cfam2_i2c11: i2c-bus@b { +- reg = <11>; /* OP3B */ +- }; +- +- cfam2_i2c12: i2c-bus@c { +- reg = <12>; /* OP4A */ +- }; +- +- cfam2_i2c13: i2c-bus@d { +- reg = <13>; /* OP4B */ +- }; +- +- cfam2_i2c14: i2c-bus@e { +- reg = <14>; /* OP5A */ +- }; +- +- cfam2_i2c15: i2c-bus@f { +- reg = <15>; /* OP5B */ +- }; +- }; +- +- fsi2spi@1c00 { +- compatible = "ibm,fsi2spi"; +- reg = <0x1c00 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam2_spi0: spi@0 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam2_spi1: spi@20 { +- reg = <0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam2_spi2: spi@40 { +- reg = <0x40>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam2_spi3: spi@60 { +- reg = <0x60>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- }; +- +- sbefifo@2400 { +- compatible = "ibm,p9-sbefifo"; +- reg = <0x2400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fsi_occ2: occ { +- compatible = "ibm,p10-occ"; +- }; +- }; +- +- fsi_hub2: hub@3400 { +- compatible = "fsi-master-hub"; +- reg = <0x3400 0x400>; +- #address-cells = <2>; +- #size-cells = <0>; +- +- no-scan-on-init; +- }; +- }; +- +- cfam@3,0 { /* DCM1_C1 */ +- reg = <3 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- chip-id = <3>; +- +- scom@1000 { +- compatible = "ibm,fsi2pib"; +- reg = <0x1000 0x400>; +- }; +- +- i2c@1800 { +- compatible = "ibm,fsi-i2c-master"; +- reg = <0x1800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam3_i2c2: i2c-bus@2 { +- reg = <2>; /* OM45 */ +- }; +- +- cfam3_i2c3: i2c-bus@3 { +- reg = <3>; /* OM67 */ +- }; +- +- cfam3_i2c10: i2c-bus@a { +- reg = <10>; /* OP3A */ +- }; +- +- cfam3_i2c11: i2c-bus@b { +- reg = <11>; /* OP3B */ +- }; +- +- cfam3_i2c14: i2c-bus@e { +- reg = <14>; /* OP5A */ +- }; +- +- cfam3_i2c15: i2c-bus@f { +- reg = <15>; /* OP5B */ +- }; +- +- cfam3_i2c16: i2c-bus@10 { +- reg = <16>; /* OP6A */ +- }; +- +- cfam3_i2c17: i2c-bus@11 { +- reg = <17>; /* OP6B */ +- }; +- }; +- +- fsi2spi@1c00 { +- compatible = "ibm,fsi2spi"; +- reg = <0x1c00 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam3_spi0: spi@0 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam3_spi1: spi@20 { +- reg = <0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam3_spi2: spi@40 { +- reg = <0x40>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam3_spi3: spi@60 { +- reg = <0x60>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- }; +- +- sbefifo@2400 { +- compatible = "ibm,p9-sbefifo"; +- reg = <0x2400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fsi_occ3: occ { +- compatible = "ibm,p10-occ"; +- }; +- }; +- +- fsi_hub3: hub@3400 { +- compatible = "fsi-master-hub"; +- reg = <0x3400 0x400>; +- #address-cells = <2>; +- #size-cells = <0>; +- +- no-scan-on-init; +- }; +- }; +- +- cfam@4,0 { /* DCM2_C0 */ +- reg = <4 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- chip-id = <4>; +- +- scom@1000 { +- compatible = "ibm,fsi2pib"; +- reg = <0x1000 0x400>; +- }; +- +- i2c@1800 { +- compatible = "ibm,fsi-i2c-master"; +- reg = <0x1800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam4_i2c0: i2c-bus@0 { +- reg = <0>; /* OM01 */ +- }; +- +- cfam4_i2c1: i2c-bus@1 { +- reg = <1>; /* OM23 */ +- }; +- +- cfam4_i2c10: i2c-bus@a { +- reg = <10>; /* OP3A */ +- }; +- +- cfam4_i2c11: i2c-bus@b { +- reg = <11>; /* OP3B */ +- }; +- +- cfam4_i2c12: i2c-bus@c { +- reg = <12>; /* OP4A */ +- }; +- +- cfam4_i2c13: i2c-bus@d { +- reg = <13>; /* OP4B */ +- }; +- +- cfam4_i2c14: i2c-bus@e { +- reg = <14>; /* OP5A */ +- }; +- +- cfam4_i2c15: i2c-bus@f { +- reg = <15>; /* OP5B */ +- }; +- }; +- +- fsi2spi@1c00 { +- compatible = "ibm,fsi2spi"; +- reg = <0x1c00 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam4_spi0: spi@0 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam4_spi1: spi@20 { +- reg = <0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam4_spi2: spi@40 { +- reg = <0x40>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam4_spi3: spi@60 { +- reg = <0x60>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- }; +- +- sbefifo@2400 { +- compatible = "ibm,p9-sbefifo"; +- reg = <0x2400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fsi_occ4: occ { +- compatible = "ibm,p10-occ"; +- }; +- }; +- +- fsi_hub4: hub@3400 { +- compatible = "fsi-master-hub"; +- reg = <0x3400 0x400>; +- #address-cells = <2>; +- #size-cells = <0>; +- +- no-scan-on-init; +- }; +- }; +- +- cfam@5,0 { /* DCM2_C1 */ +- reg = <5 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- chip-id = <5>; +- +- scom@1000 { +- compatible = "ibm,fsi2pib"; +- reg = <0x1000 0x400>; +- }; +- +- i2c@1800 { +- compatible = "ibm,fsi-i2c-master"; +- reg = <0x1800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam5_i2c2: i2c-bus@2 { +- reg = <2>; /* OM45 */ +- }; +- +- cfam5_i2c3: i2c-bus@3 { +- reg = <3>; /* OM67 */ +- }; +- +- cfam5_i2c10: i2c-bus@a { +- reg = <10>; /* OP3A */ +- }; +- +- cfam5_i2c11: i2c-bus@b { +- reg = <11>; /* OP3B */ +- }; +- +- cfam5_i2c14: i2c-bus@e { +- reg = <14>; /* OP5A */ +- }; +- +- cfam5_i2c15: i2c-bus@f { +- reg = <15>; /* OP5B */ +- }; +- +- cfam5_i2c16: i2c-bus@10 { +- reg = <16>; /* OP6A */ +- }; +- +- cfam5_i2c17: i2c-bus@11 { +- reg = <17>; /* OP6B */ +- }; +- }; +- +- fsi2spi@1c00 { +- compatible = "ibm,fsi2spi"; +- reg = <0x1c00 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam5_spi0: spi@0 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam5_spi1: spi@20 { +- reg = <0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam5_spi2: spi@40 { +- reg = <0x40>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam5_spi3: spi@60 { +- reg = <0x60>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- }; +- +- sbefifo@2400 { +- compatible = "ibm,p9-sbefifo"; +- reg = <0x2400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fsi_occ5: occ { +- compatible = "ibm,p10-occ"; +- }; +- }; +- +- fsi_hub5: hub@3400 { +- compatible = "fsi-master-hub"; +- reg = <0x3400 0x400>; +- #address-cells = <2>; +- #size-cells = <0>; +- +- no-scan-on-init; +- }; +- }; +- +- cfam@6,0 { /* DCM3_C0 */ +- reg = <6 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- chip-id = <6>; +- +- scom@1000 { +- compatible = "ibm,fsi2pib"; +- reg = <0x1000 0x400>; +- }; +- +- i2c@1800 { +- compatible = "ibm,fsi-i2c-master"; +- reg = <0x1800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam6_i2c0: i2c-bus@0 { +- reg = <0>; /* OM01 */ +- }; +- +- cfam6_i2c1: i2c-bus@1 { +- reg = <1>; /* OM23 */ +- }; +- +- cfam6_i2c10: i2c-bus@a { +- reg = <10>; /* OP3A */ +- }; +- +- cfam6_i2c11: i2c-bus@b { +- reg = <11>; /* OP3B */ +- }; +- +- cfam6_i2c12: i2c-bus@c { +- reg = <12>; /* OP4A */ +- }; +- +- cfam6_i2c13: i2c-bus@d { +- reg = <13>; /* OP4B */ +- }; +- +- cfam6_i2c14: i2c-bus@e { +- reg = <14>; /* OP5A */ +- }; +- +- cfam6_i2c15: i2c-bus@f { +- reg = <15>; /* OP5B */ +- }; +- }; +- +- fsi2spi@1c00 { +- compatible = "ibm,fsi2spi"; +- reg = <0x1c00 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam6_spi0: spi@0 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam6_spi1: spi@20 { +- reg = <0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam6_spi2: spi@40 { +- reg = <0x40>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam6_spi3: spi@60 { +- reg = <0x60>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- }; +- +- sbefifo@2400 { +- compatible = "ibm,p9-sbefifo"; +- reg = <0x2400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fsi_occ6: occ { +- compatible = "ibm,p10-occ"; +- }; +- }; +- +- fsi_hub6: hub@3400 { +- compatible = "fsi-master-hub"; +- reg = <0x3400 0x400>; +- #address-cells = <2>; +- #size-cells = <0>; +- +- no-scan-on-init; +- }; +- }; +- +- cfam@7,0 { /* DCM3_C1 */ +- reg = <7 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- chip-id = <7>; +- +- scom@1000 { +- compatible = "ibm,fsi2pib"; +- reg = <0x1000 0x400>; +- }; +- +- i2c@1800 { +- compatible = "ibm,fsi-i2c-master"; +- reg = <0x1800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam7_i2c2: i2c-bus@2 { +- reg = <2>; /* OM45 */ +- }; +- +- cfam7_i2c3: i2c-bus@3 { +- reg = <3>; /* OM67 */ +- }; +- +- cfam7_i2c10: i2c-bus@a { +- reg = <10>; /* OP3A */ +- }; +- +- cfam7_i2c11: i2c-bus@b { +- reg = <11>; /* OP3B */ +- }; +- +- cfam7_i2c14: i2c-bus@e { +- reg = <14>; /* OP5A */ +- }; +- +- cfam7_i2c15: i2c-bus@f { +- reg = <15>; /* OP5B */ +- }; +- +- cfam7_i2c16: i2c-bus@10 { +- reg = <16>; /* OP6A */ +- }; +- +- cfam7_i2c17: i2c-bus@11 { +- reg = <17>; /* OP6B */ +- }; +- }; +- +- fsi2spi@1c00 { +- compatible = "ibm,fsi2spi"; +- reg = <0x1c00 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam7_spi0: spi@0 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam7_spi1: spi@20 { +- reg = <0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam7_spi2: spi@40 { +- reg = <0x40>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam7_spi3: spi@60 { +- reg = <0x60>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- }; +- +- sbefifo@2400 { +- compatible = "ibm,p9-sbefifo"; +- reg = <0x2400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fsi_occ7: occ { +- compatible = "ibm,p10-occ"; +- }; +- }; +- +- fsi_hub7: hub@3400 { +- compatible = "fsi-master-hub"; +- reg = <0x3400 0x400>; +- #address-cells = <2>; +- #size-cells = <0>; +- +- no-scan-on-init; +- }; +- }; +-}; +- +-/* Legacy OCC numbering (to get rid of when userspace is fixed) */ +-&fsi_occ0 { +- reg = <1>; +-}; +- +-&fsi_occ1 { +- reg = <2>; +-}; +- +-&fsi_occ2 { +- reg = <3>; +-}; +- +-&fsi_occ3 { +- reg = <4>; +-}; +- +-&fsi_occ4 { +- reg = <5>; +-}; +- +-&fsi_occ5 { +- reg = <6>; +-}; +- +-&fsi_occ6 { +- reg = <7>; +-}; +- +-&fsi_occ7 { +- reg = <8>; +-}; +- +-&ibt { +- status = "okay"; +-}; +- +-&vuart1 { +- status = "okay"; +-}; +- +-&vuart2 { +- status = "okay"; +-}; +- +-&lpc_ctrl { +- status = "okay"; +- memory-region = <&flash_memory>; +-}; +- +-&kcs4 { +- compatible = "openbmc,mctp-lpc"; +- status = "okay"; +-}; +- +-&mac2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii3_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, +- <&syscon ASPEED_CLK_MAC3RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&mac3 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii4_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>, +- <&syscon ASPEED_CLK_MAC4RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&wdt1 { +- aspeed,reset-type = "none"; +- aspeed,external-signal; +- aspeed,ext-push-pull; +- aspeed,ext-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdtrst1_default>; +-}; +- +-&wdt2 { +- status = "okay"; +-}; +- +-&xdma { +- status = "okay"; +- memory-region = <&vga_memory>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-ibm-rainier-1s4u.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-ibm-rainier-1s4u.dts +deleted file mode 100644 +index f5f5b18c113a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-ibm-rainier-1s4u.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-// Copyright 2021 IBM Corp. +-/dts-v1/; +- +-#include "aspeed-bmc-ibm-rainier-4u.dts" +- +-/ { +- model = "Rainier 1S4U"; +-}; +- +-&max { +- /delete-node/ fan3; +- /delete-node/ fan5; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-ibm-rainier-4u.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-ibm-rainier-4u.dts +deleted file mode 100644 +index 342546a3c0f5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-ibm-rainier-4u.dts ++++ /dev/null +@@ -1,21 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-// Copyright 2020 IBM Corp. +-/dts-v1/; +- +-#include "aspeed-bmc-ibm-rainier.dts" +- +-/ { +- model = "Rainier 4U"; +-}; +- +-&i2c3 { +- power-supply@6a { +- compatible = "ibm,cffps"; +- reg = <0x6a>; +- }; +- +- power-supply@6b { +- compatible = "ibm,cffps"; +- reg = <0x6b>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-ibm-rainier.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-ibm-rainier.dts +deleted file mode 100644 +index 6419c9762c0b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-ibm-rainier.dts ++++ /dev/null +@@ -1,1779 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-// Copyright 2019 IBM Corp. +-/dts-v1/; +- +-#include "aspeed-g6.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "Rainier 2U"; +- compatible = "ibm,rainier-bmc", "aspeed,ast2600"; +- +- aliases { +- i2c100 = &cfam0_i2c0; +- i2c101 = &cfam0_i2c1; +- i2c110 = &cfam0_i2c10; +- i2c111 = &cfam0_i2c11; +- i2c112 = &cfam0_i2c12; +- i2c113 = &cfam0_i2c13; +- i2c114 = &cfam0_i2c14; +- i2c115 = &cfam0_i2c15; +- i2c202 = &cfam1_i2c2; +- i2c203 = &cfam1_i2c3; +- i2c210 = &cfam1_i2c10; +- i2c211 = &cfam1_i2c11; +- i2c214 = &cfam1_i2c14; +- i2c215 = &cfam1_i2c15; +- i2c216 = &cfam1_i2c16; +- i2c217 = &cfam1_i2c17; +- i2c300 = &cfam2_i2c0; +- i2c301 = &cfam2_i2c1; +- i2c310 = &cfam2_i2c10; +- i2c311 = &cfam2_i2c11; +- i2c312 = &cfam2_i2c12; +- i2c313 = &cfam2_i2c13; +- i2c314 = &cfam2_i2c14; +- i2c315 = &cfam2_i2c15; +- i2c402 = &cfam3_i2c2; +- i2c403 = &cfam3_i2c3; +- i2c410 = &cfam3_i2c10; +- i2c411 = &cfam3_i2c11; +- i2c414 = &cfam3_i2c14; +- i2c415 = &cfam3_i2c15; +- i2c416 = &cfam3_i2c16; +- i2c417 = &cfam3_i2c17; +- +- serial4 = &uart5; +- i2c16 = &i2c2mux0; +- i2c17 = &i2c2mux1; +- i2c18 = &i2c2mux2; +- i2c19 = &i2c2mux3; +- i2c20 = &i2c4mux0chn0; +- i2c21 = &i2c4mux0chn1; +- i2c22 = &i2c4mux0chn2; +- i2c23 = &i2c5mux0chn0; +- i2c24 = &i2c5mux0chn1; +- i2c25 = &i2c6mux0chn0; +- i2c26 = &i2c6mux0chn1; +- i2c27 = &i2c6mux0chn2; +- i2c28 = &i2c6mux0chn3; +- i2c29 = &i2c11mux0chn0; +- i2c30 = &i2c11mux0chn1; +- +- spi10 = &cfam0_spi0; +- spi11 = &cfam0_spi1; +- spi12 = &cfam0_spi2; +- spi13 = &cfam0_spi3; +- spi20 = &cfam1_spi0; +- spi21 = &cfam1_spi1; +- spi22 = &cfam1_spi2; +- spi23 = &cfam1_spi3; +- spi30 = &cfam2_spi0; +- spi31 = &cfam2_spi1; +- spi32 = &cfam2_spi2; +- spi33 = &cfam2_spi3; +- spi40 = &cfam3_spi0; +- spi41 = &cfam3_spi1; +- spi42 = &cfam3_spi2; +- spi43 = &cfam3_spi3; +- }; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200n8"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- flash_memory: region@b8000000 { +- no-map; +- reg = <0xb8000000 0x04000000>; /* 64M */ +- }; +- +- ramoops@bc000000 { +- compatible = "ramoops"; +- reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */ +- record-size = <0x8000>; +- console-size = <0x8000>; +- pmsg-size = <0x8000>; +- max-reason = <3>; /* KMSG_DUMP_EMERG */ +- }; +- +- vga_memory: region@bf000000 { +- no-map; +- compatible = "shared-dma-pool"; +- reg = <0xbf000000 0x01000000>; /* 16M */ +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- ps0-presence { +- label = "ps0-presence"; +- gpios = <&gpio0 ASPEED_GPIO(S, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- ps1-presence { +- label = "ps1-presence"; +- gpios = <&gpio0 ASPEED_GPIO(S, 1) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- ps2-presence { +- label = "ps2-presence"; +- gpios = <&gpio0 ASPEED_GPIO(S, 2) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- ps3-presence { +- label = "ps3-presence"; +- gpios = <&gpio0 ASPEED_GPIO(S, 3) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- i2c2mux: i2cmux { +- compatible = "i2c-mux-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- i2c-parent = <&i2c2>; +- mux-gpios = <&gpio0 ASPEED_GPIO(G, 4) GPIO_ACTIVE_HIGH>, +- <&gpio0 ASPEED_GPIO(G, 5) GPIO_ACTIVE_HIGH>; +- idle-state = <0>; +- +- i2c2mux0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c2mux1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- i2c2mux2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c2mux3: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- /* BMC Card fault LED at the back */ +- bmc-ingraham0 { +- gpios = <&gpio0 ASPEED_GPIO(H, 1) GPIO_ACTIVE_LOW>; +- }; +- +- /* Enclosure ID LED at the back */ +- rear-enc-id0 { +- gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; +- }; +- +- /* Enclosure fault LED at the back */ +- rear-enc-fault0 { +- gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; +- }; +- +- /* PCIE slot power LED */ +- pcieslot-power { +- gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- #address-cells = <1>; +- #size-cells = <0>; +- poll-interval = <1000>; +- +- fan0-presence { +- label = "fan0-presence"; +- gpios = <&pca0 6 GPIO_ACTIVE_LOW>; +- linux,code = <6>; +- }; +- +- fan1-presence { +- label = "fan1-presence"; +- gpios = <&pca0 7 GPIO_ACTIVE_LOW>; +- linux,code = <7>; +- }; +- +- fan2-presence { +- label = "fan2-presence"; +- gpios = <&pca0 8 GPIO_ACTIVE_LOW>; +- linux,code = <8>; +- }; +- +- fan3-presence { +- label = "fan3-presence"; +- gpios = <&pca0 9 GPIO_ACTIVE_LOW>; +- linux,code = <9>; +- }; +- +- fan4-presence { +- label = "fan4-presence"; +- gpios = <&pca0 10 GPIO_ACTIVE_LOW>; +- linux,code = <10>; +- }; +- +- fan5-presence { +- label = "fan5-presence"; +- gpios = <&pca0 11 GPIO_ACTIVE_LOW>; +- linux,code = <11>; +- }; +- }; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gpio0 { +- gpio-line-names = +- /*A0-A7*/ "","","","","","","","", +- /*B0-B7*/ "","","","","","","checkstop","", +- /*C0-C7*/ "","","","","","","","", +- /*D0-D7*/ "","","","","","","","", +- /*E0-E7*/ "","","","","","","","", +- /*F0-F7*/ "","","","","","","","", +- /*G0-G7*/ "","","","","","","","", +- /*H0-H7*/ "","bmc-ingraham0","rear-enc-id0","rear-enc-fault0","","","","", +- /*I0-I7*/ "","","","","","","","", +- /*J0-J7*/ "","","","","","","","", +- /*K0-K7*/ "","","","","","","","", +- /*L0-L7*/ "","","","","","","","", +- /*M0-M7*/ "","","","","","","","", +- /*N0-N7*/ "","","","","","","","", +- /*O0-O7*/ "","","","usb-power","","","","", +- /*P0-P7*/ "","","","","pcieslot-power","","","", +- /*Q0-Q7*/ "cfam-reset","","","","","","","", +- /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","","","", +- /*S0-S7*/ "presence-ps0","presence-ps1","presence-ps2","presence-ps3", +- "","","","", +- /*T0-T7*/ "","","","","","","","", +- /*U0-U7*/ "","","","","","","","", +- /*V0-V7*/ "","","","","","","","", +- /*W0-W7*/ "","","","","","","","", +- /*X0-X7*/ "","","","","","","","", +- /*Y0-Y7*/ "","","","","","","","", +- /*Z0-Z7*/ "","","","","","","",""; +- +- pin_mclr_vpp { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "mclr_vpp"; +- }; +- +- i2c3_mux_oe_n { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "I2C3_MUX_OE_N"; +- }; +-}; +- +-&emmc_controller { +- status = "okay"; +-}; +- +-&pinctrl_emmc_default { +- bias-disable; +-}; +- +-&emmc { +- status = "okay"; +- clk-phase-mmc-hs200 = <180>, <180>; +-}; +- +-&fsim0 { +- status = "okay"; +- +- #address-cells = <2>; +- #size-cells = <0>; +- +- /* +- * CFAM Reset is supposed to be active low but pass1 hardware is wired +- * active high. +- */ +- cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; +- +- cfam@0,0 { +- reg = <0 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- chip-id = <0>; +- +- scom@1000 { +- compatible = "ibm,fsi2pib"; +- reg = <0x1000 0x400>; +- }; +- +- i2c@1800 { +- compatible = "ibm,fsi-i2c-master"; +- reg = <0x1800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam0_i2c0: i2c-bus@0 { +- reg = <0>; /* OMI01 */ +- }; +- +- cfam0_i2c1: i2c-bus@1 { +- reg = <1>; /* OMI23 */ +- }; +- +- cfam0_i2c10: i2c-bus@a { +- reg = <10>; /* OP3A */ +- }; +- +- cfam0_i2c11: i2c-bus@b { +- reg = <11>; /* OP3B */ +- }; +- +- cfam0_i2c12: i2c-bus@c { +- reg = <12>; /* OP4A */ +- }; +- +- cfam0_i2c13: i2c-bus@d { +- reg = <13>; /* OP4B */ +- }; +- +- cfam0_i2c14: i2c-bus@e { +- reg = <14>; /* OP5A */ +- }; +- +- cfam0_i2c15: i2c-bus@f { +- reg = <15>; /* OP5B */ +- }; +- }; +- +- fsi2spi@1c00 { +- compatible = "ibm,fsi2spi"; +- reg = <0x1c00 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam0_spi0: spi@0 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam0_spi1: spi@20 { +- reg = <0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam0_spi2: spi@40 { +- reg = <0x40>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam0_spi3: spi@60 { +- reg = <0x60>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- }; +- +- sbefifo@2400 { +- compatible = "ibm,p9-sbefifo"; +- reg = <0x2400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fsi_occ0: occ { +- compatible = "ibm,p10-occ"; +- }; +- }; +- +- fsi_hub0: hub@3400 { +- compatible = "fsi-master-hub"; +- reg = <0x3400 0x400>; +- #address-cells = <2>; +- #size-cells = <0>; +- }; +- }; +-}; +- +-&fsi_hub0 { +- cfam@1,0 { +- reg = <1 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- chip-id = <1>; +- +- scom@1000 { +- compatible = "ibm,fsi2pib"; +- reg = <0x1000 0x400>; +- }; +- +- i2c@1800 { +- compatible = "ibm,fsi-i2c-master"; +- reg = <0x1800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam1_i2c2: i2c-bus@2 { +- reg = <2>; /* OMI45 */ +- }; +- +- cfam1_i2c3: i2c-bus@3 { +- reg = <3>; /* OMI67 */ +- }; +- +- cfam1_i2c10: i2c-bus@a { +- reg = <10>; /* OP3A */ +- }; +- +- cfam1_i2c11: i2c-bus@b { +- reg = <11>; /* OP3B */ +- }; +- +- cfam1_i2c14: i2c-bus@e { +- reg = <14>; /* OP5A */ +- }; +- +- cfam1_i2c15: i2c-bus@f { +- reg = <15>; /* OP5B */ +- }; +- +- cfam1_i2c16: i2c-bus@10 { +- reg = <16>; /* OP6A */ +- }; +- +- cfam1_i2c17: i2c-bus@11 { +- reg = <17>; /* OP6B */ +- }; +- }; +- +- fsi2spi@1c00 { +- compatible = "ibm,fsi2spi"; +- reg = <0x1c00 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam1_spi0: spi@0 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam1_spi1: spi@20 { +- reg = <0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam1_spi2: spi@40 { +- reg = <0x40>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam1_spi3: spi@60 { +- reg = <0x60>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- }; +- +- sbefifo@2400 { +- compatible = "ibm,p9-sbefifo"; +- reg = <0x2400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fsi_occ1: occ { +- compatible = "ibm,p10-occ"; +- }; +- }; +- +- fsi_hub1: hub@3400 { +- compatible = "fsi-master-hub"; +- reg = <0x3400 0x400>; +- #address-cells = <2>; +- #size-cells = <0>; +- +- no-scan-on-init; +- }; +- }; +- +- cfam@2,0 { +- reg = <2 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- chip-id = <2>; +- +- scom@1000 { +- compatible = "ibm,fsi2pib"; +- reg = <0x1000 0x400>; +- }; +- +- i2c@1800 { +- compatible = "ibm,fsi-i2c-master"; +- reg = <0x1800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam2_i2c0: i2c-bus@0 { +- reg = <0>; /* OM01 */ +- }; +- +- cfam2_i2c1: i2c-bus@1 { +- reg = <1>; /* OM23 */ +- }; +- +- cfam2_i2c10: i2c-bus@a { +- reg = <10>; /* OP3A */ +- }; +- +- cfam2_i2c11: i2c-bus@b { +- reg = <11>; /* OP3B */ +- }; +- +- cfam2_i2c12: i2c-bus@c { +- reg = <12>; /* OP4A */ +- }; +- +- cfam2_i2c13: i2c-bus@d { +- reg = <13>; /* OP4B */ +- }; +- +- cfam2_i2c14: i2c-bus@e { +- reg = <14>; /* OP5A */ +- }; +- +- cfam2_i2c15: i2c-bus@f { +- reg = <15>; /* OP5B */ +- }; +- }; +- +- fsi2spi@1c00 { +- compatible = "ibm,fsi2spi"; +- reg = <0x1c00 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam2_spi0: spi@0 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam2_spi1: spi@20 { +- reg = <0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam2_spi2: spi@40 { +- reg = <0x40>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam2_spi3: spi@60 { +- reg = <0x60>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- }; +- +- sbefifo@2400 { +- compatible = "ibm,p9-sbefifo"; +- reg = <0x2400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fsi_occ2: occ { +- compatible = "ibm,p10-occ"; +- }; +- }; +- +- fsi_hub2: hub@3400 { +- compatible = "fsi-master-hub"; +- reg = <0x3400 0x400>; +- #address-cells = <2>; +- #size-cells = <0>; +- +- no-scan-on-init; +- }; +- }; +- +- cfam@3,0 { +- reg = <3 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- chip-id = <3>; +- +- scom@1000 { +- compatible = "ibm,fsi2pib"; +- reg = <0x1000 0x400>; +- }; +- +- i2c@1800 { +- compatible = "ibm,fsi-i2c-master"; +- reg = <0x1800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam3_i2c2: i2c-bus@2 { +- reg = <2>; /* OM45 */ +- }; +- +- cfam3_i2c3: i2c-bus@3 { +- reg = <3>; /* OM67 */ +- }; +- +- cfam3_i2c10: i2c-bus@a { +- reg = <10>; /* OP3A */ +- }; +- +- cfam3_i2c11: i2c-bus@b { +- reg = <11>; /* OP3B */ +- }; +- +- cfam3_i2c14: i2c-bus@e { +- reg = <14>; /* OP5A */ +- }; +- +- cfam3_i2c15: i2c-bus@f { +- reg = <15>; /* OP5B */ +- }; +- +- cfam3_i2c16: i2c-bus@10 { +- reg = <16>; /* OP6A */ +- }; +- +- cfam3_i2c17: i2c-bus@11 { +- reg = <17>; /* OP6B */ +- }; +- }; +- +- fsi2spi@1c00 { +- compatible = "ibm,fsi2spi"; +- reg = <0x1c00 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam3_spi0: spi@0 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam3_spi1: spi@20 { +- reg = <0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam3_spi2: spi@40 { +- reg = <0x40>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- cfam3_spi3: spi@60 { +- reg = <0x60>; +- compatible = "ibm,fsi2spi-restricted"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@0 { +- at25,byte-len = <0x80000>; +- at25,addr-mode = <4>; +- at25,page-size = <256>; +- +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- }; +- +- sbefifo@2400 { +- compatible = "ibm,p9-sbefifo"; +- reg = <0x2400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fsi_occ3: occ { +- compatible = "ibm,p10-occ"; +- }; +- }; +- +- fsi_hub3: hub@3400 { +- compatible = "fsi-master-hub"; +- reg = <0x3400 0x400>; +- #address-cells = <2>; +- #size-cells = <0>; +- +- no-scan-on-init; +- }; +- }; +-}; +- +-/* Legacy OCC numbering (to get rid of when userspace is fixed) */ +-&fsi_occ0 { +- reg = <1>; +-}; +- +-&fsi_occ1 { +- reg = <2>; +-}; +- +-&fsi_occ2 { +- reg = <3>; +-}; +- +-&fsi_occ3 { +- reg = <4>; +-}; +- +-&ibt { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- eeprom@51 { +- compatible = "atmel,24c64"; +- reg = <0x51>; +- }; +- +- tca_pres1: tca9554@20{ +- compatible = "ti,tca9554"; +- reg = <0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio-line-names = "", +- "RUSSEL_FW_I2C_ENABLE_N", +- "RUSSEL_OPPANEL_PRESENCE_N", +- "BLYTH_OPPANEL_PRESENCE_N", +- "CPU_TPM_CARD_PRESENT_N", +- "DASD_BP2_PRESENT_N", +- "DASD_BP1_PRESENT_N", +- "DASD_BP0_PRESENT_N"; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +- +- power-supply@68 { +- compatible = "ibm,cffps"; +- reg = <0x68>; +- }; +- +- power-supply@69 { +- compatible = "ibm,cffps"; +- reg = <0x69>; +- }; +- +- pca_pres1: pca9552@61 { +- compatible = "nxp,pca9552"; +- reg = <0x61>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio-line-names = +- "SLOT0_PRSNT_EN_RSVD", "SLOT1_PRSNT_EN_RSVD", +- "SLOT2_PRSNT_EN_RSVD", "SLOT3_PRSNT_EN_RSVD", +- "SLOT4_PRSNT_EN_RSVD", "SLOT0_EXPANDER_PRSNT_N", +- "SLOT1_EXPANDER_PRSNT_N", "SLOT2_EXPANDER_PRSNT_N", +- "SLOT3_EXPANDER_PRSNT_N", "SLOT4_EXPANDER_PRSNT_N", +- "", "", "", "", "", ""; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- +- gpio@8 { +- reg = <8>; +- type = ; +- }; +- +- gpio@9 { +- reg = <9>; +- type = ; +- }; +- +- gpio@10 { +- reg = <10>; +- type = ; +- }; +- +- gpio@11 { +- reg = <11>; +- type = ; +- }; +- +- gpio@12 { +- reg = <12>; +- type = ; +- }; +- +- gpio@13 { +- reg = <13>; +- type = ; +- }; +- +- gpio@14 { +- reg = <14>; +- type = ; +- }; +- +- gpio@15 { +- reg = <15>; +- type = ; +- }; +- }; +-}; +- +-&i2c4 { +- status = "okay"; +- +- tmp275@48 { +- compatible = "ti,tmp275"; +- reg = <0x48>; +- }; +- +- tmp275@49 { +- compatible = "ti,tmp275"; +- reg = <0x49>; +- }; +- +- tmp275@4a { +- compatible = "ti,tmp275"; +- reg = <0x4a>; +- }; +- +- pca9546@70 { +- compatible = "nxp,pca9546"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- i2c-mux-idle-disconnect; +- +- i2c4mux0chn0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- }; +- +- i2c4mux0chn1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- eeprom@51 { +- compatible = "atmel,24c64"; +- reg = <0x51>; +- }; +- }; +- +- i2c4mux0chn2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- eeprom@52 { +- compatible = "atmel,24c64"; +- reg = <0x52>; +- }; +- }; +- }; +-}; +- +-&i2c5 { +- status = "okay"; +- +- tmp275@48 { +- compatible = "ti,tmp275"; +- reg = <0x48>; +- }; +- +- tmp275@49 { +- compatible = "ti,tmp275"; +- reg = <0x49>; +- }; +- +- pca9546@70 { +- compatible = "nxp,pca9546"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- i2c-mux-idle-disconnect; +- +- i2c5mux0chn0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- }; +- +- i2c5mux0chn1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- eeprom@51 { +- compatible = "atmel,24c64"; +- reg = <0x51>; +- }; +- }; +- }; +-}; +- +-&i2c6 { +- status = "okay"; +- +- tmp275@48 { +- compatible = "ti,tmp275"; +- reg = <0x48>; +- }; +- +- tmp275@4a { +- compatible = "ti,tmp275"; +- reg = <0x4a>; +- }; +- +- tmp275@4b { +- compatible = "ti,tmp275"; +- reg = <0x4b>; +- }; +- +- pca9546@70 { +- compatible = "nxp,pca9546"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- i2c-mux-idle-disconnect; +- +- i2c6mux0chn0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- eeprom@53 { +- compatible = "atmel,24c64"; +- reg = <0x53>; +- }; +- }; +- +- i2c6mux0chn1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- eeprom@52 { +- compatible = "atmel,24c64"; +- reg = <0x52>; +- }; +- }; +- +- i2c6mux0chn2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- }; +- +- i2c6mux0chn3: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- eeprom@51 { +- compatible = "atmel,24c64"; +- reg = <0x51>; +- }; +- }; +- }; +-}; +- +-&i2c7 { +- multi-master; +- status = "okay"; +- +- si7021-a20@40 { +- compatible = "silabs,si7020"; +- reg = <0x40>; +- }; +- +- tmp275@48 { +- compatible = "ti,tmp275"; +- reg = <0x48>; +- }; +- +- max: max31785@52 { +- compatible = "maxim,max31785a"; +- reg = <0x52>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fan0: fan@0 { +- compatible = "pmbus-fan"; +- reg = <0>; +- tach-pulses = <2>; +- }; +- +- fan1: fan@1 { +- compatible = "pmbus-fan"; +- reg = <1>; +- tach-pulses = <2>; +- }; +- +- fan2: fan@2 { +- compatible = "pmbus-fan"; +- reg = <2>; +- tach-pulses = <2>; +- }; +- +- fan3: fan@3 { +- compatible = "pmbus-fan"; +- reg = <3>; +- tach-pulses = <2>; +- }; +- +- fan4: fan@4 { +- compatible = "pmbus-fan"; +- reg = <4>; +- tach-pulses = <2>; +- }; +- +- fan5: fan@5 { +- compatible = "pmbus-fan"; +- reg = <5>; +- tach-pulses = <2>; +- }; +- }; +- +- pca0: pca9552@61 { +- compatible = "nxp,pca9552"; +- reg = <0x61>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- +- gpio@8 { +- reg = <8>; +- type = ; +- }; +- +- gpio@9 { +- reg = <9>; +- type = ; +- }; +- +- gpio@10 { +- reg = <10>; +- type = ; +- }; +- +- gpio@11 { +- reg = <11>; +- type = ; +- }; +- +- gpio@12 { +- reg = <12>; +- type = ; +- }; +- +- gpio@13 { +- reg = <13>; +- type = ; +- }; +- +- gpio@14 { +- reg = <14>; +- type = ; +- }; +- +- gpio@15 { +- reg = <15>; +- type = ; +- }; +- }; +- +- ibm-panel@62 { +- compatible = "ibm,op-panel"; +- reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; +- }; +- +- dps: dps310@76 { +- compatible = "infineon,dps310"; +- reg = <0x76>; +- #io-channel-cells = <0>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c64"; +- reg = <0x51>; +- }; +-}; +- +-&i2c8 { +- status = "okay"; +- +- ucd90320@11 { +- compatible = "ti,ucd90320"; +- reg = <0x11>; +- }; +- +- rtc@32 { +- compatible = "epson,rx8900"; +- reg = <0x32>; +- }; +- +- tmp275@48 { +- compatible = "ti,tmp275"; +- reg = <0x48>; +- }; +- +- tmp275@4a { +- compatible = "ti,tmp275"; +- reg = <0x4a>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c64"; +- reg = <0x51>; +- }; +- +- pca_pres2: pca9552@61 { +- compatible = "nxp,pca9552"; +- reg = <0x61>; +- #address-cells = <1>; +- #size-cells = <0>; +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio-line-names = +- "SLOT6_PRSNT_EN_RSVD", "SLOT7_PRSNT_EN_RSVD", +- "SLOT8_PRSNT_EN_RSVD", "SLOT9_PRSNT_EN_RSVD", +- "SLOT10_PRSNT_EN_RSVD", "SLOT11_PRSNT_EN_RSVD", +- "SLOT6_EXPANDER_PRSNT_N", "SLOT7_EXPANDER_PRSNT_N", +- "SLOT8_EXPANDER_PRSNT_N", "SLOT9_EXPANDER_PRSNT_N", +- "SLOT10_EXPANDER_PRSNT_N", "SLOT11_EXPANDER_PRSNT_N", +- "", "", "", ""; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- +- gpio@8 { +- reg = <8>; +- type = ; +- }; +- +- gpio@9 { +- reg = <9>; +- type = ; +- }; +- +- gpio@10 { +- reg = <10>; +- type = ; +- }; +- +- gpio@11 { +- reg = <11>; +- type = ; +- }; +- +- gpio@12 { +- reg = <12>; +- type = ; +- }; +- +- gpio@13 { +- reg = <13>; +- type = ; +- }; +- +- gpio@14 { +- reg = <14>; +- type = ; +- }; +- +- gpio@15 { +- reg = <15>; +- type = ; +- }; +- }; +- +-}; +- +-&i2c9 { +- status = "okay"; +- +- tmp423a@4c { +- compatible = "ti,tmp423"; +- reg = <0x4c>; +- }; +- +- tmp423b@4d { +- compatible = "ti,tmp423"; +- reg = <0x4d>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c128"; +- reg = <0x50>; +- }; +-}; +- +-&i2c10 { +- status = "okay"; +- +- tmp423a@4c { +- compatible = "ti,tmp423"; +- reg = <0x4c>; +- }; +- +- tmp423b@4d { +- compatible = "ti,tmp423"; +- reg = <0x4d>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c128"; +- reg = <0x50>; +- }; +-}; +- +-&i2c11 { +- status = "okay"; +- +- tmp275@48 { +- compatible = "ti,tmp275"; +- reg = <0x48>; +- }; +- +- tmp275@49 { +- compatible = "ti,tmp275"; +- reg = <0x49>; +- }; +- +- pca9546@70 { +- compatible = "nxp,pca9546"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- i2c-mux-idle-disconnect; +- +- i2c11mux0chn0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- }; +- +- i2c11mux0chn1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- eeprom@51 { +- compatible = "atmel,24c64"; +- reg = <0x51>; +- }; +- }; +- }; +-}; +- +-&i2c12 { +- status = "okay"; +-}; +- +-&i2c13 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +-}; +- +-&i2c14 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +-}; +- +-&i2c15 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +-}; +- +-&vuart1 { +- status = "okay"; +-}; +- +-&vuart2 { +- status = "okay"; +-}; +- +-&lpc_ctrl { +- status = "okay"; +- memory-region = <&flash_memory>; +-}; +- +-&mac2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii3_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, +- <&syscon ASPEED_CLK_MAC3RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&mac3 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii4_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>, +- <&syscon ASPEED_CLK_MAC4RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +- spi-max-frequency = <50000000>; +-#include "openbmc-flash-layout-128.dtsi" +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "pnor"; +- spi-max-frequency = <100000000>; +- }; +-}; +- +-&wdt1 { +- aspeed,reset-type = "none"; +- aspeed,external-signal; +- aspeed,ext-push-pull; +- aspeed,ext-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdtrst1_default>; +-}; +- +-&wdt2 { +- status = "okay"; +-}; +- +-&xdma { +- status = "okay"; +- memory-region = <&vga_memory>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-inspur-fp5280g2.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-inspur-fp5280g2.dts +deleted file mode 100644 +index 1752f3250e44..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-inspur-fp5280g2.dts ++++ /dev/null +@@ -1,905 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/dts-v1/; +-#include "aspeed-g5.dtsi" +-#include +-#include +- +-/ { +- model = "FP5280G2 BMC"; +- compatible = "inspur,fp5280g2-bmc", "aspeed,ast2500"; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- vga_memory: framebuffer@9f000000 { +- no-map; +- reg = <0x9f000000 0x01000000>; /* 16M */ +- }; +- +- flash_memory: region@98000000 { +- no-map; +- reg = <0x98000000 0x04000000>; /* 64M */ +- }; +- +- coldfire_memory: codefire_memory@9ef00000 { +- reg = <0x9ef00000 0x00100000>; +- no-map; +- }; +- +- gfx_memory: framebuffer { +- size = <0x01000000>; +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- +- video_engine_memory: jpegbuffer { +- size = <0x02000000>; /* 32M */ +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- }; +- +- fsi: gpio-fsi { +- compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; +- #address-cells = <2>; +- #size-cells = <0>; +- no-gpio-delays; +- +- memory-region = <&coldfire_memory>; +- aspeed,sram = <&sram>; +- aspeed,cvic = <&cvic>; +- +- clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; +- data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>; +- mux-gpios = <&gpio ASPEED_GPIO(I, 2) GPIO_ACTIVE_HIGH>; +- enable-gpios = <&gpio ASPEED_GPIO(I, 3) GPIO_ACTIVE_HIGH>; +- trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- checkstop { +- label = "checkstop"; +- gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- ps0-presence { +- label = "ps0-presence"; +- gpios = <&gpio ASPEED_GPIO(F, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- ps1-presence { +- label = "ps1-presence"; +- gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- poll-interval = <1000>; +- +- fan0-presence { +- label = "fan0-presence"; +- gpios = <&pca1 0 GPIO_ACTIVE_LOW>; +- linux,code = <1>; +- }; +- +- fan1-presence { +- label = "fan1-presence"; +- gpios = <&pca1 1 GPIO_ACTIVE_LOW>; +- linux,code = <2>; +- }; +- +- fan2-presence { +- label = "fan2-presence"; +- gpios = <&pca1 2 GPIO_ACTIVE_LOW>; +- linux,code = <3>; +- }; +- +- fan3-presence { +- label = "fan3-presence"; +- gpios = <&pca1 3 GPIO_ACTIVE_LOW>; +- linux,code = <4>; +- }; +- +- fan4-presence { +- label = "fan4-presence"; +- gpios = <&pca1 4 GPIO_ACTIVE_LOW>; +- linux,code = <5>; +- }; +- +- fan5-presence { +- label = "fan5-presence"; +- gpios = <&pca1 5 GPIO_ACTIVE_LOW>; +- linux,code = <6>; +- }; +- +- fan6-presence { +- label = "fan6-presence"; +- gpios = <&pca1 6 GPIO_ACTIVE_LOW>; +- linux,code = <7>; +- }; +- +- fan7-presence { +- label = "fan7-presence"; +- gpios = <&pca1 7 GPIO_ACTIVE_LOW>; +- linux,code = <8>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- power { +- label = "power"; +- /* TODO: dummy gpio */ +- gpios = <&gpio ASPEED_GPIO(R, 1) GPIO_ACTIVE_LOW>; +- }; +- +- init-ok { +- label = "init-ok"; +- gpios = <&gpio ASPEED_GPIO(B, 7) GPIO_ACTIVE_LOW>; +- }; +- +- front-memory { +- label = "front-memory"; +- gpios = <&gpio ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>; +- }; +- +- front-syshot { +- label = "front-syshot"; +- gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; +- }; +- +- front-syshealth { +- label = "front-syshealth"; +- gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; +- }; +- +- front-fan { +- label = "front-fan"; +- gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>; +- }; +- +- front-psu { +- label = "front-psu"; +- gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>; +- }; +- +- identify { +- label = "identify"; +- gpios = <&gpio ASPEED_GPIO(Z, 7) GPIO_ACTIVE_LOW>; +- }; +- }; +- +- iio-hwmon-battery { +- compatible = "iio-hwmon"; +- io-channels = <&adc 15>; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, +- <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>, +- <&adc 10>, <&adc 11>, <&adc 12>, <&adc 13>, <&adc 14>; +- }; +- +-}; +- +-&gpio { +- gpio-line-names = +- /*A0-A7*/ "","","","","","","","", +- /*B0-B7*/ "","","front-psu","checkstop","cfam-reset","","","init-ok", +- /*C0-C7*/ "","","","","","","","", +- /*D0-D7*/ "","","","","","","","", +- /*E0-E7*/ "","","","","","","","", +- /*F0-F7*/ "ps0-presence","ps1-presence","","","front-memory","","","", +- /*G0-G7*/ "","","","","","","","", +- /*H0-H7*/ "","","","","front-fan","","","", +- /*I0-I7*/ "front-syshealth","front-syshot","mux-gpios","enable-gpios","","","","", +- /*J0-J7*/ "","","","","","","","", +- /*K0-K7*/ "","","","","","","","", +- /*L0-L7*/ "","","","","","","","", +- /*M0-M7*/ "","","","","","","","", +- /*N0-N7*/ "","","","","","","","", +- /*O0-O7*/ "","","","","","","","", +- /*P0-P7*/ "","","","","","","","", +- /*Q0-Q7*/ "","","","","","","","", +- /*R0-R7*/ "","power","trans-gpios","","","","","", +- /*S0-S7*/ "","","","","","","","", +- /*T0-T7*/ "","","","","","","","", +- /*U0-U7*/ "","","","","","","","", +- /*V0-V7*/ "","","","","","","","", +- /*W0-W7*/ "","","","","","","","", +- /*X0-X7*/ "","","","","","","","", +- /*Y0-Y7*/ "","","","","","","","", +- /*Z0-Z7*/ "","","","","","","","identify", +- /*AA0-AA7*/ "clock-gpios","","data-gpios","","","","","", +- /*AB0-AB7*/ "","","","","","","","", +- /*AC0-AC7*/ "","","","","","","",""; +-}; +- +-&fmc { +- status = "okay"; +- +- flash@0 { +- status = "okay"; +- label = "bmc"; +- m25p,fast-read; +- spi-max-frequency = <50000000>; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- +- flash@0 { +- status = "okay"; +- label = "pnor"; +- m25p,fast-read; +- spi-max-frequency = <100000000>; +- }; +-}; +- +-&uart1 { +- /* Rear RS-232 connector */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default +- &pinctrl_nrts1_default +- &pinctrl_ndtr1_default +- &pinctrl_ndsr1_default +- &pinctrl_ncts1_default +- &pinctrl_ndcd1_default +- &pinctrl_nri1_default>; +-}; +- +-&uart2 { +- /* Test Point */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; +-}; +- +-&uart3 { +- /* APSS */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&lpc_ctrl { +- status = "okay"; +- memory-region = <&flash_memory>; +- flash = <&spi1>; +-}; +- +-&mac0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&mac1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +-}; +- +-&i2c0 { +- /* LCD */ +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- label = "fru"; +- }; +- +-}; +- +-&i2c2 { +- status = "okay"; +- +- tmp112@48 { +- compatible = "ti,tmp112"; +- reg = <0x48>; +- label = "inlet"; +- }; +- +- tmp112@49 { +- compatible = "ti,tmp112"; +- reg = <0x49>; +- label = "outlet"; +- }; +- +- i2c-switch@70 { +- compatible = "nxp,pca9546"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- tmp112@4a { +- compatible = "ti,tmp112"; +- reg = <0x4a>; +- label = "psu_inlet"; +- }; +- +- }; +- +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tmp112@4a { +- compatible = "ti,tmp112"; +- reg = <0x4a>; +- label = "ocp_zone"; +- }; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- tmp112@4a { +- compatible = "ti,tmp112"; +- reg = <0x4a>; +- label = "bmc_zone"; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- tmp112@7c { +- compatible = "microchip,emc1413"; +- reg = <0x7c>; +- }; +- }; +- +- }; +-}; +- +-&i2c3 { +- /* Riser Card */ +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +- +- rtc@68 { +- compatible = "dallas,ds3232"; +- reg = <0x68>; +- }; +-}; +- +-&i2c5 { +- /* vr */ +- status = "okay"; +-}; +- +-&i2c6 { +- /* bp card */ +- status = "okay"; +-}; +- +-&i2c7 { +- status = "okay"; +- +- i2c-switch@70 { +- compatible = "nxp,pca9546"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- adm1278@10 { +- compatible = "adi,adm1278"; +- reg = <0x10>; +- }; +- +- adm1278@13 { +- compatible = "adi,adm1278"; +- reg = <0x13>; +- }; +- +- adm1278@50 { +- compatible = "adi,adm1278"; +- reg = <0x50>; +- }; +- +- adm1278@53 { +- compatible = "adi,adm1278"; +- reg = <0x53>; +- }; +- +- }; +- +- /*pcie riser*/ +- +- }; +-}; +- +-&i2c8 { +- status = "okay"; +- +- pca0: pca9555@20 { +- compatible = "nxp,pca9555"; +- reg = <0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- +- }; +- +- pca1: pca9555@21 { +- compatible = "nxp,pca9555"; +- reg = <0x21>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +- +- pca2: pca9555@22 { +- compatible = "nxp,pca9555"; +- reg = <0x22>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +- +- pca3: pca9555@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +- +- pca4: pca9555@24 { +- compatible = "nxp,pca9555"; +- reg = <0x24>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +- +- pca5: pca9555@25 { +- compatible = "nxp,pca9555"; +- reg = <0x25>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +- +-}; +- +-&i2c9 { +- /* cpld */ +- status = "okay"; +-}; +- +-&i2c10 { +- /* hdd bp */ +- status = "okay"; +-}; +- +-&i2c11 { +- status = "okay"; +- +- power-supply@58 { +- compatible = "inspur,ipsps1"; +- reg = <0x58>; +- }; +- +- power-supply@59 { +- compatible = "inspur,ipsps1"; +- reg = <0x59>; +- }; +-}; +- +-&i2c12 { +- /* odcc */ +- status = "okay"; +-}; +- +-&vuart { +- status = "okay"; +-}; +- +-&gfx { +- status = "okay"; +- memory-region = <&gfx_memory>; +-}; +- +-&pinctrl { +- aspeed,external-nodes = <&gfx &lhc>; +-}; +- +-&wdt1 { +- aspeed,reset-type = "none"; +- aspeed,external-signal; +- aspeed,ext-push-pull; +- aspeed,ext-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdtrst1_default>; +-}; +- +-&ibt { +- status = "okay"; +- +-}; +- +-&adc { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default +- &pinctrl_adc2_default &pinctrl_adc3_default &pinctrl_adc4_default +- &pinctrl_adc5_default &pinctrl_adc6_default &pinctrl_adc7_default +- &pinctrl_adc8_default &pinctrl_adc9_default &pinctrl_adc10_default +- &pinctrl_adc11_default &pinctrl_adc12_default &pinctrl_adc13_default +- &pinctrl_adc14_default &pinctrl_adc15_default>; +-}; +- +-&vhub { +- status = "okay"; +-}; +- +-&video { +- status = "okay"; +- memory-region = <&video_engine_memory>; +-}; +- +-&pwm_tacho { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default +- &pinctrl_pwm2_default &pinctrl_pwm3_default +- &pinctrl_pwm4_default &pinctrl_pwm5_default +- &pinctrl_pwm6_default &pinctrl_pwm7_default>; +- +- fan@0 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; +- }; +- +- fan@1 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; +- }; +- +- fan@2 { +- reg = <0x02>; +- aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>; +- }; +- +- fan@3 { +- reg = <0x03>; +- aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>; +- }; +- +- fan@4 { +- reg = <0x04>; +- aspeed,fan-tach-ch = /bits/ 8 <0x08 0x09>; +- }; +- +- fan@5 { +- reg = <0x05>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0a 0x0b>; +- }; +- +- fan@6 { +- reg = <0x06>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0c 0x0d>; +- }; +- +- fan@7 { +- reg = <0x07>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0e 0x0f>; +- }; +- +-}; +- +-#include "ibm-power9-dual.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-inspur-nf5280m6.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-inspur-nf5280m6.dts +deleted file mode 100644 +index b3c1e3ba5831..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-inspur-nf5280m6.dts ++++ /dev/null +@@ -1,691 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2021 Inspur Corporation +-/dts-v1/; +- +-#include "aspeed-g5.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "NF5280M6 BMC"; +- compatible = "inspur,nf5280m6-bmc", "aspeed,ast2500"; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x40000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- vga_memory: framebuffer@9f000000 { +- no-map; +- reg = <0x9f000000 0x01000000>; /* 16M */ +- }; +- +- video_engine_memory: jpegbuffer { +- size = <0x02000000>; /* 32M */ +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- bmc_alive { +- label = "bmc_alive"; +- gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>; +- linux,default-trigger = "timer"; +- led-pattern = <1000 1000>; +- }; +- +- front-fan { +- label = "front-fan"; +- gpios = <&gpio ASPEED_GPIO(F,2) GPIO_ACTIVE_LOW>; +- }; +- +- front-psu { +- label = "front-psu"; +- gpios = <&gpio ASPEED_GPIO(F,3) GPIO_ACTIVE_LOW>; +- }; +- +- front-syshot { +- label = "front-syshot"; +- gpios = <&gpio ASPEED_GPIO(J, 3) GPIO_ACTIVE_LOW>; +- }; +- +- front-memory { +- label = "front-memory"; +- gpios = <&gpio ASPEED_GPIO(S, 7) GPIO_ACTIVE_LOW>; +- }; +- +- identify { +- label = "identify"; +- gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>; +- }; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, +- <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, +- <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, +- <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; +- }; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +- spi-max-frequency = <50000000>; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bios"; +- spi-max-frequency = <100000000>; +- }; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&mac1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +-}; +- +-&gpio { +- status = "okay"; +- /* Enable GPIOE0 and GPIOE2 pass-through by default */ +- pinctrl-names = "pass-through"; +- pinctrl-0 = <&pinctrl_gpie0_default +- &pinctrl_gpie2_default>; +- gpio-line-names = +- /*A0-A7*/ "","MAC2LINK","BMC_RESET_CPLD","","BMC_SCL9","","MAC2MDC_R","", +- /*B0-B7*/ "BMC_INIT_OK","FM_SKU_ID2","FM_SPD_DDRCPU_LVLSHFT_DIS_R_N", +- "FM_CPU_MSMI_CATERR_LVT3_BMC_N","","FM_CPU0_PROCHOT_LVT3_N", +- "FM_CPU_MEM_THERMTRIP_LVT3_N","BIOS_LOAD_DEFAULT_R_N", +- /*C0-C7*/ "","","","","","","","", +- /*D0-D7*/ "","BMC_SD2CMD","BMC_SD2DAT0","BMC_SD2DAT1","BMC_SD2DAT2", +- "BMC_SD2DAT3","BMC_SD2DET","BMC_SD2WPT", +- /*E0-E7*/ "FM_BOARD_ID0","FM_BOARD_ID1","FM_BOARD_ID2","FM_BOARD_ID3", +- "FM_BOARD_ID4","FM_BOARD_ID5","","", +- /*F0-F7*/ "PSU1_PRESENT_N","PSU2_PRESENT_N","FAN_FAULT_LED_N","PSU_FAULT_LED_N", +- "BIOS_DEBUG_MODE_N","FP_LCD_RESET","FAN_TYPE_SEL", +- "RST_GLB_RST_WARN_N", +- /*G0-G7*/ "IRQ_LPTM21L_ALERT_N","IRQ_PLD_ALERT_N","AC_FAIL_N","FP_LCD_PRESENT_BMC", +- "BMC_JTAG_TCK_MUX_SEL","BMC_BIOS_RESERVED","SYS_NMI_N","BMC_NMI_N", +- /*H0-H7*/ "JTAG_BMC_TDI","JTAG_BMC_TDO","JTAG_BMC_TCK","JTAG_BMC_TMS","FM_BOARD_ID6", +- "FM_SKU_ID0","IRQ_SML1_PMBUS_ALERT_N","IRQ_SML0_ALERT_MUX_N", +- /*I0-I7*/ "FM_CPU_ERR0_LVT3_BMC_N","FM_CPU_ERR1_LVT3_BMC_N","FM_BMC_PCH_SCI_LPC_N", +- "FM_SYS_THROTTLE_LVC3","SPI2_PCH_CS0_N","","","", +- /*J0-J7*/ "FM_CPU0_SKTOCC_LVT3_N","FM_CPU1_SKTOCC_LVT3_N","","SYSHOT_FAULT_LED_N", +- "VGA_HSYNC","VGA_VSYNC","","", +- /*K0-K7*/ "","","","","","","","", +- /*L0-L7*/ "","","","","","","SYS_UART_TXD1","SYS_UART_RXD1", +- /*M0-M7*/ "","","","","","","","", +- /*N0-N7*/ "","","","","","","","", +- /*O0-O7*/ "","","","","","","","", +- /*P0-P7*/ "","","","","","","","", +- /*Q0-Q7*/ "","","","","","","FM_PCH_BMC_THERMTRIP_N","INTRUDER_N", +- /*R0-R7*/ "SPI_BMC_BOOT_CS1_R_N","FM_CPU_MEMHOT_LVC3_N", +- "DBP_CPU_PREQ_N","FM_CPU_ERR2_LVT3_BMC_N", +- "RISER_NCSI_EN_N","","LOM_NCSI_EN_N","OCP_NCSI_EN_N", +- /*S0-S7*/ "BMC_XDP_PRDY_N","SIO_POWER_GOOD","BMC_PWR_DEBUG_R_N","BMC_DEBUG_EN_R_N","", +- "GPIOS5_BMC","","GPIOS7_BMC", +- /*T0-T7*/ "","","","","","","","", +- /*U0-U7*/ "","","","","","","","", +- /*V0-V7*/ "","","","","","","","", +- /*W0-W7*/ "","","","","","","","", +- /*X0-X7*/ "","","","","","","","", +- /*Y0-Y7*/ "","BMC_DET_UID_N","BMC_JTAG_SEL","SIO_ONCONTROL","","","","", +- /*Z0-Z7*/ "XDP_PRESENT_N","DBP_SYSPWROK","BMC_JTAG_SEL","FM_SMI_ACTIVE_N","", +- "GPIOZ5","","", +- /*AA0-AA7*/ "FP_BMC_SYSLED_N","PS_PWROK","RST_PLTRST_BMC_N","HDA_SDO_BMC", +- "FM_SLPS4_R_N","","POWER_BUTTON","POWER_OUT", +- /*AB0-AB7*/ "RESET_OUT","RESET_BUTTON","BIOS_REFLASH","POST_COMPLETE","","","","", +- /*AC0-AC7*/ "","","","","","","",""; +-}; +- +-&i2c0 { +- /* FP_LCD */ +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- label = "fru"; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- +- tmp112@48 { +- compatible = "ti,tmp112"; +- reg = <0x48>; +- label = "inlet"; +- }; +- +- tmp112@49 { +- compatible = "ti,tmp112"; +- reg = <0x49>; +- label = "outlet"; +- }; +- +- pca9548@70 { +- compatible = "nxp,pca9548"; +- reg = <0x70>; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +- +- pca9548@70 { +- compatible = "nxp,pca9548"; +- reg = <0x70>; +- }; +- +- pca9548@71 { +- compatible = "nxp,pca9548"; +- reg = <0x71>; +- }; +- +- pca9548@72 { +- compatible = "nxp,pca9548"; +- reg = <0x72>; +- }; +-}; +- +-&i2c4 { +- /* IPMB */ +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +- +- pca9548@70 { +- compatible = "nxp,pca9548"; +- reg = <0x70>; +- }; +-}; +- +-&i2c6 { +- status = "okay"; +- +- pca9548@70 { +- compatible = "nxp,pca9548"; +- reg = <0x70>; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +- +- adm1278@33 { +- compatible = "adi,adm1293"; +- reg = <0x33>; +- }; +- +- adm1278@32 { +- compatible = "adi,adm1293"; +- reg = <0x32>; +- }; +- +- adm1278@20 { +- compatible = "adi,adm1293"; +- reg = <0x20>; +- }; +-}; +- +-&i2c8 { +- status = "okay"; +- +- pca0: pca9555@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- }; +- +- pca1: pca9555@22 { +- compatible = "nxp,pca9555"; +- reg = <0x22>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +- +- pca2: pca9555@20 { +- compatible = "nxp,pca9555"; +- reg = <0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +- +- pca3: pca9555@21 { +- compatible = "nxp,pca9555"; +- reg = <0x21>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +-}; +- +-&i2c9 { +- /* cpld */ +- status = "okay"; +-}; +- +-&i2c10 { +- status = "okay"; +- +- pca4: pca9555@24 { +- compatible = "nxp,pca9555"; +- reg = <0x24>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +- +- pca5: pca9555@25 { +- compatible = "nxp,pca9555"; +- reg = <0x25>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- }; +-}; +- +-&i2c11 { +- status = "okay"; +- +- power-supply@58 { +- compatible = "inspur,ipsps1"; +- reg = <0x58>; +- }; +- +- power-supply@59 { +- compatible = "inspur,ipsps1"; +- reg = <0x59>; +- }; +-}; +- +-&i2c12 { +- status = "okay"; +-}; +- +-&i2c13 { +- status = "okay"; +-}; +- +-&pwm_tacho { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default +- &pinctrl_pwm2_default &pinctrl_pwm3_default +- &pinctrl_pwm4_default &pinctrl_pwm5_default +- &pinctrl_pwm6_default &pinctrl_pwm7_default>; +- +- fan@0 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; +- }; +- +- fan@1 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; +- }; +- +- fan@2 { +- reg = <0x02>; +- aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>; +- }; +- +- fan@3 { +- reg = <0x03>; +- aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>; +- }; +- +- fan@4 { +- reg = <0x04>; +- aspeed,fan-tach-ch = /bits/ 8 <0x08 0x09>; +- }; +- +- fan@5 { +- reg = <0x05>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0a 0x0b>; +- }; +- +- fan@6 { +- reg = <0x06>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0c 0x0d>; +- }; +- +- fan@7 { +- reg = <0x07>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0e 0x0f>; +- }; +-}; +- +-&kcs3 { +- status = "okay"; +- aspeed,lpc-io-reg = <0xca2>; +-}; +- +-&kcs4 { +- status = "okay"; +- aspeed,lpc-io-reg = <0xca4>; +-}; +- +-&adc { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default +- &pinctrl_adc2_default &pinctrl_adc3_default &pinctrl_adc4_default +- &pinctrl_adc5_default &pinctrl_adc6_default &pinctrl_adc7_default +- &pinctrl_adc8_default &pinctrl_adc9_default &pinctrl_adc10_default +- &pinctrl_adc11_default &pinctrl_adc12_default &pinctrl_adc13_default +- &pinctrl_adc14_default &pinctrl_adc15_default>; +-}; +- +-&vhub { +- status = "okay"; +-}; +- +-&video { +- status = "okay"; +- memory-region = <&video_engine_memory>; +-}; +- +-&vuart { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-inspur-on5263m5.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-inspur-on5263m5.dts +deleted file mode 100644 +index 5a98a19f445e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-inspur-on5263m5.dts ++++ /dev/null +@@ -1,148 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2018 Inspur Corporation +-/dts-v1/; +- +-#include "aspeed-g5.dtsi" +-#include +- +-/ { +- model = "ON5263M5 BMC"; +- compatible = "inspur,on5263m5-bmc", "aspeed,ast2500"; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "earlycon"; +- }; +- +- memory { +- reg = <0x80000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- vga_memory: framebuffer@9f000000 { +- no-map; +- reg = <0x9f000000 0x01000000>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- bmc_alive { +- label = "bmc_alive"; +- gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; +- linux,default-trigger = "timer"; +- }; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, +- <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; +- }; +- +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "pnor"; +- }; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&mac1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +-}; +- +-&i2c6 { +- status = "okay"; +- +- tmp421@4e { +- compatible = "ti,tmp421"; +- reg = <0x4e>; +- }; +- +- tmp112@48 { +- compatible = "ti,tmp112"; +- reg = <0x48>; +- }; +- +- eeprom@54 { +- compatible = "atmel,24c64"; +- reg = <0x54>; +- pagesize = <32>; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +- +- adm1278@11 { +- compatible = "adi,adm1278"; +- reg = <0x11>; +- }; +-}; +- +-&gfx { +- status = "okay"; +-}; +- +-&pinctrl { +- aspeed,external-nodes = <&gfx &lhc>; +-}; +- +-&pwm_tacho { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; +- +- fan@0 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; +- }; +- +- fan@1 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; +- }; +-}; +- +-&adc { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-intel-s2600wf.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-intel-s2600wf.dts +deleted file mode 100644 +index d5b7d28cda88..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-intel-s2600wf.dts ++++ /dev/null +@@ -1,132 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2017 Intel Corporation +-/dts-v1/; +- +-#include "aspeed-g5.dtsi" +- +-/ { +- model = "S2600WF BMC"; +- compatible = "intel,s2600wf-bmc", "aspeed,ast2500"; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- vga_memory: framebuffer@9f000000 { +- no-map; +- reg = <0x9f000000 0x01000000>; /* 16M */ +- }; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, +- <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, +- <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, +- <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; +- }; +- +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "pnor"; +- }; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&mac1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- status = "okay"; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&i2c13 { +- status = "okay"; +-}; +- +-&gfx { +- status = "okay"; +-}; +- +-&pinctrl { +- aspeed,external-nodes = <&gfx &lhc>; +-}; +- +-&pwm_tacho { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default +- &pinctrl_pwm2_default &pinctrl_pwm3_default +- &pinctrl_pwm4_default &pinctrl_pwm5_default +- &pinctrl_pwm6_default &pinctrl_pwm7_default>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-lenovo-hr630.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-lenovo-hr630.dts +deleted file mode 100644 +index 8f543cca7c21..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-lenovo-hr630.dts ++++ /dev/null +@@ -1,569 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Device Tree file for Lenovo Hr630 platform +- * +- * Copyright (C) 2019-present Lenovo +- */ +- +-/dts-v1/; +- +-#include "aspeed-g5.dtsi" +-#include +- +-/ { +- model = "HR630 BMC"; +- compatible = "lenovo,hr630-bmc", "aspeed,ast2500"; +- +- aliases { +- i2c14 = &i2c_rbp; +- i2c15 = &i2c_fbp1; +- i2c16 = &i2c_fbp2; +- i2c17 = &i2c_fbp3; +- i2c18 = &i2c_riser2; +- i2c19 = &i2c_pcie4; +- i2c20 = &i2c_riser1; +- i2c21 = &i2c_ocp; +- }; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=tty0 console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- flash_memory: region@98000000 { +- no-map; +- reg = <0x98000000 0x00100000>; /* 1M */ +- }; +- +- gfx_memory: framebuffer { +- size = <0x01000000>; +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- heartbeat { +- gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_LOW>; +- }; +- +- fault { +- gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>; +- }; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, +- <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, +- <&adc 8>, <&adc 9>, <&adc 10>, +- <&adc 12>, <&adc 13>, <&adc 14>; +- }; +- +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +- spi-max-frequency = <50000000>; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&lpc_ctrl { +- status = "okay"; +- memory-region = <&flash_memory>; +- flash = <&spi1>; +-}; +- +-&uart1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default>; +-}; +- +-&uart2 { +- /* Rear RS-232 connector */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd2_default +- &pinctrl_rxd2_default +- &pinctrl_nrts2_default +- &pinctrl_ndtr2_default +- &pinctrl_ndsr2_default +- &pinctrl_ncts2_default +- &pinctrl_ndcd2_default +- &pinctrl_nri2_default>; +-}; +- +-&uart3 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd3_default +- &pinctrl_rxd3_default>; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&ibt { +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&mac1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +-}; +- +-&adc { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc0_default +- &pinctrl_adc1_default +- &pinctrl_adc2_default +- &pinctrl_adc3_default +- &pinctrl_adc4_default +- &pinctrl_adc5_default +- &pinctrl_adc6_default +- &pinctrl_adc7_default +- &pinctrl_adc8_default +- &pinctrl_adc9_default +- &pinctrl_adc10_default +- &pinctrl_adc12_default +- &pinctrl_adc13_default +- &pinctrl_adc14_default>; +-}; +- +-&i2c0 { +- status = "okay"; +- /* temp1 inlet */ +- tmp75@4e { +- compatible = "national,lm75"; +- reg = <0x4e>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- /* temp2 outlet */ +- tmp75@4d { +- compatible = "national,lm75"; +- reg = <0x4d>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- status = "okay"; +- /* Slot 0, +- * Slot 1, +- * Slot 2, +- * Slot 3 +- */ +- +- i2c-switch@70 { +- compatible = "nxp,pca9545"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-mux-idle-disconnect; /* may use mux@70 next. */ +- +- i2c_rbp: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c_fbp1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- i2c_fbp2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c_fbp3: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +- +- /* Slot 0, +- * Slot 1, +- * Slot 2, +- * Slot 3 +- */ +- i2c-switch@76 { +- compatible = "nxp,pca9546"; +- reg = <0x76>; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-mux-idle-disconnect; /* may use mux@76 next. */ +- +- i2c_riser2: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c_pcie4: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- i2c_riser1: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c_ocp: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +-}; +- +-&i2c8 { +- status = "okay"; +- +- eeprom@57 { +- compatible = "atmel,24c256"; +- reg = <0x57>; +- pagesize = <16>; +- }; +-}; +- +-&i2c9 { +- status = "okay"; +-}; +- +-&i2c10 { +- status = "okay"; +-}; +- +-&i2c11 { +- status = "okay"; +-}; +- +-&i2c12 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&uhci { +- status = "okay"; +-}; +- +-&gfx { +- status = "okay"; +- memory-region = <&gfx_memory>; +-}; +- +-&pwm_tacho { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default +- &pinctrl_pwm1_default +- &pinctrl_pwm2_default +- &pinctrl_pwm3_default +- &pinctrl_pwm4_default +- &pinctrl_pwm5_default +- &pinctrl_pwm6_default>; +- +- fan@0 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x00>; +- }; +- +- fan@1 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x01>; +- }; +- +- fan@2 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x02>; +- }; +- +- fan@3 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x03>; +- }; +- +- fan@4 { +- reg = <0x02>; +- aspeed,fan-tach-ch = /bits/ 8 <0x04>; +- }; +- +- fan@5 { +- reg = <0x02>; +- aspeed,fan-tach-ch = /bits/ 8 <0x05>; +- }; +- +- fan@6 { +- reg = <0x03>; +- aspeed,fan-tach-ch = /bits/ 8 <0x06>; +- }; +- +- fan@7 { +- reg = <0x03>; +- aspeed,fan-tach-ch = /bits/ 8 <0x07>; +- }; +- +- fan@8 { +- reg = <0x04>; +- aspeed,fan-tach-ch = /bits/ 8 <0x08>; +- }; +- +- fan@9 { +- reg = <0x04>; +- aspeed,fan-tach-ch = /bits/ 8 <0x09>; +- }; +- +- fan@10 { +- reg = <0x05>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0a>; +- }; +- +- fan@11 { +- reg = <0x05>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0b>; +- }; +- +- fan@12 { +- reg = <0x06>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0c>; +- }; +- +- fan@13 { +- reg = <0x06>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0d>; +- }; +-}; +- +-&gpio { +- +- pin_gpio_b5 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "IRQ_BMC_PCH_SMI_LPC_N"; +- }; +- +- pin_gpio_f0 { +- gpio-hog; +- gpios = ; +- output-low; +- line-name = "IRQ_BMC_PCH_NMI_R"; +- }; +- +- pin_gpio_f3 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "I2C_BUS0_RST_OUT_N"; +- }; +- +- pin_gpio_f4 { +- gpio-hog; +- gpios = ; +- output-low; +- line-name = "FM_SKT0_FAULT_LED"; +- }; +- +- pin_gpio_f5 { +- gpio-hog; +- gpios = ; +- output-low; +- line-name = "FM_SKT1_FAULT_LED"; +- }; +- +- pin_gpio_g4 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "FAN_PWR_CTL_N"; +- }; +- +- pin_gpio_g7 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "RST_BMC_PCIE_I2CMUX_N"; +- }; +- +- pin_gpio_h2 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "PSU1_FFS_N_R"; +- }; +- +- pin_gpio_h3 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "PSU2_FFS_N_R"; +- }; +- +- pin_gpio_i3 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "BMC_INTRUDED_COVER"; +- }; +- +- pin_gpio_j2 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "BMC_BIOS_UPDATE_N"; +- }; +- +- pin_gpio_j3 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "RST_BMC_HDD_I2CMUX_N"; +- }; +- +- pin_gpio_s2 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "BMC_VGA_SW"; +- }; +- +- pin_gpio_s4 { +- gpio-hog; +- gpios = ; +- output; +- line-name = "VBAT_EN_N"; +- }; +- +- pin_gpio_s6 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "PU_BMC_GPIOS6"; +- }; +- +- pin_gpio_y0 { +- gpio-hog; +- gpios = ; +- output-low; +- line-name = "BMC_NCSI_MUX_CTL_S0"; +- }; +- +- pin_gpio_y1 { +- gpio-hog; +- gpios = ; +- output-low; +- line-name = "BMC_NCSI_MUX_CTL_S1"; +- }; +- +- pin_gpio_z0 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "I2C_RISER2_INT_N"; +- }; +- +- pin_gpio_z2 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "I2C_RISER2_RESET_N"; +- }; +- +- pin_gpio_z3 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "FM_BMC_PCH_SCI_LPC_N"; +- }; +- +- pin_gpio_z7 { +- gpio-hog; +- gpios = ; +- output-low; +- line-name = "BMC_POST_CMPLT_N"; +- }; +- +- pin_gpio_aa0 { +- gpio-hog; +- gpios = ; +- output-low; +- line-name = "HOST_BMC_USB_SEL"; +- }; +- +- pin_gpio_aa5 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "I2C_BUS1_RST_OUT_N"; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-lenovo-hr855xg2.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-lenovo-hr855xg2.dts +deleted file mode 100644 +index bcc1820f5c07..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-lenovo-hr855xg2.dts ++++ /dev/null +@@ -1,666 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Device Tree file for Lenovo Hr855xg2 platform +- * +- * Copyright (C) 2019-present Lenovo +- */ +- +-/dts-v1/; +- +-#include "aspeed-g5.dtsi" +-#include +- +-/ { +- model = "HR855XG2 BMC"; +- compatible = "lenovo,hr855xg2-bmc", "aspeed,ast2500"; +- +- aliases { +- i2c14 = &i2c_riser1; +- i2c15 = &i2c_riser2; +- i2c16 = &i2c_riser3; +- i2c17 = &i2c_M2; +- i2c18 = &channel_0; +- i2c19 = &channel_1; +- i2c20 = &channel_2; +- i2c21 = &channel_3; +- }; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=tty0 console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- flash_memory: region@98000000 { +- no-map; +- reg = <0x98000000 0x00100000>; /* 1M */ +- }; +- +- gfx_memory: framebuffer { +- size = <0x01000000>; +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- heartbeat { +- gpios = <&gpio ASPEED_GPIO(C, 7) GPIO_ACTIVE_LOW>; +- }; +- +- fault { +- gpios = <&gpio ASPEED_GPIO(G, 3) GPIO_ACTIVE_LOW>; +- }; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, +- <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, +- <&adc 8>, <&adc 9>, <&adc 10>,<&adc 11>, +- <&adc 12>,<&adc 13>,<&adc 14>; +- }; +- +- iio-hwmon-battery { +- compatible = "iio-hwmon"; +- io-channels = <&adc 15>; +- }; +- +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +- spi-max-frequency = <50000000>; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&lpc_ctrl { +- status = "okay"; +- memory-region = <&flash_memory>; +- flash = <&spi1>; +-}; +- +-&lpc_snoop { +- status = "okay"; +- snoop-ports = <0x80>; +-}; +- +-&uart1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default>; +-}; +- +-&uart2 { +- /* Rear RS-232 connector */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd2_default +- &pinctrl_rxd2_default +- &pinctrl_nrts2_default +- &pinctrl_ndtr2_default +- &pinctrl_ndsr2_default +- &pinctrl_ncts2_default +- &pinctrl_ndcd2_default +- &pinctrl_nri2_default>; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&ibt { +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&mac1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +-}; +- +-&adc{ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc0_default +- &pinctrl_adc1_default +- &pinctrl_adc2_default +- &pinctrl_adc3_default +- &pinctrl_adc4_default +- &pinctrl_adc5_default +- &pinctrl_adc6_default +- &pinctrl_adc7_default +- &pinctrl_adc8_default +- &pinctrl_adc9_default +- &pinctrl_adc10_default +- &pinctrl_adc11_default +- &pinctrl_adc12_default +- &pinctrl_adc13_default +- &pinctrl_adc14_default +- &pinctrl_adc15_default>; +-}; +- +-&i2c0 { +- status = "okay"; +- +- i2c-switch@70 { +- compatible = "nxp,pca9545"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c_riser1: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c_riser2: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- i2c_riser3: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c_M2: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- bus-frequency = <90000>; +- HotSwap@10 { +- compatible = "adm1272"; +- reg = <0x10>; +- }; +- +- VR@45 { +- compatible = "pmbus"; +- reg = <0x45>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +- i2c-switch@70 { +- compatible = "nxp,pca9546"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel_0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- channel_1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- channel_2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- channel_3: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- status = "okay"; +- /* temp1 */ +- tmp75@49 { +- compatible = "national,lm75"; +- reg = <0x49>; +- }; +- +- /* temp2 */ +- tmp75@4d { +- compatible = "national,lm75"; +- reg = <0x4d>; +- }; +- +- eeprom@54 { +- compatible = "atmel,24c256"; +- reg = <0x54>; +- pagesize = <16>; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&i2c8 { +- status = "okay"; +-}; +- +-&i2c9 { +- status = "okay"; +-}; +- +-&i2c10 { +- status = "okay"; +-}; +- +-&i2c11 { +- status = "okay"; +-}; +- +-&i2c13 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&uhci { +- status = "okay"; +-}; +- +-&gfx { +- status = "okay"; +- memory-region = <&gfx_memory>; +-}; +- +-&pwm_tacho { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default +- &pinctrl_pwm1_default +- &pinctrl_pwm2_default +- &pinctrl_pwm3_default +- &pinctrl_pwm4_default +- &pinctrl_pwm5_default +- &pinctrl_pwm6_default +- &pinctrl_pwm7_default>; +- +- fan@0 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x00>; +- }; +- +- fan@1 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x01>; +- }; +- +- fan@2 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x02>; +- }; +- +- fan@3 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x03>; +- }; +- +- fan@4 { +- reg = <0x02>; +- aspeed,fan-tach-ch = /bits/ 8 <0x04>; +- }; +- +- fan@5 { +- reg = <0x02>; +- aspeed,fan-tach-ch = /bits/ 8 <0x05>; +- }; +- +- fan@6 { +- reg = <0x03>; +- aspeed,fan-tach-ch = /bits/ 8 <0x06>; +- }; +- +- fan@7 { +- reg = <0x03>; +- aspeed,fan-tach-ch = /bits/ 8 <0x07>; +- }; +- +- fan@8 { +- reg = <0x04>; +- aspeed,fan-tach-ch = /bits/ 8 <0x08>; +- }; +- +- fan@9 { +- reg = <0x04>; +- aspeed,fan-tach-ch = /bits/ 8 <0x09>; +- }; +- +- fan@10 { +- reg = <0x05>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0a>; +- }; +- +- fan@11 { +- reg = <0x05>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0b>; +- }; +- +- fan@12 { +- reg = <0x06>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0c>; +- }; +- +- fan@13 { +- reg = <0x06>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0d>; +- }; +- +- fan@14 { +- reg = <0x07>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0e>; +- }; +- +- fan@15 { +- reg = <0x07>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0f>; +- }; +- +- fan@16 { +- reg = <0x07>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0f>; +- }; +-}; +- +-&gpio { +- +- pin_gpio_a1 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "BMC_EMMC_RST_N"; +- }; +- +- pin_gpio_a3 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "PCH_PWROK_BMC_FPGA"; +- }; +- +- pin_gpio_b5 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "IRQ_BMC_PCH_SMI_LPC_N"; +- }; +- +- pin_gpio_b7 { +- gpio-hog; +- gpios = ; +- output-low; +- line-name = "CPU_SM_WP"; +- }; +- +- pin_gpio_e0 { +- gpio-hog; +- gpios = ; +- input; +- line-name = "PDB_PSU_SEL"; +- }; +- +- pin_gpio_e2 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "LOCATOR_LED_N"; +- }; +- +- pin_gpio_e5 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "FM_BMC_DBP_PRESENT_R1_N"; +- }; +- +- pin_gpio_e6 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "BMC_ME_SECURITY_OVERRIDE_N"; +- }; +- +- pin_gpio_f0 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "IRQ_BMC_PCH_NMI_R"; +- }; +- +- pin_gpio_f1 { +- gpio-hog; +- gpios = ; +- input; +- line-name = "CPU2_PROCDIS_BMC_N"; +- }; +- +- pin_gpio_f2 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "RM_THROTTLE_EN_N"; +- }; +- +- pin_gpio_f3 { +- gpio-hog; +- gpios = ; +- output-low; +- line-name = "FM_PMBUS_ALERT_B_EN"; +- }; +- +- pin_gpio_f4 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "BMC_FORCE_NM_THROTTLE_N"; +- }; +- +- pin_gpio_f6 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "FM_BMC_CPU_PWR_DEBUG_N"; +- }; +- +- pin_gpio_g7 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "BMC_PCIE_I2C_MUX_RST_N"; +- }; +- +- pin_gpio_h6 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "FM_BMC_DBP_PRESENT_R2_N"; +- }; +- +- pin_gpio_i3 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "SPI_BMC_BIOS_WP_N"; +- }; +- +- pin_gpio_j1 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "BMC_USB_SEL"; +- }; +- +- pin_gpio_j2 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "PDB_SMB_RST_N"; +- }; +- +- pin_gpio_j3 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "SPI_BMC_BIOS_HOLD_N"; +- }; +- +- pin_gpio_l0 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "PDB_FAN_TACH_SEL"; +- }; +- +- pin_gpio_l1 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "SYS_RESET_BMC_FPGA_N"; +- }; +- +- pin_gpio_l4 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "FM_EFUSE_FAN_G1_EN"; +- }; +- +- pin_gpio_l5 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "FM_EFUSE_FAN_G2_EN"; +- }; +- +- pin_gpio_r6 { +- gpio-hog; +- gpios = ; +- input; +- line-name = "CPU3_PROCDIS_BMC_N"; +- }; +- +- pin_gpio_r7 { +- gpio-hog; +- gpios = ; +- input; +- line-name = "CPU4_PROCDIS_BMC_N"; +- }; +- +- pin_gpio_s1 { +- gpio-hog; +- gpios = ; +- output-low; +- line-name = "DBP_SYSPWROK_BMC"; +- }; +- +- pin_gpio_s2 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "PCH_RST_RSMRST_N"; +- }; +- +- pin_gpio_s6 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "BMC_HW_STRAP_5"; +- }; +- +- pin_gpio_z3 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "FM_BMC_PCH_SCI_LPC_N"; +- }; +- +- pin_gpio_aa0 { +- gpio-hog; +- gpios = ; +- output-low; +- line-name = "FW_PSU_ALERT_EN_N"; +- }; +- +- pin_gpio_aa4 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "DBP_CPU_PREQ_N"; +- }; +- +- pin_gpio_ab3 { +- gpio-hog; +- gpios = ; +- output-low; +- line-name = "BMC_WDTRST"; +- }; +- +- pin_gpio_ac6 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "ESPI_BMC_ALERT_N"; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-microsoft-olympus.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-microsoft-olympus.dts +deleted file mode 100644 +index 3ef8358ff764..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-microsoft-olympus.dts ++++ /dev/null +@@ -1,207 +0,0 @@ +-//SPDX-License-Identifier: GPL-2.0+ +- +-/dts-v1/; +- +-#include "aspeed-g4.dtsi" +-#include +- +-/ { +- model = "Olympus BMC"; +- compatible = "microsoft,olympus-bmc", "aspeed,ast2400"; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@40000000 { +- reg = <0x40000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- vga_memory: framebuffer@5f000000 { +- no-map; +- reg = <0x5f000000 0x01000000>; /* 16M */ +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- bmc_heartbeat { +- gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>; +- }; +- +- power_green { +- gpios = <&gpio ASPEED_GPIO(U, 2) GPIO_ACTIVE_HIGH>; +- }; +- +- power_amber { +- gpios = <&gpio ASPEED_GPIO(U, 3) GPIO_ACTIVE_HIGH>; +- }; +- +- identify { +- gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>; +- }; +- +- fault { +- gpios = <&gpio ASPEED_GPIO(A, 1) GPIO_ACTIVE_LOW>; +- }; +- }; +- +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, +- <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; +- }; +-}; +- +-&adc { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc0_default +- &pinctrl_adc1_default +- &pinctrl_adc2_default +- &pinctrl_adc3_default +- &pinctrl_adc4_default +- &pinctrl_adc5_default +- &pinctrl_adc6_default +- &pinctrl_adc7_default>; +-}; +- +-&fmc { +- status = "okay"; +- +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&spi { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "pnor"; +- }; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- +- tmp421@4c { +- compatible = "ti,tmp421"; +- reg = <0x4c>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- status = "okay"; +- +- tmp421@4c { +- compatible = "ti,tmp421"; +- reg = <0x4c>; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&vuart { +- status = "okay"; +-}; +- +-&wdt2 { +- status = "okay"; +-}; +- +-&lpc_ctrl { +- status = "okay"; +-}; +- +-&pwm_tacho { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default +- &pinctrl_pwm1_default +- &pinctrl_pwm2_default +- &pinctrl_pwm3_default +- &pinctrl_pwm4_default +- &pinctrl_pwm5_default +- &pinctrl_pwm6_default>; +- +- fan@0 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x00>; +- }; +- +- fan@1 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x01>; +- }; +- +- fan@2 { +- reg = <0x02>; +- aspeed,fan-tach-ch = /bits/ 8 <0x02>; +- }; +- +- fan@3 { +- reg = <0x03>; +- aspeed,fan-tach-ch = /bits/ 8 <0x03>; +- }; +- +- fan@4 { +- reg = <0x04>; +- aspeed,fan-tach-ch = /bits/ 8 <0x04>; +- }; +- +- fan@5 { +- reg = <0x05>; +- aspeed,fan-tach-ch = /bits/ 8 <0x05>; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-lanyang.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-lanyang.dts +deleted file mode 100644 +index c0847636f20b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-lanyang.dts ++++ /dev/null +@@ -1,329 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright (c) 2018 Inventec Corporation +-/dts-v1/; +- +-#include "aspeed-g5.dtsi" +-#include +- +-/ { +- model = "Lanyang BMC"; +- compatible = "inventec,lanyang-bmc", "aspeed,ast2500"; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x40000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- flash_memory: region@98000000 { +- no-map; +- reg = <0x98000000 0x04000000>; /* 64M */ +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- sys_boot_status { +- label = "System_boot_status"; +- gpios = <&gpio ASPEED_GPIO(B, 6) GPIO_ACTIVE_LOW>; +- }; +- +- attention { +- label = "Attention_locator"; +- gpios = <&gpio ASPEED_GPIO(B, 7) GPIO_ACTIVE_HIGH>; +- }; +- +- plt_fault { +- label = "Platform_fault"; +- gpios = <&gpio ASPEED_GPIO(B, 1) GPIO_ACTIVE_HIGH>; +- }; +- +- hdd_fault { +- label = "Onboard_drive_fault"; +- gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_HIGH>; +- }; +- bmc_err { +- lable = "BMC_fault"; +- gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>; +- }; +- +- sys_err { +- lable = "Sys_fault"; +- gpios = <&gpio ASPEED_GPIO(H, 7) GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- fsi: gpio-fsi { +- compatible = "fsi-master-gpio", "fsi-master"; +- #address-cells = <2>; +- #size-cells = <0>; +- +- clock-gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_HIGH>; +- data-gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>; +- trans-gpios = <&gpio ASPEED_GPIO(D, 5) GPIO_ACTIVE_HIGH>; +- enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; +- mux-gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, +- <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, +- <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, +- <&adc 13>, <&adc 14>, <&adc 15>; +- }; +- +- iio-hwmon-battery { +- compatible = "iio-hwmon"; +- io-channels = <&adc 12>; +- }; +-}; +- +-&pwm_tacho { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default +- &pinctrl_pwm2_default &pinctrl_pwm3_default>; +- +- fan@0 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x00>; +- }; +- +- fan@1 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x01>; +- }; +- +- fan@2 { +- reg = <0x02>; +- aspeed,fan-tach-ch = /bits/ 8 <0x02>; +- }; +- +- fan@3 { +- reg = <0x03>; +- aspeed,fan-tach-ch = /bits/ 8 <0x03>; +- }; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- +- flash@0 { +- status = "okay"; +- label = "pnor"; +- m25p,fast-read; +- }; +-}; +- +-&spi2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi2ck_default +- &pinctrl_spi2cs0_default +- &pinctrl_spi2cs1_default +- &pinctrl_spi2miso_default +- &pinctrl_spi2mosi_default>; +- +- flash@0 { +- status = "okay"; +- }; +-}; +- +-&uart1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default>; +-}; +- +-&lpc_ctrl { +- status = "okay"; +- memory-region = <&flash_memory>; +- flash = <&spi1>; +-}; +- +-&lpc_snoop { +- status = "okay"; +- snoop-ports = <0x80>; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&mac1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +-}; +- +-&i2c0 { +- status = "okay"; +- +- eeprom@55 { +- compatible = "atmel,24c64"; +- reg = <0x55>; +- pagesize = <32>; +- }; +- +- rtc@68 { +- compatible = "nxp,pcf8523"; +- reg = <0x68>; +- }; +- +- tmp75@48 { +- compatible = "ti,tmp75"; +- reg = <0x48>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- status = "okay"; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&i2c8 { +- status = "okay"; +-}; +- +-&i2c9 { +- status = "okay"; +-}; +- +-&i2c10 { +- status = "okay"; +-}; +- +-&i2c11 { +- status = "okay"; +-}; +- +-&vuart { +- status = "okay"; +-}; +- +-&gfx { +- status = "okay"; +-}; +- +-&pinctrl { +- aspeed,external-nodes = <&gfx &lhc>; +-}; +- +-&gpio { +- pin_gpio_b0 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "BMC_HDD1_PWR_EN"; +- }; +- +- pin_gpio_b5 { +- gpio-hog; +- gpios = ; +- input; +- line-name = "BMC_USB1_OCI2"; +- }; +- +- pin_gpio_h5 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "BMC_CP0_PERST_ENABLE_R"; +- }; +- +- pin_gpio_z2 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "RST_PCA9546_U177_N"; +- }; +- +- pin_gpio_aa6 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "BMC_CP0_RESET_N"; +- }; +- +- pin_gpio_aa7 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "BMC_TPM_RESET_N"; +- }; +- +- pin_gpio_ab0 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "BMC_USB_PWRON_N"; +- }; +-}; +- +-&ibt { +- status = "okay"; +-}; +- +-&adc { +- status = "okay"; +-}; +- +-#include "ibm-power9-dual.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-mihawk.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-mihawk.dts +deleted file mode 100644 +index a52a289cee85..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-mihawk.dts ++++ /dev/null +@@ -1,1380 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/dts-v1/; +-#include "aspeed-g5.dtsi" +-#include +-#include +- +-/ { +- model = "Mihawk BMC"; +- compatible = "ibm,mihawk-bmc", "aspeed,ast2500"; +- +- aliases { +- i2c215 = &bus6_mux215; +- i2c216 = &bus6_mux216; +- i2c217 = &bus6_mux217; +- i2c218 = &bus6_mux218; +- i2c219 = &bus6_mux219; +- i2c220 = &bus6_mux220; +- i2c221 = &bus6_mux221; +- i2c222 = &bus6_mux222; +- i2c223 = &bus7_mux223; +- i2c224 = &bus7_mux224; +- i2c225 = &bus7_mux225; +- i2c226 = &bus7_mux226; +- i2c227 = &bus7_mux227; +- i2c228 = &bus7_mux228; +- i2c229 = &bus7_mux229; +- i2c230 = &bus7_mux230; +- i2c231 = &bus9_mux231; +- i2c232 = &bus9_mux232; +- i2c233 = &bus9_mux233; +- i2c234 = &bus9_mux234; +- i2c235 = &bus9_mux235; +- i2c236 = &bus9_mux236; +- i2c237 = &bus9_mux237; +- i2c238 = &bus9_mux238; +- i2c239 = &bus10_mux239; +- i2c240 = &bus10_mux240; +- i2c241 = &bus10_mux241; +- i2c242 = &bus10_mux242; +- i2c243 = &bus10_mux243; +- i2c244 = &bus10_mux244; +- i2c245 = &bus10_mux245; +- i2c246 = &bus10_mux246; +- i2c247 = &bus12_mux247; +- i2c248 = &bus12_mux248; +- i2c249 = &bus12_mux249; +- i2c250 = &bus12_mux250; +- i2c251 = &bus13_mux251; +- i2c252 = &bus13_mux252; +- i2c253 = &bus13_mux253; +- i2c254 = &bus13_mux254; +- i2c255 = &bus13_mux255; +- i2c256 = &bus13_mux256; +- i2c257 = &bus13_mux257; +- i2c258 = &bus13_mux258; +- }; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- flash_memory: region@98000000 { +- no-map; +- reg = <0x98000000 0x04000000>; /* 64M */ +- }; +- +- gfx_memory: framebuffer { +- size = <0x01000000>; +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- +- video_engine_memory: jpegbuffer { +- size = <0x02000000>; +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- air-water { +- label = "air-water"; +- gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- checkstop { +- label = "checkstop"; +- gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- ps0-presence { +- label = "ps0-presence"; +- gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- ps1-presence { +- label = "ps1-presence"; +- gpios = <&gpio ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- id-button { +- label = "id-button"; +- gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- poll-interval = <1000>; +- +- fan0-presence { +- label = "fan0-presence"; +- gpios = <&pca9552 9 GPIO_ACTIVE_LOW>; +- linux,code = <9>; +- }; +- +- fan1-presence { +- label = "fan1-presence"; +- gpios = <&pca9552 10 GPIO_ACTIVE_LOW>; +- linux,code = <10>; +- }; +- +- fan2-presence { +- label = "fan2-presence"; +- gpios = <&pca9552 11 GPIO_ACTIVE_LOW>; +- linux,code = <11>; +- }; +- +- fan3-presence { +- label = "fan3-presence"; +- gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; +- linux,code = <12>; +- }; +- +- fan4-presence { +- label = "fan4-presence"; +- gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; +- linux,code = <13>; +- }; +- +- fan5-presence { +- label = "fan5-presence"; +- gpios = <&pca9552 14 GPIO_ACTIVE_LOW>; +- linux,code = <14>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- front-fault { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>; +- }; +- +- power-button { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_LOW>; +- }; +- +- front-id { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>; +- }; +- +- +- fan0 { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca9552 0 GPIO_ACTIVE_LOW>; +- }; +- +- fan1 { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca9552 1 GPIO_ACTIVE_LOW>; +- }; +- +- fan2 { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca9552 2 GPIO_ACTIVE_LOW>; +- }; +- +- fan3 { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca9552 3 GPIO_ACTIVE_LOW>; +- }; +- +- fan4 { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca9552 4 GPIO_ACTIVE_LOW>; +- }; +- +- fan5 { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca9552 5 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- fsi: gpio-fsi { +- compatible = "fsi-master-gpio", "fsi-master"; +- #address-cells = <2>; +- #size-cells = <0>; +- no-gpio-delays; +- +- clock-gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_HIGH>; +- data-gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_HIGH>; +- mux-gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_HIGH>; +- enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; +- trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; +- }; +- iio-hwmon-12v { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>; +- }; +- +- iio-hwmon-5v { +- compatible = "iio-hwmon"; +- io-channels = <&adc 1>; +- }; +- +- iio-hwmon-3v { +- compatible = "iio-hwmon"; +- io-channels = <&adc 2>; +- }; +- +- iio-hwmon-vdd0 { +- compatible = "iio-hwmon"; +- io-channels = <&adc 3>; +- }; +- +- iio-hwmon-vdd1 { +- compatible = "iio-hwmon"; +- io-channels = <&adc 4>; +- }; +- +- iio-hwmon-vcs0 { +- compatible = "iio-hwmon"; +- io-channels = <&adc 5>; +- }; +- +- iio-hwmon-vcs1 { +- compatible = "iio-hwmon"; +- io-channels = <&adc 6>; +- }; +- +- iio-hwmon-vdn0 { +- compatible = "iio-hwmon"; +- io-channels = <&adc 7>; +- }; +- +- iio-hwmon-vdn1 { +- compatible = "iio-hwmon"; +- io-channels = <&adc 8>; +- }; +- +- iio-hwmon-vio0 { +- compatible = "iio-hwmon"; +- io-channels = <&adc 9>; +- }; +- +- iio-hwmon-vio1 { +- compatible = "iio-hwmon"; +- io-channels = <&adc 10>; +- }; +- +- iio-hwmon-vddra { +- compatible = "iio-hwmon"; +- io-channels = <&adc 11>; +- }; +- +- iio-hwmon-battery { +- compatible = "iio-hwmon"; +- io-channels = <&adc 12>; +- }; +- +- iio-hwmon-vddrb { +- compatible = "iio-hwmon"; +- io-channels = <&adc 13>; +- }; +- +- iio-hwmon-vddrc { +- compatible = "iio-hwmon"; +- io-channels = <&adc 14>; +- }; +- +- iio-hwmon-vddrd { +- compatible = "iio-hwmon"; +- io-channels = <&adc 15>; +- }; +-}; +- +-&pwm_tacho { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default +- &pinctrl_pwm2_default &pinctrl_pwm3_default +- &pinctrl_pwm4_default &pinctrl_pwm5_default>; +- +- fan@0 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x00>; +- }; +- +- fan@1 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x01>; +- }; +- +- fan@2 { +- reg = <0x02>; +- aspeed,fan-tach-ch = /bits/ 8 <0x02>; +- }; +- +- fan@3 { +- reg = <0x03>; +- aspeed,fan-tach-ch = /bits/ 8 <0x03>; +- }; +- +- fan@4 { +- reg = <0x04>; +- aspeed,fan-tach-ch = /bits/ 8 <0x04>; +- }; +- +- fan@5 { +- reg = <0x05>; +- aspeed,fan-tach-ch = /bits/ 8 <0x05>; +- }; +- +- fan@6 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x06>; +- }; +- +- fan@7 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x07>; +- }; +- +- fan@8 { +- reg = <0x02>; +- aspeed,fan-tach-ch = /bits/ 8 <0x08>; +- }; +- +- fan@9 { +- reg = <0x03>; +- aspeed,fan-tach-ch = /bits/ 8 <0x09>; +- }; +- +- fan@10 { +- reg = <0x04>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0a>; +- }; +- +- fan@11 { +- reg = <0x05>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0b>; +- }; +-}; +- +-&gpio { +- gpio-line-names = +- /*A0-A7*/ "","cfam-reset","","","","","","", +- /*B0-B7*/ "","","","","","","","", +- /*C0-C7*/ "","","","","","","","", +- /*D0-D7*/ "fsi-enable","","","","","","","", +- /*E0-E7*/ "","","","","","fsi-mux","fsi-clock","fsi-data", +- /*F0-F7*/ "","id-button","","","","","air-water","", +- /*G0-G7*/ "","","","","","","","", +- /*H0-H7*/ "","","","","","","","", +- /*I0-I7*/ "","","","","","","","", +- /*J0-J7*/ "","","checkstop","","","","","", +- /*K0-K7*/ "","","","","","","","", +- /*L0-L7*/ "","","","","","","","", +- /*M0-M7*/ "","","","","","","","", +- /*N0-N7*/ "","","","","","","","", +- /*O0-O7*/ "","","","","","","","", +- /*P0-P7*/ "","","","","","","","", +- /*Q0-Q7*/ "","","","","","","","", +- /*R0-R7*/ "","","fsi-trans","","","","","", +- /*S0-S7*/ "","","","","","","","", +- /*T0-T7*/ "","","","","","","","", +- /*U0-U7*/ "","","","","","","","", +- /*V0-V7*/ "","","","","","","","", +- /*W0-W7*/ "","","","","","","","", +- /*X0-X7*/ "","","","","","","","", +- /*Y0-Y7*/ "","","","","","","","", +- /*Z0-Z7*/ "presence-ps1","","presence-ps0","","","","","", +- /*AA0-AA7*/ "led-front-fault","power-button","led-front-id","","","","","", +- /*AB0-AB7*/ "","","","","","","","", +- /*AC0-AC7*/ "","","","","","","",""; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- label = "bmc"; +- m25p,fast-read; +- spi-max-frequency = <50000000>; +- partitions { +- #address-cells = < 1 >; +- #size-cells = < 1 >; +- compatible = "fixed-partitions"; +- u-boot@0 { +- reg = < 0 0x60000 >; +- label = "u-boot"; +- }; +- u-boot-env@60000 { +- reg = < 0x60000 0x20000 >; +- label = "u-boot-env"; +- }; +- obmc-ubi@80000 { +- reg = < 0x80000 0x1F80000 >; +- label = "obmc-ubi"; +- }; +- }; +- }; +- flash@1 { +- status = "okay"; +- label = "alt-bmc"; +- m25p,fast-read; +- spi-max-frequency = <50000000>; +- partitions { +- #address-cells = < 1 >; +- #size-cells = < 1 >; +- compatible = "fixed-partitions"; +- u-boot@0 { +- reg = < 0 0x60000 >; +- label = "alt-u-boot"; +- }; +- u-boot-env@60000 { +- reg = < 0x60000 0x20000 >; +- label = "alt-u-boot-env"; +- }; +- obmc-ubi@80000 { +- reg = < 0x80000 0x1F80000 >; +- label = "alt-obmc-ubi"; +- }; +- }; +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- +- flash@0 { +- status = "okay"; +- label = "pnor"; +- m25p,fast-read; +- spi-max-frequency = <100000000>; +- }; +-}; +- +-&lpc_ctrl { +- status = "okay"; +- memory-region = <&flash_memory>; +- flash = <&spi1>; +-}; +- +-&uart1 { +- /* Rear RS-232 connector */ +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default +- &pinctrl_nrts1_default +- &pinctrl_ndtr1_default +- &pinctrl_ndsr1_default +- &pinctrl_ncts1_default +- &pinctrl_ndcd1_default +- &pinctrl_nri1_default>; +-}; +- +-&uart2 { +- /* APSS */ +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&mac1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +-}; +- +-&i2c0 { +- status = "disabled"; +-}; +- +-&i2c1 { +- status = "disabled"; +-}; +- +-&i2c2 { +- status = "okay"; +- +- /* SAMTEC P0 */ +- /* SAMTEC P1 */ +- +-}; +- +-&i2c3 { +- status = "okay"; +- +- /* APSS */ +- /* CPLD */ +- +- /* PCA9516 (repeater) -> +- * CLK Buffer 9FGS9092 +- * CLK Buffer 9DBL0651BKILFT +- * CLK Buffer 9DBL0651BKILFT +- * Power Supply 0 +- * Power Supply 1 +- * PCA 9552 LED +- */ +- +- power-supply@58 { +- compatible = "ibm,cffps1"; +- reg = <0x58>; +- }; +- +- power-supply@5b { +- compatible = "ibm,cffps1"; +- reg = <0x5b>; +- }; +- +- pca9552: pca9552@60 { +- compatible = "nxp,pca9552"; +- reg = <0x60>; +- #address-cells = <1>; +- #size-cells = <0>; +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- gpio@8 { +- reg = <8>; +- type = ; +- }; +- gpio@9 { +- reg = <9>; +- type = ; +- }; +- gpio@10 { +- reg = <10>; +- type = ; +- }; +- gpio@11 { +- reg = <11>; +- type = ; +- }; +- gpio@12 { +- reg = <12>; +- type = ; +- }; +- gpio@13 { +- reg = <13>; +- type = ; +- }; +- gpio@14 { +- reg = <14>; +- type = ; +- }; +- gpio@15 { +- reg = <15>; +- type = ; +- }; +- +- }; +- +-}; +- +-&i2c4 { +- status = "okay"; +- +- /* CP0 VDD & VCS : IR35221 */ +- /* CP0 VDN : IR35221 */ +- /* CP0 VIO : IR38064 */ +- /* CP0 VDDR : PXM1330 */ +- +- ir35221@70 { +- compatible = "infineon,ir35221"; +- reg = <0x70>; +- }; +- +- ir35221@72 { +- compatible = "infineon,ir35221"; +- reg = <0x72>; +- }; +- +-}; +- +-&i2c5 { +- status = "okay"; +- +- /* CP0 VDD & VCS : IR35221 */ +- /* CP0 VDN : IR35221 */ +- /* CP0 VIO : IR38064 */ +- /* CP0 VDDR : PXM1330 */ +- +- ir35221@70 { +- compatible = "infineon,ir35221"; +- reg = <0x70>; +- }; +- +- ir35221@72 { +- compatible = "infineon,ir35221"; +- reg = <0x72>; +- }; +- +-}; +- +-&i2c6 { +- status = "okay"; +- +- /* pca9548 -> NVMe1 to 8 */ +- +- pca9548@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- +- bus7_mux223: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- bus7_mux224: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- bus7_mux225: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- bus7_mux226: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- bus7_mux227: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- bus7_mux228: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- bus7_mux229: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- bus7_mux230: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +-}; +- +-&i2c7 { +- status = "okay"; +- +- /* pca9548 -> NVMe9 to 16 */ +- +- pca9548@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- +- bus6_mux215: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- bus6_mux216: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- bus6_mux217: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- bus6_mux218: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- bus6_mux219: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- bus6_mux220: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- bus6_mux221: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- bus6_mux222: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +- +-}; +- +-&i2c8 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +-}; +- +-&i2c9 { +- status = "okay"; +- +- /* pca9545 Riser -> +- * PCIe x8 Slot3 +- * PCIe x16 slot4 +- * PCIe x8 slot5 +- * I2C BMC RISER PCA9554 +- * BMC SCL/SDA PCA9554 +- * PCA9554 +- */ +- +- /* pca9545 -> +- * PCIe x16 Slot1 +- * PCIe x8 slot2 +- * PEX8748 +- */ +- +- pca9545riser@70 { +- compatible = "nxp,pca9545"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- +- i2c-mux-idle-disconnect; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- bus9_mux231: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- tca9554@39 { +- compatible = "ti,tca9554"; +- reg = <0x39>; +- gpio-controller; +- #gpio-cells = <2>; +- +- smbus0-hog { +- gpio-hog; +- gpios = <4 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "smbus0"; +- }; +- }; +- +- tmp431@4c { +- compatible = "ti,tmp401"; +- reg = <0x4c>; +- }; +- }; +- +- bus9_mux232: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tca9554@39 { +- compatible = "ti,tca9554"; +- reg = <0x39>; +- gpio-controller; +- #gpio-cells = <2>; +- +- smbus1-hog { +- gpio-hog; +- gpios = <4 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "smbus1"; +- }; +- }; +- +- tmp431@4c { +- compatible = "ti,tmp401"; +- reg = <0x4c>; +- }; +- }; +- +- bus9_mux233: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- bus9_mux234: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +- +- pca9545@71 { +- compatible = "nxp,pca9545"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x71>; +- +- i2c-mux-idle-disconnect; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- bus9_mux235: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- tca9554@39 { +- compatible = "ti,tca9554"; +- reg = <0x39>; +- gpio-controller; +- #gpio-cells = <2>; +- +- smbus2-hog { +- gpio-hog; +- gpios = <4 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "smbus2"; +- }; +- }; +- +- tmp431@4c { +- compatible = "ti,tmp401"; +- reg = <0x4c>; +- }; +- }; +- +- bus9_mux236: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tca9554@39 { +- compatible = "ti,tca9554"; +- reg = <0x39>; +- gpio-controller; +- #gpio-cells = <2>; +- +- smbus3-hog { +- gpio-hog; +- gpios = <4 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "smbus3"; +- }; +- }; +- +- tmp431@4c { +- compatible = "ti,tmp401"; +- reg = <0x4c>; +- }; +- }; +- +- bus9_mux237: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- bus9_mux238: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +-}; +- +-&i2c10 { +- status = "okay"; +- +- /* pca9545 Riser -> +- * PCIe x8 Slot8 +- * PCIe x16 slot9 +- * PCIe x8 slot10 +- * I2C BMC RISER PCA9554 +- * BMC SCL/SDA PCA9554 +- * PCA9554 +- */ +- +- /* pca9545 -> +- * PCIe x16 Slot1 +- * PCIe x8 slot2 +- * PEX8748 +- */ +- +- pca9545riser@70 { +- compatible = "nxp,pca9545"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- +- i2c-mux-idle-disconnect; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- bus10_mux239: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- tca9554@39 { +- compatible = "ti,tca9554"; +- reg = <0x39>; +- gpio-controller; +- #gpio-cells = <2>; +- +- smbus4-hog { +- gpio-hog; +- gpios = <4 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "smbus4"; +- }; +- }; +- +- tmp431@4c { +- compatible = "ti,tmp401"; +- reg = <0x4c>; +- }; +- }; +- +- bus10_mux240: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tca9554@39 { +- compatible = "ti,tca9554"; +- reg = <0x39>; +- gpio-controller; +- #gpio-cells = <2>; +- +- smbus5-hog { +- gpio-hog; +- gpios = <4 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "smbus5"; +- }; +- }; +- +- tmp431@4c { +- compatible = "ti,tmp401"; +- reg = <0x4c>; +- }; +- }; +- +- bus10_mux241: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- bus10_mux242: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +- +- pca9545@71 { +- compatible = "nxp,pca9545"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x71>; +- +- i2c-mux-idle-disconnect; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- bus10_mux243: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- tca9554@39 { +- compatible = "ti,tca9554"; +- reg = <0x39>; +- gpio-controller; +- #gpio-cells = <2>; +- +- smbus6-hog { +- gpio-hog; +- gpios = <4 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "smbus6"; +- }; +- }; +- +- tmp431@4c { +- compatible = "ti,tmp401"; +- reg = <0x4c>; +- }; +- }; +- +- bus10_mux244: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tca9554@39 { +- compatible = "ti,tca9554"; +- reg = <0x39>; +- gpio-controller; +- #gpio-cells = <2>; +- +- smbus7-hog { +- gpio-hog; +- gpios = <4 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "smbus7"; +- }; +- }; +- +- tmp431@4c { +- compatible = "ti,tmp401"; +- reg = <0x4c>; +- }; +- }; +- +- bus10_mux245: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- bus10_mux246: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +-}; +- +-&i2c11 { +- status = "okay"; +- +- /* TPM */ +- /* RTC RX8900CE */ +- /* FPGA for power sequence */ +- /* TMP275A */ +- /* TMP275A */ +- /* EMC1462 */ +- +- tpm@57 { +- compatible = "infineon,slb9645tt"; +- reg = <0x57>; +- }; +- +- rtc@32 { +- compatible = "epson,rx8900"; +- reg = <0x32>; +- }; +- +- tmp275@48 { +- compatible = "ti,tmp275"; +- reg = <0x48>; +- }; +- +- tmp275@49 { +- compatible = "ti,tmp275"; +- reg = <0x49>; +- }; +- +- /* chip emc1462 use emc1403 driver */ +- emc1403@4c { +- compatible = "smsc,emc1403"; +- reg = <0x4c>; +- }; +- +-}; +- +-&i2c12 { +- status = "okay"; +- +- /* pca9545 -> +- * SAS BP1 +- * SAS BP2 +- * NVMe BP +- * M.2 riser +- */ +- +- pca9545@70 { +- compatible = "nxp,pca9545"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- bus12_mux247: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- }; +- +- bus12_mux248: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- }; +- +- bus12_mux249: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- }; +- +- bus12_mux250: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- tmp275@48 { +- compatible = "ti,tmp275"; +- reg = <0x48>; +- }; +- }; +- +- }; +- +-}; +- +-&i2c13 { +- status = "okay"; +- +- /* pca9548 -> +- * NVMe BP +- * NVMe HDD17 to 24 +- */ +- +- pca9548@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- bus13_mux251: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- bus13_mux252: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- bus13_mux253: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- bus13_mux254: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- bus13_mux255: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- bus13_mux256: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- bus13_mux257: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- bus13_mux258: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +-}; +- +-&vuart { +- status = "okay"; +-}; +- +-&gfx { +- status = "okay"; +- memory-region = <&gfx_memory>; +-}; +- +-&adc { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc0_default +- &pinctrl_adc1_default +- &pinctrl_adc2_default +- &pinctrl_adc3_default +- &pinctrl_adc4_default +- &pinctrl_adc5_default +- &pinctrl_adc6_default +- &pinctrl_adc7_default +- &pinctrl_adc8_default +- &pinctrl_adc9_default +- &pinctrl_adc10_default +- &pinctrl_adc11_default +- &pinctrl_adc12_default +- &pinctrl_adc13_default +- &pinctrl_adc14_default +- &pinctrl_adc15_default>; +-}; +- +-&wdt1 { +- aspeed,reset-type = "none"; +- aspeed,external-signal; +- aspeed,ext-push-pull; +- aspeed,ext-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdtrst1_default>; +-}; +- +-&wdt2 { +- aspeed,alt-boot; +-}; +- +-&ibt { +- status = "okay"; +-}; +- +-&vhub { +- status = "okay"; +-}; +- +-&video { +- status = "okay"; +- memory-region = <&video_engine_memory>; +-}; +- +-#include "ibm-power9-dual.dtsi" +- +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-mowgli.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-mowgli.dts +deleted file mode 100644 +index 7d38d121ec6d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-mowgli.dts ++++ /dev/null +@@ -1,667 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/dts-v1/; +-#include "aspeed-g5.dtsi" +-#include +-#include +- +-/ { +- model = "Mowgli BMC"; +- compatible = "ibm,mowgli-bmc", "aspeed,ast2500"; +- +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- flash_memory: region@98000000 { +- no-map; +- reg = <0x98000000 0x04000000>; /* 64M */ +- }; +- +- gfx_memory: framebuffer { +- size = <0x01000000>; +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- +- video_engine_memory: jpegbuffer { +- size = <0x02000000>; +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- air-water { +- label = "air-water"; +- gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- checkstop { +- label = "checkstop"; +- gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- ps0-presence { +- label = "ps0-presence"; +- gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- ps1-presence { +- label = "ps1-presence"; +- gpios = <&gpio ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- id-button { +- label = "id-button"; +- gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- poll-interval = <1000>; +- +- fan0-presence { +- label = "fan0-presence"; +- gpios = <&pca9552 9 GPIO_ACTIVE_LOW>; +- linux,code = <9>; +- }; +- +- fan1-presence { +- label = "fan1-presence"; +- gpios = <&pca9552 10 GPIO_ACTIVE_LOW>; +- linux,code = <10>; +- }; +- +- fan2-presence { +- label = "fan2-presence"; +- gpios = <&pca9552 11 GPIO_ACTIVE_LOW>; +- linux,code = <11>; +- }; +- +- fan3-presence { +- label = "fan3-presence"; +- gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; +- linux,code = <12>; +- }; +- +- fan4-presence { +- label = "fan4-presence"; +- gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; +- linux,code = <13>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- front-fault { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>; +- }; +- +- power-button { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_LOW>; +- }; +- +- front-id { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>; +- }; +- +- fan0 { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca9552 0 GPIO_ACTIVE_LOW>; +- }; +- +- fan1 { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca9552 1 GPIO_ACTIVE_LOW>; +- }; +- +- fan2 { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca9552 2 GPIO_ACTIVE_LOW>; +- }; +- +- fan3 { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca9552 3 GPIO_ACTIVE_LOW>; +- }; +- +- fan4 { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca9552 4 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- fsi: gpio-fsi { +- compatible = "fsi-master-gpio", "fsi-master"; +- #address-cells = <2>; +- #size-cells = <0>; +- no-gpio-delays; +- +- clock-gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_HIGH>; +- data-gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_HIGH>; +- mux-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; +- enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; +- trans-gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_HIGH>; +- }; +- +- iio-hwmon-12v { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>; +- }; +- +- iio-hwmon-5v { +- compatible = "iio-hwmon"; +- io-channels = <&adc 1>; +- }; +- +- iio-hwmon-3v { +- compatible = "iio-hwmon"; +- io-channels = <&adc 2>; +- }; +- +- iio-hwmon-vdd { +- compatible = "iio-hwmon"; +- io-channels = <&adc 3>; +- }; +- +- iio-hwmon-vcs { +- compatible = "iio-hwmon"; +- io-channels = <&adc 5>; +- }; +- +- iio-hwmon-vdn { +- compatible = "iio-hwmon"; +- io-channels = <&adc 7>; +- }; +- +- iio-hwmon-vio { +- compatible = "iio-hwmon"; +- io-channels = <&adc 9>; +- }; +- +- iio-hwmon-vddra { +- compatible = "iio-hwmon"; +- io-channels = <&adc 11>; +- }; +- +- iio-hwmon-battery { +- compatible = "iio-hwmon"; +- io-channels = <&adc 12>; +- }; +- +- iio-hwmon-vddrb { +- compatible = "iio-hwmon"; +- io-channels = <&adc 13>; +- }; +-}; +- +-&pwm_tacho { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default +- &pinctrl_pwm2_default &pinctrl_pwm3_default +- &pinctrl_pwm4_default>; +- +- fan@0 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x00>; +- }; +- +- fan@1 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x01>; +- }; +- +- fan@2 { +- reg = <0x02>; +- aspeed,fan-tach-ch = /bits/ 8 <0x02>; +- }; +- +- fan@3 { +- reg = <0x03>; +- aspeed,fan-tach-ch = /bits/ 8 <0x03>; +- }; +- +- fan@4 { +- reg = <0x04>; +- aspeed,fan-tach-ch = /bits/ 8 <0x04>; +- }; +- +- fan@5 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x05>; +- }; +- +- fan@6 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x06>; +- }; +- +- fan@7 { +- reg = <0x02>; +- aspeed,fan-tach-ch = /bits/ 8 <0x07>; +- }; +- +- fan@8 { +- reg = <0x03>; +- aspeed,fan-tach-ch = /bits/ 8 <0x08>; +- }; +- +- fan@9 { +- reg = <0x04>; +- aspeed,fan-tach-ch = /bits/ 8 <0x09>; +- }; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- label = "bmc"; +- m25p,fast-read; +- spi-max-frequency = <50000000>; +- partitions { +- #address-cells = < 1 >; +- #size-cells = < 1 >; +- compatible = "fixed-partitions"; +- u-boot@0 { +- reg = < 0 0x60000 >; +- label = "u-boot"; +- }; +- u-boot-env@60000 { +- reg = < 0x60000 0x20000 >; +- label = "u-boot-env"; +- }; +- obmc-ubi@80000 { +- reg = < 0x80000 0x1F80000 >; +- label = "obmc-ubi"; +- }; +- }; +- }; +- flash@1 { +- status = "okay"; +- label = "alt-bmc"; +- m25p,fast-read; +- spi-max-frequency = <50000000>; +- partitions { +- #address-cells = < 1 >; +- #size-cells = < 1 >; +- compatible = "fixed-partitions"; +- u-boot@0 { +- reg = < 0 0x60000 >; +- label = "alt-u-boot"; +- }; +- u-boot-env@60000 { +- reg = < 0x60000 0x20000 >; +- label = "alt-u-boot-env"; +- }; +- obmc-ubi@80000 { +- reg = < 0x80000 0x1F80000 >; +- label = "alt-obmc-ubi"; +- }; +- }; +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- +- flash@0 { +- status = "okay"; +- label = "pnor"; +- m25p,fast-read; +- spi-max-frequency = <100000000>; +- }; +-}; +- +-&lpc_ctrl { +- status = "okay"; +- memory-region = <&flash_memory>; +- flash = <&spi1>; +-}; +- +-&uart1 { +- /* Rear RS-232 connector */ +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default +- &pinctrl_nrts1_default +- &pinctrl_ndtr1_default +- &pinctrl_ndsr1_default +- &pinctrl_ncts1_default +- &pinctrl_ndcd1_default +- &pinctrl_nri1_default>; +-}; +- +-&uart2 { +- /* APSS */ +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&mac1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +-}; +- +-&i2c0 { +- status = "okay"; +- +- tmp275@48 { +- compatible = "ti,tmp275"; +- reg = <0x48>; +- }; +-}; +- +-&i2c1 { +- status = "disabled"; +-}; +- +-&i2c2 { +- status = "okay"; +- +- /* CPU MFG CONN */ +- +-}; +- +-&i2c3 { +- status = "okay"; +- +- /* APSS */ +- /* CPLD */ +- +- /* PCA9516 (repeater) -> +- * CLK Buffer 9FGS9092 +- * Power Supply 0 +- * Power Supply 1 +- * PCA 9552 LED +- */ +- +- pca9552: pca9552@60 { +- compatible = "nxp,pca9552"; +- reg = <0x60>; +- #address-cells = <1>; +- #size-cells = <0>; +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- gpio@8 { +- reg = <8>; +- type = ; +- }; +- gpio@9 { +- reg = <9>; +- type = ; +- }; +- gpio@10 { +- reg = <10>; +- type = ; +- }; +- gpio@11 { +- reg = <11>; +- type = ; +- }; +- gpio@12 { +- reg = <12>; +- type = ; +- }; +- gpio@13 { +- reg = <13>; +- type = ; +- }; +- gpio@14 { +- reg = <14>; +- type = ; +- }; +- gpio@15 { +- reg = <15>; +- type = ; +- }; +- }; +- +- power-supply@68 { +- compatible = "ibm,cffps1"; +- reg = <0x68>; +- }; +- +- power-supply@69 { +- compatible = "ibm,cffps1"; +- reg = <0x69>; +- }; +-}; +- +-&i2c4 { +- status = "okay"; +- +- /* CP0 VDD & VCS : IR35221 */ +- /* CP0 VDN & VIO : IR35221 */ +- /* CP0 VDDR : IR35221 */ +- +- ir35221@28 { +- compatible = "infineon,ir35221"; +- reg = <0x28>; +- }; +- +- ir35221@29 { +- compatible = "infineon,ir35221"; +- reg = <0x29>; +- }; +- +- ir35221@2d { +- compatible = "infineon,ir35221"; +- reg = <0x2d>; +- }; +- +-}; +- +-&i2c5 { +- status = "disabled"; +-}; +- +-&i2c6 { +- status = "disabled"; +-}; +- +-&i2c7 { +- status = "disabled"; +-}; +- +-&i2c8 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +-}; +- +-&i2c9 { +- status = "okay"; +- +- /* PCIe G3 x16 slot */ +-}; +- +-&i2c10 { +- status = "disabled"; +-}; +- +-&i2c11 { +- status = "okay"; +- +- /* CPLD */ +- /* TPM */ +- /* RTC RX8900CE */ +- /* TMP275A */ +- /* TMP275A */ +- +- rtc@32 { +- compatible = "epson,rx8900"; +- reg = <0x32>; +- }; +- +- tmp275@48 { +- compatible = "ti,tmp275"; +- reg = <0x48>; +- }; +- +- tmp275@49 { +- compatible = "ti,tmp275"; +- reg = <0x49>; +- }; +- +-}; +- +-&i2c12 { +- status = "disabled"; +-}; +- +-&i2c13 { +- status = "disabled"; +-}; +- +-&vuart { +- status = "okay"; +-}; +- +-&gfx { +- status = "okay"; +- memory-region = <&gfx_memory>; +-}; +- +-&adc { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc0_default +- &pinctrl_adc1_default +- &pinctrl_adc2_default +- &pinctrl_adc3_default +- &pinctrl_adc4_default +- &pinctrl_adc5_default +- &pinctrl_adc6_default +- &pinctrl_adc7_default +- &pinctrl_adc8_default +- &pinctrl_adc9_default +- &pinctrl_adc10_default +- &pinctrl_adc11_default +- &pinctrl_adc12_default +- &pinctrl_adc13_default +- &pinctrl_adc14_default +- &pinctrl_adc15_default>; +-}; +- +-&wdt1 { +- aspeed,reset-type = "none"; +- aspeed,external-signal; +- aspeed,ext-push-pull; +- aspeed,ext-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdtrst1_default>; +-}; +- +-&wdt2 { +- aspeed,alt-boot; +-}; +- +-&ibt { +- status = "okay"; +-}; +- +-&vhub { +- status = "okay"; +-}; +- +-&video { +- status = "okay"; +- memory-region = <&video_engine_memory>; +-}; +- +-#include "ibm-power9-dual.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-nicole.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-nicole.dts +deleted file mode 100644 +index 3d4bdad27c2d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-nicole.dts ++++ /dev/null +@@ -1,326 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright 2019 YADRO +-/dts-v1/; +-#include "aspeed-g5.dtsi" +-#include +- +-/ { +- model = "Nicole BMC"; +- compatible = "yadro,nicole-bmc", "aspeed,ast2500"; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- vga_memory: framebuffer@9f000000 { +- no-map; +- reg = <0x9f000000 0x01000000>; /* 16M */ +- }; +- +- flash_memory: region@98000000 { +- no-map; +- reg = <0x98000000 0x04000000>; /* 64M */ +- }; +- +- coldfire_memory: codefire_memory@9ef00000 { +- reg = <0x9ef00000 0x00100000>; +- no-map; +- }; +- +- gfx_memory: framebuffer { +- size = <0x01000000>; +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- +- video_engine_memory: jpegbuffer { +- size = <0x02000000>; /* 32M */ +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- power { +- label = "platform:green:power"; +- gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_HIGH>; +- }; +- +- identify { +- label = "platform:blue:indicator"; +- gpios = <&gpio ASPEED_GPIO(AA, 7) GPIO_ACTIVE_HIGH>; +- }; +- +- fault { +- label = "platform:red:fault"; +- gpios = <&gpio ASPEED_GPIO(AA, 3) GPIO_ACTIVE_HIGH>; +- }; +- +- attention { +- label = "platform:yellow:alarm"; +- gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- fsi: gpio-fsi { +- compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; +- #address-cells = <2>; +- #size-cells = <0>; +- no-gpio-delays; +- +- memory-region = <&coldfire_memory>; +- aspeed,sram = <&sram>; +- aspeed,cvic = <&cvic>; +- +- clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; +- data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>; +- mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; +- enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; +- trans-gpios = <&gpio ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- checkstop { +- label = "checkstop"; +- gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- iio-hwmon-battery { +- compatible = "iio-hwmon"; +- io-channels = <&adc 12>; +- }; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +- spi-max-frequency = <50000000>; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "pnor"; +- spi-max-frequency = <100000000>; +- }; +-}; +- +-&lpc_ctrl { +- status = "okay"; +- memory-region = <&flash_memory>; +- flash = <&spi1>; +-}; +- +-&uart1 { +- /* Rear RS-232 connector */ +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default +- &pinctrl_nrts1_default +- &pinctrl_ndtr1_default +- &pinctrl_ndsr1_default +- &pinctrl_ncts1_default +- &pinctrl_ndcd1_default +- &pinctrl_nri1_default>; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- +- use-ncsi; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- pagesize = <64>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- /* CPU0 characterization connector */ +-}; +- +-&i2c3 { +- status = "okay"; +- /* CLK GEN SI5338 */ +-}; +- +-&i2c4 { +- status = "okay"; +- /* Voltage regulators for CPU0 */ +-}; +- +-&i2c5 { +- status = "okay"; +- /* Voltage regulators for CPU1 */ +-}; +- +-&i2c6 { +- status = "okay"; +- +- rtc@32 { +- compatible = "epson,rx8900"; +- reg = <0x32>; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +- /* CPLD */ +-}; +- +-&gpio { +- gpio-line-names = +- /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","", +- /*B0-B7*/ "","","","","","","","", +- /*C0-C7*/ "","","","","","","","", +- /*D0-D7*/ "fsi-enable","bmc_power_up","sys_pwrok_buf", +- "func_mode0","func_mode1","func_mode2","","", +- /*E0-E7*/ "","ncsi_cfg","","","","","","", +- /*F0-F7*/ "","","","","","","","", +- /*G0-G7*/ "","","","","","","","", +- /*H0-H7*/ "","","","","","","","", +- /*I0-I7*/ "","","","","","","","", +- /*J0-J7*/ "","","checkstop","","","","","", +- /*K0-K7*/ "","","","","","","","", +- /*L0-L7*/ "","","","","","","","", +- /*M0-M7*/ "","","","","","","","", +- /*N0-N7*/ "","","","","","","","", +- /*O0-O7*/ "","","power-button","","","","","", +- /*P0-P7*/ "","fsi-trans","pm_rtc_adc_en","","","","","", +- /*Q0-Q7*/ "","","","","","","","id-button", +- /*R0-R7*/ "","software_pwrgood","","","","","","", +- /*S0-S7*/ "","","","","","","","seq_cont", +- /*T0-T7*/ "","","","","","","","", +- /*U0-U7*/ "","","","","","","","", +- /*V0-V7*/ "","","","","","","","", +- /*W0-W7*/ "","","","","","","","", +- /*X0-X7*/ "","","","","","","","", +- /*Y0-Y7*/ "","","","","","","","", +- /*Z0-Z7*/ "","","","","","","","", +- /*AA0-AA7*/ "fsi-clock","led-attention","fsi-data","led-fault", +- "led-power","","","led-identify", +- /*AB0-AB7*/ "","","","","","","","", +- /*AC0-AC7*/ "","","","","","","",""; +- +- func_mode0 { +- gpio-hog; +- gpios = ; +- output-low; +- }; +- func_mode1 { +- gpio-hog; +- gpios = ; +- output-low; +- }; +- func_mode2 { +- gpio-hog; +- gpios = ; +- output-low; +- }; +- seq_cont { +- gpio-hog; +- gpios = ; +- output-low; +- }; +- ncsi_cfg { +- gpio-hog; +- input; +- gpios = ; +- }; +-}; +- +-&vuart { +- status = "okay"; +-}; +- +-&gfx { +- status = "okay"; +- memory-region = <&gfx_memory>; +-}; +- +-&pinctrl { +- aspeed,external-nodes = <&gfx &lhc>; +-}; +- +-&ibt { +- status = "okay"; +-}; +- +-&vhub { +- status = "okay"; +-}; +- +-&adc { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc0_default +- &pinctrl_adc1_default +- &pinctrl_adc2_default +- &pinctrl_adc3_default +- &pinctrl_adc4_default +- &pinctrl_adc5_default +- &pinctrl_adc6_default +- &pinctrl_adc7_default +- &pinctrl_adc8_default +- &pinctrl_adc9_default +- &pinctrl_adc10_default +- &pinctrl_adc11_default +- &pinctrl_adc12_default +- &pinctrl_adc13_default +- &pinctrl_adc14_default +- &pinctrl_adc15_default>; +-}; +- +-&video { +- status = "okay"; +- memory-region = <&video_engine_memory>; +-}; +- +-#include "ibm-power9-dual.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-palmetto.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-palmetto.dts +deleted file mode 100644 +index cd660c1ff3f5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-palmetto.dts ++++ /dev/null +@@ -1,373 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/dts-v1/; +- +-#include "aspeed-g4.dtsi" +-#include +- +-/ { +- model = "Palmetto BMC"; +- compatible = "tyan,palmetto-bmc", "aspeed,ast2400"; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@40000000 { +- reg = <0x40000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- vga_memory: framebuffer@5f000000 { +- no-map; +- reg = <0x5f000000 0x01000000>; /* 16M */ +- }; +- +- coldfire_memory: codefire_memory@5ee00000 { +- reg = <0x5ee00000 0x00200000>; +- no-map; +- }; +- +- flash_memory: region@5c000000 { +- no-map; +- reg = <0x5C000000 0x02000000>; /* 32MB */ +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- heartbeat { +- gpios = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_LOW>; +- }; +- +- power { +- gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; +- }; +- +- identify { +- gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; +- }; +- }; +- +- fsi: gpio-fsi { +- compatible = "aspeed,ast2400-cf-fsi-master", "fsi-master"; +- #address-cells = <2>; +- #size-cells = <0>; +- +- memory-region = <&coldfire_memory>; +- aspeed,sram = <&sram>; +- aspeed,cvic = <&cvic>; +- +- clock-gpios = <&gpio ASPEED_GPIO(A, 4) GPIO_ACTIVE_HIGH>; +- data-gpios = <&gpio ASPEED_GPIO(A, 5) GPIO_ACTIVE_HIGH>; +- mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; +- enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; +- trans-gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- checkstop { +- label = "checkstop"; +- gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +- spi-max-frequency = <50000000>; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&spi { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1debug_default>; +- +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- spi-max-frequency = <50000000>; +- label = "pnor"; +- }; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default +- +- &pinctrl_vgahs_default &pinctrl_vgavs_default +- &pinctrl_ddcclk_default &pinctrl_ddcdat_default>; +-}; +- +-&uart1 { +- /* Rear RS-232 connector */ +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default +- &pinctrl_nrts1_default +- &pinctrl_ndtr1_default +- &pinctrl_ndsr1_default +- &pinctrl_ncts1_default +- &pinctrl_ndcd1_default +- &pinctrl_nri1_default>; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- +- use-ncsi; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +-}; +- +-&i2c0 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- pagesize = <64>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds3231"; +- reg = <0x68>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +- +- tmp423@4c { +- compatible = "ti,tmp423"; +- reg = <0x4c>; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +- +- occ-hwmon@50 { +- compatible = "ibm,p8-occ-hwmon"; +- reg = <0x50>; +- }; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- status = "okay"; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&vuart { +- status = "okay"; +-}; +- +-&ibt { +- status = "okay"; +-}; +- +-&lpc_ctrl { +- status = "okay"; +- memory-region = <&flash_memory>; +- flash = <&spi>; +-}; +- +-&gpio { +- pin_func_mode0 { +- gpio-hog; +- gpios = ; +- output-low; +- line-name = "func_mode0"; +- }; +- +- pin_func_mode1 { +- gpio-hog; +- gpios = ; +- output-low; +- line-name = "func_mode1"; +- }; +- +- pin_func_mode2 { +- gpio-hog; +- gpios = ; +- output-low; +- line-name = "func_mode2"; +- }; +- +- pin_gpio_a0 { +- gpio-hog; +- gpios = ; +- input; +- line-name = "BMC_FAN_RESERVED_N"; +- }; +- +- pin_gpio_a1 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "APSS_WDT_N"; +- }; +- +- pin_gpio_b1 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "APSS_BOOT_MODE"; +- }; +- +- pin_gpio_b2 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "APSS_RESET_N"; +- }; +- +- pin_gpio_b7 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "SPIVID_STBY_RESET_N"; +- }; +- +- pin_gpio_d1 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "BMC_POWER_UP"; +- }; +- +- pin_gpio_f1 { +- gpio-hog; +- gpios = ; +- input; +- line-name = "BMC_BATTERY_TEST"; +- }; +- +- pin_gpio_f4 { +- gpio-hog; +- gpios = ; +- input; +- line-name = "AST_HW_FAULT_N"; +- }; +- +- pin_gpio_f5 { +- gpio-hog; +- gpios = ; +- input; +- line-name = "AST_SYS_FAULT_N"; +- }; +- +- pin_gpio_f7 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "BMC_FULL_SPEED_N"; +- }; +- +- pin_gpio_g3 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "BMC_FAN_ERROR_N"; +- }; +- +- pin_gpio_g4 { +- gpio-hog; +- gpios = ; +- input; +- line-name = "BMC_WDT_RST1_P"; +- }; +- +- pin_gpio_g5 { +- gpio-hog; +- gpios = ; +- input; +- line-name = "BMC_WDT_RST2_P"; +- }; +- +- pin_gpio_h0 { +- gpio-hog; +- gpios = ; +- input; +- line-name = "PE_SLOT_TEST_EN_N"; +- }; +- +- pin_gpio_h1 { +- gpio-hog; +- gpios = ; +- input; +- line-name = "BMC_RTCRST_N"; +- }; +- +- pin_gpio_h2 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "SYS_PWROK_BMC"; +- }; +- +- pin_gpio_h7 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "BMC_TPM_INT_N"; +- }; +-}; +- +-&fsi { +- cfam@0,0 { +- reg = <0 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- chip-id = <0>; +- +- scom@1000 { +- compatible = "ibm,fsi2pib"; +- reg = <0x1000 0x400>; +- }; +- +- fsi_hub0: hub@3400 { +- compatible = "ibm,fsi-master-hub"; +- reg = <0x3400 0x400>; +- #address-cells = <2>; +- #size-cells = <0>; +- no-scan-on-init; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-romulus.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-romulus.dts +deleted file mode 100644 +index 084f54866f38..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-romulus.dts ++++ /dev/null +@@ -1,354 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/dts-v1/; +-#include "aspeed-g5.dtsi" +-#include +- +-/ { +- model = "Romulus BMC"; +- compatible = "ibm,romulus-bmc", "aspeed,ast2500"; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- vga_memory: framebuffer@9f000000 { +- no-map; +- reg = <0x9f000000 0x01000000>; /* 16M */ +- }; +- +- flash_memory: region@98000000 { +- no-map; +- reg = <0x98000000 0x04000000>; /* 64M */ +- }; +- +- coldfire_memory: codefire_memory@9ef00000 { +- reg = <0x9ef00000 0x00100000>; +- no-map; +- }; +- +- gfx_memory: framebuffer { +- size = <0x01000000>; +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- +- video_engine_memory: jpegbuffer { +- size = <0x02000000>; /* 32M */ +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- fault { +- gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>; +- }; +- +- identify { +- gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_HIGH>; +- }; +- +- power { +- gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; +- }; +- }; +- +- fsi: gpio-fsi { +- compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; +- #address-cells = <2>; +- #size-cells = <0>; +- no-gpio-delays; +- +- memory-region = <&coldfire_memory>; +- aspeed,sram = <&sram>; +- aspeed,cvic = <&cvic>; +- +- clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; +- data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>; +- mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; +- enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; +- trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- checkstop { +- label = "checkstop"; +- gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- id-button { +- label = "id-button"; +- gpios = <&gpio ASPEED_GPIO(Q, 7) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- iio-hwmon-battery { +- compatible = "iio-hwmon"; +- io-channels = <&adc 12>; +- }; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +- spi-max-frequency = <50000000>; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "pnor"; +- spi-max-frequency = <100000000>; +- }; +-}; +- +-&lpc_ctrl { +- status = "okay"; +- memory-region = <&flash_memory>; +- flash = <&spi1>; +-}; +- +-&uart1 { +- /* Rear RS-232 connector */ +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default +- &pinctrl_nrts1_default +- &pinctrl_ndtr1_default +- &pinctrl_ndsr1_default +- &pinctrl_ncts1_default +- &pinctrl_ndcd1_default +- &pinctrl_nri1_default>; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- +- use-ncsi; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- /* PCIe slot 1 (x8) */ +- status = "okay"; +-}; +- +-&i2c7 { +- /* PCIe slot 2 (x16) */ +- status = "okay"; +-}; +- +-&i2c8 { +- /* PCIe slot 3 (x16) */ +- status = "okay"; +-}; +- +-&i2c9 { +- /* PCIe slot 4 (x16) */ +- status = "okay"; +-}; +- +-&i2c10 { +- /* PCIe slot 5 (x8) */ +- status = "okay"; +-}; +- +-&i2c11 { +- status = "okay"; +- +- rtc@32 { +- compatible = "epson,rx8900"; +- reg = <0x32>; +- }; +-}; +- +-&i2c12 { +- status = "okay"; +- +- w83773g@4c { +- compatible = "nuvoton,w83773g"; +- reg = <0x4c>; +- }; +-}; +- +-&gpio { +- gpio-line-names = +- /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","", +- /*B0-B7*/ "","","","","","","","", +- /*C0-C7*/ "","","","","","","","", +- /*D0-D7*/ "fsi-enable","","","nic_func_mode0","nic_func_mode1","","","", +- /*E0-E7*/ "","","","","","","","", +- /*F0-F7*/ "","","","","","","","", +- /*G0-G7*/ "","","","","","","","", +- /*H0-H7*/ "","","","","","","","", +- /*I0-I7*/ "","","","power-button","","","","", +- /*J0-J7*/ "","","checkstop","","","","","", +- /*K0-K7*/ "","","","","","","","", +- /*L0-L7*/ "","","","","","","","", +- /*M0-M7*/ "","","","","","","","", +- /*N0-N7*/ "","","led-fault","", +- "led-identify","","","", +- /*O0-O7*/ "","","","","","","","", +- /*P0-P7*/ "","","","","","","","", +- /*Q0-Q7*/ "","","","","","","","id-button", +- /*R0-R7*/ "","","fsi-trans","","","led-power","","", +- /*S0-S7*/ "","","","","","","","seq_cont", +- /*T0-T7*/ "","","","","","","","", +- /*U0-U7*/ "","","","","","","","", +- /*V0-V7*/ "","","","","","","","", +- /*W0-W7*/ "","","","","","","","", +- /*X0-X7*/ "","","","","","","","", +- /*Y0-Y7*/ "","","","","","","","", +- /*Z0-Z7*/ "","","","","","","","", +- /*AA0-AA7*/ "fsi-clock","","fsi-data","","","","","", +- /*AB0-AB7*/ "","","","","","","","", +- /*AC0-AC7*/ "","","","","","","",""; +- +- nic_func_mode0 { +- gpio-hog; +- gpios = ; +- output-low; +- }; +- nic_func_mode1 { +- gpio-hog; +- gpios = ; +- output-low; +- }; +- seq_cont { +- gpio-hog; +- gpios = ; +- output-low; +- }; +-}; +- +-&vuart { +- status = "okay"; +-}; +- +-&gfx { +- status = "okay"; +- memory-region = <&gfx_memory>; +-}; +- +-&pinctrl { +- aspeed,external-nodes = <&gfx &lhc>; +-}; +- +-&pwm_tacho { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; +- +- fan@0 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x08>; +- }; +- +- fan@1 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x09>; +- }; +- +- fan@2 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0a>; +- }; +- +- fan@3 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0b>; +- }; +- +- fan@4 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0c>; +- }; +- +- fan@5 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0d>; +- }; +- +- fan@6 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x0e>; +- }; +-}; +- +-&ibt { +- status = "okay"; +-}; +- +-&vhub { +- status = "okay"; +-}; +- +-&adc { +- status = "okay"; +-}; +- +-&video { +- status = "okay"; +- memory-region = <&video_engine_memory>; +-}; +- +-#include "ibm-power9-dual.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-swift.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-swift.dts +deleted file mode 100644 +index 4816486c0c9e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-swift.dts ++++ /dev/null +@@ -1,978 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/dts-v1/; +-#include "aspeed-g5.dtsi" +-#include +-#include +- +-/ { +- model = "Swift BMC"; +- compatible = "ibm,swift-bmc", "aspeed,ast2500"; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- flash_memory: region@98000000 { +- no-map; +- reg = <0x98000000 0x04000000>; /* 64M */ +- }; +- +- gfx_memory: framebuffer { +- size = <0x01000000>; +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- air-water { +- label = "air-water"; +- gpios = <&gpio ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- checkstop { +- label = "checkstop"; +- gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- ps0-presence { +- label = "ps0-presence"; +- gpios = <&gpio ASPEED_GPIO(R, 7) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- ps1-presence { +- label = "ps1-presence"; +- gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- oppanel-presence { +- label = "oppanel-presence"; +- gpios = <&gpio ASPEED_GPIO(A, 7) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- opencapi-riser-presence { +- label = "opencapi-riser-presence"; +- gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- iio-hwmon-battery { +- compatible = "iio-hwmon"; +- io-channels = <&adc 12>; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- poll-interval = <1000>; +- +- scm0-presence { +- label = "scm0-presence"; +- gpios = <&pca9552 6 GPIO_ACTIVE_LOW>; +- linux,code = <6>; +- }; +- +- scm1-presence { +- label = "scm1-presence"; +- gpios = <&pca9552 7 GPIO_ACTIVE_LOW>; +- linux,code = <7>; +- }; +- +- cpu0vrm-presence { +- label = "cpu0vrm-presence"; +- gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; +- linux,code = <12>; +- }; +- +- cpu1vrm-presence { +- label = "cpu1vrm-presence"; +- gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; +- linux,code = <13>; +- }; +- +- fan0-presence { +- label = "fan0-presence"; +- gpios = <&pca0 5 GPIO_ACTIVE_LOW>; +- linux,code = <5>; +- }; +- +- fan1-presence { +- label = "fan1-presence"; +- gpios = <&pca0 6 GPIO_ACTIVE_LOW>; +- linux,code = <6>; +- }; +- +- fan2-presence { +- label = "fan2-presence"; +- gpios = <&pca0 7 GPIO_ACTIVE_LOW>; +- linux,code = <7>; +- }; +- +- fan3-presence { +- label = "fan3-presence"; +- gpios = <&pca0 8 GPIO_ACTIVE_LOW>; +- linux,code = <8>; +- }; +- +- fanboost-presence { +- label = "fanboost-presence"; +- gpios = <&pca0 9 GPIO_ACTIVE_LOW>; +- linux,code = <9>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- fan0 { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca0 0 GPIO_ACTIVE_LOW>; +- }; +- +- fan1 { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca0 1 GPIO_ACTIVE_LOW>; +- }; +- +- fan2 { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca0 2 GPIO_ACTIVE_LOW>; +- }; +- +- fan3 { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca0 3 GPIO_ACTIVE_LOW>; +- }; +- +- fanboost { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca0 4 GPIO_ACTIVE_LOW>; +- }; +- +- front-fault { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca1 2 GPIO_ACTIVE_LOW>; +- }; +- +- front-power { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca1 3 GPIO_ACTIVE_LOW>; +- }; +- +- front-id { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca1 0 GPIO_ACTIVE_LOW>; +- }; +- +- rear-fault { +- gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>; +- }; +- +- rear-id { +- gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_LOW>; +- }; +- }; +- +- fsi: gpio-fsi { +- compatible = "fsi-master-gpio", "fsi-master"; +- #address-cells = <2>; +- #size-cells = <0>; +- no-gpio-delays; +- +- clock-gpios = <&gpio ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>; +- data-gpios = <&gpio ASPEED_GPIO(P, 2) GPIO_ACTIVE_HIGH>; +- mux-gpios = <&gpio ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>; +- enable-gpios = <&gpio ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>; +- trans-gpios = <&gpio ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>; +- }; +- +- iio-hwmon-dps310 { +- compatible = "iio-hwmon"; +- io-channels = <&dps 0>; +- }; +- +-}; +- +-&fmc { +- status = "okay"; +- +- flash@0 { +- status = "okay"; +- label = "bmc"; +- m25p,fast-read; +- spi-max-frequency = <100000000>; +- partitions { +- #address-cells = < 1 >; +- #size-cells = < 1 >; +- compatible = "fixed-partitions"; +- u-boot@0 { +- reg = < 0 0x60000 >; +- label = "u-boot"; +- }; +- u-boot-env@60000 { +- reg = < 0x60000 0x20000 >; +- label = "u-boot-env"; +- }; +- obmc-ubi@80000 { +- reg = < 0x80000 0x7F80000>; +- label = "obmc-ubi"; +- }; +- }; +- }; +- +- flash@1 { +- status = "okay"; +- label = "alt-bmc"; +- m25p,fast-read; +- spi-max-frequency = <100000000>; +- partitions { +- #address-cells = < 1 >; +- #size-cells = < 1 >; +- compatible = "fixed-partitions"; +- u-boot@0 { +- reg = < 0 0x60000 >; +- label = "alt-u-boot"; +- }; +- u-boot-env@60000 { +- reg = < 0x60000 0x20000 >; +- label = "alt-u-boot-env"; +- }; +- obmc-ubi@80000 { +- reg = < 0x80000 0x7F80000>; +- label = "alt-obmc-ubi"; +- }; +- }; +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- +- flash@0 { +- status = "okay"; +- label = "pnor"; +- m25p,fast-read; +- spi-max-frequency = <100000000>; +- }; +-}; +- +-&uart1 { +- /* Rear RS-232 connector */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default +- &pinctrl_nrts1_default +- &pinctrl_ndtr1_default +- &pinctrl_ndsr1_default +- &pinctrl_ncts1_default +- &pinctrl_ndcd1_default +- &pinctrl_nri1_default>; +-}; +- +-&uart2 { +- /* APSS */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&lpc_ctrl { +- status = "okay"; +- memory-region = <&flash_memory>; +- flash = <&spi1>; +-}; +- +-&mac0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- use-ncsi; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +-}; +- +-&i2c2 { +- status = "okay"; +- +- /* MUX -> +- * Samtec 1 +- * Samtec 2 +- */ +-}; +- +-&i2c3 { +- status = "okay"; +- +- max31785@52 { +- compatible = "maxim,max31785a"; +- reg = <0x52>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fan@0 { +- compatible = "pmbus-fan"; +- reg = <0>; +- tach-pulses = <2>; +- maxim,fan-rotor-input = "tach"; +- maxim,fan-pwm-freq = <25000>; +- maxim,fan-no-watchdog; +- maxim,fan-no-fault-ramp; +- maxim,fan-ramp = <2>; +- maxim,fan-fault-pin-mon; +- }; +- +- fan@1 { +- compatible = "pmbus-fan"; +- reg = <1>; +- tach-pulses = <2>; +- maxim,fan-rotor-input = "tach"; +- maxim,fan-pwm-freq = <25000>; +- maxim,fan-no-watchdog; +- maxim,fan-no-fault-ramp; +- maxim,fan-ramp = <2>; +- maxim,fan-fault-pin-mon; +- }; +- +- fan@2 { +- compatible = "pmbus-fan"; +- reg = <2>; +- tach-pulses = <2>; +- maxim,fan-rotor-input = "tach"; +- maxim,fan-pwm-freq = <25000>; +- maxim,fan-no-watchdog; +- maxim,fan-no-fault-ramp; +- maxim,fan-ramp = <2>; +- maxim,fan-fault-pin-mon; +- }; +- +- fan@3 { +- compatible = "pmbus-fan"; +- reg = <3>; +- tach-pulses = <2>; +- maxim,fan-rotor-input = "tach"; +- maxim,fan-pwm-freq = <25000>; +- maxim,fan-no-watchdog; +- maxim,fan-no-fault-ramp; +- maxim,fan-ramp = <2>; +- maxim,fan-fault-pin-mon; +- }; +- +- fan@4 { +- compatible = "pmbus-fan"; +- reg = <4>; +- tach-pulses = <2>; +- maxim,fan-rotor-input = "tach"; +- maxim,fan-pwm-freq = <25000>; +- maxim,fan-no-watchdog; +- maxim,fan-no-fault-ramp; +- maxim,fan-ramp = <2>; +- maxim,fan-fault-pin-mon; +- }; +- }; +- +- pca0: pca9552@60 { +- compatible = "nxp,pca9552"; +- reg = <0x60>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- +- gpio@8 { +- reg = <8>; +- type = ; +- }; +- +- gpio@9 { +- reg = <9>; +- type = ; +- }; +- +- gpio@10 { +- reg = <10>; +- type = ; +- }; +- +- gpio@11 { +- reg = <11>; +- type = ; +- }; +- +- gpio@12 { +- reg = <12>; +- type = ; +- }; +- +- gpio@13 { +- reg = <13>; +- type = ; +- }; +- +- gpio@14 { +- reg = <14>; +- type = ; +- }; +- +- gpio@15 { +- reg = <15>; +- type = ; +- }; +- }; +- +- power-supply@68 { +- compatible = "ibm,cffps2"; +- reg = <0x68>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- +- power-supply@69 { +- compatible = "ibm,cffps2"; +- reg = <0x69>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c64"; +- reg = <0x51>; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +- +- dps: dps310@76 { +- compatible = "infineon,dps310"; +- reg = <0x76>; +- #io-channel-cells = <0>; +- }; +- +- tmp275@48 { +- compatible = "ti,tmp275"; +- reg = <0x48>; +- }; +- +- si7021a20@20 { +- compatible = "si,si7021a20"; +- reg = <0x20>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- +- pca1: pca9551@60 { +- compatible = "nxp,pca9551"; +- reg = <0x60>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- }; +-}; +- +-&i2c8 { +- status = "okay"; +- +- pca9552: pca9552@60 { +- compatible = "nxp,pca9552"; +- reg = <0x60>; +- #address-cells = <1>; +- #size-cells = <0>; +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N", +- "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF", +- "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF", +- "P9_SCM0_PRES", "P9_SCM1_PRES", +- "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF", +- "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF", +- "PRESENT_VRM_CP0_N", "PRESENT_VRM_CP1_N", +- "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N"; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- +- gpio@8 { +- reg = <8>; +- type = ; +- }; +- +- gpio@9 { +- reg = <9>; +- type = ; +- }; +- +- gpio@10 { +- reg = <10>; +- type = ; +- }; +- +- gpio@11 { +- reg = <11>; +- type = ; +- }; +- +- gpio@12 { +- reg = <12>; +- type = ; +- }; +- +- gpio@13 { +- reg = <13>; +- type = ; +- }; +- +- gpio@14 { +- reg = <14>; +- type = ; +- }; +- +- gpio@15 { +- reg = <15>; +- type = ; +- }; +- }; +- +- rtc@32 { +- compatible = "epson,rx8900"; +- reg = <0x32>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c64"; +- reg = <0x51>; +- }; +- +- ucd90160@64 { +- compatible = "ti,ucd90160"; +- reg = <0x64>; +- }; +-}; +- +-&i2c9 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- +- tmp423a@4c { +- compatible = "ti,tmp423"; +- reg = <0x4c>; +- }; +- +- ir35221@71 { +- compatible = "infineon,ir35221"; +- reg = <0x71>; +- }; +- +- ir35221@72 { +- compatible = "infineon,ir35221"; +- reg = <0x72>; +- }; +- +- pca2: pca9539@74 { +- compatible = "nxp,pca9539"; +- reg = <0x74>; +- #address-cells = <1>; +- #size-cells = <0>; +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- }; +- +- gpio@1 { +- reg = <1>; +- }; +- +- gpio@2 { +- reg = <2>; +- }; +- +- gpio@3 { +- reg = <3>; +- }; +- +- gpio@4 { +- reg = <4>; +- }; +- +- gpio@5 { +- reg = <5>; +- }; +- +- gpio@6 { +- reg = <6>; +- }; +- +- gpio@7 { +- reg = <7>; +- }; +- +- gpio@8 { +- reg = <8>; +- }; +- +- gpio@9 { +- reg = <9>; +- }; +- +- gpio@10 { +- reg = <10>; +- }; +- +- gpio@11 { +- reg = <11>; +- }; +- +- gpio@12 { +- reg = <12>; +- }; +- +- gpio@13 { +- reg = <13>; +- }; +- +- gpio@14 { +- reg = <14>; +- }; +- +- gpio@15 { +- reg = <15>; +- }; +- }; +-}; +- +-&i2c10 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- +- tmp423a@4c { +- compatible = "ti,tmp423"; +- reg = <0x4c>; +- }; +- +- ir35221@71 { +- compatible = "infineon,ir35221"; +- reg = <0x71>; +- }; +- +- ir35221@72 { +- compatible = "infineon,ir35221"; +- reg = <0x72>; +- }; +- +- pca3: pca9539@74 { +- compatible = "nxp,pca9539"; +- reg = <0x74>; +- #address-cells = <1>; +- #size-cells = <0>; +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- }; +- +- gpio@1 { +- reg = <1>; +- }; +- +- gpio@2 { +- reg = <2>; +- }; +- +- gpio@3 { +- reg = <3>; +- }; +- +- gpio@4 { +- reg = <4>; +- }; +- +- gpio@5 { +- reg = <5>; +- }; +- +- gpio@6 { +- reg = <6>; +- }; +- +- gpio@7 { +- reg = <7>; +- }; +- +- gpio@8 { +- reg = <8>; +- }; +- +- gpio@9 { +- reg = <9>; +- }; +- +- gpio@10 { +- reg = <10>; +- }; +- +- gpio@11 { +- reg = <11>; +- }; +- +- gpio@12 { +- reg = <12>; +- }; +- +- gpio@13 { +- reg = <13>; +- }; +- +- gpio@14 { +- reg = <14>; +- }; +- +- gpio@15 { +- reg = <15>; +- }; +- }; +-}; +- +-&i2c11 { +- /* MUX +- * -> PCIe Slot 0 +- * -> PCIe Slot 1 +- * -> PCIe Slot 2 +- * -> PCIe Slot 3 +- */ +- status = "okay"; +-}; +- +-&i2c12 { +- status = "okay"; +- +- tmp275@48 { +- compatible = "ti,tmp275"; +- reg = <0x48>; +- }; +- +- tmp275@4a { +- compatible = "ti,tmp275"; +- reg = <0x4a>; +- }; +-}; +- +-&i2c13 { +- status = "okay"; +-}; +- +-&vuart { +- status = "okay"; +-}; +- +-&gfx { +- status = "okay"; +- memory-region = <&gfx_memory>; +-}; +- +-&pinctrl { +- aspeed,external-nodes = <&gfx &lhc>; +-}; +- +-&wdt1 { +- aspeed,reset-type = "none"; +- aspeed,external-signal; +- aspeed,ext-push-pull; +- aspeed,ext-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdtrst1_default>; +-}; +- +-&wdt2 { +- aspeed,alt-boot; +-}; +- +-&ibt { +- status = "okay"; +-}; +- +-&adc { +- status = "okay"; +-}; +- +-&sdmmc { +- status = "okay"; +-}; +- +-&sdhci1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sd2_default>; +-}; +- +-#include "ibm-power9-dual.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-tacoma.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-tacoma.dts +deleted file mode 100644 +index e39f310d55eb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-tacoma.dts ++++ /dev/null +@@ -1,879 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-// Copyright 2019 IBM Corp. +-/dts-v1/; +- +-#include "aspeed-g6.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "Tacoma"; +- compatible = "ibm,tacoma-bmc", "aspeed,ast2600"; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200n8 earlycon"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- flash_memory: region@b8000000 { +- no-map; +- reg = <0xb8000000 0x4000000>; /* 64M */ +- }; +- +- ramoops@bc000000 { +- compatible = "ramoops"; +- reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */ +- record-size = <0x8000>; +- console-size = <0x8000>; +- pmsg-size = <0x8000>; +- max-reason = <3>; /* KMSG_DUMP_EMERG */ +- }; +- +- vga_memory: region@bf000000 { +- no-map; +- compatible = "shared-dma-pool"; +- reg = <0xbf000000 0x01000000>; /* 16M */ +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- ps0-presence { +- label = "ps0-presence"; +- gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- ps1-presence { +- label = "ps1-presence"; +- gpios = <&gpio0 ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- #address-cells = <1>; +- #size-cells = <0>; +- poll-interval = <1000>; +- +- fan0-presence { +- label = "fan0-presence"; +- gpios = <&pca0 4 GPIO_ACTIVE_LOW>; +- linux,code = <4>; +- }; +- +- fan1-presence { +- label = "fan1-presence"; +- gpios = <&pca0 5 GPIO_ACTIVE_LOW>; +- linux,code = <5>; +- }; +- +- fan2-presence { +- label = "fan2-presence"; +- gpios = <&pca0 6 GPIO_ACTIVE_LOW>; +- linux,code = <6>; +- }; +- +- fan3-presence { +- label = "fan3-presence"; +- gpios = <&pca0 7 GPIO_ACTIVE_LOW>; +- linux,code = <7>; +- }; +- }; +- +- iio-hwmon-dps310 { +- compatible = "iio-hwmon"; +- io-channels = <&dps 0>; +- }; +- +- iio-hwmon-bmp280 { +- compatible = "iio-hwmon"; +- io-channels = <&bmp 1>; +- }; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gpio0 { +- gpio-line-names = +- /*A0-A7*/ "","","","","","","","", +- /*B0-B7*/ "fsi-mux","","","","","","","", +- /*C0-C7*/ "","","","","","","","", +- /*D0-D7*/ "","","","","","","","", +- /*E0-E7*/ "power-button","","","checkstop","","presence-ps1","","led-rear-fault", +- /*F0-F7*/ "","","","","","","","", +- /*G0-G7*/ "","","","","","","","", +- /*H0-H7*/ "","","","presence-ps0","","","","", +- /*I0-I7*/ "","","","","","","","", +- /*J0-J7*/ "","","","","","","","", +- /*K0-K7*/ "","","","","","","","", +- /*L0-L7*/ "","","","","","","","", +- /*M0-M7*/ "","","","","","","","", +- /*N0-N7*/ "","","","","","","","", +- /*O0-O7*/ "led-rear-power","led-rear-id","","usb-power","","","","", +- /*P0-P7*/ "","","","","","bmc-tpm-reset","","", +- /*Q0-Q7*/ "cfam-reset","","","","","","","fsi-routing", +- /*R0-R7*/ "","","","","","","","", +- /*S0-S7*/ "","","","","","","","", +- /*T0-T7*/ "","","","","","","","", +- /*U0-U7*/ "","","","","","","","", +- /*V0-V7*/ "","","","","","","","", +- /*W0-W7*/ "","","","","","","","", +- /*X0-X7*/ "","","","","","","","", +- /*Y0-Y7*/ "","","","","","","","", +- /*Z0-Z7*/ "","","","","","","",""; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +- spi-max-frequency = <50000000>; +-#include "openbmc-flash-layout-128.dtsi" +- }; +- +- flash@1 { +- status = "okay"; +- m25p,fast-read; +- label = "alt-bmc"; +- spi-max-frequency = <50000000>; +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "pnor"; +- spi-max-frequency = <100000000>; +- }; +-}; +- +-&mac2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii3_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, +- <&syscon ASPEED_CLK_MAC3RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&emmc_controller { +- status = "okay"; +-}; +- +-&emmc { +- status = "okay"; +- clk-phase-mmc-hs200 = <36>, <270>; +-}; +- +-&fsim0 { +- status = "okay"; +- +- #address-cells = <2>; +- #size-cells = <0>; +- +- fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; +- fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>; +- cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_LOW>; +- +- cfam@0,0 { +- reg = <0 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- chip-id = <0>; +- +- scom@1000 { +- compatible = "ibm,fsi2pib"; +- reg = <0x1000 0x400>; +- }; +- +- i2c@1800 { +- compatible = "ibm,fsi-i2c-master"; +- reg = <0x1800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam0_i2c0: i2c-bus@0 { +- reg = <0>; +- }; +- +- cfam0_i2c1: i2c-bus@1 { +- reg = <1>; +- }; +- +- cfam0_i2c2: i2c-bus@2 { +- reg = <2>; +- }; +- +- cfam0_i2c3: i2c-bus@3 { +- reg = <3>; +- }; +- +- cfam0_i2c4: i2c-bus@4 { +- reg = <4>; +- }; +- +- cfam0_i2c5: i2c-bus@5 { +- reg = <5>; +- }; +- +- cfam0_i2c6: i2c-bus@6 { +- reg = <6>; +- }; +- +- cfam0_i2c7: i2c-bus@7 { +- reg = <7>; +- }; +- +- cfam0_i2c8: i2c-bus@8 { +- reg = <8>; +- }; +- +- cfam0_i2c9: i2c-bus@9 { +- reg = <9>; +- }; +- +- cfam0_i2c10: i2c-bus@a { +- reg = <10>; +- }; +- +- cfam0_i2c11: i2c-bus@b { +- reg = <11>; +- }; +- +- cfam0_i2c12: i2c-bus@c { +- reg = <12>; +- }; +- +- cfam0_i2c13: i2c-bus@d { +- reg = <13>; +- }; +- +- cfam0_i2c14: i2c-bus@e { +- reg = <14>; +- }; +- }; +- +- sbefifo@2400 { +- compatible = "ibm,p9-sbefifo"; +- reg = <0x2400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fsi_occ0: occ { +- compatible = "ibm,p9-occ"; +- }; +- }; +- +- fsi_hub0: hub@3400 { +- compatible = "fsi-master-hub"; +- reg = <0x3400 0x400>; +- #address-cells = <2>; +- #size-cells = <0>; +- +- no-scan-on-init; +- }; +- }; +-}; +- +-&fsi_hub0 { +- cfam@1,0 { +- reg = <1 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- chip-id = <1>; +- +- scom@1000 { +- compatible = "ibm,fsi2pib"; +- reg = <0x1000 0x400>; +- }; +- +- i2c@1800 { +- compatible = "ibm,fsi-i2c-master"; +- reg = <0x1800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam1_i2c0: i2c-bus@0 { +- reg = <0>; +- }; +- +- cfam1_i2c1: i2c-bus@1 { +- reg = <1>; +- }; +- +- cfam1_i2c2: i2c-bus@2 { +- reg = <2>; +- }; +- +- cfam1_i2c3: i2c-bus@3 { +- reg = <3>; +- }; +- +- cfam1_i2c4: i2c-bus@4 { +- reg = <4>; +- }; +- +- cfam1_i2c5: i2c-bus@5 { +- reg = <5>; +- }; +- +- cfam1_i2c6: i2c-bus@6 { +- reg = <6>; +- }; +- +- cfam1_i2c7: i2c-bus@7 { +- reg = <7>; +- }; +- +- cfam1_i2c8: i2c-bus@8 { +- reg = <8>; +- }; +- +- cfam1_i2c9: i2c-bus@9 { +- reg = <9>; +- }; +- +- cfam1_i2c10: i2c-bus@a { +- reg = <10>; +- }; +- +- cfam1_i2c11: i2c-bus@b { +- reg = <11>; +- }; +- +- cfam1_i2c12: i2c-bus@c { +- reg = <12>; +- }; +- +- cfam1_i2c13: i2c-bus@d { +- reg = <13>; +- }; +- +- cfam1_i2c14: i2c-bus@e { +- reg = <14>; +- }; +- }; +- +- sbefifo@2400 { +- compatible = "ibm,p9-sbefifo"; +- reg = <0x2400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fsi_occ1: occ { +- compatible = "ibm,p9-occ"; +- }; +- }; +- +- fsi_hub1: hub@3400 { +- compatible = "fsi-master-hub"; +- reg = <0x3400 0x400>; +- #address-cells = <2>; +- #size-cells = <0>; +- +- no-scan-on-init; +- }; +- }; +-}; +- +-/* Legacy OCC numbering (to get rid of when userspace is fixed) */ +-&fsi_occ0 { +- reg = <1>; +-}; +- +-&fsi_occ1 { +- reg = <2>; +-}; +- +-/ { +- aliases { +- i2c100 = &cfam0_i2c0; +- i2c101 = &cfam0_i2c1; +- i2c102 = &cfam0_i2c2; +- i2c103 = &cfam0_i2c3; +- i2c104 = &cfam0_i2c4; +- i2c105 = &cfam0_i2c5; +- i2c106 = &cfam0_i2c6; +- i2c107 = &cfam0_i2c7; +- i2c108 = &cfam0_i2c8; +- i2c109 = &cfam0_i2c9; +- i2c110 = &cfam0_i2c10; +- i2c111 = &cfam0_i2c11; +- i2c112 = &cfam0_i2c12; +- i2c113 = &cfam0_i2c13; +- i2c114 = &cfam0_i2c14; +- i2c200 = &cfam1_i2c0; +- i2c201 = &cfam1_i2c1; +- i2c202 = &cfam1_i2c2; +- i2c203 = &cfam1_i2c3; +- i2c204 = &cfam1_i2c4; +- i2c205 = &cfam1_i2c5; +- i2c206 = &cfam1_i2c6; +- i2c207 = &cfam1_i2c7; +- i2c208 = &cfam1_i2c8; +- i2c209 = &cfam1_i2c9; +- i2c210 = &cfam1_i2c10; +- i2c211 = &cfam1_i2c11; +- i2c212 = &cfam1_i2c12; +- i2c213 = &cfam1_i2c13; +- i2c214 = &cfam1_i2c14; +- }; +- +-}; +- +-&i2c0 { +- multi-master; +- status = "okay"; +- +- ibm-panel@62 { +- compatible = "ibm,op-panel"; +- reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- tpm: tpm@2e { +- compatible = "tcg,tpm-tis-i2c"; +- reg = <0x2e>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +- +- bmp: bmp280@77 { +- compatible = "bosch,bmp280"; +- reg = <0x77>; +- #io-channel-cells = <1>; +- }; +- +- max31785@52 { +- compatible = "maxim,max31785a"; +- reg = <0x52>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fan@0 { +- compatible = "pmbus-fan"; +- reg = <0>; +- tach-pulses = <2>; +- maxim,fan-rotor-input = "tach"; +- maxim,fan-pwm-freq = <25000>; +- maxim,fan-dual-tach; +- maxim,fan-no-watchdog; +- maxim,fan-no-fault-ramp; +- maxim,fan-ramp = <2>; +- maxim,fan-fault-pin-mon; +- }; +- +- fan@1 { +- compatible = "pmbus-fan"; +- reg = <1>; +- tach-pulses = <2>; +- maxim,fan-rotor-input = "tach"; +- maxim,fan-pwm-freq = <25000>; +- maxim,fan-dual-tach; +- maxim,fan-no-watchdog; +- maxim,fan-no-fault-ramp; +- maxim,fan-ramp = <2>; +- maxim,fan-fault-pin-mon; +- }; +- +- fan@2 { +- compatible = "pmbus-fan"; +- reg = <2>; +- tach-pulses = <2>; +- maxim,fan-rotor-input = "tach"; +- maxim,fan-pwm-freq = <25000>; +- maxim,fan-dual-tach; +- maxim,fan-no-watchdog; +- maxim,fan-no-fault-ramp; +- maxim,fan-ramp = <2>; +- maxim,fan-fault-pin-mon; +- }; +- +- fan@3 { +- compatible = "pmbus-fan"; +- reg = <3>; +- tach-pulses = <2>; +- maxim,fan-rotor-input = "tach"; +- maxim,fan-pwm-freq = <25000>; +- maxim,fan-dual-tach; +- maxim,fan-no-watchdog; +- maxim,fan-no-fault-ramp; +- maxim,fan-ramp = <2>; +- maxim,fan-fault-pin-mon; +- }; +- }; +- +- dps: dps310@76 { +- compatible = "infineon,dps310"; +- reg = <0x76>; +- #io-channel-cells = <0>; +- }; +- +- pca0: pca9552@60 { +- compatible = "nxp,pca9552"; +- reg = <0x60>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- +- gpio@8 { +- reg = <8>; +- type = ; +- }; +- +- gpio@9 { +- reg = <9>; +- type = ; +- }; +- +- gpio@10 { +- reg = <10>; +- type = ; +- }; +- +- gpio@11 { +- reg = <11>; +- type = ; +- }; +- +- gpio@12 { +- reg = <12>; +- type = ; +- }; +- +- gpio@13 { +- reg = <13>; +- type = ; +- }; +- +- gpio@14 { +- reg = <14>; +- type = ; +- }; +- +- gpio@15 { +- reg = <15>; +- type = ; +- }; +- }; +- +- power-supply@68 { +- compatible = "ibm,cffps1"; +- reg = <0x68>; +- }; +- +- power-supply@69 { +- compatible = "ibm,cffps1"; +- reg = <0x69>; +- }; +-}; +- +-&i2c4 { +- status = "okay"; +- +- tmp423a@4c { +- compatible = "ti,tmp423"; +- reg = <0x4c>; +- }; +- +- ir35221@70 { +- compatible = "infineon,ir35221"; +- reg = <0x70>; +- }; +- +- ir35221@71 { +- compatible = "infineon,ir35221"; +- reg = <0x71>; +- }; +-}; +- +-&i2c5 { +- status = "okay"; +- +- tmp423a@4c { +- compatible = "ti,tmp423"; +- reg = <0x4c>; +- }; +- +- ir35221@70 { +- compatible = "infineon,ir35221"; +- reg = <0x70>; +- }; +- +- ir35221@71 { +- compatible = "infineon,ir35221"; +- reg = <0x71>; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&i2c9 { +- status = "okay"; +- +- tmp275@4a { +- compatible = "ti,tmp275"; +- reg = <0x4a>; +- }; +-}; +- +-&i2c10 { +- status = "okay"; +-}; +- +-&i2c11 { +- status = "okay"; +- +- pca9552: pca9552@60 { +- compatible = "nxp,pca9552"; +- reg = <0x60>; +- #address-cells = <1>; +- #size-cells = <0>; +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N", +- "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF", +- "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF", +- "GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF", +- "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF", +- "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF", +- "GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF", +- "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N"; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- +- gpio@8 { +- reg = <8>; +- type = ; +- }; +- +- gpio@9 { +- reg = <9>; +- type = ; +- }; +- +- gpio@10 { +- reg = <10>; +- type = ; +- }; +- +- gpio@11 { +- reg = <11>; +- type = ; +- }; +- +- gpio@12 { +- reg = <12>; +- type = ; +- }; +- +- gpio@13 { +- reg = <13>; +- type = ; +- }; +- +- gpio@14 { +- reg = <14>; +- type = ; +- }; +- +- gpio@15 { +- reg = <15>; +- type = ; +- }; +- }; +- +- rtc@32 { +- compatible = "epson,rx8900"; +- reg = <0x32>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c64"; +- reg = <0x51>; +- }; +- +- ucd90160@64 { +- compatible = "ti,ucd90160"; +- reg = <0x64>; +- }; +-}; +- +-&i2c12 { +- status = "okay"; +-}; +- +-&i2c13 { +- status = "okay"; +-}; +- +-&ibt { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +- // Workaround for A0 +- compatible = "snps,dw-apb-uart"; +-}; +- +-&uart5 { +- // Workaround for A0 +- compatible = "snps,dw-apb-uart"; +-}; +- +-&vuart1 { +- status = "okay"; +-}; +- +-&vuart2 { +- status = "okay"; +-}; +- +-&lpc_ctrl { +- status = "okay"; +- memory-region = <&flash_memory>; +- flash = <&spi1>; +-}; +- +-&wdt1 { +- aspeed,reset-type = "none"; +- aspeed,external-signal; +- aspeed,ext-push-pull; +- aspeed,ext-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdtrst1_default>; +-}; +- +-&wdt2 { +- status = "okay"; +-}; +- +-&pinctrl { +- /* Hog these as no driver is probed for the entire LPC block */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lpc_default>, +- <&pinctrl_lsirq_default>; +-}; +- +-&xdma { +- status = "okay"; +- memory-region = <&vga_memory>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-vesnin.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-vesnin.dts +deleted file mode 100644 +index 328ef472c479..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-vesnin.dts ++++ /dev/null +@@ -1,248 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright 2019 YADRO +-/dts-v1/; +- +-#include "aspeed-g4.dtsi" +-#include +- +-/ { +- model = "Vesnin BMC"; +- compatible = "yadro,vesnin-bmc", "aspeed,ast2400"; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@40000000 { +- reg = <0x40000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- vga_memory: framebuffer@5f000000 { +- no-map; +- reg = <0x5f000000 0x01000000>; /* 16MB */ +- }; +- flash_memory: region@5c000000 { +- no-map; +- reg = <0x5c000000 0x02000000>; /* 32M */ +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- heartbeat { +- gpios = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_LOW>; +- }; +- power_red { +- gpios = <&gpio ASPEED_GPIO(N, 1) GPIO_ACTIVE_LOW>; +- }; +- +- power_green { +- gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; +- }; +- +- id_blue { +- gpios = <&gpio ASPEED_GPIO(O, 0) GPIO_ACTIVE_LOW>; +- }; +- +- alarm_red { +- gpios = <&gpio ASPEED_GPIO(N, 6) GPIO_ACTIVE_LOW>; +- }; +- +- alarm_yel { +- gpios = <&gpio ASPEED_GPIO(N, 7) GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- button_checkstop { +- label = "checkstop"; +- linux,code = <74>; +- gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>; +- }; +- +- button_identify { +- label = "identify"; +- linux,code = <152>; +- gpios = <&gpio ASPEED_GPIO(O, 7) GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +-#include "openbmc-flash-layout.dtsi" +- }; +- +- flash@1 { +- status = "okay"; +- m25p,fast-read; +- label = "alt"; +- }; +-}; +- +-&spi { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1debug_default>; +- +- flash@0 { +- status = "okay"; +- label = "pnor"; +- m25p,fast-read; +- }; +-}; +- +-&mac0 { +- status = "okay"; +- use-ncsi; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +-}; +- +- +-&uart5 { +- status = "okay"; +-}; +- +-&lpc_ctrl { +- status = "okay"; +- memory-region = <&flash_memory>; +- flash = <&spi>; +-}; +- +-&ibt { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; +-}; +- +-&i2c0 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- pagesize = <64>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- tmp75@49 { +- compatible = "ti,tmp75"; +- reg = <0x49>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +- +- occ-hwmon@50 { +- compatible = "ibm,p8-occ-hwmon"; +- reg = <0x50>; +- }; +-}; +- +-&i2c5 { +- status = "okay"; +- +- occ-hwmon@51 { +- compatible = "ibm,p8-occ-hwmon"; +- reg = <0x51>; +- }; +-}; +- +-&i2c6 { +- status = "okay"; +- +- w83795g@2f { +- compatible = "nuvoton,w83795g"; +- reg = <0x2f>; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +- +- occ-hwmon@56 { +- compatible = "ibm,p8-occ-hwmon"; +- reg = <0x56>; +- }; +-}; +- +-&i2c9 { +- status = "okay"; +-}; +- +-&i2c10 { +- status = "okay"; +-}; +- +-&i2c11 { +- status = "okay"; +- +- occ-hwmon@57 { +- compatible = "ibm,p8-occ-hwmon"; +- reg = <0x57>; +- }; +-}; +- +-&i2c12 { +- status = "okay"; +- +- rtc@68 { +- compatible = "maxim,ds3231"; +- reg = <0x68>; +- }; +-}; +- +-&i2c13 { +- status = "okay"; +-}; +- +-&vuart { +- status = "okay"; +-}; +- +-&wdt2 { +- aspeed,alt-boot; +-}; +- +-&sdmmc { +- status = "okay"; +-}; +- +-&sdhci1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sd2_default>; +- cd-inverted; +- disable-wp; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-witherspoon.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-witherspoon.dts +deleted file mode 100644 +index 230f3584bcab..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-witherspoon.dts ++++ /dev/null +@@ -1,704 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/dts-v1/; +-#include "aspeed-g5.dtsi" +-#include +-#include +- +-/ { +- model = "Witherspoon BMC"; +- compatible = "ibm,witherspoon-bmc", "aspeed,ast2500"; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- flash_memory: region@98000000 { +- no-map; +- reg = <0x98000000 0x04000000>; /* 64M */ +- }; +- +- vga_memory: region@9f000000 { +- no-map; +- compatible = "shared-dma-pool"; +- reg = <0x9f000000 0x01000000>; /* 16M */ +- }; +- +- gfx_memory: framebuffer { +- size = <0x01000000>; +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- +- video_engine_memory: jpegbuffer { +- size = <0x02000000>; /* 32MM */ +- alignment = <0x01000000>; +- compatible = "shared-dma-pool"; +- reusable; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- air-water { +- label = "air-water"; +- gpios = <&gpio ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- checkstop { +- label = "checkstop"; +- gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- ps0-presence { +- label = "ps0-presence"; +- gpios = <&gpio ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- ps1-presence { +- label = "ps1-presence"; +- gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- iio-hwmon-battery { +- compatible = "iio-hwmon"; +- io-channels = <&adc 12>; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- poll-interval = <1000>; +- +- fan0-presence { +- label = "fan0-presence"; +- gpios = <&pca0 4 GPIO_ACTIVE_LOW>; +- linux,code = <4>; +- }; +- +- fan1-presence { +- label = "fan1-presence"; +- gpios = <&pca0 5 GPIO_ACTIVE_LOW>; +- linux,code = <5>; +- }; +- +- fan2-presence { +- label = "fan2-presence"; +- gpios = <&pca0 6 GPIO_ACTIVE_LOW>; +- linux,code = <6>; +- }; +- +- fan3-presence { +- label = "fan3-presence"; +- gpios = <&pca0 7 GPIO_ACTIVE_LOW>; +- linux,code = <7>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- fan0 { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca0 0 GPIO_ACTIVE_LOW>; +- }; +- +- fan1 { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca0 1 GPIO_ACTIVE_LOW>; +- }; +- +- fan2 { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca0 2 GPIO_ACTIVE_LOW>; +- }; +- +- fan3 { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca0 3 GPIO_ACTIVE_LOW>; +- }; +- +- front-fault { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca0 13 GPIO_ACTIVE_LOW>; +- }; +- +- front-power { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca0 14 GPIO_ACTIVE_LOW>; +- }; +- +- front-id { +- retain-state-shutdown; +- default-state = "keep"; +- gpios = <&pca0 15 GPIO_ACTIVE_LOW>; +- }; +- +- rear-fault { +- gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>; +- }; +- +- rear-id { +- gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_LOW>; +- }; +- +- rear-power { +- gpios = <&gpio ASPEED_GPIO(N, 3) GPIO_ACTIVE_LOW>; +- }; +- +- power-button { +- gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; +- }; +- }; +- +- fsi: gpio-fsi { +- compatible = "fsi-master-gpio", "fsi-master"; +- #address-cells = <2>; +- #size-cells = <0>; +- no-gpio-delays; +- +- clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; +- data-gpios = <&gpio ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>; +- mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; +- enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; +- trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; +- }; +- +- iio-hwmon-dps310 { +- compatible = "iio-hwmon"; +- io-channels = <&dps 0>; +- }; +- +- iio-hwmon-bmp280 { +- compatible = "iio-hwmon"; +- io-channels = <&bmp 1>; +- }; +- +-}; +- +-&gpio { +- gpio-line-names = +- /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","", +- /*B0-B7*/ "","","","","","air-water","","", +- /*C0-C7*/ "","","","","","","","", +- /*D0-D7*/ "fsi-enable","","","","","","","", +- /*E0-E7*/ "fsi-data","","","","","","","", +- /*F0-F7*/ "","","","","","","","", +- /*G0-G7*/ "","","","","","","","", +- /*H0-H7*/ "","","","","","","","", +- /*I0-I7*/ "","","","","","","","", +- /*J0-J7*/ "","","checkstop","","","","","", +- /*K0-K7*/ "","","","","","","","", +- /*L0-L7*/ "","","","","","","","", +- /*M0-M7*/ "","","","","","","","", +- /*N0-N7*/ "presence-ps1","","led-rear-fault","led-rear-power", +- "led-rear-id","","","", +- /*O0-O7*/ "","","","","","","","", +- /*P0-P7*/ "","","","","","","","presence-ps0", +- /*Q0-Q7*/ "","","","","","","","", +- /*R0-R7*/ "","","fsi-trans","","","power-button","","", +- /*S0-S7*/ "","","","","","","","", +- /*T0-T7*/ "","","","","","","","", +- /*U0-U7*/ "","","","","","","","", +- /*V0-V7*/ "","","","","","","","", +- /*W0-W7*/ "","","","","","","","", +- /*X0-X7*/ "","","","","","","","", +- /*Y0-Y7*/ "","","","","","","","", +- /*Z0-Z7*/ "","","","","","","","", +- /*AA0-AA7*/ "fsi-clock","","","","","","","", +- /*AB0-AB7*/ "","","","","","","","", +- /*AC0-AC7*/ "","","","","","","",""; +-}; +- +-&fmc { +- status = "okay"; +- +- flash@0 { +- status = "okay"; +- label = "bmc"; +- m25p,fast-read; +- spi-max-frequency = <50000000>; +- +- partitions { +- #address-cells = < 1 >; +- #size-cells = < 1 >; +- compatible = "fixed-partitions"; +- u-boot@0 { +- reg = < 0 0x60000 >; +- label = "u-boot"; +- }; +- u-boot-env@60000 { +- reg = < 0x60000 0x20000 >; +- label = "u-boot-env"; +- }; +- obmc-ubi@80000 { +- reg = < 0x80000 0x1F80000 >; +- label = "obmc-ubi"; +- }; +- }; +- }; +- +- flash@1 { +- status = "okay"; +- label = "alt-bmc"; +- m25p,fast-read; +- spi-max-frequency = <50000000>; +- +- partitions { +- #address-cells = < 1 >; +- #size-cells = < 1 >; +- compatible = "fixed-partitions"; +- u-boot@0 { +- reg = < 0 0x60000 >; +- label = "alt-u-boot"; +- }; +- u-boot-env@60000 { +- reg = < 0x60000 0x20000 >; +- label = "alt-u-boot-env"; +- }; +- obmc-ubi@80000 { +- reg = < 0x80000 0x1F80000 >; +- label = "alt-obmc-ubi"; +- }; +- }; +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- +- flash@0 { +- status = "okay"; +- label = "pnor"; +- m25p,fast-read; +- spi-max-frequency = <100000000>; +- }; +-}; +- +-&uart1 { +- /* Rear RS-232 connector */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default +- &pinctrl_nrts1_default +- &pinctrl_ndtr1_default +- &pinctrl_ndsr1_default +- &pinctrl_ncts1_default +- &pinctrl_ndcd1_default +- &pinctrl_nri1_default>; +-}; +- +-&uart2 { +- /* APSS */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&lpc_ctrl { +- status = "okay"; +- memory-region = <&flash_memory>; +- flash = <&spi1>; +-}; +- +-&mac0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&i2c2 { +- status = "okay"; +- +- /* MUX -> +- * Samtec 1 +- * Samtec 2 +- */ +-}; +- +-&i2c3 { +- status = "okay"; +- +- bmp: bmp280@77 { +- compatible = "bosch,bmp280"; +- reg = <0x77>; +- #io-channel-cells = <1>; +- }; +- +- max31785@52 { +- compatible = "maxim,max31785a"; +- reg = <0x52>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- dps: dps310@76 { +- compatible = "infineon,dps310"; +- reg = <0x76>; +- #io-channel-cells = <0>; +- }; +- +- pca0: pca9552@60 { +- compatible = "nxp,pca9552"; +- reg = <0x60>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- +- gpio@8 { +- reg = <8>; +- type = ; +- }; +- +- gpio@9 { +- reg = <9>; +- type = ; +- }; +- +- gpio@10 { +- reg = <10>; +- type = ; +- }; +- +- gpio@11 { +- reg = <11>; +- type = ; +- }; +- +- gpio@12 { +- reg = <12>; +- type = ; +- }; +- +- gpio@13 { +- reg = <13>; +- type = ; +- }; +- +- gpio@14 { +- reg = <14>; +- type = ; +- }; +- +- gpio@15 { +- reg = <15>; +- type = ; +- }; +- }; +- +- power-supply@68 { +- compatible = "ibm,cffps1"; +- reg = <0x68>; +- }; +- +- power-supply@69 { +- compatible = "ibm,cffps1"; +- reg = <0x69>; +- }; +-}; +- +-&i2c4 { +- status = "okay"; +- +- tmp423a@4c { +- compatible = "ti,tmp423"; +- reg = <0x4c>; +- }; +- +- ir35221@70 { +- compatible = "infineon,ir35221"; +- reg = <0x70>; +- }; +- +- ir35221@71 { +- compatible = "infineon,ir35221"; +- reg = <0x71>; +- }; +-}; +- +- +-&i2c5 { +- status = "okay"; +- +- tmp423a@4c { +- compatible = "ti,tmp423"; +- reg = <0x4c>; +- }; +- +- ir35221@70 { +- compatible = "infineon,ir35221"; +- reg = <0x70>; +- }; +- +- ir35221@71 { +- compatible = "infineon,ir35221"; +- reg = <0x71>; +- }; +-}; +- +-&i2c9 { +- status = "okay"; +- +- tmp275@4a { +- compatible = "ti,tmp275"; +- reg = <0x4a>; +- }; +-}; +- +-&i2c10 { +- /* MUX +- * -> PCIe Slot 3 +- * -> PCIe Slot 4 +- */ +- status = "okay"; +-}; +- +-&i2c11 { +- status = "okay"; +- +- pca9552: pca9552@60 { +- compatible = "nxp,pca9552"; +- reg = <0x60>; +- #address-cells = <1>; +- #size-cells = <0>; +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N", +- "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF", +- "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF", +- "GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF", +- "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF", +- "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF", +- "GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF", +- "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N"; +- +- gpio@0 { +- reg = <0>; +- type = ; +- }; +- +- gpio@1 { +- reg = <1>; +- type = ; +- }; +- +- gpio@2 { +- reg = <2>; +- type = ; +- }; +- +- gpio@3 { +- reg = <3>; +- type = ; +- }; +- +- gpio@4 { +- reg = <4>; +- type = ; +- }; +- +- gpio@5 { +- reg = <5>; +- type = ; +- }; +- +- gpio@6 { +- reg = <6>; +- type = ; +- }; +- +- gpio@7 { +- reg = <7>; +- type = ; +- }; +- +- gpio@8 { +- reg = <8>; +- type = ; +- }; +- +- gpio@9 { +- reg = <9>; +- type = ; +- }; +- +- gpio@10 { +- reg = <10>; +- type = ; +- }; +- +- gpio@11 { +- reg = <11>; +- type = ; +- }; +- +- gpio@12 { +- reg = <12>; +- type = ; +- }; +- +- gpio@13 { +- reg = <13>; +- type = ; +- }; +- +- gpio@14 { +- reg = <14>; +- type = ; +- }; +- +- gpio@15 { +- reg = <15>; +- type = ; +- }; +- }; +- +- rtc@32 { +- compatible = "epson,rx8900"; +- reg = <0x32>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c64"; +- reg = <0x51>; +- }; +- +- ucd90160@64 { +- compatible = "ti,ucd90160"; +- reg = <0x64>; +- }; +-}; +- +-&i2c12 { +- status = "okay"; +-}; +- +-&i2c13 { +- status = "okay"; +-}; +- +-&vuart { +- status = "okay"; +-}; +- +-&gfx { +- status = "okay"; +- memory-region = <&gfx_memory>; +-}; +- +-&pinctrl { +- aspeed,external-nodes = <&gfx &lhc>; +-}; +- +-&wdt1 { +- aspeed,reset-type = "none"; +- aspeed,external-signal; +- aspeed,ext-push-pull; +- aspeed,ext-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdtrst1_default>; +-}; +- +-&wdt2 { +- aspeed,alt-boot; +-}; +- +-&ibt { +- status = "okay"; +-}; +- +-&adc { +- status = "okay"; +-}; +- +-&vhub { +- status = "okay"; +-}; +- +-&video { +- status = "okay"; +- memory-region = <&video_engine_memory>; +-}; +- +-&xdma { +- status = "okay"; +- memory-region = <&vga_memory>; +-}; +- +-#include "ibm-power9-dual.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-zaius.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-zaius.dts +deleted file mode 100644 +index 7ae4ea0d2931..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-opp-zaius.dts ++++ /dev/null +@@ -1,578 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "aspeed-g5.dtsi" +-#include +- +-/ { +- model = "Zaius BMC"; +- compatible = "ingrasys,zaius-bmc", "aspeed,ast2500"; +- +- aliases { +- i2c15 = &i2cpcie0; +- i2c16 = &i2cpcie1; +- i2c17 = &i2cpcie2; +- i2c19 = &i2cpcie3; +- i2c20 = &i2cpcie4; +- }; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x40000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- flash_memory: region@98000000 { +- no-map; +- reg = <0x98000000 0x04000000>; /* 64M */ +- }; +- }; +- +- onewire0 { +- compatible = "w1-gpio"; +- gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>; +- }; +- +- onewire1 { +- compatible = "w1-gpio"; +- gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>; +- }; +- +- onewire2 { +- compatible = "w1-gpio"; +- gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>; +- }; +- +- onewire3 { +- compatible = "w1-gpio"; +- gpios = <&gpio ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- checkstop { +- label = "checkstop"; +- gpios = <&gpio ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- pcie-e2b-present{ +- label = "pcie-e2b-present"; +- gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- sys_boot_status { +- label = "System boot status"; +- gpios = <&gpio ASPEED_GPIO(D, 5) GPIO_ACTIVE_LOW>; +- }; +- +- attention { +- label = "Attention"; +- gpios = <&gpio ASPEED_GPIO(D, 6) GPIO_ACTIVE_LOW>; +- }; +- +- plt_fault { +- label = "Platform fault"; +- gpios = <&gpio ASPEED_GPIO(D, 7) GPIO_ACTIVE_LOW>; +- }; +- +- hdd_fault { +- label = "Onboard drive fault"; +- gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>; +- }; +- }; +- +- fsi: gpio-fsi { +- compatible = "fsi-master-gpio", "fsi-master"; +- #address-cells = <2>; +- #size-cells = <0>; +- no-gpio-delays; +- +- trans-gpios = <&gpio ASPEED_GPIO(O, 6) GPIO_ACTIVE_HIGH>; +- enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; +- clock-gpios = <&gpio ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>; +- data-gpios = <&gpio ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>; +- mux-gpios = <&gpio ASPEED_GPIO(P, 6) GPIO_ACTIVE_HIGH>; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, +- <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, +- <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, +- <&adc 13>, <&adc 14>, <&adc 15>; +- }; +- +- iio-hwmon-battery { +- compatible = "iio-hwmon"; +- io-channels = <&adc 12>; +- }; +- +-}; +- +-&fmc { +- status = "okay"; +- +- flash@0 { +- status = "okay"; +- label = "bmc"; +- m25p,fast-read; +- spi-max-frequency = <50000000>; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- +- flash@0 { +- status = "okay"; +- label = "pnor"; +- m25p,fast-read; +- spi-max-frequency = <100000000>; +- }; +-}; +- +-&spi2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi2ck_default +- &pinctrl_spi2cs0_default +- &pinctrl_spi2cs1_default +- &pinctrl_spi2miso_default +- &pinctrl_spi2mosi_default>; +- +- flash@0 { +- status = "okay"; +- }; +-}; +- +-&uart1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default>; +-}; +- +-&lpc_ctrl { +- status = "okay"; +- memory-region = <&flash_memory>; +- flash = <&spi1>; +-}; +- +-&lpc_snoop { +- status = "okay"; +- snoop-ports = <0x80>; +-}; +- +- +-&uart5 { +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&mac1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +-}; +- +-&i2c0 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- pagesize = <32>; +- }; +- +- rtc@68 { +- compatible = "nxp,pcf8523"; +- reg = <0x68>; +- }; +- +- ucd90160@64 { +- compatible = "ti,ucd90160"; +- reg = <0x64>; +- }; +- +- /* Power sequencer UCD90160 PMBUS @64h +- * FRU AT24C64D @50h +- * RTC PCF8523 @68h +- * Clock buffer 9DBL04 @6dh +- */ +-}; +- +-&i2c1 { +- status = "okay"; +- +- i2c-switch@71 { +- compatible = "nxp,pca9546"; +- reg = <0x71>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2cpcie0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- i2cpcie1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- i2cpcie2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- i2ctpm: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +- +- /* MUX1 PCA9546A @71h +- * PCIe 0 +- * PCIe 1 +- * PCIe 2 +- * TPM header +- */ +-}; +- +-&i2c2 { +- status = "disabled"; +- +- /* OCP Mezz Connector A (OOB SMBUS) */ +-}; +- +-&i2c3 { +- status = "disabled"; +- +- /* OCP Mezz Connector A (PCIe slot SMBUS) */ +-}; +- +-&i2c4 { +- status = "okay"; +- +- i2c-switch@71 { +- compatible = "nxp,pca9546"; +- reg = <0x71>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2cpcie3: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- i2cpcie4: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- }; +- +- /* MUX1 PCA9546A @71h +- * PCIe 3 +- * PCIe 4 +- */ +-}; +- +- +-&i2c5 { +- status = "disabled"; +- +- /* CPU0 PRM 0.7V */ +- /* CPU0 PRM 1.2V CH03 */ +- /* CPU0 PRM 0.8V */ +- /* CPU0 PRM 1.2V CH47 */ +-}; +- +-&i2c6 { +- status = "disabled"; +- +- /* CPU1 PRM 0.7V */ +- /* CPU1 PRM 1.2V CH03 */ +- /* CPU1 PRM 0.8V */ +- /* CPU1 PRM 1.2V CH47 */ +-}; +- +-&i2c7 { +- status = "okay"; +- +- pca9541a@70 { +- compatible = "nxp,pca9541"; +- reg = <0x70>; +- +- i2c-arb { +- #address-cells = <1>; +- #size-cells = <0>; +- +- hotswap@54 { +- compatible = "ti,lm5066i"; +- reg = <0x54>; +- }; +- }; +- +- }; +- +- vrm@64 { +- compatible = "isil,isl68137"; +- reg = <0x64>; +- }; +- +- vrm@40 { +- compatible = "isil,isl68137"; +- reg = <0x40>; +- }; +- +- vrm@60 { +- compatible = "isil,isl68137"; +- reg = <0x60>; +- }; +- +- vrm@43 { +- compatible = "infineon,ir38064"; +- reg = <0x43>; +- }; +- +- vrm@41 { +- compatible = "isil,isl68137"; +- reg = <0x41>; +- }; +- +- /* Master selector PCA9541A @70h (other master: CPU0) +- * LM5066I PMBUS @10h +- */ +- +- /* +- * Brick will be one of these types/addresses. Depending +- * on the board SKU only one is actually present and will successfully +- * instantiate while the others will fail the probe operation. +- * These are the PVT (and presumably beyond) addresses: +- * 12V Quarter Brick DC/DC Converter Q54SJ12050 @6Ah +- * 12V Quarter Brick DC/DC Converter Q54SH12050 @30h +- */ +- power-brick@6a { +- compatible = "delta,dps800"; +- reg = <0x6a>; +- }; +- power-brick@30 { +- compatible = "delta,dps800"; +- reg = <0x30>; +- }; +- +- /* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */ +- /* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */ +- /* CPU0 VR ISL68137 0.8V PMBUS @60h */ +- /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @43h */ +- /* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */ +- /* Master selector PCA9541A @70h (other master: CPU0) +- * LM5066I PMBUS @10h +- */ +-}; +- +-&i2c8 { +- status = "okay"; +- +- vrm@64 { +- compatible = "isil,isl68137"; +- reg = <0x64>; +- }; +- +- vrm@40 { +- compatible = "isil,isl68137"; +- reg = <0x40>; +- }; +- +- vrm@41 { +- compatible = "isil,isl68137"; +- reg = <0x41>; +- }; +- +- vrm@42 { +- compatible = "infineon,ir38064"; +- reg = <0x42>; +- }; +- +- vrm@60 { +- compatible = "isil,isl68137"; +- reg = <0x60>; +- }; +- +- /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @64h */ +- /* CPU1 VR ISL68137 1.2V CH03 PMBUS @40h */ +- /* CPU1 VR ISL68137 1.2V CH47 PMBUS @41h */ +- /* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */ +- /* CPU1 VR ISL68137 0.8V PMBUS @60h */ +-}; +- +- +-&i2c9 { +- status = "disabled"; +- +- /* Fan board */ +-}; +- +-&i2c10 { +- status = "disabled"; +-}; +- +-&i2c11 { +- status = "disabled"; +- +- /* GPU sideband */ +-}; +- +-&i2c12 { +- status = "disabled"; +-}; +- +-&i2c13 { +- status = "disabled"; +- +- /* MUX PI3USB102 +- * CPU0 debug +- * CPU1 debug +- */ +-}; +- +-&pinctrl { +- aspeed,external-nodes = <&gfx &lhc>; +- +- pinctrl_gpioh_unbiased: gpioi_unbiased { +- pins = "A8", "C7", "B7", "A7", "D7", "B6", "A6", "E7"; +- bias-disable; +- }; +-}; +- +-&gpio { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpioh_unbiased>; +- +- gpio-line-names = +- /*A0-A7*/ "","cfam-reset","","","","","","", +- /*B0-B7*/ "","","","","","","","", +- /*C0-C7*/ "","","","","","","","", +- /*D0-D7*/ "fsi-enable","","","","","led-sys-boot-status","led-attention", +- "led-fault", +- /*E0-E7*/ "","","","","","","","presence-pcie-e2b", +- /*F0-F7*/ "","","","","","","","checkstop", +- /*G0-G7*/ "fsi-clock","fsi-data","","","","","","", +- /*H0-H7*/ "onewire0","onewire1","onewire2","onewire3","","","","", +- /*I0-I7*/ "","","","power-button","","","","", +- /*J0-J7*/ "","","","","","","","", +- /*K0-K7*/ "","","","","","","","", +- /*L0-L7*/ "","","","","","","","", +- /*M0-M7*/ "","","","","","","","", +- /*N0-N7*/ "","","","","","","","", +- /*O0-O7*/ "","","","","iso_u164_en","","fsi-trans","", +- /*P0-P7*/ "ncsi_mux_en_n","bmc_i2c2_sw_rst_n","","bmc_i2c5_sw_rst_n","", +- "","fsi-mux","", +- /*Q0-Q7*/ "","","","","","","","", +- /*R0-R7*/ "","","","","","","","", +- /*S0-S7*/ "","","","","","","","", +- /*T0-T7*/ "","","","","","","","", +- /*U0-U7*/ "","","","","","","","", +- /*V0-V7*/ "","","","","","","","", +- /*W0-W7*/ "","","","","","","","", +- /*X0-X7*/ "","","","","","","","", +- /*Y0-Y7*/ "","","","","","","","", +- /*Z0-Z7*/ "","","","","","","","", +- /*AA0-AA7*/ "","","led-hdd-fault","","","","","", +- /*AB0-AB7*/ "","","","","","","","", +- /*AC0-AC7*/ "","","","","","","",""; +- +- line_iso_u146_en { +- gpio-hog; +- gpios = ; +- output-high; +- }; +- +- ncsi_mux_en_n { +- gpio-hog; +- gpios = ; +- output-low; +- }; +- +- line_bmc_i2c2_sw_rst_n { +- gpio-hog; +- gpios = ; +- output-high; +- }; +- +- line_bmc_i2c5_sw_rst_n { +- gpio-hog; +- gpios = ; +- output-high; +- }; +-}; +- +-&vuart { +- status = "okay"; +-}; +- +-&gfx { +- status = "okay"; +-}; +- +-&pwm_tacho { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default +- &pinctrl_pwm2_default &pinctrl_pwm3_default>; +- +- fan@0 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x00>; +- }; +- +- fan@1 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x01>; +- }; +- +- fan@2 { +- reg = <0x02>; +- aspeed,fan-tach-ch = /bits/ 8 <0x02>; +- }; +- +- fan@3 { +- reg = <0x03>; +- aspeed,fan-tach-ch = /bits/ 8 <0x03>; +- }; +-}; +- +-&ibt { +- status = "okay"; +-}; +- +-#include "ibm-power9-dual.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-portwell-neptune.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-portwell-neptune.dts +deleted file mode 100644 +index 61bc74b423cf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-portwell-neptune.dts ++++ /dev/null +@@ -1,167 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2017 Facebook Inc. +-/dts-v1/; +- +-#include "aspeed-g5.dtsi" +-#include +- +-/ { +- model = "Portwell Neptune BMC"; +- compatible = "portwell,neptune-bmc", "aspeed,ast2500"; +- aliases { +- serial0 = &uart1; +- serial4 = &uart5; +- }; +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x20000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- postcode0 { +- label="BMC_UP"; +- gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- postcode1 { +- label="BMC_HB"; +- gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- postcode2 { +- label="FAULT"; +- gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>; +- }; +- // postcode3-7 are GPIOH3-H7 +- }; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "pnor"; +- }; +-}; +- +-&uart1 { +- // Host Console +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default>; +-}; +- +-&uart5 { +- // BMC Console +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default +- &pinctrl_mdio1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +-}; +- +-&mac1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii2_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>, +- <&syscon ASPEED_CLK_MAC2RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&i2c1 { +- status = "okay"; +- // To PCIe slot SMBUS +-}; +- +-&i2c2 { +- status = "okay"; +- // To LAN I210 +-}; +- +-&i2c3 { +- status = "okay"; +- // SMBus to COMe AB +-}; +- +-&i2c4 { +- status = "okay"; +- // I2C to COMe AB +-}; +- +-&i2c5 { +- status = "okay"; +-// USB Debug card +- pca9555@27 { +- compatible = "nxp,pca9555"; +- reg = <0x27>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&i2c6 { +- status = "okay"; +- tpm@20 { +- compatible = "infineon,slb9645tt"; +- reg = <0x20>; +- }; +- tmp421@4e { +- compatible = "ti,tmp421"; +- reg = <0x4e>; +- }; +- tmp421@4f { +- compatible = "ti,tmp421"; +- reg = <0x4f>; +- }; +-}; +- +-&i2c8 { +- status = "okay"; +- eeprom@51 { +- compatible = "atmel,24c128"; +- reg = <0x51>; +- pagesize = <32>; +- }; +-}; +- +-&pwm_tacho { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; +- fan@0 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x00>; +- }; +- +- fan@1 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x01>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-quanta-q71l.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-quanta-q71l.dts +deleted file mode 100644 +index 9605e53f5bbf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-quanta-q71l.dts ++++ /dev/null +@@ -1,518 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "aspeed-g4.dtsi" +-#include +- +-/ { +- model = "Quanta Q71L BMC"; +- compatible = "quanta,q71l-bmc", "aspeed,ast2400"; +- +- aliases { +- i2c14 = &i2c_pcie2; +- i2c15 = &i2c_pcie3; +- i2c16 = &i2c_pcie6; +- i2c17 = &i2c_pcie7; +- i2c18 = &i2c_pcie1; +- i2c19 = &i2c_pcie4; +- i2c20 = &i2c_pcie5; +- i2c21 = &i2c_pcie8; +- i2c22 = &i2c_pcie9; +- i2c23 = &i2c_pcie10; +- i2c24 = &i2c_ssd1; +- i2c25 = &i2c_ssd2; +- i2c26 = &i2c_psu4; +- i2c27 = &i2c_psu1; +- i2c28 = &i2c_psu3; +- i2c29 = &i2c_psu2; +- }; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "console=ttyS4,115200 earlycon"; +- }; +- +- memory@40000000 { +- reg = <0x40000000 0x8000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- vga_memory: framebuffer@47800000 { +- no-map; +- reg = <0x47800000 0x00800000>; /* 8MB */ +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- heartbeat { +- gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>; +- }; +- +- power { +- gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>; +- }; +- +- identify { +- gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>; +- }; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, +- <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, +- <&adc 8>, <&adc 9>, <&adc 10>; +- }; +- +- iio-hwmon-battery { +- compatible = "iio-hwmon"; +- io-channels = <&adc 11>; +- }; +- +- i2c1mux: i2cmux { +- compatible = "i2c-mux-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* mux-gpios = <&sgpio 10 GPIO_ACTIVE_HIGH> */ +- i2c-parent = <&i2c1>; +- }; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- label = "bmc"; +- m25p,fast-read; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&spi { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "pnor"; +- }; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default +- &pinctrl_ddcclk_default &pinctrl_ddcdat_default>; +-}; +- +-&p2a { +- status = "okay"; +- memory-region = <&vga_memory>; +-}; +- +-&ibt { +- status = "okay"; +-}; +- +-&lpc_ctrl { +- status = "okay"; +-}; +- +-&lpc_snoop { +- status = "okay"; +- snoop-ports = <0x80>; +-}; +- +-&mac0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- use-ncsi; +-}; +- +-&mac1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- +- /* temp2 inlet */ +- tmp75@4c { +- compatible = "ti,tmp75"; +- reg = <0x4c>; +- }; +- +- /* temp3 */ +- tmp75@4e { +- compatible = "ti,tmp75"; +- reg = <0x4e>; +- }; +- +- /* temp1 */ +- tmp75@4f { +- compatible = "ti,tmp75"; +- reg = <0x4f>; +- }; +- +- /* Baseboard FRU */ +- eeprom@54 { +- compatible = "atmel,24c64"; +- reg = <0x54>; +- }; +- +- /* FP FRU */ +- eeprom@57 { +- compatible = "atmel,24c64"; +- reg = <0x57>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- +- /* 0: PCIe Slot 2, +- * Slot 3, +- * Slot 6, +- * Slot 7 +- */ +- i2c-switch@74 { +- compatible = "nxp,pca9546"; +- reg = <0x74>; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-mux-idle-disconnect; /* may use mux@77 next. */ +- +- i2c_pcie2: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c_pcie3: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- i2c_pcie6: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c_pcie7: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +- +- /* 0: PCIe Slot 1, +- * Slot 4, +- * Slot 5, +- * Slot 8, +- * Slot 9, +- * Slot 10, +- * SSD 1, +- * SSD 2 +- */ +- i2c-switch@77 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x77>; +- i2c-mux-idle-disconnect; /* may use mux@74 next. */ +- +- i2c_pcie1: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c_pcie4: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- i2c_pcie5: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c_pcie8: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- i2c_pcie9: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- i2c_pcie10: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- i2c_ssd1: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- i2c_ssd2: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +- +- /* BIOS FRU */ +- eeprom@56 { +- compatible = "atmel,24c64"; +- reg = <0x56>; +- }; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- status = "okay"; +-}; +- +-&i2c7 { +- status = "okay"; +- +- /* 0: PSU4 +- * PSU1 +- * PSU3 +- * PSU2 +- */ +- i2c-switch@70 { +- compatible = "nxp,pca9546"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c_psu4: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- psu@59 { +- compatible = "pmbus"; +- reg = <0x59>; +- }; +- }; +- +- i2c_psu1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- psu@58 { +- compatible = "pmbus"; +- reg = <0x58>; +- }; +- }; +- +- i2c_psu3: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- psu@58 { +- compatible = "pmbus"; +- reg = <0x58>; +- }; +- }; +- +- i2c_psu2: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- psu@59 { +- compatible = "pmbus"; +- reg = <0x59>; +- }; +- }; +- }; +- +- /* PDB FRU */ +- eeprom@52 { +- compatible = "atmel,24c64"; +- reg = <0x52>; +- }; +-}; +- +-&i2c8 { +- status = "okay"; +- +- /* BMC FRU */ +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +-}; +- +-&vuart { +- status = "okay"; +-}; +- +-&wdt2 { +- status = "okay"; +-}; +- +-&adc { +- status = "okay"; +-}; +- +-&pwm_tacho { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default +- &pinctrl_pwm1_default +- &pinctrl_pwm2_default +- &pinctrl_pwm3_default>; +- +- fan@0 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x00>; +- }; +- +- fan@1 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x01>; +- }; +- +- fan@2 { +- reg = <0x02>; +- aspeed,fan-tach-ch = /bits/ 8 <0x02>; +- }; +- +- fan@3 { +- reg = <0x03>; +- aspeed,fan-tach-ch = /bits/ 8 <0x03>; +- }; +- +- fan@4 { +- reg = <0x00>; +- aspeed,fan-tach-ch = /bits/ 8 <0x04>; +- }; +- +- fan@5 { +- reg = <0x01>; +- aspeed,fan-tach-ch = /bits/ 8 <0x05>; +- }; +- +- fan@6 { +- reg = <0x02>; +- aspeed,fan-tach-ch = /bits/ 8 <0x06>; +- }; +- +- fan@7 { +- reg = <0x03>; +- aspeed,fan-tach-ch = /bits/ 8 <0x07>; +- }; +-}; +- +-&i2c1mux { +- i2c@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Memory Riser 1 FRU */ +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- }; +- +- /* Memory Riser 2 FRU */ +- eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- }; +- +- /* Memory Riser 3 FRU */ +- eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- }; +- +- /* Memory Riser 4 FRU */ +- eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- }; +- }; +- +- i2c@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Memory Riser 5 FRU */ +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- }; +- +- /* Memory Riser 6 FRU */ +- eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- }; +- +- /* Memory Riser 7 FRU */ +- eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- }; +- +- /* Memory Riser 8 FRU */ +- eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-bmc-supermicro-x11spi.dts b/scripts/dtc/include-prefixes/arm/aspeed-bmc-supermicro-x11spi.dts +deleted file mode 100644 +index 50f3c6a5c0c8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-bmc-supermicro-x11spi.dts ++++ /dev/null +@@ -1,137 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2020 Super Micro Computer, Inc +- +-/dts-v1/; +- +-#include "aspeed-g5.dtsi" +- +-/ { +- model = "X11SPI BMC"; +- compatible = "supermicro,x11spi-bmc", "aspeed,ast2500"; +- +- chosen { +- stdout-path = &uart5; +- bootargs = "earlycon"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- vga_memory: framebuffer@7f000000 { +- no-map; +- reg = <0x7f000000 0x01000000>; +- }; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, +- <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, +- <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, +- <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; +- }; +- +-}; +- +-&gpio { +- status = "okay"; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "bmc"; +-#include "openbmc-flash-layout.dtsi" +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "pnor"; +- }; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&mac0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rmii1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, +- <&syscon ASPEED_CLK_MAC1RCLK>; +- clock-names = "MACCLK", "RCLK"; +- use-ncsi; +-}; +- +-&mac1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- status = "okay"; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&i2c13 { +- status = "okay"; +-}; +- +-&gfx { +- status = "okay"; +-}; +- +-&pinctrl { +- aspeed,external-nodes = <&gfx &lhc>; +-}; +- +-&pwm_tacho { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default +- &pinctrl_pwm2_default &pinctrl_pwm3_default +- &pinctrl_pwm4_default &pinctrl_pwm5_default +- &pinctrl_pwm6_default &pinctrl_pwm7_default>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-g4.dtsi b/scripts/dtc/include-prefixes/arm/aspeed-g4.dtsi +deleted file mode 100644 +index c5aeb3cf3a09..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-g4.dtsi ++++ /dev/null +@@ -1,1427 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-#include +- +-/ { +- model = "Aspeed BMC"; +- compatible = "aspeed,ast2400"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&vic>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c7; +- i2c8 = &i2c8; +- i2c9 = &i2c9; +- i2c10 = &i2c10; +- i2c11 = &i2c11; +- i2c12 = &i2c12; +- i2c13 = &i2c13; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- serial4 = &uart5; +- serial5 = &vuart; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,arm926ej-s"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0>; +- }; +- +- ahb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- fmc: spi@1e620000 { +- reg = < 0x1e620000 0x94 +- 0x20000000 0x10000000 >; +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "aspeed,ast2400-fmc"; +- clocks = <&syscon ASPEED_CLK_AHB>; +- status = "disabled"; +- interrupts = <19>; +- flash@0 { +- reg = < 0 >; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- status = "disabled"; +- }; +- flash@1 { +- reg = < 1 >; +- compatible = "jedec,spi-nor"; +- status = "disabled"; +- }; +- flash@2 { +- reg = < 2 >; +- compatible = "jedec,spi-nor"; +- status = "disabled"; +- }; +- flash@3 { +- reg = < 3 >; +- compatible = "jedec,spi-nor"; +- status = "disabled"; +- }; +- flash@4 { +- reg = < 4 >; +- compatible = "jedec,spi-nor"; +- status = "disabled"; +- }; +- }; +- +- spi: spi@1e630000 { +- reg = < 0x1e630000 0x18 +- 0x30000000 0x10000000 >; +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "aspeed,ast2400-spi"; +- clocks = <&syscon ASPEED_CLK_AHB>; +- status = "disabled"; +- flash@0 { +- reg = < 0 >; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- status = "disabled"; +- }; +- }; +- +- vic: interrupt-controller@1e6c0080 { +- compatible = "aspeed,ast2400-vic"; +- interrupt-controller; +- #interrupt-cells = <1>; +- valid-sources = <0xffffffff 0x0007ffff>; +- reg = <0x1e6c0080 0x80>; +- }; +- +- cvic: copro-interrupt-controller@1e6c2000 { +- compatible = "aspeed,ast2400-cvic", "aspeed-cvic"; +- valid-sources = <0x7fffffff>; +- reg = <0x1e6c2000 0x80>; +- }; +- +- mac0: ethernet@1e660000 { +- compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; +- reg = <0x1e660000 0x180>; +- interrupts = <2>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; +- status = "disabled"; +- }; +- +- mac1: ethernet@1e680000 { +- compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; +- reg = <0x1e680000 0x180>; +- interrupts = <3>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; +- status = "disabled"; +- }; +- +- ehci0: usb@1e6a1000 { +- compatible = "aspeed,ast2400-ehci", "generic-ehci"; +- reg = <0x1e6a1000 0x100>; +- interrupts = <5>; +- clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb2h_default>; +- status = "disabled"; +- }; +- +- uhci: usb@1e6b0000 { +- compatible = "aspeed,ast2400-uhci", "generic-uhci"; +- reg = <0x1e6b0000 0x100>; +- interrupts = <14>; +- #ports = <3>; +- clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; +- status = "disabled"; +- /* +- * No default pinmux, it will follow EHCI, use an explicit pinmux +- * override if you don't enable EHCI +- */ +- }; +- +- vhub: usb-vhub@1e6a0000 { +- compatible = "aspeed,ast2400-usb-vhub"; +- reg = <0x1e6a0000 0x300>; +- interrupts = <5>; +- clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; +- aspeed,vhub-downstream-ports = <5>; +- aspeed,vhub-generic-endpoints = <15>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb2d_default>; +- status = "disabled"; +- }; +- +- apb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- syscon: syscon@1e6e2000 { +- compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; +- reg = <0x1e6e2000 0x1a8>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1e6e2000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- +- p2a: p2a-control@2c { +- reg = <0x2c 0x4>; +- compatible = "aspeed,ast2400-p2a-ctrl"; +- status = "disabled"; +- }; +- +- silicon-id@7c { +- compatible = "aspeed,ast2400-silicon-id", "aspeed,silicon-id"; +- reg = <0x7c 0x4>; +- }; +- +- pinctrl: pinctrl@80 { +- reg = <0x80 0x18>, <0xa0 0x10>; +- compatible = "aspeed,ast2400-pinctrl"; +- }; +- }; +- +- rng: hwrng@1e6e2078 { +- compatible = "timeriomem_rng"; +- reg = <0x1e6e2078 0x4>; +- period = <1>; +- quality = <100>; +- }; +- +- adc: adc@1e6e9000 { +- compatible = "aspeed,ast2400-adc"; +- reg = <0x1e6e9000 0xb0>; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_ADC>; +- #io-channel-cells = <1>; +- status = "disabled"; +- }; +- +- sram: sram@1e720000 { +- compatible = "mmio-sram"; +- reg = <0x1e720000 0x8000>; // 32K +- }; +- +- video: video@1e700000 { +- compatible = "aspeed,ast2400-video-engine"; +- reg = <0x1e700000 0x1000>; +- clocks = <&syscon ASPEED_CLK_GATE_VCLK>, +- <&syscon ASPEED_CLK_GATE_ECLK>; +- clock-names = "vclk", "eclk"; +- interrupts = <7>; +- status = "disabled"; +- }; +- +- sdmmc: sd-controller@1e740000 { +- compatible = "aspeed,ast2400-sd-controller"; +- reg = <0x1e740000 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1e740000 0x10000>; +- clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; +- status = "disabled"; +- +- sdhci0: sdhci@100 { +- compatible = "aspeed,ast2400-sdhci"; +- reg = <0x100 0x100>; +- interrupts = <26>; +- sdhci,auto-cmd12; +- clocks = <&syscon ASPEED_CLK_SDIO>; +- status = "disabled"; +- }; +- +- sdhci1: sdhci@200 { +- compatible = "aspeed,ast2400-sdhci"; +- reg = <0x200 0x100>; +- interrupts = <26>; +- sdhci,auto-cmd12; +- clocks = <&syscon ASPEED_CLK_SDIO>; +- status = "disabled"; +- }; +- }; +- +- gpio: gpio@1e780000 { +- #gpio-cells = <2>; +- gpio-controller; +- compatible = "aspeed,ast2400-gpio"; +- reg = <0x1e780000 0x1000>; +- interrupts = <20>; +- gpio-ranges = <&pinctrl 0 0 220>; +- clocks = <&syscon ASPEED_CLK_APB>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- timer: timer@1e782000 { +- /* This timer is a Faraday FTTMR010 derivative */ +- compatible = "aspeed,ast2400-timer"; +- reg = <0x1e782000 0x90>; +- interrupts = <16 17 18 35 36 37 38 39>; +- clocks = <&syscon ASPEED_CLK_APB>; +- clock-names = "PCLK"; +- }; +- +- rtc: rtc@1e781000 { +- compatible = "aspeed,ast2400-rtc"; +- reg = <0x1e781000 0x18>; +- status = "disabled"; +- }; +- +- uart1: serial@1e783000 { +- compatible = "ns16550a"; +- reg = <0x1e783000 0x20>; +- reg-shift = <2>; +- interrupts = <9>; +- clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; +- resets = <&lpc_reset 4>; +- no-loopback-test; +- status = "disabled"; +- }; +- +- uart5: serial@1e784000 { +- compatible = "ns16550a"; +- reg = <0x1e784000 0x20>; +- reg-shift = <2>; +- interrupts = <10>; +- clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; +- no-loopback-test; +- status = "disabled"; +- }; +- +- wdt1: watchdog@1e785000 { +- compatible = "aspeed,ast2400-wdt"; +- reg = <0x1e785000 0x1c>; +- clocks = <&syscon ASPEED_CLK_APB>; +- }; +- +- wdt2: watchdog@1e785020 { +- compatible = "aspeed,ast2400-wdt"; +- reg = <0x1e785020 0x1c>; +- clocks = <&syscon ASPEED_CLK_APB>; +- }; +- +- pwm_tacho: pwm-tacho-controller@1e786000 { +- compatible = "aspeed,ast2400-pwm-tacho"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x1e786000 0x1000>; +- clocks = <&syscon ASPEED_CLK_24M>; +- resets = <&syscon ASPEED_RESET_PWM>; +- status = "disabled"; +- }; +- +- vuart: serial@1e787000 { +- compatible = "aspeed,ast2400-vuart"; +- reg = <0x1e787000 0x40>; +- reg-shift = <2>; +- interrupts = <8>; +- clocks = <&syscon ASPEED_CLK_APB>; +- no-loopback-test; +- status = "disabled"; +- }; +- +- lpc: lpc@1e789000 { +- compatible = "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"; +- reg = <0x1e789000 0x1000>; +- reg-io-width = <4>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1e789000 0x1000>; +- +- lpc_ctrl: lpc-ctrl@80 { +- compatible = "aspeed,ast2400-lpc-ctrl"; +- reg = <0x80 0x10>; +- clocks = <&syscon ASPEED_CLK_GATE_LCLK>; +- status = "disabled"; +- }; +- +- lpc_snoop: lpc-snoop@90 { +- compatible = "aspeed,ast2400-lpc-snoop"; +- reg = <0x90 0x8>; +- interrupts = <8>; +- clocks = <&syscon ASPEED_CLK_GATE_LCLK>; +- status = "disabled"; +- }; +- +- lhc: lhc@a0 { +- compatible = "aspeed,ast2400-lhc"; +- reg = <0xa0 0x24 0xc8 0x8>; +- }; +- +- lpc_reset: reset-controller@98 { +- compatible = "aspeed,ast2400-lpc-reset"; +- reg = <0x98 0x4>; +- #reset-cells = <1>; +- }; +- +- ibt: ibt@140 { +- compatible = "aspeed,ast2400-ibt-bmc"; +- reg = <0x140 0x18>; +- interrupts = <8>; +- status = "disabled"; +- }; +- }; +- +- uart2: serial@1e78d000 { +- compatible = "ns16550a"; +- reg = <0x1e78d000 0x20>; +- reg-shift = <2>; +- interrupts = <32>; +- clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; +- resets = <&lpc_reset 5>; +- no-loopback-test; +- status = "disabled"; +- }; +- +- uart3: serial@1e78e000 { +- compatible = "ns16550a"; +- reg = <0x1e78e000 0x20>; +- reg-shift = <2>; +- interrupts = <33>; +- clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; +- resets = <&lpc_reset 6>; +- no-loopback-test; +- status = "disabled"; +- }; +- +- uart4: serial@1e78f000 { +- compatible = "ns16550a"; +- reg = <0x1e78f000 0x20>; +- reg-shift = <2>; +- interrupts = <34>; +- clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; +- resets = <&lpc_reset 7>; +- no-loopback-test; +- status = "disabled"; +- }; +- +- i2c: bus@1e78a000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1e78a000 0x1000>; +- }; +- }; +- }; +-}; +- +-&i2c { +- i2c_ic: interrupt-controller@0 { +- #interrupt-cells = <1>; +- compatible = "aspeed,ast2400-i2c-ic"; +- reg = <0x0 0x40>; +- interrupts = <12>; +- interrupt-controller; +- }; +- +- i2c0: i2c-bus@40 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x40 0x40>; +- compatible = "aspeed,ast2400-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <0>; +- interrupt-parent = <&i2c_ic>; +- status = "disabled"; +- /* Does not need pinctrl properties */ +- }; +- +- i2c1: i2c-bus@80 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x80 0x40>; +- compatible = "aspeed,ast2400-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <1>; +- interrupt-parent = <&i2c_ic>; +- status = "disabled"; +- /* Does not need pinctrl properties */ +- }; +- +- i2c2: i2c-bus@c0 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0xc0 0x40>; +- compatible = "aspeed,ast2400-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <2>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3_default>; +- status = "disabled"; +- }; +- +- i2c3: i2c-bus@100 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x100 0x40>; +- compatible = "aspeed,ast2400-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <3>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4_default>; +- status = "disabled"; +- }; +- +- i2c4: i2c-bus@140 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x140 0x40>; +- compatible = "aspeed,ast2400-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <4>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c5_default>; +- status = "disabled"; +- }; +- +- i2c5: i2c-bus@180 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x180 0x40>; +- compatible = "aspeed,ast2400-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <5>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c6_default>; +- status = "disabled"; +- }; +- +- i2c6: i2c-bus@1c0 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x1c0 0x40>; +- compatible = "aspeed,ast2400-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <6>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c7_default>; +- status = "disabled"; +- }; +- +- i2c7: i2c-bus@300 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x300 0x40>; +- compatible = "aspeed,ast2400-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <7>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c8_default>; +- status = "disabled"; +- }; +- +- i2c8: i2c-bus@340 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x340 0x40>; +- compatible = "aspeed,ast2400-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <8>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c9_default>; +- status = "disabled"; +- }; +- +- i2c9: i2c-bus@380 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x380 0x40>; +- compatible = "aspeed,ast2400-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <9>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c10_default>; +- status = "disabled"; +- }; +- +- i2c10: i2c-bus@3c0 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x3c0 0x40>; +- compatible = "aspeed,ast2400-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <10>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c11_default>; +- status = "disabled"; +- }; +- +- i2c11: i2c-bus@400 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x400 0x40>; +- compatible = "aspeed,ast2400-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <11>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c12_default>; +- status = "disabled"; +- }; +- +- i2c12: i2c-bus@440 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x440 0x40>; +- compatible = "aspeed,ast2400-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <12>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c13_default>; +- status = "disabled"; +- }; +- +- i2c13: i2c-bus@480 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x480 0x40>; +- compatible = "aspeed,ast2400-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <13>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c14_default>; +- status = "disabled"; +- }; +-}; +- +-&pinctrl { +- pinctrl_acpi_default: acpi_default { +- function = "ACPI"; +- groups = "ACPI"; +- }; +- +- pinctrl_adc0_default: adc0_default { +- function = "ADC0"; +- groups = "ADC0"; +- }; +- +- pinctrl_adc1_default: adc1_default { +- function = "ADC1"; +- groups = "ADC1"; +- }; +- +- pinctrl_adc10_default: adc10_default { +- function = "ADC10"; +- groups = "ADC10"; +- }; +- +- pinctrl_adc11_default: adc11_default { +- function = "ADC11"; +- groups = "ADC11"; +- }; +- +- pinctrl_adc12_default: adc12_default { +- function = "ADC12"; +- groups = "ADC12"; +- }; +- +- pinctrl_adc13_default: adc13_default { +- function = "ADC13"; +- groups = "ADC13"; +- }; +- +- pinctrl_adc14_default: adc14_default { +- function = "ADC14"; +- groups = "ADC14"; +- }; +- +- pinctrl_adc15_default: adc15_default { +- function = "ADC15"; +- groups = "ADC15"; +- }; +- +- pinctrl_adc2_default: adc2_default { +- function = "ADC2"; +- groups = "ADC2"; +- }; +- +- pinctrl_adc3_default: adc3_default { +- function = "ADC3"; +- groups = "ADC3"; +- }; +- +- pinctrl_adc4_default: adc4_default { +- function = "ADC4"; +- groups = "ADC4"; +- }; +- +- pinctrl_adc5_default: adc5_default { +- function = "ADC5"; +- groups = "ADC5"; +- }; +- +- pinctrl_adc6_default: adc6_default { +- function = "ADC6"; +- groups = "ADC6"; +- }; +- +- pinctrl_adc7_default: adc7_default { +- function = "ADC7"; +- groups = "ADC7"; +- }; +- +- pinctrl_adc8_default: adc8_default { +- function = "ADC8"; +- groups = "ADC8"; +- }; +- +- pinctrl_adc9_default: adc9_default { +- function = "ADC9"; +- groups = "ADC9"; +- }; +- +- pinctrl_bmcint_default: bmcint_default { +- function = "BMCINT"; +- groups = "BMCINT"; +- }; +- +- pinctrl_ddcclk_default: ddcclk_default { +- function = "DDCCLK"; +- groups = "DDCCLK"; +- }; +- +- pinctrl_ddcdat_default: ddcdat_default { +- function = "DDCDAT"; +- groups = "DDCDAT"; +- }; +- +- pinctrl_extrst_default: extrst_default { +- function = "EXTRST"; +- groups = "EXTRST"; +- }; +- +- pinctrl_flack_default: flack_default { +- function = "FLACK"; +- groups = "FLACK"; +- }; +- +- pinctrl_flbusy_default: flbusy_default { +- function = "FLBUSY"; +- groups = "FLBUSY"; +- }; +- +- pinctrl_flwp_default: flwp_default { +- function = "FLWP"; +- groups = "FLWP"; +- }; +- +- pinctrl_gpid_default: gpid_default { +- function = "GPID"; +- groups = "GPID"; +- }; +- +- pinctrl_gpid0_default: gpid0_default { +- function = "GPID0"; +- groups = "GPID0"; +- }; +- +- pinctrl_gpid2_default: gpid2_default { +- function = "GPID2"; +- groups = "GPID2"; +- }; +- +- pinctrl_gpid4_default: gpid4_default { +- function = "GPID4"; +- groups = "GPID4"; +- }; +- +- pinctrl_gpid6_default: gpid6_default { +- function = "GPID6"; +- groups = "GPID6"; +- }; +- +- pinctrl_gpie0_default: gpie0_default { +- function = "GPIE0"; +- groups = "GPIE0"; +- }; +- +- pinctrl_gpie2_default: gpie2_default { +- function = "GPIE2"; +- groups = "GPIE2"; +- }; +- +- pinctrl_gpie4_default: gpie4_default { +- function = "GPIE4"; +- groups = "GPIE4"; +- }; +- +- pinctrl_gpie6_default: gpie6_default { +- function = "GPIE6"; +- groups = "GPIE6"; +- }; +- +- pinctrl_i2c10_default: i2c10_default { +- function = "I2C10"; +- groups = "I2C10"; +- }; +- +- pinctrl_i2c11_default: i2c11_default { +- function = "I2C11"; +- groups = "I2C11"; +- }; +- +- pinctrl_i2c12_default: i2c12_default { +- function = "I2C12"; +- groups = "I2C12"; +- }; +- +- pinctrl_i2c13_default: i2c13_default { +- function = "I2C13"; +- groups = "I2C13"; +- }; +- +- pinctrl_i2c14_default: i2c14_default { +- function = "I2C14"; +- groups = "I2C14"; +- }; +- +- pinctrl_i2c3_default: i2c3_default { +- function = "I2C3"; +- groups = "I2C3"; +- }; +- +- pinctrl_i2c4_default: i2c4_default { +- function = "I2C4"; +- groups = "I2C4"; +- }; +- +- pinctrl_i2c5_default: i2c5_default { +- function = "I2C5"; +- groups = "I2C5"; +- }; +- +- pinctrl_i2c6_default: i2c6_default { +- function = "I2C6"; +- groups = "I2C6"; +- }; +- +- pinctrl_i2c7_default: i2c7_default { +- function = "I2C7"; +- groups = "I2C7"; +- }; +- +- pinctrl_i2c8_default: i2c8_default { +- function = "I2C8"; +- groups = "I2C8"; +- }; +- +- pinctrl_i2c9_default: i2c9_default { +- function = "I2C9"; +- groups = "I2C9"; +- }; +- +- pinctrl_lpcpd_default: lpcpd_default { +- function = "LPCPD"; +- groups = "LPCPD"; +- }; +- +- pinctrl_lpcpme_default: lpcpme_default { +- function = "LPCPME"; +- groups = "LPCPME"; +- }; +- +- pinctrl_lpcrst_default: lpcrst_default { +- function = "LPCRST"; +- groups = "LPCRST"; +- }; +- +- pinctrl_lpcsmi_default: lpcsmi_default { +- function = "LPCSMI"; +- groups = "LPCSMI"; +- }; +- +- pinctrl_mac1link_default: mac1link_default { +- function = "MAC1LINK"; +- groups = "MAC1LINK"; +- }; +- +- pinctrl_mac2link_default: mac2link_default { +- function = "MAC2LINK"; +- groups = "MAC2LINK"; +- }; +- +- pinctrl_mdio1_default: mdio1_default { +- function = "MDIO1"; +- groups = "MDIO1"; +- }; +- +- pinctrl_mdio2_default: mdio2_default { +- function = "MDIO2"; +- groups = "MDIO2"; +- }; +- +- pinctrl_ncts1_default: ncts1_default { +- function = "NCTS1"; +- groups = "NCTS1"; +- }; +- +- pinctrl_ncts2_default: ncts2_default { +- function = "NCTS2"; +- groups = "NCTS2"; +- }; +- +- pinctrl_ncts3_default: ncts3_default { +- function = "NCTS3"; +- groups = "NCTS3"; +- }; +- +- pinctrl_ncts4_default: ncts4_default { +- function = "NCTS4"; +- groups = "NCTS4"; +- }; +- +- pinctrl_ndcd1_default: ndcd1_default { +- function = "NDCD1"; +- groups = "NDCD1"; +- }; +- +- pinctrl_ndcd2_default: ndcd2_default { +- function = "NDCD2"; +- groups = "NDCD2"; +- }; +- +- pinctrl_ndcd3_default: ndcd3_default { +- function = "NDCD3"; +- groups = "NDCD3"; +- }; +- +- pinctrl_ndcd4_default: ndcd4_default { +- function = "NDCD4"; +- groups = "NDCD4"; +- }; +- +- pinctrl_ndsr1_default: ndsr1_default { +- function = "NDSR1"; +- groups = "NDSR1"; +- }; +- +- pinctrl_ndsr2_default: ndsr2_default { +- function = "NDSR2"; +- groups = "NDSR2"; +- }; +- +- pinctrl_ndsr3_default: ndsr3_default { +- function = "NDSR3"; +- groups = "NDSR3"; +- }; +- +- pinctrl_ndsr4_default: ndsr4_default { +- function = "NDSR4"; +- groups = "NDSR4"; +- }; +- +- pinctrl_ndtr1_default: ndtr1_default { +- function = "NDTR1"; +- groups = "NDTR1"; +- }; +- +- pinctrl_ndtr2_default: ndtr2_default { +- function = "NDTR2"; +- groups = "NDTR2"; +- }; +- +- pinctrl_ndtr3_default: ndtr3_default { +- function = "NDTR3"; +- groups = "NDTR3"; +- }; +- +- pinctrl_ndtr4_default: ndtr4_default { +- function = "NDTR4"; +- groups = "NDTR4"; +- }; +- +- pinctrl_ndts4_default: ndts4_default { +- function = "NDTS4"; +- groups = "NDTS4"; +- }; +- +- pinctrl_nri1_default: nri1_default { +- function = "NRI1"; +- groups = "NRI1"; +- }; +- +- pinctrl_nri2_default: nri2_default { +- function = "NRI2"; +- groups = "NRI2"; +- }; +- +- pinctrl_nri3_default: nri3_default { +- function = "NRI3"; +- groups = "NRI3"; +- }; +- +- pinctrl_nri4_default: nri4_default { +- function = "NRI4"; +- groups = "NRI4"; +- }; +- +- pinctrl_nrts1_default: nrts1_default { +- function = "NRTS1"; +- groups = "NRTS1"; +- }; +- +- pinctrl_nrts2_default: nrts2_default { +- function = "NRTS2"; +- groups = "NRTS2"; +- }; +- +- pinctrl_nrts3_default: nrts3_default { +- function = "NRTS3"; +- groups = "NRTS3"; +- }; +- +- pinctrl_oscclk_default: oscclk_default { +- function = "OSCCLK"; +- groups = "OSCCLK"; +- }; +- +- pinctrl_pwm0_default: pwm0_default { +- function = "PWM0"; +- groups = "PWM0"; +- }; +- +- pinctrl_pwm1_default: pwm1_default { +- function = "PWM1"; +- groups = "PWM1"; +- }; +- +- pinctrl_pwm2_default: pwm2_default { +- function = "PWM2"; +- groups = "PWM2"; +- }; +- +- pinctrl_pwm3_default: pwm3_default { +- function = "PWM3"; +- groups = "PWM3"; +- }; +- +- pinctrl_pwm4_default: pwm4_default { +- function = "PWM4"; +- groups = "PWM4"; +- }; +- +- pinctrl_pwm5_default: pwm5_default { +- function = "PWM5"; +- groups = "PWM5"; +- }; +- +- pinctrl_pwm6_default: pwm6_default { +- function = "PWM6"; +- groups = "PWM6"; +- }; +- +- pinctrl_pwm7_default: pwm7_default { +- function = "PWM7"; +- groups = "PWM7"; +- }; +- +- pinctrl_rgmii1_default: rgmii1_default { +- function = "RGMII1"; +- groups = "RGMII1"; +- }; +- +- pinctrl_rgmii2_default: rgmii2_default { +- function = "RGMII2"; +- groups = "RGMII2"; +- }; +- +- pinctrl_rmii1_default: rmii1_default { +- function = "RMII1"; +- groups = "RMII1"; +- }; +- +- pinctrl_rmii2_default: rmii2_default { +- function = "RMII2"; +- groups = "RMII2"; +- }; +- +- pinctrl_rom16_default: rom16_default { +- function = "ROM16"; +- groups = "ROM16"; +- }; +- +- pinctrl_rom8_default: rom8_default { +- function = "ROM8"; +- groups = "ROM8"; +- }; +- +- pinctrl_romcs1_default: romcs1_default { +- function = "ROMCS1"; +- groups = "ROMCS1"; +- }; +- +- pinctrl_romcs2_default: romcs2_default { +- function = "ROMCS2"; +- groups = "ROMCS2"; +- }; +- +- pinctrl_romcs3_default: romcs3_default { +- function = "ROMCS3"; +- groups = "ROMCS3"; +- }; +- +- pinctrl_romcs4_default: romcs4_default { +- function = "ROMCS4"; +- groups = "ROMCS4"; +- }; +- +- pinctrl_rxd1_default: rxd1_default { +- function = "RXD1"; +- groups = "RXD1"; +- }; +- +- pinctrl_rxd2_default: rxd2_default { +- function = "RXD2"; +- groups = "RXD2"; +- }; +- +- pinctrl_rxd3_default: rxd3_default { +- function = "RXD3"; +- groups = "RXD3"; +- }; +- +- pinctrl_rxd4_default: rxd4_default { +- function = "RXD4"; +- groups = "RXD4"; +- }; +- +- pinctrl_salt1_default: salt1_default { +- function = "SALT1"; +- groups = "SALT1"; +- }; +- +- pinctrl_salt2_default: salt2_default { +- function = "SALT2"; +- groups = "SALT2"; +- }; +- +- pinctrl_salt3_default: salt3_default { +- function = "SALT3"; +- groups = "SALT3"; +- }; +- +- pinctrl_salt4_default: salt4_default { +- function = "SALT4"; +- groups = "SALT4"; +- }; +- +- pinctrl_sd1_default: sd1_default { +- function = "SD1"; +- groups = "SD1"; +- }; +- +- pinctrl_sd2_default: sd2_default { +- function = "SD2"; +- groups = "SD2"; +- }; +- +- pinctrl_sgpmck_default: sgpmck_default { +- function = "SGPMCK"; +- groups = "SGPMCK"; +- }; +- +- pinctrl_sgpmi_default: sgpmi_default { +- function = "SGPMI"; +- groups = "SGPMI"; +- }; +- +- pinctrl_sgpmld_default: sgpmld_default { +- function = "SGPMLD"; +- groups = "SGPMLD"; +- }; +- +- pinctrl_sgpmo_default: sgpmo_default { +- function = "SGPMO"; +- groups = "SGPMO"; +- }; +- +- pinctrl_sgpsck_default: sgpsck_default { +- function = "SGPSCK"; +- groups = "SGPSCK"; +- }; +- +- pinctrl_sgpsi0_default: sgpsi0_default { +- function = "SGPSI0"; +- groups = "SGPSI0"; +- }; +- +- pinctrl_sgpsi1_default: sgpsi1_default { +- function = "SGPSI1"; +- groups = "SGPSI1"; +- }; +- +- pinctrl_sgpsld_default: sgpsld_default { +- function = "SGPSLD"; +- groups = "SGPSLD"; +- }; +- +- pinctrl_sioonctrl_default: sioonctrl_default { +- function = "SIOONCTRL"; +- groups = "SIOONCTRL"; +- }; +- +- pinctrl_siopbi_default: siopbi_default { +- function = "SIOPBI"; +- groups = "SIOPBI"; +- }; +- +- pinctrl_siopbo_default: siopbo_default { +- function = "SIOPBO"; +- groups = "SIOPBO"; +- }; +- +- pinctrl_siopwreq_default: siopwreq_default { +- function = "SIOPWREQ"; +- groups = "SIOPWREQ"; +- }; +- +- pinctrl_siopwrgd_default: siopwrgd_default { +- function = "SIOPWRGD"; +- groups = "SIOPWRGD"; +- }; +- +- pinctrl_sios3_default: sios3_default { +- function = "SIOS3"; +- groups = "SIOS3"; +- }; +- +- pinctrl_sios5_default: sios5_default { +- function = "SIOS5"; +- groups = "SIOS5"; +- }; +- +- pinctrl_siosci_default: siosci_default { +- function = "SIOSCI"; +- groups = "SIOSCI"; +- }; +- +- pinctrl_spi1_default: spi1_default { +- function = "SPI1"; +- groups = "SPI1"; +- }; +- +- pinctrl_spi1debug_default: spi1debug_default { +- function = "SPI1DEBUG"; +- groups = "SPI1DEBUG"; +- }; +- +- pinctrl_spi1passthru_default: spi1passthru_default { +- function = "SPI1PASSTHRU"; +- groups = "SPI1PASSTHRU"; +- }; +- +- pinctrl_spics1_default: spics1_default { +- function = "SPICS1"; +- groups = "SPICS1"; +- }; +- +- pinctrl_timer3_default: timer3_default { +- function = "TIMER3"; +- groups = "TIMER3"; +- }; +- +- pinctrl_timer4_default: timer4_default { +- function = "TIMER4"; +- groups = "TIMER4"; +- }; +- +- pinctrl_timer5_default: timer5_default { +- function = "TIMER5"; +- groups = "TIMER5"; +- }; +- +- pinctrl_timer6_default: timer6_default { +- function = "TIMER6"; +- groups = "TIMER6"; +- }; +- +- pinctrl_timer7_default: timer7_default { +- function = "TIMER7"; +- groups = "TIMER7"; +- }; +- +- pinctrl_timer8_default: timer8_default { +- function = "TIMER8"; +- groups = "TIMER8"; +- }; +- +- pinctrl_txd1_default: txd1_default { +- function = "TXD1"; +- groups = "TXD1"; +- }; +- +- pinctrl_txd2_default: txd2_default { +- function = "TXD2"; +- groups = "TXD2"; +- }; +- +- pinctrl_txd3_default: txd3_default { +- function = "TXD3"; +- groups = "TXD3"; +- }; +- +- pinctrl_txd4_default: txd4_default { +- function = "TXD4"; +- groups = "TXD4"; +- }; +- +- pinctrl_uart6_default: uart6_default { +- function = "UART6"; +- groups = "UART6"; +- }; +- +- pinctrl_usbcki_default: usbcki_default { +- function = "USBCKI"; +- groups = "USBCKI"; +- }; +- +- pinctrl_usb2h_default: usb2h_default { +- function = "USB2H1"; +- groups = "USB2H1"; +- }; +- +- pinctrl_usb2d_default: usb2d_default { +- function = "USB2D1"; +- groups = "USB2D1"; +- }; +- +- pinctrl_vgabios_rom_default: vgabios_rom_default { +- function = "VGABIOS_ROM"; +- groups = "VGABIOS_ROM"; +- }; +- +- pinctrl_vgahs_default: vgahs_default { +- function = "VGAHS"; +- groups = "VGAHS"; +- }; +- +- pinctrl_vgavs_default: vgavs_default { +- function = "VGAVS"; +- groups = "VGAVS"; +- }; +- +- pinctrl_vpi18_default: vpi18_default { +- function = "VPI18"; +- groups = "VPI18"; +- }; +- +- pinctrl_vpi24_default: vpi24_default { +- function = "VPI24"; +- groups = "VPI24"; +- }; +- +- pinctrl_vpi30_default: vpi30_default { +- function = "VPI30"; +- groups = "VPI30"; +- }; +- +- pinctrl_vpo12_default: vpo12_default { +- function = "VPO12"; +- groups = "VPO12"; +- }; +- +- pinctrl_vpo24_default: vpo24_default { +- function = "VPO24"; +- groups = "VPO24"; +- }; +- +- pinctrl_wdtrst1_default: wdtrst1_default { +- function = "WDTRST1"; +- groups = "WDTRST1"; +- }; +- +- pinctrl_wdtrst2_default: wdtrst2_default { +- function = "WDTRST2"; +- groups = "WDTRST2"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-g5.dtsi b/scripts/dtc/include-prefixes/arm/aspeed-g5.dtsi +deleted file mode 100644 +index 73ca1ec6fc24..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-g5.dtsi ++++ /dev/null +@@ -1,1627 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-#include +-#include +- +-/ { +- model = "Aspeed BMC"; +- compatible = "aspeed,ast2500"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&vic>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c7; +- i2c8 = &i2c8; +- i2c9 = &i2c9; +- i2c10 = &i2c10; +- i2c11 = &i2c11; +- i2c12 = &i2c12; +- i2c13 = &i2c13; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- serial4 = &uart5; +- serial5 = &vuart; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,arm1176jzf-s"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0>; +- }; +- +- ahb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- fmc: spi@1e620000 { +- reg = < 0x1e620000 0xc4 +- 0x20000000 0x10000000 >; +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "aspeed,ast2500-fmc"; +- clocks = <&syscon ASPEED_CLK_AHB>; +- status = "disabled"; +- interrupts = <19>; +- flash@0 { +- reg = < 0 >; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- status = "disabled"; +- }; +- flash@1 { +- reg = < 1 >; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- status = "disabled"; +- }; +- flash@2 { +- reg = < 2 >; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- status = "disabled"; +- }; +- }; +- +- spi1: spi@1e630000 { +- reg = < 0x1e630000 0xc4 +- 0x30000000 0x08000000 >; +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "aspeed,ast2500-spi"; +- clocks = <&syscon ASPEED_CLK_AHB>; +- status = "disabled"; +- flash@0 { +- reg = < 0 >; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- status = "disabled"; +- }; +- flash@1 { +- reg = < 1 >; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- status = "disabled"; +- }; +- }; +- +- spi2: spi@1e631000 { +- reg = < 0x1e631000 0xc4 +- 0x38000000 0x08000000 >; +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "aspeed,ast2500-spi"; +- clocks = <&syscon ASPEED_CLK_AHB>; +- status = "disabled"; +- flash@0 { +- reg = < 0 >; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- status = "disabled"; +- }; +- flash@1 { +- reg = < 1 >; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- status = "disabled"; +- }; +- }; +- +- vic: interrupt-controller@1e6c0080 { +- compatible = "aspeed,ast2400-vic"; +- interrupt-controller; +- #interrupt-cells = <1>; +- valid-sources = <0xfefff7ff 0x0807ffff>; +- reg = <0x1e6c0080 0x80>; +- }; +- +- cvic: copro-interrupt-controller@1e6c2000 { +- compatible = "aspeed,ast2500-cvic", "aspeed-cvic"; +- valid-sources = <0xffffffff>; +- copro-sw-interrupts = <1>; +- reg = <0x1e6c2000 0x80>; +- }; +- +- mac0: ethernet@1e660000 { +- compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; +- reg = <0x1e660000 0x180>; +- interrupts = <2>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; +- status = "disabled"; +- }; +- +- mac1: ethernet@1e680000 { +- compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; +- reg = <0x1e680000 0x180>; +- interrupts = <3>; +- clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; +- status = "disabled"; +- }; +- +- ehci0: usb@1e6a1000 { +- compatible = "aspeed,ast2500-ehci", "generic-ehci"; +- reg = <0x1e6a1000 0x100>; +- interrupts = <5>; +- clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb2ah_default>; +- status = "disabled"; +- }; +- +- ehci1: usb@1e6a3000 { +- compatible = "aspeed,ast2500-ehci", "generic-ehci"; +- reg = <0x1e6a3000 0x100>; +- interrupts = <13>; +- clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb2bh_default>; +- status = "disabled"; +- }; +- +- uhci: usb@1e6b0000 { +- compatible = "aspeed,ast2500-uhci", "generic-uhci"; +- reg = <0x1e6b0000 0x100>; +- interrupts = <14>; +- #ports = <2>; +- clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; +- status = "disabled"; +- /* +- * No default pinmux, it will follow EHCI, use an explicit pinmux +- * override if you don't enable EHCI +- */ +- }; +- +- vhub: usb-vhub@1e6a0000 { +- compatible = "aspeed,ast2500-usb-vhub"; +- reg = <0x1e6a0000 0x300>; +- interrupts = <5>; +- clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; +- aspeed,vhub-downstream-ports = <5>; +- aspeed,vhub-generic-endpoints = <15>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb2ad_default>; +- status = "disabled"; +- }; +- +- apb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- edac: memory-controller@1e6e0000 { +- compatible = "aspeed,ast2500-sdram-edac"; +- reg = <0x1e6e0000 0x174>; +- interrupts = <0>; +- status = "disabled"; +- }; +- +- syscon: syscon@1e6e2000 { +- compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; +- reg = <0x1e6e2000 0x1a8>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1e6e2000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- +- scu_ic: interrupt-controller@18 { +- #interrupt-cells = <1>; +- compatible = "aspeed,ast2500-scu-ic"; +- reg = <0x18 0x4>; +- interrupts = <21>; +- interrupt-controller; +- }; +- +- p2a: p2a-control@2c { +- compatible = "aspeed,ast2500-p2a-ctrl"; +- reg = <0x2c 0x4>; +- status = "disabled"; +- }; +- +- silicon-id@7c { +- compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id"; +- reg = <0x7c 0x4 0x150 0x8>; +- }; +- +- pinctrl: pinctrl@80 { +- compatible = "aspeed,ast2500-pinctrl"; +- reg = <0x80 0x18>, <0xa0 0x10>; +- aspeed,external-nodes = <&gfx>, <&lhc>; +- }; +- }; +- +- rng: hwrng@1e6e2078 { +- compatible = "timeriomem_rng"; +- reg = <0x1e6e2078 0x4>; +- period = <1>; +- quality = <100>; +- }; +- +- gfx: display@1e6e6000 { +- compatible = "aspeed,ast2500-gfx", "syscon"; +- reg = <0x1e6e6000 0x1000>; +- reg-io-width = <4>; +- clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; +- resets = <&syscon ASPEED_RESET_CRT1>; +- syscon = <&syscon>; +- status = "disabled"; +- interrupts = <0x19>; +- }; +- +- xdma: xdma@1e6e7000 { +- compatible = "aspeed,ast2500-xdma"; +- reg = <0x1e6e7000 0x100>; +- clocks = <&syscon ASPEED_CLK_GATE_BCLK>; +- resets = <&syscon ASPEED_RESET_XDMA>; +- interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>; +- aspeed,pcie-device = "bmc"; +- aspeed,scu = <&syscon>; +- status = "disabled"; +- }; +- +- adc: adc@1e6e9000 { +- compatible = "aspeed,ast2500-adc"; +- reg = <0x1e6e9000 0xb0>; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_ADC>; +- #io-channel-cells = <1>; +- status = "disabled"; +- }; +- +- video: video@1e700000 { +- compatible = "aspeed,ast2500-video-engine"; +- reg = <0x1e700000 0x1000>; +- clocks = <&syscon ASPEED_CLK_GATE_VCLK>, +- <&syscon ASPEED_CLK_GATE_ECLK>; +- clock-names = "vclk", "eclk"; +- interrupts = <7>; +- status = "disabled"; +- }; +- +- sram: sram@1e720000 { +- compatible = "mmio-sram"; +- reg = <0x1e720000 0x9000>; // 36K +- }; +- +- sdmmc: sd-controller@1e740000 { +- compatible = "aspeed,ast2500-sd-controller"; +- reg = <0x1e740000 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1e740000 0x10000>; +- clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; +- status = "disabled"; +- +- sdhci0: sdhci@100 { +- compatible = "aspeed,ast2500-sdhci"; +- reg = <0x100 0x100>; +- interrupts = <26>; +- sdhci,auto-cmd12; +- clocks = <&syscon ASPEED_CLK_SDIO>; +- status = "disabled"; +- }; +- +- sdhci1: sdhci@200 { +- compatible = "aspeed,ast2500-sdhci"; +- reg = <0x200 0x100>; +- interrupts = <26>; +- sdhci,auto-cmd12; +- clocks = <&syscon ASPEED_CLK_SDIO>; +- status = "disabled"; +- }; +- }; +- +- gpio: gpio@1e780000 { +- #gpio-cells = <2>; +- gpio-controller; +- compatible = "aspeed,ast2500-gpio"; +- reg = <0x1e780000 0x200>; +- interrupts = <20>; +- gpio-ranges = <&pinctrl 0 0 232>; +- clocks = <&syscon ASPEED_CLK_APB>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- sgpio: sgpio@1e780200 { +- #gpio-cells = <2>; +- compatible = "aspeed,ast2500-sgpio"; +- gpio-controller; +- interrupts = <40>; +- reg = <0x1e780200 0x0100>; +- clocks = <&syscon ASPEED_CLK_APB>; +- interrupt-controller; +- bus-frequency = <12000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sgpm_default>; +- status = "disabled"; +- }; +- +- rtc: rtc@1e781000 { +- compatible = "aspeed,ast2500-rtc"; +- reg = <0x1e781000 0x18>; +- status = "disabled"; +- }; +- +- timer: timer@1e782000 { +- /* This timer is a Faraday FTTMR010 derivative */ +- compatible = "aspeed,ast2400-timer"; +- reg = <0x1e782000 0x90>; +- interrupts = <16 17 18 35 36 37 38 39>; +- clocks = <&syscon ASPEED_CLK_APB>; +- clock-names = "PCLK"; +- }; +- +- uart1: serial@1e783000 { +- compatible = "ns16550a"; +- reg = <0x1e783000 0x20>; +- reg-shift = <2>; +- interrupts = <9>; +- clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; +- resets = <&lpc_reset 4>; +- no-loopback-test; +- status = "disabled"; +- }; +- +- uart5: serial@1e784000 { +- compatible = "ns16550a"; +- reg = <0x1e784000 0x20>; +- reg-shift = <2>; +- interrupts = <10>; +- clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; +- no-loopback-test; +- status = "disabled"; +- }; +- +- wdt1: watchdog@1e785000 { +- compatible = "aspeed,ast2500-wdt"; +- reg = <0x1e785000 0x20>; +- clocks = <&syscon ASPEED_CLK_APB>; +- }; +- +- wdt2: watchdog@1e785020 { +- compatible = "aspeed,ast2500-wdt"; +- reg = <0x1e785020 0x20>; +- clocks = <&syscon ASPEED_CLK_APB>; +- }; +- +- wdt3: watchdog@1e785040 { +- compatible = "aspeed,ast2500-wdt"; +- reg = <0x1e785040 0x20>; +- clocks = <&syscon ASPEED_CLK_APB>; +- status = "disabled"; +- }; +- +- pwm_tacho: pwm-tacho-controller@1e786000 { +- compatible = "aspeed,ast2500-pwm-tacho"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x1e786000 0x1000>; +- clocks = <&syscon ASPEED_CLK_24M>; +- resets = <&syscon ASPEED_RESET_PWM>; +- status = "disabled"; +- }; +- +- vuart: serial@1e787000 { +- compatible = "aspeed,ast2500-vuart"; +- reg = <0x1e787000 0x40>; +- reg-shift = <2>; +- interrupts = <8>; +- clocks = <&syscon ASPEED_CLK_APB>; +- no-loopback-test; +- status = "disabled"; +- }; +- +- lpc: lpc@1e789000 { +- compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"; +- reg = <0x1e789000 0x1000>; +- reg-io-width = <4>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1e789000 0x1000>; +- +- kcs1: kcs@24 { +- compatible = "aspeed,ast2500-kcs-bmc-v2"; +- reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; +- interrupts = <8>; +- status = "disabled"; +- }; +- +- kcs2: kcs@28 { +- compatible = "aspeed,ast2500-kcs-bmc-v2"; +- reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; +- interrupts = <8>; +- status = "disabled"; +- }; +- +- kcs3: kcs@2c { +- compatible = "aspeed,ast2500-kcs-bmc-v2"; +- reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; +- interrupts = <8>; +- status = "disabled"; +- }; +- +- kcs4: kcs@114 { +- compatible = "aspeed,ast2500-kcs-bmc-v2"; +- reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>; +- interrupts = <8>; +- status = "disabled"; +- }; +- +- lpc_ctrl: lpc-ctrl@80 { +- compatible = "aspeed,ast2500-lpc-ctrl"; +- reg = <0x80 0x10>; +- clocks = <&syscon ASPEED_CLK_GATE_LCLK>; +- status = "disabled"; +- }; +- +- lpc_snoop: lpc-snoop@90 { +- compatible = "aspeed,ast2500-lpc-snoop"; +- reg = <0x90 0x8>; +- interrupts = <8>; +- clocks = <&syscon ASPEED_CLK_GATE_LCLK>; +- status = "disabled"; +- }; +- +- lpc_reset: reset-controller@98 { +- compatible = "aspeed,ast2500-lpc-reset"; +- reg = <0x98 0x4>; +- #reset-cells = <1>; +- }; +- +- lhc: lhc@a0 { +- compatible = "aspeed,ast2500-lhc"; +- reg = <0xa0 0x24 0xc8 0x8>; +- }; +- +- +- ibt: ibt@140 { +- compatible = "aspeed,ast2500-ibt-bmc"; +- reg = <0x140 0x18>; +- interrupts = <8>; +- status = "disabled"; +- }; +- }; +- +- uart2: serial@1e78d000 { +- compatible = "ns16550a"; +- reg = <0x1e78d000 0x20>; +- reg-shift = <2>; +- interrupts = <32>; +- clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; +- resets = <&lpc_reset 5>; +- no-loopback-test; +- status = "disabled"; +- }; +- +- uart3: serial@1e78e000 { +- compatible = "ns16550a"; +- reg = <0x1e78e000 0x20>; +- reg-shift = <2>; +- interrupts = <33>; +- clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; +- resets = <&lpc_reset 6>; +- no-loopback-test; +- status = "disabled"; +- }; +- +- uart4: serial@1e78f000 { +- compatible = "ns16550a"; +- reg = <0x1e78f000 0x20>; +- reg-shift = <2>; +- interrupts = <34>; +- clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; +- resets = <&lpc_reset 7>; +- no-loopback-test; +- status = "disabled"; +- }; +- +- i2c: bus@1e78a000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1e78a000 0x1000>; +- }; +- }; +- }; +-}; +- +-&i2c { +- i2c_ic: interrupt-controller@0 { +- #interrupt-cells = <1>; +- compatible = "aspeed,ast2500-i2c-ic"; +- reg = <0x0 0x40>; +- interrupts = <12>; +- interrupt-controller; +- }; +- +- i2c0: i2c-bus@40 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x40 0x40>; +- compatible = "aspeed,ast2500-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <0>; +- interrupt-parent = <&i2c_ic>; +- status = "disabled"; +- /* Does not need pinctrl properties */ +- }; +- +- i2c1: i2c-bus@80 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x80 0x40>; +- compatible = "aspeed,ast2500-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <1>; +- interrupt-parent = <&i2c_ic>; +- status = "disabled"; +- /* Does not need pinctrl properties */ +- }; +- +- i2c2: i2c-bus@c0 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0xc0 0x40>; +- compatible = "aspeed,ast2500-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <2>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3_default>; +- status = "disabled"; +- }; +- +- i2c3: i2c-bus@100 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x100 0x40>; +- compatible = "aspeed,ast2500-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <3>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4_default>; +- status = "disabled"; +- }; +- +- i2c4: i2c-bus@140 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x140 0x40>; +- compatible = "aspeed,ast2500-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <4>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c5_default>; +- status = "disabled"; +- }; +- +- i2c5: i2c-bus@180 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x180 0x40>; +- compatible = "aspeed,ast2500-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <5>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c6_default>; +- status = "disabled"; +- }; +- +- i2c6: i2c-bus@1c0 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x1c0 0x40>; +- compatible = "aspeed,ast2500-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <6>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c7_default>; +- status = "disabled"; +- }; +- +- i2c7: i2c-bus@300 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x300 0x40>; +- compatible = "aspeed,ast2500-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <7>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c8_default>; +- status = "disabled"; +- }; +- +- i2c8: i2c-bus@340 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x340 0x40>; +- compatible = "aspeed,ast2500-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <8>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c9_default>; +- status = "disabled"; +- }; +- +- i2c9: i2c-bus@380 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x380 0x40>; +- compatible = "aspeed,ast2500-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <9>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c10_default>; +- status = "disabled"; +- }; +- +- i2c10: i2c-bus@3c0 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x3c0 0x40>; +- compatible = "aspeed,ast2500-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <10>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c11_default>; +- status = "disabled"; +- }; +- +- i2c11: i2c-bus@400 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x400 0x40>; +- compatible = "aspeed,ast2500-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <11>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c12_default>; +- status = "disabled"; +- }; +- +- i2c12: i2c-bus@440 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x440 0x40>; +- compatible = "aspeed,ast2500-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <12>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c13_default>; +- status = "disabled"; +- }; +- +- i2c13: i2c-bus@480 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- +- reg = <0x480 0x40>; +- compatible = "aspeed,ast2500-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB>; +- resets = <&syscon ASPEED_RESET_I2C>; +- bus-frequency = <100000>; +- interrupts = <13>; +- interrupt-parent = <&i2c_ic>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c14_default>; +- status = "disabled"; +- }; +-}; +- +-&pinctrl { +- pinctrl_acpi_default: acpi_default { +- function = "ACPI"; +- groups = "ACPI"; +- }; +- +- pinctrl_adc0_default: adc0_default { +- function = "ADC0"; +- groups = "ADC0"; +- }; +- +- pinctrl_adc1_default: adc1_default { +- function = "ADC1"; +- groups = "ADC1"; +- }; +- +- pinctrl_adc10_default: adc10_default { +- function = "ADC10"; +- groups = "ADC10"; +- }; +- +- pinctrl_adc11_default: adc11_default { +- function = "ADC11"; +- groups = "ADC11"; +- }; +- +- pinctrl_adc12_default: adc12_default { +- function = "ADC12"; +- groups = "ADC12"; +- }; +- +- pinctrl_adc13_default: adc13_default { +- function = "ADC13"; +- groups = "ADC13"; +- }; +- +- pinctrl_adc14_default: adc14_default { +- function = "ADC14"; +- groups = "ADC14"; +- }; +- +- pinctrl_adc15_default: adc15_default { +- function = "ADC15"; +- groups = "ADC15"; +- }; +- +- pinctrl_adc2_default: adc2_default { +- function = "ADC2"; +- groups = "ADC2"; +- }; +- +- pinctrl_adc3_default: adc3_default { +- function = "ADC3"; +- groups = "ADC3"; +- }; +- +- pinctrl_adc4_default: adc4_default { +- function = "ADC4"; +- groups = "ADC4"; +- }; +- +- pinctrl_adc5_default: adc5_default { +- function = "ADC5"; +- groups = "ADC5"; +- }; +- +- pinctrl_adc6_default: adc6_default { +- function = "ADC6"; +- groups = "ADC6"; +- }; +- +- pinctrl_adc7_default: adc7_default { +- function = "ADC7"; +- groups = "ADC7"; +- }; +- +- pinctrl_adc8_default: adc8_default { +- function = "ADC8"; +- groups = "ADC8"; +- }; +- +- pinctrl_adc9_default: adc9_default { +- function = "ADC9"; +- groups = "ADC9"; +- }; +- +- pinctrl_bmcint_default: bmcint_default { +- function = "BMCINT"; +- groups = "BMCINT"; +- }; +- +- pinctrl_ddcclk_default: ddcclk_default { +- function = "DDCCLK"; +- groups = "DDCCLK"; +- }; +- +- pinctrl_ddcdat_default: ddcdat_default { +- function = "DDCDAT"; +- groups = "DDCDAT"; +- }; +- +- pinctrl_espi_default: espi_default { +- function = "ESPI"; +- groups = "ESPI"; +- }; +- +- pinctrl_fwspics1_default: fwspics1_default { +- function = "FWSPICS1"; +- groups = "FWSPICS1"; +- }; +- +- pinctrl_fwspics2_default: fwspics2_default { +- function = "FWSPICS2"; +- groups = "FWSPICS2"; +- }; +- +- pinctrl_gpid0_default: gpid0_default { +- function = "GPID0"; +- groups = "GPID0"; +- }; +- +- pinctrl_gpid2_default: gpid2_default { +- function = "GPID2"; +- groups = "GPID2"; +- }; +- +- pinctrl_gpid4_default: gpid4_default { +- function = "GPID4"; +- groups = "GPID4"; +- }; +- +- pinctrl_gpid6_default: gpid6_default { +- function = "GPID6"; +- groups = "GPID6"; +- }; +- +- pinctrl_gpie0_default: gpie0_default { +- function = "GPIE0"; +- groups = "GPIE0"; +- }; +- +- pinctrl_gpie2_default: gpie2_default { +- function = "GPIE2"; +- groups = "GPIE2"; +- }; +- +- pinctrl_gpie4_default: gpie4_default { +- function = "GPIE4"; +- groups = "GPIE4"; +- }; +- +- pinctrl_gpie6_default: gpie6_default { +- function = "GPIE6"; +- groups = "GPIE6"; +- }; +- +- pinctrl_i2c10_default: i2c10_default { +- function = "I2C10"; +- groups = "I2C10"; +- }; +- +- pinctrl_i2c11_default: i2c11_default { +- function = "I2C11"; +- groups = "I2C11"; +- }; +- +- pinctrl_i2c12_default: i2c12_default { +- function = "I2C12"; +- groups = "I2C12"; +- }; +- +- pinctrl_i2c13_default: i2c13_default { +- function = "I2C13"; +- groups = "I2C13"; +- }; +- +- pinctrl_i2c14_default: i2c14_default { +- function = "I2C14"; +- groups = "I2C14"; +- }; +- +- pinctrl_i2c3_default: i2c3_default { +- function = "I2C3"; +- groups = "I2C3"; +- }; +- +- pinctrl_i2c4_default: i2c4_default { +- function = "I2C4"; +- groups = "I2C4"; +- }; +- +- pinctrl_i2c5_default: i2c5_default { +- function = "I2C5"; +- groups = "I2C5"; +- }; +- +- pinctrl_i2c6_default: i2c6_default { +- function = "I2C6"; +- groups = "I2C6"; +- }; +- +- pinctrl_i2c7_default: i2c7_default { +- function = "I2C7"; +- groups = "I2C7"; +- }; +- +- pinctrl_i2c8_default: i2c8_default { +- function = "I2C8"; +- groups = "I2C8"; +- }; +- +- pinctrl_i2c9_default: i2c9_default { +- function = "I2C9"; +- groups = "I2C9"; +- }; +- +- pinctrl_lad0_default: lad0_default { +- function = "LAD0"; +- groups = "LAD0"; +- }; +- +- pinctrl_lad1_default: lad1_default { +- function = "LAD1"; +- groups = "LAD1"; +- }; +- +- pinctrl_lad2_default: lad2_default { +- function = "LAD2"; +- groups = "LAD2"; +- }; +- +- pinctrl_lad3_default: lad3_default { +- function = "LAD3"; +- groups = "LAD3"; +- }; +- +- pinctrl_lclk_default: lclk_default { +- function = "LCLK"; +- groups = "LCLK"; +- }; +- +- pinctrl_lframe_default: lframe_default { +- function = "LFRAME"; +- groups = "LFRAME"; +- }; +- +- pinctrl_lpchc_default: lpchc_default { +- function = "LPCHC"; +- groups = "LPCHC"; +- }; +- +- pinctrl_lpcpd_default: lpcpd_default { +- function = "LPCPD"; +- groups = "LPCPD"; +- }; +- +- pinctrl_lpcplus_default: lpcplus_default { +- function = "LPCPLUS"; +- groups = "LPCPLUS"; +- }; +- +- pinctrl_lpcpme_default: lpcpme_default { +- function = "LPCPME"; +- groups = "LPCPME"; +- }; +- +- pinctrl_lpcrst_default: lpcrst_default { +- function = "LPCRST"; +- groups = "LPCRST"; +- }; +- +- pinctrl_lpcsmi_default: lpcsmi_default { +- function = "LPCSMI"; +- groups = "LPCSMI"; +- }; +- +- pinctrl_lsirq_default: lsirq_default { +- function = "LSIRQ"; +- groups = "LSIRQ"; +- }; +- +- pinctrl_mac1link_default: mac1link_default { +- function = "MAC1LINK"; +- groups = "MAC1LINK"; +- }; +- +- pinctrl_mac2link_default: mac2link_default { +- function = "MAC2LINK"; +- groups = "MAC2LINK"; +- }; +- +- pinctrl_mdio1_default: mdio1_default { +- function = "MDIO1"; +- groups = "MDIO1"; +- }; +- +- pinctrl_mdio2_default: mdio2_default { +- function = "MDIO2"; +- groups = "MDIO2"; +- }; +- +- pinctrl_ncts1_default: ncts1_default { +- function = "NCTS1"; +- groups = "NCTS1"; +- }; +- +- pinctrl_ncts2_default: ncts2_default { +- function = "NCTS2"; +- groups = "NCTS2"; +- }; +- +- pinctrl_ncts3_default: ncts3_default { +- function = "NCTS3"; +- groups = "NCTS3"; +- }; +- +- pinctrl_ncts4_default: ncts4_default { +- function = "NCTS4"; +- groups = "NCTS4"; +- }; +- +- pinctrl_ndcd1_default: ndcd1_default { +- function = "NDCD1"; +- groups = "NDCD1"; +- }; +- +- pinctrl_ndcd2_default: ndcd2_default { +- function = "NDCD2"; +- groups = "NDCD2"; +- }; +- +- pinctrl_ndcd3_default: ndcd3_default { +- function = "NDCD3"; +- groups = "NDCD3"; +- }; +- +- pinctrl_ndcd4_default: ndcd4_default { +- function = "NDCD4"; +- groups = "NDCD4"; +- }; +- +- pinctrl_ndsr1_default: ndsr1_default { +- function = "NDSR1"; +- groups = "NDSR1"; +- }; +- +- pinctrl_ndsr2_default: ndsr2_default { +- function = "NDSR2"; +- groups = "NDSR2"; +- }; +- +- pinctrl_ndsr3_default: ndsr3_default { +- function = "NDSR3"; +- groups = "NDSR3"; +- }; +- +- pinctrl_ndsr4_default: ndsr4_default { +- function = "NDSR4"; +- groups = "NDSR4"; +- }; +- +- pinctrl_ndtr1_default: ndtr1_default { +- function = "NDTR1"; +- groups = "NDTR1"; +- }; +- +- pinctrl_ndtr2_default: ndtr2_default { +- function = "NDTR2"; +- groups = "NDTR2"; +- }; +- +- pinctrl_ndtr3_default: ndtr3_default { +- function = "NDTR3"; +- groups = "NDTR3"; +- }; +- +- pinctrl_ndtr4_default: ndtr4_default { +- function = "NDTR4"; +- groups = "NDTR4"; +- }; +- +- pinctrl_nri1_default: nri1_default { +- function = "NRI1"; +- groups = "NRI1"; +- }; +- +- pinctrl_nri2_default: nri2_default { +- function = "NRI2"; +- groups = "NRI2"; +- }; +- +- pinctrl_nri3_default: nri3_default { +- function = "NRI3"; +- groups = "NRI3"; +- }; +- +- pinctrl_nri4_default: nri4_default { +- function = "NRI4"; +- groups = "NRI4"; +- }; +- +- pinctrl_nrts1_default: nrts1_default { +- function = "NRTS1"; +- groups = "NRTS1"; +- }; +- +- pinctrl_nrts2_default: nrts2_default { +- function = "NRTS2"; +- groups = "NRTS2"; +- }; +- +- pinctrl_nrts3_default: nrts3_default { +- function = "NRTS3"; +- groups = "NRTS3"; +- }; +- +- pinctrl_nrts4_default: nrts4_default { +- function = "NRTS4"; +- groups = "NRTS4"; +- }; +- +- pinctrl_oscclk_default: oscclk_default { +- function = "OSCCLK"; +- groups = "OSCCLK"; +- }; +- +- pinctrl_pewake_default: pewake_default { +- function = "PEWAKE"; +- groups = "PEWAKE"; +- }; +- +- pinctrl_pnor_default: pnor_default { +- function = "PNOR"; +- groups = "PNOR"; +- }; +- +- pinctrl_pwm0_default: pwm0_default { +- function = "PWM0"; +- groups = "PWM0"; +- }; +- +- pinctrl_pwm1_default: pwm1_default { +- function = "PWM1"; +- groups = "PWM1"; +- }; +- +- pinctrl_pwm2_default: pwm2_default { +- function = "PWM2"; +- groups = "PWM2"; +- }; +- +- pinctrl_pwm3_default: pwm3_default { +- function = "PWM3"; +- groups = "PWM3"; +- }; +- +- pinctrl_pwm4_default: pwm4_default { +- function = "PWM4"; +- groups = "PWM4"; +- }; +- +- pinctrl_pwm5_default: pwm5_default { +- function = "PWM5"; +- groups = "PWM5"; +- }; +- +- pinctrl_pwm6_default: pwm6_default { +- function = "PWM6"; +- groups = "PWM6"; +- }; +- +- pinctrl_pwm7_default: pwm7_default { +- function = "PWM7"; +- groups = "PWM7"; +- }; +- +- pinctrl_rgmii1_default: rgmii1_default { +- function = "RGMII1"; +- groups = "RGMII1"; +- }; +- +- pinctrl_rgmii2_default: rgmii2_default { +- function = "RGMII2"; +- groups = "RGMII2"; +- }; +- +- pinctrl_rmii1_default: rmii1_default { +- function = "RMII1"; +- groups = "RMII1"; +- }; +- +- pinctrl_rmii2_default: rmii2_default { +- function = "RMII2"; +- groups = "RMII2"; +- }; +- +- pinctrl_rxd1_default: rxd1_default { +- function = "RXD1"; +- groups = "RXD1"; +- }; +- +- pinctrl_rxd2_default: rxd2_default { +- function = "RXD2"; +- groups = "RXD2"; +- }; +- +- pinctrl_rxd3_default: rxd3_default { +- function = "RXD3"; +- groups = "RXD3"; +- }; +- +- pinctrl_rxd4_default: rxd4_default { +- function = "RXD4"; +- groups = "RXD4"; +- }; +- +- pinctrl_salt1_default: salt1_default { +- function = "SALT1"; +- groups = "SALT1"; +- }; +- +- pinctrl_salt10_default: salt10_default { +- function = "SALT10"; +- groups = "SALT10"; +- }; +- +- pinctrl_salt11_default: salt11_default { +- function = "SALT11"; +- groups = "SALT11"; +- }; +- +- pinctrl_salt12_default: salt12_default { +- function = "SALT12"; +- groups = "SALT12"; +- }; +- +- pinctrl_salt13_default: salt13_default { +- function = "SALT13"; +- groups = "SALT13"; +- }; +- +- pinctrl_salt14_default: salt14_default { +- function = "SALT14"; +- groups = "SALT14"; +- }; +- +- pinctrl_salt2_default: salt2_default { +- function = "SALT2"; +- groups = "SALT2"; +- }; +- +- pinctrl_salt3_default: salt3_default { +- function = "SALT3"; +- groups = "SALT3"; +- }; +- +- pinctrl_salt4_default: salt4_default { +- function = "SALT4"; +- groups = "SALT4"; +- }; +- +- pinctrl_salt5_default: salt5_default { +- function = "SALT5"; +- groups = "SALT5"; +- }; +- +- pinctrl_salt6_default: salt6_default { +- function = "SALT6"; +- groups = "SALT6"; +- }; +- +- pinctrl_salt7_default: salt7_default { +- function = "SALT7"; +- groups = "SALT7"; +- }; +- +- pinctrl_salt8_default: salt8_default { +- function = "SALT8"; +- groups = "SALT8"; +- }; +- +- pinctrl_salt9_default: salt9_default { +- function = "SALT9"; +- groups = "SALT9"; +- }; +- +- pinctrl_scl1_default: scl1_default { +- function = "SCL1"; +- groups = "SCL1"; +- }; +- +- pinctrl_scl2_default: scl2_default { +- function = "SCL2"; +- groups = "SCL2"; +- }; +- +- pinctrl_sd1_default: sd1_default { +- function = "SD1"; +- groups = "SD1"; +- }; +- +- pinctrl_sd2_default: sd2_default { +- function = "SD2"; +- groups = "SD2"; +- }; +- +- pinctrl_sda1_default: sda1_default { +- function = "SDA1"; +- groups = "SDA1"; +- }; +- +- pinctrl_sda2_default: sda2_default { +- function = "SDA2"; +- groups = "SDA2"; +- }; +- +- pinctrl_sgpm_default: sgpm_default { +- function = "SGPM"; +- groups = "SGPM"; +- }; +- +- pinctrl_sgps1_default: sgps1_default { +- function = "SGPS1"; +- groups = "SGPS1"; +- }; +- +- pinctrl_sgps2_default: sgps2_default { +- function = "SGPS2"; +- groups = "SGPS2"; +- }; +- +- pinctrl_sioonctrl_default: sioonctrl_default { +- function = "SIOONCTRL"; +- groups = "SIOONCTRL"; +- }; +- +- pinctrl_siopbi_default: siopbi_default { +- function = "SIOPBI"; +- groups = "SIOPBI"; +- }; +- +- pinctrl_siopbo_default: siopbo_default { +- function = "SIOPBO"; +- groups = "SIOPBO"; +- }; +- +- pinctrl_siopwreq_default: siopwreq_default { +- function = "SIOPWREQ"; +- groups = "SIOPWREQ"; +- }; +- +- pinctrl_siopwrgd_default: siopwrgd_default { +- function = "SIOPWRGD"; +- groups = "SIOPWRGD"; +- }; +- +- pinctrl_sios3_default: sios3_default { +- function = "SIOS3"; +- groups = "SIOS3"; +- }; +- +- pinctrl_sios5_default: sios5_default { +- function = "SIOS5"; +- groups = "SIOS5"; +- }; +- +- pinctrl_siosci_default: siosci_default { +- function = "SIOSCI"; +- groups = "SIOSCI"; +- }; +- +- pinctrl_spi1_default: spi1_default { +- function = "SPI1"; +- groups = "SPI1"; +- }; +- +- pinctrl_spi1cs1_default: spi1cs1_default { +- function = "SPI1CS1"; +- groups = "SPI1CS1"; +- }; +- +- pinctrl_spi1debug_default: spi1debug_default { +- function = "SPI1DEBUG"; +- groups = "SPI1DEBUG"; +- }; +- +- pinctrl_spi1passthru_default: spi1passthru_default { +- function = "SPI1PASSTHRU"; +- groups = "SPI1PASSTHRU"; +- }; +- +- pinctrl_spi2ck_default: spi2ck_default { +- function = "SPI2CK"; +- groups = "SPI2CK"; +- }; +- +- pinctrl_spi2cs0_default: spi2cs0_default { +- function = "SPI2CS0"; +- groups = "SPI2CS0"; +- }; +- +- pinctrl_spi2cs1_default: spi2cs1_default { +- function = "SPI2CS1"; +- groups = "SPI2CS1"; +- }; +- +- pinctrl_spi2miso_default: spi2miso_default { +- function = "SPI2MISO"; +- groups = "SPI2MISO"; +- }; +- +- pinctrl_spi2mosi_default: spi2mosi_default { +- function = "SPI2MOSI"; +- groups = "SPI2MOSI"; +- }; +- +- pinctrl_timer3_default: timer3_default { +- function = "TIMER3"; +- groups = "TIMER3"; +- }; +- +- pinctrl_timer4_default: timer4_default { +- function = "TIMER4"; +- groups = "TIMER4"; +- }; +- +- pinctrl_timer5_default: timer5_default { +- function = "TIMER5"; +- groups = "TIMER5"; +- }; +- +- pinctrl_timer6_default: timer6_default { +- function = "TIMER6"; +- groups = "TIMER6"; +- }; +- +- pinctrl_timer7_default: timer7_default { +- function = "TIMER7"; +- groups = "TIMER7"; +- }; +- +- pinctrl_timer8_default: timer8_default { +- function = "TIMER8"; +- groups = "TIMER8"; +- }; +- +- pinctrl_txd1_default: txd1_default { +- function = "TXD1"; +- groups = "TXD1"; +- }; +- +- pinctrl_txd2_default: txd2_default { +- function = "TXD2"; +- groups = "TXD2"; +- }; +- +- pinctrl_txd3_default: txd3_default { +- function = "TXD3"; +- groups = "TXD3"; +- }; +- +- pinctrl_txd4_default: txd4_default { +- function = "TXD4"; +- groups = "TXD4"; +- }; +- +- pinctrl_uart6_default: uart6_default { +- function = "UART6"; +- groups = "UART6"; +- }; +- +- pinctrl_usbcki_default: usbcki_default { +- function = "USBCKI"; +- groups = "USBCKI"; +- }; +- +- pinctrl_usb2ah_default: usb2ah_default { +- function = "USB2AH"; +- groups = "USB2AH"; +- }; +- +- pinctrl_usb2ad_default: usb2ad_default { +- function = "USB2AD"; +- groups = "USB2AD"; +- }; +- +- pinctrl_usb11bhid_default: usb11bhid_default { +- function = "USB11BHID"; +- groups = "USB11BHID"; +- }; +- +- pinctrl_usb2bh_default: usb2bh_default { +- function = "USB2BH"; +- groups = "USB2BH"; +- }; +- +- pinctrl_vgabiosrom_default: vgabiosrom_default { +- function = "VGABIOSROM"; +- groups = "VGABIOSROM"; +- }; +- +- pinctrl_vgahs_default: vgahs_default { +- function = "VGAHS"; +- groups = "VGAHS"; +- }; +- +- pinctrl_vgavs_default: vgavs_default { +- function = "VGAVS"; +- groups = "VGAVS"; +- }; +- +- pinctrl_vpi24_default: vpi24_default { +- function = "VPI24"; +- groups = "VPI24"; +- }; +- +- pinctrl_vpo_default: vpo_default { +- function = "VPO"; +- groups = "VPO"; +- }; +- +- pinctrl_wdtrst1_default: wdtrst1_default { +- function = "WDTRST1"; +- groups = "WDTRST1"; +- }; +- +- pinctrl_wdtrst2_default: wdtrst2_default { +- function = "WDTRST2"; +- groups = "WDTRST2"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-g6-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/aspeed-g6-pinctrl.dtsi +deleted file mode 100644 +index e4775bbceecc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-g6-pinctrl.dtsi ++++ /dev/null +@@ -1,1184 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-// Copyright 2019 IBM Corp. +- +-&pinctrl { +- pinctrl_adc0_default: adc0_default { +- function = "ADC0"; +- groups = "ADC0"; +- }; +- +- pinctrl_adc1_default: adc1_default { +- function = "ADC1"; +- groups = "ADC1"; +- }; +- +- pinctrl_adc10_default: adc10_default { +- function = "ADC10"; +- groups = "ADC10"; +- }; +- +- pinctrl_adc11_default: adc11_default { +- function = "ADC11"; +- groups = "ADC11"; +- }; +- +- pinctrl_adc12_default: adc12_default { +- function = "ADC12"; +- groups = "ADC12"; +- }; +- +- pinctrl_adc13_default: adc13_default { +- function = "ADC13"; +- groups = "ADC13"; +- }; +- +- pinctrl_adc14_default: adc14_default { +- function = "ADC14"; +- groups = "ADC14"; +- }; +- +- pinctrl_adc15_default: adc15_default { +- function = "ADC15"; +- groups = "ADC15"; +- }; +- +- pinctrl_adc2_default: adc2_default { +- function = "ADC2"; +- groups = "ADC2"; +- }; +- +- pinctrl_adc3_default: adc3_default { +- function = "ADC3"; +- groups = "ADC3"; +- }; +- +- pinctrl_adc4_default: adc4_default { +- function = "ADC4"; +- groups = "ADC4"; +- }; +- +- pinctrl_adc5_default: adc5_default { +- function = "ADC5"; +- groups = "ADC5"; +- }; +- +- pinctrl_adc6_default: adc6_default { +- function = "ADC6"; +- groups = "ADC6"; +- }; +- +- pinctrl_adc7_default: adc7_default { +- function = "ADC7"; +- groups = "ADC7"; +- }; +- +- pinctrl_adc8_default: adc8_default { +- function = "ADC8"; +- groups = "ADC8"; +- }; +- +- pinctrl_adc9_default: adc9_default { +- function = "ADC9"; +- groups = "ADC9"; +- }; +- +- pinctrl_bmcint_default: bmcint_default { +- function = "BMCINT"; +- groups = "BMCINT"; +- }; +- +- pinctrl_espi_default: espi_default { +- function = "ESPI"; +- groups = "ESPI"; +- }; +- +- pinctrl_espialt_default: espialt_default { +- function = "ESPIALT"; +- groups = "ESPIALT"; +- }; +- +- pinctrl_fsi1_default: fsi1_default { +- function = "FSI1"; +- groups = "FSI1"; +- }; +- +- pinctrl_fsi2_default: fsi2_default { +- function = "FSI2"; +- groups = "FSI2"; +- }; +- +- pinctrl_fwspiabr_default: fwspiabr_default { +- function = "FWSPIABR"; +- groups = "FWSPIABR"; +- }; +- +- pinctrl_fwspid_default: fwspid_default { +- function = "FWSPID"; +- groups = "FWSPID"; +- }; +- +- pinctrl_fwqspid_default: fwqspid_default { +- function = "FWSPID"; +- groups = "FWQSPID"; +- }; +- +- pinctrl_fwspiwp_default: fwspiwp_default { +- function = "FWSPIWP"; +- groups = "FWSPIWP"; +- }; +- +- pinctrl_gpit0_default: gpit0_default { +- function = "GPIT0"; +- groups = "GPIT0"; +- }; +- +- pinctrl_gpit1_default: gpit1_default { +- function = "GPIT1"; +- groups = "GPIT1"; +- }; +- +- pinctrl_gpit2_default: gpit2_default { +- function = "GPIT2"; +- groups = "GPIT2"; +- }; +- +- pinctrl_gpit3_default: gpit3_default { +- function = "GPIT3"; +- groups = "GPIT3"; +- }; +- +- pinctrl_gpit4_default: gpit4_default { +- function = "GPIT4"; +- groups = "GPIT4"; +- }; +- +- pinctrl_gpit5_default: gpit5_default { +- function = "GPIT5"; +- groups = "GPIT5"; +- }; +- +- pinctrl_gpit6_default: gpit6_default { +- function = "GPIT6"; +- groups = "GPIT6"; +- }; +- +- pinctrl_gpit7_default: gpit7_default { +- function = "GPIT7"; +- groups = "GPIT7"; +- }; +- +- pinctrl_gpiu0_default: gpiu0_default { +- function = "GPIU0"; +- groups = "GPIU0"; +- }; +- +- pinctrl_gpiu1_default: gpiu1_default { +- function = "GPIU1"; +- groups = "GPIU1"; +- }; +- +- pinctrl_gpiu2_default: gpiu2_default { +- function = "GPIU2"; +- groups = "GPIU2"; +- }; +- +- pinctrl_gpiu3_default: gpiu3_default { +- function = "GPIU3"; +- groups = "GPIU3"; +- }; +- +- pinctrl_gpiu4_default: gpiu4_default { +- function = "GPIU4"; +- groups = "GPIU4"; +- }; +- +- pinctrl_gpiu5_default: gpiu5_default { +- function = "GPIU5"; +- groups = "GPIU5"; +- }; +- +- pinctrl_gpiu6_default: gpiu6_default { +- function = "GPIU6"; +- groups = "GPIU6"; +- }; +- +- pinctrl_gpiu7_default: gpiu7_default { +- function = "GPIU7"; +- groups = "GPIU7"; +- }; +- +- pinctrl_hvi3c3_default: hvi3c3_default { +- function = "I3C3"; +- groups = "HVI3C3"; +- }; +- +- pinctrl_hvi3c4_default: hvi3c4_default { +- function = "I3C4"; +- groups = "HVI3C4"; +- }; +- +- pinctrl_i2c1_default: i2c1_default { +- function = "I2C1"; +- groups = "I2C1"; +- }; +- +- pinctrl_i2c10_default: i2c10_default { +- function = "I2C10"; +- groups = "I2C10"; +- }; +- +- pinctrl_i2c11_default: i2c11_default { +- function = "I2C11"; +- groups = "I2C11"; +- }; +- +- pinctrl_i2c12_default: i2c12_default { +- function = "I2C12"; +- groups = "I2C12"; +- }; +- +- pinctrl_i2c13_default: i2c13_default { +- function = "I2C13"; +- groups = "I2C13"; +- }; +- +- pinctrl_i2c14_default: i2c14_default { +- function = "I2C14"; +- groups = "I2C14"; +- }; +- +- pinctrl_i2c15_default: i2c15_default { +- function = "I2C15"; +- groups = "I2C15"; +- }; +- +- pinctrl_i2c16_default: i2c16_default { +- function = "I2C16"; +- groups = "I2C16"; +- }; +- +- pinctrl_i2c2_default: i2c2_default { +- function = "I2C2"; +- groups = "I2C2"; +- }; +- +- pinctrl_i2c3_default: i2c3_default { +- function = "I2C3"; +- groups = "I2C3"; +- }; +- +- pinctrl_i2c4_default: i2c4_default { +- function = "I2C4"; +- groups = "I2C4"; +- }; +- +- pinctrl_i2c5_default: i2c5_default { +- function = "I2C5"; +- groups = "I2C5"; +- }; +- +- pinctrl_i2c6_default: i2c6_default { +- function = "I2C6"; +- groups = "I2C6"; +- }; +- +- pinctrl_i2c7_default: i2c7_default { +- function = "I2C7"; +- groups = "I2C7"; +- }; +- +- pinctrl_i2c8_default: i2c8_default { +- function = "I2C8"; +- groups = "I2C8"; +- }; +- +- pinctrl_i2c9_default: i2c9_default { +- function = "I2C9"; +- groups = "I2C9"; +- }; +- +- pinctrl_i3c3_default: i3c3_default { +- function = "I3C3"; +- groups = "I3C3"; +- }; +- +- pinctrl_i3c4_default: i3c4_default { +- function = "I3C4"; +- groups = "I3C4"; +- }; +- +- pinctrl_i3c5_default: i3c5_default { +- function = "I3C5"; +- groups = "I3C5"; +- }; +- +- pinctrl_i3c6_default: i3c6_default { +- function = "I3C6"; +- groups = "I3C6"; +- }; +- +- pinctrl_jtagm_default: jtagm_default { +- function = "JTAGM"; +- groups = "JTAGM"; +- }; +- +- pinctrl_lhpd_default: lhpd_default { +- function = "LHPD"; +- groups = "LHPD"; +- }; +- +- pinctrl_lhsirq_default: lhsirq_default { +- function = "LHSIRQ"; +- groups = "LHSIRQ"; +- }; +- +- pinctrl_lpc_default: lpc_default { +- function = "LPC"; +- groups = "LPC"; +- }; +- +- pinctrl_lpchc_default: lpchc_default { +- function = "LPCHC"; +- groups = "LPCHC"; +- }; +- +- pinctrl_lpcpd_default: lpcpd_default { +- function = "LPCPD"; +- groups = "LPCPD"; +- }; +- +- pinctrl_lpcpme_default: lpcpme_default { +- function = "LPCPME"; +- groups = "LPCPME"; +- }; +- +- pinctrl_lpcsmi_default: lpcsmi_default { +- function = "LPCSMI"; +- groups = "LPCSMI"; +- }; +- +- pinctrl_lsirq_default: lsirq_default { +- function = "LSIRQ"; +- groups = "LSIRQ"; +- }; +- +- pinctrl_maclink1_default: maclink1_default { +- function = "MACLINK1"; +- groups = "MACLINK1"; +- }; +- +- pinctrl_maclink2_default: maclink2_default { +- function = "MACLINK2"; +- groups = "MACLINK2"; +- }; +- +- pinctrl_maclink3_default: maclink3_default { +- function = "MACLINK3"; +- groups = "MACLINK3"; +- }; +- +- pinctrl_maclink4_default: maclink4_default { +- function = "MACLINK4"; +- groups = "MACLINK4"; +- }; +- +- pinctrl_mdio1_default: mdio1_default { +- function = "MDIO1"; +- groups = "MDIO1"; +- }; +- +- pinctrl_mdio2_default: mdio2_default { +- function = "MDIO2"; +- groups = "MDIO2"; +- }; +- +- pinctrl_mdio3_default: mdio3_default { +- function = "MDIO3"; +- groups = "MDIO3"; +- }; +- +- pinctrl_mdio4_default: mdio4_default { +- function = "MDIO4"; +- groups = "MDIO4"; +- }; +- +- pinctrl_ncts1_default: ncts1_default { +- function = "NCTS1"; +- groups = "NCTS1"; +- }; +- +- pinctrl_ncts2_default: ncts2_default { +- function = "NCTS2"; +- groups = "NCTS2"; +- }; +- +- pinctrl_ncts3_default: ncts3_default { +- function = "NCTS3"; +- groups = "NCTS3"; +- }; +- +- pinctrl_ncts4_default: ncts4_default { +- function = "NCTS4"; +- groups = "NCTS4"; +- }; +- +- pinctrl_ndcd1_default: ndcd1_default { +- function = "NDCD1"; +- groups = "NDCD1"; +- }; +- +- pinctrl_ndcd2_default: ndcd2_default { +- function = "NDCD2"; +- groups = "NDCD2"; +- }; +- +- pinctrl_ndcd3_default: ndcd3_default { +- function = "NDCD3"; +- groups = "NDCD3"; +- }; +- +- pinctrl_ndcd4_default: ndcd4_default { +- function = "NDCD4"; +- groups = "NDCD4"; +- }; +- +- pinctrl_ndsr1_default: ndsr1_default { +- function = "NDSR1"; +- groups = "NDSR1"; +- }; +- +- pinctrl_ndsr2_default: ndsr2_default { +- function = "NDSR2"; +- groups = "NDSR2"; +- }; +- +- pinctrl_ndsr3_default: ndsr3_default { +- function = "NDSR3"; +- groups = "NDSR3"; +- }; +- +- pinctrl_ndsr4_default: ndsr4_default { +- function = "NDSR4"; +- groups = "NDSR4"; +- }; +- +- pinctrl_ndtr1_default: ndtr1_default { +- function = "NDTR1"; +- groups = "NDTR1"; +- }; +- +- pinctrl_ndtr2_default: ndtr2_default { +- function = "NDTR2"; +- groups = "NDTR2"; +- }; +- +- pinctrl_ndtr3_default: ndtr3_default { +- function = "NDTR3"; +- groups = "NDTR3"; +- }; +- +- pinctrl_ndtr4_default: ndtr4_default { +- function = "NDTR4"; +- groups = "NDTR4"; +- }; +- +- pinctrl_nri1_default: nri1_default { +- function = "NRI1"; +- groups = "NRI1"; +- }; +- +- pinctrl_nri2_default: nri2_default { +- function = "NRI2"; +- groups = "NRI2"; +- }; +- +- pinctrl_nri3_default: nri3_default { +- function = "NRI3"; +- groups = "NRI3"; +- }; +- +- pinctrl_nri4_default: nri4_default { +- function = "NRI4"; +- groups = "NRI4"; +- }; +- +- pinctrl_nrts1_default: nrts1_default { +- function = "NRTS1"; +- groups = "NRTS1"; +- }; +- +- pinctrl_nrts2_default: nrts2_default { +- function = "NRTS2"; +- groups = "NRTS2"; +- }; +- +- pinctrl_nrts3_default: nrts3_default { +- function = "NRTS3"; +- groups = "NRTS3"; +- }; +- +- pinctrl_nrts4_default: nrts4_default { +- function = "NRTS4"; +- groups = "NRTS4"; +- }; +- +- pinctrl_oscclk_default: oscclk_default { +- function = "OSCCLK"; +- groups = "OSCCLK"; +- }; +- +- pinctrl_pewake_default: pewake_default { +- function = "PEWAKE"; +- groups = "PEWAKE"; +- }; +- +- pinctrl_pwm0_default: pwm0_default { +- function = "PWM0"; +- groups = "PWM0"; +- }; +- +- pinctrl_pwm1_default: pwm1_default { +- function = "PWM1"; +- groups = "PWM1"; +- }; +- +- pinctrl_pwm10g0_default: pwm10g0_default { +- function = "PWM10"; +- groups = "PWM10G0"; +- }; +- +- pinctrl_pwm10g1_default: pwm10g1_default { +- function = "PWM10"; +- groups = "PWM10G1"; +- }; +- +- pinctrl_pwm11g0_default: pwm11g0_default { +- function = "PWM11"; +- groups = "PWM11G0"; +- }; +- +- pinctrl_pwm11g1_default: pwm11g1_default { +- function = "PWM11"; +- groups = "PWM11G1"; +- }; +- +- pinctrl_pwm12g0_default: pwm12g0_default { +- function = "PWM12"; +- groups = "PWM12G0"; +- }; +- +- pinctrl_pwm12g1_default: pwm12g1_default { +- function = "PWM12"; +- groups = "PWM12G1"; +- }; +- +- pinctrl_pwm13g0_default: pwm13g0_default { +- function = "PWM13"; +- groups = "PWM13G0"; +- }; +- +- pinctrl_pwm13g1_default: pwm13g1_default { +- function = "PWM13"; +- groups = "PWM13G1"; +- }; +- +- pinctrl_pwm14g0_default: pwm14g0_default { +- function = "PWM14"; +- groups = "PWM14G0"; +- }; +- +- pinctrl_pwm14g1_default: pwm14g1_default { +- function = "PWM14"; +- groups = "PWM14G1"; +- }; +- +- pinctrl_pwm15g0_default: pwm15g0_default { +- function = "PWM15"; +- groups = "PWM15G0"; +- }; +- +- pinctrl_pwm15g1_default: pwm15g1_default { +- function = "PWM15"; +- groups = "PWM15G1"; +- }; +- +- pinctrl_pwm2_default: pwm2_default { +- function = "PWM2"; +- groups = "PWM2"; +- }; +- +- pinctrl_pwm3_default: pwm3_default { +- function = "PWM3"; +- groups = "PWM3"; +- }; +- +- pinctrl_pwm4_default: pwm4_default { +- function = "PWM4"; +- groups = "PWM4"; +- }; +- +- pinctrl_pwm5_default: pwm5_default { +- function = "PWM5"; +- groups = "PWM5"; +- }; +- +- pinctrl_pwm6_default: pwm6_default { +- function = "PWM6"; +- groups = "PWM6"; +- }; +- +- pinctrl_pwm7_default: pwm7_default { +- function = "PWM7"; +- groups = "PWM7"; +- }; +- +- pinctrl_pwm8g0_default: pwm8g0_default { +- function = "PWM8"; +- groups = "PWM8G0"; +- }; +- +- pinctrl_pwm8g1_default: pwm8g1_default { +- function = "PWM8"; +- groups = "PWM8G1"; +- }; +- +- pinctrl_pwm9g0_default: pwm9g0_default { +- function = "PWM9"; +- groups = "PWM9G0"; +- }; +- +- pinctrl_pwm9g1_default: pwm9g1_default { +- function = "PWM9"; +- groups = "PWM9G1"; +- }; +- +- pinctrl_qspi1_default: qspi1_default { +- function = "QSPI1"; +- groups = "QSPI1"; +- }; +- +- pinctrl_qspi2_default: qspi2_default { +- function = "QSPI2"; +- groups = "QSPI2"; +- }; +- +- pinctrl_rgmii1_default: rgmii1_default { +- function = "RGMII1"; +- groups = "RGMII1"; +- }; +- +- pinctrl_rgmii2_default: rgmii2_default { +- function = "RGMII2"; +- groups = "RGMII2"; +- }; +- +- pinctrl_rgmii3_default: rgmii3_default { +- function = "RGMII3"; +- groups = "RGMII3"; +- }; +- +- pinctrl_rgmii4_default: rgmii4_default { +- function = "RGMII4"; +- groups = "RGMII4"; +- }; +- +- pinctrl_rmii1_default: rmii1_default { +- function = "RMII1"; +- groups = "RMII1"; +- }; +- +- pinctrl_rmii2_default: rmii2_default { +- function = "RMII2"; +- groups = "RMII2"; +- }; +- +- pinctrl_rmii3_default: rmii3_default { +- function = "RMII3"; +- groups = "RMII3"; +- }; +- +- pinctrl_rmii4_default: rmii4_default { +- function = "RMII4"; +- groups = "RMII4"; +- }; +- +- pinctrl_rxd1_default: rxd1_default { +- function = "RXD1"; +- groups = "RXD1"; +- }; +- +- pinctrl_rxd2_default: rxd2_default { +- function = "RXD2"; +- groups = "RXD2"; +- }; +- +- pinctrl_rxd3_default: rxd3_default { +- function = "RXD3"; +- groups = "RXD3"; +- }; +- +- pinctrl_rxd4_default: rxd4_default { +- function = "RXD4"; +- groups = "RXD4"; +- }; +- +- pinctrl_salt1_default: salt1_default { +- function = "SALT1"; +- groups = "SALT1"; +- }; +- +- pinctrl_salt10g0_default: salt10g0_default { +- function = "SALT10"; +- groups = "SALT10G0"; +- }; +- +- pinctrl_salt10g1_default: salt10g1_default { +- function = "SALT10"; +- groups = "SALT10G1"; +- }; +- +- pinctrl_salt11g0_default: salt11g0_default { +- function = "SALT11"; +- groups = "SALT11G0"; +- }; +- +- pinctrl_salt11g1_default: salt11g1_default { +- function = "SALT11"; +- groups = "SALT11G1"; +- }; +- +- pinctrl_salt12g0_default: salt12g0_default { +- function = "SALT12"; +- groups = "SALT12G0"; +- }; +- +- pinctrl_salt12g1_default: salt12g1_default { +- function = "SALT12"; +- groups = "SALT12G1"; +- }; +- +- pinctrl_salt13g0_default: salt13g0_default { +- function = "SALT13"; +- groups = "SALT13G0"; +- }; +- +- pinctrl_salt13g1_default: salt13g1_default { +- function = "SALT13"; +- groups = "SALT13G1"; +- }; +- +- pinctrl_salt14g0_default: salt14g0_default { +- function = "SALT14"; +- groups = "SALT14G0"; +- }; +- +- pinctrl_salt14g1_default: salt14g1_default { +- function = "SALT14"; +- groups = "SALT14G1"; +- }; +- +- pinctrl_salt15g0_default: salt15g0_default { +- function = "SALT15"; +- groups = "SALT15G0"; +- }; +- +- pinctrl_salt15g1_default: salt15g1_default { +- function = "SALT15"; +- groups = "SALT15G1"; +- }; +- +- pinctrl_salt16g0_default: salt16g0_default { +- function = "SALT16"; +- groups = "SALT16G0"; +- }; +- +- pinctrl_salt16g1_default: salt16g1_default { +- function = "SALT16"; +- groups = "SALT16G1"; +- }; +- +- pinctrl_salt2_default: salt2_default { +- function = "SALT2"; +- groups = "SALT2"; +- }; +- +- pinctrl_salt3_default: salt3_default { +- function = "SALT3"; +- groups = "SALT3"; +- }; +- +- pinctrl_salt4_default: salt4_default { +- function = "SALT4"; +- groups = "SALT4"; +- }; +- +- pinctrl_salt5_default: salt5_default { +- function = "SALT5"; +- groups = "SALT5"; +- }; +- +- pinctrl_salt6_default: salt6_default { +- function = "SALT6"; +- groups = "SALT6"; +- }; +- +- pinctrl_salt7_default: salt7_default { +- function = "SALT7"; +- groups = "SALT7"; +- }; +- +- pinctrl_salt8_default: salt8_default { +- function = "SALT8"; +- groups = "SALT8"; +- }; +- +- pinctrl_salt9g0_default: salt9g0_default { +- function = "SALT9"; +- groups = "SALT9G0"; +- }; +- +- pinctrl_salt9g1_default: salt9g1_default { +- function = "SALT9"; +- groups = "SALT9G1"; +- }; +- +- pinctrl_sd1_default: sd1_default { +- function = "SD1"; +- groups = "SD1"; +- }; +- +- pinctrl_sd2_default: sd2_default { +- function = "SD2"; +- groups = "SD2"; +- }; +- +- pinctrl_emmc_default: emmc_default { +- function = "EMMC"; +- groups = "EMMCG4"; +- }; +- +- pinctrl_sgpm1_default: sgpm1_default { +- function = "SGPM1"; +- groups = "SGPM1"; +- }; +- +- pinctrl_sgpm2_default: sgpm2_default { +- function = "SGPM2"; +- groups = "SGPM2"; +- }; +- +- pinctrl_sgps1_default: sgps1_default { +- function = "SGPS1"; +- groups = "SGPS1"; +- }; +- +- pinctrl_sgps2_default: sgps2_default { +- function = "SGPS2"; +- groups = "SGPS2"; +- }; +- +- pinctrl_sioonctrl_default: sioonctrl_default { +- function = "SIOONCTRL"; +- groups = "SIOONCTRL"; +- }; +- +- pinctrl_siopbi_default: siopbi_default { +- function = "SIOPBI"; +- groups = "SIOPBI"; +- }; +- +- pinctrl_siopbo_default: siopbo_default { +- function = "SIOPBO"; +- groups = "SIOPBO"; +- }; +- +- pinctrl_siopwreq_default: siopwreq_default { +- function = "SIOPWREQ"; +- groups = "SIOPWREQ"; +- }; +- +- pinctrl_siopwrgd_default: siopwrgd_default { +- function = "SIOPWRGD"; +- groups = "SIOPWRGD"; +- }; +- +- pinctrl_sios3_default: sios3_default { +- function = "SIOS3"; +- groups = "SIOS3"; +- }; +- +- pinctrl_sios5_default: sios5_default { +- function = "SIOS5"; +- groups = "SIOS5"; +- }; +- +- pinctrl_siosci_default: siosci_default { +- function = "SIOSCI"; +- groups = "SIOSCI"; +- }; +- +- pinctrl_spi1_default: spi1_default { +- function = "SPI1"; +- groups = "SPI1"; +- }; +- +- pinctrl_spi1abr_default: spi1abr_default { +- function = "SPI1ABR"; +- groups = "SPI1ABR"; +- }; +- +- pinctrl_spi1cs1_default: spi1cs1_default { +- function = "SPI1CS1"; +- groups = "SPI1CS1"; +- }; +- +- pinctrl_spi1wp_default: spi1wp_default { +- function = "SPI1WP"; +- groups = "SPI1WP"; +- }; +- +- pinctrl_spi2_default: spi2_default { +- function = "SPI2"; +- groups = "SPI2"; +- }; +- +- pinctrl_spi2cs1_default: spi2cs1_default { +- function = "SPI2CS1"; +- groups = "SPI2CS1"; +- }; +- +- pinctrl_spi2cs2_default: spi2cs2_default { +- function = "SPI2CS2"; +- groups = "SPI2CS2"; +- }; +- +- pinctrl_tach0_default: tach0_default { +- function = "TACH0"; +- groups = "TACH0"; +- }; +- +- pinctrl_tach1_default: tach1_default { +- function = "TACH1"; +- groups = "TACH1"; +- }; +- +- pinctrl_tach10_default: tach10_default { +- function = "TACH10"; +- groups = "TACH10"; +- }; +- +- pinctrl_tach11_default: tach11_default { +- function = "TACH11"; +- groups = "TACH11"; +- }; +- +- pinctrl_tach12_default: tach12_default { +- function = "TACH12"; +- groups = "TACH12"; +- }; +- +- pinctrl_tach13_default: tach13_default { +- function = "TACH13"; +- groups = "TACH13"; +- }; +- +- pinctrl_tach14_default: tach14_default { +- function = "TACH14"; +- groups = "TACH14"; +- }; +- +- pinctrl_tach15_default: tach15_default { +- function = "TACH15"; +- groups = "TACH15"; +- }; +- +- pinctrl_tach2_default: tach2_default { +- function = "TACH2"; +- groups = "TACH2"; +- }; +- +- pinctrl_tach3_default: tach3_default { +- function = "TACH3"; +- groups = "TACH3"; +- }; +- +- pinctrl_tach4_default: tach4_default { +- function = "TACH4"; +- groups = "TACH4"; +- }; +- +- pinctrl_tach5_default: tach5_default { +- function = "TACH5"; +- groups = "TACH5"; +- }; +- +- pinctrl_tach6_default: tach6_default { +- function = "TACH6"; +- groups = "TACH6"; +- }; +- +- pinctrl_tach7_default: tach7_default { +- function = "TACH7"; +- groups = "TACH7"; +- }; +- +- pinctrl_tach8_default: tach8_default { +- function = "TACH8"; +- groups = "TACH8"; +- }; +- +- pinctrl_tach9_default: tach9_default { +- function = "TACH9"; +- groups = "TACH9"; +- }; +- +- pinctrl_thru0_default: thru0_default { +- function = "THRU0"; +- groups = "THRU0"; +- }; +- +- pinctrl_thru1_default: thru1_default { +- function = "THRU1"; +- groups = "THRU1"; +- }; +- +- pinctrl_thru2_default: thru2_default { +- function = "THRU2"; +- groups = "THRU2"; +- }; +- +- pinctrl_thru3_default: thru3_default { +- function = "THRU3"; +- groups = "THRU3"; +- }; +- +- pinctrl_txd1_default: txd1_default { +- function = "TXD1"; +- groups = "TXD1"; +- }; +- +- pinctrl_txd2_default: txd2_default { +- function = "TXD2"; +- groups = "TXD2"; +- }; +- +- pinctrl_txd3_default: txd3_default { +- function = "TXD3"; +- groups = "TXD3"; +- }; +- +- pinctrl_txd4_default: txd4_default { +- function = "TXD4"; +- groups = "TXD4"; +- }; +- +- pinctrl_uart10_default: uart10_default { +- function = "UART10"; +- groups = "UART10"; +- }; +- +- pinctrl_uart11_default: uart11_default { +- function = "UART11"; +- groups = "UART11"; +- }; +- +- pinctrl_uart12g0_default: uart12g0_default { +- function = "UART12"; +- groups = "UART12G0"; +- }; +- +- pinctrl_uart12g1_default: uart12g1_default { +- function = "UART12"; +- groups = "UART12G1"; +- }; +- +- pinctrl_uart13g0_default: uart13g0_default { +- function = "UART13"; +- groups = "UART13G0"; +- }; +- +- pinctrl_uart13g1_default: uart13g1_default { +- function = "UART13"; +- groups = "UART13G1"; +- }; +- +- pinctrl_uart6_default: uart6_default { +- function = "UART6"; +- groups = "UART6"; +- }; +- +- pinctrl_uart7_default: uart7_default { +- function = "UART7"; +- groups = "UART7"; +- }; +- +- pinctrl_uart8_default: uart8_default { +- function = "UART8"; +- groups = "UART8"; +- }; +- +- pinctrl_uart9_default: uart9_default { +- function = "UART9"; +- groups = "UART9"; +- }; +- +- pinctrl_usb2ah_default: usb2ah_default { +- function = "USB2AH"; +- groups = "USBA"; +- }; +- +- pinctrl_usb2ad_default: usb2ad_default { +- function = "USB2AD"; +- groups = "USBA"; +- }; +- +- pinctrl_usb2bh_default: usb2bh_default { +- function = "USB2BH"; +- groups = "USBB"; +- }; +- +- pinctrl_usb2bd_default: usb2bd_default { +- function = "USB2BD"; +- groups = "USBB"; +- }; +- +- pinctrl_usb11bhid_default: usb11bhid_default { +- function = "USB11BHID"; +- groups = "USBB"; +- }; +- +- pinctrl_vb_default: vb_default { +- function = "VB"; +- groups = "VB"; +- }; +- +- pinctrl_vgahs_default: vgahs_default { +- function = "VGAHS"; +- groups = "VGAHS"; +- }; +- +- pinctrl_vgavs_default: vgavs_default { +- function = "VGAVS"; +- groups = "VGAVS"; +- }; +- +- pinctrl_wdtrst1_default: wdtrst1_default { +- function = "WDTRST1"; +- groups = "WDTRST1"; +- }; +- +- pinctrl_wdtrst2_default: wdtrst2_default { +- function = "WDTRST2"; +- groups = "WDTRST2"; +- }; +- +- pinctrl_wdtrst3_default: wdtrst3_default { +- function = "WDTRST3"; +- groups = "WDTRST3"; +- }; +- +- pinctrl_wdtrst4_default: wdtrst4_default { +- function = "WDTRST4"; +- groups = "WDTRST4"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/aspeed-g6.dtsi b/scripts/dtc/include-prefixes/arm/aspeed-g6.dtsi +deleted file mode 100644 +index 1b47be1704f8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/aspeed-g6.dtsi ++++ /dev/null +@@ -1,944 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-// Copyright 2019 IBM Corp. +- +-#include +-#include +-#include +- +-/ { +- model = "Aspeed BMC"; +- compatible = "aspeed,ast2600"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&gic>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c7; +- i2c8 = &i2c8; +- i2c9 = &i2c9; +- i2c10 = &i2c10; +- i2c11 = &i2c11; +- i2c12 = &i2c12; +- i2c13 = &i2c13; +- i2c14 = &i2c14; +- i2c15 = &i2c15; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- serial4 = &uart5; +- serial5 = &vuart1; +- serial6 = &vuart2; +- }; +- +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "aspeed,ast2600-smp"; +- +- cpu@f00 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <0xf00>; +- }; +- +- cpu@f01 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <0xf01>; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- clocks = <&syscon ASPEED_CLK_HPLL>; +- arm,cpu-registers-not-fw-configured; +- always-on; +- }; +- +- edac: sdram@1e6e0000 { +- compatible = "aspeed,ast2600-sdram-edac", "syscon"; +- reg = <0x1e6e0000 0x174>; +- interrupts = ; +- }; +- +- ahb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- ranges; +- +- gic: interrupt-controller@40461000 { +- compatible = "arm,cortex-a7-gic"; +- interrupts = ; +- #interrupt-cells = <3>; +- interrupt-controller; +- interrupt-parent = <&gic>; +- reg = <0x40461000 0x1000>, +- <0x40462000 0x1000>, +- <0x40464000 0x2000>, +- <0x40466000 0x2000>; +- }; +- +- fmc: spi@1e620000 { +- reg = < 0x1e620000 0xc4 +- 0x20000000 0x10000000 >; +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "aspeed,ast2600-fmc"; +- clocks = <&syscon ASPEED_CLK_AHB>; +- status = "disabled"; +- interrupts = ; +- flash@0 { +- reg = < 0 >; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- status = "disabled"; +- }; +- flash@1 { +- reg = < 1 >; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- status = "disabled"; +- }; +- flash@2 { +- reg = < 2 >; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- status = "disabled"; +- }; +- }; +- +- spi1: spi@1e630000 { +- reg = < 0x1e630000 0xc4 +- 0x30000000 0x10000000 >; +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "aspeed,ast2600-spi"; +- clocks = <&syscon ASPEED_CLK_AHB>; +- status = "disabled"; +- flash@0 { +- reg = < 0 >; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- status = "disabled"; +- }; +- flash@1 { +- reg = < 1 >; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- status = "disabled"; +- }; +- }; +- +- spi2: spi@1e631000 { +- reg = < 0x1e631000 0xc4 +- 0x50000000 0x10000000 >; +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "aspeed,ast2600-spi"; +- clocks = <&syscon ASPEED_CLK_AHB>; +- status = "disabled"; +- flash@0 { +- reg = < 0 >; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- status = "disabled"; +- }; +- flash@1 { +- reg = < 1 >; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- status = "disabled"; +- }; +- flash@2 { +- reg = < 2 >; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- status = "disabled"; +- }; +- }; +- +- mdio0: mdio@1e650000 { +- compatible = "aspeed,ast2600-mdio"; +- reg = <0x1e650000 0x8>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mdio1_default>; +- }; +- +- mdio1: mdio@1e650008 { +- compatible = "aspeed,ast2600-mdio"; +- reg = <0x1e650008 0x8>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mdio2_default>; +- }; +- +- mdio2: mdio@1e650010 { +- compatible = "aspeed,ast2600-mdio"; +- reg = <0x1e650010 0x8>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mdio3_default>; +- }; +- +- mdio3: mdio@1e650018 { +- compatible = "aspeed,ast2600-mdio"; +- reg = <0x1e650018 0x8>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mdio4_default>; +- }; +- +- mac0: ftgmac@1e660000 { +- compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; +- reg = <0x1e660000 0x180>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; +- status = "disabled"; +- }; +- +- mac1: ftgmac@1e680000 { +- compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; +- reg = <0x1e680000 0x180>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; +- status = "disabled"; +- }; +- +- mac2: ftgmac@1e670000 { +- compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; +- reg = <0x1e670000 0x180>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>; +- status = "disabled"; +- }; +- +- mac3: ftgmac@1e690000 { +- compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; +- reg = <0x1e690000 0x180>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>; +- status = "disabled"; +- }; +- +- ehci0: usb@1e6a1000 { +- compatible = "aspeed,ast2600-ehci", "generic-ehci"; +- reg = <0x1e6a1000 0x100>; +- interrupts = ; +- clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb2ah_default>; +- status = "disabled"; +- }; +- +- ehci1: usb@1e6a3000 { +- compatible = "aspeed,ast2600-ehci", "generic-ehci"; +- reg = <0x1e6a3000 0x100>; +- interrupts = ; +- clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb2bh_default>; +- status = "disabled"; +- }; +- +- uhci: usb@1e6b0000 { +- compatible = "aspeed,ast2600-uhci", "generic-uhci"; +- reg = <0x1e6b0000 0x100>; +- interrupts = ; +- #ports = <2>; +- clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; +- status = "disabled"; +- /* +- * No default pinmux, it will follow EHCI, use an +- * explicit pinmux override if EHCI is not enabled. +- */ +- }; +- +- vhub: usb-vhub@1e6a0000 { +- compatible = "aspeed,ast2600-usb-vhub"; +- reg = <0x1e6a0000 0x350>; +- interrupts = ; +- clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; +- aspeed,vhub-downstream-ports = <7>; +- aspeed,vhub-generic-endpoints = <21>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb2ad_default>; +- status = "disabled"; +- }; +- +- apb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- syscon: syscon@1e6e2000 { +- compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd"; +- reg = <0x1e6e2000 0x1000>; +- ranges = <0 0x1e6e2000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- +- pinctrl: pinctrl { +- compatible = "aspeed,ast2600-pinctrl"; +- }; +- +- silicon-id@14 { +- compatible = "aspeed,ast2600-silicon-id", "aspeed,silicon-id"; +- reg = <0x14 0x4 0x5b0 0x8>; +- }; +- +- smp-memram@180 { +- compatible = "aspeed,ast2600-smpmem"; +- reg = <0x180 0x40>; +- }; +- +- scu_ic0: interrupt-controller@560 { +- #interrupt-cells = <1>; +- compatible = "aspeed,ast2600-scu-ic0"; +- reg = <0x560 0x4>; +- interrupts = ; +- interrupt-controller; +- }; +- +- scu_ic1: interrupt-controller@570 { +- #interrupt-cells = <1>; +- compatible = "aspeed,ast2600-scu-ic1"; +- reg = <0x570 0x4>; +- interrupts = ; +- interrupt-controller; +- }; +- }; +- +- rng: hwrng@1e6e2524 { +- compatible = "timeriomem_rng"; +- reg = <0x1e6e2524 0x4>; +- period = <1>; +- quality = <100>; +- }; +- +- xdma: xdma@1e6e7000 { +- compatible = "aspeed,ast2600-xdma"; +- reg = <0x1e6e7000 0x100>; +- clocks = <&syscon ASPEED_CLK_GATE_BCLK>; +- resets = <&syscon ASPEED_RESET_DEV_XDMA>, <&syscon ASPEED_RESET_RC_XDMA>; +- reset-names = "device", "root-complex"; +- interrupts-extended = <&gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, +- <&scu_ic0 ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI>; +- aspeed,pcie-device = "bmc"; +- aspeed,scu = <&syscon>; +- status = "disabled"; +- }; +- +- gpio0: gpio@1e780000 { +- #gpio-cells = <2>; +- gpio-controller; +- compatible = "aspeed,ast2600-gpio"; +- reg = <0x1e780000 0x400>; +- interrupts = ; +- gpio-ranges = <&pinctrl 0 0 208>; +- ngpios = <208>; +- clocks = <&syscon ASPEED_CLK_APB2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- sgpiom0: sgpiom@1e780500 { +- #gpio-cells = <2>; +- gpio-controller; +- compatible = "aspeed,ast2600-sgpiom"; +- reg = <0x1e780500 0x100>; +- interrupts = ; +- clocks = <&syscon ASPEED_CLK_APB2>; +- interrupt-controller; +- bus-frequency = <12000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sgpm1_default>; +- status = "disabled"; +- }; +- +- sgpiom1: sgpiom@1e780600 { +- #gpio-cells = <2>; +- gpio-controller; +- compatible = "aspeed,ast2600-sgpiom"; +- reg = <0x1e780600 0x100>; +- interrupts = ; +- clocks = <&syscon ASPEED_CLK_APB2>; +- interrupt-controller; +- bus-frequency = <12000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sgpm2_default>; +- status = "disabled"; +- }; +- +- gpio1: gpio@1e780800 { +- #gpio-cells = <2>; +- gpio-controller; +- compatible = "aspeed,ast2600-gpio"; +- reg = <0x1e780800 0x800>; +- interrupts = ; +- gpio-ranges = <&pinctrl 0 208 36>; +- ngpios = <36>; +- clocks = <&syscon ASPEED_CLK_APB1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- rtc: rtc@1e781000 { +- compatible = "aspeed,ast2600-rtc"; +- reg = <0x1e781000 0x18>; +- interrupts = ; +- status = "disabled"; +- }; +- +- timer: timer@1e782000 { +- compatible = "aspeed,ast2600-timer"; +- reg = <0x1e782000 0x90>; +- interrupts-extended = <&gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&syscon ASPEED_CLK_APB1>; +- clock-names = "PCLK"; +- status = "disabled"; +- }; +- +- uart1: serial@1e783000 { +- compatible = "ns16550a"; +- reg = <0x1e783000 0x20>; +- reg-shift = <2>; +- reg-io-width = <4>; +- interrupts = ; +- clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; +- resets = <&lpc_reset 4>; +- no-loopback-test; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default>; +- status = "disabled"; +- }; +- +- uart5: serial@1e784000 { +- compatible = "ns16550a"; +- reg = <0x1e784000 0x1000>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; +- no-loopback-test; +- }; +- +- wdt1: watchdog@1e785000 { +- compatible = "aspeed,ast2600-wdt"; +- reg = <0x1e785000 0x40>; +- }; +- +- wdt2: watchdog@1e785040 { +- compatible = "aspeed,ast2600-wdt"; +- reg = <0x1e785040 0x40>; +- status = "disabled"; +- }; +- +- wdt3: watchdog@1e785080 { +- compatible = "aspeed,ast2600-wdt"; +- reg = <0x1e785080 0x40>; +- status = "disabled"; +- }; +- +- wdt4: watchdog@1e7850c0 { +- compatible = "aspeed,ast2600-wdt"; +- reg = <0x1e7850C0 0x40>; +- status = "disabled"; +- }; +- +- lpc: lpc@1e789000 { +- compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"; +- reg = <0x1e789000 0x1000>; +- reg-io-width = <4>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1e789000 0x1000>; +- +- kcs1: kcs@24 { +- compatible = "aspeed,ast2500-kcs-bmc-v2"; +- reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; +- interrupts = ; +- kcs_chan = <1>; +- status = "disabled"; +- }; +- +- kcs2: kcs@28 { +- compatible = "aspeed,ast2500-kcs-bmc-v2"; +- reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; +- interrupts = ; +- status = "disabled"; +- }; +- +- kcs3: kcs@2c { +- compatible = "aspeed,ast2500-kcs-bmc-v2"; +- reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; +- interrupts = ; +- status = "disabled"; +- }; +- +- kcs4: kcs@114 { +- compatible = "aspeed,ast2500-kcs-bmc-v2"; +- reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>; +- interrupts = ; +- status = "disabled"; +- }; +- +- lpc_ctrl: lpc-ctrl@80 { +- compatible = "aspeed,ast2600-lpc-ctrl"; +- reg = <0x80 0x80>; +- clocks = <&syscon ASPEED_CLK_GATE_LCLK>; +- status = "disabled"; +- }; +- +- lpc_snoop: lpc-snoop@80 { +- compatible = "aspeed,ast2600-lpc-snoop"; +- reg = <0x80 0x80>; +- interrupts = ; +- clocks = <&syscon ASPEED_CLK_GATE_LCLK>; +- status = "disabled"; +- }; +- +- lhc: lhc@a0 { +- compatible = "aspeed,ast2600-lhc"; +- reg = <0xa0 0x24 0xc8 0x8>; +- }; +- +- lpc_reset: reset-controller@98 { +- compatible = "aspeed,ast2600-lpc-reset"; +- reg = <0x98 0x4>; +- #reset-cells = <1>; +- }; +- +- ibt: ibt@140 { +- compatible = "aspeed,ast2600-ibt-bmc"; +- reg = <0x140 0x18>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- sdc: sdc@1e740000 { +- compatible = "aspeed,ast2600-sd-controller"; +- reg = <0x1e740000 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1e740000 0x10000>; +- clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; +- status = "disabled"; +- +- sdhci0: sdhci@1e740100 { +- compatible = "aspeed,ast2600-sdhci", "sdhci"; +- reg = <0x100 0x100>; +- interrupts = ; +- sdhci,auto-cmd12; +- clocks = <&syscon ASPEED_CLK_SDIO>; +- status = "disabled"; +- }; +- +- sdhci1: sdhci@1e740200 { +- compatible = "aspeed,ast2600-sdhci", "sdhci"; +- reg = <0x200 0x100>; +- interrupts = ; +- sdhci,auto-cmd12; +- clocks = <&syscon ASPEED_CLK_SDIO>; +- status = "disabled"; +- }; +- }; +- +- emmc_controller: sdc@1e750000 { +- compatible = "aspeed,ast2600-sd-controller"; +- reg = <0x1e750000 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1e750000 0x10000>; +- clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>; +- status = "disabled"; +- +- emmc: sdhci@1e750100 { +- compatible = "aspeed,ast2600-sdhci"; +- reg = <0x100 0x100>; +- sdhci,auto-cmd12; +- interrupts = ; +- clocks = <&syscon ASPEED_CLK_EMMC>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_emmc_default>; +- }; +- }; +- +- vuart1: serial@1e787000 { +- compatible = "aspeed,ast2500-vuart"; +- reg = <0x1e787000 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&syscon ASPEED_CLK_APB1>; +- no-loopback-test; +- status = "disabled"; +- }; +- +- vuart2: serial@1e788000 { +- compatible = "aspeed,ast2500-vuart"; +- reg = <0x1e788000 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&syscon ASPEED_CLK_APB1>; +- no-loopback-test; +- status = "disabled"; +- }; +- +- uart2: serial@1e78d000 { +- compatible = "ns16550a"; +- reg = <0x1e78d000 0x20>; +- reg-shift = <2>; +- reg-io-width = <4>; +- interrupts = ; +- clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; +- resets = <&lpc_reset 5>; +- no-loopback-test; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; +- status = "disabled"; +- }; +- +- uart3: serial@1e78e000 { +- compatible = "ns16550a"; +- reg = <0x1e78e000 0x20>; +- reg-shift = <2>; +- reg-io-width = <4>; +- interrupts = ; +- clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; +- resets = <&lpc_reset 6>; +- no-loopback-test; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; +- status = "disabled"; +- }; +- +- uart4: serial@1e78f000 { +- compatible = "ns16550a"; +- reg = <0x1e78f000 0x20>; +- reg-shift = <2>; +- reg-io-width = <4>; +- interrupts = ; +- clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; +- resets = <&lpc_reset 7>; +- no-loopback-test; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>; +- status = "disabled"; +- }; +- +- i2c: bus@1e78a000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1e78a000 0x1000>; +- }; +- +- fsim0: fsi@1e79b000 { +- compatible = "aspeed,ast2600-fsi-master", "fsi-master"; +- reg = <0x1e79b000 0x94>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fsi1_default>; +- clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; +- status = "disabled"; +- }; +- +- fsim1: fsi@1e79b100 { +- compatible = "aspeed,ast2600-fsi-master", "fsi-master"; +- reg = <0x1e79b100 0x94>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fsi2_default>; +- clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; +- status = "disabled"; +- }; +- }; +- }; +-}; +- +-#include "aspeed-g6-pinctrl.dtsi" +- +-&i2c { +- i2c0: i2c-bus@80 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x80 0x80>; +- compatible = "aspeed,ast2600-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB2>; +- resets = <&syscon ASPEED_RESET_I2C>; +- interrupts = ; +- bus-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1_default>; +- status = "disabled"; +- }; +- +- i2c1: i2c-bus@100 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x100 0x80>; +- compatible = "aspeed,ast2600-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB2>; +- resets = <&syscon ASPEED_RESET_I2C>; +- interrupts = ; +- bus-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2_default>; +- status = "disabled"; +- }; +- +- i2c2: i2c-bus@180 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x180 0x80>; +- compatible = "aspeed,ast2600-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB2>; +- resets = <&syscon ASPEED_RESET_I2C>; +- interrupts = ; +- bus-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3_default>; +- status = "disabled"; +- }; +- +- i2c3: i2c-bus@200 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x200 0x80>; +- compatible = "aspeed,ast2600-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB2>; +- resets = <&syscon ASPEED_RESET_I2C>; +- interrupts = ; +- bus-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4_default>; +- status = "disabled"; +- }; +- +- i2c4: i2c-bus@280 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x280 0x80>; +- compatible = "aspeed,ast2600-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB2>; +- resets = <&syscon ASPEED_RESET_I2C>; +- interrupts = ; +- bus-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c5_default>; +- status = "disabled"; +- }; +- +- i2c5: i2c-bus@300 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x300 0x80>; +- compatible = "aspeed,ast2600-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB2>; +- resets = <&syscon ASPEED_RESET_I2C>; +- interrupts = ; +- bus-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c6_default>; +- status = "disabled"; +- }; +- +- i2c6: i2c-bus@380 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x380 0x80>; +- compatible = "aspeed,ast2600-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB2>; +- resets = <&syscon ASPEED_RESET_I2C>; +- interrupts = ; +- bus-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c7_default>; +- status = "disabled"; +- }; +- +- i2c7: i2c-bus@400 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x400 0x80>; +- compatible = "aspeed,ast2600-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB2>; +- resets = <&syscon ASPEED_RESET_I2C>; +- interrupts = ; +- bus-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c8_default>; +- status = "disabled"; +- }; +- +- i2c8: i2c-bus@480 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x480 0x80>; +- compatible = "aspeed,ast2600-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB2>; +- resets = <&syscon ASPEED_RESET_I2C>; +- interrupts = ; +- bus-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c9_default>; +- status = "disabled"; +- }; +- +- i2c9: i2c-bus@500 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x500 0x80>; +- compatible = "aspeed,ast2600-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB2>; +- resets = <&syscon ASPEED_RESET_I2C>; +- interrupts = ; +- bus-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c10_default>; +- status = "disabled"; +- }; +- +- i2c10: i2c-bus@580 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x580 0x80>; +- compatible = "aspeed,ast2600-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB2>; +- resets = <&syscon ASPEED_RESET_I2C>; +- interrupts = ; +- bus-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c11_default>; +- status = "disabled"; +- }; +- +- i2c11: i2c-bus@600 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x600 0x80>; +- compatible = "aspeed,ast2600-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB2>; +- resets = <&syscon ASPEED_RESET_I2C>; +- interrupts = ; +- bus-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c12_default>; +- status = "disabled"; +- }; +- +- i2c12: i2c-bus@680 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x680 0x80>; +- compatible = "aspeed,ast2600-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB2>; +- resets = <&syscon ASPEED_RESET_I2C>; +- interrupts = ; +- bus-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c13_default>; +- status = "disabled"; +- }; +- +- i2c13: i2c-bus@700 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x700 0x80>; +- compatible = "aspeed,ast2600-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB2>; +- resets = <&syscon ASPEED_RESET_I2C>; +- interrupts = ; +- bus-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c14_default>; +- status = "disabled"; +- }; +- +- i2c14: i2c-bus@780 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x780 0x80>; +- compatible = "aspeed,ast2600-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB2>; +- resets = <&syscon ASPEED_RESET_I2C>; +- interrupts = ; +- bus-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c15_default>; +- status = "disabled"; +- }; +- +- i2c15: i2c-bus@800 { +- #address-cells = <1>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x800 0x80>; +- compatible = "aspeed,ast2600-i2c-bus"; +- clocks = <&syscon ASPEED_CLK_APB2>; +- resets = <&syscon ASPEED_RESET_I2C>; +- interrupts = ; +- bus-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c16_default>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ast2400-facebook-netbmc-common.dtsi b/scripts/dtc/include-prefixes/arm/ast2400-facebook-netbmc-common.dtsi +deleted file mode 100644 +index 4e5e786e18b7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ast2400-facebook-netbmc-common.dtsi ++++ /dev/null +@@ -1,121 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright (c) 2020 Facebook Inc. +-/dts-v1/; +- +-#include "aspeed-g4.dtsi" +- +-/ { +- aliases { +- /* +- * Override the default uart aliases to avoid breaking +- * the legacy applications. +- */ +- serial0 = &uart5; +- serial1 = &uart1; +- serial2 = &uart3; +- serial3 = &uart4; +- }; +- +- memory@40000000 { +- reg = <0x40000000 0x20000000>; +- }; +-}; +- +-&wdt1 { +- status = "okay"; +- aspeed,reset-type = "system"; +-}; +- +-&fmc { +- status = "okay"; +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "spi0.0"; +-#include "facebook-bmc-flash-layout.dtsi" +- }; +-}; +- +-&uart1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default>; +-}; +- +-&uart3 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd3_default +- &pinctrl_rxd3_default>; +-}; +- +-&uart4 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd4_default +- &pinctrl_rxd4_default +- &pinctrl_ndts4_default>; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&mac1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- status = "okay"; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&i2c8 { +- status = "okay"; +-}; +- +-&i2c11 { +- status = "okay"; +-}; +- +-&i2c12 { +- status = "okay"; +-}; +- +-&vhub { +- status = "okay"; +-}; +- +-&adc { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ast2500-facebook-netbmc-common.dtsi b/scripts/dtc/include-prefixes/arm/ast2500-facebook-netbmc-common.dtsi +deleted file mode 100644 +index c0c43b8644ee..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ast2500-facebook-netbmc-common.dtsi ++++ /dev/null +@@ -1,82 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright (c) 2019 Facebook Inc. +- +-#include "aspeed-g5.dtsi" +- +-/ { +- memory@80000000 { +- reg = <0x80000000 0x40000000>; +- }; +-}; +- +-/* +- * Update reset type to "system" (full chip) to fix warm reboot hang issue +- * when reset type is set to default ("soc", gated by reset mask registers). +- */ +-&wdt1 { +- status = "okay"; +- aspeed,reset-type = "system"; +-}; +- +-&wdt2 { +- status = "disabled"; +-}; +- +-&uart1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd1_default +- &pinctrl_rxd1_default>; +-}; +- +-&uart3 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_txd3_default +- &pinctrl_rxd3_default>; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&fmc { +- status = "okay"; +- +- fmc_flash0: flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "spi0.0"; +- }; +- +- fmc_flash1: flash@1 { +- status = "okay"; +- m25p,fast-read; +- label = "spi0.1"; +- }; +-}; +- +-&mac1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&vhub { +- status = "okay"; +-}; +- +-&sdmmc { +- status = "okay"; +-}; +- +-&sdhci1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sd2_default>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ast2600-facebook-netbmc-common.dtsi b/scripts/dtc/include-prefixes/arm/ast2600-facebook-netbmc-common.dtsi +deleted file mode 100644 +index 051de5bec345..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ast2600-facebook-netbmc-common.dtsi ++++ /dev/null +@@ -1,169 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright (c) 2020 Facebook Inc. +- +-#include "aspeed-g6.dtsi" +-#include +- +-/ { +- aliases { +- mmc0 = &emmc; +- spi1 = &spi1; +- spi2 = &spi_gpio; +- }; +- +- chosen { +- bootargs = "console=ttyS0,9600n8 root=/dev/ram rw vmalloc=640M"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x80000000>; +- }; +- +- /* +- * GPIO-based SPI Master is required to access SPI TPM, because +- * full-duplex SPI transactions are not supported by ASPEED SPI +- * Controllers. +- */ +- spi_gpio: spi-gpio { +- status = "okay"; +- compatible = "spi-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio-sck = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>; +- gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>; +- gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>; +- +- tpmdev@0 { +- compatible = "tcg,tpm_tis-spi"; +- spi-max-frequency = <33000000>; +- reg = <0>; +- }; +- }; +-}; +- +-&fmc { +- status = "okay"; +- +- flash@0 { +- status = "okay"; +- m25p,fast-read; +- label = "spi0.0"; +- +-#include "facebook-bmc-flash-layout-128.dtsi" +- }; +- +- flash@1 { +- status = "okay"; +- m25p,fast-read; +- label = "spi0.1"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- flash1@0 { +- reg = <0x0 0x8000000>; +- label = "flash1"; +- }; +- }; +- }; +-}; +- +-&spi1 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&wdt1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- status = "okay"; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&i2c8 { +- status = "okay"; +-}; +- +-&i2c9 { +- status = "okay"; +-}; +- +-&i2c10 { +- status = "okay"; +-}; +- +-&i2c12 { +- status = "okay"; +-}; +- +-&i2c13 { +- status = "okay"; +-}; +- +-&i2c15 { +- status = "okay"; +-}; +- +-&vhub { +- status = "okay"; +-}; +- +-&emmc_controller { +- status = "okay"; +-}; +- +-&emmc { +- status = "okay"; +- +- non-removable; +- max-frequency = <25000000>; +- bus-width = <4>; +-}; +- +-&rtc { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-ariag25.dts b/scripts/dtc/include-prefixes/arm/at91-ariag25.dts +deleted file mode 100644 +index 713d18f80356..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-ariag25.dts ++++ /dev/null +@@ -1,183 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91-ariag25.dts - Device Tree file for Acme Systems Aria G25 (AT91SAM9G25 based) +- * +- * Copyright (C) 2013 Douglas Gilbert , +- * Robert Nelson +- */ +-/dts-v1/; +-#include "at91sam9g25.dtsi" +- +-/ { +- model = "Acme Systems Aria G25"; +- compatible = "acme,ariag25", "atmel,at91sam9x5ek", +- "atmel,at91sam9x5", "atmel,at91sam9"; +- +- aliases { +- serial5 = &uart0; +- serial6 = &uart1; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"; +- }; +- +- memory@20000000 { +- /* 128 MB, change this for 256 MB revision */ +- reg = <0x20000000 0x8000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- /* little green LED in middle of Aria G25 module */ +- aria_led { +- label = "aria_led"; +- gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */ +- linux,default-trigger = "heartbeat"; +- }; +- +- }; +- +- onewire { +- compatible = "w1-gpio"; +- gpios = <&pioA 21 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_w1_0>; +- }; +-}; +- +-&adc0 { +- status = "okay"; +- atmel,adc-channels-used = <0xf>; +-}; +- +-&dbgu { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-/* TWD2+TCLK2 hidden behind ethernet, so no i2c2 */ +- +-&macb0 { +- phy-mode = "rmii"; +- /* +- * following can be overwritten by bootloader: +- * for example u-boot 'ftd set' command +- */ +- local-mac-address = [00 00 00 00 00 00]; +- status = "okay"; +-}; +- +- +-&mmc0 { +- /* N.B. Aria has no SD card detect (CD), assumed present */ +- +- pinctrl-0 = < +- &pinctrl_mmc0_slot0_clk_cmd_dat0 +- &pinctrl_mmc0_slot0_dat1_3>; +- pinctrl-names = "default"; +- status = "okay"; +- +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- }; +-}; +- +-&pinctrl { +- w1_0 { +- pinctrl_w1_0: w1_0-0 { +- atmel,pins = <0 21 0x0 0x1>; /* PA21 PIO, pull-up */ +- }; +- }; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&tcb0 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>; +- }; +- +- timer@1 { +- compatible = "atmel,tcb-timer"; +- reg = <1>; +- }; +-}; +- +-/* +- * UART0/1 pins are marked as GPIO on +- * Aria documentation. +- * Change to "okay" if you need additional serial ports +- */ +-&uart0 { +- status = "disabled"; +-}; +- +-&uart1 { +- status = "disabled"; +-}; +- +-&usart0 { +- pinctrl-0 = <&pinctrl_usart0 +- &pinctrl_usart0_rts +- &pinctrl_usart0_cts>; +- status = "okay"; +-}; +- +-&usart1 { +- pinctrl-0 = <&pinctrl_usart1 +- /* &pinctrl_usart1_rts */ +- /* &pinctrl_usart1_cts */ +- >; +- status = "okay"; +-}; +- +-&usart2 { +- /* cannot activate RTS2+CTS2, clash with +- * ethernet on PB0 and PB1 */ +- pinctrl-0 = <&pinctrl_usart2>; +- status = "okay"; +-}; +- +-&usart3 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf8028000 0x200>; +- interrupts = <8 4 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart3 +- /* &pinctrl_usart3_rts */ +- /* &pinctrl_usart3_cts */ +- >; +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- num-ports = <3>; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-ariettag25.dts b/scripts/dtc/include-prefixes/arm/at91-ariettag25.dts +deleted file mode 100644 +index 2c52a71752c2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-ariettag25.dts ++++ /dev/null +@@ -1,87 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree file for Arietta G25 +- * This device tree is minimal, to activate more peripherals, see: +- * http://dts.acmesystems.it/arietta/ +- */ +-/dts-v1/; +-#include "at91sam9g25.dtsi" +- +-/ { +- model = "Acme Systems Arietta G25"; +- compatible = "acme,ariettag25", "atmel,at91sam9x5", "atmel,at91sam9"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x8000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- arietta_led { +- label = "arietta_led"; +- gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */ +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-&dbgu { +- status = "okay"; +-}; +- +-&mmc0 { +- pinctrl-0 = < +- &pinctrl_mmc0_slot0_clk_cmd_dat0 +- &pinctrl_mmc0_slot0_dat1_3>; +- pinctrl-names = "default"; +- status = "okay"; +- +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- }; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&tcb0 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>; +- }; +- +- timer@1 { +- compatible = "atmel,tcb-timer"; +- reg = <1>; +- }; +-}; +- +-&usb0 { +- num-ports = <3>; +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&usb2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-cosino.dtsi b/scripts/dtc/include-prefixes/arm/at91-cosino.dtsi +deleted file mode 100644 +index ee0f5da6d819..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-cosino.dtsi ++++ /dev/null +@@ -1,152 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91-cosino.dtsi - Device Tree file for Cosino core module +- * +- * Copyright (C) 2013 - Rodolfo Giometti +- * HCE Engineering +- * +- * Derived from at91sam9x5ek.dtsi by: +- * Copyright (C) 2012 Atmel, +- * 2012 Nicolas Ferre +- */ +- +-#include "at91sam9g35.dtsi" +- +-/ { +- model = "HCE Cosino core module"; +- compatible = "hce,cosino", "atmel,at91sam9x5", "atmel,at91sam9"; +- +- chosen { +- bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x8000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +-}; +- +-&adc0 { +- atmel,adc-ts-wires = <4>; +- atmel,adc-ts-pressure-threshold = <10000>; +- status = "okay"; +-}; +- +-&dbgu { +- status = "okay"; +-}; +- +-&ebi { +- pinctrl-0 = <&pinctrl_ebi_addr_nand +- &pinctrl_ebi_data_0_7>; +- pinctrl-names = "default"; +- status = "okay"; +- +- nand-controller { +- pinctrl-0 = <&pinctrl_nand_oe_we +- &pinctrl_nand_cs +- &pinctrl_nand_rb>; +- pinctrl-names = "default"; +- status = "okay"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x40000>; +- }; +- +- uboot@40000 { +- label = "u-boot"; +- reg = <0x40000 0x80000>; +- }; +- +- ubootenv@c0000 { +- label = "U-Boot Env"; +- reg = <0xc0000 0x140000>; +- }; +- +- kernel@200000 { +- label = "kernel"; +- reg = <0x200000 0x600000>; +- }; +- +- rootfs@800000 { +- label = "rootfs"; +- reg = <0x800000 0x0f800000>; +- }; +- }; +- }; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&mmc0 { +- pinctrl-0 = < +- &pinctrl_board_mmc0 +- &pinctrl_mmc0_slot0_clk_cmd_dat0 +- &pinctrl_mmc0_slot0_dat1_3>; +- pinctrl-names = "default"; +- status = "okay"; +- +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&pinctrl { +- mmc0 { +- pinctrl_board_mmc0: mmc0-board { +- atmel,pins = +- ; /* PD15 gpio CD pin pull up and deglitch */ +- }; +- }; +-}; +- +-&tcb0 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>; +- }; +- +- timer@1 { +- compatible = "atmel,tcb-timer"; +- reg = <1>; +- }; +-}; +- +-&usart0 { +- status = "okay"; +-}; +- +-&watchdog { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-cosino_mega2560.dts b/scripts/dtc/include-prefixes/arm/at91-cosino_mega2560.dts +deleted file mode 100644 +index 04cb7bee937d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-cosino_mega2560.dts ++++ /dev/null +@@ -1,75 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91-cosino_mega2560.dts - Device Tree file for Cosino board with +- * Mega 2560 extension +- * +- * Copyright (C) 2013 - Rodolfo Giometti +- * HCE Engineering +- * +- * Derived from at91sam9g35ek.dts by: +- * Copyright (C) 2012 Atmel, +- * 2012 Nicolas Ferre +- */ +- +-/dts-v1/; +-#include "at91-cosino.dtsi" +- +-/ { +- model = "HCE Cosino Mega 2560"; +- compatible = "hce,cosino_mega2560", "atmel,at91sam9x5", "atmel,at91sam9"; +-}; +- +-&adc0 { +- atmel,adc-ts-wires = <4>; +- atmel,adc-ts-pressure-threshold = <10000>; +- status = "okay"; +-}; +- +-&macb0 { +- phy-mode = "rmii"; +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-0 = < +- &pinctrl_mmc1_slot0_clk_cmd_dat0 +- &pinctrl_mmc1_slot0_dat1_3>; +- pinctrl-names = "default"; +- status = "okay"; +- +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- non-removable; +- }; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&usart1 { +- status = "okay"; +-}; +- +-&usart2 { +- status = "okay"; +-}; +- +-&usb0 { +- num-ports = <3>; +- atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW */ +- &pioD 19 GPIO_ACTIVE_LOW +- &pioD 20 GPIO_ACTIVE_LOW +- >; +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&usb2 { +- atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-dvk_som60.dts b/scripts/dtc/include-prefixes/arm/at91-dvk_som60.dts +deleted file mode 100644 +index ededd5b0d27b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-dvk_som60.dts ++++ /dev/null +@@ -1,95 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * at91-dvk_som60.dts - Device Tree file for the DVK SOM60 board +- * +- * Copyright (C) 2018 Laird, +- * 2018 Ben Whitten +- * +- */ +-/dts-v1/; +-#include "at91-som60.dtsi" +-#include "at91-dvk_su60_somc.dtsi" +-#include "at91-dvk_su60_somc_lcm.dtsi" +- +-/ { +- model = "Laird DVK SOM60"; +- compatible = "laird,dvk-som60", "laird,som60", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; +- +- chosen { +- stdout-path = &dbgu; +- tick-timer = &pit; +- }; +-}; +- +-&mmc0 { +- status = "okay"; +-}; +- +-&spi0 { +- status = "okay"; +-}; +- +-&ssc0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&usart1 { +- status = "okay"; +-}; +- +-&usart2 { +- status = "okay"; +-}; +- +-&usart3 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&dbgu { +- status = "okay"; +-}; +- +-&pit { +- status = "okay"; +-}; +- +-&adc0 { +- status = "okay"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&macb0 { +- status = "okay"; +-}; +- +-&macb1 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&usb2 { +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/at91-dvk_su60_somc.dtsi b/scripts/dtc/include-prefixes/arm/at91-dvk_su60_somc.dtsi +deleted file mode 100644 +index c1c8650dafce..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-dvk_su60_somc.dtsi ++++ /dev/null +@@ -1,159 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * at91-dvk_su60_somc.dtsi - Device Tree file for the DVK SOM60 base board +- * +- * Copyright (C) 2018 Laird, +- * 2018 Ben Whitten +- * +- */ +- +-/ { +- sound { +- compatible = "atmel,asoc-wm8904"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pck2_as_audio_mck>; +- +- atmel,model = "wm8904 @ DVK-SOM60"; +- atmel,audio-routing = +- "Headphone Jack", "HPOUTL", +- "Headphone Jack", "HPOUTR", +- "IN2L", "Line In Jack", +- "IN2R", "Line In Jack", +- "Mic", "MICBIAS", +- "IN1L", "Mic"; +- +- atmel,ssc-controller = <&ssc0>; +- atmel,audio-codec = <&wm8904>; +- +- status = "okay"; +- }; +-}; +- +-&mmc0 { +- status = "okay"; +- +- pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; +- slot@0 { +- bus-width = <4>; +- cd-gpios = <&pioE 31 GPIO_ACTIVE_HIGH>; +- cd-inverted; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- +- /* spi0.0: 4M Flash Macronix MX25R4035FM1IL0 */ +- spi-flash@0 { +- compatible = "mxicy,mx25u4035", "jedec,spi-nor"; +- spi-max-frequency = <33000000>; +- reg = <0>; +- }; +-}; +- +-&ssc0 { +- atmel,clk-from-rk-pin; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- wm8904: wm8904@1a { +- compatible = "wlf,wm8904"; +- reg = <0x1a>; +- clocks = <&pmc PMC_TYPE_SYSTEM 10>; +- clock-names = "mclk"; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- eeprom@57 { +- compatible = "giantec,gt24c32a", "atmel,24c32"; +- reg = <0x57>; +- pagesize = <32>; +- }; +-}; +- +-&usart1 { +- status = "okay"; +-}; +- +-&usart2 { +- status = "okay"; +-}; +- +-&usart3 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&dbgu { +- status = "okay"; +-}; +- +-&pit { +- status = "okay"; +-}; +- +-&adc0 { +- status = "okay"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&macb0 { +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- ethernet-phy@7 { +- reg = <7>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_geth_int>; +- interrupt-parent = <&pioB>; +- interrupts = <25 IRQ_TYPE_EDGE_FALLING>; +- txen-skew-ps = <800>; +- txc-skew-ps = <3000>; +- rxdv-skew-ps = <400>; +- rxc-skew-ps = <3000>; +- rxd0-skew-ps = <400>; +- rxd1-skew-ps = <400>; +- rxd2-skew-ps = <400>; +- rxd3-skew-ps = <400>; +- }; +-}; +- +-&macb1 { +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- ethernet-phy@1 { +- reg = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_eth_int>; +- interrupt-parent = <&pioC>; +- interrupts = <10 IRQ_TYPE_EDGE_FALLING>; +- }; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&usb2 { +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/at91-dvk_su60_somc_lcm.dtsi b/scripts/dtc/include-prefixes/arm/at91-dvk_su60_somc_lcm.dtsi +deleted file mode 100644 +index bea920b192b6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-dvk_su60_somc_lcm.dtsi ++++ /dev/null +@@ -1,90 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * at91-dvk_su60_somc_lcm.dtsi - Device Tree file for the DVK SOM60 LCD board +- * +- * Copyright (C) 2018 Laird, +- * 2018 Ben Whitten +- * +- */ +- +-/ { +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&hlcdc_pwm 0 50000 0>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- status = "okay"; +- }; +- +- panel: panel { +- compatible = "winstar,wf70gtiagdng0", "innolux,at070tn92"; +- backlight = <&backlight>; +- power-supply = <&vcc_lcd_reg>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- panel_input: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&hlcdc_panel_output>; +- }; +- }; +- }; +- +- vcc_lcd_reg: fixedregulator_lcd { +- compatible = "regulator-fixed"; +- regulator-name = "VCC LCM"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- status = "okay"; +- }; +-}; +- +-&pinctrl { +- board { +- pinctrl_lcd_ctp_int: lcd_ctp_int { +- atmel,pins = +- ; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- ft5426@38 { +- compatible = "focaltech,ft5426", "edt,edt-ft5406"; +- reg = <0x38>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd_ctp_int>; +- +- interrupt-parent = <&pioC>; +- interrupts = <28 IRQ_TYPE_EDGE_FALLING>; +- +- touchscreen-size-x = <800>; +- touchscreen-size-y = <480>; +- }; +-}; +- +-&hlcdc { +- status = "okay"; +- +- hlcdc-display-controller { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; +- +- port@0 { +- hlcdc_panel_output: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_input>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-foxg20.dts b/scripts/dtc/include-prefixes/arm/at91-foxg20.dts +deleted file mode 100644 +index 7edf057047f8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-foxg20.dts ++++ /dev/null +@@ -1,168 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91-foxg20.dts - Device Tree file for Acme Systems FoxG20 board +- * +- * Based on DT files for at91sam9g20ek evaluation board (AT91SAM9G20 SoC) +- * +- * Copyright (C) 2013 Douglas Gilbert +- */ +-/dts-v1/; +-#include "at91sam9g20.dtsi" +- +-/ { +- model = "Acme Systems FoxG20"; +- compatible = "acme,foxg20", "atmel,at91sam9g20", "atmel,at91sam9"; +- +- chosen { +- bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <18432000>; +- }; +- }; +- +- ahb { +- apb { +- tcb0: timer@fffa0000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +- }; +- +- usb1: gadget@fffa4000 { +- atmel,vbus-gpio = <&pioC 6 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- mmc0: mmc@fffa8000 { +- pinctrl-0 = < +- &pinctrl_mmc0_clk +- &pinctrl_mmc0_slot1_cmd_dat0 +- &pinctrl_mmc0_slot1_dat1_3>; +- pinctrl-names = "default"; +- status = "okay"; +- +- slot@1 { +- reg = <1>; +- bus-width = <4>; +- }; +- }; +- +- usart0: serial@fffb0000 { +- pinctrl-0 = +- <&pinctrl_usart0 +- &pinctrl_usart0_rts +- &pinctrl_usart0_cts +- >; +- status = "okay"; +- }; +- +- usart1: serial@fffb4000 { +- status = "okay"; +- }; +- +- usart2: serial@fffb8000 { +- status = "okay"; +- }; +- +- macb0: ethernet@fffc4000 { +- phy-mode = "rmii"; +- status = "okay"; +- }; +- +- usart3: serial@fffd0000 { +- status = "okay"; +- }; +- +- uart0: serial@fffd4000 { +- status = "okay"; +- }; +- +- uart1: serial@fffd8000 { +- status = "okay"; +- }; +- +- dbgu: serial@fffff200 { +- status = "okay"; +- }; +- +- pinctrl@fffff400 { +- board { +- pinctrl_pck0_as_mck: pck0_as_mck { +- atmel,pins = +- ; +- }; +- }; +- +- mmc0_slot1 { +- pinctrl_board_mmc0_slot1: mmc0_slot1-board { +- atmel,pins = +- ; /* CD pin */ +- }; +- }; +- +- i2c0 { +- pinctrl_i2c0: i2c0-0 { +- atmel,pins = +- ; /* TWCK (SCL), open drain */ +- }; +- }; +- }; +- +- watchdog@fffffd40 { +- status = "okay"; +- }; +- }; +- +- usb0: ohci@500000 { +- num-ports = <2>; +- status = "okay"; +- }; +- }; +- +- i2c-gpio-0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0>; +- i2c-gpio,delay-us = <5>; /* ~85 kHz */ +- status = "okay"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- /* red LED marked "PC7" near mini USB (device) receptacle */ +- user_led { +- label = "user_led"; +- gpios = <&pioC 7 GPIO_ACTIVE_HIGH>; /* PC7 */ +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- btn { +- label = "Button"; +- gpios = <&pioC 4 GPIO_ACTIVE_LOW>; +- linux,code = <0x103>; +- wakeup-source; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-gatwick.dts b/scripts/dtc/include-prefixes/arm/at91-gatwick.dts +deleted file mode 100644 +index 5a81cab5fc3a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-gatwick.dts ++++ /dev/null +@@ -1,121 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * at91-gatwick.dts - Device Tree file for the Gatwick board +- * +- * Copyright (C) 2018 Laird +- * +- */ +-/dts-v1/; +-#include "at91-wb50n.dtsi" +-#include +- +-/ { +- model = "Laird Workgroup Bridge 50N - Project Gatwick"; +- compatible = "laird,gatwick", "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; +- +- gpio_keys { +- compatible = "gpio-keys"; +- autorepeat; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_key_gpio>; +- +- reset-button { +- label = "Reset Button"; +- linux,code = ; +- gpios = <&pioE 31 GPIO_ACTIVE_LOW>; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- ethernet { +- label = "gatwick:yellow:ethernet"; +- gpios = <&pioA 10 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- wifi { +- label = "gatwick:green:wifi"; +- gpios = <&pioA 28 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- ble { +- label = "gatwick:blue:ble"; +- gpios = <&pioA 22 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- lora { +- label = "gatwick:orange:lora"; +- gpios = <&pioA 26 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- blank { +- label = "gatwick:green:blank"; +- gpios = <&pioA 24 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- user { +- label = "gatwick:yellow:user"; +- gpios = <&pioA 12 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +-}; +- +-&pinctrl { +- board { +- pinctrl_key_gpio: key_gpio_0 { +- atmel,pins = +- ; /* PE31 GPIO with pullup deglitch */ +- }; +- }; +-}; +- +-&mmc0 { +- status = "okay"; +-}; +- +-&macb1 { +- status = "okay"; +-}; +- +-&dbgu { +- status = "okay"; +-}; +- +-/* FTDI USART */ +-&usart0 { +- status = "okay"; +-}; +- +-/* GPS USART */ +-&usart1 { +- pinctrl-0 = <&pinctrl_usart1>; +- status = "okay"; +-}; +- +-&spi1 { +- status = "okay"; +- +- spidev@0 { +- compatible = "semtech,sx1301"; +- reg = <0>; +- spi-max-frequency = <8000000>; +- }; +-}; +- +-&usb1 { +- status = "okay"; +- /delete-property/atmel,oc-gpio; +-}; +- +-&usb2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-kizbox.dts b/scripts/dtc/include-prefixes/arm/at91-kizbox.dts +deleted file mode 100644 +index 3b8812fcd854..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-kizbox.dts ++++ /dev/null +@@ -1,192 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91-kizbox.dts - Device Tree file for Overkiz Kizbox board +- * +- * Copyright (C) 2012-2014 Boris BREZILLON +- * 2014-2015 Gaël PORTAY +- */ +-/dts-v1/; +-#include "at91sam9g20.dtsi" +-#include +- +-/ { +- model = "Overkiz Kizbox"; +- compatible = "overkiz,kizbox", "atmel,at91sam9g20", "atmel,at91sam9"; +- +- chosen { +- bootargs = "ubi.mtd=ubi"; +- stdout-path = &dbgu; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x2000000>; +- }; +- +- clocks { +- main_xtal { +- clock-frequency = <18432000>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reset { +- label = "PB_RST"; +- gpios = <&pioB 30 GPIO_ACTIVE_HIGH>; +- linux,code = <0x100>; +- wakeup-source; +- }; +- +- user { +- label = "PB_USER"; +- gpios = <&pioB 31 GPIO_ACTIVE_HIGH>; +- linux,code = <0x101>; +- wakeup-source; +- }; +- }; +- +- led-controller { +- compatible = "pwm-leds"; +- +- led-1 { +- label = "pwm:green:network"; +- pwms = <&tcb1_pwm1 0 10000000 PWM_POLARITY_INVERTED>; +- max-brightness = <255>; +- linux,default-trigger = "default-on"; +- }; +- +- led-2 { +- label = "pwm:red:network"; +- pwms = <&tcb1_pwm2 0 10000000 PWM_POLARITY_INVERTED>; +- max-brightness = <255>; +- linux,default-trigger = "default-on"; +- }; +- +- led-3 { +- label = "pwm:green:user"; +- pwms = <&tcb1_pwm0 0 10000000 PWM_POLARITY_INVERTED>; +- max-brightness = <255>; +- linux,default-trigger = "default-on"; +- }; +- +- led-4 { +- label = "pwm:red:user"; +- pwms = <&tcb1_pwm0 1 10000000 PWM_POLARITY_INVERTED>; +- max-brightness = <255>; +- linux,default-trigger = "default-on"; +- }; +- }; +-}; +- +-&tcb0 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +-}; +- +-&tcb1 { +- tcb1_pwm0: pwm@0 { +- compatible = "atmel,tcb-pwm"; +- reg = <0>; +- #pwm-cells = <3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tcb1_tioa0 &pinctrl_tcb1_tiob0>; +- }; +- +- tcb1_pwm1: pwm@1 { +- compatible = "atmel,tcb-pwm"; +- reg = <1>; +- #pwm-cells = <3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tcb1_tioa1>; +- }; +- +- tcb1_pwm2: pwm@2 { +- compatible = "atmel,tcb-pwm"; +- reg = <2>; +- #pwm-cells = <3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tcb1_tioa2>; +- }; +-}; +- +-&ebi { +- status = "okay"; +-}; +- +-&nand_controller { +- status = "okay"; +- pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; +- pinctrl-names = "default"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "soft"; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- bootstrap@0 { +- label = "bootstrap"; +- reg = <0x0 0x20000>; +- }; +- +- ubi@20000 { +- label = "ubi"; +- reg = <0x20000 0x7fe0000>; +- }; +- }; +- }; +-}; +- +-&macb0 { +- phy-mode = "mii"; +- pinctrl-0 = <&pinctrl_macb_rmii +- &pinctrl_macb_rmii_mii_alt>; +- status = "okay"; +-}; +- +-&usart3 { +- status = "okay"; +-}; +- +-&dbgu { +- status = "okay"; +-}; +- +-&watchdog { +- timeout-sec = <15>; +- atmel,max-heartbeat-sec = <16>; +- atmel,min-heartbeat-sec = <0>; +- status = "okay"; +-}; +- +-&usb0 { +- num-ports = <1>; +- status = "okay"; +-}; +- +-&i2c_gpio0 { +- status = "okay"; +- +- rtc: pcf8563@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-kizbox2-2.dts b/scripts/dtc/include-prefixes/arm/at91-kizbox2-2.dts +deleted file mode 100644 +index cab8b3579efa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-kizbox2-2.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * at91-kizbox2-2.dts - Device Tree file for the Kizbox2 with +- * two head board +- * +- * Copyright (C) 2015 Overkiz SAS +- * +- * Authors: Antoine Aubert +- * Kévin Raymond +- */ +-/dts-v1/; +-#include "at91-kizbox2-common.dtsi" +- +-/ { +- model = "Overkiz Kizbox 2 with two heads"; +- compatible = "overkiz,kizbox2-2", "atmel,sama5d31", +- "atmel,sama5d3", "atmel,sama5"; +-}; +- +-&usart1 { +- status = "okay"; +-}; +- +-&usart2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-kizbox2-common.dtsi b/scripts/dtc/include-prefixes/arm/at91-kizbox2-common.dtsi +deleted file mode 100644 +index c08834ddf07b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-kizbox2-common.dtsi ++++ /dev/null +@@ -1,258 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * at91-kizbox2_common.dtsi - Device Tree Include file for +- * Overkiz Kizbox 2 family SoC +- * +- * Copyright (C) 2014-2018 Overkiz SAS +- * +- * Authors: Antoine Aubert +- * Gaël Portay +- * Kévin Raymond +- */ +-#include "sama5d31.dtsi" +- +-/ { +- chosen { +- bootargs = "ubi.mtd=ubi"; +- stdout-path = &dbgu; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x10000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- prog { +- label = "PB_PROG"; +- gpios = <&pioE 27 GPIO_ACTIVE_LOW>; +- linux,code = <0x102>; +- wakeup-source; +- }; +- +- reset { +- label = "PB_RST"; +- gpios = <&pioE 29 GPIO_ACTIVE_LOW>; +- linux,code = <0x100>; +- wakeup-source; +- }; +- +- user { +- label = "PB_USER"; +- gpios = <&pioE 31 GPIO_ACTIVE_HIGH>; +- linux,code = <0x101>; +- wakeup-source; +- }; +- }; +- +- led-controller { +- compatible = "pwm-leds"; +- +- led-1 { +- label = "pwm:blue:user"; +- pwms = <&pwm0 2 10000000 0>; +- max-brightness = <255>; +- linux,default-trigger = "none"; +- }; +- +- led-2 { +- label = "pwm:green:user"; +- pwms = <&pwm0 1 10000000 0>; +- max-brightness = <255>; +- linux,default-trigger = "default-on"; +- }; +- +- led-3 { +- label = "pwm:red:user"; +- pwms = <&pwm0 0 10000000 0>; +- max-brightness = <255>; +- linux,default-trigger = "default-on"; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- pmic: act8865@5b { +- compatible = "active-semi,act8865"; +- reg = <0x5b>; +- status = "okay"; +- +- regulators { +- vcc_1v8_reg: DCDC_REG1 { +- regulator-name = "VCC_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcc_1v2_reg: DCDC_REG2 { +- regulator-name = "VCC_1V2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vcc_3v3_reg: DCDC_REG3 { +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vddfuse_reg: LDO_REG1 { +- regulator-name = "FUSE_2V5"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- }; +- +- vddana_reg: LDO_REG2 { +- regulator-name = "VDDANA"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vled_reg: LDO_REG3 { +- regulator-name = "VLED"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- v3v8_rf_reg: LDO_REG4 { +- regulator-name = "V3V8_RF"; +- regulator-min-microvolt = <3800000>; +- regulator-max-microvolt = <3800000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&usart0 { +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +-}; +- +-&usart1 { +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +-}; +- +-&usart2 { +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +-}; +- +-&pwm0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_pwmh0_1 +- &pinctrl_pwm0_pwmh1_1 +- &pinctrl_pwm0_pwmh2_0>; +- status = "okay"; +-}; +- +-&adc0 { +- atmel,adc-vref = <3333>; +- status = "okay"; +-}; +- +-&macb1 { +- phy-mode = "rmii"; +- status = "okay"; +-}; +- +-&dbgu { +- status = "okay"; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-&ebi { +- pinctrl-0 = <&pinctrl_ebi_nand_addr>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@3 { +- reg = <0x3 0x0 0x2>; +- atmel,rb = <0>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- bootstrap@0 { +- label = "bootstrap"; +- reg = <0x0 0x20000>; +- }; +- +- ubi@20000 { +- label = "ubi"; +- reg = <0x20000 0x7fe0000>; +- }; +- }; +- }; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&usb2 { +- status = "okay"; +-}; +- +-/* WMBUS (inverted with IO in the latest schematic) */ +-&pinctrl_usart0 { +- atmel,pins = +- ; +-}; +- +-/* RTS */ +-&pinctrl_usart1 { +- atmel,pins = +- ; +-}; +- +-/* IO (inverted with WMBUS in the latest schematic) */ +-&pinctrl_usart2 { +- atmel,pins = +- ; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-kizbox3-hs.dts b/scripts/dtc/include-prefixes/arm/at91-kizbox3-hs.dts +deleted file mode 100644 +index 2799b2a1f4d2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-kizbox3-hs.dts ++++ /dev/null +@@ -1,309 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * at91-kizbox3-hs.dts - Device Tree file for Overkiz KIZBOX3-HS board +- * +- * Copyright (C) 2018 Overkiz SAS +- * +- * Authors: Dorian Rocipon +- * Kevin Carli +- * Mickael Gardet +- */ +-/dts-v1/; +-#include "at91-kizbox3_common.dtsi" +- +-/ { +- model = "Overkiz KIZBOX3-HS"; +- compatible = "overkiz,kizbox3-hs", "atmel,sama5d2", "atmel,sama5"; +- +- led-controller-1 { +- status = "okay"; +- +- led-1 { +- status = "okay"; +- }; +- +- led-2 { +- status = "okay"; +- }; +- +- led-3 { +- status = "okay"; +- }; +- +- led-4 { +- status = "okay"; +- }; +- }; +- +- led-controller-2 { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led_red +- &pinctrl_led_white>; +- status = "okay"; +- +- led-5 { +- label = "pio:red:user"; +- gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-6 { +- label = "pio:white:user"; +- gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default" , "default", "default", +- "default", "default" ; +- pinctrl-0 = <&pinctrl_key_gpio_default>; +- pinctrl-1 = <&pinctrl_pio_rf &pinctrl_pio_wifi>; +- pinctrl-2 = <&pinctrl_pio_io_boot +- &pinctrl_pio_io_reset +- &pinctrl_pio_io_test_radio>; +- pinctrl-3 = <&pinctrl_pio_zbe_test_radio +- &pinctrl_pio_zbe_rst>; +- pinctrl-4 = <&pinctrl_pio_input>; +- +- SW1 { +- label = "SW1"; +- gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>; +- linux,code = <0x101>; +- wakeup-source; +- }; +- +- SW2 { +- label = "SW2"; +- gpios = <&pioA PIN_PA18 GPIO_ACTIVE_LOW>; +- linux,code = <0x102>; +- wakeup-source; +- }; +- +- SW3 { +- label = "SW3"; +- gpios = <&pioA PIN_PA22 GPIO_ACTIVE_LOW>; +- linux,code = <0x103>; +- wakeup-source; +- }; +- +- SW7 { +- label = "SW7"; +- gpios = <&pioA PIN_PA26 GPIO_ACTIVE_LOW>; +- linux,code = <0x107>; +- wakeup-source; +- }; +- +- SW8 { +- label = "SW8"; +- gpios = <&pioA PIN_PA24 GPIO_ACTIVE_LOW>; +- linux,code = <0x108>; +- wakeup-source; +- }; +- }; +- +- gpios { +- compatible = "gpio"; +- status = "okay"; +- +- rf_on { +- label = "rf on"; +- gpio = <&pioA PIN_PC19 GPIO_ACTIVE_HIGH>; +- output; +- init-low; +- }; +- +- wifi_on { +- label = "wifi on"; +- gpio = <&pioA PIN_PC20 GPIO_ACTIVE_HIGH>; +- output; +- init-low; +- }; +- +- zbe_test_radio { +- label = "zbe test radio"; +- gpio = <&pioA PIN_PB21 GPIO_ACTIVE_HIGH>; +- output; +- init-low; +- }; +- +- zbe_rst { +- label = "zbe rst"; +- gpio = <&pioA PIN_PB25 GPIO_ACTIVE_HIGH>; +- output; +- init-low; +- }; +- +- io_reset { +- label = "io reset"; +- gpio = <&pioA PIN_PB30 GPIO_ACTIVE_HIGH>; +- output; +- init-low; +- }; +- +- io_test_radio { +- label = "io test radio"; +- gpio = <&pioA PIN_PC9 GPIO_ACTIVE_HIGH>; +- output; +- init-low; +- }; +- +- io_boot_0 { +- label = "io boot 0"; +- gpio = <&pioA PIN_PC11 GPIO_ACTIVE_HIGH>; +- output; +- init-low; +- }; +- +- io_boot_1 { +- label = "io boot 1"; +- gpio = <&pioA PIN_PC17 GPIO_ACTIVE_HIGH>; +- output; +- init-low; +- }; +- +- verbose_bootloader { +- label = "verbose bootloader"; +- gpio = <&pioA PIN_PB11 GPIO_ACTIVE_HIGH>; +- input; +- }; +- +- nail_bed_detection { +- label = "nail bed detection"; +- gpio = <&pioA PIN_PB12 GPIO_ACTIVE_HIGH>; +- input; +- }; +- +- id_usba { +- label = "id usba"; +- gpio = <&pioA PIN_PC0 GPIO_ACTIVE_LOW>; +- input; +- }; +- }; +-}; +- +-&pioA { +- pinctrl_key_gpio_default: key_gpio_default { +- pinmux= , +- , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_gpio { +- pinctrl_pio_rf: gpio_rf { +- pinmux = ; +- bias-disable; +- }; +- pinctrl_pio_wifi: gpio_wifi { +- pinmux = ; +- bias-disable; +- }; +- pinctrl_pio_io_boot: gpio_io_boot { +- pinmux = +- , +- ; +- bias-disable; +- }; +- pinctrl_pio_io_test_radio: gpio_io_test_radio { +- pinmux = ; +- bias-disable; +- }; +- pinctrl_pio_zbe_test_radio: gpio_zbe_test_radio { +- pinmux = ; +- bias-disable; +- }; +- pinctrl_pio_zbe_rst: gpio_zbe_rst { +- pinmux = ; +- bias-disable; +- }; +- /* stm32 reset must be open drain (internal pull up) */ +- pinctrl_pio_io_reset: gpio_io_reset { +- pinmux = ; +- bias-disable; +- drive-open-drain = <1>; +- output-low; +- }; +- pinctrl_pio_input: gpio_input { +- pinmux = +- , +- , +- ; +- bias-disable; +- }; +- }; +- +- pinctrl_leds { +- pinctrl_led_red: led_red { +- pinmux = ; +- bias-disable; +- }; +- pinctrl_led_white: led_white { +- pinmux = ; +- bias-disable; +- }; +- }; +-}; +- +-&adc { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&uart4 { +- status = "okay"; +-}; +- +-&flx0 { +- status = "okay"; +- +- uart5: serial@200 { +- status = "okay"; +- }; +-}; +- +-&flx3 { +- status = "okay"; +- uart8: serial@200 { +- status = "okay"; +- }; +-}; +- +-&flx4 { +- status = "okay"; +- +- i2c6: i2c@600 { +- status = "okay"; +- }; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&usb2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-kizbox3_common.dtsi b/scripts/dtc/include-prefixes/arm/at91-kizbox3_common.dtsi +deleted file mode 100644 +index abe27adfa4d6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-kizbox3_common.dtsi ++++ /dev/null +@@ -1,371 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * at91-kizbox3.dts - Device Tree Include file for Overkiz Kizbox 3 +- * family SoC boards +- * +- * Copyright (C) 2018 Overkiz SAS +- * +- * Authors: Dorian Rocipon +- * Kevin Carli +- * Mickael Gardet +- */ +-/dts-v1/; +-#include "sama5d2.dtsi" +-#include "sama5d2-pinfunc.h" +-#include +-#include +-#include +-#include +- +-/ { +- model = "Overkiz Kizbox3"; +- compatible = "overkiz,kizbox3", "atmel,sama5d2", "atmel,sama5"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- serial5 = &uart5; +- serial6 = &uart8; +- }; +- +- chosen { +- bootargs = "ubi.mtd=ubi"; +- stdout-path = "serial1:115200n8"; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- vdd_adc_vddana: supply_3v3_ana { +- compatible = "regulator-fixed"; +- regulator-name = "adc-vddana"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_adc_vref: supply_3v3_ref { +- compatible = "regulator-fixed"; +- regulator-name = "adc-vref"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- led-controller-1 { +- compatible = "pwm-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_pwm_h0 +- &pinctrl_pwm0_pwm_h1 +- &pinctrl_pwm0_pwm_h2 +- &pinctrl_pwm0_pwm_h3>; +- status = "disabled"; +- +- led-1 { +- label = "pwm:red:user"; +- pwms = <&pwm0 0 10000000 0>; +- max-brightness = <255>; +- linux,default-trigger = "default-on"; +- status = "disabled"; +- }; +- +- led-2 { +- label = "pwm:green:user"; +- pwms = <&pwm0 1 10000000 0>; +- max-brightness = <255>; +- linux,default-trigger = "default-on"; +- status = "disabled"; +- }; +- +- led-3 { +- label = "pwm:blue:user"; +- pwms = <&pwm0 2 10000000 0>; +- max-brightness = <255>; +- status = "disabled"; +- }; +- +- led-4 { +- label = "pwm:white:user"; +- pwms = <&pwm0 3 10000000 0>; +- max-brightness = <255>; +- status = "disabled"; +- }; +- }; +-}; +- +-&ebi { +- status = "okay"; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@3 { +- pinctrl-0 = <&pinctrl_ebi_nand_addr>; +- pinctrl-names = "default"; +- reg = <0x3 0x0 0x800000>; +- +- atmel,rb = <0>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- bootstrap@0 { +- label = "bootstrap"; +- reg = <0x0 0x20000>; +- }; +- +- u-boot@20000 { +- label = "u-boot"; +- reg = <0x20000 0x140000>; +- }; +- +- u-boot-factory@160000 { +- label = "u-boot-factory"; +- reg = <0x160000 0x140000>; +- }; +- +- ubi@2A0000 { +- label = "ubi"; +- reg = <0x2A0000 0x7D60000>; +- }; +- }; +- +- }; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&pioA { +- pinctrl_ebi_nand_addr: ebi-addr-1 { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_usart { +- pinctrl_usart_0: usart0-0 { +- pinmux = < PIN_PB26__URXD0>, ; +- bias-disable; +- }; +- pinctrl_usart_1: usart1-0 { +- pinmux = < PIN_PD2__URXD1>, ; +- bias-disable; +- }; +- pinctrl_usart_2: usart2-0 { +- pinmux = < PIN_PD4__URXD2>, ; +- bias-disable; +- }; +- pinctrl_usart_3: usart3-0 { +- pinmux = < PIN_PC12__URXD3>, ; +- bias-disable; +- }; +- pinctrl_usart_4: usart4-0 { +- pinmux = < PIN_PB3__URXD4>, ; +- bias-disable; +- }; +- pinctrl_flx0_default: flx0_usart_default { +- pinmux = , //TX +- ; //RX +- bias-disable; +- }; +- pinctrl_flx3_default: flx3_usart_default { +- pinmux = , //RX +- ; //TX +- bias-disable; +- }; +- }; +- +- pinctrl_flx4_default: flx4_i2c6_default { +- pinmux = , //DATA +- ; //CLK +- bias-disable; +- drive-open-drain = <1>; +- }; +- +- pinctrl_pwm0 { +- pinctrl_pwm0_pwm_h0: pwm0_pwm_h0 { +- pinmux = ; +- bias-disable; +- }; +- pinctrl_pwm0_pwm_h1: pwm0_pwmh1 { +- pinmux = ; +- bias-disable; +- }; +- pinctrl_pwm0_pwm_h2: pwm0_pwm_h2 { +- pinmux = ; +- bias-disable; +- }; +- pinctrl_pwm0_pwm_h3: pwm0_pwm_h3 { +- pinmux = ; +- bias-disable; +- }; +- }; +- +- pinctrl_adc { +- pinctrl_adc2: adc2 { +- pinmux = ; +- bias-disable; +- }; +- pinctrl_adc3: adc3 { +- pinmux = ; +- bias-disable; +- }; +- pinctrl_adc4: adc4 { +- pinmux = ; +- bias-disable; +- }; +- pinctrl_adc5: adc5 { +- pinmux = ; +- bias-disable; +- }; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart_0>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +-}; +- +-/* debug uart */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart_1>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart_2>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart_3>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart_4>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +-}; +- +-&flx0 { +- atmel,flexcom-mode = ; +- status = "disabled"; +- +- uart5: serial@200 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flx0_default>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +- }; +-}; +- +-&flx3 { +- atmel,flexcom-mode = ; +- status = "disabled"; +- +- uart8: serial@200 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flx3_default>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +- }; +-}; +- +-&flx4 { +- atmel,flexcom-mode = ; +- status = "disabled"; +- +- i2c6: i2c@600 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flx4_default>; +- status = "disabled"; +- }; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&shutdown_controller { +- debounce-delay-us = <976>; +- atmel,wakeup-rtc-timer; +- +- input@0 { +- reg = <0>; +- }; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-&adc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc2 +- &pinctrl_adc3 +- &pinctrl_adc4 +- &pinctrl_adc5>; +- +- vddana-supply = <&vdd_adc_vddana>; +- vref-supply = <&vdd_adc_vref>; +- status = "disabled"; +-}; +- +-&securam { +- export; +- +- /* export overkiz u-boot mode/version and factory */ +- uboot@1400 { +- reg = <0x1400 0x20>; +- export; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-kizboxmini-base.dts b/scripts/dtc/include-prefixes/arm/at91-kizboxmini-base.dts +deleted file mode 100644 +index 81c29ca5cc1b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-kizboxmini-base.dts ++++ /dev/null +@@ -1,24 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91-kizboxmini-base.dts - Device Tree file for Overkiz Kizbox mini +- * base board +- * +- * Copyright (C) 2015 Overkiz SAS +- * Author: Antoine Aubert +- * Kévin Raymond +- */ +-/dts-v1/; +-#include "at91-kizboxmini-common.dtsi" +- +-/ { +- model = "Overkiz Kizbox Mini"; +- compatible = "overkiz,kizboxmini-base", "atmel,at91sam9g25", +- "atmel,at91sam9x5", "atmel,at91sam9"; +-}; +- +-&pinctrl_usart0 { +- atmel,pins = +- ; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-kizboxmini-common.dtsi b/scripts/dtc/include-prefixes/arm/at91-kizboxmini-common.dtsi +deleted file mode 100644 +index 9c622892c692..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-kizboxmini-common.dtsi ++++ /dev/null +@@ -1,170 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * at91-kizboxmini.dts - Device Tree file for Overkiz Kizbox mini board +- * +- * Copyright (C) 2014-2018 Overkiz SAS +- * Author: Antoine Aubert +- * Gaël Portay +- * Kévin Raymond +- * Dorian Rocipon +- */ +-#include "at91sam9g25.dtsi" +- +-/ { +- chosen { +- bootargs = "ubi.mtd=ubi"; +- stdout-path = &dbgu; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x8000000>; +- }; +- +- clocks { +- main_xtal { +- clock-frequency = <12000000>; +- }; +- +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- adc_op_clk { +- status = "disabled"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- prog { +- label = "PB_PROG"; +- gpios = <&pioC 17 GPIO_ACTIVE_LOW>; +- linux,code = <0x102>; +- wakeup-source; +- }; +- +- reset { +- label = "PB_RST"; +- gpios = <&pioC 16 GPIO_ACTIVE_LOW>; +- linux,code = <0x100>; +- wakeup-source; +- }; +- }; +- +- leds: led-controller-1 { +- compatible = "pwm-leds"; +- +- led_blue: led-1 { +- label = "pwm:blue:user"; +- pwms = <&pwm0 2 10000000 0>; +- max-brightness = <255>; +- linux,default-trigger = "none"; +- status = "disabled"; +- }; +- +- led_green: led-2 { +- label = "pwm:green:user"; +- pwms = <&pwm0 0 10000000 0>; +- max-brightness = <255>; +- linux,default-trigger = "default-on"; +- }; +- +- led_red: led-3 { +- label = "pwm:red:user"; +- pwms = <&pwm0 1 10000000 0>; +- max-brightness = <255>; +- linux,default-trigger = "default-on"; +- }; +- }; +-}; +- +-&usart0 { +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "okay"; +-}; +- +-&macb0 { +- phy-mode = "rmii"; +- status = "okay"; +-}; +- +-&pwm0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_pwm0_1 +- &pinctrl_pwm0_pwm1_1 +- &pinctrl_pwm0_pwm2_1>; +- status = "okay"; +-}; +- +-&dbgu { +- status = "okay"; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-&adc0 { +- status = "disabled"; +-}; +- +-&rtc { +- status = "disabled"; +-}; +- +-&ebi { +- pinctrl-0 = <&pinctrl_ebi_addr_nand +- &pinctrl_ebi_data_0_7>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&nand_controller { +- status = "okay"; +- pinctrl-0 = <&pinctrl_nand_oe_we +- &pinctrl_nand_cs +- &pinctrl_nand_rb>; +- pinctrl-names = "default"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- bootstrap@0 { +- label = "bootstrap"; +- reg = <0x0 0x20000>; +- }; +- +- ubi@20000 { +- label = "ubi"; +- reg = <0x20000 0x7fe0000>; +- }; +- }; +- }; +-}; +- +-&usb0 { +- num-ports = <1>; +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/at91-kizboxmini-mb.dts b/scripts/dtc/include-prefixes/arm/at91-kizboxmini-mb.dts +deleted file mode 100644 +index c07d3076a9bc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-kizboxmini-mb.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2015-2018 Overkiz SAS +- * Author: Mickael Gardet +- * Kévin Raymond +- */ +-/dts-v1/; +-#include "at91-kizboxmini-common.dtsi" +- +-/ { +- model = "Overkiz Kizbox Mini Mother Board"; +- compatible = "overkiz,kizboxmini-mb", "atmel,at91sam9g25", +- "atmel,at91sam9x5", "atmel,at91sam9"; +-}; +- +-&usb0 { +- num-ports = <2>; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&led_blue { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-kizboxmini-rd.dts b/scripts/dtc/include-prefixes/arm/at91-kizboxmini-rd.dts +deleted file mode 100644 +index ab50f4d22387..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-kizboxmini-rd.dts ++++ /dev/null +@@ -1,49 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2015-2018 Overkiz SAS +- * Author: Mickael Gardet +- * Kévin Raymond +- */ +-/dts-v1/; +-#include "at91-kizboxmini-common.dtsi" +- +-/ { +- model = "Overkiz Kizbox Mini RailDIN"; +- compatible = "overkiz,kizboxmini-rd", "atmel,at91sam9g25", +- "atmel,at91sam9x5", "atmel,at91sam9"; +- +- clocks { +- adc_op_clk { +- status = "okay"; +- }; +- }; +-}; +- +-&pinctrl { +- adc0 { +- pinctrl_adc0_ad5: adc0_ad5-0 { +- /* pull-up disable */ +- atmel,pins = ; +- }; +- }; +-}; +- +-&usart0 { +- status = "disabled"; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&led_blue { +- status = "okay"; +-}; +- +-&adc0 { +- atmel,adc-vref = <2500>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc0_ad5>; +- atmel,adc-channels-used = <0x0020>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-linea.dtsi b/scripts/dtc/include-prefixes/arm/at91-linea.dtsi +deleted file mode 100644 +index 533a440d5583..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-linea.dtsi ++++ /dev/null +@@ -1,71 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91-linea.dtsi - Device Tree Include file for the Axentia Linea Module. +- * +- * Copyright (C) 2017 Axentia Technologies AB +- * +- * Author: Peter Rosin +- */ +- +-#include "sama5d31.dtsi" +- +-/ { +- compatible = "axentia,linea", +- "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +-}; +- +-&slow_xtal { +- clock-frequency = <32768>; +-}; +- +-&main_xtal { +- clock-frequency = <12000000>; +-}; +- +-&tcb0 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>; +- }; +- +- timer@1 { +- compatible = "atmel,tcb-timer"; +- reg = <1>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- eeprom@51 { +- compatible = "st,24c64", "atmel,24c64"; +- reg = <0x51>; +- pagesize = <32>; +- }; +-}; +- +-&ebi { +- pinctrl-0 = <&pinctrl_ebi_nand_addr>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +- +-&nand_controller { +- status = "okay"; +- +- nand: nand@3 { +- reg = <0x3 0x0 0x2>; +- atmel,rb = <0>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-natte.dtsi b/scripts/dtc/include-prefixes/arm/at91-natte.dtsi +deleted file mode 100644 +index 49f0a0c46cde..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-natte.dtsi ++++ /dev/null +@@ -1,244 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * at91-natte.dts - Device Tree include file for the Natte board +- * +- * Copyright (C) 2017 Axentia Technologies AB +- * +- * Author: Peter Rosin +- */ +- +-/ { +- mux: mux-controller { +- compatible = "gpio-mux"; +- #mux-control-cells = <0>; +- +- mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>, +- <&ioexp 1 GPIO_ACTIVE_HIGH>, +- <&ioexp 2 GPIO_ACTIVE_HIGH>; +- }; +- +- batntc-mux { +- compatible = "io-channel-mux"; +- io-channels = <&adc 5>; +- io-channel-names = "parent"; +- mux-controls = <&mux>; +- +- channels = +- "batntc0", "batntc1", "batntc2", "batntc3", +- "batntc4", "batntc5", "batntc6", "batntc7"; +- }; +- +- batv-mux { +- compatible = "io-channel-mux"; +- io-channels = <&adc 6>; +- io-channel-names = "parent"; +- mux-controls = <&mux>; +- +- channels = +- "batv0", "batv1", "batv2", "batv3", +- "batv4", "batv5", "batv6", "batv7"; +- }; +- +- iout-mux { +- compatible = "io-channel-mux"; +- io-channels = <&adc 7>; +- io-channel-names = "parent"; +- mux-controls = <&mux>; +- +- channels = +- "iout0", "iout1", "iout2", "iout3", +- "iout4", "iout5", "iout6", "iout7"; +- }; +- +- i2c-mux { +- compatible = "i2c-mux"; +- mux-locked; +- i2c-parent = <&i2c0>; +- mux-controls = <&mux>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- charger@9 { +- compatible = "ti,bq24735"; +- reg = <0x9>; +- +- ti,charge-current = <2000>; +- ti,charge-voltage = <16800>; +- +- poll-interval = <20000>; +- }; +- }; +- +- i2c@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- charger@9 { +- compatible = "ti,bq24735"; +- reg = <0x9>; +- +- ti,charge-current = <2000>; +- ti,charge-voltage = <16800>; +- +- poll-interval = <20000>; +- }; +- }; +- +- i2c@2 { +- reg = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- charger@9 { +- compatible = "ti,bq24735"; +- reg = <0x9>; +- +- ti,charge-current = <2000>; +- ti,charge-voltage = <16800>; +- +- poll-interval = <20000>; +- }; +- }; +- +- i2c@3 { +- reg = <3>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- charger@9 { +- compatible = "ti,bq24735"; +- reg = <0x9>; +- +- ti,charge-current = <2000>; +- ti,charge-voltage = <16800>; +- +- poll-interval = <20000>; +- }; +- }; +- +- i2c@4 { +- reg = <4>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- charger@9 { +- compatible = "ti,bq24735"; +- reg = <0x9>; +- +- ti,charge-current = <2000>; +- ti,charge-voltage = <16800>; +- +- poll-interval = <20000>; +- }; +- }; +- +- i2c@5 { +- reg = <5>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- charger@9 { +- compatible = "ti,bq24735"; +- reg = <0x9>; +- +- ti,charge-current = <2000>; +- ti,charge-voltage = <16800>; +- +- poll-interval = <20000>; +- }; +- }; +- +- i2c@6 { +- reg = <6>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- charger@9 { +- compatible = "ti,bq24735"; +- reg = <0x9>; +- +- ti,charge-current = <2000>; +- ti,charge-voltage = <16800>; +- +- poll-interval = <20000>; +- }; +- }; +- +- i2c@7 { +- reg = <7>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- charger@9 { +- compatible = "ti,bq24735"; +- reg = <0x9>; +- +- ti,charge-current = <2000>; +- ti,charge-voltage = <16800>; +- +- poll-interval = <20000>; +- }; +- }; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- ioexp: ioexp@20 { +- #gpio-cells = <2>; +- compatible = "semtech,sx1502q"; +- reg = <0x20>; +- +- gpio-controller; +- ngpios = <8>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio3_cfg_pins>; +- +- gpio3_cfg_pins: gpio3_cfg { +- pins = "gpio3"; +- bias-pull-up; +- }; +- }; +- +- adc: adc@48 { +- compatible = "ti,ads1015"; +- reg = <0x48>; +- #io-channel-cells = <1>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@4 { +- reg = <4>; +- ti,gain = <2>; +- ti,datarate = <4>; +- }; +- +- channel@5 { +- reg = <5>; +- ti,gain = <2>; +- ti,datarate = <4>; +- }; +- +- channel@6 { +- reg = <6>; +- ti,gain = <1>; +- ti,datarate = <4>; +- }; +- +- channel@7 { +- reg = <7>; +- ti,gain = <3>; +- ti,datarate = <4>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-nattis-2-natte-2.dts b/scripts/dtc/include-prefixes/arm/at91-nattis-2-natte-2.dts +deleted file mode 100644 +index 4f123477e631..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-nattis-2-natte-2.dts ++++ /dev/null +@@ -1,306 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * at91-nattis-2-natte-2.dts - Device Tree file for the Linea/Nattis board +- * +- * Copyright (C) 2017 Axentia Technologies AB +- * +- * Author: Peter Rosin +- */ +-/dts-v1/; +-#include "at91-linea.dtsi" +-#include "at91-natte.dtsi" +- +-/ { +- model = "Axentia Linea-Nattis v2 Natte v2"; +- compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea", +- "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- wakeup { +- label = "Wakeup"; +- linux,code = <10>; +- wakeup-source; +- gpios = <&pioB 27 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- panel_reg: panel-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "panel-VCC"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- bl_reg: backlight-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "panel-VDD"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- panel_bl: backlight { +- compatible = "pwm-backlight"; +- pwms = <&hlcdc_pwm 0 100000 0>; +- +- brightness-levels = < 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100>; +- default-brightness-level = <40>; +- +- power-supply = <&bl_reg>; +- enable-gpios = <&pioA 20 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_blon>; +- }; +- +- panel: panel { +- compatible = "sharp,lq150x1lg11", "panel-lvds"; +- +- backlight = <&panel_bl>; +- power-supply = <&panel_reg>; +- +- width-mm = <304>; +- height-mm = <228>; +- +- data-mapping = "jeida-18"; +- +- panel-timing { +- // 1024x768 @ 60Hz (typical) +- clock-frequency = <50000000 65000000 80000000>; +- hactive = <1024>; +- vactive = <768>; +- hfront-porch = <48 88 88>; +- hback-porch = <96 168 168>; +- hsync-len = <32 64 64>; +- vsync-len = <3 13 74>; +- vfront-porch = <3 13 74>; +- vback-porch = <3 12 74>; +- }; +- +- port { +- panel_input: endpoint { +- remote-endpoint = <&lvds_encoder_output>; +- }; +- }; +- }; +- +- lvds-encoder { +- compatible = "ti,ds90c185", "lvds-encoder"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lvds_prlud0 &pinctrl_lvds_hipow0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- lvds_encoder_input: endpoint { +- remote-endpoint = <&hlcdc_output>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lvds_encoder_output: endpoint { +- remote-endpoint = <&panel_input>; +- }; +- }; +- }; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- +- simple-audio-card,name = "nattis-tfa9879"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&cpu_dai>; +- simple-audio-card,frame-master = <&cpu_dai>; +- simple-audio-card,widgets = "Line", "Line Out Jack"; +- simple-audio-card,routing = "Line Out Jack", "LINEOUT"; +- +- cpu_dai: simple-audio-card,cpu { +- sound-dai = <&ssc0>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&>; +- }; +- }; +-}; +- +-&pinctrl { +- nattis { +- pinctrl_usba_vbus: usba_vbus { +- atmel,pins = ; +- }; +- +- pinctrl_mmc0_cd: mmc0_cd { +- atmel,pins = ; +- }; +- +- pinctrl_lvds_prlud0: lvds_prlud0 { +- atmel,pins = ; +- }; +- +- pinctrl_lvds_hipow0: lvds_hipow0 { +- atmel,pins = ; +- }; +- +- pinctrl_blon: blon { +- atmel,pins = ; +- }; +- }; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- clock-frequency = <100000>; +- +- temp@18 { +- compatible = "nxp,se97b", "jedec,jc-42.4-temp"; +- reg = <0x18>; +- smbus-timeout-disable; +- }; +- +- eeprom@50 { +- compatible = "nxp,se97b", "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- amp: amplifier@6c { +- compatible = "nxp,tfa9879"; +- reg = <0x6c>; +- #sound-dai-cells = <0>; +- }; +-}; +- +-&ssc0 { +- status = "okay"; +- +- atmel,clk-from-rk-pin; +- #sound-dai-cells = <0>; +-}; +- +-&hlcdc { +- status = "okay"; +- +- hlcdc-display-controller { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>; +- +- port@0 { +- hlcdc_output: endpoint { +- remote-endpoint = <&lvds_encoder_input>; +- bus-width = <16>; +- }; +- }; +- }; +-}; +- +-&mmc0 { +- status = "okay"; +- +- pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 +- &pinctrl_mmc0_dat1_3 +- &pinctrl_mmc0_cd>; +- +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; +- cd-inverted; +- }; +-}; +- +-&usart0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart0>; +- atmel,use-dma-rx; +-}; +- +-&nand { +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x40000>; +- }; +- +- barebox@40000 { +- label = "barebox"; +- reg = <0x40000 0x60000>; +- }; +- +- bareboxenv@c0000 { +- label = "bareboxenv"; +- reg = <0xc0000 0x40000>; +- }; +- +- bareboxenv2@100000 { +- label = "bareboxenv2"; +- reg = <0x100000 0x40000>; +- }; +- +- oftree@180000 { +- label = "oftree"; +- reg = <0x180000 0x20000>; +- }; +- +- kernel@200000 { +- label = "kernel"; +- reg = <0x200000 0x500000>; +- }; +- +- rootfs@800000 { +- label = "rootfs"; +- reg = <0x800000 0x1f800000>; +- }; +- }; +-}; +- +-&dbgu { +- status = "okay"; +- +- atmel,use-dma-rx; +-}; +- +-&usb0 { +- status = "okay"; +- +- atmel,vbus-gpio = <&pioD 28 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usba_vbus>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-qil_a9260.dts b/scripts/dtc/include-prefixes/arm/at91-qil_a9260.dts +deleted file mode 100644 +index 969d990767fc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-qil_a9260.dts ++++ /dev/null +@@ -1,215 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91-qil_a9260.dts - Device Tree file for Calao QIL A9260 board +- * +- * Copyright (C) 2011-2013 Jean-Christophe PLAGNIOL-VILLARD +- */ +-/dts-v1/; +-#include "at91sam9260.dtsi" +-/ { +- model = "Calao QIL A9260"; +- compatible = "calao,qil-a9260", "atmel,at91sam9260", "atmel,at91sam9"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- ahb { +- apb { +- tcb0: timer@fffa0000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +- }; +- +- usb1: gadget@fffa4000 { +- atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- mmc0: mmc@fffa8000 { +- pinctrl-0 = < +- &pinctrl_mmc0_clk +- &pinctrl_mmc0_slot0_cmd_dat0 +- &pinctrl_mmc0_slot0_dat1_3>; +- pinctrl-names = "default"; +- status = "okay"; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- }; +- }; +- +- usart0: serial@fffb0000 { +- pinctrl-0 = +- <&pinctrl_usart0 +- &pinctrl_usart0_rts +- &pinctrl_usart0_cts +- &pinctrl_usart0_dtr_dsr +- &pinctrl_usart0_dcd +- &pinctrl_usart0_ri>; +- status = "okay"; +- }; +- +- usart1: serial@fffb4000 { +- pinctrl-0 = +- <&pinctrl_usart1 +- &pinctrl_usart1_rts +- &pinctrl_usart1_cts>; +- status = "okay"; +- }; +- +- usart2: serial@fffb8000 { +- pinctrl-0 = +- <&pinctrl_usart2 +- &pinctrl_usart2_rts +- &pinctrl_usart2_cts>; +- status = "okay"; +- }; +- +- macb0: ethernet@fffc4000 { +- phy-mode = "rmii"; +- status = "okay"; +- }; +- +- spi0: spi@fffc8000 { +- status = "okay"; +- cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>; +- +- m41t94@0 { +- compatible = "st,m41t94"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- +- }; +- +- dbgu: serial@fffff200 { +- status = "okay"; +- }; +- +- shdwc@fffffd10 { +- atmel,wakeup-counter = <10>; +- atmel,wakeup-rtt-timer; +- }; +- }; +- +- usb0: ohci@500000 { +- num-ports = <2>; +- status = "okay"; +- }; +- +- ebi: ebi@10000000 { +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; +- pinctrl-names = "default"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "soft"; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x20000>; +- }; +- +- barebox@20000 { +- label = "barebox"; +- reg = <0x20000 0x40000>; +- }; +- +- bareboxenv@60000 { +- label = "bareboxenv"; +- reg = <0x60000 0x20000>; +- }; +- +- bareboxenv2@80000 { +- label = "bareboxenv2"; +- reg = <0x80000 0x20000>; +- }; +- +- oftree@a0000 { +- label = "oftree"; +- reg = <0xa0000 0x20000>; +- }; +- +- kernel@c0000 { +- label = "kernel"; +- reg = <0xc0000 0x400000>; +- }; +- +- rootfs@4c0000 { +- label = "rootfs"; +- reg = <0x4c0000 0x7800000>; +- }; +- +- data@7cc0000 { +- label = "data"; +- reg = <0x7cc0000 0x8340000>; +- }; +- }; +- }; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- user_led { +- label = "user_led"; +- gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- user_pb { +- label = "user_pb"; +- gpios = <&pioB 10 GPIO_ACTIVE_LOW>; +- linux,code = <28>; +- wakeup-source; +- }; +- }; +- +- i2c-gpio-0 { +- status = "okay"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-sam9_l9260.dts b/scripts/dtc/include-prefixes/arm/at91-sam9_l9260.dts +deleted file mode 100644 +index 1e2a28c2f365..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-sam9_l9260.dts ++++ /dev/null +@@ -1,133 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91-sam9_l9260.dts - Device Tree file for Olimex SAM9-L9260 board +- * +- * Copyright (C) 2016 Raashid Muhammed +- */ +-/dts-v1/; +-#include "at91sam9260.dtsi" +- +-/ { +- model = "Olimex sam9-l9260"; +- compatible = "olimex,sam9-l9260", "atmel,at91sam9260", "atmel,at91sam9"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <18432000>; +- }; +- }; +- +- ahb { +- apb { +- tcb0: timer@fffa0000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +- }; +- +- mmc0: mmc@fffa8000 { +- pinctrl-0 = < +- &pinctrl_board_mmc0 +- &pinctrl_mmc0_clk +- &pinctrl_mmc0_slot1_cmd_dat0 +- &pinctrl_mmc0_slot1_dat1_3>; +- pinctrl-names = "default"; +- status = "okay"; +- +- slot@1 { +- reg = <1>; +- bus-width = <4>; +- cd-gpios = <&pioC 8 GPIO_ACTIVE_HIGH>; +- wp-gpios = <&pioC 4 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- macb0: ethernet@fffc4000 { +- pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_rmii_mii_alt>; +- phy-mode = "mii"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- ethernet-phy@1 { +- reg = <0x1>; +- }; +- }; +- +- spi0: spi@fffc8000 { +- cs-gpios = <&pioC 11 0>, <0>, <0>, <0>; +- status = "okay"; +- +- flash@0 { +- compatible = "atmel,at45", "atmel,dataflash"; +- spi-max-frequency = <15000000>; +- reg = <0>; +- }; +- }; +- +- dbgu: serial@fffff200 { +- status = "okay"; +- }; +- +- pinctrl@fffff400 { +- mmc0 { +- pinctrl_board_mmc0: mmc0-board { +- atmel,pins = +- ; /* WP pin */ +- }; +- }; +- }; +- }; +- +- nand0: nand@40000000 { +- nand-bus-width = <8>; +- nand-ecc-mode = "soft"; +- nand-on-flash-bbt = <1>; +- status = "okay"; +- }; +- +- usb0: ohci@500000 { +- status = "okay"; +- }; +- +- }; +- +- i2c-gpio-0 { +- status = "okay"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pwr_led { +- label = "sam9-l9260:yellow:pwr"; +- gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "cpu0"; +- }; +- +- status_led { +- label = "sam9-l9260:green:status"; +- gpios = <&pioA 6 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "timer"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-sam9x60ek.dts b/scripts/dtc/include-prefixes/arm/at91-sam9x60ek.dts +deleted file mode 100644 +index b1068cca4228..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-sam9x60ek.dts ++++ /dev/null +@@ -1,709 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board +- * +- * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries +- * +- * Author: Sandeep Sheriker M +- */ +-/dts-v1/; +-#include "sam9x60.dtsi" +-#include +- +-/ { +- model = "Microchip SAM9X60-EK"; +- compatible = "microchip,sam9x60ek", "microchip,sam9x60", "atmel,at91sam9"; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- serial1 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <24000000>; +- }; +- }; +- +- regulators: regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- vdd_1v8: fixed-regulator-vdd_1v8@0 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- status = "okay"; +- }; +- +- vdd_1v5: fixed-regulator-vdd_1v5@1 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_1V5"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- status = "okay"; +- }; +- +- vdd1_3v3: fixed-regulator-vdd1_3v3@2 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD1_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- status = "okay"; +- }; +- +- vdd2_3v3: regulator-fixed-vdd2_3v3@3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD2_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- status = "okay"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_key_gpio_default>; +- status = "okay"; +- +- sw1 { +- label = "SW1"; +- gpios = <&pioD 18 GPIO_ACTIVE_LOW>; +- linux,code=; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- status = "okay"; /* Conflict with pwm0. */ +- +- red { +- label = "red"; +- gpios = <&pioB 11 GPIO_ACTIVE_HIGH>; +- }; +- +- green { +- label = "green"; +- gpios = <&pioB 12 GPIO_ACTIVE_HIGH>; +- }; +- +- blue { +- label = "blue"; +- gpios = <&pioB 13 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-&adc { +- vddana-supply = <&vdd1_3v3>; +- vref-supply = <&vdd1_3v3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>; +- status = "okay"; +-}; +- +-&can0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can0_rx_tx>; +- status = "disabled"; /* Conflict with dbgu. */ +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1_rx_tx>; +- status = "okay"; +-}; +- +-&classd { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_classd_default>; +- atmel,pwm-type = "diff"; +- atmel,non-overlap-time = <10>; +- status = "okay"; +-}; +- +-&dbgu { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dbgu>; +- status = "okay"; /* Conflict with can0. */ +-}; +- +-&ebi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>; +- status = "okay"; +- +- nand_controller: nand-controller { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>; +- status = "okay"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <8>; +- nand-ecc-step-size = <512>; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x40000>; +- }; +- +- uboot@40000 { +- label = "u-boot"; +- reg = <0x40000 0xc0000>; +- }; +- +- ubootenvred@100000 { +- label = "U-Boot Env Redundant"; +- reg = <0x100000 0x40000>; +- }; +- +- ubootenv@140000 { +- label = "U-Boot Env"; +- reg = <0x140000 0x40000>; +- }; +- +- dtb@180000 { +- label = "device tree"; +- reg = <0x180000 0x80000>; +- }; +- +- kernel@200000 { +- label = "kernel"; +- reg = <0x200000 0x600000>; +- }; +- +- rootfs@800000 { +- label = "rootfs"; +- reg = <0x800000 0x1f800000>; +- }; +- }; +- }; +- }; +-}; +- +-&flx0 { +- atmel,flexcom-mode = ; +- status = "okay"; +- +- i2c0: i2c@600 { +- compatible = "microchip,sam9x60-i2c"; +- reg = <0x600 0x200>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flx0_default>; +- atmel,fifo-size = <16>; +- i2c-analog-filter; +- i2c-digital-filter; +- i2c-digital-filter-width-ns = <35>; +- status = "okay"; +- +- eeprom@53 { +- compatible = "atmel,24c32"; +- reg = <0x53>; +- pagesize = <16>; +- size = <128>; +- status = "okay"; +- }; +- }; +-}; +- +-&flx4 { +- atmel,flexcom-mode = ; +- status = "disabled"; +- +- spi0: spi@400 { +- compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; +- reg = <0x400 0x200>; +- interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; +- clock-names = "spi_clk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flx4_default>; +- atmel,fifo-size = <16>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +-}; +- +-&flx5 { +- atmel,flexcom-mode = ; +- status = "okay"; +- +- uart1: serial@200 { +- compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; +- reg = <0x200 0x200>; +- interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(10))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(11))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; +- clock-names = "usart"; +- pinctrl-0 = <&pinctrl_flx5_default>; +- pinctrl-names = "default"; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "okay"; +- }; +-}; +- +-&flx6 { +- atmel,flexcom-mode = ; +- status = "okay"; +- +- i2c1: i2c@600 { +- compatible = "microchip,sam9x60-i2c"; +- reg = <0x600 0x200>; +- interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flx6_default>; +- atmel,fifo-size = <16>; +- i2c-analog-filter; +- i2c-digital-filter; +- i2c-digital-filter-width-ns = <35>; +- status = "okay"; +- +- gpio_exp: mcp23008@20 { +- compatible = "microchip,mcp23008"; +- reg = <0x20>; +- }; +- }; +-}; +- +-&gpbr { +- status = "okay"; +-}; +- +-&i2s { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2s_default>; +- #sound-dai-cells = <0>; +- status = "disabled"; /* Conflict with QSPI. */ +-}; +- +-&macb0 { +- phy-mode = "rmii"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_macb0_rmii>; +- status = "okay"; +- +- ethernet-phy@0 { +- reg = <0x0>; +- }; +-}; +- +-&pinctrl { +- adc { +- pinctrl_adc_default: adc_default { +- atmel,pins = ; +- }; +- +- pinctrl_adtrg_default: adtrg_default { +- atmel,pins = ; +- }; +- }; +- +- dbgu { +- pinctrl_dbgu: dbgu-0 { +- atmel,pins = ; +- }; +- }; +- +- i2s { +- pinctrl_i2s_default: i2s { +- atmel,pins = +- ; /* I2SMCK */ +- }; +- }; +- +- qspi { +- pinctrl_qspi: qspi { +- atmel,pins = +- ; +- }; +- }; +- +- nand { +- pinctrl_nand_oe_we: nand-oe-we-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_nand_rb: nand-rb-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_nand_cs: nand-cs-0 { +- atmel,pins = +- ; +- }; +- }; +- +- ebi { +- pinctrl_ebi_data_0_7: ebi-data-lsb-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_data_0_15: ebi-data-msb-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_addr_nand: ebi-addr-0 { +- atmel,pins = +- ; +- }; +- }; +- +- flexcom { +- pinctrl_flx0_default: flx0_twi { +- atmel,pins = +- ; +- }; +- +- pinctrl_flx4_default: flx4_spi { +- atmel,pins = +- ; +- }; +- +- pinctrl_flx5_default: flx_uart { +- atmel,pins = +- ; +- }; +- +- pinctrl_flx6_default: flx6_twi { +- atmel,pins = +- ; +- }; +- }; +- +- classd { +- pinctrl_classd_default: classd { +- atmel,pins = +- ; +- }; +- }; +- +- can0 { +- pinctrl_can0_rx_tx: can0_rx_tx { +- atmel,pins = +- ; /* Enable CAN Transceivers */ +- }; +- }; +- +- can1 { +- pinctrl_can1_rx_tx: can1_rx_tx { +- atmel,pins = +- ; /* Enable CAN Transceivers */ +- }; +- }; +- +- macb0 { +- pinctrl_macb0_rmii: macb0_rmii-0 { +- atmel,pins = +- ; /* PB10 periph A */ +- }; +- }; +- +- pwm0 { +- pinctrl_pwm0_0: pwm0_0 { +- atmel,pins = ; +- }; +- +- pinctrl_pwm0_1: pwm0_1 { +- atmel,pins = ; +- }; +- +- pinctrl_pwm0_2: pwm0_2 { +- atmel,pins = ; +- }; +- +- pinctrl_pwm0_3: pwm0_3 { +- atmel,pins = ; +- }; +- }; +- +- sdmmc0 { +- pinctrl_sdmmc0_default: sdmmc0 { +- atmel,pins = +- ; /* PA20 DAT3 periph A with pullup */ +- }; +- pinctrl_sdmmc0_cd: sdmmc0_cd { +- atmel,pins = +- ; +- }; +- }; +- +- sdmmc1 { +- pinctrl_sdmmc1_default: sdmmc1 { +- atmel,pins = +- ; /* PA4 DAT3 periph B with pullup */ +- }; +- }; +- +- gpio_keys { +- pinctrl_key_gpio_default: pinctrl_key_gpio { +- atmel,pins = ; +- }; +- }; +- +- usb0 { +- pinctrl_usba_vbus: usba_vbus { +- atmel,pins = ; +- }; +- }; +- +- usb1 { +- pinctrl_usb_default: usb_default { +- atmel,pins = ; +- }; +- }; +- +- leds { +- pinctrl_gpio_leds: gpio_leds { +- atmel,pins = ; +- }; +- }; +-}; /* pinctrl */ +- +-&pwm0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2 &pinctrl_pwm0_3>; +- status = "disabled"; /* Conflict with leds. */ +-}; +- +-&sdmmc0 { +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdmmc0_default &pinctrl_sdmmc0_cd>; +- status = "okay"; +- cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>; +- disable-wp; +-}; +- +-&sdmmc1 { +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdmmc1_default>; +- no-1-8-v; +- non-removable; +- status = "disabled"; /* Conflict with flx4. */ +-}; +- +-&qspi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_qspi>; +- status = "okay"; /* Conflict with i2s. */ +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <80000000>; +- spi-tx-bus-width = <4>; +- spi-rx-bus-width = <4>; +- m25p,fast-read; +- +- at91bootstrap@0 { +- label = "qspi: at91bootstrap"; +- reg = <0x0 0x40000>; +- }; +- +- bootloader@40000 { +- label = "qspi: bootloader"; +- reg = <0x40000 0xc0000>; +- }; +- +- bootloaderenvred@100000 { +- label = "qspi: bootloader env redundant"; +- reg = <0x100000 0x40000>; +- }; +- +- bootloaderenv@140000 { +- label = "qspi: bootloader env"; +- reg = <0x140000 0x40000>; +- }; +- +- dtb@180000 { +- label = "qspi: device tree"; +- reg = <0x180000 0x80000>; +- }; +- +- kernel@200000 { +- label = "qspi: kernel"; +- reg = <0x200000 0x600000>; +- }; +- }; +-}; +- +-&rtt { +- atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +- status = "okay"; +-}; +- +-&shutdown_controller { +- debounce-delay-us = <976>; +- status = "okay"; +- +- input@0 { +- reg = <0>; +- }; +-}; +- +-&tcb0 { +- timer0: timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>; +- }; +- +- timer1: timer@1 { +- compatible = "atmel,tcb-timer"; +- reg = <1>; +- }; +-}; +- +-&usb0 { +- atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usba_vbus>; +- status = "okay"; +-}; +- +-&usb1 { +- num-ports = <3>; +- atmel,vbus-gpio = <0 +- &pioD 15 GPIO_ACTIVE_HIGH +- &pioD 16 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_default>; +- status = "okay"; +-}; +- +-&usb2 { +- status = "okay"; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/at91-sama5d27_som1.dtsi b/scripts/dtc/include-prefixes/arm/at91-sama5d27_som1.dtsi +deleted file mode 100644 +index b48ac3b62a31..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-sama5d27_som1.dtsi ++++ /dev/null +@@ -1,153 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * at91-sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SoM1 board +- * +- * Copyright (c) 2017, Microchip Technology Inc. +- * 2017 Cristian Birsan +- * 2017 Claudiu Beznea +- */ +-#include "sama5d2.dtsi" +-#include "sama5d2-pinfunc.h" +- +-/ { +- model = "Atmel SAMA5D27 SoM1"; +- compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; +- +- aliases { +- i2c0 = &i2c0; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <24000000>; +- }; +- }; +- +- ahb { +- sdmmc0: sdio-host@a0000000 { +- microchip,sdcal-inverted; +- }; +- +- apb { +- qspi1: spi@f0024000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_qspi1_default>; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <80000000>; +- spi-tx-bus-width = <4>; +- spi-rx-bus-width = <4>; +- m25p,fast-read; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x00000000 0x00040000>; +- }; +- +- bootloader@40000 { +- label = "bootloader"; +- reg = <0x00040000 0x000c0000>; +- }; +- +- bootloaderenvred@100000 { +- label = "bootloader env redundant"; +- reg = <0x00100000 0x00040000>; +- }; +- +- bootloaderenv@140000 { +- label = "bootloader env"; +- reg = <0x00140000 0x00040000>; +- }; +- +- dtb@180000 { +- label = "device tree"; +- reg = <0x00180000 0x00080000>; +- }; +- +- kernel@200000 { +- label = "kernel"; +- reg = <0x00200000 0x00600000>; +- }; +- }; +- }; +- +- macb0: ethernet@f8008000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_macb0_default>; +- phy-mode = "rmii"; +- +- ethernet-phy@7 { +- reg = <0x7>; +- interrupt-parent = <&pioA>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_macb0_phy_irq>; +- }; +- }; +- +- i2c0: i2c@f8028000 { +- dmas = <0>, <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0_default>; +- status = "okay"; +- +- at24@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <8>; +- }; +- }; +- +- pinctrl@fc038000 { +- pinctrl_i2c0_default: i2c0_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_qspi1_default: qspi1_default { +- sck_cs { +- pinmux = , +- ; +- bias-disable; +- }; +- +- data { +- pinmux = , +- , +- , +- ; +- bias-pull-up; +- }; +- }; +- +- pinctrl_macb0_default: macb0_default { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_macb0_phy_irq: macb0_phy_irq { +- pinmux = ; +- bias-disable; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-sama5d27_som1_ek.dts b/scripts/dtc/include-prefixes/arm/at91-sama5d27_som1_ek.dts +deleted file mode 100644 +index cd4672501add..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-sama5d27_som1_ek.dts ++++ /dev/null +@@ -1,533 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * at91-sama5d27_som1_ek.dts - Device Tree file for SAMA5D27-SOM1-EK board +- * +- * Copyright (c) 2017, Microchip Technology Inc. +- * 2016 Nicolas Ferre +- * 2017 Cristian Birsan +- * 2017 Claudiu Beznea +- */ +-/dts-v1/; +-#include "at91-sama5d27_som1.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "Atmel SAMA5D27 SOM1 EK"; +- compatible = "atmel,sama5d27-som1-ek", "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; +- +- aliases { +- serial0 = &uart1; /* DBGU */ +- serial1 = &uart4; /* mikro BUS 1 */ +- serial2 = &uart2; /* mikro BUS 2 */ +- i2c1 = &i2c1; +- i2c2 = &i2c3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- ahb { +- usb0: gadget@300000 { +- atmel,vbus-gpio = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usba_vbus>; +- status = "okay"; +- }; +- +- usb1: ohci@400000 { +- num-ports = <3>; +- atmel,vbus-gpio = <0 /* &pioA PIN_PD20 GPIO_ACTIVE_HIGH */ +- &pioA PIN_PA27 GPIO_ACTIVE_HIGH +- 0 +- >; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_default>; +- status = "okay"; +- }; +- +- usb2: ehci@500000 { +- status = "okay"; +- }; +- +- sdmmc0: sdio-host@a0000000 { +- bus-width = <8>; +- mmc-ddr-3_3v; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdmmc0_default>; +- status = "okay"; +- }; +- +- sdmmc1: sdio-host@b0000000 { +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdmmc1_default>; +- status = "okay"; +- }; +- +- apb { +- isc: isc@f0008000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_isc_base &pinctrl_isc_data_8bit &pinctrl_isc_data_9_10 &pinctrl_isc_data_11_12>; +- }; +- +- qspi1: spi@f0024000 { +- status = "okay"; +- }; +- +- spi0: spi@f8000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0_default>; +- status = "okay"; +- }; +- +- macb0: ethernet@f8008000 { +- status = "okay"; +- }; +- +- tcb0: timer@f800c000 { +- timer0: timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>; +- }; +- +- timer1: timer@1 { +- compatible = "atmel,tcb-timer"; +- reg = <1>; +- }; +- }; +- +- uart1: serial@f8020000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1_default>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "okay"; +- }; +- +- uart2: serial@f8024000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mikrobus2_uart>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "okay"; +- }; +- +- pwm0: pwm@f802c000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mikrobus1_pwm &pinctrl_mikrobus2_pwm>; +- status = "disabled"; /* Conflict with leds. */ +- }; +- +- flx1: flexcom@f8038000 { +- atmel,flexcom-mode = ; +- status = "okay"; +- +- i2c3: i2c@600 { +- dmas = <0>, <0>; +- i2c-analog-filter; +- i2c-digital-filter; +- i2c-digital-filter-width-ns = <35>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mikrobus_i2c>; +- status = "okay"; +- }; +- }; +- +- shdwc@f8048010 { +- debounce-delay-us = <976>; +- atmel,wakeup-rtc-timer; +- +- input@0 { +- reg = <0>; +- }; +- }; +- +- watchdog@f8048040 { +- status = "okay"; +- }; +- +- uart3: serial@fc008000 { +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3_default>; +- status = "disabled"; /* Conflict with isc. */ +- }; +- +- uart4: serial@fc00c000 { +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mikrobus1_uart>; +- status = "okay"; +- }; +- +- flx3: flexcom@fc014000 { +- atmel,flexcom-mode = ; +- status = "disabled"; +- +- uart8: serial@200 { +- dmas = <0>, <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flx3_default>; +- status = "disabled"; /* Conflict with isc. */ +- }; +- +- spi5: spi@400 { +- dmas = <0>, <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flx3_default>; +- status = "disabled"; /* Conflict with isc. */ +- }; +- }; +- +- flx4: flexcom@fc018000 { +- atmel,flexcom-mode = ; +- status = "okay"; +- +- uart9: serial@200 { +- dmas = <0>, <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flx4_default>; +- status = "disabled"; /* Conflict with spi6 and i2c6. */ +- }; +- +- spi6: spi@400 { +- dmas = <0>, <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>; +- status = "okay"; /* Conflict with uart5 and i2c6. */ +- }; +- +- i2c6: i2c@600 { +- dmas = <0>, <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flx4_default>; +- status = "disabled"; /* Conflict with uart5 and spi6. */ +- }; +- }; +- +- i2c1: i2c@fc028000 { +- dmas = <0>, <0>; +- i2c-analog-filter; +- i2c-digital-filter; +- i2c-digital-filter-width-ns = <35>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1_default>; +- status = "okay"; +- }; +- +- adc: adc@fc030000 { +- vddana-supply = <&vddana>; +- vref-supply = <&advref>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mikrobus1_an &pinctrl_mikrobus2_an>; +- +- status = "okay"; +- }; +- +- pinctrl@fc038000 { +- +- pinctrl_can1_default: can1_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_flx3_default: flx3_default { +- pinmux = , +- , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_i2c1_default: i2c1_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_isc_base: isc_base { +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_isc_data_8bit: isc_data_8bit { +- pinmux = , +- , +- , +- , +- , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_isc_data_9_10: isc_data_9_10 { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_isc_data_11_12: isc_data_11_12 { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_key_gpio_default: key_gpio_default { +- pinmux = ; +- bias-pull-up; +- }; +- +- pinctrl_led_gpio_default: led_gpio_default { +- pinmux = , +- , +- ; +- bias-pull-up; +- }; +- +- pinctrl_sdmmc0_default: sdmmc0_default { +- cmd_data { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- ; +- bias-disable; +- }; +- +- ck_cd_vddsel { +- pinmux = , +- , +- ; +- bias-disable; +- }; +- }; +- +- pinctrl_sdmmc1_default: sdmmc1_default { +- cmd_data { +- pinmux = , +- , +- , +- , +- ; +- bias-disable; +- }; +- +- conf-ck_cd { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- pinctrl_spi0_default: spi0_default { +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_uart1_default: uart1_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_uart3_default: uart3_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_usb_default: usb_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_usba_vbus: usba_vbus { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus1_an: mikrobus1_an { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus2_an: mikrobus2_an { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus1_rst: mikrobus1_rst { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus2_rst: mikrobus2_rst { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus2_spi_cs: mikrobus2_spi_cs { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus_spi: mikrobus_spi { +- pinmux = , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_mikrobus1_pwm: mikrobus1_pwm { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus2_pwm: mikrobus2_pwm { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus1_int: mikrobus1_int { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus2_int: mikrobus2_int { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus1_uart: mikrobus1_uart { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_mikrobus2_uart: mikrobus2_uart { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_mikrobus_i2c: mikrobus1_i2c { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_flx4_default: flx4_uart_default { +- pinmux = , +- , +- , +- , +- ; +- bias-disable; +- }; +- }; +- +- can1: can@fc050000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1_default>; +- status = "okay"; +- }; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_key_gpio_default>; +- +- pb4 { +- label = "USER"; +- gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led_gpio_default>; +- status = "okay"; /* Conflict with pwm0. */ +- +- red { +- label = "red"; +- gpios = <&pioA PIN_PA10 GPIO_ACTIVE_HIGH>; +- }; +- +- green { +- label = "green"; +- gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; +- }; +- +- blue { +- label = "blue"; +- gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- vddin_3v3: fixed-regulator-vddin_3v3 { +- compatible = "regulator-fixed"; +- +- regulator-name = "VDDIN_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- status = "okay"; +- }; +- +- vddana: fixed-regulator-vddana { +- compatible = "regulator-fixed"; +- +- regulator-name = "VDDANA"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vddin_3v3>; +- status = "okay"; +- }; +- +- advref: fixed-regulator-advref { +- compatible = "regulator-fixed"; +- +- regulator-name = "advref"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vddana>; +- status = "okay"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-sama5d27_wlsom1.dtsi b/scripts/dtc/include-prefixes/arm/at91-sama5d27_wlsom1.dtsi +deleted file mode 100644 +index 025a78310e3a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-sama5d27_wlsom1.dtsi ++++ /dev/null +@@ -1,314 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * at91-sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1 +- * +- * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries +- * +- * Author: Nicolas Ferre +- * Author: Eugen Hristev +- */ +-#include "sama5d2.dtsi" +-#include "sama5d2-pinfunc.h" +-#include +-#include +-#include +- +-/ { +- model = "Microchip SAMA5D27 WLSOM1"; +- compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; +- +- aliases { +- i2c0 = &i2c0; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <24000000>; +- }; +- }; +-}; +- +-&flx1 { +- atmel,flexcom-mode = ; +- +- uart6: serial@200 { +- pinctrl-0 = <&pinctrl_flx1_default>; +- pinctrl-names = "default"; +- }; +-}; +- +-&i2c0 { +- pinctrl-0 = <&pinctrl_i2c0_default>; +- pinctrl-1 = <&pinctrl_i2c0_gpio>; +- pinctrl-names = "default", "gpio"; +- sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +-}; +- +-&i2c1 { +- dmas = <0>, <0>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c1_default>; +- pinctrl-1 = <&pinctrl_i2c1_gpio>; +- sda-gpios = <&pioA PIN_PD19 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&pioA PIN_PD20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +- +- mcp16502@5b { +- compatible = "microchip,mcp16502"; +- reg = <0x5b>; +- status = "okay"; +- lpm-gpios = <&pioBU 0 GPIO_ACTIVE_LOW>; +- +- regulators { +- vdd_3v3: VDD_IO { +- regulator-name = "VDD_IO"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3700000>; +- regulator-initial-mode = <2>; +- regulator-allowed-modes = <2>, <4>; +- regulator-always-on; +- +- regulator-state-standby { +- regulator-on-in-suspend; +- regulator-mode = <4>; +- }; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-mode = <4>; +- }; +- }; +- +- vddio_ddr: VDD_DDR { +- regulator-name = "VDD_DDR"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1850000>; +- regulator-initial-mode = <2>; +- regulator-allowed-modes = <2>, <4>; +- regulator-always-on; +- +- regulator-state-standby { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1200000>; +- regulator-changeable-in-suspend; +- regulator-mode = <4>; +- }; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1200000>; +- regulator-changeable-in-suspend; +- regulator-mode = <4>; +- }; +- }; +- +- vdd_core: VDD_CORE { +- regulator-name = "VDD_CORE"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1850000>; +- regulator-initial-mode = <2>; +- regulator-allowed-modes = <2>, <4>; +- regulator-always-on; +- +- regulator-state-standby { +- regulator-on-in-suspend; +- regulator-mode = <4>; +- }; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-mode = <4>; +- }; +- }; +- +- vdd_ddr: VDD_OTHER { +- regulator-name = "VDD_OTHER"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = <2>; +- regulator-allowed-modes = <2>, <4>; +- regulator-always-on; +- +- regulator-state-standby { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- regulator-changeable-in-suspend; +- regulator-mode = <4>; +- }; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- regulator-changeable-in-suspend; +- regulator-mode = <4>; +- }; +- }; +- +- LDO1 { +- regulator-name = "LDO1"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3700000>; +- regulator-always-on; +- +- regulator-state-standby { +- regulator-on-in-suspend; +- }; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- LDO2 { +- regulator-name = "LDO2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3700000>; +- regulator-always-on; +- +- regulator-state-standby { +- regulator-on-in-suspend; +- }; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +-}; +- +-&macb0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_macb0_default>; +- phy-mode = "rmii"; +- +- ethernet-phy@0 { +- reg = <0x0>; +- interrupt-parent = <&pioA>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_macb0_phy_irq>; +- }; +-}; +- +-&pmc { +- atmel,osc-bypass; +-}; +- +-&qspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_qspi1_default>; +- status = "disabled"; +- +- qspi1_flash: spi_flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <80000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <4>; +- m25p,fast-read; +- status = "disabled"; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x40000>; +- }; +- +- bootloader@40000 { +- label = "bootloader"; +- reg = <0x40000 0xc0000>; +- }; +- +- bootloaderenvred@100000 { +- label = "bootloader env redundant"; +- reg = <0x100000 0x40000>; +- }; +- +- bootloaderenv@140000 { +- label = "bootloader env"; +- reg = <0x140000 0x40000>; +- }; +- +- dtb@180000 { +- label = "device tree"; +- reg = <0x180000 0x80000>; +- }; +- +- kernel@200000 { +- label = "kernel"; +- reg = <0x200000 0x600000>; +- }; +- }; +-}; +- +-&pioA { +- pinctrl_flx1_default: flx1_usart_default { +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_i2c0_default: i2c0_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_i2c0_gpio: i2c0_gpio { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_i2c1_default: i2c1_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_i2c1_gpio: i2c1_gpio { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_macb0_default: macb0_default { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_macb0_phy_irq: macb0_phy_irq { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_qspi1_default: qspi1_default { +- pinmux = , +- , +- , +- , +- , +- ; +- bias-pull-up; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/at91-sama5d27_wlsom1_ek.dts b/scripts/dtc/include-prefixes/arm/at91-sama5d27_wlsom1_ek.dts +deleted file mode 100644 +index c145c4e5ef58..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-sama5d27_wlsom1_ek.dts ++++ /dev/null +@@ -1,270 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * at91-sama5d27_wlsom1_ek.dts - Device Tree file for SAMA5D27 WLSOM1 EK +- * +- * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries +- * +- * Author: Nicolas Ferre +- */ +-/dts-v1/; +-#include "at91-sama5d27_wlsom1.dtsi" +-#include +- +-/ { +- model = "Microchip SAMA5D27 WLSOM1 EK"; +- compatible = "microchip,sama5d27-wlsom1-ek", "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; +- +- aliases { +- serial0 = &uart0; /* DBGU */ +- serial1 = &uart6; /* BT */ +- serial2 = &uart5; /* mikro BUS 2 */ +- serial3 = &uart3; /* mikro BUS 1 */ +- i2c1 = &i2c1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_key_gpio_default>; +- status = "okay"; +- +- sw4 { +- label = "USER BUTTON"; +- gpios = <&pioA PIN_PB2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led_gpio_default>; +- status = "okay"; +- +- red { +- label = "red"; +- gpios = <&pioA PIN_PA6 GPIO_ACTIVE_HIGH>; +- }; +- +- green { +- label = "green"; +- gpios = <&pioA PIN_PA7 GPIO_ACTIVE_HIGH>; +- }; +- +- blue { +- label = "blue"; +- gpios = <&pioA PIN_PA8 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-&adc { +- vddana-supply = <&vdd_3v3>; +- vref-supply = <&vdd_3v3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc_default>; +- status = "okay"; +-}; +- +-&flx0 { +- atmel,flexcom-mode = ; +- status = "okay"; +- +- uart5: serial@200 { +- pinctrl-0 = <&pinctrl_flx0_default>; +- pinctrl-names = "default"; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "okay"; +- }; +-}; +- +-&flx1 { +- status = "okay"; +- +- uart6: serial@200 { +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "okay"; +- }; +-}; +- +-&macb0 { +- status = "okay"; +-}; +- +-&pioA { +- /* +- * There is no real pinmux for ADC, if the pin +- * is not requested by another peripheral then +- * the muxing is done when channel is enabled. +- * Requesting pins for ADC is GPIO is +- * encouraged to prevent conflicts and to +- * disable bias in order to be in the same +- * state when the pin is not muxed to the adc. +- */ +- pinctrl_adc_default: adc_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_flx0_default: flx0_usart_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_key_gpio_default: key_gpio_default { +- pinmux = ; +- bias-pull-up; +- }; +- +- pinctrl_led_gpio_default: led_gpio_default { +- pinmux = , +- , +- ; +- bias-pull-down; +- }; +- +- pinctrl_sdmmc0_default: sdmmc0_default { +- cmd_data { +- pinmux = , +- , +- , +- , +- ; +- bias-disable; +- }; +- +- ck_cd_vddsel { +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- }; +- +- pinctrl_uart0_default: uart0_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_uart3_default: uart3_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_pwm0_default: pwm0_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_usb_default: usb_default { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_usba_vbus: usba_vbus { +- pinmux = ; +- bias-disable; +- }; +-}; +- +-&pwm0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_default>; +- status = "okay"; +-}; +- +-&qspi1 { +- status = "okay"; +- +- qspi1_flash: spi_flash@0 { +- status = "okay"; +- }; +-}; +- +-&sdmmc0 { +- bus-width = <4>; +- mmc-ddr-3_3v; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdmmc0_default>; +- status = "okay"; +-}; +- +-&shutdown_controller { +- debounce-delay-us = <976>; +- atmel,wakeup-rtc-timer; +- +- input@0 { +- reg = <0>; +- }; +-}; +- +-&tcb0 { +- timer0: timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>; +- }; +- +- timer1: timer@1 { +- compatible = "atmel,tcb-timer"; +- reg = <1>; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0_default>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3_default>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "okay"; +-}; +- +-&usb0 { +- atmel,vbus-gpio = <&pioA PIN_PA16 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usba_vbus>; +- status = "okay"; +-}; +- +-&usb1 { +- num-ports = <3>; +- atmel,vbus-gpio = <0 +- &pioA PIN_PA10 GPIO_ACTIVE_HIGH +- 0 +- >; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_default>; +- status = "okay"; +-}; +- +-&usb2 { +- phy_type = "hsic"; +- status = "okay"; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/at91-sama5d2_icp.dts b/scripts/dtc/include-prefixes/arm/at91-sama5d2_icp.dts +deleted file mode 100644 +index e06b58724ca8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-sama5d2_icp.dts ++++ /dev/null +@@ -1,773 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * at91-sama5d2_icp.dts - Device Tree file for SAMA5D2-ICP board +- * +- * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries +- * +- * Author: Radu Pirea & Razvan Stefanescu, +- * Codrin Ciubotariu , +- * Cristian Birsan +- */ +-/dts-v1/; +-#include "sama5d2.dtsi" +-#include "sama5d2-pinfunc.h" +-#include +-#include +-#include +- +-/ { +- model = "Microchip SAMA5D2-ICP"; +- compatible = "microchip,sama5d2-icp", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; +- +- aliases { +- serial0 = &uart0; /* debug uart0 + mikro BUS 1 */ +- serial1 = &uart1; /* mikro BUS 3 */ +- serial3 = &uart3; /* mikro BUS 2 */ +- serial5 = &uart7; /* flx2 */ +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_key_gpio_default>; +- status = "okay"; +- +- sw4 { +- label = "USER_PB1"; +- gpios = <&pioA PIN_PD0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led_gpio_default>; +- status = "okay"; /* conflict with pwm0 */ +- +- red { +- label = "red"; +- gpios = <&pioA PIN_PB0 GPIO_ACTIVE_HIGH>; +- }; +- +- green { +- label = "green"; +- gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; +- }; +- +- blue { +- label = "blue"; +- gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-&adc { +- vddana-supply = <&vdd_io_reg>; +- vref-supply = <&vdd_io_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>; +- status = "okay"; +-}; +- +-&can0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can0_default>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1_default>; +- status = "okay"; +-}; +- +-&flx0 { /* mikrobus2 spi */ +- atmel,flexcom-mode = ; +- status = "okay"; +- +- spi2: spi@400 { +- dmas = <0>, <0>; +- cs-gpios = <&pioA PIN_PC0 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mikrobus2_spi &pinctrl_ksz_spi_cs>; +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch0: ksz8563@0 { +- compatible = "microchip,ksz8563"; +- reg = <0>; +- reset-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_LOW>; +- +- spi-max-frequency = <500000>; +- spi-cpha; +- spi-cpol; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- label = "lan1"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan2"; +- }; +- +- port@2 { +- reg = <2>; +- label = "cpu"; +- ethernet = <&macb0>; +- phy-mode = "mii"; +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&flx2 { +- atmel,flexcom-mode = ; +- status = "okay"; +- +- uart7: serial@200 { +- pinctrl-0 = <&pinctrl_flx2_default>; +- pinctrl-names = "default"; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "okay"; /* Conflict w/ qspi1. */ +- }; +-}; +- +-&flx3 { /* mikrobus1 spi */ +- atmel,flexcom-mode = ; +- status = "okay"; +- +- spi5: spi@400 { +- dmas = <0>, <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mikrobus1_spi &pinctrl_mikrobus1_spi_cs>; +- status = "okay"; +- }; +-}; +- +-&flx4 { +- atmel,flexcom-mode = ; +- status = "okay"; +- +- i2c6: i2c@600 { +- dmas = <0>, <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flx4_default>; +- i2c-digital-filter; +- i2c-digital-filter-width-ns = <35>; +- status = "okay"; +- +- mcp16502@5b { +- compatible = "microchip,mcp16502"; +- reg = <0x5b>; +- status = "okay"; +- lpm-gpios = <&pioBU 7 GPIO_ACTIVE_LOW>; +- +- regulators { +- vdd_io_reg: VDD_IO { +- regulator-name = "VDD_IO"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3700000>; +- regulator-initial-mode = <2>; +- regulator-allowed-modes = <2>, <4>; +- regulator-always-on; +- +- regulator-state-standby { +- regulator-on-in-suspend; +- regulator-mode = <4>; +- }; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-mode = <4>; +- }; +- }; +- +- VDD_DDR { +- regulator-name = "VDD_DDR"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1850000>; +- regulator-initial-mode = <2>; +- regulator-allowed-modes = <2>, <4>; +- regulator-always-on; +- +- regulator-state-standby { +- regulator-on-in-suspend; +- regulator-mode = <4>; +- }; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-mode = <4>; +- }; +- }; +- +- VDD_CORE { +- regulator-name = "VDD_CORE"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1850000>; +- regulator-initial-mode = <2>; +- regulator-allowed-modes = <2>, <4>; +- regulator-always-on; +- +- regulator-state-standby { +- regulator-on-in-suspend; +- regulator-mode = <4>; +- }; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-mode = <4>; +- }; +- }; +- +- VDD_OTHER { +- regulator-name = "VDD_OTHER"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1850000>; +- regulator-initial-mode = <2>; +- regulator-allowed-modes = <2>, <4>; +- regulator-always-on; +- +- regulator-state-standby { +- regulator-on-in-suspend; +- regulator-mode = <4>; +- }; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-mode = <4>; +- }; +- }; +- +- LDO1 { +- regulator-name = "LDO1"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3700000>; +- regulator-always-on; +- +- regulator-state-standby { +- regulator-on-in-suspend; +- }; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- LDO2 { +- regulator-name = "LDO2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3700000>; +- regulator-always-on; +- +- regulator-state-standby { +- regulator-on-in-suspend; +- }; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- }; +- }; +- }; +-}; +- +-&i2c0 { /* mikrobus i2c */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mikrobus_i2c>; +- i2c-digital-filter; +- i2c-digital-filter-width-ns = <35>; +- status = "okay"; +-}; +- +-&i2c1 { +- dmas = <0>, <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1_default>; +- i2c-digital-filter; +- i2c-digital-filter-width-ns = <35>; +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c32"; +- reg = <0x50>; +- pagesize = <16>; +- status = "okay"; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c32"; +- reg = <0x52>; +- pagesize = <16>; +- status = "disabled"; +- }; +- +- eeprom@53 { +- compatible = "atmel,24c32"; +- reg = <0x53>; +- pagesize = <16>; +- status = "disabled"; +- }; +-}; +- +-&macb0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq &pinctrl_macb0_rst>; +- phy-mode = "mii"; +- status = "okay"; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +-}; +- +-&pioA { +- pinctrl_adc_default: adc_default { +- pinmux = , +- , +- ; +- bias-disable; +- }; +- +- /* +- * The ADTRG pin can work on any edge type. +- * In here it's being pulled up, so need to +- * connect it to ground to get an edge e.g. +- * Trigger can be configured on falling, rise +- * or any edge, and the pull-up can be changed +- * to pull-down or left floating according to +- * needs. +- */ +- pinctrl_adtrg_default: adtrg_default { +- pinmux = ; +- bias-pull-up; +- }; +- +- pinctrl_flx4_default: flx4_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_can0_default: can0_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_can1_default: can1_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_i2c1_default: i2c1_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_key_gpio_default: key_gpio_default { +- pinmux = ; +- bias-pull-up; +- }; +- +- pinctrl_led_gpio_default: led_gpio_default { +- pinmux = , +- , +- ; +- bias-pull-up; +- }; +- +- pinctrl_qspi1_default: qspi1_default { +- pinmux = , +- , +- , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_sdmmc0_default: sdmmc0_default { +- cmd_data { +- pinmux = , +- , +- , +- , +- ; +- bias-disable; +- }; +- +- ck_cd { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- pinctrl_sdmmc1_default: sdmmc1_default { +- cmd_data { +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- +- ck_cd { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- pinctrl_mikrobus_i2c: mikrobus_i2c { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_mikrobus1_an: mikrobus1_an { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus1_rst: mikrobus1_rst { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus1_spi: mikrobus1_spi { +- pinmux = , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_mikrobus1_pwm: mikrobus1_pwm { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus1_int: mikrobus1_int { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus1_uart: mikrobus1_uart { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_mikrobus2_an: mikrobus2_an { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus2_rst: mikrobus2_rst { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus2_spi_cs: mikrobus2_spi_cs { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus2_spi: mikrobus2_spi { +- pinmux = , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_ksz_spi_cs: ksz_spi_cs { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus2_pwm: mikrobus2_pwm { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus2_int: mikrobus2_int { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus2_uart: mikrobus2_uart { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_mikrobus3_an: mikrobus3_an { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus3_rst: mikrobus3_rst { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus3_spi_cs: mikrobus3_spi_cs { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus3_spi: mikrobus3_spi { +- pinmux = , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_mikrobus3_pwm: mikrobus3_pwm { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus3_int: mikrobus3_int { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus3_uart: mikrobus3_uart { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_usb_default: usb_default { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_usba_vbus: usba_vbus { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_pwm0_pwm2_default: pwm0_pwm2_default { +- pinmux = , +- ; +- bias-pull-up; +- }; +- +- pinctrl_macb0_default: macb0_default { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_macb0_phy_irq: macb0_phy_irq { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_macb0_rst: macb0_sw_rst { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_flx2_default: flx2_default { +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +-}; +- +-&pwm0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_pwm2_default>; +- status = "disabled"; /* conflict with leds, HSIC */ +-}; +- +-&qspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_qspi1_default>; +- status = "disabled"; /* Conflict with wilc_pwrseq, flx2 */ +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <80000000>; +- spi-tx-bus-width = <4>; +- spi-rx-bus-width = <4>; +- m25p,fast-read; +- +- at91bootstrap@0 { +- label = "qspi: at91bootstrap"; +- reg = <0x00000000 0x00040000>; +- }; +- +- bootloader@40000 { +- label = "qspi: bootloader"; +- reg = <0x00040000 0x000c0000>; +- }; +- +- bootloaderenvred@100000 { +- label = "qspi: bootloader env redundant"; +- reg = <0x00100000 0x00040000>; +- }; +- +- bootloaderenv@140000 { +- label = "qspi: bootloader env"; +- reg = <0x00140000 0x00040000>; +- }; +- +- dtb@180000 { +- label = "qspi: device tree"; +- reg = <0x00180000 0x00080000>; +- }; +- +- kernel@200000 { +- label = "qspi: kernel"; +- reg = <0x00200000 0x00600000>; +- }; +- }; +-}; +- +-&sdmmc0 { +- no-1-8-v; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdmmc0_default>; +- status = "okay"; +-}; +- +-&shutdown_controller { +- debounce-delay-us = <976>; +- atmel,wakeup-rtc-timer; +- +- input@0 { +- reg = <0>; +- }; +-}; +- +-&spi0 { /* mikrobus3 spi */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mikrobus3_spi &pinctrl_mikrobus3_spi_cs>; +- status = "okay"; +-}; +- +-&tcb0 { +- timer0: timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>; +- }; +- +- timer1: timer@1 { +- compatible = "atmel,tcb-timer"; +- reg = <1>; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mikrobus1_uart>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mikrobus3_uart>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mikrobus2_uart>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "okay"; +-}; +- +-&usb0 { +- atmel,vbus-gpio = <&pioA PIN_PD23 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usba_vbus>; +- status = "okay"; +-}; +- +-&usb1 { +- num-ports = <3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_default>; +- status = "okay"; +-}; +- +-&usb2 { +- phy_type = "hsic"; +- status = "okay"; +-}; +- +-&watchdog { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-sama5d2_ptc_ek.dts b/scripts/dtc/include-prefixes/arm/at91-sama5d2_ptc_ek.dts +deleted file mode 100644 +index 8ed58af01391..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-sama5d2_ptc_ek.dts ++++ /dev/null +@@ -1,433 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR X11) +-/* +- * at91-sama5d2_ptc_ek.dts - Device Tree file for SAMA5D2 PTC EK board +- * +- * Copyright (C) 2017 Microchip/Atmel, +- * 2017 Wenyou Yang +- * 2017 Ludovic Desroches +- */ +-/dts-v1/; +-#include "sama5d2.dtsi" +-#include "sama5d2-pinfunc.h" +-#include +-#include +-#include +-#include +- +-/ { +- model = "Atmel SAMA5D2 PTC EK"; +- compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5"; +- +- aliases { +- serial0 = &uart0; /* DBGU */ +- i2c0 = &i2c0; /* mikroBUS 1 */ +- i2c1 = &i2c1; /* XPRO EXT1 */ +- i2c2 = &i2c2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <24000000>; +- }; +- }; +- +- ahb { +- usb0: gadget@300000 { +- atmel,vbus-gpio = <&pioA PIN_PB11 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usba_vbus>; +- status = "okay"; +- }; +- +- usb1: ohci@400000 { +- num-ports = <3>; +- atmel,vbus-gpio = <0 +- &pioA PIN_PB12 GPIO_ACTIVE_HIGH +- 0 +- >; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_default>; +- status = "okay"; +- }; +- +- usb2: ehci@500000 { +- status = "okay"; +- }; +- +- ebi: ebi@10000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nand_default>; +- status = "okay"; /* conflicts with sdmmc1 and qspi0 */ +- +- nand_controller: nand-controller { +- status = "okay"; +- +- nand@3 { +- reg = <0x3 0x0 0x2>; +- atmel,rb = <0>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "bootstrap"; +- reg = <0x0 0x40000>; +- }; +- +- bootloader@40000 { +- label = "bootloader"; +- reg = <0x40000 0xc0000>; +- }; +- +- bootloaderenvred@100000 { +- label = "bootloader env redundant"; +- reg = <0x100000 0x40000>; +- }; +- +- bootloaderenv@140000 { +- label = "bootloader env"; +- reg = <0x140000 0x40000>; +- }; +- +- dtb@180000 { +- label = "device tree"; +- reg = <0x180000 0x80000>; +- }; +- +- kernel@200000 { +- label = "kernel"; +- reg = <0x200000 0x600000>; +- }; +- +- rootfs@800000 { +- label = "rootfs"; +- reg = <0x800000 0x1f800000>; +- }; +- }; +- }; +- }; +- }; +- +- sdmmc0: sdio-host@a0000000 { +- bus-width = <8>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdmmc0_default>; +- status = "okay"; +- }; +- +- apb { +- spi0: spi@f8000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0_default>; +- status = "okay"; +- }; +- +- macb0: ethernet@f8008000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>; +- phy-mode = "rmii"; +- status = "okay"; +- +- ethernet-phy@1 { +- reg = <0x1>; +- interrupt-parent = <&pioA>; +- interrupts = <56 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +- +- tcb0: timer@f800c000 { +- timer0: timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>; +- }; +- +- timer1: timer@1 { +- compatible = "atmel,tcb-timer"; +- reg = <1>; +- }; +- }; +- +- uart0: serial@f801c000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0_default>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "okay"; +- }; +- +- uart2: serial@f8024000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2_default>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "okay"; +- }; +- +- i2c0: i2c@f8028000 { +- dmas = <0>, <0>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c0_default>; +- pinctrl-1 = <&pinctrl_i2c0_gpio>; +- sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +- }; +- +- flx0: flexcom@f8034000 { +- atmel,flexcom-mode = ; +- status = "okay"; +- +- i2c2: i2c@600 { +- dmas = <0>, <0>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_flx0_default>; +- pinctrl-1 = <&pinctrl_flx0_gpio>; +- sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&pioA PIN_PB29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +- }; +- }; +- +- shdwc@f8048010 { +- debounce-delay-us = <976>; +- +- input@0 { +- reg = <0>; +- }; +- }; +- +- watchdog@f8048040 { +- status = "okay"; +- }; +- +- spi1: spi@fc000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- status = "okay"; +- }; +- +- i2c1: i2c@fc028000 { +- dmas = <0>, <0>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c1_default>; +- pinctrl-1 = <&pinctrl_i2c1_gpio>; +- sda-gpios = <&pioA PIN_PC6 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&pioA PIN_PC7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +- +- at24@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <8>; +- }; +- }; +- +- pinctrl@fc038000 { +- pinctrl_flx0_default: flx0_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_flx0_gpio: flx0_gpio { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_i2c0_default: i2c0_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_i2c0_gpio: i2c0_gpio { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_i2c1_default: i2c1_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_i2c1_gpio: i2c1_gpio { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_key_gpio_default: key_gpio_default { +- pinmux = ; +- bias-pull-up; +- }; +- +- pinctrl_led_gpio_default: led_gpio_default { +- pinmux = , +- , +- ; +- bias-pull-up; +- }; +- +- pinctrl_macb0_default: macb0_default { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_macb0_phy_irq: macb0_phy_irq { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_nand_default: nand_default { +- re_we_data { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- bias-pull-up; +- atmel,drive-strength = ; +- }; +- +- ale_cle_rdy_cs { +- pinmux = , +- , +- , +- ; +- bias-pull-up; +- }; +- }; +- +- pinctrl_sdmmc0_default: sdmmc0_default { +- cmd_data { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- ; +- bias-pull-up; +- }; +- +- ck_cd_vddsel { +- pinmux = , +- , +- ; +- bias-disable; +- }; +- }; +- +- pinctrl_spi0_default: spi0_default { +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_spi1_default: spi1_default { +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_uart0_default: uart0_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_uart2_default: uart2_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_usb_default: usb_default { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_usba_vbus: usba_vbus { +- pinmux = ; +- bias-disable; +- }; +- +- }; +- +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_key_gpio_default>; +- +- bp1 { +- label = "PB_USER"; +- gpios = <&pioA PIN_PA10 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led_gpio_default>; +- status = "okay"; +- +- red { +- label = "red"; +- gpios = <&pioA PIN_PB10 GPIO_ACTIVE_HIGH>; +- }; +- +- green { +- label = "green"; +- gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; +- }; +- +- blue { +- label = "blue"; +- gpios = <&pioA PIN_PB6 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-sama5d2_xplained.dts b/scripts/dtc/include-prefixes/arm/at91-sama5d2_xplained.dts +deleted file mode 100644 +index b1e854f658de..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-sama5d2_xplained.dts ++++ /dev/null +@@ -1,744 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * at91-sama5d2_xplained.dts - Device Tree file for SAMA5D2 Xplained board +- * +- * Copyright (C) 2015 Atmel, +- * 2015 Nicolas Ferre +- */ +-/dts-v1/; +-#include "sama5d2.dtsi" +-#include "sama5d2-pinfunc.h" +-#include +-#include +-#include +-#include +- +-/ { +- model = "Atmel SAMA5D2 Xplained"; +- compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5"; +- +- aliases { +- serial0 = &uart1; /* DBGU */ +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; /* XPRO EXT2 */ +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- ahb { +- usb0: gadget@300000 { +- atmel,vbus-gpio = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usba_vbus>; +- status = "okay"; +- }; +- +- usb1: ohci@400000 { +- num-ports = <3>; +- atmel,vbus-gpio = <0 /* &pioA PIN_PB9 GPIO_ACTIVE_HIGH */ +- &pioA PIN_PB10 GPIO_ACTIVE_HIGH +- 0 +- >; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_default>; +- status = "okay"; +- }; +- +- usb2: ehci@500000 { +- status = "okay"; +- }; +- +- sdmmc0: sdio-host@a0000000 { +- bus-width = <8>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdmmc0_default>; +- non-removable; +- mmc-ddr-1_8v; +- status = "okay"; +- }; +- +- sdmmc1: sdio-host@b0000000 { +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdmmc1_default>; +- status = "okay"; /* conflict with qspi0 */ +- vqmmc-supply = <&vdd_3v3_reg>; +- vmmc-supply = <&vdd_3v3_reg>; +- }; +- +- apb { +- qspi0: spi@f0020000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_qspi0_default>; +- status = "disabled"; /* conflict with sdmmc1 */ +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <80000000>; +- spi-tx-bus-width = <4>; +- spi-rx-bus-width = <4>; +- m25p,fast-read; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x00000000 0x00040000>; +- }; +- +- bootloader@40000 { +- label = "bootloader"; +- reg = <0x00040000 0x000c0000>; +- }; +- +- bootloaderenvred@100000 { +- label = "bootloader env redundant"; +- reg = <0x00100000 0x00040000>; +- }; +- +- bootloaderenv@140000 { +- label = "bootloader env"; +- reg = <0x00140000 0x00040000>; +- }; +- +- dtb@180000 { +- label = "device tree"; +- reg = <0x00180000 0x00080000>; +- }; +- +- kernel@200000 { +- label = "kernel"; +- reg = <0x00200000 0x00600000>; +- }; +- +- misc@800000 { +- label = "misc"; +- reg = <0x00800000 0x00000000>; +- }; +- }; +- }; +- +- spi0: spi@f8000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0_default>; +- status = "okay"; +- +- m25p80@0 { +- compatible = "atmel,at25df321a"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- }; +- }; +- +- macb0: ethernet@f8008000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>; +- phy-mode = "rmii"; +- status = "okay"; +- +- ethernet-phy@1 { +- reg = <0x1>; +- interrupt-parent = <&pioA>; +- interrupts = ; +- }; +- }; +- +- tcb0: timer@f800c000 { +- timer0: timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>; +- }; +- +- timer1: timer@1 { +- compatible = "atmel,tcb-timer"; +- reg = <1>; +- }; +- }; +- +- uart1: serial@f8020000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1_default>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "okay"; +- }; +- +- i2c0: i2c@f8028000 { +- dmas = <0>, <0>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c0_default>; +- pinctrl-1 = <&pinctrl_i2c0_gpio>; +- sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-sda-hold-time-ns = <350>; +- status = "okay"; +- +- pmic@5b { +- compatible = "active-semi,act8945a"; +- reg = <0x5b>; +- active-semi,vsel-high; +- status = "okay"; +- +- regulators { +- vdd_1v35_reg: REG_DCDC1 { +- regulator-name = "VDD_1V35"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-allowed-modes = , +- ; +- regulator-initial-mode = ; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-min-microvolt=<1400000>; +- regulator-suspend-max-microvolt=<1400000>; +- regulator-changeable-in-suspend; +- regulator-mode=; +- }; +- }; +- +- vdd_1v2_reg: REG_DCDC2 { +- regulator-name = "VDD_1V2"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1300000>; +- regulator-allowed-modes = , +- ; +- regulator-initial-mode = ; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_3v3_reg: REG_DCDC3 { +- regulator-name = "VDD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-allowed-modes = , +- ; +- regulator-initial-mode = ; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_fuse_reg: REG_LDO1 { +- regulator-name = "VDD_FUSE"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-allowed-modes = , +- ; +- regulator-initial-mode = ; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_3v3_lp_reg: REG_LDO2 { +- regulator-name = "VDD_3V3_LP"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-allowed-modes = , +- ; +- regulator-initial-mode = ; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_led_reg: REG_LDO3 { +- regulator-name = "VDD_LED"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-allowed-modes = , +- ; +- regulator-initial-mode = ; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_sdhc_1v8_reg: REG_LDO4 { +- regulator-name = "VDD_SDHC_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-allowed-modes = , +- ; +- regulator-initial-mode = ; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- +- charger { +- compatible = "active-semi,act8945a-charger"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>; +- interrupt-parent = <&pioA>; +- interrupts = ; +- +- active-semi,chglev-gpios = <&pioA PIN_PA12 GPIO_ACTIVE_HIGH>; +- active-semi,lbo-gpios = <&pioA PIN_PC8 GPIO_ACTIVE_LOW>; +- active-semi,input-voltage-threshold-microvolt = <6600>; +- active-semi,precondition-timeout = <40>; +- active-semi,total-timeout = <3>; +- status = "okay"; +- }; +- }; +- }; +- +- pwm0: pwm@f802c000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_pwm2_default>; +- status = "disabled"; /* conflict with leds */ +- }; +- +- flx0: flexcom@f8034000 { +- atmel,flexcom-mode = ; +- status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */ +- +- uart5: serial@200 { +- dmas = <0>, <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flx0_default>; +- status = "okay"; +- }; +- +- i2c2: i2c@600 { +- dmas = <0>, <0>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_flx0_default>; +- pinctrl-1 = <&pinctrl_i2c2_gpio>; +- sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&pioA PIN_PB29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-sda-hold-time-ns = <350>; +- i2c-analog-filter; +- i2c-digital-filter; +- i2c-digital-filter-width-ns = <35>; +- status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */ +- }; +- }; +- +- shdwc@f8048010 { +- debounce-delay-us = <976>; +- atmel,wakeup-rtc-timer; +- +- input@0 { +- reg = <0>; +- }; +- }; +- +- watchdog@f8048040 { +- status = "okay"; +- }; +- +- i2s0: i2s@f8050000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2s0_default>; +- status = "disabled"; /* conflict with can0 */ +- }; +- +- can0: can@f8054000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can0_default>; +- status = "okay"; +- }; +- +- uart3: serial@fc008000 { +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3_default>; +- status = "okay"; +- }; +- +- flx4: flexcom@fc018000 { +- atmel,flexcom-mode = ; +- status = "okay"; +- +- i2c6: i2c@600 { +- dmas = <0>, <0>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_flx4_default>; +- pinctrl-1 = <&pinctrl_flx4_gpio>; +- sda-gpios = <&pioA PIN_PD12 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&pioA PIN_PD13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-analog-filter; +- i2c-digital-filter; +- i2c-digital-filter-width-ns = <35>; +- status = "okay"; +- }; +- }; +- +- i2c1: i2c@fc028000 { +- dmas = <0>, <0>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c1_default>; +- i2c-analog-filter; +- i2c-digital-filter; +- i2c-digital-filter-width-ns = <35>; +- pinctrl-1 = <&pinctrl_i2c1_gpio>; +- sda-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&pioA PIN_PD5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +- +- at24@54 { +- compatible = "atmel,24c02"; +- reg = <0x54>; +- pagesize = <16>; +- }; +- }; +- +- adc: adc@fc030000 { +- vddana-supply = <&vdd_3v3_lp_reg>; +- vref-supply = <&vdd_3v3_lp_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>; +- status = "okay"; +- }; +- +- pinctrl@fc038000 { +- /* +- * There is no real pinmux for ADC, if the pin +- * is not requested by another peripheral then +- * the muxing is done when channel is enabled. +- * Requesting pins for ADC is GPIO is +- * encouraged to prevent conflicts and to +- * disable bias in order to be in the same +- * state when the pin is not muxed to the adc. +- */ +- pinctrl_adc_default: adc_default { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_can0_default: can0_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_can1_default: can1_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- /* +- * The ADTRG pin can work on any edge type. +- * In here it's being pulled up, so need to +- * connect it to ground to get an edge e.g. +- * Trigger can be configured on falling, rise +- * or any edge, and the pull-up can be changed +- * to pull-down or left floating according to +- * needs. +- */ +- pinctrl_adtrg_default: adtrg_default { +- pinmux = ; +- bias-pull-up; +- }; +- +- pinctrl_charger_chglev: charger_chglev { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_charger_irq: charger_irq { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_charger_lbo: charger_lbo { +- pinmux = ; +- bias-pull-up; +- }; +- +- pinctrl_classd_default_pfets: classd_default_pfets { +- pinmux = , +- ; +- bias-pull-up; +- }; +- +- pinctrl_classd_default_nfets: classd_default_nfets { +- pinmux = , +- ; +- bias-pull-down; +- }; +- +- pinctrl_flx0_default: flx0_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_flx4_default: flx4_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_flx4_gpio: flx4_gpio { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_i2c0_default: i2c0_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_i2c0_gpio: i2c0_gpio { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_i2c1_default: i2c1_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_i2c1_gpio: i2c1_gpio { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_i2c2_gpio: i2c2_gpio { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_i2s0_default: i2s0_default { +- pinmux = , +- , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_i2s1_default: i2s1_default { +- pinmux = , +- , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_key_gpio_default: key_gpio_default { +- pinmux = ; +- bias-pull-up; +- }; +- +- pinctrl_led_gpio_default: led_gpio_default { +- pinmux = , +- , +- ; +- bias-pull-up; +- }; +- +- pinctrl_macb0_default: macb0_default { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_macb0_phy_irq: macb0_phy_irq { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_qspi0_default: qspi0_default { +- sck_cs { +- pinmux = , +- ; +- bias-disable; +- }; +- +- data { +- pinmux = , +- , +- , +- ; +- bias-pull-up; +- }; +- }; +- +- pinctrl_sdmmc0_default: sdmmc0_default { +- cmd_data { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- ; +- bias-disable; +- }; +- +- ck_cd_rstn_vddsel { +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- }; +- +- pinctrl_sdmmc1_default: sdmmc1_default { +- cmd_data { +- pinmux = , +- , +- , +- , +- ; +- bias-disable; +- }; +- +- conf-ck_cd { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- pinctrl_spi0_default: spi0_default { +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_uart1_default: uart1_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_uart3_default: uart3_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_usb_default: usb_default { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_usba_vbus: usba_vbus { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_pwm0_pwm2_default: pwm0_pwm2_default { +- pinmux = , +- ; +- bias-pull-up; +- }; +- }; +- +- classd: classd@fc048000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_classd_default_pfets &pinctrl_classd_default_nfets>; +- atmel,pwm-type = "diff"; +- atmel,non-overlap-time = <10>; +- status = "okay"; +- }; +- +- i2s1: i2s@fc04c000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2s1_default>; +- status = "disabled"; /* conflict with spi0, sdmmc1 */ +- }; +- +- can1: can@fc050000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1_default>; +- status = "okay"; +- }; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_key_gpio_default>; +- +- bp1 { +- label = "PB_USER"; +- gpios = <&pioA PIN_PB9 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led_gpio_default>; +- status = "okay"; /* conflict with pwm0 */ +- +- red { +- label = "red"; +- gpios = <&pioA PIN_PB6 GPIO_ACTIVE_LOW>; +- }; +- +- +- green { +- label = "green"; +- gpios = <&pioA PIN_PB5 GPIO_ACTIVE_LOW>; +- }; +- +- blue { +- label = "blue"; +- gpios = <&pioA PIN_PB0 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-sama5d3_xplained.dts b/scripts/dtc/include-prefixes/arm/at91-sama5d3_xplained.dts +deleted file mode 100644 +index d72c042f2850..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-sama5d3_xplained.dts ++++ /dev/null +@@ -1,406 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91-sama5d3_xplained.dts - Device Tree file for the SAMA5D3 Xplained board +- * +- * Copyright (C) 2014 Atmel, +- * 2014 Nicolas Ferre +- */ +-/dts-v1/; +-#include "sama5d36.dtsi" +-#include +- +-/ { +- model = "SAMA5D3 Xplained"; +- compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x10000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- ahb { +- apb { +- mmc0: mmc@f0000000 { +- pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; +- vmmc-supply = <&vcc_mmc0_reg>; +- vqmmc-supply = <&vcc_3v3_reg>; +- status = "okay"; +- slot@0 { +- reg = <0>; +- bus-width = <8>; +- cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- mmc1: mmc@f8000000 { +- vmmc-supply = <&vcc_3v3_reg>; +- vqmmc-supply = <&vcc_3v3_reg>; +- status = "disabled"; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioE 1 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- spi0: spi@f0004000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0_cs>; +- cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>; +- status = "okay"; +- }; +- +- can0: can@f000c000 { +- status = "okay"; +- }; +- +- tcb0: timer@f0010000 { +- timer0: timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>; +- }; +- +- timer1: timer@1 { +- compatible = "atmel,tcb-timer"; +- reg = <1>; +- }; +- }; +- +- i2c0: i2c@f0014000 { +- pinctrl-0 = <&pinctrl_i2c0_pu>; +- status = "okay"; +- }; +- +- i2c1: i2c@f0018000 { +- status = "okay"; +- +- pmic: act8865@5b { +- compatible = "active-semi,act8865"; +- reg = <0x5b>; +- status = "disabled"; +- +- regulators { +- vcc_1v8_reg: DCDC_REG1 { +- regulator-name = "VCC_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcc_1v2_reg: DCDC_REG2 { +- regulator-name = "VCC_1V2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vcc_3v3_reg: DCDC_REG3 { +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vddfuse_reg: LDO_REG1 { +- regulator-name = "FUSE_2V5"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- }; +- +- vddana_reg: LDO_REG2 { +- regulator-name = "VDDANA"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +- }; +- +- macb0: ethernet@f0028000 { +- phy-mode = "rgmii-rxid"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- ethernet-phy@7 { +- reg = <0x7>; +- }; +- }; +- +- pwm0: pwm@f002c000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_pwmh0_0 &pinctrl_pwm0_pwmh1_0>; +- status = "okay"; +- }; +- +- usart0: serial@f001c000 { +- status = "okay"; +- }; +- +- usart1: serial@f0020000 { +- pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; +- status = "okay"; +- }; +- +- uart0: serial@f0024000 { +- status = "okay"; +- }; +- +- mmc1: mmc@f8000000 { +- pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; +- status = "okay"; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioE 1 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- spi1: spi@f8008000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_cs>; +- cs-gpios = <&pioC 25 0>; +- status = "okay"; +- }; +- +- adc0: adc@f8018000 { +- atmel,adc-vref = <3300>; +- atmel,adc-channels-used = <0xfe>; +- pinctrl-0 = < +- &pinctrl_adc0_adtrg +- &pinctrl_adc0_ad1 +- &pinctrl_adc0_ad2 +- &pinctrl_adc0_ad3 +- &pinctrl_adc0_ad4 +- &pinctrl_adc0_ad5 +- &pinctrl_adc0_ad6 +- &pinctrl_adc0_ad7 +- >; +- status = "okay"; +- }; +- +- i2c2: i2c@f801c000 { +- dmas = <0>, <0>; /* Do not use DMA for i2c2 */ +- pinctrl-0 = <&pinctrl_i2c2_pu>; +- status = "okay"; +- }; +- +- macb1: ethernet@f802c000 { +- phy-mode = "rmii"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- ethernet-phy@1 { +- reg = <0x1>; +- }; +- }; +- +- dbgu: serial@ffffee00 { +- status = "okay"; +- }; +- +- pinctrl@fffff200 { +- board { +- pinctrl_i2c0_pu: i2c0_pu { +- atmel,pins = +- , +- ; +- }; +- +- pinctrl_i2c2_pu: i2c2_pu { +- atmel,pins = +- , +- ; +- }; +- +- pinctrl_key_gpio: key_gpio_0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_mmc0_cd: mmc0_cd { +- atmel,pins = +- ; +- }; +- +- pinctrl_mmc1_cd: mmc1_cd { +- atmel,pins = +- ; +- }; +- +- pinctrl_usba_vbus: usba_vbus { +- atmel,pins = +- ; /* PE9, conflicts with A9 */ +- }; +- pinctrl_usb_default: usb_default { +- atmel,pins = +- ; +- }; +- +- pinctrl_gpio_leds: gpio_leds_default { +- atmel,pins = +- ; +- }; +- +- pinctrl_spi0_cs: spi0_cs_default { +- atmel,pins = +- ; +- }; +- +- pinctrl_spi1_cs: spi1_cs_default { +- atmel,pins = ; +- }; +- +- pinctrl_vcc_mmc0_reg_gpio: vcc_mmc0_reg_gpio_default { +- atmel,pins = ; +- }; +- }; +- }; +- }; +- +- usb0: gadget@500000 { +- atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; /* PE9, conflicts with A9 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usba_vbus>; +- status = "okay"; +- }; +- +- usb1: ohci@600000 { +- num-ports = <3>; +- atmel,vbus-gpio = <0 +- &pioE 3 GPIO_ACTIVE_LOW +- &pioE 4 GPIO_ACTIVE_LOW +- >; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_default>; +- status = "okay"; +- }; +- +- usb2: ehci@700000 { +- status = "okay"; +- }; +- +- ebi: ebi@10000000 { +- pinctrl-0 = <&pinctrl_ebi_nand_addr>; +- pinctrl-names = "default"; +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- +- nand@3 { +- reg = <0x3 0x0 0x2>; +- atmel,rb = <0>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x40000>; +- }; +- +- bootloader@40000 { +- label = "bootloader"; +- reg = <0x40000 0xc0000>; +- }; +- +- bootloaderenvred@100000 { +- label = "bootloader env redundant"; +- reg = <0x100000 0x40000>; +- }; +- +- bootloaderenv@140000 { +- label = "bootloader env"; +- reg = <0x140000 0x40000>; +- }; +- +- dtb@180000 { +- label = "device tree"; +- reg = <0x180000 0x80000>; +- }; +- +- kernel@200000 { +- label = "kernel"; +- reg = <0x200000 0x600000>; +- }; +- +- rootfs@800000 { +- label = "rootfs"; +- reg = <0x800000 0x0f800000>; +- }; +- }; +- }; +- }; +- }; +- }; +- +- vcc_mmc0_reg: fixedregulator_mmc0 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_vcc_mmc0_reg_gpio>; +- gpio = <&pioE 2 GPIO_ACTIVE_LOW>; +- regulator-name = "mmc0-card-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_key_gpio>; +- +- bp3 { +- label = "PB_USER"; +- gpios = <&pioE 29 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- status = "okay"; +- +- d2 { +- label = "d2"; +- gpios = <&pioE 23 GPIO_ACTIVE_LOW>; /* PE23, conflicts with A23, CTS2 */ +- linux,default-trigger = "heartbeat"; +- }; +- +- d3 { +- label = "d3"; /* Conflict with EBI CS0, USART2 CTS. */ +- gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-sama5d4_ma5d4.dtsi b/scripts/dtc/include-prefixes/arm/at91-sama5d4_ma5d4.dtsi +deleted file mode 100644 +index 710cb72bda5a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-sama5d4_ma5d4.dtsi ++++ /dev/null +@@ -1,136 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2015 Marek Vasut +- */ +- +-#include "sama5d4.dtsi" +- +-/ { +- model = "Aries/DENX MA5D4"; +- compatible = "aries,ma5d4", "denx,ma5d4", "atmel,sama5d4", "atmel,sama5"; +- +- memory@20000000 { +- reg = <0x20000000 0x10000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- +- clk20m: clk20m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <20000000>; +- clock-output-names = "clk20m"; +- }; +- }; +- +- ahb { +- apb { +- mmc0: mmc@f8000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; +- vmmc-supply = <&vcc_mmc0_reg>; +- vqmmc-supply = <&vcc_3v3_reg>; +- status = "okay"; +- slot@0 { +- reg = <0>; +- bus-width = <8>; +- broken-cd; +- }; +- }; +- +- spi0: spi@f8010000 { +- cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; +- status = "okay"; +- +- m25p80@0 { +- compatible = "atmel,at25df321a"; +- spi-max-frequency = <50000000>; +- reg = <0>; +- }; +- }; +- +- i2c0: i2c@f8014000 { +- status = "okay"; +- }; +- +- spi1: spi@fc018000 { +- cs-gpios = <&pioB 22 0>, <&pioB 23 0>, <0>, <0>; +- status = "okay"; +- +- can0: can@0 { +- compatible = "microchip,mcp2515"; +- reg = <0>; +- clocks = <&clk20m>; +- interrupt-parent = <&pioE>; +- interrupts = <6 IRQ_TYPE_EDGE_RISING>; +- spi-max-frequency = <10000000>; +- }; +- +- can1: can@1 { +- compatible = "microchip,mcp2515"; +- reg = <1>; +- clocks = <&clk20m>; +- interrupt-parent = <&pioE>; +- interrupts = <7 IRQ_TYPE_EDGE_RISING>; +- spi-max-frequency = <10000000>; +- }; +- }; +- +- tcb2: timer@fc024000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>; +- }; +- +- timer@1 { +- compatible = "atmel,tcb-timer"; +- reg = <1>; +- }; +- }; +- +- adc0: adc@fc034000 { +- pinctrl-names = "default"; +- pinctrl-0 = < +- /* external trigger conflicts with USBA_VBUS */ +- &pinctrl_adc0_ad0 +- &pinctrl_adc0_ad1 +- &pinctrl_adc0_ad2 +- &pinctrl_adc0_ad3 +- &pinctrl_adc0_ad4 +- >; +- atmel,adc-vref = <3300>; +- status = "okay"; +- }; +- +- watchdog@fc068640 { +- status = "okay"; +- }; +- }; +- }; +- +- vcc_3v3_reg: fixedregulator_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC 3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcc_mmc0_reg: fixedregulator_mmc0 { +- compatible = "regulator-fixed"; +- gpio = <&pioE 15 GPIO_ACTIVE_HIGH>; +- regulator-name = "RST_n MCI0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc_3v3_reg>; +- regulator-boot-on; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-sama5d4_ma5d4evk.dts b/scripts/dtc/include-prefixes/arm/at91-sama5d4_ma5d4evk.dts +deleted file mode 100644 +index 4d7cee569ff2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-sama5d4_ma5d4evk.dts ++++ /dev/null +@@ -1,164 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2015 Marek Vasut +- */ +- +-/dts-v1/; +-#include "at91-sama5d4_ma5d4.dtsi" +- +-/ { +- model = "Aries/DENX MA5D4EVK"; +- compatible = "aries,ma5d4evk", "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5"; +- +- chosen { +- stdout-path = "serial3:115200n8"; +- }; +- +- ahb { +- usb0: gadget@400000 { +- atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usba_vbus>; +- status = "okay"; +- }; +- +- usb1: ohci@500000 { +- num-ports = <3>; +- atmel,vbus-gpio = <0 +- &pioE 11 GPIO_ACTIVE_LOW +- &pioE 14 GPIO_ACTIVE_LOW +- >; +- status = "okay"; +- }; +- +- usb2: ehci@600000 { +- status = "okay"; +- }; +- +- apb { +- hlcdc: hlcdc@f0000000 { +- status = "okay"; +- +- hlcdc-display-controller { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; +- +- port@0 { +- hlcdc_panel_output: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_input>; +- }; +- }; +- }; +- +- }; +- +- macb0: ethernet@f8020000 { +- phy-mode = "rmii"; +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- usart0: serial@f802c000 { +- status = "okay"; +- }; +- +- usart1: serial@f8030000 { +- status = "okay"; +- }; +- +- mmc1: mmc@fc000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; +- vmmc-supply = <&vcc_mmc1_reg>; +- vqmmc-supply = <&vcc_3v3_reg>; +- status = "okay"; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioE 5 0>; +- }; +- }; +- +- adc0: adc@fc034000 { +- atmel,adc-ts-wires = <4>; +- atmel,adc-ts-pressure-threshold = <10000>; +- }; +- +- +- pinctrl@fc06a000 { +- board { +- pinctrl_mmc1_cd: mmc1_cd { +- atmel,pins = ; +- }; +- pinctrl_usba_vbus: usba_vbus { +- atmel,pins = +- ; +- }; +- }; +- }; +- }; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&hlcdc_pwm 0 50000 0>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- status = "okay"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- status = "okay"; +- +- user1 { +- label = "user1"; +- gpios = <&pioD 28 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- user2 { +- label = "user2"; +- gpios = <&pioD 29 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- user3 { +- label = "user3"; +- gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- panel: panel { +- /* Actually Ampire 800480R2 */ +- compatible = "foxlink,fl500wvr00-a0t"; +- backlight = <&backlight>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- panel_input: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&hlcdc_panel_output>; +- }; +- }; +- }; +- +- vcc_mmc1_reg: fixedregulator_mmc1 { +- compatible = "regulator-fixed"; +- gpio = <&pioE 17 GPIO_ACTIVE_LOW>; +- regulator-name = "VDD MCI1"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc_3v3_reg>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-sama5d4_xplained.dts b/scripts/dtc/include-prefixes/arm/at91-sama5d4_xplained.dts +deleted file mode 100644 +index d241c24f0d83..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-sama5d4_xplained.dts ++++ /dev/null +@@ -1,298 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * at91-sama5d4_xplained.dts - Device Tree file for SAMA5D4 Xplained board +- * +- * Copyright (C) 2015 Atmel, +- * 2015 Josh Wu +- */ +-/dts-v1/; +-#include "sama5d4.dtsi" +-#include +- +-/ { +- model = "Atmel SAMA5D4 Xplained"; +- compatible = "atmel,sama5d4-xplained", "atmel,sama5d4", "atmel,sama5"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x20000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- ahb { +- apb { +- uart0: serial@f8004000 { +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "okay"; +- }; +- +- i2c0: i2c@f8014000 { +- i2c-digital-filter; +- status = "okay"; +- }; +- +- macb0: ethernet@f8020000 { +- phy-mode = "rmii"; +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; +- +- phy0: ethernet-phy@1 { +- interrupt-parent = <&pioE>; +- interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +- reg = <1>; +- }; +- }; +- +- mmc1: mmc@fc000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; +- vmmc-supply = <&vcc_mmc1_reg>; +- vqmmc-supply = <&vcc_3v3_reg>; +- status = "okay"; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioE 3 0>; +- }; +- }; +- +- usart3: serial@fc00c000 { +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "okay"; +- }; +- +- usart4: serial@fc010000 { +- status = "okay"; +- }; +- +- spi1: spi@fc018000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0_cs>; +- cs-gpios = <&pioB 21 0>; +- status = "okay"; +- }; +- +- tcb2: timer@fc024000 { +- timer0: timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>; +- }; +- +- timer1: timer@1 { +- compatible = "atmel,tcb-timer"; +- reg = <1>; +- }; +- }; +- +- adc0: adc@fc034000 { +- pinctrl-names = "default"; +- pinctrl-0 = < +- /* external trigger conflicts with USBA_VBUS */ +- &pinctrl_adc0_ad0 +- &pinctrl_adc0_ad1 +- &pinctrl_adc0_ad2 +- &pinctrl_adc0_ad3 +- &pinctrl_adc0_ad4 +- >; +- atmel,adc-vref = <3300>; +- status = "okay"; +- }; +- +- watchdog@fc068640 { +- status = "okay"; +- }; +- +- pinctrl@fc06a000 { +- board { +- pinctrl_mmc1_cd: mmc1_cd { +- atmel,pins = +- ; +- }; +- pinctrl_usba_vbus: usba_vbus { +- atmel,pins = +- ; +- }; +- pinctrl_usb_default: usb_default { +- atmel,pins = +- ; +- }; +- pinctrl_key_gpio: key_gpio_0 { +- atmel,pins = +- ; +- }; +- pinctrl_macb0_phy_irq: macb0_phy_irq_0 { +- atmel,pins = +- ; +- }; +- pinctrl_spi0_cs: spi0_cs_default { +- atmel,pins = +- ; +- }; +- pinctrl_gpio_leds: gpio_leds_default { +- atmel,pins = +- ; +- }; +- pinctrl_vcc_mmc1_reg: vcc_mmc1_reg { +- atmel,pins = +- ; +- }; +- }; +- }; +- }; +- +- usb0: gadget@400000 { +- atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usba_vbus>; +- status = "okay"; +- }; +- +- usb1: ohci@500000 { +- num-ports = <3>; +- atmel,vbus-gpio = <0 +- &pioE 11 GPIO_ACTIVE_HIGH +- &pioE 14 GPIO_ACTIVE_HIGH +- >; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_default>; +- status = "okay"; +- }; +- +- usb2: ehci@600000 { +- status = "okay"; +- }; +- +- ebi: ebi@10000000 { +- pinctrl-0 = <&pinctrl_ebi_cs3 &pinctrl_ebi_nrd_nandoe +- &pinctrl_ebi_nwe_nandwe &pinctrl_ebi_nandrdy +- &pinctrl_ebi_data_0_7 &pinctrl_ebi_nand_addr>; +- pinctrl-names = "default"; +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- +- nand@3 { +- reg = <0x3 0x0 0x2>; +- atmel,rb = <0>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x40000>; +- }; +- +- bootloader@40000 { +- label = "bootloader"; +- reg = <0x40000 0xc0000>; +- }; +- +- bootloaderenvred@100000 { +- label = "bootloader env redundant"; +- reg = <0x100000 0x40000>; +- }; +- +- bootloaderenv@140000 { +- label = "bootloader env"; +- reg = <0x140000 0x40000>; +- }; +- +- dtb@180000 { +- label = "device tree"; +- reg = <0x180000 0x80000>; +- }; +- +- kernel@200000 { +- label = "kernel"; +- reg = <0x200000 0x600000>; +- }; +- +- rootfs@800000 { +- label = "rootfs"; +- reg = <0x800000 0x1f800000>; +- }; +- }; +- }; +- }; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_key_gpio>; +- +- pb_user1 { +- label = "pb_user1"; +- gpios = <&pioE 8 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- status = "okay"; +- +- d8 { +- label = "d8"; +- gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- d10 { +- label = "d10"; +- gpios = <&pioE 15 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- vcc_3v3_reg: fixedregulator_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC 3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcc_mmc1_reg: fixedregulator_mmc1 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_vcc_mmc1_reg>; +- gpio = <&pioE 4 GPIO_ACTIVE_LOW>; +- regulator-name = "VDD MCI1"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc_3v3_reg>; +- regulator-always-on; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-sama5d4ek.dts b/scripts/dtc/include-prefixes/arm/at91-sama5d4ek.dts +deleted file mode 100644 +index fe432b6b7e95..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-sama5d4ek.dts ++++ /dev/null +@@ -1,323 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit +- * +- * Copyright (C) 2014 Atmel, +- * 2014 Nicolas Ferre +- */ +-/dts-v1/; +-#include "sama5d4.dtsi" +- +-/ { +- model = "Atmel SAMA5D4-EK"; +- compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x20000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- ahb { +- apb { +- adc0: adc@fc034000 { +- pinctrl-names = "default"; +- pinctrl-0 = < +- /* external trigger conflicts with USBA_VBUS */ +- &pinctrl_adc0_ad0 +- &pinctrl_adc0_ad1 +- &pinctrl_adc0_ad2 +- &pinctrl_adc0_ad3 +- &pinctrl_adc0_ad4 +- >; +- /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */ +- atmel,adc-vref = <3300>; +- /*atmel,adc-ts-wires = <4>;*/ /* Set up ADC touch screen */ +- status = "okay"; /* Enable ADC IIO support */ +- }; +- +- mmc0: mmc@f8000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioE 5 0>; +- }; +- }; +- +- ssc0: ssc@f8008000 { +- status = "okay"; +- }; +- +- spi0: spi@f8010000 { +- cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; +- status = "okay"; +- m25p80@0 { +- compatible = "atmel,at25df321a"; +- spi-max-frequency = <50000000>; +- reg = <0>; +- }; +- }; +- +- i2c0: i2c@f8014000 { +- status = "okay"; +- +- wm8904: codec@1a { +- compatible = "wlf,wm8904"; +- reg = <0x1a>; +- clocks = <&pmc PMC_TYPE_SYSTEM 10>; +- clock-names = "mclk"; +- }; +- +- qt1070:keyboard@1b { +- compatible = "qt1070"; +- reg = <0x1b>; +- interrupt-parent = <&pioE>; +- interrupts = <25 0x0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_qt1070_irq>; +- wakeup-source; +- }; +- +- touchscreen@4c { +- compatible = "atmel,maxtouch"; +- reg = <0x4c>; +- interrupt-parent = <&pioE>; +- interrupts = <24 0x0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mxt_ts>; +- }; +- }; +- +- macb0: ethernet@f8020000 { +- pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; +- phy-mode = "rmii"; +- status = "okay"; +- +- ethernet-phy@1 { +- reg = <0x1>; +- interrupt-parent = <&pioE>; +- interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +- +- mmc1: mmc@fc000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; +- status = "okay"; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioE 6 0>; +- }; +- }; +- +- usart2: serial@fc008000 { +- status = "okay"; +- }; +- +- usart3: serial@fc00c000 { +- status = "okay"; +- }; +- +- usart4: serial@fc010000 { +- status = "okay"; +- }; +- +- tcb2: timer@fc024000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>; +- }; +- +- timer@1 { +- compatible = "atmel,tcb-timer"; +- reg = <1>; +- }; +- }; +- +- watchdog@fc068640 { +- status = "okay"; +- }; +- +- pinctrl@fc06a000 { +- board { +- pinctrl_macb0_phy_irq: macb0_phy_irq { +- atmel,pins = +- ; +- }; +- pinctrl_mmc0_cd: mmc0_cd { +- atmel,pins = +- ; +- }; +- pinctrl_mmc1_cd: mmc1_cd { +- atmel,pins = +- ; +- }; +- pinctrl_pck2_as_audio_mck: pck2_as_audio_mck { +- atmel,pins = +- ; +- }; +- pinctrl_usba_vbus: usba_vbus { +- atmel,pins = +- ; +- }; +- pinctrl_key_gpio: key_gpio_0 { +- atmel,pins = +- ; /* PE13 gpio */ +- }; +- pinctrl_qt1070_irq: qt1070_irq { +- atmel,pins = +- ; +- }; +- pinctrl_mxt_ts: mxt_irq { +- atmel,pins = +- ; +- }; +- }; +- }; +- }; +- +- usb0: gadget@400000 { +- atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usba_vbus>; +- status = "okay"; +- }; +- +- usb1: ohci@500000 { +- num-ports = <3>; +- atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */ +- &pioE 11 GPIO_ACTIVE_LOW +- &pioE 12 GPIO_ACTIVE_LOW +- >; +- status = "okay"; +- }; +- +- usb2: ehci@600000 { +- status = "okay"; +- }; +- +- ebi: ebi@10000000 { +- pinctrl-0 = <&pinctrl_ebi_cs3 &pinctrl_ebi_nrd_nandoe +- &pinctrl_ebi_nwe_nandwe &pinctrl_ebi_nandrdy +- &pinctrl_ebi_data_0_7 &pinctrl_ebi_nand_addr>; +- pinctrl-names = "default"; +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- +- nand@3 { +- reg = <0x3 0x0 0x2>; +- atmel,rb = <0>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x40000>; +- }; +- +- bootloader@40000 { +- label = "bootloader"; +- reg = <0x40000 0x80000>; +- }; +- +- bootloaderenv@c0000 { +- label = "bootloader env"; +- reg = <0xc0000 0xc0000>; +- }; +- +- dtb@180000 { +- label = "device tree"; +- reg = <0x180000 0x80000>; +- }; +- +- kernel@200000 { +- label = "kernel"; +- reg = <0x200000 0x600000>; +- }; +- +- rootfs@800000 { +- label = "rootfs"; +- reg = <0x800000 0x0f800000>; +- }; +- }; +- }; +- }; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_key_gpio>; +- +- pb_user1 { +- label = "pb_user1"; +- gpios = <&pioE 13 GPIO_ACTIVE_HIGH>; +- linux,code = <0x100>; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- status = "okay"; +- +- d8 { +- label = "d8"; +- /* PE28, conflicts with usart4 rts pin */ +- gpios = <&pioE 28 GPIO_ACTIVE_LOW>; +- }; +- +- d9 { +- label = "d9"; +- gpios = <&pioE 9 GPIO_ACTIVE_HIGH>; +- }; +- +- d10 { +- label = "d10"; +- gpios = <&pioE 8 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- sound { +- compatible = "atmel,asoc-wm8904"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pck2_as_audio_mck>; +- +- atmel,model = "wm8904 @ SAMA5D4EK"; +- atmel,audio-routing = +- "Headphone Jack", "HPOUTL", +- "Headphone Jack", "HPOUTR", +- "IN1L", "Line In Jack", +- "IN1R", "Line In Jack"; +- +- atmel,ssc-controller = <&ssc0>; +- atmel,audio-codec = <&wm8904>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-sama7g5ek.dts b/scripts/dtc/include-prefixes/arm/at91-sama7g5ek.dts +deleted file mode 100644 +index f3d6aaa3a78d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-sama7g5ek.dts ++++ /dev/null +@@ -1,689 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * at91-sama7g5ek.dts - Device Tree file for SAMA7G5-EK board +- * +- * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries +- * +- * Author: Eugen Hristev +- * Author: Claudiu Beznea +- * +- */ +-/dts-v1/; +-#include "sama7g5-pinfunc.h" +-#include "sama7g5.dtsi" +-#include +-#include +- +-/ { +- model = "Microchip SAMA7G5-EK"; +- compatible = "microchip,sama7g5ek", "microchip,sama7g5", "microchip,sama7"; +- +- chosen { +- bootargs = "rw root=/dev/mmcblk1p2 rootfstype=ext4 rootwait"; +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- serial0 = &uart3; +- serial1 = &uart4; +- serial2 = &uart7; +- serial3 = &uart0; +- i2c0 = &i2c1; +- i2c1 = &i2c8; +- i2c2 = &i2c9; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <24000000>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_key_gpio_default>; +- +- bp1 { +- label = "PB_USER"; +- gpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led_gpio_default>; +- status = "okay"; /* Conflict with pwm. */ +- +- red_led { +- label = "red"; +- gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; +- }; +- +- green_led { +- label = "green"; +- gpios = <&pioA PIN_PA13 GPIO_ACTIVE_HIGH>; +- }; +- +- blue_led { +- label = "blue"; +- gpios = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- /* 512 M */ +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x20000000>; +- }; +- +- sound: sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "sama7g5ek audio"; +- #address-cells = <1>; +- #size-cells = <0>; +- simple-audio-card,dai-link@0 { +- reg = <0>; +- cpu { +- sound-dai = <&spdiftx>; +- }; +- codec { +- sound-dai = <&spdif_out>; +- }; +- }; +- simple-audio-card,dai-link@1 { +- reg = <1>; +- cpu { +- sound-dai = <&spdifrx>; +- }; +- codec { +- sound-dai = <&spdif_in>; +- }; +- }; +- }; +- +- spdif_in: spdif-in { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dir"; +- }; +- +- spdif_out: spdif-out { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vddcpu>; +-}; +- +-&dma0 { +- status = "okay"; +-}; +- +-&dma1 { +- status = "okay"; +-}; +- +-&dma2 { +- status = "okay"; +-}; +- +-&flx0 { +- atmel,flexcom-mode = ; +- status = "disabled"; +- +- uart0: serial@200 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flx0_default>; +- status = "disabled"; +- }; +-}; +- +-&flx1 { +- atmel,flexcom-mode = ; +- status = "okay"; +- +- i2c1: i2c@600 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1_default>; +- i2c-analog-filter; +- i2c-digital-filter; +- i2c-digital-filter-width-ns = <35>; +- status = "okay"; +- +- mcp16502@5b { +- compatible = "microchip,mcp16502"; +- reg = <0x5b>; +- status = "okay"; +- +- regulators { +- vdd_3v3: VDD_IO { +- regulator-name = "VDD_IO"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3700000>; +- regulator-initial-mode = <2>; +- regulator-allowed-modes = <2>, <4>; +- regulator-always-on; +- +- regulator-state-standby { +- regulator-on-in-suspend; +- regulator-mode = <4>; +- }; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-mode = <4>; +- }; +- }; +- +- vddioddr: VDD_DDR { +- regulator-name = "VDD_DDR"; +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1450000>; +- regulator-initial-mode = <2>; +- regulator-allowed-modes = <2>, <4>; +- regulator-always-on; +- +- regulator-state-standby { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1350000>; +- regulator-mode = <4>; +- }; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1350000>; +- regulator-mode = <4>; +- }; +- }; +- +- vddcore: VDD_CORE { +- regulator-name = "VDD_CORE"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1850000>; +- regulator-initial-mode = <2>; +- regulator-allowed-modes = <2>, <4>; +- regulator-always-on; +- +- regulator-state-standby { +- regulator-on-in-suspend; +- regulator-mode = <4>; +- }; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-mode = <4>; +- }; +- }; +- +- vddcpu: VDD_OTHER { +- regulator-name = "VDD_OTHER"; +- regulator-min-microvolt = <1125000>; +- regulator-max-microvolt = <1850000>; +- regulator-initial-mode = <2>; +- regulator-allowed-modes = <2>, <4>; +- regulator-ramp-delay = <3125>; +- regulator-always-on; +- +- regulator-state-standby { +- regulator-on-in-suspend; +- regulator-mode = <4>; +- }; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-mode = <4>; +- }; +- }; +- +- vldo1: LDO1 { +- regulator-name = "LDO1"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3700000>; +- regulator-always-on; +- +- regulator-state-standby { +- regulator-on-in-suspend; +- }; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vldo2: LDO2 { +- regulator-name = "LDO2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3700000>; +- +- regulator-state-standby { +- regulator-on-in-suspend; +- }; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&flx3 { +- atmel,flexcom-mode = ; +- status = "okay"; +- +- uart3: serial@200 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flx3_default>; +- status = "okay"; +- }; +-}; +- +-&flx4 { +- atmel,flexcom-mode = ; +- status = "okay"; +- +- uart4: serial@200 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flx4_default>; +- status = "okay"; +- }; +-}; +- +-&flx7 { +- atmel,flexcom-mode = ; +- status = "okay"; +- +- uart7: serial@200 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flx7_default>; +- status = "okay"; +- }; +-}; +- +-&flx8 { +- atmel,flexcom-mode = ; +- status = "okay"; +- +- i2c8: i2c@600 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c8_default>; +- i2c-analog-filter; +- i2c-digital-filter; +- i2c-digital-filter-width-ns = <35>; +- status = "okay"; +- }; +-}; +- +-&flx9 { +- atmel,flexcom-mode = ; +- status = "okay"; +- +- i2c9: i2c@600 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c9_default>; +- i2c-analog-filter; +- i2c-digital-filter; +- i2c-digital-filter-width-ns = <35>; +- status = "okay"; +- }; +-}; +- +-&flx11 { +- atmel,flexcom-mode = ; +- status = "okay"; +- +- spi11: spi@400 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mikrobus1_spi &pinctrl_mikrobus1_spi_cs>; +- status = "okay"; +- }; +-}; +- +-&gmac0 { +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gmac0_default +- &pinctrl_gmac0_mdio_default +- &pinctrl_gmac0_txck_default +- &pinctrl_gmac0_phy_irq>; +- phy-mode = "rgmii-id"; +- status = "okay"; +- +- ethernet-phy@7 { +- reg = <0x7>; +- interrupt-parent = <&pioA>; +- interrupts = ; +- }; +-}; +- +-&gmac1 { +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gmac1_default +- &pinctrl_gmac1_mdio_default +- &pinctrl_gmac1_phy_irq>; +- phy-mode = "rmii"; +- status = "okay"; +- +- ethernet-phy@0 { +- reg = <0x0>; +- interrupt-parent = <&pioA>; +- interrupts = ; +- }; +-}; +- +-&i2s0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2s0_default>; +-}; +- +-&pioA { +- pinctrl_flx0_default: flx0_default { +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_flx3_default: flx3_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_flx4_default: flx4_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_flx7_default: flx7_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_gmac0_default: gmac0_default { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- slew-rate = <0>; +- bias-disable; +- }; +- +- pinctrl_gmac0_mdio_default: gmac0_mdio_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_gmac0_txck_default: gmac0_txck_default { +- pinmux = ; +- slew-rate = <0>; +- bias-pull-up; +- }; +- +- pinctrl_gmac0_phy_irq: gmac0_phy_irq { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_gmac1_default: gmac1_default { +- pinmux = , +- , +- , +- , +- , +- , +- , +- ; +- slew-rate = <0>; +- bias-disable; +- }; +- +- pinctrl_gmac1_mdio_default: gmac1_mdio_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_gmac1_phy_irq: gmac1_phy_irq { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_i2c1_default: i2c1_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_i2c8_default: i2c8_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_i2c9_default: i2c9_default { +- pinmux = , +- ; +- bias-disable; +- }; +- +- pinctrl_i2s0_default: i2s0_default { +- pinmux = , +- , +- , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_key_gpio_default: key_gpio_default { +- pinmux = ; +- bias-pull-up; +- }; +- +- pinctrl_led_gpio_default: led_gpio_default { +- pinmux = , +- , +- ; +- bias-pull-up; +- }; +- +- pinctrl_mikrobus1_an_default: mikrobus1_an_default { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus2_an_default: mikrobus2_an_default { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus1_pwm2_default: mikrobus1_pwm2_default { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus2_pwm3_default: mikrobus2_pwm3_default { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_mikrobus1_spi: mikrobus1_spi { +- pinmux = , +- , +- ; +- bias-disable; +- }; +- +- pinctrl_sdmmc0_default: sdmmc0_default { +- cmd_data { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- ; +- slew-rate = <0>; +- bias-pull-up; +- }; +- +- ck_cd_rstn_vddsel { +- pinmux = , +- , +- ; +- slew-rate = <0>; +- bias-pull-up; +- }; +- }; +- +- pinctrl_sdmmc1_default: sdmmc1_default { +- cmd_data { +- pinmux = , +- , +- , +- , +- ; +- slew-rate = <0>; +- bias-pull-up; +- }; +- +- ck_cd_rstn_vddsel { +- pinmux = , +- , +- , +- ; +- slew-rate = <0>; +- bias-pull-up; +- }; +- }; +- +- pinctrl_sdmmc2_default: sdmmc2_default { +- cmd_data { +- pinmux = , +- , +- , +- , +- ; +- slew-rate = <0>; +- bias-pull-up; +- }; +- +- ck { +- pinmux = ; +- slew-rate = <0>; +- bias-pull-up; +- }; +- }; +- +- pinctrl_spdifrx_default: spdifrx_default { +- pinmux = ; +- bias-disable; +- }; +- +- pinctrl_spdiftx_default: spdiftx_default { +- pinmux = ; +- bias-disable; +- }; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mikrobus1_pwm2_default &pinctrl_mikrobus2_pwm3_default>; +- status = "disabled"; /* Conflict with leds. */ +-}; +- +-&rtt { +- atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +-}; +- +-&sdmmc0 { +- bus-width = <8>; +- non-removable; +- no-1-8-v; +- sdhci-caps-mask = <0x0 0x00200000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdmmc0_default>; +- status = "okay"; +-}; +- +-&sdmmc1 { +- bus-width = <4>; +- no-1-8-v; +- sdhci-caps-mask = <0x0 0x00200000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdmmc1_default>; +- status = "okay"; +-}; +- +-&sdmmc2 { +- bus-width = <4>; +- no-1-8-v; +- sdhci-caps-mask = <0x0 0x00200000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdmmc2_default>; +-}; +- +-&shdwc { +- atmel,shdwc-debouncer = <976>; +- status = "okay"; +- +- input@0 { +- reg = <0>; +- }; +-}; +- +-&spdifrx { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spdifrx_default>; +- status = "okay"; +-}; +- +-&spdiftx { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spdiftx_default>; +- status = "okay"; +-}; +- +-&trng { +- status = "okay"; +-}; +- +-&vddout25 { +- vin-supply = <&vdd_3v3>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-smartkiz.dts b/scripts/dtc/include-prefixes/arm/at91-smartkiz.dts +deleted file mode 100644 +index b76a6b5ac464..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-smartkiz.dts ++++ /dev/null +@@ -1,107 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2017-2018 Overkiz SAS +- * Author: Mickael Gardet +- * Kévin Raymond +- * Dorian Rocipon +- */ +-/dts-v1/; +-#include "at91-kizboxmini-common.dtsi" +- +-/ { +- model = "Overkiz SmartKiz"; +- compatible = "overkiz,smartkiz", "atmel,at91sam9g25", +- "atmel,at91sam9x5", "atmel,at91sam9"; +- +- clocks { +- adc_op_clk { +- status = "okay"; +- }; +- }; +- +- aliases { +- serial5 = &uart0; +- }; +- +- pio_keys { +- hk_reset { +- label = "HK_RESET"; +- gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; +- }; +- +- power_rf { +- label = "POWER_RF"; +- gpios = <&pioA 20 GPIO_ACTIVE_HIGH>; +- }; +- +- power_wifi { +- label = "POWER_WIFI"; +- gpios = <&pioA 21 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&pinctrl { +- i2c1 { +- pinctrl_i2c1: i2c1-0 { +- atmel,pins = +- ; +- }; +- }; +- +- adc0 { +- pinctrl_adc0_ad0: adc0_ad0-0 { +- /* pull-up disable */ +- atmel,pins = ; +- }; +- pinctrl_adc0_ad5: adc0_ad5-0 { +- /* pull-up disable */ +- atmel,pins = ; +- }; +- pinctrl_adc0_ad6: adc0_ad6-0 { +- /* pull-up disable */ +- atmel,pins = ; +- }; +- pinctrl_adc0_ad11: adc0_ad11-0 { +- /* pull-up disable */ +- atmel,pins = ; +- }; +- }; +-}; +- +-&i2c1 { +- dmas = <0>, <0>; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "disabled"; +-}; +- +-&macb0 { +- status = "disabled"; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&led_blue { +- status = "okay"; +-}; +- +-&adc0 { +- atmel,adc-vref = <2500>; +- pinctrl-names = "default"; +- pinctrl-0 = < +- &pinctrl_adc0_ad0 +- &pinctrl_adc0_ad5 +- &pinctrl_adc0_ad6 +- &pinctrl_adc0_ad11 +- >; +- atmel,adc-channels-used = <0x0861>; +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/at91-som60.dtsi b/scripts/dtc/include-prefixes/arm/at91-som60.dtsi +deleted file mode 100644 +index 39474a112b16..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-som60.dtsi ++++ /dev/null +@@ -1,230 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * at91-som60.dtsi - Device Tree file for the SOM60 module +- * +- * Copyright (C) 2018 Laird, +- * 2018 Ben Whitten +- * +- */ +-#include "sama5d36.dtsi" +- +-/ { +- model = "Laird SOM60"; +- compatible = "laird,som60", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; +- +- chosen { +- stdout-path = &dbgu; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x8000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +-}; +- +-&pinctrl { +- board { +- pinctrl_mmc0_cd: mmc0_cd { +- atmel,pins = +- ; +- }; +- +- pinctrl_mmc0_en: mmc0_en { +- atmel,pins = +- ; +- }; +- +- pinctrl_nand0_wp: nand0_wp { +- atmel,pins = +- ; +- }; +- +- pinctrl_usb_vbus: usb_vbus { +- atmel,pins = +- ; +- /* Conflicts with USART2_SCK */ +- }; +- +- pinctrl_usart2_sck: usart2_sck { +- atmel,pins = +- ; +- /* Conflicts with USB_VBUS */ +- }; +- +- pinctrl_usb_oc: usb_oc { +- atmel,pins = +- ; +- /* Conflicts with USART3_SCK */ +- }; +- +- pinctrl_usart3_sck: usart3_sck { +- atmel,pins = +- ; +- /* Conflicts with USB_OC */ +- }; +- +- pinctrl_usba_vbus: usba_vbus { +- atmel,pins = +- ; +- }; +- +- pinctrl_geth_int: geth_int { +- atmel,pins = +- ; +- /* Conflicts with USART1_SCK */ +- }; +- +- pinctrl_usart1_sck: usart1_sck { +- atmel,pins = +- ; +- /* Conflicts with GETH_INT */ +- }; +- +- pinctrl_eth_int: eth_int { +- atmel,pins = +- ; +- }; +- +- pinctrl_pck2_as_audio_mck: pck2_as_audio_mck { +- atmel,pins = +- ; +- }; +- }; +-}; +- +-&mmc0 { +- slot@0 { +- reg = <0>; +- bus-width = <8>; +- }; +-}; +- +-&mmc1 { +- status = "okay"; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- }; +-}; +- +-&spi0 { +- cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; +-}; +- +-&usart0 { +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "okay"; +- pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>; +-}; +- +-&usart1 { +- pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; +-}; +- +-&usart2 { +- pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts_cts>; +-}; +- +-&usart3 { +- pinctrl-0 = <&pinctrl_usart3 &pinctrl_usart3_rts_cts>; +-}; +- +-&adc0 { +- pinctrl-0 = < +- &pinctrl_adc0_adtrg +- &pinctrl_adc0_ad0 +- &pinctrl_adc0_ad1 +- &pinctrl_adc0_ad2 +- &pinctrl_adc0_ad3 +- &pinctrl_adc0_ad4 +- &pinctrl_adc0_ad5 +- >; +-}; +- +-&macb0 { +- phy-mode = "rgmii"; +-}; +- +-&macb1 { +- phy-mode = "rmii"; +-}; +- +-&ebi { +- pinctrl-0 = <&pinctrl_ebi_nand_addr>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand: nand@3 { +- reg = <0x3 0x0 0x2>; +- atmel,rb = <0>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <8>; +- nand-ecc-step-size = <512>; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ubootspl@0 { +- label = "u-boot-spl"; +- reg = <0x0 0x20000>; +- }; +- +- uboot@20000 { +- label = "u-boot"; +- reg = <0x20000 0x80000>; +- }; +- +- ubootenv@a0000 { +- label = "u-boot-env"; +- reg = <0xa0000 0x20000>; +- }; +- +- ubootenv@c0000 { +- label = "u-boot-env"; +- reg = <0xc0000 0x20000>; +- }; +- +- ubi@e0000 { +- label = "ubi"; +- reg = <0xe0000 0xfe00000>; +- }; +- }; +- }; +-}; +- +-&usb0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usba_vbus>; +- atmel,vbus-gpio = <&pioC 14 GPIO_ACTIVE_HIGH>; +-}; +- +-&usb1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_vbus &pinctrl_usb_oc>; +- num-ports = <3>; +- atmel,vbus-gpio = <0 +- &pioE 20 GPIO_ACTIVE_HIGH +- 0>; +- atmel,oc-gpio = <0 +- &pioE 15 GPIO_ACTIVE_LOW +- 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-tse850-3.dts b/scripts/dtc/include-prefixes/arm/at91-tse850-3.dts +deleted file mode 100644 +index 7e5c598e7e68..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-tse850-3.dts ++++ /dev/null +@@ -1,302 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91-tse850-3.dts - Device Tree file for the Axentia TSE-850 3.0 board +- * +- * Copyright (C) 2017 Axentia Technologies AB +- * +- * Author: Peter Rosin +- */ +-/dts-v1/; +-#include +-#include "at91-linea.dtsi" +- +-/ { +- model = "Axentia TSE-850 3.0"; +- compatible = "axentia,tse850v3", "axentia,linea", +- "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; +- +- sck: oscillator { +- compatible = "fixed-clock"; +- +- #clock-cells = <0>; +- clock-frequency = <16000000>; +- clock-output-names = "sck"; +- }; +- +- reg_3v3: regulator { +- compatible = "regulator-fixed"; +- +- regulator-name = "3v3-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ana: reg-ana { +- compatible = "pwm-regulator"; +- +- regulator-name = "ANA"; +- +- pwms = <&pwm0 2 1000 PWM_POLARITY_INVERTED>; +- pwm-dutycycle-unit = <1000>; +- pwm-dutycycle-range = <100 1000>; +- +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <20000000>; +- regulator-ramp-delay = <1000>; +- }; +- +- sound { +- compatible = "axentia,tse850-pcm5142"; +- +- axentia,cpu-dai = <&ssc0>; +- axentia,audio-codec = <&pcm5142>; +- +- axentia,add-gpios = <&pioA 8 GPIO_ACTIVE_LOW>; +- axentia,loop1-gpios = <&pioA 10 GPIO_ACTIVE_LOW>; +- axentia,loop2-gpios = <&pioA 11 GPIO_ACTIVE_LOW>; +- +- axentia,ana-supply = <&ana>; +- }; +- +- dac: dpot-dac { +- compatible = "dpot-dac"; +- vref-supply = <®_3v3>; +- io-channels = <&dpot 0>; +- io-channel-names = "dpot"; +- #io-channel-cells = <1>; +- }; +- +- env_det: envelope-detector { +- compatible = "axentia,tse850-envelope-detector"; +- io-channels = <&dac 0>; +- io-channel-names = "dac"; +- #io-channel-cells = <1>; +- +- interrupt-parent = <&pioA>; +- interrupts = <3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "comp"; +- }; +- +- mux: mux-controller { +- compatible = "gpio-mux"; +- #mux-control-cells = <0>; +- +- mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>, +- <&pioA 1 GPIO_ACTIVE_HIGH>, +- <&pioA 2 GPIO_ACTIVE_HIGH>; +- idle-state = <0>; +- }; +- +- envelope-detector-mux { +- compatible = "io-channel-mux"; +- io-channels = <&env_det 0>; +- io-channel-names = "parent"; +- +- mux-controls = <&mux>; +- +- channels = "", "", +- "sync-1", +- "in", +- "out", +- "sync-2", +- "sys-reg", +- "ana-reg"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- ch1-red { +- label = "ch-1:red"; +- gpios = <&pioA 23 GPIO_ACTIVE_LOW>; +- }; +- ch1-green { +- label = "ch-1:green"; +- gpios = <&pioA 22 GPIO_ACTIVE_LOW>; +- }; +- ch2-red { +- label = "ch-2:red"; +- gpios = <&pioA 21 GPIO_ACTIVE_LOW>; +- }; +- ch2-green { +- label = "ch-2:green"; +- gpios = <&pioA 20 GPIO_ACTIVE_LOW>; +- }; +- data-red { +- label = "data:red"; +- gpios = <&pioA 19 GPIO_ACTIVE_LOW>; +- }; +- data-green { +- label = "data:green"; +- gpios = <&pioA 18 GPIO_ACTIVE_LOW>; +- }; +- alarm-red { +- label = "alarm:red"; +- gpios = <&pioA 17 GPIO_ACTIVE_LOW>; +- }; +- alarm-green { +- label = "alarm:green"; +- gpios = <&pioA 16 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&nand { +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x40000>; +- }; +- +- barebox@40000 { +- label = "bootloader"; +- reg = <0x40000 0x60000>; +- }; +- +- bareboxenv@c0000 { +- label = "bareboxenv"; +- reg = <0xc0000 0x40000>; +- }; +- +- bareboxenv2@100000 { +- label = "bareboxenv2"; +- reg = <0x100000 0x40000>; +- }; +- +- oftree@180000 { +- label = "oftree"; +- reg = <0x180000 0x20000>; +- }; +- +- kernel@200000 { +- label = "kernel"; +- reg = <0x200000 0x500000>; +- }; +- +- rootfs@800000 { +- label = "rootfs"; +- reg = <0x800000 0x0f800000>; +- }; +- +- ovlfs@10000000 { +- label = "ovlfs"; +- reg = <0x10000000 0x10000000>; +- }; +- }; +-}; +- +-&ssc0 { +- #sound-dai-cells = <0>; +- +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- jc42@18 { +- compatible = "nxp,se97b", "jedec,jc-42.4-temp"; +- reg = <0x18>; +- smbus-timeout-disable; +- }; +- +- dpot: mcp4651-104@28 { +- compatible = "microchip,mcp4651-104"; +- reg = <0x28>; +- #io-channel-cells = <1>; +- }; +- +- pcm5142: pcm5142@4c { +- compatible = "ti,pcm5142"; +- +- reg = <0x4c>; +- #sound-dai-cells = <0>; +- +- AVDD-supply = <®_3v3>; +- DVDD-supply = <®_3v3>; +- CPVDD-supply = <®_3v3>; +- +- clocks = <&sck>; +- +- pll-in = <3>; +- pll-out = <6>; +- }; +- +- eeprom@50 { +- compatible = "nxp,se97b", "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +-}; +- +-&pinctrl { +- tse850 { +- pinctrl_usba_vbus: usba-vbus { +- atmel,pins = ; +- }; +- }; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-&usart0 { +- status = "okay"; +- +- atmel,use-dma-rx; +-}; +- +-&pwm0 { +- status = "okay"; +- +- pinctrl-0 = <&pinctrl_pwm0_pwml2_1>; +- pinctrl-names = "default"; +-}; +- +-&macb1 { +- status = "okay"; +- +- phy-mode = "rmii"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: ethernet-phy@3 { +- reg = <3>; +- +- interrupt-parent = <&pioE>; +- interrupts = <31 IRQ_TYPE_EDGE_FALLING>; +- }; +-}; +- +-&usb0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usba_vbus>; +- atmel,vbus-gpio = <&pioC 31 GPIO_ACTIVE_HIGH>; +-}; +- +-&usb1 { +- status = "okay"; +- +- num-ports = <1>; +- atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; +- atmel,oc-gpio = <&pioC 15 GPIO_ACTIVE_LOW>; +-}; +- +-&usb2 { +- status = "okay"; +-}; +- +-&dbgu { +- status = "okay"; +- +- dmas = <0>, <0>; /* Do not use DMA for dbgu */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-vinco.dts b/scripts/dtc/include-prefixes/arm/at91-vinco.dts +deleted file mode 100644 +index a51a3372afa1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-vinco.dts ++++ /dev/null +@@ -1,231 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for VInCo platform +- * +- * Copyright (C) 2014 Atmel, +- * 2014 Nicolas Ferre +- * 2015 Gregory CLEMENT +- */ +-/dts-v1/; +-#include "sama5d4.dtsi" +- +-/ { +- model = "L+G VInCo platform"; +- compatible = "l+g,vinco", "atmel,sama5d4", "atmel,sama5"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- ahb { +- apb { +- +- adc0: adc@fc034000 { +- status = "okay"; /* Enable ADC IIO support */ +- }; +- +- mmc0: mmc@f8000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 +- &pinctrl_mmc0_dat1_3 +- &pinctrl_mmc0_dat4_7>; +- vqmmc-supply = <&vcc_3v3_reg>; +- vmmc-supply = <&vcc_3v3_reg>; +- no-1-8-v; +- status = "okay"; +- slot@0 { +- reg = <0>; +- bus-width = <8>; +- non-removable; +- broken-cd; +- status = "okay"; +- }; +- }; +- +- spi0: spi@f8010000 { +- cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; +- status = "okay"; +- m25p80@0 { +- compatible = "n25q32b", "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- reg = <0>; +- }; +- }; +- +- i2c0: i2c@f8014000 { +- status = "okay"; +- }; +- +- i2c1: i2c@f8018000 { +- status = "okay"; +- /* kerkey security module */ +- }; +- +- macb0: ethernet@f8020000 { +- phy-mode = "rmii"; +- status = "okay"; +- +- ethernet-phy@1 { +- reg = <0x1>; +- reset-gpios = <&pioE 8 GPIO_ACTIVE_LOW>; +- interrupt-parent = <&pioB>; +- interrupts = <15 IRQ_TYPE_EDGE_FALLING>; +- }; +- +- }; +- +- i2c2: i2c@f8024000 { +- status = "okay"; +- +- rtc1: rtc@32 { +- compatible = "epson,rx8900"; +- reg = <0x32>; +- }; +- }; +- +- usart2: serial@fc008000 { +- /* MBUS */ +- status = "okay"; +- }; +- +- usart3: serial@fc00c000 { +- /* debug */ +- status = "okay"; +- }; +- +- usart4: serial@fc010000 { +- /* LMN */ +- pinctrl-0 = <&pinctrl_usart4 &pinctrl_usart4_rts>; +- linux,rs485-enabled-at-boot-time; +- status = "okay"; +- }; +- +- tcb2: timer@fc024000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>; +- }; +- +- timer@1 { +- compatible = "atmel,tcb-timer"; +- reg = <1>; +- }; +- }; +- +- macb1: ethernet@fc028000 { +- phy-mode = "rmii"; +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- ethernet-phy@1 { +- reg = <0x1>; +- interrupt-parent = <&pioB>; +- interrupts = <31 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&pioE 6 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- watchdog@fc068640 { +- status = "okay"; +- }; +- +- pinctrl@fc06a000 { +- board { +- pinctrl_usba_vbus: usba_vbus { +- atmel,pins = +- ; +- }; +- }; +- }; +- }; +- +- usb0: gadget@400000 { +- atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usba_vbus>; +- status = "disable"; +- }; +- +- usb1: ohci@500000 { +- num-ports = <3>; +- atmel,vbus-gpio = <0 +- &pioE 11 GPIO_ACTIVE_LOW +- &pioE 12 GPIO_ACTIVE_LOW +- >; +- status = "disable"; +- }; +- +- usb2: ehci@600000 { +- /* 4G Modem */ +- status = "okay"; +- }; +- +- }; +- +- leds { +- compatible = "gpio-leds"; +- status = "okay"; +- +- led_err { +- label = "err"; +- gpios = <&pioA 7 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_rssi { +- label = "rssi"; +- gpios = <&pioA 9 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_tls { +- label = "tls"; +- gpios = <&pioA 24 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_lmc { +- label = "lmc"; +- gpios = <&pioA 25 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_wmt { +- label = "wmt"; +- gpios = <&pioA 29 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_pwr { +- label = "pwr"; +- gpios = <&pioA 26 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- +- }; +- +- vcc_3v3_reg: fixedregulator_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC 3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-wb45n.dts b/scripts/dtc/include-prefixes/arm/at91-wb45n.dts +deleted file mode 100644 +index 54d130c92185..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-wb45n.dts ++++ /dev/null +@@ -1,64 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * at91-wb45n.dts - Device Tree file for WB45NBT board +- * +- * Copyright (C) 2018 Laird +- * +- */ +-/dts-v1/; +-#include "at91-wb45n.dtsi" +- +-/ { +- model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)"; +- compatible = "laird,wb45n", "laird,wbxx", "atmel,at91sam9x5", "atmel,at91sam9"; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- irqbtn@18 { +- reg = <18>; +- label = "IRQBTN"; +- linux,code = <99>; +- gpios = <&pioB 18 GPIO_ACTIVE_LOW>; +- wakeup-source; +- }; +- }; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&mmc0 { +- status = "okay"; +-}; +- +-&spi0 { +- status = "okay"; +-}; +- +-&macb0 { +- status = "okay"; +-}; +- +-&dbgu { +- status = "okay"; +-}; +- +-&usart0 { +- status = "okay"; +-}; +- +-&usart3 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91-wb45n.dtsi b/scripts/dtc/include-prefixes/arm/at91-wb45n.dtsi +deleted file mode 100644 +index 430c75358086..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-wb45n.dtsi ++++ /dev/null +@@ -1,166 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * at91-wb45n.dtsi - Device Tree file for WB45NBT board +- * +- * Copyright (C) 2018 Laird +- * +- */ +- +-#include "at91sam9g25.dtsi" +- +-/ { +- model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)"; +- compatible = "laird,wb45n", "laird,wbxx", "atmel,at91sam9x5", "atmel,at91sam9"; +- +- chosen { +- bootargs = "ubi.mtd=6 root=ubi0:rootfs rootfstype=ubifs rw"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +- +- atheros { +- compatible = "atheros,ath6kl"; +- atheros,board-id = "SD32"; +- }; +-}; +- +-&reset_controller { +- compatible = "atmel,sama5d3-rstc"; +-}; +- +-&shutdown_controller { +- atmel,wakeup-mode = "low"; +-}; +- +-&slow_xtal { +- clock-frequency = <32768>; +-}; +- +-&main_xtal { +- clock-frequency = <12000000>; +-}; +- +-&ebi { +- status = "okay"; +- nand_controller: nand-controller { +- pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb &pinctrl_nand_oe_we>; +- pinctrl-names = "default"; +- status = "okay"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bs"; +- reg = <0x0 0x20000>; +- }; +- +- uboot@20000 { +- label = "u-boot"; +- reg = <0x20000 0x80000>; +- }; +- +- ubootenv@a0000 { +- label = "u-boot-env"; +- reg = <0xa0000 0x20000>; +- }; +- +- ubootenv@c0000 { +- label = "redund-env"; +- reg = <0xc0000 0x20000>; +- }; +- +- kernel-a@e0000 { +- label = "kernel-a"; +- reg = <0xe0000 0x280000>; +- }; +- +- kernel-b@360000 { +- label = "kernel-b"; +- reg = <0x360000 0x280000>; +- }; +- +- rootfs-a@5e0000 { +- label = "rootfs-a"; +- reg = <0x5e0000 0x2600000>; +- }; +- +- rootfs-b@2be0000 { +- label = "rootfs-b"; +- reg = <0x2be0000 0x2600000>; +- }; +- +- user@51e0000 { +- label = "user"; +- reg = <0x51e0000 0x2dc0000>; +- }; +- +- logs@7fa0000 { +- label = "logs"; +- reg = <0x7fa0000 0x60000>; +- }; +- +- }; +- }; +- }; +-}; +- +-&usb0 { +- num-ports = <2>; +- atmel,vbus-gpio = < +- &pioB 12 GPIO_ACTIVE_HIGH +- &pioA 31 GPIO_ACTIVE_HIGH +- >; +- atmel,oc-gpio = <&pioB 13 GPIO_ACTIVE_LOW>; +-}; +- +-&macb0 { +- phy-mode = "rmii"; +-}; +- +-&spi0 { +- cs-gpios = <&pioA 14 0>, <&pioA 7 0>, <0>, <0>; +-}; +- +-&usb2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_board_usb2>; +- atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &pinctrl_mmc0_slot0_clk_cmd_dat0 +- &pinctrl_mmc0_slot0_dat1_3>; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- }; +-}; +- +-&pinctrl { +- usb2 { +- pinctrl_board_usb2: usb2-board { +- atmel,pins = +- ; /* PB11 gpio vbus sense, deglitch */ +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/at91-wb50n.dts b/scripts/dtc/include-prefixes/arm/at91-wb50n.dts +deleted file mode 100644 +index a5e45bb95c04..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-wb50n.dts ++++ /dev/null +@@ -1,112 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * at91-wb50n.dts - Device Tree file for wb50n evaluation board +- * +- * Copyright (C) 2018 Laird +- * +- */ +- +-/dts-v1/; +-#include "at91-wb50n.dtsi" +- +-/ { +- model = "Laird Workgroup Bridge 50N - Atmel SAMA5D"; +- compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- btn0@10 { +- reg = <10>; +- label = "BTNESC"; +- linux,code = <1>; /* ESC button */ +- gpios = <&pioA 10 GPIO_ACTIVE_LOW>; +- wakeup-source; +- }; +- +- irqbtn@31 { +- reg = <31>; +- label = "IRQBTN"; +- linux,code = <99>; /* SysReq button */ +- gpios = <&pioE 31 GPIO_ACTIVE_LOW>; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led0 { +- label = "wb50n:blue:led0"; +- gpios = <&pioA 12 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led1 { +- label = "wb50n:green:led1"; +- gpios = <&pioA 24 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led2 { +- label = "wb50n:red:led2"; +- gpios = <&pioA 26 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-&mmc0 { +- status = "okay"; +-}; +- +-&macb1 { +- status = "okay"; +-}; +- +-&dbgu { +- status = "okay"; +-}; +- +-/* On BB40 this port is labeled UART1 */ +-&usart0 { +- status = "okay"; +-}; +- +-/* On BB40 this port is labeled UART0 */ +-&usart1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&spi1 { +- status = "okay"; +- +- spidev@0 { +- compatible = "spidev"; +- reg = <0>; +- spi-max-frequency = <8000000>; +- }; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&usb2 { +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/at91-wb50n.dtsi b/scripts/dtc/include-prefixes/arm/at91-wb50n.dtsi +deleted file mode 100644 +index 74b249bb6351..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91-wb50n.dtsi ++++ /dev/null +@@ -1,194 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * at91-wb50n.dtsi - Device Tree include file for wb50n cpu module +- * +- * Copyright (C) 2018 Laird +- * +- */ +- +-#include "sama5d31.dtsi" +- +-/ { +- model = "Laird Workgroup Bridge 50N - Atmel SAMA5D"; +- compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; +- +- chosen { +- bootargs = "ubi.mtd=6 root=ubi0:rootfs rootfstype=ubifs rw"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +-}; +- +-&pinctrl { +- board { +- pinctrl_mmc0_cd: mmc0_cd { +- atmel,pins = ; /* PC26 GPIO with pullup deglitch */ +- }; +- +- pinctrl_usba_vbus: usba_vbus { +- atmel,pins = ; /* PB13 GPIO with deglitch */ +- }; +- }; +-}; +- +-&slow_xtal { +- clock-frequency = <32768>; +-}; +- +-&main_xtal { +- clock-frequency = <12000000>; +-}; +- +-&clk32k { +- atmel,osc-bypass; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; +- cd-gpios = <&pioC 26 GPIO_ACTIVE_LOW>; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; +- status = "okay"; +- atheros@0 { +- compatible = "atheros,ath6kl"; +- atheros,board-id = "SD32"; +- reg = <0>; +- bus-width = <4>; +- }; +-}; +- +-&macb1 { +- phy-mode = "rmii"; +-}; +- +-&dbgu { +- dmas = <0>, <0>; /* Do not use DMA for dbgu */ +-}; +- +-/* On BB40 this port is labeled UART1 */ +-&usart0 { +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>; +-}; +- +-/* On BB40 this port is labeled UART0 */ +-&usart1 { +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; +- dtr-gpios = <&pioD 13 GPIO_ACTIVE_LOW>; +- dsr-gpios = <&pioD 11 GPIO_ACTIVE_LOW>; +- dcd-gpios = <&pioD 7 GPIO_ACTIVE_LOW>; +- rng-gpios = <&pioD 8 GPIO_ACTIVE_LOW>; +-}; +- +-/* USART3 is direct-connect to the Bluetooth UART on the radio SIP */ +-&usart3 { +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart3 &pinctrl_usart3_rts_cts>; +- status = "okay"; +-}; +- +-&spi1 { +- cs-gpios = <&pioC 25 0>, <0>, <0>, <0>; +-}; +- +-&ebi { +- pinctrl-0 = <&pinctrl_ebi_nand_addr>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand: nand@3 { +- reg = <0x3 0x0 0x2>; +- atmel,rb = <0>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <8>; +- nand-ecc-step-size = <512>; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bs"; +- reg = <0x0 0x20000>; +- }; +- +- uboot@20000 { +- label = "u-boot"; +- reg = <0x20000 0x80000>; +- }; +- +- ubootenv@a0000 { +- label = "u-boot-env"; +- reg = <0xa0000 0x20000>; +- }; +- +- ubootenv@c0000 { +- label = "u-boot-env"; +- reg = <0xc0000 0x20000>; +- }; +- +- kernel-a@e0000 { +- label = "kernel-a"; +- reg = <0xe0000 0x500000>; +- }; +- +- kernel-b@5e0000 { +- label = "kernel-b"; +- reg = <0x5e0000 0x500000>; +- }; +- +- rootfs-a@ae0000 { +- label = "rootfs-a"; +- reg = <0xae0000 0x3000000>; +- }; +- +- rootfs-b@3ae0000 { +- label = "rootfs-b"; +- reg = <0x3ae0000 0x3000000>; +- }; +- +- user@6ae0000 { +- label = "user"; +- reg = <0x6ae0000 0x14e0000>; +- }; +- }; +- }; +-}; +- +-&usb0 { +- atmel,vbus-gpio = <&pioB 13 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usba_vbus>; +-}; +- +-&usb1 { +- num-ports = <3>; +- atmel,vbus-gpio = <&pioA 2 GPIO_ACTIVE_LOW>; +- atmel,oc-gpio = <&pioA 4 GPIO_ACTIVE_LOW>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91rm9200.dtsi b/scripts/dtc/include-prefixes/arm/at91rm9200.dtsi +deleted file mode 100644 +index d1181ead18e5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91rm9200.dtsi ++++ /dev/null +@@ -1,723 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC +- * +- * Copyright (C) 2011 Atmel, +- * 2011 Nicolas Ferre , +- * 2012 Joachim Eastwood +- * +- * Based on at91sam9260.dtsi +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Atmel AT91RM9200 family SoC"; +- compatible = "atmel,at91rm9200"; +- interrupt-parent = <&aic>; +- +- aliases { +- serial0 = &dbgu; +- serial1 = &usart0; +- serial2 = &usart1; +- serial3 = &usart2; +- serial4 = &usart3; +- gpio0 = &pioA; +- gpio1 = &pioB; +- gpio2 = &pioC; +- gpio3 = &pioD; +- tcb0 = &tcb0; +- tcb1 = &tcb1; +- i2c0 = &i2c0; +- ssc0 = &ssc0; +- ssc1 = &ssc1; +- ssc2 = &ssc2; +- }; +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,arm920t"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x04000000>; +- }; +- +- clocks { +- slow_xtal: slow_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- main_xtal: main_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- }; +- +- sram: sram@200000 { +- compatible = "mmio-sram"; +- reg = <0x00200000 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00200000 0x4000>; +- }; +- +- ahb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- apb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- aic: interrupt-controller@fffff000 { +- #interrupt-cells = <3>; +- compatible = "atmel,at91rm9200-aic"; +- interrupt-controller; +- reg = <0xfffff000 0x200>; +- atmel,external-irqs = <25 26 27 28 29 30 31>; +- }; +- +- ramc0: ramc@ffffff00 { +- compatible = "atmel,at91rm9200-sdramc", "syscon"; +- reg = <0xffffff00 0x100>; +- }; +- +- pmc: pmc@fffffc00 { +- compatible = "atmel,at91rm9200-pmc", "syscon"; +- reg = <0xfffffc00 0x100>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- #clock-cells = <2>; +- clocks = <&slow_xtal>, <&main_xtal>; +- clock-names = "slow_xtal", "main_xtal"; +- }; +- +- st: timer@fffffd00 { +- compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd"; +- reg = <0xfffffd00 0x100>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&slow_xtal>; +- +- watchdog { +- compatible = "atmel,at91rm9200-wdt"; +- }; +- }; +- +- rtc: rtc@fffffe00 { +- compatible = "atmel,at91rm9200-rtc"; +- reg = <0xfffffe00 0x40>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&slow_xtal>; +- status = "disabled"; +- }; +- +- tcb0: timer@fffa0000 { +- compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xfffa0000 0x100>; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 +- 18 IRQ_TYPE_LEVEL_HIGH 0 +- 19 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>; +- clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; +- }; +- +- tcb1: timer@fffa4000 { +- compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xfffa4000 0x100>; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 +- 21 IRQ_TYPE_LEVEL_HIGH 0 +- 22 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&slow_xtal>; +- clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; +- }; +- +- i2c0: i2c@fffb8000 { +- compatible = "atmel,at91rm9200-i2c"; +- reg = <0xfffb8000 0x4000>; +- interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_twi>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- mmc0: mmc@fffb4000 { +- compatible = "atmel,hsmci"; +- reg = <0xfffb4000 0x4000>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; +- clock-names = "mci_clk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- ssc0: ssc@fffd0000 { +- compatible = "atmel,at91rm9200-ssc"; +- reg = <0xfffd0000 0x4000>; +- interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; +- clock-names = "pclk"; +- status = "disabled"; +- }; +- +- ssc1: ssc@fffd4000 { +- compatible = "atmel,at91rm9200-ssc"; +- reg = <0xfffd4000 0x4000>; +- interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; +- clock-names = "pclk"; +- status = "disabled"; +- }; +- +- ssc2: ssc@fffd8000 { +- compatible = "atmel,at91rm9200-ssc"; +- reg = <0xfffd8000 0x4000>; +- interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; +- clock-names = "pclk"; +- status = "disabled"; +- }; +- +- macb0: ethernet@fffbc000 { +- compatible = "cdns,at91rm9200-emac", "cdns,emac"; +- reg = <0xfffbc000 0x4000>; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_macb_rmii>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; +- clock-names = "ether_clk"; +- status = "disabled"; +- }; +- +- pinctrl@fffff400 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; +- ranges = <0xfffff400 0xfffff400 0x800>; +- +- atmel,mux-mask = < +- /* A B */ +- 0xffffffff 0xffffffff /* pioA */ +- 0xffffffff 0x083fffff /* pioB */ +- 0xffff3fff 0x00000000 /* pioC */ +- 0x03ff87ff 0x0fffff80 /* pioD */ +- >; +- +- /* shared pinctrl settings */ +- dbgu { +- pinctrl_dbgu: dbgu-0 { +- atmel,pins = +- ; +- }; +- }; +- +- uart0 { +- pinctrl_uart0: uart0-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_uart0_cts: uart0_cts-0 { +- atmel,pins = +- ; /* PA20 periph A */ +- }; +- +- pinctrl_uart0_rts: uart0_rts-0 { +- atmel,pins = +- ; /* PA21 periph A */ +- }; +- }; +- +- uart1 { +- pinctrl_uart1: uart1-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_uart1_rts: uart1_rts-0 { +- atmel,pins = +- ; /* PB24 periph A */ +- }; +- +- pinctrl_uart1_cts: uart1_cts-0 { +- atmel,pins = +- ; /* PB26 periph A */ +- }; +- +- pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 { +- atmel,pins = +- ; /* PB25 periph A */ +- }; +- +- pinctrl_uart1_dcd: uart1_dcd-0 { +- atmel,pins = +- ; /* PB23 periph A */ +- }; +- +- pinctrl_uart1_ri: uart1_ri-0 { +- atmel,pins = +- ; /* PB18 periph A */ +- }; +- }; +- +- uart2 { +- pinctrl_uart2: uart2-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_uart2_rts: uart2_rts-0 { +- atmel,pins = +- ; /* PA30 periph B */ +- }; +- +- pinctrl_uart2_cts: uart2_cts-0 { +- atmel,pins = +- ; /* PA31 periph B */ +- }; +- }; +- +- uart3 { +- pinctrl_uart3: uart3-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_uart3_rts: uart3_rts-0 { +- atmel,pins = +- ; /* PB0 periph B */ +- }; +- +- pinctrl_uart3_cts: uart3_cts-0 { +- atmel,pins = +- ; /* PB1 periph B */ +- }; +- }; +- +- nand { +- pinctrl_nand: nand-0 { +- atmel,pins = +- ; /* PB1 gpio CD pin pull_up */ +- }; +- }; +- +- macb { +- pinctrl_macb_rmii: macb_rmii-0 { +- atmel,pins = +- ; /* PA16 periph A */ +- }; +- +- pinctrl_macb_rmii_mii: macb_rmii_mii-0 { +- atmel,pins = +- ; /* PB19 periph B */ +- }; +- }; +- +- mmc0 { +- pinctrl_mmc0_clk: mmc0_clk-0 { +- atmel,pins = +- ; /* PA27 periph A */ +- }; +- +- pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { +- atmel,pins = +- ; /* PA29 periph A with pullup */ +- }; +- +- pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { +- atmel,pins = +- ; /* PB5 periph B with pullup */ +- }; +- +- pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { +- atmel,pins = +- ; /* PA9 periph B with pullup */ +- }; +- +- pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { +- atmel,pins = +- ; /* PA12 periph B with pullup */ +- }; +- }; +- +- ssc0 { +- pinctrl_ssc0_tx: ssc0_tx-0 { +- atmel,pins = +- ; /* PB2 periph A */ +- }; +- +- pinctrl_ssc0_rx: ssc0_rx-0 { +- atmel,pins = +- ; /* PB5 periph A */ +- }; +- }; +- +- ssc1 { +- pinctrl_ssc1_tx: ssc1_tx-0 { +- atmel,pins = +- ; /* PB8 periph A */ +- }; +- +- pinctrl_ssc1_rx: ssc1_rx-0 { +- atmel,pins = +- ; /* PB11 periph A */ +- }; +- }; +- +- ssc2 { +- pinctrl_ssc2_tx: ssc2_tx-0 { +- atmel,pins = +- ; /* PB14 periph A */ +- }; +- +- pinctrl_ssc2_rx: ssc2_rx-0 { +- atmel,pins = +- ; /* PB17 periph A */ +- }; +- }; +- +- twi { +- pinctrl_twi: twi-0 { +- atmel,pins = +- ; /* PA26 periph A with multi drive */ +- }; +- +- pinctrl_twi_gpio: twi_gpio-0 { +- atmel,pins = +- ; /* PA26 GPIO with multi drive */ +- }; +- }; +- +- tcb0 { +- pinctrl_tcb0_tclk0: tcb0_tclk0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tclk1: tcb0_tclk1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tclk2: tcb0_tclk2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa0: tcb0_tioa0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa1: tcb0_tioa1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa2: tcb0_tioa2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob0: tcb0_tiob0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob1: tcb0_tiob1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob2: tcb0_tiob2-0 { +- atmel,pins = ; +- }; +- }; +- +- tcb1 { +- pinctrl_tcb1_tclk0: tcb1_tclk0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tclk1: tcb1_tclk1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tclk2: tcb1_tclk2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tioa0: tcb1_tioa0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tioa1: tcb1_tioa1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tioa2: tcb1_tioa2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tiob0: tcb1_tiob0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tiob1: tcb1_tiob1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tiob2: tcb1_tiob2-0 { +- atmel,pins = ; +- }; +- }; +- +- spi0 { +- pinctrl_spi0: spi0-0 { +- atmel,pins = +- ; /* PA2 periph A SPI0_SPCK pin */ +- }; +- }; +- +- pioA: gpio@fffff400 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff400 0x200>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; +- }; +- +- pioB: gpio@fffff600 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff600 0x200>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; +- }; +- +- pioC: gpio@fffff800 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff800 0x200>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; +- }; +- +- pioD: gpio@fffffa00 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffffa00 0x200>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; +- }; +- }; +- +- dbgu: serial@fffff200 { +- compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart"; +- reg = <0xfffff200 0x200>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dbgu>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart0: serial@fffc0000 { +- compatible = "atmel,at91rm9200-usart"; +- reg = <0xfffc0000 0x200>; +- interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart1: serial@fffc4000 { +- compatible = "atmel,at91rm9200-usart"; +- reg = <0xfffc4000 0x200>; +- interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart2: serial@fffc8000 { +- compatible = "atmel,at91rm9200-usart"; +- reg = <0xfffc8000 0x200>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart3: serial@fffcc000 { +- compatible = "atmel,at91rm9200-usart"; +- reg = <0xfffcc000 0x200>; +- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usb1: gadget@fffb0000 { +- compatible = "atmel,at91rm9200-udc"; +- reg = <0xfffb0000 0x4000>; +- interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 11>, <&pmc PMC_TYPE_SYSTEM 2>; +- clock-names = "pclk", "hclk"; +- status = "disabled"; +- }; +- +- spi0: spi@fffe0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xfffe0000 0x200>; +- interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; +- clock-names = "spi_clk"; +- status = "disabled"; +- }; +- }; +- +- nand0: nand@40000000 { +- compatible = "atmel,at91rm9200-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x40000000 0x10000000>; +- atmel,nand-addr-offset = <21>; +- atmel,nand-cmd-offset = <22>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nand>; +- nand-ecc-mode = "soft"; +- gpios = <&pioC 2 GPIO_ACTIVE_HIGH +- 0 +- &pioB 1 GPIO_ACTIVE_HIGH +- >; +- status = "disabled"; +- }; +- +- usb0: ohci@300000 { +- compatible = "atmel,at91rm9200-ohci", "usb-ohci"; +- reg = <0x00300000 0x100000>; +- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_SYSTEM 4>; +- clock-names = "ohci_clk", "hclk", "uhpck"; +- status = "disabled"; +- }; +- }; +- +- i2c-gpio-0 { +- compatible = "i2c-gpio"; +- gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */ +- &pioA 26 GPIO_ACTIVE_HIGH /* scl */ +- >; +- i2c-gpio,sda-open-drain; +- i2c-gpio,scl-open-drain; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_twi_gpio>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91rm9200_pqfp.dtsi b/scripts/dtc/include-prefixes/arm/at91rm9200_pqfp.dtsi +deleted file mode 100644 +index c3d4177b9823..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91rm9200_pqfp.dtsi ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91rm9200_pqfp.dtsi - Device Tree Include file for AT91RM9200 PQFP family SoC +- * +- * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD +- */ +- +-#include "at91rm9200.dtsi" +- +-/ { +- compatible = "atmel,at91rm9200-pqfp", "atmel,at91rm9200"; +-}; +- +-&pioD { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91rm9200ek.dts b/scripts/dtc/include-prefixes/arm/at91rm9200ek.dts +deleted file mode 100644 +index e1ef4e44e663..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91rm9200ek.dts ++++ /dev/null +@@ -1,147 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91rm9200ek.dts - Device Tree file for Atmel AT91RM9200 evaluation kit +- * +- * Copyright (C) 2012 Joachim Eastwood +- */ +-/dts-v1/; +-#include "at91rm9200.dtsi" +- +-/ { +- model = "Atmel AT91RM9200 evaluation kit"; +- compatible = "atmel,at91rm9200ek", "atmel,at91rm9200"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <18432000>; +- }; +- }; +- +- ahb { +- apb { +- tcb0: timer@fffa0000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +- }; +- +- usb1: gadget@fffb0000 { +- atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; +- atmel,pullup-gpio = <&pioD 5 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- macb0: ethernet@fffbc000 { +- phy-mode = "rmii"; +- status = "okay"; +- +- phy0: ethernet-phy { +- interrupt-parent = <&pioC>; +- interrupts = <4 IRQ_TYPE_EDGE_BOTH>; +- }; +- }; +- +- usart1: serial@fffc4000 { +- pinctrl-0 = +- <&pinctrl_uart1 +- &pinctrl_uart1_rts +- &pinctrl_uart1_cts +- &pinctrl_uart1_dtr_dsr +- &pinctrl_uart1_dcd +- &pinctrl_uart1_ri>; +- status = "okay"; +- }; +- +- spi0: spi@fffe0000 { +- status = "okay"; +- cs-gpios = <&pioA 3 0>, <0>, <0>, <0>; +- mtd_dataflash@0 { +- compatible = "atmel,at45", "atmel,dataflash"; +- spi-max-frequency = <15000000>; +- reg = <0>; +- }; +- }; +- +- dbgu: serial@fffff200 { +- status = "okay"; +- }; +- +- rtc: rtc@fffffe00 { +- status = "okay"; +- }; +- }; +- +- usb0: ohci@300000 { +- num-ports = <2>; +- status = "okay"; +- }; +- +- nor_flash@10000000 { +- compatible = "cfi-flash"; +- reg = <0x10000000 0x800000>; +- linux,mtd-name = "physmap-flash.0"; +- bank-width = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- barebox@0 { +- label = "barebox"; +- reg = <0x00000 0x40000>; +- }; +- +- bareboxenv@40000 { +- label = "bareboxenv"; +- reg = <0x40000 0x10000>; +- }; +- +- kernel@50000 { +- label = "kernel"; +- reg = <0x50000 0x300000>; +- }; +- +- root@350000 { +- label = "root"; +- reg = <0x350000 0x4B0000>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- ds2 { +- label = "green"; +- gpios = <&pioB 0 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "mmc0"; +- }; +- +- ds4 { +- label = "yellow"; +- gpios = <&pioB 1 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- +- ds6 { +- label = "red"; +- gpios = <&pioB 2 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9260.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9260.dtsi +deleted file mode 100644 +index 019f1c3d4d30..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9260.dtsi ++++ /dev/null +@@ -1,788 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC +- * +- * Copyright (C) 2011 Atmel, +- * 2011 Nicolas Ferre , +- * 2011 Jean-Christophe PLAGNIOL-VILLARD +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Atmel AT91SAM9260 family SoC"; +- compatible = "atmel,at91sam9260"; +- interrupt-parent = <&aic>; +- +- aliases { +- serial0 = &dbgu; +- serial1 = &usart0; +- serial2 = &usart1; +- serial3 = &usart2; +- serial4 = &usart3; +- serial5 = &uart0; +- serial6 = &uart1; +- gpio0 = &pioA; +- gpio1 = &pioB; +- gpio2 = &pioC; +- tcb0 = &tcb0; +- tcb1 = &tcb1; +- i2c0 = &i2c0; +- ssc0 = &ssc0; +- }; +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,arm926ej-s"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x04000000>; +- }; +- +- clocks { +- slow_xtal: slow_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- main_xtal: main_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- adc_op_clk: adc_op_clk{ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <5000000>; +- }; +- }; +- +- sram0: sram@2ff000 { +- compatible = "mmio-sram"; +- reg = <0x002ff000 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x002ff000 0x2000>; +- }; +- +- ahb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- apb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- aic: interrupt-controller@fffff000 { +- #interrupt-cells = <3>; +- compatible = "atmel,at91rm9200-aic"; +- interrupt-controller; +- reg = <0xfffff000 0x200>; +- atmel,external-irqs = <29 30 31>; +- }; +- +- ramc0: ramc@ffffea00 { +- compatible = "atmel,at91sam9260-sdramc"; +- reg = <0xffffea00 0x200>; +- }; +- +- smc: smc@ffffec00 { +- compatible = "atmel,at91sam9260-smc", "syscon"; +- reg = <0xffffec00 0x200>; +- }; +- +- matrix: matrix@ffffee00 { +- compatible = "atmel,at91sam9260-matrix", "syscon"; +- reg = <0xffffee00 0x200>; +- }; +- +- pmc: pmc@fffffc00 { +- compatible = "atmel,at91sam9260-pmc", "syscon"; +- reg = <0xfffffc00 0x100>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- #clock-cells = <2>; +- clocks = <&slow_xtal>, <&main_xtal>; +- clock-names = "slow_xtal", "main_xtal"; +- }; +- +- rstc@fffffd00 { +- compatible = "atmel,at91sam9260-rstc"; +- reg = <0xfffffd00 0x10>; +- clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; +- }; +- +- shdwc@fffffd10 { +- compatible = "atmel,at91sam9260-shdwc"; +- reg = <0xfffffd10 0x10>; +- clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; +- }; +- +- pit: timer@fffffd30 { +- compatible = "atmel,at91sam9260-pit"; +- reg = <0xfffffd30 0xf>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- }; +- +- tcb0: timer@fffa0000 { +- compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xfffa0000 0x100>; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 +- 18 IRQ_TYPE_LEVEL_HIGH 0 +- 19 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&pmc PMC_TYPE_CORE PMC_SLOW>; +- clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; +- }; +- +- tcb1: timer@fffdc000 { +- compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xfffdc000 0x100>; +- interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 +- 27 IRQ_TYPE_LEVEL_HIGH 0 +- 28 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 28>, <&pmc PMC_TYPE_CORE PMC_SLOW>; +- clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; +- }; +- +- pinctrl@fffff400 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; +- ranges = <0xfffff400 0xfffff400 0x600>; +- +- atmel,mux-mask = < +- /* A B */ +- 0xffffffff 0xffc00c3b /* pioA */ +- 0xffffffff 0x7fff3ccf /* pioB */ +- 0xffffffff 0x007fffff /* pioC */ +- >; +- +- /* shared pinctrl settings */ +- dbgu { +- pinctrl_dbgu: dbgu-0 { +- atmel,pins = +- ; +- }; +- }; +- +- usart0 { +- pinctrl_usart0: usart0-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart0_rts: usart0_rts-0 { +- atmel,pins = +- ; /* PB26 periph A */ +- }; +- +- pinctrl_usart0_cts: usart0_cts-0 { +- atmel,pins = +- ; /* PB27 periph A */ +- }; +- +- pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { +- atmel,pins = +- ; /* PB22 periph A */ +- }; +- +- pinctrl_usart0_dcd: usart0_dcd-0 { +- atmel,pins = +- ; /* PB23 periph A */ +- }; +- +- pinctrl_usart0_ri: usart0_ri-0 { +- atmel,pins = +- ; /* PB25 periph A */ +- }; +- }; +- +- usart1 { +- pinctrl_usart1: usart1-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart1_rts: usart1_rts-0 { +- atmel,pins = +- ; /* PB28 periph A */ +- }; +- +- pinctrl_usart1_cts: usart1_cts-0 { +- atmel,pins = +- ; /* PB29 periph A */ +- }; +- }; +- +- usart2 { +- pinctrl_usart2: usart2-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart2_rts: usart2_rts-0 { +- atmel,pins = +- ; /* PA4 periph A */ +- }; +- +- pinctrl_usart2_cts: usart2_cts-0 { +- atmel,pins = +- ; /* PA5 periph A */ +- }; +- }; +- +- usart3 { +- pinctrl_usart3: usart3-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart3_rts: usart3_rts-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart3_cts: usart3_cts-0 { +- atmel,pins = +- ; +- }; +- }; +- +- uart0 { +- pinctrl_uart0: uart0-0 { +- atmel,pins = +- ; +- }; +- }; +- +- uart1 { +- pinctrl_uart1: uart1-0 { +- atmel,pins = +- ; +- }; +- }; +- +- nand { +- pinctrl_nand_rb: nand-rb-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_nand_cs: nand-cs-0 { +- atmel,pins = +- ; +- }; +- }; +- +- macb { +- pinctrl_macb_rmii: macb_rmii-0 { +- atmel,pins = +- ; /* PA21 periph A */ +- }; +- +- pinctrl_macb_rmii_mii: macb_rmii_mii-0 { +- atmel,pins = +- ; /* PA29 periph B */ +- }; +- +- pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 { +- atmel,pins = +- ; /* PA29 periph B */ +- }; +- }; +- +- mmc0 { +- pinctrl_mmc0_clk: mmc0_clk-0 { +- atmel,pins = +- ; /* PA8 periph A */ +- }; +- +- pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { +- atmel,pins = +- ; /* PA6 periph A with pullup */ +- }; +- +- pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { +- atmel,pins = +- ; /* PA11 periph A with pullup */ +- }; +- +- pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { +- atmel,pins = +- ; /* PA0 periph B with pullup */ +- }; +- +- pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { +- atmel,pins = +- ; /* PA3 periph B with pullup */ +- }; +- }; +- +- ssc0 { +- pinctrl_ssc0_tx: ssc0_tx-0 { +- atmel,pins = +- ; /* PB18 periph A */ +- }; +- +- pinctrl_ssc0_rx: ssc0_rx-0 { +- atmel,pins = +- ; /* PB21 periph A */ +- }; +- }; +- +- spi0 { +- pinctrl_spi0: spi0-0 { +- atmel,pins = +- ; /* PA2 periph A SPI0_SPCK pin */ +- }; +- }; +- +- spi1 { +- pinctrl_spi1: spi1-0 { +- atmel,pins = +- ; /* PB2 periph A SPI1_SPCK pin */ +- }; +- }; +- +- i2c_gpio0 { +- pinctrl_i2c_gpio0: i2c_gpio0-0 { +- atmel,pins = +- ; +- }; +- }; +- +- tcb0 { +- pinctrl_tcb0_tclk0: tcb0_tclk0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tclk1: tcb0_tclk1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tclk2: tcb0_tclk2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa0: tcb0_tioa0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa1: tcb0_tioa1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa2: tcb0_tioa2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob0: tcb0_tiob0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob1: tcb0_tiob1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob2: tcb0_tiob2-0 { +- atmel,pins = ; +- }; +- }; +- +- tcb1 { +- pinctrl_tcb1_tclk0: tcb1_tclk0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tclk1: tcb1_tclk1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tclk2: tcb1_tclk2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tioa0: tcb1_tioa0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tioa1: tcb1_tioa1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tioa2: tcb1_tioa2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tiob0: tcb1_tiob0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tiob1: tcb1_tiob1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tiob2: tcb1_tiob2-0 { +- atmel,pins = ; +- }; +- }; +- +- pioA: gpio@fffff400 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff400 0x200>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; +- }; +- +- pioB: gpio@fffff600 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff600 0x200>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; +- }; +- +- pioC: gpio@fffff800 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff800 0x200>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; +- }; +- }; +- +- dbgu: serial@fffff200 { +- compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; +- reg = <0xfffff200 0x200>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dbgu>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart0: serial@fffb0000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffb0000 0x200>; +- interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart1: serial@fffb4000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffb4000 0x200>; +- interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart2: serial@fffb8000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffb8000 0x200>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart3: serial@fffd0000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffd0000 0x200>; +- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- uart0: serial@fffd4000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffd4000 0x200>; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- uart1: serial@fffd8000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffd8000 0x200>; +- interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- macb0: ethernet@fffc4000 { +- compatible = "cdns,at91sam9260-macb", "cdns,macb"; +- reg = <0xfffc4000 0x100>; +- interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_macb_rmii>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 21>; +- clock-names = "hclk", "pclk"; +- status = "disabled"; +- }; +- +- usb1: gadget@fffa4000 { +- compatible = "atmel,at91sam9260-udc"; +- reg = <0xfffa4000 0x4000>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 10>, <&pmc PMC_TYPE_SYSTEM 7>; +- clock-names = "pclk", "hclk"; +- status = "disabled"; +- }; +- +- i2c0: i2c@fffac000 { +- compatible = "atmel,at91sam9260-i2c"; +- reg = <0xfffac000 0x100>; +- interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; +- status = "disabled"; +- }; +- +- mmc0: mmc@fffa8000 { +- compatible = "atmel,hsmci"; +- reg = <0xfffa8000 0x600>; +- interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; +- clock-names = "mci_clk"; +- status = "disabled"; +- }; +- +- ssc0: ssc@fffbc000 { +- compatible = "atmel,at91rm9200-ssc"; +- reg = <0xfffbc000 0x4000>; +- interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; +- clock-names = "pclk"; +- status = "disabled"; +- }; +- +- spi0: spi@fffc8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xfffc8000 0x200>; +- interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; +- clock-names = "spi_clk"; +- status = "disabled"; +- }; +- +- spi1: spi@fffcc000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xfffcc000 0x200>; +- interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; +- clock-names = "spi_clk"; +- status = "disabled"; +- }; +- +- adc0: adc@fffe0000 { +- compatible = "atmel,at91sam9260-adc"; +- reg = <0xfffe0000 0x100>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&adc_op_clk>; +- clock-names = "adc_clk", "adc_op_clk"; +- atmel,adc-use-external-triggers; +- atmel,adc-channels-used = <0xf>; +- atmel,adc-vref = <3300>; +- atmel,adc-startup-time = <15>; +- }; +- +- rtc@fffffd20 { +- compatible = "atmel,at91sam9260-rtt"; +- reg = <0xfffffd20 0x10>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; +- status = "disabled"; +- }; +- +- watchdog: watchdog@fffffd40 { +- compatible = "atmel,at91sam9260-wdt"; +- reg = <0xfffffd40 0x10>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; +- atmel,watchdog-type = "hardware"; +- atmel,reset-type = "all"; +- atmel,dbg-halt; +- status = "disabled"; +- }; +- +- gpbr: syscon@fffffd50 { +- compatible = "atmel,at91sam9260-gpbr", "syscon"; +- reg = <0xfffffd50 0x10>; +- status = "disabled"; +- }; +- }; +- +- usb0: ohci@500000 { +- compatible = "atmel,at91rm9200-ohci", "usb-ohci"; +- reg = <0x00500000 0x100000>; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_SYSTEM 6>; +- clock-names = "ohci_clk", "hclk", "uhpck"; +- status = "disabled"; +- }; +- +- ebi: ebi@10000000 { +- compatible = "atmel,at91sam9260-ebi"; +- #address-cells = <2>; +- #size-cells = <1>; +- atmel,smc = <&smc>; +- atmel,matrix = <&matrix>; +- reg = <0x10000000 0x80000000>; +- ranges = <0x0 0x0 0x10000000 0x10000000 +- 0x1 0x0 0x20000000 0x10000000 +- 0x2 0x0 0x30000000 0x10000000 +- 0x3 0x0 0x40000000 0x10000000 +- 0x4 0x0 0x50000000 0x10000000 +- 0x5 0x0 0x60000000 0x10000000 +- 0x6 0x0 0x70000000 0x10000000 +- 0x7 0x0 0x80000000 0x10000000>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- status = "disabled"; +- +- nand_controller: nand-controller { +- compatible = "atmel,at91sam9260-nand-controller"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- }; +- }; +- }; +- +- i2c_gpio0: i2c-gpio-0 { +- compatible = "i2c-gpio"; +- gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */ +- &pioA 24 GPIO_ACTIVE_HIGH /* scl */ +- >; +- i2c-gpio,sda-open-drain; +- i2c-gpio,scl-open-drain; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c_gpio0>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9260ek.dts b/scripts/dtc/include-prefixes/arm/at91sam9260ek.dts +deleted file mode 100644 +index ce96345d28a3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9260ek.dts ++++ /dev/null +@@ -1,188 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Atmel at91sam9260 Evaluation Kit +- * +- * Copyright (C) 2016 Atmel, +- * 2016 Nicolas Ferre +- */ +-/dts-v1/; +-#include "at91sam9260.dtsi" +-#include +- +-/ { +- model = "Atmel at91sam9260ek"; +- compatible = "atmel,at91sam9260ek", "atmel,at91sam9260", "atmel,at91sam9"; +- +- chosen { +- stdout-path = &dbgu; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <18432000>; +- }; +- }; +- +- ahb { +- apb { +- tcb0: timer@fffa0000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +- }; +- +- usb1: gadget@fffa4000 { +- atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- mmc0: mmc@fffa8000 { +- pinctrl-0 = < +- &pinctrl_board_mmc0_slot1 +- &pinctrl_mmc0_clk +- &pinctrl_mmc0_slot1_cmd_dat0 +- &pinctrl_mmc0_slot1_dat1_3>; +- pinctrl-names = "default"; +- status = "okay"; +- slot@1 { +- reg = <1>; +- bus-width = <4>; +- cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- usart0: serial@fffb0000 { +- pinctrl-0 = +- <&pinctrl_usart0 +- &pinctrl_usart0_rts +- &pinctrl_usart0_cts +- &pinctrl_usart0_dtr_dsr +- &pinctrl_usart0_dcd +- &pinctrl_usart0_ri>; +- status = "okay"; +- }; +- +- usart1: serial@fffb4000 { +- status = "okay"; +- }; +- +- ssc0: ssc@fffbc000 { +- status = "okay"; +- pinctrl-0 = <&pinctrl_ssc0_tx>; +- }; +- +- macb0: ethernet@fffc4000 { +- phy-mode = "rmii"; +- status = "okay"; +- }; +- +- spi0: spi@fffc8000 { +- cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; +- mtd_dataflash@1 { +- compatible = "atmel,at45", "atmel,dataflash"; +- spi-max-frequency = <50000000>; +- reg = <1>; +- }; +- }; +- +- dbgu: serial@fffff200 { +- status = "okay"; +- }; +- +- pinctrl@fffff400 { +- board { +- pinctrl_board_mmc0_slot1: mmc0_slot1-board { +- atmel,pins = +- ; +- }; +- }; +- }; +- +- shdwc@fffffd10 { +- atmel,wakeup-counter = <10>; +- atmel,wakeup-rtt-timer; +- }; +- +- rtc@fffffd20 { +- atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +- status = "okay"; +- }; +- +- watchdog@fffffd40 { +- status = "okay"; +- }; +- +- gpbr: syscon@fffffd50 { +- status = "okay"; +- }; +- }; +- +- usb0: ohci@500000 { +- num-ports = <2>; +- status = "okay"; +- }; +- +- nand0: nand@40000000 { +- nand-bus-width = <8>; +- nand-ecc-mode = "soft"; +- nand-on-flash-bbt; +- status = "okay"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- btn3 { +- label = "Button 3"; +- gpios = <&pioA 30 GPIO_ACTIVE_LOW>; +- linux,code = <0x103>; +- wakeup-source; +- }; +- +- btn4 { +- label = "Button 4"; +- gpios = <&pioA 31 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- i2c-gpio-0 { +- status = "okay"; +- +- 24c512@50 { +- compatible = "atmel,24c512"; +- reg = <0x50>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- ds1 { +- label = "ds1"; +- gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- ds5 { +- label = "ds5"; +- gpios = <&pioA 6 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9261.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9261.dtsi +deleted file mode 100644 +index 7adc36ca8a46..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9261.dtsi ++++ /dev/null +@@ -1,662 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC +- * +- * Copyright (C) 2013 Jean-Jacques Hiblot +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Atmel AT91SAM9261 family SoC"; +- compatible = "atmel,at91sam9261"; +- interrupt-parent = <&aic>; +- +- aliases { +- serial0 = &dbgu; +- serial1 = &usart0; +- serial2 = &usart1; +- serial3 = &usart2; +- gpio0 = &pioA; +- gpio1 = &pioB; +- gpio2 = &pioC; +- tcb0 = &tcb0; +- i2c0 = &i2c0; +- ssc0 = &ssc0; +- ssc1 = &ssc1; +- ssc2 = &ssc2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,arm926ej-s"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x08000000>; +- }; +- +- clocks { +- main_xtal: main_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- slow_xtal: slow_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- }; +- +- sram: sram@300000 { +- compatible = "mmio-sram"; +- reg = <0x00300000 0x28000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00300000 0x28000>; +- }; +- +- ahb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- usb0: ohci@500000 { +- compatible = "atmel,at91rm9200-ohci", "usb-ohci"; +- reg = <0x00500000 0x100000>; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_SYSTEM 16>, <&pmc PMC_TYPE_SYSTEM 6>; +- clock-names = "ohci_clk", "hclk", "uhpck"; +- status = "disabled"; +- }; +- +- fb0: fb@600000 { +- compatible = "atmel,at91sam9261-lcdc"; +- reg = <0x00600000 0x1000>; +- interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fb>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_SYSTEM 17>; +- clock-names = "lcdc_clk", "hclk"; +- status = "disabled"; +- }; +- +- ebi: ebi@10000000 { +- compatible = "atmel,at91sam9261-ebi"; +- #address-cells = <2>; +- #size-cells = <1>; +- atmel,smc = <&smc>; +- atmel,matrix = <&matrix>; +- reg = <0x10000000 0x80000000>; +- ranges = <0x0 0x0 0x10000000 0x10000000 +- 0x1 0x0 0x20000000 0x10000000 +- 0x2 0x0 0x30000000 0x10000000 +- 0x3 0x0 0x40000000 0x10000000 +- 0x4 0x0 0x50000000 0x10000000 +- 0x5 0x0 0x60000000 0x10000000 +- 0x6 0x0 0x70000000 0x10000000 +- 0x7 0x0 0x80000000 0x10000000>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- status = "disabled"; +- +- nand_controller: nand-controller { +- compatible = "atmel,at91sam9261-nand-controller"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- }; +- }; +- +- apb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- tcb0: timer@fffa0000 { +- compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xfffa0000 0x100>; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>, +- <18 IRQ_TYPE_LEVEL_HIGH 0>, +- <19 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>; +- clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; +- }; +- +- usb1: gadget@fffa4000 { +- compatible = "atmel,at91sam9261-udc"; +- reg = <0xfffa4000 0x4000>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 10>, <&pmc PMC_TYPE_SYSTEM 7>; +- clock-names = "pclk", "hclk"; +- atmel,matrix = <&matrix>; +- status = "disabled"; +- }; +- +- mmc0: mmc@fffa8000 { +- compatible = "atmel,hsmci"; +- reg = <0xfffa8000 0x600>; +- interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; +- clock-names = "mci_clk"; +- status = "disabled"; +- }; +- +- i2c0: i2c@fffac000 { +- compatible = "atmel,at91sam9261-i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c_twi>; +- reg = <0xfffac000 0x100>; +- interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; +- status = "disabled"; +- }; +- +- usart0: serial@fffb0000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffb0000 0x200>; +- interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart1: serial@fffb4000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffb4000 0x200>; +- interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart2: serial@fffb8000{ +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffb8000 0x200>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- ssc0: ssc@fffbc000 { +- compatible = "atmel,at91rm9200-ssc"; +- reg = <0xfffbc000 0x4000>; +- interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; +- clock-names = "pclk"; +- status = "disabled"; +- }; +- +- ssc1: ssc@fffc0000 { +- compatible = "atmel,at91rm9200-ssc"; +- reg = <0xfffc0000 0x4000>; +- interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; +- clock-names = "pclk"; +- status = "disabled"; +- }; +- +- ssc2: ssc@fffc4000 { +- compatible = "atmel,at91rm9200-ssc"; +- reg = <0xfffc4000 0x4000>; +- interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; +- clock-names = "pclk"; +- status = "disabled"; +- }; +- +- spi0: spi@fffc8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xfffc8000 0x200>; +- cs-gpios = <0>, <0>, <0>, <0>; +- interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; +- clock-names = "spi_clk"; +- status = "disabled"; +- }; +- +- spi1: spi@fffcc000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xfffcc000 0x200>; +- interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; +- clock-names = "spi_clk"; +- status = "disabled"; +- }; +- +- ramc: ramc@ffffea00 { +- compatible = "atmel,at91sam9260-sdramc"; +- reg = <0xffffea00 0x200>; +- }; +- +- smc: smc@ffffec00 { +- compatible = "atmel,at91sam9260-smc", "syscon"; +- reg = <0xffffec00 0x200>; +- }; +- +- matrix: matrix@ffffee00 { +- compatible = "atmel,at91sam9261-matrix", "syscon"; +- reg = <0xffffee00 0x200>; +- }; +- +- aic: interrupt-controller@fffff000 { +- #interrupt-cells = <3>; +- compatible = "atmel,at91rm9200-aic"; +- interrupt-controller; +- reg = <0xfffff000 0x200>; +- atmel,external-irqs = <29 30 31>; +- }; +- +- dbgu: serial@fffff200 { +- compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; +- reg = <0xfffff200 0x200>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dbgu>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- pinctrl@fffff400 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; +- ranges = <0xfffff400 0xfffff400 0x600>; +- +- atmel,mux-mask = +- /* A B */ +- <0xffffffff 0xfffffff7>, /* pioA */ +- <0xffffffff 0xfffffff4>, /* pioB */ +- <0xffffffff 0xffffff07>; /* pioC */ +- +- /* shared pinctrl settings */ +- dbgu { +- pinctrl_dbgu: dbgu-0 { +- atmel,pins = +- , +- ; +- }; +- }; +- +- usart0 { +- pinctrl_usart0: usart0-0 { +- atmel,pins = +- , +- ; +- }; +- +- pinctrl_usart0_rts: usart0_rts-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart0_cts: usart0_cts-0 { +- atmel,pins = +- ; +- }; +- }; +- +- usart1 { +- pinctrl_usart1: usart1-0 { +- atmel,pins = +- , +- ; +- }; +- +- pinctrl_usart1_rts: usart1_rts-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart1_cts: usart1_cts-0 { +- atmel,pins = +- ; +- }; +- }; +- +- usart2 { +- pinctrl_usart2: usart2-0 { +- atmel,pins = +- , +- ; +- }; +- +- pinctrl_usart2_rts: usart2_rts-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart2_cts: usart2_cts-0 { +- atmel,pins = +- ; +- }; +- }; +- +- nand { +- pinctrl_nand_rb: nand-rb-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_nand_cs: nand-cs-0 { +- atmel,pins = +- ; +- }; +- }; +- +- mmc0 { +- pinctrl_mmc0_clk: mmc0_clk-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { +- atmel,pins = +- , +- ; +- }; +- +- pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { +- atmel,pins = +- , +- , +- ; +- }; +- }; +- +- ssc0 { +- pinctrl_ssc0_tx: ssc0_tx-0 { +- atmel,pins = +- , +- , +- ; +- }; +- +- pinctrl_ssc0_rx: ssc0_rx-0 { +- atmel,pins = +- , +- , +- ; +- }; +- }; +- +- ssc1 { +- pinctrl_ssc1_tx: ssc1_tx-0 { +- atmel,pins = +- , +- , +- ; +- }; +- +- pinctrl_ssc1_rx: ssc1_rx-0 { +- atmel,pins = +- , +- , +- ; +- }; +- }; +- +- ssc2 { +- pinctrl_ssc2_tx: ssc2_tx-0 { +- atmel,pins = +- , +- , +- ; +- }; +- +- pinctrl_ssc2_rx: ssc2_rx-0 { +- atmel,pins = +- , +- , +- ; +- }; +- }; +- +- spi0 { +- pinctrl_spi0: spi0-0 { +- atmel,pins = +- , +- , +- ; +- }; +- }; +- +- spi1 { +- pinctrl_spi1: spi1-0 { +- atmel,pins = +- , +- , +- ; +- }; +- }; +- +- tcb0 { +- pinctrl_tcb0_tclk0: tcb0_tclk0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tclk1: tcb0_tclk1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tclk2: tcb0_tclk2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa0: tcb0_tioa0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa1: tcb0_tioa1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa2: tcb0_tioa2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob0: tcb0_tiob0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob1: tcb0_tiob1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob2: tcb0_tiob2-0 { +- atmel,pins = ; +- }; +- }; +- +- i2c0 { +- pinctrl_i2c_bitbang: i2c-0-bitbang { +- atmel,pins = +- , +- ; +- }; +- pinctrl_i2c_twi: i2c-0-twi { +- atmel,pins = +- , +- ; +- }; +- }; +- +- fb { +- pinctrl_fb: fb-0 { +- atmel,pins = +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- }; +- }; +- +- pioA: gpio@fffff400 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff400 0x200>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; +- }; +- +- pioB: gpio@fffff600 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff600 0x200>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; +- }; +- +- pioC: gpio@fffff800 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff800 0x200>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; +- }; +- }; +- +- pmc: pmc@fffffc00 { +- compatible = "atmel,at91sam9261-pmc", "syscon"; +- reg = <0xfffffc00 0x100>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- #clock-cells = <2>; +- clocks = <&slow_xtal>, <&main_xtal>; +- clock-names = "slow_xtal", "main_xtal"; +- }; +- +- rstc@fffffd00 { +- compatible = "atmel,at91sam9260-rstc"; +- reg = <0xfffffd00 0x10>; +- clocks = <&slow_xtal>; +- }; +- +- shdwc@fffffd10 { +- compatible = "atmel,at91sam9260-shdwc"; +- reg = <0xfffffd10 0x10>; +- clocks = <&slow_xtal>; +- }; +- +- pit: timer@fffffd30 { +- compatible = "atmel,at91sam9260-pit"; +- reg = <0xfffffd30 0xf>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- }; +- +- rtc@fffffd20 { +- compatible = "atmel,at91sam9260-rtt"; +- reg = <0xfffffd20 0x10>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&slow_xtal>; +- status = "disabled"; +- }; +- +- watchdog@fffffd40 { +- compatible = "atmel,at91sam9260-wdt"; +- reg = <0xfffffd40 0x10>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&slow_xtal>; +- status = "disabled"; +- }; +- +- gpbr: syscon@fffffd50 { +- compatible = "atmel,at91sam9260-gpbr", "syscon"; +- reg = <0xfffffd50 0x10>; +- status = "disabled"; +- }; +- }; +- }; +- +- i2c-gpio-0 { +- compatible = "i2c-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c_bitbang>; +- gpios = <&pioA 7 GPIO_ACTIVE_HIGH>, /* sda */ +- <&pioA 8 GPIO_ACTIVE_HIGH>; /* scl */ +- i2c-gpio,sda-open-drain; +- i2c-gpio,scl-open-drain; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9261ek.dts b/scripts/dtc/include-prefixes/arm/at91sam9261ek.dts +deleted file mode 100644 +index beed819609e8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9261ek.dts ++++ /dev/null +@@ -1,241 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9261ek.dts - Device Tree file for Atmel at91sam9261 reference board +- * +- * Copyright (C) 2013 Jean-Jacques Hiblot +- */ +-/dts-v1/; +-#include "at91sam9261.dtsi" +- +-/ { +- model = "Atmel at91sam9261ek"; +- compatible = "atmel,at91sam9261ek", "atmel,at91sam9261", "atmel,at91sam9"; +- +- chosen { +- bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <18432000>; +- }; +- }; +- +- ahb { +- usb0: ohci@500000 { +- status = "okay"; +- }; +- +- fb0: fb@600000 { +- display = <&display0>; +- atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- display0: panel { +- bits-per-pixel = <16>; +- atmel,lcdcon-backlight; +- atmel,dmacon = <0x1>; +- atmel,lcdcon2 = <0x80008002>; +- atmel,guard-time = <1>; +- atmel,lcd-wiring-mode = "BRG"; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing0 { +- clock-frequency = <4965000>; +- hactive = <240>; +- vactive = <320>; +- hback-porch = <1>; +- hfront-porch = <33>; +- vback-porch = <1>; +- vfront-porch = <0>; +- hsync-len = <5>; +- vsync-len = <1>; +- hsync-active = <1>; +- vsync-active = <1>; +- }; +- }; +- }; +- }; +- +- ebi: ebi@10000000 { +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; +- pinctrl-names = "default"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioC 15 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "soft"; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x40000>; +- }; +- +- bootloader@40000 { +- label = "bootloader"; +- reg = <0x40000 0x80000>; +- }; +- +- bootloaderenv@c0000 { +- label = "bootloader env"; +- reg = <0xc0000 0xc0000>; +- }; +- +- dtb@180000 { +- label = "device tree"; +- reg = <0x180000 0x80000>; +- }; +- +- kernel@200000 { +- label = "kernel"; +- reg = <0x200000 0x600000>; +- }; +- +- rootfs@800000 { +- label = "rootfs"; +- reg = <0x800000 0x0f800000>; +- }; +- }; +- }; +- }; +- }; +- +- apb { +- tcb0: timer@fffa0000 { +- timer0: timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer1: timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +- }; +- +- usb1: gadget@fffa4000 { +- atmel,vbus-gpio = <&pioB 29 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- spi0: spi@fffc8000 { +- cs-gpios = <&pioA 3 0>, <0>, <&pioA 28 0>, <0>; +- status = "okay"; +- +- mtd_dataflash@0 { +- compatible = "atmel,at45", "atmel,dataflash"; +- reg = <0>; +- spi-max-frequency = <15000000>; +- }; +- +- tsc2046@2 { +- reg = <2>; +- compatible = "ti,ads7843"; +- interrupts-extended = <&pioC 2 IRQ_TYPE_EDGE_BOTH>; +- spi-max-frequency = <3000000>; +- pendown-gpio = <&pioC 2 GPIO_ACTIVE_HIGH>; +- +- ti,x-min = /bits/ 16 <150>; +- ti,x-max = /bits/ 16 <3830>; +- ti,y-min = /bits/ 16 <190>; +- ti,y-max = /bits/ 16 <3830>; +- ti,vref-delay-usecs = /bits/ 16 <450>; +- ti,x-plate-ohms = /bits/ 16 <450>; +- ti,y-plate-ohms = /bits/ 16 <250>; +- ti,pressure-max = /bits/ 16 <15000>; +- ti,debounce-rep = /bits/ 16 <0>; +- ti,debounce-tol = /bits/ 16 <65535>; +- ti,debounce-max = /bits/ 16 <1>; +- +- wakeup-source; +- }; +- }; +- +- dbgu: serial@fffff200 { +- status = "okay"; +- }; +- +- watchdog@fffffd40 { +- status = "okay"; +- }; +- +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- ds8 { +- label = "ds8"; +- gpios = <&pioA 13 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "none"; +- }; +- +- ds7 { +- label = "ds7"; +- gpios = <&pioA 14 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "nand-disk"; +- }; +- +- ds1 { +- label = "ds1"; +- gpios = <&pioA 23 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- button_0 { +- label = "button_0"; +- gpios = <&pioA 27 GPIO_ACTIVE_LOW>; +- linux,code = <256>; +- wakeup-source; +- }; +- +- button_1 { +- label = "button_1"; +- gpios = <&pioA 26 GPIO_ACTIVE_LOW>; +- linux,code = <257>; +- wakeup-source; +- }; +- +- button_2 { +- label = "button_2"; +- gpios = <&pioA 25 GPIO_ACTIVE_LOW>; +- linux,code = <258>; +- wakeup-source; +- }; +- +- button_3 { +- label = "button_3"; +- gpios = <&pioA 24 GPIO_ACTIVE_LOW>; +- linux,code = <259>; +- wakeup-source; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9263.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9263.dtsi +deleted file mode 100644 +index fe45d96239c9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9263.dtsi ++++ /dev/null +@@ -1,834 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC +- * +- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Atmel AT91SAM9263 family SoC"; +- compatible = "atmel,at91sam9263"; +- interrupt-parent = <&aic>; +- +- aliases { +- serial0 = &dbgu; +- serial1 = &usart0; +- serial2 = &usart1; +- serial3 = &usart2; +- gpio0 = &pioA; +- gpio1 = &pioB; +- gpio2 = &pioC; +- gpio3 = &pioD; +- gpio4 = &pioE; +- tcb0 = &tcb0; +- i2c0 = &i2c0; +- ssc0 = &ssc0; +- ssc1 = &ssc1; +- pwm0 = &pwm0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,arm926ej-s"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x08000000>; +- }; +- +- clocks { +- main_xtal: main_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- slow_xtal: slow_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- }; +- +- sram0: sram@300000 { +- compatible = "mmio-sram"; +- reg = <0x00300000 0x14000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00300000 0x14000>; +- }; +- +- sram1: sram@500000 { +- compatible = "mmio-sram"; +- reg = <0x00500000 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00500000 0x4000>; +- }; +- +- ahb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- apb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- aic: interrupt-controller@fffff000 { +- #interrupt-cells = <3>; +- compatible = "atmel,at91rm9200-aic"; +- interrupt-controller; +- reg = <0xfffff000 0x200>; +- atmel,external-irqs = <30 31>; +- }; +- +- pmc: pmc@fffffc00 { +- compatible = "atmel,at91sam9263-pmc", "syscon"; +- reg = <0xfffffc00 0x100>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- #clock-cells = <2>; +- clocks = <&slow_xtal>, <&main_xtal>; +- clock-names = "slow_xtal", "main_xtal"; +- }; +- +- ramc0: ramc@ffffe200 { +- compatible = "atmel,at91sam9260-sdramc"; +- reg = <0xffffe200 0x200>; +- }; +- +- smc0: smc@ffffe400 { +- compatible = "atmel,at91sam9260-smc", "syscon"; +- reg = <0xffffe400 0x200>; +- }; +- +- ramc1: ramc@ffffe800 { +- compatible = "atmel,at91sam9260-sdramc"; +- reg = <0xffffe800 0x200>; +- }; +- +- smc1: smc@ffffea00 { +- compatible = "atmel,at91sam9260-smc", "syscon"; +- reg = <0xffffea00 0x200>; +- }; +- +- matrix: matrix@ffffec00 { +- compatible = "atmel,at91sam9263-matrix", "syscon"; +- reg = <0xffffec00 0x200>; +- }; +- +- pit: timer@fffffd30 { +- compatible = "atmel,at91sam9260-pit"; +- reg = <0xfffffd30 0xf>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- }; +- +- tcb0: timer@fff7c000 { +- compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xfff7c000 0x100>; +- interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>; +- clock-names = "t0_clk", "slow_clk"; +- }; +- +- rstc@fffffd00 { +- compatible = "atmel,at91sam9260-rstc"; +- reg = <0xfffffd00 0x10>; +- clocks = <&slow_xtal>; +- }; +- +- shdwc@fffffd10 { +- compatible = "atmel,at91sam9260-shdwc"; +- reg = <0xfffffd10 0x10>; +- clocks = <&slow_xtal>; +- }; +- +- pinctrl@fffff200 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; +- ranges = <0xfffff200 0xfffff200 0xa00>; +- +- atmel,mux-mask = < +- /* A B */ +- 0xfffffffb 0xffffe07f /* pioA */ +- 0x0007ffff 0x39072fff /* pioB */ +- 0xffffffff 0x3ffffff8 /* pioC */ +- 0xfffffbff 0xffffffff /* pioD */ +- 0xffe00fff 0xfbfcff00 /* pioE */ +- >; +- +- /* shared pinctrl settings */ +- dbgu { +- pinctrl_dbgu: dbgu-0 { +- atmel,pins = +- ; +- }; +- }; +- +- usart0 { +- pinctrl_usart0: usart0-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart0_rts: usart0_rts-0 { +- atmel,pins = +- ; /* PA28 periph A */ +- }; +- +- pinctrl_usart0_cts: usart0_cts-0 { +- atmel,pins = +- ; /* PA29 periph A */ +- }; +- }; +- +- usart1 { +- pinctrl_usart1: usart1-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart1_rts: usart1_rts-0 { +- atmel,pins = +- ; /* PD7 periph B */ +- }; +- +- pinctrl_usart1_cts: usart1_cts-0 { +- atmel,pins = +- ; /* PD8 periph B */ +- }; +- }; +- +- usart2 { +- pinctrl_usart2: usart2-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart2_rts: usart2_rts-0 { +- atmel,pins = +- ; /* PD5 periph B */ +- }; +- +- pinctrl_usart2_cts: usart2_cts-0 { +- atmel,pins = +- ; /* PD6 periph B */ +- }; +- }; +- +- nand { +- pinctrl_nand_rb: nand-rb-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_nand_cs: nand-cs-0 { +- atmel,pins = +- ; +- }; +- }; +- +- macb { +- pinctrl_macb_rmii: macb_rmii-0 { +- atmel,pins = +- ; /* PE30 periph A */ +- }; +- +- pinctrl_macb_rmii_mii: macb_rmii_mii-0 { +- atmel,pins = +- ; /* PE22 periph B */ +- }; +- }; +- +- mmc0 { +- pinctrl_mmc0_clk: mmc0_clk-0 { +- atmel,pins = +- ; /* PA12 periph A */ +- }; +- +- pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { +- atmel,pins = +- ; /* PA0 periph A with pullup */ +- }; +- +- pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { +- atmel,pins = +- ; /* PA5 periph A with pullup */ +- }; +- +- pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { +- atmel,pins = +- ; /* PA17 periph A with pullup */ +- }; +- +- pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { +- atmel,pins = +- ; /* PA20 periph A with pullup */ +- }; +- }; +- +- mmc1 { +- pinctrl_mmc1_clk: mmc1_clk-0 { +- atmel,pins = +- ; /* PA6 periph A */ +- }; +- +- pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 { +- atmel,pins = +- ; /* PA8 periph A with pullup */ +- }; +- +- pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { +- atmel,pins = +- ; /* PA11 periph A with pullup */ +- }; +- +- pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 { +- atmel,pins = +- ; /* PA22 periph A with pullup */ +- }; +- +- pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 { +- atmel,pins = +- ; /* PA25 periph A with pullup */ +- }; +- }; +- +- ssc0 { +- pinctrl_ssc0_tx: ssc0_tx-0 { +- atmel,pins = +- ; /* PB2 periph B */ +- }; +- +- pinctrl_ssc0_rx: ssc0_rx-0 { +- atmel,pins = +- ; /* PB5 periph B */ +- }; +- }; +- +- ssc1 { +- pinctrl_ssc1_tx: ssc1_tx-0 { +- atmel,pins = +- ; /* PB8 periph A */ +- }; +- +- pinctrl_ssc1_rx: ssc1_rx-0 { +- atmel,pins = +- ; /* PB11 periph A */ +- }; +- }; +- +- spi0 { +- pinctrl_spi0: spi0-0 { +- atmel,pins = +- ; /* PA2 periph B SPI0_SPCK pin */ +- }; +- }; +- +- spi1 { +- pinctrl_spi1: spi1-0 { +- atmel,pins = +- ; /* PB14 periph A SPI1_SPCK pin */ +- }; +- }; +- +- tcb0 { +- pinctrl_tcb0_tclk0: tcb0_tclk0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tclk1: tcb0_tclk1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tclk2: tcb0_tclk2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa0: tcb0_tioa0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa1: tcb0_tioa1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa2: tcb0_tioa2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob0: tcb0_tiob0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob1: tcb0_tiob1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob2: tcb0_tiob2-0 { +- atmel,pins = ; +- }; +- }; +- +- fb { +- pinctrl_fb: fb-0 { +- atmel,pins = +- ; /* PC27 periph A */ +- }; +- }; +- +- can { +- pinctrl_can_rx_tx: can_rx_tx { +- atmel,pins = +- ; /* CANTX, conflicts with PCK0 */ +- }; +- }; +- +- ac97 { +- pinctrl_ac97: ac97-0 { +- atmel,pins = +- ; /* PB14 periph A AC97RX pin */ +- }; +- }; +- +- pioA: gpio@fffff200 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff200 0x200>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; +- }; +- +- pioB: gpio@fffff400 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff400 0x200>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; +- }; +- +- pioC: gpio@fffff600 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff600 0x200>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; +- }; +- +- pioD: gpio@fffff800 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff800 0x200>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; +- }; +- +- pioE: gpio@fffffa00 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffffa00 0x200>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; +- }; +- }; +- +- dbgu: serial@ffffee00 { +- compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; +- reg = <0xffffee00 0x200>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dbgu>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart0: serial@fff8c000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfff8c000 0x200>; +- interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart1: serial@fff90000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfff90000 0x200>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart2: serial@fff94000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfff94000 0x200>; +- interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- ssc0: ssc@fff98000 { +- compatible = "atmel,at91rm9200-ssc"; +- reg = <0xfff98000 0x4000>; +- interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; +- clock-names = "pclk"; +- status = "disabled"; +- }; +- +- ssc1: ssc@fff9c000 { +- compatible = "atmel,at91rm9200-ssc"; +- reg = <0xfff9c000 0x4000>; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; +- clock-names = "pclk"; +- status = "disabled"; +- }; +- +- ac97: sound@fffa0000 { +- compatible = "atmel,at91sam9263-ac97c"; +- reg = <0xfffa0000 0x4000>; +- interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ac97>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; +- clock-names = "ac97_clk"; +- status = "disabled"; +- }; +- +- macb0: ethernet@fffbc000 { +- compatible = "cdns,at91sam9260-macb", "cdns,macb"; +- reg = <0xfffbc000 0x100>; +- interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_macb_rmii>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 21>; +- clock-names = "hclk", "pclk"; +- status = "disabled"; +- }; +- +- usb1: gadget@fff78000 { +- compatible = "atmel,at91sam9263-udc"; +- reg = <0xfff78000 0x4000>; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_SYSTEM 7>; +- clock-names = "pclk", "hclk"; +- status = "disabled"; +- }; +- +- i2c0: i2c@fff88000 { +- compatible = "atmel,at91sam9260-i2c"; +- reg = <0xfff88000 0x100>; +- interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; +- status = "disabled"; +- }; +- +- mmc0: mmc@fff80000 { +- compatible = "atmel,hsmci"; +- reg = <0xfff80000 0x600>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; +- clock-names = "mci_clk"; +- status = "disabled"; +- }; +- +- mmc1: mmc@fff84000 { +- compatible = "atmel,hsmci"; +- reg = <0xfff84000 0x600>; +- interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; +- clock-names = "mci_clk"; +- status = "disabled"; +- }; +- +- watchdog@fffffd40 { +- compatible = "atmel,at91sam9260-wdt"; +- reg = <0xfffffd40 0x10>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&slow_xtal>; +- atmel,watchdog-type = "hardware"; +- atmel,reset-type = "all"; +- atmel,dbg-halt; +- status = "disabled"; +- }; +- +- spi0: spi@fffa4000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xfffa4000 0x200>; +- interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; +- clock-names = "spi_clk"; +- status = "disabled"; +- }; +- +- spi1: spi@fffa8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xfffa8000 0x200>; +- interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; +- clock-names = "spi_clk"; +- status = "disabled"; +- }; +- +- pwm0: pwm@fffb8000 { +- compatible = "atmel,at91sam9rl-pwm"; +- reg = <0xfffb8000 0x300>; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>; +- #pwm-cells = <3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; +- clock-names = "pwm_clk"; +- status = "disabled"; +- }; +- +- can: can@fffac000 { +- compatible = "atmel,at91sam9263-can"; +- reg = <0xfffac000 0x300>; +- interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can_rx_tx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; +- clock-names = "can_clk"; +- }; +- +- rtc@fffffd20 { +- compatible = "atmel,at91sam9260-rtt"; +- reg = <0xfffffd20 0x10>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&slow_xtal>; +- status = "disabled"; +- }; +- +- rtc@fffffd50 { +- compatible = "atmel,at91sam9260-rtt"; +- reg = <0xfffffd50 0x10>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&slow_xtal>; +- status = "disabled"; +- }; +- +- gpbr: syscon@fffffd60 { +- compatible = "atmel,at91sam9260-gpbr", "syscon"; +- reg = <0xfffffd60 0x50>; +- status = "disabled"; +- }; +- }; +- +- fb0: fb@700000 { +- compatible = "atmel,at91sam9263-lcdc"; +- reg = <0x00700000 0x1000>; +- interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fb>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 26>; +- clock-names = "lcdc_clk", "hclk"; +- status = "disabled"; +- }; +- +- usb0: ohci@a00000 { +- compatible = "atmel,at91rm9200-ohci", "usb-ohci"; +- reg = <0x00a00000 0x100000>; +- interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_SYSTEM 6>; +- clock-names = "ohci_clk", "hclk", "uhpck"; +- status = "disabled"; +- }; +- +- ebi0: ebi@10000000 { +- compatible = "atmel,at91sam9263-ebi0"; +- #address-cells = <2>; +- #size-cells = <1>; +- atmel,smc = <&smc0>; +- atmel,matrix = <&matrix>; +- reg = <0x10000000 0x80000000>; +- ranges = <0x0 0x0 0x10000000 0x10000000 +- 0x1 0x0 0x20000000 0x10000000 +- 0x2 0x0 0x30000000 0x10000000 +- 0x3 0x0 0x40000000 0x10000000 +- 0x4 0x0 0x50000000 0x10000000 +- 0x5 0x0 0x60000000 0x10000000>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- status = "disabled"; +- +- nand_controller0: nand-controller { +- compatible = "atmel,at91sam9260-nand-controller"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- }; +- }; +- +- ebi1: ebi@70000000 { +- compatible = "atmel,at91sam9263-ebi1"; +- #address-cells = <2>; +- #size-cells = <1>; +- atmel,smc = <&smc1>; +- atmel,matrix = <&matrix>; +- reg = <0x80000000 0x20000000>; +- ranges = <0x0 0x0 0x80000000 0x10000000 +- 0x1 0x0 0x90000000 0x10000000>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- status = "disabled"; +- +- nand_controller1: nand-controller { +- compatible = "atmel,at91sam9260-nand-controller"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- }; +- }; +- }; +- +- i2c-gpio-0 { +- compatible = "i2c-gpio"; +- gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ +- &pioB 5 GPIO_ACTIVE_HIGH /* scl */ +- >; +- i2c-gpio,sda-open-drain; +- i2c-gpio,scl-open-drain; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9263ek.dts b/scripts/dtc/include-prefixes/arm/at91sam9263ek.dts +deleted file mode 100644 +index 71f60576761a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9263ek.dts ++++ /dev/null +@@ -1,258 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9263ek.dts - Device Tree file for Atmel at91sam9263 reference board +- * +- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +-/dts-v1/; +-#include "at91sam9263.dtsi" +- +-/ { +- model = "Atmel at91sam9263ek"; +- compatible = "atmel,at91sam9263ek", "atmel,at91sam9263", "atmel,at91sam9"; +- +- chosen { +- bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <16367660>; +- }; +- }; +- +- ahb { +- apb { +- dbgu: serial@ffffee00 { +- status = "okay"; +- }; +- +- tcb0: timer@fff7c000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +- }; +- +- usart0: serial@fff8c000 { +- pinctrl-0 = < +- &pinctrl_usart0 +- &pinctrl_usart0_rts +- &pinctrl_usart0_cts>; +- status = "okay"; +- }; +- +- macb0: ethernet@fffbc000 { +- phy-mode = "rmii"; +- status = "okay"; +- }; +- +- usb1: gadget@fff78000 { +- atmel,vbus-gpio = <&pioA 25 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- mmc0: mmc@fff80000 { +- pinctrl-0 = < +- &pinctrl_board_mmc0 +- &pinctrl_mmc0_clk +- &pinctrl_mmc0_slot0_cmd_dat0 +- &pinctrl_mmc0_slot0_dat1_3>; +- pinctrl-names = "default"; +- status = "okay"; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioE 18 GPIO_ACTIVE_HIGH>; +- wp-gpios = <&pioE 19 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- pinctrl@fffff200 { +- mmc0 { +- pinctrl_board_mmc0: mmc0-board { +- atmel,pins = +- ; /* PE19 gpio WP pin pull up */ +- }; +- }; +- }; +- +- spi0: spi@fffa4000 { +- status = "okay"; +- cs-gpios = <&pioA 5 0>, <0>, <0>, <0>; +- mtd_dataflash@0 { +- compatible = "atmel,at45", "atmel,dataflash"; +- spi-max-frequency = <50000000>; +- reg = <0>; +- }; +- }; +- +- watchdog@fffffd40 { +- status = "okay"; +- }; +- }; +- +- fb0: fb@700000 { +- display = <&display0>; +- status = "okay"; +- +- display0: panel { +- bits-per-pixel = <16>; +- atmel,lcdcon-backlight; +- atmel,dmacon = <0x1>; +- atmel,lcdcon2 = <0x80008002>; +- atmel,guard-time = <1>; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing0 { +- clock-frequency = <4965000>; +- hactive = <240>; +- vactive = <320>; +- hback-porch = <1>; +- hfront-porch = <33>; +- vback-porch = <1>; +- vfront-porch = <0>; +- hsync-len = <5>; +- vsync-len = <1>; +- hsync-active = <1>; +- vsync-active = <1>; +- }; +- }; +- }; +- }; +- +- ebi0: ebi@10000000 { +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; +- pinctrl-names = "default"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "soft"; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x20000>; +- }; +- +- barebox@20000 { +- label = "barebox"; +- reg = <0x20000 0x40000>; +- }; +- +- bareboxenv@60000 { +- label = "bareboxenv"; +- reg = <0x60000 0x20000>; +- }; +- +- bareboxenv2@80000 { +- label = "bareboxenv2"; +- reg = <0x80000 0x20000>; +- }; +- +- oftree@80000 { +- label = "oftree"; +- reg = <0xa0000 0x20000>; +- }; +- +- kernel@a0000 { +- label = "kernel"; +- reg = <0xc0000 0x400000>; +- }; +- +- rootfs@4a0000 { +- label = "rootfs"; +- reg = <0x4c0000 0x7800000>; +- }; +- +- data@7ca0000 { +- label = "data"; +- reg = <0x7cc0000 0x8340000>; +- }; +- }; +- }; +- }; +- }; +- +- usb0: ohci@a00000 { +- num-ports = <2>; +- status = "okay"; +- atmel,vbus-gpio = <&pioA 24 GPIO_ACTIVE_HIGH +- &pioA 21 GPIO_ACTIVE_HIGH +- >; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- d3 { +- label = "d3"; +- gpios = <&pioB 7 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- d2 { +- label = "d2"; +- gpios = <&pioC 29 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "nand-disk"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- left_click { +- label = "left_click"; +- gpios = <&pioC 5 GPIO_ACTIVE_LOW>; +- linux,code = <272>; +- wakeup-source; +- }; +- +- right_click { +- label = "right_click"; +- gpios = <&pioC 4 GPIO_ACTIVE_LOW>; +- linux,code = <273>; +- wakeup-source; +- }; +- }; +- +- i2c-gpio-0 { +- status = "okay"; +- +- 24c512@50 { +- compatible = "atmel,24c512"; +- reg = <0x50>; +- pagesize = <128>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9g15.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9g15.dtsi +deleted file mode 100644 +index dde88276fe52..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9g15.dtsi ++++ /dev/null +@@ -1,28 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9g15.dtsi - Device Tree Include file for AT91SAM9G15 SoC +- * +- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +- +-#include "at91sam9x5.dtsi" +-#include "at91sam9x5_lcd.dtsi" +- +-/ { +- model = "Atmel AT91SAM9G15 SoC"; +- compatible = "atmel,at91sam9g15", "atmel,at91sam9x5"; +-}; +- +-&pinctrl { +- atmel,mux-mask = < +- /* A B C */ +- 0xffffffff 0xffe0399f 0x00000000 /* pioA */ +- 0x00040000 0x00047e3f 0x00000000 /* pioB */ +- 0xfdffffff 0x00000000 0xb83fffff /* pioC */ +- 0x003fffff 0x003f8000 0x00000000 /* pioD */ +- >; +-}; +- +-&pmc { +- compatible = "atmel,at91sam9g15-pmc", "atmel,at91sam9x5-pmc", "syscon"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9g15ek.dts b/scripts/dtc/include-prefixes/arm/at91sam9g15ek.dts +deleted file mode 100644 +index 889a5097eb2d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9g15ek.dts ++++ /dev/null +@@ -1,36 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91sam9g15ek.dts - Device Tree file for AT91SAM9G15-EK board +- * +- * Copyright (C) 2012 Atmel, +- * 2012 Nicolas Ferre +- */ +-/dts-v1/; +-#include "at91sam9g15.dtsi" +-#include "at91sam9x5dm.dtsi" +-#include "at91sam9x5ek.dtsi" +- +-/ { +- model = "Atmel AT91SAM9G15-EK"; +- compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; +- +- backlight: backlight { +- status = "okay"; +- }; +- +- bl_reg: backlight_regulator { +- status = "okay"; +- }; +- +- panel: panel { +- status = "okay"; +- }; +- +- panel_reg: panel_regulator { +- status = "okay"; +- }; +-}; +- +-&hlcdc { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9g20.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9g20.dtsi +deleted file mode 100644 +index 708e1646b7f4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9g20.dtsi ++++ /dev/null +@@ -1,49 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC +- * +- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +- +-#include "at91sam9260.dtsi" +- +-/ { +- model = "Atmel AT91SAM9G20 family SoC"; +- compatible = "atmel,at91sam9g20"; +- +- memory@20000000 { +- reg = <0x20000000 0x08000000>; +- }; +- +- sram0: sram@2ff000 { +- status = "disabled"; +- }; +- +- sram1: sram@2fc000 { +- compatible = "mmio-sram"; +- reg = <0x002fc000 0x8000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x002fc000 0x8000>; +- }; +- +- ahb { +- apb { +- i2c0: i2c@fffac000 { +- compatible = "atmel,at91sam9g20-i2c"; +- }; +- +- ssc0: ssc@fffbc000 { +- compatible = "atmel,at91sam9rl-ssc"; +- }; +- +- adc0: adc@fffe0000 { +- atmel,adc-startup-time = <40>; +- }; +- +- pmc: pmc@fffffc00 { +- compatible = "atmel,at91sam9g20-pmc", "atmel,at91sam9260-pmc", "syscon"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9g20ek.dts b/scripts/dtc/include-prefixes/arm/at91sam9g20ek.dts +deleted file mode 100644 +index 6de7a7cd3c07..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9g20ek.dts ++++ /dev/null +@@ -1,28 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board +- * +- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +-/dts-v1/; +-#include "at91sam9g20ek_common.dtsi" +- +-/ { +- model = "Atmel at91sam9g20ek"; +- compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9"; +- +- leds { +- compatible = "gpio-leds"; +- +- ds1 { +- label = "ds1"; +- gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- ds5 { +- label = "ds5"; +- gpios = <&pioA 6 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9g20ek_2mmc.dts b/scripts/dtc/include-prefixes/arm/at91sam9g20ek_2mmc.dts +deleted file mode 100644 +index 2db95e8ffc64..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9g20ek_2mmc.dts ++++ /dev/null +@@ -1,54 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9g20ek_2mmc.dts - Device Tree file for Atmel at91sam9g20ek 2 MMC board +- * +- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +-/dts-v1/; +-#include "at91sam9g20ek_common.dtsi" +- +-/ { +- model = "Atmel at91sam9g20ek 2 mmc"; +- compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9"; +- +- ahb { +- apb{ +- mmc0: mmc@fffa8000 { +- /* clk already mux wuth slot0 */ +- pinctrl-0 = < +- &pinctrl_board_mmc0_slot0 +- &pinctrl_mmc0_slot0_cmd_dat0 +- &pinctrl_mmc0_slot0_dat1_3>; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioC 2 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- pinctrl@fffff400 { +- mmc0_slot0 { +- pinctrl_board_mmc0_slot0: mmc0_slot0-board { +- atmel,pins = +- ; /* PC2 gpio CD pin pull up and deglitch */ +- }; +- }; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- ds1 { +- label = "ds1"; +- gpios = <&pioB 9 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- ds5 { +- label = "ds5"; +- gpios = <&pioB 8 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9g20ek_common.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9g20ek_common.dtsi +deleted file mode 100644 +index 87bb39060e8b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9g20ek_common.dtsi ++++ /dev/null +@@ -1,257 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9g20ek_common.dtsi - Device Tree file for Atmel at91sam9g20ek board +- * +- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +-#include "at91sam9g20.dtsi" +-#include +- +-/ { +- +- chosen { +- bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <18432000>; +- }; +- }; +- +- ahb { +- apb { +- pinctrl@fffff400 { +- board { +- pinctrl_pck0_as_mck: pck0_as_mck { +- atmel,pins = +- ; /* PC1 periph B */ +- }; +- +- }; +- +- mmc0_slot1 { +- pinctrl_board_mmc0_slot1: mmc0_slot1-board { +- atmel,pins = +- ; /* PC9 gpio CD pin pull up and deglitch */ +- }; +- }; +- }; +- +- dbgu: serial@fffff200 { +- status = "okay"; +- }; +- +- tcb0: timer@fffa0000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +- }; +- +- usart0: serial@fffb0000 { +- pinctrl-0 = +- <&pinctrl_usart0 +- &pinctrl_usart0_rts +- &pinctrl_usart0_cts +- &pinctrl_usart0_dtr_dsr +- &pinctrl_usart0_dcd +- &pinctrl_usart0_ri>; +- status = "okay"; +- }; +- +- usart1: serial@fffb4000 { +- status = "okay"; +- }; +- +- macb0: ethernet@fffc4000 { +- phy-mode = "rmii"; +- status = "okay"; +- }; +- +- usb1: gadget@fffa4000 { +- atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- mmc0: mmc@fffa8000 { +- pinctrl-0 = < +- &pinctrl_board_mmc0_slot1 +- &pinctrl_mmc0_clk +- &pinctrl_mmc0_slot1_cmd_dat0 +- &pinctrl_mmc0_slot1_dat1_3>; +- pinctrl-names = "default"; +- status = "okay"; +- slot@1 { +- reg = <1>; +- bus-width = <4>; +- cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- ssc0: ssc@fffbc000 { +- status = "okay"; +- pinctrl-0 = <&pinctrl_ssc0_tx>; +- }; +- +- spi0: spi@fffc8000 { +- cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; +- mtd_dataflash@1 { +- compatible = "atmel,at45", "atmel,dataflash"; +- spi-max-frequency = <50000000>; +- reg = <1>; +- }; +- }; +- +- shdwc@fffffd10 { +- atmel,wakeup-counter = <10>; +- atmel,wakeup-rtt-timer; +- }; +- +- rtc@fffffd20 { +- atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +- status = "okay"; +- }; +- +- watchdog@fffffd40 { +- status = "okay"; +- }; +- +- gpbr: syscon@fffffd50 { +- status = "okay"; +- }; +- }; +- +- ebi: ebi@10000000 { +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; +- pinctrl-names = "default"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "soft"; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x20000>; +- }; +- +- barebox@20000 { +- label = "barebox"; +- reg = <0x20000 0x40000>; +- }; +- +- bareboxenv@60000 { +- label = "bareboxenv"; +- reg = <0x60000 0x20000>; +- }; +- +- bareboxenv2@80000 { +- label = "bareboxenv2"; +- reg = <0x80000 0x20000>; +- }; +- +- oftree@80000 { +- label = "oftree"; +- reg = <0xa0000 0x20000>; +- }; +- +- kernel@a0000 { +- label = "kernel"; +- reg = <0xc0000 0x400000>; +- }; +- +- rootfs@4a0000 { +- label = "rootfs"; +- reg = <0x4c0000 0x7800000>; +- }; +- +- data@7ca0000 { +- label = "data"; +- reg = <0x7cc0000 0x8340000>; +- }; +- }; +- }; +- }; +- }; +- +- usb0: ohci@500000 { +- num-ports = <2>; +- status = "okay"; +- }; +- }; +- +- i2c-gpio-0 { +- status = "okay"; +- +- 24c512@50 { +- compatible = "atmel,24c512"; +- reg = <0x50>; +- }; +- +- wm8731: wm8731@1b { +- compatible = "wm8731"; +- reg = <0x1b>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- btn3 { +- label = "Button 3"; +- gpios = <&pioA 30 GPIO_ACTIVE_LOW>; +- linux,code = <0x103>; +- wakeup-source; +- }; +- +- btn4 { +- label = "Button 4"; +- gpios = <&pioA 31 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- sound { +- compatible = "atmel,at91sam9g20ek-wm8731-audio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pck0_as_mck>; +- +- atmel,model = "wm8731 @ AT91SAMG20EK"; +- +- atmel,audio-routing = +- "Ext Spk", "LHPOUT", +- "Int Mic", "MICIN"; +- +- atmel,ssc-controller = <&ssc0>; +- atmel,audio-codec = <&wm8731>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9g25-gardena-smart-gateway.dts b/scripts/dtc/include-prefixes/arm/at91sam9g25-gardena-smart-gateway.dts +deleted file mode 100644 +index 7da70aeeb528..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9g25-gardena-smart-gateway.dts ++++ /dev/null +@@ -1,158 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Device Tree file for the GARDENA smart Gateway (Article No. 19000) +- * +- * Copyright (C) 2020 GARDENA GmbH +- */ +- +-/dts-v1/; +- +-#include "at91sam9g25.dtsi" +-#include "at91sam9x5ek.dtsi" +-#include +- +-/ { +- model = "GARDENA smart Gateway (Article No. 19000)"; +- compatible = "gardena,smart-gateway-at91sam", "atmel,at91sam9g25", "atmel,at91sam9x5", +- "atmel,at91sam9"; +- +- aliases { +- serial1 = &usart3; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user_btn1 { +- label = "USER_BTN1"; +- gpios = <&pioA 24 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- 1wire_cm { +- status = "disabled"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- power_blue { +- label = "smartgw:power:blue"; +- gpios = <&pioC 21 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- power_green { +- label = "smartgw:power:green"; +- gpios = <&pioC 20 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- power_red { +- label = "smartgw:power:red"; +- gpios = <&pioC 19 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- radio_blue { +- label = "smartgw:radio:blue"; +- gpios = <&pioC 18 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- radio_green { +- label = "smartgw:radio:green"; +- gpios = <&pioC 17 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- radio_red { +- label = "smartgw:radio:red"; +- gpios = <&pioC 16 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- internet_blue { +- label = "smartgw:internet:blue"; +- gpios = <&pioC 15 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- internet_green { +- label = "smartgw:internet:green"; +- gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- internet_red { +- label = "smartgw:internet:red"; +- gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- heartbeat { +- label = "smartgw:heartbeat"; +- gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- pb18 { +- status = "disabled"; +- }; +- +- pd21 { +- status = "disabled"; +- }; +- }; +-}; +- +-&macb0 { +- phy-mode = "rmii"; +- status = "okay"; +-}; +- +-&usart0 { +- status = "disabled"; +-}; +- +-&usart2 { +- status = "disabled"; +-}; +- +-&usart3 { +- status = "okay"; +- +- pinctrl-0 = <&pinctrl_usart3 +- &pinctrl_usart3_rts +- &pinctrl_usart3_cts +- >; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-&mmc0 { +- status = "disabled"; +-}; +- +-&mmc1 { +- status = "disabled"; +-}; +- +-&spi0 { +- status = "disabled"; +-}; +- +-&i2c0 { +- status = "disabled"; +-}; +- +-&adc0 { +- status = "disabled"; +-}; +- +-&ssc0 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9g25.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9g25.dtsi +deleted file mode 100644 +index d2f13afb35ea..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9g25.dtsi ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9g25.dtsi - Device Tree Include file for AT91SAM9G25 SoC +- * +- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +- +-#include "at91sam9x5.dtsi" +-#include "at91sam9x5_isi.dtsi" +-#include "at91sam9x5_usart3.dtsi" +-#include "at91sam9x5_macb0.dtsi" +- +-/ { +- model = "Atmel AT91SAM9G25 SoC"; +- compatible = "atmel,at91sam9g25", "atmel,at91sam9x5"; +- +- ahb { +- apb { +- pinctrl@fffff400 { +- atmel,mux-mask = < +- /* A B C */ +- 0xffffffff 0xffe0399f 0xc000001c /* pioA */ +- 0x0007ffff 0x00047e3f 0x00000000 /* pioB */ +- 0x80000000 0x07c0ffff 0xb83fffff /* pioC */ +- 0x003fffff 0x003f8000 0x00000000 /* pioD */ +- >; +- }; +- +- pmc: pmc@fffffc00 { +- compatible = "atmel,at91sam9g25-pmc", "atmel,at91sam9x5-pmc", "syscon"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9g25ek.dts b/scripts/dtc/include-prefixes/arm/at91sam9g25ek.dts +deleted file mode 100644 +index 61b0bdb615dc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9g25ek.dts ++++ /dev/null +@@ -1,65 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board +- * +- * Copyright (C) 2012 Atmel, +- * 2012 Nicolas Ferre +- */ +-/dts-v1/; +-#include "at91sam9g25.dtsi" +-#include "at91sam9x5ek.dtsi" +- +-/ { +- model = "Atmel AT91SAM9G25-EK"; +- compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; +-}; +- +-&i2c0 { +- camera@30 { +- compatible = "ovti,ov2640"; +- reg = <0x30>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; +- resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>; +- pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>; +- clocks = <&pmc PMC_TYPE_SYSTEM 8>; +- clock-names = "xvclk"; +- assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>; +- assigned-clock-rates = <25000000>; +- status = "okay"; +- +- port { +- ov2640_0: endpoint { +- remote-endpoint = <&isi_0>; +- bus-width = <8>; +- }; +- }; +- }; +-}; +- +-&isi { +- status = "okay"; +- +- port { +- isi_0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&ov2640_0>; +- bus-width = <8>; +- vsync-active = <1>; +- hsync-active = <1>; +- }; +- }; +-}; +- +-&macb0 { +- phy-mode = "rmii"; +- status = "okay"; +-}; +- +-&mmc1 { +- status = "disabled"; +-}; +- +-&spi0 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9g35.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9g35.dtsi +deleted file mode 100644 +index 48c2bc4a7753..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9g35.dtsi ++++ /dev/null +@@ -1,33 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9g35.dtsi - Device Tree Include file for AT91SAM9G35 SoC +- * +- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +- +-#include "at91sam9x5.dtsi" +-#include "at91sam9x5_lcd.dtsi" +-#include "at91sam9x5_macb0.dtsi" +- +-/ { +- model = "Atmel AT91SAM9G35 SoC"; +- compatible = "atmel,at91sam9g35", "atmel,at91sam9x5"; +- +- ahb { +- apb { +- pinctrl@fffff400 { +- atmel,mux-mask = < +- /* A B C */ +- 0xffffffff 0xffe0399f 0xc000000c /* pioA */ +- 0x000406ff 0x00047e3f 0x00000000 /* pioB */ +- 0xfdffffff 0x00000000 0xb83fffff /* pioC */ +- 0x003fffff 0x003f8000 0x00000000 /* pioD */ +- >; +- }; +- +- pmc: pmc@fffffc00 { +- compatible = "atmel,at91sam9g35-pmc", "atmel,at91sam9x5-pmc", "syscon"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9g35ek.dts b/scripts/dtc/include-prefixes/arm/at91sam9g35ek.dts +deleted file mode 100644 +index f966b56de63c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9g35ek.dts ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91sam9g35ek.dts - Device Tree file for AT91SAM9G35-EK board +- * +- * Copyright (C) 2012 Atmel, +- * 2012 Nicolas Ferre +- */ +-/dts-v1/; +-#include "at91sam9g35.dtsi" +-#include "at91sam9x5dm.dtsi" +-#include "at91sam9x5ek.dtsi" +- +-/ { +- model = "Atmel AT91SAM9G35-EK"; +- compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; +- +- backlight: backlight { +- status = "okay"; +- }; +- +- bl_reg: backlight_regulator { +- status = "okay"; +- }; +- +- panel: panel { +- status = "okay"; +- }; +- +- panel_reg: panel_regulator { +- status = "okay"; +- }; +-}; +- +-&hlcdc { +- status = "okay"; +-}; +- +-&macb0 { +- phy-mode = "rmii"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9g45.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9g45.dtsi +deleted file mode 100644 +index 2ab730fd6472..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9g45.dtsi ++++ /dev/null +@@ -1,1017 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC +- * applies to AT91SAM9G45, AT91SAM9M10, +- * AT91SAM9G46, AT91SAM9M11 SoC +- * +- * Copyright (C) 2011 Atmel, +- * 2011 Nicolas Ferre +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Atmel AT91SAM9G45 family SoC"; +- compatible = "atmel,at91sam9g45"; +- interrupt-parent = <&aic>; +- +- aliases { +- serial0 = &dbgu; +- serial1 = &usart0; +- serial2 = &usart1; +- serial3 = &usart2; +- serial4 = &usart3; +- gpio0 = &pioA; +- gpio1 = &pioB; +- gpio2 = &pioC; +- gpio3 = &pioD; +- gpio4 = &pioE; +- tcb0 = &tcb0; +- tcb1 = &tcb1; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- ssc0 = &ssc0; +- ssc1 = &ssc1; +- pwm0 = &pwm0; +- }; +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,arm926ej-s"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- memory@70000000 { +- device_type = "memory"; +- reg = <0x70000000 0x10000000>; +- }; +- +- clocks { +- slow_xtal: slow_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- main_xtal: main_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- adc_op_clk: adc_op_clk{ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <300000>; +- }; +- }; +- +- sram: sram@300000 { +- compatible = "mmio-sram"; +- reg = <0x00300000 0x10000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00300000 0x10000>; +- }; +- +- ahb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- apb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- aic: interrupt-controller@fffff000 { +- #interrupt-cells = <3>; +- compatible = "atmel,at91rm9200-aic"; +- interrupt-controller; +- reg = <0xfffff000 0x200>; +- atmel,external-irqs = <31>; +- }; +- +- ramc0: ramc@ffffe400 { +- compatible = "atmel,at91sam9g45-ddramc"; +- reg = <0xffffe400 0x200>; +- clocks = <&pmc PMC_TYPE_SYSTEM 2>; +- clock-names = "ddrck"; +- }; +- +- ramc1: ramc@ffffe600 { +- compatible = "atmel,at91sam9g45-ddramc"; +- reg = <0xffffe600 0x200>; +- clocks = <&pmc PMC_TYPE_SYSTEM 2>; +- clock-names = "ddrck"; +- }; +- +- smc: smc@ffffe800 { +- compatible = "atmel,at91sam9260-smc", "syscon"; +- reg = <0xffffe800 0x200>; +- }; +- +- matrix: matrix@ffffea00 { +- compatible = "atmel,at91sam9g45-matrix", "syscon"; +- reg = <0xffffea00 0x200>; +- }; +- +- pmc: pmc@fffffc00 { +- compatible = "atmel,at91sam9g45-pmc", "syscon"; +- reg = <0xfffffc00 0x100>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- #clock-cells = <2>; +- clocks = <&clk32k>, <&main_xtal>; +- clock-names = "slow_clk", "main_xtal"; +- }; +- +- rstc@fffffd00 { +- compatible = "atmel,at91sam9g45-rstc"; +- reg = <0xfffffd00 0x10>; +- clocks = <&clk32k>; +- }; +- +- pit: timer@fffffd30 { +- compatible = "atmel,at91sam9260-pit"; +- reg = <0xfffffd30 0xf>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- }; +- +- +- shdwc@fffffd10 { +- compatible = "atmel,at91sam9rl-shdwc"; +- reg = <0xfffffd10 0x10>; +- clocks = <&clk32k>; +- }; +- +- tcb0: timer@fff7c000 { +- compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xfff7c000 0x100>; +- interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; +- clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; +- }; +- +- tcb1: timer@fffd4000 { +- compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xfffd4000 0x100>; +- interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; +- clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; +- }; +- +- dma: dma-controller@ffffec00 { +- compatible = "atmel,at91sam9g45-dma"; +- reg = <0xffffec00 0x200>; +- interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; +- #dma-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; +- clock-names = "dma_clk"; +- }; +- +- pinctrl@fffff200 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; +- ranges = <0xfffff200 0xfffff200 0xa00>; +- +- atmel,mux-mask = < +- /* A B */ +- 0xffffffff 0xffc003ff /* pioA */ +- 0xffffffff 0x800f8f00 /* pioB */ +- 0xffffffff 0x00000e00 /* pioC */ +- 0xffffffff 0xff0c1381 /* pioD */ +- 0xffffffff 0x81ffff81 /* pioE */ +- >; +- +- /* shared pinctrl settings */ +- ac97 { +- pinctrl_ac97: ac97-0 { +- atmel,pins = +- ; /* AC97CK */ +- }; +- }; +- +- adc0 { +- pinctrl_adc0_adtrg: adc0_adtrg { +- atmel,pins = ; +- }; +- pinctrl_adc0_ad0: adc0_ad0 { +- atmel,pins = ; +- }; +- pinctrl_adc0_ad1: adc0_ad1 { +- atmel,pins = ; +- }; +- pinctrl_adc0_ad2: adc0_ad2 { +- atmel,pins = ; +- }; +- pinctrl_adc0_ad3: adc0_ad3 { +- atmel,pins = ; +- }; +- pinctrl_adc0_ad4: adc0_ad4 { +- atmel,pins = ; +- }; +- pinctrl_adc0_ad5: adc0_ad5 { +- atmel,pins = ; +- }; +- pinctrl_adc0_ad6: adc0_ad6 { +- atmel,pins = ; +- }; +- pinctrl_adc0_ad7: adc0_ad7 { +- atmel,pins = ; +- }; +- }; +- +- dbgu { +- pinctrl_dbgu: dbgu-0 { +- atmel,pins = +- ; +- }; +- }; +- +- i2c0 { +- pinctrl_i2c0: i2c0-0 { +- atmel,pins = +- ; /* PA20 periph A TWD0 */ +- }; +- }; +- +- i2c1 { +- pinctrl_i2c1: i2c1-0 { +- atmel,pins = +- ; /* PB10 periph A TWD1 */ +- }; +- }; +- +- isi { +- pinctrl_isi_data_0_7: isi-0-data-0-7 { +- atmel,pins = +- ; /* HSYNC */ +- }; +- +- pinctrl_isi_data_8_9: isi-0-data-8-9 { +- atmel,pins = +- ; /* D9 */ +- }; +- +- pinctrl_isi_data_10_11: isi-0-data-10-11 { +- atmel,pins = +- ; /* D11 */ +- }; +- }; +- +- usart0 { +- pinctrl_usart0: usart0-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart0_rts: usart0_rts-0 { +- atmel,pins = +- ; /* PB17 periph B */ +- }; +- +- pinctrl_usart0_cts: usart0_cts-0 { +- atmel,pins = +- ; /* PB15 periph B */ +- }; +- }; +- +- usart1 { +- pinctrl_usart1: usart1-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart1_rts: usart1_rts-0 { +- atmel,pins = +- ; /* PD16 periph A */ +- }; +- +- pinctrl_usart1_cts: usart1_cts-0 { +- atmel,pins = +- ; /* PD17 periph A */ +- }; +- }; +- +- usart2 { +- pinctrl_usart2: usart2-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart2_rts: usart2_rts-0 { +- atmel,pins = +- ; /* PC9 periph B */ +- }; +- +- pinctrl_usart2_cts: usart2_cts-0 { +- atmel,pins = +- ; /* PC11 periph B */ +- }; +- }; +- +- usart3 { +- pinctrl_usart3: usart3-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart3_rts: usart3_rts-0 { +- atmel,pins = +- ; /* PA23 periph B */ +- }; +- +- pinctrl_usart3_cts: usart3_cts-0 { +- atmel,pins = +- ; /* PA24 periph B */ +- }; +- }; +- +- nand { +- pinctrl_nand_rb: nand-rb-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_nand_cs: nand-cs-0 { +- atmel,pins = +- ; +- }; +- }; +- +- macb { +- pinctrl_macb_rmii: macb_rmii-0 { +- atmel,pins = +- ; /* PA19 periph A */ +- }; +- +- pinctrl_macb_rmii_mii: macb_rmii_mii-0 { +- atmel,pins = +- ; /* PA30 periph B */ +- }; +- }; +- +- mmc0 { +- pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { +- atmel,pins = +- ; /* PA2 periph A with pullup */ +- }; +- +- pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { +- atmel,pins = +- ; /* PA5 periph A with pullup */ +- }; +- +- pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { +- atmel,pins = +- ; /* PA9 periph A with pullup */ +- }; +- }; +- +- mmc1 { +- pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { +- atmel,pins = +- ; /* PA23 periph A with pullup */ +- }; +- +- pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { +- atmel,pins = +- ; /* PA26 periph A with pullup */ +- }; +- +- pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 { +- atmel,pins = +- ; /* PA30 periph A with pullup */ +- }; +- }; +- +- ssc0 { +- pinctrl_ssc0_tx: ssc0_tx-0 { +- atmel,pins = +- ; /* PD2 periph A */ +- }; +- +- pinctrl_ssc0_rx: ssc0_rx-0 { +- atmel,pins = +- ; /* PD5 periph A */ +- }; +- }; +- +- ssc1 { +- pinctrl_ssc1_tx: ssc1_tx-0 { +- atmel,pins = +- ; /* PD12 periph A */ +- }; +- +- pinctrl_ssc1_rx: ssc1_rx-0 { +- atmel,pins = +- ; /* PD15 periph A */ +- }; +- }; +- +- spi0 { +- pinctrl_spi0: spi0-0 { +- atmel,pins = +- ; /* PB2 periph A SPI0_SPCK pin */ +- }; +- }; +- +- spi1 { +- pinctrl_spi1: spi1-0 { +- atmel,pins = +- ; /* PB16 periph A SPI1_SPCK pin */ +- }; +- }; +- +- tcb0 { +- pinctrl_tcb0_tclk0: tcb0_tclk0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tclk1: tcb0_tclk1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tclk2: tcb0_tclk2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa0: tcb0_tioa0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa1: tcb0_tioa1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa2: tcb0_tioa2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob0: tcb0_tiob0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob1: tcb0_tiob1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob2: tcb0_tiob2-0 { +- atmel,pins = ; +- }; +- }; +- +- tcb1 { +- pinctrl_tcb1_tclk0: tcb1_tclk0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tclk1: tcb1_tclk1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tclk2: tcb1_tclk2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tioa0: tcb1_tioa0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tioa1: tcb1_tioa1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tioa2: tcb1_tioa2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tiob0: tcb1_tiob0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tiob1: tcb1_tiob1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tiob2: tcb1_tiob2-0 { +- atmel,pins = ; +- }; +- }; +- +- fb { +- pinctrl_fb: fb-0 { +- atmel,pins = +- ; /* PE30 periph A */ +- }; +- }; +- +- pioA: gpio@fffff200 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff200 0x200>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; +- }; +- +- pioB: gpio@fffff400 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff400 0x200>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; +- }; +- +- pioC: gpio@fffff600 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff600 0x200>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; +- }; +- +- pioD: gpio@fffff800 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff800 0x200>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; +- }; +- +- pioE: gpio@fffffa00 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffffa00 0x200>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; +- }; +- }; +- +- dbgu: serial@ffffee00 { +- compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; +- reg = <0xffffee00 0x200>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dbgu>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart0: serial@fff8c000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfff8c000 0x200>; +- interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart1: serial@fff90000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfff90000 0x200>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart2: serial@fff94000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfff94000 0x200>; +- interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart3: serial@fff98000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfff98000 0x200>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- macb0: ethernet@fffbc000 { +- compatible = "cdns,at91sam9260-macb", "cdns,macb"; +- reg = <0xfffbc000 0x100>; +- interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_macb_rmii>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_PERIPHERAL 25>; +- clock-names = "hclk", "pclk"; +- status = "disabled"; +- }; +- +- trng@fffcc000 { +- compatible = "atmel,at91sam9g45-trng"; +- reg = <0xfffcc000 0x100>; +- interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; +- }; +- +- i2c0: i2c@fff84000 { +- compatible = "atmel,at91sam9g10-i2c"; +- reg = <0xfff84000 0x100>; +- interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; +- status = "disabled"; +- }; +- +- i2c1: i2c@fff88000 { +- compatible = "atmel,at91sam9g10-i2c"; +- reg = <0xfff88000 0x100>; +- interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; +- status = "disabled"; +- }; +- +- ssc0: ssc@fff9c000 { +- compatible = "atmel,at91sam9g45-ssc"; +- reg = <0xfff9c000 0x4000>; +- interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; +- clock-names = "pclk"; +- status = "disabled"; +- }; +- +- ssc1: ssc@fffa0000 { +- compatible = "atmel,at91sam9g45-ssc"; +- reg = <0xfffa0000 0x4000>; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; +- clock-names = "pclk"; +- status = "disabled"; +- }; +- +- ac97: sound@fffac000 { +- compatible = "atmel,at91sam9263-ac97c"; +- reg = <0xfffac000 0x4000>; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ac97>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; +- clock-names = "ac97_clk"; +- status = "disabled"; +- }; +- +- adc0: adc@fffb0000 { +- compatible = "atmel,at91sam9g45-adc"; +- reg = <0xfffb0000 0x100>; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&adc_op_clk>; +- clock-names = "adc_clk", "adc_op_clk"; +- atmel,adc-channels-used = <0xff>; +- atmel,adc-vref = <3300>; +- atmel,adc-startup-time = <40>; +- }; +- +- isi@fffb4000 { +- compatible = "atmel,at91sam9g45-isi"; +- reg = <0xfffb4000 0x4000>; +- interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; +- clock-names = "isi_clk"; +- status = "disabled"; +- port { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- pwm0: pwm@fffb8000 { +- compatible = "atmel,at91sam9rl-pwm"; +- reg = <0xfffb8000 0x300>; +- interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; +- #pwm-cells = <3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; +- status = "disabled"; +- }; +- +- mmc0: mmc@fff80000 { +- compatible = "atmel,hsmci"; +- reg = <0xfff80000 0x600>; +- interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; +- dma-names = "rxtx"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; +- clock-names = "mci_clk"; +- status = "disabled"; +- }; +- +- mmc1: mmc@fffd0000 { +- compatible = "atmel,hsmci"; +- reg = <0xfffd0000 0x600>; +- interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; +- dma-names = "rxtx"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; +- clock-names = "mci_clk"; +- status = "disabled"; +- }; +- +- watchdog@fffffd40 { +- compatible = "atmel,at91sam9260-wdt"; +- reg = <0xfffffd40 0x10>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&clk32k>; +- atmel,watchdog-type = "hardware"; +- atmel,reset-type = "all"; +- atmel,dbg-halt; +- status = "disabled"; +- }; +- +- spi0: spi@fffa4000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xfffa4000 0x200>; +- interrupts = <14 4 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; +- clock-names = "spi_clk"; +- status = "disabled"; +- }; +- +- spi1: spi@fffa8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xfffa8000 0x200>; +- interrupts = <15 4 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; +- clock-names = "spi_clk"; +- status = "disabled"; +- }; +- +- usb2: gadget@fff78000 { +- compatible = "atmel,at91sam9g45-udc"; +- reg = <0x00600000 0x80000 +- 0xfff78000 0x400>; +- interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_CORE PMC_UTMI>; +- clock-names = "pclk", "hclk"; +- status = "disabled"; +- }; +- +- clk32k: sckc@fffffd50 { +- compatible = "atmel,at91sam9x5-sckc"; +- reg = <0xfffffd50 0x4>; +- clocks = <&slow_xtal>; +- #clock-cells = <0>; +- }; +- +- rtc@fffffd20 { +- compatible = "atmel,at91sam9260-rtt"; +- reg = <0xfffffd20 0x10>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&clk32k>; +- status = "disabled"; +- }; +- +- rtc@fffffdb0 { +- compatible = "atmel,at91rm9200-rtc"; +- reg = <0xfffffdb0 0x30>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&clk32k>; +- status = "disabled"; +- }; +- +- gpbr: syscon@fffffd60 { +- compatible = "atmel,at91sam9260-gpbr", "syscon"; +- reg = <0xfffffd60 0x10>; +- status = "disabled"; +- }; +- }; +- +- fb0: fb@500000 { +- compatible = "atmel,at91sam9g45-lcdc"; +- reg = <0x00500000 0x1000>; +- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fb>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>; +- clock-names = "hclk", "lcdc_clk"; +- status = "disabled"; +- }; +- +- usb0: ohci@700000 { +- compatible = "atmel,at91rm9200-ohci", "usb-ohci"; +- reg = <0x00700000 0x100000>; +- interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; +- clock-names = "ohci_clk", "hclk", "uhpck"; +- status = "disabled"; +- }; +- +- usb1: ehci@800000 { +- compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; +- reg = <0x00800000 0x100000>; +- interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; +- clock-names = "usb_clk", "ehci_clk"; +- status = "disabled"; +- }; +- +- ebi: ebi@10000000 { +- compatible = "atmel,at91sam9g45-ebi"; +- #address-cells = <2>; +- #size-cells = <1>; +- atmel,smc = <&smc>; +- atmel,matrix = <&matrix>; +- reg = <0x10000000 0x80000000>; +- ranges = <0x0 0x0 0x10000000 0x10000000 +- 0x1 0x0 0x20000000 0x10000000 +- 0x2 0x0 0x30000000 0x10000000 +- 0x3 0x0 0x40000000 0x10000000 +- 0x4 0x0 0x50000000 0x10000000 +- 0x5 0x0 0x60000000 0x10000000>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- status = "disabled"; +- +- nand_controller: nand-controller { +- compatible = "atmel,at91sam9g45-nand-controller"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- }; +- }; +- }; +- +- i2c-gpio-0 { +- compatible = "i2c-gpio"; +- gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */ +- &pioA 21 GPIO_ACTIVE_HIGH /* scl */ +- >; +- i2c-gpio,sda-open-drain; +- i2c-gpio,scl-open-drain; +- i2c-gpio,delay-us = <5>; /* ~100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9m10g45ek.dts b/scripts/dtc/include-prefixes/arm/at91sam9m10g45ek.dts +deleted file mode 100644 +index b6256a20fbc7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9m10g45ek.dts ++++ /dev/null +@@ -1,393 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board +- * +- * Copyright (C) 2011 Atmel, +- * 2011 Nicolas Ferre +- */ +-/dts-v1/; +-#include "at91sam9g45.dtsi" +-#include +- +-/ { +- model = "Atmel AT91SAM9M10G45-EK"; +- compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9"; +- +- chosen { +- bootargs = "mem=64M root=/dev/mtdblock1 rw rootfstype=jffs2"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@70000000 { +- reg = <0x70000000 0x4000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- ahb { +- apb { +- dbgu: serial@ffffee00 { +- status = "okay"; +- }; +- +- tcb0: timer@fff7c000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +- }; +- +- usart1: serial@fff90000 { +- pinctrl-0 = +- <&pinctrl_usart1 +- &pinctrl_usart1_rts +- &pinctrl_usart1_cts>; +- status = "okay"; +- }; +- +- macb0: ethernet@fffbc000 { +- phy-mode = "rmii"; +- status = "okay"; +- }; +- +- i2c0: i2c@fff84000 { +- status = "okay"; +- ov2640: camera@30 { +- compatible = "ovti,ov2640"; +- reg = <0x30>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; +- resetb-gpios = <&pioD 12 GPIO_ACTIVE_LOW>; +- pwdn-gpios = <&pioD 13 GPIO_ACTIVE_HIGH>; +- clocks = <&pmc PMC_TYPE_SYSTEM 9>; +- clock-names = "xvclk"; +- assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; +- assigned-clock-rates = <25000000>; +- +- port { +- ov2640_0: endpoint { +- remote-endpoint = <&isi_0>; +- bus-width = <8>; +- }; +- }; +- }; +- }; +- +- i2c1: i2c@fff88000 { +- status = "okay"; +- }; +- +- watchdog@fffffd40 { +- status = "okay"; +- }; +- +- mmc0: mmc@fff80000 { +- pinctrl-0 = < +- &pinctrl_board_mmc0 +- &pinctrl_mmc0_slot0_clk_cmd_dat0 +- &pinctrl_mmc0_slot0_dat1_3>; +- pinctrl-names = "default"; +- status = "okay"; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- mmc1: mmc@fffd0000 { +- pinctrl-0 = < +- &pinctrl_board_mmc1 +- &pinctrl_mmc1_slot0_clk_cmd_dat0 +- &pinctrl_mmc1_slot0_dat1_3>; +- pinctrl-names = "default"; +- status = "okay"; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>; +- wp-gpios = <&pioD 29 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- pinctrl@fffff200 { +- camera_sensor { +- pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_sensor_reset: sensor_reset-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_sensor_power: sensor_power-0 { +- atmel,pins = +- ; +- }; +- }; +- mmc0 { +- pinctrl_board_mmc0: mmc0-board { +- atmel,pins = +- ; /* PD10 gpio CD pin pull up and deglitch */ +- }; +- }; +- +- mmc1 { +- pinctrl_board_mmc1: mmc1-board { +- atmel,pins = +- ; /* PD29 gpio WP pin pull up */ +- }; +- }; +- +- pwm0 { +- pinctrl_pwm_leds: pwm-led { +- atmel,pins = +- ; /* PD31 periph B */ +- }; +- }; +- }; +- +- spi0: spi@fffa4000{ +- status = "okay"; +- cs-gpios = <&pioB 3 0>, <0>, <0>, <0>; +- mtd_dataflash@0 { +- compatible = "atmel,at45", "atmel,dataflash"; +- spi-max-frequency = <13000000>; +- reg = <0>; +- }; +- }; +- +- usb2: gadget@fff78000 { +- atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- ac97: sound@fffac000 { +- status = "okay"; +- }; +- +- adc0: adc@fffb0000 { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &pinctrl_adc0_ad0 +- &pinctrl_adc0_ad1 +- &pinctrl_adc0_ad2 +- &pinctrl_adc0_ad3 +- &pinctrl_adc0_ad4 +- &pinctrl_adc0_ad5 +- &pinctrl_adc0_ad6 +- &pinctrl_adc0_ad7>; +- atmel,adc-ts-wires = <4>; +- status = "okay"; +- }; +- +- isi@fffb4000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_isi_data_0_7>; +- status = "okay"; +- port { +- isi_0: endpoint { +- remote-endpoint = <&ov2640_0>; +- bus-width = <8>; +- vsync-active = <1>; +- hsync-active = <1>; +- }; +- }; +- }; +- +- pwm0: pwm@fffb8000 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm_leds>; +- }; +- +- rtc@fffffd20 { +- atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +- status = "okay"; +- }; +- +- gpbr: syscon@fffffd60 { +- status = "okay"; +- }; +- +- rtc@fffffdb0 { +- status = "okay"; +- }; +- }; +- +- fb0: fb@500000 { +- display = <&display0>; +- status = "okay"; +- +- display0: panel { +- bits-per-pixel = <32>; +- atmel,lcdcon-backlight; +- atmel,dmacon = <0x1>; +- atmel,lcdcon2 = <0x80008002>; +- atmel,guard-time = <9>; +- atmel,lcd-wiring-mode = "RGB"; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing0 { +- clock-frequency = <9000000>; +- hactive = <480>; +- vactive = <272>; +- hback-porch = <1>; +- hfront-porch = <1>; +- vback-porch = <40>; +- vfront-porch = <1>; +- hsync-len = <45>; +- vsync-len = <1>; +- }; +- }; +- }; +- }; +- +- ebi: ebi@10000000 { +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; +- pinctrl-names = "default"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioC 8 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "soft"; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- boot@0 { +- label = "bootstrap/uboot/kernel"; +- reg = <0x0 0x400000>; +- }; +- +- rootfs@400000 { +- label = "rootfs"; +- reg = <0x400000 0x3C00000>; +- }; +- +- data@4000000 { +- label = "data"; +- reg = <0x4000000 0xC000000>; +- }; +- }; +- }; +- }; +- }; +- +- usb0: ohci@700000 { +- status = "okay"; +- num-ports = <2>; +- atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW +- &pioD 3 GPIO_ACTIVE_LOW>; +- }; +- +- usb1: ehci@800000 { +- status = "okay"; +- }; +- }; +- +- led-controller-1 { +- compatible = "gpio-leds"; +- +- led-1 { +- label = "d8"; +- gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- led-controller-2 { +- compatible = "pwm-leds"; +- +- led-2 { +- label = "d6"; +- pwms = <&pwm0 3 5000 PWM_POLARITY_INVERTED>; +- max-brightness = <255>; +- linux,default-trigger = "nand-disk"; +- }; +- +- led-3 { +- label = "d7"; +- pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; +- max-brightness = <255>; +- linux,default-trigger = "mmc0"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- left_click { +- label = "left_click"; +- gpios = <&pioB 6 GPIO_ACTIVE_LOW>; +- linux,code = <272>; +- wakeup-source; +- }; +- +- right_click { +- label = "right_click"; +- gpios = <&pioB 7 GPIO_ACTIVE_LOW>; +- linux,code = <273>; +- wakeup-source; +- }; +- +- left { +- label = "Joystick Left"; +- gpios = <&pioB 14 GPIO_ACTIVE_LOW>; +- linux,code = <105>; +- }; +- +- right { +- label = "Joystick Right"; +- gpios = <&pioB 15 GPIO_ACTIVE_LOW>; +- linux,code = <106>; +- }; +- +- up { +- label = "Joystick Up"; +- gpios = <&pioB 16 GPIO_ACTIVE_LOW>; +- linux,code = <103>; +- }; +- +- down { +- label = "Joystick Down"; +- gpios = <&pioB 17 GPIO_ACTIVE_LOW>; +- linux,code = <108>; +- }; +- +- enter { +- label = "Joystick Press"; +- gpios = <&pioB 18 GPIO_ACTIVE_LOW>; +- linux,code = <28>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9n12.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9n12.dtsi +deleted file mode 100644 +index 0785389f5507..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9n12.dtsi ++++ /dev/null +@@ -1,810 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC +- * +- * Copyright (C) 2012 Atmel, +- * 2012 Hong Xu +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Atmel AT91SAM9N12 SoC"; +- compatible = "atmel,at91sam9n12"; +- interrupt-parent = <&aic>; +- +- aliases { +- serial0 = &dbgu; +- serial1 = &usart0; +- serial2 = &usart1; +- serial3 = &usart2; +- serial4 = &usart3; +- gpio0 = &pioA; +- gpio1 = &pioB; +- gpio2 = &pioC; +- gpio3 = &pioD; +- tcb0 = &tcb0; +- tcb1 = &tcb1; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- ssc0 = &ssc0; +- pwm0 = &pwm0; +- }; +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,arm926ej-s"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x10000000>; +- }; +- +- clocks { +- slow_xtal: slow_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- main_xtal: main_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- }; +- +- sram: sram@300000 { +- compatible = "mmio-sram"; +- reg = <0x00300000 0x8000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00300000 0x8000>; +- }; +- +- ahb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- apb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- aic: interrupt-controller@fffff000 { +- #interrupt-cells = <3>; +- compatible = "atmel,at91rm9200-aic"; +- interrupt-controller; +- reg = <0xfffff000 0x200>; +- atmel,external-irqs = <31>; +- }; +- +- matrix: matrix@ffffde00 { +- compatible = "atmel,at91sam9n12-matrix", "syscon"; +- reg = <0xffffde00 0x100>; +- }; +- +- pmecc: ecc-engine@ffffe000 { +- compatible = "atmel,at91sam9g45-pmecc"; +- reg = <0xffffe000 0x600>, +- <0xffffe600 0x200>; +- }; +- +- ramc0: ramc@ffffe800 { +- compatible = "atmel,at91sam9g45-ddramc"; +- reg = <0xffffe800 0x200>; +- clocks = <&pmc PMC_TYPE_SYSTEM 2>; +- clock-names = "ddrck"; +- }; +- +- smc: smc@ffffea00 { +- compatible = "atmel,at91sam9260-smc", "syscon"; +- reg = <0xffffea00 0x200>; +- }; +- +- pmc: pmc@fffffc00 { +- compatible = "atmel,at91sam9n12-pmc", "syscon"; +- reg = <0xfffffc00 0x200>; +- #clock-cells = <2>; +- clocks = <&clk32k>, <&main_xtal>; +- clock-names = "slow_clk", "main_xtal"; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- }; +- +- rstc@fffffe00 { +- compatible = "atmel,at91sam9g45-rstc"; +- reg = <0xfffffe00 0x10>; +- clocks = <&clk32k>; +- }; +- +- pit: timer@fffffe30 { +- compatible = "atmel,at91sam9260-pit"; +- reg = <0xfffffe30 0xf>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- }; +- +- shdwc@fffffe10 { +- compatible = "atmel,at91sam9x5-shdwc"; +- reg = <0xfffffe10 0x10>; +- clocks = <&clk32k>; +- }; +- +- sckc@fffffe50 { +- compatible = "atmel,at91sam9x5-sckc"; +- reg = <0xfffffe50 0x4>; +- +- slow_osc: slow_osc { +- compatible = "atmel,at91sam9x5-clk-slow-osc"; +- #clock-cells = <0>; +- clocks = <&slow_xtal>; +- }; +- +- slow_rc_osc: slow_rc_osc { +- compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-accuracy = <50000000>; +- }; +- +- clk32k: slck { +- compatible = "atmel,at91sam9x5-clk-slow"; +- #clock-cells = <0>; +- clocks = <&slow_rc_osc>, <&slow_osc>; +- }; +- }; +- +- mmc0: mmc@f0008000 { +- compatible = "atmel,hsmci"; +- reg = <0xf0008000 0x600>; +- interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; +- dma-names = "rxtx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; +- clock-names = "mci_clk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- tcb0: timer@f8008000 { +- compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xf8008000 0x100>; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; +- clock-names = "t0_clk", "slow_clk"; +- }; +- +- tcb1: timer@f800c000 { +- compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xf800c000 0x100>; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; +- clock-names = "t0_clk", "slow_clk"; +- }; +- +- hlcdc: hlcdc@f8038000 { +- compatible = "atmel,at91sam9n12-hlcdc"; +- reg = <0xf8038000 0x2000>; +- interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; +- clock-names = "periph_clk", "sys_clk", "slow_clk"; +- status = "disabled"; +- +- hlcdc-display-controller { +- compatible = "atmel,hlcdc-display-controller"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- }; +- +- hlcdc_pwm: hlcdc-pwm { +- compatible = "atmel,hlcdc-pwm"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd_pwm>; +- #pwm-cells = <3>; +- }; +- }; +- +- dma: dma-controller@ffffec00 { +- compatible = "atmel,at91sam9g45-dma"; +- reg = <0xffffec00 0x200>; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; +- #dma-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; +- clock-names = "dma_clk"; +- }; +- +- pinctrl@fffff400 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; +- ranges = <0xfffff400 0xfffff400 0x800>; +- +- atmel,mux-mask = < +- /* A B C */ +- 0xffffffff 0xffe07983 0x00000000 /* pioA */ +- 0x00040000 0x00047e0f 0x00000000 /* pioB */ +- 0xfdffffff 0x07c00000 0xb83fffff /* pioC */ +- 0x003fffff 0x003f8000 0x00000000 /* pioD */ +- >; +- +- /* shared pinctrl settings */ +- dbgu { +- pinctrl_dbgu: dbgu-0 { +- atmel,pins = +- ; +- }; +- }; +- +- lcd { +- pinctrl_lcd_base: lcd-base-0 { +- atmel,pins = +- ; /* LCDPCK */ +- }; +- +- pinctrl_lcd_pwm: lcd-pwm-0 { +- atmel,pins = ; /* LCDPWM */ +- }; +- +- pinctrl_lcd_rgb888: lcd-rgb-3 { +- atmel,pins = +- ; /* LCDD23 pin */ +- }; +- }; +- +- usart0 { +- pinctrl_usart0: usart0-0 { +- atmel,pins = +- ; /* PA0 periph A */ +- }; +- +- pinctrl_usart0_rts: usart0_rts-0 { +- atmel,pins = +- ; /* PA2 periph A */ +- }; +- +- pinctrl_usart0_cts: usart0_cts-0 { +- atmel,pins = +- ; /* PA3 periph A */ +- }; +- }; +- +- usart1 { +- pinctrl_usart1: usart1-0 { +- atmel,pins = +- ; /* PA5 periph A */ +- }; +- }; +- +- usart2 { +- pinctrl_usart2: usart2-0 { +- atmel,pins = +- ; /* PA7 periph A */ +- }; +- +- pinctrl_usart2_rts: usart2_rts-0 { +- atmel,pins = +- ; /* PB0 periph B */ +- }; +- +- pinctrl_usart2_cts: usart2_cts-0 { +- atmel,pins = +- ; /* PB1 periph B */ +- }; +- }; +- +- usart3 { +- pinctrl_usart3: usart3-0 { +- atmel,pins = +- ; /* PC22 periph B */ +- }; +- +- pinctrl_usart3_rts: usart3_rts-0 { +- atmel,pins = +- ; /* PC24 periph B */ +- }; +- +- pinctrl_usart3_cts: usart3_cts-0 { +- atmel,pins = +- ; /* PC25 periph B */ +- }; +- }; +- +- uart0 { +- pinctrl_uart0: uart0-0 { +- atmel,pins = +- ; /* PC8 periph C */ +- }; +- }; +- +- uart1 { +- pinctrl_uart1: uart1-0 { +- atmel,pins = +- ; +- }; +- }; +- +- nand { +- pinctrl_nand_rb: nand-rb-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_nand_cs: nand-cs-0 { +- atmel,pins = +- ; +- }; +- }; +- +- mmc0 { +- pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { +- atmel,pins = +- ; /* PA15 periph A with pullup */ +- }; +- +- pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { +- atmel,pins = +- ; /* PA20 periph A with pullup */ +- }; +- +- pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { +- atmel,pins = +- ; /* PA14 periph B with pullup */ +- }; +- }; +- +- ssc0 { +- pinctrl_ssc0_tx: ssc0_tx-0 { +- atmel,pins = +- ; /* PA26 periph B */ +- }; +- +- pinctrl_ssc0_rx: ssc0_rx-0 { +- atmel,pins = +- ; /* PA29 periph B */ +- }; +- }; +- +- spi0 { +- pinctrl_spi0: spi0-0 { +- atmel,pins = +- ; /* PA13 periph A SPI0_SPCK pin */ +- }; +- }; +- +- spi1 { +- pinctrl_spi1: spi1-0 { +- atmel,pins = +- ; /* PA23 periph B SPI1_SPCK pin */ +- }; +- }; +- +- i2c0 { +- pinctrl_i2c0: i2c0-0 { +- atmel,pins = +- ; +- }; +- }; +- +- i2c1 { +- pinctrl_i2c1: i2c1-0 { +- atmel,pins = +- ; +- }; +- }; +- +- tcb0 { +- pinctrl_tcb0_tclk0: tcb0_tclk0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tclk1: tcb0_tclk1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tclk2: tcb0_tclk2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa0: tcb0_tioa0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa1: tcb0_tioa1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa2: tcb0_tioa2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob0: tcb0_tiob0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob1: tcb0_tiob1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob2: tcb0_tiob2-0 { +- atmel,pins = ; +- }; +- }; +- +- tcb1 { +- pinctrl_tcb1_tclk0: tcb1_tclk0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tclk1: tcb1_tclk1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tclk2: tcb1_tclk2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tioa0: tcb1_tioa0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tioa1: tcb1_tioa1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tioa2: tcb1_tioa2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tiob0: tcb1_tiob0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tiob1: tcb1_tiob1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tiob2: tcb1_tiob2-0 { +- atmel,pins = ; +- }; +- }; +- +- pioA: gpio@fffff400 { +- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfffff400 0x200>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; +- }; +- +- pioB: gpio@fffff600 { +- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfffff600 0x200>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; +- }; +- +- pioC: gpio@fffff800 { +- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfffff800 0x200>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; +- }; +- +- pioD: gpio@fffffa00 { +- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfffffa00 0x200>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; +- }; +- }; +- +- dbgu: serial@fffff200 { +- compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; +- reg = <0xfffff200 0x200>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dbgu>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- ssc0: ssc@f0010000 { +- compatible = "atmel,at91sam9g45-ssc"; +- reg = <0xf0010000 0x4000>; +- interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; +- dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>, +- <&dma 0 AT91_DMA_CFG_PER_ID(22)>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; +- clock-names = "pclk"; +- status = "disabled"; +- }; +- +- usart0: serial@f801c000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf801c000 0x4000>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart1: serial@f8020000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf8020000 0x4000>; +- interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart2: serial@f8024000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf8024000 0x4000>; +- interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart3: serial@f8028000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf8028000 0x4000>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- i2c0: i2c@f8010000 { +- compatible = "atmel,at91sam9x5-i2c"; +- reg = <0xf8010000 0x100>; +- interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; +- dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>, +- <&dma 1 AT91_DMA_CFG_PER_ID(14)>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; +- status = "disabled"; +- }; +- +- i2c1: i2c@f8014000 { +- compatible = "atmel,at91sam9x5-i2c"; +- reg = <0xf8014000 0x100>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; +- dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>, +- <&dma 1 AT91_DMA_CFG_PER_ID(16)>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; +- status = "disabled"; +- }; +- +- spi0: spi@f0000000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xf0000000 0x100>; +- interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; +- dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>, +- <&dma 1 AT91_DMA_CFG_PER_ID(2)>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; +- clock-names = "spi_clk"; +- status = "disabled"; +- }; +- +- spi1: spi@f0004000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xf0004000 0x100>; +- interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; +- dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>, +- <&dma 1 AT91_DMA_CFG_PER_ID(4)>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; +- clock-names = "spi_clk"; +- status = "disabled"; +- }; +- +- watchdog@fffffe40 { +- compatible = "atmel,at91sam9260-wdt"; +- reg = <0xfffffe40 0x10>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&clk32k>; +- atmel,watchdog-type = "hardware"; +- atmel,reset-type = "all"; +- atmel,dbg-halt; +- status = "disabled"; +- }; +- +- rtc@fffffeb0 { +- compatible = "atmel,at91rm9200-rtc"; +- reg = <0xfffffeb0 0x40>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&clk32k>; +- status = "disabled"; +- }; +- +- pwm0: pwm@f8034000 { +- compatible = "atmel,at91sam9rl-pwm"; +- reg = <0xf8034000 0x300>; +- interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; +- #pwm-cells = <3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; +- status = "disabled"; +- }; +- +- usb1: gadget@f803c000 { +- compatible = "atmel,at91sam9260-udc"; +- reg = <0xf803c000 0x4000>; +- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_SYSTEM 7>; +- clock-names = "pclk", "hclk"; +- status = "disabled"; +- }; +- }; +- +- usb0: ohci@500000 { +- compatible = "atmel,at91rm9200-ohci", "usb-ohci"; +- reg = <0x00500000 0x00100000>; +- interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; +- clock-names = "ohci_clk", "hclk", "uhpck"; +- status = "disabled"; +- }; +- +- ebi: ebi@10000000 { +- compatible = "atmel,at91sam9x5-ebi"; +- #address-cells = <2>; +- #size-cells = <1>; +- atmel,smc = <&smc>; +- atmel,matrix = <&matrix>; +- reg = <0x10000000 0x60000000>; +- ranges = <0x0 0x0 0x10000000 0x10000000 +- 0x1 0x0 0x20000000 0x10000000 +- 0x2 0x0 0x30000000 0x10000000 +- 0x3 0x0 0x40000000 0x10000000 +- 0x4 0x0 0x50000000 0x10000000 +- 0x5 0x0 0x60000000 0x10000000>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- status = "disabled"; +- +- nand_controller: nand-controller { +- compatible = "atmel,at91sam9g45-nand-controller"; +- ecc-engine = <&pmecc>; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- }; +- }; +- }; +- +- i2c-gpio-0 { +- compatible = "i2c-gpio"; +- gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ +- &pioA 31 GPIO_ACTIVE_HIGH /* scl */ +- >; +- i2c-gpio,sda-open-drain; +- i2c-gpio,scl-open-drain; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9n12ek.dts b/scripts/dtc/include-prefixes/arm/at91sam9n12ek.dts +deleted file mode 100644 +index 2bc4e6e0a923..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9n12ek.dts ++++ /dev/null +@@ -1,285 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91sam9n12ek.dts - Device Tree file for AT91SAM9N12-EK board +- * +- * Copyright (C) 2012 Atmel, +- * 2012 Hong Xu +- */ +-/dts-v1/; +-#include "at91sam9n12.dtsi" +- +-/ { +- model = "Atmel AT91SAM9N12-EK"; +- compatible = "atmel,at91sam9n12ek", "atmel,at91sam9n12", "atmel,at91sam9"; +- +- chosen { +- bootargs = "root=/dev/mtdblock1 rw rootfstype=jffs2"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x8000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <16000000>; +- }; +- }; +- +- ahb { +- apb { +- dbgu: serial@fffff200 { +- status = "okay"; +- }; +- +- ssc0: ssc@f0010000 { +- status = "okay"; +- }; +- +- tcb0: timer@f8008000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>; +- }; +- +- timer@1 { +- compatible = "atmel,tcb-timer"; +- reg = <1>; +- }; +- }; +- +- i2c0: i2c@f8010000 { +- status = "okay"; +- +- wm8904: codec@1a { +- compatible = "wlf,wm8904"; +- reg = <0x1a>; +- clocks = <&pmc PMC_TYPE_SYSTEM 8>; +- clock-names = "mclk"; +- }; +- +- qt1070: keyboard@1b { +- compatible = "qt1070"; +- reg = <0x1b>; +- interrupt-parent = <&pioA>; +- interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_qt1070_irq>; +- }; +- }; +- +- mmc0: mmc@f0008000 { +- pinctrl-0 = < +- &pinctrl_board_mmc0 +- &pinctrl_mmc0_slot0_clk_cmd_dat0 +- &pinctrl_mmc0_slot0_dat1_3>; +- status = "okay"; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioA 7 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- pinctrl@fffff400 { +- mmc0 { +- pinctrl_board_mmc0: mmc0-board { +- atmel,pins = +- ; /* PA7 gpio CD pin pull up and deglitch */ +- }; +- }; +- +- qt1070 { +- pinctrl_qt1070_irq: qt1070_irq { +- atmel,pins = +- ; +- }; +- }; +- +- sound { +- pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { +- atmel,pins = +- ; +- }; +- }; +- +- usb1 { +- pinctrl_usb1_vbus_sense: usb1_vbus_sense { +- atmel,pins = +- ; /* PB16 gpio usb vbus sense, no pull up and deglitch */ +- }; +- }; +- }; +- +- spi0: spi@f0000000 { +- status = "okay"; +- cs-gpios = <&pioA 14 0>, <0>, <0>, <0>; +- m25p80@0 { +- compatible = "atmel,at25df321a"; +- spi-max-frequency = <50000000>; +- reg = <0>; +- }; +- }; +- +- hlcdc: hlcdc@f8038000 { +- status = "okay"; +- +- hlcdc-display-controller { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; +- +- port@0 { +- hlcdc_panel_output: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_input>; +- }; +- }; +- }; +- }; +- +- usb1: gadget@f803c000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb1_vbus_sense>; +- atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- watchdog@fffffe40 { +- status = "okay"; +- }; +- +- rtc@fffffeb0 { +- status = "okay"; +- }; +- }; +- +- ebi: ebi@10000000 { +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; +- pinctrl-names = "default"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "soft"; +- nand-ecc-strength = <2>; +- nand-ecc-step-size = <512>; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- }; +- }; +- }; +- +- usb0: ohci@500000 { +- num-ports = <1>; +- atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>; +- status = "okay"; +- }; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&hlcdc_pwm 0 50000 0>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- power-supply = <&bl_reg>; +- status = "okay"; +- }; +- +- bl_reg: backlight_regulator { +- compatible = "regulator-fixed"; +- regulator-name = "backlight-power-supply"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- status = "okay"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- d8 { +- label = "d8"; +- gpios = <&pioB 4 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "mmc0"; +- }; +- +- d9 { +- label = "d9"; +- gpios = <&pioB 5 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "nand-disk"; +- }; +- +- d10 { +- label = "d10"; +- gpios = <&pioB 6 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- enter { +- label = "Enter"; +- gpios = <&pioB 3 GPIO_ACTIVE_LOW>; +- linux,code = <28>; +- wakeup-source; +- }; +- }; +- +- panel: panel { +- compatible = "qiaodian,qd43003c0-40"; +- backlight = <&backlight>; +- power-supply = <&panel_reg>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- port@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- panel_input: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&hlcdc_panel_output>; +- }; +- }; +- }; +- +- panel_reg: panel_regulator { +- compatible = "regulator-fixed"; +- regulator-name = "panel-power-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- status = "okay"; +- }; +- +- sound { +- compatible = "atmel,asoc-wm8904"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; +- +- atmel,model = "wm8904 @ AT91SAM9N12"; +- atmel,audio-routing = +- "Headphone Jack", "HPOUTL", +- "Headphone Jack", "HPOUTR", +- "IN2L", "Line In Jack", +- "IN2R", "Line In Jack", +- "Mic", "MICBIAS", +- "IN1L", "Mic"; +- +- atmel,ssc-controller = <&ssc0>; +- atmel,audio-codec = <&wm8904>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9rl.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9rl.dtsi +deleted file mode 100644 +index 730d1182c73e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9rl.dtsi ++++ /dev/null +@@ -1,855 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC +- * +- * Copyright (C) 2014 Microchip +- * Alexandre Belloni +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Atmel AT91SAM9RL family SoC"; +- compatible = "atmel,at91sam9rl", "atmel,at91sam9"; +- interrupt-parent = <&aic>; +- +- aliases { +- serial0 = &dbgu; +- serial1 = &usart0; +- serial2 = &usart1; +- serial3 = &usart2; +- serial4 = &usart3; +- gpio0 = &pioA; +- gpio1 = &pioB; +- gpio2 = &pioC; +- gpio3 = &pioD; +- tcb0 = &tcb0; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- ssc0 = &ssc0; +- ssc1 = &ssc1; +- pwm0 = &pwm0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,arm926ej-s"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x04000000>; +- }; +- +- clocks { +- slow_xtal: slow_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- main_xtal: main_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- adc_op_clk: adc_op_clk{ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <1000000>; +- }; +- }; +- +- sram: sram@300000 { +- compatible = "mmio-sram"; +- reg = <0x00300000 0x10000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00300000 0x10000>; +- }; +- +- ahb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- fb0: fb@500000 { +- compatible = "atmel,at91sam9rl-lcdc"; +- reg = <0x00500000 0x1000>; +- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fb>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>; +- clock-names = "hclk", "lcdc_clk"; +- status = "disabled"; +- }; +- +- ebi: ebi@10000000 { +- compatible = "atmel,at91sam9rl-ebi"; +- #address-cells = <2>; +- #size-cells = <1>; +- atmel,smc = <&smc>; +- atmel,matrix = <&matrix>; +- reg = <0x10000000 0x80000000>; +- ranges = <0x0 0x0 0x10000000 0x10000000 +- 0x1 0x0 0x20000000 0x10000000 +- 0x2 0x0 0x30000000 0x10000000 +- 0x3 0x0 0x40000000 0x10000000 +- 0x4 0x0 0x50000000 0x10000000 +- 0x5 0x0 0x60000000 0x10000000>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- status = "disabled"; +- +- nand_controller: nand-controller { +- compatible = "atmel,at91sam9g45-nand-controller"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- }; +- }; +- +- apb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- tcb0: timer@fffa0000 { +- compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xfffa0000 0x100>; +- interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>, +- <17 IRQ_TYPE_LEVEL_HIGH 0>, +- <18 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 16>, <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; +- clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; +- }; +- +- mmc0: mmc@fffa4000 { +- compatible = "atmel,hsmci"; +- reg = <0xfffa4000 0x600>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; +- clock-names = "mci_clk"; +- status = "disabled"; +- }; +- +- i2c0: i2c@fffa8000 { +- compatible = "atmel,at91sam9260-i2c"; +- reg = <0xfffa8000 0x100>; +- interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; +- status = "disabled"; +- }; +- +- i2c1: i2c@fffac000 { +- compatible = "atmel,at91sam9260-i2c"; +- reg = <0xfffac000 0x100>; +- interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- usart0: serial@fffb0000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffb0000 0x200>; +- interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart1: serial@fffb4000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffb4000 0x200>; +- interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart2: serial@fffb8000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffb8000 0x200>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart3: serial@fffbc000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffbc000 0x200>; +- interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- ssc0: ssc@fffc0000 { +- compatible = "atmel,at91sam9rl-ssc"; +- reg = <0xfffc0000 0x4000>; +- interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; +- status = "disabled"; +- }; +- +- ssc1: ssc@fffc4000 { +- compatible = "atmel,at91sam9rl-ssc"; +- reg = <0xfffc4000 0x4000>; +- interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; +- status = "disabled"; +- }; +- +- pwm0: pwm@fffc8000 { +- compatible = "atmel,at91sam9rl-pwm"; +- reg = <0xfffc8000 0x300>; +- interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; +- #pwm-cells = <3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; +- clock-names = "pwm_clk"; +- status = "disabled"; +- }; +- +- spi0: spi@fffcc000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xfffcc000 0x200>; +- interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; +- clock-names = "spi_clk"; +- status = "disabled"; +- }; +- +- adc0: adc@fffd0000 { +- compatible = "atmel,at91sam9rl-adc"; +- reg = <0xfffd0000 0x100>; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&adc_op_clk>; +- clock-names = "adc_clk", "adc_op_clk"; +- atmel,adc-use-external-triggers; +- atmel,adc-channels-used = <0x3f>; +- atmel,adc-vref = <3300>; +- atmel,adc-startup-time = <40>; +- }; +- +- usb0: gadget@fffd4000 { +- compatible = "atmel,at91sam9rl-udc"; +- reg = <0x00600000 0x100000>, +- <0xfffd4000 0x4000>; +- interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_CORE PMC_UTMI>; +- clock-names = "pclk", "hclk"; +- status = "disabled"; +- }; +- +- dma0: dma-controller@ffffe600 { +- compatible = "atmel,at91sam9rl-dma"; +- reg = <0xffffe600 0x200>; +- interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; +- #dma-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; +- clock-names = "dma_clk"; +- }; +- +- ramc0: ramc@ffffea00 { +- compatible = "atmel,at91sam9260-sdramc"; +- reg = <0xffffea00 0x200>; +- }; +- +- smc: smc@ffffec00 { +- compatible = "atmel,at91sam9260-smc", "syscon"; +- reg = <0xffffec00 0x200>; +- }; +- +- matrix: matrix@ffffee00 { +- compatible = "atmel,at91sam9rl-matrix", "syscon"; +- reg = <0xffffee00 0x200>; +- }; +- +- aic: interrupt-controller@fffff000 { +- #interrupt-cells = <3>; +- compatible = "atmel,at91rm9200-aic"; +- interrupt-controller; +- reg = <0xfffff000 0x200>; +- atmel,external-irqs = <31>; +- }; +- +- dbgu: serial@fffff200 { +- compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; +- reg = <0xfffff200 0x200>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dbgu>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- pinctrl@fffff400 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; +- ranges = <0xfffff400 0xfffff400 0x800>; +- +- atmel,mux-mask = +- /* A B */ +- <0xffffffff 0xe05c6738>, /* pioA */ +- <0xffffffff 0x0000c780>, /* pioB */ +- <0xffffffff 0xe3ffff0e>, /* pioC */ +- <0x003fffff 0x0001ff3c>; /* pioD */ +- +- /* shared pinctrl settings */ +- adc0 { +- pinctrl_adc0_ts: adc0_ts-0 { +- atmel,pins = +- , +- , +- , +- ; +- }; +- +- pinctrl_adc0_ad0: adc0_ad0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_adc0_ad1: adc0_ad1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_adc0_ad2: adc0_ad2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_adc0_ad3: adc0_ad3-0 { +- atmel,pins = ; +- }; +- +- pinctrl_adc0_ad4: adc0_ad4-0 { +- atmel,pins = ; +- }; +- +- pinctrl_adc0_ad5: adc0_ad5-0 { +- atmel,pins = ; +- }; +- +- pinctrl_adc0_adtrg: adc0_adtrg-0 { +- atmel,pins = ; +- }; +- }; +- +- dbgu { +- pinctrl_dbgu: dbgu-0 { +- atmel,pins = +- , +- ; +- }; +- }; +- +- ebi { +- pinctrl_ebi_addr_nand: ebi-addr-0 { +- atmel,pins = +- , +- ; +- }; +- }; +- +- fb { +- pinctrl_fb: fb-0 { +- atmel,pins = +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- }; +- }; +- +- i2c_gpio0 { +- pinctrl_i2c_gpio0: i2c_gpio0-0 { +- atmel,pins = +- , +- ; +- }; +- }; +- +- i2c_gpio1 { +- pinctrl_i2c_gpio1: i2c_gpio1-0 { +- atmel,pins = +- , +- ; +- }; +- }; +- +- mmc0 { +- pinctrl_mmc0_clk: mmc0_clk-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { +- atmel,pins = +- , +- ; +- }; +- +- pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { +- atmel,pins = +- , +- , +- ; +- }; +- }; +- +- nand { +- pinctrl_nand_rb: nand-rb-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_nand_cs: nand-cs-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_nand_oe_we: nand-oe-we-0 { +- atmel,pins = +- , +- ; +- }; +- }; +- +- pwm0 { +- pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { +- atmel,pins = ; +- }; +- +- pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { +- atmel,pins = ; +- }; +- +- pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { +- atmel,pins = ; +- }; +- +- pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { +- atmel,pins = ; +- }; +- +- pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { +- atmel,pins = ; +- }; +- +- pinctrl_pwm0_pwm2_2: pwm0_pwm2-2 { +- atmel,pins = ; +- }; +- +- pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { +- atmel,pins = ; +- }; +- +- pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { +- atmel,pins = ; +- }; +- }; +- +- spi0 { +- pinctrl_spi0: spi0-0 { +- atmel,pins = +- , +- , +- ; +- }; +- }; +- +- ssc0 { +- pinctrl_ssc0_tx: ssc0_tx-0 { +- atmel,pins = +- , +- , +- ; +- }; +- +- pinctrl_ssc0_rx: ssc0_rx-0 { +- atmel,pins = +- , +- , +- ; +- }; +- }; +- +- ssc1 { +- pinctrl_ssc1_tx: ssc1_tx-0 { +- atmel,pins = +- , +- , +- ; +- }; +- +- pinctrl_ssc1_rx: ssc1_rx-0 { +- atmel,pins = +- , +- , +- ; +- }; +- }; +- +- tcb0 { +- pinctrl_tcb0_tclk0: tcb0_tclk0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tclk1: tcb0_tclk1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tclk2: tcb0_tclk2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa0: tcb0_tioa0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa1: tcb0_tioa1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa2: tcb0_tioa2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob0: tcb0_tiob0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob1: tcb0_tiob1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob2: tcb0_tiob2-0 { +- atmel,pins = ; +- }; +- }; +- +- usart0 { +- pinctrl_usart0: usart0-0 { +- atmel,pins = +- , +- ; +- }; +- +- pinctrl_usart0_rts: usart0_rts-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart0_cts: usart0_cts-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { +- atmel,pins = +- , +- ; +- }; +- +- pinctrl_usart0_dcd: usart0_dcd-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart0_ri: usart0_ri-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart0_sck: usart0_sck-0 { +- atmel,pins = +- ; +- }; +- }; +- +- usart1 { +- pinctrl_usart1: usart1-0 { +- atmel,pins = +- , +- ; +- }; +- +- pinctrl_usart1_rts: usart1_rts-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart1_cts: usart1_cts-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart1_sck: usart1_sck-0 { +- atmel,pins = +- ; +- }; +- }; +- +- usart2 { +- pinctrl_usart2: usart2-0 { +- atmel,pins = +- , +- ; +- }; +- +- pinctrl_usart2_rts: usart2_rts-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart2_cts: usart2_cts-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart2_sck: usart2_sck-0 { +- atmel,pins = +- ; +- }; +- }; +- +- usart3 { +- pinctrl_usart3: usart3-0 { +- atmel,pins = +- , +- ; +- }; +- +- pinctrl_usart3_rts: usart3_rts-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart3_cts: usart3_cts-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart3_sck: usart3_sck-0 { +- atmel,pins = +- ; +- }; +- }; +- +- pioA: gpio@fffff400 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff400 0x200>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; +- }; +- +- pioB: gpio@fffff600 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff600 0x200>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; +- }; +- +- pioC: gpio@fffff800 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff800 0x200>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; +- }; +- +- pioD: gpio@fffffa00 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffffa00 0x200>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; +- }; +- }; +- +- pmc: pmc@fffffc00 { +- compatible = "atmel,at91sam9rl-pmc", "syscon"; +- reg = <0xfffffc00 0x100>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- #clock-cells = <2>; +- clocks = <&clk32k>, <&main_xtal>; +- clock-names = "slow_clk", "main_xtal"; +- }; +- +- rstc@fffffd00 { +- compatible = "atmel,at91sam9260-rstc"; +- reg = <0xfffffd00 0x10>; +- clocks = <&clk32k>; +- }; +- +- shdwc@fffffd10 { +- compatible = "atmel,at91sam9260-shdwc"; +- reg = <0xfffffd10 0x10>; +- clocks = <&clk32k>; +- }; +- +- pit: timer@fffffd30 { +- compatible = "atmel,at91sam9260-pit"; +- reg = <0xfffffd30 0xf>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- }; +- +- watchdog@fffffd40 { +- compatible = "atmel,at91sam9260-wdt"; +- reg = <0xfffffd40 0x10>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&clk32k>; +- status = "disabled"; +- }; +- +- clk32k: sckc@fffffd50 { +- compatible = "atmel,at91sam9x5-sckc"; +- reg = <0xfffffd50 0x4>; +- clocks = <&slow_xtal>; +- #clock-cells = <0>; +- }; +- +- rtc@fffffd20 { +- compatible = "atmel,at91sam9260-rtt"; +- reg = <0xfffffd20 0x10>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&clk32k>; +- status = "disabled"; +- }; +- +- gpbr: syscon@fffffd60 { +- compatible = "atmel,at91sam9260-gpbr", "syscon"; +- reg = <0xfffffd60 0x10>; +- status = "disabled"; +- }; +- +- rtc@fffffe00 { +- compatible = "atmel,at91rm9200-rtc"; +- reg = <0xfffffe00 0x40>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&clk32k>; +- status = "disabled"; +- }; +- +- }; +- }; +- +- i2c-gpio-0 { +- compatible = "i2c-gpio"; +- gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */ +- <&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */ +- i2c-gpio,sda-open-drain; +- i2c-gpio,scl-open-drain; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c_gpio0>; +- status = "disabled"; +- }; +- +- i2c-gpio-1 { +- compatible = "i2c-gpio"; +- gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */ +- <&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */ +- i2c-gpio,sda-open-drain; +- i2c-gpio,scl-open-drain; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c_gpio1>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9rlek.dts b/scripts/dtc/include-prefixes/arm/at91sam9rlek.dts +deleted file mode 100644 +index 62981b39c815..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9rlek.dts ++++ /dev/null +@@ -1,272 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9rlek.dts - Device Tree file for Atmel at91sam9rl reference board +- * +- * Copyright (C) 2014 Microchip +- * Alexandre Belloni +- */ +-/dts-v1/; +-#include "at91sam9rl.dtsi" +- +-/ { +- model = "Atmel at91sam9rlek"; +- compatible = "atmel,at91sam9rlek", "atmel,at91sam9rl", "atmel,at91sam9"; +- +- chosen { +- bootargs = "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=5 rw"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- ahb { +- fb0: fb@500000 { +- display = <&display0>; +- status = "okay"; +- +- display0: panel { +- bits-per-pixel = <16>; +- atmel,lcdcon-backlight; +- atmel,dmacon = <0x1>; +- atmel,lcdcon2 = <0x80008002>; +- atmel,guard-time = <1>; +- atmel,lcd-wiring-mode = "RGB"; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing0 { +- clock-frequency = <4965000>; +- hactive = <240>; +- vactive = <320>; +- hback-porch = <1>; +- hfront-porch = <33>; +- vback-porch = <1>; +- vfront-porch = <0>; +- hsync-len = <5>; +- vsync-len = <1>; +- hsync-active = <1>; +- vsync-active = <1>; +- }; +- }; +- }; +- }; +- +- ebi: ebi@10000000 { +- pinctrl-0 = <&pinctrl_ebi_addr_nand>; +- pinctrl-names = "default"; +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- pinctrl-0 = <&pinctrl_nand_oe_we +- &pinctrl_nand_cs +- &pinctrl_nand_rb>; +- pinctrl-names = "default"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioB 6 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "soft"; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x40000>; +- }; +- +- bootloader@40000 { +- label = "bootloader"; +- reg = <0x40000 0x80000>; +- }; +- +- bootloaderenv@c0000 { +- label = "bootloader env"; +- reg = <0xc0000 0xc0000>; +- }; +- +- dtb@180000 { +- label = "device tree"; +- reg = <0x180000 0x80000>; +- }; +- +- kernel@200000 { +- label = "kernel"; +- reg = <0x200000 0x600000>; +- }; +- +- rootfs@800000 { +- label = "rootfs"; +- reg = <0x800000 0x0f800000>; +- }; +- }; +- }; +- }; +- }; +- +- apb { +- tcb0: timer@fffa0000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +- }; +- +- mmc0: mmc@fffa4000 { +- pinctrl-0 = < +- &pinctrl_board_mmc0 +- &pinctrl_mmc0_clk +- &pinctrl_mmc0_slot0_cmd_dat0 +- &pinctrl_mmc0_slot0_dat1_3>; +- status = "okay"; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- usart0: serial@fffb0000 { +- pinctrl-0 = < +- &pinctrl_usart0 +- &pinctrl_usart0_rts +- &pinctrl_usart0_cts>; +- status = "okay"; +- }; +- +- adc0: adc@fffd0000 { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &pinctrl_adc0_ad0 +- &pinctrl_adc0_ad1 +- &pinctrl_adc0_ad2 +- &pinctrl_adc0_ad3 +- &pinctrl_adc0_ad4 +- &pinctrl_adc0_ad5 +- &pinctrl_adc0_adtrg>; +- atmel,adc-ts-wires = <4>; +- status = "okay"; +- }; +- +- usb0: gadget@fffd4000 { +- atmel,vbus-gpio = <&pioA 8 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- spi0: spi@fffcc000 { +- status = "okay"; +- cs-gpios = <&pioA 28 0>, <0>, <0>, <0>; +- mtd_dataflash@0 { +- compatible = "atmel,at45", "atmel,dataflash"; +- spi-max-frequency = <15000000>; +- reg = <0>; +- }; +- }; +- +- pwm0: pwm@fffc8000 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_pwm1_2>, +- <&pinctrl_pwm0_pwm2_2>; +- }; +- +- dbgu: serial@fffff200 { +- status = "okay"; +- }; +- +- pinctrl@fffff400 { +- mmc0 { +- pinctrl_board_mmc0: mmc0-board { +- atmel,pins = +- ; +- }; +- }; +- }; +- +- watchdog@fffffd40 { +- status = "okay"; +- }; +- +- rtc@fffffe00 { +- status = "okay"; +- }; +- }; +- }; +- +- led-controller-1 { +- compatible = "pwm-leds"; +- +- led-1 { +- label = "ds1"; +- pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; +- max-brightness = <255>; +- }; +- +- led-2 { +- label = "ds2"; +- pwms = <&pwm0 2 5000 PWM_POLARITY_INVERTED>; +- max-brightness = <255>; +- }; +- }; +- +- led-controller-2 { +- compatible = "gpio-leds"; +- +- led-3 { +- label = "ds3"; +- gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- right_click { +- label = "right_click"; +- gpios = <&pioB 0 GPIO_ACTIVE_LOW>; +- linux,code = <273>; +- wakeup-source; +- }; +- +- left_click { +- label = "left_click"; +- gpios = <&pioB 1 GPIO_ACTIVE_LOW>; +- linux,code = <272>; +- wakeup-source; +- }; +- }; +- +- i2c-gpio-0 { +- status = "okay"; +- }; +- +- i2c-gpio-1 { +- status = "okay"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9x25.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9x25.dtsi +deleted file mode 100644 +index 0fe8802e1242..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9x25.dtsi ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9x25.dtsi - Device Tree Include file for AT91SAM9X25 SoC +- * +- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +- +-#include "at91sam9x5.dtsi" +-#include "at91sam9x5_usart3.dtsi" +-#include "at91sam9x5_macb0.dtsi" +-#include "at91sam9x5_macb1.dtsi" +-#include "at91sam9x5_can.dtsi" +- +-/ { +- model = "Atmel AT91SAM9X25 SoC"; +- compatible = "atmel,at91sam9x25", "atmel,at91sam9x5"; +- +- ahb { +- apb { +- pinctrl@fffff400 { +- atmel,mux-mask = < +- /* A B C */ +- 0xffffffff 0xffe03fff 0xc000001c /* pioA */ +- 0x0007ffff 0x00047e3f 0x00000000 /* pioB */ +- 0x80000000 0xfffd0000 0xb83fffff /* pioC */ +- 0x003fffff 0x003f8000 0x00000000 /* pioD */ +- >; +- }; +- +- pmc: pmc@fffffc00 { +- compatible = "atmel,at91sam9x25-pmc", "atmel,at91sam9x5-pmc", "syscon"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9x25ek.dts b/scripts/dtc/include-prefixes/arm/at91sam9x25ek.dts +deleted file mode 100644 +index ad7c6b36f0ba..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9x25ek.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board +- * +- * Copyright (C) 2012 Atmel, +- * 2012 Nicolas Ferre +- */ +-/dts-v1/; +-#include "at91sam9x25.dtsi" +-#include "at91sam9x5ek.dtsi" +- +-/ { +- model = "Atmel AT91SAM9X25-EK"; +- compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&macb0 { +- phy-mode = "rmii"; +- status = "okay"; +-}; +- +-&macb1 { +- phy-mode = "rmii"; +- status = "okay"; +-}; +- +-&pwm0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_pwm0_1>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9x35.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9x35.dtsi +deleted file mode 100644 +index 0bfa21f18f87..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9x35.dtsi ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9x35.dtsi - Device Tree Include file for AT91SAM9X35 SoC +- * +- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +- +-#include "at91sam9x5.dtsi" +-#include "at91sam9x5_lcd.dtsi" +-#include "at91sam9x5_macb0.dtsi" +-#include "at91sam9x5_can.dtsi" +- +-/ { +- model = "Atmel AT91SAM9X35 SoC"; +- compatible = "atmel,at91sam9x35", "atmel,at91sam9x5"; +- +- ahb { +- apb { +- pinctrl@fffff400 { +- atmel,mux-mask = < +- /* A B C */ +- 0xffffffff 0xffe03fff 0xc000000c /* pioA */ +- 0x000406ff 0x00047e3f 0x00000000 /* pioB */ +- 0xfdffffff 0x00000000 0xb83fffff /* pioC */ +- 0x003fffff 0x003f8000 0x00000000 /* pioD */ +- >; +- }; +- +- pmc: pmc@fffffc00 { +- compatible = "atmel,at91sam9x35-pmc", "atmel,at91sam9x5-pmc", "syscon"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9x35ek.dts b/scripts/dtc/include-prefixes/arm/at91sam9x35ek.dts +deleted file mode 100644 +index 66675c787b97..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9x35ek.dts ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board +- * +- * Copyright (C) 2012 Atmel, +- * 2012 Nicolas Ferre +- */ +-/dts-v1/; +-#include "at91sam9x35.dtsi" +-#include "at91sam9x5dm.dtsi" +-#include "at91sam9x5ek.dtsi" +- +-/ { +- model = "Atmel AT91SAM9X35-EK"; +- compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; +-}; +- +-&backlight { +- status = "okay"; +-}; +- +-&bl_reg { +- status = "okay"; +-}; +- +-&hlcdc { +- status = "okay"; +-}; +- +-&macb0 { +- phy-mode = "rmii"; +- status = "okay"; +-}; +- +-&panel { +- status = "okay"; +-}; +- +-&panel_reg { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9x5.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9x5.dtsi +deleted file mode 100644 +index 395e883644cd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9x5.dtsi ++++ /dev/null +@@ -1,971 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC +- * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, +- * AT91SAM9X25, AT91SAM9X35 SoC +- * +- * Copyright (C) 2012 Atmel, +- * 2012 Nicolas Ferre +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Atmel AT91SAM9x5 family SoC"; +- compatible = "atmel,at91sam9x5"; +- interrupt-parent = <&aic>; +- +- aliases { +- serial0 = &dbgu; +- serial1 = &usart0; +- serial2 = &usart1; +- serial3 = &usart2; +- gpio0 = &pioA; +- gpio1 = &pioB; +- gpio2 = &pioC; +- gpio3 = &pioD; +- tcb0 = &tcb0; +- tcb1 = &tcb1; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- ssc0 = &ssc0; +- pwm0 = &pwm0; +- }; +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,arm926ej-s"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x10000000>; +- }; +- +- clocks { +- slow_xtal: slow_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- main_xtal: main_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- adc_op_clk: adc_op_clk{ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <1000000>; +- }; +- }; +- +- sram: sram@300000 { +- compatible = "mmio-sram"; +- reg = <0x00300000 0x8000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00300000 0x8000>; +- }; +- +- ahb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- apb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- aic: interrupt-controller@fffff000 { +- #interrupt-cells = <3>; +- compatible = "atmel,at91rm9200-aic"; +- interrupt-controller; +- reg = <0xfffff000 0x200>; +- atmel,external-irqs = <31>; +- }; +- +- matrix: matrix@ffffde00 { +- compatible = "atmel,at91sam9x5-matrix", "syscon"; +- reg = <0xffffde00 0x100>; +- }; +- +- pmecc: ecc-engine@ffffe000 { +- compatible = "atmel,at91sam9g45-pmecc"; +- reg = <0xffffe000 0x600>, +- <0xffffe600 0x200>; +- }; +- +- ramc0: ramc@ffffe800 { +- compatible = "atmel,at91sam9g45-ddramc"; +- reg = <0xffffe800 0x200>; +- clocks = <&pmc PMC_TYPE_SYSTEM 2>; +- clock-names = "ddrck"; +- }; +- +- smc: smc@ffffea00 { +- compatible = "atmel,at91sam9260-smc", "syscon"; +- reg = <0xffffea00 0x200>; +- }; +- +- pmc: pmc@fffffc00 { +- compatible = "atmel,at91sam9x5-pmc", "syscon"; +- reg = <0xfffffc00 0x200>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- #clock-cells = <2>; +- clocks = <&clk32k>, <&main_xtal>; +- clock-names = "slow_clk", "main_xtal"; +- }; +- +- reset_controller: rstc@fffffe00 { +- compatible = "atmel,at91sam9g45-rstc"; +- reg = <0xfffffe00 0x10>; +- clocks = <&clk32k>; +- }; +- +- shutdown_controller: shdwc@fffffe10 { +- compatible = "atmel,at91sam9x5-shdwc"; +- reg = <0xfffffe10 0x10>; +- clocks = <&clk32k>; +- }; +- +- pit: timer@fffffe30 { +- compatible = "atmel,at91sam9260-pit"; +- reg = <0xfffffe30 0xf>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- }; +- +- clk32k: sckc@fffffe50 { +- compatible = "atmel,at91sam9x5-sckc"; +- reg = <0xfffffe50 0x4>; +- clocks = <&slow_xtal>; +- #clock-cells = <0>; +- }; +- +- tcb0: timer@f8008000 { +- compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xf8008000 0x100>; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; +- clock-names = "t0_clk", "slow_clk"; +- }; +- +- tcb1: timer@f800c000 { +- compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xf800c000 0x100>; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; +- clock-names = "t0_clk", "slow_clk"; +- }; +- +- dma0: dma-controller@ffffec00 { +- compatible = "atmel,at91sam9g45-dma"; +- reg = <0xffffec00 0x200>; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; +- #dma-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; +- clock-names = "dma_clk"; +- }; +- +- dma1: dma-controller@ffffee00 { +- compatible = "atmel,at91sam9g45-dma"; +- reg = <0xffffee00 0x200>; +- interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; +- #dma-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; +- clock-names = "dma_clk"; +- }; +- +- pinctrl: pinctrl@fffff400 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; +- ranges = <0xfffff400 0xfffff400 0x800>; +- +- /* shared pinctrl settings */ +- dbgu { +- pinctrl_dbgu: dbgu-0 { +- atmel,pins = +- ; +- }; +- }; +- +- ebi { +- pinctrl_ebi_data_0_7: ebi-data-lsb-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_data_8_15: ebi-data-msb-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_addr_nand: ebi-addr-0 { +- atmel,pins = +- ; +- }; +- }; +- +- usart0 { +- pinctrl_usart0: usart0-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart0_rts: usart0_rts-0 { +- atmel,pins = +- ; /* PA2 periph A */ +- }; +- +- pinctrl_usart0_cts: usart0_cts-0 { +- atmel,pins = +- ; /* PA3 periph A */ +- }; +- +- pinctrl_usart0_sck: usart0_sck-0 { +- atmel,pins = +- ; /* PA4 periph A */ +- }; +- }; +- +- usart1 { +- pinctrl_usart1: usart1-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart1_rts: usart1_rts-0 { +- atmel,pins = +- ; /* PC27 periph C */ +- }; +- +- pinctrl_usart1_cts: usart1_cts-0 { +- atmel,pins = +- ; /* PC28 periph C */ +- }; +- +- pinctrl_usart1_sck: usart1_sck-0 { +- atmel,pins = +- ; /* PC29 periph C */ +- }; +- }; +- +- usart2 { +- pinctrl_usart2: usart2-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart2_rts: usart2_rts-0 { +- atmel,pins = +- ; /* PB0 periph B */ +- }; +- +- pinctrl_usart2_cts: usart2_cts-0 { +- atmel,pins = +- ; /* PB1 periph B */ +- }; +- +- pinctrl_usart2_sck: usart2_sck-0 { +- atmel,pins = +- ; /* PB2 periph B */ +- }; +- }; +- +- uart0 { +- pinctrl_uart0: uart0-0 { +- atmel,pins = +- ; /* PC9 periph C with pullup */ +- }; +- }; +- +- uart1 { +- pinctrl_uart1: uart1-0 { +- atmel,pins = +- ; /* PC17 periph C with pullup */ +- }; +- }; +- +- nand { +- pinctrl_nand_oe_we: nand-oe-we-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_nand_rb: nand-rb-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_nand_cs: nand-cs-0 { +- atmel,pins = +- ; +- }; +- }; +- +- mmc0 { +- pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { +- atmel,pins = +- ; /* PA15 periph A with pullup */ +- }; +- +- pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { +- atmel,pins = +- ; /* PA20 periph A with pullup */ +- }; +- }; +- +- mmc1 { +- pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { +- atmel,pins = +- ; /* PA11 periph B with pullup */ +- }; +- +- pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { +- atmel,pins = +- ; /* PA4 periph B with pullup */ +- }; +- }; +- +- ssc0 { +- pinctrl_ssc0_tx: ssc0_tx-0 { +- atmel,pins = +- ; /* PA26 periph B */ +- }; +- +- pinctrl_ssc0_rx: ssc0_rx-0 { +- atmel,pins = +- ; /* PA29 periph B */ +- }; +- }; +- +- spi0 { +- pinctrl_spi0: spi0-0 { +- atmel,pins = +- ; /* PA13 periph A SPI0_SPCK pin */ +- }; +- }; +- +- spi1 { +- pinctrl_spi1: spi1-0 { +- atmel,pins = +- ; /* PA23 periph B SPI1_SPCK pin */ +- }; +- }; +- +- i2c0 { +- pinctrl_i2c0: i2c0-0 { +- atmel,pins = +- ; /* PA31 periph A I2C0 clock */ +- }; +- }; +- +- i2c1 { +- pinctrl_i2c1: i2c1-0 { +- atmel,pins = +- ; /* PC1 periph C I2C1 clock */ +- }; +- }; +- +- i2c2 { +- pinctrl_i2c2: i2c2-0 { +- atmel,pins = +- ; /* PB5 periph B I2C2 clock */ +- }; +- }; +- +- i2c_gpio0 { +- pinctrl_i2c_gpio0: i2c_gpio0-0 { +- atmel,pins = +- ; /* PA31 gpio multidrive I2C0 clock */ +- }; +- }; +- +- i2c_gpio1 { +- pinctrl_i2c_gpio1: i2c_gpio1-0 { +- atmel,pins = +- ; /* PC1 gpio multidrive I2C1 clock */ +- }; +- }; +- +- i2c_gpio2 { +- pinctrl_i2c_gpio2: i2c_gpio2-0 { +- atmel,pins = +- ; /* PB5 gpio multidrive I2C2 clock */ +- }; +- }; +- +- pwm0 { +- pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { +- atmel,pins = +- ; +- }; +- pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { +- atmel,pins = +- ; +- }; +- pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { +- atmel,pins = +- ; +- }; +- +- pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { +- atmel,pins = +- ; +- }; +- pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { +- atmel,pins = +- ; +- }; +- pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { +- atmel,pins = +- ; +- }; +- +- pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { +- atmel,pins = +- ; +- }; +- pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { +- atmel,pins = +- ; +- }; +- +- pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { +- atmel,pins = +- ; +- }; +- pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { +- atmel,pins = +- ; +- }; +- }; +- +- tcb0 { +- pinctrl_tcb0_tclk0: tcb0_tclk0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tclk1: tcb0_tclk1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tclk2: tcb0_tclk2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa0: tcb0_tioa0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa1: tcb0_tioa1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tioa2: tcb0_tioa2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob0: tcb0_tiob0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob1: tcb0_tiob1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb0_tiob2: tcb0_tiob2-0 { +- atmel,pins = ; +- }; +- }; +- +- tcb1 { +- pinctrl_tcb1_tclk0: tcb1_tclk0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tclk1: tcb1_tclk1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tclk2: tcb1_tclk2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tioa0: tcb1_tioa0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tioa1: tcb1_tioa1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tioa2: tcb1_tioa2-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tiob0: tcb1_tiob0-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tiob1: tcb1_tiob1-0 { +- atmel,pins = ; +- }; +- +- pinctrl_tcb1_tiob2: tcb1_tiob2-0 { +- atmel,pins = ; +- }; +- }; +- +- pioA: gpio@fffff400 { +- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfffff400 0x200>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; +- }; +- +- pioB: gpio@fffff600 { +- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfffff600 0x200>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- #gpio-lines = <19>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; +- }; +- +- pioC: gpio@fffff800 { +- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfffff800 0x200>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; +- }; +- +- pioD: gpio@fffffa00 { +- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfffffa00 0x200>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- #gpio-lines = <22>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; +- }; +- }; +- +- ssc0: ssc@f0010000 { +- compatible = "atmel,at91sam9g45-ssc"; +- reg = <0xf0010000 0x4000>; +- interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; +- dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>, +- <&dma0 1 AT91_DMA_CFG_PER_ID(14)>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; +- clock-names = "pclk"; +- status = "disabled"; +- }; +- +- mmc0: mmc@f0008000 { +- compatible = "atmel,hsmci"; +- reg = <0xf0008000 0x600>; +- interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>; +- dma-names = "rxtx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; +- clock-names = "mci_clk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- mmc1: mmc@f000c000 { +- compatible = "atmel,hsmci"; +- reg = <0xf000c000 0x600>; +- interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>; +- dma-names = "rxtx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; +- clock-names = "mci_clk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- dbgu: serial@fffff200 { +- compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; +- reg = <0xfffff200 0x200>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dbgu>; +- dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>, +- <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart0: serial@f801c000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf801c000 0x200>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart0>; +- dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>, +- <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart1: serial@f8020000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf8020000 0x200>; +- interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart1>; +- dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>, +- <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart2: serial@f8024000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf8024000 0x200>; +- interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart2>; +- dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>, +- <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- i2c0: i2c@f8010000 { +- compatible = "atmel,at91sam9x5-i2c"; +- reg = <0xf8010000 0x100>; +- interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; +- dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>, +- <&dma0 1 AT91_DMA_CFG_PER_ID(8)>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; +- status = "disabled"; +- }; +- +- i2c1: i2c@f8014000 { +- compatible = "atmel,at91sam9x5-i2c"; +- reg = <0xf8014000 0x100>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; +- dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>, +- <&dma1 1 AT91_DMA_CFG_PER_ID(6)>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; +- status = "disabled"; +- }; +- +- i2c2: i2c@f8018000 { +- compatible = "atmel,at91sam9x5-i2c"; +- reg = <0xf8018000 0x100>; +- interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; +- dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>, +- <&dma0 1 AT91_DMA_CFG_PER_ID(10)>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; +- status = "disabled"; +- }; +- +- uart0: serial@f8040000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf8040000 0x200>; +- interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- uart1: serial@f8044000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf8044000 0x200>; +- interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- adc0: adc@f804c000 { +- compatible = "atmel,at91sam9x5-adc"; +- reg = <0xf804c000 0x100>; +- interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 19>, +- <&adc_op_clk>; +- clock-names = "adc_clk", "adc_op_clk"; +- atmel,adc-use-external-triggers; +- atmel,adc-channels-used = <0xffff>; +- atmel,adc-vref = <3300>; +- atmel,adc-startup-time = <40>; +- atmel,adc-sample-hold-time = <11>; +- }; +- +- spi0: spi@f0000000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xf0000000 0x100>; +- interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; +- dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>, +- <&dma0 1 AT91_DMA_CFG_PER_ID(2)>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; +- clock-names = "spi_clk"; +- status = "disabled"; +- }; +- +- spi1: spi@f0004000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xf0004000 0x100>; +- interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; +- dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>, +- <&dma1 1 AT91_DMA_CFG_PER_ID(2)>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; +- clock-names = "spi_clk"; +- status = "disabled"; +- }; +- +- usb2: gadget@f803c000 { +- compatible = "atmel,at91sam9g45-udc"; +- reg = <0x00500000 0x80000 +- 0xf803c000 0x400>; +- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 23>; +- clock-names = "hclk", "pclk"; +- status = "disabled"; +- }; +- +- watchdog: watchdog@fffffe40 { +- compatible = "atmel,at91sam9260-wdt"; +- reg = <0xfffffe40 0x10>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&clk32k>; +- atmel,watchdog-type = "hardware"; +- atmel,reset-type = "all"; +- atmel,dbg-halt; +- status = "disabled"; +- }; +- +- rtc: rtc@fffffeb0 { +- compatible = "atmel,at91sam9x5-rtc"; +- reg = <0xfffffeb0 0x40>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&clk32k>; +- status = "disabled"; +- }; +- +- pwm0: pwm@f8034000 { +- compatible = "atmel,at91sam9rl-pwm"; +- reg = <0xf8034000 0x300>; +- interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- }; +- +- usb0: ohci@600000 { +- compatible = "atmel,at91rm9200-ohci", "usb-ohci"; +- reg = <0x00600000 0x100000>; +- interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; +- clock-names = "ohci_clk", "hclk", "uhpck"; +- status = "disabled"; +- }; +- +- usb1: ehci@700000 { +- compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; +- reg = <0x00700000 0x100000>; +- interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; +- clock-names = "usb_clk", "ehci_clk"; +- status = "disabled"; +- }; +- +- ebi: ebi@10000000 { +- compatible = "atmel,at91sam9x5-ebi"; +- #address-cells = <2>; +- #size-cells = <1>; +- atmel,smc = <&smc>; +- atmel,matrix = <&matrix>; +- reg = <0x10000000 0x60000000>; +- ranges = <0x0 0x0 0x10000000 0x10000000 +- 0x1 0x0 0x20000000 0x10000000 +- 0x2 0x0 0x30000000 0x10000000 +- 0x3 0x0 0x40000000 0x10000000 +- 0x4 0x0 0x50000000 0x10000000 +- 0x5 0x0 0x60000000 0x10000000>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- status = "disabled"; +- +- nand_controller: nand-controller { +- compatible = "atmel,at91sam9g45-nand-controller"; +- ecc-engine = <&pmecc>; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- }; +- }; +- }; +- +- i2c-gpio-0 { +- compatible = "i2c-gpio"; +- gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ +- &pioA 31 GPIO_ACTIVE_HIGH /* scl */ +- >; +- i2c-gpio,sda-open-drain; +- i2c-gpio,scl-open-drain; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c_gpio0>; +- status = "disabled"; +- }; +- +- i2c-gpio-1 { +- compatible = "i2c-gpio"; +- gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */ +- &pioC 1 GPIO_ACTIVE_HIGH /* scl */ +- >; +- i2c-gpio,sda-open-drain; +- i2c-gpio,scl-open-drain; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c_gpio1>; +- status = "disabled"; +- }; +- +- i2c-gpio-2 { +- compatible = "i2c-gpio"; +- gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ +- &pioB 5 GPIO_ACTIVE_HIGH /* scl */ +- >; +- i2c-gpio,sda-open-drain; +- i2c-gpio,scl-open-drain; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c_gpio2>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9x5_can.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9x5_can.dtsi +deleted file mode 100644 +index 04ccb25d342c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9x5_can.dtsi ++++ /dev/null +@@ -1,56 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 +- * Ethernet interface. +- * +- * Copyright (C) 2013 Boris BREZILLON +- */ +- +-#include +-#include +- +-/ { +- ahb { +- apb { +- can0: can@f8000000 { +- compatible = "atmel,at91sam9x5-can"; +- reg = <0xf8000000 0x300>; +- interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can0_rx_tx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; +- clock-names = "can_clk"; +- status = "disabled"; +- }; +- +- can1: can@f8004000 { +- compatible = "atmel,at91sam9x5-can"; +- reg = <0xf8004000 0x300>; +- interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1_rx_tx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; +- clock-names = "can_clk"; +- status = "disabled"; +- }; +- +- pinctrl@fffff400 { +- can0 { +- pinctrl_can0_rx_tx: can0_rx_tx { +- atmel,pins = +- ; /* CANTX0, conflicts with DTXD */ +- }; +- }; +- +- can1 { +- pinctrl_can1_rx_tx: can1_rx_tx { +- atmel,pins = +- ; /* CANTX1, conflicts with TXD1 */ +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9x5_isi.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9x5_isi.dtsi +deleted file mode 100644 +index 4ce98f05d7db..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9x5_isi.dtsi ++++ /dev/null +@@ -1,62 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an +- * Image Sensor Interface. +- * +- * Copyright (C) 2013 Boris BREZILLON +- */ +- +-#include +-#include +- +-/ { +- ahb { +- apb { +- pinctrl@fffff400 { +- isi { +- pinctrl_isi_data_0_7: isi-0-data-0-7 { +- atmel,pins = +- ; /* ISI_VSYNC, conflicts with LCDDAT13 */ +- }; +- +- pinctrl_isi_data_8_9: isi-0-data-8-9 { +- atmel,pins = +- ; /* ISI_D9, conflicts with LCDDAT9 */ +- }; +- +- pinctrl_isi_data_10_11: isi-0-data-10-11 { +- atmel,pins = +- ; /* ISI_D11, conflicts with LCDDAT11 */ +- }; +- }; +- }; +- +- isi: isi@f8048000 { +- compatible = "atmel,at91sam9g45-isi"; +- reg = <0xf8048000 0x4000>; +- interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_isi_data_0_7>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; +- clock-names = "isi_clk"; +- status = "disabled"; +- port { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9x5_lcd.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9x5_lcd.dtsi +deleted file mode 100644 +index f81c9d1691e0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9x5_lcd.dtsi ++++ /dev/null +@@ -1,147 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an +- * LCD controller. +- * +- * Copyright (C) 2013 Boris BREZILLON +- */ +- +-#include +-#include +- +-/ { +- ahb { +- apb { +- hlcdc: hlcdc@f8038000 { +- compatible = "atmel,at91sam9x5-hlcdc"; +- reg = <0xf8038000 0x4000>; +- interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; +- clock-names = "periph_clk","sys_clk", "slow_clk"; +- status = "disabled"; +- +- hlcdc-display-controller { +- compatible = "atmel,hlcdc-display-controller"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- }; +- +- hlcdc_pwm: hlcdc-pwm { +- compatible = "atmel,hlcdc-pwm"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd_pwm>; +- #pwm-cells = <3>; +- }; +- }; +- }; +- }; +-}; +- +-&pinctrl { +- lcd { +- pinctrl_lcd_base: lcd-base-0 { +- atmel,pins = +- ; /* LCDPCK */ +- }; +- +- pinctrl_lcd_pwm: lcd-pwm-0 { +- atmel,pins = ; /* LCDPWM */ +- }; +- +- pinctrl_lcd_rgb444: lcd-rgb-0 { +- atmel,pins = +- ; /* LCDD11 pin */ +- }; +- +- pinctrl_lcd_rgb565: lcd-rgb-1 { +- atmel,pins = +- ; /* LCDD15 pin */ +- }; +- +- pinctrl_lcd_rgb666: lcd-rgb-2 { +- atmel,pins = +- ; /* LCDD17 pin */ +- }; +- +- pinctrl_lcd_rgb888: lcd-rgb-3 { +- atmel,pins = +- ; /* LCDD23 pin */ +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9x5_macb0.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9x5_macb0.dtsi +deleted file mode 100644 +index 222aa30f6860..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9x5_macb0.dtsi ++++ /dev/null +@@ -1,57 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 +- * Ethernet interface. +- * +- * Copyright (C) 2013 Boris BREZILLON +- */ +- +-#include +-#include +- +-/ { +- ahb { +- apb { +- pinctrl@fffff400 { +- macb0 { +- pinctrl_macb0_rmii: macb0_rmii-0 { +- atmel,pins = +- ; /* PB10 periph A */ +- }; +- +- pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { +- atmel,pins = +- ; /* PB17 periph A */ +- }; +- }; +- }; +- +- macb0: ethernet@f802c000 { +- compatible = "cdns,at91sam9260-macb", "cdns,macb"; +- reg = <0xf802c000 0x100>; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_macb0_rmii>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>; +- clock-names = "hclk", "pclk"; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9x5_macb1.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9x5_macb1.dtsi +deleted file mode 100644 +index 26bf9b5de9ee..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9x5_macb1.dtsi ++++ /dev/null +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2 +- * Ethernet interfaces. +- * +- * Copyright (C) 2013 Boris BREZILLON +- */ +- +-#include +-#include +- +-/ { +- ahb { +- apb { +- pinctrl@fffff400 { +- macb1 { +- pinctrl_macb1_rmii: macb1_rmii-0 { +- atmel,pins = +- ; /* PC31 periph B */ +- }; +- }; +- }; +- +- macb1: ethernet@f8030000 { +- compatible = "cdns,at91sam9260-macb", "cdns,macb"; +- reg = <0xf8030000 0x100>; +- interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_macb1_rmii>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>; +- clock-names = "hclk", "pclk"; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9x5_usart3.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9x5_usart3.dtsi +deleted file mode 100644 +index 098d3fef5c37..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9x5_usart3.dtsi ++++ /dev/null +@@ -1,59 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * at91sam9x5_usart3.dtsi - Device Tree Include file for AT91SAM9x5 SoC with +- * 4 USART. +- * +- * Copyright (C) 2013 Boris BREZILLON +- */ +- +-#include +-#include +- +-/ { +- aliases { +- serial4 = &usart3; +- }; +- +- ahb { +- apb { +- pinctrl@fffff400 { +- usart3 { +- pinctrl_usart3: usart3-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart3_rts: usart3_rts-0 { +- atmel,pins = +- ; /* PC24 periph B */ +- }; +- +- pinctrl_usart3_cts: usart3_cts-0 { +- atmel,pins = +- ; /* PC25 periph B */ +- }; +- +- pinctrl_usart3_sck: usart3_sck-0 { +- atmel,pins = +- ; /* PC26 periph B */ +- }; +- }; +- }; +- +- usart3: serial@f8028000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf8028000 0x200>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart3>; +- dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>, +- <&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9x5cm.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9x5cm.dtsi +deleted file mode 100644 +index cdd37f67280b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9x5cm.dtsi ++++ /dev/null +@@ -1,144 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module +- * +- * Copyright (C) 2012 Atmel, +- * 2012 Nicolas Ferre +- */ +- +-/ { +- memory@20000000 { +- reg = <0x20000000 0x8000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- ahb { +- apb { +- tcb0: timer@f8008000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>; +- }; +- +- timer@1 { +- compatible = "atmel,tcb-timer"; +- reg = <1>; +- }; +- }; +- +- pinctrl@fffff400 { +- 1wire_cm { +- pinctrl_1wire_cm: 1wire_cm-0 { +- atmel,pins = ; /* PB18 multidrive, conflicts with led */ +- }; +- }; +- }; +- +- rtc@fffffeb0 { +- status = "okay"; +- }; +- }; +- +- ebi: ebi@10000000 { +- pinctrl-0 = <&pinctrl_ebi_addr_nand +- &pinctrl_ebi_data_0_7>; +- pinctrl-names = "default"; +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- pinctrl-0 = <&pinctrl_nand_oe_we +- &pinctrl_nand_cs +- &pinctrl_nand_rb>; +- pinctrl-names = "default"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <2>; +- nand-ecc-step-size = <512>; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x40000>; +- }; +- +- uboot@40000 { +- label = "u-boot"; +- reg = <0x40000 0xc0000>; +- }; +- +- ubootenvred@100000 { +- label = "U-Boot Env Redundant"; +- reg = <0x100000 0x40000>; +- }; +- +- ubootenv@140000 { +- label = "U-Boot Env"; +- reg = <0x140000 0x40000>; +- }; +- +- dtb@180000 { +- label = "device tree"; +- reg = <0x180000 0x80000>; +- }; +- +- kernel@200000 { +- label = "kernel"; +- reg = <0x200000 0x600000>; +- }; +- +- rootfs@800000 { +- label = "rootfs"; +- reg = <0x800000 0x0f800000>; +- }; +- }; +- }; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pb18 { +- label = "pb18"; +- gpios = <&pioB 18 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- +- pd21 { +- label = "pd21"; +- gpios = <&pioD 21 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- 1wire_cm { +- compatible = "w1-gpio"; +- gpios = <&pioB 18 GPIO_ACTIVE_HIGH>; +- linux,open-drain; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_1wire_cm>; +- status = "okay"; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9x5dm.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9x5dm.dtsi +deleted file mode 100644 +index a9278038af3b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9x5dm.dtsi ++++ /dev/null +@@ -1,96 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91sam9x5dm.dtsi - Device Tree file for SAM9x5 display module +- * +- * Copyright (C) 2014 Atmel, +- * 2014 Free Electrons +- * +- * Author: Boris Brezillon +- */ +- +-/ { +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&hlcdc_pwm 0 50000 0>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- power-supply = <&bl_reg>; +- status = "disabled"; +- }; +- +- bl_reg: backlight_regulator { +- compatible = "regulator-fixed"; +- regulator-name = "backlight-power-supply"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- status = "disabled"; +- }; +- +- panel: panel { +- compatible = "foxlink,fl500wvr00-a0t"; +- backlight = <&backlight>; +- power-supply = <&panel_reg>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- panel_input: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&hlcdc_panel_output>; +- }; +- }; +- }; +- +- panel_reg: panel_regulator { +- compatible = "regulator-fixed"; +- regulator-name = "panel-power-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- status = "disabled"; +- }; +-}; +- +-&adc0 { +- atmel,adc-ts-wires = <4>; +- atmel,adc-ts-pressure-threshold = <10000>; +- status = "okay"; +-}; +- +-&i2c0 { +- keyboard@1b { +- compatible = "qt1070"; +- reg = <0x1b>; +- interrupt-parent = <&pioA>; +- interrupts = <7 0x0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_qt1070_irq>; +- wakeup-source; +- }; +-}; +- +-&hlcdc { +- hlcdc-display-controller { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; +- +- port@0 { +- hlcdc_panel_output: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_input>; +- }; +- }; +- }; +-}; +- +-&pinctrl { +- board { +- pinctrl_qt1070_irq: qt1070_irq { +- atmel,pins = +- ; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9x5ek.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9x5ek.dtsi +deleted file mode 100644 +index 6d1264de6060..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9x5ek.dtsi ++++ /dev/null +@@ -1,167 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board +- * +- * Copyright (C) 2012 Atmel, +- * 2012 Nicolas Ferre +- */ +-#include "at91sam9x5cm.dtsi" +- +-/ { +- model = "Atmel AT91SAM9X5-EK"; +- compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; +- +- chosen { +- bootargs = "root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; +- stdout-path = "serial0:115200n8"; +- }; +- +- sound { +- compatible = "atmel,sam9x5-wm8731-audio"; +- +- atmel,model = "wm8731 @ AT91SAM9X5EK"; +- +- atmel,audio-routing = +- "Headphone Jack", "RHPOUT", +- "Headphone Jack", "LHPOUT", +- "LLINEIN", "Line In Jack", +- "RLINEIN", "Line In Jack"; +- +- atmel,ssc-controller = <&ssc0>; +- atmel,audio-codec = <&wm8731>; +- }; +-}; +- +-&adc0 { +- atmel,adc-ts-wires = <4>; +- atmel,adc-ts-pressure-threshold = <10000>; +- status = "okay"; +-}; +- +-&dbgu { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- wm8731: wm8731@1a { +- compatible = "wm8731"; +- reg = <0x1a>; +- }; +-}; +- +-&mmc0 { +- pinctrl-0 = < +- &pinctrl_board_mmc0 +- &pinctrl_mmc0_slot0_clk_cmd_dat0 +- &pinctrl_mmc0_slot0_dat1_3>; +- pinctrl-names = "default"; +- status = "okay"; +- +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&mmc1 { +- pinctrl-0 = < +- &pinctrl_board_mmc1 +- &pinctrl_mmc1_slot0_clk_cmd_dat0 +- &pinctrl_mmc1_slot0_dat1_3>; +- pinctrl-names = "default"; +- status = "okay"; +- +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&pinctrl { +- camera_sensor { +- pinctrl_pck0_as_isi_mck: pck0_as_isi_mck-0 { +- atmel,pins = +- ; /* ISI_MCK */ +- }; +- +- pinctrl_sensor_power: sensor_power-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_sensor_reset: sensor_reset-0 { +- atmel,pins = +- ; +- }; +- }; +- +- mmc0 { +- pinctrl_board_mmc0: mmc0-board { +- atmel,pins = +- ; /* PD15 gpio CD pin pull up and deglitch */ +- }; +- }; +- +- mmc1 { +- pinctrl_board_mmc1: mmc1-board { +- atmel,pins = +- ; /* PD14 gpio CD pin pull up and deglitch */ +- }; +- }; +- +- usb2 { +- pinctrl_board_usb2: usb2-board { +- atmel,pins = +- ; /* PB16 gpio vbus sense, deglitch */ +- }; +- }; +-}; +- +-&spi0 { +- cs-gpios = <&pioA 14 0>, <0>, <0>, <0>; +- status = "disabled"; /* conflicts with mmc1 */ +- +- m25p80@0 { +- compatible = "atmel,at25df321a"; +- spi-max-frequency = <50000000>; +- reg = <0>; +- }; +-}; +- +-&ssc0 { +- status = "okay"; +-}; +- +-&usart0 { +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "okay"; +-}; +- +-&usb0 { +- num-ports = <3>; +- atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW *//* Activate to have access to port A */ +- &pioD 19 GPIO_ACTIVE_LOW +- &pioD 20 GPIO_ACTIVE_LOW +- >; +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&usb2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_board_usb2>; +- atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&watchdog { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/at91sam9xe.dtsi b/scripts/dtc/include-prefixes/arm/at91sam9xe.dtsi +deleted file mode 100644 +index f571f77779c3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/at91sam9xe.dtsi ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * at91sam9xe.dtsi - Device Tree Include file for AT91SAM9XE family SoC +- * +- * Copyright (C) 2015 Atmel, +- * 2015 Alexandre Belloni +- */ +- +-#include "at91sam9260.dtsi" +- +-/ { +- model = "Atmel AT91SAM9XE family SoC"; +- compatible = "atmel,at91sam9xe", "atmel,at91sam9260"; +- +- sram0: sram@2ff000 { +- status = "disabled"; +- }; +- +- sram1: sram@300000 { +- compatible = "mmio-sram"; +- reg = <0x00300000 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00300000 0x4000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/axm5516-amarillo.dts b/scripts/dtc/include-prefixes/arm/axm5516-amarillo.dts +deleted file mode 100644 +index 2e2ad3c7ee77..000000000000 +--- a/scripts/dtc/include-prefixes/arm/axm5516-amarillo.dts ++++ /dev/null +@@ -1,47 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * arch/arm/boot/dts/axm5516-amarillo.dts +- * +- * Copyright (C) 2013 LSI +- */ +- +-/dts-v1/; +- +-/memreserve/ 0x00000000 0x00400000; +- +-#include "axm55xx.dtsi" +-#include "axm5516-cpus.dtsi" +- +-/ { +- model = "Amarillo AXM5516"; +- compatible = "lsi,axm5516-amarillo", "lsi,axm5516"; +- +- memory { +- device_type = "memory"; +- reg = <0 0x00000000 0x02 0x00000000>; +- }; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&serial1 { +- status = "okay"; +-}; +- +-&serial2 { +- status = "okay"; +-}; +- +-&serial3 { +- status = "okay"; +-}; +- +-&gpio0 { +- status = "okay"; +-}; +- +-&gpio1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/axm5516-cpus.dtsi b/scripts/dtc/include-prefixes/arm/axm5516-cpus.dtsi +deleted file mode 100644 +index 3bcf4e0a3c85..000000000000 +--- a/scripts/dtc/include-prefixes/arm/axm5516-cpus.dtsi ++++ /dev/null +@@ -1,200 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * arch/arm/boot/dts/axm5516-cpus.dtsi +- * +- * Copyright (C) 2013 LSI +- */ +- +-/ { +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&CPU0>; +- }; +- core1 { +- cpu = <&CPU1>; +- }; +- core2 { +- cpu = <&CPU2>; +- }; +- core3 { +- cpu = <&CPU3>; +- }; +- }; +- cluster1 { +- core0 { +- cpu = <&CPU4>; +- }; +- core1 { +- cpu = <&CPU5>; +- }; +- core2 { +- cpu = <&CPU6>; +- }; +- core3 { +- cpu = <&CPU7>; +- }; +- }; +- cluster2 { +- core0 { +- cpu = <&CPU8>; +- }; +- core1 { +- cpu = <&CPU9>; +- }; +- core2 { +- cpu = <&CPU10>; +- }; +- core3 { +- cpu = <&CPU11>; +- }; +- }; +- cluster3 { +- core0 { +- cpu = <&CPU12>; +- }; +- core1 { +- cpu = <&CPU13>; +- }; +- core2 { +- cpu = <&CPU14>; +- }; +- core3 { +- cpu = <&CPU15>; +- }; +- }; +- }; +- +- CPU0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x00>; +- clock-frequency= <1400000000>; +- cpu-release-addr = <0>; // Fixed by the boot loader +- }; +- +- CPU1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x01>; +- clock-frequency= <1400000000>; +- cpu-release-addr = <0>; // Fixed by the boot loader +- }; +- +- CPU2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x02>; +- clock-frequency= <1400000000>; +- cpu-release-addr = <0>; // Fixed by the boot loader +- }; +- +- CPU3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x03>; +- clock-frequency= <1400000000>; +- cpu-release-addr = <0>; // Fixed by the boot loader +- }; +- +- CPU4: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x100>; +- clock-frequency= <1400000000>; +- cpu-release-addr = <0>; // Fixed by the boot loader +- }; +- +- CPU5: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x101>; +- clock-frequency= <1400000000>; +- cpu-release-addr = <0>; // Fixed by the boot loader +- }; +- +- CPU6: cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x102>; +- clock-frequency= <1400000000>; +- cpu-release-addr = <0>; // Fixed by the boot loader +- }; +- +- CPU7: cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x103>; +- clock-frequency= <1400000000>; +- cpu-release-addr = <0>; // Fixed by the boot loader +- }; +- +- CPU8: cpu@200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x200>; +- clock-frequency= <1400000000>; +- cpu-release-addr = <0>; // Fixed by the boot loader +- }; +- +- CPU9: cpu@201 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x201>; +- clock-frequency= <1400000000>; +- cpu-release-addr = <0>; // Fixed by the boot loader +- }; +- +- CPU10: cpu@202 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x202>; +- clock-frequency= <1400000000>; +- cpu-release-addr = <0>; // Fixed by the boot loader +- }; +- +- CPU11: cpu@203 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x203>; +- clock-frequency= <1400000000>; +- cpu-release-addr = <0>; // Fixed by the boot loader +- }; +- +- CPU12: cpu@300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x300>; +- clock-frequency= <1400000000>; +- cpu-release-addr = <0>; // Fixed by the boot loader +- }; +- +- CPU13: cpu@301 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x301>; +- clock-frequency= <1400000000>; +- cpu-release-addr = <0>; // Fixed by the boot loader +- }; +- +- CPU14: cpu@302 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x302>; +- clock-frequency= <1400000000>; +- cpu-release-addr = <0>; // Fixed by the boot loader +- }; +- +- CPU15: cpu@303 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x303>; +- clock-frequency= <1400000000>; +- cpu-release-addr = <0>; // Fixed by the boot loader +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/axm55xx.dtsi b/scripts/dtc/include-prefixes/arm/axm55xx.dtsi +deleted file mode 100644 +index 7676a65059a4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/axm55xx.dtsi ++++ /dev/null +@@ -1,200 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * arch/arm/boot/dts/axm55xx.dtsi +- * +- * Copyright (C) 2013 LSI +- */ +- +-#include +-#include +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&gic>; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- timer = &timer0; +- }; +- +- clocks { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clk_ref0: clk_ref0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- }; +- +- clk_ref1: clk_ref1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- }; +- +- clk_ref2: clk_ref2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- }; +- +- clks: clock-controller@2010020000 { +- compatible = "lsi,axm5516-clks"; +- #clock-cells = <1>; +- reg = <0x20 0x10020000 0 0x20000>; +- }; +- }; +- +- gic: interrupt-controller@2001001000 { +- compatible = "arm,cortex-a15-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x20 0x01001000 0 0x1000>, +- <0x20 0x01002000 0 0x2000>, +- <0x20 0x01004000 0 0x2000>, +- <0x20 0x01006000 0 0x2000>; +- interrupts = ; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = +- , +- , +- , +- ; +- }; +- +- +- pmu { +- compatible = "arm,cortex-a15-pmu"; +- interrupts = ; +- }; +- +- soc { +- compatible = "simple-bus"; +- device_type = "soc"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&gic>; +- ranges; +- +- syscon: syscon@2010030000 { +- compatible = "lsi,axxia-syscon", "syscon"; +- reg = <0x20 0x10030000 0 0x2000>; +- }; +- +- reset: reset@2010031000 { +- compatible = "lsi,axm55xx-reset"; +- syscon = <&syscon>; +- }; +- +- amba { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- serial0: uart@2010080000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x20 0x10080000 0 0x1000>; +- interrupts = ; +- clocks = <&clks AXXIA_CLK_PER>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- serial1: uart@2010081000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x20 0x10081000 0 0x1000>; +- interrupts = ; +- clocks = <&clks AXXIA_CLK_PER>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- serial2: uart@2010082000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x20 0x10082000 0 0x1000>; +- interrupts = ; +- clocks = <&clks AXXIA_CLK_PER>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- serial3: uart@2010083000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x20 0x10083000 0 0x1000>; +- interrupts = ; +- clocks = <&clks AXXIA_CLK_PER>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- timer0: timer@2010091000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x20 0x10091000 0 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&clks AXXIA_CLK_PER>; +- clock-names = "apb_pclk"; +- status = "okay"; +- }; +- +- gpio0: gpio@2010092000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x20 0x10092000 0x00 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&clks AXXIA_CLK_PER>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- gpio1: gpio@2010093000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x20 0x10093000 0x00 0x1000>; +- interrupts = ; +- clocks = <&clks AXXIA_CLK_PER>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- }; +- }; +-}; +- +-/* +- Local Variables: +- mode: C +- End: +-*/ +diff --git a/scripts/dtc/include-prefixes/arm/axp152.dtsi b/scripts/dtc/include-prefixes/arm/axp152.dtsi +deleted file mode 100644 +index f90ad6c64a07..000000000000 +--- a/scripts/dtc/include-prefixes/arm/axp152.dtsi ++++ /dev/null +@@ -1,49 +0,0 @@ +-/* +- * Copyright 2015 Chen-Yu Tsai +- * +- * Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-&axp152 { +- compatible = "x-powers,axp152"; +- interrupt-controller; +- #interrupt-cells = <1>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/axp209.dtsi b/scripts/dtc/include-prefixes/arm/axp209.dtsi +deleted file mode 100644 +index 0d9ff12bdf28..000000000000 +--- a/scripts/dtc/include-prefixes/arm/axp209.dtsi ++++ /dev/null +@@ -1,119 +0,0 @@ +-/* +- * Copyright 2015 Chen-Yu Tsai +- * +- * Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/* +- * AXP202/209 Integrated Power Management Chip +- * http://www.x-powers.com/product/AXP20X.php +- * http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf +- */ +- +-&axp209 { +- compatible = "x-powers,axp209"; +- interrupt-controller; +- #interrupt-cells = <1>; +- +- ac_power_supply: ac-power-supply { +- compatible = "x-powers,axp202-ac-power-supply"; +- status = "disabled"; +- }; +- +- axp_adc: adc { +- compatible = "x-powers,axp209-adc"; +- #io-channel-cells = <1>; +- }; +- +- axp_gpio: gpio { +- compatible = "x-powers,axp209-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- battery_power_supply: battery-power-supply { +- compatible = "x-powers,axp209-battery-power-supply"; +- status = "disabled"; +- }; +- +- regulators { +- /* Default work frequency for buck regulators */ +- x-powers,dcdc-freq = <1500>; +- +- reg_dcdc2: dcdc2 { +- regulator-name = "dcdc2"; +- }; +- +- reg_dcdc3: dcdc3 { +- regulator-name = "dcdc3"; +- }; +- +- reg_ldo1: ldo1 { +- /* LDO1 is a fixed output regulator */ +- regulator-always-on; +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "ldo1"; +- }; +- +- reg_ldo2: ldo2 { +- regulator-name = "ldo2"; +- }; +- +- reg_ldo3: ldo3 { +- regulator-name = "ldo3"; +- }; +- +- reg_ldo4: ldo4 { +- regulator-name = "ldo4"; +- }; +- +- reg_ldo5: ldo5 { +- regulator-name = "ldo5"; +- status = "disabled"; +- }; +- }; +- +- usb_power_supply: usb-power-supply { +- compatible = "x-powers,axp202-usb-power-supply"; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/axp223.dtsi b/scripts/dtc/include-prefixes/arm/axp223.dtsi +deleted file mode 100644 +index b91b6c1278c7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/axp223.dtsi ++++ /dev/null +@@ -1,58 +0,0 @@ +-/* +- * Copyright 2016 Free Electrons +- * +- * Quentin Schulz +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/* +- * AXP223 Integrated Power Management Chip +- * http://www.x-powers.com/product/AXP22X.php +- * http://dl.linux-sunxi.org/AXP/AXP223-en.pdf +- * +- * The AXP223 shares most of its logic with the AXP221 but it has some +- * differences, for the VBUS driver for example. +- */ +- +-#include "axp22x.dtsi" +- +-&usb_power_supply { +- compatible = "x-powers,axp223-usb-power-supply"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/axp22x.dtsi b/scripts/dtc/include-prefixes/arm/axp22x.dtsi +deleted file mode 100644 +index 65a07a67aca9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/axp22x.dtsi ++++ /dev/null +@@ -1,170 +0,0 @@ +-/* +- * Copyright 2015 Chen-Yu Tsai +- * +- * Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/* +- * AXP221/221s/223 Integrated Power Management Chip +- * http://www.x-powers.com/product/AXP22X.php +- * http://dl.linux-sunxi.org/AXP/AXP221%20Datasheet%20V1.2%2020130326%20.pdf +- */ +- +-&axp22x { +- interrupt-controller; +- #interrupt-cells = <1>; +- +- ac_power_supply: ac-power-supply { +- compatible = "x-powers,axp221-ac-power-supply"; +- status = "disabled"; +- }; +- +- axp_adc: adc { +- compatible = "x-powers,axp221-adc"; +- #io-channel-cells = <1>; +- }; +- +- battery_power_supply: battery-power-supply { +- compatible = "x-powers,axp221-battery-power-supply"; +- status = "disabled"; +- }; +- +- regulators { +- /* Default work frequency for buck regulators */ +- x-powers,dcdc-freq = <3000>; +- +- reg_dcdc1: dcdc1 { +- regulator-name = "dcdc1"; +- }; +- +- reg_dcdc2: dcdc2 { +- regulator-name = "dcdc2"; +- }; +- +- reg_dcdc3: dcdc3 { +- regulator-name = "dcdc3"; +- }; +- +- reg_dcdc4: dcdc4 { +- regulator-name = "dcdc4"; +- }; +- +- reg_dcdc5: dcdc5 { +- regulator-name = "dcdc5"; +- }; +- +- reg_dc1sw: dc1sw { +- regulator-name = "dc1sw"; +- }; +- +- reg_dc5ldo: dc5ldo { +- regulator-name = "dc5ldo"; +- }; +- +- reg_aldo1: aldo1 { +- regulator-name = "aldo1"; +- }; +- +- reg_aldo2: aldo2 { +- regulator-name = "aldo2"; +- }; +- +- reg_aldo3: aldo3 { +- regulator-name = "aldo3"; +- }; +- +- reg_dldo1: dldo1 { +- regulator-name = "dldo1"; +- }; +- +- reg_dldo2: dldo2 { +- regulator-name = "dldo2"; +- }; +- +- reg_dldo3: dldo3 { +- regulator-name = "dldo3"; +- }; +- +- reg_dldo4: dldo4 { +- regulator-name = "dldo4"; +- }; +- +- reg_eldo1: eldo1 { +- regulator-name = "eldo1"; +- }; +- +- reg_eldo2: eldo2 { +- regulator-name = "eldo2"; +- }; +- +- reg_eldo3: eldo3 { +- regulator-name = "eldo3"; +- }; +- +- reg_ldo_io0: ldo_io0 { +- regulator-name = "ldo_io0"; +- status = "disabled"; +- }; +- +- reg_ldo_io1: ldo_io1 { +- regulator-name = "ldo_io1"; +- status = "disabled"; +- }; +- +- reg_rtc_ldo: rtc_ldo { +- /* RTC_LDO is a fixed, always-on regulator */ +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "rtc_ldo"; +- }; +- +- reg_drivevbus: drivevbus { +- regulator-name = "drivevbus"; +- status = "disabled"; +- }; +- }; +- +- usb_power_supply: usb_power_supply { +- compatible = "x-powers,axp221-usb-power-supply"; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/axp809.dtsi b/scripts/dtc/include-prefixes/arm/axp809.dtsi +deleted file mode 100644 +index ab8e5f2d9246..000000000000 +--- a/scripts/dtc/include-prefixes/arm/axp809.dtsi ++++ /dev/null +@@ -1,53 +0,0 @@ +-/* +- * Copyright 2015 Chen-Yu Tsai +- * +- * Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/* +- * AXP809 Integrated Power Management Chip +- */ +- +-&axp809 { +- compatible = "x-powers,axp809"; +- interrupt-controller; +- #interrupt-cells = <1>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/axp81x.dtsi b/scripts/dtc/include-prefixes/arm/axp81x.dtsi +deleted file mode 100644 +index 1dfeeceabf4c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/axp81x.dtsi ++++ /dev/null +@@ -1,178 +0,0 @@ +-/* +- * Copyright 2017 Chen-Yu Tsai +- * +- * Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/* AXP813/818 Integrated Power Management Chip */ +- +-&axp81x { +- interrupt-controller; +- #interrupt-cells = <1>; +- +- ac_power_supply: ac-power-supply { +- compatible = "x-powers,axp813-ac-power-supply"; +- status = "disabled"; +- }; +- +- axp_adc: adc { +- compatible = "x-powers,axp813-adc"; +- #io-channel-cells = <1>; +- }; +- +- axp_gpio: gpio { +- compatible = "x-powers,axp813-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio0_ldo: gpio0-ldo { +- pins = "GPIO0"; +- function = "ldo"; +- }; +- +- gpio1_ldo: gpio1-ldo { +- pins = "GPIO1"; +- function = "ldo"; +- }; +- }; +- +- battery_power_supply: battery-power-supply { +- compatible = "x-powers,axp813-battery-power-supply"; +- status = "disabled"; +- }; +- +- regulators { +- /* Default work frequency for buck regulators */ +- x-powers,dcdc-freq = <3000>; +- +- reg_dcdc1: dcdc1 { +- }; +- +- reg_dcdc2: dcdc2 { +- }; +- +- reg_dcdc3: dcdc3 { +- }; +- +- reg_dcdc4: dcdc4 { +- }; +- +- reg_dcdc5: dcdc5 { +- }; +- +- reg_dcdc6: dcdc6 { +- }; +- +- reg_dcdc7: dcdc7 { +- }; +- +- reg_aldo1: aldo1 { +- }; +- +- reg_aldo2: aldo2 { +- }; +- +- reg_aldo3: aldo3 { +- }; +- +- reg_dldo1: dldo1 { +- }; +- +- reg_dldo2: dldo2 { +- }; +- +- reg_dldo3: dldo3 { +- }; +- +- reg_dldo4: dldo4 { +- }; +- +- reg_eldo1: eldo1 { +- }; +- +- reg_eldo2: eldo2 { +- }; +- +- reg_eldo3: eldo3 { +- }; +- +- reg_fldo1: fldo1 { +- }; +- +- reg_fldo2: fldo2 { +- }; +- +- reg_fldo3: fldo3 { +- }; +- +- reg_ldo_io0: ldo-io0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio0_ldo>; +- /* Disable by default to avoid conflicts with GPIO */ +- status = "disabled"; +- }; +- +- reg_ldo_io1: ldo-io1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio1_ldo>; +- /* Disable by default to avoid conflicts with GPIO */ +- status = "disabled"; +- }; +- +- reg_rtc_ldo: rtc-ldo { +- /* RTC_LDO is a fixed, always-on regulator */ +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- reg_sw: sw { +- }; +- +- reg_drivevbus: drivevbus { +- status = "disabled"; +- }; +- }; +- +- usb_power_supply: usb-power-supply { +- compatible = "x-powers,axp813-usb-power-supply"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm-cygnus-clock.dtsi b/scripts/dtc/include-prefixes/arm/bcm-cygnus-clock.dtsi +deleted file mode 100644 +index 52f91a12a99a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm-cygnus-clock.dtsi ++++ /dev/null +@@ -1,133 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2014 Broadcom Corporation. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- osc: oscillator { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25000000>; +- }; +- +- /* Cygnus ARM PLL */ +- armpll: armpll@19000000 { +- #clock-cells = <0>; +- compatible = "brcm,cygnus-armpll"; +- clocks = <&osc>; +- reg = <0x19000000 0x1000>; +- }; +- +- /* peripheral clock for system timer */ +- periph_clk: arm_periph_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&armpll>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- /* APB bus clock */ +- apb_clk: apb_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&armpll>; +- clock-div = <4>; +- clock-mult = <1>; +- }; +- +- genpll: genpll@301d000 { +- #clock-cells = <1>; +- compatible = "brcm,cygnus-genpll"; +- reg = <0x0301d000 0x2c>, <0x0301c020 0x4>; +- clocks = <&osc>; +- clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys", +- "enet_sw", "audio_125", "can"; +- }; +- +- /* always 1/2 of the axi21 clock */ +- axi41_clk: axi41_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&genpll 1>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- /* always 1/4 of the axi21 clock */ +- axi81_clk: axi81_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&genpll 1>; +- clock-div = <4>; +- clock-mult = <1>; +- }; +- +- lcpll0: lcpll0@301d02c { +- #clock-cells = <1>; +- compatible = "brcm,cygnus-lcpll0"; +- reg = <0x0301d02c 0x1c>, <0x0301c020 0x4>; +- clocks = <&osc>; +- clock-output-names = "lcpll0", "pcie_phy", "ddr_phy", "sdio", +- "usb_phy", "smart_card", "ch5"; +- }; +- +- mipipll: mipipll@180a9800 { +- #clock-cells = <1>; +- compatible = "brcm,cygnus-mipipll"; +- reg = <0x180a9800 0x2c>, <0x0301c020 0x4>, <0x180aa024 0x4>; +- clocks = <&osc>; +- clock-output-names = "mipipll", "ch0_unused", "ch1_lcd", +- "ch2_v3d", "ch3_unused", "ch4_unused", +- "ch5_unused"; +- }; +- +- asiu_clks: asiu_clks@301d048 { +- #clock-cells = <1>; +- compatible = "brcm,cygnus-asiu-clk"; +- reg = <0x0301d048 0xc>, <0x180aa024 0x4>; +- +- clocks = <&osc>; +- clock-output-names = "keypad", "adc/touch", "pwm"; +- }; +- +- audiopll: audiopll@180aeb00 { +- #clock-cells = <1>; +- compatible = "brcm,cygnus-audiopll"; +- reg = <0x180aeb00 0x68>; +- clocks = <&osc>; +- clock-output-names = "audiopll", "ch0_audio", +- "ch1_audio", "ch2_audio"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm-cygnus.dtsi b/scripts/dtc/include-prefixes/arm/bcm-cygnus.dtsi +deleted file mode 100644 +index 8ecb7861ce10..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm-cygnus.dtsi ++++ /dev/null +@@ -1,623 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2014 Broadcom Corporation. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "brcm,cygnus"; +- model = "Broadcom Cygnus SoC"; +- interrupt-parent = <&gic>; +- +- aliases { +- ethernet0 = ð0; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- reg = <0x0>; +- }; +- }; +- +- /include/ "bcm-cygnus-clock.dtsi" +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = ; +- }; +- +- core@19000000 { +- compatible = "simple-bus"; +- ranges = <0x00000000 0x19000000 0x1000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- timer@20200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0x20200 0x100>; +- interrupts = ; +- clocks = <&periph_clk>; +- }; +- +- gic: interrupt-controller@21000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x21000 0x1000>, +- <0x20100 0x100>; +- }; +- +- L2: cache-controller@22000 { +- compatible = "arm,pl310-cache"; +- reg = <0x22000 0x1000>; +- cache-unified; +- cache-level = <2>; +- }; +- }; +- +- axi { +- compatible = "simple-bus"; +- ranges; +- #address-cells = <1>; +- #size-cells = <1>; +- +- otp: otp@301c800 { +- compatible = "brcm,ocotp"; +- reg = <0x0301c800 0x2c>; +- brcm,ocotp-size = <2048>; +- status = "disabled"; +- }; +- +- pcie_phy: phy@301d0a0 { +- compatible = "brcm,cygnus-pcie-phy"; +- reg = <0x0301d0a0 0x14>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pcie0_phy: phy@0 { +- reg = <0>; +- #phy-cells = <0>; +- }; +- +- pcie1_phy: phy@1 { +- reg = <1>; +- #phy-cells = <0>; +- }; +- }; +- +- pinctrl: pinctrl@301d0c8 { +- compatible = "brcm,cygnus-pinmux"; +- reg = <0x0301d0c8 0x30>, +- <0x0301d24c 0x2c>; +- +- spi_0: spi_0 { +- function = "spi0"; +- groups = "spi0_grp"; +- }; +- +- spi_1: spi_1 { +- function = "spi1"; +- groups = "spi1_grp"; +- }; +- +- spi_2: spi_2 { +- function = "spi2"; +- groups = "spi2_grp"; +- }; +- }; +- +- mailbox: mailbox@3024024 { +- compatible = "brcm,iproc-mailbox"; +- reg = <0x03024024 0x40>; +- interrupts = ; +- #interrupt-cells = <1>; +- interrupt-controller; +- #mbox-cells = <1>; +- }; +- +- gpio_crmu: gpio@3024800 { +- compatible = "brcm,cygnus-crmu-gpio"; +- reg = <0x03024800 0x50>, +- <0x03024008 0x18>; +- ngpios = <6>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupt-parent = <&mailbox>; +- interrupts = <0>; +- }; +- +- mdio: mdio@18002000 { +- compatible = "brcm,iproc-mdio"; +- reg = <0x18002000 0x8>; +- #size-cells = <0>; +- #address-cells = <1>; +- status = "disabled"; +- +- gphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- gphy1: ethernet-phy@1 { +- reg = <1>; +- }; +- }; +- +- switch: switch@18007000 { +- compatible = "brcm,bcm11360-srab", "brcm,cygnus-srab"; +- reg = <0x18007000 0x1000>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- phy-handle = <&gphy0>; +- phy-mode = "rgmii"; +- }; +- +- port@1 { +- reg = <1>; +- phy-handle = <&gphy1>; +- phy-mode = "rgmii"; +- }; +- +- port@8 { +- reg = <8>; +- label = "cpu"; +- ethernet = <ð0>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; +- +- i2c0: i2c@18008000 { +- compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; +- reg = <0x18008000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clock-frequency = <100000>; +- status = "disabled"; +- }; +- +- wdt0: wdt@18009000 { +- compatible = "arm,sp805" , "arm,primecell"; +- reg = <0x18009000 0x1000>; +- interrupts = ; +- clocks = <&axi81_clk>, <&axi81_clk>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- gpio_ccm: gpio@1800a000 { +- compatible = "brcm,cygnus-ccm-gpio"; +- reg = <0x1800a000 0x50>, +- <0x0301d164 0x20>; +- ngpios = <24>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupts = ; +- interrupt-controller; +- }; +- +- i2c1: i2c@1800b000 { +- compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; +- reg = <0x1800b000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clock-frequency = <100000>; +- status = "disabled"; +- }; +- +- pcie0: pcie@18012000 { +- compatible = "brcm,iproc-pcie"; +- reg = <0x18012000 0x1000>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; +- +- linux,pci-domain = <0>; +- +- bus-range = <0x00 0xff>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x81000000 0 0 0x28000000 0 0x00010000 +- 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; +- +- phys = <&pcie0_phy>; +- phy-names = "pcie-phy"; +- +- status = "disabled"; +- +- msi-parent = <&msi0>; +- msi0: msi-controller { +- compatible = "brcm,iproc-msi"; +- msi-controller; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- }; +- }; +- +- pcie1: pcie@18013000 { +- compatible = "brcm,iproc-pcie"; +- reg = <0x18013000 0x1000>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; +- +- linux,pci-domain = <1>; +- +- bus-range = <0x00 0xff>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x81000000 0 0 0x48000000 0 0x00010000 +- 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; +- +- phys = <&pcie1_phy>; +- phy-names = "pcie-phy"; +- +- status = "disabled"; +- +- msi-parent = <&msi1>; +- msi1: msi-controller { +- compatible = "brcm,iproc-msi"; +- msi-controller; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- }; +- }; +- +- dma0: dma@18018000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x18018000 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&apb_clk>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- }; +- +- uart0: serial@18020000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x18020000 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; +- interrupts = ; +- clocks = <&axi81_clk>; +- clock-frequency = <100000000>; +- status = "disabled"; +- }; +- +- uart1: serial@18021000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x18021000 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; +- interrupts = ; +- clocks = <&axi81_clk>; +- clock-frequency = <100000000>; +- status = "disabled"; +- }; +- +- uart2: serial@18022000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x18022000 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; +- interrupts = ; +- clocks = <&axi81_clk>; +- clock-frequency = <100000000>; +- status = "disabled"; +- }; +- +- uart3: serial@18023000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x18023000 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; +- interrupts = ; +- clocks = <&axi81_clk>; +- clock-frequency = <100000000>; +- status = "disabled"; +- }; +- +- spi0: spi@18028000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x18028000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- pinctrl-0 = <&spi_0>; +- clocks = <&axi81_clk>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- spi1: spi@18029000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x18029000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- pinctrl-0 = <&spi_1>; +- clocks = <&axi81_clk>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- spi2: spi@1802a000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x1802a000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- pinctrl-0 = <&spi_2>; +- clocks = <&axi81_clk>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- rng: rng@18032000 { +- compatible = "brcm,iproc-rng200"; +- reg = <0x18032000 0x28>; +- }; +- +- sdhci0: sdhci@18041000 { +- compatible = "brcm,sdhci-iproc-cygnus"; +- reg = <0x18041000 0x100>; +- interrupts = ; +- clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>; +- bus-width = <4>; +- sdhci,auto-cmd12; +- status = "disabled"; +- }; +- +- eth0: ethernet@18042000 { +- compatible = "brcm,amac"; +- reg = <0x18042000 0x1000>, +- <0x18110000 0x1000>; +- reg-names = "amac_base", "idm_base"; +- interrupts = ; +- status = "disabled"; +- }; +- +- sdhci1: sdhci@18043000 { +- compatible = "brcm,sdhci-iproc-cygnus"; +- reg = <0x18043000 0x100>; +- interrupts = ; +- clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>; +- bus-width = <4>; +- sdhci,auto-cmd12; +- status = "disabled"; +- }; +- +- nand_controller: nand-controller@18046000 { +- compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; +- reg = <0x18046000 0x600>, <0xf8105408 0x600>, +- <0x18046f00 0x20>; +- reg-names = "nand", "iproc-idm", "iproc-ext"; +- interrupts = ; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- brcm,nand-has-wp; +- }; +- +- ehci0: usb@18048000 { +- compatible = "generic-ehci"; +- reg = <0x18048000 0x100>; +- interrupts = ; +- status = "disabled"; +- }; +- +- ohci0: usb@18048800 { +- compatible = "generic-ohci"; +- reg = <0x18048800 0x100>; +- interrupts = ; +- status = "disabled"; +- }; +- +- clcd: clcd@180a0000 { +- compatible = "arm,pl111", "arm,primecell"; +- reg = <0x180a0000 0x1000>; +- interrupts = ; +- interrupt-names = "combined"; +- clocks = <&axi41_clk>, <&apb_clk>; +- clock-names = "clcdclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- v3d: v3d@180a2000 { +- compatible = "brcm,cygnus-v3d"; +- reg = <0x180a2000 0x1000>; +- clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>; +- clock-names = "v3d_clk"; +- interrupts = ; +- status = "disabled"; +- }; +- +- vc4: gpu { +- compatible = "brcm,cygnus-vc4"; +- }; +- +- gpio_asiu: gpio@180a5000 { +- compatible = "brcm,cygnus-asiu-gpio"; +- reg = <0x180a5000 0x668>; +- ngpios = <146>; +- #gpio-cells = <2>; +- gpio-controller; +- +- interrupt-controller; +- interrupts = ; +- gpio-ranges = <&pinctrl 0 42 1>, +- <&pinctrl 1 44 3>, +- <&pinctrl 4 48 1>, +- <&pinctrl 5 50 3>, +- <&pinctrl 8 126 1>, +- <&pinctrl 9 155 1>, +- <&pinctrl 10 152 1>, +- <&pinctrl 11 154 1>, +- <&pinctrl 12 153 1>, +- <&pinctrl 13 127 3>, +- <&pinctrl 16 140 1>, +- <&pinctrl 17 145 7>, +- <&pinctrl 24 130 10>, +- <&pinctrl 34 141 4>, +- <&pinctrl 38 54 1>, +- <&pinctrl 39 56 3>, +- <&pinctrl 42 60 3>, +- <&pinctrl 45 64 3>, +- <&pinctrl 48 68 2>, +- <&pinctrl 50 84 6>, +- <&pinctrl 56 94 6>, +- <&pinctrl 62 72 1>, +- <&pinctrl 63 70 1>, +- <&pinctrl 64 80 1>, +- <&pinctrl 65 74 3>, +- <&pinctrl 68 78 1>, +- <&pinctrl 69 82 1>, +- <&pinctrl 70 156 17>, +- <&pinctrl 87 104 12>, +- <&pinctrl 99 102 2>, +- <&pinctrl 101 90 4>, +- <&pinctrl 105 116 6>, +- <&pinctrl 111 100 2>, +- <&pinctrl 113 122 4>, +- <&pinctrl 123 11 1>, +- <&pinctrl 124 38 4>, +- <&pinctrl 128 43 1>, +- <&pinctrl 129 47 1>, +- <&pinctrl 130 49 1>, +- <&pinctrl 131 53 1>, +- <&pinctrl 132 55 1>, +- <&pinctrl 133 59 1>, +- <&pinctrl 134 63 1>, +- <&pinctrl 135 67 1>, +- <&pinctrl 136 71 1>, +- <&pinctrl 137 73 1>, +- <&pinctrl 138 77 1>, +- <&pinctrl 139 79 1>, +- <&pinctrl 140 81 1>, +- <&pinctrl 141 83 1>, +- <&pinctrl 142 10 1>; +- }; +- +- ts_adc_syscon: ts_adc_syscon@180a6000 { +- compatible = "brcm,iproc-ts-adc-syscon", "syscon"; +- reg = <0x180a6000 0xc30>; +- }; +- +- touchscreen: touchscreen@180a6000 { +- compatible = "brcm,iproc-touchscreen"; +- #address-cells = <1>; +- #size-cells = <1>; +- ts_syscon = <&ts_adc_syscon>; +- clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; +- clock-names = "tsc_clk"; +- interrupts = ; +- status = "disabled"; +- }; +- +- adc: adc@180a6000 { +- compatible = "brcm,iproc-static-adc"; +- #io-channel-cells = <1>; +- adc-syscon = <&ts_adc_syscon>; +- clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; +- clock-names = "tsc_clk"; +- interrupts = ; +- status = "disabled"; +- }; +- +- pwm: pwm@180aa500 { +- compatible = "brcm,kona-pwm"; +- reg = <0x180aa500 0xc4>; +- #pwm-cells = <3>; +- clocks = <&asiu_clks BCM_CYGNUS_ASIU_PWM_CLK>; +- status = "disabled"; +- }; +- +- keypad: keypad@180ac000 { +- compatible = "brcm,bcm-keypad"; +- reg = <0x180ac000 0x14c>; +- interrupts = ; +- clocks = <&asiu_clks BCM_CYGNUS_ASIU_KEYPAD_CLK>; +- clock-names = "peri_clk"; +- clock-frequency = <31250>; +- pull-up-enabled; +- col-debounce-filter-period = <0>; +- status-debounce-filter-period = <0>; +- row-output-enabled; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm-hr2.dtsi b/scripts/dtc/include-prefixes/arm/bcm-hr2.dtsi +deleted file mode 100644 +index 84cda16f68a2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm-hr2.dtsi ++++ /dev/null +@@ -1,368 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2017 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#include +-#include +- +-/ { +- compatible = "brcm,hr2"; +- model = "Broadcom Hurricane 2 SoC"; +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- reg = <0x0>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = ; +- interrupt-affinity = <&cpu0>; +- }; +- +- mpcore@19000000 { +- compatible = "simple-bus"; +- ranges = <0x00000000 0x19000000 0x00023000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- a9pll: arm_clk@0 { +- #clock-cells = <0>; +- compatible = "brcm,hr2-armpll"; +- clocks = <&osc>; +- reg = <0x0 0x1000>; +- }; +- +- timer@20200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0x20200 0x100>; +- interrupts = ; +- clocks = <&periph_clk>; +- }; +- +- twd-timer@20600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x20600 0x20>; +- interrupts = ; +- clocks = <&periph_clk>; +- }; +- +- twd-watchdog@20620 { +- compatible = "arm,cortex-a9-twd-wdt"; +- reg = <0x20620 0x20>; +- interrupts = ; +- clocks = <&periph_clk>; +- }; +- +- gic: interrupt-controller@21000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x21000 0x1000>, +- <0x20100 0x100>; +- }; +- +- L2: cache-controller@22000 { +- compatible = "arm,pl310-cache"; +- reg = <0x22000 0x1000>; +- cache-unified; +- cache-level = <2>; +- }; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- osc: oscillator { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25000000>; +- }; +- +- periph_clk: periph_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&a9pll>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- }; +- +- axi@18000000 { +- compatible = "simple-bus"; +- ranges = <0x00000000 0x18000000 0x0011c40c>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- uart0: serial@300 { +- compatible = "ns16550a"; +- reg = <0x0300 0x100>; +- interrupts = ; +- clocks = <&osc>; +- status = "disabled"; +- }; +- +- uart1: serial@400 { +- compatible = "ns16550a"; +- reg = <0x0400 0x100>; +- interrupts = ; +- clocks = <&osc>; +- status = "disabled"; +- }; +- +- dma@20000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x20000 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- #dma-cells = <1>; +- status = "disabled"; +- }; +- +- amac0: ethernet@22000 { +- compatible = "brcm,nsp-amac"; +- reg = <0x22000 0x1000>, +- <0x110000 0x1000>; +- reg-names = "amac_base", "idm_base"; +- interrupts = ; +- status = "disabled"; +- }; +- +- nand_controller: nand-controller@26000 { +- compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; +- reg = <0x26000 0x600>, +- <0x11b408 0x600>, +- <0x026f00 0x20>; +- reg-names = "nand", "iproc-idm", "iproc-ext"; +- interrupts = ; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- brcm,nand-has-wp; +- }; +- +- gpiob: gpio@30000 { +- compatible = "brcm,iproc-hr2-gpio", "brcm,iproc-gpio"; +- reg = <0x30000 0x50>; +- #gpio-cells = <2>; +- gpio-controller; +- ngpios = <4>; +- interrupt-controller; +- interrupts = ; +- }; +- +- pwm: pwm@31000 { +- compatible = "brcm,iproc-pwm"; +- reg = <0x31000 0x28>; +- clocks = <&osc>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- rng: rng@33000 { +- compatible = "brcm,bcm-nsp-rng"; +- reg = <0x33000 0x14>; +- }; +- +- qspi: spi@27200 { +- compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; +- reg = <0x027200 0x184>, +- <0x027000 0x124>, +- <0x11c408 0x004>, +- <0x0273a0 0x01c>; +- reg-names = "mspi", "bspi", "intr_regs", +- "intr_status_reg"; +- interrupts = , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "spi_lr_fullness_reached", +- "spi_lr_session_aborted", +- "spi_lr_impatient", +- "spi_lr_session_done", +- "spi_lr_overhead", +- "mspi_done", +- "mspi_halted"; +- num-cs = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* partitions defined in board DTS */ +- }; +- +- ccbtimer0: timer@34000 { +- compatible = "arm,sp804"; +- reg = <0x34000 0x1000>; +- interrupts = , +- ; +- }; +- +- ccbtimer1: timer@35000 { +- compatible = "arm,sp804"; +- reg = <0x35000 0x1000>; +- interrupts = , +- ; +- }; +- +- i2c0: i2c@38000 { +- compatible = "brcm,iproc-i2c"; +- reg = <0x38000 0x50>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clock-frequency = <100000>; +- }; +- +- watchdog: watchdog@39000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x39000 0x1000>; +- interrupts = ; +- }; +- +- i2c1: i2c@3b000 { +- compatible = "brcm,iproc-i2c"; +- reg = <0x3b000 0x50>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clock-frequency = <100000>; +- }; +- }; +- +- pflash: nor@20000000 { +- compatible = "cfi-flash", "jedec-flash"; +- reg = <0x20000000 0x04000000>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* partitions defined in board DTS */ +- }; +- +- pcie0: pcie@18012000 { +- compatible = "brcm,iproc-pcie"; +- reg = <0x18012000 0x1000>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; +- +- linux,pci-domain = <0>; +- +- bus-range = <0x00 0xff>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- +- /* Note: The HW does not support I/O resources. So, +- * only the memory resource range is being specified. +- */ +- ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; +- +- status = "disabled"; +- +- msi-parent = <&msi0>; +- msi0: msi-controller { +- compatible = "brcm,iproc-msi"; +- msi-controller; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- brcm,pcie-msi-inten; +- }; +- }; +- +- pcie1: pcie@18013000 { +- compatible = "brcm,iproc-pcie"; +- reg = <0x18013000 0x1000>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; +- +- linux,pci-domain = <1>; +- +- bus-range = <0x00 0xff>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- +- /* Note: The HW does not support I/O resources. So, +- * only the memory resource range is being specified. +- */ +- ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; +- +- status = "disabled"; +- +- msi-parent = <&msi1>; +- msi1: msi-controller { +- compatible = "brcm,iproc-msi"; +- msi-controller; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- brcm,pcie-msi-inten; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm-nsp.dtsi b/scripts/dtc/include-prefixes/arm/bcm-nsp.dtsi +deleted file mode 100644 +index e96ddb2e26e2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm-nsp.dtsi ++++ /dev/null +@@ -1,663 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2015 Broadcom Corporation. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "brcm,nsp"; +- model = "Broadcom Northstar Plus SoC"; +- interrupt-parent = <&gic>; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- ethernet0 = &amac0; +- ethernet1 = &amac1; +- ethernet2 = &amac2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- reg = <0x0>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- enable-method = "brcm,bcm-nsp-smp"; +- secondary-boot-reg = <0xffff0fec>; +- reg = <0x1>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = ; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- mpcore-bus@19000000 { +- compatible = "simple-bus"; +- ranges = <0x00000000 0x19000000 0x00023000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- a9pll: arm_clk@0 { +- #clock-cells = <0>; +- compatible = "brcm,nsp-armpll"; +- clocks = <&osc>; +- reg = <0x00000 0x1000>; +- }; +- +- timer@20200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0x20200 0x100>; +- interrupts = ; +- clocks = <&periph_clk>; +- }; +- +- twd-timer@20600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x20600 0x20>; +- interrupts = ; +- clocks = <&periph_clk>; +- }; +- +- twd-watchdog@20620 { +- compatible = "arm,cortex-a9-twd-wdt"; +- reg = <0x20620 0x20>; +- interrupts = ; +- clocks = <&periph_clk>; +- }; +- +- gic: interrupt-controller@21000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x21000 0x1000>, +- <0x20100 0x100>; +- }; +- +- L2: cache-controller@22000 { +- compatible = "arm,pl310-cache"; +- reg = <0x22000 0x1000>; +- cache-unified; +- cache-level = <2>; +- }; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- osc: oscillator { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25000000>; +- }; +- +- iprocmed: iprocmed { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- iprocslow: iprocslow { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; +- clock-div = <4>; +- clock-mult = <1>; +- }; +- +- periph_clk: periph_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&a9pll>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- }; +- +- axi@18000000 { +- compatible = "simple-bus"; +- ranges = <0x00000000 0x18000000 0x0011c40c>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- gpioa: gpio@20 { +- compatible = "brcm,nsp-gpio-a"; +- reg = <0x0020 0x70>, +- <0x3f1c4 0x1c>; +- #gpio-cells = <2>; +- gpio-controller; +- ngpios = <32>; +- interrupt-controller; +- interrupts = ; +- gpio-ranges = <&pinctrl 0 0 32>; +- }; +- +- uart0: serial@300 { +- compatible = "ns16550a"; +- reg = <0x0300 0x100>; +- interrupts = ; +- clocks = <&osc>; +- status = "disabled"; +- }; +- +- uart1: serial@400 { +- compatible = "ns16550a"; +- reg = <0x0400 0x100>; +- interrupts = ; +- clocks = <&osc>; +- status = "disabled"; +- }; +- +- dma: dma@20000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x20000 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&iprocslow>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- dma-coherent; +- status = "disabled"; +- }; +- +- sdio: mmc@21000 { +- compatible = "brcm,sdhci-iproc-cygnus"; +- reg = <0x21000 0x100>; +- interrupts = ; +- sdhci,auto-cmd12; +- clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>; +- dma-coherent; +- status = "disabled"; +- }; +- +- amac0: ethernet@22000 { +- compatible = "brcm,nsp-amac"; +- reg = <0x022000 0x1000>, +- <0x110000 0x1000>; +- reg-names = "amac_base", "idm_base"; +- interrupts = ; +- dma-coherent; +- status = "disabled"; +- }; +- +- amac1: ethernet@23000 { +- compatible = "brcm,nsp-amac"; +- reg = <0x023000 0x1000>, +- <0x111000 0x1000>; +- reg-names = "amac_base", "idm_base"; +- interrupts = ; +- dma-coherent; +- status = "disabled"; +- }; +- +- amac2: ethernet@24000 { +- compatible = "brcm,nsp-amac"; +- reg = <0x024000 0x1000>, +- <0x112000 0x1000>; +- reg-names = "amac_base", "idm_base"; +- interrupts = ; +- dma-coherent; +- status = "disabled"; +- }; +- +- mailbox: mailbox@25c00 { +- compatible = "brcm,iproc-fa2-mbox"; +- reg = <0x25c00 0x400>; +- interrupts = ; +- #mbox-cells = <1>; +- brcm,rx-status-len = <32>; +- brcm,use-bcm-hdr; +- dma-coherent; +- }; +- +- nand_controller: nand-controller@26000 { +- compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; +- reg = <0x026000 0x600>, +- <0x11b408 0x600>, +- <0x026f00 0x20>; +- reg-names = "nand", "iproc-idm", "iproc-ext"; +- interrupts = ; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- brcm,nand-has-wp; +- }; +- +- qspi: spi@27200 { +- compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; +- reg = <0x027200 0x184>, +- <0x027000 0x124>, +- <0x11c408 0x004>, +- <0x0273a0 0x01c>; +- reg-names = "mspi", "bspi", "intr_regs", +- "intr_status_reg"; +- interrupts = , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "spi_lr_fullness_reached", +- "spi_lr_session_aborted", +- "spi_lr_impatient", +- "spi_lr_session_done", +- "spi_lr_overhead", +- "mspi_done", +- "mspi_halted"; +- clocks = <&iprocmed>; +- clock-names = "iprocmed"; +- num-cs = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- xhci: usb@29000 { +- compatible = "generic-xhci"; +- reg = <0x29000 0x1000>; +- interrupts = ; +- phys = <&usb3_phy>; +- phy-names = "usb3-phy"; +- dma-coherent; +- status = "disabled"; +- }; +- +- ehci0: usb@2a000 { +- compatible = "generic-ehci"; +- reg = <0x2a000 0x100>; +- interrupts = ; +- dma-coherent; +- status = "disabled"; +- }; +- +- ohci0: usb@2b000 { +- compatible = "generic-ohci"; +- reg = <0x2b000 0x100>; +- interrupts = ; +- dma-coherent; +- status = "disabled"; +- }; +- +- crypto@2f000 { +- compatible = "brcm,spum-nsp-crypto"; +- reg = <0x2f000 0x900>; +- mboxes = <&mailbox 0>; +- }; +- +- gpiob: gpio@30000 { +- compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio"; +- reg = <0x30000 0x50>; +- #gpio-cells = <2>; +- gpio-controller; +- ngpios = <4>; +- interrupt-controller; +- interrupts = ; +- }; +- +- pwm: pwm@31000 { +- compatible = "brcm,iproc-pwm"; +- reg = <0x31000 0x28>; +- clocks = <&osc>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- rng: rng@33000 { +- compatible = "brcm,bcm-nsp-rng"; +- reg = <0x33000 0x14>; +- }; +- +- ccbtimer0: timer@34000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x34000 0x1000>; +- interrupts = , +- ; +- clocks = <&iprocslow>; +- clock-names = "apb_pclk"; +- }; +- +- ccbtimer1: timer@35000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x35000 0x1000>; +- interrupts = , +- ; +- clocks = <&iprocslow>; +- clock-names = "apb_pclk"; +- }; +- +- srab: ethernet-switch@36000 { +- compatible = "brcm,nsp-srab"; +- reg = <0x36000 0x1000>, +- <0x3f308 0x8>, +- <0x3f410 0xc>; +- reg-names = "srab", "mux_config", "sgmii_config"; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "link_state_p0", +- "link_state_p1", +- "link_state_p2", +- "link_state_p3", +- "link_state_p4", +- "link_state_p5", +- "link_state_p7", +- "link_state_p8", +- "phy", +- "ts", +- "imp_sleep_timer_p5", +- "imp_sleep_timer_p7", +- "imp_sleep_timer_p8"; +- status = "disabled"; +- +- /* ports are defined in board DTS */ +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- i2c0: i2c@38000 { +- compatible = "brcm,iproc-i2c"; +- reg = <0x38000 0x50>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clock-frequency = <100000>; +- dma-coherent; +- status = "disabled"; +- }; +- +- watchdog@39000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x39000 0x1000>; +- interrupts = ; +- clocks = <&iprocslow>, <&iprocslow>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- lcpll0: lcpll0@3f100 { +- #clock-cells = <1>; +- compatible = "brcm,nsp-lcpll0"; +- reg = <0x3f100 0x14>; +- clocks = <&osc>; +- clock-output-names = "lcpll0", "pcie_phy", "sdio", +- "ddr_phy"; +- }; +- +- genpll: genpll@3f140 { +- #clock-cells = <1>; +- compatible = "brcm,nsp-genpll"; +- reg = <0x3f140 0x24>; +- clocks = <&osc>; +- clock-output-names = "genpll", "phy", "ethernetclk", +- "usbclk", "iprocfast", "sata1", +- "sata2"; +- }; +- +- pinctrl: pinctrl@3f1c0 { +- compatible = "brcm,nsp-pinmux"; +- reg = <0x3f1c0 0x04>, +- <0x30028 0x04>, +- <0x3f408 0x04>; +- }; +- +- thermal: thermal@3f2c0 { +- compatible = "brcm,ns-thermal"; +- reg = <0x3f2c0 0x10>; +- #thermal-sensor-cells = <0>; +- }; +- +- sata_phy: sata_phy@40100 { +- compatible = "brcm,iproc-nsp-sata-phy"; +- reg = <0x40100 0x340>; +- reg-names = "phy"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- sata_phy0: sata-phy@0 { +- reg = <0>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- sata_phy1: sata-phy@1 { +- reg = <1>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- sata: ahci@41000 { +- compatible = "brcm,bcm-nsp-ahci"; +- reg-names = "ahci", "top-ctrl"; +- reg = <0x41000 0x1000>, <0x40020 0x1c>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- dma-coherent; +- status = "disabled"; +- +- sata0: sata-port@0 { +- reg = <0>; +- phys = <&sata_phy0>; +- phy-names = "sata-phy"; +- }; +- +- sata1: sata-port@1 { +- reg = <1>; +- phys = <&sata_phy1>; +- phy-names = "sata-phy"; +- }; +- }; +- +- usb3_phy: usb3-phy@104000 { +- compatible = "brcm,ns-bx-usb3-phy"; +- reg = <0x104000 0x1000>, +- <0x032000 0x1000>; +- reg-names = "dmp", "ccb-mii"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- pcie0: pcie@18012000 { +- compatible = "brcm,iproc-pcie"; +- reg = <0x18012000 0x1000>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; +- +- linux,pci-domain = <0>; +- +- bus-range = <0x00 0xff>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- +- /* Note: The HW does not support I/O resources. So, +- * only the memory resource range is being specified. +- */ +- ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; +- +- dma-coherent; +- status = "disabled"; +- +- msi-parent = <&msi0>; +- msi0: msi-controller { +- compatible = "brcm,iproc-msi"; +- msi-controller; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- brcm,pcie-msi-inten; +- }; +- }; +- +- pcie1: pcie@18013000 { +- compatible = "brcm,iproc-pcie"; +- reg = <0x18013000 0x1000>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; +- +- linux,pci-domain = <1>; +- +- bus-range = <0x00 0xff>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- +- /* Note: The HW does not support I/O resources. So, +- * only the memory resource range is being specified. +- */ +- ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; +- +- dma-coherent; +- status = "disabled"; +- +- msi-parent = <&msi1>; +- msi1: msi-controller { +- compatible = "brcm,iproc-msi"; +- msi-controller; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- brcm,pcie-msi-inten; +- }; +- }; +- +- pcie2: pcie@18014000 { +- compatible = "brcm,iproc-pcie"; +- reg = <0x18014000 0x1000>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; +- +- linux,pci-domain = <2>; +- +- bus-range = <0x00 0xff>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- +- /* Note: The HW does not support I/O resources. So, +- * only the memory resource range is being specified. +- */ +- ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>; +- +- dma-coherent; +- status = "disabled"; +- +- msi-parent = <&msi2>; +- msi2: msi-controller { +- compatible = "brcm,iproc-msi"; +- msi-controller; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- brcm,pcie-msi-inten; +- }; +- }; +- +- thermal-zones { +- cpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <1000>; +- coefficients = <(-556) 418000>; +- thermal-sensors = <&thermal>; +- +- trips { +- cpu-crit { +- temperature = <125000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm11351.dtsi b/scripts/dtc/include-prefixes/arm/bcm11351.dtsi +deleted file mode 100644 +index 6197e7d80e3b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm11351.dtsi ++++ /dev/null +@@ -1,424 +0,0 @@ +-/* +- * Copyright (C) 2012-2013 Broadcom Corporation +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation version 2. +- * +- * This program is distributed "as is" WITHOUT ANY WARRANTY of any +- * kind, whether express or implied; without even the implied warranty +- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#include +-#include +- +-#include "dt-bindings/clock/bcm281xx.h" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "BCM11351 SoC"; +- compatible = "brcm,bcm11351"; +- interrupt-parent = <&gic>; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- enable-method = "brcm,bcm11351-cpu-method"; +- secondary-boot-reg = <0x3500417c>; +- reg = <1>; +- }; +- }; +- +- gic: interrupt-controller@3ff00100 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x3ff01000 0x1000>, +- <0x3ff00100 0x100>; +- }; +- +- smc@3404c000 { +- compatible = "brcm,bcm11351-smc", "brcm,kona-smc"; +- reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */ +- }; +- +- uart@3e000000 { +- compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; +- status = "disabled"; +- reg = <0x3e000000 0x1000>; +- clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- uart@3e001000 { +- compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; +- status = "disabled"; +- reg = <0x3e001000 0x1000>; +- clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- uart@3e002000 { +- compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; +- status = "disabled"; +- reg = <0x3e002000 0x1000>; +- clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- uart@3e003000 { +- compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; +- status = "disabled"; +- reg = <0x3e003000 0x1000>; +- clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- L2: l2-cache@3ff20000 { +- compatible = "brcm,bcm11351-a2-pl310-cache"; +- reg = <0x3ff20000 0x1000>; +- cache-unified; +- cache-level = <2>; +- }; +- +- watchdog@35002f40 { +- compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt"; +- reg = <0x35002f40 0x6c>; +- }; +- +- timer@35006000 { +- compatible = "brcm,kona-timer"; +- reg = <0x35006000 0x1000>; +- interrupts = ; +- clocks = <&aon_ccu BCM281XX_AON_CCU_HUB_TIMER>; +- }; +- +- gpio: gpio@35003000 { +- compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio"; +- reg = <0x35003000 0x800>; +- interrupts = +- ; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- gpio-controller; +- interrupt-controller; +- }; +- +- sdio1: sdio@3f180000 { +- compatible = "brcm,kona-sdhci"; +- reg = <0x3f180000 0x10000>; +- interrupts = ; +- clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO1>; +- status = "disabled"; +- }; +- +- sdio2: sdio@3f190000 { +- compatible = "brcm,kona-sdhci"; +- reg = <0x3f190000 0x10000>; +- interrupts = ; +- clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO2>; +- status = "disabled"; +- }; +- +- sdio3: sdio@3f1a0000 { +- compatible = "brcm,kona-sdhci"; +- reg = <0x3f1a0000 0x10000>; +- interrupts = ; +- clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO3>; +- status = "disabled"; +- }; +- +- sdio4: sdio@3f1b0000 { +- compatible = "brcm,kona-sdhci"; +- reg = <0x3f1b0000 0x10000>; +- interrupts = ; +- clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO4>; +- status = "disabled"; +- }; +- +- pinctrl@35004800 { +- compatible = "brcm,bcm11351-pinctrl"; +- reg = <0x35004800 0x430>; +- }; +- +- i2c@3e016000 { +- compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; +- reg = <0x3e016000 0x80>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC1>; +- status = "disabled"; +- }; +- +- i2c@3e017000 { +- compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; +- reg = <0x3e017000 0x80>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC2>; +- status = "disabled"; +- }; +- +- i2c@3e018000 { +- compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; +- reg = <0x3e018000 0x80>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC3>; +- status = "disabled"; +- }; +- +- i2c@3500d000 { +- compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; +- reg = <0x3500d000 0x80>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&aon_ccu BCM281XX_AON_CCU_PMU_BSC>; +- status = "disabled"; +- }; +- +- pwm: pwm@3e01a000 { +- compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm"; +- reg = <0x3e01a000 0xcc>; +- clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- root_ccu: root_ccu@35001000 { +- compatible = "brcm,bcm11351-root-ccu"; +- reg = <0x35001000 0x0f00>; +- #clock-cells = <1>; +- clock-output-names = "frac_1m"; +- }; +- +- hub_ccu: hub_ccu@34000000 { +- compatible = "brcm,bcm11351-hub-ccu"; +- reg = <0x34000000 0x0f00>; +- #clock-cells = <1>; +- clock-output-names = "tmon_1m"; +- }; +- +- aon_ccu: aon_ccu@35002000 { +- compatible = "brcm,bcm11351-aon-ccu"; +- reg = <0x35002000 0x0f00>; +- #clock-cells = <1>; +- clock-output-names = "hub_timer", +- "pmu_bsc", +- "pmu_bsc_var"; +- }; +- +- master_ccu: master_ccu@3f001000 { +- compatible = "brcm,bcm11351-master-ccu"; +- reg = <0x3f001000 0x0f00>; +- #clock-cells = <1>; +- clock-output-names = "sdio1", +- "sdio2", +- "sdio3", +- "sdio4", +- "usb_ic", +- "hsic2_48m", +- "hsic2_12m"; +- }; +- +- slave_ccu: slave_ccu@3e011000 { +- compatible = "brcm,bcm11351-slave-ccu"; +- reg = <0x3e011000 0x0f00>; +- #clock-cells = <1>; +- clock-output-names = "uartb", +- "uartb2", +- "uartb3", +- "uartb4", +- "ssp0", +- "ssp2", +- "bsc1", +- "bsc2", +- "bsc3", +- "pwm"; +- }; +- +- ref_1m_clk: ref_1m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <1000000>; +- }; +- +- ref_32k_clk: ref_32k { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- bbl_32k_clk: bbl_32k { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- ref_13m_clk: ref_13m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <13000000>; +- }; +- +- var_13m_clk: var_13m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <13000000>; +- }; +- +- dft_19_5m_clk: dft_19_5m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <19500000>; +- }; +- +- ref_crystal_clk: ref_crystal { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- }; +- +- ref_cx40_clk: ref_cx40 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <40000000>; +- }; +- +- ref_52m_clk: ref_52m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <52000000>; +- }; +- +- var_52m_clk: var_52m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <52000000>; +- }; +- +- usb_otg_ahb_clk: usb_otg_ahb { +- compatible = "fixed-clock"; +- clock-frequency = <52000000>; +- #clock-cells = <0>; +- }; +- +- ref_96m_clk: ref_96m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <96000000>; +- }; +- +- var_96m_clk: var_96m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <96000000>; +- }; +- +- ref_104m_clk: ref_104m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <104000000>; +- }; +- +- var_104m_clk: var_104m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <104000000>; +- }; +- +- ref_156m_clk: ref_156m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <156000000>; +- }; +- +- var_156m_clk: var_156m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <156000000>; +- }; +- +- ref_208m_clk: ref_208m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <208000000>; +- }; +- +- var_208m_clk: var_208m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <208000000>; +- }; +- +- ref_312m_clk: ref_312m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <312000000>; +- }; +- +- var_312m_clk: var_312m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <312000000>; +- }; +- }; +- +- usbotg: usb@3f120000 { +- compatible = "snps,dwc2"; +- reg = <0x3f120000 0x10000>; +- interrupts = ; +- clocks = <&usb_otg_ahb_clk>; +- clock-names = "otg"; +- phys = <&usbphy>; +- phy-names = "usb2-phy"; +- status = "disabled"; +- }; +- +- usbphy: usb-phy@3f130000 { +- compatible = "brcm,kona-usb2-phy"; +- reg = <0x3f130000 0x28>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm21664-garnet.dts b/scripts/dtc/include-prefixes/arm/bcm21664-garnet.dts +deleted file mode 100644 +index be468f4adc37..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm21664-garnet.dts ++++ /dev/null +@@ -1,57 +0,0 @@ +-/* +- * Copyright (C) 2014 Broadcom Corporation +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation version 2. +- * +- * This program is distributed "as is" WITHOUT ANY WARRANTY of any +- * kind, whether express or implied; without even the implied warranty +- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-/dts-v1/; +- +-#include +- +-#include "bcm21664.dtsi" +- +-/ { +- model = "BCM21664 Garnet board"; +- compatible = "brcm,bcm21664-garnet", "brcm,bcm21664"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; /* 1 GB */ +- }; +- +- uart@3e000000 { +- status = "okay"; +- }; +- +- sdio1: sdio@3f180000 { +- max-frequency = <48000000>; +- status = "okay"; +- }; +- +- sdio2: sdio@3f190000 { +- non-removable; +- max-frequency = <48000000>; +- status = "okay"; +- }; +- +- sdio4: sdio@3f1b0000 { +- max-frequency = <48000000>; +- cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>; +- status = "okay"; +- }; +- +- usbotg: usb@3f120000 { +- status = "okay"; +- }; +- +- usbphy: usb-phy@3f130000 { +- status = "okay"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm21664.dtsi b/scripts/dtc/include-prefixes/arm/bcm21664.dtsi +deleted file mode 100644 +index cc58f2b926b9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm21664.dtsi ++++ /dev/null +@@ -1,357 +0,0 @@ +-/* +- * Copyright (C) 2014 Broadcom Corporation +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation version 2. +- * +- * This program is distributed "as is" WITHOUT ANY WARRANTY of any +- * kind, whether express or implied; without even the implied warranty +- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#include +-#include +- +-#include "dt-bindings/clock/bcm21664.h" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "BCM21664 SoC"; +- compatible = "brcm,bcm21664"; +- interrupt-parent = <&gic>; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- enable-method = "brcm,bcm11351-cpu-method"; +- secondary-boot-reg = <0x35004178>; +- reg = <1>; +- }; +- }; +- +- gic: interrupt-controller@3ff00100 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x3ff01000 0x1000>, +- <0x3ff00100 0x100>; +- }; +- +- smc@3404e000 { +- compatible = "brcm,bcm21664-smc", "brcm,kona-smc"; +- reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */ +- }; +- +- uart@3e000000 { +- compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; +- status = "disabled"; +- reg = <0x3e000000 0x118>; +- clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- uart@3e001000 { +- compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; +- status = "disabled"; +- reg = <0x3e001000 0x118>; +- clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- uart@3e002000 { +- compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; +- status = "disabled"; +- reg = <0x3e002000 0x118>; +- clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- L2: cache-controller@3ff20000 { +- compatible = "arm,pl310-cache"; +- reg = <0x3ff20000 0x1000>; +- cache-unified; +- cache-level = <2>; +- }; +- +- brcm,resetmgr@35001f00 { +- compatible = "brcm,bcm21664-resetmgr"; +- reg = <0x35001f00 0x24>; +- }; +- +- timer@35006000 { +- compatible = "brcm,kona-timer"; +- reg = <0x35006000 0x1c>; +- interrupts = ; +- clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; +- }; +- +- gpio: gpio@35003000 { +- compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio"; +- reg = <0x35003000 0x524>; +- interrupts = +- ; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- gpio-controller; +- interrupt-controller; +- }; +- +- sdio1: sdio@3f180000 { +- compatible = "brcm,kona-sdhci"; +- reg = <0x3f180000 0x801c>; +- interrupts = ; +- clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; +- status = "disabled"; +- }; +- +- sdio2: sdio@3f190000 { +- compatible = "brcm,kona-sdhci"; +- reg = <0x3f190000 0x801c>; +- interrupts = ; +- clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; +- status = "disabled"; +- }; +- +- sdio3: sdio@3f1a0000 { +- compatible = "brcm,kona-sdhci"; +- reg = <0x3f1a0000 0x801c>; +- interrupts = ; +- clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; +- status = "disabled"; +- }; +- +- sdio4: sdio@3f1b0000 { +- compatible = "brcm,kona-sdhci"; +- reg = <0x3f1b0000 0x801c>; +- interrupts = ; +- clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; +- status = "disabled"; +- }; +- +- i2c@3e016000 { +- compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; +- reg = <0x3e016000 0x70>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; +- status = "disabled"; +- }; +- +- i2c@3e017000 { +- compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; +- reg = <0x3e017000 0x70>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; +- status = "disabled"; +- }; +- +- i2c@3e018000 { +- compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; +- reg = <0x3e018000 0x70>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; +- status = "disabled"; +- }; +- +- i2c@3e01c000 { +- compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; +- reg = <0x3e01c000 0x70>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; +- status = "disabled"; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* +- * Fixed clocks are defined before CCUs whose +- * clocks may depend on them. +- */ +- +- ref_32k_clk: ref_32k { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- bbl_32k_clk: bbl_32k { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- ref_13m_clk: ref_13m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <13000000>; +- }; +- +- var_13m_clk: var_13m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <13000000>; +- }; +- +- dft_19_5m_clk: dft_19_5m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <19500000>; +- }; +- +- ref_crystal_clk: ref_crystal { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- }; +- +- ref_52m_clk: ref_52m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <52000000>; +- }; +- +- var_52m_clk: var_52m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <52000000>; +- }; +- +- usb_otg_ahb_clk: usb_otg_ahb { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <52000000>; +- }; +- +- ref_96m_clk: ref_96m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <96000000>; +- }; +- +- var_96m_clk: var_96m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <96000000>; +- }; +- +- ref_104m_clk: ref_104m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <104000000>; +- }; +- +- var_104m_clk: var_104m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <104000000>; +- }; +- +- ref_156m_clk: ref_156m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <156000000>; +- }; +- +- var_156m_clk: var_156m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <156000000>; +- }; +- +- root_ccu: root_ccu@35001000 { +- compatible = BCM21664_DT_ROOT_CCU_COMPAT; +- reg = <0x35001000 0x0f00>; +- #clock-cells = <1>; +- clock-output-names = "frac_1m"; +- }; +- +- aon_ccu: aon_ccu@35002000 { +- compatible = BCM21664_DT_AON_CCU_COMPAT; +- reg = <0x35002000 0x0f00>; +- #clock-cells = <1>; +- clock-output-names = "hub_timer"; +- }; +- +- master_ccu: master_ccu@3f001000 { +- compatible = BCM21664_DT_MASTER_CCU_COMPAT; +- reg = <0x3f001000 0x0f00>; +- #clock-cells = <1>; +- clock-output-names = "sdio1", +- "sdio2", +- "sdio3", +- "sdio4", +- "sdio1_sleep", +- "sdio2_sleep", +- "sdio3_sleep", +- "sdio4_sleep"; +- }; +- +- slave_ccu: slave_ccu@3e011000 { +- compatible = BCM21664_DT_SLAVE_CCU_COMPAT; +- reg = <0x3e011000 0x0f00>; +- #clock-cells = <1>; +- clock-output-names = "uartb", +- "uartb2", +- "uartb3", +- "bsc1", +- "bsc2", +- "bsc3", +- "bsc4"; +- }; +- }; +- +- usbotg: usb@3f120000 { +- compatible = "snps,dwc2"; +- reg = <0x3f120000 0x10000>; +- interrupts = ; +- clocks = <&usb_otg_ahb_clk>; +- clock-names = "otg"; +- phys = <&usbphy>; +- phy-names = "usb2-phy"; +- status = "disabled"; +- }; +- +- usbphy: usb-phy@3f130000 { +- compatible = "brcm,kona-usb2-phy"; +- reg = <0x3f130000 0x28>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm23550-sparrow.dts b/scripts/dtc/include-prefixes/arm/bcm23550-sparrow.dts +deleted file mode 100644 +index ace77709f468..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm23550-sparrow.dts ++++ /dev/null +@@ -1,81 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2016 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include +- +-#include "bcm23550.dtsi" +- +-/ { +- model = "BCM23550 Sparrow board"; +- compatible = "brcm,bcm23550-sparrow", "brcm,bcm23550"; +- +- chosen { +- stdout-path = "/slaves@3e000000/serial@0:115200n8"; +- bootargs = "console=ttyS0,115200n8"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512 MB */ +- }; +-}; +- +-&uartb { +- status = "okay"; +-}; +- +-&usbotg { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&sdio1 { +- max-frequency = <48000000>; +- status = "okay"; +-}; +- +-&sdio2 { +- non-removable; +- max-frequency = <48000000>; +- status = "okay"; +-}; +- +-&sdio4 { +- max-frequency = <48000000>; +- cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm23550.dtsi b/scripts/dtc/include-prefixes/arm/bcm23550.dtsi +deleted file mode 100644 +index a36c9b1d23c8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm23550.dtsi ++++ /dev/null +@@ -1,415 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2016 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#include +-#include +- +-/* BCM23550 and BCM21664 have almost identical clocks */ +-#include "dt-bindings/clock/bcm21664.h" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "BCM23550 SoC"; +- compatible = "brcm,bcm23550"; +- interrupt-parent = <&gic>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0>; +- clock-frequency = <1000000000>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- enable-method = "brcm,bcm23550"; +- secondary-boot-reg = <0x35004178>; +- reg = <1>; +- clock-frequency = <1000000000>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- enable-method = "brcm,bcm23550"; +- secondary-boot-reg = <0x35004178>; +- reg = <2>; +- clock-frequency = <1000000000>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- enable-method = "brcm,bcm23550"; +- secondary-boot-reg = <0x35004178>; +- reg = <3>; +- clock-frequency = <1000000000>; +- }; +- }; +- +- /* Hub bus */ +- hub@34000000 { +- compatible = "simple-bus"; +- ranges = <0 0x34000000 0x102f83ac>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- smc@4e000 { +- compatible = "brcm,bcm23550-smc", "brcm,kona-smc"; +- reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */ +- }; +- +- resetmgr: reset-controller@1001f00 { +- compatible = "brcm,bcm21664-resetmgr"; +- reg = <0x01001f00 0x24>; +- }; +- +- gpio: gpio@1003000 { +- compatible = "brcm,bcm23550-gpio", "brcm,kona-gpio"; +- reg = <0x01003000 0x524>; +- interrupts = +- ; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- gpio-controller; +- interrupt-controller; +- }; +- +- timer@1006000 { +- compatible = "brcm,kona-timer"; +- reg = <0x01006000 0x1c>; +- interrupts = ; +- clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; +- }; +- }; +- +- /* Slaves bus */ +- slaves@3e000000 { +- compatible = "simple-bus"; +- ranges = <0 0x3e000000 0x0001c070>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- uartb: serial@0 { +- compatible = "snps,dw-apb-uart"; +- status = "disabled"; +- reg = <0x00000000 0x118>; +- clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- uartb2: serial@1000 { +- compatible = "snps,dw-apb-uart"; +- status = "disabled"; +- reg = <0x00001000 0x118>; +- clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- uartb3: serial@2000 { +- compatible = "snps,dw-apb-uart"; +- status = "disabled"; +- reg = <0x00002000 0x118>; +- clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +- +- bsc1: i2c@16000 { +- compatible = "brcm,kona-i2c"; +- reg = <0x00016000 0x70>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; +- status = "disabled"; +- }; +- +- bsc2: i2c@17000 { +- compatible = "brcm,kona-i2c"; +- reg = <0x00017000 0x70>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; +- status = "disabled"; +- }; +- +- bsc3: i2c@18000 { +- compatible = "brcm,kona-i2c"; +- reg = <0x00018000 0x70>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; +- status = "disabled"; +- }; +- +- bsc4: i2c@1c000 { +- compatible = "brcm,kona-i2c"; +- reg = <0x0001c000 0x70>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; +- status = "disabled"; +- }; +- }; +- +- /* Apps bus */ +- apps@3e300000 { +- compatible = "simple-bus"; +- ranges = <0 0x3e300000 0x01b77000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- usbotg: usb@e20000 { +- compatible = "snps,dwc2"; +- reg = <0x00e20000 0x10000>; +- interrupts = ; +- clocks = <&usb_otg_ahb_clk>; +- clock-names = "otg"; +- phys = <&usbphy>; +- phy-names = "usb2-phy"; +- status = "disabled"; +- }; +- +- usbphy: usb-phy@e30000 { +- compatible = "brcm,kona-usb2-phy"; +- reg = <0x00e30000 0x28>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- sdio1: sdio@e80000 { +- compatible = "brcm,kona-sdhci"; +- reg = <0x00e80000 0x801c>; +- interrupts = ; +- clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; +- status = "disabled"; +- }; +- +- sdio2: sdio@e90000 { +- compatible = "brcm,kona-sdhci"; +- reg = <0x00e90000 0x801c>; +- interrupts = ; +- clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; +- status = "disabled"; +- }; +- +- sdio3: sdio@ea0000 { +- compatible = "brcm,kona-sdhci"; +- reg = <0x00ea0000 0x801c>; +- interrupts = ; +- clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; +- status = "disabled"; +- }; +- +- sdio4: sdio@eb0000 { +- compatible = "brcm,kona-sdhci"; +- reg = <0x00eb0000 0x801c>; +- interrupts = ; +- clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; +- status = "disabled"; +- }; +- +- cdc: cdc@1b0e000 { +- compatible = "brcm,bcm23550-cdc"; +- reg = <0x01b0e000 0x78>; +- }; +- +- gic: interrupt-controller@1b21000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x01b21000 0x1000>, +- <0x01b22000 0x1000>; +- }; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* +- * Fixed clocks are defined before CCUs whose +- * clocks may depend on them. +- */ +- +- ref_32k_clk: ref_32k { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- bbl_32k_clk: bbl_32k { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- ref_13m_clk: ref_13m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <13000000>; +- }; +- +- var_13m_clk: var_13m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <13000000>; +- }; +- +- dft_19_5m_clk: dft_19_5m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <19500000>; +- }; +- +- ref_crystal_clk: ref_crystal { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- }; +- +- ref_52m_clk: ref_52m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <52000000>; +- }; +- +- var_52m_clk: var_52m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <52000000>; +- }; +- +- usb_otg_ahb_clk: usb_otg_ahb { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <52000000>; +- }; +- +- ref_96m_clk: ref_96m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <96000000>; +- }; +- +- var_96m_clk: var_96m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <96000000>; +- }; +- +- ref_104m_clk: ref_104m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <104000000>; +- }; +- +- var_104m_clk: var_104m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <104000000>; +- }; +- +- ref_156m_clk: ref_156m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <156000000>; +- }; +- +- var_156m_clk: var_156m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <156000000>; +- }; +- +- root_ccu: root_ccu@35001000 { +- compatible = BCM21664_DT_ROOT_CCU_COMPAT; +- reg = <0x35001000 0x0f00>; +- #clock-cells = <1>; +- clock-output-names = "frac_1m"; +- }; +- +- aon_ccu: aon_ccu@35002000 { +- compatible = BCM21664_DT_AON_CCU_COMPAT; +- reg = <0x35002000 0x0f00>; +- #clock-cells = <1>; +- clock-output-names = "hub_timer"; +- }; +- +- slave_ccu: slave_ccu@3e011000 { +- compatible = BCM21664_DT_SLAVE_CCU_COMPAT; +- reg = <0x3e011000 0x0f00>; +- #clock-cells = <1>; +- clock-output-names = "uartb", +- "uartb2", +- "uartb3", +- "bsc1", +- "bsc2", +- "bsc3", +- "bsc4"; +- }; +- +- master_ccu: master_ccu@3f001000 { +- compatible = BCM21664_DT_MASTER_CCU_COMPAT; +- reg = <0x3f001000 0x0f00>; +- #clock-cells = <1>; +- clock-output-names = "sdio1", +- "sdio2", +- "sdio3", +- "sdio4", +- "sdio1_sleep", +- "sdio2_sleep", +- "sdio3_sleep", +- "sdio4_sleep"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2711-rpi-4-b.dts b/scripts/dtc/include-prefixes/arm/bcm2711-rpi-4-b.dts +deleted file mode 100644 +index 72ce80fbf266..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2711-rpi-4-b.dts ++++ /dev/null +@@ -1,262 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "bcm2711.dtsi" +-#include "bcm2711-rpi.dtsi" +-#include "bcm283x-rpi-usb-peripheral.dtsi" +- +-/ { +- compatible = "raspberrypi,4-model-b", "brcm,bcm2711"; +- model = "Raspberry Pi 4 Model B"; +- +- chosen { +- /* 8250 auxiliary UART instead of pl011 */ +- stdout-path = "serial1:115200n8"; +- }; +- +- leds { +- led-act { +- gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; +- }; +- +- led-pwr { +- label = "PWR"; +- gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- linux,default-trigger = "default-on"; +- }; +- }; +- +- wifi_pwrseq: wifi-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; +- }; +- +- sd_io_1v8_reg: sd_io_1v8_reg { +- compatible = "regulator-gpio"; +- regulator-name = "vdd-sd-io"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-settling-time-us = <5000>; +- gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>; +- states = <1800000 0x1>, +- <3300000 0x0>; +- status = "okay"; +- }; +- +- sd_vcc_reg: sd_vcc_reg { +- compatible = "regulator-fixed"; +- regulator-name = "vcc-sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- enable-active-high; +- gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&ddc0 { +- status = "okay"; +-}; +- +-&ddc1 { +- status = "okay"; +-}; +- +-&expgpio { +- gpio-line-names = "BT_ON", +- "WL_ON", +- "PWR_LED_OFF", +- "GLOBAL_RESET", +- "VDD_SD_IO_SEL", +- "CAM_GPIO", +- "SD_PWR_ON", +- ""; +-}; +- +-&gpio { +- /* +- * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and +- * the official GPU firmware DT blob. +- * +- * Legend: +- * "FOO" = GPIO line named "FOO" on the schematic +- * "FOO_N" = GPIO line named "FOO" on schematic, active low +- */ +- gpio-line-names = "ID_SDA", +- "ID_SCL", +- "SDA1", +- "SCL1", +- "GPIO_GCLK", +- "GPIO5", +- "GPIO6", +- "SPI_CE1_N", +- "SPI_CE0_N", +- "SPI_MISO", +- "SPI_MOSI", +- "SPI_SCLK", +- "GPIO12", +- "GPIO13", +- /* Serial port */ +- "TXD1", +- "RXD1", +- "GPIO16", +- "GPIO17", +- "GPIO18", +- "GPIO19", +- "GPIO20", +- "GPIO21", +- "GPIO22", +- "GPIO23", +- "GPIO24", +- "GPIO25", +- "GPIO26", +- "GPIO27", +- "RGMII_MDIO", +- "RGMIO_MDC", +- /* Used by BT module */ +- "CTS0", +- "RTS0", +- "TXD0", +- "RXD0", +- /* Used by Wifi */ +- "SD1_CLK", +- "SD1_CMD", +- "SD1_DATA0", +- "SD1_DATA1", +- "SD1_DATA2", +- "SD1_DATA3", +- /* Shared with SPI flash */ +- "PWM0_MISO", +- "PWM1_MOSI", +- "STATUS_LED_G_CLK", +- "SPIFLASH_CE_N", +- "SDA0", +- "SCL0", +- "RGMII_RXCLK", +- "RGMII_RXCTL", +- "RGMII_RXD0", +- "RGMII_RXD1", +- "RGMII_RXD2", +- "RGMII_RXD3", +- "RGMII_TXCLK", +- "RGMII_TXCTL", +- "RGMII_TXD0", +- "RGMII_TXD1", +- "RGMII_TXD2", +- "RGMII_TXD3"; +-}; +- +-&hdmi0 { +- status = "okay"; +-}; +- +-&hdmi1 { +- status = "okay"; +-}; +- +-&pixelvalve0 { +- status = "okay"; +-}; +- +-&pixelvalve1 { +- status = "okay"; +-}; +- +-&pixelvalve2 { +- status = "okay"; +-}; +- +-&pixelvalve4 { +- status = "okay"; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>; +- status = "okay"; +-}; +- +-/* SDHCI is used to control the SDIO for wireless */ +-&sdhci { +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_gpio34>; +- bus-width = <4>; +- non-removable; +- mmc-pwrseq = <&wifi_pwrseq>; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* EMMC2 is used to drive the SD card */ +-&emmc2 { +- vqmmc-supply = <&sd_io_1v8_reg>; +- vmmc-supply = <&sd_vcc_reg>; +- broken-cd; +- status = "okay"; +-}; +- +-&genet { +- phy-handle = <&phy1>; +- phy-mode = "rgmii-rxid"; +- status = "okay"; +-}; +- +-&genet_mdio { +- phy1: ethernet-phy@1 { +- /* No PHY interrupt */ +- reg = <0x1>; +- }; +-}; +- +-&pcie0 { +- pci@0,0 { +- device_type = "pci"; +- #address-cells = <3>; +- #size-cells = <2>; +- ranges; +- +- reg = <0 0 0 0 0>; +- +- usb@0,0 { +- reg = <0 0 0 0 0>; +- resets = <&reset RASPBERRYPI_FIRMWARE_RESET_ID_USB>; +- }; +- }; +-}; +- +-/* uart0 communicates with the BT module */ +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- max-speed = <2000000>; +- shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-/* uart1 is mapped to the pin header */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_gpio14>; +- status = "okay"; +-}; +- +-&vc4 { +- status = "okay"; +-}; +- +-&vec { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2711-rpi-400.dts b/scripts/dtc/include-prefixes/arm/bcm2711-rpi-400.dts +deleted file mode 100644 +index f4d2fc20397c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2711-rpi-400.dts ++++ /dev/null +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "bcm2711-rpi-4-b.dts" +- +-/ { +- compatible = "raspberrypi,400", "brcm,bcm2711"; +- model = "Raspberry Pi 400"; +- +- chosen { +- /* 8250 auxiliary UART instead of pl011 */ +- stdout-path = "serial1:115200n8"; +- }; +- +- leds { +- /delete-node/ led-act; +- +- led-pwr { +- gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- gpios = <&expgpio 5 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&expgpio { +- gpio-line-names = "BT_ON", +- "WL_ON", +- "", +- "GLOBAL_RESET", +- "VDD_SD_IO_SEL", +- "CAM_GPIO", +- "SD_PWR_ON", +- "SD_OC_N"; +-}; +- +-&genet_mdio { +- clock-frequency = <1950000>; +-}; +- +-&pm { +- /delete-property/ system-power-controller; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2711-rpi.dtsi b/scripts/dtc/include-prefixes/arm/bcm2711-rpi.dtsi +deleted file mode 100644 +index ca266c5d9f9b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2711-rpi.dtsi ++++ /dev/null +@@ -1,74 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "bcm2835-rpi.dtsi" +- +-#include +- +-/ { +- /* Will be filled by the bootloader */ +- memory@0 { +- device_type = "memory"; +- reg = <0 0 0>; +- }; +- +- aliases { +- emmc2bus = &emmc2bus; +- ethernet0 = &genet; +- pcie0 = &pcie0; +- blconfig = &blconfig; +- }; +-}; +- +-&firmware { +- firmware_clocks: clocks { +- compatible = "raspberrypi,firmware-clocks"; +- #clock-cells = <1>; +- }; +- +- expgpio: gpio { +- compatible = "raspberrypi,firmware-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- status = "okay"; +- }; +- +- reset: reset { +- compatible = "raspberrypi,firmware-reset"; +- #reset-cells = <1>; +- }; +-}; +- +-&hdmi0 { +- clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; +- clock-names = "hdmi", "bvb", "audio", "cec"; +- wifi-2.4ghz-coexistence; +-}; +- +-&hdmi1 { +- clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; +- clock-names = "hdmi", "bvb", "audio", "cec"; +- wifi-2.4ghz-coexistence; +-}; +- +-&hvs { +- clocks = <&firmware_clocks 4>; +-}; +- +-&rmem { +- /* +- * RPi4's co-processor will copy the board's bootloader configuration +- * into memory for the OS to consume. It'll also update this node with +- * its placement information. +- */ +- blconfig: nvram@0 { +- compatible = "raspberrypi,bootloader-config", "nvmem-rmem"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x0 0x0 0x0>; +- no-map; +- status = "disabled"; +- }; +-}; +- +-&vchiq { +- interrupts = ; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2711.dtsi b/scripts/dtc/include-prefixes/arm/bcm2711.dtsi +deleted file mode 100644 +index 21294f775a20..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2711.dtsi ++++ /dev/null +@@ -1,1109 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "bcm283x.dtsi" +- +-#include +-#include +- +-/ { +- compatible = "brcm,bcm2711"; +- +- #address-cells = <2>; +- #size-cells = <1>; +- +- interrupt-parent = <&gicv2>; +- +- vc4: gpu { +- compatible = "brcm,bcm2711-vc5"; +- status = "disabled"; +- }; +- +- clk_27MHz: clk-27M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <27000000>; +- clock-output-names = "27MHz-clock"; +- }; +- +- clk_108MHz: clk-108M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <108000000>; +- clock-output-names = "108MHz-clock"; +- }; +- +- soc { +- /* +- * Defined ranges: +- * Common BCM283x peripherals +- * BCM2711-specific peripherals +- * ARM-local peripherals +- */ +- ranges = <0x7e000000 0x0 0xfe000000 0x01800000>, +- <0x7c000000 0x0 0xfc000000 0x02000000>, +- <0x40000000 0x0 0xff800000 0x00800000>; +- /* Emulate a contiguous 30-bit address range for DMA */ +- dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>; +- +- /* +- * This node is the provider for the enable-method for +- * bringing up secondary cores. +- */ +- local_intc: local_intc@40000000 { +- compatible = "brcm,bcm2836-l1-intc"; +- reg = <0x40000000 0x100>; +- }; +- +- gicv2: interrupt-controller@40041000 { +- interrupt-controller; +- #interrupt-cells = <3>; +- compatible = "arm,gic-400"; +- reg = <0x40041000 0x1000>, +- <0x40042000 0x2000>, +- <0x40044000 0x2000>, +- <0x40046000 0x2000>; +- interrupts = ; +- }; +- +- avs_monitor: avs-monitor@7d5d2000 { +- compatible = "brcm,bcm2711-avs-monitor", +- "syscon", "simple-mfd"; +- reg = <0x7d5d2000 0xf00>; +- +- thermal: thermal { +- compatible = "brcm,bcm2711-thermal"; +- #thermal-sensor-cells = <0>; +- }; +- }; +- +- dma: dma@7e007000 { +- compatible = "brcm,bcm2835-dma"; +- reg = <0x7e007000 0xb00>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- /* DMA lite 7 - 10 */ +- , +- , +- , +- ; +- interrupt-names = "dma0", +- "dma1", +- "dma2", +- "dma3", +- "dma4", +- "dma5", +- "dma6", +- "dma7", +- "dma8", +- "dma9", +- "dma10"; +- #dma-cells = <1>; +- brcm,dma-channel-mask = <0x07f5>; +- }; +- +- pm: watchdog@7e100000 { +- compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; +- #power-domain-cells = <1>; +- #reset-cells = <1>; +- reg = <0x7e100000 0x114>, +- <0x7e00a000 0x24>, +- <0x7ec11000 0x20>; +- clocks = <&clocks BCM2835_CLOCK_V3D>, +- <&clocks BCM2835_CLOCK_PERI_IMAGE>, +- <&clocks BCM2835_CLOCK_H264>, +- <&clocks BCM2835_CLOCK_ISP>; +- clock-names = "v3d", "peri_image", "h264", "isp"; +- system-power-controller; +- }; +- +- rng@7e104000 { +- compatible = "brcm,bcm2711-rng200"; +- reg = <0x7e104000 0x28>; +- }; +- +- uart2: serial@7e201400 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x7e201400 0x200>; +- interrupts = ; +- clocks = <&clocks BCM2835_CLOCK_UART>, +- <&clocks BCM2835_CLOCK_VPU>; +- clock-names = "uartclk", "apb_pclk"; +- arm,primecell-periphid = <0x00241011>; +- status = "disabled"; +- }; +- +- uart3: serial@7e201600 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x7e201600 0x200>; +- interrupts = ; +- clocks = <&clocks BCM2835_CLOCK_UART>, +- <&clocks BCM2835_CLOCK_VPU>; +- clock-names = "uartclk", "apb_pclk"; +- arm,primecell-periphid = <0x00241011>; +- status = "disabled"; +- }; +- +- uart4: serial@7e201800 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x7e201800 0x200>; +- interrupts = ; +- clocks = <&clocks BCM2835_CLOCK_UART>, +- <&clocks BCM2835_CLOCK_VPU>; +- clock-names = "uartclk", "apb_pclk"; +- arm,primecell-periphid = <0x00241011>; +- status = "disabled"; +- }; +- +- uart5: serial@7e201a00 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x7e201a00 0x200>; +- interrupts = ; +- clocks = <&clocks BCM2835_CLOCK_UART>, +- <&clocks BCM2835_CLOCK_VPU>; +- clock-names = "uartclk", "apb_pclk"; +- arm,primecell-periphid = <0x00241011>; +- status = "disabled"; +- }; +- +- spi3: spi@7e204600 { +- compatible = "brcm,bcm2835-spi"; +- reg = <0x7e204600 0x0200>; +- interrupts = ; +- clocks = <&clocks BCM2835_CLOCK_VPU>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi4: spi@7e204800 { +- compatible = "brcm,bcm2835-spi"; +- reg = <0x7e204800 0x0200>; +- interrupts = ; +- clocks = <&clocks BCM2835_CLOCK_VPU>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi5: spi@7e204a00 { +- compatible = "brcm,bcm2835-spi"; +- reg = <0x7e204a00 0x0200>; +- interrupts = ; +- clocks = <&clocks BCM2835_CLOCK_VPU>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi6: spi@7e204c00 { +- compatible = "brcm,bcm2835-spi"; +- reg = <0x7e204c00 0x0200>; +- interrupts = ; +- clocks = <&clocks BCM2835_CLOCK_VPU>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@7e205600 { +- compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; +- reg = <0x7e205600 0x200>; +- interrupts = ; +- clocks = <&clocks BCM2835_CLOCK_VPU>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@7e205800 { +- compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; +- reg = <0x7e205800 0x200>; +- interrupts = ; +- clocks = <&clocks BCM2835_CLOCK_VPU>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c5: i2c@7e205a00 { +- compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; +- reg = <0x7e205a00 0x200>; +- interrupts = ; +- clocks = <&clocks BCM2835_CLOCK_VPU>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c6: i2c@7e205c00 { +- compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; +- reg = <0x7e205c00 0x200>; +- interrupts = ; +- clocks = <&clocks BCM2835_CLOCK_VPU>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pixelvalve0: pixelvalve@7e206000 { +- compatible = "brcm,bcm2711-pixelvalve0"; +- reg = <0x7e206000 0x100>; +- interrupts = ; +- status = "disabled"; +- }; +- +- pixelvalve1: pixelvalve@7e207000 { +- compatible = "brcm,bcm2711-pixelvalve1"; +- reg = <0x7e207000 0x100>; +- interrupts = ; +- status = "disabled"; +- }; +- +- pixelvalve2: pixelvalve@7e20a000 { +- compatible = "brcm,bcm2711-pixelvalve2"; +- reg = <0x7e20a000 0x100>; +- interrupts = ; +- status = "disabled"; +- }; +- +- pwm1: pwm@7e20c800 { +- compatible = "brcm,bcm2835-pwm"; +- reg = <0x7e20c800 0x28>; +- clocks = <&clocks BCM2835_CLOCK_PWM>; +- assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; +- assigned-clock-rates = <10000000>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pixelvalve4: pixelvalve@7e216000 { +- compatible = "brcm,bcm2711-pixelvalve4"; +- reg = <0x7e216000 0x100>; +- interrupts = ; +- status = "disabled"; +- }; +- +- hvs: hvs@7e400000 { +- compatible = "brcm,bcm2711-hvs"; +- reg = <0x7e400000 0x8000>; +- interrupts = ; +- }; +- +- pixelvalve3: pixelvalve@7ec12000 { +- compatible = "brcm,bcm2711-pixelvalve3"; +- reg = <0x7ec12000 0x100>; +- interrupts = ; +- status = "disabled"; +- }; +- +- vec: vec@7ec13000 { +- compatible = "brcm,bcm2711-vec"; +- reg = <0x7ec13000 0x1000>; +- clocks = <&clocks BCM2835_CLOCK_VEC>; +- interrupts = ; +- status = "disabled"; +- }; +- +- dvp: clock@7ef00000 { +- compatible = "brcm,brcm2711-dvp"; +- reg = <0x7ef00000 0x10>; +- clocks = <&clk_108MHz>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- aon_intr: interrupt-controller@7ef00100 { +- compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; +- reg = <0x7ef00100 0x30>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- hdmi0: hdmi@7ef00700 { +- compatible = "brcm,bcm2711-hdmi0"; +- reg = <0x7ef00700 0x300>, +- <0x7ef00300 0x200>, +- <0x7ef00f00 0x80>, +- <0x7ef00f80 0x80>, +- <0x7ef01b00 0x200>, +- <0x7ef01f00 0x400>, +- <0x7ef00200 0x80>, +- <0x7ef04300 0x100>, +- <0x7ef20000 0x100>; +- reg-names = "hdmi", +- "dvp", +- "phy", +- "rm", +- "packet", +- "metadata", +- "csc", +- "cec", +- "hd"; +- clock-names = "hdmi", "bvb", "audio", "cec"; +- resets = <&dvp 0>; +- interrupt-parent = <&aon_intr>; +- interrupts = <0>, <1>, <2>, +- <3>, <4>, <5>; +- interrupt-names = "cec-tx", "cec-rx", "cec-low", +- "wakeup", "hpd-connected", "hpd-removed"; +- ddc = <&ddc0>; +- dmas = <&dma 10>; +- dma-names = "audio-rx"; +- status = "disabled"; +- }; +- +- ddc0: i2c@7ef04500 { +- compatible = "brcm,bcm2711-hdmi-i2c"; +- reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>; +- reg-names = "bsc", "auto-i2c"; +- clock-frequency = <97500>; +- status = "disabled"; +- }; +- +- hdmi1: hdmi@7ef05700 { +- compatible = "brcm,bcm2711-hdmi1"; +- reg = <0x7ef05700 0x300>, +- <0x7ef05300 0x200>, +- <0x7ef05f00 0x80>, +- <0x7ef05f80 0x80>, +- <0x7ef06b00 0x200>, +- <0x7ef06f00 0x400>, +- <0x7ef00280 0x80>, +- <0x7ef09300 0x100>, +- <0x7ef20000 0x100>; +- reg-names = "hdmi", +- "dvp", +- "phy", +- "rm", +- "packet", +- "metadata", +- "csc", +- "cec", +- "hd"; +- ddc = <&ddc1>; +- clock-names = "hdmi", "bvb", "audio", "cec"; +- resets = <&dvp 1>; +- interrupt-parent = <&aon_intr>; +- interrupts = <8>, <7>, <6>, +- <9>, <10>, <11>; +- interrupt-names = "cec-tx", "cec-rx", "cec-low", +- "wakeup", "hpd-connected", "hpd-removed"; +- dmas = <&dma 17>; +- dma-names = "audio-rx"; +- status = "disabled"; +- }; +- +- ddc1: i2c@7ef09500 { +- compatible = "brcm,bcm2711-hdmi-i2c"; +- reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>; +- reg-names = "bsc", "auto-i2c"; +- clock-frequency = <97500>; +- status = "disabled"; +- }; +- }; +- +- /* +- * emmc2 has different DMA constraints based on SoC revisions. It was +- * moved into its own bus, so as for RPi4's firmware to update them. +- * The firmware will find whether the emmc2bus alias is defined, and if +- * so, it'll edit the dma-ranges property below accordingly. +- */ +- emmc2bus: emmc2bus { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- +- ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; +- dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>; +- +- emmc2: mmc@7e340000 { +- compatible = "brcm,bcm2711-emmc2"; +- reg = <0x0 0x7e340000 0x100>; +- interrupts = ; +- clocks = <&clocks BCM2711_CLOCK_EMMC2>; +- status = "disabled"; +- }; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- /* This only applies to the ARMv7 stub */ +- arm,cpu-registers-not-fw-configured; +- }; +- +- cpus: cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x000000d8>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <1>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x000000e0>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <2>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x000000e8>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <3>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x000000f0>; +- }; +- }; +- +- scb { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- +- ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, +- <0x6 0x00000000 0x6 0x00000000 0x40000000>; +- +- pcie0: pcie@7d500000 { +- compatible = "brcm,bcm2711-pcie"; +- reg = <0x0 0x7d500000 0x9310>; +- device_type = "pci"; +- #address-cells = <3>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- interrupts = , +- ; +- interrupt-names = "pcie", "msi"; +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 +- IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 2 &gicv2 GIC_SPI 144 +- IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 3 &gicv2 GIC_SPI 145 +- IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 4 &gicv2 GIC_SPI 146 +- IRQ_TYPE_LEVEL_HIGH>; +- msi-controller; +- msi-parent = <&pcie0>; +- +- ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 +- 0x0 0x04000000>; +- /* +- * The wrapper around the PCIe block has a bug +- * preventing it from accessing beyond the first 3GB of +- * memory. +- */ +- dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 +- 0x0 0xc0000000>; +- brcm,enable-ssc; +- }; +- +- genet: ethernet@7d580000 { +- compatible = "brcm,bcm2711-genet-v5"; +- reg = <0x0 0x7d580000 0x10000>; +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- interrupts = , +- ; +- status = "disabled"; +- +- genet_mdio: mdio@e14 { +- compatible = "brcm,genet-mdio-v5"; +- reg = <0xe14 0x8>; +- reg-names = "mdio"; +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- }; +- }; +- }; +-}; +- +-&clk_osc { +- clock-frequency = <54000000>; +-}; +- +-&clocks { +- compatible = "brcm,bcm2711-cprman"; +-}; +- +-&cpu_thermal { +- coefficients = <(-487) 410040>; +- thermal-sensors = <&thermal>; +-}; +- +-&dsi0 { +- interrupts = ; +-}; +- +-&dsi1 { +- interrupts = ; +- compatible = "brcm,bcm2711-dsi1"; +-}; +- +-&gpio { +- compatible = "brcm,bcm2711-gpio"; +- interrupts = , +- , +- , +- ; +- +- gpio-ranges = <&gpio 0 0 58>; +- +- gpclk0_gpio49: gpclk0_gpio49 { +- pin-gpclk { +- pins = "gpio49"; +- function = "alt1"; +- bias-disable; +- }; +- }; +- gpclk1_gpio50: gpclk1_gpio50 { +- pin-gpclk { +- pins = "gpio50"; +- function = "alt1"; +- bias-disable; +- }; +- }; +- gpclk2_gpio51: gpclk2_gpio51 { +- pin-gpclk { +- pins = "gpio51"; +- function = "alt1"; +- bias-disable; +- }; +- }; +- +- i2c0_gpio46: i2c0_gpio46 { +- pin-sda { +- function = "alt0"; +- pins = "gpio46"; +- bias-pull-up; +- }; +- pin-scl { +- function = "alt0"; +- pins = "gpio47"; +- bias-disable; +- }; +- }; +- i2c1_gpio46: i2c1_gpio46 { +- pin-sda { +- function = "alt1"; +- pins = "gpio46"; +- bias-pull-up; +- }; +- pin-scl { +- function = "alt1"; +- pins = "gpio47"; +- bias-disable; +- }; +- }; +- i2c3_gpio2: i2c3_gpio2 { +- pin-sda { +- function = "alt5"; +- pins = "gpio2"; +- bias-pull-up; +- }; +- pin-scl { +- function = "alt5"; +- pins = "gpio3"; +- bias-disable; +- }; +- }; +- i2c3_gpio4: i2c3_gpio4 { +- pin-sda { +- function = "alt5"; +- pins = "gpio4"; +- bias-pull-up; +- }; +- pin-scl { +- function = "alt5"; +- pins = "gpio5"; +- bias-disable; +- }; +- }; +- i2c4_gpio6: i2c4_gpio6 { +- pin-sda { +- function = "alt5"; +- pins = "gpio6"; +- bias-pull-up; +- }; +- pin-scl { +- function = "alt5"; +- pins = "gpio7"; +- bias-disable; +- }; +- }; +- i2c4_gpio8: i2c4_gpio8 { +- pin-sda { +- function = "alt5"; +- pins = "gpio8"; +- bias-pull-up; +- }; +- pin-scl { +- function = "alt5"; +- pins = "gpio9"; +- bias-disable; +- }; +- }; +- i2c5_gpio10: i2c5_gpio10 { +- pin-sda { +- function = "alt5"; +- pins = "gpio10"; +- bias-pull-up; +- }; +- pin-scl { +- function = "alt5"; +- pins = "gpio11"; +- bias-disable; +- }; +- }; +- i2c5_gpio12: i2c5_gpio12 { +- pin-sda { +- function = "alt5"; +- pins = "gpio12"; +- bias-pull-up; +- }; +- pin-scl { +- function = "alt5"; +- pins = "gpio13"; +- bias-disable; +- }; +- }; +- i2c6_gpio0: i2c6_gpio0 { +- pin-sda { +- function = "alt5"; +- pins = "gpio0"; +- bias-pull-up; +- }; +- pin-scl { +- function = "alt5"; +- pins = "gpio1"; +- bias-disable; +- }; +- }; +- i2c6_gpio22: i2c6_gpio22 { +- pin-sda { +- function = "alt5"; +- pins = "gpio22"; +- bias-pull-up; +- }; +- pin-scl { +- function = "alt5"; +- pins = "gpio23"; +- bias-disable; +- }; +- }; +- i2c_slave_gpio8: i2c_slave_gpio8 { +- pins-i2c-slave { +- pins = "gpio8", +- "gpio9", +- "gpio10", +- "gpio11"; +- function = "alt3"; +- }; +- }; +- +- jtag_gpio48: jtag_gpio48 { +- pins-jtag { +- pins = "gpio48", +- "gpio49", +- "gpio50", +- "gpio51", +- "gpio52", +- "gpio53"; +- function = "alt4"; +- }; +- }; +- +- mii_gpio28: mii_gpio28 { +- pins-mii { +- pins = "gpio28", +- "gpio29", +- "gpio30", +- "gpio31"; +- function = "alt4"; +- }; +- }; +- mii_gpio36: mii_gpio36 { +- pins-mii { +- pins = "gpio36", +- "gpio37", +- "gpio38", +- "gpio39"; +- function = "alt5"; +- }; +- }; +- +- pcm_gpio50: pcm_gpio50 { +- pins-pcm { +- pins = "gpio50", +- "gpio51", +- "gpio52", +- "gpio53"; +- function = "alt2"; +- }; +- }; +- +- pwm0_0_gpio12: pwm0_0_gpio12 { +- pin-pwm { +- pins = "gpio12"; +- function = "alt0"; +- bias-disable; +- }; +- }; +- pwm0_0_gpio18: pwm0_0_gpio18 { +- pin-pwm { +- pins = "gpio18"; +- function = "alt5"; +- bias-disable; +- }; +- }; +- pwm1_0_gpio40: pwm1_0_gpio40 { +- pin-pwm { +- pins = "gpio40"; +- function = "alt0"; +- bias-disable; +- }; +- }; +- pwm0_1_gpio13: pwm0_1_gpio13 { +- pin-pwm { +- pins = "gpio13"; +- function = "alt0"; +- bias-disable; +- }; +- }; +- pwm0_1_gpio19: pwm0_1_gpio19 { +- pin-pwm { +- pins = "gpio19"; +- function = "alt5"; +- bias-disable; +- }; +- }; +- pwm1_1_gpio41: pwm1_1_gpio41 { +- pin-pwm { +- pins = "gpio41"; +- function = "alt0"; +- bias-disable; +- }; +- }; +- pwm0_1_gpio45: pwm0_1_gpio45 { +- pin-pwm { +- pins = "gpio45"; +- function = "alt0"; +- bias-disable; +- }; +- }; +- pwm0_0_gpio52: pwm0_0_gpio52 { +- pin-pwm { +- pins = "gpio52"; +- function = "alt1"; +- bias-disable; +- }; +- }; +- pwm0_1_gpio53: pwm0_1_gpio53 { +- pin-pwm { +- pins = "gpio53"; +- function = "alt1"; +- bias-disable; +- }; +- }; +- +- rgmii_gpio35: rgmii_gpio35 { +- pin-start-stop { +- pins = "gpio35"; +- function = "alt4"; +- }; +- pin-rx-ok { +- pins = "gpio36"; +- function = "alt4"; +- }; +- }; +- rgmii_irq_gpio34: rgmii_irq_gpio34 { +- pin-irq { +- pins = "gpio34"; +- function = "alt5"; +- }; +- }; +- rgmii_irq_gpio39: rgmii_irq_gpio39 { +- pin-irq { +- pins = "gpio39"; +- function = "alt4"; +- }; +- }; +- rgmii_mdio_gpio28: rgmii_mdio_gpio28 { +- pins-mdio { +- pins = "gpio28", +- "gpio29"; +- function = "alt5"; +- }; +- }; +- rgmii_mdio_gpio37: rgmii_mdio_gpio37 { +- pins-mdio { +- pins = "gpio37", +- "gpio38"; +- function = "alt4"; +- }; +- }; +- +- spi0_gpio46: spi0_gpio46 { +- pins-spi { +- pins = "gpio46", +- "gpio47", +- "gpio48", +- "gpio49"; +- function = "alt2"; +- }; +- }; +- spi2_gpio46: spi2_gpio46 { +- pins-spi { +- pins = "gpio46", +- "gpio47", +- "gpio48", +- "gpio49", +- "gpio50"; +- function = "alt5"; +- }; +- }; +- spi3_gpio0: spi3_gpio0 { +- pins-spi { +- pins = "gpio0", +- "gpio1", +- "gpio2", +- "gpio3"; +- function = "alt3"; +- }; +- }; +- spi4_gpio4: spi4_gpio4 { +- pins-spi { +- pins = "gpio4", +- "gpio5", +- "gpio6", +- "gpio7"; +- function = "alt3"; +- }; +- }; +- spi5_gpio12: spi5_gpio12 { +- pins-spi { +- pins = "gpio12", +- "gpio13", +- "gpio14", +- "gpio15"; +- function = "alt3"; +- }; +- }; +- spi6_gpio18: spi6_gpio18 { +- pins-spi { +- pins = "gpio18", +- "gpio19", +- "gpio20", +- "gpio21"; +- function = "alt3"; +- }; +- }; +- +- uart2_gpio0: uart2_gpio0 { +- pin-tx { +- pins = "gpio0"; +- function = "alt4"; +- bias-disable; +- }; +- pin-rx { +- pins = "gpio1"; +- function = "alt4"; +- bias-pull-up; +- }; +- }; +- uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 { +- pin-cts { +- pins = "gpio2"; +- function = "alt4"; +- bias-pull-up; +- }; +- pin-rts { +- pins = "gpio3"; +- function = "alt4"; +- bias-disable; +- }; +- }; +- uart3_gpio4: uart3_gpio4 { +- pin-tx { +- pins = "gpio4"; +- function = "alt4"; +- bias-disable; +- }; +- pin-rx { +- pins = "gpio5"; +- function = "alt4"; +- bias-pull-up; +- }; +- }; +- uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 { +- pin-cts { +- pins = "gpio6"; +- function = "alt4"; +- bias-pull-up; +- }; +- pin-rts { +- pins = "gpio7"; +- function = "alt4"; +- bias-disable; +- }; +- }; +- uart4_gpio8: uart4_gpio8 { +- pin-tx { +- pins = "gpio8"; +- function = "alt4"; +- bias-disable; +- }; +- pin-rx { +- pins = "gpio9"; +- function = "alt4"; +- bias-pull-up; +- }; +- }; +- uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 { +- pin-cts { +- pins = "gpio10"; +- function = "alt4"; +- bias-pull-up; +- }; +- pin-rts { +- pins = "gpio11"; +- function = "alt4"; +- bias-disable; +- }; +- }; +- uart5_gpio12: uart5_gpio12 { +- pin-tx { +- pins = "gpio12"; +- function = "alt4"; +- bias-disable; +- }; +- pin-rx { +- pins = "gpio13"; +- function = "alt4"; +- bias-pull-up; +- }; +- }; +- uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 { +- pin-cts { +- pins = "gpio14"; +- function = "alt4"; +- bias-pull-up; +- }; +- pin-rts { +- pins = "gpio15"; +- function = "alt4"; +- bias-disable; +- }; +- }; +-}; +- +-&rmem { +- #address-cells = <2>; +-}; +- +-&cma { +- /* +- * arm64 reserves the CMA by default somewhere in ZONE_DMA32, +- * that's not good enough for the BCM2711 as some devices can +- * only address the lower 1G of memory (ZONE_DMA). +- */ +- alloc-ranges = <0x0 0x00000000 0x40000000>; +-}; +- +-&i2c0 { +- compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; +- interrupts = ; +-}; +- +-&i2c1 { +- compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; +- interrupts = ; +-}; +- +-&mailbox { +- interrupts = ; +-}; +- +-&sdhci { +- interrupts = ; +-}; +- +-&sdhost { +- interrupts = ; +-}; +- +-&spi { +- interrupts = ; +-}; +- +-&spi1 { +- interrupts = ; +-}; +- +-&spi2 { +- interrupts = ; +-}; +- +-&system_timer { +- interrupts = , +- , +- , +- ; +-}; +- +-&txp { +- interrupts = ; +-}; +- +-&uart0 { +- interrupts = ; +-}; +- +-&uart1 { +- interrupts = ; +-}; +- +-&usb { +- interrupts = ; +-}; +- +-&vec { +- compatible = "brcm,bcm2711-vec"; +- interrupts = ; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm28155-ap.dts b/scripts/dtc/include-prefixes/arm/bcm28155-ap.dts +deleted file mode 100644 +index ead6e9804dbf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm28155-ap.dts ++++ /dev/null +@@ -1,122 +0,0 @@ +-/* +- * Copyright (C) 2013 Broadcom Corporation +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation version 2. +- * +- * This program is distributed "as is" WITHOUT ANY WARRANTY of any +- * kind, whether express or implied; without even the implied warranty +- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-/dts-v1/; +- +-#include +- +-#include "bcm11351.dtsi" +- +-/ { +- model = "BCM28155 AP board"; +- compatible = "brcm,bcm28155-ap", "brcm,bcm11351"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; /* 1 GB */ +- }; +- +- uart@3e000000 { +- status = "okay"; +- }; +- +- i2c@3e016000 { +- status="okay"; +- clock-frequency = <400000>; +- }; +- +- i2c@3e017000 { +- status="okay"; +- clock-frequency = <400000>; +- }; +- +- i2c@3e018000 { +- status="okay"; +- clock-frequency = <400000>; +- }; +- +- i2c@3500d000 { +- status="okay"; +- clock-frequency = <100000>; +- +- pmu: pmu@8 { +- reg = <0x08>; +- }; +- }; +- +- sdio2: sdio@3f190000 { +- non-removable; +- max-frequency = <48000000>; +- vmmc-supply = <&camldo1_reg>; +- vqmmc-supply = <&iosr1_reg>; +- status = "okay"; +- }; +- +- sdio4: sdio@3f1b0000 { +- max-frequency = <48000000>; +- cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>; +- vmmc-supply = <&sdldo_reg>; +- vqmmc-supply = <&sdxldo_reg>; +- status = "okay"; +- }; +- +- pwm: pwm@3e01a000 { +- status = "okay"; +- }; +- +- usbotg: usb@3f120000 { +- vusb_d-supply = <&usbldo_reg>; +- vusb_a-supply = <&iosr1_reg>; +- status = "okay"; +- }; +- +- usbphy: usb-phy@3f130000 { +- status = "okay"; +- }; +-}; +- +-#include "bcm59056.dtsi" +- +-&pmu { +- compatible = "brcm,bcm59056"; +- interrupts = ; +- regulators { +- camldo1_reg: camldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- sdldo_reg: sdldo { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- sdxldo_reg: sdxldo { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- usbldo_reg: usbldo { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- iosr1_reg: iosr1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2835-common.dtsi b/scripts/dtc/include-prefixes/arm/bcm2835-common.dtsi +deleted file mode 100644 +index c25e797b9060..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2835-common.dtsi ++++ /dev/null +@@ -1,207 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/* This include file covers the common peripherals and configuration between +- * bcm2835, bcm2836 and bcm2837 implementations. +- */ +- +-/ { +- interrupt-parent = <&intc>; +- +- soc { +- dma: dma@7e007000 { +- compatible = "brcm,bcm2835-dma"; +- reg = <0x7e007000 0xf00>; +- interrupts = <1 16>, +- <1 17>, +- <1 18>, +- <1 19>, +- <1 20>, +- <1 21>, +- <1 22>, +- <1 23>, +- <1 24>, +- <1 25>, +- <1 26>, +- /* dma channel 11-14 share one irq */ +- <1 27>, +- <1 27>, +- <1 27>, +- <1 27>, +- /* unused shared irq for all channels */ +- <1 28>; +- interrupt-names = "dma0", +- "dma1", +- "dma2", +- "dma3", +- "dma4", +- "dma5", +- "dma6", +- "dma7", +- "dma8", +- "dma9", +- "dma10", +- "dma11", +- "dma12", +- "dma13", +- "dma14", +- "dma-shared-all"; +- #dma-cells = <1>; +- brcm,dma-channel-mask = <0x7f35>; +- }; +- +- intc: interrupt-controller@7e00b200 { +- compatible = "brcm,bcm2835-armctrl-ic"; +- reg = <0x7e00b200 0x200>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pm: watchdog@7e100000 { +- compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; +- #power-domain-cells = <1>; +- #reset-cells = <1>; +- reg = <0x7e100000 0x114>, +- <0x7e00a000 0x24>; +- clocks = <&clocks BCM2835_CLOCK_V3D>, +- <&clocks BCM2835_CLOCK_PERI_IMAGE>, +- <&clocks BCM2835_CLOCK_H264>, +- <&clocks BCM2835_CLOCK_ISP>; +- clock-names = "v3d", "peri_image", "h264", "isp"; +- system-power-controller; +- }; +- +- rng@7e104000 { +- compatible = "brcm,bcm2835-rng"; +- reg = <0x7e104000 0x10>; +- interrupts = <2 29>; +- }; +- +- pixelvalve@7e206000 { +- compatible = "brcm,bcm2835-pixelvalve0"; +- reg = <0x7e206000 0x100>; +- interrupts = <2 13>; /* pwa0 */ +- }; +- +- pixelvalve@7e207000 { +- compatible = "brcm,bcm2835-pixelvalve1"; +- reg = <0x7e207000 0x100>; +- interrupts = <2 14>; /* pwa1 */ +- }; +- +- thermal: thermal@7e212000 { +- compatible = "brcm,bcm2835-thermal"; +- reg = <0x7e212000 0x8>; +- clocks = <&clocks BCM2835_CLOCK_TSENS>; +- #thermal-sensor-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@7e805000 { +- compatible = "brcm,bcm2835-i2c"; +- reg = <0x7e805000 0x1000>; +- interrupts = <2 21>; +- clocks = <&clocks BCM2835_CLOCK_VPU>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- }; +- +- vec: vec@7e806000 { +- compatible = "brcm,bcm2835-vec"; +- reg = <0x7e806000 0x1000>; +- clocks = <&clocks BCM2835_CLOCK_VEC>; +- interrupts = <2 27>; +- status = "disabled"; +- }; +- +- pixelvalve@7e807000 { +- compatible = "brcm,bcm2835-pixelvalve2"; +- reg = <0x7e807000 0x100>; +- interrupts = <2 10>; /* pixelvalve */ +- }; +- +- hdmi: hdmi@7e902000 { +- compatible = "brcm,bcm2835-hdmi"; +- reg = <0x7e902000 0x600>, +- <0x7e808000 0x100>; +- interrupts = <2 8>, <2 9>; +- ddc = <&i2c2>; +- clocks = <&clocks BCM2835_PLLH_PIX>, +- <&clocks BCM2835_CLOCK_HSM>; +- clock-names = "pixel", "hdmi"; +- dmas = <&dma 17>; +- dma-names = "audio-rx"; +- status = "disabled"; +- }; +- +- v3d: v3d@7ec00000 { +- compatible = "brcm,bcm2835-v3d"; +- reg = <0x7ec00000 0x1000>; +- interrupts = <1 10>; +- }; +- +- vc4: gpu { +- compatible = "brcm,bcm2835-vc4"; +- }; +- }; +-}; +- +-&cpu_thermal { +- thermal-sensors = <&thermal>; +-}; +- +-&gpio { +- i2c_slave_gpio18: i2c_slave_gpio18 { +- brcm,pins = <18 19 20 21>; +- brcm,function = ; +- }; +- +- jtag_gpio4: jtag_gpio4 { +- brcm,pins = <4 5 6 12 13>; +- brcm,function = ; +- }; +- +- pwm0_gpio12: pwm0_gpio12 { +- brcm,pins = <12>; +- brcm,function = ; +- }; +- pwm0_gpio18: pwm0_gpio18 { +- brcm,pins = <18>; +- brcm,function = ; +- }; +- pwm0_gpio40: pwm0_gpio40 { +- brcm,pins = <40>; +- brcm,function = ; +- }; +- pwm1_gpio13: pwm1_gpio13 { +- brcm,pins = <13>; +- brcm,function = ; +- }; +- pwm1_gpio19: pwm1_gpio19 { +- brcm,pins = <19>; +- brcm,function = ; +- }; +- pwm1_gpio41: pwm1_gpio41 { +- brcm,pins = <41>; +- brcm,function = ; +- }; +- pwm1_gpio45: pwm1_gpio45 { +- brcm,pins = <45>; +- brcm,function = ; +- }; +-}; +- +-&i2s { +- dmas = <&dma 2>, <&dma 3>; +- dma-names = "tx", "rx"; +-}; +- +-&sdhost { +- dmas = <&dma 13>; +- dma-names = "rx-tx"; +-}; +- +-&spi { +- dmas = <&dma 6>, <&dma 7>; +- dma-names = "tx", "rx"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-a-plus.dts b/scripts/dtc/include-prefixes/arm/bcm2835-rpi-a-plus.dts +deleted file mode 100644 +index 40b9405f1a8e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-a-plus.dts ++++ /dev/null +@@ -1,128 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "bcm2835.dtsi" +-#include "bcm2835-rpi.dtsi" +-#include "bcm283x-rpi-usb-host.dtsi" +- +-/ { +- compatible = "raspberrypi,model-a-plus", "brcm,bcm2835"; +- model = "Raspberry Pi Model A+"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0x10000000>; +- }; +- +- leds { +- led-act { +- gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; +- }; +- +- led-pwr { +- label = "PWR"; +- gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; +- linux,default-trigger = "default-on"; +- }; +- }; +-}; +- +-&gpio { +- /* +- * This is based on the unreleased schematic for the Model A+. +- * +- * Legend: +- * "NC" = not connected (no rail from the SoC) +- * "FOO" = GPIO line named "FOO" on the schematic +- * "FOO_N" = GPIO line named "FOO" on schematic, active low +- */ +- gpio-line-names = "ID_SDA", +- "ID_SCL", +- "SDA1", +- "SCL1", +- "GPIO_GCLK", +- "GPIO5", +- "GPIO6", +- "SPI_CE1_N", +- "SPI_CE0_N", +- "SPI_MISO", +- "SPI_MOSI", +- "SPI_SCLK", +- "GPIO12", +- "GPIO13", +- /* Serial port */ +- "TXD0", +- "RXD0", +- "GPIO16", +- "GPIO17", +- "GPIO18", +- "GPIO19", +- "GPIO20", +- "GPIO21", +- "GPIO22", +- "GPIO23", +- "GPIO24", +- "GPIO25", +- "GPIO26", +- "GPIO27", +- "SDA0", +- "SCL0", +- "NC", /* GPIO30 */ +- "NC", /* GPIO31 */ +- "CAM_GPIO1", /* GPIO32 */ +- "NC", /* GPIO33 */ +- "NC", /* GPIO34 */ +- "PWR_LOW_N", /* GPIO35 */ +- "NC", /* GPIO36 */ +- "NC", /* GPIO37 */ +- "USB_LIMIT", /* GPIO38 */ +- "NC", /* GPIO39 */ +- "PWM0_OUT", /* GPIO40 */ +- "CAM_GPIO0", /* GPIO41 */ +- "NC", /* GPIO42 */ +- "NC", /* GPIO43 */ +- "NC", /* GPIO44 */ +- "PWM1_OUT", /* GPIO45 */ +- "HDMI_HPD_N", +- "STATUS_LED", +- /* Used by SD Card */ +- "SD_CLK_R", +- "SD_CMD_R", +- "SD_DATA0_R", +- "SD_DATA1_R", +- "SD_DATA2_R", +- "SD_DATA3_R"; +- +- pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; +- +- /* I2S interface */ +- i2s_alt0: i2s_alt0 { +- brcm,pins = <18 19 20 21>; +- brcm,function = ; +- }; +-}; +- +-&hdmi { +- hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +- power-domains = <&power RPI_POWER_DOMAIN_HDMI>; +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; +- status = "okay"; +-}; +- +-&sdhost { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhost_gpio48>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_gpio14>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-a.dts b/scripts/dtc/include-prefixes/arm/bcm2835-rpi-a.dts +deleted file mode 100644 +index 11edb581dbaf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-a.dts ++++ /dev/null +@@ -1,123 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "bcm2835.dtsi" +-#include "bcm2835-rpi.dtsi" +-#include "bcm283x-rpi-usb-host.dtsi" +- +-/ { +- compatible = "raspberrypi,model-a", "brcm,bcm2835"; +- model = "Raspberry Pi Model A"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0x10000000>; +- }; +- +- leds { +- led-act { +- gpios = <&gpio 16 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&gpio { +- /* +- * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf +- * RPI00021 sheet 02 +- * +- * Legend: +- * "NC" = not connected (no rail from the SoC) +- * "FOO" = GPIO line named "FOO" on the schematic +- * "FOO_N" = GPIO line named "FOO" on schematic, active low +- */ +- gpio-line-names = "SDA0", +- "SCL0", +- "SDA1", +- "SCL1", +- "GPIO_GCLK", +- "CAM_GPIO1", +- "LAN_RUN", +- "SPI_CE1_N", +- "SPI_CE0_N", +- "SPI_MISO", +- "SPI_MOSI", +- "SPI_SCLK", +- "NC", /* GPIO12 */ +- "NC", /* GPIO13 */ +- /* Serial port */ +- "TXD0", +- "RXD0", +- "STATUS_LED_N", +- "GPIO17", +- "GPIO18", +- "NC", /* GPIO19 */ +- "NC", /* GPIO20 */ +- "GPIO21", +- "GPIO22", +- "GPIO23", +- "GPIO24", +- "GPIO25", +- "NC", /* GPIO26 */ +- "CAM_GPIO0", +- /* Binary number representing build/revision */ +- "CONFIG0", +- "CONFIG1", +- "CONFIG2", +- "CONFIG3", +- "NC", /* GPIO32 */ +- "NC", /* GPIO33 */ +- "NC", /* GPIO34 */ +- "NC", /* GPIO35 */ +- "NC", /* GPIO36 */ +- "NC", /* GPIO37 */ +- "NC", /* GPIO38 */ +- "NC", /* GPIO39 */ +- "PWM0_OUT", +- "NC", /* GPIO41 */ +- "NC", /* GPIO42 */ +- "NC", /* GPIO43 */ +- "NC", /* GPIO44 */ +- "PWM1_OUT", +- "HDMI_HPD_P", +- "SD_CARD_DET", +- /* Used by SD Card */ +- "SD_CLK_R", +- "SD_CMD_R", +- "SD_DATA0_R", +- "SD_DATA1_R", +- "SD_DATA2_R", +- "SD_DATA3_R"; +- +- pinctrl-0 = <&gpioout &alt0 &i2s_alt2>; +- +- /* I2S interface */ +- i2s_alt2: i2s_alt2 { +- brcm,pins = <28 29 30 31>; +- brcm,function = ; +- }; +-}; +- +-&hdmi { +- hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; +- power-domains = <&power RPI_POWER_DOMAIN_HDMI>; +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; +- status = "okay"; +-}; +- +-&sdhost { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhost_gpio48>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_gpio14>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-b-plus.dts b/scripts/dtc/include-prefixes/arm/bcm2835-rpi-b-plus.dts +deleted file mode 100644 +index 1b435c64bd9c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-b-plus.dts ++++ /dev/null +@@ -1,130 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "bcm2835.dtsi" +-#include "bcm2835-rpi.dtsi" +-#include "bcm283x-rpi-smsc9514.dtsi" +-#include "bcm283x-rpi-usb-host.dtsi" +- +-/ { +- compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; +- model = "Raspberry Pi Model B+"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0x20000000>; +- }; +- +- leds { +- led-act { +- gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; +- }; +- +- led-pwr { +- label = "PWR"; +- gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; +- linux,default-trigger = "default-on"; +- }; +- }; +-}; +- +-&gpio { +- /* +- * Taken from Raspberry-Pi-B-Plus-V1.2-Schematics.pdf +- * RPI-BPLUS sheet 1 +- * +- * Legend: +- * "NC" = not connected (no rail from the SoC) +- * "FOO" = GPIO line named "FOO" on the schematic +- * "FOO_N" = GPIO line named "FOO" on schematic, active low +- */ +- gpio-line-names = "ID_SDA", +- "ID_SCL", +- "SDA1", +- "SCL1", +- "GPIO_GCLK", +- "GPIO5", +- "GPIO6", +- "SPI_CE1_N", +- "SPI_CE0_N", +- "SPI_MISO", +- "SPI_MOSI", +- "SPI_SCLK", +- "GPIO12", +- "GPIO13", +- /* Serial port */ +- "TXD0", +- "RXD0", +- "GPIO16", +- "GPIO17", +- "GPIO18", +- "GPIO19", +- "GPIO20", +- "GPIO21", +- "GPIO22", +- "GPIO23", +- "GPIO24", +- "GPIO25", +- "GPIO26", +- "GPIO27", +- "SDA0", +- "SCL0", +- "NC", /* GPIO30 */ +- "LAN_RUN", /* GPIO31 */ +- "CAM_GPIO1", /* GPIO32 */ +- "NC", /* GPIO33 */ +- "NC", /* GPIO34 */ +- "PWR_LOW_N", /* GPIO35 */ +- "NC", /* GPIO36 */ +- "NC", /* GPIO37 */ +- "USB_LIMIT", /* GPIO38 */ +- "NC", /* GPIO39 */ +- "PWM0_OUT", /* GPIO40 */ +- "CAM_GPIO0", /* GPIO41 */ +- "NC", /* GPIO42 */ +- "NC", /* GPIO43 */ +- "ETHCLK", /* GPIO44 */ +- "PWM1_OUT", /* GPIO45 */ +- "HDMI_HPD_N", +- "STATUS_LED", +- /* Used by SD Card */ +- "SD_CLK_R", +- "SD_CMD_R", +- "SD_DATA0_R", +- "SD_DATA1_R", +- "SD_DATA2_R", +- "SD_DATA3_R"; +- +- pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; +- +- /* I2S interface */ +- i2s_alt0: i2s_alt0 { +- brcm,pins = <18 19 20 21>; +- brcm,function = ; +- }; +-}; +- +-&hdmi { +- hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +- power-domains = <&power RPI_POWER_DOMAIN_HDMI>; +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; +- status = "okay"; +-}; +- +-&sdhost { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhost_gpio48>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_gpio14>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-b-rev2.dts b/scripts/dtc/include-prefixes/arm/bcm2835-rpi-b-rev2.dts +deleted file mode 100644 +index a23c25c00eea..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-b-rev2.dts ++++ /dev/null +@@ -1,123 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "bcm2835.dtsi" +-#include "bcm2835-rpi.dtsi" +-#include "bcm283x-rpi-smsc9512.dtsi" +-#include "bcm283x-rpi-usb-host.dtsi" +- +-/ { +- compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835"; +- model = "Raspberry Pi Model B rev2"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0x10000000>; +- }; +- +- leds { +- led-act { +- gpios = <&gpio 16 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&gpio { +- /* +- * Taken from Raspberry-Pi-Rev-2.0-Model-AB-Schematics.pdf +- * RPI00022 sheet 02 +- * +- * Legend: +- * "NC" = not connected (no rail from the SoC) +- * "FOO" = GPIO line named "FOO" on the schematic +- * "FOO_N" = GPIO line named "FOO" on schematic, active low +- */ +- gpio-line-names = "SDA0", +- "SCL0", +- "SDA1", +- "SCL1", +- "GPIO_GCLK", +- "CAM_CLK", +- "LAN_RUN", +- "SPI_CE1_N", +- "SPI_CE0_N", +- "SPI_MISO", +- "SPI_MOSI", +- "SPI_SCLK", +- "NC", /* GPIO12 */ +- "NC", /* GPIO13 */ +- /* Serial port */ +- "TXD0", +- "RXD0", +- "STATUS_LED_N", +- "GPIO17", +- "GPIO18", +- "NC", /* GPIO19 */ +- "NC", /* GPIO20 */ +- "CAM_GPIO", +- "GPIO22", +- "GPIO23", +- "GPIO24", +- "GPIO25", +- "NC", /* GPIO26 */ +- "GPIO27", +- "GPIO28", +- "GPIO29", +- "GPIO30", +- "GPIO31", +- "NC", /* GPIO32 */ +- "NC", /* GPIO33 */ +- "NC", /* GPIO34 */ +- "NC", /* GPIO35 */ +- "NC", /* GPIO36 */ +- "NC", /* GPIO37 */ +- "NC", /* GPIO38 */ +- "NC", /* GPIO39 */ +- "PWM0_OUT", +- "NC", /* GPIO41 */ +- "NC", /* GPIO42 */ +- "NC", /* GPIO43 */ +- "NC", /* GPIO44 */ +- "PWM1_OUT", +- "HDMI_HPD_P", +- "SD_CARD_DET", +- /* Used by SD Card */ +- "SD_CLK_R", +- "SD_CMD_R", +- "SD_DATA0_R", +- "SD_DATA1_R", +- "SD_DATA2_R", +- "SD_DATA3_R"; +- +- pinctrl-0 = <&gpioout &alt0 &i2s_alt2>; +- +- /* I2S interface */ +- i2s_alt2: i2s_alt2 { +- brcm,pins = <28 29 30 31>; +- brcm,function = ; +- }; +-}; +- +-&hdmi { +- hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; +- power-domains = <&power RPI_POWER_DOMAIN_HDMI>; +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; +- status = "okay"; +-}; +- +-&sdhost { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhost_gpio48>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_gpio14>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-b.dts b/scripts/dtc/include-prefixes/arm/bcm2835-rpi-b.dts +deleted file mode 100644 +index 1b63d6b19750..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-b.dts ++++ /dev/null +@@ -1,118 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "bcm2835.dtsi" +-#include "bcm2835-rpi.dtsi" +-#include "bcm283x-rpi-smsc9512.dtsi" +-#include "bcm283x-rpi-usb-host.dtsi" +- +-/ { +- compatible = "raspberrypi,model-b", "brcm,bcm2835"; +- model = "Raspberry Pi Model B"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0x10000000>; +- }; +- +- leds { +- led-act { +- gpios = <&gpio 16 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&gpio { +- /* +- * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf +- * RPI00021 sheet 02 +- * +- * Legend: +- * "NC" = not connected (no rail from the SoC) +- * "FOO" = GPIO line named "FOO" on the schematic +- * "FOO_N" = GPIO line named "FOO" on schematic, active low +- */ +- gpio-line-names = "SDA0", +- "SCL0", +- "SDA1", +- "SCL1", +- "GPIO_GCLK", +- "CAM_GPIO1", +- "LAN_RUN", +- "SPI_CE1_N", +- "SPI_CE0_N", +- "SPI_MISO", +- "SPI_MOSI", +- "SPI_SCLK", +- "NC", /* GPIO12 */ +- "NC", /* GPIO13 */ +- /* Serial port */ +- "TXD0", +- "RXD0", +- "STATUS_LED_N", +- "GPIO17", +- "GPIO18", +- "NC", /* GPIO19 */ +- "NC", /* GPIO20 */ +- "GPIO21", +- "GPIO22", +- "GPIO23", +- "GPIO24", +- "GPIO25", +- "NC", /* GPIO26 */ +- "CAM_GPIO0", +- /* Binary number representing build/revision */ +- "CONFIG0", +- "CONFIG1", +- "CONFIG2", +- "CONFIG3", +- "NC", /* GPIO32 */ +- "NC", /* GPIO33 */ +- "NC", /* GPIO34 */ +- "NC", /* GPIO35 */ +- "NC", /* GPIO36 */ +- "NC", /* GPIO37 */ +- "NC", /* GPIO38 */ +- "NC", /* GPIO39 */ +- "PWM0_OUT", +- "NC", /* GPIO41 */ +- "NC", /* GPIO42 */ +- "NC", /* GPIO43 */ +- "NC", /* GPIO44 */ +- "PWM1_OUT", +- "HDMI_HPD_P", +- "SD_CARD_DET", +- /* Used by SD Card */ +- "SD_CLK_R", +- "SD_CMD_R", +- "SD_DATA0_R", +- "SD_DATA1_R", +- "SD_DATA2_R", +- "SD_DATA3_R"; +- +- pinctrl-0 = <&gpioout &alt0>; +-}; +- +-&hdmi { +- hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; +- power-domains = <&power RPI_POWER_DOMAIN_HDMI>; +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; +- status = "okay"; +-}; +- +-&sdhost { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhost_gpio48>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_gpio14>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-cm1-io1.dts b/scripts/dtc/include-prefixes/arm/bcm2835-rpi-cm1-io1.dts +deleted file mode 100644 +index a75c882e6575..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-cm1-io1.dts ++++ /dev/null +@@ -1,97 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "bcm2835-rpi-cm1.dtsi" +-#include "bcm283x-rpi-usb-host.dtsi" +- +-/ { +- compatible = "raspberrypi,compute-module", "brcm,bcm2835"; +- model = "Raspberry Pi Compute Module IO board rev1"; +-}; +- +-&gpio { +- /* +- * This is based on the official GPU firmware DT blob. +- * +- * Legend: +- * "NC" = not connected (no rail from the SoC) +- * "FOO" = GPIO line named "FOO" on the schematic +- * "FOO_N" = GPIO line named "FOO" on schematic, active low +- */ +- gpio-line-names = "GPIO0", +- "GPIO1", +- "GPIO2", +- "GPIO3", +- "GPIO4", +- "GPIO5", +- "GPIO6", +- "GPIO7", +- "GPIO8", +- "GPIO9", +- "GPIO10", +- "GPIO11", +- "GPIO12", +- "GPIO13", +- "GPIO14", +- "GPIO15", +- "GPIO16", +- "GPIO17", +- "GPIO18", +- "GPIO19", +- "GPIO20", +- "GPIO21", +- "GPIO22", +- "GPIO23", +- "GPIO24", +- "GPIO25", +- "GPIO26", +- "GPIO27", +- "GPIO28", +- "GPIO29", +- "GPIO30", +- "GPIO31", +- "GPIO32", +- "GPIO33", +- "GPIO34", +- "GPIO35", +- "GPIO36", +- "GPIO37", +- "GPIO38", +- "GPIO39", +- "GPIO40", +- "GPIO41", +- "GPIO42", +- "GPIO43", +- "GPIO44", +- "GPIO45", +- "HDMI_HPD_N", +- /* Also used as ACT LED */ +- "EMMC_EN_N", +- /* Used by eMMC */ +- "SD_CLK_R", +- "SD_CMD_R", +- "SD_DATA0_R", +- "SD_DATA1_R", +- "SD_DATA2_R", +- "SD_DATA3_R"; +- +- pinctrl-0 = <&gpioout &alt0>; +-}; +- +-&hdmi { +- hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +- power-domains = <&power RPI_POWER_DOMAIN_HDMI>; +- status = "okay"; +-}; +- +-&sdhost { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhost_gpio48>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_gpio14>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-cm1.dtsi b/scripts/dtc/include-prefixes/arm/bcm2835-rpi-cm1.dtsi +deleted file mode 100644 +index e4e6b6abbfc1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-cm1.dtsi ++++ /dev/null +@@ -1,39 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "bcm2835.dtsi" +-#include "bcm2835-rpi.dtsi" +- +-/ { +- leds { +- led-act { +- gpios = <&gpio 47 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0x20000000>; +- }; +- +- reg_3v3: fixed-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_1v8: fixed-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +-}; +- +-&sdhost { +- non-removable; +- vmmc-supply = <®_3v3>; +- vqmmc-supply = <®_1v8>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-common.dtsi b/scripts/dtc/include-prefixes/arm/bcm2835-rpi-common.dtsi +deleted file mode 100644 +index 8a55b6cded59..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-common.dtsi ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * This include file covers the common peripherals and configuration between +- * bcm2835, bcm2836 and bcm2837 implementations that interact with RPi's +- * firmware interface. +- */ +- +-#include +- +-&v3d { +- power-domains = <&power RPI_POWER_DOMAIN_V3D>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-zero-w.dts b/scripts/dtc/include-prefixes/arm/bcm2835-rpi-zero-w.dts +deleted file mode 100644 +index 33b2b77aa47d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-zero-w.dts ++++ /dev/null +@@ -1,151 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2017 Stefan Wahren +- */ +- +-/dts-v1/; +-#include "bcm2835.dtsi" +-#include "bcm2835-rpi.dtsi" +-#include "bcm283x-rpi-usb-otg.dtsi" +- +-/ { +- compatible = "raspberrypi,model-zero-w", "brcm,bcm2835"; +- model = "Raspberry Pi Zero W"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0x20000000>; +- }; +- +- chosen { +- /* 8250 auxiliary UART instead of pl011 */ +- stdout-path = "serial1:115200n8"; +- }; +- +- leds { +- led-act { +- gpios = <&gpio 47 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- wifi_pwrseq: wifi-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&gpio { +- /* +- * This is based on the official GPU firmware DT blob. +- * +- * Legend: +- * "NC" = not connected (no rail from the SoC) +- * "FOO" = GPIO line named "FOO" on the schematic +- * "FOO_N" = GPIO line named "FOO" on schematic, active low +- */ +- gpio-line-names = "ID_SDA", +- "ID_SCL", +- "SDA1", +- "SCL1", +- "GPIO_GCLK", +- "GPIO5", +- "GPIO6", +- "SPI_CE1_N", +- "SPI_CE0_N", +- "SPI_MISO", +- "SPI_MOSI", +- "SPI_SCLK", +- "GPIO12", +- "GPIO13", +- /* Serial port */ +- "TXD0", +- "RXD0", +- "GPIO16", +- "GPIO17", +- "GPIO18", +- "GPIO19", +- "GPIO20", +- "GPIO21", +- "GPIO22", +- "GPIO23", +- "GPIO24", +- "GPIO25", +- "GPIO26", +- "GPIO27", +- "SDA0", +- "SCL0", +- "NC", /* GPIO30 */ +- "NC", /* GPIO31 */ +- "NC", /* GPIO32 */ +- "NC", /* GPIO33 */ +- "NC", /* GPIO34 */ +- "NC", /* GPIO35 */ +- "NC", /* GPIO36 */ +- "NC", /* GPIO37 */ +- "NC", /* GPIO38 */ +- "NC", /* GPIO39 */ +- "CAM_GPIO1", /* GPIO40 */ +- "WL_ON", /* GPIO41 */ +- "NC", /* GPIO42 */ +- "WIFI_CLK", /* GPIO43 */ +- "CAM_GPIO0", /* GPIO44 */ +- "BT_ON", /* GPIO45 */ +- "HDMI_HPD_N", +- "STATUS_LED_N", +- /* Used by SD Card */ +- "SD_CLK_R", +- "SD_CMD_R", +- "SD_DATA0_R", +- "SD_DATA1_R", +- "SD_DATA2_R", +- "SD_DATA3_R"; +- +- pinctrl-0 = <&gpioout &alt0>; +-}; +- +-&hdmi { +- hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +- power-domains = <&power RPI_POWER_DOMAIN_HDMI>; +- status = "okay"; +-}; +- +-&sdhci { +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; +- bus-width = <4>; +- mmc-pwrseq = <&wifi_pwrseq>; +- non-removable; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-&sdhost { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhost_gpio48>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- max-speed = <2000000>; +- shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_gpio14>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-zero.dts b/scripts/dtc/include-prefixes/arm/bcm2835-rpi-zero.dts +deleted file mode 100644 +index 6f9b3a908f28..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2835-rpi-zero.dts ++++ /dev/null +@@ -1,119 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2016 Stefan Wahren +- */ +- +-/dts-v1/; +-#include "bcm2835.dtsi" +-#include "bcm2835-rpi.dtsi" +-#include "bcm283x-rpi-usb-otg.dtsi" +- +-/ { +- compatible = "raspberrypi,model-zero", "brcm,bcm2835"; +- model = "Raspberry Pi Zero"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0x20000000>; +- }; +- +- leds { +- led-act { +- gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&gpio { +- /* +- * This is based on the official GPU firmware DT blob. +- * +- * Legend: +- * "NC" = not connected (no rail from the SoC) +- * "FOO" = GPIO line named "FOO" on the schematic +- * "FOO_N" = GPIO line named "FOO" on schematic, active low +- */ +- gpio-line-names = "ID_SDA", +- "ID_SCL", +- "SDA1", +- "SCL1", +- "GPIO_GCLK", +- "GPIO5", +- "GPIO6", +- "SPI_CE1_N", +- "SPI_CE0_N", +- "SPI_MISO", +- "SPI_MOSI", +- "SPI_SCLK", +- "GPIO12", +- "GPIO13", +- /* Serial port */ +- "TXD0", +- "RXD0", +- "GPIO16", +- "GPIO17", +- "GPIO18", +- "GPIO19", +- "GPIO20", +- "GPIO21", +- "GPIO22", +- "GPIO23", +- "GPIO24", +- "GPIO25", +- "GPIO26", +- "GPIO27", +- "SDA0", +- "SCL0", +- "NC", /* GPIO30 */ +- "NC", /* GPIO31 */ +- "CAM_GPIO1", /* GPIO32 */ +- "NC", /* GPIO33 */ +- "NC", /* GPIO34 */ +- "NC", /* GPIO35 */ +- "NC", /* GPIO36 */ +- "NC", /* GPIO37 */ +- "NC", /* GPIO38 */ +- "NC", /* GPIO39 */ +- "NC", /* GPIO40 */ +- "CAM_GPIO0", /* GPIO41 */ +- "NC", /* GPIO42 */ +- "NC", /* GPIO43 */ +- "NC", /* GPIO44 */ +- "NC", /* GPIO45 */ +- "HDMI_HPD_N", +- "STATUS_LED_N", +- /* Used by SD Card */ +- "SD_CLK_R", +- "SD_CMD_R", +- "SD_DATA0_R", +- "SD_DATA1_R", +- "SD_DATA2_R", +- "SD_DATA3_R"; +- +- pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; +- +- /* I2S interface */ +- i2s_alt0: i2s_alt0 { +- brcm,pins = <18 19 20 21>; +- brcm,function = ; +- }; +-}; +- +-&hdmi { +- hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +- power-domains = <&power RPI_POWER_DOMAIN_HDMI>; +- status = "okay"; +-}; +- +-&sdhost { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhost_gpio48>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_gpio14>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2835-rpi.dtsi b/scripts/dtc/include-prefixes/arm/bcm2835-rpi.dtsi +deleted file mode 100644 +index 87ddcad76083..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2835-rpi.dtsi ++++ /dev/null +@@ -1,81 +0,0 @@ +-#include +- +-/ { +- leds { +- compatible = "gpio-leds"; +- +- led-act { +- label = "ACT"; +- default-state = "keep"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- soc { +- firmware: firmware { +- compatible = "raspberrypi,bcm2835-firmware", "simple-mfd"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- mboxes = <&mailbox>; +- dma-ranges; +- }; +- +- power: power { +- compatible = "raspberrypi,bcm2835-power"; +- firmware = <&firmware>; +- #power-domain-cells = <1>; +- }; +- +- vchiq: mailbox@7e00b840 { +- compatible = "brcm,bcm2835-vchiq"; +- reg = <0x7e00b840 0x3c>; +- interrupts = <0 2>; +- }; +- }; +-}; +- +-&gpio { +- pinctrl-names = "default"; +- +- gpioout: gpioout { +- brcm,pins = <6>; +- brcm,function = ; +- }; +- +- alt0: alt0 { +- brcm,pins = <4 5 7 8 9 10 11>; +- brcm,function = ; +- }; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_gpio0>; +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_gpio2>; +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&usb { +- power-domains = <&power RPI_POWER_DOMAIN_USB>; +-}; +- +-&vec { +- power-domains = <&power RPI_POWER_DOMAIN_VEC>; +- status = "okay"; +-}; +- +-&dsi0 { +- power-domains = <&power RPI_POWER_DOMAIN_DSI0>; +-}; +- +-&dsi1 { +- power-domains = <&power RPI_POWER_DOMAIN_DSI1>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2835.dtsi b/scripts/dtc/include-prefixes/arm/bcm2835.dtsi +deleted file mode 100644 +index 0549686134ea..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2835.dtsi ++++ /dev/null +@@ -1,38 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "bcm283x.dtsi" +-#include "bcm2835-common.dtsi" +-#include "bcm2835-rpi-common.dtsi" +- +-/ { +- compatible = "brcm,bcm2835"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,arm1176jzf-s"; +- reg = <0x0>; +- }; +- }; +- +- soc { +- ranges = <0x7e000000 0x20000000 0x02000000>; +- dma-ranges = <0x40000000 0x00000000 0x20000000>; +- }; +- +- arm-pmu { +- compatible = "arm,arm1176-pmu"; +- }; +-}; +- +-&cpu_thermal { +- coefficients = <(-538) 407000>; +-}; +- +-/* enable thermal sensor with the correct compatible property set */ +-&thermal { +- compatible = "brcm,bcm2835-thermal"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2836-rpi-2-b.dts b/scripts/dtc/include-prefixes/arm/bcm2836-rpi-2-b.dts +deleted file mode 100644 +index d8af8eeac7b6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2836-rpi-2-b.dts ++++ /dev/null +@@ -1,130 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "bcm2836.dtsi" +-#include "bcm2836-rpi.dtsi" +-#include "bcm283x-rpi-smsc9514.dtsi" +-#include "bcm283x-rpi-usb-host.dtsi" +- +-/ { +- compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; +- model = "Raspberry Pi 2 Model B"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0x40000000>; +- }; +- +- leds { +- led-act { +- gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; +- }; +- +- led-pwr { +- label = "PWR"; +- gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; +- linux,default-trigger = "default-on"; +- }; +- }; +-}; +- +-&gpio { +- /* +- * Taken from rpi_SCH_2b_1p2_reduced.pdf and +- * the official GPU firmware DT blob. +- * +- * Legend: +- * "NC" = not connected (no rail from the SoC) +- * "FOO" = GPIO line named "FOO" on the schematic +- * "FOO_N" = GPIO line named "FOO" on schematic, active low +- */ +- gpio-line-names = "ID_SDA", +- "ID_SCL", +- "SDA1", +- "SCL1", +- "GPIO_GCLK", +- "GPIO5", +- "GPIO6", +- "SPI_CE1_N", +- "SPI_CE0_N", +- "SPI_MISO", +- "SPI_MOSI", +- "SPI_SCLK", +- "GPIO12", +- "GPIO13", +- /* Serial port */ +- "TXD0", +- "RXD0", +- "GPIO16", +- "GPIO17", +- "GPIO18", +- "GPIO19", +- "GPIO20", +- "GPIO21", +- "GPIO22", +- "GPIO23", +- "GPIO24", +- "GPIO25", +- "GPIO26", +- "GPIO27", +- "SDA0", +- "SCL0", +- "", /* GPIO30 */ +- "LAN_RUN", +- "CAM_GPIO1", +- "", /* GPIO33 */ +- "", /* GPIO34 */ +- "PWR_LOW_N", +- "", /* GPIO36 */ +- "", /* GPIO37 */ +- "USB_LIMIT", +- "", /* GPIO39 */ +- "PWM0_OUT", +- "CAM_GPIO0", +- "SMPS_SCL", +- "SMPS_SDA", +- "ETHCLK", +- "PWM1_OUT", +- "HDMI_HPD_N", +- "STATUS_LED", +- /* Used by SD Card */ +- "SD_CLK_R", +- "SD_CMD_R", +- "SD_DATA0_R", +- "SD_DATA1_R", +- "SD_DATA2_R", +- "SD_DATA3_R"; +- +- pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; +- +- /* I2S interface */ +- i2s_alt0: i2s_alt0 { +- brcm,pins = <18 19 20 21>; +- brcm,function = ; +- }; +-}; +- +-&hdmi { +- hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +- power-domains = <&power RPI_POWER_DOMAIN_HDMI>; +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; +- status = "okay"; +-}; +- +-&sdhost { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhost_gpio48>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_gpio14>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2836-rpi.dtsi b/scripts/dtc/include-prefixes/arm/bcm2836-rpi.dtsi +deleted file mode 100644 +index c4c858b984c6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2836-rpi.dtsi ++++ /dev/null +@@ -1,6 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "bcm2835-rpi.dtsi" +- +-&vchiq { +- compatible = "brcm,bcm2836-vchiq", "brcm,bcm2835-vchiq"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2836.dtsi b/scripts/dtc/include-prefixes/arm/bcm2836.dtsi +deleted file mode 100644 +index b390006aef79..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2836.dtsi ++++ /dev/null +@@ -1,92 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "bcm283x.dtsi" +-#include "bcm2835-common.dtsi" +-#include "bcm2835-rpi-common.dtsi" +- +-/ { +- compatible = "brcm,bcm2836"; +- +- soc { +- ranges = <0x7e000000 0x3f000000 0x1000000>, +- <0x40000000 0x40000000 0x00001000>; +- dma-ranges = <0xc0000000 0x00000000 0x3f000000>; +- +- local_intc: local_intc@40000000 { +- compatible = "brcm,bcm2836-l1-intc"; +- reg = <0x40000000 0x100>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupt-parent = <&local_intc>; +- }; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupt-parent = <&local_intc>; +- interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupt-parent = <&local_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI +- <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI +- <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI +- <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI +- always-on; +- }; +- +- cpus: cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "brcm,bcm2836-smp"; +- +- v7_cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0xf00>; +- clock-frequency = <800000000>; +- }; +- +- v7_cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0xf01>; +- clock-frequency = <800000000>; +- }; +- +- v7_cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0xf02>; +- clock-frequency = <800000000>; +- }; +- +- v7_cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0xf03>; +- clock-frequency = <800000000>; +- }; +- }; +-}; +- +-/* Make the BCM2835-style global interrupt controller be a child of the +- * CPU-local interrupt controller. +- */ +-&intc { +- compatible = "brcm,bcm2836-armctrl-ic"; +- reg = <0x7e00b200 0x200>; +- interrupt-parent = <&local_intc>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&cpu_thermal { +- coefficients = <(-538) 407000>; +-}; +- +-/* enable thermal sensor with the correct compatible property set */ +-&thermal { +- compatible = "brcm,bcm2836-thermal"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2837-rpi-3-a-plus.dts b/scripts/dtc/include-prefixes/arm/bcm2837-rpi-3-a-plus.dts +deleted file mode 100644 +index 77099a7871b0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2837-rpi-3-a-plus.dts ++++ /dev/null +@@ -1,180 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "bcm2837.dtsi" +-#include "bcm2836-rpi.dtsi" +-#include "bcm283x-rpi-usb-host.dtsi" +- +-/ { +- compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837"; +- model = "Raspberry Pi 3 Model A+"; +- +- chosen { +- /* 8250 auxiliary UART instead of pl011 */ +- stdout-path = "serial1:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0x20000000>; +- }; +- +- leds { +- led-act { +- gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; +- }; +- +- led-pwr { +- label = "PWR"; +- gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- linux,default-trigger = "default-on"; +- }; +- }; +-}; +- +-&firmware { +- expgpio: gpio { +- compatible = "raspberrypi,firmware-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-line-names = "", +- "BT_WL_ON", +- "STATUS_LED_R", +- "", +- "", +- "CAM_GPIO0", +- "CAM_GPIO1", +- ""; +- status = "okay"; +- }; +-}; +- +-&gpio { +- /* +- * This is mostly based on the official GPU firmware DT blob. +- * +- * Legend: +- * "NC" = not connected (no rail from the SoC) +- * "FOO" = GPIO line named "FOO" on the schematic +- * "FOO_N" = GPIO line named "FOO" on schematic, active low +- */ +- gpio-line-names = "ID_SDA", +- "ID_SCL", +- "SDA1", +- "SCL1", +- "GPIO_GCLK", +- "GPIO5", +- "GPIO6", +- "SPI_CE1_N", +- "SPI_CE0_N", +- "SPI_MISO", +- "SPI_MOSI", +- "SPI_SCLK", +- "GPIO12", +- "GPIO13", +- /* Serial port */ +- "TXD1", +- "RXD1", +- "GPIO16", +- "GPIO17", +- "GPIO18", +- "GPIO19", +- "GPIO20", +- "GPIO21", +- "GPIO22", +- "GPIO23", +- "GPIO24", +- "GPIO25", +- "GPIO26", +- "GPIO27", +- "HDMI_HPD_N", +- "STATUS_LED_G", +- /* Used by BT module */ +- "CTS0", +- "RTS0", +- "TXD0", +- "RXD0", +- /* Used by Wifi */ +- "SD1_CLK", +- "SD1_CMD", +- "SD1_DATA0", +- "SD1_DATA1", +- "SD1_DATA2", +- "SD1_DATA3", +- "PWM0_OUT", +- "PWM1_OUT", +- "", /* GPIO42 */ +- "WIFI_CLK", +- "SDA0", +- "SCL0", +- "SMPS_SCL", +- "SMPS_SDA", +- /* Used by SD Card */ +- "SD_CLK_R", +- "SD_CMD_R", +- "SD_DATA0_R", +- "SD_DATA1_R", +- "SD_DATA2_R", +- "SD_DATA3_R"; +-}; +- +-&hdmi { +- hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; +- power-domains = <&power RPI_POWER_DOMAIN_HDMI>; +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; +- status = "okay"; +-}; +- +-/* +- * SDHCI is used to control the SDIO for wireless +- * +- * WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven +- * by a single GPIO. We can't give GPIO control to one of the drivers, +- * otherwise the other part would get unexpectedly disturbed. +- */ +-&sdhci { +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_gpio34>; +- status = "okay"; +- bus-width = <4>; +- non-removable; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* SDHOST is used to drive the SD card */ +-&sdhost { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhost_gpio48>; +- status = "okay"; +- bus-width = <4>; +-}; +- +-/* uart0 communicates with the BT module */ +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- max-speed = <2000000>; +- }; +-}; +- +-/* uart1 is mapped to the pin header */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_gpio14>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2837-rpi-3-b-plus.dts b/scripts/dtc/include-prefixes/arm/bcm2837-rpi-3-b-plus.dts +deleted file mode 100644 +index 61010266ca9a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2837-rpi-3-b-plus.dts ++++ /dev/null +@@ -1,183 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "bcm2837.dtsi" +-#include "bcm2836-rpi.dtsi" +-#include "bcm283x-rpi-lan7515.dtsi" +-#include "bcm283x-rpi-usb-host.dtsi" +- +-/ { +- compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837"; +- model = "Raspberry Pi 3 Model B+"; +- +- chosen { +- /* 8250 auxiliary UART instead of pl011 */ +- stdout-path = "serial1:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0x40000000>; +- }; +- +- leds { +- led-act { +- gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; +- }; +- +- led-pwr { +- label = "PWR"; +- gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- linux,default-trigger = "default-on"; +- }; +- }; +- +- wifi_pwrseq: wifi-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&firmware { +- expgpio: gpio { +- compatible = "raspberrypi,firmware-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-line-names = "BT_ON", +- "WL_ON", +- "STATUS_LED_R", +- "LAN_RUN", +- "", +- "CAM_GPIO0", +- "CAM_GPIO1", +- ""; +- status = "okay"; +- }; +-}; +- +-&gpio { +- /* +- * Taken from rpi_SCH_3bplus_1p0_reduced.pdf and +- * the official GPU firmware DT blob. +- * +- * Legend: +- * "NC" = not connected (no rail from the SoC) +- * "FOO" = GPIO line named "FOO" on the schematic +- * "FOO_N" = GPIO line named "FOO" on schematic, active low +- */ +- gpio-line-names = "ID_SDA", +- "ID_SCL", +- "SDA1", +- "SCL1", +- "GPIO_GCLK", +- "GPIO5", +- "GPIO6", +- "SPI_CE1_N", +- "SPI_CE0_N", +- "SPI_MISO", +- "SPI_MOSI", +- "SPI_SCLK", +- "GPIO12", +- "GPIO13", +- /* Serial port */ +- "TXD1", +- "RXD1", +- "GPIO16", +- "GPIO17", +- "GPIO18", +- "GPIO19", +- "GPIO20", +- "GPIO21", +- "GPIO22", +- "GPIO23", +- "GPIO24", +- "GPIO25", +- "GPIO26", +- "GPIO27", +- "HDMI_HPD_N", +- "STATUS_LED_G", +- /* Used by BT module */ +- "CTS0", +- "RTS0", +- "TXD0", +- "RXD0", +- /* Used by Wifi */ +- "SD1_CLK", +- "SD1_CMD", +- "SD1_DATA0", +- "SD1_DATA1", +- "SD1_DATA2", +- "SD1_DATA3", +- "PWM0_OUT", +- "PWM1_OUT", +- "ETHCLK", +- "WIFI_CLK", +- "SDA0", +- "SCL0", +- "SMPS_SCL", +- "SMPS_SDA", +- /* Used by SD Card */ +- "SD_CLK_R", +- "SD_CMD_R", +- "SD_DATA0_R", +- "SD_DATA1_R", +- "SD_DATA2_R", +- "SD_DATA3_R"; +-}; +- +-&hdmi { +- hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; +- power-domains = <&power RPI_POWER_DOMAIN_HDMI>; +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; +- status = "okay"; +-}; +- +-/* SDHCI is used to control the SDIO for wireless */ +-&sdhci { +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_gpio34>; +- status = "okay"; +- bus-width = <4>; +- non-removable; +- mmc-pwrseq = <&wifi_pwrseq>; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* SDHOST is used to drive the SD card */ +-&sdhost { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhost_gpio48>; +- status = "okay"; +- bus-width = <4>; +-}; +- +-/* uart0 communicates with the BT module */ +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- max-speed = <2000000>; +- shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-/* uart1 is mapped to the pin header */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_gpio14>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2837-rpi-3-b.dts b/scripts/dtc/include-prefixes/arm/bcm2837-rpi-3-b.dts +deleted file mode 100644 +index dd4a48604097..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2837-rpi-3-b.dts ++++ /dev/null +@@ -1,176 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "bcm2837.dtsi" +-#include "bcm2836-rpi.dtsi" +-#include "bcm283x-rpi-smsc9514.dtsi" +-#include "bcm283x-rpi-usb-host.dtsi" +- +-/ { +- compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; +- model = "Raspberry Pi 3 Model B"; +- +- chosen { +- /* 8250 auxiliary UART instead of pl011 */ +- stdout-path = "serial1:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0x40000000>; +- }; +- +- leds { +- led-act { +- gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- wifi_pwrseq: wifi-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&firmware { +- expgpio: gpio { +- compatible = "raspberrypi,firmware-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-line-names = "BT_ON", +- "WL_ON", +- "STATUS_LED", +- "LAN_RUN", +- "HDMI_HPD_N", +- "CAM_GPIO0", +- "CAM_GPIO1", +- "PWR_LOW_N"; +- status = "okay"; +- }; +-}; +- +-&gpio { +- /* +- * Taken from rpi_SCH_3b_1p2_reduced.pdf and +- * the official GPU firmware DT blob. +- * +- * Legend: +- * "NC" = not connected (no rail from the SoC) +- * "FOO" = GPIO line named "FOO" on the schematic +- * "FOO_N" = GPIO line named "FOO" on schematic, active low +- */ +- gpio-line-names = "ID_SDA", +- "ID_SCL", +- "SDA1", +- "SCL1", +- "GPIO_GCLK", +- "GPIO5", +- "GPIO6", +- "SPI_CE1_N", +- "SPI_CE0_N", +- "SPI_MISO", +- "SPI_MOSI", +- "SPI_SCLK", +- "GPIO12", +- "GPIO13", +- /* Serial port */ +- "TXD1", +- "RXD1", +- "GPIO16", +- "GPIO17", +- "GPIO18", +- "GPIO19", +- "GPIO20", +- "GPIO21", +- "GPIO22", +- "GPIO23", +- "GPIO24", +- "GPIO25", +- "GPIO26", +- "GPIO27", +- "", /* GPIO 28 */ +- "LAN_RUN_BOOT", +- /* Used by BT module */ +- "CTS0", +- "RTS0", +- "TXD0", +- "RXD0", +- /* Used by Wifi */ +- "SD1_CLK", +- "SD1_CMD", +- "SD1_DATA0", +- "SD1_DATA1", +- "SD1_DATA2", +- "SD1_DATA3", +- "PWM0_OUT", +- "PWM1_OUT", +- "ETHCLK", +- "WIFI_CLK", +- "SDA0", +- "SCL0", +- "SMPS_SCL", +- "SMPS_SDA", +- /* Used by SD Card */ +- "SD_CLK_R", +- "SD_CMD_R", +- "SD_DATA0_R", +- "SD_DATA1_R", +- "SD_DATA2_R", +- "SD_DATA3_R"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; +- status = "okay"; +-}; +- +-&hdmi { +- hpd-gpios = <&expgpio 4 GPIO_ACTIVE_LOW>; +- power-domains = <&power RPI_POWER_DOMAIN_HDMI>; +- status = "okay"; +-}; +- +-/* uart0 communicates with the BT module */ +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- max-speed = <2000000>; +- shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-/* uart1 is mapped to the pin header */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_gpio14>; +- status = "okay"; +-}; +- +-/* SDHCI is used to control the SDIO for wireless */ +-&sdhci { +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_gpio34>; +- status = "okay"; +- bus-width = <4>; +- non-removable; +- mmc-pwrseq = <&wifi_pwrseq>; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* SDHOST is used to drive the SD card */ +-&sdhost { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhost_gpio48>; +- status = "okay"; +- bus-width = <4>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2837-rpi-cm3-io3.dts b/scripts/dtc/include-prefixes/arm/bcm2837-rpi-cm3-io3.dts +deleted file mode 100644 +index 588d9411ceb6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2837-rpi-cm3-io3.dts ++++ /dev/null +@@ -1,96 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "bcm2837-rpi-cm3.dtsi" +-#include "bcm283x-rpi-usb-host.dtsi" +- +-/ { +- compatible = "raspberrypi,3-compute-module", "brcm,bcm2837"; +- model = "Raspberry Pi Compute Module 3 IO board V3.0"; +-}; +- +-&gpio { +- /* +- * This is based on the official GPU firmware DT blob. +- * +- * Legend: +- * "NC" = not connected (no rail from the SoC) +- * "FOO" = GPIO line named "FOO" on the schematic +- * "FOO_N" = GPIO line named "FOO" on schematic, active low +- */ +- gpio-line-names = "GPIO0", +- "GPIO1", +- "GPIO2", +- "GPIO3", +- "GPIO4", +- "GPIO5", +- "GPIO6", +- "GPIO7", +- "GPIO8", +- "GPIO9", +- "GPIO10", +- "GPIO11", +- "GPIO12", +- "GPIO13", +- "GPIO14", +- "GPIO15", +- "GPIO16", +- "GPIO17", +- "GPIO18", +- "GPIO19", +- "GPIO20", +- "GPIO21", +- "GPIO22", +- "GPIO23", +- "GPIO24", +- "GPIO25", +- "GPIO26", +- "GPIO27", +- "GPIO28", +- "GPIO29", +- "GPIO30", +- "GPIO31", +- "GPIO32", +- "GPIO33", +- "GPIO34", +- "GPIO35", +- "GPIO36", +- "GPIO37", +- "GPIO38", +- "GPIO39", +- "GPIO40", +- "GPIO41", +- "GPIO42", +- "GPIO43", +- "GPIO44", +- "GPIO45", +- "GPIO46", +- "GPIO47", +- /* Used by eMMC */ +- "SD_CLK_R", +- "SD_CMD_R", +- "SD_DATA0_R", +- "SD_DATA1_R", +- "SD_DATA2_R", +- "SD_DATA3_R"; +- +- pinctrl-0 = <&gpioout &alt0>; +-}; +- +-&hdmi { +- hpd-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; +- power-domains = <&power RPI_POWER_DOMAIN_HDMI>; +- status = "okay"; +-}; +- +-&sdhost { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhost_gpio48>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_gpio14>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2837-rpi-cm3.dtsi b/scripts/dtc/include-prefixes/arm/bcm2837-rpi-cm3.dtsi +deleted file mode 100644 +index 828a20561b96..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2837-rpi-cm3.dtsi ++++ /dev/null +@@ -1,61 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "bcm2837.dtsi" +-#include "bcm2836-rpi.dtsi" +- +-/ { +- memory@0 { +- device_type = "memory"; +- reg = <0 0x40000000>; +- }; +- +- leds { +- /* +- * Since there is no upstream GPIO driver yet, +- * remove the incomplete node. +- */ +- /delete-node/ led-act; +- }; +- +- reg_3v3: fixed-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_1v8: fixed-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +-}; +- +-&firmware { +- expgpio: gpio { +- compatible = "raspberrypi,firmware-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-line-names = "HDMI_HPD_N", +- "EMMC_EN_N", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC"; +- status = "okay"; +- }; +-}; +- +-&sdhost { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhost_gpio48>; +- bus-width = <4>; +- vmmc-supply = <®_3v3>; +- vqmmc-supply = <®_1v8>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm2837.dtsi b/scripts/dtc/include-prefixes/arm/bcm2837.dtsi +deleted file mode 100644 +index 0199ec98cd61..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm2837.dtsi ++++ /dev/null +@@ -1,95 +0,0 @@ +-#include "bcm283x.dtsi" +-#include "bcm2835-common.dtsi" +-#include "bcm2835-rpi-common.dtsi" +- +-/ { +- compatible = "brcm,bcm2837"; +- +- soc { +- ranges = <0x7e000000 0x3f000000 0x1000000>, +- <0x40000000 0x40000000 0x00001000>; +- dma-ranges = <0xc0000000 0x00000000 0x3f000000>; +- +- local_intc: local_intc@40000000 { +- compatible = "brcm,bcm2836-l1-intc"; +- reg = <0x40000000 0x100>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupt-parent = <&local_intc>; +- }; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupt-parent = <&local_intc>; +- interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupt-parent = <&local_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI +- <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI +- <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI +- <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI +- always-on; +- }; +- +- cpus: cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x000000d8>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <1>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x000000e0>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <2>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x000000e8>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <3>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x000000f0>; +- }; +- }; +-}; +- +-/* Make the BCM2835-style global interrupt controller be a child of the +- * CPU-local interrupt controller. +- */ +-&intc { +- compatible = "brcm,bcm2836-armctrl-ic"; +- reg = <0x7e00b200 0x200>; +- interrupt-parent = <&local_intc>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&cpu_thermal { +- coefficients = <(-538) 412000>; +-}; +- +-/* enable thermal sensor with the correct compatible property set */ +-&thermal { +- compatible = "brcm,bcm2837-thermal"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm283x-rpi-lan7515.dtsi b/scripts/dtc/include-prefixes/arm/bcm283x-rpi-lan7515.dtsi +deleted file mode 100644 +index 70bece63f9a7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm283x-rpi-lan7515.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +- +-/ { +- aliases { +- ethernet0 = ðernet; +- }; +-}; +- +-&usb { +- usb-port@1 { +- compatible = "usb424,2514"; +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- usb-port@1 { +- compatible = "usb424,2514"; +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethernet: ethernet@1 { +- compatible = "usb424,7800"; +- reg = <1>; +- +- mdio { +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- eth_phy: ethernet-phy@1 { +- reg = <1>; +- microchip,led-modes = < +- LAN78XX_LINK_1000_ACTIVITY +- LAN78XX_LINK_10_100_ACTIVITY +- >; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm283x-rpi-smsc9512.dtsi b/scripts/dtc/include-prefixes/arm/bcm283x-rpi-smsc9512.dtsi +deleted file mode 100644 +index 967e081cb9c2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm283x-rpi-smsc9512.dtsi ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- aliases { +- ethernet0 = ðernet; +- }; +-}; +- +-&usb { +- usb1@1 { +- compatible = "usb424,9512"; +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethernet: usbether@1 { +- compatible = "usb424,ec00"; +- reg = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm283x-rpi-smsc9514.dtsi b/scripts/dtc/include-prefixes/arm/bcm283x-rpi-smsc9514.dtsi +deleted file mode 100644 +index dc7ae776db5f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm283x-rpi-smsc9514.dtsi ++++ /dev/null +@@ -1,19 +0,0 @@ +-/ { +- aliases { +- ethernet0 = ðernet; +- }; +-}; +- +-&usb { +- usb1@1 { +- compatible = "usb424,9514"; +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethernet: usbether@1 { +- compatible = "usb424,ec00"; +- reg = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm283x-rpi-usb-host.dtsi b/scripts/dtc/include-prefixes/arm/bcm283x-rpi-usb-host.dtsi +deleted file mode 100644 +index 73f4ece8dcd0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm283x-rpi-usb-host.dtsi ++++ /dev/null +@@ -1,3 +0,0 @@ +-&usb { +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm283x-rpi-usb-otg.dtsi b/scripts/dtc/include-prefixes/arm/bcm283x-rpi-usb-otg.dtsi +deleted file mode 100644 +index e2fd9610e125..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm283x-rpi-usb-otg.dtsi ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-&usb { +- dr_mode = "otg"; +- g-rx-fifo-size = <256>; +- g-np-tx-fifo-size = <32>; +- /* +- * According to dwc2 the sum of all device EP +- * fifo sizes shouldn't exceed 3776 bytes. +- */ +- g-tx-fifo-size = <256 256 512 512 512 768 768>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm283x-rpi-usb-peripheral.dtsi b/scripts/dtc/include-prefixes/arm/bcm283x-rpi-usb-peripheral.dtsi +deleted file mode 100644 +index 0ff0e9e25327..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm283x-rpi-usb-peripheral.dtsi ++++ /dev/null +@@ -1,7 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-&usb { +- dr_mode = "peripheral"; +- g-rx-fifo-size = <256>; +- g-np-tx-fifo-size = <32>; +- g-tx-fifo-size = <256 256 512 512 512 768 768>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm283x.dtsi b/scripts/dtc/include-prefixes/arm/bcm283x.dtsi +deleted file mode 100644 +index c113661a6668..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm283x.dtsi ++++ /dev/null +@@ -1,503 +0,0 @@ +-#include +-#include +-#include +-#include +-#include +-#include +- +-/* firmware-provided startup stubs live here, where the secondary CPUs are +- * spinning. +- */ +-/memreserve/ 0x00000000 0x00001000; +- +-/* This include file covers the common peripherals and configuration between +- * bcm2835 and bcm2836 implementations, leaving the CPU configuration to +- * bcm2835.dtsi and bcm2836.dtsi. +- */ +- +-/ { +- compatible = "brcm,bcm2835"; +- model = "BCM2835"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- rmem: reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- cma: linux,cma { +- compatible = "shared-dma-pool"; +- size = <0x4000000>; /* 64MB */ +- reusable; +- linux,cma-default; +- }; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <1000>; +- +- trips { +- cpu-crit { +- temperature = <90000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- }; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- system_timer: timer@7e003000 { +- compatible = "brcm,bcm2835-system-timer"; +- reg = <0x7e003000 0x1000>; +- interrupts = <1 0>, <1 1>, <1 2>, <1 3>; +- /* This could be a reference to BCM2835_CLOCK_TIMER, +- * but we don't have the driver using the common clock +- * support yet. +- */ +- clock-frequency = <1000000>; +- }; +- +- txp: txp@7e004000 { +- compatible = "brcm,bcm2835-txp"; +- reg = <0x7e004000 0x20>; +- interrupts = <1 11>; +- }; +- +- clocks: cprman@7e101000 { +- compatible = "brcm,bcm2835-cprman"; +- #clock-cells = <1>; +- reg = <0x7e101000 0x2000>; +- +- /* CPRMAN derives almost everything from the +- * platform's oscillator. However, the DSI +- * pixel clocks come from the DSI analog PHY. +- */ +- clocks = <&clk_osc>, +- <&dsi0 0>, <&dsi0 1>, <&dsi0 2>, +- <&dsi1 0>, <&dsi1 1>, <&dsi1 2>; +- }; +- +- mailbox: mailbox@7e00b880 { +- compatible = "brcm,bcm2835-mbox"; +- reg = <0x7e00b880 0x40>; +- interrupts = <0 1>; +- #mbox-cells = <0>; +- }; +- +- gpio: gpio@7e200000 { +- compatible = "brcm,bcm2835-gpio"; +- reg = <0x7e200000 0xb4>; +- /* +- * The GPIO IP block is designed for 3 banks of GPIOs. +- * Each bank has a GPIO interrupt for itself. +- * There is an overall "any bank" interrupt. +- * In order, these are GIC interrupts 17, 18, 19, 20. +- * Since the BCM2835 only has 2 banks, the 2nd bank +- * interrupt output appears to be mirrored onto the +- * 3rd bank's interrupt signal. +- * So, a bank0 interrupt shows up on 17, 20, and +- * a bank1 interrupt shows up on 18, 19, 20! +- */ +- interrupts = <2 17>, <2 18>, <2 19>, <2 20>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- gpio-ranges = <&gpio 0 0 54>; +- +- /* Defines common pin muxing groups +- * +- * While each pin can have its mux selected +- * for various functions individually, some +- * groups only make sense to switch to a +- * particular function together. +- */ +- dpi_gpio0: dpi_gpio0 { +- brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 +- 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27>; +- brcm,function = ; +- }; +- emmc_gpio22: emmc_gpio22 { +- brcm,pins = <22 23 24 25 26 27>; +- brcm,function = ; +- }; +- emmc_gpio34: emmc_gpio34 { +- brcm,pins = <34 35 36 37 38 39>; +- brcm,function = ; +- brcm,pull = ; +- }; +- emmc_gpio48: emmc_gpio48 { +- brcm,pins = <48 49 50 51 52 53>; +- brcm,function = ; +- }; +- +- gpclk0_gpio4: gpclk0_gpio4 { +- brcm,pins = <4>; +- brcm,function = ; +- }; +- gpclk1_gpio5: gpclk1_gpio5 { +- brcm,pins = <5>; +- brcm,function = ; +- }; +- gpclk1_gpio42: gpclk1_gpio42 { +- brcm,pins = <42>; +- brcm,function = ; +- }; +- gpclk1_gpio44: gpclk1_gpio44 { +- brcm,pins = <44>; +- brcm,function = ; +- }; +- gpclk2_gpio6: gpclk2_gpio6 { +- brcm,pins = <6>; +- brcm,function = ; +- }; +- gpclk2_gpio43: gpclk2_gpio43 { +- brcm,pins = <43>; +- brcm,function = ; +- brcm,pull = ; +- }; +- +- i2c0_gpio0: i2c0_gpio0 { +- brcm,pins = <0 1>; +- brcm,function = ; +- }; +- i2c0_gpio28: i2c0_gpio28 { +- brcm,pins = <28 29>; +- brcm,function = ; +- }; +- i2c0_gpio44: i2c0_gpio44 { +- brcm,pins = <44 45>; +- brcm,function = ; +- }; +- i2c1_gpio2: i2c1_gpio2 { +- brcm,pins = <2 3>; +- brcm,function = ; +- }; +- i2c1_gpio44: i2c1_gpio44 { +- brcm,pins = <44 45>; +- brcm,function = ; +- }; +- +- jtag_gpio22: jtag_gpio22 { +- brcm,pins = <22 23 24 25 26 27>; +- brcm,function = ; +- }; +- +- pcm_gpio18: pcm_gpio18 { +- brcm,pins = <18 19 20 21>; +- brcm,function = ; +- }; +- pcm_gpio28: pcm_gpio28 { +- brcm,pins = <28 29 30 31>; +- brcm,function = ; +- }; +- +- sdhost_gpio48: sdhost_gpio48 { +- brcm,pins = <48 49 50 51 52 53>; +- brcm,function = ; +- }; +- +- spi0_gpio7: spi0_gpio7 { +- brcm,pins = <7 8 9 10 11>; +- brcm,function = ; +- }; +- spi0_gpio35: spi0_gpio35 { +- brcm,pins = <35 36 37 38 39>; +- brcm,function = ; +- }; +- spi1_gpio16: spi1_gpio16 { +- brcm,pins = <16 17 18 19 20 21>; +- brcm,function = ; +- }; +- spi2_gpio40: spi2_gpio40 { +- brcm,pins = <40 41 42 43 44 45>; +- brcm,function = ; +- }; +- +- uart0_gpio14: uart0_gpio14 { +- brcm,pins = <14 15>; +- brcm,function = ; +- }; +- /* Separate from the uart0_gpio14 group +- * because it conflicts with spi1_gpio16, and +- * people often run uart0 on the two pins +- * without flow control. +- */ +- uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 { +- brcm,pins = <16 17>; +- brcm,function = ; +- }; +- uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 { +- brcm,pins = <30 31>; +- brcm,function = ; +- brcm,pull = ; +- }; +- uart0_gpio32: uart0_gpio32 { +- brcm,pins = <32 33>; +- brcm,function = ; +- brcm,pull = ; +- }; +- uart0_gpio36: uart0_gpio36 { +- brcm,pins = <36 37>; +- brcm,function = ; +- }; +- uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 { +- brcm,pins = <38 39>; +- brcm,function = ; +- }; +- +- uart1_gpio14: uart1_gpio14 { +- brcm,pins = <14 15>; +- brcm,function = ; +- }; +- uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 { +- brcm,pins = <16 17>; +- brcm,function = ; +- }; +- uart1_gpio32: uart1_gpio32 { +- brcm,pins = <32 33>; +- brcm,function = ; +- }; +- uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 { +- brcm,pins = <30 31>; +- brcm,function = ; +- }; +- uart1_gpio40: uart1_gpio40 { +- brcm,pins = <40 41>; +- brcm,function = ; +- }; +- uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 { +- brcm,pins = <42 43>; +- brcm,function = ; +- }; +- }; +- +- uart0: serial@7e201000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x7e201000 0x200>; +- interrupts = <2 25>; +- clocks = <&clocks BCM2835_CLOCK_UART>, +- <&clocks BCM2835_CLOCK_VPU>; +- clock-names = "uartclk", "apb_pclk"; +- arm,primecell-periphid = <0x00241011>; +- }; +- +- sdhost: mmc@7e202000 { +- compatible = "brcm,bcm2835-sdhost"; +- reg = <0x7e202000 0x100>; +- interrupts = <2 24>; +- clocks = <&clocks BCM2835_CLOCK_VPU>; +- status = "disabled"; +- }; +- +- i2s: i2s@7e203000 { +- compatible = "brcm,bcm2835-i2s"; +- reg = <0x7e203000 0x24>; +- clocks = <&clocks BCM2835_CLOCK_PCM>; +- status = "disabled"; +- }; +- +- spi: spi@7e204000 { +- compatible = "brcm,bcm2835-spi"; +- reg = <0x7e204000 0x200>; +- interrupts = <2 22>; +- clocks = <&clocks BCM2835_CLOCK_VPU>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c0: i2c@7e205000 { +- compatible = "brcm,bcm2835-i2c"; +- reg = <0x7e205000 0x200>; +- interrupts = <2 21>; +- clocks = <&clocks BCM2835_CLOCK_VPU>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- dpi: dpi@7e208000 { +- compatible = "brcm,bcm2835-dpi"; +- reg = <0x7e208000 0x8c>; +- clocks = <&clocks BCM2835_CLOCK_VPU>, +- <&clocks BCM2835_CLOCK_DPI>; +- clock-names = "core", "pixel"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- dsi0: dsi@7e209000 { +- compatible = "brcm,bcm2835-dsi0"; +- reg = <0x7e209000 0x78>; +- interrupts = <2 4>; +- #address-cells = <1>; +- #size-cells = <0>; +- #clock-cells = <1>; +- +- clocks = <&clocks BCM2835_PLLA_DSI0>, +- <&clocks BCM2835_CLOCK_DSI0E>, +- <&clocks BCM2835_CLOCK_DSI0P>; +- clock-names = "phy", "escape", "pixel"; +- +- clock-output-names = "dsi0_byte", +- "dsi0_ddr2", +- "dsi0_ddr"; +- +- status = "disabled"; +- }; +- +- aux: aux@7e215000 { +- compatible = "brcm,bcm2835-aux"; +- #clock-cells = <1>; +- reg = <0x7e215000 0x8>; +- clocks = <&clocks BCM2835_CLOCK_VPU>; +- }; +- +- uart1: serial@7e215040 { +- compatible = "brcm,bcm2835-aux-uart"; +- reg = <0x7e215040 0x40>; +- interrupts = <1 29>; +- clocks = <&aux BCM2835_AUX_CLOCK_UART>; +- status = "disabled"; +- }; +- +- spi1: spi@7e215080 { +- compatible = "brcm,bcm2835-aux-spi"; +- reg = <0x7e215080 0x40>; +- interrupts = <1 29>; +- clocks = <&aux BCM2835_AUX_CLOCK_SPI1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi2: spi@7e2150c0 { +- compatible = "brcm,bcm2835-aux-spi"; +- reg = <0x7e2150c0 0x40>; +- interrupts = <1 29>; +- clocks = <&aux BCM2835_AUX_CLOCK_SPI2>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pwm: pwm@7e20c000 { +- compatible = "brcm,bcm2835-pwm"; +- reg = <0x7e20c000 0x28>; +- clocks = <&clocks BCM2835_CLOCK_PWM>; +- assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; +- assigned-clock-rates = <10000000>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- sdhci: mmc@7e300000 { +- compatible = "brcm,bcm2835-sdhci"; +- reg = <0x7e300000 0x100>; +- interrupts = <2 30>; +- clocks = <&clocks BCM2835_CLOCK_EMMC>; +- status = "disabled"; +- }; +- +- hvs@7e400000 { +- compatible = "brcm,bcm2835-hvs"; +- reg = <0x7e400000 0x6000>; +- interrupts = <2 1>; +- }; +- +- dsi1: dsi@7e700000 { +- compatible = "brcm,bcm2835-dsi1"; +- reg = <0x7e700000 0x8c>; +- interrupts = <2 12>; +- #address-cells = <1>; +- #size-cells = <0>; +- #clock-cells = <1>; +- +- clocks = <&clocks BCM2835_PLLD_DSI1>, +- <&clocks BCM2835_CLOCK_DSI1E>, +- <&clocks BCM2835_CLOCK_DSI1P>; +- clock-names = "phy", "escape", "pixel"; +- +- clock-output-names = "dsi1_byte", +- "dsi1_ddr2", +- "dsi1_ddr"; +- +- status = "disabled"; +- }; +- +- i2c1: i2c@7e804000 { +- compatible = "brcm,bcm2835-i2c"; +- reg = <0x7e804000 0x1000>; +- interrupts = <2 21>; +- clocks = <&clocks BCM2835_CLOCK_VPU>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- usb: usb@7e980000 { +- compatible = "brcm,bcm2835-usb"; +- reg = <0x7e980000 0x10000>; +- interrupts = <1 9>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clk_usb>; +- clock-names = "otg"; +- phys = <&usbphy>; +- phy-names = "usb2-phy"; +- }; +- }; +- +- clocks { +- /* The oscillator is the root of the clock tree. */ +- clk_osc: clk-osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-output-names = "osc"; +- clock-frequency = <19200000>; +- }; +- +- clk_usb: clk-usb { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-output-names = "otg"; +- clock-frequency = <480000000>; +- }; +- }; +- +- usbphy: phy { +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm4708-asus-rt-ac56u.dts b/scripts/dtc/include-prefixes/arm/bcm4708-asus-rt-ac56u.dts +deleted file mode 100644 +index 8ed403767540..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm4708-asus-rt-ac56u.dts ++++ /dev/null +@@ -1,95 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Broadcom BCM470X / BCM5301X ARM platform code. +- * DTS for Asus RT-AC56U +- * +- * Copyright (C) 2015 Rafał Miłecki +- */ +- +-/dts-v1/; +- +-#include "bcm4708.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "asus,rt-ac56u", "brcm,bcm4708"; +- model = "Asus RT-AC56U (BCM4708)"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x08000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- usb3 { +- label = "bcm53xx:blue:usb3"; +- gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; +- }; +- +- wan { +- label = "bcm53xx:blue:wan"; +- gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; +- }; +- +- lan { +- label = "bcm53xx:blue:lan"; +- gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; +- }; +- +- power { +- label = "bcm53xx:blue:power"; +- gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- all { +- label = "bcm53xx:blue:all"; +- gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- 2ghz { +- label = "bcm53xx:blue:2ghz"; +- gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; +- }; +- +- +- usb2 { +- label = "bcm53xx:blue:usb2"; +- gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- rfkill { +- label = "WiFi"; +- linux,code = ; +- gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; +- }; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm4708-asus-rt-ac68u.dts b/scripts/dtc/include-prefixes/arm/bcm4708-asus-rt-ac68u.dts +deleted file mode 100644 +index 667b118ba4ee..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm4708-asus-rt-ac68u.dts ++++ /dev/null +@@ -1,85 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Broadcom BCM470X / BCM5301X ARM platform code. +- * DTS for Asus RT-AC68U +- * +- * Copyright (C) 2015 Rafał Miłecki +- */ +- +-/dts-v1/; +- +-#include "bcm4708.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "asus,rt-ac68u", "brcm,bcm4708"; +- model = "Asus RT-AC68U (BCM4708)"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x08000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- usb2 { +- label = "bcm53xx:blue:usb2"; +- gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; +- }; +- +- power { +- label = "bcm53xx:blue:power"; +- gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- logo { +- label = "bcm53xx:white:logo"; +- gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- usb3 { +- label = "bcm53xx:blue:usb3"; +- gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- brightness { +- label = "Backlight"; +- linux,code = ; +- gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; +- }; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; +- }; +- +- rfkill { +- label = "WiFi"; +- linux,code = ; +- gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm4708-buffalo-wzr-1750dhp.dts b/scripts/dtc/include-prefixes/arm/bcm4708-buffalo-wzr-1750dhp.dts +deleted file mode 100644 +index ff31ce45831a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm4708-buffalo-wzr-1750dhp.dts ++++ /dev/null +@@ -1,151 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Broadcom BCM470X / BCM5301X ARM platform code. +- * DTS for Buffalo WZR-1750DHP +- * +- * Copyright (C) 2014 Rafał Miłecki +- */ +- +-/dts-v1/; +- +-#include "bcm4708.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "buffalo,wzr-1750dhp", "brcm,bcm4708"; +- model = "Buffalo WZR-1750DHP (BCM4708)"; +- +- chosen { +- bootargs = "console=ttyS0,115200 earlycon"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x18000000>; +- }; +- +- spi { +- compatible = "spi-gpio"; +- num-chipselects = <1>; +- gpio-sck = <&chipcommon 7 0>; +- gpio-mosi = <&chipcommon 4 0>; +- cs-gpios = <&chipcommon 6 0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- hc595: gpio_spi@0 { +- compatible = "fairchild,74hc595"; +- reg = <0>; +- registers-number = <1>; +- spi-max-frequency = <100000>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- usb { +- label = "bcm53xx:blue:usb"; +- gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; +- trigger-sources = <&ohci_port1>, <&ehci_port1>, +- <&xhci_port1>, <&ohci_port2>, +- <&ehci_port2>; +- linux,default-trigger = "usbport"; +- }; +- +- power0 { +- label = "bcm53xx:red:power"; +- gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; +- }; +- +- power1 { +- label = "bcm53xx:white:power"; +- gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- router0 { +- label = "bcm53xx:blue:router"; +- gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- router1 { +- label = "bcm53xx:amber:router"; +- gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; +- }; +- +- wan { +- label = "bcm53xx:blue:wan"; +- gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- wireless0 { +- label = "bcm53xx:blue:wireless"; +- gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; +- }; +- +- wireless1 { +- label = "bcm53xx:amber:wireless"; +- gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; +- }; +- +- aoss { +- label = "AOSS"; +- linux,code = ; +- gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; +- }; +- +- /* Commit mode set by switch? */ +- mode { +- label = "Mode"; +- linux,code = ; +- gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; +- }; +- +- /* Switch: AP mode */ +- sw_ap { +- label = "AP"; +- linux,code = ; +- gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; +- }; +- +- eject { +- label = "USB eject"; +- linux,code = ; +- gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb2 { +- vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; +-}; +- +-&usb3 { +- vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>; +-}; +- +-&spi_nor { +- status = "okay"; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm4708-linksys-ea6300-v1.dts b/scripts/dtc/include-prefixes/arm/bcm4708-linksys-ea6300-v1.dts +deleted file mode 100644 +index 5bac1e15775a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm4708-linksys-ea6300-v1.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (C) 2017 Rafał Miłecki +- */ +- +-/dts-v1/; +- +-#include "bcm4708.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "linksys,ea6300-v1", "brcm,bcm4708"; +- model = "Linksys EA6300 V1"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +- +- nvram@1c080000 { +- compatible = "brcm,nvram"; +- reg = <0x1c080000 0x180000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm4708-linksys-ea6500-v2.dts b/scripts/dtc/include-prefixes/arm/bcm4708-linksys-ea6500-v2.dts +deleted file mode 100644 +index cd797b4202ad..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm4708-linksys-ea6500-v2.dts ++++ /dev/null +@@ -1,44 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (C) 2017 Rafał Miłecki +- * Copyright (C) 2018 Rene Kjellerup +- */ +- +-/dts-v1/; +- +-#include "bcm4708.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "linksys,ea6500-v2", "brcm,bcm4708"; +- model = "Linksys EA6500 V2"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm4708-luxul-xap-1510.dts b/scripts/dtc/include-prefixes/arm/bcm4708-luxul-xap-1510.dts +deleted file mode 100644 +index 5b4a481be4f4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm4708-luxul-xap-1510.dts ++++ /dev/null +@@ -1,80 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright 2016 Luxul Inc. +- */ +- +-/dts-v1/; +- +-#include "bcm4708.dtsi" +- +-/ { +- compatible = "luxul,xap-1510v1", "brcm,bcm4708"; +- model = "Luxul XAP-1510 V1"; +- +- chosen { +- bootargs = "console=ttyS0,115200 earlycon"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- 5ghz { +- label = "bcm53xx:blue:5ghz"; +- gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "none"; +- }; +- +- 2ghz { +- label = "bcm53xx:blue:2ghz"; +- gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "none"; +- }; +- +- status { +- label = "bcm53xx:green:status"; +- gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "timer"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&spi_nor { +- status = "okay"; +-}; +- +-&srab { +- status = "okay"; +- +- ports { +- port@0 { +- reg = <0>; +- label = "poe"; +- }; +- +- port@4 { +- reg = <4>; +- label = "lan"; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <&gmac0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm4708-luxul-xwc-1000.dts b/scripts/dtc/include-prefixes/arm/bcm4708-luxul-xwc-1000.dts +deleted file mode 100644 +index c81944cd6d0b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm4708-luxul-xwc-1000.dts ++++ /dev/null +@@ -1,82 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Broadcom BCM470X / BCM5301X ARM platform code. +- * DTS for Luxul XWC-1000 +- * +- * Copyright 2014 Luxul Inc. +- */ +- +-/dts-v1/; +- +-#include "bcm4708.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "luxul,xwc-1000", "brcm,bcm4708"; +- model = "Luxul XWC-1000 (BCM4708)"; +- +- chosen { +- bootargs = "console=ttyS0,115200 earlycon"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +- +- nand_controller: nand-controller@18028000 { +- nand@0 { +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "ubi"; +- reg = <0x00000000 0x08000000>; +- }; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- status { +- label = "bcm53xx:green:status"; +- gpios = <&chipcommon 0 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "timer"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&spi_nor { +- status = "okay"; +-}; +- +-&srab { +- status = "okay"; +- +- ports { +- port@4 { +- reg = <4>; +- label = "lan"; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <&gmac0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm4708-netgear-r6250.dts b/scripts/dtc/include-prefixes/arm/bcm4708-netgear-r6250.dts +deleted file mode 100644 +index 7900aac4f35a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm4708-netgear-r6250.dts ++++ /dev/null +@@ -1,96 +0,0 @@ +-/* +- * Broadcom BCM470X / BCM5301X arm platform code. +- * DTS for Netgear R6250 V1 +- * +- * Copyright 2013 Hauke Mehrtens +- * +- * Licensed under the GNU/GPL. See COPYING for details. +- */ +- +-/dts-v1/; +- +-#include "bcm4708.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "netgear,r6250v1", "brcm,bcm4708"; +- model = "Netgear R6250 V1 (BCM4708)"; +- +- chosen { +- bootargs = "console=ttyS0,115200 earlycon"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x08000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- logo { +- label = "bcm53xx:white:logo"; +- gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- power0 { +- label = "bcm53xx:green:power"; +- gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- power1 { +- label = "bcm53xx:amber:power"; +- gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; +- }; +- +- usb { +- label = "bcm53xx:blue:usb"; +- gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; +- trigger-sources = <&ohci_port1>, <&ehci_port1>, +- <&xhci_port1>; +- linux,default-trigger = "usbport"; +- }; +- +- wireless { +- label = "bcm53xx:blue:wireless"; +- gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; +- }; +- +- rfkill { +- label = "WiFi"; +- linux,code = ; +- gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb3 { +- vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; +-}; +- +-&spi_nor { +- status = "okay"; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm4708-netgear-r6300-v2.dts b/scripts/dtc/include-prefixes/arm/bcm4708-netgear-r6300-v2.dts +deleted file mode 100644 +index 4c60eda296d9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm4708-netgear-r6300-v2.dts ++++ /dev/null +@@ -1,88 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Broadcom BCM470X / BCM5301X ARM platform code. +- * DTS for Netgear R6300 V2 +- * +- * Copyright (C) 2014 Rafał Miłecki +- */ +- +-/dts-v1/; +- +-#include "bcm4708.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "netgear,r6300v2", "brcm,bcm4708"; +- model = "Netgear R6300 V2 (BCM4708)"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x08000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- logo { +- label = "bcm53xx:white:logo"; +- gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- power0 { +- label = "bcm53xx:green:power"; +- gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; +- }; +- +- power1 { +- label = "bcm53xx:amber:power"; +- gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- usb { +- label = "bcm53xx:blue:usb"; +- gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; +- }; +- +- wireless { +- label = "bcm53xx:blue:wireless"; +- gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; +- }; +- +- rfkill { +- label = "WiFi"; +- linux,code = ; +- gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&spi_nor { +- status = "okay"; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm4708-smartrg-sr400ac.dts b/scripts/dtc/include-prefixes/arm/bcm4708-smartrg-sr400ac.dts +deleted file mode 100644 +index 9ca6d1b2590d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm4708-smartrg-sr400ac.dts ++++ /dev/null +@@ -1,160 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Broadcom BCM470X / BCM5301X arm platform code. +- * DTS for SmartRG SR400ac +- * +- * Copyright (C) 2015 Rafał Miłecki +- */ +- +-/dts-v1/; +- +-#include "bcm4708.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "smartrg,sr400ac", "brcm,bcm4708"; +- model = "SmartRG SR400ac"; +- +- chosen { +- bootargs = "console=ttyS0,115200 earlycon"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x08000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- power-white { +- label = "bcm53xx:white:power"; +- gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- power-amber { +- label = "bcm53xx:amber:power"; +- gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; +- }; +- +- usb2 { +- label = "bcm53xx:white:usb2"; +- gpios = <&chipcommon 3 GPIO_ACTIVE_HIGH>; +- trigger-sources = <&ohci_port2>, <&ehci_port2>; +- linux,default-trigger = "usbport"; +- }; +- +- usb3-white { +- label = "bcm53xx:white:usb3"; +- gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; +- trigger-sources = <&xhci_port1>; +- linux,default-trigger = "usbport"; +- }; +- +- usb3-green { +- label = "bcm53xx:green:usb3"; +- gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; +- trigger-sources = <&ohci_port1>, <&ehci_port1>; +- linux,default-trigger = "usbport"; +- }; +- +- wps { +- label = "bcm53xx:white:wps"; +- gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; +- }; +- +- status-red { +- label = "bcm53xx:red:status"; +- gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; +- }; +- +- status-green { +- label = "bcm53xx:green:status"; +- gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; +- }; +- +- status-blue { +- label = "bcm53xx:blue:status"; +- gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; +- }; +- +- wan-white { +- label = "bcm53xx:white:wan"; +- gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; +- }; +- +- wan-red { +- label = "bcm53xx:red:wan"; +- gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- rfkill { +- label = "WiFi"; +- linux,code = ; +- gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; +- }; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&spi_nor { +- status = "okay"; +-}; +- +-&srab { +- status = "okay"; +- +- ports { +- port@0 { +- reg = <0>; +- label = "lan4"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan3"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan1"; +- }; +- +- port@4 { +- reg = <4>; +- label = "wan"; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <&gmac0>; +- }; +- }; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm4708.dtsi b/scripts/dtc/include-prefixes/arm/bcm4708.dtsi +deleted file mode 100644 +index 1a19e97a987d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm4708.dtsi ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* +- * Broadcom BCM470X / BCM5301X ARM platform code. +- * DTS for BCM4708 SoC. +- * +- * Copyright 2013-2014 Hauke Mehrtens +- * +- * Licensed under the GNU/GPL. See COPYING for details. +- */ +- +-#include "bcm5301x.dtsi" +- +-/ { +- compatible = "brcm,bcm4708"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "brcm,bcm-nsp-smp"; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- reg = <0x0>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- secondary-boot-reg = <0xffff0400>; +- reg = <0x1>; +- }; +- }; +- +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47081-asus-rt-n18u.dts b/scripts/dtc/include-prefixes/arm/bcm47081-asus-rt-n18u.dts +deleted file mode 100644 +index 0e273c598732..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47081-asus-rt-n18u.dts ++++ /dev/null +@@ -1,79 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Broadcom BCM470X / BCM5301X ARM platform code. +- * DTS for Asus RT-N18U +- * +- * Copyright (C) 2014 Rafał Miłecki +- */ +- +-/dts-v1/; +- +-#include "bcm47081.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "asus,rt-n18u", "brcm,bcm47081", "brcm,bcm4708"; +- model = "Asus RT-N18U (BCM47081)"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x08000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- power { +- label = "bcm53xx:blue:power"; +- gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- usb2 { +- label = "bcm53xx:blue:usb2"; +- gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; +- }; +- +- wan { +- label = "bcm53xx:blue:wan"; +- gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- lan { +- label = "bcm53xx:blue:lan"; +- gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- usb3 { +- label = "bcm53xx:blue:usb3"; +- gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; +- }; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47081-buffalo-wzr-600dhp2.dts b/scripts/dtc/include-prefixes/arm/bcm47081-buffalo-wzr-600dhp2.dts +deleted file mode 100644 +index d857751ec507..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47081-buffalo-wzr-600dhp2.dts ++++ /dev/null +@@ -1,119 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Broadcom BCM470X / BCM5301X ARM platform code. +- * DTS for Buffalo WZR-600DHP2 +- * +- * Copyright (C) 2014 Rafał Miłecki +- */ +- +-/dts-v1/; +- +-#include "bcm47081.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "buffalo,wzr-600dhp2", "brcm,bcm47081", "brcm,bcm4708"; +- model = "Buffalo WZR-600DHP2 (BCM47081)"; +- +- chosen { +- bootargs = "console=ttyS0,115200 earlycon"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x08000000>; +- }; +- +- spi { +- compatible = "spi-gpio"; +- num-chipselects = <1>; +- gpio-sck = <&chipcommon 7 0>; +- gpio-mosi = <&chipcommon 4 0>; +- cs-gpios = <&chipcommon 6 0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- hc595: gpio_spi@0 { +- compatible = "fairchild,74hc595"; +- reg = <0>; +- registers-number = <1>; +- spi-max-frequency = <100000>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- power0 { +- label = "bcm53xx:green:power"; +- gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- power1 { +- label = "bcm53xx:red:power"; +- gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; +- }; +- +- router0 { +- label = "bcm53xx:green:router"; +- gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- router1 { +- label = "bcm53xx:amber:router"; +- gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; +- }; +- +- wan { +- label = "bcm53xx:green:wan"; +- gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- wireless0 { +- label = "bcm53xx:green:wireless"; +- gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; +- }; +- +- wireless1 { +- label = "bcm53xx:amber:wireless"; +- gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- aoss { +- label = "AOSS"; +- linux,code = ; +- gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; +- }; +- +- /* Switch device mode? */ +- mode { +- label = "Mode"; +- linux,code = ; +- gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; +- }; +- +- eject { +- label = "USB eject"; +- linux,code = ; +- gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47081-buffalo-wzr-900dhp.dts b/scripts/dtc/include-prefixes/arm/bcm47081-buffalo-wzr-900dhp.dts +deleted file mode 100644 +index 8b1a05a0f1a1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47081-buffalo-wzr-900dhp.dts ++++ /dev/null +@@ -1,109 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Broadcom BCM470X / BCM5301X ARM platform code. +- * DTS for Buffalo WZR-900DHP +- * +- * Copyright (C) 2015 Rafał Miłecki +- */ +- +-/dts-v1/; +- +-#include "bcm47081.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "buffalo,wzr-900dhp", "brcm,bcm47081", "brcm,bcm4708"; +- model = "Buffalo WZR-900DHP (BCM47081)"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x08000000>; +- }; +- +- spi { +- compatible = "spi-gpio"; +- num-chipselects = <1>; +- gpio-sck = <&chipcommon 7 0>; +- gpio-mosi = <&chipcommon 4 0>; +- cs-gpios = <&chipcommon 6 0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- hc595: gpio_spi@0 { +- compatible = "fairchild,74hc595"; +- reg = <0>; +- registers-number = <1>; +- spi-max-frequency = <100000>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- usb { +- label = "bcm53xx:green:usb"; +- gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; +- }; +- +- power0 { +- label = "bcm53xx:green:power"; +- gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- power1 { +- label = "bcm53xx:red:power"; +- gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; +- }; +- +- router0 { +- label = "bcm53xx:green:router"; +- gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- router1 { +- label = "bcm53xx:amber:router"; +- gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; +- }; +- +- wan { +- label = "bcm53xx:green:wan"; +- gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- wireless0 { +- label = "bcm53xx:green:wireless"; +- gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; +- }; +- +- wireless1 { +- label = "bcm53xx:amber:wireless"; +- gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47081-luxul-xap-1410.dts b/scripts/dtc/include-prefixes/arm/bcm47081-luxul-xap-1410.dts +deleted file mode 100644 +index 68aaf0af3945..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47081-luxul-xap-1410.dts ++++ /dev/null +@@ -1,75 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright 2017 Luxul Inc. +- */ +- +-/dts-v1/; +- +-#include "bcm47081.dtsi" +- +-/ { +- compatible = "luxul,xap-1410v1", "brcm,bcm47081", "brcm,bcm4708"; +- model = "Luxul XAP-1410 V1"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- 5ghz { +- label = "bcm53xx:blue:5ghz"; +- gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "none"; +- }; +- +- 2ghz { +- label = "bcm53xx:blue:2ghz"; +- gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "none"; +- }; +- +- status { +- label = "bcm53xx:green:status"; +- gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "timer"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&spi_nor { +- status = "okay"; +-}; +- +-&srab { +- status = "okay"; +- +- ports { +- port@4 { +- reg = <4>; +- label = "poe"; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <&gmac0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47081-luxul-xwr-1200.dts b/scripts/dtc/include-prefixes/arm/bcm47081-luxul-xwr-1200.dts +deleted file mode 100644 +index 9316a36434f7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47081-luxul-xwr-1200.dts ++++ /dev/null +@@ -1,148 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright 2017 Luxul Inc. +- */ +- +-/dts-v1/; +- +-#include "bcm47081.dtsi" +-#include "bcm5301x-nand-cs0-bch4.dtsi" +- +-/ { +- compatible = "luxul,xwr-1200v1", "brcm,bcm47081", "brcm,bcm4708"; +- model = "Luxul XWR-1200 V1"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +- +- nvram@1eff0000 { +- compatible = "brcm,nvram"; +- reg = <0x1eff0000 0x10000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- power { +- label = "bcm53xx:green:power"; +- gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- lan3 { +- label = "bcm53xx:green:lan3"; +- gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "none"; +- }; +- +- lan4 { +- label = "bcm53xx:green:lan4"; +- gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "none"; +- }; +- +- wan { +- label = "bcm53xx:green:wan"; +- gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "none"; +- }; +- +- lan2 { +- label = "bcm53xx:green:lan2"; +- gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "none"; +- }; +- +- usb { +- label = "bcm53xx:green:usb"; +- gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; +- trigger-sources = <&ohci_port2>, <&ehci_port2>; +- linux,default-trigger = "usbport"; +- }; +- +- status { +- label = "bcm53xx:green:status"; +- gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "timer"; +- }; +- +- 2ghz { +- label = "bcm53xx:green:2ghz"; +- gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "none"; +- }; +- +- 5ghz { +- label = "bcm53xx:green:5ghz"; +- gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "none"; +- }; +- +- lan1 { +- label = "bcm53xx:green:lan1"; +- gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "none"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb2 { +- vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; +-}; +- +-&spi_nor { +- status = "okay"; +-}; +- +-&srab { +- status = "okay"; +- +- ports { +- port@0 { +- reg = <0>; +- label = "lan4"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan3"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan1"; +- }; +- +- port@4 { +- reg = <4>; +- label = "wan"; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <&gmac0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47081-tplink-archer-c5-v2.dts b/scripts/dtc/include-prefixes/arm/bcm47081-tplink-archer-c5-v2.dts +deleted file mode 100644 +index 12e34a0439b4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47081-tplink-archer-c5-v2.dts ++++ /dev/null +@@ -1,128 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (C) 2017 Rafał Miłecki +- */ +- +-/dts-v1/; +- +-#include "bcm47081.dtsi" +- +-/ { +- compatible = "tplink,archer-c5-v2", "brcm,bcm47081", "brcm,bcm4708"; +- model = "TP-LINK Archer C5 V2"; +- +- chosen { +- bootargs = "earlycon"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- 2ghz { +- label = "bcm53xx:green:2ghz"; +- gpios = <&chipcommon 0 GPIO_ACTIVE_HIGH>; +- }; +- +- lan { +- label = "bcm53xx:green:lan"; +- gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; +- }; +- +- usb2-port1 { +- label = "bcm53xx:green:usb2-port1"; +- gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; +- trigger-sources = <&ohci_port1>, <&ehci_port1>; +- linux,default-trigger = "usbport"; +- }; +- +- power { +- label = "bcm53xx:green:power"; +- gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- wan-green { +- label = "bcm53xx:green:wan"; +- gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; +- }; +- +- wps { +- label = "bcm53xx:green:wps"; +- gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; +- }; +- +- wan-amber { +- label = "bcm53xx:amber:wan"; +- gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; +- }; +- +- 5ghz { +- label = "bcm53xx:green:5ghz"; +- gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; +- }; +- +- usb2-port2 { +- label = "bcm53xx:green:usb2-port2"; +- gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; +- trigger-sources = <&ohci_port2>, <&ehci_port2>; +- linux,default-trigger = "usbport"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- rfkill { +- label = "WiFi"; +- linux,code = ; +- gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&spi_nor { +- status = "okay"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- boot@0 { +- label = "boot"; +- reg = <0x000000 0x040000>; +- read-only; +- }; +- +- os-image@100000 { +- label = "os-image"; +- reg = <0x040000 0x200000>; +- compatible = "brcm,trx"; +- }; +- +- rootfs@240000 { +- label = "rootfs"; +- reg = <0x240000 0xc00000>; +- }; +- +- nvram@ff0000 { +- label = "nvram"; +- reg = <0xff0000 0x010000>; +- }; +- }; +-}; +- +-&usb2 { +- vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47081.dtsi b/scripts/dtc/include-prefixes/arm/bcm47081.dtsi +deleted file mode 100644 +index ed13af028528..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47081.dtsi ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Broadcom BCM470X / BCM5301X ARM platform code. +- * DTS for BCM47081 SoC. +- * +- * Copyright © 2014 Rafał Miłecki +- */ +- +-#include "bcm5301x.dtsi" +- +-/ { +- compatible = "brcm,bcm47081"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- reg = <0x0>; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm4709-asus-rt-ac87u.dts b/scripts/dtc/include-prefixes/arm/bcm4709-asus-rt-ac87u.dts +deleted file mode 100644 +index 7546c8d07bcd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm4709-asus-rt-ac87u.dts ++++ /dev/null +@@ -1,100 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Broadcom BCM470X / BCM5301X ARM platform code. +- * DTS for Asus RT-AC87U +- * +- * Copyright (C) 2015 Rafał Miłecki +- */ +- +-/dts-v1/; +- +-#include "bcm4709.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "asus,rt-ac87u", "brcm,bcm4709", "brcm,bcm4708"; +- model = "Asus RT-AC87U"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x08000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- wps { +- label = "bcm53xx:blue:wps"; +- gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; +- }; +- +- power { +- label = "bcm53xx:blue:power"; +- gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- wan { +- label = "bcm53xx:red:wan"; +- gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +- +-&nandcs { +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- boot@0 { +- label = "boot"; +- reg = <0x00000000 0x00080000>; +- read-only; +- }; +- +- nvram@80000 { +- label = "nvram"; +- reg = <0x00080000 0x00180000>; +- }; +- +- firmware@200000 { +- label = "firmware"; +- reg = <0x00200000 0x07cc0000>; +- compatible = "brcm,trx"; +- }; +- +- asus@7ec0000 { +- label = "asus"; +- reg = <0x07ec0000 0x00140000>; +- read-only; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm4709-buffalo-wxr-1900dhp.dts b/scripts/dtc/include-prefixes/arm/bcm4709-buffalo-wxr-1900dhp.dts +deleted file mode 100644 +index beae9eab9cb8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm4709-buffalo-wxr-1900dhp.dts ++++ /dev/null +@@ -1,134 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Broadcom BCM470X / BCM5301X ARM platform code. +- * DTS for Buffalo WXR-1900DHP +- * +- * Copyright (C) 2015 Felix Fietkau +- */ +- +-/dts-v1/; +- +-#include "bcm4709.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "buffalo,wxr-1900dhp", "brcm,bcm4709", "brcm,bcm4708"; +- model = "Buffalo WXR-1900DHP"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x18000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- usb { +- label = "bcm53xx:green:usb"; +- gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; +- }; +- +- power-amber { +- label = "bcm53xx:amber:power"; +- gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; +- }; +- +- power-white { +- label = "bcm53xx:white:power"; +- gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- router-amber { +- label = "bcm53xx:amber:router"; +- gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; +- }; +- +- router-white { +- label = "bcm53xx:white:router"; +- gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; +- }; +- +- wan-amber { +- label = "bcm53xx:amber:wan"; +- gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; +- }; +- +- wan-white { +- label = "bcm53xx:white:wan"; +- gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; +- }; +- +- wireless-amber { +- label = "bcm53xx:amber:wireless"; +- gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; +- }; +- +- wireless-white { +- label = "bcm53xx:white:wireless"; +- gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- power { +- label = "Power"; +- linux,code = ; +- gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; +- }; +- +- aoss { +- label = "AOSS"; +- linux,code = ; +- gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; +- }; +- +- /* Commit mode set by switch? */ +- mode { +- label = "Mode"; +- linux,code = ; +- gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; +- }; +- +- /* Switch: AP mode */ +- sw_ap { +- label = "AP"; +- linux,code = ; +- gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; +- }; +- +- eject { +- label = "USB eject"; +- linux,code = ; +- gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +- +-&usb2 { +- vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; +-}; +- +-&spi_nor { +- status = "okay"; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm4709-linksys-ea9200.dts b/scripts/dtc/include-prefixes/arm/bcm4709-linksys-ea9200.dts +deleted file mode 100644 +index 7879f7d7d9c3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm4709-linksys-ea9200.dts ++++ /dev/null +@@ -1,51 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (C) 2017 Rafał Miłecki +- */ +- +-/dts-v1/; +- +-#include "bcm4709.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "linksys,ea9200", "brcm,bcm4709", "brcm,bcm4708"; +- model = "Linksys EA9200"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x08000000>; +- }; +- +- nvram@1c080000 { +- compatible = "brcm,nvram"; +- reg = <0x1c080000 0x180000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm4709-netgear-r7000.dts b/scripts/dtc/include-prefixes/arm/bcm4709-netgear-r7000.dts +deleted file mode 100644 +index 56d309dbc6b0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm4709-netgear-r7000.dts ++++ /dev/null +@@ -1,108 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Broadcom BCM470X / BCM5301X ARM platform code. +- * DTS for Netgear R7000 +- * +- * Copyright (C) 2015 Rafał Miłecki +- */ +- +-/dts-v1/; +- +-#include "bcm4709.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "netgear,r7000", "brcm,bcm4709", "brcm,bcm4708"; +- model = "Netgear R7000"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x08000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- power-white { +- label = "bcm53xx:white:power"; +- gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- power-amber { +- label = "bcm53xx:amber:power"; +- gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; +- }; +- +- 5ghz { +- label = "bcm53xx:white:5ghz"; +- gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; +- }; +- +- 2ghz { +- label = "bcm53xx:white:2ghz"; +- gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; +- }; +- +- wps { +- label = "bcm53xx:white:wps"; +- gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; +- }; +- +- wireless { +- label = "bcm53xx:white:wireless"; +- gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; +- }; +- +- usb3 { +- label = "bcm53xx:white:usb3"; +- gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; +- }; +- +- usb2 { +- label = "bcm53xx:white:usb2"; +- gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; +- }; +- +- rfkill { +- label = "WiFi"; +- linux,code = ; +- gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb2 { +- vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; +-}; +- +-&usb3 { +- vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm4709-netgear-r8000.dts b/scripts/dtc/include-prefixes/arm/bcm4709-netgear-r8000.dts +deleted file mode 100644 +index 184e3039aa86..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm4709-netgear-r8000.dts ++++ /dev/null +@@ -1,189 +0,0 @@ +-/* +- * Broadcom BCM470X / BCM5301X ARM platform code. +- * DTS for Netgear R8000 +- * +- * Copyright (C) 2015 Rafał Miłecki +- * +- * Permission to use, copy, modify, and/or distribute this software for any +- * purpose with or without fee is hereby granted, provided that the above +- * copyright notice and this permission notice appear in all copies. +- * +- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH +- * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +- * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, +- * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM +- * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE +- * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +- * PERFORMANCE OF THIS SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include "bcm4709.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "netgear,r8000", "brcm,bcm4709", "brcm,bcm4708"; +- model = "Netgear R8000 (BCM4709)"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x08000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- power-white { +- label = "bcm53xx:white:power"; +- gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- power-amber { +- label = "bcm53xx:amber:power"; +- gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; +- }; +- +- wan-white { +- label = "bcm53xx:white:wan"; +- gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- wan-amber { +- label = "bcm53xx:amber:wan"; +- gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; +- }; +- +- 5ghz-1 { +- label = "bcm53xx:white:5ghz-1"; +- gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; +- }; +- +- 2ghz { +- label = "bcm53xx:white:2ghz"; +- gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; +- }; +- +- wireless { +- label = "bcm53xx:white:wireless"; +- gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; +- }; +- +- wps { +- label = "bcm53xx:white:wps"; +- gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; +- }; +- +- 5ghz-2 { +- label = "bcm53xx:white:5ghz-2"; +- gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; +- }; +- +- usb3 { +- label = "bcm53xx:white:usb3"; +- gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; +- }; +- +- usb2 { +- label = "bcm53xx:white:usb2"; +- gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rfkill { +- label = "WiFi"; +- linux,code = ; +- gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; +- }; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; +- }; +- +- brightness { +- label = "Backlight"; +- linux,code = ; +- gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&pcie0 { +- #address-cells = <3>; +- #size-cells = <2>; +- +- bridge@0,0,0 { +- reg = <0x0000 0 0 0 0>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- wifi@0,1,0 { +- reg = <0x0000 0 0 0 0>; +- ieee80211-freq-limit = <5735000 5835000>; +- }; +- }; +-}; +- +-&pcie1 { +- #address-cells = <3>; +- #size-cells = <2>; +- +- bridge@1,0,0 { +- reg = <0x0000 0 0 0 0>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- bridge@1,1,0 { +- reg = <0x0000 0 0 0 0>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- bridge@1,2,2 { +- reg = <0x1000 0 0 0 0>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- wifi@1,4,0 { +- reg = <0x0000 0 0 0 0>; +- ieee80211-freq-limit = <5170000 5730000>; +- }; +- }; +- }; +- }; +-}; +- +-&usb2 { +- vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; +-}; +- +-&usb3 { +- vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm4709-tplink-archer-c9-v1.dts b/scripts/dtc/include-prefixes/arm/bcm4709-tplink-archer-c9-v1.dts +deleted file mode 100644 +index c2a266a439d0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm4709-tplink-archer-c9-v1.dts ++++ /dev/null +@@ -1,139 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (C) 2016 Rafał Miłecki +- */ +- +-/dts-v1/; +- +-#include "bcm4709.dtsi" +- +-/ { +- compatible = "tplink,archer-c9-v1", "brcm,bcm4709", "brcm,bcm4708"; +- model = "TP-LINK Archer C9 V1"; +- +- chosen { +- bootargs = "console=ttyS0,115200 earlycon"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- lan { +- label = "bcm53xx:blue:lan"; +- gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; +- }; +- +- wps { +- label = "bcm53xx:blue:wps"; +- gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; +- }; +- +- 2ghz { +- label = "bcm53xx:blue:2ghz"; +- gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; +- }; +- +- 5ghz { +- label = "bcm53xx:blue:5ghz"; +- gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; +- }; +- +- usb3 { +- label = "bcm53xx:blue:usb3"; +- gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; +- trigger-sources = <&ohci_port1>, <&ehci_port1>, +- <&xhci_port1>; +- linux,default-trigger = "usbport"; +- }; +- +- usb2 { +- label = "bcm53xx:blue:usb2"; +- gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; +- trigger-sources = <&ohci_port2>, <&ehci_port2>; +- linux,default-trigger = "usbport"; +- }; +- +- wan-blue { +- label = "bcm53xx:blue:wan"; +- gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; +- }; +- +- wan-amber { +- label = "bcm53xx:amber:wan"; +- gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; +- }; +- +- power { +- label = "bcm53xx:blue:power"; +- gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb2 { +- vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; +-}; +- +-&usb3 { +- vcc-gpio = <&chipcommon 12 GPIO_ACTIVE_HIGH>; +-}; +- +-&spi_nor { +- status = "okay"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- boot@0 { +- label = "boot"; +- reg = <0x000000 0x040000>; +- read-only; +- }; +- +- os-image@100000 { +- label = "os-image"; +- reg = <0x040000 0x200000>; +- compatible = "brcm,trx"; +- }; +- +- rootfs@240000 { +- label = "rootfs"; +- reg = <0x240000 0xc00000>; +- }; +- +- nvram@ff0000 { +- label = "nvram"; +- reg = <0xff0000 0x010000>; +- }; +- }; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm4709.dtsi b/scripts/dtc/include-prefixes/arm/bcm4709.dtsi +deleted file mode 100644 +index cba3d910bed8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm4709.dtsi ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (C) 2016 Rafał Miłecki +- */ +- +-#include "bcm4708.dtsi" +- +-&uart0 { +- clock-frequency = <125000000>; +- status = "okay"; +-}; +- +-&srab { +- compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47094-dlink-dir-885l.dts b/scripts/dtc/include-prefixes/arm/bcm47094-dlink-dir-885l.dts +deleted file mode 100644 +index a6e2aeb28675..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47094-dlink-dir-885l.dts ++++ /dev/null +@@ -1,120 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Broadcom BCM470X / BCM5301X ARM platform code. +- * DTS for D-Link DIR-885L +- * +- * Copyright (C) 2016 Rafał Miłecki +- */ +- +-/dts-v1/; +- +-#include "bcm47094.dtsi" +-#include "bcm5301x-nand-cs0-bch1.dtsi" +- +-/ { +- compatible = "dlink,dir-885l", "brcm,bcm47094", "brcm,bcm4708"; +- model = "D-Link DIR-885L"; +- +- chosen { +- bootargs = "console=ttyS0,115200 earlycon"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x08000000>; +- }; +- +- nand_controller: nand-controller@18028000 { +- nand@0 { +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "firmware"; +- reg = <0x00000000 0x08000000>; +- }; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- power-white { +- label = "bcm53xx:white:power"; +- gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- wan-white { +- label = "bcm53xx:white:wan"; +- gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; +- }; +- +- power-amber { +- label = "bcm53xx:amber:power"; +- gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; +- }; +- +- wan-amber { +- label = "bcm53xx:amber:wan"; +- gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; +- }; +- +- usb3-white { +- label = "bcm53xx:white:usb3"; +- gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; +- trigger-sources = <&ohci_port1>, <&ehci_port1>, +- <&xhci_port1>; +- linux,default-trigger = "usbport"; +- }; +- +- 2ghz { +- label = "bcm53xx:white:2ghz"; +- gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; +- }; +- +- 5ghz { +- label = "bcm53xx:white:5ghz"; +- gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; +- }; +- +- /* Switch: router / extender */ +- extender { +- label = "Extender"; +- linux,code = ; +- gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb3 { +- vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +-}; +- +-&spi_nor { +- status = "okay"; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47094-linksys-panamera.dts b/scripts/dtc/include-prefixes/arm/bcm47094-linksys-panamera.dts +deleted file mode 100644 +index 9bef6b9bfa8d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47094-linksys-panamera.dts ++++ /dev/null +@@ -1,318 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (C) 2017 Rafał Miłecki +- */ +- +-/dts-v1/; +- +-#include "bcm47094.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "linksys,panamera", "brcm,bcm47094", "brcm,bcm4708"; +- model = "Linksys EA9500"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x08000000>; +- }; +- +- nvram@1c080000 { +- compatible = "brcm,nvram"; +- reg = <0x1c080000 0x100000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; +- }; +- +- rfkill { +- label = "WiFi"; +- linux,code = ; +- gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; +- }; +- +- reset { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- wps { +- label = "bcm53xx:white:wps"; +- gpios = <&chipcommon 22 GPIO_ACTIVE_LOW>; +- }; +- +- usb2 { +- label = "bcm53xx:green:usb2"; +- gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; +- trigger-sources = <&ohci_port2>, <&ehci_port2>; +- linux,default-trigger = "usbport"; +- }; +- +- usb3 { +- label = "bcm53xx:green:usb3"; +- gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; +- trigger-sources = <&ohci_port1>, <&ehci_port1>, +- <&xhci_port1>; +- linux,default-trigger = "usbport"; +- }; +- +- power { +- label = "bcm53xx:white:power"; +- gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- wifi-disabled { +- label = "bcm53xx:amber:wifi-disabled"; +- gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; +- }; +- +- wifi-enabled { +- label = "bcm53xx:white:wifi-enabled"; +- gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; +- }; +- +- bluebar1 { +- label = "bcm53xx:white:bluebar1"; +- gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; +- }; +- +- bluebar2 { +- label = "bcm53xx:white:bluebar2"; +- gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; +- }; +- +- bluebar3 { +- label = "bcm53xx:white:bluebar3"; +- gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; +- }; +- +- bluebar4 { +- label = "bcm53xx:white:bluebar4"; +- gpios = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +- }; +- +- bluebar5 { +- label = "bcm53xx:white:bluebar5"; +- gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; +- }; +- +- bluebar6 { +- label = "bcm53xx:white:bluebar6"; +- gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; +- }; +- +- bluebar7 { +- label = "bcm53xx:white:bluebar7"; +- gpios = <&chipcommon 21 GPIO_ACTIVE_HIGH>; +- }; +- +- bluebar8 { +- label = "bcm53xx:white:bluebar8"; +- gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- mdio-mux@18003000 { +- +- /* BIT(9) = 1 => external mdio */ +- mdio@200 { +- reg = <0x200>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch@0 { +- compatible = "brcm,bcm53125"; +- #address-cells = <1>; +- #size-cells = <0>; +- reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; +- reset-names = "robo_reset"; +- reg = <0>; +- dsa,member = <1 0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinmux_mdio>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan1"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan5"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan6"; +- }; +- +- port@4 { +- reg = <4>; +- label = "lan3"; +- }; +- +- sw1_p8: port@8 { +- reg = <8>; +- ethernet = <&sw0_p0>; +- label = "cpu"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&usb2 { +- vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; +-}; +- +-&usb3 { +- vcc-gpio = <&chipcommon 14 GPIO_ACTIVE_HIGH>; +-}; +- +-&srab { +- compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; +- status = "okay"; +- dsa,member = <0 0>; +- +- ports { +- port@1 { +- reg = <1>; +- label = "lan7"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan4"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan8"; +- }; +- +- port@4 { +- reg = <4>; +- label = "wan"; +- }; +- +- port@5 { +- reg = <5>; +- ethernet = <&gmac0>; +- label = "cpu"; +- status = "disabled"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- port@7 { +- reg = <7>; +- ethernet = <&gmac1>; +- label = "cpu"; +- status = "disabled"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- port@8 { +- reg = <8>; +- ethernet = <&gmac2>; +- label = "cpu"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- sw0_p0: port@0 { +- reg = <0>; +- label = "extsw"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +- +-&nandcs { +- partitions { +- compatible = "linksys,ns-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "boot"; +- reg = <0x0000000 0x0080000>; +- read-only; +- }; +- +- partition@80000 { +- label = "nvram"; +- reg = <0x080000 0x0100000>; +- }; +- +- partition@180000{ +- label = "devinfo"; +- reg = <0x0180000 0x080000>; +- }; +- +- partition@200000 { +- reg = <0x0200000 0x01d00000>; +- compatible = "linksys,ns-firmware", "brcm,trx"; +- }; +- +- partition@1f00000 { +- reg = <0x01f00000 0x01d00000>; +- compatible = "linksys,ns-firmware", "brcm,trx"; +- }; +- +- partition@5200000 { +- label = "system"; +- reg = <0x05200000 0x02e00000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47094-luxul-abr-4500.dts b/scripts/dtc/include-prefixes/arm/bcm47094-luxul-abr-4500.dts +deleted file mode 100644 +index 4b8117f32d26..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47094-luxul-abr-4500.dts ++++ /dev/null +@@ -1,70 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (C) 2017 Luxul Inc. +- */ +- +-/dts-v1/; +- +-#include "bcm4708.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "luxul,abr-4500-v1", "brcm,bcm47094", "brcm,bcm4708"; +- model = "Luxul ABR-4500 V1"; +- +- chosen { +- bootargs = "earlycon"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x18000000>; +- }; +- +- nvram@1eff0000 { +- compatible = "brcm,nvram"; +- reg = <0x1eff0000 0x10000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- status { +- label = "bcm53xx:green:status"; +- gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "timer"; +- }; +- +- usb3 { +- label = "bcm53xx:green:usb3"; +- gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; +- trigger-sources = <&ohci_port1>, <&ehci_port1>, +- <&xhci_port1>; +- linux,default-trigger = "usbport"; +- }; +- +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb3 { +- vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +-}; +- +-&spi_nor { +- status = "okay"; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47094-luxul-xap-1610.dts b/scripts/dtc/include-prefixes/arm/bcm47094-luxul-xap-1610.dts +deleted file mode 100644 +index 6fa101f0a90d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47094-luxul-xap-1610.dts ++++ /dev/null +@@ -1,78 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright 2018 Luxul Inc. +- */ +- +-/dts-v1/; +- +-#include "bcm47094.dtsi" +- +-/ { +- compatible = "luxul,xap-1610-v1", "brcm,bcm47094", "brcm,bcm4708"; +- model = "Luxul XAP-1610 V1"; +- +- chosen { +- bootargs = "earlycon"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- status { +- label = "bcm53xx:green:status"; +- gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "timer"; +- }; +- +- 2ghz { +- label = "bcm53xx:blue:2ghz"; +- gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; +- }; +- +- 5ghz { +- label = "bcm53xx:blue:5ghz"; +- gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&spi_nor { +- status = "okay"; +-}; +- +-&srab { +- status = "okay"; +- +- ports { +- port@0 { +- reg = <0>; +- label = "poe"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan"; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <&gmac0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47094-luxul-xbr-4500.dts b/scripts/dtc/include-prefixes/arm/bcm47094-luxul-xbr-4500.dts +deleted file mode 100644 +index 5fecce0422c7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47094-luxul-xbr-4500.dts ++++ /dev/null +@@ -1,70 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (C) 2017 Luxul Inc. +- */ +- +-/dts-v1/; +- +-#include "bcm4708.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "luxul,xbr-4500-v1", "brcm,bcm47094", "brcm,bcm4708"; +- model = "Luxul XBR-4500 V1"; +- +- chosen { +- bootargs = "earlycon"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x18000000>; +- }; +- +- nvram@1eff0000 { +- compatible = "brcm,nvram"; +- reg = <0x1eff0000 0x10000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- status { +- label = "bcm53xx:green:status"; +- gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "timer"; +- }; +- +- usb3 { +- label = "bcm53xx:green:usb3"; +- gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; +- trigger-sources = <&ohci_port1>, <&ehci_port1>, +- <&xhci_port1>; +- linux,default-trigger = "usbport"; +- }; +- +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb3 { +- vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +-}; +- +-&spi_nor { +- status = "okay"; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47094-luxul-xwc-2000.dts b/scripts/dtc/include-prefixes/arm/bcm47094-luxul-xwc-2000.dts +deleted file mode 100644 +index b0d8a688141d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47094-luxul-xwc-2000.dts ++++ /dev/null +@@ -1,71 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright 2019 Legrand AV Inc. +- */ +- +-/dts-v1/; +- +-#include "bcm47094.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "luxul,xwc-2000-v1", "brcm,bcm47094", "brcm,bcm4708"; +- model = "Luxul XWC-2000 V1"; +- +- chosen { +- bootargs = "earlycon"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x18000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- status { +- label = "bcm53xx:green:status"; +- gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "timer"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&spi_nor { +- status = "okay"; +-}; +- +-&srab { +- status = "okay"; +- +- ports { +- port@0 { +- reg = <0>; +- label = "lan"; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <&gmac0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47094-luxul-xwr-3100.dts b/scripts/dtc/include-prefixes/arm/bcm47094-luxul-xwr-3100.dts +deleted file mode 100644 +index cbe8c8e4a301..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47094-luxul-xwr-3100.dts ++++ /dev/null +@@ -1,147 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright 2016 Luxul Inc. +- */ +- +-/dts-v1/; +- +-#include "bcm47094.dtsi" +-#include "bcm5301x-nand-cs0-bch4.dtsi" +- +-/ { +- compatible = "luxul,xwr-3100v1", "brcm,bcm47094", "brcm,bcm4708"; +- model = "Luxul XWR-3100 V1"; +- +- chosen { +- bootargs = "console=ttyS0,115200 earlycon"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x08000000>; +- }; +- +- nvram@1eff0000 { +- compatible = "brcm,nvram"; +- reg = <0x1eff0000 0x10000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- power { +- label = "bcm53xx:green:power"; +- gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- lan3 { +- label = "bcm53xx:green:lan3"; +- gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; +- }; +- +- lan4 { +- label = "bcm53xx:green:lan4"; +- gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; +- }; +- +- wan { +- label = "bcm53xx:green:wan"; +- gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; +- }; +- +- lan1 { +- label = "bcm53xx:green:lan1"; +- gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; +- }; +- +- lan2 { +- label = "bcm53xx:green:lan2"; +- gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; +- }; +- +- usb3 { +- label = "bcm53xx:green:usb3"; +- gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; +- trigger-sources = <&ohci_port1>, <&ehci_port1>, +- <&xhci_port1>; +- linux,default-trigger = "usbport"; +- }; +- +- status { +- label = "bcm53xx:green:status"; +- gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "timer"; +- }; +- +- 2ghz { +- label = "bcm53xx:green:2ghz"; +- gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; +- }; +- +- 5ghz { +- label = "bcm53xx:green:5ghz"; +- gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb3 { +- vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +-}; +- +-&spi_nor { +- status = "okay"; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +- +-&srab { +- status = "okay"; +- +- ports { +- port@0 { +- reg = <0>; +- label = "lan4"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan3"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan1"; +- }; +- +- port@4 { +- reg = <4>; +- label = "wan"; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <&gmac0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47094-luxul-xwr-3150-v1.dts b/scripts/dtc/include-prefixes/arm/bcm47094-luxul-xwr-3150-v1.dts +deleted file mode 100644 +index 24ae3c8a3e09..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47094-luxul-xwr-3150-v1.dts ++++ /dev/null +@@ -1,122 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright 2018 Luxul Inc. +- */ +- +-/dts-v1/; +- +-#include "bcm47094.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "luxul,xwr-3150-v1", "brcm,bcm47094", "brcm,bcm4708"; +- model = "Luxul XWR-3150 V1"; +- +- chosen { +- bootargs = "earlycon"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x18000000>; +- }; +- +- nvram@1eff0000 { +- compatible = "brcm,nvram"; +- reg = <0x1eff0000 0x10000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- power { +- label = "bcm53xx:green:power"; +- gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- usb3 { +- label = "bcm53xx:green:usb3"; +- gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; +- trigger-sources = <&ohci_port1>, <&ehci_port1>, +- <&xhci_port1>; +- linux,default-trigger = "usbport"; +- }; +- +- status { +- label = "bcm53xx:green:status"; +- gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "timer"; +- }; +- +- 2ghz { +- label = "bcm53xx:green:2ghz"; +- gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; +- }; +- +- 5ghz { +- label = "bcm53xx:green:5ghz"; +- gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb3 { +- vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +- +-&spi_nor { +- status = "okay"; +-}; +- +-&srab { +- status = "okay"; +- +- ports { +- port@0 { +- reg = <0>; +- label = "lan4"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan3"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan1"; +- }; +- +- port@4 { +- reg = <4>; +- label = "wan"; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <&gmac0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47094-netgear-r8500.dts b/scripts/dtc/include-prefixes/arm/bcm47094-netgear-r8500.dts +deleted file mode 100644 +index 42097a4c2659..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47094-netgear-r8500.dts ++++ /dev/null +@@ -1,96 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (C) 2016 Rafał Miłecki +- */ +- +-/dts-v1/; +- +-#include "bcm47094.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- compatible = "netgear,r8500", "brcm,bcm47094", "brcm,bcm4708"; +- model = "Netgear R8500"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x18000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- power0 { +- label = "bcm53xx:white:power"; +- gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- power1 { +- label = "bcm53xx:amber:power"; +- gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; +- }; +- +- 5ghz-1 { +- label = "bcm53xx:white:5ghz-1"; +- gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; +- }; +- +- 5ghz-2 { +- label = "bcm53xx:white:5ghz-2"; +- gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; +- }; +- +- 2ghz { +- label = "bcm53xx:white:2ghz"; +- gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; +- }; +- +- usb2 { +- label = "bcm53xx:white:usb2"; +- gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; +- }; +- +- usb3 { +- label = "bcm53xx:white:usb3"; +- gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- brightness { +- label = "Backlight"; +- linux,code = ; +- gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; +- }; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; +- }; +- +- rfkill { +- label = "WiFi"; +- linux,code = ; +- gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47094-phicomm-k3.dts b/scripts/dtc/include-prefixes/arm/bcm47094-phicomm-k3.dts +deleted file mode 100644 +index a2566ad4619c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47094-phicomm-k3.dts ++++ /dev/null +@@ -1,70 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (C) 2017 Hamster Tian +- * Copyright (C) 2019 Hao Dong +- */ +- +-/dts-v1/; +- +-#include "bcm47094.dtsi" +-#include "bcm5301x-nand-cs0-bch4.dtsi" +- +-/ { +- compatible = "phicomm,k3", "brcm,bcm47094", "brcm,bcm4708"; +- model = "Phicomm K3"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x88000000 0x18000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +- +-&nandcs { +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "boot"; +- reg = <0x0000000 0x0080000>; +- read-only; +- }; +- +- partition@80000 { +- label = "nvram"; +- reg = <0x0080000 0x0100000>; +- }; +- +- partition@180000{ +- label = "phicomm"; +- reg = <0x0180000 0x0280000>; +- read-only; +- }; +- +- partition@400000 { +- label = "firmware"; +- reg = <0x0400000 0x7C00000>; +- compatible = "brcm,trx"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47094.dtsi b/scripts/dtc/include-prefixes/arm/bcm47094.dtsi +deleted file mode 100644 +index 6282363313e1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47094.dtsi ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (C) 2016 Rafał Miłecki +- */ +- +-#include "bcm4708.dtsi" +- +-/ { +-}; +- +-&pinctrl { +- compatible = "brcm,bcm4709-pinmux"; +- +- pinmux_mdio: mdio-pins { +- groups = "mdio_grp"; +- function = "mdio"; +- }; +-}; +- +-&usb3_phy { +- compatible = "brcm,ns-bx-usb3-phy"; +-}; +- +-&uart0 { +- clock-frequency = <125000000>; +- status = "okay"; +-}; +- +-&srab { +- compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47189-luxul-xap-1440.dts b/scripts/dtc/include-prefixes/arm/bcm47189-luxul-xap-1440.dts +deleted file mode 100644 +index 57ca1cfaecd8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47189-luxul-xap-1440.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright 2017 Luxul Inc. +- */ +- +-/dts-v1/; +- +-#include "bcm53573.dtsi" +- +-/ { +- compatible = "luxul,xap-1440-v1", "brcm,bcm47189", "brcm,bcm53573"; +- model = "Luxul XAP-1440 V1"; +- +- chosen { +- bootargs = "earlycon"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- wlan { +- label = "bcm53xx:blue:wlan"; +- gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-off"; +- }; +- +- system { +- label = "bcm53xx:green:system"; +- gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "timer"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47189-luxul-xap-810.dts b/scripts/dtc/include-prefixes/arm/bcm47189-luxul-xap-810.dts +deleted file mode 100644 +index 2e1a7e382cb7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47189-luxul-xap-810.dts ++++ /dev/null +@@ -1,85 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright 2017 Luxul Inc. +- */ +- +-/dts-v1/; +- +-#include "bcm53573.dtsi" +- +-/ { +- compatible = "luxul,xap-810-v1", "brcm,bcm47189", "brcm,bcm53573"; +- model = "Luxul XAP-810 V1"; +- +- chosen { +- bootargs = "earlycon"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- 5ghz { +- label = "bcm53xx:blue:5ghz"; +- gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-off"; +- }; +- +- system { +- label = "bcm53xx:green:system"; +- gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "timer"; +- }; +- }; +- +- pcie0_leds { +- compatible = "gpio-leds"; +- +- 2ghz { +- label = "bcm53xx:blue:2ghz"; +- gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-off"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&pcie0 { +- ranges = <0x00000000 0 0 0 0 0x00100000>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- bridge@0,0,0 { +- reg = <0x0000 0 0 0 0>; +- ranges = <0x00000000 0 0 0 0 0 0 0x00100000>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- wifi@0,1,0 { +- reg = <0x0000 0 0 0 0>; +- ranges = <0x00000000 0 0 0 0x00100000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- pcie0_chipcommon: chipcommon@0 { +- reg = <0 0x1000>; +- +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm47189-tenda-ac9.dts b/scripts/dtc/include-prefixes/arm/bcm47189-tenda-ac9.dts +deleted file mode 100644 +index 049cdfd92706..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm47189-tenda-ac9.dts ++++ /dev/null +@@ -1,107 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (C) 2016 Rafał Miłecki +- */ +- +-/dts-v1/; +- +-#include "bcm53573.dtsi" +- +-/ { +- compatible = "tenda,ac9", "brcm,bcm47189", "brcm,bcm53573"; +- model = "Tenda AC9"; +- +- chosen { +- bootargs = "console=ttyS0,115200 earlycon"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- usb { +- label = "bcm53xx:blue:usb"; +- gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; +- trigger-sources = <&ohci_port1>, <&ehci_port1>; +- linux,default-trigger = "usbport"; +- }; +- +- wps { +- label = "bcm53xx:blue:wps"; +- gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; +- }; +- +- 5ghz { +- label = "bcm53xx:blue:5ghz"; +- gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; +- }; +- +- system { +- label = "bcm53xx:blue:system"; +- gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "timer"; +- }; +- }; +- +- pcie0_leds { +- compatible = "gpio-leds"; +- +- 2ghz { +- label = "bcm53xx:blue:2ghz"; +- gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- rfkill { +- label = "WiFi"; +- linux,code = ; +- gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; +- }; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&pcie0 { +- ranges = <0x00000000 0 0 0 0 0x00100000>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- bridge@0,0,0 { +- reg = <0x0000 0 0 0 0>; +- ranges = <0x00000000 0 0 0 0 0 0 0x00100000>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- wifi@0,1,0 { +- reg = <0x0000 0 0 0 0>; +- ranges = <0x00000000 0 0 0 0x00100000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- pcie0_chipcommon: chipcommon@0 { +- reg = <0 0x1000>; +- +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm53016-meraki-mr32.dts b/scripts/dtc/include-prefixes/arm/bcm53016-meraki-mr32.dts +deleted file mode 100644 +index 577a4dc604d9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm53016-meraki-mr32.dts ++++ /dev/null +@@ -1,219 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Broadcom BCM470X / BCM5301X ARM platform code. +- * DTS for Meraki MR32 / Codename: Espresso +- * +- * Copyright (C) 2018-2020 Christian Lamparter +- */ +- +-/dts-v1/; +- +-#include "bcm4708.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +-#include +- +-/ { +- compatible = "meraki,mr32", "brcm,brcm53016", "brcm,bcm4708"; +- model = "Meraki MR32"; +- +- chosen { +- bootargs = " console=ttyS0,115200n8 earlycon"; +- }; +- +- memory@0 { +- reg = <0x00000000 0x08000000>; +- device_type = "memory"; +- }; +- +- aliases { +- serial1 = &uart2; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- sysled3 { +- function = LED_FUNCTION_FAULT; +- color = ; +- gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; +- panic-indicator; +- }; +- sysled2 { +- function = LED_FUNCTION_INDICATOR; +- color = ; +- gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- pwm-leds { +- compatible = "pwm-leds"; +- +- red { +- /* SYS-LED 1 - Tricolor */ +- function = LED_FUNCTION_INDICATOR; +- color = ; +- pwms = <&pwm 0 50000 0>; +- max-brightness = <255>; +- }; +- +- green { +- /* SYS-LED 1 - Tricolor */ +- function = LED_FUNCTION_POWER; +- color = ; +- pwms = <&pwm 1 50000 0>; +- max-brightness = <255>; +- }; +- +- blue { +- /* SYS-LED 1 - Tricolor */ +- function = LED_FUNCTION_INDICATOR; +- color = ; +- pwms = <&pwm 2 50000 0>; +- max-brightness = <255>; +- }; +- }; +- +- i2c { +- /* +- * The platform provided I2C does not budge. +- * This is a replacement until I can figure +- * out what are the missing bits... +- */ +- +- compatible = "i2c-gpio"; +- sda-gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; +- i2c-gpio,delay-us = <10>; /* close to 100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- +- current_sense: ina219@45 { +- compatible = "ti,ina219"; +- reg = <0x45>; +- shunt-resistor = <60000>; /* = 60 mOhms */ +- }; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- pagesize = <32>; +- read-only; +- }; +- }; +-}; +- +-&uart0 { +- clock-frequency = <62500000>; +- /delete-property/ clocks; +-}; +- +-&uart1 { +- status = "disabled"; +-}; +- +-&uart2 { +- status = "okay"; +- /* +- * bluetooth-le { +- * compatible = "brcm,bcm20732"; +- * enable-gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; +- *}; +- */ +-}; +- +-&gmac1 { +- status = "disabled"; +-}; +-&gmac2 { +- status = "disabled"; +-}; +-&gmac3 { +- status = "disabled"; +-}; +- +-&pwm { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinmux_pwm>; +-}; +- +-&nandcs { +- nand-ecc-algo = "hw"; +- +- partitions { +- /* +- * The partition autodetection does not work for this device. +- * It will only detect the "nvram" partition with an incorrect size. +- * [ 1.721667] 1 bcm47xxpart partitions found on MTD device brcmnand.0 +- * [ 1.727962] Creating 1 MTD partitions on "brcmnand.0": +- * [ 1.733117] 0x000000400000-0x000008000000 : "nvram" +- */ +- +- compatible = "fixed-partitions"; +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- +- partition0@0 { +- label = "u-boot"; +- reg = <0x0 0x100000>; +- read-only; +- }; +- +- partition1@100000 { +- label = "bootkernel1"; +- reg = <0x100000 0x300000>; +- read-only; +- }; +- +- partition2@400000 { +- label = "nvram"; +- reg = <0x400000 0x100000>; +- read-only; +- }; +- +- partition3@500000 { +- label = "bootkernel2"; +- reg = <0x500000 0x300000>; +- read-only; +- }; +- +- partition4@800000 { +- label = "ubi"; +- reg = <0x800000 0x7780000>; +- }; +- }; +-}; +- +-&srab { +- status = "okay"; +- +- ports { +- port@0 { +- reg = <0>; +- label = "poe"; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <&gmac0>; +- +- fixed-link { +- speed = <1000>; +- duplex-full; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm5301x-nand-cs0-bch1.dtsi b/scripts/dtc/include-prefixes/arm/bcm5301x-nand-cs0-bch1.dtsi +deleted file mode 100644 +index c349e8f0afc5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm5301x-nand-cs0-bch1.dtsi ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Broadcom Northstar NAND. +- * +- * Copyright (C) 2016 Rafał Miłecki +- */ +- +-#include "bcm5301x-nand-cs0.dtsi" +- +-&nandcs { +- nand-ecc-algo = "bch"; +- nand-ecc-strength = <1>; +- nand-ecc-step-size = <512>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm5301x-nand-cs0-bch4.dtsi b/scripts/dtc/include-prefixes/arm/bcm5301x-nand-cs0-bch4.dtsi +deleted file mode 100644 +index 18e25e302b13..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm5301x-nand-cs0-bch4.dtsi ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright 2016 Luxul Inc. +- */ +- +-#include "bcm5301x-nand-cs0.dtsi" +- +-&nandcs { +- nand-ecc-algo = "bch"; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm5301x-nand-cs0-bch8.dtsi b/scripts/dtc/include-prefixes/arm/bcm5301x-nand-cs0-bch8.dtsi +deleted file mode 100644 +index c8e56d30bd6f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm5301x-nand-cs0-bch8.dtsi ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Broadcom BCM470X / BCM5301X Nand chip defaults. +- * +- * This should be included if the NAND controller is on chip select 0 +- * and uses 8 bit ECC. +- * +- * Copyright (C) 2015 Hauke Mehrtens +- */ +- +-#include "bcm5301x-nand-cs0.dtsi" +- +-&nandcs { +- nand-ecc-algo = "bch"; +- nand-ecc-strength = <8>; +- nand-ecc-step-size = <512>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm5301x-nand-cs0.dtsi b/scripts/dtc/include-prefixes/arm/bcm5301x-nand-cs0.dtsi +deleted file mode 100644 +index be9a00ff752d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm5301x-nand-cs0.dtsi ++++ /dev/null +@@ -1,21 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Broadcom Northstar NAND. +- * +- * Copyright (C) 2015 Hauke Mehrtens +- */ +- +-/ { +- nand-controller@18028000 { +- nandcs: nand@0 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partitions { +- compatible = "brcm,bcm947xx-cfe-partitions"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm5301x.dtsi b/scripts/dtc/include-prefixes/arm/bcm5301x.dtsi +deleted file mode 100644 +index f69d2af3c1fa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm5301x.dtsi ++++ /dev/null +@@ -1,576 +0,0 @@ +-/* +- * Broadcom BCM470X / BCM5301X ARM platform code. +- * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, +- * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs +- * +- * Copyright 2013-2014 Hauke Mehrtens +- * +- * Licensed under the GNU/GPL. See COPYING for details. +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&gic>; +- +- chipcommon-a-bus@18000000 { +- compatible = "simple-bus"; +- ranges = <0x00000000 0x18000000 0x00001000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- uart0: serial@300 { +- compatible = "ns16550"; +- reg = <0x0300 0x100>; +- interrupts = ; +- clocks = <&iprocslow>; +- status = "disabled"; +- }; +- +- uart1: serial@400 { +- compatible = "ns16550"; +- reg = <0x0400 0x100>; +- interrupts = ; +- clocks = <&iprocslow>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinmux_uart1>; +- status = "disabled"; +- }; +- }; +- +- mpcore-bus@19000000 { +- compatible = "simple-bus"; +- ranges = <0x00000000 0x19000000 0x00023000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- a9pll: arm_clk@0 { +- #clock-cells = <0>; +- compatible = "brcm,nsp-armpll"; +- clocks = <&osc>; +- reg = <0x00000 0x1000>; +- }; +- +- scu@20000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0x20000 0x100>; +- }; +- +- timer@20200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0x20200 0x100>; +- interrupts = ; +- clocks = <&periph_clk>; +- }; +- +- timer@20600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x20600 0x20>; +- interrupts = ; +- clocks = <&periph_clk>; +- }; +- +- watchdog@20620 { +- compatible = "arm,cortex-a9-twd-wdt"; +- reg = <0x20620 0x20>; +- interrupts = ; +- clocks = <&periph_clk>; +- }; +- +- gic: interrupt-controller@21000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x21000 0x1000>, +- <0x20100 0x100>; +- }; +- +- L2: cache-controller@22000 { +- compatible = "arm,pl310-cache"; +- reg = <0x22000 0x1000>; +- cache-unified; +- arm,shared-override; +- prefetch-data = <1>; +- prefetch-instr = <1>; +- cache-level = <2>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = +- , +- ; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- osc: oscillator { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25000000>; +- }; +- +- iprocmed: iprocmed { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- iprocslow: iprocslow { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; +- clock-div = <4>; +- clock-mult = <1>; +- }; +- +- periph_clk: periph_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&a9pll>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- }; +- +- usb2_phy: usb2-phy@1800c000 { +- compatible = "brcm,ns-usb2-phy"; +- reg = <0x1800c000 0x1000>; +- reg-names = "dmu"; +- #phy-cells = <0>; +- clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; +- clock-names = "phy-ref-clk"; +- }; +- +- axi@18000000 { +- compatible = "brcm,bus-axi"; +- reg = <0x18000000 0x1000>; +- ranges = <0x00000000 0x18000000 0x00100000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0x000fffff 0xffff>; +- interrupt-map = +- /* ChipCommon */ +- <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, +- +- /* Switch Register Access Block */ +- <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, +- +- /* PCIe Controller 0 */ +- <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, +- <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, +- <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, +- <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, +- <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, +- <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, +- +- /* PCIe Controller 1 */ +- <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, +- <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, +- <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, +- <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, +- <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, +- <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, +- +- /* PCIe Controller 2 */ +- <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, +- <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, +- <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, +- <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, +- <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, +- <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, +- +- /* USB 2.0 Controller */ +- <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, +- +- /* USB 3.0 Controller */ +- <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, +- +- /* Ethernet Controller 0 */ +- <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, +- +- /* Ethernet Controller 1 */ +- <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, +- +- /* Ethernet Controller 2 */ +- <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, +- +- /* Ethernet Controller 3 */ +- <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, +- +- /* NAND Controller */ +- <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; +- +- chipcommon: chipcommon@0 { +- reg = <0x00000000 0x1000>; +- +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pcie0: pcie@12000 { +- reg = <0x00012000 0x1000>; +- }; +- +- pcie1: pcie@13000 { +- reg = <0x00013000 0x1000>; +- }; +- +- pcie2: pcie@14000 { +- reg = <0x00014000 0x1000>; +- }; +- +- usb2: usb2@21000 { +- reg = <0x00021000 0x1000>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- interrupt-parent = <&gic>; +- +- ehci: usb@21000 { +- #usb-cells = <0>; +- +- compatible = "generic-ehci"; +- reg = <0x00021000 0x1000>; +- interrupts = ; +- phys = <&usb2_phy>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- ehci_port1: port@1 { +- reg = <1>; +- #trigger-source-cells = <0>; +- }; +- +- ehci_port2: port@2 { +- reg = <2>; +- #trigger-source-cells = <0>; +- }; +- }; +- +- ohci: usb@22000 { +- #usb-cells = <0>; +- +- compatible = "generic-ohci"; +- reg = <0x00022000 0x1000>; +- interrupts = ; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- ohci_port1: port@1 { +- reg = <1>; +- #trigger-source-cells = <0>; +- }; +- +- ohci_port2: port@2 { +- reg = <2>; +- #trigger-source-cells = <0>; +- }; +- }; +- }; +- +- usb3: usb3@23000 { +- reg = <0x00023000 0x1000>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- interrupt-parent = <&gic>; +- +- xhci: usb@23000 { +- #usb-cells = <0>; +- +- compatible = "generic-xhci"; +- reg = <0x00023000 0x1000>; +- interrupts = ; +- phys = <&usb3_phy>; +- phy-names = "usb"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- xhci_port1: port@1 { +- reg = <1>; +- #trigger-source-cells = <0>; +- }; +- }; +- }; +- +- gmac0: ethernet@24000 { +- reg = <0x24000 0x800>; +- }; +- +- gmac1: ethernet@25000 { +- reg = <0x25000 0x800>; +- }; +- +- gmac2: ethernet@26000 { +- reg = <0x26000 0x800>; +- }; +- +- gmac3: ethernet@27000 { +- reg = <0x27000 0x800>; +- }; +- }; +- +- pwm: pwm@18002000 { +- compatible = "brcm,iproc-pwm"; +- reg = <0x18002000 0x28>; +- clocks = <&osc>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- mdio: mdio@18003000 { +- compatible = "brcm,iproc-mdio"; +- reg = <0x18003000 0x8>; +- #size-cells = <0>; +- #address-cells = <1>; +- }; +- +- mdio-mux@18003000 { +- compatible = "mdio-mux-mmioreg", "mdio-mux"; +- mdio-parent-bus = <&mdio>; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x18003000 0x4>; +- mux-mask = <0x200>; +- +- mdio@0 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- usb3_phy: usb3-phy@10 { +- compatible = "brcm,ns-ax-usb3-phy"; +- reg = <0x10>; +- usb3-dmp-syscon = <&usb3_dmp>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- }; +- +- usb3_dmp: syscon@18105000 { +- reg = <0x18105000 0x1000>; +- }; +- +- uart2: serial@18008000 { +- compatible = "ns16550a"; +- reg = <0x18008000 0x20>; +- clocks = <&iprocslow>; +- interrupts = ; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- i2c0: i2c@18009000 { +- compatible = "brcm,iproc-i2c"; +- reg = <0x18009000 0x50>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <100000>; +- status = "disabled"; +- }; +- +- dmu-bus@1800c000 { +- compatible = "simple-bus"; +- ranges = <0 0x1800c000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cru@100 { +- compatible = "simple-bus"; +- reg = <0x100 0x1a4>; +- ranges; +- #address-cells = <1>; +- #size-cells = <1>; +- +- lcpll0: lcpll0@100 { +- #clock-cells = <1>; +- compatible = "brcm,nsp-lcpll0"; +- reg = <0x100 0x14>; +- clocks = <&osc>; +- clock-output-names = "lcpll0", "pcie_phy", +- "sdio", "ddr_phy"; +- }; +- +- genpll: genpll@140 { +- #clock-cells = <1>; +- compatible = "brcm,nsp-genpll"; +- reg = <0x140 0x24>; +- clocks = <&osc>; +- clock-output-names = "genpll", "phy", +- "ethernetclk", +- "usbclk", "iprocfast", +- "sata1", "sata2"; +- }; +- +- pinctrl: pin-controller@1c0 { +- compatible = "brcm,bcm4708-pinmux"; +- reg = <0x1c0 0x24>; +- reg-names = "cru_gpio_control"; +- +- spi-pins { +- groups = "spi_grp"; +- function = "spi"; +- }; +- +- pinmux_i2c: i2c-pins { +- groups = "i2c_grp"; +- function = "i2c"; +- }; +- +- pinmux_pwm: pwm-pins { +- groups = "pwm0_grp", "pwm1_grp", +- "pwm2_grp", "pwm3_grp"; +- function = "pwm"; +- }; +- +- pinmux_uart1: uart1-pins { +- groups = "uart1_grp"; +- function = "uart1"; +- }; +- }; +- +- thermal: thermal@2c0 { +- compatible = "brcm,ns-thermal"; +- reg = <0x2c0 0x10>; +- #thermal-sensor-cells = <0>; +- }; +- }; +- }; +- +- srab: ethernet-switch@18007000 { +- compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab"; +- reg = <0x18007000 0x1000>; +- +- status = "disabled"; +- +- /* ports are defined in board DTS */ +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- rng: rng@18004000 { +- compatible = "brcm,bcm5301x-rng"; +- reg = <0x18004000 0x14>; +- }; +- +- nand_controller: nand-controller@18028000 { +- compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; +- reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; +- reg-names = "nand", "iproc-idm", "iproc-ext"; +- interrupts = ; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- brcm,nand-has-wp; +- }; +- +- spi@18029200 { +- compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; +- reg = <0x18029200 0x184>, +- <0x18029000 0x124>, +- <0x1811b408 0x004>, +- <0x180293a0 0x01c>; +- reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; +- interrupts = , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "mspi_done", +- "mspi_halted", +- "spi_lr_fullness_reached", +- "spi_lr_session_aborted", +- "spi_lr_impatient", +- "spi_lr_session_done", +- "spi_lr_overread"; +- clocks = <&iprocmed>; +- clock-names = "iprocmed"; +- num-cs = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- spi_nor: flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- status = "disabled"; +- +- partitions { +- compatible = "brcm,bcm947xx-cfe-partitions"; +- }; +- }; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <1000>; +- coefficients = <(-556) 418000>; +- thermal-sensors = <&thermal>; +- +- trips { +- cpu-crit { +- temperature = <125000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm53340-ubnt-unifi-switch8.dts b/scripts/dtc/include-prefixes/arm/bcm53340-ubnt-unifi-switch8.dts +deleted file mode 100644 +index 2e7fda9b998c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm53340-ubnt-unifi-switch8.dts ++++ /dev/null +@@ -1,86 +0,0 @@ +-/* +- * DTS for Unifi Switch 8 port +- * +- * Copyright (C) 2017 Florian Fainelli +- * +- * Licensed under the GNU/GPL. See COPYING for details. +- */ +- +-/dts-v1/; +- +-#include "bcm-hr2.dtsi" +- +-/ { +- compatible = "ubnt,unifi-switch8", "brcm,bcm53342", "brcm,hr2"; +- model = "Ubiquiti UniFi Switch 8 (BCM53342)"; +- +- /* Hurricane 2 designs use the second UART */ +- chosen { +- bootargs = "console=ttyS1,115200 earlyprintk"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>, +- <0x68000000 0x08000000>; +- }; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&qspi { +- status = "okay"; +- bspi-sel = <0>; +- +- flash: m25p80@0 { +- compatible = "m25p80"; +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <12500000>; +- spi-cpol; +- spi-cpha; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0 0xc0000>; +- }; +- +- partition@c0000 { +- label = "u-boot-env"; +- reg = <0xc0000 0x10000>; +- }; +- +- partition@d0000 { +- label = "shmoo"; +- reg = <0xd0000 0x10000>; +- }; +- +- partition@e0000 { +- label = "kernel0"; +- reg = <0xe0000 0xf00000>; +- }; +- +- partition@fe0000 { +- label = "kernel1"; +- reg = <0xfe0000 0xf10000>; +- }; +- +- partition@1ef0000 { +- label = "cfg"; +- reg = <0x1ef0000 0x100000>; +- }; +- +- partition@1ff0000 { +- label = "EEPROM"; +- reg = <0x1ff0000 0x10000>; +- }; +- }; +-}; +- +-&pcie0 { +- /* Attaches to the internal switch */ +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm53573.dtsi b/scripts/dtc/include-prefixes/arm/bcm53573.dtsi +deleted file mode 100644 +index 51546fccc616..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm53573.dtsi ++++ /dev/null +@@ -1,201 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (C) 2016 Rafał Miłecki +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&gic>; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x0>; +- }; +- }; +- +- mpcore@18310000 { +- compatible = "simple-bus"; +- ranges = <0x00000000 0x18310000 0x00008000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- gic: interrupt-controller@1000 { +- compatible = "arm,cortex-a7-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x1000 0x1000>, +- <0x2000 0x0100>; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- alp: oscillator { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <40000000>; +- }; +- }; +- +- axi@18000000 { +- compatible = "brcm,bus-axi"; +- reg = <0x18000000 0x1000>; +- ranges = <0x00000000 0x18000000 0x00100000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0x000fffff 0xffff>; +- interrupt-map = +- /* ChipCommon */ +- <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, +- +- /* IEEE 802.11 0 */ +- <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, +- +- /* PCIe Controller 0 */ +- <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, +- <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, +- <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, +- <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, +- <0x00002000 4 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, +- <0x00002000 5 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, +- +- /* USB 2.0 Controller */ +- <0x00004000 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, +- +- /* Ethernet Controller 0 */ +- <0x00005000 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, +- +- /* IEEE 802.11 1 */ +- <0x0000a000 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, +- +- /* Ethernet Controller 1 */ +- <0x0000b000 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; +- +- chipcommon: chipcommon@0 { +- compatible = "simple-bus"; +- reg = <0x00000000 0x1000>; +- ranges; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- uart0: serial@300 { +- compatible = "ns16550a"; +- reg = <0x0300 0x100>; +- interrupt-parent = <&gic>; +- interrupts = ; +- clocks = <&alp>; +- status = "okay"; +- }; +- }; +- +- pcie0: pcie@2000 { +- reg = <0x00002000 0x1000>; +- }; +- +- usb2: usb2@4000 { +- reg = <0x4000 0x1000>; +- ranges; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ehci: usb@4000 { +- compatible = "generic-ehci"; +- reg = <0x4000 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = ; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- ehci_port1: port@1 { +- reg = <1>; +- #trigger-source-cells = <0>; +- }; +- +- ehci_port2: port@2 { +- reg = <2>; +- #trigger-source-cells = <0>; +- }; +- }; +- +- ohci: usb@d000 { +- #usb-cells = <0>; +- +- compatible = "generic-ohci"; +- reg = <0xd000 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = ; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- ohci_port1: port@1 { +- reg = <1>; +- #trigger-source-cells = <0>; +- }; +- +- ohci_port2: port@2 { +- reg = <2>; +- #trigger-source-cells = <0>; +- }; +- }; +- }; +- +- gmac0: ethernet@5000 { +- reg = <0x5000 0x1000>; +- }; +- +- gmac1: ethernet@b000 { +- reg = <0xb000 0x1000>; +- }; +- +- pmu@12000 { +- compatible = "simple-mfd", "syscon"; +- reg = <0x00012000 0x00001000>; +- +- ilp: ilp { +- compatible = "brcm,bcm53573-ilp"; +- clocks = <&alp>; +- #clock-cells = <0>; +- clock-output-names = "ilp"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm59056.dtsi b/scripts/dtc/include-prefixes/arm/bcm59056.dtsi +deleted file mode 100644 +index a9bb7ad81378..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm59056.dtsi ++++ /dev/null +@@ -1,91 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +-* Copyright 2014 Linaro Limited +-* Author: Matt Porter +-*/ +- +-&pmu { +- compatible = "brcm,bcm59056"; +- regulators { +- rfldo_reg: rfldo { +- }; +- +- camldo1_reg: camldo1 { +- }; +- +- camldo2_reg: camldo2 { +- }; +- +- simldo1_reg: simldo1 { +- }; +- +- simldo2_reg: simldo2 { +- }; +- +- sdldo_reg: sdldo { +- }; +- +- sdxldo_reg: sdxldo { +- }; +- +- mmcldo1_reg: mmcldo1 { +- }; +- +- mmcldo2_reg: mmcldo2 { +- }; +- +- audldo_reg: audldo { +- }; +- +- micldo_reg: micldo { +- }; +- +- usbldo_reg: usbldo { +- }; +- +- vibldo_reg: vibldo { +- }; +- +- csr_reg: csr { +- }; +- +- iosr1_reg: iosr1 { +- }; +- +- iosr2_reg: iosr2 { +- }; +- +- msr_reg: msr { +- }; +- +- sdsr1_reg: sdsr1 { +- }; +- +- sdsr2_reg: sdsr2 { +- }; +- +- vsr_reg: vsr { +- }; +- +- gpldo1_reg: gpldo1 { +- }; +- +- gpldo2_reg: gpldo2 { +- }; +- +- gpldo3_reg: gpldo3 { +- }; +- +- gpldo4_reg: gpldo4 { +- }; +- +- gpldo5_reg: gpldo5 { +- }; +- +- gpldo6_reg: gpldo6 { +- }; +- +- vbus_reg: vbus { +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm63138.dtsi b/scripts/dtc/include-prefixes/arm/bcm63138.dtsi +deleted file mode 100644 +index cca49a2e2d62..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm63138.dtsi ++++ /dev/null +@@ -1,229 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Broadcom BCM63138 DSL SoCs Device Tree +- */ +- +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "brcm,bcm63138"; +- model = "Broadcom BCM63138 DSL SoC"; +- interrupt-parent = <&gic>; +- +- aliases { +- uart0 = &serial0; +- uart1 = &serial1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- reg = <0>; +- enable-method = "brcm,bcm63138"; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- reg = <1>; +- enable-method = "brcm,bcm63138"; +- resets = <&pmb0 4 1>; +- }; +- }; +- +- clocks { +- /* UBUS peripheral clock */ +- periph_clk: periph_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- clock-output-names = "periph"; +- }; +- +- /* peripheral clock for system timer */ +- axi_clk: axi_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&armpll>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- /* APB bus clock */ +- apb_clk: apb_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&armpll>; +- clock-div = <4>; +- clock-mult = <1>; +- }; +- }; +- +- /* ARM bus */ +- axi@80000000 { +- compatible = "simple-bus"; +- ranges = <0 0x80000000 0x784000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- L2: cache-controller@1d000 { +- compatible = "arm,pl310-cache"; +- reg = <0x1d000 0x1000>; +- cache-unified; +- cache-level = <2>; +- cache-size = <524288>; +- cache-sets = <1024>; +- cache-line-size = <32>; +- interrupts = ; +- }; +- +- scu: scu@1e000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0x1e000 0x100>; +- }; +- +- gic: interrupt-controller@1f000 { +- compatible = "arm,cortex-a9-gic"; +- reg = <0x1f000 0x1000 +- 0x1e100 0x100>; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- }; +- +- global_timer: timer@1e200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0x1e200 0x20>; +- interrupts = ; +- clocks = <&axi_clk>; +- }; +- +- local_timer: local-timer@1e600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x1e600 0x20>; +- interrupts = ; +- clocks = <&axi_clk>; +- }; +- +- twd_watchdog: watchdog@1e620 { +- compatible = "arm,cortex-a9-twd-wdt"; +- reg = <0x1e620 0x20>; +- interrupts = ; +- }; +- +- armpll: armpll@20000 { +- #clock-cells = <0>; +- compatible = "brcm,bcm63138-armpll"; +- clocks = <&periph_clk>; +- reg = <0x20000 0xf00>; +- }; +- +- pmb0: reset-controller@4800c0 { +- compatible = "brcm,bcm63138-pmb"; +- reg = <0x4800c0 0x10>; +- #reset-cells = <2>; +- }; +- +- pmb1: reset-controller@4800e0 { +- compatible = "brcm,bcm63138-pmb"; +- reg = <0x4800e0 0x10>; +- #reset-cells = <2>; +- }; +- +- ahci: sata@a000 { +- compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci"; +- reg-names = "ahci", "top-ctrl"; +- reg = <0xa000 0x9ac>, <0x8040 0x24>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- resets = <&pmb0 3 1>; +- reset-names = "ahci"; +- status = "disabled"; +- +- sata0: sata-port@0 { +- reg = <0>; +- phys = <&sata_phy0>; +- }; +- }; +- +- sata_phy: sata-phy@8100 { +- compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3"; +- reg = <0x8100 0x1e00>; +- reg-names = "phy"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- sata_phy0: sata-phy@0 { +- reg = <0>; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- /* Legacy UBUS base */ +- ubus@fffe8000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xfffe8000 0x8100>; +- +- timer: timer@80 { +- compatible = "brcm,bcm6328-timer", "syscon"; +- reg = <0x80 0x3c>; +- }; +- +- serial0: serial@600 { +- compatible = "brcm,bcm6345-uart"; +- reg = <0x600 0x1b>; +- interrupts = ; +- clocks = <&periph_clk>; +- clock-names = "periph"; +- status = "disabled"; +- }; +- +- serial1: serial@620 { +- compatible = "brcm,bcm6345-uart"; +- reg = <0x620 0x1b>; +- interrupts = ; +- clocks = <&periph_clk>; +- clock-names = "periph"; +- status = "disabled"; +- }; +- +- nand_controller: nand-controller@2000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand"; +- reg = <0x2000 0x600>, <0xf0 0x10>; +- reg-names = "nand", "nand-int-base"; +- status = "disabled"; +- interrupts = ; +- interrupt-names = "nand"; +- }; +- +- bootlut: bootlut@8000 { +- compatible = "brcm,bcm63138-bootlut"; +- reg = <0x8000 0x50>; +- }; +- +- reboot { +- compatible = "syscon-reboot"; +- regmap = <&timer>; +- offset = <0x34>; +- mask = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm7445-bcm97445svmb.dts b/scripts/dtc/include-prefixes/arm/bcm7445-bcm97445svmb.dts +deleted file mode 100644 +index f92d2cf85972..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm7445-bcm97445svmb.dts ++++ /dev/null +@@ -1,38 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "bcm7445.dtsi" +- +-/ { +- model = "Broadcom STB (bcm7445), SVMB reference board"; +- compatible = "brcm,bcm7445", "brcm,brcmstb"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00 0x00000000 0x00 0x40000000>, +- <0x00 0x40000000 0x00 0x40000000>, +- <0x00 0x80000000 0x00 0x40000000>; +- }; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@1 { +- compatible = "brcm,nandcs"; +- reg = <1>; +- nand-ecc-step-size = <512>; +- nand-ecc-strength = <8>; +- nand-on-flash-bbt; +- +- #size-cells = <2>; +- #address-cells = <2>; +- +- flash1.rootfs0@0 { +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- flash1.rootfs1@80000000 { +- reg = <0x0 0x80000000 0x0 0x80000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm7445.dtsi b/scripts/dtc/include-prefixes/arm/bcm7445.dtsi +deleted file mode 100644 +index 5ac2042515b8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm7445.dtsi ++++ /dev/null +@@ -1,315 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- model = "Broadcom STB (bcm7445)"; +- compatible = "brcm,bcm7445", "brcm,brcmstb"; +- interrupt-parent = <&gic>; +- +- chosen { +- bootargs = "console=ttyS0,115200 earlyprintk"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "brcm,brahma-b15"; +- device_type = "cpu"; +- enable-method = "brcm,brahma-b15"; +- reg = <0>; +- }; +- +- cpu@1 { +- compatible = "brcm,brahma-b15"; +- device_type = "cpu"; +- enable-method = "brcm,brahma-b15"; +- reg = <1>; +- }; +- +- cpu@2 { +- compatible = "brcm,brahma-b15"; +- device_type = "cpu"; +- enable-method = "brcm,brahma-b15"; +- reg = <2>; +- }; +- +- cpu@3 { +- compatible = "brcm,brahma-b15"; +- device_type = "cpu"; +- enable-method = "brcm,brahma-b15"; +- reg = <3>; +- }; +- }; +- +- gic: interrupt-controller@ffd00000 { +- compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic"; +- reg = <0x00 0xffd01000 0x00 0x1000>, +- <0x00 0xffd02000 0x00 0x2000>, +- <0x00 0xffd04000 0x00 0x2000>, +- <0x00 0xffd06000 0x00 0x2000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- rdb@f0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0 0x00 0xf0000000 0x1000000>; +- +- serial@40ab00 { +- compatible = "ns16550a"; +- reg = <0x40ab00 0x20>; +- reg-shift = <2>; +- reg-io-width = <4>; +- interrupts = ; +- clock-frequency = <81000000>; +- }; +- +- sun_top_ctrl: syscon@404000 { +- compatible = "brcm,bcm7445-sun-top-ctrl", +- "syscon"; +- reg = <0x404000 0x51c>; +- }; +- +- hif_cpubiuctrl: syscon@3e2400 { +- compatible = "brcm,bcm7445-hif-cpubiuctrl", +- "syscon"; +- reg = <0x3e2400 0x5b4>; +- }; +- +- hif_continuation: syscon@452000 { +- compatible = "brcm,bcm7445-hif-continuation", +- "syscon"; +- reg = <0x452000 0x100>; +- }; +- +- irq0_intc: interrupt-controller@40a780 { +- compatible = "brcm,bcm7120-l2-intc"; +- interrupt-parent = <&gic>; +- #interrupt-cells = <1>; +- reg = <0x40a780 0x8>; +- interrupt-controller; +- interrupts = , +- ; +- brcm,int-map-mask = <0x25c>, <0x7000000>; +- brcm,int-fwd-mask = <0x70000>; +- }; +- +- irq0_aon_intc: interrupt-controller@417280 { +- compatible = "brcm,bcm7120-l2-intc"; +- reg = <0x417280 0x8>; +- interrupt-parent = <&gic>; +- #interrupt-cells = <1>; +- interrupt-controller; +- interrupts = , +- , +- ; +- brcm,int-map-mask = <0x1e3 0x18000000 0x100000>; +- brcm,int-fwd-mask = <0x0>; +- brcm,irq-can-wake; +- }; +- +- hif_intr2_intc: interrupt-controller@3e1000 { +- compatible = "brcm,l2-intc"; +- reg = <0x3e1000 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupts = ; +- interrupt-parent = <&gic>; +- interrupt-names = "hif"; +- }; +- +- aon_pm_l2_intc: interrupt-controller@410640 { +- compatible = "brcm,l2-intc"; +- reg = <0x410640 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupts = ; +- interrupt-parent = <&gic>; +- brcm,irq-can-wake; +- }; +- +- aon-ctrl@410000 { +- compatible = "brcm,brcmstb-aon-ctrl"; +- reg = <0x410000 0x200>, <0x410200 0x400>; +- reg-names = "aon-ctrl", "aon-sram"; +- }; +- +- nand_controller: nand-controller@3e2800 { +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand"; +- reg-names = "nand", "flash-dma"; +- reg = <0x3e2800 0x600>, <0x3e3000 0x2c>; +- interrupt-parent = <&hif_intr2_intc>; +- interrupts = <24>, <4>; +- interrupt-names = "nand_ctlrdy", "flash_dma_done"; +- }; +- +- sata@45a000 { +- compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci"; +- reg-names = "ahci", "top-ctrl"; +- reg = <0x45a000 0xa9c>, <0x458040 0x24>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- +- sata0: sata-port@0 { +- reg = <0>; +- phys = <&sata_phy0>; +- }; +- +- sata1: sata-port@1 { +- reg = <1>; +- phys = <&sata_phy1>; +- }; +- }; +- +- sata_phy: sata-phy@458100 { +- compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3"; +- reg = <0x458100 0x1f00>; +- reg-names = "phy"; +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- +- sata_phy0: sata-phy@0 { +- reg = <0>; +- #phy-cells = <0>; +- }; +- +- sata_phy1: sata-phy@1 { +- reg = <1>; +- #phy-cells = <0>; +- }; +- }; +- +- upg_gio: gpio@40a700 { +- compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; +- reg = <0x40a700 0x80>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupt-parent = <&irq0_intc>; +- interrupts = <6>; +- brcm,gpio-bank-widths = <32 32 32 24>; +- }; +- +- upg_gio_aon: gpio@4172c0 { +- compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; +- reg = <0x4172c0 0x40>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupts-extended = <&irq0_aon_intc 0x6>, +- <&aon_pm_l2_intc 0x5>; +- wakeup-source; +- brcm,gpio-bank-widths = <18 4>; +- }; +- +- }; +- +- memory_controllers@f1100000 { +- compatible = "simple-bus"; +- ranges = <0x0 0x0 0xf1100000 0x200000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memc@0 { +- compatible = "brcm,brcmstb-memc", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x80000>; +- +- memc-ddr@2000 { +- compatible = "brcm,brcmstb-memc-ddr"; +- reg = <0x2000 0x800>; +- }; +- +- ddr-phy@6000 { +- compatible = "brcm,brcmstb-ddr-phy-v240.1"; +- reg = <0x6000 0x21c>; +- }; +- +- shimphy@8000 { +- compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; +- reg = <0x8000 0xe4>; +- }; +- }; +- +- memc@80000 { +- compatible = "brcm,brcmstb-memc", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x80000 0x80000>; +- +- memc-ddr@2000 { +- compatible = "brcm,brcmstb-memc-ddr"; +- reg = <0x2000 0x800>; +- }; +- +- ddr-phy@6000 { +- compatible = "brcm,brcmstb-ddr-phy-v240.1"; +- reg = <0x6000 0x21c>; +- }; +- +- shimphy@8000 { +- compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; +- reg = <0x8000 0xe4>; +- }; +- }; +- +- memc@100000 { +- compatible = "brcm,brcmstb-memc", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x100000 0x80000>; +- +- memc-ddr@2000 { +- compatible = "brcm,brcmstb-memc-ddr"; +- reg = <0x2000 0x800>; +- }; +- +- ddr-phy@6000 { +- compatible = "brcm,brcmstb-ddr-phy-v240.1"; +- reg = <0x6000 0x21c>; +- }; +- +- shimphy@8000 { +- compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; +- reg = <0x8000 0xe4>; +- }; +- }; +- }; +- +- sram@ffe00000 { +- compatible = "brcm,boot-sram", "mmio-sram"; +- reg = <0x0 0xffe00000 0x0 0x10000>; +- }; +- +- smpboot { +- compatible = "brcm,brcmstb-smpboot"; +- syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>; +- syscon-cont = <&hif_continuation>; +- }; +- +- reboot { +- compatible = "brcm,brcmstb-reboot"; +- syscon = <&sun_top_ctrl 0x304 0x308>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm911360_entphn.dts b/scripts/dtc/include-prefixes/arm/bcm911360_entphn.dts +deleted file mode 100644 +index a76c74b44bba..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm911360_entphn.dts ++++ /dev/null +@@ -1,99 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2014 Broadcom Corporation. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "bcm-cygnus.dtsi" +-#include "dt-bindings/input/input.h" +- +-/ { +- model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)"; +- compatible = "brcm,bcm11360", "brcm,cygnus"; +- +- aliases { +- serial0 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- hook { +- label = "HOOK"; +- linux,code = ; +- gpios = <&gpio_asiu 48 0>; +- }; +- }; +-}; +- +-ð0 { +- status = "okay"; +-}; +- +-&mdio { +- status = "okay"; +-}; +- +-&switch { +- status = "okay"; +-}; +- +-&v3d { +- assigned-clocks = +- <&mipipll BCM_CYGNUS_MIPIPLL>, +- <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>; +- assigned-clock-rates = <525000000>, <300000000>; +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&nand_controller { +- nand@1 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- nand-on-flash-bbt; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- nand-ecc-strength = <24>; +- nand-ecc-step-size = <1024>; +- +- brcm,nand-oob-sector-size = <27>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm911360k.dts b/scripts/dtc/include-prefixes/arm/bcm911360k.dts +deleted file mode 100644 +index 091c73a46e08..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm911360k.dts ++++ /dev/null +@@ -1,52 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2014 Broadcom Corporation. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "bcm-cygnus.dtsi" +- +-/ { +- model = "Cygnus SVK (BCM911360K)"; +- compatible = "brcm,bcm11360", "brcm,cygnus"; +- +- aliases { +- serial0 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&uart3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm94708.dts b/scripts/dtc/include-prefixes/arm/bcm94708.dts +deleted file mode 100644 +index d9eb2040b963..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm94708.dts ++++ /dev/null +@@ -1,49 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2015 Broadcom Corporation. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "bcm4708.dtsi" +- +-/ { +- model = "NorthStar SVK (BCM94708)"; +- compatible = "brcm,bcm94708", "brcm,bcm4708"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm94709.dts b/scripts/dtc/include-prefixes/arm/bcm94709.dts +deleted file mode 100644 +index 618c812eef73..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm94709.dts ++++ /dev/null +@@ -1,49 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2015 Broadcom Corporation. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "bcm4708.dtsi" +- +-/ { +- model = "NorthStar SVK (BCM94709)"; +- compatible = "brcm,bcm94709", "brcm,bcm4709", "brcm,bcm4708"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm947189acdbmr.dts b/scripts/dtc/include-prefixes/arm/bcm947189acdbmr.dts +deleted file mode 100644 +index b0b8c774a37f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm947189acdbmr.dts ++++ /dev/null +@@ -1,96 +0,0 @@ +-/* +- * Copyright (C) 2017 Broadcom +- * Author: Florian Fainelli +- * +- * Licensed under the ISC license. +- */ +- +-/dts-v1/; +- +-#include "bcm53573.dtsi" +- +-/ { +- compatible = "brcm,bcm947189acdbmr", "brcm,bcm47189", "brcm,bcm53573"; +- model = "Broadcom BCM947189ACDBMR"; +- +- chosen { +- bootargs = "console=ttyS0,115200 earlycon"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- wps { +- label = "bcm53xx:blue:wps"; +- gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; +- }; +- +- 5ghz { +- label = "bcm53xx:blue:5ghz"; +- gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; +- }; +- +- 2ghz { +- label = "bcm53xx:blue:2ghz"; +- gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; +- }; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- spi { +- compatible = "spi-gpio"; +- num-chipselects = <1>; +- gpio-sck = <&chipcommon 21 0>; +- gpio-miso = <&chipcommon 22 0>; +- gpio-mosi = <&chipcommon 23 0>; +- cs-gpios = <&chipcommon 24 0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* External BCM6802 MoCA chip is connected */ +- }; +-}; +- +-&pcie0 { +- ranges = <0x00000000 0 0 0 0 0x00100000>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- bridge@0,0,0 { +- reg = <0x0000 0 0 0 0>; +- ranges = <0x00000000 0 0 0 0 0 0 0x00100000>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- wifi@0,1,0 { +- reg = <0x0000 0 0 0 0>; +- ranges = <0x00000000 0 0 0 0x00100000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- }; +-}; +- +-&usb2 { +- vcc-gpio = <&chipcommon 8 GPIO_ACTIVE_HIGH>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm953012er.dts b/scripts/dtc/include-prefixes/arm/bcm953012er.dts +deleted file mode 100644 +index 52feca0fb906..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm953012er.dts ++++ /dev/null +@@ -1,92 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2016 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "bcm4708.dtsi" +-#include "bcm5301x-nand-cs0-bch8.dtsi" +- +-/ { +- model = "NorthStar Enterprise Router (BCM953012ER)"; +- compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&spi_nor { +- status = "okay"; +-}; +- +-&srab { +- status = "okay"; +- +- ports { +- port@0 { +- reg = <0>; +- label = "port0"; +- }; +- +- port@1 { +- reg = <1>; +- label = "port1"; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <&gmac0>; +- }; +- }; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm953012hr.dts b/scripts/dtc/include-prefixes/arm/bcm953012hr.dts +deleted file mode 100644 +index 9140be7ec053..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm953012hr.dts ++++ /dev/null +@@ -1,102 +0,0 @@ +-/* +- * SPDX-License-Identifier: BSD-3-Clause +- * +- * Copyright(c) 2017 Broadcom +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom nor the names of its contributors +- * may be used to endorse or promote products derived from this +- * software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "bcm4708.dtsi" +-#include "bcm5301x-nand-cs0-bch4.dtsi" +- +-/ { +- model = "NorthStar HR (BCM953012HR)"; +- compatible = "brcm,bcm953012hr", "brcm,brcm53012", "brcm,bcm4708"; +- +- aliases { +- ethernet0 = &gmac0; +- ethernet1 = &gmac1; +- ethernet2 = &gmac2; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; +- }; +-}; +- +-&nandcs { +- partition@0 { +- label = "nboot"; +- reg = <0x00000000 0x00200000>; +- read-only; +- }; +- partition@200000 { +- label = "nenv"; +- reg = <0x00200000 0x00400000>; +- }; +- partition@600000 { +- label = "nsystem"; +- reg = <0x00600000 0x00a00000>; +- }; +- partition@1000000 { +- label = "nrootfs"; +- reg = <0x01000000 0x07000000>; +- }; +-}; +- +-&spi_nor { +- status = "okay"; +- spi-max-frequency = <62500000>; +- m25p,default-addr-width = <3>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "boot"; +- reg = <0x00000000 0x000d0000>; +- }; +- partition@d000 { +- label = "env"; +- reg = <0x000d0000 0x00030000>; +- }; +- partition@100000 { +- label = "system"; +- reg = <0x00100000 0x00600000>; +- }; +- partition@700000 { +- label = "rootfs"; +- reg = <0x00700000 0x00900000>; +- }; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm953012k.dts b/scripts/dtc/include-prefixes/arm/bcm953012k.dts +deleted file mode 100644 +index de40bd59a5fa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm953012k.dts ++++ /dev/null +@@ -1,120 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2015 Broadcom Corporation. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "bcm4708.dtsi" +- +-/ { +- model = "NorthStar SVK (BCM953012K)"; +- compatible = "brcm,bcm953012k", "brcm,brcm53012", "brcm,bcm4708"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; +- }; +-}; +- +-&nand_controller { +- nand@0 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- nand-on-flash-bbt; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- +- partition@0 { +- label = "nboot"; +- reg = <0x00000000 0x00200000>; +- read-only; +- }; +- partition@200000 { +- label = "nenv"; +- reg = <0x00200000 0x00400000>; +- }; +- partition@600000 { +- label = "nsystem"; +- reg = <0x00600000 0x00a00000>; +- }; +- partition@1000000 { +- label = "nrootfs"; +- reg = <0x01000000 0x07000000>; +- }; +- }; +-}; +- +-&spi_nor { +- status = "okay"; +- spi-max-frequency = <62500000>; +- m25p,default-addr-width = <3>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "boot"; +- reg = <0x00000000 0x000d0000>; +- }; +- partition@d000 { +- label = "env"; +- reg = <0x000d0000 0x00030000>; +- }; +- partition@100000 { +- label = "system"; +- reg = <0x00100000 0x00600000>; +- }; +- partition@700000 { +- label = "rootfs"; +- reg = <0x00700000 0x00900000>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm958300k.dts b/scripts/dtc/include-prefixes/arm/bcm958300k.dts +deleted file mode 100644 +index dda3e11b711f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm958300k.dts ++++ /dev/null +@@ -1,77 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2014 Broadcom Corporation. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "bcm-cygnus.dtsi" +-#include "bcm9hmidc.dtsi" +- +-/ { +- model = "Cygnus SVK (BCM958300K)"; +- compatible = "brcm,bcm58300", "brcm,cygnus"; +- +- aliases { +- serial0 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&nand_controller { +- nand@1 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- nand-on-flash-bbt; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- nand-ecc-strength = <24>; +- nand-ecc-step-size = <1024>; +- +- brcm,nand-oob-sector-size = <27>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm958305k.dts b/scripts/dtc/include-prefixes/arm/bcm958305k.dts +deleted file mode 100644 +index ea3c6b88b313..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm958305k.dts ++++ /dev/null +@@ -1,85 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2015 Broadcom Corporation. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "bcm-cygnus.dtsi" +-#include "bcm9hmidc.dtsi" +- +-/ { +- model = "Cygnus Wireless Audio (BCM958305K)"; +- compatible = "brcm,bcm58305", "brcm,cygnus"; +- +- aliases { +- serial0 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&nand_controller { +- nand@1 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- nand-on-flash-bbt; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- nand-ecc-strength = <24>; +- nand-ecc-step-size = <1024>; +- +- brcm,nand-oob-sector-size = <27>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm958522er.dts b/scripts/dtc/include-prefixes/arm/bcm958522er.dts +deleted file mode 100644 +index 1f73885ec274..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm958522er.dts ++++ /dev/null +@@ -1,184 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2016 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "bcm-nsp.dtsi" +-#include +- +-/ { +- model = "NorthStar Plus SVK (BCM958522ER)"; +- compatible = "brcm,bcm58522", "brcm,nsp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x80000000>; +- }; +- +- gpio-restart { +- compatible = "gpio-restart"; +- gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; +- open-source; +- priority = <200>; +- }; +-}; +- +-/* USB 3 support needed to be complete */ +- +-&dma { +- status = "okay"; +-}; +- +-&amac0 { +- status = "okay"; +-}; +- +-&amac1 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&nand_controller { +- nand@0 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- nand-on-flash-bbt; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- nand-ecc-strength = <24>; +- nand-ecc-step-size = <1024>; +- +- brcm,nand-oob-sector-size = <27>; +- +- partition@0 { +- label = "nboot"; +- reg = <0x00000000 0x00200000>; +- read-only; +- }; +- partition@200000 { +- label = "nenv"; +- reg = <0x00200000 0x00400000>; +- }; +- partition@600000 { +- label = "nsystem"; +- reg = <0x00600000 0x00a00000>; +- }; +- partition@1000000 { +- label = "nrootfs"; +- reg = <0x01000000 0x03000000>; +- }; +- partition@4000000 { +- label = "ncustfs"; +- reg = <0x04000000 0x3c000000>; +- }; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&nand_sel>; +- nand_sel: nand_sel { +- function = "nand"; +- groups = "nand_grp"; +- }; +-}; +- +-&qspi { +- bspi-sel = <0>; +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p80"; +- reg = <0x0>; +- spi-max-frequency = <12500000>; +- m25p,fast-read; +- spi-cpol; +- spi-cpha; +- +- partition@0 { +- label = "boot"; +- reg = <0x00000000 0x000a0000>; +- }; +- +- partition@a0000 { +- label = "env"; +- reg = <0x000a0000 0x00060000>; +- }; +- +- partition@100000 { +- label = "system"; +- reg = <0x00100000 0x00600000>; +- }; +- +- partition@700000 { +- label = "rootfs"; +- reg = <0x00700000 0x01900000>; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +- +-&xhci { +- status = "okay"; +-}; +- +-&srab { +- compatible = "brcm,bcm58522-srab", "brcm,nsp-srab"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm958525er.dts b/scripts/dtc/include-prefixes/arm/bcm958525er.dts +deleted file mode 100644 +index b6b9ca8b0972..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm958525er.dts ++++ /dev/null +@@ -1,196 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2016 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "bcm-nsp.dtsi" +-#include +- +-/ { +- model = "NorthStar Plus SVK (BCM958525ER)"; +- compatible = "brcm,bcm58525", "brcm,nsp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x80000000>; +- }; +- +- gpio-restart { +- compatible = "gpio-restart"; +- gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; +- open-source; +- priority = <200>; +- }; +-}; +- +-/* USB 3 support needed to be complete */ +- +-&dma { +- status = "okay"; +-}; +- +-&amac0 { +- status = "okay"; +-}; +- +-&amac1 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&nand_controller { +- nand@0 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- nand-on-flash-bbt; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- nand-ecc-strength = <24>; +- nand-ecc-step-size = <1024>; +- +- brcm,nand-oob-sector-size = <27>; +- +- partition@0 { +- label = "nboot"; +- reg = <0x00000000 0x00200000>; +- read-only; +- }; +- partition@200000 { +- label = "nenv"; +- reg = <0x00200000 0x00400000>; +- }; +- partition@600000 { +- label = "nsystem"; +- reg = <0x00600000 0x00a00000>; +- }; +- partition@1000000 { +- label = "nrootfs"; +- reg = <0x01000000 0x03000000>; +- }; +- partition@4000000 { +- label = "ncustfs"; +- reg = <0x04000000 0x3c000000>; +- }; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&nand_sel>; +- nand_sel: nand_sel { +- function = "nand"; +- groups = "nand_grp"; +- }; +-}; +- +-&qspi { +- bspi-sel = <0>; +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p80"; +- reg = <0x0>; +- spi-max-frequency = <12500000>; +- m25p,fast-read; +- spi-cpol; +- spi-cpha; +- +- partition@0 { +- label = "boot"; +- reg = <0x00000000 0x000a0000>; +- }; +- +- partition@a0000 { +- label = "env"; +- reg = <0x000a0000 0x00060000>; +- }; +- +- partition@100000 { +- label = "system"; +- reg = <0x00100000 0x00600000>; +- }; +- +- partition@700000 { +- label = "rootfs"; +- reg = <0x00700000 0x01900000>; +- }; +- }; +-}; +- +-&sata_phy0 { +- status = "okay"; +-}; +- +-&sata_phy1 { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +- +-&xhci { +- status = "okay"; +-}; +- +-&srab { +- compatible = "brcm,bcm58525-srab", "brcm,nsp-srab"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm958525xmc.dts b/scripts/dtc/include-prefixes/arm/bcm958525xmc.dts +deleted file mode 100644 +index ecf426f6ad5d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm958525xmc.dts ++++ /dev/null +@@ -1,216 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2016 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "bcm-nsp.dtsi" +-#include +- +-/ { +- model = "NorthStar Plus XMC (BCM958525xmc)"; +- compatible = "brcm,bcm58525", "brcm,nsp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x40000000>; +- }; +- +- gpio-restart { +- compatible = "gpio-restart"; +- gpios = <&gpioa 31 GPIO_ACTIVE_LOW>; +- open-source; +- priority = <200>; +- }; +-}; +- +-/* XHCI support needed to be complete */ +- +-&dma { +- status = "okay"; +-}; +- +-&amac0 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- temperature-sensor@4c { +- compatible = "adi,adt7461a"; +- reg = <0x4c>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- rtc@68 { +- compatible = "st,m41t81"; +- reg = <0x68>; +- }; +-}; +- +-&nand_controller { +- nand@0 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- nand-on-flash-bbt; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- nand-ecc-strength = <24>; +- nand-ecc-step-size = <1024>; +- +- brcm,nand-oob-sector-size = <27>; +- +- partition@0 { +- label = "nboot"; +- reg = <0x00000000 0x00200000>; +- read-only; +- }; +- partition@200000 { +- label = "nenv"; +- reg = <0x00200000 0x00400000>; +- }; +- partition@600000 { +- label = "nsystem"; +- reg = <0x00600000 0x00a00000>; +- }; +- partition@1000000 { +- label = "nrootfs"; +- reg = <0x01000000 0x03000000>; +- }; +- partition@4000000 { +- label = "ncustfs"; +- reg = <0x04000000 0x3c000000>; +- }; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&nand_sel>; +- nand_sel: nand_sel { +- function = "nand"; +- groups = "nand_grp"; +- }; +-}; +- +-&qspi { +- bspi-sel = <0>; +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p80"; +- reg = <0x0>; +- spi-max-frequency = <12500000>; +- m25p,fast-read; +- spi-cpol; +- spi-cpha; +- +- partition@0 { +- label = "boot"; +- reg = <0x00000000 0x000a0000>; +- }; +- +- partition@a0000 { +- label = "env"; +- reg = <0x000a0000 0x00060000>; +- }; +- +- partition@100000 { +- label = "system"; +- reg = <0x00100000 0x00600000>; +- }; +- +- partition@700000 { +- label = "rootfs"; +- reg = <0x00700000 0x01900000>; +- }; +- }; +-}; +- +-&sata_phy0 { +- status = "okay"; +-}; +- +-&sata_phy1 { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&sdio { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +- +-&xhci { +- status = "okay"; +-}; +- +-&srab { +- compatible = "brcm,bcm58525-srab", "brcm,nsp-srab"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm958622hr.dts b/scripts/dtc/include-prefixes/arm/bcm958622hr.dts +deleted file mode 100644 +index 8ca18da981ad..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm958622hr.dts ++++ /dev/null +@@ -1,226 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2016 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "bcm-nsp.dtsi" +-#include +- +-/ { +- model = "NorthStar Plus SVK (BCM958622HR)"; +- compatible = "brcm,bcm58622", "brcm,nsp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x80000000>; +- }; +- +- gpio-restart { +- compatible = "gpio-restart"; +- gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; +- open-source; +- priority = <200>; +- }; +-}; +- +-/* USB 3 and SLIC support needed to be complete */ +- +-&dma { +- status = "okay"; +-}; +- +-&amac0 { +- status = "okay"; +-}; +- +-&amac1 { +- status = "okay"; +-}; +- +-&amac2 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&nand_controller { +- nand@0 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- nand-on-flash-bbt; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- nand-ecc-strength = <24>; +- nand-ecc-step-size = <1024>; +- +- brcm,nand-oob-sector-size = <27>; +- +- partition@0 { +- label = "nboot"; +- reg = <0x00000000 0x00200000>; +- read-only; +- }; +- partition@200000 { +- label = "nenv"; +- reg = <0x00200000 0x00400000>; +- }; +- partition@600000 { +- label = "nsystem"; +- reg = <0x00600000 0x00a00000>; +- }; +- partition@1000000 { +- label = "nrootfs"; +- reg = <0x01000000 0x03000000>; +- }; +- partition@4000000 { +- label = "ncustfs"; +- reg = <0x04000000 0x3c000000>; +- }; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&nand_sel>; +- nand_sel: nand_sel { +- function = "nand"; +- groups = "nand_grp"; +- }; +-}; +- +-&qspi { +- bspi-sel = <0>; +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p80"; +- reg = <0x0>; +- spi-max-frequency = <12500000>; +- m25p,fast-read; +- spi-cpol; +- spi-cpha; +- +- partition@0 { +- label = "boot"; +- reg = <0x00000000 0x000a0000>; +- }; +- +- partition@a0000 { +- label = "env"; +- reg = <0x000a0000 0x00060000>; +- }; +- +- partition@100000 { +- label = "system"; +- reg = <0x00100000 0x00600000>; +- }; +- +- partition@700000 { +- label = "rootfs"; +- reg = <0x00700000 0x01900000>; +- }; +- }; +-}; +- +-&srab { +- compatible = "brcm,bcm58622-srab", "brcm,nsp-srab"; +- status = "okay"; +- +- ports { +- port@0 { +- label = "port0"; +- reg = <0>; +- }; +- +- port@1 { +- label = "port1"; +- reg = <1>; +- }; +- +- port@2 { +- label = "port2"; +- reg = <2>; +- }; +- +- port@3 { +- label = "port3"; +- reg = <3>; +- }; +- +- port@4 { +- label = "port4"; +- reg = <4>; +- }; +- +- port@8 { +- ethernet = <&amac2>; +- label = "cpu"; +- reg = <8>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +- +-&xhci { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm958623hr.dts b/scripts/dtc/include-prefixes/arm/bcm958623hr.dts +deleted file mode 100644 +index 9747378db531..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm958623hr.dts ++++ /dev/null +@@ -1,230 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2016 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "bcm-nsp.dtsi" +-#include +- +-/ { +- model = "NorthStar Plus SVK (BCM958623HR)"; +- compatible = "brcm,bcm58623", "brcm,nsp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x80000000>; +- }; +- +- gpio-restart { +- compatible = "gpio-restart"; +- gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; +- open-source; +- priority = <200>; +- }; +-}; +- +-/* USB 3 and SLIC support needed to be complete */ +- +-&dma { +- status = "okay"; +-}; +- +-&amac0 { +- status = "okay"; +-}; +- +-&amac1 { +- status = "okay"; +-}; +- +-&amac2 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&nand_controller { +- nand@0 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- nand-on-flash-bbt; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- nand-ecc-strength = <24>; +- nand-ecc-step-size = <1024>; +- +- brcm,nand-oob-sector-size = <27>; +- +- partition@0 { +- label = "nboot"; +- reg = <0x00000000 0x00200000>; +- read-only; +- }; +- partition@200000 { +- label = "nenv"; +- reg = <0x00200000 0x00400000>; +- }; +- partition@600000 { +- label = "nsystem"; +- reg = <0x00600000 0x00a00000>; +- }; +- partition@1000000 { +- label = "nrootfs"; +- reg = <0x01000000 0x03000000>; +- }; +- partition@4000000 { +- label = "ncustfs"; +- reg = <0x04000000 0x3c000000>; +- }; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&nand_sel>; +- nand_sel: nand_sel { +- function = "nand"; +- groups = "nand_grp"; +- }; +-}; +- +-&sata_phy0 { +- status = "okay"; +-}; +- +-&qspi { +- bspi-sel = <0>; +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p80"; +- reg = <0x0>; +- spi-max-frequency = <12500000>; +- m25p,fast-read; +- spi-cpol; +- spi-cpha; +- +- partition@0 { +- label = "boot"; +- reg = <0x00000000 0x000a0000>; +- }; +- +- partition@a0000 { +- label = "env"; +- reg = <0x000a0000 0x00060000>; +- }; +- +- partition@100000 { +- label = "system"; +- reg = <0x00100000 0x00600000>; +- }; +- +- partition@700000 { +- label = "rootfs"; +- reg = <0x00700000 0x01900000>; +- }; +- }; +-}; +- +-&srab { +- compatible = "brcm,bcm58623-srab", "brcm,nsp-srab"; +- status = "okay"; +- +- ports { +- port@0 { +- label = "port0"; +- reg = <0>; +- }; +- +- port@1 { +- label = "port1"; +- reg = <1>; +- }; +- +- port@2 { +- label = "port2"; +- reg = <2>; +- }; +- +- port@3 { +- label = "port3"; +- reg = <3>; +- }; +- +- port@4 { +- label = "port4"; +- reg = <4>; +- }; +- +- port@8 { +- ethernet = <&amac2>; +- label = "cpu"; +- reg = <8>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +- +-&xhci { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm958625hr.dts b/scripts/dtc/include-prefixes/arm/bcm958625hr.dts +deleted file mode 100644 +index 0f92b773afb8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm958625hr.dts ++++ /dev/null +@@ -1,253 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2016 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "bcm-nsp.dtsi" +-#include +- +-/ { +- model = "NorthStar Plus SVK (BCM958625HR)"; +- compatible = "brcm,bcm58625", "brcm,nsp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x20000000>; +- }; +- +- gpio-restart { +- compatible = "gpio-restart"; +- gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; +- open-source; +- priority = <200>; +- }; +- +- sfp: sfp { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c0>; +- mod-def0-gpios = <&gpioa 28 GPIO_ACTIVE_LOW>; +- los-gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>; +- tx-fault-gpios = <&gpioa 30 GPIO_ACTIVE_HIGH>; +- tx-disable-gpios = <&gpioa 26 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&dma { +- status = "okay"; +-}; +- +-&amac0 { +- status = "okay"; +-}; +- +-&amac1 { +- status = "okay"; +-}; +- +-&amac2 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&nand_controller { +- nand@0 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- nand-on-flash-bbt; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- nand-ecc-strength = <24>; +- nand-ecc-step-size = <1024>; +- +- brcm,nand-oob-sector-size = <27>; +- +- partition@0 { +- label = "nboot"; +- reg = <0x00000000 0x00200000>; +- read-only; +- }; +- partition@200000 { +- label = "nenv"; +- reg = <0x00200000 0x00400000>; +- }; +- partition@600000 { +- label = "nsystem"; +- reg = <0x00600000 0x00a00000>; +- }; +- partition@1000000 { +- label = "nrootfs"; +- reg = <0x01000000 0x03000000>; +- }; +- partition@4000000 { +- label = "ncustfs"; +- reg = <0x04000000 0x3c000000>; +- }; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&nand_sel>; +- nand_sel: nand_sel { +- function = "nand"; +- groups = "nand_grp"; +- }; +-}; +- +-&qspi { +- bspi-sel = <0>; +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p80"; +- reg = <0x0>; +- spi-max-frequency = <12500000>; +- m25p,fast-read; +- spi-cpol; +- spi-cpha; +- +- partition@0 { +- label = "boot"; +- reg = <0x00000000 0x000a0000>; +- }; +- +- partition@a0000 { +- label = "env"; +- reg = <0x000a0000 0x00060000>; +- }; +- +- partition@100000 { +- label = "system"; +- reg = <0x00100000 0x00600000>; +- }; +- +- partition@700000 { +- label = "rootfs"; +- reg = <0x00700000 0x01900000>; +- }; +- }; +-}; +- +-&sata_phy0 { +- status = "okay"; +-}; +- +-&sata_phy1 { +- status = "okay"; +-}; +- +-&srab { +- compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; +- status = "okay"; +- +- ports { +- port@0 { +- label = "port0"; +- reg = <0>; +- }; +- +- port@1 { +- label = "port1"; +- reg = <1>; +- }; +- +- port@2 { +- label = "port2"; +- reg = <2>; +- }; +- +- port@3 { +- label = "port3"; +- reg = <3>; +- }; +- +- port@4 { +- label = "port4"; +- reg = <4>; +- }; +- +- port@5 { +- label = "sfp"; +- phy-mode = "sgmii"; +- reg = <5>; +- sfp = <&sfp>; +- managed = "in-band-status"; +- }; +- +- port@8 { +- ethernet = <&amac2>; +- label = "cpu"; +- reg = <8>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +- +-&xhci { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm958625k.dts b/scripts/dtc/include-prefixes/arm/bcm958625k.dts +deleted file mode 100644 +index 9e984ca0e6df..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm958625k.dts ++++ /dev/null +@@ -1,270 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2015 Broadcom Corporation. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "bcm-nsp.dtsi" +- +-/ { +- model = "NorthStar Plus SVK (BCM958625K)"; +- compatible = "brcm,bcm58625", "brcm,nsp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x80000000>; +- }; +-}; +- +-&dma { +- status = "okay"; +-}; +- +-&amac0 { +- status = "okay"; +-}; +- +-&amac1 { +- status = "okay"; +-}; +- +-&amac2 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&nand_controller { +- nand@0 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- nand-on-flash-bbt; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- nand-ecc-strength = <24>; +- nand-ecc-step-size = <1024>; +- +- brcm,nand-oob-sector-size = <27>; +- +- partition@0 { +- label = "nboot"; +- reg = <0x00000000 0x00200000>; +- read-only; +- }; +- partition@200000 { +- label = "nenv"; +- reg = <0x00200000 0x00400000>; +- }; +- partition@600000 { +- label = "nsystem"; +- reg = <0x00600000 0x00a00000>; +- }; +- partition@1000000 { +- label = "nrootfs"; +- reg = <0x01000000 0x03000000>; +- }; +- partition@4000000 { +- label = "ncustfs"; +- reg = <0x04000000 0x3c000000>; +- }; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +- +-&pcie2 { +- status = "okay"; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&nand_sel>, <&gpiobs>, <&pwmc>; +- +- nand_sel: nand_sel { +- function = "nand"; +- groups = "nand_grp"; +- }; +- +- gpiobs: gpiobs { +- function = "gpio_b"; +- groups = "gpio_b_0_grp", "gpio_b_1_grp", "gpio_b_2_grp", +- "gpio_b_3_grp"; +- }; +- +- pwmc: pwmc { +- function = "pwm"; +- groups = "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"; +- }; +- +- emmc_sel: emmc_sel { +- function = "emmc"; +- groups = "emmc_grp"; +- }; +-}; +- +-&pwm { +- status = "okay"; +-}; +- +-&qspi { +- bspi-sel = <0>; +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p80"; +- reg = <0x0>; +- spi-max-frequency = <12500000>; +- m25p,fast-read; +- spi-cpol; +- spi-cpha; +- +- partition@0 { +- label = "boot"; +- reg = <0x00000000 0x000a0000>; +- }; +- +- partition@a0000 { +- label = "env"; +- reg = <0x000a0000 0x00060000>; +- }; +- +- partition@100000 { +- label = "system"; +- reg = <0x00100000 0x00600000>; +- }; +- +- partition@700000 { +- label = "rootfs"; +- reg = <0x00700000 0x01900000>; +- }; +- }; +-}; +- +-&sata_phy0 { +- status = "okay"; +-}; +- +-&sata_phy1 { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-/* +- * By default the sd slot is functional. For emmc to work add "<&emmc_sel>" +- * and delete "<&nand_sel>" in "pinctrl-0" property of pinctrl node. Remove the +- * bus-width property here and disable the nand node with status = "disabled";. +- * +- * Ex: pinctrl-0 = <&emmc_sel>, <&gpiobs>, <&pwmc>; +- */ +-&sdio { +- bus-width = <4>; +- no-1-8-v; +- status = "okay"; +-}; +- +-&srab { +- compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; +- status = "okay"; +- +- ports { +- port@0 { +- label = "port0"; +- reg = <0>; +- }; +- +- port@1 { +- label = "port1"; +- reg = <1>; +- }; +- +- port@2 { +- label = "port2"; +- reg = <2>; +- }; +- +- port@3 { +- label = "port3"; +- reg = <3>; +- }; +- +- port@4 { +- label = "port4"; +- reg = <4>; +- }; +- +- port@8 { +- ethernet = <&amac2>; +- label = "cpu"; +- reg = <8>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&usb3_phy { +- status = "okay"; +-}; +- +-&xhci { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm963138dvt.dts b/scripts/dtc/include-prefixes/arm/bcm963138dvt.dts +deleted file mode 100644 +index df5c8ab90627..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm963138dvt.dts ++++ /dev/null +@@ -1,52 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Broadcom BCM63138 Reference Board DTS +- */ +- +-/dts-v1/; +- +-#include "bcm63138.dtsi" +- +-/ { +- compatible = "brcm,BCM963138DVT", "brcm,bcm63138"; +- model = "Broadcom BCM963138DVT"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &serial0; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x08000000>; +- }; +- +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&serial1 { +- status = "okay"; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@0 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- brcm,nand-oob-sectors-size = <16>; +- }; +-}; +- +-&ahci { +- status = "okay"; +-}; +- +-&sata_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm988312hr.dts b/scripts/dtc/include-prefixes/arm/bcm988312hr.dts +deleted file mode 100644 +index 5475dab8181d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm988312hr.dts ++++ /dev/null +@@ -1,226 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2016 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "bcm-nsp.dtsi" +-#include +- +-/ { +- model = "NorthStar Plus SVK (BCM988312HR)"; +- compatible = "brcm,bcm88312", "brcm,nsp"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x80000000>; +- }; +- +- gpio-restart { +- compatible = "gpio-restart"; +- gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; +- open-source; +- priority = <200>; +- }; +-}; +- +-/* USB 3 support needed to be complete */ +- +-&amac0 { +- status = "okay"; +-}; +- +-&amac1 { +- status = "okay"; +-}; +- +-&amac2 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&nand_controller { +- nand@0 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- nand-on-flash-bbt; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- nand-ecc-strength = <24>; +- nand-ecc-step-size = <1024>; +- +- brcm,nand-oob-sector-size = <27>; +- +- partition@0 { +- label = "nboot"; +- reg = <0x00000000 0x00200000>; +- read-only; +- }; +- partition@200000 { +- label = "nenv"; +- reg = <0x00200000 0x00400000>; +- }; +- partition@600000 { +- label = "nsystem"; +- reg = <0x00600000 0x00a00000>; +- }; +- partition@1000000 { +- label = "nrootfs"; +- reg = <0x01000000 0x03000000>; +- }; +- partition@4000000 { +- label = "ncustfs"; +- reg = <0x04000000 0x3c000000>; +- }; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&nand_sel>; +- nand_sel: nand_sel { +- function = "nand"; +- groups = "nand_grp"; +- }; +-}; +- +-&qspi { +- bspi-sel = <0>; +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p80"; +- reg = <0x0>; +- spi-max-frequency = <12500000>; +- m25p,fast-read; +- spi-cpol; +- spi-cpha; +- +- partition@0 { +- label = "boot"; +- reg = <0x00000000 0x000a0000>; +- }; +- +- partition@a0000 { +- label = "env"; +- reg = <0x000a0000 0x00060000>; +- }; +- +- partition@100000 { +- label = "system"; +- reg = <0x00100000 0x00600000>; +- }; +- +- partition@700000 { +- label = "rootfs"; +- reg = <0x00700000 0x01900000>; +- }; +- }; +-}; +- +-&sata_phy0 { +- status = "okay"; +-}; +- +-&sata_phy1 { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&srab { +- compatible = "brcm,bcm88312-srab", "brcm,nsp-srab"; +- status = "okay"; +- +- ports { +- port@0 { +- label = "port0"; +- reg = <0>; +- }; +- +- port@1 { +- label = "port1"; +- reg = <1>; +- }; +- +- port@2 { +- label = "port2"; +- reg = <2>; +- }; +- +- port@3 { +- label = "port3"; +- reg = <3>; +- }; +- +- port@4 { +- label = "port4"; +- reg = <4>; +- }; +- +- port@8 { +- ethernet = <&amac2>; +- label = "cpu"; +- reg = <8>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/bcm9hmidc.dtsi b/scripts/dtc/include-prefixes/arm/bcm9hmidc.dtsi +deleted file mode 100644 +index 65397c088335..000000000000 +--- a/scripts/dtc/include-prefixes/arm/bcm9hmidc.dtsi ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2015 Broadcom Corporation. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/* +- * Broadcom human machine interface daughter card (bcm9hmidc) installed on +- * bcm958300k/bcm958305k boards +- */ +- +-&touchscreen { +- touchscreen-inverted-x; +- touchscreen-inverted-y; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/berlin2-sony-nsz-gs7.dts b/scripts/dtc/include-prefixes/arm/berlin2-sony-nsz-gs7.dts +deleted file mode 100644 +index 64a297759eb9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/berlin2-sony-nsz-gs7.dts ++++ /dev/null +@@ -1,43 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for Sony NSZ-GS7 +- * +- * Sebastian Hesselbarth +- */ +- +-/dts-v1/; +- +-#include "berlin2.dtsi" +- +-/ { +- model = "Sony NSZ-GS7"; +- compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin"; +- +- chosen { +- bootargs = "earlyprintk"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x40000000>; /* 1 GB */ +- }; +-}; +- +-&ahci { status = "okay"; }; +- +-ð1 { status = "okay"; }; +- +-/* Unpopulated SATA plug on solder side */ +-&sata0 { status = "okay"; }; +- +-&sata_phy { status = "okay"; }; +- +-/* Samsung M8G2FA 8GB eMMC */ +-&sdhci2 { +- non-removable; +- bus-width = <8>; +- status = "okay"; +-}; +- +-&uart0 { status = "okay"; }; +diff --git a/scripts/dtc/include-prefixes/arm/berlin2.dtsi b/scripts/dtc/include-prefixes/arm/berlin2.dtsi +deleted file mode 100644 +index 1114c592e461..000000000000 +--- a/scripts/dtc/include-prefixes/arm/berlin2.dtsi ++++ /dev/null +@@ -1,540 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC +- * +- * Sebastian Hesselbarth +- * +- * based on GPL'ed 2.6 kernel sources +- * (c) Marvell International Ltd. +- */ +- +-#include +-#include +- +-/ { +- model = "Marvell Armada 1500 (BG2) SoC"; +- compatible = "marvell,berlin2", "marvell,berlin"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "marvell,berlin-smp"; +- +- cpu@0 { +- compatible = "marvell,pj4b"; +- device_type = "cpu"; +- next-level-cache = <&l2>; +- reg = <0>; +- +- clocks = <&chip_clk CLKID_CPU>; +- clock-latency = <100000>; +- operating-points = < +- /* kHz uV */ +- 1200000 1200000 +- 1000000 1200000 +- 800000 1200000 +- 600000 1200000 +- >; +- }; +- +- cpu@1 { +- compatible = "marvell,pj4b"; +- device_type = "cpu"; +- next-level-cache = <&l2>; +- reg = <1>; +- +- clocks = <&chip_clk CLKID_CPU>; +- clock-latency = <100000>; +- operating-points = < +- /* kHz uV */ +- 1200000 1200000 +- 1000000 1200000 +- 800000 1200000 +- 600000 1200000 +- >; +- }; +- }; +- +- refclk: oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- soc@f7000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&gic>; +- +- ranges = <0 0xf7000000 0x1000000>; +- +- sdhci0: mmc@ab0000 { +- compatible = "mrvl,pxav3-mmc"; +- reg = <0xab0000 0x200>; +- clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; +- clock-names = "io", "core"; +- interrupts = ; +- status = "disabled"; +- }; +- +- sdhci1: mmc@ab0800 { +- compatible = "mrvl,pxav3-mmc"; +- reg = <0xab0800 0x200>; +- clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>; +- clock-names = "io", "core"; +- interrupts = ; +- status = "disabled"; +- }; +- +- sdhci2: mmc@ab1000 { +- compatible = "mrvl,pxav3-mmc"; +- reg = <0xab1000 0x200>; +- interrupts = ; +- clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>; +- clock-names = "io", "core"; +- pinctrl-0 = <&emmc_pmux>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- l2: cache-controller@ac0000 { +- compatible = "marvell,tauros3-cache", "arm,pl310-cache"; +- reg = <0xac0000 0x1000>; +- cache-unified; +- cache-level = <2>; +- }; +- +- scu: snoop-control-unit@ad0000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0xad0000 0x58>; +- }; +- +- gic: interrupt-controller@ad1000 { +- compatible = "arm,cortex-a9-gic"; +- reg = <0xad1000 0x1000>, <0xad0100 0x0100>; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- +- local-timer@ad0600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0xad0600 0x20>; +- interrupts = ; +- clocks = <&chip_clk CLKID_TWD>; +- }; +- +- eth1: ethernet@b90000 { +- compatible = "marvell,pxa168-eth"; +- reg = <0xb90000 0x10000>; +- clocks = <&chip_clk CLKID_GETH1>; +- interrupts = ; +- /* set by bootloader */ +- local-mac-address = [00 00 00 00 00 00]; +- #address-cells = <1>; +- #size-cells = <0>; +- phy-connection-type = "mii"; +- phy-handle = <ðphy1>; +- status = "disabled"; +- +- ethphy1: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- cpu-ctrl@dd0000 { +- compatible = "marvell,berlin-cpu-ctrl"; +- reg = <0xdd0000 0x10000>; +- }; +- +- eth0: ethernet@e50000 { +- compatible = "marvell,pxa168-eth"; +- reg = <0xe50000 0x10000>; +- clocks = <&chip_clk CLKID_GETH0>; +- interrupts = ; +- /* set by bootloader */ +- local-mac-address = [00 00 00 00 00 00]; +- #address-cells = <1>; +- #size-cells = <0>; +- phy-connection-type = "mii"; +- phy-handle = <ðphy0>; +- status = "disabled"; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- apb@e80000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0 0xe80000 0x10000>; +- interrupt-parent = <&aic>; +- +- gpio0: gpio@400 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x0400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- porta: gpio-port@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <8>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <0>; +- }; +- }; +- +- gpio1: gpio@800 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x0800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- portb: gpio-port@1 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <8>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <1>; +- }; +- }; +- +- gpio2: gpio@c00 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x0c00 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- portc: gpio-port@2 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <8>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <2>; +- }; +- }; +- +- gpio3: gpio@1000 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x1000 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- portd: gpio-port@3 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <8>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <3>; +- }; +- }; +- +- timer0: timer@2c00 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c00 0x14>; +- interrupts = <8>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "okay"; +- }; +- +- timer1: timer@2c14 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c14 0x14>; +- interrupts = <9>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "okay"; +- }; +- +- timer2: timer@2c28 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c28 0x14>; +- interrupts = <10>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "disabled"; +- }; +- +- timer3: timer@2c3c { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c3c 0x14>; +- interrupts = <11>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "disabled"; +- }; +- +- timer4: timer@2c50 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c50 0x14>; +- interrupts = <12>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "disabled"; +- }; +- +- timer5: timer@2c64 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c64 0x14>; +- interrupts = <13>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "disabled"; +- }; +- +- timer6: timer@2c78 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c78 0x14>; +- interrupts = <14>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "disabled"; +- }; +- +- timer7: timer@2c8c { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c8c 0x14>; +- interrupts = <15>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "disabled"; +- }; +- +- aic: interrupt-controller@3000 { +- compatible = "snps,dw-apb-ictl"; +- reg = <0x3000 0xc00>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +- +- ahci: sata@e90000 { +- compatible = "marvell,berlin2-ahci", "generic-ahci"; +- reg = <0xe90000 0x1000>; +- interrupts = ; +- clocks = <&chip_clk CLKID_SATA>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- sata0: sata-port@0 { +- reg = <0>; +- phys = <&sata_phy 0>; +- status = "disabled"; +- }; +- +- sata1: sata-port@1 { +- reg = <1>; +- phys = <&sata_phy 1>; +- status = "disabled"; +- }; +- }; +- +- sata_phy: phy@e900a0 { +- compatible = "marvell,berlin2-sata-phy"; +- reg = <0xe900a0 0x200>; +- clocks = <&chip_clk CLKID_SATA>; +- #address-cells = <1>; +- #size-cells = <0>; +- #phy-cells = <1>; +- status = "disabled"; +- +- sata-phy@0 { +- reg = <0>; +- }; +- +- sata-phy@1 { +- reg = <1>; +- }; +- }; +- +- chip: chip-control@ea0000 { +- compatible = "simple-mfd", "syscon"; +- reg = <0xea0000 0x400>; +- +- chip_clk: clock { +- compatible = "marvell,berlin2-clk"; +- #clock-cells = <1>; +- clocks = <&refclk>; +- clock-names = "refclk"; +- }; +- +- soc_pinctrl: pin-controller { +- compatible = "marvell,berlin2-soc-pinctrl"; +- +- emmc_pmux: emmc-pmux { +- groups = "G26"; +- function = "emmc"; +- }; +- }; +- +- chip_rst: reset { +- compatible = "marvell,berlin2-reset"; +- #reset-cells = <2>; +- }; +- }; +- +- pwm: pwm@f20000 { +- compatible = "marvell,berlin-pwm"; +- reg = <0xf20000 0x40>; +- clocks = <&chip_clk CLKID_CFG>; +- #pwm-cells = <3>; +- }; +- +- apb@fc0000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0 0xfc0000 0x10000>; +- interrupt-parent = <&sic>; +- +- wdt0: watchdog@1000 { +- compatible = "snps,dw-wdt"; +- reg = <0x1000 0x100>; +- clocks = <&refclk>; +- interrupts = <0>; +- }; +- +- wdt1: watchdog@2000 { +- compatible = "snps,dw-wdt"; +- reg = <0x2000 0x100>; +- clocks = <&refclk>; +- interrupts = <1>; +- }; +- +- wdt2: watchdog@3000 { +- compatible = "snps,dw-wdt"; +- reg = <0x3000 0x100>; +- clocks = <&refclk>; +- interrupts = <2>; +- }; +- +- sm_gpio1: gpio@5000 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x5000 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- portf: gpio-port@5 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <8>; +- reg = <0>; +- }; +- }; +- +- sm_gpio0: gpio@c000 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0xc000 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- porte: gpio-port@4 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <8>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <11>; +- }; +- }; +- +- uart0: serial@9000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x9000 0x100>; +- reg-shift = <2>; +- reg-io-width = <1>; +- interrupts = <8>; +- clocks = <&refclk>; +- pinctrl-0 = <&uart0_pmux>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- uart1: serial@a000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0xa000 0x100>; +- reg-shift = <2>; +- reg-io-width = <1>; +- interrupts = <9>; +- clocks = <&refclk>; +- pinctrl-0 = <&uart1_pmux>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- uart2: serial@b000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0xb000 0x100>; +- reg-shift = <2>; +- reg-io-width = <1>; +- interrupts = <10>; +- clocks = <&refclk>; +- pinctrl-0 = <&uart2_pmux>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- sysctrl: system-controller@d000 { +- compatible = "simple-mfd", "syscon"; +- reg = <0xd000 0x100>; +- +- sys_pinctrl: pin-controller { +- compatible = "marvell,berlin2-system-pinctrl"; +- uart0_pmux: uart0-pmux { +- groups = "GSM4"; +- function = "uart0"; +- }; +- +- uart1_pmux: uart1-pmux { +- groups = "GSM5"; +- function = "uart1"; +- }; +- uart2_pmux: uart2-pmux { +- groups = "GSM3"; +- function = "uart2"; +- }; +- }; +- }; +- +- sic: interrupt-controller@e000 { +- compatible = "snps,dw-apb-ictl"; +- reg = <0xe000 0x400>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/berlin2cd-google-chromecast.dts b/scripts/dtc/include-prefixes/arm/berlin2cd-google-chromecast.dts +deleted file mode 100644 +index c1d91424e658..000000000000 +--- a/scripts/dtc/include-prefixes/arm/berlin2cd-google-chromecast.dts ++++ /dev/null +@@ -1,77 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for Google Chromecast +- * +- * Sebastian Hesselbarth +- */ +- +-/dts-v1/; +- +-#include "berlin2cd.dtsi" +-#include +- +-/ { +- model = "Google Chromecast"; +- compatible = "google,chromecast", "marvell,berlin2cd", "marvell,berlin"; +- +- chosen { +- bootargs = "earlyprintk"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- +- /* +- * We're using "linux,usable-memory" instead of "reg" here +- * because the (signed and encrypted) bootloader that shipped +- * with this device provides an incorrect memory range in +- * ATAG_MEM. Linux helpfully overrides the "reg" property with +- * data from the ATAG, so we can't specify the proper range +- * normally. Fortunately, this alternate property is checked +- * first by the OF driver, so we can (ab)use it instead. +- */ +- linux,usable-memory = <0x00000000 0x20000000>; /* 512 MB */ +- }; +- +- led-controller { +- compatible = "pwm-leds"; +- pinctrl-0 = <&ledpwm_pmux>; +- pinctrl-names = "default"; +- +- led-1 { +- label = "white"; +- pwms = <&pwm 0 600000 0>; +- max-brightness = <255>; +- linux,default-trigger = "default-on"; +- }; +- +- led-2 { +- label = "red"; +- pwms = <&pwm 1 600000 0>; +- max-brightness = <255>; +- }; +- }; +-}; +- +-/* +- * AzureWave AW-NH387 (Marvell 88W8787) +- * 802.11b/g/n + Bluetooth 2.1 +- */ +-&sdhci0 { +- non-removable; +- status = "okay"; +-}; +- +-&uart0 { status = "okay"; }; +- +-&usb_phy1 { status = "okay"; }; +- +-&usb1 { status = "okay"; }; +- +-&soc_pinctrl { +- ledpwm_pmux: ledpwm-pmux { +- groups = "G0"; +- function = "pwm"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/berlin2cd-valve-steamlink.dts b/scripts/dtc/include-prefixes/arm/berlin2cd-valve-steamlink.dts +deleted file mode 100644 +index 79ac842ae461..000000000000 +--- a/scripts/dtc/include-prefixes/arm/berlin2cd-valve-steamlink.dts ++++ /dev/null +@@ -1,79 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2018 Alexander Monakov +- */ +-/dts-v1/; +- +-#include "berlin2cd.dtsi" +-#include +- +-/ { +- model = "Valve Steam Link"; +- compatible = "valve,steamlink", "marvell,berlin2cd", "marvell,berlin"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; /* 512 MB */ +- }; +- +- gpio-restart { +- compatible = "gpio-restart"; +- gpios = <&porta 6 GPIO_ACTIVE_HIGH>; +- active-delay = <100>; +- inactive-delay = <10>; +- wait-delay = <100>; +- priority = <200>; +- }; +-}; +- +-&cpu { +- cpu-supply = <&vcpu>; +- operating-points = < +- /* kHz uV */ +- 1000000 1325000 +- >; +-}; +- +-&i2c0 { +- status = "okay"; +- +- /* There are two regulators on the board. One is accessible via I2C, +- * with buck1 providing SoC power (set up by bootloader to 1.325V or +- * less depending on leakage value in OTP), and buck2 likely used for +- * DRAM (providing 1.35V). The other regulator on the opposite side +- * of the board is probably supplying SDIO and NAND fixed voltages. */ +- regulator@19 { +- compatible = "marvell,88pg868"; +- reg = <0x19>; +- +- vcpu: buck1 { +- regulator-boot-on; +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1325000>; +- }; +- }; +-}; +- +-/* Fixed interface to on-board Marvell 8897 Wi-Fi/Bluetooth/NFC chip. */ +-&sdhci0 { +- keep-power-in-suspend; +- non-removable; +- status = "okay"; +-}; +- +-&uart0 { +- /* RX/TX are routed to TP50/TP51 on the board. */ +- status = "okay"; +-}; +- +-/* The SoC is connected to on-board USB hub that in turn has one downstream +- * port wired to the on-board Steam Controller wireless receiver chip. */ +-&usb_phy1 { status = "okay"; }; +- +-&usb1 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-ð1 { status = "okay"; }; +diff --git a/scripts/dtc/include-prefixes/arm/berlin2cd.dtsi b/scripts/dtc/include-prefixes/arm/berlin2cd.dtsi +deleted file mode 100644 +index b2768f7a3185..000000000000 +--- a/scripts/dtc/include-prefixes/arm/berlin2cd.dtsi ++++ /dev/null +@@ -1,583 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC +- * +- * Sebastian Hesselbarth +- * +- * based on GPL'ed 2.6 kernel sources +- * (c) Marvell International Ltd. +- */ +- +-#include +-#include +- +-/ { +- model = "Marvell Armada 1500-mini (BG2CD) SoC"; +- compatible = "marvell,berlin2cd", "marvell,berlin"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu: cpu@0 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- next-level-cache = <&l2>; +- reg = <0>; +- +- clocks = <&chip_clk CLKID_CPU>; +- clock-latency = <100000>; +- operating-points = < +- /* kHz uV */ +- 800000 1200000 +- 600000 1200000 +- >; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- +- refclk: oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- soc@f7000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&gic>; +- +- ranges = <0 0xf7000000 0x1000000>; +- +- sdhci0: mmc@ab0000 { +- compatible = "mrvl,pxav3-mmc"; +- reg = <0xab0000 0x200>; +- clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; +- clock-names = "io", "core"; +- interrupts = ; +- status = "disabled"; +- }; +- +- l2: cache-controller@ac0000 { +- compatible = "arm,pl310-cache"; +- reg = <0xac0000 0x1000>; +- cache-unified; +- cache-level = <2>; +- }; +- +- snoop-control-unit@ad0000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0xad0000 0x100>; +- }; +- +- gic: interrupt-controller@ad1000 { +- compatible = "arm,cortex-a9-gic"; +- reg = <0xad1000 0x1000>, <0xad0100 0x0100>; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- +- global-timer@ad0200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0xad0200 0x20>; +- interrupts = ; +- clocks = <&chip_clk CLKID_TWD>; +- }; +- +- local-timer@ad0600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0xad0600 0x20>; +- interrupts = ; +- clocks = <&chip_clk CLKID_TWD>; +- }; +- +- local-wdt@ad0620 { +- compatible = "arm,cortex-a9-twd-wdt"; +- reg = <0xad0620 0x20>; +- interrupts = ; +- clocks = <&chip_clk CLKID_TWD>; +- }; +- +- usb_phy0: usb-phy@b74000 { +- compatible = "marvell,berlin2cd-usb-phy"; +- reg = <0xb74000 0x128>; +- #phy-cells = <0>; +- resets = <&chip_rst 0x178 23>; +- status = "disabled"; +- }; +- +- usb_phy1: usb-phy@b78000 { +- compatible = "marvell,berlin2cd-usb-phy"; +- reg = <0xb78000 0x128>; +- #phy-cells = <0>; +- resets = <&chip_rst 0x178 24>; +- status = "disabled"; +- }; +- +- eth1: ethernet@b90000 { +- compatible = "marvell,pxa168-eth"; +- reg = <0xb90000 0x10000>; +- clocks = <&chip_clk CLKID_GETH1>; +- interrupts = ; +- /* set by bootloader */ +- local-mac-address = [00 00 00 00 00 00]; +- #address-cells = <1>; +- #size-cells = <0>; +- phy-connection-type = "mii"; +- phy-handle = <ðphy1>; +- status = "disabled"; +- +- ethphy1: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- eth0: ethernet@e50000 { +- compatible = "marvell,pxa168-eth"; +- reg = <0xe50000 0x10000>; +- clocks = <&chip_clk CLKID_GETH0>; +- interrupts = ; +- /* set by bootloader */ +- local-mac-address = [00 00 00 00 00 00]; +- #address-cells = <1>; +- #size-cells = <0>; +- phy-connection-type = "mii"; +- phy-handle = <ðphy0>; +- status = "disabled"; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- apb@e80000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0 0xe80000 0x10000>; +- interrupt-parent = <&aic>; +- +- gpio0: gpio@400 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x0400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- porta: gpio-port@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <8>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <0>; +- }; +- }; +- +- gpio1: gpio@800 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x0800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- portb: gpio-port@1 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <8>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <1>; +- }; +- }; +- +- gpio2: gpio@c00 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x0c00 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- portc: gpio-port@2 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <8>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <2>; +- }; +- }; +- +- gpio3: gpio@1000 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x1000 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- portd: gpio-port@3 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <8>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <3>; +- }; +- }; +- +- i2c0: i2c@1400 { +- compatible = "snps,designware-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x1400 0x100>; +- interrupts = <16>; +- clocks = <&chip_clk CLKID_CFG>; +- status = "disabled"; +- }; +- +- i2c1: i2c@1800 { +- compatible = "snps,designware-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x1800 0x100>; +- interrupts = <17>; +- clocks = <&chip_clk CLKID_CFG>; +- status = "disabled"; +- }; +- +- spi0: spi@1c00 { +- compatible = "snps,dw-apb-ssi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x1c00 0x100>; +- interrupts = <4>; +- clocks = <&chip_clk CLKID_CFG>; +- status = "disabled"; +- }; +- +- wdt4: watchdog@2000 { +- compatible = "snps,dw-wdt"; +- reg = <0x2000 0x100>; +- clocks = <&chip_clk CLKID_CFG>; +- interrupts = <5>; +- status = "disabled"; +- }; +- +- wdt5: watchdog@2400 { +- compatible = "snps,dw-wdt"; +- reg = <0x2400 0x100>; +- clocks = <&chip_clk CLKID_CFG>; +- interrupts = <6>; +- status = "disabled"; +- }; +- +- wdt6: watchdog@2800 { +- compatible = "snps,dw-wdt"; +- reg = <0x2800 0x100>; +- clocks = <&chip_clk CLKID_CFG>; +- interrupts = <7>; +- status = "disabled"; +- }; +- +- timer0: timer@2c00 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c00 0x14>; +- interrupts = <8>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "okay"; +- }; +- +- timer1: timer@2c14 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c14 0x14>; +- interrupts = <9>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "okay"; +- }; +- +- timer2: timer@2c28 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c28 0x14>; +- interrupts = <10>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "disabled"; +- }; +- +- timer3: timer@2c3c { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c3c 0x14>; +- interrupts = <11>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "disabled"; +- }; +- +- timer4: timer@2c50 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c50 0x14>; +- interrupts = <12>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "disabled"; +- }; +- +- timer5: timer@2c64 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c64 0x14>; +- interrupts = <13>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "disabled"; +- }; +- +- timer6: timer@2c78 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c78 0x14>; +- interrupts = <14>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "disabled"; +- }; +- +- timer7: timer@2c8c { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c8c 0x14>; +- interrupts = <15>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "disabled"; +- }; +- +- aic: interrupt-controller@3000 { +- compatible = "snps,dw-apb-ictl"; +- reg = <0x3000 0xc00>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +- +- chip: chip-control@ea0000 { +- compatible = "simple-mfd", "syscon"; +- reg = <0xea0000 0x400>; +- +- chip_clk: clock { +- compatible = "marvell,berlin2-clk"; +- #clock-cells = <1>; +- clocks = <&refclk>; +- clock-names = "refclk"; +- }; +- +- soc_pinctrl: pin-controller { +- compatible = "marvell,berlin2cd-soc-pinctrl"; +- +- uart0_pmux: uart0-pmux { +- groups = "G6"; +- function = "uart0"; +- }; +- }; +- +- chip_rst: reset { +- compatible = "marvell,berlin2-reset"; +- #reset-cells = <2>; +- }; +- }; +- +- usb0: usb@ed0000 { +- compatible = "chipidea,usb2"; +- reg = <0xed0000 0x200>; +- interrupts = ; +- clocks = <&chip_clk CLKID_USB0>; +- phys = <&usb_phy0>; +- phy-names = "usb-phy"; +- status = "disabled"; +- }; +- +- usb1: usb@ee0000 { +- compatible = "chipidea,usb2"; +- reg = <0xee0000 0x200>; +- interrupts = ; +- clocks = <&chip_clk CLKID_USB1>; +- phys = <&usb_phy1>; +- phy-names = "usb-phy"; +- status = "disabled"; +- }; +- +- pwm: pwm@f20000 { +- compatible = "marvell,berlin-pwm"; +- reg = <0xf20000 0x40>; +- clocks = <&chip_clk CLKID_CFG>; +- #pwm-cells = <3>; +- }; +- +- apb@fc0000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0 0xfc0000 0x10000>; +- interrupt-parent = <&sic>; +- +- wdt0: watchdog@1000 { +- compatible = "snps,dw-wdt"; +- reg = <0x1000 0x100>; +- clocks = <&refclk>; +- interrupts = <0>; +- }; +- +- wdt1: watchdog@2000 { +- compatible = "snps,dw-wdt"; +- reg = <0x2000 0x100>; +- clocks = <&refclk>; +- interrupts = <1>; +- status = "disabled"; +- }; +- +- wdt2: watchdog@3000 { +- compatible = "snps,dw-wdt"; +- reg = <0x3000 0x100>; +- clocks = <&refclk>; +- interrupts = <2>; +- status = "disabled"; +- }; +- +- sm_gpio1: gpio@5000 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x5000 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- portf: gpio-port@5 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <8>; +- reg = <0>; +- }; +- }; +- +- spi1: spi@6000 { +- compatible = "snps,dw-apb-ssi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x6000 0x100>; +- clocks = <&refclk>; +- interrupts = <5>; +- status = "disabled"; +- }; +- +- i2c2: i2c@7000 { +- compatible = "snps,designware-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x7000 0x100>; +- interrupts = <6>; +- clocks = <&refclk>; +- status = "disabled"; +- }; +- +- i2c3: i2c@8000 { +- compatible = "snps,designware-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x8000 0x100>; +- interrupts = <7>; +- clocks = <&refclk>; +- status = "disabled"; +- }; +- +- sm_gpio0: gpio@c000 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0xc000 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- porte: gpio-port@4 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <8>; +- reg = <0>; +- }; +- }; +- +- uart0: serial@9000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x9000 0x100>; +- reg-shift = <2>; +- reg-io-width = <1>; +- interrupts = <8>; +- clocks = <&refclk>; +- pinctrl-0 = <&uart0_pmux>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- uart1: serial@a000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0xa000 0x100>; +- reg-shift = <2>; +- reg-io-width = <1>; +- interrupts = <9>; +- clocks = <&refclk>; +- status = "disabled"; +- }; +- +- uart2: serial@b000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0xb000 0x100>; +- reg-shift = <2>; +- reg-io-width = <1>; +- interrupts = <10>; +- clocks = <&refclk>; +- status = "disabled"; +- }; +- +- sysctrl: system-controller@d000 { +- compatible = "simple-mfd", "syscon"; +- reg = <0xd000 0x100>; +- +- sys_pinctrl: pin-controller { +- compatible = "marvell,berlin2cd-system-pinctrl"; +- }; +- +- adc: adc { +- compatible = "marvell,berlin2-adc"; +- interrupts = <12>, <14>; +- interrupt-names = "adc", "tsen"; +- }; +- }; +- +- sic: interrupt-controller@e000 { +- compatible = "snps,dw-apb-ictl"; +- reg = <0xe000 0x400>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/berlin2q-marvell-dmp.dts b/scripts/dtc/include-prefixes/arm/berlin2q-marvell-dmp.dts +deleted file mode 100644 +index c162f98cb8e8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/berlin2q-marvell-dmp.dts ++++ /dev/null +@@ -1,144 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2014 Antoine Ténart +- */ +- +-/dts-v1/; +- +-#include +-#include "berlin2q.dtsi" +- +-/ { +- model = "Marvell BG2-Q DMP"; +- compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x80000000>; +- }; +- +- chosen { +- bootargs = "earlyprintk"; +- stdout-path = "serial0:115200n8"; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_usb0_vbus: regulator_usb0 { +- compatible = "regulator-fixed"; +- regulator-name = "usb0_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&portb 8 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb1_vbus: regulator_usb1 { +- compatible = "regulator-fixed"; +- regulator-name = "usb1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&portb 10 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb2_vbus: regulator_usb2 { +- compatible = "regulator-fixed"; +- regulator-name = "usb2_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&portb 12 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_sdio1_vmmc: regulator_sdio1_vmmc { +- compatible = "regulator-fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "sdio1_vmmc"; +- enable-active-high; +- regulator-boot-on; +- gpio = <&portb 21 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_sdio1_vqmmc: regulator_sido1_vqmmc { +- compatible = "regulator-gpio"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "sdio1_vqmmc"; +- regulator-type = "voltage"; +- enable-active-high; +- gpios = <&portb 16 GPIO_ACTIVE_HIGH>; +- states = <3300000 0x1 +- 1800000 0x0>; +- }; +- }; +-}; +- +-&soc_pinctrl { +- sd1gpio_pmux: sd1pwr-pmux { +- groups = "G23", "G32"; +- function = "gpio"; +- }; +-}; +- +-&sdhci1 { +- vmmc-supply = <®_sdio1_vmmc>; +- vqmmc-supply = <®_sdio1_vqmmc>; +- cd-gpios = <&portc 30 GPIO_ACTIVE_LOW>; +- wp-gpios = <&portd 0 GPIO_ACTIVE_HIGH>; +- pinctrl-0 = <&sd1gpio_pmux>, <&sd1_pmux>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&sdhci2 { +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&usb_phy0 { +- status = "okay"; +-}; +- +-&usb_phy2 { +- status = "okay"; +-}; +- +-&usb0 { +- vbus-supply = <®_usb0_vbus>; +- status = "okay"; +-}; +- +-&usb2 { +- vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +- +-ð0 { +- status = "okay"; +-}; +- +-&sata0 { +- status = "okay"; +-}; +- +-&sata_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/berlin2q.dtsi b/scripts/dtc/include-prefixes/arm/berlin2q.dtsi +deleted file mode 100644 +index 598a46f96a82..000000000000 +--- a/scripts/dtc/include-prefixes/arm/berlin2q.dtsi ++++ /dev/null +@@ -1,666 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2014 Antoine Ténart +- */ +- +-#include +-#include +- +-/ { +- model = "Marvell Armada 1500 pro (BG2-Q) SoC"; +- compatible = "marvell,berlin2q", "marvell,berlin"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "marvell,berlin-smp"; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- next-level-cache = <&l2>; +- reg = <0>; +- +- clocks = <&chip_clk CLKID_CPU>; +- clock-latency = <100000>; +- /* Can be modified by the bootloader */ +- operating-points = < +- /* kHz uV */ +- 1200000 1200000 +- 1000000 1200000 +- 800000 1200000 +- 600000 1200000 +- >; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- next-level-cache = <&l2>; +- reg = <1>; +- +- clocks = <&chip_clk CLKID_CPU>; +- clock-latency = <100000>; +- /* Can be modified by the bootloader */ +- operating-points = < +- /* kHz uV */ +- 1200000 1200000 +- 1000000 1200000 +- 800000 1200000 +- 600000 1200000 +- >; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- next-level-cache = <&l2>; +- reg = <2>; +- +- clocks = <&chip_clk CLKID_CPU>; +- clock-latency = <100000>; +- /* Can be modified by the bootloader */ +- operating-points = < +- /* kHz uV */ +- 1200000 1200000 +- 1000000 1200000 +- 800000 1200000 +- 600000 1200000 +- >; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- next-level-cache = <&l2>; +- reg = <3>; +- +- clocks = <&chip_clk CLKID_CPU>; +- clock-latency = <100000>; +- /* Can be modified by the bootloader */ +- operating-points = < +- /* kHz uV */ +- 1200000 1200000 +- 1000000 1200000 +- 800000 1200000 +- 600000 1200000 +- >; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, +- <&cpu1>, +- <&cpu2>, +- <&cpu3>; +- }; +- +- refclk: oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- soc@f7000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0 0xf7000000 0x1000000>; +- interrupt-parent = <&gic>; +- +- sdhci0: mmc@ab0000 { +- compatible = "mrvl,pxav3-mmc"; +- reg = <0xab0000 0x200>; +- clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; +- clock-names = "io", "core"; +- interrupts = ; +- status = "disabled"; +- }; +- +- sdhci1: mmc@ab0800 { +- compatible = "mrvl,pxav3-mmc"; +- reg = <0xab0800 0x200>; +- clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; +- clock-names = "io", "core"; +- interrupts = ; +- status = "disabled"; +- }; +- +- sdhci2: mmc@ab1000 { +- compatible = "mrvl,pxav3-mmc"; +- reg = <0xab1000 0x200>; +- interrupts = ; +- clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_SDIO>; +- clock-names = "io", "core"; +- status = "disabled"; +- }; +- +- l2: cache-controller@ac0000 { +- compatible = "arm,pl310-cache"; +- reg = <0xac0000 0x1000>; +- cache-unified; +- cache-level = <2>; +- arm,data-latency = <2 2 2>; +- arm,tag-latency = <2 2 2>; +- }; +- +- scu: snoop-control-unit@ad0000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0xad0000 0x58>; +- }; +- +- local-timer@ad0600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0xad0600 0x20>; +- clocks = <&chip_clk CLKID_TWD>; +- interrupts = ; +- }; +- +- gic: interrupt-controller@ad1000 { +- compatible = "arm,cortex-a9-gic"; +- reg = <0xad1000 0x1000>, <0xad0100 0x100>; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- +- usb_phy2: phy@a2f400 { +- compatible = "marvell,berlin2cd-usb-phy"; +- reg = <0xa2f400 0x128>; +- #phy-cells = <0>; +- resets = <&chip_rst 0x104 14>; +- status = "disabled"; +- }; +- +- usb2: usb@a30000 { +- compatible = "chipidea,usb2"; +- reg = <0xa30000 0x10000>; +- interrupts = ; +- clocks = <&chip_clk CLKID_USB2>; +- phys = <&usb_phy2>; +- phy-names = "usb-phy"; +- status = "disabled"; +- }; +- +- usb_phy0: phy@b74000 { +- compatible = "marvell,berlin2cd-usb-phy"; +- reg = <0xb74000 0x128>; +- #phy-cells = <0>; +- resets = <&chip_rst 0x104 12>; +- status = "disabled"; +- }; +- +- usb_phy1: phy@b78000 { +- compatible = "marvell,berlin2cd-usb-phy"; +- reg = <0xb78000 0x128>; +- #phy-cells = <0>; +- resets = <&chip_rst 0x104 13>; +- status = "disabled"; +- }; +- +- eth0: ethernet@b90000 { +- compatible = "marvell,pxa168-eth"; +- reg = <0xb90000 0x10000>; +- clocks = <&chip_clk CLKID_GETH0>; +- interrupts = ; +- /* set by bootloader */ +- local-mac-address = [00 00 00 00 00 00]; +- #address-cells = <1>; +- #size-cells = <0>; +- phy-connection-type = "mii"; +- phy-handle = <ðphy0>; +- status = "disabled"; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- cpu-ctrl@dd0000 { +- compatible = "marvell,berlin-cpu-ctrl"; +- reg = <0xdd0000 0x10000>; +- }; +- +- apb@e80000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0 0xe80000 0x10000>; +- interrupt-parent = <&aic>; +- +- gpio0: gpio@400 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x0400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- porta: gpio-port@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <0>; +- }; +- }; +- +- gpio1: gpio@800 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x0800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- portb: gpio-port@1 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <1>; +- }; +- }; +- +- gpio2: gpio@c00 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x0c00 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- portc: gpio-port@2 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <2>; +- }; +- }; +- +- gpio3: gpio@1000 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x1000 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- portd: gpio-port@3 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <3>; +- }; +- }; +- +- i2c0: i2c@1400 { +- compatible = "snps,designware-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x1400 0x100>; +- interrupts = <4>; +- clocks = <&chip_clk CLKID_CFG>; +- pinctrl-0 = <&twsi0_pmux>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- i2c1: i2c@1800 { +- compatible = "snps,designware-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x1800 0x100>; +- interrupts = <5>; +- clocks = <&chip_clk CLKID_CFG>; +- pinctrl-0 = <&twsi1_pmux>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- timer0: timer@2c00 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c00 0x14>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- interrupts = <8>; +- }; +- +- timer1: timer@2c14 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c14 0x14>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- }; +- +- timer2: timer@2c28 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c28 0x14>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "disabled"; +- }; +- +- timer3: timer@2c3c { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c3c 0x14>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "disabled"; +- }; +- +- timer4: timer@2c50 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c50 0x14>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "disabled"; +- }; +- +- timer5: timer@2c64 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c64 0x14>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "disabled"; +- }; +- +- timer6: timer@2c78 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c78 0x14>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "disabled"; +- }; +- +- timer7: timer@2c8c { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2c8c 0x14>; +- clocks = <&chip_clk CLKID_CFG>; +- clock-names = "timer"; +- status = "disabled"; +- }; +- +- aic: interrupt-controller@3800 { +- compatible = "snps,dw-apb-ictl"; +- reg = <0x3800 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +- +- chip: chip-control@ea0000 { +- compatible = "simple-mfd", "syscon"; +- reg = <0xea0000 0x400>, <0xdd0170 0x10>; +- +- chip_clk: clock { +- compatible = "marvell,berlin2q-clk"; +- #clock-cells = <1>; +- clocks = <&refclk>; +- clock-names = "refclk"; +- }; +- +- soc_pinctrl: pin-controller { +- compatible = "marvell,berlin2q-soc-pinctrl"; +- +- sd1_pmux: sd1-pmux { +- groups = "G31"; +- function = "sd1"; +- }; +- +- twsi0_pmux: twsi0-pmux { +- groups = "G6"; +- function = "twsi0"; +- }; +- +- twsi1_pmux: twsi1-pmux { +- groups = "G7"; +- function = "twsi1"; +- }; +- }; +- +- chip_rst: reset { +- compatible = "marvell,berlin2-reset"; +- #reset-cells = <2>; +- }; +- }; +- +- ahci: sata@e90000 { +- compatible = "marvell,berlin2q-ahci", "generic-ahci"; +- reg = <0xe90000 0x1000>; +- interrupts = ; +- clocks = <&chip_clk CLKID_SATA>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- sata0: sata-port@0 { +- reg = <0>; +- phys = <&sata_phy 0>; +- status = "disabled"; +- }; +- +- sata1: sata-port@1 { +- reg = <1>; +- phys = <&sata_phy 1>; +- status = "disabled"; +- }; +- }; +- +- sata_phy: phy@e900a0 { +- compatible = "marvell,berlin2q-sata-phy"; +- reg = <0xe900a0 0x200>; +- clocks = <&chip_clk CLKID_SATA>; +- #address-cells = <1>; +- #size-cells = <0>; +- #phy-cells = <1>; +- status = "disabled"; +- +- sata-phy@0 { +- reg = <0>; +- }; +- +- sata-phy@1 { +- reg = <1>; +- }; +- }; +- +- usb0: usb@ed0000 { +- compatible = "chipidea,usb2"; +- reg = <0xed0000 0x10000>; +- interrupts = ; +- clocks = <&chip_clk CLKID_USB0>; +- phys = <&usb_phy0>; +- phy-names = "usb-phy"; +- status = "disabled"; +- }; +- +- usb1: usb@ee0000 { +- compatible = "chipidea,usb2"; +- reg = <0xee0000 0x10000>; +- interrupts = ; +- clocks = <&chip_clk CLKID_USB1>; +- phys = <&usb_phy1>; +- phy-names = "usb-phy"; +- status = "disabled"; +- }; +- +- pwm: pwm@f20000 { +- compatible = "marvell,berlin-pwm"; +- reg = <0xf20000 0x40>; +- clocks = <&chip_clk CLKID_CFG>; +- #pwm-cells = <3>; +- }; +- +- apb@fc0000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0 0xfc0000 0x10000>; +- interrupt-parent = <&sic>; +- +- wdt0: watchdog@1000 { +- compatible = "snps,dw-wdt"; +- reg = <0x1000 0x100>; +- clocks = <&refclk>; +- interrupts = <0>; +- }; +- +- wdt1: watchdog@2000 { +- compatible = "snps,dw-wdt"; +- reg = <0x2000 0x100>; +- clocks = <&refclk>; +- interrupts = <1>; +- }; +- +- wdt2: watchdog@3000 { +- compatible = "snps,dw-wdt"; +- reg = <0x3000 0x100>; +- clocks = <&refclk>; +- interrupts = <2>; +- }; +- +- sm_gpio1: gpio@5000 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x5000 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- portf: gpio-port@5 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- reg = <0>; +- }; +- }; +- +- i2c2: i2c@7000 { +- compatible = "snps,designware-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x7000 0x100>; +- interrupts = <6>; +- clocks = <&refclk>; +- pinctrl-0 = <&twsi2_pmux>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- i2c3: i2c@8000 { +- compatible = "snps,designware-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x8000 0x100>; +- interrupts = <7>; +- clocks = <&refclk>; +- pinctrl-0 = <&twsi3_pmux>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- uart0: uart@9000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x9000 0x100>; +- interrupts = <8>; +- clocks = <&refclk>; +- reg-shift = <2>; +- pinctrl-0 = <&uart0_pmux>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- uart1: uart@a000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0xa000 0x100>; +- interrupts = <9>; +- clocks = <&refclk>; +- reg-shift = <2>; +- pinctrl-0 = <&uart1_pmux>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- sm_gpio0: gpio@c000 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0xc000 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- porte: gpio-port@4 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- reg = <0>; +- }; +- }; +- +- sysctrl: pin-controller@d000 { +- compatible = "simple-mfd", "syscon"; +- reg = <0xd000 0x100>; +- +- sys_pinctrl: pin-controller { +- compatible = "marvell,berlin2q-system-pinctrl"; +- +- uart0_pmux: uart0-pmux { +- groups = "GSM12"; +- function = "uart0"; +- }; +- +- uart1_pmux: uart1-pmux { +- groups = "GSM14"; +- function = "uart1"; +- }; +- +- twsi2_pmux: twsi2-pmux { +- groups = "GSM13"; +- function = "twsi2"; +- }; +- +- twsi3_pmux: twsi3-pmux { +- groups = "GSM14"; +- function = "twsi3"; +- }; +- }; +- +- adc: adc { +- compatible = "marvell,berlin2-adc"; +- interrupts = <12>, <14>; +- interrupt-names = "adc", "tsen"; +- }; +- }; +- +- sic: interrupt-controller@e000 { +- compatible = "snps,dw-apb-ictl"; +- reg = <0xe000 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/compulab-sb-som.dtsi b/scripts/dtc/include-prefixes/arm/compulab-sb-som.dtsi +deleted file mode 100644 +index f5e6216718d8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/compulab-sb-som.dtsi ++++ /dev/null +@@ -1,46 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ +- */ +- +-/ { +- model = "CompuLab SB-SOM"; +- compatible = "compulab,sb-som"; +- +- vsb_3v3: fixedregulator-v3_3 { +- compatible = "regulator-fixed"; +- regulator-name = "vsb_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- enable-active-high; +- }; +- +- lcd0: display { +- compatible = "startek,startek-kd050c", "panel-dpi"; +- label = "lcd"; +- +- panel-timing { +- clock-frequency = <33000000>; +- hactive = <800>; +- vactive = <480>; +- hfront-porch = <40>; +- hback-porch = <40>; +- hsync-len = <43>; +- vback-porch = <29>; +- vfront-porch = <13>; +- vsync-len = <3>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- +- hdmi_conn: connector { +- compatible = "hdmi-connector"; +- label = "hdmi"; +- +- type = "a"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/cros-adc-thermistors.dtsi b/scripts/dtc/include-prefixes/arm/cros-adc-thermistors.dtsi +deleted file mode 100644 +index 97e616f7b841..000000000000 +--- a/scripts/dtc/include-prefixes/arm/cros-adc-thermistors.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Thermistor dts fragment for devices that use Thermistors as +- * children of the IIO based ADC. +- * +- * Currently, used by Exynos5420 based Peach PIT and +- * Exynos5800 based Peach PI. +- * +- * Copyright (c) 2014 Samsung Electronics Co., Ltd. +-*/ +- +-&adc { +- thermistor3 { +- compatible = "murata,ncp15wb473"; +- pullup-uv = <1800000>; +- pullup-ohm = <47000>; +- pulldown-ohm = <0>; +- io-channels = <&adc 3>; +- }; +- thermistor4 { +- compatible = "murata,ncp15wb473"; +- pullup-uv = <1800000>; +- pullup-ohm = <47000>; +- pulldown-ohm = <0>; +- io-channels = <&adc 4>; +- }; +- thermistor5 { +- compatible = "murata,ncp15wb473"; +- pullup-uv = <1800000>; +- pullup-ohm = <47000>; +- pulldown-ohm = <0>; +- io-channels = <&adc 5>; +- }; +- thermistor6 { +- compatible = "murata,ncp15wb473"; +- pullup-uv = <1800000>; +- pullup-ohm = <47000>; +- pulldown-ohm = <0>; +- io-channels = <&adc 6>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/cros-ec-keyboard.dtsi b/scripts/dtc/include-prefixes/arm/cros-ec-keyboard.dtsi +deleted file mode 100644 +index 55c4744fa7e7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/cros-ec-keyboard.dtsi ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Keyboard dts fragment for devices that use cros-ec-keyboard +- * +- * Copyright (c) 2014 Google, Inc +-*/ +- +-#include +-#include +- +-&cros_ec { +- keyboard_controller: keyboard-controller { +- compatible = "google,cros-ec-keyb"; +- keypad,num-rows = <8>; +- keypad,num-columns = <13>; +- google,needs-ghost-filter; +- +- linux,keymap = < +- CROS_STD_TOP_ROW_KEYMAP +- CROS_STD_MAIN_KEYMAP +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/cros-ec-sbs.dtsi b/scripts/dtc/include-prefixes/arm/cros-ec-sbs.dtsi +deleted file mode 100644 +index 71f5c5ecce46..000000000000 +--- a/scripts/dtc/include-prefixes/arm/cros-ec-sbs.dtsi ++++ /dev/null +@@ -1,52 +0,0 @@ +-/* +- * Smart battery dts fragment for devices that use cros-ec-sbs +- * +- * Copyright (c) 2015 Google, Inc +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-&i2c_tunnel { +- battery: sbs-battery@b { +- compatible = "sbs,sbs-battery"; +- reg = <0xb>; +- sbs,i2c-retry-count = <2>; +- sbs,poll-retry-count = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/cx92755.dtsi b/scripts/dtc/include-prefixes/arm/cx92755.dtsi +deleted file mode 100644 +index d2e8f36f8c60..000000000000 +--- a/scripts/dtc/include-prefixes/arm/cx92755.dtsi ++++ /dev/null +@@ -1,144 +0,0 @@ +-/* +- * Device Tree Include file for the Conexant Digicolor CX92755 SoC +- * +- * Author: Baruch Siach +- * +- * Copyright (C) 2014 Paradox Innovation Ltd. +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cnxt,cx92755"; +- +- interrupt-parent = <&intc>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a8"; +- reg = <0x0>; +- }; +- }; +- +- main_clk: main_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <200000000>; +- }; +- +- intc: interrupt-controller@f0000040 { +- compatible = "cnxt,cx92755-ic"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0xf0000040 0x40>; +- syscon = <&uc_regs>; +- }; +- +- timer@f0000fc0 { +- compatible = "cnxt,cx92755-timer"; +- reg = <0xf0000fc0 0x40>; +- interrupts = <19>, <31>, <34>, <35>, <52>, <53>, <54>, <55>; +- clocks = <&main_clk>; +- }; +- +- rtc@f0000c30 { +- compatible = "cnxt,cx92755-rtc"; +- reg = <0xf0000c30 0x18>; +- interrupts = <25>; +- }; +- +- watchdog@f0000fc0 { +- compatible = "cnxt,cx92755-wdt"; +- reg = <0xf0000fc0 0x8>; +- clocks = <&main_clk>; +- timeout-sec = <15>; +- }; +- +- pinctrl: pinctrl@f0000e20 { +- compatible = "cnxt,cx92755-pinctrl"; +- reg = <0xf0000e20 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- uc_regs: syscon@f00003a0 { +- compatible = "cnxt,cx92755-uc", "syscon"; +- reg = <0xf00003a0 0x10>; +- }; +- +- uart0: uart@f0000740 { +- compatible = "cnxt,cx92755-usart"; +- reg = <0xf0000740 0x20>; +- clocks = <&main_clk>; +- interrupts = <44>; +- status = "disabled"; +- }; +- +- uart1: uart@f0000760 { +- compatible = "cnxt,cx92755-usart"; +- reg = <0xf0000760 0x20>; +- clocks = <&main_clk>; +- interrupts = <45>; +- status = "disabled"; +- }; +- +- uart2: uart@f0000780 { +- compatible = "cnxt,cx92755-usart"; +- reg = <0xf0000780 0x20>; +- clocks = <&main_clk>; +- interrupts = <46>; +- status = "disabled"; +- }; +- +- i2c: i2c@f0000120 { +- compatible = "cnxt,cx92755-i2c"; +- reg = <0xf0000120 0x10>; +- interrupts = <28>; +- clocks = <&main_clk>; +- clock-frequency = <100000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/cx92755_equinox.dts b/scripts/dtc/include-prefixes/arm/cx92755_equinox.dts +deleted file mode 100644 +index 026f556c8c50..000000000000 +--- a/scripts/dtc/include-prefixes/arm/cx92755_equinox.dts ++++ /dev/null +@@ -1,86 +0,0 @@ +-/* +- * Device Tree file for the Conexant Equinox CX92755 EVK +- * +- * Author: Baruch Siach +- * +- * Copyright (C) 2014 Paradox Innovation Ltd. +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include "cx92755.dtsi" +- +-/ { +- model = "Conexant Equinox CX92755 EVK"; +- compatible = "cnxt,equinox", "cnxt,cx92755"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- }; +- +- memory@0 { +- reg = <0 0x8000000>; +- device_type = "memory"; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +- pinctrl-0 = <&uart0_default>; +- pinctrl-names = "default"; +-}; +- +-&i2c { +- status = "okay"; +-}; +- +-&pinctrl { +- uart0_default: uart0_active { +- pins = "GP_O0", "GP_O1"; +- function = "client_b"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/da850-enbw-cmc.dts b/scripts/dtc/include-prefixes/arm/da850-enbw-cmc.dts +deleted file mode 100644 +index d4a5237cee0a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/da850-enbw-cmc.dts ++++ /dev/null +@@ -1,44 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Device Tree for AM1808 EnBW CMC board +- * +- * Copyright 2012 DENX Software Engineering GmbH +- * Heiko Schocher +- */ +-/dts-v1/; +-#include "da850.dtsi" +- +-/ { +- compatible = "enbw,cmc", "ti,da850"; +- model = "EnBW CMC"; +- +- soc@1c00000 { +- serial0: serial@42000 { +- status = "okay"; +- }; +- serial1: serial@10c000 { +- status = "okay"; +- }; +- serial2: serial@10d000 { +- status = "okay"; +- }; +- mdio: mdio@224000 { +- status = "okay"; +- }; +- eth0: ethernet@220000 { +- status = "okay"; +- }; +- }; +-}; +- +-&ref_clk { +- clock-frequency = <24000000>; +-}; +- +-&edma0 { +- ti,edma-reserved-slot-ranges = <32 50>; +-}; +- +-&edma1 { +- ti,edma-reserved-slot-ranges = <32 90>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/da850-evm.dts b/scripts/dtc/include-prefixes/arm/da850-evm.dts +deleted file mode 100644 +index 87c517d65f62..000000000000 +--- a/scripts/dtc/include-prefixes/arm/da850-evm.dts ++++ /dev/null +@@ -1,466 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree for DA850 EVM board +- * +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +-#include "da850.dtsi" +-#include +- +-/ { +- compatible = "ti,da850-evm", "ti,da850"; +- model = "DA850/AM1808/OMAP-L138 EVM"; +- +- chosen { +- stdout-path = &serial2; +- }; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- ethernet0 = ð0; +- spi0 = &spi1; +- }; +- +- backlight: backlight-pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&ecap2_pins>; +- power-supply = <&backlight_lcd>; +- compatible = "pwm-backlight"; +- /* +- * The PWM here corresponds to production hardware. The +- * schematic needs to be 1015171 (15 March 2010), Rev A +- * or newer. +- */ +- pwms = <&ecap2 0 50000 0>; +- brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>; +- default-brightness-level = <7>; +- }; +- +- panel { +- compatible = "ti,tilcdc,panel"; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_pins>; +- /* +- * The vpif and the LCD are mutually exclusive. +- * To enable VPIF, change the status below to 'disabled' then +- * then change the status of the vpif below to 'okay' +- */ +- status = "okay"; +- enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */ +- +- panel-info { +- ac-bias = <255>; +- ac-bias-intrpt = <0>; +- dma-burst-sz = <16>; +- bpp = <16>; +- fdd = <0x80>; +- sync-edge = <0>; +- sync-ctrl = <1>; +- raster-order = <0>; +- fifo-th = <0>; +- }; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: 480x272 { +- clock-frequency = <9000000>; +- hactive = <480>; +- vactive = <272>; +- hfront-porch = <3>; +- hback-porch = <2>; +- hsync-len = <42>; +- vback-porch = <3>; +- vfront-porch = <4>; +- vsync-len = <11>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- }; +- +- vbat: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vbat"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- }; +- +- baseboard_3v3: fixedregulator-3v3 { +- /* TPS73701DCQ */ +- compatible = "regulator-fixed"; +- regulator-name = "baseboard_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vbat>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- baseboard_1v8: fixedregulator-1v8 { +- /* TPS73701DCQ */ +- compatible = "regulator-fixed"; +- regulator-name = "baseboard_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vbat>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- backlight_lcd: backlight-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "lcd_backlight_pwr"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio 47 GPIO_ACTIVE_HIGH>; /* lcd_backlight_pwr */ +- enable-active-high; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "DA850-OMAPL138 EVM"; +- simple-audio-card,widgets = +- "Line", "Line In", +- "Line", "Line Out"; +- simple-audio-card,routing = +- "LINE1L", "Line In", +- "LINE1R", "Line In", +- "Line Out", "LLOUT", +- "Line Out", "RLOUT"; +- simple-audio-card,format = "dsp_b"; +- simple-audio-card,bitclock-master = <&link0_codec>; +- simple-audio-card,frame-master = <&link0_codec>; +- simple-audio-card,bitclock-inversion; +- +- simple-audio-card,cpu { +- sound-dai = <&mcasp0>; +- system-clock-frequency = <24576000>; +- }; +- +- link0_codec: simple-audio-card,codec { +- sound-dai = <&tlv320aic3106>; +- system-clock-frequency = <24576000>; +- }; +- }; +-}; +- +-&ecap2 { +- status = "okay"; +-}; +- +-&ref_clk { +- clock-frequency = <24000000>; +-}; +- +-&pmx_core { +- status = "okay"; +- +- mcasp0_pins: pinmux_mcasp0_pins { +- pinctrl-single,bits = < +- /* +- * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR, +- * AFSR, AMUTE +- */ +- 0x00 0x11111111 0xffffffff +- /* AXR11, AXR12 */ +- 0x04 0x00011000 0x000ff000 +- >; +- }; +- nand_pins: nand_pins { +- pinctrl-single,bits = < +- /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */ +- 0x1c 0x10110110 0xf0ff0ff0 +- /* +- * EMA_D[0], EMA_D[1], EMA_D[2], +- * EMA_D[3], EMA_D[4], EMA_D[5], +- * EMA_D[6], EMA_D[7] +- */ +- 0x24 0x11111111 0xffffffff +- /* EMA_A[1], EMA_A[2] */ +- 0x30 0x01100000 0x0ff00000 +- >; +- }; +-}; +- +-&cpu { +- cpu-supply = <&vdcdc3_reg>; +-}; +- +-/* +- * The standard da850-evm kits and SOM's are 375MHz so enable this operating +- * point by default. Higher frequencies must be enabled for custom boards with +- * other variants of the SoC. +- */ +-&opp_375 { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&serial1 { +- status = "okay"; +-}; +- +-&serial2 { +- status = "okay"; +-}; +- +-&rtc0 { +- status = "okay"; +-}; +- +-&lcdc { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- +- tps: tps@48 { +- reg = <0x48>; +- }; +- tlv320aic3106: tlv320aic3106@18 { +- #sound-dai-cells = <0>; +- compatible = "ti,tlv320aic3106"; +- reg = <0x18>; +- status = "okay"; +- +- /* Regulators */ +- IOVDD-supply = <&vdcdc2_reg>; +- AVDD-supply = <&baseboard_3v3>; +- DRVDD-supply = <&baseboard_3v3>; +- DVDD-supply = <&baseboard_1v8>; +- }; +- tca6416: gpio@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- tca6416_bb: gpio@21 { +- compatible = "ti,tca6416"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&wdt { +- status = "okay"; +-}; +- +-&mmc0 { +- max-frequency = <50000000>; +- bus-width = <4>; +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio 65 GPIO_ACTIVE_HIGH>; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins &spi1_cs0_pin>; +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <30000000>; +- m25p,fast-read; +- reg = <0>; +- partition@0 { +- label = "U-Boot-SPL"; +- reg = <0x00000000 0x00010000>; +- read-only; +- }; +- partition@1 { +- label = "U-Boot"; +- reg = <0x00010000 0x00080000>; +- read-only; +- }; +- partition@2 { +- label = "U-Boot-Env"; +- reg = <0x00090000 0x00010000>; +- read-only; +- }; +- partition@3 { +- label = "Kernel"; +- reg = <0x000a0000 0x00280000>; +- }; +- partition@4 { +- label = "Filesystem"; +- reg = <0x00320000 0x00400000>; +- }; +- partition@5 { +- label = "MAC-Address"; +- reg = <0x007f0000 0x00010000>; +- read-only; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mdio_pins>; +- bus_freq = <2200000>; +-}; +- +-ð0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mii_pins>; +-}; +- +-&gpio { +- status = "okay"; +-}; +- +-/include/ "tps6507x.dtsi" +- +-&tps { +- vdcdc1_2-supply = <&vbat>; +- vdcdc3-supply = <&vbat>; +- vldo1_2-supply = <&vbat>; +- +- regulators { +- vdcdc1_reg: regulator@0 { +- regulator-name = "VDCDC1_3.3V"; +- regulator-min-microvolt = <3150000>; +- regulator-max-microvolt = <3450000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdcdc2_reg: regulator@1 { +- regulator-name = "VDCDC2_3.3V"; +- regulator-min-microvolt = <1710000>; +- regulator-max-microvolt = <3450000>; +- regulator-always-on; +- regulator-boot-on; +- ti,defdcdc_default = <1>; +- }; +- +- vdcdc3_reg: regulator@2 { +- regulator-name = "VDCDC3_1.2V"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- ti,defdcdc_default = <1>; +- }; +- +- ldo1_reg: regulator@3 { +- regulator-name = "LDO1_1.8V"; +- regulator-min-microvolt = <1710000>; +- regulator-max-microvolt = <1890000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo2_reg: regulator@4 { +- regulator-name = "LDO2_1.2V"; +- regulator-min-microvolt = <1140000>; +- regulator-max-microvolt = <1320000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +-}; +- +-&mcasp0 { +- #sound-dai-cells = <0>; +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mcasp0_pins>; +- +- op-mode = <0>; /* MCASP_IIS_MODE */ +- tdm-slots = <2>; +- /* 4 serializer */ +- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ +- 0 0 0 0 +- 0 0 0 0 +- 0 0 0 1 +- 2 0 0 0 +- >; +- tx-num-evt = <32>; +- rx-num-evt = <32>; +-}; +- +-&edma0 { +- ti,edma-reserved-slot-ranges = <32 50>; +-}; +- +-&edma1 { +- ti,edma-reserved-slot-ranges = <32 90>; +-}; +- +-&aemif { +- pinctrl-names = "default"; +- pinctrl-0 = <&nand_pins>; +- status = "ok"; +- cs3 { +- #address-cells = <2>; +- #size-cells = <1>; +- clock-ranges; +- ranges; +- +- ti,cs-chipselect = <3>; +- +- nand@2000000,0 { +- compatible = "ti,davinci-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0 0x02000000 0x02000000 +- 1 0x00000000 0x00008000>; +- +- ti,davinci-chipselect = <1>; +- ti,davinci-mask-ale = <0>; +- ti,davinci-mask-cle = <0>; +- ti,davinci-mask-chipsel = <0>; +- ti,davinci-ecc-mode = "hw"; +- ti,davinci-ecc-bits = <4>; +- ti,davinci-nand-use-bbt; +- }; +- }; +-}; +- +-&usb_phy { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&vpif { +- pinctrl-names = "default"; +- pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>; +- /* +- * The vpif and the LCD are mutually exclusive. +- * To enable VPIF, disable the ti,tilcdc,panel then +- * change the status below to 'okay' +- */ +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/da850-lcdk.dts b/scripts/dtc/include-prefixes/arm/da850-lcdk.dts +deleted file mode 100644 +index e379d6e7ad49..000000000000 +--- a/scripts/dtc/include-prefixes/arm/da850-lcdk.dts ++++ /dev/null +@@ -1,425 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2016 BayLibre, Inc. +- */ +-/dts-v1/; +-#include "da850.dtsi" +-#include +-#include +- +-/ { +- model = "DA850/AM1808/OMAP-L138 LCDK"; +- compatible = "ti,da850-lcdk", "ti,da850"; +- +- aliases { +- serial2 = &serial2; +- ethernet0 = ð0; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- memory@c0000000 { +- /* 128 MB DDR2 SDRAM @ 0xc0000000 */ +- reg = <0xc0000000 0x08000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- dsp_memory_region: dsp-memory@c3000000 { +- compatible = "shared-dma-pool"; +- reg = <0xc3000000 0x1000000>; +- reusable; +- status = "okay"; +- }; +- }; +- +- vcc_5vd: fixedregulator-vcc_5vd { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_5vd"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- }; +- +- vcc_3v3d: fixedregulator-vcc_3v3d { +- /* TPS650250 - VDCDC1 */ +- compatible = "regulator-fixed"; +- regulator-name = "vcc_3v3d"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc_5vd>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc_1v8d: fixedregulator-vcc_1v8d { +- /* TPS650250 - VDCDC2 */ +- compatible = "regulator-fixed"; +- regulator-name = "vcc_1v8d"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_5vd>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "DA850-OMAPL138 LCDK"; +- simple-audio-card,widgets = +- "Line", "Line In", +- "Line", "Line Out", +- "Microphone", "Mic Jack"; +- simple-audio-card,routing = +- "LINE1L", "Line In", +- "LINE1R", "Line In", +- "Line Out", "LLOUT", +- "Line Out", "RLOUT", +- "MIC3L", "Mic Jack", +- "MIC3R", "Mic Jack", +- "Mic Jack", "Mic Bias"; +- simple-audio-card,format = "dsp_b"; +- simple-audio-card,bitclock-master = <&link0_codec>; +- simple-audio-card,frame-master = <&link0_codec>; +- simple-audio-card,bitclock-inversion; +- +- simple-audio-card,cpu { +- sound-dai = <&mcasp0>; +- system-clock-frequency = <24576000>; +- }; +- +- link0_codec: simple-audio-card,codec { +- sound-dai = <&tlv320aic3106>; +- system-clock-frequency = <24576000>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- +- user1 { +- label = "GPIO Key USER1"; +- linux,code = ; +- gpios = <&gpio 36 GPIO_ACTIVE_LOW>; +- }; +- +- user2 { +- label = "GPIO Key USER2"; +- linux,code = ; +- gpios = <&gpio 37 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- vga-bridge { +- compatible = "ti,ths8135"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- vga_bridge_in: endpoint { +- remote-endpoint = <&lcdc_out_vga>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- vga_bridge_out: endpoint { +- remote-endpoint = <&vga_con_in>; +- }; +- }; +- }; +- }; +- +- vga { +- compatible = "vga-connector"; +- +- ddc-i2c-bus = <&i2c0>; +- +- port { +- vga_con_in: endpoint { +- remote-endpoint = <&vga_bridge_out>; +- }; +- }; +- }; +- +- cvdd: regulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "cvdd"; +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&ref_clk { +- clock-frequency = <24000000>; +-}; +- +-&cpu { +- cpu-supply = <&cvdd>; +-}; +- +-/* +- * LCDK has a fixed CVDD of 1.3V, so only operating points >= 300MHz are +- * valid. Unfortunately due to a problem with the DA8XX OHCI controller, we +- * can't enable more than one OPP by default, since the controller sometimes +- * becomes unresponsive after a transition. Fix the frequency at 456 MHz. +- */ +- +-&opp_100 { +- status = "disabled"; +-}; +- +-&opp_200 { +- status = "disabled"; +-}; +- +-&opp_300 { +- status = "disabled"; +-}; +- +-&opp_456 { +- status = "okay"; +-}; +- +-&pmx_core { +- status = "okay"; +- +- mcasp0_pins: pinmux_mcasp0_pins { +- pinctrl-single,bits = < +- /* AHCLKX AFSX ACLKX */ +- 0x00 0x00101010 0x00f0f0f0 +- /* ARX13 ARX14 */ +- 0x04 0x00000110 0x00000ff0 +- >; +- }; +- +- nand_pins: nand_pins { +- pinctrl-single,bits = < +- /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */ +- 0x1c 0x10110010 0xf0ff00f0 +- /* +- * EMA_D[0], EMA_D[1], EMA_D[2], +- * EMA_D[3], EMA_D[4], EMA_D[5], +- * EMA_D[6], EMA_D[7] +- */ +- 0x24 0x11111111 0xffffffff +- /* +- * EMA_D[8], EMA_D[9], EMA_D[10], +- * EMA_D[11], EMA_D[12], EMA_D[13], +- * EMA_D[14], EMA_D[15] +- */ +- 0x20 0x11111111 0xffffffff +- /* EMA_A[1], EMA_A[2] */ +- 0x30 0x01100000 0x0ff00000 +- >; +- }; +-}; +- +-&serial2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&serial2_rxtx_pins>; +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +- +-&rtc0 { +- status = "okay"; +-}; +- +-&gpio { +- status = "okay"; +-}; +- +-&sata_refclk { +- status = "okay"; +- clock-frequency = <100000000>; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&mdio { +- pinctrl-names = "default"; +- pinctrl-0 = <&mdio_pins>; +- bus_freq = <2200000>; +- status = "okay"; +-}; +- +-ð0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mii_pins>; +- status = "okay"; +-}; +- +-&mmc0 { +- max-frequency = <50000000>; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- clock-frequency = <100000>; +- status = "okay"; +- +- tlv320aic3106: tlv320aic3106@18 { +- #sound-dai-cells = <0>; +- compatible = "ti,tlv320aic3106"; +- reg = <0x18>; +- adc-settle-ms = <40>; +- ai3x-micbias-vg = <1>; /* 2.0V */ +- status = "okay"; +- +- /* Regulators */ +- IOVDD-supply = <&vcc_3v3d>; +- AVDD-supply = <&vcc_3v3d>; +- DRVDD-supply = <&vcc_3v3d>; +- DVDD-supply = <&vcc_1v8d>; +- }; +-}; +- +-&mcasp0 { +- #sound-dai-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mcasp0_pins>; +- status = "okay"; +- +- op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ +- tdm-slots = <2>; +- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ +- 0 0 0 0 +- 0 0 0 0 +- 0 0 0 0 +- 0 1 2 0 +- >; +- tx-num-evt = <32>; +- rx-num-evt = <32>; +-}; +- +-&usb_phy { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&aemif { +- pinctrl-names = "default"; +- pinctrl-0 = <&nand_pins>; +- status = "okay"; +- cs3 { +- #address-cells = <2>; +- #size-cells = <1>; +- clock-ranges; +- ranges; +- +- ti,cs-chipselect = <3>; +- +- nand@2000000,0 { +- compatible = "ti,davinci-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0 0x02000000 0x02000000 +- 1 0x00000000 0x00008000>; +- +- ti,davinci-chipselect = <1>; +- ti,davinci-mask-ale = <0>; +- ti,davinci-mask-cle = <0>; +- ti,davinci-mask-chipsel = <0>; +- +- ti,davinci-nand-buswidth = <16>; +- ti,davinci-ecc-mode = "hw"; +- ti,davinci-ecc-bits = <4>; +- ti,davinci-nand-use-bbt; +- +- /* +- * The OMAP-L132/L138 Bootloader doc SPRAB41E reads: +- * "To boot from NAND Flash, the AIS should be written +- * to NAND block 1 (NAND block 0 is not used by default)". +- * The same doc mentions that for ROM "Silicon Revision 2.1", +- * "Updated NAND boot mode to offer boot from block 0 or block 1". +- * However the limitaion is left here by default for compatibility +- * with older silicon and because it needs new boot pin settings +- * not possible in stock LCDK. +- */ +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot env"; +- reg = <0 0x020000>; +- }; +- partition@20000 { +- /* The LCDK defaults to booting from this partition */ +- label = "u-boot"; +- reg = <0x020000 0x080000>; +- }; +- partition@a0000 { +- label = "free space"; +- reg = <0x0a0000 0>; +- }; +- }; +- }; +- }; +-}; +- +-&prictrl { +- status = "okay"; +-}; +- +-&memctrl { +- status = "okay"; +-}; +- +-&lcdc { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_pins>; +- +- port { +- lcdc_out_vga: endpoint { +- remote-endpoint = <&vga_bridge_in>; +- }; +- }; +-}; +- +-&vpif { +- pinctrl-names = "default"; +- pinctrl-0 = <&vpif_capture_pins>; +- status = "okay"; +-}; +- +-&dsp { +- memory-region = <&dsp_memory_region>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/da850-lego-ev3.dts b/scripts/dtc/include-prefixes/arm/da850-lego-ev3.dts +deleted file mode 100644 +index afd04a423856..000000000000 +--- a/scripts/dtc/include-prefixes/arm/da850-lego-ev3.dts ++++ /dev/null +@@ -1,466 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device tree for LEGO MINDSTORMS EV3 +- * +- * Copyright (C) 2017 David Lechner +- */ +- +-/dts-v1/; +-#include +-#include +-#include +- +-#include "da850.dtsi" +- +-/ { +- compatible = "lego,ev3", "ti,da850"; +- model = "LEGO MINDSTORMS EV3"; +- +- aliases { +- serial1 = &serial1; +- }; +- +- memory@c0000000 { +- device_type = "memory"; +- reg = <0xc0000000 0x04000000>; +- }; +- +- /* +- * The buttons on the EV3 are mapped to keyboard keys. +- */ +- gpio_keys { +- compatible = "gpio-keys"; +- label = "EV3 Brick Buttons"; +- pinctrl-names = "default"; +- pinctrl-0 = <&button_bias>; +- +- center { +- label = "Center"; +- linux,code = ; +- gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; +- }; +- +- left { +- label = "Left"; +- linux,code = ; +- gpios = <&gpio 102 GPIO_ACTIVE_HIGH>; +- }; +- +- back { +- label = "Back"; +- linux,code = ; +- gpios = <&gpio 106 GPIO_ACTIVE_HIGH>; +- }; +- +- right { +- label = "Right"; +- linux,code = ; +- gpios = <&gpio 124 GPIO_ACTIVE_HIGH>; +- }; +- +- down { +- label = "Down"; +- linux,code = ; +- gpios = <&gpio 126 GPIO_ACTIVE_HIGH>; +- }; +- +- up { +- label = "Up"; +- linux,code = ; +- gpios = <&gpio 127 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- /* +- * The EV3 has two built-in bi-color LEDs behind the buttons. +- */ +- leds { +- compatible = "gpio-leds"; +- +- left_green { +- label = "led0:green:brick-status"; +- /* GP6[13] */ +- gpios = <&gpio 103 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- right_red { +- label = "led1:red:brick-status"; +- /* GP6[7] */ +- gpios = <&gpio 108 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- left_red { +- label = "led0:red:brick-status"; +- /* GP6[12] */ +- gpios = <&gpio 109 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- right_green { +- label = "led1:green:brick-status"; +- /* GP6[14] */ +- gpios = <&gpio 110 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- }; +- +- /* +- * The EV3 is powered down by turning off the main 5V supply. +- */ +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- gpios = <&gpio 107 GPIO_ACTIVE_LOW>; +- }; +- +- sound { +- compatible = "pwm-beeper"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ehrpwm0b_pins>; +- pwms = <&ehrpwm0 1 1000000 0>; +- amp-supply = <&>; +- }; +- +- cvdd: regulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "cvdd"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* +- * This is a 5V current limiting regulator that is shared by USB, +- * the sensor (input) ports, the motor (output) ports and the A/DC. +- */ +- vcc5v: regulator1 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio 101 0>; +- over-current-gpios = <&gpio 99 GPIO_ACTIVE_LOW>; +- enable-active-high; +- regulator-boot-on; +- }; +- +- /* +- * This is a simple voltage divider on VCC5V to provide a 2.5V +- * reference signal to the ADC. +- */ +- adc_ref: regulator2 { +- compatible = "regulator-fixed"; +- regulator-name = "adc ref"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-boot-on; +- vin-supply = <&vcc5v>; +- }; +- +- /* +- * This is the amplifier for the speaker. +- */ +- amp: regulator3 { +- compatible = "regulator-fixed"; +- regulator-name = "amp"; +- gpio = <&gpio 111 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- /* +- * The EV3 can use 6-AA batteries or a rechargeable Li-ion battery pack. +- */ +- battery { +- compatible = "lego,ev3-battery"; +- io-channels = <&adc 4>, <&adc 3>; +- io-channel-names = "voltage", "current"; +- rechargeable-gpios = <&gpio 136 GPIO_ACTIVE_LOW>; +- }; +- +- bt_slow_clk: bt-clock { +- pinctrl-names = "default"; +- pinctrl-0 = <&ecap2_pins>, <&bt_clock_bias>; +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pwms = <&ecap2 0 30518 0>; +- }; +- +- /* ARM local RAM */ +- memory@ffff0000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0xffff0000 0x2000>; /* 8k */ +- +- /* +- * The I2C bootloader looks for this magic value to either +- * boot normally or boot into a firmware update mode. +- */ +- reboot-mode { +- compatible = "syscon-reboot-mode"; +- offset = <0x1ffc>; +- mode-normal = <0x00000000>; +- mode-loader = <0x5555aaaa>; +- }; +- }; +-}; +- +-&ref_clk { +- clock-frequency = <24000000>; +-}; +- +-&cpu { +- cpu-supply = <&cvdd>; +-}; +- +-/* since we have a fixed regulator, we can't run at these points */ +-&opp_100 { +- status = "disabled"; +-}; +- +-&opp_200 { +- status = "disabled"; +-}; +- +-/* +- * The SoC is actually the 456MHz version, but because of the fixed regulator +- * This is the fastest we can go. +- */ +-&opp_375 { +- status = "okay"; +-}; +- +-&pmx_core { +- status = "okay"; +- +- ev3_lcd_pins: pinmux_lcd { +- pinctrl-single,bits = < +- /* SIMO, CLK */ +- 0x14 0x00100100 0x00f00f00 +- >; +- }; +-}; +- +-&pinconf { +- status = "okay"; +- +- /* Buttons have external pulldown resistors */ +- button_bias: button-bias-groups { +- disable { +- groups = "cp5", "cp24", "cp25", "cp28"; +- bias-disable; +- }; +- }; +- +- bt_clock_bias: bt-clock-bias-groups { +- disable { +- groups = "cp2"; +- bias-disable; +- }; +- }; +- +- bt_pic_bias: bt-pic-bias-groups { +- disable { +- groups = "cp20"; +- bias-disable; +- }; +- }; +-}; +- +-/* Input port 1 */ +-&serial1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&serial1_rxtx_pins>; +-}; +- +-&serial2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&serial2_rxtx_pins>, <&serial2_rtscts_pins>, <&bt_pic_bias>; +- status = "okay"; +- +- bluetooth { +- compatible = "ti,cc2560"; +- clocks = <&bt_slow_clk>; +- clock-names = "ext_clock"; +- enable-gpios = <&gpio 73 GPIO_ACTIVE_HIGH>; +- max-speed = <2000000>; +- nvmem-cells = <&bdaddr>; +- nvmem-cell-names = "bd-address"; +- }; +-}; +- +-&rtc0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- +- /* +- * EEPROM contains the first stage bootloader, HW ID and Bluetooth MAC. +- */ +- eeprom@50 { +- compatible = "microchip,24c128", "atmel,24c128"; +- pagesize = <64>; +- read-only; +- reg = <0x50>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- bdaddr: bdaddr@3f06 { +- reg = <0x3f06 0x06>; +- }; +- }; +-}; +- +-&wdt { +- status = "okay"; +-}; +- +-&mmc0 { +- status = "okay"; +- max-frequency = <50000000>; +- bus-width = <4>; +- cd-gpios = <&gpio 94 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +-}; +- +-&spi0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>, <&spi0_cs3_pin>; +- +- flash@0 { +- compatible = "n25q128a13", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- ti,spi-wdelay = <8>; +- +- /* Partitions are based on the official firmware from LEGO */ +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0 0x40000>; +- }; +- +- partition@40000 { +- label = "U-Boot Env"; +- reg = <0x40000 0x10000>; +- }; +- +- partition@50000 { +- label = "Kernel"; +- reg = <0x50000 0x200000>; +- }; +- +- partition@250000 { +- label = "Filesystem"; +- reg = <0x250000 0xa50000>; +- }; +- +- partition@cb0000 { +- label = "Storage"; +- reg = <0xcb0000 0x2f0000>; +- }; +- }; +- }; +- +- adc: adc@3 { +- compatible = "ti,ads7957"; +- reg = <3>; +- #io-channel-cells = <1>; +- spi-max-frequency = <1000000>; +- ti,spi-wdelay = <63>; +- vref-supply = <&adc_ref>; +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-0 = <&ev3_lcd_pins>; +- pinctrl-names = "default"; +- cs-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; +- +- display@0{ +- compatible = "lego,ev3-lcd"; +- reg = <0>; +- spi-max-frequency = <10000000>; +- a0-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&ecap2 { +- status = "okay"; +-}; +- +-&ehrpwm0 { +- status = "okay"; +-}; +- +-&gpio { +- status = "okay"; +- +- /* Don't pull down battery voltage adc io channel */ +- batt_volt_en { +- gpio-hog; +- gpios = <6 GPIO_ACTIVE_HIGH>; +- output-high; +- }; +- +- /* Don't impede Bluetooth clock signal */ +- bt_clock_en { +- gpio-hog; +- gpios = <5 GPIO_ACTIVE_HIGH>; +- input; +- }; +- +- /* +- * There is a PIC microcontroller for interfacing with an Apple MFi +- * chip. This interferes with normal Bluetooth operation, so we need +- * to make sure it is turned off. Note: The publicly available +- * schematics from LEGO don't show that these pins are connected to +- * anything, but they are present in the source code from LEGO. +- */ +- +- bt_pic_en { +- gpio-hog; +- gpios = <51 GPIO_ACTIVE_HIGH>; +- output-low; +- }; +- +- bt_pic_rst { +- gpio-hog; +- gpios = <78 GPIO_ACTIVE_HIGH>; +- output-high; +- }; +- +- bt_pic_cts { +- gpio-hog; +- gpios = <87 GPIO_ACTIVE_HIGH>; +- input; +- }; +-}; +- +-&usb_phy { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +- vbus-supply = <&vcc5v>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/da850.dtsi b/scripts/dtc/include-prefixes/arm/da850.dtsi +deleted file mode 100644 +index c3942b4e82ad..000000000000 +--- a/scripts/dtc/include-prefixes/arm/da850.dtsi ++++ /dev/null +@@ -1,962 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 DENX Software Engineering GmbH +- * Heiko Schocher +- */ +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- chosen { }; +- aliases { }; +- +- memory@c0000000 { +- device_type = "memory"; +- reg = <0xc0000000 0x0>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu: cpu@0 { +- compatible = "arm,arm926ej-s"; +- device_type = "cpu"; +- reg = <0>; +- clocks = <&psc0 14>; +- operating-points-v2 = <&opp_table>; +- }; +- }; +- +- opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp_100: opp100-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- opp-microvolt = <1000000 950000 1050000>; +- }; +- +- opp_200: opp110-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- opp-microvolt = <1100000 1050000 1160000>; +- }; +- +- opp_300: opp120-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <1200000 1140000 1320000>; +- }; +- +- /* +- * Original silicon was 300MHz max, so higher frequencies +- * need to be enabled on a per-board basis if the chip is +- * capable. +- */ +- +- opp_375: opp120-375000000 { +- status = "disabled"; +- opp-hz = /bits/ 64 <375000000>; +- opp-microvolt = <1200000 1140000 1320000>; +- }; +- +- opp_456: opp130-456000000 { +- status = "disabled"; +- opp-hz = /bits/ 64 <456000000>; +- opp-microvolt = <1300000 1250000 1350000>; +- }; +- }; +- +- arm { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- intc: interrupt-controller@fffee000 { +- compatible = "ti,cp-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- ti,intc-size = <101>; +- reg = <0xfffee000 0x2000>; +- }; +- }; +- clocks: clocks { +- ref_clk: ref_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-output-names = "ref_clk"; +- }; +- sata_refclk: sata_refclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-output-names = "sata_refclk"; +- status = "disabled"; +- }; +- usb_refclkin: usb_refclkin { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-output-names = "usb_refclkin"; +- status = "disabled"; +- }; +- }; +- dsp: dsp@11800000 { +- compatible = "ti,da850-dsp"; +- reg = <0x11800000 0x40000>, +- <0x11e00000 0x8000>, +- <0x11f00000 0x8000>, +- <0x01c14044 0x4>, +- <0x01c14174 0x8>; +- reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig"; +- interrupt-parent = <&intc>; +- interrupts = <28>; +- clocks = <&psc0 15>; +- resets = <&psc0 15>; +- status = "disabled"; +- }; +- soc@1c00000 { +- compatible = "simple-bus"; +- model = "da850"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x01c00000 0x400000>; +- interrupt-parent = <&intc>; +- +- psc0: clock-controller@10000 { +- compatible = "ti,da850-psc0"; +- reg = <0x10000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>, +- <&pll0_sysclk 4>, <&pll0_sysclk 6>, +- <&async1_clk>; +- clock-names = "pll0_sysclk1", "pll0_sysclk2", +- "pll0_sysclk4", "pll0_sysclk6", +- "async1"; +- }; +- pll0: clock-controller@11000 { +- compatible = "ti,da850-pll0"; +- reg = <0x11000 0x1000>; +- clocks = <&ref_clk>, <&pll1_sysclk 3>; +- clock-names = "clksrc", "extclksrc"; +- +- pll0_pllout: pllout { +- #clock-cells = <0>; +- }; +- pll0_sysclk: sysclk { +- #clock-cells = <1>; +- }; +- pll0_auxclk: auxclk { +- #clock-cells = <0>; +- }; +- pll0_obsclk: obsclk { +- #clock-cells = <0>; +- }; +- }; +- pmx_core: pinmux@14120 { +- compatible = "pinctrl-single"; +- reg = <0x14120 0x50>; +- #pinctrl-cells = <2>; +- pinctrl-single,bit-per-mux; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0xf>; +- /* pin base, nr pins & gpio function */ +- pinctrl-single,gpio-range = <&range 0 17 0x8>, +- <&range 17 8 0x4>, +- <&range 26 8 0x4>, +- <&range 34 80 0x8>, +- <&range 129 31 0x8>; +- status = "disabled"; +- +- range: gpio-range { +- #pinctrl-single,gpio-range-cells = <3>; +- }; +- +- serial0_rtscts_pins: pinmux_serial0_rtscts_pins { +- pinctrl-single,bits = < +- /* UART0_RTS UART0_CTS */ +- 0x0c 0x22000000 0xff000000 +- >; +- }; +- serial0_rxtx_pins: pinmux_serial0_rxtx_pins { +- pinctrl-single,bits = < +- /* UART0_TXD UART0_RXD */ +- 0x0c 0x00220000 0x00ff0000 +- >; +- }; +- serial1_rtscts_pins: pinmux_serial1_rtscts_pins { +- pinctrl-single,bits = < +- /* UART1_CTS UART1_RTS */ +- 0x00 0x00440000 0x00ff0000 +- >; +- }; +- serial1_rxtx_pins: pinmux_serial1_rxtx_pins { +- pinctrl-single,bits = < +- /* UART1_TXD UART1_RXD */ +- 0x10 0x22000000 0xff000000 +- >; +- }; +- serial2_rtscts_pins: pinmux_serial2_rtscts_pins { +- pinctrl-single,bits = < +- /* UART2_CTS UART2_RTS */ +- 0x00 0x44000000 0xff000000 +- >; +- }; +- serial2_rxtx_pins: pinmux_serial2_rxtx_pins { +- pinctrl-single,bits = < +- /* UART2_TXD UART2_RXD */ +- 0x10 0x00220000 0x00ff0000 +- >; +- }; +- i2c0_pins: pinmux_i2c0_pins { +- pinctrl-single,bits = < +- /* I2C0_SDA,I2C0_SCL */ +- 0x10 0x00002200 0x0000ff00 +- >; +- }; +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,bits = < +- /* I2C1_SDA, I2C1_SCL */ +- 0x10 0x00440000 0x00ff0000 +- >; +- }; +- mmc0_pins: pinmux_mmc_pins { +- pinctrl-single,bits = < +- /* MMCSD0_DAT[3] MMCSD0_DAT[2] +- * MMCSD0_DAT[1] MMCSD0_DAT[0] +- * MMCSD0_CMD MMCSD0_CLK +- */ +- 0x28 0x00222222 0x00ffffff +- >; +- }; +- ehrpwm0a_pins: pinmux_ehrpwm0a_pins { +- pinctrl-single,bits = < +- /* EPWM0A */ +- 0xc 0x00000002 0x0000000f +- >; +- }; +- ehrpwm0b_pins: pinmux_ehrpwm0b_pins { +- pinctrl-single,bits = < +- /* EPWM0B */ +- 0xc 0x00000020 0x000000f0 +- >; +- }; +- ehrpwm1a_pins: pinmux_ehrpwm1a_pins { +- pinctrl-single,bits = < +- /* EPWM1A */ +- 0x14 0x00000002 0x0000000f +- >; +- }; +- ehrpwm1b_pins: pinmux_ehrpwm1b_pins { +- pinctrl-single,bits = < +- /* EPWM1B */ +- 0x14 0x00000020 0x000000f0 +- >; +- }; +- ecap0_pins: pinmux_ecap0_pins { +- pinctrl-single,bits = < +- /* ECAP0_APWM0 */ +- 0x8 0x20000000 0xf0000000 +- >; +- }; +- ecap1_pins: pinmux_ecap1_pins { +- pinctrl-single,bits = < +- /* ECAP1_APWM1 */ +- 0x4 0x40000000 0xf0000000 +- >; +- }; +- ecap2_pins: pinmux_ecap2_pins { +- pinctrl-single,bits = < +- /* ECAP2_APWM2 */ +- 0x4 0x00000004 0x0000000f +- >; +- }; +- spi0_pins: pinmux_spi0_pins { +- pinctrl-single,bits = < +- /* SIMO, SOMI, CLK */ +- 0xc 0x00001101 0x0000ff0f +- >; +- }; +- spi0_cs0_pin: pinmux_spi0_cs0 { +- pinctrl-single,bits = < +- /* CS0 */ +- 0x10 0x00000010 0x000000f0 +- >; +- }; +- spi0_cs3_pin: pinmux_spi0_cs3_pin { +- pinctrl-single,bits = < +- /* CS3 */ +- 0xc 0x01000000 0x0f000000 +- >; +- }; +- spi1_pins: pinmux_spi1_pins { +- pinctrl-single,bits = < +- /* SIMO, SOMI, CLK */ +- 0x14 0x00110100 0x00ff0f00 +- >; +- }; +- spi1_cs0_pin: pinmux_spi1_cs0 { +- pinctrl-single,bits = < +- /* CS0 */ +- 0x14 0x00000010 0x000000f0 +- >; +- }; +- mdio_pins: pinmux_mdio_pins { +- pinctrl-single,bits = < +- /* MDIO_CLK, MDIO_D */ +- 0x10 0x00000088 0x000000ff +- >; +- }; +- mii_pins: pinmux_mii_pins { +- pinctrl-single,bits = < +- /* +- * MII_TXEN, MII_TXCLK, MII_COL +- * MII_TXD_3, MII_TXD_2, MII_TXD_1 +- * MII_TXD_0 +- */ +- 0x8 0x88888880 0xfffffff0 +- /* +- * MII_RXER, MII_CRS, MII_RXCLK +- * MII_RXDV, MII_RXD_3, MII_RXD_2 +- * MII_RXD_1, MII_RXD_0 +- */ +- 0xc 0x88888888 0xffffffff +- >; +- }; +- lcd_pins: pinmux_lcd_pins { +- pinctrl-single,bits = < +- /* +- * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5], +- * LCD_D[6], LCD_D[7] +- */ +- 0x40 0x22222200 0xffffff00 +- /* +- * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13], +- * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1] +- */ +- 0x44 0x22222222 0xffffffff +- /* LCD_D[8], LCD_D[9] */ +- 0x48 0x00000022 0x000000ff +- +- /* LCD_PCLK */ +- 0x48 0x02000000 0x0f000000 +- /* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */ +- 0x4c 0x02000022 0x0f0000ff +- >; +- }; +- vpif_capture_pins: vpif_capture_pins { +- pinctrl-single,bits = < +- /* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0 */ +- 0x38 0x11111111 0xffffffff +- /* VP_DIN[10..15,0..1] */ +- 0x3c 0x11111111 0xffffffff +- /* VP_DIN[8..9] */ +- 0x40 0x00000011 0x000000ff +- >; +- }; +- vpif_display_pins: vpif_display_pins { +- pinctrl-single,bits = < +- /* VP_DOUT[2..7] */ +- 0x40 0x11111100 0xffffff00 +- /* VP_DOUT[10..15,0..1] */ +- 0x44 0x11111111 0xffffffff +- /* VP_DOUT[8..9] */ +- 0x48 0x00000011 0x000000ff +- /* +- * VP_CLKOUT3, VP_CLKIN3, +- * VP_CLKOUT2, VP_CLKIN2 +- */ +- 0x4c 0x00111100 0x00ffff00 +- >; +- }; +- }; +- prictrl: priority-controller@14110 { +- compatible = "ti,da850-mstpri"; +- reg = <0x14110 0x0c>; +- status = "disabled"; +- }; +- cfgchip: chip-controller@1417c { +- compatible = "ti,da830-cfgchip", "syscon", "simple-mfd"; +- reg = <0x1417c 0x14>; +- +- usb_phy: usb-phy { +- compatible = "ti,da830-usb-phy"; +- #phy-cells = <1>; +- clocks = <&usb_phy_clk 0>, <&usb_phy_clk 1>; +- clock-names = "usb0_clk48", "usb1_clk48"; +- status = "disabled"; +- }; +- usb_phy_clk: usb-phy-clocks { +- compatible = "ti,da830-usb-phy-clocks"; +- #clock-cells = <1>; +- clocks = <&psc1 1>, <&usb_refclkin>, +- <&pll0_auxclk>; +- clock-names = "fck", "usb_refclkin", "auxclk"; +- }; +- ehrpwm_tbclk: ehrpwm_tbclk { +- compatible = "ti,da830-tbclksync"; +- #clock-cells = <0>; +- clocks = <&psc1 17>; +- clock-names = "fck"; +- }; +- div4p5_clk: div4.5 { +- compatible = "ti,da830-div4p5ena"; +- #clock-cells = <0>; +- clocks = <&pll0_pllout>; +- clock-names = "pll0_pllout"; +- }; +- async1_clk: async1 { +- compatible = "ti,da850-async1-clksrc"; +- #clock-cells = <0>; +- clocks = <&pll0_sysclk 3>, <&div4p5_clk>; +- clock-names = "pll0_sysclk3", "div4.5"; +- }; +- async3_clk: async3 { +- compatible = "ti,da850-async3-clksrc"; +- #clock-cells = <0>; +- clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>; +- clock-names = "pll0_sysclk2", "pll1_sysclk2"; +- }; +- }; +- edma0: edma@0 { +- compatible = "ti,edma3-tpcc"; +- /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */ +- reg = <0x0 0x8000>; +- reg-names = "edma3_cc"; +- interrupts = <11 12>; +- interrupt-names = "edma3_ccint", "edma3_ccerrint"; +- #dma-cells = <2>; +- +- ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; +- power-domains = <&psc0 0>; +- }; +- edma0_tptc0: tptc@8000 { +- compatible = "ti,edma3-tptc"; +- reg = <0x8000 0x400>; +- interrupts = <13>; +- interrupt-names = "edm3_tcerrint"; +- power-domains = <&psc0 1>; +- }; +- edma0_tptc1: tptc@8400 { +- compatible = "ti,edma3-tptc"; +- reg = <0x8400 0x400>; +- interrupts = <32>; +- interrupt-names = "edm3_tcerrint"; +- power-domains = <&psc0 2>; +- }; +- edma1: edma@230000 { +- compatible = "ti,edma3-tpcc"; +- /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */ +- reg = <0x230000 0x8000>; +- reg-names = "edma3_cc"; +- interrupts = <93 94>; +- interrupt-names = "edma3_ccint", "edma3_ccerrint"; +- #dma-cells = <2>; +- +- ti,tptcs = <&edma1_tptc0 7>; +- power-domains = <&psc1 0>; +- }; +- edma1_tptc0: tptc@238000 { +- compatible = "ti,edma3-tptc"; +- reg = <0x238000 0x400>; +- interrupts = <95>; +- interrupt-names = "edm3_tcerrint"; +- power-domains = <&psc1 21>; +- }; +- serial0: serial@42000 { +- compatible = "ti,da830-uart", "ns16550a"; +- reg = <0x42000 0x100>; +- reg-io-width = <4>; +- reg-shift = <2>; +- interrupts = <25>; +- clocks = <&psc0 9>; +- power-domains = <&psc0 9>; +- status = "disabled"; +- }; +- serial1: serial@10c000 { +- compatible = "ti,da830-uart", "ns16550a"; +- reg = <0x10c000 0x100>; +- reg-io-width = <4>; +- reg-shift = <2>; +- interrupts = <53>; +- clocks = <&psc1 12>; +- power-domains = <&psc1 12>; +- status = "disabled"; +- }; +- serial2: serial@10d000 { +- compatible = "ti,da830-uart", "ns16550a"; +- reg = <0x10d000 0x100>; +- reg-io-width = <4>; +- reg-shift = <2>; +- interrupts = <61>; +- clocks = <&psc1 13>; +- power-domains = <&psc1 13>; +- status = "disabled"; +- }; +- rtc0: rtc@23000 { +- compatible = "ti,da830-rtc"; +- reg = <0x23000 0x1000>; +- interrupts = <19 +- 19>; +- clocks = <&pll0_auxclk>; +- clock-names = "int-clk"; +- status = "disabled"; +- }; +- i2c0: i2c@22000 { +- compatible = "ti,davinci-i2c"; +- reg = <0x22000 0x1000>; +- interrupts = <15>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pll0_auxclk>; +- status = "disabled"; +- }; +- i2c1: i2c@228000 { +- compatible = "ti,davinci-i2c"; +- reg = <0x228000 0x1000>; +- interrupts = <51>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&psc1 11>; +- power-domains = <&psc1 11>; +- status = "disabled"; +- }; +- clocksource: timer@20000 { +- compatible = "ti,da830-timer"; +- reg = <0x20000 0x1000>; +- interrupts = <21>, <22>; +- interrupt-names = "tint12", "tint34"; +- clocks = <&pll0_auxclk>; +- }; +- wdt: wdt@21000 { +- compatible = "ti,davinci-wdt"; +- reg = <0x21000 0x1000>; +- clocks = <&pll0_auxclk>; +- status = "disabled"; +- }; +- mmc0: mmc@40000 { +- compatible = "ti,da830-mmc"; +- reg = <0x40000 0x1000>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- interrupts = <16>; +- dmas = <&edma0 16 0>, <&edma0 17 0>; +- dma-names = "rx", "tx"; +- clocks = <&psc0 5>; +- status = "disabled"; +- }; +- vpif: video@217000 { +- compatible = "ti,da850-vpif"; +- reg = <0x217000 0x1000>; +- interrupts = <92>; +- power-domains = <&psc1 9>; +- status = "disabled"; +- +- /* VPIF capture port */ +- port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- /* VPIF display port */ +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- mmc1: mmc@21b000 { +- compatible = "ti,da830-mmc"; +- reg = <0x21b000 0x1000>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- interrupts = <72>; +- dmas = <&edma1 28 0>, <&edma1 29 0>; +- dma-names = "rx", "tx"; +- clocks = <&psc1 18>; +- status = "disabled"; +- }; +- ehrpwm0: pwm@300000 { +- compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x300000 0x2000>; +- clocks = <&psc1 17>, <&ehrpwm_tbclk>; +- clock-names = "fck", "tbclk"; +- power-domains = <&psc1 17>; +- status = "disabled"; +- }; +- ehrpwm1: pwm@302000 { +- compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x302000 0x2000>; +- clocks = <&psc1 17>, <&ehrpwm_tbclk>; +- clock-names = "fck", "tbclk"; +- power-domains = <&psc1 17>; +- status = "disabled"; +- }; +- ecap0: pwm@306000 { +- compatible = "ti,da850-ecap", "ti,am3352-ecap"; +- #pwm-cells = <3>; +- reg = <0x306000 0x80>; +- clocks = <&psc1 20>; +- clock-names = "fck"; +- power-domains = <&psc1 20>; +- status = "disabled"; +- }; +- ecap1: pwm@307000 { +- compatible = "ti,da850-ecap", "ti,am3352-ecap"; +- #pwm-cells = <3>; +- reg = <0x307000 0x80>; +- clocks = <&psc1 20>; +- clock-names = "fck"; +- power-domains = <&psc1 20>; +- status = "disabled"; +- }; +- ecap2: pwm@308000 { +- compatible = "ti,da850-ecap", "ti,am3352-ecap"; +- #pwm-cells = <3>; +- reg = <0x308000 0x80>; +- clocks = <&psc1 20>; +- clock-names = "fck"; +- power-domains = <&psc1 20>; +- status = "disabled"; +- }; +- spi0: spi@41000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "ti,da830-spi"; +- reg = <0x41000 0x1000>; +- num-cs = <6>; +- ti,davinci-spi-intr-line = <1>; +- interrupts = <20>; +- dmas = <&edma0 14 0>, <&edma0 15 0>; +- dma-names = "rx", "tx"; +- clocks = <&psc0 4>; +- power-domains = <&psc0 4>; +- status = "disabled"; +- }; +- spi1: spi@30e000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "ti,da830-spi"; +- reg = <0x30e000 0x1000>; +- num-cs = <4>; +- ti,davinci-spi-intr-line = <1>; +- interrupts = <56>; +- dmas = <&edma0 18 0>, <&edma0 19 0>; +- dma-names = "rx", "tx"; +- clocks = <&psc1 10>; +- power-domains = <&psc1 10>; +- status = "disabled"; +- }; +- usb0: usb@200000 { +- compatible = "ti,da830-musb"; +- reg = <0x200000 0x1000>; +- ranges; +- interrupts = <58>; +- interrupt-names = "mc"; +- dr_mode = "otg"; +- phys = <&usb_phy 0>; +- phy-names = "usb-phy"; +- clocks = <&psc1 1>; +- clock-ranges; +- status = "disabled"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- dmas = <&cppi41dma 0 0 &cppi41dma 1 0 +- &cppi41dma 2 0 &cppi41dma 3 0 +- &cppi41dma 0 1 &cppi41dma 1 1 +- &cppi41dma 2 1 &cppi41dma 3 1>; +- dma-names = +- "rx1", "rx2", "rx3", "rx4", +- "tx1", "tx2", "tx3", "tx4"; +- +- cppi41dma: dma-controller@201000 { +- compatible = "ti,da830-cppi41"; +- reg = <0x201000 0x1000 +- 0x202000 0x1000 +- 0x204000 0x4000>; +- reg-names = "controller", +- "scheduler", "queuemgr"; +- interrupts = <58>; +- #dma-cells = <2>; +- #dma-channels = <4>; +- power-domains = <&psc1 1>; +- status = "okay"; +- }; +- }; +- sata: sata@218000 { +- compatible = "ti,da850-ahci"; +- reg = <0x218000 0x2000>, <0x22c018 0x4>; +- interrupts = <67>; +- clocks = <&psc1 8>, <&sata_refclk>; +- clock-names = "fck", "refclk"; +- status = "disabled"; +- }; +- pll1: clock-controller@21a000 { +- compatible = "ti,da850-pll1"; +- reg = <0x21a000 0x1000>; +- clocks = <&ref_clk>; +- clock-names = "clksrc"; +- +- pll1_sysclk: sysclk { +- #clock-cells = <1>; +- }; +- pll1_obsclk: obsclk { +- #clock-cells = <0>; +- }; +- }; +- mdio: mdio@224000 { +- compatible = "ti,davinci_mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x224000 0x1000>; +- clocks = <&psc1 5>; +- clock-names = "fck"; +- power-domains = <&psc1 5>; +- status = "disabled"; +- }; +- eth0: ethernet@220000 { +- compatible = "ti,davinci-dm6467-emac"; +- reg = <0x220000 0x4000>; +- ti,davinci-ctrl-reg-offset = <0x3000>; +- ti,davinci-ctrl-mod-reg-offset = <0x2000>; +- ti,davinci-ctrl-ram-offset = <0>; +- ti,davinci-ctrl-ram-size = <0x2000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <33 +- 34 +- 35 +- 36 +- >; +- clocks = <&psc1 5>; +- power-domains = <&psc1 5>; +- status = "disabled"; +- }; +- usb1: usb@225000 { +- compatible = "ti,da830-ohci"; +- reg = <0x225000 0x1000>; +- interrupts = <59>; +- phys = <&usb_phy 1>; +- phy-names = "usb-phy"; +- clocks = <&psc1 2>; +- status = "disabled"; +- }; +- gpio: gpio@226000 { +- compatible = "ti,dm6441-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x226000 0x1000>; +- interrupts = <42 43 44 45 46 47 48 49 50>; +- ti,ngpio = <144>; +- ti,davinci-gpio-unbanked = <0>; +- clocks = <&psc1 3>; +- clock-names = "gpio"; +- status = "disabled"; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&pmx_core 0 15 1>, +- <&pmx_core 1 14 1>, +- <&pmx_core 2 13 1>, +- <&pmx_core 3 12 1>, +- <&pmx_core 4 11 1>, +- <&pmx_core 5 10 1>, +- <&pmx_core 6 9 1>, +- <&pmx_core 7 8 1>, +- <&pmx_core 8 7 1>, +- <&pmx_core 9 6 1>, +- <&pmx_core 10 5 1>, +- <&pmx_core 11 4 1>, +- <&pmx_core 12 3 1>, +- <&pmx_core 13 2 1>, +- <&pmx_core 14 1 1>, +- <&pmx_core 15 0 1>, +- <&pmx_core 16 39 1>, +- <&pmx_core 17 38 1>, +- <&pmx_core 18 37 1>, +- <&pmx_core 19 36 1>, +- <&pmx_core 20 35 1>, +- <&pmx_core 21 34 1>, +- <&pmx_core 22 33 1>, +- <&pmx_core 23 32 1>, +- <&pmx_core 24 24 1>, +- <&pmx_core 25 22 1>, +- <&pmx_core 26 21 1>, +- <&pmx_core 27 20 1>, +- <&pmx_core 28 19 1>, +- <&pmx_core 29 18 1>, +- <&pmx_core 30 17 1>, +- <&pmx_core 31 16 1>, +- <&pmx_core 32 55 1>, +- <&pmx_core 33 54 1>, +- <&pmx_core 34 53 1>, +- <&pmx_core 35 52 1>, +- <&pmx_core 36 51 1>, +- <&pmx_core 37 50 1>, +- <&pmx_core 38 49 1>, +- <&pmx_core 39 48 1>, +- <&pmx_core 40 47 1>, +- <&pmx_core 41 46 1>, +- <&pmx_core 42 45 1>, +- <&pmx_core 43 44 1>, +- <&pmx_core 44 43 1>, +- <&pmx_core 45 42 1>, +- <&pmx_core 46 41 1>, +- <&pmx_core 47 40 1>, +- <&pmx_core 48 71 1>, +- <&pmx_core 49 70 1>, +- <&pmx_core 50 69 1>, +- <&pmx_core 51 68 1>, +- <&pmx_core 52 67 1>, +- <&pmx_core 53 66 1>, +- <&pmx_core 54 65 1>, +- <&pmx_core 55 64 1>, +- <&pmx_core 56 63 1>, +- <&pmx_core 57 62 1>, +- <&pmx_core 58 61 1>, +- <&pmx_core 59 60 1>, +- <&pmx_core 60 59 1>, +- <&pmx_core 61 58 1>, +- <&pmx_core 62 57 1>, +- <&pmx_core 63 56 1>, +- <&pmx_core 64 87 1>, +- <&pmx_core 65 86 1>, +- <&pmx_core 66 85 1>, +- <&pmx_core 67 84 1>, +- <&pmx_core 68 83 1>, +- <&pmx_core 69 82 1>, +- <&pmx_core 70 81 1>, +- <&pmx_core 71 80 1>, +- <&pmx_core 72 70 1>, +- <&pmx_core 73 78 1>, +- <&pmx_core 74 77 1>, +- <&pmx_core 75 76 1>, +- <&pmx_core 76 75 1>, +- <&pmx_core 77 74 1>, +- <&pmx_core 78 73 1>, +- <&pmx_core 79 72 1>, +- <&pmx_core 80 103 1>, +- <&pmx_core 81 102 1>, +- <&pmx_core 82 101 1>, +- <&pmx_core 83 100 1>, +- <&pmx_core 84 99 1>, +- <&pmx_core 85 98 1>, +- <&pmx_core 86 97 1>, +- <&pmx_core 87 96 1>, +- <&pmx_core 88 95 1>, +- <&pmx_core 89 94 1>, +- <&pmx_core 90 93 1>, +- <&pmx_core 91 92 1>, +- <&pmx_core 92 91 1>, +- <&pmx_core 93 90 1>, +- <&pmx_core 94 89 1>, +- <&pmx_core 95 88 1>, +- <&pmx_core 96 158 1>, +- <&pmx_core 97 157 1>, +- <&pmx_core 98 156 1>, +- <&pmx_core 99 155 1>, +- <&pmx_core 100 154 1>, +- <&pmx_core 101 129 1>, +- <&pmx_core 102 113 1>, +- <&pmx_core 103 112 1>, +- <&pmx_core 104 111 1>, +- <&pmx_core 105 110 1>, +- <&pmx_core 106 109 1>, +- <&pmx_core 107 108 1>, +- <&pmx_core 108 107 1>, +- <&pmx_core 109 106 1>, +- <&pmx_core 110 105 1>, +- <&pmx_core 111 104 1>, +- <&pmx_core 112 145 1>, +- <&pmx_core 113 144 1>, +- <&pmx_core 114 143 1>, +- <&pmx_core 115 142 1>, +- <&pmx_core 116 141 1>, +- <&pmx_core 117 140 1>, +- <&pmx_core 118 139 1>, +- <&pmx_core 119 138 1>, +- <&pmx_core 120 137 1>, +- <&pmx_core 121 136 1>, +- <&pmx_core 122 135 1>, +- <&pmx_core 123 134 1>, +- <&pmx_core 124 133 1>, +- <&pmx_core 125 132 1>, +- <&pmx_core 126 131 1>, +- <&pmx_core 127 130 1>, +- <&pmx_core 128 159 1>, +- <&pmx_core 129 31 1>, +- <&pmx_core 130 30 1>, +- <&pmx_core 131 20 1>, +- <&pmx_core 132 28 1>, +- <&pmx_core 133 27 1>, +- <&pmx_core 134 26 1>, +- <&pmx_core 135 23 1>, +- <&pmx_core 136 153 1>, +- <&pmx_core 137 152 1>, +- <&pmx_core 138 151 1>, +- <&pmx_core 139 150 1>, +- <&pmx_core 140 149 1>, +- <&pmx_core 141 148 1>, +- <&pmx_core 142 147 1>, +- <&pmx_core 143 146 1>; +- }; +- psc1: clock-controller@227000 { +- compatible = "ti,da850-psc1"; +- reg = <0x227000 0x1000>; +- #clock-cells = <1>; +- #power-domain-cells = <1>; +- clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, +- <&async3_clk>; +- clock-names = "pll0_sysclk2", "pll0_sysclk4", "async3"; +- assigned-clocks = <&async3_clk>; +- assigned-clock-parents = <&pll1_sysclk 2>; +- }; +- pinconf: pin-controller@22c00c { +- compatible = "ti,da850-pupd"; +- reg = <0x22c00c 0x8>; +- status = "disabled"; +- }; +- +- mcasp0: mcasp@100000 { +- compatible = "ti,da830-mcasp-audio"; +- reg = <0x100000 0x2000>, +- <0x102000 0x400000>; +- reg-names = "mpu", "dat"; +- interrupts = <54>; +- interrupt-names = "common"; +- power-domains = <&psc1 7>; +- status = "disabled"; +- dmas = <&edma0 1 1>, +- <&edma0 0 1>; +- dma-names = "tx", "rx"; +- }; +- +- lcdc: display@213000 { +- compatible = "ti,da850-tilcdc"; +- reg = <0x213000 0x1000>; +- interrupts = <52>; +- max-pixelclock = <37500>; +- clocks = <&psc1 16>; +- clock-names = "fck"; +- power-domains = <&psc1 16>; +- status = "disabled"; +- }; +- }; +- aemif: aemif@68000000 { +- compatible = "ti,da850-aemif"; +- #address-cells = <2>; +- #size-cells = <1>; +- +- reg = <0x68000000 0x00008000>; +- ranges = <0 0 0x60000000 0x08000000 +- 1 0 0x68000000 0x00008000>; +- clocks = <&psc0 3>; +- clock-names = "aemif"; +- clock-ranges; +- status = "disabled"; +- }; +- memctrl: memory-controller@b0000000 { +- compatible = "ti,da850-ddr-controller"; +- reg = <0xb0000000 0xe8>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dm3725.dtsi b/scripts/dtc/include-prefixes/arm/dm3725.dtsi +deleted file mode 100644 +index d24e906a14b1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dm3725.dtsi ++++ /dev/null +@@ -1,10 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2020 André Hentschel +- */ +- +-#include "omap36xx.dtsi" +- +-&sgx_module { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dm8148-evm.dts b/scripts/dtc/include-prefixes/arm/dm8148-evm.dts +deleted file mode 100644 +index 8ef48c00f98d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dm8148-evm.dts ++++ /dev/null +@@ -1,155 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/dts-v1/; +- +-#include "dm814x.dtsi" +-#include +- +-/ { +- model = "DM8148 EVM"; +- compatible = "ti,dm8148-evm", "ti,dm8148", "ti,dm814"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; /* 1 GB */ +- }; +- +- /* MIC94060YC6 controlled by SD1_POW pin */ +- vmmcsd_fixed: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsd_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&cpsw_emac0 { +- phy-handle = <ðphy0>; +- phy-mode = "rgmii-id"; +-}; +- +-&cpsw_emac1 { +- phy-handle = <ðphy1>; +- phy-mode = "rgmii-id"; +-}; +- +-&davinci_mdio { +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&gpmc { +- ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ +- +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- linux,mtd-name= "micron,mt29f2g16aadwp"; +- #address-cells = <1>; +- #size-cells = <1>; +- ti,nand-ecc-opt = "bch8"; +- nand-bus-width = <16>; +- gpmc,device-width = <2>; +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-on-ns = <0>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- partition@0 { +- label = "X-Loader"; +- reg = <0 0x80000>; +- }; +- partition@80000 { +- label = "U-Boot"; +- reg = <0x80000 0x1c0000>; +- }; +- partition@1c0000 { +- label = "Environment"; +- reg = <0x240000 0x40000>; +- }; +- partition@280000 { +- label = "Kernel"; +- reg = <0x280000 0x500000>; +- }; +- partition@780000 { +- label = "Filesystem"; +- reg = <0x780000 0xf880000>; +- }; +- }; +-}; +- +-&mmc1 { +- status = "disabled"; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sd1_pins>; +- vmmc-supply = <&vmmcsd_fixed>; +- bus-width = <4>; +- cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-&pincntl { +- sd1_pins: pinmux_sd1_pins { +- pinctrl-single,pins = < +- DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ +- DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ +- DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ +- DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ +- DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ +- DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ +- DM814X_IOPAD(0x0924, PIN_OUTPUT | 0x40) /* SD1_POW */ +- DM814X_IOPAD(0x093C, PIN_INPUT_PULLUP | 0x80) /* GP1[6] */ +- >; +- }; +- +- usb0_pins: pinmux_usb0_pins { +- pinctrl-single,pins = < +- DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ +- >; +- }; +- +- usb1_pins: pinmux_usb1_pins { +- pinctrl-single,pins = < +- DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ +- >; +- }; +-}; +- +-&usb0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb0_pins>; +- dr_mode = "host"; +-}; +- +-&usb1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb1_pins>; +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dm8148-t410.dts b/scripts/dtc/include-prefixes/arm/dm8148-t410.dts +deleted file mode 100644 +index 79ccdd4470f4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dm8148-t410.dts ++++ /dev/null +@@ -1,113 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/dts-v1/; +- +-#include "dm814x.dtsi" +- +-/ { +- model = "HP t410 Smart Zero Client"; +- compatible = "hp,t410", "ti,dm8148", "ti,dm814"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; /* 1 GB */ +- }; +- +- /* gpio9 seems to control USB VBUS regulator and/or hub power */ +- usb_power: regulator@9 { +- compatible = "regulator-fixed"; +- regulator-name = "usb_power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- vmmcsd_fixed: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsd_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&cpsw_emac0 { +- phy-handle = <ðphy0>; +- phy-mode = "rgmii-id"; +-}; +- +-&cpsw_emac1 { +- phy-handle = <ðphy1>; +- phy-mode = "rgmii-id"; +-}; +- +-&davinci_mdio { +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc1 { +- status = "disabled"; +-}; +- +-&mmc2 { +- status = "disabled"; +-}; +- +-&mmc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sd2_pins>; +- vmmc-supply = <&vmmcsd_fixed>; +- bus-width = <8>; +- dmas = <&edma_xbar 8 0 1 /* use SDTXEVT1 instead of MCASP0TX */ +- &edma_xbar 9 0 2>; /* use SDRXEVT1 instead of MCASP0RX */ +- dma-names = "tx", "rx"; +- non-removable; +-}; +- +-&pincntl { +- sd2_pins: pinmux_sd2_pins { +- pinctrl-single,pins = < +- DM814X_IOPAD(0x09c0, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[7] */ +- DM814X_IOPAD(0x09c4, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[6] */ +- DM814X_IOPAD(0x09c8, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[5] */ +- DM814X_IOPAD(0x09cc, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[4] */ +- DM814X_IOPAD(0x09d0, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[3] */ +- DM814X_IOPAD(0x09d4, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[2] */ +- DM814X_IOPAD(0x09d8, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[1] */ +- DM814X_IOPAD(0x09dc, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[0] */ +- DM814X_IOPAD(0x09e0, PIN_INPUT | 0x1) /* SD2_CLK */ +- DM814X_IOPAD(0x09f4, PIN_INPUT_PULLUP | 0x2) /* SD2_CMD */ +- DM814X_IOPAD(0x0920, PIN_INPUT | 0x40) /* SD2_SDCD */ +- >; +- }; +- +- usb0_pins: pinmux_usb0_pins { +- pinctrl-single,pins = < +- DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ +- >; +- }; +- +- usb1_pins: pinmux_usb1_pins { +- pinctrl-single,pins = < +- DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ +- >; +- }; +-}; +- +-&usb0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb0_pins>; +- dr_mode = "host"; +-}; +- +-&usb1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb1_pins>; +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dm814x-clocks.dtsi b/scripts/dtc/include-prefixes/arm/dm814x-clocks.dtsi +deleted file mode 100644 +index f7939f43413b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dm814x-clocks.dtsi ++++ /dev/null +@@ -1,379 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +- +-&pllss { +- /* +- * See TRM "2.6.10 Connected outputso DPLLS" and +- * "2.6.11 Connected Outputs of DPLLJ". Only clkout is +- * connected except for hdmi and usb. +- */ +- adpll_mpu_ck: adpll@40 { +- #clock-cells = <1>; +- compatible = "ti,dm814-adpll-s-clock"; +- reg = <0x40 0x40>; +- clocks = <&devosc_ck &devosc_ck &devosc_ck>; +- clock-names = "clkinp", "clkinpulow", "clkinphif"; +- clock-output-names = "481c5040.adpll.dcoclkldo", +- "481c5040.adpll.clkout", +- "481c5040.adpll.clkoutx2", +- "481c5040.adpll.clkouthif"; +- }; +- +- adpll_dsp_ck: adpll@80 { +- #clock-cells = <1>; +- compatible = "ti,dm814-adpll-lj-clock"; +- reg = <0x80 0x30>; +- clocks = <&devosc_ck &devosc_ck>; +- clock-names = "clkinp", "clkinpulow"; +- clock-output-names = "481c5080.adpll.dcoclkldo", +- "481c5080.adpll.clkout", +- "481c5080.adpll.clkoutldo"; +- }; +- +- adpll_sgx_ck: adpll@b0 { +- #clock-cells = <1>; +- compatible = "ti,dm814-adpll-lj-clock"; +- reg = <0xb0 0x30>; +- clocks = <&devosc_ck &devosc_ck>; +- clock-names = "clkinp", "clkinpulow"; +- clock-output-names = "481c50b0.adpll.dcoclkldo", +- "481c50b0.adpll.clkout", +- "481c50b0.adpll.clkoutldo"; +- }; +- +- adpll_hdvic_ck: adpll@e0 { +- #clock-cells = <1>; +- compatible = "ti,dm814-adpll-lj-clock"; +- reg = <0xe0 0x30>; +- clocks = <&devosc_ck &devosc_ck>; +- clock-names = "clkinp", "clkinpulow"; +- clock-output-names = "481c50e0.adpll.dcoclkldo", +- "481c50e0.adpll.clkout", +- "481c50e0.adpll.clkoutldo"; +- }; +- +- adpll_l3_ck: adpll@110 { +- #clock-cells = <1>; +- compatible = "ti,dm814-adpll-lj-clock"; +- reg = <0x110 0x30>; +- clocks = <&devosc_ck &devosc_ck>; +- clock-names = "clkinp", "clkinpulow"; +- clock-output-names = "481c5110.adpll.dcoclkldo", +- "481c5110.adpll.clkout", +- "481c5110.adpll.clkoutldo"; +- }; +- +- adpll_isp_ck: adpll@140 { +- #clock-cells = <1>; +- compatible = "ti,dm814-adpll-lj-clock"; +- reg = <0x140 0x30>; +- clocks = <&devosc_ck &devosc_ck>; +- clock-names = "clkinp", "clkinpulow"; +- clock-output-names = "481c5140.adpll.dcoclkldo", +- "481c5140.adpll.clkout", +- "481c5140.adpll.clkoutldo"; +- }; +- +- adpll_dss_ck: adpll@170 { +- #clock-cells = <1>; +- compatible = "ti,dm814-adpll-lj-clock"; +- reg = <0x170 0x30>; +- clocks = <&devosc_ck &devosc_ck>; +- clock-names = "clkinp", "clkinpulow"; +- clock-output-names = "481c5170.adpll.dcoclkldo", +- "481c5170.adpll.clkout", +- "481c5170.adpll.clkoutldo"; +- }; +- +- adpll_video0_ck: adpll@1a0 { +- #clock-cells = <1>; +- compatible = "ti,dm814-adpll-lj-clock"; +- reg = <0x1a0 0x30>; +- clocks = <&devosc_ck &devosc_ck>; +- clock-names = "clkinp", "clkinpulow"; +- clock-output-names = "481c51a0.adpll.dcoclkldo", +- "481c51a0.adpll.clkout", +- "481c51a0.adpll.clkoutldo"; +- }; +- +- adpll_video1_ck: adpll@1d0 { +- #clock-cells = <1>; +- compatible = "ti,dm814-adpll-lj-clock"; +- reg = <0x1d0 0x30>; +- clocks = <&devosc_ck &devosc_ck>; +- clock-names = "clkinp", "clkinpulow"; +- clock-output-names = "481c51d0.adpll.dcoclkldo", +- "481c51d0.adpll.clkout", +- "481c51d0.adpll.clkoutldo"; +- }; +- +- adpll_hdmi_ck: adpll@200 { +- #clock-cells = <1>; +- compatible = "ti,dm814-adpll-lj-clock"; +- reg = <0x200 0x30>; +- clocks = <&devosc_ck &devosc_ck>; +- clock-names = "clkinp", "clkinpulow"; +- clock-output-names = "481c5200.adpll.dcoclkldo", +- "481c5200.adpll.clkout", +- "481c5200.adpll.clkoutldo"; +- }; +- +- adpll_audio_ck: adpll@230 { +- #clock-cells = <1>; +- compatible = "ti,dm814-adpll-lj-clock"; +- reg = <0x230 0x30>; +- clocks = <&devosc_ck &devosc_ck>; +- clock-names = "clkinp", "clkinpulow"; +- clock-output-names = "481c5230.adpll.dcoclkldo", +- "481c5230.adpll.clkout", +- "481c5230.adpll.clkoutldo"; +- }; +- +- adpll_usb_ck: adpll@260 { +- #clock-cells = <1>; +- compatible = "ti,dm814-adpll-lj-clock"; +- reg = <0x260 0x30>; +- clocks = <&devosc_ck &devosc_ck>; +- clock-names = "clkinp", "clkinpulow"; +- clock-output-names = "481c5260.adpll.dcoclkldo", +- "481c5260.adpll.clkout", +- "481c5260.adpll.clkoutldo"; +- }; +- +- adpll_ddr_ck: adpll@290 { +- #clock-cells = <1>; +- compatible = "ti,dm814-adpll-lj-clock"; +- reg = <0x290 0x30>; +- clocks = <&devosc_ck &devosc_ck>; +- clock-names = "clkinp", "clkinpulow"; +- clock-output-names = "481c5290.adpll.dcoclkldo", +- "481c5290.adpll.clkout", +- "481c5290.adpll.clkoutldo"; +- }; +-}; +- +-&pllss_clocks { +- timer1_fck: timer1_fck@2e0 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck +- &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; +- ti,bit-shift = <3>; +- reg = <0x2e0>; +- }; +- +- timer2_fck: timer2_fck@2e0 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck +- &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; +- ti,bit-shift = <6>; +- reg = <0x2e0>; +- }; +- +- /* CPTS_RFT_CLK in RMII_REFCLK_SRC, usually sourced from auiod */ +- cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&adpll_video0_ck 1 +- &adpll_video1_ck 1 +- &adpll_audio_ck 1>; +- ti,bit-shift = <1>; +- reg = <0x2e8>; +- }; +- +- /* REVISIT: Set up with a proper mux using RMII_REFCLK_SRC */ +- cpsw_125mhz_gclk: cpsw_125mhz_gclk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- }; +- +- sysclk18_ck: sysclk18_ck@2f0 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&rtcosc_ck>, <&rtcdivider_ck>; +- ti,bit-shift = <0>; +- reg = <0x02f0>; +- }; +-}; +- +-&scm_clocks { +- devosc_ck: devosc_ck@40 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&virt_20000000_ck>, <&virt_19200000_ck>; +- ti,bit-shift = <21>; +- reg = <0x0040>; +- }; +- +- /* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */ +- auxosc_ck: auxosc_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <22572900>; +- }; +- +- /* Optional 32768Hz crystal or clock on RTCOSC pins */ +- rtcosc_ck: rtcosc_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- /* Optional external clock on TCLKIN pin, set rate in baord dts file */ +- tclkin_ck: tclkin_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- virt_20000000_ck: virt_20000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <20000000>; +- }; +- +- virt_19200000_ck: virt_19200000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <19200000>; +- }; +- +- mpu_ck: mpu_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <1000000000>; +- }; +-}; +- +-&prcm_clocks { +- osc_src_ck: osc_src_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&devosc_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- mpu_clksrc_ck: mpu_clksrc_ck@40 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&devosc_ck>, <&rtcdivider_ck>; +- ti,bit-shift = <0>; +- reg = <0x0040>; +- }; +- +- /* Fixed divider clock 0.0016384 * devosc */ +- rtcdivider_ck: rtcdivider_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&devosc_ck>; +- clock-mult = <128>; +- clock-div = <78125>; +- }; +- +- /* L4_HS 220 MHz*/ +- sysclk4_ck: sysclk4_ck { +- #clock-cells = <0>; +- compatible = "ti,fixed-factor-clock"; +- clocks = <&adpll_l3_ck 1>; +- ti,clock-mult = <1>; +- ti,clock-div = <1>; +- }; +- +- /* L4_FWCFG */ +- sysclk5_ck: sysclk5_ck { +- #clock-cells = <0>; +- compatible = "ti,fixed-factor-clock"; +- clocks = <&adpll_l3_ck 1>; +- ti,clock-mult = <1>; +- ti,clock-div = <2>; +- }; +- +- /* L4_LS 110 MHz */ +- sysclk6_ck: sysclk6_ck { +- #clock-cells = <0>; +- compatible = "ti,fixed-factor-clock"; +- clocks = <&adpll_l3_ck 1>; +- ti,clock-mult = <1>; +- ti,clock-div = <2>; +- }; +- +- sysclk8_ck: sysclk8_ck { +- #clock-cells = <0>; +- compatible = "ti,fixed-factor-clock"; +- clocks = <&adpll_usb_ck 1>; +- ti,clock-mult = <1>; +- ti,clock-div = <1>; +- }; +- +- sysclk10_ck: sysclk10_ck { +- compatible = "ti,divider-clock"; +- reg = <0x324>; +- ti,max-div = <7>; +- #clock-cells = <0>; +- clocks = <&adpll_usb_ck 1>; +- }; +- +- aud_clkin0_ck: aud_clkin0_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <20000000>; +- }; +- +- aud_clkin1_ck: aud_clkin1_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <20000000>; +- }; +- +- aud_clkin2_ck: aud_clkin2_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <20000000>; +- }; +-}; +- +-&prcm { +- default_cm: default_cm@500 { +- compatible = "ti,omap4-cm"; +- reg = <0x500 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x500 0x100>; +- +- default_clkctrl: clk@0 { +- compatible = "ti,clkctrl"; +- reg = <0x0 0x5c>; +- #clock-cells = <2>; +- }; +- }; +- +- alwon_cm: alwon_cm@1400 { +- compatible = "ti,omap4-cm"; +- reg = <0x1400 0x300>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1400 0x300>; +- +- alwon_clkctrl: clk@0 { +- compatible = "ti,clkctrl"; +- reg = <0x0 0x228>; +- #clock-cells = <2>; +- }; +- }; +- +- alwon_ethernet_cm: alwon_ethernet_cm@15d4 { +- compatible = "ti,omap4-cm"; +- reg = <0x15d4 0x4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x15d4 0x4>; +- +- alwon_ethernet_clkctrl: clk@0 { +- compatible = "ti,clkctrl"; +- reg = <0 0x4>; +- #clock-cells = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dm814x.dtsi b/scripts/dtc/include-prefixes/arm/dm814x.dtsi +deleted file mode 100644 +index 7702e048e110..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dm814x.dtsi ++++ /dev/null +@@ -1,789 +0,0 @@ +-/* +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "ti,dm814"; +- interrupt-parent = <&intc>; +- #address-cells = <1>; +- #size-cells = <1>; +- chosen { }; +- +- aliases { +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- ethernet0 = &cpsw_emac0; +- ethernet1 = &cpsw_emac1; +- usb0 = &usb0; +- usb1 = &usb1; +- phy0 = &usb0_phy; +- phy1 = &usb1_phy; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- compatible = "arm,cortex-a8"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a8-pmu"; +- interrupts = <3>; +- }; +- +- /* +- * The soc node represents the soc top level view. It is used for IPs +- * that are not memory mapped in the MPU view or for the MPU itself. +- */ +- soc { +- compatible = "ti,omap-infra"; +- mpu { +- compatible = "ti,omap3-mpu"; +- ti,hwmods = "mpu"; +- }; +- }; +- +- ocp { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- ti,hwmods = "l3_main"; +- +- usb: usb@47400000 { +- compatible = "ti,am33xx-usb"; +- reg = <0x47400000 0x1000>; +- ranges; +- #address-cells = <1>; +- #size-cells = <1>; +- ti,hwmods = "usb_otg_hs"; +- +- usb0_phy: usb-phy@47401300 { +- compatible = "ti,am335x-usb-phy"; +- reg = <0x47401300 0x100>; +- reg-names = "phy"; +- ti,ctrl_mod = <&usb_ctrl_mod>; +- #phy-cells = <0>; +- }; +- +- usb0: usb@47401000 { +- compatible = "ti,musb-am33xx"; +- reg = <0x47401400 0x400 +- 0x47401000 0x200>; +- reg-names = "mc", "control"; +- +- interrupts = <18>; +- interrupt-names = "mc"; +- dr_mode = "otg"; +- mentor,multipoint = <1>; +- mentor,num-eps = <16>; +- mentor,ram-bits = <12>; +- mentor,power = <500>; +- phys = <&usb0_phy>; +- +- dmas = <&cppi41dma 0 0 &cppi41dma 1 0 +- &cppi41dma 2 0 &cppi41dma 3 0 +- &cppi41dma 4 0 &cppi41dma 5 0 +- &cppi41dma 6 0 &cppi41dma 7 0 +- &cppi41dma 8 0 &cppi41dma 9 0 +- &cppi41dma 10 0 &cppi41dma 11 0 +- &cppi41dma 12 0 &cppi41dma 13 0 +- &cppi41dma 14 0 &cppi41dma 0 1 +- &cppi41dma 1 1 &cppi41dma 2 1 +- &cppi41dma 3 1 &cppi41dma 4 1 +- &cppi41dma 5 1 &cppi41dma 6 1 +- &cppi41dma 7 1 &cppi41dma 8 1 +- &cppi41dma 9 1 &cppi41dma 10 1 +- &cppi41dma 11 1 &cppi41dma 12 1 +- &cppi41dma 13 1 &cppi41dma 14 1>; +- dma-names = +- "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", +- "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", +- "rx14", "rx15", +- "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", +- "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", +- "tx14", "tx15"; +- }; +- +- usb1: usb@47401800 { +- compatible = "ti,musb-am33xx"; +- reg = <0x47401c00 0x400 +- 0x47401800 0x200>; +- reg-names = "mc", "control"; +- interrupts = <19>; +- interrupt-names = "mc"; +- dr_mode = "otg"; +- mentor,multipoint = <1>; +- mentor,num-eps = <16>; +- mentor,ram-bits = <12>; +- mentor,power = <500>; +- phys = <&usb1_phy>; +- +- dmas = <&cppi41dma 15 0 &cppi41dma 16 0 +- &cppi41dma 17 0 &cppi41dma 18 0 +- &cppi41dma 19 0 &cppi41dma 20 0 +- &cppi41dma 21 0 &cppi41dma 22 0 +- &cppi41dma 23 0 &cppi41dma 24 0 +- &cppi41dma 25 0 &cppi41dma 26 0 +- &cppi41dma 27 0 &cppi41dma 28 0 +- &cppi41dma 29 0 &cppi41dma 15 1 +- &cppi41dma 16 1 &cppi41dma 17 1 +- &cppi41dma 18 1 &cppi41dma 19 1 +- &cppi41dma 20 1 &cppi41dma 21 1 +- &cppi41dma 22 1 &cppi41dma 23 1 +- &cppi41dma 24 1 &cppi41dma 25 1 +- &cppi41dma 26 1 &cppi41dma 27 1 +- &cppi41dma 28 1 &cppi41dma 29 1>; +- dma-names = +- "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", +- "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", +- "rx14", "rx15", +- "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", +- "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", +- "tx14", "tx15"; +- }; +- +- cppi41dma: dma-controller@47402000 { +- compatible = "ti,am3359-cppi41"; +- reg = <0x47400000 0x1000 +- 0x47402000 0x1000 +- 0x47403000 0x1000 +- 0x47404000 0x4000>; +- reg-names = "glue", "controller", "scheduler", "queuemgr"; +- interrupts = <17>; +- interrupt-names = "glue"; +- #dma-cells = <2>; +- #dma-channels = <30>; +- #dma-requests = <256>; +- }; +- }; +- +- /* +- * See TRM "Table 1-317. L4LS Instance Summary" for hints. +- * It shows the module target agent registers though, so the +- * actual device is typically 0x1000 before the target agent +- * except in cases where the module is larger than 0x1000. +- */ +- l4ls: l4ls@48000000 { +- compatible = "ti,dm814-l4ls", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x48000000 0x2000000>; +- +- i2c1: i2c@28000 { +- compatible = "ti,omap4-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,hwmods = "i2c1"; +- reg = <0x28000 0x1000>; +- interrupts = <70>; +- }; +- +- elm: elm@80000 { +- compatible = "ti,814-elm"; +- ti,hwmods = "elm"; +- reg = <0x80000 0x2000>; +- interrupts = <4>; +- }; +- +- gpio1: gpio@32000 { +- compatible = "ti,omap4-gpio"; +- ti,hwmods = "gpio1"; +- ti,gpio-always-on; +- reg = <0x32000 0x2000>; +- interrupts = <96>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@4c000 { +- compatible = "ti,omap4-gpio"; +- ti,hwmods = "gpio2"; +- ti,gpio-always-on; +- reg = <0x4c000 0x2000>; +- interrupts = <98>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio@1ac000 { +- compatible = "ti,omap4-gpio"; +- ti,hwmods = "gpio3"; +- ti,gpio-always-on; +- reg = <0x1ac000 0x2000>; +- interrupts = <32>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio4: gpio@1ae000 { +- compatible = "ti,omap4-gpio"; +- ti,hwmods = "gpio4"; +- ti,gpio-always-on; +- reg = <0x1ae000 0x2000>; +- interrupts = <62>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- i2c2: i2c@2a000 { +- compatible = "ti,omap4-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,hwmods = "i2c2"; +- reg = <0x2a000 0x1000>; +- interrupts = <71>; +- }; +- +- mcspi1: spi@30000 { +- compatible = "ti,omap4-mcspi"; +- reg = <0x30000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <65>; +- ti,spi-num-cs = <4>; +- ti,hwmods = "mcspi1"; +- dmas = <&edma 16 0 &edma 17 0 +- &edma 18 0 &edma 19 0 +- &edma 20 0 &edma 21 0 +- &edma 22 0 &edma 23 0>; +- +- dma-names = "tx0", "rx0", "tx1", "rx1", +- "tx2", "rx2", "tx3", "rx3"; +- }; +- +- mcspi2: spi@1a0000 { +- compatible = "ti,omap4-mcspi"; +- reg = <0x1a0000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <125>; +- ti,spi-num-cs = <4>; +- ti,hwmods = "mcspi2"; +- dmas = <&edma 42 0 &edma 43 0 +- &edma 44 0 &edma 45 0>; +- dma-names = "tx0", "rx0", "tx1", "rx1"; +- }; +- +- /* Board must configure dmas with edma_xbar for EDMA */ +- mcspi3: spi@1a2000 { +- compatible = "ti,omap4-mcspi"; +- reg = <0x1a2000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <126>; +- ti,spi-num-cs = <4>; +- ti,hwmods = "mcspi3"; +- }; +- +- mcspi4: spi@1a4000 { +- compatible = "ti,omap4-mcspi"; +- reg = <0x1a4000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <127>; +- ti,spi-num-cs = <4>; +- ti,hwmods = "mcspi4"; +- }; +- +- timer1_target: target-module@2e000 { +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x2e000 0x4>, +- <0x2e010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- clocks = <&timer1_fck>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2e000 0x1000>; +- +- timer1: timer@0 { +- compatible = "ti,am335x-timer-1ms"; +- reg = <0x0 0x400>; +- interrupts = <67>; +- ti,timer-alwon; +- clocks = <&timer1_fck>; +- clock-names = "fck"; +- }; +- }; +- +- uart1: uart@20000 { +- compatible = "ti,am3352-uart", "ti,omap3-uart"; +- ti,hwmods = "uart1"; +- reg = <0x20000 0x2000>; +- clock-frequency = <48000000>; +- interrupts = <72>; +- dmas = <&edma 26 0 &edma 27 0>; +- dma-names = "tx", "rx"; +- }; +- +- uart2: uart@22000 { +- compatible = "ti,am3352-uart", "ti,omap3-uart"; +- ti,hwmods = "uart2"; +- reg = <0x22000 0x2000>; +- clock-frequency = <48000000>; +- interrupts = <73>; +- dmas = <&edma 28 0 &edma 29 0>; +- dma-names = "tx", "rx"; +- }; +- +- uart3: uart@24000 { +- compatible = "ti,am3352-uart", "ti,omap3-uart"; +- ti,hwmods = "uart3"; +- reg = <0x24000 0x2000>; +- clock-frequency = <48000000>; +- interrupts = <74>; +- dmas = <&edma 30 0 &edma 31 0>; +- dma-names = "tx", "rx"; +- }; +- +- timer2_target: target-module@40000 { +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x40000 0x4>, +- <0x40010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- clocks = <&timer2_fck>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x40000 0x1000>; +- +- timer2: timer@0 { +- compatible = "ti,dm814-timer"; +- reg = <0 0x1000>; +- interrupts = <68>; +- clocks = <&timer2_fck>; +- clock-names = "fck"; +- }; +- }; +- +- timer3: timer@42000 { +- compatible = "ti,dm814-timer"; +- reg = <0x42000 0x2000>; +- interrupts = <69>; +- ti,hwmods = "timer3"; +- }; +- +- mmc1: mmc@60000 { +- compatible = "ti,omap4-hsmmc"; +- ti,hwmods = "mmc1"; +- dmas = <&edma 24 0 +- &edma 25 0>; +- dma-names = "tx", "rx"; +- interrupts = <64>; +- interrupt-parent = <&intc>; +- reg = <0x60000 0x1000>; +- }; +- +- rtc: rtc@c0000 { +- compatible = "ti,am3352-rtc", "ti,da830-rtc"; +- reg = <0xc0000 0x1000>; +- interrupts = <75 76>; +- ti,hwmods = "rtc"; +- }; +- +- mmc2: mmc@1d8000 { +- compatible = "ti,omap4-hsmmc"; +- ti,hwmods = "mmc2"; +- dmas = <&edma 2 0 +- &edma 3 0>; +- dma-names = "tx", "rx"; +- interrupts = <28>; +- interrupt-parent = <&intc>; +- reg = <0x1d8000 0x1000>; +- }; +- +- control: control@140000 { +- compatible = "ti,dm814-scm", "simple-bus"; +- reg = <0x140000 0x20000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x140000 0x20000>; +- +- scm_conf: scm_conf@0 { +- compatible = "syscon", "simple-bus"; +- reg = <0x0 0x800>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x800>; +- +- phy_gmii_sel: phy-gmii-sel { +- compatible = "ti,dm814-phy-gmii-sel"; +- reg = <0x650 0x4>; +- #phy-cells = <1>; +- }; +- +- scm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- scm_clockdomains: clockdomains { +- }; +- }; +- +- usb_ctrl_mod: control@620 { +- compatible = "ti,am335x-usb-ctrl-module"; +- reg = <0x620 0x10 +- 0x648 0x4>; +- reg-names = "phy_ctrl", "wakeup"; +- }; +- +- edma_xbar: dma-router@f90 { +- compatible = "ti,am335x-edma-crossbar"; +- reg = <0xf90 0x40>; +- #dma-cells = <3>; +- dma-requests = <32>; +- dma-masters = <&edma>; +- }; +- +- /* +- * Note that silicon revision 2.1 and older +- * require input enabled (bit 18 set) for all +- * 3.3V I/Os to avoid cumulative hardware damage. +- * For more info, see errata advisory 2.1.87. +- * We leave bit 18 out of function-mask and rely +- * on the bootloader for it. +- */ +- pincntl: pinmux@800 { +- compatible = "pinctrl-single"; +- reg = <0x800 0x438>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0x307ff>; +- }; +- +- usb1_phy: usb-phy@1b00 { +- compatible = "ti,am335x-usb-phy"; +- reg = <0x1b00 0x100>; +- reg-names = "phy"; +- ti,ctrl_mod = <&usb_ctrl_mod>; +- #phy-cells = <0>; +- }; +- }; +- +- prcm: prcm@180000 { +- compatible = "ti,dm814-prcm", "simple-bus"; +- reg = <0x180000 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x180000 0x2000>; +- +- prcm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- prcm_clockdomains: clockdomains { +- }; +- }; +- +- /* See TRM PLL_SUBSYS_BASE and "PLLSS Registers" */ +- pllss: pllss@1c5000 { +- compatible = "ti,dm814-pllss", "simple-bus"; +- reg = <0x1c5000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1c5000 0x1000>; +- +- pllss_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- pllss_clockdomains: clockdomains { +- }; +- }; +- +- wdt1: wdt@1c7000 { +- compatible = "ti,omap3-wdt"; +- ti,hwmods = "wd_timer"; +- reg = <0x1c7000 0x1000>; +- interrupts = <91>; +- }; +- }; +- +- intc: interrupt-controller@48200000 { +- compatible = "ti,dm814-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x48200000 0x1000>; +- }; +- +- /* Board must configure evtmux with edma_xbar for EDMA */ +- mmc3: mmc@47810000 { +- compatible = "ti,omap4-hsmmc"; +- ti,hwmods = "mmc3"; +- interrupts = <29>; +- interrupt-parent = <&intc>; +- reg = <0x47810000 0x1000>; +- }; +- +- target-module@49000000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x49000000 0x4>; +- reg-names = "rev"; +- clocks = <&alwon_clkctrl DM814_TPCC_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49000000 0x10000>; +- +- edma: dma@0 { +- compatible = "ti,edma3-tpcc"; +- reg = <0 0x10000>; +- reg-names = "edma3_cc"; +- interrupts = <12 13 14>; +- interrupt-names = "edma3_ccint", "edma3_mperr", +- "edma3_ccerrint"; +- dma-requests = <64>; +- #dma-cells = <2>; +- +- ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, +- <&edma_tptc2 3>, <&edma_tptc3 0>; +- +- ti,edma-memcpy-channels = <20 21>; +- }; +- }; +- +- target-module@49800000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x49800000 0x4>, +- <0x49800010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = ; +- ti,sysc-sidle = , +- ; +- clocks = <&alwon_clkctrl DM814_TPTC0_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49800000 0x100000>; +- +- edma_tptc0: dma@0 { +- compatible = "ti,edma3-tptc"; +- reg = <0 0x100000>; +- interrupts = <112>; +- interrupt-names = "edma3_tcerrint"; +- }; +- }; +- +- target-module@49900000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x49900000 0x4>, +- <0x49900010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = ; +- ti,sysc-sidle = , +- ; +- clocks = <&alwon_clkctrl DM814_TPTC1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49900000 0x100000>; +- +- edma_tptc1: dma@0 { +- compatible = "ti,edma3-tptc"; +- reg = <0 0x100000>; +- interrupts = <113>; +- interrupt-names = "edma3_tcerrint"; +- }; +- }; +- +- target-module@49a00000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x49a00000 0x4>, +- <0x49a00010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = ; +- ti,sysc-sidle = , +- ; +- clocks = <&alwon_clkctrl DM814_TPTC2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49a00000 0x100000>; +- +- edma_tptc2: dma@0 { +- compatible = "ti,edma3-tptc"; +- reg = <0 0x100000>; +- interrupts = <114>; +- interrupt-names = "edma3_tcerrint"; +- }; +- }; +- +- target-module@49b00000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x49b00000 0x4>, +- <0x49b00010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = ; +- ti,sysc-sidle = , +- ; +- clocks = <&alwon_clkctrl DM814_TPTC3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49b00000 0x100000>; +- +- edma_tptc3: dma@0 { +- compatible = "ti,edma3-tptc"; +- reg = <0 0x100000>; +- interrupts = <115>; +- interrupt-names = "edma3_tcerrint"; +- }; +- }; +- +- /* See TRM "Table 1-318. L4HS Instance Summary" */ +- l4hs: l4hs@4a000000 { +- compatible = "ti,dm814-l4hs", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x4a000000 0x1b4040>; +- +- target-module@100000 { +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- reg = <0x100900 0x4>, +- <0x100908 0x4>, +- <0x100904 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <0>; +- ti,sysc-midle = , +- ; +- ti,sysc-sidle = , +- ; +- ti,syss-mask = <1>; +- clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x100000 0x8000>; +- +- mac: ethernet@0 { +- compatible = "ti,cpsw"; +- clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; +- clock-names = "fck", "cpts"; +- cpdma_channels = <8>; +- ale_entries = <1024>; +- bd_ram_size = <0x2000>; +- mac_control = <0x20>; +- slaves = <2>; +- active_slave = <0>; +- cpts_clock_mult = <0x80000000>; +- cpts_clock_shift = <29>; +- reg = <0 0x800>, +- <0x900 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * c0_rx_thresh_pend +- * c0_rx_pend +- * c0_tx_pend +- * c0_misc_pend +- */ +- interrupts = <40 41 42 43>; +- ranges = <0 0 0x8000>; +- syscon = <&scm_conf>; +- +- davinci_mdio: mdio@800 { +- compatible = "ti,cpsw-mdio", "ti,davinci_mdio"; +- clocks = <&cpsw_125mhz_gclk>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <0>; +- bus_freq = <1000000>; +- reg = <0x800 0x100>; +- }; +- +- cpsw_emac0: slave@200 { +- /* Filled in by U-Boot */ +- mac-address = [ 00 00 00 00 00 00 ]; +- phys = <&phy_gmii_sel 1>; +- }; +- +- cpsw_emac1: slave@300 { +- /* Filled in by U-Boot */ +- mac-address = [ 00 00 00 00 00 00 ]; +- phys = <&phy_gmii_sel 2>; +- }; +- }; +- }; +- }; +- +- gpmc: gpmc@50000000 { +- compatible = "ti,am3352-gpmc"; +- ti,hwmods = "gpmc"; +- ti,no-idle-on-init; +- reg = <0x50000000 0x2000>; +- interrupts = <100>; +- gpmc,num-cs = <7>; +- gpmc,num-waitpins = <2>; +- #address-cells = <2>; +- #size-cells = <1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +-}; +- +-#include "dm814x-clocks.dtsi" +- +-/* Preferred always-on timer for clocksource */ +-&timer1_target { +- ti,no-reset-on-init; +- ti,no-idle; +- timer@0 { +- assigned-clocks = <&timer1_fck>; +- assigned-clock-parents = <&devosc_ck>; +- }; +-}; +- +-/* Preferred timer for clockevent */ +-&timer2_target { +- ti,no-reset-on-init; +- ti,no-idle; +- timer@0 { +- assigned-clocks = <&timer2_fck>; +- assigned-clock-parents = <&devosc_ck>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dm8168-evm.dts b/scripts/dtc/include-prefixes/arm/dm8168-evm.dts +deleted file mode 100644 +index 5126e2d72ed7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dm8168-evm.dts ++++ /dev/null +@@ -1,213 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/dts-v1/; +- +-#include "dm816x.dtsi" +-#include +- +-/ { +- model = "DM8168 EVM"; +- compatible = "ti,dm8168-evm", "ti,dm8168", "ti,dm816"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000 /* 1 GB */ +- 0xc0000000 0x40000000>; /* 1 GB */ +- }; +- +- /* FDC6331L controlled by SD_POW pin */ +- vmmcsd_fixed: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsd_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- sata_refclk: fixedclock0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- }; +-}; +- +-&dm816x_pinmux { +- mcspi1_pins: pinmux_mcspi1_pins { +- pinctrl-single,pins = < +- DM816X_IOPAD(0x0a94, MUX_MODE0) /* SPI_SCLK */ +- DM816X_IOPAD(0x0a98, MUX_MODE0) /* SPI_SCS0 */ +- DM816X_IOPAD(0x0aa8, MUX_MODE0) /* SPI_D0 */ +- DM816X_IOPAD(0x0aac, MUX_MODE0) /* SPI_D1 */ +- >; +- }; +- +- mmc_pins: pinmux_mmc_pins { +- pinctrl-single,pins = < +- DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */ +- DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */ +- DM816X_IOPAD(0x0a78, MUX_MODE0) /* SD_CMD */ +- DM816X_IOPAD(0x0a7C, MUX_MODE0) /* SD_DAT0 */ +- DM816X_IOPAD(0x0a80, MUX_MODE0) /* SD_DAT1 */ +- DM816X_IOPAD(0x0a84, MUX_MODE0) /* SD_DAT2 */ +- DM816X_IOPAD(0x0a88, MUX_MODE0) /* SD_DAT2 */ +- DM816X_IOPAD(0x0a8c, MUX_MODE2) /* GP1[7] */ +- DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */ +- >; +- }; +- +- usb0_pins: pinmux_usb0_pins { +- pinctrl-single,pins = < +- DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB0_DRVVBUS */ +- >; +- }; +- +- usb1_pins: pinmux_usb1_pins { +- pinctrl-single,pins = < +- DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */ +- >; +- }; +- +- nandflash_pins: nandflash_pins { +- pinctrl-single,pins = < +- DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0) /* PINCTRL207 GPMC_CS0*/ +- DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0) /* PINCTRL217 GPMC_ADV_ALE */ +- DM816X_IOPAD(0x0b54, PULL_UP | PULL_ENA | MUX_MODE0) /* PINCTRL214 GPMC_OE_RE */ +- DM816X_IOPAD(0x0b58, PULL_ENA | MUX_MODE0) /* PINCTRL215 GPMC_BE0_CLE */ +- DM816X_IOPAD(0x0b50, PULL_UP | MUX_MODE0) /* PINCTRL213 GPMC_WE */ +- DM816X_IOPAD(0x0b6c, MUX_MODE0) /* PINCTRL220 GPMC_WAIT */ +- DM816X_IOPAD(0x0be4, PULL_ENA | MUX_MODE0) /* PINCTRL250 GPMC_CLK */ +- DM816X_IOPAD(0x0ba4, MUX_MODE0) /* PINCTRL234 GPMC_D0 */ +- DM816X_IOPAD(0x0ba8, MUX_MODE0) /* PINCTRL234 GPMC_D1 */ +- DM816X_IOPAD(0x0bac, MUX_MODE0) /* PINCTRL234 GPMC_D2 */ +- DM816X_IOPAD(0x0bb0, MUX_MODE0) /* PINCTRL234 GPMC_D3 */ +- DM816X_IOPAD(0x0bb4, MUX_MODE0) /* PINCTRL234 GPMC_D4 */ +- DM816X_IOPAD(0x0bb8, MUX_MODE0) /* PINCTRL234 GPMC_D5 */ +- DM816X_IOPAD(0x0bbc, MUX_MODE0) /* PINCTRL234 GPMC_D6 */ +- DM816X_IOPAD(0x0bc0, MUX_MODE0) /* PINCTRL234 GPMC_D7 */ +- DM816X_IOPAD(0x0bc4, MUX_MODE0) /* PINCTRL234 GPMC_D8 */ +- DM816X_IOPAD(0x0bc8, MUX_MODE0) /* PINCTRL234 GPMC_D9 */ +- DM816X_IOPAD(0x0bcc, MUX_MODE0) /* PINCTRL234 GPMC_D10 */ +- DM816X_IOPAD(0x0bd0, MUX_MODE0) /* PINCTRL234 GPMC_D11 */ +- DM816X_IOPAD(0x0bd4, MUX_MODE0) /* PINCTRL234 GPMC_D12 */ +- DM816X_IOPAD(0x0bd8, MUX_MODE0) /* PINCTRL234 GPMC_D13 */ +- DM816X_IOPAD(0x0bdc, MUX_MODE0) /* PINCTRL234 GPMC_D14 */ +- DM816X_IOPAD(0x0be0, MUX_MODE0) /* PINCTRL234 GPMC_D15 */ +- >; +- }; +-}; +- +-&i2c1 { +- extgpio0: pcf8575@20 { +- compatible = "nxp,pcf8575"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&i2c2 { +- extgpio1: pcf8575@20 { +- compatible = "nxp,pcf8575"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&gpmc { +- ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ +- pinctrl-names = "default"; +- pinctrl-0 = <&nandflash_pins>; +- +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- linux,mtd-name= "micron,mt29f2g16aadwp"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ +- #address-cells = <1>; +- #size-cells = <1>; +- ti,nand-ecc-opt = "bch8"; +- ti,elm-id = <&elm>; +- nand-bus-width = <16>; +- gpmc,device-width = <2>; +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-on-ns = <0>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- partition@0 { +- label = "X-Loader"; +- reg = <0 0x80000>; +- }; +- partition@80000 { +- label = "U-Boot"; +- reg = <0x80000 0x1c0000>; +- }; +- partition@1c0000 { +- label = "Environment"; +- reg = <0x240000 0x40000>; +- }; +- partition@280000 { +- label = "Kernel"; +- reg = <0x280000 0x500000>; +- }; +- partition@780000 { +- label = "Filesystem"; +- reg = <0x780000 0xf880000>; +- }; +- }; +-}; +- +-&mcspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcspi1_pins>; +- +- m25p80@0 { +- compatible = "w25x32"; +- spi-max-frequency = <48000000>; +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc_pins>; +- vmmc-supply = <&vmmcsd_fixed>; +- bus-width = <4>; +- cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; +-}; +- +-/* At least dm8168-evm rev c won't support multipoint, later may */ +-&usb0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb0_pins>; +- mentor,multipoint = <0>; +-}; +- +-&usb1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb1_pins>; +- mentor,multipoint = <0>; +-}; +- +-&sata { +- clocks = <&sysclk5_ck>, <&sata_refclk>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dm816x-clocks.dtsi b/scripts/dtc/include-prefixes/arm/dm816x-clocks.dtsi +deleted file mode 100644 +index 338449b32a18..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dm816x-clocks.dtsi ++++ /dev/null +@@ -1,276 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +- +-&scrm { +- main_fapll: main_fapll { +- #clock-cells = <1>; +- compatible = "ti,dm816-fapll-clock"; +- reg = <0x400 0x40>; +- clocks = <&sys_clkin_ck &sys_clkin_ck>; +- clock-indices = <1>, <2>, <3>, <4>, <5>, +- <6>, <7>; +- clock-output-names = "main_pll_clk1", +- "main_pll_clk2", +- "main_pll_clk3", +- "main_pll_clk4", +- "main_pll_clk5", +- "main_pll_clk6", +- "main_pll_clk7"; +- }; +- +- ddr_fapll: ddr_fapll { +- #clock-cells = <1>; +- compatible = "ti,dm816-fapll-clock"; +- reg = <0x440 0x30>; +- clocks = <&sys_clkin_ck &sys_clkin_ck>; +- clock-indices = <1>, <2>, <3>, <4>; +- clock-output-names = "ddr_pll_clk1", +- "ddr_pll_clk2", +- "ddr_pll_clk3", +- "ddr_pll_clk4"; +- }; +- +- video_fapll: video_fapll { +- #clock-cells = <1>; +- compatible = "ti,dm816-fapll-clock"; +- reg = <0x470 0x30>; +- clocks = <&sys_clkin_ck &sys_clkin_ck>; +- clock-indices = <1>, <2>, <3>; +- clock-output-names = "video_pll_clk1", +- "video_pll_clk2", +- "video_pll_clk3"; +- }; +- +- audio_fapll: audio_fapll { +- #clock-cells = <1>; +- compatible = "ti,dm816-fapll-clock"; +- reg = <0x4a0 0x30>; +- clocks = <&main_fapll 7>, < &sys_clkin_ck>; +- clock-indices = <1>, <2>, <3>, <4>, <5>; +- clock-output-names = "audio_pll_clk1", +- "audio_pll_clk2", +- "audio_pll_clk3", +- "audio_pll_clk4", +- "audio_pll_clk5"; +- }; +-}; +- +-&scrm_clocks { +- secure_32k_ck: secure_32k_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- sys_32k_ck: sys_32k_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- tclkin_ck: tclkin_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- sys_clkin_ck: sys_clkin_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <27000000>; +- }; +-}; +- +-/* 0x48180000 */ +-&prcm_clocks { +- clkout_pre_ck: clkout_pre_ck@100 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1 +- &audio_fapll 1>; +- reg = <0x100>; +- }; +- +- clkout_div_ck: clkout_div_ck@100 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&clkout_pre_ck>; +- ti,bit-shift = <3>; +- ti,max-div = <8>; +- reg = <0x100>; +- }; +- +- clkout_ck: clkout_ck@100 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&clkout_div_ck>; +- ti,bit-shift = <7>; +- reg = <0x100>; +- }; +- +- /* CM_DPLL clocks p1795 */ +- sysclk1_ck: sysclk1_ck@300 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&main_fapll 1>; +- ti,max-div = <7>; +- reg = <0x0300>; +- }; +- +- sysclk2_ck: sysclk2_ck@304 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&main_fapll 2>; +- ti,max-div = <7>; +- reg = <0x0304>; +- }; +- +- sysclk3_ck: sysclk3_ck@308 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&main_fapll 3>; +- ti,max-div = <7>; +- reg = <0x0308>; +- }; +- +- sysclk4_ck: sysclk4_ck@30c { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&main_fapll 4>; +- ti,max-div = <1>; +- reg = <0x030c>; +- }; +- +- sysclk5_ck: sysclk5_ck@310 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&sysclk4_ck>; +- ti,max-div = <1>; +- reg = <0x0310>; +- }; +- +- sysclk6_ck: sysclk6_ck@314 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&main_fapll 4>; +- ti,dividers = <2>, <4>; +- reg = <0x0314>; +- }; +- +- sysclk10_ck: sysclk10_ck@324 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&ddr_fapll 2>; +- ti,max-div = <7>; +- reg = <0x0324>; +- }; +- +- sysclk24_ck: sysclk24_ck@3b4 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&main_fapll 5>; +- ti,max-div = <7>; +- reg = <0x03b4>; +- }; +- +- mpu_ck: mpu_ck@15dc { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&sysclk2_ck>; +- ti,bit-shift = <1>; +- reg = <0x15dc>; +- }; +- +- audio_pll_a_ck: audio_pll_a_ck@35c { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&audio_fapll 1>; +- ti,max-div = <7>; +- reg = <0x035c>; +- }; +- +- sysclk18_ck: sysclk18_ck@378 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_32k_ck>, <&audio_pll_a_ck>; +- reg = <0x0378>; +- }; +- +- timer1_fck: timer1_fck@390 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; +- reg = <0x0390>; +- }; +- +- timer2_fck: timer2_fck@394 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; +- reg = <0x0394>; +- }; +- +- timer3_fck: timer3_fck@398 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; +- reg = <0x0398>; +- }; +- +- timer4_fck: timer4_fck@39c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; +- reg = <0x039c>; +- }; +- +- timer5_fck: timer5_fck@3a0 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; +- reg = <0x03a0>; +- }; +- +- timer6_fck: timer6_fck@3a4 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; +- reg = <0x03a4>; +- }; +- +- timer7_fck: timer7_fck@3a8 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; +- reg = <0x03a8>; +- }; +-}; +- +-&prcm { +- default_cm: default_cm@500 { +- compatible = "ti,omap4-cm"; +- reg = <0x500 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x500 0x100>; +- +- default_clkctrl: clk@0 { +- compatible = "ti,clkctrl"; +- reg = <0x0 0x5c>; +- #clock-cells = <2>; +- }; +- }; +- +- alwon_cm: alwon_cm@1400 { +- compatible = "ti,omap4-cm"; +- reg = <0x1400 0x300>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1400 0x300>; +- +- alwon_clkctrl: clk@0 { +- compatible = "ti,clkctrl"; +- reg = <0x0 0x208>; +- #clock-cells = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dm816x.dtsi b/scripts/dtc/include-prefixes/arm/dm816x.dtsi +deleted file mode 100644 +index a9e7274806f4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dm816x.dtsi ++++ /dev/null +@@ -1,692 +0,0 @@ +-/* +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "ti,dm816"; +- interrupt-parent = <&intc>; +- #address-cells = <1>; +- #size-cells = <1>; +- chosen { }; +- +- aliases { +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- ethernet0 = ð0; +- ethernet1 = ð1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- compatible = "arm,cortex-a8"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a8-pmu"; +- interrupts = <3>; +- }; +- +- /* +- * The soc node represents the soc top level view. It is used for IPs +- * that are not memory mapped in the MPU view or for the MPU itself. +- */ +- soc { +- compatible = "ti,omap-infra"; +- mpu { +- compatible = "ti,omap3-mpu"; +- ti,hwmods = "mpu"; +- }; +- }; +- +- /* +- * XXX: Use a flat representation of the dm816x interconnect. +- * The real dm816x interconnect network is quite complex. Since +- * it will not bring real advantage to represent that in DT +- * for the moment, just use a fake OCP bus entry to represent +- * the whole bus hierarchy. +- */ +- ocp { +- compatible = "simple-bus"; +- reg = <0x44000000 0x10000>; +- interrupts = <9 10>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- prcm: prcm@48180000 { +- compatible = "ti,dm816-prcm", "simple-bus"; +- reg = <0x48180000 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x48180000 0x4000>; +- +- prcm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- prcm_clockdomains: clockdomains { +- }; +- }; +- +- scrm: scrm@48140000 { +- compatible = "ti,dm816-scrm", "simple-bus"; +- reg = <0x48140000 0x21000>; +- #address-cells = <1>; +- #size-cells = <1>; +- #pinctrl-cells = <1>; +- ranges = <0 0x48140000 0x21000>; +- +- dm816x_pinmux: pinmux@800 { +- compatible = "pinctrl-single"; +- reg = <0x800 0x50a>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <16>; +- pinctrl-single,function-mask = <0xf>; +- }; +- +- /* Device Configuration Registers */ +- scm_conf: syscon@600 { +- compatible = "syscon", "simple-bus"; +- reg = <0x600 0x110>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x600 0x110>; +- +- usb_phy0: usb-phy@20 { +- compatible = "ti,dm8168-usb-phy"; +- reg = <0x20 0x8>; +- reg-names = "phy"; +- clocks = <&main_fapll 6>; +- clock-names = "refclk"; +- #phy-cells = <0>; +- syscon = <&scm_conf>; +- }; +- +- usb_phy1: usb-phy@28 { +- compatible = "ti,dm8168-usb-phy"; +- reg = <0x28 0x8>; +- reg-names = "phy"; +- clocks = <&main_fapll 6>; +- clock-names = "refclk"; +- #phy-cells = <0>; +- syscon = <&scm_conf>; +- }; +- }; +- +- scrm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- scrm_clockdomains: clockdomains { +- }; +- }; +- +- target-module@49000000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x49000000 0x4>; +- reg-names = "rev"; +- clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49000000 0x10000>; +- +- edma: dma@0 { +- compatible = "ti,edma3-tpcc"; +- reg = <0 0x10000>; +- reg-names = "edma3_cc"; +- interrupts = <12 13 14>; +- interrupt-names = "edma3_ccint", "edma3_mperr", +- "edma3_ccerrint"; +- dma-requests = <64>; +- #dma-cells = <2>; +- +- ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, +- <&edma_tptc2 3>, <&edma_tptc3 0>; +- +- ti,edma-memcpy-channels = <20 21>; +- }; +- }; +- +- target-module@49800000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x49800000 0x4>, +- <0x49800010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = ; +- ti,sysc-sidle = , +- ; +- clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49800000 0x100000>; +- +- edma_tptc0: dma@0 { +- compatible = "ti,edma3-tptc"; +- reg = <0 0x100000>; +- interrupts = <112>; +- interrupt-names = "edma3_tcerrint"; +- }; +- }; +- +- target-module@49900000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x49900000 0x4>, +- <0x49900010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = ; +- ti,sysc-sidle = , +- ; +- clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49900000 0x100000>; +- +- edma_tptc1: dma@0 { +- compatible = "ti,edma3-tptc"; +- reg = <0 0x100000>; +- interrupts = <113>; +- interrupt-names = "edma3_tcerrint"; +- }; +- }; +- +- target-module@49a00000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x49a00000 0x4>, +- <0x49a00010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = ; +- ti,sysc-sidle = , +- ; +- clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49a00000 0x100000>; +- +- edma_tptc2: dma@0 { +- compatible = "ti,edma3-tptc"; +- reg = <0 0x100000>; +- interrupts = <114>; +- interrupt-names = "edma3_tcerrint"; +- }; +- }; +- +- target-module@49b00000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x49b00000 0x4>, +- <0x49b00010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = ; +- ti,sysc-sidle = , +- ; +- clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49b00000 0x100000>; +- +- edma_tptc3: dma@0 { +- compatible = "ti,edma3-tptc"; +- reg = <0 0x100000>; +- interrupts = <115>; +- interrupt-names = "edma3_tcerrint"; +- }; +- }; +- +- elm: elm@48080000 { +- compatible = "ti,am3352-elm"; +- ti,hwmods = "elm"; +- reg = <0x48080000 0x2000>; +- interrupts = <4>; +- }; +- +- gpio1: gpio@48032000 { +- compatible = "ti,omap4-gpio"; +- ti,hwmods = "gpio1"; +- ti,gpio-always-on; +- reg = <0x48032000 0x1000>; +- interrupts = <96>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@4804c000 { +- compatible = "ti,omap4-gpio"; +- ti,hwmods = "gpio2"; +- ti,gpio-always-on; +- reg = <0x4804c000 0x1000>; +- interrupts = <98>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpmc: gpmc@50000000 { +- compatible = "ti,am3352-gpmc"; +- ti,hwmods = "gpmc"; +- reg = <0x50000000 0x2000>; +- #address-cells = <2>; +- #size-cells = <1>; +- interrupts = <100>; +- dmas = <&edma 52 0>; +- dma-names = "rxtx"; +- gpmc,num-cs = <6>; +- gpmc,num-waitpins = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- i2c1: i2c@48028000 { +- compatible = "ti,omap4-i2c"; +- ti,hwmods = "i2c1"; +- reg = <0x48028000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <70>; +- }; +- +- i2c2: i2c@4802a000 { +- compatible = "ti,omap4-i2c"; +- ti,hwmods = "i2c2"; +- reg = <0x4802a000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <71>; +- }; +- +- intc: interrupt-controller@48200000 { +- compatible = "ti,dm816-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x48200000 0x1000>; +- }; +- +- rtc: rtc@480c0000 { +- compatible = "ti,am3352-rtc", "ti,da830-rtc"; +- reg = <0x480c0000 0x1000>; +- interrupts = <75 76>; +- ti,hwmods = "rtc"; +- }; +- +- mailbox: mailbox@480c8000 { +- compatible = "ti,omap4-mailbox"; +- reg = <0x480c8000 0x2000>; +- interrupts = <77>; +- ti,hwmods = "mailbox"; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <12>; +- mbox_dsp: mbox-dsp { +- ti,mbox-tx = <3 0 0>; +- ti,mbox-rx = <0 0 0>; +- }; +- }; +- +- spinbox: spinbox@480ca000 { +- compatible = "ti,omap4-hwspinlock"; +- reg = <0x480ca000 0x2000>; +- ti,hwmods = "spinbox"; +- #hwlock-cells = <1>; +- }; +- +- mdio: mdio@4a100800 { +- compatible = "ti,davinci_mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x4a100800 0x100>; +- ti,hwmods = "davinci_mdio"; +- bus_freq = <1000000>; +- phy0: ethernet-phy@0 { +- reg = <1>; +- }; +- phy1: ethernet-phy@1 { +- reg = <2>; +- }; +- }; +- +- eth0: ethernet@4a100000 { +- compatible = "ti,dm816-emac"; +- ti,hwmods = "emac0"; +- reg = <0x4a100000 0x800 +- 0x4a100900 0x3700>; +- clocks = <&sysclk24_ck>; +- syscon = <&scm_conf>; +- ti,davinci-ctrl-reg-offset = <0>; +- ti,davinci-ctrl-mod-reg-offset = <0x900>; +- ti,davinci-ctrl-ram-offset = <0x2000>; +- ti,davinci-ctrl-ram-size = <0x2000>; +- interrupts = <40 41 42 43>; +- phy-handle = <&phy0>; +- }; +- +- eth1: ethernet@4a120000 { +- compatible = "ti,dm816-emac"; +- ti,hwmods = "emac1"; +- reg = <0x4a120000 0x4000>; +- clocks = <&sysclk24_ck>; +- syscon = <&scm_conf>; +- ti,davinci-ctrl-reg-offset = <0>; +- ti,davinci-ctrl-mod-reg-offset = <0x900>; +- ti,davinci-ctrl-ram-offset = <0x2000>; +- ti,davinci-ctrl-ram-size = <0x2000>; +- interrupts = <44 45 46 47>; +- phy-handle = <&phy1>; +- }; +- +- sata: sata@4a140000 { +- compatible = "ti,dm816-ahci"; +- reg = <0x4a140000 0x10000>; +- interrupts = <16>; +- ti,hwmods = "sata"; +- }; +- +- mcspi1: spi@48030000 { +- compatible = "ti,omap4-mcspi"; +- reg = <0x48030000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <65>; +- ti,spi-num-cs = <4>; +- ti,hwmods = "mcspi1"; +- dmas = <&edma 16 0 &edma 17 0 +- &edma 18 0 &edma 19 0 +- &edma 20 0 &edma 21 0 +- &edma 22 0 &edma 23 0>; +- dma-names = "tx0", "rx0", "tx1", "rx1", +- "tx2", "rx2", "tx3", "rx3"; +- }; +- +- mmc1: mmc@48060000 { +- compatible = "ti,omap4-hsmmc"; +- reg = <0x48060000 0x11000>; +- ti,hwmods = "mmc1"; +- interrupts = <64>; +- dmas = <&edma 24 0 &edma 25 0>; +- dma-names = "tx", "rx"; +- }; +- +- timer1_target: target-module@4802e000 { +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x4802e000 0x4>, +- <0x4802e010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4802e000 0x1000>; +- +- timer1: timer@0 { +- compatible = "ti,dm816-timer"; +- reg = <0 0x1000>; +- interrupts = <67>; +- ti,timer-alwon; +- clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>; +- clock-names = "fck"; +- }; +- }; +- +- timer2_target: target-module@48040000 { +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x48040000 0x4>, +- <0x48040010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x48040000 0x1000>; +- +- timer2: timer@0 { +- compatible = "ti,dm816-timer"; +- reg = <0 0x1000>; +- interrupts = <68>; +- clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>; +- clock-names = "fck"; +- }; +- }; +- +- timer3: timer@48042000 { +- compatible = "ti,dm816-timer"; +- reg = <0x48042000 0x2000>; +- interrupts = <69>; +- ti,hwmods = "timer3"; +- }; +- +- timer4: timer@48044000 { +- compatible = "ti,dm816-timer"; +- reg = <0x48044000 0x2000>; +- interrupts = <92>; +- ti,hwmods = "timer4"; +- ti,timer-pwm; +- }; +- +- timer5: timer@48046000 { +- compatible = "ti,dm816-timer"; +- reg = <0x48046000 0x2000>; +- interrupts = <93>; +- ti,hwmods = "timer5"; +- ti,timer-pwm; +- }; +- +- timer6: timer@48048000 { +- compatible = "ti,dm816-timer"; +- reg = <0x48048000 0x2000>; +- interrupts = <94>; +- ti,hwmods = "timer6"; +- ti,timer-pwm; +- }; +- +- timer7: timer@4804a000 { +- compatible = "ti,dm816-timer"; +- reg = <0x4804a000 0x2000>; +- interrupts = <95>; +- ti,hwmods = "timer7"; +- ti,timer-pwm; +- }; +- +- uart1: uart@48020000 { +- compatible = "ti,am3352-uart", "ti,omap3-uart"; +- ti,hwmods = "uart1"; +- reg = <0x48020000 0x2000>; +- clock-frequency = <48000000>; +- interrupts = <72>; +- dmas = <&edma 26 0 &edma 27 0>; +- dma-names = "tx", "rx"; +- }; +- +- uart2: uart@48022000 { +- compatible = "ti,am3352-uart", "ti,omap3-uart"; +- ti,hwmods = "uart2"; +- reg = <0x48022000 0x2000>; +- clock-frequency = <48000000>; +- interrupts = <73>; +- dmas = <&edma 28 0 &edma 29 0>; +- dma-names = "tx", "rx"; +- }; +- +- uart3: uart@48024000 { +- compatible = "ti,am3352-uart", "ti,omap3-uart"; +- ti,hwmods = "uart3"; +- reg = <0x48024000 0x2000>; +- clock-frequency = <48000000>; +- interrupts = <74>; +- dmas = <&edma 30 0 &edma 31 0>; +- dma-names = "tx", "rx"; +- }; +- +- /* NOTE: USB needs a transceiver driver for phys to work */ +- usb: usb_otg_hs@47401000 { +- compatible = "ti,am33xx-usb"; +- reg = <0x47401000 0x400000>; +- ranges; +- #address-cells = <1>; +- #size-cells = <1>; +- ti,hwmods = "usb_otg_hs"; +- +- usb0: usb@47401000 { +- compatible = "ti,musb-dm816"; +- reg = <0x47401400 0x400 +- 0x47401000 0x200>; +- reg-names = "mc", "control"; +- interrupts = <18>; +- interrupt-names = "mc"; +- dr_mode = "host"; +- interface-type = <0>; +- phys = <&usb_phy0>; +- phy-names = "usb2-phy"; +- mentor,multipoint = <1>; +- mentor,num-eps = <16>; +- mentor,ram-bits = <12>; +- mentor,power = <500>; +- +- dmas = <&cppi41dma 0 0 &cppi41dma 1 0 +- &cppi41dma 2 0 &cppi41dma 3 0 +- &cppi41dma 4 0 &cppi41dma 5 0 +- &cppi41dma 6 0 &cppi41dma 7 0 +- &cppi41dma 8 0 &cppi41dma 9 0 +- &cppi41dma 10 0 &cppi41dma 11 0 +- &cppi41dma 12 0 &cppi41dma 13 0 +- &cppi41dma 14 0 &cppi41dma 0 1 +- &cppi41dma 1 1 &cppi41dma 2 1 +- &cppi41dma 3 1 &cppi41dma 4 1 +- &cppi41dma 5 1 &cppi41dma 6 1 +- &cppi41dma 7 1 &cppi41dma 8 1 +- &cppi41dma 9 1 &cppi41dma 10 1 +- &cppi41dma 11 1 &cppi41dma 12 1 +- &cppi41dma 13 1 &cppi41dma 14 1>; +- dma-names = +- "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", +- "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", +- "rx14", "rx15", +- "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", +- "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", +- "tx14", "tx15"; +- }; +- +- usb1: usb@47401800 { +- compatible = "ti,musb-dm816"; +- reg = <0x47401c00 0x400 +- 0x47401800 0x200>; +- reg-names = "mc", "control"; +- interrupts = <19>; +- interrupt-names = "mc"; +- dr_mode = "host"; +- interface-type = <0>; +- phys = <&usb_phy1>; +- phy-names = "usb2-phy"; +- mentor,multipoint = <1>; +- mentor,num-eps = <16>; +- mentor,ram-bits = <12>; +- mentor,power = <500>; +- +- dmas = <&cppi41dma 15 0 &cppi41dma 16 0 +- &cppi41dma 17 0 &cppi41dma 18 0 +- &cppi41dma 19 0 &cppi41dma 20 0 +- &cppi41dma 21 0 &cppi41dma 22 0 +- &cppi41dma 23 0 &cppi41dma 24 0 +- &cppi41dma 25 0 &cppi41dma 26 0 +- &cppi41dma 27 0 &cppi41dma 28 0 +- &cppi41dma 29 0 &cppi41dma 15 1 +- &cppi41dma 16 1 &cppi41dma 17 1 +- &cppi41dma 18 1 &cppi41dma 19 1 +- &cppi41dma 20 1 &cppi41dma 21 1 +- &cppi41dma 22 1 &cppi41dma 23 1 +- &cppi41dma 24 1 &cppi41dma 25 1 +- &cppi41dma 26 1 &cppi41dma 27 1 +- &cppi41dma 28 1 &cppi41dma 29 1>; +- dma-names = +- "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", +- "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", +- "rx14", "rx15", +- "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", +- "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", +- "tx14", "tx15"; +- }; +- +- cppi41dma: dma-controller@47402000 { +- compatible = "ti,am3359-cppi41"; +- reg = <0x47400000 0x1000 +- 0x47402000 0x1000 +- 0x47403000 0x1000 +- 0x47404000 0x4000>; +- reg-names = "glue", "controller", "scheduler", "queuemgr"; +- interrupts = <17>; +- interrupt-names = "glue"; +- #dma-cells = <2>; +- #dma-channels = <30>; +- #dma-requests = <256>; +- }; +- }; +- +- wd_timer2: wd_timer@480c2000 { +- compatible = "ti,omap3-wdt"; +- ti,hwmods = "wd_timer"; +- reg = <0x480c2000 0x1000>; +- interrupts = <0>; +- }; +- }; +-}; +- +-#include "dm816x-clocks.dtsi" +- +-/* Preferred always-on timer for clocksource */ +-&timer1_target { +- ti,no-reset-on-init; +- ti,no-idle; +- timer@0 { +- assigned-clocks = <&timer1_fck>; +- assigned-clock-parents = <&sys_clkin_ck>; +- }; +-}; +- +-/* Preferred timer for clockevent */ +-&timer2_target { +- ti,no-reset-on-init; +- ti,no-idle; +- timer@0 { +- assigned-clocks = <&timer2_fck>; +- assigned-clock-parents = <&sys_clkin_ck>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dove-cm-a510.dtsi b/scripts/dtc/include-prefixes/arm/dove-cm-a510.dtsi +deleted file mode 100644 +index 9b9dfbe07be4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dove-cm-a510.dtsi ++++ /dev/null +@@ -1,195 +0,0 @@ +-/* +- * Device Tree include for Compulab CM-A510 System-on-Module +- * +- * Copyright (C) 2015, Sebastian Hesselbarth +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; version 2 of the +- * License. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/* +- * The CM-A510 comes with several optional components: +- * +- * Memory options: +- * D512: 512M +- * D1024: 1G +- * +- * NAND options: +- * N512: 512M NAND +- * +- * Ethernet options: +- * E1: PHY RTL8211D on internal GbE (SMI address 0x03) +- * E2: Additional ethernet NIC RTL8111D on PCIe1 +- * +- * Audio options: +- * A: TI TLV320AIC23b audio codec (I2C address 0x1a) +- * +- * Touchscreen options: +- * I: TI TSC2046 touchscreen controller (on SPI1) +- * +- * USB options: +- * U2: 2 dual-role USB2.0 ports +- * U4: 2 additional USB2.0 host ports (via USB1) +- * +- * WiFi options: +- * W: Broadcom BCM4319 802.11b/g/n (USI WM-N-BM-01 on SDIO1) +- * +- * GPIOs used on CM-A510: +- * 1 GbE PHY reset (active low) +- * 3 WakeUp +- * 8 PowerOff (active low) +- * 13 Touchscreen pen irq (active low) +- * 65 System LED (active high) +- * 69 USB Hub reset (active low) +- * 70 WLAN reset (active low) +- * 71 WLAN regulator (active high) +- */ +- +-#include "dove.dtsi" +- +-/ { +- model = "Compulab CM-A510"; +- compatible = "compulab,cm-a510", "marvell,dove"; +- +- /* +- * Set the minimum memory size here and let the +- * bootloader set the real size. +- */ +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- /* Set upper NAND data bit to GPO */ +- pinctrl-0 = <&pmx_nand_gpo>; +- pinctrl-names = "default"; +- +- system { +- label = "cm-a510:system:green"; +- gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- wifi_power: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "WiFi Power"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-/* Optional RTL8211D GbE PHY on SMI address 0x03 */ +-ðphy { +- reg = <3>; +- status = "disabled"; +-}; +- +-&i2c0 { +- /* Optional TI TLV320AIC23b audio codec */ +- opt_audio: audio@1a { +- compatible = "ti,tlv320aic23"; +- reg = <0x1a>; +- status = "disabled"; +- }; +-}; +- +-/* Optional RTL8111D GbE NIC on PCIe1 */ +-&pcie { status = "disabled"; }; +- +-&pcie1 { +- pinctrl-0 = <&pmx_pcie1_clkreq>; +- pinctrl-names = "default"; +- status = "disabled"; +-}; +- +-&pinctrl { +- pmx_uart2: pmx-uart2 { +- marvell,pins = "mpp14", "mpp15"; +- marvell,function = "uart2"; +- }; +-}; +- +-/* Optional Broadcom BCM4319 802.11b/g/n WiFi module */ +-&sdio1 { +- non-removable; +- vmmc-supply = <&wifi_power>; +- reset-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; +- status = "disabled"; +-}; +- +-&spi0 { +- status = "okay"; +- +- /* 1M Flash Winbond W25Q80BL */ +- flash@0 { +- compatible = "winbond,w25q80"; +- spi-max-frequency = <80000000>; +- reg = <0>; +- }; +-}; +- +-&spi1 { +- pinctrl-0 = <&pmx_spi1_20_23>; +- pinctrl-names = "default"; +- status = "disabled"; +- +- /* Optional TI TSC2046 touchscreen controller */ +- opt_touch: touchscreen@0 { +- compatible = "ti,tsc2046"; +- spi-max-frequency = <2500000>; +- reg = <0>; +- pinctrl-0 = <&pmx_gpio_13>; +- pinctrl-names = "default"; +- interrupts-extended = <&gpio0 13 IRQ_TYPE_EDGE_FALLING>; +- }; +-}; +- +-&uart2 { +- pinctrl-0 = <&pmx_uart2>; +- pinctrl-names = "default"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dove-cubox-es.dts b/scripts/dtc/include-prefixes/arm/dove-cubox-es.dts +deleted file mode 100644 +index ad361ec1361d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dove-cubox-es.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "dove-cubox.dts" +- +-/ { +- model = "SolidRun CuBox (Engineering Sample)"; +- compatible = "solidrun,cubox-es", "solidrun,cubox", "marvell,dove"; +-}; +- +-&sdio0 { +- /* sdio0 card detect is connected to wrong pin on CuBox ES */ +- cd-gpios = <&gpio0 12 1>; +- pinctrl-0 = <&pmx_sdio0 &pmx_gpio_12>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dove-cubox.dts b/scripts/dtc/include-prefixes/arm/dove-cubox.dts +deleted file mode 100644 +index 3e1584e787ae..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dove-cubox.dts ++++ /dev/null +@@ -1,143 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "dove.dtsi" +- +-/ { +- model = "SolidRun CuBox"; +- compatible = "solidrun,cubox", "marvell,dove"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x40000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_gpio_18>; +- pinctrl-names = "default"; +- +- power { +- label = "Power"; +- gpios = <&gpio0 18 1>; +- default-state = "keep"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- usb_power: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "USB Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 1 0>; +- pinctrl-0 = <&pmx_gpio_1>; +- pinctrl-names = "default"; +- }; +- }; +- +- clocks { +- /* 25MHz reference crystal */ +- ref25: oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- }; +- +- ir_recv: ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio0 19 1>; +- pinctrl-0 = <&pmx_gpio_19>; +- pinctrl-names = "default"; +- }; +- +- gpu-subsystem { +- status = "okay"; +- }; +-}; +- +-&uart0 { status = "okay"; }; +-&sata0 { status = "okay"; }; +-&mdio { status = "okay"; }; +-ð { status = "okay"; }; +- +-ðphy { +- compatible = "marvell,88e1310"; +- reg = <1>; +-}; +- +-&gpu { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <100000>; +- +- si5351: clock-generator@60 { +- compatible = "silabs,si5351a-msop"; +- reg = <0x60>; +- #address-cells = <1>; +- #size-cells = <0>; +- #clock-cells = <1>; +- +- /* connect xtal input to 25MHz reference */ +- clocks = <&ref25>; +- clock-names = "xtal"; +- +- /* connect xtal input as source of pll0 and pll1 */ +- silabs,pll-source = <0 0>, <1 0>; +- +- clkout0 { +- reg = <0>; +- silabs,drive-strength = <8>; +- silabs,multisynth-source = <0>; +- silabs,clock-source = <0>; +- silabs,pll-master; +- }; +- +- clkout2 { +- reg = <2>; +- silabs,drive-strength = <8>; +- silabs,multisynth-source = <1>; +- silabs,clock-source = <0>; +- silabs,pll-master; +- }; +- }; +-}; +- +-&sdio0 { +- status = "okay"; +-}; +- +-&spi0 { +- status = "okay"; +- +- /* spi0.0: 4M Flash Winbond W25Q32BV */ +- spi-flash@0 { +- compatible = "st,w25q32"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +- +-&audio1 { +- status = "okay"; +- clocks = <&gate_clk 13>, <&si5351 2>; +- clock-names = "internal", "extclk"; +- pinctrl-0 = <&pmx_audio1_i2s1_spdifo &pmx_audio1_extclk>; +- pinctrl-names = "default"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dove-d2plug.dts b/scripts/dtc/include-prefixes/arm/dove-d2plug.dts +deleted file mode 100644 +index 273f12ca2512..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dove-d2plug.dts ++++ /dev/null +@@ -1,70 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "dove.dtsi" +- +-/ { +- model = "Globalscale D2Plug"; +- compatible = "globalscale,d2plug", "marvell,dove"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x40000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>; +- pinctrl-names = "default"; +- +- wlan-ap { +- label = "wlan-ap"; +- gpios = <&gpio0 0 1>; +- }; +- +- wlan-act { +- label = "wlan-act"; +- gpios = <&gpio0 1 1>; +- }; +- +- bluetooth-act { +- label = "bt-act"; +- gpios = <&gpio0 2 1>; +- }; +- }; +-}; +- +-&uart0 { status = "okay"; }; +-&sata0 { status = "okay"; }; +-&i2c0 { status = "okay"; }; +-&mdio { status = "okay"; }; +-ð { status = "okay"; }; +- +-/* Samsung M8G2F eMMC */ +-&sdio0 { +- status = "okay"; +- non-removable; +- bus-width = <4>; +-}; +- +-/* Marvell SD8787 WLAN/BT */ +-&sdio1 { +- status = "okay"; +- non-removable; +- bus-width = <4>; +-}; +- +-&spi0 { +- status = "okay"; +- +- /* spi0.0: 4M Flash Macronix MX25L3205D */ +- spi-flash@0 { +- compatible = "st,m25l3205d"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dove-d3plug.dts b/scripts/dtc/include-prefixes/arm/dove-d3plug.dts +deleted file mode 100644 +index 826026c28f90..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dove-d3plug.dts ++++ /dev/null +@@ -1,104 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "dove.dtsi" +- +-/ { +- model = "Globalscale D3Plug"; +- compatible = "globalscale,d3plug", "marvell,dove"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x40000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p2 rw rootwait"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>; +- pinctrl-names = "default"; +- +- wlan-act { +- label = "wlan-act"; +- gpios = <&gpio0 0 1>; +- }; +- +- wlan-ap { +- label = "wlan-ap"; +- gpios = <&gpio0 1 1>; +- }; +- +- status { +- label = "status"; +- gpios = <&gpio0 2 1>; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- usb_power: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "USB Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 8 0>; +- pinctrl-0 = <&pmx_gpio_8>; +- pinctrl-names = "default"; +- }; +- }; +-}; +- +-&uart0 { status = "okay"; }; +-&sata0 { status = "okay"; }; +-&i2c0 { status = "okay"; }; +- +-/* Samsung M8G2F eMMC */ +-&sdio0 { +- status = "okay"; +- non-removable; +- bus-width = <4>; +-}; +- +-/* Marvell SD8787 WLAN/BT */ +-&sdio1 { +- status = "okay"; +- non-removable; +-}; +- +-&spi0 { +- status = "okay"; +- +- /* spi0.0: 2M Flash Macronix MX25L1605D */ +- spi-flash@0 { +- compatible = "st,m25l1605d"; +- spi-max-frequency = <86000000>; +- reg = <0>; +- }; +-}; +- +-&pcie { +- status = "okay"; +- /* Fresco Logic USB3.0 xHCI controller */ +- pcie@1 { +- status = "okay"; +- reset-gpios = <&gpio0 26 1>; +- reset-delay-us = <20000>; +- pinctrl-0 = <&pmx_camera_gpio>; +- pinctrl-names = "default"; +- }; +- /* Mini-PCIe slot */ +- pcie@2 { +- status = "okay"; +- reset-gpios = <&gpio0 25 1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dove-dove-db.dts b/scripts/dtc/include-prefixes/arm/dove-dove-db.dts +deleted file mode 100644 +index 1754a62e014e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dove-dove-db.dts ++++ /dev/null +@@ -1,39 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "dove.dtsi" +- +-/ { +- model = "Marvell DB-MV88AP510-BP Development Board"; +- compatible = "marvell,dove-db", "marvell,dove"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x40000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- }; +-}; +- +-&uart0 { status = "okay"; }; +-&uart1 { status = "okay"; }; +-&sdio0 { status = "okay"; }; +-&sdio1 { status = "okay"; }; +-&sata0 { status = "okay"; }; +- +-&spi0 { +- status = "okay"; +- +- /* spi0.0: 4M Flash ST-M25P32-VMF6P */ +- spi-flash@0 { +- compatible = "st,m25p32"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dove-sbc-a510.dts b/scripts/dtc/include-prefixes/arm/dove-sbc-a510.dts +deleted file mode 100644 +index df021f9b0117..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dove-sbc-a510.dts ++++ /dev/null +@@ -1,183 +0,0 @@ +-/* +- * Device Tree file for Compulab SBC-A510 Single Board Computer +- * +- * Copyright (C) 2015, Sebastian Hesselbarth +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; version 2 of the +- * License. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/* +- * SBC-A510 comprises a PCA9555 I2C GPIO expander its GPIO lines connected to +- * +- * 0.0 USB0 VBUS_EN (active high) +- * 0.1 USB0 VBUS_GOOD +- * 0.2 DVI transmitter TI TFP410 MSEN +- * 0.3 DVI transmitter TI TFP410 PD# (active low power down) +- * 0.4 LVDS transmitter DS90C365 PD# (active low power down) +- * 0.5 LCD nRST (active low reset) +- * 0.6 PCIe0 nRST (active low reset) +- * 0.7 mini-PCIe slot W_DISABLE# +- * +- * 1.0 MMC WP +- * 1.1 Camera Input FPC FLASH_STB and P21.5 +- * 1.2 Camera Input FPC WE and P21.22 +- * 1.3 MMC VCC_EN (active high) and P21.7 +- * 1.4 Camera Input FPC AFTR_RST and P21.17 +- * 1.5 Camera Input FPC OE and P21.19 +- * 1.6 Camera Input FPC SNPSHT and P21.6 +- * 1.7 Camera Input FPC SHTR and P21.10 +- */ +- +-/dts-v1/; +- +-#include "dove-cm-a510.dtsi" +- +-/ { +- model = "Compulab SBC-A510"; +- compatible = "compulab,sbc-a510", "compulab,cm-a510", "marvell,dove"; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- regulators { +- usb0_power: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "USB Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio_ext 0 GPIO_ACTIVE_HIGH>; +- }; +- +- mmc_power: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "MMC Power"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio_ext 13 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-/* Ethernet0 depends on CM-A510 option E1 */ +-&mdio { status = "disabled"; }; +-ð { status = "disabled"; }; +-ðphy { status = "disabled"; }; +- +-/* +- * USB port 0 can be powered and monitored by I2C GPIO expander: +- * VBUS_ENABLE on GPIO0, VBUS_GOOD on GPIO1 +- */ +-&ehci0 { +- status = "okay"; +- vbus-supply = <&usb0_power>; +-}; +- +-/* USB port 1 (and ports 2, 3 if CM-A510 has U4 option) */ +-&ehci1 { status = "okay"; }; +- +-/* +- * I2C bus layout: +- * i2c0: +- * - Audio Codec, 0x1a (option from CM-A510) +- * - DVI transmitter TI TFP410, 0x39 +- * - HDMI/DVI DDC channel +- * i2c1: +- * - GPIO expander, NXP PCA9555, 0x20 +- * - VGA DDC channel +- */ +-&i2c { +- pinctrl-0 = <&pmx_i2c1>; +- pinctrl-names = "default"; +-}; +- +-&i2c0 { +- /* TI TFP410 DVI transmitter */ +- dvi: video@39 { +- compatible = "ti,tfp410"; +- reg = <0x39>; +- powerdown-gpio = <&gpio_ext 3 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- /* NXP PCA9555 GPIO expander */ +- gpio_ext: gpio@20 { +- compatible = "nxp,pca9555"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&pcie { status = "okay"; }; +- +-/* +- * PCIe0 can be configured by Jumper E1 to be either connected to +- * a mini-PCIe slot or a Pericom PI7C9X111 PCIe-to-PCI bridge. +- */ +-&pcie0 { +- status = "okay"; +- pinctrl-0 = <&pmx_pcie0_clkreq>; +- pinctrl-names = "default"; +- reset-gpios = <&gpio_ext 6 GPIO_ACTIVE_LOW>; +-}; +- +-/* Ethernet1 depends on CM-A510 option E2 */ +-&pcie1 { status = "disabled"; }; +- +-/* SATA connector */ +-&sata0 { status = "okay"; }; +- +-/* +- * SDIO0 is connected to a MMC/SD/SDIO socket, I2C GPIO expander has +- * VCC_MMC_ENABLE on GPIO13, MMC_WP on GPIO10 +- */ +-&sdio0 { +- vmmc-supply = <&mmc_power>; +- wp-gpios = <&gpio_ext 10 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-/* UART0 on RS232 mini-connector */ +-&uart0 { status = "okay"; }; +-/* UART2 on pin headers */ +-&uart2 { status = "okay"; }; +diff --git a/scripts/dtc/include-prefixes/arm/dove.dtsi b/scripts/dtc/include-prefixes/arm/dove.dtsi +deleted file mode 100644 +index 89e0bdaf3a85..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dove.dtsi ++++ /dev/null +@@ -1,805 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +- +-#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "marvell,dove"; +- model = "Marvell Armada 88AP510 SoC"; +- interrupt-parent = <&intc>; +- +- aliases { +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- gpio2 = &gpio2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "marvell,pj4a", "marvell,sheeva-v7"; +- device_type = "cpu"; +- next-level-cache = <&l2>; +- reg = <0>; +- }; +- }; +- +- l2: l2-cache { +- compatible = "marvell,tauros2-cache"; +- marvell,tauros2-cache-features = <0>; +- }; +- +- gpu-subsystem { +- compatible = "marvell,dove-gpu-subsystem"; +- cores = <&gpu>; +- status = "disabled"; +- }; +- +- i2c-mux { +- compatible = "i2c-mux-pinctrl"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c-parent = <&i2c>; +- +- pinctrl-names = "i2c0", "i2c1", "i2c2"; +- pinctrl-0 = <&pmx_i2cmux_0>; +- pinctrl-1 = <&pmx_i2cmux_1>; +- pinctrl-2 = <&pmx_i2cmux_2>; +- +- i2c0: i2c@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- }; +- +- i2c1: i2c@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- /* Requires pmx_i2c1 on i2c controller node */ +- status = "disabled"; +- }; +- +- i2c2: i2c@2 { +- reg = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- /* Requires pmx_i2c2 on i2c controller node */ +- status = "disabled"; +- }; +- }; +- +- mbus { +- compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- controller = <&mbusc>; +- pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */ +- pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */ +- +- ranges = ; /* PMU SRAM 1M */ +- +- pcie: pcie { +- compatible = "marvell,dove-pcie"; +- status = "disabled"; +- device_type = "pci"; +- #address-cells = <3>; +- #size-cells = <2>; +- +- msi-parent = <&intc>; +- bus-range = <0x00 0xff>; +- +- ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000 +- 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000 +- 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */ +- 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */ +- 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ +- 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ +- +- pcie0: pcie@1 { +- device_type = "pci"; +- status = "disabled"; +- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; +- reg = <0x0800 0 0 0 0>; +- clocks = <&gate_clk 4>; +- marvell,pcie-port = <0>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 +- 0x81000000 0 0 0x81000000 0x1 0 1 0>; +- bus-range = <0x00 0xff>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &intc 16>; +- }; +- +- pcie1: pcie@2 { +- device_type = "pci"; +- status = "disabled"; +- assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; +- reg = <0x1000 0 0 0 0>; +- clocks = <&gate_clk 5>; +- marvell,pcie-port = <1>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 +- 0x81000000 0 0 0x81000000 0x2 0 1 0>; +- bus-range = <0x00 0xff>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &intc 18>; +- }; +- }; +- +- internal-regs { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */ +- 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */ +- 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */ +- 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */ +- +- spi0: spi@10600 { +- compatible = "marvell,orion-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- interrupts = <6>; +- reg = <0x10600 0x28>; +- clocks = <&core_clk 0>; +- pinctrl-0 = <&pmx_spi0>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- i2c: i2c@11000 { +- compatible = "marvell,mv64xxx-i2c"; +- reg = <0x11000 0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <11>; +- clock-frequency = <400000>; +- clocks = <&core_clk 0>; +- status = "okay"; +- }; +- +- uart0: serial@12000 { +- compatible = "ns16550a"; +- reg = <0x12000 0x100>; +- reg-shift = <2>; +- interrupts = <7>; +- clocks = <&core_clk 0>; +- status = "disabled"; +- }; +- +- uart1: serial@12100 { +- compatible = "ns16550a"; +- reg = <0x12100 0x100>; +- reg-shift = <2>; +- interrupts = <8>; +- clocks = <&core_clk 0>; +- pinctrl-0 = <&pmx_uart1>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- uart2: serial@12200 { +- compatible = "ns16550a"; +- reg = <0x12200 0x100>; +- reg-shift = <2>; +- interrupts = <9>; +- clocks = <&core_clk 0>; +- status = "disabled"; +- }; +- +- uart3: serial@12300 { +- compatible = "ns16550a"; +- reg = <0x12300 0x100>; +- reg-shift = <2>; +- interrupts = <10>; +- clocks = <&core_clk 0>; +- status = "disabled"; +- }; +- +- spi1: spi@14600 { +- compatible = "marvell,orion-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- interrupts = <5>; +- reg = <0x14600 0x28>; +- clocks = <&core_clk 0>; +- status = "disabled"; +- }; +- +- mbusc: mbus-ctrl@20000 { +- compatible = "marvell,mbus-controller"; +- reg = <0x20000 0x80>, <0x800100 0x8>; +- }; +- +- sysc: system-ctrl@20000 { +- compatible = "marvell,orion-system-controller"; +- reg = <0x20000 0x110>; +- }; +- +- bridge_intc: bridge-interrupt-ctrl@20110 { +- compatible = "marvell,orion-bridge-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x20110 0x8>; +- interrupts = <0>; +- marvell,#interrupts = <5>; +- }; +- +- intc: interrupt-controller@20200 { +- compatible = "marvell,orion-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x20200 0x10>, <0x20210 0x10>; +- }; +- +- timer: timer@20300 { +- compatible = "marvell,orion-timer"; +- reg = <0x20300 0x20>; +- interrupt-parent = <&bridge_intc>; +- interrupts = <1>, <2>; +- clocks = <&core_clk 0>; +- }; +- +- watchdog@20300 { +- compatible = "marvell,orion-wdt"; +- reg = <0x20300 0x28>, <0x20108 0x4>; +- interrupt-parent = <&bridge_intc>; +- interrupts = <3>; +- clocks = <&core_clk 0>; +- }; +- +- crypto: crypto-engine@30000 { +- compatible = "marvell,dove-crypto"; +- reg = <0x30000 0x10000>; +- reg-names = "regs"; +- interrupts = <31>; +- clocks = <&gate_clk 15>; +- marvell,crypto-srams = <&crypto_sram>; +- marvell,crypto-sram-size = <0x800>; +- status = "okay"; +- }; +- +- ehci0: usb-host@50000 { +- compatible = "marvell,orion-ehci"; +- reg = <0x50000 0x1000>; +- interrupts = <24>; +- clocks = <&gate_clk 0>; +- status = "okay"; +- }; +- +- ehci1: usb-host@51000 { +- compatible = "marvell,orion-ehci"; +- reg = <0x51000 0x1000>; +- interrupts = <25>; +- clocks = <&gate_clk 1>; +- status = "okay"; +- }; +- +- xor0: dma-engine@60800 { +- compatible = "marvell,orion-xor"; +- reg = <0x60800 0x100 +- 0x60a00 0x100>; +- clocks = <&gate_clk 23>; +- status = "okay"; +- +- channel0 { +- interrupts = <39>; +- dmacap,memcpy; +- dmacap,xor; +- }; +- +- channel1 { +- interrupts = <40>; +- dmacap,memcpy; +- dmacap,xor; +- }; +- }; +- +- xor1: dma-engine@60900 { +- compatible = "marvell,orion-xor"; +- reg = <0x60900 0x100 +- 0x60b00 0x100>; +- clocks = <&gate_clk 24>; +- status = "okay"; +- +- channel0 { +- interrupts = <42>; +- dmacap,memcpy; +- dmacap,xor; +- }; +- +- channel1 { +- interrupts = <43>; +- dmacap,memcpy; +- dmacap,xor; +- }; +- }; +- +- sdio1: sdio-host@90000 { +- compatible = "marvell,dove-sdhci"; +- reg = <0x90000 0x100>; +- interrupts = <36>, <38>; +- clocks = <&gate_clk 9>; +- pinctrl-0 = <&pmx_sdio1>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- eth: ethernet-ctrl@72000 { +- compatible = "marvell,orion-eth"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x72000 0x4000>; +- clocks = <&gate_clk 2>; +- marvell,tx-checksum-limit = <1600>; +- status = "disabled"; +- +- ethernet-port@0 { +- compatible = "marvell,orion-eth-port"; +- reg = <0>; +- interrupts = <29>; +- /* overwrite MAC address in bootloader */ +- local-mac-address = [00 00 00 00 00 00]; +- phy-handle = <ðphy>; +- }; +- }; +- +- mdio: mdio-bus@72004 { +- compatible = "marvell,orion-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x72004 0x84>; +- interrupts = <30>; +- clocks = <&gate_clk 2>; +- status = "disabled"; +- +- ethphy: ethernet-phy { +- /* set phy address in board file */ +- }; +- }; +- +- sdio0: sdio-host@92000 { +- compatible = "marvell,dove-sdhci"; +- reg = <0x92000 0x100>; +- interrupts = <35>, <37>; +- clocks = <&gate_clk 8>; +- pinctrl-0 = <&pmx_sdio0>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- sata0: sata-host@a0000 { +- compatible = "marvell,orion-sata"; +- reg = <0xa0000 0x2400>; +- interrupts = <62>; +- clocks = <&gate_clk 3>; +- phys = <&sata_phy0>; +- phy-names = "port0"; +- nr-ports = <1>; +- status = "disabled"; +- }; +- +- sata_phy0: sata-phy@a2000 { +- compatible = "marvell,mvebu-sata-phy"; +- reg = <0xa2000 0x0334>; +- clocks = <&gate_clk 3>; +- clock-names = "sata"; +- #phy-cells = <0>; +- status = "ok"; +- }; +- +- audio0: audio-controller@b0000 { +- compatible = "marvell,dove-audio"; +- reg = <0xb0000 0x2210>; +- interrupts = <19>, <20>; +- clocks = <&gate_clk 12>; +- clock-names = "internal"; +- status = "disabled"; +- }; +- +- audio1: audio-controller@b4000 { +- compatible = "marvell,dove-audio"; +- reg = <0xb4000 0x2210>; +- interrupts = <21>, <22>; +- clocks = <&gate_clk 13>; +- clock-names = "internal"; +- status = "disabled"; +- }; +- +- pmu: power-management@d0000 { +- compatible = "marvell,dove-pmu", "simple-bus"; +- reg = <0xd0000 0x8000>, <0xd8000 0x8000>; +- ranges = <0x00000000 0x000d0000 0x8000 +- 0x00008000 0x000d8000 0x8000>; +- interrupts = <33>; +- interrupt-controller; +- #address-cells = <1>; +- #size-cells = <1>; +- #interrupt-cells = <1>; +- #reset-cells = <1>; +- +- domains { +- vpu_domain: vpu-domain { +- #power-domain-cells = <0>; +- marvell,pmu_pwr_mask = <0x00000008>; +- marvell,pmu_iso_mask = <0x00000001>; +- resets = <&pmu 16>; +- }; +- +- gpu_domain: gpu-domain { +- #power-domain-cells = <0>; +- marvell,pmu_pwr_mask = <0x00000004>; +- marvell,pmu_iso_mask = <0x00000002>; +- resets = <&pmu 18>; +- }; +- }; +- +- thermal: thermal-diode@1c { +- compatible = "marvell,dove-thermal"; +- reg = <0x001c 0x0c>, <0x005c 0x08>; +- }; +- +- gate_clk: clock-gating-ctrl@38 { +- compatible = "marvell,dove-gating-clock"; +- reg = <0x0038 0x4>; +- clocks = <&core_clk 0>; +- #clock-cells = <1>; +- }; +- +- divider_clk: core-clock@64 { +- compatible = "marvell,dove-divider-clock"; +- reg = <0x0064 0x8>; +- #clock-cells = <1>; +- }; +- +- pinctrl: pin-ctrl@200 { +- compatible = "marvell,dove-pinctrl"; +- reg = <0x0200 0x14>, +- <0x0440 0x04>; +- clocks = <&gate_clk 22>; +- +- pmx_gpio_0: pmx-gpio-0 { +- marvell,pins = "mpp0"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_1: pmx-gpio-1 { +- marvell,pins = "mpp1"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_2: pmx-gpio-2 { +- marvell,pins = "mpp2"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_3: pmx-gpio-3 { +- marvell,pins = "mpp3"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_4: pmx-gpio-4 { +- marvell,pins = "mpp4"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_5: pmx-gpio-5 { +- marvell,pins = "mpp5"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_6: pmx-gpio-6 { +- marvell,pins = "mpp6"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_7: pmx-gpio-7 { +- marvell,pins = "mpp7"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_8: pmx-gpio-8 { +- marvell,pins = "mpp8"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_9: pmx-gpio-9 { +- marvell,pins = "mpp9"; +- marvell,function = "gpio"; +- }; +- +- pmx_pcie1_clkreq: pmx-pcie1-clkreq { +- marvell,pins = "mpp9"; +- marvell,function = "pex1"; +- }; +- +- pmx_gpio_10: pmx-gpio-10 { +- marvell,pins = "mpp10"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_11: pmx-gpio-11 { +- marvell,pins = "mpp11"; +- marvell,function = "gpio"; +- }; +- +- pmx_pcie0_clkreq: pmx-pcie0-clkreq { +- marvell,pins = "mpp11"; +- marvell,function = "pex0"; +- }; +- +- pmx_gpio_12: pmx-gpio-12 { +- marvell,pins = "mpp12"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_13: pmx-gpio-13 { +- marvell,pins = "mpp13"; +- marvell,function = "gpio"; +- }; +- +- pmx_audio1_extclk: pmx-audio1-extclk { +- marvell,pins = "mpp13"; +- marvell,function = "audio1"; +- }; +- +- pmx_gpio_14: pmx-gpio-14 { +- marvell,pins = "mpp14"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_15: pmx-gpio-15 { +- marvell,pins = "mpp15"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_16: pmx-gpio-16 { +- marvell,pins = "mpp16"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_17: pmx-gpio-17 { +- marvell,pins = "mpp17"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_18: pmx-gpio-18 { +- marvell,pins = "mpp18"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_19: pmx-gpio-19 { +- marvell,pins = "mpp19"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_20: pmx-gpio-20 { +- marvell,pins = "mpp20"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_21: pmx-gpio-21 { +- marvell,pins = "mpp21"; +- marvell,function = "gpio"; +- }; +- +- pmx_camera: pmx-camera { +- marvell,pins = "mpp_camera"; +- marvell,function = "camera"; +- }; +- +- pmx_camera_gpio: pmx-camera-gpio { +- marvell,pins = "mpp_camera"; +- marvell,function = "gpio"; +- }; +- +- pmx_sdio0: pmx-sdio0 { +- marvell,pins = "mpp_sdio0"; +- marvell,function = "sdio0"; +- }; +- +- pmx_sdio0_gpio: pmx-sdio0-gpio { +- marvell,pins = "mpp_sdio0"; +- marvell,function = "gpio"; +- }; +- +- pmx_sdio1: pmx-sdio1 { +- marvell,pins = "mpp_sdio1"; +- marvell,function = "sdio1"; +- }; +- +- pmx_sdio1_gpio: pmx-sdio1-gpio { +- marvell,pins = "mpp_sdio1"; +- marvell,function = "gpio"; +- }; +- +- pmx_audio1_gpio: pmx-audio1-gpio { +- marvell,pins = "mpp_audio1"; +- marvell,function = "gpio"; +- }; +- +- pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo { +- marvell,pins = "mpp_audio1"; +- marvell,function = "i2s1/spdifo"; +- }; +- +- pmx_spi0: pmx-spi0 { +- marvell,pins = "mpp_spi0"; +- marvell,function = "spi0"; +- }; +- +- pmx_spi0_gpio: pmx-spi0-gpio { +- marvell,pins = "mpp_spi0"; +- marvell,function = "gpio"; +- }; +- +- pmx_spi1_4_7: pmx-spi1-4-7 { +- marvell,pins = "mpp4", "mpp5", +- "mpp6", "mpp7"; +- marvell,function = "spi1"; +- }; +- +- pmx_spi1_20_23: pmx-spi1-20-23 { +- marvell,pins = "mpp20", "mpp21", +- "mpp22", "mpp23"; +- marvell,function = "spi1"; +- }; +- +- pmx_uart1: pmx-uart1 { +- marvell,pins = "mpp_uart1"; +- marvell,function = "uart1"; +- }; +- +- pmx_uart1_gpio: pmx-uart1-gpio { +- marvell,pins = "mpp_uart1"; +- marvell,function = "gpio"; +- }; +- +- pmx_nand: pmx-nand { +- marvell,pins = "mpp_nand"; +- marvell,function = "nand"; +- }; +- +- pmx_nand_gpo: pmx-nand-gpo { +- marvell,pins = "mpp_nand"; +- marvell,function = "gpo"; +- }; +- +- pmx_i2c1: pmx-i2c1 { +- marvell,pins = "mpp17", "mpp19"; +- marvell,function = "twsi"; +- }; +- +- pmx_i2c2: pmx-i2c2 { +- marvell,pins = "mpp_audio1"; +- marvell,function = "twsi"; +- }; +- +- pmx_ssp_i2c2: pmx-ssp-i2c2 { +- marvell,pins = "mpp_audio1"; +- marvell,function = "ssp/twsi"; +- }; +- +- pmx_i2cmux_0: pmx-i2cmux-0 { +- marvell,pins = "twsi"; +- marvell,function = "twsi-opt1"; +- }; +- +- pmx_i2cmux_1: pmx-i2cmux-1 { +- marvell,pins = "twsi"; +- marvell,function = "twsi-opt2"; +- }; +- +- pmx_i2cmux_2: pmx-i2cmux-2 { +- marvell,pins = "twsi"; +- marvell,function = "twsi-opt3"; +- }; +- }; +- +- core_clk: core-clocks@214 { +- compatible = "marvell,dove-core-clock"; +- reg = <0x0214 0x4>; +- #clock-cells = <1>; +- }; +- +- gpio0: gpio-ctrl@400 { +- compatible = "marvell,orion-gpio"; +- #gpio-cells = <2>; +- gpio-controller; +- reg = <0x0400 0x20>; +- ngpios = <32>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupt-parent = <&intc>; +- interrupts = <12>, <13>, <14>, <60>; +- }; +- +- gpio1: gpio-ctrl@420 { +- compatible = "marvell,orion-gpio"; +- #gpio-cells = <2>; +- gpio-controller; +- reg = <0x0420 0x20>; +- ngpios = <32>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupt-parent = <&intc>; +- interrupts = <61>; +- }; +- +- rtc: real-time-clock@8500 { +- compatible = "marvell,orion-rtc"; +- reg = <0x8500 0x20>; +- interrupts = <5>; +- }; +- }; +- +- gconf: global-config@e802c { +- compatible = "marvell,dove-global-config", +- "syscon"; +- reg = <0xe802c 0x14>; +- }; +- +- gpio2: gpio-ctrl@e8400 { +- compatible = "marvell,orion-gpio"; +- #gpio-cells = <2>; +- gpio-controller; +- reg = <0xe8400 0x0c>; +- ngpios = <8>; +- }; +- +- lcd1: lcd-controller@810000 { +- compatible = "marvell,dove-lcd"; +- reg = <0x810000 0x1000>; +- interrupts = <46>; +- status = "disabled"; +- }; +- +- lcd0: lcd-controller@820000 { +- compatible = "marvell,dove-lcd"; +- reg = <0x820000 0x1000>; +- interrupts = <47>; +- status = "disabled"; +- }; +- +- crypto_sram: sram@ffffe000 { +- compatible = "mmio-sram"; +- reg = <0xffffe000 0x800>; +- clocks = <&gate_clk 15>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- gpu: gpu@840000 { +- clocks = <÷r_clk 1>; +- clock-names = "core"; +- compatible = "vivante,gc"; +- interrupts = <48>; +- power-domains = <&gpu_domain>; +- reg = <0x840000 0x4000>; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra62x-clocks.dtsi b/scripts/dtc/include-prefixes/arm/dra62x-clocks.dtsi +deleted file mode 100644 +index 11d1241b0e13..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra62x-clocks.dtsi ++++ /dev/null +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +- +-#include "dm814x-clocks.dtsi" +- +-/* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */ +-&adpll_hdvic_ck { +- status = "disabled"; +-}; +- +-&adpll_l3_ck { +- status = "disabled"; +-}; +- +-&adpll_dss_ck { +- status = "disabled"; +-}; +- +-/* Compared to dm814x, dra62x has interconnect clocks on isp PLL */ +-&sysclk4_ck { +- clocks = <&adpll_isp_ck 1>; +-}; +- +-&sysclk5_ck { +- clocks = <&adpll_isp_ck 1>; +-}; +- +-&sysclk6_ck { +- clocks = <&adpll_isp_ck 1>; +-}; +- +-/* +- * Compared to dm814x, dra62x has different shifts and more mux options. +- * Please add the extra options for ysclk_14 and 16 if really needed. +- */ +-&timer1_fck { +- clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck +- &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; +- ti,bit-shift = <4>; +-}; +- +-&timer2_fck { +- clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck +- &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; +- ti,bit-shift = <8>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra62x-j5eco-evm.dts b/scripts/dtc/include-prefixes/arm/dra62x-j5eco-evm.dts +deleted file mode 100644 +index c16e183822be..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra62x-j5eco-evm.dts ++++ /dev/null +@@ -1,144 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/dts-v1/; +- +-#include "dra62x.dtsi" +-#include +- +-/ { +- model = "DRA62x J5 Eco EVM"; +- compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148", "ti,dm814"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; /* 1 GB */ +- }; +- +- /* MIC94060YC6 controlled by SD1_POW pin */ +- vmmcsd_fixed: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsd_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&cpsw_emac0 { +- phy-handle = <ðphy0>; +- phy-mode = "rgmii-id"; +-}; +- +-&cpsw_emac1 { +- phy-handle = <ðphy1>; +- phy-mode = "rgmii-id"; +-}; +- +-&davinci_mdio { +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&gpmc { +- ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ +- +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- linux,mtd-name= "micron,mt29f2g16aadwp"; +- #address-cells = <1>; +- #size-cells = <1>; +- ti,nand-ecc-opt = "bch8"; +- nand-bus-width = <16>; +- gpmc,device-width = <2>; +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-on-ns = <0>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- partition@0 { +- label = "X-Loader"; +- reg = <0 0x80000>; +- }; +- partition@80000 { +- label = "U-Boot"; +- reg = <0x80000 0x1c0000>; +- }; +- partition@1c0000 { +- label = "Environment"; +- reg = <0x240000 0x40000>; +- }; +- partition@280000 { +- label = "Kernel"; +- reg = <0x280000 0x500000>; +- }; +- partition@780000 { +- label = "Filesystem"; +- reg = <0x780000 0xf880000>; +- }; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sd1_pins>; +- vmmc-supply = <&vmmcsd_fixed>; +- bus-width = <4>; +- cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; +-}; +- +-&pincntl { +- sd1_pins: pinmux_sd1_pins { +- pinctrl-single,pins = < +- DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ +- DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ +- DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ +- DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ +- DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ +- DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ +- DM814X_IOPAD(0x0924, PIN_OUTPUT | 0x40) /* SD1_POW */ +- DM814X_IOPAD(0x093C, PIN_INPUT_PULLUP | 0x80) /* GP1[6] */ +- >; +- }; +- +- usb0_pins: pinmux_usb0_pins { +- pinctrl-single,pins = < +- DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ +- >; +- }; +-}; +- +-/* USB0_ID pin state: SW10[1] = 0 cable detection, SW10[1] = 1 ID grounded */ +-&usb0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb0_pins>; +- dr_mode = "otg"; +-}; +- +-&usb1_phy { +- status = "disabled"; +-}; +- +-&usb1 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra62x.dtsi b/scripts/dtc/include-prefixes/arm/dra62x.dtsi +deleted file mode 100644 +index cc4878aaa8ea..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra62x.dtsi ++++ /dev/null +@@ -1,23 +0,0 @@ +-/* +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-#include "dm814x.dtsi" +- +-/ { +- compatible = "ti,dra62x"; +-}; +- +-/* Compared to dm814x, dra62x has different offsets for Ethernet */ +-&mac { +- reg = <0 0x800>, +- <0x1200 0x100>; +-}; +- +-&davinci_mdio { +- reg = <0x1000 0x100>; +-}; +- +-#include "dra62x-clocks.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/dra7-dspeve-thermal.dtsi b/scripts/dtc/include-prefixes/arm/dra7-dspeve-thermal.dtsi +deleted file mode 100644 +index e75569383dd8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra7-dspeve-thermal.dtsi ++++ /dev/null +@@ -1,27 +0,0 @@ +-/* +- * Device Tree Source for DRA7x SoC DSPEVE thermal +- * +- * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-#include +- +-dspeve_thermal: dspeve_thermal { +- polling-delay-passive = <250>; /* milliseconds */ +- polling-delay = <500>; /* milliseconds */ +- +- /* sensor ID */ +- thermal-sensors = <&bandgap 3>; +- +- trips { +- dspeve_crit: dspeve_crit { +- temperature = <125000>; /* milliCelsius */ +- hysteresis = <2000>; /* milliCelsius */ +- type = "critical"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra7-evm-common.dtsi b/scripts/dtc/include-prefixes/arm/dra7-evm-common.dtsi +deleted file mode 100644 +index 0f71a9f37a72..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra7-evm-common.dtsi ++++ /dev/null +@@ -1,265 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include "dra74-ipu-dsp-common.dtsi" +-#include +-#include +-#include +- +-/ { +- chosen { +- stdout-path = &uart1; +- }; +- +- extcon_usb1: extcon_usb1 { +- compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; +- }; +- +- extcon_usb2: extcon_usb2 { +- compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; +- }; +- +- sound0: sound0 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "DRA7xx-EVM"; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack", +- "Line", "Line Out", +- "Microphone", "Mic Jack", +- "Line", "Line In"; +- simple-audio-card,routing = +- "Headphone Jack", "HPLOUT", +- "Headphone Jack", "HPROUT", +- "Line Out", "LLOUT", +- "Line Out", "RLOUT", +- "MIC3L", "Mic Jack", +- "MIC3R", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "LINE1L", "Line In", +- "LINE1R", "Line In"; +- simple-audio-card,format = "dsp_b"; +- simple-audio-card,bitclock-master = <&sound0_master>; +- simple-audio-card,frame-master = <&sound0_master>; +- simple-audio-card,bitclock-inversion; +- +- sound0_master: simple-audio-card,cpu { +- sound-dai = <&mcasp3>; +- system-clock-frequency = <5644800>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&tlv320aic3106>; +- clocks = <&atl_clkin2_ck>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led0 { +- label = "dra7:usr1"; +- gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led1 { +- label = "dra7:usr2"; +- gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led2 { +- label = "dra7:usr3"; +- gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led3 { +- label = "dra7:usr4"; +- gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- autorepeat; +- +- USER1 { +- label = "btnUser1"; +- linux,code = ; +- gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>; +- }; +- +- USER2 { +- label = "btnUser2"; +- linux,code = ; +- gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +- clock-frequency = <400000>; +-}; +- +-&mcspi1 { +- status = "okay"; +-}; +- +-&mcspi2 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +- interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, +- <&dra7_pmx_core 0x3e0>; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&qspi { +- status = "okay"; +- +- spi-max-frequency = <76800000>; +- m25p80@0 { +- compatible = "s25fl256s1"; +- spi-max-frequency = <76800000>; +- reg = <0>; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* MTD partition table. +- * The ROM checks the first four physical blocks +- * for a valid file to boot and the flash here is +- * 64KiB block size. +- */ +- partition@0 { +- label = "QSPI.SPL"; +- reg = <0x00000000 0x000010000>; +- }; +- partition@1 { +- label = "QSPI.SPL.backup1"; +- reg = <0x00010000 0x00010000>; +- }; +- partition@2 { +- label = "QSPI.SPL.backup2"; +- reg = <0x00020000 0x00010000>; +- }; +- partition@3 { +- label = "QSPI.SPL.backup3"; +- reg = <0x00030000 0x00010000>; +- }; +- partition@4 { +- label = "QSPI.u-boot"; +- reg = <0x00040000 0x00100000>; +- }; +- partition@5 { +- label = "QSPI.u-boot-spl-os"; +- reg = <0x00140000 0x00080000>; +- }; +- partition@6 { +- label = "QSPI.u-boot-env"; +- reg = <0x001c0000 0x00010000>; +- }; +- partition@7 { +- label = "QSPI.u-boot-env.backup1"; +- reg = <0x001d0000 0x0010000>; +- }; +- partition@8 { +- label = "QSPI.kernel"; +- reg = <0x001e0000 0x0800000>; +- }; +- partition@9 { +- label = "QSPI.file-system"; +- reg = <0x009e0000 0x01620000>; +- }; +- }; +-}; +- +-&omap_dwc3_1 { +- extcon = <&extcon_usb1>; +-}; +- +-&usb1 { +- dr_mode = "otg"; +- extcon = <&extcon_usb1>; +-}; +- +-&omap_dwc3_2 { +- extcon = <&extcon_usb2>; +-}; +- +-&usb2 { +- dr_mode = "host"; +- extcon = <&extcon_usb2>; +-}; +- +-&atl { +- assigned-clocks = <&abe_dpll_sys_clk_mux>, +- <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>, +- <&dpll_abe_ck>, +- <&dpll_abe_m2x2_ck>, +- <&atl_clkin2_ck>; +- assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; +- assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; +- +- status = "okay"; +- +- atl2 { +- bws = ; +- aws = ; +- }; +-}; +- +-&mcasp3 { +- #sound-dai-cells = <0>; +- +- assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; +- assigned-clock-parents = <&atl_clkin2_ck>; +- +- status = "okay"; +- +- op-mode = <0>; /* MCASP_IIS_MODE */ +- tdm-slots = <2>; +- /* 4 serializer */ +- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ +- 1 2 0 0 +- >; +- tx-num-evt = <32>; +- rx-num-evt = <32>; +-}; +- +-&pcie1_rc { +- status = "okay"; +-}; +- +-&mmc4 { +- bus-width = <4>; +- cap-power-off-card; +- keep-power-in-suspend; +- non-removable; +- #address-cells = <1>; +- #size-cells = <0>; +- wifi@2 { +- compatible = "ti,wl1835"; +- reg = <2>; +- interrupt-parent = <&gpio5>; +- interrupts = <7 IRQ_TYPE_EDGE_RISING>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra7-evm.dts b/scripts/dtc/include-prefixes/arm/dra7-evm.dts +deleted file mode 100644 +index 87deb6a76eff..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra7-evm.dts ++++ /dev/null +@@ -1,592 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "dra74x.dtsi" +-#include "dra7-evm-common.dtsi" +-#include "dra74x-mmc-iodelay.dtsi" +- +-/ { +- model = "TI DRA742"; +- compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */ +- }; +- +- evm_12v0: fixedregulator-evm_12v0 { +- /* main supply */ +- compatible = "regulator-fixed"; +- regulator-name = "evm_12v0"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- evm_1v8_sw: fixedregulator-evm_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "evm_1v8"; +- vin-supply = <&smps9_reg>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ipu2_memory_region: ipu2-memory@95800000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x95800000 0x0 0x3800000>; +- reusable; +- status = "okay"; +- }; +- +- dsp1_memory_region: dsp1-memory@99000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x99000000 0x0 0x4000000>; +- reusable; +- status = "okay"; +- }; +- +- ipu1_memory_region: ipu1-memory@9d000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x9d000000 0x0 0x2000000>; +- reusable; +- status = "okay"; +- }; +- +- dsp2_memory_region: dsp2-memory@9f000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x9f000000 0x0 0x800000>; +- reusable; +- status = "okay"; +- }; +- }; +- +- evm_3v3_sd: fixedregulator-sd { +- compatible = "regulator-fixed"; +- regulator-name = "evm_3v3_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; +- }; +- +- evm_3v3_sw: fixedregulator-evm_3v3_sw { +- compatible = "regulator-fixed"; +- regulator-name = "evm_3v3_sw"; +- vin-supply = <&sysen1>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- aic_dvdd: fixedregulator-aic_dvdd { +- /* TPS77018DBVT */ +- compatible = "regulator-fixed"; +- regulator-name = "aic_dvdd"; +- vin-supply = <&evm_3v3_sw>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vsys_3v3: fixedregulator-vsys3v3 { +- /* Output of Cntlr A of TPS43351-Q1 on dra7-evm */ +- compatible = "regulator-fixed"; +- regulator-name = "vsys_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&evm_12v0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- evm_5v0: fixedregulator-evm_5v0 { +- /* Output of Cntlr B of TPS43351-Q1 on dra7-evm */ +- compatible = "regulator-fixed"; +- regulator-name = "evm_5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&evm_12v0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- evm_3v6: fixedregulator-evm_3v6 { +- compatible = "regulator-fixed"; +- regulator-name = "evm_3v6"; +- regulator-min-microvolt = <3600000>; +- regulator-max-microvolt = <3600000>; +- vin-supply = <&evm_5v0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vmmcwl_fixed: fixedregulator-mmcwl { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcwl_fixed"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio5 8 0>; +- startup-delay-us = <70000>; +- enable-active-high; +- }; +- +- vtt_fixed: fixedregulator-vtt { +- compatible = "regulator-fixed"; +- regulator-name = "vtt_fixed"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- vin-supply = <&sysen2>; +- gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; +- }; +- +-}; +- +-&dra7_pmx_core { +- dcan1_pins_default: dcan1_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ +- DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ +- >; +- }; +- +- dcan1_pins_sleep: dcan1_pins_sleep { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ +- DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ +- >; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- tps659038: tps659038@58 { +- compatible = "ti,tps659038"; +- reg = <0x58>; +- ti,palmas-override-powerhold; +- ti,system-power-controller; +- +- tps659038_pmic { +- compatible = "ti,tps659038-pmic"; +- +- regulators { +- smps123_reg: smps123 { +- /* VDD_MPU */ +- regulator-name = "smps123"; +- regulator-min-microvolt = < 850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps45_reg: smps45 { +- /* VDD_DSPEVE */ +- regulator-name = "smps45"; +- regulator-min-microvolt = < 850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps6_reg: smps6 { +- /* VDD_GPU - over VDD_SMPS6 */ +- regulator-name = "smps6"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps7_reg: smps7 { +- /* CORE_VDD */ +- regulator-name = "smps7"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1150000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps8_reg: smps8 { +- /* VDD_IVAHD */ +- regulator-name = "smps8"; +- regulator-min-microvolt = < 850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps9_reg: smps9 { +- /* VDDS1V8 */ +- regulator-name = "smps9"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo1_reg: ldo1 { +- /* LDO1_OUT --> SDIO */ +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo2_reg: ldo2 { +- /* VDD_RTCIO */ +- /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ +- regulator-name = "ldo2"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo3_reg: ldo3 { +- /* VDDA_1V8_PHY */ +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo9_reg: ldo9 { +- /* VDD_RTC */ +- regulator-name = "ldo9"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-allow-bypass; +- }; +- +- ldoln_reg: ldoln { +- /* VDDA_1V8_PLL */ +- regulator-name = "ldoln"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldousb_reg: ldousb { +- /* VDDA_3V_USB: VDDA_USBHS33 */ +- regulator-name = "ldousb"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- +- /* REGEN1 is unused */ +- +- regen2: regen2 { +- /* Needed for PMIC internal resources */ +- regulator-name = "regen2"; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* REGEN3 is unused */ +- +- sysen1: sysen1 { +- /* PMIC_REGEN_3V3 */ +- regulator-name = "sysen1"; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sysen2: sysen2 { +- /* PMIC_REGEN_DDR */ +- regulator-name = "sysen2"; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +- }; +- +- pcf_lcd: gpio@20 { +- compatible = "nxp,pcf8575"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gpio6>; +- interrupts = <11 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pcf_gpio_21: gpio@21 { +- compatible = "nxp,pcf8575"; +- reg = <0x21>; +- lines-initial-states = <0x1408>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gpio6>; +- interrupts = <11 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- tlv320aic3106: tlv320aic3106@19 { +- #sound-dai-cells = <0>; +- compatible = "ti,tlv320aic3106"; +- reg = <0x19>; +- adc-settle-ms = <40>; +- ai3x-micbias-vg = <1>; /* 2.0V */ +- status = "okay"; +- +- /* Regulators */ +- AVDD-supply = <&evm_3v3_sw>; +- IOVDD-supply = <&evm_3v3_sw>; +- DRVDD-supply = <&evm_3v3_sw>; +- DVDD-supply = <&aic_dvdd>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- clock-frequency = <400000>; +- +- pcf_hdmi: gpio@26 { +- compatible = "nxp,pcf8575"; +- reg = <0x26>; +- gpio-controller; +- #gpio-cells = <2>; +- hdmi-audio-hog { +- /* vin6_sel_s0: high: VIN6, low: audio */ +- gpio-hog; +- gpios = <1 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "vin6_sel_s0"; +- }; +- }; +-}; +- +-&mmc1 { +- status = "okay"; +- vmmc-supply = <&evm_3v3_sd>; +- vqmmc-supply = <&ldo1_reg>; +- bus-width = <4>; +- /* +- * SDCD signal is not being used here - using the fact that GPIO mode +- * is always hardwired. +- */ +- cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104"; +- pinctrl-0 = <&mmc1_pins_default>; +- pinctrl-1 = <&mmc1_pins_hs>; +- pinctrl-2 = <&mmc1_pins_sdr12>; +- pinctrl-3 = <&mmc1_pins_sdr25>; +- pinctrl-4 = <&mmc1_pins_sdr50>; +- pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>; +- pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>; +- pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>; +- pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; +-}; +- +-&mmc2 { +- status = "okay"; +- vmmc-supply = <&evm_1v8_sw>; +- vqmmc-supply = <&evm_1v8_sw>; +- bus-width = <8>; +- non-removable; +- pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v"; +- pinctrl-0 = <&mmc2_pins_default>; +- pinctrl-1 = <&mmc2_pins_hs>; +- pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>; +- pinctrl-3 = <&mmc2_pins_ddr_rev20>; +- pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>; +- pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; +-}; +- +-&mmc4 { +- status = "okay"; +- vmmc-supply = <&evm_3v6>; +- vqmmc-supply = <&vmmcwl_fixed>; +- pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11", "sdr25"; +- pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_rev11_conf>; +- pinctrl-1 = <&mmc4_pins_default &mmc4_iodelay_ds_rev20_conf>; +- pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>; +- pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>; +- pinctrl-4 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>; +- pinctrl-5 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>; +- pinctrl-6 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>; +- pinctrl-7 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>; +-}; +- +-&cpu0 { +- vdd-supply = <&smps123_reg>; +-}; +- +-&elm { +- status = "okay"; +-}; +- +-&gpmc { +- /* +- * For the existing IOdelay configuration via U-Boot we don't +- * support NAND on dra7-evm. Keep it disabled. Enabling it +- * requires a different configuration by U-Boot. +- */ +- status = "disabled"; +- ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* device IO registers */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ +- ti,nand-xfer-type = "prefetch-dma"; +- ti,nand-ecc-opt = "bch8"; +- ti,elm-id = <&elm>; +- nand-bus-width = <16>; +- gpmc,device-width = <2>; +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <80>; +- gpmc,cs-wr-off-ns = <80>; +- gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <60>; +- gpmc,adv-wr-off-ns = <60>; +- gpmc,we-on-ns = <10>; +- gpmc,we-off-ns = <50>; +- gpmc,oe-on-ns = <4>; +- gpmc,oe-off-ns = <40>; +- gpmc,access-ns = <40>; +- gpmc,wr-access-ns = <80>; +- gpmc,rd-cycle-ns = <80>; +- gpmc,wr-cycle-ns = <80>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-data-mux-bus-ns = <0>; +- /* MTD partition table */ +- /* All SPL-* partitions are sized to minimal length +- * which can be independently programmable. For +- * NAND flash this is equal to size of erase-block */ +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "NAND.SPL"; +- reg = <0x00000000 0x000020000>; +- }; +- partition@1 { +- label = "NAND.SPL.backup1"; +- reg = <0x00020000 0x00020000>; +- }; +- partition@2 { +- label = "NAND.SPL.backup2"; +- reg = <0x00040000 0x00020000>; +- }; +- partition@3 { +- label = "NAND.SPL.backup3"; +- reg = <0x00060000 0x00020000>; +- }; +- partition@4 { +- label = "NAND.u-boot-spl-os"; +- reg = <0x00080000 0x00040000>; +- }; +- partition@5 { +- label = "NAND.u-boot"; +- reg = <0x000c0000 0x00100000>; +- }; +- partition@6 { +- label = "NAND.u-boot-env"; +- reg = <0x001c0000 0x00020000>; +- }; +- partition@7 { +- label = "NAND.u-boot-env.backup1"; +- reg = <0x001e0000 0x00020000>; +- }; +- partition@8 { +- label = "NAND.kernel"; +- reg = <0x00200000 0x00800000>; +- }; +- partition@9 { +- label = "NAND.file-system"; +- reg = <0x00a00000 0x0f600000>; +- }; +- }; +-}; +- +-&usb2_phy1 { +- phy-supply = <&ldousb_reg>; +-}; +- +-&usb2_phy2 { +- phy-supply = <&ldousb_reg>; +-}; +- +-&gpio7_target { +- ti,no-reset-on-init; +- ti,no-idle-on-init; +-}; +- +-&mac_sw { +- status = "okay"; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "rgmii"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- phy-handle = <ðphy1>; +- phy-mode = "rgmii"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&davinci_mdio_sw { +- ethphy0: ethernet-phy@2 { +- reg = <2>; +- }; +- +- ethphy1: ethernet-phy@3 { +- reg = <3>; +- }; +-}; +- +-&dcan1 { +- status = "okay"; +- pinctrl-names = "default", "sleep", "active"; +- pinctrl-0 = <&dcan1_pins_sleep>; +- pinctrl-1 = <&dcan1_pins_sleep>; +- pinctrl-2 = <&dcan1_pins_default>; +-}; +- +-&ipu2 { +- status = "okay"; +- memory-region = <&ipu2_memory_region>; +-}; +- +-&ipu1 { +- status = "okay"; +- memory-region = <&ipu1_memory_region>; +-}; +- +-&dsp1 { +- status = "okay"; +- memory-region = <&dsp1_memory_region>; +-}; +- +-&dsp2 { +- status = "okay"; +- memory-region = <&dsp2_memory_region>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra7-ipu-dsp-common.dtsi b/scripts/dtc/include-prefixes/arm/dra7-ipu-dsp-common.dtsi +deleted file mode 100644 +index a5bdc6431d8d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra7-ipu-dsp-common.dtsi ++++ /dev/null +@@ -1,39 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Common IPU and DSP data for TI DRA7xx/AM57xx platforms +- */ +- +-&mailbox5 { +- status = "okay"; +- mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { +- status = "okay"; +- }; +- mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { +- status = "okay"; +- }; +-}; +- +-&mailbox6 { +- status = "okay"; +- mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { +- status = "okay"; +- }; +-}; +- +-&ipu2 { +- mboxes = <&mailbox6 &mbox_ipu2_ipc3x>; +- ti,timers = <&timer3>; +- ti,watchdog-timers = <&timer4>, <&timer9>; +-}; +- +-&ipu1 { +- mboxes = <&mailbox5 &mbox_ipu1_ipc3x>; +- ti,timers = <&timer11>; +- ti,watchdog-timers = <&timer7>, <&timer8>; +-}; +- +-&dsp1 { +- mboxes = <&mailbox5 &mbox_dsp1_ipc3x>; +- ti,timers = <&timer5>; +- ti,watchdog-timers = <&timer10>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra7-iva-thermal.dtsi b/scripts/dtc/include-prefixes/arm/dra7-iva-thermal.dtsi +deleted file mode 100644 +index a7077321613f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra7-iva-thermal.dtsi ++++ /dev/null +@@ -1,27 +0,0 @@ +-/* +- * Device Tree Source for DRA7x SoC IVA thermal +- * +- * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-#include +- +-iva_thermal: iva_thermal { +- polling-delay-passive = <250>; /* milliseconds */ +- polling-delay = <500>; /* milliseconds */ +- +- /* sensor ID */ +- thermal-sensors = <&bandgap 4>; +- +- trips { +- iva_crit: iva_crit { +- temperature = <125000>; /* milliCelsius */ +- hysteresis = <2000>; /* milliCelsius */ +- type = "critical"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra7-l4.dtsi b/scripts/dtc/include-prefixes/arm/dra7-l4.dtsi +deleted file mode 100644 +index 956a26d52a4c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra7-l4.dtsi ++++ /dev/null +@@ -1,4607 +0,0 @@ +-&l4_cfg { /* 0x4a000000 */ +- compatible = "ti,dra7-l4-cfg", "simple-pm-bus"; +- power-domains = <&prm_coreaon>; +- clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>; +- clock-names = "fck"; +- reg = <0x4a000000 0x800>, +- <0x4a000800 0x800>, +- <0x4a001000 0x1000>; +- reg-names = "ap", "la", "ia0"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */ +- <0x00100000 0x4a100000 0x100000>, /* segment 1 */ +- <0x00200000 0x4a200000 0x100000>; /* segment 2 */ +- +- segment@0 { /* 0x4a000000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ +- <0x00000800 0x00000800 0x000800>, /* ap 1 */ +- <0x00001000 0x00001000 0x001000>, /* ap 2 */ +- <0x00002000 0x00002000 0x002000>, /* ap 3 */ +- <0x00004000 0x00004000 0x001000>, /* ap 4 */ +- <0x00005000 0x00005000 0x001000>, /* ap 5 */ +- <0x00006000 0x00006000 0x001000>, /* ap 6 */ +- <0x00008000 0x00008000 0x002000>, /* ap 7 */ +- <0x0000a000 0x0000a000 0x001000>, /* ap 8 */ +- <0x00056000 0x00056000 0x001000>, /* ap 9 */ +- <0x00057000 0x00057000 0x001000>, /* ap 10 */ +- <0x0005e000 0x0005e000 0x002000>, /* ap 11 */ +- <0x00060000 0x00060000 0x001000>, /* ap 12 */ +- <0x00080000 0x00080000 0x008000>, /* ap 13 */ +- <0x00088000 0x00088000 0x001000>, /* ap 14 */ +- <0x000a0000 0x000a0000 0x008000>, /* ap 15 */ +- <0x000a8000 0x000a8000 0x001000>, /* ap 16 */ +- <0x000d9000 0x000d9000 0x001000>, /* ap 17 */ +- <0x000da000 0x000da000 0x001000>, /* ap 18 */ +- <0x000dd000 0x000dd000 0x001000>, /* ap 19 */ +- <0x000de000 0x000de000 0x001000>, /* ap 20 */ +- <0x000e0000 0x000e0000 0x001000>, /* ap 21 */ +- <0x000e1000 0x000e1000 0x001000>, /* ap 22 */ +- <0x000f4000 0x000f4000 0x001000>, /* ap 23 */ +- <0x000f5000 0x000f5000 0x001000>, /* ap 24 */ +- <0x000f6000 0x000f6000 0x001000>, /* ap 25 */ +- <0x000f7000 0x000f7000 0x001000>, /* ap 26 */ +- <0x00090000 0x00090000 0x008000>, /* ap 59 */ +- <0x00098000 0x00098000 0x001000>; /* ap 60 */ +- +- target-module@2000 { /* 0x4a002000, ap 3 08.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x2000 0x4>; +- reg-names = "rev"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2000 0x2000>; +- +- scm: scm@0 { +- compatible = "ti,dra7-scm-core", "simple-bus"; +- reg = <0 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x2000>; +- +- scm_conf: scm_conf@0 { +- compatible = "syscon", "simple-bus"; +- reg = <0x0 0x1400>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x0 0x1400>; +- +- pbias_regulator: pbias_regulator@e00 { +- compatible = "ti,pbias-dra7", "ti,pbias-omap"; +- reg = <0xe00 0x4>; +- syscon = <&scm_conf>; +- pbias_mmc_reg: pbias_mmc_omap5 { +- regulator-name = "pbias_mmc_omap5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +- +- phy_gmii_sel: phy-gmii-sel { +- compatible = "ti,dra7xx-phy-gmii-sel"; +- reg = <0x554 0x4>; +- #phy-cells = <1>; +- }; +- +- scm_conf_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- dra7_pmx_core: pinmux@1400 { +- compatible = "ti,dra7-padconf", +- "pinctrl-single"; +- reg = <0x1400 0x0468>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <1>; +- #interrupt-cells = <1>; +- interrupt-controller; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0x3fffffff>; +- }; +- +- scm_conf1: scm_conf@1c04 { +- compatible = "syscon"; +- reg = <0x1c04 0x0020>; +- #syscon-cells = <2>; +- }; +- +- scm_conf_pcie: scm_conf@1c24 { +- compatible = "syscon"; +- reg = <0x1c24 0x0024>; +- }; +- +- sdma_xbar: dma-router@b78 { +- compatible = "ti,dra7-dma-crossbar"; +- reg = <0xb78 0xfc>; +- #dma-cells = <1>; +- dma-requests = <205>; +- ti,dma-safe-map = <0>; +- dma-masters = <&sdma>; +- }; +- +- edma_xbar: dma-router@c78 { +- compatible = "ti,dra7-dma-crossbar"; +- reg = <0xc78 0x7c>; +- #dma-cells = <2>; +- dma-requests = <204>; +- ti,dma-safe-map = <0>; +- dma-masters = <&edma>; +- }; +- }; +- }; +- +- target-module@5000 { /* 0x4a005000, ap 5 10.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x5000 0x4>; +- reg-names = "rev"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5000 0x1000>; +- +- cm_core_aon: cm_core_aon@0 { +- compatible = "ti,dra7-cm-core-aon", +- "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0 0x2000>; +- ranges = <0 0 0x2000>; +- +- cm_core_aon_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- cm_core_aon_clockdomains: clockdomains { +- }; +- }; +- }; +- +- target-module@8000 { /* 0x4a008000, ap 7 0e.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x8000 0x4>; +- reg-names = "rev"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x8000 0x2000>; +- +- cm_core: cm_core@0 { +- compatible = "ti,dra7-cm-core", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0 0x3000>; +- ranges = <0 0 0x3000>; +- +- cm_core_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- cm_core_clockdomains: clockdomains { +- }; +- }; +- }; +- +- target-module@56000 { /* 0x4a056000, ap 9 02.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x56000 0x4>, +- <0x5602c 0x4>, +- <0x56028 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): core_pwrdm, dma_clkdm */ +- clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x56000 0x1000>; +- +- sdma: dma-controller@0 { +- compatible = "ti,omap4430-sdma", "ti,omap-sdma"; +- reg = <0x0 0x1000>; +- interrupts = , +- , +- , +- ; +- #dma-cells = <1>; +- dma-channels = <32>; +- dma-requests = <127>; +- }; +- }; +- +- target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5e000 0x2000>; +- }; +- +- target-module@80000 { /* 0x4a080000, ap 13 20.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x80000 0x4>, +- <0x80010 0x4>, +- <0x80014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ +- clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x80000 0x8000>; +- +- ocp2scp@0 { +- compatible = "ti,omap-ocp2scp"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x8000>; +- reg = <0x0 0x20>; +- +- usb2_phy1: phy@4000 { +- compatible = "ti,dra7x-usb2", "ti,omap-usb2"; +- reg = <0x4000 0x400>; +- syscon-phy-power = <&scm_conf 0x300>; +- clocks = <&usb_phy1_always_on_clk32k>, +- <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; +- clock-names = "wkupclk", +- "refclk"; +- #phy-cells = <0>; +- }; +- +- usb2_phy2: phy@5000 { +- compatible = "ti,dra7x-usb2-phy2", +- "ti,omap-usb2"; +- reg = <0x5000 0x400>; +- syscon-phy-power = <&scm_conf 0xe74>; +- clocks = <&usb_phy2_always_on_clk32k>, +- <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>; +- clock-names = "wkupclk", +- "refclk"; +- #phy-cells = <0>; +- }; +- +- usb3_phy1: phy@4400 { +- compatible = "ti,omap-usb3"; +- reg = <0x4400 0x80>, +- <0x4800 0x64>, +- <0x4c00 0x40>; +- reg-names = "phy_rx", "phy_tx", "pll_ctrl"; +- syscon-phy-power = <&scm_conf 0x370>; +- clocks = <&usb_phy3_always_on_clk32k>, +- <&sys_clkin1>, +- <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; +- clock-names = "wkupclk", +- "sysclk", +- "refclk"; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- target-module@90000 { /* 0x4a090000, ap 59 42.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x90000 0x4>, +- <0x90010 0x4>, +- <0x90014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ +- clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x90000 0x8000>; +- +- ocp2scp@0 { +- compatible = "ti,omap-ocp2scp"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x8000>; +- reg = <0x0 0x20>; +- +- pcie1_phy: pciephy@4000 { +- compatible = "ti,phy-pipe3-pcie"; +- reg = <0x4000 0x80>, /* phy_rx */ +- <0x4400 0x64>; /* phy_tx */ +- reg-names = "phy_rx", "phy_tx"; +- syscon-phy-power = <&scm_conf_pcie 0x1c>; +- syscon-pcs = <&scm_conf_pcie 0x10>; +- clocks = <&dpll_pcie_ref_ck>, +- <&dpll_pcie_ref_m2ldo_ck>, +- <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>, +- <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>, +- <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>, +- <&optfclk_pciephy_div>, +- <&sys_clkin1>; +- clock-names = "dpll_ref", "dpll_ref_m2", +- "wkupclk", "refclk", +- "div-clk", "phy-div", "sysclk"; +- #phy-cells = <0>; +- }; +- +- pcie2_phy: pciephy@5000 { +- compatible = "ti,phy-pipe3-pcie"; +- reg = <0x5000 0x80>, /* phy_rx */ +- <0x5400 0x64>; /* phy_tx */ +- reg-names = "phy_rx", "phy_tx"; +- syscon-phy-power = <&scm_conf_pcie 0x20>; +- syscon-pcs = <&scm_conf_pcie 0x10>; +- clocks = <&dpll_pcie_ref_ck>, +- <&dpll_pcie_ref_m2ldo_ck>, +- <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>, +- <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>, +- <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>, +- <&optfclk_pciephy_div>, +- <&sys_clkin1>; +- clock-names = "dpll_ref", "dpll_ref_m2", +- "wkupclk", "refclk", +- "div-clk", "phy-div", "sysclk"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- sata_phy: phy@6000 { +- compatible = "ti,phy-pipe3-sata"; +- reg = <0x6000 0x80>, /* phy_rx */ +- <0x6400 0x64>, /* phy_tx */ +- <0x6800 0x40>; /* pll_ctrl */ +- reg-names = "phy_rx", "phy_tx", "pll_ctrl"; +- syscon-phy-power = <&scm_conf 0x374>; +- clocks = <&sys_clkin1>, +- <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; +- clock-names = "sysclk", "refclk"; +- syscon-pllreset = <&scm_conf 0x3fc>; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa0000 0x8000>; +- }; +- +- target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */ +- compatible = "ti,sysc-omap4-sr", "ti,sysc"; +- reg = <0xd9038 0x4>; +- reg-names = "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ +- clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xd9000 0x1000>; +- +- /* SmartReflex child device marked reserved in TRM */ +- }; +- +- target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */ +- compatible = "ti,sysc-omap4-sr", "ti,sysc"; +- reg = <0xdd038 0x4>; +- reg-names = "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ +- clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xdd000 0x1000>; +- +- /* SmartReflex child device marked reserved in TRM */ +- }; +- +- target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xe0000 0x1000>; +- }; +- +- target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xf4000 0x4>, +- <0xf4010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ +- clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf4000 0x1000>; +- +- mailbox1: mailbox@0 { +- compatible = "ti,omap4-mailbox"; +- reg = <0x0 0x200>; +- interrupts = , +- , +- ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <3>; +- ti,mbox-num-fifos = <8>; +- status = "disabled"; +- }; +- }; +- +- target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xf6000 0x4>, +- <0xf6010 0x4>, +- <0xf6014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ +- clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf6000 0x1000>; +- +- hwspinlock: spinlock@0 { +- compatible = "ti,omap4-hwspinlock"; +- reg = <0x0 0x1000>; +- #hwlock-cells = <1>; +- }; +- }; +- }; +- +- segment@100000 { /* 0x4a100000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */ +- <0x00003000 0x00103000 0x001000>, /* ap 28 */ +- <0x00008000 0x00108000 0x001000>, /* ap 29 */ +- <0x00009000 0x00109000 0x001000>, /* ap 30 */ +- <0x00040000 0x00140000 0x010000>, /* ap 31 */ +- <0x00050000 0x00150000 0x001000>, /* ap 32 */ +- <0x00051000 0x00151000 0x001000>, /* ap 33 */ +- <0x00052000 0x00152000 0x001000>, /* ap 34 */ +- <0x00053000 0x00153000 0x001000>, /* ap 35 */ +- <0x00054000 0x00154000 0x001000>, /* ap 36 */ +- <0x00055000 0x00155000 0x001000>, /* ap 37 */ +- <0x00056000 0x00156000 0x001000>, /* ap 38 */ +- <0x00057000 0x00157000 0x001000>, /* ap 39 */ +- <0x00058000 0x00158000 0x001000>, /* ap 40 */ +- <0x0005b000 0x0015b000 0x001000>, /* ap 41 */ +- <0x0005c000 0x0015c000 0x001000>, /* ap 42 */ +- <0x0005d000 0x0015d000 0x001000>, /* ap 45 */ +- <0x0005e000 0x0015e000 0x001000>, /* ap 46 */ +- <0x0005f000 0x0015f000 0x001000>, /* ap 47 */ +- <0x00060000 0x00160000 0x001000>, /* ap 48 */ +- <0x00061000 0x00161000 0x001000>, /* ap 49 */ +- <0x00062000 0x00162000 0x001000>, /* ap 50 */ +- <0x00063000 0x00163000 0x001000>, /* ap 51 */ +- <0x00064000 0x00164000 0x001000>, /* ap 52 */ +- <0x00065000 0x00165000 0x001000>, /* ap 53 */ +- <0x00066000 0x00166000 0x001000>, /* ap 54 */ +- <0x00067000 0x00167000 0x001000>, /* ap 55 */ +- <0x00068000 0x00168000 0x001000>, /* ap 56 */ +- <0x0006d000 0x0016d000 0x001000>, /* ap 57 */ +- <0x0006e000 0x0016e000 0x001000>, /* ap 58 */ +- <0x00071000 0x00171000 0x001000>, /* ap 61 */ +- <0x00072000 0x00172000 0x001000>, /* ap 62 */ +- <0x00073000 0x00173000 0x001000>, /* ap 63 */ +- <0x00074000 0x00174000 0x001000>, /* ap 64 */ +- <0x00075000 0x00175000 0x001000>, /* ap 65 */ +- <0x00076000 0x00176000 0x001000>, /* ap 66 */ +- <0x00077000 0x00177000 0x001000>, /* ap 67 */ +- <0x00078000 0x00178000 0x001000>, /* ap 68 */ +- <0x00081000 0x00181000 0x001000>, /* ap 69 */ +- <0x00082000 0x00182000 0x001000>, /* ap 70 */ +- <0x00083000 0x00183000 0x001000>, /* ap 71 */ +- <0x00084000 0x00184000 0x001000>, /* ap 72 */ +- <0x00085000 0x00185000 0x001000>, /* ap 73 */ +- <0x00086000 0x00186000 0x001000>, /* ap 74 */ +- <0x00087000 0x00187000 0x001000>, /* ap 75 */ +- <0x00088000 0x00188000 0x001000>, /* ap 76 */ +- <0x00069000 0x00169000 0x001000>, /* ap 103 */ +- <0x0006a000 0x0016a000 0x001000>, /* ap 104 */ +- <0x00079000 0x00179000 0x001000>, /* ap 105 */ +- <0x0007a000 0x0017a000 0x001000>, /* ap 106 */ +- <0x0006b000 0x0016b000 0x001000>, /* ap 107 */ +- <0x0006c000 0x0016c000 0x001000>, /* ap 108 */ +- <0x0007b000 0x0017b000 0x001000>, /* ap 121 */ +- <0x0007c000 0x0017c000 0x001000>, /* ap 122 */ +- <0x0007d000 0x0017d000 0x001000>, /* ap 123 */ +- <0x0007e000 0x0017e000 0x001000>, /* ap 124 */ +- <0x00059000 0x00159000 0x001000>, /* ap 125 */ +- <0x0005a000 0x0015a000 0x001000>; /* ap 126 */ +- +- target-module@2000 { /* 0x4a102000, ap 27 3c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2000 0x1000>; +- }; +- +- target-module@8000 { /* 0x4a108000, ap 29 1e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x8000 0x1000>; +- }; +- +- target-module@40000 { /* 0x4a140000, ap 31 06.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x400fc 4>, +- <0x41100 4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- power-domains = <&prm_l3init>; +- clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 0>; +- clock-names = "fck"; +- #size-cells = <1>; +- #address-cells = <1>; +- ranges = <0x0 0x40000 0x10000>; +- +- sata: sata@0 { +- compatible = "snps,dwc-ahci"; +- reg = <0 0x1100>, <0x1100 0x8>; +- interrupts = ; +- phys = <&sata_phy>; +- phy-names = "sata-phy"; +- clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; +- ports-implemented = <0x1>; +- }; +- }; +- +- target-module@51000 { /* 0x4a151000, ap 33 50.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x51000 0x1000>; +- }; +- +- target-module@53000 { /* 0x4a153000, ap 35 54.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x53000 0x1000>; +- }; +- +- target-module@55000 { /* 0x4a155000, ap 37 46.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x55000 0x1000>; +- }; +- +- target-module@57000 { /* 0x4a157000, ap 39 58.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x57000 0x1000>; +- }; +- +- target-module@59000 { /* 0x4a159000, ap 125 6a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x59000 0x1000>; +- }; +- +- target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5b000 0x1000>; +- }; +- +- target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5d000 0x1000>; +- }; +- +- target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5f000 0x1000>; +- }; +- +- target-module@61000 { /* 0x4a161000, ap 49 32.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x61000 0x1000>; +- }; +- +- target-module@63000 { /* 0x4a163000, ap 51 5c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x63000 0x1000>; +- }; +- +- target-module@65000 { /* 0x4a165000, ap 53 4e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x65000 0x1000>; +- }; +- +- target-module@67000 { /* 0x4a167000, ap 55 5e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x67000 0x1000>; +- }; +- +- target-module@69000 { /* 0x4a169000, ap 103 4a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x69000 0x1000>; +- }; +- +- target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6b000 0x1000>; +- }; +- +- target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6d000 0x1000>; +- }; +- +- target-module@71000 { /* 0x4a171000, ap 61 48.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x71000 0x1000>; +- }; +- +- target-module@73000 { /* 0x4a173000, ap 63 2a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x73000 0x1000>; +- }; +- +- target-module@75000 { /* 0x4a175000, ap 65 64.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x75000 0x1000>; +- }; +- +- target-module@77000 { /* 0x4a177000, ap 67 66.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x77000 0x1000>; +- }; +- +- target-module@79000 { /* 0x4a179000, ap 105 34.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x79000 0x1000>; +- }; +- +- target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x7b000 0x1000>; +- }; +- +- target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x7d000 0x1000>; +- }; +- +- target-module@81000 { /* 0x4a181000, ap 69 26.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x81000 0x1000>; +- }; +- +- target-module@83000 { /* 0x4a183000, ap 71 2e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x83000 0x1000>; +- }; +- +- target-module@85000 { /* 0x4a185000, ap 73 36.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x85000 0x1000>; +- }; +- +- target-module@87000 { /* 0x4a187000, ap 75 74.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x87000 0x1000>; +- }; +- }; +- +- segment@200000 { /* 0x4a200000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */ +- <0x00019000 0x00219000 0x001000>, /* ap 44 */ +- <0x00000000 0x00200000 0x001000>, /* ap 77 */ +- <0x00001000 0x00201000 0x001000>, /* ap 78 */ +- <0x0000a000 0x0020a000 0x001000>, /* ap 79 */ +- <0x0000b000 0x0020b000 0x001000>, /* ap 80 */ +- <0x0000c000 0x0020c000 0x001000>, /* ap 81 */ +- <0x0000d000 0x0020d000 0x001000>, /* ap 82 */ +- <0x0000e000 0x0020e000 0x001000>, /* ap 83 */ +- <0x0000f000 0x0020f000 0x001000>, /* ap 84 */ +- <0x00010000 0x00210000 0x001000>, /* ap 85 */ +- <0x00011000 0x00211000 0x001000>, /* ap 86 */ +- <0x00012000 0x00212000 0x001000>, /* ap 87 */ +- <0x00013000 0x00213000 0x001000>, /* ap 88 */ +- <0x00014000 0x00214000 0x001000>, /* ap 89 */ +- <0x00015000 0x00215000 0x001000>, /* ap 90 */ +- <0x0002a000 0x0022a000 0x001000>, /* ap 91 */ +- <0x0002b000 0x0022b000 0x001000>, /* ap 92 */ +- <0x0001c000 0x0021c000 0x001000>, /* ap 93 */ +- <0x0001d000 0x0021d000 0x001000>, /* ap 94 */ +- <0x0001e000 0x0021e000 0x001000>, /* ap 95 */ +- <0x0001f000 0x0021f000 0x001000>, /* ap 96 */ +- <0x00020000 0x00220000 0x001000>, /* ap 97 */ +- <0x00021000 0x00221000 0x001000>, /* ap 98 */ +- <0x00024000 0x00224000 0x001000>, /* ap 99 */ +- <0x00025000 0x00225000 0x001000>, /* ap 100 */ +- <0x00026000 0x00226000 0x001000>, /* ap 101 */ +- <0x00027000 0x00227000 0x001000>, /* ap 102 */ +- <0x0002c000 0x0022c000 0x001000>, /* ap 109 */ +- <0x0002d000 0x0022d000 0x001000>, /* ap 110 */ +- <0x0002e000 0x0022e000 0x001000>, /* ap 111 */ +- <0x0002f000 0x0022f000 0x001000>, /* ap 112 */ +- <0x00030000 0x00230000 0x001000>, /* ap 113 */ +- <0x00031000 0x00231000 0x001000>, /* ap 114 */ +- <0x00032000 0x00232000 0x001000>, /* ap 115 */ +- <0x00033000 0x00233000 0x001000>, /* ap 116 */ +- <0x00034000 0x00234000 0x001000>, /* ap 117 */ +- <0x00035000 0x00235000 0x001000>, /* ap 118 */ +- <0x00036000 0x00236000 0x001000>, /* ap 119 */ +- <0x00037000 0x00237000 0x001000>, /* ap 120 */ +- <0x0001a000 0x0021a000 0x001000>, /* ap 127 */ +- <0x0001b000 0x0021b000 0x001000>; /* ap 128 */ +- +- target-module@0 { /* 0x4a200000, ap 77 3e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1000>; +- }; +- +- target-module@a000 { /* 0x4a20a000, ap 79 30.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa000 0x1000>; +- }; +- +- target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc000 0x1000>; +- }; +- +- target-module@e000 { /* 0x4a20e000, ap 83 22.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xe000 0x1000>; +- }; +- +- target-module@10000 { /* 0x4a210000, ap 85 14.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10000 0x1000>; +- }; +- +- target-module@12000 { /* 0x4a212000, ap 87 16.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x12000 0x1000>; +- }; +- +- target-module@14000 { /* 0x4a214000, ap 89 1c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x14000 0x1000>; +- }; +- +- target-module@18000 { /* 0x4a218000, ap 43 12.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x18000 0x1000>; +- }; +- +- target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1a000 0x1000>; +- }; +- +- target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1c000 0x1000>; +- }; +- +- target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1e000 0x1000>; +- }; +- +- target-module@20000 { /* 0x4a220000, ap 97 24.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x20000 0x1000>; +- }; +- +- target-module@24000 { /* 0x4a224000, ap 99 44.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x24000 0x1000>; +- }; +- +- target-module@26000 { /* 0x4a226000, ap 101 2c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x26000 0x1000>; +- }; +- +- target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2a000 0x1000>; +- }; +- +- target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2c000 0x1000>; +- }; +- +- target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2e000 0x1000>; +- }; +- +- target-module@30000 { /* 0x4a230000, ap 113 70.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x30000 0x1000>; +- }; +- +- target-module@32000 { /* 0x4a232000, ap 115 5a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x32000 0x1000>; +- }; +- +- target-module@34000 { /* 0x4a234000, ap 117 76.1 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x34000 0x1000>; +- }; +- +- target-module@36000 { /* 0x4a236000, ap 119 62.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x36000 0x1000>; +- }; +- }; +-}; +- +-&l4_per1 { /* 0x48000000 */ +- compatible = "ti,dra7-l4-per1", "simple-pm-bus"; +- power-domains = <&prm_l4per>; +- clocks = <&l4per_clkctrl DRA7_L4PER_L4_PER1_CLKCTRL 0>; +- clock-names = "fck"; +- reg = <0x48000000 0x800>, +- <0x48000800 0x800>, +- <0x48001000 0x400>, +- <0x48001400 0x400>, +- <0x48001800 0x400>, +- <0x48001c00 0x400>; +- reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ +- <0x00200000 0x48200000 0x200000>; /* segment 1 */ +- +- segment@0 { /* 0x48000000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ +- <0x00001000 0x00001000 0x000400>, /* ap 1 */ +- <0x00000800 0x00000800 0x000800>, /* ap 2 */ +- <0x00020000 0x00020000 0x001000>, /* ap 3 */ +- <0x00021000 0x00021000 0x001000>, /* ap 4 */ +- <0x00032000 0x00032000 0x001000>, /* ap 5 */ +- <0x00033000 0x00033000 0x001000>, /* ap 6 */ +- <0x00034000 0x00034000 0x001000>, /* ap 7 */ +- <0x00035000 0x00035000 0x001000>, /* ap 8 */ +- <0x00036000 0x00036000 0x001000>, /* ap 9 */ +- <0x00037000 0x00037000 0x001000>, /* ap 10 */ +- <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ +- <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ +- <0x00055000 0x00055000 0x001000>, /* ap 13 */ +- <0x00056000 0x00056000 0x001000>, /* ap 14 */ +- <0x00057000 0x00057000 0x001000>, /* ap 15 */ +- <0x00058000 0x00058000 0x001000>, /* ap 16 */ +- <0x00059000 0x00059000 0x001000>, /* ap 17 */ +- <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ +- <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ +- <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ +- <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ +- <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ +- <0x00060000 0x00060000 0x001000>, /* ap 23 */ +- <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ +- <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ +- <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ +- <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ +- <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ +- <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ +- <0x00070000 0x00070000 0x001000>, /* ap 30 */ +- <0x00071000 0x00071000 0x001000>, /* ap 31 */ +- <0x00072000 0x00072000 0x001000>, /* ap 32 */ +- <0x00073000 0x00073000 0x001000>, /* ap 33 */ +- <0x00061000 0x00061000 0x001000>, /* ap 34 */ +- <0x00053000 0x00053000 0x001000>, /* ap 35 */ +- <0x00054000 0x00054000 0x001000>, /* ap 36 */ +- <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ +- <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ +- <0x00078000 0x00078000 0x001000>, /* ap 39 */ +- <0x00079000 0x00079000 0x001000>, /* ap 40 */ +- <0x00086000 0x00086000 0x001000>, /* ap 41 */ +- <0x00087000 0x00087000 0x001000>, /* ap 42 */ +- <0x00088000 0x00088000 0x001000>, /* ap 43 */ +- <0x00089000 0x00089000 0x001000>, /* ap 44 */ +- <0x00051000 0x00051000 0x001000>, /* ap 45 */ +- <0x00052000 0x00052000 0x001000>, /* ap 46 */ +- <0x00098000 0x00098000 0x001000>, /* ap 47 */ +- <0x00099000 0x00099000 0x001000>, /* ap 48 */ +- <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ +- <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ +- <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ +- <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ +- <0x00068000 0x00068000 0x001000>, /* ap 53 */ +- <0x00069000 0x00069000 0x001000>, /* ap 54 */ +- <0x00090000 0x00090000 0x002000>, /* ap 55 */ +- <0x00092000 0x00092000 0x001000>, /* ap 56 */ +- <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ +- <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ +- <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ +- <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ +- <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ +- <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ +- <0x00066000 0x00066000 0x001000>, /* ap 63 */ +- <0x00067000 0x00067000 0x001000>, /* ap 64 */ +- <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ +- <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ +- <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ +- <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ +- <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ +- <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ +- <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ +- <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ +- <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ +- <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ +- <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ +- <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ +- <0x00001400 0x00001400 0x000400>, /* ap 77 */ +- <0x00001800 0x00001800 0x000400>, /* ap 78 */ +- <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ +- <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ +- <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ +- <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ +- <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ +- <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ +- +- target-module@20000 { /* 0x48020000, ap 3 04.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x20050 0x4>, +- <0x20054 0x4>, +- <0x20058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x20000 0x1000>; +- +- uart3: serial@0 { +- compatible = "ti,dra742-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- status = "disabled"; +- dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@32000 { /* 0x48032000, ap 5 3e.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x32000 0x4>, +- <0x32010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x32000 0x1000>; +- +- timer2: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>, <&timer_sys_clk_div>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- }; +- }; +- +- timer3_target: target-module@34000 { /* 0x48034000, ap 7 46.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x34000 0x4>, +- <0x34010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x34000 0x1000>; +- +- timer3: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>, <&timer_sys_clk_div>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- }; +- }; +- +- timer4_target: target-module@36000 { /* 0x48036000, ap 9 4e.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x36000 0x4>, +- <0x36010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x36000 0x1000>; +- +- timer4: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>, <&timer_sys_clk_div>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- }; +- }; +- +- target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x3e000 0x4>, +- <0x3e010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3e000 0x1000>; +- +- timer9: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>, <&timer_sys_clk_div>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- }; +- }; +- +- gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x51000 0x4>, +- <0x51010 0x4>, +- <0x51114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>, +- <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x51000 0x1000>; +- +- gpio7: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@53000 { /* 0x48053000, ap 35 36.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x53000 0x4>, +- <0x53010 0x4>, +- <0x53114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>, +- <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x53000 0x1000>; +- +- gpio8: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- gpio2_target: target-module@55000 { /* 0x48055000, ap 13 0e.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x55000 0x4>, +- <0x55010 0x4>, +- <0x55114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>, +- <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x55000 0x1000>; +- +- gpio2: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- gpio3_target: target-module@57000 { /* 0x48057000, ap 15 06.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x57000 0x4>, +- <0x57010 0x4>, +- <0x57114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>, +- <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x57000 0x1000>; +- +- gpio3: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@59000 { /* 0x48059000, ap 17 16.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x59000 0x4>, +- <0x59010 0x4>, +- <0x59114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>, +- <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x59000 0x1000>; +- +- gpio4: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x5b000 0x4>, +- <0x5b010 0x4>, +- <0x5b114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>, +- <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5b000 0x1000>; +- +- gpio5: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x5d000 0x4>, +- <0x5d010 0x4>, +- <0x5d114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>, +- <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5d000 0x1000>; +- +- gpio6: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@60000 { /* 0x48060000, ap 23 32.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x60000 0x8>, +- <0x60010 0x8>, +- <0x60090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x60000 0x1000>; +- +- i2c3: i2c@0 { +- compatible = "ti,omap4-i2c"; +- reg = <0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- target-module@66000 { /* 0x48066000, ap 63 14.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x66050 0x4>, +- <0x66054 0x4>, +- <0x66058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x66000 0x1000>; +- +- uart5: serial@0 { +- compatible = "ti,dra742-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- status = "disabled"; +- dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@68000 { /* 0x48068000, ap 53 1c.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x68050 0x4>, +- <0x68054 0x4>, +- <0x68058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ +- clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x68000 0x1000>; +- +- uart6: serial@0 { +- compatible = "ti,dra742-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- status = "disabled"; +- dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@6a000 { /* 0x4806a000, ap 24 24.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x6a050 0x4>, +- <0x6a054 0x4>, +- <0x6a058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6a000 0x1000>; +- +- uart1: serial@0 { +- compatible = "ti,dra742-uart"; +- reg = <0x0 0x100>; +- interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; +- clock-frequency = <48000000>; +- status = "disabled"; +- dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x6c050 0x4>, +- <0x6c054 0x4>, +- <0x6c058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6c000 0x1000>; +- +- uart2: serial@0 { +- compatible = "ti,dra742-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- status = "disabled"; +- dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x6e050 0x4>, +- <0x6e054 0x4>, +- <0x6e058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6e000 0x1000>; +- +- uart4: serial@0 { +- compatible = "ti,dra742-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- status = "disabled"; +- dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@70000 { /* 0x48070000, ap 30 22.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x70000 0x8>, +- <0x70010 0x8>, +- <0x70090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x70000 0x1000>; +- +- i2c1: i2c@0 { +- compatible = "ti,omap4-i2c"; +- reg = <0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- target-module@72000 { /* 0x48072000, ap 32 2a.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x72000 0x8>, +- <0x72010 0x8>, +- <0x72090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x72000 0x1000>; +- +- i2c2: i2c@0 { +- compatible = "ti,omap4-i2c"; +- reg = <0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- target-module@78000 { /* 0x48078000, ap 39 0a.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x78000 0x4>, +- <0x78010 0x4>, +- <0x78014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x78000 0x1000>; +- +- elm: elm@0 { +- compatible = "ti,am3352-elm"; +- reg = <0x0 0xfc0>; /* device IO registers */ +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x7a000 0x8>, +- <0x7a010 0x8>, +- <0x7a090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x7a000 0x1000>; +- +- i2c4: i2c@0 { +- compatible = "ti,omap4-i2c"; +- reg = <0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x7c000 0x8>, +- <0x7c010 0x8>, +- <0x7c090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ +- clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x7c000 0x1000>; +- +- i2c5: i2c@0 { +- compatible = "ti,omap4-i2c"; +- reg = <0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- target-module@86000 { /* 0x48086000, ap 41 5e.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x86000 0x4>, +- <0x86010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x86000 0x1000>; +- +- timer10: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>, <&timer_sys_clk_div>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- }; +- }; +- +- target-module@88000 { /* 0x48088000, ap 43 66.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x88000 0x4>, +- <0x88010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x88000 0x1000>; +- +- timer11: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>, <&timer_sys_clk_div>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- }; +- }; +- +- target-module@90000 { /* 0x48090000, ap 55 12.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x91fe0 0x4>, +- <0x91fe4 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- ; +- /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ +- clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x90000 0x2000>; +- +- rng: rng@0 { +- compatible = "ti,omap4-rng"; +- reg = <0x0 0x2000>; +- interrupts = ; +- clocks = <&l3_iclk_div>; +- clock-names = "fck"; +- }; +- }; +- +- target-module@98000 { /* 0x48098000, ap 47 08.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x98000 0x4>, +- <0x98010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x98000 0x1000>; +- +- mcspi1: spi@0 { +- compatible = "ti,omap4-mcspi"; +- reg = <0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,spi-num-cs = <4>; +- dmas = <&sdma_xbar 35>, +- <&sdma_xbar 36>, +- <&sdma_xbar 37>, +- <&sdma_xbar 38>, +- <&sdma_xbar 39>, +- <&sdma_xbar 40>, +- <&sdma_xbar 41>, +- <&sdma_xbar 42>; +- dma-names = "tx0", "rx0", "tx1", "rx1", +- "tx2", "rx2", "tx3", "rx3"; +- status = "disabled"; +- }; +- }; +- +- target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x9a000 0x4>, +- <0x9a010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x9a000 0x1000>; +- +- mcspi2: spi@0 { +- compatible = "ti,omap4-mcspi"; +- reg = <0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,spi-num-cs = <2>; +- dmas = <&sdma_xbar 43>, +- <&sdma_xbar 44>, +- <&sdma_xbar 45>, +- <&sdma_xbar 46>; +- dma-names = "tx0", "rx0", "tx1", "rx1"; +- status = "disabled"; +- }; +- }; +- +- target-module@9c000 { /* 0x4809c000, ap 51 38.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x9c000 0x4>, +- <0x9c010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ +- clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x9c000 0x1000>; +- +- mmc1: mmc@0 { +- compatible = "ti,dra7-sdhci"; +- reg = <0x0 0x400>; +- interrupts = ; +- status = "disabled"; +- pbias-supply = <&pbias_mmc_reg>; +- max-frequency = <192000000>; +- mmc-ddr-1_8v; +- mmc-ddr-3_3v; +- }; +- }; +- +- target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa2000 0x1000>; +- }; +- +- target-module@a4000 { /* 0x480a4000, ap 57 42.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x000a4000 0x00001000>, +- <0x00001000 0x000a5000 0x00001000>; +- }; +- +- des_target: target-module@a5000 { /* 0x480a5000 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xa5030 0x4>, +- <0xa5034 0x4>, +- <0xa5038 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ +- clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xa5000 0x00001000>; +- +- des: des@0 { +- compatible = "ti,omap4-des"; +- reg = <0 0xa0>; +- interrupts = ; +- dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; +- dma-names = "tx", "rx"; +- clocks = <&l3_iclk_div>; +- clock-names = "fck"; +- }; +- }; +- +- target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa8000 0x4000>; +- }; +- +- target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xad000 0x4>, +- <0xad010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xad000 0x1000>; +- +- mmc3: mmc@0 { +- compatible = "ti,dra7-sdhci"; +- reg = <0x0 0x400>; +- interrupts = ; +- status = "disabled"; +- /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ +- max-frequency = <64000000>; +- /* SDMA is not supported */ +- sdhci-caps-mask = <0x0 0x400000>; +- }; +- }; +- +- target-module@b2000 { /* 0x480b2000, ap 37 52.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xb2000 0x4>, +- <0xb2014 0x4>, +- <0xb2018 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,syss-mask = <1>; +- ti,no-reset-on-init; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xb2000 0x1000>; +- +- hdqw1w: 1w@0 { +- compatible = "ti,omap3-1w"; +- reg = <0x0 0x1000>; +- interrupts = ; +- }; +- }; +- +- target-module@b4000 { /* 0x480b4000, ap 65 40.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xb4000 0x4>, +- <0xb4010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ +- clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xb4000 0x1000>; +- +- mmc2: mmc@0 { +- compatible = "ti,dra7-sdhci"; +- reg = <0x0 0x400>; +- interrupts = ; +- status = "disabled"; +- max-frequency = <192000000>; +- /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */ +- sdhci-caps-mask = <0x7 0x0>; +- mmc-hs200-1_8v; +- mmc-ddr-1_8v; +- mmc-ddr-3_3v; +- }; +- }; +- +- target-module@b8000 { /* 0x480b8000, ap 67 48.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xb8000 0x4>, +- <0xb8010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xb8000 0x1000>; +- +- mcspi3: spi@0 { +- compatible = "ti,omap4-mcspi"; +- reg = <0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,spi-num-cs = <2>; +- dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; +- dma-names = "tx0", "rx0"; +- status = "disabled"; +- }; +- }; +- +- target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xba000 0x4>, +- <0xba010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xba000 0x1000>; +- +- mcspi4: spi@0 { +- compatible = "ti,omap4-mcspi"; +- reg = <0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,spi-num-cs = <1>; +- dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; +- dma-names = "tx0", "rx0"; +- status = "disabled"; +- }; +- }; +- +- target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xd1000 0x4>, +- <0xd1010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xd1000 0x1000>; +- +- mmc4: mmc@0 { +- compatible = "ti,dra7-sdhci"; +- reg = <0x0 0x400>; +- interrupts = ; +- status = "disabled"; +- max-frequency = <192000000>; +- /* SDMA is not supported */ +- sdhci-caps-mask = <0x0 0x400000>; +- }; +- }; +- +- target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xd5000 0x1000>; +- }; +- }; +- +- segment@200000 { /* 0x48200000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&l4_per2 { /* 0x48400000 */ +- compatible = "ti,dra7-l4-per2", "simple-pm-bus"; +- power-domains = <&prm_l4per>; +- clocks = <&l4per2_clkctrl DRA7_L4PER2_L4_PER2_CLKCTRL 0>; +- clock-names = "fck"; +- reg = <0x48400000 0x800>, +- <0x48400800 0x800>, +- <0x48401000 0x400>, +- <0x48401400 0x400>, +- <0x48401800 0x400>; +- reg-names = "ap", "la", "ia0", "ia1", "ia2"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */ +- <0x45800000 0x45800000 0x400000>, /* L3 data port */ +- <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ +- <0x46000000 0x46000000 0x400000>, /* L3 data port */ +- <0x48436000 0x48436000 0x400000>, /* L3 data port */ +- <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ +- <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ +- <0x48450000 0x48450000 0x400000>, /* L3 data port */ +- <0x48454000 0x48454000 0x400000>; /* L3 data port */ +- +- segment@0 { /* 0x48400000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ +- <0x00001000 0x00001000 0x000400>, /* ap 1 */ +- <0x00000800 0x00000800 0x000800>, /* ap 2 */ +- <0x00084000 0x00084000 0x004000>, /* ap 3 */ +- <0x00001400 0x00001400 0x000400>, /* ap 4 */ +- <0x00001800 0x00001800 0x000400>, /* ap 5 */ +- <0x00088000 0x00088000 0x001000>, /* ap 6 */ +- <0x0002c000 0x0002c000 0x001000>, /* ap 7 */ +- <0x0002d000 0x0002d000 0x001000>, /* ap 8 */ +- <0x00060000 0x00060000 0x002000>, /* ap 9 */ +- <0x00062000 0x00062000 0x001000>, /* ap 10 */ +- <0x00064000 0x00064000 0x002000>, /* ap 11 */ +- <0x00066000 0x00066000 0x001000>, /* ap 12 */ +- <0x00068000 0x00068000 0x002000>, /* ap 13 */ +- <0x0006a000 0x0006a000 0x001000>, /* ap 14 */ +- <0x0006c000 0x0006c000 0x002000>, /* ap 15 */ +- <0x0006e000 0x0006e000 0x001000>, /* ap 16 */ +- <0x00036000 0x00036000 0x001000>, /* ap 17 */ +- <0x00037000 0x00037000 0x001000>, /* ap 18 */ +- <0x00070000 0x00070000 0x002000>, /* ap 19 */ +- <0x00072000 0x00072000 0x001000>, /* ap 20 */ +- <0x0003a000 0x0003a000 0x001000>, /* ap 21 */ +- <0x0003b000 0x0003b000 0x001000>, /* ap 22 */ +- <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ +- <0x0003d000 0x0003d000 0x001000>, /* ap 24 */ +- <0x0003e000 0x0003e000 0x001000>, /* ap 25 */ +- <0x0003f000 0x0003f000 0x001000>, /* ap 26 */ +- <0x00040000 0x00040000 0x001000>, /* ap 27 */ +- <0x00041000 0x00041000 0x001000>, /* ap 28 */ +- <0x00042000 0x00042000 0x001000>, /* ap 29 */ +- <0x00043000 0x00043000 0x001000>, /* ap 30 */ +- <0x00080000 0x00080000 0x002000>, /* ap 31 */ +- <0x00082000 0x00082000 0x001000>, /* ap 32 */ +- <0x0004a000 0x0004a000 0x001000>, /* ap 33 */ +- <0x0004b000 0x0004b000 0x001000>, /* ap 34 */ +- <0x00074000 0x00074000 0x002000>, /* ap 35 */ +- <0x00076000 0x00076000 0x001000>, /* ap 36 */ +- <0x00050000 0x00050000 0x001000>, /* ap 37 */ +- <0x00051000 0x00051000 0x001000>, /* ap 38 */ +- <0x00078000 0x00078000 0x002000>, /* ap 39 */ +- <0x0007a000 0x0007a000 0x001000>, /* ap 40 */ +- <0x00054000 0x00054000 0x001000>, /* ap 41 */ +- <0x00055000 0x00055000 0x001000>, /* ap 42 */ +- <0x0007c000 0x0007c000 0x002000>, /* ap 43 */ +- <0x0007e000 0x0007e000 0x001000>, /* ap 44 */ +- <0x0004c000 0x0004c000 0x001000>, /* ap 45 */ +- <0x0004d000 0x0004d000 0x001000>, /* ap 46 */ +- <0x00020000 0x00020000 0x001000>, /* ap 47 */ +- <0x00021000 0x00021000 0x001000>, /* ap 48 */ +- <0x00022000 0x00022000 0x001000>, /* ap 49 */ +- <0x00023000 0x00023000 0x001000>, /* ap 50 */ +- <0x00024000 0x00024000 0x001000>, /* ap 51 */ +- <0x00025000 0x00025000 0x001000>, /* ap 52 */ +- <0x00046000 0x00046000 0x001000>, /* ap 53 */ +- <0x00047000 0x00047000 0x001000>, /* ap 54 */ +- <0x00048000 0x00048000 0x001000>, /* ap 55 */ +- <0x00049000 0x00049000 0x001000>, /* ap 56 */ +- <0x00058000 0x00058000 0x002000>, /* ap 57 */ +- <0x0005a000 0x0005a000 0x001000>, /* ap 58 */ +- <0x0005b000 0x0005b000 0x001000>, /* ap 59 */ +- <0x0005c000 0x0005c000 0x001000>, /* ap 60 */ +- <0x0005d000 0x0005d000 0x001000>, /* ap 61 */ +- <0x0005e000 0x0005e000 0x001000>, /* ap 62 */ +- <0x45800000 0x45800000 0x400000>, /* L3 data port */ +- <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ +- <0x46000000 0x46000000 0x400000>, /* L3 data port */ +- <0x48436000 0x48436000 0x400000>, /* L3 data port */ +- <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ +- <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ +- <0x48450000 0x48450000 0x400000>, /* L3 data port */ +- <0x48454000 0x48454000 0x400000>; /* L3 data port */ +- +- target-module@20000 { /* 0x48420000, ap 47 02.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x20050 0x4>, +- <0x20054 0x4>, +- <0x20058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ +- clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x20000 0x1000>; +- +- uart7: serial@0 { +- compatible = "ti,dra742-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- status = "disabled"; +- }; +- }; +- +- target-module@22000 { /* 0x48422000, ap 49 0a.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x22050 0x4>, +- <0x22054 0x4>, +- <0x22058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ +- clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x22000 0x1000>; +- +- uart8: serial@0 { +- compatible = "ti,dra742-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- status = "disabled"; +- }; +- }; +- +- target-module@24000 { /* 0x48424000, ap 51 12.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x24050 0x4>, +- <0x24054 0x4>, +- <0x24058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ +- clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x24000 0x1000>; +- +- uart9: serial@0 { +- compatible = "ti,dra742-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- status = "disabled"; +- }; +- }; +- +- target-module@2c000 { /* 0x4842c000, ap 7 18.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2c000 0x1000>; +- }; +- +- target-module@36000 { /* 0x48436000, ap 17 06.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x36000 0x1000>; +- }; +- +- target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3a000 0x1000>; +- }; +- +- atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x3c000 0x4>; +- reg-names = "rev"; +- clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3c000 0x1000>; +- +- atl: atl@0 { +- compatible = "ti,dra7-atl"; +- reg = <0x0 0x3ff>; +- ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, +- <&atl_clkin2_ck>, <&atl_clkin3_ck>; +- clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- }; +- +- target-module@3e000 { /* 0x4843e000, ap 25 30.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x3e000 0x4>, +- <0x3e004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ +- clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3e000 0x1000>; +- +- epwmss0: epwmss@0 { +- compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; +- reg = <0x0 0x30>; +- #address-cells = <1>; +- #size-cells = <1>; +- status = "disabled"; +- ranges = <0 0 0x1000>; +- +- ecap0: pwm@100 { +- compatible = "ti,dra746-ecap", +- "ti,am3352-ecap"; +- #pwm-cells = <3>; +- reg = <0x100 0x80>; +- clocks = <&l4_root_clk_div>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- +- ehrpwm0: pwm@200 { +- compatible = "ti,dra746-ehrpwm", +- "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x200 0x80>; +- clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; +- clock-names = "tbclk", "fck"; +- status = "disabled"; +- }; +- }; +- }; +- +- target-module@40000 { /* 0x48440000, ap 27 38.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x40000 0x4>, +- <0x40004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ +- clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x40000 0x1000>; +- +- epwmss1: epwmss@0 { +- compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; +- reg = <0x0 0x30>; +- #address-cells = <1>; +- #size-cells = <1>; +- status = "disabled"; +- ranges = <0 0 0x1000>; +- +- ecap1: pwm@100 { +- compatible = "ti,dra746-ecap", +- "ti,am3352-ecap"; +- #pwm-cells = <3>; +- reg = <0x100 0x80>; +- clocks = <&l4_root_clk_div>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- +- ehrpwm1: pwm@200 { +- compatible = "ti,dra746-ehrpwm", +- "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x200 0x80>; +- clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; +- clock-names = "tbclk", "fck"; +- status = "disabled"; +- }; +- }; +- }; +- +- target-module@42000 { /* 0x48442000, ap 29 20.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x42000 0x4>, +- <0x42004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ +- clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x42000 0x1000>; +- +- epwmss2: epwmss@0 { +- compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; +- reg = <0x0 0x30>; +- #address-cells = <1>; +- #size-cells = <1>; +- status = "disabled"; +- ranges = <0 0 0x1000>; +- +- ecap2: pwm@100 { +- compatible = "ti,dra746-ecap", +- "ti,am3352-ecap"; +- #pwm-cells = <3>; +- reg = <0x100 0x80>; +- clocks = <&l4_root_clk_div>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- +- ehrpwm2: pwm@200 { +- compatible = "ti,dra746-ehrpwm", +- "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x200 0x80>; +- clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; +- clock-names = "tbclk", "fck"; +- status = "disabled"; +- }; +- }; +- }; +- +- target-module@46000 { /* 0x48446000, ap 53 40.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x46000 0x1000>; +- }; +- +- target-module@48000 { /* 0x48448000, ap 55 48.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x48000 0x1000>; +- }; +- +- target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4a000 0x1000>; +- }; +- +- target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4c000 0x1000>; +- }; +- +- target-module@50000 { /* 0x48450000, ap 37 24.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x50000 0x1000>; +- }; +- +- target-module@54000 { /* 0x48454000, ap 41 2c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x54000 0x1000>; +- }; +- +- target-module@58000 { /* 0x48458000, ap 57 28.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x58000 0x2000>; +- }; +- +- target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5b000 0x1000>; +- }; +- +- target-module@5d000 { /* 0x4845d000, ap 61 22.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5d000 0x1000>; +- }; +- +- target-module@60000 { /* 0x48460000, ap 9 0e.0 */ +- compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; +- reg = <0x60000 0x4>, +- <0x60004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ +- clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, +- <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, +- <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; +- clock-names = "fck", "ahclkx", "ahclkr"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x60000 0x2000>, +- <0x45800000 0x45800000 0x400000>; +- +- mcasp1: mcasp@0 { +- compatible = "ti,dra7-mcasp-audio"; +- reg = <0x0 0x2000>, +- <0x45800000 0x1000>; /* L3 data port */ +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; +- dma-names = "tx", "rx"; +- clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, +- <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, +- <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; +- clock-names = "fck", "ahclkx", "ahclkr"; +- status = "disabled"; +- }; +- }; +- +- target-module@64000 { /* 0x48464000, ap 11 1e.0 */ +- compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; +- reg = <0x64000 0x4>, +- <0x64004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ +- clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, +- <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, +- <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; +- clock-names = "fck", "ahclkx", "ahclkr"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x64000 0x2000>, +- <0x45c00000 0x45c00000 0x400000>; +- +- mcasp2: mcasp@0 { +- compatible = "ti,dra7-mcasp-audio"; +- reg = <0x0 0x2000>, +- <0x45c00000 0x1000>; /* L3 data port */ +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; +- dma-names = "tx", "rx"; +- clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, +- <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, +- <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; +- clock-names = "fck", "ahclkx", "ahclkr"; +- status = "disabled"; +- }; +- }; +- +- target-module@68000 { /* 0x48468000, ap 13 26.0 */ +- compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; +- reg = <0x68000 0x4>, +- <0x68004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ +- clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, +- <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; +- clock-names = "fck", "ahclkx"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x68000 0x2000>, +- <0x46000000 0x46000000 0x400000>; +- +- mcasp3: mcasp@0 { +- compatible = "ti,dra7-mcasp-audio"; +- reg = <0x0 0x2000>, +- <0x46000000 0x1000>; /* L3 data port */ +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; +- dma-names = "tx", "rx"; +- clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, +- <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; +- clock-names = "fck", "ahclkx"; +- status = "disabled"; +- }; +- }; +- +- target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */ +- compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; +- reg = <0x6c000 0x4>, +- <0x6c004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ +- clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, +- <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; +- clock-names = "fck", "ahclkx"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6c000 0x2000>, +- <0x48436000 0x48436000 0x400000>; +- +- mcasp4: mcasp@0 { +- compatible = "ti,dra7-mcasp-audio"; +- reg = <0x0 0x2000>, +- <0x48436000 0x1000>; /* L3 data port */ +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; +- dma-names = "tx", "rx"; +- clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, +- <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; +- clock-names = "fck", "ahclkx"; +- status = "disabled"; +- }; +- }; +- +- target-module@70000 { /* 0x48470000, ap 19 36.0 */ +- compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; +- reg = <0x70000 0x4>, +- <0x70004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ +- clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, +- <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; +- clock-names = "fck", "ahclkx"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x70000 0x2000>, +- <0x4843a000 0x4843a000 0x400000>; +- +- mcasp5: mcasp@0 { +- compatible = "ti,dra7-mcasp-audio"; +- reg = <0x0 0x2000>, +- <0x4843a000 0x1000>; /* L3 data port */ +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; +- dma-names = "tx", "rx"; +- clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, +- <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; +- clock-names = "fck", "ahclkx"; +- status = "disabled"; +- }; +- }; +- +- target-module@74000 { /* 0x48474000, ap 35 14.0 */ +- compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; +- reg = <0x74000 0x4>, +- <0x74004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ +- clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, +- <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; +- clock-names = "fck", "ahclkx"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x74000 0x2000>, +- <0x4844c000 0x4844c000 0x400000>; +- +- mcasp6: mcasp@0 { +- compatible = "ti,dra7-mcasp-audio"; +- reg = <0x0 0x2000>, +- <0x4844c000 0x1000>; /* L3 data port */ +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; +- dma-names = "tx", "rx"; +- clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, +- <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; +- clock-names = "fck", "ahclkx"; +- status = "disabled"; +- }; +- }; +- +- target-module@78000 { /* 0x48478000, ap 39 0c.0 */ +- compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; +- reg = <0x78000 0x4>, +- <0x78004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ +- clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, +- <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; +- clock-names = "fck", "ahclkx"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x78000 0x2000>, +- <0x48450000 0x48450000 0x400000>; +- +- mcasp7: mcasp@0 { +- compatible = "ti,dra7-mcasp-audio"; +- reg = <0x0 0x2000>, +- <0x48450000 0x1000>; /* L3 data port */ +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; +- dma-names = "tx", "rx"; +- clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, +- <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; +- clock-names = "fck", "ahclkx"; +- status = "disabled"; +- }; +- }; +- +- target-module@7c000 { /* 0x4847c000, ap 43 04.0 */ +- compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; +- reg = <0x7c000 0x4>, +- <0x7c004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ +- clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, +- <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; +- clock-names = "fck", "ahclkx"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x7c000 0x2000>, +- <0x48454000 0x48454000 0x400000>; +- +- mcasp8: mcasp@0 { +- compatible = "ti,dra7-mcasp-audio"; +- reg = <0x0 0x2000>, +- <0x48454000 0x1000>; /* L3 data port */ +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; +- dma-names = "tx", "rx"; +- clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, +- <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; +- clock-names = "fck", "ahclkx"; +- status = "disabled"; +- }; +- }; +- +- target-module@80000 { /* 0x48480000, ap 31 16.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x80020 0x4>; +- reg-names = "rev"; +- clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x80000 0x2000>; +- +- dcan2: can@0 { +- compatible = "ti,dra7-d_can"; +- reg = <0x0 0x2000>; +- syscon-raminit = <&scm_conf 0x558 1>; +- interrupts = ; +- clocks = <&sys_clkin1>; +- status = "disabled"; +- }; +- }; +- +- target-module@84000 { /* 0x48484000, ap 3 10.0 */ +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- reg = <0x85200 0x4>, +- <0x85208 0x4>, +- <0x85204 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <0>; +- ti,sysc-midle = , +- ; +- ti,sysc-sidle = , +- ; +- ti,syss-mask = <1>; +- clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x84000 0x4000>; +- /* +- * Do not allow gating of cpsw clock as workaround +- * for errata i877. Keeping internal clock disabled +- * causes the device switching characteristics +- * to degrade over time and eventually fail to meet +- * the data manual delay time/skew specs. +- */ +- ti,no-idle; +- +- mac_sw: switch@0 { +- compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch"; +- reg = <0x0 0x4000>; +- ranges = <0 0 0x4000>; +- clocks = <&gmac_main_clk>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- syscon = <&scm_conf>; +- status = "disabled"; +- +- interrupts = , +- , +- , +- ; +- interrupt-names = "rx_thresh", "rx", "tx", "misc"; +- +- ethernet-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpsw_port1: port@1 { +- reg = <1>; +- label = "port1"; +- mac-address = [ 00 00 00 00 00 00 ]; +- phys = <&phy_gmii_sel 1>; +- }; +- +- cpsw_port2: port@2 { +- reg = <2>; +- label = "port2"; +- mac-address = [ 00 00 00 00 00 00 ]; +- phys = <&phy_gmii_sel 2>; +- }; +- }; +- +- davinci_mdio_sw: mdio@1000 { +- compatible = "ti,cpsw-mdio","ti,davinci_mdio"; +- clocks = <&gmac_main_clk>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <0>; +- bus_freq = <1000000>; +- reg = <0x1000 0x100>; +- }; +- +- cpts { +- clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; +- clock-names = "cpts"; +- }; +- }; +- }; +- }; +-}; +- +-&l4_per3 { /* 0x48800000 */ +- compatible = "ti,dra7-l4-per3", "simple-pm-bus"; +- power-domains = <&prm_l4per>; +- clocks = <&l4per3_clkctrl DRA7_L4PER3_L4_PER3_CLKCTRL 0>; +- clock-names = "fck"; +- reg = <0x48800000 0x800>, +- <0x48800800 0x800>, +- <0x48801000 0x400>, +- <0x48801400 0x400>, +- <0x48801800 0x400>; +- reg-names = "ap", "la", "ia0", "ia1", "ia2"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */ +- +- segment@0 { /* 0x48800000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ +- <0x00000800 0x00000800 0x000800>, /* ap 1 */ +- <0x00001000 0x00001000 0x000400>, /* ap 2 */ +- <0x00001400 0x00001400 0x000400>, /* ap 3 */ +- <0x00001800 0x00001800 0x000400>, /* ap 4 */ +- <0x00020000 0x00020000 0x001000>, /* ap 5 */ +- <0x00021000 0x00021000 0x001000>, /* ap 6 */ +- <0x00022000 0x00022000 0x001000>, /* ap 7 */ +- <0x00023000 0x00023000 0x001000>, /* ap 8 */ +- <0x00024000 0x00024000 0x001000>, /* ap 9 */ +- <0x00025000 0x00025000 0x001000>, /* ap 10 */ +- <0x00026000 0x00026000 0x001000>, /* ap 11 */ +- <0x00027000 0x00027000 0x001000>, /* ap 12 */ +- <0x00028000 0x00028000 0x001000>, /* ap 13 */ +- <0x00029000 0x00029000 0x001000>, /* ap 14 */ +- <0x0002a000 0x0002a000 0x001000>, /* ap 15 */ +- <0x0002b000 0x0002b000 0x001000>, /* ap 16 */ +- <0x0002c000 0x0002c000 0x001000>, /* ap 17 */ +- <0x0002d000 0x0002d000 0x001000>, /* ap 18 */ +- <0x0002e000 0x0002e000 0x001000>, /* ap 19 */ +- <0x0002f000 0x0002f000 0x001000>, /* ap 20 */ +- <0x00170000 0x00170000 0x010000>, /* ap 21 */ +- <0x00180000 0x00180000 0x001000>, /* ap 22 */ +- <0x00190000 0x00190000 0x010000>, /* ap 23 */ +- <0x001a0000 0x001a0000 0x001000>, /* ap 24 */ +- <0x001b0000 0x001b0000 0x010000>, /* ap 25 */ +- <0x001c0000 0x001c0000 0x001000>, /* ap 26 */ +- <0x001d0000 0x001d0000 0x010000>, /* ap 27 */ +- <0x001e0000 0x001e0000 0x001000>, /* ap 28 */ +- <0x00038000 0x00038000 0x001000>, /* ap 29 */ +- <0x00039000 0x00039000 0x001000>, /* ap 30 */ +- <0x0005c000 0x0005c000 0x001000>, /* ap 31 */ +- <0x0005d000 0x0005d000 0x001000>, /* ap 32 */ +- <0x0003a000 0x0003a000 0x001000>, /* ap 33 */ +- <0x0003b000 0x0003b000 0x001000>, /* ap 34 */ +- <0x0003c000 0x0003c000 0x001000>, /* ap 35 */ +- <0x0003d000 0x0003d000 0x001000>, /* ap 36 */ +- <0x0003e000 0x0003e000 0x001000>, /* ap 37 */ +- <0x0003f000 0x0003f000 0x001000>, /* ap 38 */ +- <0x00040000 0x00040000 0x001000>, /* ap 39 */ +- <0x00041000 0x00041000 0x001000>, /* ap 40 */ +- <0x00042000 0x00042000 0x001000>, /* ap 41 */ +- <0x00043000 0x00043000 0x001000>, /* ap 42 */ +- <0x00044000 0x00044000 0x001000>, /* ap 43 */ +- <0x00045000 0x00045000 0x001000>, /* ap 44 */ +- <0x00046000 0x00046000 0x001000>, /* ap 45 */ +- <0x00047000 0x00047000 0x001000>, /* ap 46 */ +- <0x00048000 0x00048000 0x001000>, /* ap 47 */ +- <0x00049000 0x00049000 0x001000>, /* ap 48 */ +- <0x0004a000 0x0004a000 0x001000>, /* ap 49 */ +- <0x0004b000 0x0004b000 0x001000>, /* ap 50 */ +- <0x0004c000 0x0004c000 0x001000>, /* ap 51 */ +- <0x0004d000 0x0004d000 0x001000>, /* ap 52 */ +- <0x0004e000 0x0004e000 0x001000>, /* ap 53 */ +- <0x0004f000 0x0004f000 0x001000>, /* ap 54 */ +- <0x00050000 0x00050000 0x001000>, /* ap 55 */ +- <0x00051000 0x00051000 0x001000>, /* ap 56 */ +- <0x00052000 0x00052000 0x001000>, /* ap 57 */ +- <0x00053000 0x00053000 0x001000>, /* ap 58 */ +- <0x00054000 0x00054000 0x001000>, /* ap 59 */ +- <0x00055000 0x00055000 0x001000>, /* ap 60 */ +- <0x00056000 0x00056000 0x001000>, /* ap 61 */ +- <0x00057000 0x00057000 0x001000>, /* ap 62 */ +- <0x00058000 0x00058000 0x001000>, /* ap 63 */ +- <0x00059000 0x00059000 0x001000>, /* ap 64 */ +- <0x0005a000 0x0005a000 0x001000>, /* ap 65 */ +- <0x0005b000 0x0005b000 0x001000>, /* ap 66 */ +- <0x00064000 0x00064000 0x001000>, /* ap 67 */ +- <0x00065000 0x00065000 0x001000>, /* ap 68 */ +- <0x0005e000 0x0005e000 0x001000>, /* ap 69 */ +- <0x0005f000 0x0005f000 0x001000>, /* ap 70 */ +- <0x00060000 0x00060000 0x001000>, /* ap 71 */ +- <0x00061000 0x00061000 0x001000>, /* ap 72 */ +- <0x00062000 0x00062000 0x001000>, /* ap 73 */ +- <0x00063000 0x00063000 0x001000>, /* ap 74 */ +- <0x00140000 0x00140000 0x020000>, /* ap 75 */ +- <0x00160000 0x00160000 0x001000>, /* ap 76 */ +- <0x00016000 0x00016000 0x001000>, /* ap 77 */ +- <0x00017000 0x00017000 0x001000>, /* ap 78 */ +- <0x000c0000 0x000c0000 0x020000>, /* ap 79 */ +- <0x000e0000 0x000e0000 0x001000>, /* ap 80 */ +- <0x00004000 0x00004000 0x001000>, /* ap 81 */ +- <0x00005000 0x00005000 0x001000>, /* ap 82 */ +- <0x00080000 0x00080000 0x020000>, /* ap 83 */ +- <0x000a0000 0x000a0000 0x001000>, /* ap 84 */ +- <0x00100000 0x00100000 0x020000>, /* ap 85 */ +- <0x00120000 0x00120000 0x001000>, /* ap 86 */ +- <0x00010000 0x00010000 0x001000>, /* ap 87 */ +- <0x00011000 0x00011000 0x001000>, /* ap 88 */ +- <0x0000a000 0x0000a000 0x001000>, /* ap 89 */ +- <0x0000b000 0x0000b000 0x001000>, /* ap 90 */ +- <0x0001c000 0x0001c000 0x001000>, /* ap 91 */ +- <0x0001d000 0x0001d000 0x001000>, /* ap 92 */ +- <0x0001e000 0x0001e000 0x001000>, /* ap 93 */ +- <0x0001f000 0x0001f000 0x001000>, /* ap 94 */ +- <0x00002000 0x00002000 0x001000>, /* ap 95 */ +- <0x00003000 0x00003000 0x001000>; /* ap 96 */ +- +- target-module@2000 { /* 0x48802000, ap 95 7c.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x2000 0x4>, +- <0x2010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ +- clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2000 0x1000>; +- +- mailbox13: mailbox@0 { +- compatible = "ti,omap4-mailbox"; +- reg = <0x0 0x200>; +- interrupts = , +- , +- , +- ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <12>; +- status = "disabled"; +- }; +- }; +- +- target-module@4000 { /* 0x48804000, ap 81 20.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4000 0x1000>; +- }; +- +- target-module@a000 { /* 0x4880a000, ap 89 18.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa000 0x1000>; +- }; +- +- target-module@10000 { /* 0x48810000, ap 87 28.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10000 0x1000>; +- }; +- +- target-module@16000 { /* 0x48816000, ap 77 1e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x16000 0x1000>; +- }; +- +- target-module@1c000 { /* 0x4881c000, ap 91 1c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1c000 0x1000>; +- }; +- +- target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1e000 0x1000>; +- }; +- +- target-module@20000 { /* 0x48820000, ap 5 08.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x20000 0x4>, +- <0x20010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ +- clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x20000 0x1000>; +- +- timer5: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>, <&timer_sys_clk_div>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- }; +- }; +- +- target-module@22000 { /* 0x48822000, ap 7 24.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x22000 0x4>, +- <0x22010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ +- clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x22000 0x1000>; +- +- timer6: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>, <&timer_sys_clk_div>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- }; +- }; +- +- target-module@24000 { /* 0x48824000, ap 9 26.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x24000 0x4>, +- <0x24010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ +- clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x24000 0x1000>; +- +- timer7: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>, <&timer_sys_clk_div>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- }; +- }; +- +- target-module@26000 { /* 0x48826000, ap 11 0c.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x26000 0x4>, +- <0x26010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ +- clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x26000 0x1000>; +- +- timer8: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>, <&timer_sys_clk_div>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- }; +- }; +- +- target-module@28000 { /* 0x48828000, ap 13 16.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x28000 0x4>, +- <0x28010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ +- clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x28000 0x1000>; +- +- timer13: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>, <&timer_sys_clk_div>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-pwm; +- }; +- }; +- +- target-module@2a000 { /* 0x4882a000, ap 15 10.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x2a000 0x4>, +- <0x2a010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ +- clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2a000 0x1000>; +- +- timer14: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>, <&timer_sys_clk_div>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-pwm; +- }; +- }; +- +- target-module@2c000 { /* 0x4882c000, ap 17 02.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x2c000 0x4>, +- <0x2c010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ +- clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2c000 0x1000>; +- +- timer15: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>, <&timer_sys_clk_div>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-pwm; +- }; +- }; +- +- target-module@2e000 { /* 0x4882e000, ap 19 14.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x2e000 0x4>, +- <0x2e010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ +- clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2e000 0x1000>; +- +- timer16: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>, <&timer_sys_clk_div>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-pwm; +- }; +- }; +- +- rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */ +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- reg = <0x38074 0x4>, +- <0x38078 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): rtc_pwrdm, rtc_clkdm */ +- clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x38000 0x1000>; +- +- rtc: rtc@0 { +- compatible = "ti,am3352-rtc"; +- reg = <0x0 0x100>; +- interrupts = , +- ; +- clocks = <&sys_32k_ck>; +- }; +- }; +- +- target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x3a000 0x4>, +- <0x3a010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ +- clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3a000 0x1000>; +- +- mailbox2: mailbox@0 { +- compatible = "ti,omap4-mailbox"; +- reg = <0x0 0x200>; +- interrupts = , +- , +- , +- ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <12>; +- status = "disabled"; +- }; +- }; +- +- target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x3c000 0x4>, +- <0x3c010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ +- clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3c000 0x1000>; +- +- mailbox3: mailbox@0 { +- compatible = "ti,omap4-mailbox"; +- reg = <0x0 0x200>; +- interrupts = , +- , +- , +- ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <12>; +- status = "disabled"; +- }; +- }; +- +- target-module@3e000 { /* 0x4883e000, ap 37 46.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x3e000 0x4>, +- <0x3e010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ +- clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3e000 0x1000>; +- +- mailbox4: mailbox@0 { +- compatible = "ti,omap4-mailbox"; +- reg = <0x0 0x200>; +- interrupts = , +- , +- , +- ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <12>; +- status = "disabled"; +- }; +- }; +- +- target-module@40000 { /* 0x48840000, ap 39 64.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x40000 0x4>, +- <0x40010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ +- clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x40000 0x1000>; +- +- mailbox5: mailbox@0 { +- compatible = "ti,omap4-mailbox"; +- reg = <0x0 0x200>; +- interrupts = , +- , +- , +- ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <12>; +- status = "disabled"; +- }; +- }; +- +- target-module@42000 { /* 0x48842000, ap 41 4e.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x42000 0x4>, +- <0x42010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ +- clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x42000 0x1000>; +- +- mailbox6: mailbox@0 { +- compatible = "ti,omap4-mailbox"; +- reg = <0x0 0x200>; +- interrupts = , +- , +- , +- ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <12>; +- status = "disabled"; +- }; +- }; +- +- target-module@44000 { /* 0x48844000, ap 43 42.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x44000 0x4>, +- <0x44010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ +- clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x44000 0x1000>; +- +- mailbox7: mailbox@0 { +- compatible = "ti,omap4-mailbox"; +- reg = <0x0 0x200>; +- interrupts = , +- , +- , +- ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <12>; +- status = "disabled"; +- }; +- }; +- +- target-module@46000 { /* 0x48846000, ap 45 48.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x46000 0x4>, +- <0x46010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ +- clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x46000 0x1000>; +- +- mailbox8: mailbox@0 { +- compatible = "ti,omap4-mailbox"; +- reg = <0x0 0x200>; +- interrupts = , +- , +- , +- ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <12>; +- status = "disabled"; +- }; +- }; +- +- target-module@48000 { /* 0x48848000, ap 47 36.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x48000 0x1000>; +- }; +- +- target-module@4a000 { /* 0x4884a000, ap 49 38.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4a000 0x1000>; +- }; +- +- target-module@4c000 { /* 0x4884c000, ap 51 44.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4c000 0x1000>; +- }; +- +- target-module@4e000 { /* 0x4884e000, ap 53 4c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4e000 0x1000>; +- }; +- +- target-module@50000 { /* 0x48850000, ap 55 40.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x50000 0x1000>; +- }; +- +- target-module@52000 { /* 0x48852000, ap 57 54.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x52000 0x1000>; +- }; +- +- target-module@54000 { /* 0x48854000, ap 59 1a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x54000 0x1000>; +- }; +- +- target-module@56000 { /* 0x48856000, ap 61 22.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x56000 0x1000>; +- }; +- +- target-module@58000 { /* 0x48858000, ap 63 2a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x58000 0x1000>; +- }; +- +- target-module@5a000 { /* 0x4885a000, ap 65 5c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5a000 0x1000>; +- }; +- +- target-module@5c000 { /* 0x4885c000, ap 31 32.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5c000 0x1000>; +- }; +- +- target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x5e000 0x4>, +- <0x5e010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ +- clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5e000 0x1000>; +- +- mailbox9: mailbox@0 { +- compatible = "ti,omap4-mailbox"; +- reg = <0x0 0x200>; +- interrupts = , +- , +- , +- ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <12>; +- status = "disabled"; +- }; +- }; +- +- target-module@60000 { /* 0x48860000, ap 71 4a.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x60000 0x4>, +- <0x60010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ +- clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x60000 0x1000>; +- +- mailbox10: mailbox@0 { +- compatible = "ti,omap4-mailbox"; +- reg = <0x0 0x200>; +- interrupts = , +- , +- , +- ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <12>; +- status = "disabled"; +- }; +- }; +- +- target-module@62000 { /* 0x48862000, ap 73 74.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x62000 0x4>, +- <0x62010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ +- clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x62000 0x1000>; +- +- mailbox11: mailbox@0 { +- compatible = "ti,omap4-mailbox"; +- reg = <0x0 0x200>; +- interrupts = , +- , +- , +- ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <12>; +- status = "disabled"; +- }; +- }; +- +- target-module@64000 { /* 0x48864000, ap 67 52.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x64000 0x4>, +- <0x64010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ +- clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x64000 0x1000>; +- +- mailbox12: mailbox@0 { +- compatible = "ti,omap4-mailbox"; +- reg = <0x0 0x200>; +- interrupts = , +- , +- , +- ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <12>; +- status = "disabled"; +- }; +- }; +- +- target-module@80000 { /* 0x48880000, ap 83 0e.1 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x80000 0x4>, +- <0x80010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ +- clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x80000 0x20000>; +- +- omap_dwc3_1: omap_dwc3_1@0 { +- compatible = "ti,dwc3"; +- reg = <0x0 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <1>; +- utmi-mode = <2>; +- ranges = <0 0 0x20000>; +- +- usb1: usb@10000 { +- compatible = "snps,dwc3"; +- reg = <0x10000 0x17000>; +- interrupts = , +- , +- ; +- interrupt-names = "peripheral", +- "host", +- "otg"; +- phys = <&usb2_phy1>, <&usb3_phy1>; +- phy-names = "usb2-phy", "usb3-phy"; +- maximum-speed = "super-speed"; +- dr_mode = "otg"; +- snps,dis_u3_susphy_quirk; +- snps,dis_u2_susphy_quirk; +- }; +- }; +- }; +- +- target-module@c0000 { /* 0x488c0000, ap 79 06.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xc0000 0x4>, +- <0xc0010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ +- clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc0000 0x20000>; +- +- omap_dwc3_2: omap_dwc3_2@0 { +- compatible = "ti,dwc3"; +- reg = <0x0 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <1>; +- utmi-mode = <2>; +- ranges = <0 0 0x20000>; +- +- usb2: usb@10000 { +- compatible = "snps,dwc3"; +- reg = <0x10000 0x17000>; +- interrupts = , +- , +- ; +- interrupt-names = "peripheral", +- "host", +- "otg"; +- phys = <&usb2_phy2>; +- phy-names = "usb2-phy"; +- maximum-speed = "high-speed"; +- dr_mode = "otg"; +- snps,dis_u3_susphy_quirk; +- snps,dis_u2_susphy_quirk; +- snps,dis_metastability_quirk; +- }; +- }; +- }; +- +- usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x100000 0x4>, +- <0x100010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ +- clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x100000 0x20000>; +- +- omap_dwc3_3: omap_dwc3_3@0 { +- compatible = "ti,dwc3"; +- reg = <0x0 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <1>; +- utmi-mode = <2>; +- ranges = <0 0 0x20000>; +- status = "disabled"; +- +- usb3: usb@10000 { +- compatible = "snps,dwc3"; +- reg = <0x10000 0x17000>; +- interrupts = , +- , +- ; +- interrupt-names = "peripheral", +- "host", +- "otg"; +- maximum-speed = "high-speed"; +- dr_mode = "otg"; +- snps,dis_u3_susphy_quirk; +- snps,dis_u2_susphy_quirk; +- }; +- }; +- }; +- +- target-module@170000 { /* 0x48970000, ap 21 0a.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x170010 0x4>; +- reg-names = "sysc"; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x170000 0x10000>; +- status = "disabled"; +- }; +- +- target-module@190000 { /* 0x48990000, ap 23 2e.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x190010 0x4>; +- reg-names = "sysc"; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x190000 0x10000>; +- status = "disabled"; +- }; +- +- target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x1b0000 0x4>, +- <0x1b0010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1b0000 0x10000>; +- status = "disabled"; +- }; +- +- target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x1d0010 0x4>; +- reg-names = "sysc"; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1d0000 0x10000>; +- +- vpe: vpe@0 { +- compatible = "ti,dra7-vpe"; +- reg = <0x0000 0x120>, +- <0x0700 0x80>, +- <0x5700 0x18>, +- <0xd000 0x400>; +- reg-names = "vpe_top", +- "sc", +- "csc", +- "vpdma"; +- interrupts = ; +- }; +- }; +- }; +-}; +- +-&l4_wkup { /* 0x4ae00000 */ +- compatible = "ti,dra7-l4-wkup", "simple-pm-bus"; +- power-domains = <&prm_wkupaon>; +- clocks = <&wkupaon_clkctrl DRA7_WKUPAON_L4_WKUP_CLKCTRL 0>; +- clock-names = "fck"; +- reg = <0x4ae00000 0x800>, +- <0x4ae00800 0x800>, +- <0x4ae01000 0x1000>; +- reg-names = "ap", "la", "ia0"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ +- <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ +- <0x00020000 0x4ae20000 0x010000>, /* segment 2 */ +- <0x00030000 0x4ae30000 0x010000>; /* segment 3 */ +- +- segment@0 { /* 0x4ae00000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ +- <0x00001000 0x00001000 0x001000>, /* ap 1 */ +- <0x00000800 0x00000800 0x000800>, /* ap 2 */ +- <0x00006000 0x00006000 0x002000>, /* ap 3 */ +- <0x00008000 0x00008000 0x001000>, /* ap 4 */ +- <0x00004000 0x00004000 0x001000>, /* ap 15 */ +- <0x00005000 0x00005000 0x001000>, /* ap 16 */ +- <0x0000c000 0x0000c000 0x001000>, /* ap 17 */ +- <0x0000d000 0x0000d000 0x001000>; /* ap 18 */ +- +- target-module@4000 { /* 0x4ae04000, ap 15 40.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4000 0x4>, +- <0x4010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ +- clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4000 0x1000>; +- +- counter32k: counter@0 { +- compatible = "ti,omap-counter32k"; +- reg = <0x0 0x40>; +- }; +- }; +- +- target-module@6000 { /* 0x4ae06000, ap 3 10.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x6000 0x4>; +- reg-names = "rev"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6000 0x2000>; +- +- prm: prm@0 { +- compatible = "ti,dra7-prm", "simple-bus"; +- reg = <0 0x3000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x3000>; +- +- prm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- prm_clockdomains: clockdomains { +- }; +- }; +- }; +- +- target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xc000 0x4>; +- reg-names = "rev"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc000 0x1000>; +- +- scm_wkup: scm_conf@0 { +- compatible = "syscon"; +- reg = <0 0x1000>; +- }; +- }; +- }; +- +- segment@10000 { /* 0x4ae10000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ +- <0x00001000 0x00011000 0x001000>, /* ap 6 */ +- <0x00004000 0x00014000 0x001000>, /* ap 7 */ +- <0x00005000 0x00015000 0x001000>, /* ap 8 */ +- <0x00008000 0x00018000 0x001000>, /* ap 9 */ +- <0x00009000 0x00019000 0x001000>, /* ap 10 */ +- <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ +- <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ +- +- target-module@0 { /* 0x4ae10000, ap 5 20.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x0 0x4>, +- <0x10 0x4>, +- <0x114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ +- clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>, +- <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1000>; +- +- gpio1: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@4000 { /* 0x4ae14000, ap 7 28.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4000 0x4>, +- <0x4010 0x4>, +- <0x4014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ +- clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4000 0x1000>; +- +- wdt2: wdt@0 { +- compatible = "ti,omap3-wdt"; +- reg = <0x0 0x80>; +- interrupts = ; +- }; +- }; +- +- timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 30.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x8000 0x4>, +- <0x8010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ +- clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x8000 0x1000>; +- +- timer1: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; +- clock-names = "fck"; +- interrupts = ; +- ti,timer-alwon; +- }; +- }; +- +- target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc000 0x1000>; +- }; +- }; +- +- segment@20000 { /* 0x4ae20000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ +- <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ +- <0x00000000 0x00020000 0x001000>, /* ap 19 */ +- <0x00001000 0x00021000 0x001000>, /* ap 20 */ +- <0x00002000 0x00022000 0x001000>, /* ap 21 */ +- <0x00003000 0x00023000 0x001000>, /* ap 22 */ +- <0x00007000 0x00027000 0x000400>, /* ap 23 */ +- <0x00008000 0x00028000 0x000800>, /* ap 24 */ +- <0x00009000 0x00029000 0x000100>, /* ap 25 */ +- <0x00008800 0x00028800 0x000200>, /* ap 26 */ +- <0x00008a00 0x00028a00 0x000100>, /* ap 27 */ +- <0x0000b000 0x0002b000 0x001000>, /* ap 28 */ +- <0x0000c000 0x0002c000 0x001000>, /* ap 29 */ +- <0x0000f000 0x0002f000 0x001000>; /* ap 32 */ +- +- target-module@0 { /* 0x4ae20000, ap 19 08.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x0 0x4>, +- <0x10 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ +- clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1000>; +- +- timer12: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- interrupts = ; +- ti,timer-alwon; +- ti,timer-secure; +- }; +- }; +- +- target-module@2000 { /* 0x4ae22000, ap 21 18.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2000 0x1000>; +- }; +- +- target-module@6000 { /* 0x4ae26000, ap 13 48.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00006000 0x00001000>, +- <0x00001000 0x00007000 0x00000400>, +- <0x00002000 0x00008000 0x00000800>, +- <0x00002800 0x00008800 0x00000200>, +- <0x00002a00 0x00008a00 0x00000100>, +- <0x00003000 0x00009000 0x00000100>; +- }; +- +- target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xb050 0x4>, +- <0xb054 0x4>, +- <0xb058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ +- clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xb000 0x1000>; +- +- uart10: serial@0 { +- compatible = "ti,dra742-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- status = "disabled"; +- }; +- }; +- +- target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf000 0x1000>; +- }; +- }; +- +- segment@30000 { /* 0x4ae30000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */ +- <0x0000e000 0x0003e000 0x001000>, /* ap 31 */ +- <0x00000000 0x00030000 0x001000>, /* ap 33 */ +- <0x00001000 0x00031000 0x001000>, /* ap 34 */ +- <0x00002000 0x00032000 0x001000>, /* ap 35 */ +- <0x00003000 0x00033000 0x001000>, /* ap 36 */ +- <0x00004000 0x00034000 0x001000>, /* ap 37 */ +- <0x00005000 0x00035000 0x001000>, /* ap 38 */ +- <0x00006000 0x00036000 0x001000>, /* ap 39 */ +- <0x00007000 0x00037000 0x001000>, /* ap 40 */ +- <0x00008000 0x00038000 0x001000>, /* ap 41 */ +- <0x00009000 0x00039000 0x001000>, /* ap 42 */ +- <0x0000a000 0x0003a000 0x001000>; /* ap 43 */ +- +- target-module@1000 { /* 0x4ae31000, ap 34 60.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1000 0x1000>; +- }; +- +- target-module@3000 { /* 0x4ae33000, ap 36 0a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3000 0x1000>; +- }; +- +- target-module@5000 { /* 0x4ae35000, ap 38 0c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5000 0x1000>; +- }; +- +- target-module@7000 { /* 0x4ae37000, ap 40 68.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x7000 0x1000>; +- }; +- +- target-module@9000 { /* 0x4ae39000, ap 42 70.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x9000 0x1000>; +- }; +- +- target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xc020 0x4>; +- reg-names = "rev"; +- clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc000 0x2000>; +- +- dcan1: can@0 { +- compatible = "ti,dra7-d_can"; +- reg = <0x0 0x2000>; +- syscon-raminit = <&scm_conf 0x558 0>; +- interrupts = ; +- clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>; +- status = "disabled"; +- }; +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/dra7-mmc-iodelay.dtsi b/scripts/dtc/include-prefixes/arm/dra7-mmc-iodelay.dtsi +deleted file mode 100644 +index aa0947266526..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra7-mmc-iodelay.dtsi ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * MMC IOdelay values for TI's DRA7xx SoCs. +- * Copyright (C) 2018 Texas Instruments +- * Author: Kishon Vijay Abraham I +- */ +- +-&dra7_pmx_core { +- mmc1_pins_default_no_clk_pu: mmc1_pins_default_no_clk_pu { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra7.dtsi b/scripts/dtc/include-prefixes/arm/dra7.dtsi +deleted file mode 100644 +index dfc1ef8ef6ae..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra7.dtsi ++++ /dev/null +@@ -1,1339 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * Based on "omap4.dtsi" +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#define MAX_SOURCES 400 +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- +- compatible = "ti,dra7xx"; +- interrupt-parent = <&crossbar_mpu>; +- chosen { }; +- +- aliases { +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- i2c3 = &i2c4; +- i2c4 = &i2c5; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- serial4 = &uart5; +- serial5 = &uart6; +- serial6 = &uart7; +- serial7 = &uart8; +- serial8 = &uart9; +- serial9 = &uart10; +- ethernet0 = &cpsw_port1; +- ethernet1 = &cpsw_port2; +- d_can0 = &dcan1; +- d_can1 = &dcan2; +- spi0 = &qspi; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- status = "disabled"; /* See ARM architected timer wrap erratum i940 */ +- interrupts = , +- , +- , +- ; +- interrupt-parent = <&gic>; +- }; +- +- gic: interrupt-controller@48211000 { +- compatible = "arm,cortex-a15-gic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x0 0x48211000 0x0 0x1000>, +- <0x0 0x48212000 0x0 0x2000>, +- <0x0 0x48214000 0x0 0x2000>, +- <0x0 0x48216000 0x0 0x2000>; +- interrupts = ; +- interrupt-parent = <&gic>; +- }; +- +- wakeupgen: interrupt-controller@48281000 { +- compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x0 0x48281000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0>; +- +- operating-points-v2 = <&cpu0_opp_table>; +- +- clocks = <&dpll_mpu_ck>; +- clock-names = "cpu"; +- +- clock-latency = <300000>; /* From omap-cpufreq driver */ +- +- /* cooling options */ +- #cooling-cells = <2>; /* min followed by max */ +- +- vbb-supply = <&abb_mpu>; +- }; +- }; +- +- cpu0_opp_table: opp-table { +- compatible = "operating-points-v2-ti-cpu"; +- syscon = <&scm_wkup>; +- +- opp_nom-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <1060000 850000 1150000>, +- <1060000 850000 1150000>; +- opp-supported-hw = <0xFF 0x01>; +- opp-suspend; +- }; +- +- opp_od-1176000000 { +- opp-hz = /bits/ 64 <1176000000>; +- opp-microvolt = <1160000 885000 1160000>, +- <1160000 885000 1160000>; +- +- opp-supported-hw = <0xFF 0x02>; +- }; +- +- opp_high@1500000000 { +- opp-hz = /bits/ 64 <1500000000>; +- opp-microvolt = <1210000 950000 1250000>, +- <1210000 950000 1250000>; +- opp-supported-hw = <0xFF 0x04>; +- }; +- }; +- +- /* +- * XXX: Use a flat representation of the SOC interconnect. +- * The real OMAP interconnect network is quite complex. +- * Since it will not bring real advantage to represent that in DT for +- * the moment, just use a fake OCP bus entry to represent the whole bus +- * hierarchy. +- */ +- ocp: ocp { +- compatible = "simple-pm-bus"; +- power-domains = <&prm_core>; +- clocks = <&l3main1_clkctrl DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL 0>, +- <&l3instr_clkctrl DRA7_L3INSTR_L3_MAIN_2_CLKCTRL 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x0 0xc0000000>; +- dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; +- +- l3-noc@44000000 { +- compatible = "ti,dra7-l3-noc"; +- reg = <0x44000000 0x1000>, +- <0x45000000 0x1000>; +- interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, +- <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- l4_cfg: interconnect@4a000000 { +- }; +- l4_wkup: interconnect@4ae00000 { +- }; +- l4_per1: interconnect@48000000 { +- }; +- +- target-module@48210000 { +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- power-domains = <&prm_mpu>; +- clocks = <&mpu_clkctrl DRA7_MPU_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x48210000 0x1f0000>; +- +- mpu { +- compatible = "ti,omap5-mpu"; +- }; +- }; +- +- l4_per2: interconnect@48400000 { +- }; +- l4_per3: interconnect@48800000 { +- }; +- +- /* +- * Register access seems to have complex dependencies and also +- * seems to need an enabled phy. See the TRM chapter for "Table +- * 26-678. Main Sequence PCIe Controller Global Initialization" +- * and also dra7xx_pcie_probe(). +- */ +- axi0: target-module@51000000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- power-domains = <&prm_l3init>; +- resets = <&prm_l3init 0>; +- reset-names = "rstctrl"; +- clocks = <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 0>, +- <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>, +- <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>; +- clock-names = "fck", "phy-clk", "phy-clk-div"; +- #size-cells = <1>; +- #address-cells = <1>; +- ranges = <0x51000000 0x51000000 0x3000>, +- <0x20000000 0x20000000 0x10000000>; +- dma-ranges; +- /** +- * To enable PCI endpoint mode, disable the pcie1_rc +- * node and enable pcie1_ep mode. +- */ +- pcie1_rc: pcie@51000000 { +- reg = <0x51000000 0x2000>, +- <0x51002000 0x14c>, +- <0x20001000 0x2000>; +- reg-names = "rc_dbics", "ti_conf", "config"; +- interrupts = <0 232 0x4>, <0 233 0x4>; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x81000000 0 0x00000000 0x20003000 0 0x00010000>, +- <0x82000000 0 0x20013000 0x20013000 0 0x0ffed000>; +- bus-range = <0x00 0xff>; +- #interrupt-cells = <1>; +- num-lanes = <1>; +- linux,pci-domain = <0>; +- phys = <&pcie1_phy>; +- phy-names = "pcie-phy0"; +- ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie1_intc 1>, +- <0 0 0 2 &pcie1_intc 2>, +- <0 0 0 3 &pcie1_intc 3>, +- <0 0 0 4 &pcie1_intc 4>; +- ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; +- status = "disabled"; +- pcie1_intc: interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- }; +- }; +- +- pcie1_ep: pcie_ep@51000000 { +- reg = <0x51000000 0x28>, +- <0x51002000 0x14c>, +- <0x51001000 0x28>, +- <0x20001000 0x10000000>; +- reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; +- interrupts = <0 232 0x4>; +- num-lanes = <1>; +- num-ib-windows = <4>; +- num-ob-windows = <16>; +- phys = <&pcie1_phy>; +- phy-names = "pcie-phy0"; +- ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; +- ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; +- status = "disabled"; +- }; +- }; +- +- /* +- * Register access seems to have complex dependencies and also +- * seems to need an enabled phy. See the TRM chapter for "Table +- * 26-678. Main Sequence PCIe Controller Global Initialization" +- * and also dra7xx_pcie_probe(). +- */ +- axi1: target-module@51800000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- clocks = <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 0>, +- <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>, +- <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>; +- clock-names = "fck", "phy-clk", "phy-clk-div"; +- power-domains = <&prm_l3init>; +- resets = <&prm_l3init 1>; +- reset-names = "rstctrl"; +- #size-cells = <1>; +- #address-cells = <1>; +- ranges = <0x51800000 0x51800000 0x3000>, +- <0x30000000 0x30000000 0x10000000>; +- dma-ranges; +- status = "disabled"; +- pcie2_rc: pcie@51800000 { +- reg = <0x51800000 0x2000>, +- <0x51802000 0x14c>, +- <0x30001000 0x2000>; +- reg-names = "rc_dbics", "ti_conf", "config"; +- interrupts = <0 355 0x4>, <0 356 0x4>; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>, +- <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>; +- bus-range = <0x00 0xff>; +- #interrupt-cells = <1>; +- num-lanes = <1>; +- linux,pci-domain = <1>; +- phys = <&pcie2_phy>; +- phy-names = "pcie-phy0"; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie2_intc 1>, +- <0 0 0 2 &pcie2_intc 2>, +- <0 0 0 3 &pcie2_intc 3>, +- <0 0 0 4 &pcie2_intc 4>; +- ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; +- pcie2_intc: interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- }; +- }; +- }; +- +- ocmcram1: ocmcram@40300000 { +- compatible = "mmio-sram"; +- reg = <0x40300000 0x80000>; +- ranges = <0x0 0x40300000 0x80000>; +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * This is a placeholder for an optional reserved +- * region for use by secure software. The size +- * of this region is not known until runtime so it +- * is set as zero to either be updated to reserve +- * space or left unchanged to leave all SRAM for use. +- * On HS parts that that require the reserved region +- * either the bootloader can update the size to +- * the required amount or the node can be overridden +- * from the board dts file for the secure platform. +- */ +- sram-hs@0 { +- compatible = "ti,secure-ram"; +- reg = <0x0 0x0>; +- }; +- }; +- +- /* +- * NOTE: ocmcram2 and ocmcram3 are not available on all +- * DRA7xx and AM57xx variants. Confirm availability in +- * the data manual for the exact part number in use +- * before enabling these nodes in the board dts file. +- */ +- ocmcram2: ocmcram@40400000 { +- status = "disabled"; +- compatible = "mmio-sram"; +- reg = <0x40400000 0x100000>; +- ranges = <0x0 0x40400000 0x100000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- ocmcram3: ocmcram@40500000 { +- status = "disabled"; +- compatible = "mmio-sram"; +- reg = <0x40500000 0x100000>; +- ranges = <0x0 0x40500000 0x100000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- bandgap: bandgap@4a0021e0 { +- reg = <0x4a0021e0 0xc +- 0x4a00232c 0xc +- 0x4a002380 0x2c +- 0x4a0023C0 0x3c +- 0x4a002564 0x8 +- 0x4a002574 0x50>; +- compatible = "ti,dra752-bandgap"; +- interrupts = ; +- #thermal-sensor-cells = <1>; +- }; +- +- dsp1_system: dsp_system@40d00000 { +- compatible = "syscon"; +- reg = <0x40d00000 0x100>; +- }; +- +- dra7_iodelay_core: padconf@4844a000 { +- compatible = "ti,dra7-iodelay"; +- reg = <0x4844a000 0x0d1c>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <2>; +- }; +- +- target-module@43300000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x43300000 0x4>, +- <0x43300010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x43300000 0x100000>; +- +- edma: dma@0 { +- compatible = "ti,edma3-tpcc"; +- reg = <0 0x100000>; +- reg-names = "edma3_cc"; +- interrupts = , +- , +- ; +- interrupt-names = "edma3_ccint", "edma3_mperr", +- "edma3_ccerrint"; +- dma-requests = <64>; +- #dma-cells = <2>; +- +- ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; +- +- /* +- * memcpy is disabled, can be enabled with: +- * ti,edma-memcpy-channels = <20 21>; +- * for example. Note that these channels need to be +- * masked in the xbar as well. +- */ +- }; +- }; +- +- target-module@43400000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x43400000 0x4>, +- <0x43400010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x43400000 0x100000>; +- +- edma_tptc0: dma@0 { +- compatible = "ti,edma3-tptc"; +- reg = <0 0x100000>; +- interrupts = ; +- interrupt-names = "edma3_tcerrint"; +- }; +- }; +- +- target-module@43500000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x43500000 0x4>, +- <0x43500010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x43500000 0x100000>; +- +- edma_tptc1: dma@0 { +- compatible = "ti,edma3-tptc"; +- reg = <0 0x100000>; +- interrupts = ; +- interrupt-names = "edma3_tcerrint"; +- }; +- }; +- +- target-module@4e000000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4e000000 0x4>, +- <0x4e000010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- ; +- ranges = <0x0 0x4e000000 0x2000000>; +- #size-cells = <1>; +- #address-cells = <1>; +- +- dmm@0 { +- compatible = "ti,omap5-dmm"; +- reg = <0 0x800>; +- interrupts = ; +- }; +- }; +- +- ipu1: ipu@58820000 { +- compatible = "ti,dra7-ipu"; +- reg = <0x58820000 0x10000>; +- reg-names = "l2ram"; +- iommus = <&mmu_ipu1>; +- status = "disabled"; +- resets = <&prm_ipu 0>, <&prm_ipu 1>; +- clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; +- firmware-name = "dra7-ipu1-fw.xem4"; +- }; +- +- ipu2: ipu@55020000 { +- compatible = "ti,dra7-ipu"; +- reg = <0x55020000 0x10000>; +- reg-names = "l2ram"; +- iommus = <&mmu_ipu2>; +- status = "disabled"; +- resets = <&prm_core 0>, <&prm_core 1>; +- clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; +- firmware-name = "dra7-ipu2-fw.xem4"; +- }; +- +- dsp1: dsp@40800000 { +- compatible = "ti,dra7-dsp"; +- reg = <0x40800000 0x48000>, +- <0x40e00000 0x8000>, +- <0x40f00000 0x8000>; +- reg-names = "l2ram", "l1pram", "l1dram"; +- ti,bootreg = <&scm_conf 0x55c 10>; +- iommus = <&mmu0_dsp1>, <&mmu1_dsp1>; +- status = "disabled"; +- resets = <&prm_dsp1 0>; +- clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; +- firmware-name = "dra7-dsp1-fw.xe66"; +- }; +- +- target-module@40d01000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x40d01000 0x4>, +- <0x40d01010 0x4>, +- <0x40d01014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; +- clock-names = "fck"; +- resets = <&prm_dsp1 1>; +- reset-names = "rstctrl"; +- ranges = <0x0 0x40d01000 0x1000>; +- #size-cells = <1>; +- #address-cells = <1>; +- +- mmu0_dsp1: mmu@0 { +- compatible = "ti,dra7-dsp-iommu"; +- reg = <0x0 0x100>; +- interrupts = ; +- #iommu-cells = <0>; +- ti,syscon-mmuconfig = <&dsp1_system 0x0>; +- }; +- }; +- +- target-module@40d02000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x40d02000 0x4>, +- <0x40d02010 0x4>, +- <0x40d02014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; +- clock-names = "fck"; +- resets = <&prm_dsp1 1>; +- reset-names = "rstctrl"; +- ranges = <0x0 0x40d02000 0x1000>; +- #size-cells = <1>; +- #address-cells = <1>; +- +- mmu1_dsp1: mmu@0 { +- compatible = "ti,dra7-dsp-iommu"; +- reg = <0x0 0x100>; +- interrupts = ; +- #iommu-cells = <0>; +- ti,syscon-mmuconfig = <&dsp1_system 0x1>; +- }; +- }; +- +- target-module@58882000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x58882000 0x4>, +- <0x58882010 0x4>, +- <0x58882014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; +- clock-names = "fck"; +- resets = <&prm_ipu 2>; +- reset-names = "rstctrl"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x58882000 0x100>; +- +- mmu_ipu1: mmu@0 { +- compatible = "ti,dra7-iommu"; +- reg = <0x0 0x100>; +- interrupts = ; +- #iommu-cells = <0>; +- ti,iommu-bus-err-back; +- }; +- }; +- +- target-module@55082000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x55082000 0x4>, +- <0x55082010 0x4>, +- <0x55082014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; +- clock-names = "fck"; +- resets = <&prm_core 2>; +- reset-names = "rstctrl"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x55082000 0x100>; +- +- mmu_ipu2: mmu@0 { +- compatible = "ti,dra7-iommu"; +- reg = <0x0 0x100>; +- interrupts = ; +- #iommu-cells = <0>; +- ti,iommu-bus-err-back; +- }; +- }; +- +- abb_mpu: regulator-abb-mpu { +- compatible = "ti,abb-v3"; +- regulator-name = "abb_mpu"; +- #address-cells = <0>; +- #size-cells = <0>; +- clocks = <&sys_clkin1>; +- ti,settling-time = <50>; +- ti,clock-cycles = <16>; +- +- reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, +- <0x4ae06014 0x4>, <0x4a003b20 0xc>, +- <0x4ae0c158 0x4>; +- reg-names = "setup-address", "control-address", +- "int-address", "efuse-address", +- "ldo-address"; +- ti,tranxdone-status-mask = <0x80>; +- /* LDOVBBMPU_FBB_MUX_CTRL */ +- ti,ldovbb-override-mask = <0x400>; +- /* LDOVBBMPU_FBB_VSET_OUT */ +- ti,ldovbb-vset-mask = <0x1F>; +- +- /* +- * NOTE: only FBB mode used but actual vset will +- * determine final biasing +- */ +- ti,abb_info = < +- /*uV ABB efuse rbb_m fbb_m vset_m*/ +- 1060000 0 0x0 0 0x02000000 0x01F00000 +- 1160000 0 0x4 0 0x02000000 0x01F00000 +- 1210000 0 0x8 0 0x02000000 0x01F00000 +- >; +- }; +- +- abb_ivahd: regulator-abb-ivahd { +- compatible = "ti,abb-v3"; +- regulator-name = "abb_ivahd"; +- #address-cells = <0>; +- #size-cells = <0>; +- clocks = <&sys_clkin1>; +- ti,settling-time = <50>; +- ti,clock-cycles = <16>; +- +- reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, +- <0x4ae06010 0x4>, <0x4a0025cc 0xc>, +- <0x4a002470 0x4>; +- reg-names = "setup-address", "control-address", +- "int-address", "efuse-address", +- "ldo-address"; +- ti,tranxdone-status-mask = <0x40000000>; +- /* LDOVBBIVA_FBB_MUX_CTRL */ +- ti,ldovbb-override-mask = <0x400>; +- /* LDOVBBIVA_FBB_VSET_OUT */ +- ti,ldovbb-vset-mask = <0x1F>; +- +- /* +- * NOTE: only FBB mode used but actual vset will +- * determine final biasing +- */ +- ti,abb_info = < +- /*uV ABB efuse rbb_m fbb_m vset_m*/ +- 1055000 0 0x0 0 0x02000000 0x01F00000 +- 1150000 0 0x4 0 0x02000000 0x01F00000 +- 1250000 0 0x8 0 0x02000000 0x01F00000 +- >; +- }; +- +- abb_dspeve: regulator-abb-dspeve { +- compatible = "ti,abb-v3"; +- regulator-name = "abb_dspeve"; +- #address-cells = <0>; +- #size-cells = <0>; +- clocks = <&sys_clkin1>; +- ti,settling-time = <50>; +- ti,clock-cycles = <16>; +- +- reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, +- <0x4ae06010 0x4>, <0x4a0025e0 0xc>, +- <0x4a00246c 0x4>; +- reg-names = "setup-address", "control-address", +- "int-address", "efuse-address", +- "ldo-address"; +- ti,tranxdone-status-mask = <0x20000000>; +- /* LDOVBBDSPEVE_FBB_MUX_CTRL */ +- ti,ldovbb-override-mask = <0x400>; +- /* LDOVBBDSPEVE_FBB_VSET_OUT */ +- ti,ldovbb-vset-mask = <0x1F>; +- +- /* +- * NOTE: only FBB mode used but actual vset will +- * determine final biasing +- */ +- ti,abb_info = < +- /*uV ABB efuse rbb_m fbb_m vset_m*/ +- 1055000 0 0x0 0 0x02000000 0x01F00000 +- 1150000 0 0x4 0 0x02000000 0x01F00000 +- 1250000 0 0x8 0 0x02000000 0x01F00000 +- >; +- }; +- +- abb_gpu: regulator-abb-gpu { +- compatible = "ti,abb-v3"; +- regulator-name = "abb_gpu"; +- #address-cells = <0>; +- #size-cells = <0>; +- clocks = <&sys_clkin1>; +- ti,settling-time = <50>; +- ti,clock-cycles = <16>; +- +- reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, +- <0x4ae06010 0x4>, <0x4a003b08 0xc>, +- <0x4ae0c154 0x4>; +- reg-names = "setup-address", "control-address", +- "int-address", "efuse-address", +- "ldo-address"; +- ti,tranxdone-status-mask = <0x10000000>; +- /* LDOVBBGPU_FBB_MUX_CTRL */ +- ti,ldovbb-override-mask = <0x400>; +- /* LDOVBBGPU_FBB_VSET_OUT */ +- ti,ldovbb-vset-mask = <0x1F>; +- +- /* +- * NOTE: only FBB mode used but actual vset will +- * determine final biasing +- */ +- ti,abb_info = < +- /*uV ABB efuse rbb_m fbb_m vset_m*/ +- 1090000 0 0x0 0 0x02000000 0x01F00000 +- 1210000 0 0x4 0 0x02000000 0x01F00000 +- 1280000 0 0x8 0 0x02000000 0x01F00000 +- >; +- }; +- +- target-module@4b300000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x4b300000 0x4>, +- <0x4b300010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- , +- ; +- clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4b300000 0x1000>, +- <0x5c000000 0x5c000000 0x4000000>; +- +- qspi: spi@0 { +- compatible = "ti,dra7xxx-qspi"; +- reg = <0 0x100>, +- <0x5c000000 0x4000000>; +- reg-names = "qspi_base", "qspi_mmap"; +- syscon-chipselects = <&scm_conf 0x558>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>; +- clock-names = "fck"; +- num-cs = <4>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- /* OCP2SCP1 */ +- /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ +- +- target-module@50000000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x50000000 4>, +- <0x50000010 4>, +- <0x50000014 4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- clocks = <&l3main1_clkctrl DRA7_L3MAIN1_GPMC_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ +- <0x00000000 0x00000000 0x40000000>; /* data */ +- +- gpmc: gpmc@50000000 { +- compatible = "ti,am3352-gpmc"; +- reg = <0x50000000 0x37c>; /* device IO registers */ +- interrupts = ; +- dmas = <&edma_xbar 4 0>; +- dma-names = "rxtx"; +- gpmc,num-cs = <8>; +- gpmc,num-waitpins = <2>; +- #address-cells = <2>; +- #size-cells = <1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- status = "disabled"; +- }; +- }; +- +- target-module@56000000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x5600fe00 0x4>, +- <0x5600fe10 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x56000000 0x2000000>; +- }; +- +- crossbar_mpu: crossbar@4a002a48 { +- compatible = "ti,irq-crossbar"; +- reg = <0x4a002a48 0x130>; +- interrupt-controller; +- interrupt-parent = <&wakeupgen>; +- #interrupt-cells = <3>; +- ti,max-irqs = <160>; +- ti,max-crossbar-sources = ; +- ti,reg-size = <2>; +- ti,irqs-reserved = <0 1 2 3 5 6 131 132>; +- ti,irqs-skip = <10 133 139 140>; +- ti,irqs-safe-map = <0>; +- }; +- +- target-module@58000000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x58000000 4>, +- <0x58000014 4>; +- reg-names = "rev", "syss"; +- ti,syss-mask = <1>; +- clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>, +- <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, +- <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>, +- <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 11>; +- clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x58000000 0x800000>; +- +- dss: dss@0 { +- compatible = "ti,dra7-dss"; +- /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ +- /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ +- status = "disabled"; +- /* CTRL_CORE_DSS_PLL_CONTROL */ +- syscon-pll-ctrl = <&scm_conf 0x538>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x800000>; +- +- target-module@1000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x1000 0x4>, +- <0x1010 0x4>, +- <0x1014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,syss-mask = <1>; +- clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1000 0x1000>; +- +- dispc@0 { +- compatible = "ti,dra7-dispc"; +- reg = <0 0x1000>; +- interrupts = ; +- clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; +- clock-names = "fck"; +- /* CTRL_CORE_SMA_SW_1 */ +- syscon-pol = <&scm_conf 0x534>; +- }; +- }; +- +- target-module@40000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x40000 0x4>, +- <0x40010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; +- clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, +- <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; +- clock-names = "fck", "dss_clk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x40000 0x40000>; +- +- hdmi: encoder@0 { +- compatible = "ti,dra7-hdmi"; +- reg = <0 0x200>, +- <0x200 0x80>, +- <0x300 0x80>, +- <0x20000 0x19000>; +- reg-names = "wp", "pll", "phy", "core"; +- interrupts = ; +- status = "disabled"; +- clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, +- <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>; +- clock-names = "fck", "sys_clk"; +- dmas = <&sdma_xbar 76>; +- dma-names = "audio_tx"; +- }; +- }; +- }; +- }; +- +- aes1_target: target-module@4b500000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4b500080 0x4>, +- <0x4b500084 0x4>, +- <0x4b500088 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4sec_clkdm */ +- clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4b500000 0x1000>; +- +- aes1: aes@0 { +- compatible = "ti,omap4-aes"; +- reg = <0 0xa0>; +- interrupts = ; +- dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; +- dma-names = "tx", "rx"; +- clocks = <&l3_iclk_div>; +- clock-names = "fck"; +- }; +- }; +- +- aes2_target: target-module@4b700000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4b700080 0x4>, +- <0x4b700084 0x4>, +- <0x4b700088 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): per_pwrdm, l4sec_clkdm */ +- clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4b700000 0x1000>; +- +- aes2: aes@0 { +- compatible = "ti,omap4-aes"; +- reg = <0 0xa0>; +- interrupts = ; +- dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; +- dma-names = "tx", "rx"; +- clocks = <&l3_iclk_div>; +- clock-names = "fck"; +- }; +- }; +- +- sham1_target: target-module@4b101000 { +- compatible = "ti,sysc-omap3-sham", "ti,sysc"; +- reg = <0x4b101100 0x4>, +- <0x4b101110 0x4>, +- <0x4b101114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ +- clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4b101000 0x1000>; +- +- sham1: sham@0 { +- compatible = "ti,omap5-sham"; +- reg = <0 0x300>; +- interrupts = ; +- dmas = <&edma_xbar 119 0>; +- dma-names = "rx"; +- clocks = <&l3_iclk_div>; +- clock-names = "fck"; +- }; +- }; +- +- sham2_target: target-module@42701000 { +- compatible = "ti,sysc-omap3-sham", "ti,sysc"; +- reg = <0x42701100 0x4>, +- <0x42701110 0x4>, +- <0x42701114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ +- clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x42701000 0x1000>; +- +- sham2: sham@0 { +- compatible = "ti,omap5-sham"; +- reg = <0 0x300>; +- interrupts = ; +- dmas = <&edma_xbar 165 0>; +- dma-names = "rx"; +- clocks = <&l3_iclk_div>; +- clock-names = "fck"; +- }; +- }; +- +- iva_hd_target: target-module@5a000000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x5a05a400 0x4>, +- <0x5a05a410 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- power-domains = <&prm_iva>; +- resets = <&prm_iva 2>; +- reset-names = "rstctrl"; +- clocks = <&iva_clkctrl DRA7_IVA_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x5a000000 0x5a000000 0x1000000>, +- <0x5b000000 0x5b000000 0x1000000>; +- +- iva { +- compatible = "ti,ivahd"; +- }; +- }; +- +- opp_supply_mpu: opp-supply@4a003b20 { +- compatible = "ti,omap5-opp-supply"; +- reg = <0x4a003b20 0xc>; +- ti,efuse-settings = < +- /* uV offset */ +- 1060000 0x0 +- 1160000 0x4 +- 1210000 0x8 +- >; +- ti,absolute-max-voltage-uv = <1500000>; +- }; +- +- }; +- +- thermal_zones: thermal-zones { +- #include "omap4-cpu-thermal.dtsi" +- #include "omap5-gpu-thermal.dtsi" +- #include "omap5-core-thermal.dtsi" +- #include "dra7-dspeve-thermal.dtsi" +- #include "dra7-iva-thermal.dtsi" +- }; +- +-}; +- +-&cpu_thermal { +- polling-delay = <500>; /* milliseconds */ +- coefficients = <0 2000>; +-}; +- +-&gpu_thermal { +- coefficients = <0 2000>; +-}; +- +-&core_thermal { +- coefficients = <0 2000>; +-}; +- +-&dspeve_thermal { +- coefficients = <0 2000>; +-}; +- +-&iva_thermal { +- coefficients = <0 2000>; +-}; +- +-&cpu_crit { +- temperature = <120000>; /* milli Celsius */ +-}; +- +-&core_crit { +- temperature = <120000>; /* milli Celsius */ +-}; +- +-&gpu_crit { +- temperature = <120000>; /* milli Celsius */ +-}; +- +-&dspeve_crit { +- temperature = <120000>; /* milli Celsius */ +-}; +- +-&iva_crit { +- temperature = <120000>; /* milli Celsius */ +-}; +- +-#include "dra7-l4.dtsi" +-#include "dra7xx-clocks.dtsi" +- +-&prm { +- prm_mpu: prm@300 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0x300 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_dsp1: prm@400 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0x400 0x100>; +- #reset-cells = <1>; +- #power-domain-cells = <0>; +- }; +- +- prm_ipu: prm@500 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0x500 0x100>; +- #reset-cells = <1>; +- #power-domain-cells = <0>; +- }; +- +- prm_coreaon: prm@628 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0x628 0xd8>; +- #power-domain-cells = <0>; +- }; +- +- prm_core: prm@700 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0x700 0x100>; +- #reset-cells = <1>; +- #power-domain-cells = <0>; +- }; +- +- prm_iva: prm@f00 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0xf00 0x100>; +- #reset-cells = <1>; +- #power-domain-cells = <0>; +- }; +- +- prm_cam: prm@1000 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1000 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_dss: prm@1100 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1100 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_gpu: prm@1200 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1200 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_l3init: prm@1300 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1300 0x100>; +- #reset-cells = <1>; +- #power-domain-cells = <0>; +- }; +- +- prm_l4per: prm@1400 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1400 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_custefuse: prm@1600 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1600 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_wkupaon: prm@1724 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1724 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_dsp2: prm@1b00 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1b00 0x40>; +- #reset-cells = <1>; +- #power-domain-cells = <0>; +- }; +- +- prm_eve1: prm@1b40 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1b40 0x40>; +- #power-domain-cells = <0>; +- }; +- +- prm_eve2: prm@1b80 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1b80 0x40>; +- #power-domain-cells = <0>; +- }; +- +- prm_eve3: prm@1bc0 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1bc0 0x40>; +- #power-domain-cells = <0>; +- }; +- +- prm_eve4: prm@1c00 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1c00 0x60>; +- #power-domain-cells = <0>; +- }; +- +- prm_rtc: prm@1c60 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1c60 0x20>; +- #power-domain-cells = <0>; +- }; +- +- prm_vpe: prm@1c80 { +- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1c80 0x80>; +- #power-domain-cells = <0>; +- }; +-}; +- +-/* Preferred always-on timer for clockevent */ +-&timer1_target { +- ti,no-reset-on-init; +- ti,no-idle; +- timer@0 { +- assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>; +- assigned-clock-parents = <&sys_32k_ck>; +- }; +-}; +- +-/* Local timers, see ARM architected timer wrap erratum i940 */ +-&timer3_target { +- ti,no-reset-on-init; +- ti,no-idle; +- timer@0 { +- assigned-clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>; +- assigned-clock-parents = <&timer_sys_clk_div>; +- }; +-}; +- +-&timer4_target { +- ti,no-reset-on-init; +- ti,no-idle; +- timer@0 { +- assigned-clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>; +- assigned-clock-parents = <&timer_sys_clk_div>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra71-evm.dts b/scripts/dtc/include-prefixes/arm/dra71-evm.dts +deleted file mode 100644 +index a64364443031..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra71-evm.dts ++++ /dev/null +@@ -1,316 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include "dra71x.dtsi" +-#include "dra7-mmc-iodelay.dtsi" +-#include "dra72x-mmc-iodelay.dtsi" +-#include +- +-/ { +- compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"; +- model = "TI DRA718 EVM"; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ipu2_memory_region: ipu2-memory@95800000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x95800000 0x0 0x3800000>; +- reusable; +- status = "okay"; +- }; +- +- dsp1_memory_region: dsp1-memory@99000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x99000000 0x0 0x4000000>; +- reusable; +- status = "okay"; +- }; +- +- ipu1_memory_region: ipu1-memory@9d000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x9d000000 0x0 0x2000000>; +- reusable; +- status = "okay"; +- }; +- }; +- +- vpo_sd_1v8_3v3: gpio-regulator-TPS74801 { +- compatible = "regulator-gpio"; +- +- regulator-name = "vddshv8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- vin-supply = <&evm_5v0>; +- +- gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; +- states = <1800000 0x0 +- 3300000 0x1>; +- }; +- +- evm_1v8_sw: fixedregulator-evm_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "evm_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&lp8732_buck0_reg>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- poweroff: gpio-poweroff { +- compatible = "gpio-poweroff"; +- gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>; +- input; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- lp8733: lp8733@60 { +- compatible = "ti,lp8733"; +- reg = <0x60>; +- +- buck0-in-supply =<&vsys_3v3>; +- buck1-in-supply =<&vsys_3v3>; +- ldo0-in-supply =<&evm_5v0>; +- ldo1-in-supply =<&evm_5v0>; +- +- lp8733_regulators: regulators { +- lp8733_buck0_reg: buck0 { +- /* FB_B0 -> LP8733-BUCK1 - VPO_S1_AVS - VDD_CORE_AVS (core, mpu, gpu) */ +- regulator-name = "lp8733-buck0"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- lp8733_buck1_reg: buck1 { +- /* FB_B1 -> LP8733-BUCK2 - VPO_S2_AVS - VDD_DSP_AVS (DSP/eve/iva) */ +- regulator-name = "lp8733-buck1"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- lp8733_ldo0_reg: ldo0 { +- /* LDO0 -> LP8733-LDO1 - VPO_L1_3V3 - VDDSHV8 (optional) */ +- regulator-name = "lp8733-ldo0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- lp8733_ldo1_reg: ldo1 { +- /* LDO1 -> LP8733-LDO2 - VPO_L2_3V3 - VDDA_USB3V3 */ +- regulator-name = "lp8733-ldo1"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +- +- lp8732: lp8732@61 { +- compatible = "ti,lp8732"; +- reg = <0x61>; +- +- buck0-in-supply =<&vsys_3v3>; +- buck1-in-supply =<&vsys_3v3>; +- ldo0-in-supply =<&vsys_3v3>; +- ldo1-in-supply =<&vsys_3v3>; +- +- lp8732_regulators: regulators { +- lp8732_buck0_reg: buck0 { +- /* FB_B0 -> LP8732-BUCK1 - VPO_S3_1V8 - VDDS_1V8 */ +- regulator-name = "lp8732-buck0"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- lp8732_buck1_reg: buck1 { +- /* FB_B1 -> LP8732-BUCK2 - VPO_S4_DDR - VDD_DDR_1V35 */ +- regulator-name = "lp8732-buck1"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- lp8732_ldo0_reg: ldo0 { +- /* LDO0 -> LP8732-LDO1 - VPO_L3_1V8 - VDA_1V8_PLL */ +- regulator-name = "lp8732-ldo0"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- lp8732_ldo1_reg: ldo1 { +- /* LDO1 -> LP8732-LDO2 - VPO_L4_1V8 - VDA_1V8_PHY */ +- regulator-name = "lp8732-ldo1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&pcf_lcd { +- interrupt-parent = <&gpio7>; +- interrupts = <31 IRQ_TYPE_EDGE_FALLING>; +-}; +- +-&pcf_gpio_21 { +- interrupt-parent = <&gpio7>; +- interrupts = <31 IRQ_TYPE_EDGE_FALLING>; +-}; +- +-&pcf_hdmi { +- hdmi-i2c-disable-hog { +- /* +- * PM_OEn to High: Disable routing I2C3 to PM_I2C +- * With this PM_SEL(p3) should not matter +- */ +- gpio-hog; +- gpios = <0 GPIO_ACTIVE_LOW>; +- output-high; +- line-name = "pm_oe_n"; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; +- pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; +- pinctrl-1 = <&mmc1_pins_hs>; +- pinctrl-2 = <&mmc1_pins_sdr12>; +- pinctrl-3 = <&mmc1_pins_sdr25>; +- pinctrl-4 = <&mmc1_pins_sdr50>; +- pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>; +- pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; +- vqmmc-supply = <&vpo_sd_1v8_3v3>; +-}; +- +-&mmc2 { +- pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; +- pinctrl-0 = <&mmc2_pins_default>; +- pinctrl-1 = <&mmc2_pins_hs>; +- pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; +- pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; +- vmmc-supply = <&evm_1v8_sw>; +- vqmmc-supply = <&evm_1v8_sw>; +-}; +- +-&mac_sw { +- mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, +- <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ +- <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ +- status = "okay"; +-}; +- +-&cpsw_port1 { +- phy-handle = <&dp83867_0>; +- phy-mode = "rgmii-id"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- phy-handle = <&dp83867_1>; +- phy-mode = "rgmii-id"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&davinci_mdio_sw { +- dp83867_0: ethernet-phy@2 { +- reg = <2>; +- ti,rx-internal-delay = ; +- ti,tx-internal-delay = ; +- ti,fifo-depth = ; +- ti,min-output-impedance; +- ti,dp83867-rxctrl-strap-quirk; +- }; +- +- dp83867_1: ethernet-phy@3 { +- reg = <3>; +- ti,rx-internal-delay = ; +- ti,tx-internal-delay = ; +- ti,fifo-depth = ; +- ti,min-output-impedance; +- ti,dp83867-rxctrl-strap-quirk; +- }; +-}; +- +-/* No Sata on this device */ +-&sata_phy { +- status = "disabled"; +-}; +- +-&sata { +- status = "disabled"; +-}; +- +-/* No RTC on this device */ +-&rtc { +- status = "disabled"; +-}; +- +-&usb2_phy1 { +- phy-supply = <&lp8733_ldo1_reg>; +-}; +- +-&usb2_phy2 { +- phy-supply = <&lp8733_ldo1_reg>; +-}; +- +-&dss { +- /* Supplied by VDA_1V8_PLL */ +- vdda_video-supply = <&lp8732_ldo0_reg>; +-}; +- +-&hdmi { +- /* Supplied by VDA_1V8_PHY */ +- vdda_video-supply = <&lp8732_ldo1_reg>; +-}; +- +-&extcon_usb1 { +- vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>; +-}; +- +-&extcon_usb2 { +- vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>; +-}; +- +-&ipu2 { +- status = "okay"; +- memory-region = <&ipu2_memory_region>; +-}; +- +-&ipu1 { +- status = "okay"; +- memory-region = <&ipu1_memory_region>; +-}; +- +-&dsp1 { +- status = "okay"; +- memory-region = <&dsp1_memory_region>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra71x.dtsi b/scripts/dtc/include-prefixes/arm/dra71x.dtsi +deleted file mode 100644 +index 9c270d8f75d5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra71x.dtsi ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* +- * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License version 2 as +- * published by the Free Software Foundation. +- */ +- +-#include "dra72-evm-common.dtsi" +- +-&rtctarget { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra72-evm-common.dtsi b/scripts/dtc/include-prefixes/arm/dra72-evm-common.dtsi +deleted file mode 100644 +index f12825268188..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra72-evm-common.dtsi ++++ /dev/null +@@ -1,593 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "dra72x.dtsi" +-#include "dra7-ipu-dsp-common.dtsi" +-#include +-#include +- +-/ { +- compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; +- +- aliases { +- display0 = &hdmi0; +- }; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- evm_12v0: fixedregulator-evm12v0 { +- /* main supply */ +- compatible = "regulator-fixed"; +- regulator-name = "evm_12v0"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- evm_5v0: fixedregulator-evm5v0 { +- /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */ +- /* Output 1 of LM5140QRWGTQ1 on dra71-evm */ +- compatible = "regulator-fixed"; +- regulator-name = "evm_5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&evm_12v0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- evm_3v6: fixedregulator-evm_3v6 { +- compatible = "regulator-fixed"; +- regulator-name = "evm_3v6"; +- regulator-min-microvolt = <3600000>; +- regulator-max-microvolt = <3600000>; +- vin-supply = <&evm_5v0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vsys_3v3: fixedregulator-vsys3v3 { +- /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */ +- /* Output 2 of LM5140QRWGTQ1 on dra71-evm */ +- compatible = "regulator-fixed"; +- regulator-name = "vsys_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&evm_12v0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- evm_3v3_sw: fixedregulator-evm_3v3 { +- /* TPS22965DSG */ +- compatible = "regulator-fixed"; +- regulator-name = "evm_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vsys_3v3>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- aic_dvdd: fixedregulator-aic_dvdd { +- /* TPS77018DBVT */ +- compatible = "regulator-fixed"; +- regulator-name = "aic_dvdd"; +- vin-supply = <&evm_3v3_sw>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- evm_3v3_sd: fixedregulator-sd { +- compatible = "regulator-fixed"; +- regulator-name = "evm_3v3_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&evm_3v3_sw>; +- enable-active-high; +- gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; +- }; +- +- extcon_usb1: extcon_usb1 { +- compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; +- }; +- +- extcon_usb2: extcon_usb2 { +- compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; +- }; +- +- hdmi0: connector { +- compatible = "hdmi-connector"; +- label = "hdmi"; +- +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&tpd12s015_out>; +- }; +- }; +- }; +- +- tpd12s015: encoder { +- compatible = "ti,tpd12s015"; +- +- gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ +- <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ +- <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tpd12s015_in: endpoint { +- remote-endpoint = <&hdmi_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- tpd12s015_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +- }; +- }; +- }; +- +- sound0: sound0 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "DRA7xx-EVM"; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack", +- "Line", "Line Out", +- "Microphone", "Mic Jack", +- "Line", "Line In"; +- simple-audio-card,routing = +- "Headphone Jack", "HPLOUT", +- "Headphone Jack", "HPROUT", +- "Line Out", "LLOUT", +- "Line Out", "RLOUT", +- "MIC3L", "Mic Jack", +- "MIC3R", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "LINE1L", "Line In", +- "LINE1R", "Line In"; +- simple-audio-card,format = "dsp_b"; +- simple-audio-card,bitclock-master = <&sound0_master>; +- simple-audio-card,frame-master = <&sound0_master>; +- simple-audio-card,bitclock-inversion; +- +- sound0_master: simple-audio-card,cpu { +- sound-dai = <&mcasp3>; +- system-clock-frequency = <5644800>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&tlv320aic3106>; +- clocks = <&atl_clkin2_ck>; +- }; +- }; +- +- vmmcwl_fixed: fixedregulator-mmcwl { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcwl_fixed"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- clk_ov5640_fixed: clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- }; +-}; +- +-&dra7_pmx_core { +- dcan1_pins_default: dcan1_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ +- DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ +- >; +- }; +- +- dcan1_pins_sleep: dcan1_pins_sleep { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ +- DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ +- >; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- pcf_lcd: gpio@20 { +- compatible = "nxp,pcf8575"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pcf_gpio_21: gpio@21 { +- compatible = "nxp,pcf8575"; +- reg = <0x21>; +- lines-initial-states = <0x1408>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- tlv320aic3106: tlv320aic3106@19 { +- #sound-dai-cells = <0>; +- compatible = "ti,tlv320aic3106"; +- reg = <0x19>; +- adc-settle-ms = <40>; +- ai3x-micbias-vg = <1>; /* 2.0V */ +- status = "okay"; +- +- /* Regulators */ +- AVDD-supply = <&evm_3v3_sw>; +- IOVDD-supply = <&evm_3v3_sw>; +- DRVDD-supply = <&evm_3v3_sw>; +- DVDD-supply = <&aic_dvdd>; +- }; +-}; +- +-&i2c5 { +- status = "okay"; +- clock-frequency = <400000>; +- +- pcf_hdmi: pcf8575@26 { +- compatible = "nxp,pcf8575"; +- reg = <0x26>; +- gpio-controller; +- #gpio-cells = <2>; +- /* +- * initial state is used here to keep the mdio interface +- * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and +- * VIN2_S0 driven high otherwise Ethernet stops working +- * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 +- */ +- lines-initial-states = <0x0f2b>; +- +- hdmi-audio-hog { +- /* vin6_sel_s0: high: VIN6, low: audio */ +- gpio-hog; +- gpios = <1 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "vin6_sel_s0"; +- }; +- }; +- +- ov5640@3c { +- compatible = "ovti,ov5640"; +- reg = <0x3c>; +- +- clocks = <&clk_ov5640_fixed>; +- clock-names = "xclk"; +- +- port { +- csi2_cam0: endpoint { +- remote-endpoint = <&csi2_phy0>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- }; +- }; +- }; +- +-}; +- +-&uart1 { +- status = "okay"; +- interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, +- <&dra7_pmx_core 0x3e0>; +-}; +- +-&elm { +- status = "okay"; +-}; +- +-&gpmc { +- /* +- * For the existing IOdelay configuration via U-Boot we don't +- * support NAND on dra72-evm. Keep it disabled. Enabling it +- * requires a different configuration by U-Boot. +- */ +- status = "disabled"; +- ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ +- nand@0,0 { +- /* To use NAND, DIP switch SW5 must be set like so: +- * SW5.1 (NAND_SELn) = ON (LOW) +- * SW5.9 (GPMC_WPN) = OFF (HIGH) +- */ +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* device IO registers */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ +- ti,nand-xfer-type = "prefetch-dma"; +- ti,nand-ecc-opt = "bch8"; +- ti,elm-id = <&elm>; +- nand-bus-width = <16>; +- gpmc,device-width = <2>; +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <80>; +- gpmc,cs-wr-off-ns = <80>; +- gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <60>; +- gpmc,adv-wr-off-ns = <60>; +- gpmc,we-on-ns = <10>; +- gpmc,we-off-ns = <50>; +- gpmc,oe-on-ns = <4>; +- gpmc,oe-off-ns = <40>; +- gpmc,access-ns = <40>; +- gpmc,wr-access-ns = <80>; +- gpmc,rd-cycle-ns = <80>; +- gpmc,wr-cycle-ns = <80>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-data-mux-bus-ns = <0>; +- /* MTD partition table */ +- /* All SPL-* partitions are sized to minimal length +- * which can be independently programmable. For +- * NAND flash this is equal to size of erase-block */ +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "NAND.SPL"; +- reg = <0x00000000 0x000020000>; +- }; +- partition@1 { +- label = "NAND.SPL.backup1"; +- reg = <0x00020000 0x00020000>; +- }; +- partition@2 { +- label = "NAND.SPL.backup2"; +- reg = <0x00040000 0x00020000>; +- }; +- partition@3 { +- label = "NAND.SPL.backup3"; +- reg = <0x00060000 0x00020000>; +- }; +- partition@4 { +- label = "NAND.u-boot-spl-os"; +- reg = <0x00080000 0x00040000>; +- }; +- partition@5 { +- label = "NAND.u-boot"; +- reg = <0x000c0000 0x00100000>; +- }; +- partition@6 { +- label = "NAND.u-boot-env"; +- reg = <0x001c0000 0x00020000>; +- }; +- partition@7 { +- label = "NAND.u-boot-env.backup1"; +- reg = <0x001e0000 0x00020000>; +- }; +- partition@8 { +- label = "NAND.kernel"; +- reg = <0x00200000 0x00800000>; +- }; +- partition@9 { +- label = "NAND.file-system"; +- reg = <0x00a00000 0x0f600000>; +- }; +- }; +-}; +- +-&omap_dwc3_1 { +- extcon = <&extcon_usb1>; +-}; +- +-&omap_dwc3_2 { +- extcon = <&extcon_usb2>; +-}; +- +-&usb1 { +- dr_mode = "otg"; +- extcon = <&extcon_usb1>; +-}; +- +-&usb2 { +- dr_mode = "host"; +- extcon = <&extcon_usb2>; +-}; +- +-&mmc1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins_default>; +- vmmc-supply = <&evm_3v3_sd>; +- bus-width = <4>; +- /* +- * SDCD signal is not being used here - using the fact that GPIO mode +- * is a viable alternative +- */ +- cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; +- max-frequency = <192000000>; +-}; +- +-&mmc2 { +- /* SW5-3 in ON position */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins_default>; +- bus-width = <8>; +- non-removable; +- max-frequency = <192000000>; +-}; +- +-&mmc4 { +- status = "okay"; +- vmmc-supply = <&evm_3v6>; +- vqmmc-supply = <&vmmcwl_fixed>; +- bus-width = <4>; +- cap-power-off-card; +- keep-power-in-suspend; +- non-removable; +- pinctrl-names = "default", "hs", "sdr12", "sdr25"; +- pinctrl-0 = <&mmc4_pins_default>; +- pinctrl-1 = <&mmc4_pins_default>; +- pinctrl-2 = <&mmc4_pins_default>; +- pinctrl-3 = <&mmc4_pins_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- wifi@2 { +- compatible = "ti,wl1835"; +- reg = <2>; +- interrupt-parent = <&gpio5>; +- interrupts = <7 IRQ_TYPE_EDGE_RISING>; +- }; +-}; +- +-&dcan1 { +- status = "okay"; +- pinctrl-names = "default", "sleep", "active"; +- pinctrl-0 = <&dcan1_pins_sleep>; +- pinctrl-1 = <&dcan1_pins_sleep>; +- pinctrl-2 = <&dcan1_pins_default>; +-}; +- +-&qspi { +- status = "okay"; +- +- spi-max-frequency = <76800000>; +- m25p80@0 { +- compatible = "s25fl256s1"; +- spi-max-frequency = <76800000>; +- reg = <0>; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* MTD partition table. +- * The ROM checks the first four physical blocks +- * for a valid file to boot and the flash here is +- * 64KiB block size. +- */ +- partition@0 { +- label = "QSPI.SPL"; +- reg = <0x00000000 0x000010000>; +- }; +- partition@1 { +- label = "QSPI.SPL.backup1"; +- reg = <0x00010000 0x00010000>; +- }; +- partition@2 { +- label = "QSPI.SPL.backup2"; +- reg = <0x00020000 0x00010000>; +- }; +- partition@3 { +- label = "QSPI.SPL.backup3"; +- reg = <0x00030000 0x00010000>; +- }; +- partition@4 { +- label = "QSPI.u-boot"; +- reg = <0x00040000 0x00100000>; +- }; +- partition@5 { +- label = "QSPI.u-boot-spl-os"; +- reg = <0x00140000 0x00080000>; +- }; +- partition@6 { +- label = "QSPI.u-boot-env"; +- reg = <0x001c0000 0x00010000>; +- }; +- partition@7 { +- label = "QSPI.u-boot-env.backup1"; +- reg = <0x001d0000 0x0010000>; +- }; +- partition@8 { +- label = "QSPI.kernel"; +- reg = <0x001e0000 0x0800000>; +- }; +- partition@9 { +- label = "QSPI.file-system"; +- reg = <0x009e0000 0x01620000>; +- }; +- }; +-}; +- +-&dss { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +- +- port { +- hdmi_out: endpoint { +- remote-endpoint = <&tpd12s015_in>; +- }; +- }; +-}; +- +-&atl { +- assigned-clocks = <&abe_dpll_sys_clk_mux>, +- <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>, +- <&dpll_abe_ck>, +- <&dpll_abe_m2x2_ck>, +- <&atl_clkin2_ck>; +- assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; +- assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; +- +- status = "okay"; +- +- atl2 { +- bws = ; +- aws = ; +- }; +-}; +- +-&mcasp3 { +- #sound-dai-cells = <0>; +- +- assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; +- assigned-clock-parents = <&atl_clkin2_ck>; +- +- status = "okay"; +- +- op-mode = <0>; /* MCASP_IIS_MODE */ +- tdm-slots = <2>; +- /* 4 serializer */ +- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ +- 1 2 0 0 +- >; +- tx-num-evt = <32>; +- rx-num-evt = <32>; +-}; +- +-&pcie1_rc { +- status = "okay"; +-}; +- +-&csi2_0 { +- csi2_phy0: endpoint { +- remote-endpoint = <&csi2_cam0>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra72-evm-revc.dts b/scripts/dtc/include-prefixes/arm/dra72-evm-revc.dts +deleted file mode 100644 +index f242b937f88c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra72-evm-revc.dts ++++ /dev/null +@@ -1,157 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-#include "dra72-evm-common.dtsi" +-#include "dra72x-mmc-iodelay.dtsi" +-#include +- +-/ { +- model = "TI DRA722 Rev C EVM"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ipu2_cma_pool: ipu2_cma@95800000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x95800000 0x0 0x3800000>; +- reusable; +- status = "okay"; +- }; +- +- dsp1_cma_pool: dsp1_cma@99000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x99000000 0x0 0x4000000>; +- reusable; +- status = "okay"; +- }; +- +- ipu1_cma_pool: ipu1_cma@9d000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x9d000000 0x0 0x2000000>; +- reusable; +- status = "okay"; +- }; +- }; +- +- evm_1v8_sw: fixedregulator-evm_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "evm_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&smps4_reg>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&i2c1 { +- tps65917: tps65917@58 { +- reg = <0x58>; +- +- interrupts = ; /* IRQ_SYS_1N */ +- }; +-}; +- +-#include "dra72-evm-tps65917.dtsi" +- +-&ldo2_reg { +- /* LDO2_OUT --> VDDA_1V8_PHY2 */ +- regulator-always-on; +- regulator-boot-on; +-}; +- +-&hdmi { +- vdda-supply = <&ldo2_reg>; +-}; +- +-&pcf_gpio_21 { +- interrupt-parent = <&gpio3>; +- interrupts = <30 IRQ_TYPE_EDGE_FALLING>; +-}; +- +-&mac_sw { +- mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, +- <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ +- <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ +- status = "okay"; +-}; +- +-&cpsw_port1 { +- phy-handle = <&dp83867_0>; +- phy-mode = "rgmii-id"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- phy-handle = <&dp83867_1>; +- phy-mode = "rgmii-id"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&davinci_mdio_sw { +- dp83867_0: ethernet-phy@2 { +- reg = <2>; +- ti,rx-internal-delay = ; +- ti,tx-internal-delay = ; +- ti,fifo-depth = ; +- ti,min-output-impedance; +- interrupt-parent = <&gpio6>; +- interrupts = <16 IRQ_TYPE_EDGE_FALLING>; +- ti,dp83867-rxctrl-strap-quirk; +- }; +- +- dp83867_1: ethernet-phy@3 { +- reg = <3>; +- ti,rx-internal-delay = ; +- ti,tx-internal-delay = ; +- ti,fifo-depth = ; +- ti,min-output-impedance; +- interrupt-parent = <&gpio6>; +- interrupts = <16 IRQ_TYPE_EDGE_FALLING>; +- ti,dp83867-rxctrl-strap-quirk; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; +- pinctrl-0 = <&mmc1_pins_default>; +- pinctrl-1 = <&mmc1_pins_hs>; +- pinctrl-2 = <&mmc1_pins_sdr12>; +- pinctrl-3 = <&mmc1_pins_sdr25>; +- pinctrl-4 = <&mmc1_pins_sdr50>; +- pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>; +- pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; +- vqmmc-supply = <&ldo1_reg>; +-}; +- +-&mmc2 { +- pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; +- pinctrl-0 = <&mmc2_pins_default>; +- pinctrl-1 = <&mmc2_pins_hs>; +- pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; +- pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; +- vmmc-supply = <&evm_1v8_sw>; +-}; +- +-&ipu2 { +- status = "okay"; +- memory-region = <&ipu2_cma_pool>; +-}; +- +-&ipu1 { +- status = "okay"; +- memory-region = <&ipu1_cma_pool>; +-}; +- +-&dsp1 { +- status = "okay"; +- memory-region = <&dsp1_cma_pool>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra72-evm-tps65917.dtsi b/scripts/dtc/include-prefixes/arm/dra72-evm-tps65917.dtsi +deleted file mode 100644 +index 7b433f549239..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra72-evm-tps65917.dtsi ++++ /dev/null +@@ -1,151 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/* +- * Integrated Power Management Chip +- * https://www.ti.com/lit/ds/symlink/tps65917-q1.pdf +- */ +- +-&tps65917 { +- compatible = "ti,tps65917"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- ti,system-power-controller; +- +- tps65917_pmic { +- compatible = "ti,tps65917-pmic"; +- +- smps1-in-supply = <&vsys_3v3>; +- smps2-in-supply = <&vsys_3v3>; +- smps3-in-supply = <&vsys_3v3>; +- smps4-in-supply = <&vsys_3v3>; +- smps5-in-supply = <&vsys_3v3>; +- ldo1-in-supply = <&vsys_3v3>; +- ldo2-in-supply = <&vsys_3v3>; +- ldo3-in-supply = <&vsys_3v3>; +- ldo4-in-supply = <&evm_5v0>; +- ldo5-in-supply = <&vsys_3v3>; +- +- tps65917_regulators: regulators { +- smps1_reg: smps1 { +- /* VDD_MPU */ +- regulator-name = "smps1"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps2_reg: smps2 { +- /* VDD_CORE */ +- regulator-name = "smps2"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- smps3_reg: smps3 { +- /* VDD_GPU IVA DSPEVE */ +- regulator-name = "smps3"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- smps4_reg: smps4 { +- /* VDDS1V8 */ +- regulator-name = "smps4"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps5_reg: smps5 { +- /* VDD_DDR */ +- regulator-name = "smps5"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1_reg: ldo1 { +- /* LDO1_OUT --> SDIO */ +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-allow-bypass; +- }; +- +- ldo2_reg: ldo2 { +- regulator-name = "ldo2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-allow-bypass; +- }; +- +- ldo3_reg: ldo3 { +- /* VDDA_1V8_PHY */ +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo5_reg: ldo5 { +- /* VDDA_1V8_PLL */ +- regulator-name = "ldo5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo4_reg: ldo4 { +- /* VDDA_3V_USB: VDDA_USBHS33 */ +- regulator-name = "ldo4"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- }; +- }; +- +- tps65917_power_button { +- compatible = "ti,palmas-pwrbutton"; +- interrupt-parent = <&tps65917>; +- interrupts = <1 IRQ_TYPE_NONE>; +- wakeup-source; +- ti,palmas-long-press-seconds = <6>; +- }; +-}; +- +-&usb2_phy1 { +- phy-supply = <&ldo4_reg>; +-}; +- +-&usb2_phy2 { +- phy-supply = <&ldo4_reg>; +-}; +- +-&dss { +- vdda_video-supply = <&ldo5_reg>; +-}; +- +-&mmc1 { +- vqmmc-supply = <&ldo1_reg>; +-}; +- +-&cpu0 { +- vdd-supply = <&smps1_reg>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra72-evm.dts b/scripts/dtc/include-prefixes/arm/dra72-evm.dts +deleted file mode 100644 +index 5f62f92eb96c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra72-evm.dts ++++ /dev/null +@@ -1,127 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-#include "dra72-evm-common.dtsi" +-#include "dra72x-mmc-iodelay.dtsi" +-/ { +- model = "TI DRA722"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */ +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ipu2_memory_region: ipu2-memory@95800000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x95800000 0x0 0x3800000>; +- reusable; +- status = "okay"; +- }; +- +- dsp1_memory_region: dsp1-memory@99000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x99000000 0x0 0x4000000>; +- reusable; +- status = "okay"; +- }; +- +- ipu1_memory_region: ipu1-memory@9d000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x9d000000 0x0 0x2000000>; +- reusable; +- status = "okay"; +- }; +- }; +- +- evm_1v8_sw: fixedregulator-evm_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "evm_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&smps4_reg>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&i2c1 { +- tps65917: tps65917@58 { +- reg = <0x58>; +- +- interrupts = ; /* IRQ_SYS_1N */ +- }; +-}; +- +-#include "dra72-evm-tps65917.dtsi" +- +-&hdmi { +- vdda-supply = <&ldo3_reg>; +-}; +- +-&pcf_gpio_21 { +- interrupt-parent = <&gpio6>; +- interrupts = <11 IRQ_TYPE_EDGE_FALLING>; +-}; +- +-&mac_sw { +- mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&cpsw_port1 { +- phy-handle = <ðphy0>; +- phy-mode = "rgmii"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- status = "disabled"; +-}; +- +-&davinci_mdio_sw { +- ethphy0: ethernet-phy@3 { +- reg = <3>; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; +- pinctrl-0 = <&mmc1_pins_default>; +- pinctrl-1 = <&mmc1_pins_hs>; +- pinctrl-2 = <&mmc1_pins_sdr12>; +- pinctrl-3 = <&mmc1_pins_sdr25>; +- pinctrl-4 = <&mmc1_pins_sdr50>; +- pinctrl-5 = <&mmc1_pins_ddr50_rev10>; +- pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev10_conf>; +- vqmmc-supply = <&ldo1_reg>; +-}; +- +-&mmc2 { +- pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; +- pinctrl-0 = <&mmc2_pins_default>; +- pinctrl-1 = <&mmc2_pins_hs>; +- pinctrl-2 = <&mmc2_pins_ddr_rev10>; +- pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>; +- vmmc-supply = <&evm_1v8_sw>; +-}; +- +-&ipu2 { +- status = "okay"; +- memory-region = <&ipu2_memory_region>; +-}; +- +-&ipu1 { +- status = "okay"; +- memory-region = <&ipu1_memory_region>; +-}; +- +-&dsp1 { +- status = "okay"; +- memory-region = <&dsp1_memory_region>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra72x-mmc-iodelay.dtsi b/scripts/dtc/include-prefixes/arm/dra72x-mmc-iodelay.dtsi +deleted file mode 100644 +index a9dce919d443..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra72x-mmc-iodelay.dtsi ++++ /dev/null +@@ -1,361 +0,0 @@ +-/* +- * MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs. +- * +- * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation version 2. +- * +- * This program is distributed "as is" WITHOUT ANY WARRANTY of any +- * kind, whether express or implied; without even the implied warranty +- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-/* +- * Rules for modifying this file: +- * a) Update of this file should typically correspond to a datamanual revision. +- * Datamanual revision that was used should be updated in comment below. +- * If there is no update to datamanual, do not update the values. If you +- * need to use values different from that recommended by the datamanual +- * for your design, then you should consider adding values to the device- +- * -tree file for your board directly. +- * b) We keep the mode names as close to the datamanual as possible. So +- * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, +- * we follow that in code too. +- * c) If the values change between multiple revisions of silicon, we add +- * a revision tag to both the new and old entry. Use 'rev10' for PG 1.0, +- * 'rev20' for PG 2.0 and so on. +- * d) The node name and node label should be the exact same string. This is +- * to curb naming creativity and achieve consistency. +- * e) If in future, DRA71x and DRA72x values differ, then add 'dra71_' and +- * 'dra72_' tag to entries. Both the new and old entries should gain a tag. +- * +- * Datamanual Revisions: +- * +- * AM571x Silicon Revision 2.0: SPRS957D, Revised January 2017 +- * AM571x Silicon Revision 1.0: SPRS919M, Revised November 2017 +- * DRA71x : SPRS960B, Revised February 2017 +- */ +- +-&dra7_pmx_core { +- mmc1_pins_default: mmc1_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +- +- mmc1_pins_sdr12: mmc1_pins_sdr12 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +- +- mmc1_pins_hs: mmc1_pins_hs { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +- +- mmc1_pins_sdr25: mmc1_pins_sdr25 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +- +- mmc1_pins_sdr50: mmc1_pins_sdr50 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +- +- mmc1_pins_ddr50_rev10: mmc1_pins_ddr50_rev10 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_clk.mmc1_clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ +- DRA7XX_CORE_IOPAD(0x375C, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ +- >; +- }; +- +- mmc1_pins_ddr50_rev20: mmc1_pins_ddr50_rev20 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +- +- mmc1_pins_sdr104: mmc1_pins_sdr104 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +- +- mmc2_pins_default: mmc2_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ +- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ +- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ +- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ +- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ +- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ +- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ +- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ +- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ +- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ +- >; +- }; +- +- mmc2_pins_hs: mmc2_pins_hs { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ +- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ +- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ +- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ +- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ +- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ +- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ +- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ +- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ +- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ +- >; +- }; +- +- mmc2_pins_ddr_rev10: mmc2_pins_ddr_rev10 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ +- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ +- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ +- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ +- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ +- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ +- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ +- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ +- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ +- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ +- >; +- }; +- +- mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ +- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ +- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ +- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ +- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ +- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ +- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ +- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ +- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ +- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ +- >; +- }; +- +- mmc2_pins_hs200: mmc2_pins_hs200 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ +- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ +- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ +- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ +- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ +- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ +- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ +- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ +- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ +- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ +- >; +- }; +- +- mmc4_pins_default: mmc4_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ +- DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ +- DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ +- DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ +- DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ +- DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ +- >; +- }; +-}; +- +-&dra7_iodelay_core { +- +- /* Corresponds to MMC1_MANUAL1 in datamanual */ +- mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf { +- pinctrl-pin-array = < +- 0x618 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */ +- 0x624 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ +- 0x630 A_DELAY_PS(1375) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ +- 0x63C A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ +- 0x648 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ +- 0x654 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ +- 0x620 A_DELAY_PS(1230) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ +- 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ +- 0x638 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ +- 0x644 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ +- 0x650 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ +- 0x65C A_DELAY_PS(99) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ +- 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ +- 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ +- 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ +- 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ +- 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ +- >; +- }; +- +- /* Corresponds to MMC1_MANUAL2 in datamanual */ +- mmc1_iodelay_sdr104_rev10_conf: mmc1_iodelay_sdr104_rev10_conf { +- pinctrl-pin-array = < +- 0x620 A_DELAY_PS(560) G_DELAY_PS(365) /* CFG_MMC1_CLK_OUT */ +- 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ +- 0x638 A_DELAY_PS(29) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ +- 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ +- 0x650 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ +- 0x65c A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ +- 0x628 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ +- 0x634 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ +- 0x640 A_DELAY_PS(433) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ +- 0x64c A_DELAY_PS(287) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ +- 0x658 A_DELAY_PS(351) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ +- >; +- }; +- +- /* Corresponds to MMC1_MANUAL2 in datamanual */ +- mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf { +- pinctrl-pin-array = < +- 0x620 A_DELAY_PS(520) G_DELAY_PS(320) /* CFG_MMC1_CLK_OUT */ +- 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ +- 0x638 A_DELAY_PS(40) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ +- 0x644 A_DELAY_PS(83) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ +- 0x650 A_DELAY_PS(98) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ +- 0x65c A_DELAY_PS(106) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ +- 0x628 A_DELAY_PS(51) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ +- 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ +- 0x640 A_DELAY_PS(363) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ +- 0x64c A_DELAY_PS(199) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ +- 0x658 A_DELAY_PS(273) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ +- >; +- }; +- +- /* Corresponds to MMC2_MANUAL1 in datamanual */ +- mmc2_iodelay_ddr_conf: mmc2_iodelay_ddr_conf { +- pinctrl-pin-array = < +- 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */ +- 0x1a4 A_DELAY_PS(119) G_DELAY_PS(0) /* CFG_GPMC_A20_IN */ +- 0x1b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_IN */ +- 0x1bc A_DELAY_PS(18) G_DELAY_PS(0) /* CFG_GPMC_A22_IN */ +- 0x1c8 A_DELAY_PS(894) G_DELAY_PS(0) /* CFG_GPMC_A23_IN */ +- 0x1d4 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_IN */ +- 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ +- 0x1ec A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ +- 0x1f8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_IN */ +- 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ +- 0x194 A_DELAY_PS(152) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ +- 0x1ac A_DELAY_PS(206) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ +- 0x1b8 A_DELAY_PS(78) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ +- 0x1c4 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ +- 0x1d0 A_DELAY_PS(266) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ +- 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ +- 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ +- 0x1f4 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ +- 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ +- 0x368 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ +- 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ +- 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ +- 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ +- 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ +- 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ +- 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ +- 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ +- 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ +- 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ +- >; +- }; +- +- /* Corresponds to MMC2_MANUAL3 in datamanual */ +- mmc2_iodelay_hs200_rev10_conf: mmc2_iodelay_hs200_rev10_conf { +- pinctrl-pin-array = < +- 0x194 A_DELAY_PS(150) G_DELAY_PS(95) /* CFG_GPMC_A19_OUT */ +- 0x1ac A_DELAY_PS(250) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ +- 0x1b8 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ +- 0x1c4 A_DELAY_PS(100) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ +- 0x1d0 A_DELAY_PS(870) G_DELAY_PS(415) /* CFG_GPMC_A23_OUT */ +- 0x1dc A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ +- 0x1e8 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ +- 0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ +- 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ +- 0x368 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ +- 0x190 A_DELAY_PS(695) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ +- 0x1a8 A_DELAY_PS(924) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ +- 0x1b4 A_DELAY_PS(719) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ +- 0x1c0 A_DELAY_PS(824) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ +- 0x1d8 A_DELAY_PS(877) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ +- 0x1e4 A_DELAY_PS(446) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ +- 0x1f0 A_DELAY_PS(847) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ +- 0x1fc A_DELAY_PS(586) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ +- 0x364 A_DELAY_PS(1039) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ +- >; +- }; +- +- /* Corresponds to MMC2_MANUAL3 in datamanual */ +- mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf { +- pinctrl-pin-array = < +- 0x194 A_DELAY_PS(285) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ +- 0x1ac A_DELAY_PS(189) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ +- 0x1b8 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_OUT */ +- 0x1c4 A_DELAY_PS(0) G_DELAY_PS(70) /* CFG_GPMC_A22_OUT */ +- 0x1d0 A_DELAY_PS(730) G_DELAY_PS(360) /* CFG_GPMC_A23_OUT */ +- 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ +- 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ +- 0x1f4 A_DELAY_PS(70) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ +- 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ +- 0x368 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_CS1_OUT */ +- 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ +- 0x1a8 A_DELAY_PS(231) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ +- 0x1b4 A_DELAY_PS(39) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ +- 0x1c0 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ +- 0x1d8 A_DELAY_PS(176) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ +- 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ +- 0x1f0 A_DELAY_PS(101) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ +- 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ +- 0x364 A_DELAY_PS(360) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra72x.dtsi b/scripts/dtc/include-prefixes/arm/dra72x.dtsi +deleted file mode 100644 +index 90617261373c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra72x.dtsi ++++ /dev/null +@@ -1,110 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * Based on "omap4.dtsi" +- */ +- +-#include "dra7.dtsi" +- +-/ { +- compatible = "ti,dra722", "ti,dra72", "ti,dra7"; +- +- aliases { +- rproc0 = &ipu1; +- rproc1 = &ipu2; +- rproc2 = &dsp1; +- }; +- +- pmu { +- compatible = "arm,cortex-a15-pmu"; +- interrupt-parent = <&wakeupgen>; +- interrupts = ; +- }; +-}; +- +-&l4_per2 { +- target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x5b000 0x4>, +- <0x5b010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- ; +- ti,sysc-sidle = , +- ; +- clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5b000 0x1000>; +- +- cal: cal@0 { +- compatible = "ti,dra72-cal"; +- reg = <0x0000 0x400>, +- <0x0800 0x40>, +- <0x0900 0x40>; +- reg-names = "cal_top", +- "cal_rx_core0", +- "cal_rx_core1"; +- interrupts = ; +- ti,camerrx-control = <&scm_conf 0xE94>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- csi2_0: port@0 { +- reg = <0>; +- }; +- csi2_1: port@1 { +- reg = <1>; +- }; +- }; +- }; +- }; +-}; +- +-&dss { +- reg = <0 0x80>, +- <0x4054 0x4>, +- <0x4300 0x20>; +- reg-names = "dss", "pll1_clkctrl", "pll1"; +- +- clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>, +- <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>; +- clock-names = "fck", "video1_clk"; +-}; +- +-&mailbox5 { +- mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { +- ti,mbox-tx = <6 2 2>; +- ti,mbox-rx = <4 2 2>; +- status = "disabled"; +- }; +- mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { +- ti,mbox-tx = <5 2 2>; +- ti,mbox-rx = <1 2 2>; +- status = "disabled"; +- }; +-}; +- +-&mailbox6 { +- mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { +- ti,mbox-tx = <6 2 2>; +- ti,mbox-rx = <4 2 2>; +- status = "disabled"; +- }; +-}; +- +-&pcie1_rc { +- compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; +-}; +- +-&pcie1_ep { +- compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep"; +-}; +- +-&pcie2_rc { +- compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra74-ipu-dsp-common.dtsi b/scripts/dtc/include-prefixes/arm/dra74-ipu-dsp-common.dtsi +deleted file mode 100644 +index 3256631510c5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra74-ipu-dsp-common.dtsi ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Common IPU and DSP data for TI DRA74x/DRA76x/AM572x/AM574x platforms +- */ +- +-#include "dra7-ipu-dsp-common.dtsi" +- +-&mailbox6 { +- mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { +- status = "okay"; +- }; +-}; +- +-&dsp2 { +- mboxes = <&mailbox6 &mbox_dsp2_ipc3x>; +- ti,timers = <&timer6>; +- ti,watchdog-timers = <&timer13>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra74x-mmc-iodelay.dtsi b/scripts/dtc/include-prefixes/arm/dra74x-mmc-iodelay.dtsi +deleted file mode 100644 +index e86da7a970b6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra74x-mmc-iodelay.dtsi ++++ /dev/null +@@ -1,647 +0,0 @@ +-/* +- * MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs. +- * +- * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation version 2. +- * +- * This program is distributed "as is" WITHOUT ANY WARRANTY of any +- * kind, whether express or implied; without even the implied warranty +- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-/* +- * Rules for modifying this file: +- * a) Update of this file should typically correspond to a datamanual revision. +- * Datamanual revision that was used should be updated in comment below. +- * If there is no update to datamanual, do not update the values. If you +- * need to use values different from that recommended by the datamanual +- * for your design, then you should consider adding values to the device- +- * -tree file for your board directly. +- * b) We keep the mode names as close to the datamanual as possible. So +- * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, +- * we follow that in code too. +- * c) If the values change between multiple revisions of silicon, we add +- * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1, +- * 'rev20' for PG 2.0 and so on. +- * d) The node name and node label should be the exact same string. This is +- * to curb naming creativity and achieve consistency. +- * +- * Datamanual Revisions: +- * +- * AM572x Silicon Revision 2.0: SPRS953F, Revised May 2019 +- * AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016 +- * +- */ +- +-&dra7_pmx_core { +- mmc1_pins_default: mmc1_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +- +- mmc1_pins_sdr12: mmc1_pins_sdr12 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +- +- mmc1_pins_hs: mmc1_pins_hs { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +- +- mmc1_pins_sdr25: mmc1_pins_sdr25 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +- +- mmc1_pins_sdr50: mmc1_pins_sdr50 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +- +- mmc1_pins_ddr50: mmc1_pins_ddr50 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +- +- mmc1_pins_sdr104: mmc1_pins_sdr104 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +- +- mmc2_pins_default: mmc2_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ +- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ +- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ +- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ +- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ +- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ +- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ +- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ +- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ +- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ +- >; +- }; +- +- mmc2_pins_hs: mmc2_pins_hs { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ +- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ +- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ +- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ +- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ +- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ +- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ +- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ +- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ +- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ +- >; +- }; +- +- mmc2_pins_ddr_3_3v_rev11: mmc2_pins_ddr_3_3v_rev11 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ +- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ +- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ +- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ +- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ +- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ +- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ +- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ +- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ +- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ +- >; +- }; +- +- mmc2_pins_ddr_1_8v_rev11: mmc2_pins_ddr_1_8v_rev11 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ +- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ +- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ +- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ +- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ +- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ +- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ +- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ +- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ +- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ +- >; +- }; +- +- mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ +- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ +- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ +- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ +- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ +- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ +- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ +- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ +- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ +- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ +- >; +- }; +- +- mmc2_pins_hs200: mmc2_pins_hs200 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ +- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ +- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ +- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ +- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ +- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ +- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ +- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ +- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ +- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ +- >; +- }; +- +- mmc4_pins_default: mmc4_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ +- DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ +- DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ +- DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ +- DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ +- DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ +- >; +- }; +- +- mmc4_pins_hs: mmc4_pins_hs { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ +- DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ +- DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ +- DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ +- DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ +- DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ +- >; +- }; +- +- mmc3_pins_default: mmc3_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ +- DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ +- DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ +- DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ +- DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ +- DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ +- >; +- }; +- +- mmc3_pins_hs: mmc3_pins_hs { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ +- DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ +- DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ +- DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ +- DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ +- DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ +- >; +- }; +- +- mmc3_pins_sdr12: mmc3_pins_sdr12 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ +- DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ +- DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ +- DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ +- DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ +- DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ +- >; +- }; +- +- mmc3_pins_sdr25: mmc3_pins_sdr25 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ +- DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ +- DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ +- DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ +- DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ +- DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ +- >; +- }; +- +- mmc3_pins_sdr50: mmc3_pins_sdr50 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ +- DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ +- DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ +- DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ +- DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ +- DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ +- >; +- }; +- +- mmc4_pins_sdr12: mmc4_pins_sdr12 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ +- DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ +- DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ +- DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ +- DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ +- DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ +- >; +- }; +- +- mmc4_pins_sdr25: mmc4_pins_sdr25 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ +- DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ +- DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ +- DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ +- DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ +- DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ +- >; +- }; +-}; +- +-&dra7_iodelay_core { +- +- /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ +- mmc1_iodelay_ddr_rev11_conf: mmc1_iodelay_ddr_rev11_conf { +- pinctrl-pin-array = < +- 0x618 A_DELAY_PS(572) G_DELAY_PS(540) /* CFG_MMC1_CLK_IN */ +- 0x620 A_DELAY_PS(1525) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ +- 0x624 A_DELAY_PS(0) G_DELAY_PS(600) /* CFG_MMC1_CMD_IN */ +- 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ +- 0x62c A_DELAY_PS(55) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ +- 0x630 A_DELAY_PS(403) G_DELAY_PS(120) /* CFG_MMC1_DAT0_IN */ +- 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ +- 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ +- 0x63c A_DELAY_PS(23) G_DELAY_PS(60) /* CFG_MMC1_DAT1_IN */ +- 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ +- 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ +- 0x648 A_DELAY_PS(25) G_DELAY_PS(60) /* CFG_MMC1_DAT2_IN */ +- 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ +- 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ +- 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ +- 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ +- 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ +- >; +- }; +- +- /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ +- mmc1_iodelay_ddr_rev20_conf: mmc1_iodelay_ddr50_rev20_conf { +- pinctrl-pin-array = < +- 0x618 A_DELAY_PS(1076) G_DELAY_PS(330) /* CFG_MMC1_CLK_IN */ +- 0x620 A_DELAY_PS(1271) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ +- 0x624 A_DELAY_PS(722) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ +- 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ +- 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ +- 0x630 A_DELAY_PS(751) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ +- 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ +- 0x638 A_DELAY_PS(20) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ +- 0x63C A_DELAY_PS(256) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ +- 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ +- 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ +- 0x648 A_DELAY_PS(263) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ +- 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ +- 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ +- 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ +- 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ +- 0x65C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ +- >; +- }; +- +- /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ +- mmc1_iodelay_sdr104_rev11_conf: mmc1_iodelay_sdr104_rev11_conf { +- pinctrl-pin-array = < +- 0x620 A_DELAY_PS(1063) G_DELAY_PS(17) /* CFG_MMC1_CLK_OUT */ +- 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ +- 0x62c A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ +- 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ +- 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ +- 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ +- 0x644 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ +- 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ +- 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ +- 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ +- 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ +- >; +- }; +- +- /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ +- mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf { +- pinctrl-pin-array = < +- 0x620 A_DELAY_PS(600) G_DELAY_PS(400) /* CFG_MMC1_CLK_OUT */ +- 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ +- 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ +- 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ +- 0x638 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ +- 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ +- 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ +- 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ +- 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ +- 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ +- 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ +- >; +- }; +- +- /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ +- mmc2_iodelay_hs200_rev11_conf: mmc2_iodelay_hs200_rev11_conf { +- pinctrl-pin-array = < +- 0x190 A_DELAY_PS(621) G_DELAY_PS(600) /* CFG_GPMC_A19_OEN */ +- 0x194 A_DELAY_PS(300) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ +- 0x1a8 A_DELAY_PS(739) G_DELAY_PS(600) /* CFG_GPMC_A20_OEN */ +- 0x1ac A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ +- 0x1b4 A_DELAY_PS(812) G_DELAY_PS(600) /* CFG_GPMC_A21_OEN */ +- 0x1b8 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ +- 0x1c0 A_DELAY_PS(954) G_DELAY_PS(600) /* CFG_GPMC_A22_OEN */ +- 0x1c4 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ +- 0x1d0 A_DELAY_PS(1340) G_DELAY_PS(420) /* CFG_GPMC_A23_OUT */ +- 0x1d8 A_DELAY_PS(935) G_DELAY_PS(600) /* CFG_GPMC_A24_OEN */ +- 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ +- 0x1e4 A_DELAY_PS(525) G_DELAY_PS(600) /* CFG_GPMC_A25_OEN */ +- 0x1e8 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ +- 0x1f0 A_DELAY_PS(767) G_DELAY_PS(600) /* CFG_GPMC_A26_OEN */ +- 0x1f4 A_DELAY_PS(225) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ +- 0x1fc A_DELAY_PS(565) G_DELAY_PS(600) /* CFG_GPMC_A27_OEN */ +- 0x200 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ +- 0x364 A_DELAY_PS(969) G_DELAY_PS(600) /* CFG_GPMC_CS1_OEN */ +- 0x368 A_DELAY_PS(180) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ +- >; +- }; +- +- /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ +- mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf { +- pinctrl-pin-array = < +- 0x190 A_DELAY_PS(274) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ +- 0x194 A_DELAY_PS(162) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ +- 0x1a8 A_DELAY_PS(401) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ +- 0x1ac A_DELAY_PS(73) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ +- 0x1b4 A_DELAY_PS(465) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ +- 0x1b8 A_DELAY_PS(115) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ +- 0x1c0 A_DELAY_PS(633) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ +- 0x1c4 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ +- 0x1d0 A_DELAY_PS(935) G_DELAY_PS(280) /* CFG_GPMC_A23_OUT */ +- 0x1d8 A_DELAY_PS(621) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ +- 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ +- 0x1e4 A_DELAY_PS(183) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ +- 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ +- 0x1f0 A_DELAY_PS(467) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ +- 0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ +- 0x1fc A_DELAY_PS(262) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ +- 0x200 A_DELAY_PS(46) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ +- 0x364 A_DELAY_PS(684) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ +- 0x368 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ +- >; +- }; +- +- /* Correspnds to MMC2_DDR_3V3_MANUAL1 in datamanual */ +- mmc2_iodelay_ddr_3_3v_rev11_conf: mmc2_iodelay_ddr_3_3v_rev11_conf { +- pinctrl-pin-array = < +- 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ +- 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ +- 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ +- 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ +- 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ +- 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ +- 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ +- 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ +- 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ +- 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ +- 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ +- 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ +- 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ +- 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ +- 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ +- 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ +- 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ +- 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ +- 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ +- 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ +- 0x1ec A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A26_IN */ +- 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ +- 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ +- 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ +- 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ +- 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ +- 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ +- 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ +- 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ +- >; +- }; +- +- /* Corresponds to MMC2_DDR_1V8_MANUAL1 in datamanual */ +- mmc2_iodelay_ddr_1_8v_rev11_conf: mmc2_iodelay_ddr_1_8v_rev11_conf { +- pinctrl-pin-array = < +- 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */ +- 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ +- 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ +- 0x1a4 A_DELAY_PS(274) G_DELAY_PS(240) /* CFG_GPMC_A20_IN */ +- 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ +- 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ +- 0x1b0 A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A21_IN */ +- 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ +- 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ +- 0x1bc A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A22_IN */ +- 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ +- 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ +- 0x1c8 A_DELAY_PS(514) G_DELAY_PS(360) /* CFG_GPMC_A23_IN */ +- 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ +- 0x1d4 A_DELAY_PS(187) G_DELAY_PS(120) /* CFG_GPMC_A24_IN */ +- 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ +- 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ +- 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ +- 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ +- 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ +- 0x1ec A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A26_IN */ +- 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ +- 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ +- 0x1f8 A_DELAY_PS(121) G_DELAY_PS(60) /* CFG_GPMC_A27_IN */ +- 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ +- 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ +- 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ +- 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ +- 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ +- >; +- }; +- +- /* Corresponds to MMC3_MANUAL1 in datamanual */ +- mmc3_iodelay_manual1_rev20_conf: mmc3_iodelay_manual1_conf { +- pinctrl-pin-array = < +- 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */ +- 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ +- 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ +- 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ +- 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ +- 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ +- 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ +- 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ +- 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ +- 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ +- 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ +- 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ +- 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ +- 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ +- 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ +- 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ +- 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ +- >; +- }; +- +- /* Corresponds to MMC3_MANUAL1 in datamanual */ +- mmc3_iodelay_manual1_rev11_conf: mmc3_iodelay_manual1_conf { +- pinctrl-pin-array = < +- 0x678 A_DELAY_PS(406) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */ +- 0x680 A_DELAY_PS(659) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ +- 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ +- 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ +- 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ +- 0x690 A_DELAY_PS(130) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ +- 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ +- 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ +- 0x69c A_DELAY_PS(169) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ +- 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ +- 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ +- 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ +- 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ +- 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ +- 0x6b4 A_DELAY_PS(457) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ +- 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ +- 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ +- >; +- }; +- +- /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ +- mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf { +- pinctrl-pin-array = < +- 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ +- 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ +- 0x84c A_DELAY_PS(96) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ +- 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ +- 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ +- 0x870 A_DELAY_PS(582) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ +- 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ +- 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ +- 0x87c A_DELAY_PS(391) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ +- 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ +- 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ +- 0x888 A_DELAY_PS(561) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ +- 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ +- 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ +- 0x894 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ +- 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ +- 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ +- >; +- }; +- +- /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ +- mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf { +- pinctrl-pin-array = < +- 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ +- 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ +- 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ +- 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ +- 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ +- 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ +- 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ +- 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ +- 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ +- 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ +- 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ +- 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ +- 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ +- 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ +- 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ +- 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ +- 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ +- >; +- }; +- +- /* Corresponds to MMC4_MANUAL1 in datamanual */ +- mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf { +- pinctrl-pin-array = < +- 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ +- 0x848 A_DELAY_PS(2651) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ +- 0x84c A_DELAY_PS(1572) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ +- 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ +- 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ +- 0x870 A_DELAY_PS(1913) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ +- 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ +- 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ +- 0x87c A_DELAY_PS(1721) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ +- 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ +- 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ +- 0x888 A_DELAY_PS(1891) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ +- 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ +- 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ +- 0x894 A_DELAY_PS(1919) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ +- 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ +- 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ +- >; +- }; +- +- /* Corresponds to MMC4_MANUAL1 in datamanual */ +- mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf { +- pinctrl-pin-array = < +- 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ +- 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ +- 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ +- 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ +- 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ +- 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ +- 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ +- 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ +- 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */ +- 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ +- 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ +- 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */ +- 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ +- 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ +- 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */ +- 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ +- 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra74x-p.dtsi b/scripts/dtc/include-prefixes/arm/dra74x-p.dtsi +deleted file mode 100644 +index 006189dad7a7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra74x-p.dtsi ++++ /dev/null +@@ -1,27 +0,0 @@ +-/* +- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License version 2 as +- * published by the Free Software Foundation. +- */ +- +-#include "dra74x.dtsi" +- +-/ { +- compatible = "ti,dra762", "ti,dra7"; +- +- ocp { +- emif1: emif@4c000000 { +- compatible = "ti,emif-dra7xx"; +- reg = <0x4c000000 0x200>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +-}; +- +-/* MCAN interrupts are hard-wired to irqs 67, 68 */ +-&crossbar_mpu { +- ti,irqs-skip = <10 67 68 133 139 140>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra74x.dtsi b/scripts/dtc/include-prefixes/arm/dra74x.dtsi +deleted file mode 100644 +index cfb39dde4930..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra74x.dtsi ++++ /dev/null +@@ -1,232 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * Based on "omap4.dtsi" +- */ +- +-#include "dra7.dtsi" +- +-/ { +- compatible = "ti,dra742", "ti,dra74", "ti,dra7"; +- +- cpus { +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <1>; +- operating-points-v2 = <&cpu0_opp_table>; +- +- clocks = <&dpll_mpu_ck>; +- clock-names = "cpu"; +- +- clock-latency = <300000>; /* From omap-cpufreq driver */ +- +- /* cooling options */ +- #cooling-cells = <2>; /* min followed by max */ +- +- vbb-supply = <&abb_mpu>; +- }; +- }; +- +- aliases { +- rproc0 = &ipu1; +- rproc1 = &ipu2; +- rproc2 = &dsp1; +- rproc3 = &dsp2; +- }; +- +- pmu { +- compatible = "arm,cortex-a15-pmu"; +- interrupt-parent = <&wakeupgen>; +- interrupts = , +- ; +- }; +- +- ocp { +- dsp2_system: dsp_system@41500000 { +- compatible = "syscon"; +- reg = <0x41500000 0x100>; +- }; +- +- +- target-module@41501000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x41501000 0x4>, +- <0x41501010 0x4>, +- <0x41501014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; +- clock-names = "fck"; +- resets = <&prm_dsp2 1>; +- reset-names = "rstctrl"; +- ranges = <0x0 0x41501000 0x1000>; +- #size-cells = <1>; +- #address-cells = <1>; +- +- mmu0_dsp2: mmu@0 { +- compatible = "ti,dra7-dsp-iommu"; +- reg = <0x0 0x100>; +- interrupts = ; +- #iommu-cells = <0>; +- ti,syscon-mmuconfig = <&dsp2_system 0x0>; +- }; +- }; +- +- target-module@41502000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x41502000 0x4>, +- <0x41502010 0x4>, +- <0x41502014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- +- clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; +- clock-names = "fck"; +- resets = <&prm_dsp2 1>; +- reset-names = "rstctrl"; +- ranges = <0x0 0x41502000 0x1000>; +- #size-cells = <1>; +- #address-cells = <1>; +- +- mmu1_dsp2: mmu@0 { +- compatible = "ti,dra7-dsp-iommu"; +- reg = <0x0 0x100>; +- interrupts = ; +- #iommu-cells = <0>; +- ti,syscon-mmuconfig = <&dsp2_system 0x1>; +- }; +- }; +- +- dsp2: dsp@41000000 { +- compatible = "ti,dra7-dsp"; +- reg = <0x41000000 0x48000>, +- <0x41600000 0x8000>, +- <0x41700000 0x8000>; +- reg-names = "l2ram", "l1pram", "l1dram"; +- ti,bootreg = <&scm_conf 0x560 10>; +- iommus = <&mmu0_dsp2>, <&mmu1_dsp2>; +- status = "disabled"; +- resets = <&prm_dsp2 0>; +- clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; +- firmware-name = "dra7-dsp2-fw.xe66"; +- }; +- }; +-}; +- +-&cpu0_opp_table { +- opp-shared; +-}; +- +-&dss { +- reg = <0 0x80>, +- <0x4054 0x4>, +- <0x4300 0x20>, +- <0x9054 0x4>, +- <0x9300 0x20>; +- reg-names = "dss", "pll1_clkctrl", "pll1", +- "pll2_clkctrl", "pll2"; +- +- clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>, +- <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>, +- <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 13>; +- clock-names = "fck", "video1_clk", "video2_clk"; +-}; +- +-&mailbox5 { +- mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { +- ti,mbox-tx = <6 2 2>; +- ti,mbox-rx = <4 2 2>; +- status = "disabled"; +- }; +- mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { +- ti,mbox-tx = <5 2 2>; +- ti,mbox-rx = <1 2 2>; +- status = "disabled"; +- }; +-}; +- +-&mailbox6 { +- mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { +- ti,mbox-tx = <6 2 2>; +- ti,mbox-rx = <4 2 2>; +- status = "disabled"; +- }; +- mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { +- ti,mbox-tx = <5 2 2>; +- ti,mbox-rx = <1 2 2>; +- status = "disabled"; +- }; +-}; +- +-&pcie1_rc { +- compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie"; +-}; +- +-&pcie1_ep { +- compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep"; +-}; +- +-&pcie2_rc { +- compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie"; +-}; +- +-&l4_per3 { +- segment@0 { +- usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x140000 0x4>, +- <0x140010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ +- clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x140000 0x20000>; +- +- omap_dwc3_4: omap_dwc3_4@0 { +- compatible = "ti,dwc3"; +- reg = <0 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <1>; +- utmi-mode = <2>; +- ranges; +- status = "disabled"; +- usb4: usb@10000 { +- compatible = "snps,dwc3"; +- reg = <0x10000 0x17000>; +- interrupts = , +- , +- ; +- interrupt-names = "peripheral", +- "host", +- "otg"; +- maximum-speed = "high-speed"; +- dr_mode = "otg"; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra76-evm.dts b/scripts/dtc/include-prefixes/arm/dra76-evm.dts +deleted file mode 100644 +index e2b7fcb061cf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra76-evm.dts ++++ /dev/null +@@ -1,567 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "dra76x.dtsi" +-#include "dra7-evm-common.dtsi" +-#include "dra76x-mmc-iodelay.dtsi" +-#include +- +-/ { +- model = "TI DRA762 EVM"; +- compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7"; +- +- aliases { +- display0 = &hdmi0; +- +- sound0 = &sound0; +- sound1 = &hdmi; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0x80000000>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ipu2_cma_pool: ipu2_cma@95800000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x95800000 0x0 0x3800000>; +- reusable; +- status = "okay"; +- }; +- +- dsp1_cma_pool: dsp1_cma@99000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x99000000 0x0 0x4000000>; +- reusable; +- status = "okay"; +- }; +- +- ipu1_cma_pool: ipu1_cma@9d000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x9d000000 0x0 0x2000000>; +- reusable; +- status = "okay"; +- }; +- +- dsp2_cma_pool: dsp2_cma@9f000000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x9f000000 0x0 0x800000>; +- reusable; +- status = "okay"; +- }; +- }; +- +- vsys_12v0: fixedregulator-vsys12v0 { +- /* main supply */ +- compatible = "regulator-fixed"; +- regulator-name = "vsys_12v0"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vsys_5v0: fixedregulator-vsys5v0 { +- /* Output of Cntlr B of TPS43351-Q1 on dra76-evm */ +- compatible = "regulator-fixed"; +- regulator-name = "vsys_5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vsys_12v0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vio_3v6: fixedregulator-vio_3v6 { +- compatible = "regulator-fixed"; +- regulator-name = "vio_3v6"; +- regulator-min-microvolt = <3600000>; +- regulator-max-microvolt = <3600000>; +- vin-supply = <&vsys_5v0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vsys_3v3: fixedregulator-vsys3v3 { +- /* Output of Cntlr A of TPS43351-Q1 on dra76-evm */ +- compatible = "regulator-fixed"; +- regulator-name = "vsys_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vsys_12v0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vio_3v3: fixedregulator-vio_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vio_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vsys_3v3>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vio_3v3_sd: fixedregulator-sd { +- compatible = "regulator-fixed"; +- regulator-name = "vio_3v3_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vio_3v3>; +- enable-active-high; +- gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; +- }; +- +- vio_1v8: fixedregulator-vio_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "vio_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&smps5_reg>; +- }; +- +- vmmcwl_fixed: fixedregulator-mmcwl { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcwl_fixed"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio5 8 0>; /* gpio5_8 */ +- startup-delay-us = <70000>; +- enable-active-high; +- }; +- +- vtt_fixed: fixedregulator-vtt { +- compatible = "regulator-fixed"; +- regulator-name = "vtt_fixed"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- vin-supply = <&vsys_3v3>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- aic_dvdd: fixedregulator-aic_dvdd { +- /* TPS77018DBVT */ +- compatible = "regulator-fixed"; +- regulator-name = "aic_dvdd"; +- vin-supply = <&vio_3v3>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- hdmi0: connector { +- compatible = "hdmi-connector"; +- label = "hdmi"; +- +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&tpd12s015_out>; +- }; +- }; +- }; +- +- tpd12s015: encoder { +- compatible = "ti,tpd12s015"; +- +- gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>, /* gpio7_30, CT CP HPD */ +- <&gpio7 31 GPIO_ACTIVE_HIGH>, /* gpio7_31, LS OE */ +- <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tpd12s015_in: endpoint { +- remote-endpoint = <&hdmi_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- tpd12s015_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- tps65917: tps65917@58 { +- compatible = "ti,tps65917"; +- reg = <0x58>; +- ti,system-power-controller; +- ti,palmas-override-powerhold; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- tps65917_pmic { +- compatible = "ti,tps65917-pmic"; +- +- smps12-in-supply = <&vsys_3v3>; +- smps3-in-supply = <&vsys_3v3>; +- smps4-in-supply = <&vsys_3v3>; +- smps5-in-supply = <&vsys_3v3>; +- ldo1-in-supply = <&vsys_3v3>; +- ldo2-in-supply = <&vsys_3v3>; +- ldo3-in-supply = <&vsys_5v0>; +- ldo4-in-supply = <&vsys_5v0>; +- ldo5-in-supply = <&vsys_3v3>; +- +- tps65917_regulators: regulators { +- smps12_reg: smps12 { +- /* VDD_DSPEVE */ +- regulator-name = "smps12"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps3_reg: smps3 { +- /* VDD_CORE */ +- regulator-name = "smps3"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- smps4_reg: smps4 { +- /* VDD_IVA */ +- regulator-name = "smps4"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps5_reg: smps5 { +- /* VDDS1V8 */ +- regulator-name = "smps5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1_reg: ldo1 { +- /* LDO1_OUT --> VDA_PHY1_1V8 */ +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-allow-bypass; +- }; +- +- ldo2_reg: ldo2 { +- /* LDO2_OUT --> VDA_PHY2_1V8 */ +- regulator-name = "ldo2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-allow-bypass; +- regulator-always-on; +- }; +- +- ldo3_reg: ldo3 { +- /* VDA_USB_3V3 */ +- regulator-name = "ldo3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo5_reg: ldo5 { +- /* VDDA_1V8_PLL */ +- regulator-name = "ldo5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo4_reg: ldo4 { +- /* VDD_SDIO_DV */ +- regulator-name = "ldo4"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +- +- tps65917_power_button { +- compatible = "ti,palmas-pwrbutton"; +- interrupt-parent = <&tps65917>; +- interrupts = <1 IRQ_TYPE_NONE>; +- wakeup-source; +- ti,palmas-long-press-seconds = <6>; +- }; +- }; +- +- lp87565: lp87565@60 { +- compatible = "ti,lp87565-q1"; +- reg = <0x60>; +- +- buck10-in-supply =<&vsys_3v3>; +- buck23-in-supply =<&vsys_3v3>; +- +- regulators: regulators { +- buck10_reg: buck10 { +- /*VDD_MPU*/ +- regulator-name = "buck10"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck23_reg: buck23 { +- /* VDD_GPU*/ +- regulator-name = "buck23"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +- +- pcf_lcd: pcf8757@20 { +- compatible = "nxp,pcf8575"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupt-parent = <&gpio1>; +- interrupts = <3 IRQ_TYPE_EDGE_FALLING>; +- }; +- +- pcf_gpio_21: pcf8757@21 { +- compatible = "nxp,pcf8575"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gpio1>; +- interrupts = <3 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pcf_hdmi: pcf8575@26 { +- compatible = "nxp,pcf8575"; +- reg = <0x26>; +- gpio-controller; +- #gpio-cells = <2>; +- hdmi-audio-hog { +- /* vin6_sel_s0: high: VIN6, low: audio */ +- gpio-hog; +- gpios = <1 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "vin6_sel_s0"; +- }; +- }; +- +- tlv320aic3106: tlv320aic3106@19 { +- #sound-dai-cells = <0>; +- compatible = "ti,tlv320aic3106"; +- reg = <0x19>; +- adc-settle-ms = <40>; +- ai3x-micbias-vg = <1>; /* 2.0V */ +- status = "okay"; +- +- /* Regulators */ +- AVDD-supply = <&vio_3v3>; +- IOVDD-supply = <&vio_3v3>; +- DRVDD-supply = <&vio_3v3>; +- DVDD-supply = <&aic_dvdd>; +- }; +-}; +- +-&cpu0 { +- vdd-supply = <&buck10_reg>; +-}; +- +-&mmc1 { +- status = "okay"; +- vmmc-supply = <&vio_3v3_sd>; +- vqmmc-supply = <&ldo4_reg>; +- bus-width = <4>; +- /* +- * SDCD signal is not being used here - using the fact that GPIO mode +- * is always hardwired. +- */ +- cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default", "hs"; +- pinctrl-0 = <&mmc1_pins_default>; +- pinctrl-1 = <&mmc1_pins_hs>; +-}; +- +-&mmc2 { +- status = "okay"; +- vmmc-supply = <&vio_1v8>; +- vqmmc-supply = <&vio_1v8>; +- bus-width = <8>; +- non-removable; +- pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; +- pinctrl-0 = <&mmc2_pins_default>; +- pinctrl-1 = <&mmc2_pins_default>; +- pinctrl-2 = <&mmc2_pins_default>; +- pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>; +-}; +- +-&mmc4 { +- status = "okay"; +- vmmc-supply = <&vio_3v6>; +- vqmmc-supply = <&vmmcwl_fixed>; +- pinctrl-names = "default", "hs", "sdr12", "sdr25"; +- pinctrl-0 = <&mmc4_pins_hs &mmc4_iodelay_default_conf>; +- pinctrl-1 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; +- pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; +- pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; +-}; +- +-/* No RTC on this device */ +-&rtc { +- status = "disabled"; +-}; +- +-&mac_sw { +- status = "okay"; +-}; +- +-&cpsw_port1 { +- phy-handle = <&dp83867_0>; +- phy-mode = "rgmii-id"; +- ti,dual-emac-pvid = <1>; +-}; +- +-&cpsw_port2 { +- phy-handle = <&dp83867_1>; +- phy-mode = "rgmii-id"; +- ti,dual-emac-pvid = <2>; +-}; +- +-&davinci_mdio_sw { +- dp83867_0: ethernet-phy@2 { +- reg = <2>; +- ti,rx-internal-delay = ; +- ti,tx-internal-delay = ; +- ti,fifo-depth = ; +- ti,min-output-impedance; +- ti,dp83867-rxctrl-strap-quirk; +- }; +- +- dp83867_1: ethernet-phy@3 { +- reg = <3>; +- ti,rx-internal-delay = ; +- ti,tx-internal-delay = ; +- ti,fifo-depth = ; +- ti,min-output-impedance; +- ti,dp83867-rxctrl-strap-quirk; +- }; +-}; +- +-&usb2_phy1 { +- phy-supply = <&ldo3_reg>; +-}; +- +-&usb2_phy2 { +- phy-supply = <&ldo3_reg>; +-}; +- +-&dss { +- status = "okay"; +- vdda_video-supply = <&ldo5_reg>; +-}; +- +-&hdmi { +- status = "okay"; +- +- vdda-supply = <&ldo1_reg>; +- +- port { +- hdmi_out: endpoint { +- remote-endpoint = <&tpd12s015_in>; +- }; +- }; +-}; +- +-&qspi { +- spi-max-frequency = <96000000>; +- m25p80@0 { +- spi-max-frequency = <96000000>; +- }; +-}; +- +-&pcie2_phy { +- status = "okay"; +-}; +- +-&pcie1_rc { +- num-lanes = <2>; +- phys = <&pcie1_phy>, <&pcie2_phy>; +- phy-names = "pcie-phy0", "pcie-phy1"; +-}; +- +-&pcie1_ep { +- num-lanes = <2>; +- phys = <&pcie1_phy>, <&pcie2_phy>; +- phy-names = "pcie-phy0", "pcie-phy1"; +-}; +- +-&extcon_usb1 { +- vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>; +-}; +- +-&extcon_usb2 { +- vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>; +-}; +- +-&m_can0 { +- can-transceiver { +- max-bitrate = <5000000>; +- }; +-}; +- +-&ipu2 { +- status = "okay"; +- memory-region = <&ipu2_cma_pool>; +-}; +- +-&ipu1 { +- status = "okay"; +- memory-region = <&ipu1_cma_pool>; +-}; +- +-&dsp1 { +- status = "okay"; +- memory-region = <&dsp1_cma_pool>; +-}; +- +-&dsp2 { +- status = "okay"; +- memory-region = <&dsp2_cma_pool>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra76x-mmc-iodelay.dtsi b/scripts/dtc/include-prefixes/arm/dra76x-mmc-iodelay.dtsi +deleted file mode 100644 +index fdca48186916..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra76x-mmc-iodelay.dtsi ++++ /dev/null +@@ -1,285 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2018 Texas Instruments +-// MMC IOdelay values for TI's DRA76x and AM576x SoCs. +-// Author: Sekhar Nori +- +-/* +- * Rules for modifying this file: +- * a) Update of this file should typically correspond to a datamanual revision. +- * Datamanual revision that was used should be updated in comment below. +- * If there is no update to datamanual, do not update the values. If you +- * need to use values different from that recommended by the datamanual +- * for your design, then you should consider adding values to the device- +- * -tree file for your board directly. +- * b) We keep the mode names as close to the datamanual as possible. So +- * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, +- * we follow that in code too. +- * c) If the values change between multiple revisions of silicon, we add +- * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1, +- * 'rev20' for PG 2.0 and so on. +- * d) The node name and node label should be the exact same string. This is +- * to curb naming creativity and achieve consistency. +- * +- * Datamanual Revisions: +- * +- * DRA76x Silicon Revision 1.0: SPRS993E, Revised December 2018 +- * +- */ +- +-&dra7_pmx_core { +- mmc1_pins_default: mmc1_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +- +- mmc1_pins_hs: mmc1_pins_hs { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +- +- mmc1_pins_sdr50: mmc1_pins_sdr50 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +- +- mmc1_pins_ddr50: mmc1_pins_ddr50 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +- +- mmc2_pins_default: mmc2_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ +- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ +- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ +- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ +- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ +- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ +- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ +- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ +- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ +- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ +- >; +- }; +- +- mmc2_pins_hs200: mmc2_pins_hs200 { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ +- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ +- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ +- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ +- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ +- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ +- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ +- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ +- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ +- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ +- >; +- }; +- +- mmc3_pins_default: mmc3_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ +- DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ +- DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ +- DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ +- DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ +- DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ +- >; +- }; +- +- mmc4_pins_hs: mmc4_pins_hs { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ +- DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ +- DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ +- DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ +- DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ +- DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ +- >; +- }; +-}; +- +-&dra7_iodelay_core { +- +- /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ +- mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf { +- pinctrl-pin-array = < +- 0x618 A_DELAY_PS(489) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */ +- 0x624 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ +- 0x630 A_DELAY_PS(374) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ +- 0x63c A_DELAY_PS(31) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ +- 0x648 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ +- 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ +- 0x620 A_DELAY_PS(1355) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ +- 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ +- 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ +- 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ +- 0x638 A_DELAY_PS(0) G_DELAY_PS(4) /* CFG_MMC1_DAT0_OUT */ +- 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ +- 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ +- 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ +- 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ +- 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ +- 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ +- >; +- }; +- +- /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ +- mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf { +- pinctrl-pin-array = < +- 0x620 A_DELAY_PS(892) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ +- 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ +- 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ +- 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ +- 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ +- 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ +- 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ +- 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ +- 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ +- 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ +- 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ +- >; +- }; +- +- /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ +- mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf { +- pinctrl-pin-array = < +- 0x190 A_DELAY_PS(384) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ +- 0x194 A_DELAY_PS(350) G_DELAY_PS(174) /* CFG_GPMC_A19_OUT */ +- 0x1a8 A_DELAY_PS(410) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ +- 0x1ac A_DELAY_PS(335) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ +- 0x1b4 A_DELAY_PS(468) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ +- 0x1b8 A_DELAY_PS(339) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ +- 0x1c0 A_DELAY_PS(676) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ +- 0x1c4 A_DELAY_PS(219) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ +- 0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154) /* CFG_GPMC_A23_OUT */ +- 0x1d8 A_DELAY_PS(640) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ +- 0x1dc A_DELAY_PS(150) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ +- 0x1e4 A_DELAY_PS(356) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ +- 0x1e8 A_DELAY_PS(150) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ +- 0x1f0 A_DELAY_PS(579) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ +- 0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ +- 0x1fc A_DELAY_PS(435) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ +- 0x200 A_DELAY_PS(236) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ +- 0x364 A_DELAY_PS(759) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ +- 0x368 A_DELAY_PS(372) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ +- >; +- }; +- +- /* Corresponds to MMC3_MANUAL1 in datamanual */ +- mmc3_iodelay_manual1_conf: mmc3_iodelay_manual1_conf { +- pinctrl-pin-array = < +- 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */ +- 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ +- 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ +- 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ +- 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ +- 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ +- 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ +- 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ +- 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ +- 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ +- 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ +- 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ +- 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ +- 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ +- 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ +- 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ +- 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ +- >; +- }; +- +- /* Corresponds to MMC3_MANUAL2 in datamanual */ +- mmc3_iodelay_sdr50_conf: mmc3_iodelay_sdr50_conf { +- pinctrl-pin-array = < +- 0x678 A_DELAY_PS(852) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */ +- 0x680 A_DELAY_PS(94) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ +- 0x684 A_DELAY_PS(122) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ +- 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ +- 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ +- 0x690 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ +- 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ +- 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ +- 0x69c A_DELAY_PS(57) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ +- 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ +- 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ +- 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ +- 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ +- 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ +- 0x6b4 A_DELAY_PS(375) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ +- 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ +- 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ +- >; +- }; +- +- /* Corresponds to MMC4_MANUAL1 in datamanual */ +- mmc4_iodelay_manual1_conf: mmc4_iodelay_manual1_conf { +- pinctrl-pin-array = < +- 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ +- 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ +- 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ +- 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ +- 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ +- 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ +- 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ +- 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ +- 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */ +- 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ +- 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ +- 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */ +- 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ +- 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ +- 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */ +- 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ +- 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ +- >; +- }; +- +- /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ +- mmc4_iodelay_default_conf: mmc4_iodelay_default_conf { +- pinctrl-pin-array = < +- 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ +- 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ +- 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ +- 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ +- 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ +- 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ +- 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ +- 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ +- 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ +- 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ +- 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ +- 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ +- 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ +- 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ +- 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ +- 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ +- 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra76x.dtsi b/scripts/dtc/include-prefixes/arm/dra76x.dtsi +deleted file mode 100644 +index bc4ae91cba16..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra76x.dtsi ++++ /dev/null +@@ -1,159 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include "dra74x.dtsi" +- +-/ { +- compatible = "ti,dra762", "ti,dra7"; +- +- ocp { +- target-module@42c01900 { +- compatible = "ti,sysc-dra7-mcan", "ti,sysc"; +- ranges = <0x0 0x42c00000 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x42c01900 0x4>, +- <0x42c01904 0x4>, +- <0x42c01908 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET | +- SYSC_DRA7_MCAN_ENAWAKEUP)>; +- ti,syss-mask = <1>; +- clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>; +- clock-names = "fck"; +- +- m_can0: mcan@1a00 { +- compatible = "bosch,m_can"; +- reg = <0x1a00 0x4000>, <0x0 0x18FC>; +- reg-names = "m_can", "message_ram"; +- interrupt-parent = <&gic>; +- interrupts = , +- ; +- interrupt-names = "int0", "int1"; +- clocks = <&l3_iclk_div>, <&mcan_clk>; +- clock-names = "hclk", "cclk"; +- bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>; +- }; +- }; +- }; +- +-}; +- +-&l4_per3 { +- target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x1b0000 0x4>, +- <0x1b0010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- ; +- ti,sysc-sidle = , +- ; +- clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1b0000 0x10000>; +- +- cal: cal@0 { +- compatible = "ti,dra76-cal"; +- reg = <0x0000 0x400>, +- <0x0800 0x40>, +- <0x0900 0x40>; +- reg-names = "cal_top", +- "cal_rx_core0", +- "cal_rx_core1"; +- interrupts = ; +- ti,camerrx-control = <&scm_conf 0x6dc>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- csi2_0: port@0 { +- reg = <0>; +- }; +- csi2_1: port@1 { +- reg = <1>; +- }; +- }; +- }; +- }; +-}; +- +-&scm_conf_clocks { +- dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_gmac_x2_ck>; +- ti,max-div = <63>; +- reg = <0x03fc>; +- ti,bit-shift=<20>; +- ti,latch-bit=<26>; +- assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>; +- assigned-clock-rates = <80000000>; +- }; +- +- dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>; +- reg = <0x3fc>; +- ti,bit-shift = <29>; +- ti,latch-bit=<26>; +- assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; +- assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>; +- }; +- +- mcan_clk: mcan_clk@3fc { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; +- ti,bit-shift = <27>; +- reg = <0x3fc>; +- }; +-}; +- +-&rtctarget { +- status = "disabled"; +-}; +- +-&usb4_tm { +- status = "disabled"; +-}; +- +-&mmc3 { +- /* dra76x is not affected by i887 */ +- max-frequency = <96000000>; +-}; +- +-&cpu0_opp_table { +- opp_plus@1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <1250000 950000 1250000>, +- <1250000 950000 1250000>; +- opp-supported-hw = <0xFF 0x08>; +- }; +-}; +- +-&opp_supply_mpu { +- ti,efuse-settings = < +- /* uV offset */ +- 1060000 0x0 +- 1160000 0x4 +- 1210000 0x8 +- 1250000 0xC +- >; +-}; +- +-&abb_mpu { +- ti,abb_info = < +- /*uV ABB efuse rbb_m fbb_m vset_m*/ +- 1060000 0 0x0 0 0x02000000 0x01F00000 +- 1160000 0 0x4 0 0x02000000 0x01F00000 +- 1210000 0 0x8 0 0x02000000 0x01F00000 +- 1250000 0 0xC 0 0x02000000 0x01F00000 +- >; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/dra7xx-clocks.dtsi b/scripts/dtc/include-prefixes/arm/dra7xx-clocks.dtsi +deleted file mode 100644 +index 2365554eef3c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/dra7xx-clocks.dtsi ++++ /dev/null +@@ -1,1863 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for DRA7xx clock data +- * +- * Copyright (C) 2013 Texas Instruments, Inc. +- */ +-&cm_core_aon_clocks { +- atl_clkin0_ck: atl_clkin0_ck { +- #clock-cells = <0>; +- compatible = "ti,dra7-atl-clock"; +- clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; +- }; +- +- atl_clkin1_ck: atl_clkin1_ck { +- #clock-cells = <0>; +- compatible = "ti,dra7-atl-clock"; +- clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; +- }; +- +- atl_clkin2_ck: atl_clkin2_ck { +- #clock-cells = <0>; +- compatible = "ti,dra7-atl-clock"; +- clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; +- }; +- +- atl_clkin3_ck: atl_clkin3_ck { +- #clock-cells = <0>; +- compatible = "ti,dra7-atl-clock"; +- clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; +- }; +- +- hdmi_clkin_ck: hdmi_clkin_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- mlb_clkin_ck: mlb_clkin_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- mlbp_clkin_ck: mlbp_clkin_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- pciesref_acs_clk_ck: pciesref_acs_clk_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <100000000>; +- }; +- +- ref_clkin0_ck: ref_clkin0_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- ref_clkin1_ck: ref_clkin1_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- ref_clkin2_ck: ref_clkin2_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- ref_clkin3_ck: ref_clkin3_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- rmii_clk_ck: rmii_clk_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- sdvenc_clkin_ck: sdvenc_clkin_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- secure_32k_clk_src_ck: secure_32k_clk_src_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- sys_clk32_crystal_ck: sys_clk32_crystal_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- sys_clk32_pseudo_ck: sys_clk32_pseudo_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin1>; +- clock-mult = <1>; +- clock-div = <610>; +- }; +- +- virt_12000000_ck: virt_12000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <12000000>; +- }; +- +- virt_13000000_ck: virt_13000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <13000000>; +- }; +- +- virt_16800000_ck: virt_16800000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <16800000>; +- }; +- +- virt_19200000_ck: virt_19200000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <19200000>; +- }; +- +- virt_20000000_ck: virt_20000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <20000000>; +- }; +- +- virt_26000000_ck: virt_26000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- }; +- +- virt_27000000_ck: virt_27000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <27000000>; +- }; +- +- virt_38400000_ck: virt_38400000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <38400000>; +- }; +- +- sys_clkin2: sys_clkin2 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <22579200>; +- }; +- +- usb_otg_clkin_ck: usb_otg_clkin_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- video1_clkin_ck: video1_clkin_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- video1_m2_clkin_ck: video1_m2_clkin_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- video2_clkin_ck: video2_clkin_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- video2_m2_clkin_ck: video2_m2_clkin_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- dpll_abe_ck: dpll_abe_ck@1e0 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-m4xen-clock"; +- clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; +- reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; +- }; +- +- dpll_abe_x2_ck: dpll_abe_x2_ck { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-x2-clock"; +- clocks = <&dpll_abe_ck>; +- }; +- +- dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_abe_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x01f0>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- abe_clk: abe_clk@108 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_abe_m2x2_ck>; +- ti,max-div = <4>; +- reg = <0x0108>; +- ti,index-power-of-two; +- }; +- +- dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_abe_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x01f0>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_abe_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x01f4>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_core_byp_mux: dpll_core_byp_mux@12c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; +- ti,bit-shift = <23>; +- reg = <0x012c>; +- }; +- +- dpll_core_ck: dpll_core_ck@120 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-core-clock"; +- clocks = <&sys_clkin1>, <&dpll_core_byp_mux>; +- reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; +- }; +- +- dpll_core_x2_ck: dpll_core_x2_ck { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-x2-clock"; +- clocks = <&dpll_core_ck>; +- }; +- +- dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <63>; +- ti,autoidle-shift = <8>; +- reg = <0x013c>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_h12x2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dpll_mpu_ck: dpll_mpu_ck@160 { +- #clock-cells = <0>; +- compatible = "ti,omap5-mpu-dpll-clock"; +- clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; +- reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; +- }; +- +- dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_mpu_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x0170>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- mpu_dclk_div: mpu_dclk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_mpu_m2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_h12x2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; +- ti,bit-shift = <23>; +- reg = <0x0240>; +- }; +- +- dpll_dsp_ck: dpll_dsp_ck@234 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-clock"; +- clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; +- reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; +- assigned-clocks = <&dpll_dsp_ck>; +- assigned-clock-rates = <600000000>; +- }; +- +- dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_dsp_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x0244>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- assigned-clocks = <&dpll_dsp_m2_ck>; +- assigned-clock-rates = <600000000>; +- }; +- +- iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_h12x2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; +- ti,bit-shift = <23>; +- reg = <0x01ac>; +- }; +- +- dpll_iva_ck: dpll_iva_ck@1a0 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-clock"; +- clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; +- reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; +- assigned-clocks = <&dpll_iva_ck>; +- assigned-clock-rates = <1165000000>; +- }; +- +- dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_iva_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x01b0>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- assigned-clocks = <&dpll_iva_m2_ck>; +- assigned-clock-rates = <388333334>; +- }; +- +- iva_dclk: iva_dclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_iva_m2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; +- ti,bit-shift = <23>; +- reg = <0x02e4>; +- }; +- +- dpll_gpu_ck: dpll_gpu_ck@2d8 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-clock"; +- clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; +- reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; +- assigned-clocks = <&dpll_gpu_ck>; +- assigned-clock-rates = <1277000000>; +- }; +- +- dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_gpu_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x02e8>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- assigned-clocks = <&dpll_gpu_m2_ck>; +- assigned-clock-rates = <425666667>; +- }; +- +- dpll_core_m2_ck: dpll_core_m2_ck@130 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x0130>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- core_dpll_out_dclk_div: core_dpll_out_dclk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_m2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; +- ti,bit-shift = <23>; +- reg = <0x021c>; +- }; +- +- dpll_ddr_ck: dpll_ddr_ck@210 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-clock"; +- clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>; +- reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; +- }; +- +- dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_ddr_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x0220>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; +- ti,bit-shift = <23>; +- reg = <0x02b4>; +- }; +- +- dpll_gmac_ck: dpll_gmac_ck@2a8 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-clock"; +- clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>; +- reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; +- }; +- +- dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_gmac_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x02b8>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- video2_dclk_div: video2_dclk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&video2_m2_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- video1_dclk_div: video1_dclk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&video1_m2_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- hdmi_dclk_div: hdmi_dclk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&hdmi_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- per_dpll_hs_clk_div: per_dpll_hs_clk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_abe_m3x2_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_abe_m3x2_ck>; +- clock-mult = <1>; +- clock-div = <3>; +- }; +- +- eve_dpll_hs_clk_div: eve_dpll_hs_clk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_h12x2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dpll_eve_byp_mux: dpll_eve_byp_mux@290 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; +- ti,bit-shift = <23>; +- reg = <0x0290>; +- }; +- +- dpll_eve_ck: dpll_eve_ck@284 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-clock"; +- clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>; +- reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; +- }; +- +- dpll_eve_m2_ck: dpll_eve_m2_ck@294 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_eve_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x0294>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- eve_dclk_div: eve_dclk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_eve_m2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <63>; +- ti,autoidle-shift = <8>; +- reg = <0x0140>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <63>; +- ti,autoidle-shift = <8>; +- reg = <0x0144>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <63>; +- ti,autoidle-shift = <8>; +- reg = <0x0154>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <63>; +- ti,autoidle-shift = <8>; +- reg = <0x0158>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <63>; +- ti,autoidle-shift = <8>; +- reg = <0x015c>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_ddr_x2_ck: dpll_ddr_x2_ck { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-x2-clock"; +- clocks = <&dpll_ddr_ck>; +- }; +- +- dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_ddr_x2_ck>; +- ti,max-div = <63>; +- ti,autoidle-shift = <8>; +- reg = <0x0228>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_dsp_x2_ck: dpll_dsp_x2_ck { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-x2-clock"; +- clocks = <&dpll_dsp_ck>; +- }; +- +- dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_dsp_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x0248>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- assigned-clocks = <&dpll_dsp_m3x2_ck>; +- assigned-clock-rates = <400000000>; +- }; +- +- dpll_gmac_x2_ck: dpll_gmac_x2_ck { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-x2-clock"; +- clocks = <&dpll_gmac_ck>; +- }; +- +- dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_gmac_x2_ck>; +- ti,max-div = <63>; +- ti,autoidle-shift = <8>; +- reg = <0x02c0>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_gmac_x2_ck>; +- ti,max-div = <63>; +- ti,autoidle-shift = <8>; +- reg = <0x02c4>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_gmac_x2_ck>; +- ti,max-div = <63>; +- ti,autoidle-shift = <8>; +- reg = <0x02c8>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_gmac_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x02bc>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- gmii_m_clk_div: gmii_m_clk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_gmac_h11x2_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- hdmi_clk2_div: hdmi_clk2_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&hdmi_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- hdmi_div_clk: hdmi_div_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&hdmi_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- l3_iclk_div: l3_iclk_div@100 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- ti,max-div = <2>; +- ti,bit-shift = <4>; +- reg = <0x0100>; +- clocks = <&dpll_core_h12x2_ck>; +- ti,index-power-of-two; +- }; +- +- l4_root_clk_div: l4_root_clk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&l3_iclk_div>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- video1_clk2_div: video1_clk2_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&video1_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- video1_div_clk: video1_div_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&video1_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- video2_clk2_div: video2_clk2_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&video2_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- video2_div_clk: video2_div_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&video2_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dummy_ck: dummy_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +-}; +-&prm_clocks { +- sys_clkin1: sys_clkin1@110 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; +- reg = <0x0110>; +- ti,index-starts-at-one; +- }; +- +- abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin1>, <&sys_clkin2>; +- reg = <0x0118>; +- }; +- +- abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; +- reg = <0x0114>; +- }; +- +- abe_dpll_clk_mux: abe_dpll_clk_mux@10c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; +- reg = <0x010c>; +- }; +- +- abe_24m_fclk: abe_24m_fclk@11c { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_abe_m2x2_ck>; +- reg = <0x011c>; +- ti,dividers = <8>, <16>; +- }; +- +- aess_fclk: aess_fclk@178 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&abe_clk>; +- reg = <0x0178>; +- ti,max-div = <2>; +- }; +- +- abe_giclk_div: abe_giclk_div@174 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&aess_fclk>; +- reg = <0x0174>; +- ti,max-div = <2>; +- }; +- +- abe_lp_clk_div: abe_lp_clk_div@1d8 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_abe_m2x2_ck>; +- reg = <0x01d8>; +- ti,dividers = <16>, <32>; +- }; +- +- abe_sys_clk_div: abe_sys_clk_div@120 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&sys_clkin1>; +- reg = <0x0120>; +- ti,max-div = <2>; +- }; +- +- adc_gfclk_mux: adc_gfclk_mux@1dc { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>; +- reg = <0x01dc>; +- }; +- +- sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&sys_clkin1>; +- ti,max-div = <64>; +- reg = <0x01c8>; +- ti,index-power-of-two; +- }; +- +- sys_clk2_dclk_div: sys_clk2_dclk_div@1cc { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&sys_clkin2>; +- ti,max-div = <64>; +- reg = <0x01cc>; +- ti,index-power-of-two; +- }; +- +- per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_abe_m2_ck>; +- ti,max-div = <64>; +- reg = <0x01bc>; +- ti,index-power-of-two; +- }; +- +- dsp_gclk_div: dsp_gclk_div@18c { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_dsp_m2_ck>; +- ti,max-div = <64>; +- reg = <0x018c>; +- ti,index-power-of-two; +- }; +- +- gpu_dclk: gpu_dclk@1a0 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_gpu_m2_ck>; +- ti,max-div = <64>; +- reg = <0x01a0>; +- ti,index-power-of-two; +- }; +- +- emif_phy_dclk_div: emif_phy_dclk_div@190 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_ddr_m2_ck>; +- ti,max-div = <64>; +- reg = <0x0190>; +- ti,index-power-of-two; +- }; +- +- gmac_250m_dclk_div: gmac_250m_dclk_div@19c { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_gmac_m2_ck>; +- ti,max-div = <64>; +- reg = <0x019c>; +- ti,index-power-of-two; +- }; +- +- gmac_main_clk: gmac_main_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&gmac_250m_dclk_div>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- l3init_480m_dclk_div: l3init_480m_dclk_div@1ac { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_usb_m2_ck>; +- ti,max-div = <64>; +- reg = <0x01ac>; +- ti,index-power-of-two; +- }; +- +- usb_otg_dclk_div: usb_otg_dclk_div@184 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&usb_otg_clkin_ck>; +- ti,max-div = <64>; +- reg = <0x0184>; +- ti,index-power-of-two; +- }; +- +- sata_dclk_div: sata_dclk_div@1c0 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&sys_clkin1>; +- ti,max-div = <64>; +- reg = <0x01c0>; +- ti,index-power-of-two; +- }; +- +- pcie2_dclk_div: pcie2_dclk_div@1b8 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_pcie_ref_m2_ck>; +- ti,max-div = <64>; +- reg = <0x01b8>; +- ti,index-power-of-two; +- }; +- +- pcie_dclk_div: pcie_dclk_div@1b4 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&apll_pcie_m2_ck>; +- ti,max-div = <64>; +- reg = <0x01b4>; +- ti,index-power-of-two; +- }; +- +- emu_dclk_div: emu_dclk_div@194 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&sys_clkin1>; +- ti,max-div = <64>; +- reg = <0x0194>; +- ti,index-power-of-two; +- }; +- +- secure_32k_dclk_div: secure_32k_dclk_div@1c4 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&secure_32k_clk_src_ck>; +- ti,max-div = <64>; +- reg = <0x01c4>; +- ti,index-power-of-two; +- }; +- +- clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; +- reg = <0x0158>; +- }; +- +- clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; +- reg = <0x015c>; +- }; +- +- clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; +- reg = <0x0160>; +- }; +- +- custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin1>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- eve_clk: eve_clk@180 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>; +- reg = <0x0180>; +- }; +- +- hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin1>, <&sys_clkin2>; +- reg = <0x0164>; +- }; +- +- mlb_clk: mlb_clk@134 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&mlb_clkin_ck>; +- ti,max-div = <64>; +- reg = <0x0134>; +- ti,index-power-of-two; +- }; +- +- mlbp_clk: mlbp_clk@130 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&mlbp_clkin_ck>; +- ti,max-div = <64>; +- reg = <0x0130>; +- ti,index-power-of-two; +- }; +- +- per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_abe_m2_ck>; +- ti,max-div = <64>; +- reg = <0x0138>; +- ti,index-power-of-two; +- }; +- +- timer_sys_clk_div: timer_sys_clk_div@144 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&sys_clkin1>; +- reg = <0x0144>; +- ti,max-div = <2>; +- }; +- +- video1_dpll_clk_mux: video1_dpll_clk_mux@168 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin1>, <&sys_clkin2>; +- reg = <0x0168>; +- }; +- +- video2_dpll_clk_mux: video2_dpll_clk_mux@16c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin1>, <&sys_clkin2>; +- reg = <0x016c>; +- }; +- +- wkupaon_iclk_mux: wkupaon_iclk_mux@108 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin1>, <&abe_lp_clk_div>; +- reg = <0x0108>; +- }; +-}; +- +-&cm_core_clocks { +- dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-clock"; +- clocks = <&sys_clkin1>, <&sys_clkin1>; +- reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; +- }; +- +- dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_pcie_ref_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x0210>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { +- compatible = "ti,mux-clock"; +- clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; +- #clock-cells = <0>; +- reg = <0x021c 0x4>; +- ti,bit-shift = <7>; +- }; +- +- apll_pcie_ck: apll_pcie_ck@21c { +- #clock-cells = <0>; +- compatible = "ti,dra7-apll-clock"; +- clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; +- reg = <0x021c>, <0x0220>; +- }; +- +- optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { +- compatible = "ti,divider-clock"; +- clocks = <&apll_pcie_ck>; +- #clock-cells = <0>; +- reg = <0x021c>; +- ti,dividers = <2>, <1>; +- ti,bit-shift = <8>; +- ti,max-div = <2>; +- }; +- +- apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&apll_pcie_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&apll_pcie_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- apll_pcie_m2_ck: apll_pcie_m2_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&apll_pcie_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dpll_per_byp_mux: dpll_per_byp_mux@14c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; +- ti,bit-shift = <23>; +- reg = <0x014c>; +- }; +- +- dpll_per_ck: dpll_per_ck@140 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-clock"; +- clocks = <&sys_clkin1>, <&dpll_per_byp_mux>; +- reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; +- }; +- +- dpll_per_m2_ck: dpll_per_m2_ck@150 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x0150>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- func_96m_aon_dclk_div: func_96m_aon_dclk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dpll_usb_byp_mux: dpll_usb_byp_mux@18c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; +- ti,bit-shift = <23>; +- reg = <0x018c>; +- }; +- +- dpll_usb_ck: dpll_usb_ck@180 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-j-type-clock"; +- clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>; +- reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; +- }; +- +- dpll_usb_m2_ck: dpll_usb_m2_ck@190 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_usb_ck>; +- ti,max-div = <127>; +- ti,autoidle-shift = <8>; +- reg = <0x0190>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_pcie_ref_ck>; +- ti,max-div = <127>; +- ti,autoidle-shift = <8>; +- reg = <0x0210>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_per_x2_ck: dpll_per_x2_ck { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-x2-clock"; +- clocks = <&dpll_per_ck>; +- }; +- +- dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_x2_ck>; +- ti,max-div = <63>; +- ti,autoidle-shift = <8>; +- reg = <0x0158>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_x2_ck>; +- ti,max-div = <63>; +- ti,autoidle-shift = <8>; +- reg = <0x015c>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_x2_ck>; +- ti,max-div = <63>; +- ti,autoidle-shift = <8>; +- reg = <0x0160>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_x2_ck>; +- ti,max-div = <63>; +- ti,autoidle-shift = <8>; +- reg = <0x0164>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x0150>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_usb_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- func_128m_clk: func_128m_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_h11x2_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- func_12m_fclk: func_12m_fclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2x2_ck>; +- clock-mult = <1>; +- clock-div = <16>; +- }; +- +- func_24m_clk: func_24m_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2_ck>; +- clock-mult = <1>; +- clock-div = <4>; +- }; +- +- func_48m_fclk: func_48m_fclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2x2_ck>; +- clock-mult = <1>; +- clock-div = <4>; +- }; +- +- func_96m_fclk: func_96m_fclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2x2_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- l3init_60m_fclk: l3init_60m_fclk@104 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_usb_m2_ck>; +- reg = <0x0104>; +- ti,dividers = <1>, <8>; +- }; +- +- clkout2_clk: clkout2_clk@6b0 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&clkoutmux2_clk_mux>; +- ti,bit-shift = <8>; +- reg = <0x06b0>; +- }; +- +- l3init_960m_gfclk: l3init_960m_gfclk@6c0 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&dpll_usb_clkdcoldo>; +- ti,bit-shift = <8>; +- reg = <0x06c0>; +- }; +- +- usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&sys_32k_ck>; +- ti,bit-shift = <8>; +- reg = <0x0640>; +- }; +- +- usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&sys_32k_ck>; +- ti,bit-shift = <8>; +- reg = <0x0688>; +- }; +- +- usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&sys_32k_ck>; +- ti,bit-shift = <8>; +- reg = <0x0698>; +- }; +- +- gpu_core_gclk_mux: gpu_core_gclk_mux@1220 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; +- ti,bit-shift = <24>; +- reg = <0x1220>; +- assigned-clocks = <&gpu_core_gclk_mux>; +- assigned-clock-parents = <&dpll_gpu_m2_ck>; +- }; +- +- gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; +- ti,bit-shift = <26>; +- reg = <0x1220>; +- assigned-clocks = <&gpu_hyd_gclk_mux>; +- assigned-clock-parents = <&dpll_gpu_m2_ck>; +- }; +- +- l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&wkupaon_iclk_mux>; +- ti,bit-shift = <24>; +- reg = <0x0e50>; +- ti,dividers = <8>, <16>, <32>; +- }; +- +- vip1_gclk_mux: vip1_gclk_mux@1020 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; +- ti,bit-shift = <24>; +- reg = <0x1020>; +- }; +- +- vip2_gclk_mux: vip2_gclk_mux@1028 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; +- ti,bit-shift = <24>; +- reg = <0x1028>; +- }; +- +- vip3_gclk_mux: vip3_gclk_mux@1030 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; +- ti,bit-shift = <24>; +- reg = <0x1030>; +- }; +-}; +- +-&cm_core_clockdomains { +- coreaon_clkdm: coreaon_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&dpll_usb_ck>; +- }; +-}; +- +-&scm_conf_clocks { +- dss_deshdcp_clk: dss_deshdcp_clk@558 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&l3_iclk_div>; +- ti,bit-shift = <0>; +- reg = <0x558>; +- }; +- +- ehrpwm0_tbclk: ehrpwm0_tbclk@558 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&l4_root_clk_div>; +- ti,bit-shift = <20>; +- reg = <0x0558>; +- }; +- +- ehrpwm1_tbclk: ehrpwm1_tbclk@558 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&l4_root_clk_div>; +- ti,bit-shift = <21>; +- reg = <0x0558>; +- }; +- +- ehrpwm2_tbclk: ehrpwm2_tbclk@558 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&l4_root_clk_div>; +- ti,bit-shift = <22>; +- reg = <0x0558>; +- }; +- +- sys_32k_ck: sys_32k_ck { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>; +- ti,bit-shift = <8>; +- reg = <0x6c4>; +- }; +-}; +- +-&cm_core_aon { +- mpu_cm: mpu-cm@300 { +- compatible = "ti,omap4-cm"; +- reg = <0x300 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x300 0x100>; +- +- mpu_clkctrl: mpu-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- +- }; +- +- dsp1_cm: dsp1-cm@400 { +- compatible = "ti,omap4-cm"; +- reg = <0x400 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x400 0x100>; +- +- dsp1_clkctrl: dsp1-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- +- }; +- +- ipu_cm: ipu-cm@500 { +- compatible = "ti,omap4-cm"; +- reg = <0x500 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x500 0x100>; +- +- ipu1_clkctrl: ipu1-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>; +- assigned-clock-parents = <&dpll_core_h22x2_ck>; +- }; +- +- ipu_clkctrl: ipu-clkctrl@50 { +- compatible = "ti,clkctrl"; +- reg = <0x50 0x34>; +- #clock-cells = <2>; +- }; +- +- }; +- +- dsp2_cm: dsp2-cm@600 { +- compatible = "ti,omap4-cm"; +- reg = <0x600 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x600 0x100>; +- +- dsp2_clkctrl: dsp2-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- +- }; +- +- rtc_cm: rtc-cm@700 { +- compatible = "ti,omap4-cm"; +- reg = <0x700 0x60>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x700 0x60>; +- +- rtc_clkctrl: rtc-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x28>; +- #clock-cells = <2>; +- }; +- }; +- +- vpe_cm: vpe-cm@760 { +- compatible = "ti,omap4-cm"; +- reg = <0x760 0xc>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x760 0xc>; +- +- vpe_clkctrl: vpe-clkctrl@0 { +- compatible = "ti,clkctrl"; +- reg = <0x0 0xc>; +- #clock-cells = <2>; +- }; +- }; +- +-}; +- +-&cm_core { +- coreaon_cm: coreaon-cm@600 { +- compatible = "ti,omap4-cm"; +- reg = <0x600 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x600 0x100>; +- +- coreaon_clkctrl: coreaon-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x1c>; +- #clock-cells = <2>; +- }; +- }; +- +- l3main1_cm: l3main1-cm@700 { +- compatible = "ti,omap4-cm"; +- reg = <0x700 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x700 0x100>; +- +- l3main1_clkctrl: l3main1-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x74>; +- #clock-cells = <2>; +- }; +- +- }; +- +- ipu2_cm: ipu2-cm@900 { +- compatible = "ti,omap4-cm"; +- reg = <0x900 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x900 0x100>; +- +- ipu2_clkctrl: ipu2-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- +- }; +- +- dma_cm: dma-cm@a00 { +- compatible = "ti,omap4-cm"; +- reg = <0xa00 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xa00 0x100>; +- +- dma_clkctrl: dma-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- emif_cm: emif-cm@b00 { +- compatible = "ti,omap4-cm"; +- reg = <0xb00 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xb00 0x100>; +- +- emif_clkctrl: emif-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- atl_cm: atl-cm@c00 { +- compatible = "ti,omap4-cm"; +- reg = <0xc00 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xc00 0x100>; +- +- atl_clkctrl: atl-clkctrl@0 { +- compatible = "ti,clkctrl"; +- reg = <0x0 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- l4cfg_cm: l4cfg-cm@d00 { +- compatible = "ti,omap4-cm"; +- reg = <0xd00 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xd00 0x100>; +- +- l4cfg_clkctrl: l4cfg-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x84>; +- #clock-cells = <2>; +- }; +- }; +- +- l3instr_cm: l3instr-cm@e00 { +- compatible = "ti,omap4-cm"; +- reg = <0xe00 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xe00 0x100>; +- +- l3instr_clkctrl: l3instr-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0xc>; +- #clock-cells = <2>; +- }; +- }; +- +- iva_cm: iva-cm@f00 { +- compatible = "ti,omap4-cm"; +- reg = <0xf00 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xf00 0x100>; +- +- iva_clkctrl: iva-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0xc>; +- #clock-cells = <2>; +- }; +- }; +- +- cam_cm: cam-cm@1000 { +- compatible = "ti,omap4-cm"; +- reg = <0x1000 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1000 0x100>; +- +- cam_clkctrl: cam-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x2c>; +- #clock-cells = <2>; +- }; +- }; +- +- dss_cm: dss-cm@1100 { +- compatible = "ti,omap4-cm"; +- reg = <0x1100 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1100 0x100>; +- +- dss_clkctrl: dss-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x14>; +- #clock-cells = <2>; +- }; +- }; +- +- gpu_cm: gpu-cm@1200 { +- compatible = "ti,omap4-cm"; +- reg = <0x1200 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1200 0x100>; +- +- gpu_clkctrl: gpu-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- l3init_cm: l3init-cm@1300 { +- compatible = "ti,omap4-cm"; +- reg = <0x1300 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1300 0x100>; +- +- l3init_clkctrl: l3init-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x6c>, <0xe0 0x14>; +- #clock-cells = <2>; +- }; +- +- pcie_clkctrl: pcie-clkctrl@b0 { +- compatible = "ti,clkctrl"; +- reg = <0xb0 0xc>; +- #clock-cells = <2>; +- }; +- +- gmac_clkctrl: gmac-clkctrl@d0 { +- compatible = "ti,clkctrl"; +- reg = <0xd0 0x4>; +- #clock-cells = <2>; +- }; +- +- }; +- +- l4per_cm: l4per-cm@1700 { +- compatible = "ti,omap4-cm"; +- reg = <0x1700 0x300>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1700 0x300>; +- +- l4per_clkctrl: l4per-clkctrl@28 { +- compatible = "ti,clkctrl"; +- reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>; +- #clock-cells = <2>; +- +- assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; +- assigned-clock-parents = <&abe_24m_fclk>; +- }; +- +- l4sec_clkctrl: l4sec-clkctrl@1a0 { +- compatible = "ti,clkctrl"; +- reg = <0x1a0 0x2c>; +- #clock-cells = <2>; +- }; +- +- l4per2_clkctrl: l4per2-clkctrl@c { +- compatible = "ti,clkctrl"; +- reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>; +- #clock-cells = <2>; +- }; +- +- l4per3_clkctrl: l4per3-clkctrl@14 { +- compatible = "ti,clkctrl"; +- reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +-}; +- +-&prm { +- wkupaon_cm: wkupaon-cm@1800 { +- compatible = "ti,omap4-cm"; +- reg = <0x1800 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1800 0x100>; +- +- wkupaon_clkctrl: wkupaon-clkctrl@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x6c>; +- #clock-cells = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/e60k02.dtsi b/scripts/dtc/include-prefixes/arm/e60k02.dtsi +deleted file mode 100644 +index cfb239d5186a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/e60k02.dtsi ++++ /dev/null +@@ -1,310 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2019 Andreas Kemnade +- * based on works +- * Copyright 2016 Freescale Semiconductor, Inc. +- * and +- * Copyright (C) 2014 Ricoh Electronic Devices Co., Ltd +- * +- * Netronix E60K02 board common. +- * This board is equipped with different SoCs and +- * found in ebook-readers like the Kobo Clara HD (with i.MX6SLL) and +- * the Tolino Shine 3 (with i.MX6SL) +- */ +-#include +- +-/ { +- +- chosen { +- stdout-path = &uart1; +- }; +- +- gpio_keys: gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "Power"; +- gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- cover { +- label = "Cover"; +- gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; +- linux,code = ; +- linux,input-type = ; +- wakeup-source; +- }; +- }; +- +- leds: leds { +- compatible = "gpio-leds"; +- +- on { +- label = "e60k02:white:on"; +- gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "timer"; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +- +- reg_wifi: regulator-wifi { +- compatible = "regulator-fixed"; +- regulator-name = "SD3_SPWR"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- post-power-on-delay-ms = <20>; +- reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; +- }; +-}; +- +- +-&i2c1 { +- clock-frequency = <100000>; +- status = "okay"; +- +- lm3630a: backlight@36 { +- reg = <0x36>; +- compatible = "ti,lm3630a"; +- enable-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- led@0 { +- reg = <0>; +- led-sources = <0>; +- label = "backlight_warm"; +- default-brightness = <0>; +- max-brightness = <255>; +- }; +- +- led@1 { +- reg = <1>; +- led-sources = <1>; +- label = "backlight_cold"; +- default-brightness = <0>; +- max-brightness = <255>; +- }; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- status = "okay"; +- +- /* TODO: CYTTSP5 touch controller at 0x24 */ +- +- /* TODO: TPS65185 PMIC for E Ink at 0x68 */ +- +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- status = "okay"; +- +- ricoh619: pmic@32 { +- compatible = "ricoh,rc5t619"; +- reg = <0x32>; +- interrupt-parent = <&gpio5>; +- interrupts = <11 IRQ_TYPE_EDGE_FALLING>; +- system-power-controller; +- +- regulators { +- dcdc1_reg: DCDC1 { +- regulator-name = "DCDC1"; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-max-microvolt = <900000>; +- regulator-suspend-min-microvolt = <900000>; +- }; +- }; +- +- /* Core3_3V3 */ +- dcdc2_reg: DCDC2 { +- regulator-name = "DCDC2"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-max-microvolt = <3300000>; +- regulator-suspend-min-microvolt = <3300000>; +- }; +- }; +- +- dcdc3_reg: DCDC3 { +- regulator-name = "DCDC3"; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-max-microvolt = <1140000>; +- regulator-suspend-min-microvolt = <1140000>; +- }; +- }; +- +- /* Core4_1V2 */ +- dcdc4_reg: DCDC4 { +- regulator-name = "DCDC4"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-max-microvolt = <1140000>; +- regulator-suspend-min-microvolt = <1140000>; +- }; +- }; +- +- /* Core4_1V8 */ +- dcdc5_reg: DCDC5 { +- regulator-name = "DCDC5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-max-microvolt = <1700000>; +- regulator-suspend-min-microvolt = <1700000>; +- }; +- }; +- +- /* IR_3V3 */ +- ldo1_reg: LDO1 { +- regulator-name = "LDO1"; +- regulator-boot-on; +- }; +- +- /* Core1_3V3 */ +- ldo2_reg: LDO2 { +- regulator-name = "LDO2"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-max-microvolt = <3000000>; +- regulator-suspend-min-microvolt = <3000000>; +- }; +- }; +- +- /* Core5_1V2 */ +- ldo3_reg: LDO3 { +- regulator-name = "LDO3"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "LDO4"; +- regulator-boot-on; +- }; +- +- /* SPD_3V3 */ +- ldo5_reg: LDO5 { +- regulator-name = "LDO5"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* DDR_0V6 */ +- ldo6_reg: LDO6 { +- regulator-name = "LDO6"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* VDD_PWM */ +- ldo7_reg: LDO7 { +- regulator-name = "LDO7"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* ldo_1v8 */ +- ldo8_reg: LDO8 { +- regulator-name = "LDO8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "LDO9"; +- regulator-boot-on; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "LDO10"; +- regulator-boot-on; +- }; +- +- ldortc1_reg: LDORTC1 { +- regulator-name = "LDORTC1"; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&snvs_rtc { +- /* we are using the rtc in the pmic, not disabled in imx6sll.dtsi */ +- status = "disabled"; +-}; +- +-&uart1 { +- /* J4, through-hole */ +- status = "okay"; +-}; +- +-&uart4 { +- /* TP198, next to J4, SMD pads */ +- status = "okay"; +-}; +- +-&usdhc2 { +- non-removable; +- status = "okay"; +-}; +- +-&usdhc3 { +- vmmc-supply = <®_wifi>; +- mmc-pwrseq = <&wifi_pwrseq>; +- cap-power-off-card; +- non-removable; +- status = "okay"; +-}; +- +-&usbotg1 { +- pinctrl-names = "default"; +- disable-over-current; +- srp-disable; +- hnp-disable; +- adp-disable; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ecx-2000.dts b/scripts/dtc/include-prefixes/arm/ecx-2000.dts +deleted file mode 100644 +index f6eb71553b95..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ecx-2000.dts ++++ /dev/null +@@ -1,101 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright 2011-2012 Calxeda, Inc. +- */ +- +-/dts-v1/; +- +-/* First 4KB has pen for secondary cores. */ +-/memreserve/ 0x00000000 0x0001000; +- +-/ { +- model = "Calxeda ECX-2000"; +- compatible = "calxeda,ecx-2000"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- reg = <0>; +- clocks = <&a9pll>; +- clock-names = "cpu"; +- }; +- +- cpu@1 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- reg = <1>; +- clocks = <&a9pll>; +- clock-names = "cpu"; +- }; +- +- cpu@2 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- reg = <2>; +- clocks = <&a9pll>; +- clock-names = "cpu"; +- }; +- +- cpu@3 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- reg = <3>; +- clocks = <&a9pll>; +- clock-names = "cpu"; +- }; +- }; +- +- memory@0 { +- name = "memory"; +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000 0xff800000>; +- }; +- +- memory@200000000 { +- name = "memory"; +- device_type = "memory"; +- reg = <0x00000002 0x00000000 0x00000003 0x00000000>; +- }; +- +- soc { +- ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>; +- +- timer { +- compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>, +- <1 14 0xf08>, +- <1 11 0xf08>, +- <1 10 0xf08>; +- }; +- +- memory-controller@fff00000 { +- compatible = "calxeda,ecx-2000-ddr-ctrl"; +- reg = <0xfff00000 0x1000>; +- interrupts = <0 91 4>; +- }; +- +- intc: interrupt-controller@fff11000 { +- compatible = "arm,cortex-a15-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- interrupts = <1 9 0xf04>; +- reg = <0xfff11000 0x1000>, +- <0xfff12000 0x2000>, +- <0xfff14000 0x2000>, +- <0xfff16000 0x2000>; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>; +- }; +- }; +-}; +- +-/include/ "ecx-common.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/ecx-common.dtsi b/scripts/dtc/include-prefixes/arm/ecx-common.dtsi +deleted file mode 100644 +index 57a028a69373..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ecx-common.dtsi ++++ /dev/null +@@ -1,231 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright 2011-2012 Calxeda, Inc. +- */ +- +-/ { +- chosen { +- bootargs = "console=ttyAMA0"; +- }; +- +- psci { +- compatible = "arm,psci"; +- method = "smc"; +- cpu_suspend = <0x84000002>; +- cpu_off = <0x84000004>; +- cpu_on = <0x84000006>; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&intc>; +- +- sata@ffe08000 { +- compatible = "calxeda,hb-ahci"; +- reg = <0xffe08000 0x10000>; +- interrupts = <0 83 4>; +- dma-coherent; +- calxeda,port-phys = < &combophy5 0>, <&combophy0 0>, +- <&combophy0 1>, <&combophy0 2>, +- <&combophy0 3>; +- calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>, +- <&gpioh 7 1>; +- calxeda,led-order = <4 0 1 2 3>; +- }; +- +- sdhci@ffe0e000 { +- compatible = "calxeda,hb-sdhci"; +- reg = <0xffe0e000 0x1000>; +- interrupts = <0 90 4>; +- clocks = <&eclk>; +- status = "disabled"; +- }; +- +- ipc@fff20000 { +- compatible = "arm,pl320", "arm,primecell"; +- reg = <0xfff20000 0x1000>; +- interrupts = <0 7 4>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- gpioe: gpio@fff30000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0xfff30000 0x1000>; +- interrupts = <0 14 4>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- gpiof: gpio@fff31000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0xfff31000 0x1000>; +- interrupts = <0 15 4>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- gpiog: gpio@fff32000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0xfff32000 0x1000>; +- interrupts = <0 16 4>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- gpioh: gpio@fff33000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0xfff33000 0x1000>; +- interrupts = <0 17 4>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- timer@fff34000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0xfff34000 0x1000>; +- interrupts = <0 18 4>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- rtc@fff35000 { +- compatible = "arm,pl031", "arm,primecell"; +- reg = <0xfff35000 0x1000>; +- interrupts = <0 19 4>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- serial@fff36000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xfff36000 0x1000>; +- interrupts = <0 20 4>; +- clocks = <&pclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- smic@fff3a000 { +- compatible = "ipmi-smic"; +- device_type = "ipmi"; +- reg = <0xfff3a000 0x1000>; +- interrupts = <0 24 4>; +- reg-size = <4>; +- reg-spacing = <4>; +- }; +- +- sregs@fff3c000 { +- compatible = "calxeda,hb-sregs"; +- reg = <0xfff3c000 0x1000>; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- osc: oscillator { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <33333000>; +- }; +- +- ddrpll: ddrpll { +- #clock-cells = <0>; +- compatible = "calxeda,hb-pll-clock"; +- clocks = <&osc>; +- reg = <0x108>; +- }; +- +- a9pll: a9pll { +- #clock-cells = <0>; +- compatible = "calxeda,hb-pll-clock"; +- clocks = <&osc>; +- reg = <0x100>; +- }; +- +- a9periphclk: a9periphclk { +- #clock-cells = <0>; +- compatible = "calxeda,hb-a9periph-clock"; +- clocks = <&a9pll>; +- reg = <0x104>; +- }; +- +- a9bclk: a9bclk { +- #clock-cells = <0>; +- compatible = "calxeda,hb-a9bus-clock"; +- clocks = <&a9pll>; +- reg = <0x104>; +- }; +- +- emmcpll: emmcpll { +- #clock-cells = <0>; +- compatible = "calxeda,hb-pll-clock"; +- clocks = <&osc>; +- reg = <0x10C>; +- }; +- +- eclk: eclk { +- #clock-cells = <0>; +- compatible = "calxeda,hb-emmc-clock"; +- clocks = <&emmcpll>; +- reg = <0x114>; +- }; +- +- pclk: pclk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <150000000>; +- }; +- }; +- }; +- +- dma@fff3d000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0xfff3d000 0x1000>; +- interrupts = <0 92 4>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- ethernet@fff50000 { +- compatible = "calxeda,hb-xgmac"; +- reg = <0xfff50000 0x1000>; +- interrupts = <0 77 4>, <0 78 4>, <0 79 4>; +- dma-coherent; +- }; +- +- ethernet@fff51000 { +- compatible = "calxeda,hb-xgmac"; +- reg = <0xfff51000 0x1000>; +- interrupts = <0 80 4>, <0 81 4>, <0 82 4>; +- dma-coherent; +- }; +- +- combophy0: combo-phy@fff58000 { +- compatible = "calxeda,hb-combophy"; +- #phy-cells = <1>; +- reg = <0xfff58000 0x1000>; +- phydev = <5>; +- }; +- +- combophy5: combo-phy@fff5d000 { +- compatible = "calxeda,hb-combophy"; +- #phy-cells = <1>; +- reg = <0xfff5d000 0x1000>; +- phydev = <31>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/elpida_ecb240abacn.dtsi b/scripts/dtc/include-prefixes/arm/elpida_ecb240abacn.dtsi +deleted file mode 100644 +index d87ee4794f83..000000000000 +--- a/scripts/dtc/include-prefixes/arm/elpida_ecb240abacn.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Common devices used in different OMAP boards +- */ +- +-/ { +- elpida_ECB240ABACN: lpddr2 { +- compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; +- density = <2048>; +- io-width = <32>; +- +- tRPab-min-tck = <3>; +- tRCD-min-tck = <3>; +- tWR-min-tck = <3>; +- tRASmin-min-tck = <3>; +- tRRD-min-tck = <2>; +- tWTR-min-tck = <2>; +- tXP-min-tck = <2>; +- tRTP-min-tck = <2>; +- tCKE-min-tck = <3>; +- tCKESR-min-tck = <3>; +- tFAW-min-tck = <8>; +- +- timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { +- compatible = "jedec,lpddr2-timings"; +- min-freq = <10000000>; +- max-freq = <400000000>; +- tRPab = <21000>; +- tRCD = <18000>; +- tWR = <15000>; +- tRAS-min = <42000>; +- tRRD = <10000>; +- tWTR = <7500>; +- tXP = <7500>; +- tRTP = <7500>; +- tCKESR = <15000>; +- tDQSCK-max = <5500>; +- tFAW = <50000>; +- tZQCS = <90000>; +- tZQCL = <360000>; +- tZQinit = <1000000>; +- tRAS-max-ns = <70000>; +- tDQSCK-max-derated = <6000>; +- }; +- +- timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { +- compatible = "jedec,lpddr2-timings"; +- min-freq = <10000000>; +- max-freq = <200000000>; +- tRPab = <21000>; +- tRCD = <18000>; +- tWR = <15000>; +- tRAS-min = <42000>; +- tRRD = <10000>; +- tWTR = <10000>; +- tXP = <7500>; +- tRTP = <7500>; +- tCKESR = <15000>; +- tDQSCK-max = <5500>; +- tFAW = <50000>; +- tZQCS = <90000>; +- tZQCL = <360000>; +- tZQinit = <1000000>; +- tRAS-max-ns = <70000>; +- tDQSCK-max-derated = <6000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/emev2-kzm9d.dts b/scripts/dtc/include-prefixes/arm/emev2-kzm9d.dts +deleted file mode 100644 +index 0a27f034dd6b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/emev2-kzm9d.dts ++++ /dev/null +@@ -1,115 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the KZM9D board +- * +- * Copyright (C) 2013 Renesas Solutions Corp. +- */ +-/dts-v1/; +- +-#include "emev2.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "EMEV2 KZM9D Board"; +- compatible = "renesas,kzm9d", "renesas,emev2"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x8000000>; +- }; +- +- aliases { +- serial1 = &uart1; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial1:115200n8"; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- one { +- debounce-interval = <50>; +- wakeup-source; +- label = "DSW2-1"; +- linux,code = ; +- gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; +- }; +- two { +- debounce-interval = <50>; +- wakeup-source; +- label = "DSW2-2"; +- linux,code = ; +- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; +- }; +- three { +- debounce-interval = <50>; +- wakeup-source; +- label = "DSW2-3"; +- linux,code = ; +- gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; +- }; +- four { +- debounce-interval = <50>; +- wakeup-source; +- label = "DSW2-4"; +- linux,code = ; +- gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ethernet@20000000 { +- compatible = "smsc,lan9220", "smsc,lan9115"; +- reg = <0x20000000 0x10000>; +- phy-mode = "mii"; +- interrupt-parent = <&gpio0>; +- interrupts = <1 IRQ_TYPE_EDGE_RISING>; +- reg-io-width = <4>; +- smsc,irq-active-high; +- smsc,irq-push-pull; +- vddvario-supply = <®_1p8v>; +- vdd33a-supply = <®_3p3v>; +- }; +-}; +- +-&iic0 { +- status = "okay"; +-}; +- +-&iic1 { +- status = "okay"; +-}; +- +-&pfc { +- uart1_pins: uart1 { +- groups = "uart1_ctrl", "uart1_data"; +- function = "uart1"; +- }; +-}; +- +-&uart1 { +- pinctrl-0 = <&uart1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/emev2.dtsi b/scripts/dtc/include-prefixes/arm/emev2.dtsi +deleted file mode 100644 +index ecfaa0b7523e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/emev2.dtsi ++++ /dev/null +@@ -1,289 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Emma Mobile EV2 SoC +- * +- * Copyright (C) 2012 Renesas Solutions Corp. +- */ +- +-#include +-#include +- +-/ { +- compatible = "renesas,emev2"; +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- gpio2 = &gpio2; +- gpio3 = &gpio3; +- gpio4 = &gpio4; +- i2c0 = &iic0; +- i2c1 = &iic1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- clock-frequency = <533000000>; +- }; +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <1>; +- clock-frequency = <533000000>; +- }; +- }; +- +- gic: interrupt-controller@e0020000 { +- compatible = "arm,pl390"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0xe0028000 0x1000>, +- <0xe0020000 0x0100>; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- clocks@e0110000 { +- compatible = "renesas,emev2-smu"; +- reg = <0xe0110000 0x10000>; +- #address-cells = <2>; +- #size-cells = <0>; +- +- c32ki: c32ki { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- iic0_sclkdiv: iic0_sclkdiv@624,0 { +- compatible = "renesas,emev2-smu-clkdiv"; +- reg = <0x624 0>; +- clocks = <&pll3_fo>; +- #clock-cells = <0>; +- }; +- iic0_sclk: iic0_sclk@48c,1 { +- compatible = "renesas,emev2-smu-gclk"; +- reg = <0x48c 1>; +- clocks = <&iic0_sclkdiv>; +- #clock-cells = <0>; +- }; +- iic1_sclkdiv: iic1_sclkdiv@624,16 { +- compatible = "renesas,emev2-smu-clkdiv"; +- reg = <0x624 16>; +- clocks = <&pll3_fo>; +- #clock-cells = <0>; +- }; +- iic1_sclk: iic1_sclk@490,1 { +- compatible = "renesas,emev2-smu-gclk"; +- reg = <0x490 1>; +- clocks = <&iic1_sclkdiv>; +- #clock-cells = <0>; +- }; +- pll3_fo: pll3_fo { +- compatible = "fixed-factor-clock"; +- clocks = <&c32ki>; +- clock-div = <1>; +- clock-mult = <7000>; +- #clock-cells = <0>; +- }; +- usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 { +- compatible = "renesas,emev2-smu-clkdiv"; +- reg = <0x610 0>; +- clocks = <&pll3_fo>; +- #clock-cells = <0>; +- }; +- usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 { +- compatible = "renesas,emev2-smu-clkdiv"; +- reg = <0x65c 0>; +- clocks = <&pll3_fo>; +- #clock-cells = <0>; +- }; +- usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 { +- compatible = "renesas,emev2-smu-clkdiv"; +- reg = <0x65c 16>; +- clocks = <&pll3_fo>; +- #clock-cells = <0>; +- }; +- usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 { +- compatible = "renesas,emev2-smu-clkdiv"; +- reg = <0x660 0>; +- clocks = <&pll3_fo>; +- #clock-cells = <0>; +- }; +- usia_u0_sclk: usia_u0_sclk@4a0,1 { +- compatible = "renesas,emev2-smu-gclk"; +- reg = <0x4a0 1>; +- clocks = <&usia_u0_sclkdiv>; +- #clock-cells = <0>; +- }; +- usib_u1_sclk: usib_u1_sclk@4b8,1 { +- compatible = "renesas,emev2-smu-gclk"; +- reg = <0x4b8 1>; +- clocks = <&usib_u1_sclkdiv>; +- #clock-cells = <0>; +- }; +- usib_u2_sclk: usib_u2_sclk@4bc,1 { +- compatible = "renesas,emev2-smu-gclk"; +- reg = <0x4bc 1>; +- clocks = <&usib_u2_sclkdiv>; +- #clock-cells = <0>; +- }; +- usib_u3_sclk: usib_u3_sclk@4c0,1 { +- compatible = "renesas,emev2-smu-gclk"; +- reg = <0x4c0 1>; +- clocks = <&usib_u3_sclkdiv>; +- #clock-cells = <0>; +- }; +- sti_sclk: sti_sclk@528,1 { +- compatible = "renesas,emev2-smu-gclk"; +- reg = <0x528 1>; +- clocks = <&c32ki>; +- #clock-cells = <0>; +- }; +- }; +- +- timer@e0180000 { +- compatible = "renesas,em-sti"; +- reg = <0xe0180000 0x54>; +- interrupts = ; +- clocks = <&sti_sclk>; +- clock-names = "sclk"; +- }; +- +- uart0: serial@e1020000 { +- compatible = "renesas,em-uart"; +- reg = <0xe1020000 0x38>; +- interrupts = ; +- clocks = <&usia_u0_sclk>; +- clock-names = "sclk"; +- }; +- +- uart1: serial@e1030000 { +- compatible = "renesas,em-uart"; +- reg = <0xe1030000 0x38>; +- interrupts = ; +- clocks = <&usib_u1_sclk>; +- clock-names = "sclk"; +- }; +- +- uart2: serial@e1040000 { +- compatible = "renesas,em-uart"; +- reg = <0xe1040000 0x38>; +- interrupts = ; +- clocks = <&usib_u2_sclk>; +- clock-names = "sclk"; +- }; +- +- uart3: serial@e1050000 { +- compatible = "renesas,em-uart"; +- reg = <0xe1050000 0x38>; +- interrupts = ; +- clocks = <&usib_u3_sclk>; +- clock-names = "sclk"; +- }; +- +- pfc: pinctrl@e0140200 { +- compatible = "renesas,pfc-emev2"; +- reg = <0xe0140200 0x100>; +- }; +- +- gpio0: gpio@e0050000 { +- compatible = "renesas,em-gio"; +- reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; +- interrupts = , +- ; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 32>; +- #gpio-cells = <2>; +- ngpios = <32>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio@e0050080 { +- compatible = "renesas,em-gio"; +- reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>; +- interrupts = , +- ; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 32>; +- #gpio-cells = <2>; +- ngpios = <32>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@e0050100 { +- compatible = "renesas,em-gio"; +- reg = <0xe0050100 0x2c>, <0xe0050140 0x20>; +- interrupts = , +- ; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 32>; +- #gpio-cells = <2>; +- ngpios = <32>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio@e0050180 { +- compatible = "renesas,em-gio"; +- reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>; +- interrupts = , +- ; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 32>; +- #gpio-cells = <2>; +- ngpios = <32>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio4: gpio@e0050200 { +- compatible = "renesas,em-gio"; +- reg = <0xe0050200 0x2c>, <0xe0050240 0x20>; +- interrupts = , +- ; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 31>; +- #gpio-cells = <2>; +- ngpios = <31>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- iic0: i2c@e0070000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-emev2"; +- reg = <0xe0070000 0x28>; +- interrupts = ; +- clocks = <&iic0_sclk>; +- clock-names = "sclk"; +- status = "disabled"; +- }; +- +- iic1: i2c@e10a0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-emev2"; +- reg = <0xe10a0000 0x28>; +- interrupts = ; +- clocks = <&iic1_sclk>; +- clock-names = "sclk"; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ep7209.dtsi b/scripts/dtc/include-prefixes/arm/ep7209.dtsi +deleted file mode 100644 +index 57bdad2c1994..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ep7209.dtsi ++++ /dev/null +@@ -1,201 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +- +-/dts-v1/; +- +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Cirrus Logic EP7209"; +- compatible = "cirrus,ep7209"; +- +- chosen { }; +- +- aliases { +- gpio0 = &porta; +- gpio1 = &portb; +- gpio3 = &portd; +- gpio4 = &porte; +- serial0 = &uart1; +- serial1 = &uart2; +- spi0 = &spi; +- timer0 = &timer1; +- timer1 = &timer2; +- }; +- +- cpus { +- #address-cells = <0>; +- #size-cells = <0>; +- +- cpu { +- device_type = "cpu"; +- compatible = "arm,arm720t"; +- }; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&intc>; +- ranges; +- +- clks: clks@80000000 { +- #clock-cells = <1>; +- compatible = "cirrus,ep7209-clk"; +- reg = <0x80000000 0xc000>; +- startup-frequency = <73728000>; +- }; +- +- intc: intc@80000000 { +- compatible = "cirrus,ep7209-intc"; +- reg = <0x80000000 0x4000>; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- porta: gpio@80000000 { +- compatible = "cirrus,ep7209-gpio"; +- reg = <0x80000000 0x1 0x80000040 0x1>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- portb: gpio@80000001 { +- compatible = "cirrus,ep7209-gpio"; +- reg = <0x80000001 0x1 0x80000041 0x1>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- portd: gpio@80000003 { +- compatible = "cirrus,ep7209-gpio"; +- reg = <0x80000003 0x1 0x80000043 0x1>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- porte: gpio@80000083 { +- compatible = "cirrus,ep7209-gpio"; +- reg = <0x80000083 0x1 0x800000c3 0x1>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- syscon1: syscon@80000100 { +- compatible = "cirrus,ep7209-syscon1", "syscon"; +- reg = <0x80000100 0x80>; +- }; +- +- bus: bus@80000180 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "cirrus,ep7209-bus", "simple-bus"; +- clocks = <&clks CLPS711X_CLK_BUS>; +- reg = <0x80000180 0x80>; +- ranges = < +- 0 0 0x00000000 0x10000000 +- 1 0 0x10000000 0x10000000 +- 2 0 0x20000000 0x10000000 +- 3 0 0x30000000 0x10000000 +- 4 0 0x40000000 0x10000000 +- 5 0 0x50000000 0x10000000 +- 6 0 0x60000000 0x0000c000 +- 7 0 0x70000000 0x00000080 +- >; +- }; +- +- fb: fb@800002c0 { +- compatible = "cirrus,ep7209-fb"; +- reg = <0x800002c0 0xd44>, <0x60000000 0xc000>; +- clocks = <&clks CLPS711X_CLK_BUS>; +- syscon = <&syscon1>; +- status = "disabled"; +- }; +- +- timer1: timer@80000300 { +- compatible = "cirrus,ep7209-timer"; +- reg = <0x80000300 0x4>; +- clocks = <&clks CLPS711X_CLK_TIMER1>; +- interrupts = <8>; +- }; +- +- timer2: timer@80000340 { +- compatible = "cirrus,ep7209-timer"; +- reg = <0x80000340 0x4>; +- clocks = <&clks CLPS711X_CLK_TIMER2>; +- interrupts = <9>; +- }; +- +- pwm: pwm@80000400 { +- compatible = "cirrus,ep7209-pwm"; +- reg = <0x80000400 0x4>; +- clocks = <&clks CLPS711X_CLK_PWM>; +- #pwm-cells = <1>; +- }; +- +- uart1: serial@80000480 { +- compatible = "cirrus,ep7209-uart"; +- reg = <0x80000480 0x80>; +- interrupts = <12 13>; +- clocks = <&clks CLPS711X_CLK_UART>; +- syscon = <&syscon1>; +- }; +- +- spi: spi@80000500 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "cirrus,ep7209-spi"; +- reg = <0x80000500 0x4>; +- interrupts = <15>; +- clocks = <&clks CLPS711X_CLK_SPI>; +- syscon = <&syscon3>; +- status = "disabled"; +- }; +- +- syscon2: syscon@80001100 { +- compatible = "cirrus,ep7209-syscon2", "syscon"; +- reg = <0x80001100 0x80>; +- }; +- +- uart2: serial@80001480 { +- compatible = "cirrus,ep7209-uart"; +- reg = <0x80001480 0x80>; +- interrupts = <28 29>; +- clocks = <&clks CLPS711X_CLK_UART>; +- syscon = <&syscon2>; +- }; +- +- dai: dai@80002000 { +- #sound-dai-cells = <0>; +- compatible = "cirrus,ep7209-dai"; +- reg = <0x80002000 0x604>; +- clocks = <&clks CLPS711X_CLK_PLL>; +- clock-names = "pll"; +- interrupts = <32>; +- syscon = <&syscon3>; +- status = "disabled"; +- }; +- +- syscon3: syscon@80002200 { +- compatible = "cirrus,ep7209-syscon3", "syscon"; +- reg = <0x80002200 0x40>; +- }; +- }; +- +- keypad: keypad { +- compatible = "cirrus,ep7209-keypad"; +- interrupt-parent = <&intc>; +- interrupts = <16>; +- syscon = <&syscon1>; +- status = "disabled"; +- }; +- +- mctrl: mctrl { +- compatible = "cirrus,ep7209-mctrl-gpio"; +- gpio,syscon-dev = <&syscon1 0 0>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ep7211-edb7211.dts b/scripts/dtc/include-prefixes/arm/ep7211-edb7211.dts +deleted file mode 100644 +index 7fb532f227af..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ep7211-edb7211.dts ++++ /dev/null +@@ -1,97 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +- +-#include "ep7211.dtsi" +-#include +- +-/ { +- model = "Cirrus Logic EP7211 Development Board"; +- compatible = "cirrus,edb7211", "cirrus,ep7211", "cirrus,ep7209"; +- +- memory@c0000000 { +- device_type = "memory"; +- reg = <0xc0000000 0x02000000>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0>; +- brightness-levels = < +- 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 +- 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf +- >; +- default-brightness-level = <0x0>; +- power-supply = <&blen>; +- }; +- +- display: display { +- model = "320x240x4"; +- bits-per-pixel = <4>; +- ac-prescale = <17>; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: 320x240 { +- hactive = <320>; +- hback-porch = <0>; +- hfront-porch = <0>; +- hsync-len = <0>; +- vactive = <240>; +- vback-porch = <0>; +- vfront-porch = <0>; +- vsync-len = <0>; +- clock-frequency = <6500000>; +- }; +- }; +- }; +- +- i2c: i2c { +- compatible = "i2c-gpio"; +- gpios = <&portd 4 GPIO_ACTIVE_HIGH>, +- <&portd 5 GPIO_ACTIVE_HIGH>; +- i2c-gpio,delay-us = <2>; +- i2c-gpio,scl-output-only; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- lcddc: lcddc { +- compatible = "regulator-fixed"; +- regulator-name = "BACKLIGHT ENABLE"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&portd 1 GPIO_ACTIVE_HIGH>; +- }; +- +- blen: blen { +- compatible = "regulator-fixed"; +- regulator-name = "BACKLIGHT ENABLE"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&portd 3 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&bus { +- flash: nor@0 { +- compatible = "cfi-flash"; +- reg = <0 0x00000000 0x02000000>; +- bank-width = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&fb { +- display = <&display>; +- lcd-supply = <&lcddc>; +- status = "okay"; +-}; +- +-&portd { +- lcden { +- gpio-hog; +- gpios = <2 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "LCD ENABLE"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ep7211.dtsi b/scripts/dtc/include-prefixes/arm/ep7211.dtsi +deleted file mode 100644 +index 32a4e1237145..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ep7211.dtsi ++++ /dev/null +@@ -1,8 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +- +-#include "ep7209.dtsi" +- +-/ { +- model = "Cirrus Logic EP7211"; +- compatible = "cirrus,ep7211", "cirrus,ep7209"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ethernut5.dts b/scripts/dtc/include-prefixes/arm/ethernut5.dts +deleted file mode 100644 +index ad7a0850252a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ethernut5.dts ++++ /dev/null +@@ -1,118 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * ethernut5.dts - Device Tree file for Ethernut 5 board +- * +- * Copyright (C) 2012 egnite GmbH +- */ +-/dts-v1/; +-#include "at91sam9xe.dtsi" +- +-/ { +- model = "Ethernut 5"; +- compatible = "egnite,ethernut5", "atmel,at91sam9260", "atmel,at91sam9"; +- +- chosen { +- bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x08000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <18432000>; +- }; +- }; +- +- ahb { +- apb { +- dbgu: serial@fffff200 { +- status = "okay"; +- }; +- +- tcb0: timer@fffa0000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +- }; +- +- usart0: serial@fffb0000 { +- status = "okay"; +- }; +- +- usart1: serial@fffb4000 { +- status = "okay"; +- }; +- +- macb0: ethernet@fffc4000 { +- phy-mode = "rmii"; +- status = "okay"; +- }; +- +- usb1: gadget@fffa4000 { +- atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- }; +- +- ebi: ebi@10000000 { +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- pinctrl-0 = <&pinctrl_nand_cs>; +- pinctrl-names = "default"; +- +- nand: nand@3 { +- reg = <0x3 0x0 0x800000>; +- cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "soft"; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- root@0 { +- label = "root"; +- reg = <0x0 0x08000000>; +- }; +- +- data@20000 { +- label = "data"; +- reg = <0x08000000 0x38000000>; +- }; +- }; +- }; +- }; +- }; +- +- usb0: ohci@500000 { +- num-ports = <2>; +- status = "okay"; +- }; +- }; +- +- i2c-gpio-0 { +- status = "okay"; +- +- pcf8563@50 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/evk-pro3.dts b/scripts/dtc/include-prefixes/arm/evk-pro3.dts +deleted file mode 100644 +index 6d519d02d190..000000000000 +--- a/scripts/dtc/include-prefixes/arm/evk-pro3.dts ++++ /dev/null +@@ -1,58 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * evk-pro3.dts - Device Tree file for Telit EVK-PRO3 with Telit GE863-PRO3 +- * +- * Copyright (C) 2012 Telit, +- * 2012 Fabio Porcedda +- */ +- +-/dts-v1/; +- +-#include "ge863-pro3.dtsi" +- +-/ { +- model = "Telit EVK-PRO3 for Telit GE863-PRO3"; +- compatible = "telit,evk-pro3", "atmel,at91sam9260", "atmel,at91sam9"; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- }; +- +- ahb { +- apb { +- macb0: ethernet@fffc4000 { +- phy-mode = "rmii"; +- status = "okay"; +- }; +- +- usart0: serial@fffb0000 { +- status = "okay"; +- }; +- +- usart2: serial@fffb8000 { +- status = "okay"; +- }; +- +- usb1: gadget@fffa4000 { +- atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- watchdog@fffffd40 { +- status = "okay"; +- }; +- }; +- +- usb0: ohci@500000 { +- num-ports = <2>; +- status = "okay"; +- }; +- }; +- +- i2c-gpio-0 { +- status = "okay"; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos-mfc-reserved-memory.dtsi b/scripts/dtc/include-prefixes/arm/exynos-mfc-reserved-memory.dtsi +deleted file mode 100644 +index 597ade3e252f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos-mfc-reserved-memory.dtsi ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos SoC MFC (Video Codec) reserved memory common definition. +- * +- * Copyright (c) 2016 Samsung Electronics Co., Ltd +- */ +- +-/ { +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- mfc_left: region-mfc-left { +- compatible = "shared-dma-pool"; +- no-map; +- size = <0x2400000>; +- alignment = <0x100000>; +- }; +- +- mfc_right: region-mfc-right { +- compatible = "shared-dma-pool"; +- no-map; +- size = <0x800000>; +- alignment = <0x100000>; +- }; +- }; +-}; +- +-&mfc { +- memory-region = <&mfc_left>, <&mfc_right>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos-syscon-restart.dtsi b/scripts/dtc/include-prefixes/arm/exynos-syscon-restart.dtsi +deleted file mode 100644 +index ecf416690a15..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos-syscon-restart.dtsi ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos SoC syscon reboot/poweroff nodes common definition. +- */ +- +-&pmu_system_controller { +- poweroff: syscon-poweroff { +- compatible = "syscon-poweroff"; +- regmap = <&pmu_system_controller>; +- offset = <0x330C>; /* PS_HOLD_CONTROL */ +- mask = <0x5200>; /* reset value */ +- }; +- +- reboot: syscon-reboot { +- compatible = "syscon-reboot"; +- regmap = <&pmu_system_controller>; +- offset = <0x0400>; /* SWRESET */ +- mask = <0x1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos3250-artik5-eval.dts b/scripts/dtc/include-prefixes/arm/exynos3250-artik5-eval.dts +deleted file mode 100644 +index a1e22f630638..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos3250-artik5-eval.dts ++++ /dev/null +@@ -1,65 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos3250 based ARTIK5 evaluation board device tree source +- * +- * Copyright (c) 2016 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Device tree source file for Samsung's ARTIK5 evaluation board +- * which is based on Samsung Exynos3250 SoC. +- */ +- +-/dts-v1/; +-#include "exynos3250-artik5.dtsi" +- +-/ { +- model = "Samsung ARTIK5 evaluation board"; +- compatible = "samsung,artik5-eval", "samsung,artik5", +- "samsung,exynos3250", "samsung,exynos3"; +-}; +- +-&mshc_2 { +- cap-sd-highspeed; +- disable-wp; +- vqmmc-supply = <&ldo3_reg>; +- card-detect-delay = <200>; +- clock-frequency = <100000000>; +- max-frequency = <100000000>; +- samsung,dw-mshc-ciu-div = <1>; +- samsung,dw-mshc-sdr-timing = <0 1>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&serial_2 { +- status = "okay"; +-}; +- +-&spi_0 { +- status = "okay"; +- cs-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>, <0>; +- +- assigned-clocks = <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>, +- <&cmu CLK_DIV_SPI0_PRE>, <&cmu CLK_SCLK_SPI0>; +- assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */ +- <&cmu CLK_MOUT_SPI0>, /* for: CLK_DIV_SPI0 */ +- <&cmu CLK_DIV_SPI0>, /* for: CLK_DIV_SPI0_PRE */ +- <&cmu CLK_DIV_SPI0_PRE>; /* for: CLK_SCLK_SPI0 */ +- +- ethernet@0 { +- compatible = "asix,ax88796c"; +- reg = <0x0>; +- local-mac-address = [00 00 00 00 00 00]; /* Filled in by a boot-loader */ +- interrupt-parent = <&gpx2>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- spi-max-frequency = <40000000>; +- reset-gpios = <&gpe0 2 GPIO_ACTIVE_LOW>; +- +- controller-data { +- samsung,spi-feedback-delay = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos3250-artik5.dtsi b/scripts/dtc/include-prefixes/arm/exynos3250-artik5.dtsi +deleted file mode 100644 +index 829c05b2c405..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos3250-artik5.dtsi ++++ /dev/null +@@ -1,426 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos3250 based ARTIK5 module device tree source +- * +- * Copyright (c) 2016 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Device tree source file for Samsung's ARTIK5 module which is based on +- * Samsung Exynos3250 SoC. +- */ +- +-#include "exynos3250.dtsi" +-#include +-#include +-#include +- +-/ { +- compatible = "samsung,artik5", "samsung,exynos3250", "samsung,exynos3"; +- +- chosen { +- stdout-path = &serial_2; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x1f800000>; +- }; +- +- firmware@205f000 { +- compatible = "samsung,secure-firmware"; +- reg = <0x0205f000 0x1000>; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- cooling-maps { +- map0 { +- /* Corresponds to 500MHz */ +- cooling-device = <&cpu0 5 5>, +- <&cpu1 5 5>; +- }; +- map1 { +- /* Corresponds to 200MHz */ +- cooling-device = <&cpu0 8 8>, +- <&cpu1 8 8>; +- }; +- }; +- }; +- }; +-}; +- +-&adc { +- vdd-supply = <&ldo7_reg>; +- assigned-clocks = <&cmu CLK_SCLK_TSADC>; +- assigned-clock-rates = <6000000>; +-}; +- +-&cmu { +- clocks = <&xusbxti>; +-}; +- +-&cpu0 { +- cpu0-supply = <&buck2_reg>; +-}; +- +-&gpu { +- mali-supply = <&buck3_reg>; +- status = "okay"; +-}; +- +-&i2c_0 { +- #address-cells = <1>; +- #size-cells = <0>; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <100000>; +- status = "okay"; +- +- pmic@66 { +- compatible = "samsung,s2mps14-pmic"; +- interrupt-parent = <&gpx3>; +- interrupts = <5 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&s2mps14_irq>; +- reg = <0x66>; +- +- s2mps14_osc: clocks { +- compatible = "samsung,s2mps14-clk"; +- #clock-cells = <1>; +- clock-output-names = "s2mps14_ap", "unused", +- "s2mps14_bt"; +- }; +- +- regulators { +- ldo1_reg: LDO1 { +- /* VDD_ALIVE15x */ +- regulator-name = "VLDO1_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo2_reg: LDO2 { +- /* VDDQM176 ~ VDDQM185 */ +- regulator-name = "VLDO2_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- /* +- * VDD1_E106 ~ VDD1_E111 +- * DVDD_RTC_AP, DVDD_MMC2_AP +- */ +- regulator-name = "VLDO3_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo4_reg: LDO4 { +- /* AVDD_PLL1120 ~ AVDD_PLL11201 */ +- regulator-name = "VLDO4_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo5_reg: LDO5 { +- /* VDDI_PLL_ISO141 ~ VDDI_PLL_ISO142 */ +- regulator-name = "VLDO5_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo6_reg: LDO6 { +- /* VDD_USB, VDD10_HSIC */ +- regulator-name = "VLDO6_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo7_reg: LDO7 { +- /* +- * VDD18P, AVDD18_TS, AVDD18_HSIC, AVDD_PLL2, +- * AVDD_ADC, AVDD_ABB_0, M4S_VDD18 +- */ +- regulator-name = "VLDO7_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo8_reg: LDO8 { +- /* AVDD33_UOTG */ +- regulator-name = "VLDO8_3.0V"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- +- ldo9_reg: LDO9 { +- /* VDDQ_E86 ~ VDDQ_E105*/ +- regulator-name = "VLDO9_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "VLDO10_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- ldo11_reg: LDO11 { +- /* VDD74 ~ VDD75 */ +- regulator-name = "VLDO11_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; +- }; +- +- ldo12_reg: LDO12 { +- /* VDD72 ~ VDD73 */ +- regulator-name = "VLDO12_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "VLDO13_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "VLDO14_2.7V"; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "VLDO_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "VLDO16_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "VLDO17_3.0V"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- ldo18_reg: LDO18 { +- /* DVDD_MMC2_AP */ +- regulator-name = "VLDO18_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo19_reg: LDO19 { +- regulator-name = "VLDO19_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo20_reg: LDO20 { +- regulator-name = "VLDO20_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo21_reg: LDO21 { +- regulator-name = "VLDO21_1.25V"; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- }; +- +- ldo22_reg: LDO22 { +- regulator-name = "VLDO22_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo23_reg: LDO23 { +- /* Xi2c3_SDA/SCL, Xi2c7_SDA/SCL, WLAN_SDIO */ +- regulator-name = "VLDO23_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo24_reg: LDO24 { +- regulator-name = "VLDO24_3.0V"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- ldo25_reg: LDO25 { +- regulator-name = "VLDO25_3.0V"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- buck1_reg: BUCK1 { +- /* VDD_MIF */ +- regulator-name = "VBUCK1_1.0V"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- buck2_reg: BUCK2 { +- /* VDD_CPU */ +- regulator-name = "VBUCK2_1.2V"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- buck3_reg: BUCK3 { +- /* VDD_G3D */ +- regulator-name = "VBUCK3_1.0V"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "VBUCK4_1.95V"; +- regulator-min-microvolt = <1950000>; +- regulator-max-microvolt = <1950000>; +- regulator-always-on; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "VBUCK5_1.35V"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&mshc_0 { +- non-removable; +- cap-mmc-highspeed; +- card-detect-delay = <200>; +- vmmc-supply = <&ldo12_reg>; +- clock-frequency = <100000000>; +- max-frequency = <100000000>; +- samsung,dw-mshc-ciu-div = <1>; +- samsung,dw-mshc-sdr-timing = <0 1>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; +- bus-width = <8>; +- status = "okay"; +-}; +- +-&mshc_1 { +- cap-sd-highspeed; +- cap-sdio-irq; +- disable-wp; +- non-removable; +- keep-power-in-suspend; +- fifo-depth = <0x40>; +- vqmmc-supply = <&ldo11_reg>; +- /* +- * Voltage negotiation is broken for the SDIO periph so we +- * can't actually set the voltage here. +- * vmmc-supply = <&ldo23_reg>; +- */ +- card-detect-delay = <500>; +- clock-frequency = <100000000>; +- max-frequency = <100000000>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <0 1>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd1_cmd &sd1_clk &sd1_bus1 &sd1_bus4 &wlanen>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&pinctrl_1 { +- bten: bten { +- samsung,pins ="gpx1-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-con-pdn = ; +- samsung,pin-pud-pdn = ; +- }; +- +- wlanen: wlanen { +- samsung,pins = "gpx2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- samsung,pin-val = <1>; +- }; +- +- s2mps14_irq: s2mps14-irq { +- samsung,pins = "gpx3-5"; +- samsung,pin-pud = ; +- }; +- +- bthostwake: bthostwake { +- samsung,pins = "gpx3-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-con-pdn = ; +- samsung,pin-pud-pdn = ; +- }; +- +- btwake: btwake { +- samsung,pins = "gpx3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-con-pdn = ; +- samsung,pin-pud-pdn = ; +- }; +-}; +- +-&rtc { +- clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>; +- clock-names = "rtc", "rtc_src"; +- status = "okay"; +-}; +- +-&serial_0 { +- assigned-clocks = <&cmu CLK_SCLK_UART0>; +- assigned-clock-rates = <100000000>; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm4330-bt"; +- pinctrl-names = "default"; +- pinctrl-0 = <&bten &btwake &bthostwake>; +- max-speed = <3000000>; +- shutdown-gpios = <&gpx1 7 GPIO_ACTIVE_HIGH>; +- device-wakeup-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpx3 6 GPIO_ACTIVE_HIGH>; +- clocks = <&s2mps14_osc S2MPS11_CLK_BT>; +- }; +-}; +- +-&tmu { +- status = "okay"; +-}; +- +-&xusbxti { +- clock-frequency = <24000000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos3250-monk.dts b/scripts/dtc/include-prefixes/arm/exynos3250-monk.dts +deleted file mode 100644 +index 8b41a9d5e2db..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos3250-monk.dts ++++ /dev/null +@@ -1,643 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos3250 based Monk board device tree source +- * +- * Copyright (c) 2014 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Device tree source file for Samsung's Monk board which is based on +- * Samsung Exynos3250 SoC. +- */ +- +-/dts-v1/; +-#include "exynos3250.dtsi" +-#include "exynos4412-ppmu-common.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "Samsung Monk board"; +- compatible = "samsung,monk", "samsung,exynos3250", "samsung,exynos3"; +- +- aliases { +- i2c7 = &i2c_max77836; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x1ff00000>; +- }; +- +- firmware@205f000 { +- compatible = "samsung,secure-firmware"; +- reg = <0x0205F000 0x1000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power-key { +- gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "power key"; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- vemmc_reg: voltage-regulator-0 { +- compatible = "regulator-fixed"; +- regulator-name = "V_EMMC_2.8V-fixed"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- i2c_max77836: i2c-gpio-0 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpd0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpd0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- max77836: pmic@25 { +- compatible = "maxim,max77836"; +- interrupt-parent = <&gpx1>; +- interrupts = <5 IRQ_TYPE_NONE>; +- reg = <0x25>; +- wakeup-source; +- +- muic: max77836-muic { +- compatible = "maxim,max77836-muic"; +- }; +- +- regulators { +- compatible = "maxim,max77836-regulator"; +- safeout_reg: SAFEOUT { +- regulator-name = "SAFEOUT"; +- }; +- +- charger_reg: CHARGER { +- regulator-name = "CHARGER"; +- regulator-min-microamp = <45000>; +- regulator-max-microamp = <475000>; +- regulator-boot-on; +- }; +- +- motor_reg: LDO1 { +- regulator-name = "MOT_2.7V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- LDO2 { +- regulator-name = "UNUSED_LDO2"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- }; +- +- charger { +- compatible = "maxim,max77836-charger"; +- +- maxim,constant-uvolt = <4350000>; +- maxim,fast-charge-uamp = <225000>; +- maxim,eoc-uamp = <7500>; +- maxim,ovp-uvolt = <6500000>; +- }; +- }; +- }; +- +- haptics { +- compatible = "regulator-haptic"; +- haptic-supply = <&motor_reg>; +- min-microvolt = <1100000>; +- max-microvolt = <2700000>; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- cooling-maps { +- map0 { +- /* Correspond to 500MHz at freq_table */ +- cooling-device = <&cpu0 5 5>, +- <&cpu1 5 5>; +- }; +- map1 { +- /* Correspond to 200MHz at freq_table */ +- cooling-device = <&cpu0 8 8>, +- <&cpu1 8 8>; +- }; +- }; +- }; +- }; +-}; +- +-&adc { +- vdd-supply = <&ldo3_reg>; +- status = "okay"; +- assigned-clocks = <&cmu CLK_SCLK_TSADC>; +- assigned-clock-rates = <6000000>; +- +- thermistor-ap { +- compatible = "murata,ncp15wb473"; +- pullup-uv = <1800000>; +- pullup-ohm = <100000>; +- pulldown-ohm = <100000>; +- io-channels = <&adc 0>; +- }; +- +- thermistor-battery { +- compatible = "murata,ncp15wb473"; +- pullup-uv = <1800000>; +- pullup-ohm = <100000>; +- pulldown-ohm = <100000>; +- io-channels = <&adc 1>; +- }; +-}; +- +-&bus_dmc { +- devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; +- vdd-supply = <&buck1_reg>; +- status = "okay"; +-}; +- +-&cmu { +- clocks = <&xusbxti>; +-}; +- +-&cpu0 { +- cpu0-supply = <&buck2_reg>; +-}; +- +-&exynos_usbphy { +- vbus-supply = <&safeout_reg>; +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&buck3_reg>; +- status = "okay"; +-}; +- +-&hsotg { +- vusb_d-supply = <&ldo15_reg>; +- vusb_a-supply = <&ldo12_reg>; +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&i2c_0 { +- #address-cells = <1>; +- #size-cells = <0>; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <100000>; +- status = "okay"; +- +- pmic@66 { +- compatible = "samsung,s2mps14-pmic"; +- interrupt-parent = <&gpx0>; +- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x66>; +- wakeup-source; +- +- s2mps14_osc: clocks { +- compatible = "samsung,s2mps14-clk"; +- #clock-cells = <1>; +- clock-output-names = "s2mps14_ap", "unused", +- "s2mps14_bt"; +- }; +- +- regulators { +- ldo1_reg: LDO1 { +- regulator-name = "VAP_ALIVE_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "VAP_M1_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "VCC_AP_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "VAP_AVDD_PLL1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "VAP_PLL_ISO_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "VAP_MIPI_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "VAP_AVDD_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "VAP_USB_3.0V"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "V_LPDDR_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "UNUSED_LDO10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "V_EMMC_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "V_EMMC_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "VSENSOR_2.85V"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "UNUSED_LDO14"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "TSP_AVDD_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "LCD_VDD_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "UNUSED_LDO17"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo18_reg: LDO18 { +- regulator-name = "UNUSED_LDO18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo19_reg: LDO19 { +- regulator-name = "TSP_VDD_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo20_reg: LDO20 { +- regulator-name = "LCD_VDD_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo21_reg: LDO21 { +- regulator-name = "UNUSED_LDO21"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- ldo22_reg: LDO22 { +- regulator-name = "UNUSED_LDO22"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- ldo23_reg: LDO23 { +- regulator-name = "UNUSED_LDO23"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo24_reg: LDO24 { +- regulator-name = "UNUSED_LDO24"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo25_reg: LDO25 { +- regulator-name = "UNUSED_LDO25"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "VAP_MIF_1.0V"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <900000>; +- regulator-always-on; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "VAP_ARM_1.0V"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1150000>; +- regulator-always-on; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "VAP_INT3D_1.0V"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "VCC_SUB_1.95V"; +- regulator-min-microvolt = <1950000>; +- regulator-max-microvolt = <1950000>; +- regulator-always-on; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "VCC_SUB_1.35V"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c_1 { +- #address-cells = <1>; +- #size-cells = <0>; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <400000>; +- status = "okay"; +- +- fuelgauge@36 { +- compatible = "maxim,max77836-battery"; +- interrupt-parent = <&gpx1>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x36>; +- }; +-}; +- +-&i2s2 { +- status = "okay"; +-}; +- +-&mshc_0 { +- #address-cells = <1>; +- #size-cells = <0>; +- broken-cd; +- non-removable; +- cap-mmc-highspeed; +- desc-num = <4>; +- mmc-hs200-1_8v; +- card-detect-delay = <200>; +- vmmc-supply = <&vemmc_reg>; +- clock-frequency = <100000000>; +- max-frequency = <100000000>; +- samsung,dw-mshc-ciu-div = <1>; +- samsung,dw-mshc-sdr-timing = <0 1>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; +- bus-width = <8>; +- status = "okay"; +-}; +- +-&serial_0 { +- assigned-clocks = <&cmu CLK_SCLK_UART0>; +- assigned-clock-rates = <100000000>; +- status = "okay"; +-}; +- +-&serial_1 { +- status = "okay"; +-}; +- +-&tmu { +- vtmu-supply = <&ldo7_reg>; +- status = "okay"; +-}; +- +-&rtc { +- clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>; +- clock-names = "rtc", "rtc_src"; +- status = "okay"; +-}; +- +-&xusbxti { +- clock-frequency = <24000000>; +-}; +- +-&pinctrl_0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sleep0>; +- +- sleep0: sleep-state { +- PIN_SLP(gpa0-0, INPUT, DOWN); +- PIN_SLP(gpa0-1, INPUT, DOWN); +- PIN_SLP(gpa0-2, INPUT, DOWN); +- PIN_SLP(gpa0-3, INPUT, DOWN); +- PIN_SLP(gpa0-4, INPUT, DOWN); +- PIN_SLP(gpa0-5, INPUT, DOWN); +- PIN_SLP(gpa0-6, INPUT, DOWN); +- PIN_SLP(gpa0-7, INPUT, DOWN); +- +- PIN_SLP(gpa1-0, INPUT, DOWN); +- PIN_SLP(gpa1-1, INPUT, DOWN); +- PIN_SLP(gpa1-2, INPUT, DOWN); +- PIN_SLP(gpa1-3, INPUT, DOWN); +- PIN_SLP(gpa1-4, INPUT, DOWN); +- PIN_SLP(gpa1-5, INPUT, DOWN); +- +- PIN_SLP(gpb-0, PREV, NONE); +- PIN_SLP(gpb-1, PREV, NONE); +- PIN_SLP(gpb-2, PREV, NONE); +- PIN_SLP(gpb-3, PREV, NONE); +- PIN_SLP(gpb-4, INPUT, DOWN); +- PIN_SLP(gpb-5, INPUT, DOWN); +- PIN_SLP(gpb-6, INPUT, DOWN); +- PIN_SLP(gpb-7, INPUT, DOWN); +- +- PIN_SLP(gpc0-0, INPUT, DOWN); +- PIN_SLP(gpc0-1, INPUT, DOWN); +- PIN_SLP(gpc0-2, INPUT, DOWN); +- PIN_SLP(gpc0-3, INPUT, DOWN); +- PIN_SLP(gpc0-4, INPUT, DOWN); +- +- PIN_SLP(gpc1-0, INPUT, DOWN); +- PIN_SLP(gpc1-1, INPUT, DOWN); +- PIN_SLP(gpc1-2, INPUT, DOWN); +- PIN_SLP(gpc1-3, INPUT, DOWN); +- PIN_SLP(gpc1-4, INPUT, DOWN); +- +- PIN_SLP(gpd0-0, INPUT, DOWN); +- PIN_SLP(gpd0-1, INPUT, DOWN); +- PIN_SLP(gpd0-2, INPUT, NONE); +- PIN_SLP(gpd0-3, INPUT, NONE); +- +- PIN_SLP(gpd1-0, INPUT, NONE); +- PIN_SLP(gpd1-1, INPUT, NONE); +- PIN_SLP(gpd1-2, INPUT, NONE); +- PIN_SLP(gpd1-3, INPUT, NONE); +- }; +-}; +- +-&pinctrl_1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&initial1 &sleep1>; +- +- initial1: initial-state { +- PIN_IN(gpk2-0, DOWN, LV1); +- PIN_IN(gpk2-1, DOWN, LV1); +- PIN_IN(gpk2-2, DOWN, LV1); +- PIN_IN(gpk2-3, DOWN, LV1); +- PIN_IN(gpk2-4, DOWN, LV1); +- PIN_IN(gpk2-5, DOWN, LV1); +- PIN_IN(gpk2-6, DOWN, LV1); +- }; +- +- sleep1: sleep-state { +- PIN_SLP(gpe0-0, PREV, NONE); +- PIN_SLP(gpe0-1, PREV, NONE); +- PIN_SLP(gpe0-2, INPUT, DOWN); +- PIN_SLP(gpe0-3, INPUT, DOWN); +- PIN_SLP(gpe0-4, PREV, NONE); +- PIN_SLP(gpe0-5, INPUT, DOWN); +- PIN_SLP(gpe0-6, INPUT, DOWN); +- PIN_SLP(gpe0-7, INPUT, DOWN); +- +- PIN_SLP(gpe1-0, INPUT, DOWN); +- PIN_SLP(gpe1-1, PREV, NONE); +- PIN_SLP(gpe1-2, INPUT, DOWN); +- PIN_SLP(gpe1-3, INPUT, DOWN); +- PIN_SLP(gpe1-4, INPUT, DOWN); +- PIN_SLP(gpe1-5, INPUT, DOWN); +- PIN_SLP(gpe1-6, INPUT, DOWN); +- PIN_SLP(gpe1-7, INPUT, NONE); +- +- PIN_SLP(gpe2-0, INPUT, NONE); +- PIN_SLP(gpe2-1, INPUT, NONE); +- PIN_SLP(gpe2-2, INPUT, NONE); +- +- PIN_SLP(gpk0-0, INPUT, DOWN); +- PIN_SLP(gpk0-1, INPUT, DOWN); +- PIN_SLP(gpk0-2, OUT0, NONE); +- PIN_SLP(gpk0-3, INPUT, DOWN); +- PIN_SLP(gpk0-4, INPUT, DOWN); +- PIN_SLP(gpk0-5, INPUT, DOWN); +- PIN_SLP(gpk0-6, INPUT, DOWN); +- PIN_SLP(gpk0-7, INPUT, DOWN); +- +- PIN_SLP(gpk1-0, PREV, NONE); +- PIN_SLP(gpk1-1, PREV, NONE); +- PIN_SLP(gpk1-2, INPUT, DOWN); +- PIN_SLP(gpk1-3, PREV, NONE); +- PIN_SLP(gpk1-4, PREV, NONE); +- PIN_SLP(gpk1-5, PREV, NONE); +- PIN_SLP(gpk1-6, PREV, NONE); +- +- PIN_SLP(gpk2-0, INPUT, DOWN); +- PIN_SLP(gpk2-1, INPUT, DOWN); +- PIN_SLP(gpk2-2, INPUT, DOWN); +- PIN_SLP(gpk2-3, INPUT, DOWN); +- PIN_SLP(gpk2-4, INPUT, DOWN); +- PIN_SLP(gpk2-5, INPUT, DOWN); +- PIN_SLP(gpk2-6, INPUT, DOWN); +- +- PIN_SLP(gpl0-0, INPUT, DOWN); +- PIN_SLP(gpl0-1, INPUT, DOWN); +- PIN_SLP(gpl0-2, INPUT, DOWN); +- PIN_SLP(gpl0-3, INPUT, DOWN); +- +- PIN_SLP(gpm0-0, INPUT, DOWN); +- PIN_SLP(gpm0-1, INPUT, DOWN); +- PIN_SLP(gpm0-2, INPUT, DOWN); +- PIN_SLP(gpm0-3, INPUT, DOWN); +- PIN_SLP(gpm0-4, INPUT, DOWN); +- PIN_SLP(gpm0-5, INPUT, DOWN); +- PIN_SLP(gpm0-6, INPUT, DOWN); +- PIN_SLP(gpm0-7, INPUT, DOWN); +- +- PIN_SLP(gpm1-0, INPUT, DOWN); +- PIN_SLP(gpm1-1, INPUT, DOWN); +- PIN_SLP(gpm1-2, INPUT, DOWN); +- PIN_SLP(gpm1-3, INPUT, DOWN); +- PIN_SLP(gpm1-4, INPUT, DOWN); +- PIN_SLP(gpm1-5, INPUT, DOWN); +- PIN_SLP(gpm1-6, INPUT, DOWN); +- +- PIN_SLP(gpm2-0, INPUT, DOWN); +- PIN_SLP(gpm2-1, INPUT, DOWN); +- PIN_SLP(gpm2-2, INPUT, DOWN); +- PIN_SLP(gpm2-3, INPUT, DOWN); +- PIN_SLP(gpm2-4, INPUT, DOWN); +- +- PIN_SLP(gpm3-0, INPUT, DOWN); +- PIN_SLP(gpm3-1, INPUT, DOWN); +- PIN_SLP(gpm3-2, INPUT, DOWN); +- PIN_SLP(gpm3-3, INPUT, DOWN); +- PIN_SLP(gpm3-4, INPUT, DOWN); +- PIN_SLP(gpm3-5, INPUT, DOWN); +- PIN_SLP(gpm3-6, INPUT, DOWN); +- PIN_SLP(gpm3-7, INPUT, DOWN); +- +- PIN_SLP(gpm4-0, INPUT, DOWN); +- PIN_SLP(gpm4-1, INPUT, DOWN); +- PIN_SLP(gpm4-2, INPUT, DOWN); +- PIN_SLP(gpm4-3, INPUT, DOWN); +- PIN_SLP(gpm4-4, INPUT, DOWN); +- PIN_SLP(gpm4-5, INPUT, DOWN); +- PIN_SLP(gpm4-6, INPUT, DOWN); +- PIN_SLP(gpm4-7, INPUT, DOWN); +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos3250-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/exynos3250-pinctrl.dtsi +deleted file mode 100644 +index dff3c6e3aa1f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos3250-pinctrl.dtsi ++++ /dev/null +@@ -1,568 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source +- * +- * Copyright (c) 2014 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are listed as device +- * tree nodes are listed in this file. +- */ +- +-#include +- +-#define PIN_IN(_pin, _pull, _drv) \ +- _pin { \ +- samsung,pins = #_pin; \ +- samsung,pin-function = ; \ +- samsung,pin-pud = ; \ +- samsung,pin-drv = ; \ +- } +- +-#define PIN_OUT(_pin, _drv) \ +- _pin { \ +- samsung,pins = #_pin; \ +- samsung,pin-function = ; \ +- samsung,pin-pud = ; \ +- samsung,pin-drv = ; \ +- } +- +-#define PIN_OUT_SET(_pin, _val, _drv) \ +- _pin { \ +- samsung,pins = #_pin; \ +- samsung,pin-function = ; \ +- samsung,pin-pud = ; \ +- samsung,pin-drv = ; \ +- samsung,pin-val = <_val>; \ +- } +- +-#define PIN_CFG(_pin, _sel, _pull, _drv) \ +- _pin { \ +- samsung,pins = #_pin; \ +- samsung,pin-function = <_sel>; \ +- samsung,pin-pud = ; \ +- samsung,pin-drv = ; \ +- } +- +-#define PIN_SLP(_pin, _mode, _pull) \ +- _pin { \ +- samsung,pins = #_pin; \ +- samsung,pin-con-pdn = ; \ +- samsung,pin-pud-pdn = ; \ +- } +- +-&pinctrl_0 { +- gpa0: gpa0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpa1: gpa1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb: gpb { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc0: gpc0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc1: gpc1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd0: gpd0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd1: gpd1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- uart0_data: uart0-data { +- samsung,pins = "gpa0-0", "gpa0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart0_fctl: uart0-fctl { +- samsung,pins = "gpa0-2", "gpa0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart1_data: uart1-data { +- samsung,pins = "gpa0-4", "gpa0-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart1_fctl: uart1-fctl { +- samsung,pins = "gpa0-6", "gpa0-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c2_bus: i2c2-bus { +- samsung,pins = "gpa0-6", "gpa0-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart2_data: uart2-data { +- samsung,pins = "gpa1-0", "gpa1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c3_bus: i2c3-bus { +- samsung,pins = "gpa1-2", "gpa1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi0_bus: spi0-bus { +- samsung,pins = "gpb-0", "gpb-2", "gpb-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c4_bus: i2c4-bus { +- samsung,pins = "gpb-0", "gpb-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi1_bus: spi1-bus { +- samsung,pins = "gpb-4", "gpb-6", "gpb-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c5_bus: i2c5-bus { +- samsung,pins = "gpb-2", "gpb-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2s2_bus: i2s2-bus { +- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", +- "gpc1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pcm2_bus: pcm2-bus { +- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", +- "gpc1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c6_bus: i2c6-bus { +- samsung,pins = "gpc1-3", "gpc1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm0_out: pwm0-out { +- samsung,pins = "gpd0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm1_out: pwm1-out { +- samsung,pins = "gpd0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c7_bus: i2c7-bus { +- samsung,pins = "gpd0-2", "gpd0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm2_out: pwm2-out { +- samsung,pins = "gpd0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm3_out: pwm3-out { +- samsung,pins = "gpd0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c0_bus: i2c0-bus { +- samsung,pins = "gpd1-0", "gpd1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- mipi0_clk: mipi0-clk { +- samsung,pins = "gpd1-0", "gpd1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c1_bus: i2c1-bus { +- samsung,pins = "gpd1-2", "gpd1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_1 { +- gpe0: gpe0 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpe1: gpe1 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpe2: gpe2 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpk0: gpk0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpk1: gpk1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpk2: gpk2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpl0: gpl0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpm0: gpm0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpm1: gpm1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpm2: gpm2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpm3: gpm3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpm4: gpm4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpx0: gpx0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- #interrupt-cells = <2>; +- }; +- +- gpx1: gpx1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- #interrupt-cells = <2>; +- }; +- +- gpx2: gpx2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpx3: gpx3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- sd0_clk: sd0-clk { +- samsung,pins = "gpk0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_cmd: sd0-cmd { +- samsung,pins = "gpk0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_cd: sd0-cd { +- samsung,pins = "gpk0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_rdqs: sd0-rdqs { +- samsung,pins = "gpk0-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus1: sd0-bus-width1 { +- samsung,pins = "gpk0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus4: sd0-bus-width4 { +- samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus8: sd0-bus-width8 { +- samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_clk: sd1-clk { +- samsung,pins = "gpk1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_cmd: sd1-cmd { +- samsung,pins = "gpk1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_cd: sd1-cd { +- samsung,pins = "gpk1-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus1: sd1-bus-width1 { +- samsung,pins = "gpk1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus4: sd1-bus-width4 { +- samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_clk: sd2-clk { +- samsung,pins = "gpk2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cmd: sd2-cmd { +- samsung,pins = "gpk2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cd: sd2-cd { +- samsung,pins = "gpk2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus1: sd2-bus-width1 { +- samsung,pins = "gpk2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus4: sd2-bus-width4 { +- samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_port_b_io: cam-port-b-io { +- samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", +- "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", +- "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_port_b_clk_active: cam-port-b-clk-active { +- samsung,pins = "gpm2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_port_b_clk_idle: cam-port-b-clk-idle { +- samsung,pins = "gpm2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- fimc_is_i2c0: fimc-is-i2c0 { +- samsung,pins = "gpm4-0", "gpm4-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- fimc_is_i2c1: fimc-is-i2c1 { +- samsung,pins = "gpm4-2", "gpm4-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- fimc_is_uart: fimc-is-uart { +- samsung,pins = "gpm3-5", "gpm3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos3250-rinato.dts b/scripts/dtc/include-prefixes/arm/exynos3250-rinato.dts +deleted file mode 100644 +index f6ba5e426040..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos3250-rinato.dts ++++ /dev/null +@@ -1,918 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos3250 based Rinato board device tree source +- * +- * Copyright (c) 2014 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Device tree source file for Samsung's Rinato board which is based on +- * Samsung Exynos3250 SoC. +- */ +- +-/dts-v1/; +-#include "exynos3250.dtsi" +-#include "exynos4412-ppmu-common.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "Samsung Rinato board"; +- compatible = "samsung,rinato", "samsung,exynos3250", "samsung,exynos3"; +- +- aliases { +- i2c7 = &i2c_max77836; +- }; +- +- chosen { +- stdout-path = &serial_1; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x1ff00000>; +- }; +- +- firmware@205f000 { +- compatible = "samsung,secure-firmware"; +- reg = <0x0205F000 0x1000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power-key { +- gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "power key"; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- wlan_pwrseq: mshc1-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>; +- }; +- +- i2c_max77836: i2c-gpio-0 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpd0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpd0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- max77836: pmic@25 { +- compatible = "maxim,max77836"; +- interrupt-parent = <&gpx1>; +- interrupts = <5 IRQ_TYPE_NONE>; +- reg = <0x25>; +- wakeup-source; +- +- muic: max77836-muic { +- compatible = "maxim,max77836-muic"; +- }; +- +- regulators { +- compatible = "maxim,max77836-regulator"; +- safeout_reg: SAFEOUT { +- regulator-name = "SAFEOUT"; +- }; +- +- charger_reg: CHARGER { +- regulator-name = "CHARGER"; +- regulator-min-microamp = <45000>; +- regulator-max-microamp = <475000>; +- regulator-boot-on; +- }; +- +- motor_reg: LDO1 { +- regulator-name = "MOT_2.7V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- LDO2 { +- regulator-name = "UNUSED_LDO2"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- }; +- +- charger { +- compatible = "maxim,max77836-charger"; +- +- maxim,constant-uvolt = <4350000>; +- maxim,fast-charge-uamp = <225000>; +- maxim,eoc-uamp = <7500>; +- maxim,ovp-uvolt = <6500000>; +- }; +- }; +- }; +- +- haptics { +- compatible = "regulator-haptic"; +- haptic-supply = <&motor_reg>; +- min-microvolt = <1100000>; +- max-microvolt = <2700000>; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- cooling-maps { +- map0 { +- /* Corresponds to 500MHz */ +- cooling-device = <&cpu0 5 5>, +- <&cpu1 5 5>; +- }; +- map1 { +- /* Corresponds to 200MHz */ +- cooling-device = <&cpu0 8 8>, +- <&cpu1 8 8>; +- }; +- }; +- }; +- }; +-}; +- +-&adc { +- vdd-supply = <&ldo3_reg>; +- status = "okay"; +- assigned-clocks = <&cmu CLK_SCLK_TSADC>; +- assigned-clock-rates = <6000000>; +- +- thermistor-ap { +- compatible = "murata,ncp15wb473"; +- pullup-uv = <1800000>; +- pullup-ohm = <100000>; +- pulldown-ohm = <100000>; +- io-channels = <&adc 0>; +- }; +- +- thermistor-battery { +- compatible = "murata,ncp15wb473"; +- pullup-uv = <1800000>; +- pullup-ohm = <100000>; +- pulldown-ohm = <100000>; +- io-channels = <&adc 1>; +- }; +-}; +- +-&bus_dmc { +- devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; +- vdd-supply = <&buck1_reg>; +- status = "okay"; +-}; +- +-&bus_leftbus { +- devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; +- vdd-supply = <&buck3_reg>; +- status = "okay"; +-}; +- +-&bus_rightbus { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_lcd0 { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_fsys { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_mcuisp { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_isp { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_peril { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_mfc { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&cmu { +- clocks = <&xusbxti>; +-}; +- +-&cpu0 { +- cpu0-supply = <&buck2_reg>; +-}; +- +-&exynos_usbphy { +- status = "okay"; +- vbus-supply = <&safeout_reg>; +-}; +- +-&hsotg { +- vusb_d-supply = <&ldo15_reg>; +- vusb_a-supply = <&ldo12_reg>; +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&dsi_0 { +- vddcore-supply = <&ldo6_reg>; +- vddio-supply = <&ldo6_reg>; +- samsung,burst-clock-frequency = <250000000>; +- samsung,esc-clock-frequency = <20000000>; +- samsung,pll-clock-frequency = <24000000>; +- status = "okay"; +- +- panel@0 { +- compatible = "samsung,s6e63j0x03"; +- reg = <0>; +- vdd3-supply = <&ldo16_reg>; +- vci-supply = <&ldo20_reg>; +- reset-gpios = <&gpe0 1 GPIO_ACTIVE_LOW>; +- te-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&fimd { +- status = "okay"; +- +- i80-if-timings { +- cs-setup = <0>; +- wr-setup = <0>; +- wr-act = <1>; +- wr-hold = <0>; +- }; +-}; +- +-&gpu { +- mali-supply = <&buck3_reg>; +- status = "okay"; +-}; +- +-&i2c_0 { +- #address-cells = <1>; +- #size-cells = <0>; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <100000>; +- status = "okay"; +- +- pmic@66 { +- compatible = "samsung,s2mps14-pmic"; +- interrupt-parent = <&gpx0>; +- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x66>; +- wakeup-source; +- +- s2mps14_osc: clocks { +- compatible = "samsung,s2mps14-clk"; +- #clock-cells = <1>; +- clock-output-names = "s2mps14_ap", "unused", +- "s2mps14_bt"; +- }; +- +- regulators { +- ldo1_reg: LDO1 { +- regulator-name = "VAP_ALIVE_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "VAP_M1_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "VCC_AP_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "VAP_AVDD_PLL1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "VAP_PLL_ISO_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "VAP_VMIPI_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "VAP_AVDD_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "VAP_USB_3.0V"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "V_LPDDR_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "UNUSED_LDO10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "V_EMMC_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "V_EMMC_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "CAM_AVDD_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "UNUSED_LDO14"; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "TSP_AVDD_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "LCD_VDD_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "V_IRLED_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo18_reg: LDO18 { +- regulator-name = "CAM_AF_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo19_reg: LDO19 { +- regulator-name = "TSP_VDD_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo20_reg: LDO20 { +- regulator-name = "LCD_VDD_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo21_reg: LDO21 { +- regulator-name = "CAM_IO_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo22_reg: LDO22 { +- regulator-name = "CAM_DVDD_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo23_reg: LDO23 { +- regulator-name = "HRM_VCC_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo24_reg: LDO24 { +- regulator-name = "HRM_VCC_3.3V"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo25_reg: LDO25 { +- regulator-name = "UNUSED_LDO25"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "VAP_MIF_1.0V"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <900000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "VAP_ARM_1.0V"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1150000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "VAP_INT3D_1.0V"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "VCC_SUB_1.95V"; +- regulator-min-microvolt = <1950000>; +- regulator-max-microvolt = <1950000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "VCC_SUB_1.35V"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- }; +- }; +-}; +- +-&i2c_1 { +- #address-cells = <1>; +- #size-cells = <0>; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <400000>; +- status = "okay"; +- +- fuelgauge@36 { +- compatible = "maxim,max77836-battery"; +- interrupt-parent = <&gpx1>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x36>; +- }; +-}; +- +-&i2s2 { +- status = "okay"; +-}; +- +-&jpeg { +- status = "okay"; +-}; +- +-&mshc_0 { +- broken-cd; +- non-removable; +- cap-mmc-highspeed; +- desc-num = <4>; +- mmc-hs200-1_8v; +- card-detect-delay = <200>; +- vmmc-supply = <&ldo12_reg>; +- clock-frequency = <100000000>; +- max-frequency = <100000000>; +- samsung,dw-mshc-ciu-div = <1>; +- samsung,dw-mshc-sdr-timing = <0 1>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; +- bus-width = <8>; +- status = "okay"; +-}; +- +-&mshc_1 { +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- non-removable; +- cap-sd-highspeed; +- cap-sdio-irq; +- keep-power-in-suspend; +- samsung,dw-mshc-ciu-div = <1>; +- samsung,dw-mshc-sdr-timing = <0 1>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus1 &sd1_bus4>; +- bus-width = <4>; +- +- mmc-pwrseq = <&wlan_pwrseq>; +- +- brcmf: wifi@1 { +- compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; +- reg = <1>; +- +- interrupt-parent = <&gpx1>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "host-wake"; +- }; +-}; +- +-&serial_0 { +- assigned-clocks = <&cmu CLK_SCLK_UART0>; +- assigned-clock-rates = <100000000>; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm4330-bt"; +- max-speed = <3000000>; +- shutdown-gpios = <&gpe0 0 GPIO_ACTIVE_HIGH>; +- device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; +- clocks = <&s2mps14_osc S2MPS11_CLK_BT>; +- }; +-}; +- +-&serial_1 { +- status = "okay"; +-}; +- +-&tmu { +- vtmu-supply = <&ldo7_reg>; +- status = "okay"; +-}; +- +-&rtc { +- clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>; +- clock-names = "rtc", "rtc_src"; +- status = "okay"; +-}; +- +-&xusbxti { +- clock-frequency = <24000000>; +-}; +- +-&pinctrl_0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&initial0 &sleep0>; +- +- initial0: initial-state { +- PIN_IN(gpa1-4, DOWN, LV1); +- PIN_IN(gpa1-5, DOWN, LV1); +- +- PIN_IN(gpc0-0, DOWN, LV1); +- PIN_IN(gpc0-1, DOWN, LV1); +- PIN_IN(gpc0-2, DOWN, LV1); +- PIN_IN(gpc0-3, DOWN, LV1); +- PIN_IN(gpc0-4, DOWN, LV1); +- +- PIN_IN(gpd0-0, DOWN, LV1); +- PIN_IN(gpd0-1, DOWN, LV1); +- }; +- +- sleep0: sleep-state { +- PIN_SLP(gpa0-0, INPUT, DOWN); +- PIN_SLP(gpa0-1, INPUT, DOWN); +- PIN_SLP(gpa0-2, INPUT, DOWN); +- PIN_SLP(gpa0-3, INPUT, DOWN); +- PIN_SLP(gpa0-4, INPUT, DOWN); +- PIN_SLP(gpa0-5, INPUT, DOWN); +- PIN_SLP(gpa0-6, INPUT, DOWN); +- PIN_SLP(gpa0-7, INPUT, DOWN); +- +- PIN_SLP(gpa1-0, INPUT, DOWN); +- PIN_SLP(gpa1-1, INPUT, DOWN); +- PIN_SLP(gpa1-2, INPUT, DOWN); +- PIN_SLP(gpa1-3, INPUT, DOWN); +- PIN_SLP(gpa1-4, INPUT, DOWN); +- PIN_SLP(gpa1-5, INPUT, DOWN); +- +- PIN_SLP(gpb-0, PREV, NONE); +- PIN_SLP(gpb-1, PREV, NONE); +- PIN_SLP(gpb-2, PREV, NONE); +- PIN_SLP(gpb-3, PREV, NONE); +- PIN_SLP(gpb-4, INPUT, DOWN); +- PIN_SLP(gpb-5, INPUT, DOWN); +- PIN_SLP(gpb-6, INPUT, DOWN); +- PIN_SLP(gpb-7, INPUT, DOWN); +- +- PIN_SLP(gpc0-0, INPUT, DOWN); +- PIN_SLP(gpc0-1, INPUT, DOWN); +- PIN_SLP(gpc0-2, INPUT, DOWN); +- PIN_SLP(gpc0-3, INPUT, DOWN); +- PIN_SLP(gpc0-4, INPUT, DOWN); +- +- PIN_SLP(gpc1-0, INPUT, DOWN); +- PIN_SLP(gpc1-1, INPUT, DOWN); +- PIN_SLP(gpc1-2, INPUT, DOWN); +- PIN_SLP(gpc1-3, INPUT, DOWN); +- PIN_SLP(gpc1-4, INPUT, DOWN); +- +- PIN_SLP(gpd0-0, INPUT, DOWN); +- PIN_SLP(gpd0-1, INPUT, DOWN); +- PIN_SLP(gpd0-2, INPUT, NONE); +- PIN_SLP(gpd0-3, INPUT, NONE); +- +- PIN_SLP(gpd1-0, INPUT, NONE); +- PIN_SLP(gpd1-1, INPUT, NONE); +- PIN_SLP(gpd1-2, INPUT, NONE); +- PIN_SLP(gpd1-3, INPUT, NONE); +- }; +-}; +- +-&pinctrl_1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&initial1 &sleep1>; +- +- initial1: initial-state { +- PIN_IN(gpe0-6, DOWN, LV1); +- PIN_IN(gpe0-7, DOWN, LV1); +- +- PIN_IN(gpe1-0, DOWN, LV1); +- PIN_IN(gpe1-3, DOWN, LV1); +- PIN_IN(gpe1-4, DOWN, LV1); +- PIN_IN(gpe1-5, DOWN, LV1); +- PIN_IN(gpe1-6, DOWN, LV1); +- +- PIN_IN(gpk2-0, DOWN, LV1); +- PIN_IN(gpk2-1, DOWN, LV1); +- PIN_IN(gpk2-2, DOWN, LV1); +- PIN_IN(gpk2-3, DOWN, LV1); +- PIN_IN(gpk2-4, DOWN, LV1); +- PIN_IN(gpk2-5, DOWN, LV1); +- PIN_IN(gpk2-6, DOWN, LV1); +- +- PIN_IN(gpm0-0, DOWN, LV1); +- PIN_IN(gpm0-1, DOWN, LV1); +- PIN_IN(gpm0-2, DOWN, LV1); +- PIN_IN(gpm0-3, DOWN, LV1); +- PIN_IN(gpm0-4, DOWN, LV1); +- PIN_IN(gpm0-5, DOWN, LV1); +- PIN_IN(gpm0-6, DOWN, LV1); +- PIN_IN(gpm0-7, DOWN, LV1); +- +- PIN_IN(gpm1-0, DOWN, LV1); +- PIN_IN(gpm1-1, DOWN, LV1); +- PIN_IN(gpm1-2, DOWN, LV1); +- PIN_IN(gpm1-3, DOWN, LV1); +- PIN_IN(gpm1-4, DOWN, LV1); +- PIN_IN(gpm1-5, DOWN, LV1); +- PIN_IN(gpm1-6, DOWN, LV1); +- +- PIN_IN(gpm2-0, DOWN, LV1); +- PIN_IN(gpm2-1, DOWN, LV1); +- +- PIN_IN(gpm3-0, DOWN, LV1); +- PIN_IN(gpm3-1, DOWN, LV1); +- PIN_IN(gpm3-2, DOWN, LV1); +- PIN_IN(gpm3-3, DOWN, LV1); +- PIN_IN(gpm3-4, DOWN, LV1); +- +- PIN_IN(gpm4-1, DOWN, LV1); +- PIN_IN(gpm4-2, DOWN, LV1); +- PIN_IN(gpm4-3, DOWN, LV1); +- PIN_IN(gpm4-4, DOWN, LV1); +- PIN_IN(gpm4-5, DOWN, LV1); +- PIN_IN(gpm4-6, DOWN, LV1); +- PIN_IN(gpm4-7, DOWN, LV1); +- }; +- +- sleep1: sleep-state { +- PIN_SLP(gpe0-0, PREV, NONE); +- PIN_SLP(gpe0-1, PREV, NONE); +- PIN_SLP(gpe0-2, INPUT, DOWN); +- PIN_SLP(gpe0-3, INPUT, UP); +- PIN_SLP(gpe0-4, INPUT, DOWN); +- PIN_SLP(gpe0-5, INPUT, DOWN); +- PIN_SLP(gpe0-6, INPUT, DOWN); +- PIN_SLP(gpe0-7, INPUT, DOWN); +- +- PIN_SLP(gpe1-0, INPUT, DOWN); +- PIN_SLP(gpe1-1, PREV, NONE); +- PIN_SLP(gpe1-2, INPUT, DOWN); +- PIN_SLP(gpe1-3, INPUT, DOWN); +- PIN_SLP(gpe1-4, INPUT, DOWN); +- PIN_SLP(gpe1-5, INPUT, DOWN); +- PIN_SLP(gpe1-6, INPUT, DOWN); +- PIN_SLP(gpe1-7, INPUT, NONE); +- +- PIN_SLP(gpe2-0, INPUT, NONE); +- PIN_SLP(gpe2-1, INPUT, NONE); +- PIN_SLP(gpe2-2, INPUT, NONE); +- +- PIN_SLP(gpk0-0, INPUT, DOWN); +- PIN_SLP(gpk0-1, INPUT, DOWN); +- PIN_SLP(gpk0-2, OUT0, NONE); +- PIN_SLP(gpk0-3, INPUT, DOWN); +- PIN_SLP(gpk0-4, INPUT, DOWN); +- PIN_SLP(gpk0-5, INPUT, DOWN); +- PIN_SLP(gpk0-6, INPUT, DOWN); +- PIN_SLP(gpk0-7, INPUT, DOWN); +- +- PIN_SLP(gpk1-0, INPUT, DOWN); +- PIN_SLP(gpk1-1, INPUT, DOWN); +- PIN_SLP(gpk1-2, INPUT, DOWN); +- PIN_SLP(gpk1-3, INPUT, DOWN); +- PIN_SLP(gpk1-4, INPUT, DOWN); +- PIN_SLP(gpk1-5, INPUT, DOWN); +- PIN_SLP(gpk1-6, INPUT, DOWN); +- +- PIN_SLP(gpk2-0, INPUT, DOWN); +- PIN_SLP(gpk2-1, INPUT, DOWN); +- PIN_SLP(gpk2-2, INPUT, DOWN); +- PIN_SLP(gpk2-3, INPUT, DOWN); +- PIN_SLP(gpk2-4, INPUT, DOWN); +- PIN_SLP(gpk2-5, INPUT, DOWN); +- PIN_SLP(gpk2-6, INPUT, DOWN); +- +- PIN_SLP(gpl0-0, INPUT, DOWN); +- PIN_SLP(gpl0-1, INPUT, DOWN); +- PIN_SLP(gpl0-2, INPUT, DOWN); +- PIN_SLP(gpl0-3, INPUT, DOWN); +- +- PIN_SLP(gpm0-0, INPUT, DOWN); +- PIN_SLP(gpm0-1, INPUT, DOWN); +- PIN_SLP(gpm0-2, INPUT, DOWN); +- PIN_SLP(gpm0-3, INPUT, DOWN); +- PIN_SLP(gpm0-4, INPUT, DOWN); +- PIN_SLP(gpm0-5, INPUT, DOWN); +- PIN_SLP(gpm0-6, INPUT, DOWN); +- PIN_SLP(gpm0-7, INPUT, DOWN); +- +- PIN_SLP(gpm1-0, INPUT, DOWN); +- PIN_SLP(gpm1-1, INPUT, DOWN); +- PIN_SLP(gpm1-2, INPUT, DOWN); +- PIN_SLP(gpm1-3, INPUT, DOWN); +- PIN_SLP(gpm1-4, INPUT, DOWN); +- PIN_SLP(gpm1-5, INPUT, DOWN); +- PIN_SLP(gpm1-6, INPUT, DOWN); +- +- PIN_SLP(gpm2-0, INPUT, DOWN); +- PIN_SLP(gpm2-1, INPUT, DOWN); +- PIN_SLP(gpm2-2, INPUT, DOWN); +- PIN_SLP(gpm2-3, INPUT, DOWN); +- PIN_SLP(gpm2-4, INPUT, DOWN); +- +- PIN_SLP(gpm3-0, INPUT, DOWN); +- PIN_SLP(gpm3-1, INPUT, DOWN); +- PIN_SLP(gpm3-2, INPUT, DOWN); +- PIN_SLP(gpm3-3, INPUT, DOWN); +- PIN_SLP(gpm3-4, INPUT, DOWN); +- PIN_SLP(gpm3-5, INPUT, DOWN); +- PIN_SLP(gpm3-6, INPUT, DOWN); +- PIN_SLP(gpm3-7, INPUT, DOWN); +- +- PIN_SLP(gpm4-0, INPUT, DOWN); +- PIN_SLP(gpm4-1, INPUT, DOWN); +- PIN_SLP(gpm4-2, INPUT, DOWN); +- PIN_SLP(gpm4-3, INPUT, DOWN); +- PIN_SLP(gpm4-4, INPUT, DOWN); +- PIN_SLP(gpm4-5, INPUT, DOWN); +- PIN_SLP(gpm4-6, INPUT, DOWN); +- PIN_SLP(gpm4-7, INPUT, DOWN); +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos3250.dtsi b/scripts/dtc/include-prefixes/arm/exynos3250.dtsi +deleted file mode 100644 +index a10b789d8acf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos3250.dtsi ++++ /dev/null +@@ -1,957 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos3250 SoC device tree source +- * +- * Copyright (c) 2014 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250 +- * based board files can include this file and provide values for board specfic +- * bindings. +- * +- * Note: This file does not include device nodes for all the controllers in +- * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional +- * nodes can be added to this file. +- */ +- +-#include "exynos4-cpu-thermal.dtsi" +-#include +-#include +-#include +- +-/ { +- compatible = "samsung,exynos3250"; +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- pinctrl0 = &pinctrl_0; +- pinctrl1 = &pinctrl_1; +- mshc0 = &mshc_0; +- mshc1 = &mshc_1; +- mshc2 = &mshc_2; +- spi0 = &spi_0; +- spi1 = &spi_1; +- i2c0 = &i2c_0; +- i2c1 = &i2c_1; +- i2c2 = &i2c_2; +- i2c3 = &i2c_3; +- i2c4 = &i2c_4; +- i2c5 = &i2c_5; +- i2c6 = &i2c_6; +- i2c7 = &i2c_7; +- serial0 = &serial_0; +- serial1 = &serial_1; +- serial2 = &serial_2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- }; +- }; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0>; +- clock-frequency = <1000000000>; +- clocks = <&cmu CLK_ARM_CLK>; +- clock-names = "cpu"; +- #cooling-cells = <2>; +- +- operating-points = < +- 1000000 1150000 +- 900000 1112500 +- 800000 1075000 +- 700000 1037500 +- 600000 1000000 +- 500000 962500 +- 400000 925000 +- 300000 887500 +- 200000 850000 +- 100000 850000 +- >; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <1>; +- clock-frequency = <1000000000>; +- clocks = <&cmu CLK_ARM_CLK>; +- clock-names = "cpu"; +- #cooling-cells = <2>; +- +- operating-points = < +- 1000000 1150000 +- 900000 1112500 +- 800000 1075000 +- 700000 1037500 +- 600000 1000000 +- 500000 962500 +- 400000 925000 +- 300000 887500 +- 200000 850000 +- 100000 850000 +- >; +- }; +- }; +- +- xusbxti: clock-0 { +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- #clock-cells = <0>; +- clock-output-names = "xusbxti"; +- }; +- +- xxti: clock-1 { +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- #clock-cells = <0>; +- clock-output-names = "xxti"; +- }; +- +- xtcxo: clock-2 { +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- #clock-cells = <0>; +- clock-output-names = "xtcxo"; +- }; +- +- pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupts = , +- ; +- }; +- +- soc: soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- sram@2020000 { +- compatible = "mmio-sram"; +- reg = <0x02020000 0x40000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x02020000 0x40000>; +- +- smp-sram@0 { +- compatible = "samsung,exynos4210-sysram"; +- reg = <0x0 0x1000>; +- }; +- +- smp-sram@3f000 { +- compatible = "samsung,exynos4210-sysram-ns"; +- reg = <0x3f000 0x1000>; +- }; +- }; +- +- chipid@10000000 { +- compatible = "samsung,exynos4210-chipid"; +- reg = <0x10000000 0x100>; +- }; +- +- sys_reg: syscon@10010000 { +- compatible = "samsung,exynos3-sysreg", "syscon"; +- reg = <0x10010000 0x400>; +- }; +- +- pmu_system_controller: system-controller@10020000 { +- compatible = "samsung,exynos3250-pmu", "syscon"; +- reg = <0x10020000 0x4000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- clock-names = "clkout8"; +- clocks = <&cmu CLK_FIN_PLL>; +- #clock-cells = <1>; +- }; +- +- mipi_phy: video-phy { +- compatible = "samsung,s5pv210-mipi-video-phy"; +- #phy-cells = <1>; +- syscon = <&pmu_system_controller>; +- }; +- +- pd_cam: power-domain@10023c00 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10023C00 0x20>; +- #power-domain-cells = <0>; +- label = "CAM"; +- }; +- +- pd_mfc: power-domain@10023c40 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10023C40 0x20>; +- #power-domain-cells = <0>; +- label = "MFC"; +- }; +- +- pd_g3d: power-domain@10023c60 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10023C60 0x20>; +- #power-domain-cells = <0>; +- label = "G3D"; +- }; +- +- pd_lcd0: power-domain@10023c80 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10023C80 0x20>; +- #power-domain-cells = <0>; +- label = "LCD0"; +- }; +- +- pd_isp: power-domain@10023ca0 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10023CA0 0x20>; +- #power-domain-cells = <0>; +- label = "ISP"; +- }; +- +- cmu: clock-controller@10030000 { +- compatible = "samsung,exynos3250-cmu"; +- reg = <0x10030000 0x20000>; +- #clock-cells = <1>; +- assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>, +- <&cmu CLK_MOUT_ACLK_266_SUB>; +- assigned-clock-parents = <&cmu CLK_FIN_PLL>, +- <&cmu CLK_FIN_PLL>; +- }; +- +- cmu_dmc: clock-controller@105c0000 { +- compatible = "samsung,exynos3250-cmu-dmc"; +- reg = <0x105C0000 0x2000>; +- #clock-cells = <1>; +- }; +- +- rtc: rtc@10070000 { +- compatible = "samsung,s3c6410-rtc"; +- reg = <0x10070000 0x100>; +- interrupts = , +- ; +- interrupt-parent = <&pmu_system_controller>; +- status = "disabled"; +- }; +- +- tmu: tmu@100c0000 { +- compatible = "samsung,exynos3250-tmu"; +- reg = <0x100C0000 0x100>; +- interrupts = ; +- clocks = <&cmu CLK_TMU_APBIF>; +- clock-names = "tmu_apbif"; +- #thermal-sensor-cells = <0>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@10481000 { +- compatible = "arm,cortex-a15-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x10481000 0x1000>, +- <0x10482000 0x2000>, +- <0x10484000 0x2000>, +- <0x10486000 0x2000>; +- interrupts = ; +- }; +- +- timer@10050000 { +- compatible = "samsung,exynos4210-mct"; +- reg = <0x10050000 0x800>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; +- clock-names = "fin_pll", "mct"; +- }; +- +- pinctrl_1: pinctrl@11000000 { +- compatible = "samsung,exynos3250-pinctrl"; +- reg = <0x11000000 0x1000>; +- interrupts = ; +- +- wakeup-interrupt-controller { +- compatible = "samsung,exynos4210-wakeup-eint"; +- interrupts = ; +- }; +- }; +- +- pinctrl_0: pinctrl@11400000 { +- compatible = "samsung,exynos3250-pinctrl"; +- reg = <0x11400000 0x1000>; +- interrupts = ; +- }; +- +- jpeg: codec@11830000 { +- compatible = "samsung,exynos3250-jpeg"; +- reg = <0x11830000 0x1000>; +- interrupts = ; +- clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>; +- clock-names = "jpeg", "sclk"; +- power-domains = <&pd_cam>; +- assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>; +- assigned-clock-rates = <0>, <150000000>; +- assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>; +- iommus = <&sysmmu_jpeg>; +- status = "disabled"; +- }; +- +- sysmmu_jpeg: sysmmu@11a60000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x11a60000 0x1000>; +- interrupts = ; +- clock-names = "sysmmu", "master"; +- clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>; +- power-domains = <&pd_cam>; +- #iommu-cells = <0>; +- }; +- +- fimd: fimd@11c00000 { +- compatible = "samsung,exynos3250-fimd"; +- reg = <0x11c00000 0x30000>; +- interrupt-names = "fifo", "vsync", "lcd_sys"; +- interrupts = , +- , +- ; +- clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; +- clock-names = "sclk_fimd", "fimd"; +- power-domains = <&pd_lcd0>; +- iommus = <&sysmmu_fimd0>; +- samsung,sysreg = <&sys_reg>; +- status = "disabled"; +- }; +- +- dsi_0: dsi@11c80000 { +- compatible = "samsung,exynos3250-mipi-dsi"; +- reg = <0x11C80000 0x10000>; +- interrupts = ; +- samsung,phy-type = <0>; +- power-domains = <&pd_lcd0>; +- phys = <&mipi_phy 1>; +- phy-names = "dsim"; +- clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; +- clock-names = "bus_clk", "pll_clk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- sysmmu_fimd0: sysmmu@11e20000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x11e20000 0x1000>; +- interrupts = ; +- clock-names = "sysmmu", "master"; +- clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; +- power-domains = <&pd_lcd0>; +- #iommu-cells = <0>; +- }; +- +- hsotg: hsotg@12480000 { +- compatible = "samsung,s3c6400-hsotg"; +- reg = <0x12480000 0x20000>; +- interrupts = ; +- clocks = <&cmu CLK_USBOTG>; +- clock-names = "otg"; +- phys = <&exynos_usbphy 0>; +- phy-names = "usb2-phy"; +- status = "disabled"; +- }; +- +- mshc_0: mshc@12510000 { +- compatible = "samsung,exynos5420-dw-mshc"; +- reg = <0x12510000 0x1000>; +- interrupts = ; +- clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- mshc_1: mshc@12520000 { +- compatible = "samsung,exynos5420-dw-mshc"; +- reg = <0x12520000 0x1000>; +- interrupts = ; +- clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- mshc_2: mshc@12530000 { +- compatible = "samsung,exynos5250-dw-mshc"; +- reg = <0x12530000 0x1000>; +- interrupts = ; +- clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- exynos_usbphy: exynos-usbphy@125b0000 { +- compatible = "samsung,exynos3250-usb2-phy"; +- reg = <0x125B0000 0x100>; +- samsung,pmureg-phandle = <&pmu_system_controller>; +- clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>; +- clock-names = "phy", "ref"; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- pdma0: pdma@12680000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x12680000 0x1000>; +- interrupts = ; +- clocks = <&cmu CLK_PDMA0>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- }; +- +- pdma1: pdma@12690000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x12690000 0x1000>; +- interrupts = ; +- clocks = <&cmu CLK_PDMA1>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- }; +- +- adc: adc@126c0000 { +- compatible = "samsung,exynos3250-adc"; +- reg = <0x126C0000 0x100>; +- interrupts = ; +- clock-names = "adc", "sclk"; +- clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; +- #io-channel-cells = <1>; +- samsung,syscon-phandle = <&pmu_system_controller>; +- status = "disabled"; +- }; +- +- gpu: gpu@13000000 { +- compatible = "samsung,exynos4210-mali", "arm,mali-400"; +- reg = <0x13000000 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "gp", +- "gpmmu", +- "pp0", +- "ppmmu0", +- "pp1", +- "ppmmu1", +- "pp2", +- "ppmmu2", +- "pp3", +- "ppmmu3", +- "pmu"; +- clocks = <&cmu CLK_G3D>, +- <&cmu CLK_SCLK_G3D>; +- clock-names = "bus", "core"; +- power-domains = <&pd_g3d>; +- status = "disabled"; +- /* TODO: operating points for DVFS, assigned clock as 134 MHz */ +- }; +- +- mfc: codec@13400000 { +- compatible = "samsung,mfc-v7"; +- reg = <0x13400000 0x10000>; +- interrupts = ; +- clock-names = "mfc", "sclk_mfc"; +- clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; +- power-domains = <&pd_mfc>; +- iommus = <&sysmmu_mfc>; +- }; +- +- sysmmu_mfc: sysmmu@13620000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13620000 0x1000>; +- interrupts = ; +- clock-names = "sysmmu", "master"; +- clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>; +- power-domains = <&pd_mfc>; +- #iommu-cells = <0>; +- }; +- +- serial_0: serial@13800000 { +- compatible = "samsung,exynos4210-uart"; +- reg = <0x13800000 0x100>; +- interrupts = ; +- clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; +- clock-names = "uart", "clk_uart_baud0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_data &uart0_fctl>; +- status = "disabled"; +- }; +- +- serial_1: serial@13810000 { +- compatible = "samsung,exynos4210-uart"; +- reg = <0x13810000 0x100>; +- interrupts = ; +- clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; +- clock-names = "uart", "clk_uart_baud0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_data>; +- status = "disabled"; +- }; +- +- serial_2: serial@13820000 { +- compatible = "samsung,exynos4210-uart"; +- reg = <0x13820000 0x100>; +- interrupts = ; +- clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; +- clock-names = "uart", "clk_uart_baud0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_data>; +- status = "disabled"; +- }; +- +- i2c_0: i2c@13860000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x13860000 0x100>; +- interrupts = ; +- clocks = <&cmu CLK_I2C0>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_bus>; +- status = "disabled"; +- }; +- +- i2c_1: i2c@13870000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x13870000 0x100>; +- interrupts = ; +- clocks = <&cmu CLK_I2C1>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_bus>; +- status = "disabled"; +- }; +- +- i2c_2: i2c@13880000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x13880000 0x100>; +- interrupts = ; +- clocks = <&cmu CLK_I2C2>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_bus>; +- status = "disabled"; +- }; +- +- i2c_3: i2c@13890000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x13890000 0x100>; +- interrupts = ; +- clocks = <&cmu CLK_I2C3>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_bus>; +- status = "disabled"; +- }; +- +- i2c_4: i2c@138a0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x138A0000 0x100>; +- interrupts = ; +- clocks = <&cmu CLK_I2C4>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_bus>; +- status = "disabled"; +- }; +- +- i2c_5: i2c@138b0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x138B0000 0x100>; +- interrupts = ; +- clocks = <&cmu CLK_I2C5>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_bus>; +- status = "disabled"; +- }; +- +- i2c_6: i2c@138c0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x138C0000 0x100>; +- interrupts = ; +- clocks = <&cmu CLK_I2C6>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c6_bus>; +- status = "disabled"; +- }; +- +- i2c_7: i2c@138d0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x138D0000 0x100>; +- interrupts = ; +- clocks = <&cmu CLK_I2C7>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c7_bus>; +- status = "disabled"; +- }; +- +- spi_0: spi@13920000 { +- compatible = "samsung,exynos4210-spi"; +- reg = <0x13920000 0x100>; +- interrupts = ; +- dmas = <&pdma0 7>, <&pdma0 6>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; +- clock-names = "spi", "spi_busclk0"; +- samsung,spi-src-clk = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_bus>; +- status = "disabled"; +- }; +- +- spi_1: spi@13930000 { +- compatible = "samsung,exynos4210-spi"; +- reg = <0x13930000 0x100>; +- interrupts = ; +- dmas = <&pdma1 7>, <&pdma1 6>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; +- clock-names = "spi", "spi_busclk0"; +- samsung,spi-src-clk = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_bus>; +- status = "disabled"; +- }; +- +- i2s2: i2s@13970000 { +- compatible = "samsung,s3c6410-i2s"; +- reg = <0x13970000 0x100>; +- interrupts = ; +- clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>; +- clock-names = "iis", "i2s_opclk0"; +- dmas = <&pdma0 14>, <&pdma0 13>; +- dma-names = "tx", "rx"; +- pinctrl-0 = <&i2s2_bus>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- pwm: pwm@139d0000 { +- compatible = "samsung,exynos4210-pwm"; +- reg = <0x139D0000 0x1000>; +- interrupts = , +- , +- , +- , +- ; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- ppmu_dmc0: ppmu@106a0000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x106a0000 0x2000>; +- status = "disabled"; +- }; +- +- ppmu_dmc1: ppmu@106b0000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x106b0000 0x2000>; +- status = "disabled"; +- }; +- +- ppmu_cpu: ppmu@106c0000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x106c0000 0x2000>; +- status = "disabled"; +- }; +- +- ppmu_rightbus: ppmu@112a0000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x112a0000 0x2000>; +- clocks = <&cmu CLK_PPMURIGHT>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- ppmu_leftbus: ppmu@116a0000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x116a0000 0x2000>; +- clocks = <&cmu CLK_PPMULEFT>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- ppmu_camif: ppmu@11ac0000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x11ac0000 0x2000>; +- clocks = <&cmu CLK_PPMUCAMIF>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- ppmu_lcd0: ppmu@11e40000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x11e40000 0x2000>; +- clocks = <&cmu CLK_PPMULCD0>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- ppmu_fsys: ppmu@12630000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x12630000 0x2000>; +- clocks = <&cmu CLK_PPMUFILE>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- ppmu_g3d: ppmu@13220000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x13220000 0x2000>; +- clocks = <&cmu CLK_PPMUG3D>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- ppmu_mfc: ppmu@13660000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x13660000 0x2000>; +- clocks = <&cmu CLK_PPMUMFC_L>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- bus_dmc: bus-dmc { +- compatible = "samsung,exynos-bus"; +- clocks = <&cmu_dmc CLK_DIV_DMC>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_dmc_opp_table>; +- status = "disabled"; +- }; +- +- bus_dmc_opp_table: opp-table1 { +- compatible = "operating-points-v2"; +- +- opp-50000000 { +- opp-hz = /bits/ 64 <50000000>; +- opp-microvolt = <800000>; +- }; +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- opp-microvolt = <800000>; +- }; +- opp-134000000 { +- opp-hz = /bits/ 64 <134000000>; +- opp-microvolt = <800000>; +- }; +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- opp-microvolt = <825000>; +- }; +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <875000>; +- }; +- }; +- +- bus_leftbus: bus-leftbus { +- compatible = "samsung,exynos-bus"; +- clocks = <&cmu CLK_DIV_GDL>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_leftbus_opp_table>; +- status = "disabled"; +- }; +- +- bus_rightbus: bus-rightbus { +- compatible = "samsung,exynos-bus"; +- clocks = <&cmu CLK_DIV_GDR>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_leftbus_opp_table>; +- status = "disabled"; +- }; +- +- bus_lcd0: bus-lcd0 { +- compatible = "samsung,exynos-bus"; +- clocks = <&cmu CLK_DIV_ACLK_160>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_leftbus_opp_table>; +- status = "disabled"; +- }; +- +- bus_fsys: bus-fsys { +- compatible = "samsung,exynos-bus"; +- clocks = <&cmu CLK_DIV_ACLK_200>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_leftbus_opp_table>; +- status = "disabled"; +- }; +- +- bus_mcuisp: bus-mcuisp { +- compatible = "samsung,exynos-bus"; +- clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_mcuisp_opp_table>; +- status = "disabled"; +- }; +- +- bus_isp: bus-isp { +- compatible = "samsung,exynos-bus"; +- clocks = <&cmu CLK_DIV_ACLK_266>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_isp_opp_table>; +- status = "disabled"; +- }; +- +- bus_peril: bus-peril { +- compatible = "samsung,exynos-bus"; +- clocks = <&cmu CLK_DIV_ACLK_100>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_peril_opp_table>; +- status = "disabled"; +- }; +- +- bus_mfc: bus-mfc { +- compatible = "samsung,exynos-bus"; +- clocks = <&cmu CLK_SCLK_MFC>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_leftbus_opp_table>; +- status = "disabled"; +- }; +- +- bus_leftbus_opp_table: opp-table2 { +- compatible = "operating-points-v2"; +- +- opp-50000000 { +- opp-hz = /bits/ 64 <50000000>; +- opp-microvolt = <900000>; +- }; +- opp-80000000 { +- opp-hz = /bits/ 64 <80000000>; +- opp-microvolt = <900000>; +- }; +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- opp-microvolt = <1000000>; +- }; +- opp-134000000 { +- opp-hz = /bits/ 64 <134000000>; +- opp-microvolt = <1000000>; +- }; +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- opp-microvolt = <1000000>; +- }; +- }; +- +- bus_mcuisp_opp_table: opp-table3 { +- compatible = "operating-points-v2"; +- +- opp-50000000 { +- opp-hz = /bits/ 64 <50000000>; +- }; +- opp-80000000 { +- opp-hz = /bits/ 64 <80000000>; +- }; +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- }; +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- }; +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- }; +- }; +- +- bus_isp_opp_table: opp-table4 { +- compatible = "operating-points-v2"; +- +- opp-50000000 { +- opp-hz = /bits/ 64 <50000000>; +- }; +- opp-80000000 { +- opp-hz = /bits/ 64 <80000000>; +- }; +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- }; +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- }; +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- }; +- }; +- +- bus_peril_opp_table: opp-table5 { +- compatible = "operating-points-v2"; +- +- opp-50000000 { +- opp-hz = /bits/ 64 <50000000>; +- }; +- opp-80000000 { +- opp-hz = /bits/ 64 <80000000>; +- }; +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- }; +- }; +- }; +-}; +- +-#include "exynos3250-pinctrl.dtsi" +-#include "exynos-syscon-restart.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/exynos4-cpu-thermal.dtsi b/scripts/dtc/include-prefixes/arm/exynos4-cpu-thermal.dtsi +deleted file mode 100644 +index 021d9fc1b492..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4-cpu-thermal.dtsi ++++ /dev/null +@@ -1,48 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device tree sources for Exynos4 thermal zone +- * +- * Copyright (c) 2014 Lukasz Majewski +- */ +- +-#include +- +-/ { +-thermal-zones { +- cpu_thermal: cpu-thermal { +- thermal-sensors = <&tmu 0>; +- polling-delay-passive = <0>; +- polling-delay = <0>; +- trips { +- cpu_alert0: cpu-alert-0 { +- temperature = <70000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "active"; +- }; +- cpu_alert1: cpu-alert-1 { +- temperature = <95000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "active"; +- }; +- cpu_alert2: cpu-alert-2 { +- temperature = <110000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "active"; +- }; +- cpu_crit0: cpu-crit-0 { +- temperature = <120000>; /* millicelsius */ +- hysteresis = <0>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- }; +- map1 { +- trip = <&cpu_alert1>; +- }; +- }; +- }; +-}; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4.dtsi b/scripts/dtc/include-prefixes/arm/exynos4.dtsi +deleted file mode 100644 +index eab77a66ae8f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4.dtsi ++++ /dev/null +@@ -1,1014 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos4 SoC series common device tree source +- * +- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * Copyright (c) 2010-2011 Linaro Ltd. +- * www.linaro.org +- * +- * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular +- * SoCs from Exynos4 series can include this file and provide values for SoCs +- * specfic bindings. +- * +- * Note: This file does not include device nodes for all the controllers in +- * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional +- * nodes can be added to this file. +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- spi0 = &spi_0; +- spi1 = &spi_1; +- spi2 = &spi_2; +- i2c0 = &i2c_0; +- i2c1 = &i2c_1; +- i2c2 = &i2c_2; +- i2c3 = &i2c_3; +- i2c4 = &i2c_4; +- i2c5 = &i2c_5; +- i2c6 = &i2c_6; +- i2c7 = &i2c_7; +- i2c8 = &i2c_8; +- csis0 = &csis_0; +- csis1 = &csis_1; +- fimc0 = &fimc_0; +- fimc1 = &fimc_1; +- fimc2 = &fimc_2; +- fimc3 = &fimc_3; +- serial0 = &serial_0; +- serial1 = &serial_1; +- serial2 = &serial_2; +- serial3 = &serial_3; +- }; +- +- pmu: pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupt-parent = <&combiner>; +- status = "disabled"; +- }; +- +- soc: soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clock_audss: clock-controller@3810000 { +- compatible = "samsung,exynos4210-audss-clock"; +- reg = <0x03810000 0x0C>; +- #clock-cells = <1>; +- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, +- <&clock CLK_SCLK_AUDIO0>, +- <&clock CLK_SCLK_AUDIO0>; +- clock-names = "pll_ref", "pll_in", "sclk_audio", +- "sclk_pcm_in"; +- }; +- +- i2s0: i2s@3830000 { +- compatible = "samsung,s5pv210-i2s"; +- reg = <0x03830000 0x100>; +- clocks = <&clock_audss EXYNOS_I2S_BUS>, +- <&clock_audss EXYNOS_DOUT_AUD_BUS>, +- <&clock_audss EXYNOS_SCLK_I2S>; +- clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; +- #clock-cells = <1>; +- clock-output-names = "i2s_cdclk0"; +- dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>; +- dma-names = "tx", "rx", "tx-sec"; +- samsung,idma-addr = <0x03000000>; +- #sound-dai-cells = <1>; +- status = "disabled"; +- }; +- +- chipid@10000000 { +- compatible = "samsung,exynos4210-chipid"; +- reg = <0x10000000 0x100>; +- }; +- +- scu: snoop-control-unit@10500000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0x10500000 0x2000>; +- }; +- +- memory-controller@12570000 { +- compatible = "samsung,exynos4210-srom"; +- reg = <0x12570000 0x14>; +- }; +- +- mipi_phy: video-phy { +- compatible = "samsung,s5pv210-mipi-video-phy"; +- #phy-cells = <1>; +- syscon = <&pmu_system_controller>; +- }; +- +- pd_mfc: power-domain@10023c40 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10023C40 0x20>; +- #power-domain-cells = <0>; +- label = "MFC"; +- }; +- +- pd_g3d: power-domain@10023c60 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10023C60 0x20>; +- #power-domain-cells = <0>; +- label = "G3D"; +- }; +- +- pd_lcd0: power-domain@10023c80 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10023C80 0x20>; +- #power-domain-cells = <0>; +- label = "LCD0"; +- }; +- +- pd_tv: power-domain@10023c20 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10023C20 0x20>; +- #power-domain-cells = <0>; +- power-domains = <&pd_lcd0>; +- label = "TV"; +- }; +- +- pd_cam: power-domain@10023c00 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10023C00 0x20>; +- #power-domain-cells = <0>; +- label = "CAM"; +- }; +- +- pd_gps: power-domain@10023ce0 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10023CE0 0x20>; +- #power-domain-cells = <0>; +- label = "GPS"; +- }; +- +- pd_gps_alive: power-domain@10023d00 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10023D00 0x20>; +- #power-domain-cells = <0>; +- label = "GPS alive"; +- }; +- +- gic: interrupt-controller@10490000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x10490000 0x10000>, <0x10480000 0x10000>; +- }; +- +- combiner: interrupt-controller@10440000 { +- compatible = "samsung,exynos4210-combiner"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0x10440000 0x1000>; +- }; +- +- sys_reg: syscon@10010000 { +- compatible = "samsung,exynos4-sysreg", "syscon"; +- reg = <0x10010000 0x400>; +- }; +- +- pmu_system_controller: system-controller@10020000 { +- compatible = "samsung,exynos4210-pmu", "syscon"; +- reg = <0x10020000 0x4000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- }; +- +- dsi_0: dsi@11c80000 { +- compatible = "samsung,exynos4210-mipi-dsi"; +- reg = <0x11C80000 0x10000>; +- interrupts = ; +- power-domains = <&pd_lcd0>; +- phys = <&mipi_phy 1>; +- phy-names = "dsim"; +- clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; +- clock-names = "bus_clk", "sclk_mipi"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- camera: camera { +- compatible = "samsung,fimc", "simple-bus"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- #clock-cells = <1>; +- clock-output-names = "cam_a_clkout", "cam_b_clkout"; +- ranges; +- +- fimc_0: fimc@11800000 { +- compatible = "samsung,exynos4210-fimc"; +- reg = <0x11800000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_FIMC0>, +- <&clock CLK_SCLK_FIMC0>; +- clock-names = "fimc", "sclk_fimc"; +- power-domains = <&pd_cam>; +- samsung,sysreg = <&sys_reg>; +- iommus = <&sysmmu_fimc0>; +- status = "disabled"; +- }; +- +- fimc_1: fimc@11810000 { +- compatible = "samsung,exynos4210-fimc"; +- reg = <0x11810000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_FIMC1>, +- <&clock CLK_SCLK_FIMC1>; +- clock-names = "fimc", "sclk_fimc"; +- power-domains = <&pd_cam>; +- samsung,sysreg = <&sys_reg>; +- iommus = <&sysmmu_fimc1>; +- status = "disabled"; +- }; +- +- fimc_2: fimc@11820000 { +- compatible = "samsung,exynos4210-fimc"; +- reg = <0x11820000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_FIMC2>, +- <&clock CLK_SCLK_FIMC2>; +- clock-names = "fimc", "sclk_fimc"; +- power-domains = <&pd_cam>; +- samsung,sysreg = <&sys_reg>; +- iommus = <&sysmmu_fimc2>; +- status = "disabled"; +- }; +- +- fimc_3: fimc@11830000 { +- compatible = "samsung,exynos4210-fimc"; +- reg = <0x11830000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_FIMC3>, +- <&clock CLK_SCLK_FIMC3>; +- clock-names = "fimc", "sclk_fimc"; +- power-domains = <&pd_cam>; +- samsung,sysreg = <&sys_reg>; +- iommus = <&sysmmu_fimc3>; +- status = "disabled"; +- }; +- +- csis_0: csis@11880000 { +- compatible = "samsung,exynos4210-csis"; +- reg = <0x11880000 0x4000>; +- interrupts = ; +- clocks = <&clock CLK_CSIS0>, +- <&clock CLK_SCLK_CSIS0>; +- clock-names = "csis", "sclk_csis"; +- bus-width = <4>; +- power-domains = <&pd_cam>; +- phys = <&mipi_phy 0>; +- phy-names = "csis"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- csis_1: csis@11890000 { +- compatible = "samsung,exynos4210-csis"; +- reg = <0x11890000 0x4000>; +- interrupts = ; +- clocks = <&clock CLK_CSIS1>, +- <&clock CLK_SCLK_CSIS1>; +- clock-names = "csis", "sclk_csis"; +- bus-width = <2>; +- power-domains = <&pd_cam>; +- phys = <&mipi_phy 2>; +- phy-names = "csis"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- rtc: rtc@10070000 { +- compatible = "samsung,s3c6410-rtc"; +- reg = <0x10070000 0x100>; +- interrupt-parent = <&pmu_system_controller>; +- interrupts = , +- ; +- clocks = <&clock CLK_RTC>; +- clock-names = "rtc"; +- status = "disabled"; +- }; +- +- keypad: keypad@100a0000 { +- compatible = "samsung,s5pv210-keypad"; +- reg = <0x100A0000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_KEYIF>; +- clock-names = "keypad"; +- status = "disabled"; +- }; +- +- sdhci_0: sdhci@12510000 { +- compatible = "samsung,exynos4210-sdhci"; +- reg = <0x12510000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; +- clock-names = "hsmmc", "mmc_busclk.2"; +- status = "disabled"; +- }; +- +- sdhci_1: sdhci@12520000 { +- compatible = "samsung,exynos4210-sdhci"; +- reg = <0x12520000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; +- clock-names = "hsmmc", "mmc_busclk.2"; +- status = "disabled"; +- }; +- +- sdhci_2: sdhci@12530000 { +- compatible = "samsung,exynos4210-sdhci"; +- reg = <0x12530000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; +- clock-names = "hsmmc", "mmc_busclk.2"; +- status = "disabled"; +- }; +- +- sdhci_3: sdhci@12540000 { +- compatible = "samsung,exynos4210-sdhci"; +- reg = <0x12540000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; +- clock-names = "hsmmc", "mmc_busclk.2"; +- status = "disabled"; +- }; +- +- exynos_usbphy: exynos-usbphy@125b0000 { +- compatible = "samsung,exynos4210-usb2-phy"; +- reg = <0x125B0000 0x100>; +- samsung,pmureg-phandle = <&pmu_system_controller>; +- clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>; +- clock-names = "phy", "ref"; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- hsotg: hsotg@12480000 { +- compatible = "samsung,s3c6400-hsotg"; +- reg = <0x12480000 0x20000>; +- interrupts = ; +- clocks = <&clock CLK_USB_DEVICE>; +- clock-names = "otg"; +- phys = <&exynos_usbphy 0>; +- phy-names = "usb2-phy"; +- status = "disabled"; +- }; +- +- ehci: ehci@12580000 { +- compatible = "samsung,exynos4210-ehci"; +- reg = <0x12580000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_USB_HOST>; +- clock-names = "usbhost"; +- status = "disabled"; +- phys = <&exynos_usbphy 1>, <&exynos_usbphy 2>, <&exynos_usbphy 3>; +- phy-names = "host", "hsic0", "hsic1"; +- }; +- +- ohci: ohci@12590000 { +- compatible = "samsung,exynos4210-ohci"; +- reg = <0x12590000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_USB_HOST>; +- clock-names = "usbhost"; +- status = "disabled"; +- phys = <&exynos_usbphy 1>; +- phy-names = "host"; +- }; +- +- gpu: gpu@13000000 { +- compatible = "samsung,exynos4210-mali", "arm,mali-400"; +- reg = <0x13000000 0x10000>; +- /* +- * CLK_G3D is not actually bus clock but a IP-level clock. +- * The bus clock is not described in hardware manual. +- */ +- clocks = <&clock CLK_G3D>, +- <&clock CLK_SCLK_G3D>; +- clock-names = "bus", "core"; +- power-domains = <&pd_g3d>; +- status = "disabled"; +- }; +- +- i2s1: i2s@13960000 { +- compatible = "samsung,s3c6410-i2s"; +- reg = <0x13960000 0x100>; +- clocks = <&clock CLK_I2S1>; +- clock-names = "iis"; +- #clock-cells = <1>; +- clock-output-names = "i2s_cdclk1"; +- dmas = <&pdma1 12>, <&pdma1 11>; +- dma-names = "tx", "rx"; +- #sound-dai-cells = <1>; +- status = "disabled"; +- }; +- +- i2s2: i2s@13970000 { +- compatible = "samsung,s3c6410-i2s"; +- reg = <0x13970000 0x100>; +- clocks = <&clock CLK_I2S2>; +- clock-names = "iis"; +- #clock-cells = <1>; +- clock-output-names = "i2s_cdclk2"; +- dmas = <&pdma0 14>, <&pdma0 13>; +- dma-names = "tx", "rx"; +- #sound-dai-cells = <1>; +- status = "disabled"; +- }; +- +- mfc: codec@13400000 { +- compatible = "samsung,mfc-v5"; +- reg = <0x13400000 0x10000>; +- interrupts = ; +- power-domains = <&pd_mfc>; +- clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; +- clock-names = "mfc", "sclk_mfc"; +- iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; +- iommu-names = "left", "right"; +- }; +- +- serial_0: serial@13800000 { +- compatible = "samsung,exynos4210-uart"; +- reg = <0x13800000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; +- clock-names = "uart", "clk_uart_baud0"; +- dmas = <&pdma0 15>, <&pdma0 16>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- serial_1: serial@13810000 { +- compatible = "samsung,exynos4210-uart"; +- reg = <0x13810000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; +- clock-names = "uart", "clk_uart_baud0"; +- dmas = <&pdma1 15>, <&pdma1 16>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- serial_2: serial@13820000 { +- compatible = "samsung,exynos4210-uart"; +- reg = <0x13820000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; +- clock-names = "uart", "clk_uart_baud0"; +- dmas = <&pdma0 17>, <&pdma0 18>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- serial_3: serial@13830000 { +- compatible = "samsung,exynos4210-uart"; +- reg = <0x13830000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; +- clock-names = "uart", "clk_uart_baud0"; +- dmas = <&pdma1 17>, <&pdma1 18>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c_0: i2c@13860000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x13860000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_I2C0>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_bus>; +- status = "disabled"; +- }; +- +- i2c_1: i2c@13870000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x13870000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_I2C1>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_bus>; +- status = "disabled"; +- }; +- +- i2c_2: i2c@13880000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x13880000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_I2C2>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_bus>; +- status = "disabled"; +- }; +- +- i2c_3: i2c@13890000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x13890000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_I2C3>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_bus>; +- status = "disabled"; +- }; +- +- i2c_4: i2c@138a0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x138A0000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_I2C4>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_bus>; +- status = "disabled"; +- }; +- +- i2c_5: i2c@138b0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x138B0000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_I2C5>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_bus>; +- status = "disabled"; +- }; +- +- i2c_6: i2c@138c0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x138C0000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_I2C6>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c6_bus>; +- status = "disabled"; +- }; +- +- i2c_7: i2c@138d0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x138D0000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_I2C7>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c7_bus>; +- status = "disabled"; +- }; +- +- i2c_8: i2c@138e0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "samsung,s3c2440-hdmiphy-i2c"; +- reg = <0x138E0000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_I2C_HDMI>; +- clock-names = "i2c"; +- status = "disabled"; +- +- hdmi_i2c_phy: hdmiphy@38 { +- compatible = "exynos4210-hdmiphy"; +- reg = <0x38>; +- }; +- }; +- +- spi_0: spi@13920000 { +- compatible = "samsung,exynos4210-spi"; +- reg = <0x13920000 0x100>; +- interrupts = ; +- dmas = <&pdma0 7>, <&pdma0 6>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; +- clock-names = "spi", "spi_busclk0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_bus>; +- status = "disabled"; +- }; +- +- spi_1: spi@13930000 { +- compatible = "samsung,exynos4210-spi"; +- reg = <0x13930000 0x100>; +- interrupts = ; +- dmas = <&pdma1 7>, <&pdma1 6>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; +- clock-names = "spi", "spi_busclk0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_bus>; +- status = "disabled"; +- }; +- +- spi_2: spi@13940000 { +- compatible = "samsung,exynos4210-spi"; +- reg = <0x13940000 0x100>; +- interrupts = ; +- dmas = <&pdma0 9>, <&pdma0 8>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; +- clock-names = "spi", "spi_busclk0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_bus>; +- status = "disabled"; +- }; +- +- pwm: pwm@139d0000 { +- compatible = "samsung,exynos4210-pwm"; +- reg = <0x139D0000 0x1000>; +- interrupts = , +- , +- , +- , +- ; +- clocks = <&clock CLK_PWM>; +- clock-names = "timers"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pdma0: pdma@12680000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x12680000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_PDMA0>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- }; +- +- pdma1: pdma@12690000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x12690000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_PDMA1>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- }; +- +- mdma1: mdma@12850000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x12850000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_MDMA>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <1>; +- }; +- +- fimd: fimd@11c00000 { +- compatible = "samsung,exynos4210-fimd"; +- interrupt-parent = <&combiner>; +- reg = <0x11c00000 0x20000>; +- interrupt-names = "fifo", "vsync", "lcd_sys"; +- interrupts = <11 0>, <11 1>, <11 2>; +- clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; +- clock-names = "sclk_fimd", "fimd"; +- power-domains = <&pd_lcd0>; +- iommus = <&sysmmu_fimd0>; +- samsung,sysreg = <&sys_reg>; +- status = "disabled"; +- }; +- +- tmu: tmu@100c0000 { +- interrupt-parent = <&combiner>; +- reg = <0x100C0000 0x100>; +- interrupts = <2 4>; +- status = "disabled"; +- #thermal-sensor-cells = <0>; +- }; +- +- jpeg_codec: jpeg-codec@11840000 { +- compatible = "samsung,exynos4210-jpeg"; +- reg = <0x11840000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_JPEG>; +- clock-names = "jpeg"; +- power-domains = <&pd_cam>; +- iommus = <&sysmmu_jpeg>; +- }; +- +- rotator: rotator@12810000 { +- compatible = "samsung,exynos4210-rotator"; +- reg = <0x12810000 0x64>; +- interrupts = ; +- clocks = <&clock CLK_ROTATOR>; +- clock-names = "rotator"; +- iommus = <&sysmmu_rotator>; +- }; +- +- hdmi: hdmi@12d00000 { +- compatible = "samsung,exynos4210-hdmi"; +- reg = <0x12D00000 0x70000>; +- interrupts = ; +- clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", +- "sclk_hdmiphy", "mout_hdmi"; +- clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, +- <&clock CLK_SCLK_PIXEL>, +- <&clock CLK_SCLK_HDMIPHY>, +- <&clock CLK_MOUT_HDMI>; +- phy = <&hdmi_i2c_phy>; +- power-domains = <&pd_tv>; +- samsung,syscon-phandle = <&pmu_system_controller>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- hdmicec: cec@100b0000 { +- compatible = "samsung,s5p-cec"; +- reg = <0x100B0000 0x200>; +- interrupts = ; +- clocks = <&clock CLK_HDMI_CEC>; +- clock-names = "hdmicec"; +- samsung,syscon-phandle = <&pmu_system_controller>; +- hdmi-phandle = <&hdmi>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_cec>; +- status = "disabled"; +- }; +- +- mixer: mixer@12c10000 { +- compatible = "samsung,exynos4210-mixer"; +- interrupts = ; +- reg = <0x12C10000 0x2100>, <0x12c00000 0x300>; +- power-domains = <&pd_tv>; +- iommus = <&sysmmu_tv>; +- status = "disabled"; +- }; +- +- ppmu_dmc0: ppmu@106a0000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x106a0000 0x2000>; +- clocks = <&clock CLK_PPMUDMC0>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- ppmu_dmc1: ppmu@106b0000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x106b0000 0x2000>; +- clocks = <&clock CLK_PPMUDMC1>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- ppmu_cpu: ppmu@106c0000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x106c0000 0x2000>; +- clocks = <&clock CLK_PPMUCPU>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- ppmu_rightbus: ppmu@112a0000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x112a0000 0x2000>; +- clocks = <&clock CLK_PPMURIGHT>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- ppmu_leftbus: ppmu@116a0000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x116a0000 0x2000>; +- clocks = <&clock CLK_PPMULEFT>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- ppmu_camif: ppmu@11ac0000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x11ac0000 0x2000>; +- clocks = <&clock CLK_PPMUCAMIF>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- ppmu_lcd0: ppmu@11e40000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x11e40000 0x2000>; +- clocks = <&clock CLK_PPMULCD0>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- ppmu_fsys: ppmu@12630000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x12630000 0x2000>; +- status = "disabled"; +- }; +- +- ppmu_image: ppmu@12aa0000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x12aa0000 0x2000>; +- clocks = <&clock CLK_PPMUIMAGE>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- ppmu_tv: ppmu@12e40000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x12e40000 0x2000>; +- clocks = <&clock CLK_PPMUTV>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- ppmu_g3d: ppmu@13220000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x13220000 0x2000>; +- clocks = <&clock CLK_PPMUG3D>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- ppmu_mfc_left: ppmu@13660000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x13660000 0x2000>; +- clocks = <&clock CLK_PPMUMFC_L>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- ppmu_mfc_right: ppmu@13670000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x13670000 0x2000>; +- clocks = <&clock CLK_PPMUMFC_R>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- sysmmu_mfc_l: sysmmu@13620000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13620000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <5 5>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; +- power-domains = <&pd_mfc>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_mfc_r: sysmmu@13630000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13630000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <5 6>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; +- power-domains = <&pd_mfc>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_tv: sysmmu@12e20000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x12E20000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <5 4>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; +- power-domains = <&pd_tv>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc0: sysmmu@11a20000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x11A20000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <4 2>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>; +- power-domains = <&pd_cam>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc1: sysmmu@11a30000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x11A30000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <4 3>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>; +- power-domains = <&pd_cam>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc2: sysmmu@11a40000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x11A40000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <4 4>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>; +- power-domains = <&pd_cam>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc3: sysmmu@11a50000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x11A50000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <4 5>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>; +- power-domains = <&pd_cam>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_jpeg: sysmmu@11a60000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x11A60000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <4 6>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; +- power-domains = <&pd_cam>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_rotator: sysmmu@12a30000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x12A30000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <5 0>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_ROTATOR>, +- <&clock CLK_ROTATOR>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimd0: sysmmu@11e20000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x11E20000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <5 2>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>; +- power-domains = <&pd_lcd0>; +- #iommu-cells = <0>; +- }; +- +- sss: sss@10830000 { +- compatible = "samsung,exynos4210-secss"; +- reg = <0x10830000 0x300>; +- interrupts = ; +- clocks = <&clock CLK_SSS>; +- clock-names = "secss"; +- }; +- +- prng: rng@10830400 { +- compatible = "samsung,exynos4-rng"; +- reg = <0x10830400 0x200>; +- clocks = <&clock CLK_SSS>; +- clock-names = "secss"; +- }; +- }; +-}; +- +-#include "exynos-syscon-restart.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/exynos4210-i9100.dts b/scripts/dtc/include-prefixes/arm/exynos4210-i9100.dts +deleted file mode 100644 +index 5f5d9b135736..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4210-i9100.dts ++++ /dev/null +@@ -1,850 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos4210 based Galaxy S2 (GT-I9100 version) device tree +- * +- * Copyright (c) 2012 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * Copyright (c) 2020 Stenkin Evgeniy +- * Copyright (c) 2020 Paul Cercueil +- */ +- +-/dts-v1/; +-#include "exynos4210.dtsi" +-#include "exynos4412-ppmu-common.dtsi" +- +-#include +-#include +- +-/ { +- model = "Samsung Galaxy S2 (GT-I9100)"; +- compatible = "samsung,i9100", "samsung,exynos4210", "samsung,exynos4"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x40000000>; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- vemmc_reg: regulator-0 { +- compatible = "regulator-fixed"; +- regulator-name = "VMEM_VDD_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- tsp_reg: regulator-1 { +- compatible = "regulator-fixed"; +- regulator-name = "TSP_FIXED_VOLTAGES"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpl0 3 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <70000>; +- enable-active-high; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- cam_af_28v_reg: regulator-2 { +- compatible = "regulator-fixed"; +- regulator-name = "8M_AF_2.8V_EN"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpk1 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- cam_io_en_reg: regulator-3 { +- compatible = "regulator-fixed"; +- regulator-name = "CAM_IO_EN"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpe2 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- cam_io_12v_reg: regulator-4 { +- compatible = "regulator-fixed"; +- regulator-name = "8M_1.2V_EN"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- gpio = <&gpe2 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vt_core_15v_reg: regulator-5 { +- compatible = "regulator-fixed"; +- regulator-name = "VT_CORE_1.5V"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- gpio = <&gpe2 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- vol-down { +- gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "volume down"; +- debounce-interval = <10>; +- }; +- +- vol-up { +- gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "volume up"; +- debounce-interval = <10>; +- }; +- +- power { +- gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "power"; +- debounce-interval = <10>; +- wakeup-source; +- }; +- +- ok { +- gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "ok"; +- debounce-interval = <10>; +- }; +- }; +- +- wlan_pwrseq: sdhci3-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpl1 2 GPIO_ACTIVE_LOW>; +- }; +- +- i2c_max17042_fuel: i2c-gpio-0 { +- compatible = "i2c-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- sda-gpios = <&gpy4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpy4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <5>; +- +- battery@36 { +- compatible = "maxim,max17042"; +- +- interrupt-parent = <&gpx2>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- +- pinctrl-0 = <&max17042_fuel_irq>; +- pinctrl-names = "default"; +- +- reg = <0x36>; +- maxim,over-heat-temp = <700>; +- maxim,over-volt = <4500>; +- }; +- }; +- +- i2c_s5k5baf: i2c-gpio-1 { +- compatible = "i2c-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- sda-gpios = <&gpc1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpc1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; +- +- image-sensor@2d { +- compatible = "samsung,s5k5baf"; +- reg = <0x2d>; +- vdda-supply = <&cam_io_en_reg>; +- vddreg-supply = <&vt_core_15v_reg>; +- vddio-supply = <&vtcam_reg>; +- clocks = <&camera 0>; +- clock-names = "mclk"; +- stbyn-gpios = <&gpl2 0 GPIO_ACTIVE_LOW>; +- rstn-gpios = <&gpl2 1 GPIO_ACTIVE_LOW>; +- clock-frequency = <24000000>; +- +- port { +- s5k5bafx_ep: endpoint { +- remote-endpoint = <&csis1_ep>; +- data-lanes = <1>; +- }; +- }; +- }; +- }; +- +- spi-3 { +- compatible = "spi-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- num-chipselects = <1>; +- cs-gpios = <&gpy4 3 GPIO_ACTIVE_LOW>; +- sck-gpios = <&gpy3 1 GPIO_ACTIVE_HIGH>; +- mosi-gpios = <&gpy3 3 GPIO_ACTIVE_HIGH>; +- +- lcd@0 { +- compatible = "samsung,ld9040"; +- reg = <0>; +- +- spi-max-frequency = <1200000>; +- +- vdd3-supply = <&vmipi_reg>; +- vci-supply = <&vcclcd_reg>; +- +- reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; +- power-on-delay = <10>; +- reset-delay = <10>; +- +- panel-width-mm = <90>; +- panel-height-mm = <154>; +- +- display-timings { +- timing { +- clock-frequency = <23492370>; +- hactive = <480>; +- vactive = <800>; +- hback-porch = <16>; +- hfront-porch = <16>; +- vback-porch = <2>; +- vfront-porch = <28>; +- hsync-len = <2>; +- vsync-len = <1>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <0>; +- pixelclk-active = <0>; +- }; +- }; +- +- port { +- lcd_ep: endpoint { +- remote-endpoint = <&fimd_dpi_ep>; +- }; +- }; +- }; +- }; +- +- fixed-rate-clocks { +- xxti { +- compatible = "samsung,clock-xxti"; +- clock-frequency = <0>; +- }; +- +- xusbxti { +- compatible = "samsung,clock-xusbxti"; +- clock-frequency = <24000000>; +- }; +- +- pmic_ap_clk: pmic-ap-clk { +- /* Workaround for missing clock on max8997 PMIC */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- }; +-}; +- +-&camera { +- pinctrl-0 = <&cam_port_a_clk_active>; +- pinctrl-names = "default"; +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_CAM0>, <&clock CLK_MOUT_CAM1>; +- assigned-clock-parents = <&clock CLK_XUSBXTI>, <&clock CLK_XUSBXTI>; +-}; +- +-&csis_1 { +- status = "okay"; +- vddcore-supply = <&vusb_reg>; +- vddio-supply = <&vmipi_reg>; +- clock-frequency = <160000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@4 { +- reg = <4>; +- csis1_ep: endpoint { +- remote-endpoint = <&s5k5bafx_ep>; +- data-lanes = <1>; +- samsung,csis-hs-settle = <6>; +- }; +- }; +-}; +- +-&cpu0 { +- cpu0-supply = <&varm_breg>; +-}; +- +-&cpu_thermal { +- cooling-maps { +- map0 { +- /* Corresponds to 800MHz */ +- cooling-device = <&cpu0 2 2>; +- }; +- map1 { +- /* Corresponds to 200MHz */ +- cooling-device = <&cpu0 4 4>; +- }; +- }; +-}; +- +-&ehci { +- status = "okay"; +- +- phys = <&exynos_usbphy 1>; +- phy-names = "host"; +-}; +- +-&exynos_usbphy { +- status = "okay"; +- +- vbus-supply = <&safe1_sreg>; +-}; +- +-&fimc_0 { +- status = "okay"; +- +- assigned-clocks = <&clock CLK_MOUT_FIMC0>, <&clock CLK_SCLK_FIMC0>; +- assigned-clock-parents = <&clock CLK_SCLK_MPLL>; +- assigned-clock-rates = <0>, <160000000>; +-}; +- +-&fimc_1 { +- /* Back camera not implemented */ +- status = "disabled"; +- +- assigned-clocks = <&clock CLK_MOUT_FIMC1>, <&clock CLK_SCLK_FIMC1>; +- assigned-clock-parents = <&clock CLK_SCLK_MPLL>; +- assigned-clock-rates = <0>, <160000000>; +-}; +- +-&fimc_2 { +- status = "okay"; +- +- assigned-clocks = <&clock CLK_MOUT_FIMC2>, <&clock CLK_SCLK_FIMC2>; +- assigned-clock-parents = <&clock CLK_SCLK_MPLL>; +- assigned-clock-rates = <0>, <160000000>; +-}; +- +-&fimc_3 { +- /* Back camera not implemented */ +- status = "disabled"; +- +- assigned-clocks = <&clock CLK_MOUT_FIMC3>, <&clock CLK_SCLK_FIMC3>; +- assigned-clock-parents = <&clock CLK_SCLK_MPLL>; +- assigned-clock-rates = <0>, <160000000>; +-}; +- +-&fimd { +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- samsung,invert-vden; +- samsung,invert-vclk; +- +- pinctrl-0 = <&lcd_clk>, <&lcd_data24>; +- pinctrl-names = "default"; +- +- port@3 { +- reg = <3>; +- +- fimd_dpi_ep: endpoint { +- remote-endpoint = <&lcd_ep>; +- }; +- }; +-}; +- +-&gpu { +- status = "okay"; +- +- mali-supply = <&vg3d_breg>; +-}; +- +-&hsotg { +- status = "okay"; +- +- dr_mode = "otg"; +- vusb_d-supply = <&vusb_reg>; +- vusb_a-supply = <&vusbdac_reg>; +-}; +- +-&i2c_3 { +- status = "okay"; +- +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <100000>; +- +- pinctrl-0 = <&i2c3_bus>; +- pinctrl-names = "default"; +- +- touchscreen@4a { +- compatible = "atmel,maxtouch"; +- reg = <0x4a>; +- +- interrupt-parent = <&gpx0>; +- interrupts = <4 IRQ_TYPE_EDGE_FALLING>; +- }; +-}; +- +-&i2c_5 { +- status = "okay"; +- +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <100000>; +- +- pinctrl-0 = <&i2c5_bus>; +- pinctrl-names = "default"; +- +- pmic@66 { +- compatible = "maxim,max8997-pmic"; +- reg = <0x66>; +- +- interrupts-extended = <&gpx0 7 IRQ_TYPE_NONE>, +- <&gpx2 3 IRQ_TYPE_EDGE_FALLING>; +- +- max8997,pmic-buck1-uses-gpio-dvs; +- max8997,pmic-buck2-uses-gpio-dvs; +- max8997,pmic-buck5-uses-gpio-dvs; +- +- max8997,pmic-ignore-gpiodvs-side-effect; +- max8997,pmic-buck125-default-dvs-idx = <0>; +- +- max8997,pmic-buck125-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>, +- <&gpx0 6 GPIO_ACTIVE_HIGH>, +- <&gpl0 0 GPIO_ACTIVE_HIGH>; +- +- max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, +- <1250000>, <1200000>, +- <1150000>, <1100000>, +- <1000000>, <950000>; +- +- max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>, +- <950000>, <900000>, +- <1100000>, <1000000>, +- <950000>, <900000>; +- +- max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>, +- <1200000>, <1200000>, +- <1200000>, <1200000>, +- <1200000>, <1200000>; +- +- pinctrl-0 = <&max8997_irq>, <&otg_gp>, <&usb_sel>; +- pinctrl-names = "default"; +- +- charger-supply = <&charger_reg>; +- +- regulators { +- vadc_reg: LDO1 { +- regulator-name = "VADC_3.3V_C210"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- +- }; +- valive_reg: LDO2 { +- regulator-name = "VALIVE_1.1V_C210"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- +- }; +- +- vusb_reg: LDO3 { +- regulator-name = "VUSB_1.1V_C210"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- vmipi_reg: LDO4 { +- regulator-name = "VMIPI_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vhsic_reg: LDO5 { +- regulator-name = "VHSIC_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vpda_reg: LDO6 { +- regulator-name = "VCC_1.8V_PDA"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcam_reg: LDO7 { +- regulator-name = "CAM_ISP_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vusbdac_reg: LDO8 { +- regulator-name = "VUSB+VDAC_3.3V_C210"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vccpda_reg: LDO9 { +- regulator-name = "VCC_2.8V_PDA"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- vtouch_reg: LDO11 { +- regulator-name = "TOUCH_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- vpll_reg: LDO10 { +- regulator-name = "VPLL_1.1V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- vtcam_reg: LDO12 { +- regulator-name = "VT_CAM_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vcclcd_reg: LDO13 { +- regulator-name = "VCC_3.0V_LCD"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- vmotor_reg: LDO14 { +- regulator-name = "VCC_2.8V_MOTOR"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- vled_reg: LDO15 { +- regulator-name = "LED_A_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- camsensor_reg: LDO16 { +- regulator-name = "CAM_SENSOR_IO_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vtf_reg: LDO17 { +- regulator-name = "VTF_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- vtouchled_reg: LDO18 { +- regulator-name = "TOUCH_LED_3.3V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vddq_reg: LDO21 { +- regulator-name = "VDDQ_M1M2_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- varm_breg: BUCK1 { +- regulator-name = "VARM_1.2V_C210"; +- regulator-min-microvolt = <65000>; +- regulator-max-microvolt = <2225000>; +- regulator-always-on; +- }; +- +- vint_breg: BUCK2 { +- regulator-name = "VINT_1.1V_C210"; +- regulator-min-microvolt = <65000>; +- regulator-max-microvolt = <2225000>; +- regulator-always-on; +- }; +- +- vg3d_breg: BUCK3 { +- regulator-name = "G3D_1.1V"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1200000>; +- regulator-microvolt-offset = <50000>; +- regulator-always-on; +- }; +- +- camisp_breg: BUCK4 { +- regulator-name = "CAM_ISP_CORE_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- vmem_breg: BUCK5 { +- regulator-name = "VMEM_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vccsub_breg: BUCK7 { +- regulator-name = "VCC_SUB_2.0V"; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- regulator-always-on; +- }; +- +- safe1_sreg: ESAFEOUT1 { +- regulator-name = "SAFEOUT1"; +- }; +- +- safe2_sreg: ESAFEOUT2 { +- regulator-name = "SAFEOUT2"; +- regulator-boot-on; +- }; +- +- EN32KHZ_AP { +- regulator-name = "EN32KHZ_AP"; +- regulator-always-on; +- }; +- +- EN32KHZ_CP { +- regulator-name = "EN32KHZ_CP"; +- regulator-always-on; +- }; +- +- charger_reg: CHARGER { +- regulator-name = "CHARGER"; +- regulator-min-microamp = <200000>; +- regulator-max-microamp = <950000>; +- }; +- +- chargercv_reg: CHARGER_CV { +- regulator-name = "CHARGER_CV"; +- regulator-min-microvolt = <4200000>; +- regulator-max-microvolt = <4200000>; +- regulator-always-on; +- }; +- +- CHARGER_TOPOFF { +- regulator-name = "CHARGER_TOPOFF"; +- regulator-min-microamp = <200000>; +- regulator-max-microamp = <200000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c_7 { +- status = "okay"; +- +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <400000>; +- +- pinctrl-0 = <&i2c7_bus>; +- pinctrl-names = "default"; +- +- magnetometer@c { +- compatible = "asahi-kasei,ak8975"; +- reg = <0x0c>; +- +- gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&pinctrl_0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sleep0>; +- +- sleep0: sleep-states { +- gpa0-0 { +- samsung,pins = "gpa0-0"; +- samsung,pin-con-pdn = ; +- samsung,pin-pud-pdn = ; +- }; +- +- gpa0-1 { +- samsung,pins = "gpa0-1"; +- samsung,pin-con-pdn = ; +- samsung,pin-pud-pdn = ; +- }; +- +- gpa0-2 { +- samsung,pins = "gpa0-2"; +- samsung,pin-con-pdn = ; +- samsung,pin-pud-pdn = ; +- }; +- +- gpa0-3 { +- samsung,pins = "gpa0-3"; +- samsung,pin-con-pdn = ; +- samsung,pin-pud-pdn = ; +- }; +- }; +-}; +- +-&pinctrl_1 { +- mhl_int: mhl-int { +- samsung,pins = "gpf3-5"; +- samsung,pin-pud = ; +- }; +- +- i2c_mhl_bus: i2c-mhl-bus { +- samsung,pins = "gpf0-4", "gpf0-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- usb_sel: usb-sel { +- samsung,pins = "gpl0-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- samsung,pin-val = <0>; +- }; +- +- bt_en: bt-en { +- samsung,pins = "gpl0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- samsung,pin-val = <0>; +- }; +- +- bt_res: bt-res { +- samsung,pins = "gpl1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- samsung,pin-val = <0>; +- }; +- +- otg_gp: otg-gp { +- samsung,pins = "gpx3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- samsung,pin-val = <0>; +- }; +- +- mag_mhl_gpio: mag-mhl { +- samsung,pins = "gpd0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- max8997_irq: max8997-irq { +- samsung,pins = "gpx0-7"; +- samsung,pin-pud = ; +- }; +- +- max17042_fuel_irq: max17042-fuel-irq { +- samsung,pins = "gpx2-3"; +- samsung,pin-pud = ; +- }; +- +- tsp224_irq: tsp224-irq { +- samsung,pins = "gpx0-4"; +- samsung,pin-pud = ; +- }; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&sdhci_0 { +- status = "okay"; +- +- bus-width = <8>; +- non-removable; +- vmmc-supply = <&vemmc_reg>; +- +- pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_bus8>; +- pinctrl-names = "default"; +-}; +- +-&sdhci_2 { +- status = "okay"; +- +- bus-width = <4>; +- cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; +- vmmc-supply = <&vtf_reg>; +- +- pinctrl-0 = <&sd2_clk>, <&sd2_cmd>, <&sd2_bus4>; +- pinctrl-names = "default"; +-}; +- +-&sdhci_3 { +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- non-removable; +- bus-width = <4>; +- mmc-pwrseq = <&wlan_pwrseq>; +- vmmc-supply = <&vtf_reg>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; +- +- brcmf: wifi@1 { +- compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; +- reg = <1>; +- +- interrupt-parent = <&gpx2>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "host-wake"; +- }; +-}; +- +-&serial_0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_en>, <&bt_res>, <&uart0_data>, <&uart0_fctl>; +- +- bluetooth { +- compatible = "brcm,bcm4330-bt"; +- +- shutdown-gpios = <&gpl0 4 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&gpl1 0 GPIO_ACTIVE_LOW>; +- device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&serial_1 { +- status = "okay"; +-}; +- +-&serial_2 { +- status = "okay"; +-}; +- +-&serial_3 { +- status = "okay"; +-}; +- +-&tmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4210-origen.dts b/scripts/dtc/include-prefixes/arm/exynos4210-origen.dts +deleted file mode 100644 +index 1c5394152561..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4210-origen.dts ++++ /dev/null +@@ -1,365 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos4210 based Origen board device tree source +- * +- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * Copyright (c) 2010-2011 Linaro Ltd. +- * www.linaro.org +- * +- * Device tree source file for Insignal's Origen board which is based on +- * Samsung's Exynos4210 SoC. +- */ +- +-/dts-v1/; +-#include "exynos4210.dtsi" +-#include +-#include +-#include "exynos-mfc-reserved-memory.dtsi" +- +-/ { +- model = "Insignal Origen evaluation board based on Exynos4210"; +- compatible = "insignal,origen", "samsung,exynos4210", "samsung,exynos4"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x10000000 +- 0x50000000 0x10000000 +- 0x60000000 0x10000000 +- 0x70000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; +- stdout-path = "serial2:115200n8"; +- }; +- +- mmc_reg: voltage-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "VMEM_VDD_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- up { +- label = "Up"; +- gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- down { +- label = "Down"; +- gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- back { +- label = "Back"; +- gpios = <&gpx1 7 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- home { +- label = "Home"; +- gpios = <&gpx1 6 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- menu { +- label = "Menu"; +- gpios = <&gpx1 5 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- status { +- gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- fixed-rate-clocks { +- xxti { +- compatible = "samsung,clock-xxti"; +- clock-frequency = <0>; +- }; +- +- xusbxti { +- compatible = "samsung,clock-xusbxti"; +- clock-frequency = <24000000>; +- }; +- +- pmic_ap_clk: pmic-ap-clk { +- /* Workaround for missing clock on max8997 PMIC */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- }; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing { +- clock-frequency = <47500000>; +- hactive = <1024>; +- vactive = <600>; +- hfront-porch = <64>; +- hback-porch = <16>; +- hsync-len = <48>; +- vback-porch = <64>; +- vfront-porch = <16>; +- vsync-len = <3>; +- }; +- }; +-}; +- +-&cpu0 { +- cpu0-supply = <&buck1_reg>; +-}; +- +-&cpu_thermal { +- cooling-maps { +- map0 { +- /* Corresponds to 800MHz */ +- cooling-device = <&cpu0 2 2>; +- }; +- map1 { +- /* Corresponds to 200MHz */ +- cooling-device = <&cpu0 4 4>; +- }; +- }; +-}; +- +-&exynos_usbphy { +- status = "okay"; +-}; +- +-&fimd { +- pinctrl-0 = <&lcd_en &lcd_clk &lcd_data24 &pwm0_out>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&buck3_reg>; +- status = "okay"; +-}; +- +-&hsotg { +- vusb_d-supply = <&ldo3_reg>; +- vusb_a-supply = <&ldo8_reg>; +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&i2c_0 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <20000>; +- pinctrl-0 = <&i2c0_bus>; +- pinctrl-names = "default"; +- +- pmic@66 { +- compatible = "maxim,max8997-pmic"; +- reg = <0x66>; +- interrupt-parent = <&gpx0>; +- interrupts = <4 IRQ_TYPE_NONE>, <3 IRQ_TYPE_NONE>; +- pinctrl-names = "default"; +- pinctrl-0 = <&max8997_irq>; +- +- max8997,pmic-buck1-dvs-voltage = <1350000>; +- max8997,pmic-buck2-dvs-voltage = <1100000>; +- max8997,pmic-buck5-dvs-voltage = <1200000>; +- +- regulators { +- ldo1_reg: LDO1 { +- regulator-name = "VDD_ABB_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "VDD_ALIVE_1.1V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "VMIPI_1.1V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "VDD_RTC_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "VMIPI_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "VDD_AUD_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "VADC_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "DVDD_SWB_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "VDD_PLL_1.1V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "VDD_AUD_3V"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "AVDD18_SWB_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "VDD_SWB_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo21_reg: LDO21 { +- regulator-name = "VDD_MIF_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "VDD_ARM_1.2V"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "VDD_INT_1.1V"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "VDD_G3D_1.1V"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "VDDQ_M1M2_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- buck7_reg: BUCK7 { +- regulator-name = "VDD_LCD_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- EN32KHZ_AP { +- regulator-name = "EN32KHZ_AP"; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&pinctrl_1 { +- max8997_irq: max8997-irq { +- samsung,pins = "gpx0-3", "gpx0-4"; +- samsung,pin-pud = ; +- }; +-}; +- +-&sdhci_0 { +- bus-width = <4>; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_cd>; +- pinctrl-names = "default"; +- vmmc-supply = <&mmc_reg>; +- status = "okay"; +-}; +- +-&sdhci_2 { +- bus-width = <4>; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; +- pinctrl-names = "default"; +- vmmc-supply = <&mmc_reg>; +- status = "okay"; +-}; +- +-&serial_0 { +- status = "okay"; +-}; +- +-&serial_1 { +- status = "okay"; +-}; +- +-&serial_2 { +- status = "okay"; +-}; +- +-&serial_3 { +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&tmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4210-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/exynos4210-pinctrl.dtsi +deleted file mode 100644 +index 520c5934a8d4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4210-pinctrl.dtsi ++++ /dev/null +@@ -1,863 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source +- * +- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * Copyright (c) 2011-2012 Linaro Ltd. +- * www.linaro.org +- * +- * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device +- * tree nodes are listed in this file. +- */ +- +-#include +- +-&pinctrl_0 { +- gpa0: gpa0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpa1: gpa1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb: gpb { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc0: gpc0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc1: gpc1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd0: gpd0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd1: gpd1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpe0: gpe0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpe1: gpe1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpe2: gpe2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpe3: gpe3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpe4: gpe4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf0: gpf0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf1: gpf1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf2: gpf2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf3: gpf3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- uart0_data: uart0-data { +- samsung,pins = "gpa0-0", "gpa0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart0_fctl: uart0-fctl { +- samsung,pins = "gpa0-2", "gpa0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart1_data: uart1-data { +- samsung,pins = "gpa0-4", "gpa0-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart1_fctl: uart1-fctl { +- samsung,pins = "gpa0-6", "gpa0-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c2_bus: i2c2-bus { +- samsung,pins = "gpa0-6", "gpa0-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart2_data: uart2-data { +- samsung,pins = "gpa1-0", "gpa1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart2_fctl: uart2-fctl { +- samsung,pins = "gpa1-2", "gpa1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart_audio_a: uart-audio-a { +- samsung,pins = "gpa1-0", "gpa1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c3_bus: i2c3-bus { +- samsung,pins = "gpa1-2", "gpa1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart3_data: uart3-data { +- samsung,pins = "gpa1-4", "gpa1-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart_audio_b: uart-audio-b { +- samsung,pins = "gpa1-4", "gpa1-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi0_bus: spi0-bus { +- samsung,pins = "gpb-0", "gpb-2", "gpb-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c4_bus: i2c4-bus { +- samsung,pins = "gpb-2", "gpb-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi1_bus: spi1-bus { +- samsung,pins = "gpb-4", "gpb-6", "gpb-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c5_bus: i2c5-bus { +- samsung,pins = "gpb-6", "gpb-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2s1_bus: i2s1-bus { +- samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", +- "gpc0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pcm1_bus: pcm1-bus { +- samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", +- "gpc0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- ac97_bus: ac97-bus { +- samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", +- "gpc0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2s2_bus: i2s2-bus { +- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", +- "gpc1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pcm2_bus: pcm2-bus { +- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", +- "gpc1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spdif_bus: spdif-bus { +- samsung,pins = "gpc1-0", "gpc1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c6_bus: i2c6-bus { +- samsung,pins = "gpc1-3", "gpc1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi2_bus: spi2-bus { +- samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c7_bus: i2c7-bus { +- samsung,pins = "gpd0-2", "gpd0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c0_bus: i2c0-bus { +- samsung,pins = "gpd1-0", "gpd1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c1_bus: i2c1-bus { +- samsung,pins = "gpd1-2", "gpd1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm0_out: pwm0-out { +- samsung,pins = "gpd0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm1_out: pwm1-out { +- samsung,pins = "gpd0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm2_out: pwm2-out { +- samsung,pins = "gpd0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm3_out: pwm3-out { +- samsung,pins = "gpd0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lcd_ctrl: lcd-ctrl { +- samsung,pins = "gpd0-0", "gpd0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lcd_sync: lcd-sync { +- samsung,pins = "gpf0-0", "gpf0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lcd_en: lcd-en { +- samsung,pins = "gpe3-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lcd_clk: lcd-clk { +- samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lcd_data16: lcd-data-width16 { +- samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", +- "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", +- "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", +- "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lcd_data18: lcd-data-width18 { +- samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", +- "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", +- "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", +- "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", +- "gpf3-2", "gpf3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lcd_data24: lcd-data-width24 { +- samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", +- "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", +- "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", +- "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", +- "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", +- "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_1 { +- gpj0: gpj0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpj1: gpj1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpk0: gpk0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpk1: gpk1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpk2: gpk2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpk3: gpk3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpl0: gpl0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpl1: gpl1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpl2: gpl2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpy0: gpy0 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy1: gpy1 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy2: gpy2 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy3: gpy3 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy4: gpy4 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy5: gpy5 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy6: gpy6 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpx0: gpx0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- #interrupt-cells = <2>; +- }; +- +- gpx1: gpx1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- #interrupt-cells = <2>; +- }; +- +- gpx2: gpx2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpx3: gpx3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- sd0_clk: sd0-clk { +- samsung,pins = "gpk0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_cmd: sd0-cmd { +- samsung,pins = "gpk0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_cd: sd0-cd { +- samsung,pins = "gpk0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus1: sd0-bus-width1 { +- samsung,pins = "gpk0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus4: sd0-bus-width4 { +- samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus8: sd0-bus-width8 { +- samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd4_clk: sd4-clk { +- samsung,pins = "gpk0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd4_cmd: sd4-cmd { +- samsung,pins = "gpk0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd4_cd: sd4-cd { +- samsung,pins = "gpk0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd4_bus1: sd4-bus-width1 { +- samsung,pins = "gpk0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd4_bus4: sd4-bus-width4 { +- samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd4_bus8: sd4-bus-width8 { +- samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_clk: sd1-clk { +- samsung,pins = "gpk1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_cmd: sd1-cmd { +- samsung,pins = "gpk1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_cd: sd1-cd { +- samsung,pins = "gpk1-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus1: sd1-bus-width1 { +- samsung,pins = "gpk1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus4: sd1-bus-width4 { +- samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_clk: sd2-clk { +- samsung,pins = "gpk2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cmd: sd2-cmd { +- samsung,pins = "gpk2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cd: sd2-cd { +- samsung,pins = "gpk2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus1: sd2-bus-width1 { +- samsung,pins = "gpk2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus4: sd2-bus-width4 { +- samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus8: sd2-bus-width8 { +- samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_clk: sd3-clk { +- samsung,pins = "gpk3-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_cmd: sd3-cmd { +- samsung,pins = "gpk3-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_cd: sd3-cd { +- samsung,pins = "gpk3-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_bus1: sd3-bus-width1 { +- samsung,pins = "gpk3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_bus4: sd3-bus-width4 { +- samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- eint0: ext-int0 { +- samsung,pins = "gpx0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- eint8: ext-int8 { +- samsung,pins = "gpx1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- eint15: ext-int15 { +- samsung,pins = "gpx1-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- eint16: ext-int16 { +- samsung,pins = "gpx2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- eint31: ext-int31 { +- samsung,pins = "gpx3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_port_a_io: cam-port-a-io { +- samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", +- "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", +- "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_port_a_clk_active: cam-port-a-clk-active { +- samsung,pins = "gpj1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_port_a_clk_idle: cam-port-a-clk-idle { +- samsung,pins = "gpj1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hdmi_cec: hdmi-cec { +- samsung,pins = "gpx3-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_2 { +- gpz: gpz { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- i2s0_bus: i2s0-bus { +- samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", +- "gpz-4", "gpz-5", "gpz-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pcm0_bus: pcm0-bus { +- samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", +- "gpz-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4210-smdkv310.dts b/scripts/dtc/include-prefixes/arm/exynos4210-smdkv310.dts +deleted file mode 100644 +index d5797a67bf48..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4210-smdkv310.dts ++++ /dev/null +@@ -1,225 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos4210 based SMDKV310 board device tree source +- * +- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * Copyright (c) 2010-2011 Linaro Ltd. +- * www.linaro.org +- * +- * Device tree source file for Samsung's SMDKV310 board which is based on +- * Samsung's Exynos4210 SoC. +- */ +- +-/dts-v1/; +-#include "exynos4210.dtsi" +-#include +-#include "exynos-mfc-reserved-memory.dtsi" +- +-/ { +- model = "Samsung smdkv310 evaluation board based on Exynos4210"; +- compatible = "samsung,smdkv310", "samsung,exynos4210", "samsung,exynos4"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x80000000>; +- }; +- +- chosen { +- bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; +- stdout-path = "serial1:115200n8"; +- }; +- +- fixed-rate-clocks { +- xxti { +- compatible = "samsung,clock-xxti"; +- clock-frequency = <12000000>; +- }; +- +- xusbxti { +- compatible = "samsung,clock-xusbxti"; +- clock-frequency = <24000000>; +- }; +- +- pmic_ap_clk: pmic-ap-clk { +- /* Workaround for missing clock on PMIC */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- }; +-}; +- +-&cpu_thermal { +- cooling-maps { +- map0 { +- /* Corresponds to 800MHz */ +- cooling-device = <&cpu0 2 2>; +- }; +- map1 { +- /* Corresponds to 200MHz */ +- cooling-device = <&cpu0 4 4>; +- }; +- }; +-}; +- +-&i2c_0 { +- #address-cells = <1>; +- #size-cells = <0>; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <100000>; +- status = "okay"; +- +- eeprom@50 { +- compatible = "samsung,24ad0xd1"; +- reg = <0x50>; +- }; +- +- eeprom@52 { +- compatible = "samsung,24ad0xd1"; +- reg = <0x52>; +- }; +-}; +- +-&keypad { +- samsung,keypad-num-rows = <2>; +- samsung,keypad-num-columns = <8>; +- linux,keypad-no-autorepeat; +- wakeup-source; +- pinctrl-names = "default"; +- pinctrl-0 = <&keypad_rows &keypad_cols>; +- status = "okay"; +- +- key-1 { +- keypad,row = <0>; +- keypad,column = <3>; +- linux,code = <2>; +- }; +- +- key-2 { +- keypad,row = <0>; +- keypad,column = <4>; +- linux,code = <3>; +- }; +- +- key-3 { +- keypad,row = <0>; +- keypad,column = <5>; +- linux,code = <4>; +- }; +- +- key-4 { +- keypad,row = <0>; +- keypad,column = <6>; +- linux,code = <5>; +- }; +- +- key-5 { +- keypad,row = <0>; +- keypad,column = <7>; +- linux,code = <6>; +- }; +- +- key-a { +- keypad,row = <1>; +- keypad,column = <3>; +- linux,code = <30>; +- }; +- +- key-b { +- keypad,row = <1>; +- keypad,column = <4>; +- linux,code = <48>; +- }; +- +- key-c { +- keypad,row = <1>; +- keypad,column = <5>; +- linux,code = <46>; +- }; +- +- key-d { +- keypad,row = <1>; +- keypad,column = <6>; +- linux,code = <32>; +- }; +- +- key-e { +- keypad,row = <1>; +- keypad,column = <7>; +- linux,code = <18>; +- }; +-}; +- +-&pinctrl_1 { +- keypad_rows: keypad-rows { +- samsung,pins = "gpx2-0", "gpx2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- keypad_cols: keypad-cols { +- samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", +- "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&rtc { +- clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&sdhci_2 { +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; +- status = "okay"; +-}; +- +-&serial_0 { +- status = "okay"; +-}; +- +-&serial_1 { +- status = "okay"; +-}; +- +-&serial_2 { +- status = "okay"; +-}; +- +-&serial_3 { +- status = "okay"; +-}; +- +-&spi_2 { +- cs-gpios = <&gpc1 2 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "w25x80"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- +- controller-data { +- samsung,spi-feedback-delay = <0>; +- }; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0x0 0x40000>; +- read-only; +- }; +- +- partition@40000 { +- label = "Kernel"; +- reg = <0x40000 0xc0000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4210-trats.dts b/scripts/dtc/include-prefixes/arm/exynos4210-trats.dts +deleted file mode 100644 +index 3eb8df319246..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4210-trats.dts ++++ /dev/null +@@ -1,562 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos4210 based Trats board device tree source +- * +- * Copyright (c) 2012 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Device tree source file for Samsung's Trats board which is based on +- * Samsung's Exynos4210 SoC. +- */ +- +-/dts-v1/; +-#include "exynos4210.dtsi" +-#include +- +-/ { +- model = "Samsung Trats based on Exynos4210"; +- compatible = "samsung,trats", "samsung,exynos4210", "samsung,exynos4"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x10000000 +- 0x50000000 0x10000000 +- 0x60000000 0x10000000 +- 0x70000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; +- stdout-path = "serial2:115200n8"; +- }; +- +- vemmc_reg: regulator-0 { +- compatible = "regulator-fixed"; +- regulator-name = "VMEM_VDD_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- tsp_reg: regulator-1 { +- compatible = "regulator-fixed"; +- regulator-name = "TSP_FIXED_VOLTAGES"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpl0 3 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- cam_af_28v_reg: regulator-2 { +- compatible = "regulator-fixed"; +- regulator-name = "8M_AF_2.8V_EN"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpk1 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- cam_io_en_reg: regulator-3 { +- compatible = "regulator-fixed"; +- regulator-name = "CAM_IO_EN"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpe2 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- cam_io_12v_reg: regulator-4 { +- compatible = "regulator-fixed"; +- regulator-name = "8M_1.2V_EN"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- gpio = <&gpe2 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vt_core_15v_reg: regulator-5 { +- compatible = "regulator-fixed"; +- regulator-name = "VT_CORE_1.5V"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- gpio = <&gpe2 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- vol-down-key { +- gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; +- linux,code = <114>; +- label = "volume down"; +- debounce-interval = <10>; +- }; +- +- vol-up-key { +- gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; +- linux,code = <115>; +- label = "volume up"; +- debounce-interval = <10>; +- }; +- +- power-key { +- gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; +- linux,code = <116>; +- label = "power"; +- debounce-interval = <10>; +- wakeup-source; +- }; +- +- ok-key { +- gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; +- linux,code = <352>; +- label = "ok"; +- debounce-interval = <10>; +- }; +- }; +- +- wlan_pwrseq: sdhci3-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpl1 2 GPIO_ACTIVE_LOW>; +- }; +- +- fixed-rate-clocks { +- xxti { +- compatible = "samsung,clock-xxti"; +- clock-frequency = <0>; +- }; +- +- xusbxti { +- compatible = "samsung,clock-xusbxti"; +- clock-frequency = <24000000>; +- }; +- +- pmic_ap_clk: pmic-ap-clk { +- /* Workaround for missing clock on max8997 PMIC */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- }; +-}; +- +-&camera { +- pinctrl-names = "default"; +- pinctrl-0 = <>; +- status = "okay"; +-}; +- +-&cpu0 { +- cpu0-supply = <&varm_breg>; +-}; +- +-&cpu_thermal { +- cooling-maps { +- map0 { +- /* Corresponds to 800MHz at freq_table */ +- cooling-device = <&cpu0 2 2>, <&cpu1 2 2>; +- }; +- map1 { +- /* Corresponds to 200MHz at freq_table */ +- cooling-device = <&cpu0 4 4>, <&cpu1 4 4>; +- }; +- }; +-}; +- +-&dsi_0 { +- vddcore-supply = <&vusb_reg>; +- vddio-supply = <&vmipi_reg>; +- samsung,burst-clock-frequency = <500000000>; +- samsung,esc-clock-frequency = <20000000>; +- samsung,pll-clock-frequency = <24000000>; +- status = "okay"; +- +- panel@0 { +- reg = <0>; +- compatible = "samsung,s6e8aa0"; +- vdd3-supply = <&vcclcd_reg>; +- vci-supply = <&vlcd_reg>; +- reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; +- power-on-delay= <50>; +- reset-delay = <100>; +- init-delay = <100>; +- flip-horizontal; +- flip-vertical; +- panel-width-mm = <58>; +- panel-height-mm = <103>; +- +- display-timings { +- timing-0 { +- clock-frequency = <57153600>; +- hactive = <720>; +- vactive = <1280>; +- hfront-porch = <5>; +- hback-porch = <5>; +- hsync-len = <5>; +- vfront-porch = <13>; +- vback-porch = <1>; +- vsync-len = <2>; +- }; +- }; +- }; +-}; +- +-&exynos_usbphy { +- status = "okay"; +- vbus-supply = <&safe1_sreg>; +-}; +- +-&fimc_0 { +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_FIMC0>, +- <&clock CLK_SCLK_FIMC0>; +- assigned-clock-parents = <&clock CLK_SCLK_MPLL>; +- assigned-clock-rates = <0>, <160000000>; +-}; +- +-&fimc_1 { +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_FIMC1>, +- <&clock CLK_SCLK_FIMC1>; +- assigned-clock-parents = <&clock CLK_SCLK_MPLL>; +- assigned-clock-rates = <0>, <160000000>; +-}; +- +-&fimc_2 { +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_FIMC2>, +- <&clock CLK_SCLK_FIMC2>; +- assigned-clock-parents = <&clock CLK_SCLK_MPLL>; +- assigned-clock-rates = <0>, <160000000>; +-}; +- +-&fimc_3 { +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_FIMC3>, +- <&clock CLK_SCLK_FIMC3>; +- assigned-clock-parents = <&clock CLK_SCLK_MPLL>; +- assigned-clock-rates = <0>, <160000000>; +-}; +- +-&fimd { +- status = "okay"; +-}; +- +-&gpu { +- status = "okay"; +-}; +- +-&hsotg { +- vusb_d-supply = <&vusb_reg>; +- vusb_a-supply = <&vusbdac_reg>; +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&i2c_3 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <400000>; +- pinctrl-0 = <&i2c3_bus>; +- pinctrl-names = "default"; +- status = "okay"; +- +- touchscreen@48 { +- compatible = "melfas,mms114"; +- reg = <0x48>; +- interrupt-parent = <&gpx0>; +- interrupts = <4 IRQ_TYPE_EDGE_FALLING>; +- touchscreen-size-x = <720>; +- touchscreen-size-y = <1280>; +- avdd-supply = <&tsp_reg>; +- vdd-supply = <&tsp_reg>; +- }; +-}; +- +-&i2c_5 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <100000>; +- pinctrl-0 = <&i2c5_bus>; +- pinctrl-names = "default"; +- status = "okay"; +- +- pmic@66 { +- compatible = "maxim,max8997-pmic"; +- +- reg = <0x66>; +- interrupts-extended = <&gpx0 7 IRQ_TYPE_LEVEL_LOW>, +- <&gpx2 3 IRQ_TYPE_EDGE_FALLING>; +- +- max8997,pmic-buck1-uses-gpio-dvs; +- max8997,pmic-buck2-uses-gpio-dvs; +- max8997,pmic-buck5-uses-gpio-dvs; +- +- max8997,pmic-ignore-gpiodvs-side-effect; +- max8997,pmic-buck125-default-dvs-idx = <0>; +- +- max8997,pmic-buck125-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>, +- <&gpx0 6 GPIO_ACTIVE_HIGH>, +- <&gpl0 0 GPIO_ACTIVE_HIGH>; +- +- max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, +- <1250000>, <1200000>, +- <1150000>, <1100000>, +- <1000000>, <950000>; +- +- max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>, +- <950000>, <900000>, +- <1100000>, <1000000>, +- <950000>, <900000>; +- +- max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>, +- <1200000>, <1200000>, +- <1200000>, <1200000>, +- <1200000>, <1200000>; +- +- regulators { +- valive_reg: LDO2 { +- regulator-name = "VALIVE_1.1V_C210"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- vusb_reg: LDO3 { +- regulator-name = "VUSB_1.1V_C210"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- vmipi_reg: LDO4 { +- regulator-name = "VMIPI_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vpda_reg: LDO6 { +- regulator-name = "VCC_1.8V_PDA"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcam_reg: LDO7 { +- regulator-name = "CAM_ISP_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vusbdac_reg: LDO8 { +- regulator-name = "VUSB+VDAC_3.3V_C210"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vccpda_reg: LDO9 { +- regulator-name = "VCC_2.8V_PDA"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- vpll_reg: LDO10 { +- regulator-name = "VPLL_1.1V_C210"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- vtcam_reg: LDO12 { +- regulator-name = "VT_CAM_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vcclcd_reg: LDO13 { +- regulator-name = "VCC_3.3V_LCD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vlcd_reg: LDO15 { +- regulator-name = "VLCD_2.2V"; +- regulator-min-microvolt = <2200000>; +- regulator-max-microvolt = <2200000>; +- }; +- +- camsensor_reg: LDO16 { +- regulator-name = "CAM_SENSOR_IO_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- tflash_reg: LDO17 { +- regulator-name = "VTF_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- vddq_reg: LDO21 { +- regulator-name = "VDDQ_M1M2_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- varm_breg: BUCK1 { +- regulator-name = "VARM_1.2V_C210"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- }; +- +- vint_breg: BUCK2 { +- regulator-name = "VINT_1.1V_C210"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- camisp_breg: BUCK4 { +- regulator-name = "CAM_ISP_CORE_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- vmem_breg: BUCK5 { +- regulator-name = "VMEM_1.2V_C210"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vccsub_breg: BUCK7 { +- regulator-name = "VCC_SUB_2.0V"; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- regulator-always-on; +- }; +- +- safe1_sreg: ESAFEOUT1 { +- regulator-name = "SAFEOUT1"; +- }; +- +- safe2_sreg: ESAFEOUT2 { +- regulator-name = "SAFEOUT2"; +- regulator-boot-on; +- }; +- +- EN32KHZ_AP { +- regulator-name = "EN32KHZ_AP"; +- regulator-always-on; +- }; +- +- EN32KHZ_CP { +- regulator-name = "EN32KHZ_CP"; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&pinctrl_1 { +- bt_shutdown: bt-shutdown { +- samsung,pins = "gpl1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- bt_host_wakeup: bt-host-wakeup { +- samsung,pins = "gpx2-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- bt_device_wakeup: bt-device-wakeup { +- samsung,pins = "gpx3-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&sdhci_0 { +- bus-width = <8>; +- non-removable; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; +- pinctrl-names = "default"; +- vmmc-supply = <&vemmc_reg>; +- status = "okay"; +-}; +- +-&sdhci_2 { +- bus-width = <4>; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; +- pinctrl-names = "default"; +- vmmc-supply = <&tflash_reg>; +- cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&sdhci_3 { +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- non-removable; +- bus-width = <4>; +- mmc-pwrseq = <&wlan_pwrseq>; +- vmmc-supply = <&tflash_reg>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; +- +- brcmf: wifi@1 { +- compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; +- reg = <1>; +- +- interrupt-parent = <&gpx2>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "host-wake"; +- }; +-}; +- +-&serial_0 { +- status = "okay"; +- pinctrl-0 = <&uart0_data &uart0_fctl>; +- pinctrl-names = "default"; +- +- bluetooth { +- compatible = "brcm,bcm4330-bt"; +- pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; +- pinctrl-names = "default"; +- shutdown-gpios = <&gpl1 0 GPIO_ACTIVE_HIGH>; +- device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&serial_1 { +- status = "okay"; +-}; +- +-&serial_2 { +- status = "okay"; +-}; +- +-&serial_3 { +- status = "okay"; +-}; +- +-&tmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4210-universal_c210.dts b/scripts/dtc/include-prefixes/arm/exynos4210-universal_c210.dts +deleted file mode 100644 +index f052853244a4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4210-universal_c210.dts ++++ /dev/null +@@ -1,687 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos4210 based Universal C210 board device tree source +- * +- * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Device tree source file for Samsung's Universal C210 board which is based on +- * Samsung's Exynos4210 rev0 SoC. +- */ +- +-/dts-v1/; +-#include "exynos4210.dtsi" +-#include +- +-/ { +- model = "Samsung Universal C210 based on Exynos4210 rev0"; +- compatible = "samsung,universal_c210", "samsung,exynos4210", "samsung,exynos4"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x10000000 +- 0x50000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; +- stdout-path = "serial2:115200n8"; +- }; +- +- +- fixed-rate-clocks { +- xxti { +- compatible = "samsung,clock-xxti"; +- clock-frequency = <0>; +- }; +- +- xusbxti { +- compatible = "samsung,clock-xusbxti"; +- clock-frequency = <24000000>; +- }; +- +- pmic_ap_clk: pmic-ap-clk { +- /* Workaround for missing clock on PMIC */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- }; +- +- vemmc_reg: voltage-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "VMEM_VDD_2_8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpe1 3 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- wlan_pwrseq: sdhci3-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpe3 1 GPIO_ACTIVE_LOW>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- vol-up-key { +- gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; +- linux,code = <115>; +- label = "volume up"; +- debounce-interval = <1>; +- }; +- +- vol-down-key { +- gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; +- linux,code = <114>; +- label = "volume down"; +- debounce-interval = <1>; +- }; +- +- config-key { +- gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; +- linux,code = <171>; +- label = "config"; +- debounce-interval = <1>; +- wakeup-source; +- }; +- +- camera-key { +- gpios = <&gpx2 3 GPIO_ACTIVE_LOW>; +- linux,code = <212>; +- label = "camera"; +- debounce-interval = <1>; +- }; +- +- power-key { +- gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; +- linux,code = <116>; +- label = "power"; +- debounce-interval = <1>; +- wakeup-source; +- }; +- +- ok-key { +- gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; +- linux,code = <352>; +- label = "ok"; +- debounce-interval = <1>; +- }; +- }; +- +- tsp_reg: voltage-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "TSP_2_8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpe2 3 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- spi-3 { +- compatible = "spi-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- sck-gpios = <&gpy3 1 GPIO_ACTIVE_HIGH>; +- mosi-gpios = <&gpy3 3 GPIO_ACTIVE_HIGH>; +- num-chipselects = <1>; +- cs-gpios = <&gpy4 3 GPIO_ACTIVE_LOW>; +- +- lcd@0 { +- compatible = "samsung,ld9040"; +- reg = <0>; +- vdd3-supply = <&ldo7_reg>; +- vci-supply = <&ldo17_reg>; +- reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; +- spi-max-frequency = <1200000>; +- power-on-delay = <10>; +- reset-delay = <10>; +- panel-width-mm = <90>; +- panel-height-mm = <154>; +- display-timings { +- timing { +- clock-frequency = <23492370>; +- hactive = <480>; +- vactive = <800>; +- hback-porch = <16>; +- hfront-porch = <16>; +- vback-porch = <2>; +- vfront-porch = <28>; +- hsync-len = <2>; +- vsync-len = <1>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <0>; +- pixelclk-active = <0>; +- }; +- }; +- port { +- lcd_ep: endpoint { +- remote-endpoint = <&fimd_dpi_ep>; +- }; +- }; +- }; +- }; +- +- hdmi_en: voltage-regulator-hdmi-5v { +- compatible = "regulator-fixed"; +- regulator-name = "HDMI_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpe0 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- hdmi_ddc: i2c-ddc { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpe4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpe4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <100>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pinctrl-0 = <&i2c_ddc_bus>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +-}; +- +-&camera { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <>; +-}; +- +-&cpu0 { +- cpu0-supply = <&vdd_arm_reg>; +-}; +- +-&cpu_thermal { +- cooling-maps { +- map0 { +- /* Corresponds to 800MHz */ +- cooling-device = <&cpu0 2 2>; +- }; +- map1 { +- /* Corresponds to 200MHz */ +- cooling-device = <&cpu0 4 4>; +- }; +- }; +-}; +- +-&ehci { +- status = "okay"; +- phys = <&exynos_usbphy 1>; +- phy-names = "host"; +-}; +- +-&exynos_usbphy { +- status = "okay"; +- vbus-supply = <&safeout1_reg>; +-}; +- +-&fimc_0 { +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_FIMC0>, +- <&clock CLK_SCLK_FIMC0>; +- assigned-clock-parents = <&clock CLK_SCLK_MPLL>; +- assigned-clock-rates = <0>, <160000000>; +-}; +- +-&fimc_1 { +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_FIMC1>, +- <&clock CLK_SCLK_FIMC1>; +- assigned-clock-parents = <&clock CLK_SCLK_MPLL>; +- assigned-clock-rates = <0>, <160000000>; +-}; +- +-&fimc_2 { +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_FIMC2>, +- <&clock CLK_SCLK_FIMC2>; +- assigned-clock-parents = <&clock CLK_SCLK_MPLL>; +- assigned-clock-rates = <0>, <160000000>; +-}; +- +-&fimc_3 { +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_FIMC3>, +- <&clock CLK_SCLK_FIMC3>; +- assigned-clock-parents = <&clock CLK_SCLK_MPLL>; +- assigned-clock-rates = <0>, <160000000>; +-}; +- +-&fimd { +- pinctrl-0 = <&lcd_clk>, <&lcd_data24>; +- pinctrl-names = "default"; +- status = "okay"; +- samsung,invert-vden; +- samsung,invert-vclk; +- #address-cells = <1>; +- #size-cells = <0>; +- port@3 { +- reg = <3>; +- fimd_dpi_ep: endpoint { +- remote-endpoint = <&lcd_ep>; +- }; +- }; +-}; +- +-&gpu { +- mali-supply = <&buck2_reg>; +- status = "okay"; +-}; +- +-&hdmi { +- hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_hpd>; +- hdmi-en-supply = <&hdmi_en>; +- vdd-supply = <&ldo3_reg>; +- vdd_osc-supply = <&ldo4_reg>; +- vdd_pll-supply = <&ldo3_reg>; +- ddc = <&hdmi_ddc>; +- status = "okay"; +-}; +- +-&hsotg { +- vusb_d-supply = <&ldo3_reg>; +- vusb_a-supply = <&ldo8_reg>; +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&i2c_3 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <100000>; +- pinctrl-0 = <&i2c3_bus>; +- pinctrl-names = "default"; +- status = "okay"; +- +- tsp@4a { +- /* TBD: Atmel maXtouch touchscreen */ +- reg = <0x4a>; +- }; +-}; +- +-&i2c_5 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <100000>; +- pinctrl-0 = <&i2c5_bus>; +- pinctrl-names = "default"; +- status = "okay"; +- +- vdd_arm_reg: pmic@60 { +- compatible = "maxim,max8952"; +- reg = <0x60>; +- +- max8952,vid-gpios = <&gpx0 3 GPIO_ACTIVE_HIGH>, +- <&gpx0 4 GPIO_ACTIVE_HIGH>; +- max8952,default-mode = <0>; +- max8952,dvs-mode-microvolt = <1250000>, <1200000>, +- <1050000>, <950000>; +- max8952,sync-freq = <0>; +- max8952,ramp-speed = <0>; +- +- regulator-name = "VARM_1.2V_C210"; +- regulator-min-microvolt = <770000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- pmic@66 { +- compatible = "national,lp3974"; +- interrupts-extended = <&gpx0 7 0>, <&gpx2 7 0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&lp3974_irq>; +- reg = <0x66>; +- +- max8998,pmic-buck1-default-dvs-idx = <0>; +- max8998,pmic-buck1-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>, +- <&gpx0 6 GPIO_ACTIVE_HIGH>; +- max8998,pmic-buck1-dvs-voltage = <1100000>, <1000000>, +- <1100000>, <1000000>; +- +- max8998,pmic-buck2-default-dvs-idx = <0>; +- max8998,pmic-buck2-dvs-gpio = <&gpe2 0 GPIO_ACTIVE_HIGH>; +- max8998,pmic-buck2-dvs-voltage = <1200000>, <1100000>; +- +- regulators { +- ldo2_reg: LDO2 { +- regulator-name = "VALIVE_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "VUSB+MIPI_1.1V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "VADC_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "VTF_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "LDO6"; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "VLCD+VMIPI_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "VUSB+VDAC_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "VCC_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "VPLL_1.1V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "CAM_AF_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "PS_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "VHIC_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "CAM_I_HOST_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "CAM_S_DIG+FM33_CORE_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "CAM_S_ANA_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "VCC_3.0V_LCD"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "VINT_1.1V"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "VG3D_1.1V"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "VCC_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "VMEM_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ap32khz_reg: EN32KHz-AP { +- regulator-name = "32KHz AP"; +- regulator-always-on; +- }; +- +- cp32khz_reg: EN32KHz-CP { +- regulator-name = "32KHz CP"; +- }; +- +- vichg_reg: ENVICHG { +- regulator-name = "VICHG"; +- }; +- +- safeout1_reg: ESAFEOUT1 { +- regulator-name = "SAFEOUT1"; +- }; +- +- safeout2_reg: ESAFEOUT2 { +- regulator-name = "SAFEOUT2"; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&i2c_8 { +- status = "okay"; +-}; +- +-&mct { +- compatible = "none"; +-}; +- +-&mdma1 { +- /* Use the secure mdma0 */ +- status = "disabled"; +-}; +- +-&mixer { +- status = "okay"; +-}; +- +-&ohci { +- status = "okay"; +-}; +- +-&pinctrl_1 { +- bt_shutdown: bt-shutdown { +- samsung,pins = "gpe1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- bt_host_wakeup: bt-host-wakeup { +- samsung,pins = "gpx2-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- bt_device_wakeup: bt-device-wakeup { +- samsung,pins = "gpx3-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- lp3974_irq: lp3974-irq { +- samsung,pins = "gpx0-7", "gpx2-7"; +- samsung,pin-pud = ; +- }; +- +- hdmi_hpd: hdmi-hpd { +- samsung,pins = "gpx3-7"; +- samsung,pin-pud = ; +- }; +-}; +- +-&pinctrl_0 { +- i2c_ddc_bus: i2c-ddc-bus { +- samsung,pins = "gpe4-2", "gpe4-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pwm { +- compatible = "samsung,s5p6440-pwm"; +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&sdhci_0 { +- bus-width = <8>; +- non-removable; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; +- pinctrl-names = "default"; +- vmmc-supply = <&vemmc_reg>; +- status = "okay"; +-}; +- +-&sdhci_2 { +- bus-width = <4>; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; +- pinctrl-names = "default"; +- vmmc-supply = <&ldo5_reg>; +- cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&sdhci_3 { +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- non-removable; +- bus-width = <4>; +- mmc-pwrseq = <&wlan_pwrseq>; +- vmmc-supply = <&ldo5_reg>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; +- +- brcmf: wifi@1 { +- compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; +- reg = <1>; +- interrupt-parent = <&gpx2>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "host-wake"; +- }; +-}; +- +-&serial_0 { +- status = "okay"; +- /delete-property/dmas; +- /delete-property/dma-names; +- pinctrl-0 = <&uart0_data &uart0_fctl>; +- pinctrl-names = "default"; +- +- bluetooth { +- compatible = "brcm,bcm4330-bt"; +- pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; +- pinctrl-names = "default"; +- shutdown-gpios = <&gpe1 4 GPIO_ACTIVE_HIGH>; +- device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&serial_1 { +- status = "okay"; +- /delete-property/dmas; +- /delete-property/dma-names; +-}; +- +-&serial_2 { +- status = "okay"; +- /delete-property/dmas; +- /delete-property/dma-names; +-}; +- +-&serial_3 { +- status = "okay"; +- /delete-property/dmas; +- /delete-property/dma-names; +-}; +- +-&soc { +- mdma0: mdma@12840000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x12840000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_MDMA>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <1>; +- power-domains = <&pd_lcd0>; +- }; +-}; +- +-&sysram { +- smp-sram@0 { +- status = "disabled"; +- }; +- +- smp-sram@5000 { +- compatible = "samsung,exynos4210-sysram"; +- reg = <0x5000 0x1000>; +- }; +- +- smp-sram@1f000 { +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4210.dtsi b/scripts/dtc/include-prefixes/arm/exynos4210.dtsi +deleted file mode 100644 +index 7e7d65ce6585..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4210.dtsi ++++ /dev/null +@@ -1,534 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos4210 SoC device tree source +- * +- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * Copyright (c) 2010-2011 Linaro Ltd. +- * www.linaro.org +- * +- * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210 +- * based board files can include this file and provide values for board specific +- * bindings. +- * +- * Note: This file does not include device nodes for all the controllers in +- * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional +- * nodes can be added to this file. +- */ +- +-#include "exynos4.dtsi" +-#include "exynos4-cpu-thermal.dtsi" +- +-/ { +- compatible = "samsung,exynos4210", "samsung,exynos4"; +- +- aliases { +- pinctrl0 = &pinctrl_0; +- pinctrl1 = &pinctrl_1; +- pinctrl2 = &pinctrl_2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- }; +- }; +- +- cpu0: cpu@900 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0x900>; +- clocks = <&clock CLK_ARM_CLK>; +- clock-names = "cpu"; +- clock-latency = <160000>; +- +- operating-points = < +- 1200000 1250000 +- 1000000 1150000 +- 800000 1075000 +- 500000 975000 +- 400000 975000 +- 200000 950000 +- >; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- +- cpu1: cpu@901 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0x901>; +- clocks = <&clock CLK_ARM_CLK>; +- clock-names = "cpu"; +- clock-latency = <160000>; +- +- operating-points = < +- 1200000 1250000 +- 1000000 1150000 +- 800000 1075000 +- 500000 975000 +- 400000 975000 +- 200000 950000 +- >; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- }; +- +- soc: soc { +- sysram: sram@2020000 { +- compatible = "mmio-sram"; +- reg = <0x02020000 0x20000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x02020000 0x20000>; +- +- smp-sram@0 { +- compatible = "samsung,exynos4210-sysram"; +- reg = <0x0 0x1000>; +- }; +- +- smp-sram@1f000 { +- compatible = "samsung,exynos4210-sysram-ns"; +- reg = <0x1f000 0x1000>; +- }; +- }; +- +- pd_lcd1: power-domain@10023ca0 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10023CA0 0x20>; +- #power-domain-cells = <0>; +- label = "LCD1"; +- }; +- +- l2c: cache-controller@10502000 { +- compatible = "arm,pl310-cache"; +- reg = <0x10502000 0x1000>; +- cache-unified; +- cache-level = <2>; +- prefetch-data = <1>; +- prefetch-instr = <1>; +- arm,tag-latency = <2 2 1>; +- arm,data-latency = <2 2 1>; +- }; +- +- mct: timer@10050000 { +- compatible = "samsung,exynos4210-mct"; +- reg = <0x10050000 0x800>; +- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; +- clock-names = "fin_pll", "mct"; +- interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, +- <&combiner 12 6>, +- <&combiner 12 7>, +- <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- watchdog: watchdog@10060000 { +- compatible = "samsung,s3c6410-wdt"; +- reg = <0x10060000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_WDT>; +- clock-names = "watchdog"; +- }; +- +- clock: clock-controller@10030000 { +- compatible = "samsung,exynos4210-clock"; +- reg = <0x10030000 0x20000>; +- #clock-cells = <1>; +- }; +- +- pinctrl_0: pinctrl@11400000 { +- compatible = "samsung,exynos4210-pinctrl"; +- reg = <0x11400000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_1: pinctrl@11000000 { +- compatible = "samsung,exynos4210-pinctrl"; +- reg = <0x11000000 0x1000>; +- interrupts = ; +- +- wakup_eint: wakeup-interrupt-controller { +- compatible = "samsung,exynos4210-wakeup-eint"; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +- +- pinctrl_2: pinctrl@3860000 { +- compatible = "samsung,exynos4210-pinctrl"; +- reg = <0x03860000 0x1000>; +- }; +- +- g2d: g2d@12800000 { +- compatible = "samsung,s5pv210-g2d"; +- reg = <0x12800000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; +- clock-names = "sclk_fimg2d", "fimg2d"; +- power-domains = <&pd_lcd0>; +- iommus = <&sysmmu_g2d>; +- }; +- +- ppmu_acp: ppmu@10ae0000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x10ae0000 0x2000>; +- status = "disabled"; +- }; +- +- ppmu_lcd1: ppmu@12240000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x12240000 0x2000>; +- clocks = <&clock CLK_PPMULCD1>; +- clock-names = "ppmu"; +- status = "disabled"; +- }; +- +- sysmmu_g2d: sysmmu@12a20000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x12A20000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <4 7>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; +- power-domains = <&pd_lcd0>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimd1: sysmmu@12220000 { +- compatible = "samsung,exynos-sysmmu"; +- interrupt-parent = <&combiner>; +- reg = <0x12220000 0x1000>; +- interrupts = <5 3>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; +- power-domains = <&pd_lcd1>; +- #iommu-cells = <0>; +- }; +- +- bus_dmc: bus-dmc { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DIV_DMC>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_dmc_opp_table>; +- status = "disabled"; +- }; +- +- bus_acp: bus-acp { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DIV_ACP>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_acp_opp_table>; +- status = "disabled"; +- }; +- +- bus_peri: bus-peri { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_ACLK100>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_peri_opp_table>; +- status = "disabled"; +- }; +- +- bus_fsys: bus-fsys { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_ACLK133>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_fsys_opp_table>; +- status = "disabled"; +- }; +- +- bus_display: bus-display { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_ACLK160>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_display_opp_table>; +- status = "disabled"; +- }; +- +- bus_lcd0: bus-lcd0 { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_ACLK200>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_leftbus_opp_table>; +- status = "disabled"; +- }; +- +- bus_leftbus: bus-leftbus { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DIV_GDL>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_leftbus_opp_table>; +- status = "disabled"; +- }; +- +- bus_rightbus: bus-rightbus { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DIV_GDR>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_leftbus_opp_table>; +- status = "disabled"; +- }; +- +- bus_mfc: bus-mfc { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_SCLK_MFC>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_leftbus_opp_table>; +- status = "disabled"; +- }; +- +- bus_dmc_opp_table: opp-table1 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-134000000 { +- opp-hz = /bits/ 64 <134000000>; +- opp-microvolt = <1025000>; +- }; +- opp-267000000 { +- opp-hz = /bits/ 64 <267000000>; +- opp-microvolt = <1050000>; +- }; +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <1150000>; +- opp-suspend; +- }; +- }; +- +- bus_acp_opp_table: opp-table2 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-134000000 { +- opp-hz = /bits/ 64 <134000000>; +- }; +- opp-160000000 { +- opp-hz = /bits/ 64 <160000000>; +- }; +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- }; +- }; +- +- bus_peri_opp_table: opp-table3 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-5000000 { +- opp-hz = /bits/ 64 <5000000>; +- }; +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- }; +- }; +- +- bus_fsys_opp_table: opp-table4 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-10000000 { +- opp-hz = /bits/ 64 <10000000>; +- }; +- opp-134000000 { +- opp-hz = /bits/ 64 <134000000>; +- }; +- }; +- +- bus_display_opp_table: opp-table5 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- }; +- opp-134000000 { +- opp-hz = /bits/ 64 <134000000>; +- }; +- opp-160000000 { +- opp-hz = /bits/ 64 <160000000>; +- }; +- }; +- +- bus_leftbus_opp_table: opp-table6 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- }; +- opp-160000000 { +- opp-hz = /bits/ 64 <160000000>; +- }; +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- opp-suspend; +- }; +- }; +- }; +-}; +- +-&cpu_alert0 { +- temperature = <85000>; /* millicelsius */ +-}; +- +-&cpu_alert1 { +- temperature = <100000>; /* millicelsius */ +-}; +- +-&cpu_alert2 { +- temperature = <110000>; /* millicelsius */ +-}; +- +-&cpu_thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&tmu 0>; +-}; +- +-&gic { +- cpu-offset = <0x8000>; +-}; +- +-&camera { +- clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, +- <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; +- clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; +-}; +- +-&combiner { +- samsung,combiner-nr = <16>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +-}; +- +-&fimc_0 { +- samsung,pix-limits = <4224 8192 1920 4224>; +- samsung,mainscaler-ext; +- samsung,cam-if; +-}; +- +-&fimc_1 { +- samsung,pix-limits = <4224 8192 1920 4224>; +- samsung,mainscaler-ext; +- samsung,cam-if; +-}; +- +-&fimc_2 { +- samsung,pix-limits = <4224 8192 1920 4224>; +- samsung,mainscaler-ext; +- samsung,lcd-wb; +-}; +- +-&fimc_3 { +- samsung,pix-limits = <1920 8192 1366 1920>; +- samsung,rotators = <0>; +- samsung,mainscaler-ext; +- samsung,lcd-wb; +-}; +- +-&gpu { +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "gp", +- "gpmmu", +- "pp0", +- "ppmmu0", +- "pp1", +- "ppmmu1", +- "pp2", +- "ppmmu2", +- "pp3", +- "ppmmu3"; +- operating-points-v2 = <&gpu_opp_table>; +- +- gpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-160000000 { +- opp-hz = /bits/ 64 <160000000>; +- opp-microvolt = <950000>; +- }; +- opp-267000000 { +- opp-hz = /bits/ 64 <267000000>; +- opp-microvolt = <1050000>; +- }; +- }; +-}; +- +-&mdma1 { +- power-domains = <&pd_lcd0>; +-}; +- +-&mixer { +- clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer", +- "sclk_mixer"; +- clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, +- <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>, +- <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>; +-}; +- +-&pmu { +- interrupts = <2 2>, <3 2>; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- status = "okay"; +-}; +- +-&pmu_system_controller { +- clock-names = "clkout0", "clkout1", "clkout2", "clkout3", +- "clkout4", "clkout8", "clkout9"; +- clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, +- <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, +- <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; +- #clock-cells = <1>; +-}; +- +-&rotator { +- power-domains = <&pd_lcd0>; +-}; +- +-&sysmmu_rotator { +- power-domains = <&pd_lcd0>; +-}; +- +-&tmu { +- compatible = "samsung,exynos4210-tmu"; +- clocks = <&clock CLK_TMU_APBIF>; +- clock-names = "tmu_apbif"; +- samsung,tmu_gain = <15>; +- samsung,tmu_reference_voltage = <7>; +-}; +- +-#include "exynos4210-pinctrl.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-galaxy-s3.dtsi b/scripts/dtc/include-prefixes/arm/exynos4412-galaxy-s3.dtsi +deleted file mode 100644 +index c14e37dc3a9b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-galaxy-s3.dtsi ++++ /dev/null +@@ -1,214 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos4412 based Galaxy S3 board device tree source +- * +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-/dts-v1/; +-#include "exynos4412-midas.dtsi" +- +-/ { +- aliases { +- i2c9 = &i2c_ak8975; +- i2c10 = &i2c_cm36651; +- }; +- +- led-controller { +- compatible = "skyworks,aat1290"; +- flen-gpios = <&gpj1 1 GPIO_ACTIVE_HIGH>; +- enset-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>; +- +- pinctrl-names = "default", "host", "isp"; +- pinctrl-0 = <&camera_flash_host>; +- pinctrl-1 = <&camera_flash_host>; +- pinctrl-2 = <&camera_flash_isp>; +- +- flash-led { +- label = "flash"; +- led-max-microamp = <520833>; +- flash-max-microamp = <1012500>; +- flash-max-timeout-us = <1940000>; +- }; +- }; +- +- lcd_vdd3_reg: voltage-regulator-10 { +- compatible = "regulator-fixed"; +- regulator-name = "LCD_VDD_2.2V"; +- regulator-min-microvolt = <2200000>; +- regulator-max-microvolt = <2200000>; +- gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- ps_als_reg: voltage-regulator-11 { +- compatible = "regulator-fixed"; +- regulator-name = "LED_A_3.0V"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- gpio = <&gpj0 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- i2c_ak8975: i2c-gpio-0 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpy2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpy2 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- magnetometer@c { +- compatible = "asahi-kasei,ak8975"; +- reg = <0x0c>; +- gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- i2c_cm36651: i2c-gpio-2 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpf0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpf0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- light-sensor@18 { +- compatible = "capella,cm36651"; +- reg = <0x18>; +- interrupt-parent = <&gpx0>; +- interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +- vled-supply = <&ps_als_reg>; +- }; +- }; +-}; +- +-&buck9_reg { +- maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>; +-}; +- +-&cam_af_reg { +- gpio = <&gpm0 4 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&cam_io_reg { +- gpio = <&gpm0 2 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&dsi_0 { +- status = "okay"; +- +- panel@0 { +- compatible = "samsung,s6e8aa0"; +- reg = <0>; +- vdd3-supply = <&lcd_vdd3_reg>; +- vci-supply = <&ldo25_reg>; +- reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>; +- power-on-delay= <50>; +- reset-delay = <100>; +- init-delay = <100>; +- flip-horizontal; +- flip-vertical; +- panel-width-mm = <58>; +- panel-height-mm = <103>; +- +- display-timings { +- timing-0 { +- clock-frequency = <57153600>; +- hactive = <720>; +- vactive = <1280>; +- hfront-porch = <5>; +- hback-porch = <5>; +- hsync-len = <5>; +- vfront-porch = <13>; +- vback-porch = <1>; +- vsync-len = <2>; +- }; +- }; +- }; +-}; +- +-&i2c_3 { +- touchscreen@48 { +- compatible = "melfas,mms114"; +- reg = <0x48>; +- interrupt-parent = <&gpm2>; +- interrupts = <3 IRQ_TYPE_EDGE_FALLING>; +- touchscreen-size-x = <720>; +- touchscreen-size-y = <1280>; +- avdd-supply = <&ldo23_reg>; +- vdd-supply = <&ldo24_reg>; +- }; +-}; +- +-&ldo25_reg { +- regulator-name = "LCD_VCC_3.3V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +-}; +- +-&pinctrl_0 { +- camera_flash_host: camera-flash-host { +- samsung,pins = "gpj1-0"; +- samsung,pin-function = ; +- samsung,pin-val = <0>; +- }; +- +- camera_flash_isp: camera-flash-isp { +- samsung,pins = "gpj1-0"; +- samsung,pin-function = ; +- samsung,pin-val = <1>; +- }; +-}; +- +-&s5c73m3 { +- standby-gpios = <&gpm0 1 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */ +- vdda-supply = <&ldo17_reg>; +- status = "okay"; +-}; +- +-&sound { +- samsung,audio-routing = +- "HP", "HPOUT1L", +- "HP", "HPOUT1R", +- +- "SPK", "SPKOUTLN", +- "SPK", "SPKOUTLP", +- "SPK", "SPKOUTRN", +- "SPK", "SPKOUTRP", +- +- "RCV", "HPOUT2N", +- "RCV", "HPOUT2P", +- +- "HDMI", "LINEOUT1N", +- "HDMI", "LINEOUT1P", +- +- "LINE", "LINEOUT2N", +- "LINE", "LINEOUT2P", +- +- "IN1LP", "MICBIAS1", +- "IN1LN", "MICBIAS1", +- "Main Mic", "MICBIAS1", +- +- "IN1RP", "Sub Mic", +- "IN1RN", "Sub Mic", +- +- "IN2LP:VXRN", "MICBIAS2", +- "Headset Mic", "MICBIAS2", +- +- "IN2RN", "FM In", +- "IN2RP:VXRP", "FM In"; +-}; +- +-&submic_bias_reg { +- gpio = <&gpf2 0 GPIO_ACTIVE_HIGH>; +- enable-active-high; +-}; +- +-&touchkey_reg { +- gpio = <&gpm0 0 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-i9300.dts b/scripts/dtc/include-prefixes/arm/exynos4412-i9300.dts +deleted file mode 100644 +index 07fbcf845c49..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-i9300.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos4412 based M0 (GT-I9300) board device tree source +- * +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-/dts-v1/; +-#include "exynos4412-galaxy-s3.dtsi" +- +-/ { +- model = "Samsung Galaxy S3 (GT-I9300) based on Exynos4412"; +- compatible = "samsung,i9300", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; +- +- /* bootargs are passed in by bootloader */ +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x40000000>; +- }; +-}; +- +-&sound { +- fm-sel-gpios = <&gpl0 3 GPIO_ACTIVE_HIGH>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-i9305.dts b/scripts/dtc/include-prefixes/arm/exynos4412-i9305.dts +deleted file mode 100644 +index 6bc3d897f432..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-i9305.dts ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "exynos4412-galaxy-s3.dtsi" +- +-/ { +- model = "Samsung Galaxy S3 (GT-I9305) based on Exynos4412"; +- compatible = "samsung,i9305", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; +- +- /* bootargs are passed in by bootloader */ +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x80000000>; +- }; +-}; +- +-&i2c0_bus { +- /* SCL and SDA pins are swapped */ +- samsung,pins = "gpd1-1", "gpd1-0"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-itop-elite.dts b/scripts/dtc/include-prefixes/arm/exynos4412-itop-elite.dts +deleted file mode 100644 +index 47431307cb3c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-itop-elite.dts ++++ /dev/null +@@ -1,227 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * TOPEET's Exynos4412 based itop board device tree source +- * +- * Copyright (c) 2016 SUMOMO Computer Association +- * https://www.sumomo.mobi +- * Randy Li +- * +- * Device tree source file for TOPEET iTop Exynos 4412 core board +- * which is based on Samsung's Exynos4412 SoC. +- */ +- +-/dts-v1/; +-#include +-#include +-#include "exynos4412-itop-scp-core.dtsi" +- +-/ { +- model = "TOPEET iTop 4412 Elite board based on Exynos4412"; +- compatible = "topeet,itop4412-elite", "samsung,exynos4412", "samsung,exynos4"; +- +- chosen { +- bootargs = "root=/dev/mmcblk0p2 rw rootfstype=ext4 rootdelay=1 rootwait"; +- stdout-path = "serial2:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led2 { +- label = "red:system"; +- gpios = <&gpx1 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led3 { +- label = "red:user"; +- gpios = <&gpk1 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- home { +- label = "GPIO Key Home"; +- linux,code = ; +- gpios = <&gpx1 1 GPIO_ACTIVE_LOW>; +- }; +- +- back { +- label = "GPIO Key Back"; +- linux,code = ; +- gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; +- }; +- +- sleep { +- label = "GPIO Key Sleep"; +- linux,code = ; +- gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; +- }; +- +- vol-up { +- label = "GPIO Key Vol+"; +- linux,code = ; +- gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; +- }; +- +- vol-down { +- label = "GPIO Key Vol-"; +- linux,code = ; +- gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "wm-sound"; +- +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&link0_codec>; +- simple-audio-card,frame-master = <&link0_codec>; +- +- simple-audio-card,widgets = +- "Microphone", "Mic Jack", +- "Line", "Line In", +- "Line", "Line Out", +- "Speaker", "Speaker", +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "Headphone Jack", "HP_L", +- "Headphone Jack", "HP_R", +- "Speaker", "SPK_LP", +- "Speaker", "SPK_LN", +- "Speaker", "SPK_RP", +- "Speaker", "SPK_RN", +- "LINPUT1", "Mic Jack", +- "LINPUT3", "Mic Jack", +- "RINPUT1", "Mic Jack", +- "RINPUT2", "Mic Jack"; +- +- simple-audio-card,cpu { +- sound-dai = <&i2s0 0>; +- }; +- +- link0_codec: simple-audio-card,codec { +- sound-dai = <&codec>; +- clocks = <&i2s0 CLK_I2S_CDCLK>; +- system-clock-frequency = <11289600>; +- }; +- }; +- +- beep { +- compatible = "pwm-beeper"; +- pwms = <&pwm 0 4000000 PWM_POLARITY_INVERTED>; +- }; +-}; +- +-&adc { +- vdd-supply = <&ldo3_reg>; +- status = "okay"; +-}; +- +-&camera { +- pinctrl-0 = <&cam_port_a_clk_active>; +- pinctrl-names = "default"; +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_CAM0>; +- assigned-clock-parents = <&clock CLK_XUSBXTI>; +-}; +- +-&clock_audss { +- assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, +- <&clock_audss EXYNOS_MOUT_I2S>, +- <&clock_audss EXYNOS_DOUT_SRP>, +- <&clock_audss EXYNOS_DOUT_AUD_BUS>; +- assigned-clock-parents = <&clock CLK_FOUT_EPLL>, +- <&clock_audss EXYNOS_MOUT_AUDSS>; +- assigned-clock-rates = <0>, <0>, <112896000>, <11289600>; +-}; +- +-&ehci { +- status = "okay"; +- /* In order to reset USB ethernet */ +- samsung,vbus-gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; +- +- phys = <&exynos_usbphy 1>, <&exynos_usbphy 3>; +- phy-names = "host", "hsic1"; +-}; +- +-&exynos_usbphy { +- status = "okay"; +-}; +- +-&fimc_0 { +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_FIMC0>, +- <&clock CLK_SCLK_FIMC0>; +- assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; +- assigned-clock-rates = <0>, <176000000>; +-}; +- +-&hsotg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&i2c_4 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <100000>; +- pinctrl-0 = <&i2c4_bus>; +- pinctrl-names = "default"; +- status = "okay"; +- +- codec: audio-codec@1a { +- compatible = "wlf,wm8960"; +- reg = <0x1a>; +- clocks = <&pmu_system_controller 0>; +- clock-names = "MCLK1"; +- wlf,shared-lrclk; +- #sound-dai-cells = <0>; +- }; +-}; +- +-&i2s0 { +- pinctrl-0 = <&i2s0_bus>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&pinctrl_1 { +- ether-reset { +- samsung,pins = "gpc0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pwm { +- status = "okay"; +- pinctrl-0 = <&pwm0_out>; +- pinctrl-names = "default"; +- samsung,pwm-outputs = <0>; +-}; +- +-&sdhci_2 { +- bus-width = <4>; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; +- pinctrl-names = "default"; +- cd-gpio = <&gpx0 7 GPIO_ACTIVE_LOW>; +- cap-sd-highspeed; +- vmmc-supply = <&ldo23_reg>; +- vqmmc-supply = <&ldo17_reg>; +- status = "okay"; +-}; +- +-&serial_1 { +- status = "okay"; +-}; +- +-&serial_2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-itop-scp-core.dtsi b/scripts/dtc/include-prefixes/arm/exynos4412-itop-scp-core.dtsi +deleted file mode 100644 +index b3726d4d7d93..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-itop-scp-core.dtsi ++++ /dev/null +@@ -1,504 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * TOPEET's Exynos4412 based itop board device tree source +- * +- * Copyright (c) 2016 SUMOMO Computer Association +- * https://www.sumomo.mobi +- * Randy Li +- * +- * Device tree source file for TOPEET iTop Exynos 4412 SCP package core +- * board which is based on Samsung's Exynos4412 SoC. +- */ +- +-#include +-#include +-#include +-#include "exynos4412.dtsi" +-#include "exynos4412-ppmu-common.dtsi" +-#include "exynos-mfc-reserved-memory.dtsi" +- +-/ { +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x40000000>; +- }; +- +- firmware@203f000 { +- compatible = "samsung,secure-firmware"; +- reg = <0x0203F000 0x1000>; +- }; +- +- fixed-rate-clocks { +- xxti { +- compatible = "samsung,clock-xxti"; +- clock-frequency = <0>; +- }; +- +- xusbxti { +- compatible = "samsung,clock-xusbxti"; +- clock-frequency = <24000000>; +- }; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- cooling-maps { +- map0 { +- /* Corresponds to 800MHz at freq_table */ +- cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, +- <&cpu2 7 7>, <&cpu3 7 7>; +- }; +- map1 { +- /* Corresponds to 200MHz at freq_table */ +- cooling-device = <&cpu0 13 13>, +- <&cpu1 13 13>, +- <&cpu2 13 13>, +- <&cpu3 13 13>; +- }; +- }; +- }; +- }; +- +- usb-hub { +- compatible = "smsc,usb3503a"; +- reset-gpios = <&gpm2 4 GPIO_ACTIVE_LOW>; +- connect-gpios = <&gpm3 3 GPIO_ACTIVE_HIGH>; +- intn-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hsic_reset>; +- }; +-}; +- +-&bus_dmc { +- devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; +- vdd-supply = <&buck1_reg>; +- status = "okay"; +-}; +- +-&bus_acp { +- devfreq = <&bus_dmc>; +- status = "okay"; +-}; +- +-&bus_c2c { +- devfreq = <&bus_dmc>; +- status = "okay"; +-}; +- +-&bus_leftbus { +- devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; +- vdd-supply = <&buck3_reg>; +- status = "okay"; +-}; +- +-&bus_rightbus { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_fsys { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_peri { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_mfc { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&cpu0 { +- cpu0-supply = <&buck2_reg>; +-}; +- +-&gpu { +- mali-supply = <&buck4_reg>; +- status = "okay"; +-}; +- +-&hsotg { +- vusb_d-supply = <&ldo15_reg>; +- vusb_a-supply = <&ldo12_reg>; +-}; +- +-&i2c_1 { +- #address-cells = <1>; +- #size-cells = <0>; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <400000>; +- pinctrl-0 = <&i2c1_bus>; +- pinctrl-names = "default"; +- status = "okay"; +- +- s5m8767: pmic@66 { +- compatible = "samsung,s5m8767-pmic"; +- reg = <0x66>; +- +- s5m8767,pmic-buck-default-dvs-idx = <3>; +- +- s5m8767,pmic-buck-dvs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>, +- <&gpb 6 GPIO_ACTIVE_HIGH>, +- <&gpb 7 GPIO_ACTIVE_HIGH>; +- +- s5m8767,pmic-buck-ds-gpios = <&gpm3 5 GPIO_ACTIVE_HIGH>, +- <&gpm3 6 GPIO_ACTIVE_HIGH>, +- <&gpm3 7 GPIO_ACTIVE_HIGH>; +- +- /* VDD_ARM */ +- s5m8767,pmic-buck2-dvs-voltage = <1356250>, <1300000>, +- <1243750>, <1118750>, +- <1068750>, <1012500>, +- <956250>, <900000>; +- /* VDD_INT */ +- s5m8767,pmic-buck3-dvs-voltage = <1000000>, <1000000>, +- <925000>, <925000>, +- <887500>, <887500>, +- <850000>, <850000>; +- /* VDD_G3D */ +- s5m8767,pmic-buck4-dvs-voltage = <1081250>, <1081250>, +- <1025000>, <950000>, +- <918750>, <900000>, +- <875000>, <831250>; +- wakeup-source; +- +- regulators { +- ldo1_reg: LDO1 { +- regulator-name = "VDD_ALIVE"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- /* SCP uses 1.5v, POP uses 1.2v */ +- ldo2_reg: LDO2 { +- regulator-name = "VDDQ_M12"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "VDDIOAP_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "VDDQ_PRE"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "VDD_LDO5"; +- op_mode = <0>; /* Always off Mode */ +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "VDD10_MPLL"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "VDD10_XPLL"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "VDD10_MIPI"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "VDD33_LCD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "VDD18_MIPI"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "VDD18_ABB1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "VDD33_UOTG"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "VDDIOPERI_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "VDD18_ABB02"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "VDD10_USH"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "VDD18_HSIC"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "VDDIOAP_MMC012_28"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- /* Used by HSIC */ +- ldo18_reg: LDO18 { +- regulator-name = "VDDIOPERI_28"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo19_reg: LDO19 { +- regulator-name = "VDD_LDO19"; +- op_mode = <0>; /* Always off Mode */ +- }; +- +- ldo20_reg: LDO20 { +- regulator-name = "VDD28_CAM"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2800000>; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo21_reg: LDO21 { +- regulator-name = "VDD28_AF"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2800000>; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo22_reg: LDO22 { +- regulator-name = "VDDA28_2M"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo23_reg: LDO23 { +- regulator-name = "VDD28_TF"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo24_reg: LDO24 { +- regulator-name = "VDD33_A31"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo25_reg: LDO25 { +- regulator-name = "VDD18_CAM"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo26_reg: LDO26 { +- regulator-name = "VDD18_A31"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo27_reg: LDO27 { +- regulator-name = "GPS_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo28_reg: LDO28 { +- regulator-name = "DVDD12"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "vdd_mif"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1456250>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "vdd_int"; +- regulator-min-microvolt = <875000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "vdd_g3d"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "vdd_m12"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- buck6_reg: BUCK6 { +- regulator-name = "vdd12_5m"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- buck7_reg: BUCK7 { +- regulator-name = "pvdd_buck7"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <2000000>; +- regulator-boot-on; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- buck8_reg: BUCK8 { +- regulator-name = "pvdd_buck8"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- buck9_reg: BUCK9 { +- regulator-name = "vddf28_emmc"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3000000>; +- op_mode = <1>; /* Normal Mode */ +- }; +- }; +- +- s5m8767_osc: clocks { +- compatible = "samsung,s5m8767-clk"; +- #clock-cells = <1>; +- clock-output-names = "s5m8767_ap", +- "s5m8767_cp", "s5m8767_bt"; +- }; +- +- }; +-}; +- +-&mfc { +- status = "okay"; +-}; +- +-&mshc_0 { +- pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; +- pinctrl-names = "default"; +- status = "okay"; +- vmmc-supply = <&buck9_reg>; +- broken-cd; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- bus-width = <8>; +- cap-mmc-highspeed; +-}; +- +-&pinctrl_1 { +- hsic_reset: hsic-reset { +- samsung,pins = "gpm2-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&tmu { +- vtmu-supply = <&ldo16_reg>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-midas.dtsi b/scripts/dtc/include-prefixes/arm/exynos4412-midas.dtsi +deleted file mode 100644 +index 968c7943653e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-midas.dtsi ++++ /dev/null +@@ -1,1449 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos4412 based Trats 2 board device tree source +- * +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Device tree source file for Samsung's Trats 2 board which is based on +- * Samsung's Exynos4412 SoC. +- */ +- +-/dts-v1/; +-#include "exynos4412.dtsi" +-#include "exynos4412-ppmu-common.dtsi" +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; +- +- aliases { +- i2c11 = &i2c_max77693; +- i2c12 = &i2c_max77693_fuel; +- }; +- +- chosen { +- stdout-path = &serial_2; +- }; +- +- firmware@204f000 { +- compatible = "samsung,secure-firmware"; +- reg = <0x0204F000 0x1000>; +- }; +- +- fixed-rate-clocks { +- xxti { +- compatible = "samsung,clock-xxti"; +- clock-frequency = <0>; +- }; +- +- xusbxti { +- compatible = "samsung,clock-xusbxti"; +- clock-frequency = <24000000>; +- }; +- }; +- +- cam_io_reg: voltage-regulator-1 { +- compatible = "regulator-fixed"; +- regulator-name = "CAM_SENSOR_A"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- enable-active-high; +- status = "disabled"; +- }; +- +- cam_af_reg: voltage-regulator-2 { +- compatible = "regulator-fixed"; +- regulator-name = "CAM_AF"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- enable-active-high; +- status = "disabled"; +- }; +- +- vsil12: voltage-regulator-3 { +- compatible = "regulator-fixed"; +- regulator-name = "VSIL_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&buck7_reg>; +- }; +- +- vcc33mhl: voltage-regulator-4 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3.3_MHL"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vcc18mhl: voltage-regulator-5 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_1.8_MHL"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- touchkey_reg: voltage-regulator-6 { +- compatible = "regulator-fixed"; +- regulator-name = "LED_VDD_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- status = "disabled"; +- }; +- +- vbatt_reg: voltage-regulator-7 { +- compatible = "regulator-fixed"; +- regulator-name = "VBATT"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- mic_bias_reg: voltage-regulator-8 { +- compatible = "regulator-fixed"; +- regulator-name = "MICBIAS_LDO_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpf1 7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- submic_bias_reg: voltage-regulator-9 { +- compatible = "regulator-fixed"; +- regulator-name = "SUB_MICBIAS_LDO_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys>; +- +- key-down { +- gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; +- linux,code = <114>; +- label = "volume down"; +- debounce-interval = <10>; +- }; +- +- key-up { +- gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; +- linux,code = <115>; +- label = "volume up"; +- debounce-interval = <10>; +- }; +- +- key-power { +- gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; +- linux,code = <116>; +- label = "power"; +- debounce-interval = <10>; +- wakeup-source; +- }; +- +- key-ok { +- gpios = <&gpx0 1 GPIO_ACTIVE_LOW>; +- linux,code = <139>; +- label = "ok"; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- i2c_max77693: i2c-gpio-1 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpm2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpm2 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pmic@66 { +- compatible = "maxim,max77693"; +- interrupt-parent = <&gpx1>; +- interrupts = <5 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&max77693_irq>; +- reg = <0x66>; +- +- regulators { +- esafeout1_reg: ESAFEOUT1 { +- regulator-name = "ESAFEOUT1"; +- }; +- esafeout2_reg: ESAFEOUT2 { +- regulator-name = "ESAFEOUT2"; +- }; +- charger_reg: CHARGER { +- regulator-name = "CHARGER"; +- regulator-min-microamp = <60000>; +- regulator-max-microamp = <2580000>; +- }; +- }; +- +- motor-driver { +- compatible = "maxim,max77693-haptic"; +- haptic-supply = <&ldo26_reg>; +- pwms = <&pwm 0 38022 0>; +- }; +- +- charger { +- compatible = "maxim,max77693-charger"; +- +- maxim,constant-microvolt = <4350000>; +- maxim,min-system-microvolt = <3600000>; +- maxim,thermal-regulation-celsius = <100>; +- maxim,battery-overcurrent-microamp = <3500000>; +- maxim,charge-input-threshold-microvolt = <4300000>; +- }; +- }; +- }; +- +- i2c_max77693_fuel: i2c-gpio-3 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpf1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpf1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fuel-gauge@36 { +- compatible = "maxim,max17047"; +- interrupt-parent = <&gpx2>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&max77693_fuel_irq>; +- reg = <0x36>; +- +- maxim,over-heat-temp = <700>; +- maxim,over-volt = <4500>; +- }; +- }; +- +- i2c-gpio-4 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpl0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpl0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- touchkey@20 { +- compatible = "cypress,midas-touchkey"; +- reg = <0x20>; +- vdd-supply = <&touchkey_reg>; +- vcc-supply = <&ldo5_reg>; +- interrupt-parent = <&gpj0>; +- interrupts = <3 IRQ_TYPE_EDGE_FALLING>; +- linux,keycodes = ; +- }; +- }; +- +- i2c-mhl { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpf0 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpf0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <100>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pinctrl-0 = <&i2c_mhl_bus>; +- pinctrl-names = "default"; +- +- sii9234: hdmi-bridge@39 { +- compatible = "sil,sii9234"; +- avcc33-supply = <&vcc33mhl>; +- iovcc18-supply = <&vcc18mhl>; +- avcc12-supply = <&vsil12>; +- cvcc12-supply = <&vsil12>; +- reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>; +- interrupt-parent = <&gpf3>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; +- reg = <0x39>; +- +- port { +- mhl_to_hdmi: endpoint { +- remote-endpoint = <&hdmi_to_mhl>; +- }; +- }; +- }; +- }; +- +- wlan_pwrseq: sdhci3-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpj0 0 GPIO_ACTIVE_LOW>; +- clocks = <&max77686 MAX77686_CLK_PMIC>; +- clock-names = "ext_clock"; +- }; +- +- sound: sound { +- compatible = "samsung,midas-audio"; +- model = "Midas"; +- mic-bias-supply = <&mic_bias_reg>; +- submic-bias-supply = <&submic_bias_reg>; +- +- cpu { +- sound-dai = <&i2s0 0>; +- }; +- codec { +- sound-dai = <&wm1811>; +- }; +- }; +- +- thermistor-ap { +- compatible = "murata,ncp15wb473"; +- pullup-uv = <1800000>; /* VCC_1.8V_AP */ +- pullup-ohm = <100000>; /* 100K */ +- pulldown-ohm = <100000>; /* 100K */ +- io-channels = <&adc 1>; /* AP temperature */ +- }; +- +- thermistor-battery { +- compatible = "murata,ncp15wb473"; +- pullup-uv = <1800000>; /* VCC_1.8V_AP */ +- pullup-ohm = <100000>; /* 100K */ +- pulldown-ohm = <100000>; /* 100K */ +- io-channels = <&adc 2>; /* Battery temperature */ +- }; +-}; +- +-&adc { +- vdd-supply = <&ldo3_reg>; +- status = "okay"; +-}; +- +-&bus_dmc { +- devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; +- vdd-supply = <&buck1_reg>; +- status = "okay"; +-}; +- +-&bus_acp { +- devfreq = <&bus_dmc>; +- status = "okay"; +-}; +- +-&bus_c2c { +- devfreq = <&bus_dmc>; +- status = "okay"; +-}; +- +-&bus_leftbus { +- devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; +- vdd-supply = <&buck3_reg>; +- status = "okay"; +-}; +- +-&bus_rightbus { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_display { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_fsys { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_peri { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_mfc { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&camera { +- pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; +- pinctrl-names = "default"; +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_CAM0>, +- <&clock CLK_MOUT_CAM1>; +- assigned-clock-parents = <&clock CLK_XUSBXTI>, +- <&clock CLK_XUSBXTI>; +-}; +- +-&cpu0 { +- cpu0-supply = <&buck2_reg>; +-}; +- +-&cpu_thermal { +- cooling-maps { +- map0 { +- /* Corresponds to 800MHz at freq_table */ +- cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, +- <&cpu2 7 7>, <&cpu3 7 7>; +- }; +- map1 { +- /* Corresponds to 200MHz at freq_table */ +- cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, +- <&cpu2 13 13>, <&cpu3 13 13>; +- }; +- }; +-}; +- +-&csis_0 { +- status = "okay"; +- vddcore-supply = <&ldo8_reg>; +- vddio-supply = <&ldo10_reg>; +- assigned-clocks = <&clock CLK_MOUT_CSIS0>, +- <&clock CLK_SCLK_CSIS0>; +- assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; +- assigned-clock-rates = <0>, <176000000>; +- +- /* Camera C (3) MIPI CSI-2 (CSIS0) */ +- port@3 { +- reg = <3>; +- csis0_ep: endpoint { +- remote-endpoint = <&s5c73m3_ep>; +- data-lanes = <1 2 3 4>; +- samsung,csis-hs-settle = <12>; +- }; +- }; +-}; +- +-&csis_1 { +- status = "okay"; +- vddcore-supply = <&ldo8_reg>; +- vddio-supply = <&ldo10_reg>; +- assigned-clocks = <&clock CLK_MOUT_CSIS1>, +- <&clock CLK_SCLK_CSIS1>; +- assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; +- assigned-clock-rates = <0>, <176000000>; +- +- /* Camera D (4) MIPI CSI-2 (CSIS1) */ +- port@4 { +- reg = <4>; +- csis1_ep: endpoint { +- remote-endpoint = <&is_s5k6a3_ep>; +- data-lanes = <1>; +- samsung,csis-hs-settle = <18>; +- samsung,csis-wclk; +- }; +- }; +-}; +- +-&dsi_0 { +- vddcore-supply = <&ldo8_reg>; +- vddio-supply = <&ldo10_reg>; +- samsung,burst-clock-frequency = <500000000>; +- samsung,esc-clock-frequency = <20000000>; +- samsung,pll-clock-frequency = <24000000>; +-}; +- +-&exynos_usbphy { +- vbus-supply = <&esafeout1_reg>; +- status = "okay"; +-}; +- +-&fimc_0 { +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_FIMC0>, +- <&clock CLK_SCLK_FIMC0>; +- assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; +- assigned-clock-rates = <0>, <176000000>; +-}; +- +-&fimc_1 { +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_FIMC1>, +- <&clock CLK_SCLK_FIMC1>; +- assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; +- assigned-clock-rates = <0>, <176000000>; +-}; +- +-&fimc_2 { +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_FIMC2>, +- <&clock CLK_SCLK_FIMC2>; +- assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; +- assigned-clock-rates = <0>, <176000000>; +-}; +- +-&fimc_3 { +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_FIMC3>, +- <&clock CLK_SCLK_FIMC3>; +- assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; +- assigned-clock-rates = <0>, <176000000>; +-}; +- +-&fimc_is { +- pinctrl-0 = <&fimc_is_uart>; +- pinctrl-names = "default"; +- status = "okay"; +- +- }; +- +-&fimc_lite_0 { +- status = "okay"; +-}; +- +-&fimc_lite_1 { +- status = "okay"; +-}; +- +-&fimd { +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&buck4_reg>; +- status = "okay"; +-}; +- +-&hdmi { +- hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_hpd>; +- vdd-supply = <&ldo3_reg>; +- vdd_osc-supply = <&ldo4_reg>; +- vdd_pll-supply = <&ldo3_reg>; +- ddc = <&i2c_5>; +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <1>; +- hdmi_to_mhl: endpoint { +- remote-endpoint = <&mhl_to_hdmi>; +- }; +- }; +- }; +-}; +- +-&hsotg { +- vusb_d-supply = <&ldo15_reg>; +- vusb_a-supply = <&ldo12_reg>; +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&i2c_0 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <400000>; +- pinctrl-0 = <&i2c0_bus>; +- pinctrl-names = "default"; +- status = "okay"; +- +- s5c73m3: image-sensor@3c { +- compatible = "samsung,s5c73m3"; +- reg = <0x3c>; +- xshutdown-gpios = <&gpf1 3 GPIO_ACTIVE_LOW>; /* ISP_RESET */ +- vdd-int-supply = <&buck9_reg>; +- vddio-cis-supply = <&ldo9_reg>; +- vddio-host-supply = <&ldo18_reg>; +- vdd-af-supply = <&cam_af_reg>; +- vdd-reg-supply = <&cam_io_reg>; +- clock-frequency = <24000000>; +- /* CAM_A_CLKOUT */ +- clocks = <&camera 0>; +- clock-names = "cis_extclk"; +- status = "disabled"; +- port { +- s5c73m3_ep: endpoint { +- remote-endpoint = <&csis0_ep>; +- data-lanes = <1 2 3 4>; +- }; +- }; +- }; +-}; +- +-&i2c1_isp { +- pinctrl-0 = <&fimc_is_i2c1>; +- pinctrl-names = "default"; +- +- image-sensor@10 { +- compatible = "samsung,s5k6a3"; +- reg = <0x10>; +- svdda-supply = <&cam_io_reg>; +- svddio-supply = <&ldo19_reg>; +- afvdd-supply = <&ldo19_reg>; +- clock-frequency = <24000000>; +- /* CAM_B_CLKOUT */ +- clocks = <&camera 1>; +- clock-names = "extclk"; +- samsung,camclk-out = <1>; +- gpios = <&gpm1 6 GPIO_ACTIVE_HIGH>; +- +- port { +- is_s5k6a3_ep: endpoint { +- remote-endpoint = <&csis1_ep>; +- data-lanes = <1>; +- }; +- }; +- }; +-}; +- +-&i2c_3 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <400000>; +- pinctrl-0 = <&i2c3_bus>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&i2c_4 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <100000>; +- pinctrl-0 = <&i2c4_bus>; +- pinctrl-names = "default"; +- status = "okay"; +- +- wm1811: audio-codec@1a { +- compatible = "wlf,wm1811"; +- reg = <0x1a>; +- clocks = <&pmu_system_controller 0>, +- <&max77686 MAX77686_CLK_PMIC>; +- clock-names = "MCLK1", "MCLK2"; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupt-parent = <&gpx3>; +- interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; +- +- gpio-controller; +- #gpio-cells = <2>; +- #sound-dai-cells = <0>; +- +- wlf,gpio-cfg = <0x3 0x0 0x0 0x0 0x0 0x0 +- 0x0 0x8000 0x0 0x0 0x0>; +- wlf,micbias-cfg = <0x2f 0x2b>; +- +- wlf,lineout1-feedback; +- wlf,lineout1-se; +- wlf,lineout2-se; +- wlf,ldoena-always-driven; +- +- AVDD2-supply = <&vbatt_reg>; +- DBVDD1-supply = <&ldo3_reg>; +- DBVDD2-supply = <&vbatt_reg>; +- DBVDD3-supply = <&vbatt_reg>; +- DCVDD-supply = <&ldo3_reg>; +- CPVDD-supply = <&vbatt_reg>; +- SPKVDD1-supply = <&vbatt_reg>; +- SPKVDD2-supply = <&vbatt_reg>; +- wlf,ldo1ena = <&gpj0 4 0>; +- wlf,ldo2ena = <&gpj0 4 0>; +- }; +-}; +- +-&i2c_5 { +- status = "okay"; +-}; +- +-&i2c_7 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <100000>; +- pinctrl-0 = <&i2c7_bus>; +- pinctrl-names = "default"; +- status = "okay"; +- +- max77686: pmic@9 { +- compatible = "maxim,max77686"; +- interrupt-parent = <&gpx0>; +- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-0 = <&max77686_irq>; +- pinctrl-names = "default"; +- wakeup-source; +- reg = <0x09>; +- #clock-cells = <1>; +- +- voltage-regulators { +- ldo1_reg: LDO1 { +- regulator-name = "VALIVE_1.0V_AP"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "VM1M2_1.2V_AP"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "VCC_1.8V_AP"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "VCC_2.8V_AP"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "VCC_1.8V_IO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "VMPLL_1.0V_AP"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "VPLL_1.0V_AP"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "VMIPI_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "CAM_ISP_MIPI_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "VMIPI_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "VABB1_1.95V"; +- regulator-min-microvolt = <1950000>; +- regulator-max-microvolt = <1950000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "VUOTG_3.0V"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "NFC_AVDD_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "VABB2_1.95V"; +- regulator-min-microvolt = <1950000>; +- regulator-max-microvolt = <1950000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "VHSIC_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "VHSIC_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "CAM_SENSOR_CORE_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo18_reg: LDO18 { +- regulator-name = "CAM_ISP_SEN_IO_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo19_reg: LDO19 { +- regulator-name = "VT_CAM_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo20_reg: LDO20 { +- regulator-name = "VDDQ_PRE_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo21_reg: LDO21 { +- regulator-name = "VTF_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>; +- }; +- +- ldo22_reg: LDO22 { +- regulator-name = "VMEM_VDD_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; +- }; +- +- ldo23_reg: LDO23 { +- regulator-name = "TSP_AVDD_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo24_reg: LDO24 { +- regulator-name = "TSP_VDD_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo25_reg: LDO25 { +- regulator-name = "LDO25"; +- }; +- +- ldo26_reg: LDO26 { +- regulator-name = "MOTOR_VCC_3.0V"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "VDD_MIF"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "VDD_ARM"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "VDD_INT"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1150000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "VDD_G3D"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1150000>; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "VMEM_1.2V_AP"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- buck6_reg: BUCK6 { +- regulator-name = "VCC_SUB_1.35V"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- }; +- +- buck7_reg: BUCK7 { +- regulator-name = "VCC_SUB_2.0V"; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- regulator-always-on; +- }; +- +- buck8_reg: BUCK8 { +- regulator-name = "VMEM_VDDF_3.0V"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; +- }; +- +- buck9_reg: BUCK9 { +- regulator-name = "CAM_ISP_CORE_1.2V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1200000>; +- }; +- }; +- }; +-}; +- +-&i2c_8 { +- status = "okay"; +-}; +- +-&i2s0 { +- pinctrl-0 = <&i2s0_bus>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&mixer { +- status = "okay"; +-}; +- +-&mshc_0 { +- broken-cd; +- non-removable; +- card-detect-delay = <200>; +- vmmc-supply = <&ldo22_reg>; +- clock-frequency = <400000000>; +- samsung,dw-mshc-ciu-div = <0>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; +- pinctrl-names = "default"; +- status = "okay"; +- bus-width = <8>; +- cap-mmc-highspeed; +-}; +- +-&pmu_system_controller { +- assigned-clocks = <&pmu_system_controller 0>; +- assigned-clock-parents = <&clock CLK_XUSBXTI>; +-}; +- +-&pinctrl_0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sleep0>; +- +- mhl_int: mhl-int { +- samsung,pins = "gpf3-5"; +- samsung,pin-pud = ; +- }; +- +- i2c_mhl_bus: i2c-mhl-bus { +- samsung,pins = "gpf0-4", "gpf0-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sleep0: sleep-states { +- PIN_SLP(gpa0-0, INPUT, NONE); +- PIN_SLP(gpa0-1, OUT0, NONE); +- PIN_SLP(gpa0-2, INPUT, NONE); +- PIN_SLP(gpa0-3, INPUT, UP); +- PIN_SLP(gpa0-4, INPUT, NONE); +- PIN_SLP(gpa0-5, INPUT, DOWN); +- PIN_SLP(gpa0-6, INPUT, DOWN); +- PIN_SLP(gpa0-7, INPUT, UP); +- +- PIN_SLP(gpa1-0, INPUT, DOWN); +- PIN_SLP(gpa1-1, INPUT, DOWN); +- PIN_SLP(gpa1-2, INPUT, DOWN); +- PIN_SLP(gpa1-3, INPUT, DOWN); +- PIN_SLP(gpa1-4, INPUT, DOWN); +- PIN_SLP(gpa1-5, INPUT, DOWN); +- +- PIN_SLP(gpb-0, INPUT, NONE); +- PIN_SLP(gpb-1, INPUT, NONE); +- PIN_SLP(gpb-2, INPUT, NONE); +- PIN_SLP(gpb-3, INPUT, NONE); +- PIN_SLP(gpb-4, INPUT, DOWN); +- PIN_SLP(gpb-5, INPUT, UP); +- PIN_SLP(gpb-6, INPUT, DOWN); +- PIN_SLP(gpb-7, INPUT, DOWN); +- +- PIN_SLP(gpc0-0, INPUT, DOWN); +- PIN_SLP(gpc0-1, INPUT, DOWN); +- PIN_SLP(gpc0-2, INPUT, DOWN); +- PIN_SLP(gpc0-3, INPUT, DOWN); +- PIN_SLP(gpc0-4, INPUT, DOWN); +- +- PIN_SLP(gpc1-0, INPUT, NONE); +- PIN_SLP(gpc1-1, PREV, NONE); +- PIN_SLP(gpc1-2, INPUT, NONE); +- PIN_SLP(gpc1-3, INPUT, NONE); +- PIN_SLP(gpc1-4, INPUT, NONE); +- +- PIN_SLP(gpd0-0, INPUT, DOWN); +- PIN_SLP(gpd0-1, INPUT, DOWN); +- PIN_SLP(gpd0-2, INPUT, NONE); +- PIN_SLP(gpd0-3, INPUT, NONE); +- +- PIN_SLP(gpd1-0, INPUT, DOWN); +- PIN_SLP(gpd1-1, INPUT, DOWN); +- PIN_SLP(gpd1-2, INPUT, NONE); +- PIN_SLP(gpd1-3, INPUT, NONE); +- +- PIN_SLP(gpf0-0, INPUT, NONE); +- PIN_SLP(gpf0-1, INPUT, NONE); +- PIN_SLP(gpf0-2, INPUT, DOWN); +- PIN_SLP(gpf0-3, INPUT, DOWN); +- PIN_SLP(gpf0-4, INPUT, NONE); +- PIN_SLP(gpf0-5, INPUT, DOWN); +- PIN_SLP(gpf0-6, INPUT, NONE); +- PIN_SLP(gpf0-7, INPUT, DOWN); +- +- PIN_SLP(gpf1-0, INPUT, DOWN); +- PIN_SLP(gpf1-1, INPUT, DOWN); +- PIN_SLP(gpf1-2, INPUT, DOWN); +- PIN_SLP(gpf1-3, INPUT, DOWN); +- PIN_SLP(gpf1-4, INPUT, NONE); +- PIN_SLP(gpf1-5, INPUT, NONE); +- PIN_SLP(gpf1-6, INPUT, DOWN); +- PIN_SLP(gpf1-7, PREV, NONE); +- +- PIN_SLP(gpf2-0, PREV, NONE); +- PIN_SLP(gpf2-1, INPUT, DOWN); +- PIN_SLP(gpf2-2, INPUT, DOWN); +- PIN_SLP(gpf2-3, INPUT, DOWN); +- PIN_SLP(gpf2-4, INPUT, DOWN); +- PIN_SLP(gpf2-5, INPUT, DOWN); +- PIN_SLP(gpf2-6, INPUT, NONE); +- PIN_SLP(gpf2-7, INPUT, NONE); +- +- PIN_SLP(gpf3-0, INPUT, NONE); +- PIN_SLP(gpf3-1, PREV, NONE); +- PIN_SLP(gpf3-2, PREV, NONE); +- PIN_SLP(gpf3-3, PREV, NONE); +- PIN_SLP(gpf3-4, OUT1, NONE); +- PIN_SLP(gpf3-5, INPUT, DOWN); +- +- PIN_SLP(gpj0-0, PREV, NONE); +- PIN_SLP(gpj0-1, PREV, NONE); +- PIN_SLP(gpj0-2, PREV, NONE); +- PIN_SLP(gpj0-3, INPUT, DOWN); +- PIN_SLP(gpj0-4, PREV, NONE); +- PIN_SLP(gpj0-5, PREV, NONE); +- PIN_SLP(gpj0-6, INPUT, DOWN); +- PIN_SLP(gpj0-7, INPUT, DOWN); +- +- PIN_SLP(gpj1-0, INPUT, DOWN); +- PIN_SLP(gpj1-1, PREV, NONE); +- PIN_SLP(gpj1-2, PREV, NONE); +- PIN_SLP(gpj1-3, INPUT, DOWN); +- PIN_SLP(gpj1-4, INPUT, DOWN); +- }; +-}; +- +-&pinctrl_1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sleep1>; +- +- gpio_keys: gpio-keys { +- samsung,pins = "gpx0-1", "gpx2-2", "gpx2-7", "gpx3-3"; +- samsung,pin-pud = ; +- }; +- +- bt_shutdown: bt-shutdown { +- samsung,pins = "gpl0-6"; +- samsung,pin-pud = ; +- }; +- +- bt_host_wakeup: bt-host-wakeup { +- samsung,pins = "gpx2-6"; +- samsung,pin-pud = ; +- }; +- +- bt_device_wakeup: bt-device-wakeup { +- samsung,pins = "gpx3-1"; +- samsung,pin-pud = ; +- }; +- +- max77686_irq: max77686-irq { +- samsung,pins = "gpx0-7"; +- samsung,pin-pud = ; +- }; +- +- max77693_irq: max77693-irq { +- samsung,pins = "gpx1-5"; +- samsung,pin-pud = ; +- }; +- +- max77693_fuel_irq: max77693-fuel-irq { +- samsung,pins = "gpx2-3"; +- samsung,pin-pud = ; +- }; +- +- sdhci2_cd: sdhci2-cd-irq { +- samsung,pins = "gpx3-4"; +- samsung,pin-pud = ; +- }; +- +- hdmi_hpd: hdmi-hpd { +- samsung,pins = "gpx3-7"; +- samsung,pin-pud = ; +- }; +- +- sleep1: sleep-states { +- PIN_SLP(gpk0-0, PREV, NONE); +- PIN_SLP(gpk0-1, PREV, NONE); +- PIN_SLP(gpk0-2, OUT0, NONE); +- PIN_SLP(gpk0-3, PREV, NONE); +- PIN_SLP(gpk0-4, PREV, NONE); +- PIN_SLP(gpk0-5, PREV, NONE); +- PIN_SLP(gpk0-6, PREV, NONE); +- +- PIN_SLP(gpk1-0, INPUT, DOWN); +- PIN_SLP(gpk1-1, INPUT, DOWN); +- PIN_SLP(gpk1-2, INPUT, DOWN); +- PIN_SLP(gpk1-3, PREV, NONE); +- PIN_SLP(gpk1-4, PREV, NONE); +- PIN_SLP(gpk1-5, PREV, NONE); +- PIN_SLP(gpk1-6, PREV, NONE); +- +- PIN_SLP(gpk2-0, INPUT, DOWN); +- PIN_SLP(gpk2-1, INPUT, DOWN); +- PIN_SLP(gpk2-2, INPUT, DOWN); +- PIN_SLP(gpk2-3, INPUT, DOWN); +- PIN_SLP(gpk2-4, INPUT, DOWN); +- PIN_SLP(gpk2-5, INPUT, DOWN); +- PIN_SLP(gpk2-6, INPUT, DOWN); +- +- PIN_SLP(gpk3-0, OUT0, NONE); +- PIN_SLP(gpk3-1, INPUT, NONE); +- PIN_SLP(gpk3-2, INPUT, DOWN); +- PIN_SLP(gpk3-3, INPUT, NONE); +- PIN_SLP(gpk3-4, INPUT, NONE); +- PIN_SLP(gpk3-5, INPUT, NONE); +- PIN_SLP(gpk3-6, INPUT, NONE); +- +- PIN_SLP(gpl0-0, INPUT, DOWN); +- PIN_SLP(gpl0-1, INPUT, DOWN); +- PIN_SLP(gpl0-2, INPUT, DOWN); +- PIN_SLP(gpl0-3, INPUT, DOWN); +- PIN_SLP(gpl0-4, PREV, NONE); +- PIN_SLP(gpl0-6, PREV, NONE); +- +- PIN_SLP(gpl1-0, INPUT, DOWN); +- PIN_SLP(gpl1-1, INPUT, DOWN); +- PIN_SLP(gpl2-0, INPUT, DOWN); +- PIN_SLP(gpl2-1, INPUT, DOWN); +- PIN_SLP(gpl2-2, INPUT, DOWN); +- PIN_SLP(gpl2-3, INPUT, DOWN); +- PIN_SLP(gpl2-4, INPUT, DOWN); +- PIN_SLP(gpl2-5, INPUT, DOWN); +- PIN_SLP(gpl2-6, PREV, NONE); +- PIN_SLP(gpl2-7, INPUT, DOWN); +- +- PIN_SLP(gpm0-0, INPUT, DOWN); +- PIN_SLP(gpm0-1, INPUT, DOWN); +- PIN_SLP(gpm0-2, INPUT, DOWN); +- PIN_SLP(gpm0-3, INPUT, DOWN); +- PIN_SLP(gpm0-4, INPUT, DOWN); +- PIN_SLP(gpm0-5, INPUT, DOWN); +- PIN_SLP(gpm0-6, INPUT, DOWN); +- PIN_SLP(gpm0-7, INPUT, DOWN); +- +- PIN_SLP(gpm1-0, INPUT, DOWN); +- PIN_SLP(gpm1-1, INPUT, DOWN); +- PIN_SLP(gpm1-2, INPUT, NONE); +- PIN_SLP(gpm1-3, INPUT, NONE); +- PIN_SLP(gpm1-4, INPUT, NONE); +- PIN_SLP(gpm1-5, INPUT, NONE); +- PIN_SLP(gpm1-6, INPUT, DOWN); +- +- PIN_SLP(gpm2-0, INPUT, NONE); +- PIN_SLP(gpm2-1, INPUT, NONE); +- PIN_SLP(gpm2-2, INPUT, DOWN); +- PIN_SLP(gpm2-3, INPUT, DOWN); +- PIN_SLP(gpm2-4, INPUT, DOWN); +- +- PIN_SLP(gpm3-0, PREV, NONE); +- PIN_SLP(gpm3-1, PREV, NONE); +- PIN_SLP(gpm3-2, PREV, NONE); +- PIN_SLP(gpm3-3, OUT1, NONE); +- PIN_SLP(gpm3-4, INPUT, DOWN); +- PIN_SLP(gpm3-5, INPUT, DOWN); +- PIN_SLP(gpm3-6, INPUT, DOWN); +- PIN_SLP(gpm3-7, INPUT, DOWN); +- +- PIN_SLP(gpm4-0, INPUT, DOWN); +- PIN_SLP(gpm4-1, INPUT, DOWN); +- PIN_SLP(gpm4-2, INPUT, DOWN); +- PIN_SLP(gpm4-3, INPUT, DOWN); +- PIN_SLP(gpm4-4, INPUT, DOWN); +- PIN_SLP(gpm4-5, INPUT, DOWN); +- PIN_SLP(gpm4-6, INPUT, DOWN); +- PIN_SLP(gpm4-7, INPUT, DOWN); +- +- PIN_SLP(gpy0-0, INPUT, DOWN); +- PIN_SLP(gpy0-1, INPUT, DOWN); +- PIN_SLP(gpy0-2, INPUT, DOWN); +- PIN_SLP(gpy0-3, INPUT, DOWN); +- PIN_SLP(gpy0-4, INPUT, DOWN); +- PIN_SLP(gpy0-5, INPUT, DOWN); +- +- PIN_SLP(gpy1-0, INPUT, DOWN); +- PIN_SLP(gpy1-1, INPUT, DOWN); +- PIN_SLP(gpy1-2, INPUT, DOWN); +- PIN_SLP(gpy1-3, INPUT, DOWN); +- +- PIN_SLP(gpy2-0, PREV, NONE); +- PIN_SLP(gpy2-1, INPUT, DOWN); +- PIN_SLP(gpy2-2, INPUT, NONE); +- PIN_SLP(gpy2-3, INPUT, NONE); +- PIN_SLP(gpy2-4, INPUT, NONE); +- PIN_SLP(gpy2-5, INPUT, NONE); +- +- PIN_SLP(gpy3-0, INPUT, DOWN); +- PIN_SLP(gpy3-1, INPUT, DOWN); +- PIN_SLP(gpy3-2, INPUT, DOWN); +- PIN_SLP(gpy3-3, INPUT, DOWN); +- PIN_SLP(gpy3-4, INPUT, DOWN); +- PIN_SLP(gpy3-5, INPUT, DOWN); +- PIN_SLP(gpy3-6, INPUT, DOWN); +- PIN_SLP(gpy3-7, INPUT, DOWN); +- +- PIN_SLP(gpy4-0, INPUT, DOWN); +- PIN_SLP(gpy4-1, INPUT, DOWN); +- PIN_SLP(gpy4-2, INPUT, DOWN); +- PIN_SLP(gpy4-3, INPUT, DOWN); +- PIN_SLP(gpy4-4, INPUT, DOWN); +- PIN_SLP(gpy4-5, INPUT, DOWN); +- PIN_SLP(gpy4-6, INPUT, DOWN); +- PIN_SLP(gpy4-7, INPUT, DOWN); +- +- PIN_SLP(gpy5-0, INPUT, DOWN); +- PIN_SLP(gpy5-1, INPUT, DOWN); +- PIN_SLP(gpy5-2, INPUT, DOWN); +- PIN_SLP(gpy5-3, INPUT, DOWN); +- PIN_SLP(gpy5-4, INPUT, DOWN); +- PIN_SLP(gpy5-5, INPUT, DOWN); +- PIN_SLP(gpy5-6, INPUT, DOWN); +- PIN_SLP(gpy5-7, INPUT, DOWN); +- +- PIN_SLP(gpy6-0, INPUT, DOWN); +- PIN_SLP(gpy6-1, INPUT, DOWN); +- PIN_SLP(gpy6-2, INPUT, DOWN); +- PIN_SLP(gpy6-3, INPUT, DOWN); +- PIN_SLP(gpy6-4, INPUT, DOWN); +- PIN_SLP(gpy6-5, INPUT, DOWN); +- PIN_SLP(gpy6-6, INPUT, DOWN); +- PIN_SLP(gpy6-7, INPUT, DOWN); +- }; +-}; +- +-&pinctrl_2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sleep2>; +- +- sleep2: sleep-states { +- PIN_SLP(gpz-0, INPUT, DOWN); +- PIN_SLP(gpz-1, INPUT, DOWN); +- PIN_SLP(gpz-2, INPUT, DOWN); +- PIN_SLP(gpz-3, INPUT, DOWN); +- PIN_SLP(gpz-4, INPUT, DOWN); +- PIN_SLP(gpz-5, INPUT, DOWN); +- PIN_SLP(gpz-6, INPUT, DOWN); +- }; +-}; +- +-&pinctrl_3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sleep3>; +- +- sleep3: sleep-states { +- PIN_SLP(gpv0-0, INPUT, DOWN); +- PIN_SLP(gpv0-1, INPUT, DOWN); +- PIN_SLP(gpv0-2, INPUT, DOWN); +- PIN_SLP(gpv0-3, INPUT, DOWN); +- PIN_SLP(gpv0-4, INPUT, DOWN); +- PIN_SLP(gpv0-5, INPUT, DOWN); +- PIN_SLP(gpv0-6, INPUT, DOWN); +- PIN_SLP(gpv0-7, INPUT, DOWN); +- +- PIN_SLP(gpv1-0, INPUT, DOWN); +- PIN_SLP(gpv1-1, INPUT, DOWN); +- PIN_SLP(gpv1-2, INPUT, DOWN); +- PIN_SLP(gpv1-3, INPUT, DOWN); +- PIN_SLP(gpv1-4, INPUT, DOWN); +- PIN_SLP(gpv1-5, INPUT, DOWN); +- PIN_SLP(gpv1-6, INPUT, DOWN); +- PIN_SLP(gpv1-7, INPUT, DOWN); +- +- PIN_SLP(gpv2-0, INPUT, DOWN); +- PIN_SLP(gpv2-1, INPUT, DOWN); +- PIN_SLP(gpv2-2, INPUT, DOWN); +- PIN_SLP(gpv2-3, INPUT, DOWN); +- PIN_SLP(gpv2-4, INPUT, DOWN); +- PIN_SLP(gpv2-5, INPUT, DOWN); +- PIN_SLP(gpv2-6, INPUT, DOWN); +- PIN_SLP(gpv2-7, INPUT, DOWN); +- +- PIN_SLP(gpv3-0, INPUT, DOWN); +- PIN_SLP(gpv3-1, INPUT, DOWN); +- PIN_SLP(gpv3-2, INPUT, DOWN); +- PIN_SLP(gpv3-3, INPUT, DOWN); +- PIN_SLP(gpv3-4, INPUT, DOWN); +- PIN_SLP(gpv3-5, INPUT, DOWN); +- PIN_SLP(gpv3-6, INPUT, DOWN); +- PIN_SLP(gpv3-7, INPUT, DOWN); +- +- PIN_SLP(gpv4-0, INPUT, DOWN); +- }; +-}; +- +-&pwm { +- pinctrl-0 = <&pwm0_out>; +- pinctrl-names = "default"; +- samsung,pwm-outputs = <0>; +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&sdhci_2 { +- bus-width = <4>; +- cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sdhci2_cd>; +- pinctrl-names = "default"; +- vmmc-supply = <&ldo21_reg>; +- status = "okay"; +-}; +- +-&sdhci_3 { +- #address-cells = <1>; +- #size-cells = <0>; +- non-removable; +- bus-width = <4>; +- +- mmc-pwrseq = <&wlan_pwrseq>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&gpx2>; +- interrupts = <5 IRQ_TYPE_NONE>; +- interrupt-names = "host-wake"; +- }; +-}; +- +-&serial_0 { +- pinctrl-0 = <&uart0_data &uart0_fctl>; +- pinctrl-names = "default"; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm4330-bt"; +- pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; +- pinctrl-names = "default"; +- max-speed = <3000000>; +- shutdown-gpios = <&gpl0 6 GPIO_ACTIVE_HIGH>; +- device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; +- clocks = <&max77686 MAX77686_CLK_PMIC>; +- }; +-}; +- +-&serial_1 { +- status = "okay"; +-}; +- +-&serial_2 { +- status = "okay"; +-}; +- +-&serial_3 { +- status = "okay"; +-}; +- +-&spi_1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_bus>; +- cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- +- s5c73m3_spi: image-sensor@0 { +- compatible = "samsung,s5c73m3"; +- spi-max-frequency = <50000000>; +- reg = <0>; +- controller-data { +- samsung,spi-feedback-delay = <2>; +- }; +- }; +-}; +- +-&tmu { +- vtmu-supply = <&ldo10_reg>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-n710x.dts b/scripts/dtc/include-prefixes/arm/exynos4412-n710x.dts +deleted file mode 100644 +index 2c792142605c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-n710x.dts ++++ /dev/null +@@ -1,115 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "exynos4412-midas.dtsi" +- +-/ { +- compatible = "samsung,n710x", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; +- model = "Samsung Galaxy Note 2 (GT-N7100, GT-N7105) based on Exynos4412"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x80000000>; +- }; +- +- /* bootargs are passed in by bootloader */ +- +- cam_vdda_reg: voltage-regulator-10 { +- compatible = "regulator-fixed"; +- regulator-name = "CAM_SENSOR_CORE_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- gpio = <&gpm4 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&buck9_reg { +- maxim,ena-gpios = <&gpm1 0 GPIO_ACTIVE_HIGH>; +-}; +- +-&cam_af_reg { +- gpio = <&gpm1 1 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&cam_io_reg { +- gpio = <&gpm0 7 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&i2c_3 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <400000>; +- pinctrl-0 = <&i2c3_bus>; +- pinctrl-names = "default"; +- status = "okay"; +- +- touchscreen@48 { +- compatible = "melfas,mms152"; +- reg = <0x48>; +- interrupt-parent = <&gpm2>; +- interrupts = <3 IRQ_TYPE_EDGE_FALLING>; +- touchscreen-size-x = <720>; +- touchscreen-size-y = <1280>; +- avdd-supply = <&ldo23_reg>; +- vdd-supply = <&ldo24_reg>; +- }; +-}; +- +-&ldo13_reg { +- regulator-name = "VCC_1.8V_LCD"; +- regulator-always-on; +-}; +- +-&ldo25_reg { +- regulator-name = "VCI_3.0V_LCD"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +-}; +- +-&s5c73m3 { +- standby-gpios = <&gpm0 6 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */ +- vdda-supply = <&cam_vdda_reg>; +- status = "okay"; +-}; +- +-&sound { +- samsung,audio-routing = +- "HP", "HPOUT1L", +- "HP", "HPOUT1R", +- +- "SPK", "SPKOUTLN", +- "SPK", "SPKOUTLP", +- +- "RCV", "HPOUT2N", +- "RCV", "HPOUT2P", +- +- "HDMI", "LINEOUT1N", +- "HDMI", "LINEOUT1P", +- +- "LINE", "LINEOUT2N", +- "LINE", "LINEOUT2P", +- +- "IN1LP", "MICBIAS2", +- "IN1LN", "MICBIAS2", +- "Headset Mic", "MICBIAS2", +- +- "IN1RP", "Sub Mic", +- "IN1RN", "Sub Mic", +- +- "IN2LP:VXRN", "Main Mic", +- "IN2LN", "Main Mic", +- +- "IN2RN", "FM In", +- "IN2RP:VXRP", "FM In"; +-}; +- +-&submic_bias_reg { +- regulator-always-on; +-}; +- +-&touchkey_reg { +- gpio = <&gpm0 5 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-odroid-common.dtsi b/scripts/dtc/include-prefixes/arm/exynos4412-odroid-common.dtsi +deleted file mode 100644 +index 5b1d4591b35c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-odroid-common.dtsi ++++ /dev/null +@@ -1,570 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards +- * device tree source +- */ +- +-#include +-#include +-#include +-#include "exynos4412.dtsi" +-#include "exynos4412-ppmu-common.dtsi" +-#include +-#include "exynos-mfc-reserved-memory.dtsi" +- +-/ { +- chosen { +- stdout-path = &serial_1; +- }; +- +- firmware@204f000 { +- compatible = "samsung,secure-firmware"; +- reg = <0x0204F000 0x1000>; +- }; +- +- gpio_keys: gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_power_key>; +- +- power-key { +- gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "power key"; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- sound: sound { +- compatible = "hardkernel,odroid-xu4-audio"; +- +- cpu { +- sound-dai = <&i2s0 0>; +- }; +- +- codec { +- sound-dai = <&hdmi>, <&max98090>; +- }; +- }; +- +- emmc_pwrseq: pwrseq { +- pinctrl-0 = <&emmc_rstn>; +- pinctrl-names = "default"; +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpk1 2 GPIO_ACTIVE_LOW>; +- }; +- +- fixed-rate-clocks { +- xxti { +- compatible = "samsung,clock-xxti"; +- clock-frequency = <0>; +- }; +- +- xusbxti { +- compatible = "samsung,clock-xusbxti"; +- clock-frequency = <24000000>; +- }; +- }; +-}; +- +-&bus_dmc { +- devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; +- vdd-supply = <&buck1_reg>; +- status = "okay"; +-}; +- +-&bus_acp { +- devfreq = <&bus_dmc>; +- status = "okay"; +-}; +- +-&bus_c2c { +- devfreq = <&bus_dmc>; +- status = "okay"; +-}; +- +-&bus_leftbus { +- devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; +- vdd-supply = <&buck3_reg>; +- status = "okay"; +-}; +- +-&bus_rightbus { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_display { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_fsys { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_peri { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_mfc { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&camera { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <>; +-}; +- +-&clock { +- clocks = <&clock CLK_XUSBXTI>; +- assigned-clocks = <&clock CLK_FOUT_EPLL>; +- assigned-clock-rates = <45158401>; +-}; +- +-&clock_audss { +- assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, +- <&clock_audss EXYNOS_MOUT_I2S>, +- <&clock_audss EXYNOS_DOUT_SRP>, +- <&clock_audss EXYNOS_DOUT_AUD_BUS>, +- <&clock_audss EXYNOS_DOUT_I2S>; +- +- assigned-clock-parents = <&clock CLK_FOUT_EPLL>, +- <&clock_audss EXYNOS_MOUT_AUDSS>; +- +- assigned-clock-rates = <0>, <0>, +- <196608001>, +- <(196608001 / 2)>, +- <(196608001 / 8)>; +-}; +- +-&cpu0 { +- cpu0-supply = <&buck2_reg>; +-}; +- +-&cpu0_opp_table { +- opp-1000000000 { +- opp-suspend; +- }; +- opp-800000000 { +- /delete-property/opp-suspend; +- }; +-}; +- +-&cpu_thermal { +- cooling-maps { +- cooling_map0: map0 { +- /* Corresponds to 800MHz at freq_table */ +- cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, +- <&cpu2 7 7>, <&cpu3 7 7>; +- }; +- cooling_map1: map1 { +- /* Corresponds to 200MHz at freq_table */ +- cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, +- <&cpu2 13 13>, <&cpu3 13 13>; +- }; +- }; +-}; +- +-&pinctrl_1 { +- gpio_power_key: power-key { +- samsung,pins = "gpx1-3"; +- samsung,pin-pud = ; +- }; +- +- max77686_irq: max77686-irq { +- samsung,pins = "gpx3-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hdmi_hpd: hdmi-hpd { +- samsung,pins = "gpx3-7"; +- samsung,pin-pud = ; +- }; +- +- emmc_rstn: emmc-rstn { +- samsung,pins = "gpk1-2"; +- samsung,pin-pud = ; +- }; +-}; +- +-&ehci { +- status = "okay"; +-}; +- +-&exynos_usbphy { +- status = "okay"; +-}; +- +-&fimc_0 { +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_FIMC0>, +- <&clock CLK_SCLK_FIMC0>; +- assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; +- assigned-clock-rates = <0>, <176000000>; +-}; +- +-&fimc_1 { +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_FIMC1>, +- <&clock CLK_SCLK_FIMC1>; +- assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; +- assigned-clock-rates = <0>, <176000000>; +-}; +- +-&fimc_2 { +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_FIMC2>, +- <&clock CLK_SCLK_FIMC2>; +- assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; +- assigned-clock-rates = <0>, <176000000>; +-}; +- +-&fimc_3 { +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_FIMC3>, +- <&clock CLK_SCLK_FIMC3>; +- assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; +- assigned-clock-rates = <0>, <176000000>; +-}; +- +-&gpu { +- mali-supply = <&buck4_reg>; +- status = "okay"; +-}; +- +-&hdmi { +- hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_hpd>; +- vdd-supply = <&ldo8_reg>; +- vdd_osc-supply = <&ldo10_reg>; +- vdd_pll-supply = <&ldo8_reg>; +- ddc = <&i2c_2>; +- status = "okay"; +-}; +- +-&hdmicec { +- status = "okay"; +-}; +- +-&hsotg { +- status = "okay"; +- vusb_d-supply = <&ldo15_reg>; +- vusb_a-supply = <&ldo12_reg>; +-}; +- +-&i2c_0 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <400000>; +- status = "okay"; +- +- usb3503: usb-hub@8 { +- compatible = "smsc,usb3503"; +- reg = <0x08>; +- +- intn-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>; +- connect-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; +- initial-mode = <1>; +- }; +- +- max77686: pmic@9 { +- compatible = "maxim,max77686"; +- interrupt-parent = <&gpx3>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&max77686_irq>; +- wakeup-source; +- reg = <0x09>; +- #clock-cells = <1>; +- +- voltage-regulators { +- ldo1_reg: LDO1 { +- regulator-name = "VDD_ALIVE_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "VDDQ_M1_2_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "VDDQ_EXT_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "VDDQ_MMC2_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-boot-on; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "VDDQ_MMC1_3_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "VDD10_MPLL_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "VDD10_XPLL_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "VDD10_HDMI_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "VDDQ_MIPIHSI_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "VDD18_ABB1_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "VDD33_USB_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "VDDQ_C2C_W_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "VDD18_ABB0_2_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "VDD10_HSIC_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "VDD18_HSIC_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo20_reg: LDO20 { +- regulator-name = "LDO20_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo21_reg: LDO21 { +- regulator-name = "TFLASH_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-boot-on; +- }; +- +- ldo22_reg: LDO22 { +- /* +- * Only U3 uses it, so let it define the +- * constraints +- */ +- regulator-name = "LDO22"; +- regulator-boot-on; +- }; +- +- ldo25_reg: LDO25 { +- regulator-name = "VDDQ_LCD_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "VDD_MIF"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "VDD_ARM"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "VDD_INT"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1050000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "VDD_G3D"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1100000>; +- regulator-microvolt-offset = <50000>; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "VDDQ_CKEM1_2_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck6_reg: BUCK6 { +- regulator-name = "BUCK6_1.35V"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck7_reg: BUCK7 { +- regulator-name = "BUCK7_2.0V"; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- regulator-always-on; +- }; +- +- buck8_reg: BUCK8 { +- /* +- * Constraints set by specific board: X, +- * X2 and U3. +- */ +- regulator-name = "BUCK8_2.8V"; +- }; +- }; +- }; +-}; +- +-&i2c_1 { +- status = "okay"; +- max98090: audio-codec@10 { +- compatible = "maxim,max98090"; +- reg = <0x10>; +- interrupt-parent = <&gpx0>; +- interrupts = <0 IRQ_TYPE_NONE>; +- clocks = <&i2s0 CLK_I2S_CDCLK>; +- clock-names = "mclk"; +- #sound-dai-cells = <0>; +- }; +-}; +- +-&i2c_2 { +- status = "okay"; +-}; +- +-&i2c_8 { +- status = "okay"; +-}; +- +-&i2s0 { +- pinctrl-0 = <&i2s0_bus>; +- pinctrl-names = "default"; +- status = "okay"; +- assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; +- assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>; +-}; +- +-&mixer { +- status = "okay"; +-}; +- +-&mshc_0 { +- pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; +- pinctrl-names = "default"; +- vmmc-supply = <&ldo20_reg>; +- mmc-pwrseq = <&emmc_pwrseq>; +- status = "okay"; +- +- broken-cd; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- bus-width = <8>; +- cap-mmc-highspeed; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&sdhci_2 { +- bus-width = <4>; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; +- pinctrl-names = "default"; +- vmmc-supply = <&ldo21_reg>; +- vqmmc-supply = <&ldo4_reg>; +- cd-gpios = <&gpk2 2 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&serial_0 { +- status = "okay"; +-}; +- +-&serial_1 { +- status = "okay"; +-}; +- +-&tmu { +- vtmu-supply = <&ldo10_reg>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-odroidu3.dts b/scripts/dtc/include-prefixes/arm/exynos4412-odroidu3.dts +deleted file mode 100644 +index efaf7533e84f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-odroidu3.dts ++++ /dev/null +@@ -1,153 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Hardkernel's Exynos4412 based ODROID-U3 board device tree source +- * +- * Copyright (c) 2014 Marek Szyprowski +- * +- * Device tree source file for Hardkernel's ODROID-U3 board which is based +- * on Samsung's Exynos4412 SoC. +- */ +- +-/dts-v1/; +-#include "exynos4412-odroid-common.dtsi" +-#include "exynos4412-prime.dtsi" +- +-/ { +- model = "Hardkernel ODROID-U3 board based on Exynos4412"; +- compatible = "hardkernel,odroid-u3", "samsung,exynos4412", "samsung,exynos4"; +- +- aliases { +- ethernet = ðernet; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x7FF00000>; +- }; +- +- vbus_otg_reg: regulator-1 { +- compatible = "regulator-fixed"; +- regulator-name = "VBUS_VDD_5.0V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpl2 0 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led1 { +- label = "led1:heart"; +- gpios = <&gpc1 0 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- fan0: pwm-fan { +- compatible = "pwm-fan"; +- pwms = <&pwm 0 10000 0>; +- #cooling-cells = <2>; +- cooling-levels = <0 102 170 230>; +- }; +-}; +- +-&adc { +- vdd-supply = <&ldo10_reg>; +- /* Nothing connected to ADC inputs, keep it disabled */ +-}; +- +-/* Supply for LAN9730/SMSC95xx */ +-&buck8_reg { +- regulator-name = "BUCK8_P3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +-}; +- +-&cpu_thermal { +- cooling-maps { +- map0 { +- trip = <&cpu_alert1>; +- cooling-device = <&cpu0 9 9>, <&cpu1 9 9>, +- <&cpu2 9 9>, <&cpu3 9 9>, +- <&fan0 1 2>; +- }; +- map1 { +- trip = <&cpu_alert2>; +- cooling-device = <&cpu0 15 15>, <&cpu1 15 15>, +- <&cpu2 15 15>, <&cpu3 15 15>, +- <&fan0 2 3>; +- }; +- map2 { +- trip = <&cpu_alert0>; +- cooling-device = <&fan0 0 1>; +- }; +- }; +-}; +- +-&hdmicec { +- needs-hpd; +-}; +- +-/* VDDQ for MSHC (eMMC card) */ +-&ldo22_reg { +- regulator-name = "LDO22_VDDQ_MMC4_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +-}; +- +-&mshc_0 { +- vqmmc-supply = <&ldo22_reg>; +-}; +- +-&pwm { +- pinctrl-0 = <&pwm0_out>; +- pinctrl-names = "default"; +- samsung,pwm-outputs = <0>; +- status = "okay"; +-}; +- +-&usb3503 { +- clock-names = "refclk"; +- clocks = <&pmu_system_controller 0>; +- refclk-frequency = <24000000>; +-}; +- +-&ehci { +- #address-cells = <1>; +- #size-cells = <0>; +- phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>; +- phy-names = "hsic0", "hsic1"; +- +- ethernet: usbether@2 { +- compatible = "usb0424,9730"; +- reg = <2>; +- local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ +- }; +-}; +- +-&hsotg { +- dr_mode = "otg"; +- vbus-supply = <&vbus_otg_reg>; +-}; +- +-&sound { +- model = "Odroid-U3"; +- samsung,audio-widgets = +- "Headphone", "Headphone Jack", +- "Speakers", "Speakers"; +- samsung,audio-routing = +- "Headphone Jack", "HPL", +- "Headphone Jack", "HPR", +- "Headphone Jack", "MICBIAS", +- "IN1", "Headphone Jack", +- "Speakers", "SPKL", +- "Speakers", "SPKR"; +-}; +- +-&spi_1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_bus>; +- cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-odroidx.dts b/scripts/dtc/include-prefixes/arm/exynos4412-odroidx.dts +deleted file mode 100644 +index 440135d0ff2a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-odroidx.dts ++++ /dev/null +@@ -1,140 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Hardkernel's Exynos4412 based ODROID-X board device tree source +- * +- * Copyright (c) 2012 Dongjin Kim +- * +- * Device tree source file for Hardkernel's ODROID-X board which is based +- * on Samsung's Exynos4412 SoC. +- */ +- +-/dts-v1/; +-#include "exynos4412-odroid-common.dtsi" +- +-/ { +- model = "Hardkernel ODROID-X board based on Exynos4412"; +- compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4"; +- +- aliases { +- ethernet = ðernet; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x3FF00000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led1 { +- label = "led1:heart"; +- gpios = <&gpc1 0 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- led2 { +- label = "led2:mmc0"; +- gpios = <&gpc1 2 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- linux,default-trigger = "mmc0"; +- }; +- }; +- +- regulator-1 { +- compatible = "regulator-fixed"; +- regulator-name = "p3v3_en"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpa1 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +-}; +- +-&adc { +- vdd-supply = <&ldo10_reg>; +- status = "okay"; +-}; +- +-/* VDDQ for MSHC (eMMC card) */ +-&buck8_reg { +- regulator-name = "BUCK8_VDDQ_MMC4_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +-}; +- +-&ehci { +- #address-cells = <1>; +- #size-cells = <0>; +- phys = <&exynos_usbphy 2>; +- phy-names = "hsic0"; +- +- hub@2 { +- compatible = "usb0424,3503"; +- reg = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- hub@1 { +- compatible = "usb0424,9514"; +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethernet: usbether@1 { +- compatible = "usb0424,ec00"; +- reg = <1>; +- /* Filled in by a bootloader */ +- local-mac-address = [00 00 00 00 00 00]; +- }; +- }; +- }; +-}; +- +-&gpio_keys { +- pinctrl-0 = <&gpio_power_key &gpio_home_key>; +- +- home-key { +- gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- label = "home key"; +- debounce-interval = <10>; +- wakeup-source; +- }; +-}; +- +-&hsotg { +- dr_mode = "peripheral"; +-}; +- +-&mshc_0 { +- vqmmc-supply = <&buck8_reg>; +-}; +- +-&pinctrl_1 { +- gpio_home_key: home-key { +- samsung,pins = "gpx2-2"; +- samsung,pin-pud = ; +- }; +-}; +- +-&serial_2 { +- status = "okay"; +-}; +- +-&serial_3 { +- status = "okay"; +-}; +- +-&sound { +- model = "Odroid-X"; +- samsung,audio-widgets = +- "Headphone", "Headphone Jack", +- "Microphone", "Mic Jack", +- "Microphone", "DMIC"; +- samsung,audio-routing = +- "Headphone Jack", "HPL", +- "Headphone Jack", "HPR", +- "IN1", "Mic Jack", +- "Mic Jack", "MICBIAS"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-odroidx2.dts b/scripts/dtc/include-prefixes/arm/exynos4412-odroidx2.dts +deleted file mode 100644 +index f4b68c75c962..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-odroidx2.dts ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Hardkernel's Exynos4412 based ODROID-X2 board device tree source +- * +- * Copyright (c) 2012 Dongjin Kim +- * +- * Device tree source file for Hardkernel's ODROID-X2 board which is based +- * on Samsung's Exynos4412 SoC. +- */ +- +-#include "exynos4412-odroidx.dts" +-#include "exynos4412-prime.dtsi" +- +-/ { +- model = "Hardkernel ODROID-X2 board based on Exynos4412"; +- compatible = "hardkernel,odroid-x2", "samsung,exynos4412", "samsung,exynos4"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x7FF00000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-origen.dts b/scripts/dtc/include-prefixes/arm/exynos4412-origen.dts +deleted file mode 100644 +index 5479ef09f9f3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-origen.dts ++++ /dev/null +@@ -1,552 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Insignal's Exynos4412 based Origen board device tree source +- * +- * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Device tree source file for Insignal's Origen board which is based on +- * Samsung's Exynos4412 SoC. +- */ +- +-/dts-v1/; +-#include "exynos4412.dtsi" +-#include +-#include +-#include +-#include "exynos-mfc-reserved-memory.dtsi" +- +-/ { +- model = "Insignal Origen evaluation board based on Exynos4412"; +- compatible = "insignal,origen4412", "samsung,exynos4412", "samsung,exynos4"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x40000000>; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- firmware@203f000 { +- compatible = "samsung,secure-firmware"; +- reg = <0x0203F000 0x1000>; +- }; +- +- mmc_reg: regulator-0 { +- compatible = "regulator-fixed"; +- regulator-name = "VMEM_VDD_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing { +- clock-frequency = <47500000>; +- hactive = <1024>; +- vactive = <600>; +- hfront-porch = <64>; +- hback-porch = <16>; +- hsync-len = <48>; +- vback-porch = <64>; +- vfront-porch = <16>; +- vsync-len = <3>; +- }; +- }; +- +- fixed-rate-clocks { +- xxti { +- compatible = "samsung,clock-xxti"; +- clock-frequency = <0>; +- }; +- +- xusbxti { +- compatible = "samsung,clock-xusbxti"; +- clock-frequency = <24000000>; +- }; +- }; +-}; +- +-&cpu0 { +- cpu0-supply = <&buck2_reg>; +-}; +- +-&cpu_thermal { +- cooling-maps { +- cooling_map0: map0 { +- /* Corresponds to 800MHz at freq_table */ +- cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, +- <&cpu2 7 7>, <&cpu3 7 7>; +- }; +- cooling_map1: map1 { +- /* Corresponds to 200MHz at freq_table */ +- cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, +- <&cpu2 13 13>, <&cpu3 13 13>; +- }; +- }; +-}; +- +-&exynos_usbphy { +- status = "okay"; +-}; +- +-&ehci { +- samsung,vbus-gpio = <&gpx3 5 1>; +- status = "okay"; +- phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>; +- phy-names = "hsic0", "hsic1"; +-}; +- +-&fimd { +- pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&i2c_0 { +- #address-cells = <1>; +- #size-cells = <0>; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <20000>; +- pinctrl-0 = <&i2c0_bus>; +- pinctrl-names = "default"; +- status = "okay"; +- +- pmic@66 { +- compatible = "samsung,s5m8767-pmic"; +- reg = <0x66>; +- +- s5m8767,pmic-buck-default-dvs-idx = <3>; +- +- s5m8767,pmic-buck-dvs-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>, +- <&gpx2 4 GPIO_ACTIVE_HIGH>, +- <&gpx2 5 GPIO_ACTIVE_HIGH>; +- +- s5m8767,pmic-buck-ds-gpios = <&gpm3 5 GPIO_ACTIVE_HIGH>, +- <&gpm3 6 GPIO_ACTIVE_HIGH>, +- <&gpm3 7 GPIO_ACTIVE_HIGH>; +- +- s5m8767,pmic-buck2-dvs-voltage = <1250000>, <1200000>, +- <1200000>, <1200000>, +- <1200000>, <1200000>, +- <1200000>, <1200000>; +- +- s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, +- <1100000>, <1100000>, +- <1100000>, <1100000>, +- <1100000>, <1100000>; +- +- s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, +- <1200000>, <1200000>, +- <1200000>, <1200000>, +- <1200000>, <1200000>; +- wakeup-source; +- +- s5m8767_osc: clocks { +- compatible = "samsung,s5m8767-clk"; +- #clock-cells = <1>; +- clock-output-names = "s5m8767_ap", "s5m8767_cp", +- "s5m8767_bt"; +- }; +- +- regulators { +- ldo1_reg: LDO1 { +- regulator-name = "VDD_ALIVE"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "VDDQ_M12"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "VDDIOAP_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "VDDQ_PRE"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "VDD18_2M"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "VDD10_MPLL"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "VDD10_XPLL"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "VDD10_MIPI"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "VDD33_LCD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "VDD18_MIPI"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "VDD18_ABB1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "VDD33_UOTG"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "VDDIOPERI_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "VDD18_ABB02"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "VDD10_USH"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "VDD18_HSIC"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "VDDIOAP_MMC012_28"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo18_reg: LDO18 { +- regulator-name = "VDDIOPERI_28"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo19_reg: LDO19 { +- regulator-name = "DVDD25"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo20_reg: LDO20 { +- regulator-name = "VDD28_CAM"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo21_reg: LDO21 { +- regulator-name = "VDD28_AF"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo22_reg: LDO22 { +- regulator-name = "VDDA28_2M"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo23_reg: LDO23 { +- regulator-name = "VDD28_TF"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo24_reg: LDO24 { +- regulator-name = "VDD33_A31"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo25_reg: LDO25 { +- regulator-name = "VDD18_CAM"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo26_reg: LDO26 { +- regulator-name = "VDD18_A31"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo27_reg: LDO27 { +- regulator-name = "GPS_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- ldo28_reg: LDO28 { +- regulator-name = "DVDD12"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "VDD_MIF"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "VDD_ARM"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "VDD_INT"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "VDD_G3D"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "VDD_M12"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- buck6_reg: BUCK6 { +- regulator-name = "VDD12_5M"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- +- buck9_reg: BUCK9 { +- regulator-name = "VDDF28_EMMC"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; /* Normal Mode */ +- }; +- }; +- }; +-}; +- +-&keypad { +- samsung,keypad-num-rows = <3>; +- samsung,keypad-num-columns = <2>; +- linux,keypad-no-autorepeat; +- wakeup-source; +- pinctrl-0 = <&keypad_rows &keypad_cols>; +- pinctrl-names = "default"; +- status = "okay"; +- +- key-home { +- keypad,row = <0>; +- keypad,column = <0>; +- linux,code = ; +- }; +- +- key-down { +- keypad,row = <0>; +- keypad,column = <1>; +- linux,code = ; +- }; +- +- key-up { +- keypad,row = <1>; +- keypad,column = <0>; +- linux,code = ; +- }; +- +- key-menu { +- keypad,row = <1>; +- keypad,column = <1>; +- linux,code = ; +- }; +- +- key-back { +- keypad,row = <2>; +- keypad,column = <0>; +- linux,code = ; +- }; +- +- key-enter { +- keypad,row = <2>; +- keypad,column = <1>; +- linux,code = ; +- }; +-}; +- +-&mshc_0 { +- pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; +- pinctrl-names = "default"; +- status = "okay"; +- +- broken-cd; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- bus-width = <8>; +- cap-mmc-highspeed; +-}; +- +-&pinctrl_1 { +- keypad_rows: keypad-rows { +- samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- keypad_cols: keypad-cols { +- samsung,pins = "gpx1-0", "gpx1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&sdhci_2 { +- bus-width = <4>; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; +- pinctrl-names = "default"; +- vmmc-supply = <&mmc_reg>; +- status = "okay"; +-}; +- +-&serial_0 { +- status = "okay"; +-}; +- +-&serial_1 { +- status = "okay"; +-}; +- +-&serial_2 { +- status = "okay"; +-}; +- +-&serial_3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-p4note-n8010.dts b/scripts/dtc/include-prefixes/arm/exynos4412-p4note-n8010.dts +deleted file mode 100644 +index 9f559425bd2c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-p4note-n8010.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Galaxy Note 10.1 - N801x (wifi only version) +- * +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-/dts-v1/; +-#include "exynos4412-p4note.dtsi" +- +-/ { +- model = "Samsung Galaxy Note 10.1 (GT-N8010/N8013) based on Exynos4412"; +- compatible = "samsung,n8010", "samsung,p4note", "samsung,exynos4412", "samsung,exynos4"; +- +- /* this is the base variant without any kind of modem */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-p4note.dtsi b/scripts/dtc/include-prefixes/arm/exynos4412-p4note.dtsi +deleted file mode 100644 +index 22c3086e0076..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-p4note.dtsi ++++ /dev/null +@@ -1,1133 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos4412 based p4note device family base DT. +- * Based on exynos4412-midas.dtsi. +- * +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-/dts-v1/; +-#include "exynos4412.dtsi" +-#include "exynos4412-ppmu-common.dtsi" +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "samsung,p4note", "samsung,exynos4412", "samsung,exynos4"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x80000000>; +- }; +- +- chosen { +- stdout-path = &serial_2; +- }; +- +- firmware@204f000 { +- compatible = "samsung,secure-firmware"; +- reg = <0x0204F000 0x1000>; +- }; +- +- fixed-rate-clocks { +- xxti { +- compatible = "samsung,clock-xxti"; +- clock-frequency = <0>; +- }; +- +- xusbxti { +- compatible = "samsung,clock-xusbxti"; +- clock-frequency = <24000000>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys>; +- +- key-down { +- gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "volume down"; +- debounce-interval = <10>; +- }; +- +- key-up { +- gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "volume up"; +- debounce-interval = <10>; +- }; +- +- key-power { +- gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "power"; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- voltage-regulator-1 { +- compatible = "regulator-fixed"; +- regulator-name = "TSP_LDO1"; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsp_reg_gpio_1>; +- gpios = <&gpm4 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- voltage-regulator-2 { +- compatible = "regulator-fixed"; +- regulator-name = "TSP_LDO2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsp_reg_gpio_2>; +- gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- voltage-regulator-3 { +- compatible = "regulator-fixed"; +- regulator-name = "TSP_LDO3"; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsp_reg_gpio_3>; +- gpios = <&gpb 7 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <20000>; +- enable-active-high; +- regulator-always-on; +- }; +- +- wlan_pwrseq: sdhci3-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpm3 5 GPIO_ACTIVE_LOW>; +- pinctrl-0 = <&wifi_reset>; +- pinctrl-names = "default"; +- clocks = <&max77686 MAX77686_CLK_PMIC>; +- clock-names = "ext_clock"; +- }; +- +- i2c-gpio-1 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpy2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpy2 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- magnetometer@c { +- compatible = "asahi-kasei,ak8975"; +- reg = <0x0c>; +- pinctrl-0 = <&ak8975_irq>; +- pinctrl-names = "default"; +- interrupt-parent = <&gpm4>; +- interrupts = <7 IRQ_TYPE_EDGE_RISING>; +- }; +- }; +- +- i2c-gpio-2 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpy0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpy0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fuel-gauge@36 { +- compatible = "maxim,max17042"; +- reg = <0x36>; +- pinctrl-0 = <&fuel_alert_irq>; +- pinctrl-names = "default"; +- interrupt-parent = <&gpx2>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- maxim,rsns-microohm = <10000>; +- maxim,over-heat-temp = <600>; +- maxim,over-volt = <4300>; +- }; +- }; +- +- i2c-gpio-3 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpm4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpm4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <5>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- adc@41 { +- compatible = "st,stmpe811"; +- reg = <0x41>; +- pinctrl-0 = <&stmpe_adc_irq>; +- pinctrl-names = "default"; +- interrupt-parent = <&gpx0>; +- interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- irq-trigger = <0x1>; +- st,adc-freq = <3>; +- st,mod-12b = <1>; +- st,ref-sel = <0>; +- st,sample-time = <3>; +- +- stmpe_adc { +- compatible = "st,stmpe-adc"; +- #io-channel-cells = <1>; +- st,norequest-mask = <0x2F>; +- }; +- }; +- }; +-}; +- +-&adc { +- vdd-supply = <&ldo3_reg>; +- /* not verified */ +- status = "okay"; +-}; +- +-&bus_dmc { +- devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; +- vdd-supply = <&buck1_reg>; +- status = "okay"; +-}; +- +-&bus_acp { +- devfreq = <&bus_dmc>; +- status = "okay"; +-}; +- +-&bus_c2c { +- devfreq = <&bus_dmc>; +- status = "okay"; +-}; +- +-&bus_leftbus { +- devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; +- vdd-supply = <&buck3_reg>; +- status = "okay"; +-}; +- +-&bus_rightbus { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_display { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_fsys { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_peri { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&bus_mfc { +- devfreq = <&bus_leftbus>; +- status = "okay"; +-}; +- +-&cpu0 { +- cpu0-supply = <&buck2_reg>; +-}; +- +-&cpu_thermal { +- cooling-maps { +- map0 { +- /* Corresponds to 800MHz at freq_table */ +- cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, +- <&cpu2 7 7>, <&cpu3 7 7>; +- }; +- map1 { +- /* Corresponds to 200MHz at freq_table */ +- cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, +- <&cpu2 13 13>, <&cpu3 13 13>; +- }; +- }; +-}; +- +-&exynos_usbphy { +- status = "okay"; +-}; +- +-&fimd { +- pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; +- pinctrl-names = "default"; +- status = "okay"; +- +- display-timings { +- timing0 { +- clock-frequency = <66666666>; +- hactive = <1280>; +- vactive = <800>; +- hfront-porch = <18>; +- hback-porch = <36>; +- hsync-len = <16>; +- vback-porch = <16>; +- vfront-porch = <4>; +- vsync-len = <3>; +- hsync-active = <1>; +- }; +- }; +-}; +- +-&gpu { +- mali-supply = <&buck4_reg>; +- status = "okay"; +-}; +- +-&hsotg { +- vusb_a-supply = <&ldo12_reg>; +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&i2c_3 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <400000>; +- pinctrl-0 = <&i2c3_bus>; +- pinctrl-names = "default"; +- status = "okay"; +- +- touchscreen@4a { +- compatible = "atmel,maxtouch"; +- reg = <0x4a>; +- pinctrl-0 = <&tsp_rst &tsp_irq>; +- pinctrl-names = "default"; +- interrupt-parent = <&gpm2>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpm0 4 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&i2c_7 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-slave-addr = <0x10>; +- samsung,i2c-max-bus-freq = <400000>; +- pinctrl-0 = <&i2c7_bus>; +- pinctrl-names = "default"; +- status = "okay"; +- +- max77686: pmic@9 { +- compatible = "maxim,max77686"; +- interrupt-parent = <&gpx0>; +- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-0 = <&max77686_irq>; +- pinctrl-names = "default"; +- wakeup-source; +- reg = <0x09>; +- #clock-cells = <1>; +- +- voltage-regulators { +- ldo1_reg: LDO1 { +- regulator-name = "ldo1"; +- regulator-always-on; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "ldo2"; +- regulator-always-on; +- }; +- +- /* WM8994 audio */ +- ldo3_reg: LDO3 { +- regulator-name = "VCC_1.8V_AP"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "ldo4"; +- regulator-always-on; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "VCC_1.8V_IO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "ldo6"; +- regulator-always-on; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "ldo7"; +- regulator-always-on; +- }; +- +- /* CSI IP block */ +- ldo8_reg: LDO8 { +- regulator-name = "VMIPI_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- /* IR LED on/off */ +- ldo9_reg: LDO9 { +- regulator-name = "VLED_IC_1.9V"; +- regulator-min-microvolt = <1950000>; +- regulator-max-microvolt = <1950000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- /* CSI IP block */ +- ldo10_reg: LDO10 { +- regulator-name = "VMIPI_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "VABB1_1.9V"; +- regulator-min-microvolt = <1950000>; +- regulator-max-microvolt = <1950000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- /* USB OTG */ +- ldo12_reg: LDO12 { +- regulator-name = "VUOTG_3.0V"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- /* not connected */ +- ldo13_reg: LDO13 { +- regulator-name = "ldo13"; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "VABB2_1.9V"; +- regulator-min-microvolt = <1950000>; +- regulator-max-microvolt = <1950000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "ldo15"; +- regulator-always-on; +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "ldo16"; +- regulator-always-on; +- }; +- +- /* not connected */ +- ldo17_reg: LDO17 { +- regulator-name = "ldo17"; +- }; +- +- /* Camera ISX012 */ +- ldo18_reg: LDO18 { +- regulator-name = "CAM_IO_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- /* Camera S5K6A3 */ +- ldo19_reg: LDO19 { +- regulator-name = "VT_CORE_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- /* not connected */ +- ldo20_reg: LDO20 { +- regulator-name = "ldo20"; +- }; +- +- /* MMC2 */ +- ldo21_reg: LDO21 { +- regulator-name = "VTF_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>; +- }; +- +- /* not connected */ +- ldo22_reg: LDO22 { +- regulator-name = "ldo22"; +- }; +- +- /* ADC */ +- ldo23_reg: LDO23 { +- regulator-name = "VDD_ADC_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- /* Camera S5K6A3 */ +- ldo24_reg: LDO24 { +- regulator-name = "CAM_A2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo25_reg: LDO25 { +- regulator-name = "VLED_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- /* Camera ISX012 */ +- ldo26_reg: LDO26 { +- regulator-name = "3MP_AF_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "VDD_MIF"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1050000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "VDD_ARM"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "VDD_INT"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "VDD_G3D"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1075000>; +- regulator-boot-on; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "buck5"; +- regulator-always-on; +- }; +- +- buck6_reg: BUCK6 { +- regulator-name = "buck6"; +- regulator-always-on; +- }; +- +- buck7_reg: BUCK7 { +- regulator-name = "buck7"; +- regulator-always-on; +- }; +- +- /* not connected */ +- buck8_reg: BUCK8 { +- regulator-name = "buck8"; +- }; +- +- buck9_reg: BUCK9 { +- regulator-name = "3MP_CORE_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +-}; +- +-&mshc_0 { +- broken-cd; +- non-removable; +- card-detect-delay = <200>; +- clock-frequency = <400000000>; +- samsung,dw-mshc-ciu-div = <0>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; +- pinctrl-names = "default"; +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- status = "okay"; +-}; +- +-&pinctrl_0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sleep0>; +- +- tsp_reg_gpio_2: tsp-reg-gpio-2 { +- samsung,pins = "gpb-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- tsp_reg_gpio_3: tsp-reg-gpio-3 { +- samsung,pins = "gpb-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- sleep0: sleep-states { +- PIN_SLP(gpa0-0, INPUT, NONE); +- PIN_SLP(gpa0-1, OUT0, NONE); +- PIN_SLP(gpa0-2, INPUT, NONE); +- PIN_SLP(gpa0-3, INPUT, UP); +- PIN_SLP(gpa0-4, INPUT, NONE); +- PIN_SLP(gpa0-5, INPUT, DOWN); +- PIN_SLP(gpa0-6, INPUT, DOWN); +- PIN_SLP(gpa0-7, INPUT, UP); +- +- PIN_SLP(gpa1-0, INPUT, DOWN); +- PIN_SLP(gpa1-1, INPUT, DOWN); +- PIN_SLP(gpa1-2, INPUT, DOWN); +- PIN_SLP(gpa1-3, INPUT, DOWN); +- PIN_SLP(gpa1-4, INPUT, DOWN); +- PIN_SLP(gpa1-5, INPUT, DOWN); +- +- PIN_SLP(gpb-0, INPUT, NONE); +- PIN_SLP(gpb-1, INPUT, NONE); +- PIN_SLP(gpb-2, INPUT, NONE); +- PIN_SLP(gpb-3, INPUT, NONE); +- PIN_SLP(gpb-4, INPUT, DOWN); +- PIN_SLP(gpb-5, INPUT, DOWN); +- PIN_SLP(gpb-6, INPUT, DOWN); +- PIN_SLP(gpb-7, INPUT, DOWN); +- +- PIN_SLP(gpc0-0, INPUT, DOWN); +- PIN_SLP(gpc0-1, INPUT, DOWN); +- PIN_SLP(gpc0-2, INPUT, DOWN); +- PIN_SLP(gpc0-3, INPUT, DOWN); +- PIN_SLP(gpc0-4, INPUT, DOWN); +- +- PIN_SLP(gpc1-0, INPUT, UP); +- PIN_SLP(gpc1-1, PREV, NONE); +- PIN_SLP(gpc1-2, INPUT, UP); +- PIN_SLP(gpc1-3, INPUT, UP); +- PIN_SLP(gpc1-4, INPUT, UP); +- +- PIN_SLP(gpd0-0, INPUT, DOWN); +- PIN_SLP(gpd0-1, OUT0, NONE); +- PIN_SLP(gpd0-2, INPUT, NONE); +- PIN_SLP(gpd0-3, INPUT, NONE); +- +- PIN_SLP(gpd1-0, INPUT, DOWN); +- PIN_SLP(gpd1-1, INPUT, DOWN); +- PIN_SLP(gpd1-2, INPUT, NONE); +- PIN_SLP(gpd1-3, INPUT, NONE); +- +- PIN_SLP(gpf0-0, OUT0, NONE); +- PIN_SLP(gpf0-1, OUT0, NONE); +- PIN_SLP(gpf0-2, OUT0, NONE); +- PIN_SLP(gpf0-3, OUT0, NONE); +- PIN_SLP(gpf0-4, OUT0, NONE); +- PIN_SLP(gpf0-5, OUT0, NONE); +- PIN_SLP(gpf0-6, OUT0, NONE); +- PIN_SLP(gpf0-7, OUT0, NONE); +- +- PIN_SLP(gpf1-0, OUT0, NONE); +- PIN_SLP(gpf1-1, OUT0, NONE); +- PIN_SLP(gpf1-2, OUT0, NONE); +- PIN_SLP(gpf1-3, OUT0, NONE); +- PIN_SLP(gpf1-4, OUT0, NONE); +- PIN_SLP(gpf1-5, OUT0, NONE); +- PIN_SLP(gpf1-6, OUT0, NONE); +- PIN_SLP(gpf1-7, OUT0, NONE); +- +- PIN_SLP(gpf2-0, OUT0, NONE); +- PIN_SLP(gpf2-1, OUT0, NONE); +- PIN_SLP(gpf2-2, OUT0, NONE); +- PIN_SLP(gpf2-3, OUT0, NONE); +- PIN_SLP(gpf2-4, OUT0, NONE); +- PIN_SLP(gpf2-5, OUT0, NONE); +- PIN_SLP(gpf2-6, OUT0, NONE); +- PIN_SLP(gpf2-7, OUT0, NONE); +- +- PIN_SLP(gpf3-0, OUT0, NONE); +- PIN_SLP(gpf3-1, OUT0, NONE); +- PIN_SLP(gpf3-2, OUT0, NONE); +- PIN_SLP(gpf3-3, OUT0, NONE); +- PIN_SLP(gpf3-4, OUT0, NONE); +- PIN_SLP(gpf3-5, OUT0, NONE); +- +- PIN_SLP(gpj0-0, INPUT, DOWN); +- PIN_SLP(gpj0-1, INPUT, DOWN); +- PIN_SLP(gpj0-2, INPUT, DOWN); +- PIN_SLP(gpj0-3, PREV, NONE); +- PIN_SLP(gpj0-4, PREV, NONE); +- PIN_SLP(gpj0-5, OUT0, NONE); +- PIN_SLP(gpj0-6, OUT0, NONE); +- PIN_SLP(gpj0-7, OUT0, NONE); +- +- PIN_SLP(gpj1-0, OUT0, NONE); +- PIN_SLP(gpj1-1, INPUT, DOWN); +- PIN_SLP(gpj1-2, PREV, NONE); +- PIN_SLP(gpj1-3, OUT0, NONE); +- }; +-}; +- +-&pinctrl_1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sleep1>; +- +- sd3_wifi: sd3-wifi { +- samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- bt_shutdown: bt-shutdown { +- samsung,pins = "gpl0-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- uart_sel: uart-sel { +- samsung,pins = "gpl2-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-val = <1>; +- /* 0 = CP, 1 = AP (serial output) */ +- }; +- +- tsp_rst: tsp-rst { +- samsung,pins = "gpm0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- tsp_irq: tsp-irq { +- samsung,pins = "gpm2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- wifi_reset: wifi-reset { +- samsung,pins = "gpm3-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- tsp_reg_gpio_1: tsp-reg-gpio-1 { +- samsung,pins = "gpm4-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- ak8975_irq: ak8975-irq { +- samsung,pins = "gpm4-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- stmpe_adc_irq: stmpe-adc-irq { +- samsung,pins = "gpx0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- max77686_irq: max77686-irq { +- samsung,pins = "gpx0-7"; +- samsung,pin-pud = ; +- }; +- +- gpio_keys: gpio-keys { +- samsung,pins = "gpx2-2", "gpx2-7", "gpx3-3"; +- samsung,pin-pud = ; +- }; +- +- fuel_alert_irq: fuel-alert-irq { +- samsung,pins = "gpx2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- wifi_host_wake: wifi-host-wake { +- samsung,pins = "gpx2-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- bt_host_wakeup: bt-host-wakeup { +- samsung,pins = "gpx2-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- bt_device_wakeup: bt-device-wakeup { +- samsung,pins = "gpx3-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- sdhci2_cd: sdhci2-cd { +- samsung,pins = "gpx3-4"; +- samsung,pin-pud = ; +- }; +- +- sleep1: sleep-states { +- PIN_SLP(gpk0-0, PREV, NONE); +- PIN_SLP(gpk0-1, PREV, NONE); +- PIN_SLP(gpk0-2, PREV, NONE); +- PIN_SLP(gpk0-3, PREV, NONE); +- PIN_SLP(gpk0-4, PREV, NONE); +- PIN_SLP(gpk0-5, PREV, NONE); +- PIN_SLP(gpk0-6, PREV, NONE); +- +- PIN_SLP(gpk1-0, INPUT, DOWN); +- PIN_SLP(gpk1-1, INPUT, DOWN); +- PIN_SLP(gpk1-2, INPUT, DOWN); +- PIN_SLP(gpk1-3, PREV, NONE); +- PIN_SLP(gpk1-4, PREV, NONE); +- PIN_SLP(gpk1-5, PREV, NONE); +- PIN_SLP(gpk1-6, PREV, NONE); +- +- PIN_SLP(gpk2-0, INPUT, DOWN); +- PIN_SLP(gpk2-1, INPUT, DOWN); +- PIN_SLP(gpk2-2, INPUT, DOWN); +- PIN_SLP(gpk2-3, INPUT, DOWN); +- PIN_SLP(gpk2-4, INPUT, DOWN); +- PIN_SLP(gpk2-5, INPUT, DOWN); +- PIN_SLP(gpk2-6, INPUT, DOWN); +- +- PIN_SLP(gpk3-0, OUT0, NONE); +- PIN_SLP(gpk3-1, INPUT, NONE); +- PIN_SLP(gpk3-2, INPUT, DOWN); +- PIN_SLP(gpk3-3, INPUT, NONE); +- PIN_SLP(gpk3-4, INPUT, NONE); +- PIN_SLP(gpk3-5, INPUT, NONE); +- PIN_SLP(gpk3-6, INPUT, NONE); +- +- PIN_SLP(gpl0-0, OUT0, NONE); +- PIN_SLP(gpl0-1, INPUT, NONE); +- PIN_SLP(gpl0-2, INPUT, NONE); +- PIN_SLP(gpl0-3, INPUT, DOWN); +- PIN_SLP(gpl0-4, PREV, NONE); +- PIN_SLP(gpl0-6, PREV, NONE); +- +- PIN_SLP(gpl1-0, OUT0, NONE); +- PIN_SLP(gpl1-1, OUT0, NONE); +- +- PIN_SLP(gpl2-0, INPUT, DOWN); +- PIN_SLP(gpl2-1, INPUT, DOWN); +- PIN_SLP(gpl2-2, INPUT, DOWN); +- PIN_SLP(gpl2-3, INPUT, DOWN); +- PIN_SLP(gpl2-4, OUT0, NONE); +- PIN_SLP(gpl2-5, INPUT, DOWN); +- PIN_SLP(gpl2-6, PREV, NONE); +- PIN_SLP(gpl2-7, PREV, NONE); +- +- PIN_SLP(gpm0-0, PREV, NONE); +- PIN_SLP(gpm0-1, OUT0, NONE); +- PIN_SLP(gpm0-2, INPUT, DOWN); +- PIN_SLP(gpm0-3, INPUT, NONE); +- PIN_SLP(gpm0-4, OUT0, NONE); +- PIN_SLP(gpm0-5, OUT0, NONE); +- PIN_SLP(gpm0-6, INPUT, DOWN); +- PIN_SLP(gpm0-7, OUT0, NONE); +- +- PIN_SLP(gpm1-0, INPUT, NONE); +- PIN_SLP(gpm1-1, INPUT, NONE); +- PIN_SLP(gpm1-2, INPUT, NONE); +- PIN_SLP(gpm1-3, INPUT, NONE); +- PIN_SLP(gpm1-4, INPUT, NONE); +- PIN_SLP(gpm1-5, INPUT, NONE); +- PIN_SLP(gpm1-6, INPUT, DOWN); +- +- PIN_SLP(gpm2-0, INPUT, NONE); +- PIN_SLP(gpm2-1, INPUT, NONE); +- PIN_SLP(gpm2-2, OUT0, NONE); +- PIN_SLP(gpm2-3, OUT0, DOWN); +- PIN_SLP(gpm2-4, INPUT, DOWN); +- +- PIN_SLP(gpm3-0, PREV, NONE); +- PIN_SLP(gpm3-1, PREV, NONE); +- PIN_SLP(gpm3-2, PREV, NONE); +- PIN_SLP(gpm3-3, OUT1, NONE); +- PIN_SLP(gpm3-4, OUT0, DOWN); +- PIN_SLP(gpm3-5, PREV, NONE); +- PIN_SLP(gpm3-6, PREV, NONE); +- PIN_SLP(gpm3-7, OUT0, NONE); +- +- PIN_SLP(gpm4-0, INPUT, NONE); +- PIN_SLP(gpm4-1, INPUT, NONE); +- PIN_SLP(gpm4-2, INPUT, DOWN); +- PIN_SLP(gpm4-3, INPUT, DOWN); +- PIN_SLP(gpm4-4, PREV, NONE); +- PIN_SLP(gpm4-5, OUT0, NONE); +- PIN_SLP(gpm4-6, OUT0, NONE); +- PIN_SLP(gpm4-7, INPUT, DOWN); +- +- PIN_SLP(gpy0-0, INPUT, DOWN); +- PIN_SLP(gpy0-1, INPUT, DOWN); +- PIN_SLP(gpy0-2, INPUT, NONE); +- PIN_SLP(gpy0-3, INPUT, NONE); +- PIN_SLP(gpy0-4, INPUT, NONE); +- PIN_SLP(gpy0-5, INPUT, NONE); +- +- PIN_SLP(gpy1-0, INPUT, DOWN); +- PIN_SLP(gpy1-1, INPUT, DOWN); +- PIN_SLP(gpy1-2, INPUT, DOWN); +- PIN_SLP(gpy1-3, INPUT, DOWN); +- +- PIN_SLP(gpy2-0, PREV, NONE); +- PIN_SLP(gpy2-1, INPUT, DOWN); +- PIN_SLP(gpy2-2, INPUT, NONE); +- PIN_SLP(gpy2-3, INPUT, NONE); +- PIN_SLP(gpy2-4, INPUT, NONE); +- PIN_SLP(gpy2-5, INPUT, NONE); +- +- PIN_SLP(gpy3-0, INPUT, DOWN); +- PIN_SLP(gpy3-1, INPUT, DOWN); +- PIN_SLP(gpy3-2, INPUT, DOWN); +- PIN_SLP(gpy3-3, INPUT, DOWN); +- PIN_SLP(gpy3-4, INPUT, DOWN); +- PIN_SLP(gpy3-5, INPUT, DOWN); +- PIN_SLP(gpy3-6, INPUT, DOWN); +- PIN_SLP(gpy3-7, INPUT, DOWN); +- +- PIN_SLP(gpy4-0, INPUT, DOWN); +- PIN_SLP(gpy4-1, INPUT, DOWN); +- PIN_SLP(gpy4-2, INPUT, DOWN); +- PIN_SLP(gpy4-3, INPUT, DOWN); +- PIN_SLP(gpy4-4, INPUT, DOWN); +- PIN_SLP(gpy4-5, INPUT, DOWN); +- PIN_SLP(gpy4-6, INPUT, DOWN); +- PIN_SLP(gpy4-7, INPUT, DOWN); +- +- PIN_SLP(gpy5-0, INPUT, DOWN); +- PIN_SLP(gpy5-1, INPUT, DOWN); +- PIN_SLP(gpy5-2, INPUT, DOWN); +- PIN_SLP(gpy5-3, INPUT, DOWN); +- PIN_SLP(gpy5-4, INPUT, DOWN); +- PIN_SLP(gpy5-5, INPUT, DOWN); +- PIN_SLP(gpy5-6, INPUT, DOWN); +- PIN_SLP(gpy5-7, INPUT, DOWN); +- +- PIN_SLP(gpy6-0, INPUT, DOWN); +- PIN_SLP(gpy6-1, INPUT, DOWN); +- PIN_SLP(gpy6-2, INPUT, DOWN); +- PIN_SLP(gpy6-3, INPUT, DOWN); +- PIN_SLP(gpy6-4, INPUT, DOWN); +- PIN_SLP(gpy6-5, INPUT, DOWN); +- PIN_SLP(gpy6-6, INPUT, DOWN); +- PIN_SLP(gpy6-7, INPUT, DOWN); +- }; +-}; +- +-&pinctrl_2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sleep2>; +- +- sleep2: sleep-states { +- PIN_SLP(gpz-0, INPUT, DOWN); +- PIN_SLP(gpz-1, INPUT, DOWN); +- PIN_SLP(gpz-2, INPUT, DOWN); +- PIN_SLP(gpz-3, INPUT, DOWN); +- PIN_SLP(gpz-4, INPUT, DOWN); +- PIN_SLP(gpz-5, INPUT, DOWN); +- PIN_SLP(gpz-6, INPUT, DOWN); +- }; +-}; +- +-&pinctrl_3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sleep3>; +- +- sleep3: sleep-states { +- PIN_SLP(gpv0-0, INPUT, DOWN); +- PIN_SLP(gpv0-1, INPUT, DOWN); +- PIN_SLP(gpv0-2, INPUT, DOWN); +- PIN_SLP(gpv0-3, INPUT, DOWN); +- PIN_SLP(gpv0-4, INPUT, DOWN); +- PIN_SLP(gpv0-5, INPUT, DOWN); +- PIN_SLP(gpv0-6, INPUT, DOWN); +- PIN_SLP(gpv0-7, INPUT, DOWN); +- +- PIN_SLP(gpv1-0, INPUT, DOWN); +- PIN_SLP(gpv1-1, INPUT, DOWN); +- PIN_SLP(gpv1-2, INPUT, DOWN); +- PIN_SLP(gpv1-3, INPUT, DOWN); +- PIN_SLP(gpv1-4, INPUT, DOWN); +- PIN_SLP(gpv1-5, INPUT, DOWN); +- PIN_SLP(gpv1-6, INPUT, DOWN); +- PIN_SLP(gpv1-7, INPUT, DOWN); +- +- PIN_SLP(gpv2-0, INPUT, DOWN); +- PIN_SLP(gpv2-1, INPUT, DOWN); +- PIN_SLP(gpv2-2, INPUT, DOWN); +- PIN_SLP(gpv2-3, INPUT, DOWN); +- PIN_SLP(gpv2-4, INPUT, DOWN); +- PIN_SLP(gpv2-5, INPUT, DOWN); +- PIN_SLP(gpv2-6, INPUT, DOWN); +- PIN_SLP(gpv2-7, INPUT, DOWN); +- +- PIN_SLP(gpv3-0, INPUT, DOWN); +- PIN_SLP(gpv3-1, INPUT, DOWN); +- PIN_SLP(gpv3-2, INPUT, DOWN); +- PIN_SLP(gpv3-3, INPUT, DOWN); +- PIN_SLP(gpv3-4, INPUT, DOWN); +- PIN_SLP(gpv3-5, INPUT, DOWN); +- PIN_SLP(gpv3-6, INPUT, DOWN); +- PIN_SLP(gpv3-7, INPUT, DOWN); +- +- PIN_SLP(gpv4-0, INPUT, DOWN); +- PIN_SLP(gpv4-1, INPUT, DOWN); +- }; +-}; +- +-&pmu_system_controller { +- assigned-clocks = <&pmu_system_controller 0>; +- assigned-clock-parents = <&clock CLK_XUSBXTI>; +-}; +- +-&rtc { +- clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; +- clock-names = "rtc", "rtc_src"; +- status = "okay"; +-}; +- +-&sdhci_2 { +- bus-width = <4>; +- cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sdhci2_cd>; +- pinctrl-names = "default"; +- vmmc-supply = <&ldo21_reg>; +- status = "okay"; +-}; +- +-&sdhci_3 { +- #address-cells = <1>; +- #size-cells = <0>; +- non-removable; +- bus-width = <4>; +- mmc-pwrseq = <&wlan_pwrseq>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_wifi>; +- status = "okay"; +- +- wifi@1 { +- compatible = "brcm,bcm4329-fmac"; +- reg = <0x1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_host_wake>; +- interrupt-parent = <&gpx2>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "host-wake"; +- }; +-}; +- +-&serial_0 { +- pinctrl-0 = <&uart0_data &uart0_fctl>; +- pinctrl-names = "default"; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm4330-bt"; +- pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; +- pinctrl-names = "default"; +- +- max-speed = <2000000>; +- shutdown-gpios = <&gpl0 6 GPIO_ACTIVE_HIGH>; +- device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; +- clocks = <&max77686 MAX77686_CLK_PMIC>; +- clock-names = "lpo"; +- }; +-}; +- +-&serial_2 { +- pinctrl-0 = <&uart_sel>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&tmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/exynos4412-pinctrl.dtsi +deleted file mode 100644 +index d7d5fdc230d8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-pinctrl.dtsi ++++ /dev/null +@@ -1,979 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos4412 SoCs pin-mux and pin-config device tree source +- * +- * Copyright (c) 2012 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Samsung's Exynos4412 SoCs pin-mux and pin-config optiosn are listed as device +- * tree nodes are listed in this file. +- */ +- +-#include +- +-#define PIN_SLP(_pin, _mode, _pull) \ +- _pin { \ +- samsung,pins = #_pin; \ +- samsung,pin-con-pdn = ; \ +- samsung,pin-pud-pdn = ; \ +- } +- +-&pinctrl_0 { +- gpa0: gpa0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpa1: gpa1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb: gpb { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc0: gpc0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc1: gpc1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd0: gpd0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd1: gpd1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf0: gpf0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf1: gpf1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf2: gpf2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf3: gpf3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpj0: gpj0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpj1: gpj1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- uart0_data: uart0-data { +- samsung,pins = "gpa0-0", "gpa0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart0_fctl: uart0-fctl { +- samsung,pins = "gpa0-2", "gpa0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart1_data: uart1-data { +- samsung,pins = "gpa0-4", "gpa0-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart1_fctl: uart1-fctl { +- samsung,pins = "gpa0-6", "gpa0-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c2_bus: i2c2-bus { +- samsung,pins = "gpa0-6", "gpa0-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart2_data: uart2-data { +- samsung,pins = "gpa1-0", "gpa1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart2_fctl: uart2-fctl { +- samsung,pins = "gpa1-2", "gpa1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart_audio_a: uart-audio-a { +- samsung,pins = "gpa1-0", "gpa1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c3_bus: i2c3-bus { +- samsung,pins = "gpa1-2", "gpa1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart3_data: uart3-data { +- samsung,pins = "gpa1-4", "gpa1-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart_audio_b: uart-audio-b { +- samsung,pins = "gpa1-4", "gpa1-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi0_bus: spi0-bus { +- samsung,pins = "gpb-0", "gpb-2", "gpb-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c4_bus: i2c4-bus { +- samsung,pins = "gpb-0", "gpb-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi1_bus: spi1-bus { +- samsung,pins = "gpb-4", "gpb-6", "gpb-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c5_bus: i2c5-bus { +- samsung,pins = "gpb-2", "gpb-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2s1_bus: i2s1-bus { +- samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", +- "gpc0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pcm1_bus: pcm1-bus { +- samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", +- "gpc0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- ac97_bus: ac97-bus { +- samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", +- "gpc0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2s2_bus: i2s2-bus { +- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", +- "gpc1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pcm2_bus: pcm2-bus { +- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", +- "gpc1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spdif_bus: spdif-bus { +- samsung,pins = "gpc1-0", "gpc1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c6_bus: i2c6-bus { +- samsung,pins = "gpc1-3", "gpc1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi2_bus: spi2-bus { +- samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm0_out: pwm0-out { +- samsung,pins = "gpd0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm1_out: pwm1-out { +- samsung,pins = "gpd0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lcd_ctrl: lcd-ctrl { +- samsung,pins = "gpd0-0", "gpd0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c7_bus: i2c7-bus { +- samsung,pins = "gpd0-2", "gpd0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm2_out: pwm2-out { +- samsung,pins = "gpd0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm3_out: pwm3-out { +- samsung,pins = "gpd0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c0_bus: i2c0-bus { +- samsung,pins = "gpd1-0", "gpd1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- mipi0_clk: mipi0-clk { +- samsung,pins = "gpd1-0", "gpd1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c1_bus: i2c1-bus { +- samsung,pins = "gpd1-2", "gpd1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- mipi1_clk: mipi1-clk { +- samsung,pins = "gpd1-2", "gpd1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lcd_clk: lcd-clk { +- samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lcd_data16: lcd-data-width16 { +- samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", +- "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", +- "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", +- "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lcd_data18: lcd-data-width18 { +- samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", +- "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", +- "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", +- "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", +- "gpf3-2", "gpf3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lcd_data24: lcd-data-width24 { +- samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", +- "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", +- "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", +- "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", +- "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", +- "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lcd_ldi: lcd-ldi { +- samsung,pins = "gpf3-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_port_a_io: cam-port-a-io { +- samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", +- "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", +- "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_port_a_clk_active: cam-port-a-clk-active { +- samsung,pins = "gpj1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_port_a_clk_idle: cam-port-a-clk-idle { +- samsung,pins = "gpj1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_1 { +- gpk0: gpk0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpk1: gpk1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpk2: gpk2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpk3: gpk3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpl0: gpl0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpl1: gpl1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpl2: gpl2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpm0: gpm0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpm1: gpm1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpm2: gpm2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpm3: gpm3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpm4: gpm4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpy0: gpy0 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy1: gpy1 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy2: gpy2 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy3: gpy3 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy4: gpy4 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy5: gpy5 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy6: gpy6 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpx0: gpx0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- #interrupt-cells = <2>; +- }; +- +- gpx1: gpx1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- #interrupt-cells = <2>; +- }; +- +- gpx2: gpx2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpx3: gpx3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- sd0_clk: sd0-clk { +- samsung,pins = "gpk0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_cmd: sd0-cmd { +- samsung,pins = "gpk0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_cd: sd0-cd { +- samsung,pins = "gpk0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus1: sd0-bus-width1 { +- samsung,pins = "gpk0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus4: sd0-bus-width4 { +- samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus8: sd0-bus-width8 { +- samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd4_clk: sd4-clk { +- samsung,pins = "gpk0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd4_cmd: sd4-cmd { +- samsung,pins = "gpk0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd4_cd: sd4-cd { +- samsung,pins = "gpk0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd4_bus1: sd4-bus-width1 { +- samsung,pins = "gpk0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd4_bus4: sd4-bus-width4 { +- samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd4_bus8: sd4-bus-width8 { +- samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_clk: sd1-clk { +- samsung,pins = "gpk1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_cmd: sd1-cmd { +- samsung,pins = "gpk1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_cd: sd1-cd { +- samsung,pins = "gpk1-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus1: sd1-bus-width1 { +- samsung,pins = "gpk1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus4: sd1-bus-width4 { +- samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_clk: sd2-clk { +- samsung,pins = "gpk2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cmd: sd2-cmd { +- samsung,pins = "gpk2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cd: sd2-cd { +- samsung,pins = "gpk2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus1: sd2-bus-width1 { +- samsung,pins = "gpk2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus4: sd2-bus-width4 { +- samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus8: sd2-bus-width8 { +- samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_clk: sd3-clk { +- samsung,pins = "gpk3-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_cmd: sd3-cmd { +- samsung,pins = "gpk3-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_cd: sd3-cd { +- samsung,pins = "gpk3-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_bus1: sd3-bus-width1 { +- samsung,pins = "gpk3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_bus4: sd3-bus-width4 { +- samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_port_b_io: cam-port-b-io { +- samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", +- "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", +- "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_port_b_clk_active: cam-port-b-clk-active { +- samsung,pins = "gpm2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_port_b_clk_idle: cam-port-b-clk-idle { +- samsung,pins = "gpm2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- eint0: ext-int0 { +- samsung,pins = "gpx0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- eint8: ext-int8 { +- samsung,pins = "gpx1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- eint15: ext-int15 { +- samsung,pins = "gpx1-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- eint16: ext-int16 { +- samsung,pins = "gpx2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- eint31: ext-int31 { +- samsung,pins = "gpx3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- fimc_is_i2c0: fimc-is-i2c0 { +- samsung,pins = "gpm4-0", "gpm4-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- fimc_is_i2c1: fimc-is-i2c1 { +- samsung,pins = "gpm4-2", "gpm4-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- fimc_is_uart: fimc-is-uart { +- samsung,pins = "gpm3-5", "gpm3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hdmi_cec: hdmi-cec { +- samsung,pins = "gpx3-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_2 { +- gpz: gpz { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- i2s0_bus: i2s0-bus { +- samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", +- "gpz-4", "gpz-5", "gpz-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pcm0_bus: pcm0-bus { +- samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", +- "gpz-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_3 { +- gpv0: gpv0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpv1: gpv1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpv2: gpv2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpv3: gpv3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpv4: gpv4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- c2c_bus: c2c-bus { +- samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", +- "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", +- "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", +- "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7", +- "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", +- "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", +- "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", +- "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7", +- "gpv4-0", "gpv4-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-ppmu-common.dtsi b/scripts/dtc/include-prefixes/arm/exynos4412-ppmu-common.dtsi +deleted file mode 100644 +index 7f187a3dedcc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-ppmu-common.dtsi ++++ /dev/null +@@ -1,47 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device tree sources for Exynos4412 PPMU common device tree +- * +- * Copyright (C) 2015 Samsung Electronics +- * Author: Chanwoo Choi +- */ +- +-&ppmu_dmc0 { +- status = "okay"; +- +- events { +- ppmu_dmc0_3: ppmu-event3-dmc0 { +- event-name = "ppmu-event3-dmc0"; +- }; +- }; +-}; +- +-&ppmu_dmc1 { +- status = "okay"; +- +- events { +- ppmu_dmc1_3: ppmu-event3-dmc1 { +- event-name = "ppmu-event3-dmc1"; +- }; +- }; +-}; +- +-&ppmu_leftbus { +- status = "okay"; +- +- events { +- ppmu_leftbus_3: ppmu-event3-leftbus { +- event-name = "ppmu-event3-leftbus"; +- }; +- }; +-}; +- +-&ppmu_rightbus { +- status = "okay"; +- +- events { +- ppmu_rightbus_3: ppmu-event3-rightbus { +- event-name = "ppmu-event3-rightbus"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-prime.dtsi b/scripts/dtc/include-prefixes/arm/exynos4412-prime.dtsi +deleted file mode 100644 +index 3731a225f779..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-prime.dtsi ++++ /dev/null +@@ -1,47 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos4412 Prime SoC device tree source +- * +- * Copyright (c) 2016 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-/* +- * Exynos4412 Prime SoC revision supports higher CPU frequencies than +- * non-Prime version. Therefore we need to update OPPs table and +- * thermal maps accordingly. +- */ +- +-&cpu0_opp_1500 { +- /delete-property/turbo-mode; +-}; +- +-&cpu0_opp_table { +- opp-1600000000 { +- opp-hz = /bits/ 64 <1600000000>; +- opp-microvolt = <1350000>; +- clock-latency-ns = <200000>; +- }; +- opp-1704000000 { +- opp-hz = /bits/ 64 <1704000000>; +- opp-microvolt = <1350000>; +- clock-latency-ns = <200000>; +- }; +-}; +- +-&cooling_map0 { +- cooling-device = <&cpu0 9 9>, <&cpu1 9 9>, +- <&cpu2 9 9>, <&cpu3 9 9>; +-}; +- +-&cooling_map1 { +- cooling-device = <&cpu0 15 15>, <&cpu1 15 15>, +- <&cpu2 15 15>, <&cpu3 15 15>; +-}; +- +-&gpu_opp_table { +- opp-533000000 { +- opp-hz = /bits/ 64 <533000000>; +- opp-microvolt = <1075000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-smdk4412.dts b/scripts/dtc/include-prefixes/arm/exynos4412-smdk4412.dts +deleted file mode 100644 +index cc99b955af0c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-smdk4412.dts ++++ /dev/null +@@ -1,178 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos4412 based SMDK board device tree source +- * +- * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Device tree source file for Samsung's SMDK4412 board which is based on +- * Samsung's Exynos4412 SoC. +- */ +- +-/dts-v1/; +-#include "exynos4412.dtsi" +-#include "exynos-mfc-reserved-memory.dtsi" +- +-/ { +- model = "Samsung SMDK evaluation board based on Exynos4412"; +- compatible = "samsung,smdk4412", "samsung,exynos4412", "samsung,exynos4"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x40000000>; +- }; +- +- chosen { +- bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; +- stdout-path = "serial1:115200n8"; +- }; +- +- fixed-rate-clocks { +- xxti { +- compatible = "samsung,clock-xxti"; +- clock-frequency = <0>; +- }; +- +- xusbxti { +- compatible = "samsung,clock-xusbxti"; +- clock-frequency = <24000000>; +- }; +- +- pmic_ap_clk: pmic-ap-clk { +- /* Workaround for missing clock on PMIC */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- }; +-}; +- +-&cpu_thermal { +- cooling-maps { +- cooling_map0: map0 { +- /* Corresponds to 800MHz at freq_table */ +- cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, +- <&cpu2 7 7>, <&cpu3 7 7>; +- }; +- cooling_map1: map1 { +- /* Corresponds to 200MHz at freq_table */ +- cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, +- <&cpu2 13 13>, <&cpu3 13 13>; +- }; +- }; +-}; +- +-&keypad { +- samsung,keypad-num-rows = <3>; +- samsung,keypad-num-columns = <8>; +- linux,keypad-no-autorepeat; +- wakeup-source; +- pinctrl-0 = <&keypad_rows &keypad_cols>; +- pinctrl-names = "default"; +- status = "okay"; +- +- key-1 { +- keypad,row = <1>; +- keypad,column = <3>; +- linux,code = <2>; +- }; +- +- key-2 { +- keypad,row = <1>; +- keypad,column = <4>; +- linux,code = <3>; +- }; +- +- key-3 { +- keypad,row = <1>; +- keypad,column = <5>; +- linux,code = <4>; +- }; +- +- key-4 { +- keypad,row = <1>; +- keypad,column = <6>; +- linux,code = <5>; +- }; +- +- key-5 { +- keypad,row = <1>; +- keypad,column = <7>; +- linux,code = <6>; +- }; +- +- key-A { +- keypad,row = <2>; +- keypad,column = <6>; +- linux,code = <30>; +- }; +- +- key-B { +- keypad,row = <2>; +- keypad,column = <7>; +- linux,code = <48>; +- }; +- +- key-C { +- keypad,row = <0>; +- keypad,column = <5>; +- linux,code = <46>; +- }; +- +- key-D { +- keypad,row = <2>; +- keypad,column = <5>; +- linux,code = <32>; +- }; +- +- key-E { +- keypad,row = <0>; +- keypad,column = <7>; +- linux,code = <18>; +- }; +-}; +- +-&pinctrl_1 { +- keypad_rows: keypad-rows { +- samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- keypad_cols: keypad-cols { +- samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", +- "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&rtc { +- clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&sdhci_2 { +- bus-width = <4>; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&serial_0 { +- status = "okay"; +-}; +- +-&serial_1 { +- status = "okay"; +-}; +- +-&serial_2 { +- status = "okay"; +-}; +- +-&serial_3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-tiny4412.dts b/scripts/dtc/include-prefixes/arm/exynos4412-tiny4412.dts +deleted file mode 100644 +index 017b26108bb0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-tiny4412.dts ++++ /dev/null +@@ -1,145 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * FriendlyARM's Exynos4412 based TINY4412 board device tree source +- * +- * Copyright (c) 2013 Alex Ling +- * +- * Device tree source file for FriendlyARM's TINY4412 board which is based on +- * Samsung's Exynos4412 SoC. +- */ +- +-/dts-v1/; +-#include "exynos4412.dtsi" +-#include +- +-/ { +- model = "FriendlyARM TINY4412 board based on Exynos4412"; +- compatible = "friendlyarm,tiny4412", "samsung,exynos4412", "samsung,exynos4"; +- +- chosen { +- stdout-path = &serial_0; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x40000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led1 { +- label = "led1"; +- gpios = <&gpm4 0 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led2 { +- label = "led2"; +- gpios = <&gpm4 1 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led3 { +- label = "led3"; +- gpios = <&gpm4 2 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led4 { +- label = "led4"; +- gpios = <&gpm4 3 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- linux,default-trigger = "mmc0"; +- }; +- }; +- +- fixed-rate-clocks { +- xxti { +- compatible = "samsung,clock-xxti"; +- clock-frequency = <0>; +- }; +- +- xusbxti { +- compatible = "samsung,clock-xusbxti"; +- clock-frequency = <24000000>; +- }; +- +- pmic_ap_clk: pmic-ap-clk { +- /* Workaround for missing clock on PMIC */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- }; +- +- panel { +- compatible = "innolux,at070tn92"; +- +- port { +- panel_input: endpoint { +- remote-endpoint = <&lcdc_output>; +- }; +- }; +- }; +-}; +- +-&cpu_thermal { +- cooling-maps { +- cooling_map0: map0 { +- /* Corresponds to 800MHz at freq_table */ +- cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, +- <&cpu2 7 7>, <&cpu3 7 7>; +- }; +- cooling_map1: map1 { +- /* Corresponds to 200MHz at freq_table */ +- cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, +- <&cpu2 13 13>, <&cpu3 13 13>; +- }; +- }; +-}; +- +-&fimd { +- pinctrl-0 = <&lcd_clk>, <&lcd_data24>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- port@3 { +- reg = <3>; +- lcdc_output: endpoint { +- remote-endpoint = <&panel_input>; +- }; +- }; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&sdhci_2 { +- bus-width = <4>; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&serial_0 { +- status = "okay"; +-}; +- +-&serial_1 { +- status = "okay"; +-}; +- +-&serial_2 { +- status = "okay"; +-}; +- +-&serial_3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412-trats2.dts b/scripts/dtc/include-prefixes/arm/exynos4412-trats2.dts +deleted file mode 100644 +index 7b447b63007e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412-trats2.dts ++++ /dev/null +@@ -1,28 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos4412 based Trats 2 board device tree source +- * +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Device tree source file for Samsung's Trats 2 board which is based on +- * Samsung's Exynos4412 SoC. +- */ +- +-/dts-v1/; +-#include "exynos4412-galaxy-s3.dtsi" +- +-/ { +- model = "Samsung Trats 2 based on Exynos4412"; +- compatible = "samsung,trats2", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x40000000>; +- }; +- +- chosen { +- bootargs = "root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; +- stdout-path = "serial2:115200n8"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos4412.dtsi b/scripts/dtc/include-prefixes/arm/exynos4412.dtsi +deleted file mode 100644 +index d3802046c8b8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos4412.dtsi ++++ /dev/null +@@ -1,821 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos4412 SoC device tree source +- * +- * Copyright (c) 2012 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412 +- * based board files can include this file and provide values for board specfic +- * bindings. +- * +- * Note: This file does not include device nodes for all the controllers in +- * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional +- * nodes can be added to this file. +- */ +- +-#include "exynos4.dtsi" +- +-#include "exynos4-cpu-thermal.dtsi" +- +-/ { +- compatible = "samsung,exynos4412", "samsung,exynos4"; +- +- aliases { +- pinctrl0 = &pinctrl_0; +- pinctrl1 = &pinctrl_1; +- pinctrl2 = &pinctrl_2; +- pinctrl3 = &pinctrl_3; +- fimc-lite0 = &fimc_lite_0; +- fimc-lite1 = &fimc_lite_1; +- mshc0 = &mshc_0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- core2 { +- cpu = <&cpu2>; +- }; +- core3 { +- cpu = <&cpu3>; +- }; +- }; +- }; +- +- cpu0: cpu@a00 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0xA00>; +- clocks = <&clock CLK_ARM_CLK>; +- clock-names = "cpu"; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- +- cpu1: cpu@a01 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0xA01>; +- clocks = <&clock CLK_ARM_CLK>; +- clock-names = "cpu"; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- +- cpu2: cpu@a02 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0xA02>; +- clocks = <&clock CLK_ARM_CLK>; +- clock-names = "cpu"; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- +- cpu3: cpu@a03 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0xA03>; +- clocks = <&clock CLK_ARM_CLK>; +- clock-names = "cpu"; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- }; +- +- cpu0_opp_table: opp-table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- opp-microvolt = <900000>; +- clock-latency-ns = <200000>; +- }; +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <900000>; +- clock-latency-ns = <200000>; +- }; +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <925000>; +- clock-latency-ns = <200000>; +- }; +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <950000>; +- clock-latency-ns = <200000>; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <975000>; +- clock-latency-ns = <200000>; +- }; +- opp-700000000 { +- opp-hz = /bits/ 64 <700000000>; +- opp-microvolt = <987500>; +- clock-latency-ns = <200000>; +- }; +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <1000000>; +- clock-latency-ns = <200000>; +- opp-suspend; +- }; +- opp-900000000 { +- opp-hz = /bits/ 64 <900000000>; +- opp-microvolt = <1037500>; +- clock-latency-ns = <200000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <1087500>; +- clock-latency-ns = <200000>; +- }; +- opp-1100000000 { +- opp-hz = /bits/ 64 <1100000000>; +- opp-microvolt = <1137500>; +- clock-latency-ns = <200000>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <1187500>; +- clock-latency-ns = <200000>; +- }; +- opp-1300000000 { +- opp-hz = /bits/ 64 <1300000000>; +- opp-microvolt = <1250000>; +- clock-latency-ns = <200000>; +- }; +- opp-1400000000 { +- opp-hz = /bits/ 64 <1400000000>; +- opp-microvolt = <1287500>; +- clock-latency-ns = <200000>; +- }; +- cpu0_opp_1500: opp-1500000000 { +- opp-hz = /bits/ 64 <1500000000>; +- opp-microvolt = <1350000>; +- clock-latency-ns = <200000>; +- turbo-mode; +- }; +- }; +- +- +- soc: soc { +- +- pinctrl_0: pinctrl@11400000 { +- compatible = "samsung,exynos4x12-pinctrl"; +- reg = <0x11400000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_1: pinctrl@11000000 { +- compatible = "samsung,exynos4x12-pinctrl"; +- reg = <0x11000000 0x1000>; +- interrupts = ; +- +- wakup_eint: wakeup-interrupt-controller { +- compatible = "samsung,exynos4210-wakeup-eint"; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +- +- pinctrl_2: pinctrl@3860000 { +- compatible = "samsung,exynos4x12-pinctrl"; +- reg = <0x03860000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <10 0>; +- }; +- +- pinctrl_3: pinctrl@106e0000 { +- compatible = "samsung,exynos4x12-pinctrl"; +- reg = <0x106E0000 0x1000>; +- interrupts = ; +- }; +- +- sram@2020000 { +- compatible = "mmio-sram"; +- reg = <0x02020000 0x40000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x02020000 0x40000>; +- +- smp-sram@0 { +- compatible = "samsung,exynos4210-sysram"; +- reg = <0x0 0x1000>; +- }; +- +- smp-sram@2f000 { +- compatible = "samsung,exynos4210-sysram-ns"; +- reg = <0x2f000 0x1000>; +- }; +- }; +- +- pd_isp: power-domain@10023ca0 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10023CA0 0x20>; +- #power-domain-cells = <0>; +- label = "ISP"; +- }; +- +- l2c: cache-controller@10502000 { +- compatible = "arm,pl310-cache"; +- reg = <0x10502000 0x1000>; +- cache-unified; +- cache-level = <2>; +- prefetch-data = <1>; +- prefetch-instr = <1>; +- arm,tag-latency = <2 2 1>; +- arm,data-latency = <3 2 1>; +- arm,double-linefill = <1>; +- arm,double-linefill-incr = <0>; +- arm,double-linefill-wrap = <1>; +- arm,prefetch-drop = <1>; +- arm,prefetch-offset = <7>; +- }; +- +- clock: clock-controller@10030000 { +- compatible = "samsung,exynos4412-clock"; +- reg = <0x10030000 0x18000>; +- #clock-cells = <1>; +- }; +- +- isp_clock: clock-controller@10048000 { +- compatible = "samsung,exynos4412-isp-clock"; +- reg = <0x10048000 0x1000>; +- #clock-cells = <1>; +- power-domains = <&pd_isp>; +- clocks = <&clock CLK_ACLK200>, +- <&clock CLK_ACLK400_MCUISP>; +- clock-names = "aclk200", "aclk400_mcuisp"; +- }; +- +- timer@10050000 { +- compatible = "samsung,exynos4412-mct"; +- reg = <0x10050000 0x800>; +- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; +- clock-names = "fin_pll", "mct"; +- interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, +- <&combiner 12 5>, +- <&combiner 12 6>, +- <&combiner 12 7>, +- <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- watchdog: watchdog@10060000 { +- compatible = "samsung,exynos5250-wdt"; +- reg = <0x10060000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_WDT>; +- clock-names = "watchdog"; +- samsung,syscon-phandle = <&pmu_system_controller>; +- }; +- +- adc: adc@126c0000 { +- compatible = "samsung,exynos4212-adc"; +- reg = <0x126C0000 0x100>; +- interrupt-parent = <&combiner>; +- interrupts = <10 3>; +- clocks = <&clock CLK_TSADC>; +- clock-names = "adc"; +- #io-channel-cells = <1>; +- samsung,syscon-phandle = <&pmu_system_controller>; +- status = "disabled"; +- }; +- +- g2d: g2d@10800000 { +- compatible = "samsung,exynos4212-g2d"; +- reg = <0x10800000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; +- clock-names = "sclk_fimg2d", "fimg2d"; +- iommus = <&sysmmu_g2d>; +- }; +- +- mshc_0: mmc@12550000 { +- compatible = "samsung,exynos4412-dw-mshc"; +- reg = <0x12550000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- fifo-depth = <0x80>; +- clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; +- clock-names = "biu", "ciu"; +- status = "disabled"; +- }; +- +- sysmmu_g2d: sysmmu@10a40000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x10A40000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <4 7>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc_isp: sysmmu@12260000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x12260000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <16 2>; +- power-domains = <&pd_isp>; +- clock-names = "sysmmu"; +- clocks = <&isp_clock CLK_ISP_SMMU_ISP>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc_drc: sysmmu@12270000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x12270000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <16 3>; +- power-domains = <&pd_isp>; +- clock-names = "sysmmu"; +- clocks = <&isp_clock CLK_ISP_SMMU_DRC>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc_fd: sysmmu@122a0000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x122A0000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <16 4>; +- power-domains = <&pd_isp>; +- clock-names = "sysmmu"; +- clocks = <&isp_clock CLK_ISP_SMMU_FD>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc_mcuctl: sysmmu@122b0000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x122B0000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <16 5>; +- power-domains = <&pd_isp>; +- clock-names = "sysmmu"; +- clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc_lite0: sysmmu@123b0000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x123B0000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <16 0>; +- power-domains = <&pd_isp>; +- clock-names = "sysmmu", "master"; +- clocks = <&isp_clock CLK_ISP_SMMU_LITE0>, +- <&isp_clock CLK_ISP_FIMC_LITE0>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc_lite1: sysmmu@123c0000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x123C0000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <16 1>; +- power-domains = <&pd_isp>; +- clock-names = "sysmmu", "master"; +- clocks = <&isp_clock CLK_ISP_SMMU_LITE1>, +- <&isp_clock CLK_ISP_FIMC_LITE1>; +- #iommu-cells = <0>; +- }; +- +- bus_dmc: bus-dmc { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DIV_DMC>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_dmc_opp_table>; +- samsung,data-clock-ratio = <4>; +- #interconnect-cells = <0>; +- status = "disabled"; +- }; +- +- bus_acp: bus-acp { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DIV_ACP>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_acp_opp_table>; +- status = "disabled"; +- }; +- +- bus_c2c: bus-c2c { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DIV_C2C>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_dmc_opp_table>; +- status = "disabled"; +- }; +- +- bus_dmc_opp_table: opp-table1 { +- compatible = "operating-points-v2"; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- opp-microvolt = <900000>; +- }; +- opp-134000000 { +- opp-hz = /bits/ 64 <134000000>; +- opp-microvolt = <900000>; +- }; +- opp-160000000 { +- opp-hz = /bits/ 64 <160000000>; +- opp-microvolt = <900000>; +- }; +- opp-267000000 { +- opp-hz = /bits/ 64 <267000000>; +- opp-microvolt = <950000>; +- }; +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <1050000>; +- opp-suspend; +- }; +- }; +- +- bus_acp_opp_table: opp-table2 { +- compatible = "operating-points-v2"; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- }; +- opp-134000000 { +- opp-hz = /bits/ 64 <134000000>; +- }; +- opp-160000000 { +- opp-hz = /bits/ 64 <160000000>; +- }; +- opp-267000000 { +- opp-hz = /bits/ 64 <267000000>; +- }; +- }; +- +- bus_leftbus: bus-leftbus { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DIV_GDL>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_leftbus_opp_table>; +- interconnects = <&bus_dmc>; +- #interconnect-cells = <0>; +- status = "disabled"; +- }; +- +- bus_rightbus: bus-rightbus { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DIV_GDR>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_leftbus_opp_table>; +- status = "disabled"; +- }; +- +- bus_display: bus-display { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_ACLK160>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_display_opp_table>; +- interconnects = <&bus_leftbus &bus_dmc>; +- #interconnect-cells = <0>; +- status = "disabled"; +- }; +- +- bus_fsys: bus-fsys { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_ACLK133>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_fsys_opp_table>; +- status = "disabled"; +- }; +- +- bus_peri: bus-peri { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_ACLK100>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_peri_opp_table>; +- status = "disabled"; +- }; +- +- bus_mfc: bus-mfc { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_SCLK_MFC>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_leftbus_opp_table>; +- status = "disabled"; +- }; +- +- bus_leftbus_opp_table: opp-table3 { +- compatible = "operating-points-v2"; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- opp-microvolt = <900000>; +- }; +- opp-134000000 { +- opp-hz = /bits/ 64 <134000000>; +- opp-microvolt = <925000>; +- }; +- opp-160000000 { +- opp-hz = /bits/ 64 <160000000>; +- opp-microvolt = <950000>; +- }; +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- opp-microvolt = <1000000>; +- opp-suspend; +- }; +- }; +- +- bus_display_opp_table: opp-table4 { +- compatible = "operating-points-v2"; +- +- opp-160000000 { +- opp-hz = /bits/ 64 <160000000>; +- }; +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- }; +- }; +- +- bus_fsys_opp_table: opp-table5 { +- compatible = "operating-points-v2"; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- }; +- opp-134000000 { +- opp-hz = /bits/ 64 <134000000>; +- }; +- }; +- +- bus_peri_opp_table: opp-table6 { +- compatible = "operating-points-v2"; +- +- opp-50000000 { +- opp-hz = /bits/ 64 <50000000>; +- }; +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- }; +- }; +- }; +-}; +- +-&combiner { +- samsung,combiner-nr = <20>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +-}; +- +-&camera { +- clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, +- <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; +- clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; +- +- /* fimc_[0-3] are configured outside, under phandles */ +- fimc_lite_0: fimc-lite@12390000 { +- compatible = "samsung,exynos4212-fimc-lite"; +- reg = <0x12390000 0x1000>; +- interrupts = ; +- power-domains = <&pd_isp>; +- clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; +- clock-names = "flite"; +- iommus = <&sysmmu_fimc_lite0>; +- status = "disabled"; +- }; +- +- fimc_lite_1: fimc-lite@123a0000 { +- compatible = "samsung,exynos4212-fimc-lite"; +- reg = <0x123A0000 0x1000>; +- interrupts = ; +- power-domains = <&pd_isp>; +- clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; +- clock-names = "flite"; +- iommus = <&sysmmu_fimc_lite1>; +- status = "disabled"; +- }; +- +- fimc_is: fimc-is@12000000 { +- compatible = "samsung,exynos4212-fimc-is"; +- reg = <0x12000000 0x260000>; +- interrupts = , +- ; +- power-domains = <&pd_isp>; +- clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, +- <&isp_clock CLK_ISP_FIMC_LITE1>, +- <&isp_clock CLK_ISP_PPMUISPX>, +- <&isp_clock CLK_ISP_PPMUISPMX>, +- <&isp_clock CLK_ISP_FIMC_ISP>, +- <&isp_clock CLK_ISP_FIMC_DRC>, +- <&isp_clock CLK_ISP_FIMC_FD>, +- <&isp_clock CLK_ISP_MCUISP>, +- <&isp_clock CLK_ISP_GICISP>, +- <&isp_clock CLK_ISP_MCUCTL_ISP>, +- <&isp_clock CLK_ISP_PWM_ISP>, +- <&isp_clock CLK_ISP_DIV_ISP0>, +- <&isp_clock CLK_ISP_DIV_ISP1>, +- <&isp_clock CLK_ISP_DIV_MCUISP0>, +- <&isp_clock CLK_ISP_DIV_MCUISP1>, +- <&clock CLK_MOUT_MPLL_USER_T>, +- <&clock CLK_ACLK200>, +- <&clock CLK_ACLK400_MCUISP>, +- <&clock CLK_DIV_ACLK200>, +- <&clock CLK_DIV_ACLK400_MCUISP>, +- <&clock CLK_UART_ISP_SCLK>; +- clock-names = "lite0", "lite1", "ppmuispx", +- "ppmuispmx", "isp", +- "drc", "fd", "mcuisp", +- "gicisp", "mcuctl_isp", "pwm_isp", +- "ispdiv0", "ispdiv1", "mcuispdiv0", +- "mcuispdiv1", "mpll", "aclk200", +- "aclk400mcuisp", "div_aclk200", +- "div_aclk400mcuisp", "uart"; +- iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, +- <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; +- iommu-names = "isp", "drc", "fd", "mcuctl"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- +- pmu@10020000 { +- reg = <0x10020000 0x3000>; +- }; +- +- i2c1_isp: i2c-isp@12140000 { +- compatible = "samsung,exynos4212-i2c-isp"; +- reg = <0x12140000 0x100>; +- clocks = <&isp_clock CLK_ISP_I2C1_ISP>; +- clock-names = "i2c_isp"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +-}; +- +-&exynos_usbphy { +- compatible = "samsung,exynos4x12-usb2-phy"; +- samsung,sysreg-phandle = <&sys_reg>; +-}; +- +-&fimc_0 { +- compatible = "samsung,exynos4212-fimc"; +- samsung,pix-limits = <4224 8192 1920 4224>; +- samsung,mainscaler-ext; +- samsung,isp-wb; +- samsung,cam-if; +-}; +- +-&fimc_1 { +- compatible = "samsung,exynos4212-fimc"; +- samsung,pix-limits = <4224 8192 1920 4224>; +- samsung,mainscaler-ext; +- samsung,isp-wb; +- samsung,cam-if; +-}; +- +-&fimc_2 { +- compatible = "samsung,exynos4212-fimc"; +- samsung,pix-limits = <4224 8192 1920 4224>; +- samsung,mainscaler-ext; +- samsung,isp-wb; +- samsung,lcd-wb; +- samsung,cam-if; +-}; +- +-&fimc_3 { +- compatible = "samsung,exynos4212-fimc"; +- samsung,pix-limits = <1920 8192 1366 1920>; +- samsung,rotators = <0>; +- samsung,mainscaler-ext; +- samsung,isp-wb; +- samsung,lcd-wb; +-}; +- +-&gic { +- cpu-offset = <0x4000>; +-}; +- +-&gpu { +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "gp", +- "gpmmu", +- "pp0", +- "ppmmu0", +- "pp1", +- "ppmmu1", +- "pp2", +- "ppmmu2", +- "pp3", +- "ppmmu3", +- "pmu"; +- operating-points-v2 = <&gpu_opp_table>; +- +- gpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-160000000 { +- opp-hz = /bits/ 64 <160000000>; +- opp-microvolt = <875000>; +- }; +- opp-267000000 { +- opp-hz = /bits/ 64 <267000000>; +- opp-microvolt = <900000>; +- }; +- opp-350000000 { +- opp-hz = /bits/ 64 <350000000>; +- opp-microvolt = <950000>; +- }; +- opp-440000000 { +- opp-hz = /bits/ 64 <440000000>; +- opp-microvolt = <1025000>; +- }; +- }; +-}; +- +-&hdmi { +- compatible = "samsung,exynos4212-hdmi"; +-}; +- +-&jpeg_codec { +- compatible = "samsung,exynos4212-jpeg"; +-}; +- +-&rotator { +- compatible = "samsung,exynos4212-rotator"; +-}; +- +-&mixer { +- compatible = "samsung,exynos4212-mixer"; +- clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; +- clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, +- <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; +- interconnects = <&bus_display &bus_dmc>; +-}; +- +-&pmu { +- interrupts = <2 2>, <3 2>, <18 2>, <19 2>; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- status = "okay"; +-}; +- +-&pmu_system_controller { +- compatible = "samsung,exynos4412-pmu", "syscon"; +- clock-names = "clkout0", "clkout1", "clkout2", "clkout3", +- "clkout4", "clkout8", "clkout9"; +- clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, +- <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, +- <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; +- #clock-cells = <1>; +-}; +- +-&tmu { +- compatible = "samsung,exynos4412-tmu"; +- interrupt-parent = <&combiner>; +- interrupts = <2 4>; +- reg = <0x100C0000 0x100>; +- clocks = <&clock 383>; +- clock-names = "tmu_apbif"; +- status = "disabled"; +-}; +- +-#include "exynos4412-pinctrl.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/exynos5.dtsi b/scripts/dtc/include-prefixes/arm/exynos5.dtsi +deleted file mode 100644 +index 9ce9fb3fc190..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5.dtsi ++++ /dev/null +@@ -1,230 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos5 SoC series common device tree source +- * +- * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular +- * SoCs from Exynos5 series can include this file and provide values for SoCs +- * specfic bindings. +- */ +- +-#include +-#include +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- i2c0 = &i2c_0; +- i2c1 = &i2c_1; +- i2c2 = &i2c_2; +- i2c3 = &i2c_3; +- serial0 = &serial_0; +- serial1 = &serial_1; +- serial2 = &serial_2; +- serial3 = &serial_3; +- }; +- +- soc: soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- chipid: chipid@10000000 { +- compatible = "samsung,exynos4210-chipid"; +- reg = <0x10000000 0x100>; +- }; +- +- sromc: memory-controller@12250000 { +- compatible = "samsung,exynos4210-srom"; +- reg = <0x12250000 0x14>; +- }; +- +- combiner: interrupt-controller@10440000 { +- compatible = "samsung,exynos4210-combiner"; +- #interrupt-cells = <2>; +- interrupt-controller; +- samsung,combiner-nr = <32>; +- reg = <0x10440000 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- }; +- +- gic: interrupt-controller@10481000 { +- compatible = "arm,gic-400", "arm,cortex-a15-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x10481000 0x1000>, +- <0x10482000 0x2000>, +- <0x10484000 0x2000>, +- <0x10486000 0x2000>; +- interrupts = ; +- }; +- +- sysreg_system_controller: syscon@10050000 { +- compatible = "samsung,exynos5-sysreg", "syscon"; +- reg = <0x10050000 0x5000>; +- }; +- +- serial_0: serial@12c00000 { +- compatible = "samsung,exynos4210-uart"; +- reg = <0x12C00000 0x100>; +- interrupts = ; +- }; +- +- serial_1: serial@12c10000 { +- compatible = "samsung,exynos4210-uart"; +- reg = <0x12C10000 0x100>; +- interrupts = ; +- }; +- +- serial_2: serial@12c20000 { +- compatible = "samsung,exynos4210-uart"; +- reg = <0x12C20000 0x100>; +- interrupts = ; +- }; +- +- serial_3: serial@12c30000 { +- compatible = "samsung,exynos4210-uart"; +- reg = <0x12C30000 0x100>; +- interrupts = ; +- }; +- +- i2c_0: i2c@12c60000 { +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x12C60000 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- samsung,sysreg-phandle = <&sysreg_system_controller>; +- status = "disabled"; +- }; +- +- i2c_1: i2c@12c70000 { +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x12C70000 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- samsung,sysreg-phandle = <&sysreg_system_controller>; +- status = "disabled"; +- }; +- +- i2c_2: i2c@12c80000 { +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x12C80000 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- samsung,sysreg-phandle = <&sysreg_system_controller>; +- status = "disabled"; +- }; +- +- i2c_3: i2c@12c90000 { +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x12C90000 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- samsung,sysreg-phandle = <&sysreg_system_controller>; +- status = "disabled"; +- }; +- +- pwm: pwm@12dd0000 { +- compatible = "samsung,exynos4210-pwm"; +- reg = <0x12DD0000 0x100>; +- interrupts = , +- , +- , +- , +- ; +- samsung,pwm-outputs = <0>, <1>, <2>, <3>; +- #pwm-cells = <3>; +- }; +- +- rtc: rtc@101e0000 { +- compatible = "samsung,s3c6410-rtc"; +- reg = <0x101E0000 0x100>; +- interrupts = , +- ; +- status = "disabled"; +- }; +- +- fimd: fimd@14400000 { +- compatible = "samsung,exynos5250-fimd"; +- interrupt-parent = <&combiner>; +- reg = <0x14400000 0x40000>; +- interrupt-names = "fifo", "vsync", "lcd_sys"; +- interrupts = <18 4>, <18 5>, <18 6>; +- samsung,sysreg = <&sysreg_system_controller>; +- status = "disabled"; +- }; +- +- dp: dp-controller@145b0000 { +- compatible = "samsung,exynos5-dp"; +- reg = <0x145B0000 0x1000>; +- interrupts = <10 3>; +- interrupt-parent = <&combiner>; +- status = "disabled"; +- }; +- +- sss: sss@10830000 { +- compatible = "samsung,exynos4210-secss"; +- reg = <0x10830000 0x300>; +- interrupts = ; +- }; +- +- prng: rng@10830400 { +- compatible = "samsung,exynos5250-prng"; +- reg = <0x10830400 0x200>; +- }; +- +- trng: rng@10830600 { +- compatible = "samsung,exynos5250-trng"; +- reg = <0x10830600 0x100>; +- }; +- +- g2d: g2d@10850000 { +- compatible = "samsung,exynos5250-g2d"; +- reg = <0x10850000 0x1000>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5250-arndale.dts b/scripts/dtc/include-prefixes/arm/exynos5250-arndale.dts +deleted file mode 100644 +index a771542e28b8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5250-arndale.dts ++++ /dev/null +@@ -1,637 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos5250 based Arndale board device tree source +- * +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-/dts-v1/; +-#include +-#include +-#include +-#include +-#include +-#include "exynos5250.dtsi" +- +-/ { +- model = "Insignal Arndale evaluation board based on Exynos5250"; +- compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x80000000>; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- menu { +- label = "SW-TACT2"; +- gpios = <&gpx1 4 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- home { +- label = "SW-TACT3"; +- gpios = <&gpx1 5 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- up { +- label = "SW-TACT4"; +- gpios = <&gpx1 6 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- down { +- label = "SW-TACT5"; +- gpios = <&gpx1 7 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- back { +- label = "SW-TACT6"; +- gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- wakeup { +- label = "SW-TACT7"; +- gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- panel: panel { +- compatible = "boe,hv070wsa-100"; +- power-supply = <&vcc_3v3_reg>; +- enable-gpios = <&gpd1 3 GPIO_ACTIVE_HIGH>; +- port { +- panel_ep: endpoint { +- remote-endpoint = <&bridge_out_ep>; +- }; +- }; +- }; +- +- main_dc_reg: regulator-0 { +- compatible = "regulator-fixed"; +- regulator-name = "MAIN_DC"; +- regulator-always-on; +- }; +- +- mmc_reg: regulator-1 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_MMC"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- reg_hdmi_en: regulator-2 { +- compatible = "regulator-fixed"; +- regulator-name = "hdmi-en"; +- regulator-always-on; +- }; +- +- vcc_1v2_reg: regulator-3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_1V2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vcc_1v8_reg: regulator-4 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcc_3v3_reg: regulator-5 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- sound { +- compatible = "samsung,arndale-wm1811"; +- samsung,audio-cpu = <&i2s0>; +- samsung,audio-codec = <&wm1811>; +- }; +- +- fixed-rate-clocks { +- xxti { +- compatible = "samsung,clock-xxti"; +- clock-frequency = <24000000>; +- }; +- }; +- +- // SMSC USB3503 connected in hardware only mode as a PHY +- usb_hub: usb-hub { +- compatible = "smsc,usb3503a"; +- +- reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; +- connect-gpios = <&gpd1 7 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&clock { +- assigned-clocks = <&clock CLK_FOUT_EPLL>; +- assigned-clock-rates = <49152000>; +-}; +- +-&clock_audss { +- assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; +- assigned-clock-parents = <&clock CLK_FOUT_EPLL>; +-}; +- +-&cpu0 { +- cpu0-supply = <&buck2_reg>; +-}; +- +-&dsi_0 { +- vddcore-supply = <&ldo8_reg>; +- vddio-supply = <&ldo10_reg>; +- samsung,pll-clock-frequency = <24000000>; +- samsung,burst-clock-frequency = <320000000>; +- samsung,esc-clock-frequency = <10000000>; +- status = "okay"; +- +- bridge@0 { +- reg = <0>; +- compatible = "toshiba,tc358764"; +- vddc-supply = <&vcc_1v2_reg>; +- vddio-supply = <&vcc_1v8_reg>; +- vddlvds-supply = <&vcc_3v3_reg>; +- reset-gpios = <&gpd1 6 GPIO_ACTIVE_LOW>; +- #address-cells = <1>; +- #size-cells = <0>; +- port@1 { +- reg = <1>; +- bridge_out_ep: endpoint { +- remote-endpoint = <&panel_ep>; +- }; +- }; +- }; +-}; +- +-&fimd { +- status = "okay"; +-}; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_hpd>; +- status = "okay"; +- ddc = <&i2c_ddc>; +- hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; +- vdd_osc-supply = <&ldo10_reg>; +- vdd_pll-supply = <&ldo8_reg>; +- vdd-supply = <&ldo8_reg>; +-}; +- +-&i2c_0 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <20000>; +- samsung,i2c-slave-addr = <0x66>; +- +- pmic@66 { +- compatible = "samsung,s5m8767-pmic"; +- reg = <0x66>; +- interrupt-parent = <&gpx3>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&s5m8767_irq>; +- wakeup-source; +- +- vinb1-supply = <&main_dc_reg>; +- vinb2-supply = <&main_dc_reg>; +- vinb3-supply = <&main_dc_reg>; +- vinb4-supply = <&main_dc_reg>; +- vinb5-supply = <&main_dc_reg>; +- vinb6-supply = <&main_dc_reg>; +- vinb7-supply = <&main_dc_reg>; +- vinb8-supply = <&main_dc_reg>; +- vinb9-supply = <&main_dc_reg>; +- +- vinl1-supply = <&buck7_reg>; +- vinl2-supply = <&buck7_reg>; +- vinl3-supply = <&buck7_reg>; +- vinl4-supply = <&main_dc_reg>; +- vinl5-supply = <&main_dc_reg>; +- vinl6-supply = <&main_dc_reg>; +- vinl7-supply = <&main_dc_reg>; +- vinl8-supply = <&buck8_reg>; +- vinl9-supply = <&buck8_reg>; +- +- s5m8767,pmic-buck2-dvs-voltage = <1300000>; +- s5m8767,pmic-buck3-dvs-voltage = <1100000>; +- s5m8767,pmic-buck4-dvs-voltage = <1200000>; +- s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>, +- <&gpd1 1 GPIO_ACTIVE_HIGH>, +- <&gpd1 2 GPIO_ACTIVE_HIGH>; +- s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>, +- <&gpx2 4 GPIO_ACTIVE_HIGH>, +- <&gpx2 5 GPIO_ACTIVE_HIGH>; +- +- s5m8767_osc: clocks { +- compatible = "samsung,s5m8767-clk"; +- #clock-cells = <1>; +- clock-output-names = "s5m8767_ap", "unused1", "unused2"; +- }; +- +- regulators { +- ldo1_reg: LDO1 { +- regulator-name = "VDD_ALIVE_1.0V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "VDD_28IO_DP_1.35V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "VDD_COMMON1_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "VDD_IOPERI_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <1>; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "VDD_EXT_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "VDD_MPLL_1.1V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "VDD_XPLL_1.1V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "VDD_COMMON2_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "VDD_33ON_3.0V"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- op_mode = <1>; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "VDD_COMMON3_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "VDD_ABB2_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "VDD_USB_3.0V"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "VDDQ_C2C_W_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "VDD18_ABB0_3_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "VDD10_COMMON4_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "VDD18_HSIC_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "VDDQ_MMC2_3_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- ldo18_reg: LDO18 { +- regulator-name = "VDD_33ON_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- op_mode = <1>; +- }; +- +- ldo22_reg: LDO22 { +- regulator-name = "EXT_33_OFF"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- op_mode = <1>; +- }; +- +- ldo23_reg: LDO23 { +- regulator-name = "EXT_28_OFF"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- op_mode = <1>; +- }; +- +- ldo25_reg: LDO25 { +- regulator-name = "PVDD_LDO25"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- op_mode = <1>; +- }; +- +- ldo26_reg: LDO26 { +- regulator-name = "EXT_18_OFF"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- op_mode = <1>; +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "VDD_MIF"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "VDD_ARM"; +- regulator-min-microvolt = <912500>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "VDD_INT"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "VDD_G3D"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "VDD_MEM_1.35V"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1355000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- buck7_reg: BUCK7 { +- regulator-name = "PVDD_BUCK7"; +- regulator-always-on; +- op_mode = <1>; +- }; +- +- buck8_reg: BUCK8 { +- regulator-name = "PVDD_BUCK8"; +- regulator-always-on; +- op_mode = <1>; +- }; +- +- buck9_reg: BUCK9 { +- regulator-name = "VDD_33_OFF_EXT1"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3000000>; +- op_mode = <1>; +- }; +- }; +- }; +-}; +- +-&i2c_3 { +- status = "okay"; +- +- wm1811: audio-codec@1a { +- compatible = "wlf,wm1811"; +- reg = <0x1a>; +- clocks = <&i2s0 CLK_I2S_CDCLK>; +- clock-names = "MCLK1"; +- +- AVDD2-supply = <&main_dc_reg>; +- CPVDD-supply = <&main_dc_reg>; +- DBVDD1-supply = <&main_dc_reg>; +- DBVDD2-supply = <&main_dc_reg>; +- DBVDD3-supply = <&main_dc_reg>; +- LDO1VDD-supply = <&main_dc_reg>; +- SPKVDD1-supply = <&main_dc_reg>; +- SPKVDD2-supply = <&main_dc_reg>; +- +- wlf,ldo1ena = <&gpb0 0 GPIO_ACTIVE_HIGH>; +- wlf,ldo2ena = <&gpb0 1 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&i2c_8 { +- status = "okay"; +- /* used by HDMI PHY */ +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <66000>; +-}; +- +-&i2c_9 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <40000>; +-}; +- +-&i2s0 { +- assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; +- assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>; +- status = "okay"; +-}; +- +-&i2s0_bus { +- samsung,pin-drv = ; +-}; +- +-&mali { +- mali-supply = <&buck4_reg>; +- status = "okay"; +-}; +- +-&mixer { +- status = "okay"; +-}; +- +-&mmc_0 { +- status = "okay"; +- broken-cd; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- vmmc-supply = <&mmc_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; +- bus-width = <8>; +- cap-mmc-highspeed; +-}; +- +-&mmc_2 { +- status = "okay"; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- vmmc-supply = <&mmc_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; +- bus-width = <4>; +- disable-wp; +- cap-sd-highspeed; +-}; +- +-&pinctrl_0 { +- s5m8767_irq: s5m8767-irq { +- samsung,pins = "gpx3-2"; +- samsung,pin-pud = ; +- }; +-}; +- +-&rtc { +- clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; +- clock-names = "rtc", "rtc_src"; +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&sata_phy { +- status = "okay"; +- samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; +-}; +- +-&sata_phy_i2c { +- status = "okay"; +-}; +- +-&soc { +- /* +- * For unknown reasons HDMI-DDC does not work with Exynos I2C +- * controllers. Lets use software I2C over GPIO pins as a workaround. +- */ +- i2c_ddc: i2c-10 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_gpio_bus>; +- status = "okay"; +- compatible = "i2c-gpio"; +- sda-gpios = <&gpa0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpa0 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5250-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/exynos5250-pinctrl.dtsi +deleted file mode 100644 +index d31a68672bfa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5250-pinctrl.dtsi ++++ /dev/null +@@ -1,833 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source +- * +- * Copyright (c) 2012 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device +- * tree nodes are listed in this file. +- */ +- +-#include +- +-&pinctrl_0 { +- gpa0: gpa0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpa1: gpa1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpa2: gpa2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb0: gpb0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb1: gpb1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb2: gpb2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb3: gpb3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc0: gpc0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc1: gpc1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc2: gpc2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc3: gpc3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd0: gpd0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd1: gpd1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpy0: gpy0 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy1: gpy1 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy2: gpy2 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy3: gpy3 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy4: gpy4 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy5: gpy5 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy6: gpy6 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpc4: gpc4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpx0: gpx0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- interrupt-parent = <&combiner>; +- #interrupt-cells = <2>; +- interrupts = <23 0>, <24 0>, <25 0>, <25 1>, +- <26 0>, <26 1>, <27 0>, <27 1>; +- }; +- +- gpx1: gpx1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- interrupt-parent = <&combiner>; +- #interrupt-cells = <2>; +- interrupts = <28 0>, <28 1>, <29 0>, <29 1>, +- <30 0>, <30 1>, <31 0>, <31 1>; +- }; +- +- gpx2: gpx2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpx3: gpx3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- uart0_data: uart0-data { +- samsung,pins = "gpa0-0", "gpa0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart0_fctl: uart0-fctl { +- samsung,pins = "gpa0-2", "gpa0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c2_bus: i2c2-bus { +- samsung,pins = "gpa0-6", "gpa0-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c2_hs_bus: i2c2-hs-bus { +- samsung,pins = "gpa0-6", "gpa0-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c2_gpio_bus: i2c2-gpio-bus { +- samsung,pins = "gpa0-6", "gpa0-7"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart2_data: uart2-data { +- samsung,pins = "gpa1-0", "gpa1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart2_fctl: uart2-fctl { +- samsung,pins = "gpa1-2", "gpa1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c3_bus: i2c3-bus { +- samsung,pins = "gpa1-2", "gpa1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c3_hs_bus: i2c3-hs-bus { +- samsung,pins = "gpa1-2", "gpa1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart3_data: uart3-data { +- samsung,pins = "gpa1-4", "gpa1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi0_bus: spi0-bus { +- samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c4_bus: i2c4-bus { +- samsung,pins = "gpa2-0", "gpa2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c5_bus: i2c5-bus { +- samsung,pins = "gpa2-2", "gpa2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi1_bus: spi1-bus { +- samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2s1_bus: i2s1-bus { +- samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", +- "gpb0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pcm1_bus: pcm1-bus { +- samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", +- "gpb0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- ac97_bus: ac97-bus { +- samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", +- "gpb0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2s2_bus: i2s2-bus { +- samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", +- "gpb1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pcm2_bus: pcm2-bus { +- samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", +- "gpb1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spdif_bus: spdif-bus { +- samsung,pins = "gpb1-0", "gpb1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi2_bus: spi2-bus { +- samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c6_bus: i2c6-bus { +- samsung,pins = "gpb1-3", "gpb1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm0_out: pwm0-out { +- samsung,pins = "gpb2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm1_out: pwm1-out { +- samsung,pins = "gpb2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm2_out: pwm2-out { +- samsung,pins = "gpb2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm3_out: pwm3-out { +- samsung,pins = "gpb2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c7_bus: i2c7-bus { +- samsung,pins = "gpb2-2", "gpb2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c0_bus: i2c0-bus { +- samsung,pins = "gpb3-0", "gpb3-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c1_bus: i2c1-bus { +- samsung,pins = "gpb3-2", "gpb3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c0_hs_bus: i2c0-hs-bus { +- samsung,pins = "gpb3-0", "gpb3-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c1_hs_bus: i2c1-hs-bus { +- samsung,pins = "gpb3-2", "gpb3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_clk: sd0-clk { +- samsung,pins = "gpc0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_cmd: sd0-cmd { +- samsung,pins = "gpc0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_cd: sd0-cd { +- samsung,pins = "gpc0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus1: sd0-bus-width1 { +- samsung,pins = "gpc0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus4: sd0-bus-width4 { +- samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus8: sd0-bus-width8 { +- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_clk: sd1-clk { +- samsung,pins = "gpc2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_cmd: sd1-cmd { +- samsung,pins = "gpc2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_cd: sd1-cd { +- samsung,pins = "gpc2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus1: sd1-bus-width1 { +- samsung,pins = "gpc2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus4: sd1-bus-width4 { +- samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_clk: sd2-clk { +- samsung,pins = "gpc3-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cmd: sd2-cmd { +- samsung,pins = "gpc3-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cd: sd2-cd { +- samsung,pins = "gpc3-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus1: sd2-bus-width1 { +- samsung,pins = "gpc3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus4: sd2-bus-width4 { +- samsung,pins = "gpc3-3", "gpc3-4", "gpc3-5", "gpc3-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus8: sd2-bus-width8 { +- samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_clk: sd3-clk { +- samsung,pins = "gpc4-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_cmd: sd3-cmd { +- samsung,pins = "gpc4-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_cd: sd3-cd { +- samsung,pins = "gpc4-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_bus1: sd3-bus-width1 { +- samsung,pins = "gpc4-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_bus4: sd3-bus-width4 { +- samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart1_data: uart1-data { +- samsung,pins = "gpd0-0", "gpd0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart1_fctl: uart1-fctl { +- samsung,pins = "gpd0-2", "gpd0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- dp_hpd: dp_hpd { +- samsung,pins = "gpx0-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hdmi_cec: hdmi-cec { +- samsung,pins = "gpx3-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hdmi_hpd: hdmi-hpd { +- samsung,pins = "gpx3-7"; +- samsung,pin-pud = ; +- }; +-}; +- +-&pinctrl_1 { +- gpe0: gpe0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpe1: gpe1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf0: gpf0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf1: gpf1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg0: gpg0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg1: gpg1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg2: gpg2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gph0: gph0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gph1: gph1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- cam_gpio_a: cam-gpio-a { +- samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", +- "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", +- "gpe1-0", "gpe1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_gpio_b: cam-gpio-b { +- samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", +- "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_i2c2_bus: cam-i2c2-bus { +- samsung,pins = "gpe0-6", "gpe1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_spi1_bus: cam-spi1-bus { +- samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_i2c1_bus: cam-i2c1-bus { +- samsung,pins = "gpf0-2", "gpf0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_i2c0_bus: cam-i2c0-bus { +- samsung,pins = "gpf0-0", "gpf0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_spi0_bus: cam-spi0-bus { +- samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_bayrgb_bus: cam-bayrgb-bus { +- samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", +- "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", +- "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", +- "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", +- "gpg2-0", "gpg2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_port_a: cam-port-a { +- samsung,pins = "gph0-0", "gph0-1", "gph0-2", "gph0-3", +- "gph1-0", "gph1-1", "gph1-2", "gph1-3", +- "gph1-4", "gph1-5", "gph1-6", "gph1-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_2 { +- gpv0: gpv0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpv1: gpv1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpv2: gpv2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpv3: gpv3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpv4: gpv4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- c2c_rxd: c2c-rxd { +- samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", +- "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", +- "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", +- "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- c2c_txd: c2c-txd { +- samsung,pins = "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", +- "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", +- "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", +- "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_3 { +- gpz: gpz { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- i2s0_bus: i2s0-bus { +- samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", +- "gpz-4", "gpz-5", "gpz-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5250-smdk5250.dts b/scripts/dtc/include-prefixes/arm/exynos5250-smdk5250.dts +deleted file mode 100644 +index 39bbe18145cf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5250-smdk5250.dts ++++ /dev/null +@@ -1,419 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung SMDK5250 board device tree source +- * +- * Copyright (c) 2012 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-/dts-v1/; +-#include +-#include +-#include +-#include "exynos5250.dtsi" +- +-/ { +- model = "Samsung SMDK5250 board based on Exynos5250"; +- compatible = "samsung,smdk5250", "samsung,exynos5250", "samsung,exynos5"; +- +- aliases { +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x80000000>; +- }; +- +- chosen { +- bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; +- stdout-path = "serial2:115200n8"; +- }; +- +- vdd: fixed-regulator-vdd { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-supply"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- dbvdd: fixed-regulator-dbvdd { +- compatible = "regulator-fixed"; +- regulator-name = "dbvdd-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- spkvdd: fixed-regulator-spkvdd { +- compatible = "regulator-fixed"; +- regulator-name = "spkvdd-supply"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- sound { +- compatible = "samsung,smdk-wm8994"; +- +- samsung,i2s-controller = <&i2s0>; +- samsung,audio-codec = <&wm8994>; +- }; +- +- fixed-rate-clocks { +- xxti { +- compatible = "samsung,clock-xxti"; +- clock-frequency = <24000000>; +- }; +- +- codec_mclk: codec-mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <16934000>; +- }; +- }; +-}; +- +-&cpu0 { +- cpu0-supply = <&buck2_reg>; +-}; +- +-&dp { +- samsung,color-space = <0>; +- samsung,color-depth = <1>; +- samsung,link-rate = <0x0a>; +- samsung,lane-count = <4>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dp_hpd>; +- status = "okay"; +- +- display-timings { +- native-mode = <&timing0>; +- +- timing0: timing { +- /* 1280x800 */ +- clock-frequency = <50000>; +- hactive = <1280>; +- vactive = <800>; +- hfront-porch = <4>; +- hback-porch = <4>; +- hsync-len = <4>; +- vback-porch = <4>; +- vfront-porch = <4>; +- vsync-len = <4>; +- }; +- }; +-}; +- +-&ehci { +- samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; +-}; +- +-&fimd { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +- ddc = <&i2c_2>; +- hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; +-}; +- +-&i2c_0 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <20000>; +- +- eeprom@50 { +- compatible = "samsung,s524ad0xd1"; +- reg = <0x50>; +- }; +- +- max77686: pmic@9 { +- compatible = "maxim,max77686"; +- reg = <0x09>; +- interrupt-parent = <&gpx3>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&max77686_irq>; +- #clock-cells = <1>; +- wakeup-source; +- +- voltage-regulators { +- ldo1_reg: LDO1 { +- regulator-name = "P1.0V_LDO_OUT1"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "P1.2V_LDO_OUT2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "P1.8V_LDO_OUT3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "P2.8V_LDO_OUT4"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "P1.8V_LDO_OUT5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "P1.1V_LDO_OUT6"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "P1.1V_LDO_OUT7"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "P1.0V_LDO_OUT8"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "P1.8V_LDO_OUT10"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "P1.8V_LDO_OUT11"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "P3.0V_LDO_OUT12"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "P1.8V_LDO_OUT13"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "P1.8V_LDO_OUT14"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "P1.0V_LDO_OUT15"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "P1.8V_LDO_OUT16"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "vdd_mif"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "vdd_int"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "vdd_g3d"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "P1.8V_BUCK_OUT5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&i2c_1 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <20000>; +- +- eeprom@51 { +- compatible = "samsung,s524ad0xd1"; +- reg = <0x51>; +- }; +- +- wm8994: audio-codec@1a { +- compatible = "wlf,wm8994"; +- reg = <0x1a>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- clocks = <&codec_mclk>; +- clock-names = "MCLK1"; +- +- AVDD2-supply = <&vdd>; +- CPVDD-supply = <&vdd>; +- DBVDD-supply = <&dbvdd>; +- SPKVDD1-supply = <&spkvdd>; +- SPKVDD2-supply = <&spkvdd>; +- }; +-}; +- +-&i2c_2 { +- status = "okay"; +- /* used by HDMI DDC */ +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <66000>; +-}; +- +-&i2c_8 { +- status = "okay"; +- /* used by HDMI PHY */ +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <66000>; +-}; +- +-&i2c_9 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <40000>; +-}; +- +-&i2s0 { +- status = "okay"; +-}; +- +-&mixer { +- status = "okay"; +-}; +- +-&mmc_0 { +- status = "okay"; +- broken-cd; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; +- bus-width = <8>; +- cap-mmc-highspeed; +-}; +- +-&mmc_2 { +- status = "okay"; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; +- bus-width = <4>; +- disable-wp; +- cap-sd-highspeed; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&sata_phy { +- status = "okay"; +- samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; +-}; +- +-&sata_phy_i2c { +- status = "okay"; +-}; +- +-&spi_1 { +- status = "okay"; +- cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "w25x80"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- +- controller-data { +- samsung,spi-feedback-delay = <0>; +- }; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0x0 0x40000>; +- read-only; +- }; +- +- partition@40000 { +- label = "Kernel"; +- reg = <0x40000 0xc0000>; +- }; +- }; +-}; +- +-&pinctrl_0 { +- max77686_irq: max77686-irq { +- samsung,pins = "gpx3-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5250-snow-common.dtsi b/scripts/dtc/include-prefixes/arm/exynos5250-snow-common.dtsi +deleted file mode 100644 +index 2335c4687349..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5250-snow-common.dtsi ++++ /dev/null +@@ -1,709 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Google Snow board device tree source +- * +- * Copyright (c) 2012 Google, Inc +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include "exynos5250.dtsi" +- +-/ { +- aliases { +- i2c104 = &i2c_104; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x80000000>; +- }; +- +- chosen { +- bootargs = "console=tty1"; +- stdout-path = "serial3:115200n8"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&power_key_irq &lid_irq>; +- +- power { +- label = "Power"; +- gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- lid-switch { +- label = "Lid"; +- gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; +- linux,input-type = <5>; /* EV_SW */ +- linux,code = <0>; /* SW_LID */ +- debounce-interval = <1>; +- wakeup-source; +- }; +- }; +- +- vbat: vbat-fixed-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vbat-supply"; +- regulator-boot-on; +- }; +- +- i2c-arbitrator { +- compatible = "i2c-arb-gpio-challenge"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c-parent = <&i2c_4>; +- +- our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>; +- their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>; +- slew-delay-us = <10>; +- wait-retry-us = <3000>; +- wait-free-us = <50000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&arb_our_claim &arb_their_claim>; +- +- /* Use ID 104 as a hint that we're on physical bus 4 */ +- i2c_104: i2c@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- battery: sbs-battery@b { +- compatible = "sbs,sbs-battery"; +- reg = <0xb>; +- sbs,poll-retry-count = <1>; +- }; +- +- cros_ec: embedded-controller@1e { +- compatible = "google,cros-ec-i2c"; +- reg = <0x1e>; +- interrupts = <6 IRQ_TYPE_NONE>; +- interrupt-parent = <&gpx1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ec_irq>; +- wakeup-source; +- }; +- +- power-regulator@48 { +- compatible = "ti,tps65090"; +- reg = <0x48>; +- +- /* +- * Config irq to disable internal pulls +- * even though we run in polling mode. +- */ +- pinctrl-names = "default"; +- pinctrl-0 = <&tps65090_irq>; +- +- vsys1-supply = <&vbat>; +- vsys2-supply = <&vbat>; +- vsys3-supply = <&vbat>; +- infet1-supply = <&vbat>; +- infet2-supply = <&vbat>; +- infet3-supply = <&vbat>; +- infet4-supply = <&vbat>; +- infet5-supply = <&vbat>; +- infet6-supply = <&vbat>; +- infet7-supply = <&vbat>; +- vsys-l1-supply = <&vbat>; +- vsys-l2-supply = <&vbat>; +- +- regulators { +- dcdc1 { +- ti,enable-ext-control; +- }; +- dcdc2 { +- ti,enable-ext-control; +- }; +- dcdc3 { +- ti,enable-ext-control; +- }; +- fet1: fet1 { +- regulator-name = "vcd_led"; +- ti,overcurrent-wait = <3>; +- }; +- tps65090_fet2: fet2 { +- regulator-name = "video_mid"; +- regulator-always-on; +- ti,overcurrent-wait = <3>; +- }; +- fet3 { +- regulator-name = "wwan_r"; +- regulator-always-on; +- ti,overcurrent-wait = <3>; +- }; +- fet4 { +- regulator-name = "sdcard"; +- ti,overcurrent-wait = <3>; +- }; +- fet5 { +- regulator-name = "camout"; +- regulator-always-on; +- ti,overcurrent-wait = <3>; +- }; +- fet6: fet6 { +- regulator-name = "lcd_vdd"; +- ti,overcurrent-wait = <3>; +- }; +- tps65090_fet7: fet7 { +- regulator-name = "video_mid_1a"; +- regulator-always-on; +- ti,overcurrent-wait = <3>; +- }; +- ldo1 { +- }; +- ldo2 { +- }; +- }; +- +- charger { +- compatible = "ti,tps65090-charger"; +- }; +- }; +- }; +- }; +- +- sound { +- samsung,i2s-controller = <&i2s0>; +- }; +- +- usb3_vbus_reg: regulator-usb3 { +- compatible = "regulator-fixed"; +- regulator-name = "P5.0V_USB3CON"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb3_vbus_en>; +- enable-active-high; +- }; +- +- fixed-rate-clocks { +- xxti { +- compatible = "samsung,clock-xxti"; +- clock-frequency = <24000000>; +- }; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 1000000 0>; +- brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; +- default-brightness-level = <7>; +- enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>; +- power-supply = <&fet1>; +- pinctrl-0 = <&pwm0_out>; +- pinctrl-names = "default"; +- }; +- +- panel: panel { +- compatible = "auo,b116xw03"; +- power-supply = <&fet6>; +- backlight = <&backlight>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&bridge_out>; +- }; +- }; +- }; +- +- mmc3_pwrseq: mmc3-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpx0 2 GPIO_ACTIVE_LOW>, /* WIFI_RSTn */ +- <&gpx0 1 GPIO_ACTIVE_LOW>; /* WIFI_EN */ +- clocks = <&max77686 MAX77686_CLK_PMIC>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&clock { +- assigned-clocks = <&clock CLK_FOUT_EPLL>; +- assigned-clock-rates = <49152000>; +-}; +- +-&clock_audss { +- assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; +- assigned-clock-parents = <&clock CLK_FOUT_EPLL>; +-}; +- +-&cpu0 { +- cpu0-supply = <&buck2_reg>; +-}; +- +-&dp { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dp_hpd>; +- samsung,color-space = <0>; +- samsung,color-depth = <1>; +- samsung,link-rate = <0x0a>; +- samsung,lane-count = <2>; +- hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>; +- +- ports { +- port { +- dp_out: endpoint { +- remote-endpoint = <&bridge_in>; +- }; +- }; +- }; +-}; +- +-&ehci { +- samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; +-}; +- +-&fimd { +- status = "okay"; +- samsung,invert-vclk; +-}; +- +-&hdmi { +- status = "okay"; +- hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_hpd_irq>; +- ddc = <&i2c_2>; +- hdmi-en-supply = <&tps65090_fet7>; +- vdd-supply = <&ldo8_reg>; +- vdd_osc-supply = <&ldo10_reg>; +- vdd_pll-supply = <&ldo8_reg>; +-}; +- +-&hdmicec { +- status = "okay"; +-}; +- +-&i2c_0 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <378000>; +- +- max77686: pmic@9 { +- compatible = "maxim,max77686"; +- interrupt-parent = <&gpx3>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&max77686_irq>; +- wakeup-source; +- reg = <0x09>; +- #clock-cells = <1>; +- +- voltage-regulators { +- ldo1_reg: LDO1 { +- regulator-name = "P1.0V_LDO_OUT1"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "P1.8V_LDO_OUT2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "P1.8V_LDO_OUT3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "P1.1V_LDO_OUT7"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "P1.0V_LDO_OUT8"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "P1.8V_LDO_OUT10"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "P3.0V_LDO_OUT12"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "P1.8V_LDO_OUT14"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "P1.0V_LDO_OUT15"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "P1.8V_LDO_OUT16"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "vdd_mif"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "vdd_int"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "vdd_g3d"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "P1.8V_BUCK_OUT5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck6_reg: BUCK6 { +- regulator-name = "P1.35V_BUCK_OUT6"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- }; +- +- buck7_reg: BUCK7 { +- regulator-name = "P2.0V_BUCK_OUT7"; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- regulator-always-on; +- }; +- +- buck8_reg: BUCK8 { +- regulator-name = "P2.85V_BUCK_OUT8"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c_1 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <378000>; +- +- trackpad@67 { +- reg = <0x67>; +- compatible = "cypress,cyapa"; +- interrupts = <2 IRQ_TYPE_NONE>; +- interrupt-parent = <&gpx1>; +- wakeup-source; +- }; +-}; +- +-/* +- * Disabled pullups since external part has its own pullups and +- * double-pulling gets us out of spec in some cases. +- */ +-&i2c2_bus { +- samsung,pin-pud = ; +-}; +- +-&i2c_2 { +- status = "okay"; +- /* used by HDMI DDC */ +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <66000>; +-}; +- +-&i2c_3 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <66000>; +-}; +- +-&i2c_4 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <66000>; +-}; +- +-&i2c_5 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <66000>; +-}; +- +-&i2c_7 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <66000>; +- +- ptn3460: lvds-bridge@20 { +- compatible = "nxp,ptn3460"; +- reg = <0x20>; +- powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>; +- edid-emulation = <5>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- bridge_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- bridge_in: endpoint { +- remote-endpoint = <&dp_out>; +- }; +- }; +- }; +- }; +-}; +- +-&i2c_8 { +- status = "okay"; +- /* used by HDMI PHY */ +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <378000>; +-}; +- +-&i2s0 { +- assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; +- assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>; +- status = "okay"; +-}; +- +-&mali { +- mali-supply = <&buck4_reg>; +- status = "okay"; +-}; +- +-&mixer { +- status = "okay"; +-}; +- +-/* eMMC flash */ +-&mmc_0 { +- status = "okay"; +- non-removable; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; +- bus-width = <8>; +- cap-mmc-highspeed; +-}; +- +-/* uSD card */ +-&mmc_2 { +- status = "okay"; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; +- bus-width = <4>; +- wp-gpios = <&gpc2 1 GPIO_ACTIVE_HIGH>; +- cap-sd-highspeed; +-}; +- +-/* +- * On Snow we've got SIP WiFi and so can keep drive strengths low to +- * reduce EMI. +- * +- * WiFi SDIO module +- */ +-&mmc_3 { +- status = "okay"; +- non-removable; +- cap-sdio-irq; +- keep-power-in-suspend; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4 &wifi_en &wifi_rst>; +- bus-width = <4>; +- cap-sd-highspeed; +- mmc-pwrseq = <&mmc3_pwrseq>; +-}; +- +-&pinctrl_0 { +- wifi_en: wifi-en { +- samsung,pins = "gpx0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- wifi_rst: wifi-rst { +- samsung,pins = "gpx0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- power_key_irq: power-key-irq { +- samsung,pins = "gpx1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- ec_irq: ec-irq { +- samsung,pins = "gpx1-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- tps65090_irq: tps65090-irq { +- samsung,pins = "gpx2-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- usb3_vbus_en: usb3-vbus-en { +- samsung,pins = "gpx2-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- max77686_irq: max77686-irq { +- samsung,pins = "gpx3-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lid_irq: lid-irq { +- samsung,pins = "gpx3-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hdmi_hpd_irq: hdmi-hpd-irq { +- samsung,pins = "gpx3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_1 { +- arb_their_claim: arb-their-claim { +- samsung,pins = "gpe0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- arb_our_claim: arb-our-claim { +- samsung,pins = "gpf0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pmu_system_controller { +- assigned-clocks = <&pmu_system_controller 0>; +- assigned-clock-parents = <&clock CLK_FIN_PLL>; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&sd3_bus4 { +- samsung,pin-drv = ; +-}; +- +-&sd3_clk { +- samsung,pin-drv = ; +-}; +- +-&sd3_cmd { +- samsung,pin-pud = ; +- samsung,pin-drv = ; +-}; +- +-&spi_1 { +- status = "okay"; +- samsung,spi-src-clk = <0>; +- num-cs = <1>; +- cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; +-}; +- +-&usbdrd_dwc3 { +- dr_mode = "host"; +-}; +- +-&usbdrd_phy { +- vbus-supply = <&usb3_vbus_reg>; +-}; +- +-#include "cros-ec-keyboard.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/exynos5250-snow-rev5.dts b/scripts/dtc/include-prefixes/arm/exynos5250-snow-rev5.dts +deleted file mode 100644 +index 0822b778c035..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5250-snow-rev5.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Google Snow Rev 5+ board device tree source +- * +- * Copyright (c) 2012 Google, Inc +- * Copyright (c) 2015 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-/dts-v1/; +-#include "exynos5250-snow-common.dtsi" +- +-/ { +- model = "Google Snow Rev 5+"; +- compatible = "google,snow-rev5", "samsung,exynos5250", +- "samsung,exynos5"; +- +- sound { +- compatible = "google,snow-audio-max98090"; +- +- samsung,model = "Snow-I2S-MAX98090"; +- samsung,audio-codec = <&max98090>; +- +- cpu { +- sound-dai = <&i2s0 0>; +- }; +- +- codec { +- sound-dai = <&max98090 0>, <&hdmi>; +- }; +- }; +-}; +- +-&i2c_7 { +- max98090: audio-codec@10 { +- compatible = "maxim,max98090"; +- reg = <0x10>; +- interrupts = <4 IRQ_TYPE_NONE>; +- interrupt-parent = <&gpx0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&max98090_irq>; +- clocks = <&pmu_system_controller 0>; +- clock-names = "mclk"; +- #sound-dai-cells = <1>; +- }; +-}; +- +-&pinctrl_0 { +- max98090_irq: max98090-irq { +- samsung,pins = "gpx0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5250-snow.dts b/scripts/dtc/include-prefixes/arm/exynos5250-snow.dts +deleted file mode 100644 +index 9946dce54d74..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5250-snow.dts ++++ /dev/null +@@ -1,51 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Google Snow board device tree source +- * +- * Copyright (c) 2012 Google, Inc +- */ +- +-/dts-v1/; +-#include "exynos5250-snow-common.dtsi" +- +-/ { +- model = "Google Snow"; +- compatible = "google,snow-rev4", "google,snow", "samsung,exynos5250", +- "samsung,exynos5"; +- +- sound { +- compatible = "google,snow-audio-max98095"; +- +- samsung,model = "Snow-I2S-MAX98095"; +- samsung,audio-codec = <&max98095>; +- +- cpu { +- sound-dai = <&i2s0 0>; +- }; +- +- codec { +- sound-dai = <&max98095 0>, <&hdmi>; +- }; +- }; +-}; +- +-&i2c_7 { +- max98095: audio-codec@11 { +- compatible = "maxim,max98095"; +- reg = <0x11>; +- pinctrl-names = "default"; +- pinctrl-0 = <&max98095_en>; +- clocks = <&pmu_system_controller 0>; +- clock-names = "mclk"; +- #sound-dai-cells = <1>; +- }; +-}; +- +-&pinctrl_0 { +- max98095_en: max98095-en { +- samsung,pins = "gpx1-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5250-spring.dts b/scripts/dtc/include-prefixes/arm/exynos5250-spring.dts +deleted file mode 100644 +index fba1462b19df..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5250-spring.dts ++++ /dev/null +@@ -1,555 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Google Spring board device tree source +- * +- * Copyright (c) 2013 Google, Inc +- * Copyright (c) 2014 SUSE LINUX Products GmbH +- */ +- +-/dts-v1/; +-#include +-#include +-#include +-#include +-#include "exynos5250.dtsi" +- +-/ { +- model = "Google Spring"; +- compatible = "google,spring", "samsung,exynos5250", "samsung,exynos5"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x80000000>; +- }; +- +- chosen { +- bootargs = "console=tty1"; +- stdout-path = "serial3:115200n8"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&power_key_irq>, <&lid_irq>; +- +- power { +- label = "Power"; +- gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- lid-switch { +- label = "Lid"; +- gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; +- linux,input-type = <5>; /* EV_SW */ +- linux,code = <0>; /* SW_LID */ +- debounce-interval = <1>; +- wakeup-source; +- }; +- }; +- +- usb-hub { +- compatible = "smsc,usb3503a"; +- reset-gpios = <&gpe1 0 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hsic_reset>; +- }; +- +- fixed-rate-clocks { +- xxti { +- compatible = "samsung,clock-xxti"; +- clock-frequency = <24000000>; +- }; +- }; +-}; +- +-&cpu0 { +- cpu0-supply = <&buck2_reg>; +-}; +- +-&dp { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dp_hpd_gpio>; +- samsung,color-space = <0>; +- samsung,color-depth = <1>; +- samsung,link-rate = <0x0a>; +- samsung,lane-count = <1>; +- hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>; +-}; +- +-&ehci { +- samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; +-}; +- +-&fimd { +- status = "okay"; +- samsung,invert-vclk; +-}; +- +-&hdmi { +- status = "okay"; +- hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_hpd_irq>; +- ddc = <&i2c_2>; +- hdmi-en-supply = <&ldo8_reg>; +- vdd-supply = <&ldo8_reg>; +- vdd_osc-supply = <&ldo10_reg>; +- vdd_pll-supply = <&ldo8_reg>; +-}; +- +-&i2c_0 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <378000>; +- +- pmic@66 { +- compatible = "samsung,s5m8767-pmic"; +- reg = <0x66>; +- interrupt-parent = <&gpx3>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&s5m8767_irq &s5m8767_dvs &s5m8767_ds>; +- wakeup-source; +- +- s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, /* DVS1 */ +- <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */ +- <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */ +- +- s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, /* SET1 */ +- <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */ +- <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */ +- +- /* +- * The following arrays of DVS voltages are not used, since we are +- * not using GPIOs to control PMIC bucks, but they must be defined +- * to please the driver. +- */ +- s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>, +- <1250000>, <1200000>, +- <1150000>, <1100000>, +- <1000000>, <950000>; +- +- s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, +- <1100000>, <1100000>, +- <1000000>, <1000000>, +- <1000000>, <1000000>; +- +- s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, +- <1200000>, <1200000>, +- <1200000>, <1200000>, +- <1200000>, <1200000>; +- +- s5m8767_osc: clocks { +- compatible = "samsung,s5m8767-clk"; +- #clock-cells = <1>; +- clock-output-names = "en32khz_ap", +- "en32khz_cp", +- "en32khz_bt"; +- }; +- +- regulators { +- ldo4_reg: LDO4 { +- regulator-name = "P1.0V_LDO_OUT4"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- op_mode = <0>; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "P1.0V_LDO_OUT5"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- op_mode = <0>; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "vdd_mydp"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- op_mode = <3>; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "P1.1V_LDO_OUT7"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- op_mode = <3>; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "P1.0V_LDO_OUT8"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- op_mode = <3>; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "P1.8V_LDO_OUT10"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <3>; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "P1.8V_LDO_OUT11"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <0>; +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "P3.0V_LDO_OUT12"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- op_mode = <3>; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "P1.8V_LDO_OUT13"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <0>; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "P1.8V_LDO_OUT14"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <3>; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "P1.0V_LDO_OUT15"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- op_mode = <3>; +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "P1.8V_LDO_OUT16"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- op_mode = <3>; +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "P2.8V_LDO_OUT17"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- op_mode = <0>; +- }; +- +- ldo25_reg: LDO25 { +- regulator-name = "vdd_bridge"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- op_mode = <1>; +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "vdd_mif"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <3>; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <3>; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "vdd_int"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <3>; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "vdd_g3d"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- op_mode = <3>; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "P1.8V_BUCK_OUT5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <1>; +- }; +- +- buck6_reg: BUCK6 { +- regulator-name = "P1.2V_BUCK_OUT6"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <0>; +- }; +- +- buck9_reg: BUCK9 { +- regulator-name = "vdd_ummc"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- op_mode = <3>; +- }; +- }; +- }; +-}; +- +-&i2c_1 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <378000>; +- +- trackpad@4b { +- compatible = "atmel,maxtouch"; +- reg = <0x4b>; +- interrupt-parent = <&gpx1>; +- interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&trackpad_irq>; +- linux,gpio-keymap = ; +- wakeup-source; +- }; +-}; +- +-/* +- * Disabled pullups since external part has its own pullups and +- * double-pulling gets us out of spec in some cases. +- */ +-&i2c2_bus { +- samsung,pin-pud = ; +-}; +- +-&i2c_2 { +- status = "okay"; +- /* used by HDMI DDC */ +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <66000>; +-}; +- +-&i2c_3 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <66000>; +-}; +- +-&i2c_4 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <66000>; +- +- cros_ec: embedded-controller@1e { +- compatible = "google,cros-ec-i2c"; +- reg = <0x1e>; +- interrupts = <6 IRQ_TYPE_NONE>; +- interrupt-parent = <&gpx1>; +- wakeup-source; +- pinctrl-names = "default"; +- pinctrl-0 = <&ec_irq>; +- }; +-}; +- +-&i2c_5 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <66000>; +-}; +- +-&i2c_7 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <66000>; +- +- temperature-sensor@4c { +- compatible = "gmt,g781"; +- reg = <0x4c>; +- }; +-}; +- +-&i2c_8 { +- status = "okay"; +- /* used by HDMI PHY */ +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <378000>; +-}; +- +-&i2s0 { +- status = "okay"; +-}; +- +-&mixer { +- status = "okay"; +-}; +- +-&mmc_0 { +- status = "okay"; +- broken-cd; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; +- bus-width = <8>; +- cap-mmc-highspeed; +-}; +- +-/* +- * On Spring we've got SIP WiFi and so can keep drive strengths low to +- * reduce EMI. +- */ +-&mmc_1 { +- status = "okay"; +- broken-cd; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; +- bus-width = <4>; +- cap-sd-highspeed; +-}; +- +-&pinctrl_0 { +- s5m8767_dvs: s5m8767-dvs { +- samsung,pins = "gpd1-0", "gpd1-1", "gpd1-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- dp_hpd_gpio: dp-hpd { +- samsung,pins = "gpc3-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- trackpad_irq: trackpad-irq { +- samsung,pins = "gpx1-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- power_key_irq: power-key-irq { +- samsung,pins = "gpx1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- ec_irq: ec-irq { +- samsung,pins = "gpx1-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- s5m8767_ds: s5m8767-ds { +- samsung,pins = "gpx2-3", "gpx2-4", "gpx2-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- s5m8767_irq: s5m8767-irq { +- samsung,pins = "gpx3-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lid_irq: lid-irq { +- samsung,pins = "gpx3-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hdmi_hpd_irq: hdmi-hpd-irq { +- samsung,pins = "gpx3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_1 { +- hsic_reset: hsic-reset { +- samsung,pins = "gpe1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&sd1_bus4 { +- samsung,pin-drv = ; +-}; +- +-&sd1_cd { +- samsung,pin-drv = ; +-}; +- +-&sd1_clk { +- samsung,pin-drv = ; +-}; +- +-&sd1_cmd { +- samsung,pin-pud = ; +- samsung,pin-drv = ; +-}; +- +-&spi_1 { +- status = "okay"; +- samsung,spi-src-clk = <0>; +- num-cs = <1>; +-}; +- +-#include "cros-ec-keyboard.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/exynos5250.dtsi b/scripts/dtc/include-prefixes/arm/exynos5250.dtsi +deleted file mode 100644 +index 4ffa9253b566..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5250.dtsi ++++ /dev/null +@@ -1,1243 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung Exynos5250 SoC device tree source +- * +- * Copyright (c) 2012 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Samsung Exynos5250 SoC device nodes are listed in this file. +- * Exynos5250 based board files can include this file and provide +- * values for board specfic bindings. +- * +- * Note: This file does not include device nodes for all the controllers in +- * Exynos5250 SoC. As device tree coverage for Exynos5250 increases, +- * additional nodes can be added to this file. +- */ +- +-#include +-#include "exynos5.dtsi" +-#include "exynos4-cpu-thermal.dtsi" +-#include +- +-/ { +- compatible = "samsung,exynos5250", "samsung,exynos5"; +- +- aliases { +- spi0 = &spi_0; +- spi1 = &spi_1; +- spi2 = &spi_2; +- gsc0 = &gsc_0; +- gsc1 = &gsc_1; +- gsc2 = &gsc_2; +- gsc3 = &gsc_3; +- mshc0 = &mmc_0; +- mshc1 = &mmc_1; +- mshc2 = &mmc_2; +- mshc3 = &mmc_3; +- i2c4 = &i2c_4; +- i2c5 = &i2c_5; +- i2c6 = &i2c_6; +- i2c7 = &i2c_7; +- i2c8 = &i2c_8; +- i2c9 = &i2c_9; +- pinctrl0 = &pinctrl_0; +- pinctrl1 = &pinctrl_1; +- pinctrl2 = &pinctrl_2; +- pinctrl3 = &pinctrl_3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- }; +- }; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0>; +- clocks = <&clock CLK_ARM_CLK>; +- clock-names = "cpu"; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <1>; +- clocks = <&clock CLK_ARM_CLK>; +- clock-names = "cpu"; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- }; +- +- cpu0_opp_table: opp-table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- opp-microvolt = <925000>; +- clock-latency-ns = <140000>; +- }; +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <937500>; +- clock-latency-ns = <140000>; +- }; +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <950000>; +- clock-latency-ns = <140000>; +- }; +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <975000>; +- clock-latency-ns = <140000>; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <1000000>; +- clock-latency-ns = <140000>; +- }; +- opp-700000000 { +- opp-hz = /bits/ 64 <700000000>; +- opp-microvolt = <1012500>; +- clock-latency-ns = <140000>; +- }; +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <1025000>; +- clock-latency-ns = <140000>; +- }; +- opp-900000000 { +- opp-hz = /bits/ 64 <900000000>; +- opp-microvolt = <1050000>; +- clock-latency-ns = <140000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <1075000>; +- clock-latency-ns = <140000>; +- opp-suspend; +- }; +- opp-1100000000 { +- opp-hz = /bits/ 64 <1100000000>; +- opp-microvolt = <1100000>; +- clock-latency-ns = <140000>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <1125000>; +- clock-latency-ns = <140000>; +- }; +- opp-1300000000 { +- opp-hz = /bits/ 64 <1300000000>; +- opp-microvolt = <1150000>; +- clock-latency-ns = <140000>; +- }; +- opp-1400000000 { +- opp-hz = /bits/ 64 <1400000000>; +- opp-microvolt = <1200000>; +- clock-latency-ns = <140000>; +- }; +- opp-1500000000 { +- opp-hz = /bits/ 64 <1500000000>; +- opp-microvolt = <1225000>; +- clock-latency-ns = <140000>; +- }; +- opp-1600000000 { +- opp-hz = /bits/ 64 <1600000000>; +- opp-microvolt = <1250000>; +- clock-latency-ns = <140000>; +- }; +- opp-1700000000 { +- opp-hz = /bits/ 64 <1700000000>; +- opp-microvolt = <1300000>; +- clock-latency-ns = <140000>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a15-pmu"; +- interrupt-parent = <&combiner>; +- interrupts = <1 2>, <22 4>; +- }; +- +- soc: soc { +- sram@2020000 { +- compatible = "mmio-sram"; +- reg = <0x02020000 0x30000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x02020000 0x30000>; +- +- smp-sram@0 { +- compatible = "samsung,exynos4210-sysram"; +- reg = <0x0 0x1000>; +- }; +- +- smp-sram@2f000 { +- compatible = "samsung,exynos4210-sysram-ns"; +- reg = <0x2f000 0x1000>; +- }; +- }; +- +- pd_gsc: power-domain@10044000 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10044000 0x20>; +- #power-domain-cells = <0>; +- label = "GSC"; +- }; +- +- pd_mfc: power-domain@10044040 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10044040 0x20>; +- #power-domain-cells = <0>; +- label = "MFC"; +- }; +- +- pd_g3d: power-domain@10044060 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10044060 0x20>; +- #power-domain-cells = <0>; +- label = "G3D"; +- }; +- +- pd_disp1: power-domain@100440a0 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x100440A0 0x20>; +- #power-domain-cells = <0>; +- label = "DISP1"; +- }; +- +- pd_mau: power-domain@100440c0 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x100440C0 0x20>; +- #power-domain-cells = <0>; +- label = "MAU"; +- }; +- +- clock: clock-controller@10010000 { +- compatible = "samsung,exynos5250-clock"; +- reg = <0x10010000 0x30000>; +- #clock-cells = <1>; +- }; +- +- clock_audss: audss-clock-controller@3810000 { +- compatible = "samsung,exynos5250-audss-clock"; +- reg = <0x03810000 0x0C>; +- #clock-cells = <1>; +- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, +- <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; +- clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; +- power-domains = <&pd_mau>; +- }; +- +- timer@101c0000 { +- compatible = "samsung,exynos4210-mct"; +- reg = <0x101C0000 0x800>; +- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; +- clock-names = "fin_pll", "mct"; +- interrupts-extended = <&combiner 23 3>, +- <&combiner 23 4>, +- <&combiner 25 2>, +- <&combiner 25 3>, +- <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- pinctrl_0: pinctrl@11400000 { +- compatible = "samsung,exynos5250-pinctrl"; +- reg = <0x11400000 0x1000>; +- interrupts = ; +- +- wakup_eint: wakeup-interrupt-controller { +- compatible = "samsung,exynos4210-wakeup-eint"; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +- +- pinctrl_1: pinctrl@13400000 { +- compatible = "samsung,exynos5250-pinctrl"; +- reg = <0x13400000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_2: pinctrl@10d10000 { +- compatible = "samsung,exynos5250-pinctrl"; +- reg = <0x10d10000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_3: pinctrl@3860000 { +- compatible = "samsung,exynos5250-pinctrl"; +- reg = <0x03860000 0x1000>; +- interrupts = ; +- power-domains = <&pd_mau>; +- }; +- +- pmu_system_controller: system-controller@10040000 { +- compatible = "samsung,exynos5250-pmu", "syscon"; +- reg = <0x10040000 0x5000>; +- clock-names = "clkout16"; +- clocks = <&clock CLK_FIN_PLL>; +- #clock-cells = <1>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- }; +- +- watchdog@101d0000 { +- compatible = "samsung,exynos5250-wdt"; +- reg = <0x101D0000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_WDT>; +- clock-names = "watchdog"; +- samsung,syscon-phandle = <&pmu_system_controller>; +- }; +- +- mfc: codec@11000000 { +- compatible = "samsung,mfc-v6"; +- reg = <0x11000000 0x10000>; +- interrupts = ; +- power-domains = <&pd_mfc>; +- clocks = <&clock CLK_MFC>; +- clock-names = "mfc"; +- iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; +- iommu-names = "left", "right"; +- }; +- +- rotator: rotator@11c00000 { +- compatible = "samsung,exynos5250-rotator"; +- reg = <0x11C00000 0x64>; +- interrupts = ; +- clocks = <&clock CLK_ROTATOR>; +- clock-names = "rotator"; +- iommus = <&sysmmu_rotator>; +- }; +- +- mali: gpu@11800000 { +- compatible = "samsung,exynos5250-mali", "arm,mali-t604"; +- reg = <0x11800000 0x5000>; +- interrupts = , +- , +- ; +- interrupt-names = "job", "mmu", "gpu"; +- clocks = <&clock CLK_G3D>; +- clock-names = "core"; +- operating-points-v2 = <&gpu_opp_table>; +- power-domains = <&pd_g3d>; +- status = "disabled"; +- +- gpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- opp-microvolt = <925000>; +- }; +- opp-160000000 { +- opp-hz = /bits/ 64 <160000000>; +- opp-microvolt = <925000>; +- }; +- opp-266000000 { +- opp-hz = /bits/ 64 <266000000>; +- opp-microvolt = <1025000>; +- }; +- opp-350000000 { +- opp-hz = /bits/ 64 <350000000>; +- opp-microvolt = <1075000>; +- }; +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <1125000>; +- }; +- opp-450000000 { +- opp-hz = /bits/ 64 <450000000>; +- opp-microvolt = <1150000>; +- }; +- opp-533000000 { +- opp-hz = /bits/ 64 <533000000>; +- opp-microvolt = <1250000>; +- }; +- }; +- }; +- +- tmu: tmu@10060000 { +- compatible = "samsung,exynos5250-tmu"; +- reg = <0x10060000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_TMU>; +- clock-names = "tmu_apbif"; +- #thermal-sensor-cells = <0>; +- }; +- +- sata: sata@122f0000 { +- compatible = "snps,dwc-ahci"; +- samsung,sata-freq = <66>; +- reg = <0x122F0000 0x1ff>; +- interrupts = ; +- clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; +- clock-names = "sata", "sclk_sata"; +- phys = <&sata_phy>; +- phy-names = "sata-phy"; +- ports-implemented = <0x1>; +- status = "disabled"; +- }; +- +- sata_phy: sata-phy@12170000 { +- compatible = "samsung,exynos5250-sata-phy"; +- reg = <0x12170000 0x1ff>; +- clocks = <&clock CLK_SATA_PHYCTRL>; +- clock-names = "sata_phyctrl"; +- #phy-cells = <0>; +- samsung,syscon-phandle = <&pmu_system_controller>; +- status = "disabled"; +- }; +- +- /* i2c_0-3 are defined in exynos5.dtsi */ +- i2c_4: i2c@12ca0000 { +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x12CA0000 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clock CLK_I2C4>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_bus>; +- status = "disabled"; +- }; +- +- i2c_5: i2c@12cb0000 { +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x12CB0000 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clock CLK_I2C5>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_bus>; +- status = "disabled"; +- }; +- +- i2c_6: i2c@12cc0000 { +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x12CC0000 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clock CLK_I2C6>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c6_bus>; +- status = "disabled"; +- }; +- +- i2c_7: i2c@12cd0000 { +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x12CD0000 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clock CLK_I2C7>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c7_bus>; +- status = "disabled"; +- }; +- +- i2c_8: i2c@12ce0000 { +- compatible = "samsung,s3c2440-hdmiphy-i2c"; +- reg = <0x12CE0000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clock CLK_I2C_HDMI>; +- clock-names = "i2c"; +- status = "disabled"; +- +- hdmiphy: hdmiphy@38 { +- compatible = "samsung,exynos4212-hdmiphy"; +- reg = <0x38>; +- }; +- }; +- +- i2c_9: i2c@121d0000 { +- compatible = "samsung,exynos5-sata-phy-i2c"; +- reg = <0x121D0000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clock CLK_SATA_PHYI2C>; +- clock-names = "i2c"; +- status = "disabled"; +- +- sata_phy_i2c: sata-phy-i2c@38 { +- compatible = "samsung,exynos-sataphy-i2c"; +- reg = <0x38>; +- status = "disabled"; +- }; +- }; +- +- spi_0: spi@12d20000 { +- compatible = "samsung,exynos4210-spi"; +- status = "disabled"; +- reg = <0x12d20000 0x100>; +- interrupts = ; +- dmas = <&pdma0 5 +- &pdma0 4>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; +- clock-names = "spi", "spi_busclk0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_bus>; +- }; +- +- spi_1: spi@12d30000 { +- compatible = "samsung,exynos4210-spi"; +- status = "disabled"; +- reg = <0x12d30000 0x100>; +- interrupts = ; +- dmas = <&pdma1 5 +- &pdma1 4>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; +- clock-names = "spi", "spi_busclk0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_bus>; +- }; +- +- spi_2: spi@12d40000 { +- compatible = "samsung,exynos4210-spi"; +- status = "disabled"; +- reg = <0x12d40000 0x100>; +- interrupts = ; +- dmas = <&pdma0 7 +- &pdma0 6>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; +- clock-names = "spi", "spi_busclk0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_bus>; +- }; +- +- mmc_0: mmc@12200000 { +- compatible = "samsung,exynos5250-dw-mshc"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x12200000 0x1000>; +- clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x80>; +- status = "disabled"; +- }; +- +- mmc_1: mmc@12210000 { +- compatible = "samsung,exynos5250-dw-mshc"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x12210000 0x1000>; +- clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x80>; +- status = "disabled"; +- }; +- +- mmc_2: mmc@12220000 { +- compatible = "samsung,exynos5250-dw-mshc"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x12220000 0x1000>; +- clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x80>; +- status = "disabled"; +- }; +- +- mmc_3: mmc@12230000 { +- compatible = "samsung,exynos5250-dw-mshc"; +- reg = <0x12230000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x80>; +- status = "disabled"; +- }; +- +- i2s0: i2s@3830000 { +- compatible = "samsung,s5pv210-i2s"; +- status = "disabled"; +- reg = <0x03830000 0x100>; +- dmas = <&pdma0 10>, +- <&pdma0 9>, +- <&pdma0 8>; +- dma-names = "tx", "rx", "tx-sec"; +- clocks = <&clock_audss EXYNOS_I2S_BUS>, +- <&clock_audss EXYNOS_I2S_BUS>, +- <&clock_audss EXYNOS_SCLK_I2S>; +- clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; +- samsung,idma-addr = <0x03000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s0_bus>; +- power-domains = <&pd_mau>; +- #clock-cells = <1>; +- #sound-dai-cells = <1>; +- }; +- +- i2s1: i2s@12d60000 { +- compatible = "samsung,s3c6410-i2s"; +- status = "disabled"; +- reg = <0x12D60000 0x100>; +- dmas = <&pdma1 12>, +- <&pdma1 11>; +- dma-names = "tx", "rx"; +- clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; +- clock-names = "iis", "i2s_opclk0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s1_bus>; +- power-domains = <&pd_mau>; +- #sound-dai-cells = <1>; +- }; +- +- i2s2: i2s@12d70000 { +- compatible = "samsung,s3c6410-i2s"; +- status = "disabled"; +- reg = <0x12D70000 0x100>; +- dmas = <&pdma0 12>, +- <&pdma0 11>; +- dma-names = "tx", "rx"; +- clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; +- clock-names = "iis", "i2s_opclk0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s2_bus>; +- power-domains = <&pd_mau>; +- #sound-dai-cells = <1>; +- }; +- +- usb_dwc3 { +- compatible = "samsung,exynos5250-dwusb3"; +- clocks = <&clock CLK_USB3>; +- clock-names = "usbdrd30"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- usbdrd_dwc3: usb@12000000 { +- compatible = "snps,dwc3"; +- reg = <0x12000000 0x10000>; +- interrupts = ; +- phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; +- phy-names = "usb2-phy", "usb3-phy"; +- }; +- }; +- +- usbdrd_phy: phy@12100000 { +- compatible = "samsung,exynos5250-usbdrd-phy"; +- reg = <0x12100000 0x100>; +- clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; +- clock-names = "phy", "ref"; +- samsung,pmu-syscon = <&pmu_system_controller>; +- #phy-cells = <1>; +- }; +- +- ehci: usb@12110000 { +- compatible = "samsung,exynos4210-ehci"; +- reg = <0x12110000 0x100>; +- interrupts = ; +- +- clocks = <&clock CLK_USB2>; +- clock-names = "usbhost"; +- phys = <&usb2_phy_gen 1>; +- phy-names = "host"; +- }; +- +- ohci: usb@12120000 { +- compatible = "samsung,exynos4210-ohci"; +- reg = <0x12120000 0x100>; +- interrupts = ; +- +- clocks = <&clock CLK_USB2>; +- clock-names = "usbhost"; +- phys = <&usb2_phy_gen 1>; +- phy-names = "host"; +- }; +- +- usb2_phy_gen: phy@12130000 { +- compatible = "samsung,exynos5250-usb2-phy"; +- reg = <0x12130000 0x100>; +- clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; +- clock-names = "phy", "ref"; +- #phy-cells = <1>; +- samsung,sysreg-phandle = <&sysreg_system_controller>; +- samsung,pmureg-phandle = <&pmu_system_controller>; +- }; +- +- pdma0: pdma@121a0000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x121A0000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_PDMA0>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- }; +- +- pdma1: pdma@121b0000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x121B0000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_PDMA1>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- }; +- +- mdma0: mdma@10800000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x10800000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_MDMA0>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <1>; +- }; +- +- mdma1: mdma@11c10000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x11C10000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_MDMA1>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <1>; +- }; +- +- gsc_0: gsc@13e00000 { +- compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; +- reg = <0x13e00000 0x1000>; +- interrupts = ; +- power-domains = <&pd_gsc>; +- clocks = <&clock CLK_GSCL0>; +- clock-names = "gscl"; +- iommus = <&sysmmu_gsc0>; +- }; +- +- gsc_1: gsc@13e10000 { +- compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; +- reg = <0x13e10000 0x1000>; +- interrupts = ; +- power-domains = <&pd_gsc>; +- clocks = <&clock CLK_GSCL1>; +- clock-names = "gscl"; +- iommus = <&sysmmu_gsc1>; +- }; +- +- gsc_2: gsc@13e20000 { +- compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; +- reg = <0x13e20000 0x1000>; +- interrupts = ; +- power-domains = <&pd_gsc>; +- clocks = <&clock CLK_GSCL2>; +- clock-names = "gscl"; +- iommus = <&sysmmu_gsc2>; +- }; +- +- gsc_3: gsc@13e30000 { +- compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; +- reg = <0x13e30000 0x1000>; +- interrupts = ; +- power-domains = <&pd_gsc>; +- clocks = <&clock CLK_GSCL3>; +- clock-names = "gscl"; +- iommus = <&sysmmu_gsc3>; +- }; +- +- hdmi: hdmi@14530000 { +- compatible = "samsung,exynos4212-hdmi"; +- reg = <0x14530000 0x70000>; +- power-domains = <&pd_disp1>; +- interrupts = ; +- clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, +- <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, +- <&clock CLK_MOUT_HDMI>; +- clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", +- "sclk_hdmiphy", "mout_hdmi"; +- samsung,syscon-phandle = <&pmu_system_controller>; +- phy = <&hdmiphy>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- hdmicec: cec@101b0000 { +- compatible = "samsung,s5p-cec"; +- reg = <0x101B0000 0x200>; +- interrupts = ; +- clocks = <&clock CLK_HDMI_CEC>; +- clock-names = "hdmicec"; +- samsung,syscon-phandle = <&pmu_system_controller>; +- hdmi-phandle = <&hdmi>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_cec>; +- status = "disabled"; +- }; +- +- mixer: mixer@14450000 { +- compatible = "samsung,exynos5250-mixer"; +- reg = <0x14450000 0x10000>; +- power-domains = <&pd_disp1>; +- interrupts = ; +- clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, +- <&clock CLK_SCLK_HDMI>; +- clock-names = "mixer", "hdmi", "sclk_hdmi"; +- iommus = <&sysmmu_tv>; +- status = "disabled"; +- }; +- +- dp_phy: video-phy { +- compatible = "samsung,exynos5250-dp-video-phy"; +- samsung,pmu-syscon = <&pmu_system_controller>; +- #phy-cells = <0>; +- }; +- +- mipi_phy: video-phy@10040710 { +- compatible = "samsung,s5pv210-mipi-video-phy"; +- reg = <0x10040710 0x100>; +- #phy-cells = <1>; +- syscon = <&pmu_system_controller>; +- }; +- +- dsi_0: dsi@14500000 { +- compatible = "samsung,exynos4210-mipi-dsi"; +- reg = <0x14500000 0x10000>; +- interrupts = ; +- samsung,power-domain = <&pd_disp1>; +- phys = <&mipi_phy 3>; +- phy-names = "dsim"; +- clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>; +- clock-names = "bus_clk", "sclk_mipi"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- adc: adc@12d10000 { +- compatible = "samsung,exynos-adc-v1"; +- reg = <0x12D10000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_ADC>; +- clock-names = "adc"; +- #io-channel-cells = <1>; +- samsung,syscon-phandle = <&pmu_system_controller>; +- status = "disabled"; +- }; +- +- sysmmu_g2d: sysmmu@10a60000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x10A60000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <24 5>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_mfc_r: sysmmu@11200000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x11200000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <6 2>; +- power-domains = <&pd_mfc>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_mfc_l: sysmmu@11210000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x11210000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <8 5>; +- power-domains = <&pd_mfc>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_rotator: sysmmu@11d40000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x11D40000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <4 0>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_jpeg: sysmmu@11f20000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x11F20000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <4 2>; +- power-domains = <&pd_gsc>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc_isp: sysmmu@13260000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13260000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <10 6>; +- clock-names = "sysmmu"; +- clocks = <&clock CLK_SMMU_FIMC_ISP>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc_drc: sysmmu@13270000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13270000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <11 6>; +- clock-names = "sysmmu"; +- clocks = <&clock CLK_SMMU_FIMC_DRC>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc_fd: sysmmu@132a0000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x132A0000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <5 0>; +- clock-names = "sysmmu"; +- clocks = <&clock CLK_SMMU_FIMC_FD>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc_scc: sysmmu@13280000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13280000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <5 2>; +- clock-names = "sysmmu"; +- clocks = <&clock CLK_SMMU_FIMC_SCC>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc_scp: sysmmu@13290000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13290000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <3 6>; +- clock-names = "sysmmu"; +- clocks = <&clock CLK_SMMU_FIMC_SCP>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc_mcuctl: sysmmu@132b0000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x132B0000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <5 4>; +- clock-names = "sysmmu"; +- clocks = <&clock CLK_SMMU_FIMC_MCU>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc_odc: sysmmu@132c0000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x132C0000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <11 0>; +- clock-names = "sysmmu"; +- clocks = <&clock CLK_SMMU_FIMC_ODC>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc_dis0: sysmmu@132d0000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x132D0000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <10 4>; +- clock-names = "sysmmu"; +- clocks = <&clock CLK_SMMU_FIMC_DIS0>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc_dis1: sysmmu@132e0000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x132E0000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <9 4>; +- clock-names = "sysmmu"; +- clocks = <&clock CLK_SMMU_FIMC_DIS1>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc_3dnr: sysmmu@132f0000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x132F0000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <5 6>; +- clock-names = "sysmmu"; +- clocks = <&clock CLK_SMMU_FIMC_3DNR>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc_lite0: sysmmu@13c40000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13C40000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <3 4>; +- power-domains = <&pd_gsc>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimc_lite1: sysmmu@13c50000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13C50000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <24 1>; +- power-domains = <&pd_gsc>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_gsc0: sysmmu@13e80000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13E80000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <2 0>; +- power-domains = <&pd_gsc>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_gsc1: sysmmu@13e90000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13E90000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <2 2>; +- power-domains = <&pd_gsc>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_gsc2: sysmmu@13ea0000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13EA0000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <2 4>; +- power-domains = <&pd_gsc>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_gsc3: sysmmu@13eb0000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13EB0000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <2 6>; +- power-domains = <&pd_gsc>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimd1: sysmmu@14640000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x14640000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <3 2>; +- power-domains = <&pd_disp1>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_tv: sysmmu@14650000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x14650000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <7 4>; +- power-domains = <&pd_disp1>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; +- #iommu-cells = <0>; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- /* +- * Unfortunately we need this since some versions +- * of U-Boot on Exynos don't set the CNTFRQ register, +- * so we need the value from DT. +- */ +- clock-frequency = <24000000>; +- }; +-}; +- +-&cpu_thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&tmu 0>; +- +- cooling-maps { +- map0 { +- /* Corresponds to 800MHz at freq_table */ +- cooling-device = <&cpu0 9 9>, <&cpu1 9 9>; +- }; +- map1 { +- /* Corresponds to 200MHz at freq_table */ +- cooling-device = <&cpu0 15 15>, +- <&cpu1 15 15>; +- }; +- }; +-}; +- +-&dp { +- power-domains = <&pd_disp1>; +- clocks = <&clock CLK_DP>; +- clock-names = "dp"; +- phys = <&dp_phy>; +- phy-names = "dp"; +-}; +- +-&fimd { +- power-domains = <&pd_disp1>; +- clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; +- clock-names = "sclk_fimd", "fimd"; +- iommus = <&sysmmu_fimd1>; +-}; +- +-&g2d { +- iommus = <&sysmmu_g2d>; +- clocks = <&clock CLK_G2D>; +- clock-names = "fimg2d"; +- status = "okay"; +-}; +- +-&i2c_0 { +- clocks = <&clock CLK_I2C0>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_bus>; +-}; +- +-&i2c_1 { +- clocks = <&clock CLK_I2C1>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_bus>; +-}; +- +-&i2c_2 { +- clocks = <&clock CLK_I2C2>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_bus>; +-}; +- +-&i2c_3 { +- clocks = <&clock CLK_I2C3>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_bus>; +-}; +- +-&prng { +- clocks = <&clock CLK_SSS>; +- clock-names = "secss"; +-}; +- +-&pwm { +- clocks = <&clock CLK_PWM>; +- clock-names = "timers"; +-}; +- +-&rtc { +- clocks = <&clock CLK_RTC>; +- clock-names = "rtc"; +- interrupt-parent = <&pmu_system_controller>; +- status = "disabled"; +-}; +- +-&serial_0 { +- clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; +- clock-names = "uart", "clk_uart_baud0"; +- dmas = <&pdma0 13>, <&pdma0 14>; +- dma-names = "rx", "tx"; +-}; +- +-&serial_1 { +- clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; +- clock-names = "uart", "clk_uart_baud0"; +- dmas = <&pdma1 15>, <&pdma1 16>; +- dma-names = "rx", "tx"; +-}; +- +-&serial_2 { +- clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; +- clock-names = "uart", "clk_uart_baud0"; +- dmas = <&pdma0 15>, <&pdma0 16>; +- dma-names = "rx", "tx"; +-}; +- +-&serial_3 { +- clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; +- clock-names = "uart", "clk_uart_baud0"; +- dmas = <&pdma1 17>, <&pdma1 18>; +- dma-names = "rx", "tx"; +-}; +- +-&sss { +- clocks = <&clock CLK_SSS>; +- clock-names = "secss"; +-}; +- +-&trng { +- clocks = <&clock CLK_SSS>; +- clock-names = "secss"; +-}; +- +-#include "exynos5250-pinctrl.dtsi" +-#include "exynos-syscon-restart.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/exynos5260-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/exynos5260-pinctrl.dtsi +deleted file mode 100644 +index 17e2f3e0d71e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5260-pinctrl.dtsi ++++ /dev/null +@@ -1,585 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source +- * +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device +- * tree nodes are listed in this file. +- */ +- +-#include +- +-&pinctrl_0 { +- gpa0: gpa0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpa1: gpa1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpa2: gpa2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb0: gpb0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb1: gpb1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb2: gpb2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb3: gpb3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb4: gpb4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb5: gpb5 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd0: gpd0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd1: gpd1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd2: gpd2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpe0: gpe0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpe1: gpe1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf0: gpf0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf1: gpf1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpk0: gpk0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpx0: gpx0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- #interrupt-cells = <2>; +- }; +- +- gpx1: gpx1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- #interrupt-cells = <2>; +- }; +- +- gpx2: gpx2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpx3: gpx3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- uart0_data: uart0-data { +- samsung,pins = "gpa0-0", "gpa0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart0_fctl: uart0-fctl { +- samsung,pins = "gpa0-2", "gpa0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart1_data: uart1-data { +- samsung,pins = "gpa1-0", "gpa1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart1_fctl: uart1-fctl { +- samsung,pins = "gpa1-2", "gpa1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart2_data: uart2-data { +- samsung,pins = "gpa1-4", "gpa1-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi0_bus: spi0-bus { +- samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi1_bus: spi1-bus { +- samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- usb3_vbus0_en: usb3-vbus0-en { +- samsung,pins = "gpa2-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2s1_bus: i2s1-bus { +- samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", +- "gpb0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pcm1_bus: pcm1-bus { +- samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", +- "gpb0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spdif1_bus: spdif1-bus { +- samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi2_bus: spi2-bus { +- samsung,pins = "gpb1-0", "gpb1-2", "gpb1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c0_hs_bus: i2c0-hs-bus { +- samsung,pins = "gpb3-0", "gpb3-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c1_hs_bus: i2c1-hs-bus { +- samsung,pins = "gpb3-2", "gpb3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c2_hs_bus: i2c2-hs-bus { +- samsung,pins = "gpb3-4", "gpb3-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c3_hs_bus: i2c3-hs-bus { +- samsung,pins = "gpb3-6", "gpb3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c4_bus: i2c4-bus { +- samsung,pins = "gpb4-0", "gpb4-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c5_bus: i2c5-bus { +- samsung,pins = "gpb4-2", "gpb4-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c6_bus: i2c6-bus { +- samsung,pins = "gpb4-4", "gpb4-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c7_bus: i2c7-bus { +- samsung,pins = "gpb4-6", "gpb4-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c8_bus: i2c8-bus { +- samsung,pins = "gpb5-0", "gpb5-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c9_bus: i2c9-bus { +- samsung,pins = "gpb5-2", "gpb5-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c10_bus: i2c10-bus { +- samsung,pins = "gpb5-4", "gpb5-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c11_bus: i2c11-bus { +- samsung,pins = "gpb5-6", "gpb5-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_gpio_a: cam-gpio-a { +- samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", +- "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", +- "gpe1-0", "gpe1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_gpio_b: cam-gpio-b { +- samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", +- "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_i2c1_bus: cam-i2c1-bus { +- samsung,pins = "gpf0-2", "gpf0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_i2c0_bus: cam-i2c0-bus { +- samsung,pins = "gpf0-0", "gpf0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_spi0_bus: cam-spi0-bus { +- samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_spi1_bus: cam-spi1-bus { +- samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_1 { +- gpc0: gpc0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc1: gpc1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc2: gpc2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc3: gpc3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc4: gpc4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- sd0_clk: sd0-clk { +- samsung,pins = "gpc0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_cmd: sd0-cmd { +- samsung,pins = "gpc0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus1: sd0-bus-width1 { +- samsung,pins = "gpc0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus4: sd0-bus-width4 { +- samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus8: sd0-bus-width8 { +- samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_rdqs: sd0-rdqs { +- samsung,pins = "gpc0-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_clk: sd1-clk { +- samsung,pins = "gpc1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_cmd: sd1-cmd { +- samsung,pins = "gpc1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus1: sd1-bus-width1 { +- samsung,pins = "gpc1-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus4: sd1-bus-width4 { +- samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus8: sd1-bus-width8 { +- samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_clk: sd2-clk { +- samsung,pins = "gpc2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cmd: sd2-cmd { +- samsung,pins = "gpc2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cd: sd2-cd { +- samsung,pins = "gpc2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus1: sd2-bus-width1 { +- samsung,pins = "gpc2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus4: sd2-bus-width4 { +- samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_2 { +- gpz0: gpz0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpz1: gpz1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5260-xyref5260.dts b/scripts/dtc/include-prefixes/arm/exynos5260-xyref5260.dts +deleted file mode 100644 +index 0dc2ec16aa0a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5260-xyref5260.dts ++++ /dev/null +@@ -1,90 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung XYREF5260 board device tree source +- * +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-/dts-v1/; +-#include "exynos5260.dtsi" +- +-/ { +- model = "Samsung XYREF5260 board based on Exynos5260"; +- compatible = "samsung,xyref5260", "samsung,exynos5260", "samsung,exynos5"; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x80000000>; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- fin_pll: xxti { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "fin_pll"; +- #clock-cells = <0>; +- }; +- +- xrtcxti: xrtcxti { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-output-names = "xrtcxti"; +- #clock-cells = <0>; +- }; +-}; +- +-&pinctrl_0 { +- hdmi_hpd_irq: hdmi-hpd-irq { +- samsung,pins = "gpx3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&mmc_0 { +- status = "okay"; +- broken-cd; +- cap-mmc-highspeed; +- supports-hs200-mode; /* 200 MHz */ +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <0 4>; +- samsung,dw-mshc-ddr-timing = <0 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; +- bus-width = <8>; +-}; +- +-&mmc_2 { +- status = "okay"; +- cap-sd-highspeed; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; +- bus-width = <4>; +- disable-wp; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5260.dtsi b/scripts/dtc/include-prefixes/arm/exynos5260.dtsi +deleted file mode 100644 +index 52fa211525ce..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5260.dtsi ++++ /dev/null +@@ -1,425 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung Exynos5260 SoC device tree source +- * +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "samsung,exynos5260", "samsung,exynos5"; +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- i2c0 = &hsi2c_0; +- i2c1 = &hsi2c_1; +- i2c2 = &hsi2c_2; +- i2c3 = &hsi2c_3; +- pinctrl0 = &pinctrl_0; +- pinctrl1 = &pinctrl_1; +- pinctrl2 = &pinctrl_2; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&cpu2>; +- }; +- core1 { +- cpu = <&cpu3>; +- }; +- core2 { +- cpu = <&cpu4>; +- }; +- core3 { +- cpu = <&cpu5>; +- }; +- }; +- }; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x0>; +- cci-control-port = <&cci_control1>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x1>; +- cci-control-port = <&cci_control1>; +- }; +- +- cpu2: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x100>; +- cci-control-port = <&cci_control0>; +- }; +- +- cpu3: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x101>; +- cci-control-port = <&cci_control0>; +- }; +- +- cpu4: cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x102>; +- cci-control-port = <&cci_control0>; +- }; +- +- cpu5: cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x103>; +- cci-control-port = <&cci_control0>; +- }; +- }; +- +- soc: soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clock_top: clock-controller@10010000 { +- compatible = "samsung,exynos5260-clock-top"; +- reg = <0x10010000 0x10000>; +- #clock-cells = <1>; +- }; +- +- clock_peri: clock-controller@10200000 { +- compatible = "samsung,exynos5260-clock-peri"; +- reg = <0x10200000 0x10000>; +- #clock-cells = <1>; +- }; +- +- clock_egl: clock-controller@10600000 { +- compatible = "samsung,exynos5260-clock-egl"; +- reg = <0x10600000 0x10000>; +- #clock-cells = <1>; +- }; +- +- clock_kfc: clock-controller@10700000 { +- compatible = "samsung,exynos5260-clock-kfc"; +- reg = <0x10700000 0x10000>; +- #clock-cells = <1>; +- }; +- +- clock_g2d: clock-controller@10a00000 { +- compatible = "samsung,exynos5260-clock-g2d"; +- reg = <0x10A00000 0x10000>; +- #clock-cells = <1>; +- }; +- +- clock_mif: clock-controller@10ce0000 { +- compatible = "samsung,exynos5260-clock-mif"; +- reg = <0x10CE0000 0x10000>; +- #clock-cells = <1>; +- }; +- +- clock_mfc: clock-controller@11090000 { +- compatible = "samsung,exynos5260-clock-mfc"; +- reg = <0x11090000 0x10000>; +- #clock-cells = <1>; +- }; +- +- clock_g3d: clock-controller@11830000 { +- compatible = "samsung,exynos5260-clock-g3d"; +- reg = <0x11830000 0x10000>; +- #clock-cells = <1>; +- }; +- +- clock_fsys: clock-controller@122e0000 { +- compatible = "samsung,exynos5260-clock-fsys"; +- reg = <0x122E0000 0x10000>; +- #clock-cells = <1>; +- }; +- +- clock_aud: clock-controller@128c0000 { +- compatible = "samsung,exynos5260-clock-aud"; +- reg = <0x128C0000 0x10000>; +- #clock-cells = <1>; +- }; +- +- clock_isp: clock-controller@133c0000 { +- compatible = "samsung,exynos5260-clock-isp"; +- reg = <0x133C0000 0x10000>; +- #clock-cells = <1>; +- }; +- +- clock_gscl: clock-controller@13f00000 { +- compatible = "samsung,exynos5260-clock-gscl"; +- reg = <0x13F00000 0x10000>; +- #clock-cells = <1>; +- }; +- +- clock_disp: clock-controller@14550000 { +- compatible = "samsung,exynos5260-clock-disp"; +- reg = <0x14550000 0x10000>; +- #clock-cells = <1>; +- }; +- +- gic: interrupt-controller@10481000 { +- compatible = "arm,gic-400", "arm,cortex-a15-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x10481000 0x1000>, +- <0x10482000 0x2000>, +- <0x10484000 0x2000>, +- <0x10486000 0x2000>; +- interrupts = ; +- }; +- +- chipid: chipid@10000000 { +- compatible = "samsung,exynos4210-chipid"; +- reg = <0x10000000 0x100>; +- }; +- +- mct: timer@100b0000 { +- compatible = "samsung,exynos4210-mct"; +- reg = <0x100B0000 0x1000>; +- clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; +- clock-names = "fin_pll", "mct"; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- }; +- +- cci: cci@10f00000 { +- compatible = "arm,cci-400"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x10F00000 0x1000>; +- ranges = <0x0 0x10F00000 0x6000>; +- +- cci_control0: slave-if@4000 { +- compatible = "arm,cci-400-ctrl-if"; +- interface-type = "ace"; +- reg = <0x4000 0x1000>; +- }; +- +- cci_control1: slave-if@5000 { +- compatible = "arm,cci-400-ctrl-if"; +- interface-type = "ace"; +- reg = <0x5000 0x1000>; +- }; +- }; +- +- pinctrl_0: pinctrl@11600000 { +- compatible = "samsung,exynos5260-pinctrl"; +- reg = <0x11600000 0x1000>; +- interrupts = ; +- +- wakeup-interrupt-controller { +- compatible = "samsung,exynos4210-wakeup-eint"; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +- +- pinctrl_1: pinctrl@12290000 { +- compatible = "samsung,exynos5260-pinctrl"; +- reg = <0x12290000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_2: pinctrl@128b0000 { +- compatible = "samsung,exynos5260-pinctrl"; +- reg = <0x128B0000 0x1000>; +- interrupts = ; +- }; +- +- pmu_system_controller: system-controller@10d50000 { +- compatible = "samsung,exynos5260-pmu", "syscon"; +- reg = <0x10D50000 0x10000>; +- }; +- +- uart0: serial@12c00000 { +- compatible = "samsung,exynos4210-uart"; +- reg = <0x12C00000 0x100>; +- interrupts = ; +- clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>; +- clock-names = "uart", "clk_uart_baud0"; +- status = "disabled"; +- }; +- +- uart1: serial@12c10000 { +- compatible = "samsung,exynos4210-uart"; +- reg = <0x12C10000 0x100>; +- interrupts = ; +- clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>; +- clock-names = "uart", "clk_uart_baud0"; +- status = "disabled"; +- }; +- +- uart2: serial@12c20000 { +- compatible = "samsung,exynos4210-uart"; +- reg = <0x12C20000 0x100>; +- interrupts = ; +- clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>; +- clock-names = "uart", "clk_uart_baud0"; +- status = "disabled"; +- }; +- +- uart3: serial@12860000 { +- compatible = "samsung,exynos4210-uart"; +- reg = <0x12860000 0x100>; +- interrupts = ; +- clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>; +- clock-names = "uart", "clk_uart_baud0"; +- status = "disabled"; +- }; +- +- mmc_0: mmc@12140000 { +- compatible = "samsung,exynos5250-dw-mshc"; +- reg = <0x12140000 0x2000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>; +- clock-names = "biu", "ciu"; +- assigned-clocks = +- <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>, +- <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B>, +- <&clock_top TOP_SCLK_MMC0>; +- assigned-clock-parents = +- <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, +- <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>; +- assigned-clock-rates = <0>, <0>, <800000000>; +- fifo-depth = <64>; +- status = "disabled"; +- }; +- +- mmc_1: mmc@12150000 { +- compatible = "samsung,exynos5250-dw-mshc"; +- reg = <0x12150000 0x2000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>; +- clock-names = "biu", "ciu"; +- assigned-clocks = +- <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>, +- <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B>, +- <&clock_top TOP_SCLK_MMC1>; +- assigned-clock-parents = +- <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, +- <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>; +- assigned-clock-rates = <0>, <0>, <800000000>; +- fifo-depth = <64>; +- status = "disabled"; +- }; +- +- mmc_2: mmc@12160000 { +- compatible = "samsung,exynos5250-dw-mshc"; +- reg = <0x12160000 0x2000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>; +- clock-names = "biu", "ciu"; +- assigned-clocks = +- <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>, +- <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B>, +- <&clock_top TOP_SCLK_MMC2>; +- assigned-clock-parents = +- <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, +- <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>; +- assigned-clock-rates = <0>, <0>, <800000000>; +- fifo-depth = <64>; +- status = "disabled"; +- }; +- +- hsi2c_0: hsi2c@12da0000 { +- compatible = "samsung,exynos5260-hsi2c"; +- reg = <0x12DA0000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_hs_bus>; +- clocks = <&clock_peri PERI_CLK_HSIC0>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_1: hsi2c@12db0000 { +- compatible = "samsung,exynos5260-hsi2c"; +- reg = <0x12DB0000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_hs_bus>; +- clocks = <&clock_peri PERI_CLK_HSIC1>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_2: hsi2c@12dc0000 { +- compatible = "samsung,exynos5260-hsi2c"; +- reg = <0x12DC0000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_hs_bus>; +- clocks = <&clock_peri PERI_CLK_HSIC2>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_3: hsi2c@12dd0000 { +- compatible = "samsung,exynos5260-hsi2c"; +- reg = <0x12DD0000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_hs_bus>; +- clocks = <&clock_peri PERI_CLK_HSIC3>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- }; +-}; +- +-#include "exynos5260-pinctrl.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/exynos5410-odroidxu.dts b/scripts/dtc/include-prefixes/arm/exynos5410-odroidxu.dts +deleted file mode 100644 +index 884fef55836c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5410-odroidxu.dts ++++ /dev/null +@@ -1,683 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Hardkernel Odroid XU board device tree source +- * +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * Copyright (c) 2016 Krzysztof Kozlowski +- */ +- +-/dts-v1/; +-#include "exynos5410.dtsi" +-#include +-#include +-#include +-#include +-#include "exynos54xx-odroidxu-leds.dtsi" +- +-/ { +- model = "Hardkernel Odroid XU"; +- compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5"; +- +- aliases { +- ethernet = ðernet; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x7ea00000>; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- emmc_pwrseq: pwrseq { +- pinctrl-0 = <&emmc_nrst_pin>; +- pinctrl-names = "default"; +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>; +- }; +- +- fan0: pwm-fan { +- compatible = "pwm-fan"; +- pwms = <&pwm 0 20972 0>; +- #cooling-cells = <2>; +- cooling-levels = <0 130 170 230>; +- }; +- +- fin_pll: xxti { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "fin_pll"; +- #clock-cells = <0>; +- }; +- +- firmware@2073000 { +- compatible = "samsung,secure-firmware"; +- reg = <0x02073000 0x1000>; +- }; +- +- sound: sound { +- compatible = "simple-audio-card"; +- +- simple-audio-card,name = "Odroid-XU"; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack", +- "Speakers", "Speakers"; +- simple-audio-card,routing = +- "Headphone Jack", "HPL", +- "Headphone Jack", "HPR", +- "Headphone Jack", "MICBIAS", +- "IN1", "Headphone Jack", +- "Speakers", "SPKL", +- "Speakers", "SPKR"; +- +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&link0_codec>; +- simple-audio-card,frame-master = <&link0_codec>; +- +- simple-audio-card,cpu { +- sound-dai = <&audi2s0 0>; +- system-clock-frequency = <19200000>; +- }; +- +- link0_codec: simple-audio-card,codec { +- sound-dai = <&max98090>; +- clocks = <&audi2s0 CLK_I2S_CDCLK>; +- }; +- }; +-}; +- +-&adc { +- vdd-supply = <&ldo10_reg>; +- status = "okay"; +-}; +- +-&audi2s0 { +- status = "okay"; +-}; +- +-&clock { +- clocks = <&fin_pll>; +- assigned-clocks = <&clock CLK_FOUT_EPLL>; +- assigned-clock-rates = <192000000>; +-}; +- +-&clock_audss { +- assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, +- <&clock_audss EXYNOS_MOUT_I2S>, +- <&clock_audss EXYNOS_DOUT_SRP>, +- <&clock_audss EXYNOS_DOUT_AUD_BUS>; +- +- assigned-clock-parents = <&clock CLK_FOUT_EPLL>, +- <&clock_audss EXYNOS_MOUT_AUDSS>; +- +- assigned-clock-rates = <0>, +- <0>, +- <96000000>, +- <19200000>; +-}; +- +-&cpu0_thermal { +- thermal-sensors = <&tmu_cpu0 0>; +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- trips { +- cpu_alert0: cpu-alert-0 { +- temperature = <50000>; /* millicelsius */ +- hysteresis = <5000>; /* millicelsius */ +- type = "active"; +- }; +- cpu_alert1: cpu-alert-1 { +- temperature = <60000>; /* millicelsius */ +- hysteresis = <5000>; /* millicelsius */ +- type = "active"; +- }; +- cpu_alert2: cpu-alert-2 { +- temperature = <70000>; /* millicelsius */ +- hysteresis = <5000>; /* millicelsius */ +- type = "active"; +- }; +- cpu_crit0: cpu-crit-0 { +- temperature = <120000>; /* millicelsius */ +- hysteresis = <0>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- cooling-device = <&fan0 0 1>; +- }; +- map1 { +- trip = <&cpu_alert1>; +- cooling-device = <&fan0 1 2>; +- }; +- map2 { +- trip = <&cpu_alert2>; +- cooling-device = <&fan0 2 3>; +- }; +- }; +-}; +- +-&hsi2c_4 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <400000>; +- status = "okay"; +- +- usb3503: usb-hub@8 { +- compatible = "smsc,usb3503"; +- reg = <0x08>; +- +- intn-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>; +- connect-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&gpx1 4 GPIO_ACTIVE_LOW>; +- initial-mode = <1>; +- +- clock-names = "refclk"; +- clocks = <&pmu_system_controller 0>; +- refclk-frequency = <24000000>; +- }; +- +- max77802: pmic@9 { +- compatible = "maxim,max77802"; +- reg = <0x9>; +- interrupt-parent = <&gpx0>; +- interrupts = <4 IRQ_TYPE_NONE>; +- pinctrl-names = "default"; +- pinctrl-0 = <&max77802_irq>, <&pmic_dvs_1>, <&pmic_dvs_2>, +- <&pmic_dvs_3>; +- wakeup-source; +- #clock-cells = <1>; +- +- inl1-supply = <&buck5_reg>; +- inl2-supply = <&buck7_reg>; +- inl3-supply = <&buck9_reg>; +- inl4-supply = <&buck9_reg>; +- inl5-supply = <&buck9_reg>; +- inl6-supply = <&buck10_reg>; +- inl7-supply = <&buck9_reg>; +- /* inl9 supply is BOOST, not configured here */ +- inl10-supply = <&buck7_reg>; +- +- regulators { +- buck1_reg: BUCK1 { +- regulator-name = "vdd_mif"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "vdd_int"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "vdd_g3d"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "vdd_mem"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck6_reg: BUCK6 { +- regulator-name = "vdd_kfc"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck7_reg: BUCK7 { +- regulator-name = "buck7"; +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck8_reg: BUCK8 { +- /* vdd_mmc0 */ +- regulator-name = "vddf_2v85"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck9_reg: BUCK9 { +- regulator-name = "buck9"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck10_reg: BUCK10 { +- regulator-name = "buck10"; +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo1_reg: LDO1 { +- regulator-name = "vdd_alive"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "vddq_m1_m2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "vddq_gpio"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "vddq_mmc2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- /* Having it off prevents reboot */ +- regulator-always-on; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "vdd18_hsic"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "vdd18_bpll"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "vddq_lcd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- /* Supplies also GPK and GPJ */ +- regulator-always-on; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "vdd10_hdmi"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "ldo9"; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "vdd18_mipi"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "vddq_mmc01"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- /* +- * Having it off prevents accessing MMC after +- * reboot with error: +- * MMC Device 1: Clock OFF has been failed. +- */ +- regulator-always-on; +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "vdd33_usb3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "vddq_abbg0"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "vddq_abbg1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "vdd10_usb3"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "ldo16"; +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "cam_sensor_core"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo18_reg: LDO18 { +- regulator-name = "ldo18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo19_reg: LDO19 { +- regulator-name = "ldo19"; +- }; +- +- ldo20_reg: LDO20 { +- regulator-name = "vdd_mmc0"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo21_reg: LDO21 { +- /* vdd_mmc2 */ +- regulator-name = "vddf_2v8"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- ldo22_reg: LDO22 { +- regulator-name = "ldo22"; +- }; +- +- ldo23_reg: LDO23 { +- regulator-name = "dp_p3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo24_reg: LDO24 { +- regulator-name = "cam_af"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo25_reg: LDO25 { +- regulator-name = "eth_p3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo26_reg: LDO26 { +- regulator-name = "usb30_extclk"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo27_reg: LDO27 { +- regulator-name = "ldo27"; +- }; +- +- ldo28_reg: LDO28 { +- regulator-name = "ldo28"; +- }; +- +- ldo29_reg: LDO29 { +- regulator-name = "ldo29"; +- }; +- +- ldo30_reg: LDO30 { +- regulator-name = "vddq_e1_e2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo31_reg: LDO31 { +- regulator-name = "ldo31"; +- }; +- +- /* On revisions with ti,ina231 this is sensor VS */ +- ldo32_reg: LDO32 { +- regulator-name = "vs_power_meter"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo33_reg: LDO33 { +- regulator-name = "ldo33"; +- }; +- +- ldo34_reg: LDO34 { +- regulator-name = "ldo34"; +- }; +- +- ldo35_reg: LDO35 { +- regulator-name = "ldo35"; +- }; +- }; +- }; +-}; +- +-&i2c_1 { +- status = "okay"; +- max98090: audio-codec@10 { +- compatible = "maxim,max98090"; +- reg = <0x10>; +- interrupt-parent = <&gpj3>; +- interrupts = <0 IRQ_TYPE_NONE>; +- clocks = <&audi2s0 CLK_I2S_CDCLK>; +- clock-names = "mclk"; +- #sound-dai-cells = <0>; +- }; +-}; +- +-&mmc_0 { +- status = "okay"; +- mmc-pwrseq = <&emmc_pwrseq>; +- cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <0 4>; +- samsung,dw-mshc-ddr-timing = <0 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd>; +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +- vmmc-supply = <&ldo20_reg>; +- vqmmc-supply = <&ldo11_reg>; +-}; +- +-&mmc_2 { +- status = "okay"; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <0 4>; +- samsung,dw-mshc-ddr-timing = <0 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4 &sd2_wp>; +- bus-width = <4>; +- cap-sd-highspeed; +- vmmc-supply = <&ldo21_reg>; +- vqmmc-supply = <&ldo4_reg>; +-}; +- +-&pinctrl_0 { +- emmc_nrst_pin: emmc-nrst { +- samsung,pins = "gpd1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_wp: sd2-wp { +- samsung,pins = "gpm5-0"; +- samsung,pin-function = ; +- /* Pin is floating so be sure to disable write-protect */ +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pmic_dvs_3: pmic-dvs-3 { +- samsung,pins = "gpx0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pmic_dvs_2: pmic-dvs-2 { +- samsung,pins = "gpx0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pmic_dvs_1: pmic-dvs-1 { +- samsung,pins = "gpx0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- samsung,pin-val = <1>; +- }; +- +- max77802_irq: max77802-irq { +- samsung,pins = "gpx0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pwm { +- /* +- * PWM 0 -- fan +- * PWM 1 -- Green LED +- * PWM 2 -- Blue LED +- * PWM 3 -- on MIPI connector for backlight +- */ +- pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&serial_0 { +- status = "okay"; +-}; +- +-&serial_1 { +- status = "okay"; +-}; +- +-&serial_2 { +- status = "okay"; +-}; +- +-&serial_3 { +- status = "okay"; +-}; +- +-&tmu_cpu0 { +- vtmu-supply = <&ldo10_reg>; +-}; +- +-&tmu_cpu1 { +- vtmu-supply = <&ldo10_reg>; +-}; +- +-&tmu_cpu2 { +- vtmu-supply = <&ldo10_reg>; +-}; +- +-&tmu_cpu3 { +- vtmu-supply = <&ldo10_reg>; +-}; +- +-&usb3_0_oc { +- /* External pull up */ +- samsung,pin-pud = ; +-}; +- +-&usb3_1_oc { +- /* External pull up */ +- samsung,pin-pud = ; +-}; +- +-&usbdrd_dwc3_0 { +- dr_mode = "peripheral"; +-}; +- +-&usbdrd_dwc3_1 { +- dr_mode = "host"; +-}; +- +-&usbdrd3_0 { +- vdd33-supply = <&ldo12_reg>; +- vdd10-supply = <&ldo15_reg>; +-}; +- +-&usbdrd3_1 { +- vdd33-supply = <&ldo12_reg>; +- vdd10-supply = <&ldo15_reg>; +-}; +- +-&usbhost2 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethernet: usbether@2 { +- compatible = "usb0424,9730"; +- reg = <2>; +- local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5410-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/exynos5410-pinctrl.dtsi +deleted file mode 100644 +index 9599ba8ba798..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5410-pinctrl.dtsi ++++ /dev/null +@@ -1,652 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Exynos5410 SoC pin-mux and pin-config device tree source +- * +- * Copyright (c) 2013 Hardkernel Co., Ltd. +- * https://www.hardkernel.com +- */ +- +-#include +- +-&pinctrl_0 { +- gpa0: gpa0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpa1: gpa1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpa2: gpa2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb0: gpb0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb1: gpb1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb2: gpb2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb3: gpb3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc0: gpc0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc3: gpc3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc1: gpc1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc2: gpc2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpm5: gpm5 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpd1: gpd1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpe0: gpe0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpe1: gpe1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf0: gpf0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf1: gpf1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg0: gpg0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg1: gpg1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg2: gpg2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gph0: gph0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gph1: gph1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpm7: gpm7 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy0: gpy0 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy1: gpy1 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy2: gpy2 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy3: gpy3 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy4: gpy4 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy5: gpy5 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy6: gpy6 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy7: gpy7 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpx0: gpx0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- interrupt-parent = <&combiner>; +- #interrupt-cells = <2>; +- interrupts = <23 0>, +- <24 0>, +- <25 0>, +- <25 1>, +- <26 0>, +- <26 1>, +- <27 0>, +- <27 1>; +- }; +- +- gpx1: gpx1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- interrupt-parent = <&combiner>; +- #interrupt-cells = <2>; +- interrupts = <28 0>, +- <28 1>, +- <29 0>, +- <29 1>, +- <30 0>, +- <30 1>, +- <31 0>, +- <31 1>; +- }; +- +- gpx2: gpx2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpx3: gpx3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- uart0_data: uart0-data { +- samsung,pins = "gpa0-0", "gpa0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart0_fctl: uart0-fctl { +- samsung,pins = "gpa0-2", "gpa0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart1_data: uart1-data { +- samsung,pins = "gpa0-4", "gpa0-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart1_fctl: uart1-fctl { +- samsung,pins = "gpa0-6", "gpa0-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c2_bus: i2c2-bus { +- samsung,pins = "gpa0-6", "gpa0-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart2_data: uart2-data { +- samsung,pins = "gpa1-0", "gpa1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart2_fctl: uart2-fctl { +- samsung,pins = "gpa1-2", "gpa1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c3_bus: i2c3-bus { +- samsung,pins = "gpa1-2", "gpa1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart3_data: uart3-data { +- samsung,pins = "gpa1-4", "gpa1-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c4_hs_bus: i2c4-hs-bus { +- samsung,pins = "gpa2-0", "gpa2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c5_hs_bus: i2c5-hs-bus { +- samsung,pins = "gpa2-2", "gpa2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c6_hs_bus: i2c6-hs-bus { +- samsung,pins = "gpb1-3", "gpb1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm0_out: pwm0-out { +- samsung,pins = "gpb2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm1_out: pwm1-out { +- samsung,pins = "gpb2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm2_out: pwm2-out { +- samsung,pins = "gpb2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm3_out: pwm3-out { +- samsung,pins = "gpb2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c7_hs_bus: i2c7-hs-bus { +- samsung,pins = "gpb2-2", "gpb2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c0_bus: i2c0-bus { +- samsung,pins = "gpb3-0", "gpb3-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c1_bus: i2c1-bus { +- samsung,pins = "gpb3-2", "gpb3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_clk: sd0-clk { +- samsung,pins = "gpc0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_cmd: sd0-cmd { +- samsung,pins = "gpc0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_cd: sd0-cd { +- samsung,pins = "gpc0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus1: sd0-bus-width1 { +- samsung,pins = "gpc0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus4: sd0-bus-width4 { +- samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_clk: sd2-clk { +- samsung,pins = "gpc2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cmd: sd2-cmd { +- samsung,pins = "gpc2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cd: sd2-cd { +- samsung,pins = "gpc2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus1: sd2-bus-width1 { +- samsung,pins = "gpc2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus4: sd2-bus-width4 { +- samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus8: sd0-bus-width8 { +- samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_1 { +- gpj0: gpj0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpj1: gpj1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpj2: gpj2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpj3: gpj3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpj4: gpj4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpk0: gpk0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpk1: gpk1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpk2: gpk2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpk3: gpk3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- usb3_1_oc: usb3-1-oc { +- samsung,pins = "gpk2-4", "gpk2-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- usb3_1_vbusctrl: usb3-1-vbusctrl { +- samsung,pins = "gpk2-6", "gpk2-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- usb3_0_oc: usb3-0-oc { +- samsung,pins = "gpk3-0", "gpk3-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- usb3_0_vbusctrl: usb3-0-vbusctrl { +- samsung,pins = "gpk3-2", "gpk3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_2 { +- gpv0: gpv0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpv1: gpv1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpv2: gpv2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpv3: gpv3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpv4: gpv4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +-}; +- +-&pinctrl_3 { +- gpz: gpz { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- audi2s0_bus: audi2s0-bus { +- samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", +- "gpz-4"; +- samsung,pin-function = <2>; +- samsung,pin-pud = <0>; +- samsung,pin-drv = <0>; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5410-smdk5410.dts b/scripts/dtc/include-prefixes/arm/exynos5410-smdk5410.dts +deleted file mode 100644 +index 2a3ade77a2de..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5410-smdk5410.dts ++++ /dev/null +@@ -1,123 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung SMDK5410 board device tree source +- * +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-/dts-v1/; +-#include "exynos5410.dtsi" +-#include +-/ { +- model = "Samsung SMDK5410 board based on Exynos5410"; +- compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x80000000>; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- fin_pll: xxti { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "fin_pll"; +- #clock-cells = <0>; +- }; +- +- pmic_ap_clk: pmic-ap-clk { +- /* Workaround for missing PMIC and its clock */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- firmware@2037000 { +- compatible = "samsung,secure-firmware"; +- reg = <0x02037000 0x1000>; +- }; +- +-}; +- +-&mmc_0 { +- status = "okay"; +- cap-mmc-highspeed; +- broken-cd; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- bus-width = <8>; +-}; +- +-&mmc_2 { +- status = "okay"; +- cap-sd-highspeed; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- bus-width = <4>; +- disable-wp; +-}; +- +-&pinctrl_0 { +- srom_ctl: srom-ctl { +- samsung,pins = "gpy0-3", "gpy0-4", "gpy0-5", +- "gpy1-0", "gpy1-1", "gpy1-2", "gpy1-3"; +- samsung,pin-function = ; +- samsung,pin-drv = ; +- }; +- +- srom_ebi: srom-ebi { +- samsung,pins = "gpy3-0", "gpy3-1", "gpy3-2", "gpy3-3", +- "gpy3-4", "gpy3-5", "gpy3-6", "gpy3-7", +- "gpy5-0", "gpy5-1", "gpy5-2", "gpy5-3", +- "gpy5-4", "gpy5-5", "gpy5-6", "gpy5-7", +- "gpy6-0", "gpy6-1", "gpy6-2", "gpy6-3", +- "gpy6-4", "gpy6-5", "gpy6-6", "gpy6-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&rtc { +- clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&sromc { +- pinctrl-names = "default"; +- pinctrl-0 = <&srom_ctl>, <&srom_ebi>; +- +- ethernet@3,0 { +- compatible = "smsc,lan9115"; +- reg = <3 0 0x10000>; +- phy-mode = "mii"; +- interrupt-parent = <&gpx0>; +- interrupts = <5 IRQ_TYPE_LEVEL_LOW>; +- reg-io-width = <2>; +- smsc,irq-push-pull; +- smsc,force-internal-phy; +- +- samsung,srom-page-mode; +- samsung,srom-timing = <9 12 1 9 1 1>; +- }; +-}; +- +-&serial_0 { +- status = "okay"; +-}; +- +-&serial_1 { +- status = "okay"; +-}; +- +-&serial_2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5410.dtsi b/scripts/dtc/include-prefixes/arm/exynos5410.dtsi +deleted file mode 100644 +index 584ce62361b1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5410.dtsi ++++ /dev/null +@@ -1,444 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung Exynos5410 SoC device tree source +- * +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Samsung Exynos5410 SoC device nodes are listed in this file. +- * Exynos5410 based board files can include this file and provide +- * values for board specfic bindings. +- */ +- +-#include "exynos54xx.dtsi" +-#include +-#include +-#include +- +-/ { +- compatible = "samsung,exynos5410", "samsung,exynos5"; +- interrupt-parent = <&gic>; +- +- aliases { +- pinctrl0 = &pinctrl_0; +- pinctrl1 = &pinctrl_1; +- pinctrl2 = &pinctrl_2; +- pinctrl3 = &pinctrl_3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x0>; +- clock-frequency = <1600000000>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x1>; +- clock-frequency = <1600000000>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x2>; +- clock-frequency = <1600000000>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x3>; +- clock-frequency = <1600000000>; +- }; +- }; +- +- soc: soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- pmu_system_controller: system-controller@10040000 { +- compatible = "samsung,exynos5410-pmu", "syscon"; +- reg = <0x10040000 0x5000>; +- clock-names = "clkout16"; +- clocks = <&fin_pll>; +- #clock-cells = <1>; +- }; +- +- clock: clock-controller@10010000 { +- compatible = "samsung,exynos5410-clock"; +- reg = <0x10010000 0x30000>; +- #clock-cells = <1>; +- }; +- +- clock_audss: audss-clock-controller@3810000 { +- compatible = "samsung,exynos5410-audss-clock"; +- reg = <0x03810000 0x0C>; +- #clock-cells = <1>; +- clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>; +- clock-names = "pll_ref", "pll_in"; +- }; +- +- tmu_cpu0: tmu@10060000 { +- compatible = "samsung,exynos5420-tmu"; +- reg = <0x10060000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_TMU>; +- clock-names = "tmu_apbif"; +- #thermal-sensor-cells = <0>; +- }; +- +- tmu_cpu1: tmu@10064000 { +- compatible = "samsung,exynos5420-tmu"; +- reg = <0x10064000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_TMU>; +- clock-names = "tmu_apbif"; +- #thermal-sensor-cells = <0>; +- }; +- +- tmu_cpu2: tmu@10068000 { +- compatible = "samsung,exynos5420-tmu"; +- reg = <0x10068000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_TMU>; +- clock-names = "tmu_apbif"; +- #thermal-sensor-cells = <0>; +- }; +- +- tmu_cpu3: tmu@1006c000 { +- compatible = "samsung,exynos5420-tmu"; +- reg = <0x1006c000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_TMU>; +- clock-names = "tmu_apbif"; +- #thermal-sensor-cells = <0>; +- }; +- +- mmc_0: mmc@12200000 { +- compatible = "samsung,exynos5250-dw-mshc"; +- reg = <0x12200000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x80>; +- status = "disabled"; +- }; +- +- mmc_1: mmc@12210000 { +- compatible = "samsung,exynos5250-dw-mshc"; +- reg = <0x12210000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x80>; +- status = "disabled"; +- }; +- +- mmc_2: mmc@12220000 { +- compatible = "samsung,exynos5250-dw-mshc"; +- reg = <0x12220000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x80>; +- status = "disabled"; +- }; +- +- pinctrl_0: pinctrl@13400000 { +- compatible = "samsung,exynos5410-pinctrl"; +- reg = <0x13400000 0x1000>; +- interrupts = ; +- +- wakeup-interrupt-controller { +- compatible = "samsung,exynos4210-wakeup-eint"; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +- +- pinctrl_1: pinctrl@14000000 { +- compatible = "samsung,exynos5410-pinctrl"; +- reg = <0x14000000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_2: pinctrl@10d10000 { +- compatible = "samsung,exynos5410-pinctrl"; +- reg = <0x10d10000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_3: pinctrl@3860000 { +- compatible = "samsung,exynos5410-pinctrl"; +- reg = <0x03860000 0x1000>; +- interrupts = ; +- }; +- +- pdma0: pdma@121a0000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x121a0000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_PDMA0>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- }; +- +- pdma1: pdma@121b0000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x121b0000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_PDMA1>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- }; +- +- audi2s0: i2s@3830000 { +- compatible = "samsung,exynos5420-i2s"; +- reg = <0x03830000 0x100>; +- dmas = <&pdma0 10>, +- <&pdma0 9>, +- <&pdma0 8>; +- dma-names = "tx", "rx", "tx-sec"; +- clocks = <&clock_audss EXYNOS_I2S_BUS>, +- <&clock_audss EXYNOS_I2S_BUS>, +- <&clock_audss EXYNOS_SCLK_I2S>; +- clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; +- #clock-cells = <1>; +- clock-output-names = "i2s_cdclk0"; +- #sound-dai-cells = <1>; +- samsung,idma-addr = <0x03000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&audi2s0_bus>; +- status = "disabled"; +- }; +- }; +- +- thermal-zones { +- cpu0_thermal: cpu0-thermal { +- thermal-sensors = <&tmu_cpu0>; +- #include "exynos5420-trip-points.dtsi" +- }; +- cpu1_thermal: cpu1-thermal { +- thermal-sensors = <&tmu_cpu1>; +- #include "exynos5420-trip-points.dtsi" +- }; +- cpu2_thermal: cpu2-thermal { +- thermal-sensors = <&tmu_cpu2>; +- #include "exynos5420-trip-points.dtsi" +- }; +- cpu3_thermal: cpu3-thermal { +- thermal-sensors = <&tmu_cpu3>; +- #include "exynos5420-trip-points.dtsi" +- }; +- }; +-}; +- +-&adc { +- clocks = <&clock CLK_TSADC>; +- clock-names = "adc"; +- samsung,syscon-phandle = <&pmu_system_controller>; +-}; +- +-&arm_a15_pmu { +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- status = "okay"; +-}; +- +-&i2c_0 { +- clocks = <&clock CLK_I2C0>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_bus>; +-}; +- +-&i2c_1 { +- clocks = <&clock CLK_I2C1>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_bus>; +-}; +- +-&i2c_2 { +- clocks = <&clock CLK_I2C2>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_bus>; +-}; +- +-&i2c_3 { +- clocks = <&clock CLK_I2C3>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_bus>; +-}; +- +-&hsi2c_4 { +- clocks = <&clock CLK_USI0>; +- clock-names = "hsi2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_hs_bus>; +-}; +- +-&hsi2c_5 { +- clocks = <&clock CLK_USI1>; +- clock-names = "hsi2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_hs_bus>; +-}; +- +-&hsi2c_6 { +- clocks = <&clock CLK_USI2>; +- clock-names = "hsi2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c6_hs_bus>; +-}; +- +-&hsi2c_7 { +- clocks = <&clock CLK_USI3>; +- clock-names = "hsi2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c7_hs_bus>; +-}; +- +-&mct { +- clocks = <&fin_pll>, <&clock CLK_MCT>; +- clock-names = "fin_pll", "mct"; +-}; +- +-&prng { +- clocks = <&clock CLK_SSS>; +- clock-names = "secss"; +-}; +- +-&pwm { +- clocks = <&clock CLK_PWM>; +- clock-names = "timers"; +-}; +- +-&rtc { +- clocks = <&clock CLK_RTC>; +- clock-names = "rtc"; +- status = "disabled"; +-}; +- +-&serial_0 { +- clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; +- clock-names = "uart", "clk_uart_baud0"; +- dmas = <&pdma0 13>, <&pdma0 14>; +- dma-names = "rx", "tx"; +-}; +- +-&serial_1 { +- clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; +- clock-names = "uart", "clk_uart_baud0"; +- dmas = <&pdma1 15>, <&pdma1 16>; +- dma-names = "rx", "tx"; +-}; +- +-&serial_2 { +- clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; +- clock-names = "uart", "clk_uart_baud0"; +- dmas = <&pdma0 15>, <&pdma0 16>; +- dma-names = "rx", "tx"; +-}; +- +-&serial_3 { +- clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; +- clock-names = "uart", "clk_uart_baud0"; +- dmas = <&pdma1 17>, <&pdma1 18>; +- dma-names = "rx", "tx"; +-}; +- +-&sss { +- clocks = <&clock CLK_SSS>; +- clock-names = "secss"; +-}; +- +-&sromc { +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0 0x04000000 0x20000 +- 1 0 0x05000000 0x20000 +- 2 0 0x06000000 0x20000 +- 3 0 0x07000000 0x20000>; +-}; +- +-&trng { +- clocks = <&clock CLK_SSS>; +- clock-names = "secss"; +-}; +- +-&usbdrd3_0 { +- clocks = <&clock CLK_USBD300>; +- clock-names = "usbdrd30"; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb3_0_oc>, <&usb3_0_vbusctrl>; +-}; +- +-&usbdrd_phy0 { +- clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; +- clock-names = "phy", "ref"; +- samsung,pmu-syscon = <&pmu_system_controller>; +-}; +- +-&usbdrd3_1 { +- clocks = <&clock CLK_USBD301>; +- clock-names = "usbdrd30"; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb3_1_oc>, <&usb3_1_vbusctrl>; +-}; +- +-&usbdrd_dwc3_1 { +- interrupts = ; +-}; +- +-&usbdrd_phy1 { +- clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; +- clock-names = "phy", "ref"; +- samsung,pmu-syscon = <&pmu_system_controller>; +-}; +- +-&usbhost1 { +- clocks = <&clock CLK_USBH20>; +- clock-names = "usbhost"; +-}; +- +-&usbhost2 { +- clocks = <&clock CLK_USBH20>; +- clock-names = "usbhost"; +-}; +- +-&usb2_phy { +- clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; +- clock-names = "phy", "ref"; +- samsung,sysreg-phandle = <&sysreg_system_controller>; +- samsung,pmureg-phandle = <&pmu_system_controller>; +-}; +- +-&watchdog { +- clocks = <&clock CLK_WDT>; +- clock-names = "watchdog"; +- samsung,syscon-phandle = <&pmu_system_controller>; +-}; +- +-#include "exynos5410-pinctrl.dtsi" +-#include "exynos-syscon-restart.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/exynos5420-arndale-octa.dts b/scripts/dtc/include-prefixes/arm/exynos5420-arndale-octa.dts +deleted file mode 100644 +index dfc7f14f5772..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5420-arndale-octa.dts ++++ /dev/null +@@ -1,827 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos5420 based Arndale Octa board device tree source +- * +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-/dts-v1/; +-#include "exynos5420.dtsi" +-#include "exynos5420-cpus.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "Insignal Arndale Octa evaluation board based on Exynos5420"; +- compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5"; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x80000000>; +- }; +- +- chosen { +- stdout-path = "serial3:115200n8"; +- }; +- +- firmware@2073000 { +- compatible = "samsung,secure-firmware"; +- reg = <0x02073000 0x1000>; +- }; +- +- fixed-rate-clocks { +- oscclk { +- compatible = "samsung,exynos5420-oscclk"; +- clock-frequency = <24000000>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- wakeup { +- label = "SW-TACT1"; +- gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +-}; +- +-&adc { +- vdd-supply = <&ldo4_reg>; +- status = "okay"; +-}; +- +-&cci { +- status = "disabled"; +-}; +- +-&cpu0 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&cpu4 { +- cpu-supply = <&buck6_reg>; +-}; +- +-&cpu0_thermal { +- trips { +- cpu0_alert0: cpu-alert-0 { +- temperature = <60000>; /* millicelsius */ +- hysteresis = <5000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu0_alert1: cpu-alert-1 { +- temperature = <80000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu0_alert2: cpu-alert-2 { +- temperature = <110000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu0_crit0: cpu-crit-0 { +- temperature = <120000>; /* millicelsius */ +- hysteresis = <0>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- /* +- * Reduce the CPU speed by 2 steps, down to: 1600 MHz +- * and 1100 MHz. +- */ +- map0 { +- trip = <&cpu0_alert0>; +- cooling-device = <&cpu0 0 2>, +- <&cpu1 0 2>, +- <&cpu2 0 2>, +- <&cpu3 0 2>, +- <&cpu4 0 2>, +- <&cpu5 0 2>, +- <&cpu6 0 2>, +- <&cpu7 0 2>; +- }; +- +- /* +- * Reduce the CPU speed down to 1200 MHz big (6 steps) +- * and 800 MHz LITTLE (5 steps). +- */ +- map1 { +- trip = <&cpu0_alert1>; +- cooling-device = <&cpu0 3 6>, +- <&cpu1 3 6>, +- <&cpu2 3 6>, +- <&cpu3 3 6>, +- <&cpu4 3 5>, +- <&cpu5 3 5>, +- <&cpu6 3 5>, +- <&cpu7 3 5>; +- }; +- +- /* +- * Reduce the CPU speed as much as possible, down to 700 MHz +- * big (11 steps) and 600 MHz LITTLE (7 steps). +- */ +- map2 { +- trip = <&cpu0_alert2>; +- cooling-device = <&cpu0 6 11>, +- <&cpu1 6 11>, +- <&cpu2 6 11>, +- <&cpu3 6 11>, +- <&cpu4 5 7>, +- <&cpu5 5 7>, +- <&cpu6 5 7>, +- <&cpu7 5 7>; +- }; +- }; +-}; +- +-&cpu1_thermal { +- trips { +- cpu1_alert0: cpu-alert-0 { +- temperature = <60000>; /* millicelsius */ +- hysteresis = <5000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu1_alert1: cpu-alert-1 { +- temperature = <80000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu1_alert2: cpu-alert-2 { +- temperature = <110000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu1_crit0: cpu-crit-0 { +- temperature = <120000>; /* millicelsius */ +- hysteresis = <0>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu1_alert0>; +- cooling-device = <&cpu0 0 2>, +- <&cpu1 0 2>, +- <&cpu2 0 2>, +- <&cpu3 0 2>, +- <&cpu4 0 2>, +- <&cpu5 0 2>, +- <&cpu6 0 2>, +- <&cpu7 0 2>; +- }; +- +- map1 { +- trip = <&cpu1_alert1>; +- cooling-device = <&cpu0 3 6>, +- <&cpu1 3 6>, +- <&cpu2 3 6>, +- <&cpu3 3 6>, +- <&cpu4 3 5>, +- <&cpu5 3 5>, +- <&cpu6 3 5>, +- <&cpu7 3 5>; +- }; +- +- map2 { +- trip = <&cpu1_alert2>; +- cooling-device = <&cpu0 6 11>, +- <&cpu1 6 11>, +- <&cpu2 6 11>, +- <&cpu3 6 11>, +- <&cpu4 5 7>, +- <&cpu5 5 7>, +- <&cpu6 5 7>, +- <&cpu7 5 7>; +- }; +- }; +-}; +- +-&cpu2_thermal { +- trips { +- cpu2_alert0: cpu-alert-0 { +- temperature = <60000>; /* millicelsius */ +- hysteresis = <5000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu2_alert1: cpu-alert-1 { +- temperature = <80000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu2_alert2: cpu-alert-2 { +- temperature = <110000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu2_crit0: cpu-crit-0 { +- temperature = <120000>; /* millicelsius */ +- hysteresis = <0>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu2_alert0>; +- cooling-device = <&cpu0 0 2>, +- <&cpu1 0 2>, +- <&cpu2 0 2>, +- <&cpu3 0 2>, +- <&cpu4 0 2>, +- <&cpu5 0 2>, +- <&cpu6 0 2>, +- <&cpu7 0 2>; +- }; +- +- map1 { +- trip = <&cpu2_alert1>; +- cooling-device = <&cpu0 3 6>, +- <&cpu1 3 6>, +- <&cpu2 3 6>, +- <&cpu3 3 6>, +- <&cpu4 3 5>, +- <&cpu5 3 5>, +- <&cpu6 3 5>, +- <&cpu7 3 5>; +- }; +- +- map2 { +- trip = <&cpu2_alert2>; +- cooling-device = <&cpu0 6 11>, +- <&cpu1 6 11>, +- <&cpu2 6 11>, +- <&cpu3 6 11>, +- <&cpu4 6 7>, +- <&cpu5 6 7>, +- <&cpu6 6 7>, +- <&cpu7 6 7>; +- }; +- }; +-}; +- +-&cpu3_thermal { +- trips { +- cpu3_alert0: cpu-alert-0 { +- temperature = <60000>; /* millicelsius */ +- hysteresis = <5000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu3_alert1: cpu-alert-1 { +- temperature = <80000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu3_alert2: cpu-alert-2 { +- temperature = <110000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu3_crit0: cpu-crit-0 { +- temperature = <120000>; /* millicelsius */ +- hysteresis = <0>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu3_alert0>; +- cooling-device = <&cpu0 0 2>, +- <&cpu1 0 2>, +- <&cpu2 0 2>, +- <&cpu3 0 2>, +- <&cpu4 0 2>, +- <&cpu5 0 2>, +- <&cpu6 0 2>, +- <&cpu7 0 2>; +- }; +- +- map1 { +- trip = <&cpu3_alert1>; +- cooling-device = <&cpu0 3 6>, +- <&cpu1 3 6>, +- <&cpu2 3 6>, +- <&cpu3 3 6>, +- <&cpu4 3 5>, +- <&cpu5 3 5>, +- <&cpu6 3 5>, +- <&cpu7 3 5>; +- }; +- +- map2 { +- trip = <&cpu3_alert2>; +- cooling-device = <&cpu0 6 11>, +- <&cpu1 6 11>, +- <&cpu2 6 11>, +- <&cpu3 6 11>, +- <&cpu4 5 7>, +- <&cpu5 5 7>, +- <&cpu6 5 7>, +- <&cpu7 5 7>; +- }; +- }; +-}; +- +-&hdmi { +- hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; +- vdd_osc-supply = <&ldo7_reg>; +- vdd_pll-supply = <&ldo6_reg>; +- vdd-supply = <&ldo6_reg>; +- ddc = <&i2c_2>; +- status = "okay"; +-}; +- +-&hsi2c_4 { +- status = "okay"; +- +- pmic@66 { +- compatible = "samsung,s2mps11-pmic"; +- reg = <0x66>; +- +- interrupt-parent = <&gpx3>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&s2mps11_irq>; +- wakeup-source; +- +- s2mps11_osc: clocks { +- compatible = "samsung,s2mps11-clk"; +- #clock-cells = <1>; +- clock-output-names = "s2mps11_ap", +- "s2mps11_cp", "s2mps11_bt"; +- }; +- +- regulators { +- ldo1_reg: LDO1 { +- regulator-name = "PVDD_ALIVE_1V0"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "PVDD_APIO_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "PVDD_APIO_MMCON_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- /* +- * Must be always on, even though there is +- * a consumer (mmc_0). Otherwise the board +- * does not reboot with vendor U-Boot +- * (Linaro for Arndale Octa, v2012.07). +- */ +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "PVDD_ADC_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "PVDD_PLL_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "PVDD_ANAIP_1V0"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "PVDD_ANAIP_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "PVDD_ABB_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "PVDD_USB_3V3"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "PVDD_PRE_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "PVDD_USB_1V0"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "PVDD_HSIC_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "PVDD_APIO_MMCOFF_2V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo14_reg: LDO14 { +- /* Unused */ +- regulator-name = "PVDD_LDO14"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "PVDD_PERI_2V8"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "PVDD_PERI_3V3"; +- regulator-min-microvolt = <2200000>; +- regulator-max-microvolt = <2200000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo17_reg: LDO17 { +- /* Unused */ +- regulator-name = "PVDD_LDO17"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo18_reg: LDO18 { +- regulator-name = "PVDD_EMMC_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- /* +- * Must stay in "off" mode during shutdown for +- * proper eMMC reset. The "off" mode is in +- * fact controlled by LDO18EN. The eMMC does +- * not have reset pin connected so the reset +- * will be triggered by falling edge of +- * LDO18EN. +- */ +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo19_reg: LDO19 { +- regulator-name = "PVDD_TFLASH_2V8"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo20_reg: LDO20 { +- regulator-name = "PVDD_BTWIFI_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo21_reg: LDO21 { +- regulator-name = "PVDD_CAM1IO_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo22_reg: LDO22 { +- /* Unused */ +- regulator-name = "PVDD_LDO22"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <2375000>; +- }; +- +- ldo23_reg: LDO23 { +- regulator-name = "PVDD_MIFS_1V1"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo24_reg: LDO24 { +- regulator-name = "PVDD_CAM1_AVDD_2V8"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo25_reg: LDO25 { +- /* Unused */ +- regulator-name = "PVDD_LDO25"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo26_reg: LDO26 { +- regulator-name = "PVDD_CAM0_AF_2V8"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- ldo27_reg: LDO27 { +- regulator-name = "PVDD_G3DS_1V0"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo28_reg: LDO28 { +- regulator-name = "PVDD_TSP_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo29_reg: LDO29 { +- regulator-name = "PVDD_AUDIO_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo30_reg: LDO30 { +- /* Unused */ +- regulator-name = "PVDD_LDO30"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo31_reg: LDO31 { +- regulator-name = "PVDD_PERI_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo32_reg: LDO32 { +- regulator-name = "PVDD_LCD_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo33_reg: LDO33 { +- regulator-name = "PVDD_CAM0IO_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo34_reg: LDO34 { +- /* Unused */ +- regulator-name = "PVDD_LDO34"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo35_reg: LDO35 { +- regulator-name = "PVDD_CAM0_DVDD_1V2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo36_reg: LDO36 { +- /* Unused */ +- regulator-name = "PVDD_LDO36"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo37_reg: LDO37 { +- /* Unused */ +- regulator-name = "PVDD_LDO37"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo38_reg: LDO38 { +- regulator-name = "PVDD_CAM0_AVDD_2V8"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "PVDD_MIF_1V1"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "PVDD_ARM_1V0"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "PVDD_INT_1V0"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "PVDD_G3D_1V0"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "PVDD_LPDDR3_1V2"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- }; +- +- buck6_reg: BUCK6 { +- regulator-name = "PVDD_KFC_1V0"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck7_reg: BUCK7 { +- regulator-name = "VIN_LLDO_1V4"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- +- buck8_reg: BUCK8 { +- regulator-name = "VIN_MLDO_2V0"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2100000>; +- regulator-always-on; +- }; +- +- buck9_reg: BUCK9 { +- regulator-name = "VIN_HLDO_3V5"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3500000>; +- regulator-always-on; +- }; +- +- buck10_reg: BUCK10 { +- regulator-name = "PVDD_EMMCF_2V8"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- /* +- * Must stay in "off" mode during shutdown for +- * proper eMMC reset. The "off" mode is in +- * fact controlled by BUCK10EN. The eMMC does +- * not have reset pin connected so the reset +- * will be triggered by falling edge of +- * BUCK10EN. +- */ +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +-}; +- +-&i2c_2 { +- status = "okay"; +-}; +- +-&mixer { +- status = "okay"; +-}; +- +-&mmc_0 { +- status = "okay"; +- non-removable; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <0 4>; +- samsung,dw-mshc-ddr-timing = <0 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; +- vmmc-supply = <&ldo18_reg>; +- vqmmc-supply = <&ldo3_reg>; +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +-}; +- +-&mmc_2 { +- status = "okay"; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <0 4>; +- samsung,dw-mshc-ddr-timing = <0 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; +- vmmc-supply = <&ldo19_reg>; +- vqmmc-supply = <&ldo13_reg>; +- bus-width = <4>; +- cap-sd-highspeed; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- sd-uhs-ddr50; +-}; +- +-&pinctrl_0 { +- s2mps11_irq: s2mps11-irq { +- samsung,pins = "gpx3-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&usbdrd_dwc3_1 { +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5420-cpus.dtsi b/scripts/dtc/include-prefixes/arm/exynos5420-cpus.dtsi +deleted file mode 100644 +index e9f4eb75b50f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5420-cpus.dtsi ++++ /dev/null +@@ -1,163 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung Exynos5420 SoC cpu device tree source +- * +- * Copyright (c) 2015 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * This file provides desired ordering for Exynos5420 and Exynos5800 +- * boards: CPU[0123] being the A15. +- * +- * The Exynos5420, 5422 and 5800 actually share the same CPU configuration +- * but particular boards choose different booting order. +- * +- * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422 +- * booting cluster (big or LITTLE) is chosen by IROM code by reading +- * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting +- * from the LITTLE: Cortex-A7. +- */ +- +-/ { +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- core2 { +- cpu = <&cpu2>; +- }; +- core3 { +- cpu = <&cpu3>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&cpu4>; +- }; +- core1 { +- cpu = <&cpu5>; +- }; +- core2 { +- cpu = <&cpu6>; +- }; +- core3 { +- cpu = <&cpu7>; +- }; +- }; +- }; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x0>; +- clocks = <&clock CLK_ARM_CLK>; +- clock-frequency = <1800000000>; +- cci-control-port = <&cci_control1>; +- operating-points-v2 = <&cluster_a15_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- capacity-dmips-mhz = <1024>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x1>; +- clocks = <&clock CLK_ARM_CLK>; +- clock-frequency = <1800000000>; +- cci-control-port = <&cci_control1>; +- operating-points-v2 = <&cluster_a15_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- capacity-dmips-mhz = <1024>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x2>; +- clocks = <&clock CLK_ARM_CLK>; +- clock-frequency = <1800000000>; +- cci-control-port = <&cci_control1>; +- operating-points-v2 = <&cluster_a15_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- capacity-dmips-mhz = <1024>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x3>; +- clocks = <&clock CLK_ARM_CLK>; +- clock-frequency = <1800000000>; +- cci-control-port = <&cci_control1>; +- operating-points-v2 = <&cluster_a15_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- capacity-dmips-mhz = <1024>; +- }; +- +- cpu4: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x100>; +- clocks = <&clock CLK_KFC_CLK>; +- clock-frequency = <1000000000>; +- cci-control-port = <&cci_control0>; +- operating-points-v2 = <&cluster_a7_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- capacity-dmips-mhz = <539>; +- }; +- +- cpu5: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x101>; +- clocks = <&clock CLK_KFC_CLK>; +- clock-frequency = <1000000000>; +- cci-control-port = <&cci_control0>; +- operating-points-v2 = <&cluster_a7_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- capacity-dmips-mhz = <539>; +- }; +- +- cpu6: cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x102>; +- clocks = <&clock CLK_KFC_CLK>; +- clock-frequency = <1000000000>; +- cci-control-port = <&cci_control0>; +- operating-points-v2 = <&cluster_a7_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- capacity-dmips-mhz = <539>; +- }; +- +- cpu7: cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x103>; +- clocks = <&clock CLK_KFC_CLK>; +- clock-frequency = <1000000000>; +- cci-control-port = <&cci_control0>; +- operating-points-v2 = <&cluster_a7_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- capacity-dmips-mhz = <539>; +- }; +- }; +-}; +- +-&arm_a7_pmu { +- interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; +- status = "okay"; +-}; +- +-&arm_a15_pmu { +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5420-peach-pit.dts b/scripts/dtc/include-prefixes/arm/exynos5420-peach-pit.dts +deleted file mode 100644 +index 315b3dc9c017..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5420-peach-pit.dts ++++ /dev/null +@@ -1,1118 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Google Peach Pit Rev 6+ board device tree source +- * +- * Copyright (c) 2014 Google, Inc +- */ +- +-/dts-v1/; +-#include +-#include +-#include +-#include +-#include +-#include +-#include "exynos5420.dtsi" +-#include "exynos5420-cpus.dtsi" +- +-/ { +- model = "Google Peach Pit Rev 6+"; +- +- compatible = "google,pit-rev16", +- "google,pit-rev15", "google,pit-rev14", +- "google,pit-rev13", "google,pit-rev12", +- "google,pit-rev11", "google,pit-rev10", +- "google,pit-rev9", "google,pit-rev8", +- "google,pit-rev7", "google,pit-rev6", +- "google,pit", "google,peach","samsung,exynos5420", +- "samsung,exynos5"; +- +- aliases { +- /* Assign 20 so we don't get confused w/ builtin ones */ +- i2c20 = &i2c_tunnel; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 1000000 0>; +- brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; +- default-brightness-level = <7>; +- power-supply = <&tps65090_fet1>; +- pinctrl-0 = <&pwm0_out>; +- pinctrl-names = "default"; +- }; +- +- chosen { +- stdout-path = "serial3:115200n8"; +- }; +- +- fixed-rate-clocks { +- oscclk { +- compatible = "samsung,exynos5420-oscclk"; +- clock-frequency = <24000000>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&power_key_irq &lid_irq>; +- +- power { +- label = "Power"; +- gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- lid-switch { +- label = "Lid"; +- gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; +- linux,input-type = <5>; /* EV_SW */ +- linux,code = <0>; /* SW_LID */ +- debounce-interval = <1>; +- wakeup-source; +- }; +- }; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x80000000>; +- }; +- +- sound { +- compatible = "google,snow-audio-max98090"; +- +- samsung,model = "Peach-Pit-I2S-MAX98090"; +- samsung,i2s-controller = <&i2s0>; +- samsung,audio-codec = <&max98090>; +- +- cpu { +- sound-dai = <&i2s0 0>; +- }; +- +- codec { +- sound-dai = <&max98090>, <&hdmi>; +- }; +- }; +- +- usb300_vbus_reg: regulator-usb300 { +- compatible = "regulator-fixed"; +- regulator-name = "P5.0V_USB3CON0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gph0 0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb300_vbus_en>; +- enable-active-high; +- }; +- +- usb301_vbus_reg: regulator-usb301 { +- compatible = "regulator-fixed"; +- regulator-name = "P5.0V_USB3CON1"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gph0 1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb301_vbus_en>; +- enable-active-high; +- }; +- +- vbat: fixed-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vbat-supply"; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- panel: panel { +- compatible = "auo,b116xw03"; +- power-supply = <&tps65090_fet6>; +- backlight = <&backlight>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&bridge_out>; +- }; +- }; +- }; +- +- mmc1_pwrseq: mmc1-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */ +- clocks = <&max77802 MAX77802_CLK_32K_CP>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&adc { +- status = "okay"; +- vdd-supply = <&ldo9_reg>; +-}; +- +-&clock_audss { +- assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; +- assigned-clock-parents = <&clock CLK_MAU_EPLL>; +-}; +- +-&cpu0 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&cpu4 { +- cpu-supply = <&buck6_reg>; +-}; +- +-&dp { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dp_hpd_gpio>; +- samsung,color-space = <0>; +- samsung,color-depth = <1>; +- samsung,link-rate = <0x06>; +- samsung,lane-count = <2>; +- hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; +- +- ports { +- port { +- dp_out: endpoint { +- remote-endpoint = <&bridge_in>; +- }; +- }; +- }; +-}; +- +-&fimd { +- status = "okay"; +- samsung,invert-vclk; +-}; +- +-&hdmi { +- status = "okay"; +- hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_hpd_irq>; +- ddc = <&i2c_2>; +- +- hdmi-en-supply = <&tps65090_fet7>; +- vdd-supply = <&ldo8_reg>; +- vdd_osc-supply = <&ldo10_reg>; +- vdd_pll-supply = <&ldo8_reg>; +-}; +- +-&hsi2c_4 { +- status = "okay"; +- clock-frequency = <400000>; +- +- max77802: pmic@9 { +- compatible = "maxim,max77802"; +- interrupt-parent = <&gpx3>; +- interrupts = <1 IRQ_TYPE_NONE>; +- pinctrl-names = "default"; +- pinctrl-0 = <&max77802_irq>, <&pmic_selb>, +- <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>; +- wakeup-source; +- reg = <0x9>; +- #clock-cells = <1>; +- +- inb1-supply = <&tps65090_dcdc2>; +- inb2-supply = <&tps65090_dcdc1>; +- inb3-supply = <&tps65090_dcdc2>; +- inb4-supply = <&tps65090_dcdc2>; +- inb5-supply = <&tps65090_dcdc1>; +- inb6-supply = <&tps65090_dcdc2>; +- inb7-supply = <&tps65090_dcdc1>; +- inb8-supply = <&tps65090_dcdc1>; +- inb9-supply = <&tps65090_dcdc1>; +- inb10-supply = <&tps65090_dcdc1>; +- +- inl1-supply = <&buck5_reg>; +- inl2-supply = <&buck7_reg>; +- inl3-supply = <&buck9_reg>; +- inl4-supply = <&buck9_reg>; +- inl5-supply = <&buck9_reg>; +- inl6-supply = <&tps65090_dcdc2>; +- inl7-supply = <&buck9_reg>; +- inl9-supply = <&tps65090_dcdc2>; +- inl10-supply = <&buck7_reg>; +- +- regulators { +- buck1_reg: BUCK1 { +- regulator-name = "vdd_mif"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-ramp-delay = <12500>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-ramp-delay = <12500>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "vdd_int"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-ramp-delay = <12500>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "vdd_g3d"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-ramp-delay = <12500>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "vdd_1v2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck6_reg: BUCK6 { +- regulator-name = "vdd_kfc"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-ramp-delay = <12500>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck7_reg: BUCK7 { +- regulator-name = "vdd_1v35"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- buck8_reg: BUCK8 { +- regulator-name = "vdd_emmc"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck9_reg: BUCK9 { +- regulator-name = "vdd_2v"; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- buck10_reg: BUCK10 { +- regulator-name = "vdd_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo1_reg: LDO1 { +- regulator-name = "vdd_1v0"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-mode = ; +- }; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "vdd_1v2_2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "vdd_1v8_3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-mode = ; +- }; +- }; +- +- vqmmc_sdcard: ldo4_reg: LDO4 { +- regulator-name = "vdd_sd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "vdd_1v8_5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "vdd_1v8_6"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "vdd_1v8_7"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "vdd_ldo8"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "vdd_ldo9"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-mode = ; +- }; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "vdd_ldo10"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "vdd_ldo11"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-mode = ; +- }; +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "vdd_ldo12"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "vdd_ldo13"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-mode = ; +- }; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "vdd_ldo14"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "vdd_ldo15"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "vdd_g3ds"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo18_reg: LDO18 { +- regulator-name = "ldo_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo19_reg: LDO19 { +- regulator-name = "ldo_19"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo20_reg: LDO20 { +- regulator-name = "ldo_20"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo21_reg: LDO21 { +- regulator-name = "ldo_21"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo23_reg: LDO23 { +- regulator-name = "ldo_23"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- ldo24_reg: LDO24 { +- regulator-name = "ldo_24"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo25_reg: LDO25 { +- regulator-name = "ldo_25"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo26_reg: LDO26 { +- regulator-name = "ldo_26"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo27_reg: LDO27 { +- regulator-name = "ldo_27"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo28_reg: LDO28 { +- regulator-name = "ldo_28"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo29_reg: LDO29 { +- regulator-name = "ldo_29"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo30_reg: LDO30 { +- regulator-name = "vdd_mifs"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo32_reg: LDO32 { +- regulator-name = "ldo_32"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- ldo33_reg: LDO33 { +- regulator-name = "ldo_33"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo34_reg: LDO34 { +- regulator-name = "ldo_34"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- ldo35_reg: LDO35 { +- regulator-name = "ldo_35"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- }; +- }; +-}; +- +-&hsi2c_7 { +- status = "okay"; +- clock-frequency = <400000>; +- +- max98090: audio-codec@10 { +- compatible = "maxim,max98090"; +- reg = <0x10>; +- interrupts = <2 IRQ_TYPE_NONE>; +- interrupt-parent = <&gpx0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&max98090_irq>; +- clocks = <&pmu_system_controller 0>; +- clock-names = "mclk"; +- #sound-dai-cells = <0>; +- }; +- +- light-sensor@44 { +- compatible = "isil,isl29018"; +- reg = <0x44>; +- vcc-supply = <&tps65090_fet5>; +- }; +- +- ps8625: lvds-bridge@48 { +- compatible = "parade,ps8625"; +- reg = <0x48>; +- sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>; +- lane-count = <2>; +- use-external-pwm; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- bridge_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- bridge_in: endpoint { +- remote-endpoint = <&dp_out>; +- }; +- }; +- }; +- +- }; +-}; +- +-&hsi2c_8 { +- status = "okay"; +- clock-frequency = <333000>; +- +- /* Atmel mXT336S */ +- trackpad@4b { +- compatible = "atmel,maxtouch"; +- reg = <0x4b>; +- interrupt-parent = <&gpx1>; +- interrupts = <1 IRQ_TYPE_EDGE_FALLING>; +- wakeup-source; +- pinctrl-names = "default"; +- pinctrl-0 = <&trackpad_irq>; +- linux,gpio-keymap = ; /* GPIO3 */ +- }; +-}; +- +-&hsi2c_9 { +- status = "okay"; +- clock-frequency = <400000>; +- +- tpm@20 { +- compatible = "infineon,slb9645tt"; +- reg = <0x20>; +- +- /* Unused irq; but still need to configure the pins */ +- pinctrl-names = "default"; +- pinctrl-0 = <&tpm_irq>; +- }; +-}; +- +-&i2c_2 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <66000>; +- samsung,i2c-slave-addr = <0x50>; +-}; +- +-&i2s0 { +- assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; +- assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>; +- status = "okay"; +-}; +- +-&mixer { +- status = "okay"; +-}; +- +-/* eMMC flash */ +-&mmc_0 { +- status = "okay"; +- mmc-hs200-1_8v; +- cap-mmc-highspeed; +- non-removable; +- clock-frequency = <400000000>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <0 4>; +- samsung,dw-mshc-ddr-timing = <0 2>; +- samsung,dw-mshc-hs400-timing = <0 2>; +- samsung,read-strobe-delay = <90>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; +- bus-width = <8>; +-}; +- +-/* WiFi SDIO module */ +-&mmc_1 { +- status = "okay"; +- non-removable; +- cap-sdio-irq; +- keep-power-in-suspend; +- clock-frequency = <400000000>; +- samsung,dw-mshc-ciu-div = <1>; +- samsung,dw-mshc-sdr-timing = <0 1>; +- samsung,dw-mshc-ddr-timing = <0 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>, +- <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>; +- bus-width = <4>; +- cap-sd-highspeed; +- mmc-pwrseq = <&mmc1_pwrseq>; +- vqmmc-supply = <&buck10_reg>; +-}; +- +-/* uSD card */ +-&mmc_2 { +- status = "okay"; +- cap-sd-highspeed; +- card-detect-delay = <200>; +- clock-frequency = <400000000>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; +- bus-width = <4>; +-}; +- +- +-&pinctrl_0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mask_tpm_reset>; +- +- wifi_en: wifi-en { +- samsung,pins = "gpx0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- max98090_irq: max98090-irq { +- samsung,pins = "gpx0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- /* We need GPX0_6 to be low at sleep time; just keep it low always */ +- mask_tpm_reset: mask-tpm-reset { +- samsung,pins = "gpx0-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- samsung,pin-val = <0>; +- }; +- +- tpm_irq: tpm-irq { +- samsung,pins = "gpx1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- trackpad_irq: trackpad-irq { +- samsung,pins = "gpx1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- power_key_irq: power-key-irq { +- samsung,pins = "gpx1-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- ec_irq: ec-irq { +- samsung,pins = "gpx1-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- tps65090_irq: tps65090-irq { +- samsung,pins = "gpx2-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- dp_hpd_gpio: dp_hpd_gpio { +- samsung,pins = "gpx2-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- max77802_irq: max77802-irq { +- samsung,pins = "gpx3-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lid_irq: lid-irq { +- samsung,pins = "gpx3-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hdmi_hpd_irq: hdmi-hpd-irq { +- samsung,pins = "gpx3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pmic_dvs_1: pmic-dvs-1 { +- samsung,pins = "gpy7-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_1 { +- /* Adjust WiFi drive strengths lower for EMI */ +- sd1_clk: sd1-clk { +- samsung,pin-drv = ; +- }; +- +- sd1_cmd: sd1-cmd { +- samsung,pin-drv = ; +- }; +- +- sd1_bus1: sd1-bus-width1 { +- samsung,pin-drv = ; +- }; +- +- sd1_bus4: sd1-bus-width4 { +- samsung,pin-drv = ; +- }; +- +- sd1_bus8: sd1-bus-width8 { +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_2 { +- pmic_dvs_2: pmic-dvs-2 { +- samsung,pins = "gpj4-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pmic_dvs_3: pmic-dvs-3 { +- samsung,pins = "gpj4-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_3 { +- /* Drive SPI lines at x2 for better integrity */ +- spi2-bus { +- samsung,pin-drv = ; +- }; +- +- /* Drive SPI chip select at x2 for better integrity */ +- ec_spi_cs: ec-spi-cs { +- samsung,pins = "gpb1-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- usb300_vbus_en: usb300-vbus-en { +- samsung,pins = "gph0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- usb301_vbus_en: usb301-vbus-en { +- samsung,pins = "gph0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pmic_selb: pmic-selb { +- samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", +- "gph0-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pmu_system_controller { +- assigned-clocks = <&pmu_system_controller 0>; +- assigned-clock-parents = <&clock CLK_FIN_PLL>; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&spi_2 { +- status = "okay"; +- num-cs = <1>; +- samsung,spi-src-clk = <0>; +- cs-gpios = <&gpb1 2 GPIO_ACTIVE_HIGH>; +- +- cros_ec: cros-ec@0 { +- compatible = "google,cros-ec-spi"; +- interrupt-parent = <&gpx1>; +- interrupts = <5 IRQ_TYPE_NONE>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ec_spi_cs &ec_irq>; +- reg = <0>; +- spi-max-frequency = <3125000>; +- google,has-vbc-nvram; +- +- controller-data { +- samsung,spi-feedback-delay = <1>; +- }; +- +- i2c_tunnel: i2c-tunnel { +- compatible = "google,cros-ec-i2c-tunnel"; +- #address-cells = <1>; +- #size-cells = <0>; +- google,remote-bus = <0>; +- +- battery: sbs-battery@b { +- compatible = "sbs,sbs-battery"; +- reg = <0xb>; +- sbs,poll-retry-count = <1>; +- sbs,i2c-retry-count = <2>; +- }; +- +- power-regulator@48 { +- compatible = "ti,tps65090"; +- reg = <0x48>; +- +- /* +- * Config irq to disable internal pulls +- * even though we run in polling mode. +- */ +- pinctrl-names = "default"; +- pinctrl-0 = <&tps65090_irq>; +- +- vsys1-supply = <&vbat>; +- vsys2-supply = <&vbat>; +- vsys3-supply = <&vbat>; +- infet1-supply = <&vbat>; +- infet2-supply = <&tps65090_dcdc1>; +- infet3-supply = <&tps65090_dcdc2>; +- infet4-supply = <&tps65090_dcdc2>; +- infet5-supply = <&tps65090_dcdc2>; +- infet6-supply = <&tps65090_dcdc2>; +- infet7-supply = <&tps65090_dcdc1>; +- vsys-l1-supply = <&vbat>; +- vsys-l2-supply = <&vbat>; +- +- regulators { +- tps65090_dcdc1: dcdc1 { +- ti,enable-ext-control; +- }; +- tps65090_dcdc2: dcdc2 { +- ti,enable-ext-control; +- }; +- tps65090_dcdc3: dcdc3 { +- ti,enable-ext-control; +- }; +- tps65090_fet1: fet1 { +- regulator-name = "vcd_led"; +- }; +- tps65090_fet2: fet2 { +- regulator-name = "video_mid"; +- regulator-always-on; +- }; +- tps65090_fet3: fet3 { +- regulator-name = "wwan_r"; +- regulator-always-on; +- }; +- tps65090_fet4: fet4 { +- regulator-name = "sdcard"; +- regulator-always-on; +- }; +- tps65090_fet5: fet5 { +- regulator-name = "camout"; +- regulator-always-on; +- }; +- tps65090_fet6: fet6 { +- regulator-name = "lcd_vdd"; +- }; +- tps65090_fet7: fet7 { +- regulator-name = "video_mid_1a"; +- regulator-always-on; +- }; +- tps65090_ldo1: ldo1 { +- }; +- tps65090_ldo2: ldo2 { +- }; +- }; +- +- charger { +- compatible = "ti,tps65090-charger"; +- }; +- }; +- }; +- }; +-}; +- +-&serial_3 { +- status = "okay"; +-}; +- +-&timer { +- arm,cpu-registers-not-fw-configured; +-}; +- +-&tmu_cpu0 { +- vtmu-supply = <&ldo10_reg>; +-}; +- +-&tmu_cpu1 { +- vtmu-supply = <&ldo10_reg>; +-}; +- +-&tmu_cpu2 { +- vtmu-supply = <&ldo10_reg>; +-}; +- +-&tmu_cpu3 { +- vtmu-supply = <&ldo10_reg>; +-}; +- +-&tmu_gpu { +- vtmu-supply = <&ldo10_reg>; +-}; +- +-&usbdrd_dwc3_0 { +- dr_mode = "host"; +-}; +- +-&usbdrd_dwc3_1 { +- dr_mode = "host"; +-}; +- +-&usbdrd_phy0 { +- vbus-supply = <&usb300_vbus_reg>; +-}; +- +-&usbdrd_phy1 { +- vbus-supply = <&usb301_vbus_reg>; +-}; +- +-/* +- * Use longest HW watchdog in SoC (32 seconds) since the hardware +- * watchdog provides no debugging information (compared to soft/hard +- * lockup detectors) and so should be last resort. +- */ +-&watchdog { +- timeout-sec = <32>; +-}; +- +-#include "cros-ec-keyboard.dtsi" +-#include "cros-adc-thermistors.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/exynos5420-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/exynos5420-pinctrl.dtsi +deleted file mode 100644 +index b82af7c89654..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5420-pinctrl.dtsi ++++ /dev/null +@@ -1,734 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source +- * +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device +- * tree nodes are listed in this file. +- */ +- +-#include +- +-&pinctrl_0 { +- gpy7: gpy7 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpx0: gpx0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- interrupt-parent = <&combiner>; +- #interrupt-cells = <2>; +- interrupts = <23 0>, <24 0>, <25 0>, <25 1>, +- <26 0>, <26 1>, <27 0>, <27 1>; +- }; +- +- gpx1: gpx1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- interrupt-parent = <&combiner>; +- #interrupt-cells = <2>; +- interrupts = <28 0>, <28 1>, <29 0>, <29 1>, +- <30 0>, <30 1>, <31 0>, <31 1>; +- }; +- +- gpx2: gpx2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpx3: gpx3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- dp_hpd: dp_hpd { +- samsung,pins = "gpx0-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hdmi_cec: hdmi-cec { +- samsung,pins = "gpx3-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_1 { +- gpc0: gpc0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc1: gpc1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc2: gpc2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc3: gpc3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc4: gpc4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd1: gpd1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpy0: gpy0 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy1: gpy1 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy2: gpy2 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy3: gpy3 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy4: gpy4 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy5: gpy5 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpy6: gpy6 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- sd0_clk: sd0-clk { +- samsung,pins = "gpc0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_cmd: sd0-cmd { +- samsung,pins = "gpc0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_cd: sd0-cd { +- samsung,pins = "gpc0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus1: sd0-bus-width1 { +- samsung,pins = "gpc0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus4: sd0-bus-width4 { +- samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus8: sd0-bus-width8 { +- samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_rclk: sd0-rclk { +- samsung,pins = "gpc0-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_clk: sd1-clk { +- samsung,pins = "gpc1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_cmd: sd1-cmd { +- samsung,pins = "gpc1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_cd: sd1-cd { +- samsung,pins = "gpc1-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_int: sd1-int { +- samsung,pins = "gpd1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus1: sd1-bus-width1 { +- samsung,pins = "gpc1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus4: sd1-bus-width4 { +- samsung,pins = "gpc1-4", "gpc1-5", "gpc1-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus8: sd1-bus-width8 { +- samsung,pins = "gpd1-4", "gpd1-5", "gpd1-6", "gpd1-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_clk: sd2-clk { +- samsung,pins = "gpc2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cmd: sd2-cmd { +- samsung,pins = "gpc2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cd: sd2-cd { +- samsung,pins = "gpc2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus1: sd2-bus-width1 { +- samsung,pins = "gpc2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus4: sd2-bus-width4 { +- samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_wp: sd2-wp { +- samsung,pins = "gpc4-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_2 { +- gpe0: gpe0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpe1: gpe1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf0: gpf0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf1: gpf1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg0: gpg0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg1: gpg1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg2: gpg2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpj4: gpj4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- cam_gpio_a: cam-gpio-a { +- samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", +- "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", +- "gpe1-0", "gpe1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_gpio_b: cam-gpio-b { +- samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", +- "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_i2c2_bus: cam-i2c2-bus { +- samsung,pins = "gpf0-4", "gpf0-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_spi1_bus: cam-spi1-bus { +- samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_i2c1_bus: cam-i2c1-bus { +- samsung,pins = "gpf0-2", "gpf0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_i2c0_bus: cam-i2c0-bus { +- samsung,pins = "gpf0-0", "gpf0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_spi0_bus: cam-spi0-bus { +- samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_bayrgb_bus: cam-bayrgb-bus { +- samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", +- "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", +- "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", +- "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", +- "gpg2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_3 { +- gpa0: gpa0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpa1: gpa1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpa2: gpa2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb0: gpb0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb1: gpb1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb2: gpb2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb3: gpb3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb4: gpb4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gph0: gph0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- uart0_data: uart0-data { +- samsung,pins = "gpa0-0", "gpa0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart0_fctl: uart0-fctl { +- samsung,pins = "gpa0-2", "gpa0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart1_data: uart1-data { +- samsung,pins = "gpa0-4", "gpa0-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart1_fctl: uart1-fctl { +- samsung,pins = "gpa0-6", "gpa0-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c2_bus: i2c2-bus { +- samsung,pins = "gpa0-6", "gpa0-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart2_data: uart2-data { +- samsung,pins = "gpa1-0", "gpa1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart2_fctl: uart2-fctl { +- samsung,pins = "gpa1-2", "gpa1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c3_bus: i2c3-bus { +- samsung,pins = "gpa1-2", "gpa1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart3_data: uart3-data { +- samsung,pins = "gpa1-4", "gpa1-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi0_bus: spi0-bus { +- samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi1_bus: spi1-bus { +- samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c4_hs_bus: i2c4-hs-bus { +- samsung,pins = "gpa2-0", "gpa2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c5_hs_bus: i2c5-hs-bus { +- samsung,pins = "gpa2-2", "gpa2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2s1_bus: i2s1-bus { +- samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", +- "gpb0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pcm1_bus: pcm1-bus { +- samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", +- "gpb0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2s2_bus: i2s2-bus { +- samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", +- "gpb1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pcm2_bus: pcm2-bus { +- samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", +- "gpb1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spdif_bus: spdif-bus { +- samsung,pins = "gpb1-0", "gpb1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi2_bus: spi2-bus { +- samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c6_hs_bus: i2c6-hs-bus { +- samsung,pins = "gpb1-3", "gpb1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm0_out: pwm0-out { +- samsung,pins = "gpb2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm1_out: pwm1-out { +- samsung,pins = "gpb2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm2_out: pwm2-out { +- samsung,pins = "gpb2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm3_out: pwm3-out { +- samsung,pins = "gpb2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c7_hs_bus: i2c7-hs-bus { +- samsung,pins = "gpb2-2", "gpb2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c0_bus: i2c0-bus { +- samsung,pins = "gpb3-0", "gpb3-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c1_bus: i2c1-bus { +- samsung,pins = "gpb3-2", "gpb3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c8_hs_bus: i2c8-hs-bus { +- samsung,pins = "gpb3-4", "gpb3-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c9_hs_bus: i2c9-hs-bus { +- samsung,pins = "gpb3-6", "gpb3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c10_hs_bus: i2c10-hs-bus { +- samsung,pins = "gpb4-0", "gpb4-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_4 { +- gpz: gpz { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- i2s0_bus: i2s0-bus { +- samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", +- "gpz-4", "gpz-5", "gpz-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5420-smdk5420.dts b/scripts/dtc/include-prefixes/arm/exynos5420-smdk5420.dts +deleted file mode 100644 +index a4f0e3ffedbd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5420-smdk5420.dts ++++ /dev/null +@@ -1,416 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung SMDK5420 board device tree source +- * +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-/dts-v1/; +-#include "exynos5420.dtsi" +-#include "exynos5420-cpus.dtsi" +-#include +-#include +- +-/ { +- model = "Samsung SMDK5420 board based on Exynos5420"; +- compatible = "samsung,smdk5420", "samsung,exynos5420", "samsung,exynos5"; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x80000000>; +- }; +- +- chosen { +- bootargs = "init=/linuxrc"; +- stdout-path = "serial2:115200n8"; +- }; +- +- fixed-rate-clocks { +- oscclk { +- compatible = "samsung,exynos5420-oscclk"; +- clock-frequency = <24000000>; +- }; +- }; +- +- vdd: regulator-0 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-supply"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- dbvdd: regulator-1 { +- compatible = "regulator-fixed"; +- regulator-name = "dbvdd-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- spkvdd: regulator-2 { +- compatible = "regulator-fixed"; +- regulator-name = "spkvdd-supply"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- usb300_vbus_reg: regulator-3 { +- compatible = "regulator-fixed"; +- regulator-name = "VBUS0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpg0 5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb300_vbus_en>; +- enable-active-high; +- }; +- +- usb301_vbus_reg: regulator-4 { +- compatible = "regulator-fixed"; +- regulator-name = "VBUS1"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpg1 4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb301_vbus_en>; +- enable-active-high; +- }; +- +-}; +- +-&cpu0 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&cpu4 { +- cpu-supply = <&buck6_reg>; +-}; +- +-&dp { +- pinctrl-names = "default"; +- pinctrl-0 = <&dp_hpd>; +- samsung,color-space = <0>; +- samsung,color-depth = <1>; +- samsung,link-rate = <0x0a>; +- samsung,lane-count = <4>; +- status = "okay"; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing { +- clock-frequency = <50000>; +- hactive = <2560>; +- vactive = <1600>; +- hfront-porch = <48>; +- hback-porch = <80>; +- hsync-len = <32>; +- vback-porch = <16>; +- vfront-porch = <8>; +- vsync-len = <6>; +- }; +- }; +-}; +- +-&fimd { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +- ddc = <&i2c_2>; +- hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_hpd_irq>; +-}; +- +-&hsi2c_4 { +- status = "okay"; +- +- pmic@66 { +- compatible = "samsung,s2mps11-pmic"; +- reg = <0x66>; +- wakeup-source; +- +- s2mps11_osc: clocks { +- compatible = "samsung,s2mps11-clk"; +- #clock-cells = <1>; +- clock-output-names = "s2mps11_ap", +- "s2mps11_cp", "s2mps11_bt"; +- }; +- +- regulators { +- ldo1_reg: LDO1 { +- regulator-name = "vdd_ldo1"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "vdd_ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "vdd_ldo5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "vdd_ldo6"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "vdd_ldo7"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "vdd_ldo8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "vdd_ldo9"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "vdd_ldo10"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "vdd_ldo11"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "vdd_ldo12"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "vdd_ldo13"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "vdd_ldo15"; +- regulator-min-microvolt = <3100000>; +- regulator-max-microvolt = <3100000>; +- regulator-always-on; +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "vdd_ldo16"; +- regulator-min-microvolt = <2200000>; +- regulator-max-microvolt = <2200000>; +- regulator-always-on; +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "tsp_avdd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo19_reg: LDO19 { +- regulator-name = "vdd_sd"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- ldo24_reg: LDO24 { +- regulator-name = "tsp_io"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "vdd_mif"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "vdd_int"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "vdd_g3d"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "vdd_mem"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck6_reg: BUCK6 { +- regulator-name = "vdd_kfc"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck7_reg: BUCK7 { +- regulator-name = "vdd_1.0v_ldo"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck8_reg: BUCK8 { +- regulator-name = "vdd_1.8v_ldo"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck9_reg: BUCK9 { +- regulator-name = "vdd_2.8v_ldo"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3750000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck10_reg: BUCK10 { +- regulator-name = "vdd_vmem"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&i2c_2 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <66000>; +- /* used by HDMI DDC */ +- status = "okay"; +-}; +- +-&mixer { +- status = "okay"; +-}; +- +-&mmc_0 { +- status = "okay"; +- broken-cd; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <0 4>; +- samsung,dw-mshc-ddr-timing = <0 2>; +- samsung,dw-mshc-hs400-timing = <0 2>; +- samsung,read-strobe-delay = <90>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 +- &sd0_rclk>; +- bus-width = <8>; +- cap-mmc-highspeed; +-}; +- +-&mmc_2 { +- status = "okay"; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; +- bus-width = <4>; +- cap-sd-highspeed; +-}; +- +-&pinctrl_0 { +- hdmi_hpd_irq: hdmi-hpd-irq { +- samsung,pins = "gpx3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_2 { +- usb300_vbus_en: usb300-vbus-en { +- samsung,pins = "gpg0-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- usb301_vbus_en: usb301-vbus-en { +- samsung,pins = "gpg1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&usbdrd_phy0 { +- vbus-supply = <&usb300_vbus_reg>; +-}; +- +-&usbdrd_phy1 { +- vbus-supply = <&usb301_vbus_reg>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5420-trip-points.dtsi b/scripts/dtc/include-prefixes/arm/exynos5420-trip-points.dtsi +deleted file mode 100644 +index a67a380717ec..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5420-trip-points.dtsi ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device tree sources for default Exynos5420 thermal zone definition +- * +- * Copyright (c) 2014 Lukasz Majewski +- */ +- +-polling-delay-passive = <0>; +-polling-delay = <0>; +-trips { +- cpu-alert-0 { +- temperature = <85000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "active"; +- }; +- cpu-alert-1 { +- temperature = <103000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "active"; +- }; +- cpu-alert-2 { +- temperature = <110000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "active"; +- }; +- cpu-crit-0 { +- temperature = <120000>; /* millicelsius */ +- hysteresis = <0>; /* millicelsius */ +- type = "critical"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5420.dtsi b/scripts/dtc/include-prefixes/arm/exynos5420.dtsi +deleted file mode 100644 +index e23e8ffb093f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5420.dtsi ++++ /dev/null +@@ -1,1413 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung Exynos5420 SoC device tree source +- * +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Samsung Exynos5420 SoC device nodes are listed in this file. +- * Exynos5420 based board files can include this file and provide +- * values for board specfic bindings. +- */ +- +-#include "exynos54xx.dtsi" +-#include +-#include +-#include +- +-/ { +- compatible = "samsung,exynos5420", "samsung,exynos5"; +- +- aliases { +- mshc0 = &mmc_0; +- mshc1 = &mmc_1; +- mshc2 = &mmc_2; +- pinctrl0 = &pinctrl_0; +- pinctrl1 = &pinctrl_1; +- pinctrl2 = &pinctrl_2; +- pinctrl3 = &pinctrl_3; +- pinctrl4 = &pinctrl_4; +- i2c8 = &hsi2c_8; +- i2c9 = &hsi2c_9; +- i2c10 = &hsi2c_10; +- gsc0 = &gsc_0; +- gsc1 = &gsc_1; +- spi0 = &spi_0; +- spi1 = &spi_1; +- spi2 = &spi_2; +- }; +- +- /* +- * The 'cpus' node is not present here but instead it is provided +- * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. +- */ +- +- cluster_a15_opp_table: opp-table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <1250000 1250000 1500000>; +- clock-latency-ns = <140000>; +- }; +- opp-1700000000 { +- opp-hz = /bits/ 64 <1700000000>; +- opp-microvolt = <1212500 1212500 1500000>; +- clock-latency-ns = <140000>; +- }; +- opp-1600000000 { +- opp-hz = /bits/ 64 <1600000000>; +- opp-microvolt = <1175000 1175000 1500000>; +- clock-latency-ns = <140000>; +- }; +- opp-1500000000 { +- opp-hz = /bits/ 64 <1500000000>; +- opp-microvolt = <1137500 1137500 1500000>; +- clock-latency-ns = <140000>; +- }; +- opp-1400000000 { +- opp-hz = /bits/ 64 <1400000000>; +- opp-microvolt = <1112500 1112500 1500000>; +- clock-latency-ns = <140000>; +- }; +- opp-1300000000 { +- opp-hz = /bits/ 64 <1300000000>; +- opp-microvolt = <1062500 1062500 1500000>; +- clock-latency-ns = <140000>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <1037500 1037500 1500000>; +- clock-latency-ns = <140000>; +- }; +- opp-1100000000 { +- opp-hz = /bits/ 64 <1100000000>; +- opp-microvolt = <1012500 1012500 1500000>; +- clock-latency-ns = <140000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = < 987500 987500 1500000>; +- clock-latency-ns = <140000>; +- }; +- opp-900000000 { +- opp-hz = /bits/ 64 <900000000>; +- opp-microvolt = < 962500 962500 1500000>; +- clock-latency-ns = <140000>; +- }; +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = < 937500 937500 1500000>; +- clock-latency-ns = <140000>; +- }; +- opp-700000000 { +- opp-hz = /bits/ 64 <700000000>; +- opp-microvolt = < 912500 912500 1500000>; +- clock-latency-ns = <140000>; +- }; +- }; +- +- cluster_a7_opp_table: opp-table1 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-1300000000 { +- opp-hz = /bits/ 64 <1300000000>; +- opp-microvolt = <1275000>; +- clock-latency-ns = <140000>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <1212500>; +- clock-latency-ns = <140000>; +- }; +- opp-1100000000 { +- opp-hz = /bits/ 64 <1100000000>; +- opp-microvolt = <1162500>; +- clock-latency-ns = <140000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <1112500>; +- clock-latency-ns = <140000>; +- }; +- opp-900000000 { +- opp-hz = /bits/ 64 <900000000>; +- opp-microvolt = <1062500>; +- clock-latency-ns = <140000>; +- }; +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <1025000>; +- clock-latency-ns = <140000>; +- }; +- opp-700000000 { +- opp-hz = /bits/ 64 <700000000>; +- opp-microvolt = <975000>; +- clock-latency-ns = <140000>; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <937500>; +- clock-latency-ns = <140000>; +- }; +- }; +- +- soc: soc { +- cci: cci@10d20000 { +- compatible = "arm,cci-400"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x10d20000 0x1000>; +- ranges = <0x0 0x10d20000 0x6000>; +- +- cci_control0: slave-if@4000 { +- compatible = "arm,cci-400-ctrl-if"; +- interface-type = "ace"; +- reg = <0x4000 0x1000>; +- }; +- cci_control1: slave-if@5000 { +- compatible = "arm,cci-400-ctrl-if"; +- interface-type = "ace"; +- reg = <0x5000 0x1000>; +- }; +- }; +- +- clock: clock-controller@10010000 { +- compatible = "samsung,exynos5420-clock", "syscon"; +- reg = <0x10010000 0x30000>; +- #clock-cells = <1>; +- }; +- +- clock_audss: audss-clock-controller@3810000 { +- compatible = "samsung,exynos5420-audss-clock"; +- reg = <0x03810000 0x0C>; +- #clock-cells = <1>; +- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, +- <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; +- clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; +- power-domains = <&mau_pd>; +- }; +- +- mfc: codec@11000000 { +- compatible = "samsung,mfc-v7"; +- reg = <0x11000000 0x10000>; +- interrupts = ; +- clocks = <&clock CLK_MFC>; +- clock-names = "mfc"; +- power-domains = <&mfc_pd>; +- iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; +- iommu-names = "left", "right"; +- }; +- +- mmc_0: mmc@12200000 { +- compatible = "samsung,exynos5420-dw-mshc-smu"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x12200000 0x2000>; +- clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x40>; +- status = "disabled"; +- }; +- +- mmc_1: mmc@12210000 { +- compatible = "samsung,exynos5420-dw-mshc-smu"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x12210000 0x2000>; +- clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x40>; +- status = "disabled"; +- }; +- +- mmc_2: mmc@12220000 { +- compatible = "samsung,exynos5420-dw-mshc"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x12220000 0x1000>; +- clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x40>; +- status = "disabled"; +- }; +- +- dmc: memory-controller@10c20000 { +- compatible = "samsung,exynos5422-dmc"; +- reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; +- clocks = <&clock CLK_FOUT_SPLL>, +- <&clock CLK_MOUT_SCLK_SPLL>, +- <&clock CLK_FF_DOUT_SPLL2>, +- <&clock CLK_FOUT_BPLL>, +- <&clock CLK_MOUT_BPLL>, +- <&clock CLK_SCLK_BPLL>, +- <&clock CLK_MOUT_MX_MSPLL_CCORE>, +- <&clock CLK_MOUT_MCLK_CDREX>; +- clock-names = "fout_spll", +- "mout_sclk_spll", +- "ff_dout_spll2", +- "fout_bpll", +- "mout_bpll", +- "sclk_bpll", +- "mout_mx_mspll_ccore", +- "mout_mclk_cdrex"; +- samsung,syscon-clk = <&clock>; +- status = "disabled"; +- }; +- +- nocp_mem0_0: nocp@10ca1000 { +- compatible = "samsung,exynos5420-nocp"; +- reg = <0x10CA1000 0x200>; +- status = "disabled"; +- }; +- +- nocp_mem0_1: nocp@10ca1400 { +- compatible = "samsung,exynos5420-nocp"; +- reg = <0x10CA1400 0x200>; +- status = "disabled"; +- }; +- +- nocp_mem1_0: nocp@10ca1800 { +- compatible = "samsung,exynos5420-nocp"; +- reg = <0x10CA1800 0x200>; +- status = "disabled"; +- }; +- +- nocp_mem1_1: nocp@10ca1c00 { +- compatible = "samsung,exynos5420-nocp"; +- reg = <0x10CA1C00 0x200>; +- status = "disabled"; +- }; +- +- nocp_g3d_0: nocp@11a51000 { +- compatible = "samsung,exynos5420-nocp"; +- reg = <0x11A51000 0x200>; +- status = "disabled"; +- }; +- +- nocp_g3d_1: nocp@11a51400 { +- compatible = "samsung,exynos5420-nocp"; +- reg = <0x11A51400 0x200>; +- status = "disabled"; +- }; +- +- ppmu_dmc0_0: ppmu@10d00000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x10d00000 0x2000>; +- clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; +- clock-names = "ppmu"; +- events { +- ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 { +- event-name = "ppmu-event3-dmc0_0"; +- }; +- }; +- }; +- +- ppmu_dmc0_1: ppmu@10d10000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x10d10000 0x2000>; +- clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; +- clock-names = "ppmu"; +- events { +- ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 { +- event-name = "ppmu-event3-dmc0_1"; +- }; +- }; +- }; +- +- ppmu_dmc1_0: ppmu@10d60000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x10d60000 0x2000>; +- clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; +- clock-names = "ppmu"; +- events { +- ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 { +- event-name = "ppmu-event3-dmc1_0"; +- }; +- }; +- }; +- +- ppmu_dmc1_1: ppmu@10d70000 { +- compatible = "samsung,exynos-ppmu"; +- reg = <0x10d70000 0x2000>; +- clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; +- clock-names = "ppmu"; +- events { +- ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 { +- event-name = "ppmu-event3-dmc1_1"; +- }; +- }; +- }; +- +- gsc_pd: power-domain@10044000 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10044000 0x20>; +- #power-domain-cells = <0>; +- label = "GSC"; +- }; +- +- isp_pd: power-domain@10044020 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10044020 0x20>; +- #power-domain-cells = <0>; +- label = "ISP"; +- }; +- +- mfc_pd: power-domain@10044060 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10044060 0x20>; +- #power-domain-cells = <0>; +- label = "MFC"; +- }; +- +- g3d_pd: power-domain@10044080 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10044080 0x20>; +- #power-domain-cells = <0>; +- label = "G3D"; +- }; +- +- disp_pd: power-domain@100440c0 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x100440C0 0x20>; +- #power-domain-cells = <0>; +- label = "DISP"; +- }; +- +- mau_pd: power-domain@100440e0 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x100440E0 0x20>; +- #power-domain-cells = <0>; +- label = "MAU"; +- }; +- +- msc_pd: power-domain@10044120 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10044120 0x20>; +- #power-domain-cells = <0>; +- label = "MSC"; +- }; +- +- pinctrl_0: pinctrl@13400000 { +- compatible = "samsung,exynos5420-pinctrl"; +- reg = <0x13400000 0x1000>; +- interrupts = ; +- +- wakeup-interrupt-controller { +- compatible = "samsung,exynos4210-wakeup-eint"; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +- +- pinctrl_1: pinctrl@13410000 { +- compatible = "samsung,exynos5420-pinctrl"; +- reg = <0x13410000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_2: pinctrl@14000000 { +- compatible = "samsung,exynos5420-pinctrl"; +- reg = <0x14000000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_3: pinctrl@14010000 { +- compatible = "samsung,exynos5420-pinctrl"; +- reg = <0x14010000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_4: pinctrl@3860000 { +- compatible = "samsung,exynos5420-pinctrl"; +- reg = <0x03860000 0x1000>; +- interrupts = ; +- power-domains = <&mau_pd>; +- }; +- +- adma: adma@3880000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x03880000 0x1000>; +- interrupts = ; +- clocks = <&clock_audss EXYNOS_ADMA>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <6>; +- #dma-requests = <16>; +- power-domains = <&mau_pd>; +- }; +- +- pdma0: pdma@121a0000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x121A0000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_PDMA0>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- }; +- +- pdma1: pdma@121b0000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x121B0000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_PDMA1>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- }; +- +- mdma0: mdma@10800000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x10800000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_MDMA0>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <1>; +- }; +- +- mdma1: mdma@11c10000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x11C10000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_MDMA1>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <1>; +- /* +- * MDMA1 can support both secure and non-secure +- * AXI transactions. When this is enabled in +- * the kernel for boards that run in secure +- * mode, we are getting imprecise external +- * aborts causing the kernel to oops. +- */ +- status = "disabled"; +- }; +- +- i2s0: i2s@3830000 { +- compatible = "samsung,exynos5420-i2s"; +- reg = <0x03830000 0x100>; +- dmas = <&adma 0>, +- <&adma 2>, +- <&adma 1>; +- dma-names = "tx", "rx", "tx-sec"; +- clocks = <&clock_audss EXYNOS_I2S_BUS>, +- <&clock_audss EXYNOS_I2S_BUS>, +- <&clock_audss EXYNOS_SCLK_I2S>; +- clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; +- #clock-cells = <1>; +- clock-output-names = "i2s_cdclk0"; +- #sound-dai-cells = <1>; +- samsung,idma-addr = <0x03000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s0_bus>; +- power-domains = <&mau_pd>; +- status = "disabled"; +- }; +- +- i2s1: i2s@12d60000 { +- compatible = "samsung,exynos5420-i2s"; +- reg = <0x12D60000 0x100>; +- dmas = <&pdma1 12>, +- <&pdma1 11>; +- dma-names = "tx", "rx"; +- clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; +- clock-names = "iis", "i2s_opclk0"; +- #clock-cells = <1>; +- clock-output-names = "i2s_cdclk1"; +- #sound-dai-cells = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s1_bus>; +- status = "disabled"; +- }; +- +- i2s2: i2s@12d70000 { +- compatible = "samsung,exynos5420-i2s"; +- reg = <0x12D70000 0x100>; +- dmas = <&pdma0 12>, +- <&pdma0 11>; +- dma-names = "tx", "rx"; +- clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; +- clock-names = "iis", "i2s_opclk0"; +- #clock-cells = <1>; +- clock-output-names = "i2s_cdclk2"; +- #sound-dai-cells = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s2_bus>; +- status = "disabled"; +- }; +- +- spi_0: spi@12d20000 { +- compatible = "samsung,exynos4210-spi"; +- reg = <0x12d20000 0x100>; +- interrupts = ; +- dmas = <&pdma0 5 +- &pdma0 4>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_bus>; +- clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; +- clock-names = "spi", "spi_busclk0"; +- status = "disabled"; +- }; +- +- spi_1: spi@12d30000 { +- compatible = "samsung,exynos4210-spi"; +- reg = <0x12d30000 0x100>; +- interrupts = ; +- dmas = <&pdma1 5 +- &pdma1 4>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_bus>; +- clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; +- clock-names = "spi", "spi_busclk0"; +- status = "disabled"; +- }; +- +- spi_2: spi@12d40000 { +- compatible = "samsung,exynos4210-spi"; +- reg = <0x12d40000 0x100>; +- interrupts = ; +- dmas = <&pdma0 7 +- &pdma0 6>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_bus>; +- clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; +- clock-names = "spi", "spi_busclk0"; +- status = "disabled"; +- }; +- +- dp_phy: dp-video-phy { +- compatible = "samsung,exynos5420-dp-video-phy"; +- samsung,pmu-syscon = <&pmu_system_controller>; +- #phy-cells = <0>; +- }; +- +- mipi_phy: mipi-video-phy { +- compatible = "samsung,s5pv210-mipi-video-phy"; +- syscon = <&pmu_system_controller>; +- #phy-cells = <1>; +- }; +- +- dsi@14500000 { +- compatible = "samsung,exynos5410-mipi-dsi"; +- reg = <0x14500000 0x10000>; +- interrupts = ; +- phys = <&mipi_phy 1>; +- phy-names = "dsim"; +- clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; +- clock-names = "bus_clk", "pll_clk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- hsi2c_8: i2c@12e00000 { +- compatible = "samsung,exynos5250-hsi2c"; +- reg = <0x12E00000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c8_hs_bus>; +- clocks = <&clock CLK_USI4>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_9: i2c@12e10000 { +- compatible = "samsung,exynos5250-hsi2c"; +- reg = <0x12E10000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c9_hs_bus>; +- clocks = <&clock CLK_USI5>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_10: i2c@12e20000 { +- compatible = "samsung,exynos5250-hsi2c"; +- reg = <0x12E20000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c10_hs_bus>; +- clocks = <&clock CLK_USI6>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hdmi: hdmi@14530000 { +- compatible = "samsung,exynos5420-hdmi"; +- reg = <0x14530000 0x70000>; +- interrupts = ; +- clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, +- <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, +- <&clock CLK_MOUT_HDMI>; +- clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", +- "sclk_hdmiphy", "mout_hdmi"; +- phy = <&hdmiphy>; +- samsung,syscon-phandle = <&pmu_system_controller>; +- status = "disabled"; +- power-domains = <&disp_pd>; +- #sound-dai-cells = <0>; +- }; +- +- hdmiphy: hdmiphy@145d0000 { +- reg = <0x145D0000 0x20>; +- }; +- +- hdmicec: cec@101b0000 { +- compatible = "samsung,s5p-cec"; +- reg = <0x101B0000 0x200>; +- interrupts = ; +- clocks = <&clock CLK_HDMI_CEC>; +- clock-names = "hdmicec"; +- samsung,syscon-phandle = <&pmu_system_controller>; +- hdmi-phandle = <&hdmi>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_cec>; +- status = "disabled"; +- }; +- +- mixer: mixer@14450000 { +- compatible = "samsung,exynos5420-mixer"; +- reg = <0x14450000 0x10000>; +- interrupts = ; +- clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, +- <&clock CLK_SCLK_HDMI>; +- clock-names = "mixer", "hdmi", "sclk_hdmi"; +- power-domains = <&disp_pd>; +- iommus = <&sysmmu_tv>; +- status = "disabled"; +- }; +- +- rotator: rotator@11c00000 { +- compatible = "samsung,exynos5250-rotator"; +- reg = <0x11C00000 0x64>; +- interrupts = ; +- clocks = <&clock CLK_ROTATOR>; +- clock-names = "rotator"; +- iommus = <&sysmmu_rotator>; +- }; +- +- gsc_0: video-scaler@13e00000 { +- compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; +- reg = <0x13e00000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_GSCL0>; +- clock-names = "gscl"; +- power-domains = <&gsc_pd>; +- iommus = <&sysmmu_gscl0>; +- }; +- +- gsc_1: video-scaler@13e10000 { +- compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; +- reg = <0x13e10000 0x1000>; +- interrupts = ; +- clocks = <&clock CLK_GSCL1>; +- clock-names = "gscl"; +- power-domains = <&gsc_pd>; +- iommus = <&sysmmu_gscl1>; +- }; +- +- gpu: gpu@11800000 { +- compatible = "samsung,exynos5420-mali", "arm,mali-t628"; +- reg = <0x11800000 0x5000>; +- interrupts = , +- , +- ; +- interrupt-names = "job", "mmu", "gpu"; +- +- clocks = <&clock CLK_G3D>; +- clock-names = "core"; +- power-domains = <&g3d_pd>; +- operating-points-v2 = <&gpu_opp_table>; +- +- status = "disabled"; +- #cooling-cells = <2>; +- +- gpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-177000000 { +- opp-hz = /bits/ 64 <177000000>; +- opp-microvolt = <812500>; +- }; +- opp-266000000 { +- opp-hz = /bits/ 64 <266000000>; +- opp-microvolt = <862500>; +- }; +- opp-350000000 { +- opp-hz = /bits/ 64 <350000000>; +- opp-microvolt = <912500>; +- }; +- opp-420000000 { +- opp-hz = /bits/ 64 <420000000>; +- opp-microvolt = <962500>; +- }; +- opp-480000000 { +- opp-hz = /bits/ 64 <480000000>; +- opp-microvolt = <1000000>; +- }; +- opp-543000000 { +- opp-hz = /bits/ 64 <543000000>; +- opp-microvolt = <1037500>; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <1150000>; +- }; +- }; +- }; +- +- scaler_0: scaler@12800000 { +- compatible = "samsung,exynos5420-scaler"; +- reg = <0x12800000 0x1294>; +- interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clock CLK_MSCL0>; +- clock-names = "mscl"; +- power-domains = <&msc_pd>; +- iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>; +- }; +- +- scaler_1: scaler@12810000 { +- compatible = "samsung,exynos5420-scaler"; +- reg = <0x12810000 0x1294>; +- interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clock CLK_MSCL1>; +- clock-names = "mscl"; +- power-domains = <&msc_pd>; +- iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>; +- }; +- +- scaler_2: scaler@12820000 { +- compatible = "samsung,exynos5420-scaler"; +- reg = <0x12820000 0x1294>; +- interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clock CLK_MSCL2>; +- clock-names = "mscl"; +- power-domains = <&msc_pd>; +- iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>; +- }; +- +- jpeg_0: jpeg@11f50000 { +- compatible = "samsung,exynos5420-jpeg"; +- reg = <0x11F50000 0x1000>; +- interrupts = ; +- clock-names = "jpeg"; +- clocks = <&clock CLK_JPEG>; +- iommus = <&sysmmu_jpeg0>; +- }; +- +- jpeg_1: jpeg@11f60000 { +- compatible = "samsung,exynos5420-jpeg"; +- reg = <0x11F60000 0x1000>; +- interrupts = ; +- clock-names = "jpeg"; +- clocks = <&clock CLK_JPEG2>; +- iommus = <&sysmmu_jpeg1>; +- }; +- +- pmu_system_controller: system-controller@10040000 { +- compatible = "samsung,exynos5420-pmu", "syscon"; +- reg = <0x10040000 0x5000>; +- clock-names = "clkout16"; +- clocks = <&clock CLK_FIN_PLL>; +- #clock-cells = <1>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- }; +- +- tmu_cpu0: tmu@10060000 { +- compatible = "samsung,exynos5420-tmu"; +- reg = <0x10060000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_TMU>; +- clock-names = "tmu_apbif"; +- #thermal-sensor-cells = <0>; +- }; +- +- tmu_cpu1: tmu@10064000 { +- compatible = "samsung,exynos5420-tmu"; +- reg = <0x10064000 0x100>; +- interrupts = ; +- clocks = <&clock CLK_TMU>; +- clock-names = "tmu_apbif"; +- #thermal-sensor-cells = <0>; +- }; +- +- tmu_cpu2: tmu@10068000 { +- compatible = "samsung,exynos5420-tmu-ext-triminfo"; +- reg = <0x10068000 0x100>, <0x1006c000 0x4>; +- interrupts = ; +- clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; +- clock-names = "tmu_apbif", "tmu_triminfo_apbif"; +- #thermal-sensor-cells = <0>; +- }; +- +- tmu_cpu3: tmu@1006c000 { +- compatible = "samsung,exynos5420-tmu-ext-triminfo"; +- reg = <0x1006c000 0x100>, <0x100a0000 0x4>; +- interrupts = ; +- clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; +- clock-names = "tmu_apbif", "tmu_triminfo_apbif"; +- #thermal-sensor-cells = <0>; +- }; +- +- tmu_gpu: tmu@100a0000 { +- compatible = "samsung,exynos5420-tmu-ext-triminfo"; +- reg = <0x100a0000 0x100>, <0x10068000 0x4>; +- interrupts = ; +- clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; +- clock-names = "tmu_apbif", "tmu_triminfo_apbif"; +- #thermal-sensor-cells = <0>; +- }; +- +- sysmmu_g2dr: sysmmu@10a60000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x10A60000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <24 5>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_g2dw: sysmmu@10a70000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x10A70000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <22 2>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_tv: sysmmu@14650000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x14650000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <7 4>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>; +- power-domains = <&disp_pd>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_gscl0: sysmmu@13e80000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13E80000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <2 0>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; +- power-domains = <&gsc_pd>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_gscl1: sysmmu@13e90000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13E90000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <2 2>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; +- power-domains = <&gsc_pd>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_scaler0r: sysmmu@12880000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x12880000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <22 4>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; +- power-domains = <&msc_pd>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_scaler1r: sysmmu@12890000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x12890000 0x1000>; +- interrupts = ; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; +- power-domains = <&msc_pd>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_scaler2r: sysmmu@128a0000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x128A0000 0x1000>; +- interrupts = ; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; +- power-domains = <&msc_pd>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_scaler0w: sysmmu@128c0000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x128C0000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <27 2>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; +- power-domains = <&msc_pd>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_scaler1w: sysmmu@128d0000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x128D0000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <22 6>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; +- power-domains = <&msc_pd>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_scaler2w: sysmmu@128e0000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x128E0000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <19 6>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; +- power-domains = <&msc_pd>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_rotator: sysmmu@11d40000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x11D40000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <4 0>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_jpeg0: sysmmu@11f10000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x11F10000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <4 2>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_jpeg1: sysmmu@11f20000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x11F20000 0x1000>; +- interrupts = ; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_mfc_l: sysmmu@11200000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x11200000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <6 2>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; +- power-domains = <&mfc_pd>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_mfc_r: sysmmu@11210000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x11210000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <8 5>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; +- power-domains = <&mfc_pd>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimd1_0: sysmmu@14640000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x14640000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <3 2>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; +- power-domains = <&disp_pd>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_fimd1_1: sysmmu@14680000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x14680000 0x1000>; +- interrupt-parent = <&combiner>; +- interrupts = <3 0>; +- clock-names = "sysmmu", "master"; +- clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>; +- power-domains = <&disp_pd>; +- #iommu-cells = <0>; +- }; +- +- bus_wcore: bus-wcore { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DOUT_ACLK400_WCORE>; +- clock-names = "bus"; +- status = "disabled"; +- }; +- +- bus_noc: bus-noc { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DOUT_ACLK100_NOC>; +- clock-names = "bus"; +- status = "disabled"; +- }; +- +- bus_fsys_apb: bus-fsys-apb { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DOUT_PCLK200_FSYS>; +- clock-names = "bus"; +- status = "disabled"; +- }; +- +- bus_fsys: bus-fsys { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DOUT_ACLK200_FSYS>; +- clock-names = "bus"; +- status = "disabled"; +- }; +- +- bus_fsys2: bus-fsys2 { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; +- clock-names = "bus"; +- status = "disabled"; +- }; +- +- bus_mfc: bus-mfc { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DOUT_ACLK333>; +- clock-names = "bus"; +- status = "disabled"; +- }; +- +- bus_gen: bus-gen { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DOUT_ACLK266>; +- clock-names = "bus"; +- status = "disabled"; +- }; +- +- bus_peri: bus-peri { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DOUT_ACLK66>; +- clock-names = "bus"; +- status = "disabled"; +- }; +- +- bus_g2d: bus-g2d { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DOUT_ACLK333_G2D>; +- clock-names = "bus"; +- status = "disabled"; +- }; +- +- bus_g2d_acp: bus-g2d-acp { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DOUT_ACLK266_G2D>; +- clock-names = "bus"; +- status = "disabled"; +- }; +- +- bus_jpeg: bus-jpeg { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DOUT_ACLK300_JPEG>; +- clock-names = "bus"; +- status = "disabled"; +- }; +- +- bus_jpeg_apb: bus-jpeg-apb { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DOUT_ACLK166>; +- clock-names = "bus"; +- status = "disabled"; +- }; +- +- bus_disp1_fimd: bus-disp1-fimd { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DOUT_ACLK300_DISP1>; +- clock-names = "bus"; +- status = "disabled"; +- }; +- +- bus_disp1: bus-disp1 { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DOUT_ACLK400_DISP1>; +- clock-names = "bus"; +- status = "disabled"; +- }; +- +- bus_gscl_scaler: bus-gscl-scaler { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DOUT_ACLK300_GSCL>; +- clock-names = "bus"; +- status = "disabled"; +- }; +- +- bus_mscl: bus-mscl { +- compatible = "samsung,exynos-bus"; +- clocks = <&clock CLK_DOUT_ACLK400_MSCL>; +- clock-names = "bus"; +- status = "disabled"; +- }; +- }; +- +- thermal-zones { +- cpu0_thermal: cpu0-thermal { +- thermal-sensors = <&tmu_cpu0>; +- #include "exynos5420-trip-points.dtsi" +- }; +- cpu1_thermal: cpu1-thermal { +- thermal-sensors = <&tmu_cpu1>; +- #include "exynos5420-trip-points.dtsi" +- }; +- cpu2_thermal: cpu2-thermal { +- thermal-sensors = <&tmu_cpu2>; +- #include "exynos5420-trip-points.dtsi" +- }; +- cpu3_thermal: cpu3-thermal { +- thermal-sensors = <&tmu_cpu3>; +- #include "exynos5420-trip-points.dtsi" +- }; +- gpu_thermal: gpu-thermal { +- thermal-sensors = <&tmu_gpu>; +- #include "exynos5420-trip-points.dtsi" +- }; +- }; +-}; +- +-&adc { +- clocks = <&clock CLK_TSADC>; +- clock-names = "adc"; +- samsung,syscon-phandle = <&pmu_system_controller>; +-}; +- +-&dp { +- clocks = <&clock CLK_DP1>; +- clock-names = "dp"; +- phys = <&dp_phy>; +- phy-names = "dp"; +- power-domains = <&disp_pd>; +-}; +- +-&fimd { +- compatible = "samsung,exynos5420-fimd"; +- clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; +- clock-names = "sclk_fimd", "fimd"; +- power-domains = <&disp_pd>; +- iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>; +- iommu-names = "m0", "m1"; +-}; +- +-&g2d { +- iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>; +- clocks = <&clock CLK_G2D>; +- clock-names = "fimg2d"; +- status = "okay"; +-}; +- +-&i2c_0 { +- clocks = <&clock CLK_I2C0>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_bus>; +-}; +- +-&i2c_1 { +- clocks = <&clock CLK_I2C1>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_bus>; +-}; +- +-&i2c_2 { +- clocks = <&clock CLK_I2C2>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_bus>; +-}; +- +-&i2c_3 { +- clocks = <&clock CLK_I2C3>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_bus>; +-}; +- +-&hsi2c_4 { +- clocks = <&clock CLK_USI0>; +- clock-names = "hsi2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_hs_bus>; +-}; +- +-&hsi2c_5 { +- clocks = <&clock CLK_USI1>; +- clock-names = "hsi2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_hs_bus>; +-}; +- +-&hsi2c_6 { +- clocks = <&clock CLK_USI2>; +- clock-names = "hsi2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c6_hs_bus>; +-}; +- +-&hsi2c_7 { +- clocks = <&clock CLK_USI3>; +- clock-names = "hsi2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c7_hs_bus>; +-}; +- +-&mct { +- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; +- clock-names = "fin_pll", "mct"; +-}; +- +-&prng { +- clocks = <&clock CLK_SSS>; +- clock-names = "secss"; +-}; +- +-&pwm { +- clocks = <&clock CLK_PWM>; +- clock-names = "timers"; +-}; +- +-&rtc { +- clocks = <&clock CLK_RTC>; +- clock-names = "rtc"; +- interrupt-parent = <&pmu_system_controller>; +- status = "disabled"; +-}; +- +-&serial_0 { +- clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; +- clock-names = "uart", "clk_uart_baud0"; +- dmas = <&pdma0 13>, <&pdma0 14>; +- dma-names = "rx", "tx"; +-}; +- +-&serial_1 { +- clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; +- clock-names = "uart", "clk_uart_baud0"; +- dmas = <&pdma1 15>, <&pdma1 16>; +- dma-names = "rx", "tx"; +-}; +- +-&serial_2 { +- clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; +- clock-names = "uart", "clk_uart_baud0"; +- dmas = <&pdma0 15>, <&pdma0 16>; +- dma-names = "rx", "tx"; +-}; +- +-&serial_3 { +- clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; +- clock-names = "uart", "clk_uart_baud0"; +- dmas = <&pdma1 17>, <&pdma1 18>; +- dma-names = "rx", "tx"; +-}; +- +-&sss { +- clocks = <&clock CLK_SSS>; +- clock-names = "secss"; +-}; +- +-&trng { +- clocks = <&clock CLK_SSS>; +- clock-names = "secss"; +-}; +- +-&usbdrd3_0 { +- clocks = <&clock CLK_USBD300>; +- clock-names = "usbdrd30"; +-}; +- +-&usbdrd_phy0 { +- clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; +- clock-names = "phy", "ref"; +- samsung,pmu-syscon = <&pmu_system_controller>; +-}; +- +-&usbdrd3_1 { +- clocks = <&clock CLK_USBD301>; +- clock-names = "usbdrd30"; +-}; +- +-&usbdrd_dwc3_1 { +- interrupts = ; +-}; +- +-&usbdrd_phy1 { +- clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; +- clock-names = "phy", "ref"; +- samsung,pmu-syscon = <&pmu_system_controller>; +-}; +- +-&usbhost1 { +- clocks = <&clock CLK_USBH20>; +- clock-names = "usbhost"; +-}; +- +-&usbhost2 { +- clocks = <&clock CLK_USBH20>; +- clock-names = "usbhost"; +-}; +- +-&usb2_phy { +- clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; +- clock-names = "phy", "ref"; +- samsung,sysreg-phandle = <&sysreg_system_controller>; +- samsung,pmureg-phandle = <&pmu_system_controller>; +-}; +- +-&watchdog { +- clocks = <&clock CLK_WDT>; +- clock-names = "watchdog"; +- samsung,syscon-phandle = <&pmu_system_controller>; +-}; +- +-#include "exynos5420-pinctrl.dtsi" +-#include "exynos-syscon-restart.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/exynos5422-cpus.dtsi b/scripts/dtc/include-prefixes/arm/exynos5422-cpus.dtsi +deleted file mode 100644 +index 412a0bb4b988..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5422-cpus.dtsi ++++ /dev/null +@@ -1,170 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung Exynos5422 SoC cpu device tree source +- * +- * Copyright (c) 2015 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * This file provides desired ordering for Exynos5422: CPU[0123] being the A7. +- * +- * The Exynos5420, 5422 and 5800 actually share the same CPU configuration +- * but particular boards choose different booting order. +- * +- * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422 +- * booting cluster (big or LITTLE) is chosen by IROM code by reading +- * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting +- * from the LITTLE: Cortex-A7. +- */ +- +-/ { +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- core2 { +- cpu = <&cpu2>; +- }; +- core3 { +- cpu = <&cpu3>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&cpu4>; +- }; +- core1 { +- cpu = <&cpu5>; +- }; +- core2 { +- cpu = <&cpu6>; +- }; +- core3 { +- cpu = <&cpu7>; +- }; +- }; +- }; +- +- cpu0: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x100>; +- clocks = <&clock CLK_KFC_CLK>; +- clock-frequency = <1000000000>; +- cci-control-port = <&cci_control0>; +- operating-points-v2 = <&cluster_a7_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- capacity-dmips-mhz = <539>; +- dynamic-power-coefficient = <90>; +- }; +- +- cpu1: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x101>; +- clocks = <&clock CLK_KFC_CLK>; +- clock-frequency = <1000000000>; +- cci-control-port = <&cci_control0>; +- operating-points-v2 = <&cluster_a7_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- capacity-dmips-mhz = <539>; +- dynamic-power-coefficient = <90>; +- }; +- +- cpu2: cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x102>; +- clocks = <&clock CLK_KFC_CLK>; +- clock-frequency = <1000000000>; +- cci-control-port = <&cci_control0>; +- operating-points-v2 = <&cluster_a7_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- capacity-dmips-mhz = <539>; +- dynamic-power-coefficient = <90>; +- }; +- +- cpu3: cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x103>; +- clocks = <&clock CLK_KFC_CLK>; +- clock-frequency = <1000000000>; +- cci-control-port = <&cci_control0>; +- operating-points-v2 = <&cluster_a7_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- capacity-dmips-mhz = <539>; +- dynamic-power-coefficient = <90>; +- }; +- +- cpu4: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x0>; +- clocks = <&clock CLK_ARM_CLK>; +- clock-frequency = <1800000000>; +- cci-control-port = <&cci_control1>; +- operating-points-v2 = <&cluster_a15_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <310>; +- }; +- +- cpu5: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x1>; +- clocks = <&clock CLK_ARM_CLK>; +- clock-frequency = <1800000000>; +- cci-control-port = <&cci_control1>; +- operating-points-v2 = <&cluster_a15_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <310>; +- }; +- +- cpu6: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x2>; +- clocks = <&clock CLK_ARM_CLK>; +- clock-frequency = <1800000000>; +- cci-control-port = <&cci_control1>; +- operating-points-v2 = <&cluster_a15_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <310>; +- }; +- +- cpu7: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x3>; +- clocks = <&clock CLK_ARM_CLK>; +- clock-frequency = <1800000000>; +- cci-control-port = <&cci_control1>; +- operating-points-v2 = <&cluster_a15_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <310>; +- }; +- }; +-}; +- +-&arm_a7_pmu { +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- status = "okay"; +-}; +- +-&arm_a15_pmu { +- interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5422-odroid-core.dtsi b/scripts/dtc/include-prefixes/arm/exynos5422-odroid-core.dtsi +deleted file mode 100644 +index e7958dbecfd2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5422-odroid-core.dtsi ++++ /dev/null +@@ -1,1071 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source +- * +- * Copyright (c) 2017 Marek Szyprowski +- * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-#include +-#include +-#include +-#include "exynos5800.dtsi" +-#include "exynos5422-cpus.dtsi" +- +-/ { +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x7EA00000>; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- firmware@2073000 { +- compatible = "samsung,secure-firmware"; +- reg = <0x02073000 0x1000>; +- }; +- +- fixed-rate-clocks { +- oscclk { +- compatible = "samsung,exynos5420-oscclk"; +- clock-frequency = <24000000>; +- }; +- }; +- +- bus_wcore_opp_table: opp-table2 { +- compatible = "operating-points-v2"; +- +- /* derived from 532MHz MPLL */ +- opp00 { +- opp-hz = /bits/ 64 <88700000>; +- opp-microvolt = <925000 925000 1400000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <133000000>; +- opp-microvolt = <950000 950000 1400000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <177400000>; +- opp-microvolt = <950000 950000 1400000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <266000000>; +- opp-microvolt = <950000 950000 1400000>; +- }; +- opp04 { +- opp-hz = /bits/ 64 <532000000>; +- opp-microvolt = <1000000 1000000 1400000>; +- }; +- }; +- +- bus_noc_opp_table: opp-table3 { +- compatible = "operating-points-v2"; +- +- /* derived from 666MHz CPLL */ +- opp00 { +- opp-hz = /bits/ 64 <66600000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <74000000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <83250000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <111000000>; +- }; +- }; +- +- bus_fsys_apb_opp_table: opp-table4 { +- compatible = "operating-points-v2"; +- +- /* derived from 666MHz CPLL */ +- opp00 { +- opp-hz = /bits/ 64 <111000000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <222000000>; +- }; +- }; +- +- bus_fsys2_opp_table: opp-table5 { +- compatible = "operating-points-v2"; +- +- /* derived from 600MHz DPLL */ +- opp00 { +- opp-hz = /bits/ 64 <75000000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <120000000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <200000000>; +- }; +- }; +- +- bus_mfc_opp_table: opp-table6 { +- compatible = "operating-points-v2"; +- +- /* derived from 666MHz CPLL */ +- opp00 { +- opp-hz = /bits/ 64 <83250000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <111000000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <166500000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <222000000>; +- }; +- opp04 { +- opp-hz = /bits/ 64 <333000000>; +- }; +- }; +- +- bus_gen_opp_table: opp-table7 { +- compatible = "operating-points-v2"; +- +- /* derived from 532MHz MPLL */ +- opp00 { +- opp-hz = /bits/ 64 <88700000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <133000000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <178000000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <266000000>; +- }; +- }; +- +- bus_peri_opp_table: opp-table8 { +- compatible = "operating-points-v2"; +- +- /* derived from 666MHz CPLL */ +- opp00 { +- opp-hz = /bits/ 64 <66600000>; +- }; +- }; +- +- bus_g2d_opp_table: opp-table9 { +- compatible = "operating-points-v2"; +- +- /* derived from 666MHz CPLL */ +- opp00 { +- opp-hz = /bits/ 64 <83250000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <111000000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <166500000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <222000000>; +- }; +- opp04 { +- opp-hz = /bits/ 64 <333000000>; +- }; +- }; +- +- bus_g2d_acp_opp_table: opp-table10 { +- compatible = "operating-points-v2"; +- +- /* derived from 532MHz MPLL */ +- opp00 { +- opp-hz = /bits/ 64 <66500000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <133000000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <178000000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <266000000>; +- }; +- }; +- +- bus_jpeg_opp_table: opp-table11 { +- compatible = "operating-points-v2"; +- +- /* derived from 600MHz DPLL */ +- opp00 { +- opp-hz = /bits/ 64 <75000000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <150000000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <200000000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <300000000>; +- }; +- }; +- +- bus_jpeg_apb_opp_table: opp-table12 { +- compatible = "operating-points-v2"; +- +- /* derived from 666MHz CPLL */ +- opp00 { +- opp-hz = /bits/ 64 <83250000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <111000000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <133000000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <166500000>; +- }; +- }; +- +- bus_disp1_fimd_opp_table: opp-table13 { +- compatible = "operating-points-v2"; +- +- /* derived from 600MHz DPLL */ +- opp00 { +- opp-hz = /bits/ 64 <120000000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <200000000>; +- }; +- }; +- +- bus_disp1_opp_table: opp-table14 { +- compatible = "operating-points-v2"; +- +- /* derived from 600MHz DPLL */ +- opp00 { +- opp-hz = /bits/ 64 <120000000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <200000000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <300000000>; +- }; +- }; +- +- bus_gscl_opp_table: opp-table15 { +- compatible = "operating-points-v2"; +- +- /* derived from 600MHz DPLL */ +- opp00 { +- opp-hz = /bits/ 64 <150000000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <200000000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <300000000>; +- }; +- }; +- +- bus_mscl_opp_table: opp-table16 { +- compatible = "operating-points-v2"; +- +- /* derived from 666MHz CPLL */ +- opp00 { +- opp-hz = /bits/ 64 <84000000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <167000000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <222000000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <333000000>; +- }; +- opp04 { +- opp-hz = /bits/ 64 <666000000>; +- }; +- }; +- +- dmc_opp_table: opp-table17 { +- compatible = "operating-points-v2"; +- +- opp00 { +- opp-hz = /bits/ 64 <165000000>; +- opp-microvolt = <875000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <206000000>; +- opp-microvolt = <875000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <275000000>; +- opp-microvolt = <875000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <413000000>; +- opp-microvolt = <887500>; +- }; +- opp04 { +- opp-hz = /bits/ 64 <543000000>; +- opp-microvolt = <937500>; +- }; +- opp05 { +- opp-hz = /bits/ 64 <633000000>; +- opp-microvolt = <1012500>; +- }; +- opp06 { +- opp-hz = /bits/ 64 <728000000>; +- opp-microvolt = <1037500>; +- }; +- opp07 { +- opp-hz = /bits/ 64 <825000000>; +- opp-microvolt = <1050000>; +- }; +- }; +- +- samsung_K3QF2F20DB: lpddr3 { +- compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; +- density = <16384>; +- io-width = <32>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- tRFC-min-tck = <17>; +- tRRD-min-tck = <2>; +- tRPab-min-tck = <2>; +- tRPpb-min-tck = <2>; +- tRCD-min-tck = <3>; +- tRC-min-tck = <6>; +- tRAS-min-tck = <5>; +- tWTR-min-tck = <2>; +- tWR-min-tck = <7>; +- tRTP-min-tck = <2>; +- tW2W-C2C-min-tck = <0>; +- tR2R-C2C-min-tck = <0>; +- tWL-min-tck = <8>; +- tDQSCK-min-tck = <5>; +- tRL-min-tck = <14>; +- tFAW-min-tck = <5>; +- tXSR-min-tck = <12>; +- tXP-min-tck = <2>; +- tCKE-min-tck = <2>; +- tCKESR-min-tck = <2>; +- tMRD-min-tck = <5>; +- +- timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { +- compatible = "jedec,lpddr3-timings"; +- /* workaround: 'reg' shows max-freq */ +- reg = <800000000>; +- min-freq = <100000000>; +- tRFC = <65000>; +- tRRD = <6000>; +- tRPab = <12000>; +- tRPpb = <12000>; +- tRCD = <10000>; +- tRC = <33750>; +- tRAS = <23000>; +- tWTR = <3750>; +- tWR = <7500>; +- tRTP = <3750>; +- tW2W-C2C = <0>; +- tR2R-C2C = <0>; +- tFAW = <25000>; +- tXSR = <70000>; +- tXP = <3750>; +- tCKE = <3750>; +- tCKESR = <3750>; +- tMRD = <7000>; +- }; +- }; +-}; +- +-&adc { +- vdd-supply = <&ldo4_reg>; +- status = "okay"; +-}; +- +-&bus_wcore { +- operating-points-v2 = <&bus_wcore_opp_table>; +- devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>, +- <&nocp_mem1_0>, <&nocp_mem1_1>; +- vdd-supply = <&buck3_reg>; +- exynos,saturation-ratio = <100>; +- status = "okay"; +-}; +- +-&bus_noc { +- operating-points-v2 = <&bus_noc_opp_table>; +- devfreq = <&bus_wcore>; +- status = "okay"; +-}; +- +-&bus_fsys_apb { +- operating-points-v2 = <&bus_fsys_apb_opp_table>; +- devfreq = <&bus_wcore>; +- status = "okay"; +-}; +- +-&bus_fsys2 { +- operating-points-v2 = <&bus_fsys2_opp_table>; +- devfreq = <&bus_wcore>; +- status = "okay"; +-}; +- +-&bus_mfc { +- operating-points-v2 = <&bus_mfc_opp_table>; +- devfreq = <&bus_wcore>; +- status = "okay"; +-}; +- +-&bus_gen { +- operating-points-v2 = <&bus_gen_opp_table>; +- devfreq = <&bus_wcore>; +- status = "okay"; +-}; +- +-&bus_peri { +- operating-points-v2 = <&bus_peri_opp_table>; +- devfreq = <&bus_wcore>; +- status = "okay"; +-}; +- +-&bus_g2d { +- operating-points-v2 = <&bus_g2d_opp_table>; +- devfreq = <&bus_wcore>; +- status = "okay"; +-}; +- +-&bus_g2d_acp { +- operating-points-v2 = <&bus_g2d_acp_opp_table>; +- devfreq = <&bus_wcore>; +- status = "okay"; +-}; +- +-&bus_jpeg { +- operating-points-v2 = <&bus_jpeg_opp_table>; +- devfreq = <&bus_wcore>; +- status = "okay"; +-}; +- +-&bus_jpeg_apb { +- operating-points-v2 = <&bus_jpeg_apb_opp_table>; +- devfreq = <&bus_wcore>; +- status = "okay"; +-}; +- +-&bus_disp1_fimd { +- operating-points-v2 = <&bus_disp1_fimd_opp_table>; +- devfreq = <&bus_wcore>; +- status = "okay"; +-}; +- +-&bus_disp1 { +- operating-points-v2 = <&bus_disp1_opp_table>; +- devfreq = <&bus_wcore>; +- status = "okay"; +-}; +- +-&bus_gscl_scaler { +- operating-points-v2 = <&bus_gscl_opp_table>; +- devfreq = <&bus_wcore>; +- status = "okay"; +-}; +- +-&bus_mscl { +- operating-points-v2 = <&bus_mscl_opp_table>; +- devfreq = <&bus_wcore>; +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <&buck6_reg>; +-}; +- +-&cpu4 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&dmc { +- devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, +- <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; +- device-handle = <&samsung_K3QF2F20DB>; +- operating-points-v2 = <&dmc_opp_table>; +- vdd-supply = <&buck1_reg>; +- status = "okay"; +-}; +- +-&hsi2c_4 { +- status = "okay"; +- +- pmic@66 { +- compatible = "samsung,s2mps11-pmic"; +- reg = <0x66>; +- samsung,s2mps11-acokb-ground; +- +- interrupt-parent = <&gpx0>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&s2mps11_irq>; +- wakeup-source; +- +- s2mps11_osc: clocks { +- compatible = "samsung,s2mps11-clk"; +- #clock-cells = <1>; +- clock-output-names = "s2mps11_ap", +- "s2mps11_cp", "s2mps11_bt"; +- }; +- +- regulators { +- ldo1_reg: LDO1 { +- regulator-name = "vdd_ldo1"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "vdd_ldo2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "vddq_mmc0"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "vdd_adc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "vdd_ldo5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "vdd_ldo6"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "vdd_ldo7"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "vdd_ldo8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "vdd_ldo9"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "vdd_ldo10"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "vdd_ldo11"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo12_reg: LDO12 { +- /* Unused */ +- regulator-name = "vdd_ldo12"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <2375000>; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "vddq_mmc2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo14_reg: LDO14 { +- /* Unused */ +- regulator-name = "vdd_ldo14"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "vdd_ldo15"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo16_reg: LDO16 { +- /* Unused */ +- regulator-name = "vdd_ldo16"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "vdd_ldo17"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo18_reg: LDO18 { +- regulator-name = "vdd_emmc_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo19_reg: LDO19 { +- regulator-name = "vdd_sd"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo20_reg: LDO20 { +- /* Unused */ +- regulator-name = "vdd_ldo20"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo21_reg: LDO21 { +- /* Unused */ +- regulator-name = "vdd_ldo21"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo22_reg: LDO22 { +- /* Unused */ +- regulator-name = "vdd_ldo22"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <2375000>; +- }; +- +- ldo23_reg: LDO23 { +- regulator-name = "vdd_mifs"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo24_reg: LDO24 { +- /* Unused */ +- regulator-name = "vdd_ldo24"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo25_reg: LDO25 { +- /* Unused */ +- regulator-name = "vdd_ldo25"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo26_reg: LDO26 { +- /* Used on XU3, XU3-Lite and XU4 */ +- regulator-name = "vdd_ldo26"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo27_reg: LDO27 { +- regulator-name = "vdd_g3ds"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo28_reg: LDO28 { +- /* Used on XU3 */ +- regulator-name = "vdd_ldo28"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo29_reg: LDO29 { +- /* Unused */ +- regulator-name = "vdd_ldo29"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo30_reg: LDO30 { +- /* Unused */ +- regulator-name = "vdd_ldo30"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo31_reg: LDO31 { +- /* Unused */ +- regulator-name = "vdd_ldo31"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo32_reg: LDO32 { +- /* Unused */ +- regulator-name = "vdd_ldo32"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo33_reg: LDO33 { +- /* Unused */ +- regulator-name = "vdd_ldo33"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo34_reg: LDO34 { +- /* Unused */ +- regulator-name = "vdd_ldo34"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo35_reg: LDO35 { +- /* Unused */ +- regulator-name = "vdd_ldo35"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <2375000>; +- }; +- +- ldo36_reg: LDO36 { +- /* Unused */ +- regulator-name = "vdd_ldo36"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo37_reg: LDO37 { +- /* Unused */ +- regulator-name = "vdd_ldo37"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- ldo38_reg: LDO38 { +- /* Unused */ +- regulator-name = "vdd_ldo38"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "vdd_mif"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-coupled-with = <&buck3_reg>; +- regulator-coupled-max-spread = <300000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "vdd_int"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-coupled-with = <&buck2_reg>; +- regulator-coupled-max-spread = <300000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "vdd_g3d"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "vdd_mem"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck6_reg: BUCK6 { +- regulator-name = "vdd_kfc"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck7_reg: BUCK7 { +- regulator-name = "vdd_1.35v_ldo"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck8_reg: BUCK8 { +- regulator-name = "vdd_2.0v_ldo"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2100000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- buck9_reg: BUCK9 { +- regulator-name = "vdd_2.8v_ldo"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3750000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck10_reg: BUCK10 { +- regulator-name = "vdd_vmem"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +-}; +- +-&mmc_2 { +- status = "okay"; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <0 4>; +- samsung,dw-mshc-ddr-timing = <0 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>; +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <200000000>; +- vmmc-supply = <&ldo19_reg>; +- vqmmc-supply = <&ldo13_reg>; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- sd-uhs-ddr50; +-}; +- +-&nocp_mem0_0 { +- status = "okay"; +-}; +- +-&nocp_mem0_1 { +- status = "okay"; +-}; +- +-&nocp_mem1_0 { +- status = "okay"; +-}; +- +-&nocp_mem1_1 { +- status = "okay"; +-}; +- +-&pinctrl_0 { +- s2mps11_irq: s2mps11-irq { +- samsung,pins = "gpx0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&ppmu_dmc0_0 { +- status = "okay"; +-}; +- +-&ppmu_dmc0_1 { +- status = "okay"; +-}; +- +-&ppmu_dmc1_0 { +- status = "okay"; +-}; +- +-&ppmu_dmc1_1 { +- status = "okay"; +-}; +- +-&tmu_cpu0 { +- vtmu-supply = <&ldo7_reg>; +-}; +- +-&tmu_cpu1 { +- vtmu-supply = <&ldo7_reg>; +-}; +- +-&tmu_cpu2 { +- vtmu-supply = <&ldo7_reg>; +-}; +- +-&tmu_cpu3 { +- vtmu-supply = <&ldo7_reg>; +-}; +- +-&tmu_gpu { +- vtmu-supply = <&ldo7_reg>; +-}; +- +-&gpu { +- mali-supply = <&buck4_reg>; +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&usbdrd_dwc3_0 { +- dr_mode = "host"; +-}; +- +-/* usbdrd_dwc3_1 mode customized in each board */ +- +-&usbdrd3_0 { +- vdd33-supply = <&ldo9_reg>; +- vdd10-supply = <&ldo11_reg>; +-}; +- +-&usbdrd3_1 { +- vdd33-supply = <&ldo9_reg>; +- vdd10-supply = <&ldo11_reg>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5422-odroidhc1.dts b/scripts/dtc/include-prefixes/arm/exynos5422-odroidhc1.dts +deleted file mode 100644 +index d91f7fa2cf80..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5422-odroidhc1.dts ++++ /dev/null +@@ -1,264 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Hardkernel Odroid HC1 board device tree source +- * +- * Copyright (c) 2017 Marek Szyprowski +- * Copyright (c) 2017 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-/dts-v1/; +-#include "exynos5422-odroid-core.dtsi" +- +-/ { +- model = "Hardkernel Odroid HC1"; +- compatible = "hardkernel,odroid-hc1", "samsung,exynos5800", \ +- "samsung,exynos5"; +- +- led-controller { +- compatible = "pwm-leds"; +- +- led-1 { +- label = "blue:heartbeat"; +- pwms = <&pwm 2 2000000 0>; +- pwm-names = "pwm2"; +- max-brightness = <255>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- thermal-zones { +- cpu0_thermal: cpu0-thermal { +- thermal-sensors = <&tmu_cpu0 0>; +- trips { +- cpu0_alert0: cpu-alert-0 { +- temperature = <70000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "active"; +- }; +- cpu0_alert1: cpu-alert-1 { +- temperature = <85000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "active"; +- }; +- cpu0_crit0: cpu-crit-0 { +- temperature = <120000>; /* millicelsius */ +- hysteresis = <0>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- /* +- * When reaching cpu0_alert0, reduce CPU +- * by 2 steps. On Exynos5422/5800 that would +- * be: 1600 MHz and 1100 MHz. +- */ +- map0 { +- trip = <&cpu0_alert0>; +- cooling-device = <&cpu0 0 2>, +- <&cpu1 0 2>, +- <&cpu2 0 2>, +- <&cpu3 0 2>, +- <&cpu4 0 2>, +- <&cpu5 0 2>, +- <&cpu6 0 2>, +- <&cpu7 0 2>; +- }; +- /* +- * When reaching cpu0_alert1, reduce CPU +- * further, down to 600 MHz (12 steps for big, +- * 7 steps for LITTLE). +- */ +- map1 { +- trip = <&cpu0_alert1>; +- cooling-device = <&cpu0 3 8>, +- <&cpu1 3 8>, +- <&cpu2 3 8>, +- <&cpu3 3 8>, +- <&cpu4 3 14>, +- <&cpu5 3 14>, +- <&cpu6 3 14>, +- <&cpu7 3 14>; +- }; +- }; +- }; +- cpu1_thermal: cpu1-thermal { +- thermal-sensors = <&tmu_cpu1 0>; +- trips { +- cpu1_alert0: cpu-alert-0 { +- temperature = <70000>; +- hysteresis = <10000>; +- type = "active"; +- }; +- cpu1_alert1: cpu-alert-1 { +- temperature = <85000>; +- hysteresis = <10000>; +- type = "active"; +- }; +- cpu1_crit0: cpu-crit-0 { +- temperature = <120000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- cooling-maps { +- map0 { +- trip = <&cpu1_alert0>; +- cooling-device = <&cpu0 0 2>, +- <&cpu1 0 2>, +- <&cpu2 0 2>, +- <&cpu3 0 2>, +- <&cpu4 0 2>, +- <&cpu5 0 2>, +- <&cpu6 0 2>, +- <&cpu7 0 2>; +- }; +- map1 { +- trip = <&cpu1_alert1>; +- cooling-device = <&cpu0 3 8>, +- <&cpu1 3 8>, +- <&cpu2 3 8>, +- <&cpu3 3 8>, +- <&cpu4 3 14>, +- <&cpu5 3 14>, +- <&cpu6 3 14>, +- <&cpu7 3 14>; +- }; +- }; +- }; +- cpu2_thermal: cpu2-thermal { +- thermal-sensors = <&tmu_cpu2 0>; +- trips { +- cpu2_alert0: cpu-alert-0 { +- temperature = <70000>; +- hysteresis = <10000>; +- type = "active"; +- }; +- cpu2_alert1: cpu-alert-1 { +- temperature = <85000>; +- hysteresis = <10000>; +- type = "active"; +- }; +- cpu2_crit0: cpu-crit-0 { +- temperature = <120000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- cooling-maps { +- map0 { +- trip = <&cpu2_alert0>; +- cooling-device = <&cpu0 0 2>, +- <&cpu1 0 2>, +- <&cpu2 0 2>, +- <&cpu3 0 2>, +- <&cpu4 0 2>, +- <&cpu5 0 2>, +- <&cpu6 0 2>, +- <&cpu7 0 2>; +- }; +- map1 { +- trip = <&cpu2_alert1>; +- cooling-device = <&cpu0 3 8>, +- <&cpu1 3 8>, +- <&cpu2 3 8>, +- <&cpu3 3 8>, +- <&cpu4 3 14>, +- <&cpu5 3 14>, +- <&cpu6 3 14>, +- <&cpu7 3 14>; +- }; +- }; +- }; +- cpu3_thermal: cpu3-thermal { +- thermal-sensors = <&tmu_cpu3 0>; +- trips { +- cpu3_alert0: cpu-alert-0 { +- temperature = <70000>; +- hysteresis = <10000>; +- type = "active"; +- }; +- cpu3_alert1: cpu-alert-1 { +- temperature = <85000>; +- hysteresis = <10000>; +- type = "active"; +- }; +- cpu3_crit0: cpu-crit-0 { +- temperature = <120000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- cooling-maps { +- map0 { +- trip = <&cpu3_alert0>; +- cooling-device = <&cpu0 0 2>, +- <&cpu1 0 2>, +- <&cpu2 0 2>, +- <&cpu3 0 2>, +- <&cpu4 0 2>, +- <&cpu5 0 2>, +- <&cpu6 0 2>, +- <&cpu7 0 2>; +- }; +- map1 { +- trip = <&cpu3_alert1>; +- cooling-device = <&cpu0 3 8>, +- <&cpu1 3 8>, +- <&cpu2 3 8>, +- <&cpu3 3 8>, +- <&cpu4 3 14>, +- <&cpu5 3 14>, +- <&cpu6 3 14>, +- <&cpu7 3 14>; +- }; +- }; +- }; +- gpu_thermal: gpu-thermal { +- thermal-sensors = <&tmu_gpu 0>; +- trips { +- gpu_alert0: gpu-alert-0 { +- temperature = <70000>; +- hysteresis = <10000>; +- type = "active"; +- }; +- gpu_alert1: gpu-alert-1 { +- temperature = <85000>; +- hysteresis = <10000>; +- type = "active"; +- }; +- gpu_crit0: gpu-crit-0 { +- temperature = <120000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- cooling-maps { +- map0 { +- trip = <&gpu_alert0>; +- cooling-device = <&gpu 0 2>; +- }; +- map1 { +- trip = <&gpu_alert1>; +- cooling-device = <&gpu 3 6>; +- }; +- }; +- }; +- }; +- +-}; +- +-&pwm { +- /* +- * PWM 2 -- Blue LED +- */ +- pinctrl-0 = <&pwm2_out>; +- pinctrl-names = "default"; +- samsung,pwm-outputs = <2>; +- status = "okay"; +-}; +- +-&usbdrd_dwc3_1 { +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5422-odroidxu3-audio.dtsi b/scripts/dtc/include-prefixes/arm/exynos5422-odroidxu3-audio.dtsi +deleted file mode 100644 +index 86b96f9706db..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5422-odroidxu3-audio.dtsi ++++ /dev/null +@@ -1,83 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Hardkernel Odroid XU3 audio subsystem device tree source +- * +- * Copyright (c) 2015 Krzysztof Kozlowski +- * Copyright (c) 2014 Collabora Ltd. +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-#include +- +-/ { +- sound: sound { +- compatible = "samsung,odroid-xu3-audio"; +- model = "Odroid-XU3"; +- +- samsung,audio-widgets = +- "Headphone", "Headphone Jack", +- "Speakers", "Speakers"; +- samsung,audio-routing = +- "Headphone Jack", "HPL", +- "Headphone Jack", "HPR", +- "Headphone Jack", "MICBIAS", +- "IN12", "Headphone Jack", +- "Speakers", "SPKL", +- "Speakers", "SPKR", +- "I2S Playback", "Mixer DAI TX", +- "HiFi Playback", "Mixer DAI TX", +- "Mixer DAI RX", "HiFi Capture"; +- +- cpu { +- sound-dai = <&i2s0 0>, <&i2s0 1>; +- }; +- codec { +- sound-dai = <&hdmi>, <&max98090>; +- }; +- }; +-}; +- +-&hsi2c_5 { +- status = "okay"; +- max98090: audio-codec@10 { +- compatible = "maxim,max98090"; +- reg = <0x10>; +- interrupt-parent = <&gpx3>; +- interrupts = <2 IRQ_TYPE_NONE>; +- clocks = <&i2s0 CLK_I2S_CDCLK>; +- clock-names = "mclk"; +- #sound-dai-cells = <0>; +- }; +-}; +- +-&i2s0 { +- status = "okay"; +- assigned-clocks = <&clock CLK_MOUT_EPLL>, +- <&clock CLK_MOUT_MAU_EPLL>, +- <&clock CLK_MOUT_USER_MAU_EPLL>, +- <&clock_audss EXYNOS_MOUT_AUDSS>, +- <&clock_audss EXYNOS_MOUT_I2S>, +- <&i2s0 CLK_I2S_RCLK_SRC>, +- <&clock_audss EXYNOS_DOUT_SRP>, +- <&clock_audss EXYNOS_DOUT_AUD_BUS>, +- <&clock_audss EXYNOS_DOUT_I2S>; +- +- assigned-clock-parents = <&clock CLK_FOUT_EPLL>, +- <&clock CLK_MOUT_EPLL>, +- <&clock CLK_MOUT_MAU_EPLL>, +- <&clock CLK_MAU_EPLL>, +- <&clock_audss EXYNOS_MOUT_AUDSS>, +- <&clock_audss EXYNOS_SCLK_I2S>; +- +- assigned-clock-rates = <0>, +- <0>, +- <0>, +- <0>, +- <0>, +- <0>, +- <196608001>, +- <(196608002 / 2)>, +- <196608000>; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5422-odroidxu3-common.dtsi b/scripts/dtc/include-prefixes/arm/exynos5422-odroidxu3-common.dtsi +deleted file mode 100644 +index e35af40a55cb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5422-odroidxu3-common.dtsi ++++ /dev/null +@@ -1,505 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source +- * +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * Copyright (c) 2014 Collabora Ltd. +- * Copyright (c) 2015 Lukasz Majewski +- * Anand Moon +- */ +- +-#include +-#include "exynos5422-odroid-core.dtsi" +- +-/ { +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&power_key>; +- +- power-key { +- /* +- * The power button (SW2) is connected to the PWRON +- * pin (active high) of the S2MPS11 PMIC, which acts +- * as a 16ms debouce filter and signal inverter with +- * output on ONOB pin (active low). ONOB PMIC pin is +- * then connected to XEINT3 SoC pin. +- */ +- gpios = <&gpx0 3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "power key"; +- debounce-interval = <0>; +- wakeup-source; +- }; +- }; +- +- emmc_pwrseq: pwrseq { +- pinctrl-0 = <&emmc_nrst_pin>; +- pinctrl-names = "default"; +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>; +- }; +- +- fan0: pwm-fan { +- compatible = "pwm-fan"; +- pwms = <&pwm 0 20972 0>; +- #cooling-cells = <2>; +- cooling-levels = <0 130 170 230>; +- }; +- +- thermal-zones { +- cpu0_thermal: cpu0-thermal { +- thermal-sensors = <&tmu_cpu0 0>; +- polling-delay-passive = <250>; +- polling-delay = <0>; +- trips { +- cpu0_alert0: cpu-alert-0 { +- temperature = <50000>; /* millicelsius */ +- hysteresis = <5000>; /* millicelsius */ +- type = "active"; +- }; +- cpu0_alert1: cpu-alert-1 { +- temperature = <60000>; /* millicelsius */ +- hysteresis = <5000>; /* millicelsius */ +- type = "active"; +- }; +- cpu0_alert2: cpu-alert-2 { +- temperature = <70000>; /* millicelsius */ +- hysteresis = <5000>; /* millicelsius */ +- type = "active"; +- }; +- cpu0_crit0: cpu-crit-0 { +- temperature = <120000>; /* millicelsius */ +- hysteresis = <0>; /* millicelsius */ +- type = "critical"; +- }; +- /* +- * Exynos542x supports only 4 trip-points +- * so for these polling mode is required. +- * Start polling at temperature level of last +- * interrupt-driven trip: cpu0_alert2 +- */ +- cpu0_alert3: cpu-alert-3 { +- temperature = <70000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu0_alert4: cpu-alert-4 { +- temperature = <85000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "passive"; +- }; +- }; +- cooling-maps { +- map0 { +- trip = <&cpu0_alert0>; +- cooling-device = <&fan0 0 1>; +- }; +- map1 { +- trip = <&cpu0_alert1>; +- cooling-device = <&fan0 1 2>; +- }; +- map2 { +- trip = <&cpu0_alert2>; +- cooling-device = <&fan0 2 3>; +- }; +- /* +- * When reaching cpu0_alert3, reduce CPU +- * by 2 steps. On Exynos5422/5800 that would +- * (usually) be: 1800 MHz and 1200 MHz. +- */ +- map3 { +- trip = <&cpu0_alert3>; +- cooling-device = <&cpu0 0 2>, +- <&cpu1 0 2>, +- <&cpu2 0 2>, +- <&cpu3 0 2>, +- <&cpu4 0 2>, +- <&cpu5 0 2>, +- <&cpu6 0 2>, +- <&cpu7 0 2>; +- }; +- /* +- * When reaching cpu0_alert4, reduce CPU +- * further, down to 600 MHz (14 steps for big, +- * 8 steps for LITTLE). +- */ +- cpu0_cooling_map4: map4 { +- trip = <&cpu0_alert4>; +- cooling-device = <&cpu0 3 8>, +- <&cpu1 3 8>, +- <&cpu2 3 8>, +- <&cpu3 3 8>, +- <&cpu4 3 14>, +- <&cpu5 3 14>, +- <&cpu6 3 14>, +- <&cpu7 3 14>; +- }; +- }; +- }; +- cpu1_thermal: cpu1-thermal { +- thermal-sensors = <&tmu_cpu1 0>; +- polling-delay-passive = <250>; +- polling-delay = <0>; +- trips { +- cpu1_alert0: cpu-alert-0 { +- temperature = <50000>; +- hysteresis = <5000>; +- type = "active"; +- }; +- cpu1_alert1: cpu-alert-1 { +- temperature = <60000>; +- hysteresis = <5000>; +- type = "active"; +- }; +- cpu1_alert2: cpu-alert-2 { +- temperature = <70000>; +- hysteresis = <5000>; +- type = "active"; +- }; +- cpu1_crit0: cpu-crit-0 { +- temperature = <120000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- cpu1_alert3: cpu-alert-3 { +- temperature = <70000>; +- hysteresis = <10000>; +- type = "passive"; +- }; +- cpu1_alert4: cpu-alert-4 { +- temperature = <85000>; +- hysteresis = <10000>; +- type = "passive"; +- }; +- }; +- cooling-maps { +- map0 { +- trip = <&cpu1_alert0>; +- cooling-device = <&fan0 0 1>; +- }; +- map1 { +- trip = <&cpu1_alert1>; +- cooling-device = <&fan0 1 2>; +- }; +- map2 { +- trip = <&cpu1_alert2>; +- cooling-device = <&fan0 2 3>; +- }; +- map3 { +- trip = <&cpu1_alert3>; +- cooling-device = <&cpu0 0 2>, +- <&cpu1 0 2>, +- <&cpu2 0 2>, +- <&cpu3 0 2>, +- <&cpu4 0 2>, +- <&cpu5 0 2>, +- <&cpu6 0 2>, +- <&cpu7 0 2>; +- }; +- cpu1_cooling_map4: map4 { +- trip = <&cpu1_alert4>; +- cooling-device = <&cpu0 3 8>, +- <&cpu1 3 8>, +- <&cpu2 3 8>, +- <&cpu3 3 8>, +- <&cpu4 3 14>, +- <&cpu5 3 14>, +- <&cpu6 3 14>, +- <&cpu7 3 14>; +- }; +- }; +- }; +- cpu2_thermal: cpu2-thermal { +- thermal-sensors = <&tmu_cpu2 0>; +- polling-delay-passive = <250>; +- polling-delay = <0>; +- trips { +- cpu2_alert0: cpu-alert-0 { +- temperature = <50000>; +- hysteresis = <5000>; +- type = "active"; +- }; +- cpu2_alert1: cpu-alert-1 { +- temperature = <60000>; +- hysteresis = <5000>; +- type = "active"; +- }; +- cpu2_alert2: cpu-alert-2 { +- temperature = <70000>; +- hysteresis = <5000>; +- type = "active"; +- }; +- cpu2_crit0: cpu-crit-0 { +- temperature = <120000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- cpu2_alert3: cpu-alert-3 { +- temperature = <70000>; +- hysteresis = <10000>; +- type = "passive"; +- }; +- cpu2_alert4: cpu-alert-4 { +- temperature = <85000>; +- hysteresis = <10000>; +- type = "passive"; +- }; +- }; +- cooling-maps { +- map0 { +- trip = <&cpu2_alert0>; +- cooling-device = <&fan0 0 1>; +- }; +- map1 { +- trip = <&cpu2_alert1>; +- cooling-device = <&fan0 1 2>; +- }; +- map2 { +- trip = <&cpu2_alert2>; +- cooling-device = <&fan0 2 3>; +- }; +- map3 { +- trip = <&cpu2_alert3>; +- cooling-device = <&cpu0 0 2>, +- <&cpu1 0 2>, +- <&cpu2 0 2>, +- <&cpu3 0 2>, +- <&cpu4 0 2>, +- <&cpu5 0 2>, +- <&cpu6 0 2>, +- <&cpu7 0 2>; +- }; +- cpu2_cooling_map4: map4 { +- trip = <&cpu2_alert4>; +- cooling-device = <&cpu0 3 8>, +- <&cpu1 3 8>, +- <&cpu2 3 8>, +- <&cpu3 3 8>, +- <&cpu4 3 14>, +- <&cpu5 3 14>, +- <&cpu6 3 14>, +- <&cpu7 3 14>; +- }; +- }; +- }; +- cpu3_thermal: cpu3-thermal { +- thermal-sensors = <&tmu_cpu3 0>; +- polling-delay-passive = <250>; +- polling-delay = <0>; +- trips { +- cpu3_alert0: cpu-alert-0 { +- temperature = <50000>; +- hysteresis = <5000>; +- type = "active"; +- }; +- cpu3_alert1: cpu-alert-1 { +- temperature = <60000>; +- hysteresis = <5000>; +- type = "active"; +- }; +- cpu3_alert2: cpu-alert-2 { +- temperature = <70000>; +- hysteresis = <5000>; +- type = "active"; +- }; +- cpu3_crit0: cpu-crit-0 { +- temperature = <120000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- cpu3_alert3: cpu-alert-3 { +- temperature = <70000>; +- hysteresis = <10000>; +- type = "passive"; +- }; +- cpu3_alert4: cpu-alert-4 { +- temperature = <85000>; +- hysteresis = <10000>; +- type = "passive"; +- }; +- }; +- cooling-maps { +- map0 { +- trip = <&cpu3_alert0>; +- cooling-device = <&fan0 0 1>; +- }; +- map1 { +- trip = <&cpu3_alert1>; +- cooling-device = <&fan0 1 2>; +- }; +- map2 { +- trip = <&cpu3_alert2>; +- cooling-device = <&fan0 2 3>; +- }; +- map3 { +- trip = <&cpu3_alert3>; +- cooling-device = <&cpu0 0 2>, +- <&cpu1 0 2>, +- <&cpu2 0 2>, +- <&cpu3 0 2>, +- <&cpu4 0 2>, +- <&cpu5 0 2>, +- <&cpu6 0 2>, +- <&cpu7 0 2>; +- }; +- cpu3_cooling_map4: map4 { +- trip = <&cpu3_alert4>; +- cooling-device = <&cpu0 3 8>, +- <&cpu1 3 8>, +- <&cpu2 3 8>, +- <&cpu3 3 8>, +- <&cpu4 3 14>, +- <&cpu5 3 14>, +- <&cpu6 3 14>, +- <&cpu7 3 14>; +- }; +- }; +- }; +- gpu_thermal: gpu-thermal { +- thermal-sensors = <&tmu_gpu 0>; +- polling-delay-passive = <250>; +- polling-delay = <0>; +- trips { +- gpu_alert0: gpu-alert-0 { +- temperature = <50000>; +- hysteresis = <5000>; +- type = "active"; +- }; +- gpu_alert1: gpu-alert-1 { +- temperature = <60000>; +- hysteresis = <5000>; +- type = "active"; +- }; +- gpu_alert2: gpu-alert-2 { +- temperature = <70000>; +- hysteresis = <5000>; +- type = "active"; +- }; +- gpu_crit0: gpu-crit-0 { +- temperature = <120000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- gpu_alert3: gpu-alert-3 { +- temperature = <70000>; +- hysteresis = <10000>; +- type = "passive"; +- }; +- gpu_alert4: gpu-alert-4 { +- temperature = <85000>; +- hysteresis = <10000>; +- type = "passive"; +- }; +- }; +- cooling-maps { +- map0 { +- trip = <&gpu_alert0>; +- cooling-device = <&fan0 0 1>; +- }; +- map1 { +- trip = <&gpu_alert1>; +- cooling-device = <&fan0 1 2>; +- }; +- map2 { +- trip = <&gpu_alert2>; +- cooling-device = <&fan0 2 3>; +- }; +- map3 { +- trip = <&gpu_alert3>; +- cooling-device = <&gpu 0 2>; +- }; +- map4 { +- trip = <&gpu_alert4>; +- cooling-device = <&gpu 3 6>; +- }; +- }; +- }; +- }; +-}; +- +-&buck10_reg { +- /* Supplies vmmc-supply of mmc_0 */ +- regulator-always-on; +- regulator-boot-on; +-}; +- +-&hdmi { +- status = "okay"; +- ddc = <&i2c_2>; +- hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_hpd_irq>; +- +- vdd_osc-supply = <&ldo7_reg>; +- vdd_pll-supply = <&ldo6_reg>; +- vdd-supply = <&ldo6_reg>; +-}; +- +-&hdmicec { +- status = "okay"; +- needs-hpd; +-}; +- +-&i2c_2 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <66000>; +- /* used by HDMI DDC */ +- status = "okay"; +-}; +- +-&ldo26_reg { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +-}; +- +-&mixer { +- status = "okay"; +-}; +- +-&mmc_0 { +- status = "okay"; +- mmc-pwrseq = <&emmc_pwrseq>; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <0 4>; +- samsung,dw-mshc-ddr-timing = <0 2>; +- samsung,dw-mshc-hs400-timing = <0 2>; +- samsung,read-strobe-delay = <90>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>; +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- max-frequency = <200000000>; +- vmmc-supply = <&ldo18_reg>; +- vqmmc-supply = <&ldo3_reg>; +-}; +- +-&pinctrl_0 { +- power_key: power-key { +- samsung,pins = "gpx0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hdmi_hpd_irq: hdmi-hpd-irq { +- samsung,pins = "gpx3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_1 { +- emmc_nrst_pin: emmc-nrst { +- samsung,pins = "gpd1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5422-odroidxu3-lite.dts b/scripts/dtc/include-prefixes/arm/exynos5422-odroidxu3-lite.dts +deleted file mode 100644 +index 62c5928aa994..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5422-odroidxu3-lite.dts ++++ /dev/null +@@ -1,127 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Hardkernel Odroid XU3-Lite board device tree source +- * +- * Copyright (c) 2015 Krzysztof Kozlowski +- * Copyright (c) 2014 Collabora Ltd. +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-/dts-v1/; +-#include "exynos5422-odroidxu3-common.dtsi" +-#include "exynos5422-odroidxu3-audio.dtsi" +-#include "exynos54xx-odroidxu-leds.dtsi" +- +-/ { +- model = "Hardkernel Odroid XU3 Lite"; +- compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5"; +- +- aliases { +- ethernet = ðernet; +- }; +-}; +- +-&arm_a7_pmu { +- status = "disabled"; +-}; +- +-&arm_a15_pmu { +- status = "disabled"; +-}; +- +-&chipid { +- samsung,asv-bin = <2>; +-}; +- +-/* +- * Odroid XU3-Lite board uses SoC revision with lower maximum frequencies +- * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores. +- * Therefore we need to update OPPs tables and thermal maps accordingly. +- */ +-&cluster_a15_opp_table { +- /delete-node/opp-2000000000; +- /delete-node/opp-1900000000; +-}; +- +-&cluster_a7_opp_table { +- /delete-node/opp-1400000000; +-}; +- +-&cpu0_cooling_map4 { +- cooling-device = <&cpu0 3 7>, +- <&cpu1 3 7>, +- <&cpu2 3 7>, +- <&cpu3 3 7>, +- <&cpu4 3 12>, +- <&cpu5 3 12>, +- <&cpu6 3 12>, +- <&cpu7 3 12>; +-}; +- +-&cpu1_cooling_map4 { +- cooling-device = <&cpu0 3 7>, +- <&cpu1 3 7>, +- <&cpu2 3 7>, +- <&cpu3 3 7>, +- <&cpu4 3 12>, +- <&cpu5 3 12>, +- <&cpu6 3 12>, +- <&cpu7 3 12>; +-}; +- +-&cpu2_cooling_map4 { +- cooling-device = <&cpu0 3 7>, +- <&cpu1 3 7>, +- <&cpu2 3 7>, +- <&cpu3 3 7>, +- <&cpu4 3 12>, +- <&cpu5 3 12>, +- <&cpu6 3 12>, +- <&cpu7 3 12>; +-}; +- +-&cpu3_cooling_map4 { +- cooling-device = <&cpu0 3 7>, +- <&cpu1 3 7>, +- <&cpu2 3 7>, +- <&cpu3 3 7>, +- <&cpu4 3 12>, +- <&cpu5 3 12>, +- <&cpu6 3 12>, +- <&cpu7 3 12>; +-}; +- +-&pwm { +- /* +- * PWM 0 -- fan +- * PWM 1 -- Green LED +- * PWM 2 -- Blue LED +- * PWM 3 -- on MIPI connector for backlight +- */ +- pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&usbdrd_dwc3_1 { +- dr_mode = "peripheral"; +-}; +- +-&usbhost2 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- hub@1 { +- compatible = "usb0424,9514"; +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethernet: usbether@1 { +- compatible = "usb0424,ec00"; +- reg = <1>; +- local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5422-odroidxu3.dts b/scripts/dtc/include-prefixes/arm/exynos5422-odroidxu3.dts +deleted file mode 100644 +index cecaeb69e623..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5422-odroidxu3.dts ++++ /dev/null +@@ -1,94 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Hardkernel Odroid XU3 board device tree source +- * +- * Copyright (c) 2014 Collabora Ltd. +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-/dts-v1/; +-#include "exynos5422-odroidxu3-common.dtsi" +-#include "exynos5422-odroidxu3-audio.dtsi" +-#include "exynos54xx-odroidxu-leds.dtsi" +- +-/ { +- model = "Hardkernel Odroid XU3"; +- compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5"; +- +- aliases { +- ethernet = ðernet; +- }; +-}; +- +-&i2c_0 { +- status = "okay"; +- +- /* A15 cluster: VDD_ARM */ +- power-sensor@40 { +- compatible = "ti,ina231"; +- reg = <0x40>; +- shunt-resistor = <10000>; +- }; +- +- /* memory: VDD_MEM */ +- power-sensor@41 { +- compatible = "ti,ina231"; +- reg = <0x41>; +- shunt-resistor = <10000>; +- }; +- +- /* GPU: VDD_G3D */ +- power-sensor@44 { +- compatible = "ti,ina231"; +- reg = <0x44>; +- shunt-resistor = <10000>; +- }; +- +- /* A7 cluster: VDD_KFC */ +- power-sensor@45 { +- compatible = "ti,ina231"; +- reg = <0x45>; +- shunt-resistor = <10000>; +- }; +-}; +- +-&ldo28_reg { +- regulator-name = "dp_p3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +-}; +- +-&pwm { +- /* +- * PWM 0 -- fan +- * PWM 1 -- Green LED +- * PWM 2 -- Blue LED +- * PWM 3 -- on MIPI connector for backlight +- */ +- pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&usbdrd_dwc3_1 { +- dr_mode = "peripheral"; +-}; +- +-&usbhost2 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- hub@1 { +- compatible = "usb0424,9514"; +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethernet: usbether@1 { +- compatible = "usb0424,ec00"; +- reg = <1>; +- local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5422-odroidxu4.dts b/scripts/dtc/include-prefixes/arm/exynos5422-odroidxu4.dts +deleted file mode 100644 +index 1c24f9b35973..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5422-odroidxu4.dts ++++ /dev/null +@@ -1,92 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Hardkernel Odroid XU4 board device tree source +- * +- * Copyright (c) 2015 Krzysztof Kozlowski +- * Copyright (c) 2014 Collabora Ltd. +- * Copyright (c) 2013-2015 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-/dts-v1/; +-#include +-#include "exynos5422-odroidxu3-common.dtsi" +- +-/ { +- model = "Hardkernel Odroid XU4"; +- compatible = "hardkernel,odroid-xu4", "samsung,exynos5800", \ +- "samsung,exynos5"; +- +- led-controller { +- compatible = "pwm-leds"; +- +- led-1 { +- label = "blue:heartbeat"; +- pwms = <&pwm 2 2000000 0>; +- pwm-names = "pwm2"; +- max-brightness = <255>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- sound: sound { +- compatible = "samsung,odroid-xu3-audio"; +- model = "Odroid-XU4"; +- +- samsung,audio-routing = "I2S Playback", "Mixer DAI TX"; +- +- cpu { +- sound-dai = <&i2s0 0>, <&i2s0 1>; +- }; +- +- codec { +- sound-dai = <&hdmi>; +- }; +- }; +-}; +- +-&i2s0 { +- status = "okay"; +- +- assigned-clocks = <&clock CLK_MOUT_EPLL>, +- <&clock CLK_MOUT_MAU_EPLL>, +- <&clock CLK_MOUT_USER_MAU_EPLL>, +- <&clock_audss EXYNOS_MOUT_AUDSS>, +- <&clock_audss EXYNOS_MOUT_I2S>, +- <&i2s0 CLK_I2S_RCLK_SRC>, +- <&clock_audss EXYNOS_DOUT_SRP>, +- <&clock_audss EXYNOS_DOUT_AUD_BUS>, +- <&clock_audss EXYNOS_DOUT_I2S>; +- +- assigned-clock-parents = <&clock CLK_FOUT_EPLL>, +- <&clock CLK_MOUT_EPLL>, +- <&clock CLK_MOUT_MAU_EPLL>, +- <&clock CLK_MAU_EPLL>, +- <&clock_audss EXYNOS_MOUT_AUDSS>, +- <&clock_audss EXYNOS_SCLK_I2S>; +- +- assigned-clock-rates = <0>, +- <0>, +- <0>, +- <0>, +- <0>, +- <0>, +- <196608001>, +- <(196608002 / 2)>, +- <196608000>; +-}; +- +-&pwm { +- /* +- * PWM 0 -- fan +- * PWM 2 -- Blue LED +- */ +- pinctrl-0 = <&pwm0_out &pwm2_out>; +- pinctrl-names = "default"; +- samsung,pwm-outputs = <0>, <2>; +- status = "okay"; +-}; +- +-&usbdrd_dwc3_1 { +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos54xx-odroidxu-leds.dtsi b/scripts/dtc/include-prefixes/arm/exynos54xx-odroidxu-leds.dtsi +deleted file mode 100644 +index 982752e1df24..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos54xx-odroidxu-leds.dtsi ++++ /dev/null +@@ -1,48 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Hardkernel Odroid XU/XU3 LED device tree source +- * +- * Copyright (c) 2015,2016 Krzysztof Kozlowski +- * Copyright (c) 2014 Collabora Ltd. +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-#include +- +-/ { +- led-controller-1 { +- compatible = "pwm-leds"; +- +- led-1 { +- label = "green:mmc0"; +- pwms = <&pwm 1 2000000 0>; +- pwm-names = "pwm1"; +- /* +- * Green LED is much brighter than the others +- * so limit its max brightness +- */ +- max-brightness = <127>; +- linux,default-trigger = "mmc0"; +- }; +- +- led-2 { +- label = "blue:heartbeat"; +- pwms = <&pwm 2 2000000 0>; +- pwm-names = "pwm2"; +- max-brightness = <255>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- led-controller-2 { +- compatible = "gpio-leds"; +- +- led-3 { +- label = "red:microSD"; +- gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "mmc1"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos54xx.dtsi b/scripts/dtc/include-prefixes/arm/exynos54xx.dtsi +deleted file mode 100644 +index 2ddb7a5f12b3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos54xx.dtsi ++++ /dev/null +@@ -1,209 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos54xx SoC series common device tree source +- * +- * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * Copyright (c) 2016 Krzysztof Kozlowski +- * +- * Device nodes common for Samsung Exynos5410/5420/5422/5800. Specific +- * Exynos 54xx SoCs should include this file and customize it further +- * (e.g. with clocks). +- */ +- +-#include "exynos5.dtsi" +- +-/ { +- compatible = "samsung,exynos5"; +- +- aliases { +- i2c4 = &hsi2c_4; +- i2c5 = &hsi2c_5; +- i2c6 = &hsi2c_6; +- i2c7 = &hsi2c_7; +- usbdrdphy0 = &usbdrd_phy0; +- usbdrdphy1 = &usbdrd_phy1; +- }; +- +- arm_a7_pmu: arm-a7-pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- status = "disabled"; +- }; +- +- arm_a15_pmu: arm-a15-pmu { +- compatible = "arm,cortex-a15-pmu"; +- interrupt-parent = <&combiner>; +- interrupts = <1 2>, +- <7 0>, +- <16 6>, +- <19 2>; +- status = "disabled"; +- }; +- +- timer: timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- clock-frequency = <24000000>; +- }; +- +- soc: soc { +- sram@2020000 { +- compatible = "mmio-sram"; +- reg = <0x02020000 0x54000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x02020000 0x54000>; +- +- smp-sram@0 { +- compatible = "samsung,exynos4210-sysram"; +- reg = <0x0 0x1000>; +- }; +- +- smp-sram@53000 { +- compatible = "samsung,exynos4210-sysram-ns"; +- reg = <0x53000 0x1000>; +- }; +- }; +- +- mct: timer@101c0000 { +- compatible = "samsung,exynos4210-mct"; +- reg = <0x101c0000 0xb00>; +- interrupts-extended = <&combiner 23 3>, +- <&combiner 23 4>, +- <&combiner 25 2>, +- <&combiner 25 3>, +- <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- watchdog: watchdog@101d0000 { +- compatible = "samsung,exynos5420-wdt"; +- reg = <0x101d0000 0x100>; +- interrupts = ; +- }; +- +- adc: adc@12d10000 { +- compatible = "samsung,exynos-adc-v2"; +- reg = <0x12d10000 0x100>; +- interrupts = ; +- #io-channel-cells = <1>; +- status = "disabled"; +- }; +- +- /* i2c_0-3 are defined in exynos5.dtsi */ +- hsi2c_4: i2c@12ca0000 { +- compatible = "samsung,exynos5250-hsi2c"; +- reg = <0x12ca0000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- hsi2c_5: i2c@12cb0000 { +- compatible = "samsung,exynos5250-hsi2c"; +- reg = <0x12cb0000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- hsi2c_6: i2c@12cc0000 { +- compatible = "samsung,exynos5250-hsi2c"; +- reg = <0x12cc0000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- hsi2c_7: i2c@12cd0000 { +- compatible = "samsung,exynos5250-hsi2c"; +- reg = <0x12cd0000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- usbdrd3_0: usb3-0 { +- compatible = "samsung,exynos5250-dwusb3"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- usbdrd_dwc3_0: usb@12000000 { +- compatible = "snps,dwc3"; +- reg = <0x12000000 0x10000>; +- interrupts = ; +- phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; +- phy-names = "usb2-phy", "usb3-phy"; +- snps,dis_u3_susphy_quirk; +- }; +- }; +- +- usbdrd_phy0: phy@12100000 { +- compatible = "samsung,exynos5420-usbdrd-phy"; +- reg = <0x12100000 0x100>; +- #phy-cells = <1>; +- }; +- +- usbdrd3_1: usb3-1 { +- compatible = "samsung,exynos5250-dwusb3"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- usbdrd_dwc3_1: usb@12400000 { +- compatible = "snps,dwc3"; +- reg = <0x12400000 0x10000>; +- phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; +- phy-names = "usb2-phy", "usb3-phy"; +- snps,dis_u3_susphy_quirk; +- }; +- }; +- +- usbdrd_phy1: phy@12500000 { +- compatible = "samsung,exynos5420-usbdrd-phy"; +- reg = <0x12500000 0x100>; +- #phy-cells = <1>; +- }; +- +- usbhost2: usb@12110000 { +- compatible = "samsung,exynos4210-ehci"; +- reg = <0x12110000 0x100>; +- interrupts = ; +- phys = <&usb2_phy 0>; +- phy-names = "host"; +- }; +- +- usbhost1: usb@12120000 { +- compatible = "samsung,exynos4210-ohci"; +- reg = <0x12120000 0x100>; +- interrupts = ; +- phys = <&usb2_phy 0>; +- phy-names = "host"; +- }; +- +- usb2_phy: phy@12130000 { +- compatible = "samsung,exynos5420-usb2-phy"; +- reg = <0x12130000 0x100>; +- #phy-cells = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/exynos5800-peach-pi.dts b/scripts/dtc/include-prefixes/arm/exynos5800-peach-pi.dts +deleted file mode 100644 +index 0ce3443d39a8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5800-peach-pi.dts ++++ /dev/null +@@ -1,1100 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Google Peach Pi Rev 10+ board device tree source +- * +- * Copyright (c) 2014 Google, Inc +- */ +- +-/dts-v1/; +-#include +-#include +-#include +-#include +-#include +-#include +-#include "exynos5800.dtsi" +-#include "exynos5420-cpus.dtsi" +- +-/ { +- model = "Google Peach Pi Rev 10+"; +- +- compatible = "google,pi-rev16", +- "google,pi-rev15", "google,pi-rev14", +- "google,pi-rev13", "google,pi-rev12", +- "google,pi-rev11", "google,pi-rev10", +- "google,pi", "google,peach", "samsung,exynos5800", +- "samsung,exynos5"; +- +- aliases { +- /* Assign 20 so we don't get confused w/ builtin ones */ +- i2c20 = &i2c_tunnel; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 1000000 0>; +- brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; +- default-brightness-level = <7>; +- enable-gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; +- power-supply = <&tps65090_fet1>; +- pinctrl-0 = <&pwm0_out>; +- pinctrl-names = "default"; +- }; +- +- chosen { +- stdout-path = "serial3:115200n8"; +- }; +- +- fixed-rate-clocks { +- oscclk { +- compatible = "samsung,exynos5420-oscclk"; +- clock-frequency = <24000000>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&power_key_irq &lid_irq>; +- +- power { +- label = "Power"; +- gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- lid-switch { +- label = "Lid"; +- gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; +- linux,input-type = <5>; /* EV_SW */ +- linux,code = <0>; /* SW_LID */ +- debounce-interval = <1>; +- wakeup-source; +- }; +- +- }; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x80000000>; +- }; +- +- sound { +- compatible = "google,snow-audio-max98091"; +- +- samsung,model = "Peach-Pi-I2S-MAX98091"; +- samsung,i2s-controller = <&i2s0>; +- samsung,audio-codec = <&max98091>; +- +- cpu { +- sound-dai = <&i2s0 0>; +- }; +- +- codec { +- sound-dai = <&max98091>, <&hdmi>; +- }; +- }; +- +- usb300_vbus_reg: regulator-usb300 { +- compatible = "regulator-fixed"; +- regulator-name = "P5.0V_USB3CON0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gph0 0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb300_vbus_en>; +- enable-active-high; +- }; +- +- usb301_vbus_reg: regulator-usb301 { +- compatible = "regulator-fixed"; +- regulator-name = "P5.0V_USB3CON1"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gph0 1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb301_vbus_en>; +- enable-active-high; +- }; +- +- vbat: fixed-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vbat-supply"; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- panel: panel { +- compatible = "auo,b133htn01"; +- power-supply = <&tps65090_fet6>; +- backlight = <&backlight>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&dp_out>; +- }; +- }; +- }; +- +- mmc1_pwrseq: mmc1-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */ +- clocks = <&max77802 MAX77802_CLK_32K_CP>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&adc { +- status = "okay"; +- vdd-supply = <&ldo9_reg>; +-}; +- +-&clock_audss { +- assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; +- assigned-clock-parents = <&clock CLK_MAU_EPLL>; +-}; +- +-/* +- * Peach Pi board uses SoC revision with lower maximum frequency for A7 cores +- * (1.3 GHz instead of 1.4 GHz) than Odroid XU3/XU4 boards. Thus we need to +- * update A7 OPPs table accordingly. +- */ +-&cluster_a7_opp_table { +- /delete-node/opp-1400000000; +-}; +- +-&cpu0 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&cpu4 { +- cpu-supply = <&buck6_reg>; +-}; +- +-&dp { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dp_hpd_gpio>; +- samsung,color-space = <0>; +- samsung,color-depth = <1>; +- samsung,link-rate = <0x0a>; +- samsung,lane-count = <2>; +- samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; +- +- ports { +- port { +- dp_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&fimd { +- status = "okay"; +- samsung,invert-vclk; +-}; +- +-&hdmi { +- status = "okay"; +- hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_hpd_irq>; +- ddc = <&i2c_2>; +- +- hdmi-en-supply = <&tps65090_fet7>; +- vdd-supply = <&ldo8_reg>; +- vdd_osc-supply = <&ldo10_reg>; +- vdd_pll-supply = <&ldo8_reg>; +-}; +- +-&hsi2c_4 { +- status = "okay"; +- clock-frequency = <400000>; +- +- max77802: pmic@9 { +- compatible = "maxim,max77802"; +- interrupt-parent = <&gpx3>; +- interrupts = <1 IRQ_TYPE_NONE>; +- pinctrl-names = "default"; +- pinctrl-0 = <&max77802_irq>, <&pmic_selb>, +- <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>; +- wakeup-source; +- reg = <0x9>; +- #clock-cells = <1>; +- +- inb1-supply = <&tps65090_dcdc2>; +- inb2-supply = <&tps65090_dcdc1>; +- inb3-supply = <&tps65090_dcdc2>; +- inb4-supply = <&tps65090_dcdc2>; +- inb5-supply = <&tps65090_dcdc1>; +- inb6-supply = <&tps65090_dcdc2>; +- inb7-supply = <&tps65090_dcdc1>; +- inb8-supply = <&tps65090_dcdc1>; +- inb9-supply = <&tps65090_dcdc1>; +- inb10-supply = <&tps65090_dcdc1>; +- +- inl1-supply = <&buck5_reg>; +- inl2-supply = <&buck7_reg>; +- inl3-supply = <&buck9_reg>; +- inl4-supply = <&buck9_reg>; +- inl5-supply = <&buck9_reg>; +- inl6-supply = <&tps65090_dcdc2>; +- inl7-supply = <&buck9_reg>; +- inl9-supply = <&tps65090_dcdc2>; +- inl10-supply = <&buck7_reg>; +- +- regulators { +- buck1_reg: BUCK1 { +- regulator-name = "vdd_mif"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-ramp-delay = <12500>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-ramp-delay = <12500>; +- regulator-coupled-with = <&buck3_reg>; +- regulator-coupled-max-spread = <300000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "vdd_int"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-ramp-delay = <12500>; +- regulator-coupled-with = <&buck2_reg>; +- regulator-coupled-max-spread = <300000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "vdd_g3d"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-ramp-delay = <12500>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "vdd_1v2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck6_reg: BUCK6 { +- regulator-name = "vdd_kfc"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-ramp-delay = <12500>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck7_reg: BUCK7 { +- regulator-name = "vdd_1v35"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- buck8_reg: BUCK8 { +- regulator-name = "vdd_emmc"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck9_reg: BUCK9 { +- regulator-name = "vdd_2v"; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- buck10_reg: BUCK10 { +- regulator-name = "vdd_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo1_reg: LDO1 { +- regulator-name = "vdd_1v0"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-mode = ; +- }; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "vdd_1v2_2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "vdd_1v8_3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-mode = ; +- }; +- }; +- +- vqmmc_sdcard: ldo4_reg: LDO4 { +- regulator-name = "vdd_sd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "vdd_1v8_5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "vdd_1v8_6"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "vdd_1v8_7"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "vdd_ldo8"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "vdd_ldo9"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-mode = ; +- }; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "vdd_ldo10"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "vdd_ldo11"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-mode = ; +- }; +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "vdd_ldo12"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "vdd_ldo13"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-mode = ; +- }; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "vdd_ldo14"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "vdd_ldo15"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "vdd_g3ds"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo18_reg: LDO18 { +- regulator-name = "ldo_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo19_reg: LDO19 { +- regulator-name = "ldo_19"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo20_reg: LDO20 { +- regulator-name = "ldo_20"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo21_reg: LDO21 { +- regulator-name = "ldo_21"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo23_reg: LDO23 { +- regulator-name = "ldo_23"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- ldo24_reg: LDO24 { +- regulator-name = "ldo_24"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo25_reg: LDO25 { +- regulator-name = "ldo_25"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo26_reg: LDO26 { +- regulator-name = "ldo_26"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo27_reg: LDO27 { +- regulator-name = "ldo_27"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo28_reg: LDO28 { +- regulator-name = "ldo_28"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo29_reg: LDO29 { +- regulator-name = "ldo_29"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo30_reg: LDO30 { +- regulator-name = "vdd_mifs"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo32_reg: LDO32 { +- regulator-name = "ldo_32"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- ldo33_reg: LDO33 { +- regulator-name = "ldo_33"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo34_reg: LDO34 { +- regulator-name = "ldo_34"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- ldo35_reg: LDO35 { +- regulator-name = "ldo_35"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- }; +- }; +-}; +- +-&hsi2c_7 { +- status = "okay"; +- clock-frequency = <400000>; +- +- max98091: codec@10 { +- compatible = "maxim,max98091"; +- reg = <0x10>; +- interrupts = <2 IRQ_TYPE_NONE>; +- interrupt-parent = <&gpx0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&max98091_irq>; +- clocks = <&pmu_system_controller 0>; +- clock-names = "mclk"; +- #sound-dai-cells = <0>; +- }; +- +- light-sensor@44 { +- compatible = "isil,isl29018"; +- reg = <0x44>; +- vcc-supply = <&tps65090_fet5>; +- }; +-}; +- +-&hsi2c_8 { +- status = "okay"; +- clock-frequency = <333000>; +- /* Atmel mXT540S */ +- trackpad@4b { +- compatible = "atmel,maxtouch"; +- reg = <0x4b>; +- interrupt-parent = <&gpx1>; +- interrupts = <1 IRQ_TYPE_EDGE_FALLING>; +- wakeup-source; +- pinctrl-names = "default"; +- pinctrl-0 = <&trackpad_irq>; +- linux,gpio-keymap = ; /* GPIO 3 */ +- }; +-}; +- +-&hsi2c_9 { +- status = "okay"; +- clock-frequency = <400000>; +- +- tpm@20 { +- compatible = "infineon,slb9645tt"; +- reg = <0x20>; +- +- /* Unused irq; but still need to configure the pins */ +- pinctrl-names = "default"; +- pinctrl-0 = <&tpm_irq>; +- }; +-}; +- +-&i2c_2 { +- status = "okay"; +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <66000>; +- samsung,i2c-slave-addr = <0x50>; +-}; +- +-&i2s0 { +- assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; +- assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>; +- status = "okay"; +-}; +- +-&mixer { +- status = "okay"; +-}; +- +-/* eMMC flash */ +-&mmc_0 { +- status = "okay"; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- cap-mmc-highspeed; +- non-removable; +- clock-frequency = <800000000>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <0 4>; +- samsung,dw-mshc-ddr-timing = <0 2>; +- samsung,dw-mshc-hs400-timing = <0 2>; +- samsung,read-strobe-delay = <90>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; +- bus-width = <8>; +-}; +- +-/* WiFi SDIO module */ +-&mmc_1 { +- status = "okay"; +- non-removable; +- cap-sdio-irq; +- keep-power-in-suspend; +- clock-frequency = <400000000>; +- samsung,dw-mshc-ciu-div = <1>; +- samsung,dw-mshc-sdr-timing = <0 1>; +- samsung,dw-mshc-ddr-timing = <0 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>, +- <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>; +- bus-width = <4>; +- cap-sd-highspeed; +- mmc-pwrseq = <&mmc1_pwrseq>; +- vqmmc-supply = <&buck10_reg>; +-}; +- +-/* uSD card */ +-&mmc_2 { +- status = "okay"; +- cap-sd-highspeed; +- card-detect-delay = <200>; +- clock-frequency = <400000000>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; +- bus-width = <4>; +-}; +- +- +-&pinctrl_0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mask_tpm_reset>; +- +- wifi_en: wifi-en { +- samsung,pins = "gpx0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- max98091_irq: max98091-irq { +- samsung,pins = "gpx0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- /* We need GPX0_6 to be low at sleep time; just keep it low always */ +- mask_tpm_reset: mask-tpm-reset { +- samsung,pins = "gpx0-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- samsung,pin-val = <0>; +- }; +- +- tpm_irq: tpm-irq { +- samsung,pins = "gpx1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- trackpad_irq: trackpad-irq { +- samsung,pins = "gpx1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- power_key_irq: power-key-irq { +- samsung,pins = "gpx1-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- ec_irq: ec-irq { +- samsung,pins = "gpx1-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- tps65090_irq: tps65090-irq { +- samsung,pins = "gpx2-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- dp_hpd_gpio: dp_hpd_gpio { +- samsung,pins = "gpx2-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- max77802_irq: max77802-irq { +- samsung,pins = "gpx3-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lid_irq: lid-irq { +- samsung,pins = "gpx3-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hdmi_hpd_irq: hdmi-hpd-irq { +- samsung,pins = "gpx3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pmic_dvs_1: pmic-dvs-1 { +- samsung,pins = "gpy7-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_1 { +- /* Adjust WiFi drive strengths lower for EMI */ +- sd1_clk: sd1-clk { +- samsung,pin-drv = ; +- }; +- +- sd1_cmd: sd1-cmd { +- samsung,pin-drv = ; +- }; +- +- sd1_bus1: sd1-bus-width1 { +- samsung,pin-drv = ; +- }; +- +- sd1_bus4: sd1-bus-width4 { +- samsung,pin-drv = ; +- }; +- +- sd1_bus8: sd1-bus-width8 { +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_2 { +- pmic_dvs_2: pmic-dvs-2 { +- samsung,pins = "gpj4-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pmic_dvs_3: pmic-dvs-3 { +- samsung,pins = "gpj4-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_3 { +- /* Drive SPI lines at x2 for better integrity */ +- spi2-bus { +- samsung,pin-drv = ; +- }; +- +- /* Drive SPI chip select at x2 for better integrity */ +- ec_spi_cs: ec-spi-cs { +- samsung,pins = "gpb1-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- usb300_vbus_en: usb300-vbus-en { +- samsung,pins = "gph0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- usb301_vbus_en: usb301-vbus-en { +- samsung,pins = "gph0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pmic_selb: pmic-selb { +- samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", +- "gph0-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pmu_system_controller { +- assigned-clocks = <&pmu_system_controller 0>; +- assigned-clock-parents = <&clock CLK_FIN_PLL>; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&spi_2 { +- status = "okay"; +- num-cs = <1>; +- samsung,spi-src-clk = <0>; +- cs-gpios = <&gpb1 2 GPIO_ACTIVE_HIGH>; +- +- cros_ec: cros-ec@0 { +- compatible = "google,cros-ec-spi"; +- interrupt-parent = <&gpx1>; +- interrupts = <5 IRQ_TYPE_NONE>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ec_spi_cs &ec_irq>; +- reg = <0>; +- spi-max-frequency = <3125000>; +- google,has-vbc-nvram; +- +- controller-data { +- samsung,spi-feedback-delay = <1>; +- }; +- +- i2c_tunnel: i2c-tunnel { +- compatible = "google,cros-ec-i2c-tunnel"; +- #address-cells = <1>; +- #size-cells = <0>; +- google,remote-bus = <0>; +- +- battery: sbs-battery@b { +- compatible = "sbs,sbs-battery"; +- reg = <0xb>; +- sbs,poll-retry-count = <1>; +- sbs,i2c-retry-count = <2>; +- }; +- +- power-regulator@48 { +- compatible = "ti,tps65090"; +- reg = <0x48>; +- +- /* +- * Config irq to disable internal pulls +- * even though we run in polling mode. +- */ +- pinctrl-names = "default"; +- pinctrl-0 = <&tps65090_irq>; +- +- vsys1-supply = <&vbat>; +- vsys2-supply = <&vbat>; +- vsys3-supply = <&vbat>; +- infet1-supply = <&vbat>; +- infet2-supply = <&tps65090_dcdc1>; +- infet3-supply = <&tps65090_dcdc2>; +- infet4-supply = <&tps65090_dcdc2>; +- infet5-supply = <&tps65090_dcdc2>; +- infet6-supply = <&tps65090_dcdc2>; +- infet7-supply = <&tps65090_dcdc1>; +- vsys-l1-supply = <&vbat>; +- vsys-l2-supply = <&vbat>; +- +- regulators { +- tps65090_dcdc1: dcdc1 { +- ti,enable-ext-control; +- }; +- tps65090_dcdc2: dcdc2 { +- ti,enable-ext-control; +- }; +- tps65090_dcdc3: dcdc3 { +- ti,enable-ext-control; +- }; +- tps65090_fet1: fet1 { +- regulator-name = "vcd_led"; +- }; +- tps65090_fet2: fet2 { +- regulator-name = "video_mid"; +- regulator-always-on; +- }; +- tps65090_fet3: fet3 { +- regulator-name = "wwan_r"; +- regulator-always-on; +- }; +- tps65090_fet4: fet4 { +- regulator-name = "sdcard"; +- regulator-always-on; +- }; +- tps65090_fet5: fet5 { +- regulator-name = "camout"; +- regulator-always-on; +- }; +- tps65090_fet6: fet6 { +- regulator-name = "lcd_vdd"; +- }; +- tps65090_fet7: fet7 { +- regulator-name = "video_mid_1a"; +- regulator-always-on; +- }; +- tps65090_ldo1: ldo1 { +- }; +- tps65090_ldo2: ldo2 { +- }; +- }; +- +- charger { +- compatible = "ti,tps65090-charger"; +- }; +- }; +- }; +- }; +-}; +- +-&serial_3 { +- status = "okay"; +-}; +- +-&timer { +- arm,cpu-registers-not-fw-configured; +-}; +- +-&tmu_cpu0 { +- vtmu-supply = <&ldo10_reg>; +-}; +- +-&tmu_cpu1 { +- vtmu-supply = <&ldo10_reg>; +-}; +- +-&tmu_cpu2 { +- vtmu-supply = <&ldo10_reg>; +-}; +- +-&tmu_cpu3 { +- vtmu-supply = <&ldo10_reg>; +-}; +- +-&tmu_gpu { +- vtmu-supply = <&ldo10_reg>; +-}; +- +-&usbdrd_dwc3_0 { +- dr_mode = "host"; +-}; +- +-&usbdrd_dwc3_1 { +- dr_mode = "host"; +-}; +- +-&usbdrd_phy0 { +- vbus-supply = <&usb300_vbus_reg>; +-}; +- +-&usbdrd_phy1 { +- vbus-supply = <&usb301_vbus_reg>; +-}; +- +-/* +- * Use longest HW watchdog in SoC (32 seconds) since the hardware +- * watchdog provides no debugging information (compared to soft/hard +- * lockup detectors) and so should be last resort. +- */ +-&watchdog { +- timeout-sec = <32>; +-}; +- +-#include "cros-ec-keyboard.dtsi" +-#include "cros-adc-thermistors.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/exynos5800.dtsi b/scripts/dtc/include-prefixes/arm/exynos5800.dtsi +deleted file mode 100644 +index 526729dad53f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/exynos5800.dtsi ++++ /dev/null +@@ -1,162 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung Exynos5800 SoC device tree source +- * +- * Copyright (c) 2014 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Samsung Exynos5800 SoC device nodes are listed in this file. +- * Exynos5800 based board files can include this file and provide +- * values for board specfic bindings. +- */ +- +-#include "exynos5420.dtsi" +- +-/ { +- compatible = "samsung,exynos5800", "samsung,exynos5"; +-}; +- +-&clock { +- compatible = "samsung,exynos5800-clock", "syscon"; +-}; +- +-&cluster_a15_opp_table { +- opp-2000000000 { +- opp-hz = /bits/ 64 <2000000000>; +- opp-microvolt = <1312500 1312500 1500000>; +- clock-latency-ns = <140000>; +- }; +- opp-1900000000 { +- opp-hz = /bits/ 64 <1900000000>; +- opp-microvolt = <1262500 1262500 1500000>; +- clock-latency-ns = <140000>; +- }; +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <1237500 1237500 1500000>; +- clock-latency-ns = <140000>; +- }; +- opp-1700000000 { +- opp-microvolt = <1250000 1250000 1500000>; +- }; +- opp-1600000000 { +- opp-microvolt = <1250000 1250000 1500000>; +- }; +- opp-1500000000 { +- opp-microvolt = <1100000 1100000 1500000>; +- }; +- opp-1400000000 { +- opp-microvolt = <1100000 1100000 1500000>; +- }; +- opp-1300000000 { +- opp-microvolt = <1100000 1100000 1500000>; +- }; +- opp-1200000000 { +- opp-microvolt = <1000000 1000000 1500000>; +- }; +- opp-1100000000 { +- opp-microvolt = <1000000 1000000 1500000>; +- }; +- opp-1000000000 { +- opp-microvolt = <1000000 1000000 1500000>; +- }; +- opp-900000000 { +- opp-microvolt = <1000000 1000000 1500000>; +- }; +- opp-800000000 { +- opp-microvolt = <900000 900000 1500000>; +- }; +- opp-700000000 { +- opp-microvolt = <900000 900000 1500000>; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <900000 900000 1500000>; +- clock-latency-ns = <140000>; +- }; +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <900000 900000 1500000>; +- clock-latency-ns = <140000>; +- }; +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <900000 900000 1500000>; +- clock-latency-ns = <140000>; +- }; +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <900000 900000 1500000>; +- clock-latency-ns = <140000>; +- }; +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- opp-microvolt = <900000 900000 1500000>; +- clock-latency-ns = <140000>; +- }; +-}; +- +-&cluster_a7_opp_table { +- opp-1400000000 { +- opp-hz = /bits/ 64 <1400000000>; +- opp-microvolt = <1275000>; +- clock-latency-ns = <140000>; +- }; +- opp-1300000000 { +- opp-microvolt = <1250000>; +- }; +- opp-1200000000 { +- opp-microvolt = <1250000>; +- }; +- opp-1100000000 { +- opp-microvolt = <1250000>; +- }; +- opp-1000000000 { +- opp-microvolt = <1100000>; +- }; +- opp-900000000 { +- opp-microvolt = <1100000>; +- }; +- opp-800000000 { +- opp-microvolt = <1100000>; +- }; +- opp-700000000 { +- opp-microvolt = <1000000>; +- }; +- opp-600000000 { +- opp-microvolt = <1000000>; +- }; +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <1000000>; +- clock-latency-ns = <140000>; +- }; +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <1000000>; +- clock-latency-ns = <140000>; +- }; +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <900000>; +- clock-latency-ns = <140000>; +- }; +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- opp-microvolt = <900000>; +- clock-latency-ns = <140000>; +- }; +-}; +- +-&mfc { +- compatible = "samsung,mfc-v8"; +-}; +- +-&soc { +- cam_pd: power-domain@10045100 { +- compatible = "samsung,exynos4210-pd"; +- reg = <0x10045100 0x20>; +- #power-domain-cells = <0>; +- label = "CAM"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/facebook-bmc-flash-layout-128.dtsi b/scripts/dtc/include-prefixes/arm/facebook-bmc-flash-layout-128.dtsi +deleted file mode 100644 +index 7f3652dea550..000000000000 +--- a/scripts/dtc/include-prefixes/arm/facebook-bmc-flash-layout-128.dtsi ++++ /dev/null +@@ -1,60 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright (c) 2020 Facebook Inc. +- +-partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* +- * u-boot partition: 896KB. +- */ +- u-boot@0 { +- reg = <0x0 0xe0000>; +- label = "u-boot"; +- }; +- +- /* +- * u-boot environment variables: 64KB. +- */ +- u-boot-env@e0000 { +- reg = <0xe0000 0x10000>; +- label = "env"; +- }; +- +- /* +- * image metadata partition (64KB), used by Facebook internal +- * tools. +- */ +- image-meta@f0000 { +- reg = <0xf0000 0x10000>; +- label = "meta"; +- }; +- +- /* +- * FIT image: 119 MB. +- */ +- fit@100000 { +- reg = <0x100000 0x7700000>; +- label = "fit"; +- }; +- +- /* +- * "data0" partition (8MB) is used by Facebook BMC platforms as +- * persistent data store. +- */ +- data0@7800000 { +- reg = <0x7800000 0x800000>; +- label = "data0"; +- }; +- +- /* +- * Although the master partition can be created by enabling +- * MTD_PARTITIONED_MASTER option, below "flash0" partition is +- * explicitly created to avoid breaking legacy applications. +- */ +- flash0@0 { +- reg = <0x0 0x8000000>; +- label = "flash0"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/facebook-bmc-flash-layout.dtsi b/scripts/dtc/include-prefixes/arm/facebook-bmc-flash-layout.dtsi +deleted file mode 100644 +index 87bb8b576250..000000000000 +--- a/scripts/dtc/include-prefixes/arm/facebook-bmc-flash-layout.dtsi ++++ /dev/null +@@ -1,42 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright (c) 2018 Facebook Inc. +- +-partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- u-boot@0 { +- reg = <0x0 0x60000>; +- label = "u-boot"; +- }; +- +- u-boot-env@60000 { +- reg = <0x60000 0x20000>; +- label = "env"; +- }; +- +- fit@80000 { +- reg = <0x80000 0x1b80000>; +- label = "fit"; +- }; +- +- /* +- * "data0" partition is used by several Facebook BMC platforms +- * as persistent data store. +- */ +- data0@1c00000 { +- reg = <0x1c00000 0x400000>; +- label = "data0"; +- }; +- +- /* +- * Although the master partition can be created by enabling +- * MTD_PARTITIONED_MASTER option, below "flash0" partition is +- * explicitly created to avoid breaking legacy applications. +- */ +- flash0@0 { +- reg = <0x0 0x2000000>; +- label = "flash0"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ge863-pro3.dtsi b/scripts/dtc/include-prefixes/arm/ge863-pro3.dtsi +deleted file mode 100644 +index dbba33e5a06c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ge863-pro3.dtsi ++++ /dev/null +@@ -1,77 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * ge863_pro3.dtsi - Device Tree file for Telit GE863-PRO3 +- * +- * Copyright (C) 2012 Telit, +- * 2012 Fabio Porcedda +- */ +- +-#include "at91sam9260.dtsi" +- +-/ { +- clocks { +- main_xtal { +- clock-frequency = <6000000>; +- }; +- }; +- +- ahb { +- apb { +- tcb0: timer@fffa0000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +- }; +- +- dbgu: serial@fffff200 { +- status = "okay"; +- }; +- }; +- +- ebi: ebi@10000000 { +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; +- pinctrl-names = "default"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "soft"; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- boot@0 { +- label = "boot"; +- reg = <0x0 0x7c0000>; +- }; +- +- root@7c0000 { +- label = "root"; +- reg = <0x7c0000 0x7840000>; +- }; +- }; +- }; +- }; +- }; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200 root=ubi0:rootfs ubi.mtd=1 rootfstype=ubifs"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/gemini-dlink-dir-685.dts b/scripts/dtc/include-prefixes/arm/gemini-dlink-dir-685.dts +deleted file mode 100644 +index c79a2a02dd6b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/gemini-dlink-dir-685.dts ++++ /dev/null +@@ -1,510 +0,0 @@ +-/* +- * Device Tree file for D-Link DIR-685 Xtreme N Storage Router +- */ +- +-/dts-v1/; +- +-#include "gemini.dtsi" +-#include +- +-/ { +- model = "D-Link DIR-685 Xtreme N Storage Router"; +- compatible = "dlink,dir-685", "cortina,gemini"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { +- /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */ +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait consoleblank=300"; +- stdout-path = "uart0:19200n8"; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- button-esc { +- debounce-interval = <100>; +- wakeup-source; +- linux,code = ; +- label = "reset"; +- /* Collides with LPC_LAD[0], UART DCD, SSP 97RST */ +- gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; +- }; +- button-eject { +- debounce-interval = <100>; +- wakeup-source; +- linux,code = ; +- label = "unmount"; +- /* Collides with LPC LFRAME, UART RTS, SSP TXD */ +- gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- vdisp: regulator { +- compatible = "regulator-fixed"; +- regulator-name = "display-power"; +- regulator-min-microvolt = <3600000>; +- regulator-max-microvolt = <3600000>; +- /* Collides with LCD E */ +- gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- spi { +- compatible = "spi-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Collides with IDE pins, that's cool (we do not use them) */ +- sck-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- miso-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- mosi-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; +- num-chipselects = <1>; +- +- panel: display@0 { +- compatible = "dlink,dir-685-panel", "ilitek,ili9322"; +- reg = <0>; +- /* 50 ns min period = 20 MHz */ +- spi-max-frequency = <20000000>; +- vcc-supply = <&vdisp>; +- iovcc-supply = <&vdisp>; +- vci-supply = <&vdisp>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-wps { +- label = "dir685:blue:WPS"; +- /* Collides with ICE */ +- gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- /* +- * These two LEDs are on the side of the device. +- * For electrical reasons, both LEDs cannot be active +- * at the same time so only blue or orange can be on at +- * one time. Enabling both makes the LED go dark. +- * The LEDs both sit inside the unmount button and the +- * label on the case says "unmount". +- */ +- led-blue-hd { +- label = "dir685:blue:HD"; +- /* Collides with LPC_SERIRQ, UART DTR, SSP FSC pins */ +- gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "disk-read"; +- }; +- led-orange-hd { +- label = "dir685:orange:HD"; +- /* Collides with LPC_LAD[2], UART DSR, SSP ECLK pins */ +- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "disk-write"; +- }; +- }; +- +- /* +- * This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM. +- * sensor. It is turned on when the temperature exceeds 46 degrees +- * and turned off when the temperatures goes below 41 degrees +- * (celsius). +- */ +- fan0: gpio-fan { +- compatible = "gpio-fan"; +- /* Collides with IDE */ +- gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; +- gpio-fan,speed-map = <0 0>, <10000 1>; +- #cooling-cells = <2>; +- }; +- +- thermal-zones { +- chassis-thermal { +- /* Poll every 20 seconds */ +- polling-delay = <20000>; +- /* Poll every 2nd second when cooling */ +- polling-delay-passive = <2000>; +- /* Use the thermal sensor in the hard drive */ +- thermal-sensors = <&drive0>; +- +- /* Tripping points from the fan.script in the rootfs */ +- trips { +- alert: chassis-alert { +- /* At 43 degrees turn on the fan */ +- temperature = <43000>; +- hysteresis = <3000>; +- type = "active"; +- }; +- crit: chassis-crit { +- /* Just shut down at 60 degrees */ +- temperature = <60000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&alert>; +- cooling-device = <&fan0 1 1>; +- }; +- }; +- }; +- }; +- +- /* +- * The touchpad input is connected to a GPIO bit-banged +- * I2C bus. +- */ +- i2c { +- compatible = "i2c-gpio"; +- /* Collides with ICE */ +- sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- touchkeys@26 { +- compatible = "dlink,dir685-touchkeys"; +- reg = <0x26>; +- interrupt-parent = <&gpio0>; +- /* Collides with NAND flash */ +- interrupts = <17 IRQ_TYPE_EDGE_FALLING>; +- }; +- }; +- +- /* This is a RealTek RTL8366RB switch and PHY using SMI over GPIO */ +- switch { +- compatible = "realtek,rtl8366rb"; +- /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ +- mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; +- mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; +- realtek,disable-leds; +- +- switch_intc: interrupt-controller { +- /* GPIO 15 provides the interrupt */ +- interrupt-parent = <&gpio0>; +- interrupts = <15 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- }; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan0"; +- phy-handle = <&phy0>; +- }; +- port@1 { +- reg = <1>; +- label = "lan1"; +- phy-handle = <&phy1>; +- }; +- port@2 { +- reg = <2>; +- label = "lan2"; +- phy-handle = <&phy2>; +- }; +- port@3 { +- reg = <3>; +- label = "lan3"; +- phy-handle = <&phy3>; +- }; +- port@4 { +- reg = <4>; +- label = "wan"; +- phy-handle = <&phy4>; +- }; +- rtl8366rb_cpu_port: port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <&gmac0>; +- phy-mode = "rgmii"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- pause; +- }; +- }; +- +- }; +- +- mdio { +- compatible = "realtek,smi-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: phy@0 { +- reg = <0>; +- interrupt-parent = <&switch_intc>; +- interrupts = <0>; +- }; +- phy1: phy@1 { +- reg = <1>; +- interrupt-parent = <&switch_intc>; +- interrupts = <1>; +- }; +- phy2: phy@2 { +- reg = <2>; +- interrupt-parent = <&switch_intc>; +- interrupts = <2>; +- }; +- phy3: phy@3 { +- reg = <3>; +- interrupt-parent = <&switch_intc>; +- interrupts = <3>; +- }; +- phy4: phy@4 { +- reg = <4>; +- interrupt-parent = <&switch_intc>; +- interrupts = <12>; +- }; +- }; +- }; +- +- soc { +- flash@30000000 { +- /* +- * Flash access collides with the Chip Enable signal for +- * the display panel, that reuse the parallel flash Chip +- * Select 1 (CS1). We switch the pin control state so we +- * enable these pins for flash access only when we need +- * then, and when disabled they can be used for GPIO which +- * is what the display panel needs. +- */ +- status = "okay"; +- pinctrl-names = "enabled", "disabled"; +- pinctrl-0 = <&pflash_default_pins>; +- pinctrl-1 = <&pflash_disabled_pins>; +- +- /* 32MB of flash */ +- reg = <0x30000000 0x02000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* +- * This "RedBoot" is the Storlink derivative. +- */ +- partition@0 { +- label = "RedBoot"; +- reg = <0x00000000 0x00040000>; +- read-only; +- }; +- /* +- * This firmware image contains the kernel catenated +- * with the squashfs root filesystem. For some reason +- * this is called "upgrade" on the vendor system. +- */ +- partition@40000 { +- label = "upgrade"; +- reg = <0x00040000 0x01f40000>; +- read-only; +- }; +- /* RGDB, Residental Gateway Database? */ +- partition@1f80000 { +- label = "rgdb"; +- reg = <0x01f80000 0x00040000>; +- read-only; +- }; +- /* +- * This partition contains MAC addresses for WAN, +- * WLAN and LAN, and the country code (for wireless +- * I guess). +- */ +- partition@1fc0000 { +- label = "nvram"; +- reg = <0x01fc0000 0x00020000>; +- read-only; +- }; +- partition@1fe0000 { +- label = "LangPack"; +- reg = <0x01fe0000 0x00020000>; +- read-only; +- }; +- }; +- }; +- +- syscon: syscon@40000000 { +- pinctrl { +- /* +- * gpio0bgrp cover line 5, 6 used by TK I2C +- * gpio0bgrp cover line 7 used by WPS LED +- * gpio0cgrp cover line 8, 13 used by keys +- * and 11, 12 used by the HD LEDs +- * and line 14, 15 used by RTL8366 +- * RESET and phy ready +- * gpio0egrp cover line 16 used by VDISP +- * gpio0fgrp cover line 17 used by TK IRQ +- * gpio0ggrp cover line 20 used by panel CS +- * gpio0hgrp cover line 21,22 used by RTL8366RB MDIO +- */ +- gpio0_default_pins: pinctrl-gpio0 { +- mux { +- function = "gpio0"; +- groups = "gpio0bgrp", +- "gpio0cgrp", +- "gpio0egrp", +- "gpio0fgrp", +- "gpio0hgrp"; +- }; +- }; +- /* +- * gpio1bgrp cover line 5,8,7 used by panel SPI +- * also line 6 used by the fan +- * +- */ +- gpio1_default_pins: pinctrl-gpio1 { +- mux { +- function = "gpio1"; +- groups = "gpio1bgrp"; +- }; +- }; +- /* +- * These GPIO groups will be mapped in over some +- * of the flash pins when the flash is not in +- * active use. +- */ +- pflash_disabled_pins: pinctrl-pflash-disabled { +- mux { +- function = "gpio0"; +- groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp", +- "gpio0kgrp"; +- }; +- }; +- pinctrl-gmii { +- mux { +- function = "gmii"; +- groups = "gmii_gmac0_grp"; +- }; +- conf0 { +- pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV", +- "Y7 GMAC0 RXC", "Y11 GMAC1 RXC", +- "T8 GMAC0 TXEN", "W11 GMAC1 TXEN", +- "U8 GMAC0 TXC", "V11 GMAC1 TXC", +- "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", +- "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", +- "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", +- "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", +- "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", +- "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", +- "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", +- "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; +- skew-delay = <7>; +- }; +- /* Set up drive strength on GMAC0 to 16 mA */ +- conf1 { +- groups = "gmii_gmac0_grp"; +- drive-strength = <16>; +- }; +- }; +- }; +- }; +- +- sata: sata@46000000 { +- cortina,gemini-ata-muxmode = <0>; +- cortina,gemini-enable-sata-bridge; +- status = "okay"; +- }; +- +- gpio0: gpio@4d000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio0_default_pins>; +- }; +- +- gpio1: gpio@4e000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio1_default_pins>; +- }; +- +- pci@50000000 { +- status = "okay"; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = +- <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ +- <0x4800 0 0 2 &pci_intc 1>, +- <0x4800 0 0 3 &pci_intc 2>, +- <0x4800 0 0 4 &pci_intc 3>, +- <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ +- <0x5000 0 0 2 &pci_intc 2>, +- <0x5000 0 0 3 &pci_intc 3>, +- <0x5000 0 0 4 &pci_intc 0>, +- <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ +- <0x5800 0 0 2 &pci_intc 3>, +- <0x5800 0 0 3 &pci_intc 0>, +- <0x5800 0 0 4 &pci_intc 1>, +- <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ +- <0x6000 0 0 2 &pci_intc 0>, +- <0x6000 0 0 3 &pci_intc 1>, +- <0x6000 0 0 4 &pci_intc 2>; +- }; +- +- ethernet@60000000 { +- status = "okay"; +- +- ethernet-port@0 { +- phy-mode = "rgmii"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- pause; +- }; +- }; +- ethernet-port@1 { +- /* Not used in this platform */ +- }; +- }; +- +- ide@63000000 { +- status = "okay"; +- +- /* +- * This drive may have a temperature sensor with a +- * thermal zone we can use for thermal control of the +- * chassis temperature using the fan. +- */ +- drive0: ide-port@0 { +- reg = <0>; +- #thermal-sensor-cells = <0>; +- }; +- }; +- +- display-controller@6a000000 { +- status = "okay"; +- +- port { +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +- +- usb@68000000 { +- status = "okay"; +- }; +- +- usb@69000000 { +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/gemini-dlink-dns-313.dts b/scripts/dtc/include-prefixes/arm/gemini-dlink-dns-313.dts +deleted file mode 100644 +index eba1c94ed7f7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/gemini-dlink-dns-313.dts ++++ /dev/null +@@ -1,304 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree file for D-Link DNS-313 1-Bay Network Storage Enclosure +- */ +- +-/dts-v1/; +- +-#include "gemini.dtsi" +-#include +-#include +- +-/ { +- model = "D-Link DNS-313 1-Bay Network Storage Enclosure"; +- compatible = "dlink,dns-313", "cortina,gemini"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { +- /* 64 MB SDRAM in a Nanya NT5DS32M16BS-6K package */ +- device_type = "memory"; +- reg = <0x00000000 0x4000000>; +- }; +- +- aliases { +- mdio-gpio0 = &mdio0; +- }; +- +- chosen { +- bootargs = "console=ttyS0,19200n8 root=/dev/sda4 rw rootwait"; +- stdout-path = "uart0:19200n8"; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- button-esc { +- debounce-interval = <100>; +- wakeup-source; +- linux,code = ; +- label = "reset"; +- gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-power { +- label = "dns313:blue:power"; +- gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- led-disk-blue { +- label = "dns313:blue:disk"; +- gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led-disk-green { +- label = "dns313:green:disk"; +- gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "disk-read"; +- }; +- led-disk-red { +- label = "dns313:red:disk"; +- gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "disk-write"; +- }; +- }; +- +- /* +- * This is a ADDA AD0405GB-G73 fan @3000 and 6000 RPM. +- */ +- fan0: gpio-fan { +- compatible = "gpio-fan"; +- gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>, +- <&gpio0 12 GPIO_ACTIVE_HIGH>; +- gpio-fan,speed-map = <0 0>, <3000 1>, <6000 2>; +- #cooling-cells = <2>; +- }; +- +- +- /* Global Mixed-Mode Technology G751 mounted on GPIO I2C */ +- i2c { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- g751: temperature-sensor@48 { +- compatible = "gmt,g751"; +- reg = <0x48>; +- #thermal-sensor-cells = <0>; +- }; +- }; +- +- thermal-zones { +- chassis-thermal { +- /* Poll every 20 seconds */ +- polling-delay = <20000>; +- /* Poll every 2nd second when cooling */ +- polling-delay-passive = <2000>; +- +- thermal-sensors = <&g751>; +- +- /* Tripping points from the fan.script in the rootfs */ +- trips { +- chassis_alert0: chassis-alert0 { +- /* At 43 degrees turn on low speed */ +- temperature = <43000>; +- hysteresis = <3000>; +- type = "active"; +- }; +- chassis_alert1: chassis-alert1 { +- /* At 47 degrees turn on high speed */ +- temperature = <47000>; +- hysteresis = <3000>; +- type = "active"; +- }; +- chassis_crit: chassis-crit { +- /* Just shut down at 60 degrees */ +- temperature = <60000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&chassis_alert0>; +- cooling-device = <&fan0 1 1>; +- }; +- map1 { +- trip = <&chassis_alert1>; +- cooling-device = <&fan0 2 2>; +- }; +- }; +- }; +- }; +- +- mdio0: mdio { +- compatible = "virtual,mdio-gpio"; +- /* Uses MDC and MDIO */ +- gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ +- <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* This is a Realtek RTL8211B Gigabit ethernet transceiver */ +- phy0: ethernet-phy@1 { +- reg = <1>; +- device_type = "ethernet-phy"; +- }; +- }; +- +- soc { +- flash@30000000 { +- /* +- * This is a Eon EN29LV400AB 512 KiB flash with +- * three partitions. +- */ +- compatible = "cortina,gemini-flash", "jedec-flash"; +- status = "okay"; +- reg = <0x30000000 0x00080000>; +- +- /* +- * This "RedBoot" is the Storlink derivative. +- */ +- partition@0 { +- label = "RedBoot"; +- reg = <0x00000000 0x00040000>; +- read-only; +- }; +- partition@40000 { +- label = "MTD1"; +- reg = <0x00040000 0x00020000>; +- read-only; +- }; +- partition@60000 { +- label = "MTD2"; +- reg = <0x00060000 0x00020000>; +- read-only; +- }; +- }; +- +- syscon: syscon@40000000 { +- pinctrl { +- /* +- */ +- gpio0_default_pins: pinctrl-gpio0 { +- mux { +- function = "gpio0"; +- groups = +- /* Used by LEDs conflicts ICE */ +- "gpio0bgrp", +- /* Used by ? conflicts ICE */ +- "gpio0cgrp", +- /* +- * Used by fan & G751, conflicts LPC, +- * UART modem lines, SSP +- */ +- "gpio0egrp", +- /* Used by G751 */ +- "gpio0fgrp", +- /* Used by MDIO */ +- "gpio0igrp"; +- }; +- }; +- gpio1_default_pins: pinctrl-gpio1 { +- mux { +- function = "gpio1"; +- /* Used by "reset" button */ +- groups = "gpio1dgrp"; +- }; +- }; +- pinctrl-gmii { +- mux { +- function = "gmii"; +- groups = "gmii_gmac0_grp"; +- }; +- /* +- * In the vendor Linux tree, these values are set for the C3 +- * version of the SL3512 ASIC with the comment "benson suggest" +- */ +- conf0 { +- pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV"; +- skew-delay = <0>; +- }; +- conf1 { +- pins = "T8 GMAC0 RXC"; +- skew-delay = <10>; +- }; +- conf2 { +- pins = "T11 GMAC1 RXC"; +- skew-delay = <15>; +- }; +- conf3 { +- pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN"; +- skew-delay = <7>; +- }; +- conf4 { +- pins = "V7 GMAC0 TXC", "P10 GMAC1 TXC"; +- skew-delay = <10>; +- }; +- conf5 { +- /* The data lines all have default skew */ +- pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1", +- "P9 GMAC0 RXD2", "R9 GMAC0 RXD3", +- "R11 GMAC1 RXD0", "P11 GMAC1 RXD1", +- "V12 GMAC1 RXD2", "U12 GMAC1 RXD3", +- "R10 GMAC1 TXD0", "T10 GMAC1 TXD1", +- "U10 GMAC1 TXD2", "V10 GMAC1 TXD3"; +- skew-delay = <7>; +- }; +- conf6 { +- pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1", +- "R7 GMAC0 TXD2", "P7 GMAC0 TXD3"; +- skew-delay = <5>; +- }; +- /* Set up drive strength on GMAC0 to 16 mA */ +- conf7 { +- groups = "gmii_gmac0_grp"; +- drive-strength = <16>; +- }; +- }; +- }; +- }; +- +- sata: sata@46000000 { +- /* The ROM uses this muxmode */ +- cortina,gemini-ata-muxmode = <0>; +- cortina,gemini-enable-sata-bridge; +- status = "okay"; +- }; +- +- gpio0: gpio@4d000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio0_default_pins>; +- }; +- +- gpio1: gpio@4e000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio1_default_pins>; +- }; +- +- ethernet@60000000 { +- status = "okay"; +- +- ethernet-port@0 { +- phy-mode = "rgmii"; +- phy-handle = <&phy0>; +- }; +- ethernet-port@1 { +- /* Not used in this platform */ +- }; +- }; +- +- ide@63000000 { +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/gemini-nas4220b.dts b/scripts/dtc/include-prefixes/arm/gemini-nas4220b.dts +deleted file mode 100644 +index 6544c730340f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/gemini-nas4220b.dts ++++ /dev/null +@@ -1,189 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree file for the Gemini-based Raidsonic NAS IB-4220-B +- */ +- +-/dts-v1/; +- +-#include "gemini.dtsi" +-#include +- +-/ { +- model = "Raidsonic NAS IB-4220-B"; +- compatible = "raidsonic,ib-4220-b", "cortina,gemini"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { /* 128 MB */ +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,19200n8 root=/dev/mtdblock3 rw rootfstype=squashfs,jffs2 rootwait"; +- stdout-path = &uart0; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- button-setup { +- debounce-interval = <100>; +- wakeup-source; +- linux,code = ; +- label = "Backup button"; +- /* Conflict with TVC */ +- gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; +- }; +- button-restart { +- debounce-interval = <100>; +- wakeup-source; +- linux,code = ; +- label = "Softreset button"; +- /* Conflict with TVC */ +- gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-orange-hdd { +- label = "nas4220b:orange:hdd"; +- /* Conflict with TVC */ +- gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- led-green-os { +- label = "nas4220b:green:os"; +- /* Conflict with TVC */ +- gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- mdio0: mdio { +- compatible = "virtual,mdio-gpio"; +- gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ +- <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: ethernet-phy@1 { +- reg = <1>; +- device_type = "ethernet-phy"; +- }; +- }; +- +- soc { +- flash@30000000 { +- status = "okay"; +- /* 16MB of flash */ +- reg = <0x30000000 0x01000000>; +- +- partitions { +- compatible = "redboot-fis"; +- /* Eraseblock at 0xfe0000 */ +- fis-index-block = <0x7f>; +- }; +- }; +- +- syscon: syscon@40000000 { +- pinctrl { +- /* +- * gpio1dgrp cover line 28-31 otherwise used +- * by TVC. +- */ +- gpio1_default_pins: pinctrl-gpio1 { +- mux { +- function = "gpio1"; +- groups = "gpio1dgrp"; +- }; +- }; +- pinctrl-gmii { +- mux { +- function = "gmii"; +- groups = "gmii_gmac0_grp"; +- }; +- /* Settings come from OpenWRT, pins on SL3516 */ +- conf0 { +- pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV"; +- skew-delay = <0>; +- }; +- conf1 { +- pins = "Y7 GMAC0 RXC", "Y11 GMAC1 RXC"; +- skew-delay = <15>; +- }; +- conf2 { +- pins = "T8 GMAC0 TXEN", "W11 GMAC1 TXEN"; +- skew-delay = <7>; +- }; +- conf3 { +- pins = "U8 GMAC0 TXC"; +- skew-delay = <11>; +- }; +- conf4 { +- pins = "V11 GMAC1 TXC"; +- skew-delay = <10>; +- }; +- conf5 { +- /* The data lines all have default skew */ +- pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", +- "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", +- "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", +- "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", +- "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", +- "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", +- "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", +- "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; +- skew-delay = <7>; +- }; +- /* Set up drive strength on GMAC0 to 16 mA */ +- conf6 { +- groups = "gmii_gmac0_grp"; +- drive-strength = <16>; +- }; +- }; +- }; +- }; +- +- sata: sata@46000000 { +- cortina,gemini-ata-muxmode = <0>; +- cortina,gemini-enable-sata-bridge; +- status = "okay"; +- }; +- +- gpio1: gpio@4e000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio1_default_pins>; +- }; +- +- ethernet@60000000 { +- status = "okay"; +- +- ethernet-port@0 { +- phy-mode = "rgmii"; +- phy-handle = <&phy0>; +- }; +- ethernet-port@1 { +- /* Not used in this platform */ +- }; +- }; +- +- ide@63000000 { +- status = "okay"; +- }; +- +- ide@63400000 { +- status = "okay"; +- }; +- +- usb@68000000 { +- status = "okay"; +- }; +- +- usb@69000000 { +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/gemini-rut1xx.dts b/scripts/dtc/include-prefixes/arm/gemini-rut1xx.dts +deleted file mode 100644 +index 0ebda4efd9d0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/gemini-rut1xx.dts ++++ /dev/null +@@ -1,136 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree file for Teltonika RUT1xx +- */ +- +-/dts-v1/; +- +-#include "gemini.dtsi" +-#include +- +-/ { +- model = "Teltonika RUT1xx"; +- compatible = "teltonika,rut1xx", "cortina,gemini"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { /* 128 MB */ +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- button-setup { +- debounce-interval = <100>; +- wakeup-source; +- linux,code = ; +- label = "Reset to defaults"; +- /* Conflict with TVC */ +- gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-gsm { +- /* FIXME: add the LED color */ +- label = "rut1xx::gsm"; +- /* Conflict with ICE */ +- gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- led-power { +- /* FIXME: add the LED color */ +- label = "rut1xx::power"; +- /* Conflict with NAND CE0 */ +- gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- mdio0: mdio { +- compatible = "virtual,mdio-gpio"; +- gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ +- <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: ethernet-phy@1 { +- reg = <1>; +- device_type = "ethernet-phy"; +- }; +- }; +- +- soc { +- flash@30000000 { +- status = "okay"; +- /* 8MB of flash */ +- reg = <0x30000000 0x00800000>; +- /* TODO: add flash partitions here */ +- }; +- +- syscon: syscon@40000000 { +- pinctrl { +- /* +- * gpio0bgrp cover line 7 used by GSM LED +- * gpio0fgrp cover line 17 used by power LED +- */ +- gpio0_default_pins: pinctrl-gpio0 { +- mux { +- function = "gpio0"; +- groups = "gpio0bgrp", +- "gpio0fgrp"; +- }; +- }; +- /* +- * gpio1dgrp cover line 28-31 otherwise used +- * by TVC. +- */ +- gpio1_default_pins: pinctrl-gpio1 { +- mux { +- function = "gpio1"; +- groups = "gpio1dgrp"; +- }; +- }; +- }; +- }; +- +- gpio0: gpio@4d000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio0_default_pins>; +- }; +- +- gpio1: gpio@4e000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio1_default_pins>; +- }; +- +- ethernet@60000000 { +- status = "okay"; +- +- ethernet-port@0 { +- phy-mode = "rgmii"; +- phy-handle = <&phy0>; +- }; +- ethernet-port@1 { +- /* Not used in this platform */ +- }; +- }; +- +- usb@68000000 { +- status = "okay"; +- }; +- +- usb@69000000 { +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/gemini-sl93512r.dts b/scripts/dtc/include-prefixes/arm/gemini-sl93512r.dts +deleted file mode 100644 +index c78e55fd2562..000000000000 +--- a/scripts/dtc/include-prefixes/arm/gemini-sl93512r.dts ++++ /dev/null +@@ -1,312 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree file for the Storm Semiconductor SL93512R_BRD +- * Gemini reference design, also initially called +- * "Gemini324 EV-Board" before Storm acquired Storlink Semiconductor. +- * The series were later acquired by Cortina Systems. +- */ +- +-/dts-v1/; +- +-#include "gemini.dtsi" +-#include +- +-/ { +- model = "Storlink Semiconductor Gemini324 EV-Board / Storm Semiconductor SL93512R_BRD"; +- compatible = "storlink,gemini324", "storm,sl93512r", "cortina,gemini"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { +- /* 64 MB Samsung K4H511638B */ +- device_type = "memory"; +- reg = <0x00000000 0x4000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,19200n8 root=/dev/mtdblock3 rw rootfstype=squashfs,jffs2 rootwait"; +- stdout-path = &uart0; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- button-wps { +- debounce-interval = <50>; +- wakeup-source; +- linux,code = ; +- label = "WPS"; +- /* Conflicts with TVC and extended flash */ +- gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; +- }; +- +- button-setup { +- debounce-interval = <50>; +- wakeup-source; +- linux,code = ; +- label = "factory reset"; +- /* Conflict with NAND flash */ +- gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-green-harddisk { +- label = "sq201:green:harddisk"; +- /* Conflict with LCD (no problem) */ +- gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- linux,default-trigger = "disk-activity"; +- }; +- led-green-wireless { +- label = "sq201:green:wireless"; +- /* Conflict with NAND flash CE0 (no problem) */ +- gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- mdio0: mdio { +- compatible = "virtual,mdio-gpio"; +- /* Uses MDC and MDIO */ +- gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ +- <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* This is a Marvell 88E1111 ethernet transciever */ +- phy0: ethernet-phy@1 { +- reg = <1>; +- }; +- }; +- +- spi { +- compatible = "spi-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- /* Check pin collisions */ +- sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; +- miso-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; +- mosi-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; +- num-chipselects = <1>; +- +- switch@0 { +- compatible = "vitesse,vsc7385"; +- reg = <0>; +- /* Specified for 2.5 MHz or below */ +- spi-max-frequency = <2500000>; +- gpio-controller; +- #gpio-cells = <2>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan1"; +- }; +- port@1 { +- reg = <1>; +- label = "lan2"; +- }; +- port@2 { +- reg = <2>; +- label = "lan3"; +- }; +- port@3 { +- reg = <3>; +- label = "lan4"; +- }; +- vsc: port@6 { +- reg = <6>; +- label = "cpu"; +- ethernet = <&gmac1>; +- phy-mode = "rgmii"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- pause; +- }; +- }; +- }; +- }; +- }; +- +- +- soc { +- flash@30000000 { +- status = "okay"; +- /* 16MB of flash */ +- reg = <0x30000000 0x01000000>; +- +- partitions { +- compatible = "redboot-fis"; +- /* Eraseblock at 0xfe0000 */ +- fis-index-block = <0x1fc>; +- }; +- }; +- +- syscon: syscon@40000000 { +- pinctrl { +- /* +- * gpio0agrp cover line 0, used by WPS button +- * gpio0fgrp cover line 16 used by HD LED +- * gpio0ggrp cover line 17, 18 used by wireless LAN LED and +- * reset button OR USB ID select on 17 and USB VBUS select +- * on 18. (Confusing.) +- * gpio0igrp cover line 21, 22 used by MDIO for Marvell PHY +- */ +- gpio0_default_pins: pinctrl-gpio0 { +- mux { +- function = "gpio0"; +- groups = "gpio0agrp", +- "gpio0fgrp", +- "gpio0ggrp", +- "gpio0igrp"; +- }; +- }; +- /* +- * gpio1dgrp cover lines used by SPI for +- * the Vitesse chip (28-31) +- */ +- gpio1_default_pins: pinctrl-gpio1 { +- mux { +- function = "gpio1"; +- groups = "gpio1dgrp"; +- }; +- }; +- pinctrl-gmii { +- mux { +- function = "gmii"; +- groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; +- }; +- /* Control pad skew comes from sl_switch.c in the vendor code */ +- conf0 { +- pins = "P10 GMAC1 TXC"; +- skew-delay = <5>; +- }; +- conf1 { +- pins = "V11 GMAC1 TXEN"; +- skew-delay = <7>; +- }; +- conf2 { +- pins = "T11 GMAC1 RXC"; +- skew-delay = <8>; +- }; +- conf3 { +- pins = "U11 GMAC1 RXDV"; +- skew-delay = <7>; +- }; +- conf4 { +- pins = "V7 GMAC0 TXC"; +- skew-delay = <10>; +- }; +- conf5 { +- pins = "P8 GMAC0 TXEN"; +- skew-delay = <7>; /* 5 at another place? */ +- }; +- conf6 { +- pins = "T8 GMAC0 RXC"; +- skew-delay = <15>; +- }; +- conf7 { +- pins = "R8 GMAC0 RXDV"; +- skew-delay = <0>; +- }; +- conf8 { +- /* The data lines all have default skew */ +- pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1", +- "P9 GMAC0 RXD2", "R9 GMAC0 RXD3", +- "R11 GMAC1 RXD0", "P11 GMAC1 RXD1", +- "V12 GMAC1 RXD2", "U12 GMAC1 RXD3", +- "R10 GMAC1 TXD0", "T10 GMAC1 TXD1", +- "U10 GMAC1 TXD2", "V10 GMAC1 TXD3"; +- skew-delay = <7>; +- }; +- /* Appears in sl351x_gmac.c in the vendor code */ +- conf9 { +- pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1", +- "R7 GMAC0 TXD2", "P7 GMAC0 TXD3"; +- skew-delay = <5>; +- }; +- }; +- }; +- }; +- +- /* Both interfaces brought out on SATA connectors */ +- sata: sata@46000000 { +- cortina,gemini-ata-muxmode = <0>; +- cortina,gemini-enable-sata-bridge; +- status = "okay"; +- }; +- +- gpio0: gpio@4d000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio0_default_pins>; +- }; +- +- gpio1: gpio@4e000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio1_default_pins>; +- }; +- +- pci@50000000 { +- status = "okay"; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = +- <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ +- <0x4800 0 0 2 &pci_intc 1>, +- <0x4800 0 0 3 &pci_intc 2>, +- <0x4800 0 0 4 &pci_intc 3>, +- <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ +- <0x5000 0 0 2 &pci_intc 2>, +- <0x5000 0 0 3 &pci_intc 3>, +- <0x5000 0 0 4 &pci_intc 0>, +- <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ +- <0x5800 0 0 2 &pci_intc 3>, +- <0x5800 0 0 3 &pci_intc 0>, +- <0x5800 0 0 4 &pci_intc 1>, +- <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ +- <0x6000 0 0 2 &pci_intc 0>, +- <0x6000 0 0 3 &pci_intc 1>, +- <0x6000 0 0 4 &pci_intc 2>; +- }; +- +- ethernet@60000000 { +- status = "okay"; +- +- ethernet-port@0 { +- phy-mode = "rgmii"; +- phy-handle = <&phy0>; +- }; +- ethernet-port@1 { +- phy-mode = "rgmii"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- pause; +- }; +- }; +- }; +- +- ide@63000000 { +- status = "okay"; +- }; +- +- ide@63400000 { +- status = "okay"; +- }; +- +- usb@68000000 { +- status = "okay"; +- }; +- +- usb@69000000 { +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/gemini-sq201.dts b/scripts/dtc/include-prefixes/arm/gemini-sq201.dts +deleted file mode 100644 +index 1b64cc80b55a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/gemini-sq201.dts ++++ /dev/null +@@ -1,304 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree file for ITian Square One SQ201 NAS +- */ +- +-/dts-v1/; +- +-#include "gemini.dtsi" +-#include +- +-/ { +- model = "ITian Square One SQ201"; +- compatible = "itian,sq201", "cortina,gemini"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { /* 128 MB */ +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait"; +- stdout-path = &uart0; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- button-setup { +- debounce-interval = <100>; +- wakeup-source; +- linux,code = ; +- label = "factory reset"; +- /* Conflict with NAND flash */ +- gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-green-info { +- label = "sq201:green:info"; +- gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- led-green-usb { +- label = "sq201:green:usb"; +- gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "usb-host"; +- }; +- }; +- +- mdio0: mdio { +- compatible = "virtual,mdio-gpio"; +- /* Uses MDC and MDIO */ +- gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ +- <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* This is a Marvell 88E1111 ethernet transciever */ +- phy0: ethernet-phy@1 { +- reg = <1>; +- }; +- }; +- +- spi { +- compatible = "spi-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- /* Check pin collisions */ +- sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; +- miso-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; +- mosi-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; +- num-chipselects = <1>; +- +- switch@0 { +- compatible = "vitesse,vsc7395"; +- reg = <0>; +- /* Specified for 2.5 MHz or below */ +- spi-max-frequency = <2500000>; +- gpio-controller; +- #gpio-cells = <2>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan1"; +- }; +- port@1 { +- reg = <1>; +- label = "lan2"; +- }; +- port@2 { +- reg = <2>; +- label = "lan3"; +- }; +- port@3 { +- reg = <3>; +- label = "lan4"; +- }; +- vsc: port@6 { +- reg = <6>; +- label = "cpu"; +- ethernet = <&gmac1>; +- phy-mode = "rgmii"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- pause; +- }; +- }; +- }; +- }; +- }; +- +- +- soc { +- flash@30000000 { +- status = "okay"; +- pinctrl-names = "enabled", "disabled"; +- pinctrl-0 = <&pflash_default_pins>; +- pinctrl-1 = <&pflash_disabled_pins>; +- /* 16MB of flash */ +- reg = <0x30000000 0x01000000>; +- +- partitions { +- compatible = "redboot-fis"; +- /* Eraseblock at 0xfe0000 */ +- fis-index-block = <0x1fc>; +- }; +- }; +- +- syscon: syscon@40000000 { +- pinctrl { +- /* +- * gpio0fgrp cover line 18 used by reset button +- * gpio0ggrp cover line 20 used by info LED +- * gpio0hgrp cover line 21, 22 used by MDIO for Marvell PHY +- * gpio0kgrp cover line 31 used by USB LED +- */ +- gpio0_default_pins: pinctrl-gpio0 { +- mux { +- function = "gpio0"; +- groups = "gpio0fgrp", +- "gpio0hgrp"; +- }; +- }; +- /* +- * gpio0dgrp cover lines used by the SPI +- * to the Vitesse G5x chip. +- */ +- gpio1_default_pins: pinctrl-gpio1 { +- mux { +- function = "gpio1"; +- groups = "gpio1dgrp"; +- }; +- }; +- /* +- * These GPIO groups will be mapped in over some +- * of the flash pins when the flash is not in +- * active use. +- */ +- pflash_disabled_pins: pinctrl-pflash-disabled { +- mux { +- function = "gpio0"; +- groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp", +- "gpio0kgrp"; +- }; +- }; +- pinctrl-gmii { +- mux { +- function = "gmii"; +- groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; +- }; +- /* Settings come from memory dump in PLATO */ +- conf0 { +- pins = "V8 GMAC0 RXDV"; +- skew-delay = <0>; +- }; +- conf1 { +- pins = "Y7 GMAC0 RXC"; +- skew-delay = <15>; +- }; +- conf2 { +- pins = "T8 GMAC0 TXEN"; +- skew-delay = <7>; +- }; +- conf3 { +- pins = "U8 GMAC0 TXC"; +- skew-delay = <10>; +- }; +- conf4 { +- pins = "T10 GMAC1 RXDV"; +- skew-delay = <7>; +- }; +- conf5 { +- pins = "Y11 GMAC1 RXC"; +- skew-delay = <8>; +- }; +- conf6 { +- pins = "W11 GMAC1 TXEN"; +- skew-delay = <7>; +- }; +- conf7 { +- pins = "V11 GMAC1 TXC"; +- skew-delay = <5>; +- }; +- conf8 { +- /* The data lines all have default skew */ +- pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", +- "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", +- "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", +- "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", +- "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", +- "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", +- "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", +- "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; +- skew-delay = <7>; +- }; +- /* Set up drive strength on GMAC0 and GMAC1 to 16 mA */ +- conf9 { +- groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; +- drive-strength = <16>; +- }; +- }; +- }; +- }; +- +- sata: sata@46000000 { +- cortina,gemini-ata-muxmode = <0>; +- cortina,gemini-enable-sata-bridge; +- status = "okay"; +- }; +- +- gpio0: gpio@4d000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio0_default_pins>; +- }; +- +- gpio1: gpio@4e000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio1_default_pins>; +- }; +- +- pci@50000000 { +- status = "okay"; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = +- <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ +- <0x4800 0 0 2 &pci_intc 1>, +- <0x4800 0 0 3 &pci_intc 2>, +- <0x4800 0 0 4 &pci_intc 3>, +- <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ +- <0x5000 0 0 2 &pci_intc 2>, +- <0x5000 0 0 3 &pci_intc 3>, +- <0x5000 0 0 4 &pci_intc 0>, +- <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ +- <0x5800 0 0 2 &pci_intc 3>, +- <0x5800 0 0 3 &pci_intc 0>, +- <0x5800 0 0 4 &pci_intc 1>, +- <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ +- <0x6000 0 0 2 &pci_intc 0>, +- <0x6000 0 0 3 &pci_intc 1>, +- <0x6000 0 0 4 &pci_intc 2>; +- }; +- +- ethernet@60000000 { +- status = "okay"; +- +- ethernet-port@0 { +- phy-mode = "rgmii"; +- phy-handle = <&phy0>; +- }; +- ethernet-port@1 { +- phy-mode = "rgmii"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- pause; +- }; +- }; +- }; +- +- ide@63000000 { +- status = "okay"; +- }; +- +- usb@68000000 { +- status = "okay"; +- }; +- +- usb@69000000 { +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/gemini-wbd111.dts b/scripts/dtc/include-prefixes/arm/gemini-wbd111.dts +deleted file mode 100644 +index 5602ba8f30f2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/gemini-wbd111.dts ++++ /dev/null +@@ -1,183 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree file for Wiliboard WBD-111 +- */ +- +-/dts-v1/; +- +-#include "gemini.dtsi" +-#include +- +-/ { +- model = "Wiliboard WBD-111"; +- compatible = "wiliboard,wbd111", "cortina,gemini"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { +- /* 128 MB */ +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- button-setup { +- debounce-interval = <100>; +- wakeup-source; +- linux,code = ; +- label = "reset"; +- /* Conflict with ICE */ +- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-red-l3 { +- label = "wbd111:red:L3"; +- /* Conflict with TVC and extended parallel flash */ +- gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led-green-l4 { +- label = "wbd111:green:L4"; +- /* Conflict with TVC and extended parallel flash */ +- gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led-red-l4 { +- label = "wbd111:red:L4"; +- /* Conflict with TVC and extended parallel flash */ +- gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led-greeb-l3 { +- label = "wbd111:green:L3"; +- /* Conflict with TVC and extended parallel flash */ +- gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- mdio0: mdio { +- compatible = "virtual,mdio-gpio"; +- gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ +- <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: ethernet-phy@1 { +- reg = <1>; +- device_type = "ethernet-phy"; +- }; +- }; +- +- soc { +- flash@30000000 { +- status = "okay"; +- /* 8MB of flash */ +- reg = <0x30000000 0x00800000>; +- +- partition@0 { +- label = "RedBoot"; +- reg = <0x00000000 0x00020000>; +- read-only; +- }; +- partition@20000 { +- label = "kernel"; +- reg = <0x00020000 0x00100000>; +- }; +- partition@120000 { +- label = "rootfs"; +- reg = <0x00120000 0x006a0000>; +- }; +- partition@7c0000 { +- label = "VCTL"; +- reg = <0x007c0000 0x00010000>; +- read-only; +- }; +- partition@7d0000 { +- label = "cfg"; +- reg = <0x007d0000 0x00010000>; +- read-only; +- }; +- partition@7e0000 { +- label = "FIS"; +- reg = <0x007e0000 0x00010000>; +- read-only; +- }; +- }; +- +- syscon: syscon@40000000 { +- pinctrl { +- /* +- * gpio0agrp cover line 0-4 +- * gpio0bgrp cover line 5 +- */ +- gpio0_default_pins: pinctrl-gpio0 { +- mux { +- function = "gpio0"; +- groups = "gpio0agrp", +- "gpio0bgrp"; +- }; +- }; +- }; +- }; +- +- gpio0: gpio@4d000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio0_default_pins>; +- }; +- +- pci@50000000 { +- status = "okay"; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = +- <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ +- <0x4800 0 0 2 &pci_intc 1>, +- <0x4800 0 0 3 &pci_intc 2>, +- <0x4800 0 0 4 &pci_intc 3>, +- <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ +- <0x5000 0 0 2 &pci_intc 2>, +- <0x5000 0 0 3 &pci_intc 3>, +- <0x5000 0 0 4 &pci_intc 0>, +- <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ +- <0x5800 0 0 2 &pci_intc 3>, +- <0x5800 0 0 3 &pci_intc 0>, +- <0x5800 0 0 4 &pci_intc 1>, +- <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ +- <0x6000 0 0 2 &pci_intc 0>, +- <0x6000 0 0 3 &pci_intc 1>, +- <0x6000 0 0 4 &pci_intc 2>; +- }; +- +- ethernet@60000000 { +- status = "okay"; +- +- ethernet-port@0 { +- phy-mode = "rgmii"; +- phy-handle = <&phy0>; +- }; +- ethernet-port@1 { +- /* Not used in this platform */ +- }; +- }; +- +- usb@68000000 { +- status = "okay"; +- }; +- +- usb@69000000 { +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/gemini-wbd222.dts b/scripts/dtc/include-prefixes/arm/gemini-wbd222.dts +deleted file mode 100644 +index a4a260c36d75..000000000000 +--- a/scripts/dtc/include-prefixes/arm/gemini-wbd222.dts ++++ /dev/null +@@ -1,195 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree file for Wiliboard WBD-222 +- */ +- +-/dts-v1/; +- +-#include "gemini.dtsi" +-#include +- +-/ { +- model = "Wiliboard WBD-222"; +- compatible = "wiliboard,wbd222", "cortina,gemini"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { /* 128 MB */ +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- button-setup { +- debounce-interval = <100>; +- wakeup-source; +- linux,code = ; +- label = "reset"; +- /* Conflict with ICE */ +- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-red-l3 { +- label = "wbd111:red:L3"; +- /* Conflict with TVC and extended parallel flash */ +- gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led-green-l4 { +- label = "wbd111:green:L4"; +- /* Conflict with TVC and extended parallel flash */ +- gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led-red-l4 { +- label = "wbd111:red:L4"; +- /* Conflict with TVC and extended parallel flash */ +- gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led-green-l3 { +- label = "wbd111:green:L3"; +- /* Conflict with TVC and extended parallel flash */ +- gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- mdio0: mdio { +- compatible = "virtual,mdio-gpio"; +- gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ +- <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: ethernet-phy@1 { +- reg = <1>; +- device_type = "ethernet-phy"; +- }; +- +- phy1: ethernet-phy@3 { +- reg = <3>; +- device_type = "ethernet-phy"; +- }; +- }; +- +- soc { +- flash@30000000 { +- status = "okay"; +- /* 8MB of flash */ +- reg = <0x30000000 0x00800000>; +- +- partition@0 { +- label = "RedBoot"; +- reg = <0x00000000 0x00020000>; +- read-only; +- }; +- partition@20000 { +- label = "kernel"; +- reg = <0x00020000 0x00100000>; +- }; +- partition@120000 { +- label = "rootfs"; +- reg = <0x00120000 0x006a0000>; +- }; +- partition@7c0000 { +- label = "VCTL"; +- reg = <0x007c0000 0x00010000>; +- read-only; +- }; +- partition@7d0000 { +- label = "cfg"; +- reg = <0x007d0000 0x00010000>; +- read-only; +- }; +- partition@7e0000 { +- label = "FIS"; +- reg = <0x007e0000 0x00010000>; +- read-only; +- }; +- }; +- +- syscon: syscon@40000000 { +- pinctrl { +- /* +- * gpio0agrp cover line 0-4 +- * gpio0bgrp cover line 5 +- */ +- gpio0_default_pins: pinctrl-gpio0 { +- mux { +- function = "gpio0"; +- groups = "gpio0agrp", +- "gpio0bgrp"; +- }; +- }; +- pinctrl-gmii { +- /* This platform use both the ethernet ports */ +- mux { +- function = "gmii"; +- groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; +- }; +- }; +- }; +- }; +- +- gpio0: gpio@4d000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio0_default_pins>; +- }; +- +- pci@50000000 { +- status = "okay"; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = +- <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ +- <0x4800 0 0 2 &pci_intc 1>, +- <0x4800 0 0 3 &pci_intc 2>, +- <0x4800 0 0 4 &pci_intc 3>, +- <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ +- <0x5000 0 0 2 &pci_intc 2>, +- <0x5000 0 0 3 &pci_intc 3>, +- <0x5000 0 0 4 &pci_intc 0>, +- <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ +- <0x5800 0 0 2 &pci_intc 3>, +- <0x5800 0 0 3 &pci_intc 0>, +- <0x5800 0 0 4 &pci_intc 1>, +- <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ +- <0x6000 0 0 2 &pci_intc 0>, +- <0x6000 0 0 3 &pci_intc 1>, +- <0x6000 0 0 4 &pci_intc 2>; +- }; +- +- ethernet@60000000 { +- status = "okay"; +- +- ethernet-port@0 { +- phy-mode = "rgmii"; +- phy-handle = <&phy0>; +- }; +- ethernet-port@1 { +- phy-mode = "rgmii"; +- phy-handle = <&phy1>; +- }; +- }; +- +- usb@68000000 { +- status = "okay"; +- }; +- +- usb@69000000 { +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/gemini.dtsi b/scripts/dtc/include-prefixes/arm/gemini.dtsi +deleted file mode 100644 +index cc053af3c347..000000000000 +--- a/scripts/dtc/include-prefixes/arm/gemini.dtsi ++++ /dev/null +@@ -1,456 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree file for Cortina systems Gemini SoC +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "simple-bus"; +- interrupt-parent = <&intcon>; +- +- flash@30000000 { +- compatible = "cortina,gemini-flash", "cfi-flash"; +- syscon = <&syscon>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pflash_default_pins>; +- bank-width = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- status = "disabled"; +- }; +- +- syscon: syscon@40000000 { +- compatible = "cortina,gemini-syscon", +- "syscon", "simple-mfd"; +- reg = <0x40000000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- +- syscon-reboot { +- compatible = "syscon-reboot"; +- regmap = <&syscon>; +- /* GLOBAL_RESET register */ +- offset = <0x0c>; +- /* RESET_GLOBAL | RESET_CPU1 */ +- mask = <0xC0000000>; +- }; +- +- pinctrl { +- compatible = "cortina,gemini-pinctrl"; +- regmap = <&syscon>; +- /* Hog the DRAM pins */ +- pinctrl-names = "default"; +- pinctrl-0 = <&dram_default_pins>, <&system_default_pins>, +- <&vcontrol_default_pins>; +- +- dram_default_pins: pinctrl-dram { +- mux { +- function = "dram"; +- groups = "dramgrp"; +- }; +- }; +- rtc_default_pins: pinctrl-rtc { +- mux { +- function = "rtc"; +- groups = "rtcgrp"; +- }; +- }; +- power_default_pins: pinctrl-power { +- mux { +- function = "power"; +- groups = "powergrp"; +- }; +- }; +- cir_default_pins: pinctrl-cir { +- mux { +- function = "cir"; +- groups = "cirgrp"; +- }; +- }; +- system_default_pins: pinctrl-system { +- mux { +- function = "system"; +- groups = "systemgrp"; +- }; +- }; +- vcontrol_default_pins: pinctrl-vcontrol { +- mux { +- function = "vcontrol"; +- groups = "vcontrolgrp"; +- }; +- }; +- ice_default_pins: pinctrl-ice { +- mux { +- function = "ice"; +- groups = "icegrp"; +- }; +- }; +- uart_default_pins: pinctrl-uart { +- mux { +- function = "uart"; +- groups = "uartrxtxgrp"; +- }; +- }; +- pflash_default_pins: pinctrl-pflash { +- mux { +- function = "pflash"; +- groups = "pflashgrp"; +- }; +- }; +- usb_default_pins: pinctrl-usb { +- mux { +- function = "usb"; +- groups = "usbgrp"; +- }; +- }; +- gmii_default_pins: pinctrl-gmii { +- /* +- * Only activate GMAC0 by default since +- * GMAC1 will overlap with 8 GPIO lines +- * gpio2a, gpio2b. Overlay groups with +- * "gmii_gmac0_grp", "gmii_gmac1_grp" for +- * both ethernet interfaces. +- */ +- mux { +- function = "gmii"; +- groups = "gmii_gmac0_grp"; +- }; +- }; +- pci_default_pins: pinctrl-pci { +- mux { +- function = "pci"; +- groups = "pcigrp"; +- }; +- }; +- sata_default_pins: pinctrl-sata { +- mux { +- function = "sata"; +- groups = "satagrp"; +- }; +- }; +- /* Activate both groups of pins for this state */ +- sata_and_ide_pins: pinctrl-sata-ide { +- mux0 { +- function = "sata"; +- groups = "satagrp"; +- }; +- mux1 { +- function = "ide"; +- groups = "idegrp"; +- }; +- }; +- tvc_default_pins: pinctrl-tvc { +- mux { +- function = "tvc"; +- groups = "tvcgrp"; +- }; +- }; +- }; +- }; +- +- watchdog@41000000 { +- compatible = "cortina,gemini-watchdog", "faraday,ftwdt010"; +- reg = <0x41000000 0x1000>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; +- resets = <&syscon GEMINI_RESET_WDOG>; +- clocks = <&syscon GEMINI_CLK_APB>; +- clock-names = "PCLK"; +- }; +- +- uart0: serial@42000000 { +- compatible = "ns16550a"; +- reg = <0x42000000 0x100>; +- resets = <&syscon GEMINI_RESET_UART>; +- clocks = <&syscon GEMINI_CLK_UART>; +- interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart_default_pins>; +- reg-shift = <2>; +- }; +- +- timer@43000000 { +- compatible = "faraday,fttmr010"; +- reg = <0x43000000 0x1000>; +- interrupt-parent = <&intcon>; +- interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ +- <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ +- <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ +- resets = <&syscon GEMINI_RESET_TIMER>; +- /* APB clock or RTC clock */ +- clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>; +- clock-names = "PCLK", "EXTCLK"; +- syscon = <&syscon>; +- }; +- +- rtc@45000000 { +- compatible = "cortina,gemini-rtc", "faraday,ftrtc010"; +- reg = <0x45000000 0x100>; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; +- resets = <&syscon GEMINI_RESET_RTC>; +- clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>; +- clock-names = "PCLK", "EXTCLK"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rtc_default_pins>; +- }; +- +- sata: sata@46000000 { +- compatible = "cortina,gemini-sata-bridge"; +- reg = <0x46000000 0x100>; +- resets = <&syscon GEMINI_RESET_SATA0>, +- <&syscon GEMINI_RESET_SATA1>; +- reset-names = "sata0", "sata1"; +- clocks = <&syscon GEMINI_CLK_GATE_SATA0>, +- <&syscon GEMINI_CLK_GATE_SATA1>; +- clock-names = "SATA0_PCLK", "SATA1_PCLK"; +- /* +- * This defines the special "ide" state that needs +- * to be explicitly enabled to enable the IDE pins, +- * as these pins are normally used for other things. +- */ +- pinctrl-names = "default", "ide"; +- pinctrl-0 = <&sata_default_pins>; +- pinctrl-1 = <&sata_and_ide_pins>; +- syscon = <&syscon>; +- status = "disabled"; +- }; +- +- intcon: interrupt-controller@48000000 { +- compatible = "faraday,ftintc010"; +- reg = <0x48000000 0x1000>; +- resets = <&syscon GEMINI_RESET_INTCON0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- power-controller@4b000000 { +- compatible = "cortina,gemini-power-controller"; +- reg = <0x4b000000 0x100>; +- interrupts = <26 IRQ_TYPE_EDGE_RISING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&power_default_pins>; +- }; +- +- gpio0: gpio@4d000000 { +- compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; +- reg = <0x4d000000 0x100>; +- interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; +- resets = <&syscon GEMINI_RESET_GPIO0>; +- clocks = <&syscon GEMINI_CLK_APB>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio@4e000000 { +- compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; +- reg = <0x4e000000 0x100>; +- interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; +- resets = <&syscon GEMINI_RESET_GPIO1>; +- clocks = <&syscon GEMINI_CLK_APB>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@4f000000 { +- compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; +- reg = <0x4f000000 0x100>; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; +- resets = <&syscon GEMINI_RESET_GPIO2>; +- clocks = <&syscon GEMINI_CLK_APB>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pci@50000000 { +- compatible = "cortina,gemini-pci", "faraday,ftpci100"; +- /* +- * The first 256 bytes in the IO range is actually used +- * to configure the host bridge. +- */ +- reg = <0x50000000 0x100>; +- resets = <&syscon GEMINI_RESET_PCI>; +- clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>; +- clock-names = "PCLK", "PCICLK"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pci_default_pins>; +- device_type = "pci"; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- status = "disabled"; +- +- bus-range = <0x00 0xff>; +- /* PCI ranges mappings */ +- ranges = +- /* 1MiB I/O space 0x50000000-0x500fffff */ +- <0x01000000 0 0 0x50000000 0 0x00100000>, +- /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */ +- <0x02000000 0 0x58000000 0x58000000 0 0x08000000>; +- +- /* DMA ranges */ +- dma-ranges = +- /* 128MiB at 0x00000000-0x07ffffff */ +- <0x02000000 0 0x00000000 0x00000000 0 0x08000000>, +- /* 64MiB at 0x00000000-0x03ffffff */ +- <0x02000000 0 0x00000000 0x00000000 0 0x04000000>, +- /* 64MiB at 0x00000000-0x03ffffff */ +- <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; +- +- /* +- * This PCI host bridge variant has a cascaded interrupt +- * controller embedded in the host bridge. +- */ +- pci_intc: interrupt-controller { +- interrupt-parent = <&intcon>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- }; +- }; +- +- ethernet@60000000 { +- compatible = "cortina,gemini-ethernet"; +- reg = <0x60000000 0x4000>, /* Global registers, queue */ +- <0x60004000 0x2000>, /* V-bit */ +- <0x60006000 0x2000>; /* A-bit */ +- pinctrl-names = "default"; +- pinctrl-0 = <&gmii_default_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gmac0: ethernet-port@0 { +- compatible = "cortina,gemini-ethernet-port"; +- reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */ +- <0x6000a000 0x2000>; /* Port 0 GMAC */ +- interrupt-parent = <&intcon>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; +- resets = <&syscon GEMINI_RESET_GMAC0>; +- clocks = <&syscon GEMINI_CLK_GATE_GMAC0>; +- clock-names = "PCLK"; +- }; +- +- gmac1: ethernet-port@1 { +- compatible = "cortina,gemini-ethernet-port"; +- reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */ +- <0x6000e000 0x2000>; /* Port 1 GMAC */ +- interrupt-parent = <&intcon>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; +- resets = <&syscon GEMINI_RESET_GMAC1>; +- clocks = <&syscon GEMINI_CLK_GATE_GMAC1>; +- clock-names = "PCLK"; +- }; +- }; +- +- crypto: crypto@62000000 { +- compatible = "cortina,sl3516-crypto"; +- reg = <0x62000000 0x10000>; +- interrupts = <7 IRQ_TYPE_EDGE_RISING>; +- resets = <&syscon GEMINI_RESET_SECURITY>; +- clocks = <&syscon GEMINI_CLK_GATE_SECURITY>; +- }; +- +- ide@63000000 { +- compatible = "cortina,gemini-pata", "faraday,ftide010"; +- reg = <0x63000000 0x1000>; +- interrupts = <4 IRQ_TYPE_EDGE_RISING>; +- resets = <&syscon GEMINI_RESET_IDE>; +- clocks = <&syscon GEMINI_CLK_GATE_IDE>; +- clock-names = "PCLK"; +- sata = <&sata>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- ide@63400000 { +- compatible = "cortina,gemini-pata", "faraday,ftide010"; +- reg = <0x63400000 0x1000>; +- interrupts = <5 IRQ_TYPE_EDGE_RISING>; +- resets = <&syscon GEMINI_RESET_IDE>; +- clocks = <&syscon GEMINI_CLK_GATE_IDE>; +- clock-names = "PCLK"; +- sata = <&sata>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- dma-controller@67000000 { +- compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell"; +- /* Faraday Technology FTDMAC020 variant */ +- arm,primecell-periphid = <0x0003b080>; +- reg = <0x67000000 0x1000>; +- interrupts = <9 IRQ_TYPE_EDGE_RISING>; +- resets = <&syscon GEMINI_RESET_DMAC>; +- clocks = <&syscon GEMINI_CLK_AHB>; +- clock-names = "apb_pclk"; +- /* Bus interface AHB1 (AHB0) is totally tilted */ +- lli-bus-interface-ahb2; +- mem-bus-interface-ahb2; +- memcpy-burst-size = <256>; +- memcpy-bus-width = <32>; +- #dma-cells = <2>; +- }; +- +- display-controller@6a000000 { +- compatible = "cortina,gemini-tvc", "faraday,tve200"; +- reg = <0x6a000000 0x1000>; +- interrupts = <13 IRQ_TYPE_EDGE_RISING>; +- resets = <&syscon GEMINI_RESET_TVC>; +- clocks = <&syscon GEMINI_CLK_GATE_TVC>, +- <&syscon GEMINI_CLK_TVC>; +- clock-names = "PCLK", "TVE"; +- pinctrl-names = "default"; +- pinctrl-0 = <&tvc_default_pins>; +- status = "disabled"; +- }; +- +- usb@68000000 { +- compatible = "cortina,gemini-usb", "faraday,fotg210"; +- reg = <0x68000000 0x1000>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; +- resets = <&syscon GEMINI_RESET_USB0>; +- clocks = <&syscon GEMINI_CLK_GATE_USB0>; +- clock-names = "PCLK"; +- /* +- * This will claim pins for USB0 and USB1 at the same +- * time as they are using some common pins. If you for +- * some reason have a system using USB1 at 96000000 but +- * NOT using USB0 at 68000000 you wll have to add the +- * usb_default_pins to the USB controller at 96000000 +- * in your .dts for the board. +- */ +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_default_pins>; +- syscon = <&syscon>; +- status = "disabled"; +- }; +- +- usb@69000000 { +- compatible = "cortina,gemini-usb", "faraday,fotg210"; +- reg = <0x69000000 0x1000>; +- interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; +- resets = <&syscon GEMINI_RESET_USB1>; +- clocks = <&syscon GEMINI_CLK_GATE_USB1>; +- clock-names = "PCLK"; +- syscon = <&syscon>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/gr-peach-audiocamerashield.dtsi b/scripts/dtc/include-prefixes/arm/gr-peach-audiocamerashield.dtsi +deleted file mode 100644 +index 8d77579807ec..000000000000 +--- a/scripts/dtc/include-prefixes/arm/gr-peach-audiocamerashield.dtsi ++++ /dev/null +@@ -1,75 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the GR-Peach audiocamera shield expansion board +- * +- * Copyright (C) 2017 Jacopo Mondi +- */ +- +-#include "r7s72100.dtsi" +-#include +-#include +- +-/ { +- /* On-board camera clock. */ +- camera_clk: camera_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- }; +-}; +- +-&pinctrl { +- i2c1_pins: i2c1 { +- /* P1_2 as SCL; P1_3 as SDA */ +- pinmux = , ; +- }; +- +- vio_pins: vio { +- /* CEU pins: VIO_D[0-10], VIO_VD, VIO_HD, VIO_CLK */ +- pinmux = , /* VIO_VD */ +- , /* VIO_HD */ +- , /* VIO_D0 */ +- , /* VIO_D1 */ +- , /* VIO_D2 */ +- , /* VIO_D3 */ +- , /* VIO_D4 */ +- , /* VIO_D5 */ +- , /* VIO_D6 */ +- , /* VIO_D7 */ +- ; /* VIO_CLK */ +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- +- status = "okay"; +- clock-frequency = <100000>; +- +- camera@48 { +- compatible = "aptina,mt9v111"; +- reg = <0x48>; +- +- clocks = <&camera_clk>; +- +- port { +- mt9v111_out: endpoint { +- remote-endpoint = <&ceu_in>; +- }; +- }; +- }; +-}; +- +-&ceu { +- pinctrl-names = "default"; +- pinctrl-0 = <&vio_pins>; +- +- status = "okay"; +- +- port { +- ceu_in: endpoint { +- remote-endpoint = <&mt9v111_out>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/hi3519-demb.dts b/scripts/dtc/include-prefixes/arm/hi3519-demb.dts +deleted file mode 100644 +index f473fa22e9ce..000000000000 +--- a/scripts/dtc/include-prefixes/arm/hi3519-demb.dts ++++ /dev/null +@@ -1,29 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. +- */ +- +-/dts-v1/; +-#include "hi3519.dtsi" +- +-/ { +- model = "HiSilicon HI3519 DEMO Board"; +- compatible = "hisilicon,hi3519"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&dual_timer0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/hi3519.dtsi b/scripts/dtc/include-prefixes/arm/hi3519.dtsi +deleted file mode 100644 +index c524c854d319..000000000000 +--- a/scripts/dtc/include-prefixes/arm/hi3519.dtsi ++++ /dev/null +@@ -1,174 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. +- */ +- +-#include +-#include +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- chosen { }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0>; +- }; +- }; +- +- gic: interrupt-controller@10300000 { +- compatible = "arm,cortex-a7-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x10301000 0x1000>, <0x10302000 0x1000>; +- }; +- +- clk_3m: clk_3m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <3000000>; +- }; +- +- crg: clock-reset-controller@12010000 { +- compatible = "hisilicon,hi3519-crg"; +- #clock-cells = <1>; +- #reset-cells = <2>; +- reg = <0x12010000 0x10000>; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- ranges; +- +- uart0: serial@12100000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x12100000 0x1000>; +- interrupts = ; +- clocks = <&crg HI3519_UART0_CLK>, <&crg HI3519_UART0_CLK>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disable"; +- }; +- +- uart1: serial@12101000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x12101000 0x1000>; +- interrupts = ; +- clocks = <&crg HI3519_UART1_CLK>, <&crg HI3519_UART1_CLK>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disable"; +- }; +- +- uart2: serial@12102000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x12102000 0x1000>; +- interrupts = ; +- clocks = <&crg HI3519_UART2_CLK>, <&crg HI3519_UART2_CLK>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disable"; +- }; +- +- uart3: serial@12103000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x12103000 0x1000>; +- interrupts = ; +- clocks = <&crg HI3519_UART3_CLK>, <&crg HI3519_UART3_CLK>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disable"; +- }; +- +- uart4: serial@12104000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x12104000 0x1000>; +- interrupts = ; +- clocks = <&crg HI3519_UART4_CLK>, <&crg HI3519_UART4_CLK>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disable"; +- }; +- +- dual_timer0: timer@12000000 { +- compatible = "arm,sp804", "arm,primecell"; +- interrupts = , +- ; +- reg = <0x12000000 0x1000>; +- clocks = <&clk_3m>; +- clock-names = "apb_pclk"; +- status = "disable"; +- }; +- +- dual_timer1: timer@12001000 { +- compatible = "arm,sp804", "arm,primecell"; +- interrupts = , +- ; +- reg = <0x12001000 0x1000>; +- clocks = <&clk_3m>; +- clock-names = "apb_pclk"; +- status = "disable"; +- }; +- +- dual_timer2: timer@12002000 { +- compatible = "arm,sp804", "arm,primecell"; +- interrupts = , +- ; +- reg = <0x12002000 0x1000>; +- clocks = <&clk_3m>; +- clock-names = "apb_pclk"; +- status = "disable"; +- }; +- +- spi_bus0: spi@12120000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x12120000 0x1000>; +- interrupts = ; +- clocks = <&crg HI3519_SPI0_CLK>, <&crg HI3519_SPI0_CLK>; +- clock-names = "sspclk", "apb_pclk"; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disable"; +- }; +- +- spi_bus1: spi@12121000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x12121000 0x1000>; +- interrupts = ; +- clocks = <&crg HI3519_SPI1_CLK>, <&crg HI3519_SPI1_CLK>; +- clock-names = "sspclk", "apb_pclk"; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disable"; +- }; +- +- spi_bus2: spi@12122000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x12122000 0x1000>; +- interrupts = ; +- clocks = <&crg HI3519_SPI2_CLK>, <&crg HI3519_SPI2_CLK>; +- clock-names = "sspclk", "apb_pclk"; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disable"; +- }; +- +- sysctrl: system-controller@12020000 { +- compatible = "hisilicon,hi3519-sysctrl", "syscon"; +- reg = <0x12020000 0x1000>; +- }; +- +- reboot { +- compatible = "syscon-reboot"; +- regmap = <&sysctrl>; +- offset = <0x4>; +- mask = <0xdeadbeef>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/hi3620-hi4511.dts b/scripts/dtc/include-prefixes/arm/hi3620-hi4511.dts +deleted file mode 100644 +index ce356c469e1e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/hi3620-hi4511.dts ++++ /dev/null +@@ -1,647 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012-2013 Linaro Ltd. +- * Author: Haojian Zhuang +- */ +- +-/dts-v1/; +- +-#include "hi3620.dtsi" +- +-/ { +- model = "Hisilicon Hi4511 Development Board"; +- compatible = "hisilicon,hi3620-hi4511"; +- +- chosen { +- bootargs = "root=/dev/ram0"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x20000000>; +- }; +- +- amba-bus { +- dual_timer0: dual_timer@800000 { +- status = "ok"; +- }; +- +- uart0: serial@b00000 { /* console */ +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; +- pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>; +- status = "ok"; +- }; +- +- uart1: serial@b01000 { /* modem */ +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; +- pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>; +- status = "ok"; +- }; +- +- uart2: serial@b02000 { /* audience */ +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; +- pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>; +- status = "ok"; +- }; +- +- uart3: serial@b03000 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; +- pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>; +- status = "ok"; +- }; +- +- uart4: serial@b04000 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; +- pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>; +- status = "ok"; +- }; +- +- pmx0: pinmux@803000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&board_pmx_pins>; +- +- board_pmx_pins: board_pmx_pins { +- pinctrl-single,pins = < +- 0x008 0x0 /* GPIO -- eFUSE_DOUT */ +- 0x100 0x0 /* USIM_CLK & USIM_DATA (IOMG63) */ +- >; +- }; +- uart0_pmx_func: uart0_pmx_func { +- pinctrl-single,pins = < +- 0x0f0 0x0 +- 0x0f4 0x0 /* UART0_RX & UART0_TX */ +- >; +- }; +- uart0_pmx_idle: uart0_pmx_idle { +- pinctrl-single,pins = < +- /*0x0f0 0x1*/ /* UART0_CTS & UART0_RTS */ +- 0x0f4 0x1 /* UART0_RX & UART0_TX */ +- >; +- }; +- uart1_pmx_func: uart1_pmx_func { +- pinctrl-single,pins = < +- 0x0f8 0x0 /* UART1_CTS & UART1_RTS (IOMG61) */ +- 0x0fc 0x0 /* UART1_RX & UART1_TX (IOMG62) */ +- >; +- }; +- uart1_pmx_idle: uart1_pmx_idle { +- pinctrl-single,pins = < +- 0x0f8 0x1 /* GPIO (IOMG61) */ +- 0x0fc 0x1 /* GPIO (IOMG62) */ +- >; +- }; +- uart2_pmx_func: uart2_pmx_func { +- pinctrl-single,pins = < +- 0x104 0x2 /* UART2_RXD (IOMG96) */ +- 0x108 0x2 /* UART2_TXD (IOMG64) */ +- >; +- }; +- uart2_pmx_idle: uart2_pmx_idle { +- pinctrl-single,pins = < +- 0x104 0x1 /* GPIO (IOMG96) */ +- 0x108 0x1 /* GPIO (IOMG64) */ +- >; +- }; +- uart3_pmx_func: uart3_pmx_func { +- pinctrl-single,pins = < +- 0x160 0x2 /* UART3_CTS & UART3_RTS (IOMG85) */ +- 0x164 0x2 /* UART3_RXD & UART3_TXD (IOMG86) */ +- >; +- }; +- uart3_pmx_idle: uart3_pmx_idle { +- pinctrl-single,pins = < +- 0x160 0x1 /* GPIO (IOMG85) */ +- 0x164 0x1 /* GPIO (IOMG86) */ +- >; +- }; +- uart4_pmx_func: uart4_pmx_func { +- pinctrl-single,pins = < +- 0x168 0x0 /* UART4_CTS & UART4_RTS (IOMG87) */ +- 0x16c 0x0 /* UART4_RXD (IOMG88) */ +- 0x170 0x0 /* UART4_TXD (IOMG93) */ +- >; +- }; +- uart4_pmx_idle: uart4_pmx_idle { +- pinctrl-single,pins = < +- 0x168 0x1 /* GPIO (IOMG87) */ +- 0x16c 0x1 /* GPIO (IOMG88) */ +- 0x170 0x1 /* GPIO (IOMG93) */ +- >; +- }; +- i2c0_pmx_func: i2c0_pmx_func { +- pinctrl-single,pins = < +- 0x0b4 0x0 /* I2C0_SCL & I2C0_SDA (IOMG45) */ +- >; +- }; +- i2c0_pmx_idle: i2c0_pmx_idle { +- pinctrl-single,pins = < +- 0x0b4 0x1 /* GPIO (IOMG45) */ +- >; +- }; +- i2c1_pmx_func: i2c1_pmx_func { +- pinctrl-single,pins = < +- 0x0b8 0x0 /* I2C1_SCL & I2C1_SDA (IOMG46) */ +- >; +- }; +- i2c1_pmx_idle: i2c1_pmx_idle { +- pinctrl-single,pins = < +- 0x0b8 0x1 /* GPIO (IOMG46) */ +- >; +- }; +- i2c2_pmx_func: i2c2_pmx_func { +- pinctrl-single,pins = < +- 0x068 0x0 /* I2C2_SCL (IOMG26) */ +- 0x06c 0x0 /* I2C2_SDA (IOMG27) */ +- >; +- }; +- i2c2_pmx_idle: i2c2_pmx_idle { +- pinctrl-single,pins = < +- 0x068 0x1 /* GPIO (IOMG26) */ +- 0x06c 0x1 /* GPIO (IOMG27) */ +- >; +- }; +- i2c3_pmx_func: i2c3_pmx_func { +- pinctrl-single,pins = < +- 0x050 0x2 /* I2C3_SCL (IOMG20) */ +- 0x054 0x2 /* I2C3_SDA (IOMG21) */ +- >; +- }; +- i2c3_pmx_idle: i2c3_pmx_idle { +- pinctrl-single,pins = < +- 0x050 0x1 /* GPIO (IOMG20) */ +- 0x054 0x1 /* GPIO (IOMG21) */ +- >; +- }; +- spi0_pmx_func: spi0_pmx_func { +- pinctrl-single,pins = < +- 0x0d4 0x0 /* SPI0_CLK/SPI0_DI/SPI0_DO (IOMG53) */ +- 0x0d8 0x0 /* SPI0_CS0 (IOMG54) */ +- 0x0dc 0x0 /* SPI0_CS1 (IOMG55) */ +- 0x0e0 0x0 /* SPI0_CS2 (IOMG56) */ +- 0x0e4 0x0 /* SPI0_CS3 (IOMG57) */ +- >; +- }; +- spi0_pmx_idle: spi0_pmx_idle { +- pinctrl-single,pins = < +- 0x0d4 0x1 /* GPIO (IOMG53) */ +- 0x0d8 0x1 /* GPIO (IOMG54) */ +- 0x0dc 0x1 /* GPIO (IOMG55) */ +- 0x0e0 0x1 /* GPIO (IOMG56) */ +- 0x0e4 0x1 /* GPIO (IOMG57) */ +- >; +- }; +- spi1_pmx_func: spi1_pmx_func { +- pinctrl-single,pins = < +- 0x184 0x0 /* SPI1_CLK/SPI1_DI (IOMG98) */ +- 0x0e8 0x0 /* SPI1_DO (IOMG58) */ +- 0x0ec 0x0 /* SPI1_CS (IOMG95) */ +- >; +- }; +- spi1_pmx_idle: spi1_pmx_idle { +- pinctrl-single,pins = < +- 0x184 0x1 /* GPIO (IOMG98) */ +- 0x0e8 0x1 /* GPIO (IOMG58) */ +- 0x0ec 0x1 /* GPIO (IOMG95) */ +- >; +- }; +- kpc_pmx_func: kpc_pmx_func { +- pinctrl-single,pins = < +- 0x12c 0x0 /* KEY_IN0 (IOMG73) */ +- 0x130 0x0 /* KEY_IN1 (IOMG74) */ +- 0x134 0x0 /* KEY_IN2 (IOMG75) */ +- 0x10c 0x0 /* KEY_OUT0 (IOMG65) */ +- 0x110 0x0 /* KEY_OUT1 (IOMG66) */ +- 0x114 0x0 /* KEY_OUT2 (IOMG67) */ +- >; +- }; +- kpc_pmx_idle: kpc_pmx_idle { +- pinctrl-single,pins = < +- 0x12c 0x1 /* GPIO (IOMG73) */ +- 0x130 0x1 /* GPIO (IOMG74) */ +- 0x134 0x1 /* GPIO (IOMG75) */ +- 0x10c 0x1 /* GPIO (IOMG65) */ +- 0x110 0x1 /* GPIO (IOMG66) */ +- 0x114 0x1 /* GPIO (IOMG67) */ +- >; +- }; +- gpio_key_func: gpio_key_func { +- pinctrl-single,pins = < +- 0x10c 0x1 /* KEY_OUT0/GPIO (IOMG65) */ +- 0x130 0x1 /* KEY_IN1/GPIO (IOMG74) */ +- >; +- }; +- emmc_pmx_func: emmc_pmx_func { +- pinctrl-single,pins = < +- 0x030 0x2 /* eMMC_CMD/eMMC_CLK (IOMG12) */ +- 0x018 0x0 /* NAND_CS3_N (IOMG6) */ +- 0x024 0x0 /* NAND_BUSY2_N (IOMG8) */ +- 0x028 0x0 /* NAND_BUSY3_N (IOMG9) */ +- 0x02c 0x2 /* eMMC_DATA[0:7] (IOMG10) */ +- >; +- }; +- emmc_pmx_idle: emmc_pmx_idle { +- pinctrl-single,pins = < +- 0x030 0x0 /* GPIO (IOMG12) */ +- 0x018 0x1 /* GPIO (IOMG6) */ +- 0x024 0x1 /* GPIO (IOMG8) */ +- 0x028 0x1 /* GPIO (IOMG9) */ +- 0x02c 0x1 /* GPIO (IOMG10) */ +- >; +- }; +- sd_pmx_func: sd_pmx_func { +- pinctrl-single,pins = < +- 0x0bc 0x0 /* SD_CLK/SD_CMD/SD_DATA0/SD_DATA1/SD_DATA2 (IOMG47) */ +- 0x0c0 0x0 /* SD_DATA3 (IOMG48) */ +- >; +- }; +- sd_pmx_idle: sd_pmx_idle { +- pinctrl-single,pins = < +- 0x0bc 0x1 /* GPIO (IOMG47) */ +- 0x0c0 0x1 /* GPIO (IOMG48) */ +- >; +- }; +- nand_pmx_func: nand_pmx_func { +- pinctrl-single,pins = < +- 0x00c 0x0 /* NAND_ALE/NAND_CLE/.../NAND_DATA[0:7] (IOMG3) */ +- 0x010 0x0 /* NAND_CS1_N (IOMG4) */ +- 0x014 0x0 /* NAND_CS2_N (IOMG5) */ +- 0x018 0x0 /* NAND_CS3_N (IOMG6) */ +- 0x01c 0x0 /* NAND_BUSY0_N (IOMG94) */ +- 0x020 0x0 /* NAND_BUSY1_N (IOMG7) */ +- 0x024 0x0 /* NAND_BUSY2_N (IOMG8) */ +- 0x028 0x0 /* NAND_BUSY3_N (IOMG9) */ +- 0x02c 0x0 /* NAND_DATA[8:15] (IOMG10) */ +- >; +- }; +- nand_pmx_idle: nand_pmx_idle { +- pinctrl-single,pins = < +- 0x00c 0x1 /* GPIO (IOMG3) */ +- 0x010 0x1 /* GPIO (IOMG4) */ +- 0x014 0x1 /* GPIO (IOMG5) */ +- 0x018 0x1 /* GPIO (IOMG6) */ +- 0x01c 0x1 /* GPIO (IOMG94) */ +- 0x020 0x1 /* GPIO (IOMG7) */ +- 0x024 0x1 /* GPIO (IOMG8) */ +- 0x028 0x1 /* GPIO (IOMG9) */ +- 0x02c 0x1 /* GPIO (IOMG10) */ +- >; +- }; +- sdio_pmx_func: sdio_pmx_func { +- pinctrl-single,pins = < +- 0x0c4 0x0 /* SDIO_CLK/SDIO_CMD/SDIO_DATA[0:3] (IOMG49) */ +- >; +- }; +- sdio_pmx_idle: sdio_pmx_idle { +- pinctrl-single,pins = < +- 0x0c4 0x1 /* GPIO (IOMG49) */ +- >; +- }; +- audio_out_pmx_func: audio_out_pmx_func { +- pinctrl-single,pins = < +- 0x0f0 0x1 /* GPIO (IOMG59), audio spk & earphone */ +- >; +- }; +- }; +- +- pmx1: pinmux@803800 { +- pinctrl-names = "default"; +- pinctrl-0 = < &board_pu_pins &board_pd_pins &board_pd_ps_pins +- &board_np_pins &board_ps_pins &kpc_cfg_func +- &audio_out_cfg_func>; +- board_pu_pins: board_pu_pins { +- pinctrl-single,pins = < +- 0x014 0 /* GPIO_158 (IOCFG2) */ +- 0x018 0 /* GPIO_159 (IOCFG3) */ +- 0x01c 0 /* BOOT_MODE0 (IOCFG4) */ +- 0x020 0 /* BOOT_MODE1 (IOCFG5) */ +- >; +- pinctrl-single,bias-pulldown = <0 2 0 2>; +- pinctrl-single,bias-pullup = <1 1 0 1>; +- }; +- board_pd_pins: board_pd_pins { +- pinctrl-single,pins = < +- 0x038 0 /* eFUSE_DOUT (IOCFG11) */ +- 0x150 0 /* ISP_GPIO8 (IOCFG93) */ +- 0x154 0 /* ISP_GPIO9 (IOCFG94) */ +- >; +- pinctrl-single,bias-pulldown = <2 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- }; +- board_pd_ps_pins: board_pd_ps_pins { +- pinctrl-single,pins = < +- 0x2d8 0 /* CLK_OUT0 (IOCFG190) */ +- 0x004 0 /* PMU_SPI_DATA (IOCFG192) */ +- >; +- pinctrl-single,bias-pulldown = <2 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- pinctrl-single,drive-strength = <0x30 0xf0>; +- }; +- board_np_pins: board_np_pins { +- pinctrl-single,pins = < +- 0x24c 0 /* KEYPAD_OUT7 (IOCFG155) */ +- >; +- pinctrl-single,bias-pulldown = <0 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- }; +- board_ps_pins: board_ps_pins { +- pinctrl-single,pins = < +- 0x000 0 /* PMU_SPI_CLK (IOCFG191) */ +- 0x008 0 /* PMU_SPI_CS_N (IOCFG193) */ +- >; +- pinctrl-single,drive-strength = <0x30 0xf0>; +- }; +- uart0_cfg_func: uart0_cfg_func { +- pinctrl-single,pins = < +- 0x208 0 /* UART0_RXD (IOCFG138) */ +- 0x20c 0 /* UART0_TXD (IOCFG139) */ +- >; +- pinctrl-single,bias-pulldown = <0 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- }; +- uart0_cfg_idle: uart0_cfg_idle { +- pinctrl-single,pins = < +- 0x208 0 /* UART0_RXD (IOCFG138) */ +- 0x20c 0 /* UART0_TXD (IOCFG139) */ +- >; +- pinctrl-single,bias-pulldown = <2 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- }; +- uart1_cfg_func: uart1_cfg_func { +- pinctrl-single,pins = < +- 0x210 0 /* UART1_CTS (IOCFG140) */ +- 0x214 0 /* UART1_RTS (IOCFG141) */ +- 0x218 0 /* UART1_RXD (IOCFG142) */ +- 0x21c 0 /* UART1_TXD (IOCFG143) */ +- >; +- pinctrl-single,bias-pulldown = <0 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- }; +- uart1_cfg_idle: uart1_cfg_idle { +- pinctrl-single,pins = < +- 0x210 0 /* UART1_CTS (IOCFG140) */ +- 0x214 0 /* UART1_RTS (IOCFG141) */ +- 0x218 0 /* UART1_RXD (IOCFG142) */ +- 0x21c 0 /* UART1_TXD (IOCFG143) */ +- >; +- pinctrl-single,bias-pulldown = <2 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- }; +- uart2_cfg_func: uart2_cfg_func { +- pinctrl-single,pins = < +- 0x220 0 /* UART2_CTS (IOCFG144) */ +- 0x224 0 /* UART2_RTS (IOCFG145) */ +- 0x228 0 /* UART2_RXD (IOCFG146) */ +- 0x22c 0 /* UART2_TXD (IOCFG147) */ +- >; +- pinctrl-single,bias-pulldown = <0 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- }; +- uart2_cfg_idle: uart2_cfg_idle { +- pinctrl-single,pins = < +- 0x220 0 /* GPIO (IOCFG144) */ +- 0x224 0 /* GPIO (IOCFG145) */ +- 0x228 0 /* GPIO (IOCFG146) */ +- 0x22c 0 /* GPIO (IOCFG147) */ +- >; +- pinctrl-single,bias-pulldown = <2 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- }; +- uart3_cfg_func: uart3_cfg_func { +- pinctrl-single,pins = < +- 0x294 0 /* UART3_CTS (IOCFG173) */ +- 0x298 0 /* UART3_RTS (IOCFG174) */ +- 0x29c 0 /* UART3_RXD (IOCFG175) */ +- 0x2a0 0 /* UART3_TXD (IOCFG176) */ +- >; +- pinctrl-single,bias-pulldown = <0 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- }; +- uart3_cfg_idle: uart3_cfg_idle { +- pinctrl-single,pins = < +- 0x294 0 /* UART3_CTS (IOCFG173) */ +- 0x298 0 /* UART3_RTS (IOCFG174) */ +- 0x29c 0 /* UART3_RXD (IOCFG175) */ +- 0x2a0 0 /* UART3_TXD (IOCFG176) */ +- >; +- pinctrl-single,bias-pulldown = <2 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- }; +- uart4_cfg_func: uart4_cfg_func { +- pinctrl-single,pins = < +- 0x2a4 0 /* UART4_CTS (IOCFG177) */ +- 0x2a8 0 /* UART4_RTS (IOCFG178) */ +- 0x2ac 0 /* UART4_RXD (IOCFG179) */ +- 0x2b0 0 /* UART4_TXD (IOCFG180) */ +- >; +- pinctrl-single,bias-pulldown = <0 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- }; +- i2c0_cfg_func: i2c0_cfg_func { +- pinctrl-single,pins = < +- 0x17c 0 /* I2C0_SCL (IOCFG103) */ +- 0x180 0 /* I2C0_SDA (IOCFG104) */ +- >; +- pinctrl-single,bias-pulldown = <0 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- pinctrl-single,drive-strength = <0x30 0xf0>; +- }; +- i2c1_cfg_func: i2c1_cfg_func { +- pinctrl-single,pins = < +- 0x184 0 /* I2C1_SCL (IOCFG105) */ +- 0x188 0 /* I2C1_SDA (IOCFG106) */ +- >; +- pinctrl-single,bias-pulldown = <0 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- pinctrl-single,drive-strength = <0x30 0xf0>; +- }; +- i2c2_cfg_func: i2c2_cfg_func { +- pinctrl-single,pins = < +- 0x118 0 /* I2C2_SCL (IOCFG79) */ +- 0x11c 0 /* I2C2_SDA (IOCFG80) */ +- >; +- pinctrl-single,bias-pulldown = <0 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- pinctrl-single,drive-strength = <0x30 0xf0>; +- }; +- i2c3_cfg_func: i2c3_cfg_func { +- pinctrl-single,pins = < +- 0x100 0 /* I2C3_SCL (IOCFG73) */ +- 0x104 0 /* I2C3_SDA (IOCFG74) */ +- >; +- pinctrl-single,bias-pulldown = <0 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- pinctrl-single,drive-strength = <0x30 0xf0>; +- }; +- spi0_cfg_func1: spi0_cfg_func1 { +- pinctrl-single,pins = < +- 0x1d4 0 /* SPI0_CLK (IOCFG125) */ +- 0x1d8 0 /* SPI0_DI (IOCFG126) */ +- 0x1dc 0 /* SPI0_DO (IOCFG127) */ +- >; +- pinctrl-single,bias-pulldown = <2 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- pinctrl-single,drive-strength = <0x30 0xf0>; +- }; +- spi0_cfg_func2: spi0_cfg_func2 { +- pinctrl-single,pins = < +- 0x1e0 0 /* SPI0_CS0 (IOCFG128) */ +- 0x1e4 0 /* SPI0_CS1 (IOCFG129) */ +- 0x1e8 0 /* SPI0_CS2 (IOCFG130 */ +- 0x1ec 0 /* SPI0_CS3 (IOCFG131) */ +- >; +- pinctrl-single,bias-pulldown = <0 2 0 2>; +- pinctrl-single,bias-pullup = <1 1 0 1>; +- pinctrl-single,drive-strength = <0x30 0xf0>; +- }; +- spi1_cfg_func1: spi1_cfg_func1 { +- pinctrl-single,pins = < +- 0x1f0 0 /* SPI1_CLK (IOCFG132) */ +- 0x1f4 0 /* SPI1_DI (IOCFG133) */ +- 0x1f8 0 /* SPI1_DO (IOCFG134) */ +- >; +- pinctrl-single,bias-pulldown = <2 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- pinctrl-single,drive-strength = <0x30 0xf0>; +- }; +- spi1_cfg_func2: spi1_cfg_func2 { +- pinctrl-single,pins = < +- 0x1fc 0 /* SPI1_CS (IOCFG135) */ +- >; +- pinctrl-single,bias-pulldown = <0 2 0 2>; +- pinctrl-single,bias-pullup = <1 1 0 1>; +- pinctrl-single,drive-strength = <0x30 0xf0>; +- }; +- kpc_cfg_func: kpc_cfg_func { +- pinctrl-single,pins = < +- 0x250 0 /* KEY_IN0 (IOCFG156) */ +- 0x254 0 /* KEY_IN1 (IOCFG157) */ +- 0x258 0 /* KEY_IN2 (IOCFG158) */ +- 0x230 0 /* KEY_OUT0 (IOCFG148) */ +- 0x234 0 /* KEY_OUT1 (IOCFG149) */ +- 0x238 0 /* KEY_OUT2 (IOCFG150) */ +- >; +- pinctrl-single,bias-pulldown = <2 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- }; +- emmc_cfg_func: emmc_cfg_func { +- pinctrl-single,pins = < +- 0x0ac 0 /* eMMC_CMD (IOCFG40) */ +- 0x0b0 0 /* eMMC_CLK (IOCFG41) */ +- 0x058 0 /* NAND_CS3_N (IOCFG19) */ +- 0x064 0 /* NAND_BUSY2_N (IOCFG22) */ +- 0x068 0 /* NAND_BUSY3_N (IOCFG23) */ +- 0x08c 0 /* NAND_DATA8 (IOCFG32) */ +- 0x090 0 /* NAND_DATA9 (IOCFG33) */ +- 0x094 0 /* NAND_DATA10 (IOCFG34) */ +- 0x098 0 /* NAND_DATA11 (IOCFG35) */ +- 0x09c 0 /* NAND_DATA12 (IOCFG36) */ +- 0x0a0 0 /* NAND_DATA13 (IOCFG37) */ +- 0x0a4 0 /* NAND_DATA14 (IOCFG38) */ +- 0x0a8 0 /* NAND_DATA15 (IOCFG39) */ +- >; +- pinctrl-single,bias-pulldown = <0 2 0 2>; +- pinctrl-single,bias-pullup = <1 1 0 1>; +- pinctrl-single,drive-strength = <0x30 0xf0>; +- }; +- sd_cfg_func1: sd_cfg_func1 { +- pinctrl-single,pins = < +- 0x18c 0 /* SD_CLK (IOCFG107) */ +- 0x190 0 /* SD_CMD (IOCFG108) */ +- >; +- pinctrl-single,bias-pulldown = <2 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- pinctrl-single,drive-strength = <0x30 0xf0>; +- }; +- sd_cfg_func2: sd_cfg_func2 { +- pinctrl-single,pins = < +- 0x194 0 /* SD_DATA0 (IOCFG109) */ +- 0x198 0 /* SD_DATA1 (IOCFG110) */ +- 0x19c 0 /* SD_DATA2 (IOCFG111) */ +- 0x1a0 0 /* SD_DATA3 (IOCFG112) */ +- >; +- pinctrl-single,bias-pulldown = <2 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- pinctrl-single,drive-strength = <0x70 0xf0>; +- }; +- nand_cfg_func1: nand_cfg_func1 { +- pinctrl-single,pins = < +- 0x03c 0 /* NAND_ALE (IOCFG12) */ +- 0x040 0 /* NAND_CLE (IOCFG13) */ +- 0x06c 0 /* NAND_DATA0 (IOCFG24) */ +- 0x070 0 /* NAND_DATA1 (IOCFG25) */ +- 0x074 0 /* NAND_DATA2 (IOCFG26) */ +- 0x078 0 /* NAND_DATA3 (IOCFG27) */ +- 0x07c 0 /* NAND_DATA4 (IOCFG28) */ +- 0x080 0 /* NAND_DATA5 (IOCFG29) */ +- 0x084 0 /* NAND_DATA6 (IOCFG30) */ +- 0x088 0 /* NAND_DATA7 (IOCFG31) */ +- 0x08c 0 /* NAND_DATA8 (IOCFG32) */ +- 0x090 0 /* NAND_DATA9 (IOCFG33) */ +- 0x094 0 /* NAND_DATA10 (IOCFG34) */ +- 0x098 0 /* NAND_DATA11 (IOCFG35) */ +- 0x09c 0 /* NAND_DATA12 (IOCFG36) */ +- 0x0a0 0 /* NAND_DATA13 (IOCFG37) */ +- 0x0a4 0 /* NAND_DATA14 (IOCFG38) */ +- 0x0a8 0 /* NAND_DATA15 (IOCFG39) */ +- >; +- pinctrl-single,bias-pulldown = <2 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- pinctrl-single,drive-strength = <0x30 0xf0>; +- }; +- nand_cfg_func2: nand_cfg_func2 { +- pinctrl-single,pins = < +- 0x044 0 /* NAND_RE_N (IOCFG14) */ +- 0x048 0 /* NAND_WE_N (IOCFG15) */ +- 0x04c 0 /* NAND_CS0_N (IOCFG16) */ +- 0x050 0 /* NAND_CS1_N (IOCFG17) */ +- 0x054 0 /* NAND_CS2_N (IOCFG18) */ +- 0x058 0 /* NAND_CS3_N (IOCFG19) */ +- 0x05c 0 /* NAND_BUSY0_N (IOCFG20) */ +- 0x060 0 /* NAND_BUSY1_N (IOCFG21) */ +- 0x064 0 /* NAND_BUSY2_N (IOCFG22) */ +- 0x068 0 /* NAND_BUSY3_N (IOCFG23) */ +- >; +- pinctrl-single,bias-pulldown = <0 2 0 2>; +- pinctrl-single,bias-pullup = <1 1 0 1>; +- pinctrl-single,drive-strength = <0x30 0xf0>; +- }; +- sdio_cfg_func: sdio_cfg_func { +- pinctrl-single,pins = < +- 0x1a4 0 /* SDIO0_CLK (IOCG113) */ +- 0x1a8 0 /* SDIO0_CMD (IOCG114) */ +- 0x1ac 0 /* SDIO0_DATA0 (IOCG115) */ +- 0x1b0 0 /* SDIO0_DATA1 (IOCG116) */ +- 0x1b4 0 /* SDIO0_DATA2 (IOCG117) */ +- 0x1b8 0 /* SDIO0_DATA3 (IOCG118) */ +- >; +- pinctrl-single,bias-pulldown = <2 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- pinctrl-single,drive-strength = <0x30 0xf0>; +- }; +- audio_out_cfg_func: audio_out_cfg_func { +- pinctrl-single,pins = < +- 0x200 0 /* GPIO (IOCFG136) */ +- 0x204 0 /* GPIO (IOCFG137) */ +- >; +- pinctrl-single,bias-pulldown = <2 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- call { +- label = "call"; +- gpios = <&gpio17 2 0>; +- linux,code = <169>; /* KEY_PHONE */ +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/hi3620.dtsi b/scripts/dtc/include-prefixes/arm/hi3620.dtsi +deleted file mode 100644 +index cf48ec14af43..000000000000 +--- a/scripts/dtc/include-prefixes/arm/hi3620.dtsi ++++ /dev/null +@@ -1,577 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * HiSilicon Ltd. Hi3620 SoC +- * +- * Copyright (C) 2012-2013 HiSilicon Ltd. +- * Copyright (C) 2012-2013 Linaro Ltd. +- * +- * Author: Haojian Zhuang +- */ +- +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- }; +- +- pclk: clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- clock-output-names = "apb_pclk"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "hisilicon,hi3620-smp"; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0x0>; +- next-level-cache = <&L2>; +- }; +- +- cpu@1 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <1>; +- next-level-cache = <&L2>; +- }; +- +- cpu@2 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <2>; +- next-level-cache = <&L2>; +- }; +- +- cpu@3 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <3>; +- next-level-cache = <&L2>; +- }; +- }; +- +- amba-bus { +- +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- ranges = <0 0xfc000000 0x2000000>; +- +- L2: cache-controller { +- compatible = "arm,pl310-cache"; +- reg = <0x100000 0x100000>; +- interrupts = <0 15 4>; +- cache-unified; +- cache-level = <2>; +- }; +- +- gic: interrupt-controller@1000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- /* gic dist base, gic cpu base */ +- reg = <0x1000 0x1000>, <0x100 0x100>; +- }; +- +- sysctrl: system-controller@802000 { +- compatible = "hisilicon,sysctrl", "syscon"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x802000 0x1000>; +- reg = <0x802000 0x1000>; +- +- smp-offset = <0x31c>; +- resume-offset = <0x308>; +- reboot-offset = <0x4>; +- +- clock: clock@0 { +- compatible = "hisilicon,hi3620-clock"; +- reg = <0 0x10000>; +- #clock-cells = <1>; +- }; +- }; +- +- dual_timer0: dual_timer@800000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x800000 0x1000>; +- /* timer00 & timer01 */ +- interrupts = <0 0 4>, <0 1 4>; +- clocks = <&clock HI3620_TIMER0_MUX>, +- <&clock HI3620_TIMER1_MUX>, +- <&clock HI3620_TIMER0_MUX>; +- clock-names = "timer0clk", "timer1clk", "apb_pclk"; +- status = "disabled"; +- }; +- +- dual_timer1: dual_timer@801000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x801000 0x1000>; +- /* timer10 & timer11 */ +- interrupts = <0 2 4>, <0 3 4>; +- clocks = <&clock HI3620_TIMER2_MUX>, +- <&clock HI3620_TIMER3_MUX>, +- <&clock HI3620_TIMER2_MUX>; +- clock-names = "timer0clk", "timer1clk", "apb_pclk"; +- status = "disabled"; +- }; +- +- dual_timer2: dual_timer@a01000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0xa01000 0x1000>; +- /* timer20 & timer21 */ +- interrupts = <0 4 4>, <0 5 4>; +- clocks = <&clock HI3620_TIMER4_MUX>, +- <&clock HI3620_TIMER5_MUX>, +- <&clock HI3620_TIMER4_MUX>; +- clock-names = "timer0lck", "timer1clk", "apb_pclk"; +- status = "disabled"; +- }; +- +- dual_timer3: dual_timer@a02000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0xa02000 0x1000>; +- /* timer30 & timer31 */ +- interrupts = <0 6 4>, <0 7 4>; +- clocks = <&clock HI3620_TIMER6_MUX>, +- <&clock HI3620_TIMER7_MUX>, +- <&clock HI3620_TIMER6_MUX>; +- clock-names = "timer0clk", "timer1clk", "apb_pclk"; +- status = "disabled"; +- }; +- +- dual_timer4: dual_timer@a03000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0xa03000 0x1000>; +- /* timer40 & timer41 */ +- interrupts = <0 96 4>, <0 97 4>; +- clocks = <&clock HI3620_TIMER8_MUX>, +- <&clock HI3620_TIMER9_MUX>, +- <&clock HI3620_TIMER8_MUX>; +- clock-names = "timer0clk", "timer1clk", "apb_pclk"; +- status = "disabled"; +- }; +- +- timer5: timer@600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x600 0x20>; +- interrupts = <1 13 0xf01>; +- }; +- +- uart0: serial@b00000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xb00000 0x1000>; +- interrupts = <0 20 4>; +- clocks = <&clock HI3620_UARTCLK0>, <&clock HI3620_UARTCLK0>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- uart1: serial@b01000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xb01000 0x1000>; +- interrupts = <0 21 4>; +- clocks = <&clock HI3620_UARTCLK1>, <&clock HI3620_UARTCLK1>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- uart2: serial@b02000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xb02000 0x1000>; +- interrupts = <0 22 4>; +- clocks = <&clock HI3620_UARTCLK2>, <&clock HI3620_UARTCLK2>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- uart3: serial@b03000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xb03000 0x1000>; +- interrupts = <0 23 4>; +- clocks = <&clock HI3620_UARTCLK3>, <&clock HI3620_UARTCLK3>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- uart4: serial@b04000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xb04000 0x1000>; +- interrupts = <0 24 4>; +- clocks = <&clock HI3620_UARTCLK4>, <&clock HI3620_UARTCLK4>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- gpio0: gpio@806000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x806000 0x1000>; +- interrupts = <0 64 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1 +- &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK0>; +- clock-names = "apb_pclk"; +- }; +- +- gpio1: gpio@807000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x807000 0x1000>; +- interrupts = <0 65 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1 +- &pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1 +- &pmx0 6 5 1 &pmx0 7 6 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK1>; +- clock-names = "apb_pclk"; +- }; +- +- gpio2: gpio@808000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x808000 0x1000>; +- interrupts = <0 66 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1 +- &pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1 +- &pmx0 6 3 1 &pmx0 7 3 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio3: gpio@809000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x809000 0x1000>; +- interrupts = <0 67 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1 +- &pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1 +- &pmx0 6 11 1 &pmx0 7 11 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK3>; +- clock-names = "apb_pclk"; +- }; +- +- gpio4: gpio@80a000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x80a000 0x1000>; +- interrupts = <0 68 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1 +- &pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1 +- &pmx0 6 13 1 &pmx0 7 13 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK4>; +- clock-names = "apb_pclk"; +- }; +- +- gpio5: gpio@80b000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x80b000 0x1000>; +- interrupts = <0 69 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1 +- &pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1 +- &pmx0 6 16 1 &pmx0 7 16 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK5>; +- clock-names = "apb_pclk"; +- }; +- +- gpio6: gpio@80c000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x80c000 0x1000>; +- interrupts = <0 70 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1 +- &pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1 +- &pmx0 6 18 1 &pmx0 7 19 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK6>; +- clock-names = "apb_pclk"; +- }; +- +- gpio7: gpio@80d000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x80d000 0x1000>; +- interrupts = <0 71 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1 +- &pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1 +- &pmx0 6 25 1 &pmx0 7 26 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK7>; +- clock-names = "apb_pclk"; +- }; +- +- gpio8: gpio@80e000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x80e000 0x1000>; +- interrupts = <0 72 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1 +- &pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1 +- &pmx0 6 33 1 &pmx0 7 34 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK8>; +- clock-names = "apb_pclk"; +- }; +- +- gpio9: gpio@80f000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x80f000 0x1000>; +- interrupts = <0 73 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1 +- &pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1 +- &pmx0 6 41 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK9>; +- clock-names = "apb_pclk"; +- }; +- +- gpio10: gpio@810000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x810000 0x1000>; +- interrupts = <0 74 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1 +- &pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK10>; +- clock-names = "apb_pclk"; +- }; +- +- gpio11: gpio@811000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x811000 0x1000>; +- interrupts = <0 75 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1 +- &pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1 +- &pmx0 6 49 1 &pmx0 7 49 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK11>; +- clock-names = "apb_pclk"; +- }; +- +- gpio12: gpio@812000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x812000 0x1000>; +- interrupts = <0 76 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1 +- &pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1 +- &pmx0 6 51 1 &pmx0 7 52 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK12>; +- clock-names = "apb_pclk"; +- }; +- +- gpio13: gpio@813000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x813000 0x1000>; +- interrupts = <0 77 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1 +- &pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1 +- &pmx0 6 55 1 &pmx0 7 56 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK13>; +- clock-names = "apb_pclk"; +- }; +- +- gpio14: gpio@814000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x814000 0x1000>; +- interrupts = <0 78 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1 +- &pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1 +- &pmx0 6 60 1 &pmx0 7 61 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK14>; +- clock-names = "apb_pclk"; +- }; +- +- gpio15: gpio@815000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x815000 0x1000>; +- interrupts = <0 79 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1 +- &pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1 +- &pmx0 6 64 1 &pmx0 7 65 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK15>; +- clock-names = "apb_pclk"; +- }; +- +- gpio16: gpio@816000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x816000 0x1000>; +- interrupts = <0 80 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1 +- &pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1 +- &pmx0 6 72 1 &pmx0 7 73 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK16>; +- clock-names = "apb_pclk"; +- }; +- +- gpio17: gpio@817000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x817000 0x1000>; +- interrupts = <0 81 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1 +- &pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1 +- &pmx0 6 80 1 &pmx0 7 81 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK17>; +- clock-names = "apb_pclk"; +- }; +- +- gpio18: gpio@818000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x818000 0x1000>; +- interrupts = <0 82 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1 +- &pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1 +- &pmx0 6 86 1 &pmx0 7 87 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK18>; +- clock-names = "apb_pclk"; +- }; +- +- gpio19: gpio@819000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x819000 0x1000>; +- interrupts = <0 83 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1 +- &pmx0 3 88 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK19>; +- clock-names = "apb_pclk"; +- }; +- +- gpio20: gpio@81a000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x81a000 0x1000>; +- interrupts = <0 84 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1 +- &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK20>; +- clock-names = "apb_pclk"; +- }; +- +- gpio21: gpio@81b000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x81b000 0x1000>; +- interrupts = <0 85 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&clock HI3620_GPIOCLK21>; +- clock-names = "apb_pclk"; +- }; +- +- pmx0: pinmux@803000 { +- compatible = "pinctrl-single"; +- reg = <0x803000 0x188>; +- #address-cells = <1>; +- #size-cells = <1>; +- #pinctrl-cells = <1>; +- #gpio-range-cells = <3>; +- ranges; +- +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <7>; +- /* pin base, nr pins & gpio function */ +- pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1 +- &range 12 1 0 &range 13 29 1 +- &range 43 1 0 &range 44 49 1 +- &range 94 1 1 &range 96 2 1>; +- +- range: gpio-range { +- #pinctrl-single,gpio-range-cells = <3>; +- }; +- }; +- +- pmx1: pinmux@803800 { +- compatible = "pinconf-single"; +- reg = <0x803800 0x2dc>; +- #address-cells = <1>; +- #size-cells = <1>; +- #pinctrl-cells = <1>; +- ranges; +- +- pinctrl-single,register-width = <32>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/highbank.dts b/scripts/dtc/include-prefixes/arm/highbank.dts +deleted file mode 100644 +index b6b0225a769e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/highbank.dts ++++ /dev/null +@@ -1,158 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright 2011-2012 Calxeda, Inc. +- */ +- +-/dts-v1/; +- +-/* First 4KB has pen for secondary cores. */ +-/memreserve/ 0x00000000 0x0001000; +- +-/ { +- model = "Calxeda Highbank"; +- compatible = "calxeda,highbank"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@900 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <0x900>; +- next-level-cache = <&L2>; +- clocks = <&a9pll>; +- clock-names = "cpu"; +- operating-points = < +- /* kHz ignored */ +- 1300000 1000000 +- 1200000 1000000 +- 1100000 1000000 +- 800000 1000000 +- 400000 1000000 +- 200000 1000000 +- >; +- clock-latency = <100000>; +- }; +- +- cpu@901 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <0x901>; +- next-level-cache = <&L2>; +- clocks = <&a9pll>; +- clock-names = "cpu"; +- operating-points = < +- /* kHz ignored */ +- 1300000 1000000 +- 1200000 1000000 +- 1100000 1000000 +- 800000 1000000 +- 400000 1000000 +- 200000 1000000 +- >; +- clock-latency = <100000>; +- }; +- +- cpu@902 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <0x902>; +- next-level-cache = <&L2>; +- clocks = <&a9pll>; +- clock-names = "cpu"; +- operating-points = < +- /* kHz ignored */ +- 1300000 1000000 +- 1200000 1000000 +- 1100000 1000000 +- 800000 1000000 +- 400000 1000000 +- 200000 1000000 +- >; +- clock-latency = <100000>; +- }; +- +- cpu@903 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <0x903>; +- next-level-cache = <&L2>; +- clocks = <&a9pll>; +- clock-names = "cpu"; +- operating-points = < +- /* kHz ignored */ +- 1300000 1000000 +- 1200000 1000000 +- 1100000 1000000 +- 800000 1000000 +- 400000 1000000 +- 200000 1000000 +- >; +- clock-latency = <100000>; +- }; +- }; +- +- memory@0 { +- name = "memory"; +- device_type = "memory"; +- reg = <0x00000000 0xff900000>; +- }; +- +- soc { +- ranges = <0x00000000 0x00000000 0xffffffff>; +- +- memory-controller@fff00000 { +- compatible = "calxeda,hb-ddr-ctrl"; +- reg = <0xfff00000 0x1000>; +- interrupts = <0 91 4>; +- }; +- +- timer@fff10600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0xfff10600 0x20>; +- interrupts = <1 13 0xf01>; +- clocks = <&a9periphclk>; +- }; +- +- watchdog@fff10620 { +- compatible = "arm,cortex-a9-twd-wdt"; +- reg = <0xfff10620 0x20>; +- interrupts = <1 14 0xf01>; +- clocks = <&a9periphclk>; +- }; +- +- intc: interrupt-controller@fff11000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0xfff11000 0x1000>, +- <0xfff10100 0x100>; +- }; +- +- L2: cache-controller { +- compatible = "arm,pl310-cache"; +- reg = <0xfff12000 0x1000>; +- interrupts = <0 70 4>; +- cache-unified; +- cache-level = <2>; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>; +- }; +- +- +- sregs@fff3c200 { +- compatible = "calxeda,hb-sregs-l2-ecc"; +- reg = <0xfff3c200 0x100>; +- interrupts = <0 71 4>, <0 72 4>; +- }; +- +- }; +-}; +- +-/include/ "ecx-common.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/hip01-ca9x2.dts b/scripts/dtc/include-prefixes/arm/hip01-ca9x2.dts +deleted file mode 100644 +index f3faf247cd61..000000000000 +--- a/scripts/dtc/include-prefixes/arm/hip01-ca9x2.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * HiSilicon Ltd. HiP01 SoC +- * +- * Copyright (C) 2014 HiSilicon Ltd. +- * Copyright (C) 2014 Huawei Ltd. +- * +- * Author: Wang Long +- */ +- +-/dts-v1/; +- +-/* First 8KB reserved for secondary core boot */ +-/memreserve/ 0x80000000 0x00002000; +- +-#include "hip01.dtsi" +- +-/ { +- model = "Hisilicon HIP01 Development Board"; +- compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "hisilicon,hip01-smp"; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <1>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x80000000>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/hip01.dtsi b/scripts/dtc/include-prefixes/arm/hip01.dtsi +deleted file mode 100644 +index e17f36bd9006..000000000000 +--- a/scripts/dtc/include-prefixes/arm/hip01.dtsi ++++ /dev/null +@@ -1,105 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * HiSilicon Ltd. HiP01 SoC +- * +- * Copyright (c) 2014 HiSilicon Ltd. +- * Copyright (c) 2014 Huawei Ltd. +- * +- * Author: Wang Long +- */ +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- gic: interrupt-controller@1e001000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>; +- }; +- +- hisi_refclk144mhz: refclk144mkhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <144000000>; +- clock-output-names = "hisi:refclk144khz"; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- ranges = <0 0x10000000 0x20000000>; +- +- amba-bus { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges; +- +- uart0: serial@10001000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x10001000 0x1000>; +- clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; +- clock-names = "baudclk", "apb_pclk"; +- reg-shift = <2>; +- interrupts = <0 32 4>; +- status = "disabled"; +- }; +- +- uart1: serial@10002000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x10002000 0x1000>; +- clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; +- clock-names = "baudclk", "apb_pclk"; +- reg-shift = <2>; +- interrupts = <0 33 4>; +- status = "disabled"; +- }; +- +- uart2: serial@10003000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x10003000 0x1000>; +- clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; +- clock-names = "baudclk", "apb_pclk"; +- reg-shift = <2>; +- interrupts = <0 34 4>; +- status = "disabled"; +- }; +- +- uart3: serial@10006000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x10006000 0x1000>; +- clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; +- clock-names = "baudclk", "apb_pclk"; +- reg-shift = <2>; +- interrupts = <0 4 4>; +- status = "disabled"; +- }; +- }; +- +- system-controller@10000000 { +- compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; +- reg = <0x10000000 0x1000>; +- reboot-offset = <0x4>; +- }; +- +- global_timer@a000200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0x0a000200 0x100>; +- interrupts = <1 11 0xf04>; +- clocks = <&hisi_refclk144mhz>; +- }; +- +- local_timer@a000600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x0a000600 0x100>; +- interrupts = <1 13 0xf04>; +- clocks = <&hisi_refclk144mhz>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/hip04-d01.dts b/scripts/dtc/include-prefixes/arm/hip04-d01.dts +deleted file mode 100644 +index f5691dbc26d2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/hip04-d01.dts ++++ /dev/null +@@ -1,29 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013-2014 Linaro Ltd. +- * Author: Haojian Zhuang +- */ +- +-/dts-v1/; +- +-#include "hip04.dtsi" +- +-/ { +- /* memory bus is 64-bit */ +- #address-cells = <2>; +- #size-cells = <2>; +- model = "Hisilicon D01 Development Board"; +- compatible = "hisilicon,hip04-d01"; +- +- memory@0,10000000 { +- device_type = "memory"; +- reg = <0x00000000 0x10000000 0x00000000 0xc0000000>, +- <0x00000004 0xc0000000 0x00000003 0x40000000>; +- }; +- +- soc { +- uart0: serial@4007000 { +- status = "ok"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/hip04.dtsi b/scripts/dtc/include-prefixes/arm/hip04.dtsi +deleted file mode 100644 +index 2424cc545c9c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/hip04.dtsi ++++ /dev/null +@@ -1,986 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * HiSilicon Ltd. HiP04 SoC +- * +- * Copyright (C) 2013-2014 HiSilicon Ltd. +- * Copyright (C) 2013-2014 Linaro Ltd. +- * +- * Author: Haojian Zhuang +- */ +- +-/ { +- /* memory bus is 64-bit */ +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- serial0 = &uart0; +- }; +- +- bootwrapper { +- compatible = "hisilicon,hip04-bootwrapper"; +- boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&CPU0>; +- }; +- core1 { +- cpu = <&CPU1>; +- }; +- core2 { +- cpu = <&CPU2>; +- }; +- core3 { +- cpu = <&CPU3>; +- }; +- }; +- cluster1 { +- core0 { +- cpu = <&CPU4>; +- }; +- core1 { +- cpu = <&CPU5>; +- }; +- core2 { +- cpu = <&CPU6>; +- }; +- core3 { +- cpu = <&CPU7>; +- }; +- }; +- cluster2 { +- core0 { +- cpu = <&CPU8>; +- }; +- core1 { +- cpu = <&CPU9>; +- }; +- core2 { +- cpu = <&CPU10>; +- }; +- core3 { +- cpu = <&CPU11>; +- }; +- }; +- cluster3 { +- core0 { +- cpu = <&CPU12>; +- }; +- core1 { +- cpu = <&CPU13>; +- }; +- core2 { +- cpu = <&CPU14>; +- }; +- core3 { +- cpu = <&CPU15>; +- }; +- }; +- }; +- CPU0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0>; +- }; +- CPU1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <1>; +- }; +- CPU2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <2>; +- }; +- CPU3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <3>; +- }; +- CPU4: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x100>; +- }; +- CPU5: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x101>; +- }; +- CPU6: cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x102>; +- }; +- CPU7: cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x103>; +- }; +- CPU8: cpu@200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x200>; +- }; +- CPU9: cpu@201 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x201>; +- }; +- CPU10: cpu@202 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x202>; +- }; +- CPU11: cpu@203 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x203>; +- }; +- CPU12: cpu@300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x300>; +- }; +- CPU13: cpu@301 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x301>; +- }; +- CPU14: cpu@302 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x302>; +- }; +- CPU15: cpu@303 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x303>; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupt-parent = <&gic>; +- interrupts = <1 13 0xf08>, +- <1 14 0xf08>, +- <1 11 0xf08>, +- <1 10 0xf08>; +- }; +- +- clk_50m: clk_50m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- }; +- +- clk_168m: clk_168m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <168000000>; +- }; +- +- clk_375m: clk_375m { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <375000000>; +- }; +- +- soc { +- /* It's a 32-bit SoC. */ +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- ranges = <0 0 0xe0000000 0x10000000>; +- +- gic: interrupt-controller@c01000 { +- compatible = "hisilicon,hip04-intc"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- interrupts = <1 9 0xf04>; +- +- reg = <0xc01000 0x1000>, <0xc02000 0x1000>, +- <0xc04000 0x2000>, <0xc06000 0x2000>; +- }; +- +- sysctrl: sysctrl { +- compatible = "hisilicon,sysctrl", "syscon"; +- reg = <0x3e00000 0x00100000>; +- }; +- +- fabric: fabric { +- compatible = "hisilicon,hip04-fabric"; +- reg = <0x302a000 0x1000>; +- }; +- +- dual_timer0: dual_timer@3000000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x3000000 0x1000>; +- interrupts = <0 224 4>; +- clocks = <&clk_50m>, <&clk_50m>, <&clk_50m>; +- clock-names = "timer0clk", "timer1clk", "apb_pclk"; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a15-pmu"; +- interrupts = <0 64 4>, +- <0 65 4>, +- <0 66 4>, +- <0 67 4>, +- <0 68 4>, +- <0 69 4>, +- <0 70 4>, +- <0 71 4>, +- <0 72 4>, +- <0 73 4>, +- <0 74 4>, +- <0 75 4>, +- <0 76 4>, +- <0 77 4>, +- <0 78 4>, +- <0 79 4>; +- }; +- +- uart0: serial@4007000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x4007000 0x1000>; +- interrupts = <0 381 4>; +- clocks = <&clk_168m>, <&clk_168m>; +- clock-names = "baudclk", "apb_pclk"; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- sata0: sata@a000000 { +- compatible = "hisilicon,hisi-ahci"; +- reg = <0xa000000 0x1000000>; +- interrupts = <0 372 4>; +- }; +- +- }; +- +- etb@0,e3c42000 { +- compatible = "arm,coresight-etb10", "arm,primecell"; +- reg = <0 0xe3c42000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- in-ports { +- port { +- etb0_in_port: endpoint@0 { +- remote-endpoint = <&replicator0_out_port0>; +- }; +- }; +- }; +- }; +- +- etb@0,e3c82000 { +- compatible = "arm,coresight-etb10", "arm,primecell"; +- reg = <0 0xe3c82000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- in-ports { +- port { +- etb1_in_port: endpoint@0 { +- remote-endpoint = <&replicator1_out_port0>; +- }; +- }; +- }; +- }; +- +- etb@0,e3cc2000 { +- compatible = "arm,coresight-etb10", "arm,primecell"; +- reg = <0 0xe3cc2000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- in-ports { +- port { +- etb2_in_port: endpoint@0 { +- remote-endpoint = <&replicator2_out_port0>; +- }; +- }; +- }; +- }; +- +- etb@0,e3d02000 { +- compatible = "arm,coresight-etb10", "arm,primecell"; +- reg = <0 0xe3d02000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- in-ports { +- port { +- etb3_in_port: endpoint@0 { +- remote-endpoint = <&replicator3_out_port0>; +- }; +- }; +- }; +- }; +- +- tpiu@0,e3c05000 { +- compatible = "arm,coresight-tpiu", "arm,primecell"; +- reg = <0 0xe3c05000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- in-ports { +- port { +- tpiu_in_port: endpoint@0 { +- remote-endpoint = <&funnel4_out_port0>; +- }; +- }; +- }; +- }; +- +- replicator0 { +- /* non-configurable replicators don't show up on the +- * AMBA bus. As such no need to add "arm,primecell". +- */ +- compatible = "arm,coresight-static-replicator"; +- +- out-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* replicator output ports */ +- port@0 { +- reg = <0>; +- replicator0_out_port0: endpoint { +- remote-endpoint = <&etb0_in_port>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- replicator0_out_port1: endpoint { +- remote-endpoint = <&funnel4_in_port0>; +- }; +- }; +- }; +- +- in-ports { +- port { +- replicator0_in_port0: endpoint { +- remote-endpoint = <&funnel0_out_port0>; +- }; +- }; +- }; +- }; +- +- replicator1 { +- /* non-configurable replicators don't show up on the +- * AMBA bus. As such no need to add "arm,primecell". +- */ +- compatible = "arm,coresight-static-replicator"; +- +- out-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* replicator output ports */ +- port@0 { +- reg = <0>; +- replicator1_out_port0: endpoint { +- remote-endpoint = <&etb1_in_port>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- replicator1_out_port1: endpoint { +- remote-endpoint = <&funnel4_in_port1>; +- }; +- }; +- }; +- +- in-ports { +- port { +- replicator1_in_port0: endpoint { +- remote-endpoint = <&funnel1_out_port0>; +- }; +- }; +- }; +- }; +- +- replicator2 { +- /* non-configurable replicators don't show up on the +- * AMBA bus. As such no need to add "arm,primecell". +- */ +- compatible = "arm,coresight-static-replicator"; +- +- out-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- replicator2_out_port0: endpoint { +- remote-endpoint = <&etb2_in_port>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- replicator2_out_port1: endpoint { +- remote-endpoint = <&funnel4_in_port2>; +- }; +- }; +- }; +- +- in-ports { +- port { +- replicator2_in_port0: endpoint { +- remote-endpoint = <&funnel2_out_port0>; +- }; +- }; +- }; +- }; +- +- replicator3 { +- /* non-configurable replicators don't show up on the +- * AMBA bus. As such no need to add "arm,primecell". +- */ +- compatible = "arm,coresight-static-replicator"; +- +- out-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- replicator3_out_port0: endpoint { +- remote-endpoint = <&etb3_in_port>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- replicator3_out_port1: endpoint { +- remote-endpoint = <&funnel4_in_port3>; +- }; +- }; +- }; +- +- in-ports { +- port { +- replicator3_in_port0: endpoint { +- remote-endpoint = <&funnel3_out_port0>; +- }; +- }; +- }; +- }; +- +- funnel@0,e3c41000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0xe3c41000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- funnel0_out_port0: endpoint { +- remote-endpoint = +- <&replicator0_in_port0>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- funnel0_in_port0: endpoint { +- remote-endpoint = <&ptm0_out_port>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- funnel0_in_port1: endpoint { +- remote-endpoint = <&ptm1_out_port>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- funnel0_in_port2: endpoint { +- remote-endpoint = <&ptm2_out_port>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- funnel0_in_port3: endpoint { +- remote-endpoint = <&ptm3_out_port>; +- }; +- }; +- }; +- }; +- +- funnel@0,e3c81000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0xe3c81000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- funnel1_out_port0: endpoint { +- remote-endpoint = +- <&replicator1_in_port0>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- funnel1_in_port0: endpoint { +- remote-endpoint = <&ptm4_out_port>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- funnel1_in_port1: endpoint { +- remote-endpoint = <&ptm5_out_port>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- funnel1_in_port2: endpoint { +- remote-endpoint = <&ptm6_out_port>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- funnel1_in_port3: endpoint { +- remote-endpoint = <&ptm7_out_port>; +- }; +- }; +- }; +- }; +- +- funnel@0,e3cc1000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0xe3cc1000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- funnel2_out_port0: endpoint { +- remote-endpoint = +- <&replicator2_in_port0>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- funnel2_in_port0: endpoint { +- remote-endpoint = <&ptm8_out_port>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- funnel2_in_port1: endpoint { +- remote-endpoint = <&ptm9_out_port>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- funnel2_in_port2: endpoint { +- remote-endpoint = <&ptm10_out_port>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- funnel2_in_port3: endpoint { +- remote-endpoint = <&ptm11_out_port>; +- }; +- }; +- }; +- }; +- +- funnel@0,e3d01000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0xe3d01000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- funnel3_out_port0: endpoint { +- remote-endpoint = +- <&replicator3_in_port0>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- funnel3_in_port0: endpoint { +- remote-endpoint = <&ptm12_out_port>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- funnel3_in_port1: endpoint { +- remote-endpoint = <&ptm13_out_port>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- funnel3_in_port2: endpoint { +- remote-endpoint = <&ptm14_out_port>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- funnel3_in_port3: endpoint { +- remote-endpoint = <&ptm15_out_port>; +- }; +- }; +- }; +- }; +- +- funnel@0,e3c04000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0xe3c04000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- funnel4_out_port0: endpoint { +- remote-endpoint = <&tpiu_in_port>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- funnel4_in_port0: endpoint { +- remote-endpoint = +- <&replicator0_out_port1>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- funnel4_in_port1: endpoint { +- remote-endpoint = +- <&replicator1_out_port1>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- funnel4_in_port2: endpoint { +- remote-endpoint = +- <&replicator2_out_port1>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- funnel4_in_port3: endpoint { +- remote-endpoint = +- <&replicator3_out_port1>; +- }; +- }; +- }; +- }; +- +- ptm@0,e3c7c000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0xe3c7c000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- cpu = <&CPU0>; +- out-ports { +- port { +- ptm0_out_port: endpoint { +- remote-endpoint = <&funnel0_in_port0>; +- }; +- }; +- }; +- }; +- +- ptm@0,e3c7d000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0xe3c7d000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- cpu = <&CPU1>; +- out-ports { +- port { +- ptm1_out_port: endpoint { +- remote-endpoint = <&funnel0_in_port1>; +- }; +- }; +- }; +- }; +- +- ptm@0,e3c7e000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0xe3c7e000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- cpu = <&CPU2>; +- out-ports { +- port { +- ptm2_out_port: endpoint { +- remote-endpoint = <&funnel0_in_port2>; +- }; +- }; +- }; +- }; +- +- ptm@0,e3c7f000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0xe3c7f000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- cpu = <&CPU3>; +- out-ports { +- port { +- ptm3_out_port: endpoint { +- remote-endpoint = <&funnel0_in_port3>; +- }; +- }; +- }; +- }; +- +- ptm@0,e3cbc000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0xe3cbc000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- cpu = <&CPU4>; +- out-ports { +- port { +- ptm4_out_port: endpoint { +- remote-endpoint = <&funnel1_in_port0>; +- }; +- }; +- }; +- }; +- +- ptm@0,e3cbd000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0xe3cbd000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- cpu = <&CPU5>; +- out-ports { +- port { +- ptm5_out_port: endpoint { +- remote-endpoint = <&funnel1_in_port1>; +- }; +- }; +- }; +- }; +- +- ptm@0,e3cbe000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0xe3cbe000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- cpu = <&CPU6>; +- out-ports { +- port { +- ptm6_out_port: endpoint { +- remote-endpoint = <&funnel1_in_port2>; +- }; +- }; +- }; +- }; +- +- ptm@0,e3cbf000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0xe3cbf000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- cpu = <&CPU7>; +- out-ports { +- port { +- ptm7_out_port: endpoint { +- remote-endpoint = <&funnel1_in_port3>; +- }; +- }; +- }; +- }; +- +- ptm@0,e3cfc000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0xe3cfc000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- cpu = <&CPU8>; +- out-ports { +- port { +- ptm8_out_port: endpoint { +- remote-endpoint = <&funnel2_in_port0>; +- }; +- }; +- }; +- }; +- +- ptm@0,e3cfd000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0xe3cfd000 0 0x1000>; +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- cpu = <&CPU9>; +- out-ports { +- port { +- ptm9_out_port: endpoint { +- remote-endpoint = <&funnel2_in_port1>; +- }; +- }; +- }; +- }; +- +- ptm@0,e3cfe000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0xe3cfe000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- cpu = <&CPU10>; +- out-ports { +- port { +- ptm10_out_port: endpoint { +- remote-endpoint = <&funnel2_in_port2>; +- }; +- }; +- }; +- }; +- +- ptm@0,e3cff000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0xe3cff000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- cpu = <&CPU11>; +- out-ports { +- port { +- ptm11_out_port: endpoint { +- remote-endpoint = <&funnel2_in_port3>; +- }; +- }; +- }; +- }; +- +- ptm@0,e3d3c000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0xe3d3c000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- cpu = <&CPU12>; +- out-ports { +- port { +- ptm12_out_port: endpoint { +- remote-endpoint = <&funnel3_in_port0>; +- }; +- }; +- }; +- }; +- +- ptm@0,e3d3d000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0xe3d3d000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- cpu = <&CPU13>; +- out-ports { +- port { +- ptm13_out_port: endpoint { +- remote-endpoint = <&funnel3_in_port1>; +- }; +- }; +- }; +- }; +- +- ptm@0,e3d3e000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0xe3d3e000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- cpu = <&CPU14>; +- out-ports { +- port { +- ptm14_out_port: endpoint { +- remote-endpoint = <&funnel3_in_port2>; +- }; +- }; +- }; +- }; +- +- ptm@0,e3d3f000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0xe3d3f000 0 0x1000>; +- +- clocks = <&clk_375m>; +- clock-names = "apb_pclk"; +- cpu = <&CPU15>; +- out-ports { +- port { +- ptm15_out_port: endpoint { +- remote-endpoint = <&funnel3_in_port3>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/hisi-x5hd2-dkb.dts b/scripts/dtc/include-prefixes/arm/hisi-x5hd2-dkb.dts +deleted file mode 100644 +index 7758c19038f0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/hisi-x5hd2-dkb.dts ++++ /dev/null +@@ -1,83 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2013-2014 Linaro Ltd. +- * Copyright (c) 2013-2014 HiSilicon Limited. +- */ +- +-/dts-v1/; +-#include "hisi-x5hd2.dtsi" +- +-/ { +- model = "Hisilicon HIX5HD2 Development Board"; +- compatible = "hisilicon,hix5hd2"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "hisilicon,hix5hd2-smp"; +- +- cpu@0 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <0>; +- next-level-cache = <&l2>; +- }; +- +- cpu@1 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <1>; +- next-level-cache = <&l2>; +- }; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x80000000>; +- }; +-}; +- +-&timer0 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&gmac0 { +- #address-cells = <1>; +- #size-cells = <0>; +- phy-handle = <&phy2>; +- phy-mode = "mii"; +- /* Placeholder, overwritten by bootloader */ +- mac-address = [00 00 00 00 00 00]; +- status = "okay"; +- +- phy2: ethernet-phy@2 { +- reg = <2>; +- }; +-}; +- +-&gmac1 { +- #address-cells = <1>; +- #size-cells = <0>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii"; +- /* Placeholder, overwritten by bootloader */ +- mac-address = [00 00 00 00 00 00]; +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&ahci { +- phys = <&sata_phy>; +- phy-names = "sata-phy"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/hisi-x5hd2.dtsi b/scripts/dtc/include-prefixes/arm/hisi-x5hd2.dtsi +deleted file mode 100644 +index dc991ba2a9fb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/hisi-x5hd2.dtsi ++++ /dev/null +@@ -1,558 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2013-2014 Linaro Ltd. +- * Copyright (c) 2013-2014 HiSilicon Limited. +- */ +- +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- serial0 = &uart0; +- }; +- +- gic: interrupt-controller@f8a01000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- /* gic dist base, gic cpu base */ +- reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- ranges = <0 0xf8000000 0x8000000>; +- +- amba-bus { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges; +- +- timer0: timer@2000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x00002000 0x1000>; +- /* timer00 & timer01 */ +- interrupts = <0 24 4>; +- clocks = <&clock HIX5HD2_FIXED_24M>; +- status = "disabled"; +- }; +- +- timer1: timer@a29000 { +- /* +- * Only used in NORMAL state, not available ins +- * SLOW or DOZE state. +- * The rate is fixed in 24MHz. +- */ +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x00a29000 0x1000>; +- /* timer10 & timer11 */ +- interrupts = <0 25 4>; +- clocks = <&clock HIX5HD2_FIXED_24M>; +- status = "disabled"; +- }; +- +- timer2: timer@a2a000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x00a2a000 0x1000>; +- /* timer20 & timer21 */ +- interrupts = <0 26 4>; +- clocks = <&clock HIX5HD2_FIXED_24M>; +- status = "disabled"; +- }; +- +- timer3: timer@a2b000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x00a2b000 0x1000>; +- /* timer30 & timer31 */ +- interrupts = <0 27 4>; +- clocks = <&clock HIX5HD2_FIXED_24M>; +- status = "disabled"; +- }; +- +- timer4: timer@a81000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x00a81000 0x1000>; +- /* timer30 & timer31 */ +- interrupts = <0 28 4>; +- clocks = <&clock HIX5HD2_FIXED_24M>; +- status = "disabled"; +- }; +- +- uart0: serial@b00000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x00b00000 0x1000>; +- interrupts = <0 49 4>; +- clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- uart1: serial@6000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x00006000 0x1000>; +- interrupts = <0 50 4>; +- clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- uart2: serial@b02000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x00b02000 0x1000>; +- interrupts = <0 51 4>; +- clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- uart3: serial@b03000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x00b03000 0x1000>; +- interrupts = <0 52 4>; +- clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- uart4: serial@b04000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xb04000 0x1000>; +- interrupts = <0 53 4>; +- clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- gpio0: gpio@b20000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xb20000 0x1000>; +- interrupts = <0 108 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&clock HIX5HD2_FIXED_100M>; +- clock-names = "apb_pclk"; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- gpio1: gpio@b21000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xb21000 0x1000>; +- interrupts = <0 109 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&clock HIX5HD2_FIXED_100M>; +- clock-names = "apb_pclk"; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- gpio2: gpio@b22000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xb22000 0x1000>; +- interrupts = <0 110 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&clock HIX5HD2_FIXED_100M>; +- clock-names = "apb_pclk"; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- gpio3: gpio@b23000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xb23000 0x1000>; +- interrupts = <0 111 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&clock HIX5HD2_FIXED_100M>; +- clock-names = "apb_pclk"; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- gpio4: gpio@b24000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xb24000 0x1000>; +- interrupts = <0 112 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&clock HIX5HD2_FIXED_100M>; +- clock-names = "apb_pclk"; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- gpio5: gpio@4000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x004000 0x1000>; +- interrupts = <0 113 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&clock HIX5HD2_FIXED_100M>; +- clock-names = "apb_pclk"; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- gpio6: gpio@b26000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xb26000 0x1000>; +- interrupts = <0 114 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&clock HIX5HD2_FIXED_100M>; +- clock-names = "apb_pclk"; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- gpio7: gpio@b27000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xb27000 0x1000>; +- interrupts = <0 115 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&clock HIX5HD2_FIXED_100M>; +- clock-names = "apb_pclk"; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- gpio8: gpio@b28000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xb28000 0x1000>; +- interrupts = <0 116 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&clock HIX5HD2_FIXED_100M>; +- clock-names = "apb_pclk"; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- gpio9: gpio@b29000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xb29000 0x1000>; +- interrupts = <0 117 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&clock HIX5HD2_FIXED_100M>; +- clock-names = "apb_pclk"; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- gpio10: gpio@b2a000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xb2a000 0x1000>; +- interrupts = <0 118 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&clock HIX5HD2_FIXED_100M>; +- clock-names = "apb_pclk"; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- gpio11: gpio@b2b000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xb2b000 0x1000>; +- interrupts = <0 119 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&clock HIX5HD2_FIXED_100M>; +- clock-names = "apb_pclk"; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- gpio12: gpio@b2c000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xb2c000 0x1000>; +- interrupts = <0 120 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&clock HIX5HD2_FIXED_100M>; +- clock-names = "apb_pclk"; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- gpio13: gpio@b2d000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xb2d000 0x1000>; +- interrupts = <0 121 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&clock HIX5HD2_FIXED_100M>; +- clock-names = "apb_pclk"; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- gpio14: gpio@b2e000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xb2e000 0x1000>; +- interrupts = <0 122 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&clock HIX5HD2_FIXED_100M>; +- clock-names = "apb_pclk"; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- gpio15: gpio@b2f000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xb2f000 0x1000>; +- interrupts = <0 123 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&clock HIX5HD2_FIXED_100M>; +- clock-names = "apb_pclk"; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- gpio16: gpio@b30000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xb30000 0x1000>; +- interrupts = <0 124 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&clock HIX5HD2_FIXED_100M>; +- clock-names = "apb_pclk"; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- gpio17: gpio@b31000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xb31000 0x1000>; +- interrupts = <0 125 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&clock HIX5HD2_FIXED_100M>; +- clock-names = "apb_pclk"; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- wdt0: watchdog@a2c000 { +- compatible = "arm,sp805", "arm,primecell"; +- arm,primecell-periphid = <0x00141805>; +- reg = <0xa2c000 0x1000>; +- interrupts = <0 29 4>; +- clocks = <&clock HIX5HD2_WDG0_RST>, +- <&clock HIX5HD2_WDG0_RST>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- }; +- +- local_timer@a00600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x00a00600 0x20>; +- interrupts = <1 13 0xf01>; +- }; +- +- l2: cache-controller { +- compatible = "arm,pl310-cache"; +- reg = <0x00a10000 0x100000>; +- interrupts = <0 15 4>; +- cache-unified; +- cache-level = <2>; +- }; +- +- sysctrl: system-controller@0 { +- compatible = "hisilicon,sysctrl", "syscon"; +- reg = <0x00000000 0x1000>; +- }; +- +- reboot { +- compatible = "syscon-reboot"; +- regmap = <&sysctrl>; +- offset = <0x4>; +- mask = <0xdeadbeef>; +- }; +- +- cpuctrl@a22000 { +- compatible = "hisilicon,cpuctrl"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x00a22000 0x2000>; +- ranges = <0 0x00a22000 0x2000>; +- +- clock: clock@0 { +- compatible = "hisilicon,hix5hd2-clock"; +- reg = <0 0x2000>; +- #clock-cells = <1>; +- }; +- }; +- +- /* unremovable emmc as mmcblk0 */ +- mmc: mmc@1830000 { +- compatible = "snps,dw-mshc"; +- reg = <0x1830000 0x1000>; +- interrupts = <0 35 4>; +- clocks = <&clock HIX5HD2_MMC_CIU_RST>, +- <&clock HIX5HD2_MMC_BIU_CLK>; +- clock-names = "biu", "ciu"; +- }; +- +- sd: mmc@1820000 { +- compatible = "snps,dw-mshc"; +- reg = <0x1820000 0x1000>; +- interrupts = <0 34 4>; +- clocks = <&clock HIX5HD2_SD_CIU_RST>, +- <&clock HIX5HD2_SD_BIU_CLK>; +- clock-names = "biu", "ciu"; +- }; +- +- gmac0: ethernet@1840000 { +- compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1"; +- reg = <0x1840000 0x1000>,<0x184300c 0x4>; +- interrupts = <0 71 4>; +- clocks = <&clock HIX5HD2_MAC0_CLK>; +- clock-names = "mac_core"; +- status = "disabled"; +- }; +- +- gmac1: ethernet@1841000 { +- compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1"; +- reg = <0x1841000 0x1000>,<0x1843010 0x4>; +- interrupts = <0 72 4>; +- clocks = <&clock HIX5HD2_MAC1_CLK>; +- clock-names = "mac_core"; +- status = "disabled"; +- }; +- +- usb0: usb@1890000 { +- compatible = "generic-ehci"; +- reg = <0x1890000 0x1000>; +- interrupts = <0 66 4>; +- clocks = <&clock HIX5HD2_USB_CLK>; +- }; +- +- usb1: usb@1880000 { +- compatible = "generic-ohci"; +- reg = <0x1880000 0x1000>; +- interrupts = <0 67 4>; +- clocks = <&clock HIX5HD2_USB_CLK>; +- }; +- +- peripheral_ctrl: syscon@a20000 { +- compatible = "hisilicon,peri-subctrl", "syscon"; +- reg = <0xa20000 0x1000>; +- }; +- +- sata_phy: phy@1900000 { +- compatible = "hisilicon,hix5hd2-sata-phy"; +- reg = <0x1900000 0x10000>; +- #phy-cells = <0>; +- hisilicon,peripheral-syscon = <&peripheral_ctrl>; +- hisilicon,power-reg = <0x8 10>; +- }; +- +- ahci: sata@1900000 { +- compatible = "hisilicon,hisi-ahci"; +- reg = <0x1900000 0x10000>; +- interrupts = <0 70 4>; +- clocks = <&clock HIX5HD2_SATA_CLK>; +- }; +- +- ir: ir@1000 { +- compatible = "hisilicon,hix5hd2-ir"; +- reg = <0x001000 0x1000>; +- interrupts = <0 47 4>; +- clocks = <&clock HIX5HD2_FIXED_24M>; +- hisilicon,power-syscon = <&sysctrl>; +- }; +- +- i2c0: i2c@b10000 { +- compatible = "hisilicon,hix5hd2-i2c"; +- reg = <0xb10000 0x1000>; +- interrupts = <0 38 4>; +- clocks = <&clock HIX5HD2_I2C0_RST>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@b11000 { +- compatible = "hisilicon,hix5hd2-i2c"; +- reg = <0xb11000 0x1000>; +- interrupts = <0 39 4>; +- clocks = <&clock HIX5HD2_I2C1_RST>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@b12000 { +- compatible = "hisilicon,hix5hd2-i2c"; +- reg = <0xb12000 0x1000>; +- interrupts = <0 40 4>; +- clocks = <&clock HIX5HD2_I2C2_RST>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@b13000 { +- compatible = "hisilicon,hix5hd2-i2c"; +- reg = <0xb13000 0x1000>; +- interrupts = <0 41 4>; +- clocks = <&clock HIX5HD2_I2C3_RST>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@b16000 { +- compatible = "hisilicon,hix5hd2-i2c"; +- reg = <0xb16000 0x1000>; +- interrupts = <0 43 4>; +- clocks = <&clock HIX5HD2_I2C4_RST>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c5: i2c@b17000 { +- compatible = "hisilicon,hix5hd2-i2c"; +- reg = <0xb17000 0x1000>; +- interrupts = <0 44 4>; +- clocks = <&clock HIX5HD2_I2C5_RST>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ibm-power9-dual.dtsi b/scripts/dtc/include-prefixes/arm/ibm-power9-dual.dtsi +deleted file mode 100644 +index a0fa65b44b0f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ibm-power9-dual.dtsi ++++ /dev/null +@@ -1,248 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright 2018 IBM Corp +- +-&fsi { +- cfam@0,0 { +- reg = <0 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- chip-id = <0>; +- +- scom@1000 { +- compatible = "ibm,fsi2pib"; +- reg = <0x1000 0x400>; +- }; +- +- i2c@1800 { +- compatible = "ibm,fsi-i2c-master"; +- reg = <0x1800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam0_i2c0: i2c-bus@0 { +- reg = <0>; +- }; +- +- cfam0_i2c1: i2c-bus@1 { +- reg = <1>; +- }; +- +- cfam0_i2c2: i2c-bus@2 { +- reg = <2>; +- }; +- +- cfam0_i2c3: i2c-bus@3 { +- reg = <3>; +- }; +- +- cfam0_i2c4: i2c-bus@4 { +- reg = <4>; +- }; +- +- cfam0_i2c5: i2c-bus@5 { +- reg = <5>; +- }; +- +- cfam0_i2c6: i2c-bus@6 { +- reg = <6>; +- }; +- +- cfam0_i2c7: i2c-bus@7 { +- reg = <7>; +- }; +- +- cfam0_i2c8: i2c-bus@8 { +- reg = <8>; +- }; +- +- cfam0_i2c9: i2c-bus@9 { +- reg = <9>; +- }; +- +- cfam0_i2c10: i2c-bus@a { +- reg = <10>; +- }; +- +- cfam0_i2c11: i2c-bus@b { +- reg = <11>; +- }; +- +- cfam0_i2c12: i2c-bus@c { +- reg = <12>; +- }; +- +- cfam0_i2c13: i2c-bus@d { +- reg = <13>; +- }; +- +- cfam0_i2c14: i2c-bus@e { +- reg = <14>; +- }; +- }; +- +- sbefifo@2400 { +- compatible = "ibm,p9-sbefifo"; +- reg = <0x2400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fsi_occ0: occ@1 { +- compatible = "ibm,p9-occ"; +- }; +- }; +- +- fsi_hub0: hub@3400 { +- compatible = "fsi-master-hub"; +- reg = <0x3400 0x400>; +- #address-cells = <2>; +- #size-cells = <0>; +- +- no-scan-on-init; +- }; +- }; +-}; +- +-&fsi_hub0 { +- cfam@1,0 { +- reg = <1 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- chip-id = <1>; +- +- scom@1000 { +- compatible = "ibm,fsi2pib"; +- reg = <0x1000 0x400>; +- }; +- +- i2c@1800 { +- compatible = "ibm,fsi-i2c-master"; +- reg = <0x1800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cfam1_i2c0: i2c-bus@0 { +- reg = <0>; +- }; +- +- cfam1_i2c1: i2c-bus@1 { +- reg = <1>; +- }; +- +- cfam1_i2c2: i2c-bus@2 { +- reg = <2>; +- }; +- +- cfam1_i2c3: i2c-bus@3 { +- reg = <3>; +- }; +- +- cfam1_i2c4: i2c-bus@4 { +- reg = <4>; +- }; +- +- cfam1_i2c5: i2c-bus@5 { +- reg = <5>; +- }; +- +- cfam1_i2c6: i2c-bus@6 { +- reg = <6>; +- }; +- +- cfam1_i2c7: i2c-bus@7 { +- reg = <7>; +- }; +- +- cfam1_i2c8: i2c-bus@8 { +- reg = <8>; +- }; +- +- cfam1_i2c9: i2c-bus@9 { +- reg = <9>; +- }; +- +- cfam1_i2c10: i2c-bus@a { +- reg = <10>; +- }; +- +- cfam1_i2c11: i2c-bus@b { +- reg = <11>; +- }; +- +- cfam1_i2c12: i2c-bus@c { +- reg = <12>; +- }; +- +- cfam1_i2c13: i2c-bus@d { +- reg = <13>; +- }; +- +- cfam1_i2c14: i2c-bus@e { +- reg = <14>; +- }; +- }; +- +- sbefifo@2400 { +- compatible = "ibm,p9-sbefifo"; +- reg = <0x2400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fsi_occ1: occ@2 { +- compatible = "ibm,p9-occ"; +- }; +- }; +- +- fsi_hub1: hub@3400 { +- compatible = "fsi-master-hub"; +- reg = <0x3400 0x400>; +- #address-cells = <2>; +- #size-cells = <0>; +- +- no-scan-on-init; +- }; +- }; +-}; +- +-/* Legacy OCC numbering (to get rid of when userspace is fixed) */ +-&fsi_occ0 { +- reg = <1>; +-}; +- +-&fsi_occ1 { +- reg = <2>; +-}; +- +-/ { +- aliases { +- i2c100 = &cfam0_i2c0; +- i2c101 = &cfam0_i2c1; +- i2c102 = &cfam0_i2c2; +- i2c103 = &cfam0_i2c3; +- i2c104 = &cfam0_i2c4; +- i2c105 = &cfam0_i2c5; +- i2c106 = &cfam0_i2c6; +- i2c107 = &cfam0_i2c7; +- i2c108 = &cfam0_i2c8; +- i2c109 = &cfam0_i2c9; +- i2c110 = &cfam0_i2c10; +- i2c111 = &cfam0_i2c11; +- i2c112 = &cfam0_i2c12; +- i2c113 = &cfam0_i2c13; +- i2c114 = &cfam0_i2c14; +- i2c200 = &cfam1_i2c0; +- i2c201 = &cfam1_i2c1; +- i2c202 = &cfam1_i2c2; +- i2c203 = &cfam1_i2c3; +- i2c204 = &cfam1_i2c4; +- i2c205 = &cfam1_i2c5; +- i2c206 = &cfam1_i2c6; +- i2c207 = &cfam1_i2c7; +- i2c208 = &cfam1_i2c8; +- i2c209 = &cfam1_i2c9; +- i2c210 = &cfam1_i2c10; +- i2c211 = &cfam1_i2c11; +- i2c212 = &cfam1_i2c12; +- i2c213 = &cfam1_i2c13; +- i2c214 = &cfam1_i2c14; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx1-ads.dts b/scripts/dtc/include-prefixes/arm/imx1-ads.dts +deleted file mode 100644 +index 5833fb6f15d8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx1-ads.dts ++++ /dev/null +@@ -1,135 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2014 Alexander Shiyan +- */ +- +-/dts-v1/; +-#include "imx1.dtsi" +- +-/ { +- model = "Freescale MX1 ADS"; +- compatible = "fsl,imx1ads", "fsl,imx1"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@8000000 { +- device_type = "memory"; +- reg = <0x08000000 0x04000000>; +- }; +-}; +- +-&cspi1 { +- pinctrl-0 = <&pinctrl_cspi1>; +- cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&i2c { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c>; +- status = "okay"; +- +- extgpio0: pcf8575@22 { +- compatible = "nxp,pcf8575"; +- reg = <0x22>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- extgpio1: pcf8575@24 { +- compatible = "nxp,pcf8575"; +- reg = <0x24>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&weim { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_weim>; +- status = "okay"; +- +- nor: nor@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0x00000000 0x02000000>; +- bank-width = <4>; +- fsl,weim-cs-timing = <0x00003e00 0x00000801>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&iomuxc { +- imx1-ads { +- pinctrl_cspi1: cspi1grp { +- fsl,pins = < +- MX1_PAD_SPI1_MISO__SPI1_MISO 0x0 +- MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0 +- MX1_PAD_SPI1_RDY__SPI1_RDY 0x0 +- MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0 +- MX1_PAD_SPI1_SS__GPIO3_15 0x0 +- >; +- }; +- +- pinctrl_i2c: i2cgrp { +- fsl,pins = < +- MX1_PAD_I2C_SCL__I2C_SCL 0x0 +- MX1_PAD_I2C_SDA__I2C_SDA 0x0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX1_PAD_UART1_TXD__UART1_TXD 0x0 +- MX1_PAD_UART1_RXD__UART1_RXD 0x0 +- MX1_PAD_UART1_CTS__UART1_CTS 0x0 +- MX1_PAD_UART1_RTS__UART1_RTS 0x0 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX1_PAD_UART2_TXD__UART2_TXD 0x0 +- MX1_PAD_UART2_RXD__UART2_RXD 0x0 +- MX1_PAD_UART2_CTS__UART2_CTS 0x0 +- MX1_PAD_UART2_RTS__UART2_RTS 0x0 +- >; +- }; +- +- pinctrl_weim: weimgrp { +- fsl,pins = < +- MX1_PAD_A0__A0 0x0 +- MX1_PAD_A16__A16 0x0 +- MX1_PAD_A17__A17 0x0 +- MX1_PAD_A18__A18 0x0 +- MX1_PAD_A19__A19 0x0 +- MX1_PAD_A20__A20 0x0 +- MX1_PAD_A21__A21 0x0 +- MX1_PAD_A22__A22 0x0 +- MX1_PAD_A23__A23 0x0 +- MX1_PAD_A24__A24 0x0 +- MX1_PAD_BCLK__BCLK 0x0 +- MX1_PAD_CS4__CS4 0x0 +- MX1_PAD_DTACK__DTACK 0x0 +- MX1_PAD_ECB__ECB 0x0 +- MX1_PAD_LBA__LBA 0x0 +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx1-apf9328.dts b/scripts/dtc/include-prefixes/arm/imx1-apf9328.dts +deleted file mode 100644 +index 77b21aa7a146..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx1-apf9328.dts ++++ /dev/null +@@ -1,124 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2014 Alexander Shiyan +- */ +- +-/dts-v1/; +-#include "imx1.dtsi" +- +-/ { +- model = "Armadeus APF9328"; +- compatible = "armadeus,imx1-apf9328", "fsl,imx1"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@8000000 { +- device_type = "memory"; +- reg = <0x08000000 0x00800000>; +- }; +-}; +- +-&i2c { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&weim { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_weim>; +- status = "okay"; +- +- nor: nor@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0x00000000 0x02000000>; +- bank-width = <2>; +- fsl,weim-cs-timing = <0x00330e04 0x00000d01>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- eth: eth@4,c00000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_eth>; +- compatible = "davicom,dm9000"; +- reg = < +- 4 0x00c00000 0x2 +- 4 0x00c00002 0x2 +- >; +- interrupt-parent = <&gpio2>; +- interrupts = <14 IRQ_TYPE_LEVEL_LOW>; +- fsl,weim-cs-timing = <0x0000c700 0x19190d01>; +- }; +-}; +- +-&iomuxc { +- imx1-apf9328 { +- pinctrl_eth: ethgrp { +- fsl,pins = < +- MX1_PAD_SIM_SVEN__GPIO2_14 0x0 +- >; +- }; +- +- pinctrl_i2c: i2cgrp { +- fsl,pins = < +- MX1_PAD_I2C_SCL__I2C_SCL 0x0 +- MX1_PAD_I2C_SDA__I2C_SDA 0x0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX1_PAD_UART1_TXD__UART1_TXD 0x0 +- MX1_PAD_UART1_RXD__UART1_RXD 0x0 +- MX1_PAD_UART1_CTS__UART1_CTS 0x0 +- MX1_PAD_UART1_RTS__UART1_RTS 0x0 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX1_PAD_UART2_TXD__UART2_TXD 0x0 +- MX1_PAD_UART2_RXD__UART2_RXD 0x0 +- MX1_PAD_UART2_CTS__UART2_CTS 0x0 +- MX1_PAD_UART2_RTS__UART2_RTS 0x0 +- >; +- }; +- +- pinctrl_weim: weimgrp { +- fsl,pins = < +- MX1_PAD_A0__A0 0x0 +- MX1_PAD_A16__A16 0x0 +- MX1_PAD_A17__A17 0x0 +- MX1_PAD_A18__A18 0x0 +- MX1_PAD_A19__A19 0x0 +- MX1_PAD_A20__A20 0x0 +- MX1_PAD_A21__A21 0x0 +- MX1_PAD_A22__A22 0x0 +- MX1_PAD_A23__A23 0x0 +- MX1_PAD_A24__A24 0x0 +- MX1_PAD_BCLK__BCLK 0x0 +- MX1_PAD_CS4__CS4 0x0 +- MX1_PAD_DTACK__DTACK 0x0 +- MX1_PAD_ECB__ECB 0x0 +- MX1_PAD_LBA__LBA 0x0 +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx1-pinfunc.h b/scripts/dtc/include-prefixes/arm/imx1-pinfunc.h +deleted file mode 100644 +index 050a1fc46a77..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx1-pinfunc.h ++++ /dev/null +@@ -1,296 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (C) 2014 Alexander Shiyan +- */ +- +-#ifndef __DTS_IMX1_PINFUNC_H +-#define __DTS_IMX1_PINFUNC_H +- +-/* +- * The pin function ID is a tuple of +- * +- * mux_id consists of +- * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10) +- * +- * function: 0 - Primary function +- * 1 - Alternate function +- * 2 - GPIO +- * direction: 0 - Input +- * 1 - Output +- * gpio_oconf: 0 - A_IN +- * 1 - B_IN +- * 2 - A_OUT +- * 3 - Data Register +- * gpio_iconfa/b: 0 - GPIO_IN +- * 1 - Interrupt Status Register +- * 2 - 0 +- * 3 - 1 +- * +- * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 configurable +- * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin +- * number on the specific port (between 0 and 31). +- */ +- +-#define MX1_PAD_A24__A24 0x00 0x004 +-#define MX1_PAD_A24__GPIO1_0 0x00 0x032 +-#define MX1_PAD_A24__SPI2_CLK 0x00 0x006 +-#define MX1_PAD_TIN__TIN 0x01 0x000 +-#define MX1_PAD_TIN__GPIO1_1 0x01 0x032 +-#define MX1_PAD_TIN__SPI2_RXD 0x01 0x022 +-#define MX1_PAD_PWMO__PWMO 0x02 0x004 +-#define MX1_PAD_PWMO__GPIO1_2 0x02 0x032 +-#define MX1_PAD_CSI_MCLK__CSI_MCLK 0x03 0x004 +-#define MX1_PAD_CSI_MCLK__GPIO1_3 0x03 0x032 +-#define MX1_PAD_CSI_D0__CSI_D0 0x04 0x000 +-#define MX1_PAD_CSI_D0__GPIO1_4 0x04 0x032 +-#define MX1_PAD_CSI_D1__CSI_D1 0x05 0x000 +-#define MX1_PAD_CSI_D1__GPIO1_5 0x05 0x032 +-#define MX1_PAD_CSI_D2__CSI_D2 0x06 0x000 +-#define MX1_PAD_CSI_D2__GPIO1_6 0x06 0x032 +-#define MX1_PAD_CSI_D3__CSI_D3 0x07 0x000 +-#define MX1_PAD_CSI_D3__GPIO1_7 0x07 0x032 +-#define MX1_PAD_CSI_D4__CSI_D4 0x08 0x000 +-#define MX1_PAD_CSI_D4__GPIO1_8 0x08 0x032 +-#define MX1_PAD_CSI_D5__CSI_D5 0x09 0x000 +-#define MX1_PAD_CSI_D5__GPIO1_9 0x09 0x032 +-#define MX1_PAD_CSI_D6__CSI_D6 0x0a 0x000 +-#define MX1_PAD_CSI_D6__GPIO1_10 0x0a 0x032 +-#define MX1_PAD_CSI_D7__CSI_D7 0x0b 0x000 +-#define MX1_PAD_CSI_D7__GPIO1_11 0x0b 0x032 +-#define MX1_PAD_CSI_VSYNC__CSI_VSYNC 0x0c 0x000 +-#define MX1_PAD_CSI_VSYNC__GPIO1_12 0x0c 0x032 +-#define MX1_PAD_CSI_HSYNC__CSI_HSYNC 0x0d 0x000 +-#define MX1_PAD_CSI_HSYNC__GPIO1_13 0x0d 0x032 +-#define MX1_PAD_CSI_PIXCLK__CSI_PIXCLK 0x0e 0x000 +-#define MX1_PAD_CSI_PIXCLK__GPIO1_14 0x0e 0x032 +-#define MX1_PAD_I2C_SDA__I2C_SDA 0x0f 0x000 +-#define MX1_PAD_I2C_SDA__GPIO1_15 0x0f 0x032 +-#define MX1_PAD_I2C_SCL__I2C_SCL 0x10 0x004 +-#define MX1_PAD_I2C_SCL__GPIO1_16 0x10 0x032 +-#define MX1_PAD_DTACK__DTACK 0x11 0x000 +-#define MX1_PAD_DTACK__GPIO1_17 0x11 0x032 +-#define MX1_PAD_DTACK__SPI2_SS 0x11 0x002 +-#define MX1_PAD_DTACK__A25 0x11 0x016 +-#define MX1_PAD_BCLK__BCLK 0x12 0x004 +-#define MX1_PAD_BCLK__GPIO1_18 0x12 0x032 +-#define MX1_PAD_LBA__LBA 0x13 0x004 +-#define MX1_PAD_LBA__GPIO1_19 0x13 0x032 +-#define MX1_PAD_ECB__ECB 0x14 0x000 +-#define MX1_PAD_ECB__GPIO1_20 0x14 0x032 +-#define MX1_PAD_A0__A0 0x15 0x004 +-#define MX1_PAD_A0__GPIO1_21 0x15 0x032 +-#define MX1_PAD_CS4__CS4 0x16 0x004 +-#define MX1_PAD_CS4__GPIO1_22 0x16 0x032 +-#define MX1_PAD_CS5__CS5 0x17 0x004 +-#define MX1_PAD_CS5__GPIO1_23 0x17 0x032 +-#define MX1_PAD_A16__A16 0x18 0x004 +-#define MX1_PAD_A16__GPIO1_24 0x18 0x032 +-#define MX1_PAD_A17__A17 0x19 0x004 +-#define MX1_PAD_A17__GPIO1_25 0x19 0x032 +-#define MX1_PAD_A18__A18 0x1a 0x004 +-#define MX1_PAD_A18__GPIO1_26 0x1a 0x032 +-#define MX1_PAD_A19__A19 0x1b 0x004 +-#define MX1_PAD_A19__GPIO1_27 0x1b 0x032 +-#define MX1_PAD_A20__A20 0x1c 0x004 +-#define MX1_PAD_A20__GPIO1_28 0x1c 0x032 +-#define MX1_PAD_A21__A21 0x1d 0x004 +-#define MX1_PAD_A21__GPIO1_29 0x1d 0x032 +-#define MX1_PAD_A22__A22 0x1e 0x004 +-#define MX1_PAD_A22__GPIO1_30 0x1e 0x032 +-#define MX1_PAD_A23__A23 0x1f 0x004 +-#define MX1_PAD_A23__GPIO1_31 0x1f 0x032 +-#define MX1_PAD_SD_DAT0__SD_DAT0 0x28 0x000 +-#define MX1_PAD_SD_DAT0__MS_PI0 0x28 0x001 +-#define MX1_PAD_SD_DAT0__GPIO2_8 0x28 0x032 +-#define MX1_PAD_SD_DAT1__SD_DAT1 0x29 0x000 +-#define MX1_PAD_SD_DAT1__MS_PI1 0x29 0x001 +-#define MX1_PAD_SD_DAT1__GPIO2_9 0x29 0x032 +-#define MX1_PAD_SD_DAT2__SD_DAT2 0x2a 0x000 +-#define MX1_PAD_SD_DAT2__MS_SCLKI 0x2a 0x001 +-#define MX1_PAD_SD_DAT2__GPIO2_10 0x2a 0x032 +-#define MX1_PAD_SD_DAT3__SD_DAT3 0x2b 0x000 +-#define MX1_PAD_SD_DAT3__MS_SDIO 0x2b 0x001 +-#define MX1_PAD_SD_DAT3__GPIO2_11 0x2b 0x032 +-#define MX1_PAD_SD_SCLK__SD_SCLK 0x2c 0x004 +-#define MX1_PAD_SD_SCLK__MS_SCLKO 0x2c 0x005 +-#define MX1_PAD_SD_SCLK__GPIO2_12 0x2c 0x032 +-#define MX1_PAD_SD_CMD__SD_CMD 0x2d 0x000 +-#define MX1_PAD_SD_CMD__MS_BS 0x2d 0x005 +-#define MX1_PAD_SD_CMD__GPIO2_13 0x2d 0x032 +-#define MX1_PAD_SIM_SVEN__SIM_SVEN 0x2e 0x004 +-#define MX1_PAD_SIM_SVEN__SSI_RXFS 0x2e 0x001 +-#define MX1_PAD_SIM_SVEN__GPIO2_14 0x2e 0x032 +-#define MX1_PAD_SIM_PD__SIM_PD 0x2f 0x000 +-#define MX1_PAD_SIM_PD__SSI_RXCLK 0x2f 0x001 +-#define MX1_PAD_SIM_PD__GPIO2_15 0x2f 0x032 +-#define MX1_PAD_SIM_TX__SIM_TX 0x30 0x000 +-#define MX1_PAD_SIM_TX__SSI_RXDAT 0x30 0x001 +-#define MX1_PAD_SIM_TX__GPIO2_16 0x30 0x032 +-#define MX1_PAD_SIM_RX__SIM_RX 0x31 0x000 +-#define MX1_PAD_SIM_RX__SSI_TXDAT 0x31 0x005 +-#define MX1_PAD_SIM_RX__GPIO2_17 0x31 0x032 +-#define MX1_PAD_SIM_RST__SIM_RST 0x32 0x004 +-#define MX1_PAD_SIM_RST__SSI_TXFS 0x32 0x001 +-#define MX1_PAD_SIM_RST__GPIO2_18 0x32 0x032 +-#define MX1_PAD_SIM_CLK__SIM_CLK 0x33 0x004 +-#define MX1_PAD_SIM_CLK__SSI_TXCLK 0x33 0x001 +-#define MX1_PAD_SIM_CLK__GPIO2_19 0x33 0x032 +-#define MX1_PAD_USBD_AFE__USBD_AFE 0x34 0x004 +-#define MX1_PAD_USBD_AFE__GPIO2_20 0x34 0x032 +-#define MX1_PAD_USBD_OE__USBD_OE 0x35 0x004 +-#define MX1_PAD_USBD_OE__GPIO2_21 0x35 0x032 +-#define MX1_PAD_USBD_RCV__USBD_RCV 0x36 0x000 +-#define MX1_PAD_USBD_RCV__GPIO2_22 0x36 0x032 +-#define MX1_PAD_USBD_SUSPND__USBD_SUSPND 0x37 0x004 +-#define MX1_PAD_USBD_SUSPND__GPIO2_23 0x37 0x032 +-#define MX1_PAD_USBD_VP__USBD_VP 0x38 0x000 +-#define MX1_PAD_USBD_VP__GPIO2_24 0x38 0x032 +-#define MX1_PAD_USBD_VM__USBD_VM 0x39 0x000 +-#define MX1_PAD_USBD_VM__GPIO2_25 0x39 0x032 +-#define MX1_PAD_USBD_VPO__USBD_VPO 0x3a 0x004 +-#define MX1_PAD_USBD_VPO__GPIO2_26 0x3a 0x032 +-#define MX1_PAD_USBD_VMO__USBD_VMO 0x3b 0x004 +-#define MX1_PAD_USBD_VMO__GPIO2_27 0x3b 0x032 +-#define MX1_PAD_UART2_CTS__UART2_CTS 0x3c 0x004 +-#define MX1_PAD_UART2_CTS__GPIO2_28 0x3c 0x032 +-#define MX1_PAD_UART2_RTS__UART2_RTS 0x3d 0x000 +-#define MX1_PAD_UART2_RTS__GPIO2_29 0x3d 0x032 +-#define MX1_PAD_UART2_TXD__UART2_TXD 0x3e 0x004 +-#define MX1_PAD_UART2_TXD__GPIO2_30 0x3e 0x032 +-#define MX1_PAD_UART2_RXD__UART2_RXD 0x3f 0x000 +-#define MX1_PAD_UART2_RXD__GPIO2_31 0x3f 0x032 +-#define MX1_PAD_SSI_RXFS__SSI_RXFS 0x43 0x000 +-#define MX1_PAD_SSI_RXFS__GPIO3_3 0x43 0x032 +-#define MX1_PAD_SSI_RXCLK__SSI_RXCLK 0x44 0x000 +-#define MX1_PAD_SSI_RXCLK__GPIO3_4 0x44 0x032 +-#define MX1_PAD_SSI_RXDAT__SSI_RXDAT 0x45 0x000 +-#define MX1_PAD_SSI_RXDAT__GPIO3_5 0x45 0x032 +-#define MX1_PAD_SSI_TXDAT__SSI_TXDAT 0x46 0x004 +-#define MX1_PAD_SSI_TXDAT__GPIO3_6 0x46 0x032 +-#define MX1_PAD_SSI_TXFS__SSI_TXFS 0x47 0x000 +-#define MX1_PAD_SSI_TXFS__GPIO3_7 0x47 0x032 +-#define MX1_PAD_SSI_TXCLK__SSI_TXCLK 0x48 0x000 +-#define MX1_PAD_SSI_TXCLK__GPIO3_8 0x48 0x032 +-#define MX1_PAD_UART1_CTS__UART1_CTS 0x49 0x004 +-#define MX1_PAD_UART1_CTS__GPIO3_9 0x49 0x032 +-#define MX1_PAD_UART1_RTS__UART1_RTS 0x4a 0x000 +-#define MX1_PAD_UART1_RTS__GPIO3_10 0x4a 0x032 +-#define MX1_PAD_UART1_TXD__UART1_TXD 0x4b 0x004 +-#define MX1_PAD_UART1_TXD__GPIO3_11 0x4b 0x032 +-#define MX1_PAD_UART1_RXD__UART1_RXD 0x4c 0x000 +-#define MX1_PAD_UART1_RXD__GPIO3_12 0x4c 0x032 +-#define MX1_PAD_SPI1_RDY__SPI1_RDY 0x4d 0x000 +-#define MX1_PAD_SPI1_RDY__GPIO3_13 0x4d 0x032 +-#define MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x4e 0x004 +-#define MX1_PAD_SPI1_SCLK__GPIO3_14 0x4e 0x032 +-#define MX1_PAD_SPI1_SS__SPI1_SS 0x4f 0x000 +-#define MX1_PAD_SPI1_SS__GPIO3_15 0x4f 0x032 +-#define MX1_PAD_SPI1_MISO__SPI1_MISO 0x50 0x000 +-#define MX1_PAD_SPI1_MISO__GPIO3_16 0x50 0x032 +-#define MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x51 0x004 +-#define MX1_PAD_SPI1_MOSI__GPIO3_17 0x51 0x032 +-#define MX1_PAD_BT13__BT13 0x53 0x004 +-#define MX1_PAD_BT13__SSI2_RXCLK 0x53 0x001 +-#define MX1_PAD_BT13__GPIO3_19 0x53 0x032 +-#define MX1_PAD_BT12__BT12 0x54 0x004 +-#define MX1_PAD_BT12__SSI2_TXFS 0x54 0x001 +-#define MX1_PAD_BT12__GPIO3_20 0x54 0x032 +-#define MX1_PAD_BT11__BT11 0x55 0x004 +-#define MX1_PAD_BT11__SSI2_TXCLK 0x55 0x001 +-#define MX1_PAD_BT11__GPIO3_21 0x55 0x032 +-#define MX1_PAD_BT10__BT10 0x56 0x004 +-#define MX1_PAD_BT10__SSI2_TX 0x56 0x001 +-#define MX1_PAD_BT10__GPIO3_22 0x56 0x032 +-#define MX1_PAD_BT9__BT9 0x57 0x004 +-#define MX1_PAD_BT9__SSI2_RX 0x57 0x001 +-#define MX1_PAD_BT9__GPIO3_23 0x57 0x032 +-#define MX1_PAD_BT8__BT8 0x58 0x004 +-#define MX1_PAD_BT8__SSI2_RXFS 0x58 0x001 +-#define MX1_PAD_BT8__GPIO3_24 0x58 0x032 +-#define MX1_PAD_BT8__UART3_RI 0x58 0x016 +-#define MX1_PAD_BT7__BT7 0x59 0x004 +-#define MX1_PAD_BT7__GPIO3_25 0x59 0x032 +-#define MX1_PAD_BT7__UART3_DSR 0x59 0x016 +-#define MX1_PAD_BT6__BT6 0x5a 0x004 +-#define MX1_PAD_BT6__GPIO3_26 0x5a 0x032 +-#define MX1_PAD_BT6__SPI2_SS3 0x5a 0x016 +-#define MX1_PAD_BT6__UART3_DTR 0x5a 0x022 +-#define MX1_PAD_BT5__BT5 0x5b 0x000 +-#define MX1_PAD_BT5__GPIO3_27 0x5b 0x032 +-#define MX1_PAD_BT5__UART3_DCD 0x5b 0x016 +-#define MX1_PAD_BT4__BT4 0x5c 0x000 +-#define MX1_PAD_BT4__GPIO3_28 0x5c 0x032 +-#define MX1_PAD_BT4__UART3_CTS 0x5c 0x016 +-#define MX1_PAD_BT3__BT3 0x5d 0x000 +-#define MX1_PAD_BT3__GPIO3_29 0x5d 0x032 +-#define MX1_PAD_BT3__UART3_RTS 0x5d 0x022 +-#define MX1_PAD_BT2__BT2 0x5e 0x004 +-#define MX1_PAD_BT2__GPIO3_30 0x5e 0x032 +-#define MX1_PAD_BT2__UART3_TX 0x5e 0x016 +-#define MX1_PAD_BT1__BT1 0x5f 0x000 +-#define MX1_PAD_BT1__GPIO3_31 0x5f 0x032 +-#define MX1_PAD_BT1__UART3_RX 0x5f 0x022 +-#define MX1_PAD_LSCLK__LSCLK 0x66 0x004 +-#define MX1_PAD_LSCLK__GPIO4_6 0x66 0x032 +-#define MX1_PAD_REV__REV 0x67 0x004 +-#define MX1_PAD_REV__UART2_DTR 0x67 0x001 +-#define MX1_PAD_REV__GPIO4_7 0x67 0x032 +-#define MX1_PAD_REV__SPI2_CLK 0x67 0x006 +-#define MX1_PAD_CLS__CLS 0x68 0x004 +-#define MX1_PAD_CLS__UART2_DCD 0x68 0x005 +-#define MX1_PAD_CLS__GPIO4_8 0x68 0x032 +-#define MX1_PAD_CLS__SPI2_SS 0x68 0x002 +-#define MX1_PAD_PS__PS 0x69 0x004 +-#define MX1_PAD_PS__UART2_RI 0x69 0x005 +-#define MX1_PAD_PS__GPIO4_9 0x69 0x032 +-#define MX1_PAD_PS__SPI2_RXD 0x69 0x022 +-#define MX1_PAD_SPL_SPR__SPL_SPR 0x6a 0x004 +-#define MX1_PAD_SPL_SPR__UART2_DSR 0x6a 0x005 +-#define MX1_PAD_SPL_SPR__GPIO4_10 0x6a 0x032 +-#define MX1_PAD_SPL_SPR__SPI2_TXD 0x6a 0x006 +-#define MX1_PAD_CONTRAST__CONTRAST 0x6b 0x004 +-#define MX1_PAD_CONTRAST__GPIO4_11 0x6b 0x032 +-#define MX1_PAD_CONTRAST__SPI2_SS2 0x6b 0x012 +-#define MX1_PAD_ACD_OE__ACD_OE 0x6c 0x004 +-#define MX1_PAD_ACD_OE__GPIO4_12 0x6c 0x032 +-#define MX1_PAD_LP_HSYNC__LP_HSYNC 0x6d 0x004 +-#define MX1_PAD_LP_HSYNC__GPIO4_13 0x6d 0x032 +-#define MX1_PAD_FLM_VSYNC__FLM_VSYNC 0x6e 0x004 +-#define MX1_PAD_FLM_VSYNC__GPIO4_14 0x6e 0x032 +-#define MX1_PAD_LD0__LD0 0x6f 0x004 +-#define MX1_PAD_LD0__GPIO4_15 0x6f 0x032 +-#define MX1_PAD_LD1__LD1 0x70 0x004 +-#define MX1_PAD_LD1__GPIO4_16 0x70 0x032 +-#define MX1_PAD_LD2__LD2 0x71 0x004 +-#define MX1_PAD_LD2__GPIO4_17 0x71 0x032 +-#define MX1_PAD_LD3__LD3 0x72 0x004 +-#define MX1_PAD_LD3__GPIO4_18 0x72 0x032 +-#define MX1_PAD_LD4__LD4 0x73 0x004 +-#define MX1_PAD_LD4__GPIO4_19 0x73 0x032 +-#define MX1_PAD_LD5__LD5 0x74 0x004 +-#define MX1_PAD_LD5__GPIO4_20 0x74 0x032 +-#define MX1_PAD_LD6__LD6 0x75 0x004 +-#define MX1_PAD_LD6__GPIO4_21 0x75 0x032 +-#define MX1_PAD_LD7__LD7 0x76 0x004 +-#define MX1_PAD_LD7__GPIO4_22 0x76 0x032 +-#define MX1_PAD_LD8__LD8 0x77 0x004 +-#define MX1_PAD_LD8__GPIO4_23 0x77 0x032 +-#define MX1_PAD_LD9__LD9 0x78 0x004 +-#define MX1_PAD_LD9__GPIO4_24 0x78 0x032 +-#define MX1_PAD_LD10__LD10 0x79 0x004 +-#define MX1_PAD_LD10__GPIO4_25 0x79 0x032 +-#define MX1_PAD_LD11__LD11 0x7a 0x004 +-#define MX1_PAD_LD11__GPIO4_26 0x7a 0x032 +-#define MX1_PAD_LD12__LD12 0x7b 0x004 +-#define MX1_PAD_LD12__GPIO4_27 0x7b 0x032 +-#define MX1_PAD_LD13__LD13 0x7c 0x004 +-#define MX1_PAD_LD13__GPIO4_28 0x7c 0x032 +-#define MX1_PAD_LD14__LD14 0x7d 0x004 +-#define MX1_PAD_LD14__GPIO4_29 0x7d 0x032 +-#define MX1_PAD_LD15__LD15 0x7e 0x004 +-#define MX1_PAD_LD15__GPIO4_30 0x7e 0x032 +-#define MX1_PAD_TMR2OUT__TMR2OUT 0x7f 0x000 +-#define MX1_PAD_TMR2OUT__GPIO4_31 0x7f 0x032 +-#define MX1_PAD_TMR2OUT__SPI2_TXD 0x7f 0x006 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/arm/imx1.dtsi b/scripts/dtc/include-prefixes/arm/imx1.dtsi +deleted file mode 100644 +index 9b940987864c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx1.dtsi ++++ /dev/null +@@ -1,276 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright (C) 2014 Alexander Shiyan +- +-#include "imx1-pinfunc.h" +- +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * The decompressor and also some bootloaders rely on a +- * pre-existing /chosen node to be available to insert the +- * command line and merge other ATAGS info. +- */ +- chosen {}; +- +- aliases { +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- gpio3 = &gpio4; +- i2c0 = &i2c; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- spi0 = &cspi1; +- spi1 = &cspi2; +- }; +- +- aitc: aitc-interrupt-controller@223000 { +- compatible = "fsl,imx1-aitc", "fsl,avic"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x00223000 0x1000>; +- }; +- +- cpus { +- #size-cells = <0>; +- #address-cells = <1>; +- +- cpu@0 { +- device_type = "cpu"; +- reg = <0>; +- compatible = "arm,arm920t"; +- operating-points = <200000 1900000>; +- clock-latency = <62500>; +- clocks = <&clks IMX1_CLK_MCU>; +- voltage-tolerance = <5>; +- }; +- }; +- +- clocks { +- clk32 { +- compatible = "fsl,imx-clk32", "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32000>; +- }; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&aitc>; +- ranges; +- +- aipi@200000 { +- compatible = "fsl,aipi-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x00200000 0x10000>; +- ranges; +- +- gpt1: timer@202000 { +- compatible = "fsl,imx1-gpt"; +- reg = <0x00202000 0x1000>; +- interrupts = <59>; +- clocks = <&clks IMX1_CLK_HCLK>, +- <&clks IMX1_CLK_PER1>; +- clock-names = "ipg", "per"; +- }; +- +- gpt2: timer@203000 { +- compatible = "fsl,imx1-gpt"; +- reg = <0x00203000 0x1000>; +- interrupts = <58>; +- clocks = <&clks IMX1_CLK_HCLK>, +- <&clks IMX1_CLK_PER1>; +- clock-names = "ipg", "per"; +- }; +- +- fb: fb@205000 { +- compatible = "fsl,imx1-fb"; +- reg = <0x00205000 0x1000>; +- interrupts = <14>; +- clocks = <&clks IMX1_CLK_DUMMY>, +- <&clks IMX1_CLK_DUMMY>, +- <&clks IMX1_CLK_PER2>; +- clock-names = "ipg", "ahb", "per"; +- status = "disabled"; +- }; +- +- uart1: serial@206000 { +- compatible = "fsl,imx1-uart"; +- reg = <0x00206000 0x1000>; +- interrupts = <30 29 26>; +- clocks = <&clks IMX1_CLK_HCLK>, +- <&clks IMX1_CLK_PER1>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart2: serial@207000 { +- compatible = "fsl,imx1-uart"; +- reg = <0x00207000 0x1000>; +- interrupts = <24 23 20>; +- clocks = <&clks IMX1_CLK_HCLK>, +- <&clks IMX1_CLK_PER1>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- pwm: pwm@208000 { +- #pwm-cells = <3>; +- compatible = "fsl,imx1-pwm"; +- reg = <0x00208000 0x1000>; +- interrupts = <34>; +- clocks = <&clks IMX1_CLK_DUMMY>, +- <&clks IMX1_CLK_PER1>; +- clock-names = "ipg", "per"; +- }; +- +- dma: dma@209000 { +- compatible = "fsl,imx1-dma"; +- reg = <0x00209000 0x1000>; +- interrupts = <61 60>; +- clocks = <&clks IMX1_CLK_HCLK>, +- <&clks IMX1_CLK_DMA_GATE>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <1>; +- }; +- +- uart3: serial@20a000 { +- compatible = "fsl,imx1-uart"; +- reg = <0x0020a000 0x1000>; +- interrupts = <54 4 1>; +- clocks = <&clks IMX1_CLK_UART3_GATE>, +- <&clks IMX1_CLK_PER1>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- }; +- +- aipi@210000 { +- compatible = "fsl,aipi-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x00210000 0x10000>; +- ranges; +- +- cspi1: spi@213000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx1-cspi"; +- reg = <0x00213000 0x1000>; +- interrupts = <41>; +- clocks = <&clks IMX1_CLK_DUMMY>, +- <&clks IMX1_CLK_PER1>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- i2c: i2c@217000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx1-i2c"; +- reg = <0x00217000 0x1000>; +- interrupts = <39>; +- clocks = <&clks IMX1_CLK_HCLK>; +- status = "disabled"; +- }; +- +- cspi2: spi@219000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx1-cspi"; +- reg = <0x00219000 0x1000>; +- interrupts = <40>; +- clocks = <&clks IMX1_CLK_DUMMY>, +- <&clks IMX1_CLK_PER1>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- clks: ccm@21b000 { +- compatible = "fsl,imx1-ccm"; +- reg = <0x0021b000 0x1000>; +- #clock-cells = <1>; +- }; +- +- iomuxc: iomuxc@21c000 { +- compatible = "fsl,imx1-iomuxc"; +- reg = <0x0021c000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gpio1: gpio@21c000 { +- compatible = "fsl,imx1-gpio"; +- reg = <0x0021c000 0x100>; +- interrupts = <11>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@21c100 { +- compatible = "fsl,imx1-gpio"; +- reg = <0x0021c100 0x100>; +- interrupts = <12>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio@21c200 { +- compatible = "fsl,imx1-gpio"; +- reg = <0x0021c200 0x100>; +- interrupts = <13>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio4: gpio@21c300 { +- compatible = "fsl,imx1-gpio"; +- reg = <0x0021c300 0x100>; +- interrupts = <62>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- }; +- +- weim: weim@220000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,imx1-weim"; +- reg = <0x00220000 0x1000>; +- clocks = <&clks IMX1_CLK_DUMMY>; +- ranges = < +- 0 0 0x10000000 0x02000000 +- 1 0 0x12000000 0x01000000 +- 2 0 0x13000000 0x01000000 +- 3 0 0x14000000 0x01000000 +- 4 0 0x15000000 0x01000000 +- 5 0 0x16000000 0x01000000 +- >; +- status = "disabled"; +- }; +- +- esram: esram@300000 { +- compatible = "mmio-sram"; +- reg = <0x00300000 0x20000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx23-evk.dts b/scripts/dtc/include-prefixes/arm/imx23-evk.dts +deleted file mode 100644 +index 3b609d987d88..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx23-evk.dts ++++ /dev/null +@@ -1,144 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2012 Freescale Semiconductor, Inc. +- +-/dts-v1/; +-#include "imx23.dtsi" +- +-/ { +- model = "Freescale i.MX23 Evaluation Kit"; +- compatible = "fsl,imx23-evk", "fsl,imx23"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x08000000>; +- }; +- +- reg_vddio_sd0: regulator-vddio-sd0 { +- compatible = "regulator-fixed"; +- regulator-name = "vddio-sd0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 29 0>; +- }; +- +- reg_lcd_3v3: regulator-lcd-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "lcd-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 18 0>; +- enable-active-high; +- }; +- +- reg_lcd_5v: regulator-lcd-5v { +- compatible = "regulator-fixed"; +- regulator-name = "lcd-5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- panel { +- compatible = "sii,43wvf1g"; +- backlight = <&backlight_display>; +- dvdd-supply = <®_lcd_3v3>; +- avdd-supply = <®_lcd_5v>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +- +- apb@80000000 { +- apbh@80000000 { +- nand-controller@8000c000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>; +- status = "okay"; +- }; +- +- ssp0: spi@80010000 { +- compatible = "fsl,imx23-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; +- bus-width = <4>; +- wp-gpios = <&gpio1 30 0>; +- vmmc-supply = <®_vddio_sd0>; +- status = "okay"; +- }; +- +- pinctrl@80018000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_a>; +- +- hog_pins_a: hog@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_LCD_RESET__GPIO_1_18 +- MX23_PAD_PWM3__GPIO_1_29 +- MX23_PAD_PWM4__GPIO_1_30 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- }; +- +- lcdif@80030000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcdif_24bit_pins_a>; +- status = "okay"; +- +- port { +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +- }; +- +- apbx@80040000 { +- lradc@80050000 { +- status = "okay"; +- fsl,lradc-touchscreen-wires = <4>; +- }; +- +- pwm: pwm@80064000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm2_pins_a>; +- status = "okay"; +- }; +- +- auart0: serial@8006c000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart0_pins_a>; +- status = "okay"; +- }; +- +- duart: serial@80070000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_pins_a>; +- status = "okay"; +- }; +- +- usbphy0: usbphy@8007c000 { +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb0: usb@80080000 { +- status = "okay"; +- }; +- }; +- +- backlight_display: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 2 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx23-olinuxino.dts b/scripts/dtc/include-prefixes/arm/imx23-olinuxino.dts +deleted file mode 100644 +index 0729e72f2283..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx23-olinuxino.dts ++++ /dev/null +@@ -1,131 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Freescale Semiconductor, Inc. +- * +- * Author: Fabio Estevam +- */ +- +-/dts-v1/; +-#include +-#include "imx23.dtsi" +- +-/ { +- model = "i.MX23 Olinuxino Low Cost Board"; +- compatible = "olimex,imx23-olinuxino", "fsl,imx23"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x04000000>; +- }; +- +- apb@80000000 { +- apbh@80000000 { +- ssp0: spi@80010000 { +- compatible = "fsl,imx23-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; +- bus-width = <4>; +- broken-cd; +- status = "okay"; +- }; +- +- pinctrl@80018000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_a>; +- +- hog_pins_a: hog@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_GPMI_ALE__GPIO_0_17 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- led_pin_gpio2_1: led_gpio2_1@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_SSP1_DETECT__GPIO_2_1 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- }; +- +- ssp1: spi@80034000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx23-spi"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pins_a>; +- status = "okay"; +- }; +- }; +- +- apbx@80040000 { +- lradc@80050000 { +- status = "okay"; +- }; +- +- i2c: i2c@80058000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_pins_b>; +- status = "okay"; +- }; +- +- duart: serial@80070000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_pins_a>; +- status = "okay"; +- }; +- +- auart0: serial@8006c000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart0_2pins_a>; +- status = "okay"; +- }; +- +- usbphy0: usbphy@8007c000 { +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb0: usb@80080000 { +- dr_mode = "host"; +- vbus-supply = <®_usb0_vbus>; +- status = "okay"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_usb0_vbus: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "usb0_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */ +- gpio = <&gpio0 17 0>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pin_gpio2_1>; +- +- user { +- label = "green"; +- gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx23-pinfunc.h b/scripts/dtc/include-prefixes/arm/imx23-pinfunc.h +deleted file mode 100644 +index 5c0f32ca3a93..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx23-pinfunc.h ++++ /dev/null +@@ -1,333 +0,0 @@ +-/* +- * Header providing constants for i.MX23 pinctrl bindings. +- * +- * Copyright (C) 2013 Lothar Waßmann +- * +- * The code contained herein is licensed under the GNU General Public +- * License. You may obtain a copy of the GNU General Public License +- * Version 2 at the following locations: +- * +- * http://www.opensource.org/licenses/gpl-license.html +- * http://www.gnu.org/copyleft/gpl.html +- */ +- +-#ifndef __DT_BINDINGS_MX23_PINCTRL_H__ +-#define __DT_BINDINGS_MX23_PINCTRL_H__ +- +-#include "mxs-pinfunc.h" +- +-#define MX23_PAD_GPMI_D00__GPMI_D00 0x0000 +-#define MX23_PAD_GPMI_D01__GPMI_D01 0x0010 +-#define MX23_PAD_GPMI_D02__GPMI_D02 0x0020 +-#define MX23_PAD_GPMI_D03__GPMI_D03 0x0030 +-#define MX23_PAD_GPMI_D04__GPMI_D04 0x0040 +-#define MX23_PAD_GPMI_D05__GPMI_D05 0x0050 +-#define MX23_PAD_GPMI_D06__GPMI_D06 0x0060 +-#define MX23_PAD_GPMI_D07__GPMI_D07 0x0070 +-#define MX23_PAD_GPMI_D08__GPMI_D08 0x0080 +-#define MX23_PAD_GPMI_D09__GPMI_D09 0x0090 +-#define MX23_PAD_GPMI_D10__GPMI_D10 0x00a0 +-#define MX23_PAD_GPMI_D11__GPMI_D11 0x00b0 +-#define MX23_PAD_GPMI_D12__GPMI_D12 0x00c0 +-#define MX23_PAD_GPMI_D13__GPMI_D13 0x00d0 +-#define MX23_PAD_GPMI_D14__GPMI_D14 0x00e0 +-#define MX23_PAD_GPMI_D15__GPMI_D15 0x00f0 +-#define MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100 +-#define MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110 +-#define MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 +-#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130 +-#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140 +-#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150 +-#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160 +-#define MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170 +-#define MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180 +-#define MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190 +-#define MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0 +-#define MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0 +-#define MX23_PAD_AUART1_RX__AUART1_RX 0x01c0 +-#define MX23_PAD_AUART1_TX__AUART1_TX 0x01d0 +-#define MX23_PAD_I2C_SCL__I2C_SCL 0x01e0 +-#define MX23_PAD_I2C_SDA__I2C_SDA 0x01f0 +-#define MX23_PAD_LCD_D00__LCD_D00 0x1000 +-#define MX23_PAD_LCD_D01__LCD_D01 0x1010 +-#define MX23_PAD_LCD_D02__LCD_D02 0x1020 +-#define MX23_PAD_LCD_D03__LCD_D03 0x1030 +-#define MX23_PAD_LCD_D04__LCD_D04 0x1040 +-#define MX23_PAD_LCD_D05__LCD_D05 0x1050 +-#define MX23_PAD_LCD_D06__LCD_D06 0x1060 +-#define MX23_PAD_LCD_D07__LCD_D07 0x1070 +-#define MX23_PAD_LCD_D08__LCD_D08 0x1080 +-#define MX23_PAD_LCD_D09__LCD_D09 0x1090 +-#define MX23_PAD_LCD_D10__LCD_D10 0x10a0 +-#define MX23_PAD_LCD_D11__LCD_D11 0x10b0 +-#define MX23_PAD_LCD_D12__LCD_D12 0x10c0 +-#define MX23_PAD_LCD_D13__LCD_D13 0x10d0 +-#define MX23_PAD_LCD_D14__LCD_D14 0x10e0 +-#define MX23_PAD_LCD_D15__LCD_D15 0x10f0 +-#define MX23_PAD_LCD_D16__LCD_D16 0x1100 +-#define MX23_PAD_LCD_D17__LCD_D17 0x1110 +-#define MX23_PAD_LCD_RESET__LCD_RESET 0x1120 +-#define MX23_PAD_LCD_RS__LCD_RS 0x1130 +-#define MX23_PAD_LCD_WR__LCD_WR 0x1140 +-#define MX23_PAD_LCD_CS__LCD_CS 0x1150 +-#define MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160 +-#define MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170 +-#define MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180 +-#define MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190 +-#define MX23_PAD_PWM0__PWM0 0x11a0 +-#define MX23_PAD_PWM1__PWM1 0x11b0 +-#define MX23_PAD_PWM2__PWM2 0x11c0 +-#define MX23_PAD_PWM3__PWM3 0x11d0 +-#define MX23_PAD_PWM4__PWM4 0x11e0 +-#define MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000 +-#define MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010 +-#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020 +-#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030 +-#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040 +-#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050 +-#define MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060 +-#define MX23_PAD_ROTARYA__ROTARYA 0x2070 +-#define MX23_PAD_ROTARYB__ROTARYB 0x2080 +-#define MX23_PAD_EMI_A00__EMI_A00 0x2090 +-#define MX23_PAD_EMI_A01__EMI_A01 0x20a0 +-#define MX23_PAD_EMI_A02__EMI_A02 0x20b0 +-#define MX23_PAD_EMI_A03__EMI_A03 0x20c0 +-#define MX23_PAD_EMI_A04__EMI_A04 0x20d0 +-#define MX23_PAD_EMI_A05__EMI_A05 0x20e0 +-#define MX23_PAD_EMI_A06__EMI_A06 0x20f0 +-#define MX23_PAD_EMI_A07__EMI_A07 0x2100 +-#define MX23_PAD_EMI_A08__EMI_A08 0x2110 +-#define MX23_PAD_EMI_A09__EMI_A09 0x2120 +-#define MX23_PAD_EMI_A10__EMI_A10 0x2130 +-#define MX23_PAD_EMI_A11__EMI_A11 0x2140 +-#define MX23_PAD_EMI_A12__EMI_A12 0x2150 +-#define MX23_PAD_EMI_BA0__EMI_BA0 0x2160 +-#define MX23_PAD_EMI_BA1__EMI_BA1 0x2170 +-#define MX23_PAD_EMI_CASN__EMI_CASN 0x2180 +-#define MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190 +-#define MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0 +-#define MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0 +-#define MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0 +-#define MX23_PAD_EMI_CKE__EMI_CKE 0x21d0 +-#define MX23_PAD_EMI_RASN__EMI_RASN 0x21e0 +-#define MX23_PAD_EMI_WEN__EMI_WEN 0x21f0 +-#define MX23_PAD_EMI_D00__EMI_D00 0x3000 +-#define MX23_PAD_EMI_D01__EMI_D01 0x3010 +-#define MX23_PAD_EMI_D02__EMI_D02 0x3020 +-#define MX23_PAD_EMI_D03__EMI_D03 0x3030 +-#define MX23_PAD_EMI_D04__EMI_D04 0x3040 +-#define MX23_PAD_EMI_D05__EMI_D05 0x3050 +-#define MX23_PAD_EMI_D06__EMI_D06 0x3060 +-#define MX23_PAD_EMI_D07__EMI_D07 0x3070 +-#define MX23_PAD_EMI_D08__EMI_D08 0x3080 +-#define MX23_PAD_EMI_D09__EMI_D09 0x3090 +-#define MX23_PAD_EMI_D10__EMI_D10 0x30a0 +-#define MX23_PAD_EMI_D11__EMI_D11 0x30b0 +-#define MX23_PAD_EMI_D12__EMI_D12 0x30c0 +-#define MX23_PAD_EMI_D13__EMI_D13 0x30d0 +-#define MX23_PAD_EMI_D14__EMI_D14 0x30e0 +-#define MX23_PAD_EMI_D15__EMI_D15 0x30f0 +-#define MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100 +-#define MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110 +-#define MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120 +-#define MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130 +-#define MX23_PAD_EMI_CLK__EMI_CLK 0x3140 +-#define MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150 +-#define MX23_PAD_GPMI_D00__LCD_D8 0x0001 +-#define MX23_PAD_GPMI_D01__LCD_D9 0x0011 +-#define MX23_PAD_GPMI_D02__LCD_D10 0x0021 +-#define MX23_PAD_GPMI_D03__LCD_D11 0x0031 +-#define MX23_PAD_GPMI_D04__LCD_D12 0x0041 +-#define MX23_PAD_GPMI_D05__LCD_D13 0x0051 +-#define MX23_PAD_GPMI_D06__LCD_D14 0x0061 +-#define MX23_PAD_GPMI_D07__LCD_D15 0x0071 +-#define MX23_PAD_GPMI_D08__LCD_D18 0x0081 +-#define MX23_PAD_GPMI_D09__LCD_D19 0x0091 +-#define MX23_PAD_GPMI_D10__LCD_D20 0x00a1 +-#define MX23_PAD_GPMI_D11__LCD_D21 0x00b1 +-#define MX23_PAD_GPMI_D12__LCD_D22 0x00c1 +-#define MX23_PAD_GPMI_D13__LCD_D23 0x00d1 +-#define MX23_PAD_GPMI_D14__AUART2_RX 0x00e1 +-#define MX23_PAD_GPMI_D15__AUART2_TX 0x00f1 +-#define MX23_PAD_GPMI_CLE__LCD_D16 0x0101 +-#define MX23_PAD_GPMI_ALE__LCD_D17 0x0111 +-#define MX23_PAD_GPMI_CE2N__ATA_A2 0x0121 +-#define MX23_PAD_AUART1_RTS__IR_CLK 0x01b1 +-#define MX23_PAD_AUART1_RX__IR_RX 0x01c1 +-#define MX23_PAD_AUART1_TX__IR_TX 0x01d1 +-#define MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1 +-#define MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1 +-#define MX23_PAD_LCD_D00__ETM_DA8 0x1001 +-#define MX23_PAD_LCD_D01__ETM_DA9 0x1011 +-#define MX23_PAD_LCD_D02__ETM_DA10 0x1021 +-#define MX23_PAD_LCD_D03__ETM_DA11 0x1031 +-#define MX23_PAD_LCD_D04__ETM_DA12 0x1041 +-#define MX23_PAD_LCD_D05__ETM_DA13 0x1051 +-#define MX23_PAD_LCD_D06__ETM_DA14 0x1061 +-#define MX23_PAD_LCD_D07__ETM_DA15 0x1071 +-#define MX23_PAD_LCD_D08__ETM_DA0 0x1081 +-#define MX23_PAD_LCD_D09__ETM_DA1 0x1091 +-#define MX23_PAD_LCD_D10__ETM_DA2 0x10a1 +-#define MX23_PAD_LCD_D11__ETM_DA3 0x10b1 +-#define MX23_PAD_LCD_D12__ETM_DA4 0x10c1 +-#define MX23_PAD_LCD_D13__ETM_DA5 0x10d1 +-#define MX23_PAD_LCD_D14__ETM_DA6 0x10e1 +-#define MX23_PAD_LCD_D15__ETM_DA7 0x10f1 +-#define MX23_PAD_LCD_RESET__ETM_TCTL 0x1121 +-#define MX23_PAD_LCD_RS__ETM_TCLK 0x1131 +-#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161 +-#define MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171 +-#define MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181 +-#define MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191 +-#define MX23_PAD_PWM0__ROTARYA 0x11a1 +-#define MX23_PAD_PWM1__ROTARYB 0x11b1 +-#define MX23_PAD_PWM2__GPMI_RDY3 0x11c1 +-#define MX23_PAD_PWM3__ETM_TCTL 0x11d1 +-#define MX23_PAD_PWM4__ETM_TCLK 0x11e1 +-#define MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011 +-#define MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031 +-#define MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041 +-#define MX23_PAD_ROTARYA__AUART2_RTS 0x2071 +-#define MX23_PAD_ROTARYB__AUART2_CTS 0x2081 +-#define MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002 +-#define MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012 +-#define MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022 +-#define MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032 +-#define MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042 +-#define MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052 +-#define MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062 +-#define MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072 +-#define MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082 +-#define MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092 +-#define MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2 +-#define MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2 +-#define MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2 +-#define MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132 +-#define MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142 +-#define MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182 +-#define MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2 +-#define MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2 +-#define MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2 +-#define MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2 +-#define MX23_PAD_I2C_SCL__AUART1_TX 0x01e2 +-#define MX23_PAD_I2C_SDA__AUART1_RX 0x01f2 +-#define MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082 +-#define MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092 +-#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2 +-#define MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2 +-#define MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2 +-#define MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2 +-#define MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2 +-#define MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2 +-#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102 +-#define MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122 +-#define MX23_PAD_PWM0__DUART_RX 0x11a2 +-#define MX23_PAD_PWM1__DUART_TX 0x11b2 +-#define MX23_PAD_PWM3__AUART1_CTS 0x11d2 +-#define MX23_PAD_PWM4__AUART1_RTS 0x11e2 +-#define MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002 +-#define MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012 +-#define MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022 +-#define MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032 +-#define MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042 +-#define MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052 +-#define MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062 +-#define MX23_PAD_ROTARYA__SPDIF 0x2072 +-#define MX23_PAD_ROTARYB__GPMI_CE3N 0x2082 +-#define MX23_PAD_GPMI_D00__GPIO_0_0 0x0003 +-#define MX23_PAD_GPMI_D01__GPIO_0_1 0x0013 +-#define MX23_PAD_GPMI_D02__GPIO_0_2 0x0023 +-#define MX23_PAD_GPMI_D03__GPIO_0_3 0x0033 +-#define MX23_PAD_GPMI_D04__GPIO_0_4 0x0043 +-#define MX23_PAD_GPMI_D05__GPIO_0_5 0x0053 +-#define MX23_PAD_GPMI_D06__GPIO_0_6 0x0063 +-#define MX23_PAD_GPMI_D07__GPIO_0_7 0x0073 +-#define MX23_PAD_GPMI_D08__GPIO_0_8 0x0083 +-#define MX23_PAD_GPMI_D09__GPIO_0_9 0x0093 +-#define MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3 +-#define MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3 +-#define MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3 +-#define MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3 +-#define MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3 +-#define MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3 +-#define MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103 +-#define MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113 +-#define MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123 +-#define MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133 +-#define MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143 +-#define MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153 +-#define MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163 +-#define MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173 +-#define MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183 +-#define MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193 +-#define MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3 +-#define MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3 +-#define MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3 +-#define MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3 +-#define MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3 +-#define MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3 +-#define MX23_PAD_LCD_D00__GPIO_1_0 0x1003 +-#define MX23_PAD_LCD_D01__GPIO_1_1 0x1013 +-#define MX23_PAD_LCD_D02__GPIO_1_2 0x1023 +-#define MX23_PAD_LCD_D03__GPIO_1_3 0x1033 +-#define MX23_PAD_LCD_D04__GPIO_1_4 0x1043 +-#define MX23_PAD_LCD_D05__GPIO_1_5 0x1053 +-#define MX23_PAD_LCD_D06__GPIO_1_6 0x1063 +-#define MX23_PAD_LCD_D07__GPIO_1_7 0x1073 +-#define MX23_PAD_LCD_D08__GPIO_1_8 0x1083 +-#define MX23_PAD_LCD_D09__GPIO_1_9 0x1093 +-#define MX23_PAD_LCD_D10__GPIO_1_10 0x10a3 +-#define MX23_PAD_LCD_D11__GPIO_1_11 0x10b3 +-#define MX23_PAD_LCD_D12__GPIO_1_12 0x10c3 +-#define MX23_PAD_LCD_D13__GPIO_1_13 0x10d3 +-#define MX23_PAD_LCD_D14__GPIO_1_14 0x10e3 +-#define MX23_PAD_LCD_D15__GPIO_1_15 0x10f3 +-#define MX23_PAD_LCD_D16__GPIO_1_16 0x1103 +-#define MX23_PAD_LCD_D17__GPIO_1_17 0x1113 +-#define MX23_PAD_LCD_RESET__GPIO_1_18 0x1123 +-#define MX23_PAD_LCD_RS__GPIO_1_19 0x1133 +-#define MX23_PAD_LCD_WR__GPIO_1_20 0x1143 +-#define MX23_PAD_LCD_CS__GPIO_1_21 0x1153 +-#define MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163 +-#define MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173 +-#define MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183 +-#define MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193 +-#define MX23_PAD_PWM0__GPIO_1_26 0x11a3 +-#define MX23_PAD_PWM1__GPIO_1_27 0x11b3 +-#define MX23_PAD_PWM2__GPIO_1_28 0x11c3 +-#define MX23_PAD_PWM3__GPIO_1_29 0x11d3 +-#define MX23_PAD_PWM4__GPIO_1_30 0x11e3 +-#define MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003 +-#define MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013 +-#define MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023 +-#define MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033 +-#define MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043 +-#define MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053 +-#define MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063 +-#define MX23_PAD_ROTARYA__GPIO_2_7 0x2073 +-#define MX23_PAD_ROTARYB__GPIO_2_8 0x2083 +-#define MX23_PAD_EMI_A00__GPIO_2_9 0x2093 +-#define MX23_PAD_EMI_A01__GPIO_2_10 0x20a3 +-#define MX23_PAD_EMI_A02__GPIO_2_11 0x20b3 +-#define MX23_PAD_EMI_A03__GPIO_2_12 0x20c3 +-#define MX23_PAD_EMI_A04__GPIO_2_13 0x20d3 +-#define MX23_PAD_EMI_A05__GPIO_2_14 0x20e3 +-#define MX23_PAD_EMI_A06__GPIO_2_15 0x20f3 +-#define MX23_PAD_EMI_A07__GPIO_2_16 0x2103 +-#define MX23_PAD_EMI_A08__GPIO_2_17 0x2113 +-#define MX23_PAD_EMI_A09__GPIO_2_18 0x2123 +-#define MX23_PAD_EMI_A10__GPIO_2_19 0x2133 +-#define MX23_PAD_EMI_A11__GPIO_2_20 0x2143 +-#define MX23_PAD_EMI_A12__GPIO_2_21 0x2153 +-#define MX23_PAD_EMI_BA0__GPIO_2_22 0x2163 +-#define MX23_PAD_EMI_BA1__GPIO_2_23 0x2173 +-#define MX23_PAD_EMI_CASN__GPIO_2_24 0x2183 +-#define MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193 +-#define MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3 +-#define MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3 +-#define MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3 +-#define MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3 +-#define MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3 +-#define MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3 +- +-#endif /* __DT_BINDINGS_MX23_PINCTRL_H__ */ +diff --git a/scripts/dtc/include-prefixes/arm/imx23-sansa.dts b/scripts/dtc/include-prefixes/arm/imx23-sansa.dts +deleted file mode 100644 +index 46057d9bf555..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx23-sansa.dts ++++ /dev/null +@@ -1,207 +0,0 @@ +-/* +- * Copyright (C) 2013-2016 Marek Vasut +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-/dts-v1/; +-#include +-#include "imx23.dtsi" +- +-/ { +- model = "SanDisk Sansa Fuze+"; +- compatible = "sandisk,sansa_fuze_plus", "fsl,imx23"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x04000000>; +- }; +- +- apb@80000000 { +- apbh@80000000 { +- ssp0: spi@80010000 { +- compatible = "fsl,imx23-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; +- bus-width = <4>; +- vmmc-supply = <®_vddio_sd0>; +- cd-inverted; +- status = "okay"; +- }; +- +- ssp1: spi@80034000 { +- compatible = "fsl,imx23-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_8bit_pins_a>; +- bus-width = <8>; +- vmmc-supply = <®_vddio_sd1>; +- non-removable; +- status = "okay"; +- }; +- +- pinctrl@80018000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_a>; +- +- hog_pins_a: hog@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_GPMI_D08__GPIO_0_8 +- MX23_PAD_PWM3__GPIO_1_29 +- MX23_PAD_AUART1_RTS__GPIO_0_27 +- MX23_PAD_AUART1_CTS__GPIO_0_26 +- MX23_PAD_I2C_SCL__I2C_SCL +- MX23_PAD_I2C_SDA__I2C_SDA +- MX23_PAD_LCD_DOTCK__GPIO_1_22 +- MX23_PAD_LCD_HSYNC__GPIO_1_24 +- MX23_PAD_PWM3__GPIO_1_29 +- >; +- fsl,drive-strength = <0>; +- fsl,voltage = <1>; +- fsl,pull-up = <0>; +- }; +- }; +- }; +- +- apbx@80040000 { +- pwm: pwm@80064000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm2_pins_a>; +- status = "okay"; +- }; +- +- duart: serial@80070000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_pins_a>; +- status = "okay"; +- }; +- +- usbphy0: usbphy@8007c000 { +- status = "okay"; +- }; +- +- lradc@80050000 { +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb0: usb@80080000 { +- dr_mode = "peripheral"; +- status = "okay"; +- }; +- }; +- +- reg_vddio_sd0: regulator-vddio-sd0 { +- compatible = "regulator-fixed"; +- regulator-name = "vddio-sd0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio0 8 0>; +- }; +- +- reg_vddio_sd1: regulator-vddio-sd1 { +- compatible = "regulator-fixed"; +- regulator-name = "vddio-sd1"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 29 0>; +- }; +- +- reg_vdd_touchpad: regulator-vdd-touchpad0 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-touchpad0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio0 26 GPIO_ACTIVE_LOW>; +- regulator-always-on; +- }; +- +- reg_vdd_tuner: regulator-vdd-tuner0 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-tuner0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio0 29 GPIO_ACTIVE_LOW>; +- regulator-always-on; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 2 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +- +- i2c-0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "i2c-gpio"; +- gpios = < +- &gpio1 24 0 /* SDA */ +- &gpio1 22 0 /* SCL */ +- >; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- }; +- +- i2c-1 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "i2c-gpio"; +- gpios = < +- &gpio0 31 0 /* SDA */ +- &gpio0 30 0 /* SCL */ +- >; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- +- touch: touch@20 { +- compatible = "synaptics,synaptics_i2c"; +- reg = <0x20>; +- }; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- pagesize = <32>; +- }; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx23-stmp378x_devb.dts b/scripts/dtc/include-prefixes/arm/imx23-stmp378x_devb.dts +deleted file mode 100644 +index da4b88f32eaa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx23-stmp378x_devb.dts ++++ /dev/null +@@ -1,76 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Freescale Semiconductor, Inc. +- */ +- +-/dts-v1/; +-#include "imx23.dtsi" +- +-/ { +- model = "Freescale STMP378x Development Board"; +- compatible = "fsl,stmp378x-devb", "fsl,imx23"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x04000000>; +- }; +- +- apb@80000000 { +- apbh@80000000 { +- ssp0: spi@80010000 { +- compatible = "fsl,imx23-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; +- bus-width = <4>; +- wp-gpios = <&gpio1 30 0>; +- vmmc-supply = <®_vddio_sd0>; +- status = "okay"; +- }; +- +- pinctrl@80018000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_a>; +- +- hog_pins_a: hog@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_PWM3__GPIO_1_29 +- MX23_PAD_PWM4__GPIO_1_30 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- }; +- }; +- +- apbx@80040000 { +- auart0: serial@8006c000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart0_pins_a>; +- status = "okay"; +- }; +- +- duart: serial@80070000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_pins_a>; +- status = "okay"; +- }; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_vddio_sd0: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "vddio-sd0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 29 0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx23-xfi3.dts b/scripts/dtc/include-prefixes/arm/imx23-xfi3.dts +deleted file mode 100644 +index a6213c590f94..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx23-xfi3.dts ++++ /dev/null +@@ -1,180 +0,0 @@ +-/* +- * Copyright (C) 2013-2016 Marek Vasut +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-/dts-v1/; +-#include "imx23.dtsi" +- +-/ { +- model = "Creative ZEN X-Fi3"; +- compatible = "creative,x-fi3", "fsl,imx23"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x04000000>; +- }; +- +- apb@80000000 { +- apbh@80000000 { +- ssp0: spi@80010000 { +- compatible = "fsl,imx23-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; +- bus-width = <4>; +- vmmc-supply = <®_vddio_sd0>; +- cd-inverted; +- status = "okay"; +- }; +- +- ssp1: spi@80034000 { +- compatible = "fsl,imx23-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_4bit_pins_a>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- }; +- +- pinctrl@80018000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_a>; +- +- hog_pins_a: hog@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_GPMI_D07__GPIO_0_7 +- >; +- fsl,drive-strength = <0>; +- fsl,voltage = <1>; +- fsl,pull-up = <0>; +- }; +- +- key_pins_a: keys@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_ROTARYA__GPIO_2_7 +- MX23_PAD_ROTARYB__GPIO_2_8 +- >; +- fsl,drive-strength = <0>; +- fsl,voltage = <1>; +- fsl,pull-up = <1>; +- }; +- }; +- }; +- +- apbx@80040000 { +- i2c: i2c@80058000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_pins_a>; +- status = "okay"; +- }; +- +- pwm: pwm@80064000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm2_pins_a>; +- status = "okay"; +- }; +- +- duart: serial@80070000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_pins_a>; +- status = "okay"; +- }; +- +- auart1: serial@8006e000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart1_2pins_a>; +- status = "okay"; +- }; +- +- usbphy0: usbphy@8007c000 { +- status = "okay"; +- }; +- +- lradc@80050000 { +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb0: usb@80080000 { +- dr_mode = "peripheral"; +- status = "okay"; +- }; +- }; +- +- reg_vddio_sd0: regulator-vddio-sd0 { +- compatible = "regulator-fixed"; +- regulator-name = "vddio-sd0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio0 7 0>; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 2 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&key_pins_a>; +- +- voldown { +- label = "volume-down"; +- linux,code = <114>; +- gpios = <&gpio2 7 0>; +- debounce-interval = <20>; +- }; +- +- volup { +- label = "volume-up"; +- linux,code = <115>; +- gpios = <&gpio2 8 0>; +- debounce-interval = <20>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx23.dtsi b/scripts/dtc/include-prefixes/arm/imx23.dtsi +deleted file mode 100644 +index 7f4c602454a5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx23.dtsi ++++ /dev/null +@@ -1,636 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2012 Freescale Semiconductor, Inc. +- +-#include "imx23-pinfunc.h" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- interrupt-parent = <&icoll>; +- /* +- * The decompressor and also some bootloaders rely on a +- * pre-existing /chosen node to be available to insert the +- * command line and merge other ATAGS info. +- */ +- chosen {}; +- +- aliases { +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- gpio2 = &gpio2; +- serial0 = &auart0; +- serial1 = &auart1; +- spi0 = &ssp0; +- spi1 = &ssp1; +- usbphy0 = &usbphy0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,arm926ej-s"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- apb@80000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x80000000 0x80000>; +- ranges; +- +- apbh@80000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x80000000 0x40000>; +- ranges; +- +- icoll: interrupt-controller@80000000 { +- compatible = "fsl,imx23-icoll", "fsl,icoll"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x80000000 0x2000>; +- }; +- +- dma_apbh: dma-apbh@80004000 { +- compatible = "fsl,imx23-dma-apbh"; +- reg = <0x80004000 0x2000>; +- interrupts = <0 14 20 0 +- 13 13 13 13>; +- interrupt-names = "empty", "ssp0", "ssp1", "empty", +- "gpmi0", "gpmi1", "gpmi2", "gpmi3"; +- #dma-cells = <1>; +- dma-channels = <8>; +- clocks = <&clks 15>; +- }; +- +- ecc@80008000 { +- reg = <0x80008000 0x2000>; +- status = "disabled"; +- }; +- +- nand-controller@8000c000 { +- compatible = "fsl,imx23-gpmi-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; +- reg-names = "gpmi-nand", "bch"; +- interrupts = <56>; +- interrupt-names = "bch"; +- clocks = <&clks 34>; +- clock-names = "gpmi_io"; +- dmas = <&dma_apbh 4>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- ssp0: spi@80010000 { +- reg = <0x80010000 0x2000>; +- interrupts = <15>; +- clocks = <&clks 33>; +- dmas = <&dma_apbh 1>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- etm@80014000 { +- reg = <0x80014000 0x2000>; +- status = "disabled"; +- }; +- +- pinctrl@80018000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx23-pinctrl", "simple-bus"; +- reg = <0x80018000 0x2000>; +- +- gpio0: gpio@0 { +- compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; +- reg = <0>; +- interrupts = <16>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio@1 { +- compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; +- reg = <1>; +- interrupts = <17>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@2 { +- compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; +- reg = <2>; +- interrupts = <18>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- duart_pins_a: duart@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_PWM0__DUART_RX +- MX23_PAD_PWM1__DUART_TX +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- auart0_pins_a: auart0@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_AUART1_RX__AUART1_RX +- MX23_PAD_AUART1_TX__AUART1_TX +- MX23_PAD_AUART1_CTS__AUART1_CTS +- MX23_PAD_AUART1_RTS__AUART1_RTS +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- auart0_2pins_a: auart0-2pins@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_I2C_SCL__AUART1_TX +- MX23_PAD_I2C_SDA__AUART1_RX +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- auart1_2pins_a: auart1-2pins@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_GPMI_D14__AUART2_RX +- MX23_PAD_GPMI_D15__AUART2_TX +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- gpmi_pins_a: gpmi-nand@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_GPMI_D00__GPMI_D00 +- MX23_PAD_GPMI_D01__GPMI_D01 +- MX23_PAD_GPMI_D02__GPMI_D02 +- MX23_PAD_GPMI_D03__GPMI_D03 +- MX23_PAD_GPMI_D04__GPMI_D04 +- MX23_PAD_GPMI_D05__GPMI_D05 +- MX23_PAD_GPMI_D06__GPMI_D06 +- MX23_PAD_GPMI_D07__GPMI_D07 +- MX23_PAD_GPMI_CLE__GPMI_CLE +- MX23_PAD_GPMI_ALE__GPMI_ALE +- MX23_PAD_GPMI_RDY0__GPMI_RDY0 +- MX23_PAD_GPMI_RDY1__GPMI_RDY1 +- MX23_PAD_GPMI_WPN__GPMI_WPN +- MX23_PAD_GPMI_WRN__GPMI_WRN +- MX23_PAD_GPMI_RDN__GPMI_RDN +- MX23_PAD_GPMI_CE1N__GPMI_CE1N +- MX23_PAD_GPMI_CE0N__GPMI_CE0N +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- gpmi_pins_fixup: gpmi-pins-fixup@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_GPMI_WPN__GPMI_WPN +- MX23_PAD_GPMI_WRN__GPMI_WRN +- MX23_PAD_GPMI_RDN__GPMI_RDN +- >; +- fsl,drive-strength = ; +- }; +- +- mmc0_4bit_pins_a: mmc0-4bit@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_SSP1_DATA0__SSP1_DATA0 +- MX23_PAD_SSP1_DATA1__SSP1_DATA1 +- MX23_PAD_SSP1_DATA2__SSP1_DATA2 +- MX23_PAD_SSP1_DATA3__SSP1_DATA3 +- MX23_PAD_SSP1_CMD__SSP1_CMD +- MX23_PAD_SSP1_SCK__SSP1_SCK +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mmc0_8bit_pins_a: mmc0-8bit@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_SSP1_DATA0__SSP1_DATA0 +- MX23_PAD_SSP1_DATA1__SSP1_DATA1 +- MX23_PAD_SSP1_DATA2__SSP1_DATA2 +- MX23_PAD_SSP1_DATA3__SSP1_DATA3 +- MX23_PAD_GPMI_D08__SSP1_DATA4 +- MX23_PAD_GPMI_D09__SSP1_DATA5 +- MX23_PAD_GPMI_D10__SSP1_DATA6 +- MX23_PAD_GPMI_D11__SSP1_DATA7 +- MX23_PAD_SSP1_CMD__SSP1_CMD +- MX23_PAD_SSP1_DETECT__SSP1_DETECT +- MX23_PAD_SSP1_SCK__SSP1_SCK +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mmc0_pins_fixup: mmc0-pins-fixup@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_SSP1_DETECT__SSP1_DETECT +- MX23_PAD_SSP1_SCK__SSP1_SCK +- >; +- fsl,pull-up = ; +- }; +- +- mmc0_sck_cfg: mmc0-sck-cfg@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_SSP1_SCK__SSP1_SCK +- >; +- fsl,pull-up = ; +- }; +- +- mmc1_4bit_pins_a: mmc1-4bit@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_GPMI_D00__SSP2_DATA0 +- MX23_PAD_GPMI_D01__SSP2_DATA1 +- MX23_PAD_GPMI_D02__SSP2_DATA2 +- MX23_PAD_GPMI_D03__SSP2_DATA3 +- MX23_PAD_GPMI_RDY1__SSP2_CMD +- MX23_PAD_GPMI_WRN__SSP2_SCK +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mmc1_8bit_pins_a: mmc1-8bit@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_GPMI_D00__SSP2_DATA0 +- MX23_PAD_GPMI_D01__SSP2_DATA1 +- MX23_PAD_GPMI_D02__SSP2_DATA2 +- MX23_PAD_GPMI_D03__SSP2_DATA3 +- MX23_PAD_GPMI_D04__SSP2_DATA4 +- MX23_PAD_GPMI_D05__SSP2_DATA5 +- MX23_PAD_GPMI_D06__SSP2_DATA6 +- MX23_PAD_GPMI_D07__SSP2_DATA7 +- MX23_PAD_GPMI_RDY1__SSP2_CMD +- MX23_PAD_GPMI_WRN__SSP2_SCK +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- pwm2_pins_a: pwm2@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_PWM2__PWM2 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_24bit_pins_a: lcdif-24bit@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_LCD_D00__LCD_D00 +- MX23_PAD_LCD_D01__LCD_D01 +- MX23_PAD_LCD_D02__LCD_D02 +- MX23_PAD_LCD_D03__LCD_D03 +- MX23_PAD_LCD_D04__LCD_D04 +- MX23_PAD_LCD_D05__LCD_D05 +- MX23_PAD_LCD_D06__LCD_D06 +- MX23_PAD_LCD_D07__LCD_D07 +- MX23_PAD_LCD_D08__LCD_D08 +- MX23_PAD_LCD_D09__LCD_D09 +- MX23_PAD_LCD_D10__LCD_D10 +- MX23_PAD_LCD_D11__LCD_D11 +- MX23_PAD_LCD_D12__LCD_D12 +- MX23_PAD_LCD_D13__LCD_D13 +- MX23_PAD_LCD_D14__LCD_D14 +- MX23_PAD_LCD_D15__LCD_D15 +- MX23_PAD_LCD_D16__LCD_D16 +- MX23_PAD_LCD_D17__LCD_D17 +- MX23_PAD_GPMI_D08__LCD_D18 +- MX23_PAD_GPMI_D09__LCD_D19 +- MX23_PAD_GPMI_D10__LCD_D20 +- MX23_PAD_GPMI_D11__LCD_D21 +- MX23_PAD_GPMI_D12__LCD_D22 +- MX23_PAD_GPMI_D13__LCD_D23 +- MX23_PAD_LCD_DOTCK__LCD_DOTCK +- MX23_PAD_LCD_ENABLE__LCD_ENABLE +- MX23_PAD_LCD_HSYNC__LCD_HSYNC +- MX23_PAD_LCD_VSYNC__LCD_VSYNC +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- spi2_pins_a: spi2@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_GPMI_WRN__SSP2_SCK +- MX23_PAD_GPMI_RDY1__SSP2_CMD +- MX23_PAD_GPMI_D00__SSP2_DATA0 +- MX23_PAD_GPMI_D03__SSP2_DATA3 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- i2c_pins_a: i2c@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX23_PAD_I2C_SCL__I2C_SCL +- MX23_PAD_I2C_SDA__I2C_SDA +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- i2c_pins_b: i2c@1 { +- reg = <1>; +- fsl,pinmux-ids = < +- MX23_PAD_LCD_ENABLE__I2C_SCL +- MX23_PAD_LCD_HSYNC__I2C_SDA +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- i2c_pins_c: i2c@2 { +- reg = <2>; +- fsl,pinmux-ids = < +- MX23_PAD_SSP1_DATA1__I2C_SCL +- MX23_PAD_SSP1_DATA2__I2C_SDA +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- }; +- +- digctl@8001c000 { +- compatible = "fsl,imx23-digctl"; +- reg = <0x8001c000 2000>; +- status = "disabled"; +- }; +- +- emi@80020000 { +- reg = <0x80020000 0x2000>; +- status = "disabled"; +- }; +- +- dma_apbx: dma-apbx@80024000 { +- compatible = "fsl,imx23-dma-apbx"; +- reg = <0x80024000 0x2000>; +- interrupts = <7 5 9 26 +- 19 0 25 23 +- 60 58 9 0 +- 0 0 0 0>; +- interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c", +- "saif0", "empty", "auart0-rx", "auart0-tx", +- "auart1-rx", "auart1-tx", "saif1", "empty", +- "empty", "empty", "empty", "empty"; +- #dma-cells = <1>; +- dma-channels = <16>; +- clocks = <&clks 16>; +- }; +- +- dcp: crypto@80028000 { +- compatible = "fsl,imx23-dcp"; +- reg = <0x80028000 0x2000>; +- interrupts = <53 54>; +- status = "okay"; +- }; +- +- pxp@8002a000 { +- reg = <0x8002a000 0x2000>; +- status = "disabled"; +- }; +- +- efuse@8002c000 { +- compatible = "fsl,imx23-ocotp", "fsl,ocotp"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x8002c000 0x2000>; +- clocks = <&clks 15>; +- }; +- +- axi-ahb@8002e000 { +- reg = <0x8002e000 0x2000>; +- status = "disabled"; +- }; +- +- lcdif@80030000 { +- compatible = "fsl,imx23-lcdif"; +- reg = <0x80030000 2000>; +- interrupts = <46 45>; +- clocks = <&clks 38>; +- status = "disabled"; +- }; +- +- ssp1: spi@80034000 { +- reg = <0x80034000 0x2000>; +- interrupts = <2>; +- clocks = <&clks 33>; +- dmas = <&dma_apbh 2>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- tvenc@80038000 { +- reg = <0x80038000 0x2000>; +- status = "disabled"; +- }; +- }; +- +- apbx@80040000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x80040000 0x40000>; +- ranges; +- +- clks: clkctrl@80040000 { +- compatible = "fsl,imx23-clkctrl", "fsl,clkctrl"; +- reg = <0x80040000 0x2000>; +- #clock-cells = <1>; +- }; +- +- saif0: saif@80042000 { +- reg = <0x80042000 0x2000>; +- dmas = <&dma_apbx 4>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- power@80044000 { +- reg = <0x80044000 0x2000>; +- status = "disabled"; +- }; +- +- saif1: saif@80046000 { +- reg = <0x80046000 0x2000>; +- dmas = <&dma_apbx 10>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- audio-out@80048000 { +- reg = <0x80048000 0x2000>; +- dmas = <&dma_apbx 1>; +- dma-names = "tx"; +- status = "disabled"; +- }; +- +- audio-in@8004c000 { +- reg = <0x8004c000 0x2000>; +- dmas = <&dma_apbx 0>; +- dma-names = "rx"; +- status = "disabled"; +- }; +- +- lradc: lradc@80050000 { +- compatible = "fsl,imx23-lradc"; +- reg = <0x80050000 0x2000>; +- interrupts = <36 37 38 39 40 41 42 43 44>; +- status = "disabled"; +- clocks = <&clks 26>; +- #io-channel-cells = <1>; +- }; +- +- spdif@80054000 { +- reg = <0x80054000 2000>; +- dmas = <&dma_apbx 2>; +- dma-names = "tx"; +- status = "disabled"; +- }; +- +- i2c: i2c@80058000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx23-i2c"; +- reg = <0x80058000 0x2000>; +- interrupts = <27>; +- clock-frequency = <100000>; +- dmas = <&dma_apbx 3>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- rtc@8005c000 { +- compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc"; +- reg = <0x8005c000 0x2000>; +- interrupts = <22>; +- }; +- +- pwm: pwm@80064000 { +- compatible = "fsl,imx23-pwm"; +- reg = <0x80064000 0x2000>; +- clocks = <&clks 30>; +- #pwm-cells = <2>; +- fsl,pwm-number = <5>; +- status = "disabled"; +- }; +- +- timrot@80068000 { +- compatible = "fsl,imx23-timrot", "fsl,timrot"; +- reg = <0x80068000 0x2000>; +- interrupts = <28 29 30 31>; +- clocks = <&clks 28>; +- }; +- +- auart0: serial@8006c000 { +- compatible = "fsl,imx23-auart"; +- reg = <0x8006c000 0x2000>; +- interrupts = <24>; +- clocks = <&clks 32>; +- dmas = <&dma_apbx 6>, <&dma_apbx 7>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- auart1: serial@8006e000 { +- compatible = "fsl,imx23-auart"; +- reg = <0x8006e000 0x2000>; +- interrupts = <59>; +- clocks = <&clks 32>; +- dmas = <&dma_apbx 8>, <&dma_apbx 9>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- duart: serial@80070000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x80070000 0x2000>; +- interrupts = <0>; +- clocks = <&clks 32>, <&clks 16>; +- clock-names = "uart", "apb_pclk"; +- status = "disabled"; +- }; +- +- usbphy0: usbphy@8007c000 { +- compatible = "fsl,imx23-usbphy"; +- reg = <0x8007c000 0x2000>; +- clocks = <&clks 41>; +- status = "disabled"; +- }; +- }; +- }; +- +- ahb@80080000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x80080000 0x80000>; +- ranges; +- +- usb0: usb@80080000 { +- compatible = "fsl,imx23-usb", "fsl,imx27-usb"; +- reg = <0x80080000 0x40000>; +- interrupts = <11>; +- fsl,usbphy = <&usbphy0>; +- clocks = <&clks 40>; +- status = "disabled"; +- }; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&lradc 8>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx25-eukrea-cpuimx25.dtsi b/scripts/dtc/include-prefixes/arm/imx25-eukrea-cpuimx25.dtsi +deleted file mode 100644 +index 0703f62d10d1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx25-eukrea-cpuimx25.dtsi ++++ /dev/null +@@ -1,66 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Eukréa Electromatique +- */ +- +-#include "imx25.dtsi" +- +-/ { +- model = "Eukrea CPUIMX25"; +- compatible = "eukrea,cpuimx25", "fsl,imx25"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x4000000>; /* 64M */ +- }; +-}; +- +-&fec { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pcf8563@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +-}; +- +-&iomuxc { +- imx25-eukrea-cpuimx25 { +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 +- MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 +- MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 +- MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 +- MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 +- MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 +- MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 +- MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 +- MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 +- MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 +- >; +- }; +- }; +-}; +- +-&nfc { +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-on-flash-bbt; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts b/scripts/dtc/include-prefixes/arm/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts +deleted file mode 100644 +index 7d4301b22b90..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts ++++ /dev/null +@@ -1,65 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Eukréa Electromatique +- */ +- +-#include "imx25-eukrea-mbimxsd25-baseboard.dts" +- +-/ { +- model = "Eukrea MBIMXSD25 with the CMO-QVGA Display"; +- compatible = "eukrea,mbimxsd25-baseboard-cmo-qvga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; +- +- cmo_qvga: display { +- model = "CMO-QVGA"; +- bits-per-pixel = <16>; +- fsl,pcr = <0xcad08b80>; +- bus-width = <18>; +- display-timings { +- native-mode = <&qvga_timings>; +- qvga_timings: 320x240 { +- clock-frequency = <6500000>; +- hactive = <320>; +- vactive = <240>; +- hback-porch = <30>; +- hfront-porch = <38>; +- vback-porch = <20>; +- vfront-porch = <3>; +- hsync-len = <15>; +- vsync-len = <4>; +- }; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_lcd_3v3: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_lcd_3v3>; +- regulator-name = "lcd-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- }; +-}; +- +-&iomuxc { +- imx25-eukrea-mbimxsd25-baseboard-cmo-qvga { +- pinctrl_reg_lcd_3v3: reg_lcd_3v3 { +- fsl,pins = ; +- }; +- }; +-}; +- +-&lcdc { +- display = <&cmo_qvga>; +- fsl,lpccr = <0x00a903ff>; +- lcd-supply = <®_lcd_3v3>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts b/scripts/dtc/include-prefixes/arm/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts +deleted file mode 100644 +index 80a7f96de4c6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Eukréa Electromatique +- */ +- +-#include "imx25-eukrea-mbimxsd25-baseboard.dts" +- +-/ { +- model = "Eukrea MBIMXSD25 with the DVI-SVGA Display"; +- compatible = "eukrea,mbimxsd25-baseboard-dvi-svga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; +- +- dvi_svga: display { +- model = "DVI-SVGA"; +- bits-per-pixel = <16>; +- fsl,pcr = <0xfa208b80>; +- bus-width = <18>; +- display-timings { +- native-mode = <&dvi_svga_timings>; +- dvi_svga_timings: 800x600 { +- clock-frequency = <40000000>; +- hactive = <800>; +- vactive = <600>; +- hback-porch = <75>; +- hfront-porch = <75>; +- vback-porch = <7>; +- vfront-porch = <75>; +- hsync-len = <7>; +- vsync-len = <7>; +- }; +- }; +- }; +-}; +- +-&lcdc { +- display = <&dvi_svga>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts b/scripts/dtc/include-prefixes/arm/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts +deleted file mode 100644 +index 24027a1fb46d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Eukréa Electromatique +- */ +- +-#include "imx25-eukrea-mbimxsd25-baseboard.dts" +- +-/ { +- model = "Eukrea MBIMXSD25 with the DVI-VGA Display"; +- compatible = "eukrea,mbimxsd25-baseboard-dvi-vga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; +- +- dvi_vga: display { +- model = "DVI-VGA"; +- bits-per-pixel = <16>; +- fsl,pcr = <0xfa208b80>; +- bus-width = <18>; +- display-timings { +- native-mode = <&dvi_vga_timings>; +- dvi_vga_timings: 640x480 { +- clock-frequency = <31250000>; +- hactive = <640>; +- vactive = <480>; +- hback-porch = <100>; +- hfront-porch = <100>; +- vback-porch = <7>; +- vfront-porch = <100>; +- hsync-len = <7>; +- vsync-len = <7>; +- }; +- }; +- }; +-}; +- +-&lcdc { +- display = <&dvi_vga>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx25-eukrea-mbimxsd25-baseboard.dts b/scripts/dtc/include-prefixes/arm/imx25-eukrea-mbimxsd25-baseboard.dts +deleted file mode 100644 +index 3f38c2e60a74..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx25-eukrea-mbimxsd25-baseboard.dts ++++ /dev/null +@@ -1,174 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Eukréa Electromatique +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "imx25-eukrea-cpuimx25.dtsi" +- +-/ { +- model = "Eukrea MBIMXSD25"; +- compatible = "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; +- +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpiokeys>; +- +- bp1 { +- label = "BP1"; +- gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpioled>; +- +- led1 { +- label = "led1"; +- gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- sound { +- compatible = "eukrea,asoc-tlv320"; +- eukrea,model = "imx25-eukrea-tlv320aic23"; +- ssi-controller = <&ssi1>; +- fsl,mux-int-port = <1>; +- fsl,mux-ext-port = <5>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- cd-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&i2c1 { +- tlv320aic23: codec@1a { +- compatible = "ti,tlv320aic23"; +- reg = <0x1a>; +- }; +-}; +- +-&iomuxc { +- imx25-eukrea-mbimxsd25-baseboard { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0 +- MX25_PAD_KPP_COL2__AUD5_TXC 0xe0 +- MX25_PAD_KPP_COL1__AUD5_RXD 0xe0 +- MX25_PAD_KPP_COL0__AUD5_TXD 0xe0 +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX25_PAD_SD1_CMD__ESDHC1_CMD 0x400000c0 +- MX25_PAD_SD1_CLK__ESDHC1_CLK 0x400000c0 +- MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x400000c0 +- MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x400000c0 +- MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x400000c0 +- MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x400000c0 +- >; +- }; +- +- pinctrl_gpiokeys: gpiokeysgrp { +- fsl,pins = ; +- }; +- +- pinctrl_gpioled: gpioledgrp { +- fsl,pins = ; +- }; +- +- pinctrl_lcdc: lcdcgrp { +- fsl,pins = < +- MX25_PAD_LD0__LD0 0x1 +- MX25_PAD_LD1__LD1 0x1 +- MX25_PAD_LD2__LD2 0x1 +- MX25_PAD_LD3__LD3 0x1 +- MX25_PAD_LD4__LD4 0x1 +- MX25_PAD_LD5__LD5 0x1 +- MX25_PAD_LD6__LD6 0x1 +- MX25_PAD_LD7__LD7 0x1 +- MX25_PAD_LD8__LD8 0x1 +- MX25_PAD_LD9__LD9 0x1 +- MX25_PAD_LD10__LD10 0x1 +- MX25_PAD_LD11__LD11 0x1 +- MX25_PAD_LD12__LD12 0x1 +- MX25_PAD_LD13__LD13 0x1 +- MX25_PAD_LD14__LD14 0x1 +- MX25_PAD_LD15__LD15 0x1 +- MX25_PAD_GPIO_E__LD16 0x1 +- MX25_PAD_GPIO_F__LD17 0x1 +- MX25_PAD_HSYNC__HSYNC 0x80000000 +- MX25_PAD_VSYNC__VSYNC 0x80000000 +- MX25_PAD_LSCLK__LSCLK 0x80000000 +- MX25_PAD_OE_ACD__OE_ACD 0x80000000 +- MX25_PAD_CONTRAST__CONTRAST 0x80000000 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX25_PAD_UART1_RTS__UART1_RTS 0xe0 +- MX25_PAD_UART1_CTS__UART1_CTS 0xe0 +- MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 +- MX25_PAD_UART1_RXD__UART1_RXD 0xc0 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX25_PAD_UART2_RXD__UART2_RXD 0x80000000 +- MX25_PAD_UART2_TXD__UART2_TXD 0x80000000 +- MX25_PAD_UART2_RTS__UART2_RTS 0x80000000 +- MX25_PAD_UART2_CTS__UART2_CTS 0x80000000 +- >; +- }; +- }; +-}; +- +-&ssi1 { +- codec-handle = <&tlv320aic23>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbhost1 { +- status = "okay"; +-}; +- +-&usbotg { +- external-vbus-divider; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx25-karo-tx25.dts b/scripts/dtc/include-prefixes/arm/imx25-karo-tx25.dts +deleted file mode 100644 +index 0950eb66d3d9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx25-karo-tx25.dts ++++ /dev/null +@@ -1,108 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Sascha Hauer, Pengutronix +- */ +- +-/dts-v1/; +-#include "imx25.dtsi" +- +-/ { +- model = "Ka-Ro TX25"; +- compatible = "karo,imx25-tx25", "fsl,imx25"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_fec_phy: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "fec-phy"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio4 9 0>; +- enable-active-high; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x02000000 0x90000000 0x02000000>; +- }; +-}; +- +-&iomuxc { +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 +- MX25_PAD_UART1_RXD__UART1_RXD 0x80000000 +- MX25_PAD_UART1_CTS__UART1_CTS 0x80000000 +- MX25_PAD_UART1_RTS__UART1_RTS 0x80000000 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */ +- MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */ +- MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 +- MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000 +- MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 +- MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 +- MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 +- MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 +- MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 +- MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 +- MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 +- >; +- }; +- +- pinctrl_nfc: nfcgrp { +- fsl,pins = < +- MX25_PAD_NF_CE0__NF_CE0 0x80000000 +- MX25_PAD_NFWE_B__NFWE_B 0x80000000 +- MX25_PAD_NFRE_B__NFRE_B 0x80000000 +- MX25_PAD_NFALE__NFALE 0x80000000 +- MX25_PAD_NFCLE__NFCLE 0x80000000 +- MX25_PAD_NFWP_B__NFWP_B 0x80000000 +- MX25_PAD_NFRB__NFRB 0x80000000 +- MX25_PAD_D7__D7 0x80000000 +- MX25_PAD_D6__D6 0x80000000 +- MX25_PAD_D5__D5 0x80000000 +- MX25_PAD_D4__D4 0x80000000 +- MX25_PAD_D3__D3 0x80000000 +- MX25_PAD_D2__D2 0x80000000 +- MX25_PAD_D1__D1 0x80000000 +- MX25_PAD_D0__D0 0x80000000 +- >; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; +- phy-mode = "rmii"; +- phy-supply = <®_fec_phy>; +- status = "okay"; +-}; +- +-&nfc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nfc>; +- nand-on-flash-bbt; +- nand-ecc-mode = "hw"; +- nand-bus-width = <8>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx25-pdk.dts b/scripts/dtc/include-prefixes/arm/imx25-pdk.dts +deleted file mode 100644 +index fb66884d8a2f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx25-pdk.dts ++++ /dev/null +@@ -1,313 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2013 Freescale Semiconductor, Inc. +- +-/dts-v1/; +-#include +-#include +-#include "imx25.dtsi" +- +-/ { +- model = "Freescale i.MX25 Product Development Kit"; +- compatible = "fsl,imx25-pdk", "fsl,imx25"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x4000000>; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_fec_3v3: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "fec-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 3 0>; +- enable-active-high; +- }; +- +- reg_2p5v: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- }; +- +- reg_3p3v: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_can_3v3: regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- regulator-name = "can-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio4 6 0>; +- }; +- }; +- +- sound { +- compatible = "fsl,imx25-pdk-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "imx25-pdk-sgtl5000"; +- ssi-controller = <&ssi1>; +- audio-codec = <&codec>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <4>; +- }; +- +- wvga: display { +- model = "CLAA057VC01CW"; +- bits-per-pixel = <16>; +- fsl,pcr = <0xfa208b80>; +- bus-width = <18>; +- display-timings { +- native-mode = <&wvga_timings>; +- wvga_timings: 640x480 { +- hactive = <640>; +- vactive = <480>; +- hback-porch = <45>; +- hfront-porch = <114>; +- hsync-len = <1>; +- vback-porch = <33>; +- vfront-porch = <11>; +- vsync-len = <1>; +- clock-frequency = <25200000>; +- }; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- xceiver-supply = <®_can_3v3>; +- status = "okay"; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&fec { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-supply = <®_fec_3v3>; +- phy-reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- codec: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&clks 129>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_3p3v>; +- }; +-}; +- +-&iomuxc { +- imx25-pdk { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX25_PAD_RW__AUD4_TXFS 0xe0 +- MX25_PAD_OE__AUD4_TXC 0xe0 +- MX25_PAD_EB0__AUD4_TXD 0xe0 +- MX25_PAD_EB1__AUD4_RXD 0xe0 +- >; +- }; +- +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX25_PAD_GPIO_A__CAN1_TX 0x0 +- MX25_PAD_GPIO_B__CAN1_RX 0x0 +- MX25_PAD_D14__GPIO_4_6 0x80000000 +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX25_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 +- MX25_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 +- MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 +- MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 +- MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 +- MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 +- MX25_PAD_A14__GPIO_2_0 0x80000000 +- MX25_PAD_A15__GPIO_2_1 0x80000000 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 +- MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 +- MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 +- MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 +- MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 +- MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 +- MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 +- MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 +- MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 +- MX25_PAD_A17__GPIO_2_3 0x80000000 +- MX25_PAD_D12__GPIO_4_8 0x80000000 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 +- MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 +- >; +- }; +- +- pinctrl_kpp: kppgrp { +- fsl,pins = < +- MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000 +- MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000 +- MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000 +- MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000 +- MX25_PAD_KPP_COL0__KPP_COL0 0x80000000 +- MX25_PAD_KPP_COL1__KPP_COL1 0x80000000 +- MX25_PAD_KPP_COL2__KPP_COL2 0x80000000 +- MX25_PAD_KPP_COL3__KPP_COL3 0x80000000 +- >; +- }; +- +- pinctrl_lcd: lcdgrp { +- fsl,pins = < +- MX25_PAD_LD0__LD0 0xe0 +- MX25_PAD_LD1__LD1 0xe0 +- MX25_PAD_LD2__LD2 0xe0 +- MX25_PAD_LD3__LD3 0xe0 +- MX25_PAD_LD4__LD4 0xe0 +- MX25_PAD_LD5__LD5 0xe0 +- MX25_PAD_LD6__LD6 0xe0 +- MX25_PAD_LD7__LD7 0xe0 +- MX25_PAD_LD8__LD8 0xe0 +- MX25_PAD_LD9__LD9 0xe0 +- MX25_PAD_LD10__LD10 0xe0 +- MX25_PAD_LD11__LD11 0xe0 +- MX25_PAD_LD12__LD12 0xe0 +- MX25_PAD_LD13__LD13 0xe0 +- MX25_PAD_LD14__LD14 0xe0 +- MX25_PAD_LD15__LD15 0xe0 +- MX25_PAD_GPIO_E__LD16 0xe0 +- MX25_PAD_GPIO_F__LD17 0xe0 +- MX25_PAD_HSYNC__HSYNC 0xe0 +- MX25_PAD_VSYNC__VSYNC 0xe0 +- MX25_PAD_LSCLK__LSCLK 0xe0 +- MX25_PAD_OE_ACD__OE_ACD 0xe0 +- MX25_PAD_CONTRAST__CONTRAST 0xe0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX25_PAD_UART1_RTS__UART1_RTS 0xe0 +- MX25_PAD_UART1_CTS__UART1_CTS 0xe0 +- MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 +- MX25_PAD_UART1_RXD__UART1_RXD 0xc0 +- >; +- }; +- }; +-}; +- +-&lcdc { +- display = <&wvga>; +- fsl,lpccr = <0x00a903ff>; +- fsl,lscr1 = <0x00120300>; +- fsl,dmacr = <0x00020010>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd>; +- status = "okay"; +-}; +- +-&nfc { +- nand-on-flash-bbt; +- status = "okay"; +-}; +- +-&kpp { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_kpp>; +- linux,keymap = < +- MATRIX_KEY(0x0, 0x0, KEY_UP) +- MATRIX_KEY(0x0, 0x1, KEY_DOWN) +- MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN) +- MATRIX_KEY(0x0, 0x3, KEY_HOME) +- MATRIX_KEY(0x1, 0x0, KEY_RIGHT) +- MATRIX_KEY(0x1, 0x1, KEY_LEFT) +- MATRIX_KEY(0x1, 0x2, KEY_ENTER) +- MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP) +- MATRIX_KEY(0x2, 0x0, KEY_F6) +- MATRIX_KEY(0x2, 0x1, KEY_F8) +- MATRIX_KEY(0x2, 0x2, KEY_F9) +- MATRIX_KEY(0x2, 0x3, KEY_F10) +- MATRIX_KEY(0x3, 0x0, KEY_F1) +- MATRIX_KEY(0x3, 0x1, KEY_F2) +- MATRIX_KEY(0x3, 0x2, KEY_F3) +- MATRIX_KEY(0x3, 0x2, KEY_POWER) +- >; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&tsc { +- status = "okay"; +-}; +- +-&tscadc { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbhost1 { +- status = "okay"; +-}; +- +-&usbotg { +- external-vbus-divider; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx25-pinfunc.h b/scripts/dtc/include-prefixes/arm/imx25-pinfunc.h +deleted file mode 100644 +index 908caf810351..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx25-pinfunc.h ++++ /dev/null +@@ -1,652 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2013 Eukréa Electromatique +- * Based on imx35-pinfunc.h in the same directory Which is: +- * Copyright 2013 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __DTS_IMX25_PINFUNC_H +-#define __DTS_IMX25_PINFUNC_H +- +-/* +- * The pin function ID is a tuple of +- * +- */ +- +-#define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 +-#define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 +- +-#define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 +-#define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 +-#define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000 +- +-#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000 +-#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000 +-#define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000 +-#define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000 +- +-#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000 +-#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x05 0x000 +-#define MX25_PAD_A15__SIM1_RST1 0x014 0x234 0x000 0x06 0x000 +-#define MX25_PAD_A15__LCDC_PS 0x014 0x234 0x000 0x07 0x000 +- +-#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x00 0x000 +-#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x05 0x000 +-#define MX25_PAD_A16__SIM1_VEN1 0x018 0x000 0x000 0x06 0x000 +-#define MX25_PAD_A16__LCDC_REV 0x018 0x000 0x000 0x07 0x000 +- +-#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x00 0x000 +-#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x05 0x000 +-#define MX25_PAD_A17__SIM1_TX 0x01c 0x238 0x554 0x06 0x000 +-#define MX25_PAD_A17__FEC_TX_ERR 0x01c 0x238 0x000 0x07 0x000 +- +-#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x00 0x000 +-#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x05 0x000 +-#define MX25_PAD_A18__SIM1_PD1 0x020 0x23c 0x550 0x06 0x000 +-#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x07 0x000 +- +-#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x00 0x000 +-#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x05 0x000 +-#define MX25_PAD_A19__SIM1_RX1 0x024 0x240 0x54c 0x06 0x000 +-#define MX25_PAD_A19__FEC_RX_ERR 0x024 0x240 0x518 0x07 0x000 +- +-#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x00 0x000 +-#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x05 0x000 +-#define MX25_PAD_A20__SIM2_CLK1 0x028 0x244 0x000 0x06 0x000 +-#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x07 0x000 +- +-#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x00 0x000 +-#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x05 0x000 +-#define MX25_PAD_A21__SIM2_RST1 0x02c 0x248 0x000 0x06 0x000 +-#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x07 0x000 +- +-#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x00 0x000 +-#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x05 0x000 +-#define MX25_PAD_A22__SIM2_VEN1 0x030 0x000 0x000 0x06 0x000 +-#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x07 0x000 +- +-#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x00 0x000 +-#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x05 0x000 +-#define MX25_PAD_A23__SIM2_TX1 0x034 0x24c 0x560 0x06 0x000 +-#define MX25_PAD_A23__FEC_TDATA3 0x034 0x24c 0x000 0x07 0x000 +- +-#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x00 0x000 +-#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x05 0x000 +-#define MX25_PAD_A24__SIM2_PD1 0x038 0x250 0x55c 0x06 0x000 +-#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x07 0x000 +- +-#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x00 0x000 +-#define MX25_PAD_A25__GPIO_2_11 0x03c 0x254 0x000 0x05 0x000 +-#define MX25_PAD_A25__FEC_CRS 0x03c 0x254 0x508 0x07 0x000 +- +-#define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x00 0x000 +-#define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x04 0x000 +-#define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x05 0x000 +-#define MX25_PAD_EB0__CSPI3_SS0 0x040 0x258 0x4bc 0x06 0x000 +- +-#define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x00 0x000 +-#define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x04 0x000 +-#define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x05 0x000 +-#define MX25_PAD_EB1__CSPI3_SS1 0x044 0x25c 0x4c0 0x06 0x000 +- +-#define MX25_PAD_OE__OE 0x048 0x260 0x000 0x00 0x000 +-#define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x04 0x000 +-#define MX25_PAD_OE__GPIO_2_14 0x048 0x260 0x000 0x05 0x000 +- +-#define MX25_PAD_CS0__CS0 0x04c 0x000 0x000 0x00 0x000 +-#define MX25_PAD_CS0__GPIO_4_2 0x04c 0x000 0x000 0x05 0x000 +- +-#define MX25_PAD_CS1__CS1 0x050 0x000 0x000 0x00 0x000 +-#define MX25_PAD_CS1__NF_CE3 0x050 0x000 0x000 0x01 0x000 +-#define MX25_PAD_CS1__GPIO_4_3 0x050 0x000 0x000 0x05 0x000 +- +-#define MX25_PAD_CS4__CS4 0x054 0x264 0x000 0x00 0x000 +-#define MX25_PAD_CS4__NF_CE1 0x054 0x264 0x000 0x01 0x000 +-#define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x03 0x000 +-#define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x05 0x000 +-#define MX25_PAD_CS4__CSPI3_MOSI 0x054 0x264 0x4b8 0x06 0x000 +- +-#define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x00 0x000 +-#define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000 +-#define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x03 0x000 +-#define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x05 0x000 +-#define MX25_PAD_CS5__CSPI3_MISO 0x058 0x268 0x4b4 0x06 0x000 +- +-#define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x00 0x000 +-#define MX25_PAD_NF_CE0__CSPI1_SS3 0x05c 0x26c 0x490 0x01 0x000 +-#define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x05 0x000 +- +-#define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x00 0x000 +-#define MX25_PAD_ECB__UART5_TXD 0x060 0x270 0x000 0x03 0x000 +-#define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x05 0x000 +-#define MX25_PAD_ECB__CSPI3_SCLK 0x060 0x270 0x4ac 0x06 0x000 +- +-#define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x00 0x000 +-#define MX25_PAD_LBA__UART5_RXD 0x064 0x274 0x578 0x03 0x000 +-#define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x05 0x000 +-#define MX25_PAD_LBA__CSPI3_RDY 0x064 0x274 0x4b0 0x06 0x000 +- +-#define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000 +-#define MX25_PAD_BCLK__GPIO_4_4 0x068 0x000 0x000 0x05 0x000 +- +-#define MX25_PAD_RW__RW 0x06c 0x278 0x000 0x00 0x000 +-#define MX25_PAD_RW__AUD4_TXFS 0x06c 0x278 0x474 0x04 0x000 +-#define MX25_PAD_RW__GPIO_3_25 0x06c 0x278 0x000 0x05 0x000 +- +-#define MX25_PAD_NFWE_B__NFWE_B 0x070 0x000 0x000 0x00 0x000 +-#define MX25_PAD_NFWE_B__GPIO_3_26 0x070 0x000 0x000 0x05 0x000 +- +-#define MX25_PAD_NFRE_B__NFRE_B 0x074 0x000 0x000 0x00 0x000 +-#define MX25_PAD_NFRE_B__GPIO_3_27 0x074 0x000 0x000 0x05 0x000 +- +-#define MX25_PAD_NFALE__NFALE 0x078 0x000 0x000 0x00 0x000 +-#define MX25_PAD_NFALE__GPIO_3_28 0x078 0x000 0x000 0x05 0x000 +- +-#define MX25_PAD_NFCLE__NFCLE 0x07c 0x000 0x000 0x00 0x000 +-#define MX25_PAD_NFCLE__GPIO_3_29 0x07c 0x000 0x000 0x05 0x000 +- +-#define MX25_PAD_NFWP_B__NFWP_B 0x080 0x000 0x000 0x00 0x000 +-#define MX25_PAD_NFWP_B__GPIO_3_30 0x080 0x000 0x000 0x05 0x000 +- +-#define MX25_PAD_NFRB__NFRB 0x084 0x27c 0x000 0x00 0x000 +-#define MX25_PAD_NFRB__GPIO_3_31 0x084 0x27c 0x000 0x05 0x000 +- +-#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000 +-#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000 +-#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000 +-#define MX25_PAD_D15__ESDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000 +- +-#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000 +-#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000 +-#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000 +-#define MX25_PAD_D14__ESDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000 +- +-#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000 +-#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000 +-#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000 +-#define MX25_PAD_D13__ESDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000 +- +-#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000 +-#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000 +-#define MX25_PAD_D12__ESDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000 +- +-#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000 +-#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000 +-#define MX25_PAD_D11__USBOTG_PWR 0x098 0x290 0x000 0x06 0x000 +- +-#define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000 +-#define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000 +-#define MX25_PAD_D10__USBOTG_OC 0x09c 0x294 0x57c 0x06 0x000 +- +-#define MX25_PAD_D9__D9 0x0a0 0x298 0x000 0x00 0x000 +-#define MX25_PAD_D9__GPIO_4_11 0x0a0 0x298 0x000 0x05 0x000 +-#define MX25_PAD_D9__USBH2_PWR 0x0a0 0x298 0x000 0x06 0x000 +- +-#define MX25_PAD_D8__D8 0x0a4 0x29c 0x000 0x00 0x000 +-#define MX25_PAD_D8__GPIO_4_12 0x0a4 0x29c 0x000 0x05 0x000 +-#define MX25_PAD_D8__USBH2_OC 0x0a4 0x29c 0x580 0x06 0x000 +- +-#define MX25_PAD_D7__D7 0x0a8 0x2a0 0x000 0x00 0x000 +-#define MX25_PAD_D7__GPIO_4_13 0x0a8 0x2a0 0x000 0x05 0x000 +- +-#define MX25_PAD_D6__D6 0x0ac 0x2a4 0x000 0x00 0x000 +-#define MX25_PAD_D6__GPIO_4_14 0x0ac 0x2a4 0x000 0x05 0x000 +- +-#define MX25_PAD_D5__D5 0x0b0 0x2a8 0x000 0x00 0x000 +-#define MX25_PAD_D5__GPIO_4_15 0x0b0 0x2a8 0x000 0x05 0x000 +- +-#define MX25_PAD_D4__D4 0x0b4 0x2ac 0x000 0x00 0x000 +-#define MX25_PAD_D4__GPIO_4_16 0x0b4 0x2ac 0x000 0x05 0x000 +- +-#define MX25_PAD_D3__D3 0x0b8 0x2b0 0x000 0x00 0x000 +-#define MX25_PAD_D3__GPIO_4_17 0x0b8 0x2b0 0x000 0x05 0x000 +- +-#define MX25_PAD_D2__D2 0x0bc 0x2b4 0x000 0x00 0x000 +-#define MX25_PAD_D2__GPIO_4_18 0x0bc 0x2b4 0x000 0x05 0x000 +- +-#define MX25_PAD_D1__D1 0x0c0 0x2b8 0x000 0x00 0x000 +-#define MX25_PAD_D1__GPIO_4_19 0x0c0 0x2b8 0x000 0x05 0x000 +- +-#define MX25_PAD_D0__D0 0x0c4 0x2bc 0x000 0x00 0x000 +-#define MX25_PAD_D0__GPIO_4_20 0x0c4 0x2bc 0x000 0x05 0x000 +- +-#define MX25_PAD_LD0__LD0 0x0c8 0x2c0 0x000 0x00 0x000 +-#define MX25_PAD_LD0__CSI_D0 0x0c8 0x2c0 0x488 0x02 0x000 +-#define MX25_PAD_LD0__GPIO_2_15 0x0c8 0x2c0 0x000 0x05 0x000 +- +-#define MX25_PAD_LD1__LD1 0x0cc 0x2c4 0x000 0x00 0x000 +-#define MX25_PAD_LD1__CSI_D1 0x0cc 0x2c4 0x48c 0x02 0x000 +-#define MX25_PAD_LD1__GPIO_2_16 0x0cc 0x2c4 0x000 0x05 0x000 +- +-#define MX25_PAD_LD2__LD2 0x0d0 0x2c8 0x000 0x00 0x000 +-#define MX25_PAD_LD2__GPIO_2_17 0x0d0 0x2c8 0x000 0x05 0x000 +- +-#define MX25_PAD_LD3__LD3 0x0d4 0x2cc 0x000 0x00 0x000 +-#define MX25_PAD_LD3__GPIO_2_18 0x0d4 0x2cc 0x000 0x05 0x000 +- +-#define MX25_PAD_LD4__LD4 0x0d8 0x2d0 0x000 0x00 0x000 +-#define MX25_PAD_LD4__GPIO_2_19 0x0d8 0x2d0 0x000 0x05 0x000 +- +-#define MX25_PAD_LD5__LD5 0x0dc 0x2d4 0x000 0x00 0x000 +-#define MX25_PAD_LD5__GPIO_1_19 0x0dc 0x2d4 0x000 0x05 0x000 +- +-#define MX25_PAD_LD6__LD6 0x0e0 0x2d8 0x000 0x00 0x000 +-#define MX25_PAD_LD6__GPIO_1_20 0x0e0 0x2d8 0x000 0x05 0x000 +- +-#define MX25_PAD_LD7__LD7 0x0e4 0x2dc 0x000 0x00 0x000 +-#define MX25_PAD_LD7__GPIO_1_21 0x0e4 0x2dc 0x000 0x05 0x000 +- +-#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x00 0x000 +-#define MX25_PAD_LD8__UART4_RXD 0x0e8 0x2e0 0x570 0x02 0x000 +-#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x05 0x000 +-/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */ +-#define MX25_PAD_LD8__ESDHC2_CMD 0x0e8 0x2e0 0x4e0 0x16 0x000 +- +-#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x00 0x000 +-#define MX25_PAD_LD9__UART4_TXD 0x0ec 0x2e4 0x000 0x02 0x000 +-#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x05 0x001 +-#define MX25_PAD_LD9__ESDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000 +- +-#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x00 0x000 +-#define MX25_PAD_LD10__UART4_RTS 0x0f0 0x2e8 0x56c 0x02 0x000 +-#define MX25_PAD_LD10__FEC_RX_ERR 0x0f0 0x2e8 0x518 0x05 0x001 +- +-#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x00 0x000 +-#define MX25_PAD_LD11__UART4_CTS 0x0f4 0x2ec 0x000 0x02 0x000 +-#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x05 0x001 +-#define MX25_PAD_LD11__ESDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000 +- +-#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x00 0x000 +-#define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000 +-#define MX25_PAD_LD12__KPP_ROW6 0x0f8 0x2f0 0x544 0x04 0x000 +-#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x05 0x001 +- +-#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x00 0x000 +-#define MX25_PAD_LD13__CSPI2_MISO 0x0fc 0x2f4 0x49c 0x02 0x000 +-#define MX25_PAD_LD13__KPP_ROW7 0x0fc 0x2f4 0x548 0x04 0x000 +-#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x05 0x000 +- +-#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x00 0x000 +-#define MX25_PAD_LD14__CSPI2_SCLK 0x100 0x2f8 0x494 0x02 0x000 +-#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x05 0x000 +- +-#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x00 0x000 +-#define MX25_PAD_LD15__CSPI2_RDY 0x104 0x2fc 0x498 0x02 0x000 +-#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x05 0x001 +- +-#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x00 0x000 +-#define MX25_PAD_HSYNC__GPIO_1_22 0x108 0x300 0x000 0x05 0x000 +- +-#define MX25_PAD_VSYNC__VSYNC 0x10c 0x304 0x000 0x00 0x000 +-#define MX25_PAD_VSYNC__GPIO_1_23 0x10c 0x304 0x000 0x05 0x000 +- +-#define MX25_PAD_LSCLK__LSCLK 0x110 0x308 0x000 0x00 0x000 +-#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x05 0x000 +- +-#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x00 0x000 +-#define MX25_PAD_OE_ACD__CSPI2_SS0 0x114 0x30c 0x4a4 0x02 0x000 +-#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x05 0x000 +- +-#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x00 0x000 +-#define MX25_PAD_CONTRAST__GPT4_CAPIN1 0x118 0x310 0x000 0x01 0x000 +-#define MX25_PAD_CONTRAST__CSPI2_SS1 0x118 0x310 0x4a8 0x02 0x000 +-#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x04 0x000 +-#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x05 0x001 +-#define MX25_PAD_CONTRAST__USBH2_PWR 0x118 0x310 0x000 0x06 0x000 +- +-#define MX25_PAD_PWM__PWM 0x11c 0x314 0x000 0x00 0x000 +-#define MX25_PAD_PWM__GPIO_1_26 0x11c 0x314 0x000 0x05 0x000 +-#define MX25_PAD_PWM__USBH2_OC 0x11c 0x314 0x580 0x06 0x001 +- +-#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x00 0x000 +-#define MX25_PAD_CSI_D2__UART5_RXD 0x120 0x318 0x578 0x01 0x001 +-#define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000 +-#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x05 0x000 +-#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x4b8 0x07 0x001 +- +-#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x00 0x000 +-#define MX25_PAD_CSI_D3__UART5_TXD 0x124 0x31c 0x000 0x01 0x000 +-#define MX25_PAD_CSI_D3__SIM1_RST0 0x124 0x31c 0x000 0x04 0x000 +-#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x05 0x000 +-#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x07 0x001 +- +-#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x00 0x000 +-#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x01 0x001 +-#define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000 +-#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x05 0x000 +-#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x4ac 0x07 0x001 +- +-#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x00 0x000 +-#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x01 0x000 +-#define MX25_PAD_CSI_D5__SIM1_TX0 0x12c 0x324 0x000 0x04 0x000 +-#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x05 0x000 +-#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x4b0 0x07 0x001 +- +-#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x00 0x000 +-/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */ +-#define MX25_PAD_CSI_D6__ESDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001 +-#define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000 +-#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x05 0x000 +-#define MX25_PAD_CSI_D6__CSPI3_SS0 0x130 0x328 0x4bc 0x07 0x001 +- +-#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x00 0x000 +-#define MX25_PAD_CSI_D7__ESDHC2_CLK 0x134 0x32C 0x4dc 0x02 0x001 +-#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x05 0x000 +-#define MX25_PAD_CSI_D7__CSPI3_SS1 0x134 0x32c 0x4c0 0x07 0x001 +- +-#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x00 0x000 +-#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x02 0x000 +-#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x05 0x000 +-#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x07 0x000 +- +-#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x00 0x000 +-#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x02 0x000 +-#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x05 0x000 +-#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x07 0x000 +- +-#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x00 0x000 +-#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x01 0x000 +-#define MX25_PAD_CSI_MCLK__ESDHC2_DAT0 0x140 0x338 0x4e4 0x02 0x001 +-#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x05 0x000 +- +-#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x00 0x000 +-#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x01 0x000 +-#define MX25_PAD_CSI_VSYNC__ESDHC2_DAT1 0x144 0x33c 0x4e8 0x02 0x001 +-#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x05 0x000 +- +-#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x00 0x000 +-#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x01 0x000 +-#define MX25_PAD_CSI_HSYNC__ESDHC2_DAT2 0x148 0x340 0x4ec 0x02 0x001 +-#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x05 0x000 +- +-#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x00 0x000 +-#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x01 0x000 +-#define MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3 0x14c 0x344 0x4f0 0x02 0x001 +-#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x05 0x000 +- +-#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x00 0x000 +-#define MX25_PAD_I2C1_CLK__GPIO_1_12 0x150 0x348 0x000 0x05 0x000 +- +-#define MX25_PAD_I2C1_DAT__I2C1_DAT 0x154 0x34c 0x000 0x00 0x000 +-#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x05 0x000 +- +-#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x00 0x000 +-#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x568 0x02 0x000 +-#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x05 0x000 +- +-#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x00 0x000 +-#define MX25_PAD_CSPI1_MISO__UART3_TXD 0x15c 0x354 0x000 0x02 0x000 +-#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x05 0x000 +- +-#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x00 0x000 +-#define MX25_PAD_CSPI1_SS0__PWM2_PWMO 0x160 0x358 0x000 0x02 0x000 +-#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x05 0x000 +- +-#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x00 0x000 +-#define MX25_PAD_CSPI1_SS1__I2C3_DAT 0x164 0x35C 0x528 0x01 0x001 +-#define MX25_PAD_CSPI1_SS1__UART3_RTS 0x164 0x35c 0x000 0x02 0x000 +-#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x05 0x000 +- +-#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x00 0x000 +-#define MX25_PAD_CSPI1_SCLK__UART3_CTS 0x168 0x360 0x000 0x02 0x000 +-#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x05 0x000 +- +-#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x00 0x000 +-#define MX25_PAD_CSPI1_RDY__GPIO_2_22 0x16c 0x364 0x000 0x05 0x000 +- +-#define MX25_PAD_UART1_RXD__UART1_RXD 0x170 0x368 0x000 0x00 0x000 +-#define MX25_PAD_UART1_RXD__UART2_DTR 0x170 0x368 0x000 0x03 0x000 +-#define MX25_PAD_UART1_RXD__GPIO_4_22 0x170 0x368 0x000 0x05 0x000 +- +-#define MX25_PAD_UART1_TXD__UART1_TXD 0x174 0x36c 0x000 0x00 0x000 +-#define MX25_PAD_UART1_TXD__UART2_DSR 0x174 0x36c 0x000 0x03 0x000 +-#define MX25_PAD_UART1_TXD__GPIO_4_23 0x174 0x36c 0x000 0x05 0x000 +- +-#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x00 0x000 +-#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x01 0x001 +-#define MX25_PAD_UART1_RTS__GPT3_CAPIN1 0x178 0x370 0x000 0x02 0x000 +-#define MX25_PAD_UART1_RTS__UART2_DCD 0x178 0x370 0x000 0x03 0x000 +-#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x05 0x000 +- +-#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x00 0x000 +-#define MX25_PAD_UART1_CTS__CSI_D1 0x17c 0x374 0x48c 0x01 0x001 +-#define MX25_PAD_UART1_CTS__UART2_RI 0x17c 0x374 0x000 0x03 0x001 +-#define MX25_PAD_UART1_CTS__GPIO_4_25 0x17c 0x374 0x000 0x05 0x000 +- +-#define MX25_PAD_UART2_RXD__UART2_RXD 0x180 0x378 0x000 0x00 0x000 +-#define MX25_PAD_UART2_RXD__GPIO_4_26 0x180 0x378 0x000 0x05 0x000 +- +-#define MX25_PAD_UART2_TXD__UART2_TXD 0x184 0x37c 0x000 0x00 0x000 +-#define MX25_PAD_UART2_TXD__GPIO_4_27 0x184 0x37c 0x000 0x05 0x000 +- +-#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x00 0x000 +-#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x02 0x002 +-#define MX25_PAD_UART2_RTS__GPT1_CAPIN1 0x188 0x380 0x000 0x03 0x000 +-#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x05 0x000 +-#define MX25_PAD_UART2_RTS__CSPI2_SS3 0x188 0x380 0x000 0x06 0x000 +- +-#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x00 0x000 +-#define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x02 0x002 +-#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x05 0x000 +-#define MX25_PAD_UART2_CTS__CSPI3_SS3 0x18c 0x384 0x4c8 0x06 0x001 +- +-/* +- * Removing the SION bit from MX25_PAD_*__ESDHCn_CMD breaks detecting an SD +- * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM +- * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon +- * bug that configuring the ESDHCn_CMD function doesn't enable the input path +- * for this pin. +- * This might have side effects for other hardware units that are connected to +- * that pin and use the respective function as input. +- */ +-#define MX25_PAD_SD1_CMD__ESDHC1_CMD 0x190 0x388 0x000 0x10 0x000 +-#define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x01 0x001 +-#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x02 0x002 +-#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x05 0x000 +- +-#define MX25_PAD_SD1_CLK__ESDHC1_CLK 0x194 0x38c 0x000 0x00 0x000 +-#define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x01 0x001 +-#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x02 0x002 +-#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x05 0x000 +- +-#define MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x198 0x390 0x000 0x00 0x000 +-#define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x01 0x001 +-#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x05 0x000 +- +-#define MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x19c 0x394 0x000 0x00 0x000 +-#define MX25_PAD_SD1_DATA1__CSPI2_RDY 0x19c 0x394 0x498 0x01 0x001 +-#define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x03 0x000 +-#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x05 0x000 +- +-#define MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x1a0 0x398 0x000 0x00 0x000 +-#define MX25_PAD_SD1_DATA2__CSPI2_SS0 0x1a0 0x398 0x4a4 0x01 0x001 +-#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x02 0x002 +-#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x05 0x000 +- +-#define MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x1a4 0x39c 0x000 0x00 0x000 +-#define MX25_PAD_SD1_DATA3__CSPI2_SS1 0x1a4 0x39c 0x4a8 0x01 0x001 +-#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x02 0x002 +-#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x05 0x000 +- +-#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x00 0x000 +-#define MX25_PAD_KPP_ROW0__UART3_RXD 0x1a8 0x3a0 0x568 0x01 0x001 +-#define MX25_PAD_KPP_ROW0__UART1_DTR 0x1a8 0x3a0 0x000 0x04 0x000 +-#define MX25_PAD_KPP_ROW0__GPIO_2_29 0x1a8 0x3a0 0x000 0x05 0x000 +- +-#define MX25_PAD_KPP_ROW1__KPP_ROW1 0x1ac 0x3a4 0x000 0x00 0x000 +-#define MX25_PAD_KPP_ROW1__UART3_TXD 0x1ac 0x3a4 0x000 0x01 0x000 +-#define MX25_PAD_KPP_ROW1__UART1_DSR 0x1ac 0x3a4 0x000 0x04 0x000 +-#define MX25_PAD_KPP_ROW1__GPIO_2_30 0x1ac 0x3a4 0x000 0x05 0x000 +- +-#define MX25_PAD_KPP_ROW2__KPP_ROW2 0x1b0 0x3a8 0x000 0x00 0x000 +-#define MX25_PAD_KPP_ROW2__UART3_RTS 0x1b0 0x3a8 0x000 0x01 0x000 +-#define MX25_PAD_KPP_ROW2__CSI_D0 0x1b0 0x3a8 0x488 0x03 0x002 +-#define MX25_PAD_KPP_ROW2__UART1_DCD 0x1b0 0x3a8 0x000 0x04 0x000 +-#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x05 0x000 +- +-#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x00 0x000 +-#define MX25_PAD_KPP_ROW3__UART3_CTS 0x1b4 0x3ac 0x000 0x01 0x000 +-#define MX25_PAD_KPP_ROW3__CSI_D1 0x1b4 0x3ac 0x48c 0x03 0x002 +-#define MX25_PAD_KPP_ROW3__UART1_RI 0x1b4 0x3ac 0x000 0x04 0x000 +-#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x05 0x000 +- +-#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x00 0x000 +-#define MX25_PAD_KPP_COL0__UART4_RXD 0x1b8 0x3b0 0x570 0x01 0x001 +-#define MX25_PAD_KPP_COL0__AUD5_TXD 0x1b8 0x3b0 0x000 0x02 0x000 +-#define MX25_PAD_KPP_COL0__GPIO_3_1 0x1b8 0x3b0 0x000 0x05 0x000 +- +-#define MX25_PAD_KPP_COL1__KPP_COL1 0x1bc 0x3b4 0x000 0x00 0x000 +-#define MX25_PAD_KPP_COL1__UART4_TXD 0x1bc 0x3b4 0x000 0x01 0x000 +-#define MX25_PAD_KPP_COL1__AUD5_RXD 0x1bc 0x3b4 0x000 0x02 0x000 +-#define MX25_PAD_KPP_COL1__GPIO_3_2 0x1bc 0x3b4 0x000 0x05 0x000 +- +-#define MX25_PAD_KPP_COL2__KPP_COL2 0x1c0 0x3b8 0x000 0x00 0x000 +-#define MX25_PAD_KPP_COL2__UART4_RTS 0x1c0 0x3b8 0x56c 0x01 0x001 +-#define MX25_PAD_KPP_COL2__AUD5_TXC 0x1c0 0x3b8 0x000 0x02 0x000 +-#define MX25_PAD_KPP_COL2__GPIO_3_3 0x1c0 0x3b8 0x000 0x05 0x000 +- +-#define MX25_PAD_KPP_COL3__KPP_COL3 0x1c4 0x3bc 0x000 0x00 0x000 +-#define MX25_PAD_KPP_COL3__UART4_CTS 0x1c4 0x3bc 0x000 0x01 0x000 +-#define MX25_PAD_KPP_COL3__AUD5_TXFS 0x1c4 0x3bc 0x000 0x02 0x000 +-#define MX25_PAD_KPP_COL3__GPIO_3_4 0x1c4 0x3bc 0x000 0x05 0x000 +- +-#define MX25_PAD_FEC_MDC__FEC_MDC 0x1c8 0x3c0 0x000 0x00 0x000 +-/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */ +-#define MX25_PAD_FEC_MDC__ESDHC2_CMD 0x1c8 0x3c0 0x4e0 0x11 0x002 +-#define MX25_PAD_FEC_MDC__AUD4_TXD 0x1c8 0x3c0 0x464 0x02 0x001 +-#define MX25_PAD_FEC_MDC__GPIO_3_5 0x1c8 0x3c0 0x000 0x05 0x000 +- +-#define MX25_PAD_FEC_MDIO__FEC_MDIO 0x1cc 0x3c4 0x000 0x00 0x000 +-#define MX25_PAD_FEC_MDIO__AUD4_RXD 0x1cc 0x3c4 0x460 0x02 0x001 +-#define MX25_PAD_FEC_MDIO__GPIO_3_6 0x1cc 0x3c4 0x000 0x05 0x000 +- +-#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x1d0 0x3c8 0x000 0x00 0x000 +-#define MX25_PAD_FEC_TDATA0__GPIO_3_7 0x1d0 0x3c8 0x000 0x05 0x000 +- +-#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x1d4 0x3cc 0x000 0x00 0x000 +-#define MX25_PAD_FEC_TDATA1__AUD4_TXFS 0x1d4 0x3cc 0x474 0x02 0x001 +-#define MX25_PAD_FEC_TDATA1__GPIO_3_8 0x1d4 0x3cc 0x000 0x05 0x000 +- +-#define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x00 0x000 +-#define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x05 0x000 +-#define MX25_PAD_FEC_TX_EN__KPP_ROW4 0x1d8 0x3d0 0x53c 0x06 0x000 +- +-#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x00 0x000 +-#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x05 0x000 +-#define MX25_PAD_FEC_RDATA0__KPP_ROW5 0x1dc 0x3d4 0x540 0x06 0x000 +- +-#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x00 0x000 +-/* +- * According to the i.MX25 Reference manual (IMX25RM, Rev. 2, +- * 01/2011) this is CAN1_TX but that's wrong. +- */ +-#define MX25_PAD_FEC_RDATA1__CAN2_TX 0x1e0 0x3d8 0x000 0x04 0x000 +-#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x05 0x000 +- +-#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x00 0x000 +-/* +- * According to the i.MX25 Reference manual (IMX25RM, Rev. 2, +- * 01/2011) this is CAN1_RX but that's wrong. +- */ +-#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x04 0x000 +-#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x05 0x000 +- +-#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1e8 0x3e0 0x000 0x00 0x000 +-#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 0x1e8 0x3e0 0x000 0x05 0x000 +- +-#define MX25_PAD_RTCK__RTCK 0x1ec 0x3e4 0x000 0x00 0x000 +-#define MX25_PAD_RTCK__OWIRE 0x1ec 0x3e4 0x000 0x01 0x000 +-#define MX25_PAD_RTCK__GPIO_3_14 0x1ec 0x3e4 0x000 0x05 0x000 +- +-#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000 +- +-#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x00 0x000 +-#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x05 0x000 +- +-#define MX25_PAD_GPIO_A__GPIO_1_0 0x1f4 0x3f0 0x000 0x00 0x000 +-#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x06 0x000 +-#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x02 0x000 +- +-#define MX25_PAD_GPIO_B__GPIO_1_1 0x1f8 0x3f4 0x000 0x00 0x000 +-#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x02 0x001 +-#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x06 0x001 +- +-#define MX25_PAD_GPIO_C__GPIO_1_2 0x1fc 0x3f8 0x000 0x00 0x000 +-#define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x01 0x000 +-#define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x02 0x001 +-#define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x03 0x001 +-#define MX25_PAD_GPIO_C__GPT2_CAPIN1 0x1fc 0x3f8 0x000 0x04 0x000 +-#define MX25_PAD_GPIO_C__CSPI1_SS2 0x1fc 0x3f8 0x000 0x05 0x000 +-#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x06 0x000 +-#define MX25_PAD_GPIO_C__CSPI2_SS2 0x1fc 0x3f8 0x000 0x07 0x000 +- +-#define MX25_PAD_GPIO_D__GPIO_1_3 0x200 0x3fc 0x000 0x00 0x000 +-#define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x02 0x001 +-#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x06 0x001 +-#define MX25_PAD_GPIO_D__CSPI3_SS2 0x200 0x3fc 0x4c4 0x07 0x001 +- +-#define MX25_PAD_GPIO_E__GPIO_1_4 0x204 0x400 0x000 0x00 0x000 +-#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x01 0x002 +-#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000 +-#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x04 0x000 +-#define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x06 0x002 +- +-#define MX25_PAD_GPIO_F__GPIO_1_5 0x208 0x404 0x000 0x00 0x000 +-#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000 +-#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x04 0x000 +-#define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x06 0x000 +- +-#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x00 0x000 +-#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x05 0x000 +- +-#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK 0x210 0x000 0x000 0x00 0x000 +-#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 0x210 0x000 0x000 0x05 0x000 +- +-#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x00 0x000 +-#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x04 0x000 +-#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x05 0x000 +-#define MX25_PAD_VSTBY_REQ__UART4_RTS 0x214 0x408 0x56c 0x06 0x002 +- +-#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x00 0x000 +-#define MX25_PAD_VSTBY_ACK__CSPI1_SS3 0x218 0x40c 0x490 0x02 0x001 +-#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x05 0x000 +- +-#define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x00 0x000 +-#define MX25_PAD_POWER_FAIL__AUD7_RXD 0x21c 0x410 0x478 0x04 0x001 +-#define MX25_PAD_POWER_FAIL__GPIO_3_19 0x21c 0x410 0x000 0x05 0x000 +-#define MX25_PAD_POWER_FAIL__UART4_CTS 0x21c 0x410 0x000 0x06 0x000 +- +-#define MX25_PAD_CLKO__CLKO 0x220 0x414 0x000 0x00 0x000 +-#define MX25_PAD_CLKO__GPIO_2_21 0x220 0x414 0x000 0x05 0x000 +- +-#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000 +-#define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000 +- +-#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000 +-#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000 +- +-/* +- * Compatibility defines for out-of-tree users. You should update if you make +- * use of one of them. +- */ +-#define MX25_PAD_D15__SDHC1_DAT7 MX25_PAD_D15__ESDHC1_DAT7 +-#define MX25_PAD_D14__SDHC1_DAT6 MX25_PAD_D14__ESDHC1_DAT6 +-#define MX25_PAD_D13__SDHC1_DAT5 MX25_PAD_D13__ESDHC1_DAT5 +-#define MX25_PAD_D12__SDHC1_DAT4 MX25_PAD_D12__ESDHC1_DAT4 +-#define MX25_PAD_LD8__SDHC2_CMD MX25_PAD_LD8__ESDHC2_CMD +-#define MX25_PAD_LD9__SDHC2_CLK MX25_PAD_LD9__ESDHC2_CLK +-#define MX25_PAD_LD11__SDHC2_DAT1 MX25_PAD_LD11__ESDHC2_DAT1 +-#define MX25_PAD_CSI_D6__SDHC2_CMD MX25_PAD_CSI_D6__ESDHC2_CMD +-#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK MX25_PAD_CSI_D7__ESDHC2_CLK +-#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 MX25_PAD_CSI_MCLK__ESDHC2_DAT0 +-#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 MX25_PAD_CSI_VSYNC__ESDHC2_DAT1 +-#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 MX25_PAD_CSI_HSYNC__ESDHC2_DAT2 +-#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3 +-#define MX25_PAD_SD1_CMD__SD1_CMD MX25_PAD_SD1_CMD__ESDHC1_CMD +-#define MX25_PAD_SD1_CLK__SD1_CLK MX25_PAD_SD1_CLK__ESDHC1_CLK +-#define MX25_PAD_SD1_DATA0__SD1_DATA0 MX25_PAD_SD1_DATA0__ESDHC1_DAT0 +-#define MX25_PAD_SD1_DATA1__SD1_DATA1 MX25_PAD_SD1_DATA1__ESDHC1_DAT1 +-#define MX25_PAD_SD1_DATA2__SD1_DATA2 MX25_PAD_SD1_DATA2__ESDHC1_DAT2 +-#define MX25_PAD_SD1_DATA3__SD1_DATA3 MX25_PAD_SD1_DATA3__ESDHC1_DAT3 +- +-#endif /* __DTS_IMX25_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm/imx25.dtsi b/scripts/dtc/include-prefixes/arm/imx25.dtsi +deleted file mode 100644 +index fdcca82c9986..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx25.dtsi ++++ /dev/null +@@ -1,637 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2012 Sascha Hauer, Pengutronix +- +-#include +-#include "imx25-pinfunc.h" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * The decompressor and also some bootloaders rely on a +- * pre-existing /chosen node to be available to insert the +- * command line and merge other ATAGS info. +- */ +- chosen {}; +- +- aliases { +- ethernet0 = &fec; +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- gpio3 = &gpio4; +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- mmc0 = &esdhc1; +- mmc1 = &esdhc2; +- pwm0 = &pwm1; +- pwm1 = &pwm2; +- pwm2 = &pwm3; +- pwm3 = &pwm4; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- serial4 = &uart5; +- spi0 = &spi1; +- spi1 = &spi2; +- spi2 = &spi3; +- usb0 = &usbotg; +- usb1 = &usbhost1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,arm926ej-s"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- asic: asic-interrupt-controller@68000000 { +- compatible = "fsl,imx25-asic", "fsl,avic"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x68000000 0x8000000>; +- }; +- +- clocks { +- osc { +- compatible = "fsl,imx-osc", "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- }; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&asic>; +- ranges; +- +- bus@43f00000 { /* AIPS1 */ +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x43f00000 0x100000>; +- ranges; +- +- aips1: bridge@43f00000 { +- compatible = "fsl,imx25-aips"; +- reg = <0x43f00000 0x4000>; +- }; +- +- i2c1: i2c@43f80000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx25-i2c", "fsl,imx21-i2c"; +- reg = <0x43f80000 0x4000>; +- clocks = <&clks 48>; +- clock-names = ""; +- interrupts = <3>; +- status = "disabled"; +- }; +- +- i2c3: i2c@43f84000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx25-i2c", "fsl,imx21-i2c"; +- reg = <0x43f84000 0x4000>; +- clocks = <&clks 48>; +- clock-names = ""; +- interrupts = <10>; +- status = "disabled"; +- }; +- +- can1: can@43f88000 { +- compatible = "fsl,imx25-flexcan"; +- reg = <0x43f88000 0x4000>; +- interrupts = <43>; +- clocks = <&clks 75>, <&clks 75>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- can2: can@43f8c000 { +- compatible = "fsl,imx25-flexcan"; +- reg = <0x43f8c000 0x4000>; +- interrupts = <44>; +- clocks = <&clks 76>, <&clks 76>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart1: serial@43f90000 { +- compatible = "fsl,imx25-uart", "fsl,imx21-uart"; +- reg = <0x43f90000 0x4000>; +- interrupts = <45>; +- clocks = <&clks 120>, <&clks 57>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart2: serial@43f94000 { +- compatible = "fsl,imx25-uart", "fsl,imx21-uart"; +- reg = <0x43f94000 0x4000>; +- interrupts = <32>; +- clocks = <&clks 121>, <&clks 57>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- i2c2: i2c@43f98000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx25-i2c", "fsl,imx21-i2c"; +- reg = <0x43f98000 0x4000>; +- clocks = <&clks 48>; +- clock-names = ""; +- interrupts = <4>; +- status = "disabled"; +- }; +- +- owire@43f9c000 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x43f9c000 0x4000>; +- clocks = <&clks 51>; +- clock-names = ""; +- interrupts = <2>; +- status = "disabled"; +- }; +- +- spi1: spi@43fa4000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; +- reg = <0x43fa4000 0x4000>; +- clocks = <&clks 78>, <&clks 78>; +- clock-names = "ipg", "per"; +- interrupts = <14>; +- status = "disabled"; +- }; +- +- kpp: kpp@43fa8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx25-kpp", "fsl,imx21-kpp"; +- reg = <0x43fa8000 0x4000>; +- clocks = <&clks 102>; +- clock-names = ""; +- interrupts = <24>; +- status = "disabled"; +- }; +- +- iomuxc: iomuxc@43fac000 { +- compatible = "fsl,imx25-iomuxc"; +- reg = <0x43fac000 0x4000>; +- }; +- +- audmux: audmux@43fb0000 { +- compatible = "fsl,imx25-audmux", "fsl,imx31-audmux"; +- reg = <0x43fb0000 0x4000>; +- status = "disabled"; +- }; +- }; +- +- spba@50000000 { +- compatible = "fsl,spba-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x50000000 0x40000>; +- ranges; +- +- spi3: spi@50004000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; +- reg = <0x50004000 0x4000>; +- interrupts = <0>; +- clocks = <&clks 80>, <&clks 80>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart4: serial@50008000 { +- compatible = "fsl,imx25-uart", "fsl,imx21-uart"; +- reg = <0x50008000 0x4000>; +- interrupts = <5>; +- clocks = <&clks 123>, <&clks 57>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart3: serial@5000c000 { +- compatible = "fsl,imx25-uart", "fsl,imx21-uart"; +- reg = <0x5000c000 0x4000>; +- interrupts = <18>; +- clocks = <&clks 122>, <&clks 57>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- spi2: spi@50010000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; +- reg = <0x50010000 0x4000>; +- clocks = <&clks 79>, <&clks 79>; +- clock-names = "ipg", "per"; +- interrupts = <13>; +- status = "disabled"; +- }; +- +- ssi2: ssi@50014000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; +- reg = <0x50014000 0x4000>; +- interrupts = <11>; +- clocks = <&clks 118>; +- clock-names = "ipg"; +- dmas = <&sdma 24 1 0>, +- <&sdma 25 1 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- esai@50018000 { +- reg = <0x50018000 0x4000>; +- interrupts = <7>; +- }; +- +- uart5: serial@5002c000 { +- compatible = "fsl,imx25-uart", "fsl,imx21-uart"; +- reg = <0x5002c000 0x4000>; +- interrupts = <40>; +- clocks = <&clks 124>, <&clks 57>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- tscadc: tscadc@50030000 { +- compatible = "fsl,imx25-tsadc"; +- reg = <0x50030000 0xc>; +- interrupts = <46>; +- clocks = <&clks 119>; +- clock-names = "ipg"; +- interrupt-controller; +- #interrupt-cells = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- status = "disabled"; +- ranges; +- +- adc: adc@50030800 { +- compatible = "fsl,imx25-gcq"; +- reg = <0x50030800 0x60>; +- interrupt-parent = <&tscadc>; +- interrupts = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- tsc: tcq@50030400 { +- compatible = "fsl,imx25-tcq"; +- reg = <0x50030400 0x60>; +- interrupt-parent = <&tscadc>; +- interrupts = <0>; +- fsl,wires = <4>; +- status = "disabled"; +- }; +- }; +- +- ssi1: ssi@50034000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; +- reg = <0x50034000 0x4000>; +- interrupts = <12>; +- clocks = <&clks 117>; +- clock-names = "ipg"; +- dmas = <&sdma 28 1 0>, +- <&sdma 29 1 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- fec: ethernet@50038000 { +- compatible = "fsl,imx25-fec"; +- reg = <0x50038000 0x4000>; +- interrupts = <57>; +- clocks = <&clks 88>, <&clks 65>; +- clock-names = "ipg", "ahb"; +- status = "disabled"; +- }; +- }; +- +- bus@53f00000 { /* AIPS2 */ +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x53f00000 0x100000>; +- ranges; +- +- aips2: bridge@53f00000 { +- compatible = "fsl,imx25-aips"; +- reg = <0x53f00000 0x4000>; +- }; +- +- clks: ccm@53f80000 { +- compatible = "fsl,imx25-ccm"; +- reg = <0x53f80000 0x4000>; +- interrupts = <31>; +- #clock-cells = <1>; +- }; +- +- gpt4: timer@53f84000 { +- compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; +- reg = <0x53f84000 0x4000>; +- clocks = <&clks 95>, <&clks 47>; +- clock-names = "ipg", "per"; +- interrupts = <1>; +- }; +- +- gpt3: timer@53f88000 { +- compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; +- reg = <0x53f88000 0x4000>; +- clocks = <&clks 94>, <&clks 47>; +- clock-names = "ipg", "per"; +- interrupts = <29>; +- }; +- +- gpt2: timer@53f8c000 { +- compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; +- reg = <0x53f8c000 0x4000>; +- clocks = <&clks 93>, <&clks 47>; +- clock-names = "ipg", "per"; +- interrupts = <53>; +- }; +- +- gpt1: timer@53f90000 { +- compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; +- reg = <0x53f90000 0x4000>; +- clocks = <&clks 92>, <&clks 47>; +- clock-names = "ipg", "per"; +- interrupts = <54>; +- }; +- +- epit1: timer@53f94000 { +- compatible = "fsl,imx25-epit"; +- reg = <0x53f94000 0x4000>; +- clocks = <&clks 83>, <&clks 43>; +- clock-names = "ipg", "per"; +- interrupts = <28>; +- }; +- +- epit2: timer@53f98000 { +- compatible = "fsl,imx25-epit"; +- reg = <0x53f98000 0x4000>; +- clocks = <&clks 84>, <&clks 43>; +- clock-names = "ipg", "per"; +- interrupts = <27>; +- }; +- +- gpio4: gpio@53f9c000 { +- compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; +- reg = <0x53f9c000 0x4000>; +- interrupts = <23>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pwm2: pwm@53fa0000 { +- compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; +- #pwm-cells = <3>; +- reg = <0x53fa0000 0x4000>; +- clocks = <&clks 106>, <&clks 52>; +- clock-names = "ipg", "per"; +- interrupts = <36>; +- }; +- +- gpio3: gpio@53fa4000 { +- compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; +- reg = <0x53fa4000 0x4000>; +- interrupts = <16>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pwm3: pwm@53fa8000 { +- compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; +- #pwm-cells = <3>; +- reg = <0x53fa8000 0x4000>; +- clocks = <&clks 107>, <&clks 52>; +- clock-names = "ipg", "per"; +- interrupts = <41>; +- }; +- +- scc: crypto@53fac000 { +- compatible = "fsl,imx25-scc"; +- reg = <0x53fac000 0x4000>; +- clocks = <&clks 111>; +- clock-names = "ipg"; +- interrupts = <49>, <50>; +- interrupt-names = "scm", "smn"; +- }; +- +- rngb: rngb@53fb0000 { +- compatible = "fsl,imx25-rngb"; +- reg = <0x53fb0000 0x4000>; +- clocks = <&clks 109>; +- interrupts = <22>; +- }; +- +- esdhc1: mmc@53fb4000 { +- compatible = "fsl,imx25-esdhc"; +- reg = <0x53fb4000 0x4000>; +- interrupts = <9>; +- clocks = <&clks 86>, <&clks 63>, <&clks 45>; +- clock-names = "ipg", "ahb", "per"; +- status = "disabled"; +- }; +- +- esdhc2: mmc@53fb8000 { +- compatible = "fsl,imx25-esdhc"; +- reg = <0x53fb8000 0x4000>; +- interrupts = <8>; +- clocks = <&clks 87>, <&clks 64>, <&clks 46>; +- clock-names = "ipg", "ahb", "per"; +- status = "disabled"; +- }; +- +- lcdc: lcdc@53fbc000 { +- compatible = "fsl,imx25-fb", "fsl,imx21-fb"; +- reg = <0x53fbc000 0x4000>; +- interrupts = <39>; +- clocks = <&clks 103>, <&clks 66>, <&clks 49>; +- clock-names = "ipg", "ahb", "per"; +- status = "disabled"; +- }; +- +- slcdc@53fc0000 { +- reg = <0x53fc0000 0x4000>; +- interrupts = <38>; +- status = "disabled"; +- }; +- +- pwm4: pwm@53fc8000 { +- compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; +- #pwm-cells = <3>; +- reg = <0x53fc8000 0x4000>; +- clocks = <&clks 108>, <&clks 52>; +- clock-names = "ipg", "per"; +- interrupts = <42>; +- }; +- +- gpio1: gpio@53fcc000 { +- compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; +- reg = <0x53fcc000 0x4000>; +- interrupts = <52>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@53fd0000 { +- compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; +- reg = <0x53fd0000 0x4000>; +- interrupts = <51>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- sdma: sdma@53fd4000 { +- compatible = "fsl,imx25-sdma"; +- reg = <0x53fd4000 0x4000>; +- clocks = <&clks 112>, <&clks 68>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- interrupts = <34>; +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin"; +- }; +- +- watchdog@53fdc000 { +- compatible = "fsl,imx25-wdt", "fsl,imx21-wdt"; +- reg = <0x53fdc000 0x4000>; +- clocks = <&clks 126>; +- clock-names = ""; +- interrupts = <55>; +- }; +- +- pwm1: pwm@53fe0000 { +- compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; +- #pwm-cells = <3>; +- reg = <0x53fe0000 0x4000>; +- clocks = <&clks 105>, <&clks 52>; +- clock-names = "ipg", "per"; +- interrupts = <26>; +- }; +- +- iim: efuse@53ff0000 { +- compatible = "fsl,imx25-iim", "fsl,imx27-iim"; +- reg = <0x53ff0000 0x4000>; +- interrupts = <19>; +- clocks = <&clks 99>; +- }; +- +- usbotg: usb@53ff4000 { +- compatible = "fsl,imx25-usb", "fsl,imx27-usb"; +- reg = <0x53ff4000 0x0200>; +- interrupts = <37>; +- clocks = <&clks 9>, <&clks 70>, <&clks 8>; +- clock-names = "ipg", "ahb", "per"; +- fsl,usbmisc = <&usbmisc 0>; +- fsl,usbphy = <&usbphy0>; +- phy_type = "utmi"; +- dr_mode = "otg"; +- status = "disabled"; +- }; +- +- usbhost1: usb@53ff4400 { +- compatible = "fsl,imx25-usb", "fsl,imx27-usb"; +- reg = <0x53ff4400 0x0200>; +- interrupts = <35>; +- clocks = <&clks 9>, <&clks 70>, <&clks 8>; +- clock-names = "ipg", "ahb", "per"; +- fsl,usbmisc = <&usbmisc 1>; +- fsl,usbphy = <&usbphy1>; +- maximum-speed = "full-speed"; +- phy_type = "serial"; +- dr_mode = "host"; +- status = "disabled"; +- }; +- +- usbmisc: usbmisc@53ff4600 { +- #index-cells = <1>; +- compatible = "fsl,imx25-usbmisc"; +- reg = <0x53ff4600 0x00f>; +- }; +- +- dryice@53ffc000 { +- compatible = "fsl,imx25-dryice", "fsl,imx25-rtc"; +- reg = <0x53ffc000 0x4000>; +- clocks = <&clks 81>; +- clock-names = "ipg"; +- interrupts = <25 56>; +- }; +- }; +- +- iram: sram@78000000 { +- compatible = "mmio-sram"; +- reg = <0x78000000 0x20000>; +- }; +- +- emi@80000000 { +- compatible = "fsl,emi-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x80000000 0x3b002000>; +- ranges; +- +- nfc: nand@bb000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- +- compatible = "fsl,imx25-nand"; +- reg = <0xbb000000 0x2000>; +- clocks = <&clks 50>; +- clock-names = ""; +- interrupts = <33>; +- status = "disabled"; +- }; +- }; +- }; +- +- usbphy { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- usbphy0: usb-phy@0 { +- reg = <0>; +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- }; +- +- usbphy1: usb-phy@1 { +- reg = <1>; +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx27-apf27.dts b/scripts/dtc/include-prefixes/arm/imx27-apf27.dts +deleted file mode 100644 +index 745d5d409952..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx27-apf27.dts ++++ /dev/null +@@ -1,112 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Philippe Reynes +- * Copyright 2012 Armadeus Systems +- * +- * Based on code which is: Copyright 2012 Sascha Hauer, Pengutronix +- */ +- +-/dts-v1/; +-#include "imx27.dtsi" +- +-/ { +- model = "Armadeus Systems APF27 module"; +- compatible = "armadeus,imx27-apf27", "fsl,imx27"; +- +- memory@a0000000 { +- device_type = "memory"; +- reg = <0xa0000000 0x04000000>; +- }; +-}; +- +-&clk_osc26m { +- clock-frequency = <0>; +-}; +- +-&iomuxc { +- imx27-apf27 { +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX27_PAD_SD3_CMD__FEC_TXD0 0x0 +- MX27_PAD_SD3_CLK__FEC_TXD1 0x0 +- MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 +- MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 +- MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 +- MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 +- MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 +- MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 +- MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 +- MX27_PAD_ATA_DATA7__FEC_MDC 0x0 +- MX27_PAD_ATA_DATA8__FEC_CRS 0x0 +- MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 +- MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 +- MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 +- MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 +- MX27_PAD_ATA_DATA13__FEC_COL 0x0 +- MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 +- MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX27_PAD_UART1_TXD__UART1_TXD 0x0 +- MX27_PAD_UART1_RXD__UART1_RXD 0x0 +- >; +- }; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- status = "okay"; +-}; +- +-&nfc { +- status = "okay"; +- nand-bus-width = <16>; +- nand-ecc-mode = "hw"; +- nand-on-flash-bbt; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0 0x100000>; +- }; +- +- partition@100000 { +- label = "env"; +- reg = <0x100000 0x80000>; +- }; +- +- partition@180000 { +- label = "env2"; +- reg = <0x180000 0x80000>; +- }; +- +- partition@200000 { +- label = "firmware"; +- reg = <0x200000 0x80000>; +- }; +- +- partition@280000 { +- label = "dtb"; +- reg = <0x280000 0x80000>; +- }; +- +- partition@300000 { +- label = "kernel"; +- reg = <0x300000 0x500000>; +- }; +- +- partition@800000 { +- label = "rootfs"; +- reg = <0x800000 0xf800000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx27-apf27dev.dts b/scripts/dtc/include-prefixes/arm/imx27-apf27dev.dts +deleted file mode 100644 +index 6f1e8ce9e76e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx27-apf27dev.dts ++++ /dev/null +@@ -1,256 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Armadeus Systems - +- */ +- +-/* APF27Dev is a docking board for the APF27 SOM */ +-#include "imx27-apf27.dts" +- +-/ { +- model = "Armadeus Systems APF27Dev docking/development board"; +- compatible = "armadeus,imx27-apf27dev", "armadeus,imx27-apf27", "fsl,imx27"; +- +- display: display { +- model = "Chimei-LW700AT9003"; +- bits-per-pixel = <16>; /* non-standard but required */ +- fsl,pcr = <0xfae80083>; /* non-standard but required */ +- display-timings { +- native-mode = <&timing0>; +- timing0: 800x480 { +- clock-frequency = <33000033>; +- hactive = <800>; +- vactive = <480>; +- hback-porch = <96>; +- hfront-porch = <96>; +- vback-porch = <20>; +- vfront-porch = <21>; +- hsync-len = <64>; +- vsync-len = <4>; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- user-key { +- label = "user"; +- gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; +- linux,code = <276>; /* BTN_EXTRA */ +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- user { +- label = "Heartbeat"; +- gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_max5821: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "max5821-reg"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- }; +-}; +- +-&cspi1 { +- cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>; +- status = "okay"; +- +- adc@0 { +- compatible = "maxim,max1027"; +- reg = <0>; +- interrupt-parent = <&gpio5>; +- interrupts = <15 IRQ_TYPE_EDGE_FALLING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_max1027>; +- spi-max-frequency = <10000000>; +- }; +-}; +- +-&cspi2 { +- cs-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>, +- <&gpio4 27 GPIO_ACTIVE_LOW>, +- <&gpio2 17 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_cspi2 &pinctrl_cspi2_cs>; +- status = "okay"; +-}; +- +-&fb { +- display = <&display>; +- fsl,dmacr = <0x00020010>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_imxfb1>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- rtc@68 { +- compatible = "dallas,ds1374"; +- reg = <0x68>; +- }; +- +- max5821@38 { +- compatible = "maxim,max5821"; +- reg = <0x38>; +- vref-supply = <®_max5821>; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&iomuxc { +- imx27-apf27dev { +- pinctrl_cspi1: cspi1grp { +- fsl,pins = < +- MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 +- MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 +- MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 +- >; +- }; +- +- pinctrl_cspi1_cs: cspi1csgrp { +- fsl,pins = ; +- }; +- +- pinctrl_cspi2: cspi2grp { +- fsl,pins = < +- MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 +- MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 +- MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 +- >; +- }; +- +- pinctrl_cspi2_cs: cspi2csgrp { +- fsl,pins = < +- MX27_PAD_CSI_D5__GPIO2_17 0x0 +- MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 +- MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = ; +- }; +- +- pinctrl_gpio_keys: gpiokeysgrp { +- fsl,pins = ; +- }; +- +- pinctrl_imxfb1: imxfbgrp { +- fsl,pins = < +- MX27_PAD_CLS__CLS 0x0 +- MX27_PAD_CONTRAST__CONTRAST 0x0 +- MX27_PAD_LD0__LD0 0x0 +- MX27_PAD_LD1__LD1 0x0 +- MX27_PAD_LD2__LD2 0x0 +- MX27_PAD_LD3__LD3 0x0 +- MX27_PAD_LD4__LD4 0x0 +- MX27_PAD_LD5__LD5 0x0 +- MX27_PAD_LD6__LD6 0x0 +- MX27_PAD_LD7__LD7 0x0 +- MX27_PAD_LD8__LD8 0x0 +- MX27_PAD_LD9__LD9 0x0 +- MX27_PAD_LD10__LD10 0x0 +- MX27_PAD_LD11__LD11 0x0 +- MX27_PAD_LD12__LD12 0x0 +- MX27_PAD_LD13__LD13 0x0 +- MX27_PAD_LD14__LD14 0x0 +- MX27_PAD_LD15__LD15 0x0 +- MX27_PAD_LD16__LD16 0x0 +- MX27_PAD_LD17__LD17 0x0 +- MX27_PAD_LSCLK__LSCLK 0x0 +- MX27_PAD_OE_ACD__OE_ACD 0x0 +- MX27_PAD_PS__PS 0x0 +- MX27_PAD_REV__REV 0x0 +- MX27_PAD_SPL_SPR__SPL_SPR 0x0 +- MX27_PAD_HSYNC__HSYNC 0x0 +- MX27_PAD_VSYNC__VSYNC 0x0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX27_PAD_I2C_DATA__I2C_DATA 0x0 +- MX27_PAD_I2C_CLK__I2C_CLK 0x0 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 +- MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 +- >; +- }; +- +- pinctrl_max1027: max1027 { +- fsl,pins = < +- MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */ +- MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */ +- >; +- }; +- +- pinctrl_pwm: pwmgrp { +- fsl,pins = < +- MX27_PAD_PWMO__PWMO 0x0 +- >; +- }; +- +- pinctrl_sdhc2: sdhc2grp { +- fsl,pins = < +- MX27_PAD_SD2_CLK__SD2_CLK 0x0 +- MX27_PAD_SD2_CMD__SD2_CMD 0x0 +- MX27_PAD_SD2_D0__SD2_D0 0x0 +- MX27_PAD_SD2_D1__SD2_D1 0x0 +- MX27_PAD_SD2_D2__SD2_D2 0x0 +- MX27_PAD_SD2_D3__SD2_D3 0x0 +- >; +- }; +- +- pinctrl_sdhc2_cd: sdhc2cdgrp { +- fsl,pins = ; +- }; +- }; +-}; +- +-&sdhci2 { +- bus-width = <4>; +- cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdhc2 &pinctrl_sdhc2_cd>; +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx27-eukrea-cpuimx27.dtsi b/scripts/dtc/include-prefixes/arm/imx27-eukrea-cpuimx27.dtsi +deleted file mode 100644 +index 74110bbcd9d4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx27-eukrea-cpuimx27.dtsi ++++ /dev/null +@@ -1,284 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2014 Alexander Shiyan +- */ +- +-/dts-v1/; +-#include "imx27.dtsi" +- +-/ { +- model = "Eukrea CPUIMX27"; +- compatible = "eukrea,cpuimx27", "fsl,imx27"; +- +- memory@a0000000 { +- device_type = "memory"; +- reg = <0xa0000000 0x04000000>; +- }; +- +- clk14745600: clk-uart { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <14745600>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pcf8563@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +-}; +- +-&nfc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nfc>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-on-flash-bbt; +- status = "okay"; +-}; +- +-&owire { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_owire>; +- status = "okay"; +-}; +- +-&sdhci2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdhc2>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbh2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh2>; +- dr_mode = "host"; +- phy_type = "ulpi"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbotg { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- dr_mode = "otg"; +- phy_type = "ulpi"; +- disable-over-current; +- status = "okay"; +-}; +- +-&weim { +- status = "okay"; +- +- nor: nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0 0x00000000 0x04000000>; +- bank-width = <2>; +- linux,mtd-name = "physmap-flash.0"; +- fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>; +- }; +- +- uart8250@3,200000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart8250_1>; +- compatible = "ns8250"; +- clocks = <&clk14745600>; +- fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; +- interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>; +- reg = <3 0x200000 0x1000>; +- reg-shift = <1>; +- reg-io-width = <1>; +- no-loopback-test; +- }; +- +- uart8250@3,400000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart8250_2>; +- compatible = "ns8250"; +- clocks = <&clk14745600>; +- fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; +- interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>; +- reg = <3 0x400000 0x1000>; +- reg-shift = <1>; +- reg-io-width = <1>; +- no-loopback-test; +- }; +- +- uart8250@3,800000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart8250_3>; +- compatible = "ns8250"; +- clocks = <&clk14745600>; +- fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; +- interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>; +- reg = <3 0x800000 0x1000>; +- reg-shift = <1>; +- reg-io-width = <1>; +- no-loopback-test; +- }; +- +- uart8250@3,1000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart8250_4>; +- compatible = "ns8250"; +- clocks = <&clk14745600>; +- fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; +- interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>; +- reg = <3 0x1000000 0x1000>; +- reg-shift = <1>; +- reg-io-width = <1>; +- no-loopback-test; +- }; +-}; +- +-&iomuxc { +- imx27-eukrea-cpuimx27 { +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX27_PAD_SD3_CMD__FEC_TXD0 0x0 +- MX27_PAD_SD3_CLK__FEC_TXD1 0x0 +- MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 +- MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 +- MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 +- MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 +- MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 +- MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 +- MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 +- MX27_PAD_ATA_DATA7__FEC_MDC 0x0 +- MX27_PAD_ATA_DATA8__FEC_CRS 0x0 +- MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 +- MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 +- MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 +- MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 +- MX27_PAD_ATA_DATA13__FEC_COL 0x0 +- MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 +- MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX27_PAD_I2C_DATA__I2C_DATA 0x0 +- MX27_PAD_I2C_CLK__I2C_CLK 0x0 +- >; +- }; +- +- pinctrl_nfc: nfcgrp { +- fsl,pins = < +- MX27_PAD_NFRB__NFRB 0x0 +- MX27_PAD_NFCLE__NFCLE 0x0 +- MX27_PAD_NFWP_B__NFWP_B 0x0 +- MX27_PAD_NFCE_B__NFCE_B 0x0 +- MX27_PAD_NFALE__NFALE 0x0 +- MX27_PAD_NFRE_B__NFRE_B 0x0 +- MX27_PAD_NFWE_B__NFWE_B 0x0 +- >; +- }; +- +- pinctrl_owire: owiregrp { +- fsl,pins = < +- MX27_PAD_RTCK__OWIRE 0x0 +- >; +- }; +- +- pinctrl_sdhc2: sdhc2grp { +- fsl,pins = < +- MX27_PAD_SD2_CLK__SD2_CLK 0x0 +- MX27_PAD_SD2_CMD__SD2_CMD 0x0 +- MX27_PAD_SD2_D0__SD2_D0 0x0 +- MX27_PAD_SD2_D1__SD2_D1 0x0 +- MX27_PAD_SD2_D2__SD2_D2 0x0 +- MX27_PAD_SD2_D3__SD2_D3 0x0 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX27_PAD_USBH1_TXDM__UART4_TXD 0x0 +- MX27_PAD_USBH1_RXDP__UART4_RXD 0x0 +- MX27_PAD_USBH1_TXDP__UART4_CTS 0x0 +- MX27_PAD_USBH1_FS__UART4_RTS 0x0 +- >; +- }; +- +- pinctrl_uart8250_1: uart82501grp { +- fsl,pins = < +- MX27_PAD_USB_PWR__GPIO2_23 0x0 +- >; +- }; +- +- pinctrl_uart8250_2: uart82502grp { +- fsl,pins = < +- MX27_PAD_USBH1_SUSP__GPIO2_22 0x0 +- >; +- }; +- +- pinctrl_uart8250_3: uart82503grp { +- fsl,pins = < +- MX27_PAD_USBH1_OE_B__GPIO2_27 0x0 +- >; +- }; +- +- pinctrl_uart8250_4: uart82504grp { +- fsl,pins = < +- MX27_PAD_USBH1_RXDM__GPIO2_30 0x0 +- >; +- }; +- +- pinctrl_usbh2: usbh2grp { +- fsl,pins = < +- MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 +- MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 +- MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 +- MX27_PAD_USBH2_STP__USBH2_STP 0x0 +- MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 +- MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 +- MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 +- MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 +- MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 +- MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 +- MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 +- MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 +- MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 +- MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 +- MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 +- MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 +- MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 +- MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 +- MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 +- MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 +- MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 +- MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 +- MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx27-eukrea-mbimxsd27-baseboard.dts b/scripts/dtc/include-prefixes/arm/imx27-eukrea-mbimxsd27-baseboard.dts +deleted file mode 100644 +index 9c3ec82ec7e5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx27-eukrea-mbimxsd27-baseboard.dts ++++ /dev/null +@@ -1,266 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2014 Alexander Shiyan +- */ +- +-#include "imx27-eukrea-cpuimx27.dtsi" +- +-/ { +- model = "Eukrea MBIMXSD27"; +- compatible = "eukrea,mbimxsd27-baseboard", "eukrea,cpuimx27", "fsl,imx27"; +- +- display0: CMO-QVGA { +- model = "CMO-QVGA"; +- bits-per-pixel = <16>; +- fsl,pcr = <0xfad08b80>; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: 320x240 { +- clock-frequency = <6500000>; +- hactive = <320>; +- vactive = <240>; +- hback-porch = <20>; +- hsync-len = <30>; +- hfront-porch = <38>; +- vback-porch = <4>; +- vsync-len = <3>; +- vfront-porch = <15>; +- }; +- }; +- }; +- +- backlight { +- compatible = "gpio-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_backlight>; +- gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpioleds>; +- +- led1 { +- label = "system::live"; +- gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led2 { +- label = "system::user"; +- gpios = <&gpio6 19 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- regulators { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "simple-bus"; +- +- reg_lcd: regulator@0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcdreg>; +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "LCD"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- }; +-}; +- +-&cspi1 { +- pinctrl-0 = <&pinctrl_cspi1>; +- cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- ads7846@0 { +- compatible = "ti,ads7846"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_touch>; +- reg = <0>; +- interrupts = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; +- spi-cpol; +- spi-max-frequency = <1500000>; +- ti,keep-vref-on; +- }; +-}; +- +-&fb { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_imxfb>; +- display = <&display0>; +- lcd-supply = <®_lcd>; +- fsl,dmacr = <0x00040060>; +- fsl,lscr1 = <0x00120300>; +- fsl,lpccr = <0x00a903ff>; +- status = "okay"; +-}; +- +-&i2c1 { +- codec: codec@1a { +- compatible = "ti,tlv320aic23"; +- reg = <0x1a>; +- }; +-}; +- +-&kpp { +- linux,keymap = < +- MATRIX_KEY(0, 0, KEY_UP) +- MATRIX_KEY(0, 1, KEY_DOWN) +- MATRIX_KEY(1, 0, KEY_RIGHT) +- MATRIX_KEY(1, 1, KEY_LEFT) +- >; +- status = "okay"; +-}; +- +-&sdhci1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdhc1>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&ssi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssi1>; +- codec-handle = <&codec>; +- status = "okay"; +-}; +- +-&uart1 { +- uart-has-rtscts; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- uart-has-rtscts; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- uart-has-rtscts; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&iomuxc { +- imx27-eukrea-cpuimx27-baseboard { +- pinctrl_cspi1: cspi1grp { +- fsl,pins = < +- MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 +- MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 +- MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 +- MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* CS0 */ +- >; +- }; +- +- pinctrl_backlight: backlightgrp { +- fsl,pins = < +- MX27_PAD_PWMO__GPIO5_5 0x0 +- >; +- }; +- +- pinctrl_gpioleds: gpioledsgrp { +- fsl,pins = < +- MX27_PAD_PC_PWRON__GPIO6_16 0x0 +- MX27_PAD_PC_CD2_B__GPIO6_19 0x0 +- >; +- }; +- +- pinctrl_imxfb: imxfbgrp { +- fsl,pins = < +- MX27_PAD_LD0__LD0 0x0 +- MX27_PAD_LD1__LD1 0x0 +- MX27_PAD_LD2__LD2 0x0 +- MX27_PAD_LD3__LD3 0x0 +- MX27_PAD_LD4__LD4 0x0 +- MX27_PAD_LD5__LD5 0x0 +- MX27_PAD_LD6__LD6 0x0 +- MX27_PAD_LD7__LD7 0x0 +- MX27_PAD_LD8__LD8 0x0 +- MX27_PAD_LD9__LD9 0x0 +- MX27_PAD_LD10__LD10 0x0 +- MX27_PAD_LD11__LD11 0x0 +- MX27_PAD_LD12__LD12 0x0 +- MX27_PAD_LD13__LD13 0x0 +- MX27_PAD_LD14__LD14 0x0 +- MX27_PAD_LD15__LD15 0x0 +- MX27_PAD_LD16__LD16 0x0 +- MX27_PAD_LD17__LD17 0x0 +- MX27_PAD_CONTRAST__CONTRAST 0x0 +- MX27_PAD_OE_ACD__OE_ACD 0x0 +- MX27_PAD_HSYNC__HSYNC 0x0 +- MX27_PAD_VSYNC__VSYNC 0x0 +- >; +- }; +- +- pinctrl_lcdreg: lcdreggrp { +- fsl,pins = < +- MX27_PAD_CLS__GPIO1_25 0x0 +- >; +- }; +- +- pinctrl_sdhc1: sdhc1grp { +- fsl,pins = < +- MX27_PAD_SD1_CLK__SD1_CLK 0x0 +- MX27_PAD_SD1_CMD__SD1_CMD 0x0 +- MX27_PAD_SD1_D0__SD1_D0 0x0 +- MX27_PAD_SD1_D1__SD1_D1 0x0 +- MX27_PAD_SD1_D2__SD1_D2 0x0 +- MX27_PAD_SD1_D3__SD1_D3 0x0 +- >; +- }; +- +- pinctrl_ssi1: ssi1grp { +- fsl,pins = < +- MX27_PAD_SSI4_CLK__SSI4_CLK 0x0 +- MX27_PAD_SSI4_FS__SSI4_FS 0x0 +- MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x1 +- MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x1 +- >; +- }; +- +- pinctrl_touch: touchgrp { +- fsl,pins = < +- MX27_PAD_CSPI1_RDY__GPIO4_25 0x0 /* IRQ */ +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX27_PAD_UART1_TXD__UART1_TXD 0x0 +- MX27_PAD_UART1_RXD__UART1_RXD 0x0 +- MX27_PAD_UART1_CTS__UART1_CTS 0x0 +- MX27_PAD_UART1_RTS__UART1_RTS 0x0 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX27_PAD_UART2_TXD__UART2_TXD 0x0 +- MX27_PAD_UART2_RXD__UART2_RXD 0x0 +- MX27_PAD_UART2_CTS__UART2_CTS 0x0 +- MX27_PAD_UART2_RTS__UART2_RTS 0x0 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX27_PAD_UART3_TXD__UART3_TXD 0x0 +- MX27_PAD_UART3_RXD__UART3_RXD 0x0 +- MX27_PAD_UART3_CTS__UART3_CTS 0x0 +- MX27_PAD_UART3_RTS__UART3_RTS 0x0 +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx27-pdk.dts b/scripts/dtc/include-prefixes/arm/imx27-pdk.dts +deleted file mode 100644 +index 35123b7cb6b3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx27-pdk.dts ++++ /dev/null +@@ -1,191 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2012 Sascha Hauer, Pengutronix +- +-/dts-v1/; +-#include "imx27.dtsi" +- +-/ { +- model = "Freescale i.MX27 Product Development Kit"; +- compatible = "fsl,imx27-pdk", "fsl,imx27"; +- +- memory@a0000000 { +- device_type = "memory"; +- reg = <0xa0000000 0x08000000>; +- }; +- +- usbphy { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- usbphy0: usbphy@0 { +- compatible = "usb-nop-xceiv"; +- reg = <0>; +- clocks = <&clks IMX27_CLK_DUMMY>; +- clock-names = "main_clk"; +- #phy-cells = <0>; +- }; +- }; +-}; +- +-&cspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_cspi2>; +- cs-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- +- pmic: mc13783@0 { +- compatible = "fsl,mc13783"; +- reg = <0>; +- spi-cs-high; +- spi-max-frequency = <1000000>; +- interrupt-parent = <&gpio3>; +- interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; +- +- regulators { +- vgen_reg: vgen { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vmmc1_reg: vmmc1 { +- regulator-min-microvolt = <1600000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- gpo1_reg: gpo1 { +- regulator-always-on; +- regulator-boot-on; +- }; +- +- gpo3_reg: gpo3 { +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&fec { +- phy-mode = "mii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- status = "okay"; +-}; +- +-&kpp { +- linux,keymap = < +- MATRIX_KEY(0, 0, KEY_UP) +- MATRIX_KEY(0, 1, KEY_DOWN) +- MATRIX_KEY(1, 0, KEY_RIGHT) +- MATRIX_KEY(1, 1, KEY_LEFT) +- MATRIX_KEY(1, 2, KEY_ENTER) +- MATRIX_KEY(2, 0, KEY_F6) +- MATRIX_KEY(2, 1, KEY_F8) +- MATRIX_KEY(2, 2, KEY_F9) +- MATRIX_KEY(2, 3, KEY_F10) +- >; +- status = "okay"; +-}; +- +-&nfc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nand>; +- nand-ecc-mode = "hw"; +- nand-on-flash-bbt; +- status = "okay"; +-}; +- +-&uart1 { +- uart-has-rtscts; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usbotg { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- dr_mode = "otg"; +- fsl,usbphy = <&usbphy0>; +- phy_type = "ulpi"; +- status = "okay"; +-}; +- +-&iomuxc { +- imx27-pdk { +- pinctrl_cspi2: cspi2grp { +- fsl,pins = < +- MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 +- MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 +- MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 +- MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 /* SPI2 CS0 */ +- MX27_PAD_TOUT__GPIO3_14 0x0 /* PMIC IRQ */ +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX27_PAD_SD3_CMD__FEC_TXD0 0x0 +- MX27_PAD_SD3_CLK__FEC_TXD1 0x0 +- MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 +- MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 +- MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 +- MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 +- MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 +- MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 +- MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 +- MX27_PAD_ATA_DATA7__FEC_MDC 0x0 +- MX27_PAD_ATA_DATA8__FEC_CRS 0x0 +- MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 +- MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 +- MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 +- MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 +- MX27_PAD_ATA_DATA13__FEC_COL 0x0 +- MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 +- MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 +- >; +- }; +- +- pinctrl_nand: nandgrp { +- fsl,pins = < +- MX27_PAD_NFRB__NFRB 0x0 +- MX27_PAD_NFCLE__NFCLE 0x0 +- MX27_PAD_NFWP_B__NFWP_B 0x0 +- MX27_PAD_NFCE_B__NFCE_B 0x0 +- MX27_PAD_NFALE__NFALE 0x0 +- MX27_PAD_NFRE_B__NFRE_B 0x0 +- MX27_PAD_NFWE_B__NFWE_B 0x0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX27_PAD_UART1_TXD__UART1_TXD 0x0 +- MX27_PAD_UART1_RXD__UART1_RXD 0x0 +- MX27_PAD_UART1_CTS__UART1_CTS 0x0 +- MX27_PAD_UART1_RTS__UART1_RTS 0x0 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 +- MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 +- MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 +- MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 +- MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 +- MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 +- MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 +- MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 +- MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 +- MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 +- MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 +- MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx27-phytec-phycard-s-rdk.dts b/scripts/dtc/include-prefixes/arm/imx27-phytec-phycard-s-rdk.dts +deleted file mode 100644 +index 188639738dc3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx27-phytec-phycard-s-rdk.dts ++++ /dev/null +@@ -1,162 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Markus Pargmann, Pengutronix +- */ +- +-#include "imx27-phytec-phycard-s-som.dtsi" +- +-/ { +- model = "Phytec pca100 rapid development kit"; +- compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- display: display { +- model = "Primeview-PD050VL1"; +- bits-per-pixel = <16>; /* non-standard but required */ +- fsl,pcr = <0xf0c88080>; /* non-standard but required */ +- display-timings { +- native-mode = <&timing0>; +- timing0: 640x480 { +- hactive = <640>; +- vactive = <480>; +- hback-porch = <112>; +- hfront-porch = <36>; +- hsync-len = <32>; +- vback-porch = <33>; +- vfront-porch = <33>; +- vsync-len = <2>; +- clock-frequency = <25000000>; +- }; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_3v3: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +-}; +- +-&fb { +- display = <&display>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- +- adc@64 { +- compatible = "maxim,max1037"; +- vcc-supply = <®_3v3>; +- reg = <0x64>; +- }; +-}; +- +-&iomuxc { +- imx27-phycard-s-rdk { +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX27_PAD_I2C_DATA__I2C_DATA 0x0 +- MX27_PAD_I2C_CLK__I2C_CLK 0x0 +- >; +- }; +- +- pinctrl_owire1: owire1grp { +- fsl,pins = < +- MX27_PAD_RTCK__OWIRE 0x0 +- >; +- }; +- +- pinctrl_sdhc2: sdhc2grp { +- fsl,pins = < +- MX27_PAD_SD2_CLK__SD2_CLK 0x0 +- MX27_PAD_SD2_CMD__SD2_CMD 0x0 +- MX27_PAD_SD2_D0__SD2_D0 0x0 +- MX27_PAD_SD2_D1__SD2_D1 0x0 +- MX27_PAD_SD2_D2__SD2_D2 0x0 +- MX27_PAD_SD2_D3__SD2_D3 0x0 +- MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX27_PAD_UART1_TXD__UART1_TXD 0x0 +- MX27_PAD_UART1_RXD__UART1_RXD 0x0 +- MX27_PAD_UART1_CTS__UART1_CTS 0x0 +- MX27_PAD_UART1_RTS__UART1_RTS 0x0 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX27_PAD_UART2_TXD__UART2_TXD 0x0 +- MX27_PAD_UART2_RXD__UART2_RXD 0x0 +- MX27_PAD_UART2_CTS__UART2_CTS 0x0 +- MX27_PAD_UART2_RTS__UART2_RTS 0x0 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX27_PAD_UART3_TXD__UART3_TXD 0x0 +- MX27_PAD_UART3_RXD__UART3_RXD 0x0 +- MX27_PAD_UART3_CTS__UART3_CTS 0x0 +- MX27_PAD_UART3_RTS__UART3_RTS 0x0 +- >; +- }; +- }; +-}; +- +-&owire { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_owire1>; +- status = "okay"; +-}; +- +-&sdhci2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdhc2>; +- cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&uart1 { +- uart-has-rtscts; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- uart-has-rtscts; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- uart-has-rtscts; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx27-phytec-phycard-s-som.dtsi b/scripts/dtc/include-prefixes/arm/imx27-phytec-phycard-s-som.dtsi +deleted file mode 100644 +index 303f920201c5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx27-phytec-phycard-s-som.dtsi ++++ /dev/null +@@ -1,97 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar +- * and Markus Pargmann, Pengutronix +- */ +- +-/dts-v1/; +-#include "imx27.dtsi" +- +-/ { +- model = "Phytec pca100"; +- compatible = "phytec,imx27-pca100", "fsl,imx27"; +- +- memory@a0000000 { +- device_type = "memory"; +- reg = <0xa0000000 0x08000000>; /* 128MB */ +- }; +-}; +- +-&cspi1 { +- cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>, +- <&gpio4 27 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- at24@52 { +- compatible = "atmel,24c32"; +- pagesize = <32>; +- reg = <0x52>; +- }; +-}; +- +-&iomuxc { +- imx27-phycard-s-som { +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX27_PAD_SD3_CMD__FEC_TXD0 0x0 +- MX27_PAD_SD3_CLK__FEC_TXD1 0x0 +- MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 +- MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 +- MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 +- MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 +- MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 +- MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 +- MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 +- MX27_PAD_ATA_DATA7__FEC_MDC 0x0 +- MX27_PAD_ATA_DATA8__FEC_CRS 0x0 +- MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 +- MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 +- MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 +- MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 +- MX27_PAD_ATA_DATA13__FEC_COL 0x0 +- MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 +- MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 +- MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 +- >; +- }; +- +- pinctrl_nfc: nfcgrp { +- fsl,pins = < +- MX27_PAD_NFRB__NFRB 0x0 +- MX27_PAD_NFCLE__NFCLE 0x0 +- MX27_PAD_NFWP_B__NFWP_B 0x0 +- MX27_PAD_NFCE_B__NFCE_B 0x0 +- MX27_PAD_NFALE__NFALE 0x0 +- MX27_PAD_NFRE_B__NFRE_B 0x0 +- MX27_PAD_NFWE_B__NFWE_B 0x0 +- >; +- }; +- }; +-}; +- +-&nfc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nfc>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-on-flash-bbt; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx27-phytec-phycore-rdk.dts b/scripts/dtc/include-prefixes/arm/imx27-phytec-phycore-rdk.dts +deleted file mode 100644 +index 344e77790152..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx27-phytec-phycore-rdk.dts ++++ /dev/null +@@ -1,319 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- */ +- +-#include "imx27-phytec-phycore-som.dtsi" +- +-/ { +- model = "Phytec pcm970"; +- compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- display0: LQ035Q7 { +- model = "Sharp-LQ035Q7"; +- bits-per-pixel = <16>; +- fsl,pcr = <0xf00080c0>; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: 240x320 { +- clock-frequency = <5500000>; +- hactive = <240>; +- vactive = <320>; +- hback-porch = <5>; +- hsync-len = <7>; +- hfront-porch = <16>; +- vback-porch = <7>; +- vsync-len = <1>; +- vfront-porch = <9>; +- pixelclk-active = <1>; +- hsync-active = <1>; +- vsync-active = <1>; +- de-active = <0>; +- }; +- }; +- }; +- +- regulators { +- regulator@2 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_csien>; +- reg = <2>; +- regulator-name = "CSI_EN"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; +- regulator-always-on; +- }; +- }; +- +- usbphy { +- usbphy2: usbphy@2 { +- compatible = "usb-nop-xceiv"; +- reg = <2>; +- vcc-supply = <®_5v0>; +- clocks = <&clks IMX27_CLK_DUMMY>; +- clock-names = "main_clk"; +- #phy-cells = <0>; +- }; +- }; +-}; +- +-&cspi1 { +- pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>; +- cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>, +- <&gpio4 27 GPIO_ACTIVE_LOW>; +-}; +- +-&fb { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_imxfb1>; +- display = <&display0>; +- lcd-supply = <®_5v0>; +- fsl,dmacr = <0x00020010>; +- fsl,lscr1 = <0x00120300>; +- fsl,lpccr = <0x00a903ff>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- camgpio: pca9536@41 { +- compatible = "nxp,pca9536"; +- reg = <0x41>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&iomuxc { +- imx27_phycore_rdk { +- pinctrl_csien: csiengrp { +- fsl,pins = < +- MX27_PAD_USB_OC_B__GPIO2_24 0x0 +- >; +- }; +- +- pinctrl_cspi1cs1: cspi1cs1grp { +- fsl,pins = < +- MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 +- >; +- }; +- +- pinctrl_imxfb1: imxfbgrp { +- fsl,pins = < +- MX27_PAD_LD0__LD0 0x0 +- MX27_PAD_LD1__LD1 0x0 +- MX27_PAD_LD2__LD2 0x0 +- MX27_PAD_LD3__LD3 0x0 +- MX27_PAD_LD4__LD4 0x0 +- MX27_PAD_LD5__LD5 0x0 +- MX27_PAD_LD6__LD6 0x0 +- MX27_PAD_LD7__LD7 0x0 +- MX27_PAD_LD8__LD8 0x0 +- MX27_PAD_LD9__LD9 0x0 +- MX27_PAD_LD10__LD10 0x0 +- MX27_PAD_LD11__LD11 0x0 +- MX27_PAD_LD12__LD12 0x0 +- MX27_PAD_LD13__LD13 0x0 +- MX27_PAD_LD14__LD14 0x0 +- MX27_PAD_LD15__LD15 0x0 +- MX27_PAD_LD16__LD16 0x0 +- MX27_PAD_LD17__LD17 0x0 +- MX27_PAD_CLS__CLS 0x0 +- MX27_PAD_CONTRAST__CONTRAST 0x0 +- MX27_PAD_LSCLK__LSCLK 0x0 +- MX27_PAD_OE_ACD__OE_ACD 0x0 +- MX27_PAD_PS__PS 0x0 +- MX27_PAD_REV__REV 0x0 +- MX27_PAD_SPL_SPR__SPL_SPR 0x0 +- MX27_PAD_HSYNC__HSYNC 0x0 +- MX27_PAD_VSYNC__VSYNC 0x0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- /* Add pullup to DATA line */ +- fsl,pins = < +- MX27_PAD_I2C_DATA__I2C_DATA 0x1 +- MX27_PAD_I2C_CLK__I2C_CLK 0x0 +- >; +- }; +- +- pinctrl_owire1: owire1grp { +- fsl,pins = < +- MX27_PAD_RTCK__OWIRE 0x0 +- >; +- }; +- +- pinctrl_sdhc2: sdhc2grp { +- fsl,pins = < +- MX27_PAD_SD2_CLK__SD2_CLK 0x0 +- MX27_PAD_SD2_CMD__SD2_CMD 0x0 +- MX27_PAD_SD2_D0__SD2_D0 0x0 +- MX27_PAD_SD2_D1__SD2_D1 0x0 +- MX27_PAD_SD2_D2__SD2_D2 0x0 +- MX27_PAD_SD2_D3__SD2_D3 0x0 +- MX27_PAD_SSI3_FS__GPIO3_28 0x0 /* WP */ +- MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX27_PAD_UART1_TXD__UART1_TXD 0x0 +- MX27_PAD_UART1_RXD__UART1_RXD 0x0 +- MX27_PAD_UART1_CTS__UART1_CTS 0x0 +- MX27_PAD_UART1_RTS__UART1_RTS 0x0 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX27_PAD_UART2_TXD__UART2_TXD 0x0 +- MX27_PAD_UART2_RXD__UART2_RXD 0x0 +- MX27_PAD_UART2_CTS__UART2_CTS 0x0 +- MX27_PAD_UART2_RTS__UART2_RTS 0x0 +- >; +- }; +- +- pinctrl_usbh2: usbh2grp { +- fsl,pins = < +- MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 +- MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 +- MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 +- MX27_PAD_USBH2_STP__USBH2_STP 0x0 +- MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 +- MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 +- MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 +- MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 +- MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 +- MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 +- MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 +- MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 +- >; +- }; +- +- pinctrl_weim: weimgrp { +- fsl,pins = < +- MX27_PAD_CS4_B__CS4_B 0x0 /* CS4 */ +- MX27_PAD_SD1_D1__GPIO5_19 0x0 /* CAN IRQ */ +- >; +- }; +- }; +-}; +- +-&owire { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_owire1>; +- status = "okay"; +-}; +- +-&pmicleds { +- ledr1: led@3 { +- reg = <3>; +- label = "system:red1:user"; +- }; +- +- ledg1: led@4 { +- reg = <4>; +- label = "system:green1:user"; +- }; +- +- ledb1: led@5 { +- reg = <5>; +- label = "system:blue1:user"; +- }; +- +- ledr2: led@6 { +- reg = <6>; +- label = "system:red2:user"; +- }; +- +- ledg2: led@7 { +- reg = <7>; +- label = "system:green2:user"; +- }; +- +- ledb2: led@8 { +- reg = <8>; +- label = "system:blue2:user"; +- }; +- +- ledr3: led@9 { +- reg = <9>; +- label = "system:red3:nand"; +- linux,default-trigger = "nand-disk"; +- }; +- +- ledg3: led@10 { +- reg = <10>; +- label = "system:green3:live"; +- linux,default-trigger = "heartbeat"; +- }; +- +- ledb3: led@11 { +- reg = <11>; +- label = "system:blue3:cpu"; +- linux,default-trigger = "cpu0"; +- }; +-}; +- +-&sdhci2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdhc2>; +- bus-width = <4>; +- cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; +- wp-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; +- vmmc-supply = <&vmmc1_reg>; +- status = "okay"; +-}; +- +-&uart1 { +- uart-has-rtscts; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- uart-has-rtscts; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usbh2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh2>; +- dr_mode = "host"; +- phy_type = "ulpi"; +- vbus-supply = <®_5v0>; +- fsl,usbphy = <&usbphy2>; +- disable-over-current; +- status = "okay"; +-}; +- +-&weim { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_weim>; +- +- can@4,0 { +- compatible = "nxp,sja1000"; +- reg = <4 0x00000000 0x00000100>; +- interrupt-parent = <&gpio5>; +- interrupts = <19 IRQ_TYPE_EDGE_FALLING>; +- nxp,external-clock-frequency = <16000000>; +- nxp,tx-output-config = <0x16>; +- nxp,no-comparator-bypass; +- fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx27-phytec-phycore-som.dtsi b/scripts/dtc/include-prefixes/arm/imx27-phytec-phycore-som.dtsi +deleted file mode 100644 +index 3d10273177e9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx27-phytec-phycore-som.dtsi ++++ /dev/null +@@ -1,344 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Sascha Hauer, Pengutronix +- */ +- +-/dts-v1/; +-#include "imx27.dtsi" +- +-/ { +- model = "Phytec pcm038"; +- compatible = "phytec,imx27-pcm038", "fsl,imx27"; +- +- memory@a0000000 { +- device_type = "memory"; +- reg = <0xa0000000 0x08000000>; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_3v3: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_5v0: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "5V0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- }; +- +- usbphy { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- usbphy0: usbphy@0 { +- compatible = "usb-nop-xceiv"; +- reg = <0>; +- vcc-supply = <&sw3_reg>; +- clocks = <&clks IMX27_CLK_DUMMY>; +- clock-names = "main_clk"; +- #phy-cells = <0>; +- }; +- }; +-}; +- +-&audmux { +- status = "okay"; +- +- /* SSI0 <=> PINS_4 (MC13783 Audio) */ +- ssi0 { +- fsl,audmux-port = <0>; +- fsl,port-config = <0xcb205000>; +- }; +- +- pins4 { +- fsl,audmux-port = <2>; +- fsl,port-config = <0x00001000>; +- }; +-}; +- +-&cspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_cspi1>; +- cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- +- pmic: mc13783@0 { +- compatible = "fsl,mc13783"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- reg = <0>; +- spi-cs-high; +- spi-max-frequency = <20000000>; +- interrupt-parent = <&gpio2>; +- interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; +- fsl,mc13xxx-uses-adc; +- fsl,mc13xxx-uses-rtc; +- +- pmicleds: leds { +- #address-cells = <1>; +- #size-cells = <0>; +- led-control = <0x001 0x000 0x000 0x000 0x000 0x000>; +- }; +- +- regulators { +- /* SW1A and SW1B joined operation */ +- sw1_reg: sw1a { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1520000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* SW2A and SW2B joined operation */ +- sw2_reg: sw2a { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- sw3_reg: sw3 { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vaudio_reg: vaudio { +- regulator-always-on; +- regulator-boot-on; +- }; +- +- violo_reg: violo { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- viohi_reg: viohi { +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vgen_reg: vgen { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcam_reg: vcam { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- vrf1_reg: vrf1 { +- regulator-min-microvolt = <2775000>; +- regulator-max-microvolt = <2775000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vrf2_reg: vrf2 { +- regulator-min-microvolt = <2775000>; +- regulator-max-microvolt = <2775000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vmmc1_reg: vmmc1 { +- regulator-min-microvolt = <1600000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- gpo1_reg: gpo1 { }; +- +- pwgt1spi_reg: pwgt1spi { +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&fec { +- phy-mode = "mii"; +- phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; +- phy-supply = <®_3v3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- at24@52 { +- compatible = "atmel,24c32"; +- pagesize = <32>; +- reg = <0x52>; +- }; +- +- pcf8563@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- +- lm75@4a { +- compatible = "national,lm75"; +- reg = <0x4a>; +- }; +-}; +- +-&iomuxc { +- imx27_phycore_som { +- pinctrl_cspi1: cspi1grp { +- fsl,pins = < +- MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 +- MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 +- MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 +- MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX27_PAD_SD3_CMD__FEC_TXD0 0x0 +- MX27_PAD_SD3_CLK__FEC_TXD1 0x0 +- MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 +- MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 +- MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 +- MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 +- MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 +- MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 +- MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 +- MX27_PAD_ATA_DATA7__FEC_MDC 0x0 +- MX27_PAD_ATA_DATA8__FEC_CRS 0x0 +- MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 +- MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 +- MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 +- MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 +- MX27_PAD_ATA_DATA13__FEC_COL 0x0 +- MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 +- MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 +- MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */ +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 +- MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 +- >; +- }; +- +- pinctrl_nfc: nfcgrp { +- fsl,pins = < +- MX27_PAD_NFRB__NFRB 0x0 +- MX27_PAD_NFCLE__NFCLE 0x0 +- MX27_PAD_NFWP_B__NFWP_B 0x0 +- MX27_PAD_NFCE_B__NFCE_B 0x0 +- MX27_PAD_NFALE__NFALE 0x0 +- MX27_PAD_NFRE_B__NFRE_B 0x0 +- MX27_PAD_NFWE_B__NFWE_B 0x0 +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ +- >; +- }; +- +- pinctrl_ssi1: ssi1grp { +- fsl,pins = < +- MX27_PAD_SSI1_FS__SSI1_FS 0x0 +- MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0 +- MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0 +- MX27_PAD_SSI1_CLK__SSI1_CLK 0x0 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 +- MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 +- MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 +- MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 +- MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 +- MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 +- MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 +- MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 +- MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 +- MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 +- MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 +- MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 +- >; +- }; +- }; +-}; +- +-&nfc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nfc>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-on-flash-bbt; +- status = "okay"; +-}; +- +-&ssi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssi1>; +- status = "okay"; +-}; +- +-&usbotg { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- dr_mode = "otg"; +- phy_type = "ulpi"; +- fsl,usbphy = <&usbphy0>; +- vbus-supply = <&sw3_reg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&weim { +- status = "okay"; +- +- nor: nor@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0x00000000 0x02000000>; +- bank-width = <2>; +- linux,mtd-name = "physmap-flash.0"; +- fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- sram: sram@1,0 { +- compatible = "mtd-ram"; +- reg = <1 0x00000000 0x00800000>; +- bank-width = <2>; +- linux,mtd-name = "mtd-ram.0"; +- fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx27-pinfunc.h b/scripts/dtc/include-prefixes/arm/imx27-pinfunc.h +deleted file mode 100644 +index 1514d80a3112..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx27-pinfunc.h ++++ /dev/null +@@ -1,474 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright 2013 Markus Pargmann , Pengutronix +- */ +- +-#ifndef __DTS_IMX27_PINFUNC_H +-#define __DTS_IMX27_PINFUNC_H +- +-/* +- * The pin function ID is a tuple of +- * +- * mux_id consists of +- * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10) +- * +- * function: 0 - Primary function +- * 1 - Alternate function +- * 2 - GPIO +- * direction: 0 - Input +- * 1 - Output +- * gpio_oconf: 0 - A_IN +- * 1 - B_IN +- * 2 - C_IN +- * 3 - Data Register +- * gpio_iconfa/b: 0 - GPIO_IN +- * 1 - Interrupt Status Register +- * 2 - 0 +- * 3 - 1 +- * +- * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable +- * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin +- * number on the specific port (between 0 and 31). +- */ +- +-#define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000 +-#define MX27_PAD_USBH2_CLK__GPIO1_0 0x00 0x032 +-#define MX27_PAD_USBH2_DIR__USBH2_DIR 0x01 0x000 +-#define MX27_PAD_USBH2_DIR__GPIO1_1 0x01 0x032 +-#define MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x02 0x004 +-#define MX27_PAD_USBH2_DATA7__GPIO1_2 0x02 0x032 +-#define MX27_PAD_USBH2_NXT__USBH2_NXT 0x03 0x000 +-#define MX27_PAD_USBH2_NXT__GPIO1_3 0x03 0x032 +-#define MX27_PAD_USBH2_STP__USBH2_STP 0x04 0x004 +-#define MX27_PAD_USBH2_STP__GPIO1_4 0x04 0x032 +-#define MX27_PAD_LSCLK__LSCLK 0x05 0x004 +-#define MX27_PAD_LSCLK__GPIO1_5 0x05 0x032 +-#define MX27_PAD_LD0__LD0 0x06 0x004 +-#define MX27_PAD_LD0__GPIO1_6 0x06 0x032 +-#define MX27_PAD_LD1__LD1 0x07 0x004 +-#define MX27_PAD_LD1__GPIO1_7 0x07 0x032 +-#define MX27_PAD_LD2__LD2 0x08 0x004 +-#define MX27_PAD_LD2__GPIO1_8 0x08 0x032 +-#define MX27_PAD_LD3__LD3 0x09 0x004 +-#define MX27_PAD_LD3__GPIO1_9 0x09 0x032 +-#define MX27_PAD_LD4__LD4 0x0a 0x004 +-#define MX27_PAD_LD4__GPIO1_10 0x0a 0x032 +-#define MX27_PAD_LD5__LD5 0x0b 0x004 +-#define MX27_PAD_LD5__GPIO1_11 0x0b 0x032 +-#define MX27_PAD_LD6__LD6 0x0c 0x004 +-#define MX27_PAD_LD6__GPIO1_12 0x0c 0x032 +-#define MX27_PAD_LD7__LD7 0x0d 0x004 +-#define MX27_PAD_LD7__GPIO1_13 0x0d 0x032 +-#define MX27_PAD_LD8__LD8 0x0e 0x004 +-#define MX27_PAD_LD8__GPIO1_14 0x0e 0x032 +-#define MX27_PAD_LD9__LD9 0x0f 0x004 +-#define MX27_PAD_LD9__GPIO1_15 0x0f 0x032 +-#define MX27_PAD_LD10__LD10 0x10 0x004 +-#define MX27_PAD_LD10__GPIO1_16 0x10 0x032 +-#define MX27_PAD_LD11__LD11 0x11 0x004 +-#define MX27_PAD_LD11__GPIO1_17 0x11 0x032 +-#define MX27_PAD_LD12__LD12 0x12 0x004 +-#define MX27_PAD_LD12__GPIO1_18 0x12 0x032 +-#define MX27_PAD_LD13__LD13 0x13 0x004 +-#define MX27_PAD_LD13__GPIO1_19 0x13 0x032 +-#define MX27_PAD_LD14__LD14 0x14 0x004 +-#define MX27_PAD_LD14__GPIO1_20 0x14 0x032 +-#define MX27_PAD_LD15__LD15 0x15 0x004 +-#define MX27_PAD_LD15__GPIO1_21 0x15 0x032 +-#define MX27_PAD_LD16__LD16 0x16 0x004 +-#define MX27_PAD_LD16__GPIO1_22 0x16 0x032 +-#define MX27_PAD_LD17__LD17 0x17 0x004 +-#define MX27_PAD_LD17__GPIO1_23 0x17 0x032 +-#define MX27_PAD_REV__REV 0x18 0x004 +-#define MX27_PAD_REV__GPIO1_24 0x18 0x032 +-#define MX27_PAD_CLS__CLS 0x19 0x004 +-#define MX27_PAD_CLS__GPIO1_25 0x19 0x032 +-#define MX27_PAD_PS__PS 0x1a 0x004 +-#define MX27_PAD_PS__GPIO1_26 0x1a 0x032 +-#define MX27_PAD_SPL_SPR__SPL_SPR 0x1b 0x004 +-#define MX27_PAD_SPL_SPR__GPIO1_27 0x1b 0x032 +-#define MX27_PAD_HSYNC__HSYNC 0x1c 0x004 +-#define MX27_PAD_HSYNC__GPIO1_28 0x1c 0x032 +-#define MX27_PAD_VSYNC__VSYNC 0x1d 0x004 +-#define MX27_PAD_VSYNC__GPIO1_29 0x1d 0x032 +-#define MX27_PAD_CONTRAST__CONTRAST 0x1e 0x004 +-#define MX27_PAD_CONTRAST__GPIO1_30 0x1e 0x032 +-#define MX27_PAD_OE_ACD__OE_ACD 0x1f 0x004 +-#define MX27_PAD_OE_ACD__GPIO1_31 0x1f 0x032 +-#define MX27_PAD_SD2_D0__SD2_D0 0x24 0x004 +-#define MX27_PAD_SD2_D0__MSHC_DATA0 0x24 0x005 +-#define MX27_PAD_SD2_D0__GPIO2_4 0x24 0x032 +-#define MX27_PAD_SD2_D1__SD2_D1 0x25 0x004 +-#define MX27_PAD_SD2_D1__MSHC_DATA1 0x25 0x005 +-#define MX27_PAD_SD2_D1__GPIO2_5 0x25 0x032 +-#define MX27_PAD_SD2_D2__SD2_D2 0x26 0x004 +-#define MX27_PAD_SD2_D2__MSHC_DATA2 0x26 0x005 +-#define MX27_PAD_SD2_D2__GPIO2_6 0x26 0x032 +-#define MX27_PAD_SD2_D3__SD2_D3 0x27 0x004 +-#define MX27_PAD_SD2_D3__MSHC_DATA3 0x27 0x005 +-#define MX27_PAD_SD2_D3__GPIO2_7 0x27 0x032 +-#define MX27_PAD_SD2_CMD__SD2_CMD 0x28 0x004 +-#define MX27_PAD_SD2_CMD__MSHC_BS 0x28 0x005 +-#define MX27_PAD_SD2_CMD__GPIO2_8 0x28 0x032 +-#define MX27_PAD_SD2_CLK__SD2_CLK 0x29 0x004 +-#define MX27_PAD_SD2_CLK__MSHC_SCLK 0x29 0x005 +-#define MX27_PAD_SD2_CLK__GPIO2_9 0x29 0x032 +-#define MX27_PAD_CSI_D0__CSI_D0 0x2a 0x000 +-#define MX27_PAD_CSI_D0__UART6_TXD 0x2a 0x005 +-#define MX27_PAD_CSI_D0__GPIO2_10 0x2a 0x032 +-#define MX27_PAD_CSI_D1__CSI_D1 0x2b 0x000 +-#define MX27_PAD_CSI_D1__UART6_RXD 0x2b 0x001 +-#define MX27_PAD_CSI_D1__GPIO2_11 0x2b 0x032 +-#define MX27_PAD_CSI_D2__CSI_D2 0x2c 0x000 +-#define MX27_PAD_CSI_D2__UART6_CTS 0x2c 0x005 +-#define MX27_PAD_CSI_D2__GPIO2_12 0x2c 0x032 +-#define MX27_PAD_CSI_D3__CSI_D3 0x2d 0x000 +-#define MX27_PAD_CSI_D3__UART6_RTS 0x2d 0x001 +-#define MX27_PAD_CSI_D3__GPIO2_13 0x2d 0x032 +-#define MX27_PAD_CSI_D4__CSI_D4 0x2e 0x000 +-#define MX27_PAD_CSI_D4__GPIO2_14 0x2e 0x032 +-#define MX27_PAD_CSI_MCLK__CSI_MCLK 0x2f 0x004 +-#define MX27_PAD_CSI_MCLK__GPIO2_15 0x2f 0x032 +-#define MX27_PAD_CSI_PIXCLK__CSI_PIXCLK 0x30 0x000 +-#define MX27_PAD_CSI_PIXCLK__GPIO2_16 0x30 0x032 +-#define MX27_PAD_CSI_D5__CSI_D5 0x31 0x000 +-#define MX27_PAD_CSI_D5__GPIO2_17 0x31 0x032 +-#define MX27_PAD_CSI_D6__CSI_D6 0x32 0x000 +-#define MX27_PAD_CSI_D6__UART5_TXD 0x32 0x005 +-#define MX27_PAD_CSI_D6__GPIO2_18 0x32 0x032 +-#define MX27_PAD_CSI_D7__CSI_D7 0x33 0x000 +-#define MX27_PAD_CSI_D7__UART5_RXD 0x33 0x001 +-#define MX27_PAD_CSI_D7__GPIO2_19 0x33 0x032 +-#define MX27_PAD_CSI_VSYNC__CSI_VSYNC 0x34 0x000 +-#define MX27_PAD_CSI_VSYNC__UART5_CTS 0x34 0x005 +-#define MX27_PAD_CSI_VSYNC__GPIO2_20 0x34 0x032 +-#define MX27_PAD_CSI_HSYNC__CSI_HSYNC 0x35 0x000 +-#define MX27_PAD_CSI_HSYNC__UART5_RTS 0x35 0x001 +-#define MX27_PAD_CSI_HSYNC__GPIO2_21 0x35 0x032 +-#define MX27_PAD_USBH1_SUSP__USBH1_SUSP 0x36 0x004 +-#define MX27_PAD_USBH1_SUSP__GPIO2_22 0x36 0x032 +-#define MX27_PAD_USB_PWR__USB_PWR 0x37 0x004 +-#define MX27_PAD_USB_PWR__GPIO2_23 0x37 0x032 +-#define MX27_PAD_USB_OC_B__USB_OC_B 0x38 0x000 +-#define MX27_PAD_USB_OC_B__GPIO2_24 0x38 0x032 +-#define MX27_PAD_USBH1_RCV__USBH1_RCV 0x39 0x004 +-#define MX27_PAD_USBH1_RCV__GPIO2_25 0x39 0x032 +-#define MX27_PAD_USBH1_FS__USBH1_FS 0x3a 0x004 +-#define MX27_PAD_USBH1_FS__UART4_RTS 0x3a 0x001 +-#define MX27_PAD_USBH1_FS__GPIO2_26 0x3a 0x032 +-#define MX27_PAD_USBH1_OE_B__USBH1_OE_B 0x3b 0x004 +-#define MX27_PAD_USBH1_OE_B__GPIO2_27 0x3b 0x032 +-#define MX27_PAD_USBH1_TXDM__USBH1_TXDM 0x3c 0x004 +-#define MX27_PAD_USBH1_TXDM__UART4_TXD 0x3c 0x005 +-#define MX27_PAD_USBH1_TXDM__GPIO2_28 0x3c 0x032 +-#define MX27_PAD_USBH1_TXDP__USBH1_TXDP 0x3d 0x004 +-#define MX27_PAD_USBH1_TXDP__UART4_CTS 0x3d 0x005 +-#define MX27_PAD_USBH1_TXDP__GPIO2_29 0x3d 0x032 +-#define MX27_PAD_USBH1_RXDM__USBH1_RXDM 0x3e 0x004 +-#define MX27_PAD_USBH1_RXDM__GPIO2_30 0x3e 0x032 +-#define MX27_PAD_USBH1_RXDP__USBH1_RXDP 0x3f 0x004 +-#define MX27_PAD_USBH1_RXDP__UART4_RXD 0x3f 0x001 +-#define MX27_PAD_USBH1_RXDP__GPIO2_31 0x3f 0x032 +-#define MX27_PAD_I2C2_SDA__I2C2_SDA 0x45 0x004 +-#define MX27_PAD_I2C2_SDA__GPIO3_5 0x45 0x032 +-#define MX27_PAD_I2C2_SCL__I2C2_SCL 0x46 0x004 +-#define MX27_PAD_I2C2_SCL__GPIO3_6 0x46 0x032 +-#define MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x47 0x004 +-#define MX27_PAD_USBOTG_DATA5__GPIO3_7 0x47 0x032 +-#define MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x48 0x004 +-#define MX27_PAD_USBOTG_DATA6__GPIO3_8 0x48 0x032 +-#define MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x49 0x004 +-#define MX27_PAD_USBOTG_DATA0__GPIO3_9 0x49 0x032 +-#define MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x4a 0x004 +-#define MX27_PAD_USBOTG_DATA2__GPIO3_10 0x4a 0x032 +-#define MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x4b 0x004 +-#define MX27_PAD_USBOTG_DATA1__GPIO3_11 0x4b 0x032 +-#define MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x4c 0x004 +-#define MX27_PAD_USBOTG_DATA4__GPIO3_12 0x4c 0x032 +-#define MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x4d 0x004 +-#define MX27_PAD_USBOTG_DATA3__GPIO3_13 0x4d 0x032 +-#define MX27_PAD_TOUT__TOUT 0x4e 0x004 +-#define MX27_PAD_TOUT__GPIO3_14 0x4e 0x032 +-#define MX27_PAD_TIN__TIN 0x4f 0x000 +-#define MX27_PAD_TIN__GPIO3_15 0x4f 0x032 +-#define MX27_PAD_SSI4_FS__SSI4_FS 0x50 0x004 +-#define MX27_PAD_SSI4_FS__GPIO3_16 0x50 0x032 +-#define MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x51 0x004 +-#define MX27_PAD_SSI4_RXDAT__GPIO3_17 0x51 0x032 +-#define MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x52 0x004 +-#define MX27_PAD_SSI4_TXDAT__GPIO3_18 0x52 0x032 +-#define MX27_PAD_SSI4_CLK__SSI4_CLK 0x53 0x004 +-#define MX27_PAD_SSI4_CLK__GPIO3_19 0x53 0x032 +-#define MX27_PAD_SSI1_FS__SSI1_FS 0x54 0x004 +-#define MX27_PAD_SSI1_FS__GPIO3_20 0x54 0x032 +-#define MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x55 0x004 +-#define MX27_PAD_SSI1_RXDAT__GPIO3_21 0x55 0x032 +-#define MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x56 0x004 +-#define MX27_PAD_SSI1_TXDAT__GPIO3_22 0x56 0x032 +-#define MX27_PAD_SSI1_CLK__SSI1_CLK 0x57 0x004 +-#define MX27_PAD_SSI1_CLK__GPIO3_23 0x57 0x032 +-#define MX27_PAD_SSI2_FS__SSI2_FS 0x58 0x004 +-#define MX27_PAD_SSI2_FS__GPT5_TOUT 0x58 0x005 +-#define MX27_PAD_SSI2_FS__GPIO3_24 0x58 0x032 +-#define MX27_PAD_SSI2_RXDAT__SSI2_RXDAT 0x59 0x004 +-#define MX27_PAD_SSI2_RXDAT__GPTS_TIN 0x59 0x001 +-#define MX27_PAD_SSI2_RXDAT__GPIO3_25 0x59 0x032 +-#define MX27_PAD_SSI2_TXDAT__SSI2_TXDAT 0x5a 0x004 +-#define MX27_PAD_SSI2_TXDAT__GPT4_TOUT 0x5a 0x005 +-#define MX27_PAD_SSI2_TXDAT__GPIO3_26 0x5a 0x032 +-#define MX27_PAD_SSI2_CLK__SSI2_CLK 0x5b 0x004 +-#define MX27_PAD_SSI2_CLK__GPT4_TIN 0x5b 0x001 +-#define MX27_PAD_SSI2_CLK__GPIO3_27 0x5b 0x032 +-#define MX27_PAD_SSI3_FS__SSI3_FS 0x5c 0x004 +-#define MX27_PAD_SSI3_FS__SLCDC2_D0 0x5c 0x001 +-#define MX27_PAD_SSI3_FS__GPIO3_28 0x5c 0x032 +-#define MX27_PAD_SSI3_RXDAT__SSI3_RXDAT 0x5d 0x004 +-#define MX27_PAD_SSI3_RXDAT__SLCDC2_RS 0x5d 0x001 +-#define MX27_PAD_SSI3_RXDAT__GPIO3_29 0x5d 0x032 +-#define MX27_PAD_SSI3_TXDAT__SSI3_TXDAT 0x5e 0x004 +-#define MX27_PAD_SSI3_TXDAT__SLCDC2_CS 0x5e 0x001 +-#define MX27_PAD_SSI3_TXDAT__GPIO3_30 0x5e 0x032 +-#define MX27_PAD_SSI3_CLK__SSI3_CLK 0x5f 0x004 +-#define MX27_PAD_SSI3_CLK__SLCDC2_CLK 0x5f 0x001 +-#define MX27_PAD_SSI3_CLK__GPIO3_31 0x5f 0x032 +-#define MX27_PAD_SD3_CMD__SD3_CMD 0x60 0x004 +-#define MX27_PAD_SD3_CMD__FEC_TXD0 0x60 0x006 +-#define MX27_PAD_SD3_CMD__GPIO4_0 0x60 0x032 +-#define MX27_PAD_SD3_CLK__SD3_CLK 0x61 0x004 +-#define MX27_PAD_SD3_CLK__ETMTRACEPKT15 0x61 0x005 +-#define MX27_PAD_SD3_CLK__FEC_TXD1 0x61 0x006 +-#define MX27_PAD_SD3_CLK__GPIO4_1 0x61 0x032 +-#define MX27_PAD_ATA_DATA0__ATA_DATA0 0x62 0x004 +-#define MX27_PAD_ATA_DATA0__SD3_D0 0x62 0x005 +-#define MX27_PAD_ATA_DATA0__FEC_TXD2 0x62 0x006 +-#define MX27_PAD_ATA_DATA0__GPIO4_2 0x62 0x032 +-#define MX27_PAD_ATA_DATA1__ATA_DATA1 0x63 0x004 +-#define MX27_PAD_ATA_DATA1__SD3_D1 0x63 0x005 +-#define MX27_PAD_ATA_DATA1__FEC_TXD3 0x63 0x006 +-#define MX27_PAD_ATA_DATA1__GPIO4_3 0x63 0x032 +-#define MX27_PAD_ATA_DATA2__ATA_DATA2 0x64 0x004 +-#define MX27_PAD_ATA_DATA2__SD3_D2 0x64 0x005 +-#define MX27_PAD_ATA_DATA2__FEC_RX_ER 0x64 0x002 +-#define MX27_PAD_ATA_DATA2__GPIO4_4 0x64 0x032 +-#define MX27_PAD_ATA_DATA3__ATA_DATA3 0x65 0x004 +-#define MX27_PAD_ATA_DATA3__SD3_D3 0x65 0x005 +-#define MX27_PAD_ATA_DATA3__FEC_RXD1 0x65 0x002 +-#define MX27_PAD_ATA_DATA3__GPIO4_5 0x65 0x032 +-#define MX27_PAD_ATA_DATA4__ATA_DATA4 0x66 0x004 +-#define MX27_PAD_ATA_DATA4__ETMTRACEPKT14 0x66 0x005 +-#define MX27_PAD_ATA_DATA4__FEC_RXD2 0x66 0x002 +-#define MX27_PAD_ATA_DATA4__GPIO4_6 0x66 0x032 +-#define MX27_PAD_ATA_DATA5__ATA_DATA5 0x67 0x004 +-#define MX27_PAD_ATA_DATA5__ETMTRACEPKT13 0x67 0x005 +-#define MX27_PAD_ATA_DATA5__FEC_RXD3 0x67 0x002 +-#define MX27_PAD_ATA_DATA5__GPIO4_7 0x67 0x032 +-#define MX27_PAD_ATA_DATA6__ATA_DATA6 0x68 0x004 +-#define MX27_PAD_ATA_DATA6__FEC_MDIO 0x68 0x005 +-#define MX27_PAD_ATA_DATA6__GPIO4_8 0x68 0x032 +-#define MX27_PAD_ATA_DATA7__ATA_DATA7 0x69 0x004 +-#define MX27_PAD_ATA_DATA7__ETMTRACEPKT12 0x69 0x005 +-#define MX27_PAD_ATA_DATA7__FEC_MDC 0x69 0x006 +-#define MX27_PAD_ATA_DATA7__GPIO4_9 0x69 0x032 +-#define MX27_PAD_ATA_DATA8__ATA_DATA8 0x6a 0x004 +-#define MX27_PAD_ATA_DATA8__ETMTRACEPKT11 0x6a 0x005 +-#define MX27_PAD_ATA_DATA8__FEC_CRS 0x6a 0x002 +-#define MX27_PAD_ATA_DATA8__GPIO4_10 0x6a 0x032 +-#define MX27_PAD_ATA_DATA9__ATA_DATA9 0x6b 0x004 +-#define MX27_PAD_ATA_DATA9__ETMTRACEPKT10 0x6b 0x005 +-#define MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x6b 0x002 +-#define MX27_PAD_ATA_DATA9__GPIO4_11 0x6b 0x032 +-#define MX27_PAD_ATA_DATA10__ATA_DATA10 0x6c 0x004 +-#define MX27_PAD_ATA_DATA10__ETMTRACEPKT9 0x6c 0x005 +-#define MX27_PAD_ATA_DATA10__FEC_RXD0 0x6c 0x002 +-#define MX27_PAD_ATA_DATA10__GPIO4_12 0x6c 0x032 +-#define MX27_PAD_ATA_DATA11__ATA_DATA11 0x6d 0x004 +-#define MX27_PAD_ATA_DATA11__ETMTRACEPKT8 0x6d 0x005 +-#define MX27_PAD_ATA_DATA11__FEC_RX_DV 0x6d 0x002 +-#define MX27_PAD_ATA_DATA11__GPIO4_13 0x6d 0x032 +-#define MX27_PAD_ATA_DATA12__ATA_DATA12 0x6e 0x004 +-#define MX27_PAD_ATA_DATA12__ETMTRACEPKT7 0x6e 0x005 +-#define MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x6e 0x002 +-#define MX27_PAD_ATA_DATA12__GPIO4_14 0x6e 0x032 +-#define MX27_PAD_ATA_DATA13__ATA_DATA13 0x6f 0x004 +-#define MX27_PAD_ATA_DATA13__ETMTRACEPKT6 0x6f 0x005 +-#define MX27_PAD_ATA_DATA13__FEC_COL 0x6f 0x002 +-#define MX27_PAD_ATA_DATA13__GPIO4_15 0x6f 0x032 +-#define MX27_PAD_ATA_DATA14__ATA_DATA14 0x70 0x004 +-#define MX27_PAD_ATA_DATA14__ETMTRACEPKT5 0x70 0x005 +-#define MX27_PAD_ATA_DATA14__FEC_TX_ER 0x70 0x006 +-#define MX27_PAD_ATA_DATA14__GPIO4_16 0x70 0x032 +-#define MX27_PAD_I2C_DATA__I2C_DATA 0x71 0x004 +-#define MX27_PAD_I2C_DATA__GPIO4_17 0x71 0x032 +-#define MX27_PAD_I2C_CLK__I2C_CLK 0x72 0x004 +-#define MX27_PAD_I2C_CLK__GPIO4_18 0x72 0x032 +-#define MX27_PAD_CSPI2_SS2__CSPI2_SS2 0x73 0x004 +-#define MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x73 0x005 +-#define MX27_PAD_CSPI2_SS2__GPIO4_19 0x73 0x032 +-#define MX27_PAD_CSPI2_SS1__CSPI2_SS1 0x74 0x004 +-#define MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x74 0x005 +-#define MX27_PAD_CSPI2_SS1__GPIO4_20 0x74 0x032 +-#define MX27_PAD_CSPI2_SS0__CSPI2_SS0 0x75 0x004 +-#define MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x75 0x005 +-#define MX27_PAD_CSPI2_SS0__GPIO4_21 0x75 0x032 +-#define MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x76 0x004 +-#define MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x76 0x005 +-#define MX27_PAD_CSPI2_SCLK__GPIO4_22 0x76 0x032 +-#define MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x77 0x004 +-#define MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x77 0x005 +-#define MX27_PAD_CSPI2_MISO__GPIO4_23 0x77 0x032 +-#define MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x78 0x004 +-#define MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x78 0x005 +-#define MX27_PAD_CSPI2_MOSI__GPIO4_24 0x78 0x032 +-#define MX27_PAD_CSPI1_RDY__CSPI1_RDY 0x79 0x000 +-#define MX27_PAD_CSPI1_RDY__GPIO4_25 0x79 0x032 +-#define MX27_PAD_CSPI1_SS2__CSPI1_SS2 0x7a 0x004 +-#define MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x7a 0x005 +-#define MX27_PAD_CSPI1_SS2__GPIO4_26 0x7a 0x032 +-#define MX27_PAD_CSPI1_SS1__CSPI1_SS1 0x7b 0x004 +-#define MX27_PAD_CSPI1_SS1__GPIO4_27 0x7b 0x032 +-#define MX27_PAD_CSPI1_SS0__CSPI1_SS0 0x7c 0x004 +-#define MX27_PAD_CSPI1_SS0__GPIO4_28 0x7c 0x032 +-#define MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x7d 0x004 +-#define MX27_PAD_CSPI1_SCLK__GPIO4_29 0x7d 0x032 +-#define MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x7e 0x004 +-#define MX27_PAD_CSPI1_MISO__GPIO4_30 0x7e 0x032 +-#define MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x7f 0x004 +-#define MX27_PAD_CSPI1_MOSI__GPIO4_31 0x7f 0x032 +-#define MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x80 0x000 +-#define MX27_PAD_USBOTG_NXT__KP_COL6A 0x80 0x005 +-#define MX27_PAD_USBOTG_NXT__GPIO5_0 0x80 0x032 +-#define MX27_PAD_USBOTG_STP__USBOTG_STP 0x81 0x004 +-#define MX27_PAD_USBOTG_STP__KP_ROW6A 0x81 0x005 +-#define MX27_PAD_USBOTG_STP__GPIO5_1 0x81 0x032 +-#define MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x82 0x000 +-#define MX27_PAD_USBOTG_DIR__KP_ROW7A 0x82 0x005 +-#define MX27_PAD_USBOTG_DIR__GPIO5_2 0x82 0x032 +-#define MX27_PAD_UART2_CTS__UART2_CTS 0x83 0x004 +-#define MX27_PAD_UART2_CTS__KP_COL7 0x83 0x005 +-#define MX27_PAD_UART2_CTS__GPIO5_3 0x83 0x032 +-#define MX27_PAD_UART2_RTS__UART2_RTS 0x84 0x000 +-#define MX27_PAD_UART2_RTS__KP_ROW7 0x84 0x005 +-#define MX27_PAD_UART2_RTS__GPIO5_4 0x84 0x032 +-#define MX27_PAD_PWMO__PWMO 0x85 0x004 +-#define MX27_PAD_PWMO__GPIO5_5 0x85 0x032 +-#define MX27_PAD_UART2_TXD__UART2_TXD 0x86 0x004 +-#define MX27_PAD_UART2_TXD__KP_COL6 0x86 0x005 +-#define MX27_PAD_UART2_TXD__GPIO5_6 0x86 0x032 +-#define MX27_PAD_UART2_RXD__UART2_RXD 0x87 0x000 +-#define MX27_PAD_UART2_RXD__KP_ROW6 0x87 0x005 +-#define MX27_PAD_UART2_RXD__GPIO5_7 0x87 0x032 +-#define MX27_PAD_UART3_TXD__UART3_TXD 0x88 0x004 +-#define MX27_PAD_UART3_TXD__GPIO5_8 0x88 0x032 +-#define MX27_PAD_UART3_RXD__UART3_RXD 0x89 0x000 +-#define MX27_PAD_UART3_RXD__GPIO5_9 0x89 0x032 +-#define MX27_PAD_UART3_CTS__UART3_CTS 0x8a 0x004 +-#define MX27_PAD_UART3_CTS__GPIO5_10 0x8a 0x032 +-#define MX27_PAD_UART3_RTS__UART3_RTS 0x8b 0x000 +-#define MX27_PAD_UART3_RTS__GPIO5_11 0x8b 0x032 +-#define MX27_PAD_UART1_TXD__UART1_TXD 0x8c 0x004 +-#define MX27_PAD_UART1_TXD__GPIO5_12 0x8c 0x032 +-#define MX27_PAD_UART1_RXD__UART1_RXD 0x8d 0x000 +-#define MX27_PAD_UART1_RXD__GPIO5_13 0x8d 0x032 +-#define MX27_PAD_UART1_CTS__UART1_CTS 0x8e 0x004 +-#define MX27_PAD_UART1_CTS__GPIO5_14 0x8e 0x032 +-#define MX27_PAD_UART1_RTS__UART1_RTS 0x8f 0x000 +-#define MX27_PAD_UART1_RTS__GPIO5_15 0x8f 0x032 +-#define MX27_PAD_RTCK__RTCK 0x90 0x004 +-#define MX27_PAD_RTCK__OWIRE 0x90 0x005 +-#define MX27_PAD_RTCK__GPIO5_16 0x90 0x032 +-#define MX27_PAD_RESET_OUT_B__RESET_OUT_B 0x91 0x004 +-#define MX27_PAD_RESET_OUT_B__GPIO5_17 0x91 0x032 +-#define MX27_PAD_SD1_D0__SD1_D0 0x92 0x004 +-#define MX27_PAD_SD1_D0__CSPI3_MISO 0x92 0x001 +-#define MX27_PAD_SD1_D0__GPIO5_18 0x92 0x032 +-#define MX27_PAD_SD1_D1__SD1_D1 0x93 0x004 +-#define MX27_PAD_SD1_D1__GPIO5_19 0x93 0x032 +-#define MX27_PAD_SD1_D2__SD1_D2 0x94 0x004 +-#define MX27_PAD_SD1_D2__GPIO5_20 0x94 0x032 +-#define MX27_PAD_SD1_D3__SD1_D3 0x95 0x004 +-#define MX27_PAD_SD1_D3__CSPI3_SS 0x95 0x005 +-#define MX27_PAD_SD1_D3__GPIO5_21 0x95 0x032 +-#define MX27_PAD_SD1_CMD__SD1_CMD 0x96 0x004 +-#define MX27_PAD_SD1_CMD__CSPI3_MOSI 0x96 0x005 +-#define MX27_PAD_SD1_CMD__GPIO5_22 0x96 0x032 +-#define MX27_PAD_SD1_CLK__SD1_CLK 0x97 0x004 +-#define MX27_PAD_SD1_CLK__CSPI3_SCLK 0x97 0x005 +-#define MX27_PAD_SD1_CLK__GPIO5_23 0x97 0x032 +-#define MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x98 0x000 +-#define MX27_PAD_USBOTG_CLK__GPIO5_24 0x98 0x032 +-#define MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x99 0x004 +-#define MX27_PAD_USBOTG_DATA7__GPIO5_25 0x99 0x032 +-#define MX27_PAD_NFRB__NFRB 0xa0 0x000 +-#define MX27_PAD_NFRB__ETMTRACEPKT3 0xa0 0x005 +-#define MX27_PAD_NFRB__GPIO6_0 0xa0 0x032 +-#define MX27_PAD_NFCLE__NFCLE 0xa1 0x004 +-#define MX27_PAD_NFCLE__ETMTRACEPKT0 0xa1 0x005 +-#define MX27_PAD_NFCLE__GPIO6_1 0xa1 0x032 +-#define MX27_PAD_NFWP_B__NFWP_B 0xa2 0x004 +-#define MX27_PAD_NFWP_B__ETMTRACEPKT1 0xa2 0x005 +-#define MX27_PAD_NFWP_B__GPIO6_2 0xa2 0x032 +-#define MX27_PAD_NFCE_B__NFCE_B 0xa3 0x004 +-#define MX27_PAD_NFCE_B__ETMTRACEPKT2 0xa3 0x005 +-#define MX27_PAD_NFCE_B__GPIO6_3 0xa3 0x032 +-#define MX27_PAD_NFALE__NFALE 0xa4 0x004 +-#define MX27_PAD_NFALE__ETMPIPESTAT0 0xa4 0x005 +-#define MX27_PAD_NFALE__GPIO6_4 0xa4 0x032 +-#define MX27_PAD_NFRE_B__NFRE_B 0xa5 0x004 +-#define MX27_PAD_NFRE_B__ETMPIPESTAT1 0xa5 0x005 +-#define MX27_PAD_NFRE_B__GPIO6_5 0xa5 0x032 +-#define MX27_PAD_NFWE_B__NFWE_B 0xa6 0x004 +-#define MX27_PAD_NFWE_B__ETMPIPESTAT2 0xa6 0x005 +-#define MX27_PAD_NFWE_B__GPIO6_6 0xa6 0x032 +-#define MX27_PAD_PC_POE__PC_POE 0xa7 0x004 +-#define MX27_PAD_PC_POE__ATA_BUFFER_EN 0xa7 0x005 +-#define MX27_PAD_PC_POE__GPIO6_7 0xa7 0x032 +-#define MX27_PAD_PC_RW_B__PC_RW_B 0xa8 0x004 +-#define MX27_PAD_PC_RW_B__ATA_IORDY 0xa8 0x001 +-#define MX27_PAD_PC_RW_B__GPIO6_8 0xa8 0x032 +-#define MX27_PAD_IOIS16__IOIS16 0xa9 0x000 +-#define MX27_PAD_IOIS16__ATA_INTRQ 0xa9 0x001 +-#define MX27_PAD_IOIS16__GPIO6_9 0xa9 0x032 +-#define MX27_PAD_PC_RST__PC_RST 0xaa 0x004 +-#define MX27_PAD_PC_RST__ATA_RESET_B 0xaa 0x005 +-#define MX27_PAD_PC_RST__GPIO6_10 0xaa 0x032 +-#define MX27_PAD_PC_BVD2__PC_BVD2 0xab 0x000 +-#define MX27_PAD_PC_BVD2__ATA_DMACK 0xab 0x005 +-#define MX27_PAD_PC_BVD2__GPIO6_11 0xab 0x032 +-#define MX27_PAD_PC_BVD1__PC_BVD1 0xac 0x000 +-#define MX27_PAD_PC_BVD1__ATA_DMARQ 0xac 0x001 +-#define MX27_PAD_PC_BVD1__GPIO6_12 0xac 0x032 +-#define MX27_PAD_PC_VS2__PC_VS2 0xad 0x000 +-#define MX27_PAD_PC_VS2__ATA_DA0 0xad 0x005 +-#define MX27_PAD_PC_VS2__GPIO6_13 0xad 0x032 +-#define MX27_PAD_PC_VS1__PC_VS1 0xae 0x000 +-#define MX27_PAD_PC_VS1__ATA_DA1 0xae 0x005 +-#define MX27_PAD_PC_VS1__GPIO6_14 0xae 0x032 +-#define MX27_PAD_CLKO__CLKO 0xaf 0x004 +-#define MX27_PAD_CLKO__GPIO6_15 0xaf 0x032 +-#define MX27_PAD_PC_PWRON__PC_PWRON 0xb0 0x000 +-#define MX27_PAD_PC_PWRON__ATA_DA2 0xb0 0x005 +-#define MX27_PAD_PC_PWRON__GPIO6_16 0xb0 0x032 +-#define MX27_PAD_PC_READY__PC_READY 0xb1 0x000 +-#define MX27_PAD_PC_READY__ATA_CS0 0xb1 0x005 +-#define MX27_PAD_PC_READY__GPIO6_17 0xb1 0x032 +-#define MX27_PAD_PC_WAIT_B__PC_WAIT_B 0xb2 0x000 +-#define MX27_PAD_PC_WAIT_B__ATA_CS1 0xb2 0x005 +-#define MX27_PAD_PC_WAIT_B__GPIO6_18 0xb2 0x032 +-#define MX27_PAD_PC_CD2_B__PC_CD2_B 0xb3 0x000 +-#define MX27_PAD_PC_CD2_B__ATA_DIOW 0xb3 0x005 +-#define MX27_PAD_PC_CD2_B__GPIO6_19 0xb3 0x032 +-#define MX27_PAD_PC_CD1_B__PC_CD1_B 0xb4 0x000 +-#define MX27_PAD_PC_CD1_B__ATA_DIOR 0xb4 0x005 +-#define MX27_PAD_PC_CD1_B__GPIO6_20 0xb4 0x032 +-#define MX27_PAD_CS4_B__CS4_B 0xb5 0x004 +-#define MX27_PAD_CS4_B__ETMTRACESYNC 0xb5 0x005 +-#define MX27_PAD_CS4_B__GPIO6_21 0xb5 0x032 +-#define MX27_PAD_CS5_B__CS5_B 0xb6 0x004 +-#define MX27_PAD_CS5_B__ETMTRACECLK 0xb6 0x005 +-#define MX27_PAD_CS5_B__GPIO6_22 0xb6 0x032 +-#define MX27_PAD_ATA_DATA15__ATA_DATA15 0xb7 0x004 +-#define MX27_PAD_ATA_DATA15__ETMTRACEPKT4 0xb7 0x005 +-#define MX27_PAD_ATA_DATA15__FEC_TX_EN 0xb7 0x006 +-#define MX27_PAD_ATA_DATA15__GPIO6_23 0xb7 0x032 +- +-#endif /* __DTS_IMX27_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm/imx27.dtsi b/scripts/dtc/include-prefixes/arm/imx27.dtsi +deleted file mode 100644 +index fd525c3b16fa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx27.dtsi ++++ /dev/null +@@ -1,593 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2012 Sascha Hauer, Pengutronix +- +-#include "imx27-pinfunc.h" +- +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * The decompressor and also some bootloaders rely on a +- * pre-existing /chosen node to be available to insert the +- * command line and merge other ATAGS info. +- */ +- chosen {}; +- +- aliases { +- ethernet0 = &fec; +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- gpio3 = &gpio4; +- gpio4 = &gpio5; +- gpio5 = &gpio6; +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- serial4 = &uart5; +- serial5 = &uart6; +- spi0 = &cspi1; +- spi1 = &cspi2; +- spi2 = &cspi3; +- }; +- +- aitc: aitc-interrupt-controller@10040000 { +- compatible = "fsl,imx27-aitc", "fsl,avic"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x10040000 0x1000>; +- }; +- +- clocks { +- clk_osc26m: osc26m { +- compatible = "fsl,imx-osc26m", "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +- }; +- +- cpus { +- #size-cells = <0>; +- #address-cells = <1>; +- +- cpu: cpu@0 { +- device_type = "cpu"; +- reg = <0>; +- compatible = "arm,arm926ej-s"; +- operating-points = < +- /* kHz uV */ +- 266000 1300000 +- 399000 1450000 +- >; +- clock-latency = <62500>; +- clocks = <&clks IMX27_CLK_CPU_DIV>; +- voltage-tolerance = <5>; +- }; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&aitc>; +- ranges; +- +- aipi@10000000 { /* AIPI1 */ +- compatible = "fsl,aipi-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x10000000 0x20000>; +- ranges; +- +- dma: dma@10001000 { +- compatible = "fsl,imx27-dma"; +- reg = <0x10001000 0x1000>; +- interrupts = <32>; +- clocks = <&clks IMX27_CLK_DMA_IPG_GATE>, +- <&clks IMX27_CLK_DMA_AHB_GATE>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <1>; +- #dma-channels = <16>; +- }; +- +- wdog: watchdog@10002000 { +- compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; +- reg = <0x10002000 0x1000>; +- interrupts = <27>; +- clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>; +- }; +- +- gpt1: timer@10003000 { +- compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; +- reg = <0x10003000 0x1000>; +- interrupts = <26>; +- clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>, +- <&clks IMX27_CLK_PER1_GATE>; +- clock-names = "ipg", "per"; +- }; +- +- gpt2: timer@10004000 { +- compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; +- reg = <0x10004000 0x1000>; +- interrupts = <25>; +- clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>, +- <&clks IMX27_CLK_PER1_GATE>; +- clock-names = "ipg", "per"; +- }; +- +- gpt3: timer@10005000 { +- compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; +- reg = <0x10005000 0x1000>; +- interrupts = <24>; +- clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>, +- <&clks IMX27_CLK_PER1_GATE>; +- clock-names = "ipg", "per"; +- }; +- +- pwm: pwm@10006000 { +- #pwm-cells = <3>; +- compatible = "fsl,imx27-pwm"; +- reg = <0x10006000 0x1000>; +- interrupts = <23>; +- clocks = <&clks IMX27_CLK_PWM_IPG_GATE>, +- <&clks IMX27_CLK_PER1_GATE>; +- clock-names = "ipg", "per"; +- }; +- +- rtc: rtc@10007000 { +- compatible = "fsl,imx21-rtc"; +- reg = <0x10007000 0x1000>; +- interrupts = <22>; +- clocks = <&clks IMX27_CLK_CKIL>, +- <&clks IMX27_CLK_RTC_IPG_GATE>; +- clock-names = "ref", "ipg"; +- }; +- +- kpp: kpp@10008000 { +- compatible = "fsl,imx27-kpp", "fsl,imx21-kpp"; +- reg = <0x10008000 0x1000>; +- interrupts = <21>; +- clocks = <&clks IMX27_CLK_KPP_IPG_GATE>; +- status = "disabled"; +- }; +- +- owire: owire@10009000 { +- compatible = "fsl,imx27-owire", "fsl,imx21-owire"; +- reg = <0x10009000 0x1000>; +- clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>; +- status = "disabled"; +- }; +- +- uart1: serial@1000a000 { +- compatible = "fsl,imx27-uart", "fsl,imx21-uart"; +- reg = <0x1000a000 0x1000>; +- interrupts = <20>; +- clocks = <&clks IMX27_CLK_UART1_IPG_GATE>, +- <&clks IMX27_CLK_PER1_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart2: serial@1000b000 { +- compatible = "fsl,imx27-uart", "fsl,imx21-uart"; +- reg = <0x1000b000 0x1000>; +- interrupts = <19>; +- clocks = <&clks IMX27_CLK_UART2_IPG_GATE>, +- <&clks IMX27_CLK_PER1_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart3: serial@1000c000 { +- compatible = "fsl,imx27-uart", "fsl,imx21-uart"; +- reg = <0x1000c000 0x1000>; +- interrupts = <18>; +- clocks = <&clks IMX27_CLK_UART3_IPG_GATE>, +- <&clks IMX27_CLK_PER1_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart4: serial@1000d000 { +- compatible = "fsl,imx27-uart", "fsl,imx21-uart"; +- reg = <0x1000d000 0x1000>; +- interrupts = <17>; +- clocks = <&clks IMX27_CLK_UART4_IPG_GATE>, +- <&clks IMX27_CLK_PER1_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- cspi1: spi@1000e000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx27-cspi"; +- reg = <0x1000e000 0x1000>; +- interrupts = <16>; +- clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>, +- <&clks IMX27_CLK_PER2_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- cspi2: spi@1000f000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx27-cspi"; +- reg = <0x1000f000 0x1000>; +- interrupts = <15>; +- clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>, +- <&clks IMX27_CLK_PER2_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- ssi1: ssi@10010000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; +- reg = <0x10010000 0x1000>; +- interrupts = <14>; +- clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>; +- dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>; +- dma-names = "rx0", "tx0", "rx1", "tx1"; +- fsl,fifo-depth = <8>; +- status = "disabled"; +- }; +- +- ssi2: ssi@10011000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; +- reg = <0x10011000 0x1000>; +- interrupts = <13>; +- clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>; +- dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>; +- dma-names = "rx0", "tx0", "rx1", "tx1"; +- fsl,fifo-depth = <8>; +- status = "disabled"; +- }; +- +- i2c1: i2c@10012000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; +- reg = <0x10012000 0x1000>; +- interrupts = <12>; +- clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>; +- status = "disabled"; +- }; +- +- sdhci1: mmc@10013000 { +- compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; +- reg = <0x10013000 0x1000>; +- interrupts = <11>; +- clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>, +- <&clks IMX27_CLK_PER2_GATE>; +- clock-names = "ipg", "per"; +- dmas = <&dma 7>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- sdhci2: mmc@10014000 { +- compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; +- reg = <0x10014000 0x1000>; +- interrupts = <10>; +- clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>, +- <&clks IMX27_CLK_PER2_GATE>; +- clock-names = "ipg", "per"; +- dmas = <&dma 6>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- iomuxc: iomuxc@10015000 { +- compatible = "fsl,imx27-iomuxc"; +- reg = <0x10015000 0x600>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gpio1: gpio@10015000 { +- compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; +- reg = <0x10015000 0x100>; +- clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; +- interrupts = <8>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@10015100 { +- compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; +- reg = <0x10015100 0x100>; +- clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; +- interrupts = <8>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio@10015200 { +- compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; +- reg = <0x10015200 0x100>; +- clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; +- interrupts = <8>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio4: gpio@10015300 { +- compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; +- reg = <0x10015300 0x100>; +- clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; +- interrupts = <8>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio5: gpio@10015400 { +- compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; +- reg = <0x10015400 0x100>; +- clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; +- interrupts = <8>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio6: gpio@10015500 { +- compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; +- reg = <0x10015500 0x100>; +- clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; +- interrupts = <8>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- audmux: audmux@10016000 { +- compatible = "fsl,imx27-audmux", "fsl,imx21-audmux"; +- reg = <0x10016000 0x1000>; +- clocks = <&clks IMX27_CLK_DUMMY>; +- clock-names = "audmux"; +- status = "disabled"; +- }; +- +- cspi3: spi@10017000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx27-cspi"; +- reg = <0x10017000 0x1000>; +- interrupts = <6>; +- clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>, +- <&clks IMX27_CLK_PER2_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- gpt4: timer@10019000 { +- compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; +- reg = <0x10019000 0x1000>; +- interrupts = <4>; +- clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>, +- <&clks IMX27_CLK_PER1_GATE>; +- clock-names = "ipg", "per"; +- }; +- +- gpt5: timer@1001a000 { +- compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; +- reg = <0x1001a000 0x1000>; +- interrupts = <3>; +- clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>, +- <&clks IMX27_CLK_PER1_GATE>; +- clock-names = "ipg", "per"; +- }; +- +- uart5: serial@1001b000 { +- compatible = "fsl,imx27-uart", "fsl,imx21-uart"; +- reg = <0x1001b000 0x1000>; +- interrupts = <49>; +- clocks = <&clks IMX27_CLK_UART5_IPG_GATE>, +- <&clks IMX27_CLK_PER1_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart6: serial@1001c000 { +- compatible = "fsl,imx27-uart", "fsl,imx21-uart"; +- reg = <0x1001c000 0x1000>; +- interrupts = <48>; +- clocks = <&clks IMX27_CLK_UART6_IPG_GATE>, +- <&clks IMX27_CLK_PER1_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- i2c2: i2c@1001d000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; +- reg = <0x1001d000 0x1000>; +- interrupts = <1>; +- clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>; +- status = "disabled"; +- }; +- +- sdhci3: mmc@1001e000 { +- compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; +- reg = <0x1001e000 0x1000>; +- interrupts = <9>; +- clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>, +- <&clks IMX27_CLK_PER2_GATE>; +- clock-names = "ipg", "per"; +- dmas = <&dma 36>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- gpt6: timer@1001f000 { +- compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; +- reg = <0x1001f000 0x1000>; +- interrupts = <2>; +- clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>, +- <&clks IMX27_CLK_PER1_GATE>; +- clock-names = "ipg", "per"; +- }; +- }; +- +- aipi@10020000 { /* AIPI2 */ +- compatible = "fsl,aipi-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x10020000 0x20000>; +- ranges; +- +- fb: fb@10021000 { +- compatible = "fsl,imx27-fb", "fsl,imx21-fb"; +- interrupts = <61>; +- reg = <0x10021000 0x1000>; +- clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>, +- <&clks IMX27_CLK_LCDC_AHB_GATE>, +- <&clks IMX27_CLK_PER3_GATE>; +- clock-names = "ipg", "ahb", "per"; +- status = "disabled"; +- }; +- +- coda: coda@10023000 { +- compatible = "fsl,imx27-vpu", "cnm,codadx6"; +- reg = <0x10023000 0x0200>; +- interrupts = <53>; +- clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>, +- <&clks IMX27_CLK_VPU_AHB_GATE>; +- clock-names = "per", "ahb"; +- iram = <&iram>; +- }; +- +- usbotg: usb@10024000 { +- compatible = "fsl,imx27-usb"; +- reg = <0x10024000 0x200>; +- interrupts = <56>; +- clocks = <&clks IMX27_CLK_USB_IPG_GATE>, +- <&clks IMX27_CLK_USB_AHB_GATE>, +- <&clks IMX27_CLK_USB_DIV>; +- clock-names = "ipg", "ahb", "per"; +- fsl,usbmisc = <&usbmisc 0>; +- status = "disabled"; +- }; +- +- usbh1: usb@10024200 { +- compatible = "fsl,imx27-usb"; +- reg = <0x10024200 0x200>; +- interrupts = <54>; +- clocks = <&clks IMX27_CLK_USB_IPG_GATE>, +- <&clks IMX27_CLK_USB_AHB_GATE>, +- <&clks IMX27_CLK_USB_DIV>; +- clock-names = "ipg", "ahb", "per"; +- fsl,usbmisc = <&usbmisc 1>; +- dr_mode = "host"; +- status = "disabled"; +- }; +- +- usbh2: usb@10024400 { +- compatible = "fsl,imx27-usb"; +- reg = <0x10024400 0x200>; +- interrupts = <55>; +- clocks = <&clks IMX27_CLK_USB_IPG_GATE>, +- <&clks IMX27_CLK_USB_AHB_GATE>, +- <&clks IMX27_CLK_USB_DIV>; +- clock-names = "ipg", "ahb", "per"; +- fsl,usbmisc = <&usbmisc 2>; +- dr_mode = "host"; +- status = "disabled"; +- }; +- +- usbmisc: usbmisc@10024600 { +- #index-cells = <1>; +- compatible = "fsl,imx27-usbmisc"; +- reg = <0x10024600 0x200>; +- }; +- +- sahara2: crypto@10025000 { +- compatible = "fsl,imx27-sahara"; +- reg = <0x10025000 0x1000>; +- interrupts = <59>; +- clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>, +- <&clks IMX27_CLK_SAHARA_AHB_GATE>; +- clock-names = "ipg", "ahb"; +- }; +- +- clks: ccm@10027000{ +- compatible = "fsl,imx27-ccm"; +- reg = <0x10027000 0x1000>; +- #clock-cells = <1>; +- }; +- +- iim: efuse@10028000 { +- compatible = "fsl,imx27-iim"; +- reg = <0x10028000 0x1000>; +- interrupts = <62>; +- clocks = <&clks IMX27_CLK_IIM_IPG_GATE>; +- }; +- +- fec: ethernet@1002b000 { +- compatible = "fsl,imx27-fec"; +- reg = <0x1002b000 0x1000>; +- interrupts = <50>; +- clocks = <&clks IMX27_CLK_FEC_IPG_GATE>, +- <&clks IMX27_CLK_FEC_AHB_GATE>; +- clock-names = "ipg", "ahb"; +- status = "disabled"; +- }; +- }; +- +- nfc: nand-controller@d8000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,imx27-nand"; +- reg = <0xd8000000 0x1000>; +- interrupts = <29>; +- clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>; +- status = "disabled"; +- }; +- +- weim: weim@d8002000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,imx27-weim"; +- reg = <0xd8002000 0x1000>; +- clocks = <&clks IMX27_CLK_EMI_AHB_GATE>; +- ranges = < +- 0 0 0xc0000000 0x08000000 +- 1 0 0xc8000000 0x08000000 +- 2 0 0xd0000000 0x02000000 +- 3 0 0xd2000000 0x02000000 +- 4 0 0xd4000000 0x02000000 +- 5 0 0xd6000000 0x02000000 +- >; +- status = "disabled"; +- }; +- +- iram: sram@ffff4c00 { +- compatible = "mmio-sram"; +- reg = <0xffff4c00 0xb400>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-apf28.dts b/scripts/dtc/include-prefixes/arm/imx28-apf28.dts +deleted file mode 100644 +index 14a92fe59770..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-apf28.dts ++++ /dev/null +@@ -1,80 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Armadeus Systems - +- */ +- +-/dts-v1/; +-#include "imx28.dtsi" +- +-/ { +- model = "Armadeus Systems APF28 module"; +- compatible = "armadeus,imx28-apf28", "fsl,imx28"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x08000000>; +- }; +- +- apb@80000000 { +- apbh@80000000 { +- nand-controller@8000c000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; +- status = "okay"; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0 0x300000>; +- }; +- +- partition@300000 { +- label = "env"; +- reg = <0x300000 0x80000>; +- }; +- +- partition@380000 { +- label = "env2"; +- reg = <0x380000 0x80000>; +- }; +- +- partition@400000 { +- label = "dtb"; +- reg = <0x400000 0x80000>; +- }; +- +- partition@480000 { +- label = "splash"; +- reg = <0x480000 0x80000>; +- }; +- +- partition@500000 { +- label = "kernel"; +- reg = <0x500000 0x800000>; +- }; +- +- partition@d00000 { +- label = "rootfs"; +- reg = <0xd00000 0xf300000>; +- }; +- }; +- }; +- +- apbx@80040000 { +- duart: serial@80074000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_pins_a>; +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- mac0: ethernet@800f0000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_pins_a>; +- phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-apf28dev.dts b/scripts/dtc/include-prefixes/arm/imx28-apf28dev.dts +deleted file mode 100644 +index 1b253b47006c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-apf28dev.dts ++++ /dev/null +@@ -1,225 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Armadeus Systems - +- */ +- +-/* APF28Dev is a docking board for the APF28 SOM */ +-#include "imx28-apf28.dts" +- +-/ { +- model = "Armadeus Systems APF28Dev docking/development board"; +- compatible = "armadeus,imx28-apf28dev", "armadeus,imx28-apf28", "fsl,imx28"; +- +- apb@80000000 { +- apbh@80000000 { +- ssp0: spi@80010000 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_4bit_pins_a +- &mmc0_cd_cfg &mmc0_sck_cfg>; +- bus-width = <4>; +- status = "okay"; +- }; +- +- ssp2: spi@80014000 { +- compatible = "fsl,imx28-spi"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pins_a>; +- status = "okay"; +- }; +- +- pinctrl@80018000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_apf28dev>; +- +- hog_pins_apf28dev: hog@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D16__GPIO_1_16 +- MX28_PAD_LCD_D17__GPIO_1_17 +- MX28_PAD_LCD_D18__GPIO_1_18 +- MX28_PAD_LCD_D19__GPIO_1_19 +- MX28_PAD_LCD_D20__GPIO_1_20 +- MX28_PAD_LCD_D21__GPIO_1_21 +- MX28_PAD_LCD_D22__GPIO_1_22 +- MX28_PAD_GPMI_CE1N__GPIO_0_17 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_pins_apf28dev: lcdif-apf28dev@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_RD_E__LCD_VSYNC +- MX28_PAD_LCD_WR_RWN__LCD_HSYNC +- MX28_PAD_LCD_RS__LCD_DOTCLK +- MX28_PAD_LCD_CS__LCD_ENABLE +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- usb0_otg_apf28dev: otg-apf28dev@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D23__GPIO_1_23 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- }; +- +- lcdif@80030000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcdif_16bit_pins_a +- &lcdif_pins_apf28dev>; +- display = <&display0>; +- status = "okay"; +- +- display0: display0 { +- bits-per-pixel = <16>; +- bus-width = <16>; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing0 { +- clock-frequency = <33000033>; +- hactive = <800>; +- vactive = <480>; +- hback-porch = <96>; +- hfront-porch = <96>; +- vback-porch = <20>; +- vfront-porch = <21>; +- hsync-len = <64>; +- vsync-len = <4>; +- hsync-active = <1>; +- vsync-active = <1>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- }; +- }; +- }; +- +- can0: can@80032000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&can0_pins_a>; +- xceiver-supply = <®_can0_vcc>; +- status = "okay"; +- }; +- }; +- +- apbx@80040000 { +- lradc@80050000 { +- fsl,lradc-touchscreen-wires = <4>; +- status = "okay"; +- }; +- +- i2c0: i2c@80058000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_a>; +- status = "okay"; +- }; +- +- pwm: pwm@80064000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm3_pins_a &pwm4_pins_a>; +- status = "okay"; +- }; +- +- auart0: serial@8006a000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart0_pins_a>; +- uart-has-rtscts; +- status = "okay"; +- }; +- +- usbphy0: usbphy@8007c000 { +- status = "okay"; +- }; +- +- usbphy1: usbphy@8007e000 { +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb0: usb@80080000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb0_otg_apf28dev +- &usb0_id_pins_b>; +- vbus-supply = <®_usb0_vbus>; +- status = "okay"; +- }; +- +- usb1: usb@80090000 { +- status = "okay"; +- }; +- +- mac1: ethernet@800f4000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac1_pins_a>; +- phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; +- status = "okay"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_usb0_vbus: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "usb0_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 23 1>; +- enable-active-high; +- }; +- +- reg_can0_vcc: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "can0_vcc"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- user { +- label = "Heartbeat"; +- gpios = <&gpio0 21 0>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- +- pwms = <&pwm 3 191000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-button { +- label = "User button"; +- gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; +- linux,code = <0x100>; +- wakeup-source; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-apx4devkit.dts b/scripts/dtc/include-prefixes/arm/imx28-apx4devkit.dts +deleted file mode 100644 +index b86be320496b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-apx4devkit.dts ++++ /dev/null +@@ -1,240 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-#include "imx28.dtsi" +- +-/ { +- model = "Bluegiga APX4 Development Kit"; +- compatible = "bluegiga,apx4devkit", "fsl,imx28"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x04000000>; +- }; +- +- apb@80000000 { +- apbh@80000000 { +- nand-controller@8000c000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; +- status = "okay"; +- }; +- +- ssp0: spi@80010000 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; +- bus-width = <4>; +- status = "okay"; +- }; +- +- ssp2: spi@80014000 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>; +- bus-width = <4>; +- status = "okay"; +- }; +- +- pinctrl@80018000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_a>; +- +- hog_pins_a: hog@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_CE1N__GPIO_0_17 +- MX28_PAD_GPMI_RDY1__GPIO_0_21 +- MX28_PAD_SSP2_MISO__GPIO_2_18 +- MX28_PAD_SSP2_SS0__AUART3_TX /* was: 0x2131 - MX28_PAD_SSP2_SS0__GPIO_2_19 */ +- MX28_PAD_PWM3__GPIO_3_28 +- MX28_PAD_LCD_RESET__GPIO_3_30 +- MX28_PAD_JTAG_RTCK__GPIO_4_20 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_pins_apx4: lcdif-apx4@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_RD_E__LCD_VSYNC +- MX28_PAD_LCD_WR_RWN__LCD_HSYNC +- MX28_PAD_LCD_RS__LCD_DOTCLK +- MX28_PAD_LCD_CS__LCD_ENABLE +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP0_DATA4__SSP2_D0 +- MX28_PAD_SSP0_DATA5__SSP2_D3 +- MX28_PAD_SSP0_DATA6__SSP2_CMD +- MX28_PAD_SSP0_DATA7__SSP2_SCK +- MX28_PAD_SSP2_SS1__SSP2_D1 +- MX28_PAD_SSP2_SS2__SSP2_D2 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP0_DATA7__SSP2_SCK +- >; +- fsl,drive-strength = ; +- fsl,pull-up = ; +- }; +- }; +- +- lcdif@80030000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcdif_24bit_pins_a +- &lcdif_pins_apx4>; +- display = <&display0>; +- status = "okay"; +- +- display0: display0 { +- bits-per-pixel = <32>; +- bus-width = <24>; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing0 { +- clock-frequency = <30000000>; +- hactive = <800>; +- vactive = <480>; +- hback-porch = <88>; +- hfront-porch = <40>; +- vback-porch = <32>; +- vfront-porch = <13>; +- hsync-len = <48>; +- vsync-len = <3>; +- hsync-active = <1>; +- vsync-active = <1>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- }; +- }; +- }; +- }; +- +- apbx@80040000 { +- saif0: saif@80042000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&saif0_pins_a>; +- status = "okay"; +- }; +- +- saif1: saif@80046000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&saif1_pins_a>; +- fsl,saif-master = <&saif0>; +- status = "okay"; +- }; +- +- i2c0: i2c@80058000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_a>; +- status = "okay"; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; +- clocks = <&saif0>; +- }; +- +- pcf8563: rtc@51 { +- compatible = "phg,pcf8563"; +- reg = <0x51>; +- }; +- }; +- +- duart: serial@80074000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_pins_a>; +- status = "okay"; +- }; +- +- auart0: serial@8006a000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart0_pins_a>; +- status = "okay"; +- }; +- +- auart1: serial@8006c000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart1_2pins_a>; +- status = "okay"; +- }; +- +- auart2: serial@8006e000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart2_2pins_a>; +- status = "okay"; +- }; +- +- usbphy1: usbphy@8007e000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb1_pins_a>; +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb1: usb@80090000 { +- status = "okay"; +- }; +- +- mac0: ethernet@800f0000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_pins_a>; +- status = "okay"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_3p3v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- +- sound { +- compatible = "bluegiga,apx4devkit-sgtl5000", +- "fsl,mxs-audio-sgtl5000"; +- model = "apx4devkit-sgtl5000"; +- saif-controllers = <&saif0 &saif1>; +- audio-codec = <&sgtl5000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- user { +- label = "Heartbeat"; +- gpios = <&gpio3 28 0>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-cfa10036.dts b/scripts/dtc/include-prefixes/arm/imx28-cfa10036.dts +deleted file mode 100644 +index 85aa1cc3ff66..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-cfa10036.dts ++++ /dev/null +@@ -1,140 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Free Electrons +- */ +- +-/dts-v1/; +-#include "imx28.dtsi" +-#include +- +-/ { +- model = "Crystalfontz CFA-10036 Board"; +- compatible = "crystalfontz,cfa10036", "fsl,imx28"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x08000000>; +- }; +- +- apb@80000000 { +- apbh@80000000 { +- pinctrl@80018000 { +- ssd1306_cfa10036: ssd1306-10036@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP0_DATA7__GPIO_2_7 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- led_pins_cfa10036: leds-10036@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART1_RX__GPIO_3_4 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- usb0_otg_cfa10036: otg-10036@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_RDY0__USB0_ID +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mmc_pwr_cfa10036: mmc_pwr_cfa10036@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- 0x31c3 /* +- MX28_PAD_PWM3__GPIO_3_28 */ +- >; +- fsl,drive-strength = <0>; +- fsl,voltage = <1>; +- fsl,pull-up = <0>; +- }; +- +- }; +- +- ssp0: spi@80010000 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_4bit_pins_a +- &mmc0_cd_cfg &mmc0_sck_cfg>; +- vmmc-supply = <®_vddio_sd0>; +- bus-width = <4>; +- status = "okay"; +- }; +- }; +- +- apbx@80040000 { +- duart: serial@80074000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_pins_b>; +- status = "okay"; +- }; +- +- i2c0: i2c@80058000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_b>; +- clock-frequency = <400000>; +- status = "okay"; +- +- ssd1306: oled@3c { +- compatible = "solomon,ssd1306fb-i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ssd1306_cfa10036>; +- reg = <0x3c>; +- reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; +- solomon,height = <32>; +- solomon,width = <128>; +- solomon,page-offset = <0>; +- solomon,com-lrremap; +- solomon,com-invdir; +- solomon,com-offset = <32>; +- }; +- }; +- +- usbphy0: usbphy@8007c000 { +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb0: usb@80080000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb0_otg_cfa10036>; +- dr_mode = "peripheral"; +- phy_type = "utmi"; +- status = "okay"; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins_cfa10036>; +- +- power { +- gpios = <&gpio3 4 1>; +- default-state = "on"; +- }; +- }; +- +- reg_vddio_sd0: vddio-sd0 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc_pwr_cfa10036>; +- regulator-name = "vddio-sd0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 28 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-cfa10037.dts b/scripts/dtc/include-prefixes/arm/imx28-cfa10037.dts +deleted file mode 100644 +index d3e9a731525b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-cfa10037.dts ++++ /dev/null +@@ -1,83 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Free Electrons +- */ +- +-/* +- * The CFA-10049 is an expansion board for the CFA-10036 module, thus we +- * need to include the CFA-10036 DTS. +- */ +-#include "imx28-cfa10036.dts" +- +-/ { +- model = "Crystalfontz CFA-10037 Board"; +- compatible = "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; +- +- apb@80000000 { +- apbh@80000000 { +- pinctrl@80018000 { +- usb_pins_cfa10037: usb-10037@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_D07__GPIO_0_7 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mac0_pins_cfa10037: mac0-10037@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP2_SS2__GPIO_2_21 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- }; +- }; +- +- apbx@80040000 { +- usbphy1: usbphy@8007e000 { +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb1: usb@80090000 { +- vbus-supply = <®_usb1_vbus>; +- pinctrl-0 = <&usb1_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- +- mac0: ethernet@800f0000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_pins_a +- &mac0_pins_cfa10037>; +- phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <100>; +- status = "okay"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_usb1_vbus: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_pins_cfa10037>; +- regulator-name = "usb1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio0 7 1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-cfa10049.dts b/scripts/dtc/include-prefixes/arm/imx28-cfa10049.dts +deleted file mode 100644 +index a92b05ef390f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-cfa10049.dts ++++ /dev/null +@@ -1,428 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Free Electrons +- */ +- +-/* +- * The CFA-10049 is an expansion board for the CFA-10036 module, thus we +- * need to include the CFA-10036 DTS. +- */ +-#include "imx28-cfa10036.dts" +- +-/ { +- model = "Crystalfontz CFA-10049 Board"; +- compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28"; +- +- i2cmux { +- compatible = "i2c-mux-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2cmux_pins_cfa10049>; +- mux-gpios = <&gpio1 22 0 &gpio1 23 0>; +- i2c-parent = <&i2c1>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- adc0: nau7802@2a { +- compatible = "nuvoton,nau7802"; +- reg = <0x2a>; +- nuvoton,vldo = <3000>; +- }; +- }; +- +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- adc1: nau7802@2a { +- compatible = "nuvoton,nau7802"; +- reg = <0x2a>; +- nuvoton,vldo = <3000>; +- }; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- adc2: nau7802@2a { +- compatible = "nuvoton,nau7802"; +- reg = <0x2a>; +- nuvoton,vldo = <3000>; +- }; +- }; +- +- i2c@3 { +- reg = <3>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pca9555: pca9555@20 { +- compatible = "nxp,pca9555"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pca_pins_cfa10049>; +- interrupt-parent = <&gpio2>; +- interrupts = <19 0x2>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x20>; +- }; +- }; +- }; +- +- apb@80000000 { +- apbh@80000000 { +- pinctrl@80018000 { +- usb_pins_cfa10049: usb-10049@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_D07__GPIO_0_7 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- i2cmux_pins_cfa10049: i2cmux-10049@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D22__GPIO_1_22 +- MX28_PAD_LCD_D23__GPIO_1_23 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mac0_pins_cfa10049: mac0-10049@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP2_SS2__GPIO_2_21 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- pca_pins_cfa10049: pca-10049@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP2_SS0__GPIO_2_19 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- rotary_pins_cfa10049: rotary-10049@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_I2C0_SCL__GPIO_3_24 +- MX28_PAD_I2C0_SDA__GPIO_3_25 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- rotary_btn_pins_cfa10049: rotary-btn-10049@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SAIF1_SDATA0__GPIO_3_26 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- spi2_pins_cfa10049: spi2-cfa10049@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP2_SCK__GPIO_2_16 +- MX28_PAD_SSP2_MOSI__GPIO_2_17 +- MX28_PAD_SSP2_MISO__GPIO_2_18 +- MX28_PAD_AUART1_TX__GPIO_3_5 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- spi3_pins_cfa10049: spi3-cfa10049@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_RDN__GPIO_0_24 +- MX28_PAD_GPMI_RESETN__GPIO_0_28 +- MX28_PAD_GPMI_CE1N__GPIO_0_17 +- MX28_PAD_GPMI_ALE__GPIO_0_26 +- MX28_PAD_GPMI_CLE__GPIO_0_27 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_18bit_pins_cfa10049: lcdif-18bit@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D00__LCD_D0 +- MX28_PAD_LCD_D01__LCD_D1 +- MX28_PAD_LCD_D02__LCD_D2 +- MX28_PAD_LCD_D03__LCD_D3 +- MX28_PAD_LCD_D04__LCD_D4 +- MX28_PAD_LCD_D05__LCD_D5 +- MX28_PAD_LCD_D06__LCD_D6 +- MX28_PAD_LCD_D07__LCD_D7 +- MX28_PAD_LCD_D08__LCD_D8 +- MX28_PAD_LCD_D09__LCD_D9 +- MX28_PAD_LCD_D10__LCD_D10 +- MX28_PAD_LCD_D11__LCD_D11 +- MX28_PAD_LCD_D12__LCD_D12 +- MX28_PAD_LCD_D13__LCD_D13 +- MX28_PAD_LCD_D14__LCD_D14 +- MX28_PAD_LCD_D15__LCD_D15 +- MX28_PAD_LCD_D16__LCD_D16 +- MX28_PAD_LCD_D17__LCD_D17 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_pins_cfa10049: lcdif-evk@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_RD_E__LCD_VSYNC +- MX28_PAD_LCD_WR_RWN__LCD_HSYNC +- MX28_PAD_LCD_RS__LCD_DOTCLK +- MX28_PAD_LCD_CS__LCD_ENABLE +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_pins_cfa10049_pullup: lcdif-10049-pullup@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_RESET__GPIO_3_30 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- w1_gpio_pins: w1-gpio@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D21__GPIO_1_21 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; /* 0 will enable the keeper */ +- }; +- }; +- +- lcdif@80030000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcdif_18bit_pins_cfa10049 +- &lcdif_pins_cfa10049 +- &lcdif_pins_cfa10049_pullup>; +- display = <&display0>; +- status = "okay"; +- +- display0: display0 { +- bits-per-pixel = <32>; +- bus-width = <18>; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing0 { +- clock-frequency = <9216000>; +- hactive = <320>; +- vactive = <480>; +- hback-porch = <2>; +- hfront-porch = <2>; +- vback-porch = <2>; +- vfront-porch = <2>; +- hsync-len = <15>; +- vsync-len = <15>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- }; +- }; +- }; +- +- apbx@80040000 { +- pwm: pwm@80064000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm3_pins_b>; +- status = "okay"; +- }; +- +- i2c1: i2c@8005a000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins_a>; +- status = "okay"; +- }; +- +- usbphy1: usbphy@8007e000 { +- status = "okay"; +- }; +- +- lradc@80050000 { +- status = "okay"; +- fsl,lradc-touchscreen-wires = <4>; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb1: usb@80090000 { +- vbus-supply = <®_usb1_vbus>; +- pinctrl-0 = <&usb1_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_usb1_vbus: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_pins_cfa10049>; +- regulator-name = "usb1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio0 7 1>; +- }; +- }; +- +- ahb@80080000 { +- mac0: ethernet@800f0000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_pins_a +- &mac0_pins_cfa10049>; +- phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <100>; +- status = "okay"; +- }; +- }; +- +- spi2 { +- compatible = "spi-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pins_cfa10049>; +- status = "okay"; +- gpio-sck = <&gpio2 16 0>; +- gpio-mosi = <&gpio2 17 0>; +- gpio-miso = <&gpio2 18 0>; +- cs-gpios = <&gpio3 5 0>; +- num-chipselects = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- hx8357: hx8357@0 { +- compatible = "himax,hx8357b", "himax,hx8357"; +- reg = <0>; +- spi-max-frequency = <100000>; +- spi-cpol; +- spi-cpha; +- gpios-reset = <&gpio3 30 0>; +- im-gpios = <&gpio5 4 0 &gpio5 5 0 &gpio5 6 0>; +- }; +- }; +- +- spi3 { +- compatible = "spi-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi3_pins_cfa10049>; +- status = "okay"; +- gpio-sck = <&gpio0 24 0>; +- gpio-mosi = <&gpio0 28 0>; +- cs-gpios = <&gpio0 17 0 &gpio0 26 0 &gpio0 27 0>; +- num-chipselects = <3>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio5: gpio5@0 { +- compatible = "fairchild,74hc595"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0>; +- registers-number = <2>; +- spi-max-frequency = <100000>; +- }; +- +- gpio6: gpio6@1 { +- compatible = "fairchild,74hc595"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <1>; +- registers-number = <4>; +- spi-max-frequency = <100000>; +- }; +- +- dac0: dh2228@2 { +- compatible = "rohm,dh2228fv"; +- reg = <2>; +- spi-max-frequency = <100000>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rotary_btn_pins_cfa10049>; +- +- rotary_button { +- label = "rotary_button"; +- gpios = <&gpio3 26 1>; +- debounce-interval = <10>; +- linux,code = <28>; +- }; +- }; +- +- rotary { +- compatible = "rotary-encoder"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rotary_pins_cfa10049>; +- gpios = <&gpio3 24 1>, <&gpio3 25 1>; +- linux,axis = <1>; /* REL_Y */ +- rotary-encoder,relative-axis; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 3 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- +- }; +- +- onewire { +- compatible = "w1-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&w1_gpio_pins>; +- status = "okay"; +- gpios = <&gpio1 21 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-cfa10055.dts b/scripts/dtc/include-prefixes/arm/imx28-cfa10055.dts +deleted file mode 100644 +index d05c370dfc17..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-cfa10055.dts ++++ /dev/null +@@ -1,161 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Crystalfontz America, Inc. +- * Free Electrons +- */ +- +-/* +- * The CFA-10055 is an expansion board for the CFA-10036 module and +- * CFA-10037, thus we need to include the CFA-10037 DTS. +- */ +-#include "imx28-cfa10037.dts" +- +-/ { +- model = "Crystalfontz CFA-10055 Board"; +- compatible = "crystalfontz,cfa10055", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; +- +- apb@80000000 { +- apbh@80000000 { +- pinctrl@80018000 { +- spi2_pins_cfa10055: spi2-cfa10055@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP2_SCK__GPIO_2_16 +- MX28_PAD_SSP2_MOSI__GPIO_2_17 +- MX28_PAD_SSP2_MISO__GPIO_2_18 +- MX28_PAD_AUART1_TX__GPIO_3_5 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_18bit_pins_cfa10055: lcdif-18bit@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D00__LCD_D0 +- MX28_PAD_LCD_D01__LCD_D1 +- MX28_PAD_LCD_D02__LCD_D2 +- MX28_PAD_LCD_D03__LCD_D3 +- MX28_PAD_LCD_D04__LCD_D4 +- MX28_PAD_LCD_D05__LCD_D5 +- MX28_PAD_LCD_D06__LCD_D6 +- MX28_PAD_LCD_D07__LCD_D7 +- MX28_PAD_LCD_D08__LCD_D8 +- MX28_PAD_LCD_D09__LCD_D9 +- MX28_PAD_LCD_D10__LCD_D10 +- MX28_PAD_LCD_D11__LCD_D11 +- MX28_PAD_LCD_D12__LCD_D12 +- MX28_PAD_LCD_D13__LCD_D13 +- MX28_PAD_LCD_D14__LCD_D14 +- MX28_PAD_LCD_D15__LCD_D15 +- MX28_PAD_LCD_D16__LCD_D16 +- MX28_PAD_LCD_D17__LCD_D17 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_pins_cfa10055: lcdif-evk@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_RD_E__LCD_VSYNC +- MX28_PAD_LCD_WR_RWN__LCD_HSYNC +- MX28_PAD_LCD_RS__LCD_DOTCLK +- MX28_PAD_LCD_CS__LCD_ENABLE +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_pins_cfa10055_pullup: lcdif-10055-pullup@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_RESET__GPIO_3_30 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- }; +- +- lcdif@80030000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcdif_18bit_pins_cfa10055 +- &lcdif_pins_cfa10055 +- &lcdif_pins_cfa10055_pullup>; +- display = <&display0>; +- status = "okay"; +- +- display0: display0 { +- bits-per-pixel = <32>; +- bus-width = <18>; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing0 { +- clock-frequency = <9216000>; +- hactive = <320>; +- vactive = <480>; +- hback-porch = <2>; +- hfront-porch = <2>; +- vback-porch = <2>; +- vfront-porch = <2>; +- hsync-len = <15>; +- vsync-len = <15>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- }; +- }; +- }; +- +- apbx@80040000 { +- lradc@80050000 { +- fsl,lradc-touchscreen-wires = <4>; +- status = "okay"; +- }; +- +- pwm: pwm@80064000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm3_pins_b>; +- status = "okay"; +- }; +- }; +- }; +- +- spi2 { +- compatible = "spi-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pins_cfa10055>; +- status = "okay"; +- gpio-sck = <&gpio2 16 0>; +- gpio-mosi = <&gpio2 17 0>; +- gpio-miso = <&gpio2 18 0>; +- cs-gpios = <&gpio3 5 0>; +- num-chipselects = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- hx8357: hx8357@0 { +- compatible = "himax,hx8357b", "himax,hx8357"; +- reg = <0>; +- spi-max-frequency = <100000>; +- spi-cpol; +- spi-cpha; +- gpios-reset = <&gpio3 30 0>; +- }; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 3 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-cfa10056.dts b/scripts/dtc/include-prefixes/arm/imx28-cfa10056.dts +deleted file mode 100644 +index c1060bd5f17f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-cfa10056.dts ++++ /dev/null +@@ -1,113 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Free Electrons +- */ +- +-/* +- * The CFA-10055 is an expansion board for the CFA-10036 module and +- * CFA-10037, thus we need to include the CFA-10037 DTS. +- */ +-#include "imx28-cfa10037.dts" +- +-/ { +- model = "Crystalfontz CFA-10056 Board"; +- compatible = "crystalfontz,cfa10056", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; +- +- apb@80000000 { +- apbh@80000000 { +- pinctrl@80018000 { +- spi2_pins_cfa10056: spi2-cfa10056@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP2_SCK__GPIO_2_16 +- MX28_PAD_SSP2_MOSI__GPIO_2_17 +- MX28_PAD_SSP2_MISO__GPIO_2_18 +- MX28_PAD_AUART1_TX__GPIO_3_5 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_pins_cfa10056: lcdif-10056@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_RD_E__LCD_VSYNC +- MX28_PAD_LCD_WR_RWN__LCD_HSYNC +- MX28_PAD_LCD_RS__LCD_DOTCLK +- MX28_PAD_LCD_CS__LCD_ENABLE +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_pins_cfa10056_pullup: lcdif-10056-pullup@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_RESET__GPIO_3_30 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- }; +- +- lcdif@80030000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcdif_24bit_pins_a +- &lcdif_pins_cfa10056 +- &lcdif_pins_cfa10056_pullup >; +- display = <&display0>; +- status = "okay"; +- +- display0: display0 { +- bits-per-pixel = <32>; +- bus-width = <24>; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing0 { +- clock-frequency = <32000000>; +- hactive = <480>; +- vactive = <800>; +- hback-porch = <2>; +- hfront-porch = <2>; +- vback-porch = <2>; +- vfront-porch = <2>; +- hsync-len = <5>; +- vsync-len = <5>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- }; +- }; +- }; +- }; +- +- spi2 { +- compatible = "spi-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pins_cfa10056>; +- status = "okay"; +- gpio-sck = <&gpio2 16 0>; +- gpio-mosi = <&gpio2 17 0>; +- gpio-miso = <&gpio2 18 0>; +- cs-gpios = <&gpio3 5 0>; +- num-chipselects = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- hx8369: hx8369@0 { +- compatible = "himax,hx8369a", "himax,hx8369"; +- reg = <0>; +- spi-max-frequency = <100000>; +- spi-cpol; +- spi-cpha; +- gpios-reset = <&gpio3 30 0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-cfa10057.dts b/scripts/dtc/include-prefixes/arm/imx28-cfa10057.dts +deleted file mode 100644 +index 2f7e479dbc74..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-cfa10057.dts ++++ /dev/null +@@ -1,171 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Crystalfontz America, Inc. +- * Copyright 2012 Free Electrons +- */ +- +-/* +- * The CFA-10057 is an expansion board for the CFA-10036 module, thus we +- * need to include the CFA-10036 DTS. +- */ +-#include "imx28-cfa10036.dts" +- +-/ { +- model = "Crystalfontz CFA-10057 Board"; +- compatible = "crystalfontz,cfa10057", "crystalfontz,cfa10036", "fsl,imx28"; +- +- apb@80000000 { +- apbh@80000000 { +- pinctrl@80018000 { +- usb_pins_cfa10057: usb-10057@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_D07__GPIO_0_7 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_18bit_pins_cfa10057: lcdif-18bit@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D00__LCD_D0 +- MX28_PAD_LCD_D01__LCD_D1 +- MX28_PAD_LCD_D02__LCD_D2 +- MX28_PAD_LCD_D03__LCD_D3 +- MX28_PAD_LCD_D04__LCD_D4 +- MX28_PAD_LCD_D05__LCD_D5 +- MX28_PAD_LCD_D06__LCD_D6 +- MX28_PAD_LCD_D07__LCD_D7 +- MX28_PAD_LCD_D08__LCD_D8 +- MX28_PAD_LCD_D09__LCD_D9 +- MX28_PAD_LCD_D10__LCD_D10 +- MX28_PAD_LCD_D11__LCD_D11 +- MX28_PAD_LCD_D12__LCD_D12 +- MX28_PAD_LCD_D13__LCD_D13 +- MX28_PAD_LCD_D14__LCD_D14 +- MX28_PAD_LCD_D15__LCD_D15 +- MX28_PAD_LCD_D16__LCD_D16 +- MX28_PAD_LCD_D17__LCD_D17 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_pins_cfa10057: lcdif-evk@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_RD_E__LCD_VSYNC +- MX28_PAD_LCD_WR_RWN__LCD_HSYNC +- MX28_PAD_LCD_RS__LCD_DOTCLK +- MX28_PAD_LCD_CS__LCD_ENABLE +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- }; +- +- lcdif@80030000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcdif_18bit_pins_cfa10057 +- &lcdif_pins_cfa10057>; +- display = <&display0>; +- status = "okay"; +- +- display0: display0 { +- bits-per-pixel = <32>; +- bus-width = <18>; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing0 { +- clock-frequency = <30000000>; +- hactive = <480>; +- vactive = <800>; +- hfront-porch = <12>; +- hback-porch = <2>; +- vfront-porch = <5>; +- vback-porch = <3>; +- hsync-len = <2>; +- vsync-len = <2>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- }; +- }; +- }; +- +- apbx@80040000 { +- lradc@80050000 { +- fsl,lradc-touchscreen-wires = <4>; +- status = "okay"; +- }; +- +- pwm: pwm@80064000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm4_pins_a>; +- status = "okay"; +- }; +- +- i2c1: i2c@8005a000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins_a>; +- status = "okay"; +- }; +- +- usbphy1: usbphy@8007e000 { +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb1: usb@80090000 { +- vbus-supply = <®_usb1_vbus>; +- pinctrl-0 = <&usb1_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_usb1_vbus: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_pins_cfa10057>; +- regulator-name = "usb1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio0 7 1>; +- }; +- }; +- +- ahb@80080000 { +- mac0: ethernet@800f0000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_pins_a>; +- phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <100>; +- status = "okay"; +- }; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 4 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-cfa10058.dts b/scripts/dtc/include-prefixes/arm/imx28-cfa10058.dts +deleted file mode 100644 +index 4465fd86785a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-cfa10058.dts ++++ /dev/null +@@ -1,138 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Crystalfontz America, Inc. +- * Copyright 2013 Free Electrons +- */ +- +-/* +- * The CFA-10058 is an expansion board for the CFA-10036 module, thus we +- * need to include the CFA-10036 DTS. +- */ +-#include "imx28-cfa10036.dts" +- +-/ { +- model = "Crystalfontz CFA-10058 Board"; +- compatible = "crystalfontz,cfa10058", "crystalfontz,cfa10036", "fsl,imx28"; +- +- apb@80000000 { +- apbh@80000000 { +- pinctrl@80018000 { +- usb_pins_cfa10058: usb-10058@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_D07__GPIO_0_7 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_pins_cfa10058: lcdif-10058@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_RD_E__LCD_VSYNC +- MX28_PAD_LCD_WR_RWN__LCD_HSYNC +- MX28_PAD_LCD_RS__LCD_DOTCLK +- MX28_PAD_LCD_CS__LCD_ENABLE +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- }; +- +- lcdif@80030000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcdif_24bit_pins_a +- &lcdif_pins_cfa10058>; +- display = <&display0>; +- status = "okay"; +- +- display0: display0 { +- bits-per-pixel = <32>; +- bus-width = <24>; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing0 { +- clock-frequency = <30000000>; +- hactive = <800>; +- vactive = <480>; +- hback-porch = <40>; +- hfront-porch = <40>; +- vback-porch = <13>; +- vfront-porch = <29>; +- hsync-len = <8>; +- vsync-len = <8>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- }; +- }; +- }; +- +- apbx@80040000 { +- lradc@80050000 { +- fsl,lradc-touchscreen-wires = <4>; +- status = "okay"; +- }; +- +- pwm: pwm@80064000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm3_pins_b>; +- status = "okay"; +- }; +- +- usbphy1: usbphy@8007e000 { +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb1: usb@80090000 { +- vbus-supply = <®_usb1_vbus>; +- pinctrl-0 = <&usb1_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_usb1_vbus: regulator@0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_pins_cfa10058>; +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "usb1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio0 7 1>; +- }; +- }; +- +- ahb@80080000 { +- mac0: ethernet@800f0000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_pins_a>; +- phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <100>; +- status = "okay"; +- }; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 3 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-duckbill-2-485.dts b/scripts/dtc/include-prefixes/arm/imx28-duckbill-2-485.dts +deleted file mode 100644 +index d451fa018d83..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-duckbill-2-485.dts ++++ /dev/null +@@ -1,184 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2015-2017 I2SE GmbH +- * Copyright (C) 2016 Michael Heimpold +- */ +- +-/dts-v1/; +-#include +-#include +-#include "imx28.dtsi" +- +-/ { +- model = "I2SE Duckbill 2 485"; +- compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x08000000>; +- }; +- +- apb@80000000 { +- apbh@80000000 { +- ssp0: spi@80010000 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_8bit_pins_a +- &mmc0_cd_cfg &mmc0_sck_cfg>; +- bus-width = <8>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +- non-removable; +- }; +- +- ssp2: spi@80014000 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_4bit_pins_b +- &mmc2_cd_cfg &mmc2_sck_cfg_b>; +- bus-width = <4>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +- }; +- +- pinctrl@80018000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_a>; +- +- hog_pins_a: hog@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mac0_phy_reset_pin: mac0-phy-reset@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mac0_phy_int_pin: mac0-phy-int@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- led_pins: leds@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SAIF0_MCLK__GPIO_3_20 +- MX28_PAD_SAIF0_LRCLK__GPIO_3_21 +- MX28_PAD_I2C0_SCL__GPIO_3_24 +- MX28_PAD_I2C0_SDA__GPIO_3_25 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- }; +- }; +- +- apbx@80040000 { +- lradc@80050000 { +- status = "okay"; +- }; +- +- auart0: serial@8006a000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart0_2pins_a>; +- status = "okay"; +- }; +- +- duart: serial@80074000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_pins_a>; +- status = "okay"; +- }; +- +- usbphy0: usbphy@8007c000 { +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb0: usb@80080000 { +- status = "okay"; +- dr_mode = "peripheral"; +- }; +- +- mac0: ethernet@800f0000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; +- phy-supply = <®_3p3v>; +- phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <25>; +- phy-handle = <ðphy>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_phy_int_pin>; +- interrupt-parent = <&gpio0>; +- interrupts = <7 IRQ_TYPE_EDGE_FALLING>; +- max-speed = <100>; +- }; +- }; +- }; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins>; +- +- status-red { +- label = "duckbill:red:status"; +- gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- status-green { +- label = "duckbill:green:status"; +- gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- rs485-red { +- label = "duckbill:red:rs485"; +- gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; +- }; +- +- rs485-green { +- label = "duckbill:green:rs485"; +- gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-duckbill-2-enocean.dts b/scripts/dtc/include-prefixes/arm/imx28-duckbill-2-enocean.dts +deleted file mode 100644 +index bacb846f99e3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-duckbill-2-enocean.dts ++++ /dev/null +@@ -1,213 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2015-2017 I2SE GmbH +- * Copyright (C) 2016 Michael Heimpold +- */ +- +-/dts-v1/; +-#include +-#include +-#include +-#include "imx28.dtsi" +- +-/ { +- model = "I2SE Duckbill 2 EnOcean"; +- compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x08000000>; +- }; +- +- apb@80000000 { +- apbh@80000000 { +- ssp0: spi@80010000 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_8bit_pins_a +- &mmc0_cd_cfg &mmc0_sck_cfg>; +- bus-width = <8>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +- non-removable; +- }; +- +- ssp2: spi@80014000 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_4bit_pins_b +- &mmc2_cd_cfg &mmc2_sck_cfg_b>; +- bus-width = <4>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +- }; +- +- pinctrl@80018000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_a>; +- +- hog_pins_a: hog@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mac0_phy_reset_pin: mac0-phy-reset@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mac0_phy_int_pin: mac0-phy-int@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- led_pins: leds@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SAIF0_MCLK__GPIO_3_20 +- MX28_PAD_SAIF0_LRCLK__GPIO_3_21 +- MX28_PAD_AUART0_CTS__GPIO_3_2 +- MX28_PAD_I2C0_SCL__GPIO_3_24 +- MX28_PAD_I2C0_SDA__GPIO_3_25 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- enocean_button: enocean-button@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART0_RTS__GPIO_3_3 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- }; +- }; +- +- apbx@80040000 { +- lradc@80050000 { +- status = "okay"; +- }; +- +- auart0: serial@8006a000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart0_2pins_a>; +- status = "okay"; +- }; +- +- duart: serial@80074000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_pins_a>; +- status = "okay"; +- }; +- +- usbphy0: usbphy@8007c000 { +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb0: usb@80080000 { +- status = "okay"; +- dr_mode = "peripheral"; +- }; +- +- mac0: ethernet@800f0000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; +- phy-supply = <®_3p3v>; +- phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <25>; +- phy-handle = <ðphy>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_phy_int_pin>; +- interrupt-parent = <&gpio0>; +- interrupts = <7 IRQ_TYPE_EDGE_FALLING>; +- max-speed = <100>; +- }; +- }; +- }; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins>; +- +- status-red { +- label = "duckbill:red:status"; +- gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- status-green { +- label = "duckbill:green:status"; +- gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- enocean-blue { +- label = "duckbill:blue:enocean"; +- gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; +- }; +- +- enocean-red { +- label = "duckbill:red:enocean"; +- gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; +- }; +- +- enocean-green { +- label = "duckbill:green:enocean"; +- gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&enocean_button>; +- +- enocean { +- label = "EnOcean"; +- linux,code = ; +- gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-duckbill-2-spi.dts b/scripts/dtc/include-prefixes/arm/imx28-duckbill-2-spi.dts +deleted file mode 100644 +index 0e8be5975709..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-duckbill-2-spi.dts ++++ /dev/null +@@ -1,194 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2015-2017 I2SE GmbH +- * Copyright (C) 2016 Michael Heimpold +- */ +- +-/dts-v1/; +-#include +-#include +-#include "imx28.dtsi" +- +-/ { +- model = "I2SE Duckbill 2 SPI"; +- compatible = "i2se,duckbill-2-spi", "i2se,duckbill-2", "fsl,imx28"; +- +- aliases { +- ethernet1 = &qca7000; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x08000000>; +- }; +- +- apb@80000000 { +- apbh@80000000 { +- ssp0: spi@80010000 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_8bit_pins_a +- &mmc0_cd_cfg &mmc0_sck_cfg>; +- bus-width = <8>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +- non-removable; +- }; +- +- ssp2: spi@80014000 { +- compatible = "fsl,imx28-spi"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pins_a>; +- status = "okay"; +- +- qca7000: ethernet@0 { +- reg = <0>; +- compatible = "qca,qca7000"; +- pinctrl-names = "default"; +- pinctrl-0 = <&qca7000_pins>; +- interrupt-parent = <&gpio3>; +- interrupts = <3 IRQ_TYPE_EDGE_RISING>; +- spi-cpha; +- spi-cpol; +- spi-max-frequency = <8000000>; +- }; +- }; +- +- pinctrl@80018000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_a>; +- +- hog_pins_a: hog@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mac0_phy_reset_pin: mac0-phy-reset@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mac0_phy_int_pin: mac0-phy-int@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- led_pins: led@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SAIF0_MCLK__GPIO_3_20 +- MX28_PAD_SAIF0_LRCLK__GPIO_3_21 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- qca7000_pins: qca7000@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART0_RTS__GPIO_3_3 /* Interrupt */ +- MX28_PAD_LCD_D13__GPIO_1_13 /* QCA7K reset */ +- MX28_PAD_LCD_D14__GPIO_1_14 /* GPIO 0 */ +- MX28_PAD_LCD_D15__GPIO_1_15 /* GPIO 1 */ +- MX28_PAD_LCD_D18__GPIO_1_18 /* GPIO 2 */ +- MX28_PAD_LCD_D21__GPIO_1_21 /* GPIO 3 */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- }; +- }; +- +- apbx@80040000 { +- lradc@80050000 { +- status = "okay"; +- }; +- +- duart: serial@80074000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_pins_a>; +- status = "okay"; +- }; +- +- usbphy0: usbphy@8007c000 { +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb0: usb@80080000 { +- status = "okay"; +- dr_mode = "peripheral"; +- }; +- +- mac0: ethernet@800f0000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; +- phy-supply = <®_3p3v>; +- phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <25>; +- phy-handle = <ðphy>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_phy_int_pin>; +- interrupt-parent = <&gpio0>; +- interrupts = <7 IRQ_TYPE_EDGE_FALLING>; +- max-speed = <100>; +- }; +- }; +- }; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins>; +- +- status-red { +- label = "duckbill:red:status"; +- gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- status-green { +- label = "duckbill:green:status"; +- gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-duckbill-2.dts b/scripts/dtc/include-prefixes/arm/imx28-duckbill-2.dts +deleted file mode 100644 +index 23fd3036404d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-duckbill-2.dts ++++ /dev/null +@@ -1,178 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2015-2017 I2SE GmbH +- * Copyright (C) 2016 Michael Heimpold +- */ +- +-/dts-v1/; +-#include +-#include +-#include "imx28.dtsi" +- +-/ { +- model = "I2SE Duckbill 2"; +- compatible = "i2se,duckbill-2", "fsl,imx28"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x08000000>; +- }; +- +- apb@80000000 { +- apbh@80000000 { +- ssp0: spi@80010000 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_8bit_pins_a +- &mmc0_cd_cfg &mmc0_sck_cfg>; +- bus-width = <8>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +- non-removable; +- }; +- +- ssp2: spi@80014000 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_4bit_pins_b +- &mmc2_cd_cfg &mmc2_sck_cfg_b>; +- bus-width = <4>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +- }; +- +- pinctrl@80018000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_a>; +- +- hog_pins_a: hog@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mac0_phy_reset_pin: mac0-phy-reset@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mac0_phy_int_pin: mac0-phy-int@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- led_pins: leds@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SAIF0_MCLK__GPIO_3_20 +- MX28_PAD_SAIF0_LRCLK__GPIO_3_21 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- }; +- }; +- +- apbx@80040000 { +- lradc@80050000 { +- status = "okay"; +- }; +- +- i2c0: i2c@80058000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_a>; +- status = "okay"; +- }; +- +- auart0: serial@8006a000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart0_2pins_a>; +- status = "okay"; +- }; +- +- duart: serial@80074000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_pins_a>; +- status = "okay"; +- }; +- +- usbphy0: usbphy@8007c000 { +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb0: usb@80080000 { +- status = "okay"; +- dr_mode = "peripheral"; +- }; +- +- mac0: ethernet@800f0000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; +- phy-supply = <®_3p3v>; +- phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <25>; +- phy-handle = <ðphy>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_phy_int_pin>; +- interrupt-parent = <&gpio0>; +- interrupts = <7 IRQ_TYPE_EDGE_FALLING>; +- max-speed = <100>; +- }; +- }; +- }; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins>; +- +- status-red { +- label = "duckbill:red:status"; +- gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- status-green { +- label = "duckbill:green:status"; +- gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-duckbill.dts b/scripts/dtc/include-prefixes/arm/imx28-duckbill.dts +deleted file mode 100644 +index c666afb12445..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-duckbill.dts ++++ /dev/null +@@ -1,147 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2013-2014,2016 Michael Heimpold +- * Copyright (C) 2015-2017 I2SE GmbH +- */ +- +-/dts-v1/; +-#include +-#include "imx28.dtsi" +- +-/ { +- model = "I2SE Duckbill"; +- compatible = "i2se,duckbill", "fsl,imx28"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x08000000>; +- }; +- +- apb@80000000 { +- apbh@80000000 { +- ssp0: spi@80010000 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_4bit_pins_a +- &mmc0_cd_cfg &mmc0_sck_cfg>; +- bus-width = <4>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +- }; +- +- ssp2: spi@80014000 { +- compatible = "fsl,imx28-spi"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pins_a>; +- status = "okay"; +- }; +- +- pinctrl@80018000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_a>; +- +- hog_pins_a: hog@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mac0_phy_reset_pin: mac0-phy-reset@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- led_pins: leds@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART1_RX__GPIO_3_4 +- MX28_PAD_AUART1_TX__GPIO_3_5 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- }; +- }; +- +- apbx@80040000 { +- lradc@80050000 { +- status = "okay"; +- }; +- +- i2c0: i2c@80058000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_a>; +- status = "okay"; +- }; +- +- auart0: serial@8006a000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart0_2pins_a>; +- status = "okay"; +- }; +- +- duart: serial@80074000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_pins_a>; +- status = "okay"; +- }; +- +- usbphy0: usbphy@8007c000 { +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb0: usb@80080000 { +- status = "okay"; +- dr_mode = "peripheral"; +- }; +- +- mac0: ethernet@800f0000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; +- phy-supply = <®_3p3v>; +- phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <25>; +- status = "okay"; +- }; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins>; +- +- status-red { +- label = "duckbill:red:status"; +- gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- status-green { +- label = "duckbill:green:status"; +- gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-eukrea-mbmx283lc.dts b/scripts/dtc/include-prefixes/arm/imx28-eukrea-mbmx283lc.dts +deleted file mode 100644 +index 29f8a3a245d4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-eukrea-mbmx283lc.dts ++++ /dev/null +@@ -1,64 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Eukréa Electromatique +- * Copyright 2013 Eukréa Electromatique +- */ +- +-/* +- * Module contains : i.MX282 + 64MB DDR2 + NAND + Ethernet PHY + RTC +- */ +- +-/dts-v1/; +-#include "imx28-eukrea-mbmx28lc.dtsi" +- +-/ { +- model = "Eukrea Electromatique MBMX283LC"; +- compatible = "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x04000000>; +- }; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpmi_pins_a>; +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_a>; +- status = "okay"; +- +- pcf8563: rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +-}; +- +- +-&mac0 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_pins_a>; +- phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pinctrl{ +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_cpuimx283>; +- +- hog_pins_cpuimx283: hog-cpuimx283@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_ENET0_RX_CLK__GPIO_4_13 +- MX28_PAD_ENET0_TX_CLK__GPIO_4_5 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-eukrea-mbmx287lc.dts b/scripts/dtc/include-prefixes/arm/imx28-eukrea-mbmx287lc.dts +deleted file mode 100644 +index cd875ace168d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-eukrea-mbmx287lc.dts ++++ /dev/null +@@ -1,43 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Eukréa Electromatique +- * Copyright 2013 Eukréa Electromatique +- */ +- +-/* +- * Module contains : i.MX287 + 128MB DDR2 + NAND + 2 x Ethernet PHY + RTC +- */ +- +-#include "imx28-eukrea-mbmx283lc.dts" +- +-/ { +- model = "Eukrea Electromatique MBMX287LC"; +- compatible = "eukrea,mbmx287lc", "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x08000000>; +- }; +-}; +- +-&mac1 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac1_pins_a>; +- phy-reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_cpuimx283 &hog_pins_cpuimx287>; +- hog_pins_cpuimx287: hog-cpuimx287@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SPDIF__GPIO_3_27 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-eukrea-mbmx28lc.dtsi b/scripts/dtc/include-prefixes/arm/imx28-eukrea-mbmx28lc.dtsi +deleted file mode 100644 +index 3280fddaaf0d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-eukrea-mbmx28lc.dtsi ++++ /dev/null +@@ -1,323 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Eukréa Electromatique +- * Copyright 2013 Eukréa Electromatique +- */ +- +-#include +-#include +-#include "imx28.dtsi" +- +-/ { +- model = "Eukrea Electromatique MBMX28LC"; +- compatible = "eukrea,mbmx28lc", "fsl,imx28"; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 4 1000000>; +- brightness-levels = <0 25 50 75 100 125 150 175 200 225 255>; +- default-brightness-level = <10>; +- }; +- +- button-sw3 { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_button_sw3_pins_mbmx28lc>; +- +- sw3 { +- label = "SW3"; +- gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- button-sw4 { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_button_sw4_pins_mbmx28lc>; +- +- sw4 { +- label = "SW4"; +- gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- led-d6 { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_d6_pins_mbmx28lc>; +- +- led1 { +- label = "d6"; +- gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- led-d7 { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_d7_pins_mbmx28lc>; +- +- led1 { +- label = "d7"; +- gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_3p3v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_lcd_3v3: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <®_lcd_3v3_pins_mbmx28lc>; +- regulator-name = "lcd-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb0_vbus: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <®_usb0_vbus_pins_mbmx28lc>; +- regulator-name = "usb0_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb1_vbus: regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- pinctrl-names = "default"; +- pinctrl-0 = <®_usb1_vbus_pins_mbmx28lc>; +- regulator-name = "usb1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- }; +- +- sound { +- compatible = "fsl,imx28-mbmx28lc-sgtl5000", +- "fsl,mxs-audio-sgtl5000"; +- model = "imx28-mbmx28lc-sgtl5000"; +- saif-controllers = <&saif0 &saif1>; +- audio-codec = <&sgtl5000>; +- }; +-}; +- +-&duart { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_4pins_a>; +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_a>; +- status = "okay"; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; +- clocks = <&saif0>; +- }; +-}; +- +-&lcdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcdif_18bit_pins_a &lcdif_pins_mbmx28lc>; +- lcd-supply = <®_lcd_3v3>; +- display = <&display0>; +- status = "okay"; +- +- display0: display0 { +- model = "43WVF1G-0"; +- bits-per-pixel = <16>; +- bus-width = <18>; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing0 { +- clock-frequency = <9072000>; +- hactive = <480>; +- vactive = <272>; +- hback-porch = <10>; +- hfront-porch = <5>; +- vback-porch = <8>; +- vfront-porch = <8>; +- hsync-len = <40>; +- vsync-len = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- }; +-}; +- +-&lradc { +- fsl,lradc-touchscreen-wires = <4>; +- status = "okay"; +-}; +- +-&pinctrl { +- gpio_button_sw3_pins_mbmx28lc: gpio-button-sw3-mbmx28lc@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D21__GPIO_1_21 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- gpio_button_sw4_pins_mbmx28lc: gpio-button-sw4-mbmx28lc@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D20__GPIO_1_20 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_pins_mbmx28lc: lcdif-mbmx28lc@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_VSYNC__LCD_VSYNC +- MX28_PAD_LCD_HSYNC__LCD_HSYNC +- MX28_PAD_LCD_DOTCLK__LCD_DOTCLK +- MX28_PAD_LCD_ENABLE__LCD_ENABLE +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- led_d6_pins_mbmx28lc: led-d6-mbmx28lc@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D23__GPIO_1_23 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- led_d7_pins_mbmx28lc: led-d7-mbmx28lc@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D22__GPIO_1_22 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- reg_lcd_3v3_pins_mbmx28lc: lcd-3v3-mbmx28lc@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_RESET__GPIO_3_30 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- reg_usb0_vbus_pins_mbmx28lc: reg-usb0-vbus-mbmx28lc@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D18__GPIO_1_18 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- reg_usb1_vbus_pins_mbmx28lc: reg-usb1-vbus-mbmx28lc@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D19__GPIO_1_19 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm4_pins_a>; +- status = "okay"; +-}; +- +-&saif0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&saif0_pins_a>; +- status = "okay"; +-}; +- +-&saif1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&saif1_pins_a>; +- fsl,saif-master = <&saif0>; +- status = "okay"; +-}; +- +-&ssp0 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_cd_cfg &mmc0_sck_cfg>; +- bus-width = <4>; +- cd-inverted; +- status = "okay"; +-}; +- +-&usb0 { +- disable-over-current; +- vbus-supply = <®_usb0_vbus>; +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb0_id_pins_b>; +-}; +- +-&usb1 { +- vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +- +-&usbphy0 { +- status = "okay"; +-}; +- +-&usbphy1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-evk.dts b/scripts/dtc/include-prefixes/arm/imx28-evk.dts +deleted file mode 100644 +index 7e2b0f198dfa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-evk.dts ++++ /dev/null +@@ -1,360 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2012 Freescale Semiconductor, Inc. +- +-/dts-v1/; +-#include "imx28.dtsi" +- +-/ { +- model = "Freescale i.MX28 Evaluation Kit"; +- compatible = "fsl,imx28-evk", "fsl,imx28"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x08000000>; +- }; +- +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_vddio_sd0: regulator-vddio-sd0 { +- compatible = "regulator-fixed"; +- regulator-name = "vddio-sd0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 28 0>; +- }; +- +- reg_fec_3v3: regulator-fec-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "fec-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 15 0>; +- }; +- +- reg_usb0_vbus: regulator-usb0-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb0_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 9 0>; +- enable-active-high; +- }; +- +- reg_usb1_vbus: regulator-usb1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 8 0>; +- enable-active-high; +- }; +- +- reg_lcd_3v3: regulator-lcd-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "lcd-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 30 0>; +- enable-active-high; +- }; +- +- reg_can_3v3: regulator-can-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "can-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 13 0>; +- enable-active-high; +- }; +- +- reg_lcd_5v: regulator-lcd-5v { +- compatible = "regulator-fixed"; +- regulator-name = "lcd-5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- panel { +- compatible = "sii,43wvf1g"; +- backlight = <&backlight_display>; +- dvdd-supply = <®_lcd_3v3>; +- avdd-supply = <®_lcd_5v>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +- +- apb@80000000 { +- apbh@80000000 { +- nand-controller@8000c000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg +- &gpmi_pins_evk>; +- status = "okay"; +- }; +- +- ssp0: spi@80010000 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_8bit_pins_a +- &mmc0_cd_cfg &mmc0_sck_cfg>; +- bus-width = <8>; +- wp-gpios = <&gpio2 12 0>; +- vmmc-supply = <®_vddio_sd0>; +- status = "okay"; +- }; +- +- ssp1: spi@80012000 { +- compatible = "fsl,imx28-mmc"; +- bus-width = <8>; +- wp-gpios = <&gpio0 28 0>; +- }; +- +- ssp2: spi@80014000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx28-spi"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pins_a>; +- status = "okay"; +- +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "sst,sst25vf016b", "jedec,spi-nor"; +- spi-max-frequency = <40000000>; +- reg = <0>; +- }; +- }; +- +- pinctrl@80018000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_a>; +- +- hog_pins_a: hog@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP1_CMD__GPIO_2_13 +- MX28_PAD_SSP1_DATA3__GPIO_2_15 +- MX28_PAD_ENET0_RX_CLK__GPIO_4_13 +- MX28_PAD_SSP1_SCK__GPIO_2_12 +- MX28_PAD_PWM3__GPIO_3_28 +- MX28_PAD_LCD_RESET__GPIO_3_30 +- MX28_PAD_AUART2_RX__GPIO_3_8 +- MX28_PAD_AUART2_TX__GPIO_3_9 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- led_pin_gpio3_5: led_gpio3_5@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART1_TX__GPIO_3_5 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- gpmi_pins_evk: gpmi-nand-evk@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_CE1N__GPMI_CE1N +- MX28_PAD_GPMI_RDY1__GPMI_READY1 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_pins_evk: lcdif-evk@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_RD_E__LCD_VSYNC +- MX28_PAD_LCD_WR_RWN__LCD_HSYNC +- MX28_PAD_LCD_RS__LCD_DOTCLK +- MX28_PAD_LCD_CS__LCD_ENABLE +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- }; +- +- lcdif@80030000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcdif_24bit_pins_a +- &lcdif_pins_evk>; +- status = "okay"; +- +- port { +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +- +- can0: can@80032000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&can0_pins_a>; +- xceiver-supply = <®_can_3v3>; +- status = "okay"; +- }; +- +- can1: can@80034000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&can1_pins_a>; +- xceiver-supply = <®_can_3v3>; +- status = "okay"; +- }; +- }; +- +- apbx@80040000 { +- saif0: saif@80042000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&saif0_pins_a>; +- status = "okay"; +- }; +- +- saif1: saif@80046000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&saif1_pins_a>; +- fsl,saif-master = <&saif0>; +- status = "okay"; +- }; +- +- lradc@80050000 { +- status = "okay"; +- fsl,lradc-touchscreen-wires = <4>; +- fsl,ave-ctrl = <4>; +- fsl,ave-delay = <2>; +- fsl,settling = <10>; +- }; +- +- i2c0: i2c@80058000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_a>; +- status = "okay"; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; +- clocks = <&saif0>; +- }; +- +- at24@51 { +- compatible = "atmel,24c32"; +- pagesize = <32>; +- reg = <0x51>; +- }; +- }; +- +- pwm: pwm@80064000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm2_pins_a>; +- status = "okay"; +- }; +- +- duart: serial@80074000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_pins_a>; +- status = "okay"; +- }; +- +- auart0: serial@8006a000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart0_pins_a>; +- uart-has-rtscts; +- status = "okay"; +- }; +- +- auart3: serial@80070000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart3_pins_a>; +- status = "okay"; +- }; +- +- usbphy0: usbphy@8007c000 { +- status = "okay"; +- }; +- +- usbphy1: usbphy@8007e000 { +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb0: usb@80080000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb0_id_pins_a>; +- vbus-supply = <®_usb0_vbus>; +- status = "okay"; +- }; +- +- usb1: usb@80090000 { +- vbus-supply = <®_usb1_vbus>; +- status = "okay"; +- }; +- +- mac0: ethernet@800f0000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_pins_a>; +- phy-supply = <®_fec_3v3>; +- phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <100>; +- status = "okay"; +- }; +- +- mac1: ethernet@800f4000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac1_pins_a>; +- status = "okay"; +- }; +- }; +- +- sound { +- compatible = "fsl,imx28-evk-sgtl5000", +- "fsl,mxs-audio-sgtl5000"; +- model = "imx28-evk-sgtl5000"; +- saif-controllers = <&saif0 &saif1>; +- audio-codec = <&sgtl5000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pin_gpio3_5>; +- +- user { +- label = "Heartbeat"; +- gpios = <&gpio3 5 0>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- backlight_display: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 2 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-lwe.dtsi b/scripts/dtc/include-prefixes/arm/imx28-lwe.dtsi +deleted file mode 100644 +index bb971e660db8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-lwe.dtsi ++++ /dev/null +@@ -1,170 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright 2021 +- * Lukasz Majewski, DENX Software Engineering, lukma@denx.de +- */ +- +-/dts-v1/; +-#include "imx28.dtsi" +- +-/ { +- aliases { +- spi2 = &ssp3; +- }; +- +- chosen { +- bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 ro rootwait console=ttyAMA0,115200 panic=1"; +- }; +- +- memory@40000000 { +- reg = <0x40000000 0x08000000>; +- }; +- +- reg_3v3: regulator-reg-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_usb_5v: regulator-reg-usb-5v { +- compatible = "regulator-fixed"; +- regulator-name = "usb_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_fec_3v3: regulator-reg-fec-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "fec-phy"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&duart { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_pins_a>; +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_a>; +- status = "okay"; +-}; +- +-&saif0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&saif0_pins_a>; +- #sound-dai-cells = <0>; +- assigned-clocks = <&clks 53>; +- assigned-clock-rates = <12000000>; +- status = "okay"; +-}; +- +-&saif1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&saif1_pins_a>; +- fsl,saif-master = <&saif0>; +- #sound-dai-cells = <0>; +- status = "okay"; +-}; +- +-&spi3_pins_a { +- fsl,pinmux-ids = < +- MX28_PAD_AUART2_RX__SSP3_D4 +- MX28_PAD_AUART2_TX__SSP3_D5 +- MX28_PAD_SSP3_SCK__SSP3_SCK +- MX28_PAD_SSP3_MOSI__SSP3_CMD +- MX28_PAD_SSP3_MISO__SSP3_D0 +- MX28_PAD_SSP3_SS0__SSP3_D3 +- MX28_PAD_AUART2_TX__GPIO_3_9 +- >; +-}; +- +-&ssp0 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_8bit_pins_a>; +- bus-width = <8>; +- vmmc-supply = <®_3v3>; +- non-removable; +- status = "okay"; +-}; +- +-&ssp2 { +- compatible = "fsl,imx28-spi"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pins_a>; +- status = "okay"; +-}; +- +-&ssp3 { +- compatible = "fsl,imx28-spi"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi3_pins_a>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <40000000>; +- reg = <0>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0 0x80000>; +- read-only; +- }; +- +- partition@80000 { +- label = "env0"; +- reg = <0x80000 0x10000>; +- }; +- +- partition@90000 { +- label = "env1"; +- reg = <0x90000 0x10000>; +- }; +- +- partition@100000 { +- label = "kernel"; +- reg = <0x100000 0x400000>; +- }; +- +- partition@500000 { +- label = "swupdate"; +- reg = <0x500000 0x800000>; +- }; +- }; +- }; +-}; +- +-&usb0 { +- vbus-supply = <®_usb_5v>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb0_pins_b>, <&usb0_id_pins_a>; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbphy0 { +- status = "okay"; +-}; +- +-&usb1 { +- vbus-supply = <®_usb_5v>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb1_pins_b>; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbphy1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-m28.dtsi b/scripts/dtc/include-prefixes/arm/imx28-m28.dtsi +deleted file mode 100644 +index 2bdb4c093545..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-m28.dtsi ++++ /dev/null +@@ -1,56 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2014 Marek Vasut +- */ +- +-#include "imx28.dtsi" +- +-/ { +- model = "Aries/DENX M28"; +- compatible = "aries,m28", "denx,m28", "fsl,imx28"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x08000000>; +- }; +- +- apb@80000000 { +- apbh@80000000 { +- nand-controller@8000c000 { +- #address-cells = <1>; +- #size-cells = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; +- status = "okay"; +- }; +- }; +- +- apbx@80040000 { +- i2c0: i2c@80058000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_a>; +- status = "okay"; +- +- rtc: rtc@68 { +- compatible = "st,m41t62"; +- reg = <0x68>; +- }; +- }; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_3p3v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-m28cu3.dts b/scripts/dtc/include-prefixes/arm/imx28-m28cu3.dts +deleted file mode 100644 +index 865ac3d573c7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-m28cu3.dts ++++ /dev/null +@@ -1,266 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2013 Marek Vasut +- */ +- +-/dts-v1/; +-#include "imx28.dtsi" +- +-/ { +- model = "MSR M28CU3"; +- compatible = "msr,m28cu3", "fsl,imx28"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x08000000>; +- }; +- +- apb@80000000 { +- apbh@80000000 { +- nand-controller@8000c000 { +- #address-cells = <1>; +- #size-cells = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; +- status = "okay"; +- +- partition@0 { +- label = "gpmi-nfc-0-boot"; +- reg = <0x00000000 0x01400000>; +- read-only; +- }; +- +- partition@1 { +- label = "gpmi-nfc-general-use"; +- reg = <0x01400000 0x0ec00000>; +- }; +- }; +- +- ssp0: spi@80010000 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_4bit_pins_a +- &mmc0_cd_cfg +- &mmc0_sck_cfg>; +- bus-width = <4>; +- vmmc-supply = <®_vddio_sd0>; +- status = "okay"; +- }; +- +- ssp2: spi@80014000 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_4bit_pins_a +- &mmc2_cd_cfg +- &mmc2_sck_cfg_a>; +- bus-width = <4>; +- vmmc-supply = <®_vddio_sd1>; +- status = "okay"; +- }; +- +- pinctrl@80018000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_a>; +- +- hog_pins_a: hog@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP2_SS0__GPIO_2_19 +- MX28_PAD_PWM4__GPIO_3_29 +- MX28_PAD_AUART2_RX__GPIO_3_8 +- MX28_PAD_ENET0_RX_CLK__GPIO_4_13 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_pins_m28: lcdif-m28@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_VSYNC__LCD_VSYNC +- MX28_PAD_LCD_HSYNC__LCD_HSYNC +- MX28_PAD_LCD_DOTCLK__LCD_DOTCLK +- MX28_PAD_LCD_RESET__LCD_RESET +- MX28_PAD_LCD_CS__LCD_ENABLE +- MX28_PAD_AUART1_TX__GPIO_3_5 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- led_pins_gpio: leds-m28@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP3_MISO__GPIO_2_26 +- MX28_PAD_SSP3_SCK__GPIO_2_24 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- }; +- +- ocotp@8002c000 { +- status = "okay"; +- }; +- +- lcdif@80030000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcdif_24bit_pins_a +- &lcdif_pins_m28>; +- display = <&display0>; +- status = "okay"; +- +- display0: display0 { +- bits-per-pixel = <32>; +- bus-width = <24>; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing0 { +- clock-frequency = <6410256>; +- hactive = <320>; +- vactive = <240>; +- hback-porch = <38>; +- hfront-porch = <20>; +- vback-porch = <15>; +- vfront-porch = <5>; +- hsync-len = <30>; +- vsync-len = <3>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- }; +- }; +- }; +- +- apbx@80040000 { +- duart: serial@80074000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_pins_b>; +- status = "okay"; +- }; +- +- usbphy1: usbphy@8007e000 { +- status = "okay"; +- }; +- +- auart0: serial@8006a000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart0_2pins_a>; +- status = "okay"; +- }; +- +- auart3: serial@80070000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart3_2pins_b>; +- status = "okay"; +- }; +- +- pwm: pwm@80064000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm3_pins_a>; +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb1: usb@80090000 { +- vbus-supply = <®_usb1_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb1_pins_a>; +- disable-over-current; +- status = "okay"; +- }; +- +- mac0: ethernet@800f0000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_pins_a>; +- phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <100>; +- status = "okay"; +- }; +- +- mac1: ethernet@800f4000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac1_pins_a>; +- status = "okay"; +- }; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 3 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins_gpio>; +- +- user1 { +- label = "sd0-led"; +- gpios = <&gpio2 26 0>; +- linux,default-trigger = "mmc0"; +- }; +- +- user2 { +- label = "sd1-led"; +- gpios = <&gpio2 24 0>; +- linux,default-trigger = "mmc2"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_3p3v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_vddio_sd0: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "vddio-sd0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 29 0>; +- }; +- +- reg_vddio_sd1: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "vddio-sd1"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 19 0>; +- }; +- +- reg_usb1_vbus: regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- regulator-name = "usb1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 8 0>; +- enable-active-high; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-m28evk.dts b/scripts/dtc/include-prefixes/arm/imx28-m28evk.dts +deleted file mode 100644 +index f3bddc5ada4b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-m28evk.dts ++++ /dev/null +@@ -1,271 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- +- * Copyright (C) 2012 Marek Vasut +- */ +- +-/dts-v1/; +-#include "imx28-m28.dtsi" +- +-/ { +- model = "Aries/DENX M28EVK"; +- compatible = "aries,m28evk", "denx,m28evk", "fsl,imx28"; +- +- apb@80000000 { +- apbh@80000000 { +- ssp0: spi@80010000 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_8bit_pins_a +- &mmc0_cd_cfg +- &mmc0_sck_cfg>; +- bus-width = <8>; +- wp-gpios = <&gpio3 10 0>; +- vmmc-supply = <®_vddio_sd0>; +- status = "okay"; +- }; +- +- ssp2: spi@80014000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx28-spi"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pins_a>; +- status = "okay"; +- +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p80", "jedec,spi-nor"; +- spi-max-frequency = <40000000>; +- reg = <0>; +- }; +- }; +- +- pinctrl@80018000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_a>; +- +- hog_pins_a: hog@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_PWM3__GPIO_3_28 +- MX28_PAD_AUART2_CTS__GPIO_3_10 +- MX28_PAD_AUART2_RTS__GPIO_3_11 +- MX28_PAD_AUART3_RX__GPIO_3_12 +- MX28_PAD_AUART3_TX__GPIO_3_13 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_pins_m28: lcdif-m28@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_DOTCLK__LCD_DOTCLK +- MX28_PAD_LCD_ENABLE__LCD_ENABLE +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- }; +- +- lcdif@80030000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcdif_24bit_pins_a +- &lcdif_pins_m28>; +- display = <&display0>; +- status = "okay"; +- +- display0: display0 { +- bits-per-pixel = <16>; +- bus-width = <18>; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing0 { +- clock-frequency = <33260000>; +- hactive = <800>; +- vactive = <480>; +- hback-porch = <0>; +- hfront-porch = <256>; +- vback-porch = <0>; +- vfront-porch = <45>; +- hsync-len = <1>; +- vsync-len = <1>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- }; +- }; +- +- can0: can@80032000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&can0_pins_a>; +- status = "okay"; +- }; +- +- can1: can@80034000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&can1_pins_a>; +- status = "okay"; +- }; +- }; +- +- apbx@80040000 { +- saif0: saif@80042000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&saif0_pins_a>; +- status = "okay"; +- }; +- +- saif1: saif@80046000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&saif1_pins_a>; +- fsl,saif-master = <&saif0>; +- status = "okay"; +- }; +- +- i2c0: i2c@80058000 { +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; +- clocks = <&saif0>; +- }; +- +- eeprom: eeprom@51 { +- compatible = "atmel,24c128"; +- reg = <0x51>; +- pagesize = <32>; +- }; +- }; +- +- lradc@80050000 { +- status = "okay"; +- fsl,lradc-touchscreen-wires = <4>; +- }; +- +- duart: serial@80074000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_pins_a>; +- status = "okay"; +- }; +- +- usbphy0: usbphy@8007c000 { +- status = "okay"; +- }; +- +- usbphy1: usbphy@8007e000 { +- status = "okay"; +- }; +- +- auart0: serial@8006a000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart0_pins_a>; +- status = "okay"; +- }; +- +- auart1: serial@8006c000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart1_pins_a>; +- status = "okay"; +- }; +- +- auart2: serial@8006e000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart2_2pins_b>; +- status = "okay"; +- }; +- +- pwm: pwm@80064000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm4_pins_a>; +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb0: usb@80080000 { +- vbus-supply = <®_usb0_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb0_pins_a>; +- status = "okay"; +- }; +- +- usb1: usb@80090000 { +- vbus-supply = <®_usb1_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb1_pins_a>; +- status = "okay"; +- }; +- +- mac0: ethernet@800f0000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_pins_a>; +- clocks = <&clks 57>, <&clks 57>; +- clock-names = "ipg", "ahb"; +- status = "okay"; +- }; +- +- mac1: ethernet@800f4000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac1_pins_a>; +- status = "okay"; +- }; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 4 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +- +- regulators { +- reg_vddio_sd0: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "vddio-sd0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 28 0>; +- }; +- +- reg_usb0_vbus: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "usb0_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 12 0>; +- }; +- +- reg_usb1_vbus: regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- regulator-name = "usb1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 13 0>; +- }; +- }; +- +- sound { +- compatible = "denx,m28evk-sgtl5000", +- "fsl,mxs-audio-sgtl5000"; +- model = "m28evk-sgtl5000"; +- saif-controllers = <&saif0 &saif1>; +- audio-codec = <&sgtl5000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-pinfunc.h b/scripts/dtc/include-prefixes/arm/imx28-pinfunc.h +deleted file mode 100644 +index e11f69ba0fe4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-pinfunc.h ++++ /dev/null +@@ -1,506 +0,0 @@ +-/* +- * Header providing constants for i.MX28 pinctrl bindings. +- * +- * Copyright (C) 2013 Lothar Waßmann +- * +- * The code contained herein is licensed under the GNU General Public +- * License. You may obtain a copy of the GNU General Public License +- * Version 2 at the following locations: +- * +- * http://www.opensource.org/licenses/gpl-license.html +- * http://www.gnu.org/copyleft/gpl.html +- */ +- +-#ifndef __DT_BINDINGS_MX28_PINCTRL_H__ +-#define __DT_BINDINGS_MX28_PINCTRL_H__ +- +-#include "mxs-pinfunc.h" +- +-#define MX28_PAD_GPMI_D00__GPMI_D0 0x0000 +-#define MX28_PAD_GPMI_D01__GPMI_D1 0x0010 +-#define MX28_PAD_GPMI_D02__GPMI_D2 0x0020 +-#define MX28_PAD_GPMI_D03__GPMI_D3 0x0030 +-#define MX28_PAD_GPMI_D04__GPMI_D4 0x0040 +-#define MX28_PAD_GPMI_D05__GPMI_D5 0x0050 +-#define MX28_PAD_GPMI_D06__GPMI_D6 0x0060 +-#define MX28_PAD_GPMI_D07__GPMI_D7 0x0070 +-#define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100 +-#define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110 +-#define MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 +-#define MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130 +-#define MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140 +-#define MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150 +-#define MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160 +-#define MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170 +-#define MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180 +-#define MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190 +-#define MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0 +-#define MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0 +-#define MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0 +-#define MX28_PAD_LCD_D00__LCD_D0 0x1000 +-#define MX28_PAD_LCD_D01__LCD_D1 0x1010 +-#define MX28_PAD_LCD_D02__LCD_D2 0x1020 +-#define MX28_PAD_LCD_D03__LCD_D3 0x1030 +-#define MX28_PAD_LCD_D04__LCD_D4 0x1040 +-#define MX28_PAD_LCD_D05__LCD_D5 0x1050 +-#define MX28_PAD_LCD_D06__LCD_D6 0x1060 +-#define MX28_PAD_LCD_D07__LCD_D7 0x1070 +-#define MX28_PAD_LCD_D08__LCD_D8 0x1080 +-#define MX28_PAD_LCD_D09__LCD_D9 0x1090 +-#define MX28_PAD_LCD_D10__LCD_D10 0x10a0 +-#define MX28_PAD_LCD_D11__LCD_D11 0x10b0 +-#define MX28_PAD_LCD_D12__LCD_D12 0x10c0 +-#define MX28_PAD_LCD_D13__LCD_D13 0x10d0 +-#define MX28_PAD_LCD_D14__LCD_D14 0x10e0 +-#define MX28_PAD_LCD_D15__LCD_D15 0x10f0 +-#define MX28_PAD_LCD_D16__LCD_D16 0x1100 +-#define MX28_PAD_LCD_D17__LCD_D17 0x1110 +-#define MX28_PAD_LCD_D18__LCD_D18 0x1120 +-#define MX28_PAD_LCD_D19__LCD_D19 0x1130 +-#define MX28_PAD_LCD_D20__LCD_D20 0x1140 +-#define MX28_PAD_LCD_D21__LCD_D21 0x1150 +-#define MX28_PAD_LCD_D22__LCD_D22 0x1160 +-#define MX28_PAD_LCD_D23__LCD_D23 0x1170 +-#define MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180 +-#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190 +-#define MX28_PAD_LCD_RS__LCD_RS 0x11a0 +-#define MX28_PAD_LCD_CS__LCD_CS 0x11b0 +-#define MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0 +-#define MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0 +-#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0 +-#define MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0 +-#define MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000 +-#define MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010 +-#define MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020 +-#define MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030 +-#define MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040 +-#define MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050 +-#define MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060 +-#define MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070 +-#define MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080 +-#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090 +-#define MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0 +-#define MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0 +-#define MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0 +-#define MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0 +-#define MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0 +-#define MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100 +-#define MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110 +-#define MX28_PAD_SSP2_MISO__SSP2_D0 0x2120 +-#define MX28_PAD_SSP2_SS0__SSP2_D3 0x2130 +-#define MX28_PAD_SSP2_SS1__SSP2_D4 0x2140 +-#define MX28_PAD_SSP2_SS2__SSP2_D5 0x2150 +-#define MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180 +-#define MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190 +-#define MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0 +-#define MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0 +-#define MX28_PAD_AUART0_RX__AUART0_RX 0x3000 +-#define MX28_PAD_AUART0_TX__AUART0_TX 0x3010 +-#define MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020 +-#define MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030 +-#define MX28_PAD_AUART1_RX__AUART1_RX 0x3040 +-#define MX28_PAD_AUART1_TX__AUART1_TX 0x3050 +-#define MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060 +-#define MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070 +-#define MX28_PAD_AUART2_RX__AUART2_RX 0x3080 +-#define MX28_PAD_AUART2_TX__AUART2_TX 0x3090 +-#define MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0 +-#define MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0 +-#define MX28_PAD_AUART3_RX__AUART3_RX 0x30c0 +-#define MX28_PAD_AUART3_TX__AUART3_TX 0x30d0 +-#define MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0 +-#define MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0 +-#define MX28_PAD_PWM0__PWM_0 0x3100 +-#define MX28_PAD_PWM1__PWM_1 0x3110 +-#define MX28_PAD_PWM2__PWM_2 0x3120 +-#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140 +-#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150 +-#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160 +-#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170 +-#define MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180 +-#define MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190 +-#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0 +-#define MX28_PAD_SPDIF__SPDIF_TX 0x31b0 +-#define MX28_PAD_PWM3__PWM_3 0x31c0 +-#define MX28_PAD_PWM4__PWM_4 0x31d0 +-#define MX28_PAD_LCD_RESET__LCD_RESET 0x31e0 +-#define MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000 +-#define MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010 +-#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020 +-#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030 +-#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040 +-#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050 +-#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060 +-#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070 +-#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080 +-#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090 +-#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0 +-#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0 +-#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0 +-#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0 +-#define MX28_PAD_ENET0_COL__ENET0_COL 0x40e0 +-#define MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0 +-#define MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100 +-#define MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140 +-#define MX28_PAD_EMI_D00__EMI_DATA0 0x5000 +-#define MX28_PAD_EMI_D01__EMI_DATA1 0x5010 +-#define MX28_PAD_EMI_D02__EMI_DATA2 0x5020 +-#define MX28_PAD_EMI_D03__EMI_DATA3 0x5030 +-#define MX28_PAD_EMI_D04__EMI_DATA4 0x5040 +-#define MX28_PAD_EMI_D05__EMI_DATA5 0x5050 +-#define MX28_PAD_EMI_D06__EMI_DATA6 0x5060 +-#define MX28_PAD_EMI_D07__EMI_DATA7 0x5070 +-#define MX28_PAD_EMI_D08__EMI_DATA8 0x5080 +-#define MX28_PAD_EMI_D09__EMI_DATA9 0x5090 +-#define MX28_PAD_EMI_D10__EMI_DATA10 0x50a0 +-#define MX28_PAD_EMI_D11__EMI_DATA11 0x50b0 +-#define MX28_PAD_EMI_D12__EMI_DATA12 0x50c0 +-#define MX28_PAD_EMI_D13__EMI_DATA13 0x50d0 +-#define MX28_PAD_EMI_D14__EMI_DATA14 0x50e0 +-#define MX28_PAD_EMI_D15__EMI_DATA15 0x50f0 +-#define MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100 +-#define MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110 +-#define MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120 +-#define MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130 +-#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140 +-#define MX28_PAD_EMI_CLK__EMI_CLK 0x5150 +-#define MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160 +-#define MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170 +-#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0 +-#define MX28_PAD_EMI_A00__EMI_ADDR0 0x6000 +-#define MX28_PAD_EMI_A01__EMI_ADDR1 0x6010 +-#define MX28_PAD_EMI_A02__EMI_ADDR2 0x6020 +-#define MX28_PAD_EMI_A03__EMI_ADDR3 0x6030 +-#define MX28_PAD_EMI_A04__EMI_ADDR4 0x6040 +-#define MX28_PAD_EMI_A05__EMI_ADDR5 0x6050 +-#define MX28_PAD_EMI_A06__EMI_ADDR6 0x6060 +-#define MX28_PAD_EMI_A07__EMI_ADDR7 0x6070 +-#define MX28_PAD_EMI_A08__EMI_ADDR8 0x6080 +-#define MX28_PAD_EMI_A09__EMI_ADDR9 0x6090 +-#define MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0 +-#define MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0 +-#define MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0 +-#define MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0 +-#define MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0 +-#define MX28_PAD_EMI_BA0__EMI_BA0 0x6100 +-#define MX28_PAD_EMI_BA1__EMI_BA1 0x6110 +-#define MX28_PAD_EMI_BA2__EMI_BA2 0x6120 +-#define MX28_PAD_EMI_CASN__EMI_CASN 0x6130 +-#define MX28_PAD_EMI_RASN__EMI_RASN 0x6140 +-#define MX28_PAD_EMI_WEN__EMI_WEN 0x6150 +-#define MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160 +-#define MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170 +-#define MX28_PAD_EMI_CKE__EMI_CKE 0x6180 +-#define MX28_PAD_GPMI_D00__SSP1_D0 0x0001 +-#define MX28_PAD_GPMI_D01__SSP1_D1 0x0011 +-#define MX28_PAD_GPMI_D02__SSP1_D2 0x0021 +-#define MX28_PAD_GPMI_D03__SSP1_D3 0x0031 +-#define MX28_PAD_GPMI_D04__SSP1_D4 0x0041 +-#define MX28_PAD_GPMI_D05__SSP1_D5 0x0051 +-#define MX28_PAD_GPMI_D06__SSP1_D6 0x0061 +-#define MX28_PAD_GPMI_D07__SSP1_D7 0x0071 +-#define MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101 +-#define MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111 +-#define MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121 +-#define MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131 +-#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141 +-#define MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151 +-#define MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161 +-#define MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171 +-#define MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181 +-#define MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191 +-#define MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1 +-#define MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1 +-#define MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1 +-#define MX28_PAD_LCD_D03__ETM_DA8 0x1031 +-#define MX28_PAD_LCD_D04__ETM_DA9 0x1041 +-#define MX28_PAD_LCD_D08__ETM_DA3 0x1081 +-#define MX28_PAD_LCD_D09__ETM_DA4 0x1091 +-#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141 +-#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151 +-#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161 +-#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171 +-#define MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181 +-#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191 +-#define MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1 +-#define MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1 +-#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1 +-#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1 +-#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1 +-#define MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041 +-#define MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051 +-#define MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061 +-#define MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071 +-#define MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1 +-#define MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1 +-#define MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1 +-#define MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1 +-#define MX28_PAD_SSP2_SCK__AUART2_RX 0x2101 +-#define MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111 +-#define MX28_PAD_SSP2_MISO__AUART3_RX 0x2121 +-#define MX28_PAD_SSP2_SS0__AUART3_TX 0x2131 +-#define MX28_PAD_SSP2_SS1__SSP2_D1 0x2141 +-#define MX28_PAD_SSP2_SS2__SSP2_D2 0x2151 +-#define MX28_PAD_SSP3_SCK__AUART4_TX 0x2181 +-#define MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191 +-#define MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1 +-#define MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1 +-#define MX28_PAD_AUART0_RX__I2C0_SCL 0x3001 +-#define MX28_PAD_AUART0_TX__I2C0_SDA 0x3011 +-#define MX28_PAD_AUART0_CTS__AUART4_RX 0x3021 +-#define MX28_PAD_AUART0_RTS__AUART4_TX 0x3031 +-#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041 +-#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051 +-#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061 +-#define MX28_PAD_AUART1_RTS__USB0_ID 0x3071 +-#define MX28_PAD_AUART2_RX__SSP3_D1 0x3081 +-#define MX28_PAD_AUART2_TX__SSP3_D2 0x3091 +-#define MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1 +-#define MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1 +-#define MX28_PAD_AUART3_RX__CAN0_TX 0x30c1 +-#define MX28_PAD_AUART3_TX__CAN0_RX 0x30d1 +-#define MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1 +-#define MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1 +-#define MX28_PAD_PWM0__I2C1_SCL 0x3101 +-#define MX28_PAD_PWM1__I2C1_SDA 0x3111 +-#define MX28_PAD_PWM2__USB0_ID 0x3121 +-#define MX28_PAD_SAIF0_MCLK__PWM_3 0x3141 +-#define MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151 +-#define MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161 +-#define MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171 +-#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181 +-#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191 +-#define MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1 +-#define MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1 +-#define MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001 +-#define MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011 +-#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021 +-#define MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031 +-#define MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041 +-#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051 +-#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061 +-#define MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071 +-#define MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081 +-#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091 +-#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1 +-#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1 +-#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1 +-#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1 +-#define MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1 +-#define MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1 +-#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122 +-#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132 +-#define MX28_PAD_GPMI_RDY0__USB0_ID 0x0142 +-#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162 +-#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172 +-#define MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2 +-#define MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2 +-#define MX28_PAD_LCD_D00__ETM_DA0 0x1002 +-#define MX28_PAD_LCD_D01__ETM_DA1 0x1012 +-#define MX28_PAD_LCD_D02__ETM_DA2 0x1022 +-#define MX28_PAD_LCD_D03__ETM_DA3 0x1032 +-#define MX28_PAD_LCD_D04__ETM_DA4 0x1042 +-#define MX28_PAD_LCD_D05__ETM_DA5 0x1052 +-#define MX28_PAD_LCD_D06__ETM_DA6 0x1062 +-#define MX28_PAD_LCD_D07__ETM_DA7 0x1072 +-#define MX28_PAD_LCD_D08__ETM_DA8 0x1082 +-#define MX28_PAD_LCD_D09__ETM_DA9 0x1092 +-#define MX28_PAD_LCD_D10__ETM_DA10 0x10a2 +-#define MX28_PAD_LCD_D11__ETM_DA11 0x10b2 +-#define MX28_PAD_LCD_D12__ETM_DA12 0x10c2 +-#define MX28_PAD_LCD_D13__ETM_DA13 0x10d2 +-#define MX28_PAD_LCD_D14__ETM_DA14 0x10e2 +-#define MX28_PAD_LCD_D15__ETM_DA15 0x10f2 +-#define MX28_PAD_LCD_D16__ETM_DA7 0x1102 +-#define MX28_PAD_LCD_D17__ETM_DA6 0x1112 +-#define MX28_PAD_LCD_D18__ETM_DA5 0x1122 +-#define MX28_PAD_LCD_D19__ETM_DA4 0x1132 +-#define MX28_PAD_LCD_D20__ETM_DA3 0x1142 +-#define MX28_PAD_LCD_D21__ETM_DA2 0x1152 +-#define MX28_PAD_LCD_D22__ETM_DA1 0x1162 +-#define MX28_PAD_LCD_D23__ETM_DA0 0x1172 +-#define MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182 +-#define MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192 +-#define MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2 +-#define MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2 +-#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2 +-#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2 +-#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2 +-#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2 +-#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102 +-#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112 +-#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122 +-#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132 +-#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142 +-#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152 +-#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182 +-#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192 +-#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2 +-#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2 +-#define MX28_PAD_AUART0_RX__DUART_CTS 0x3002 +-#define MX28_PAD_AUART0_TX__DUART_RTS 0x3012 +-#define MX28_PAD_AUART0_CTS__DUART_RX 0x3022 +-#define MX28_PAD_AUART0_RTS__DUART_TX 0x3032 +-#define MX28_PAD_AUART1_RX__PWM_0 0x3042 +-#define MX28_PAD_AUART1_TX__PWM_1 0x3052 +-#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062 +-#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072 +-#define MX28_PAD_AUART2_RX__SSP3_D4 0x3082 +-#define MX28_PAD_AUART2_TX__SSP3_D5 0x3092 +-#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2 +-#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2 +-#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2 +-#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2 +-#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2 +-#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2 +-#define MX28_PAD_PWM0__DUART_RX 0x3102 +-#define MX28_PAD_PWM1__DUART_TX 0x3112 +-#define MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122 +-#define MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142 +-#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152 +-#define MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162 +-#define MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172 +-#define MX28_PAD_I2C0_SCL__DUART_RX 0x3182 +-#define MX28_PAD_I2C0_SDA__DUART_TX 0x3192 +-#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2 +-#define MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2 +-#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002 +-#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012 +-#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022 +-#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032 +-#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052 +-#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092 +-#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2 +-#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2 +-#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2 +-#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2 +-#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2 +-#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2 +-#define MX28_PAD_GPMI_D00__GPIO_0_0 0x0003 +-#define MX28_PAD_GPMI_D01__GPIO_0_1 0x0013 +-#define MX28_PAD_GPMI_D02__GPIO_0_2 0x0023 +-#define MX28_PAD_GPMI_D03__GPIO_0_3 0x0033 +-#define MX28_PAD_GPMI_D04__GPIO_0_4 0x0043 +-#define MX28_PAD_GPMI_D05__GPIO_0_5 0x0053 +-#define MX28_PAD_GPMI_D06__GPIO_0_6 0x0063 +-#define MX28_PAD_GPMI_D07__GPIO_0_7 0x0073 +-#define MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103 +-#define MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113 +-#define MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123 +-#define MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133 +-#define MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143 +-#define MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153 +-#define MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163 +-#define MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173 +-#define MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183 +-#define MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193 +-#define MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3 +-#define MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3 +-#define MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3 +-#define MX28_PAD_LCD_D00__GPIO_1_0 0x1003 +-#define MX28_PAD_LCD_D01__GPIO_1_1 0x1013 +-#define MX28_PAD_LCD_D02__GPIO_1_2 0x1023 +-#define MX28_PAD_LCD_D03__GPIO_1_3 0x1033 +-#define MX28_PAD_LCD_D04__GPIO_1_4 0x1043 +-#define MX28_PAD_LCD_D05__GPIO_1_5 0x1053 +-#define MX28_PAD_LCD_D06__GPIO_1_6 0x1063 +-#define MX28_PAD_LCD_D07__GPIO_1_7 0x1073 +-#define MX28_PAD_LCD_D08__GPIO_1_8 0x1083 +-#define MX28_PAD_LCD_D09__GPIO_1_9 0x1093 +-#define MX28_PAD_LCD_D10__GPIO_1_10 0x10a3 +-#define MX28_PAD_LCD_D11__GPIO_1_11 0x10b3 +-#define MX28_PAD_LCD_D12__GPIO_1_12 0x10c3 +-#define MX28_PAD_LCD_D13__GPIO_1_13 0x10d3 +-#define MX28_PAD_LCD_D14__GPIO_1_14 0x10e3 +-#define MX28_PAD_LCD_D15__GPIO_1_15 0x10f3 +-#define MX28_PAD_LCD_D16__GPIO_1_16 0x1103 +-#define MX28_PAD_LCD_D17__GPIO_1_17 0x1113 +-#define MX28_PAD_LCD_D18__GPIO_1_18 0x1123 +-#define MX28_PAD_LCD_D19__GPIO_1_19 0x1133 +-#define MX28_PAD_LCD_D20__GPIO_1_20 0x1143 +-#define MX28_PAD_LCD_D21__GPIO_1_21 0x1153 +-#define MX28_PAD_LCD_D22__GPIO_1_22 0x1163 +-#define MX28_PAD_LCD_D23__GPIO_1_23 0x1173 +-#define MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183 +-#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193 +-#define MX28_PAD_LCD_RS__GPIO_1_26 0x11a3 +-#define MX28_PAD_LCD_CS__GPIO_1_27 0x11b3 +-#define MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3 +-#define MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3 +-#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3 +-#define MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3 +-#define MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003 +-#define MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013 +-#define MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023 +-#define MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033 +-#define MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043 +-#define MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053 +-#define MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063 +-#define MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073 +-#define MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083 +-#define MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093 +-#define MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3 +-#define MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3 +-#define MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3 +-#define MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3 +-#define MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3 +-#define MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103 +-#define MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113 +-#define MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123 +-#define MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133 +-#define MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143 +-#define MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153 +-#define MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183 +-#define MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193 +-#define MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3 +-#define MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3 +-#define MX28_PAD_AUART0_RX__GPIO_3_0 0x3003 +-#define MX28_PAD_AUART0_TX__GPIO_3_1 0x3013 +-#define MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023 +-#define MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033 +-#define MX28_PAD_AUART1_RX__GPIO_3_4 0x3043 +-#define MX28_PAD_AUART1_TX__GPIO_3_5 0x3053 +-#define MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063 +-#define MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073 +-#define MX28_PAD_AUART2_RX__GPIO_3_8 0x3083 +-#define MX28_PAD_AUART2_TX__GPIO_3_9 0x3093 +-#define MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3 +-#define MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3 +-#define MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3 +-#define MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3 +-#define MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3 +-#define MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3 +-#define MX28_PAD_PWM0__GPIO_3_16 0x3103 +-#define MX28_PAD_PWM1__GPIO_3_17 0x3113 +-#define MX28_PAD_PWM2__GPIO_3_18 0x3123 +-#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143 +-#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153 +-#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163 +-#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173 +-#define MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183 +-#define MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193 +-#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3 +-#define MX28_PAD_SPDIF__GPIO_3_27 0x31b3 +-#define MX28_PAD_PWM3__GPIO_3_28 0x31c3 +-#define MX28_PAD_PWM4__GPIO_3_29 0x31d3 +-#define MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3 +-#define MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003 +-#define MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013 +-#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023 +-#define MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033 +-#define MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043 +-#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053 +-#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063 +-#define MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073 +-#define MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083 +-#define MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093 +-#define MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3 +-#define MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3 +-#define MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3 +-#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3 +-#define MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3 +-#define MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3 +-#define MX28_PAD_ENET_CLK__GPIO_4_16 0x4103 +-#define MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143 +- +-#endif /* __DT_BINDINGS_MX28_PINCTRL_H__ */ +diff --git a/scripts/dtc/include-prefixes/arm/imx28-sps1.dts b/scripts/dtc/include-prefixes/arm/imx28-sps1.dts +deleted file mode 100644 +index 43be7a6a769b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-sps1.dts ++++ /dev/null +@@ -1,166 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2012 Marek Vasut +- */ +- +-/dts-v1/; +-#include "imx28.dtsi" +- +-/ { +- model = "SchulerControl GmbH, SC SPS 1"; +- compatible = "schulercontrol,imx28-sps1", "fsl,imx28"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x08000000>; +- }; +- +- apb@80000000 { +- apbh@80000000 { +- pinctrl@80018000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_a>; +- +- hog_pins_a: hog-gpios@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_D00__GPIO_0_0 +- MX28_PAD_GPMI_D03__GPIO_0_3 +- MX28_PAD_GPMI_D06__GPIO_0_6 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- }; +- +- ssp0: spi@80010000 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_4bit_pins_a>; +- bus-width = <4>; +- status = "okay"; +- }; +- +- ssp2: spi@80014000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx28-spi"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pins_a>; +- status = "okay"; +- +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "everspin,mr25h256", "mr25h256"; +- spi-max-frequency = <40000000>; +- reg = <0>; +- }; +- }; +- }; +- +- apbx@80040000 { +- i2c0: i2c@80058000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_a>; +- status = "okay"; +- +- rtc: rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- +- eeprom: eeprom@52 { +- compatible = "atmel,24c64"; +- reg = <0x52>; +- pagesize = <32>; +- }; +- }; +- +- duart: serial@80074000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_pins_a>; +- status = "okay"; +- }; +- +- usbphy0: usbphy@8007c000 { +- status = "okay"; +- }; +- +- auart0: serial@8006a000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart0_pins_a>; +- status = "okay"; +- }; +- }; +- }; +- +- ahb@80080000 { +- usb0: usb@80080000 { +- vbus-supply = <®_usb0_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb0_pins_b>; +- status = "okay"; +- }; +- +- mac0: ethernet@800f0000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac0_pins_a>; +- status = "okay"; +- }; +- +- mac1: ethernet@800f4000 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac1_pins_a>; +- status = "okay"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_usb0_vbus: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "usb0_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 9 0>; +- }; +- }; +- +- leds { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "gpio-leds"; +- status = "okay"; +- +- led@1 { +- label = "sps1-1:yellow:user"; +- gpios = <&gpio0 6 0>; +- linux,default-trigger = "heartbeat"; +- reg = <0>; +- }; +- +- led@2 { +- label = "sps1-2:red:user"; +- gpios = <&gpio0 3 0>; +- linux,default-trigger = "heartbeat"; +- reg = <1>; +- }; +- +- led@3 { +- label = "sps1-3:red:user"; +- gpios = <&gpio0 0 0>; +- default-trigger = "heartbeat"; +- reg = <2>; +- }; +- +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-ts4600.dts b/scripts/dtc/include-prefixes/arm/imx28-ts4600.dts +deleted file mode 100644 +index 097ec35c62d8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-ts4600.dts ++++ /dev/null +@@ -1,74 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2016 Savoir-Faire Linux +- * Author: Sebastien Bourdelin +- */ +- +-/dts-v1/; +-#include "imx28.dtsi" +-#include "dt-bindings/gpio/gpio.h" +- +-/ { +- +- model = "Technologic Systems i.MX28 TS-4600"; +- compatible = "technologic,imx28-ts4600", "fsl,imx28"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x10000000>; /* 256MB */ +- }; +- +- apb@80000000 { +- apbh@80000000 { +- ssp0: spi@80010000 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_4bit_pins_a +- &mmc0_sck_cfg +- &en_sd_pwr>; +- broken-cd = <1>; +- bus-width = <4>; +- vmmc-supply = <®_vddio_sd0>; +- status = "okay"; +- }; +- +- pinctrl@80018000 { +- +- en_sd_pwr: en-sd-pwr@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_PWM3__GPIO_3_28 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- }; +- }; +- +- apbx@80040000 { +- pwm: pwm@80064000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm2_pins_a>; +- status = "okay"; +- }; +- +- duart: serial@80074000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_pins_a>; +- status = "okay"; +- }; +- }; +- }; +- +- reg_vddio_sd0: regulator-vddio-sd0 { +- compatible = "regulator-fixed"; +- regulator-name = "vddio-sd0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- gpio = <&gpio3 28 GPIO_ACTIVE_LOW>; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-tx28.dts b/scripts/dtc/include-prefixes/arm/imx28-tx28.dts +deleted file mode 100644 +index 164254c28f8e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-tx28.dts ++++ /dev/null +@@ -1,749 +0,0 @@ +-/* +- * Copyright 2012 Shawn Guo +- * Copyright 2013-2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx28.dtsi" +-#include +-#include +- +-/ { +- model = "Ka-Ro electronics TX28 module"; +- compatible = "karo,tx28", "fsl,imx28"; +- +- aliases { +- can0 = &can0; +- can1 = &can1; +- display = &display0; +- ds1339 = &ds1339; +- gpio5 = &gpio5; +- lcdif = &lcdif; +- lcdif_23bit_pins = &tx28_lcdif_23bit_pins; +- lcdif_24bit_pins = &lcdif_24bit_pins_a; +- reg_can_xcvr = ®_can_xcvr; +- spi_gpio = &spi_gpio; +- spi_mxs = &ssp3; +- stk5led = &user_led; +- usbotg = &usb0; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0>; /* will be filled in by U-Boot */ +- }; +- +- onewire { +- compatible = "w1-gpio"; +- gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; +- status = "disabled"; +- }; +- +- reg_usb0_vbus: regulator-usb0-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb0_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb1_vbus: regulator-usb1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_2p5v: regulator-2p5v { +- compatible = "regulator-fixed"; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_can_xcvr: regulator-can-xcvr { +- compatible = "regulator-fixed"; +- regulator-name = "CAN XCVR"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tx28_flexcan_xcvr_pins>; +- }; +- +- reg_lcd: regulator-lcd-power { +- compatible = "regulator-fixed"; +- regulator-name = "LCD POWER"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_lcd_reset: regulator-lcd-reset { +- compatible = "regulator-fixed"; +- regulator-name = "LCD RESET"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <300000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- mclk: clock-mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +- +- sound { +- compatible = "fsl,imx28-tx28-sgtl5000", +- "fsl,mxs-audio-sgtl5000"; +- model = "imx28-tx28-sgtl5000"; +- saif-controllers = <&saif0 &saif1>; +- audio-codec = <&sgtl5000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- user_led: user { +- label = "Heartbeat"; +- gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 500000>; +- /* +- * a silly way to create a 1:1 relationship between the +- * PWM value and the actual duty cycle +- */ +- brightness-levels = < 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100>; +- default-brightness-level = <50>; +- }; +- +- matrix_keypad: matrix-keypad { +- compatible = "gpio-matrix-keypad"; +- col-gpios = < +- &gpio5 0 GPIO_ACTIVE_HIGH +- &gpio5 1 GPIO_ACTIVE_HIGH +- &gpio5 2 GPIO_ACTIVE_HIGH +- &gpio5 3 GPIO_ACTIVE_HIGH +- >; +- row-gpios = < +- &gpio5 4 GPIO_ACTIVE_HIGH +- &gpio5 5 GPIO_ACTIVE_HIGH +- &gpio5 6 GPIO_ACTIVE_HIGH +- &gpio5 7 GPIO_ACTIVE_HIGH +- >; +- /* sample keymap */ +- linux,keymap = < +- 0x00000074 /* row 0, col 0, KEY_POWER */ +- 0x00010052 /* row 0, col 1, KEY_KP0 */ +- 0x0002004f /* row 0, col 2, KEY_KP1 */ +- 0x00030050 /* row 0, col 3, KEY_KP2 */ +- 0x01000051 /* row 1, col 0, KEY_KP3 */ +- 0x0101004b /* row 1, col 1, KEY_KP4 */ +- 0x0102004c /* row 1, col 2, KEY_KP5 */ +- 0x0103004d /* row 1, col 3, KEY_KP6 */ +- 0x02000047 /* row 2, col 0, KEY_KP7 */ +- 0x02010048 /* row 2, col 1, KEY_KP8 */ +- 0x02020049 /* row 2, col 2, KEY_KP9 */ +- >; +- gpio-activelow; +- wakeup-source; +- debounce-delay-ms = <100>; +- col-scan-delay-us = <5000>; +- linux,no-autorepeat; +- }; +- +- spi_gpio: spi-gpio { +- compatible = "spi-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tx28_spi_gpio_pins>; +- +- gpio-sck = <&gpio2 24 GPIO_ACTIVE_HIGH>; +- gpio-mosi = <&gpio2 25 GPIO_ACTIVE_HIGH>; +- gpio-miso = <&gpio2 26 GPIO_ACTIVE_HIGH>; +- num-chipselects = <3>; +- cs-gpios = < +- &gpio2 27 GPIO_ACTIVE_LOW +- &gpio3 8 GPIO_ACTIVE_LOW +- &gpio3 9 GPIO_ACTIVE_LOW +- >; +- /* enable this and disable ssp3 below, if you need full duplex SPI transfer */ +- status = "disabled"; +- +- spi@0 { +- compatible = "spidev"; +- reg = <0>; +- spi-max-frequency = <57600000>; +- }; +- +- spi@1 { +- compatible = "spidev"; +- reg = <1>; +- spi-max-frequency = <57600000>; +- }; +- +- spi@2 { +- compatible = "spidev"; +- reg = <2>; +- spi-max-frequency = <57600000>; +- }; +- }; +-}; +- +-/* 2nd TX-Std UART - (A)UART1 */ +-&auart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart1_pins_a>; +- status = "okay"; +-}; +- +-/* 3rd TX-Std UART - (A)UART3 */ +-&auart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&auart3_pins_a>; +- status = "okay"; +-}; +- +-&can0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&can0_pins_a>; +- xceiver-supply = <®_can_xcvr>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&can1_pins_a>; +- xceiver-supply = <®_can_xcvr>; +- status = "okay"; +-}; +- +-&digctl { +- status = "okay"; +-}; +- +-/* 1st TX-Std UART - (D)UART */ +-&duart { +- pinctrl-names = "default"; +- pinctrl-0 = <&duart_4pins_a>; +- status = "okay"; +-}; +- +-&gpmi { +- pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; +- nand-on-flash-bbt; +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_a>; +- clock-frequency = <400000>; +- status = "okay"; +- +- sgtl5000: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_3p3v>; +- clocks = <&mclk>; +- }; +- +- gpio5: pca953x@20 { +- compatible = "nxp,pca9554"; +- reg = <0x20>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tx28_pca9554_pins>; +- interrupt-parent = <&gpio3>; +- interrupts = <28 IRQ_TYPE_NONE>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- polytouch: edt-ft5x06@38 { +- compatible = "edt,edt-ft5x06"; +- reg = <0x38>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tx28_edt_ft5x06_pins>; +- interrupt-parent = <&gpio2>; +- interrupts = <5 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; +- wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; +- wakeup-source; +- }; +- +- touchscreen: tsc2007@48 { +- compatible = "ti,tsc2007"; +- reg = <0x48>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tx28_tsc2007_pins>; +- interrupt-parent = <&gpio3>; +- interrupts = <20 IRQ_TYPE_EDGE_FALLING>; +- pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; +- ti,x-plate-ohms = /bits/ 16 <660>; +- }; +- +- ds1339: rtc@68 { +- compatible = "mxim,ds1339"; +- reg = <0x68>; +- trickle-resistor-ohms = <250>; +- trickle-diode-disable; +- }; +-}; +- +-&lcdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &tx28_lcdif_ctrl_pins>; +- lcd-supply = <®_lcd>; +- display = <&display0>; +- status = "okay"; +- +- display0: display0 { +- bits-per-pixel = <32>; +- bus-width = <24>; +- display-timings { +- native-mode = <&timing5>; +- timing0: timing0 { +- panel-name = "VGA"; +- clock-frequency = <25175000>; +- hactive = <640>; +- vactive = <480>; +- hback-porch = <48>; +- hsync-len = <96>; +- hfront-porch = <16>; +- vback-porch = <33>; +- vsync-len = <2>; +- vfront-porch = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- +- timing1: timing1 { +- panel-name = "ETV570"; +- clock-frequency = <25175000>; +- hactive = <640>; +- vactive = <480>; +- hback-porch = <114>; +- hsync-len = <30>; +- hfront-porch = <16>; +- vback-porch = <32>; +- vsync-len = <3>; +- vfront-porch = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- +- timing2: timing2 { +- panel-name = "ET0350"; +- clock-frequency = <6500000>; +- hactive = <320>; +- vactive = <240>; +- hback-porch = <34>; +- hsync-len = <34>; +- hfront-porch = <20>; +- vback-porch = <15>; +- vsync-len = <3>; +- vfront-porch = <4>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- +- timing3: timing3 { +- panel-name = "ET0430"; +- clock-frequency = <9000000>; +- hactive = <480>; +- vactive = <272>; +- hback-porch = <2>; +- hsync-len = <41>; +- hfront-porch = <2>; +- vback-porch = <2>; +- vsync-len = <10>; +- vfront-porch = <2>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- +- timing4: timing4 { +- panel-name = "ET0500", "ET0700"; +- clock-frequency = <33260000>; +- hactive = <800>; +- vactive = <480>; +- hback-porch = <88>; +- hsync-len = <128>; +- hfront-porch = <40>; +- vback-porch = <33>; +- vsync-len = <2>; +- vfront-porch = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- +- timing5: timing5 { +- panel-name = "ETQ570"; +- clock-frequency = <6400000>; +- hactive = <320>; +- vactive = <240>; +- hback-porch = <38>; +- hsync-len = <30>; +- hfront-porch = <30>; +- vback-porch = <16>; +- vsync-len = <3>; +- vfront-porch = <4>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- }; +-}; +- +-&lradc { +- fsl,lradc-touchscreen-wires = <4>; +- status = "okay"; +-}; +- +-&mac0 { +- phy-mode = "rmii"; +- pinctrl-names = "default", "gpio_mode"; +- pinctrl-0 = <&mac0_pins_a>; +- pinctrl-1 = <&tx28_mac0_pins_gpio>; +- status = "okay"; +-}; +- +-&mac1 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mac1_pins_a>; +- /* not enabled by default */ +-}; +- +-&mxs_rtc { +- status = "okay"; +-}; +- +-&ocotp { +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pins_a>; +- status = "okay"; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_a>; +- +- hog_pins_a: hog@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_ENET0_RXD3__GPIO_4_10 /* module LED */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP0_DATA6__GPIO_2_6 /* RESET */ +- MX28_PAD_SSP0_DATA5__GPIO_2_5 /* IRQ */ +- MX28_PAD_ENET0_RXD2__GPIO_4_9 /* WAKE */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D00__GPIO_1_0 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- tx28_lcdif_23bit_pins: tx28-lcdif-23bit@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- /* LCD_D00 may be used as Flexcan Transceiver Enable on STK5-V5 */ +- MX28_PAD_LCD_D01__LCD_D1 +- MX28_PAD_LCD_D02__LCD_D2 +- MX28_PAD_LCD_D03__LCD_D3 +- MX28_PAD_LCD_D04__LCD_D4 +- MX28_PAD_LCD_D05__LCD_D5 +- MX28_PAD_LCD_D06__LCD_D6 +- MX28_PAD_LCD_D07__LCD_D7 +- MX28_PAD_LCD_D08__LCD_D8 +- MX28_PAD_LCD_D09__LCD_D9 +- MX28_PAD_LCD_D10__LCD_D10 +- MX28_PAD_LCD_D11__LCD_D11 +- MX28_PAD_LCD_D12__LCD_D12 +- MX28_PAD_LCD_D13__LCD_D13 +- MX28_PAD_LCD_D14__LCD_D14 +- MX28_PAD_LCD_D15__LCD_D15 +- MX28_PAD_LCD_D16__LCD_D16 +- MX28_PAD_LCD_D17__LCD_D17 +- MX28_PAD_LCD_D18__LCD_D18 +- MX28_PAD_LCD_D19__LCD_D19 +- MX28_PAD_LCD_D20__LCD_D20 +- MX28_PAD_LCD_D21__LCD_D21 +- MX28_PAD_LCD_D22__LCD_D22 +- MX28_PAD_LCD_D23__LCD_D23 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_ENABLE__GPIO_1_31 /* Enable */ +- MX28_PAD_LCD_RESET__GPIO_3_30 /* Reset */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- tx28_mac0_pins_gpio: tx28-mac0-gpio-pins@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_ENET0_MDC__GPIO_4_0 +- MX28_PAD_ENET0_MDIO__GPIO_4_1 +- MX28_PAD_ENET0_RX_EN__GPIO_4_2 +- MX28_PAD_ENET0_RXD0__GPIO_4_3 +- MX28_PAD_ENET0_RXD1__GPIO_4_4 +- MX28_PAD_ENET0_TX_EN__GPIO_4_6 +- MX28_PAD_ENET0_TXD0__GPIO_4_7 +- MX28_PAD_ENET0_TXD1__GPIO_4_8 +- MX28_PAD_ENET_CLK__GPIO_4_16 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- tx28_pca9554_pins: tx28-pca9554-pins@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_PWM3__GPIO_3_28 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- tx28_spi_gpio_pins: spi-gpiogrp@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART2_RX__GPIO_3_8 +- MX28_PAD_AUART2_TX__GPIO_3_9 +- MX28_PAD_SSP3_SCK__GPIO_2_24 +- MX28_PAD_SSP3_MOSI__GPIO_2_25 +- MX28_PAD_SSP3_MISO__GPIO_2_26 +- MX28_PAD_SSP3_SS0__GPIO_2_27 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- tx28_tsc2007_pins: tx28-tsc2007-pins@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- +- tx28_usbphy0_pins: tx28-usbphy0-pins@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_CE2N__GPIO_0_18 /* USBOTG_VBUSEN */ +- MX28_PAD_GPMI_CE3N__GPIO_0_19 /* USBOTH_OC */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- tx28_usbphy1_pins: tx28-usbphy1-pins@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SPDIF__GPIO_3_27 /* USBH_VBUSEN */ +- MX28_PAD_JTAG_RTCK__GPIO_4_20 /* USBH_OC */ +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +-}; +- +-&saif0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&saif0_pins_b>; +- fsl,saif-master; +- status = "okay"; +-}; +- +-&saif1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&saif1_pins_a>; +- status = "okay"; +-}; +- +-&ssp0 { +- compatible = "fsl,imx28-mmc"; +- pinctrl-names = "default", "special"; +- pinctrl-0 = <&mmc0_4bit_pins_a +- &mmc0_cd_cfg +- &mmc0_sck_cfg>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&ssp3 { +- compatible = "fsl,imx28-spi"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi3_pins_a>; +- clock-frequency = <57600000>; +- status = "okay"; +- +- spi@0 { +- compatible = "spidev"; +- reg = <0>; +- spi-max-frequency = <57600000>; +- }; +- +- spi@1 { +- compatible = "spidev"; +- reg = <1>; +- spi-max-frequency = <57600000>; +- }; +- +- spi@2 { +- compatible = "spidev"; +- reg = <2>; +- spi-max-frequency = <57600000>; +- }; +-}; +- +-&usb0 { +- vbus-supply = <®_usb0_vbus>; +- disable-over-current; +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usb1 { +- vbus-supply = <®_usb1_vbus>; +- disable-over-current; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbphy0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&tx28_usbphy0_pins>; +- phy_type = "utmi"; +- status = "okay"; +-}; +- +-&usbphy1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&tx28_usbphy1_pins>; +- phy_type = "utmi"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28-xea.dts b/scripts/dtc/include-prefixes/arm/imx28-xea.dts +deleted file mode 100644 +index a400c108f66a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28-xea.dts ++++ /dev/null +@@ -1,99 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright 2021 +- * Lukasz Majewski, DENX Software Engineering, lukma@denx.de +- */ +- +-/dts-v1/; +-#include "imx28-lwe.dtsi" +- +-/ { +- compatible = "lwn,imx28-xea", "fsl,imx28"; +-}; +- +-&can0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&can1_pins_a>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins_b>; +- status = "okay"; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&hog_pins_a &hog_pins_tiva>; +- +- hog_pins_a: hog@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_D00__GPIO_0_0 +- MX28_PAD_GPMI_D02__GPIO_0_2 +- MX28_PAD_GPMI_D05__GPIO_0_5 +- MX28_PAD_GPMI_CE1N__GPIO_0_17 +- MX28_PAD_GPMI_RDY0__GPIO_0_20 +- MX28_PAD_GPMI_RDY1__GPIO_0_21 +- MX28_PAD_GPMI_RDY2__GPIO_0_22 +- MX28_PAD_GPMI_RDN__GPIO_0_24 +- MX28_PAD_GPMI_CLE__GPIO_0_27 +- MX28_PAD_LCD_VSYNC__GPIO_1_28 +- MX28_PAD_SSP1_SCK__GPIO_2_12 +- MX28_PAD_SSP1_CMD__GPIO_2_13 +- MX28_PAD_SSP2_SS1__GPIO_2_20 +- MX28_PAD_SSP2_SS2__GPIO_2_21 +- MX28_PAD_LCD_D00__GPIO_1_0 +- MX28_PAD_LCD_D01__GPIO_1_1 +- MX28_PAD_LCD_D02__GPIO_1_2 +- MX28_PAD_LCD_D03__GPIO_1_3 +- MX28_PAD_LCD_D04__GPIO_1_4 +- MX28_PAD_LCD_D05__GPIO_1_5 +- MX28_PAD_LCD_D06__GPIO_1_6 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- hog_pins_tiva: hog@1 { +- reg = <1>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_RDY3__GPIO_0_23 +- MX28_PAD_GPMI_WRN__GPIO_0_25 +- >; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- hog_pins_coding: hog@2 { +- reg = <2>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_D01__GPIO_0_1 +- MX28_PAD_GPMI_D03__GPIO_0_3 +- MX28_PAD_GPMI_D04__GPIO_0_4 +- MX28_PAD_GPMI_D06__GPIO_0_6 +- MX28_PAD_GPMI_D07__GPIO_0_7 +- >; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +-}; +- +-®_fec_3v3 { +- gpio = <&gpio0 0 0>; +-}; +- +-®_usb_5v { +- gpio = <&gpio0 2 0>; +-}; +- +-&spi2_pins_a { +- fsl,pinmux-ids = < +- MX28_PAD_SSP2_SCK__SSP2_SCK +- MX28_PAD_SSP2_MOSI__SSP2_CMD +- MX28_PAD_SSP2_MISO__SSP2_D0 +- MX28_PAD_SSP2_SS0__GPIO_2_19 +- >; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx28.dtsi b/scripts/dtc/include-prefixes/arm/imx28.dtsi +deleted file mode 100644 +index 84d0176d5193..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx28.dtsi ++++ /dev/null +@@ -1,1340 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2012 Freescale Semiconductor, Inc. +- +-#include +-#include "imx28-pinfunc.h" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- interrupt-parent = <&icoll>; +- /* +- * The decompressor and also some bootloaders rely on a +- * pre-existing /chosen node to be available to insert the +- * command line and merge other ATAGS info. +- */ +- chosen {}; +- +- aliases { +- ethernet0 = &mac0; +- ethernet1 = &mac1; +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- gpio2 = &gpio2; +- gpio3 = &gpio3; +- gpio4 = &gpio4; +- saif0 = &saif0; +- saif1 = &saif1; +- serial0 = &auart0; +- serial1 = &auart1; +- serial2 = &auart2; +- serial3 = &auart3; +- serial4 = &auart4; +- spi0 = &ssp1; +- spi1 = &ssp2; +- usbphy0 = &usbphy0; +- usbphy1 = &usbphy1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,arm926ej-s"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- apb@80000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x80000000 0x80000>; +- ranges; +- +- apbh@80000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x80000000 0x3c900>; +- ranges; +- +- icoll: interrupt-controller@80000000 { +- compatible = "fsl,imx28-icoll", "fsl,icoll"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x80000000 0x2000>; +- }; +- +- hsadc: hsadc@80002000 { +- reg = <0x80002000 0x2000>; +- interrupts = <13>; +- dmas = <&dma_apbh 12>; +- dma-names = "rx"; +- status = "disabled"; +- }; +- +- dma_apbh: dma-apbh@80004000 { +- compatible = "fsl,imx28-dma-apbh"; +- reg = <0x80004000 0x2000>; +- interrupts = <82 83 84 85 +- 88 88 88 88 +- 88 88 88 88 +- 87 86 0 0>; +- interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3", +- "gpmi0", "gmpi1", "gpmi2", "gmpi3", +- "gpmi4", "gmpi5", "gpmi6", "gmpi7", +- "hsadc", "lcdif", "empty", "empty"; +- #dma-cells = <1>; +- dma-channels = <16>; +- clocks = <&clks 25>; +- }; +- +- perfmon: perfmon@80006000 { +- reg = <0x80006000 0x800>; +- interrupts = <27>; +- status = "disabled"; +- }; +- +- gpmi: nand-controller@8000c000 { +- compatible = "fsl,imx28-gpmi-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; +- reg-names = "gpmi-nand", "bch"; +- interrupts = <41>; +- interrupt-names = "bch"; +- clocks = <&clks 50>; +- clock-names = "gpmi_io"; +- dmas = <&dma_apbh 4>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- ssp0: spi@80010000 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x80010000 0x2000>; +- interrupts = <96>; +- clocks = <&clks 46>; +- dmas = <&dma_apbh 0>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- ssp1: spi@80012000 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x80012000 0x2000>; +- interrupts = <97>; +- clocks = <&clks 47>; +- dmas = <&dma_apbh 1>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- ssp2: spi@80014000 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x80014000 0x2000>; +- interrupts = <98>; +- clocks = <&clks 48>; +- dmas = <&dma_apbh 2>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- ssp3: spi@80016000 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x80016000 0x2000>; +- interrupts = <99>; +- clocks = <&clks 49>; +- dmas = <&dma_apbh 3>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- pinctrl: pinctrl@80018000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx28-pinctrl", "simple-bus"; +- reg = <0x80018000 0x2000>; +- +- gpio0: gpio@0 { +- compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; +- reg = <0>; +- interrupts = <127>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio@1 { +- compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; +- reg = <1>; +- interrupts = <126>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@2 { +- compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; +- reg = <2>; +- interrupts = <125>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio@3 { +- compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; +- reg = <3>; +- interrupts = <124>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio4: gpio@4 { +- compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; +- reg = <4>; +- interrupts = <123>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- duart_pins_a: duart@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_PWM0__DUART_RX +- MX28_PAD_PWM1__DUART_TX +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- duart_pins_b: duart@1 { +- reg = <1>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART0_CTS__DUART_RX +- MX28_PAD_AUART0_RTS__DUART_TX +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- duart_4pins_a: duart-4pins@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART0_CTS__DUART_RX +- MX28_PAD_AUART0_RTS__DUART_TX +- MX28_PAD_AUART0_RX__DUART_CTS +- MX28_PAD_AUART0_TX__DUART_RTS +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- gpmi_pins_a: gpmi-nand@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_D00__GPMI_D0 +- MX28_PAD_GPMI_D01__GPMI_D1 +- MX28_PAD_GPMI_D02__GPMI_D2 +- MX28_PAD_GPMI_D03__GPMI_D3 +- MX28_PAD_GPMI_D04__GPMI_D4 +- MX28_PAD_GPMI_D05__GPMI_D5 +- MX28_PAD_GPMI_D06__GPMI_D6 +- MX28_PAD_GPMI_D07__GPMI_D7 +- MX28_PAD_GPMI_CE0N__GPMI_CE0N +- MX28_PAD_GPMI_RDY0__GPMI_READY0 +- MX28_PAD_GPMI_RDN__GPMI_RDN +- MX28_PAD_GPMI_WRN__GPMI_WRN +- MX28_PAD_GPMI_ALE__GPMI_ALE +- MX28_PAD_GPMI_CLE__GPMI_CLE +- MX28_PAD_GPMI_RESETN__GPMI_RESETN +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- gpmi_status_cfg: gpmi-status-cfg@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_RDN__GPMI_RDN +- MX28_PAD_GPMI_WRN__GPMI_WRN +- MX28_PAD_GPMI_RESETN__GPMI_RESETN +- >; +- fsl,drive-strength = ; +- }; +- +- auart0_pins_a: auart0@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART0_RX__AUART0_RX +- MX28_PAD_AUART0_TX__AUART0_TX +- MX28_PAD_AUART0_CTS__AUART0_CTS +- MX28_PAD_AUART0_RTS__AUART0_RTS +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- auart0_2pins_a: auart0-2pins@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART0_RX__AUART0_RX +- MX28_PAD_AUART0_TX__AUART0_TX +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- auart1_pins_a: auart1@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART1_RX__AUART1_RX +- MX28_PAD_AUART1_TX__AUART1_TX +- MX28_PAD_AUART1_CTS__AUART1_CTS +- MX28_PAD_AUART1_RTS__AUART1_RTS +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- auart1_2pins_a: auart1-2pins@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART1_RX__AUART1_RX +- MX28_PAD_AUART1_TX__AUART1_TX +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- auart2_2pins_a: auart2-2pins@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP2_SCK__AUART2_RX +- MX28_PAD_SSP2_MOSI__AUART2_TX +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- auart2_2pins_b: auart2-2pins@1 { +- reg = <1>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART2_RX__AUART2_RX +- MX28_PAD_AUART2_TX__AUART2_TX +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- auart2_pins_a: auart2-pins@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART2_RX__AUART2_RX +- MX28_PAD_AUART2_TX__AUART2_TX +- MX28_PAD_AUART2_CTS__AUART2_CTS +- MX28_PAD_AUART2_RTS__AUART2_RTS +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- auart3_pins_a: auart3@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART3_RX__AUART3_RX +- MX28_PAD_AUART3_TX__AUART3_TX +- MX28_PAD_AUART3_CTS__AUART3_CTS +- MX28_PAD_AUART3_RTS__AUART3_RTS +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- auart3_2pins_a: auart3-2pins@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP2_MISO__AUART3_RX +- MX28_PAD_SSP2_SS0__AUART3_TX +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- auart3_2pins_b: auart3-2pins@1 { +- reg = <1>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART3_RX__AUART3_RX +- MX28_PAD_AUART3_TX__AUART3_TX +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- auart4_2pins_a: auart4@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP3_SCK__AUART4_TX +- MX28_PAD_SSP3_MOSI__AUART4_RX +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- auart4_2pins_b: auart4@1 { +- reg = <1>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART0_CTS__AUART4_RX +- MX28_PAD_AUART0_RTS__AUART4_TX +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mac0_pins_a: mac0@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_ENET0_MDC__ENET0_MDC +- MX28_PAD_ENET0_MDIO__ENET0_MDIO +- MX28_PAD_ENET0_RX_EN__ENET0_RX_EN +- MX28_PAD_ENET0_RXD0__ENET0_RXD0 +- MX28_PAD_ENET0_RXD1__ENET0_RXD1 +- MX28_PAD_ENET0_TX_EN__ENET0_TX_EN +- MX28_PAD_ENET0_TXD0__ENET0_TXD0 +- MX28_PAD_ENET0_TXD1__ENET0_TXD1 +- MX28_PAD_ENET_CLK__CLKCTRL_ENET +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mac0_pins_b: mac0@1 { +- reg = <1>; +- fsl,pinmux-ids = < +- MX28_PAD_ENET0_MDC__ENET0_MDC +- MX28_PAD_ENET0_MDIO__ENET0_MDIO +- MX28_PAD_ENET0_RX_EN__ENET0_RX_EN +- MX28_PAD_ENET0_RXD0__ENET0_RXD0 +- MX28_PAD_ENET0_RXD1__ENET0_RXD1 +- MX28_PAD_ENET0_RXD2__ENET0_RXD2 +- MX28_PAD_ENET0_RXD3__ENET0_RXD3 +- MX28_PAD_ENET0_TX_EN__ENET0_TX_EN +- MX28_PAD_ENET0_TXD0__ENET0_TXD0 +- MX28_PAD_ENET0_TXD1__ENET0_TXD1 +- MX28_PAD_ENET0_TXD2__ENET0_TXD2 +- MX28_PAD_ENET0_TXD3__ENET0_TXD3 +- MX28_PAD_ENET_CLK__CLKCTRL_ENET +- MX28_PAD_ENET0_COL__ENET0_COL +- MX28_PAD_ENET0_CRS__ENET0_CRS +- MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK +- MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mac1_pins_a: mac1@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_ENET0_CRS__ENET1_RX_EN +- MX28_PAD_ENET0_RXD2__ENET1_RXD0 +- MX28_PAD_ENET0_RXD3__ENET1_RXD1 +- MX28_PAD_ENET0_COL__ENET1_TX_EN +- MX28_PAD_ENET0_TXD2__ENET1_TXD0 +- MX28_PAD_ENET0_TXD3__ENET1_TXD1 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mmc0_8bit_pins_a: mmc0-8bit@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP0_DATA0__SSP0_D0 +- MX28_PAD_SSP0_DATA1__SSP0_D1 +- MX28_PAD_SSP0_DATA2__SSP0_D2 +- MX28_PAD_SSP0_DATA3__SSP0_D3 +- MX28_PAD_SSP0_DATA4__SSP0_D4 +- MX28_PAD_SSP0_DATA5__SSP0_D5 +- MX28_PAD_SSP0_DATA6__SSP0_D6 +- MX28_PAD_SSP0_DATA7__SSP0_D7 +- MX28_PAD_SSP0_CMD__SSP0_CMD +- MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT +- MX28_PAD_SSP0_SCK__SSP0_SCK +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mmc0_4bit_pins_a: mmc0-4bit@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP0_DATA0__SSP0_D0 +- MX28_PAD_SSP0_DATA1__SSP0_D1 +- MX28_PAD_SSP0_DATA2__SSP0_D2 +- MX28_PAD_SSP0_DATA3__SSP0_D3 +- MX28_PAD_SSP0_CMD__SSP0_CMD +- MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT +- MX28_PAD_SSP0_SCK__SSP0_SCK +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mmc0_cd_cfg: mmc0-cd-cfg@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT +- >; +- fsl,pull-up = ; +- }; +- +- mmc0_sck_cfg: mmc0-sck-cfg@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP0_SCK__SSP0_SCK +- >; +- fsl,drive-strength = ; +- fsl,pull-up = ; +- }; +- +- mmc1_4bit_pins_a: mmc1-4bit@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_D00__SSP1_D0 +- MX28_PAD_GPMI_D01__SSP1_D1 +- MX28_PAD_GPMI_D02__SSP1_D2 +- MX28_PAD_GPMI_D03__SSP1_D3 +- MX28_PAD_GPMI_RDY1__SSP1_CMD +- MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT +- MX28_PAD_GPMI_WRN__SSP1_SCK +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mmc1_cd_cfg: mmc1-cd-cfg@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT +- >; +- fsl,pull-up = ; +- }; +- +- mmc1_sck_cfg: mmc1-sck-cfg@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_WRN__SSP1_SCK +- >; +- fsl,drive-strength = ; +- fsl,pull-up = ; +- }; +- +- +- mmc2_4bit_pins_a: mmc2-4bit@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP0_DATA4__SSP2_D0 +- MX28_PAD_SSP1_SCK__SSP2_D1 +- MX28_PAD_SSP1_CMD__SSP2_D2 +- MX28_PAD_SSP0_DATA5__SSP2_D3 +- MX28_PAD_SSP0_DATA6__SSP2_CMD +- MX28_PAD_AUART1_RX__SSP2_CARD_DETECT +- MX28_PAD_SSP0_DATA7__SSP2_SCK +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mmc2_4bit_pins_b: mmc2-4bit@1 { +- reg = <1>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP2_SCK__SSP2_SCK +- MX28_PAD_SSP2_MOSI__SSP2_CMD +- MX28_PAD_SSP2_MISO__SSP2_D0 +- MX28_PAD_SSP2_SS0__SSP2_D3 +- MX28_PAD_SSP2_SS1__SSP2_D1 +- MX28_PAD_SSP2_SS2__SSP2_D2 +- MX28_PAD_AUART1_RX__SSP2_CARD_DETECT +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- mmc2_cd_cfg: mmc2-cd-cfg@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART1_RX__SSP2_CARD_DETECT +- >; +- fsl,pull-up = ; +- }; +- +- mmc2_sck_cfg_a: mmc2-sck-cfg@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP0_DATA7__SSP2_SCK +- >; +- fsl,drive-strength = ; +- fsl,pull-up = ; +- }; +- +- mmc2_sck_cfg_b: mmc2-sck-cfg@1 { +- reg = <1>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP2_SCK__SSP2_SCK +- >; +- fsl,drive-strength = ; +- fsl,pull-up = ; +- }; +- +- i2c0_pins_a: i2c0@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_I2C0_SCL__I2C0_SCL +- MX28_PAD_I2C0_SDA__I2C0_SDA +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- i2c0_pins_b: i2c0@1 { +- reg = <1>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART0_RX__I2C0_SCL +- MX28_PAD_AUART0_TX__I2C0_SDA +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- i2c1_pins_a: i2c1@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_PWM0__I2C1_SCL +- MX28_PAD_PWM1__I2C1_SDA +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- i2c1_pins_b: i2c1@1 { +- reg = <1>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART2_CTS__I2C1_SCL +- MX28_PAD_AUART2_RTS__I2C1_SDA +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- saif0_pins_a: saif0@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SAIF0_MCLK__SAIF0_MCLK +- MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK +- MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK +- MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- saif0_pins_b: saif0@1 { +- reg = <1>; +- fsl,pinmux-ids = < +- MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK +- MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK +- MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- saif1_pins_a: saif1@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- pwm0_pins_a: pwm0@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_PWM0__PWM_0 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- pwm2_pins_a: pwm2@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_PWM2__PWM_2 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- pwm3_pins_a: pwm3@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_PWM3__PWM_3 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- pwm3_pins_b: pwm3@1 { +- reg = <1>; +- fsl,pinmux-ids = < +- MX28_PAD_SAIF0_MCLK__PWM_3 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- pwm4_pins_a: pwm4@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_PWM4__PWM_4 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_24bit_pins_a: lcdif-24bit@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D00__LCD_D0 +- MX28_PAD_LCD_D01__LCD_D1 +- MX28_PAD_LCD_D02__LCD_D2 +- MX28_PAD_LCD_D03__LCD_D3 +- MX28_PAD_LCD_D04__LCD_D4 +- MX28_PAD_LCD_D05__LCD_D5 +- MX28_PAD_LCD_D06__LCD_D6 +- MX28_PAD_LCD_D07__LCD_D7 +- MX28_PAD_LCD_D08__LCD_D8 +- MX28_PAD_LCD_D09__LCD_D9 +- MX28_PAD_LCD_D10__LCD_D10 +- MX28_PAD_LCD_D11__LCD_D11 +- MX28_PAD_LCD_D12__LCD_D12 +- MX28_PAD_LCD_D13__LCD_D13 +- MX28_PAD_LCD_D14__LCD_D14 +- MX28_PAD_LCD_D15__LCD_D15 +- MX28_PAD_LCD_D16__LCD_D16 +- MX28_PAD_LCD_D17__LCD_D17 +- MX28_PAD_LCD_D18__LCD_D18 +- MX28_PAD_LCD_D19__LCD_D19 +- MX28_PAD_LCD_D20__LCD_D20 +- MX28_PAD_LCD_D21__LCD_D21 +- MX28_PAD_LCD_D22__LCD_D22 +- MX28_PAD_LCD_D23__LCD_D23 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_18bit_pins_a: lcdif-18bit@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D00__LCD_D0 +- MX28_PAD_LCD_D01__LCD_D1 +- MX28_PAD_LCD_D02__LCD_D2 +- MX28_PAD_LCD_D03__LCD_D3 +- MX28_PAD_LCD_D04__LCD_D4 +- MX28_PAD_LCD_D05__LCD_D5 +- MX28_PAD_LCD_D06__LCD_D6 +- MX28_PAD_LCD_D07__LCD_D7 +- MX28_PAD_LCD_D08__LCD_D8 +- MX28_PAD_LCD_D09__LCD_D9 +- MX28_PAD_LCD_D10__LCD_D10 +- MX28_PAD_LCD_D11__LCD_D11 +- MX28_PAD_LCD_D12__LCD_D12 +- MX28_PAD_LCD_D13__LCD_D13 +- MX28_PAD_LCD_D14__LCD_D14 +- MX28_PAD_LCD_D15__LCD_D15 +- MX28_PAD_LCD_D16__LCD_D16 +- MX28_PAD_LCD_D17__LCD_D17 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_16bit_pins_a: lcdif-16bit@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_D00__LCD_D0 +- MX28_PAD_LCD_D01__LCD_D1 +- MX28_PAD_LCD_D02__LCD_D2 +- MX28_PAD_LCD_D03__LCD_D3 +- MX28_PAD_LCD_D04__LCD_D4 +- MX28_PAD_LCD_D05__LCD_D5 +- MX28_PAD_LCD_D06__LCD_D6 +- MX28_PAD_LCD_D07__LCD_D7 +- MX28_PAD_LCD_D08__LCD_D8 +- MX28_PAD_LCD_D09__LCD_D9 +- MX28_PAD_LCD_D10__LCD_D10 +- MX28_PAD_LCD_D11__LCD_D11 +- MX28_PAD_LCD_D12__LCD_D12 +- MX28_PAD_LCD_D13__LCD_D13 +- MX28_PAD_LCD_D14__LCD_D14 +- MX28_PAD_LCD_D15__LCD_D15 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- lcdif_sync_pins_a: lcdif-sync@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_LCD_RS__LCD_DOTCLK +- MX28_PAD_LCD_CS__LCD_ENABLE +- MX28_PAD_LCD_RD_E__LCD_VSYNC +- MX28_PAD_LCD_WR_RWN__LCD_HSYNC +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- can0_pins_a: can0@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_RDY2__CAN0_TX +- MX28_PAD_GPMI_RDY3__CAN0_RX +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- can1_pins_a: can1@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_GPMI_CE2N__CAN1_TX +- MX28_PAD_GPMI_CE3N__CAN1_RX +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- spi2_pins_a: spi2@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP2_SCK__SSP2_SCK +- MX28_PAD_SSP2_MOSI__SSP2_CMD +- MX28_PAD_SSP2_MISO__SSP2_D0 +- MX28_PAD_SSP2_SS0__SSP2_D3 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- spi3_pins_a: spi3@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART2_RX__SSP3_D4 +- MX28_PAD_AUART2_TX__SSP3_D5 +- MX28_PAD_SSP3_SCK__SSP3_SCK +- MX28_PAD_SSP3_MOSI__SSP3_CMD +- MX28_PAD_SSP3_MISO__SSP3_D0 +- MX28_PAD_SSP3_SS0__SSP3_D3 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- spi3_pins_b: spi3@1 { +- reg = <1>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP3_SCK__SSP3_SCK +- MX28_PAD_SSP3_MOSI__SSP3_CMD +- MX28_PAD_SSP3_MISO__SSP3_D0 +- MX28_PAD_SSP3_SS0__SSP3_D3 +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- usb0_pins_a: usb0@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP2_SS2__USB0_OVERCURRENT +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- usb0_pins_b: usb0@1 { +- reg = <1>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART1_CTS__USB0_OVERCURRENT +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- usb1_pins_a: usb1@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_SSP2_SS1__USB1_OVERCURRENT +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- usb1_pins_b: usb1@1 { +- reg = <1>; +- fsl,pinmux-ids = < +- MX28_PAD_PWM2__USB1_OVERCURRENT +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- usb0_id_pins_a: usb0id@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_AUART1_RTS__USB0_ID +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- usb0_id_pins_b: usb0id1@0 { +- reg = <0>; +- fsl,pinmux-ids = < +- MX28_PAD_PWM2__USB0_ID +- >; +- fsl,drive-strength = ; +- fsl,voltage = ; +- fsl,pull-up = ; +- }; +- +- }; +- +- digctl: digctl@8001c000 { +- compatible = "fsl,imx28-digctl", "fsl,imx23-digctl"; +- reg = <0x8001c000 0x2000>; +- interrupts = <89>; +- status = "disabled"; +- }; +- +- etm: etm@80022000 { +- reg = <0x80022000 0x2000>; +- status = "disabled"; +- }; +- +- dma_apbx: dma-apbx@80024000 { +- compatible = "fsl,imx28-dma-apbx"; +- reg = <0x80024000 0x2000>; +- interrupts = <78 79 66 0 +- 80 81 68 69 +- 70 71 72 73 +- 74 75 76 77>; +- interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty", +- "saif0", "saif1", "i2c0", "i2c1", +- "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", +- "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; +- #dma-cells = <1>; +- dma-channels = <16>; +- clocks = <&clks 26>; +- }; +- +- dcp: crypto@80028000 { +- compatible = "fsl,imx28-dcp", "fsl,imx23-dcp"; +- reg = <0x80028000 0x2000>; +- interrupts = <52 53 54>; +- status = "okay"; +- }; +- +- pxp: pxp@8002a000 { +- reg = <0x8002a000 0x2000>; +- interrupts = <39>; +- status = "disabled"; +- }; +- +- ocotp: efuse@8002c000 { +- compatible = "fsl,imx28-ocotp", "fsl,ocotp"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x8002c000 0x2000>; +- clocks = <&clks 25>; +- }; +- +- axi-ahb@8002e000 { +- reg = <0x8002e000 0x2000>; +- status = "disabled"; +- }; +- +- lcdif: lcdif@80030000 { +- compatible = "fsl,imx28-lcdif"; +- reg = <0x80030000 0x2000>; +- interrupts = <38>; +- clocks = <&clks 55>; +- dmas = <&dma_apbh 13>; +- dma-names = "rx"; +- status = "disabled"; +- }; +- +- can0: can@80032000 { +- compatible = "fsl,imx28-flexcan"; +- reg = <0x80032000 0x2000>; +- interrupts = <8>; +- clocks = <&clks 58>, <&clks 58>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- can1: can@80034000 { +- compatible = "fsl,imx28-flexcan"; +- reg = <0x80034000 0x2000>; +- interrupts = <9>; +- clocks = <&clks 59>, <&clks 59>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- simdbg: simdbg@8003c000 { +- reg = <0x8003c000 0x200>; +- status = "disabled"; +- }; +- +- simgpmisel: simgpmisel@8003c200 { +- reg = <0x8003c200 0x100>; +- status = "disabled"; +- }; +- +- simsspsel: simsspsel@8003c300 { +- reg = <0x8003c300 0x100>; +- status = "disabled"; +- }; +- +- simmemsel: simmemsel@8003c400 { +- reg = <0x8003c400 0x100>; +- status = "disabled"; +- }; +- +- gpiomon: gpiomon@8003c500 { +- reg = <0x8003c500 0x100>; +- status = "disabled"; +- }; +- +- simenet: simenet@8003c700 { +- reg = <0x8003c700 0x100>; +- status = "disabled"; +- }; +- +- armjtag: armjtag@8003c800 { +- reg = <0x8003c800 0x100>; +- status = "disabled"; +- }; +- }; +- +- apbx@80040000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x80040000 0x40000>; +- ranges; +- +- clks: clkctrl@80040000 { +- compatible = "fsl,imx28-clkctrl", "fsl,clkctrl"; +- reg = <0x80040000 0x2000>; +- #clock-cells = <1>; +- }; +- +- saif0: saif@80042000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx28-saif"; +- reg = <0x80042000 0x2000>; +- interrupts = <59>; +- #clock-cells = <0>; +- clocks = <&clks 53>; +- dmas = <&dma_apbx 4>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- power: power@80044000 { +- reg = <0x80044000 0x2000>; +- status = "disabled"; +- }; +- +- saif1: saif@80046000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx28-saif"; +- reg = <0x80046000 0x2000>; +- interrupts = <58>; +- clocks = <&clks 54>; +- dmas = <&dma_apbx 5>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- lradc: lradc@80050000 { +- compatible = "fsl,imx28-lradc"; +- reg = <0x80050000 0x2000>; +- interrupts = <10 14 15 16 17 18 19 +- 20 21 22 23 24 25>; +- status = "disabled"; +- clocks = <&clks 41>; +- #io-channel-cells = <1>; +- }; +- +- spdif: spdif@80054000 { +- reg = <0x80054000 0x2000>; +- interrupts = <45>; +- dmas = <&dma_apbx 2>; +- dma-names = "tx"; +- status = "disabled"; +- }; +- +- mxs_rtc: rtc@80056000 { +- compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; +- reg = <0x80056000 0x2000>; +- interrupts = <29>; +- }; +- +- i2c0: i2c@80058000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx28-i2c"; +- reg = <0x80058000 0x2000>; +- interrupts = <111>; +- clock-frequency = <100000>; +- dmas = <&dma_apbx 6>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- i2c1: i2c@8005a000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx28-i2c"; +- reg = <0x8005a000 0x2000>; +- interrupts = <110>; +- clock-frequency = <100000>; +- dmas = <&dma_apbx 7>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- pwm: pwm@80064000 { +- compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; +- reg = <0x80064000 0x2000>; +- clocks = <&clks 44>; +- #pwm-cells = <2>; +- fsl,pwm-number = <8>; +- status = "disabled"; +- }; +- +- timer: timrot@80068000 { +- compatible = "fsl,imx28-timrot", "fsl,timrot"; +- reg = <0x80068000 0x2000>; +- interrupts = <48 49 50 51>; +- clocks = <&clks 26>; +- }; +- +- auart0: serial@8006a000 { +- compatible = "fsl,imx28-auart", "fsl,imx23-auart"; +- reg = <0x8006a000 0x2000>; +- interrupts = <112>; +- dmas = <&dma_apbx 8>, <&dma_apbx 9>; +- dma-names = "rx", "tx"; +- clocks = <&clks 45>; +- status = "disabled"; +- }; +- +- auart1: serial@8006c000 { +- compatible = "fsl,imx28-auart", "fsl,imx23-auart"; +- reg = <0x8006c000 0x2000>; +- interrupts = <113>; +- dmas = <&dma_apbx 10>, <&dma_apbx 11>; +- dma-names = "rx", "tx"; +- clocks = <&clks 45>; +- status = "disabled"; +- }; +- +- auart2: serial@8006e000 { +- compatible = "fsl,imx28-auart", "fsl,imx23-auart"; +- reg = <0x8006e000 0x2000>; +- interrupts = <114>; +- dmas = <&dma_apbx 12>, <&dma_apbx 13>; +- dma-names = "rx", "tx"; +- clocks = <&clks 45>; +- status = "disabled"; +- }; +- +- auart3: serial@80070000 { +- compatible = "fsl,imx28-auart", "fsl,imx23-auart"; +- reg = <0x80070000 0x2000>; +- interrupts = <115>; +- dmas = <&dma_apbx 14>, <&dma_apbx 15>; +- dma-names = "rx", "tx"; +- clocks = <&clks 45>; +- status = "disabled"; +- }; +- +- auart4: serial@80072000 { +- compatible = "fsl,imx28-auart", "fsl,imx23-auart"; +- reg = <0x80072000 0x2000>; +- interrupts = <116>; +- dmas = <&dma_apbx 0>, <&dma_apbx 1>; +- dma-names = "rx", "tx"; +- clocks = <&clks 45>; +- status = "disabled"; +- }; +- +- duart: serial@80074000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x80074000 0x1000>; +- interrupts = <47>; +- clocks = <&clks 45>, <&clks 26>; +- clock-names = "uart", "apb_pclk"; +- status = "disabled"; +- }; +- +- usbphy0: usbphy@8007c000 { +- compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; +- reg = <0x8007c000 0x2000>; +- clocks = <&clks 62>; +- status = "disabled"; +- }; +- +- usbphy1: usbphy@8007e000 { +- compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; +- reg = <0x8007e000 0x2000>; +- clocks = <&clks 63>; +- status = "disabled"; +- }; +- }; +- }; +- +- ahb@80080000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x80080000 0x80000>; +- ranges; +- +- usb0: usb@80080000 { +- compatible = "fsl,imx28-usb", "fsl,imx27-usb"; +- reg = <0x80080000 0x10000>; +- interrupts = <93>; +- clocks = <&clks 60>; +- fsl,usbphy = <&usbphy0>; +- status = "disabled"; +- }; +- +- usb1: usb@80090000 { +- compatible = "fsl,imx28-usb", "fsl,imx27-usb"; +- reg = <0x80090000 0x10000>; +- interrupts = <92>; +- clocks = <&clks 61>; +- fsl,usbphy = <&usbphy1>; +- dr_mode = "host"; +- status = "disabled"; +- }; +- +- dflpt: dflpt@800c0000 { +- reg = <0x800c0000 0x10000>; +- status = "disabled"; +- }; +- +- mac0: ethernet@800f0000 { +- compatible = "fsl,imx28-fec"; +- reg = <0x800f0000 0x4000>; +- interrupts = <101>; +- clocks = <&clks 57>, <&clks 57>, <&clks 64>; +- clock-names = "ipg", "ahb", "enet_out"; +- status = "disabled"; +- }; +- +- mac1: ethernet@800f4000 { +- compatible = "fsl,imx28-fec"; +- reg = <0x800f4000 0x4000>; +- interrupts = <102>; +- clocks = <&clks 57>, <&clks 57>; +- clock-names = "ipg", "ahb"; +- status = "disabled"; +- }; +- +- eth_switch: switch@800f8000 { +- reg = <0x800f8000 0x8000>; +- status = "disabled"; +- }; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&lradc 8>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx31-bug.dts b/scripts/dtc/include-prefixes/arm/imx31-bug.dts +deleted file mode 100644 +index d87eee3f9b3c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx31-bug.dts ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Denis 'GNUtoo' Carikli +- */ +- +-/dts-v1/; +-#include "imx31.dtsi" +- +-/ { +- model = "Buglabs i.MX31 Bug 1.x"; +- compatible = "buglabs,imx31-bug", "fsl,imx31"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x8000000>; /* 128M */ +- }; +-}; +- +-&uart5 { +- uart-has-rtscts; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx31-lite.dts b/scripts/dtc/include-prefixes/arm/imx31-lite.dts +deleted file mode 100644 +index d17abdfb6330..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx31-lite.dts ++++ /dev/null +@@ -1,178 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright (C) 2016-2018 Vladimir Zapolskiy +- +-/dts-v1/; +- +-#include "imx31.dtsi" +- +-#include +-#include +- +-/ { +- model = "LogicPD i.MX31 Lite"; +- compatible = "logicpd,imx31-lite", "fsl,imx31"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x8000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led0 { +- gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; +- }; +- +- led1 { +- gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&ata { +- status = "okay"; +-}; +- +-&nfc { +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-on-flash-bbt; +- status = "okay"; +-}; +- +-&sdhci1 { +- bus-width = <4>; +- cd-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; +- wp-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&spi2 { +- status = "okay"; +- +- pmic@0 { +- compatible = "fsl,mc13783"; +- reg = <0>; +- spi-cs-high; +- spi-max-frequency = <1000000>; +- interrupt-parent = <&gpio1>; +- interrupts = <3 IRQ_TYPE_EDGE_RISING>; +- +- fsl,mc13xxx-uses-adc; +- fsl,mc13xxx-uses-rtc; +- +- regulators { +- sw1a { /* QVCC */ +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- sw1b { /* QVCC */ +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- sw2a { /* 1.8V_DDR, NVCC2, NVCC21 and NVCC22 */ +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- sw2b { /* NVCC10 */ +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- violo { /* NVCC1 and NVCC7 */ +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- viohi { /* VIOHI */ +- regulator-min-microvolt = <2775000>; +- regulator-max-microvolt = <2775000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vaudio { /* VAUDIO */ +- regulator-min-microvolt = <2775000>; +- regulator-max-microvolt = <2775000>; +- }; +- +- vcam { /* NVCC4 */ +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- vgen { /* NVCC5 / NVCC8 and NVCC6 / NVCC9 */ +- regulator-min-microvolt = <2775000>; +- regulator-max-microvolt = <2775000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vmmc2 { /* NVCC3 */ +- regulator-min-microvolt = <1600000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&uart1 { +- uart-has-rtscts; +- status = "okay"; +-}; +- +-/* Routed to the extension board */ +-&uart2 { +- uart-has-rtscts; +- status = "okay"; +-}; +- +-/* Routed to the extension board */ +-&uart3 { +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&weim { +- status = "okay"; +- +- nor@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0x0 0x200000>; +- bank-width = <2>; +- linux,mtd-name = "physmap-flash.0"; +- fsl,weim-cs-timing = <0x0000cf03 0xa0330d01 0x00220800>; +- }; +- +- ethernet@4,0 { +- compatible = "smsc,lan9117", "smsc,lan9115"; +- reg = <4 0x0 0x100>; +- interrupt-parent = <&gpio1>; +- interrupts = <26 IRQ_TYPE_EDGE_FALLING>; +- phy-mode = "mii"; +- reg-io-width = <2>; +- smsc,irq-push-pull; +- fsl,weim-cs-timing = <0x00008701 0x04000541 0x00010000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx31.dtsi b/scripts/dtc/include-prefixes/arm/imx31.dtsi +deleted file mode 100644 +index 948d2a543f8d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx31.dtsi ++++ /dev/null +@@ -1,371 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2016-2018 Vladimir Zapolskiy +-// Copyright 2012 Denis 'GNUtoo' Carikli +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * The decompressor and also some bootloaders rely on a +- * pre-existing /chosen node to be available to insert the +- * command line and merge other ATAGS info. +- */ +- chosen {}; +- +- aliases { +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- serial4 = &uart5; +- spi0 = &spi1; +- spi1 = &spi2; +- spi2 = &spi3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,arm1136jf-s"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- avic: interrupt-controller@68000000 { +- compatible = "fsl,imx31-avic", "fsl,avic"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x68000000 0x100000>; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&avic>; +- ranges; +- +- iram: sram@1fffc000 { +- compatible = "mmio-sram"; +- reg = <0x1fffc000 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1fffc000 0x4000>; +- }; +- +- bus@43f00000 { /* AIPS1 */ +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x43f00000 0x100000>; +- ranges; +- +- i2c1: i2c@43f80000 { +- compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; +- reg = <0x43f80000 0x4000>; +- interrupts = <10>; +- clocks = <&clks 33>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@43f84000 { +- compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; +- reg = <0x43f84000 0x4000>; +- interrupts = <3>; +- clocks = <&clks 35>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- ata: ata@43f8c000 { +- compatible = "fsl,imx31-pata", "fsl,imx27-pata"; +- reg = <0x43f8c000 0x4000>; +- interrupts = <15>; +- clocks = <&clks 26>; +- status = "disabled"; +- }; +- +- uart1: serial@43f90000 { +- compatible = "fsl,imx31-uart", "fsl,imx21-uart"; +- reg = <0x43f90000 0x4000>; +- interrupts = <45>; +- clocks = <&clks 10>, <&clks 30>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart2: serial@43f94000 { +- compatible = "fsl,imx31-uart", "fsl,imx21-uart"; +- reg = <0x43f94000 0x4000>; +- interrupts = <32>; +- clocks = <&clks 10>, <&clks 31>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- i2c2: i2c@43f98000 { +- compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; +- reg = <0x43f98000 0x4000>; +- interrupts = <4>; +- clocks = <&clks 34>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi1: spi@43fa4000 { +- compatible = "fsl,imx31-cspi"; +- reg = <0x43fa4000 0x4000>; +- interrupts = <14>; +- clocks = <&clks 10>, <&clks 53>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 8 8 0>, <&sdma 9 8 0>; +- dma-names = "rx", "tx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- kpp: kpp@43fa8000 { +- compatible = "fsl,imx31-kpp", "fsl,imx21-kpp"; +- reg = <0x43fa8000 0x4000>; +- interrupts = <24>; +- clocks = <&clks 46>; +- status = "disabled"; +- }; +- +- uart4: serial@43fb0000 { +- compatible = "fsl,imx31-uart", "fsl,imx21-uart"; +- reg = <0x43fb0000 0x4000>; +- clocks = <&clks 10>, <&clks 49>; +- clock-names = "ipg", "per"; +- interrupts = <46>; +- status = "disabled"; +- }; +- +- uart5: serial@43fb4000 { +- compatible = "fsl,imx31-uart", "fsl,imx21-uart"; +- reg = <0x43fb4000 0x4000>; +- interrupts = <47>; +- clocks = <&clks 10>, <&clks 50>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- }; +- +- spba@50000000 { +- compatible = "fsl,spba-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x50000000 0x100000>; +- ranges; +- +- sdhci1: mmc@50004000 { +- compatible = "fsl,imx31-mmc"; +- reg = <0x50004000 0x4000>; +- interrupts = <9>; +- clocks = <&clks 10>, <&clks 20>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 20 3 0>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- sdhci2: mmc@50008000 { +- compatible = "fsl,imx31-mmc"; +- reg = <0x50008000 0x4000>; +- interrupts = <8>; +- clocks = <&clks 10>, <&clks 21>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 21 3 0>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- uart3: serial@5000c000 { +- compatible = "fsl,imx31-uart", "fsl,imx21-uart"; +- reg = <0x5000c000 0x4000>; +- interrupts = <18>; +- clocks = <&clks 10>, <&clks 48>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- spi2: spi@50010000 { +- compatible = "fsl,imx31-cspi"; +- reg = <0x50010000 0x4000>; +- interrupts = <13>; +- clocks = <&clks 10>, <&clks 54>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 6 8 0>, <&sdma 7 8 0>; +- dma-names = "rx", "tx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- iim: efuse@5001c000 { +- compatible = "fsl,imx31-iim", "fsl,imx27-iim"; +- reg = <0x5001c000 0x1000>; +- interrupts = <19>; +- clocks = <&clks 25>; +- }; +- }; +- +- bus@53f00000 { /* AIPS2 */ +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x53f00000 0x100000>; +- ranges; +- +- clks: ccm@53f80000{ +- compatible = "fsl,imx31-ccm"; +- reg = <0x53f80000 0x4000>; +- interrupts = <31>, <53>; +- #clock-cells = <1>; +- }; +- +- spi3: spi@53f84000 { +- compatible = "fsl,imx31-cspi"; +- reg = <0x53f84000 0x4000>; +- interrupts = <17>; +- clocks = <&clks 10>, <&clks 28>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 10 8 0>, <&sdma 11 8 0>; +- dma-names = "rx", "tx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- gpt: timer@53f90000 { +- compatible = "fsl,imx31-gpt"; +- reg = <0x53f90000 0x4000>; +- interrupts = <29>; +- clocks = <&clks 10>, <&clks 22>; +- clock-names = "ipg", "per"; +- }; +- +- gpio3: gpio@53fa4000 { +- compatible = "fsl,imx31-gpio"; +- reg = <0x53fa4000 0x4000>; +- interrupts = <56>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- rng@53fb0000 { +- compatible = "fsl,imx31-rnga"; +- reg = <0x53fb0000 0x4000>; +- interrupts = <22>; +- clocks = <&clks 29>; +- }; +- +- gpio1: gpio@53fcc000 { +- compatible = "fsl,imx31-gpio"; +- reg = <0x53fcc000 0x4000>; +- interrupts = <52>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@53fd0000 { +- compatible = "fsl,imx31-gpio"; +- reg = <0x53fd0000 0x4000>; +- interrupts = <51>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- sdma: sdma@53fd4000 { +- compatible = "fsl,imx31-sdma"; +- reg = <0x53fd4000 0x4000>; +- interrupts = <34>; +- clocks = <&clks 10>, <&clks 27>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin"; +- }; +- +- rtc: rtc@53fd8000 { +- compatible = "fsl,imx31-rtc", "fsl,imx21-rtc"; +- reg = <0x53fd8000 0x4000>; +- interrupts = <25>; +- clocks = <&clks 2>, <&clks 40>; +- clock-names = "ref", "ipg"; +- }; +- +- wdog: watchdog@53fdc000 { +- compatible = "fsl,imx31-wdt", "fsl,imx21-wdt"; +- reg = <0x53fdc000 0x4000>; +- clocks = <&clks 41>; +- interrupts = <55>; +- }; +- +- pwm: pwm@53fe0000 { +- compatible = "fsl,imx31-pwm", "fsl,imx27-pwm"; +- reg = <0x53fe0000 0x4000>; +- interrupts = <26>; +- clocks = <&clks 10>, <&clks 42>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- }; +- +- emi@b8000000 { /* External Memory Interface */ +- compatible = "simple-bus"; +- reg = <0xb8000000 0x5000>; +- ranges; +- #address-cells = <1>; +- #size-cells = <1>; +- +- nfc: nand@b8000000 { +- compatible = "fsl,imx31-nand", "fsl,imx27-nand"; +- reg = <0xb8000000 0x1000>; +- interrupts = <33>; +- clocks = <&clks 9>; +- dmas = <&sdma 30 17 0>; +- dma-names = "rx-tx"; +- #address-cells = <1>; +- #size-cells = <1>; +- status = "disabled"; +- }; +- +- weim: weim@b8002000 { +- compatible = "fsl,imx31-weim", "fsl,imx27-weim"; +- reg = <0xb8002000 0x1000>; +- clocks = <&clks 56>; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0 0xa0000000 0x08000000 +- 1 0 0xa8000000 0x08000000 +- 2 0 0xb0000000 0x02000000 +- 3 0 0xb2000000 0x02000000 +- 4 0 0xb4000000 0x02000000 +- 5 0 0xb6000000 0x02000000>; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx35-eukrea-cpuimx35.dtsi b/scripts/dtc/include-prefixes/arm/imx35-eukrea-cpuimx35.dtsi +deleted file mode 100644 +index 17bd2a97609a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx35-eukrea-cpuimx35.dtsi ++++ /dev/null +@@ -1,89 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Eukréa Electromatique +- */ +- +-#include "imx35.dtsi" +- +-/ { +- model = "Eukrea CPUIMX35"; +- compatible = "eukrea,cpuimx35", "fsl,imx35"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x8000000>; /* 128M */ +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pcf8563@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- +- tsc2007: tsc2007@48 { +- compatible = "ti,tsc2007"; +- gpios = <&gpio3 2 0>; +- interrupt-parent = <&gpio3>; +- interrupts = <0x2 0x8>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tsc2007_1>; +- reg = <0x48>; +- ti,x-plate-ohms = <180>; +- }; +-}; +- +-&iomuxc { +- imx35-eukrea { +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 +- MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x80000000 +- MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 +- MX35_PAD_FEC_COL__FEC_COL 0x80000000 +- MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x80000000 +- MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x80000000 +- MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 +- MX35_PAD_FEC_MDC__FEC_MDC 0x80000000 +- MX35_PAD_FEC_MDIO__FEC_MDIO 0x80000000 +- MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x80000000 +- MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x80000000 +- MX35_PAD_FEC_CRS__FEC_CRS 0x80000000 +- MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x80000000 +- MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x80000000 +- MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x80000000 +- MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x80000000 +- MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x80000000 +- MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x80000000 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000 +- MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000 +- >; +- }; +- +- pinctrl_tsc2007_1: tsc2007grp-1 { +- fsl,pins = ; +- }; +- }; +-}; +- +-&nfc { +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-on-flash-bbt; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx35-eukrea-mbimxsd35-baseboard.dts b/scripts/dtc/include-prefixes/arm/imx35-eukrea-mbimxsd35-baseboard.dts +deleted file mode 100644 +index b1c11170ac25..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx35-eukrea-mbimxsd35-baseboard.dts ++++ /dev/null +@@ -1,156 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Eukréa Electromatique +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "imx35-eukrea-cpuimx35.dtsi" +- +-/ { +- model = "Eukrea CPUIMX35"; +- compatible = "eukrea,mbimxsd35-baseboard", "eukrea,cpuimx35", "fsl,imx35"; +- +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_bp1>; +- +- bp1 { +- label = "BP1"; +- gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- linux,input-type = <1>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led1>; +- +- led1 { +- label = "led1"; +- gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- sound { +- compatible = "eukrea,asoc-tlv320"; +- eukrea,model = "imx35-eukrea-tlv320aic23"; +- ssi-controller = <&ssi1>; +- fsl,mux-int-port = <1>; +- fsl,mux-ext-port = <4>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- cd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&i2c1 { +- tlv320aic23: codec@1a { +- compatible = "ti,tlv320aic23"; +- reg = <0x1a>; +- }; +-}; +- +-&iomuxc { +- imx35-eukrea { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x80000000 +- MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x80000000 +- MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x80000000 +- MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x80000000 +- >; +- }; +- +- pinctrl_bp1: bp1grp { +- fsl,pins = ; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 +- MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 +- MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 +- MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 +- MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 +- MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 +- MX35_PAD_LD18__GPIO3_24 0x80000000 /* CD */ +- >; +- }; +- +- pinctrl_led1: led1grp { +- fsl,pins = ; +- }; +- +- pinctrl_reg_lcd_3v3: reg-lcd-3v3 { +- fsl,pins = ; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 +- MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 +- MX35_PAD_CTS1__UART1_CTS 0x1c5 +- MX35_PAD_RTS1__UART1_RTS 0x1c5 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX35_PAD_RXD2__UART2_RXD_MUX 0x1c5 +- MX35_PAD_TXD2__UART2_TXD_MUX 0x1c5 +- MX35_PAD_RTS2__UART2_RTS 0x1c5 +- MX35_PAD_CTS2__UART2_CTS 0x1c5 +- >; +- }; +- }; +-}; +- +-&ssi1 { +- codec-handle = <&tlv320aic23>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbhost1 { +- phy_type = "serial"; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbotg { +- phy_type = "utmi"; +- dr_mode = "otg"; +- external-vbus-divider; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx35-pdk.dts b/scripts/dtc/include-prefixes/arm/imx35-pdk.dts +deleted file mode 100644 +index ddce0a844758..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx35-pdk.dts ++++ /dev/null +@@ -1,62 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2013 Eukréa Electromatique +-// Copyright 2014 Freescale Semiconductor, Inc. +- +-/dts-v1/; +-#include "imx35.dtsi" +- +-/ { +- model = "Freescale i.MX35 Product Development Kit"; +- compatible = "fsl,imx35-pdk", "fsl,imx35"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x8000000>, +- <0x90000000 0x8000000>; +- }; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- status = "okay"; +-}; +- +-&iomuxc { +- imx35-pdk { +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 +- MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 +- MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 +- MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 +- MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 +- MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 +- MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 +- MX35_PAD_CTS1__UART1_CTS 0x1c5 +- MX35_PAD_RTS1__UART1_RTS 0x1c5 +- >; +- }; +- }; +-}; +- +-&nfc { +- nand-bus-width = <16>; +- nand-ecc-mode = "hw"; +- nand-on-flash-bbt; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx35-pinfunc.h b/scripts/dtc/include-prefixes/arm/imx35-pinfunc.h +deleted file mode 100644 +index 9d6cc9564b72..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx35-pinfunc.h ++++ /dev/null +@@ -1,966 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __DTS_IMX35_PINFUNC_H +-#define __DTS_IMX35_PINFUNC_H +- +-/* +- * The pin function ID is a tuple of +- * +- */ +-#define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0 +-#define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0 +-#define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0 +-#define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0 +-#define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0 +-#define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0 +-#define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0 +-#define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0 +-#define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0 +-#define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0 +-#define MX35_PAD_COMPARE__GPIO1_5 0x008 0x32c 0x854 0x5 0x0 +-#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 0x008 0x32c 0x000 0x7 0x0 +-#define MX35_PAD_WDOG_RST__WDOG_WDOG_B 0x00c 0x330 0x000 0x0 0x0 +-#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE 0x00c 0x330 0x000 0x3 0x0 +-#define MX35_PAD_WDOG_RST__GPIO1_6 0x00c 0x330 0x858 0x5 0x0 +-#define MX35_PAD_GPIO1_0__GPIO1_0 0x010 0x334 0x82c 0x0 0x0 +-#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY 0x010 0x334 0x7d4 0x1 0x0 +-#define MX35_PAD_GPIO1_0__OWIRE_LINE 0x010 0x334 0x990 0x2 0x0 +-#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 0x010 0x334 0x000 0x7 0x0 +-#define MX35_PAD_GPIO1_1__GPIO1_1 0x014 0x338 0x838 0x0 0x0 +-#define MX35_PAD_GPIO1_1__PWM_PWMO 0x014 0x338 0x000 0x2 0x0 +-#define MX35_PAD_GPIO1_1__CSPI1_SS2 0x014 0x338 0x7d8 0x3 0x0 +-#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT 0x014 0x338 0x000 0x6 0x0 +-#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 0x014 0x338 0x000 0x7 0x0 +-#define MX35_PAD_GPIO2_0__GPIO2_0 0x018 0x33c 0x868 0x0 0x0 +-#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK 0x018 0x33c 0x000 0x1 0x0 +-#define MX35_PAD_GPIO3_0__GPIO3_0 0x01c 0x340 0x8e8 0x0 0x0 +-#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK 0x01c 0x340 0x000 0x1 0x0 +-#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B 0x000 0x344 0x000 0x0 0x0 +-#define MX35_PAD_POR_B__CCM_POR_B 0x000 0x348 0x000 0x0 0x0 +-#define MX35_PAD_CLKO__CCM_CLKO 0x020 0x34c 0x000 0x0 0x0 +-#define MX35_PAD_CLKO__GPIO1_8 0x020 0x34c 0x860 0x5 0x0 +-#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 0x000 0x350 0x000 0x0 0x0 +-#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 0x000 0x354 0x000 0x0 0x0 +-#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 0x000 0x358 0x000 0x0 0x0 +-#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 0x000 0x35c 0x000 0x0 0x0 +-#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 0x000 0x360 0x000 0x0 0x0 +-#define MX35_PAD_VSTBY__CCM_VSTBY 0x024 0x364 0x000 0x0 0x0 +-#define MX35_PAD_VSTBY__GPIO1_7 0x024 0x364 0x85c 0x5 0x0 +-#define MX35_PAD_A0__EMI_EIM_DA_L_0 0x028 0x368 0x000 0x0 0x0 +-#define MX35_PAD_A1__EMI_EIM_DA_L_1 0x02c 0x36c 0x000 0x0 0x0 +-#define MX35_PAD_A2__EMI_EIM_DA_L_2 0x030 0x370 0x000 0x0 0x0 +-#define MX35_PAD_A3__EMI_EIM_DA_L_3 0x034 0x374 0x000 0x0 0x0 +-#define MX35_PAD_A4__EMI_EIM_DA_L_4 0x038 0x378 0x000 0x0 0x0 +-#define MX35_PAD_A5__EMI_EIM_DA_L_5 0x03c 0x37c 0x000 0x0 0x0 +-#define MX35_PAD_A6__EMI_EIM_DA_L_6 0x040 0x380 0x000 0x0 0x0 +-#define MX35_PAD_A7__EMI_EIM_DA_L_7 0x044 0x384 0x000 0x0 0x0 +-#define MX35_PAD_A8__EMI_EIM_DA_H_8 0x048 0x388 0x000 0x0 0x0 +-#define MX35_PAD_A9__EMI_EIM_DA_H_9 0x04c 0x38c 0x000 0x0 0x0 +-#define MX35_PAD_A10__EMI_EIM_DA_H_10 0x050 0x390 0x000 0x0 0x0 +-#define MX35_PAD_MA10__EMI_MA10 0x054 0x394 0x000 0x0 0x0 +-#define MX35_PAD_A11__EMI_EIM_DA_H_11 0x058 0x398 0x000 0x0 0x0 +-#define MX35_PAD_A12__EMI_EIM_DA_H_12 0x05c 0x39c 0x000 0x0 0x0 +-#define MX35_PAD_A13__EMI_EIM_DA_H_13 0x060 0x3a0 0x000 0x0 0x0 +-#define MX35_PAD_A14__EMI_EIM_DA_H2_14 0x064 0x3a4 0x000 0x0 0x0 +-#define MX35_PAD_A15__EMI_EIM_DA_H2_15 0x068 0x3a8 0x000 0x0 0x0 +-#define MX35_PAD_A16__EMI_EIM_A_16 0x06c 0x3ac 0x000 0x0 0x0 +-#define MX35_PAD_A17__EMI_EIM_A_17 0x070 0x3b0 0x000 0x0 0x0 +-#define MX35_PAD_A18__EMI_EIM_A_18 0x074 0x3b4 0x000 0x0 0x0 +-#define MX35_PAD_A19__EMI_EIM_A_19 0x078 0x3b8 0x000 0x0 0x0 +-#define MX35_PAD_A20__EMI_EIM_A_20 0x07c 0x3bc 0x000 0x0 0x0 +-#define MX35_PAD_A21__EMI_EIM_A_21 0x080 0x3c0 0x000 0x0 0x0 +-#define MX35_PAD_A22__EMI_EIM_A_22 0x084 0x3c4 0x000 0x0 0x0 +-#define MX35_PAD_A23__EMI_EIM_A_23 0x088 0x3c8 0x000 0x0 0x0 +-#define MX35_PAD_A24__EMI_EIM_A_24 0x08c 0x3cc 0x000 0x0 0x0 +-#define MX35_PAD_A25__EMI_EIM_A_25 0x090 0x3d0 0x000 0x0 0x0 +-#define MX35_PAD_SDBA1__EMI_EIM_SDBA1 0x000 0x3d4 0x000 0x0 0x0 +-#define MX35_PAD_SDBA0__EMI_EIM_SDBA0 0x000 0x3d8 0x000 0x0 0x0 +-#define MX35_PAD_SD0__EMI_DRAM_D_0 0x000 0x3dc 0x000 0x0 0x0 +-#define MX35_PAD_SD1__EMI_DRAM_D_1 0x000 0x3e0 0x000 0x0 0x0 +-#define MX35_PAD_SD2__EMI_DRAM_D_2 0x000 0x3e4 0x000 0x0 0x0 +-#define MX35_PAD_SD3__EMI_DRAM_D_3 0x000 0x3e8 0x000 0x0 0x0 +-#define MX35_PAD_SD4__EMI_DRAM_D_4 0x000 0x3ec 0x000 0x0 0x0 +-#define MX35_PAD_SD5__EMI_DRAM_D_5 0x000 0x3f0 0x000 0x0 0x0 +-#define MX35_PAD_SD6__EMI_DRAM_D_6 0x000 0x3f4 0x000 0x0 0x0 +-#define MX35_PAD_SD7__EMI_DRAM_D_7 0x000 0x3f8 0x000 0x0 0x0 +-#define MX35_PAD_SD8__EMI_DRAM_D_8 0x000 0x3fc 0x000 0x0 0x0 +-#define MX35_PAD_SD9__EMI_DRAM_D_9 0x000 0x400 0x000 0x0 0x0 +-#define MX35_PAD_SD10__EMI_DRAM_D_10 0x000 0x404 0x000 0x0 0x0 +-#define MX35_PAD_SD11__EMI_DRAM_D_11 0x000 0x408 0x000 0x0 0x0 +-#define MX35_PAD_SD12__EMI_DRAM_D_12 0x000 0x40c 0x000 0x0 0x0 +-#define MX35_PAD_SD13__EMI_DRAM_D_13 0x000 0x410 0x000 0x0 0x0 +-#define MX35_PAD_SD14__EMI_DRAM_D_14 0x000 0x414 0x000 0x0 0x0 +-#define MX35_PAD_SD15__EMI_DRAM_D_15 0x000 0x418 0x000 0x0 0x0 +-#define MX35_PAD_SD16__EMI_DRAM_D_16 0x000 0x41c 0x000 0x0 0x0 +-#define MX35_PAD_SD17__EMI_DRAM_D_17 0x000 0x420 0x000 0x0 0x0 +-#define MX35_PAD_SD18__EMI_DRAM_D_18 0x000 0x424 0x000 0x0 0x0 +-#define MX35_PAD_SD19__EMI_DRAM_D_19 0x000 0x428 0x000 0x0 0x0 +-#define MX35_PAD_SD20__EMI_DRAM_D_20 0x000 0x42c 0x000 0x0 0x0 +-#define MX35_PAD_SD21__EMI_DRAM_D_21 0x000 0x430 0x000 0x0 0x0 +-#define MX35_PAD_SD22__EMI_DRAM_D_22 0x000 0x434 0x000 0x0 0x0 +-#define MX35_PAD_SD23__EMI_DRAM_D_23 0x000 0x438 0x000 0x0 0x0 +-#define MX35_PAD_SD24__EMI_DRAM_D_24 0x000 0x43c 0x000 0x0 0x0 +-#define MX35_PAD_SD25__EMI_DRAM_D_25 0x000 0x440 0x000 0x0 0x0 +-#define MX35_PAD_SD26__EMI_DRAM_D_26 0x000 0x444 0x000 0x0 0x0 +-#define MX35_PAD_SD27__EMI_DRAM_D_27 0x000 0x448 0x000 0x0 0x0 +-#define MX35_PAD_SD28__EMI_DRAM_D_28 0x000 0x44c 0x000 0x0 0x0 +-#define MX35_PAD_SD29__EMI_DRAM_D_29 0x000 0x450 0x000 0x0 0x0 +-#define MX35_PAD_SD30__EMI_DRAM_D_30 0x000 0x454 0x000 0x0 0x0 +-#define MX35_PAD_SD31__EMI_DRAM_D_31 0x000 0x458 0x000 0x0 0x0 +-#define MX35_PAD_DQM0__EMI_DRAM_DQM_0 0x000 0x45c 0x000 0x0 0x0 +-#define MX35_PAD_DQM1__EMI_DRAM_DQM_1 0x000 0x460 0x000 0x0 0x0 +-#define MX35_PAD_DQM2__EMI_DRAM_DQM_2 0x000 0x464 0x000 0x0 0x0 +-#define MX35_PAD_DQM3__EMI_DRAM_DQM_3 0x000 0x468 0x000 0x0 0x0 +-#define MX35_PAD_EB0__EMI_EIM_EB0_B 0x094 0x46c 0x000 0x0 0x0 +-#define MX35_PAD_EB1__EMI_EIM_EB1_B 0x098 0x470 0x000 0x0 0x0 +-#define MX35_PAD_OE__EMI_EIM_OE 0x09c 0x474 0x000 0x0 0x0 +-#define MX35_PAD_CS0__EMI_EIM_CS0 0x0a0 0x478 0x000 0x0 0x0 +-#define MX35_PAD_CS1__EMI_EIM_CS1 0x0a4 0x47c 0x000 0x0 0x0 +-#define MX35_PAD_CS1__EMI_NANDF_CE3 0x0a4 0x47c 0x000 0x3 0x0 +-#define MX35_PAD_CS2__EMI_EIM_CS2 0x0a8 0x480 0x000 0x0 0x0 +-#define MX35_PAD_CS3__EMI_EIM_CS3 0x0ac 0x484 0x000 0x0 0x0 +-#define MX35_PAD_CS4__EMI_EIM_CS4 0x0b0 0x488 0x000 0x0 0x0 +-#define MX35_PAD_CS4__EMI_DTACK_B 0x0b0 0x488 0x800 0x1 0x0 +-#define MX35_PAD_CS4__EMI_NANDF_CE1 0x0b0 0x488 0x000 0x3 0x0 +-#define MX35_PAD_CS4__GPIO1_20 0x0b0 0x488 0x83c 0x5 0x0 +-#define MX35_PAD_CS5__EMI_EIM_CS5 0x0b4 0x48c 0x000 0x0 0x0 +-#define MX35_PAD_CS5__CSPI2_SS2 0x0b4 0x48c 0x7f8 0x1 0x0 +-#define MX35_PAD_CS5__CSPI1_SS2 0x0b4 0x48c 0x7d8 0x2 0x1 +-#define MX35_PAD_CS5__EMI_NANDF_CE2 0x0b4 0x48c 0x000 0x3 0x0 +-#define MX35_PAD_CS5__GPIO1_21 0x0b4 0x48c 0x840 0x5 0x0 +-#define MX35_PAD_NF_CE0__EMI_NANDF_CE0 0x0b8 0x490 0x000 0x0 0x0 +-#define MX35_PAD_NF_CE0__GPIO1_22 0x0b8 0x490 0x844 0x5 0x0 +-#define MX35_PAD_ECB__EMI_EIM_ECB 0x000 0x494 0x000 0x0 0x0 +-#define MX35_PAD_LBA__EMI_EIM_LBA 0x0bc 0x498 0x000 0x0 0x0 +-#define MX35_PAD_BCLK__EMI_EIM_BCLK 0x0c0 0x49c 0x000 0x0 0x0 +-#define MX35_PAD_RW__EMI_EIM_RW 0x0c4 0x4a0 0x000 0x0 0x0 +-#define MX35_PAD_RAS__EMI_DRAM_RAS 0x000 0x4a4 0x000 0x0 0x0 +-#define MX35_PAD_CAS__EMI_DRAM_CAS 0x000 0x4a8 0x000 0x0 0x0 +-#define MX35_PAD_SDWE__EMI_DRAM_SDWE 0x000 0x4ac 0x000 0x0 0x0 +-#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 0x000 0x4b0 0x000 0x0 0x0 +-#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 0x000 0x4b4 0x000 0x0 0x0 +-#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK 0x000 0x4b8 0x000 0x0 0x0 +-#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 0x000 0x4bc 0x000 0x0 0x0 +-#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 0x000 0x4c0 0x000 0x0 0x0 +-#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 0x000 0x4c4 0x000 0x0 0x0 +-#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 0x000 0x4c8 0x000 0x0 0x0 +-#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B 0x0c8 0x4cc 0x000 0x0 0x0 +-#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 0x0c8 0x4cc 0x9d8 0x1 0x0 +-#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC 0x0c8 0x4cc 0x924 0x2 0x0 +-#define MX35_PAD_NFWE_B__GPIO2_18 0x0c8 0x4cc 0x88c 0x5 0x0 +-#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 0x0c8 0x4cc 0x000 0x7 0x0 +-#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B 0x0cc 0x4d0 0x000 0x0 0x0 +-#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR 0x0cc 0x4d0 0x9ec 0x1 0x0 +-#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK 0x0cc 0x4d0 0x000 0x2 0x0 +-#define MX35_PAD_NFRE_B__GPIO2_19 0x0cc 0x4d0 0x890 0x5 0x0 +-#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 0x0cc 0x4d0 0x000 0x7 0x0 +-#define MX35_PAD_NFALE__EMI_NANDF_ALE 0x0d0 0x4d4 0x000 0x0 0x0 +-#define MX35_PAD_NFALE__USB_TOP_USBH2_STP 0x0d0 0x4d4 0x000 0x1 0x0 +-#define MX35_PAD_NFALE__IPU_DISPB_CS0 0x0d0 0x4d4 0x000 0x2 0x0 +-#define MX35_PAD_NFALE__GPIO2_20 0x0d0 0x4d4 0x898 0x5 0x0 +-#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 0x0d0 0x4d4 0x000 0x7 0x0 +-#define MX35_PAD_NFCLE__EMI_NANDF_CLE 0x0d4 0x4d8 0x000 0x0 0x0 +-#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT 0x0d4 0x4d8 0x9f0 0x1 0x0 +-#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS 0x0d4 0x4d8 0x000 0x2 0x0 +-#define MX35_PAD_NFCLE__GPIO2_21 0x0d4 0x4d8 0x89c 0x5 0x0 +-#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 0x0d4 0x4d8 0x000 0x7 0x0 +-#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B 0x0d8 0x4dc 0x000 0x0 0x0 +-#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 0x0d8 0x4dc 0x9e8 0x1 0x0 +-#define MX35_PAD_NFWP_B__IPU_DISPB_WR 0x0d8 0x4dc 0x000 0x2 0x0 +-#define MX35_PAD_NFWP_B__GPIO2_22 0x0d8 0x4dc 0x8a0 0x5 0x0 +-#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL 0x0d8 0x4dc 0x000 0x7 0x0 +-#define MX35_PAD_NFRB__EMI_NANDF_RB 0x0dc 0x4e0 0x000 0x0 0x0 +-#define MX35_PAD_NFRB__IPU_DISPB_RD 0x0dc 0x4e0 0x000 0x2 0x0 +-#define MX35_PAD_NFRB__GPIO2_23 0x0dc 0x4e0 0x8a4 0x5 0x0 +-#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK 0x0dc 0x4e0 0x000 0x7 0x0 +-#define MX35_PAD_D15__EMI_EIM_D_15 0x000 0x4e4 0x000 0x0 0x0 +-#define MX35_PAD_D14__EMI_EIM_D_14 0x000 0x4e8 0x000 0x0 0x0 +-#define MX35_PAD_D13__EMI_EIM_D_13 0x000 0x4ec 0x000 0x0 0x0 +-#define MX35_PAD_D12__EMI_EIM_D_12 0x000 0x4f0 0x000 0x0 0x0 +-#define MX35_PAD_D11__EMI_EIM_D_11 0x000 0x4f4 0x000 0x0 0x0 +-#define MX35_PAD_D10__EMI_EIM_D_10 0x000 0x4f8 0x000 0x0 0x0 +-#define MX35_PAD_D9__EMI_EIM_D_9 0x000 0x4fc 0x000 0x0 0x0 +-#define MX35_PAD_D8__EMI_EIM_D_8 0x000 0x500 0x000 0x0 0x0 +-#define MX35_PAD_D7__EMI_EIM_D_7 0x000 0x504 0x000 0x0 0x0 +-#define MX35_PAD_D6__EMI_EIM_D_6 0x000 0x508 0x000 0x0 0x0 +-#define MX35_PAD_D5__EMI_EIM_D_5 0x000 0x50c 0x000 0x0 0x0 +-#define MX35_PAD_D4__EMI_EIM_D_4 0x000 0x510 0x000 0x0 0x0 +-#define MX35_PAD_D3__EMI_EIM_D_3 0x000 0x514 0x000 0x0 0x0 +-#define MX35_PAD_D2__EMI_EIM_D_2 0x000 0x518 0x000 0x0 0x0 +-#define MX35_PAD_D1__EMI_EIM_D_1 0x000 0x51c 0x000 0x0 0x0 +-#define MX35_PAD_D0__EMI_EIM_D_0 0x000 0x520 0x000 0x0 0x0 +-#define MX35_PAD_CSI_D8__IPU_CSI_D_8 0x0e0 0x524 0x000 0x0 0x0 +-#define MX35_PAD_CSI_D8__KPP_COL_0 0x0e0 0x524 0x950 0x1 0x0 +-#define MX35_PAD_CSI_D8__GPIO1_20 0x0e0 0x524 0x83c 0x5 0x1 +-#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 0x0e0 0x524 0x000 0x7 0x0 +-#define MX35_PAD_CSI_D9__IPU_CSI_D_9 0x0e4 0x528 0x000 0x0 0x0 +-#define MX35_PAD_CSI_D9__KPP_COL_1 0x0e4 0x528 0x954 0x1 0x0 +-#define MX35_PAD_CSI_D9__GPIO1_21 0x0e4 0x528 0x840 0x5 0x1 +-#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 0x0e4 0x528 0x000 0x7 0x0 +-#define MX35_PAD_CSI_D10__IPU_CSI_D_10 0x0e8 0x52c 0x000 0x0 0x0 +-#define MX35_PAD_CSI_D10__KPP_COL_2 0x0e8 0x52c 0x958 0x1 0x0 +-#define MX35_PAD_CSI_D10__GPIO1_22 0x0e8 0x52c 0x844 0x5 0x1 +-#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 0x0e8 0x52c 0x000 0x7 0x0 +-#define MX35_PAD_CSI_D11__IPU_CSI_D_11 0x0ec 0x530 0x000 0x0 0x0 +-#define MX35_PAD_CSI_D11__KPP_COL_3 0x0ec 0x530 0x95c 0x1 0x0 +-#define MX35_PAD_CSI_D11__GPIO1_23 0x0ec 0x530 0x000 0x5 0x0 +-#define MX35_PAD_CSI_D12__IPU_CSI_D_12 0x0f0 0x534 0x000 0x0 0x0 +-#define MX35_PAD_CSI_D12__KPP_ROW_0 0x0f0 0x534 0x970 0x1 0x0 +-#define MX35_PAD_CSI_D12__GPIO1_24 0x0f0 0x534 0x000 0x5 0x0 +-#define MX35_PAD_CSI_D13__IPU_CSI_D_13 0x0f4 0x538 0x000 0x0 0x0 +-#define MX35_PAD_CSI_D13__KPP_ROW_1 0x0f4 0x538 0x974 0x1 0x0 +-#define MX35_PAD_CSI_D13__GPIO1_25 0x0f4 0x538 0x000 0x5 0x0 +-#define MX35_PAD_CSI_D14__IPU_CSI_D_14 0x0f8 0x53c 0x000 0x0 0x0 +-#define MX35_PAD_CSI_D14__KPP_ROW_2 0x0f8 0x53c 0x978 0x1 0x0 +-#define MX35_PAD_CSI_D14__GPIO1_26 0x0f8 0x53c 0x000 0x5 0x0 +-#define MX35_PAD_CSI_D15__IPU_CSI_D_15 0x0fc 0x540 0x97c 0x0 0x0 +-#define MX35_PAD_CSI_D15__KPP_ROW_3 0x0fc 0x540 0x000 0x1 0x0 +-#define MX35_PAD_CSI_D15__GPIO1_27 0x0fc 0x540 0x000 0x5 0x0 +-#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK 0x100 0x544 0x000 0x0 0x0 +-#define MX35_PAD_CSI_MCLK__GPIO1_28 0x100 0x544 0x000 0x5 0x0 +-#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC 0x104 0x548 0x000 0x0 0x0 +-#define MX35_PAD_CSI_VSYNC__GPIO1_29 0x104 0x548 0x000 0x5 0x0 +-#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC 0x108 0x54c 0x000 0x0 0x0 +-#define MX35_PAD_CSI_HSYNC__GPIO1_30 0x108 0x54c 0x000 0x5 0x0 +-#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK 0x10c 0x550 0x000 0x0 0x0 +-#define MX35_PAD_CSI_PIXCLK__GPIO1_31 0x10c 0x550 0x000 0x5 0x0 +-#define MX35_PAD_I2C1_CLK__I2C1_SCL 0x110 0x554 0x000 0x0 0x0 +-#define MX35_PAD_I2C1_CLK__GPIO2_24 0x110 0x554 0x8a8 0x5 0x0 +-#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK 0x110 0x554 0x000 0x6 0x0 +-#define MX35_PAD_I2C1_DAT__I2C1_SDA 0x114 0x558 0x000 0x0 0x0 +-#define MX35_PAD_I2C1_DAT__GPIO2_25 0x114 0x558 0x8ac 0x5 0x0 +-#define MX35_PAD_I2C2_CLK__I2C2_SCL 0x118 0x55c 0x000 0x0 0x0 +-#define MX35_PAD_I2C2_CLK__CAN1_TXCAN 0x118 0x55c 0x000 0x1 0x0 +-#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR 0x118 0x55c 0x000 0x2 0x0 +-#define MX35_PAD_I2C2_CLK__GPIO2_26 0x118 0x55c 0x8b0 0x5 0x0 +-#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 0x118 0x55c 0x000 0x6 0x0 +-#define MX35_PAD_I2C2_DAT__I2C2_SDA 0x11c 0x560 0x000 0x0 0x0 +-#define MX35_PAD_I2C2_DAT__CAN1_RXCAN 0x11c 0x560 0x7c8 0x1 0x0 +-#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC 0x11c 0x560 0x9f4 0x2 0x0 +-#define MX35_PAD_I2C2_DAT__GPIO2_27 0x11c 0x560 0x8b4 0x5 0x0 +-#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 0x11c 0x560 0x000 0x6 0x0 +-#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x120 0x564 0x000 0x0 0x0 +-#define MX35_PAD_STXD4__GPIO2_28 0x120 0x564 0x8b8 0x5 0x0 +-#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 0x120 0x564 0x000 0x7 0x0 +-#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x124 0x568 0x000 0x0 0x0 +-#define MX35_PAD_SRXD4__GPIO2_29 0x124 0x568 0x8bc 0x5 0x0 +-#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 0x124 0x568 0x000 0x7 0x0 +-#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x128 0x56c 0x000 0x0 0x0 +-#define MX35_PAD_SCK4__GPIO2_30 0x128 0x56c 0x8c4 0x5 0x0 +-#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 0x128 0x56c 0x000 0x7 0x0 +-#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x12c 0x570 0x000 0x0 0x0 +-#define MX35_PAD_STXFS4__GPIO2_31 0x12c 0x570 0x8c8 0x5 0x0 +-#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 0x12c 0x570 0x000 0x7 0x0 +-#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD 0x130 0x574 0x000 0x0 0x0 +-#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 0x130 0x574 0x000 0x1 0x0 +-#define MX35_PAD_STXD5__CSPI2_MOSI 0x130 0x574 0x7ec 0x2 0x0 +-#define MX35_PAD_STXD5__GPIO1_0 0x130 0x574 0x82c 0x5 0x1 +-#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 0x130 0x574 0x000 0x7 0x0 +-#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD 0x134 0x578 0x000 0x0 0x0 +-#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 0x134 0x578 0x998 0x1 0x0 +-#define MX35_PAD_SRXD5__CSPI2_MISO 0x134 0x578 0x7e8 0x2 0x0 +-#define MX35_PAD_SRXD5__GPIO1_1 0x134 0x578 0x838 0x5 0x1 +-#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 0x134 0x578 0x000 0x7 0x0 +-#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC 0x138 0x57c 0x000 0x0 0x0 +-#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK 0x138 0x57c 0x994 0x1 0x0 +-#define MX35_PAD_SCK5__CSPI2_SCLK 0x138 0x57c 0x7e0 0x2 0x0 +-#define MX35_PAD_SCK5__GPIO1_2 0x138 0x57c 0x848 0x5 0x0 +-#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 0x138 0x57c 0x000 0x7 0x0 +-#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS 0x13c 0x580 0x000 0x0 0x0 +-#define MX35_PAD_STXFS5__CSPI2_RDY 0x13c 0x580 0x7e4 0x2 0x0 +-#define MX35_PAD_STXFS5__GPIO1_3 0x13c 0x580 0x84c 0x5 0x0 +-#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 0x13c 0x580 0x000 0x7 0x0 +-#define MX35_PAD_SCKR__ESAI_SCKR 0x140 0x584 0x000 0x0 0x0 +-#define MX35_PAD_SCKR__GPIO1_4 0x140 0x584 0x850 0x5 0x1 +-#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 0x140 0x584 0x000 0x7 0x0 +-#define MX35_PAD_FSR__ESAI_FSR 0x144 0x588 0x000 0x0 0x0 +-#define MX35_PAD_FSR__GPIO1_5 0x144 0x588 0x854 0x5 0x1 +-#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 0x144 0x588 0x000 0x7 0x0 +-#define MX35_PAD_HCKR__ESAI_HCKR 0x148 0x58c 0x000 0x0 0x0 +-#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS 0x148 0x58c 0x000 0x1 0x0 +-#define MX35_PAD_HCKR__CSPI2_SS0 0x148 0x58c 0x7f0 0x2 0x0 +-#define MX35_PAD_HCKR__IPU_FLASH_STROBE 0x148 0x58c 0x000 0x3 0x0 +-#define MX35_PAD_HCKR__GPIO1_6 0x148 0x58c 0x858 0x5 0x1 +-#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 0x148 0x58c 0x000 0x7 0x0 +-#define MX35_PAD_SCKT__ESAI_SCKT 0x14c 0x590 0x000 0x0 0x0 +-#define MX35_PAD_SCKT__GPIO1_7 0x14c 0x590 0x85c 0x5 0x1 +-#define MX35_PAD_SCKT__IPU_CSI_D_0 0x14c 0x590 0x930 0x6 0x0 +-#define MX35_PAD_SCKT__KPP_ROW_2 0x14c 0x590 0x978 0x7 0x1 +-#define MX35_PAD_FST__ESAI_FST 0x150 0x594 0x000 0x0 0x0 +-#define MX35_PAD_FST__GPIO1_8 0x150 0x594 0x860 0x5 0x1 +-#define MX35_PAD_FST__IPU_CSI_D_1 0x150 0x594 0x934 0x6 0x0 +-#define MX35_PAD_FST__KPP_ROW_3 0x150 0x594 0x97c 0x7 0x1 +-#define MX35_PAD_HCKT__ESAI_HCKT 0x154 0x598 0x000 0x0 0x0 +-#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC 0x154 0x598 0x7a8 0x1 0x0 +-#define MX35_PAD_HCKT__GPIO1_9 0x154 0x598 0x864 0x5 0x0 +-#define MX35_PAD_HCKT__IPU_CSI_D_2 0x154 0x598 0x938 0x6 0x0 +-#define MX35_PAD_HCKT__KPP_COL_3 0x154 0x598 0x95c 0x7 0x1 +-#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0 0x158 0x59c 0x000 0x0 0x0 +-#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC 0x158 0x59c 0x000 0x1 0x0 +-#define MX35_PAD_TX5_RX0__CSPI2_SS2 0x158 0x59c 0x7f8 0x2 0x1 +-#define MX35_PAD_TX5_RX0__CAN2_TXCAN 0x158 0x59c 0x000 0x3 0x0 +-#define MX35_PAD_TX5_RX0__UART2_DTR 0x158 0x59c 0x000 0x4 0x0 +-#define MX35_PAD_TX5_RX0__GPIO1_10 0x158 0x59c 0x830 0x5 0x0 +-#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 0x158 0x59c 0x000 0x7 0x0 +-#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1 0x15c 0x5a0 0x000 0x0 0x0 +-#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS 0x15c 0x5a0 0x000 0x1 0x0 +-#define MX35_PAD_TX4_RX1__CSPI2_SS3 0x15c 0x5a0 0x7fc 0x2 0x0 +-#define MX35_PAD_TX4_RX1__CAN2_RXCAN 0x15c 0x5a0 0x7cc 0x3 0x0 +-#define MX35_PAD_TX4_RX1__UART2_DSR 0x15c 0x5a0 0x000 0x4 0x0 +-#define MX35_PAD_TX4_RX1__GPIO1_11 0x15c 0x5a0 0x834 0x5 0x0 +-#define MX35_PAD_TX4_RX1__IPU_CSI_D_3 0x15c 0x5a0 0x93c 0x6 0x0 +-#define MX35_PAD_TX4_RX1__KPP_ROW_0 0x15c 0x5a0 0x970 0x7 0x1 +-#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2 0x160 0x5a4 0x000 0x0 0x0 +-#define MX35_PAD_TX3_RX2__I2C3_SCL 0x160 0x5a4 0x91c 0x1 0x0 +-#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1 0x160 0x5a4 0x000 0x3 0x0 +-#define MX35_PAD_TX3_RX2__GPIO1_12 0x160 0x5a4 0x000 0x5 0x0 +-#define MX35_PAD_TX3_RX2__IPU_CSI_D_4 0x160 0x5a4 0x940 0x6 0x0 +-#define MX35_PAD_TX3_RX2__KPP_ROW_1 0x160 0x5a4 0x974 0x7 0x1 +-#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3 0x164 0x5a8 0x000 0x0 0x0 +-#define MX35_PAD_TX2_RX3__I2C3_SDA 0x164 0x5a8 0x920 0x1 0x0 +-#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2 0x164 0x5a8 0x000 0x3 0x0 +-#define MX35_PAD_TX2_RX3__GPIO1_13 0x164 0x5a8 0x000 0x5 0x0 +-#define MX35_PAD_TX2_RX3__IPU_CSI_D_5 0x164 0x5a8 0x944 0x6 0x0 +-#define MX35_PAD_TX2_RX3__KPP_COL_0 0x164 0x5a8 0x950 0x7 0x1 +-#define MX35_PAD_TX1__ESAI_TX1 0x168 0x5ac 0x000 0x0 0x0 +-#define MX35_PAD_TX1__CCM_PMIC_RDY 0x168 0x5ac 0x7d4 0x1 0x1 +-#define MX35_PAD_TX1__CSPI1_SS2 0x168 0x5ac 0x7d8 0x2 0x2 +-#define MX35_PAD_TX1__EMI_NANDF_CE3 0x168 0x5ac 0x000 0x3 0x0 +-#define MX35_PAD_TX1__UART2_RI 0x168 0x5ac 0x000 0x4 0x0 +-#define MX35_PAD_TX1__GPIO1_14 0x168 0x5ac 0x000 0x5 0x0 +-#define MX35_PAD_TX1__IPU_CSI_D_6 0x168 0x5ac 0x948 0x6 0x0 +-#define MX35_PAD_TX1__KPP_COL_1 0x168 0x5ac 0x954 0x7 0x1 +-#define MX35_PAD_TX0__ESAI_TX0 0x16c 0x5b0 0x000 0x0 0x0 +-#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK 0x16c 0x5b0 0x994 0x1 0x1 +-#define MX35_PAD_TX0__CSPI1_SS3 0x16c 0x5b0 0x7dc 0x2 0x0 +-#define MX35_PAD_TX0__EMI_DTACK_B 0x16c 0x5b0 0x800 0x3 0x1 +-#define MX35_PAD_TX0__UART2_DCD 0x16c 0x5b0 0x000 0x4 0x0 +-#define MX35_PAD_TX0__GPIO1_15 0x16c 0x5b0 0x000 0x5 0x0 +-#define MX35_PAD_TX0__IPU_CSI_D_7 0x16c 0x5b0 0x94c 0x6 0x0 +-#define MX35_PAD_TX0__KPP_COL_2 0x16c 0x5b0 0x958 0x7 0x1 +-#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI 0x170 0x5b4 0x000 0x0 0x0 +-#define MX35_PAD_CSPI1_MOSI__GPIO1_16 0x170 0x5b4 0x000 0x5 0x0 +-#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 0x170 0x5b4 0x000 0x7 0x0 +-#define MX35_PAD_CSPI1_MISO__CSPI1_MISO 0x174 0x5b8 0x000 0x0 0x0 +-#define MX35_PAD_CSPI1_MISO__GPIO1_17 0x174 0x5b8 0x000 0x5 0x0 +-#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 0x174 0x5b8 0x000 0x7 0x0 +-#define MX35_PAD_CSPI1_SS0__CSPI1_SS0 0x178 0x5bc 0x000 0x0 0x0 +-#define MX35_PAD_CSPI1_SS0__OWIRE_LINE 0x178 0x5bc 0x990 0x1 0x1 +-#define MX35_PAD_CSPI1_SS0__CSPI2_SS3 0x178 0x5bc 0x7fc 0x2 0x1 +-#define MX35_PAD_CSPI1_SS0__GPIO1_18 0x178 0x5bc 0x000 0x5 0x0 +-#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 0x178 0x5bc 0x000 0x7 0x0 +-#define MX35_PAD_CSPI1_SS1__CSPI1_SS1 0x17c 0x5c0 0x000 0x0 0x0 +-#define MX35_PAD_CSPI1_SS1__PWM_PWMO 0x17c 0x5c0 0x000 0x1 0x0 +-#define MX35_PAD_CSPI1_SS1__CCM_CLK32K 0x17c 0x5c0 0x7d0 0x2 0x1 +-#define MX35_PAD_CSPI1_SS1__GPIO1_19 0x17c 0x5c0 0x000 0x5 0x0 +-#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 0x17c 0x5c0 0x000 0x6 0x0 +-#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 0x17c 0x5c0 0x000 0x7 0x0 +-#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK 0x180 0x5c4 0x000 0x0 0x0 +-#define MX35_PAD_CSPI1_SCLK__GPIO3_4 0x180 0x5c4 0x904 0x5 0x0 +-#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 0x180 0x5c4 0x000 0x6 0x0 +-#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 0x180 0x5c4 0x000 0x7 0x0 +-#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY 0x184 0x5c8 0x000 0x0 0x0 +-#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 0x184 0x5c8 0x908 0x5 0x0 +-#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 0x184 0x5c8 0x000 0x6 0x0 +-#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 0x184 0x5c8 0x000 0x7 0x0 +-#define MX35_PAD_RXD1__UART1_RXD_MUX 0x188 0x5cc 0x000 0x0 0x0 +-#define MX35_PAD_RXD1__CSPI2_MOSI 0x188 0x5cc 0x7ec 0x1 0x1 +-#define MX35_PAD_RXD1__KPP_COL_4 0x188 0x5cc 0x960 0x4 0x0 +-#define MX35_PAD_RXD1__GPIO3_6 0x188 0x5cc 0x90c 0x5 0x0 +-#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 0x188 0x5cc 0x000 0x7 0x0 +-#define MX35_PAD_TXD1__UART1_TXD_MUX 0x18c 0x5d0 0x000 0x0 0x0 +-#define MX35_PAD_TXD1__CSPI2_MISO 0x18c 0x5d0 0x7e8 0x1 0x1 +-#define MX35_PAD_TXD1__KPP_COL_5 0x18c 0x5d0 0x964 0x4 0x0 +-#define MX35_PAD_TXD1__GPIO3_7 0x18c 0x5d0 0x910 0x5 0x0 +-#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 0x18c 0x5d0 0x000 0x7 0x0 +-#define MX35_PAD_RTS1__UART1_RTS 0x190 0x5d4 0x000 0x0 0x0 +-#define MX35_PAD_RTS1__CSPI2_SCLK 0x190 0x5d4 0x7e0 0x1 0x1 +-#define MX35_PAD_RTS1__I2C3_SCL 0x190 0x5d4 0x91c 0x2 0x1 +-#define MX35_PAD_RTS1__IPU_CSI_D_0 0x190 0x5d4 0x930 0x3 0x1 +-#define MX35_PAD_RTS1__KPP_COL_6 0x190 0x5d4 0x968 0x4 0x0 +-#define MX35_PAD_RTS1__GPIO3_8 0x190 0x5d4 0x914 0x5 0x0 +-#define MX35_PAD_RTS1__EMI_NANDF_CE1 0x190 0x5d4 0x000 0x6 0x0 +-#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 0x190 0x5d4 0x000 0x7 0x0 +-#define MX35_PAD_CTS1__UART1_CTS 0x194 0x5d8 0x000 0x0 0x0 +-#define MX35_PAD_CTS1__CSPI2_RDY 0x194 0x5d8 0x7e4 0x1 0x1 +-#define MX35_PAD_CTS1__I2C3_SDA 0x194 0x5d8 0x920 0x2 0x1 +-#define MX35_PAD_CTS1__IPU_CSI_D_1 0x194 0x5d8 0x934 0x3 0x1 +-#define MX35_PAD_CTS1__KPP_COL_7 0x194 0x5d8 0x96c 0x4 0x0 +-#define MX35_PAD_CTS1__GPIO3_9 0x194 0x5d8 0x918 0x5 0x0 +-#define MX35_PAD_CTS1__EMI_NANDF_CE2 0x194 0x5d8 0x000 0x6 0x0 +-#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 0x194 0x5d8 0x000 0x7 0x0 +-#define MX35_PAD_RXD2__UART2_RXD_MUX 0x198 0x5dc 0x000 0x0 0x0 +-#define MX35_PAD_RXD2__KPP_ROW_4 0x198 0x5dc 0x980 0x4 0x0 +-#define MX35_PAD_RXD2__GPIO3_10 0x198 0x5dc 0x8ec 0x5 0x0 +-#define MX35_PAD_TXD2__UART2_TXD_MUX 0x19c 0x5e0 0x000 0x0 0x0 +-#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK 0x19c 0x5e0 0x994 0x1 0x2 +-#define MX35_PAD_TXD2__KPP_ROW_5 0x19c 0x5e0 0x984 0x4 0x0 +-#define MX35_PAD_TXD2__GPIO3_11 0x19c 0x5e0 0x8f0 0x5 0x0 +-#define MX35_PAD_RTS2__UART2_RTS 0x1a0 0x5e4 0x000 0x0 0x0 +-#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1 0x1a0 0x5e4 0x998 0x1 0x1 +-#define MX35_PAD_RTS2__CAN2_RXCAN 0x1a0 0x5e4 0x7cc 0x2 0x1 +-#define MX35_PAD_RTS2__IPU_CSI_D_2 0x1a0 0x5e4 0x938 0x3 0x1 +-#define MX35_PAD_RTS2__KPP_ROW_6 0x1a0 0x5e4 0x988 0x4 0x0 +-#define MX35_PAD_RTS2__GPIO3_12 0x1a0 0x5e4 0x8f4 0x5 0x0 +-#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC 0x1a0 0x5e4 0x000 0x6 0x0 +-#define MX35_PAD_RTS2__UART3_RXD_MUX 0x1a0 0x5e4 0x9a0 0x7 0x0 +-#define MX35_PAD_CTS2__UART2_CTS 0x1a4 0x5e8 0x000 0x0 0x0 +-#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 0x1a4 0x5e8 0x000 0x1 0x0 +-#define MX35_PAD_CTS2__CAN2_TXCAN 0x1a4 0x5e8 0x000 0x2 0x0 +-#define MX35_PAD_CTS2__IPU_CSI_D_3 0x1a4 0x5e8 0x93c 0x3 0x1 +-#define MX35_PAD_CTS2__KPP_ROW_7 0x1a4 0x5e8 0x98c 0x4 0x0 +-#define MX35_PAD_CTS2__GPIO3_13 0x1a4 0x5e8 0x8f8 0x5 0x0 +-#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS 0x1a4 0x5e8 0x000 0x6 0x0 +-#define MX35_PAD_CTS2__UART3_TXD_MUX 0x1a4 0x5e8 0x000 0x7 0x0 +-#define MX35_PAD_RTCK__ARM11P_TOP_RTCK 0x000 0x5ec 0x000 0x0 0x0 +-#define MX35_PAD_TCK__SJC_TCK 0x000 0x5f0 0x000 0x0 0x0 +-#define MX35_PAD_TMS__SJC_TMS 0x000 0x5f4 0x000 0x0 0x0 +-#define MX35_PAD_TDI__SJC_TDI 0x000 0x5f8 0x000 0x0 0x0 +-#define MX35_PAD_TDO__SJC_TDO 0x000 0x5fc 0x000 0x0 0x0 +-#define MX35_PAD_TRSTB__SJC_TRSTB 0x000 0x600 0x000 0x0 0x0 +-#define MX35_PAD_DE_B__SJC_DE_B 0x000 0x604 0x000 0x0 0x0 +-#define MX35_PAD_SJC_MOD__SJC_MOD 0x000 0x608 0x000 0x0 0x0 +-#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR 0x1a8 0x60c 0x000 0x0 0x0 +-#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR 0x1a8 0x60c 0x000 0x1 0x0 +-#define MX35_PAD_USBOTG_PWR__GPIO3_14 0x1a8 0x60c 0x8fc 0x5 0x0 +-#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC 0x1ac 0x610 0x000 0x0 0x0 +-#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC 0x1ac 0x610 0x9f4 0x1 0x1 +-#define MX35_PAD_USBOTG_OC__GPIO3_15 0x1ac 0x610 0x900 0x5 0x0 +-#define MX35_PAD_LD0__IPU_DISPB_DAT_0 0x1b0 0x614 0x000 0x0 0x0 +-#define MX35_PAD_LD0__GPIO2_0 0x1b0 0x614 0x868 0x5 0x1 +-#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 0x1b0 0x614 0x000 0x6 0x0 +-#define MX35_PAD_LD1__IPU_DISPB_DAT_1 0x1b4 0x618 0x000 0x0 0x0 +-#define MX35_PAD_LD1__GPIO2_1 0x1b4 0x618 0x894 0x5 0x0 +-#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 0x1b4 0x618 0x000 0x6 0x0 +-#define MX35_PAD_LD2__IPU_DISPB_DAT_2 0x1b8 0x61c 0x000 0x0 0x0 +-#define MX35_PAD_LD2__GPIO2_2 0x1b8 0x61c 0x8c0 0x5 0x0 +-#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 0x1b8 0x61c 0x000 0x6 0x0 +-#define MX35_PAD_LD3__IPU_DISPB_DAT_3 0x1bc 0x620 0x000 0x0 0x0 +-#define MX35_PAD_LD3__GPIO2_3 0x1bc 0x620 0x8cc 0x5 0x0 +-#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 0x1bc 0x620 0x000 0x6 0x0 +-#define MX35_PAD_LD4__IPU_DISPB_DAT_4 0x1c0 0x624 0x000 0x0 0x0 +-#define MX35_PAD_LD4__GPIO2_4 0x1c0 0x624 0x8d0 0x5 0x0 +-#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 0x1c0 0x624 0x000 0x6 0x0 +-#define MX35_PAD_LD5__IPU_DISPB_DAT_5 0x1c4 0x628 0x000 0x0 0x0 +-#define MX35_PAD_LD5__GPIO2_5 0x1c4 0x628 0x8d4 0x5 0x0 +-#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 0x1c4 0x628 0x000 0x6 0x0 +-#define MX35_PAD_LD6__IPU_DISPB_DAT_6 0x1c8 0x62c 0x000 0x0 0x0 +-#define MX35_PAD_LD6__GPIO2_6 0x1c8 0x62c 0x8d8 0x5 0x0 +-#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 0x1c8 0x62c 0x000 0x6 0x0 +-#define MX35_PAD_LD7__IPU_DISPB_DAT_7 0x1cc 0x630 0x000 0x0 0x0 +-#define MX35_PAD_LD7__GPIO2_7 0x1cc 0x630 0x8dc 0x5 0x0 +-#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 0x1cc 0x630 0x000 0x6 0x0 +-#define MX35_PAD_LD8__IPU_DISPB_DAT_8 0x1d0 0x634 0x000 0x0 0x0 +-#define MX35_PAD_LD8__GPIO2_8 0x1d0 0x634 0x8e0 0x5 0x0 +-#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 0x1d0 0x634 0x000 0x6 0x0 +-#define MX35_PAD_LD9__IPU_DISPB_DAT_9 0x1d4 0x638 0x000 0x0 0x0 +-#define MX35_PAD_LD9__GPIO2_9 0x1d4 0x638 0x8e4 0x5 0x0 +-#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 0x1d4 0x638 0x000 0x6 0x0 +-#define MX35_PAD_LD10__IPU_DISPB_DAT_10 0x1d8 0x63c 0x000 0x0 0x0 +-#define MX35_PAD_LD10__GPIO2_10 0x1d8 0x63c 0x86c 0x5 0x0 +-#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 0x1d8 0x63c 0x000 0x6 0x0 +-#define MX35_PAD_LD11__IPU_DISPB_DAT_11 0x1dc 0x640 0x000 0x0 0x0 +-#define MX35_PAD_LD11__GPIO2_11 0x1dc 0x640 0x870 0x5 0x0 +-#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 0x1dc 0x640 0x000 0x6 0x0 +-#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4 0x1dc 0x640 0x000 0x7 0x0 +-#define MX35_PAD_LD12__IPU_DISPB_DAT_12 0x1e0 0x644 0x000 0x0 0x0 +-#define MX35_PAD_LD12__GPIO2_12 0x1e0 0x644 0x874 0x5 0x0 +-#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 0x1e0 0x644 0x000 0x6 0x0 +-#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5 0x1e0 0x644 0x000 0x7 0x0 +-#define MX35_PAD_LD13__IPU_DISPB_DAT_13 0x1e4 0x648 0x000 0x0 0x0 +-#define MX35_PAD_LD13__GPIO2_13 0x1e4 0x648 0x878 0x5 0x0 +-#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 0x1e4 0x648 0x000 0x6 0x0 +-#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6 0x1e4 0x648 0x000 0x7 0x0 +-#define MX35_PAD_LD14__IPU_DISPB_DAT_14 0x1e8 0x64c 0x000 0x0 0x0 +-#define MX35_PAD_LD14__GPIO2_14 0x1e8 0x64c 0x87c 0x5 0x0 +-#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 0x1e8 0x64c 0x000 0x6 0x0 +-#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7 0x1e8 0x64c 0x000 0x7 0x0 +-#define MX35_PAD_LD15__IPU_DISPB_DAT_15 0x1ec 0x650 0x000 0x0 0x0 +-#define MX35_PAD_LD15__GPIO2_15 0x1ec 0x650 0x880 0x5 0x0 +-#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 0x1ec 0x650 0x000 0x6 0x0 +-#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8 0x1ec 0x650 0x000 0x7 0x0 +-#define MX35_PAD_LD16__IPU_DISPB_DAT_16 0x1f0 0x654 0x000 0x0 0x0 +-#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC 0x1f0 0x654 0x928 0x2 0x0 +-#define MX35_PAD_LD16__GPIO2_16 0x1f0 0x654 0x884 0x5 0x0 +-#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 0x1f0 0x654 0x000 0x6 0x0 +-#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9 0x1f0 0x654 0x000 0x7 0x0 +-#define MX35_PAD_LD17__IPU_DISPB_DAT_17 0x1f4 0x658 0x000 0x0 0x0 +-#define MX35_PAD_LD17__IPU_DISPB_CS2 0x1f4 0x658 0x000 0x2 0x0 +-#define MX35_PAD_LD17__GPIO2_17 0x1f4 0x658 0x888 0x5 0x0 +-#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 0x1f4 0x658 0x000 0x6 0x0 +-#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10 0x1f4 0x658 0x000 0x7 0x0 +-#define MX35_PAD_LD18__IPU_DISPB_DAT_18 0x1f8 0x65c 0x000 0x0 0x0 +-#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC 0x1f8 0x65c 0x924 0x1 0x1 +-#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC 0x1f8 0x65c 0x928 0x2 0x1 +-#define MX35_PAD_LD18__ESDHC3_CMD 0x1f8 0x65c 0x818 0x3 0x0 +-#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 0x1f8 0x65c 0x9b0 0x4 0x0 +-#define MX35_PAD_LD18__GPIO3_24 0x1f8 0x65c 0x000 0x5 0x0 +-#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 0x1f8 0x65c 0x000 0x6 0x0 +-#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11 0x1f8 0x65c 0x000 0x7 0x0 +-#define MX35_PAD_LD19__IPU_DISPB_DAT_19 0x1fc 0x660 0x000 0x0 0x0 +-#define MX35_PAD_LD19__IPU_DISPB_BCLK 0x1fc 0x660 0x000 0x1 0x0 +-#define MX35_PAD_LD19__IPU_DISPB_CS1 0x1fc 0x660 0x000 0x2 0x0 +-#define MX35_PAD_LD19__ESDHC3_CLK 0x1fc 0x660 0x814 0x3 0x0 +-#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR 0x1fc 0x660 0x9c4 0x4 0x0 +-#define MX35_PAD_LD19__GPIO3_25 0x1fc 0x660 0x000 0x5 0x0 +-#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 0x1fc 0x660 0x000 0x6 0x0 +-#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12 0x1fc 0x660 0x000 0x7 0x0 +-#define MX35_PAD_LD20__IPU_DISPB_DAT_20 0x200 0x664 0x000 0x0 0x0 +-#define MX35_PAD_LD20__IPU_DISPB_CS0 0x200 0x664 0x000 0x1 0x0 +-#define MX35_PAD_LD20__IPU_DISPB_SD_CLK 0x200 0x664 0x000 0x2 0x0 +-#define MX35_PAD_LD20__ESDHC3_DAT0 0x200 0x664 0x81c 0x3 0x0 +-#define MX35_PAD_LD20__GPIO3_26 0x200 0x664 0x000 0x5 0x0 +-#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 0x200 0x664 0x000 0x6 0x0 +-#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13 0x200 0x664 0x000 0x7 0x0 +-#define MX35_PAD_LD21__IPU_DISPB_DAT_21 0x204 0x668 0x000 0x0 0x0 +-#define MX35_PAD_LD21__IPU_DISPB_PAR_RS 0x204 0x668 0x000 0x1 0x0 +-#define MX35_PAD_LD21__IPU_DISPB_SER_RS 0x204 0x668 0x000 0x2 0x0 +-#define MX35_PAD_LD21__ESDHC3_DAT1 0x204 0x668 0x820 0x3 0x0 +-#define MX35_PAD_LD21__USB_TOP_USBOTG_STP 0x204 0x668 0x000 0x4 0x0 +-#define MX35_PAD_LD21__GPIO3_27 0x204 0x668 0x000 0x5 0x0 +-#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x204 0x668 0x000 0x6 0x0 +-#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14 0x204 0x668 0x000 0x7 0x0 +-#define MX35_PAD_LD22__IPU_DISPB_DAT_22 0x208 0x66c 0x000 0x0 0x0 +-#define MX35_PAD_LD22__IPU_DISPB_WR 0x208 0x66c 0x000 0x1 0x0 +-#define MX35_PAD_LD22__IPU_DISPB_SD_D_I 0x208 0x66c 0x92c 0x2 0x0 +-#define MX35_PAD_LD22__ESDHC3_DAT2 0x208 0x66c 0x824 0x3 0x0 +-#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT 0x208 0x66c 0x9c8 0x4 0x0 +-#define MX35_PAD_LD22__GPIO3_28 0x208 0x66c 0x000 0x5 0x0 +-#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR 0x208 0x66c 0x000 0x6 0x0 +-#define MX35_PAD_LD22__ARM11P_TOP_TRCTL 0x208 0x66c 0x000 0x7 0x0 +-#define MX35_PAD_LD23__IPU_DISPB_DAT_23 0x20c 0x670 0x000 0x0 0x0 +-#define MX35_PAD_LD23__IPU_DISPB_RD 0x20c 0x670 0x000 0x1 0x0 +-#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO 0x20c 0x670 0x92c 0x2 0x1 +-#define MX35_PAD_LD23__ESDHC3_DAT3 0x20c 0x670 0x828 0x3 0x0 +-#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 0x20c 0x670 0x9c0 0x4 0x0 +-#define MX35_PAD_LD23__GPIO3_29 0x20c 0x670 0x000 0x5 0x0 +-#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS 0x20c 0x670 0x000 0x6 0x0 +-#define MX35_PAD_LD23__ARM11P_TOP_TRCLK 0x20c 0x670 0x000 0x7 0x0 +-#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC 0x210 0x674 0x000 0x0 0x0 +-#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO 0x210 0x674 0x92c 0x2 0x2 +-#define MX35_PAD_D3_HSYNC__GPIO3_30 0x210 0x674 0x000 0x5 0x0 +-#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE 0x210 0x674 0x000 0x6 0x0 +-#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 0x210 0x674 0x000 0x7 0x0 +-#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK 0x214 0x678 0x000 0x0 0x0 +-#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK 0x214 0x678 0x000 0x2 0x0 +-#define MX35_PAD_D3_FPSHIFT__GPIO3_31 0x214 0x678 0x000 0x5 0x0 +-#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 0x214 0x678 0x000 0x6 0x0 +-#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 0x214 0x678 0x000 0x7 0x0 +-#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY 0x218 0x67c 0x000 0x0 0x0 +-#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O 0x218 0x67c 0x000 0x2 0x0 +-#define MX35_PAD_D3_DRDY__GPIO1_0 0x218 0x67c 0x82c 0x5 0x2 +-#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 0x218 0x67c 0x000 0x6 0x0 +-#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 0x218 0x67c 0x000 0x7 0x0 +-#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR 0x21c 0x680 0x000 0x0 0x0 +-#define MX35_PAD_CONTRAST__GPIO1_1 0x21c 0x680 0x838 0x5 0x2 +-#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 0x21c 0x680 0x000 0x6 0x0 +-#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 0x21c 0x680 0x000 0x7 0x0 +-#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC 0x220 0x684 0x000 0x0 0x0 +-#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 0x220 0x684 0x000 0x2 0x0 +-#define MX35_PAD_D3_VSYNC__GPIO1_2 0x220 0x684 0x848 0x5 0x1 +-#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD 0x220 0x684 0x000 0x6 0x0 +-#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 0x220 0x684 0x000 0x7 0x0 +-#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV 0x224 0x688 0x000 0x0 0x0 +-#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS 0x224 0x688 0x000 0x2 0x0 +-#define MX35_PAD_D3_REV__GPIO1_3 0x224 0x688 0x84c 0x5 0x1 +-#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB 0x224 0x688 0x000 0x6 0x0 +-#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 0x224 0x688 0x000 0x7 0x0 +-#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS 0x228 0x68c 0x000 0x0 0x0 +-#define MX35_PAD_D3_CLS__IPU_DISPB_CS2 0x228 0x68c 0x000 0x2 0x0 +-#define MX35_PAD_D3_CLS__GPIO1_4 0x228 0x68c 0x850 0x5 0x2 +-#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 0x228 0x68c 0x000 0x6 0x0 +-#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 0x228 0x68c 0x000 0x7 0x0 +-#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL 0x22c 0x690 0x000 0x0 0x0 +-#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC 0x22c 0x690 0x928 0x2 0x2 +-#define MX35_PAD_D3_SPL__GPIO1_5 0x22c 0x690 0x854 0x5 0x2 +-#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 0x22c 0x690 0x000 0x6 0x0 +-#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 0x22c 0x690 0x000 0x7 0x0 +-#define MX35_PAD_SD1_CMD__ESDHC1_CMD 0x230 0x694 0x000 0x0 0x0 +-#define MX35_PAD_SD1_CMD__MSHC_SCLK 0x230 0x694 0x000 0x1 0x0 +-#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC 0x230 0x694 0x924 0x3 0x2 +-#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 0x230 0x694 0x9b4 0x4 0x0 +-#define MX35_PAD_SD1_CMD__GPIO1_6 0x230 0x694 0x858 0x5 0x2 +-#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL 0x230 0x694 0x000 0x7 0x0 +-#define MX35_PAD_SD1_CLK__ESDHC1_CLK 0x234 0x698 0x000 0x0 0x0 +-#define MX35_PAD_SD1_CLK__MSHC_BS 0x234 0x698 0x000 0x1 0x0 +-#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK 0x234 0x698 0x000 0x3 0x0 +-#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 0x234 0x698 0x9b8 0x4 0x0 +-#define MX35_PAD_SD1_CLK__GPIO1_7 0x234 0x698 0x85c 0x5 0x2 +-#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK 0x234 0x698 0x000 0x7 0x0 +-#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x238 0x69c 0x000 0x0 0x0 +-#define MX35_PAD_SD1_DATA0__MSHC_DATA_0 0x238 0x69c 0x000 0x1 0x0 +-#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 0x238 0x69c 0x000 0x3 0x0 +-#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 0x238 0x69c 0x9bc 0x4 0x0 +-#define MX35_PAD_SD1_DATA0__GPIO1_8 0x238 0x69c 0x860 0x5 0x2 +-#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 0x238 0x69c 0x000 0x7 0x0 +-#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x23c 0x6a0 0x000 0x0 0x0 +-#define MX35_PAD_SD1_DATA1__MSHC_DATA_1 0x23c 0x6a0 0x000 0x1 0x0 +-#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS 0x23c 0x6a0 0x000 0x3 0x0 +-#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 0x23c 0x6a0 0x9a4 0x4 0x0 +-#define MX35_PAD_SD1_DATA1__GPIO1_9 0x23c 0x6a0 0x864 0x5 0x1 +-#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 0x23c 0x6a0 0x000 0x7 0x0 +-#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x240 0x6a4 0x000 0x0 0x0 +-#define MX35_PAD_SD1_DATA2__MSHC_DATA_2 0x240 0x6a4 0x000 0x1 0x0 +-#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR 0x240 0x6a4 0x000 0x3 0x0 +-#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 0x240 0x6a4 0x9a8 0x4 0x0 +-#define MX35_PAD_SD1_DATA2__GPIO1_10 0x240 0x6a4 0x830 0x5 0x1 +-#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 0x240 0x6a4 0x000 0x7 0x0 +-#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x244 0x6a8 0x000 0x0 0x0 +-#define MX35_PAD_SD1_DATA3__MSHC_DATA_3 0x244 0x6a8 0x000 0x1 0x0 +-#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD 0x244 0x6a8 0x000 0x3 0x0 +-#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 0x244 0x6a8 0x9ac 0x4 0x0 +-#define MX35_PAD_SD1_DATA3__GPIO1_11 0x244 0x6a8 0x834 0x5 0x1 +-#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 0x244 0x6a8 0x000 0x7 0x0 +-#define MX35_PAD_SD2_CMD__ESDHC2_CMD 0x248 0x6ac 0x000 0x0 0x0 +-#define MX35_PAD_SD2_CMD__I2C3_SCL 0x248 0x6ac 0x91c 0x1 0x2 +-#define MX35_PAD_SD2_CMD__ESDHC1_DAT4 0x248 0x6ac 0x804 0x2 0x0 +-#define MX35_PAD_SD2_CMD__IPU_CSI_D_2 0x248 0x6ac 0x938 0x3 0x2 +-#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 0x248 0x6ac 0x9dc 0x4 0x0 +-#define MX35_PAD_SD2_CMD__GPIO2_0 0x248 0x6ac 0x868 0x5 0x2 +-#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 0x248 0x6ac 0x000 0x6 0x0 +-#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC 0x248 0x6ac 0x928 0x7 0x3 +-#define MX35_PAD_SD2_CLK__ESDHC2_CLK 0x24c 0x6b0 0x000 0x0 0x0 +-#define MX35_PAD_SD2_CLK__I2C3_SDA 0x24c 0x6b0 0x920 0x1 0x2 +-#define MX35_PAD_SD2_CLK__ESDHC1_DAT5 0x24c 0x6b0 0x808 0x2 0x0 +-#define MX35_PAD_SD2_CLK__IPU_CSI_D_3 0x24c 0x6b0 0x93c 0x3 0x2 +-#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 0x24c 0x6b0 0x9e0 0x4 0x0 +-#define MX35_PAD_SD2_CLK__GPIO2_1 0x24c 0x6b0 0x894 0x5 0x1 +-#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 0x24c 0x6b0 0x998 0x6 0x2 +-#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2 0x24c 0x6b0 0x000 0x7 0x0 +-#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0 0x250 0x6b4 0x000 0x0 0x0 +-#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX 0x250 0x6b4 0x9a0 0x1 0x1 +-#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6 0x250 0x6b4 0x80c 0x2 0x0 +-#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4 0x250 0x6b4 0x940 0x3 0x1 +-#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 0x250 0x6b4 0x9e4 0x4 0x0 +-#define MX35_PAD_SD2_DATA0__GPIO2_2 0x250 0x6b4 0x8c0 0x5 0x1 +-#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK 0x250 0x6b4 0x994 0x6 0x3 +-#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1 0x254 0x6b8 0x000 0x0 0x0 +-#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX 0x254 0x6b8 0x000 0x1 0x0 +-#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7 0x254 0x6b8 0x810 0x2 0x0 +-#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5 0x254 0x6b8 0x944 0x3 0x1 +-#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 0x254 0x6b8 0x9cc 0x4 0x0 +-#define MX35_PAD_SD2_DATA1__GPIO2_3 0x254 0x6b8 0x8cc 0x5 0x1 +-#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2 0x258 0x6bc 0x000 0x0 0x0 +-#define MX35_PAD_SD2_DATA2__UART3_RTS 0x258 0x6bc 0x99c 0x1 0x0 +-#define MX35_PAD_SD2_DATA2__CAN1_RXCAN 0x258 0x6bc 0x7c8 0x2 0x1 +-#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6 0x258 0x6bc 0x948 0x3 0x1 +-#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 0x258 0x6bc 0x9d0 0x4 0x0 +-#define MX35_PAD_SD2_DATA2__GPIO2_4 0x258 0x6bc 0x8d0 0x5 0x1 +-#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3 0x25c 0x6c0 0x000 0x0 0x0 +-#define MX35_PAD_SD2_DATA3__UART3_CTS 0x25c 0x6c0 0x000 0x1 0x0 +-#define MX35_PAD_SD2_DATA3__CAN1_TXCAN 0x25c 0x6c0 0x000 0x2 0x0 +-#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7 0x25c 0x6c0 0x94c 0x3 0x1 +-#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 0x25c 0x6c0 0x9d4 0x4 0x0 +-#define MX35_PAD_SD2_DATA3__GPIO2_5 0x25c 0x6c0 0x8d4 0x5 0x1 +-#define MX35_PAD_ATA_CS0__ATA_CS0 0x260 0x6c4 0x000 0x0 0x0 +-#define MX35_PAD_ATA_CS0__CSPI1_SS3 0x260 0x6c4 0x7dc 0x1 0x1 +-#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1 0x260 0x6c4 0x000 0x3 0x0 +-#define MX35_PAD_ATA_CS0__GPIO2_6 0x260 0x6c4 0x8d8 0x5 0x1 +-#define MX35_PAD_ATA_CS0__IPU_DIAGB_0 0x260 0x6c4 0x000 0x6 0x0 +-#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 0x260 0x6c4 0x000 0x7 0x0 +-#define MX35_PAD_ATA_CS1__ATA_CS1 0x264 0x6c8 0x000 0x0 0x0 +-#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2 0x264 0x6c8 0x000 0x3 0x0 +-#define MX35_PAD_ATA_CS1__CSPI2_SS0 0x264 0x6c8 0x7f0 0x4 0x1 +-#define MX35_PAD_ATA_CS1__GPIO2_7 0x264 0x6c8 0x8dc 0x5 0x1 +-#define MX35_PAD_ATA_CS1__IPU_DIAGB_1 0x264 0x6c8 0x000 0x6 0x0 +-#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 0x264 0x6c8 0x000 0x7 0x0 +-#define MX35_PAD_ATA_DIOR__ATA_DIOR 0x268 0x6cc 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0 0x268 0x6cc 0x81c 0x1 0x1 +-#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR 0x268 0x6cc 0x9c4 0x2 0x1 +-#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 0x268 0x6cc 0x000 0x3 0x0 +-#define MX35_PAD_ATA_DIOR__CSPI2_SS1 0x268 0x6cc 0x7f4 0x4 0x1 +-#define MX35_PAD_ATA_DIOR__GPIO2_8 0x268 0x6cc 0x8e0 0x5 0x1 +-#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2 0x268 0x6cc 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 0x268 0x6cc 0x000 0x7 0x0 +-#define MX35_PAD_ATA_DIOW__ATA_DIOW 0x26c 0x6d0 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1 0x26c 0x6d0 0x820 0x1 0x1 +-#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP 0x26c 0x6d0 0x000 0x2 0x0 +-#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 0x26c 0x6d0 0x000 0x3 0x0 +-#define MX35_PAD_ATA_DIOW__CSPI2_MOSI 0x26c 0x6d0 0x7ec 0x4 0x2 +-#define MX35_PAD_ATA_DIOW__GPIO2_9 0x26c 0x6d0 0x8e4 0x5 0x1 +-#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3 0x26c 0x6d0 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 0x26c 0x6d0 0x000 0x7 0x0 +-#define MX35_PAD_ATA_DMACK__ATA_DMACK 0x270 0x6d4 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2 0x270 0x6d4 0x824 0x1 0x1 +-#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT 0x270 0x6d4 0x9c8 0x2 0x1 +-#define MX35_PAD_ATA_DMACK__CSPI2_MISO 0x270 0x6d4 0x7e8 0x4 0x2 +-#define MX35_PAD_ATA_DMACK__GPIO2_10 0x270 0x6d4 0x86c 0x5 0x1 +-#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4 0x270 0x6d4 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 0x270 0x6d4 0x000 0x7 0x0 +-#define MX35_PAD_ATA_RESET_B__ATA_RESET_B 0x274 0x6d8 0x000 0x0 0x0 +-#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 0x274 0x6d8 0x828 0x1 0x1 +-#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 0x274 0x6d8 0x9a4 0x2 0x1 +-#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O 0x274 0x6d8 0x000 0x3 0x0 +-#define MX35_PAD_ATA_RESET_B__CSPI2_RDY 0x274 0x6d8 0x7e4 0x4 0x2 +-#define MX35_PAD_ATA_RESET_B__GPIO2_11 0x274 0x6d8 0x870 0x5 0x1 +-#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 0x274 0x6d8 0x000 0x6 0x0 +-#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 0x274 0x6d8 0x000 0x7 0x0 +-#define MX35_PAD_ATA_IORDY__ATA_IORDY 0x278 0x6dc 0x000 0x0 0x0 +-#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4 0x278 0x6dc 0x000 0x1 0x0 +-#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 0x278 0x6dc 0x9a8 0x2 0x1 +-#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO 0x278 0x6dc 0x92c 0x3 0x3 +-#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4 0x278 0x6dc 0x000 0x4 0x0 +-#define MX35_PAD_ATA_IORDY__GPIO2_12 0x278 0x6dc 0x874 0x5 0x1 +-#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6 0x278 0x6dc 0x000 0x6 0x0 +-#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 0x278 0x6dc 0x000 0x7 0x0 +-#define MX35_PAD_ATA_DATA0__ATA_DATA_0 0x27c 0x6e0 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5 0x27c 0x6e0 0x000 0x1 0x0 +-#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 0x27c 0x6e0 0x9ac 0x2 0x1 +-#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC 0x27c 0x6e0 0x928 0x3 0x4 +-#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5 0x27c 0x6e0 0x000 0x4 0x0 +-#define MX35_PAD_ATA_DATA0__GPIO2_13 0x27c 0x6e0 0x878 0x5 0x1 +-#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7 0x27c 0x6e0 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 0x27c 0x6e0 0x000 0x7 0x0 +-#define MX35_PAD_ATA_DATA1__ATA_DATA_1 0x280 0x6e4 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6 0x280 0x6e4 0x000 0x1 0x0 +-#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 0x280 0x6e4 0x9b0 0x2 0x1 +-#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK 0x280 0x6e4 0x000 0x3 0x0 +-#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6 0x280 0x6e4 0x000 0x4 0x0 +-#define MX35_PAD_ATA_DATA1__GPIO2_14 0x280 0x6e4 0x87c 0x5 0x1 +-#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8 0x280 0x6e4 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 0x280 0x6e4 0x000 0x7 0x0 +-#define MX35_PAD_ATA_DATA2__ATA_DATA_2 0x284 0x6e8 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7 0x284 0x6e8 0x000 0x1 0x0 +-#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 0x284 0x6e8 0x9b4 0x2 0x1 +-#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS 0x284 0x6e8 0x000 0x3 0x0 +-#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7 0x284 0x6e8 0x000 0x4 0x0 +-#define MX35_PAD_ATA_DATA2__GPIO2_15 0x284 0x6e8 0x880 0x5 0x1 +-#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 0x284 0x6e8 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 0x284 0x6e8 0x000 0x7 0x0 +-#define MX35_PAD_ATA_DATA3__ATA_DATA_3 0x288 0x6ec 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DATA3__ESDHC3_CLK 0x288 0x6ec 0x814 0x1 0x1 +-#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 0x288 0x6ec 0x9b8 0x2 0x1 +-#define MX35_PAD_ATA_DATA3__CSPI2_SCLK 0x288 0x6ec 0x7e0 0x4 0x2 +-#define MX35_PAD_ATA_DATA3__GPIO2_16 0x288 0x6ec 0x884 0x5 0x1 +-#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 0x288 0x6ec 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 0x288 0x6ec 0x000 0x7 0x0 +-#define MX35_PAD_ATA_DATA4__ATA_DATA_4 0x28c 0x6f0 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DATA4__ESDHC3_CMD 0x28c 0x6f0 0x818 0x1 0x1 +-#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 0x28c 0x6f0 0x9bc 0x2 0x1 +-#define MX35_PAD_ATA_DATA4__GPIO2_17 0x28c 0x6f0 0x888 0x5 0x1 +-#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11 0x28c 0x6f0 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 0x28c 0x6f0 0x000 0x7 0x0 +-#define MX35_PAD_ATA_DATA5__ATA_DATA_5 0x290 0x6f4 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 0x290 0x6f4 0x9c0 0x2 0x1 +-#define MX35_PAD_ATA_DATA5__GPIO2_18 0x290 0x6f4 0x88c 0x5 0x1 +-#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12 0x290 0x6f4 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 0x290 0x6f4 0x000 0x7 0x0 +-#define MX35_PAD_ATA_DATA6__ATA_DATA_6 0x294 0x6f8 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DATA6__CAN1_TXCAN 0x294 0x6f8 0x000 0x1 0x0 +-#define MX35_PAD_ATA_DATA6__UART1_DTR 0x294 0x6f8 0x000 0x2 0x0 +-#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD 0x294 0x6f8 0x7b4 0x3 0x0 +-#define MX35_PAD_ATA_DATA6__GPIO2_19 0x294 0x6f8 0x890 0x5 0x1 +-#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13 0x294 0x6f8 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DATA7__ATA_DATA_7 0x298 0x6fc 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DATA7__CAN1_RXCAN 0x298 0x6fc 0x7c8 0x1 0x2 +-#define MX35_PAD_ATA_DATA7__UART1_DSR 0x298 0x6fc 0x000 0x2 0x0 +-#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD 0x298 0x6fc 0x7b0 0x3 0x0 +-#define MX35_PAD_ATA_DATA7__GPIO2_20 0x298 0x6fc 0x898 0x5 0x1 +-#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14 0x298 0x6fc 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DATA8__ATA_DATA_8 0x29c 0x700 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DATA8__UART3_RTS 0x29c 0x700 0x99c 0x1 0x1 +-#define MX35_PAD_ATA_DATA8__UART1_RI 0x29c 0x700 0x000 0x2 0x0 +-#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC 0x29c 0x700 0x7c0 0x3 0x0 +-#define MX35_PAD_ATA_DATA8__GPIO2_21 0x29c 0x700 0x89c 0x5 0x1 +-#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15 0x29c 0x700 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DATA9__ATA_DATA_9 0x2a0 0x704 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DATA9__UART3_CTS 0x2a0 0x704 0x000 0x1 0x0 +-#define MX35_PAD_ATA_DATA9__UART1_DCD 0x2a0 0x704 0x000 0x2 0x0 +-#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS 0x2a0 0x704 0x7c4 0x3 0x0 +-#define MX35_PAD_ATA_DATA9__GPIO2_22 0x2a0 0x704 0x8a0 0x5 0x1 +-#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16 0x2a0 0x704 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DATA10__ATA_DATA_10 0x2a4 0x708 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX 0x2a4 0x708 0x9a0 0x1 0x2 +-#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC 0x2a4 0x708 0x7b8 0x3 0x0 +-#define MX35_PAD_ATA_DATA10__GPIO2_23 0x2a4 0x708 0x8a4 0x5 0x1 +-#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17 0x2a4 0x708 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DATA11__ATA_DATA_11 0x2a8 0x70c 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX 0x2a8 0x70c 0x000 0x1 0x0 +-#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS 0x2a8 0x70c 0x7bc 0x3 0x0 +-#define MX35_PAD_ATA_DATA11__GPIO2_24 0x2a8 0x70c 0x8a8 0x5 0x1 +-#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18 0x2a8 0x70c 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DATA12__ATA_DATA_12 0x2ac 0x710 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DATA12__I2C3_SCL 0x2ac 0x710 0x91c 0x1 0x3 +-#define MX35_PAD_ATA_DATA12__GPIO2_25 0x2ac 0x710 0x8ac 0x5 0x1 +-#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19 0x2ac 0x710 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DATA13__ATA_DATA_13 0x2b0 0x714 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DATA13__I2C3_SDA 0x2b0 0x714 0x920 0x1 0x3 +-#define MX35_PAD_ATA_DATA13__GPIO2_26 0x2b0 0x714 0x8b0 0x5 0x1 +-#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20 0x2b0 0x714 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DATA14__ATA_DATA_14 0x2b4 0x718 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0 0x2b4 0x718 0x930 0x1 0x2 +-#define MX35_PAD_ATA_DATA14__KPP_ROW_0 0x2b4 0x718 0x970 0x3 0x2 +-#define MX35_PAD_ATA_DATA14__GPIO2_27 0x2b4 0x718 0x8b4 0x5 0x1 +-#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21 0x2b4 0x718 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DATA15__ATA_DATA_15 0x2b8 0x71c 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1 0x2b8 0x71c 0x934 0x1 0x2 +-#define MX35_PAD_ATA_DATA15__KPP_ROW_1 0x2b8 0x71c 0x974 0x3 0x2 +-#define MX35_PAD_ATA_DATA15__GPIO2_28 0x2b8 0x71c 0x8b8 0x5 0x1 +-#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22 0x2b8 0x71c 0x000 0x6 0x0 +-#define MX35_PAD_ATA_INTRQ__ATA_INTRQ 0x2bc 0x720 0x000 0x0 0x0 +-#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 0x2bc 0x720 0x938 0x1 0x3 +-#define MX35_PAD_ATA_INTRQ__KPP_ROW_2 0x2bc 0x720 0x978 0x3 0x2 +-#define MX35_PAD_ATA_INTRQ__GPIO2_29 0x2bc 0x720 0x8bc 0x5 0x1 +-#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 0x2bc 0x720 0x000 0x6 0x0 +-#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN 0x2c0 0x724 0x000 0x0 0x0 +-#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 0x2c0 0x724 0x93c 0x1 0x3 +-#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 0x2c0 0x724 0x97c 0x3 0x2 +-#define MX35_PAD_ATA_BUFF_EN__GPIO2_30 0x2c0 0x724 0x8c4 0x5 0x1 +-#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 0x2c0 0x724 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DMARQ__ATA_DMARQ 0x2c4 0x728 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 0x2c4 0x728 0x940 0x1 0x2 +-#define MX35_PAD_ATA_DMARQ__KPP_COL_0 0x2c4 0x728 0x950 0x3 0x2 +-#define MX35_PAD_ATA_DMARQ__GPIO2_31 0x2c4 0x728 0x8c8 0x5 0x1 +-#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 0x2c4 0x728 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 0x2c4 0x728 0x000 0x7 0x0 +-#define MX35_PAD_ATA_DA0__ATA_DA_0 0x2c8 0x72c 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DA0__IPU_CSI_D_5 0x2c8 0x72c 0x944 0x1 0x2 +-#define MX35_PAD_ATA_DA0__KPP_COL_1 0x2c8 0x72c 0x954 0x3 0x2 +-#define MX35_PAD_ATA_DA0__GPIO3_0 0x2c8 0x72c 0x8e8 0x5 0x1 +-#define MX35_PAD_ATA_DA0__IPU_DIAGB_26 0x2c8 0x72c 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 0x2c8 0x72c 0x000 0x7 0x0 +-#define MX35_PAD_ATA_DA1__ATA_DA_1 0x2cc 0x730 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DA1__IPU_CSI_D_6 0x2cc 0x730 0x948 0x1 0x2 +-#define MX35_PAD_ATA_DA1__KPP_COL_2 0x2cc 0x730 0x958 0x3 0x2 +-#define MX35_PAD_ATA_DA1__GPIO3_1 0x2cc 0x730 0x000 0x5 0x0 +-#define MX35_PAD_ATA_DA1__IPU_DIAGB_27 0x2cc 0x730 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 0x2cc 0x730 0x000 0x7 0x0 +-#define MX35_PAD_ATA_DA2__ATA_DA_2 0x2d0 0x734 0x000 0x0 0x0 +-#define MX35_PAD_ATA_DA2__IPU_CSI_D_7 0x2d0 0x734 0x94c 0x1 0x2 +-#define MX35_PAD_ATA_DA2__KPP_COL_3 0x2d0 0x734 0x95c 0x3 0x2 +-#define MX35_PAD_ATA_DA2__GPIO3_2 0x2d0 0x734 0x000 0x5 0x0 +-#define MX35_PAD_ATA_DA2__IPU_DIAGB_28 0x2d0 0x734 0x000 0x6 0x0 +-#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 0x2d0 0x734 0x000 0x7 0x0 +-#define MX35_PAD_MLB_CLK__MLB_MLBCLK 0x2d4 0x738 0x000 0x0 0x0 +-#define MX35_PAD_MLB_CLK__GPIO3_3 0x2d4 0x738 0x000 0x5 0x0 +-#define MX35_PAD_MLB_DAT__MLB_MLBDAT 0x2d8 0x73c 0x000 0x0 0x0 +-#define MX35_PAD_MLB_DAT__GPIO3_4 0x2d8 0x73c 0x904 0x5 0x1 +-#define MX35_PAD_MLB_SIG__MLB_MLBSIG 0x2dc 0x740 0x000 0x0 0x0 +-#define MX35_PAD_MLB_SIG__GPIO3_5 0x2dc 0x740 0x908 0x5 0x1 +-#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x2e0 0x744 0x000 0x0 0x0 +-#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 0x2e0 0x744 0x804 0x1 0x1 +-#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX 0x2e0 0x744 0x9a0 0x2 0x3 +-#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR 0x2e0 0x744 0x9ec 0x3 0x1 +-#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI 0x2e0 0x744 0x7ec 0x4 0x3 +-#define MX35_PAD_FEC_TX_CLK__GPIO3_6 0x2e0 0x744 0x90c 0x5 0x1 +-#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC 0x2e0 0x744 0x928 0x6 0x5 +-#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 0x2e0 0x744 0x000 0x7 0x0 +-#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x2e4 0x748 0x000 0x0 0x0 +-#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 0x2e4 0x748 0x808 0x1 0x1 +-#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX 0x2e4 0x748 0x000 0x2 0x0 +-#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP 0x2e4 0x748 0x000 0x3 0x0 +-#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO 0x2e4 0x748 0x7e8 0x4 0x3 +-#define MX35_PAD_FEC_RX_CLK__GPIO3_7 0x2e4 0x748 0x910 0x5 0x1 +-#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I 0x2e4 0x748 0x92c 0x6 0x4 +-#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 0x2e4 0x748 0x000 0x7 0x0 +-#define MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x2e8 0x74c 0x000 0x0 0x0 +-#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 0x2e8 0x74c 0x80c 0x1 0x1 +-#define MX35_PAD_FEC_RX_DV__UART3_RTS 0x2e8 0x74c 0x99c 0x2 0x2 +-#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT 0x2e8 0x74c 0x9f0 0x3 0x1 +-#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK 0x2e8 0x74c 0x7e0 0x4 0x3 +-#define MX35_PAD_FEC_RX_DV__GPIO3_8 0x2e8 0x74c 0x914 0x5 0x1 +-#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK 0x2e8 0x74c 0x000 0x6 0x0 +-#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 0x2e8 0x74c 0x000 0x7 0x0 +-#define MX35_PAD_FEC_COL__FEC_COL 0x2ec 0x750 0x000 0x0 0x0 +-#define MX35_PAD_FEC_COL__ESDHC1_DAT7 0x2ec 0x750 0x810 0x1 0x1 +-#define MX35_PAD_FEC_COL__UART3_CTS 0x2ec 0x750 0x000 0x2 0x0 +-#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 0x2ec 0x750 0x9cc 0x3 0x1 +-#define MX35_PAD_FEC_COL__CSPI2_RDY 0x2ec 0x750 0x7e4 0x4 0x3 +-#define MX35_PAD_FEC_COL__GPIO3_9 0x2ec 0x750 0x918 0x5 0x1 +-#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS 0x2ec 0x750 0x000 0x6 0x0 +-#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 0x2ec 0x750 0x000 0x7 0x0 +-#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x2f0 0x754 0x000 0x0 0x0 +-#define MX35_PAD_FEC_RDATA0__PWM_PWMO 0x2f0 0x754 0x000 0x1 0x0 +-#define MX35_PAD_FEC_RDATA0__UART3_DTR 0x2f0 0x754 0x000 0x2 0x0 +-#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 0x2f0 0x754 0x9d0 0x3 0x1 +-#define MX35_PAD_FEC_RDATA0__CSPI2_SS0 0x2f0 0x754 0x7f0 0x4 0x2 +-#define MX35_PAD_FEC_RDATA0__GPIO3_10 0x2f0 0x754 0x8ec 0x5 0x1 +-#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 0x2f0 0x754 0x000 0x6 0x0 +-#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 0x2f0 0x754 0x000 0x7 0x0 +-#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x2f4 0x758 0x000 0x0 0x0 +-#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 0x2f4 0x758 0x000 0x1 0x0 +-#define MX35_PAD_FEC_TDATA0__UART3_DSR 0x2f4 0x758 0x000 0x2 0x0 +-#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 0x2f4 0x758 0x9d4 0x3 0x1 +-#define MX35_PAD_FEC_TDATA0__CSPI2_SS1 0x2f4 0x758 0x7f4 0x4 0x2 +-#define MX35_PAD_FEC_TDATA0__GPIO3_11 0x2f4 0x758 0x8f0 0x5 0x1 +-#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 0x2f4 0x758 0x000 0x6 0x0 +-#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 0x2f4 0x758 0x000 0x7 0x0 +-#define MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x2f8 0x75c 0x000 0x0 0x0 +-#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 0x2f8 0x75c 0x998 0x1 0x3 +-#define MX35_PAD_FEC_TX_EN__UART3_RI 0x2f8 0x75c 0x000 0x2 0x0 +-#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 0x2f8 0x75c 0x9d8 0x3 0x1 +-#define MX35_PAD_FEC_TX_EN__GPIO3_12 0x2f8 0x75c 0x8f4 0x5 0x1 +-#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS 0x2f8 0x75c 0x000 0x6 0x0 +-#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 0x2f8 0x75c 0x000 0x7 0x0 +-#define MX35_PAD_FEC_MDC__FEC_MDC 0x2fc 0x760 0x000 0x0 0x0 +-#define MX35_PAD_FEC_MDC__CAN2_TXCAN 0x2fc 0x760 0x000 0x1 0x0 +-#define MX35_PAD_FEC_MDC__UART3_DCD 0x2fc 0x760 0x000 0x2 0x0 +-#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 0x2fc 0x760 0x9dc 0x3 0x1 +-#define MX35_PAD_FEC_MDC__GPIO3_13 0x2fc 0x760 0x8f8 0x5 0x1 +-#define MX35_PAD_FEC_MDC__IPU_DISPB_WR 0x2fc 0x760 0x000 0x6 0x0 +-#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 0x2fc 0x760 0x000 0x7 0x0 +-#define MX35_PAD_FEC_MDIO__FEC_MDIO 0x300 0x764 0x000 0x0 0x0 +-#define MX35_PAD_FEC_MDIO__CAN2_RXCAN 0x300 0x764 0x7cc 0x1 0x2 +-#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 0x300 0x764 0x9e0 0x3 0x1 +-#define MX35_PAD_FEC_MDIO__GPIO3_14 0x300 0x764 0x8fc 0x5 0x1 +-#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD 0x300 0x764 0x000 0x6 0x0 +-#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 0x300 0x764 0x000 0x7 0x0 +-#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x304 0x768 0x000 0x0 0x0 +-#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE 0x304 0x768 0x990 0x1 0x2 +-#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK 0x304 0x768 0x994 0x2 0x4 +-#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 0x304 0x768 0x9e4 0x3 0x1 +-#define MX35_PAD_FEC_TX_ERR__GPIO3_15 0x304 0x768 0x900 0x5 0x1 +-#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC 0x304 0x768 0x924 0x6 0x3 +-#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 0x304 0x768 0x000 0x7 0x0 +-#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x308 0x76c 0x000 0x0 0x0 +-#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 0x308 0x76c 0x930 0x1 0x3 +-#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 0x308 0x76c 0x9e8 0x3 0x1 +-#define MX35_PAD_FEC_RX_ERR__KPP_COL_4 0x308 0x76c 0x960 0x4 0x1 +-#define MX35_PAD_FEC_RX_ERR__GPIO3_16 0x308 0x76c 0x000 0x5 0x0 +-#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO 0x308 0x76c 0x92c 0x6 0x5 +-#define MX35_PAD_FEC_CRS__FEC_CRS 0x30c 0x770 0x000 0x0 0x0 +-#define MX35_PAD_FEC_CRS__IPU_CSI_D_1 0x30c 0x770 0x934 0x1 0x3 +-#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR 0x30c 0x770 0x000 0x3 0x0 +-#define MX35_PAD_FEC_CRS__KPP_COL_5 0x30c 0x770 0x964 0x4 0x1 +-#define MX35_PAD_FEC_CRS__GPIO3_17 0x30c 0x770 0x000 0x5 0x0 +-#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE 0x30c 0x770 0x000 0x6 0x0 +-#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x310 0x774 0x000 0x0 0x0 +-#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 0x310 0x774 0x938 0x1 0x4 +-#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC 0x310 0x774 0x000 0x2 0x0 +-#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC 0x310 0x774 0x9f4 0x3 0x2 +-#define MX35_PAD_FEC_RDATA1__KPP_COL_6 0x310 0x774 0x968 0x4 0x1 +-#define MX35_PAD_FEC_RDATA1__GPIO3_18 0x310 0x774 0x000 0x5 0x0 +-#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 0x310 0x774 0x000 0x6 0x0 +-#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x314 0x778 0x000 0x0 0x0 +-#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 0x314 0x778 0x93c 0x1 0x4 +-#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS 0x314 0x778 0x7bc 0x2 0x1 +-#define MX35_PAD_FEC_TDATA1__KPP_COL_7 0x314 0x778 0x96c 0x4 0x1 +-#define MX35_PAD_FEC_TDATA1__GPIO3_19 0x314 0x778 0x000 0x5 0x0 +-#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 0x314 0x778 0x000 0x6 0x0 +-#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x318 0x77c 0x000 0x0 0x0 +-#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 0x318 0x77c 0x940 0x1 0x3 +-#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD 0x318 0x77c 0x7b4 0x2 0x1 +-#define MX35_PAD_FEC_RDATA2__KPP_ROW_4 0x318 0x77c 0x980 0x4 0x1 +-#define MX35_PAD_FEC_RDATA2__GPIO3_20 0x318 0x77c 0x000 0x5 0x0 +-#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x31c 0x780 0x000 0x0 0x0 +-#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 0x31c 0x780 0x944 0x1 0x3 +-#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD 0x31c 0x780 0x7b0 0x2 0x1 +-#define MX35_PAD_FEC_TDATA2__KPP_ROW_5 0x31c 0x780 0x984 0x4 0x1 +-#define MX35_PAD_FEC_TDATA2__GPIO3_21 0x31c 0x780 0x000 0x5 0x0 +-#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x320 0x784 0x000 0x0 0x0 +-#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 0x320 0x784 0x948 0x1 0x3 +-#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC 0x320 0x784 0x7c0 0x2 0x1 +-#define MX35_PAD_FEC_RDATA3__KPP_ROW_6 0x320 0x784 0x988 0x4 0x1 +-#define MX35_PAD_FEC_RDATA3__GPIO3_22 0x320 0x784 0x000 0x6 0x0 +-#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x324 0x788 0x000 0x0 0x0 +-#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 0x324 0x788 0x94c 0x1 0x3 +-#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS 0x324 0x788 0x7c4 0x2 0x1 +-#define MX35_PAD_FEC_TDATA3__KPP_ROW_7 0x324 0x788 0x98c 0x4 0x1 +-#define MX35_PAD_FEC_TDATA3__GPIO3_23 0x324 0x788 0x000 0x5 0x0 +-#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK 0x000 0x78c 0x000 0x0 0x0 +-#define MX35_PAD_TEST_MODE__TCU_TEST_MODE 0x000 0x790 0x000 0x0 0x0 +- +-#endif /* __DTS_IMX35_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm/imx35.dtsi b/scripts/dtc/include-prefixes/arm/imx35.dtsi +deleted file mode 100644 +index 8e41c8b7bd70..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx35.dtsi ++++ /dev/null +@@ -1,414 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright 2012 Steffen Trumtrar, Pengutronix +-// +-// based on imx27.dtsi +- +-#include "imx35-pinfunc.h" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * The decompressor and also some bootloaders rely on a +- * pre-existing /chosen node to be available to insert the +- * command line and merge other ATAGS info. +- */ +- chosen {}; +- +- aliases { +- ethernet0 = &fec; +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- mmc0 = &esdhc1; +- mmc1 = &esdhc2; +- mmc2 = &esdhc3; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- spi0 = &spi1; +- spi1 = &spi2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,arm1136jf-s"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- avic: avic-interrupt-controller@68000000 { +- compatible = "fsl,imx35-avic", "fsl,avic"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x68000000 0x10000000>; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&avic>; +- ranges; +- +- L2: cache-controller@30000000 { +- compatible = "arm,l210-cache"; +- reg = <0x30000000 0x1000>; +- cache-unified; +- cache-level = <2>; +- }; +- +- aips1: bus@43f00000 { +- compatible = "fsl,aips", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x43f00000 0x100000>; +- ranges; +- +- i2c1: i2c@43f80000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; +- reg = <0x43f80000 0x4000>; +- clocks = <&clks 51>; +- clock-names = "ipg_per"; +- interrupts = <10>; +- status = "disabled"; +- }; +- +- i2c3: i2c@43f84000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; +- reg = <0x43f84000 0x4000>; +- clocks = <&clks 53>; +- clock-names = "ipg_per"; +- interrupts = <3>; +- status = "disabled"; +- }; +- +- uart1: serial@43f90000 { +- compatible = "fsl,imx35-uart", "fsl,imx21-uart"; +- reg = <0x43f90000 0x4000>; +- clocks = <&clks 9>, <&clks 70>; +- clock-names = "ipg", "per"; +- interrupts = <45>; +- status = "disabled"; +- }; +- +- uart2: serial@43f94000 { +- compatible = "fsl,imx35-uart", "fsl,imx21-uart"; +- reg = <0x43f94000 0x4000>; +- clocks = <&clks 9>, <&clks 71>; +- clock-names = "ipg", "per"; +- interrupts = <32>; +- status = "disabled"; +- }; +- +- i2c2: i2c@43f98000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; +- reg = <0x43f98000 0x4000>; +- clocks = <&clks 52>; +- clock-names = "ipg_per"; +- interrupts = <4>; +- status = "disabled"; +- }; +- +- ssi1: ssi@43fa0000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx35-ssi", "fsl,imx21-ssi"; +- reg = <0x43fa0000 0x4000>; +- interrupts = <11>; +- clocks = <&clks 68>; +- dmas = <&sdma 28 0 0>, +- <&sdma 29 0 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- spi1: spi@43fa4000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx35-cspi"; +- reg = <0x43fa4000 0x4000>; +- clocks = <&clks 35 &clks 35>; +- clock-names = "ipg", "per"; +- interrupts = <14>; +- status = "disabled"; +- }; +- +- kpp: kpp@43fa8000 { +- compatible = "fsl,imx35-kpp", "fsl,imx21-kpp"; +- reg = <0x43fa8000 0x4000>; +- interrupts = <24>; +- clocks = <&clks 56>; +- status = "disabled"; +- }; +- +- iomuxc: iomuxc@43fac000 { +- compatible = "fsl,imx35-iomuxc"; +- reg = <0x43fac000 0x4000>; +- }; +- }; +- +- spba: spba-bus@50000000 { +- compatible = "fsl,spba-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x50000000 0x100000>; +- ranges; +- +- uart3: serial@5000c000 { +- compatible = "fsl,imx35-uart", "fsl,imx21-uart"; +- reg = <0x5000c000 0x4000>; +- clocks = <&clks 9>, <&clks 72>; +- clock-names = "ipg", "per"; +- interrupts = <18>; +- status = "disabled"; +- }; +- +- spi2: spi@50010000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx35-cspi"; +- reg = <0x50010000 0x4000>; +- interrupts = <13>; +- clocks = <&clks 36 &clks 36>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- fec: ethernet@50038000 { +- compatible = "fsl,imx35-fec", "fsl,imx27-fec"; +- reg = <0x50038000 0x4000>; +- clocks = <&clks 46>, <&clks 8>; +- clock-names = "ipg", "ahb"; +- interrupts = <57>; +- status = "disabled"; +- }; +- }; +- +- aips2: bus@53f00000 { +- compatible = "fsl,aips", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x53f00000 0x100000>; +- ranges; +- +- clks: ccm@53f80000 { +- compatible = "fsl,imx35-ccm"; +- reg = <0x53f80000 0x4000>; +- interrupts = <31>; +- #clock-cells = <1>; +- }; +- +- gpt: timer@53f90000 { +- compatible = "fsl,imx35-gpt", "fsl,imx31-gpt"; +- reg = <0x53f90000 0x4000>; +- interrupts = <29>; +- clocks = <&clks 9>, <&clks 50>; +- clock-names = "ipg", "per"; +- }; +- +- gpio3: gpio@53fa4000 { +- compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; +- reg = <0x53fa4000 0x4000>; +- interrupts = <56>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- esdhc1: mmc@53fb4000 { +- compatible = "fsl,imx35-esdhc"; +- reg = <0x53fb4000 0x4000>; +- interrupts = <7>; +- clocks = <&clks 9>, <&clks 8>, <&clks 43>; +- clock-names = "ipg", "ahb", "per"; +- status = "disabled"; +- }; +- +- esdhc2: mmc@53fb8000 { +- compatible = "fsl,imx35-esdhc"; +- reg = <0x53fb8000 0x4000>; +- interrupts = <8>; +- clocks = <&clks 9>, <&clks 8>, <&clks 44>; +- clock-names = "ipg", "ahb", "per"; +- status = "disabled"; +- }; +- +- esdhc3: mmc@53fbc000 { +- compatible = "fsl,imx35-esdhc"; +- reg = <0x53fbc000 0x4000>; +- interrupts = <9>; +- clocks = <&clks 9>, <&clks 8>, <&clks 45>; +- clock-names = "ipg", "ahb", "per"; +- status = "disabled"; +- }; +- +- audmux: audmux@53fc4000 { +- compatible = "fsl,imx35-audmux", "fsl,imx31-audmux"; +- reg = <0x53fc4000 0x4000>; +- status = "disabled"; +- }; +- +- gpio1: gpio@53fcc000 { +- compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; +- reg = <0x53fcc000 0x4000>; +- interrupts = <52>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@53fd0000 { +- compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; +- reg = <0x53fd0000 0x4000>; +- interrupts = <51>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- sdma: sdma@53fd4000 { +- compatible = "fsl,imx35-sdma"; +- reg = <0x53fd4000 0x4000>; +- clocks = <&clks 9>, <&clks 65>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- interrupts = <34>; +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx35.bin"; +- }; +- +- wdog: watchdog@53fdc000 { +- compatible = "fsl,imx35-wdt", "fsl,imx21-wdt"; +- reg = <0x53fdc000 0x4000>; +- clocks = <&clks 74>; +- clock-names = ""; +- interrupts = <55>; +- }; +- +- can1: can@53fe4000 { +- compatible = "fsl,imx35-flexcan", "fsl,imx25-flexcan"; +- reg = <0x53fe4000 0x1000>; +- clocks = <&clks 33>, <&clks 33>; +- clock-names = "ipg", "per"; +- interrupts = <43>; +- status = "disabled"; +- }; +- +- can2: can@53fe8000 { +- compatible = "fsl,imx35-flexcan", "fsl,imx25-flexcan"; +- reg = <0x53fe8000 0x1000>; +- clocks = <&clks 34>, <&clks 34>; +- clock-names = "ipg", "per"; +- interrupts = <44>; +- status = "disabled"; +- }; +- +- efuse@53ff0000 { +- compatible = "fsl,imx35-iim"; +- reg = <0x53ff0000 0x4000>; +- interrupts = <19>; +- clocks = <&clks 80>; +- }; +- +- usbotg: usb@53ff4000 { +- compatible = "fsl,imx35-usb", "fsl,imx27-usb"; +- reg = <0x53ff4000 0x0200>; +- interrupts = <37>; +- clocks = <&clks 9>, <&clks 73>, <&clks 28>; +- clock-names = "ipg", "ahb", "per"; +- fsl,usbmisc = <&usbmisc 0>; +- fsl,usbphy = <&usbphy0>; +- status = "disabled"; +- }; +- +- usbhost1: usb@53ff4400 { +- compatible = "fsl,imx35-usb", "fsl,imx27-usb"; +- reg = <0x53ff4400 0x0200>; +- interrupts = <35>; +- clocks = <&clks 9>, <&clks 73>, <&clks 28>; +- clock-names = "ipg", "ahb", "per"; +- fsl,usbmisc = <&usbmisc 1>; +- fsl,usbphy = <&usbphy1>; +- dr_mode = "host"; +- status = "disabled"; +- }; +- +- usbmisc: usbmisc@53ff4600 { +- #index-cells = <1>; +- compatible = "fsl,imx35-usbmisc"; +- reg = <0x53ff4600 0x00f>; +- }; +- }; +- +- emi@80000000 { /* External Memory Interface */ +- compatible = "fsl,emi", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x80000000 0x40000000>; +- ranges; +- +- nfc: nand@bb000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,imx35-nand", "fsl,imx25-nand"; +- reg = <0xbb000000 0x2000>; +- clocks = <&clks 29>; +- clock-names = ""; +- interrupts = <33>; +- status = "disabled"; +- }; +- +- weim: weim@b8002000 { +- #address-cells = <2>; +- #size-cells = <1>; +- clocks = <&clks 0>; +- compatible = "fsl,imx35-weim", "fsl,imx27-weim"; +- reg = <0xb8002000 0x1000>; +- ranges = < +- 0 0 0xa0000000 0x8000000 +- 1 0 0xa8000000 0x8000000 +- 2 0 0xb0000000 0x2000000 +- 3 0 0xb2000000 0x2000000 +- 4 0 0xb4000000 0x2000000 +- 5 0 0xb6000000 0x2000000 +- >; +- status = "disabled"; +- }; +- }; +- }; +- +- usbphy { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- usbphy0: usb-phy@0 { +- reg = <0>; +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- }; +- +- usbphy1: usb-phy@1 { +- reg = <1>; +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx50-evk.dts b/scripts/dtc/include-prefixes/arm/imx50-evk.dts +deleted file mode 100644 +index 4ea5c23f181b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx50-evk.dts ++++ /dev/null +@@ -1,104 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2013 Greg Ungerer +-// Copyright 2011 Freescale Semiconductor, Inc. +-// Copyright 2011 Linaro Ltd. +- +-/dts-v1/; +-#include "imx50.dtsi" +- +-/ { +- model = "Freescale i.MX50 Evaluation Kit"; +- compatible = "fsl,imx50-evk", "fsl,imx50"; +- +- memory@70000000 { +- device_type = "memory"; +- reg = <0x70000000 0x80000000>; +- }; +-}; +- +-&cspi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_cspi>; +- cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>, <&gpio4 13 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- flash: m25p32@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p32", "jedec,spi-nor"; +- spi-max-frequency = <25000000>; +- reg = <1>; +- +- partition@0 { +- label = "bootloader"; +- reg = <0x0 0x100000>; +- read-only; +- }; +- +- partition@100000 { +- label = "kernel"; +- reg = <0x100000 0x300000>; +- }; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-mode = "rmii"; +- phy-reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&iomuxc { +- imx50-evk { +- pinctrl_cspi: cspigrp { +- fsl,pins = < +- MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00 +- MX50_PAD_CSPI_MISO__CSPI_MISO 0x00 +- MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00 +- MX50_PAD_CSPI_SS0__GPIO4_11 0xc4 +- MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x84 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX50_PAD_SSI_RXFS__FEC_MDC 0x80 +- MX50_PAD_SSI_RXC__FEC_MDIO 0x80 +- MX50_PAD_DISP_D0__FEC_TX_CLK 0x80 +- MX50_PAD_DISP_D1__FEC_RX_ERR 0x80 +- MX50_PAD_DISP_D2__FEC_RX_DV 0x80 +- MX50_PAD_DISP_D3__FEC_RDATA_1 0x80 +- MX50_PAD_DISP_D4__FEC_RDATA_0 0x80 +- MX50_PAD_DISP_D5__FEC_TX_EN 0x80 +- MX50_PAD_DISP_D6__FEC_TDATA_1 0x80 +- MX50_PAD_DISP_D7__FEC_TDATA_0 0x80 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4 +- MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4 +- MX50_PAD_UART1_RTS__UART1_RTS 0x1e4 +- MX50_PAD_UART1_CTS__UART1_CTS 0x1e4 +- >; +- }; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbotg { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx50-kobo-aura.dts b/scripts/dtc/include-prefixes/arm/imx50-kobo-aura.dts +deleted file mode 100644 +index 82ce8c43be86..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx50-kobo-aura.dts ++++ /dev/null +@@ -1,287 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// Copyright 2019 Jonathan Neuschäfer +-// +-// The Kobo Aura e-book reader, model N514. The mainboard is marked as E606F0B. +- +-/dts-v1/; +-#include "imx50.dtsi" +-#include +-#include +- +-/ { +- model = "Kobo Aura (N514)"; +- compatible = "kobo,aura", "fsl,imx50"; +- +- chosen { +- stdout-path = "serial1:115200n8"; +- }; +- +- memory@70000000 { +- device_type = "memory"; +- reg = <0x70000000 0x10000000>; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds>; +- +- on { +- label = "kobo_aura:orange:on"; +- gpios = <&gpio6 24 GPIO_ACTIVE_LOW>; +- panic-indicator; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpiokeys>; +- +- power { +- label = "Power Button"; +- gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- hallsensor { +- label = "Hallsensor"; +- gpios = <&gpio5 15 GPIO_ACTIVE_LOW>; +- linux,code = ; +- linux,input-type = ; +- }; +- +- frontlight { +- label = "Frontlight"; +- gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- sd2_pwrseq: pwrseq { +- compatible = "mmc-pwrseq-simple"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sd2_reset>; +- reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; +- }; +- +- sd2_vmmc: gpio-regulator { +- compatible = "regulator-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sd2_vmmc>; +- regulator-name = "vmmc"; +- states = <3300000 0>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-gpio = <&gpio4 12 GPIO_ACTIVE_LOW>; +- startup-delay-us = <100000>; +- }; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sd1>; +- max-frequency = <50000000>; +- bus-width = <4>; +- cd-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; +- disable-wp; +- status = "okay"; +- +- /* External µSD card */ +-}; +- +-&esdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sd2>; +- bus-width = <4>; +- max-frequency = <50000000>; +- disable-wp; +- mmc-pwrseq = <&sd2_pwrseq>; +- vmmc-supply = <&sd2_vmmc>; +- status = "okay"; +- +- /* CyberTan WC121 SDIO WiFi (BCM43362) */ +-}; +- +-&esdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sd3>; +- bus-width = <8>; +- non-removable; +- max-frequency = <50000000>; +- disable-wp; +- status = "okay"; +- +- /* Internal eMMC */ +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- touchscreen@15 { +- reg = <0x15>; +- compatible = "elan,ektf2132"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ts>; +- power-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; +- interrupts-extended = <&gpio5 13 IRQ_TYPE_EDGE_FALLING>; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- /* TODO: TPS65185 PMIC for E Ink at 0x68 */ +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- embedded-controller@43 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ec>; +- compatible = "netronix,ntxec"; +- reg = <0x43>; +- system-power-controller; +- interrupts-extended = <&gpio4 11 IRQ_TYPE_EDGE_FALLING>; +- #pwm-cells = <2>; +- }; +-}; +- +-&iomuxc { +- pinctrl_ec: ecgrp { +- fsl,pins = < +- MX50_PAD_CSPI_SS0__GPIO4_11 0x0 /* INT */ +- >; +- }; +- +- pinctrl_gpiokeys: gpiokeysgrp { +- fsl,pins = < +- MX50_PAD_CSPI_MISO__GPIO4_10 0x0 +- MX50_PAD_SD2_D7__GPIO5_15 0x0 +- MX50_PAD_KEY_ROW0__GPIO4_1 0x0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX50_PAD_I2C1_SCL__I2C1_SCL 0x400001fd +- MX50_PAD_I2C1_SDA__I2C1_SDA 0x400001fd +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX50_PAD_I2C2_SCL__I2C2_SCL 0x400001fd +- MX50_PAD_I2C2_SDA__I2C2_SDA 0x400001fd +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX50_PAD_I2C3_SCL__I2C3_SCL 0x400001fd +- MX50_PAD_I2C3_SDA__I2C3_SDA 0x400001fd +- >; +- }; +- +- pinctrl_leds: ledsgrp { +- fsl,pins = < +- MX50_PAD_PWM1__GPIO6_24 0x0 +- >; +- }; +- +- pinctrl_sd1: sd1grp { +- fsl,pins = < +- MX50_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 +- MX50_PAD_SD1_CLK__ESDHC1_CLK 0xd4 +- MX50_PAD_SD1_D0__ESDHC1_DAT0 0x1d4 +- MX50_PAD_SD1_D1__ESDHC1_DAT1 0x1d4 +- MX50_PAD_SD1_D2__ESDHC1_DAT2 0x1d4 +- MX50_PAD_SD1_D3__ESDHC1_DAT3 0x1d4 +- +- MX50_PAD_SD2_CD__GPIO5_17 0x0 +- >; +- }; +- +- pinctrl_sd2: sd2grp { +- fsl,pins = < +- MX50_PAD_SD2_CMD__ESDHC2_CMD 0x1e4 +- MX50_PAD_SD2_CLK__ESDHC2_CLK 0xd4 +- MX50_PAD_SD2_D0__ESDHC2_DAT0 0x1d4 +- MX50_PAD_SD2_D1__ESDHC2_DAT1 0x1d4 +- MX50_PAD_SD2_D2__ESDHC2_DAT2 0x1d4 +- MX50_PAD_SD2_D3__ESDHC2_DAT3 0x1d4 +- >; +- }; +- +- pinctrl_sd2_reset: sd2-resetgrp { +- fsl,pins = < +- MX50_PAD_ECSPI2_MOSI__GPIO4_17 0x0 +- >; +- }; +- +- pinctrl_sd2_vmmc: sd2-vmmcgrp { +- fsl,pins = < +- MX50_PAD_ECSPI1_SCLK__GPIO4_12 0x0 +- >; +- }; +- +- pinctrl_sd3: sd3grp { +- fsl,pins = < +- MX50_PAD_SD3_CMD__ESDHC3_CMD 0x1e4 +- MX50_PAD_SD3_CLK__ESDHC3_CLK 0xd4 +- MX50_PAD_SD3_D0__ESDHC3_DAT0 0x1d4 +- MX50_PAD_SD3_D1__ESDHC3_DAT1 0x1d4 +- MX50_PAD_SD3_D2__ESDHC3_DAT2 0x1d4 +- MX50_PAD_SD3_D3__ESDHC3_DAT3 0x1d4 +- MX50_PAD_SD3_D4__ESDHC3_DAT4 0x1d4 +- MX50_PAD_SD3_D5__ESDHC3_DAT5 0x1d4 +- MX50_PAD_SD3_D6__ESDHC3_DAT6 0x1d4 +- MX50_PAD_SD3_D7__ESDHC3_DAT7 0x1d4 +- >; +- }; +- +- pinctrl_ts: tsgrp { +- fsl,pins = < +- MX50_PAD_CSPI_MOSI__GPIO4_9 0x0 +- MX50_PAD_SD2_D5__GPIO5_13 0x0 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x1e4 +- MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x1e4 +- >; +- }; +- +- pinctrl_usbphy: usbphygrp { +- fsl,pins = < +- MX50_PAD_ECSPI2_SS0__GPIO4_19 0x0 +- >; +- }; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usbotg { +- phy_type = "utmi_wide"; +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usbphy0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbphy>; +- vbus-detect-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx50-pinfunc.h b/scripts/dtc/include-prefixes/arm/imx50-pinfunc.h +deleted file mode 100644 +index 5e6b30247543..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx50-pinfunc.h ++++ /dev/null +@@ -1,919 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2013 Greg Ungerer +- */ +- +-#ifndef __DTS_IMX50_PINFUNC_H +-#define __DTS_IMX50_PINFUNC_H +- +-/* +- * The pin function ID is a tuple of +- * +- */ +-#define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0 +-#define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0 +-#define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0 +-#define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0 +-#define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0 +-#define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0 +-#define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0 +-#define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0 +-#define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0 +-#define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0 +-#define MX50_PAD_KEY_COL1__KPP_COL_1 0x028 0x2d4 0x000 0x0 0x0 +-#define MX50_PAD_KEY_COL1__GPIO4_2 0x028 0x2d4 0x000 0x1 0x0 +-#define MX50_PAD_KEY_COL1__EIM_NANDF_CEN_0 0x028 0x2d4 0x000 0x2 0x0 +-#define MX50_PAD_KEY_COL1__CTI_TRIGOUT_ACK6 0x028 0x2d4 0x000 0x6 0x0 +-#define MX50_PAD_KEY_COL1__USBPHY1_RXACTIVE 0x028 0x2d4 0x000 0x7 0x0 +-#define MX50_PAD_KEY_ROW1__KPP_ROW_1 0x02c 0x2d8 0x000 0x0 0x0 +-#define MX50_PAD_KEY_ROW1__GPIO4_3 0x02c 0x2d8 0x000 0x1 0x0 +-#define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1 0x02c 0x2d8 0x000 0x2 0x0 +-#define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7 0x02c 0x2d8 0x000 0x6 0x0 +-#define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR 0x02c 0x2d8 0x000 0x7 0x0 +-#define MX50_PAD_KEY_COL2__KPP_COL_2 0x030 0x2dc 0x000 0x0 0x0 +-#define MX50_PAD_KEY_COL2__GPIO4_4 0x030 0x2dc 0x000 0x1 0x0 +-#define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2 0x030 0x2dc 0x000 0x2 0x0 +-#define MX50_PAD_KEY_COL2__CTI_TRIGOUT6 0x030 0x2dc 0x000 0x6 0x0 +-#define MX50_PAD_KEY_COL2__USBPHY1_SIECLOCK 0x030 0x2dc 0x000 0x7 0x0 +-#define MX50_PAD_KEY_ROW2__KPP_ROW_2 0x034 0x2e0 0x000 0x0 0x0 +-#define MX50_PAD_KEY_ROW2__GPIO4_5 0x034 0x2e0 0x000 0x1 0x0 +-#define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3 0x034 0x2e0 0x000 0x2 0x0 +-#define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7 0x034 0x2e0 0x000 0x6 0x0 +-#define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0 0x034 0x2e0 0x000 0x7 0x0 +-#define MX50_PAD_KEY_COL3__KPP_COL_3 0x038 0x2e4 0x000 0x0 0x0 +-#define MX50_PAD_KEY_COL3__GPIO4_6 0x038 0x2e4 0x000 0x1 0x0 +-#define MX50_PAD_KEY_COL3__EIM_NANDF_READY0 0x038 0x2e4 0x7b4 0x2 0x0 +-#define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0 0x038 0x2e4 0x7b8 0x6 0x0 +-#define MX50_PAD_KEY_COL3__USBPHY1_LINESTATE_1 0x038 0x2e4 0x000 0x7 0x0 +-#define MX50_PAD_KEY_ROW3__KPP_ROW_3 0x03c 0x2e8 0x000 0x0 0x0 +-#define MX50_PAD_KEY_ROW3__GPIO4_7 0x03c 0x2e8 0x000 0x1 0x0 +-#define MX50_PAD_KEY_ROW3__EIM_NANDF_DQS 0x03c 0x2e8 0x7b0 0x2 0x0 +-#define MX50_PAD_KEY_ROW3__SDMA_EXT_EVENT_1 0x03c 0x2e8 0x7bc 0x6 0x0 +-#define MX50_PAD_KEY_ROW3__USBPHY1_VBUSVALID 0x03c 0x2e8 0x000 0x7 0x0 +-#define MX50_PAD_I2C1_SCL__I2C1_SCL 0x040 0x2ec 0x000 0x0 0x0 +-#define MX50_PAD_I2C1_SCL__GPIO6_18 0x040 0x2ec 0x000 0x1 0x0 +-#define MX50_PAD_I2C1_SCL__UART2_TXD_MUX 0x040 0x2ec 0x7cc 0x2 0x0 +-#define MX50_PAD_I2C1_SDA__I2C1_SDA 0x044 0x2f0 0x000 0x0 0x0 +-#define MX50_PAD_I2C1_SDA__GPIO6_19 0x044 0x2f0 0x000 0x1 0x0 +-#define MX50_PAD_I2C1_SDA__UART2_RXD_MUX 0x044 0x2f0 0x7cc 0x2 0x1 +-#define MX50_PAD_I2C2_SCL__I2C2_SCL 0x048 0x2f4 0x000 0x0 0x0 +-#define MX50_PAD_I2C2_SCL__GPIO6_20 0x048 0x2f4 0x000 0x1 0x0 +-#define MX50_PAD_I2C2_SCL__UART2_CTS 0x048 0x2f4 0x000 0x2 0x0 +-#define MX50_PAD_I2C2_SDA__I2C2_SDA 0x04c 0x2f8 0x000 0x0 0x0 +-#define MX50_PAD_I2C2_SDA__GPIO6_21 0x04c 0x2f8 0x000 0x1 0x0 +-#define MX50_PAD_I2C2_SDA__UART2_RTS 0x04c 0x2f8 0x7c8 0x2 0x1 +-#define MX50_PAD_I2C3_SCL__I2C3_SCL 0x050 0x2fc 0x000 0x0 0x0 +-#define MX50_PAD_I2C3_SCL__GPIO6_22 0x050 0x2fc 0x000 0x1 0x0 +-#define MX50_PAD_I2C3_SCL__FEC_MDC 0x050 0x2fc 0x000 0x2 0x0 +-#define MX50_PAD_I2C3_SCL__GPC_PMIC_RDY 0x050 0x2fc 0x000 0x3 0x0 +-#define MX50_PAD_I2C3_SCL__GPT_CAPIN1 0x050 0x2fc 0x000 0x5 0x0 +-#define MX50_PAD_I2C3_SCL__OBSERVE_MUX_OBSRV_INT_OUT0 0x050 0x2fc 0x000 0x6 0x0 +-#define MX50_PAD_I2C3_SCL__USBOH1_USBOTG_OC 0x050 0x2fc 0x7e8 0x7 0x0 +-#define MX50_PAD_I2C3_SDA__I2C3_SDA 0x054 0x300 0x000 0x0 0x0 +-#define MX50_PAD_I2C3_SDA__GPIO6_23 0x054 0x300 0x000 0x1 0x0 +-#define MX50_PAD_I2C3_SDA__FEC_MDIO 0x054 0x300 0x774 0x2 0x0 +-#define MX50_PAD_I2C3_SDA__TZIC_PWRFAIL_INT 0x054 0x300 0x000 0x3 0x0 +-#define MX50_PAD_I2C3_SDA__SRTC_ALARM_DEB 0x054 0x300 0x000 0x4 0x0 +-#define MX50_PAD_I2C3_SDA__GPT_CAPIN2 0x054 0x300 0x000 0x5 0x0 +-#define MX50_PAD_I2C3_SDA__OBSERVE_MUX_OBSRV_INT_OUT1 0x054 0x300 0x000 0x6 0x0 +-#define MX50_PAD_I2C3_SDA__USBOH1_USBOTG_PWR 0x054 0x300 0x000 0x7 0x0 +-#define MX50_PAD_PWM1__PWM1_PWMO 0x058 0x304 0x000 0x0 0x0 +-#define MX50_PAD_PWM1__GPIO6_24 0x058 0x304 0x000 0x1 0x0 +-#define MX50_PAD_PWM1__USBOH1_USBOTG_OC 0x058 0x304 0x7e8 0x2 0x1 +-#define MX50_PAD_PWM1__GPT_CMPOUT1 0x058 0x304 0x000 0x5 0x0 +-#define MX50_PAD_PWM1__OBSERVE_MUX_OBSRV_INT_OUT2 0x058 0x304 0x000 0x6 0x0 +-#define MX50_PAD_PWM1__SJC_FAIL 0x058 0x304 0x000 0x7 0x0 +-#define MX50_PAD_PWM2__PWM2_PWMO 0x05c 0x308 0x000 0x0 0x0 +-#define MX50_PAD_PWM2__GPIO6_25 0x05c 0x308 0x000 0x1 0x0 +-#define MX50_PAD_PWM2__USBOH1_USBOTG_PWR 0x05c 0x308 0x000 0x2 0x0 +-#define MX50_PAD_PWM2__GPT_CMPOUT2 0x05c 0x308 0x000 0x5 0x0 +-#define MX50_PAD_PWM2__OBSERVE_MUX_OBSRV_INT_OUT3 0x05c 0x308 0x000 0x6 0x0 +-#define MX50_PAD_PWM2__SRC_ANY_PU_RST 0x05c 0x308 0x000 0x7 0x0 +-#define MX50_PAD_OWIRE__OWIRE_LINE 0x060 0x30c 0x000 0x0 0x0 +-#define MX50_PAD_OWIRE__GPIO6_26 0x060 0x30c 0x000 0x1 0x0 +-#define MX50_PAD_OWIRE__USBOH1_USBH1_OC 0x060 0x30c 0x000 0x2 0x0 +-#define MX50_PAD_OWIRE__CCM_SSI_EXT1_CLK 0x060 0x30c 0x000 0x3 0x0 +-#define MX50_PAD_OWIRE__EPDC_PWRIRQ 0x060 0x30c 0x000 0x4 0x0 +-#define MX50_PAD_OWIRE__GPT_CMPOUT3 0x060 0x30c 0x000 0x5 0x0 +-#define MX50_PAD_OWIRE__OBSERVE_MUX_OBSRV_INT_OUT4 0x060 0x30c 0x000 0x6 0x0 +-#define MX50_PAD_OWIRE__SJC_JTAG_ACT 0x060 0x30c 0x000 0x7 0x0 +-#define MX50_PAD_EPITO__EPIT1_EPITO 0x064 0x310 0x000 0x0 0x0 +-#define MX50_PAD_EPITO__GPIO6_27 0x064 0x310 0x000 0x1 0x0 +-#define MX50_PAD_EPITO__USBOH1_USBH1_PWR 0x064 0x310 0x000 0x2 0x0 +-#define MX50_PAD_EPITO__CCM_SSI_EXT2_CLK 0x064 0x310 0x000 0x3 0x0 +-#define MX50_PAD_EPITO__DPLLIP1_TOG_EN 0x064 0x310 0x000 0x4 0x0 +-#define MX50_PAD_EPITO__GPT_CLK_IN 0x064 0x310 0x000 0x5 0x0 +-#define MX50_PAD_EPITO__PMU_IRQ_B 0x064 0x310 0x000 0x6 0x0 +-#define MX50_PAD_EPITO__SJC_DE_B 0x064 0x310 0x000 0x7 0x0 +-#define MX50_PAD_WDOG__WDOG1_WDOG_B 0x068 0x314 0x000 0x0 0x0 +-#define MX50_PAD_WDOG__GPIO6_28 0x068 0x314 0x000 0x1 0x0 +-#define MX50_PAD_WDOG__WDOG1_WDOG_RST_B_DEB 0x068 0x314 0x000 0x2 0x0 +-#define MX50_PAD_WDOG__CCM_XTAL32K 0x068 0x314 0x000 0x6 0x0 +-#define MX50_PAD_WDOG__SJC_DONE 0x068 0x314 0x000 0x7 0x0 +-#define MX50_PAD_SSI_TXFS__AUDMUX_AUD3_TXFS 0x06c 0x318 0x000 0x0 0x0 +-#define MX50_PAD_SSI_TXFS__GPIO6_0 0x06c 0x318 0x000 0x1 0x0 +-#define MX50_PAD_SSI_TXFS__SRC_BT_FUSE_RSV_1 0x06c 0x318 0x000 0x6 0x0 +-#define MX50_PAD_SSI_TXFS__USBPHY1_DATAOUT_8 0x06c 0x318 0x000 0x7 0x0 +-#define MX50_PAD_SSI_TXC__AUDMUX_AUD3_TXC 0x070 0x31c 0x000 0x0 0x0 +-#define MX50_PAD_SSI_TXC__GPIO6_1 0x070 0x31c 0x000 0x1 0x0 +-#define MX50_PAD_SSI_TXC__SRC_BT_FUSE_RSV_0 0x070 0x31c 0x000 0x6 0x0 +-#define MX50_PAD_SSI_TXC__USBPHY1_DATAOUT_9 0x070 0x31c 0x000 0x7 0x0 +-#define MX50_PAD_SSI_TXD__AUDMUX_AUD3_TXD 0x074 0x320 0x000 0x0 0x0 +-#define MX50_PAD_SSI_TXD__GPIO6_2 0x074 0x320 0x000 0x1 0x0 +-#define MX50_PAD_SSI_TXD__CSPI_RDY 0x074 0x320 0x6e8 0x4 0x0 +-#define MX50_PAD_SSI_TXD__USBPHY1_DATAOUT_10 0x074 0x320 0x000 0x7 0x0 +-#define MX50_PAD_SSI_RXD__AUDMUX_AUD3_RXD 0x078 0x324 0x000 0x0 0x0 +-#define MX50_PAD_SSI_RXD__GPIO6_3 0x078 0x324 0x000 0x1 0x0 +-#define MX50_PAD_SSI_RXD__CSPI_SS3 0x078 0x324 0x6f4 0x4 0x0 +-#define MX50_PAD_SSI_RXD__USBPHY1_DATAOUT_11 0x078 0x324 0x000 0x7 0x0 +-#define MX50_PAD_SSI_RXFS__AUDMUX_AUD3_RXFS 0x07c 0x328 0x000 0x0 0x0 +-#define MX50_PAD_SSI_RXFS__GPIO6_4 0x07c 0x328 0x000 0x1 0x0 +-#define MX50_PAD_SSI_RXFS__UART5_TXD_MUX 0x07c 0x328 0x7e4 0x2 0x0 +-#define MX50_PAD_SSI_RXFS__EIM_WEIM_D_6 0x07c 0x328 0x804 0x3 0x0 +-#define MX50_PAD_SSI_RXFS__CSPI_SS2 0x07c 0x328 0x6f0 0x4 0x0 +-#define MX50_PAD_SSI_RXFS__FEC_COL 0x07c 0x328 0x770 0x5 0x0 +-#define MX50_PAD_SSI_RXFS__FEC_MDC 0x07c 0x328 0x000 0x6 0x0 +-#define MX50_PAD_SSI_RXFS__USBPHY1_DATAOUT_12 0x07c 0x328 0x000 0x7 0x0 +-#define MX50_PAD_SSI_RXC__AUDMUX_AUD3_RXC 0x080 0x32c 0x000 0x0 0x0 +-#define MX50_PAD_SSI_RXC__GPIO6_5 0x080 0x32c 0x000 0x1 0x0 +-#define MX50_PAD_SSI_RXC__UART5_RXD_MUX 0x080 0x32c 0x7e4 0x2 0x1 +-#define MX50_PAD_SSI_RXC__EIM_WEIM_D_7 0x080 0x32c 0x808 0x3 0x0 +-#define MX50_PAD_SSI_RXC__CSPI_SS1 0x080 0x32c 0x6ec 0x4 0x0 +-#define MX50_PAD_SSI_RXC__FEC_RX_CLK 0x080 0x32c 0x780 0x5 0x0 +-#define MX50_PAD_SSI_RXC__FEC_MDIO 0x080 0x32c 0x774 0x6 0x1 +-#define MX50_PAD_SSI_RXC__USBPHY1_DATAOUT_13 0x080 0x32c 0x000 0x7 0x0 +-#define MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x084 0x330 0x7c4 0x0 0x0 +-#define MX50_PAD_UART1_TXD__GPIO6_6 0x084 0x330 0x000 0x1 0x0 +-#define MX50_PAD_UART1_TXD__USBPHY1_DATAOUT_14 0x084 0x330 0x000 0x7 0x0 +-#define MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x088 0x334 0x7c4 0x0 0x1 +-#define MX50_PAD_UART1_RXD__GPIO6_7 0x088 0x334 0x000 0x1 0x0 +-#define MX50_PAD_UART1_RXD__USBPHY1_DATAOUT_15 0x088 0x334 0x000 0x7 0x0 +-#define MX50_PAD_UART1_CTS__UART1_CTS 0x08c 0x338 0x000 0x0 0x0 +-#define MX50_PAD_UART1_CTS__GPIO6_8 0x08c 0x338 0x000 0x1 0x0 +-#define MX50_PAD_UART1_CTS__UART5_TXD_MUX 0x08c 0x338 0x7e4 0x2 0x2 +-#define MX50_PAD_UART1_CTS__ESDHC4_DAT4 0x08c 0x338 0x760 0x4 0x0 +-#define MX50_PAD_UART1_CTS__ESDHC4_CMD 0x08c 0x338 0x74c 0x5 0x0 +-#define MX50_PAD_UART1_CTS__USBPHY2_DATAOUT_8 0x08c 0x338 0x000 0x7 0x0 +-#define MX50_PAD_UART1_RTS__UART1_RTS 0x090 0x33c 0x7c0 0x0 0x3 +-#define MX50_PAD_UART1_RTS__GPIO6_9 0x090 0x33c 0x000 0x1 0x0 +-#define MX50_PAD_UART1_RTS__UART5_RXD_MUX 0x090 0x33c 0x7e4 0x2 0x3 +-#define MX50_PAD_UART1_RTS__ESDHC4_DAT5 0x090 0x33c 0x764 0x4 0x0 +-#define MX50_PAD_UART1_RTS__ESDHC4_CLK 0x090 0x33c 0x748 0x5 0x0 +-#define MX50_PAD_UART1_RTS__USBPHY2_DATAOUT_9 0x090 0x33c 0x000 0x7 0x0 +-#define MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x094 0x340 0x7cc 0x0 0x2 +-#define MX50_PAD_UART2_TXD__GPIO6_10 0x094 0x340 0x000 0x1 0x0 +-#define MX50_PAD_UART2_TXD__ESDHC4_DAT6 0x094 0x340 0x768 0x4 0x0 +-#define MX50_PAD_UART2_TXD__ESDHC4_DAT4 0x094 0x340 0x760 0x5 0x1 +-#define MX50_PAD_UART2_TXD__USBPHY2_DATAOUT_10 0x094 0x340 0x000 0x7 0x0 +-#define MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x098 0x344 0x7cc 0x0 0x3 +-#define MX50_PAD_UART2_RXD__GPIO6_11 0x098 0x344 0x000 0x1 0x0 +-#define MX50_PAD_UART2_RXD__ESDHC4_DAT7 0x098 0x344 0x76c 0x4 0x0 +-#define MX50_PAD_UART2_RXD__ESDHC4_DAT5 0x098 0x344 0x764 0x5 0x1 +-#define MX50_PAD_UART2_RXD__USBPHY2_DATAOUT_11 0x098 0x344 0x000 0x7 0x0 +-#define MX50_PAD_UART2_CTS__UART2_CTS 0x09c 0x348 0x000 0x0 0x0 +-#define MX50_PAD_UART2_CTS__GPIO6_12 0x09c 0x348 0x000 0x1 0x0 +-#define MX50_PAD_UART2_CTS__ESDHC4_CMD 0x09c 0x348 0x74c 0x4 0x1 +-#define MX50_PAD_UART2_CTS__ESDHC4_DAT6 0x09c 0x348 0x768 0x5 0x1 +-#define MX50_PAD_UART2_CTS__USBPHY2_DATAOUT_12 0x09c 0x348 0x000 0x7 0x0 +-#define MX50_PAD_UART2_RTS__UART2_RTS 0x0a0 0x34c 0x7c8 0x0 0x2 +-#define MX50_PAD_UART2_RTS__GPIO6_13 0x0a0 0x34c 0x000 0x1 0x0 +-#define MX50_PAD_UART2_RTS__ESDHC4_CLK 0x0a0 0x34c 0x748 0x4 0x1 +-#define MX50_PAD_UART2_RTS__ESDHC4_DAT7 0x0a0 0x34c 0x76c 0x5 0x1 +-#define MX50_PAD_UART2_RTS__USBPHY2_DATAOUT_13 0x0a0 0x34c 0x000 0x7 0x0 +-#define MX50_PAD_UART3_TXD__UART3_TXD_MUX 0x0a4 0x350 0x7d4 0x0 0x0 +-#define MX50_PAD_UART3_TXD__GPIO6_14 0x0a4 0x350 0x000 0x1 0x0 +-#define MX50_PAD_UART3_TXD__ESDHC1_DAT4 0x0a4 0x350 0x000 0x3 0x0 +-#define MX50_PAD_UART3_TXD__ESDHC4_DAT0 0x0a4 0x350 0x000 0x4 0x0 +-#define MX50_PAD_UART3_TXD__ESDHC2_WP 0x0a4 0x350 0x744 0x5 0x0 +-#define MX50_PAD_UART3_TXD__EIM_WEIM_D_12 0x0a4 0x350 0x81c 0x6 0x0 +-#define MX50_PAD_UART3_TXD__USBPHY2_DATAOUT_14 0x0a4 0x350 0x000 0x7 0x0 +-#define MX50_PAD_UART3_RXD__UART3_RXD_MUX 0x0a8 0x354 0x7d4 0x0 0x1 +-#define MX50_PAD_UART3_RXD__GPIO6_15 0x0a8 0x354 0x000 0x1 0x0 +-#define MX50_PAD_UART3_RXD__ESDHC1_DAT5 0x0a8 0x354 0x000 0x3 0x0 +-#define MX50_PAD_UART3_RXD__ESDHC4_DAT1 0x0a8 0x354 0x754 0x4 0x0 +-#define MX50_PAD_UART3_RXD__ESDHC2_CD 0x0a8 0x354 0x740 0x5 0x0 +-#define MX50_PAD_UART3_RXD__EIM_WEIM_D_13 0x0a8 0x354 0x820 0x6 0x0 +-#define MX50_PAD_UART3_RXD__USBPHY2_DATAOUT_15 0x0a8 0x354 0x000 0x7 0x0 +-#define MX50_PAD_UART4_TXD__UART4_TXD_MUX 0x0ac 0x358 0x7dc 0x0 0x0 +-#define MX50_PAD_UART4_TXD__GPIO6_16 0x0ac 0x358 0x000 0x1 0x0 +-#define MX50_PAD_UART4_TXD__UART3_CTS 0x0ac 0x358 0x7d0 0x2 0x0 +-#define MX50_PAD_UART4_TXD__ESDHC1_DAT6 0x0ac 0x358 0x000 0x3 0x0 +-#define MX50_PAD_UART4_TXD__ESDHC4_DAT2 0x0ac 0x358 0x758 0x4 0x0 +-#define MX50_PAD_UART4_TXD__ESDHC2_LCTL 0x0ac 0x358 0x000 0x5 0x0 +-#define MX50_PAD_UART4_TXD__EIM_WEIM_D_14 0x0ac 0x358 0x824 0x6 0x0 +-#define MX50_PAD_UART4_RXD__UART4_RXD_MUX 0x0b0 0x35c 0x7dc 0x0 0x1 +-#define MX50_PAD_UART4_RXD__GPIO6_17 0x0b0 0x35c 0x000 0x1 0x0 +-#define MX50_PAD_UART4_RXD__UART3_RTS 0x0b0 0x35c 0x7d0 0x2 0x1 +-#define MX50_PAD_UART4_RXD__ESDHC1_DAT7 0x0b0 0x35c 0x000 0x3 0x0 +-#define MX50_PAD_UART4_RXD__ESDHC4_DAT3 0x0b0 0x35c 0x75c 0x4 0x0 +-#define MX50_PAD_UART4_RXD__ESDHC1_LCTL 0x0b0 0x35c 0x000 0x5 0x0 +-#define MX50_PAD_UART4_RXD__EIM_WEIM_D_15 0x0b0 0x35c 0x828 0x6 0x0 +-#define MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x0b4 0x360 0x000 0x0 0x0 +-#define MX50_PAD_CSPI_SCLK__GPIO4_8 0x0b4 0x360 0x000 0x1 0x0 +-#define MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x0b8 0x364 0x000 0x0 0x0 +-#define MX50_PAD_CSPI_MOSI__GPIO4_9 0x0b8 0x364 0x000 0x1 0x0 +-#define MX50_PAD_CSPI_MISO__CSPI_MISO 0x0bc 0x368 0x000 0x0 0x0 +-#define MX50_PAD_CSPI_MISO__GPIO4_10 0x0bc 0x368 0x000 0x1 0x0 +-#define MX50_PAD_CSPI_SS0__CSPI_SS0 0x0c0 0x36c 0x000 0x0 0x0 +-#define MX50_PAD_CSPI_SS0__GPIO4_11 0x0c0 0x36c 0x000 0x1 0x0 +-#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x0c4 0x370 0x000 0x0 0x0 +-#define MX50_PAD_ECSPI1_SCLK__GPIO4_12 0x0c4 0x370 0x000 0x1 0x0 +-#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY 0x0c4 0x370 0x6e8 0x2 0x1 +-#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY 0x0c4 0x370 0x000 0x3 0x0 +-#define MX50_PAD_ECSPI1_SCLK__UART3_RTS 0x0c4 0x370 0x7d0 0x4 0x2 +-#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE_6 0x0c4 0x370 0x000 0x5 0x0 +-#define MX50_PAD_ECSPI1_SCLK__EIM_WEIM_D_8 0x0c4 0x370 0x80c 0x7 0x0 +-#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x0c8 0x374 0x000 0x0 0x0 +-#define MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x0c8 0x374 0x000 0x1 0x0 +-#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0x0c8 0x374 0x6ec 0x2 0x1 +-#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 0x0c8 0x374 0x000 0x3 0x0 +-#define MX50_PAD_ECSPI1_MOSI__UART3_CTS 0x0c8 0x374 0x000 0x4 0x0 +-#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE_7 0x0c8 0x374 0x000 0x5 0x0 +-#define MX50_PAD_ECSPI1_MOSI__EIM_WEIM_D_9 0x0c8 0x374 0x810 0x7 0x0 +-#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO 0x0cc 0x378 0x000 0x0 0x0 +-#define MX50_PAD_ECSPI1_MISO__GPIO4_14 0x0cc 0x378 0x000 0x1 0x0 +-#define MX50_PAD_ECSPI1_MISO__CSPI_SS2 0x0cc 0x378 0x6f0 0x2 0x1 +-#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 0x0cc 0x378 0x000 0x3 0x0 +-#define MX50_PAD_ECSPI1_MISO__UART4_RTS 0x0cc 0x378 0x7d8 0x4 0x0 +-#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE_8 0x0cc 0x378 0x000 0x5 0x0 +-#define MX50_PAD_ECSPI1_MISO__EIM_WEIM_D_10 0x0cc 0x378 0x814 0x7 0x0 +-#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 0x0d0 0x37c 0x000 0x0 0x0 +-#define MX50_PAD_ECSPI1_SS0__GPIO4_15 0x0d0 0x37c 0x000 0x1 0x0 +-#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 0x0d0 0x37c 0x6f4 0x2 0x1 +-#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 0x0d0 0x37c 0x000 0x3 0x0 +-#define MX50_PAD_ECSPI1_SS0__UART4_CTS 0x0d0 0x37c 0x000 0x4 0x0 +-#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE_9 0x0d0 0x37c 0x000 0x5 0x0 +-#define MX50_PAD_ECSPI1_SS0__EIM_WEIM_D_11 0x0d0 0x37c 0x818 0x7 0x0 +-#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x0d4 0x380 0x000 0x0 0x0 +-#define MX50_PAD_ECSPI2_SCLK__GPIO4_16 0x0d4 0x380 0x000 0x1 0x0 +-#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR_RWN 0x0d4 0x380 0x000 0x2 0x0 +-#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY 0x0d4 0x380 0x000 0x3 0x0 +-#define MX50_PAD_ECSPI2_SCLK__UART5_RTS 0x0d4 0x380 0x7e0 0x4 0x0 +-#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK 0x0d4 0x380 0x000 0x5 0x0 +-#define MX50_PAD_ECSPI2_SCLK__EIM_NANDF_CEN_4 0x0d4 0x380 0x000 0x6 0x0 +-#define MX50_PAD_ECSPI2_SCLK__EIM_WEIM_D_8 0x0d4 0x380 0x80c 0x7 0x1 +-#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x0d8 0x384 0x000 0x0 0x0 +-#define MX50_PAD_ECSPI2_MOSI__GPIO4_17 0x0d8 0x384 0x000 0x1 0x0 +-#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RE_E 0x0d8 0x384 0x000 0x2 0x0 +-#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 0x0d8 0x384 0x000 0x3 0x0 +-#define MX50_PAD_ECSPI2_MOSI__UART5_CTS 0x0d8 0x384 0x7e0 0x4 0x1 +-#define MX50_PAD_ECSPI2_MOSI__ELCDIF_ENABLE 0x0d8 0x384 0x000 0x5 0x0 +-#define MX50_PAD_ECSPI2_MOSI__EIM_NANDF_CEN_5 0x0d8 0x384 0x000 0x6 0x0 +-#define MX50_PAD_ECSPI2_MOSI__EIM_WEIM_D_9 0x0d8 0x384 0x810 0x7 0x1 +-#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO 0x0dc 0x388 0x000 0x0 0x0 +-#define MX50_PAD_ECSPI2_MISO__GPIO4_18 0x0dc 0x388 0x000 0x1 0x0 +-#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS 0x0dc 0x388 0x000 0x2 0x0 +-#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 0x0dc 0x388 0x000 0x3 0x0 +-#define MX50_PAD_ECSPI2_MISO__UART5_TXD_MUX 0x0dc 0x388 0x7e4 0x4 0x4 +-#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC 0x0dc 0x388 0x73c 0x5 0x0 +-#define MX50_PAD_ECSPI2_MISO__EIM_NANDF_CEN_6 0x0dc 0x388 0x000 0x6 0x0 +-#define MX50_PAD_ECSPI2_MISO__EIM_WEIM_D_10 0x0dc 0x388 0x814 0x7 0x1 +-#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 0x0e0 0x38c 0x000 0x0 0x0 +-#define MX50_PAD_ECSPI2_SS0__GPIO4_19 0x0e0 0x38c 0x000 0x1 0x0 +-#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS 0x0e0 0x38c 0x000 0x2 0x0 +-#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS3 0x0e0 0x38c 0x000 0x3 0x0 +-#define MX50_PAD_ECSPI2_SS0__UART5_RXD_MUX 0x0e0 0x38c 0x7e4 0x4 0x5 +-#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC 0x0e0 0x38c 0x6f8 0x5 0x0 +-#define MX50_PAD_ECSPI2_SS0__EIM_NANDF_CEN_7 0x0e0 0x38c 0x000 0x6 0x0 +-#define MX50_PAD_ECSPI2_SS0__EIM_WEIM_D_11 0x0e0 0x38c 0x818 0x7 0x1 +-#define MX50_PAD_SD1_CLK__ESDHC1_CLK 0x0e4 0x390 0x000 0x0 0x0 +-#define MX50_PAD_SD1_CLK__GPIO5_0 0x0e4 0x390 0x000 0x1 0x0 +-#define MX50_PAD_SD1_CLK__CCM_CLKO 0x0e4 0x390 0x000 0x7 0x0 +-#define MX50_PAD_SD1_CMD__ESDHC1_CMD 0x0e8 0x394 0x000 0x0 0x0 +-#define MX50_PAD_SD1_CMD__GPIO5_1 0x0e8 0x394 0x000 0x1 0x0 +-#define MX50_PAD_SD1_CMD__CCM_CLKO2 0x0e8 0x394 0x000 0x7 0x0 +-#define MX50_PAD_SD1_D0__ESDHC1_DAT0 0x0ec 0x398 0x000 0x0 0x0 +-#define MX50_PAD_SD1_D0__GPIO5_2 0x0ec 0x398 0x000 0x1 0x0 +-#define MX50_PAD_SD1_D0__CCM_PLL1_BYP 0x0ec 0x398 0x6dc 0x7 0x0 +-#define MX50_PAD_SD1_D1__ESDHC1_DAT1 0x0f0 0x39c 0x000 0x0 0x0 +-#define MX50_PAD_SD1_D1__GPIO5_3 0x0f0 0x39c 0x000 0x1 0x0 +-#define MX50_PAD_SD1_D1__CCM_PLL2_BYP 0x0f0 0x39c 0x000 0x7 0x0 +-#define MX50_PAD_SD1_D2__ESDHC1_DAT2 0x0f4 0x3a0 0x000 0x0 0x0 +-#define MX50_PAD_SD1_D2__GPIO5_4 0x0f4 0x3a0 0x000 0x1 0x0 +-#define MX50_PAD_SD1_D2__CCM_PLL3_BYP 0x0f4 0x3a0 0x6e4 0x7 0x0 +-#define MX50_PAD_SD1_D3__ESDHC1_DAT3 0x0f8 0x3a4 0x000 0x0 0x0 +-#define MX50_PAD_SD1_D3__GPIO5_5 0x0f8 0x3a4 0x000 0x1 0x0 +-#define MX50_PAD_SD2_CLK__ESDHC2_CLK 0x0fc 0x3a8 0x000 0x0 0x0 +-#define MX50_PAD_SD2_CLK__GPIO5_6 0x0fc 0x3a8 0x000 0x1 0x0 +-#define MX50_PAD_SD2_CLK__MSHC_SCLK 0x0fc 0x3a8 0x000 0x2 0x0 +-#define MX50_PAD_SD2_CMD__ESDHC2_CMD 0x100 0x3ac 0x000 0x0 0x0 +-#define MX50_PAD_SD2_CMD__GPIO5_7 0x100 0x3ac 0x000 0x1 0x0 +-#define MX50_PAD_SD2_CMD__MSHC_BS 0x100 0x3ac 0x000 0x2 0x0 +-#define MX50_PAD_SD2_D0__ESDHC2_DAT0 0x104 0x3b0 0x000 0x0 0x0 +-#define MX50_PAD_SD2_D0__GPIO5_8 0x104 0x3b0 0x000 0x1 0x0 +-#define MX50_PAD_SD2_D0__MSHC_DATA_0 0x104 0x3b0 0x000 0x2 0x0 +-#define MX50_PAD_SD2_D0__KPP_COL_4 0x104 0x3b0 0x790 0x3 0x0 +-#define MX50_PAD_SD2_D1__ESDHC2_DAT1 0x108 0x3b4 0x000 0x0 0x0 +-#define MX50_PAD_SD2_D1__GPIO5_9 0x108 0x3b4 0x000 0x1 0x0 +-#define MX50_PAD_SD2_D1__MSHC_DATA_1 0x108 0x3b4 0x000 0x2 0x0 +-#define MX50_PAD_SD2_D1__KPP_ROW_4 0x108 0x3b4 0x7a0 0x3 0x0 +-#define MX50_PAD_SD2_D2__ESDHC2_DAT2 0x10c 0x3b8 0x000 0x0 0x0 +-#define MX50_PAD_SD2_D2__GPIO5_10 0x10c 0x3b8 0x000 0x1 0x0 +-#define MX50_PAD_SD2_D2__MSHC_DATA_2 0x10c 0x3b8 0x000 0x2 0x0 +-#define MX50_PAD_SD2_D2__KPP_COL_5 0x10c 0x3b8 0x794 0x3 0x0 +-#define MX50_PAD_SD2_D3__ESDHC2_DAT3 0x110 0x3bc 0x000 0x0 0x0 +-#define MX50_PAD_SD2_D3__GPIO5_11 0x110 0x3bc 0x000 0x1 0x0 +-#define MX50_PAD_SD2_D3__MSHC_DATA_3 0x110 0x3bc 0x000 0x2 0x0 +-#define MX50_PAD_SD2_D3__KPP_ROW_5 0x110 0x3bc 0x7a4 0x3 0x0 +-#define MX50_PAD_SD2_D4__ESDHC2_DAT4 0x114 0x3c0 0x000 0x0 0x0 +-#define MX50_PAD_SD2_D4__GPIO5_12 0x114 0x3c0 0x000 0x1 0x0 +-#define MX50_PAD_SD2_D4__AUDMUX_AUD4_RXFS 0x114 0x3c0 0x6d0 0x2 0x0 +-#define MX50_PAD_SD2_D4__KPP_COL_6 0x114 0x3c0 0x798 0x3 0x0 +-#define MX50_PAD_SD2_D4__EIM_WEIM_D_0 0x114 0x3c0 0x7ec 0x4 0x0 +-#define MX50_PAD_SD2_D4__CCM_CCM_OUT_0 0x114 0x3c0 0x000 0x7 0x0 +-#define MX50_PAD_SD2_D5__ESDHC2_DAT5 0x118 0x3c4 0x000 0x0 0x0 +-#define MX50_PAD_SD2_D5__GPIO5_13 0x118 0x3c4 0x000 0x1 0x0 +-#define MX50_PAD_SD2_D5__AUDMUX_AUD4_RXC 0x118 0x3c4 0x6cc 0x2 0x0 +-#define MX50_PAD_SD2_D5__KPP_ROW_6 0x118 0x3c4 0x7a8 0x3 0x0 +-#define MX50_PAD_SD2_D5__EIM_WEIM_D_1 0x118 0x3c4 0x7f0 0x4 0x0 +-#define MX50_PAD_SD2_D5__CCM_CCM_OUT_1 0x118 0x3c4 0x000 0x7 0x0 +-#define MX50_PAD_SD2_D6__ESDHC2_DAT6 0x11c 0x3c8 0x000 0x0 0x0 +-#define MX50_PAD_SD2_D6__GPIO5_14 0x11c 0x3c8 0x000 0x1 0x0 +-#define MX50_PAD_SD2_D6__AUDMUX_AUD4_RXD 0x11c 0x3c8 0x6c4 0x2 0x0 +-#define MX50_PAD_SD2_D6__KPP_COL_7 0x11c 0x3c8 0x79c 0x3 0x0 +-#define MX50_PAD_SD2_D6__EIM_WEIM_D_2 0x11c 0x3c8 0x7f4 0x4 0x0 +-#define MX50_PAD_SD2_D6__CCM_CCM_OUT_2 0x11c 0x3c8 0x000 0x7 0x0 +-#define MX50_PAD_SD2_D7__ESDHC2_DAT7 0x120 0x3cc 0x000 0x0 0x0 +-#define MX50_PAD_SD2_D7__GPIO5_15 0x120 0x3cc 0x000 0x1 0x0 +-#define MX50_PAD_SD2_D7__AUDMUX_AUD4_TXFS 0x120 0x3cc 0x6d8 0x2 0x0 +-#define MX50_PAD_SD2_D7__KPP_ROW_7 0x120 0x3cc 0x7ac 0x3 0x0 +-#define MX50_PAD_SD2_D7__EIM_WEIM_D_3 0x120 0x3cc 0x7f8 0x4 0x0 +-#define MX50_PAD_SD2_D7__CCM_STOP 0x120 0x3cc 0x000 0x7 0x0 +-#define MX50_PAD_SD2_WP__ESDHC2_WP 0x124 0x3d0 0x744 0x0 0x1 +-#define MX50_PAD_SD2_WP__GPIO5_16 0x124 0x3d0 0x000 0x1 0x0 +-#define MX50_PAD_SD2_WP__AUDMUX_AUD4_TXD 0x124 0x3d0 0x6c8 0x2 0x0 +-#define MX50_PAD_SD2_WP__EIM_WEIM_D_4 0x124 0x3d0 0x7fc 0x4 0x0 +-#define MX50_PAD_SD2_WP__CCM_WAIT 0x124 0x3d0 0x000 0x7 0x0 +-#define MX50_PAD_SD2_CD__ESDHC2_CD 0x128 0x3d4 0x740 0x0 0x1 +-#define MX50_PAD_SD2_CD__GPIO5_17 0x128 0x3d4 0x000 0x1 0x0 +-#define MX50_PAD_SD2_CD__AUDMUX_AUD4_TXC 0x128 0x3d4 0x6d4 0x2 0x0 +-#define MX50_PAD_SD2_CD__EIM_WEIM_D_5 0x128 0x3d4 0x800 0x4 0x0 +-#define MX50_PAD_SD2_CD__CCM_REF_EN_B 0x128 0x3d4 0x000 0x7 0x0 +-#define MX50_PAD_DISP_D0__ELCDIF_DAT_0 0x12c 0x40c 0x6fc 0x0 0x0 +-#define MX50_PAD_DISP_D0__GPIO2_0 0x12c 0x40c 0x000 0x1 0x0 +-#define MX50_PAD_DISP_D0__FEC_TX_CLK 0x12c 0x40c 0x78c 0x2 0x0 +-#define MX50_PAD_DISP_D0__EIM_WEIM_A_16 0x12c 0x40c 0x000 0x3 0x0 +-#define MX50_PAD_DISP_D0__SDMA_DEBUG_PC_0 0x12c 0x40c 0x000 0x6 0x0 +-#define MX50_PAD_DISP_D0__USBPHY1_VSTATUS_0 0x12c 0x40c 0x000 0x7 0x0 +-#define MX50_PAD_DISP_D1__ELCDIF_DAT_1 0x130 0x410 0x700 0x0 0x0 +-#define MX50_PAD_DISP_D1__GPIO2_1 0x130 0x410 0x000 0x1 0x0 +-#define MX50_PAD_DISP_D1__FEC_RX_ERR 0x130 0x410 0x788 0x2 0x0 +-#define MX50_PAD_DISP_D1__EIM_WEIM_A_17 0x130 0x410 0x000 0x3 0x0 +-#define MX50_PAD_DISP_D1__SDMA_DEBUG_PC_1 0x130 0x410 0x000 0x6 0x0 +-#define MX50_PAD_DISP_D1__USBPHY1_VSTATUS_1 0x130 0x410 0x000 0x7 0x0 +-#define MX50_PAD_DISP_D2__ELCDIF_DAT_2 0x134 0x414 0x704 0x0 0x0 +-#define MX50_PAD_DISP_D2__GPIO2_2 0x134 0x414 0x000 0x1 0x0 +-#define MX50_PAD_DISP_D2__FEC_RX_DV 0x134 0x414 0x784 0x2 0x0 +-#define MX50_PAD_DISP_D2__EIM_WEIM_A_18 0x134 0x414 0x000 0x3 0x0 +-#define MX50_PAD_DISP_D2__SDMA_DEBUG_PC_2 0x134 0x414 0x000 0x6 0x0 +-#define MX50_PAD_DISP_D2__USBPHY1_VSTATUS_2 0x134 0x414 0x000 0x7 0x0 +-#define MX50_PAD_DISP_D3__ELCDIF_DAT_3 0x138 0x418 0x708 0x0 0x0 +-#define MX50_PAD_DISP_D3__GPIO2_3 0x138 0x418 0x000 0x1 0x0 +-#define MX50_PAD_DISP_D3__FEC_RDATA_1 0x138 0x418 0x77c 0x2 0x0 +-#define MX50_PAD_DISP_D3__EIM_WEIM_A_19 0x138 0x418 0x000 0x3 0x0 +-#define MX50_PAD_DISP_D3__FEC_COL 0x138 0x418 0x770 0x4 0x1 +-#define MX50_PAD_DISP_D3__SDMA_DEBUG_PC_3 0x138 0x418 0x000 0x6 0x0 +-#define MX50_PAD_DISP_D3__USBPHY1_VSTATUS_3 0x138 0x418 0x000 0x7 0x0 +-#define MX50_PAD_DISP_D4__ELCDIF_DAT_4 0x13c 0x41c 0x70c 0x0 0x0 +-#define MX50_PAD_DISP_D4__GPIO2_4 0x13c 0x41c 0x000 0x1 0x0 +-#define MX50_PAD_DISP_D4__FEC_RDATA_0 0x13c 0x41c 0x778 0x2 0x0 +-#define MX50_PAD_DISP_D4__EIM_WEIM_A_20 0x13c 0x41c 0x000 0x3 0x0 +-#define MX50_PAD_DISP_D4__SDMA_DEBUG_PC_4 0x13c 0x41c 0x000 0x6 0x0 +-#define MX50_PAD_DISP_D4__USBPHY1_VSTATUS_4 0x13c 0x41c 0x000 0x7 0x0 +-#define MX50_PAD_DISP_D5__ELCDIF_DAT_5 0x140 0x420 0x710 0x0 0x0 +-#define MX50_PAD_DISP_D5__GPIO2_5 0x140 0x420 0x000 0x1 0x0 +-#define MX50_PAD_DISP_D5__FEC_TX_EN 0x140 0x420 0x000 0x2 0x0 +-#define MX50_PAD_DISP_D5__EIM_WEIM_A_21 0x140 0x420 0x000 0x3 0x0 +-#define MX50_PAD_DISP_D5__SDMA_DEBUG_PC_5 0x140 0x420 0x000 0x6 0x0 +-#define MX50_PAD_DISP_D5__USBPHY1_VSTATUS_5 0x140 0x420 0x000 0x7 0x0 +-#define MX50_PAD_DISP_D6__ELCDIF_DAT_6 0x144 0x424 0x714 0x0 0x0 +-#define MX50_PAD_DISP_D6__GPIO2_6 0x144 0x424 0x000 0x1 0x0 +-#define MX50_PAD_DISP_D6__FEC_TDATA_1 0x144 0x424 0x000 0x2 0x0 +-#define MX50_PAD_DISP_D6__EIM_WEIM_A_22 0x144 0x424 0x000 0x3 0x0 +-#define MX50_PAD_DISP_D6__FEC_RX_CLK 0x144 0x424 0x780 0x4 0x1 +-#define MX50_PAD_DISP_D6__SDMA_DEBUG_PC_6 0x144 0x424 0x000 0x6 0x0 +-#define MX50_PAD_DISP_D6__USBPHY1_VSTATUS_6 0x144 0x424 0x000 0x7 0x0 +-#define MX50_PAD_DISP_D7__ELCDIF_DAT_7 0x148 0x428 0x718 0x0 0x0 +-#define MX50_PAD_DISP_D7__GPIO2_7 0x148 0x428 0x000 0x1 0x0 +-#define MX50_PAD_DISP_D7__FEC_TDATA_0 0x148 0x428 0x000 0x2 0x0 +-#define MX50_PAD_DISP_D7__EIM_WEIM_A_23 0x148 0x428 0x000 0x3 0x0 +-#define MX50_PAD_DISP_D7__SDMA_DEBUG_PC_7 0x148 0x428 0x000 0x6 0x0 +-#define MX50_PAD_DISP_D7__USBPHY1_VSTATUS_7 0x148 0x428 0x000 0x7 0x0 +-#define MX50_PAD_DISP_WR__ELCDIF_WR_RWN 0x14c 0x42c 0x000 0x0 0x0 +-#define MX50_PAD_DISP_WR__GPIO2_16 0x14c 0x42c 0x000 0x1 0x0 +-#define MX50_PAD_DISP_WR__ELCDIF_DOTCLK 0x14c 0x42c 0x000 0x2 0x0 +-#define MX50_PAD_DISP_WR__EIM_WEIM_A_24 0x14c 0x42c 0x000 0x3 0x0 +-#define MX50_PAD_DISP_WR__SDMA_DEBUG_PC_8 0x14c 0x42c 0x000 0x6 0x0 +-#define MX50_PAD_DISP_WR__USBPHY1_AVALID 0x14c 0x42c 0x000 0x7 0x0 +-#define MX50_PAD_DISP_RD__ELCDIF_RD_E 0x150 0x430 0x000 0x0 0x0 +-#define MX50_PAD_DISP_RD__GPIO2_19 0x150 0x430 0x000 0x1 0x0 +-#define MX50_PAD_DISP_RD__ELCDIF_ENABLE 0x150 0x430 0x000 0x2 0x0 +-#define MX50_PAD_DISP_RD__EIM_WEIM_A_25 0x150 0x430 0x000 0x3 0x0 +-#define MX50_PAD_DISP_RD__SDMA_DEBUG_PC_9 0x150 0x430 0x000 0x6 0x0 +-#define MX50_PAD_DISP_RD__USBPHY1_BVALID 0x150 0x430 0x000 0x7 0x0 +-#define MX50_PAD_DISP_RS__ELCDIF_RS 0x154 0x434 0x000 0x0 0x0 +-#define MX50_PAD_DISP_RS__GPIO2_17 0x154 0x434 0x000 0x1 0x0 +-#define MX50_PAD_DISP_RS__ELCDIF_VSYNC 0x154 0x434 0x73c 0x2 0x1 +-#define MX50_PAD_DISP_RS__EIM_WEIM_A_26 0x154 0x434 0x000 0x3 0x0 +-#define MX50_PAD_DISP_RS__SDMA_DEBUG_PC_10 0x154 0x434 0x000 0x6 0x0 +-#define MX50_PAD_DISP_RS__USBPHY1_ENDSESSION 0x154 0x434 0x000 0x7 0x0 +-#define MX50_PAD_DISP_CS__ELCDIF_CS 0x158 0x438 0x000 0x0 0x0 +-#define MX50_PAD_DISP_CS__GPIO2_21 0x158 0x438 0x000 0x1 0x0 +-#define MX50_PAD_DISP_CS__ELCDIF_HSYNC 0x158 0x438 0x6f8 0x2 0x1 +-#define MX50_PAD_DISP_CS__EIM_WEIM_A_27 0x158 0x438 0x000 0x3 0x0 +-#define MX50_PAD_DISP_CS__EIM_WEIM_CS_3 0x158 0x438 0x000 0x4 0x0 +-#define MX50_PAD_DISP_CS__SDMA_DEBUG_PC_11 0x158 0x438 0x000 0x6 0x0 +-#define MX50_PAD_DISP_CS__USBPHY1_IDDIG 0x158 0x438 0x000 0x7 0x0 +-#define MX50_PAD_DISP_BUSY__ELCDIF_BUSY 0x15c 0x43c 0x6f8 0x0 0x2 +-#define MX50_PAD_DISP_BUSY__GPIO2_18 0x15c 0x43c 0x000 0x1 0x0 +-#define MX50_PAD_DISP_BUSY__EIM_WEIM_CS_3 0x15c 0x43c 0x000 0x4 0x0 +-#define MX50_PAD_DISP_BUSY__SDMA_DEBUG_PC_12 0x15c 0x43c 0x000 0x6 0x0 +-#define MX50_PAD_DISP_BUSY__USBPHY2_HOSTDISCONNECT 0x15c 0x43c 0x000 0x7 0x0 +-#define MX50_PAD_DISP_RESET__ELCDIF_RESET 0x160 0x440 0x000 0x0 0x0 +-#define MX50_PAD_DISP_RESET__GPIO2_20 0x160 0x440 0x000 0x1 0x0 +-#define MX50_PAD_DISP_RESET__EIM_WEIM_CS_3 0x160 0x440 0x000 0x4 0x0 +-#define MX50_PAD_DISP_RESET__SDMA_DEBUG_PC_13 0x160 0x440 0x000 0x6 0x0 +-#define MX50_PAD_DISP_RESET__USBPHY2_BISTOK 0x160 0x440 0x000 0x7 0x0 +-#define MX50_PAD_SD3_CMD__ESDHC3_CMD 0x164 0x444 0x000 0x0 0x0 +-#define MX50_PAD_SD3_CMD__GPIO5_18 0x164 0x444 0x000 0x1 0x0 +-#define MX50_PAD_SD3_CMD__EIM_NANDF_WRN 0x164 0x444 0x000 0x2 0x0 +-#define MX50_PAD_SD3_CMD__SSP_CMD 0x164 0x444 0x000 0x3 0x0 +-#define MX50_PAD_SD3_CLK__ESDHC3_CLK 0x168 0x448 0x000 0x0 0x0 +-#define MX50_PAD_SD3_CLK__GPIO5_19 0x168 0x448 0x000 0x1 0x0 +-#define MX50_PAD_SD3_CLK__EIM_NANDF_RDN 0x168 0x448 0x000 0x2 0x0 +-#define MX50_PAD_SD3_CLK__SSP_CLK 0x168 0x448 0x000 0x3 0x0 +-#define MX50_PAD_SD3_D0__ESDHC3_DAT0 0x16c 0x44c 0x000 0x0 0x0 +-#define MX50_PAD_SD3_D0__GPIO5_20 0x16c 0x44c 0x000 0x1 0x0 +-#define MX50_PAD_SD3_D0__EIM_NANDF_D_4 0x16c 0x44c 0x000 0x2 0x0 +-#define MX50_PAD_SD3_D0__SSP_D0 0x16c 0x44c 0x000 0x3 0x0 +-#define MX50_PAD_SD3_D0__CCM_PLL1_BYP 0x16c 0x44c 0x6dc 0x7 0x1 +-#define MX50_PAD_SD3_D1__ESDHC3_DAT1 0x170 0x450 0x000 0x0 0x0 +-#define MX50_PAD_SD3_D1__GPIO5_21 0x170 0x450 0x000 0x1 0x0 +-#define MX50_PAD_SD3_D1__EIM_NANDF_D_5 0x170 0x450 0x000 0x2 0x0 +-#define MX50_PAD_SD3_D1__SSP_D1 0x170 0x450 0x000 0x3 0x0 +-#define MX50_PAD_SD3_D1__CCM_PLL2_BYP 0x170 0x450 0x000 0x7 0x0 +-#define MX50_PAD_SD3_D2__ESDHC3_DAT2 0x174 0x454 0x000 0x0 0x0 +-#define MX50_PAD_SD3_D2__GPIO5_22 0x174 0x454 0x000 0x1 0x0 +-#define MX50_PAD_SD3_D2__EIM_NANDF_D_6 0x174 0x454 0x000 0x2 0x0 +-#define MX50_PAD_SD3_D2__SSP_D2 0x174 0x454 0x000 0x3 0x0 +-#define MX50_PAD_SD3_D2__CCM_PLL3_BYP 0x174 0x454 0x6e4 0x7 0x1 +-#define MX50_PAD_SD3_D3__ESDHC3_DAT3 0x178 0x458 0x000 0x0 0x0 +-#define MX50_PAD_SD3_D3__GPIO5_23 0x178 0x458 0x000 0x1 0x0 +-#define MX50_PAD_SD3_D3__EIM_NANDF_D_7 0x178 0x458 0x000 0x2 0x0 +-#define MX50_PAD_SD3_D3__SSP_D3 0x178 0x458 0x000 0x3 0x0 +-#define MX50_PAD_SD3_D4__ESDHC3_DAT4 0x17c 0x45c 0x000 0x0 0x0 +-#define MX50_PAD_SD3_D4__GPIO5_24 0x17c 0x45c 0x000 0x1 0x0 +-#define MX50_PAD_SD3_D4__EIM_NANDF_D_0 0x17c 0x45c 0x000 0x2 0x0 +-#define MX50_PAD_SD3_D4__SSP_D4 0x17c 0x45c 0x000 0x3 0x0 +-#define MX50_PAD_SD3_D5__ESDHC3_DAT5 0x180 0x460 0x000 0x0 0x0 +-#define MX50_PAD_SD3_D5__GPIO5_25 0x180 0x460 0x000 0x1 0x0 +-#define MX50_PAD_SD3_D5__EIM_NANDF_D_1 0x180 0x460 0x000 0x2 0x0 +-#define MX50_PAD_SD3_D5__SSP_D5 0x180 0x460 0x000 0x3 0x0 +-#define MX50_PAD_SD3_D6__ESDHC3_DAT6 0x184 0x464 0x000 0x0 0x0 +-#define MX50_PAD_SD3_D6__GPIO5_26 0x184 0x464 0x000 0x1 0x0 +-#define MX50_PAD_SD3_D6__EIM_NANDF_D_2 0x184 0x464 0x000 0x2 0x0 +-#define MX50_PAD_SD3_D6__SSP_D6 0x184 0x464 0x000 0x3 0x0 +-#define MX50_PAD_SD3_D7__ESDHC3_DAT7 0x188 0x468 0x000 0x0 0x0 +-#define MX50_PAD_SD3_D7__GPIO5_27 0x188 0x468 0x000 0x1 0x0 +-#define MX50_PAD_SD3_D7__EIM_NANDF_D_3 0x188 0x468 0x000 0x2 0x0 +-#define MX50_PAD_SD3_D7__SSP_D7 0x188 0x468 0x000 0x3 0x0 +-#define MX50_PAD_SD3_WP__ESDHC3_WP 0x18c 0x46C 0x000 0x0 0x0 +-#define MX50_PAD_SD3_WP__GPIO5_28 0x18c 0x46C 0x000 0x1 0x0 +-#define MX50_PAD_SD3_WP__EIM_NANDF_RESETN 0x18c 0x46C 0x000 0x2 0x0 +-#define MX50_PAD_SD3_WP__SSP_CD 0x18c 0x46C 0x000 0x3 0x0 +-#define MX50_PAD_SD3_WP__ESDHC4_LCTL 0x18c 0x46C 0x000 0x4 0x0 +-#define MX50_PAD_SD3_WP__EIM_WEIM_CS_3 0x18c 0x46C 0x000 0x5 0x0 +-#define MX50_PAD_DISP_D8__ELCDIF_DAT_8 0x190 0x470 0x71c 0x0 0x0 +-#define MX50_PAD_DISP_D8__GPIO2_8 0x190 0x470 0x000 0x1 0x0 +-#define MX50_PAD_DISP_D8__EIM_NANDF_CLE 0x190 0x470 0x000 0x2 0x0 +-#define MX50_PAD_DISP_D8__ESDHC1_LCTL 0x190 0x470 0x000 0x3 0x0 +-#define MX50_PAD_DISP_D8__ESDHC4_CMD 0x190 0x470 0x74c 0x4 0x2 +-#define MX50_PAD_DISP_D8__KPP_COL_4 0x190 0x470 0x790 0x5 0x1 +-#define MX50_PAD_DISP_D8__FEC_TX_CLK 0x190 0x470 0x78c 0x6 0x1 +-#define MX50_PAD_DISP_D8__USBPHY1_DATAOUT_0 0x190 0x470 0x000 0x7 0x0 +-#define MX50_PAD_DISP_D9__ELCDIF_DAT_9 0x194 0x474 0x720 0x0 0x0 +-#define MX50_PAD_DISP_D9__GPIO2_9 0x194 0x474 0x000 0x1 0x0 +-#define MX50_PAD_DISP_D9__EIM_NANDF_ALE 0x194 0x474 0x000 0x2 0x0 +-#define MX50_PAD_DISP_D9__ESDHC2_LCTL 0x194 0x474 0x000 0x3 0x0 +-#define MX50_PAD_DISP_D9__ESDHC4_CLK 0x194 0x474 0x748 0x4 0x2 +-#define MX50_PAD_DISP_D9__KPP_ROW_4 0x194 0x474 0x7a0 0x5 0x1 +-#define MX50_PAD_DISP_D9__FEC_RX_ER 0x194 0x474 0x788 0x6 0x1 +-#define MX50_PAD_DISP_D9__USBPHY1_DATAOUT_1 0x194 0x474 0x000 0x7 0x0 +-#define MX50_PAD_DISP_D10__ELCDIF_DAT_10 0x198 0x478 0x724 0x0 0x0 +-#define MX50_PAD_DISP_D10__GPIO2_10 0x198 0x478 0x000 0x1 0x0 +-#define MX50_PAD_DISP_D10__EIM_NANDF_CEN_0 0x198 0x478 0x000 0x2 0x0 +-#define MX50_PAD_DISP_D10__ESDHC3_LCTL 0x198 0x478 0x000 0x3 0x0 +-#define MX50_PAD_DISP_D10__ESDHC4_DAT0 0x198 0x478 0x000 0x4 0x0 +-#define MX50_PAD_DISP_D10__KPP_COL_5 0x198 0x478 0x794 0x5 0x1 +-#define MX50_PAD_DISP_D10__FEC_RX_DV 0x198 0x478 0x784 0x6 0x1 +-#define MX50_PAD_DISP_D10__USBPHY1_DATAOUT_2 0x198 0x478 0x000 0x7 0x0 +-#define MX50_PAD_DISP_D11__ELCDIF_DAT_11 0x19c 0x47c 0x728 0x0 0x0 +-#define MX50_PAD_DISP_D11__GPIO2_11 0x19c 0x47c 0x000 0x1 0x0 +-#define MX50_PAD_DISP_D11__EIM_NANDF_CEN_1 0x19c 0x47c 0x000 0x2 0x0 +-#define MX50_PAD_DISP_D11__ESDHC4_DAT1 0x19c 0x47c 0x754 0x4 0x1 +-#define MX50_PAD_DISP_D11__KPP_ROW_5 0x19c 0x47c 0x7a4 0x5 0x1 +-#define MX50_PAD_DISP_D11__FEC_RDATA_1 0x19c 0x47c 0x77c 0x6 0x1 +-#define MX50_PAD_DISP_D11__USBPHY1_DATAOUT_3 0x19c 0x47c 0x000 0x7 0x0 +-#define MX50_PAD_DISP_D12__ELCDIF_DAT_12 0x1a0 0x480 0x72c 0x0 0x0 +-#define MX50_PAD_DISP_D12__GPIO2_12 0x1a0 0x480 0x000 0x1 0x0 +-#define MX50_PAD_DISP_D12__EIM_NANDF_CEN_2 0x1a0 0x480 0x000 0x2 0x0 +-#define MX50_PAD_DISP_D12__ESDHC1_CD 0x1a0 0x480 0x000 0x3 0x0 +-#define MX50_PAD_DISP_D12__ESDHC4_DAT2 0x1a0 0x480 0x758 0x4 0x1 +-#define MX50_PAD_DISP_D12__KPP_COL_6 0x1a0 0x480 0x798 0x5 0x1 +-#define MX50_PAD_DISP_D12__FEC_RDATA_0 0x1a0 0x480 0x778 0x6 0x1 +-#define MX50_PAD_DISP_D12__USBPHY1_DATAOUT_4 0x1a0 0x480 0x000 0x7 0x0 +-#define MX50_PAD_DISP_D13__ELCDIF_DAT_13 0x1a4 0x484 0x730 0x0 0x0 +-#define MX50_PAD_DISP_D13__GPIO2_13 0x1a4 0x484 0x000 0x1 0x0 +-#define MX50_PAD_DISP_D13__EIM_NANDF_CEN_3 0x1a4 0x484 0x000 0x2 0x0 +-#define MX50_PAD_DISP_D13__ESDHC3_CD 0x1a4 0x484 0x000 0x3 0x0 +-#define MX50_PAD_DISP_D13__ESDHC4_DAT3 0x1a4 0x484 0x75c 0x4 0x1 +-#define MX50_PAD_DISP_D13__KPP_ROW_6 0x1a4 0x484 0x7a8 0x5 0x1 +-#define MX50_PAD_DISP_D13__FEC_TX_EN 0x1a4 0x484 0x000 0x6 0x0 +-#define MX50_PAD_DISP_D13__USBPHY1_DATAOUT_5 0x1a4 0x484 0x000 0x7 0x0 +-#define MX50_PAD_DISP_D14__ELCDIF_DAT_14 0x1a8 0x488 0x734 0x0 0x0 +-#define MX50_PAD_DISP_D14__GPIO2_14 0x1a8 0x488 0x000 0x1 0x0 +-#define MX50_PAD_DISP_D14__EIM_NANDF_READY0 0x1a8 0x488 0x7b4 0x2 0x1 +-#define MX50_PAD_DISP_D14__ESDHC1_WP 0x1a8 0x488 0x000 0x3 0x0 +-#define MX50_PAD_DISP_D14__ESDHC4_WP 0x1a8 0x488 0x000 0x4 0x0 +-#define MX50_PAD_DISP_D14__KPP_COL_7 0x1a8 0x488 0x79c 0x5 0x1 +-#define MX50_PAD_DISP_D14__FEC_TDATA_1 0x1a8 0x488 0x000 0x6 0x0 +-#define MX50_PAD_DISP_D14__USBPHY1_DATAOUT_6 0x1a8 0x488 0x000 0x7 0x0 +-#define MX50_PAD_DISP_D15__ELCDIF_DAT_15 0x1ac 0x48c 0x738 0x0 0x0 +-#define MX50_PAD_DISP_D15__GPIO2_15 0x1ac 0x48c 0x000 0x1 0x0 +-#define MX50_PAD_DISP_D15__EIM_NANDF_DQS 0x1ac 0x48c 0x7b0 0x2 0x1 +-#define MX50_PAD_DISP_D15__ESDHC3_RST 0x1ac 0x48c 0x000 0x3 0x0 +-#define MX50_PAD_DISP_D15__ESDHC4_CD 0x1ac 0x48c 0x000 0x4 0x0 +-#define MX50_PAD_DISP_D15__KPP_ROW_7 0x1ac 0x48c 0x7ac 0x5 0x1 +-#define MX50_PAD_DISP_D15__FEC_TDATA_0 0x1ac 0x48c 0x000 0x6 0x0 +-#define MX50_PAD_DISP_D15__USBPHY1_DATAOUT_7 0x1ac 0x48c 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_D0__EPDC_SDDO_0 0x1b0 0x54c 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_D0__GPIO3_0 0x1b0 0x54c 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_D0__EIM_WEIM_D_0 0x1b0 0x54c 0x7ec 0x2 0x1 +-#define MX50_PAD_EPDC_D0__ELCDIF_RS 0x1b0 0x54c 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_D0__ELCDIF_DOTCLK 0x1b0 0x54c 0x000 0x4 0x0 +-#define MX50_PAD_EPDC_D0__SDMA_DEBUG_EVT_CHN_LINES_0 0x1b0 0x54c 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_D0__USBPHY2_DATAOUT_0 0x1b0 0x54c 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_D1__EPDC_SDDO_1 0x1b4 0x550 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_D1__GPIO3_1 0x1b4 0x550 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_D1__EIM_WEIM_D_1 0x1b4 0x550 0x7f0 0x2 0x1 +-#define MX50_PAD_EPDC_D1__ELCDIF_CS 0x1b4 0x550 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_D1__ELCDIF_ENABLE 0x1b4 0x550 0x000 0x4 0x0 +-#define MX50_PAD_EPDC_D1__SDMA_DEBUG_EVT_CHN_LINES_1 0x1b4 0x550 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_D1__USBPHY2_DATAOUT_1 0x1b4 0x550 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_D2__EPDC_SDDO_2 0x1b8 0x554 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_D2__GPIO3_2 0x1b8 0x554 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_D2__EIM_WEIM_D_2 0x1b8 0x554 0x7f4 0x2 0x1 +-#define MX50_PAD_EPDC_D2__ELCDIF_WR_RWN 0x1b8 0x554 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC 0x1b8 0x554 0x73c 0x4 0x2 +-#define MX50_PAD_EPDC_D2__SDMA_DEBUG_EVT_CHN_LINES_2 0x1b8 0x554 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_D2__USBPHY2_DATAOUT_2 0x1b8 0x554 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_D3__EPDC_SDDO_3 0x1bc 0x558 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_D3__GPIO3_3 0x1bc 0x558 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_D3__EIM_WEIM_D_3 0x1bc 0x558 0x7f8 0x2 0x1 +-#define MX50_PAD_EPDC_D3__ELCDIF_RD_E 0x1bc 0x558 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC 0x1bc 0x558 0x6f8 0x4 0x3 +-#define MX50_PAD_EPDC_D3__SDMA_DEBUG_EVT_CHN_LINES_3 0x1bc 0x558 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_D3__USBPHY2_DATAOUT_3 0x1bc 0x558 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_D4__EPDC_SDDO_4 0x1c0 0x55c 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_D4__GPIO3_4 0x1c0 0x55c 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_D4__EIM_WEIM_D_4 0x1c0 0x55c 0x7fc 0x2 0x1 +-#define MX50_PAD_EPDC_D4__SDMA_DEBUG_EVT_CHN_LINES_4 0x1c0 0x55c 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_D4__USBPHY2_DATAOUT_4 0x1c0 0x55c 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_D5__EPDC_SDDO_5 0x1c4 0x560 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_D5__GPIO3_5 0x1c4 0x560 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_D5__EIM_WEIM_D_5 0x1c4 0x560 0x800 0x2 0x1 +-#define MX50_PAD_EPDC_D5__SDMA_DEBUG_EVT_CHN_LINES_5 0x1c4 0x560 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_D5__USBPHY2_DATAOUT_5 0x1c4 0x560 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_D6__EPDC_SDDO_6 0x1c8 0x564 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_D6__GPIO3_6 0x1c8 0x564 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_D6__EIM_WEIM_D_6 0x1c8 0x564 0x804 0x2 0x1 +-#define MX50_PAD_EPDC_D6__SDMA_DEBUG_EVT_CHN_LINES_6 0x1c8 0x564 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_D6__USBPHY2_DATAOUT_6 0x1c8 0x564 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_D7__EPDC_SDDO_7 0x1cc 0x568 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_D7__GPIO3_7 0x1cc 0x568 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_D7__EIM_WEIM_D_7 0x1cc 0x568 0x808 0x2 0x1 +-#define MX50_PAD_EPDC_D7__SDMA_DEBUG_EVT_CHN_LINES_7 0x1cc 0x568 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_D7__USBPHY2_DATAOUT_7 0x1cc 0x568 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_D8__EPDC_SDDO_8 0x1d0 0x56c 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_D8__GPIO3_8 0x1d0 0x56c 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_D8__EIM_WEIM_D_8 0x1d0 0x56c 0x80c 0x2 0x2 +-#define MX50_PAD_EPDC_D8__ELCDIF_DAT_24 0x1d0 0x56c 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_D8__SDMA_DEBUG_MATCHED_DMBUS 0x1d0 0x56c 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_D8__USBPHY2_VSTATUS_0 0x1d0 0x56c 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_D9__EPDC_SDDO_9 0x1d4 0x570 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_D9__GPIO3_9 0x1d4 0x570 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_D9__EIM_WEIM_D_9 0x1d4 0x570 0x810 0x2 0x2 +-#define MX50_PAD_EPDC_D9__ELCDIF_DAT_25 0x1d4 0x570 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_D9__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x1d4 0x570 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_D9__USBPHY2_VSTATUS_1 0x1d4 0x570 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_D10__EPDC_SDDO_10 0x1d8 0x574 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_D10__GPIO3_10 0x1d8 0x574 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_D10__EIM_WEIM_D_10 0x1d8 0x574 0x814 0x2 0x2 +-#define MX50_PAD_EPDC_D10__ELCDIF_DAT_26 0x1d8 0x574 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_D10__SDMA_DEBUG_EVENT_CHANNEL_0 0x1d8 0x574 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_D10__USBPHY2_VSTATUS_2 0x1d8 0x574 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_D11__EPDC_SDDO_11 0x1dc 0x578 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_D11__GPIO3_11 0x1dc 0x578 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_D11__EIM_WEIM_D_11 0x1dc 0x578 0x818 0x2 0x2 +-#define MX50_PAD_EPDC_D11__ELCDIF_DAT_27 0x1dc 0x578 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_D11__SDMA_DEBUG_EVENT_CHANNEL_1 0x1dc 0x578 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_D11__USBPHY2_VSTATUS_3 0x1dc 0x578 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_D12__EPDC_SDDO_12 0x1e0 0x57c 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_D12__GPIO3_12 0x1e0 0x57c 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_D12__EIM_WEIM_D_12 0x1e0 0x57c 0x81c 0x2 0x1 +-#define MX50_PAD_EPDC_D12__ELCDIF_DAT_28 0x1e0 0x57c 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_D12__SDMA_DEBUG_EVENT_CHANNEL_2 0x1e0 0x57c 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_D12__USBPHY2_VSTATUS_4 0x1e0 0x57c 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_D13__EPDC_SDDO_13 0x1e4 0x580 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_D13__GPIO3_13 0x1e4 0x580 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_D13__EIM_WEIM_D_13 0x1e4 0x580 0x820 0x2 0x1 +-#define MX50_PAD_EPDC_D13__ELCDIF_DAT_29 0x1e4 0x580 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_D13__SDMA_DEBUG_EVENT_CHANNEL_3 0x1e4 0x580 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_D13__USBPHY2_VSTATUS_5 0x1e4 0x580 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_D14__EPDC_SDDO_14 0x1e8 0x584 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_D14__GPIO3_14 0x1e8 0x584 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_D14__EIM_WEIM_D_14 0x1e8 0x584 0x824 0x2 0x1 +-#define MX50_PAD_EPDC_D14__ELCDIF_DAT_30 0x1e8 0x584 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_D14__AUDMUX_AUD6_TXD 0x1e8 0x584 0x000 0x4 0x0 +-#define MX50_PAD_EPDC_D14__SDMA_DEBUG_EVENT_CHANNEL_4 0x1e8 0x584 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_D14__USBPHY2_VSTATUS_6 0x1e8 0x584 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_D15__EPDC_SDDO_15 0x1ec 0x588 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_D15__GPIO3_15 0x1ec 0x588 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_D15__EIM_WEIM_D_15 0x1ec 0x588 0x828 0x2 0x1 +-#define MX50_PAD_EPDC_D15__ELCDIF_DAT_31 0x1ec 0x588 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_D15__AUDMUX_AUD6_TXC 0x1ec 0x588 0x000 0x4 0x0 +-#define MX50_PAD_EPDC_D15__SDMA_DEBUG_EVENT_CHANNEL_5 0x1ec 0x588 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_D15__USBPHY2_VSTATUS_7 0x1ec 0x588 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK 0x1f0 0x58c 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_GDCLK__GPIO3_16 0x1f0 0x58c 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_GDCLK__EIM_WEIM_D_16 0x1f0 0x58c 0x000 0x2 0x0 +-#define MX50_PAD_EPDC_GDCLK__ELCDIF_DAT_16 0x1f0 0x58c 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_GDCLK__AUDMUX_AUD6_TXFS 0x1f0 0x58c 0x000 0x4 0x0 +-#define MX50_PAD_EPDC_GDCLK__SDMA_DEBUG_CORE_STATE_0 0x1f0 0x58c 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_GDCLK__USBPHY2_BISTOK 0x1f0 0x58c 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_GDSP__EPCD_GDSP 0x1f4 0x590 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_GDSP__GPIO3_17 0x1f4 0x590 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_GDSP__EIM_WEIM_D_17 0x1f4 0x590 0x000 0x2 0x0 +-#define MX50_PAD_EPDC_GDSP__ELCDIF_DAT_17 0x1f4 0x590 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_GDSP__AUDMUX_AUD6_RXD 0x1f4 0x590 0x000 0x4 0x0 +-#define MX50_PAD_EPDC_GDSP__SDMA_DEBUG_CORE_STATE_1 0x1f4 0x590 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_GDSP__USBPHY2_BVALID 0x1f4 0x590 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_GDOE__EPCD_GDOE 0x1f8 0x594 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_GDOE__GPIO3_18 0x1f8 0x594 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_GDOE__EIM_WEIM_D_18 0x1f8 0x594 0x000 0x2 0x0 +-#define MX50_PAD_EPDC_GDOE__ELCDIF_DAT_18 0x1f8 0x594 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_GDOE__AUDMUX_AUD6_RXC 0x1f8 0x594 0x000 0x4 0x0 +-#define MX50_PAD_EPDC_GDOE__SDMA_DEBUG_CORE_STATE_2 0x1f8 0x594 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_GDOE__USBPHY2_ENDSESSION 0x1f8 0x594 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_GDRL__EPCD_GDRL 0x1fc 0x598 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_GDRL__GPIO3_19 0x1fc 0x598 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_GDRL__EIM_WEIM_D_19 0x1f8 0x598 0x000 0x2 0x0 +-#define MX50_PAD_EPDC_GDRL__ELCDIF_DAT_19 0x1fc 0x598 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_GDRL__AUDMUX_AUD6_RXFS 0x1fc 0x598 0x000 0x4 0x0 +-#define MX50_PAD_EPDC_GDRL__SDMA_DEBUG_CORE_STATE_3 0x1fc 0x598 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_GDRL__USBPHY2_IDDIG 0x1fc 0x598 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_SDCLK__EPCD_SDCLK 0x200 0x59c 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_SDCLK__GPIO3_20 0x200 0x59c 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_SDCLK__EIM_WEIM_D_20 0x200 0x59c 0x000 0x2 0x0 +-#define MX50_PAD_EPDC_SDCLK__ELCDIF_DAT_20 0x200 0x59c 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_SDCLK__AUDMUX_AUD5_TXD 0x200 0x59c 0x000 0x4 0x0 +-#define MX50_PAD_EPDC_SDCLK__SDMA_DEBUG_BUS_DEVICE_0 0x200 0x59c 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_SDCLK__USBPHY2_HOSTDISCONNECT 0x200 0x59c 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_SDOEZ__EPCD_SDOEZ 0x204 0x5a0 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_SDOEZ__GPIO3_21 0x204 0x5a0 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_SDOEZ__EIM_WEIM_D_21 0x204 0x5a0 0x000 0x2 0x0 +-#define MX50_PAD_EPDC_SDOEZ__ELCDIF_DAT_21 0x204 0x5a0 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_SDOEZ__AUDMUX_AUD5_TXC 0x204 0x5a0 0x000 0x4 0x0 +-#define MX50_PAD_EPDC_SDOEZ__SDMA_DEBUG_BUS_DEVICE_1 0x204 0x5a0 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_SDOEZ__USBPHY2_TXREADY 0x204 0x5a0 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_SDOED__EPCD_SDOED 0x208 0x5a4 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_SDOED__GPIO3_22 0x208 0x5a4 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_SDOED__EIM_WEIM_D_22 0x208 0x5a4 0x000 0x2 0x0 +-#define MX50_PAD_EPDC_SDOED__ELCDIF_DAT_22 0x208 0x5a4 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_SDOED__AUDMUX_AUD5_TXFS 0x208 0x5a4 0x000 0x4 0x0 +-#define MX50_PAD_EPDC_SDOED__SDMA_DEBUG_BUS_DEVICE_2 0x208 0x5a4 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_SDOED__USBPHY2_RXVALID 0x208 0x5a4 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_SDOE__EPCD_SDOE 0x20c 0x5a8 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_SDOE__GPIO3_23 0x20c 0x5a8 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_SDOE__EIM_WEIM_D_23 0x20c 0x5a8 0x000 0x2 0x0 +-#define MX50_PAD_EPDC_SDOE__ELCDIF_DAT_23 0x20c 0x5a8 0x000 0x3 0x0 +-#define MX50_PAD_EPDC_SDOE__AUDMUX_AUD5_RXD 0x20c 0x5a8 0x000 0x4 0x0 +-#define MX50_PAD_EPDC_SDOE__SDMA_DEBUG_BUS_DEVICE_3 0x20c 0x5a8 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_SDOE__USBPHY2_RXACTIVE 0x20c 0x5a8 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_SDLE__EPCD_SDLE 0x210 0x5ac 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_SDLE__GPIO3_24 0x210 0x5ac 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_SDLE__EIM_WEIM_D_24 0x210 0x5ac 0x000 0x2 0x0 +-#define MX50_PAD_EPDC_SDLE__ELCDIF_DAT_8 0x210 0x5ac 0x71c 0x3 0x1 +-#define MX50_PAD_EPDC_SDLE__AUDMUX_AUD5_RXC 0x210 0x5ac 0x000 0x4 0x0 +-#define MX50_PAD_EPDC_SDLE__SDMA_DEBUG_BUS_DEVICE_4 0x210 0x5ac 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_SDLE__USBPHY2_RXERROR 0x210 0x5ac 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_SDCLKN__EPCD_SDCLKN 0x214 0x5b0 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_SDCLKN__GPIO3_25 0x214 0x5b0 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_SDCLKN__EIM_WEIM_D_25 0x214 0x5b0 0x000 0x2 0x0 +-#define MX50_PAD_EPDC_SDCLKN__ELCDIF_DAT_9 0x214 0x5b0 0x720 0x3 0x1 +-#define MX50_PAD_EPDC_SDCLKN__AUDMUX_AUD5_RXFS 0x214 0x5b0 0x000 0x4 0x0 +-#define MX50_PAD_EPDC_SDCLKN__SDMA_DEBUG_BUS_ERROR 0x214 0x5b0 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_SDCLKN__USBPHY2_SIECLOCK 0x214 0x5b0 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_SDSHR__EPCD_SDSHR 0x218 0x5b4 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_SDSHR__GPIO3_26 0x218 0x5b4 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_SDSHR__EIM_WEIM_D_26 0x218 0x5b4 0x000 0x2 0x0 +-#define MX50_PAD_EPDC_SDSHR__ELCDIF_DAT_10 0x218 0x5b4 0x724 0x3 0x1 +-#define MX50_PAD_EPDC_SDSHR__AUDMUX_AUD4_TXD 0x218 0x5b4 0x6c8 0x4 0x1 +-#define MX50_PAD_EPDC_SDSHR__SDMA_DEBUG_BUS_RWB 0x218 0x5b4 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_SDSHR__USBPHY2_LINESTATE_0 0x218 0x5b4 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_PWRCOM__EPCD_PWRCOM 0x21c 0x5b8 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_PWRCOM__GPIO3_27 0x21c 0x5b8 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_PWRCOM__EIM_WEIM_D_27 0x21c 0x5b8 0x000 0x2 0x0 +-#define MX50_PAD_EPDC_PWRCOM__ELCDIF_DAT_11 0x21c 0x5b8 0x728 0x3 0x1 +-#define MX50_PAD_EPDC_PWRCOM__AUDMUX_AUD4_TXC 0x21c 0x5b8 0x6d4 0x4 0x1 +-#define MX50_PAD_EPDC_PWRCOM__SDMA_DEBUG_CORE_RUN 0x21c 0x5b8 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_PWRCOM__USBPHY2_LINESTATE_1 0x21c 0x5b8 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_PWRSTAT__EPCD_PWRSTAT 0x220 0x5bc 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_PWRSTAT__GPIO3_28 0x220 0x5bc 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_PWRSTAT__EIM_WEIM_D_28 0x220 0x5bc 0x000 0x2 0x0 +-#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_DAT_12 0x220 0x5bc 0x72c 0x3 0x1 +-#define MX50_PAD_EPDC_PWRSTAT__AUDMUX_AUD4_TXFS 0x220 0x5bc 0x6d8 0x4 0x1 +-#define MX50_PAD_EPDC_PWRSTAT__SDMA_DEBUG_MODE 0x220 0x5bc 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_PWRSTAT__USBPHY2_VBUSVALID 0x220 0x5bc 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_PWRCTRL0__EPCD_PWRCTRL0 0x224 0x5c0 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_PWRCTRL0__GPIO3_29 0x224 0x5c0 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_PWRCTRL0__EIM_WEIM_D_29 0x224 0x5c0 0x000 0x2 0x0 +-#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_DAT_13 0x224 0x5c0 0x730 0x3 0x1 +-#define MX50_PAD_EPDC_PWRCTRL0__AUDMUX_AUD4_RXD 0x224 0x5c0 0x6c4 0x4 0x1 +-#define MX50_PAD_EPDC_PWRCTRL0__SDMA_DEBUG_RTBUFFER_WRITE 0x224 0x5c0 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_PWRCTRL0__USBPHY2_AVALID 0x224 0x5c0 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_PWRCTRL1__EPCD_PWRCTRL1 0x228 0x5c4 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_PWRCTRL1__GPIO3_30 0x228 0x5c4 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_PWRCTRL1__EIM_WEIM_D_30 0x228 0x5c4 0x000 0x2 0x0 +-#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_DAT_14 0x228 0x5c4 0x734 0x3 0x1 +-#define MX50_PAD_EPDC_PWRCTRL1__AUDMUX_AUD4_RXC 0x228 0x5c4 0x6cc 0x4 0x1 +-#define MX50_PAD_EPDC_PWRCTRL1__SDMA_DEBUG_YIELD 0x228 0x5c4 0x000 0x6 0x0 +-#define MX50_PAD_EPDC_PWRCTRL1__USBPHY1_ONBIST 0x228 0x5c4 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_PWRCTRL2__EPCD_PWRCTRL2 0x22c 0x5c8 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_PWRCTRL2__GPIO3_31 0x22c 0x5c8 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_PWRCTRL2__EIM_WEIM_D_31 0x22c 0x5c8 0x000 0x2 0x0 +-#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_DAT_15 0x22c 0x5c8 0x738 0x3 0x1 +-#define MX50_PAD_EPDC_PWRCTRL2__AUDMUX_AUD4_RXFS 0x22c 0x5c8 0x6d0 0x4 0x1 +-#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT_EVENT_0 0x22c 0x5c8 0x7b8 0x6 0x1 +-#define MX50_PAD_EPDC_PWRCTRL2__USBPHY2_ONBIST 0x22c 0x5c8 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_PWRCTRL3__EPCD_PWRCTRL3 0x230 0x5cc 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_PWRCTRL3__GPIO4_20 0x230 0x5cc 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_PWRCTRL3__EIM_WEIM_EB_2 0x230 0x5cc 0x000 0x2 0x0 +-#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT_EVENT_1 0x230 0x5cc 0x7bc 0x6 0x1 +-#define MX50_PAD_EPDC_PWRCTRL3__USBPHY1_BISTOK 0x230 0x5cc 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_VCOM0__EPCD_VCOM_0 0x234 0x5d0 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_VCOM0__GPIO4_21 0x234 0x5d0 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_VCOM0__EIM_WEIM_EB_3 0x234 0x5d0 0x000 0x2 0x0 +-#define MX50_PAD_EPDC_VCOM0__USBPHY2_BISTOK 0x234 0x5d0 0x000 0x7 0x0 +-#define MX50_PAD_EPDC_VCOM1__EPCD_VCOM_1 0x238 0x5d4 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_VCOM1__GPIO4_22 0x238 0x5d4 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_VCOM1__EIM_WEIM_CS_3 0x238 0x5d4 0x000 0x2 0x0 +-#define MX50_PAD_EPDC_BDR0__EPCD_BDR_0 0x23c 0x5d8 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_BDR0__GPIO4_23 0x23c 0x5d8 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_BDR0__ELCDIF_DAT_7 0x23c 0x5d8 0x718 0x3 0x1 +-#define MX50_PAD_EPDC_BDR1__EPCD_BDR_1 0x240 0x5dc 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_BDR1__GPIO4_24 0x240 0x5dc 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_BDR1__ELCDIF_DAT_6 0x240 0x5dc 0x714 0x3 0x1 +-#define MX50_PAD_EPDC_SDCE0__EPCD_SDCE_0 0x244 0x5e0 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_SDCE0__GPIO4_25 0x244 0x5e0 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_SDCE0__ELCDIF_DAT_5 0x244 0x5e0 0x710 0x3 0x1 +-#define MX50_PAD_EPDC_SDCE1__EPCD_SDCE_1 0x248 0x5e4 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_SDCE1__GPIO4_26 0x248 0x5e4 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_SDCE1__ELCDIF_DAT_4 0x248 0x5e4 0x70c 0x3 0x0 +-#define MX50_PAD_EPDC_SDCE2__EPCD_SDCE_2 0x24c 0x5e8 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_SDCE2__GPIO4_27 0x24c 0x5e8 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT_3 0x24c 0x5e8 0x708 0x3 0x1 +-#define MX50_PAD_EPDC_SDCE3__EPCD_SDCE_3 0x250 0x5ec 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_SDCE3__GPIO4_28 0x250 0x5ec 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_SDCE3__ELCDIF_DAT_2 0x250 0x5ec 0x704 0x3 0x1 +-#define MX50_PAD_EPDC_SDCE4__EPCD_SDCE_4 0x254 0x5f0 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_SDCE4__GPIO4_29 0x254 0x5f0 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_SDCE4__ELCDIF_DAT_1 0x254 0x5f0 0x700 0x3 0x1 +-#define MX50_PAD_EPDC_SDCE5__EPCD_SDCE_5 0x258 0x5f4 0x000 0x0 0x0 +-#define MX50_PAD_EPDC_SDCE5__GPIO4_30 0x258 0x5f4 0x000 0x1 0x0 +-#define MX50_PAD_EPDC_SDCE5__ELCDIF_DAT_0 0x258 0x5f4 0x6fc 0x3 0x1 +-#define MX50_PAD_EIM_DA0__EIM_WEIM_A_0 0x25c 0x5f8 0x000 0x0 0x0 +-#define MX50_PAD_EIM_DA0__GPIO1_0 0x25c 0x5f8 0x000 0x1 0x0 +-#define MX50_PAD_EIM_DA0__KPP_COL_4 0x25c 0x5f8 0x790 0x3 0x2 +-#define MX50_PAD_EIM_DA0__TPIU_TRACE_0 0x25c 0x5f8 0x000 0x6 0x0 +-#define MX50_PAD_EIM_DA0__SRC_BT_CFG1_0 0x25c 0x5f8 0x000 0x7 0x0 +-#define MX50_PAD_EIM_DA1__EIM_WEIM_A_1 0x260 0x5fc 0x000 0x0 0x0 +-#define MX50_PAD_EIM_DA1__GPIO1_1 0x260 0x5fc 0x000 0x1 0x0 +-#define MX50_PAD_EIM_DA1__KPP_ROW_4 0x260 0x5fc 0x7a0 0x3 0x2 +-#define MX50_PAD_EIM_DA1__TPIU_TRACE_1 0x260 0x5fc 0x000 0x6 0x0 +-#define MX50_PAD_EIM_DA1__SRC_BT_CFG1_1 0x260 0x5fc 0x000 0x7 0x0 +-#define MX50_PAD_EIM_DA2__EIM_WEIM_A_2 0x264 0x600 0x000 0x0 0x0 +-#define MX50_PAD_EIM_DA2__GPIO1_2 0x264 0x600 0x000 0x1 0x0 +-#define MX50_PAD_EIM_DA2__KPP_COL_5 0x264 0x600 0x794 0x3 0x2 +-#define MX50_PAD_EIM_DA2__TPIU_TRACE_2 0x264 0x600 0x000 0x6 0x0 +-#define MX50_PAD_EIM_DA2__SRC_BT_CFG1_2 0x264 0x600 0x000 0x7 0x0 +-#define MX50_PAD_EIM_DA3__EIM_WEIM_A_3 0x268 0x604 0x000 0x0 0x0 +-#define MX50_PAD_EIM_DA3__GPIO1_3 0x268 0x604 0x000 0x1 0x0 +-#define MX50_PAD_EIM_DA3__KPP_ROW_5 0x268 0x604 0x7a4 0x3 0x2 +-#define MX50_PAD_EIM_DA3__TPIU_TRACE_3 0x268 0x604 0x000 0x6 0x0 +-#define MX50_PAD_EIM_DA3__SRC_BT_CFG1_3 0x268 0x604 0x000 0x7 0x0 +-#define MX50_PAD_EIM_DA4__EIM_WEIM_A_4 0x26c 0x608 0x000 0x0 0x0 +-#define MX50_PAD_EIM_DA4__GPIO1_4 0x26c 0x608 0x000 0x1 0x0 +-#define MX50_PAD_EIM_DA4__KPP_COL_6 0x26c 0x608 0x798 0x3 0x2 +-#define MX50_PAD_EIM_DA4__TPIU_TRACE_4 0x26c 0x608 0x000 0x6 0x0 +-#define MX50_PAD_EIM_DA4__SRC_BT_CFG1_4 0x26c 0x608 0x000 0x7 0x0 +-#define MX50_PAD_EIM_DA5__EIM_WEIM_A_5 0x270 0x60c 0x000 0x0 0x0 +-#define MX50_PAD_EIM_DA5__GPIO1_5 0x270 0x60c 0x000 0x1 0x0 +-#define MX50_PAD_EIM_DA5__KPP_ROW_6 0x270 0x60c 0x7a8 0x3 0x2 +-#define MX50_PAD_EIM_DA5__TPIU_TRACE_5 0x270 0x60c 0x000 0x6 0x0 +-#define MX50_PAD_EIM_DA5__SRC_BT_CFG1_5 0x270 0x60c 0x000 0x7 0x0 +-#define MX50_PAD_EIM_DA6__EIM_WEIM_A_6 0x274 0x610 0x000 0x0 0x0 +-#define MX50_PAD_EIM_DA6__GPIO1_6 0x274 0x610 0x000 0x1 0x0 +-#define MX50_PAD_EIM_DA6__KPP_COL_7 0x274 0x610 0x79c 0x3 0x2 +-#define MX50_PAD_EIM_DA6__TPIU_TRACE_6 0x274 0x610 0x000 0x6 0x0 +-#define MX50_PAD_EIM_DA6__SRC_BT_CFG1_6 0x274 0x610 0x000 0x7 0x0 +-#define MX50_PAD_EIM_DA7__EIM_WEIM_A_7 0x278 0x614 0x000 0x0 0x0 +-#define MX50_PAD_EIM_DA7__GPIO1_7 0x278 0x614 0x000 0x1 0x0 +-#define MX50_PAD_EIM_DA7__KPP_ROW_7 0x278 0x614 0x7ac 0x3 0x2 +-#define MX50_PAD_EIM_DA7__TPIU_TRACE_7 0x278 0x614 0x000 0x6 0x0 +-#define MX50_PAD_EIM_DA7__SRC_BT_CFG1_7 0x278 0x614 0x000 0x7 0x0 +-#define MX50_PAD_EIM_DA8__EIM_WEIM_A_8 0x27c 0x618 0x000 0x0 0x0 +-#define MX50_PAD_EIM_DA8__GPIO1_8 0x27c 0x618 0x000 0x1 0x0 +-#define MX50_PAD_EIM_DA8__EIM_NANDF_CLE 0x27c 0x618 0x000 0x2 0x0 +-#define MX50_PAD_EIM_DA8__TPIU_TRACE_8 0x27c 0x618 0x000 0x6 0x0 +-#define MX50_PAD_EIM_DA8__SRC_BT_CFG2_0 0x27c 0x618 0x000 0x7 0x0 +-#define MX50_PAD_EIM_DA9__EIM_WEIM_A_9 0x280 0x61c 0x000 0x0 0x0 +-#define MX50_PAD_EIM_DA9__GPIO1_9 0x280 0x61c 0x000 0x1 0x0 +-#define MX50_PAD_EIM_DA9__EIM_NANDF_ALE 0x280 0x61c 0x000 0x2 0x0 +-#define MX50_PAD_EIM_DA9__TPIU_TRACE_9 0x280 0x61c 0x000 0x6 0x0 +-#define MX50_PAD_EIM_DA9__SRC_BT_CFG2_1 0x280 0x61c 0x000 0x7 0x0 +-#define MX50_PAD_EIM_DA10__EIM_WEIM_A_10 0x284 0x620 0x000 0x0 0x0 +-#define MX50_PAD_EIM_DA10__GPIO1_10 0x284 0x620 0x000 0x1 0x0 +-#define MX50_PAD_EIM_DA10__EIM_NANDF_CEN_0 0x284 0x620 0x000 0x2 0x0 +-#define MX50_PAD_EIM_DA10__TPIU_TRACE_10 0x284 0x620 0x000 0x6 0x0 +-#define MX50_PAD_EIM_DA10__SRC_BT_CFG2_2 0x284 0x620 0x000 0x7 0x0 +-#define MX50_PAD_EIM_DA11__EIM_WEIM_A_11 0x288 0x624 0x000 0x0 0x0 +-#define MX50_PAD_EIM_DA11__GPIO1_11 0x288 0x624 0x000 0x1 0x0 +-#define MX50_PAD_EIM_DA11__EIM_NANDF_CEN_1 0x288 0x624 0x000 0x2 0x0 +-#define MX50_PAD_EIM_DA11__TPIU_TRACE_11 0x288 0x624 0x000 0x6 0x0 +-#define MX50_PAD_EIM_DA11__SRC_BT_CFG2_3 0x288 0x624 0x000 0x7 0x0 +-#define MX50_PAD_EIM_DA12__EIM_WEIM_A_12 0x28c 0x628 0x000 0x0 0x0 +-#define MX50_PAD_EIM_DA12__GPIO1_12 0x28c 0x628 0x000 0x1 0x0 +-#define MX50_PAD_EIM_DA12__EIM_NANDF_CEN_2 0x28c 0x628 0x000 0x2 0x0 +-#define MX50_PAD_EIM_DA12__EPDC_SDCE_6 0x28c 0x628 0x000 0x3 0x0 +-#define MX50_PAD_EIM_DA12__TPIU_TRACE_12 0x28c 0x628 0x000 0x6 0x0 +-#define MX50_PAD_EIM_DA12__SRC_BT_CFG2_4 0x28c 0x628 0x000 0x7 0x0 +-#define MX50_PAD_EIM_DA13__EIM_WEIM_A_13 0x290 0x62c 0x000 0x0 0x0 +-#define MX50_PAD_EIM_DA13__GPIO1_13 0x290 0x62c 0x000 0x1 0x0 +-#define MX50_PAD_EIM_DA13__EIM_NANDF_CEN_3 0x290 0x62c 0x000 0x2 0x0 +-#define MX50_PAD_EIM_DA13__EPDC_SDCE_7 0x290 0x62c 0x000 0x3 0x0 +-#define MX50_PAD_EIM_DA13__TPIU_TRACE_13 0x290 0x62c 0x000 0x6 0x0 +-#define MX50_PAD_EIM_DA13__SRC_BT_CFG2_5 0x290 0x62c 0x000 0x7 0x0 +-#define MX50_PAD_EIM_DA14__EIM_WEIM_A_14 0x294 0x630 0x000 0x0 0x0 +-#define MX50_PAD_EIM_DA14__GPIO1_14 0x294 0x630 0x000 0x1 0x0 +-#define MX50_PAD_EIM_DA14__EIM_NANDF_READY0 0x294 0x630 0x7b4 0x2 0x2 +-#define MX50_PAD_EIM_DA14__EPDC_SDCE_8 0x294 0x630 0x000 0x3 0x0 +-#define MX50_PAD_EIM_DA14__TPIU_TRACE_14 0x294 0x630 0x000 0x6 0x0 +-#define MX50_PAD_EIM_DA14__SRC_BT_CFG2_6 0x294 0x630 0x000 0x7 0x0 +-#define MX50_PAD_EIM_DA15__EIM_WEIM_A_15 0x298 0x634 0x000 0x0 0x0 +-#define MX50_PAD_EIM_DA15__GPIO1_15 0x298 0x634 0x000 0x1 0x0 +-#define MX50_PAD_EIM_DA15__EIM_NANDF_DQS 0x298 0x634 0x7b0 0x2 0x2 +-#define MX50_PAD_EIM_DA15__EPDC_SDCE_9 0x298 0x634 0x000 0x3 0x0 +-#define MX50_PAD_EIM_DA15__TPIU_TRACE_15 0x298 0x634 0x000 0x6 0x0 +-#define MX50_PAD_EIM_DA15__SRC_BT_CFG2_7 0x298 0x634 0x000 0x7 0x0 +-#define MX50_PAD_EIM_CS2__EIM_WEIM_CS_2 0x29c 0x638 0x000 0x0 0x0 +-#define MX50_PAD_EIM_CS2__GPIO1_16 0x29c 0x638 0x000 0x1 0x0 +-#define MX50_PAD_EIM_CS2__EIM_WEIM_A_27 0x29c 0x638 0x000 0x2 0x0 +-#define MX50_PAD_EIM_CS2__TPIU_TRCLK 0x29c 0x638 0x000 0x6 0x0 +-#define MX50_PAD_EIM_CS2__SRC_BT_CFG3_0 0x29c 0x638 0x000 0x7 0x0 +-#define MX50_PAD_EIM_CS1__EIM_WEIM_CS_1 0x2a0 0x63c 0x000 0x0 0x0 +-#define MX50_PAD_EIM_CS1__GPIO1_17 0x2a0 0x63c 0x000 0x1 0x0 +-#define MX50_PAD_EIM_CS1__TPIU_TRCTL 0x2a0 0x63c 0x000 0x6 0x0 +-#define MX50_PAD_EIM_CS1__SRC_BT_CFG3_1 0x2a0 0x63c 0x000 0x7 0x0 +-#define MX50_PAD_EIM_CS0__EIM_WEIM_CS_0 0x2a4 0x640 0x000 0x0 0x0 +-#define MX50_PAD_EIM_CS0__GPIO1_18 0x2a4 0x640 0x000 0x1 0x0 +-#define MX50_PAD_EIM_CS0__SRC_BT_CFG3_2 0x2a4 0x640 0x000 0x7 0x0 +-#define MX50_PAD_EIM_EB0__EIM_WEIM_EB_0 0x2a8 0x644 0x000 0x0 0x0 +-#define MX50_PAD_EIM_EB0__GPIO1_19 0x2a8 0x644 0x000 0x1 0x0 +-#define MX50_PAD_EIM_EB0__SRC_BT_CFG3_3 0x2a8 0x644 0x000 0x7 0x0 +-#define MX50_PAD_EIM_EB1__EIM_WEIM_EB_1 0x2ac 0x648 0x000 0x0 0x0 +-#define MX50_PAD_EIM_EB1__GPIO1_20 0x2ac 0x648 0x000 0x1 0x0 +-#define MX50_PAD_EIM_EB1__SRC_BT_CFG3_4 0x2ac 0x648 0x000 0x7 0x0 +-#define MX50_PAD_EIM_WAIT__EIM_WEIM_WAIT 0x2b0 0x64c 0x000 0x0 0x0 +-#define MX50_PAD_EIM_WAIT__GPIO1_21 0x2b0 0x64c 0x000 0x1 0x0 +-#define MX50_PAD_EIM_WAIT__EIM_WEIM_DTACK_B 0x2b0 0x64c 0x000 0x2 0x0 +-#define MX50_PAD_EIM_WAIT__SRC_BT_CFG3_5 0x2b0 0x64c 0x000 0x7 0x0 +-#define MX50_PAD_EIM_BCLK__EIM_WEIM_BCLK 0x2b4 0x650 0x000 0x0 0x0 +-#define MX50_PAD_EIM_BCLK__GPIO1_22 0x2b4 0x650 0x000 0x1 0x0 +-#define MX50_PAD_EIM_BCLK__SRC_BT_CFG3_6 0x2b4 0x650 0x000 0x7 0x0 +-#define MX50_PAD_EIM_RDY__EIM_WEIM_RDY 0x2b8 0x654 0x000 0x0 0x0 +-#define MX50_PAD_EIM_RDY__GPIO1_23 0x2b8 0x654 0x000 0x1 0x0 +-#define MX50_PAD_EIM_RDY__SRC_BT_CFG3_7 0x2b8 0x654 0x000 0x7 0x0 +-#define MX50_PAD_EIM_OE__EIM_WEIM_OE 0x2bc 0x658 0x000 0x0 0x0 +-#define MX50_PAD_EIM_OE__GPIO1_24 0x2bc 0x658 0x000 0x1 0x0 +-#define MX50_PAD_EIM_OE__INT_BOOT 0x2bc 0x658 0x000 0x7 0x0 +-#define MX50_PAD_EIM_RW__EIM_WEIM_RW 0x2c0 0x65c 0x000 0x0 0x0 +-#define MX50_PAD_EIM_RW__GPIO1_25 0x2c0 0x65c 0x000 0x1 0x0 +-#define MX50_PAD_EIM_RW__SYSTEM_RST 0x2c0 0x65c 0x000 0x7 0x0 +-#define MX50_PAD_EIM_LBA__EIM_WEIM_LBA 0x2c4 0x660 0x000 0x0 0x0 +-#define MX50_PAD_EIM_LBA__GPIO1_26 0x2c4 0x660 0x000 0x1 0x0 +-#define MX50_PAD_EIM_LBA__TESTER_ACK 0x2c4 0x660 0x000 0x7 0x0 +-#define MX50_PAD_EIM_CRE__EIM_WEIM_CRE 0x2c8 0x664 0x000 0x0 0x0 +-#define MX50_PAD_EIM_CRE__GPIO1_27 0x2c8 0x664 0x000 0x1 0x0 +- +-#endif /* __DTS_IMX50_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm/imx50.dtsi b/scripts/dtc/include-prefixes/arm/imx50.dtsi +deleted file mode 100644 +index a969f335b240..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx50.dtsi ++++ /dev/null +@@ -1,499 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2013 Greg Ungerer +-// Copyright 2011 Freescale Semiconductor, Inc. +-// Copyright 2011 Linaro Ltd. +- +-#include "imx50-pinfunc.h" +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * The decompressor and also some bootloaders rely on a +- * pre-existing /chosen node to be available to insert the +- * command line and merge other ATAGS info. +- */ +- chosen {}; +- +- aliases { +- ethernet0 = &fec; +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- gpio3 = &gpio4; +- gpio4 = &gpio5; +- gpio5 = &gpio6; +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- mmc0 = &esdhc1; +- mmc1 = &esdhc2; +- mmc2 = &esdhc3; +- mmc3 = &esdhc4; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- serial4 = &uart5; +- spi0 = &ecspi1; +- spi1 = &ecspi2; +- spi2 = &cspi; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a8"; +- reg = <0x0>; +- }; +- }; +- +- tzic: tz-interrupt-controller@fffc000 { +- compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x0fffc000 0x4000>; +- }; +- +- clocks { +- ckil { +- compatible = "fsl,imx-ckil", "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- ckih1 { +- compatible = "fsl,imx-ckih1", "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <22579200>; +- }; +- +- ckih2 { +- compatible = "fsl,imx-ckih2", "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- osc { +- compatible = "fsl,imx-osc", "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- }; +- }; +- +- usbphy0: usbphy-0 { +- compatible = "usb-nop-xceiv"; +- clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; +- clock-names = "main_clk"; +- #phy-cells = <0>; +- status = "okay"; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&tzic>; +- ranges; +- +- bus@50000000 { /* AIPS1 */ +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x50000000 0x10000000>; +- ranges; +- +- spba@50000000 { +- compatible = "fsl,spba-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x50000000 0x40000>; +- ranges; +- +- esdhc1: mmc@50004000 { +- compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; +- reg = <0x50004000 0x4000>; +- interrupts = <1>; +- clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, +- <&clks IMX5_CLK_DUMMY>, +- <&clks IMX5_CLK_ESDHC1_PER_GATE>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- esdhc2: mmc@50008000 { +- compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; +- reg = <0x50008000 0x4000>; +- interrupts = <2>; +- clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, +- <&clks IMX5_CLK_DUMMY>, +- <&clks IMX5_CLK_ESDHC2_PER_GATE>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- uart3: serial@5000c000 { +- compatible = "fsl,imx50-uart", "fsl,imx21-uart"; +- reg = <0x5000c000 0x4000>; +- interrupts = <33>; +- clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, +- <&clks IMX5_CLK_UART3_PER_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- ecspi1: spi@50010000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi"; +- reg = <0x50010000 0x4000>; +- interrupts = <36>; +- clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, +- <&clks IMX5_CLK_ECSPI1_PER_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- ssi2: ssi@50014000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx50-ssi", +- "fsl,imx51-ssi", +- "fsl,imx21-ssi"; +- reg = <0x50014000 0x4000>; +- interrupts = <30>; +- clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; +- dmas = <&sdma 24 1 0>, +- <&sdma 25 1 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- esdhc3: mmc@50020000 { +- compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; +- reg = <0x50020000 0x4000>; +- interrupts = <3>; +- clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, +- <&clks IMX5_CLK_DUMMY>, +- <&clks IMX5_CLK_ESDHC3_PER_GATE>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- esdhc4: mmc@50024000 { +- compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; +- reg = <0x50024000 0x4000>; +- interrupts = <4>; +- clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, +- <&clks IMX5_CLK_DUMMY>, +- <&clks IMX5_CLK_ESDHC4_PER_GATE>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- }; +- +- usbotg: usb@53f80000 { +- compatible = "fsl,imx50-usb", "fsl,imx27-usb"; +- reg = <0x53f80000 0x0200>; +- interrupts = <18>; +- clocks = <&clks IMX5_CLK_USBOH3_GATE>; +- fsl,usbphy = <&usbphy0>; +- status = "disabled"; +- }; +- +- usbh1: usb@53f80200 { +- compatible = "fsl,imx50-usb", "fsl,imx27-usb"; +- reg = <0x53f80200 0x0200>; +- interrupts = <14>; +- clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; +- dr_mode = "host"; +- status = "disabled"; +- }; +- +- gpio1: gpio@53f84000 { +- compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; +- reg = <0x53f84000 0x4000>; +- interrupts = <50 51>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 151 28>; +- }; +- +- gpio2: gpio@53f88000 { +- compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; +- reg = <0x53f88000 0x4000>; +- interrupts = <52 53>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>, +- <&iomuxc 16 83 1>, <&iomuxc 17 85 1>, +- <&iomuxc 18 87 1>, <&iomuxc 19 84 1>, +- <&iomuxc 20 88 1>, <&iomuxc 21 86 1>; +- }; +- +- gpio3: gpio@53f8c000 { +- compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; +- reg = <0x53f8c000 0x4000>; +- interrupts = <54 55>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 108 32>; +- }; +- +- gpio4: gpio@53f90000 { +- compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; +- reg = <0x53f90000 0x4000>; +- interrupts = <56 57>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>, +- <&iomuxc 20 140 11>; +- }; +- +- wdog1: watchdog@53f98000 { +- compatible = "fsl,imx50-wdt", "fsl,imx21-wdt"; +- reg = <0x53f98000 0x4000>; +- interrupts = <58>; +- clocks = <&clks IMX5_CLK_DUMMY>; +- }; +- +- gpt: timer@53fa0000 { +- compatible = "fsl,imx50-gpt", "fsl,imx31-gpt"; +- reg = <0x53fa0000 0x4000>; +- interrupts = <39>; +- clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, +- <&clks IMX5_CLK_GPT_HF_GATE>; +- clock-names = "ipg", "per"; +- }; +- +- iomuxc: iomuxc@53fa8000 { +- compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc"; +- reg = <0x53fa8000 0x4000>; +- }; +- +- pwm1: pwm@53fb4000 { +- #pwm-cells = <3>; +- compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; +- reg = <0x53fb4000 0x4000>; +- clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, +- <&clks IMX5_CLK_PWM1_HF_GATE>; +- clock-names = "ipg", "per"; +- interrupts = <61>; +- }; +- +- pwm2: pwm@53fb8000 { +- #pwm-cells = <3>; +- compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; +- reg = <0x53fb8000 0x4000>; +- clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, +- <&clks IMX5_CLK_PWM2_HF_GATE>; +- clock-names = "ipg", "per"; +- interrupts = <94>; +- }; +- +- uart1: serial@53fbc000 { +- compatible = "fsl,imx50-uart", "fsl,imx21-uart"; +- reg = <0x53fbc000 0x4000>; +- interrupts = <31>; +- clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, +- <&clks IMX5_CLK_UART1_PER_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart2: serial@53fc0000 { +- compatible = "fsl,imx50-uart", "fsl,imx21-uart"; +- reg = <0x53fc0000 0x4000>; +- interrupts = <32>; +- clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, +- <&clks IMX5_CLK_UART2_PER_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- src: reset-controller@53fd0000 { +- compatible = "fsl,imx50-src", "fsl,imx51-src"; +- reg = <0x53fd0000 0x4000>; +- interrupts = <75>; +- #reset-cells = <1>; +- }; +- +- clks: ccm@53fd4000{ +- compatible = "fsl,imx50-ccm"; +- reg = <0x53fd4000 0x4000>; +- interrupts = <0 71 0x04 0 72 0x04>; +- #clock-cells = <1>; +- }; +- +- gpio5: gpio@53fdc000 { +- compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; +- reg = <0x53fdc000 0x4000>; +- interrupts = <103 104>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>; +- }; +- +- gpio6: gpio@53fe0000 { +- compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; +- reg = <0x53fe0000 0x4000>; +- interrupts = <105 106>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>; +- }; +- +- i2c3: i2c@53fec000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; +- reg = <0x53fec000 0x4000>; +- interrupts = <64>; +- clocks = <&clks IMX5_CLK_I2C3_GATE>; +- status = "disabled"; +- }; +- +- uart4: serial@53ff0000 { +- compatible = "fsl,imx50-uart", "fsl,imx21-uart"; +- reg = <0x53ff0000 0x4000>; +- interrupts = <13>; +- clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, +- <&clks IMX5_CLK_UART4_PER_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- }; +- +- bus@60000000 { /* AIPS2 */ +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x60000000 0x10000000>; +- ranges; +- +- uart5: serial@63f90000 { +- compatible = "fsl,imx50-uart", "fsl,imx21-uart"; +- reg = <0x63f90000 0x4000>; +- interrupts = <86>; +- clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, +- <&clks IMX5_CLK_UART5_PER_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- owire: owire@63fa4000 { +- compatible = "fsl,imx50-owire", "fsl,imx21-owire"; +- reg = <0x63fa4000 0x4000>; +- clocks = <&clks IMX5_CLK_OWIRE_GATE>; +- status = "disabled"; +- }; +- +- ecspi2: spi@63fac000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi"; +- reg = <0x63fac000 0x4000>; +- interrupts = <37>; +- clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, +- <&clks IMX5_CLK_ECSPI2_PER_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- sdma: sdma@63fb0000 { +- compatible = "fsl,imx50-sdma", "fsl,imx35-sdma"; +- reg = <0x63fb0000 0x4000>; +- interrupts = <6>; +- clocks = <&clks IMX5_CLK_SDMA_GATE>, +- <&clks IMX5_CLK_AHB>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin"; +- }; +- +- cspi: spi@63fc0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx50-cspi", "fsl,imx35-cspi"; +- reg = <0x63fc0000 0x4000>; +- interrupts = <38>; +- clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, +- <&clks IMX5_CLK_CSPI_IPG_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- i2c2: i2c@63fc4000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; +- reg = <0x63fc4000 0x4000>; +- interrupts = <63>; +- clocks = <&clks IMX5_CLK_I2C2_GATE>; +- status = "disabled"; +- }; +- +- i2c1: i2c@63fc8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; +- reg = <0x63fc8000 0x4000>; +- interrupts = <62>; +- clocks = <&clks IMX5_CLK_I2C1_GATE>; +- status = "disabled"; +- }; +- +- ssi1: ssi@63fcc000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx50-ssi", "fsl,imx51-ssi", +- "fsl,imx21-ssi"; +- reg = <0x63fcc000 0x4000>; +- interrupts = <29>; +- clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; +- dmas = <&sdma 28 0 0>, +- <&sdma 29 0 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- audmux: audmux@63fd0000 { +- compatible = "fsl,imx50-audmux", "fsl,imx31-audmux"; +- reg = <0x63fd0000 0x4000>; +- status = "disabled"; +- }; +- +- fec: ethernet@63fec000 { +- compatible = "fsl,imx53-fec", "fsl,imx25-fec"; +- reg = <0x63fec000 0x4000>; +- interrupts = <87>; +- clocks = <&clks IMX5_CLK_FEC_GATE>, +- <&clks IMX5_CLK_FEC_GATE>, +- <&clks IMX5_CLK_FEC_GATE>; +- clock-names = "ipg", "ahb", "ptp"; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx51-apf51.dts b/scripts/dtc/include-prefixes/arm/imx51-apf51.dts +deleted file mode 100644 +index ba28ffe06fe2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx51-apf51.dts ++++ /dev/null +@@ -1,84 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Armadeus Systems - +- * Copyright 2012 Laurent Cans +- * +- * Based on mx51-babbage.dts +- * Copyright 2011 Freescale Semiconductor, Inc. +- * Copyright 2011 Linaro Ltd. +- */ +- +-/dts-v1/; +-#include "imx51.dtsi" +- +-/ { +- model = "Armadeus Systems APF51 module"; +- compatible = "armadeus,imx51-apf51", "fsl,imx51"; +- +- memory@90000000 { +- device_type = "memory"; +- reg = <0x90000000 0x20000000>; +- }; +- +- clocks { +- osc { +- clock-frequency = <33554432>; +- }; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-mode = "mii"; +- phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <1>; +- status = "okay"; +-}; +- +-&iomuxc { +- imx51-apf51 { +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 +- MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 +- MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 +- MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 +- MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 +- MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 +- MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 +- MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 +- MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 +- MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 +- MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 +- MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 +- MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 +- MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 +- MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 +- MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 +- MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 +- MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 +- MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 +- >; +- }; +- }; +-}; +- +-&nfc { +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-on-flash-bbt; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx51-apf51dev.dts b/scripts/dtc/include-prefixes/arm/imx51-apf51dev.dts +deleted file mode 100644 +index c66f274ba4e9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx51-apf51dev.dts ++++ /dev/null +@@ -1,217 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Armadeus Systems - +- */ +- +-/* APF51Dev is a docking board for the APF51 SOM */ +-#include "imx51-apf51.dts" +- +-/ { +- model = "Armadeus Systems APF51Dev docking/development board"; +- compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51"; +- +- backlight { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_backlight>; +- compatible = "gpio-backlight"; +- gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; +- default-on; +- }; +- +- disp1 { +- compatible = "fsl,imx-parallel-display"; +- interface-pix-fmt = "bgr666"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu_disp1>; +- +- display-timings { +- lw700 { +- native-mode; +- clock-frequency = <33000033>; +- hactive = <800>; +- vactive = <480>; +- hback-porch = <96>; +- hfront-porch = <96>; +- vback-porch = <20>; +- vfront-porch = <21>; +- hsync-len = <64>; +- vsync-len = <4>; +- hsync-active = <1>; +- vsync-active = <1>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- }; +- +- port { +- display_in: endpoint { +- remote-endpoint = <&ipu_di0_disp1>; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-key { +- label = "user"; +- gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; +- linux,code = <256>; /* BTN_0 */ +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- user { +- label = "Heartbeat"; +- gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>, +- <&gpio4 25 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- cs-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>, +- <&gpio3 27 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- cd-gpios = <&gpio2 29 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&esdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc2>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx51-apf51dev { +- pinctrl_backlight: backlightgrp { +- fsl,pins = < +- MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5 +- >; +- }; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX51_PAD_EIM_EB2__GPIO2_22 0x0C5 +- MX51_PAD_EIM_EB3__GPIO2_23 0x0C5 +- MX51_PAD_EIM_CS4__GPIO2_29 0x100 +- MX51_PAD_NANDF_D13__GPIO3_27 0x0C5 +- MX51_PAD_NANDF_D12__GPIO3_28 0x0C5 +- MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5 +- MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5 +- MX51_PAD_GPIO1_2__GPIO1_2 0x0C5 +- MX51_PAD_GPIO1_3__GPIO1_3 0x0C5 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 +- MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 +- MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 +- MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 +- MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 +- MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 +- MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 +- MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 +- MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 +- MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 +- >; +- }; +- +- pinctrl_esdhc2: esdhc2grp { +- fsl,pins = < +- MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 +- MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 +- MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 +- MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 +- MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 +- MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed +- MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed +- >; +- }; +- +- pinctrl_ipu_disp1: ipudisp1grp { +- fsl,pins = < +- MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 +- MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 +- MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 +- MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 +- MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 +- MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 +- MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 +- MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 +- MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 +- MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 +- MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 +- MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 +- MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 +- MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 +- MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 +- MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 +- MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 +- MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 +- MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 +- MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 +- MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 +- MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 +- MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 +- MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 +- MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 +- MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 +- >; +- }; +- }; +-}; +- +-&ipu_di0_disp1 { +- remote-endpoint = <&display_in>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx51-babbage.dts b/scripts/dtc/include-prefixes/arm/imx51-babbage.dts +deleted file mode 100644 +index 552196d8a60a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx51-babbage.dts ++++ /dev/null +@@ -1,726 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2011 Freescale Semiconductor, Inc. +-// Copyright 2011 Linaro Ltd. +- +-/dts-v1/; +-#include "imx51.dtsi" +- +-/ { +- model = "Freescale i.MX51 Babbage Board"; +- compatible = "fsl,imx51-babbage", "fsl,imx51"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@90000000 { +- device_type = "memory"; +- reg = <0x90000000 0x20000000>; +- }; +- +- ckih1 { +- clock-frequency = <22579200>; +- }; +- +- clk_osc: clk-osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +- +- clk_osc_gate: clk-osc-gate { +- compatible = "gpio-gate-clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_clk26mhz_osc>; +- clocks = <&clk_osc>; +- #clock-cells = <0>; +- enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; +- }; +- +- clk_audio: clk-audio { +- compatible = "gpio-gate-clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_clk26mhz_audio>; +- clocks = <&clk_osc_gate>; +- #clock-cells = <0>; +- enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; +- }; +- +- clk_usb: clk-usb { +- compatible = "gpio-gate-clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_clk26mhz_usb>; +- clocks = <&clk_osc_gate>; +- #clock-cells = <0>; +- enable-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +- }; +- +- display1: disp1 { +- compatible = "fsl,imx-parallel-display"; +- #address-cells = <1>; +- #size-cells = <0>; +- interface-pix-fmt = "rgb24"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu_disp1>; +- +- port@0 { +- reg = <0>; +- +- display0_in: endpoint { +- remote-endpoint = <&ipu_di0_disp1>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- parallel_display_out: endpoint { +- remote-endpoint = <&tfp410_in>; +- }; +- }; +- }; +- +- display2: disp2 { +- compatible = "fsl,imx-parallel-display"; +- interface-pix-fmt = "rgb565"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu_disp2>; +- status = "disabled"; +- display-timings { +- native-mode = <&timing1>; +- timing1: claawvga { +- clock-frequency = <27000000>; +- hactive = <800>; +- vactive = <480>; +- hback-porch = <40>; +- hfront-porch = <60>; +- vback-porch = <10>; +- vfront-porch = <10>; +- hsync-len = <20>; +- vsync-len = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- }; +- +- port { +- display1_in: endpoint { +- remote-endpoint = <&ipu_di1_disp2>; +- }; +- }; +- }; +- +- dvi-connector { +- compatible = "dvi-connector"; +- digital; +- +- port { +- dvi_connector_in: endpoint { +- remote-endpoint = <&tfp410_out>; +- }; +- }; +- }; +- +- dvi-encoder { +- compatible = "ti,tfp410"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tfp410_in: endpoint { +- remote-endpoint = <¶llel_display_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- tfp410_out: endpoint { +- remote-endpoint = <&dvi_connector_in>; +- }; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- power { +- label = "Power Button"; +- gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led-diagnostic { +- label = "diagnostic"; +- gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_hub_reset: regulator@0 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotgreg>; +- reg = <0>; +- regulator-name = "hub_reset"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- }; +- +- sound { +- compatible = "fsl,imx51-babbage-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "imx51-babbage-sgtl5000"; +- ssi-controller = <&ssi2>; +- audio-codec = <&sgtl5000>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <2>; +- mux-ext-port = <3>; +- }; +- +- usbphy1: usbphy1 { +- compatible = "usb-nop-xceiv"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1reg>; +- clocks = <&clk_usb>; +- clock-names = "main_clk"; +- reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; +- vcc-supply = <&vusb_reg>; +- #phy-cells = <0>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, +- <&gpio4 25 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- pmic: mc13892@0 { +- compatible = "fsl,mc13892"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- spi-max-frequency = <6000000>; +- spi-cs-high; +- reg = <0>; +- interrupt-parent = <&gpio1>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; +- fsl,mc13xxx-uses-adc; +- fsl,mc13xxx-uses-rtc; +- +- regulators { +- sw1_reg: sw1 { +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1375000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3_reg: sw3 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vpll_reg: vpll { +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdig_reg: vdig { +- regulator-min-microvolt = <1650000>; +- regulator-max-microvolt = <1650000>; +- regulator-boot-on; +- }; +- +- vsd_reg: vsd { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3150000>; +- }; +- +- vusb_reg: vusb { +- regulator-boot-on; +- }; +- +- vusb2_reg: vusb2 { +- regulator-min-microvolt = <2400000>; +- regulator-max-microvolt = <2775000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vvideo_reg: vvideo { +- regulator-min-microvolt = <2775000>; +- regulator-max-microvolt = <2775000>; +- }; +- +- vaudio_reg: vaudio { +- regulator-min-microvolt = <2300000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- vcam_reg: vcam { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3150000>; +- regulator-always-on; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2900000>; +- regulator-always-on; +- }; +- }; +- }; +- +- flash: at45db321d@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; +- spi-max-frequency = <25000000>; +- reg = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0x0 0x40000>; +- read-only; +- }; +- +- partition@40000 { +- label = "Kernel"; +- reg = <0x40000 0x3c0000>; +- }; +- }; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&esdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc2>; +- cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-mode = "mii"; +- phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <1>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- clocks = <&clk_audio>; +- VDDA-supply = <&vdig_reg>; +- VDDIO-supply = <&vvideo_reg>; +- }; +-}; +- +-&ipu_di0_disp1 { +- remote-endpoint = <&display0_in>; +-}; +- +-&ipu_di1_disp2 { +- remote-endpoint = <&display1_in>; +-}; +- +-&kpp { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_kpp>; +- linux,keymap = < +- MATRIX_KEY(0, 0, KEY_UP) +- MATRIX_KEY(0, 1, KEY_DOWN) +- MATRIX_KEY(0, 2, KEY_VOLUMEDOWN) +- MATRIX_KEY(0, 3, KEY_HOME) +- MATRIX_KEY(1, 0, KEY_RIGHT) +- MATRIX_KEY(1, 1, KEY_LEFT) +- MATRIX_KEY(1, 2, KEY_ENTER) +- MATRIX_KEY(1, 3, KEY_VOLUMEUP) +- MATRIX_KEY(2, 0, KEY_F6) +- MATRIX_KEY(2, 1, KEY_F8) +- MATRIX_KEY(2, 2, KEY_F9) +- MATRIX_KEY(2, 3, KEY_F10) +- MATRIX_KEY(3, 0, KEY_F1) +- MATRIX_KEY(3, 1, KEY_F2) +- MATRIX_KEY(3, 2, KEY_F3) +- MATRIX_KEY(3, 3, KEY_POWER) +- >; +- status = "okay"; +-}; +- +-&pmu { +- secure-reg-access; +-}; +- +-&ssi2 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbh1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1>; +- vbus-supply = <®_hub_reset>; +- fsl,usbphy = <&usbphy1>; +- phy_type = "ulpi"; +- status = "okay"; +-}; +- +-&usbphy0 { +- vcc-supply = <&vusb_reg>; +-}; +- +-&usbotg { +- dr_mode = "otg"; +- disable-over-current; +- phy_type = "utmi_wide"; +- status = "okay"; +-}; +- +-&iomuxc { +- imx51-babbage { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 +- MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 +- MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 +- MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 +- >; +- }; +- +- pinctrl_clk26mhz_audio: clk26mhzaudiocgrp { +- fsl,pins = < +- MX51_PAD_CSPI1_RDY__GPIO4_26 0x85 +- >; +- }; +- +- pinctrl_clk26mhz_osc: clk26mhzoscgrp { +- fsl,pins = < +- MX51_PAD_DI1_PIN12__GPIO3_1 0x85 +- >; +- }; +- +- pinctrl_clk26mhz_usb: clk26mhzusbgrp { +- fsl,pins = < +- MX51_PAD_EIM_D17__GPIO2_1 0x85 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 +- MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 +- MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 +- MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ +- MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */ +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 +- MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 +- MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 +- MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 +- MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 +- MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 +- MX51_PAD_GPIO1_0__GPIO1_0 0x100 +- MX51_PAD_GPIO1_1__GPIO1_1 0x100 +- >; +- }; +- +- pinctrl_esdhc2: esdhc2grp { +- fsl,pins = < +- MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 +- MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 +- MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 +- MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 +- MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 +- MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 +- MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */ +- MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */ +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 +- MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 +- MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 +- MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 +- MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 +- MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 +- MX51_PAD_NANDF_RB2__FEC_COL 0x00000180 +- MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180 +- MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180 +- MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004 +- MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 +- MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004 +- MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004 +- MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004 +- MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004 +- MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004 +- MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180 +- MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4 +- MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ +- >; +- }; +- +- pinctrl_gpio_keys: gpiokeysgrp { +- fsl,pins = < +- MX51_PAD_EIM_A27__GPIO2_21 0x5 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX51_PAD_EIM_D22__GPIO2_6 0x80000000 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed +- MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed +- MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed +- >; +- }; +- +- pinctrl_ipu_disp1: ipudisp1grp { +- fsl,pins = < +- MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 +- MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 +- MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 +- MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 +- MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 +- MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 +- MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 +- MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 +- MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 +- MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 +- MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 +- MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 +- MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 +- MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 +- MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 +- MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 +- MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 +- MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 +- MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 +- MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 +- MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 +- MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 +- MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 +- MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 +- MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 +- MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 +- >; +- }; +- +- pinctrl_ipu_disp2: ipudisp2grp { +- fsl,pins = < +- MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 +- MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 +- MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 +- MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 +- MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 +- MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 +- MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 +- MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 +- MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 +- MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 +- MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 +- MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 +- MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 +- MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 +- MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 +- MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 +- MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 +- MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 +- MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 +- MX51_PAD_DI_GP4__DI2_PIN15 0x5 +- >; +- }; +- +- pinctrl_kpp: kppgrp { +- fsl,pins = < +- MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 +- MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 +- MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 +- MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 +- MX51_PAD_KEY_COL0__KEY_COL0 0xe8 +- MX51_PAD_KEY_COL1__KEY_COL1 0xe8 +- MX51_PAD_KEY_COL2__KEY_COL2 0xe8 +- MX51_PAD_KEY_COL3__KEY_COL3 0xe8 +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */ +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 +- MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 +- MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 +- MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 +- MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX51_PAD_EIM_D25__UART3_RXD 0x1c5 +- MX51_PAD_EIM_D26__UART3_TXD 0x1c5 +- MX51_PAD_EIM_D27__UART3_RTS 0x1c5 +- MX51_PAD_EIM_D24__UART3_CTS 0x1c5 +- >; +- }; +- +- pinctrl_usbh1: usbh1grp { +- fsl,pins = < +- MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000 +- MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000 +- MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000 +- MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000 +- MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000 +- MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000 +- MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000 +- MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000 +- MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000 +- MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000 +- MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000 +- >; +- }; +- +- pinctrl_usbh1reg: usbh1reggrp { +- fsl,pins = < +- MX51_PAD_EIM_D21__GPIO2_5 0x85 +- >; +- }; +- +- pinctrl_usbotgreg: usbotgreggrp { +- fsl,pins = < +- MX51_PAD_GPIO1_7__GPIO1_7 0x85 +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx51-digi-connectcore-jsk.dts b/scripts/dtc/include-prefixes/arm/imx51-digi-connectcore-jsk.dts +deleted file mode 100644 +index aab8d6f137c3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx51-digi-connectcore-jsk.dts ++++ /dev/null +@@ -1,118 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2014 Alexander Shiyan +- */ +- +-#include "imx51-digi-connectcore-som.dtsi" +- +-/ { +- model = "Digi ConnectCore CC(W)-MX51 JSK"; +- compatible = "digi,connectcore-ccxmx51-jsk", +- "digi,connectcore-ccxmx51-som", "fsl,imx51"; +- +- chosen { +- stdout-path = &uart1; +- }; +-}; +- +-&esdhc1 { +- status = "okay"; +-}; +- +-&owire { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_owire>; +- status = "okay"; +-}; +- +-&pmic { +- fsl,mc13xxx-uses-rtc; +- +- regulators { +- vcoincell_reg: vcoincell { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&usbotg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbh1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1>; +- dr_mode = "host"; +- phy_type = "ulpi"; +- disable-over-current; +- status = "okay"; +-}; +- +-&iomuxc { +- imx51-digi-connectcore-jsk { +- pinctrl_owire: owiregrp { +- fsl,pins = < +- MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x40000000 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 +- MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 +- MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 +- MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 +- >; +- }; +- +- pinctrl_usbh1: usbh1grp { +- fsl,pins = < +- MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 +- MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 +- MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 +- MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 +- MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 +- MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 +- MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 +- MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 +- MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 +- MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 +- MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 +- MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx51-digi-connectcore-som.dtsi b/scripts/dtc/include-prefixes/arm/imx51-digi-connectcore-som.dtsi +deleted file mode 100644 +index 7d4970417dce..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx51-digi-connectcore-som.dtsi ++++ /dev/null +@@ -1,389 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2014 Alexander Shiyan +- */ +- +-/dts-v1/; +-#include "imx51.dtsi" +- +-/ { +- model = "Digi ConnectCore CC(W)-MX51"; +- compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51"; +- +- memory@90000000 { +- device_type = "memory"; +- reg = <0x90000000 0x08000000>; +- }; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- +- pmic: mc13892@0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mc13892>; +- compatible = "fsl,mc13892"; +- spi-max-frequency = <16000000>; +- spi-cs-high; +- reg = <0>; +- interrupt-parent = <&gpio1>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; +- +- regulators { +- sw1_reg: sw1 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1100000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3_reg: sw3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { }; +- +- viohi_reg: viohi { +- regulator-always-on; +- }; +- +- vpll_reg: vpll { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vdig_reg: vdig { +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- }; +- +- vsd_reg: vsd { +- regulator-min-microvolt = <3150000>; +- regulator-max-microvolt = <3150000>; +- regulator-always-on; +- }; +- +- vusb2_reg: vusb2 { +- regulator-min-microvolt = <2600000>; +- regulator-max-microvolt = <2600000>; +- regulator-always-on; +- }; +- +- vvideo_reg: vvideo { +- regulator-min-microvolt = <2775000>; +- regulator-max-microvolt = <2775000>; +- regulator-always-on; +- }; +- +- vaudio_reg: vaudio { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- +- vcam_reg: vcam { +- regulator-min-microvolt = <2750000>; +- regulator-max-microvolt = <2750000>; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <3150000>; +- regulator-max-microvolt = <3150000>; +- regulator-always-on; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vusb_reg: vusb { +- regulator-always-on; +- }; +- +- gpo1_reg: gpo1 { }; +- +- gpo2_reg: gpo2 { }; +- +- gpo3_reg: gpo3 { }; +- +- gpo4_reg: gpo4 { }; +- +- pwgt2spi_reg: pwgt2spi { +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- max-frequency = <50000000>; +- bus-width = <1>; +-}; +- +-&esdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc2>; +- cap-sdio-irq; +- wakeup-source; +- keep-power-in-suspend; +- max-frequency = <50000000>; +- no-1-8-v; +- non-removable; +- vmmc-supply = <&gpo4_reg>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-mode = "mii"; +- phy-supply = <&gpo3_reg>; +- /* Pins shared with LCD2, keep status disabled */ +-}; +- +-&i2c2 { +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c2>; +- pinctrl-1 = <&pinctrl_i2c2_gpio>; +- clock-frequency = <400000>; +- scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- +- mma7455l@1d { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mma7455l>; +- compatible = "fsl,mma7455l"; +- reg = <0x1d>; +- interrupt-parent = <&gpio1>; +- interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>; +- }; +-}; +- +-&nfc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nfc>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-on-flash-bbt; +- status = "okay"; +-}; +- +-&usbotg { +- phy_type = "utmi_wide"; +- disable-over-current; +- /* Device role is not known, keep status disabled */ +-}; +- +-&weim { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_weim>; +- status = "okay"; +- +- lan9221: ethernet@5,0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lan9221>; +- compatible = "smsc,lan9221", "smsc,lan9115"; +- reg = <5 0x00000000 0x1000>; +- fsl,weim-cs-timing = < +- 0x00420081 0x00000000 +- 0x32260000 0x00000000 +- 0x72080f00 0x00000000 +- >; +- clocks = <&clks IMX5_CLK_DUMMY>; +- interrupt-parent = <&gpio1>; +- interrupts = <9 IRQ_TYPE_LEVEL_LOW>; +- phy-mode = "mii"; +- reg-io-width = <2>; +- smsc,irq-push-pull; +- vdd33a-supply = <&gpo2_reg>; +- vddvario-supply = <&gpo2_reg>; +- }; +-}; +- +-&iomuxc { +- imx51-digi-connectcore-som { +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 +- MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 +- MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 +- MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX51_PAD_SD1_CLK__SD1_CLK 0x400021d5 +- MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 +- MX51_PAD_SD1_DATA0__SD1_DATA0 0x400020d5 +- >; +- }; +- +- pinctrl_esdhc2: esdhc2grp { +- fsl,pins = < +- MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 +- MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 +- MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 +- MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 +- MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 +- MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 +- MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 +- MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 +- MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 +- MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 +- MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 +- MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 +- MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 +- MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 +- MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 +- MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 +- MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 +- MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 +- MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 +- MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 +- MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 +- MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 +- MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed +- MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed +- >; +- }; +- +- pinctrl_i2c2_gpio: i2c2gpiogrp { +- fsl,pins = < +- MX51_PAD_GPIO1_2__GPIO1_2 0x400001ed +- MX51_PAD_GPIO1_3__GPIO1_3 0x400001ed +- >; +- }; +- +- pinctrl_nfc: nfcgrp { +- fsl,pins = < +- MX51_PAD_NANDF_D0__NANDF_D0 0x80000000 +- MX51_PAD_NANDF_D1__NANDF_D1 0x80000000 +- MX51_PAD_NANDF_D2__NANDF_D2 0x80000000 +- MX51_PAD_NANDF_D3__NANDF_D3 0x80000000 +- MX51_PAD_NANDF_D4__NANDF_D4 0x80000000 +- MX51_PAD_NANDF_D5__NANDF_D5 0x80000000 +- MX51_PAD_NANDF_D6__NANDF_D6 0x80000000 +- MX51_PAD_NANDF_D7__NANDF_D7 0x80000000 +- MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000 +- MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000 +- MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000 +- MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000 +- MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000 +- MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000 +- MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000 +- >; +- }; +- +- pinctrl_lan9221: lan9221grp { +- fsl,pins = < +- MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */ +- >; +- }; +- +- pinctrl_mc13892: mc13892grp { +- fsl,pins = < +- MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */ +- >; +- }; +- +- pinctrl_mma7455l: mma7455lgrp { +- fsl,pins = < +- MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* IRQ1 */ +- MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* IRQ2 */ +- >; +- }; +- +- pinctrl_weim: weimgrp { +- fsl,pins = < +- MX51_PAD_EIM_DA0__EIM_DA0 0x80000000 +- MX51_PAD_EIM_DA1__EIM_DA1 0x80000000 +- MX51_PAD_EIM_DA2__EIM_DA2 0x80000000 +- MX51_PAD_EIM_DA3__EIM_DA3 0x80000000 +- MX51_PAD_EIM_DA4__EIM_DA4 0x80000000 +- MX51_PAD_EIM_DA5__EIM_DA5 0x80000000 +- MX51_PAD_EIM_DA6__EIM_DA6 0x80000000 +- MX51_PAD_EIM_DA7__EIM_DA7 0x80000000 +- MX51_PAD_EIM_DA8__EIM_DA8 0x80000000 +- MX51_PAD_EIM_DA9__EIM_DA9 0x80000000 +- MX51_PAD_EIM_DA10__EIM_DA10 0x80000000 +- MX51_PAD_EIM_DA11__EIM_DA11 0x80000000 +- MX51_PAD_EIM_DA12__EIM_DA12 0x80000000 +- MX51_PAD_EIM_DA13__EIM_DA13 0x80000000 +- MX51_PAD_EIM_DA14__EIM_DA14 0x80000000 +- MX51_PAD_EIM_DA15__EIM_DA15 0x80000000 +- MX51_PAD_EIM_A16__EIM_A16 0x80000000 +- MX51_PAD_EIM_A17__EIM_A17 0x80000000 +- MX51_PAD_EIM_A18__EIM_A18 0x80000000 +- MX51_PAD_EIM_A19__EIM_A19 0x80000000 +- MX51_PAD_EIM_A20__EIM_A20 0x80000000 +- MX51_PAD_EIM_A21__EIM_A21 0x80000000 +- MX51_PAD_EIM_A22__EIM_A22 0x80000000 +- MX51_PAD_EIM_A23__EIM_A23 0x80000000 +- MX51_PAD_EIM_A24__EIM_A24 0x80000000 +- MX51_PAD_EIM_A25__EIM_A25 0x80000000 +- MX51_PAD_EIM_A26__EIM_A26 0x80000000 +- MX51_PAD_EIM_A27__EIM_A27 0x80000000 +- MX51_PAD_EIM_D16__EIM_D16 0x80000000 +- MX51_PAD_EIM_D17__EIM_D17 0x80000000 +- MX51_PAD_EIM_D18__EIM_D18 0x80000000 +- MX51_PAD_EIM_D19__EIM_D19 0x80000000 +- MX51_PAD_EIM_D20__EIM_D20 0x80000000 +- MX51_PAD_EIM_D21__EIM_D21 0x80000000 +- MX51_PAD_EIM_D22__EIM_D22 0x80000000 +- MX51_PAD_EIM_D23__EIM_D23 0x80000000 +- MX51_PAD_EIM_D24__EIM_D24 0x80000000 +- MX51_PAD_EIM_D25__EIM_D25 0x80000000 +- MX51_PAD_EIM_D26__EIM_D26 0x80000000 +- MX51_PAD_EIM_D27__EIM_D27 0x80000000 +- MX51_PAD_EIM_D28__EIM_D28 0x80000000 +- MX51_PAD_EIM_D29__EIM_D29 0x80000000 +- MX51_PAD_EIM_D30__EIM_D30 0x80000000 +- MX51_PAD_EIM_D31__EIM_D31 0x80000000 +- MX51_PAD_EIM_OE__EIM_OE 0x80000000 +- MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000 +- MX51_PAD_EIM_LBA__EIM_LBA 0x80000000 +- MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 /* CS5 */ +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx51-eukrea-cpuimx51.dtsi b/scripts/dtc/include-prefixes/arm/imx51-eukrea-cpuimx51.dtsi +deleted file mode 100644 +index c2a929ba8ceb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx51-eukrea-cpuimx51.dtsi ++++ /dev/null +@@ -1,92 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Eukréa Electromatique +- */ +- +-#include "imx51.dtsi" +- +-/ { +- model = "Eukrea CPUIMX51"; +- compatible = "eukrea,cpuimx51", "fsl,imx51"; +- +- memory@90000000 { +- device_type = "memory"; +- reg = <0x90000000 0x10000000>; /* 256M */ +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pcf8563@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- +- tsc2007: tsc2007@49 { +- compatible = "ti,tsc2007"; +- gpios = <&gpio4 0 1>; +- interrupt-parent = <&gpio4>; +- interrupts = <0x0 0x8>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tsc2007_1>; +- reg = <0x49>; +- ti,x-plate-ohms = <180>; +- }; +-}; +- +-&iomuxc { +- imx51-eukrea { +- pinctrl_tsc2007_1: tsc2007grp-1 { +- fsl,pins = < +- MX51_PAD_GPIO_NAND__GPIO_NAND 0x1f5 +- MX51_PAD_NANDF_D8__GPIO4_0 0x1f5 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 +- MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 +- MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 +- MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 +- MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 +- MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 +- MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 +- MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 +- MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 +- MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 +- MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 +- MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 +- MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 +- MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 +- MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 +- MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 +- MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 +- MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX51_PAD_SD2_CMD__I2C1_SCL 0x400001ed +- MX51_PAD_SD2_CLK__I2C1_SDA 0x400001ed +- >; +- }; +- }; +-}; +- +-&nfc { +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-on-flash-bbt; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx51-eukrea-mbimxsd51-baseboard.dts b/scripts/dtc/include-prefixes/arm/imx51-eukrea-mbimxsd51-baseboard.dts +deleted file mode 100644 +index b6d931e96a8f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx51-eukrea-mbimxsd51-baseboard.dts ++++ /dev/null +@@ -1,274 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Eukréa Electromatique +- */ +- +-/dts-v1/; +-#include "imx51-eukrea-cpuimx51.dtsi" +-#include +- +-/ { +- model = "Eukrea CPUIMX51"; +- compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51"; +- +- clocks { +- clk24M: can_clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpiokeys_1>; +- +- button-1 { +- label = "BP1"; +- gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; +- linux,code = <256>; +- wakeup-source; +- linux,input-type = <1>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpioled>; +- +- led1 { +- label = "led1"; +- gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_can: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "CAN_RST"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <20000>; +- enable-active-high; +- }; +- }; +- +- sound { +- compatible = "eukrea,asoc-tlv320"; +- eukrea,model = "imx51-eukrea-tlv320aic23"; +- ssi-controller = <&ssi2>; +- fsl,mux-int-port = <2>; +- fsl,mux-ext-port = <3>; +- }; +- +- usbphy1: usbphy1 { +- compatible = "usb-nop-xceiv"; +- clocks = <&clks IMX5_CLK_USB_PHY_GATE>; +- clock-names = "main_clk"; +- clock-frequency = <19200000>; +- #phy-cells = <0>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1 &pinctrl_esdhc1_cd>; +- cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- can0: can@0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can>; +- compatible = "microchip,mcp2515"; +- reg = <0>; +- clocks = <&clk24M>; +- spi-max-frequency = <10000000>; +- interrupt-parent = <&gpio1>; +- interrupts = <1 IRQ_TYPE_EDGE_FALLING>; +- vdd-supply = <®_can>; +- }; +-}; +- +-&i2c1 { +- tlv320aic23: codec@1a { +- compatible = "ti,tlv320aic23"; +- reg = <0x1a>; +- }; +-}; +- +-&iomuxc { +- imx51-eukrea { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 +- MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 +- MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 +- MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 +- >; +- }; +- +- +- pinctrl_can: cangrp { +- fsl,pins = < +- MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x80000000 /* nReset */ +- MX51_PAD_GPIO1_1__GPIO1_1 0x80000000 /* IRQ */ +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 +- MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 +- MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 +- MX51_PAD_CSPI1_SS0__GPIO4_24 0x80000000 /* CS0 */ +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 +- MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 +- MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 +- MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 +- MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 +- MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 +- MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 +- MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 +- >; +- }; +- +- pinctrl_uart3_rtscts: uart3rtsctsgrp { +- fsl,pins = < +- MX51_PAD_KEY_COL4__UART3_RTS 0x1c5 +- MX51_PAD_KEY_COL5__UART3_CTS 0x1c5 +- >; +- }; +- +- pinctrl_backlight_1: backlightgrp-1 { +- fsl,pins = < +- MX51_PAD_DI1_D1_CS__GPIO3_4 0x1f5 +- >; +- }; +- +- pinctrl_esdhc1_cd: esdhc1_cd { +- fsl,pins = < +- MX51_PAD_GPIO1_0__GPIO1_0 0xd5 +- >; +- }; +- +- pinctrl_gpiokeys_1: gpiokeysgrp-1 { +- fsl,pins = < +- MX51_PAD_NANDF_D9__GPIO3_31 0x1f5 +- >; +- }; +- +- pinctrl_gpioled: gpioledgrp-1 { +- fsl,pins = < +- MX51_PAD_NANDF_D10__GPIO3_30 0x80000000 +- >; +- }; +- +- pinctrl_reg_lcd_3v3: reg_lcd_3v3 { +- fsl,pins = < +- MX51_PAD_CSI1_D9__GPIO3_13 0x1f5 +- >; +- }; +- +- pinctrl_usbh1: usbh1grp { +- fsl,pins = < +- MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 +- MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 +- MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 +- MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 +- MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 +- MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 +- MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 +- MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 +- MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 +- MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 +- MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 +- MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 +- >; +- }; +- +- pinctrl_usbh1_vbus: usbh1-vbusgrp { +- fsl,pins = < +- MX51_PAD_EIM_CS3__GPIO2_28 0x1f5 +- >; +- }; +- }; +-}; +- +-&ssi2 { +- codec-handle = <&tlv320aic23>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbh1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1>; +- fsl,usbphy = <&usbphy1>; +- dr_mode = "host"; +- phy_type = "ulpi"; +- status = "okay"; +-}; +- +-&usbotg { +- dr_mode = "otg"; +- phy_type = "utmi_wide"; +- status = "okay"; +-}; +- +-&usbphy0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1_vbus>; +- reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx51-pinfunc.h b/scripts/dtc/include-prefixes/arm/imx51-pinfunc.h +deleted file mode 100644 +index 910e0ec50ef3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx51-pinfunc.h ++++ /dev/null +@@ -1,768 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __DTS_IMX51_PINFUNC_H +-#define __DTS_IMX51_PINFUNC_H +- +-/* +- * The pin function ID is a tuple of +- * +- */ +-#define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0 +-#define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0 +-#define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0 +-#define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0 +-#define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0 +-#define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0 +-#define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0 +-#define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0 +-#define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0 +-#define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0 +-#define MX51_PAD_EIM_D17__UART2_RXD 0x060 0x3f4 0x9ec 0x3 0x0 +-#define MX51_PAD_EIM_D17__UART3_CTS 0x060 0x3f4 0x000 0x4 0x0 +-#define MX51_PAD_EIM_D17__USBH2_DATA1 0x060 0x3f4 0x000 0x2 0x0 +-#define MX51_PAD_EIM_D18__AUD5_TXC 0x064 0x3f8 0x8e4 0x7 0x0 +-#define MX51_PAD_EIM_D18__EIM_D18 0x064 0x3f8 0x000 0x0 0x0 +-#define MX51_PAD_EIM_D18__GPIO2_2 0x064 0x3f8 0x000 0x1 0x0 +-#define MX51_PAD_EIM_D18__UART2_TXD 0x064 0x3f8 0x000 0x3 0x0 +-#define MX51_PAD_EIM_D18__UART3_RTS 0x064 0x3f8 0x9f0 0x4 0x1 +-#define MX51_PAD_EIM_D18__USBH2_DATA2 0x064 0x3f8 0x000 0x2 0x0 +-#define MX51_PAD_EIM_D19__AUD4_RXC 0x068 0x3fc 0x000 0x5 0x0 +-#define MX51_PAD_EIM_D19__AUD5_TXFS 0x068 0x3fc 0x8e8 0x7 0x0 +-#define MX51_PAD_EIM_D19__EIM_D19 0x068 0x3fc 0x000 0x0 0x0 +-#define MX51_PAD_EIM_D19__GPIO2_3 0x068 0x3fc 0x000 0x1 0x0 +-#define MX51_PAD_EIM_D19__I2C1_SCL 0x068 0x3fc 0x9b0 0x4 0x0 +-#define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1 +-#define MX51_PAD_EIM_D19__USBH2_DATA3 0x068 0x3fc 0x000 0x2 0x0 +-#define MX51_PAD_EIM_D20__AUD4_TXD 0x06c 0x400 0x8c8 0x5 0x0 +-#define MX51_PAD_EIM_D20__EIM_D20 0x06c 0x400 0x000 0x0 0x0 +-#define MX51_PAD_EIM_D20__GPIO2_4 0x06c 0x400 0x000 0x1 0x0 +-#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB 0x06c 0x400 0x000 0x4 0x0 +-#define MX51_PAD_EIM_D20__USBH2_DATA4 0x06c 0x400 0x000 0x2 0x0 +-#define MX51_PAD_EIM_D21__AUD4_RXD 0x070 0x404 0x8c4 0x5 0x0 +-#define MX51_PAD_EIM_D21__EIM_D21 0x070 0x404 0x000 0x0 0x0 +-#define MX51_PAD_EIM_D21__GPIO2_5 0x070 0x404 0x000 0x1 0x0 +-#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB 0x070 0x404 0x000 0x3 0x0 +-#define MX51_PAD_EIM_D21__USBH2_DATA5 0x070 0x404 0x000 0x2 0x0 +-#define MX51_PAD_EIM_D22__AUD4_TXC 0x074 0x408 0x8cc 0x5 0x0 +-#define MX51_PAD_EIM_D22__EIM_D22 0x074 0x408 0x000 0x0 0x0 +-#define MX51_PAD_EIM_D22__GPIO2_6 0x074 0x408 0x000 0x1 0x0 +-#define MX51_PAD_EIM_D22__USBH2_DATA6 0x074 0x408 0x000 0x2 0x0 +-#define MX51_PAD_EIM_D23__AUD4_TXFS 0x078 0x40c 0x8d0 0x5 0x0 +-#define MX51_PAD_EIM_D23__EIM_D23 0x078 0x40c 0x000 0x0 0x0 +-#define MX51_PAD_EIM_D23__GPIO2_7 0x078 0x40c 0x000 0x1 0x0 +-#define MX51_PAD_EIM_D23__SPDIF_OUT1 0x078 0x40c 0x000 0x4 0x0 +-#define MX51_PAD_EIM_D23__USBH2_DATA7 0x078 0x40c 0x000 0x2 0x0 +-#define MX51_PAD_EIM_D24__AUD6_RXFS 0x07c 0x410 0x8f8 0x5 0x0 +-#define MX51_PAD_EIM_D24__EIM_D24 0x07c 0x410 0x000 0x0 0x0 +-#define MX51_PAD_EIM_D24__GPIO2_8 0x07c 0x410 0x000 0x1 0x0 +-#define MX51_PAD_EIM_D24__I2C2_SDA 0x07c 0x410 0x9bc 0x4 0x0 +-#define MX51_PAD_EIM_D24__UART3_CTS 0x07c 0x410 0x000 0x3 0x0 +-#define MX51_PAD_EIM_D24__USBOTG_DATA0 0x07c 0x410 0x000 0x2 0x0 +-#define MX51_PAD_EIM_D25__EIM_D25 0x080 0x414 0x000 0x0 0x0 +-#define MX51_PAD_EIM_D25__KEY_COL6 0x080 0x414 0x9c8 0x1 0x0 +-#define MX51_PAD_EIM_D25__UART2_CTS 0x080 0x414 0x000 0x4 0x0 +-#define MX51_PAD_EIM_D25__UART3_RXD 0x080 0x414 0x9f4 0x3 0x0 +-#define MX51_PAD_EIM_D25__USBOTG_DATA1 0x080 0x414 0x000 0x2 0x0 +-#define MX51_PAD_EIM_D26__EIM_D26 0x084 0x418 0x000 0x0 0x0 +-#define MX51_PAD_EIM_D26__KEY_COL7 0x084 0x418 0x9cc 0x1 0x0 +-#define MX51_PAD_EIM_D26__UART2_RTS 0x084 0x418 0x9e8 0x4 0x3 +-#define MX51_PAD_EIM_D26__UART3_TXD 0x084 0x418 0x000 0x3 0x0 +-#define MX51_PAD_EIM_D26__USBOTG_DATA2 0x084 0x418 0x000 0x2 0x0 +-#define MX51_PAD_EIM_D27__AUD6_RXC 0x088 0x41c 0x8f4 0x5 0x0 +-#define MX51_PAD_EIM_D27__EIM_D27 0x088 0x41c 0x000 0x0 0x0 +-#define MX51_PAD_EIM_D27__GPIO2_9 0x088 0x41c 0x000 0x1 0x0 +-#define MX51_PAD_EIM_D27__I2C2_SCL 0x088 0x41c 0x9b8 0x4 0x0 +-#define MX51_PAD_EIM_D27__UART3_RTS 0x088 0x41c 0x9f0 0x3 0x3 +-#define MX51_PAD_EIM_D27__USBOTG_DATA3 0x088 0x41c 0x000 0x2 0x0 +-#define MX51_PAD_EIM_D28__AUD6_TXD 0x08c 0x420 0x8f0 0x5 0x0 +-#define MX51_PAD_EIM_D28__EIM_D28 0x08c 0x420 0x000 0x0 0x0 +-#define MX51_PAD_EIM_D28__KEY_ROW4 0x08c 0x420 0x9d0 0x1 0x0 +-#define MX51_PAD_EIM_D28__USBOTG_DATA4 0x08c 0x420 0x000 0x2 0x0 +-#define MX51_PAD_EIM_D29__AUD6_RXD 0x090 0x424 0x8ec 0x5 0x0 +-#define MX51_PAD_EIM_D29__EIM_D29 0x090 0x424 0x000 0x0 0x0 +-#define MX51_PAD_EIM_D29__KEY_ROW5 0x090 0x424 0x9d4 0x1 0x0 +-#define MX51_PAD_EIM_D29__USBOTG_DATA5 0x090 0x424 0x000 0x2 0x0 +-#define MX51_PAD_EIM_D30__AUD6_TXC 0x094 0x428 0x8fc 0x5 0x0 +-#define MX51_PAD_EIM_D30__EIM_D30 0x094 0x428 0x000 0x0 0x0 +-#define MX51_PAD_EIM_D30__KEY_ROW6 0x094 0x428 0x9d8 0x1 0x0 +-#define MX51_PAD_EIM_D30__USBOTG_DATA6 0x094 0x428 0x000 0x2 0x0 +-#define MX51_PAD_EIM_D31__AUD6_TXFS 0x098 0x42c 0x900 0x5 0x0 +-#define MX51_PAD_EIM_D31__EIM_D31 0x098 0x42c 0x000 0x0 0x0 +-#define MX51_PAD_EIM_D31__KEY_ROW7 0x098 0x42c 0x9dc 0x1 0x0 +-#define MX51_PAD_EIM_D31__USBOTG_DATA7 0x098 0x42c 0x000 0x2 0x0 +-#define MX51_PAD_EIM_A16__EIM_A16 0x09c 0x430 0x000 0x0 0x0 +-#define MX51_PAD_EIM_A16__GPIO2_10 0x09c 0x430 0x000 0x1 0x0 +-#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 0x09c 0x430 0x000 0x7 0x0 +-#define MX51_PAD_EIM_A17__EIM_A17 0x0a0 0x434 0x000 0x0 0x0 +-#define MX51_PAD_EIM_A17__GPIO2_11 0x0a0 0x434 0x000 0x1 0x0 +-#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 0x0a0 0x434 0x000 0x7 0x0 +-#define MX51_PAD_EIM_A18__BOOT_LPB0 0x0a4 0x438 0x000 0x7 0x0 +-#define MX51_PAD_EIM_A18__EIM_A18 0x0a4 0x438 0x000 0x0 0x0 +-#define MX51_PAD_EIM_A18__GPIO2_12 0x0a4 0x438 0x000 0x1 0x0 +-#define MX51_PAD_EIM_A19__BOOT_LPB1 0x0a8 0x43c 0x000 0x7 0x0 +-#define MX51_PAD_EIM_A19__EIM_A19 0x0a8 0x43c 0x000 0x0 0x0 +-#define MX51_PAD_EIM_A19__GPIO2_13 0x0a8 0x43c 0x000 0x1 0x0 +-#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 0x0ac 0x440 0x000 0x7 0x0 +-#define MX51_PAD_EIM_A20__EIM_A20 0x0ac 0x440 0x000 0x0 0x0 +-#define MX51_PAD_EIM_A20__GPIO2_14 0x0ac 0x440 0x000 0x1 0x0 +-#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 0x0b0 0x444 0x000 0x7 0x0 +-#define MX51_PAD_EIM_A21__EIM_A21 0x0b0 0x444 0x000 0x0 0x0 +-#define MX51_PAD_EIM_A21__GPIO2_15 0x0b0 0x444 0x000 0x1 0x0 +-#define MX51_PAD_EIM_A22__EIM_A22 0x0b4 0x448 0x000 0x0 0x0 +-#define MX51_PAD_EIM_A22__GPIO2_16 0x0b4 0x448 0x000 0x1 0x0 +-#define MX51_PAD_EIM_A23__BOOT_HPN_EN 0x0b8 0x44c 0x000 0x7 0x0 +-#define MX51_PAD_EIM_A23__EIM_A23 0x0b8 0x44c 0x000 0x0 0x0 +-#define MX51_PAD_EIM_A23__GPIO2_17 0x0b8 0x44c 0x000 0x1 0x0 +-#define MX51_PAD_EIM_A24__EIM_A24 0x0bc 0x450 0x000 0x0 0x0 +-#define MX51_PAD_EIM_A24__GPIO2_18 0x0bc 0x450 0x000 0x1 0x0 +-#define MX51_PAD_EIM_A24__USBH2_CLK 0x0bc 0x450 0x000 0x2 0x0 +-#define MX51_PAD_EIM_A25__DISP1_PIN4 0x0c0 0x454 0x000 0x6 0x0 +-#define MX51_PAD_EIM_A25__EIM_A25 0x0c0 0x454 0x000 0x0 0x0 +-#define MX51_PAD_EIM_A25__GPIO2_19 0x0c0 0x454 0x000 0x1 0x0 +-#define MX51_PAD_EIM_A25__USBH2_DIR 0x0c0 0x454 0x000 0x2 0x0 +-#define MX51_PAD_EIM_A26__CSI1_DATA_EN 0x0c4 0x458 0x9a0 0x5 0x0 +-#define MX51_PAD_EIM_A26__DISP2_EXT_CLK 0x0c4 0x458 0x908 0x6 0x0 +-#define MX51_PAD_EIM_A26__EIM_A26 0x0c4 0x458 0x000 0x0 0x0 +-#define MX51_PAD_EIM_A26__GPIO2_20 0x0c4 0x458 0x000 0x1 0x0 +-#define MX51_PAD_EIM_A26__USBH2_STP 0x0c4 0x458 0x000 0x2 0x0 +-#define MX51_PAD_EIM_A27__CSI2_DATA_EN 0x0c8 0x45c 0x99c 0x5 0x0 +-#define MX51_PAD_EIM_A27__DISP1_PIN1 0x0c8 0x45c 0x9a4 0x6 0x0 +-#define MX51_PAD_EIM_A27__EIM_A27 0x0c8 0x45c 0x000 0x0 0x0 +-#define MX51_PAD_EIM_A27__GPIO2_21 0x0c8 0x45c 0x000 0x1 0x0 +-#define MX51_PAD_EIM_A27__USBH2_NXT 0x0c8 0x45c 0x000 0x2 0x0 +-#define MX51_PAD_EIM_EB0__EIM_EB0 0x0cc 0x460 0x000 0x0 0x0 +-#define MX51_PAD_EIM_EB1__EIM_EB1 0x0d0 0x464 0x000 0x0 0x0 +-#define MX51_PAD_EIM_EB2__AUD5_RXFS 0x0d4 0x468 0x8e0 0x6 0x0 +-#define MX51_PAD_EIM_EB2__CSI1_D2 0x0d4 0x468 0x000 0x5 0x0 +-#define MX51_PAD_EIM_EB2__EIM_EB2 0x0d4 0x468 0x000 0x0 0x0 +-#define MX51_PAD_EIM_EB2__FEC_MDIO 0x0d4 0x468 0x954 0x3 0x0 +-#define MX51_PAD_EIM_EB2__GPIO2_22 0x0d4 0x468 0x000 0x1 0x0 +-#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 0x0d4 0x468 0x000 0x7 0x0 +-#define MX51_PAD_EIM_EB3__AUD5_RXC 0x0d8 0x46c 0x8dc 0x6 0x0 +-#define MX51_PAD_EIM_EB3__CSI1_D3 0x0d8 0x46c 0x000 0x5 0x0 +-#define MX51_PAD_EIM_EB3__EIM_EB3 0x0d8 0x46c 0x000 0x0 0x0 +-#define MX51_PAD_EIM_EB3__FEC_RDATA1 0x0d8 0x46c 0x95c 0x3 0x0 +-#define MX51_PAD_EIM_EB3__GPIO2_23 0x0d8 0x46c 0x000 0x1 0x0 +-#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 0x0d8 0x46c 0x000 0x7 0x0 +-#define MX51_PAD_EIM_OE__EIM_OE 0x0dc 0x470 0x000 0x0 0x0 +-#define MX51_PAD_EIM_OE__GPIO2_24 0x0dc 0x470 0x000 0x1 0x0 +-#define MX51_PAD_EIM_CS0__EIM_CS0 0x0e0 0x474 0x000 0x0 0x0 +-#define MX51_PAD_EIM_CS0__GPIO2_25 0x0e0 0x474 0x000 0x1 0x0 +-#define MX51_PAD_EIM_CS1__EIM_CS1 0x0e4 0x478 0x000 0x0 0x0 +-#define MX51_PAD_EIM_CS1__GPIO2_26 0x0e4 0x478 0x000 0x1 0x0 +-#define MX51_PAD_EIM_CS2__AUD5_TXD 0x0e8 0x47c 0x8d8 0x6 0x1 +-#define MX51_PAD_EIM_CS2__CSI1_D4 0x0e8 0x47c 0x000 0x5 0x0 +-#define MX51_PAD_EIM_CS2__EIM_CS2 0x0e8 0x47c 0x000 0x0 0x0 +-#define MX51_PAD_EIM_CS2__FEC_RDATA2 0x0e8 0x47c 0x960 0x3 0x0 +-#define MX51_PAD_EIM_CS2__GPIO2_27 0x0e8 0x47c 0x000 0x1 0x0 +-#define MX51_PAD_EIM_CS2__USBOTG_STP 0x0e8 0x47c 0x000 0x2 0x0 +-#define MX51_PAD_EIM_CS3__AUD5_RXD 0x0ec 0x480 0x8d4 0x6 0x1 +-#define MX51_PAD_EIM_CS3__CSI1_D5 0x0ec 0x480 0x000 0x5 0x0 +-#define MX51_PAD_EIM_CS3__EIM_CS3 0x0ec 0x480 0x000 0x0 0x0 +-#define MX51_PAD_EIM_CS3__FEC_RDATA3 0x0ec 0x480 0x964 0x3 0x0 +-#define MX51_PAD_EIM_CS3__GPIO2_28 0x0ec 0x480 0x000 0x1 0x0 +-#define MX51_PAD_EIM_CS3__USBOTG_NXT 0x0ec 0x480 0x000 0x2 0x0 +-#define MX51_PAD_EIM_CS4__AUD5_TXC 0x0f0 0x484 0x8e4 0x6 0x1 +-#define MX51_PAD_EIM_CS4__CSI1_D6 0x0f0 0x484 0x000 0x5 0x0 +-#define MX51_PAD_EIM_CS4__EIM_CS4 0x0f0 0x484 0x000 0x0 0x0 +-#define MX51_PAD_EIM_CS4__FEC_RX_ER 0x0f0 0x484 0x970 0x3 0x0 +-#define MX51_PAD_EIM_CS4__GPIO2_29 0x0f0 0x484 0x000 0x1 0x0 +-#define MX51_PAD_EIM_CS4__USBOTG_CLK 0x0f0 0x484 0x000 0x2 0x0 +-#define MX51_PAD_EIM_CS5__AUD5_TXFS 0x0f4 0x488 0x8e8 0x6 0x1 +-#define MX51_PAD_EIM_CS5__CSI1_D7 0x0f4 0x488 0x000 0x5 0x0 +-#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK 0x0f4 0x488 0x904 0x4 0x0 +-#define MX51_PAD_EIM_CS5__EIM_CS5 0x0f4 0x488 0x000 0x0 0x0 +-#define MX51_PAD_EIM_CS5__FEC_CRS 0x0f4 0x488 0x950 0x3 0x0 +-#define MX51_PAD_EIM_CS5__GPIO2_30 0x0f4 0x488 0x000 0x1 0x0 +-#define MX51_PAD_EIM_CS5__USBOTG_DIR 0x0f4 0x488 0x000 0x2 0x0 +-#define MX51_PAD_EIM_DTACK__EIM_DTACK 0x0f8 0x48c 0x000 0x0 0x0 +-#define MX51_PAD_EIM_DTACK__GPIO2_31 0x0f8 0x48c 0x000 0x1 0x0 +-#define MX51_PAD_EIM_LBA__EIM_LBA 0x0fc 0x494 0x000 0x0 0x0 +-#define MX51_PAD_EIM_LBA__GPIO3_1 0x0fc 0x494 0x978 0x1 0x0 +-#define MX51_PAD_EIM_CRE__EIM_CRE 0x100 0x4a0 0x000 0x0 0x0 +-#define MX51_PAD_EIM_CRE__GPIO3_2 0x100 0x4a0 0x97c 0x1 0x0 +-#define MX51_PAD_DRAM_CS1__DRAM_CS1 0x104 0x4d0 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_WE_B__GPIO3_3 0x108 0x4e4 0x980 0x3 0x0 +-#define MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x108 0x4e4 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_WE_B__PATA_DIOW 0x108 0x4e4 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_WE_B__SD3_DATA0 0x108 0x4e4 0x93c 0x2 0x0 +-#define MX51_PAD_NANDF_RE_B__GPIO3_4 0x10c 0x4e8 0x984 0x3 0x0 +-#define MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x10c 0x4e8 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_RE_B__PATA_DIOR 0x10c 0x4e8 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_RE_B__SD3_DATA1 0x10c 0x4e8 0x940 0x2 0x0 +-#define MX51_PAD_NANDF_ALE__GPIO3_5 0x110 0x4ec 0x988 0x3 0x0 +-#define MX51_PAD_NANDF_ALE__NANDF_ALE 0x110 0x4ec 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x110 0x4ec 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_CLE__GPIO3_6 0x114 0x4f0 0x98c 0x3 0x0 +-#define MX51_PAD_NANDF_CLE__NANDF_CLE 0x114 0x4f0 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_CLE__PATA_RESET_B 0x114 0x4f0 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_WP_B__GPIO3_7 0x118 0x4f4 0x990 0x3 0x0 +-#define MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x118 0x4f4 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_WP_B__PATA_DMACK 0x118 0x4f4 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_WP_B__SD3_DATA2 0x118 0x4f4 0x944 0x2 0x0 +-#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 0x11c 0x4f8 0x930 0x5 0x0 +-#define MX51_PAD_NANDF_RB0__GPIO3_8 0x11c 0x4f8 0x994 0x3 0x0 +-#define MX51_PAD_NANDF_RB0__NANDF_RB0 0x11c 0x4f8 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_RB0__PATA_DMARQ 0x11c 0x4f8 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_RB0__SD3_DATA3 0x11c 0x4f8 0x948 0x2 0x0 +-#define MX51_PAD_NANDF_RB1__CSPI_MOSI 0x120 0x4fc 0x91c 0x6 0x0 +-#define MX51_PAD_NANDF_RB1__ECSPI2_RDY 0x120 0x4fc 0x000 0x2 0x0 +-#define MX51_PAD_NANDF_RB1__GPIO3_9 0x120 0x4fc 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_RB1__NANDF_RB1 0x120 0x4fc 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_RB1__PATA_IORDY 0x120 0x4fc 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_RB1__SD4_CMD 0x120 0x4fc 0x000 0x5 0x0 +-#define MX51_PAD_NANDF_RB2__DISP2_WAIT 0x124 0x500 0x9a8 0x5 0x0 +-#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x124 0x500 0x000 0x2 0x0 +-#define MX51_PAD_NANDF_RB2__FEC_COL 0x124 0x500 0x94c 0x1 0x0 +-#define MX51_PAD_NANDF_RB2__GPIO3_10 0x124 0x500 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_RB2__NANDF_RB2 0x124 0x500 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_RB2__USBH3_H3_DP 0x124 0x500 0x000 0x7 0x0 +-#define MX51_PAD_NANDF_RB2__USBH3_NXT 0x124 0x500 0xa20 0x6 0x0 +-#define MX51_PAD_NANDF_RB3__DISP1_WAIT 0x128 0x504 0x000 0x5 0x0 +-#define MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x128 0x504 0x000 0x2 0x0 +-#define MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x128 0x504 0x968 0x1 0x0 +-#define MX51_PAD_NANDF_RB3__GPIO3_11 0x128 0x504 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_RB3__NANDF_RB3 0x128 0x504 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_RB3__USBH3_CLK 0x128 0x504 0x9f8 0x6 0x0 +-#define MX51_PAD_NANDF_RB3__USBH3_H3_DM 0x128 0x504 0x000 0x7 0x0 +-#define MX51_PAD_GPIO_NAND__GPIO_NAND 0x12c 0x514 0x998 0x0 0x0 +-#define MX51_PAD_GPIO_NAND__PATA_INTRQ 0x12c 0x514 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_CS0__GPIO3_16 0x130 0x518 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_CS0__NANDF_CS0 0x130 0x518 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_CS1__GPIO3_17 0x134 0x51c 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_CS1__NANDF_CS1 0x134 0x51c 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_CS2__CSPI_SCLK 0x138 0x520 0x914 0x6 0x0 +-#define MX51_PAD_NANDF_CS2__FEC_TX_ER 0x138 0x520 0x000 0x2 0x0 +-#define MX51_PAD_NANDF_CS2__GPIO3_18 0x138 0x520 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_CS2__NANDF_CS2 0x138 0x520 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_CS2__PATA_CS_0 0x138 0x520 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_CS2__SD4_CLK 0x138 0x520 0x000 0x5 0x0 +-#define MX51_PAD_NANDF_CS2__USBH3_H1_DP 0x138 0x520 0x000 0x7 0x0 +-#define MX51_PAD_NANDF_CS3__FEC_MDC 0x13c 0x524 0x000 0x2 0x0 +-#define MX51_PAD_NANDF_CS3__GPIO3_19 0x13c 0x524 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_CS3__NANDF_CS3 0x13c 0x524 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_CS3__PATA_CS_1 0x13c 0x524 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_CS3__SD4_DAT0 0x13c 0x524 0x000 0x5 0x0 +-#define MX51_PAD_NANDF_CS3__USBH3_H1_DM 0x13c 0x524 0x000 0x7 0x0 +-#define MX51_PAD_NANDF_CS4__FEC_TDATA1 0x140 0x528 0x000 0x2 0x0 +-#define MX51_PAD_NANDF_CS4__GPIO3_20 0x140 0x528 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_CS4__NANDF_CS4 0x140 0x528 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_CS4__PATA_DA_0 0x140 0x528 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_CS4__SD4_DAT1 0x140 0x528 0x000 0x5 0x0 +-#define MX51_PAD_NANDF_CS4__USBH3_STP 0x140 0x528 0xa24 0x7 0x0 +-#define MX51_PAD_NANDF_CS5__FEC_TDATA2 0x144 0x52c 0x000 0x2 0x0 +-#define MX51_PAD_NANDF_CS5__GPIO3_21 0x144 0x52c 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_CS5__NANDF_CS5 0x144 0x52c 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_CS5__PATA_DA_1 0x144 0x52c 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_CS5__SD4_DAT2 0x144 0x52c 0x000 0x5 0x0 +-#define MX51_PAD_NANDF_CS5__USBH3_DIR 0x144 0x52c 0xa1c 0x7 0x0 +-#define MX51_PAD_NANDF_CS6__CSPI_SS3 0x148 0x530 0x928 0x7 0x0 +-#define MX51_PAD_NANDF_CS6__FEC_TDATA3 0x148 0x530 0x000 0x2 0x0 +-#define MX51_PAD_NANDF_CS6__GPIO3_22 0x148 0x530 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_CS6__NANDF_CS6 0x148 0x530 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_CS6__PATA_DA_2 0x148 0x530 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_CS6__SD4_DAT3 0x148 0x530 0x000 0x5 0x0 +-#define MX51_PAD_NANDF_CS7__FEC_TX_EN 0x14c 0x534 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_CS7__GPIO3_23 0x14c 0x534 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_CS7__NANDF_CS7 0x14c 0x534 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_CS7__SD3_CLK 0x14c 0x534 0x000 0x5 0x0 +-#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 0x150 0x538 0x000 0x2 0x0 +-#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x150 0x538 0x974 0x1 0x0 +-#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 0x150 0x538 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 0x150 0x538 0x938 0x0 0x0 +-#define MX51_PAD_NANDF_RDY_INT__SD3_CMD 0x150 0x538 0x000 0x5 0x0 +-#define MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x154 0x53c 0x000 0x2 0x0 +-#define MX51_PAD_NANDF_D15__GPIO3_25 0x154 0x53c 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_D15__NANDF_D15 0x154 0x53c 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_D15__PATA_DATA15 0x154 0x53c 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_D15__SD3_DAT7 0x154 0x53c 0x000 0x5 0x0 +-#define MX51_PAD_NANDF_D14__ECSPI2_SS3 0x158 0x540 0x934 0x2 0x0 +-#define MX51_PAD_NANDF_D14__GPIO3_26 0x158 0x540 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_D14__NANDF_D14 0x158 0x540 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_D14__PATA_DATA14 0x158 0x540 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_D14__SD3_DAT6 0x158 0x540 0x000 0x5 0x0 +-#define MX51_PAD_NANDF_D13__ECSPI2_SS2 0x15c 0x544 0x000 0x2 0x0 +-#define MX51_PAD_NANDF_D13__GPIO3_27 0x15c 0x544 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_D13__NANDF_D13 0x15c 0x544 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_D13__PATA_DATA13 0x15c 0x544 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_D13__SD3_DAT5 0x15c 0x544 0x000 0x5 0x0 +-#define MX51_PAD_NANDF_D12__ECSPI2_SS1 0x160 0x548 0x930 0x2 0x1 +-#define MX51_PAD_NANDF_D12__GPIO3_28 0x160 0x548 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_D12__NANDF_D12 0x160 0x548 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_D12__PATA_DATA12 0x160 0x548 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_D12__SD3_DAT4 0x160 0x548 0x000 0x5 0x0 +-#define MX51_PAD_NANDF_D11__FEC_RX_DV 0x164 0x54c 0x96c 0x2 0x0 +-#define MX51_PAD_NANDF_D11__GPIO3_29 0x164 0x54c 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_D11__NANDF_D11 0x164 0x54c 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_D11__PATA_DATA11 0x164 0x54c 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_D11__SD3_DATA3 0x164 0x54c 0x948 0x5 0x1 +-#define MX51_PAD_NANDF_D10__GPIO3_30 0x168 0x550 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_D10__NANDF_D10 0x168 0x550 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_D10__PATA_DATA10 0x168 0x550 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_D10__SD3_DATA2 0x168 0x550 0x944 0x5 0x1 +-#define MX51_PAD_NANDF_D9__FEC_RDATA0 0x16c 0x554 0x958 0x2 0x0 +-#define MX51_PAD_NANDF_D9__GPIO3_31 0x16c 0x554 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_D9__NANDF_D9 0x16c 0x554 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_D9__PATA_DATA9 0x16c 0x554 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_D9__SD3_DATA1 0x16c 0x554 0x940 0x5 0x1 +-#define MX51_PAD_NANDF_D8__FEC_TDATA0 0x170 0x558 0x000 0x2 0x0 +-#define MX51_PAD_NANDF_D8__GPIO4_0 0x170 0x558 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_D8__NANDF_D8 0x170 0x558 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_D8__PATA_DATA8 0x170 0x558 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_D8__SD3_DATA0 0x170 0x558 0x93c 0x5 0x1 +-#define MX51_PAD_NANDF_D7__GPIO4_1 0x174 0x55c 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_D7__NANDF_D7 0x174 0x55c 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_D7__PATA_DATA7 0x174 0x55c 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_D7__USBH3_DATA0 0x174 0x55c 0x9fc 0x5 0x0 +-#define MX51_PAD_NANDF_D6__GPIO4_2 0x178 0x560 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_D6__NANDF_D6 0x178 0x560 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_D6__PATA_DATA6 0x178 0x560 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_D6__SD4_LCTL 0x178 0x560 0x000 0x2 0x0 +-#define MX51_PAD_NANDF_D6__USBH3_DATA1 0x178 0x560 0xa00 0x5 0x0 +-#define MX51_PAD_NANDF_D5__GPIO4_3 0x17c 0x564 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_D5__NANDF_D5 0x17c 0x564 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_D5__PATA_DATA5 0x17c 0x564 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_D5__SD4_WP 0x17c 0x564 0x000 0x2 0x0 +-#define MX51_PAD_NANDF_D5__USBH3_DATA2 0x17c 0x564 0xa04 0x5 0x0 +-#define MX51_PAD_NANDF_D4__GPIO4_4 0x180 0x568 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_D4__NANDF_D4 0x180 0x568 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_D4__PATA_DATA4 0x180 0x568 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_D4__SD4_CD 0x180 0x568 0x000 0x2 0x0 +-#define MX51_PAD_NANDF_D4__USBH3_DATA3 0x180 0x568 0xa08 0x5 0x0 +-#define MX51_PAD_NANDF_D3__GPIO4_5 0x184 0x56c 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_D3__NANDF_D3 0x184 0x56c 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_D3__PATA_DATA3 0x184 0x56c 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_D3__SD4_DAT4 0x184 0x56c 0x000 0x2 0x0 +-#define MX51_PAD_NANDF_D3__USBH3_DATA4 0x184 0x56c 0xa0c 0x5 0x0 +-#define MX51_PAD_NANDF_D2__GPIO4_6 0x188 0x570 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_D2__NANDF_D2 0x188 0x570 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_D2__PATA_DATA2 0x188 0x570 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_D2__SD4_DAT5 0x188 0x570 0x000 0x2 0x0 +-#define MX51_PAD_NANDF_D2__USBH3_DATA5 0x188 0x570 0xa10 0x5 0x0 +-#define MX51_PAD_NANDF_D1__GPIO4_7 0x18c 0x574 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_D1__NANDF_D1 0x18c 0x574 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_D1__PATA_DATA1 0x18c 0x574 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_D1__SD4_DAT6 0x18c 0x574 0x000 0x2 0x0 +-#define MX51_PAD_NANDF_D1__USBH3_DATA6 0x18c 0x574 0xa14 0x5 0x0 +-#define MX51_PAD_NANDF_D0__GPIO4_8 0x190 0x578 0x000 0x3 0x0 +-#define MX51_PAD_NANDF_D0__NANDF_D0 0x190 0x578 0x000 0x0 0x0 +-#define MX51_PAD_NANDF_D0__PATA_DATA0 0x190 0x578 0x000 0x1 0x0 +-#define MX51_PAD_NANDF_D0__SD4_DAT7 0x190 0x578 0x000 0x2 0x0 +-#define MX51_PAD_NANDF_D0__USBH3_DATA7 0x190 0x578 0xa18 0x5 0x0 +-#define MX51_PAD_CSI1_D8__CSI1_D8 0x194 0x57c 0x000 0x0 0x0 +-#define MX51_PAD_CSI1_D8__GPIO3_12 0x194 0x57c 0x998 0x3 0x1 +-#define MX51_PAD_CSI1_D9__CSI1_D9 0x198 0x580 0x000 0x0 0x0 +-#define MX51_PAD_CSI1_D9__GPIO3_13 0x198 0x580 0x000 0x3 0x0 +-#define MX51_PAD_CSI1_D10__CSI1_D10 0x19c 0x584 0x000 0x0 0x0 +-#define MX51_PAD_CSI1_D11__CSI1_D11 0x1a0 0x588 0x000 0x0 0x0 +-#define MX51_PAD_CSI1_D12__CSI1_D12 0x1a4 0x58c 0x000 0x0 0x0 +-#define MX51_PAD_CSI1_D13__CSI1_D13 0x1a8 0x590 0x000 0x0 0x0 +-#define MX51_PAD_CSI1_D14__CSI1_D14 0x1ac 0x594 0x000 0x0 0x0 +-#define MX51_PAD_CSI1_D15__CSI1_D15 0x1b0 0x598 0x000 0x0 0x0 +-#define MX51_PAD_CSI1_D16__CSI1_D16 0x1b4 0x59c 0x000 0x0 0x0 +-#define MX51_PAD_CSI1_D17__CSI1_D17 0x1b8 0x5a0 0x000 0x0 0x0 +-#define MX51_PAD_CSI1_D18__CSI1_D18 0x1bc 0x5a4 0x000 0x0 0x0 +-#define MX51_PAD_CSI1_D19__CSI1_D19 0x1c0 0x5a8 0x000 0x0 0x0 +-#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 0x1c4 0x5ac 0x000 0x0 0x0 +-#define MX51_PAD_CSI1_VSYNC__GPIO3_14 0x1c4 0x5ac 0x000 0x3 0x0 +-#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 0x1c8 0x5b0 0x000 0x0 0x0 +-#define MX51_PAD_CSI1_HSYNC__GPIO3_15 0x1c8 0x5b0 0x000 0x3 0x0 +-#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 0x000 0x5b4 0x000 0x0 0x0 +-#define MX51_PAD_CSI1_MCLK__CSI1_MCLK 0x000 0x5b8 0x000 0x0 0x0 +-#define MX51_PAD_CSI2_D12__CSI2_D12 0x1cc 0x5bc 0x000 0x0 0x0 +-#define MX51_PAD_CSI2_D12__GPIO4_9 0x1cc 0x5bc 0x000 0x3 0x0 +-#define MX51_PAD_CSI2_D13__CSI2_D13 0x1d0 0x5c0 0x000 0x0 0x0 +-#define MX51_PAD_CSI2_D13__GPIO4_10 0x1d0 0x5c0 0x000 0x3 0x0 +-#define MX51_PAD_CSI2_D14__CSI2_D14 0x1d4 0x5c4 0x000 0x0 0x0 +-#define MX51_PAD_CSI2_D15__CSI2_D15 0x1d8 0x5c8 0x000 0x0 0x0 +-#define MX51_PAD_CSI2_D16__CSI2_D16 0x1dc 0x5cc 0x000 0x0 0x0 +-#define MX51_PAD_CSI2_D17__CSI2_D17 0x1e0 0x5d0 0x000 0x0 0x0 +-#define MX51_PAD_CSI2_D18__CSI2_D18 0x1e4 0x5d4 0x000 0x0 0x0 +-#define MX51_PAD_CSI2_D18__GPIO4_11 0x1e4 0x5d4 0x000 0x3 0x0 +-#define MX51_PAD_CSI2_D19__CSI2_D19 0x1e8 0x5d8 0x000 0x0 0x0 +-#define MX51_PAD_CSI2_D19__GPIO4_12 0x1e8 0x5d8 0x000 0x3 0x0 +-#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 0x1ec 0x5dc 0x000 0x0 0x0 +-#define MX51_PAD_CSI2_VSYNC__GPIO4_13 0x1ec 0x5dc 0x000 0x3 0x0 +-#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 0x1f0 0x5e0 0x000 0x0 0x0 +-#define MX51_PAD_CSI2_HSYNC__GPIO4_14 0x1f0 0x5e0 0x000 0x3 0x0 +-#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 0x1f4 0x5e4 0x000 0x0 0x0 +-#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x1f4 0x5e4 0x000 0x3 0x0 +-#define MX51_PAD_I2C1_CLK__GPIO4_16 0x1f8 0x5e8 0x000 0x3 0x0 +-#define MX51_PAD_I2C1_CLK__I2C1_CLK 0x1f8 0x5e8 0x000 0x0 0x0 +-#define MX51_PAD_I2C1_DAT__GPIO4_17 0x1fc 0x5ec 0x000 0x3 0x0 +-#define MX51_PAD_I2C1_DAT__I2C1_DAT 0x1fc 0x5ec 0x000 0x0 0x0 +-#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x200 0x5f0 0x000 0x0 0x0 +-#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 0x200 0x5f0 0x000 0x3 0x0 +-#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x204 0x5f4 0x000 0x0 0x0 +-#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x204 0x5f4 0x000 0x3 0x0 +-#define MX51_PAD_AUD3_BB_RXD__UART3_RXD 0x204 0x5f4 0x9f4 0x1 0x2 +-#define MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x208 0x5f8 0x000 0x0 0x0 +-#define MX51_PAD_AUD3_BB_CK__GPIO4_20 0x208 0x5f8 0x000 0x3 0x0 +-#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x20c 0x5fc 0x000 0x0 0x0 +-#define MX51_PAD_AUD3_BB_FS__GPIO4_21 0x20c 0x5fc 0x000 0x3 0x0 +-#define MX51_PAD_AUD3_BB_FS__UART3_TXD 0x20c 0x5fc 0x000 0x1 0x0 +-#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x210 0x600 0x000 0x0 0x0 +-#define MX51_PAD_CSPI1_MOSI__GPIO4_22 0x210 0x600 0x000 0x3 0x0 +-#define MX51_PAD_CSPI1_MOSI__I2C1_SDA 0x210 0x600 0x9b4 0x1 0x1 +-#define MX51_PAD_CSPI1_MISO__AUD4_RXD 0x214 0x604 0x8c4 0x1 0x1 +-#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x214 0x604 0x000 0x0 0x0 +-#define MX51_PAD_CSPI1_MISO__GPIO4_23 0x214 0x604 0x000 0x3 0x0 +-#define MX51_PAD_CSPI1_SS0__AUD4_TXC 0x218 0x608 0x8cc 0x1 0x1 +-#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 0x218 0x608 0x000 0x0 0x0 +-#define MX51_PAD_CSPI1_SS0__GPIO4_24 0x218 0x608 0x000 0x3 0x0 +-#define MX51_PAD_CSPI1_SS1__AUD4_TXD 0x21c 0x60c 0x8c8 0x1 0x1 +-#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 0x21c 0x60c 0x000 0x0 0x0 +-#define MX51_PAD_CSPI1_SS1__GPIO4_25 0x21c 0x60c 0x000 0x3 0x0 +-#define MX51_PAD_CSPI1_RDY__AUD4_TXFS 0x220 0x610 0x8d0 0x1 0x1 +-#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY 0x220 0x610 0x000 0x0 0x0 +-#define MX51_PAD_CSPI1_RDY__GPIO4_26 0x220 0x610 0x000 0x3 0x0 +-#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x224 0x614 0x000 0x0 0x0 +-#define MX51_PAD_CSPI1_SCLK__GPIO4_27 0x224 0x614 0x000 0x3 0x0 +-#define MX51_PAD_CSPI1_SCLK__I2C1_SCL 0x224 0x614 0x9b0 0x1 0x1 +-#define MX51_PAD_UART1_RXD__GPIO4_28 0x228 0x618 0x000 0x3 0x0 +-#define MX51_PAD_UART1_RXD__UART1_RXD 0x228 0x618 0x9e4 0x0 0x0 +-#define MX51_PAD_UART1_TXD__GPIO4_29 0x22c 0x61c 0x000 0x3 0x0 +-#define MX51_PAD_UART1_TXD__PWM2_PWMO 0x22c 0x61c 0x000 0x1 0x0 +-#define MX51_PAD_UART1_TXD__UART1_TXD 0x22c 0x61c 0x000 0x0 0x0 +-#define MX51_PAD_UART1_RTS__GPIO4_30 0x230 0x620 0x000 0x3 0x0 +-#define MX51_PAD_UART1_RTS__UART1_RTS 0x230 0x620 0x9e0 0x0 0x0 +-#define MX51_PAD_UART1_CTS__GPIO4_31 0x234 0x624 0x000 0x3 0x0 +-#define MX51_PAD_UART1_CTS__UART1_CTS 0x234 0x624 0x000 0x0 0x0 +-#define MX51_PAD_UART2_RXD__FIRI_TXD 0x238 0x628 0x000 0x1 0x0 +-#define MX51_PAD_UART2_RXD__GPIO1_20 0x238 0x628 0x000 0x3 0x0 +-#define MX51_PAD_UART2_RXD__UART2_RXD 0x238 0x628 0x9ec 0x0 0x2 +-#define MX51_PAD_UART2_TXD__FIRI_RXD 0x23c 0x62c 0x000 0x1 0x0 +-#define MX51_PAD_UART2_TXD__GPIO1_21 0x23c 0x62c 0x000 0x3 0x0 +-#define MX51_PAD_UART2_TXD__UART2_TXD 0x23c 0x62c 0x000 0x0 0x0 +-#define MX51_PAD_UART3_RXD__CSI1_D0 0x240 0x630 0x000 0x2 0x0 +-#define MX51_PAD_UART3_RXD__GPIO1_22 0x240 0x630 0x000 0x3 0x0 +-#define MX51_PAD_UART3_RXD__UART1_DTR 0x240 0x630 0x000 0x0 0x0 +-#define MX51_PAD_UART3_RXD__UART3_RXD 0x240 0x630 0x9f4 0x1 0x4 +-#define MX51_PAD_UART3_TXD__CSI1_D1 0x244 0x634 0x000 0x2 0x0 +-#define MX51_PAD_UART3_TXD__GPIO1_23 0x244 0x634 0x000 0x3 0x0 +-#define MX51_PAD_UART3_TXD__UART1_DSR 0x244 0x634 0x000 0x0 0x0 +-#define MX51_PAD_UART3_TXD__UART3_TXD 0x244 0x634 0x000 0x1 0x0 +-#define MX51_PAD_OWIRE_LINE__GPIO1_24 0x248 0x638 0x000 0x3 0x0 +-#define MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x248 0x638 0x000 0x0 0x0 +-#define MX51_PAD_OWIRE_LINE__SPDIF_OUT 0x248 0x638 0x000 0x6 0x0 +-#define MX51_PAD_KEY_ROW0__KEY_ROW0 0x24c 0x63c 0x000 0x0 0x0 +-#define MX51_PAD_KEY_ROW1__KEY_ROW1 0x250 0x640 0x000 0x0 0x0 +-#define MX51_PAD_KEY_ROW2__KEY_ROW2 0x254 0x644 0x000 0x0 0x0 +-#define MX51_PAD_KEY_ROW3__KEY_ROW3 0x258 0x648 0x000 0x0 0x0 +-#define MX51_PAD_KEY_COL0__KEY_COL0 0x25c 0x64c 0x000 0x0 0x0 +-#define MX51_PAD_KEY_COL0__PLL1_BYP 0x25c 0x64c 0x90c 0x7 0x0 +-#define MX51_PAD_KEY_COL1__KEY_COL1 0x260 0x650 0x000 0x0 0x0 +-#define MX51_PAD_KEY_COL1__PLL2_BYP 0x260 0x650 0x910 0x7 0x0 +-#define MX51_PAD_KEY_COL2__KEY_COL2 0x264 0x654 0x000 0x0 0x0 +-#define MX51_PAD_KEY_COL2__PLL3_BYP 0x264 0x654 0x000 0x7 0x0 +-#define MX51_PAD_KEY_COL3__KEY_COL3 0x268 0x658 0x000 0x0 0x0 +-#define MX51_PAD_KEY_COL4__I2C2_SCL 0x26c 0x65c 0x9b8 0x3 0x1 +-#define MX51_PAD_KEY_COL4__KEY_COL4 0x26c 0x65c 0x000 0x0 0x0 +-#define MX51_PAD_KEY_COL4__SPDIF_OUT1 0x26c 0x65c 0x000 0x6 0x0 +-#define MX51_PAD_KEY_COL4__UART1_RI 0x26c 0x65c 0x000 0x1 0x0 +-#define MX51_PAD_KEY_COL4__UART3_RTS 0x26c 0x65c 0x9f0 0x2 0x4 +-#define MX51_PAD_KEY_COL5__I2C2_SDA 0x270 0x660 0x9bc 0x3 0x1 +-#define MX51_PAD_KEY_COL5__KEY_COL5 0x270 0x660 0x000 0x0 0x0 +-#define MX51_PAD_KEY_COL5__UART1_DCD 0x270 0x660 0x000 0x1 0x0 +-#define MX51_PAD_KEY_COL5__UART3_CTS 0x270 0x660 0x000 0x2 0x0 +-#define MX51_PAD_USBH1_CLK__CSPI_SCLK 0x278 0x678 0x914 0x1 0x1 +-#define MX51_PAD_USBH1_CLK__GPIO1_25 0x278 0x678 0x000 0x2 0x0 +-#define MX51_PAD_USBH1_CLK__I2C2_SCL 0x278 0x678 0x9b8 0x5 0x2 +-#define MX51_PAD_USBH1_CLK__USBH1_CLK 0x278 0x678 0x000 0x0 0x0 +-#define MX51_PAD_USBH1_DIR__CSPI_MOSI 0x27c 0x67c 0x91c 0x1 0x1 +-#define MX51_PAD_USBH1_DIR__GPIO1_26 0x27c 0x67c 0x000 0x2 0x0 +-#define MX51_PAD_USBH1_DIR__I2C2_SDA 0x27c 0x67c 0x9bc 0x5 0x2 +-#define MX51_PAD_USBH1_DIR__USBH1_DIR 0x27c 0x67c 0x000 0x0 0x0 +-#define MX51_PAD_USBH1_STP__CSPI_RDY 0x280 0x680 0x000 0x1 0x0 +-#define MX51_PAD_USBH1_STP__GPIO1_27 0x280 0x680 0x000 0x2 0x0 +-#define MX51_PAD_USBH1_STP__UART3_RXD 0x280 0x680 0x9f4 0x5 0x6 +-#define MX51_PAD_USBH1_STP__USBH1_STP 0x280 0x680 0x000 0x0 0x0 +-#define MX51_PAD_USBH1_NXT__CSPI_MISO 0x284 0x684 0x918 0x1 0x0 +-#define MX51_PAD_USBH1_NXT__GPIO1_28 0x284 0x684 0x000 0x2 0x0 +-#define MX51_PAD_USBH1_NXT__UART3_TXD 0x284 0x684 0x000 0x5 0x0 +-#define MX51_PAD_USBH1_NXT__USBH1_NXT 0x284 0x684 0x000 0x0 0x0 +-#define MX51_PAD_USBH1_DATA0__GPIO1_11 0x288 0x688 0x000 0x2 0x0 +-#define MX51_PAD_USBH1_DATA0__UART2_CTS 0x288 0x688 0x000 0x1 0x0 +-#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x288 0x688 0x000 0x0 0x0 +-#define MX51_PAD_USBH1_DATA1__GPIO1_12 0x28c 0x68c 0x000 0x2 0x0 +-#define MX51_PAD_USBH1_DATA1__UART2_RXD 0x28c 0x68c 0x9ec 0x1 0x4 +-#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x28c 0x68c 0x000 0x0 0x0 +-#define MX51_PAD_USBH1_DATA2__GPIO1_13 0x290 0x690 0x000 0x2 0x0 +-#define MX51_PAD_USBH1_DATA2__UART2_TXD 0x290 0x690 0x000 0x1 0x0 +-#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x290 0x690 0x000 0x0 0x0 +-#define MX51_PAD_USBH1_DATA3__GPIO1_14 0x294 0x694 0x000 0x2 0x0 +-#define MX51_PAD_USBH1_DATA3__UART2_RTS 0x294 0x694 0x9e8 0x1 0x5 +-#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x294 0x694 0x000 0x0 0x0 +-#define MX51_PAD_USBH1_DATA4__CSPI_SS0 0x298 0x698 0x000 0x1 0x0 +-#define MX51_PAD_USBH1_DATA4__GPIO1_15 0x298 0x698 0x000 0x2 0x0 +-#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x298 0x698 0x000 0x0 0x0 +-#define MX51_PAD_USBH1_DATA5__CSPI_SS1 0x29c 0x69c 0x920 0x1 0x0 +-#define MX51_PAD_USBH1_DATA5__GPIO1_16 0x29c 0x69c 0x000 0x2 0x0 +-#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x29c 0x69c 0x000 0x0 0x0 +-#define MX51_PAD_USBH1_DATA6__CSPI_SS3 0x2a0 0x6a0 0x928 0x1 0x1 +-#define MX51_PAD_USBH1_DATA6__GPIO1_17 0x2a0 0x6a0 0x000 0x2 0x0 +-#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x2a0 0x6a0 0x000 0x0 0x0 +-#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 0x2a4 0x6a4 0x000 0x1 0x0 +-#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 0x2a4 0x6a4 0x934 0x5 0x1 +-#define MX51_PAD_USBH1_DATA7__GPIO1_18 0x2a4 0x6a4 0x000 0x2 0x0 +-#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x2a4 0x6a4 0x000 0x0 0x0 +-#define MX51_PAD_DI1_PIN11__DI1_PIN11 0x2a8 0x6a8 0x000 0x0 0x0 +-#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 0x2a8 0x6a8 0x000 0x7 0x0 +-#define MX51_PAD_DI1_PIN11__GPIO3_0 0x2a8 0x6a8 0x000 0x4 0x0 +-#define MX51_PAD_DI1_PIN12__DI1_PIN12 0x2ac 0x6ac 0x000 0x0 0x0 +-#define MX51_PAD_DI1_PIN12__GPIO3_1 0x2ac 0x6ac 0x978 0x4 0x1 +-#define MX51_PAD_DI1_PIN13__DI1_PIN13 0x2b0 0x6b0 0x000 0x0 0x0 +-#define MX51_PAD_DI1_PIN13__GPIO3_2 0x2b0 0x6b0 0x97c 0x4 0x1 +-#define MX51_PAD_DI1_D0_CS__DI1_D0_CS 0x2b4 0x6b4 0x000 0x0 0x0 +-#define MX51_PAD_DI1_D0_CS__GPIO3_3 0x2b4 0x6b4 0x980 0x4 0x1 +-#define MX51_PAD_DI1_D1_CS__DI1_D1_CS 0x2b8 0x6b8 0x000 0x0 0x0 +-#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 0x2b8 0x6b8 0x000 0x2 0x0 +-#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 0x2b8 0x6b8 0x000 0x3 0x0 +-#define MX51_PAD_DI1_D1_CS__GPIO3_4 0x2b8 0x6b8 0x984 0x4 0x1 +-#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 0x2bc 0x6bc 0x9a4 0x2 0x1 +-#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 0x2bc 0x6bc 0x9c4 0x0 0x0 +-#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 0x2bc 0x6bc 0x988 0x4 0x1 +-#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 0x2c0 0x6c0 0x000 0x3 0x0 +-#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 0x2c0 0x6c0 0x9c4 0x0 0x1 +-#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 0x2c0 0x6c0 0x98c 0x4 0x1 +-#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 0x2c4 0x6c4 0x000 0x2 0x0 +-#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 0x2c4 0x6c4 0x000 0x3 0x0 +-#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 0x2c4 0x6c4 0x000 0x0 0x0 +-#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 0x2c4 0x6c4 0x990 0x4 0x1 +-#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 0x2c8 0x6c8 0x000 0x2 0x0 +-#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 0x2c8 0x6c8 0x000 0x3 0x0 +-#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 0x2c8 0x6c8 0x000 0x0 0x0 +-#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 0x2c8 0x6c8 0x994 0x4 0x1 +-#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x2cc 0x6cc 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x2d0 0x6d0 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x2d4 0x6d4 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x2d8 0x6d8 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x2dc 0x6dc 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x2e0 0x6e0 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 0x2e4 0x6e4 0x000 0x7 0x0 +-#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x2e4 0x6e4 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 0x2e8 0x6e8 0x000 0x7 0x0 +-#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x2e8 0x6e8 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 0x2ec 0x6ec 0x000 0x7 0x0 +-#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x2ec 0x6ec 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 0x2f0 0x6f0 0x000 0x7 0x0 +-#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x2f0 0x6f0 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 0x2f4 0x6f4 0x000 0x7 0x0 +-#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x2f4 0x6f4 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 0x2f8 0x6f8 0x000 0x7 0x0 +-#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x2f8 0x6f8 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 0x2fc 0x6fc 0x000 0x7 0x0 +-#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x2fc 0x6fc 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 0x300 0x700 0x000 0x7 0x0 +-#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x300 0x700 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 0x304 0x704 0x000 0x7 0x0 +-#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x304 0x704 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 0x308 0x708 0x000 0x7 0x0 +-#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x308 0x708 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 0x30c 0x70c 0x000 0x7 0x0 +-#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x30c 0x70c 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 0x310 0x710 0x000 0x7 0x0 +-#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x310 0x710 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 0x314 0x714 0x000 0x7 0x0 +-#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x314 0x714 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 0x314 0x714 0x000 0x5 0x0 +-#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 0x314 0x714 0x000 0x4 0x0 +-#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 0x318 0x718 0x000 0x7 0x0 +-#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x318 0x718 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 0x318 0x718 0x000 0x5 0x0 +-#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 0x318 0x718 0x000 0x4 0x0 +-#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 0x31c 0x71c 0x000 0x7 0x0 +-#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x31c 0x71c 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 0x31c 0x71c 0x000 0x5 0x0 +-#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 0x31c 0x71c 0x000 0x4 0x0 +-#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 0x320 0x720 0x000 0x7 0x0 +-#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x320 0x720 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 0x320 0x720 0x000 0x5 0x0 +-#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 0x320 0x720 0x000 0x4 0x0 +-#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 0x324 0x724 0x000 0x7 0x0 +-#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x324 0x724 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS 0x324 0x724 0x000 0x6 0x0 +-#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 0x324 0x724 0x000 0x5 0x0 +-#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 0x328 0x728 0x000 0x7 0x0 +-#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x328 0x728 0x000 0x0 0x0 +-#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS 0x328 0x728 0x000 0x6 0x0 +-#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 0x328 0x728 0x000 0x5 0x0 +-#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS 0x328 0x728 0x000 0x4 0x0 +-#define MX51_PAD_DI1_PIN3__DI1_PIN3 0x32c 0x72c 0x000 0x0 0x0 +-#define MX51_PAD_DI1_PIN2__DI1_PIN2 0x330 0x734 0x000 0x0 0x0 +-#define MX51_PAD_DI_GP2__DISP1_SER_CLK 0x338 0x740 0x000 0x0 0x0 +-#define MX51_PAD_DI_GP2__DISP2_WAIT 0x338 0x740 0x9a8 0x2 0x1 +-#define MX51_PAD_DI_GP3__CSI1_DATA_EN 0x33c 0x744 0x9a0 0x3 0x1 +-#define MX51_PAD_DI_GP3__DISP1_SER_DIO 0x33c 0x744 0x9c0 0x0 0x0 +-#define MX51_PAD_DI_GP3__FEC_TX_ER 0x33c 0x744 0x000 0x2 0x0 +-#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN 0x340 0x748 0x99c 0x3 0x1 +-#define MX51_PAD_DI2_PIN4__DI2_PIN4 0x340 0x748 0x000 0x0 0x0 +-#define MX51_PAD_DI2_PIN4__FEC_CRS 0x340 0x748 0x950 0x2 0x1 +-#define MX51_PAD_DI2_PIN2__DI2_PIN2 0x344 0x74c 0x000 0x0 0x0 +-#define MX51_PAD_DI2_PIN2__FEC_MDC 0x344 0x74c 0x000 0x2 0x0 +-#define MX51_PAD_DI2_PIN3__DI2_PIN3 0x348 0x750 0x000 0x0 0x0 +-#define MX51_PAD_DI2_PIN3__FEC_MDIO 0x348 0x750 0x954 0x2 0x1 +-#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x34c 0x754 0x000 0x0 0x0 +-#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x34c 0x754 0x95c 0x2 0x1 +-#define MX51_PAD_DI_GP4__DI2_PIN15 0x350 0x758 0x000 0x4 0x0 +-#define MX51_PAD_DI_GP4__DISP1_SER_DIN 0x350 0x758 0x9c0 0x0 0x1 +-#define MX51_PAD_DI_GP4__DISP2_PIN1 0x350 0x758 0x000 0x3 0x0 +-#define MX51_PAD_DI_GP4__FEC_RDATA2 0x350 0x758 0x960 0x2 0x1 +-#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x354 0x75c 0x000 0x0 0x0 +-#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x354 0x75c 0x964 0x2 0x1 +-#define MX51_PAD_DISP2_DAT0__KEY_COL6 0x354 0x75c 0x9c8 0x4 0x1 +-#define MX51_PAD_DISP2_DAT0__UART3_RXD 0x354 0x75c 0x9f4 0x5 0x8 +-#define MX51_PAD_DISP2_DAT0__USBH3_CLK 0x354 0x75c 0x9f8 0x3 0x1 +-#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x358 0x760 0x000 0x0 0x0 +-#define MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x358 0x760 0x970 0x2 0x1 +-#define MX51_PAD_DISP2_DAT1__KEY_COL7 0x358 0x760 0x9cc 0x4 0x1 +-#define MX51_PAD_DISP2_DAT1__UART3_TXD 0x358 0x760 0x000 0x5 0x0 +-#define MX51_PAD_DISP2_DAT1__USBH3_DIR 0x358 0x760 0xa1c 0x3 0x1 +-#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x35c 0x764 0x000 0x0 0x0 +-#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x360 0x768 0x000 0x0 0x0 +-#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x364 0x76c 0x000 0x0 0x0 +-#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x368 0x770 0x000 0x0 0x0 +-#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x36c 0x774 0x000 0x0 0x0 +-#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x36c 0x774 0x000 0x2 0x0 +-#define MX51_PAD_DISP2_DAT6__GPIO1_19 0x36c 0x774 0x000 0x5 0x0 +-#define MX51_PAD_DISP2_DAT6__KEY_ROW4 0x36c 0x774 0x9d0 0x4 0x1 +-#define MX51_PAD_DISP2_DAT6__USBH3_STP 0x36c 0x774 0xa24 0x3 0x1 +-#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x370 0x778 0x000 0x0 0x0 +-#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x370 0x778 0x000 0x2 0x0 +-#define MX51_PAD_DISP2_DAT7__GPIO1_29 0x370 0x778 0x000 0x5 0x0 +-#define MX51_PAD_DISP2_DAT7__KEY_ROW5 0x370 0x778 0x9d4 0x4 0x1 +-#define MX51_PAD_DISP2_DAT7__USBH3_NXT 0x370 0x778 0xa20 0x3 0x1 +-#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x374 0x77c 0x000 0x0 0x0 +-#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x374 0x77c 0x000 0x2 0x0 +-#define MX51_PAD_DISP2_DAT8__GPIO1_30 0x374 0x77c 0x000 0x5 0x0 +-#define MX51_PAD_DISP2_DAT8__KEY_ROW6 0x374 0x77c 0x9d8 0x4 0x1 +-#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 0x374 0x77c 0x9fc 0x3 0x1 +-#define MX51_PAD_DISP2_DAT9__AUD6_RXC 0x378 0x780 0x8f4 0x4 0x1 +-#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x378 0x780 0x000 0x0 0x0 +-#define MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x378 0x780 0x000 0x2 0x0 +-#define MX51_PAD_DISP2_DAT9__GPIO1_31 0x378 0x780 0x000 0x5 0x0 +-#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 0x378 0x780 0xa00 0x3 0x1 +-#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x37c 0x784 0x000 0x0 0x0 +-#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS 0x37c 0x784 0x000 0x5 0x0 +-#define MX51_PAD_DISP2_DAT10__FEC_COL 0x37c 0x784 0x94c 0x2 0x1 +-#define MX51_PAD_DISP2_DAT10__KEY_ROW7 0x37c 0x784 0x9dc 0x4 0x1 +-#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 0x37c 0x784 0xa04 0x3 0x1 +-#define MX51_PAD_DISP2_DAT11__AUD6_TXD 0x380 0x788 0x8f0 0x4 0x1 +-#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x380 0x788 0x000 0x0 0x0 +-#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x380 0x788 0x968 0x2 0x1 +-#define MX51_PAD_DISP2_DAT11__GPIO1_10 0x380 0x788 0x000 0x7 0x0 +-#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 0x380 0x788 0xa08 0x3 0x1 +-#define MX51_PAD_DISP2_DAT12__AUD6_RXD 0x384 0x78c 0x8ec 0x4 0x1 +-#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x384 0x78c 0x000 0x0 0x0 +-#define MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x384 0x78c 0x96c 0x2 0x1 +-#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 0x384 0x78c 0xa0c 0x3 0x1 +-#define MX51_PAD_DISP2_DAT13__AUD6_TXC 0x388 0x790 0x8fc 0x4 0x1 +-#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x388 0x790 0x000 0x0 0x0 +-#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x388 0x790 0x974 0x2 0x1 +-#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 0x388 0x790 0xa10 0x3 0x1 +-#define MX51_PAD_DISP2_DAT14__AUD6_TXFS 0x38c 0x794 0x900 0x4 0x1 +-#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x38c 0x794 0x000 0x0 0x0 +-#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x38c 0x794 0x958 0x2 0x1 +-#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 0x38c 0x794 0xa14 0x3 0x1 +-#define MX51_PAD_DISP2_DAT15__AUD6_RXFS 0x390 0x798 0x8f8 0x4 0x1 +-#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS 0x390 0x798 0x000 0x5 0x0 +-#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x390 0x798 0x000 0x0 0x0 +-#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x390 0x798 0x000 0x2 0x0 +-#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 0x390 0x798 0xa18 0x3 0x1 +-#define MX51_PAD_SD1_CMD__AUD5_RXFS 0x394 0x79c 0x8e0 0x1 0x1 +-#define MX51_PAD_SD1_CMD__CSPI_MOSI 0x394 0x79c 0x91c 0x2 0x2 +-#define MX51_PAD_SD1_CMD__SD1_CMD 0x394 0x79c 0x000 0x0 0x0 +-#define MX51_PAD_SD1_CLK__AUD5_RXC 0x398 0x7a0 0x8dc 0x1 0x1 +-#define MX51_PAD_SD1_CLK__CSPI_SCLK 0x398 0x7a0 0x914 0x2 0x2 +-#define MX51_PAD_SD1_CLK__SD1_CLK 0x398 0x7a0 0x000 0x0 0x0 +-#define MX51_PAD_SD1_DATA0__AUD5_TXD 0x39c 0x7a4 0x8d8 0x1 0x2 +-#define MX51_PAD_SD1_DATA0__CSPI_MISO 0x39c 0x7a4 0x918 0x2 0x1 +-#define MX51_PAD_SD1_DATA0__SD1_DATA0 0x39c 0x7a4 0x000 0x0 0x0 +-#define MX51_PAD_EIM_DA0__EIM_DA0 0x01c 0x000 0x000 0x0 0x0 +-#define MX51_PAD_EIM_DA1__EIM_DA1 0x020 0x000 0x000 0x0 0x0 +-#define MX51_PAD_EIM_DA2__EIM_DA2 0x024 0x000 0x000 0x0 0x0 +-#define MX51_PAD_EIM_DA3__EIM_DA3 0x028 0x000 0x000 0x0 0x0 +-#define MX51_PAD_SD1_DATA1__AUD5_RXD 0x3a0 0x7a8 0x8d4 0x1 0x2 +-#define MX51_PAD_SD1_DATA1__SD1_DATA1 0x3a0 0x7a8 0x000 0x0 0x0 +-#define MX51_PAD_EIM_DA4__EIM_DA4 0x02c 0x000 0x000 0x0 0x0 +-#define MX51_PAD_EIM_DA5__EIM_DA5 0x030 0x000 0x000 0x0 0x0 +-#define MX51_PAD_EIM_DA6__EIM_DA6 0x034 0x000 0x000 0x0 0x0 +-#define MX51_PAD_EIM_DA7__EIM_DA7 0x038 0x000 0x000 0x0 0x0 +-#define MX51_PAD_SD1_DATA2__AUD5_TXC 0x3a4 0x7ac 0x8e4 0x1 0x2 +-#define MX51_PAD_SD1_DATA2__SD1_DATA2 0x3a4 0x7ac 0x000 0x0 0x0 +-#define MX51_PAD_EIM_DA10__EIM_DA10 0x044 0x000 0x000 0x0 0x0 +-#define MX51_PAD_EIM_DA11__EIM_DA11 0x048 0x000 0x000 0x0 0x0 +-#define MX51_PAD_EIM_DA8__EIM_DA8 0x03c 0x000 0x000 0x0 0x0 +-#define MX51_PAD_EIM_DA9__EIM_DA9 0x040 0x000 0x000 0x0 0x0 +-#define MX51_PAD_SD1_DATA3__AUD5_TXFS 0x3a8 0x7b0 0x8e8 0x1 0x2 +-#define MX51_PAD_SD1_DATA3__CSPI_SS1 0x3a8 0x7b0 0x920 0x2 0x1 +-#define MX51_PAD_SD1_DATA3__SD1_DATA3 0x3a8 0x7b0 0x000 0x0 0x0 +-#define MX51_PAD_GPIO1_0__CSPI_SS2 0x3ac 0x7b4 0x924 0x2 0x0 +-#define MX51_PAD_GPIO1_0__GPIO1_0 0x3ac 0x7b4 0x000 0x1 0x0 +-#define MX51_PAD_GPIO1_0__SD1_CD 0x3ac 0x7b4 0x000 0x0 0x0 +-#define MX51_PAD_GPIO1_1__CSPI_MISO 0x3b0 0x7b8 0x918 0x2 0x2 +-#define MX51_PAD_GPIO1_1__GPIO1_1 0x3b0 0x7b8 0x000 0x1 0x0 +-#define MX51_PAD_GPIO1_1__SD1_WP 0x3b0 0x7b8 0x000 0x0 0x0 +-#define MX51_PAD_EIM_DA12__EIM_DA12 0x04c 0x000 0x000 0x0 0x0 +-#define MX51_PAD_EIM_DA13__EIM_DA13 0x050 0x000 0x000 0x0 0x0 +-#define MX51_PAD_EIM_DA14__EIM_DA14 0x054 0x000 0x000 0x0 0x0 +-#define MX51_PAD_EIM_DA15__EIM_DA15 0x058 0x000 0x000 0x0 0x0 +-#define MX51_PAD_SD2_CMD__CSPI_MOSI 0x3b4 0x7bc 0x91c 0x2 0x3 +-#define MX51_PAD_SD2_CMD__I2C1_SCL 0x3b4 0x7bc 0x9b0 0x1 0x2 +-#define MX51_PAD_SD2_CMD__SD2_CMD 0x3b4 0x7bc 0x000 0x0 0x0 +-#define MX51_PAD_SD2_CLK__CSPI_SCLK 0x3b8 0x7c0 0x914 0x2 0x3 +-#define MX51_PAD_SD2_CLK__I2C1_SDA 0x3b8 0x7c0 0x9b4 0x1 0x2 +-#define MX51_PAD_SD2_CLK__SD2_CLK 0x3b8 0x7c0 0x000 0x0 0x0 +-#define MX51_PAD_SD2_DATA0__CSPI_MISO 0x3bc 0x7c4 0x918 0x2 0x3 +-#define MX51_PAD_SD2_DATA0__SD1_DAT4 0x3bc 0x7c4 0x000 0x1 0x0 +-#define MX51_PAD_SD2_DATA0__SD2_DATA0 0x3bc 0x7c4 0x000 0x0 0x0 +-#define MX51_PAD_SD2_DATA1__SD1_DAT5 0x3c0 0x7c8 0x000 0x1 0x0 +-#define MX51_PAD_SD2_DATA1__SD2_DATA1 0x3c0 0x7c8 0x000 0x0 0x0 +-#define MX51_PAD_SD2_DATA1__USBH3_H2_DP 0x3c0 0x7c8 0x000 0x2 0x0 +-#define MX51_PAD_SD2_DATA2__SD1_DAT6 0x3c4 0x7cc 0x000 0x1 0x0 +-#define MX51_PAD_SD2_DATA2__SD2_DATA2 0x3c4 0x7cc 0x000 0x0 0x0 +-#define MX51_PAD_SD2_DATA2__USBH3_H2_DM 0x3c4 0x7cc 0x000 0x2 0x0 +-#define MX51_PAD_SD2_DATA3__CSPI_SS2 0x3c8 0x7d0 0x924 0x2 0x1 +-#define MX51_PAD_SD2_DATA3__SD1_DAT7 0x3c8 0x7d0 0x000 0x1 0x0 +-#define MX51_PAD_SD2_DATA3__SD2_DATA3 0x3c8 0x7d0 0x000 0x0 0x0 +-#define MX51_PAD_GPIO1_2__CCM_OUT_2 0x3cc 0x7d4 0x000 0x5 0x0 +-#define MX51_PAD_GPIO1_2__GPIO1_2 0x3cc 0x7d4 0x000 0x0 0x0 +-#define MX51_PAD_GPIO1_2__I2C2_SCL 0x3cc 0x7d4 0x9b8 0x2 0x3 +-#define MX51_PAD_GPIO1_2__PLL1_BYP 0x3cc 0x7d4 0x90c 0x7 0x1 +-#define MX51_PAD_GPIO1_2__PWM1_PWMO 0x3cc 0x7d4 0x000 0x1 0x0 +-#define MX51_PAD_GPIO1_3__GPIO1_3 0x3d0 0x7d8 0x000 0x0 0x0 +-#define MX51_PAD_GPIO1_3__I2C2_SDA 0x3d0 0x7d8 0x9bc 0x2 0x3 +-#define MX51_PAD_GPIO1_3__PLL2_BYP 0x3d0 0x7d8 0x910 0x7 0x1 +-#define MX51_PAD_GPIO1_3__PWM2_PWMO 0x3d0 0x7d8 0x000 0x1 0x0 +-#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 0x3d4 0x7fc 0x000 0x0 0x0 +-#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 0x3d4 0x7fc 0x000 0x1 0x0 +-#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK 0x3d8 0x804 0x908 0x4 0x1 +-#define MX51_PAD_GPIO1_4__EIM_RDY 0x3d8 0x804 0x938 0x3 0x1 +-#define MX51_PAD_GPIO1_4__GPIO1_4 0x3d8 0x804 0x000 0x0 0x0 +-#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B 0x3d8 0x804 0x000 0x2 0x0 +-#define MX51_PAD_GPIO1_5__CSI2_MCLK 0x3dc 0x808 0x000 0x6 0x0 +-#define MX51_PAD_GPIO1_5__DISP2_PIN16 0x3dc 0x808 0x000 0x3 0x0 +-#define MX51_PAD_GPIO1_5__GPIO1_5 0x3dc 0x808 0x000 0x0 0x0 +-#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B 0x3dc 0x808 0x000 0x2 0x0 +-#define MX51_PAD_GPIO1_6__DISP2_PIN17 0x3e0 0x80c 0x000 0x4 0x0 +-#define MX51_PAD_GPIO1_6__GPIO1_6 0x3e0 0x80c 0x000 0x0 0x0 +-#define MX51_PAD_GPIO1_6__REF_EN_B 0x3e0 0x80c 0x000 0x3 0x0 +-#define MX51_PAD_GPIO1_7__CCM_OUT_0 0x3e4 0x810 0x000 0x3 0x0 +-#define MX51_PAD_GPIO1_7__GPIO1_7 0x3e4 0x810 0x000 0x0 0x0 +-#define MX51_PAD_GPIO1_7__SD2_WP 0x3e4 0x810 0x000 0x6 0x0 +-#define MX51_PAD_GPIO1_7__SPDIF_OUT1 0x3e4 0x810 0x000 0x2 0x0 +-#define MX51_PAD_GPIO1_8__CSI2_DATA_EN 0x3e8 0x814 0x99c 0x2 0x2 +-#define MX51_PAD_GPIO1_8__GPIO1_8 0x3e8 0x814 0x000 0x0 0x0 +-#define MX51_PAD_GPIO1_8__SD2_CD 0x3e8 0x814 0x000 0x6 0x0 +-#define MX51_PAD_GPIO1_8__USBH3_PWR 0x3e8 0x814 0x000 0x1 0x0 +-#define MX51_PAD_GPIO1_9__CCM_OUT_1 0x3ec 0x818 0x000 0x3 0x0 +-#define MX51_PAD_GPIO1_9__DISP2_D1_CS 0x3ec 0x818 0x000 0x2 0x0 +-#define MX51_PAD_GPIO1_9__DISP2_SER_CS 0x3ec 0x818 0x000 0x7 0x0 +-#define MX51_PAD_GPIO1_9__GPIO1_9 0x3ec 0x818 0x000 0x0 0x0 +-#define MX51_PAD_GPIO1_9__SD2_LCTL 0x3ec 0x818 0x000 0x6 0x0 +-#define MX51_PAD_GPIO1_9__USBH3_OC 0x3ec 0x818 0x000 0x1 0x0 +- +-#endif /* __DTS_IMX51_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm/imx51-ts4800.dts b/scripts/dtc/include-prefixes/arm/imx51-ts4800.dts +deleted file mode 100644 +index 6ecb83e7f336..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx51-ts4800.dts ++++ /dev/null +@@ -1,331 +0,0 @@ +-/* +- * Copyright 2015 Savoir-faire Linux +- * +- * This device tree is based on imx51-babbage.dts +- * +- * Licensed under the X11 license or the GPL v2 (or later) +- */ +- +-/dts-v1/; +-#include "imx51.dtsi" +- +-/ { +- model = "Technologic Systems TS-4800"; +- compatible = "technologic,imx51-ts4800", "fsl,imx51"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@90000000 { +- device_type = "memory"; +- reg = <0x90000000 0x10000000>; +- }; +- +- clocks { +- ckih1 { +- clock-frequency = <22579200>; +- }; +- +- ckih2 { +- clock-frequency = <24576000>; +- }; +- }; +- +- backlight_reg: regulator-backlight { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enable_lcd>; +- regulator-name = "enable_lcd_reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 78770>; +- brightness-levels = <0 150 200 255>; +- default-brightness-level = <1>; +- power-supply = <&backlight_reg>; +- }; +- +- display1: disp1 { +- compatible = "fsl,imx-parallel-display"; +- interface-pix-fmt = "rgb24"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd>; +- +- display-timings { +- 800x480p60 { +- native-mode; +- clock-frequency = <30066000>; +- hactive = <800>; +- vactive = <480>; +- hfront-porch = <50>; +- hback-porch = <70>; +- hsync-len = <50>; +- vback-porch = <0>; +- vfront-porch = <0>; +- vsync-len = <50>; +- }; +- }; +- +- port { +- display0_in: endpoint { +- remote-endpoint = <&ipu_di0_disp1>; +- }; +- }; +- }; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-mode = "mii"; +- phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <1>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- rtc: m41t00@68 { +- compatible = "st,m41t00"; +- reg = <0x68>; +- }; +-}; +- +-&ipu_di0_disp1 { +- remote-endpoint = <&display0_in>; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm_backlight>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&weim { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_weim>; +- status = "okay"; +- +- fpga@0 { +- compatible = "simple-bus"; +- fsl,weim-cs-timing = <0x0061008F 0x00000002 0x1c022000 +- 0x00000000 0x1c092480 0x00000000>; +- reg = <0 0x0000000 0x1d000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0 0x1d000>; +- +- syscon: syscon@10000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x10000 0x3d>; +- reg-io-width = <2>; +- +- wdt { +- compatible = "technologic,ts4800-wdt"; +- syscon = <&syscon 0xe>; +- }; +- }; +- +- touchscreen@12000 { +- compatible = "technologic,ts4800-ts"; +- reg = <0x12000 0x1000>; +- syscon = <&syscon 0x10 6>; +- }; +- +- fpga_irqc: fpga-irqc@15000 { +- compatible = "technologic,ts4800-irqc"; +- reg = <0x15000 0x1000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_interrupt_fpga>; +- interrupt-parent = <&gpio2>; +- interrupts= <9 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- can@1a000 { +- compatible = "technologic,sja1000"; +- reg = <0x1a000 0x100>; +- interrupt-parent = <&fpga_irqc>; +- interrupts = <1>; +- reg-io-width = <2>; +- nxp,tx-output-config = <0x06>; +- nxp,external-clock-frequency = <24000000>; +- }; +- }; +-}; +- +-&iomuxc { +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 +- MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 +- MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 +- MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ +- >; +- }; +- +- pinctrl_enable_lcd: enablelcdgrp { +- fsl,pins = < +- MX51_PAD_CSI2_D12__GPIO4_9 0x1c5 +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 +- MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 +- MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 +- MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 +- MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 +- MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 +- MX51_PAD_GPIO1_0__GPIO1_0 0x100 +- MX51_PAD_GPIO1_1__GPIO1_1 0x100 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 +- MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 +- MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 +- MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 +- MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 +- MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 +- MX51_PAD_DISP2_DAT10__FEC_COL 0x00000180 +- MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x00000180 +- MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x00002180 +- MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x00002004 +- MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 +- MX51_PAD_DI2_PIN2__FEC_MDC 0x00002004 +- MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x00002004 +- MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x00002004 +- MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x00002004 +- MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x00002004 +- MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x00002180 +- MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x000020a4 +- MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed +- MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed +- >; +- }; +- +- pinctrl_interrupt_fpga: fpgaicgrp { +- fsl,pins = < +- MX51_PAD_EIM_D27__GPIO2_9 0xe5 +- >; +- }; +- +- pinctrl_lcd: lcdgrp { +- fsl,pins = < +- MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 +- MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 +- MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 +- MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 +- MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 +- MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 +- MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 +- MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 +- MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 +- MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 +- MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 +- MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 +- MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 +- MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 +- MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 +- MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 +- MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 +- MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 +- MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 +- MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 +- MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 +- MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 +- MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 +- MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 +- MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 +- MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 +- MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 +- MX51_PAD_DI_GP4__DI2_PIN15 0x5 +- >; +- }; +- +- pinctrl_pwm_backlight: backlightgrp { +- fsl,pins = < +- MX51_PAD_GPIO1_2__PWM1_PWMO 0x80000000 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 +- MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 +- MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX51_PAD_EIM_D25__UART3_RXD 0x1c5 +- MX51_PAD_EIM_D26__UART3_TXD 0x1c5 +- >; +- }; +- +- pinctrl_weim: weimgrp { +- fsl,pins = < +- MX51_PAD_EIM_DTACK__EIM_DTACK 0x85 +- MX51_PAD_EIM_CS0__EIM_CS0 0x0 +- MX51_PAD_EIM_CS1__EIM_CS1 0x0 +- MX51_PAD_EIM_EB0__EIM_EB0 0x85 +- MX51_PAD_EIM_EB1__EIM_EB1 0x85 +- MX51_PAD_EIM_OE__EIM_OE 0x85 +- MX51_PAD_EIM_LBA__EIM_LBA 0x85 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx51-zii-rdu1.dts b/scripts/dtc/include-prefixes/arm/imx51-zii-rdu1.dts +deleted file mode 100644 +index ec8ca3ac2c1c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx51-zii-rdu1.dts ++++ /dev/null +@@ -1,894 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2017 Zodiac Inflight Innovations +- */ +- +-/dts-v1/; +-#include "imx51.dtsi" +-#include +- +-/ { +- model = "ZII RDU1 Board"; +- compatible = "zii,imx51-rdu1", "fsl,imx51"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- /* Will be filled by the bootloader */ +- memory@90000000 { +- device_type = "memory"; +- reg = <0x90000000 0>; +- }; +- +- aliases { +- mdio-gpio0 = &mdio_gpio; +- rtc0 = &ds1341; +- }; +- +- clk_26M_osc: 26M_osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +- +- clk_26M_osc_gate: 26M_gate { +- compatible = "gpio-gate-clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_clk26mhz>; +- clocks = <&clk_26M_osc>; +- #clock-cells = <0>; +- enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; +- }; +- +- clk_26M_usb: usbhost_gate { +- compatible = "gpio-gate-clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbgate26mhz>; +- clocks = <&clk_26M_osc_gate>; +- #clock-cells = <0>; +- enable-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; +- }; +- +- clk_26M_snd: snd_gate { +- compatible = "gpio-gate-clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sndgate26mhz>; +- clocks = <&clk_26M_osc_gate>; +- #clock-cells = <0>; +- enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; +- }; +- +- reg_5p0v_main: regulator-5p0v-main { +- compatible = "regulator-fixed"; +- regulator-name = "5V_MAIN"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- disp0 { +- compatible = "fsl,imx-parallel-display"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu_disp1>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- display_in: endpoint { +- remote-endpoint = <&ipu_di0_disp1>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +- +- panel { +- /* no compatible here, bootloader will patch in correct one */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_panel>; +- power-supply = <®_3p3v>; +- enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; +- status = "disabled"; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +- +- i2c_gpio: i2c-gpio { +- compatible = "i2c-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_swi2c>; +- gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>, /* sda */ +- <&gpio3 4 GPIO_ACTIVE_HIGH>; /* scl */ +- i2c-gpio,delay-us = <50>; +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&clk_26M_snd>; +- VDDA-supply = <&vdig_reg>; +- VDDIO-supply = <&vvideo_reg>; +- #sound-dai-cells = <0>; +- }; +- }; +- +- spi_gpio: spi-gpio { +- compatible = "spi-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpiospi0>; +- status = "okay"; +- +- gpio-sck = <&gpio4 15 GPIO_ACTIVE_HIGH>; +- gpio-mosi = <&gpio4 12 GPIO_ACTIVE_HIGH>; +- gpio-miso = <&gpio4 11 GPIO_ACTIVE_HIGH>; +- num-chipselects = <1>; +- cs-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; +- +- eeprom@0 { +- compatible = "eeprom-93xx46"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- spi-cs-high; +- data-size = <8>; +- }; +- }; +- +- mdio_gpio: mdio-gpio { +- compatible = "virtual,mdio-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_swmdio>; +- gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>, /* mdc */ +- <&gpio3 25 GPIO_ACTIVE_HIGH>; /* mdio */ +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch@0 { +- compatible = "marvell,mv88e6085"; +- reg = <0>; +- dsa,member = <0 0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "cpu"; +- ethernet = <&fec>; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +- +- port@1 { +- reg = <1>; +- label = "netaux"; +- }; +- +- port@3 { +- reg = <3>; +- label = "netright"; +- }; +- +- port@4 { +- reg = <4>; +- label = "netleft"; +- }; +- }; +- }; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "Front"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sound_codec>; +- simple-audio-card,frame-master = <&sound_codec>; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "Headphone Jack", "TPA6130A2 HPLEFT", +- "Headphone Jack", "TPA6130A2 HPRIGHT"; +- simple-audio-card,aux-devs = <&hpa1>; +- +- sound_cpu: simple-audio-card,cpu { +- sound-dai = <&ssi2>; +- }; +- +- sound_codec: simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- clocks = <&clk_26M_snd>; +- }; +- }; +- +- usbh1phy: usbphy1 { +- compatible = "usb-nop-xceiv"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1phy>; +- clocks = <&clk_26M_usb>; +- clock-names = "main_clk"; +- reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; +- vcc-supply = <&vusb_reg>; +- #phy-cells = <0>; +- }; +- +- usbh2phy: usbphy2 { +- compatible = "usb-nop-xceiv"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh2phy>; +- clocks = <&clk_26M_usb>; +- clock-names = "main_clk"; +- reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; +- vcc-supply = <&vusb_reg>; +- #phy-cells = <0>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +- +- ssi2 { +- fsl,audmux-port = <1>; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_SYN | +- IMX_AUDMUX_V2_PTCR_TFSEL(2) | +- IMX_AUDMUX_V2_PTCR_TCSEL(2) | +- IMX_AUDMUX_V2_PTCR_TFSDIR | +- IMX_AUDMUX_V2_PTCR_TCLKDIR) +- IMX_AUDMUX_V2_PDCR_RXDSEL(2) +- >; +- }; +- +- aud3 { +- fsl,audmux-port = <2>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN +- IMX_AUDMUX_V2_PDCR_RXDSEL(1) +- >; +- }; +-}; +- +-&cpu { +- cpu-supply = <&sw1_reg>; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, +- <&gpio4 25 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- pmic@0 { +- compatible = "fsl,mc13892"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- spi-max-frequency = <6000000>; +- spi-cs-high; +- reg = <0>; +- interrupt-parent = <&gpio1>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; +- fsl,mc13xxx-uses-adc; +- +- regulators { +- sw1_reg: sw1 { +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1375000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3_reg: sw3 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vpll_reg: vpll { +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdig_reg: vdig { +- regulator-min-microvolt = <1650000>; +- regulator-max-microvolt = <1650000>; +- regulator-boot-on; +- }; +- +- vsd_reg: vsd { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3150000>; +- }; +- +- vusb_reg: vusb { +- regulator-always-on; +- }; +- +- vusb2_reg: vusb2 { +- regulator-min-microvolt = <2400000>; +- regulator-max-microvolt = <2775000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vvideo_reg: vvideo { +- regulator-min-microvolt = <2775000>; +- regulator-max-microvolt = <2775000>; +- }; +- +- vaudio_reg: vaudio { +- regulator-min-microvolt = <2300000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- vcam_reg: vcam { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3150000>; +- regulator-always-on; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2900000>; +- regulator-always-on; +- }; +- }; +- +- leds { +- #address-cells = <1>; +- #size-cells = <0>; +- led-control = <0x0 0x0 0x3f83f8 0x0>; +- +- sysled0@3 { +- reg = <3>; +- label = "system:green:status"; +- linux,default-trigger = "default-on"; +- }; +- +- sysled1@4 { +- reg = <4>; +- label = "system:green:act"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- }; +- +- flash@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "atmel,at45db642d", "atmel,at45", "atmel,dataflash"; +- spi-max-frequency = <25000000>; +- reg = <1>; +- }; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- bus-width = <4>; +- no-1-8-v; +- non-removable; +- no-sdio; +- no-sd; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-mode = "mii"; +- phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; +- phy-supply = <&vgen3_reg>; +- status = "okay"; +-}; +- +-&gpio1 { +- gpio-line-names = "", "", "", "", +- "", "", "", "", +- "", "hp-amp-shutdown-b", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", ""; +- +- unused-sd3-wp-hog { +- /* +- * See pinctrl_esdhc1 below for more details on this +- */ +- gpio-hog; +- gpios = <1 GPIO_ACTIVE_HIGH>; +- output-high; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- hpa1: amp@60 { +- compatible = "ti,tpa6130a2"; +- reg = <0x60>; +- Vdd-supply = <®_3p3v>; +- sound-name-prefix = "TPA6130A2"; +- }; +- +- ds1341: rtc@68 { +- compatible = "dallas,ds1341"; +- reg = <0x68>; +- }; +- +- /* touch nodes default disabled, bootloader will enable the right one */ +- +- touchscreen@4b { +- compatible = "atmel,maxtouch"; +- reg = <0x4b>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ts>; +- interrupt-parent = <&gpio3>; +- interrupts = <12 IRQ_TYPE_LEVEL_LOW>; +- status = "disabled"; +- }; +- +- touchscreen@4c { +- compatible = "atmel,maxtouch"; +- reg = <0x4c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ts>; +- interrupt-parent = <&gpio3>; +- interrupts = <12 IRQ_TYPE_LEVEL_LOW>; +- status = "disabled"; +- }; +- +- touchscreen@20 { +- compatible = "syna,rmi4-i2c"; +- reg = <0x20>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ts>; +- interrupt-parent = <&gpio3>; +- interrupts = <12 IRQ_TYPE_LEVEL_LOW>; +- status = "disabled"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- rmi4-f01@1 { +- reg = <0x1>; +- syna,nosleep-mode = <2>; +- }; +- +- rmi4-f11@11 { +- reg = <0x11>; +- touchscreen-inverted-x; +- touchscreen-swapped-x-y; +- syna,sensor-type = <1>; +- }; +- }; +- +-}; +- +-&ipu_di0_disp1 { +- remote-endpoint = <&display_in>; +-}; +- +-&pmu { +- secure-reg-access; +-}; +- +-&ssi2 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +- +- rave-sp { +- compatible = "zii,rave-sp-rdu1"; +- current-speed = <38400>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- watchdog { +- compatible = "zii,rave-sp-watchdog"; +- }; +- +- backlight { +- compatible = "zii,rave-sp-backlight"; +- }; +- +- pwrbutton { +- compatible = "zii,rave-sp-pwrbutton"; +- }; +- +- eeprom@a3 { +- compatible = "zii,rave-sp-eeprom"; +- reg = <0xa3 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- zii,eeprom-name = "dds-eeprom"; +- }; +- +- eeprom@a4 { +- compatible = "zii,rave-sp-eeprom"; +- reg = <0xa4 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- zii,eeprom-name = "main-eeprom"; +- }; +- +- eeprom@ae { +- compatible = "zii,rave-sp-eeprom"; +- reg = <0xae 0x200>; +- zii,eeprom-name = "switch-eeprom"; +- /* +- * Not all RDU1s have this functionality, so we +- * rely on the bootloader to enable this +- */ +- status = "disabled"; +- }; +- }; +-}; +- +-&usbh1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1>; +- dr_mode = "host"; +- phy_type = "ulpi"; +- fsl,usbphy = <&usbh1phy>; +- disable-over-current; +- maximum-speed = "full-speed"; +- vbus-supply = <®_5p0v_main>; +- status = "okay"; +-}; +- +-&usbh2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh2>; +- dr_mode = "host"; +- phy_type = "ulpi"; +- fsl,usbphy = <&usbh2phy>; +- disable-over-current; +- vbus-supply = <®_5p0v_main>; +- status = "okay"; +-}; +- +-&usbphy0 { +- vcc-supply = <&vusb_reg>; +-}; +- +-&usbotg { +- dr_mode = "host"; +- disable-over-current; +- phy_type = "utmi_wide"; +- vbus-supply = <®_5p0v_main>; +- status = "okay"; +-}; +- +-&wdog1 { +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX51_PAD_GPIO1_9__GPIO1_9 0x5e +- >; +- }; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0xa5 +- MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x85 +- MX51_PAD_AUD3_BB_CK__AUD3_TXC 0xa5 +- MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x85 +- >; +- }; +- +- pinctrl_clk26mhz: clk26mhzgrp { +- fsl,pins = < +- MX51_PAD_DI1_PIN12__GPIO3_1 0x85 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 +- MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 +- MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 +- MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 +- MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 +- MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 +- MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 +- MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 +- MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 +- MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 +- /* +- * GPIO1_1 is not directly used by eSDHC1 in +- * any capacity, but earlier versions of RDU1 +- * used that pin as WP GPIO for eSDHC3 and +- * because of that that pad has an external +- * pull-up resistor. This is problematic +- * because out of reset the pad is configured +- * as ALT0 which serves as SD1_WP, which, when +- * pulled high by and external pull-up, will +- * inhibit execution of any write request to +- * attached eMMC device. +- * +- * To avoid this problem we configure the pad +- * to ALT1/GPIO and avoid driving SD1_WP +- * signal high. +- */ +- MX51_PAD_GPIO1_1__GPIO1_1 0x0000 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX51_PAD_EIM_EB2__FEC_MDIO 0x1f5 +- MX51_PAD_NANDF_D9__FEC_RDATA0 0x2180 +- MX51_PAD_EIM_EB3__FEC_RDATA1 0x180 +- MX51_PAD_EIM_CS2__FEC_RDATA2 0x180 +- MX51_PAD_EIM_CS3__FEC_RDATA3 0x180 +- MX51_PAD_EIM_CS4__FEC_RX_ER 0x180 +- MX51_PAD_NANDF_D11__FEC_RX_DV 0x2084 +- MX51_PAD_EIM_CS5__FEC_CRS 0x180 +- MX51_PAD_NANDF_RB2__FEC_COL 0x2180 +- MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x2180 +- MX51_PAD_NANDF_CS2__FEC_TX_ER 0x2004 +- MX51_PAD_NANDF_CS3__FEC_MDC 0x2004 +- MX51_PAD_NANDF_D8__FEC_TDATA0 0x2180 +- MX51_PAD_NANDF_CS4__FEC_TDATA1 0x2004 +- MX51_PAD_NANDF_CS5__FEC_TDATA2 0x2004 +- MX51_PAD_NANDF_CS6__FEC_TDATA3 0x2004 +- MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 +- MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 +- MX51_PAD_EIM_A20__GPIO2_14 0x85 +- >; +- }; +- +- pinctrl_gpiospi0: gpiospi0grp { +- fsl,pins = < +- MX51_PAD_CSI2_D18__GPIO4_11 0x85 +- MX51_PAD_CSI2_D19__GPIO4_12 0x85 +- MX51_PAD_CSI2_HSYNC__GPIO4_14 0x85 +- MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x85 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed +- MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed +- >; +- }; +- +- pinctrl_ipu_disp1: ipudisp1grp { +- fsl,pins = < +- MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 +- MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 +- MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 +- MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 +- MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 +- MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 +- MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 +- MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 +- MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 +- MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 +- MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 +- MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 +- MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 +- MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 +- MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 +- MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 +- MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 +- MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 +- MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 +- MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 +- MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 +- MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 +- MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 +- MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 +- MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 +- MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 +- MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 +- >; +- }; +- +- pinctrl_panel: panelgrp { +- fsl,pins = < +- MX51_PAD_DI1_D0_CS__GPIO3_3 0x85 +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX51_PAD_GPIO1_4__GPIO1_4 0x1e0 +- MX51_PAD_GPIO1_8__GPIO1_8 0x21e2 +- >; +- }; +- +- pinctrl_sndgate26mhz: sndgate26mhzgrp { +- fsl,pins = < +- MX51_PAD_CSPI1_RDY__GPIO4_26 0x85 +- >; +- }; +- +- pinctrl_swi2c: swi2cgrp { +- fsl,pins = < +- MX51_PAD_GPIO1_2__GPIO1_2 0xc5 +- MX51_PAD_DI1_D1_CS__GPIO3_4 0x400001f5 +- >; +- }; +- +- pinctrl_swmdio: swmdiogrp { +- fsl,pins = < +- MX51_PAD_NANDF_D14__GPIO3_26 0x21e6 +- MX51_PAD_NANDF_D15__GPIO3_25 0x21e6 +- >; +- }; +- +- pinctrl_ts: tsgrp { +- fsl,pins = < +- MX51_PAD_CSI1_D8__GPIO3_12 0x04 +- MX51_PAD_CSI1_D9__GPIO3_13 0x85 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 +- MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 +- MX51_PAD_UART1_RTS__UART1_RTS 0x1c4 +- MX51_PAD_UART1_CTS__UART1_CTS 0x1c4 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX51_PAD_UART2_RXD__UART2_RXD 0xc5 +- MX51_PAD_UART2_TXD__UART2_TXD 0xc5 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX51_PAD_EIM_D25__UART3_RXD 0x1c5 +- MX51_PAD_EIM_D26__UART3_TXD 0x1c5 +- >; +- }; +- +- pinctrl_usbgate26mhz: usbgate26mhzgrp { +- fsl,pins = < +- MX51_PAD_DISP2_DAT6__GPIO1_19 0x85 +- >; +- }; +- +- pinctrl_usbh1: usbh1grp { +- fsl,pins = < +- MX51_PAD_USBH1_STP__USBH1_STP 0x0 +- MX51_PAD_USBH1_CLK__USBH1_CLK 0x0 +- MX51_PAD_USBH1_DIR__USBH1_DIR 0x0 +- MX51_PAD_USBH1_NXT__USBH1_NXT 0x0 +- MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x0 +- MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x0 +- MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x0 +- MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x0 +- MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x0 +- MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x0 +- MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x0 +- MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x0 +- >; +- }; +- +- pinctrl_usbh1phy: usbh1phygrp { +- fsl,pins = < +- MX51_PAD_NANDF_D0__GPIO4_8 0x85 +- >; +- }; +- +- pinctrl_usbh2: usbh2grp { +- fsl,pins = < +- MX51_PAD_EIM_A26__USBH2_STP 0x0 +- MX51_PAD_EIM_A24__USBH2_CLK 0x0 +- MX51_PAD_EIM_A25__USBH2_DIR 0x0 +- MX51_PAD_EIM_A27__USBH2_NXT 0x0 +- MX51_PAD_EIM_D16__USBH2_DATA0 0x0 +- MX51_PAD_EIM_D17__USBH2_DATA1 0x0 +- MX51_PAD_EIM_D18__USBH2_DATA2 0x0 +- MX51_PAD_EIM_D19__USBH2_DATA3 0x0 +- MX51_PAD_EIM_D20__USBH2_DATA4 0x0 +- MX51_PAD_EIM_D21__USBH2_DATA5 0x0 +- MX51_PAD_EIM_D22__USBH2_DATA6 0x0 +- MX51_PAD_EIM_D23__USBH2_DATA7 0x0 +- >; +- }; +- +- pinctrl_usbh2phy: usbh2phygrp { +- fsl,pins = < +- MX51_PAD_NANDF_D1__GPIO4_7 0x85 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx51-zii-scu2-mezz.dts b/scripts/dtc/include-prefixes/arm/imx51-zii-scu2-mezz.dts +deleted file mode 100644 +index aa91e5dde4b8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx51-zii-scu2-mezz.dts ++++ /dev/null +@@ -1,457 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +- +-/* +- * Copyright (C) 2018 Zodiac Inflight Innovations +- */ +- +-/dts-v1/; +- +-#include "imx51.dtsi" +- +-/ { +- model = "ZII SCU2 Mezz Board"; +- compatible = "zii,imx51-scu2-mezz", "fsl,imx51"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- /* Will be filled by the bootloader */ +- memory@90000000 { +- device_type = "memory"; +- reg = <0x90000000 0>; +- }; +- +- aliases { +- mdio-gpio0 = &mdio_gpio; +- }; +- +- usb_vbus: regulator-usb-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_mmc_reset>; +- gpio = <&gpio3 13 GPIO_ACTIVE_LOW>; +- startup-delay-us = <150000>; +- regulator-name = "usb_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- mdio_gpio: mdio-gpio { +- compatible = "virtual,mdio-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_swmdio>; +- gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>, /* mdc */ +- <&gpio2 6 GPIO_ACTIVE_HIGH>; /* mdio */ +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch@0 { +- compatible = "marvell,mv88e6085"; +- reg = <0>; +- dsa,member = <0 0>; +- eeprom-length = <512>; +- interrupt-parent = <&gpio1>; +- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "port4"; +- }; +- +- port@1 { +- reg = <1>; +- label = "port5"; +- }; +- +- port@2 { +- reg = <2>; +- label = "port6"; +- }; +- +- port@3 { +- reg = <3>; +- label = "port7"; +- }; +- +- port@4 { +- reg = <4>; +- label = "cpu"; +- ethernet = <&fec>; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +- +- port@5 { +- reg = <5>; +- label = "mezz2esb"; +- phy-mode = "sgmii"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&cpu { +- cpu-supply = <&sw1_reg>; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, +- <&gpio4 25 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- pmic@0 { +- compatible = "fsl,mc13892"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- spi-max-frequency = <6000000>; +- spi-cs-high; +- reg = <0>; +- interrupt-parent = <&gpio1>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; +- fsl,mc13xxx-uses-adc; +- +- regulators { +- sw1_reg: sw1 { +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1375000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3_reg: sw3 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vpll_reg: vpll { +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdig_reg: vdig { +- regulator-min-microvolt = <1650000>; +- regulator-max-microvolt = <1650000>; +- regulator-boot-on; +- }; +- +- vsd_reg: vsd { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3150000>; +- regulator-always-on; +- }; +- +- vusb_reg: vusb { +- regulator-always-on; +- }; +- +- vusb2_reg: vusb2 { +- regulator-min-microvolt = <2400000>; +- regulator-max-microvolt = <2775000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vvideo_reg: vvideo { +- regulator-min-microvolt = <2775000>; +- regulator-max-microvolt = <2775000>; +- }; +- +- vaudio_reg: vaudio { +- regulator-min-microvolt = <2300000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- vcam_reg: vcam { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3150000>; +- regulator-always-on; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2900000>; +- regulator-always-on; +- }; +- }; +- +- leds { +- #address-cells = <1>; +- #size-cells = <0>; +- led-control = <0x0 0x0 0x3f83f8 0x0>; +- +- sysled3: led3@3 { +- reg = <3>; +- label = "system:red:power"; +- linux,default-trigger = "default-on"; +- }; +- +- sysled4: led4@4 { +- reg = <4>; +- label = "system:green:act"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- }; +- +- flash@1 { +- compatible = "atmel,at45", "atmel,dataflash"; +- reg = <1>; +- spi-max-frequency = <25000000>; +- }; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- bus-width = <8>; +- non-removable; +- no-1-8-v; +- no-sdio; +- no-sd; +- status = "okay"; +-}; +- +-&esdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc4>; +- bus-width = <4>; +- no-1-8-v; +- no-sdio; +- cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-mode = "mii"; +- status = "okay"; +- phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <1>; +- phy-supply = <&vgen3_reg>; +- phy-handle = <ðphy>; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy@0 { +- reg = <0>; +- max-speed = <100>; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c04"; +- pagesize = <16>; +- reg = <0x50>; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +- +- rave-sp { +- compatible = "zii,rave-sp-mezz"; +- current-speed = <57600>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- watchdog { +- compatible = "zii,rave-sp-watchdog-legacy"; +- }; +- +- eeprom@a4 { +- compatible = "zii,rave-sp-eeprom"; +- reg = <0xa4 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- zii,eeprom-name = "main-eeprom"; +- }; +- }; +-}; +- +-&usbotg { +- dr_mode = "host"; +- disable-over-current; +- phy_type = "utmi_wide"; +- vbus-supply = <&usb_vbus>; +- status = "okay"; +-}; +- +-&usbphy0 { +- vcc-supply = <&vusb2_reg>; +-}; +- +-&vpu { +- status = "disabled"; +-}; +- +-&wdog1 { +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 +- MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 +- MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 +- MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 +- MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 +- MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 +- MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 +- MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 +- MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 +- MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 +- MX51_PAD_SD2_DATA0__SD1_DAT4 0x20d5 +- MX51_PAD_SD2_DATA1__SD1_DAT5 0x20d5 +- MX51_PAD_SD2_DATA2__SD1_DAT6 0x20d5 +- MX51_PAD_SD2_DATA3__SD1_DAT7 0x20d5 +- >; +- }; +- +- pinctrl_esdhc4: esdhc4grp { +- fsl,pins = < +- MX51_PAD_NANDF_RB1__SD4_CMD 0x400020d5 +- MX51_PAD_NANDF_CS2__SD4_CLK 0x20d5 +- MX51_PAD_NANDF_CS3__SD4_DAT0 0x20d5 +- MX51_PAD_NANDF_CS4__SD4_DAT1 0x20d5 +- MX51_PAD_NANDF_CS5__SD4_DAT2 0x20d5 +- MX51_PAD_NANDF_CS6__SD4_DAT3 0x20d5 +- MX51_PAD_NANDF_D0__GPIO4_8 0x100 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004 +- MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004 +- MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004 +- MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004 +- MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 +- MX51_PAD_DISP2_DAT10__FEC_COL 0x0180 +- MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180 +- MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4 +- MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x20a4 +- MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 +- MX51_PAD_DI_GP3__FEC_TX_ER 0x2004 +- MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180 +- MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085 +- MX51_PAD_DI_GP4__FEC_RDATA2 0x0085 +- MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085 +- MX51_PAD_DI2_PIN2__FEC_MDC 0x2004 +- MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5 +- MX51_PAD_DI2_PIN4__FEC_CRS 0x0180 +- MX51_PAD_EIM_A20__GPIO2_14 0x0085 +- MX51_PAD_EIM_A21__GPIO2_15 0x00e5 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed +- MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX51_PAD_GPIO1_4__GPIO1_4 0x85 +- MX51_PAD_GPIO1_8__GPIO1_8 0xe5 +- >; +- }; +- +- pinctrl_swmdio: swmdiogrp { +- fsl,pins = < +- MX51_PAD_EIM_D22__GPIO2_6 0x100 +- MX51_PAD_EIM_D23__GPIO2_7 0x100 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 +- MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 +- MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 +- >; +- }; +- +- pinctrl_usb_mmc_reset: usbmmcgrp { +- fsl,pins = < +- MX51_PAD_CSI1_D9__GPIO3_13 0x85 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx51-zii-scu3-esb.dts b/scripts/dtc/include-prefixes/arm/imx51-zii-scu3-esb.dts +deleted file mode 100644 +index 875b10a7d674..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx51-zii-scu3-esb.dts ++++ /dev/null +@@ -1,472 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +- +-/* +- * Copyright (C) 2018 Zodiac Inflight Innovations +- */ +- +-/dts-v1/; +- +-#include "imx51.dtsi" +- +-/ { +- model = "ZII SCU3 ESB board"; +- compatible = "zii,imx51-scu3-esb", "fsl,imx51"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- /* Will be filled by the bootloader */ +- memory@90000000 { +- device_type = "memory"; +- reg = <0x90000000 0>; +- }; +- +- usb_vbus: regulator-usb-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_mmc_reset>; +- gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; +- startup-delay-us = <150000>; +- }; +-}; +- +-&cpu { +- cpu-supply = <&sw1_reg>; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, +- <&gpio4 25 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- pmic@0 { +- compatible = "fsl,mc13892"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- spi-max-frequency = <6000000>; +- spi-cs-high; +- reg = <0>; +- interrupt-parent = <&gpio1>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; +- fsl,mc13xxx-uses-adc; +- +- regulators { +- sw1_reg: sw1 { +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1375000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3_reg: sw3 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vpll_reg: vpll { +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdig_reg: vdig { +- regulator-min-microvolt = <1650000>; +- regulator-max-microvolt = <1650000>; +- regulator-boot-on; +- }; +- +- vsd_reg: vsd { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3150000>; +- }; +- +- vusb_reg: vusb { +- regulator-always-on; +- }; +- +- vusb2_reg: vusb2 { +- regulator-min-microvolt = <2400000>; +- regulator-max-microvolt = <2775000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vvideo_reg: vvideo { +- regulator-min-microvolt = <2775000>; +- regulator-max-microvolt = <2775000>; +- }; +- +- vaudio_reg: vaudio { +- regulator-min-microvolt = <2300000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- vcam_reg: vcam { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3150000>; +- regulator-always-on; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2900000>; +- regulator-always-on; +- }; +- }; +- +- leds { +- #address-cells = <1>; +- #size-cells = <0>; +- led-control = <0x0 0x0 0x3f83f8 0x0>; +- +- sysled3: led3@3 { +- reg = <3>; +- label = "system:red:power"; +- linux,default-trigger = "default-on"; +- }; +- +- sysled4: led4@4 { +- reg = <4>; +- label = "system:green:act"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- }; +- +- flash@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "atmel,at45", "atmel,dataflash"; +- spi-max-frequency = <25000000>; +- reg = <1>; +- }; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- bus-width = <8>; +- non-removable; +- no-1-8-v; +- no-sdio; +- no-sd; +- status = "okay"; +-}; +- +-&esdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc4>; +- bus-width = <4>; +- no-1-8-v; +- no-sdio; +- cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-mode = "mii"; +- status = "okay"; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- +- fec_mdio: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- switch@0 { +- compatible = "marvell,mv88e6085"; +- reg = <0>; +- dsa,member = <0 0>; +- eeprom-length = <512>; +- interrupt-parent = <&gpio4>; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-controller; +- #interrupt-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_switch>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "port1"; +- }; +- +- port@1 { +- reg = <1>; +- label = "port2"; +- }; +- +- port@2 { +- reg = <2>; +- label = "port3"; +- }; +- +- port@3 { +- reg = <3>; +- label = "scu2scu"; +- }; +- +- port@4 { +- reg = <4>; +- label = "esb2host"; +- }; +- +- port@5 { +- reg = <5>; +- label = "esb2mezz"; +- phy-mode = "sgmii"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- port@6 { +- reg = <6>; +- label = "cpu"; +- phy-mode = "mii"; +- ethernet = <&fec>; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&ipu { +- status = "disabled"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c04"; +- pagesize = <16>; +- reg = <0x50>; +- }; +- +- lm75@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +- +- rave-sp { +- compatible = "zii,rave-sp-esb"; +- current-speed = <57600>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- watchdog { +- compatible = "zii,rave-sp-watchdog-legacy"; +- }; +- +- eeprom@a4 { +- compatible = "zii,rave-sp-eeprom"; +- reg = <0xa4 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- zii,eeprom-name = "main-eeprom"; +- }; +- }; +-}; +- +-&usbotg { +- dr_mode = "host"; +- disable-over-current; +- phy_type = "utmi_wide"; +- vbus-supply = <&usb_vbus>; +- status = "okay"; +-}; +- +-&usbphy0 { +- vcc-supply = <&vusb2_reg>; +-}; +- +-&vpu { +- status = "disabled"; +-}; +- +-&wdog1 { +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 +- MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 +- MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 +- MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 +- MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 +- MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 +- MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 +- MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 +- MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 +- MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 +- MX51_PAD_SD2_DATA0__SD1_DAT4 0x20d5 +- MX51_PAD_SD2_DATA1__SD1_DAT5 0x20d5 +- MX51_PAD_SD2_DATA2__SD1_DAT6 0x20d5 +- MX51_PAD_SD2_DATA3__SD1_DAT7 0x20d5 +- >; +- }; +- +- pinctrl_esdhc4: esdhc4grp { +- fsl,pins = < +- MX51_PAD_NANDF_RB1__SD4_CMD 0x400020d5 +- MX51_PAD_NANDF_CS2__SD4_CLK 0x20d5 +- MX51_PAD_NANDF_CS3__SD4_DAT0 0x20d5 +- MX51_PAD_NANDF_CS4__SD4_DAT1 0x20d5 +- MX51_PAD_NANDF_CS5__SD4_DAT2 0x20d5 +- MX51_PAD_NANDF_CS6__SD4_DAT3 0x20d5 +- MX51_PAD_NANDF_D0__GPIO4_8 0x100 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004 +- MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004 +- MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004 +- MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004 +- MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 +- MX51_PAD_DISP2_DAT10__FEC_COL 0x0180 +- MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180 +- MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4 +- +- MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 +- MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180 +- MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085 +- MX51_PAD_DI_GP4__FEC_RDATA2 0x0085 +- MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085 +- MX51_PAD_DI2_PIN2__FEC_MDC 0x2004 +- MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5 +- MX51_PAD_DI2_PIN4__FEC_CRS 0x0180 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed +- MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX51_PAD_GPIO1_4__GPIO1_4 0x85 +- MX51_PAD_GPIO1_8__GPIO1_8 0xe5 +- >; +- }; +- +- pinctrl_switch: switchgrp { +- fsl,pins = < +- MX51_PAD_AUD3_BB_CK__GPIO4_20 0xc5 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 +- MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 +- MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 +- MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 +- MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 +- MX51_PAD_USBH1_DATA0__UART2_CTS 0x1c5 +- MX51_PAD_USBH1_DATA3__UART2_RTS 0x1c5 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 +- MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 +- >; +- }; +- +- pinctrl_usb_mmc_reset: usbmmcgrp { +- fsl,pins = < +- MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x100 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx51.dtsi b/scripts/dtc/include-prefixes/arm/imx51.dtsi +deleted file mode 100644 +index 01cfcbe5928e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx51.dtsi ++++ /dev/null +@@ -1,654 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2011 Freescale Semiconductor, Inc. +-// Copyright 2011 Linaro Ltd. +- +-#include "imx51-pinfunc.h" +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * The decompressor and also some bootloaders rely on a +- * pre-existing /chosen node to be available to insert the +- * command line and merge other ATAGS info. +- */ +- chosen {}; +- +- aliases { +- ethernet0 = &fec; +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- gpio3 = &gpio4; +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- mmc0 = &esdhc1; +- mmc1 = &esdhc2; +- mmc2 = &esdhc3; +- mmc3 = &esdhc4; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- spi0 = &ecspi1; +- spi1 = &ecspi2; +- spi2 = &cspi; +- }; +- +- tzic: tz-interrupt-controller@e0000000 { +- compatible = "fsl,imx51-tzic", "fsl,tzic"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0xe0000000 0x4000>; +- }; +- +- clocks { +- ckil { +- compatible = "fsl,imx-ckil", "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- ckih1 { +- compatible = "fsl,imx-ckih1", "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- ckih2 { +- compatible = "fsl,imx-ckih2", "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- osc { +- compatible = "fsl,imx-osc", "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a8"; +- reg = <0>; +- clock-latency = <62500>; +- clocks = <&clks IMX5_CLK_CPU_PODF>; +- clock-names = "cpu"; +- operating-points = < +- 166000 1000000 +- 600000 1050000 +- 800000 1100000 +- >; +- voltage-tolerance = <5>; +- }; +- }; +- +- pmu: pmu { +- compatible = "arm,cortex-a8-pmu"; +- interrupt-parent = <&tzic>; +- interrupts = <77>; +- }; +- +- usbphy0: usbphy0 { +- compatible = "usb-nop-xceiv"; +- clocks = <&clks IMX5_CLK_USB_PHY_GATE>; +- clock-names = "main_clk"; +- #phy-cells = <0>; +- }; +- +- capture-subsystem { +- compatible = "fsl,imx-capture-subsystem"; +- ports = <&ipu_csi0>, <&ipu_csi1>; +- }; +- +- display-subsystem { +- compatible = "fsl,imx-display-subsystem"; +- ports = <&ipu_di0>, <&ipu_di1>; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&tzic>; +- ranges; +- +- iram: sram@1ffe0000 { +- compatible = "mmio-sram"; +- reg = <0x1ffe0000 0x20000>; +- }; +- +- gpu: gpu@30000000 { +- compatible = "amd,imageon-200.1", "amd,imageon"; +- reg = <0x30000000 0x20000>; +- reg-names = "kgsl_3d0_reg_memory"; +- interrupts = <12>; +- interrupt-names = "kgsl_3d0_irq"; +- clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; +- clock-names = "core_clk", "mem_iface_clk"; +- }; +- +- ipu: ipu@40000000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx51-ipu"; +- reg = <0x40000000 0x20000000>; +- interrupts = <11 10>; +- clocks = <&clks IMX5_CLK_IPU_GATE>, +- <&clks IMX5_CLK_IPU_DI0_GATE>, +- <&clks IMX5_CLK_IPU_DI1_GATE>; +- clock-names = "bus", "di0", "di1"; +- resets = <&src 2>; +- +- ipu_csi0: port@0 { +- reg = <0>; +- }; +- +- ipu_csi1: port@1 { +- reg = <1>; +- }; +- +- ipu_di0: port@2 { +- reg = <2>; +- +- ipu_di0_disp1: endpoint { +- }; +- }; +- +- ipu_di1: port@3 { +- reg = <3>; +- +- ipu_di1_disp2: endpoint { +- }; +- }; +- }; +- +- bus@70000000 { /* AIPS1 */ +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x70000000 0x10000000>; +- ranges; +- +- spba@70000000 { +- compatible = "fsl,spba-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x70000000 0x40000>; +- ranges; +- +- esdhc1: mmc@70004000 { +- compatible = "fsl,imx51-esdhc"; +- reg = <0x70004000 0x4000>; +- interrupts = <1>; +- clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, +- <&clks IMX5_CLK_DUMMY>, +- <&clks IMX5_CLK_ESDHC1_PER_GATE>; +- clock-names = "ipg", "ahb", "per"; +- status = "disabled"; +- }; +- +- esdhc2: mmc@70008000 { +- compatible = "fsl,imx51-esdhc"; +- reg = <0x70008000 0x4000>; +- interrupts = <2>; +- clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, +- <&clks IMX5_CLK_DUMMY>, +- <&clks IMX5_CLK_ESDHC2_PER_GATE>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- uart3: serial@7000c000 { +- compatible = "fsl,imx51-uart", "fsl,imx21-uart"; +- reg = <0x7000c000 0x4000>; +- interrupts = <33>; +- clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, +- <&clks IMX5_CLK_UART3_PER_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- ecspi1: spi@70010000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx51-ecspi"; +- reg = <0x70010000 0x4000>; +- interrupts = <36>; +- clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, +- <&clks IMX5_CLK_ECSPI1_PER_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- ssi2: ssi@70014000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; +- reg = <0x70014000 0x4000>; +- interrupts = <30>; +- clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, +- <&clks IMX5_CLK_SSI2_ROOT_GATE>; +- clock-names = "ipg", "baud"; +- dmas = <&sdma 24 1 0>, +- <&sdma 25 1 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- esdhc3: mmc@70020000 { +- compatible = "fsl,imx51-esdhc"; +- reg = <0x70020000 0x4000>; +- interrupts = <3>; +- clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, +- <&clks IMX5_CLK_DUMMY>, +- <&clks IMX5_CLK_ESDHC3_PER_GATE>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- esdhc4: mmc@70024000 { +- compatible = "fsl,imx51-esdhc"; +- reg = <0x70024000 0x4000>; +- interrupts = <4>; +- clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, +- <&clks IMX5_CLK_DUMMY>, +- <&clks IMX5_CLK_ESDHC4_PER_GATE>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- }; +- +- aipstz1: bridge@73f00000 { +- compatible = "fsl,imx51-aipstz"; +- reg = <0x73f00000 0x60>; +- }; +- +- usbotg: usb@73f80000 { +- compatible = "fsl,imx51-usb", "fsl,imx27-usb"; +- reg = <0x73f80000 0x0200>; +- interrupts = <18>; +- clocks = <&clks IMX5_CLK_USBOH3_GATE>; +- fsl,usbmisc = <&usbmisc 0>; +- fsl,usbphy = <&usbphy0>; +- status = "disabled"; +- }; +- +- usbh1: usb@73f80200 { +- compatible = "fsl,imx51-usb", "fsl,imx27-usb"; +- reg = <0x73f80200 0x0200>; +- interrupts = <14>; +- clocks = <&clks IMX5_CLK_USBOH3_GATE>; +- fsl,usbmisc = <&usbmisc 1>; +- dr_mode = "host"; +- status = "disabled"; +- }; +- +- usbh2: usb@73f80400 { +- compatible = "fsl,imx51-usb", "fsl,imx27-usb"; +- reg = <0x73f80400 0x0200>; +- interrupts = <16>; +- clocks = <&clks IMX5_CLK_USBOH3_GATE>; +- fsl,usbmisc = <&usbmisc 2>; +- dr_mode = "host"; +- status = "disabled"; +- }; +- +- usbh3: usb@73f80600 { +- compatible = "fsl,imx51-usb", "fsl,imx27-usb"; +- reg = <0x73f80600 0x0200>; +- interrupts = <17>; +- clocks = <&clks IMX5_CLK_USBOH3_GATE>; +- fsl,usbmisc = <&usbmisc 3>; +- dr_mode = "host"; +- status = "disabled"; +- }; +- +- usbmisc: usbmisc@73f80800 { +- #index-cells = <1>; +- compatible = "fsl,imx51-usbmisc"; +- reg = <0x73f80800 0x200>; +- clocks = <&clks IMX5_CLK_USBOH3_GATE>; +- }; +- +- gpio1: gpio@73f84000 { +- compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; +- reg = <0x73f84000 0x4000>; +- interrupts = <50 51>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@73f88000 { +- compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; +- reg = <0x73f88000 0x4000>; +- interrupts = <52 53>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio@73f8c000 { +- compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; +- reg = <0x73f8c000 0x4000>; +- interrupts = <54 55>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio4: gpio@73f90000 { +- compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; +- reg = <0x73f90000 0x4000>; +- interrupts = <56 57>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- kpp: kpp@73f94000 { +- compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; +- reg = <0x73f94000 0x4000>; +- interrupts = <60>; +- clocks = <&clks IMX5_CLK_DUMMY>; +- status = "disabled"; +- }; +- +- wdog1: watchdog@73f98000 { +- compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; +- reg = <0x73f98000 0x4000>; +- interrupts = <58>; +- clocks = <&clks IMX5_CLK_DUMMY>; +- }; +- +- wdog2: watchdog@73f9c000 { +- compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; +- reg = <0x73f9c000 0x4000>; +- interrupts = <59>; +- clocks = <&clks IMX5_CLK_DUMMY>; +- status = "disabled"; +- }; +- +- gpt: timer@73fa0000 { +- compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; +- reg = <0x73fa0000 0x4000>; +- interrupts = <39>; +- clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, +- <&clks IMX5_CLK_GPT_HF_GATE>; +- clock-names = "ipg", "per"; +- }; +- +- iomuxc: iomuxc@73fa8000 { +- compatible = "fsl,imx51-iomuxc"; +- reg = <0x73fa8000 0x4000>; +- }; +- +- pwm1: pwm@73fb4000 { +- #pwm-cells = <3>; +- compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; +- reg = <0x73fb4000 0x4000>; +- clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, +- <&clks IMX5_CLK_PWM1_HF_GATE>; +- clock-names = "ipg", "per"; +- interrupts = <61>; +- }; +- +- pwm2: pwm@73fb8000 { +- #pwm-cells = <3>; +- compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; +- reg = <0x73fb8000 0x4000>; +- clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, +- <&clks IMX5_CLK_PWM2_HF_GATE>; +- clock-names = "ipg", "per"; +- interrupts = <94>; +- }; +- +- uart1: serial@73fbc000 { +- compatible = "fsl,imx51-uart", "fsl,imx21-uart"; +- reg = <0x73fbc000 0x4000>; +- interrupts = <31>; +- clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, +- <&clks IMX5_CLK_UART1_PER_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart2: serial@73fc0000 { +- compatible = "fsl,imx51-uart", "fsl,imx21-uart"; +- reg = <0x73fc0000 0x4000>; +- interrupts = <32>; +- clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, +- <&clks IMX5_CLK_UART2_PER_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- src: reset-controller@73fd0000 { +- compatible = "fsl,imx51-src"; +- reg = <0x73fd0000 0x4000>; +- interrupts = <75>; +- #reset-cells = <1>; +- }; +- +- clks: ccm@73fd4000{ +- compatible = "fsl,imx51-ccm"; +- reg = <0x73fd4000 0x4000>; +- interrupts = <0 71 0x04 0 72 0x04>; +- #clock-cells = <1>; +- }; +- }; +- +- bus@80000000 { /* AIPS2 */ +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x80000000 0x10000000>; +- ranges; +- +- aipstz2: bridge@83f00000 { +- compatible = "fsl,imx51-aipstz"; +- reg = <0x83f00000 0x60>; +- }; +- +- iim: efuse@83f98000 { +- compatible = "fsl,imx51-iim", "fsl,imx27-iim", "syscon"; +- reg = <0x83f98000 0x4000>; +- interrupts = <69>; +- clocks = <&clks IMX5_CLK_IIM_GATE>; +- }; +- +- tigerp: tigerp@83fa0000 { +- compatible = "fsl,imx51-tigerp"; +- reg = <0x83fa0000 0x28>; +- }; +- +- owire: owire@83fa4000 { +- compatible = "fsl,imx51-owire", "fsl,imx21-owire"; +- reg = <0x83fa4000 0x4000>; +- interrupts = <88>; +- clocks = <&clks IMX5_CLK_OWIRE_GATE>; +- status = "disabled"; +- }; +- +- ecspi2: spi@83fac000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx51-ecspi"; +- reg = <0x83fac000 0x4000>; +- interrupts = <37>; +- clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, +- <&clks IMX5_CLK_ECSPI2_PER_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- sdma: sdma@83fb0000 { +- compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; +- reg = <0x83fb0000 0x4000>; +- interrupts = <6>; +- clocks = <&clks IMX5_CLK_SDMA_GATE>, +- <&clks IMX5_CLK_AHB>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; +- }; +- +- cspi: spi@83fc0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; +- reg = <0x83fc0000 0x4000>; +- interrupts = <38>; +- clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, +- <&clks IMX5_CLK_CSPI_IPG_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- i2c2: i2c@83fc4000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; +- reg = <0x83fc4000 0x4000>; +- interrupts = <63>; +- clocks = <&clks IMX5_CLK_I2C2_GATE>; +- status = "disabled"; +- }; +- +- i2c1: i2c@83fc8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; +- reg = <0x83fc8000 0x4000>; +- interrupts = <62>; +- clocks = <&clks IMX5_CLK_I2C1_GATE>; +- status = "disabled"; +- }; +- +- ssi1: ssi@83fcc000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; +- reg = <0x83fcc000 0x4000>; +- interrupts = <29>; +- clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, +- <&clks IMX5_CLK_SSI1_ROOT_GATE>; +- clock-names = "ipg", "baud"; +- dmas = <&sdma 28 0 0>, +- <&sdma 29 0 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- audmux: audmux@83fd0000 { +- compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; +- reg = <0x83fd0000 0x4000>; +- clocks = <&clks IMX5_CLK_DUMMY>; +- clock-names = "audmux"; +- status = "disabled"; +- }; +- +- m4if: m4if@83fd8000 { +- compatible = "fsl,imx51-m4if"; +- reg = <0x83fd8000 0x1000>; +- }; +- +- weim: weim@83fda000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,imx51-weim"; +- reg = <0x83fda000 0x1000>; +- clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>; +- ranges = < +- 0 0 0xb0000000 0x08000000 +- 1 0 0xb8000000 0x08000000 +- 2 0 0xc0000000 0x08000000 +- 3 0 0xc8000000 0x04000000 +- 4 0 0xcc000000 0x02000000 +- 5 0 0xce000000 0x02000000 +- >; +- status = "disabled"; +- }; +- +- nfc: nand@83fdb000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,imx51-nand"; +- reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; +- interrupts = <8>; +- clocks = <&clks IMX5_CLK_NFC_GATE>; +- status = "disabled"; +- }; +- +- pata: pata@83fe0000 { +- compatible = "fsl,imx51-pata", "fsl,imx27-pata"; +- reg = <0x83fe0000 0x4000>; +- interrupts = <70>; +- clocks = <&clks IMX5_CLK_PATA_GATE>; +- status = "disabled"; +- }; +- +- ssi3: ssi@83fe8000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; +- reg = <0x83fe8000 0x4000>; +- interrupts = <96>; +- clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, +- <&clks IMX5_CLK_SSI3_ROOT_GATE>; +- clock-names = "ipg", "baud"; +- dmas = <&sdma 46 0 0>, +- <&sdma 47 0 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- fec: ethernet@83fec000 { +- compatible = "fsl,imx51-fec", "fsl,imx27-fec"; +- reg = <0x83fec000 0x4000>; +- interrupts = <87>; +- clocks = <&clks IMX5_CLK_FEC_GATE>, +- <&clks IMX5_CLK_FEC_GATE>, +- <&clks IMX5_CLK_FEC_GATE>; +- clock-names = "ipg", "ahb", "ptp"; +- status = "disabled"; +- }; +- +- vpu: vpu@83ff4000 { +- compatible = "fsl,imx51-vpu", "cnm,codahx4"; +- reg = <0x83ff4000 0x1000>; +- interrupts = <9>; +- clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, +- <&clks IMX5_CLK_VPU_GATE>; +- clock-names = "per", "ahb"; +- resets = <&src 1>; +- iram = <&iram>; +- }; +- +- sahara: crypto@83ff8000 { +- compatible = "fsl,imx53-sahara", "fsl,imx51-sahara"; +- reg = <0x83ff8000 0x4000>; +- interrupts = <19 20>; +- clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, +- <&clks IMX5_CLK_SAHARA_IPG_GATE>; +- clock-names = "ipg", "ahb"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-ard.dts b/scripts/dtc/include-prefixes/arm/imx53-ard.dts +deleted file mode 100644 +index 6208fbb2e741..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-ard.dts ++++ /dev/null +@@ -1,179 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2011 Freescale Semiconductor, Inc. +- * Copyright 2011 Linaro Ltd. +- */ +- +-/dts-v1/; +-#include +-#include "imx53.dtsi" +- +-/ { +- model = "Freescale i.MX53 Automotive Reference Design Board"; +- compatible = "fsl,imx53-ard", "fsl,imx53"; +- +- memory@70000000 { +- device_type = "memory"; +- reg = <0x70000000 0x40000000>; +- }; +- +- eim-cs1@f4000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,eim-bus", "simple-bus"; +- reg = <0xf4000000 0x3ff0000>; +- ranges; +- +- ethernet@f4000000 { +- compatible = "smsc,lan9220", "smsc,lan9115"; +- reg = <0xf4000000 0x2000000>; +- phy-mode = "mii"; +- interrupt-parent = <&gpio2>; +- interrupts = <31 0x8>; +- reg-io-width = <4>; +- /* +- * VDD33A and VDDVARIO of LAN9220 are supplied by +- * SW4_3V3 of LTC3589. Before the regulator driver +- * for this PMIC is available, we use a fixed dummy +- * 3V3 regulator to get LAN9220 driver probing work. +- */ +- vdd33a-supply = <®_3p3v>; +- vddvario-supply = <®_3p3v>; +- smsc,irq-push-pull; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_3p3v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- home { +- label = "Home"; +- gpios = <&gpio5 10 0>; +- linux,code = ; +- wakeup-source; +- }; +- +- back { +- label = "Back"; +- gpios = <&gpio5 11 0>; +- linux,code = ; +- wakeup-source; +- }; +- +- program { +- label = "Program"; +- gpios = <&gpio5 12 0>; +- linux,code = ; +- wakeup-source; +- }; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&gpio5 13 0>; +- linux,code = ; +- }; +- +- volume-down { +- label = "Volume Down"; +- gpios = <&gpio4 0 0>; +- linux,code = ; +- }; +- }; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx53-ard { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX53_PAD_GPIO_1__GPIO1_1 0x80000000 +- MX53_PAD_GPIO_9__GPIO1_9 0x80000000 +- MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 +- MX53_PAD_GPIO_10__GPIO4_0 0x80000000 +- MX53_PAD_DISP0_DAT16__GPIO5_10 0x80000000 +- MX53_PAD_DISP0_DAT17__GPIO5_11 0x80000000 +- MX53_PAD_DISP0_DAT18__GPIO5_12 0x80000000 +- MX53_PAD_DISP0_DAT19__GPIO5_13 0x80000000 +- MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x80000000 +- MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x80000000 +- MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x80000000 +- MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x80000000 +- MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x80000000 +- MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x80000000 +- MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x80000000 +- MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x80000000 +- MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x80000000 +- MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x80000000 +- MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x80000000 +- MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x80000000 +- MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x80000000 +- MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x80000000 +- MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x80000000 +- MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x80000000 +- MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x80000000 +- MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x80000000 +- MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x80000000 +- MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x80000000 +- MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x80000000 +- MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x80000000 +- MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x80000000 +- MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000 +- MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000 +- MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000 +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 +- MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 +- MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 +- MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 +- MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5 +- MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5 +- MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5 +- MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5 +- MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 +- MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 +- MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 +- >; +- }; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-cx9020.dts b/scripts/dtc/include-prefixes/arm/imx53-cx9020.dts +deleted file mode 100644 +index cfb18849a92b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-cx9020.dts ++++ /dev/null +@@ -1,295 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2017 Beckhoff Automation GmbH & Co. KG +- * based on imx53-qsb.dts +- */ +- +-/dts-v1/; +-#include "imx53.dtsi" +- +-/ { +- model = "Beckhoff CX9020 Embedded PC"; +- compatible = "bhf,cx9020", "fsl,imx53"; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- memory@70000000 { +- device_type = "memory"; +- reg = <0x70000000 0x20000000>, +- <0xb0000000 0x20000000>; +- }; +- +- display-0 { +- #address-cells =<1>; +- #size-cells = <0>; +- compatible = "fsl,imx-parallel-display"; +- interface-pix-fmt = "rgb24"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu_disp0>; +- +- port@0 { +- reg = <0>; +- +- display0_in: endpoint { +- remote-endpoint = <&ipu_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- display0_out: endpoint { +- remote-endpoint = <&tfp410_in>; +- }; +- }; +- }; +- +- dvi-connector { +- compatible = "dvi-connector"; +- ddc-i2c-bus = <&i2c2>; +- digital; +- +- port { +- dvi_connector_in: endpoint { +- remote-endpoint = <&tfp410_out>; +- }; +- }; +- }; +- +- dvi-converter { +- compatible = "ti,tfp410"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tfp410_in: endpoint { +- remote-endpoint = <&display0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- tfp410_out: endpoint { +- remote-endpoint = <&dvi_connector_in>; +- }; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pwr-r { +- gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- pwr-g { +- gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- pwr-b { +- gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- sd1-b { +- linux,default-trigger = "mmc0"; +- gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; +- }; +- +- sd2-b { +- linux,default-trigger = "mmc1"; +- gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- regulator-3p2v { +- compatible = "regulator-fixed"; +- regulator-name = "3P2V"; +- regulator-min-microvolt = <3200000>; +- regulator-max-microvolt = <3200000>; +- regulator-always-on; +- }; +- +- reg_usb_vbus: regulator-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&esdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc2>; +- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-mode = "rmii"; +- phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&ipu_di0_disp0 { +- remote-endpoint = <&display0_in>; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- fsl,dte-mode; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_vbus>; +- phy_type = "utmi"; +- status = "okay"; +-}; +- +-&usbotg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&vpu { +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX53_PAD_GPIO_0__CCM_CLKO 0x1c4 +- MX53_PAD_GPIO_16__I2C3_SDA 0x1c4 +- MX53_PAD_EIM_D22__GPIO3_22 0x1c4 +- MX53_PAD_EIM_D23__GPIO3_23 0x1e4 +- MX53_PAD_EIM_D24__GPIO3_24 0x1e4 +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 +- MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 +- MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 +- MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 +- MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 +- MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 +- MX53_PAD_GPIO_1__ESDHC1_CD 0x1c4 +- MX53_PAD_EIM_D17__GPIO3_17 0x1e4 +- MX53_PAD_GPIO_3__GPIO1_3 0x1c4 +- >; +- }; +- +- pinctrl_esdhc2: esdhc2grp { +- fsl,pins = < +- MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 +- MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 +- MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 +- MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 +- MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 +- MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 +- MX53_PAD_GPIO_4__ESDHC2_CD 0x1e4 +- MX53_PAD_EIM_D20__GPIO3_20 0x1e4 +- MX53_PAD_GPIO_8__GPIO1_8 0x1c4 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX53_PAD_FEC_MDC__FEC_MDC 0x4 +- MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc +- MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 +- MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 +- MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 +- MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 +- MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 +- MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 +- MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 +- MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 +- MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 +- >; +- }; +- +- pinctrl_ipu_disp0: ipudisp0grp { +- fsl,pins = < +- MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 +- MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 +- MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 +- MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 +- MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5 +- MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 +- MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 +- MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 +- MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 +- MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 +- MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 +- MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 +- MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 +- MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 +- MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 +- MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 +- MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 +- MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 +- MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 +- MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 +- MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 +- MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 +- MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 +- MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 +- MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 +- MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 +- MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 +- MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 +- MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4 +- MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4 +- MX53_PAD_EIM_D28__UART2_RTS 0x1e4 +- MX53_PAD_EIM_D29__UART2_CTS 0x1e4 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-kp-ddc.dts b/scripts/dtc/include-prefixes/arm/imx53-kp-ddc.dts +deleted file mode 100644 +index 0e7f071fd10e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-kp-ddc.dts ++++ /dev/null +@@ -1,146 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2018 +- * Lukasz Majewski, DENX Software Engineering, lukma@denx.de +- */ +- +-/dts-v1/; +-#include "imx53-kp.dtsi" +- +-/ { +- model = "K+P imx53 DDC"; +- compatible = "kiebackpeter,imx53-ddc", "fsl,imx53"; +- +- backlight_lcd: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm2 0 50000>; +- power-supply = <®_backlight>; +- brightness-levels = <0 24 28 32 36 +- 40 44 48 52 56 +- 60 64 68 72 76 +- 80 84 88 92 96 100>; +- default-brightness-level = <20>; +- }; +- +- lcd_display: display { +- compatible = "fsl,imx-parallel-display"; +- #address-cells = <1>; +- #size-cells = <0>; +- interface-pix-fmt = "rgb24"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_disp>; +- +- port@0 { +- reg = <0>; +- +- display1_in: endpoint { +- remote-endpoint = <&ipu_di1_disp1>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lcd_display_out: endpoint { +- remote-endpoint = <&lcd_panel_in>; +- }; +- }; +- }; +- +- lcd_panel: lcd-panel { +- compatible = "koe,tx14d24vm1bpa"; +- backlight = <&backlight_lcd>; +- power-supply = <®_3v3>; +- +- port { +- lcd_panel_in: endpoint { +- remote-endpoint = <&lcd_display_out>; +- }; +- }; +- }; +- +- reg_backlight: regulator-backlight { +- compatible = "regulator-fixed"; +- regulator-name = "backlight-supply"; +- regulator-min-microvolt = <15000000>; +- regulator-max-microvolt = <15000000>; +- regulator-always-on; +- }; +-}; +- +-&fec { +- status = "okay"; +-}; +- +-&i2c3 { +- adc@48 { +- compatible = "ti,ads1015"; +- reg = <0x48>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@4 { +- reg = <4>; +- ti,gain = <2>; +- ti,datarate = <4>; +- }; +- +- channel@6 { +- reg = <6>; +- ti,gain = <2>; +- ti,datarate = <4>; +- }; +- }; +- +- gpio-expander2@21 { +- compatible = "nxp,pcf8574"; +- reg = <0x21>; +- interrupts = <109>; +- #gpio-cells = <2>; +- gpio-controller; +- }; +-}; +- +-&iomuxc { +- imx53-kp-ddc { +- pinctrl_disp: dispgrp { +- fsl,pins = < +- MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x4 +- MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x4 +- MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x4 +- MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x4 +- MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x4 +- MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x4 +- MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x4 +- MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x4 +- MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x4 +- MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x4 +- MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x4 +- MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x4 +- MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x4 +- MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x4 +- MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x4 +- MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x4 +- MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x4 +- MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x4 +- MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x4 +- MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x4 +- MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x4 +- MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x4 +- MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x4 +- MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x4 +- MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x4 +- MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x4 +- MX53_PAD_GPIO_1__PWM2_PWMO 0x4 +- >; +- }; +- }; +-}; +- +-&ipu_di1_disp1 { +- remote-endpoint = <&display1_in>; +-}; +- +-&pmic { +- fsl,mc13xxx-uses-touch; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-kp-hsc.dts b/scripts/dtc/include-prefixes/arm/imx53-kp-hsc.dts +deleted file mode 100644 +index 6e3d71baac0f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-kp-hsc.dts ++++ /dev/null +@@ -1,52 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2018 +- * Lukasz Majewski, DENX Software Engineering, lukma@denx.de +- */ +- +-/dts-v1/; +-#include "imx53-kp.dtsi" +- +-/ { +- model = "K+P imx53 HSC"; +- compatible = "kiebackpeter,imx53-hsc", "fsl,imx53"; +-}; +- +-&fec { +- status = "okay"; +- +- fixed-link { /* RMII fixed link to LAN9303 */ +- speed = <100>; +- full-duplex; +- }; +-}; +- +-&i2c3 { +- switch: switch@a { +- compatible = "smsc,lan9303-i2c"; +- reg = <0xa>; +- reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; +- reset-duration = <400>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { /* RMII fixed link to master */ +- reg = <0>; +- label = "cpu"; +- ethernet = <&fec>; +- }; +- +- port@1 { /* external port 1 */ +- reg = <1>; +- label = "lan1"; +- }; +- +- port@2 { /* external port 2 */ +- reg = <2>; +- label = "lan2"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-kp.dtsi b/scripts/dtc/include-prefixes/arm/imx53-kp.dtsi +deleted file mode 100644 +index 4508f34139a0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-kp.dtsi ++++ /dev/null +@@ -1,197 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2018 +- * Lukasz Majewski, DENX Software Engineering, lukma@denx.de +- */ +- +-/dts-v1/; +-#include "imx53-tqma53.dtsi" +-#include +- +-/ { +- buzzer { +- compatible = "pwm-beeper"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_buzzer>; +- pwms = <&pwm1 0 500000>; +- }; +- +- gpio-buttons { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpiobuttons>; +- +- button-kalt { +- label = "Kaltstart"; +- linux,code = ; +- gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; +- }; +- +- button-pwr { +- label = "PowerFailInterrupt"; +- linux,code = ; +- gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds>; +- +- led-bus { +- label = "bus"; +- gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "gpio"; +- default-state = "off"; +- }; +- +- led-error { +- label = "error"; +- gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "gpio"; +- default-state = "off"; +- }; +- +- led-flash { +- label = "flash"; +- gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&can2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +- +- gpio-expander1@22 { +- compatible = "nxp,pcf8574"; +- reg = <0x22>; +- interrupts = <109>; +- #gpio-cells = <2>; +- gpio-controller; +- }; +- +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_kp_common>; +- +- imx53-kp-common { +- pinctrl_buzzer: buzzergrp { +- fsl,pins = < +- MX53_PAD_SD1_DATA3__PWM1_PWMO 0x1e4 +- >; +- }; +- +- pinctrl_gpiobuttons: gpiobuttonsgrp { +- fsl,pins = < +- MX53_PAD_EIM_RW__GPIO2_26 0x1e4 +- MX53_PAD_EIM_D22__GPIO3_22 0x1e4 +- >; +- }; +- +- pinctrl_kp_common: kpcommongrp { +- fsl,pins = < +- MX53_PAD_EIM_CS0__GPIO2_23 0x1e4 +- MX53_PAD_GPIO_19__GPIO4_5 0x1e4 +- MX53_PAD_PATA_DATA6__GPIO2_6 0x1e4 +- MX53_PAD_PATA_DATA7__GPIO2_7 0xe0 +- MX53_PAD_CSI0_DAT14__GPIO6_0 0x1e4 +- MX53_PAD_CSI0_DAT16__GPIO6_2 0x1e4 +- MX53_PAD_CSI0_DAT18__GPIO6_4 0x1e4 +- MX53_PAD_EIM_D17__GPIO3_17 0x1e4 +- MX53_PAD_EIM_D18__GPIO3_18 0x1e4 +- MX53_PAD_EIM_D21__GPIO3_21 0x1e4 +- MX53_PAD_EIM_D29__GPIO3_29 0x1e4 +- MX53_PAD_EIM_DA11__GPIO3_11 0x1e4 +- MX53_PAD_EIM_DA13__GPIO3_13 0x1e4 +- MX53_PAD_EIM_DA14__GPIO3_14 0x1e4 +- MX53_PAD_SD1_DATA0__GPIO1_16 0x1e4 +- MX53_PAD_SD1_CMD__GPIO1_18 0x1e4 +- MX53_PAD_SD1_CLK__GPIO1_20 0x1e4 +- >; +- }; +- +- pinctrl_leds: ledgrp { +- fsl,pins = < +- MX53_PAD_EIM_EB2__GPIO2_30 0x1d4 +- MX53_PAD_EIM_D28__GPIO3_28 0x1d4 +- MX53_PAD_EIM_WAIT__GPIO5_0 0x1d4 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x1e4 +- MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x1e4 +- >; +- }; +- }; +-}; +- +-&pinctrl_uart1 { +- fsl,pins = < +- MX53_PAD_EIM_D23__GPIO3_23 0x1e4 +- MX53_PAD_EIM_EB3__GPIO2_31 0x1e4 +- MX53_PAD_EIM_D24__GPIO3_24 0x1e4 +- MX53_PAD_EIM_D25__GPIO3_25 0x1e4 +- MX53_PAD_EIM_D19__GPIO3_19 0x1e4 +- MX53_PAD_EIM_D20__GPIO3_20 0x1e4 +- >; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +-}; +- +-&pwm2 { +- #pwm-cells = <2>; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbphy0 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-m53.dtsi b/scripts/dtc/include-prefixes/arm/imx53-m53.dtsi +deleted file mode 100644 +index fe5e0d308e99..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-m53.dtsi ++++ /dev/null +@@ -1,132 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2014 Marek Vasut +- */ +- +-#include "imx53.dtsi" +- +-/ { +- model = "Aries/DENX M53"; +- compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53"; +- +- memory@70000000 { +- device_type = "memory"; +- reg = <0x70000000 0x20000000>, +- <0xb0000000 0x20000000>; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_3p2v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "3P2V"; +- regulator-min-microvolt = <3200000>; +- regulator-max-microvolt = <3200000>; +- regulator-always-on; +- }; +- +- reg_backlight: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "lcd-supply"; +- regulator-min-microvolt = <3200000>; +- regulator-max-microvolt = <3200000>; +- regulator-always-on; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clock-frequency = <400000>; +- status = "okay"; +- +- touchscreen@41 { +- compatible = "st,stmpe610"; +- reg = <0x41>; +- id = <0>; +- blocks = <0x5>; +- interrupts = <6 0x0>; +- interrupt-parent = <&gpio7>; +- irq-trigger = <0x1>; +- +- stmpe_touchscreen { +- compatible = "st,stmpe-ts"; +- st,sample-time = <4>; +- st,mod-12b = <1>; +- st,ref-sel = <0>; +- st,adc-freq = <1>; +- st,ave-ctrl = <3>; +- st,touch-det-delay = <3>; +- st,settling = <4>; +- st,fraction-z = <7>; +- st,i-drive = <1>; +- }; +- }; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c128"; +- reg = <0x50>; +- pagesize = <32>; +- }; +- +- rtc: rtc@68 { +- compatible = "st,m41t62"; +- reg = <0x68>; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx53-m53evk { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 +- MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 +- MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 +- MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 +- >; +- }; +- +- pinctrl_nand: nandgrp { +- fsl,pins = < +- MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 +- MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 +- MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 +- MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 +- MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 +- MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 +- MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 +- MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 +- MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 +- MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 +- MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 +- MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 +- MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 +- MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 +- MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 +- >; +- }; +- }; +-}; +- +-&nfc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nand>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-m53evk.dts b/scripts/dtc/include-prefixes/arm/imx53-m53evk.dts +deleted file mode 100644 +index a1a6228d1aa6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-m53evk.dts ++++ /dev/null +@@ -1,371 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2013 Marek Vasut +- */ +- +-/dts-v1/; +-#include "imx53-m53.dtsi" +- +-/ { +- model = "Aries/DENX M53EVK"; +- compatible = "aries,imx53-m53evk", "denx,imx53-m53evk", "fsl,imx53"; +- +- display1: disp1 { +- compatible = "fsl,imx-parallel-display"; +- interface-pix-fmt = "bgr666"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu_disp1>; +- +- display-timings { +- 800x480p60 { +- native-mode; +- clock-frequency = <31500000>; +- hactive = <800>; +- vactive = <480>; +- hfront-porch = <40>; +- hback-porch = <88>; +- hsync-len = <128>; +- vback-porch = <33>; +- vfront-porch = <9>; +- vsync-len = <3>; +- vsync-active = <1>; +- }; +- }; +- +- port { +- display1_in: endpoint { +- remote-endpoint = <&ipu_di1_disp1>; +- }; +- }; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 3000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- power-supply = <®_backlight>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pin_gpio>; +- +- user1 { +- label = "user1"; +- gpios = <&gpio2 8 0>; +- linux,default-trigger = "heartbeat"; +- }; +- +- user2 { +- label = "user2"; +- gpios = <&gpio2 9 0>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_usbh1_vbus: regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- regulator-name = "vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 2 0>; +- }; +- +- reg_usb_otg_vbus: regulator@4 { +- compatible = "regulator-fixed"; +- reg = <4>; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 4 0>; +- }; +- }; +- +- sound { +- compatible = "fsl,imx53-m53evk-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "imx53-m53evk-sgtl5000"; +- ssi-controller = <&ssi2>; +- audio-codec = <&sgtl5000>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "LINE_IN", "Line In Jack", +- "Headphone Jack", "HP_OUT", +- "Ext Spk", "LINE_OUT"; +- mux-int-port = <2>; +- mux-ext-port = <4>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can2>; +- status = "okay"; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-mode = "rmii"; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- VDDA-supply = <®_3p2v>; +- VDDIO-supply = <®_3p2v>; +- clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; +- }; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx53-m53evk { +- pinctrl_usb: usbgrp { +- fsl,pins = < +- MX53_PAD_GPIO_2__GPIO1_2 0x80000000 +- MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX53_PAD_GPIO_4__GPIO1_4 0x000b0 +- >; +- }; +- +- led_pin_gpio: led_gpio { +- fsl,pins = < +- MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000 +- MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000 +- >; +- }; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000 +- MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000 +- MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000 +- MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000 +- >; +- }; +- +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 +- MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 +- >; +- }; +- +- pinctrl_can2: can2grp { +- fsl,pins = < +- MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 +- MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 +- MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 +- MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 +- MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 +- MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 +- MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 +- MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 +- MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 +- MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 +- MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 +- MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 +- MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 +- MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 +- MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 +- MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 +- MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 +- MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 +- >; +- }; +- +- pinctrl_ipu_disp1: ipudisp1grp { +- fsl,pins = < +- MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5 +- MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5 +- MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5 +- MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5 +- MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5 +- MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5 +- MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5 +- MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5 +- MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5 +- MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5 +- MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5 +- MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5 +- MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5 +- MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5 +- MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5 +- MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5 +- MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5 +- MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5 +- MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5 +- MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5 +- MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5 +- MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5 +- MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5 +- MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5 +- MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5 +- MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5 +- MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5 +- MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5 +- MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5 +- MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5 +- MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5 +- MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 +- MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 +- MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 +- MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 +- MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 +- MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 +- >; +- }; +- }; +-}; +- +-&ipu_di1_disp1 { +- remote-endpoint = <&display1_in>; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&ssi2 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&usbh1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb>; +- vbus-supply = <®_usbh1_vbus>; +- phy_type = "utmi"; +- status = "okay"; +-}; +- +-&usbotg { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- dr_mode = "otg"; +- vbus-supply = <®_usb_otg_vbus>; +- disable-over-current; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-m53menlo.dts b/scripts/dtc/include-prefixes/arm/imx53-m53menlo.dts +deleted file mode 100644 +index 4f88e96d81dd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-m53menlo.dts ++++ /dev/null +@@ -1,492 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 Marek Vasut +- */ +- +-/dts-v1/; +-#include "imx53-m53.dtsi" +- +-/ { +- model = "MENLO M53 EMBEDDED DEVICE"; +- compatible = "menlo,m53menlo", "fsl,imx53"; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&pinctrl_power_button>; +- pinctrl-names = "default"; +- +- power-button { +- label = "Power button"; +- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- pinctrl-0 = <&pinctrl_power_out>; +- pinctrl-names = "default"; +- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led>; +- +- user1 { +- label = "TestLed601"; +- gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- }; +- +- user2 { +- label = "TestLed602"; +- gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- eth { +- label = "EthLedYe"; +- gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "netdev"; +- }; +- }; +- +- panel { +- compatible = "edt,etm0700g0dh6"; +- pinctrl-0 = <&pinctrl_display_gpio>; +- pinctrl-names = "default"; +- enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +- +- beeper { +- compatible = "gpio-beeper"; +- pinctrl-0 = <&pinctrl_beeper>; +- gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_usbh1_vbus: regulator-usbh1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 2 0>; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can2>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX5_CLK_CKO1_SEL>, +- <&clks IMX5_CLK_CKO1_PODF>, +- <&clks IMX5_CLK_CKO1>; +- assigned-clock-parents = <&clks IMX5_CLK_AHB>; +- assigned-clock-rates = <133333334>, <33333334>, <33333334>; +-}; +- +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio2 27 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- spidev@0 { +- compatible = "menlo,m53cpld"; +- spi-max-frequency = <25000000>; +- reg = <0>; +- }; +- +- spidev@1 { +- compatible = "menlo,m53cpld"; +- spi-max-frequency = <25000000>; +- reg = <1>; +- }; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-mode = "rmii"; +- phy-reset-gpios = <&gpio7 7 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&gpio1 { +- gpio-line-names = +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", ""; +-}; +- +-&gpio2 { +- gpio-line-names = +- "", "", "", "", +- "", "", "", "", +- "TestPin_SV2_3", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", ""; +-}; +- +-&gpio3 { +- gpio-line-names = +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "CPLD_JTAG_TDI", "CPLD_JTAG_TMS", "", "", +- "", "CPLD_JTAG_TDO", "", ""; +-}; +- +-&gpio5 { +- gpio-line-names = +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "CPLD_JTAG_TCK", "KBD_intK", +- "CPLD_int", "CPLD_JTAG_internal", "CPLD_D[0]", "CPLD_D[1]", +- "CPLD_D[2]", "CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", +- "CPLD_D[6]", "CPLD_D[7]", "DISP_reset", "KBD_intI"; +-}; +- +-&gpio6 { +- gpio-line-names = +- "", "", "", "", +- "CPLD_reset", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", ""; +-}; +- +-&gpio7 { +- gpio-line-names = +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "USB-OTG_OverCurrent", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "", "", "", ""; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- touchscreen@38 { +- compatible = "edt,edt-ft5x06"; +- reg = <0x38>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_edt_ft5x06>; +- interrupt-parent = <&gpio6>; +- interrupts = <5 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; +- wake-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- pagesize = <32>; +- }; +- +- dac@60 { +- compatible = "microchip,mcp4725"; +- reg = <0x60>; +- }; +-}; +- +-&i2c2 { +- touchscreen@41 { +- status = "disabled"; +- }; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx53-m53evk { +- hoggrp { +- fsl,pins = < +- MX53_PAD_GPIO_19__CCM_CLKO 0x1e4 +- MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1e4 +- MX53_PAD_CSI0_DAT4__GPIO5_22 0x1e4 +- MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4 +- MX53_PAD_CSI0_DAT6__GPIO5_24 0x1e4 +- MX53_PAD_CSI0_DAT7__GPIO5_25 0x1e4 +- MX53_PAD_CSI0_DAT8__GPIO5_26 0x1e4 +- MX53_PAD_CSI0_DAT9__GPIO5_27 0x1c4 +- MX53_PAD_CSI0_DAT10__GPIO5_28 0x1e4 +- MX53_PAD_CSI0_DAT11__GPIO5_29 0x1e4 +- MX53_PAD_PATA_DATA11__GPIO2_11 0x1e4 +- MX53_PAD_EIM_D24__GPIO3_24 0x1e4 +- MX53_PAD_EIM_D25__GPIO3_25 0x1e4 +- MX53_PAD_EIM_D29__GPIO3_29 0x1e4 +- MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1e4 +- MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1e4 +- MX53_PAD_CSI0_DAT18__GPIO6_4 0x1c4 +- MX53_PAD_PATA_DATA8__GPIO2_8 0x1e4 +- >; +- }; +- +- pinctrl_led: ledgrp { +- fsl,pins = < +- MX53_PAD_CSI0_DAT15__GPIO6_1 0x1c4 +- MX53_PAD_CSI0_DAT16__GPIO6_2 0x1c4 +- >; +- }; +- +- pinctrl_beeper: beepergrp { +- fsl,pins = < +- MX53_PAD_CSI0_DAT17__GPIO6_3 0x1c4 +- >; +- }; +- +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX53_PAD_GPIO_7__CAN1_TXCAN 0x1c4 +- MX53_PAD_GPIO_8__CAN1_RXCAN 0x1c4 +- >; +- }; +- +- pinctrl_can2: can2grp { +- fsl,pins = < +- MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1e4 +- MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4 +- >; +- }; +- +- pinctrl_display_gpio: display-gpiogrp { +- fsl,pins = < +- MX53_PAD_CSI0_DAT12__GPIO5_30 0x1c4 /* Reset */ +- MX53_PAD_CSI0_MCLK__GPIO5_19 0x1e4 /* Int-K */ +- MX53_PAD_CSI0_DAT13__GPIO5_31 0x1c4 /* Int-I */ +- +- MX53_PAD_CSI0_DAT14__GPIO6_0 0x1c4 /* Power down */ +- >; +- }; +- +- pinctrl_edt_ft5x06: edt-ft5x06grp { +- fsl,pins = < +- MX53_PAD_PATA_DATA9__GPIO2_9 0x1e4 /* Reset */ +- MX53_PAD_CSI0_DAT19__GPIO6_5 0x1c4 /* Interrupt */ +- MX53_PAD_PATA_DATA10__GPIO2_10 0x1e4 /* Wake */ +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX53_PAD_EIM_CS0__ECSPI2_SCLK 0xe4 +- MX53_PAD_EIM_OE__ECSPI2_MISO 0xe4 +- MX53_PAD_EIM_CS1__ECSPI2_MOSI 0xe4 +- MX53_PAD_EIM_RW__GPIO2_26 0xe4 +- MX53_PAD_EIM_LBA__GPIO2_27 0xe4 +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1e4 +- MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1e4 +- MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1e4 +- MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1e4 +- MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 +- MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1e4 +- MX53_PAD_GPIO_1__GPIO1_1 0x1c4 +- MX53_PAD_GPIO_9__GPIO1_9 0x1e4 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX53_PAD_FEC_MDC__FEC_MDC 0x1e4 +- MX53_PAD_FEC_MDIO__FEC_MDIO 0x1e4 +- MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x1e4 +- MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1e4 +- MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x1e4 +- MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x1e4 +- MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x1e4 +- MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x1c4 +- MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x1e4 +- MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x1e4 +- MX53_PAD_PATA_DA_1__GPIO7_7 0x1e4 +- MX53_PAD_EIM_EB3__GPIO2_31 0x1e4 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 +- MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 +- MX53_PAD_GPIO_5__I2C3_SCL 0x400001e4 +- >; +- }; +- +- pinctrl_lvds0: lvds0grp { +- /* LVDS pins only have pin mux configuration */ +- fsl,pins = < +- MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 +- MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 +- MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 +- MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 +- MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 +- >; +- }; +- +- pinctrl_power_button: powerbutgrp { +- fsl,pins = < +- MX53_PAD_SD2_DATA0__GPIO1_15 0x1e4 +- >; +- }; +- +- pinctrl_power_out: poweroutgrp { +- fsl,pins = < +- MX53_PAD_SD2_DATA2__GPIO1_13 0x1e4 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 +- MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 +- MX53_PAD_PATA_IORDY__UART1_RTS 0x1e4 +- MX53_PAD_PATA_RESET_B__UART1_CTS 0x1e4 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 +- MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 +- MX53_PAD_PATA_DIOR__UART2_RTS 0x1e4 +- MX53_PAD_PATA_INTRQ__UART2_CTS 0x1e4 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 +- MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 +- MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 +- >; +- }; +- +- pinctrl_usb: usbgrp { +- fsl,pins = < +- MX53_PAD_GPIO_2__GPIO1_2 0x1c4 +- MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1c4 +- MX53_PAD_GPIO_4__GPIO1_4 0x1c4 +- MX53_PAD_GPIO_18__GPIO7_13 0x1c4 +- >; +- }; +- }; +-}; +- +-&ldb { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lvds0>; +- status = "okay"; +- +- lvds0: lvds-channel@0 { +- reg = <0>; +- fsl,data-mapping = "spwg"; +- fsl,data-width = <18>; +- status = "okay"; +- +- port@2 { +- reg = <2>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- linux,rs485-enabled-at-boot-time; +- status = "okay"; +-}; +- +-&usbh1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb>; +- vbus-supply = <®_usbh1_vbus>; +- phy_type = "utmi"; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbotg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-mba53.dts b/scripts/dtc/include-prefixes/arm/imx53-mba53.dts +deleted file mode 100644 +index 09eee0dd44c1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-mba53.dts ++++ /dev/null +@@ -1,249 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Sascha Hauer , Pengutronix +- * Copyright 2012 Steffen Trumtrar , Pengutronix +- */ +- +-/dts-v1/; +-#include "imx53-tqma53.dtsi" +- +-/ { +- model = "TQ MBa53 starter kit"; +- compatible = "tq,mba53", "tq,tqma53", "fsl,imx53"; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm2 0 50000>; +- brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>; +- default-brightness-level = <10>; +- enable-gpios = <&gpio7 7 0>; +- power-supply = <®_backlight>; +- }; +- +- disp1: disp1 { +- compatible = "fsl,imx-parallel-display"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_disp1_1>; +- interface-pix-fmt = "rgb24"; +- status = "disabled"; +- +- port { +- display1_in: endpoint { +- remote-endpoint = <&ipu_di1_disp1>; +- }; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_backlight: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "lcd-supply"; +- gpio = <&gpio2 5 0>; +- startup-delay-us = <5000>; +- }; +- +- reg_3p2v: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "3P2V"; +- regulator-min-microvolt = <3200000>; +- regulator-max-microvolt = <3200000>; +- regulator-always-on; +- }; +- }; +- +- sound { +- compatible = "tq,imx53-mba53-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "imx53-mba53-sgtl5000"; +- ssi-controller = <&ssi2>; +- audio-codec = <&codec>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <2>; +- mux-ext-port = <5>; +- }; +-}; +- +-&ldb { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lvds1_1>; +- status = "disabled"; +-}; +- +-&iomuxc { +- lvds1 { +- pinctrl_lvds1_1: lvds1-grp1 { +- fsl,pins = < +- MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 +- MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 +- MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 +- MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 +- MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 +- >; +- }; +- +- pinctrl_lvds1_2: lvds1-grp2 { +- fsl,pins = < +- MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 +- MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 +- MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 +- MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 +- MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 +- >; +- }; +- }; +- +- disp1 { +- pinctrl_disp1_1: disp1-grp1 { +- fsl,pins = < +- MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */ +- MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */ +- MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */ +- MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */ +- MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000 +- MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000 +- MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000 +- MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000 +- MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000 +- MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000 +- MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000 +- MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000 +- MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000 +- MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000 +- MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000 +- MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000 +- MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000 +- MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000 +- MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000 +- MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000 +- MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000 +- MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000 +- MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000 +- MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000 +- MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000 +- MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000 +- MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000 +- MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000 +- >; +- }; +- }; +- +- tve { +- pinctrl_vga_sync_1: vgasync-grp1 { +- fsl,pins = < +- /* VGA_VSYNC, HSYNC with max drive strength */ +- MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6 +- MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6 +- >; +- }; +- }; +-}; +- +-&ipu_di1_disp1 { +- remote-endpoint = <&display1_in>; +-}; +- +-&cspi { +- status = "okay"; +-}; +- +-&audmux { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +-}; +- +-&i2c2 { +- codec: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; +- VDDA-supply = <®_3p2v>; +- VDDIO-supply = <®_3p2v>; +- }; +- +- expander: pca9554@20 { +- compatible = "pca9554"; +- reg = <0x20>; +- interrupts = <109>; +- #gpio-cells = <2>; +- gpio-controller; +- }; +- +- sensor2: lm75@49 { +- compatible = "lm75"; +- reg = <0x49>; +- }; +-}; +- +-&fec { +- phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&esdhc2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&ecspi1 { +- status = "okay"; +-}; +- +-&usbotg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&ssi2 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&can2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&tve { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_vga_sync_1>; +- ddc-i2c-bus = <&i2c3>; +- fsl,tve-mode = "vga"; +- fsl,hsync-pin = <4>; +- fsl,vsync-pin = <6>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-pinfunc.h b/scripts/dtc/include-prefixes/arm/imx53-pinfunc.h +deleted file mode 100644 +index 67bd06610fdf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-pinfunc.h ++++ /dev/null +@@ -1,1189 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __DTS_IMX53_PINFUNC_H +-#define __DTS_IMX53_PINFUNC_H +- +-/* +- * The pin function ID is a tuple of +- * +- */ +-#define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0 +-#define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0 +-#define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0 +-#define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0 +-#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0 +-#define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0 +-#define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0 +-#define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0 +-#define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0 +-#define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0 +-#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x024 0x34c 0x758 0x2 0x0 +-#define MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x024 0x34c 0x000 0x4 0x0 +-#define MX53_PAD_KEY_COL0__ECSPI1_SCLK 0x024 0x34c 0x79c 0x5 0x0 +-#define MX53_PAD_KEY_COL0__FEC_RDATA_3 0x024 0x34c 0x000 0x6 0x0 +-#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST 0x024 0x34c 0x000 0x7 0x0 +-#define MX53_PAD_KEY_ROW0__KPP_ROW_0 0x028 0x350 0x000 0x0 0x0 +-#define MX53_PAD_KEY_ROW0__GPIO4_7 0x028 0x350 0x000 0x1 0x0 +-#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x028 0x350 0x74c 0x2 0x0 +-#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x028 0x350 0x890 0x4 0x1 +-#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI 0x028 0x350 0x7a4 0x5 0x0 +-#define MX53_PAD_KEY_ROW0__FEC_TX_ER 0x028 0x350 0x000 0x6 0x0 +-#define MX53_PAD_KEY_COL1__KPP_COL_1 0x02c 0x354 0x000 0x0 0x0 +-#define MX53_PAD_KEY_COL1__GPIO4_8 0x02c 0x354 0x000 0x1 0x0 +-#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x02c 0x354 0x75c 0x2 0x0 +-#define MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x02c 0x354 0x000 0x4 0x0 +-#define MX53_PAD_KEY_COL1__ECSPI1_MISO 0x02c 0x354 0x7a0 0x5 0x0 +-#define MX53_PAD_KEY_COL1__FEC_RX_CLK 0x02c 0x354 0x808 0x6 0x0 +-#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY 0x02c 0x354 0x000 0x7 0x0 +-#define MX53_PAD_KEY_ROW1__KPP_ROW_1 0x030 0x358 0x000 0x0 0x0 +-#define MX53_PAD_KEY_ROW1__GPIO4_9 0x030 0x358 0x000 0x1 0x0 +-#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x030 0x358 0x748 0x2 0x0 +-#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x030 0x358 0x898 0x4 0x1 +-#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 0x030 0x358 0x7a8 0x5 0x0 +-#define MX53_PAD_KEY_ROW1__FEC_COL 0x030 0x358 0x800 0x6 0x0 +-#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID 0x030 0x358 0x000 0x7 0x0 +-#define MX53_PAD_KEY_COL2__KPP_COL_2 0x034 0x35c 0x000 0x0 0x0 +-#define MX53_PAD_KEY_COL2__GPIO4_10 0x034 0x35c 0x000 0x1 0x0 +-#define MX53_PAD_KEY_COL2__CAN1_TXCAN 0x034 0x35c 0x000 0x2 0x0 +-#define MX53_PAD_KEY_COL2__FEC_MDIO 0x034 0x35c 0x804 0x4 0x0 +-#define MX53_PAD_KEY_COL2__ECSPI1_SS1 0x034 0x35c 0x7ac 0x5 0x0 +-#define MX53_PAD_KEY_COL2__FEC_RDATA_2 0x034 0x35c 0x000 0x6 0x0 +-#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE 0x034 0x35c 0x000 0x7 0x0 +-#define MX53_PAD_KEY_ROW2__KPP_ROW_2 0x038 0x360 0x000 0x0 0x0 +-#define MX53_PAD_KEY_ROW2__GPIO4_11 0x038 0x360 0x000 0x1 0x0 +-#define MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x038 0x360 0x760 0x2 0x0 +-#define MX53_PAD_KEY_ROW2__FEC_MDC 0x038 0x360 0x000 0x4 0x0 +-#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 0x038 0x360 0x7b0 0x5 0x0 +-#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x038 0x360 0x000 0x6 0x0 +-#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR 0x038 0x360 0x000 0x7 0x0 +-#define MX53_PAD_KEY_COL3__KPP_COL_3 0x03c 0x364 0x000 0x0 0x0 +-#define MX53_PAD_KEY_COL3__GPIO4_12 0x03c 0x364 0x000 0x1 0x0 +-#define MX53_PAD_KEY_COL3__USBOH3_H2_DP 0x03c 0x364 0x000 0x2 0x0 +-#define MX53_PAD_KEY_COL3__SPDIF_IN1 0x03c 0x364 0x870 0x3 0x0 +-#define MX53_PAD_KEY_COL3__I2C2_SCL 0x03c 0x364 0x81c 0x4 0x0 +-#define MX53_PAD_KEY_COL3__ECSPI1_SS3 0x03c 0x364 0x7b4 0x5 0x0 +-#define MX53_PAD_KEY_COL3__FEC_CRS 0x03c 0x364 0x000 0x6 0x0 +-#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK 0x03c 0x364 0x000 0x7 0x0 +-#define MX53_PAD_KEY_ROW3__KPP_ROW_3 0x040 0x368 0x000 0x0 0x0 +-#define MX53_PAD_KEY_ROW3__GPIO4_13 0x040 0x368 0x000 0x1 0x0 +-#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM 0x040 0x368 0x000 0x2 0x0 +-#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 0x040 0x368 0x768 0x3 0x0 +-#define MX53_PAD_KEY_ROW3__I2C2_SDA 0x040 0x368 0x820 0x4 0x0 +-#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT 0x040 0x368 0x000 0x5 0x0 +-#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP 0x040 0x368 0x77c 0x6 0x0 +-#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 0x040 0x368 0x000 0x7 0x0 +-#define MX53_PAD_KEY_COL4__KPP_COL_4 0x044 0x36c 0x000 0x0 0x0 +-#define MX53_PAD_KEY_COL4__GPIO4_14 0x044 0x36c 0x000 0x1 0x0 +-#define MX53_PAD_KEY_COL4__CAN2_TXCAN 0x044 0x36c 0x000 0x2 0x0 +-#define MX53_PAD_KEY_COL4__IPU_SISG_4 0x044 0x36c 0x000 0x3 0x0 +-#define MX53_PAD_KEY_COL4__UART5_RTS 0x044 0x36c 0x894 0x4 0x0 +-#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x044 0x36c 0x89c 0x5 0x0 +-#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 0x044 0x36c 0x000 0x7 0x0 +-#define MX53_PAD_KEY_ROW4__KPP_ROW_4 0x048 0x370 0x000 0x0 0x0 +-#define MX53_PAD_KEY_ROW4__GPIO4_15 0x048 0x370 0x000 0x1 0x0 +-#define MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x048 0x370 0x764 0x2 0x0 +-#define MX53_PAD_KEY_ROW4__IPU_SISG_5 0x048 0x370 0x000 0x3 0x0 +-#define MX53_PAD_KEY_ROW4__UART5_CTS 0x048 0x370 0x000 0x4 0x0 +-#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 0x048 0x370 0x000 0x5 0x0 +-#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID 0x048 0x370 0x000 0x7 0x0 +-#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x04c 0x378 0x000 0x0 0x0 +-#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 0x04c 0x378 0x000 0x1 0x0 +-#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x04c 0x378 0x000 0x2 0x0 +-#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 0x04c 0x378 0x000 0x5 0x0 +-#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 0x04c 0x378 0x000 0x6 0x0 +-#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID 0x04c 0x378 0x000 0x7 0x0 +-#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x050 0x37c 0x000 0x0 0x0 +-#define MX53_PAD_DI0_PIN15__GPIO4_17 0x050 0x37c 0x000 0x1 0x0 +-#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x050 0x37c 0x000 0x2 0x0 +-#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 0x050 0x37c 0x000 0x5 0x0 +-#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 0x050 0x37c 0x000 0x6 0x0 +-#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID 0x050 0x37c 0x000 0x7 0x0 +-#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x054 0x380 0x000 0x0 0x0 +-#define MX53_PAD_DI0_PIN2__GPIO4_18 0x054 0x380 0x000 0x1 0x0 +-#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x054 0x380 0x000 0x2 0x0 +-#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 0x054 0x380 0x000 0x5 0x0 +-#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 0x054 0x380 0x000 0x6 0x0 +-#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION 0x054 0x380 0x000 0x7 0x0 +-#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x058 0x384 0x000 0x0 0x0 +-#define MX53_PAD_DI0_PIN3__GPIO4_19 0x058 0x384 0x000 0x1 0x0 +-#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x058 0x384 0x000 0x2 0x0 +-#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 0x058 0x384 0x000 0x5 0x0 +-#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 0x058 0x384 0x000 0x6 0x0 +-#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG 0x058 0x384 0x000 0x7 0x0 +-#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x05c 0x388 0x000 0x0 0x0 +-#define MX53_PAD_DI0_PIN4__GPIO4_20 0x05c 0x388 0x000 0x1 0x0 +-#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x05c 0x388 0x000 0x2 0x0 +-#define MX53_PAD_DI0_PIN4__ESDHC1_WP 0x05c 0x388 0x7fc 0x3 0x0 +-#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 0x05c 0x388 0x000 0x5 0x0 +-#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 0x05c 0x388 0x000 0x6 0x0 +-#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT 0x05c 0x388 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x060 0x38c 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT0__GPIO4_21 0x060 0x38c 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT0__CSPI_SCLK 0x060 0x38c 0x780 0x2 0x0 +-#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x060 0x38c 0x000 0x3 0x0 +-#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN 0x060 0x38c 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 0x060 0x38c 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY 0x060 0x38c 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x064 0x390 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT1__GPIO4_22 0x064 0x390 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT1__CSPI_MOSI 0x064 0x390 0x788 0x2 0x0 +-#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x064 0x390 0x000 0x3 0x0 +-#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x064 0x390 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 0x064 0x390 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID 0x064 0x390 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x068 0x394 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT2__GPIO4_23 0x068 0x394 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT2__CSPI_MISO 0x068 0x394 0x784 0x2 0x0 +-#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x068 0x394 0x000 0x3 0x0 +-#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 0x068 0x394 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 0x068 0x394 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE 0x068 0x394 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x06c 0x398 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT3__GPIO4_24 0x06c 0x398 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT3__CSPI_SS0 0x06c 0x398 0x78c 0x2 0x0 +-#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x06c 0x398 0x000 0x3 0x0 +-#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR 0x06c 0x398 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 0x06c 0x398 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR 0x06c 0x398 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x070 0x39c 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT4__GPIO4_25 0x070 0x39c 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT4__CSPI_SS1 0x070 0x39c 0x790 0x2 0x0 +-#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x070 0x39c 0x000 0x3 0x0 +-#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 0x070 0x39c 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 0x070 0x39c 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK 0x070 0x39c 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x074 0x3a0 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT5__GPIO4_26 0x074 0x3a0 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT5__CSPI_SS2 0x074 0x3a0 0x794 0x2 0x0 +-#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x074 0x3a0 0x000 0x3 0x0 +-#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS 0x074 0x3a0 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 0x074 0x3a0 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 0x074 0x3a0 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x078 0x3a4 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT6__GPIO4_27 0x078 0x3a4 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT6__CSPI_SS3 0x078 0x3a4 0x798 0x2 0x0 +-#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x078 0x3a4 0x000 0x3 0x0 +-#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE 0x078 0x3a4 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 0x078 0x3a4 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 0x078 0x3a4 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x07c 0x3a8 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT7__GPIO4_28 0x07c 0x3a8 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT7__CSPI_RDY 0x07c 0x3a8 0x000 0x2 0x0 +-#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x07c 0x3a8 0x000 0x3 0x0 +-#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 0x07c 0x3a8 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 0x07c 0x3a8 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID 0x07c 0x3a8 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x080 0x3ac 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT8__GPIO4_29 0x080 0x3ac 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x080 0x3ac 0x000 0x2 0x0 +-#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B 0x080 0x3ac 0x000 0x3 0x0 +-#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 0x080 0x3ac 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 0x080 0x3ac 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID 0x080 0x3ac 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x084 0x3b0 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT9__GPIO4_30 0x084 0x3b0 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x084 0x3b0 0x000 0x2 0x0 +-#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B 0x084 0x3b0 0x000 0x3 0x0 +-#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 0x084 0x3b0 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 0x084 0x3b0 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 0x084 0x3b0 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x088 0x3b4 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT10__GPIO4_31 0x088 0x3b4 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x088 0x3b4 0x000 0x2 0x0 +-#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 0x088 0x3b4 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 0x088 0x3b4 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 0x088 0x3b4 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x08c 0x3b8 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT11__GPIO5_5 0x08c 0x3b8 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x08c 0x3b8 0x000 0x2 0x0 +-#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 0x08c 0x3b8 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 0x08c 0x3b8 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 0x08c 0x3b8 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x090 0x3bc 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT12__GPIO5_6 0x090 0x3bc 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x090 0x3bc 0x000 0x2 0x0 +-#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 0x090 0x3bc 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 0x090 0x3bc 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 0x090 0x3bc 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x094 0x3c0 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT13__GPIO5_7 0x094 0x3c0 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 0x094 0x3c0 0x754 0x3 0x0 +-#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 0x094 0x3c0 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 0x094 0x3c0 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 0x094 0x3c0 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x098 0x3c4 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT14__GPIO5_8 0x098 0x3c4 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 0x098 0x3c4 0x750 0x3 0x0 +-#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 0x098 0x3c4 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 0x098 0x3c4 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 0x098 0x3c4 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x09c 0x3c8 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT15__GPIO5_9 0x09c 0x3c8 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 0x09c 0x3c8 0x7ac 0x2 0x1 +-#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 0x09c 0x3c8 0x7c8 0x3 0x0 +-#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 0x09c 0x3c8 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 0x09c 0x3c8 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 0x09c 0x3c8 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x0a0 0x3cc 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT16__GPIO5_10 0x0a0 0x3cc 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0a0 0x3cc 0x7c0 0x2 0x0 +-#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 0x0a0 0x3cc 0x758 0x3 0x1 +-#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 0x0a0 0x3cc 0x868 0x4 0x0 +-#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 0x0a0 0x3cc 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 0x0a0 0x3cc 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 0x0a0 0x3cc 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x0a4 0x3d0 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT17__GPIO5_11 0x0a4 0x3d0 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO 0x0a4 0x3d0 0x7bc 0x2 0x0 +-#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 0x0a4 0x3d0 0x74c 0x3 0x1 +-#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 0x0a4 0x3d0 0x86c 0x4 0x0 +-#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 0x0a4 0x3d0 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 0x0a4 0x3d0 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x0a8 0x3d4 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT18__GPIO5_12 0x0a8 0x3d4 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 0x0a8 0x3d4 0x7c4 0x2 0x0 +-#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 0x0a8 0x3d4 0x75c 0x3 0x1 +-#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 0x0a8 0x3d4 0x73c 0x4 0x0 +-#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 0x0a8 0x3d4 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 0x0a8 0x3d4 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 0x0a8 0x3d4 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x0ac 0x3d8 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT19__GPIO5_13 0x0ac 0x3d8 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0ac 0x3d8 0x7b8 0x2 0x0 +-#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 0x0ac 0x3d8 0x748 0x3 0x1 +-#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 0x0ac 0x3d8 0x738 0x4 0x0 +-#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 0x0ac 0x3d8 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 0x0ac 0x3d8 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 0x0ac 0x3d8 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x0b0 0x3dc 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT20__GPIO5_14 0x0b0 0x3dc 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0b0 0x3dc 0x79c 0x2 0x1 +-#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 0x0b0 0x3dc 0x740 0x3 0x0 +-#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 0x0b0 0x3dc 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 0x0b0 0x3dc 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI 0x0b0 0x3dc 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x0b4 0x3e0 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT21__GPIO5_15 0x0b4 0x3e0 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0b4 0x3e0 0x7a4 0x2 0x1 +-#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 0x0b4 0x3e0 0x734 0x3 0x0 +-#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 0x0b4 0x3e0 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 0x0b4 0x3e0 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO 0x0b4 0x3e0 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x0b8 0x3e4 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT22__GPIO5_16 0x0b8 0x3e4 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x0b8 0x3e4 0x7a0 0x2 0x1 +-#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 0x0b8 0x3e4 0x744 0x3 0x0 +-#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 0x0b8 0x3e4 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 0x0b8 0x3e4 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK 0x0b8 0x3e4 0x000 0x7 0x0 +-#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x0bc 0x3e8 0x000 0x0 0x0 +-#define MX53_PAD_DISP0_DAT23__GPIO5_17 0x0bc 0x3e8 0x000 0x1 0x0 +-#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 0x0bc 0x3e8 0x7a8 0x2 0x1 +-#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 0x0bc 0x3e8 0x730 0x3 0x0 +-#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 0x0bc 0x3e8 0x000 0x5 0x0 +-#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 0x0bc 0x3e8 0x000 0x6 0x0 +-#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS 0x0bc 0x3e8 0x000 0x7 0x0 +-#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x0c0 0x3ec 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x0c0 0x3ec 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 0x0c0 0x3ec 0x000 0x5 0x0 +-#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 0x0c0 0x3ec 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x0c4 0x3f0 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_MCLK__GPIO5_19 0x0c4 0x3f0 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x0c4 0x3f0 0x000 0x2 0x0 +-#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 0x0c4 0x3f0 0x000 0x5 0x0 +-#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 0x0c4 0x3f0 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL 0x0c4 0x3f0 0x000 0x7 0x0 +-#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x0c8 0x3f4 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x0c8 0x3f4 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 0x0c8 0x3f4 0x000 0x5 0x0 +-#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 0x0c8 0x3f4 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK 0x0c8 0x3f4 0x000 0x7 0x0 +-#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x0cc 0x3f8 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_VSYNC__GPIO5_21 0x0cc 0x3f8 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 0x0cc 0x3f8 0x000 0x5 0x0 +-#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 0x0cc 0x3f8 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 0x0cc 0x3f8 0x000 0x7 0x0 +-#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x0d0 0x3fc 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_DAT4__GPIO5_22 0x0d0 0x3fc 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_DAT4__KPP_COL_5 0x0d0 0x3fc 0x840 0x2 0x1 +-#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK 0x0d0 0x3fc 0x79c 0x3 0x2 +-#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 0x0d0 0x3fc 0x000 0x4 0x0 +-#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x0d0 0x3fc 0x000 0x5 0x0 +-#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 0x0d0 0x3fc 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 0x0d0 0x3fc 0x000 0x7 0x0 +-#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x0d4 0x400 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_DAT5__GPIO5_23 0x0d4 0x400 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 0x0d4 0x400 0x84c 0x2 0x0 +-#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI 0x0d4 0x400 0x7a4 0x3 0x2 +-#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 0x0d4 0x400 0x000 0x4 0x0 +-#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x0d4 0x400 0x000 0x5 0x0 +-#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 0x0d4 0x400 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 0x0d4 0x400 0x000 0x7 0x0 +-#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x0d8 0x404 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_DAT6__GPIO5_24 0x0d8 0x404 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_DAT6__KPP_COL_6 0x0d8 0x404 0x844 0x2 0x0 +-#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO 0x0d8 0x404 0x7a0 0x3 0x2 +-#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 0x0d8 0x404 0x000 0x4 0x0 +-#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x0d8 0x404 0x000 0x5 0x0 +-#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 0x0d8 0x404 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 0x0d8 0x404 0x000 0x7 0x0 +-#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x0dc 0x408 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_DAT7__GPIO5_25 0x0dc 0x408 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 0x0dc 0x408 0x850 0x2 0x0 +-#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 0x0dc 0x408 0x7a8 0x3 0x2 +-#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 0x0dc 0x408 0x000 0x4 0x0 +-#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x0dc 0x408 0x000 0x5 0x0 +-#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 0x0dc 0x408 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 0x0dc 0x408 0x000 0x7 0x0 +-#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x0e0 0x40c 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_DAT8__GPIO5_26 0x0e0 0x40c 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_DAT8__KPP_COL_7 0x0e0 0x40c 0x848 0x2 0x0 +-#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK 0x0e0 0x40c 0x7b8 0x3 0x1 +-#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 0x0e0 0x40c 0x000 0x4 0x0 +-#define MX53_PAD_CSI0_DAT8__I2C1_SDA 0x0e0 0x40c 0x818 0x5 0x0 +-#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 0x0e0 0x40c 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 0x0e0 0x40c 0x000 0x7 0x0 +-#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x0e4 0x410 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_DAT9__GPIO5_27 0x0e4 0x410 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 0x0e4 0x410 0x854 0x2 0x0 +-#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 0x0e4 0x410 0x7c0 0x3 0x1 +-#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR 0x0e4 0x410 0x000 0x4 0x0 +-#define MX53_PAD_CSI0_DAT9__I2C1_SCL 0x0e4 0x410 0x814 0x5 0x0 +-#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 0x0e4 0x410 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 0x0e4 0x410 0x000 0x7 0x0 +-#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x0e8 0x414 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_DAT10__GPIO5_28 0x0e8 0x414 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x0e8 0x414 0x000 0x2 0x0 +-#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO 0x0e8 0x414 0x7bc 0x3 0x1 +-#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 0x0e8 0x414 0x000 0x4 0x0 +-#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 0x0e8 0x414 0x000 0x5 0x0 +-#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 0x0e8 0x414 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 0x0e8 0x414 0x000 0x7 0x0 +-#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x0ec 0x418 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_DAT11__GPIO5_29 0x0ec 0x418 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x0ec 0x418 0x878 0x2 0x1 +-#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 0x0ec 0x418 0x7c4 0x3 0x1 +-#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 0x0ec 0x418 0x000 0x4 0x0 +-#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 0x0ec 0x418 0x000 0x5 0x0 +-#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 0x0ec 0x418 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 0x0ec 0x418 0x000 0x7 0x0 +-#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x0f0 0x41c 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_DAT12__GPIO5_30 0x0f0 0x41c 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x0f0 0x41c 0x000 0x2 0x0 +-#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 0x0f0 0x41c 0x000 0x4 0x0 +-#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 0x0f0 0x41c 0x000 0x5 0x0 +-#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 0x0f0 0x41c 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 0x0f0 0x41c 0x000 0x7 0x0 +-#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x0f4 0x420 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_DAT13__GPIO5_31 0x0f4 0x420 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x0f4 0x420 0x890 0x2 0x3 +-#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 0x0f4 0x420 0x000 0x4 0x0 +-#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 0x0f4 0x420 0x000 0x5 0x0 +-#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 0x0f4 0x420 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 0x0f4 0x420 0x000 0x7 0x0 +-#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x0f8 0x424 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_DAT14__GPIO6_0 0x0f8 0x424 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX 0x0f8 0x424 0x000 0x2 0x0 +-#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 0x0f8 0x424 0x000 0x4 0x0 +-#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 0x0f8 0x424 0x000 0x5 0x0 +-#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 0x0f8 0x424 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 0x0f8 0x424 0x000 0x7 0x0 +-#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x0fc 0x428 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_DAT15__GPIO6_1 0x0fc 0x428 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX 0x0fc 0x428 0x898 0x2 0x3 +-#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 0x0fc 0x428 0x000 0x4 0x0 +-#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 0x0fc 0x428 0x000 0x5 0x0 +-#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 0x0fc 0x428 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 0x0fc 0x428 0x000 0x7 0x0 +-#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x100 0x42c 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_DAT16__GPIO6_2 0x100 0x42c 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_DAT16__UART4_RTS 0x100 0x42c 0x88c 0x2 0x0 +-#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 0x100 0x42c 0x000 0x4 0x0 +-#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 0x100 0x42c 0x000 0x5 0x0 +-#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 0x100 0x42c 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 0x100 0x42c 0x000 0x7 0x0 +-#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x104 0x430 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_DAT17__GPIO6_3 0x104 0x430 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_DAT17__UART4_CTS 0x104 0x430 0x000 0x2 0x0 +-#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 0x104 0x430 0x000 0x4 0x0 +-#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 0x104 0x430 0x000 0x5 0x0 +-#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 0x104 0x430 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 0x104 0x430 0x000 0x7 0x0 +-#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x108 0x434 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_DAT18__GPIO6_4 0x108 0x434 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_DAT18__UART5_RTS 0x108 0x434 0x894 0x2 0x2 +-#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 0x108 0x434 0x000 0x4 0x0 +-#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 0x108 0x434 0x000 0x5 0x0 +-#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 0x108 0x434 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 0x108 0x434 0x000 0x7 0x0 +-#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x10c 0x438 0x000 0x0 0x0 +-#define MX53_PAD_CSI0_DAT19__GPIO6_5 0x10c 0x438 0x000 0x1 0x0 +-#define MX53_PAD_CSI0_DAT19__UART5_CTS 0x10c 0x438 0x000 0x2 0x0 +-#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 0x10c 0x438 0x000 0x4 0x0 +-#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 0x10c 0x438 0x000 0x5 0x0 +-#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 0x10c 0x438 0x000 0x6 0x0 +-#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK 0x10c 0x438 0x000 0x7 0x0 +-#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 0x110 0x458 0x000 0x0 0x0 +-#define MX53_PAD_EIM_A25__GPIO5_2 0x110 0x458 0x000 0x1 0x0 +-#define MX53_PAD_EIM_A25__ECSPI2_RDY 0x110 0x458 0x000 0x2 0x0 +-#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x110 0x458 0x000 0x3 0x0 +-#define MX53_PAD_EIM_A25__CSPI_SS1 0x110 0x458 0x790 0x4 0x1 +-#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS 0x110 0x458 0x000 0x6 0x0 +-#define MX53_PAD_EIM_A25__USBPHY1_BISTOK 0x110 0x458 0x000 0x7 0x0 +-#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x114 0x45c 0x000 0x0 0x0 +-#define MX53_PAD_EIM_EB2__GPIO2_30 0x114 0x45c 0x000 0x1 0x0 +-#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK 0x114 0x45c 0x76c 0x2 0x0 +-#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS 0x114 0x45c 0x000 0x3 0x0 +-#define MX53_PAD_EIM_EB2__ECSPI1_SS0 0x114 0x45c 0x7a8 0x4 0x3 +-#define MX53_PAD_EIM_EB2__I2C2_SCL 0x114 0x45c 0x81c 0x5 0x1 +-#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x118 0x460 0x000 0x0 0x0 +-#define MX53_PAD_EIM_D16__GPIO3_16 0x118 0x460 0x000 0x1 0x0 +-#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 0x118 0x460 0x000 0x2 0x0 +-#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK 0x118 0x460 0x000 0x3 0x0 +-#define MX53_PAD_EIM_D16__ECSPI1_SCLK 0x118 0x460 0x79c 0x4 0x3 +-#define MX53_PAD_EIM_D16__I2C2_SDA 0x118 0x460 0x820 0x5 0x1 +-#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x11c 0x464 0x000 0x0 0x0 +-#define MX53_PAD_EIM_D17__GPIO3_17 0x11c 0x464 0x000 0x1 0x0 +-#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 0x11c 0x464 0x000 0x2 0x0 +-#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN 0x11c 0x464 0x830 0x3 0x0 +-#define MX53_PAD_EIM_D17__ECSPI1_MISO 0x11c 0x464 0x7a0 0x4 0x3 +-#define MX53_PAD_EIM_D17__I2C3_SCL 0x11c 0x464 0x824 0x5 0x0 +-#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x120 0x468 0x000 0x0 0x0 +-#define MX53_PAD_EIM_D18__GPIO3_18 0x120 0x468 0x000 0x1 0x0 +-#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 0x120 0x468 0x000 0x2 0x0 +-#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO 0x120 0x468 0x830 0x3 0x1 +-#define MX53_PAD_EIM_D18__ECSPI1_MOSI 0x120 0x468 0x7a4 0x4 0x3 +-#define MX53_PAD_EIM_D18__I2C3_SDA 0x120 0x468 0x828 0x5 0x0 +-#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS 0x120 0x468 0x000 0x6 0x0 +-#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x124 0x46c 0x000 0x0 0x0 +-#define MX53_PAD_EIM_D19__GPIO3_19 0x124 0x46c 0x000 0x1 0x0 +-#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 0x124 0x46c 0x000 0x2 0x0 +-#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS 0x124 0x46c 0x000 0x3 0x0 +-#define MX53_PAD_EIM_D19__ECSPI1_SS1 0x124 0x46c 0x7ac 0x4 0x2 +-#define MX53_PAD_EIM_D19__EPIT1_EPITO 0x124 0x46c 0x000 0x5 0x0 +-#define MX53_PAD_EIM_D19__UART1_CTS 0x124 0x46c 0x000 0x6 0x0 +-#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC 0x124 0x46c 0x8a4 0x7 0x0 +-#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x128 0x470 0x000 0x0 0x0 +-#define MX53_PAD_EIM_D20__GPIO3_20 0x128 0x470 0x000 0x1 0x0 +-#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 0x128 0x470 0x000 0x2 0x0 +-#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS 0x128 0x470 0x000 0x3 0x0 +-#define MX53_PAD_EIM_D20__CSPI_SS0 0x128 0x470 0x78c 0x4 0x1 +-#define MX53_PAD_EIM_D20__EPIT2_EPITO 0x128 0x470 0x000 0x5 0x0 +-#define MX53_PAD_EIM_D20__UART1_RTS 0x128 0x470 0x874 0x6 0x1 +-#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR 0x128 0x470 0x000 0x7 0x0 +-#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x12c 0x474 0x000 0x0 0x0 +-#define MX53_PAD_EIM_D21__GPIO3_21 0x12c 0x474 0x000 0x1 0x0 +-#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 0x12c 0x474 0x000 0x2 0x0 +-#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK 0x12c 0x474 0x000 0x3 0x0 +-#define MX53_PAD_EIM_D21__CSPI_SCLK 0x12c 0x474 0x780 0x4 0x1 +-#define MX53_PAD_EIM_D21__I2C1_SCL 0x12c 0x474 0x814 0x5 0x1 +-#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC 0x12c 0x474 0x89c 0x6 0x1 +-#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x130 0x478 0x000 0x0 0x0 +-#define MX53_PAD_EIM_D22__GPIO3_22 0x130 0x478 0x000 0x1 0x0 +-#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 0x130 0x478 0x000 0x2 0x0 +-#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN 0x130 0x478 0x82c 0x3 0x0 +-#define MX53_PAD_EIM_D22__CSPI_MISO 0x130 0x478 0x784 0x4 0x1 +-#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR 0x130 0x478 0x000 0x6 0x0 +-#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x134 0x47c 0x000 0x0 0x0 +-#define MX53_PAD_EIM_D23__GPIO3_23 0x134 0x47c 0x000 0x1 0x0 +-#define MX53_PAD_EIM_D23__UART3_CTS 0x134 0x47c 0x000 0x2 0x0 +-#define MX53_PAD_EIM_D23__UART1_DCD 0x134 0x47c 0x000 0x3 0x0 +-#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS 0x134 0x47c 0x000 0x4 0x0 +-#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x134 0x47c 0x000 0x5 0x0 +-#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN 0x134 0x47c 0x834 0x6 0x0 +-#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 0x134 0x47c 0x000 0x7 0x0 +-#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x138 0x480 0x000 0x0 0x0 +-#define MX53_PAD_EIM_EB3__GPIO2_31 0x138 0x480 0x000 0x1 0x0 +-#define MX53_PAD_EIM_EB3__UART3_RTS 0x138 0x480 0x884 0x2 0x1 +-#define MX53_PAD_EIM_EB3__UART1_RI 0x138 0x480 0x000 0x3 0x0 +-#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x138 0x480 0x000 0x5 0x0 +-#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC 0x138 0x480 0x838 0x6 0x0 +-#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 0x138 0x480 0x000 0x7 0x0 +-#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x13c 0x484 0x000 0x0 0x0 +-#define MX53_PAD_EIM_D24__GPIO3_24 0x13c 0x484 0x000 0x1 0x0 +-#define MX53_PAD_EIM_D24__UART3_TXD_MUX 0x13c 0x484 0x000 0x2 0x0 +-#define MX53_PAD_EIM_D24__ECSPI1_SS2 0x13c 0x484 0x7b0 0x3 0x1 +-#define MX53_PAD_EIM_D24__CSPI_SS2 0x13c 0x484 0x794 0x4 0x1 +-#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS 0x13c 0x484 0x754 0x5 0x1 +-#define MX53_PAD_EIM_D24__ECSPI2_SS2 0x13c 0x484 0x000 0x6 0x0 +-#define MX53_PAD_EIM_D24__UART1_DTR 0x13c 0x484 0x000 0x7 0x0 +-#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x140 0x488 0x000 0x0 0x0 +-#define MX53_PAD_EIM_D25__GPIO3_25 0x140 0x488 0x000 0x1 0x0 +-#define MX53_PAD_EIM_D25__UART3_RXD_MUX 0x140 0x488 0x888 0x2 0x1 +-#define MX53_PAD_EIM_D25__ECSPI1_SS3 0x140 0x488 0x7b4 0x3 0x1 +-#define MX53_PAD_EIM_D25__CSPI_SS3 0x140 0x488 0x798 0x4 0x1 +-#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC 0x140 0x488 0x750 0x5 0x1 +-#define MX53_PAD_EIM_D25__ECSPI2_SS3 0x140 0x488 0x000 0x6 0x0 +-#define MX53_PAD_EIM_D25__UART1_DSR 0x140 0x488 0x000 0x7 0x0 +-#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x144 0x48c 0x000 0x0 0x0 +-#define MX53_PAD_EIM_D26__GPIO3_26 0x144 0x48c 0x000 0x1 0x0 +-#define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0 +-#define MX53_PAD_EIM_D26__UART2_TXD_MUX 0x144 0x48c 0x000 0x2 0x0 +-#define MX53_PAD_EIM_D26__FIRI_RXD 0x144 0x48c 0x80c 0x3 0x0 +-#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 0x144 0x48c 0x000 0x4 0x0 +-#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 0x144 0x48c 0x000 0x5 0x0 +-#define MX53_PAD_EIM_D26__IPU_SISG_2 0x144 0x48c 0x000 0x6 0x0 +-#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x144 0x48c 0x000 0x7 0x0 +-#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x148 0x490 0x000 0x0 0x0 +-#define MX53_PAD_EIM_D27__GPIO3_27 0x148 0x490 0x000 0x1 0x0 +-#define MX53_PAD_EIM_D27__UART2_RXD_MUX 0x148 0x490 0x880 0x2 0x1 +-#define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0 +-#define MX53_PAD_EIM_D27__FIRI_TXD 0x148 0x490 0x000 0x3 0x0 +-#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 0x148 0x490 0x000 0x4 0x0 +-#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 0x148 0x490 0x000 0x5 0x0 +-#define MX53_PAD_EIM_D27__IPU_SISG_3 0x148 0x490 0x000 0x6 0x0 +-#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x148 0x490 0x000 0x7 0x0 +-#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x14c 0x494 0x000 0x0 0x0 +-#define MX53_PAD_EIM_D28__GPIO3_28 0x14c 0x494 0x000 0x1 0x0 +-#define MX53_PAD_EIM_D28__UART2_CTS 0x14c 0x494 0x000 0x2 0x0 +-#define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0 +-#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 0x14c 0x494 0x82c 0x3 0x1 +-#define MX53_PAD_EIM_D28__CSPI_MOSI 0x14c 0x494 0x788 0x4 0x1 +-#define MX53_PAD_EIM_D28__I2C1_SDA 0x14c 0x494 0x818 0x5 0x1 +-#define MX53_PAD_EIM_D28__IPU_EXT_TRIG 0x14c 0x494 0x000 0x6 0x0 +-#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 0x14c 0x494 0x000 0x7 0x0 +-#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x150 0x498 0x000 0x0 0x0 +-#define MX53_PAD_EIM_D29__GPIO3_29 0x150 0x498 0x000 0x1 0x0 +-#define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0 +-#define MX53_PAD_EIM_D29__UART2_RTS 0x150 0x498 0x87c 0x2 0x1 +-#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 0x150 0x498 0x000 0x3 0x0 +-#define MX53_PAD_EIM_D29__CSPI_SS0 0x150 0x498 0x78c 0x4 0x2 +-#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 0x150 0x498 0x000 0x5 0x0 +-#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC 0x150 0x498 0x83c 0x6 0x0 +-#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 0x150 0x498 0x000 0x7 0x0 +-#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x154 0x49c 0x000 0x0 0x0 +-#define MX53_PAD_EIM_D30__GPIO3_30 0x154 0x49c 0x000 0x1 0x0 +-#define MX53_PAD_EIM_D30__UART3_CTS 0x154 0x49c 0x000 0x2 0x0 +-#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 0x154 0x49c 0x000 0x3 0x0 +-#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 0x154 0x49c 0x000 0x4 0x0 +-#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x154 0x49c 0x000 0x5 0x0 +-#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC 0x154 0x49c 0x8a0 0x6 0x0 +-#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC 0x154 0x49c 0x8a4 0x7 0x1 +-#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x158 0x4a0 0x000 0x0 0x0 +-#define MX53_PAD_EIM_D31__GPIO3_31 0x158 0x4a0 0x000 0x1 0x0 +-#define MX53_PAD_EIM_D31__UART3_RTS 0x158 0x4a0 0x884 0x2 0x3 +-#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 0x158 0x4a0 0x000 0x3 0x0 +-#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 0x158 0x4a0 0x000 0x4 0x0 +-#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x158 0x4a0 0x000 0x5 0x0 +-#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR 0x158 0x4a0 0x000 0x6 0x0 +-#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR 0x158 0x4a0 0x000 0x7 0x0 +-#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 0x15c 0x4a8 0x000 0x0 0x0 +-#define MX53_PAD_EIM_A24__GPIO5_4 0x15c 0x4a8 0x000 0x1 0x0 +-#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x15c 0x4a8 0x000 0x2 0x0 +-#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 0x15c 0x4a8 0x000 0x3 0x0 +-#define MX53_PAD_EIM_A24__IPU_SISG_2 0x15c 0x4a8 0x000 0x6 0x0 +-#define MX53_PAD_EIM_A24__USBPHY2_BVALID 0x15c 0x4a8 0x000 0x7 0x0 +-#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 0x160 0x4ac 0x000 0x0 0x0 +-#define MX53_PAD_EIM_A23__GPIO6_6 0x160 0x4ac 0x000 0x1 0x0 +-#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x160 0x4ac 0x000 0x2 0x0 +-#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 0x160 0x4ac 0x000 0x3 0x0 +-#define MX53_PAD_EIM_A23__IPU_SISG_3 0x160 0x4ac 0x000 0x6 0x0 +-#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION 0x160 0x4ac 0x000 0x7 0x0 +-#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x164 0x4b0 0x000 0x0 0x0 +-#define MX53_PAD_EIM_A22__GPIO2_16 0x164 0x4b0 0x000 0x1 0x0 +-#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x164 0x4b0 0x000 0x2 0x0 +-#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 0x164 0x4b0 0x000 0x3 0x0 +-#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 0x164 0x4b0 0x000 0x7 0x0 +-#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x168 0x4b4 0x000 0x0 0x0 +-#define MX53_PAD_EIM_A21__GPIO2_17 0x168 0x4b4 0x000 0x1 0x0 +-#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x168 0x4b4 0x000 0x2 0x0 +-#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 0x168 0x4b4 0x000 0x3 0x0 +-#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 0x168 0x4b4 0x000 0x7 0x0 +-#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x16c 0x4b8 0x000 0x0 0x0 +-#define MX53_PAD_EIM_A20__GPIO2_18 0x16c 0x4b8 0x000 0x1 0x0 +-#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x16c 0x4b8 0x000 0x2 0x0 +-#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 0x16c 0x4b8 0x000 0x3 0x0 +-#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 0x16c 0x4b8 0x000 0x7 0x0 +-#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x170 0x4bc 0x000 0x0 0x0 +-#define MX53_PAD_EIM_A19__GPIO2_19 0x170 0x4bc 0x000 0x1 0x0 +-#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x170 0x4bc 0x000 0x2 0x0 +-#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 0x170 0x4bc 0x000 0x3 0x0 +-#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 0x170 0x4bc 0x000 0x7 0x0 +-#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x174 0x4c0 0x000 0x0 0x0 +-#define MX53_PAD_EIM_A18__GPIO2_20 0x174 0x4c0 0x000 0x1 0x0 +-#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x174 0x4c0 0x000 0x2 0x0 +-#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 0x174 0x4c0 0x000 0x3 0x0 +-#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 0x174 0x4c0 0x000 0x7 0x0 +-#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x178 0x4c4 0x000 0x0 0x0 +-#define MX53_PAD_EIM_A17__GPIO2_21 0x178 0x4c4 0x000 0x1 0x0 +-#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x178 0x4c4 0x000 0x2 0x0 +-#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 0x178 0x4c4 0x000 0x3 0x0 +-#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 0x178 0x4c4 0x000 0x7 0x0 +-#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x17c 0x4c8 0x000 0x0 0x0 +-#define MX53_PAD_EIM_A16__GPIO2_22 0x17c 0x4c8 0x000 0x1 0x0 +-#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x17c 0x4c8 0x000 0x2 0x0 +-#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK 0x17c 0x4c8 0x000 0x3 0x0 +-#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 0x17c 0x4c8 0x000 0x7 0x0 +-#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x180 0x4cc 0x000 0x0 0x0 +-#define MX53_PAD_EIM_CS0__GPIO2_23 0x180 0x4cc 0x000 0x1 0x0 +-#define MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x180 0x4cc 0x7b8 0x2 0x2 +-#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 0x180 0x4cc 0x000 0x3 0x0 +-#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x184 0x4d0 0x000 0x0 0x0 +-#define MX53_PAD_EIM_CS1__GPIO2_24 0x184 0x4d0 0x000 0x1 0x0 +-#define MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x184 0x4d0 0x7c0 0x2 0x2 +-#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x184 0x4d0 0x000 0x3 0x0 +-#define MX53_PAD_EIM_OE__EMI_WEIM_OE 0x188 0x4d4 0x000 0x0 0x0 +-#define MX53_PAD_EIM_OE__GPIO2_25 0x188 0x4d4 0x000 0x1 0x0 +-#define MX53_PAD_EIM_OE__ECSPI2_MISO 0x188 0x4d4 0x7bc 0x2 0x2 +-#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 0x188 0x4d4 0x000 0x3 0x0 +-#define MX53_PAD_EIM_OE__USBPHY2_IDDIG 0x188 0x4d4 0x000 0x7 0x0 +-#define MX53_PAD_EIM_RW__EMI_WEIM_RW 0x18c 0x4d8 0x000 0x0 0x0 +-#define MX53_PAD_EIM_RW__GPIO2_26 0x18c 0x4d8 0x000 0x1 0x0 +-#define MX53_PAD_EIM_RW__ECSPI2_SS0 0x18c 0x4d8 0x7c4 0x2 0x2 +-#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 0x18c 0x4d8 0x000 0x3 0x0 +-#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT 0x18c 0x4d8 0x000 0x7 0x0 +-#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x190 0x4dc 0x000 0x0 0x0 +-#define MX53_PAD_EIM_LBA__GPIO2_27 0x190 0x4dc 0x000 0x1 0x0 +-#define MX53_PAD_EIM_LBA__ECSPI2_SS1 0x190 0x4dc 0x7c8 0x2 0x1 +-#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 0x190 0x4dc 0x000 0x3 0x0 +-#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 0x190 0x4dc 0x000 0x7 0x0 +-#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x194 0x4e4 0x000 0x0 0x0 +-#define MX53_PAD_EIM_EB0__GPIO2_28 0x194 0x4e4 0x000 0x1 0x0 +-#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x194 0x4e4 0x000 0x3 0x0 +-#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 0x194 0x4e4 0x000 0x4 0x0 +-#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY 0x194 0x4e4 0x810 0x5 0x0 +-#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 0x194 0x4e4 0x000 0x7 0x0 +-#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x198 0x4e8 0x000 0x0 0x0 +-#define MX53_PAD_EIM_EB1__GPIO2_29 0x198 0x4e8 0x000 0x1 0x0 +-#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x198 0x4e8 0x000 0x3 0x0 +-#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 0x198 0x4e8 0x000 0x4 0x0 +-#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 0x198 0x4e8 0x000 0x7 0x0 +-#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x19c 0x4ec 0x000 0x0 0x0 +-#define MX53_PAD_EIM_DA0__GPIO3_0 0x19c 0x4ec 0x000 0x1 0x0 +-#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x19c 0x4ec 0x000 0x3 0x0 +-#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 0x19c 0x4ec 0x000 0x4 0x0 +-#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 0x19c 0x4ec 0x000 0x7 0x0 +-#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x1a0 0x4f0 0x000 0x0 0x0 +-#define MX53_PAD_EIM_DA1__GPIO3_1 0x1a0 0x4f0 0x000 0x1 0x0 +-#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x1a0 0x4f0 0x000 0x3 0x0 +-#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 0x1a0 0x4f0 0x000 0x4 0x0 +-#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 0x1a0 0x4f0 0x000 0x7 0x0 +-#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x1a4 0x4f4 0x000 0x0 0x0 +-#define MX53_PAD_EIM_DA2__GPIO3_2 0x1a4 0x4f4 0x000 0x1 0x0 +-#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x1a4 0x4f4 0x000 0x3 0x0 +-#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 0x1a4 0x4f4 0x000 0x4 0x0 +-#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 0x1a4 0x4f4 0x000 0x7 0x0 +-#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x1a8 0x4f8 0x000 0x0 0x0 +-#define MX53_PAD_EIM_DA3__GPIO3_3 0x1a8 0x4f8 0x000 0x1 0x0 +-#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x1a8 0x4f8 0x000 0x3 0x0 +-#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 0x1a8 0x4f8 0x000 0x4 0x0 +-#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 0x1a8 0x4f8 0x000 0x7 0x0 +-#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x1ac 0x4fc 0x000 0x0 0x0 +-#define MX53_PAD_EIM_DA4__GPIO3_4 0x1ac 0x4fc 0x000 0x1 0x0 +-#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x1ac 0x4fc 0x000 0x3 0x0 +-#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 0x1ac 0x4fc 0x000 0x4 0x0 +-#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 0x1ac 0x4fc 0x000 0x7 0x0 +-#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x1b0 0x500 0x000 0x0 0x0 +-#define MX53_PAD_EIM_DA5__GPIO3_5 0x1b0 0x500 0x000 0x1 0x0 +-#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x1b0 0x500 0x000 0x3 0x0 +-#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 0x1b0 0x500 0x000 0x4 0x0 +-#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 0x1b0 0x500 0x000 0x7 0x0 +-#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x1b4 0x504 0x000 0x0 0x0 +-#define MX53_PAD_EIM_DA6__GPIO3_6 0x1b4 0x504 0x000 0x1 0x0 +-#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x1b4 0x504 0x000 0x3 0x0 +-#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 0x1b4 0x504 0x000 0x4 0x0 +-#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 0x1b4 0x504 0x000 0x7 0x0 +-#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0x1b8 0x508 0x000 0x0 0x0 +-#define MX53_PAD_EIM_DA7__GPIO3_7 0x1b8 0x508 0x000 0x1 0x0 +-#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x1b8 0x508 0x000 0x3 0x0 +-#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 0x1b8 0x508 0x000 0x4 0x0 +-#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 0x1b8 0x508 0x000 0x7 0x0 +-#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0x1bc 0x50c 0x000 0x0 0x0 +-#define MX53_PAD_EIM_DA8__GPIO3_8 0x1bc 0x50c 0x000 0x1 0x0 +-#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x1bc 0x50c 0x000 0x3 0x0 +-#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 0x1bc 0x50c 0x000 0x4 0x0 +-#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 0x1bc 0x50c 0x000 0x7 0x0 +-#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0x1c0 0x510 0x000 0x0 0x0 +-#define MX53_PAD_EIM_DA9__GPIO3_9 0x1c0 0x510 0x000 0x1 0x0 +-#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x1c0 0x510 0x000 0x3 0x0 +-#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 0x1c0 0x510 0x000 0x4 0x0 +-#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 0x1c0 0x510 0x000 0x7 0x0 +-#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0x1c4 0x514 0x000 0x0 0x0 +-#define MX53_PAD_EIM_DA10__GPIO3_10 0x1c4 0x514 0x000 0x1 0x0 +-#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x1c4 0x514 0x000 0x3 0x0 +-#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN 0x1c4 0x514 0x834 0x4 0x1 +-#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 0x1c4 0x514 0x000 0x7 0x0 +-#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0x1c8 0x518 0x000 0x0 0x0 +-#define MX53_PAD_EIM_DA11__GPIO3_11 0x1c8 0x518 0x000 0x1 0x0 +-#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x1c8 0x518 0x000 0x3 0x0 +-#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC 0x1c8 0x518 0x838 0x4 0x1 +-#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0x1cc 0x51c 0x000 0x0 0x0 +-#define MX53_PAD_EIM_DA12__GPIO3_12 0x1cc 0x51c 0x000 0x1 0x0 +-#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x1cc 0x51c 0x000 0x3 0x0 +-#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC 0x1cc 0x51c 0x83c 0x4 0x1 +-#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0x1d0 0x520 0x000 0x0 0x0 +-#define MX53_PAD_EIM_DA13__GPIO3_13 0x1d0 0x520 0x000 0x1 0x0 +-#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x1d0 0x520 0x000 0x3 0x0 +-#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK 0x1d0 0x520 0x76c 0x4 0x1 +-#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0x1d4 0x524 0x000 0x0 0x0 +-#define MX53_PAD_EIM_DA14__GPIO3_14 0x1d4 0x524 0x000 0x1 0x0 +-#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x1d4 0x524 0x000 0x3 0x0 +-#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK 0x1d4 0x524 0x000 0x4 0x0 +-#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0x1d8 0x528 0x000 0x0 0x0 +-#define MX53_PAD_EIM_DA15__GPIO3_15 0x1d8 0x528 0x000 0x1 0x0 +-#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x1d8 0x528 0x000 0x3 0x0 +-#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x1d8 0x528 0x000 0x4 0x0 +-#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x1dc 0x52c 0x000 0x0 0x0 +-#define MX53_PAD_NANDF_WE_B__GPIO6_12 0x1dc 0x52c 0x000 0x1 0x0 +-#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x1e0 0x530 0x000 0x0 0x0 +-#define MX53_PAD_NANDF_RE_B__GPIO6_13 0x1e0 0x530 0x000 0x1 0x0 +-#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x1e4 0x534 0x000 0x0 0x0 +-#define MX53_PAD_EIM_WAIT__GPIO5_0 0x1e4 0x534 0x000 0x1 0x0 +-#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B 0x1e4 0x534 0x000 0x2 0x0 +-#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 0x1ec 0x000 0x000 0x0 0x0 +-#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x1ec 0x000 0x000 0x1 0x0 +-#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 0x1f0 0x000 0x000 0x0 0x0 +-#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x1f0 0x000 0x000 0x1 0x0 +-#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 0x1f4 0x000 0x000 0x0 0x0 +-#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x1f4 0x000 0x000 0x1 0x0 +-#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 0x1f8 0x000 0x000 0x0 0x0 +-#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x1f8 0x000 0x000 0x1 0x0 +-#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 0x1fc 0x000 0x000 0x0 0x0 +-#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x1fc 0x000 0x000 0x1 0x0 +-#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 0x200 0x000 0x000 0x0 0x0 +-#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x200 0x000 0x000 0x1 0x0 +-#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 0x204 0x000 0x000 0x0 0x0 +-#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x204 0x000 0x000 0x1 0x0 +-#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 0x208 0x000 0x000 0x0 0x0 +-#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x208 0x000 0x000 0x1 0x0 +-#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 0x20c 0x000 0x000 0x0 0x0 +-#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x20c 0x000 0x000 0x1 0x0 +-#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 0x210 0x000 0x000 0x0 0x0 +-#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x210 0x000 0x000 0x1 0x0 +-#define MX53_PAD_GPIO_10__GPIO4_0 0x214 0x540 0x000 0x0 0x0 +-#define MX53_PAD_GPIO_10__OSC32k_32K_OUT 0x214 0x540 0x000 0x1 0x0 +-#define MX53_PAD_GPIO_11__GPIO4_1 0x218 0x544 0x000 0x0 0x0 +-#define MX53_PAD_GPIO_12__GPIO4_2 0x21c 0x548 0x000 0x0 0x0 +-#define MX53_PAD_GPIO_13__GPIO4_3 0x220 0x54c 0x000 0x0 0x0 +-#define MX53_PAD_GPIO_14__GPIO4_4 0x224 0x550 0x000 0x0 0x0 +-#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x228 0x5a0 0x000 0x0 0x0 +-#define MX53_PAD_NANDF_CLE__GPIO6_7 0x228 0x5a0 0x000 0x1 0x0 +-#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 0x228 0x5a0 0x000 0x7 0x0 +-#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x22c 0x5a4 0x000 0x0 0x0 +-#define MX53_PAD_NANDF_ALE__GPIO6_8 0x22c 0x5a4 0x000 0x1 0x0 +-#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 0x22c 0x5a4 0x000 0x7 0x0 +-#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0x230 0x5a8 0x000 0x0 0x0 +-#define MX53_PAD_NANDF_WP_B__GPIO6_9 0x230 0x5a8 0x000 0x1 0x0 +-#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 0x230 0x5a8 0x000 0x7 0x0 +-#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0x234 0x5ac 0x000 0x0 0x0 +-#define MX53_PAD_NANDF_RB0__GPIO6_10 0x234 0x5ac 0x000 0x1 0x0 +-#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 0x234 0x5ac 0x000 0x7 0x0 +-#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x238 0x5b0 0x000 0x0 0x0 +-#define MX53_PAD_NANDF_CS0__GPIO6_11 0x238 0x5b0 0x000 0x1 0x0 +-#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 0x238 0x5b0 0x000 0x7 0x0 +-#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 0x23c 0x5b4 0x000 0x0 0x0 +-#define MX53_PAD_NANDF_CS1__GPIO6_14 0x23c 0x5b4 0x000 0x1 0x0 +-#define MX53_PAD_NANDF_CS1__MLB_MLBCLK 0x23c 0x5b4 0x858 0x6 0x0 +-#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 0x23c 0x5b4 0x000 0x7 0x0 +-#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 0x240 0x5b8 0x000 0x0 0x0 +-#define MX53_PAD_NANDF_CS2__GPIO6_15 0x240 0x5b8 0x000 0x1 0x0 +-#define MX53_PAD_NANDF_CS2__IPU_SISG_0 0x240 0x5b8 0x000 0x2 0x0 +-#define MX53_PAD_NANDF_CS2__ESAI1_TX0 0x240 0x5b8 0x7e4 0x3 0x0 +-#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE 0x240 0x5b8 0x000 0x4 0x0 +-#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK 0x240 0x5b8 0x000 0x5 0x0 +-#define MX53_PAD_NANDF_CS2__MLB_MLBSIG 0x240 0x5b8 0x860 0x6 0x0 +-#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 0x240 0x5b8 0x000 0x7 0x0 +-#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 0x244 0x5bc 0x000 0x0 0x0 +-#define MX53_PAD_NANDF_CS3__GPIO6_16 0x244 0x5bc 0x000 0x1 0x0 +-#define MX53_PAD_NANDF_CS3__IPU_SISG_1 0x244 0x5bc 0x000 0x2 0x0 +-#define MX53_PAD_NANDF_CS3__ESAI1_TX1 0x244 0x5bc 0x7e8 0x3 0x0 +-#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 0x244 0x5bc 0x000 0x4 0x0 +-#define MX53_PAD_NANDF_CS3__MLB_MLBDAT 0x244 0x5bc 0x85c 0x6 0x0 +-#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 0x244 0x5bc 0x000 0x7 0x0 +-#define MX53_PAD_FEC_MDIO__FEC_MDIO 0x248 0x5c4 0x804 0x0 0x1 +-#define MX53_PAD_FEC_MDIO__GPIO1_22 0x248 0x5c4 0x000 0x1 0x0 +-#define MX53_PAD_FEC_MDIO__ESAI1_SCKR 0x248 0x5c4 0x7dc 0x2 0x0 +-#define MX53_PAD_FEC_MDIO__FEC_COL 0x248 0x5c4 0x800 0x3 0x1 +-#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 0x248 0x5c4 0x000 0x4 0x0 +-#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 0x248 0x5c4 0x000 0x5 0x0 +-#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 0x248 0x5c4 0x000 0x6 0x0 +-#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x24c 0x5c8 0x000 0x0 0x0 +-#define MX53_PAD_FEC_REF_CLK__GPIO1_23 0x24c 0x5c8 0x000 0x1 0x0 +-#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR 0x24c 0x5c8 0x7cc 0x2 0x0 +-#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 0x24c 0x5c8 0x000 0x5 0x0 +-#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 0x24c 0x5c8 0x000 0x6 0x0 +-#define MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x250 0x5cc 0x000 0x0 0x0 +-#define MX53_PAD_FEC_RX_ER__GPIO1_24 0x250 0x5cc 0x000 0x1 0x0 +-#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR 0x250 0x5cc 0x7d4 0x2 0x0 +-#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK 0x250 0x5cc 0x808 0x3 0x1 +-#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 0x250 0x5cc 0x000 0x4 0x0 +-#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x254 0x5d0 0x000 0x0 0x0 +-#define MX53_PAD_FEC_CRS_DV__GPIO1_25 0x254 0x5d0 0x000 0x1 0x0 +-#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 0x254 0x5d0 0x7e0 0x2 0x0 +-#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x258 0x5d4 0x000 0x0 0x0 +-#define MX53_PAD_FEC_RXD1__GPIO1_26 0x258 0x5d4 0x000 0x1 0x0 +-#define MX53_PAD_FEC_RXD1__ESAI1_FST 0x258 0x5d4 0x7d0 0x2 0x0 +-#define MX53_PAD_FEC_RXD1__MLB_MLBSIG 0x258 0x5d4 0x860 0x3 0x1 +-#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 0x258 0x5d4 0x000 0x4 0x0 +-#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x25c 0x5d8 0x000 0x0 0x0 +-#define MX53_PAD_FEC_RXD0__GPIO1_27 0x25c 0x5d8 0x000 0x1 0x0 +-#define MX53_PAD_FEC_RXD0__ESAI1_HCKT 0x25c 0x5d8 0x7d8 0x2 0x0 +-#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT 0x25c 0x5d8 0x000 0x3 0x0 +-#define MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x260 0x5dc 0x000 0x0 0x0 +-#define MX53_PAD_FEC_TX_EN__GPIO1_28 0x260 0x5dc 0x000 0x1 0x0 +-#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 0x260 0x5dc 0x7f0 0x2 0x0 +-#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x264 0x5e0 0x000 0x0 0x0 +-#define MX53_PAD_FEC_TXD1__GPIO1_29 0x264 0x5e0 0x000 0x1 0x0 +-#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 0x264 0x5e0 0x7ec 0x2 0x0 +-#define MX53_PAD_FEC_TXD1__MLB_MLBCLK 0x264 0x5e0 0x858 0x3 0x1 +-#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK 0x264 0x5e0 0x000 0x4 0x0 +-#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x268 0x5e4 0x000 0x0 0x0 +-#define MX53_PAD_FEC_TXD0__GPIO1_30 0x268 0x5e4 0x000 0x1 0x0 +-#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 0x268 0x5e4 0x7f4 0x2 0x0 +-#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 0x268 0x5e4 0x000 0x7 0x0 +-#define MX53_PAD_FEC_MDC__FEC_MDC 0x26c 0x5e8 0x000 0x0 0x0 +-#define MX53_PAD_FEC_MDC__GPIO1_31 0x26c 0x5e8 0x000 0x1 0x0 +-#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 0x26c 0x5e8 0x7f8 0x2 0x0 +-#define MX53_PAD_FEC_MDC__MLB_MLBDAT 0x26c 0x5e8 0x85c 0x3 0x1 +-#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG 0x26c 0x5e8 0x000 0x4 0x0 +-#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 0x26c 0x5e8 0x000 0x7 0x0 +-#define MX53_PAD_PATA_DIOW__PATA_DIOW 0x270 0x5f0 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DIOW__GPIO6_17 0x270 0x5f0 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x270 0x5f0 0x000 0x3 0x0 +-#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 0x270 0x5f0 0x000 0x7 0x0 +-#define MX53_PAD_PATA_DMACK__PATA_DMACK 0x274 0x5f4 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DMACK__GPIO6_18 0x274 0x5f4 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x274 0x5f4 0x878 0x3 0x3 +-#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 0x274 0x5f4 0x000 0x7 0x0 +-#define MX53_PAD_PATA_DMARQ__PATA_DMARQ 0x278 0x5f8 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DMARQ__GPIO7_0 0x278 0x5f8 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x278 0x5f8 0x000 0x3 0x0 +-#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 0x278 0x5f8 0x000 0x5 0x0 +-#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 0x278 0x5f8 0x000 0x7 0x0 +-#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN 0x27c 0x5fc 0x000 0x0 0x0 +-#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 0x27c 0x5fc 0x000 0x1 0x0 +-#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x27c 0x5fc 0x880 0x3 0x3 +-#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 0x27c 0x5fc 0x000 0x5 0x0 +-#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 0x27c 0x5fc 0x000 0x7 0x0 +-#define MX53_PAD_PATA_INTRQ__PATA_INTRQ 0x280 0x600 0x000 0x0 0x0 +-#define MX53_PAD_PATA_INTRQ__GPIO7_2 0x280 0x600 0x000 0x1 0x0 +-#define MX53_PAD_PATA_INTRQ__UART2_CTS 0x280 0x600 0x000 0x3 0x0 +-#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x280 0x600 0x000 0x4 0x0 +-#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 0x280 0x600 0x000 0x5 0x0 +-#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 0x280 0x600 0x000 0x7 0x0 +-#define MX53_PAD_PATA_DIOR__PATA_DIOR 0x284 0x604 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DIOR__GPIO7_3 0x284 0x604 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DIOR__UART2_RTS 0x284 0x604 0x87c 0x3 0x3 +-#define MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x284 0x604 0x760 0x4 0x1 +-#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 0x284 0x604 0x000 0x7 0x0 +-#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B 0x288 0x608 0x000 0x0 0x0 +-#define MX53_PAD_PATA_RESET_B__GPIO7_4 0x288 0x608 0x000 0x1 0x0 +-#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x288 0x608 0x000 0x2 0x0 +-#define MX53_PAD_PATA_RESET_B__UART1_CTS 0x288 0x608 0x000 0x3 0x0 +-#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN 0x288 0x608 0x000 0x4 0x0 +-#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 0x288 0x608 0x000 0x7 0x0 +-#define MX53_PAD_PATA_IORDY__PATA_IORDY 0x28c 0x60c 0x000 0x0 0x0 +-#define MX53_PAD_PATA_IORDY__GPIO7_5 0x28c 0x60c 0x000 0x1 0x0 +-#define MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x28c 0x60c 0x000 0x2 0x0 +-#define MX53_PAD_PATA_IORDY__UART1_RTS 0x28c 0x60c 0x874 0x3 0x3 +-#define MX53_PAD_PATA_IORDY__CAN2_RXCAN 0x28c 0x60c 0x764 0x4 0x1 +-#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 0x28c 0x60c 0x000 0x7 0x0 +-#define MX53_PAD_PATA_DA_0__PATA_DA_0 0x290 0x610 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DA_0__GPIO7_6 0x290 0x610 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DA_0__ESDHC3_RST 0x290 0x610 0x000 0x2 0x0 +-#define MX53_PAD_PATA_DA_0__OWIRE_LINE 0x290 0x610 0x864 0x4 0x0 +-#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 0x290 0x610 0x000 0x7 0x0 +-#define MX53_PAD_PATA_DA_1__PATA_DA_1 0x294 0x614 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DA_1__GPIO7_7 0x294 0x614 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DA_1__ESDHC4_CMD 0x294 0x614 0x000 0x2 0x0 +-#define MX53_PAD_PATA_DA_1__UART3_CTS 0x294 0x614 0x000 0x4 0x0 +-#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 0x294 0x614 0x000 0x7 0x0 +-#define MX53_PAD_PATA_DA_2__PATA_DA_2 0x298 0x618 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DA_2__GPIO7_8 0x298 0x618 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DA_2__ESDHC4_CLK 0x298 0x618 0x000 0x2 0x0 +-#define MX53_PAD_PATA_DA_2__UART3_RTS 0x298 0x618 0x884 0x4 0x5 +-#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 0x298 0x618 0x000 0x7 0x0 +-#define MX53_PAD_PATA_CS_0__PATA_CS_0 0x29c 0x61c 0x000 0x0 0x0 +-#define MX53_PAD_PATA_CS_0__GPIO7_9 0x29c 0x61c 0x000 0x1 0x0 +-#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x29c 0x61c 0x000 0x4 0x0 +-#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 0x29c 0x61c 0x000 0x7 0x0 +-#define MX53_PAD_PATA_CS_1__PATA_CS_1 0x2a0 0x620 0x000 0x0 0x0 +-#define MX53_PAD_PATA_CS_1__GPIO7_10 0x2a0 0x620 0x000 0x1 0x0 +-#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x2a0 0x620 0x888 0x4 0x3 +-#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 0x2a0 0x620 0x000 0x7 0x0 +-#define MX53_PAD_PATA_DATA0__PATA_DATA_0 0x2a4 0x628 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DATA0__GPIO2_0 0x2a4 0x628 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0x2a4 0x628 0x000 0x3 0x0 +-#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x2a4 0x628 0x000 0x4 0x0 +-#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 0x2a4 0x628 0x000 0x5 0x0 +-#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 0x2a4 0x628 0x000 0x6 0x0 +-#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 0x2a4 0x628 0x000 0x7 0x0 +-#define MX53_PAD_PATA_DATA1__PATA_DATA_1 0x2a8 0x62c 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DATA1__GPIO2_1 0x2a8 0x62c 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0x2a8 0x62c 0x000 0x3 0x0 +-#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x2a8 0x62c 0x000 0x4 0x0 +-#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 0x2a8 0x62c 0x000 0x5 0x0 +-#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 0x2a8 0x62c 0x000 0x6 0x0 +-#define MX53_PAD_PATA_DATA2__PATA_DATA_2 0x2ac 0x630 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DATA2__GPIO2_2 0x2ac 0x630 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0x2ac 0x630 0x000 0x3 0x0 +-#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x2ac 0x630 0x000 0x4 0x0 +-#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 0x2ac 0x630 0x000 0x5 0x0 +-#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 0x2ac 0x630 0x000 0x6 0x0 +-#define MX53_PAD_PATA_DATA3__PATA_DATA_3 0x2b0 0x634 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DATA3__GPIO2_3 0x2b0 0x634 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0x2b0 0x634 0x000 0x3 0x0 +-#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x2b0 0x634 0x000 0x4 0x0 +-#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 0x2b0 0x634 0x000 0x5 0x0 +-#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 0x2b0 0x634 0x000 0x6 0x0 +-#define MX53_PAD_PATA_DATA4__PATA_DATA_4 0x2b4 0x638 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DATA4__GPIO2_4 0x2b4 0x638 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0x2b4 0x638 0x000 0x3 0x0 +-#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 0x2b4 0x638 0x000 0x4 0x0 +-#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 0x2b4 0x638 0x000 0x5 0x0 +-#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 0x2b4 0x638 0x000 0x6 0x0 +-#define MX53_PAD_PATA_DATA5__PATA_DATA_5 0x2b8 0x63c 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DATA5__GPIO2_5 0x2b8 0x63c 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0x2b8 0x63c 0x000 0x3 0x0 +-#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 0x2b8 0x63c 0x000 0x4 0x0 +-#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 0x2b8 0x63c 0x000 0x5 0x0 +-#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 0x2b8 0x63c 0x000 0x6 0x0 +-#define MX53_PAD_PATA_DATA6__PATA_DATA_6 0x2bc 0x640 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DATA6__GPIO2_6 0x2bc 0x640 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0x2bc 0x640 0x000 0x3 0x0 +-#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 0x2bc 0x640 0x000 0x4 0x0 +-#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 0x2bc 0x640 0x000 0x5 0x0 +-#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 0x2bc 0x640 0x000 0x6 0x0 +-#define MX53_PAD_PATA_DATA7__PATA_DATA_7 0x2c0 0x644 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DATA7__GPIO2_7 0x2c0 0x644 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0x2c0 0x644 0x000 0x3 0x0 +-#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 0x2c0 0x644 0x000 0x4 0x0 +-#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 0x2c0 0x644 0x000 0x5 0x0 +-#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 0x2c0 0x644 0x000 0x6 0x0 +-#define MX53_PAD_PATA_DATA8__PATA_DATA_8 0x2c4 0x648 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DATA8__GPIO2_8 0x2c4 0x648 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x2c4 0x648 0x000 0x2 0x0 +-#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0x2c4 0x648 0x000 0x3 0x0 +-#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x2c4 0x648 0x000 0x4 0x0 +-#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 0x2c4 0x648 0x000 0x5 0x0 +-#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 0x2c4 0x648 0x000 0x6 0x0 +-#define MX53_PAD_PATA_DATA9__PATA_DATA_9 0x2c8 0x64c 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DATA9__GPIO2_9 0x2c8 0x64c 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x2c8 0x64c 0x000 0x2 0x0 +-#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0x2c8 0x64c 0x000 0x3 0x0 +-#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x2c8 0x64c 0x000 0x4 0x0 +-#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 0x2c8 0x64c 0x000 0x5 0x0 +-#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 0x2c8 0x64c 0x000 0x6 0x0 +-#define MX53_PAD_PATA_DATA10__PATA_DATA_10 0x2cc 0x650 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DATA10__GPIO2_10 0x2cc 0x650 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x2cc 0x650 0x000 0x2 0x0 +-#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0x2cc 0x650 0x000 0x3 0x0 +-#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x2cc 0x650 0x000 0x4 0x0 +-#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 0x2cc 0x650 0x000 0x5 0x0 +-#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 0x2cc 0x650 0x000 0x6 0x0 +-#define MX53_PAD_PATA_DATA11__PATA_DATA_11 0x2d0 0x654 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DATA11__GPIO2_11 0x2d0 0x654 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x2d0 0x654 0x000 0x2 0x0 +-#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0x2d0 0x654 0x000 0x3 0x0 +-#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x2d0 0x654 0x000 0x4 0x0 +-#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 0x2d0 0x654 0x000 0x5 0x0 +-#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 0x2d0 0x654 0x000 0x6 0x0 +-#define MX53_PAD_PATA_DATA12__PATA_DATA_12 0x2d4 0x658 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DATA12__GPIO2_12 0x2d4 0x658 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 0x2d4 0x658 0x000 0x2 0x0 +-#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0x2d4 0x658 0x000 0x3 0x0 +-#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 0x2d4 0x658 0x000 0x4 0x0 +-#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 0x2d4 0x658 0x000 0x5 0x0 +-#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 0x2d4 0x658 0x000 0x6 0x0 +-#define MX53_PAD_PATA_DATA13__PATA_DATA_13 0x2d8 0x65c 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DATA13__GPIO2_13 0x2d8 0x65c 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 0x2d8 0x65c 0x000 0x2 0x0 +-#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0x2d8 0x65c 0x000 0x3 0x0 +-#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 0x2d8 0x65c 0x000 0x4 0x0 +-#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 0x2d8 0x65c 0x000 0x5 0x0 +-#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 0x2d8 0x65c 0x000 0x6 0x0 +-#define MX53_PAD_PATA_DATA14__PATA_DATA_14 0x2dc 0x660 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DATA14__GPIO2_14 0x2dc 0x660 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 0x2dc 0x660 0x000 0x2 0x0 +-#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0x2dc 0x660 0x000 0x3 0x0 +-#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 0x2dc 0x660 0x000 0x4 0x0 +-#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 0x2dc 0x660 0x000 0x5 0x0 +-#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 0x2dc 0x660 0x000 0x6 0x0 +-#define MX53_PAD_PATA_DATA15__PATA_DATA_15 0x2e0 0x664 0x000 0x0 0x0 +-#define MX53_PAD_PATA_DATA15__GPIO2_15 0x2e0 0x664 0x000 0x1 0x0 +-#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 0x2e0 0x664 0x000 0x2 0x0 +-#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0x2e0 0x664 0x000 0x3 0x0 +-#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 0x2e0 0x664 0x000 0x4 0x0 +-#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 0x2e0 0x664 0x000 0x5 0x0 +-#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 0x2e0 0x664 0x000 0x6 0x0 +-#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x2e4 0x66c 0x000 0x0 0x0 +-#define MX53_PAD_SD1_DATA0__GPIO1_16 0x2e4 0x66c 0x000 0x1 0x0 +-#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 0x2e4 0x66c 0x000 0x3 0x0 +-#define MX53_PAD_SD1_DATA0__CSPI_MISO 0x2e4 0x66c 0x784 0x5 0x2 +-#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP 0x2e4 0x66c 0x778 0x7 0x0 +-#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x2e8 0x670 0x000 0x0 0x0 +-#define MX53_PAD_SD1_DATA1__GPIO1_17 0x2e8 0x670 0x000 0x1 0x0 +-#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 0x2e8 0x670 0x000 0x3 0x0 +-#define MX53_PAD_SD1_DATA1__CSPI_SS0 0x2e8 0x670 0x78c 0x5 0x3 +-#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP 0x2e8 0x670 0x77c 0x7 0x1 +-#define MX53_PAD_SD1_CMD__ESDHC1_CMD 0x2ec 0x674 0x000 0x0 0x0 +-#define MX53_PAD_SD1_CMD__GPIO1_18 0x2ec 0x674 0x000 0x1 0x0 +-#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 0x2ec 0x674 0x000 0x3 0x0 +-#define MX53_PAD_SD1_CMD__CSPI_MOSI 0x2ec 0x674 0x788 0x5 0x2 +-#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP 0x2ec 0x674 0x770 0x7 0x0 +-#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x2f0 0x678 0x000 0x0 0x0 +-#define MX53_PAD_SD1_DATA2__GPIO1_19 0x2f0 0x678 0x000 0x1 0x0 +-#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 0x2f0 0x678 0x000 0x2 0x0 +-#define MX53_PAD_SD1_DATA2__PWM2_PWMO 0x2f0 0x678 0x000 0x3 0x0 +-#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B 0x2f0 0x678 0x000 0x4 0x0 +-#define MX53_PAD_SD1_DATA2__CSPI_SS1 0x2f0 0x678 0x790 0x5 0x2 +-#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB 0x2f0 0x678 0x000 0x6 0x0 +-#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP 0x2f0 0x678 0x774 0x7 0x0 +-#define MX53_PAD_SD1_CLK__ESDHC1_CLK 0x2f4 0x67c 0x000 0x0 0x0 +-#define MX53_PAD_SD1_CLK__GPIO1_20 0x2f4 0x67c 0x000 0x1 0x0 +-#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT 0x2f4 0x67c 0x000 0x2 0x0 +-#define MX53_PAD_SD1_CLK__GPT_CLKIN 0x2f4 0x67c 0x000 0x3 0x0 +-#define MX53_PAD_SD1_CLK__CSPI_SCLK 0x2f4 0x67c 0x780 0x5 0x2 +-#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 0x2f4 0x67c 0x000 0x7 0x0 +-#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x2f8 0x680 0x000 0x0 0x0 +-#define MX53_PAD_SD1_DATA3__GPIO1_21 0x2f8 0x680 0x000 0x1 0x0 +-#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 0x2f8 0x680 0x000 0x2 0x0 +-#define MX53_PAD_SD1_DATA3__PWM1_PWMO 0x2f8 0x680 0x000 0x3 0x0 +-#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B 0x2f8 0x680 0x000 0x4 0x0 +-#define MX53_PAD_SD1_DATA3__CSPI_SS2 0x2f8 0x680 0x794 0x5 0x2 +-#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB 0x2f8 0x680 0x000 0x6 0x0 +-#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 0x2f8 0x680 0x000 0x7 0x0 +-#define MX53_PAD_SD2_CLK__ESDHC2_CLK 0x2fc 0x688 0x000 0x0 0x0 +-#define MX53_PAD_SD2_CLK__GPIO1_10 0x2fc 0x688 0x000 0x1 0x0 +-#define MX53_PAD_SD2_CLK__KPP_COL_5 0x2fc 0x688 0x840 0x2 0x2 +-#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 0x2fc 0x688 0x73c 0x3 0x1 +-#define MX53_PAD_SD2_CLK__CSPI_SCLK 0x2fc 0x688 0x780 0x5 0x3 +-#define MX53_PAD_SD2_CLK__SCC_RANDOM_V 0x2fc 0x688 0x000 0x7 0x0 +-#define MX53_PAD_SD2_CMD__ESDHC2_CMD 0x300 0x68c 0x000 0x0 0x0 +-#define MX53_PAD_SD2_CMD__GPIO1_11 0x300 0x68c 0x000 0x1 0x0 +-#define MX53_PAD_SD2_CMD__KPP_ROW_5 0x300 0x68c 0x84c 0x2 0x1 +-#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC 0x300 0x68c 0x738 0x3 0x1 +-#define MX53_PAD_SD2_CMD__CSPI_MOSI 0x300 0x68c 0x788 0x5 0x3 +-#define MX53_PAD_SD2_CMD__SCC_RANDOM 0x300 0x68c 0x000 0x7 0x0 +-#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x304 0x690 0x000 0x0 0x0 +-#define MX53_PAD_SD2_DATA3__GPIO1_12 0x304 0x690 0x000 0x1 0x0 +-#define MX53_PAD_SD2_DATA3__KPP_COL_6 0x304 0x690 0x844 0x2 0x1 +-#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x304 0x690 0x740 0x3 0x1 +-#define MX53_PAD_SD2_DATA3__CSPI_SS2 0x304 0x690 0x794 0x5 0x3 +-#define MX53_PAD_SD2_DATA3__SJC_DONE 0x304 0x690 0x000 0x7 0x0 +-#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x308 0x694 0x000 0x0 0x0 +-#define MX53_PAD_SD2_DATA2__GPIO1_13 0x308 0x694 0x000 0x1 0x0 +-#define MX53_PAD_SD2_DATA2__KPP_ROW_6 0x308 0x694 0x850 0x2 0x1 +-#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x308 0x694 0x734 0x3 0x1 +-#define MX53_PAD_SD2_DATA2__CSPI_SS1 0x308 0x694 0x790 0x5 0x3 +-#define MX53_PAD_SD2_DATA2__SJC_FAIL 0x308 0x694 0x000 0x7 0x0 +-#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x30c 0x698 0x000 0x0 0x0 +-#define MX53_PAD_SD2_DATA1__GPIO1_14 0x30c 0x698 0x000 0x1 0x0 +-#define MX53_PAD_SD2_DATA1__KPP_COL_7 0x30c 0x698 0x848 0x2 0x1 +-#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x30c 0x698 0x744 0x3 0x1 +-#define MX53_PAD_SD2_DATA1__CSPI_SS0 0x30c 0x698 0x78c 0x5 0x4 +-#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO 0x30c 0x698 0x000 0x7 0x0 +-#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x310 0x69c 0x000 0x0 0x0 +-#define MX53_PAD_SD2_DATA0__GPIO1_15 0x310 0x69c 0x000 0x1 0x0 +-#define MX53_PAD_SD2_DATA0__KPP_ROW_7 0x310 0x69c 0x854 0x2 0x1 +-#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x310 0x69c 0x730 0x3 0x1 +-#define MX53_PAD_SD2_DATA0__CSPI_MISO 0x310 0x69c 0x784 0x5 0x3 +-#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT 0x310 0x69c 0x000 0x7 0x0 +-#define MX53_PAD_GPIO_0__CCM_CLKO 0x314 0x6a4 0x000 0x0 0x0 +-#define MX53_PAD_GPIO_0__GPIO1_0 0x314 0x6a4 0x000 0x1 0x0 +-#define MX53_PAD_GPIO_0__KPP_COL_5 0x314 0x6a4 0x840 0x2 0x3 +-#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x314 0x6a4 0x000 0x3 0x0 +-#define MX53_PAD_GPIO_0__EPIT1_EPITO 0x314 0x6a4 0x000 0x4 0x0 +-#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB 0x314 0x6a4 0x000 0x5 0x0 +-#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR 0x314 0x6a4 0x000 0x6 0x0 +-#define MX53_PAD_GPIO_0__CSU_TD 0x314 0x6a4 0x000 0x7 0x0 +-#define MX53_PAD_GPIO_1__ESAI1_SCKR 0x318 0x6a8 0x7dc 0x0 0x1 +-#define MX53_PAD_GPIO_1__GPIO1_1 0x318 0x6a8 0x000 0x1 0x0 +-#define MX53_PAD_GPIO_1__KPP_ROW_5 0x318 0x6a8 0x84c 0x2 0x2 +-#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK 0x318 0x6a8 0x000 0x3 0x0 +-#define MX53_PAD_GPIO_1__PWM2_PWMO 0x318 0x6a8 0x000 0x4 0x0 +-#define MX53_PAD_GPIO_1__WDOG2_WDOG_B 0x318 0x6a8 0x000 0x5 0x0 +-#define MX53_PAD_GPIO_1__ESDHC1_CD 0x318 0x6a8 0x000 0x6 0x0 +-#define MX53_PAD_GPIO_1__SRC_TESTER_ACK 0x318 0x6a8 0x000 0x7 0x0 +-#define MX53_PAD_GPIO_9__ESAI1_FSR 0x31c 0x6ac 0x7cc 0x0 0x1 +-#define MX53_PAD_GPIO_9__GPIO1_9 0x31c 0x6ac 0x000 0x1 0x0 +-#define MX53_PAD_GPIO_9__KPP_COL_6 0x31c 0x6ac 0x844 0x2 0x2 +-#define MX53_PAD_GPIO_9__CCM_REF_EN_B 0x31c 0x6ac 0x000 0x3 0x0 +-#define MX53_PAD_GPIO_9__PWM1_PWMO 0x31c 0x6ac 0x000 0x4 0x0 +-#define MX53_PAD_GPIO_9__WDOG1_WDOG_B 0x31c 0x6ac 0x000 0x5 0x0 +-#define MX53_PAD_GPIO_9__ESDHC1_WP 0x31c 0x6ac 0x7fc 0x6 0x1 +-#define MX53_PAD_GPIO_9__SCC_FAIL_STATE 0x31c 0x6ac 0x000 0x7 0x0 +-#define MX53_PAD_GPIO_3__ESAI1_HCKR 0x320 0x6b0 0x7d4 0x0 0x1 +-#define MX53_PAD_GPIO_3__GPIO1_3 0x320 0x6b0 0x000 0x1 0x0 +-#define MX53_PAD_GPIO_3__I2C3_SCL 0x320 0x6b0 0x824 0x2 0x1 +-#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN 0x320 0x6b0 0x000 0x3 0x0 +-#define MX53_PAD_GPIO_3__CCM_CLKO2 0x320 0x6b0 0x000 0x4 0x0 +-#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 0x320 0x6b0 0x000 0x5 0x0 +-#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x320 0x6b0 0x8a0 0x6 0x1 +-#define MX53_PAD_GPIO_3__MLB_MLBCLK 0x320 0x6b0 0x858 0x7 0x2 +-#define MX53_PAD_GPIO_6__ESAI1_SCKT 0x324 0x6b4 0x7e0 0x0 0x1 +-#define MX53_PAD_GPIO_6__GPIO1_6 0x324 0x6b4 0x000 0x1 0x0 +-#define MX53_PAD_GPIO_6__I2C3_SDA 0x324 0x6b4 0x828 0x2 0x1 +-#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 0x324 0x6b4 0x000 0x3 0x0 +-#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB 0x324 0x6b4 0x000 0x4 0x0 +-#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 0x324 0x6b4 0x000 0x5 0x0 +-#define MX53_PAD_GPIO_6__ESDHC2_LCTL 0x324 0x6b4 0x000 0x6 0x0 +-#define MX53_PAD_GPIO_6__MLB_MLBSIG 0x324 0x6b4 0x860 0x7 0x2 +-#define MX53_PAD_GPIO_2__ESAI1_FST 0x328 0x6b8 0x7d0 0x0 0x1 +-#define MX53_PAD_GPIO_2__GPIO1_2 0x328 0x6b8 0x000 0x1 0x0 +-#define MX53_PAD_GPIO_2__KPP_ROW_6 0x328 0x6b8 0x850 0x2 0x2 +-#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 0x328 0x6b8 0x000 0x3 0x0 +-#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 0x328 0x6b8 0x000 0x4 0x0 +-#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 0x328 0x6b8 0x000 0x5 0x0 +-#define MX53_PAD_GPIO_2__ESDHC2_WP 0x328 0x6b8 0x000 0x6 0x0 +-#define MX53_PAD_GPIO_2__MLB_MLBDAT 0x328 0x6b8 0x85c 0x7 0x2 +-#define MX53_PAD_GPIO_4__ESAI1_HCKT 0x32c 0x6bc 0x7d8 0x0 0x1 +-#define MX53_PAD_GPIO_4__GPIO1_4 0x32c 0x6bc 0x000 0x1 0x0 +-#define MX53_PAD_GPIO_4__KPP_COL_7 0x32c 0x6bc 0x848 0x2 0x2 +-#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 0x32c 0x6bc 0x000 0x3 0x0 +-#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 0x32c 0x6bc 0x000 0x4 0x0 +-#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 0x32c 0x6bc 0x000 0x5 0x0 +-#define MX53_PAD_GPIO_4__ESDHC2_CD 0x32c 0x6bc 0x000 0x6 0x0 +-#define MX53_PAD_GPIO_4__SCC_SEC_STATE 0x32c 0x6bc 0x000 0x7 0x0 +-#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 0x330 0x6c0 0x7ec 0x0 0x1 +-#define MX53_PAD_GPIO_5__GPIO1_5 0x330 0x6c0 0x000 0x1 0x0 +-#define MX53_PAD_GPIO_5__KPP_ROW_7 0x330 0x6c0 0x854 0x2 0x2 +-#define MX53_PAD_GPIO_5__CCM_CLKO 0x330 0x6c0 0x000 0x3 0x0 +-#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 0x330 0x6c0 0x000 0x4 0x0 +-#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 0x330 0x6c0 0x000 0x5 0x0 +-#define MX53_PAD_GPIO_5__I2C3_SCL 0x330 0x6c0 0x824 0x6 0x2 +-#define MX53_PAD_GPIO_5__CCM_PLL1_BYP 0x330 0x6c0 0x770 0x7 0x1 +-#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 0x334 0x6c4 0x7f4 0x0 0x1 +-#define MX53_PAD_GPIO_7__GPIO1_7 0x334 0x6c4 0x000 0x1 0x0 +-#define MX53_PAD_GPIO_7__EPIT1_EPITO 0x334 0x6c4 0x000 0x2 0x0 +-#define MX53_PAD_GPIO_7__CAN1_TXCAN 0x334 0x6c4 0x000 0x3 0x0 +-#define MX53_PAD_GPIO_7__UART2_TXD_MUX 0x334 0x6c4 0x000 0x4 0x0 +-#define MX53_PAD_GPIO_7__FIRI_RXD 0x334 0x6c4 0x80c 0x5 0x1 +-#define MX53_PAD_GPIO_7__SPDIF_PLOCK 0x334 0x6c4 0x000 0x6 0x0 +-#define MX53_PAD_GPIO_7__CCM_PLL2_BYP 0x334 0x6c4 0x774 0x7 0x1 +-#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 0x338 0x6c8 0x7f8 0x0 0x1 +-#define MX53_PAD_GPIO_8__GPIO1_8 0x338 0x6c8 0x000 0x1 0x0 +-#define MX53_PAD_GPIO_8__EPIT2_EPITO 0x338 0x6c8 0x000 0x2 0x0 +-#define MX53_PAD_GPIO_8__CAN1_RXCAN 0x338 0x6c8 0x760 0x3 0x2 +-#define MX53_PAD_GPIO_8__UART2_RXD_MUX 0x338 0x6c8 0x880 0x4 0x5 +-#define MX53_PAD_GPIO_8__FIRI_TXD 0x338 0x6c8 0x000 0x5 0x0 +-#define MX53_PAD_GPIO_8__SPDIF_SRCLK 0x338 0x6c8 0x000 0x6 0x0 +-#define MX53_PAD_GPIO_8__CCM_PLL3_BYP 0x338 0x6c8 0x778 0x7 0x1 +-#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 0x33c 0x6cc 0x7f0 0x0 0x1 +-#define MX53_PAD_GPIO_16__GPIO7_11 0x33c 0x6cc 0x000 0x1 0x0 +-#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT 0x33c 0x6cc 0x000 0x2 0x0 +-#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 0x33c 0x6cc 0x000 0x4 0x0 +-#define MX53_PAD_GPIO_16__SPDIF_IN1 0x33c 0x6cc 0x870 0x5 0x1 +-#define MX53_PAD_GPIO_16__I2C3_SDA 0x33c 0x6cc 0x828 0x6 0x2 +-#define MX53_PAD_GPIO_16__SJC_DE_B 0x33c 0x6cc 0x000 0x7 0x0 +-#define MX53_PAD_GPIO_17__ESAI1_TX0 0x340 0x6d0 0x7e4 0x0 0x1 +-#define MX53_PAD_GPIO_17__GPIO7_12 0x340 0x6d0 0x000 0x1 0x0 +-#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 0x340 0x6d0 0x868 0x2 0x1 +-#define MX53_PAD_GPIO_17__GPC_PMIC_RDY 0x340 0x6d0 0x810 0x3 0x1 +-#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG 0x340 0x6d0 0x000 0x4 0x0 +-#define MX53_PAD_GPIO_17__SPDIF_OUT1 0x340 0x6d0 0x000 0x5 0x0 +-#define MX53_PAD_GPIO_17__IPU_SNOOP2 0x340 0x6d0 0x000 0x6 0x0 +-#define MX53_PAD_GPIO_17__SJC_JTAG_ACT 0x340 0x6d0 0x000 0x7 0x0 +-#define MX53_PAD_GPIO_18__ESAI1_TX1 0x344 0x6d4 0x7e8 0x0 0x1 +-#define MX53_PAD_GPIO_18__GPIO7_13 0x344 0x6d4 0x000 0x1 0x0 +-#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 0x344 0x6d4 0x86c 0x2 0x1 +-#define MX53_PAD_GPIO_18__OWIRE_LINE 0x344 0x6d4 0x864 0x3 0x1 +-#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG 0x344 0x6d4 0x000 0x4 0x0 +-#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK 0x344 0x6d4 0x768 0x5 0x1 +-#define MX53_PAD_GPIO_18__ESDHC1_LCTL 0x344 0x6d4 0x000 0x6 0x0 +-#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST 0x344 0x6d4 0x000 0x7 0x0 +- +-#endif /* __DTS_IMX53_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm/imx53-ppd.dts b/scripts/dtc/include-prefixes/arm/imx53-ppd.dts +deleted file mode 100644 +index 37d0cffea99c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-ppd.dts ++++ /dev/null +@@ -1,1122 +0,0 @@ +-/* +- * Copyright 2014 General Electric Company +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include "imx53.dtsi" +-#include +- +-/ { +- model = "General Electric CS ONE"; +- compatible = "ge,imx53-cpuvo", "fsl,imx53"; +- +- aliases { +- spi0 = &cspi; +- spi1 = &ecspi1; +- spi2 = &ecspi2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@70000000 { +- device_type = "memory"; +- reg = <0x70000000 0x20000000>, +- <0xb0000000 0x20000000>; +- }; +- +- cko2_11M: sgtl-clock-cko2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <11289600>; +- }; +- +- achc_24M: achc-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- }; +- +- sgtlsound: sound { +- compatible = "fsl,imx53-cpuvo-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "imx53-cpuvo-sgtl5000"; +- ssi-controller = <&ssi2>; +- audio-codec = <&sgtl5000>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <2>; +- mux-ext-port = <6>; +- }; +- +- reg_sgtl5k: regulator-sgtl5k { +- compatible = "regulator-fixed"; +- regulator-name = "regulator-sgtl5k"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usbotg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- pinctrl-0 = <&pinctrl_usb_otg_vbus>; +- gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_vbus: regulator-usb-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usbh1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_usbh2_vbus: regulator-usbh2-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usbh2_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh2_vbus>; +- gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usbh3_vbus: regulator-usbh3-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usbh3_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh3_vbus>; +- gpio = <&gpio5 27 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_tsiref: regulator-tsiref { +- compatible = "regulator-fixed"; +- regulator-name = "tsiref"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- reg_3v3: regulator-3v3 { +- /* TPS54320 */ +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_3v3_lcd: regulator-3v3-lcd { +- /* MIC2009 */ +- compatible = "regulator-fixed"; +- regulator-name = "LCD_3V3"; +- vin-supply = <®_3v3>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- pwm_bl: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm2 0 50000>; +- brightness-levels = <0 2 5 7 10 12 15 17 20 22 25 28 30 33 35 +- 38 40 43 45 48 51 53 56 58 61 63 66 68 71 +- 73 76 79 81 84 86 89 91 94 96 99 102 104 +- 107 109 112 114 117 119 122 124 127 130 +- 132 135 137 140 142 145 147 150 153 155 +- 158 160 163 165 168 170 173 175 178 181 +- 183 186 188 191 193 196 198 201 204 206 +- 209 211 214 216 219 221 224 226 229 232 +- 234 237 239 242 244 247 249 252 255>; +- default-brightness-level = <0>; +- enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; +- power-supply = <®_3v3_lcd>; +- }; +- +- led-controller-1 { +- compatible = "pwm-leds"; +- +- led-1 { +- label = "alarm-brightness"; +- pwms = <&pwm1 0 100000>; +- max-brightness = <255>; +- }; +- }; +- +- led-controller-2 { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_alarmled_pins>; +- +- led-2 { +- label = "alarm:red"; +- gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; +- }; +- +- led-3 { +- label = "alarm:yellow"; +- gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; +- }; +- +- led-4 { +- label = "alarm:blue"; +- gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; +- }; +- +- led-5 { +- label = "alarm:silenced"; +- gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; +- }; +- +- gpio-restart { +- compatible = "gpio-restart"; +- gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; +- active-delay = <100>; +- inactive-delay = <10>; +- wait-delay = <100>; +- }; +- +- power-gpio-keys { +- compatible = "gpio-keys"; +- +- power-button { +- label = "Power button"; +- gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- }; +- }; +- +- touch-lock-key { +- compatible = "gpio-keys"; +- +- touch-lock-button { +- label = "Touch lock button"; +- gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- usbphy2: usbphy-2 { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <®_3v3>; +- reset-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; +- clock-names = "main_clk"; +- clock-frequency = <24000000>; +- clocks = <&clks IMX5_CLK_CKO2>; +- assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>; +- assigned-clock-parents = <&clks IMX5_CLK_OSC>; +- }; +- +- usbphy3: usbphy-3 { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <®_3v3>; +- reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; +- clock-names = "main_clk"; +- +- clock-frequency = <24000000>; +- clocks = <&clks IMX5_CLK_CKO2>; +- assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>; +- assigned-clock-parents = <&clks IMX5_CLK_OSC>; +- }; +- +- panel-lvds0 { +- compatible = "nvd,9128"; +- power-supply = <®_3v3_lcd>; +- +- port { +- panel_in_lvds0: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +-}; +- +-&usbphy0 { +- vcc-supply = <®_3v3>; +-}; +- +-&usbphy1 { +- vcc-supply = <®_3v3>; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&cpu0 { +- /* CPU rated to 1GHz, not 1.2GHz as per the default settings */ +- operating-points = < +- /* kHz uV */ +- 166666 850000 +- 400000 900000 +- 800000 1050000 +- 1000000 1200000 +- >; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW +- &gpio4 10 GPIO_ACTIVE_LOW +- &gpio4 11 GPIO_ACTIVE_LOW +- &gpio4 12 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- spidev0: spi@1 { +- compatible = "ge,achc", "nxp,kinetis-k20"; +- reg = <1>, <0>; +- vdd-supply = <®_3v3>; +- vdda-supply = <®_3v3>; +- clocks = <&achc_24M>; +- reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; +- }; +- +- gpioxra0: gpio@2 { +- compatible = "exar,xra1403"; +- reg = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- spi-max-frequency = <1000000>; +- }; +- +- gpioxra1: gpio@3 { +- compatible = "exar,xra1403"; +- reg = <3>; +- gpio-controller; +- #gpio-cells = <2>; +- spi-max-frequency = <1000000>; +- }; +-}; +- +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- da9053@0 { +- compatible = "dlg,da9053-aa"; +- reg = <0>; +- interrupt-parent = <&gpio3>; +- interrupts = <12 IRQ_TYPE_LEVEL_LOW>; +- spi-max-frequency = <1000000>; +- dlg,tsi-as-adc; +- tsiref-supply = <®_tsiref>; +- +- regulators { +- buck1_reg: buck1 { +- regulator-name = "BUCKCORE"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <2075000>; +- regulator-always-on; +- }; +- +- buck2_reg: buck2 { +- regulator-name = "BUCKPRO"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <2075000>; +- regulator-always-on; +- }; +- +- buck3_reg: buck3 { +- regulator-name = "BUCKMEM"; +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- buck4_reg: buck4 { +- regulator-name = "BUCKPERI"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3600000>; +- regulator-always-on; +- }; +- +- ldo1_reg: ldo1 { +- regulator-name = "ldo1_1v3"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo2_reg: ldo2 { +- regulator-name = "ldo2_1v3"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo3_reg: ldo3 { +- regulator-name = "ldo3_3v3"; +- regulator-min-microvolt = <1725000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo4_reg: ldo4 { +- regulator-name = "ldo4_2v775"; +- regulator-min-microvolt = <1725000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo5_reg: ldo5 { +- regulator-name = "ldo5_3v3"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3600000>; +- regulator-always-on; +- }; +- +- ldo6_reg: ldo6 { +- regulator-name = "ldo6_1v3"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3600000>; +- regulator-always-on; +- }; +- +- ldo7_reg: ldo7 { +- regulator-name = "ldo7_2v75"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3600000>; +- regulator-always-on; +- }; +- +- ldo8_reg: ldo8 { +- regulator-name = "ldo8_1v8"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3600000>; +- regulator-always-on; +- }; +- +- ldo9_reg: ldo9 { +- regulator-name = "ldo9_1v5"; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <3650000>; +- regulator-always-on; +- }; +- +- ldo10_reg: ldo10 { +- regulator-name = "ldo10_1v3"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3600000>; +- regulator-always-on; +- }; +- }; +- }; +- +-}; +- +-&esdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc3>; +- bus-width = <8>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-supply = <®_3v3>; +- phy-mode = "rmii"; +- phy-reset-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c1>; +- pinctrl-1 = <&pinctrl_i2c1_gpio>; +- sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- +- i2c-switch@70 { +- compatible = "nxp,pca9547"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- reset-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; +- +- i2c4: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0xa>; +- #sound-dai-cells = <0>; +- VDDA-supply = <®_sgtl5k>; +- VDDIO-supply = <®_sgtl5k>; +- clocks = <&cko2_11M>; +- status = "okay"; +- }; +- }; +- +- i2c5: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- rtc@30 { +- compatible = "sii,s35390a"; +- reg = <0x30>; +- }; +- +- temp@48 { +- compatible = "ti,tmp112"; +- reg = <0x48>; +- }; +- +- mma8453q: accelerometer@1c { +- compatible = "fsl,mma8453"; +- reg = <0x1c>; +- interrupt-parent = <&gpio1>; +- interrupts = <6 IRQ_TYPE_NONE>; +- interrupt-names = "INT1"; +- }; +- +- mpl3115: pressure-sensor@60 { +- compatible = "fsl,mpl3115"; +- reg = <0x60>; +- }; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c08"; +- reg = <0x50>; +- }; +- }; +- +- i2c6: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c7: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- i2c8: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- i2c9: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- i2c10: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- i2c11: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c2>; +- pinctrl-1 = <&pinctrl_i2c2_gpio>; +- sda-gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- +- touchscreen@4b { +- compatible = "atmel,maxtouch"; +- reset-gpio = <&gpio5 19 GPIO_ACTIVE_LOW>; +- reg = <0x4b>; +- interrupt-parent = <&gpio5>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c3 { +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c3>; +- pinctrl-1 = <&pinctrl_i2c3_gpio>; +- sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds0: lvds-channel@0 { +- status = "okay"; +- +- port@2 { +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in_lvds0>; +- }; +- }; +- }; +-}; +- +-&pmu { +- secure-reg-access; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&pwm2 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- status = "okay"; +-}; +- +-&ssi2 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- fsl,dma-info = <24 20>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- fsl,dma-info = <4096 4>; +- status = "okay"; +-}; +- +-&usbotg { +- dr_mode = "otg"; +- phy_type = "utmi"; +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-0 = <&pinctrl_usb_otg>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_vbus>; +- phy_type = "utmi"; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbh2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh2>; +- phy_type = "ulpi"; +- dr_mode = "host"; +- fsl,usbphy = <&usbphy2>; +- vbus-supply = <®_usbh2_vbus>; +- status = "okay"; +-}; +- +-&usbh3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh3>; +- phy_type = "ulpi"; +- dr_mode = "host"; +- vbus-supply = <®_usbh3_vbus>; +- fsl,usbphy = <&usbphy3>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog_rev6>; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 0x400 +- MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 0x400 +- MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 0x400 +- MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 0x400 +- MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x400 +- MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x400 +- MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x400 +- MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x400 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x400 +- MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x400 +- MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x400 +- /* ECSPI1_SS0, must treat as GPIO for EzPort */ +- MX53_PAD_DISP0_DAT23__GPIO5_17 0x400 +- MX53_PAD_KEY_COL2__GPIO4_10 0x0 +- MX53_PAD_KEY_ROW2__GPIO4_11 0x0 +- MX53_PAD_KEY_COL3__GPIO4_12 0x0 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x0 +- MX53_PAD_EIM_OE__ECSPI2_MISO 0x0 +- MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x0 +- MX53_PAD_EIM_RW__GPIO2_26 0x0 +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 +- MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 +- MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 +- MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 +- MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 +- MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 +- >; +- }; +- +- pinctrl_esdhc3: esdhc3grp { +- fsl,pins = < +- MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 +- MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 +- MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 +- MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 +- MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 +- MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 +- MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 +- MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 +- MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 +- MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX53_PAD_FEC_MDC__FEC_MDC 0x0 +- MX53_PAD_FEC_MDIO__FEC_MDIO 0x0 +- MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x0 +- MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x0 +- MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x0 +- MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x0 +- MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x0 +- MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x0 +- MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x0 +- MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x0 +- >; +- }; +- +- pinctrl_hog_rev6: hoggrp { +- fsl,pins = < +- /* CKO2 */ +- MX53_PAD_GPIO_3__CCM_CLKO2 0x4 +- /* DEFIB_SYNC_MARKER_IN_IRQ */ +- MX53_PAD_GPIO_5__GPIO1_5 0x0 +- /* ACCELEROMETER_DATA_RDY_N */ +- MX53_PAD_GPIO_6__GPIO1_6 0x0 +- /* TEMPERATURE_ALERT_N */ +- MX53_PAD_GPIO_7__GPIO1_7 0x0 +- /* BAROMETRIC_PRESSURE_DATA_RDY_N */ +- MX53_PAD_GPIO_8__GPIO1_8 0x0 +- /* DOCKING_I2C_INTERFACE_IRQ_N */ +- MX53_PAD_PATA_DATA4__GPIO2_4 0x0 +- /* PWR_OUT_TO_DOCK_FAULT_N */ +- MX53_PAD_PATA_DATA5__GPIO2_5 0x0 +- /* ENABLE_PWR_TO_DOCK_N */ +- MX53_PAD_PATA_DATA6__GPIO2_6 0x0 +- /* HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N */ +- MX53_PAD_PATA_DATA7__GPIO2_7 0x0 +- /* REMOTE_ON_REQUEST_FROM_DOCKING_CONNECTOR_IS_ACTIVE_N */ +- MX53_PAD_PATA_DATA12__GPIO2_12 0x0 +- /* DOCK_PRESENT_N */ +- MX53_PAD_PATA_DATA13__GPIO2_13 0x0 +- /* ECG_MARKER_IN_FROM_DOCKING_CONNECTOR_IRQ */ +- MX53_PAD_PATA_DATA14__GPIO2_14 0x0 +- /* ENABLE_ECG_MARKER_INTERFACE_TO_DOCKING_CONNECTOR */ +- MX53_PAD_PATA_DATA15__GPIO2_15 0x0 +- /* RESET_IMX535_ETHERNET_PHY_N */ +- MX53_PAD_EIM_A22__GPIO2_16 0x0 +- /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */ +- MX53_PAD_EIM_A21__GPIO2_17 0x0 +- /* RESET_I2C1_BUS_SEGMENT_MUX_N */ +- MX53_PAD_EIM_A20__GPIO2_18 0x0 +- /* RESET_IMX535_USB_HOST3_PHY_N */ +- MX53_PAD_EIM_A19__GPIO2_19 0x0 +- /* ESDHC3_EMMC_NAND_RST_N */ +- MX53_PAD_EIM_A18__GPIO2_20 0x0 +- /* LCD_AND_UI_INTERFACE_PWR_FAULT_N */ +- MX53_PAD_EIM_A17__GPIO2_21 0x0 +- /* POWER_DOWN_LVDS0_DESERIALIZER_N */ +- MX53_PAD_EIM_A16__GPIO2_22 0x0 +- /* POWER_DOWN_LVDS1_DESERIALIZER_N */ +- MX53_PAD_EIM_LBA__GPIO2_27 0x0 +- /* RESET_DP0_TRANSMITTER_N */ +- MX53_PAD_EIM_EB0__GPIO2_28 0x0 +- /* RESET_DP1_TRANSMITTER_N */ +- MX53_PAD_EIM_EB1__GPIO2_29 0x0 +- /* ENABLE_SPDIF_AUDIO_TO_DP0 */ +- MX53_PAD_EIM_DA0__GPIO3_0 0x0 +- /* ENABLE_SPDIF_AUDIO_TO_DP1 */ +- MX53_PAD_EIM_DA1__GPIO3_1 0x0 +- /* LVDS1_MUX_CTRL */ +- MX53_PAD_EIM_DA2__GPIO3_2 0x0 +- /* LVDS0_MUX_CTRL */ +- MX53_PAD_EIM_DA3__GPIO3_3 0x0 +- /* DP1_TRANSMITTER_IRQ */ +- MX53_PAD_EIM_DA4__GPIO3_4 0x0 +- /* DP0_TRANSMITTER_IRQ */ +- MX53_PAD_EIM_DA5__GPIO3_5 0x0 +- /* USB_RESET_N */ +- MX53_PAD_EIM_DA6__GPIO3_6 0x0 +- /* ENABLE_BATTERY_CHARGER */ +- MX53_PAD_EIM_DA7__GPIO3_7 0x0 +- /* SOFTWARE_CONTROLLED_PWR_CYCLE */ +- MX53_PAD_EIM_DA8__GPIO3_8 0x0 +- /* SOFTWARE_CONTROLLED_POWERDOWN */ +- MX53_PAD_EIM_DA9__GPIO3_9 0x0 +- /* DC_PWR_IN_OK */ +- MX53_PAD_EIM_DA10__GPIO3_10 0x0 +- /* BATT_PRESENT_N */ +- MX53_PAD_EIM_DA11__GPIO3_11 0xe4 +- /* PMIC_IRQ_N */ +- MX53_PAD_EIM_DA12__GPIO3_12 0x0 +- /* PMIC_VDD_FAULT_STATUS_N */ +- MX53_PAD_EIM_DA13__GPIO3_13 0x0 +- /* IMX535_ETHERNET_PHY_STATUS_IRQ_N */ +- MX53_PAD_EIM_DA14__GPIO3_14 0x0 +- /* NOT USED - AVAILABLE 3.3V GPIO */ +- MX53_PAD_EIM_DA15__GPIO3_15 0x0 +- /* NOT USED - AVAILABLE 3.3V GPIO */ +- MX53_PAD_EIM_D22__GPIO3_22 0x0 +- /* NOT USED - AVAILABLE 3.3V GPIO */ +- MX53_PAD_EIM_D24__GPIO3_24 0x0 +- /* NBP_PUMP_VALVE_PWR_ENABLE */ +- MX53_PAD_EIM_D25__GPIO3_25 0x0 +- /* NIBP_RESET_N */ +- MX53_PAD_EIM_D26__GPIO3_26 0x0 +- /* LATCHED_OVERPRESSURE_N */ +- MX53_PAD_EIM_D27__GPIO3_27 0x0 +- /* NBP_SBWTCLK */ +- MX53_PAD_EIM_D29__GPIO3_29 0x0 +- /* ENABLE_WIFI_MODULE */ +- MX53_PAD_GPIO_11__GPIO4_1 0x400 +- /* WIFI_MODULE_IRQ_N */ +- MX53_PAD_GPIO_12__GPIO4_2 0x400 +- /* ENABLE_BLUETOOTH_MODULE */ +- MX53_PAD_GPIO_13__GPIO4_3 0x400 +- /* RESET_IMX535_USB_HOST2_PHY_N */ +- MX53_PAD_GPIO_14__GPIO4_4 0x400 +- /* ONKEY_IS_DEPRESSED */ +- MX53_PAD_KEY_ROW3__GPIO4_13 0x0 +- /* UNUSED_GPIO_TO_ALARM_LIGHT_BOARD */ +- MX53_PAD_EIM_WAIT__GPIO5_0 0x0 +- /* DISPLAY_LOCK_BUTTON_IS_DEPRESSED_N */ +- MX53_PAD_EIM_A25__GPIO5_2 0x0 +- /* I2C_PCAP_TOUCHSCREEN_IRQ_N */ +- MX53_PAD_EIM_A24__GPIO5_4 0x0 +- /* NOT USED - AVAILABLE 1.8V GPIO */ +- MX53_PAD_DISP0_DAT13__GPIO5_7 0x400 +- /* NOT USED - AVAILABLE 1.8V GPIO */ +- MX53_PAD_DISP0_DAT14__GPIO5_8 0x400 +- /* NOT USED - AVAILABLE 1.8V GPIO */ +- MX53_PAD_DISP0_DAT15__GPIO5_9 0x400 +- /* HOST_CONTROLLED_RESET_TO_LCD_N */ +- MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x0 +- /* HOST_CONTROLLED_RESET_TO_PCAP_N */ +- MX53_PAD_CSI0_MCLK__GPIO5_19 0x0 +- /* LR_SCAN_CTRL */ +- MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x0 +- /* UD_SCAN_CTRL */ +- MX53_PAD_CSI0_VSYNC__GPIO5_21 0x0 +- /* DATA_WIDTH_CTRL */ +- MX53_PAD_CSI0_DAT10__GPIO5_28 0x0 +- /* BACKLIGHT_ENABLE */ +- MX53_PAD_CSI0_DAT11__GPIO5_29 0x0 +- /* MED_USB_PORT_1_HOST_SELECT */ +- MX53_PAD_EIM_A23__GPIO6_6 0x0 +- /* MED_USB_PORT_2_HOST_SELECT */ +- MX53_PAD_NANDF_CLE__GPIO6_7 0x0 +- /* MED_USB_PORT_3_HOST_SELECT */ +- MX53_PAD_NANDF_ALE__GPIO6_8 0x0 +- /* MED_USB_PORT_4_HOST_SELECT */ +- MX53_PAD_NANDF_WP_B__GPIO6_9 0x0 +- /* MED_USB_PORT_5_HOST_SELECT */ +- MX53_PAD_NANDF_RB0__GPIO6_10 0x0 +- /* MED_USB_PORT_6_HOST_SELECT */ +- MX53_PAD_NANDF_CS0__GPIO6_11 0x0 +- /* MED_USB_PORT_7_HOST_SELECT */ +- MX53_PAD_NANDF_WE_B__GPIO6_12 0x0 +- /* MED_USB_PORT_8_HOST_SELECT */ +- MX53_PAD_NANDF_RE_B__GPIO6_13 0x0 +- /* MED_USB_PORT_TO_IMX_SELECT_0 */ +- MX53_PAD_NANDF_CS1__GPIO6_14 0x0 +- /* MED_USB_PORT_TO_IMX_SELECT_1 */ +- MX53_PAD_NANDF_CS2__GPIO6_15 0x0 +- /* MED_USB_PORT_TO_IMX_SELECT_2 */ +- MX53_PAD_NANDF_CS3__GPIO6_16 0x0 +- /* POWER_AND_BOOT_STATUS_INDICATOR */ +- MX53_PAD_PATA_INTRQ__GPIO7_2 0x1e4 +- /* RUNNING_ON_BATTERY_INDICATOR_GREEN */ +- MX53_PAD_GPIO_16__GPIO7_11 0x0 +- /* BATTERY_STATUS_INDICATOR_AMBER */ +- MX53_PAD_GPIO_17__GPIO7_12 0x0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 +- MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 +- >; +- }; +- +- pinctrl_i2c1_gpio: i2c1gpiogrp { +- fsl,pins = < +- MX53_PAD_EIM_D28__GPIO3_28 0x1e4 +- MX53_PAD_EIM_D21__GPIO3_21 0x1e4 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX53_PAD_EIM_EB2__I2C2_SCL 0x400001e4 +- MX53_PAD_EIM_D16__I2C2_SDA 0x400001e4 +- >; +- }; +- +- pinctrl_i2c2_gpio: i2c2gpiogrp { +- fsl,pins = < +- MX53_PAD_EIM_D16__GPIO3_16 0x1e4 +- MX53_PAD_EIM_EB2__GPIO2_30 0x1e4 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX53_PAD_EIM_D17__I2C3_SCL 0x400001e4 +- MX53_PAD_EIM_D18__I2C3_SDA 0x400001e4 +- >; +- }; +- +- pinctrl_i2c3_gpio: i2c3gpiogrp { +- fsl,pins = < +- MX53_PAD_EIM_D18__GPIO3_18 0x1e4 +- MX53_PAD_EIM_D17__GPIO3_17 0x1e4 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX53_PAD_GPIO_9__PWM1_PWMO 0x5 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x5 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 +- MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 +- MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 +- MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 +- MX53_PAD_EIM_D23__UART3_CTS 0x1e4 +- MX53_PAD_EIM_EB3__UART3_RTS 0x1e4 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4 +- MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4 +- MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4 +- >; +- }; +- +- pinctrl_usb_otg_vbus: usb-otg-vbusgrp { +- fsl,pins = < +- /* USB_HS_OTG_VBUS_ENABLE */ +- MX53_PAD_KEY_ROW4__GPIO4_15 0x1c4 +- >; +- }; +- +- pinctrl_usbh2: usbh2grp { +- fsl,pins = < +- /* USB H2 */ +- MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x180 +- MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x180 +- MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x180 +- MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x180 +- MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x180 +- MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x180 +- MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x180 +- MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x180 +- MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x180 +- MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x180 +- MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x180 +- MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x5 +- MX53_PAD_EIM_D30__USBOH3_USBH2_OC 0x180 +- >; +- }; +- +- pinctrl_usbh2_vbus: usbh2-vbusgrp { +- fsl,pins = < +- /* USB_HS_HOST2_VBUS_ENABLE */ +- MX53_PAD_EIM_D31__GPIO3_31 0x0 +- >; +- }; +- +- pinctrl_usbh3_vbus: usbh3-vbusgrp { +- fsl,pins = < +- /* USB_HS_HOST3_VBUS_ENABLE */ +- MX53_PAD_CSI0_DAT9__GPIO5_27 0x0 +- >; +- }; +- +- pinctrl_usbh3: usbh3grp { +- fsl,pins = < +- /* USB H3 */ +- MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 0x180 +- MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 0x180 +- MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 0x180 +- MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 0x180 +- MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 0x180 +- MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 0x180 +- MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 0x180 +- MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 0x180 +- MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 0x5 +- MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 0x180 +- MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 0x180 +- MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 0x180 +- MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 0x180 +- >; +- }; +- +- pinctrl_usb_otg: usbotggrp { +- fsl,pins = < +- /* USB_OTG_FAULT_N */ +- MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x180 +- >; +- }; +- +- pinctrl_alarmled_pins: qmx6alarmledgrp { +- fsl,pins = < +- /* ACTIVATE_ALARM_LIGHT_RED */ +- MX53_PAD_PATA_DIOR__GPIO7_3 0x0 +- /* ACTIVATE_ALARM_LIGHT_YELLOW */ +- MX53_PAD_PATA_DA_1__GPIO7_7 0x0 +- /* ACTIVATE_ALARM_LIGHT_CYAN */ +- MX53_PAD_PATA_DA_2__GPIO7_8 0x0 +- /* AUDIO_ALARMS_SILENCED_INDICATOR */ +- MX53_PAD_GPIO_18__GPIO7_13 0x0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-qsb-common.dtsi b/scripts/dtc/include-prefixes/arm/imx53-qsb-common.dtsi +deleted file mode 100644 +index fe4244044a0f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-qsb-common.dtsi ++++ /dev/null +@@ -1,387 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2011 Freescale Semiconductor, Inc. +-// Copyright 2011 Linaro Ltd. +- +-#include "imx53.dtsi" +- +-/ { +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@70000000 { +- device_type = "memory"; +- reg = <0x70000000 0x20000000>, +- <0xb0000000 0x20000000>; +- }; +- +- display0: disp0 { +- compatible = "fsl,imx-parallel-display"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu_disp0>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- port@0 { +- reg = <0>; +- +- display0_in: endpoint { +- remote-endpoint = <&ipu_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "Power Button"; +- gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- volume-down { +- label = "Volume Down"; +- gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pin_gpio7_7>; +- +- user { +- label = "Heartbeat"; +- gpios = <&gpio7 7 0>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- panel { +- compatible = "sii,43wvf1g"; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_3p2v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "3P2V"; +- regulator-min-microvolt = <3200000>; +- regulator-max-microvolt = <3200000>; +- regulator-always-on; +- }; +- +- reg_usb_vbus: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "usb_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio7 8 0>; +- enable-active-high; +- }; +- }; +- +- sound { +- compatible = "fsl,imx53-qsb-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "imx53-qsb-sgtl5000"; +- ssi-controller = <&ssi2>; +- audio-codec = <&sgtl5000>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <2>; +- mux-ext-port = <5>; +- }; +-}; +- +-&cpu0 { +- /* CPU rated to 1GHz, not 1.2GHz as per the default settings */ +- operating-points = < +- /* kHz uV */ +- 166666 850000 +- 400000 900000 +- 800000 1050000 +- 1000000 1200000 +- >; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- cd-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&ipu_di0_disp0 { +- remote-endpoint = <&display0_in>; +-}; +- +-&ssi2 { +- status = "okay"; +-}; +- +-&esdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc3>; +- cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; +- bus-width = <8>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx53-qsb { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX53_PAD_GPIO_8__GPIO1_8 0x80000000 +- MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 +- MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 +- MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 +- MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 +- MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 +- MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 +- MX53_PAD_GPIO_16__GPIO7_11 0x80000000 +- >; +- }; +- +- led_pin_gpio7_7: led_gpio7_7 { +- fsl,pins = < +- MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 +- >; +- }; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 +- MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 +- MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 +- MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 +- >; +- }; +- +- pinctrl_codec: codecgrp { +- fsl,pins = < +- MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 +- MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 +- MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 +- MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 +- MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 +- MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 +- MX53_PAD_EIM_DA13__GPIO3_13 0xe4 +- >; +- }; +- +- pinctrl_esdhc3: esdhc3grp { +- fsl,pins = < +- MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 +- MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 +- MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 +- MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 +- MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 +- MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 +- MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 +- MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 +- MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 +- MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX53_PAD_FEC_MDC__FEC_MDC 0x4 +- MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc +- MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 +- MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 +- MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 +- MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 +- MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 +- MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 +- MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 +- MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 +- >; +- }; +- +- /* open drain */ +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec +- MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 +- MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 +- >; +- }; +- +- pinctrl_ipu_disp0: ipudisp0grp { +- fsl,pins = < +- MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 +- MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 +- MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 +- MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 +- MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 +- MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 +- MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 +- MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 +- MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 +- MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 +- MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 +- MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 +- MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 +- MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 +- MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 +- MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 +- MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 +- MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 +- MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 +- MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 +- MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 +- MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 +- MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 +- MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 +- MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 +- MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 +- MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 +- MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 +- >; +- }; +- +- pinctrl_vga_sync: vgasync-grp { +- fsl,pins = < +- /* VGA_HSYNC, VSYNC with max drive strength */ +- MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6 +- MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 +- MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 +- >; +- }; +- }; +-}; +- +-&tve { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_vga_sync>; +- ddc-i2c-bus = <&i2c2>; +- fsl,tve-mode = "vga"; +- fsl,hsync-pin = <7>; /* IPU DI1 PIN7 via EIM_OE */ +- fsl,vsync-pin = <8>; /* IPU DI1 PIN8 via EIM_RW */ +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_codec>; +- #sound-dai-cells = <0>; +- VDDA-supply = <®_3p2v>; +- VDDIO-supply = <®_3p2v>; +- clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- accelerometer: mma8450@1c { +- compatible = "fsl,mma8450"; +- reg = <0x1c>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-mode = "rmii"; +- phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&vpu { +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_vbus>; +- phy_type = "utmi"; +- status = "okay"; +-}; +- +-&usbotg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-qsb.dts b/scripts/dtc/include-prefixes/arm/imx53-qsb.dts +deleted file mode 100644 +index 6831836bd726..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-qsb.dts ++++ /dev/null +@@ -1,111 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2011 Freescale Semiconductor, Inc. +-// Copyright 2011 Linaro Ltd. +- +-/dts-v1/; +-#include "imx53-qsb-common.dtsi" +- +-/ { +- model = "Freescale i.MX53 Quick Start Board"; +- compatible = "fsl,imx53-qsb", "fsl,imx53"; +-}; +- +-&i2c1 { +- pmic: dialog@48 { +- compatible = "dlg,da9053-aa", "dlg,da9052"; +- reg = <0x48>; +- interrupt-parent = <&gpio7>; +- interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* low-level active IRQ at GPIO7_11 */ +- +- regulators { +- buck1_reg: buck1 { +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <2075000>; +- regulator-always-on; +- }; +- +- buck2_reg: buck2 { +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <2075000>; +- regulator-always-on; +- }; +- +- buck3_reg: buck3 { +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- buck4_reg: buck4 { +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- ldo1_reg: ldo1 { +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo2_reg: ldo2 { +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo3_reg: ldo3 { +- regulator-min-microvolt = <1725000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo4_reg: ldo4 { +- regulator-min-microvolt = <1725000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo5_reg: ldo5 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3600000>; +- regulator-always-on; +- }; +- +- ldo6_reg: ldo6 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3600000>; +- regulator-always-on; +- }; +- +- ldo7_reg: ldo7 { +- regulator-min-microvolt = <2750000>; +- regulator-max-microvolt = <2750000>; +- }; +- +- ldo8_reg: ldo8 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3600000>; +- regulator-always-on; +- }; +- +- ldo9_reg: ldo9 { +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <3600000>; +- regulator-always-on; +- }; +- +- ldo10_reg: ldo10 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3600000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&tve { +- dac-supply = <&ldo7_reg>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-qsrb.dts b/scripts/dtc/include-prefixes/arm/imx53-qsrb.dts +deleted file mode 100644 +index 1bbf24ad308a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-qsrb.dts ++++ /dev/null +@@ -1,149 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2011 Freescale Semiconductor, Inc. +-// Copyright 2011 Linaro Ltd. +- +-/dts-v1/; +- +-#include "imx53-qsb-common.dtsi" +- +-/ { +- model = "Freescale i.MX53 Quick Start-R Board"; +- compatible = "fsl,imx53-qsrb", "fsl,imx53"; +-}; +- +-&iomuxc { +- imx53-qsrb { +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4 /* IRQ */ +- >; +- }; +- }; +-}; +- +-&i2c1 { +- pmic: mc34708@8 { +- compatible = "fsl,mc34708"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- reg = <0x08>; +- interrupt-parent = <&gpio5>; +- interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; +- regulators { +- sw1_reg: sw1a { +- regulator-name = "SW1"; +- regulator-min-microvolt = <650000>; +- regulator-max-microvolt = <1437500>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw1b_reg: sw1b { +- regulator-name = "SW1B"; +- regulator-min-microvolt = <650000>; +- regulator-max-microvolt = <1437500>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw2_reg: sw2 { +- regulator-name = "SW2"; +- regulator-min-microvolt = <650000>; +- regulator-max-microvolt = <1437500>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3_reg: sw3 { +- regulator-name = "SW3"; +- regulator-min-microvolt = <650000>; +- regulator-max-microvolt = <1425000>; +- regulator-boot-on; +- }; +- +- sw4a_reg: sw4a { +- regulator-name = "SW4A"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4b_reg: sw4b { +- regulator-name = "SW4B"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw5_reg: sw5 { +- regulator-name = "SW5"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-name = "SWBST"; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vpll_reg: vpll { +- regulator-name = "VPLL"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- }; +- +- vrefddr_reg: vrefddr { +- regulator-name = "VREFDDR"; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vusb_reg: vusb { +- regulator-name = "VUSB"; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vusb2_reg: vusb2 { +- regulator-name = "VUSB2"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdac_reg: vdac { +- regulator-name = "VDAC"; +- regulator-min-microvolt = <2750000>; +- regulator-max-microvolt = <2750000>; +- }; +- +- vgen1_reg: vgen1 { +- regulator-name = "VGEN1"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1550000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen2_reg: vgen2 { +- regulator-name = "VGEN2"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&tve { +- dac-supply = <&vdac_reg>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-smd.dts b/scripts/dtc/include-prefixes/arm/imx53-smd.dts +deleted file mode 100644 +index 9be44e807188..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-smd.dts ++++ /dev/null +@@ -1,346 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2011 Freescale Semiconductor, Inc. +-// Copyright 2011 Linaro Ltd. +- +-/dts-v1/; +-#include +-#include "imx53.dtsi" +- +-/ { +- model = "Freescale i.MX53 Smart Mobile Reference Design Board"; +- compatible = "fsl,imx53-smd", "fsl,imx53"; +- +- memory@70000000 { +- device_type = "memory"; +- reg = <0x70000000 0x40000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&gpio2 14 0>; +- linux,code = ; +- }; +- +- volume-down { +- label = "Volume Down"; +- gpios = <&gpio2 15 0>; +- linux,code = ; +- }; +- }; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- cd-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&esdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc2>; +- non-removable; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- zigbee: mc1323@0 { +- compatible = "fsl,mc1323"; +- spi-max-frequency = <8000000>; +- reg = <0>; +- }; +- +- flash: m25p32@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p32", "st,m25p", "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0x0 0x40000>; +- read-only; +- }; +- +- partition@40000 { +- label = "Kernel"; +- reg = <0x40000 0x3c0000>; +- }; +- }; +-}; +- +-&esdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc3>; +- non-removable; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx53-smd { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 +- MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 +- MX53_PAD_EIM_EB2__GPIO2_30 0x80000000 +- MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 +- MX53_PAD_EIM_D19__GPIO3_19 0x80000000 +- MX53_PAD_KEY_ROW2__GPIO4_11 0x80000000 +- MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 +- MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 +- MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 +- MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 +- MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 +- MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 +- MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 +- MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 +- >; +- }; +- +- pinctrl_esdhc2: esdhc2grp { +- fsl,pins = < +- MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 +- MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 +- MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 +- MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 +- MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 +- MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 +- >; +- }; +- +- pinctrl_esdhc3: esdhc3grp { +- fsl,pins = < +- MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 +- MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 +- MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 +- MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 +- MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 +- MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 +- MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 +- MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 +- MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 +- MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 +- MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 +- MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 +- MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 +- MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 +- MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 +- MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 +- MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 +- MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 +- MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 +- MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 +- MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 +- >; +- }; +- +- pinctrl_ipu_csi0: ipucsi0grp { +- fsl,pins = < +- MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1c4 +- MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1c4 +- MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1c4 +- MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1c4 +- MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1c4 +- MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1c4 +- MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1c4 +- MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1c4 +- MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1e4 +- MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1e4 +- MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1e4 +- MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1e4 +- >; +- }; +- +- pinctrl_ov5642: ov5642grp { +- fsl,pins = < +- MX53_PAD_NANDF_WP_B__GPIO6_9 0x1e4 +- MX53_PAD_NANDF_RB0__GPIO6_10 0x1e4 +- MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 +- MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 +- MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 +- MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 +- MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 +- MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 +- >; +- }; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- codec: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- }; +- +- magnetometer: mag3110@e { +- compatible = "fsl,mag3110"; +- reg = <0x0e>; +- }; +- +- touchkey: mpr121@5a { +- compatible = "fsl,mpr121"; +- reg = <0x5a>; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- accelerometer: mma8450@1c { +- compatible = "fsl,mma8450"; +- reg = <0x1c>; +- }; +- +- camera: ov5642@3c { +- compatible = "ovti,ov5642"; +- reg = <0x3c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ov5642>; +- assigned-clocks = <&clks IMX5_CLK_SSI_EXT1_SEL>, +- <&clks IMX5_CLK_SSI_EXT1_COM_SEL>; +- assigned-clock-parents = <&clks IMX5_CLK_PLL2_SW>, +- <&clks IMX5_CLK_SSI_EXT1_PODF>; +- assigned-clock-rates = <0>, <24000000>; +- clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; +- clock-names = "xclk"; +- DVDD-supply = <&ldo9_reg>; +- AVDD-supply = <&ldo7_reg>; +- reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; +- powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; +- +- port { +- ov5642_to_ipu_csi0: endpoint { +- remote-endpoint = <&ipu_csi0_from_parallel_sensor>; +- bus-width = <8>; +- hsync-active = <1>; +- vsync-active = <1>; +- }; +- }; +- }; +- +- pmic: dialog@48 { +- compatible = "dlg,da9053", "dlg,da9052"; +- reg = <0x48>; +- interrupt-parent = <&gpio7>; +- interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +- +- regulators { +- ldo7_reg: ldo7 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3600000>; +- }; +- +- ldo9_reg: ldo9 { +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <3650000>; +- }; +- }; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-mode = "rmii"; +- phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&ipu_csi0_from_parallel_sensor { +- remote-endpoint = <&ov5642_to_ipu_csi0>; +- data-shift = <12>; /* Lines 19:12 used */ +- hsync-active = <1>; +- vsync-active = <1>; +-}; +- +-&ipu_csi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu_csi0>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-tqma53.dtsi b/scripts/dtc/include-prefixes/arm/imx53-tqma53.dtsi +deleted file mode 100644 +index 7e7f9f3b3906..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-tqma53.dtsi ++++ /dev/null +@@ -1,289 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Sascha Hauer , Pengutronix +- * Copyright 2012 Steffen Trumtrar , Pengutronix +- */ +- +-#include "imx53.dtsi" +- +-/ { +- model = "TQ TQMa53"; +- compatible = "tq,tqma53", "fsl,imx53"; +- +- memory@70000000 { +- device_type = "memory"; +- reg = <0x70000000 0x40000000>; /* Up to 1GiB */ +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_3p3v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +-}; +- +-&esdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc2>, +- <&pinctrl_esdhc2_cdwp>; +- vmmc-supply = <®_3p3v>; +- wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- status = "disabled"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "disabled"; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>, +- <&gpio3 24 GPIO_ACTIVE_LOW>, <&gpio3 25 GPIO_ACTIVE_LOW>; +- status = "disabled"; +-}; +- +-&esdhc3 { /* EMMC */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc3>; +- vmmc-supply = <®_3p3v>; +- non-removable; +- bus-width = <8>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx53-tqma53 { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */ +- MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 /* LCD_BLT_EN */ +- MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 /* LCD_RESET */ +- MX53_PAD_PATA_DATA5__GPIO2_5 0x80000000 /* LCD_POWER */ +- MX53_PAD_PATA_DATA6__GPIO2_6 0x80000000 /* PMIC_INT */ +- MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 /* CSI_RST */ +- MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 /* CSI_PWDN */ +- MX53_PAD_GPIO_19__GPIO4_5 0x80000000 /* #SYSTEM_DOWN */ +- MX53_PAD_GPIO_3__GPIO1_3 0x80000000 +- MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 /* #PHY_RESET */ +- MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */ +- >; +- }; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 +- MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 +- MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 +- MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 +- >; +- }; +- +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000 +- MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000 +- >; +- }; +- +- pinctrl_can2: can2grp { +- fsl,pins = < +- MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 +- MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 +- >; +- }; +- +- pinctrl_cspi: cspigrp { +- fsl,pins = < +- MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5 +- MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5 +- MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 +- MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 +- MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 +- >; +- }; +- +- pinctrl_esdhc2: esdhc2grp { +- fsl,pins = < +- MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 +- MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 +- MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 +- MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 +- MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 +- MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 +- >; +- }; +- +- pinctrl_esdhc2_cdwp: esdhc2cdwp { +- fsl,pins = < +- MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */ +- MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */ +- >; +- }; +- +- pinctrl_esdhc3: esdhc3grp { +- fsl,pins = < +- MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 +- MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 +- MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 +- MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 +- MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 +- MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 +- MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 +- MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 +- MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 +- MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 +- MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 +- MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 +- MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 +- MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 +- MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 +- MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 +- MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 +- MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 +- MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 +- MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 +- MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 +- MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 +- MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 +- MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 +- >; +- }; +- }; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +-}; +- +-&pwm2 { +- #pwm-cells = <2>; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; +- status = "disabled"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "disabled"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- status = "disabled"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can2>; +- status = "disabled"; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "disabled"; +-}; +- +-&cspi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_cspi>; +- cs-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>, <&gpio1 19 GPIO_ACTIVE_LOW>, +- <&gpio1 21 GPIO_ACTIVE_LOW>; +- status = "disabled"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- pmic: mc34708@8 { +- compatible = "fsl,mc34708"; +- reg = <0x8>; +- fsl,mc13xxx-uses-rtc; +- interrupt-parent = <&gpio2>; +- interrupts = <6 4>; /* PATA_DATA6, active high */ +- }; +- +- sensor1: lm75@48 { +- compatible = "lm75"; +- reg = <0x48>; +- }; +- +- eeprom: 24c64@50 { +- compatible = "atmel,24c64"; +- pagesize = <32>; +- reg = <0x50>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-mode = "rmii"; +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-tx53-x03x.dts b/scripts/dtc/include-prefixes/arm/imx53-tx53-x03x.dts +deleted file mode 100644 +index a7f77527269d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-tx53-x03x.dts ++++ /dev/null +@@ -1,351 +0,0 @@ +-/* +- * Copyright 2013-2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx53-tx53.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "Ka-Ro electronics TX53 module (LCD)"; +- compatible = "karo,tx53", "fsl,imx53"; +- +- aliases { +- display = &display; +- }; +- +- display: disp0 { +- compatible = "fsl,imx-parallel-display"; +- interface-pix-fmt = "rgb24"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgb24_vga1>; +- status = "okay"; +- +- port { +- display0_in: endpoint { +- remote-endpoint = <&ipu_di0_disp0>; +- }; +- }; +- +- display-timings { +- VGA { +- clock-frequency = <25200000>; +- hactive = <640>; +- vactive = <480>; +- hback-porch = <48>; +- hsync-len = <96>; +- hfront-porch = <16>; +- vback-porch = <31>; +- vsync-len = <2>; +- vfront-porch = <12>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- +- ETV570 { +- clock-frequency = <25200000>; +- hactive = <640>; +- vactive = <480>; +- hback-porch = <114>; +- hsync-len = <30>; +- hfront-porch = <16>; +- vback-porch = <32>; +- vsync-len = <3>; +- vfront-porch = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- +- ET0350 { +- clock-frequency = <6413760>; +- hactive = <320>; +- vactive = <240>; +- hback-porch = <34>; +- hsync-len = <34>; +- hfront-porch = <20>; +- vback-porch = <15>; +- vsync-len = <3>; +- vfront-porch = <4>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- +- ET0430 { +- clock-frequency = <9009000>; +- hactive = <480>; +- vactive = <272>; +- hback-porch = <2>; +- hsync-len = <41>; +- hfront-porch = <2>; +- vback-porch = <2>; +- vsync-len = <10>; +- vfront-porch = <2>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- +- ET0500 { +- clock-frequency = <33264000>; +- hactive = <800>; +- vactive = <480>; +- hback-porch = <88>; +- hsync-len = <128>; +- hfront-porch = <40>; +- vback-porch = <33>; +- vsync-len = <2>; +- vfront-porch = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- +- ET0700 { /* same as ET0500 */ +- clock-frequency = <33264000>; +- hactive = <800>; +- vactive = <480>; +- hback-porch = <88>; +- hsync-len = <128>; +- hfront-porch = <40>; +- vback-porch = <33>; +- vsync-len = <2>; +- vfront-porch = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- +- ETQ570 { +- clock-frequency = <6596040>; +- hactive = <320>; +- vactive = <240>; +- hback-porch = <38>; +- hsync-len = <30>; +- hfront-porch = <30>; +- vback-porch = <16>; +- vsync-len = <3>; +- vfront-porch = <4>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- }; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; +- power-supply = <®_3v3>; +- brightness-levels = < +- 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100 +- >; +- default-brightness-level = <50>; +- }; +- +- reg_lcd_pwr: regulator-lcd-pwr { +- compatible = "regulator-fixed"; +- regulator-name = "LCD POWER"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-boot-on; +- }; +- +- reg_lcd_reset: regulator-lcd-reset { +- compatible = "regulator-fixed"; +- regulator-name = "LCD RESET"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-boot-on; +- }; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- VDDA-supply = <®_2v5>; +- VDDIO-supply = <®_3v3>; +- clocks = <&mclk>; +- }; +- +- polytouch: edt-ft5x06@38 { +- compatible = "edt,edt-ft5x06"; +- reg = <0x38>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_edt_ft5x06_1>; +- interrupt-parent = <&gpio6>; +- interrupts = <15 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; +- wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; +- wakeup-source; +- }; +- +- touchscreen: tsc2007@48 { +- compatible = "ti,tsc2007"; +- reg = <0x48>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tsc2007>; +- interrupt-parent = <&gpio3>; +- interrupts = <26 IRQ_TYPE_EDGE_FALLING>; +- gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; +- ti,x-plate-ohms = <660>; +- wakeup-source; +- }; +-}; +- +-&iomuxc { +- imx53-tx53-x03x { +- pinctrl_edt_ft5x06_1: edt-ft5x06grp-1 { +- fsl,pins = < +- MX53_PAD_NANDF_CS2__GPIO6_15 0x1f0 /* Interrupt */ +- MX53_PAD_EIM_A16__GPIO2_22 0x04 /* Reset */ +- MX53_PAD_EIM_A17__GPIO2_21 0x04 /* Wake */ +- >; +- }; +- +- pinctrl_kpp: kppgrp { +- fsl,pins = < +- MX53_PAD_GPIO_9__KPP_COL_6 0x1f4 +- MX53_PAD_GPIO_4__KPP_COL_7 0x1f4 +- MX53_PAD_KEY_COL2__KPP_COL_2 0x1f4 +- MX53_PAD_KEY_COL3__KPP_COL_3 0x1f4 +- MX53_PAD_GPIO_2__KPP_ROW_6 0x1f4 +- MX53_PAD_GPIO_5__KPP_ROW_7 0x1f4 +- MX53_PAD_KEY_ROW2__KPP_ROW_2 0x1f4 +- MX53_PAD_KEY_ROW3__KPP_ROW_3 0x1f4 +- >; +- }; +- +- pinctrl_rgb24_vga1: rgb24-vgagrp1 { +- fsl,pins = < +- MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 +- MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 +- MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 +- MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 +- MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 +- MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 +- MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 +- MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 +- MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 +- MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 +- MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 +- MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 +- MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 +- MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 +- MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 +- MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 +- MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 +- MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 +- MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 +- MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 +- MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 +- MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 +- MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 +- MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 +- MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 +- MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 +- MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 +- MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 +- >; +- }; +- +- pinctrl_tsc2007: tsc2007grp { +- fsl,pins = < +- MX53_PAD_EIM_D26__GPIO3_26 0x1f0 /* Interrupt */ +- >; +- }; +- }; +-}; +- +-&ipu_di0_disp0 { +- remote-endpoint = <&display0_in>; +-}; +- +-&kpp { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_kpp>; +- /* sample keymap */ +- /* row/col 0,1 are mapped to KPP row/col 6,7 */ +- linux,keymap = < +- MATRIX_KEY(6, 6, KEY_POWER) +- MATRIX_KEY(6, 7, KEY_KP0) +- MATRIX_KEY(6, 2, KEY_KP1) +- MATRIX_KEY(6, 3, KEY_KP2) +- MATRIX_KEY(7, 6, KEY_KP3) +- MATRIX_KEY(7, 7, KEY_KP4) +- MATRIX_KEY(7, 2, KEY_KP5) +- MATRIX_KEY(7, 3, KEY_KP6) +- MATRIX_KEY(2, 6, KEY_KP7) +- MATRIX_KEY(2, 7, KEY_KP8) +- MATRIX_KEY(2, 2, KEY_KP9) +- >; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-tx53-x13x.dts b/scripts/dtc/include-prefixes/arm/imx53-tx53-x13x.dts +deleted file mode 100644 +index 6cdf2082c742..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-tx53-x13x.dts ++++ /dev/null +@@ -1,262 +0,0 @@ +-/* +- * Copyright 2013-2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * The code contained herein is licensed under the GNU General Public +- * License. You may obtain a copy of the GNU General Public License +- * Version 2 at the following locations: +- * +- * http://www.opensource.org/licenses/gpl-license.html +- * http://www.gnu.org/copyleft/gpl.html +- */ +- +-/dts-v1/; +-#include "imx53-tx53.dtsi" +-#include +- +-/ { +- model = "Ka-Ro electronics TX53 module (LVDS)"; +- compatible = "karo,tx53", "fsl,imx53"; +- +- aliases { +- display = &lvds0; +- lvds0 = &lvds0; +- lvds1 = &lvds1; +- }; +- +- backlight0: backlight0 { +- compatible = "pwm-backlight"; +- pwms = <&pwm2 0 500000 0>; +- power-supply = <®_3v3>; +- brightness-levels = < +- 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100 +- >; +- default-brightness-level = <50>; +- }; +- +- backlight1: backlight1 { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 500000 0>; +- power-supply = <®_3v3>; +- brightness-levels = < +- 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100 +- >; +- default-brightness-level = <50>; +- }; +- +- reg_lcd_pwr0: regulator-lvds0-pwr { +- compatible = "regulator-fixed"; +- regulator-name = "LVDS0 POWER"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-boot-on; +- }; +- +- reg_lcd_pwr1: regulator-lvds1-pwr { +- compatible = "regulator-fixed"; +- regulator-name = "LVDS1 POWER"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-boot-on; +- }; +-}; +- +-&i2c3 { +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c3>; +- pinctrl-1 = <&pinctrl_i2c3_gpio>; +- scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; +- sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- VDDA-supply = <®_2v5>; +- VDDIO-supply = <®_3v3>; +- clocks = <&mclk>; +- }; +-}; +- +-&iomuxc { +- imx53-tx53-x13x { +- pinctrl_lvds0: lvds0grp { +- fsl,pins = < +- MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 +- MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 +- MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 +- MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 +- MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 +- >; +- }; +- +- pinctrl_lvds1: lvds1grp { +- fsl,pins = < +- MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 +- MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 +- MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 +- MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 +- MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = ; +- }; +- +- pinctrl_eeti1: eeti1grp { +- fsl,pins = < +- MX53_PAD_EIM_D22__GPIO3_22 0x1f0 /* Interrupt */ +- >; +- }; +- +- pinctrl_eeti2: eeti2grp { +- fsl,pins = < +- MX53_PAD_EIM_D23__GPIO3_23 0x1f0 /* Interrupt */ +- >; +- }; +- }; +-}; +- +-&ldb { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lvds0 &pinctrl_lvds1>; +- status = "okay"; +- +- lvds0: lvds-channel@0 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <18>; +- status = "okay"; +- +- display-timings { +- native-mode = <&lvds0_timing0>; +- +- lvds0_timing0: hsd100pxn1 { +- clock-frequency = <65000000>; +- hactive = <1024>; +- vactive = <768>; +- hback-porch = <220>; +- hsync-len = <60>; +- hfront-porch = <40>; +- vback-porch = <21>; +- vsync-len = <10>; +- vfront-porch = <7>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- +- lvds0_timing1: nl12880bc20 { +- clock-frequency = <71000000>; +- hactive = <1280>; +- vactive = <800>; +- hback-porch = <50>; +- hsync-len = <60>; +- hfront-porch = <50>; +- vback-porch = <5>; +- vsync-len = <13>; +- vfront-porch = <5>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- }; +- +- lvds1: lvds-channel@1 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <18>; +- status = "okay"; +- +- display-timings { +- native-mode = <&lvds1_timing0>; +- +- lvds1_timing0: hsd100pxn1 { +- clock-frequency = <65000000>; +- hactive = <1024>; +- vactive = <768>; +- hback-porch = <220>; +- hsync-len = <60>; +- hfront-porch = <40>; +- vback-porch = <21>; +- vsync-len = <10>; +- vfront-porch = <7>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- }; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-tx53.dtsi b/scripts/dtc/include-prefixes/arm/imx53-tx53.dtsi +deleted file mode 100644 +index 7c9730f3f820..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-tx53.dtsi ++++ /dev/null +@@ -1,595 +0,0 @@ +-/* +- * Copyright 2012-2017 +- * based on imx53-qsb.dts +- * Copyright 2011 Freescale Semiconductor, Inc. +- * Copyright 2011 Linaro Ltd. +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "imx53.dtsi" +-#include +- +-/ { +- model = "Ka-Ro electronics TX53 module"; +- compatible = "karo,tx53", "fsl,imx53"; +- +- /* Will be filled by the bootloader */ +- memory@70000000 { +- device_type = "memory"; +- reg = <0x70000000 0>; +- }; +- +- aliases { +- can0 = &can2; /* Make the can interface indices consistent with TX28/TX48 modules */ +- can1 = &can1; +- ipu = &ipu; +- reg-can-xcvr = ®_can_xcvr; +- usbh1 = &usbh1; +- usbotg = &usbotg; +- }; +- +- clocks { +- ckih1 { +- clock-frequency = <0>; +- }; +- }; +- +- mclk: clock-mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_key>; +- +- power { +- label = "Power Button"; +- gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; +- linux,code = <116>; /* KEY_POWER */ +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_stk5led>; +- +- user { +- label = "Heartbeat"; +- gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- reg_2v5: regulator-2v5 { +- compatible = "regulator-fixed"; +- regulator-name = "2V5"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_can_xcvr: regulator-can-xcvr { +- compatible = "regulator-fixed"; +- regulator-name = "CAN XCVR"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can_xcvr>; +- gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_usbh1_vbus: regulator-usbh1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usbh1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1_vbus>; +- gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usbotg_vbus: regulator-usbotg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usbotg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg_vbus>; +- gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sound { +- compatible = "karo,tx53-audio-sgtl5000", "fsl,imx-audio-sgtl5000"; +- model = "tx53-audio-sgtl5000"; +- ssi-controller = <&ssi1>; +- audio-codec = <&sgtl5000>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- /* '1' based port numbers according to datasheet names */ +- mux-int-port = <1>; +- mux-ext-port = <5>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssi1>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- xceiver-supply = <®_can_xcvr>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can2>; +- xceiver-supply = <®_can_xcvr>; +- status = "okay"; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- cs-gpios = < +- &gpio2 30 GPIO_ACTIVE_HIGH +- &gpio3 19 GPIO_ACTIVE_HIGH +- >; +- +- spidev0: spi@0 { +- compatible = "spidev"; +- reg = <0>; +- spi-max-frequency = <54000000>; +- }; +- +- spidev1: spi@1 { +- compatible = "spidev"; +- reg = <1>; +- spi-max-frequency = <54000000>; +- }; +-}; +- +-&esdhc1 { +- cd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; +- fsl,wp-controller; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- status = "okay"; +-}; +- +-&esdhc2 { +- cd-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; +- fsl,wp-controller; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc2>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-mode = "rmii"; +- phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; +- phy-handle = <&phy0>; +- mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */ +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- interrupt-parent = <&gpio2>; +- interrupts = <4 IRQ_TYPE_EDGE_FALLING>; +- device_type = "ethernet-phy"; +- }; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c1>; +- pinctrl-0 = <&pinctrl_i2c1_gpio>; +- scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; +- sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; +- clock-frequency = <400000>; +- status = "okay"; +- +- rtc1: ds1339@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ds1339>; +- interrupt-parent = <&gpio4>; +- interrupts = <20 IRQ_TYPE_EDGE_FALLING>; +- trickle-resistor-ohms = <250>; +- trickle-diode-disable; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx53-tx53 { +- pinctrl_hog: hoggrp { +- /* pins not in use by any device on the Starterkit board series */ +- fsl,pins = < +- /* CMOS Sensor Interface */ +- MX53_PAD_CSI0_DAT12__GPIO5_30 0x1f4 +- MX53_PAD_CSI0_DAT13__GPIO5_31 0x1f4 +- MX53_PAD_CSI0_DAT14__GPIO6_0 0x1f4 +- MX53_PAD_CSI0_DAT15__GPIO6_1 0x1f4 +- MX53_PAD_CSI0_DAT16__GPIO6_2 0x1f4 +- MX53_PAD_CSI0_DAT17__GPIO6_3 0x1f4 +- MX53_PAD_CSI0_DAT18__GPIO6_4 0x1f4 +- MX53_PAD_CSI0_DAT19__GPIO6_5 0x1f4 +- MX53_PAD_CSI0_MCLK__GPIO5_19 0x1f4 +- MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1f4 +- MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1f4 +- MX53_PAD_GPIO_0__GPIO1_0 0x1f4 +- /* Module Specific Signal */ +- /* MX53_PAD_NANDF_CS2__GPIO6_15 0x1f4 maybe used by EDT-FT5x06 */ +- /* MX53_PAD_EIM_A16__GPIO2_22 0x1f4 maybe used by EDT-FT5x06 */ +- MX53_PAD_EIM_D29__GPIO3_29 0x1f4 +- MX53_PAD_EIM_EB3__GPIO2_31 0x1f4 +- /* MX53_PAD_EIM_A17__GPIO2_21 0x1f4 maybe used by EDT-FT5x06 */ +- /* MX53_PAD_EIM_A18__GPIO2_20 0x1f4 used by LED */ +- MX53_PAD_EIM_A19__GPIO2_19 0x1f4 +- MX53_PAD_EIM_A20__GPIO2_18 0x1f4 +- MX53_PAD_EIM_A21__GPIO2_17 0x1f4 +- MX53_PAD_EIM_A22__GPIO2_16 0x1f4 +- MX53_PAD_EIM_A23__GPIO6_6 0x1f4 +- MX53_PAD_EIM_A24__GPIO5_4 0x1f4 +- MX53_PAD_CSI0_DAT8__GPIO5_26 0x1f4 +- MX53_PAD_CSI0_DAT9__GPIO5_27 0x1f4 +- MX53_PAD_CSI0_DAT10__GPIO5_28 0x1f4 +- MX53_PAD_CSI0_DAT11__GPIO5_29 0x1f4 +- /* MX53_PAD_EIM_D22__GPIO3_22 0x1f4 maybe used by EETI touchpanel driver */ +- /* MX53_PAD_EIM_D23__GPIO3_23 0x1f4 maybe used by EETI touchpanel driver */ +- MX53_PAD_GPIO_13__GPIO4_3 0x1f4 +- MX53_PAD_EIM_CS0__GPIO2_23 0x1f4 +- MX53_PAD_EIM_CS1__GPIO2_24 0x1f4 +- MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1f4 +- MX53_PAD_EIM_WAIT__GPIO5_0 0x1f4 +- MX53_PAD_EIM_EB0__GPIO2_28 0x1f4 +- MX53_PAD_EIM_EB1__GPIO2_29 0x1f4 +- MX53_PAD_EIM_OE__GPIO2_25 0x1f4 +- MX53_PAD_EIM_LBA__GPIO2_27 0x1f4 +- MX53_PAD_EIM_RW__GPIO2_26 0x1f4 +- MX53_PAD_EIM_DA8__GPIO3_8 0x1f4 +- MX53_PAD_EIM_DA9__GPIO3_9 0x1f4 +- MX53_PAD_EIM_DA10__GPIO3_10 0x1f4 +- MX53_PAD_EIM_DA11__GPIO3_11 0x1f4 +- MX53_PAD_EIM_DA12__GPIO3_12 0x1f4 +- MX53_PAD_EIM_DA13__GPIO3_13 0x1f4 +- MX53_PAD_EIM_DA14__GPIO3_14 0x1f4 +- MX53_PAD_EIM_DA15__GPIO3_15 0x1f4 +- >; +- }; +- +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 +- MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 +- >; +- }; +- +- pinctrl_can2: can2grp { +- fsl,pins = < +- MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 +- MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 +- >; +- }; +- +- pinctrl_can_xcvr: can-xcvrgrp { +- fsl,pins = ; /* Flexcan XCVR enable */ +- }; +- +- pinctrl_ds1339: ds1339grp { +- fsl,pins = ; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000 +- MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000 +- MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 +- MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 +- MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 +- MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000 +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 +- MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 +- MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 +- MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 +- MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 +- MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 +- MX53_PAD_EIM_D24__GPIO3_24 0x1f0 +- >; +- }; +- +- pinctrl_esdhc2: esdhc2grp { +- fsl,pins = < +- MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 +- MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 +- MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 +- MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 +- MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 +- MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 +- MX53_PAD_EIM_D25__GPIO3_25 0x1f0 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 +- MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 +- MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 +- MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 +- MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 +- MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 +- MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 +- MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 +- MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 +- MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 +- >; +- }; +- +- pinctrl_gpio_key: gpio-keygrp { +- fsl,pins = ; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 +- MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 +- >; +- }; +- +- pinctrl_i2c1_gpio: i2c1-gpiogrp { +- fsl,pins = < +- MX53_PAD_EIM_D21__GPIO3_21 0x400001e6 +- MX53_PAD_EIM_D28__GPIO3_28 0x400001e6 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX53_PAD_GPIO_3__I2C3_SCL 0x400001e4 +- MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 +- >; +- }; +- +- pinctrl_i2c3_gpio: i2c3-gpiogrp { +- fsl,pins = < +- MX53_PAD_GPIO_3__GPIO1_3 0x400001e6 +- MX53_PAD_GPIO_6__GPIO1_6 0x400001e6 +- >; +- }; +- +- pinctrl_nand: nandgrp { +- fsl,pins = < +- MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 +- MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 +- MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 +- MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 +- MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 +- MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 +- MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 +- MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4 +- MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4 +- MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4 +- MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4 +- MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4 +- MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4 +- MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4 +- MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 +- >; +- }; +- +- pinctrl_ssi1: ssi1grp { +- fsl,pins = < +- MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 +- MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 +- MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 +- MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 +- >; +- }; +- +- pinctrl_ssi2: ssi2grp { +- fsl,pins = < +- MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000 +- MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000 +- MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000 +- MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000 +- MX53_PAD_EIM_D27__GPIO3_27 0x1f0 +- >; +- }; +- +- pinctrl_stk5led: stk5ledgrp { +- fsl,pins = ; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 +- MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 +- MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5 +- MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 +- MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 +- MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5 +- MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 +- MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 +- MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 +- MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 +- >; +- }; +- +- pinctrl_usbh1: usbh1grp { +- fsl,pins = < +- MX53_PAD_EIM_D30__GPIO3_30 0x100 /* OC */ +- >; +- }; +- +- pinctrl_usbh1_vbus: usbh1-vbusgrp { +- fsl,pins = < +- MX53_PAD_EIM_D31__GPIO3_31 0xe0 /* VBUS ENABLE */ +- >; +- }; +- +- pinctrl_usbotg_vbus: usbotg-vbusgrp { +- fsl,pins = < +- MX53_PAD_GPIO_7__GPIO1_7 0xe0 /* VBUS ENABLE */ +- MX53_PAD_GPIO_8__GPIO1_8 0x100 /* OC */ +- >; +- }; +- }; +-}; +- +-&ipu { +- status = "okay"; +-}; +- +-&nfc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nand>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-on-flash-bbt; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +-}; +- +-&sdma { +- fsl,sdma-ram-script-name = "sdma-imx53.bin"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&ssi2 { +- status = "disabled"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbh1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1>; +- phy_type = "utmi"; +- disable-over-current; +- vbus-supply = <®_usbh1_vbus>; +- status = "okay"; +-}; +- +-&usbotg { +- phy_type = "utmi"; +- dr_mode = "peripheral"; +- disable-over-current; +- vbus-supply = <®_usbotg_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-usbarmory.dts b/scripts/dtc/include-prefixes/arm/imx53-usbarmory.dts +deleted file mode 100644 +index f34993a490ee..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-usbarmory.dts ++++ /dev/null +@@ -1,225 +0,0 @@ +-/* +- * USB armory MkI device tree file +- * https://inversepath.com/usbarmory +- * +- * Copyright (C) 2015, Inverse Path +- * Andrej Rosano +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx53.dtsi" +- +-/ { +- model = "Inverse Path USB armory"; +- compatible = "inversepath,imx53-usbarmory", "fsl,imx53"; +-}; +- +-/ { +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@70000000 { +- device_type = "memory"; +- reg = <0x70000000 0x20000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led>; +- +- user { +- label = "LED"; +- gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-/* +- * Not every i.MX53 P/N supports clock > 800MHz. +- * As USB armory does not mount a specific P/N set a safe clock upper limit. +- */ +-&cpu0 { +- operating-points = < +- /* kHz */ +- 166666 850000 +- 400000 900000 +- 800000 1050000 +- >; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 +- MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 +- MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 +- MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 +- MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 +- MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 +- >; +- }; +- +- pinctrl_i2c1_pmic: i2c1grp { +- fsl,pins = < +- MX53_PAD_EIM_D21__I2C1_SCL 0x80 +- MX53_PAD_EIM_D28__I2C1_SDA 0x80 +- >; +- }; +- +- pinctrl_led: ledgrp { +- fsl,pins = < +- MX53_PAD_DISP0_DAT6__GPIO4_27 0x1e4 +- >; +- }; +- +- /* +- * UART mode pin header configuration +- * 3 - GPIO5[26], pull-down 100K +- * 4 - GPIO5[27], pull-down 100K +- * 5 - TX, pull-up 100K +- * 6 - RX, pull-up 100K +- * 7 - GPIO5[30], pull-down 100K +- */ +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX53_PAD_CSI0_DAT8__GPIO5_26 0xc0 +- MX53_PAD_CSI0_DAT9__GPIO5_27 0xc0 +- MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 +- MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 +- MX53_PAD_CSI0_DAT12__GPIO5_30 0xc0 +- >; +- }; +-}; +- +-&i2c1 { +- pinctrl-0 = <&pinctrl_i2c1_pmic>; +- status = "okay"; +- +- ltc3589: pmic@34 { +- compatible = "lltc,ltc3589-2"; +- reg = <0x34>; +- +- regulators { +- sw1_reg: sw1 { +- regulator-min-microvolt = <591930>; +- regulator-max-microvolt = <1224671>; +- lltc,fb-voltage-divider = <100000 158000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <704123>; +- regulator-max-microvolt = <1456803>; +- lltc,fb-voltage-divider = <180000 191000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3_reg: sw3 { +- regulator-min-microvolt = <1341250>; +- regulator-max-microvolt = <2775000>; +- lltc,fb-voltage-divider = <270000 100000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- bb_out_reg: bb-out { +- regulator-min-microvolt = <3387341>; +- regulator-max-microvolt = <3387341>; +- lltc,fb-voltage-divider = <511000 158000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1_reg: ldo1 { +- regulator-min-microvolt = <1306329>; +- regulator-max-microvolt = <1306329>; +- lltc,fb-voltage-divider = <100000 158000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo2_reg: ldo2 { +- regulator-min-microvolt = <704123>; +- regulator-max-microvolt = <1456806>; +- lltc,fb-voltage-divider = <180000 191000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo3_reg: ldo3 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-boot-on; +- }; +- +- ldo4_reg: ldo4 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3200000>; +- }; +- }; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usbotg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-voipac-bsb.dts b/scripts/dtc/include-prefixes/arm/imx53-voipac-bsb.dts +deleted file mode 100644 +index ae53d178a683..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-voipac-bsb.dts ++++ /dev/null +@@ -1,153 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Rostislav Lisovy , PiKRON s.r.o. +- */ +- +-/dts-v1/; +-#include "imx53-voipac-dmm-668.dtsi" +- +-/ { +- sound { +- compatible = "fsl,imx53-voipac-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "imx53-voipac-sgtl5000"; +- ssi-controller = <&ssi2>; +- audio-codec = <&sgtl5000>; +- audio-routing = +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <2>; +- mux-ext-port = <5>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pin_gpio>; +- +- led1 { +- label = "led-red"; +- gpios = <&gpio3 29 0>; +- default-state = "off"; +- }; +- +- led2 { +- label = "led-orange"; +- gpios = <&gpio2 31 0>; +- default-state = "off"; +- }; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx53-voipac { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- /* SD2_CD */ +- MX53_PAD_EIM_D25__GPIO3_25 0x80000000 +- /* SD2_WP */ +- MX53_PAD_EIM_A19__GPIO2_19 0x80000000 +- >; +- }; +- +- led_pin_gpio: led_gpio { +- fsl,pins = < +- MX53_PAD_EIM_D29__GPIO3_29 0x80000000 +- MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 +- >; +- }; +- +- /* Keyboard controller */ +- pinctrl_kpp_1: kppgrp-1 { +- fsl,pins = < +- MX53_PAD_GPIO_9__KPP_COL_6 0xe8 +- MX53_PAD_GPIO_4__KPP_COL_7 0xe8 +- MX53_PAD_KEY_COL2__KPP_COL_2 0xe8 +- MX53_PAD_KEY_COL3__KPP_COL_3 0xe8 +- MX53_PAD_KEY_COL4__KPP_COL_4 0xe8 +- MX53_PAD_GPIO_2__KPP_ROW_6 0xe0 +- MX53_PAD_GPIO_5__KPP_ROW_7 0xe0 +- MX53_PAD_KEY_ROW2__KPP_ROW_2 0xe0 +- MX53_PAD_KEY_ROW3__KPP_ROW_3 0xe0 +- MX53_PAD_KEY_ROW4__KPP_ROW_4 0xe0 +- >; +- }; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 +- MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 +- MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 +- MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 +- >; +- }; +- +- pinctrl_esdhc2: esdhc2grp { +- fsl,pins = < +- MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 +- MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 +- MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 +- MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 +- MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 +- MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000 +- MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 +- >; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; /* SSI1 */ +- status = "okay"; +-}; +- +-&esdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc2>; +- cd-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; +- clocks = <&clks 150>; +- }; +-}; +- +-&kpp { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_kpp_1>; +- linux,keymap = < +- 0x0203003b /* KEY_F1 */ +- 0x0603003c /* KEY_F2 */ +- 0x0207003d /* KEY_F3 */ +- 0x0607003e /* KEY_F4 */ +- >; +- keypad,num-rows = <8>; +- keypad,num-columns = <1>; +- status = "okay"; +-}; +- +-&ssi2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53-voipac-dmm-668.dtsi b/scripts/dtc/include-prefixes/arm/imx53-voipac-dmm-668.dtsi +deleted file mode 100644 +index 24859d0c09c1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53-voipac-dmm-668.dtsi ++++ /dev/null +@@ -1,267 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Rostislav Lisovy , PiKRON s.r.o. +- */ +- +-#include "imx53.dtsi" +- +-/ { +- model = "Voipac i.MX53 X53-DMM-668"; +- compatible = "voipac,imx53-dmm-668", "fsl,imx53"; +- +- memory@70000000 { +- device_type = "memory"; +- reg = <0x70000000 0x20000000>, +- <0xb0000000 0x20000000>; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_3p3v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_vbus: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "usb_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 31 0>; /* PEN */ +- enable-active-high; +- }; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx53-voipac { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- /* Make DA9053 regulator functional */ +- MX53_PAD_GPIO_16__GPIO7_11 0x80000000 +- /* FEC Power enable */ +- MX53_PAD_GPIO_11__GPIO4_1 0x80000000 +- /* FEC RST */ +- MX53_PAD_GPIO_12__GPIO4_2 0x80000000 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 +- MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 +- MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 +- MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 +- MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 +- MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 +- MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 +- MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 +- MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 +- MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 +- MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 +- MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 +- MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 +- MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 +- >; +- }; +- +- pinctrl_nand: nandgrp { +- fsl,pins = < +- MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 +- MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 +- MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 +- MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 +- MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 +- MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 +- MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 +- MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 +- MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 +- MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 +- MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 +- MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 +- MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 +- MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 +- MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 +- >; +- }; +- }; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>, +- <&gpio2 16 GPIO_ACTIVE_LOW>, <&gpio2 17 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-mode = "rmii"; +- phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic: dialog@48 { +- compatible = "dlg,da9053-aa", "dlg,da9052"; +- reg = <0x48>; +- interrupt-parent = <&gpio7>; +- interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* low-level active IRQ at GPIO7_11 */ +- +- regulators { +- buck1_reg: buck1 { +- regulator-name = "BUCKCORE"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- }; +- +- buck2_reg: buck2 { +- regulator-name = "BUCKPRO"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- }; +- +- buck3_reg: buck3 { +- regulator-name = "BUCKMEM"; +- regulator-min-microvolt = <1420000>; +- regulator-max-microvolt = <1580000>; +- regulator-always-on; +- }; +- +- buck4_reg: buck4 { +- regulator-name = "BUCKPERI"; +- regulator-min-microvolt = <2370000>; +- regulator-max-microvolt = <2630000>; +- regulator-always-on; +- }; +- +- ldo1_reg: ldo1 { +- regulator-name = "ldo1_1v3"; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1350000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo2_reg: ldo2 { +- regulator-name = "ldo2_1v3"; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- }; +- +- ldo3_reg: ldo3 { +- regulator-name = "ldo3_3v3"; +- regulator-min-microvolt = <3250000>; +- regulator-max-microvolt = <3350000>; +- regulator-always-on; +- }; +- +- ldo4_reg: ldo4 { +- regulator-name = "ldo4_2v775"; +- regulator-min-microvolt = <2770000>; +- regulator-max-microvolt = <2780000>; +- regulator-always-on; +- }; +- +- ldo5_reg: ldo5 { +- regulator-name = "ldo5_3v3"; +- regulator-min-microvolt = <3250000>; +- regulator-max-microvolt = <3350000>; +- regulator-always-on; +- }; +- +- ldo6_reg: ldo6 { +- regulator-name = "ldo6_1v3"; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- }; +- +- ldo7_reg: ldo7 { +- regulator-name = "ldo7_2v75"; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- ldo8_reg: ldo8 { +- regulator-name = "ldo8_1v8"; +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <1850000>; +- regulator-always-on; +- }; +- +- ldo9_reg: ldo9 { +- regulator-name = "ldo9_1v5"; +- regulator-min-microvolt = <1450000>; +- regulator-max-microvolt = <1550000>; +- regulator-always-on; +- }; +- +- ldo10_reg: ldo10 { +- regulator-name = "ldo10_1v3"; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&nfc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nand>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_vbus>; +- phy_type = "utmi"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx53.dtsi b/scripts/dtc/include-prefixes/arm/imx53.dtsi +deleted file mode 100644 +index 2cf3909cca2f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx53.dtsi ++++ /dev/null +@@ -1,856 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2011 Freescale Semiconductor, Inc. +-// Copyright 2011 Linaro Ltd. +- +-#include "imx53-pinfunc.h" +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * The decompressor and also some bootloaders rely on a +- * pre-existing /chosen node to be available to insert the +- * command line and merge other ATAGS info. +- */ +- chosen {}; +- +- aliases { +- ethernet0 = &fec; +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- gpio3 = &gpio4; +- gpio4 = &gpio5; +- gpio5 = &gpio6; +- gpio6 = &gpio7; +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- ipu0 = &ipu; +- mmc0 = &esdhc1; +- mmc1 = &esdhc2; +- mmc2 = &esdhc3; +- mmc3 = &esdhc4; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- serial4 = &uart5; +- spi0 = &ecspi1; +- spi1 = &ecspi2; +- spi2 = &cspi; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a8"; +- reg = <0x0>; +- clocks = <&clks IMX5_CLK_ARM>; +- clock-latency = <61036>; +- voltage-tolerance = <5>; +- operating-points = < +- /* kHz */ +- 166666 850000 +- 400000 900000 +- 800000 1050000 +- 1000000 1200000 +- 1200000 1300000 +- >; +- }; +- }; +- +- display-subsystem { +- compatible = "fsl,imx-display-subsystem"; +- ports = <&ipu_di0>, <&ipu_di1>; +- }; +- +- capture_subsystem { +- compatible = "fsl,imx-capture-subsystem"; +- ports = <&ipu_csi0>, <&ipu_csi1>; +- }; +- +- tzic: tz-interrupt-controller@fffc000 { +- compatible = "fsl,imx53-tzic", "fsl,tzic"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x0fffc000 0x4000>; +- }; +- +- clocks { +- ckil { +- compatible = "fsl,imx-ckil", "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- ckih1 { +- compatible = "fsl,imx-ckih1", "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <22579200>; +- }; +- +- ckih2 { +- compatible = "fsl,imx-ckih2", "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- osc { +- compatible = "fsl,imx-osc", "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- }; +- }; +- +- pmu: pmu { +- compatible = "arm,cortex-a8-pmu"; +- interrupt-parent = <&tzic>; +- interrupts = <77>; +- }; +- +- usbphy0: usbphy-0 { +- compatible = "usb-nop-xceiv"; +- clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; +- clock-names = "main_clk"; +- #phy-cells = <0>; +- status = "okay"; +- }; +- +- usbphy1: usbphy-1 { +- compatible = "usb-nop-xceiv"; +- clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; +- clock-names = "main_clk"; +- #phy-cells = <0>; +- status = "okay"; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&tzic>; +- ranges; +- +- sata: sata@10000000 { +- compatible = "fsl,imx53-ahci"; +- reg = <0x10000000 0x1000>; +- interrupts = <28>; +- clocks = <&clks IMX5_CLK_SATA_GATE>, +- <&clks IMX5_CLK_SATA_REF>, +- <&clks IMX5_CLK_AHB>; +- clock-names = "sata", "sata_ref", "ahb"; +- status = "disabled"; +- }; +- +- ipu: ipu@18000000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx53-ipu"; +- reg = <0x18000000 0x08000000>; +- interrupts = <11 10>; +- clocks = <&clks IMX5_CLK_IPU_GATE>, +- <&clks IMX5_CLK_IPU_DI0_GATE>, +- <&clks IMX5_CLK_IPU_DI1_GATE>; +- clock-names = "bus", "di0", "di1"; +- resets = <&src 2>; +- +- ipu_csi0: port@0 { +- reg = <0>; +- +- ipu_csi0_from_parallel_sensor: endpoint { +- }; +- }; +- +- ipu_csi1: port@1 { +- reg = <1>; +- +- ipu_csi1_from_parallel_sensor: endpoint { +- }; +- }; +- +- ipu_di0: port@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- ipu_di0_disp0: endpoint@0 { +- reg = <0>; +- }; +- +- ipu_di0_lvds0: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&lvds0_in>; +- }; +- }; +- +- ipu_di1: port@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- ipu_di1_disp1: endpoint@0 { +- reg = <0>; +- }; +- +- ipu_di1_lvds1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&lvds1_in>; +- }; +- +- ipu_di1_tve: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&tve_in>; +- }; +- }; +- }; +- +- gpu: gpu@30000000 { +- compatible = "amd,imageon-200.0", "amd,imageon"; +- reg = <0x30000000 0x20000>; +- reg-names = "kgsl_3d0_reg_memory"; +- interrupts = <12>; +- interrupt-names = "kgsl_3d0_irq"; +- clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; +- clock-names = "core_clk", "mem_iface_clk"; +- }; +- +- bus@50000000 { /* AIPS1 */ +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x50000000 0x10000000>; +- ranges; +- +- spba@50000000 { +- compatible = "fsl,spba-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x50000000 0x40000>; +- ranges; +- +- esdhc1: mmc@50004000 { +- compatible = "fsl,imx53-esdhc"; +- reg = <0x50004000 0x4000>; +- interrupts = <1>; +- clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, +- <&clks IMX5_CLK_DUMMY>, +- <&clks IMX5_CLK_ESDHC1_PER_GATE>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- esdhc2: mmc@50008000 { +- compatible = "fsl,imx53-esdhc"; +- reg = <0x50008000 0x4000>; +- interrupts = <2>; +- clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, +- <&clks IMX5_CLK_DUMMY>, +- <&clks IMX5_CLK_ESDHC2_PER_GATE>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- uart3: serial@5000c000 { +- compatible = "fsl,imx53-uart", "fsl,imx21-uart"; +- reg = <0x5000c000 0x4000>; +- interrupts = <33>; +- clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, +- <&clks IMX5_CLK_UART3_PER_GATE>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 42 4 0>, <&sdma 43 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ecspi1: spi@50010000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; +- reg = <0x50010000 0x4000>; +- interrupts = <36>; +- clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, +- <&clks IMX5_CLK_ECSPI1_PER_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- ssi2: ssi@50014000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx53-ssi", +- "fsl,imx51-ssi", +- "fsl,imx21-ssi"; +- reg = <0x50014000 0x4000>; +- interrupts = <30>; +- clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, +- <&clks IMX5_CLK_SSI2_ROOT_GATE>; +- clock-names = "ipg", "baud"; +- dmas = <&sdma 24 1 0>, +- <&sdma 25 1 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- esdhc3: mmc@50020000 { +- compatible = "fsl,imx53-esdhc"; +- reg = <0x50020000 0x4000>; +- interrupts = <3>; +- clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, +- <&clks IMX5_CLK_DUMMY>, +- <&clks IMX5_CLK_ESDHC3_PER_GATE>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- esdhc4: mmc@50024000 { +- compatible = "fsl,imx53-esdhc"; +- reg = <0x50024000 0x4000>; +- interrupts = <4>; +- clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, +- <&clks IMX5_CLK_DUMMY>, +- <&clks IMX5_CLK_ESDHC4_PER_GATE>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- }; +- +- aipstz1: bridge@53f00000 { +- compatible = "fsl,imx53-aipstz"; +- reg = <0x53f00000 0x60>; +- }; +- +- usbotg: usb@53f80000 { +- compatible = "fsl,imx53-usb", "fsl,imx27-usb"; +- reg = <0x53f80000 0x0200>; +- interrupts = <18>; +- clocks = <&clks IMX5_CLK_USBOH3_GATE>; +- fsl,usbmisc = <&usbmisc 0>; +- fsl,usbphy = <&usbphy0>; +- status = "disabled"; +- }; +- +- usbh1: usb@53f80200 { +- compatible = "fsl,imx53-usb", "fsl,imx27-usb"; +- reg = <0x53f80200 0x0200>; +- interrupts = <14>; +- clocks = <&clks IMX5_CLK_USBOH3_GATE>; +- fsl,usbmisc = <&usbmisc 1>; +- fsl,usbphy = <&usbphy1>; +- dr_mode = "host"; +- status = "disabled"; +- }; +- +- usbh2: usb@53f80400 { +- compatible = "fsl,imx53-usb", "fsl,imx27-usb"; +- reg = <0x53f80400 0x0200>; +- interrupts = <16>; +- clocks = <&clks IMX5_CLK_USBOH3_GATE>; +- fsl,usbmisc = <&usbmisc 2>; +- dr_mode = "host"; +- status = "disabled"; +- }; +- +- usbh3: usb@53f80600 { +- compatible = "fsl,imx53-usb", "fsl,imx27-usb"; +- reg = <0x53f80600 0x0200>; +- interrupts = <17>; +- clocks = <&clks IMX5_CLK_USBOH3_GATE>; +- fsl,usbmisc = <&usbmisc 3>; +- dr_mode = "host"; +- status = "disabled"; +- }; +- +- usbmisc: usbmisc@53f80800 { +- #index-cells = <1>; +- compatible = "fsl,imx53-usbmisc"; +- reg = <0x53f80800 0x200>; +- clocks = <&clks IMX5_CLK_USBOH3_GATE>; +- }; +- +- gpio1: gpio@53f84000 { +- compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; +- reg = <0x53f84000 0x4000>; +- interrupts = <50 51>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@53f88000 { +- compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; +- reg = <0x53f88000 0x4000>; +- interrupts = <52 53>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio@53f8c000 { +- compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; +- reg = <0x53f8c000 0x4000>; +- interrupts = <54 55>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio4: gpio@53f90000 { +- compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; +- reg = <0x53f90000 0x4000>; +- interrupts = <56 57>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- kpp: kpp@53f94000 { +- compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; +- reg = <0x53f94000 0x4000>; +- interrupts = <60>; +- clocks = <&clks IMX5_CLK_DUMMY>; +- status = "disabled"; +- }; +- +- wdog1: watchdog@53f98000 { +- compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; +- reg = <0x53f98000 0x4000>; +- interrupts = <58>; +- clocks = <&clks IMX5_CLK_DUMMY>; +- }; +- +- wdog2: watchdog@53f9c000 { +- compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; +- reg = <0x53f9c000 0x4000>; +- interrupts = <59>; +- clocks = <&clks IMX5_CLK_DUMMY>; +- status = "disabled"; +- }; +- +- gpt: timer@53fa0000 { +- compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; +- reg = <0x53fa0000 0x4000>; +- interrupts = <39>; +- clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, +- <&clks IMX5_CLK_GPT_HF_GATE>; +- clock-names = "ipg", "per"; +- }; +- +- srtc: rtc@53fa4000 { +- compatible = "fsl,imx53-rtc"; +- reg = <0x53fa4000 0x4000>; +- interrupts = <24>; +- clocks = <&clks IMX5_CLK_SRTC_GATE>; +- }; +- +- iomuxc: iomuxc@53fa8000 { +- compatible = "fsl,imx53-iomuxc"; +- reg = <0x53fa8000 0x4000>; +- }; +- +- gpr: iomuxc-gpr@53fa8000 { +- compatible = "fsl,imx53-iomuxc-gpr", "syscon"; +- reg = <0x53fa8000 0xc>; +- }; +- +- ldb: ldb@53fa8008 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx53-ldb"; +- reg = <0x53fa8008 0x4>; +- gpr = <&gpr>; +- clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, +- <&clks IMX5_CLK_LDB_DI1_SEL>, +- <&clks IMX5_CLK_IPU_DI0_SEL>, +- <&clks IMX5_CLK_IPU_DI1_SEL>, +- <&clks IMX5_CLK_LDB_DI0_GATE>, +- <&clks IMX5_CLK_LDB_DI1_GATE>; +- clock-names = "di0_pll", "di1_pll", +- "di0_sel", "di1_sel", +- "di0", "di1"; +- status = "disabled"; +- +- lvds-channel@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- status = "disabled"; +- +- port@0 { +- reg = <0>; +- +- lvds0_in: endpoint { +- remote-endpoint = <&ipu_di0_lvds0>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- }; +- }; +- +- lvds-channel@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- status = "disabled"; +- +- port@1 { +- reg = <1>; +- +- lvds1_in: endpoint { +- remote-endpoint = <&ipu_di1_lvds1>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- }; +- }; +- }; +- +- pwm1: pwm@53fb4000 { +- #pwm-cells = <3>; +- compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; +- reg = <0x53fb4000 0x4000>; +- clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, +- <&clks IMX5_CLK_PWM1_HF_GATE>; +- clock-names = "ipg", "per"; +- interrupts = <61>; +- }; +- +- pwm2: pwm@53fb8000 { +- #pwm-cells = <3>; +- compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; +- reg = <0x53fb8000 0x4000>; +- clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, +- <&clks IMX5_CLK_PWM2_HF_GATE>; +- clock-names = "ipg", "per"; +- interrupts = <94>; +- }; +- +- uart1: serial@53fbc000 { +- compatible = "fsl,imx53-uart", "fsl,imx21-uart"; +- reg = <0x53fbc000 0x4000>; +- interrupts = <31>; +- clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, +- <&clks IMX5_CLK_UART1_PER_GATE>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 18 4 0>, <&sdma 19 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart2: serial@53fc0000 { +- compatible = "fsl,imx53-uart", "fsl,imx21-uart"; +- reg = <0x53fc0000 0x4000>; +- interrupts = <32>; +- clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, +- <&clks IMX5_CLK_UART2_PER_GATE>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- can1: can@53fc8000 { +- compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; +- reg = <0x53fc8000 0x4000>; +- interrupts = <82>; +- clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, +- <&clks IMX5_CLK_CAN1_SERIAL_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- can2: can@53fcc000 { +- compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; +- reg = <0x53fcc000 0x4000>; +- interrupts = <83>; +- clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, +- <&clks IMX5_CLK_CAN2_SERIAL_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- src: reset-controller@53fd0000 { +- compatible = "fsl,imx53-src", "fsl,imx51-src"; +- reg = <0x53fd0000 0x4000>; +- interrupts = <75>; +- #reset-cells = <1>; +- }; +- +- clks: ccm@53fd4000{ +- compatible = "fsl,imx53-ccm"; +- reg = <0x53fd4000 0x4000>; +- interrupts = <0 71 0x04 0 72 0x04>; +- #clock-cells = <1>; +- }; +- +- gpio5: gpio@53fdc000 { +- compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; +- reg = <0x53fdc000 0x4000>; +- interrupts = <103 104>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio6: gpio@53fe0000 { +- compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; +- reg = <0x53fe0000 0x4000>; +- interrupts = <105 106>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio7: gpio@53fe4000 { +- compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; +- reg = <0x53fe4000 0x4000>; +- interrupts = <107 108>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- i2c3: i2c@53fec000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; +- reg = <0x53fec000 0x4000>; +- interrupts = <64>; +- clocks = <&clks IMX5_CLK_I2C3_GATE>; +- status = "disabled"; +- }; +- +- uart4: serial@53ff0000 { +- compatible = "fsl,imx53-uart", "fsl,imx21-uart"; +- reg = <0x53ff0000 0x4000>; +- interrupts = <13>; +- clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, +- <&clks IMX5_CLK_UART4_PER_GATE>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 2 4 0>, <&sdma 3 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- }; +- +- bus@60000000 { /* AIPS2 */ +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x60000000 0x10000000>; +- ranges; +- +- aipstz2: bridge@63f00000 { +- compatible = "fsl,imx53-aipstz"; +- reg = <0x63f00000 0x60>; +- }; +- +- iim: efuse@63f98000 { +- compatible = "fsl,imx53-iim", "fsl,imx27-iim", "syscon"; +- reg = <0x63f98000 0x4000>; +- interrupts = <69>; +- clocks = <&clks IMX5_CLK_IIM_GATE>; +- }; +- +- uart5: serial@63f90000 { +- compatible = "fsl,imx53-uart", "fsl,imx21-uart"; +- reg = <0x63f90000 0x4000>; +- interrupts = <86>; +- clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, +- <&clks IMX5_CLK_UART5_PER_GATE>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 16 4 0>, <&sdma 17 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- tigerp: tigerp@63fa0000 { +- compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp"; +- reg = <0x63fa0000 0x28>; +- }; +- +- owire: owire@63fa4000 { +- compatible = "fsl,imx53-owire", "fsl,imx21-owire"; +- reg = <0x63fa4000 0x4000>; +- clocks = <&clks IMX5_CLK_OWIRE_GATE>; +- status = "disabled"; +- }; +- +- ecspi2: spi@63fac000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; +- reg = <0x63fac000 0x4000>; +- interrupts = <37>; +- clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, +- <&clks IMX5_CLK_ECSPI2_PER_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- sdma: sdma@63fb0000 { +- compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; +- reg = <0x63fb0000 0x4000>; +- interrupts = <6>; +- clocks = <&clks IMX5_CLK_SDMA_GATE>, +- <&clks IMX5_CLK_AHB>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; +- }; +- +- cspi: spi@63fc0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; +- reg = <0x63fc0000 0x4000>; +- interrupts = <38>; +- clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, +- <&clks IMX5_CLK_CSPI_IPG_GATE>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- i2c2: i2c@63fc4000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; +- reg = <0x63fc4000 0x4000>; +- interrupts = <63>; +- clocks = <&clks IMX5_CLK_I2C2_GATE>; +- status = "disabled"; +- }; +- +- i2c1: i2c@63fc8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; +- reg = <0x63fc8000 0x4000>; +- interrupts = <62>; +- clocks = <&clks IMX5_CLK_I2C1_GATE>; +- status = "disabled"; +- }; +- +- ssi1: ssi@63fcc000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", +- "fsl,imx21-ssi"; +- reg = <0x63fcc000 0x4000>; +- interrupts = <29>; +- clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, +- <&clks IMX5_CLK_SSI1_ROOT_GATE>; +- clock-names = "ipg", "baud"; +- dmas = <&sdma 28 0 0>, +- <&sdma 29 0 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- audmux: audmux@63fd0000 { +- compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; +- reg = <0x63fd0000 0x4000>; +- status = "disabled"; +- }; +- +- nfc: nand@63fdb000 { +- compatible = "fsl,imx53-nand"; +- reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; +- interrupts = <8>; +- clocks = <&clks IMX5_CLK_NFC_GATE>; +- status = "disabled"; +- }; +- +- ssi3: ssi@63fe8000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", +- "fsl,imx21-ssi"; +- reg = <0x63fe8000 0x4000>; +- interrupts = <96>; +- clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, +- <&clks IMX5_CLK_SSI3_ROOT_GATE>; +- clock-names = "ipg", "baud"; +- dmas = <&sdma 46 0 0>, +- <&sdma 47 0 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- fec: ethernet@63fec000 { +- compatible = "fsl,imx53-fec", "fsl,imx25-fec"; +- reg = <0x63fec000 0x4000>; +- interrupts = <87>; +- clocks = <&clks IMX5_CLK_FEC_GATE>, +- <&clks IMX5_CLK_FEC_GATE>, +- <&clks IMX5_CLK_FEC_GATE>; +- clock-names = "ipg", "ahb", "ptp"; +- status = "disabled"; +- }; +- +- tve: tve@63ff0000 { +- compatible = "fsl,imx53-tve"; +- reg = <0x63ff0000 0x1000>; +- interrupts = <92>; +- clocks = <&clks IMX5_CLK_TVE_GATE>, +- <&clks IMX5_CLK_IPU_DI1_SEL>; +- clock-names = "tve", "di_sel"; +- status = "disabled"; +- +- port { +- tve_in: endpoint { +- remote-endpoint = <&ipu_di1_tve>; +- }; +- }; +- }; +- +- vpu: vpu@63ff4000 { +- compatible = "fsl,imx53-vpu", "cnm,coda7541"; +- reg = <0x63ff4000 0x1000>; +- interrupts = <9>; +- clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, +- <&clks IMX5_CLK_VPU_GATE>; +- clock-names = "per", "ahb"; +- resets = <&src 1>; +- iram = <&ocram>; +- }; +- +- sahara: crypto@63ff8000 { +- compatible = "fsl,imx53-sahara"; +- reg = <0x63ff8000 0x4000>; +- interrupts = <19 20>; +- clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, +- <&clks IMX5_CLK_SAHARA_IPG_GATE>; +- clock-names = "ipg", "ahb"; +- }; +- }; +- +- ocram: sram@f8000000 { +- compatible = "mmio-sram"; +- reg = <0xf8000000 0x20000>; +- clocks = <&clks IMX5_CLK_OCRAM>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6-logicpd-baseboard.dtsi b/scripts/dtc/include-prefixes/arm/imx6-logicpd-baseboard.dtsi +deleted file mode 100644 +index d9de9b4f0c52..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6-logicpd-baseboard.dtsi ++++ /dev/null +@@ -1,561 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright (C) 2019 Logic PD, Inc. +- +-/ { +- keyboard { +- compatible = "gpio-keys"; +- +- btn0 { +- gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>; +- label = "btn0"; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- +- btn1 { +- gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>; +- label = "btn1"; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- +- btn2 { +- gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>; +- label = "btn2"; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- +- btn3 { +- gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>; +- label = "btn3"; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- gen-led0 { +- label = "led0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led0>; +- gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "cpu0"; +- }; +- +- gen-led1 { +- label = "led1"; +- gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>; +- }; +- +- gen-led2 { +- label = "led2"; +- gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- gen-led3 { +- label = "led3"; +- gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- }; +- +- reg_usb_otg_vbus: regulator-otg-vbus { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usb_otg>; +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_h1_vbus: regulator-usb-h1-vbus { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>; +- compatible = "regulator-fixed"; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <70000>; +- enable-active-high; +- }; +- +- reg_3v3: regulator-3v3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_3v3>; +- compatible = "regulator-fixed"; +- regulator-name = "reg_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <70000>; +- enable-active-high; +- regulator-always-on; +- }; +- +- reg_enet: regulator-ethernet { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_enet>; +- compatible = "regulator-fixed"; +- regulator-name = "ethernet-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <70000>; +- enable-active-high; +- vin-supply = <&sw4_reg>; +- }; +- +- reg_audio: regulator-audio { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_audio>; +- compatible = "regulator-fixed"; +- regulator-name = "3v3_aud"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_3v3>; +- }; +- +- reg_hdmi: regulator-hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_hdmi>; +- compatible = "regulator-fixed"; +- regulator-name = "hdmi-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_3v3>; +- }; +- +- reg_uart3: regulator-uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_uart3>; +- compatible = "regulator-fixed"; +- regulator-name = "uart3-supply"; +- gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- vin-supply = <®_3v3>; +- }; +- +- reg_1v8: regulator-1v8 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_1v8>; +- compatible = "regulator-fixed"; +- regulator-name = "1v8-supply"; +- gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- vin-supply = <®_3v3>; +- }; +- +- reg_pcie: regulator-pcie { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_pcie>; +- regulator-name = "mpcie_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_mipi: regulator-mipi { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_mipi>; +- regulator-name = "mipi_pwr_en"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sound { +- compatible = "fsl,imx-audio-wm8962"; +- model = "wm8962-audio"; +- ssi-controller = <&ssi2>; +- audio-codec = <&wm8962>; +- audio-routing = +- "Headphone Jack", "HPOUTL", +- "Headphone Jack", "HPOUTR", +- "Ext Spk", "SPKOUTL", +- "Ext Spk", "SPKOUTR", +- "AMIC", "MICBIAS", +- "IN3R", "AMIC"; +- mux-int-port = <2>; +- mux-ext-port = <4>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; +- status = "disabled"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-reset-duration = <10>; +- phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; +- phy-supply = <®_enet>; +- interrupt-parent = <&gpio1>; +- interrupts = <25 IRQ_TYPE_EDGE_FALLING>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clock-frequency = <400000>; +- status = "okay"; +- +- wm8962: audio-codec@1a { +- compatible = "wlf,wm8962"; +- reg = <0x1a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- DCVDD-supply = <®_audio>; +- DBVDD-supply = <®_audio>; +- AVDD-supply = <®_audio>; +- CPVDD-supply = <®_audio>; +- MICVDD-supply = <®_audio>; +- PLLVDD-supply = <®_audio>; +- SPKVDD1-supply = <®_audio>; +- SPKVDD2-supply = <®_audio>; +- gpio-cfg = < +- 0x0000 /* 0:Default */ +- 0x0000 /* 1:Default */ +- 0x0000 /* 2:FN_DMICCLK */ +- 0x0000 /* 3:Default */ +- 0x0000 /* 4:FN_DMICCDAT */ +- 0x0000 /* 5:Default */ +- >; +- }; +-}; +- +-&i2c3 { +- ov5640: camera@10 { +- compatible = "ovti,ov5640"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ov5640>; +- reg = <0x10>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- clock-names = "xclk"; +- DOVDD-supply = <®_mipi>; +- AVDD-supply = <®_mipi>; +- DVDD-supply = <®_mipi>; +- reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; +- powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; +- +- port { +- ov5640_to_mipi_csi2: endpoint { +- remote-endpoint = <&mipi_csi2_in>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- }; +- }; +- }; +- +- pcf8575: gpio@20 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcf8574>; +- compatible = "nxp,pcf8575"; +- reg = <0x20>; +- interrupt-parent = <&gpio6>; +- interrupts = <31 IRQ_TYPE_EDGE_FALLING>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- lines-initial-states = <0x0710>; +- wakeup-source; +- }; +-}; +- +-&ipu1_csi1_from_mipi_vc1 { +- clock-lanes = <0>; +- data-lanes = <1 2>; +-}; +- +-&mipi_csi { +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- mipi_csi2_in: endpoint { +- remote-endpoint = <&ov5640_to_mipi_csi2>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- }; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; +- vpcie-supply = <®_pcie>; +- status = "okay"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +- +-&ssi2 { +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>; +- vmmc-supply = <®_3v3>; +- no-1-8-v; +- keep-power-in-suspend; +- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 +- MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 +- MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 +- MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 +- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */ +- MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */ +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_led0: led0grp { +- fsl,pins = < +- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 +- >; +- }; +- +- pinctrl_ov5640: ov5640grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b1 +- MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b1 +- >; +- }; +- +- pinctrl_pcf8574: pcf8575grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_reg_1v8: reg1v8grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 +- >; +- }; +- +- pinctrl_reg_3v3: reg3v3grp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 +- >; +- }; +- +- pinctrl_reg_audio: reg-audiogrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 +- >; +- }; +- +- pinctrl_reg_enet: reg-enetgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 +- >; +- }; +- +- pinctrl_reg_hdmi: reg-hdmigrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 +- >; +- }; +- +- pinctrl_reg_mipi: reg-mipigrp { +- fsl,pins = ; +- }; +- +- pinctrl_reg_pcie: reg-pciegrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +- >; +- }; +- +- pinctrl_reg_uart3: reguart3grp { +- fsl,pins = < +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +- >; +- }; +- +- pinctrl_reg_usb_h1_vbus: usbh1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 +- >; +- }; +- +- pinctrl_reg_usb_otg: reg-usb-otggrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz { +- fsl,pins = < +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz { +- fsl,pins = < +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 +- >; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6-logicpd-som.dtsi b/scripts/dtc/include-prefixes/arm/imx6-logicpd-som.dtsi +deleted file mode 100644 +index 547fb141ec0c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6-logicpd-som.dtsi ++++ /dev/null +@@ -1,369 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright (C) 2019 Logic PD, Inc. +- +-#include +-#include +- +-/ { +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +- +- reg_wl18xx_vmmc: regulator-wl18xx { +- compatible = "regulator-fixed"; +- regulator-name = "vwl1837"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio7 0 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <70000>; +- enable-active-high; +- }; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, +- <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- nand-on-flash-bbt; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- pfuze100: pmic@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1450000>; +- regulator-name = "vddcore"; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1450000>; +- regulator-name = "vddsoc"; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "gen_3v3"; +- regulator-boot-on; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-name = "sw3a_vddr"; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-name = "sw3b_vddr"; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "gen_rgmii"; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- regulator-name = "gen_5v0"; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "gen_vsns"; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "gen_1v5"; +- }; +- +- vgen2_reg: vgen2 { +- regulator-name = "vgen2"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vgen3 { +- regulator-name = "gen_vadj_0"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vgen4_reg: vgen4 { +- regulator-name = "gen_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-name = "gen_vadj_1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-name = "gen_2v5"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- coin_reg: coin { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- }; +- }; +- +- temperature-sensor@49 { +- compatible = "ti,tmp102"; +- reg = <0x49>; +- interrupt-parent = <&gpio6>; +- interrupts = <15 IRQ_TYPE_LEVEL_LOW>; +- #thermal-sensor-cells = <1>; +- }; +- +- temperature-sensor@4a { +- compatible = "ti,tmp102"; +- reg = <0x4a>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tempsense>; +- interrupt-parent = <&gpio6>; +- interrupts = <15 IRQ_TYPE_LEVEL_LOW>; +- #thermal-sensor-cells = <1>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c64"; +- pagesize = <32>; +- read-only; /* Manufacturing EEPROM programmed at factory */ +- reg = <0x51>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c64"; +- pagesize = <32>; +- reg = <0x52>; +- }; +-}; +- +-/* Reroute power feeding the CPU to come from the external PMIC */ +-®_arm +-{ +- vin-supply = <&sw1a_reg>; +-}; +- +-®_soc +-{ +- vin-supply = <&sw1c_reg>; +-}; +- +-&snvs_poweroff { +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_gpmi_nand: gpmi-nandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 +- >; +- }; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < /* Enable ARM Debugger */ +- MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0 +- MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x1b0b0 +- MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0 +- MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x1b0b0 +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_tempsense: tempsensegrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */ +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 +- MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17049 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10049 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17049 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17049 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17049 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17049 +- MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x130b0 /* WL_IRQ */ +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* WLAN_EN */ +- >; +- }; +-}; +- +-&snvs_poweroff { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "ti,wl1837-st"; +- enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&usdhc1 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- non-removable; +- keep-power-in-suspend; +- wakeup-source; +- vmmc-supply = <&sw2_reg>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- non-removable; +- cap-power-off-card; +- keep-power-in-suspend; +- wakeup-source; +- vmmc-supply = <®_wl18xx_vmmc>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- wlcore: wlcore@2 { +- compatible = "ti,wl1837"; +- reg = <2>; +- interrupt-parent = <&gpio7>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; +- tcxo-clock-frequency = <26000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-alti6p.dts b/scripts/dtc/include-prefixes/arm/imx6dl-alti6p.dts +deleted file mode 100644 +index 4329b372d8cb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-alti6p.dts ++++ /dev/null +@@ -1,564 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (c) 2016 Protonic Holland +- * Copyright (c) 2020 Oleksij Rempel , Pengutronix +- */ +- +-/dts-v1/; +-#include +-#include +-#include +-#include "imx6dl.dtsi" +- +-/ { +- model = "Altesco I6P Board"; +- compatible = "alt,alti6p", "fsl,imx6dl"; +- +- chosen { +- stdout-path = &uart4; +- }; +- +- clock_ksz8081: clock-ksz8081 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- }; +- +- i2c2-mux { +- compatible = "i2c-mux"; +- i2c-parent = <&i2c2>; +- mux-controls = <&i2c_mux>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c@2 { +- reg = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- i2c4-mux { +- compatible = "i2c-mux"; +- i2c-parent = <&i2c4>; +- mux-controls = <&i2c_mux>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c@2 { +- reg = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds>; +- +- led-debug0 { +- function = LED_FUNCTION_STATUS; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-debug1 { +- function = LED_FUNCTION_SD; +- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "disk-activity"; +- }; +- }; +- +- i2c_mux: mux-controller { +- compatible = "gpio-mux"; +- #mux-control-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2cmux>; +- +- mux-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>, +- <&gpio5 11 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_1v8: regulator-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_5v0: regulator-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_h1_vbus: regulator-h1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "h1-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_otg_vbus: regulator-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "otg-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "prti6q-sgtl5000"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,widgets = +- "Microphone", "Microphone Jack", +- "Line", "Line In Jack", +- "Headphone", "Headphone Jack", +- "Speaker", "External Speaker"; +- simple-audio-card,routing = +- "MIC_IN", "Microphone Jack", +- "LINE_IN", "Line In Jack", +- "Headphone Jack", "HP_OUT", +- "External Speaker", "LINE_OUT"; +- +- simple-audio-card,cpu { +- sound-dai = <&ssi1>; +- system-clock-frequency = <0>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- bitclock-master; +- frame-master; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +- +- mux-ssi1 { +- fsl,audmux-port = <0>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN 0 +- IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 +- IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 +- IMX_AUDMUX_V2_PTCR_TFSDIR 0 +- IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) +- >; +- }; +- +- mux-pins3 { +- fsl,audmux-port = <2>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) +- 0 IMX_AUDMUX_V2_PDCR_TXRXEN +- >; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- xceiver-supply = <®_5v0>; +- status = "okay"; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rmii"; +- clocks = <&clks IMX6QDL_CLK_ENET>, +- <&clks IMX6QDL_CLK_ENET>, +- <&clock_ksz8081>; +- clock-names = "ipg", "ahb", "ptp"; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Microchip KSZ8081RNA PHY */ +- rgmii_phy: ethernet-phy@0 { +- reg = <0>; +- interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- reset-deassert-us = <300>; +- }; +- }; +-}; +- +-&gpio1 { +- gpio-line-names = +- "", "SD1_CD", "", "USB_H1_OC", "", "", "", "", +- "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio3 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "ECSPI1_SS1", "", "USB_EXT1_OC", "USB_EXT1_PWR", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio4 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "ETH_RESET", "", "", "BUZZER", "ETH_INTRP", ""; +-}; +- +-&gpio5 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "I2C_EN13", "I2C_EN24", "", "", "", "", +- "", "", "", "", "", "AUDIO_RESET", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hdmi>; +- ddc-i2c-bus = <&i2c1>; +- status = "okay"; +-}; +- +-/* DDC */ +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- sgtl5000: audio-codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0xa>; +- #sound-dai-cells = <0>; +- clocks = <&clks 201>; +- VDDA-supply = <®_3v3>; +- VDDIO-supply = <®_3v3>; +- VDDD-supply = <®_1v8>; +- }; +- +- /* additional i2c devices are added automatically by the boot loader */ +-}; +- +-&i2c2 { +- clock-frequency = <50000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- /* external interface, device are configured from user space */ +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- +- temperature-sensor@70 { +- compatible = "ti,tmp103"; +- reg = <0x70>; +- }; +-}; +- +-&i2c4 { +- clock-frequency = <50000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&ssi1 { +- #sound-dai-cells = <0>; +- fsl,mode = "ac97-slave"; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_h1_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1>; +- phy_type = "utmi"; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- phy_type = "utmi"; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- disable-wp; +- cap-sd-highspeed; +- no-mmc; +- no-sdio; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- no-sd; +- no-sdio; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- >; +- }; +- +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b000 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x3008 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x3008 +- /* CS */ +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x3008 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- /* MX6QDL_ENET_PINGRP4 */ +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 +- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 +- +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 +- /* Phy reset */ +- MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 +- /* nINTRP */ +- MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 +- >; +- }; +- +- pinctrl_hdmi: hdmigrp { +- fsl,pins = < +- /* NOTE: DDC is done via I2C2, so DON'T configure DDC +- * pins for HDMI! +- */ +- MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x4001f8b1 +- MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x4001f8b1 +- >; +- }; +- +- pinctrl_i2cmux: i2cmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b0 +- MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b0 +- >; +- }; +- +- pinctrl_leds: ledsgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x8 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbh1: usbh1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1B058 +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1B058 +- +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 +- MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-apf6dev.dts b/scripts/dtc/include-prefixes/arm/imx6dl-apf6dev.dts +deleted file mode 100644 +index 3dcce3454b08..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-apf6dev.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Copyright 2015 Armadeus Systems +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-apf6.dtsi" +-#include "imx6qdl-apf6dev.dtsi" +- +-/ { +- model = "Armadeus APF6 Solo Module on APF6Dev Board"; +- compatible = "armadeus,imx6dl-apf6dev", "armadeus,imx6dl-apf6", "fsl,imx6dl"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-aristainetos2_4.dts b/scripts/dtc/include-prefixes/arm/imx6dl-aristainetos2_4.dts +deleted file mode 100644 +index dfa6f64d43cc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-aristainetos2_4.dts ++++ /dev/null +@@ -1,158 +0,0 @@ +-/* +- * support for the imx6 based aristainetos2 board +- * +- * Copyright (C) 2015 Heiko Schocher +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-aristainetos2.dtsi" +- +-/ { +- model = "aristainetos2 i.MX6 Dual Lite Board 4"; +- compatible = "abb,aristainetos2-imx6dl-4", "fsl,imx6dl"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- display0: disp0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx-parallel-display"; +- interface-pix-fmt = "rgb24"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu_disp>; +- +- port@0 { +- reg = <0>; +- display0_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&ecspi1 { +- lcd_panel: display@0 { +- compatible = "lg,lg4573"; +- spi-max-frequency = <10000000>; +- reg = <0>; +- power-on-delay = <10>; +- +- display-timings { +- 480x800p57 { +- native-mode; +- clock-frequency = <27000027>; +- hactive = <480>; +- vactive = <800>; +- hfront-porch = <10>; +- hback-porch = <59>; +- hsync-len = <10>; +- vback-porch = <15>; +- vfront-porch = <15>; +- vsync-len = <15>; +- hsync-active = <1>; +- vsync-active = <1>; +- }; +- }; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- touch: touch@4b { +- compatible = "atmel,maxtouch"; +- reg = <0x4b>; +- interrupt-parent = <&gpio2>; +- interrupts = <9 8>; +- }; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&display0_in>; +-}; +- +-&iomuxc { +- pinctrl_ipu_disp: ipudisp1grp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xE1 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xE1 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xE1 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xE1 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xE1 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xE1 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xE1 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xE1 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xE1 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xE1 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xE1 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xE1 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xE1 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xE1 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xE1 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xE1 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xE1 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xE1 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xE1 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xE1 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xE1 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xE1 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xE1 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xE1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-aristainetos2_7.dts b/scripts/dtc/include-prefixes/arm/imx6dl-aristainetos2_7.dts +deleted file mode 100644 +index 5e15212eaf3a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-aristainetos2_7.dts ++++ /dev/null +@@ -1,98 +0,0 @@ +-/* +- * support for the imx6 based aristainetos2 board +- * +- * Copyright (C) 2015 Heiko Schocher +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-aristainetos2.dtsi" +- +-/ { +- model = "aristainetos2 i.MX6 Dual Lite Board 7"; +- compatible = "abb,aristainetos2-imx6dl-7", "fsl,imx6dl"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- panel: panel { +- compatible = "lg,lb070wv8"; +- backlight = <&backlight>; +- enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- touch: touch@4d { +- compatible = "atmel,maxtouch"; +- reg = <0x4d>; +- interrupt-parent = <&gpio2>; +- interrupts = <9 8>; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- status = "okay"; +- +- port@0 { +- reg = <0>; +- lvds0_in: endpoint { +- remote-endpoint = <&ipu1_di0_lvds0>; +- }; +- }; +- +- port@4 { +- reg = <4>; +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-aristainetos_4.dts b/scripts/dtc/include-prefixes/arm/imx6dl-aristainetos_4.dts +deleted file mode 100644 +index cc861a43eb58..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-aristainetos_4.dts ++++ /dev/null +@@ -1,84 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * support fot the imx6 based aristainetos board +- * +- * Copyright (C) 2014 Heiko Schocher +- */ +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-aristainetos.dtsi" +- +-/ { +- model = "aristainetos i.MX6 Dual Lite Board 4"; +- compatible = "abb,aristainetos-imx6dl-4", "fsl,imx6dl"; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- enable-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_backlight>; +- status = "okay"; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- display0: disp0 { +- compatible = "fsl,imx-parallel-display"; +- interface-pix-fmt = "rgb24"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu_disp>; +- status = "okay"; +- +- display-timings { +- 480x800p60 { +- native-mode; +- clock-frequency = <30000000>; +- hactive = <480>; +- vactive = <800>; +- hfront-porch = <59>; +- hback-porch = <10>; +- hsync-len = <10>; +- vback-porch = <15>; +- vfront-porch = <15>; +- vsync-len = <15>; +- hsync-active = <1>; +- vsync-active = <1>; +- }; +- }; +- +- port { +- display0_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- }; +-}; +- +-&ecspi2 { +- cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&display0_in>; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-aristainetos_7.dts b/scripts/dtc/include-prefixes/arm/imx6dl-aristainetos_7.dts +deleted file mode 100644 +index b6cb78870cd5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-aristainetos_7.dts ++++ /dev/null +@@ -1,74 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * support fot the imx6 based aristainetos board +- * +- * Copyright (C) 2014 Heiko Schocher +- */ +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-aristainetos.dtsi" +- +-/ { +- model = "aristainetos i.MX6 Dual Lite Board 7"; +- compatible = "abb,aristainetos-imx6dl-7", "fsl,imx6dl"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- display0: disp0 { +- compatible = "fsl,imx-parallel-display"; +- interface-pix-fmt = "rgb24"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu_disp>; +- status = "okay"; +- +- display-timings { +- 800x480p60 { +- native-mode; +- clock-frequency = <33246000>; +- hactive = <800>; +- vactive = <480>; +- hfront-porch = <88>; +- hback-porch = <88>; +- hsync-len = <80>; +- vback-porch = <10>; +- vfront-porch = <10>; +- vsync-len = <25>; +- vsync-active = <1>; +- }; +- }; +- +- port { +- display0_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm3 0 3000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_backlight>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&display0_in>; +-}; +- +-&pwm3 { +- #pwm-cells = <2>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-b105pv2.dts b/scripts/dtc/include-prefixes/arm/imx6dl-b105pv2.dts +deleted file mode 100644 +index 411aa72d344b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-b105pv2.dts ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 or MIT +-// +-// Device Tree Source for General Electric B105Pv2 +-// +-// Copyright 2018-2021 General Electric Company +-// Copyright 2018-2021 Collabora +- +-/dts-v1/; +-#include "imx6dl-b1x5pv2.dtsi" +- +-/ { +- model = "General Electric B105Pv2"; +- compatible = "ge,imx6dl-b105pv2", "congatec,qmx6", "fsl,imx6dl"; +- +- panel { +- compatible = "auo,g101evn010"; +- }; +-}; +- +-&i2c3 { +- touchscreen@41 { +- compatible = "ilitek,ili251x"; +- reg = <0x41>; +- pinctrl-names = "default"; +- pinctrl-0 =<&pinctrl_q7_gpio0>; +- interrupt-parent = <&gpio5>; +- interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>; +- touchscreen-size-x = <1280>; +- touchscreen-size-y = <800>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-b105v2.dts b/scripts/dtc/include-prefixes/arm/imx6dl-b105v2.dts +deleted file mode 100644 +index d011127c635b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-b105v2.dts ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 or MIT +-// +-// Device Tree Source for General Electric B105v2 +-// +-// Copyright 2018-2021 General Electric Company +-// Copyright 2018-2021 Collabora +- +-/dts-v1/; +-#include "imx6dl-b1x5v2.dtsi" +- +-/ { +- model = "General Electric B105v2"; +- compatible = "ge,imx6dl-b105v2", "congatec,qmx6", "fsl,imx6dl"; +- +- panel { +- compatible = "auo,g101evn010"; +- }; +-}; +- +-&i2c3 { +- touchscreen@41 { +- compatible = "ilitek,ili251x"; +- reg = <0x41>; +- pinctrl-names = "default"; +- pinctrl-0 =<&pinctrl_q7_gpio0>; +- interrupt-parent = <&gpio5>; +- interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>; +- touchscreen-size-x = <1280>; +- touchscreen-size-y = <800>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-b125pv2.dts b/scripts/dtc/include-prefixes/arm/imx6dl-b125pv2.dts +deleted file mode 100644 +index ca840fa84052..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-b125pv2.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 or MIT +-// +-// Device Tree Source for General Electric B125Pv2 +-// +-// Copyright 2018-2021 General Electric Company +-// Copyright 2018-2021 Collabora +- +-/dts-v1/; +-#include "imx6dl-b1x5pv2.dtsi" +- +-/ { +- model = "General Electric B125Pv2"; +- compatible = "ge,imx6dl-b125pv2", "congatec,qmx6", "fsl,imx6dl"; +- +- panel { +- compatible = "auo,g121ean01"; +- }; +-}; +- +-&i2c3 { +- touchscreen@2a { +- compatible = "eeti,exc80h60"; +- reg = <0x2a>; +- pinctrl-names = "default"; +- pinctrl-0 =<&pinctrl_q7_gpio0>; +- interrupt-parent = <&gpio5>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-b125v2.dts b/scripts/dtc/include-prefixes/arm/imx6dl-b125v2.dts +deleted file mode 100644 +index 81e5a9cb8900..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-b125v2.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 or MIT +-// +-// Device Tree Source for General Electric B125v2 +-// +-// Copyright 2018-2021 General Electric Company +-// Copyright 2018-2021 Collabora +- +-/dts-v1/; +-#include "imx6dl-b1x5v2.dtsi" +- +-/ { +- model = "General Electric B125v2"; +- compatible = "ge,imx6dl-b125v2", "congatec,qmx6", "fsl,imx6dl"; +- +- panel { +- compatible = "auo,g121ean01"; +- }; +-}; +- +-&i2c3 { +- touchscreen@2a { +- compatible = "eeti,exc80h60"; +- reg = <0x2a>; +- pinctrl-names = "default"; +- pinctrl-0 =<&pinctrl_q7_gpio0>; +- interrupt-parent = <&gpio5>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-b155v2.dts b/scripts/dtc/include-prefixes/arm/imx6dl-b155v2.dts +deleted file mode 100644 +index c861937b30f6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-b155v2.dts ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 or MIT +-// +-// Device Tree Source for General Electric B155v2 +-// +-// Copyright 2018-2021 General Electric Company +-// Copyright 2018-2021 Collabora +- +-/dts-v1/; +-#include "imx6dl-b1x5v2.dtsi" +- +-/ { +- model = "General Electric B155v2"; +- compatible = "ge,imx6dl-b155v2", "congatec,qmx6", "fsl,imx6dl"; +- +- panel { +- compatible = "auo,g156xtn01"; +- }; +-}; +- +-&i2c3 { +- touchscreen@2a { +- compatible = "eeti,exc80h84"; +- reg = <0x2a>; +- pinctrl-names = "default"; +- pinctrl-0 =<&pinctrl_q7_gpio0>; +- interrupt-parent = <&gpio5>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- touchscreen-inverted-x; +- touchscreen-inverted-y; +- reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-b1x5pv2.dtsi b/scripts/dtc/include-prefixes/arm/imx6dl-b1x5pv2.dtsi +deleted file mode 100644 +index ec5b66453156..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-b1x5pv2.dtsi ++++ /dev/null +@@ -1,413 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 or MIT +-// +-// Device Tree Source for General Electric B1x5Pv2 +-// patient monitor series +-// +-// Copyright 2018-2021 General Electric Company +-// Copyright 2018-2021 Collabora +- +-#include +-#include "imx6dl-qmx6.dtsi" +- +-/ { +- chosen { +- stdout-path = &uart3; +- }; +- +- /* Do not allow frequencies above 800MHz */ +- cpus { +- cpu@0 { +- operating-points = < +- /* kHz uV */ +- 792000 1175000 +- 396000 1150000 +- >; +- fsl,soc-operating-points = < +- /* ARM kHz SOC-PU uV */ +- 792000 1175000 +- 396000 1175000 +- >; +- }; +- +- cpu@1 { +- operating-points = < +- /* kHz uV */ +- 792000 1175000 +- 396000 1150000 +- >; +- fsl,soc-operating-points = < +- /* ARM kHz SOC-PU uV */ +- 792000 1175000 +- 396000 1175000 +- >; +- }; +- }; +- +- reg_syspwr: regulator-12v { +- compatible = "regulator-fixed"; +- regulator-name = "SYS_PWR"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- reg_5v_pmc: regulator-5v-pmc { +- compatible = "regulator-fixed"; +- regulator-name = "5V PMC"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <®_syspwr>; +- }; +- +- reg_5v: regulator-5v { +- compatible = "regulator-fixed"; +- regulator-name = "5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <®_syspwr>; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <®_syspwr>; +- }; +- +- reg_5v0_audio: regulator-5v0-audio { +- compatible = "regulator-fixed"; +- regulator-name = "5V0_AUDIO"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <®_5v>; +- gpio = <&tca6424a 16 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- /* +- * This must be always-on for da7212, which has some not +- * properly documented dependencies for it's speaker supply +- * pin. The issue manifests as speaker volume being very low. +- */ +- regulator-always-on; +- }; +- +- +- reg_3v3_audio: regulator-3v3-audio { +- compatible = "regulator-fixed"; +- regulator-name = "3V3_AUDIO"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <®_3v3>; +- pinctrl-0 = <&pinctrl_q7_hda_reset>; +- pinctrl-names = "default"; +- gpio = <&gpio6 8 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_2v5_audio: regulator-2v5-audio { +- compatible = "regulator-fixed"; +- regulator-name = "2V5_AUDIO"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- vin-supply = <®_3v3_audio>; +- +- }; +- +- reg_wlan: regulator-wlan { +- compatible = "regulator-fixed"; +- regulator-name = "WLAN"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <®_3v3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_q7_sdio_power>; +- gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- startup-delay-us = <70000>; +- }; +- +- reg_bl: regulator-backlight { +- compatible = "regulator-fixed"; +- regulator-name = "LED_VCC"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- vin-supply = <®_syspwr>; +- pinctrl-0 = <&pinctrl_q7_lcd_power>; +- pinctrl-names = "default"; +- gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_lcd: regulator-lcd { +- compatible = "regulator-fixed"; +- regulator-name = "LCD_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <®_5v>; +- }; +- +- usb_power: regulator-usb-power { +- compatible = "regulator-fixed"; +- regulator-name = "USB POWER"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <®_5v>; +- }; +- +- charger: battery-charger { +- compatible = "gpio-charger"; /* ti,bq24172 */ +- charger-type = "mains"; +- gpios = <&tca6424a 3 GPIO_ACTIVE_LOW>; +- charge-current-limit-gpios = <&tca6424a 11 GPIO_ACTIVE_HIGH>, +- <&tca6424a 12 GPIO_ACTIVE_HIGH>; +- charge-current-limit-mapping = <1300000 0x0>, +- <700000 0x1>, +- <0 0x2>; +- charge-status-gpios = <&tca6424a 6 GPIO_ACTIVE_HIGH>; +- }; +- +- poweroff { +- compatible = "gpio-poweroff"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_q7_spi_cs1>; +- gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; +- }; +- +- power-button-key { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_q7_sleep_button>; +- +- power-button { +- label = "power button"; +- gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- rotary-encoder-key { +- compatible = "gpio-keys"; +- +- rotary-encoder-press { +- label = "rotary-encoder press"; +- gpios = <&tca6424a 0 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- linux,can-disable; +- }; +- }; +- +- rotary-encoder { +- compatible = "rotary-encoder"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_q7_gpio2 &pinctrl_q7_gpio4>; +- gpios = <&gpio4 26 GPIO_ACTIVE_LOW>, <&gpio1 0 GPIO_ACTIVE_LOW>; +- rotary-encoder,relative-axis; +- rotary-encoder,steps-per-period = <2>; +- wakeup-source; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_q7_gpio1 &pinctrl_q7_gpio3 &pinctrl_q7_gpio5>; +- +- alarm1 { +- label = "alarm:red"; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- }; +- +- alarm2 { +- label = "alarm:yellow"; +- gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; +- }; +- +- alarm3 { +- label = "alarm:blue"; +- gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_q7_backlight_enable>; +- power-supply = <®_bl>; +- pwms = <&pwm4 0 5000000 0>; +- brightness-levels = <0 255>; +- num-interpolated-steps = <255>; +- default-brightness-level = <179>; +- enable-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- }; +- +- panel { +- backlight = <&backlight>; +- power-supply = <®_lcd>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&dailink_master>; +- simple-audio-card,frame-master = <&dailink_master>; +- simple-audio-card,widgets = "Speaker", "Ext Spk"; +- simple-audio-card,audio-routing = "Ext Spk", "LINE"; +- +- simple-audio-card,cpu { +- sound-dai = <&ssi1>; +- }; +- +- dailink_master: simple-audio-card,codec { +- sound-dai = <&codec>; +- }; +- }; +- +- clk_ext_audio_codec: clock-codec { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <12288000>; +- }; +-}; +- +-&audmux { +- status = "okay"; +-}; +- +-&fec { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&i2c1 { +- battery: battery@b { +- compatible = "ti,bq20z65", "sbs,sbs-battery"; +- reg = <0x0b>; +- sbs,battery-detect-gpios = <&tca6424a 5 GPIO_ACTIVE_LOW>; +- sbs,i2c-retry-count = <5>; +- power-supplies = <&charger>; +- }; +- +- codec: audio-codec@1a { +- compatible = "dlg,da7212"; +- reg = <0x1a>; +- #sound-dai-cells = <0>; +- VDDA-supply = <®_2v5_audio>; +- VDDSP-supply = <®_5v0_audio>; +- VDDMIC-supply = <®_3v3_audio>; +- VDDIO-supply = <®_3v3_audio>; +- clocks = <&clk_ext_audio_codec>; +- clock-names = "mclk"; +- }; +-}; +- +-&i2c5 { +- tca6424a: gpio-controller@22 { +- compatible = "ti,tca6424"; +- reg = <0x22>; +- gpio-controller; +- #gpio-cells = <2>; +- vcc-supply = <®_3v3>; +- interrupt-parent = <&gpio7>; +- interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_q7_gpio6>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-line-names = "GPIO_ROTOR#", "ACM_IO_INT", "TMP_SENSOR_IRQ", "AC_IN", +- "TF_S", "BATT_T", "LED_INC_CHAR", "ACM1_OCF", +- "ACM2_OCF", "ACM_IO_RST", "USB1_POWER_EN", "EGPIO_CC_CTL0", +- "EGPIO_CC_CTL1", "12V_OEMNBP_EN", "CP2105_RST", "", +- "SPEAKER_PA_EN", "ARM7_UPI_RESET", "ARM7_PWR_RST", "NURSE_CALL", +- "MARKER_EN", "EGPIO_TOUCH_RST", "PRESSURE_INT1", "PRESSURE_INT2"; +- +- }; +- +- tmp75: temperature-sensor@48 { +- compatible = "ti,tmp75"; +- reg = <0x48>; +- vs-supply = <®_3v3>; +- interrupt-parent = <&tca6424a>; +- interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds0: lvds-channel@0 { +- status = "okay"; +- fsl,data-mapping = "spwg"; +- fsl,data-width = <24>; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&pwm4 { +- status = "okay"; +-}; +- +-&ssi1 { +- fsl,mode = "i2s-slave"; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <&usb_power>; +- disable-over-current; +- dr_mode = "host"; +- status = "okay"; +- +- /* +- * TPS2051BDGN fault-gpio is connected to Q7[86] USB_0_1_OC_N. +- * On QMX6 this is not connceted to the i.MX6, but to the USB Hub +- * from &usbh1. This means, that we cannot easily detect and handle +- * over-current events. Fortunately the regulator limits the current +- * automatically, so the hardware is still protected. +- */ +-}; +- +-&usdhc4 { +- /* WiFi module */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <4>; +- no-1-8-v; +- non-removable; +- wakeup-source; +- keep-power-in-suspend; +- cap-power-off-card; +- max-frequency = <25000000>; +- vmmc-supply = <®_wlan>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- wlcore: wlcore@2 { +- compatible = "ti,wl1837"; +- reg = <2>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_q7_gpio7>; +- +- interrupt-parent = <&gpio4>; +- interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; +- +- tcxo-clock-frequency = <26000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-b1x5v2.dtsi b/scripts/dtc/include-prefixes/arm/imx6dl-b1x5v2.dtsi +deleted file mode 100644 +index a326a331508e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-b1x5v2.dtsi ++++ /dev/null +@@ -1,58 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 or MIT +-// +-// Device Tree Source for General Electric B1x5v2 +-// patient monitor series +-// +-// Copyright 2018-2021 General Electric Company +-// Copyright 2018-2021 Collabora +- +-#include +-#include "imx6dl-b1x5pv2.dtsi" +- +-/ { +- reg_3v3_acm: regulator-3v3-acm { +- compatible = "regulator-fixed"; +- regulator-name = "3V3 ACM"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- vin-supply = <®_3v3>; +- }; +-}; +- +-&i2c1 { +- tca6416: gpio-controller@21 { +- compatible = "ti,tca6416"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- reset-gpios = <&tca6424a 9 GPIO_ACTIVE_LOW>; +- vcc-supply = <®_3v3_acm>; +- gpio-line-names = "ACM1_EN", "ACM1_CL0", "ACM1_CL1", "ACM1_CL2", +- "", "ACM2_EN", "ACM2_CL0", "ACM2_CL1", +- "ACM2_CL2", "", "", "", +- "", "", "", ""; +- +- /* +- * The interrupt pin is connected to &tca6424a pin 1, but the Linux +- * TCA6424 driver cannot handle low type interrupts at the moment +- * (and support cannot be added without some ugly hacks). Since this +- * controller does not have any input type GPIOs, just pretend +- * that the interrupt pin is unconnected. +- */ +- }; +-}; +- +-&i2c5 { +- mpl3115a2: pressure-sensor@60 { +- compatible = "fsl,mpl3115"; +- reg = <0x60>; +- vcc-supply = <®_3v3_acm>; +- +- /* +- * The MPL3115 interrupts are connected to pin 22 and 23 +- * of &tca6424a, but the binding does not yet support +- * interrupts. +- */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-colibri-eval-v3.dts b/scripts/dtc/include-prefixes/arm/imx6dl-colibri-eval-v3.dts +deleted file mode 100644 +index 7da74e6f46d9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-colibri-eval-v3.dts ++++ /dev/null +@@ -1,261 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2014-2020 Toradex +- * Copyright 2012 Freescale Semiconductor, Inc. +- * Copyright 2011 Linaro Ltd. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "imx6dl.dtsi" +-#include "imx6qdl-colibri.dtsi" +- +-/ { +- model = "Toradex Colibri iMX6DL/S on Colibri Evaluation Board V3"; +- compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl", +- "fsl,imx6dl"; +- +- /* Will be filled by the bootloader */ +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0>; +- }; +- +- aliases { +- i2c0 = &i2c2; +- i2c1 = &i2c3; +- }; +- +- aliases { +- rtc0 = &rtc_i2c; +- rtc1 = &snvs_rtc; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- /* Fixed crystal dedicated to mcp251x */ +- clk16m: clock-16m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <16000000>; +- clock-output-names = "clk16m"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- wakeup { +- label = "Wake-Up"; +- gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */ +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- lcd_display: disp0 { +- compatible = "fsl,imx-parallel-display"; +- #address-cells = <1>; +- #size-cells = <0>; +- interface-pix-fmt = "bgr666"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_lcdif>; +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- lcd_display_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lcd_display_out: endpoint { +- remote-endpoint = <&lcd_panel_in>; +- }; +- }; +- }; +- +- panel: panel { +- /* +- * edt,et057090dhu: EDT 5.7" LCD TFT +- * edt,et070080dh6: EDT 7.0" LCD TFT +- */ +- compatible = "edt,et057090dhu"; +- backlight = <&backlight>; +- +- port { +- lcd_panel_in: endpoint { +- remote-endpoint = <&lcd_display_out>; +- }; +- }; +- }; +-}; +- +-&backlight { +- brightness-levels = <0 127 191 223 239 247 251 255>; +- default-brightness-level = <1>; +- status = "okay"; +-}; +- +-/* Colibri SSP */ +-&ecspi4 { +- status = "okay"; +- +- mcp251x0: mcp251x@0 { +- compatible = "microchip,mcp2515"; +- reg = <0>; +- clocks = <&clk16m>; +- interrupt-parent = <&gpio3>; +- interrupts = <27 0x2>; +- spi-max-frequency = <10000000>; +- status = "okay"; +- }; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-/* +- * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) +- */ +-&i2c3 { +- status = "okay"; +- +- /* +- * Touchscreen is using SODIMM 28/30, also used for PWM, PWM, +- * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms +- */ +- touchscreen@4a { +- compatible = "atmel,maxtouch"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcap_1>; +- reg = <0x4a>; +- interrupt-parent = <&gpio1>; +- interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */ +- reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 */ +- status = "disabled"; +- }; +- +- /* M41T0M6 real time clock on carrier board */ +- rtc_i2c: rtc@68 { +- compatible = "st,m41t0"; +- reg = <0x68>; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &pinctrl_weim_gpio_1 &pinctrl_weim_gpio_2 +- &pinctrl_weim_gpio_3 &pinctrl_weim_gpio_4 +- &pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6 +- &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1 +- >; +- +- pinctrl_pcap_1: pcap1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* SODIMM 28 */ +- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SODIMM 30 */ +- >; +- }; +- +- pinctrl_mxt_ts: mxttsgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 /* SODIMM 107 */ +- MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */ +- >; +- }; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&lcd_display_in>; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&pwm3 { +- status = "okay"; +-}; +- +-&pwm4 { +- status = "okay"; +-}; +- +-®_usb_host_vbus { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_host_vbus>; +- status = "okay"; +-}; +- +-&usbotg { +- status = "okay"; +-}; +- +-/* Colibri MMC */ +-&usdhc1 { +- status = "okay"; +-}; +- +-&weim { +- status = "okay"; +- +- /* weim memory map: 32MB on CS0, CS1, CS2 and CS3 */ +- ranges = <0 0 0x08000000 0x02000000 +- 1 0 0x0a000000 0x02000000 +- 2 0 0x0c000000 0x02000000 +- 3 0 0x0e000000 0x02000000>; +- +- /* SRAM on Colibri nEXT_CS0 */ +- sram@0,0 { +- compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram"; +- reg = <0 0 0x00010000>; +- #address-cells = <1>; +- #size-cells = <1>; +- bank-width = <2>; +- fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000 +- 0x00000000 0x04000040 0x00000000>; +- }; +- +- /* SRAM on Colibri nEXT_CS1 */ +- sram@1,0 { +- compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram"; +- reg = <1 0 0x00010000>; +- #address-cells = <1>; +- #size-cells = <1>; +- bank-width = <2>; +- fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000 +- 0x00000000 0x04000040 0x00000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-colibri-v1_1-eval-v3.dts b/scripts/dtc/include-prefixes/arm/imx6dl-colibri-v1_1-eval-v3.dts +deleted file mode 100644 +index 223275f028f1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-colibri-v1_1-eval-v3.dts ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2020 Toradex +- */ +- +-/dts-v1/; +- +-#include "imx6dl-colibri-eval-v3.dts" +-#include "imx6qdl-colibri-v1_1-uhs.dtsi" +- +-/ { +- model = "Toradex Colibri iMX6DL/S V1.1 on Colibri Evaluation Board V3"; +- compatible = "toradex,colibri_imx6dl-v1_1-eval-v3", +- "toradex,colibri_imx6dl-v1_1", +- "toradex,colibri_imx6dl-eval-v3", +- "toradex,colibri_imx6dl", +- "fsl,imx6dl"; +-}; +- +-/* Colibri MMC */ +-&usdhc1 { +- status = "okay"; +- /* +- * Please make sure your carrier board does not pull-up any of +- * the MMC/SD signals to 3.3 volt before attempting to activate +- * UHS-I support. +- * To let signaling voltage be changed to 1.8V, please +- * delete no-1-8-v property (example below): +- * /delete-property/no-1-8-v; +- */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-cubox-i-emmc-som-v15.dts b/scripts/dtc/include-prefixes/arm/imx6dl-cubox-i-emmc-som-v15.dts +deleted file mode 100644 +index 2b2fc360b865..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-cubox-i-emmc-som-v15.dts ++++ /dev/null +@@ -1,52 +0,0 @@ +-/* +- * Copyright (C) 2014 Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-ti.dtsi" +-#include "imx6qdl-sr-som-emmc.dtsi" +-#include "imx6qdl-cubox-i.dtsi" +- +-/ { +- model = "SolidRun Cubox-i Solo/DualLite (1.5som+emmc)"; +- compatible = "solidrun,cubox-i/dl", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-cubox-i-som-v15.dts b/scripts/dtc/include-prefixes/arm/imx6dl-cubox-i-som-v15.dts +deleted file mode 100644 +index e09c565d1d1f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-cubox-i-som-v15.dts ++++ /dev/null +@@ -1,51 +0,0 @@ +-/* +- * Copyright (C) 2014 Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-ti.dtsi" +-#include "imx6qdl-cubox-i.dtsi" +- +-/ { +- model = "SolidRun Cubox-i Solo/DualLite (1.5som)"; +- compatible = "solidrun,cubox-i/dl", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-cubox-i.dts b/scripts/dtc/include-prefixes/arm/imx6dl-cubox-i.dts +deleted file mode 100644 +index 2b1b3e193f53..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-cubox-i.dts ++++ /dev/null +@@ -1,51 +0,0 @@ +-/* +- * Copyright (C) 2014 Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-brcm.dtsi" +-#include "imx6qdl-cubox-i.dtsi" +- +-/ { +- model = "SolidRun Cubox-i Solo/DualLite"; +- compatible = "solidrun,cubox-i/dl", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-dfi-fs700-m60.dts b/scripts/dtc/include-prefixes/arm/imx6dl-dfi-fs700-m60.dts +deleted file mode 100644 +index cece4aafdad8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-dfi-fs700-m60.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Sascha Hauer +- */ +- +-#ifndef __DTS_V1__ +-#define __DTS_V1__ +-/dts-v1/; +-#endif +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-dfi-fs700-m60.dtsi" +- +-/ { +- model = "DFI FS700-M60-6DL i.MX6dl Q7 Board"; +- compatible = "dfi,fs700-m60-6dl", "dfi,fs700e-m60", "fsl,imx6dl"; +- +- /* Will be filled by the bootloader */ +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-dhcom-picoitx.dts b/scripts/dtc/include-prefixes/arm/imx6dl-dhcom-picoitx.dts +deleted file mode 100644 +index 038bb0025556..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-dhcom-picoitx.dts ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2021 DH electronics GmbH +- * +- * DHCOM iMX6 variant: +- * DHCM-iMX6DL-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2 +- * DHCOM PCB number: 493-300 or newer +- * PicoITX PCB number: 487-600 or newer +- */ +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-dhcom-som.dtsi" +-#include "imx6qdl-dhcom-picoitx.dtsi" +- +-/ { +- model = "DH electronics i.MX6DL DHCOM on PicoITX"; +- compatible = "dh,imx6dl-dhcom-picoitx", "dh,imx6dl-dhcom-som", +- "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-eckelmann-ci4x10.dts b/scripts/dtc/include-prefixes/arm/imx6dl-eckelmann-ci4x10.dts +deleted file mode 100644 +index b4a9523e325b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-eckelmann-ci4x10.dts ++++ /dev/null +@@ -1,381 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2016 Eckelmann AG. +- * Copyright (C) 2013 Freescale Semiconductor, Inc. +- */ +- +-/dts-v1/; +- +-#include +- +-#include "imx6dl.dtsi" +- +-/ { +- model = "Eckelmann CI 4X10 Board"; +- compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl"; +- +- chosen { +- stdout-path = &uart3; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- rmii_clk: clock-rmii { +- /* This clock is provided by the phy (KSZ8091RNB) */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- }; +- +- reg_usb_h1_vbus: regulator-usb-h1-vbus { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>; +- compatible = "regulator-fixed"; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- siox { +- compatible = "eckelmann,siox-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_siox>; +- din-gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>; +- dout-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; +- dclk-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; +- dld-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- status = "okay"; +-}; +- +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- flash@0 { +- compatible = "everspin,mr25h256"; +- reg = <0>; +- spi-max-frequency = <15000000>; +- }; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- tpm@0 { +- compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; +- reg = <0>; +- spi-max-frequency = <10000000>; +- }; +-}; +- +-&gpio2 { +- gpio-line-names = "buzzer", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio4 { +- gpio-line-names = "", "", "", "", "", "", "", "in2", +- "prio2", "prio1", "aux", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio6 { +- gpio-line-names = "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "in1", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- temperature-sensor@49 { +- compatible = "ad,ad7414"; +- reg = <0x49>; +- }; +- +- rtc@51 { +- compatible = "nxp,pcf2127"; +- reg = <0x51>; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hog { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00000018 /* buzzer */ +- MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x00000018 /* OUT_1 */ +- MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x00000018 /* OUT_2 */ +- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x00000018 /* OUT_3 */ +- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x00000000 /* In1 */ +- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x00000000 /* In2 */ +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x00000018 /* unused watchdog pin */ +- MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x00000018 /* unused watchdog pin */ +- +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x000100a0 +- MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x000100a0 +- MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x000100a0 +- MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000100a0 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x000100b1 +- MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x000100b1 +- MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x000100b1 +- MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000100b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x0001b098 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x0001b098 +- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098 +- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098 +- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x0001b0b0 +- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x0001b0b0 +- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x0001b0b0 +- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x0001b0b0 +- MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x00000018 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x0001b020 +- MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x0001b0b0 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x0001b020 +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x0001b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- /* without SION i2c doesn't detect bus busy */ +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b820 +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b820 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x00000018 +- >; +- }; +- +- pinctrl_reg_usb_h1_vbus: reg_usb_h1_vbusgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0001b0b0 +- >; +- }; +- +- pinctrl_siox: sioxgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x0001b010 /* DIN */ +- MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b010 /* DOUT */ +- MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */ +- MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x0001b010 /* DLD */ +- >; +- }; +- +- pinctrl_uart1_dte: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x0001b010 +- MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x0001b010 +- MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x0001b010 +- MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0001b010 +- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0001b010 /* DCD */ +- MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0001b010 /* DTR */ +- MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0001b010 /* DSR */ +- >; +- }; +- +- pinctrl_uart2_dte: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0001b010 +- MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0001b010 +- MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0001b010 +- MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0001b010 +- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b010 /* DCD */ +- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b010 /* DTR */ +- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0001b010 /* DSR */ +- >; +- }; +- +- pinctrl_uart3_dce: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x0001b010 +- MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x0001b010 +- >; +- }; +- +- pinctrl_uart4_dce: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x0001b010 +- MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x0001b010 +- MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x0001b010 +- >; +- }; +- +- pinctrl_uart5_dce: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x0001b010 +- MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x0001b010 +- MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x0001b010 /* RTS */ +- >; +- }; +- +- pinctrl_usbh1: usbh1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0001b0b0 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x00017059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x00010059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x00017059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x00017059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x00017059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x00017059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x00017059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x00017059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x00017059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x00017059 +- >; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rmii"; +- phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; +- phy-handle = <&phy>; +- clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio1 20 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1_dte>; +- uart-has-rtscts; +- fsl,dte-mode; +- dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; +- dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; +- dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2_dte>; +- uart-has-rtscts; +- fsl,dte-mode; +- dcd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +- dtr-gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; +- dsr-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3_dce>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4_dce>; +- rts-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5_dce>; +- rts-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&usbh1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1>; +- vbus-supply = <®_usb_h1_vbus>; +- status = "okay"; +-}; +- +-&usbotg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-emcon-avari.dts b/scripts/dtc/include-prefixes/arm/imx6dl-emcon-avari.dts +deleted file mode 100644 +index 407ad8d43c84..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-emcon-avari.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 or MIT) +-// +-// Copyright (C) 2018 emtrion GmbH +-// +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-emcon.dtsi" +-#include "imx6qdl-emcon-avari.dtsi" +- +-/ { +- model = "emtrion SoM emCON-MX6 Solo/Dual-Lite Avari"; +- compatible = "emtrion,emcon-mx6-avari", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-gw51xx.dts b/scripts/dtc/include-prefixes/arm/imx6dl-gw51xx.dts +deleted file mode 100644 +index 9956d12a1245..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-gw51xx.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Gateworks Corporation +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-gw51xx.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 DualLite/Solo GW51XX"; +- compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-gw52xx.dts b/scripts/dtc/include-prefixes/arm/imx6dl-gw52xx.dts +deleted file mode 100644 +index 9ea23dd54f3c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-gw52xx.dts ++++ /dev/null +@@ -1,71 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Gateworks Corporation +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-gw52xx.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 DualLite/Solo GW52XX"; +- compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl"; +-}; +- +-&i2c3 { +- adv7180: camera@20 { +- compatible = "adi,adv7180"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adv7180>; +- reg = <0x20>; +- powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; +- interrupt-parent = <&gpio3>; +- interrupts = <30 IRQ_TYPE_LEVEL_LOW>; +- +- port { +- adv7180_to_ipu1_csi1_mux: endpoint { +- remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>; +- bus-width = <8>; +- }; +- }; +- }; +-}; +- +-&ipu1_csi1_from_ipu1_csi1_mux { +- bus-width = <8>; +-}; +- +-&ipu1_csi1_mux_from_parallel_sensor { +- remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; +- bus-width = <8>; +-}; +- +-&ipu1_csi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_csi1>; +-}; +- +-&iomuxc { +- pinctrl_adv7180: adv7180grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 +- >; +- }; +- +- pinctrl_ipu1_csi1: ipu1_csi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0 +- MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0 +- MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0 +- MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0 +- MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0 +- MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0 +- MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0 +- MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0 +- MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0 +- MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0 +- MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-gw53xx.dts b/scripts/dtc/include-prefixes/arm/imx6dl-gw53xx.dts +deleted file mode 100644 +index 182e8194c249..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-gw53xx.dts ++++ /dev/null +@@ -1,71 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Gateworks Corporation +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-gw53xx.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 DualLite/Solo GW53XX"; +- compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl"; +-}; +- +-&i2c3 { +- adv7180: camera@20 { +- compatible = "adi,adv7180"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adv7180>; +- reg = <0x20>; +- powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; +- interrupt-parent = <&gpio3>; +- interrupts = <30 IRQ_TYPE_LEVEL_LOW>; +- +- port { +- adv7180_to_ipu1_csi1_mux: endpoint { +- remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>; +- bus-width = <8>; +- }; +- }; +- }; +-}; +- +-&ipu1_csi1_from_ipu1_csi1_mux { +- bus-width = <8>; +-}; +- +-&ipu1_csi1_mux_from_parallel_sensor { +- remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; +- bus-width = <8>; +-}; +- +-&ipu1_csi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_csi1>; +-}; +- +-&iomuxc { +- pinctrl_adv7180: adv7180grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 +- >; +- }; +- +- pinctrl_ipu1_csi1: ipu1_csi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0 +- MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0 +- MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0 +- MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0 +- MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0 +- MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0 +- MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0 +- MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0 +- MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0 +- MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0 +- MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-gw54xx.dts b/scripts/dtc/include-prefixes/arm/imx6dl-gw54xx.dts +deleted file mode 100644 +index a106c4e3e329..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-gw54xx.dts ++++ /dev/null +@@ -1,71 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Gateworks Corporation +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-gw54xx.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 DualLite/Solo GW54XX"; +- compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl"; +-}; +- +-&i2c3 { +- adv7180: camera@20 { +- compatible = "adi,adv7180"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adv7180>; +- reg = <0x20>; +- powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; +- interrupt-parent = <&gpio3>; +- interrupts = <30 IRQ_TYPE_LEVEL_LOW>; +- +- port { +- adv7180_to_ipu1_csi1_mux: endpoint { +- remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>; +- bus-width = <8>; +- }; +- }; +- }; +-}; +- +-&ipu1_csi1_from_ipu1_csi1_mux { +- bus-width = <8>; +-}; +- +-&ipu1_csi1_mux_from_parallel_sensor { +- remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; +- bus-width = <8>; +-}; +- +-&ipu1_csi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_csi1>; +-}; +- +-&iomuxc { +- pinctrl_adv7180: adv7180grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 +- >; +- }; +- +- pinctrl_ipu1_csi1: ipu1_csi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0 +- MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0 +- MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0 +- MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0 +- MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0 +- MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0 +- MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0 +- MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0 +- MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0 +- MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0 +- MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-gw551x.dts b/scripts/dtc/include-prefixes/arm/imx6dl-gw551x.dts +deleted file mode 100644 +index 82d5f85722ea..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-gw551x.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-/* +- * Copyright 2014 Gateworks Corporation +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-gw551x.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 DualLite/Solo GW551X"; +- compatible = "gw,imx6dl-gw551x", "gw,ventana", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-gw552x.dts b/scripts/dtc/include-prefixes/arm/imx6dl-gw552x.dts +deleted file mode 100644 +index 4864a36f9b36..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-gw552x.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2014 Gateworks Corporation +- */ +- +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-gw552x.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 DualLite/Solo GW552X"; +- compatible = "gw,imx6dl-gw552x", "gw,ventana", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-gw553x.dts b/scripts/dtc/include-prefixes/arm/imx6dl-gw553x.dts +deleted file mode 100644 +index 59b8afc36e66..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-gw553x.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-/* +- * Copyright 2016 Gateworks Corporation +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-gw553x.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 DualLite/Solo GW553X"; +- compatible = "gw,imx6dl-gw553x", "gw,ventana", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-gw560x.dts b/scripts/dtc/include-prefixes/arm/imx6dl-gw560x.dts +deleted file mode 100644 +index 21bdfaf8df53..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-gw560x.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-/* +- * Copyright 2017 Gateworks Corporation +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-gw560x.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 DualLite/Solo GW560X"; +- compatible = "gw,imx6dl-gw560x", "gw,ventana", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-gw5903.dts b/scripts/dtc/include-prefixes/arm/imx6dl-gw5903.dts +deleted file mode 100644 +index 103261ea9334..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-gw5903.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-/* +- * Copyright 2017 Gateworks Corporation +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-gw5903.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 Duallite/Solo GW5903"; +- compatible = "gw,imx6dl-gw5903", "gw,ventana", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-gw5904.dts b/scripts/dtc/include-prefixes/arm/imx6dl-gw5904.dts +deleted file mode 100644 +index 9c6d3cd3d6a7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-gw5904.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-/* +- * Copyright 2017 Gateworks Corporation +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-gw5904.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 DualLite/Solo GW5904"; +- compatible = "gw,imx6dl-gw5904", "gw,ventana", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-gw5907.dts b/scripts/dtc/include-prefixes/arm/imx6dl-gw5907.dts +deleted file mode 100644 +index 3fa2822beffc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-gw5907.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2019 Gateworks Corporation +- */ +- +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-gw5907.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 DualLite/Solo GW5907"; +- compatible = "gw,imx6dl-gw5907", "gw,ventana", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-gw5910.dts b/scripts/dtc/include-prefixes/arm/imx6dl-gw5910.dts +deleted file mode 100644 +index 0d5e7e5da536..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-gw5910.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2019 Gateworks Corporation +- */ +- +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-gw5910.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 DualLite/Solo GW5910"; +- compatible = "gw,imx6dl-gw5910", "gw,ventana", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-gw5912.dts b/scripts/dtc/include-prefixes/arm/imx6dl-gw5912.dts +deleted file mode 100644 +index 5260e0142d63..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-gw5912.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2019 Gateworks Corporation +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-gw5912.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 DualLite/Solo GW5912"; +- compatible = "gw,imx6dl-gw5912", "gw,ventana", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-gw5913.dts b/scripts/dtc/include-prefixes/arm/imx6dl-gw5913.dts +deleted file mode 100644 +index b74e533c8e67..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-gw5913.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2019 Gateworks Corporation +- */ +- +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-gw5913.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 DualLite/Solo GW5913"; +- compatible = "gw,imx6dl-gw5913", "gw,ventana", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-hummingboard-emmc-som-v15.dts b/scripts/dtc/include-prefixes/arm/imx6dl-hummingboard-emmc-som-v15.dts +deleted file mode 100644 +index a63f742f20d9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-hummingboard-emmc-som-v15.dts ++++ /dev/null +@@ -1,53 +0,0 @@ +-/* +- * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) +- * Based on dt work by Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-ti.dtsi" +-#include "imx6qdl-sr-som-emmc.dtsi" +-#include "imx6qdl-hummingboard.dtsi" +- +-/ { +- model = "SolidRun HummingBoard Solo/DualLite (1.5som+emmc)"; +- compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-hummingboard-som-v15.dts b/scripts/dtc/include-prefixes/arm/imx6dl-hummingboard-som-v15.dts +deleted file mode 100644 +index 66a06cf3cdf3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-hummingboard-som-v15.dts ++++ /dev/null +@@ -1,52 +0,0 @@ +-/* +- * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) +- * Based on dt work by Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-ti.dtsi" +-#include "imx6qdl-hummingboard.dtsi" +- +-/ { +- model = "SolidRun HummingBoard Solo/DualLite (1.5som)"; +- compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-hummingboard.dts b/scripts/dtc/include-prefixes/arm/imx6dl-hummingboard.dts +deleted file mode 100644 +index cbd02eb486e1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-hummingboard.dts ++++ /dev/null +@@ -1,52 +0,0 @@ +-/* +- * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) +- * Based on dt work by Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-brcm.dtsi" +-#include "imx6qdl-hummingboard.dtsi" +- +-/ { +- model = "SolidRun HummingBoard Solo/DualLite"; +- compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-hummingboard2-emmc-som-v15.dts b/scripts/dtc/include-prefixes/arm/imx6dl-hummingboard2-emmc-som-v15.dts +deleted file mode 100644 +index 80313c13bcdb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-hummingboard2-emmc-som-v15.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-/* +- * Device Tree file for SolidRun HummingBoard2 +- * Copyright (C) 2015 Rabeeh Khoury +- * Based on work by Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License. +- * +- * This file is distributed in the hope that it will be useful +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-emmc.dtsi" +-#include "imx6qdl-sr-som-ti.dtsi" +-#include "imx6qdl-hummingboard2.dtsi" +- +-/ { +- model = "SolidRun HummingBoard2 Solo/DualLite (1.5som+emmc)"; +- compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-hummingboard2-som-v15.dts b/scripts/dtc/include-prefixes/arm/imx6dl-hummingboard2-som-v15.dts +deleted file mode 100644 +index e61ef1156f8b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-hummingboard2-som-v15.dts ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* +- * Device Tree file for SolidRun HummingBoard2 +- * Copyright (C) 2015 Rabeeh Khoury +- * Based on work by Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License. +- * +- * This file is distributed in the hope that it will be useful +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-ti.dtsi" +-#include "imx6qdl-hummingboard2.dtsi" +- +-/ { +- model = "SolidRun HummingBoard2 Solo/DualLite (1.5som)"; +- compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-hummingboard2.dts b/scripts/dtc/include-prefixes/arm/imx6dl-hummingboard2.dts +deleted file mode 100644 +index b12cd87f3f94..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-hummingboard2.dts ++++ /dev/null +@@ -1,53 +0,0 @@ +-/* +- * Copyright (C) 2015 Rabeeh Khoury +- * Based on dt work by Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-brcm.dtsi" +-#include "imx6qdl-hummingboard2.dtsi" +-#include "imx6qdl-hummingboard2-emmc.dtsi" +- +-/ { +- model = "SolidRun HummingBoard2 Solo/DualLite"; +- compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-icore-mipi.dts b/scripts/dtc/include-prefixes/arm/imx6dl-icore-mipi.dts +deleted file mode 100644 +index d8f3821a0ffd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-icore-mipi.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright (C) 2018 Engicam S.r.l. +- * Copyright (C) 2018 Amarula Solutions B.V. +- * Author: Jagan Teki +- */ +- +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-icore-1.5.dtsi" +- +-/ { +- model = "Engicam i.CoreM6 DualLite/Solo MIPI Starter Kit"; +- compatible = "engicam,imx6-icore", "fsl,imx6dl"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&usdhc3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-icore-rqs.dts b/scripts/dtc/include-prefixes/arm/imx6dl-icore-rqs.dts +deleted file mode 100644 +index 73d710d34b9d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-icore-rqs.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright (C) 2016 Amarula Solutions B.V. +- * Copyright (C) 2016 Engicam S.r.l. +- */ +- +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-icore-rqs.dtsi" +- +-/ { +- model = "Engicam i.CoreM6 DualLite/Solo RQS Starter Kit"; +- compatible = "engicam,imx6-icore-rqs", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-icore.dts b/scripts/dtc/include-prefixes/arm/imx6dl-icore.dts +deleted file mode 100644 +index 80fa60607ab1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-icore.dts ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright (C) 2016 Amarula Solutions B.V. +- * Copyright (C) 2016 Engicam S.r.l. +- */ +- +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-icore.dtsi" +- +-/ { +- model = "Engicam i.CoreM6 DualLite/Solo Starter Kit"; +- compatible = "engicam,imx6-icore", "fsl,imx6dl"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&can2 { +- status = "okay"; +-}; +- +-&i2c1 { +- max11801: touchscreen@48 { +- compatible = "maxim,max11801"; +- reg = <0x48>; +- interrupt-parent = <&gpio3>; +- interrupts = <31 IRQ_TYPE_EDGE_FALLING>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-kontron-samx6i.dtsi b/scripts/dtc/include-prefixes/arm/imx6dl-kontron-samx6i.dtsi +deleted file mode 100644 +index a864fdbd5f16..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-kontron-samx6i.dtsi ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright 2019 (C) Pengutronix, Marco Felsch +- */ +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-kontron-samx6i.dtsi" +- +-/ { +- model = "Kontron SMARC sAMX6i Dual-Lite/Solo"; +- compatible = "kontron,imx6dl-samx6i", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-lanmcu.dts b/scripts/dtc/include-prefixes/arm/imx6dl-lanmcu.dts +deleted file mode 100644 +index 6b6e6fcdea9c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-lanmcu.dts ++++ /dev/null +@@ -1,470 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (c) 2019 Protonic Holland +- * Copyright (c) 2020 Oleksij Rempel , Pengutronix +- */ +- +-/dts-v1/; +-#include +-#include +-#include "imx6dl.dtsi" +- +-/ { +- model = "Van der Laan LANMCU"; +- compatible = "vdl,lanmcu", "fsl,imx6dl"; +- +- chosen { +- stdout-path = &uart4; +- }; +- +- clock_ksz8081: clock-ksz8081 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 5000000 0>; +- brightness-levels = <0 1000>; +- num-interpolated-steps = <20>; +- default-brightness-level = <19>; +- }; +- +- display { +- compatible = "fsl,imx-parallel-display"; +- pinctrl-0 = <&pinctrl_ipu1_disp>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- display_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds>; +- +- led-0 { +- label = "debug0"; +- function = LED_FUNCTION_STATUS; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- panel { +- compatible = "edt,etm0700g0bdh6"; +- backlight = <&backlight>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +- +- reg_otg_vbus: regulator-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "otg-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wifi_npd>; +- reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; +- }; +- +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can2>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rmii"; +- clocks = <&clks IMX6QDL_CLK_ENET>, +- <&clks IMX6QDL_CLK_ENET>, +- <&clock_ksz8081>; +- clock-names = "ipg", "ahb", "ptp"; +- phy-handle = <&rgmii_phy>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Microchip KSZ8081RNA PHY */ +- rgmii_phy: ethernet-phy@0 { +- reg = <0>; +- interrupts-extended = <&gpio5 23 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- reset-deassert-us = <300>; +- }; +- }; +-}; +- +-&gpio1 { +- gpio-line-names = +- "", "SD1_CD", "", "", "", "", "", "", +- "DEBUG_0", "BL_PWM", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "ENET_LED_GREEN", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio3 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "TS_INT", "USB_OTG1_OC", "USB_OTG1_PWR", "", +- "", "", "", "", "UART2_CTS", "", "UART3_CTS", ""; +-}; +- +-&gpio5 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "ENET_RST", "ENET_INT", +- "", "", "I2C1_SDA", "I2C1_SCL", "", "", "", ""; +-}; +- +-&gpio6 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "WLAN_REG_ON", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio7 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "EMMC_RST", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- /* additional i2c devices are added automatically by the boot loader */ +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- touchscreen@38 { +- compatible = "edt,edt-ft5406"; +- reg = <0x38>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ts_edt>; +- interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; +- +- touchscreen-size-x = <1792>; +- touchscreen-size-y = <1024>; +- +- touchscreen-fuzz-x = <0>; +- touchscreen-fuzz-y = <0>; +- +- /* Touch screen calibration */ +- threshold = <50>; +- gain = <5>; +- offset = <10>; +- }; +- +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&display_in>; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- linux,rs485-enabled-at-boot-time; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- linux,rs485-enabled-at-boot-time; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- phy_type = "utmi"; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- disable-wp; +- cap-sd-highspeed; +- no-mmc; +- no-sdio; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- no-1-8-v; +- non-removable; +- mmc-pwrseq = <&usdhc2_wifi_pwrseq>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- no-sd; +- no-sdio; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 +- >; +- }; +- +- pinctrl_can2: can2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- /* MX6QDL_ENET_PINGRP4 */ +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 +- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 +- +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 +- /* Phy reset */ +- MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 +- /* nINTRP */ +- MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_ipu1_disp: ipudisp1grp { +- fsl,pins = < +- /* DSE 0x30 => 25 Ohm, 0x20 => 37 Ohm, 0x10 => 75 Ohm */ +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x30 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x30 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x30 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x30 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x30 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x30 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x30 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x30 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x30 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x30 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x30 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x30 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x30 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x30 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x30 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x30 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x30 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x30 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x30 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x30 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x30 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x30 +- >; +- }; +- +- pinctrl_leds: ledsgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 +- >; +- }; +- +- pinctrl_ts_edt: ts1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x130b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x130b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 +- /* power enable, high active */ +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 +- MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 +- >; +- }; +- +- pinctrl_wifi_npd: wifigrp { +- fsl,pins = < +- /* WL_REG_ON */ +- MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-mamoj.dts b/scripts/dtc/include-prefixes/arm/imx6dl-mamoj.dts +deleted file mode 100644 +index 028951955bde..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-mamoj.dts ++++ /dev/null +@@ -1,496 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2018 BTicino +- * Copyright (C) 2018 Amarula Solutions B.V. +- */ +- +-/dts-v1/; +- +-#include +-#include "imx6dl.dtsi" +- +-/ { +- model = "BTicino i.MX6DL Mamoj board"; +- compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl"; +- +- /* Will be filled by the bootloader */ +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0>; +- }; +- +- backlight_lcd: backlight-lcd { +- compatible = "pwm-backlight"; +- pwms = <&pwm3 0 25000>; /* 25000ns -> 40kHz */ +- brightness-levels = <0 4 8 16 32 64 128 160 192 224 255>; +- default-brightness-level = <7>; +- }; +- +- display: disp0 { +- compatible = "fsl,imx-parallel-display"; +- #address-cells = <1>; +- #size-cells = <0>; +- interface-pix-fmt = "rgb24"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_lcdif>; +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- lcd_display_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lcd_display_out: endpoint { +- remote-endpoint = <&lcd_panel_in>; +- }; +- }; +- }; +- +- panel-lcd { +- compatible = "rocktech,rk070er9427"; +- backlight = <&backlight_lcd>; +- power-supply = <®_lcd_lr>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_lcdif_pwr>; +- +- port { +- lcd_panel_in: endpoint { +- remote-endpoint = <&lcd_display_out>; +- }; +- }; +- }; +- +- reg_lcd_3v3: regulator-lcd-dvdd { +- compatible = "regulator-fixed"; +- regulator-name = "lcd-dvdd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 1 0>; +- enable-active-high; +- startup-delay-us = <21000>; +- }; +- +- reg_lcd_power: regulator-lcd-power { +- compatible = "regulator-fixed"; +- regulator-name = "lcd-enable"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 6 0>; +- enable-active-high; +- vin-supply = <®_lcd_3v3>; +- }; +- +- reg_lcd_vgl: regulator-lcd-vgl { +- compatible = "regulator-fixed"; +- regulator-name = "lcd-vgl"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <6000>; +- enable-active-high; +- vin-supply = <®_lcd_power>; +- }; +- +- reg_lcd_vgh: regulator-lcd-vgh { +- compatible = "regulator-fixed"; +- regulator-name = "lcd-vgh"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <6000>; +- enable-active-high; +- vin-supply = <®_lcd_avdd>; +- }; +- +- reg_lcd_vcom: regulator-lcd-vcom { +- compatible = "regulator-fixed"; +- regulator-name = "lcd-vcom"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <11000>; +- enable-active-high; +- vin-supply = <®_lcd_vgh>; +- }; +- +- reg_lcd_lr: regulator-lcd-lr { +- compatible = "regulator-fixed"; +- regulator-name = "lcd-lr"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_lcd_vcom>; +- }; +- +- reg_lcd_avdd: regulator-lcd-avdd { +- compatible = "regulator-fixed"; +- regulator-name = "lcd-avdd"; +- regulator-min-microvolt = <10280000>; +- regulator-max-microvolt = <10280000>; +- gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <6000>; +- enable-active-high; +- vin-supply = <®_lcd_vgl>; +- }; +- +- reg_usb_host: regulator-usb-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usbhost-vbus"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbhost>; +- regulator-min-microvolt = <50000000>; +- regulator-max-microvolt = <50000000>; +- gpio = <&gpio6 6 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_wl18xx_vmmc: regulator-wl18xx-vmcc { +- compatible = "regulator-fixed"; +- regulator-name = "vwl1807"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wlan>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <70000>; +- enable-active-high; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "mii"; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&i2c4 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +- +- pfuze100: pmic@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- /* CPU vdd_arm core */ +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- /* SOC vdd_soc */ +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- /* I/O power GEN_3V3 */ +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* DDR memory */ +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* DDR memory */ +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* not used */ +- sw4_reg: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- /* not used */ +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- /* PMIC vsnvs. EX boot mode */ +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* not used */ +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- /* not used */ +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- /* not used */ +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- /* 1v8 general power */ +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- /* 2v8 general power IMX6 */ +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- /* 3v3 Ethernet */ +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&lcd_display_in>; +-}; +- +-&pwm3 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_host>; +- status = "okay"; +-}; +- +-&usbotg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- bus-width = <4>; +- vmmc-supply = <®_wl18xx_vmmc>; +- no-1-8-v; +- non-removable; +- wakeup-source; +- keep-power-in-suspend; +- cap-power-off-card; +- max-frequency = <25000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- wlcore: wlcore@2 { +- compatible = "ti,wl1837"; +- reg = <2>; +- interrupt-parent = <&gpio6>; +- interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; +- tcxo-clock-frequency = <26000000>; +- }; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <8>; +- non-removable; +- keep-power-in-suspend; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b1 +- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 +- MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x1b0b0 +- MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1b0b0 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 +- MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x1b0b0 +- MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x1b0b1 +- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 +- MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x1b0b0 +- MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1b0b0 +- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 +- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 +- MX6QDL_PAD_KEY_COL3__ENET_CRS 0x1b0b0 +- MX6QDL_PAD_KEY_ROW1__ENET_COL 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_ipu1_lcdif: pinctrlipu1lcdif { /* parallel port 24-bit */ +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* VDOUT_PCLK */ +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* VDOUT_HSYNC */ +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VDOUT_VSYNC */ +- MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* VDOUT_RESET */ +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 +- >; +- }; +- +- pinctrl_ipu1_lcdif_pwr: ipu1lcdifpwrgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x40013058 /* EN_LCD33V */ +- MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x4001b0b0 /* EN_AVDD */ +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x40013058 /* ENVGH */ +- MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x40013058 /* ENVGL */ +- MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x40013058 /* LCD_POWER */ +- MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x40013058 /* EN_VCOM_LCD */ +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x40013058 /* LCD_L_R */ +- MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x40013058 /* LCD_U_D */ +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbhost: usbhostgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17069 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10079 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17069 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17069 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17069 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17069 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- >; +- }; +- +- pinctrl_wlan: wlangrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x4001b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-nit6xlite.dts b/scripts/dtc/include-prefixes/arm/imx6dl-nit6xlite.dts +deleted file mode 100644 +index 61fa30991d67..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-nit6xlite.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright 2015 Boundary Devices, Inc. +- */ +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-nit6xlite.dtsi" +- +-/ { +- model = "Boundary Devices i.MX6 Solo Nitrogen6_Lite Board"; +- compatible = "boundary,imx6dl-nit6xlite", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-nitrogen6x.dts b/scripts/dtc/include-prefixes/arm/imx6dl-nitrogen6x.dts +deleted file mode 100644 +index ef58d3b0ea0d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-nitrogen6x.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright 2013 Boundary Devices, Inc. +- * Copyright 2012 Freescale Semiconductor, Inc. +- * Copyright 2011 Linaro Ltd. +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-nitrogen6x.dtsi" +- +-/ { +- model = "Boundary Devices i.MX6 DualLite Nitrogen6x Board"; +- compatible = "boundary,imx6dl-nitrogen6x", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-phytec-mira-rdk-nand.dts b/scripts/dtc/include-prefixes/arm/imx6dl-phytec-mira-rdk-nand.dts +deleted file mode 100644 +index 9f7f9f98139d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-phytec-mira-rdk-nand.dts ++++ /dev/null +@@ -1,64 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2018 PHYTEC Messtechnik GmbH +- * Author: Christian Hemp +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-phytec-phycore-som.dtsi" +-#include "imx6qdl-phytec-mira.dtsi" +- +-/ { +- model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND"; +- compatible = "phytec,imx6dl-pbac06-nand", "phytec,imx6dl-pbac06", +- "phytec,imx6qdl-pcm058", "fsl,imx6dl"; +- +- chosen { +- stdout-path = &uart2; +- }; +-}; +- +-ðphy { +- max-speed = <100>; +-}; +- +-&fec { +- status = "okay"; +-}; +- +-&gpmi { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c_rtc { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbotg { +- status = "okay"; +-}; +- +-&usdhc1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-phytec-pbab01.dts b/scripts/dtc/include-prefixes/arm/imx6dl-phytec-pbab01.dts +deleted file mode 100644 +index 0a07cc6f815e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-phytec-pbab01.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH +- */ +- +-/dts-v1/; +-#include "imx6dl-phytec-pfla02.dtsi" +-#include "imx6qdl-phytec-pbab01.dtsi" +- +-/ { +- model = "Phytec phyFLEX-i.MX6 DualLite/Solo Carrier-Board"; +- compatible = "phytec,imx6dl-pbab01", "phytec,imx6dl-pfla02", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-phytec-pfla02.dtsi b/scripts/dtc/include-prefixes/arm/imx6dl-phytec-pfla02.dtsi +deleted file mode 100644 +index 6f8aaf524425..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-phytec-pfla02.dtsi ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH +- */ +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-phytec-pfla02.dtsi" +- +-/ { +- model = "Phytec phyFLEX-i.MX6 DualLite/Solo"; +- compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-pico-dwarf.dts b/scripts/dtc/include-prefixes/arm/imx6dl-pico-dwarf.dts +deleted file mode 100644 +index d85b15a8c127..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-pico-dwarf.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-// +-// Copyright 2018 Technexion Ltd. +-// +-// Author: Wig Cheng +-// Richard Hu +-// Tapani Utriainen +- +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-pico-pi.dtsi" +- +-/ { +- model = "TechNexion PICO-IMX6 DualLite/Solo Board and Dwarf baseboard"; +- compatible = "technexion,imx6dl-pico-dwarf", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-pico-hobbit.dts b/scripts/dtc/include-prefixes/arm/imx6dl-pico-hobbit.dts +deleted file mode 100644 +index 08fedcbcc91b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-pico-hobbit.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-// +-// Copyright 2018 Technexion Ltd. +-// +-// Author: Wig Cheng +-// Richard Hu +-// Tapani Utriainen +- +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-pico-hobbit.dtsi" +- +-/ { +- model = "TechNexion PICO-IMX6 DualLite/Solo Board and Hobbit baseboard"; +- compatible = "technexion,imx6dl-pico-hobbit", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-pico-nymph.dts b/scripts/dtc/include-prefixes/arm/imx6dl-pico-nymph.dts +deleted file mode 100644 +index 32ccfc5d41ce..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-pico-nymph.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-// +-// Copyright 2018 Technexion Ltd. +-// +-// Author: Wig Cheng +-// Richard Hu +-// Tapani Utriainen +- +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-pico-pi.dtsi" +- +-/ { +- model = "TechNexion PICO-IMX6 DualLite/Solo Board and Nymph baseboard"; +- compatible = "technexion,imx6dl-pico-nymph", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-pico-pi.dts b/scripts/dtc/include-prefixes/arm/imx6dl-pico-pi.dts +deleted file mode 100644 +index 4590e8ad9a91..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-pico-pi.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-// +-// Copyright 2018 Technexion Ltd. +-// +-// Author: Wig Cheng +-// Richard Hu +-// Tapani Utriainen +- +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-pico-pi.dtsi" +- +-/ { +- model = "TechNexion PICO-IMX6 DualLite/Solo Board and PI baseboard"; +- compatible = "technexion,imx6dl-pico-pi", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-pinfunc.h b/scripts/dtc/include-prefixes/arm/imx6dl-pinfunc.h +deleted file mode 100644 +index 9d88d09f9bf6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-pinfunc.h ++++ /dev/null +@@ -1,1088 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __DTS_IMX6DL_PINFUNC_H +-#define __DTS_IMX6DL_PINFUNC_H +- +-/* +- * The pin function ID is a tuple of +- * +- */ +-#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0 +-#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0 +-#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1 +-#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1 +-#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1 +-#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1 +-#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1 +-#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0 +-#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0 +-#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0 +-#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0 +-#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0 +-#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0 +-#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0 +-#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0 +-#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0 +-#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0 +-#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x398 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x088 0x39c 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x088 0x39c 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0 +-#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x088 0x39c 0x8d4 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x088 0x39c 0x868 0x4 0x0 +-#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x088 0x39c 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x088 0x39c 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x08c 0x3a0 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x08c 0x3a0 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x08c 0x3a0 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x08c 0x3a0 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x090 0x3a4 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x090 0x3a4 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x090 0x3a4 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x090 0x3a4 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x094 0x3a8 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x094 0x3a8 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x094 0x3a8 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x098 0x3ac 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x098 0x3ac 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x098 0x3ac 0x000 0x7 0x0 +-#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x09c 0x3b0 0x000 0x0 0x0 +-#define MX6QDL_PAD_DI0_DISP_CLK__LCD_CLK 0x09c 0x3b0 0x000 0x1 0x0 +-#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x09c 0x3b0 0x000 0x5 0x0 +-#define MX6QDL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0x09c 0x3b0 0x000 0x8 0x0 +-#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x0a0 0x3b4 0x000 0x0 0x0 +-#define MX6QDL_PAD_DI0_PIN15__LCD_ENABLE 0x0a0 0x3b4 0x000 0x1 0x0 +-#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0 +-#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x0a0 0x3b4 0x000 0x5 0x0 +-#define MX6QDL_PAD_DI0_PIN15__LCD_RD_E 0x0a0 0x3b4 0x000 0x8 0x0 +-#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x0a4 0x3b8 0x000 0x0 0x0 +-#define MX6QDL_PAD_DI0_PIN2__LCD_HSYNC 0x0a4 0x3b8 0x8d8 0x1 0x0 +-#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0 +-#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0a4 0x3b8 0x000 0x5 0x0 +-#define MX6QDL_PAD_DI0_PIN2__LCD_RS 0x0a4 0x3b8 0x000 0x8 0x0 +-#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x0a8 0x3bc 0x000 0x0 0x0 +-#define MX6QDL_PAD_DI0_PIN3__LCD_VSYNC 0x0a8 0x3bc 0x000 0x1 0x0 +-#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0 +-#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0a8 0x3bc 0x000 0x5 0x0 +-#define MX6QDL_PAD_DI0_PIN3__LCD_CS 0x0a8 0x3bc 0x000 0x8 0x0 +-#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x0ac 0x3c0 0x000 0x0 0x0 +-#define MX6QDL_PAD_DI0_PIN4__LCD_BUSY 0x0ac 0x3c0 0x8d8 0x1 0x1 +-#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0 +-#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x0ac 0x3c0 0x92c 0x3 0x0 +-#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0 +-#define MX6QDL_PAD_DI0_PIN4__LCD_RESET 0x0ac 0x3c0 0x000 0x8 0x0 +-#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x0b0 0x3c4 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT0__LCD_DATA00 0x0b0 0x3c4 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0 0x3c4 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x0b4 0x3c8 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT1__LCD_DATA01 0x0b4 0x3c8 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b4 0x3c8 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x0b8 0x3cc 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT10__LCD_DATA10 0x0b8 0x3cc 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b8 0x3cc 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x0bc 0x3d0 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT11__LCD_DATA11 0x0bc 0x3d0 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0bc 0x3d0 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x0c0 0x3d4 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT12__LCD_DATA12 0x0c0 0x3d4 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x0c0 0x3d4 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x0c4 0x3d8 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT13__LCD_DATA13 0x0c4 0x3d8 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x0c4 0x3d8 0x7bc 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x0c4 0x3d8 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x0c8 0x3dc 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT14__LCD_DATA14 0x0c8 0x3dc 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x0c8 0x3dc 0x7b8 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x0c8 0x3dc 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x0cc 0x3e0 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT15__LCD_DATA15 0x0cc 0x3e0 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x0cc 0x3e0 0x804 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x0cc 0x3e0 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x0d0 0x3e4 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT16__LCD_DATA16 0x0d0 0x3e4 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1 +-#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x0d0 0x3e4 0x7c0 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x0d0 0x3e4 0x8e8 0x4 0x0 +-#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x0d0 0x3e4 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x0d4 0x3e8 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT17__LCD_DATA17 0x0d4 0x3e8 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1 +-#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x0d4 0x3e8 0x7b4 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x0d4 0x3e8 0x8ec 0x4 0x0 +-#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0d4 0x3e8 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x0d8 0x3ec 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT18__LCD_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1 +-#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x0d8 0x3ec 0x7c4 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x0d8 0x3ec 0x7a4 0x4 0x0 +-#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0d8 0x3ec 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x0d8 0x3ec 0x000 0x7 0x0 +-#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x0dc 0x3f0 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT19__LCD_DATA19 0x0dc 0x3f0 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1 +-#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x0dc 0x3f0 0x7b0 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x0dc 0x3f0 0x7a0 0x4 0x0 +-#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0dc 0x3f0 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x0dc 0x3f0 0x000 0x7 0x0 +-#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x0e0 0x3f4 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT2__LCD_DATA02 0x0e0 0x3f4 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x0e0 0x3f4 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x0e4 0x3f8 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT20__LCD_DATA20 0x0e4 0x3f8 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1 +-#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x0e4 0x3f8 0x7a8 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x0e4 0x3f8 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x0e8 0x3fc 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT21__LCD_DATA21 0x0e8 0x3fc 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1 +-#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x0e8 0x3fc 0x79c 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0e8 0x3fc 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x0ec 0x400 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT22__LCD_DATA22 0x0ec 0x400 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1 +-#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x0ec 0x400 0x7ac 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0ec 0x400 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x0f0 0x404 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT23__LCD_DATA23 0x0f0 0x404 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1 +-#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x0f0 0x404 0x798 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0f0 0x404 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x0f4 0x408 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT3__LCD_DATA03 0x0f4 0x408 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x0f4 0x408 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x0f8 0x40c 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT4__LCD_DATA04 0x0f8 0x40c 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x0f8 0x40c 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x0fc 0x410 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT5__LCD_DATA05 0x0fc 0x410 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x0fc 0x410 0x000 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x0fc 0x410 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100 0x414 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT6__LCD_DATA06 0x100 0x414 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x100 0x414 0x000 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x100 0x414 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x104 0x418 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT7__LCD_DATA07 0x104 0x418 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x104 0x418 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x108 0x41c 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT8__LCD_DATA08 0x108 0x41c 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x108 0x41c 0x000 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x108 0x41c 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10c 0x420 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT9__LCD_DATA09 0x10c 0x420 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x10c 0x420 0x000 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x10c 0x420 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x110 0x4e0 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x110 0x4e0 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0 +-#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x110 0x4e0 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x110 0x4e0 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x110 0x4e0 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x114 0x4e4 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x114 0x4e4 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0 +-#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x114 0x4e4 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x114 0x4e4 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_A17__EPDC_PWR_STAT 0x114 0x4e4 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x118 0x4e8 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x118 0x4e8 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0 +-#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x118 0x4e8 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x118 0x4e8 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_A18__EPDC_PWR_CTRL0 0x118 0x4e8 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x11c 0x4ec 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x11c 0x4ec 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0 +-#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x11c 0x4ec 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x11c 0x4ec 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_A19__EPDC_PWR_CTRL1 0x11c 0x4ec 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x120 0x4f0 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x120 0x4f0 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0 +-#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x120 0x4f0 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x120 0x4f0 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_A20__EPDC_PWR_CTRL2 0x120 0x4f0 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x124 0x4f4 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x124 0x4f4 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0 +-#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x124 0x4f4 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x124 0x4f4 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x124 0x4f4 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0 +-#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x12c 0x4fc 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x12c 0x4fc 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0 +-#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x12c 0x4fc 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x12c 0x4fc 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x12c 0x4fc 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x12c 0x4fc 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x130 0x500 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x130 0x500 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0 +-#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x130 0x500 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x130 0x500 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x130 0x500 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x130 0x500 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x134 0x504 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x134 0x504 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x134 0x504 0x000 0x3 0x0 +-#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x134 0x504 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x134 0x504 0x85c 0x6 0x0 +-#define MX6QDL_PAD_EIM_A25__EPDC_DATA15 0x134 0x504 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_A25__EIM_ACLK_FREERUN 0x134 0x504 0x000 0x9 0x0 +-#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x138 0x508 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x138 0x508 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x138 0x508 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_BCLK__EPDC_SDCE9 0x138 0x508 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x13c 0x50c 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x13c 0x50c 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2 +-#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x13c 0x50c 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x13c 0x50c 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x140 0x510 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x140 0x510 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2 +-#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x140 0x510 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_CS1__EPDC_DATA08 0x140 0x510 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x144 0x514 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2 +-#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x144 0x514 0x8a8 0x3 0x1 +-#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x144 0x514 0x864 0x4 0x0 +-#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x144 0x514 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x144 0x514 0x874 0x6 0x0 +-#define MX6QDL_PAD_EIM_D16__EPDC_DATA10 0x144 0x514 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x148 0x518 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2 +-#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x148 0x518 0x8b8 0x3 0x1 +-#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x148 0x518 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x148 0x518 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x148 0x518 0x878 0x6 0x0 +-#define MX6QDL_PAD_EIM_D17__EPDC_VCOM0 0x148 0x518 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x14c 0x51c 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2 +-#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x14c 0x51c 0x8a4 0x3 0x1 +-#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x14c 0x51c 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x14c 0x51c 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x14c 0x51c 0x87c 0x6 0x0 +-#define MX6QDL_PAD_EIM_D18__EPDC_VCOM1 0x14c 0x51c 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x150 0x520 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x150 0x520 0x7e8 0x1 0x1 +-#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x150 0x520 0x8a0 0x3 0x1 +-#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x150 0x520 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x150 0x520 0x8f8 0x4 0x0 +-#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x150 0x520 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x150 0x520 0x000 0x6 0x0 +-#define MX6QDL_PAD_EIM_D19__EPDC_DATA12 0x150 0x520 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x154 0x524 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x154 0x524 0x808 0x1 0x0 +-#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x154 0x524 0x89c 0x3 0x1 +-#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x154 0x524 0x8f8 0x4 0x1 +-#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x154 0x524 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x154 0x524 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x154 0x524 0x000 0x6 0x0 +-#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x158 0x528 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x158 0x528 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D21__IPU1_CSI1_DATA11 0x158 0x528 0x88c 0x3 0x0 +-#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x158 0x528 0x920 0x4 0x0 +-#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x158 0x528 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x158 0x528 0x868 0x6 0x1 +-#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x158 0x528 0x8f0 0x7 0x0 +-#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x15c 0x52c 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x15c 0x52c 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D22__IPU1_CSI1_DATA10 0x15c 0x52c 0x888 0x3 0x0 +-#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x15c 0x52c 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x15c 0x52c 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x15c 0x52c 0x000 0x6 0x0 +-#define MX6QDL_PAD_EIM_D22__EPDC_SDCE6 0x15c 0x52c 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x160 0x530 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x160 0x530 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0 +-#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x160 0x530 0x000 0x3 0x0 +-#define MX6QDL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0x160 0x530 0x8b0 0x4 0x0 +-#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x160 0x530 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x160 0x530 0x000 0x6 0x0 +-#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x160 0x530 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_D23__EPDC_DATA11 0x160 0x530 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x164 0x534 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x164 0x534 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0 +-#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x164 0x534 0x7ec 0x3 0x0 +-#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x164 0x534 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x164 0x534 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x164 0x534 0x7bc 0x6 0x1 +-#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x164 0x534 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_D24__EPDC_SDCE7 0x164 0x534 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1 +-#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0 +-#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1 +-#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x16c 0x53c 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x16c 0x53c 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x16c 0x53c 0x898 0x3 0x1 +-#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x16c 0x53c 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x16c 0x53c 0x904 0x4 0x0 +-#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x16c 0x53c 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x16c 0x53c 0x000 0x6 0x0 +-#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x16c 0x53c 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_D26__EPDC_SDOED 0x16c 0x53c 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x170 0x540 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x170 0x540 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x170 0x540 0x894 0x3 0x1 +-#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x170 0x540 0x904 0x4 0x1 +-#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x170 0x540 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x170 0x540 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x170 0x540 0x000 0x6 0x0 +-#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x170 0x540 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x170 0x540 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1 +-#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1 +-#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0 +-#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x174 0x544 0x900 0x4 0x0 +-#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x174 0x544 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x0 +-#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x174 0x544 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_D28__EPDC_PWR_CTRL3 0x174 0x544 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1 +-#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1 +-#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x178 0x548 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x178 0x548 0x900 0x4 0x1 +-#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0 +-#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_D29__EPDC_PWR_WAKE 0x178 0x548 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x17c 0x54c 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x17c 0x54c 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x17c 0x54c 0x000 0x3 0x0 +-#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x17c 0x54c 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x17c 0x54c 0x908 0x4 0x1 +-#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x17c 0x54c 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x17c 0x54c 0x924 0x6 0x0 +-#define MX6QDL_PAD_EIM_D30__EPDC_SDOEZ 0x17c 0x54c 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x180 0x550 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x180 0x550 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x180 0x550 0x000 0x3 0x0 +-#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2 +-#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x180 0x550 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x180 0x550 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x180 0x550 0x000 0x6 0x0 +-#define MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x180 0x550 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_D31__EIM_ACLK_FREERUN 0x180 0x550 0x000 0x9 0x0 +-#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x184 0x554 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x184 0x554 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x184 0x554 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x184 0x554 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA0__EPDC_SDCLK_N 0x184 0x554 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x188 0x558 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x188 0x558 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x188 0x558 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x188 0x558 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x188 0x558 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x18c 0x55c 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x18c 0x55c 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1 +-#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x18c 0x55c 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x18c 0x55c 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x18c 0x55c 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x190 0x560 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x190 0x560 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x190 0x560 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x190 0x560 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x190 0x560 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x194 0x564 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x194 0x564 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1 +-#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x194 0x564 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x194 0x564 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x1a0 0x570 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x1a0 0x570 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1a0 0x570 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x1a0 0x570 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA15__EPDC_DATA09 0x1a0 0x570 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x1a4 0x574 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x1a4 0x574 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1a4 0x574 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x1a4 0x574 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x1a4 0x574 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x1a8 0x578 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x1a8 0x578 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1a8 0x578 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x1a8 0x578 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA3__EPDC_BDR1 0x1a8 0x578 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x1ac 0x57c 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x1ac 0x57c 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1ac 0x57c 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x1ac 0x57c 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x1ac 0x57c 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x1b0 0x580 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x1b0 0x580 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0 0x580 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x1b0 0x580 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x1b0 0x580 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x1b4 0x584 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x1b4 0x584 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b4 0x584 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x1b4 0x584 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x1b4 0x584 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x1b8 0x588 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x1b8 0x588 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b8 0x588 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x1b8 0x588 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA7__EPDC_SDCE3 0x1b8 0x588 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x1bc 0x58c 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x1bc 0x58c 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1bc 0x58c 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x1bc 0x58c 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA8__EPDC_SDCE4 0x1bc 0x58c 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x1c0 0x590 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x1c0 0x590 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1c0 0x590 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x1c0 0x590 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA9__EPDC_SDCE5 0x1c0 0x590 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x1c4 0x594 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x1c4 0x594 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1 +-#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x1c4 0x594 0x7d4 0x4 0x0 +-#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1c4 0x594 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x1c4 0x594 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_EB0__EPDC_PWR_COM 0x1c4 0x594 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x1c8 0x598 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x1c8 0x598 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1 +-#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1c8 0x598 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x1c8 0x598 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2 +-#define MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1 +-#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0 +-#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x1cc 0x59c 0x870 0x6 0x0 +-#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x1cc 0x59c 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x1cc 0x59c 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x1d0 0x5a0 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x1d0 0x5a0 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3 +-#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x1d0 0x5a0 0x000 0x3 0x0 +-#define MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1d0 0x5a0 0x8b4 0x4 0x1 +-#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1d0 0x5a0 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x1d0 0x5a0 0x000 0x6 0x0 +-#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x1d0 0x5a0 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_EB3__EPDC_SDCE0 0x1d0 0x5a0 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0x1d0 0x5a0 0x000 0x9 0x0 +-#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x1d4 0x5a4 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x1d4 0x5a4 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1 +-#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x1d4 0x5a4 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x1d4 0x5a4 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x1d8 0x5a8 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x1d8 0x5a8 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2 +-#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1d8 0x5a8 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_OE__EPDC_PWR_IRQ 0x1d8 0x5a8 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_RW__EIM_RW 0x1dc 0x5ac 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x1dc 0x5ac 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2 +-#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1dc 0x5ac 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x1dc 0x5ac 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x1dc 0x5ac 0x000 0x8 0x0 +-#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x1e0 0x5b0 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x1e0 0x5b0 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1e0 0x5b0 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x1e0 0x5b0 0x000 0x7 0x0 +-#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1e4 0x5b4 0x828 0x1 0x0 +-#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0 +-#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1e4 0x5b4 0x8f4 0x3 0x0 +-#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1e4 0x5b4 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1e8 0x5b8 0x8e0 0x0 0x0 +-#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1e8 0x5b8 0x000 0x1 0x0 +-#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0 +-#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1e8 0x5b8 0x000 0x4 0x0 +-#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1e8 0x5b8 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1ec 0x5bc 0x810 0x1 0x0 +-#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0 +-#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1ec 0x5bc 0x000 0x4 0x0 +-#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1ec 0x5bc 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1ec 0x5bc 0x000 0x6 0x0 +-#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1f0 0x5c0 0x000 0x1 0x0 +-#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0 +-#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1f0 0x5c0 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1f0 0x5c0 0x000 0x6 0x0 +-#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f4 0x5c4 0x790 0x0 0x0 +-#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1f4 0x5c4 0x000 0x1 0x0 +-#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0 +-#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1 +-#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0 +-#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x1f8 0x5c8 0x000 0x0 0x0 +-#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0 +-#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0 +-#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0 +-#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1f8 0x5c8 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1fc 0x5cc 0x8e4 0x0 0x0 +-#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1fc 0x5cc 0x81c 0x1 0x0 +-#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0 +-#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1fc 0x5cc 0x000 0x4 0x0 +-#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1fc 0x5cc 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x200 0x5d0 0x000 0x1 0x0 +-#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0 +-#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x200 0x5d0 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_TX_EN__I2C4_SCL 0x200 0x5d0 0x880 0x9 0x0 +-#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x204 0x5d4 0x000 0x1 0x0 +-#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0 +-#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x204 0x5d4 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x208 0x5d8 0x8dc 0x0 0x0 +-#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x208 0x5d8 0x000 0x1 0x0 +-#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0 +-#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x208 0x5d8 0x000 0x4 0x0 +-#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x208 0x5d8 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_TXD1__I2C4_SDA 0x208 0x5d8 0x884 0x9 0x0 +-#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x20c 0x5dc 0x000 0x0 0x0 +-#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1 +-#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x20c 0x5dc 0x794 0x3 0x0 +-#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x20c 0x5dc 0x000 0x4 0x0 +-#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x20c 0x5dc 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x20c 0x5dc 0x000 0x6 0x0 +-#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x20c 0x5dc 0x000 0x7 0x0 +-#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x210 0x5e0 0x83c 0x0 0x1 +-#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x210 0x5e0 0x000 0x1 0x0 +-#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1 +-#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x210 0x5e0 0x790 0x3 0x1 +-#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x210 0x5e0 0x000 0x4 0x0 +-#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x210 0x5e0 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x210 0x5e0 0x000 0x6 0x0 +-#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x214 0x5e4 0x850 0x0 0x1 +-#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x214 0x5e4 0x000 0x1 0x0 +-#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0 +-#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x214 0x5e4 0x000 0x3 0x0 +-#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2 +-#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x214 0x5e4 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x214 0x5e4 0x87c 0x6 0x1 +-#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x214 0x5e4 0x000 0x7 0x0 +-#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x218 0x5e8 0x844 0x0 0x0 +-#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x218 0x5e8 0x000 0x1 0x0 +-#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1 +-#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x218 0x5e8 0x8e8 0x3 0x1 +-#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x218 0x5e8 0x000 0x4 0x0 +-#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x218 0x5e8 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x21c 0x5ec 0x848 0x0 0x0 +-#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x21c 0x5ec 0x814 0x1 0x0 +-#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0 +-#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x21c 0x5ec 0x8ec 0x3 0x1 +-#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x21c 0x5ec 0x794 0x4 0x1 +-#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x21c 0x5ec 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x21c 0x5ec 0x000 0x6 0x0 +-#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2 +-#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x220 0x5f0 0x000 0x1 0x0 +-#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0 +-#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x220 0x5f0 0x000 0x3 0x0 +-#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x220 0x5f0 0x000 0x4 0x0 +-#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x220 0x5f0 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x220 0x5f0 0x000 0x6 0x0 +-#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1 +-#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1 +-#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0 +-#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1 +-#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x228 0x5f8 0x834 0x0 0x1 +-#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1 +-#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x228 0x5f8 0x000 0x3 0x0 +-#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x228 0x5f8 0x000 0x4 0x0 +-#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x228 0x5f8 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x228 0x5f8 0x924 0x6 0x1 +-#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x228 0x5f8 0x8dc 0x7 0x1 +-#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x22c 0x5fc 0x838 0x0 0x1 +-#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1 +-#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x22c 0x5fc 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x22c 0x5fc 0x000 0x6 0x0 +-#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x230 0x600 0x84c 0x0 0x1 +-#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1 +-#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x230 0x600 0x000 0x3 0x0 +-#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x230 0x600 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2 +-#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0 +-#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1 +-#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x234 0x604 0x03c 0x11 0xff000609 +-#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2 +-#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0 +-#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1 +-#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1 +-#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0 +-#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0 +-#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0 +-#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2 +-#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0 +-#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0 +-#define MX6QDL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1 +-#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x23c 0x60c 0x858 0x0 0x1 +-#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x23c 0x60c 0x000 0x1 0x0 +-#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0 +-#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x23c 0x60c 0x7c8 0x3 0x0 +-#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x23c 0x60c 0x904 0x4 0x3 +-#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x23c 0x60c 0x000 0x4 0x0 +-#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x23c 0x60c 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x23c 0x60c 0x000 0x6 0x0 +-#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x23c 0x60c 0x000 0x7 0x0 +-#define MX6QDL_PAD_GPIO_8__I2C4_SDA 0x23c 0x60c 0x884 0x8 0x1 +-#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x240 0x610 0x82c 0x0 0x1 +-#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x240 0x610 0x000 0x1 0x0 +-#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1 +-#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x240 0x610 0x000 0x3 0x0 +-#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x240 0x610 0x000 0x4 0x0 +-#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x240 0x610 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_9__SD1_WP 0x240 0x610 0x92c 0x6 0x1 +-#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x244 0x62c 0x7d8 0x0 0x3 +-#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x244 0x62c 0x824 0x1 0x0 +-#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1 +-#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x244 0x62c 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x244 0x62c 0x000 0x4 0x0 +-#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2 +-#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x244 0x62c 0x000 0x5 0x0 +-#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x244 0x62c 0x000 0x6 0x0 +-#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3 +-#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1 +-#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1 +-#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0 +-#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2 +-#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0 +-#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0 +-#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2 +-#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0 +-#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0 +-#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x24c 0x634 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x24c 0x634 0x000 0x4 0x0 +-#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x24c 0x634 0x000 0x5 0x0 +-#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x24c 0x634 0x000 0x6 0x0 +-#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1 +-#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0 +-#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1 +-#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1 +-#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0 +-#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3 +-#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0 +-#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0 +-#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1 +-#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2 +-#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0 +-#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0 +-#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x258 0x640 0x7e0 0x0 0x3 +-#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x258 0x640 0x000 0x1 0x0 +-#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1 +-#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x258 0x640 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x258 0x640 0x914 0x4 0x3 +-#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x258 0x640 0x000 0x4 0x0 +-#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x258 0x640 0x000 0x5 0x0 +-#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x258 0x640 0x000 0x6 0x0 +-#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x25c 0x644 0x7e4 0x0 0x3 +-#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x25c 0x644 0x000 0x1 0x0 +-#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1 +-#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x25c 0x644 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x25c 0x644 0x91c 0x4 0x3 +-#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x25c 0x644 0x000 0x4 0x0 +-#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x25c 0x644 0x000 0x5 0x0 +-#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x25c 0x644 0x000 0x6 0x0 +-#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x260 0x648 0x7ec 0x0 0x1 +-#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x260 0x648 0x000 0x1 0x0 +-#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1 +-#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x260 0x648 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x260 0x648 0x000 0x4 0x0 +-#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x260 0x648 0x000 0x5 0x0 +-#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x260 0x648 0x85c 0x6 0x1 +-#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2 +-#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1 +-#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x264 0x64c 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1 +-#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0 +-#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x264 0x64c 0x000 0x6 0x0 +-#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x268 0x650 0x7cc 0x0 0x0 +-#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x268 0x650 0x000 0x1 0x0 +-#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0 +-#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x268 0x650 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x268 0x650 0x000 0x4 0x0 +-#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x268 0x650 0x918 0x4 0x3 +-#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x268 0x650 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x26c 0x654 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x26c 0x654 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x26c 0x654 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x270 0x658 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x270 0x658 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x274 0x65c 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x274 0x65c 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x278 0x660 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x278 0x660 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0 +-#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x278 0x660 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x27c 0x664 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x27c 0x664 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1 +-#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x27c 0x664 0x000 0x3 0x0 +-#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x27c 0x664 0x000 0x4 0x0 +-#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x27c 0x664 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x280 0x668 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x280 0x668 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1 +-#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x280 0x668 0x000 0x3 0x0 +-#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x280 0x668 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2 +-#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x284 0x66c 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x284 0x66c 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x284 0x66c 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x288 0x670 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x288 0x670 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x288 0x670 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x28c 0x674 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x28c 0x674 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x28c 0x674 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x290 0x678 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x290 0x678 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x290 0x678 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x294 0x67c 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x294 0x67c 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x294 0x67c 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x298 0x680 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x298 0x680 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x298 0x680 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x29c 0x684 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x29c 0x684 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x29c 0x684 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x2a0 0x688 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x2a0 0x688 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x2a0 0x688 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2a4 0x68c 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2a4 0x68c 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2a8 0x690 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2a8 0x690 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2 +-#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x2ac 0x694 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x2ac 0x694 0x818 0x1 0x1 +-#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x2ac 0x694 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x2b0 0x698 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x2b0 0x698 0x81c 0x1 0x1 +-#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x2b0 0x698 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x2b4 0x69c 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1 +-#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x2b4 0x69c 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x2b8 0x6a0 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x2b8 0x6a0 0x824 0x1 0x1 +-#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x2b8 0x6a0 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x2bc 0x6a4 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x2bc 0x6a4 0x828 0x1 0x1 +-#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x2bc 0x6a4 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x2c0 0x6a8 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x2c0 0x6a8 0x814 0x1 0x1 +-#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x2c0 0x6a8 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x2c4 0x6ac 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0 +-#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x2c4 0x6ac 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x2c8 0x6b0 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x2c8 0x6b0 0x000 0x1 0x0 +-#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x2c8 0x6b0 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x2cc 0x6b4 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x2cc 0x6b4 0x000 0x1 0x0 +-#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x2cc 0x6b4 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x2d0 0x6b8 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x2d0 0x6b8 0x000 0x1 0x0 +-#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x2d0 0x6b8 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x2d4 0x6bc 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x2d4 0x6bc 0x000 0x1 0x0 +-#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x2d4 0x6bc 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x2d4 0x6bc 0x80c 0x7 0x1 +-#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x2d8 0x6c0 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x2d8 0x6c0 0x000 0x1 0x0 +-#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1 +-#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0 +-#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1 +-#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x2dc 0x6c4 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0 +-#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x2e0 0x6c8 0x000 0x3 0x0 +-#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x2e0 0x6c8 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x2e4 0x6cc 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x2e4 0x6cc 0x000 0x3 0x0 +-#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x2e4 0x6cc 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x2e8 0x6d0 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x2e8 0x6d0 0x000 0x3 0x0 +-#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x2e8 0x6d0 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x2ec 0x6d4 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x2ec 0x6d4 0x000 0x3 0x0 +-#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x2ec 0x6d4 0x000 0x4 0x0 +-#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x2ec 0x6d4 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x2ec 0x6d4 0x000 0x6 0x0 +-#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x2f0 0x6d8 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x2f0 0x6d8 0x000 0x3 0x0 +-#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x2f0 0x6d8 0x000 0x4 0x0 +-#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x2f0 0x6d8 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x2f0 0x6d8 0x000 0x6 0x0 +-#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x2f4 0x6dc 0x930 0x0 0x1 +-#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3 +-#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x2f4 0x6dc 0x7a4 0x3 0x1 +-#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x2f4 0x6dc 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x2f8 0x6e0 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2 +-#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x2f8 0x6e0 0x7a0 0x3 0x1 +-#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x2f8 0x6e0 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x2fc 0x6e4 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x2fc 0x6e4 0x798 0x3 0x1 +-#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2 +-#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x2fc 0x6e4 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x2fc 0x6e4 0x000 0x6 0x0 +-#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x300 0x6e8 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x300 0x6e8 0x7ac 0x3 0x1 +-#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2 +-#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x300 0x6e8 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x304 0x6ec 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x304 0x6ec 0x79c 0x3 0x1 +-#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2 +-#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x304 0x6ec 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x308 0x6f0 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2 +-#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x308 0x6f0 0x7a8 0x3 0x1 +-#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x308 0x6f0 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x30c 0x6f4 0x934 0x0 0x1 +-#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2 +-#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x30c 0x6f4 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2 +-#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x30c 0x6f4 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x310 0x6f8 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x310 0x6f8 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x310 0x6f8 0x900 0x1 0x3 +-#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x310 0x6f8 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x314 0x6fc 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x314 0x6fc 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2 +-#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x314 0x6fc 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x318 0x700 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x318 0x700 0x8f8 0x1 0x3 +-#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x318 0x700 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1 +-#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x318 0x700 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x31c 0x704 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x31c 0x704 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x320 0x708 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x320 0x708 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x320 0x708 0x908 0x1 0x4 +-#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x320 0x708 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x324 0x70c 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x324 0x70c 0x904 0x1 0x4 +-#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x324 0x70c 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x324 0x70c 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x328 0x710 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x328 0x710 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x328 0x710 0x904 0x1 0x5 +-#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x328 0x710 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x32c 0x714 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2 +-#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x32c 0x714 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x32c 0x714 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x330 0x718 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x330 0x718 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x330 0x718 0x8fc 0x1 0x3 +-#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x330 0x718 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x334 0x71c 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x334 0x71c 0x908 0x1 0x5 +-#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x334 0x71c 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x334 0x71c 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x338 0x720 0x938 0x0 0x1 +-#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x338 0x720 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2 +-#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x338 0x720 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x33c 0x724 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x33c 0x724 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3 +-#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x33c 0x724 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x340 0x728 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x340 0x728 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x344 0x72c 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x344 0x72c 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x348 0x730 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x348 0x730 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x34c 0x734 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x34c 0x734 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x350 0x738 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6 +-#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x350 0x738 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x354 0x73c 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4 +-#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x354 0x73c 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x358 0x740 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5 +-#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x358 0x740 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x35c 0x744 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7 +-#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x35c 0x744 0x000 0x5 0x0 +- +-#endif /* __DTS_IMX6DL_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-plybas.dts b/scripts/dtc/include-prefixes/arm/imx6dl-plybas.dts +deleted file mode 100644 +index bf72a67a9c76..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-plybas.dts ++++ /dev/null +@@ -1,392 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (c) 2014 Protonic Holland +- * Copyright (c) 2020 Oleksij Rempel , Pengutronix +- */ +- +-/dts-v1/; +-#include +-#include +-#include "imx6dl.dtsi" +- +-/ { +- model = "Plymovent BAS board"; +- compatible = "ply,plybas", "fsl,imx6dl"; +- +- chosen { +- stdout-path = &uart4; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- autorepeat; +- +- button-start { +- label = "START"; +- linux,code = <31>; +- gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; +- }; +- +- button-clean { +- label = "CLEAN"; +- linux,code = <46>; +- gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds>; +- +- led-0 { +- label = "debug0"; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- }; +- +- led-1 { +- label = "debug1"; +- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- }; +- +- led-2 { +- label = "light_tower1"; +- gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-3 { +- label = "light_tower2"; +- gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; +- }; +- +- led-4 { +- label = "light_tower3"; +- gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; +- }; +- +- led-5 { +- label = "light_tower4"; +- gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- clk50m_phy: phy-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- }; +- +- reg_5v0: regulator-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- xceiver-supply = <®_5v0>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can2>; +- xceiver-supply = <®_5v0>; +- status = "okay"; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rmii"; +- clocks = <&clks IMX6QDL_CLK_ENET>, +- <&clks IMX6QDL_CLK_ENET>, +- <&clk50m_phy>; +- clock-names = "ipg", "ahb", "ptp"; +- phy-handle = <&rgmii_phy>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Microchip KSZ8081RNA PHY */ +- rgmii_phy: ethernet-phy@0 { +- reg = <0>; +- interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- reset-deassert-us = <300>; +- }; +- }; +-}; +- +-&gpio1 { +- gpio-line-names = +- "", "SD1_CD", "", "", "", "", "", "", +- "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio3 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "ECSPI1_SS1", "", "USB_EXT_PWR", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio4 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "CAN1_SR", "CAN2_SR", "", "", +- "LED_DI0_DEBUG_0", "LED_DI0_DEBUG_1", "IMX6_IN12", "IMX6_HMI", +- "IMX6_IN11", "IMX6_BUZZER", "IMX6_LED1", "IMX6_LED2", +- "IMX6_LED3", "IMX6_LED4", "ETH_RESET", "IMX6_ANA_OUT_SD", +- "IMX6_ANA_OUT_ERR", "IMX6_ANA_OUT", "ETH_INTRP", ""; +-}; +- +-&gpio5 { +- gpio-line-names = +- "", "", "", "", "", "IMX6_RELAY1", "IMX6_RELAY2", "", +- "IMX6_IN1", "IMX6_IN2", "IMX6_IN3", "IMX6_IN4", "IMX6_IN5", +- "IMX6_IN6", "IMX6_IN7", "IMX6_IN8", +- "IMX6_IN9", "IMX6_IN10", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- /* additional i2c devices are added automatically by the boot loader */ +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- temperature-sensor@70 { +- compatible = "ti,tmp103"; +- reg = <0x70>; +- }; +- +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- fsl,uart-has-rtscts; +- linux,rs485-enabled-at-boot-time; +- rs485-rts-delay = <0 20>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbotg { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- phy_type = "utmi"; +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbphynop1 { +- status = "disabled"; +-}; +- +-&usbphynop2 { +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 +- /* CAN1_SR */ +- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 +- >; +- }; +- +- pinctrl_can2: can2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 +- /* CAN2_SR */ +- MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b000 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x3008 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x3008 +- /* CS */ +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x3008 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- /* MX6QDL_ENET_PINGRP4 */ +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 +- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 +- +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 +- /* Phy reset */ +- MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 +- /* nINTRP */ +- MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_leds: ledsgrp { +- fsl,pins = < +- /* DEBUG_0 */ +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 +- /* DEBUG_1 */ +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 +- +- /* LED1 (lighttower) */ +- MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x13070 +- /* LED2 (lighttower) */ +- MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x13070 +- /* LED3 (lighttower) */ +- MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x13070 +- /* LED4 (lighttower) */ +- MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x13070 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 +- >; +- }; +- +- /* YaCO AUX Uart */ +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x130b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 +- /* power enable, high active */ +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 +- MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-plym2m.dts b/scripts/dtc/include-prefixes/arm/imx6dl-plym2m.dts +deleted file mode 100644 +index 60fe5f14666e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-plym2m.dts ++++ /dev/null +@@ -1,446 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (c) 2014 Protonic Holland +- * Copyright (c) 2020 Oleksij Rempel , Pengutronix +- */ +- +-/dts-v1/; +-#include +-#include +-#include "imx6dl.dtsi" +- +-/ { +- model = "Plymovent M2M board"; +- compatible = "ply,plym2m", "fsl,imx6dl"; +- +- chosen { +- stdout-path = &uart4; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 5000000 0>; +- brightness-levels = <0 1000>; +- num-interpolated-steps = <20>; +- default-brightness-level = <19>; +- power-supply = <®_12v0>; +- }; +- +- display { +- compatible = "fsl,imx-parallel-display"; +- pinctrl-0 = <&pinctrl_ipu1_disp>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- display_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds>; +- +- led-0 { +- label = "debug0"; +- function = LED_FUNCTION_STATUS; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- panel { +- compatible = "edt,etm0700g0bdh6"; +- backlight = <&backlight>; +- power-supply = <®_3v3>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +- +- clk50m_phy: phy-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_5v0: regulator-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_12v0: regulator-12v0 { +- compatible = "regulator-fixed"; +- regulator-name = "12v0"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- xceiver-supply = <®_5v0>; +- status = "okay"; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- }; +-}; +- +-&ecspi2 { +- cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- status = "okay"; +- +- touchscreen@0 { +- compatible = "ti,tsc2046"; +- reg = <0>; +- pinctrl-0 = <&pinctrl_tsc2046>; +- pinctrl-names ="default"; +- spi-max-frequency = <100000>; +- interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; +- pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; +- +- touchscreen-inverted-x; +- touchscreen-inverted-y; +- touchscreen-max-pressure = <4095>; +- +- ti,vref-delay-usecs = /bits/ 16 <100>; +- ti,x-plate-ohms = /bits/ 16 <800>; +- ti,y-plate-ohms = /bits/ 16 <300>; +- ti,debounce-max = /bits/ 16 <3>; +- ti,debounce-tol = /bits/ 16 <70>; +- ti,debounce-rep = /bits/ 16 <3>; +- wakeup-source; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rmii"; +- clocks = <&clks IMX6QDL_CLK_ENET>, +- <&clks IMX6QDL_CLK_ENET>, +- <&clk50m_phy>; +- clock-names = "ipg", "ahb", "ptp"; +- phy-handle = <&rgmii_phy>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Microchip KSZ8081RNA PHY */ +- rgmii_phy: ethernet-phy@0 { +- reg = <0>; +- interrupts-extended = <&gpio5 23 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- reset-deassert-us = <300>; +- }; +- }; +-}; +- +-&gpio1 { +- gpio-line-names = +- "CAN1_TERM", "SD1_CD", "", "", "", "", "", "", +- "DEBUG_0", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio2 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "ECSPI2_SS0", "", "", "", "TSC_BUSY", ""; +-}; +- +-&gpio3 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "ECSPI1_SS1", "TSC_PENIRQ", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio4 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "CAN1_SR", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio5 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "ETH_RESET", "ETH_INTRP", +- "", "", "", "", "", "", "", ""; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- /* additional i2c devices are added automatically by the boot loader */ +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- temperature-sensor@70 { +- compatible = "ti,tmp103"; +- reg = <0x70>; +- }; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&display_in>; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbphynop1 { +- status = "disabled"; +-}; +- +-&usbphynop2 { +- status = "disabled"; +-}; +- +-&usbotg { +- phy_type = "utmi"; +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- disable-wp; +- cap-sd-highspeed; +- no-mmc; +- no-sdio; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- no-sd; +- no-sdio; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 +- /* CAN1_SR */ +- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 +- /* CAN1_TERM */ +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b000 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x3008 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x3008 +- /* CS */ +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x3008 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x10000 +- MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x3008 +- MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x3008 +- /* CS */ +- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x3008 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- /* MX6QDL_ENET_PINGRP4 */ +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 +- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 +- +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 +- /* Phy reset */ +- MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 +- /* nINTRP */ +- MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_ipu1_disp: ipudisp1grp { +- fsl,pins = < +- /* DSE 0x30 => 25 Ohm, 0x20 => 37 Ohm, 0x10 => 75 Ohm */ +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x30 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x30 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x30 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x30 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x30 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x30 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x30 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x30 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x30 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x30 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x30 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x30 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x30 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x30 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x30 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x30 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x30 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x30 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x30 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x30 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x30 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x30 +- >; +- }; +- +- pinctrl_leds: ledsgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 +- >; +- }; +- +- pinctrl_tsc2046: tsc2046grp { +- fsl,pins = < +- /* TSC_PENIRQ */ +- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 +- /* TSC_BUSY */ +- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 +- MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-prtmvt.dts b/scripts/dtc/include-prefixes/arm/imx6dl-prtmvt.dts +deleted file mode 100644 +index a35a1c66e770..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-prtmvt.dts ++++ /dev/null +@@ -1,852 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (c) 2016 Protonic Holland +- * Copyright (c) 2020 Oleksij Rempel , Pengutronix +- */ +- +-/dts-v1/; +-#include +-#include +-#include +-#include +-#include +-#include +-#include "imx6dl.dtsi" +- +-/ { +- model = "Protonic MVT board"; +- compatible = "prt,prtmvt", "fsl,imx6dl"; +- +- chosen { +- stdout-path = &uart4; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_backlight>; +- pwms = <&pwm1 0 5000000 0>; +- brightness-levels = <0 16 64 255>; +- num-interpolated-steps = <16>; +- default-brightness-level = <1>; +- power-supply = <®_3v3>; +- enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; +- }; +- +- connector { +- compatible = "composite-video-connector"; +- label = "Composite0"; +- sdtv-standards = ; +- +- port { +- comp0_out: endpoint { +- remote-endpoint = <&tvp5150_comp0_in>; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpiokeys>; +- autorepeat; +- +- power { +- label = "Power Button"; +- gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- f1 { +- label = "GPIO Key F1"; +- linux,code = ; +- gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>; +- }; +- +- f2 { +- label = "GPIO Key F2"; +- linux,code = ; +- gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>; +- }; +- +- f3 { +- label = "GPIO Key F3"; +- linux,code = ; +- gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>; +- }; +- +- f4 { +- label = "GPIO Key F4"; +- linux,code = ; +- gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>; +- }; +- +- f5 { +- label = "GPIO Key F5"; +- linux,code = ; +- gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>; +- }; +- +- cycle { +- label = "GPIO Key CYCLE"; +- linux,code = ; +- gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>; +- }; +- +- esc { +- label = "GPIO Key ESC"; +- linux,code = ; +- gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>; +- }; +- +- up { +- label = "GPIO Key UP"; +- linux,code = ; +- gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>; +- }; +- +- down { +- label = "GPIO Key DOWN"; +- linux,code = ; +- gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>; +- }; +- +- ok { +- label = "GPIO Key OK"; +- linux,code = ; +- gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>; +- }; +- +- f6 { +- label = "GPIO Key F6"; +- linux,code = ; +- gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>; +- }; +- +- f7 { +- label = "GPIO Key F7"; +- linux,code = ; +- gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>; +- }; +- +- f8 { +- label = "GPIO Key F8"; +- linux,code = ; +- gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>; +- }; +- +- f9 { +- label = "GPIO Key F9"; +- linux,code = ; +- gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>; +- }; +- +- f10 { +- label = "GPIO Key F10"; +- linux,code = ; +- gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>; +- }; +- +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds>; +- +- led-0 { +- label = "debug0"; +- function = LED_FUNCTION_HEARTBEAT; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-1 { +- label = "debug1"; +- function = LED_FUNCTION_DISK; +- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "disk-activity"; +- }; +- +- led-2 { +- label = "power_led"; +- function = LED_FUNCTION_POWER; +- gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- panel { +- compatible = "kyo,tcg070wvlq", "lg,lb070wv8"; +- backlight = <&backlight>; +- power-supply = <®_3v3>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +- +- clk50m_phy: phy-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- }; +- +- reg_1v8: regulator-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_h1_vbus: regulator-h1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "h1-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_otg_vbus: regulator-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "otg-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "prti6q-sgtl5000"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,widgets = +- "Microphone", "Microphone Jack", +- "Line", "Line In Jack", +- "Headphone", "Headphone Jack", +- "Speaker", "External Speaker"; +- simple-audio-card,routing = +- "MIC_IN", "Microphone Jack", +- "LINE_IN", "Line In Jack", +- "Headphone Jack", "HP_OUT", +- "External Speaker", "LINE_OUT"; +- +- simple-audio-card,cpu { +- sound-dai = <&ssi1>; +- system-clock-frequency = <0>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&codec>; +- bitclock-master; +- frame-master; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +- +- mux-ssi1 { +- fsl,audmux-port = <0>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN 0 +- IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 +- IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 +- IMX_AUDMUX_V2_PTCR_TFSDIR 0 +- IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) +- >; +- }; +- +- mux-pins3 { +- fsl,audmux-port = <2>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) +- 0 IMX_AUDMUX_V2_PDCR_TXRXEN +- >; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can2>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rmii"; +- clocks = <&clks IMX6QDL_CLK_ENET>, +- <&clks IMX6QDL_CLK_ENET>, +- <&clk50m_phy>; +- clock-names = "ipg", "ahb", "ptp"; +- phy-handle = <&rmii_phy>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Microchip KSZ8081RNA PHY */ +- rmii_phy: ethernet-phy@0 { +- reg = <0>; +- interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- reset-deassert-us = <3000>; +- }; +- }; +-}; +- +-&gpio1 { +- gpio-line-names = +- "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", +- "CAM2_MIRROR", "", "", "SMBALERT", +- "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", +- "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", +- "SD1_DATA3", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio2 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4", +- "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", +- "", "", "", "", "", "", "", "ON_SWITCH", +- "POWER_LED", "", "", "", "", "", "", ""; +-}; +- +-&gpio3 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", +- "CPU_ON1_FB", "USB_EXT1_OC", "USB_EXT1_PWR", "YACO_IRQ", +- "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", +- "YACO_RESET"; +-}; +- +-&gpio4 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "CAN1_SR", "CAN2_SR", "CAN2_TX", "CAN2_RX", +- "", "", "DIP1_FB", "", "", "", "", "", +- "CPU_LIGHT_ON", "", "ETH_RESET", "", "BL_EN", +- "BL_PWM", "ETH_INTRP", ""; +-}; +- +-&gpio5 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", +- "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- codec: audio-codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0xa>; +- #sound-dai-cells = <0>; +- clocks = <&clks 201>; +- VDDA-supply = <®_3v3>; +- VDDIO-supply = <®_3v3>; +- VDDD-supply = <®_1v8>; +- }; +- +- video@5c { +- compatible = "ti,tvp5150"; +- reg = <0x5c>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tvp5150_comp0_in: endpoint { +- remote-endpoint = <&comp0_out>; +- }; +- }; +- +- /* Output port 2 is video output pad */ +- port@2 { +- reg = <2>; +- tvp5151_to_ipu1_csi0_mux: endpoint { +- remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; +- }; +- }; +- }; +- +- gpio_pca: gpio@74 { +- compatible = "nxp,pca9539"; +- reg = <0x74>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pca9539>; +- interrupt-parent = <&gpio4>; +- interrupts = <5 IRQ_TYPE_LEVEL_LOW>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- /* additional i2c devices are added automatically by the boot loader */ +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- adc@49 { +- compatible = "ti,ads1015"; +- reg = <0x49>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@4 { +- reg = <4>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- +- channel@5 { +- reg = <5>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- +- channel@6 { +- reg = <6>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- +- channel@7 { +- reg = <7>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- }; +- +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- +- temperature-sensor@70 { +- compatible = "ti,tmp103"; +- reg = <0x70>; +- }; +-}; +- +-&ipu1_csi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_csi0>; +- status = "okay"; +-}; +- +-&ipu1_csi0_mux_from_parallel_sensor { +- remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&ssi1 { +- #sound-dai-cells = <0>; +- fsl,mode = "ac97-slave"; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_h1_vbus>; +- pinctrl-names = "default"; +- phy_type = "utmi"; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- phy_type = "utmi"; +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- disable-wp; +- cap-sd-highspeed; +- no-mmc; +- no-sdio; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- no-sd; +- no-sdio; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- /* SGTL5000 sys_mclk */ +- MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- >; +- }; +- +- pinctrl_backlight: backlightgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 +- >; +- }; +- +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 +- /* CAN1_SR */ +- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 +- /* CAN1_TERM */ +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 +- >; +- }; +- +- pinctrl_can2: can2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 +- /* CAN2_SR */ +- MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- /* CS */ +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- /* MX6QDL_ENET_PINGRP4 */ +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 +- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 +- /* Phy reset */ +- MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 +- /* nINTRP */ +- MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 +- >; +- }; +- +- pinctrl_gpiokeys: gpiokeygrp { +- fsl,pins = < +- /* nON_SWITCH */ +- MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 +- >; +- }; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- /* ITU656_nRESET */ +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +- /* CAM1_MIRROR */ +- MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 +- /* CAM2_MIRROR */ +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 +- /* CAM_nDETECT */ +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 +- /* ISB_IN1 */ +- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 +- /* ISB_nIN2 */ +- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 +- /* WARN_LIGHT */ +- MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0 +- /* ON2_FB */ +- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 +- /* YACO_nIRQ */ +- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 +- /* YACO_BOOT0 */ +- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 +- /* YACO_nRESET */ +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 +- /* FORCE_ON1 */ +- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +- /* AUDIO_nRESET */ +- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 +- /* ITU656_nPDN */ +- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 +- +- /* HW revision detect */ +- /* REV_ID0 */ +- MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 +- /* REV_ID1 */ +- MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 +- /* REV_ID2 */ +- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 +- /* REV_ID3 */ +- MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 +- /* REV_ID4 */ +- MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 +- +- /* New in HW revision 1 */ +- /* ON1_FB */ +- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 +- /* DIP1_FB */ +- MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_ipu1_csi0: ipu1csi0grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 +- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 +- >; +- }; +- +- pinctrl_leds: ledsgrp { +- fsl,pins = < +- /* DEBUG0 */ +- MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 +- /* DEBUG1 */ +- MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 +- /* POWER_LED */ +- MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 +- >; +- }; +- +- pinctrl_pca9539: pca9539 { +- fsl,pins = < +- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 +- >; +- }; +- +- /* YaCO AUX Uart */ +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- /* YaCO Touchscreen UART */ +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 +- /* power enable, high active */ +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 +- MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-prtrvt.dts b/scripts/dtc/include-prefixes/arm/imx6dl-prtrvt.dts +deleted file mode 100644 +index 5ac84445e9cc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-prtrvt.dts ++++ /dev/null +@@ -1,184 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (c) 2014 Protonic Holland +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-prti6q.dtsi" +-#include +- +-/ { +- model = "Protonic RVT board"; +- compatible = "prt,prtrvt", "fsl,imx6dl"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x10000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds>; +- +- led-debug0 { +- function = LED_FUNCTION_STATUS; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; +- status = "okay"; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&ecspi3 { +- cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi3>; +- status = "okay"; +- +- nfc@0 { +- compatible = "ti,trf7970a"; +- reg = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nfc>; +- spi-max-frequency = <2000000>; +- interrupts-extended = <&gpio5 14 IRQ_TYPE_LEVEL_LOW>; +- ti,enable-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>, +- <&gpio5 11 GPIO_ACTIVE_LOW>; +- vin-supply = <®_3v3>; +- vin-voltage-override = <3100000>; +- autosuspend-delay = <30000>; +- irq-status-read-quirk; +- en2-rf-quirk; +- t5t-rmb-extra-byte-quirk; +- status = "okay"; +- }; +-}; +- +-&i2c3 { +- adc@49 { +- compatible = "ti,ads1015"; +- reg = <0x49>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* nc */ +- channel@4 { +- reg = <4>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- +- /* nc */ +- channel@5 { +- reg = <5>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- +- /* can1_l */ +- channel@6 { +- reg = <6>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- +- /* can1_h */ +- channel@7 { +- reg = <7>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- }; +- +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&usbh1 { +- status = "disabled"; +-}; +- +-&vpu { +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_can1phy: can1phy { +- fsl,pins = < +- /* CAN1_SR */ +- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 +- /* CAN1_TERM */ +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- /* CS */ +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 +- >; +- }; +- +- pinctrl_ecspi3: ecspi3grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 +- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 +- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 +- MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 +- >; +- }; +- +- pinctrl_leds: ledsgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 +- >; +- }; +- +- pinctrl_nfc: nfcgrp { +- fsl,pins = < +- /* NFC_ASK_OOK */ +- MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x100b1 +- /* NFC_PWR_EN */ +- MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x100b1 +- /* NFC_EN2 */ +- MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x100b1 +- /* NFC_EN */ +- MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 +- /* NFC_MOD */ +- MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1 +- /* NFC_IRQ */ +- MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-prtvt7.dts b/scripts/dtc/include-prefixes/arm/imx6dl-prtvt7.dts +deleted file mode 100644 +index 190d26642bc8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-prtvt7.dts ++++ /dev/null +@@ -1,413 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (c) 2016 Protonic Holland +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-prti6q.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "Protonic VT7"; +- compatible = "prt,prtvt7", "fsl,imx6dl"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +- +- backlight_lcd: backlight-lcd { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 500000 0>; +- brightness-levels = <0 20 81 248 1000>; +- default-brightness-level = <20>; +- num-interpolated-steps = <21>; +- power-supply = <®_bl_12v0>; +- }; +- +- keys { +- compatible = "gpio-keys"; +- autorepeat; +- +- esc { +- label = "GPIO Key ESC"; +- linux,code = ; +- gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>; +- }; +- +- up { +- label = "GPIO Key UP"; +- linux,code = ; +- gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>; +- }; +- +- down { +- label = "GPIO Key DOWN"; +- linux,code = ; +- gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>; +- }; +- +- enter { +- label = "GPIO Key Enter"; +- linux,code = ; +- gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>; +- }; +- +- cycle { +- label = "GPIO Key CYCLE"; +- linux,code = ; +- gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>; +- }; +- +- f1 { +- label = "GPIO Key F1"; +- linux,code = ; +- gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>; +- }; +- +- f2 { +- label = "GPIO Key F2"; +- linux,code = ; +- gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>; +- }; +- +- f3 { +- label = "GPIO Key F3"; +- linux,code = ; +- gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>; +- }; +- +- f4 { +- label = "GPIO Key F4"; +- linux,code = ; +- gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>; +- }; +- +- f5 { +- label = "GPIO Key F5"; +- linux,code = ; +- gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>; +- }; +- +- f6 { +- label = "GPIO Key F6"; +- linux,code = ; +- gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>; +- }; +- +- f7 { +- label = "GPIO Key F7"; +- linux,code = ; +- gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>; +- }; +- +- f8 { +- label = "GPIO Key F8"; +- linux,code = ; +- gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>; +- }; +- +- f9 { +- label = "GPIO Key F9"; +- linux,code = ; +- gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>; +- }; +- +- f10 { +- label = "GPIO Key F10"; +- linux,code = ; +- gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds>; +- +- led-debug0 { +- function = LED_FUNCTION_STATUS; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- reg_bl_12v0: regulator-bl-12v0 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_bl_12v0>; +- regulator-name = "bl-12v0"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_1v8: regulator-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "prti6q-sgtl5000"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,widgets = +- "Microphone", "Microphone Jack", +- "Line", "Line In Jack", +- "Headphone", "Headphone Jack", +- "Speaker", "External Speaker"; +- simple-audio-card,routing = +- "MIC_IN", "Microphone Jack", +- "LINE_IN", "Line In Jack", +- "Headphone Jack", "HP_OUT", +- "External Speaker", "LINE_OUT"; +- +- simple-audio-card,cpu { +- sound-dai = <&ssi1>; +- system-clock-frequency = <0>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- bitclock-master; +- frame-master; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +- +- mux-ssi1 { +- fsl,audmux-port = <0>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN 0 +- IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 +- IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 +- IMX_AUDMUX_V2_PTCR_TFSDIR 0 +- IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) +- >; +- }; +- +- mux-pins3 { +- fsl,audmux-port = <2>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) +- 0 IMX_AUDMUX_V2_PDCR_TXRXEN +- >; +- }; +-}; +- +-&can1 { +- pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; +-}; +- +-&ecspi2 { +- cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- status = "okay"; +- +- touchscreen@0 { +- compatible = "ti,tsc2046"; +- reg = <0>; +- pinctrl-0 = <&pinctrl_tsc>; +- pinctrl-names ="default"; +- spi-max-frequency = <100000>; +- interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; +- pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; +- touchscreen-max-pressure = <4095>; +- ti,vref-delay-usecs = /bits/ 16 <100>; +- ti,x-plate-ohms = /bits/ 16 <800>; +- ti,y-plate-ohms = /bits/ 16 <300>; +- ti,debounce-max = /bits/ 16 <3>; +- ti,debounce-tol = /bits/ 16 <70>; +- ti,debounce-rep = /bits/ 16 <3>; +- wakeup-source; +- }; +-}; +- +-&i2c1 { +- sgtl5000: audio-codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0xa>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_codec>; +- #sound-dai-cells = <0>; +- clocks = <&clks 201>; +- VDDA-supply = <®_3v3>; +- VDDIO-supply = <®_3v3>; +- VDDD-supply = <®_1v8>; +- }; +-}; +- +-&i2c3 { +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- +- gpio_pca: gpio@74 { +- compatible = "nxp,pca9539"; +- reg = <0x74>; +- interrupts-extended = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>; +- #gpio-cells = <2>; +- gpio-controller; +- }; +-}; +- +-&ipu1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_csi0>; +- status = "okay"; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&snvs_poweroff { +- status = "okay"; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&usbh1 { +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- >; +- }; +- +- pinctrl_can1phy: can1phy { +- fsl,pins = < +- /* CAN1_SR */ +- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 +- /* CAN1_TERM */ +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 +- >; +- }; +- +- pinctrl_codec: codecgrp { +- fsl,pins = < +- /* AUDIO_nRESET */ +- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 +- MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 +- MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 +- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 +- >; +- }; +- +- pinctrl_ipu1_csi0: ipu1csi0grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 +- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 +- /* ITU656_nRESET */ +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +- /* ITU656_nPDN */ +- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 +- >; +- }; +- +- pinctrl_ipu1_disp: ipudisp1grp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xb0 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xb0 +- +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xb0 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xb0 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xb0 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xb0 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xb0 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xb0 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xb0 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xb0 +- +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xb0 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xb0 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xb0 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xb0 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xb0 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xb0 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xb0 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xb0 +- +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xb0 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xb0 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xb0 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xb0 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xb0 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xb0 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xb0 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xb0 +- >; +- }; +- +- pinctrl_leds: ledsgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 +- >; +- }; +- +- pinctrl_reg_bl_12v0: 12blgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 +- >; +- }; +- +- pinctrl_tsc: tscgrp { +- +- fsl,pins = < +- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 +- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-qmx6.dtsi b/scripts/dtc/include-prefixes/arm/imx6dl-qmx6.dtsi +deleted file mode 100644 +index 150d69858255..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-qmx6.dtsi ++++ /dev/null +@@ -1,612 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 or MIT +-// +-// Device Tree Source for i.MX6DL based congatec QMX6 +-// System on Module +-// +-// Copyright 2018-2021 General Electric Company +-// Copyright 2018-2021 Collabora +-// Copyright 2016 congatec AG +- +-#include "imx6dl.dtsi" +-#include +-#include +- +-/ { +- memory@10000000 { +- reg = <0x10000000 0x40000000>; +- }; +- +- reg_3p3v: 3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- i2cmux { +- compatible = "i2c-mux-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- mux-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; +- i2c-parent = <&i2c2>; +- +- i2c5: i2c@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c6: i2c@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- +- audmux_ssi1 { +- fsl,audmux-port = ; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_TFSDIR | +- IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT6) | +- IMX_AUDMUX_V2_PTCR_TCLKDIR | +- IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT6) | +- IMX_AUDMUX_V2_PTCR_SYN) +- IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT6) +- >; +- }; +- +- audmux_aud6 { +- fsl,audmux-port = ; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN +- IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) +- >; +- }; +-}; +- +-&clks { +- clocks = <&rtc_sqw>; +- clock-names = "ckil"; +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, +- <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1>; +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "sst,sst25vf032b", "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- +- partition@0 { +- label = "bootloader"; +- reg = <0x0000000 0x100000>; +- }; +- +- partition@100000 { +- label = "user"; +- reg = <0x0100000 0x2fc000>; +- }; +- +- partition@3fc000 { +- label = "reserved"; +- reg = <0x03fc000 0x4000>; +- read-only; +- }; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet &pinctrl_phy_reset>; +- phy-mode = "rgmii-id"; +- phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; +- fsl,magic-packet; +- phy-handle = <&phy0>; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: ethernet-phy@6 { +- reg = <6>; +- qca,clk-out-frequency = <125000000>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c1>; +- pinctrl-1 = <&pinctrl_i2c1_gpio>; +- scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c2>; +- pinctrl-1 = <&pinctrl_i2c2_gpio>; +- scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c3>; +- pinctrl-1 = <&pinctrl_i2c3_gpio>; +- scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +- +- rtc: m41t62@68 { +- compatible = "st,m41t62"; +- reg = <0x68>; +- +- rtc_sqw: clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- }; +-}; +- +-&i2c6 { +- pmic@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <675000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* +- * keep VGEN3, VGEN4 and VGEN5 enabled in order to +- * maintain backward compatibility with hw-rev. A.0 +- */ +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- /* supply voltage for eMMC */ +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&pcie { +- reset-gpio = <&gpio1 20 0>; +-}; +- +-&pwm4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +-}; +- +-®_arm { +- vin-supply = <&sw1a_reg>; +-}; +- +-®_pu { +- vin-supply = <&sw1c_reg>; +-}; +- +-®_soc { +- vin-supply = <&sw1c_reg>; +-}; +- +-&snvs_poweroff { +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&usbh1 { +- /* Connected to USB-Hub SMSC USB2514, provides P0, P2, P3, P4 on Qseven connector */ +- vbus-supply = <®_5v>; +- status = "okay"; +-}; +- +-&usbotg { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +-}; +- +-&usdhc2 { +- /* MicroSD card slot */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- keep-power-in-suspend; +- wakeup-source; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&usdhc3 { +- /* eMMC module */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- non-removable; +- bus-width = <8>; +- no-1-8-v; +- keep-power-in-suspend; +- wakeup-source; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- qmx6mux: imx6qdl-qmx6 { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x110b0 /* Q7[67] HDA_SDO */ +- MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x30b0 /* Q7[59] HDA_SYNC */ +- MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x30b0 /* Q7[65] HDA_SDI */ +- MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x30b0 /* Q7[63] HDA_BITCLK */ +- >; +- }; +- +- /* PHY is on System on Module, Q7[3-15] have Ethernet lines */ +- pinctrl_enet: enet { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 +- >; +- }; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* PCIE_WAKE_B */ +- MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x80000000 /* I2C multiplexer */ +- MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* SD4_CD# */ +- MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* SD4_WP */ +- MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x80000000 /* Camera MCLK */ +- >; +- }; +- +- pinctrl_i2c1: i2c1 { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 /* Q7[66] I2C_CLK */ +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 /* Q7[68] I2C_DAT */ +- >; +- }; +- +- pinctrl_i2c1_gpio: i2c1-gpio { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /* Q7[66] I2C_CLK */ +- MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b0 /* Q7[68] I2C_DAT */ +- >; +- }; +- +- pinctrl_i2c2: i2c2 { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 /* Q7[152] SDVO_CTRL_CLK */ +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 /* Q7[150] SDVO_CTRL_DAT */ +- >; +- }; +- +- pinctrl_i2c2_gpio: i2c2-gpio { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 /* Q7[152] SDVO_CTRL_CLK */ +- MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 /* Q7[150] SDVO_CTRL_DAT */ +- >; +- }; +- +- pinctrl_i2c3: i2c3 { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 /* Q7[60] SMB_CLK */ +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 /* Q7[62] SMB_DAT */ +- >; +- }; +- +- pinctrl_i2c3_gpio: i2c3-gpio { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 /* Q7[60] SMB_CLK */ +- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* Q7[62] SMB_DAT */ +- >; +- }; +- +- pinctrl_phy_reset: phy-reset { +- fsl,pins = < +- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* RGMII Phy Reset */ +- >; +- }; +- +- pinctrl_pwm4: pwm4 { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 /* Q7[123] LVDS_BLT_CTRL */ +- >; +- }; +- +- pinctrl_q7_backlight_enable: q7-backlight-enable { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* Q7[112] LVDS_BLEN */ +- >; +- }; +- +- pinctrl_q7_gpio0: q7-gpio0 { +- fsl,pins = < +- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /* Q7[185] GPIO0 */ +- >; +- }; +- +- pinctrl_q7_gpio1: q7-gpio1 { +- fsl,pins = < +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* Q7[186] GPIO1 */ +- >; +- }; +- +- pinctrl_q7_gpio2: q7-gpio2 { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 /* Q7[187] GPIO2 */ +- >; +- }; +- +- pinctrl_q7_gpio3: q7-gpio3 { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 /* Q7[188] GPIO3 */ +- >; +- }; +- +- pinctrl_q7_gpio4: q7-gpio4 { +- fsl,pins = < +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* Q7[189] GPIO4 */ +- >; +- }; +- +- pinctrl_q7_gpio5: q7-gpio5 { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* Q7[190] GPIO5 */ +- >; +- }; +- +- pinctrl_q7_gpio6: q7-gpio6 { +- fsl,pins = < +- MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /* Q7[191] GPIO6 */ +- >; +- }; +- +- pinctrl_q7_gpio7: q7-gpio7 { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* Q7[192] GPIO7 */ +- >; +- }; +- +- pinctrl_q7_hda_reset: q7-hda-reset { +- fsl,pins = < +- MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 /* Q7[61] HDA_RST_N */ +- >; +- }; +- +- pinctrl_q7_lcd_power: lcd-power { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* Q7[111] LVDS_PPEN */ +- >; +- }; +- +- pinctrl_q7_sdio_power: q7-sdio-power { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 /* Q7[47] SDIO_PWR# */ +- >; +- }; +- +- pinctrl_q7_sleep_button: q7-sleep-button { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* Q7[21] SLP_BTN# */ +- >; +- }; +- +- pinctrl_q7_spi_cs1: spi-cs1 { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 /* Q7[202] SPI_CS1# */ +- >; +- }; +- +- /* SPI1 bus does not leave System on Module */ +- pinctrl_spi1: spi1 { +- fsl,pins = < +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 +- >; +- }; +- +- /* Debug connector on Q7 module */ +- pinctrl_uart2: uart2 { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3 { +- fsl,pins = < +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 /* Q7[177] UART0_RX */ +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 /* Q7[171] UART0_TX */ +- >; +- }; +- +- pinctrl_usbotg: usbotg { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 /* Q7[92] USB_ID */ +- >; +- }; +- +- /* µSD card slot on Q7 module */ +- pinctrl_usdhc2: usdhc2 { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2_CD */ +- >; +- }; +- +- /* eMMC module on Q7 module */ +- pinctrl_usdhc3: usdhc3 { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- >; +- }; +- +- pinctrl_usdhc4: usdhc4 { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 /* Q7[45] SDIO_CMD */ +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 /* Q7[42] SDIO_CLK */ +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 /* Q7[48] SDIO_DAT1 */ +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 /* Q7[49] SDIO_DAT0 */ +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 /* Q7[50] SDIO_DAT3 */ +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 /* Q7[51] SDIO_DAT2 */ +- >; +- }; +- +- pinctrl_wdog: wdog { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 /* Watchdog output signal */ +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-rex-basic.dts b/scripts/dtc/include-prefixes/arm/imx6dl-rex-basic.dts +deleted file mode 100644 +index 0f1616bfa9a8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-rex-basic.dts ++++ /dev/null +@@ -1,27 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright 2014 FEDEVEL, Inc. +- * +- * Author: Robert Nelson +- */ +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-rex.dtsi" +- +-/ { +- model = "Rex Basic i.MX6 Dual Lite Board"; +- compatible = "rex,imx6dl-rex-basic", "fsl,imx6dl"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +-}; +- +-&ecspi3 { +- flash: m25p80@0 { +- compatible = "sst,sst25vf016b", "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-riotboard.dts b/scripts/dtc/include-prefixes/arm/imx6dl-riotboard.dts +deleted file mode 100644 +index e7d9bfbfd0e4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-riotboard.dts ++++ /dev/null +@@ -1,596 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright 2014 Iain Paton +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include +- +-/ { +- model = "RIoTboard i.MX6S"; +- compatible = "riot,imx6s-riotboard", "fsl,imx6dl"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- chosen { +- stdout-path = "serial1:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led>; +- +- led0: user1 { +- label = "user1"; +- gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led1: user2 { +- label = "user2"; +- gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- sound { +- compatible = "fsl,imx-audio-sgtl5000"; +- model = "imx6-riotboard-sgtl5000"; +- ssi-controller = <&ssi1>; +- audio-codec = <&codec>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <3>; +- }; +- +- reg_2p5v: regulator-2p5v { +- compatible = "regulator-fixed"; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_usb_otg_vbus: regulator-usbotgvbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&clks { +- fsl,pmic-stby-poweroff; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-handle = <&rgmii_phy>; +- interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, +- <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; +- fsl,err006687-workaround-present; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Atheros AR8035 PHY */ +- rgmii_phy: ethernet-phy@4 { +- reg = <4>; +- interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- reset-deassert-us = <1000>; +- qca,smarteee-tw-us-1g = <24>; +- qca,clk-out-frequency = <125000000>; +- }; +- }; +-}; +- +-&gpio1 { +- gpio-line-names = +- "", "", "SD2_WP", "", "SD2_CD", "I2C3_SCL", +- "I2C3_SDA", "I2C4_SCL", +- "I2C4_SDA", "", "", "", "", "", "", "", +- "", "PWM3", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio3 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "USB_OTG_VBUS", "", +- "UART3_TXD", "UART3_RXD", "", "", "EIM_D28", "", "", ""; +-}; +- +-&gpio4 { +- gpio-line-names = +- "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", +- "UART5_TXD", "UART5_RXD", "", "", "", "", "", "", +- "GPIO4_16", "GPIO4_17", "GPIO4_18", "GPIO4_19", "", +- "CSPI3_CLK", "CSPI3_MOSI", "CSPI3_MISO", +- "CSPI3_CS0", "CSPI3_CS1", "GPIO4_26", "GPIO4_27", +- "CSPI3_RDY", "PWM1", "PWM2", "GPIO4_31"; +-}; +- +-&gpio5 { +- gpio-line-names = +- "", "", "EIM_A25", "", "", "GPIO5_05", "GPIO5_06", +- "GPIO5_07", +- "GPIO5_08", "CSPI2_CS1", "CSPI2_MOSI", "CSPI2_MISO", +- "CSPI2_CS0", "CSPI2_CLK", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio7 { +- gpio-line-names = +- "SD3_CD", "SD3_WP", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- codec: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_3p3v>; +- }; +- +- pmic: pf0100@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- interrupt-parent = <&gpio5>; +- interrupts = <16 8>; +- fsl,pmic-stby-poweroff; +- +- regulators { +- reg_vddcore: sw1ab { /* VDDARM_IN */ +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-always-on; +- }; +- +- reg_vddsoc: sw1c { /* VDDSOC_IN */ +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-always-on; +- }; +- +- reg_gen_3v3: sw2 { /* VDDHIGH_IN */ +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_ddr_1v5a: sw3a { /* NVCC_DRAM, NVCC_RGMII */ +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-always-on; +- }; +- +- reg_ddr_1v5b: sw3b { /* NVCC_DRAM, NVCC_RGMII */ +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-always-on; +- }; +- +- reg_ddr_vtt: sw4 { /* MIPI conn */ +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-always-on; +- }; +- +- reg_5v_600mA: swbst { /* not used */ +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- reg_snvs_3v: vsnvs { /* VDD_SNVS_IN */ +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { /* VREF_DDR */ +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_vgen1_1v5: vgen1 { /* not used */ +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- reg_vgen2_1v2_eth: vgen2 { /* pcie ? */ +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- regulator-always-on; +- }; +- +- reg_vgen3_2v8: vgen3 { /* not used */ +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- reg_vgen4_1v8: vgen4 { /* NVCC_SD3 */ +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_vgen5_2v5_sgtl: vgen5 { /* Pwr LED & 5V0_delayed enable */ +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_vgen6_3v3: vgen6 { /* #V#_DELAYED enable, MIPI */ +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c4 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- clocks = <&clks 116>; +- status = "okay"; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- status = "okay"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "okay"; +-}; +- +-&pwm4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbh1 { +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- vmmc-supply = <®_3p3v>; +- non-removable; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- +- imx6-riotboard { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */ +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */ +- MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 +- MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 +- MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */ +- MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 +- >; +- }; +- +- pinctrl_ecspi3: ecspi3grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 +- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 +- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 +- MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */ +- MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */ +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: IO voltage: pull up */ +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#0: pull down */ +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */ +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#1: pull up */ +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */ +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */ +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */ +- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_led: ledgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */ +- MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */ +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */ +- MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */ +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */ +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */ +- MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */ +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +- MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */ +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-sabreauto.dts b/scripts/dtc/include-prefixes/arm/imx6dl-sabreauto.dts +deleted file mode 100644 +index ff3283c83a39..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-sabreauto.dts ++++ /dev/null +@@ -1,28 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright (C) 2013 Freescale Semiconductor, Inc. +- +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-sabreauto.dtsi" +- +-/ { +- model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board"; +- compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; +-}; +- +-&cpu0 { +- operating-points = < +- /* kHz uV */ +- 996000 1275000 +- 792000 1175000 +- 396000 1150000 +- >; +- fsl,soc-operating-points = < +- /* ARM kHz SOC-PU uV */ +- 996000 1200000 +- 792000 1175000 +- 396000 1175000 +- >; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-sabrelite.dts b/scripts/dtc/include-prefixes/arm/imx6dl-sabrelite.dts +deleted file mode 100644 +index 33040761b253..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-sabrelite.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-/* +- * Copyright 2011 Freescale Semiconductor, Inc. +- * Copyright 2011 Linaro Ltd. +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-sabrelite.dtsi" +- +-/ { +- model = "Freescale i.MX6 DualLite SABRE Lite Board"; +- compatible = "fsl,imx6dl-sabrelite", "fsl,imx6dl"; +-}; +- +-&ipu1_csi1_from_ipu1_csi1_mux { +- clock-lanes = <0>; +- data-lanes = <1 2>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-sabresd.dts b/scripts/dtc/include-prefixes/arm/imx6dl-sabresd.dts +deleted file mode 100644 +index cd6bbf22a16f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-sabresd.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright (C) 2013 Freescale Semiconductor, Inc. +- +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-sabresd.dtsi" +- +-/ { +- model = "Freescale i.MX6 DualLite SABRE Smart Device Board"; +- compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; +-}; +- +-&ipu1_csi1_from_ipu1_csi1_mux { +- clock-lanes = <0>; +- data-lanes = <1 2>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-savageboard.dts b/scripts/dtc/include-prefixes/arm/imx6dl-savageboard.dts +deleted file mode 100644 +index b95469c520a4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-savageboard.dts ++++ /dev/null +@@ -1,51 +0,0 @@ +-/* +- * Copyright (C) 2017 Milo Kim +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-savageboard.dtsi" +- +-/ { +- model = "Poslab SavageBoard Dual"; +- compatible = "poslab,imx6dl-savageboard", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-skov-revc-lt2.dts b/scripts/dtc/include-prefixes/arm/imx6dl-skov-revc-lt2.dts +deleted file mode 100644 +index 667b8faa1807..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-skov-revc-lt2.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright (C) 2020 Pengutronix, Ulrich Oelmann +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-skov-cpu.dtsi" +-#include "imx6qdl-skov-cpu-revc.dtsi" +- +-/ { +- model = "SKOV IMX6 CPU SoloCore"; +- compatible = "skov,imx6dl-skov-revc-lt2", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-skov-revc-lt6.dts b/scripts/dtc/include-prefixes/arm/imx6dl-skov-revc-lt6.dts +deleted file mode 100644 +index 5dcc433fe2af..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-skov-revc-lt6.dts ++++ /dev/null +@@ -1,106 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright (C) 2020 Pengutronix, Ulrich Oelmann +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-skov-cpu.dtsi" +-#include "imx6qdl-skov-cpu-revc.dtsi" +- +-/ { +- model = "SKOV IMX6 CPU SoloCore"; +- compatible = "skov,imx6dl-skov-revc-lt6", "fsl,imx6dl"; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_backlight>; +- enable-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; +- pwms = <&pwm2 0 20000 0>; +- brightness-levels = <0 255>; +- num-interpolated-steps = <17>; +- default-brightness-level = <8>; +- power-supply = <®_24v0>; +- }; +- +- display { +- compatible = "fsl,imx-parallel-display"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- display0_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- display0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +- +- panel { +- compatible = "logictechno,lttd800480070-l6wh-rt"; +- backlight = <&backlight>; +- power-supply = <®_3v3>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display0_out>; +- }; +- }; +- }; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&display0_in>; +-}; +- +-&iomuxc { +- pinctrl_backlight: backlightgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x58 +- >; +- }; +- +- pinctrl_ipu1: ipu1grp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-solidsense.dts b/scripts/dtc/include-prefixes/arm/imx6dl-solidsense.dts +deleted file mode 100644 +index 2a3699adbed0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-solidsense.dts ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* +- * Copyright (C) 2015 Rabeeh Khoury +- * Based on dt work by Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-emmc.dtsi" +-#include "imx6qdl-sr-som-ti.dtsi" +-#include "imx6qdl-hummingboard2.dtsi" +-#include "imx6qdl-solidsense.dtsi" +- +-/ { +- model = "SolidRun SolidSense Solo/DualLite (1.5som+emmc)"; +- compatible = "solidrun,solidsense/dl", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-tqma6a.dtsi b/scripts/dtc/include-prefixes/arm/imx6dl-tqma6a.dtsi +deleted file mode 100644 +index e891ef9b0091..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-tqma6a.dtsi ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Sascha Hauer, Pengutronix +- * Copyright 2013-2017 Markus Niebel +- */ +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-tqma6a.dtsi" +-#include "imx6qdl-tqma6.dtsi" +- +-/ { +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-tqma6b.dtsi b/scripts/dtc/include-prefixes/arm/imx6dl-tqma6b.dtsi +deleted file mode 100644 +index 38cd8501a886..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-tqma6b.dtsi ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Sascha Hauer, Pengutronix +- * Copyright 2013-2017 Markus Niebel +- */ +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-tqma6b.dtsi" +-#include "imx6qdl-tqma6.dtsi" +- +-/ { +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-ts4900.dts b/scripts/dtc/include-prefixes/arm/imx6dl-ts4900.dts +deleted file mode 100644 +index 3d60cc725d9e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-ts4900.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-/* +- * Copyright 2015 Technologic Systems +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-ts4900.dtsi" +- +-/ { +- model = "Technologic Systems i.MX6 Solo/DualLite TS-4900 (Default Device Tree)"; +- compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"; +- +- /* Will be filled by the bootloader */ +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-ts7970.dts b/scripts/dtc/include-prefixes/arm/imx6dl-ts7970.dts +deleted file mode 100644 +index 5da6feba2e66..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-ts7970.dts ++++ /dev/null +@@ -1,56 +0,0 @@ +-/* +- * Copyright 2015 Technologic Systems +- * Copyright 2017 Savoir-faire Linux +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-ts7970.dtsi" +- +-/ { +- model = "Technologic Systems i.MX6 Solo/DualLite TS-7970 (Default Device Tree)"; +- compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl"; +- +- /* Will be filled by the bootloader */ +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-tx6dl-comtft.dts b/scripts/dtc/include-prefixes/arm/imx6dl-tx6dl-comtft.dts +deleted file mode 100644 +index 51a9bb9d6bc2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-tx6dl-comtft.dts ++++ /dev/null +@@ -1,79 +0,0 @@ +-/* +- * Copyright 2014-2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-tx6.dtsi" +-#include "imx6qdl-tx6-lcd.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6DL Module on CoMpact TFT"; +- compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; +-}; +- +-&backlight { +- pwms = <&pwm2 0 500000 0>; +- /delete-property/ turn-on-delay-ms; +-}; +- +-&can1 { +- status = "disabled"; +-}; +- +-&can2 { +- xceiver-supply = <®_3v3>; +-}; +- +-&kpp { +- status = "disabled"; +-}; +- +-&lcd_panel { +- compatible = "edt,etm0700g0edh6"; +-}; +- +-®_can_xcvr { +- status = "disabled"; +-}; +- +-&touchscreen { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-tx6s-8034-mb7.dts b/scripts/dtc/include-prefixes/arm/imx6dl-tx6s-8034-mb7.dts +deleted file mode 100644 +index fc23b4d291a1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-tx6s-8034-mb7.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* +- * Copyright 2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6dl-tx6s-8034.dts" +-#include "imx6qdl-tx6-mb7.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6S-8034 Module on MB7 baseboard"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-tx6s-8034.dts b/scripts/dtc/include-prefixes/arm/imx6dl-tx6s-8034.dts +deleted file mode 100644 +index 9eb2ef17339c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-tx6s-8034.dts ++++ /dev/null +@@ -1,70 +0,0 @@ +-/* +- * Copyright 2015-2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-tx6.dtsi" +-#include "imx6qdl-tx6-lcd.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6S-8034 Module"; +- compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; +- +- cpus { +- /delete-node/ cpu@1; +- }; +-}; +- +-&ds1339 { +- status = "disabled"; +-}; +- +-&pinctrl_usdhc1 { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1 +- MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ +- >; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-tx6s-8035-mb7.dts b/scripts/dtc/include-prefixes/arm/imx6dl-tx6s-8035-mb7.dts +deleted file mode 100644 +index 4101c6597721..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-tx6s-8035-mb7.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* +- * Copyright 2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6dl-tx6s-8035.dts" +-#include "imx6qdl-tx6-mb7.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6U-8035 Module on MB7 baseboard"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-tx6s-8035.dts b/scripts/dtc/include-prefixes/arm/imx6dl-tx6s-8035.dts +deleted file mode 100644 +index a5532ecc18c5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-tx6s-8035.dts ++++ /dev/null +@@ -1,86 +0,0 @@ +-/* +- * Copyright 2015-2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-tx6.dtsi" +-#include "imx6qdl-tx6-lcd.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6S-8035 Module"; +- compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; +- +- cpus { +- /delete-node/ cpu@1; +- }; +-}; +- +-&ds1339 { +- status = "disabled"; +-}; +- +-&gpmi { +- status = "disabled"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <4>; +- non-removable; +- no-1-8-v; +- fsl,wp-controller; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 +- MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-tx6u-801x.dts b/scripts/dtc/include-prefixes/arm/imx6dl-tx6u-801x.dts +deleted file mode 100644 +index 67ed0452f5de..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-tx6u-801x.dts ++++ /dev/null +@@ -1,50 +0,0 @@ +-/* +- * Copyright 2014-2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-tx6.dtsi" +-#include "imx6qdl-tx6-lcd.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6U-801x Module"; +- compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-tx6u-8033-mb7.dts b/scripts/dtc/include-prefixes/arm/imx6dl-tx6u-8033-mb7.dts +deleted file mode 100644 +index d34189fc52d9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-tx6u-8033-mb7.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* +- * Copyright 2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6dl-tx6u-8033.dts" +-#include "imx6qdl-tx6-mb7.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6U-8033 Module on MB7 baseboard"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-tx6u-8033.dts b/scripts/dtc/include-prefixes/arm/imx6dl-tx6u-8033.dts +deleted file mode 100644 +index 7030b2654bbd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-tx6u-8033.dts ++++ /dev/null +@@ -1,82 +0,0 @@ +-/* +- * Copyright 2014-2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-tx6.dtsi" +-#include "imx6qdl-tx6-lcd.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6U-8033 Module"; +- compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; +-}; +- +-&ds1339 { +- status = "disabled"; +-}; +- +-&gpmi { +- status = "disabled"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <4>; +- non-removable; +- no-1-8-v; +- fsl,wp-controller; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 +- MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-tx6u-80xx-mb7.dts b/scripts/dtc/include-prefixes/arm/imx6dl-tx6u-80xx-mb7.dts +deleted file mode 100644 +index aef5fcc42904..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-tx6u-80xx-mb7.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* +- * Copyright 2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6dl-tx6u-801x.dts" +-#include "imx6qdl-tx6-mb7.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6U-8030/-8010/-8012 Module on MB7 baseboard"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-tx6u-811x.dts b/scripts/dtc/include-prefixes/arm/imx6dl-tx6u-811x.dts +deleted file mode 100644 +index 5342f2f5a8a8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-tx6u-811x.dts ++++ /dev/null +@@ -1,50 +0,0 @@ +-/* +- * Copyright 2014-2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-tx6.dtsi" +-#include "imx6qdl-tx6-lvds.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6U-811x Module"; +- compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-tx6u-81xx-mb7.dts b/scripts/dtc/include-prefixes/arm/imx6dl-tx6u-81xx-mb7.dts +deleted file mode 100644 +index c4588fb0bf6f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-tx6u-81xx-mb7.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* +- * Copyright 2016-2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6dl-tx6u-811x.dts" +-#include "imx6qdl-tx6-mb7.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6U-8130/-8110 Module on MB7 baseboard"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-udoo.dts b/scripts/dtc/include-prefixes/arm/imx6dl-udoo.dts +deleted file mode 100644 +index d871cac1711f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-udoo.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- * +- * Author: Fabio Estevam +- */ +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-udoo.dtsi" +- +-/ { +- model = "Udoo i.MX6 Dual-lite Board"; +- compatible = "udoo,imx6dl-udoo", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-victgo.dts b/scripts/dtc/include-prefixes/arm/imx6dl-victgo.dts +deleted file mode 100644 +index d37ba4ed847d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-victgo.dts ++++ /dev/null +@@ -1,852 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (c) 2016 Protonic Holland +- * Copyright (c) 2020 Oleksij Rempel , Pengutronix +- */ +- +-/dts-v1/; +-#include +-#include +-#include +-#include +-#include +-#include +-#include "imx6dl.dtsi" +- +-/ { +- model = "Kverneland TGO"; +- compatible = "kvg,victgo", "fsl,imx6dl"; +- +- chosen { +- stdout-path = &uart4; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_backlight>; +- pwms = <&pwm1 0 5000000 0>; +- brightness-levels = <0 16 64 255>; +- num-interpolated-steps = <16>; +- default-brightness-level = <1>; +- power-supply = <®_3v3>; +- enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; +- }; +- +- connector { +- compatible = "composite-video-connector"; +- label = "Composite0"; +- sdtv-standards = ; +- +- port { +- comp0_out: endpoint { +- remote-endpoint = <&tvp5150_comp0_in>; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpiokeys>; +- autorepeat; +- +- power { +- label = "Power Button"; +- gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- enter { +- label = "Rotary Key"; +- gpios = <&gpio2 05 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds>; +- +- led-0 { +- label = "debug0"; +- function = LED_FUNCTION_HEARTBEAT; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-1 { +- label = "debug1"; +- function = LED_FUNCTION_DISK; +- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "disk-activity"; +- }; +- +- led-2 { +- label = "power_led"; +- function = LED_FUNCTION_POWER; +- gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- panel { +- compatible = "kyo,tcg121xglp"; +- backlight = <&backlight>; +- power-supply = <®_3v3>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +- +- clk50m_phy: phy-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- }; +- +- reg_1v8: regulator-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_h1_vbus: regulator-h1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "h1-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_otg_vbus: regulator-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "otg-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- rotary-encoder { +- compatible = "rotary-encoder"; +- pinctrl-0 = <&pinctrl_rotary_ch>; +- gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>, +- <&gpio2 4 GPIO_ACTIVE_HIGH>; +- linux,axis = ; +- rotary-encoder,steps-per-period = <4>; +- rotary-encoder,relative-axis; +- rotary-encoder,rollover; +- wakeup-source; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "prti6q-sgtl5000"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,widgets = +- "Microphone", "Microphone Jack", +- "Line", "Line In Jack", +- "Headphone", "Headphone Jack", +- "Speaker", "External Speaker"; +- simple-audio-card,routing = +- "MIC_IN", "Microphone Jack", +- "LINE_IN", "Line In Jack", +- "Headphone Jack", "HP_OUT", +- "External Speaker", "LINE_OUT"; +- +- simple-audio-card,cpu { +- sound-dai = <&ssi1>; +- system-clock-frequency = <0>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&codec>; +- bitclock-master; +- frame-master; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +- +- mux-ssi1 { +- fsl,audmux-port = <0>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN 0 +- IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 +- IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 +- IMX_AUDMUX_V2_PTCR_TFSDIR 0 +- IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) +- >; +- }; +- +- mux-pins3 { +- fsl,audmux-port = <2>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) +- 0 IMX_AUDMUX_V2_PDCR_TXRXEN +- >; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can2>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- }; +-}; +- +-&ecspi2 { +- cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- status = "okay"; +- +- touchscreen@0 { +- compatible = "ti,tsc2046"; +- reg = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_touchscreen>; +- spi-max-frequency = <200000>; +- interrupts-extended = <&gpio5 8 IRQ_TYPE_EDGE_FALLING>; +- pendown-gpio = <&gpio5 8 GPIO_ACTIVE_LOW>; +- touchscreen-size-x = <800>; +- touchscreen-size-y = <480>; +- touchscreen-inverted-y; +- touchscreen-max-pressure = <4095>; +- ti,vref-delay-usecs = /bits/ 16 <100>; +- ti,x-plate-ohms = /bits/ 16 <800>; +- ti,y-plate-ohms = /bits/ 16 <300>; +- wakeup-source; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rmii"; +- clocks = <&clks IMX6QDL_CLK_ENET>, +- <&clks IMX6QDL_CLK_ENET>, +- <&clk50m_phy>; +- clock-names = "ipg", "ahb", "ptp"; +- phy-handle = <&rmii_phy>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Microchip KSZ8081RNA PHY */ +- rmii_phy: ethernet-phy@0 { +- reg = <0>; +- interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- reset-deassert-us = <300>; +- }; +- }; +-}; +- +-&gpio1 { +- gpio-line-names = +- "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", +- "CAM2_MIRROR", "", "", "SMBALERT", +- "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", +- "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", +- "SD1_DATA3", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio2 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4", +- "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", +- "", "", "", "", "", "", "ISB_IN1", "ON_SWITCH", +- "POWER_LED", "", "", "", "", "", "", ""; +-}; +- +-&gpio3 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", +- "CPU_ON1_FB", "USB_EXT1_OC", "USB_EXT1_PWR", "YACO_IRQ", +- "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", +- "YACO_RESET"; +-}; +- +-&gpio4 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "CAN1_SR", "CAN2_SR", "CAN2_TX", "CAN2_RX", +- "", "", "DIP1_FB", "", "VCAM_EN", "", "", "", +- "CPU_LIGHT_ON", "", "ETH_RESET", "CPU_CONTACT_IN", "BL_EN", +- "BL_PWM", "ETH_INTRP", "ISB_LED"; +-}; +- +-&gpio5 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "TSC_PENIRQ", "TSC_BUSY", "ECSPI2_MOSI", "ECSPI2_MISO", +- "ECSPI2_SS0", "ECSPI2_SCLK", "", "", +- "", "", "", "", "", "", "", "", +- "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", +- "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- codec: audio-codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0xa>; +- #sound-dai-cells = <0>; +- clocks = <&clks 201>; +- VDDA-supply = <®_3v3>; +- VDDIO-supply = <®_3v3>; +- VDDD-supply = <®_1v8>; +- }; +- +- video-decoder@5c { +- compatible = "ti,tvp5150"; +- reg = <0x5c>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tvp5150_comp0_in: endpoint { +- remote-endpoint = <&comp0_out>; +- }; +- }; +- +- /* Output port 2 is video output pad */ +- port@2 { +- reg = <2>; +- +- tvp5151_to_ipu1_csi0_mux: endpoint { +- remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; +- }; +- }; +- }; +- +- keypad@70 { +- compatible = "holtek,ht16k33"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_keypad>; +- reg = <0x70>; +- refresh-rate-hz = <20>; +- debounce-delay-ms = <50>; +- interrupts-extended = <&gpio4 5 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; +- keypad,num-rows = <12>; +- keypad,num-columns = <3>; +- linux,keymap = < +- MATRIX_KEY(2, 0, KEY_F6) +- MATRIX_KEY(3, 0, KEY_F8) +- MATRIX_KEY(4, 0, KEY_F10) +- MATRIX_KEY(5, 0, KEY_F4) +- MATRIX_KEY(6, 0, KEY_F2) +- MATRIX_KEY(2, 1, KEY_F5) +- MATRIX_KEY(3, 1, KEY_F7) +- MATRIX_KEY(4, 1, KEY_F9) +- MATRIX_KEY(5, 1, KEY_F3) +- MATRIX_KEY(6, 1, KEY_F1) +- >; +- }; +- +- /* additional i2c devices are added automatically by the boot loader */ +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- adc@49 { +- compatible = "ti,ads1015"; +- reg = <0x49>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@4 { +- reg = <4>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- +- channel@5 { +- reg = <5>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- +- channel@6 { +- reg = <6>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- +- channel@7 { +- reg = <7>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- }; +- +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- +- temperature-sensor@70 { +- compatible = "ti,tmp103"; +- reg = <0x70>; +- }; +-}; +- +-&ipu1_csi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_csi0>; +- status = "okay"; +-}; +- +-&ipu1_csi0_mux_from_parallel_sensor { +- remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "okay"; +-}; +- +-&ssi1 { +- #sound-dai-cells = <0>; +- fsl,mode = "ac97-slave"; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_h1_vbus>; +- pinctrl-names = "default"; +- phy_type = "utmi"; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- phy_type = "utmi"; +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- disable-wp; +- cap-sd-highspeed; +- no-mmc; +- no-sdio; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- no-sd; +- no-sdio; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- /* SGTL5000 sys_mclk */ +- MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- >; +- }; +- +- pinctrl_backlight: backlightgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 +- >; +- }; +- +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 +- /* CAN1_SR */ +- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 +- /* CAN1_TERM */ +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 +- >; +- }; +- +- pinctrl_can2: can2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 +- /* CAN2_SR */ +- MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- /* CS */ +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 +- MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 +- MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 +- MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- /* MX6QDL_ENET_PINGRP4 */ +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 +- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 +- /* Phy reset */ +- MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 +- /* nINTRP */ +- MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 +- >; +- }; +- +- pinctrl_gpiokeys: gpiokeygrp { +- fsl,pins = < +- /* ROTARY_BTN */ +- MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b0 +- /* nON_SWITCH */ +- MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 +- >; +- }; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- /* ITU656_nRESET */ +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +- /* CAM1_MIRROR */ +- MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 +- /* CAM2_MIRROR */ +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 +- /* CAM_nDETECT */ +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 +- /* ISB_IN1 */ +- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 +- /* ISB_nIN2 */ +- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 +- /* WARN_LIGHT */ +- MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0 +- /* ON2_FB */ +- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 +- /* YACO_nIRQ */ +- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 +- /* YACO_BOOT0 */ +- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 +- /* YACO_nRESET */ +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 +- /* FORCE_ON1 */ +- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +- /* AUDIO_nRESET */ +- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 +- /* ITU656_nPDN */ +- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 +- +- /* HW revision detect */ +- /* REV_ID0 */ +- MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 +- /* REV_ID1 is shared with PWM3 */ +- /* REV_ID2 */ +- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 +- /* REV_ID3 */ +- MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 +- /* REV_ID4 */ +- MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 +- +- /* New in HW revision 1 */ +- /* ON1_FB */ +- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 +- /* DIP1_FB */ +- MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_ipu1_csi0: ipu1csi0grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 +- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 +- >; +- }; +- +- pinctrl_keypad: keypadgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 +- >; +- }; +- +- pinctrl_leds: ledsgrp { +- fsl,pins = < +- /* DEBUG0 */ +- MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 +- /* DEBUG1 */ +- MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 +- /* POWER_LED */ +- MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 +- >; +- }; +- +- pinctrl_rotary_ch: rotarychgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 +- MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 +- >; +- }; +- +- pinctrl_touchscreen: touchscreengrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0 +- MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 +- >; +- }; +- +- /* YaCO AUX Uart */ +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- /* YaCO Touchscreen UART */ +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 +- /* power enable, high active */ +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 +- MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-vicut1.dts b/scripts/dtc/include-prefixes/arm/imx6dl-vicut1.dts +deleted file mode 100644 +index 174fd913bf96..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-vicut1.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (c) 2014 Protonic Holland +- */ +- +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-vicut1.dtsi" +- +-/ { +- model = "Kverneland UT1 Board"; +- compatible = "kvg,vicut1", "fsl,imx6dl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-wandboard-revb1.dts b/scripts/dtc/include-prefixes/arm/imx6dl-wandboard-revb1.dts +deleted file mode 100644 +index c2946fbaa0dd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-wandboard-revb1.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- * +- * Author: Fabio Estevam +- */ +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-wandboard-revb1.dtsi" +- +-/ { +- model = "Wandboard i.MX6 Dual Lite Board rev B1"; +- compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-wandboard-revd1.dts b/scripts/dtc/include-prefixes/arm/imx6dl-wandboard-revd1.dts +deleted file mode 100644 +index 6d1d863c2e3a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-wandboard-revd1.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- * +- * Author: Fabio Estevam +- */ +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-wandboard-revd1.dtsi" +- +-/ { +- model = "Wandboard i.MX6 Dual Lite Board revD1"; +- compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-wandboard.dts b/scripts/dtc/include-prefixes/arm/imx6dl-wandboard.dts +deleted file mode 100644 +index 4a08d5a99452..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-wandboard.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- * +- * Author: Fabio Estevam +- */ +-/dts-v1/; +-#include "imx6dl.dtsi" +-#include "imx6qdl-wandboard-revc1.dtsi" +- +-/ { +- model = "Wandboard i.MX6 Dual Lite Board"; +- compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-yapp4-common.dtsi b/scripts/dtc/include-prefixes/arm/imx6dl-yapp4-common.dtsi +deleted file mode 100644 +index e5c4dc65fbab..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-yapp4-common.dtsi ++++ /dev/null +@@ -1,658 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright (C) 2015-2018 Y Soft Corporation, a.s. +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- aliases: aliases { +- ethernet1 = ð1; +- ethernet2 = ð2; +- mmc0 = &usdhc3; +- mmc1 = &usdhc4; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; +- brightness-levels = <0 32 64 128 255>; +- default-brightness-level = <32>; +- num-interpolated-steps = <8>; +- power-supply = <&sw2_reg>; +- status = "disabled"; +- }; +- +- lcd_display: display { +- compatible = "fsl,imx-parallel-display"; +- #address-cells = <1>; +- #size-cells = <0>; +- interface-pix-fmt = "rgb24"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1>; +- status = "disabled"; +- +- port@0 { +- reg = <0>; +- +- lcd_display_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lcd_display_out: endpoint { +- remote-endpoint = <&lcd_panel_in>; +- }; +- }; +- }; +- +- panel: panel { +- compatible = "dataimage,scf0700c48ggu18"; +- power-supply = <&sw2_reg>; +- status = "disabled"; +- +- port { +- lcd_panel_in: endpoint { +- remote-endpoint = <&lcd_display_out>; +- }; +- }; +- }; +- +- reg_pcie: regulator-pcie { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie_reg>; +- regulator-name = "MPCIE_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- status = "disabled"; +- }; +- +- reg_usb_h1_vbus: regulator-usb-h1-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1_vbus>; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- status = "disabled"; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg_vbus>; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- status = "okay"; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <20>; +- phy-supply = <&sw2_reg>; +- status = "okay"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy_port2: phy@1 { +- reg = <1>; +- }; +- +- phy_port3: phy@2 { +- reg = <2>; +- }; +- +- switch@10 { +- compatible = "qca,qca8334"; +- reg = <10>; +- +- switch_ports: ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: port@0 { +- reg = <0>; +- label = "cpu"; +- phy-mode = "rgmii-id"; +- ethernet = <&fec>; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- eth2: port@2 { +- reg = <2>; +- label = "eth2"; +- phy-handle = <&phy_port2>; +- }; +- +- eth1: port@3 { +- reg = <3>; +- label = "eth1"; +- phy-handle = <&phy_port3>; +- }; +- }; +- }; +- }; +-}; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hdmi_cec>; +- ddc-i2c-bus = <&i2c2>; +- status = "disabled"; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- pmic@8 { +- compatible = "fsl,pfuze200"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- reg = <0x8>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vsnvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +- +- leds: led-controller@30 { +- compatible = "ti,lp5562"; +- reg = <0x30>; +- clock-mode = /bits/ 8 <1>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- chan@0 { +- chan-name = "R"; +- led-cur = /bits/ 8 <0x20>; +- max-cur = /bits/ 8 <0x60>; +- reg = <0>; +- color = ; +- }; +- +- chan@1 { +- chan-name = "G"; +- led-cur = /bits/ 8 <0x20>; +- max-cur = /bits/ 8 <0x60>; +- reg = <1>; +- color = ; +- }; +- +- chan@2 { +- chan-name = "B"; +- led-cur = /bits/ 8 <0x20>; +- max-cur = /bits/ 8 <0x60>; +- reg = <2>; +- color = ; +- }; +- +- chan@3 { +- chan-name = "W"; +- led-cur = /bits/ 8 <0x0>; +- max-cur = /bits/ 8 <0x0>; +- reg = <3>; +- color = ; +- }; +- }; +- +- eeprom@57 { +- compatible = "atmel,24c128"; +- reg = <0x57>; +- pagesize = <64>; +- status = "okay"; +- }; +- +- touchscreen: touchscreen@5c { +- compatible = "pixcir,pixcir_tangoc"; +- reg = <0x5c>; +- pinctrl-0 = <&pinctrl_touch>; +- interrupt-parent = <&gpio4>; +- interrupts = <5 IRQ_TYPE_EDGE_FALLING>; +- attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; +- reset-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- touchscreen-size-x = <800>; +- touchscreen-size-y = <480>; +- status = "disabled"; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- oled_1309: oled@3c { +- compatible = "solomon,ssd1309fb-i2c"; +- reg = <0x3c>; +- solomon,height = <64>; +- solomon,width = <128>; +- solomon,page-offset = <0>; +- solomon,segment-no-remap; +- solomon,prechargep2 = <15>; +- reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; +- vbat-supply = <&sw2_reg>; +- status = "disabled"; +- }; +- +- oled_1305: oled@3d { +- compatible = "solomon,ssd1305fb-i2c"; +- reg = <0x3d>; +- solomon,height = <64>; +- solomon,width = <128>; +- solomon,page-offset = <0>; +- solomon,col-offset = <4>; +- solomon,prechargep2 = <15>; +- reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; +- vbat-supply = <&sw2_reg>; +- status = "disabled"; +- }; +- +- gpio_oled: gpio@41 { +- compatible = "nxp,pca9536"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x41>; +- vcc-supply = <&sw2_reg>; +- status = "disabled"; +- }; +- +- touchkeys: keys@5a { +- compatible = "fsl,mpr121-touchkey"; +- reg = <0x5a>; +- vdd-supply = <&sw2_reg>; +- autorepeat; +- linux,keycodes = , , , , , +- , , , , +- , , ; +- poll-interval = <50>; +- status = "disabled"; +- }; +-}; +- +-&iomuxc { +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b020 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b020 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b020 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b020 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b020 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b020 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b020 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b020 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b020 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b020 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b020 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b020 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b020 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b010 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b010 +- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b098 +- >; +- }; +- +- pinctrl_hdmi_cec: hdmicecgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1b898 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b899 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899 +- >; +- }; +- +- pinctrl_ipu1: ipu1grp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b098 +- MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b098 +- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b098 +- >; +- }; +- +- pinctrl_pcie_reg: pciereggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b098 +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b098 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 +- >; +- }; +- +- pinctrl_touch: touchgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b098 +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b098 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0a8 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0a8 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b098 +- MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b098 +- >; +- }; +- +- pinctrl_usbh1: usbh1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b098 +- >; +- }; +- +- pinctrl_usbh1_vbus: usbh1-vbus { +- fsl,pins = < +- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x98 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b098 +- MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b098 +- >; +- }; +- +- pinctrl_usbotg_vbus: usbotg-vbus { +- fsl,pins = < +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x98 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b018 +- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b018 +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x1f069 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10069 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17069 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17069 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17069 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17069 +- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17069 +- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17069 +- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17069 +- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17069 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 +- >; +- }; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&lcd_display_in>; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; +- vpcie-supply = <®_pcie>; +- status = "disabled"; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "disabled"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usbh1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1>; +- vbus-supply = <®_usb_h1_vbus>; +- over-current-active-low; +- status = "disabled"; +-}; +- +-&usbotg { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- vbus-supply = <®_usb_otg_vbus>; +- over-current-active-low; +- srp-disable; +- hnp-disable; +- adp-disable; +- status = "okay"; +-}; +- +-&usbphy1 { +- fsl,tx-d-cal = <106>; +- status = "okay"; +-}; +- +-&usbphy2 { +- fsl,tx-d-cal = <109>; +- status = "disabled"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <4>; +- cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; +- no-1-8-v; +- keep-power-in-suspend; +- wakeup-source; +- vmmc-supply = <&sw2_reg>; +- status = "disabled"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <8>; +- non-removable; +- no-1-8-v; +- keep-power-in-suspend; +- vmmc-supply = <&sw2_reg>; +- status = "okay"; +-}; +- +-&wdog1 { +- status = "disabled"; +-}; +- +-&wdog2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-yapp4-draco.dts b/scripts/dtc/include-prefixes/arm/imx6dl-yapp4-draco.dts +deleted file mode 100644 +index a38c407fd837..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-yapp4-draco.dts ++++ /dev/null +@@ -1,58 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright (C) 2015-2018 Y Soft Corporation, a.s. +- +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6dl-yapp4-common.dtsi" +- +-/ { +- model = "Y Soft IOTA Draco i.MX6Solo board"; +- compatible = "ysoft,imx6dl-yapp4-draco", "fsl,imx6dl"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +-}; +- +-&backlight { +- status = "okay"; +-}; +- +-&lcd_display { +- status = "okay"; +-}; +- +-&leds { +- status = "okay"; +-}; +- +-&panel { +- status = "okay"; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-®_usb_h1_vbus { +- status = "okay"; +-}; +- +-&touchscreen { +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbphy2 { +- status = "okay"; +-}; +- +-&usdhc3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-yapp4-hydra.dts b/scripts/dtc/include-prefixes/arm/imx6dl-yapp4-hydra.dts +deleted file mode 100644 +index a19609c7c7c0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-yapp4-hydra.dts ++++ /dev/null +@@ -1,54 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright (C) 2015-2018 Y Soft Corporation, a.s. +- +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6dl-yapp4-common.dtsi" +- +-/ { +- model = "Y Soft IOTA Hydra i.MX6DualLite board"; +- compatible = "ysoft,imx6dl-yapp4-hydra", "fsl,imx6dl"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +-}; +- +-&gpio_oled { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&leds { +- status = "okay"; +-}; +- +-&oled_1305 { +- status = "okay"; +-}; +- +-&oled_1309 { +- status = "okay"; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-®_pcie { +- status = "okay"; +-}; +- +-&touchkeys { +- status = "okay"; +-}; +- +-&usdhc3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-yapp4-orion.dts b/scripts/dtc/include-prefixes/arm/imx6dl-yapp4-orion.dts +deleted file mode 100644 +index 884b236746bb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-yapp4-orion.dts ++++ /dev/null +@@ -1,54 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright (C) 2020 Y Soft Corporation, a.s. +- +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6dl-yapp4-common.dtsi" +- +-/ { +- model = "Y Soft IOTA Orion i.MX6DualLite board"; +- compatible = "ysoft,imx6dl-yapp4-orion", "fsl,imx6dl"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0xf0000000>; +- }; +-}; +- +-&gpio_oled { +- status = "okay"; +-}; +- +-&leds { +- status = "okay"; +-}; +- +-&oled_1305 { +- status = "okay"; +-}; +- +-&oled_1309 { +- status = "okay"; +-}; +- +-®_usb_h1_vbus { +- status = "okay"; +-}; +- +-&touchkeys { +- status = "okay"; +-}; +- +-&uart2 { +- status = "disabled"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbphy2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl-yapp4-ursa.dts b/scripts/dtc/include-prefixes/arm/imx6dl-yapp4-ursa.dts +deleted file mode 100644 +index f6ae24efd4aa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl-yapp4-ursa.dts ++++ /dev/null +@@ -1,58 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright (C) 2015-2018 Y Soft Corporation, a.s. +- +-/dts-v1/; +- +-#include "imx6dl.dtsi" +-#include "imx6dl-yapp4-common.dtsi" +- +-/ { +- model = "Y Soft IOTA Ursa i.MX6Solo board"; +- compatible = "ysoft,imx6dl-yapp4-ursa", "fsl,imx6dl"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +-}; +- +-&aliases { +- /delete-property/ ethernet1; +-}; +- +-&backlight { +- status = "okay"; +-}; +- +-&lcd_display { +- status = "okay"; +-}; +- +-&panel { +- status = "okay"; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-®_usb_h1_vbus { +- status = "okay"; +-}; +- +-&switch_ports { +- /delete-node/ port@3; +-}; +- +-&touchscreen { +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbphy2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6dl.dtsi b/scripts/dtc/include-prefixes/arm/imx6dl.dtsi +deleted file mode 100644 +index fdd81fdc3f35..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6dl.dtsi ++++ /dev/null +@@ -1,394 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright 2013 Freescale Semiconductor, Inc. +- +-#include +-#include "imx6dl-pinfunc.h" +-#include "imx6qdl.dtsi" +- +-/ { +- aliases { +- i2c3 = &i2c4; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <0>; +- next-level-cache = <&L2>; +- operating-points = < +- /* kHz uV */ +- 996000 1250000 +- 792000 1175000 +- 396000 1150000 +- >; +- fsl,soc-operating-points = < +- /* ARM kHz SOC-PU uV */ +- 996000 1175000 +- 792000 1175000 +- 396000 1175000 +- >; +- clock-latency = <61036>; /* two CLK32 periods */ +- #cooling-cells = <2>; +- clocks = <&clks IMX6QDL_CLK_ARM>, +- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, +- <&clks IMX6QDL_CLK_STEP>, +- <&clks IMX6QDL_CLK_PLL1_SW>, +- <&clks IMX6QDL_CLK_PLL1_SYS>; +- clock-names = "arm", "pll2_pfd2_396m", "step", +- "pll1_sw", "pll1_sys"; +- arm-supply = <®_arm>; +- pu-supply = <®_pu>; +- soc-supply = <®_soc>; +- nvmem-cells = <&cpu_speed_grade>; +- nvmem-cell-names = "speed_grade"; +- }; +- +- cpu@1 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <1>; +- next-level-cache = <&L2>; +- operating-points = < +- /* kHz uV */ +- 996000 1250000 +- 792000 1175000 +- 396000 1150000 +- >; +- fsl,soc-operating-points = < +- /* ARM kHz SOC-PU uV */ +- 996000 1175000 +- 792000 1175000 +- 396000 1175000 +- >; +- clock-latency = <61036>; /* two CLK32 periods */ +- #cooling-cells = <2>; +- clocks = <&clks IMX6QDL_CLK_ARM>, +- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, +- <&clks IMX6QDL_CLK_STEP>, +- <&clks IMX6QDL_CLK_PLL1_SW>, +- <&clks IMX6QDL_CLK_PLL1_SYS>; +- clock-names = "arm", "pll2_pfd2_396m", "step", +- "pll1_sw", "pll1_sys"; +- arm-supply = <®_arm>; +- pu-supply = <®_pu>; +- soc-supply = <®_soc>; +- }; +- }; +- +- soc { +- ocram: sram@900000 { +- compatible = "mmio-sram"; +- reg = <0x00900000 0x20000>; +- clocks = <&clks IMX6QDL_CLK_OCRAM>; +- }; +- +- aips1: bus@2000000 { +- pxp: pxp@20f0000 { +- reg = <0x020f0000 0x4000>; +- interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- epdc: epdc@20f4000 { +- reg = <0x020f4000 0x4000>; +- interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; +- }; +- }; +- +- aips2: bus@2100000 { +- i2c4: i2c@21f8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; +- reg = <0x021f8000 0x4000>; +- interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6DL_CLK_I2C4>; +- status = "disabled"; +- }; +- }; +- }; +- +- capture-subsystem { +- compatible = "fsl,imx-capture-subsystem"; +- ports = <&ipu1_csi0>, <&ipu1_csi1>; +- }; +- +- display-subsystem { +- compatible = "fsl,imx-display-subsystem"; +- ports = <&ipu1_di0>, <&ipu1_di1>; +- }; +-}; +- +-&gpio1 { +- gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>, +- <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>, +- <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>, +- <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>, +- <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>, +- <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>, +- <&iomuxc 30 129 1>, <&iomuxc 31 122 1>; +-}; +- +-&gpio2 { +- gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>, +- <&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>, +- <&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>, +- <&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>, +- <&iomuxc 28 113 4>; +-}; +- +-&gpio3 { +- gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>, +- <&iomuxc 16 81 16>; +-}; +- +-&gpio4 { +- gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>, +- <&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>, +- <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>, +- <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>, +- <&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>; +-}; +- +-&gpio5 { +- gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>, +- <&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>, +- <&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>, +- <&iomuxc 22 29 6>, <&iomuxc 28 19 4>; +-}; +- +-&gpio6 { +- gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>, +- <&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>, +- <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>, +- <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>, +- <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>, +- <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>; +-}; +- +-&gpio7 { +- gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>, +- <&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>, +- <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>; +-}; +- +-&gpr { +- ipu1_csi0_mux { +- compatible = "video-mux"; +- mux-controls = <&mux 0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- ipu1_csi0_mux_from_mipi_vc0: endpoint { +- remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- ipu1_csi0_mux_from_mipi_vc1: endpoint { +- remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- +- ipu1_csi0_mux_from_mipi_vc2: endpoint { +- remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- +- ipu1_csi0_mux_from_mipi_vc3: endpoint { +- remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>; +- }; +- }; +- +- port@4 { +- reg = <4>; +- +- ipu1_csi0_mux_from_parallel_sensor: endpoint { +- }; +- }; +- +- port@5 { +- reg = <5>; +- +- ipu1_csi0_mux_to_ipu1_csi0: endpoint { +- remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>; +- }; +- }; +- }; +- +- ipu1_csi1_mux { +- compatible = "video-mux"; +- mux-controls = <&mux 1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- ipu1_csi1_mux_from_mipi_vc0: endpoint { +- remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- ipu1_csi1_mux_from_mipi_vc1: endpoint { +- remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- +- ipu1_csi1_mux_from_mipi_vc2: endpoint { +- remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- +- ipu1_csi1_mux_from_mipi_vc3: endpoint { +- remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>; +- }; +- }; +- +- port@4 { +- reg = <4>; +- +- ipu1_csi1_mux_from_parallel_sensor: endpoint { +- }; +- }; +- +- port@5 { +- reg = <5>; +- +- ipu1_csi1_mux_to_ipu1_csi1: endpoint { +- remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>; +- }; +- }; +- }; +-}; +- +-&gpt { +- compatible = "fsl,imx6dl-gpt"; +-}; +- +-&hdmi { +- compatible = "fsl,imx6dl-hdmi"; +-}; +- +-&iomuxc { +- compatible = "fsl,imx6dl-iomuxc"; +-}; +- +-&ipu1_csi1 { +- ipu1_csi1_from_ipu1_csi1_mux: endpoint { +- remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>; +- }; +-}; +- +-&ldb { +- clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, +- <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; +- clock-names = "di0_pll", "di1_pll", +- "di0_sel", "di1_sel", +- "di0", "di1"; +-}; +- +-&mipi_csi { +- port@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- mipi_vc0_to_ipu1_csi0_mux: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>; +- }; +- +- mipi_vc0_to_ipu1_csi1_mux: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- mipi_vc1_to_ipu1_csi0_mux: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>; +- }; +- +- mipi_vc1_to_ipu1_csi1_mux: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- mipi_vc2_to_ipu1_csi0_mux: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>; +- }; +- +- mipi_vc2_to_ipu1_csi1_mux: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>; +- }; +- }; +- +- port@4 { +- reg = <4>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- mipi_vc3_to_ipu1_csi0_mux: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>; +- }; +- +- mipi_vc3_to_ipu1_csi1_mux: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>; +- }; +- }; +-}; +- +-&mux { +- mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */ +- <0x34 0x00000038>, /* IPU_CSI1_MUX */ +- <0x0c 0x0000000c>, /* HDMI_MUX_CTL */ +- <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */ +- <0x0c 0x00000300>, /* LVDS1_MUX_CTL */ +- <0x28 0x00000003>, /* DCIC1_MUX_CTL */ +- <0x28 0x0000000c>; /* DCIC2_MUX_CTL */ +-}; +- +-&vpu { +- compatible = "fsl,imx6dl-vpu", "cnm,coda960"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-apalis-eval.dts b/scripts/dtc/include-prefixes/arm/imx6q-apalis-eval.dts +deleted file mode 100644 +index a0683b4aeca1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-apalis-eval.dts ++++ /dev/null +@@ -1,273 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2014-2020 Toradex +- * Copyright 2012 Freescale Semiconductor, Inc. +- * Copyright 2011 Linaro Ltd. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include "imx6q.dtsi" +-#include "imx6qdl-apalis.dtsi" +- +-/ { +- model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board"; +- compatible = "toradex,apalis_imx6q-eval", "toradex,apalis_imx6q", +- "fsl,imx6q"; +- +- aliases { +- i2c0 = &i2c1; +- i2c1 = &i2c3; +- i2c2 = &i2c2; +- rtc0 = &rtc_i2c; +- rtc1 = &snvs_rtc; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- wakeup { +- label = "Wake-Up"; +- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- lcd_display: disp0 { +- compatible = "fsl,imx-parallel-display"; +- #address-cells = <1>; +- #size-cells = <0>; +- interface-pix-fmt = "rgb24"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_lcdif>; +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- lcd_display_in: endpoint { +- remote-endpoint = <&ipu1_di1_disp1>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lcd_display_out: endpoint { +- remote-endpoint = <&lcd_panel_in>; +- }; +- }; +- }; +- +- panel: panel { +- /* +- * edt,et057090dhu: EDT 5.7" LCD TFT +- * edt,et070080dh6: EDT 7.0" LCD TFT +- */ +- compatible = "edt,et057090dhu"; +- backlight = <&backlight>; +- power-supply = <®_3v3_sw>; +- +- port { +- lcd_panel_in: endpoint { +- remote-endpoint = <&lcd_display_out>; +- }; +- }; +- }; +- +- reg_pcie_switch: regulator-pcie-switch { +- compatible = "regulator-fixed"; +- regulator-name = "pcie_switch"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <100000>; +- enable-active-high; +- status = "okay"; +- }; +- +- reg_3v3_sw: regulator-3v3-sw { +- compatible = "regulator-fixed"; +- regulator-name = "3.3V_SW"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +-}; +- +-&backlight { +- brightness-levels = <0 127 191 223 239 247 251 255>; +- default-brightness-level = <1>; +- power-supply = <®_3v3_sw>; +- status = "okay"; +-}; +- +-&can1 { +- xceiver-supply = <®_3v3_sw>; +- status = "okay"; +-}; +- +-&can2 { +- xceiver-supply = <®_3v3_sw>; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ +-&i2c1 { +- status = "okay"; +- +- /* +- * Touchscreen is using SODIMM 28/30, also used for PWM, PWM, +- * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms +- */ +- touchscreen@4a { +- compatible = "atmel,maxtouch"; +- reg = <0x4a>; +- interrupt-parent = <&gpio6>; +- interrupts = <10 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* SODIMM 13 */ +- status = "disabled"; +- }; +- +- pcie-switch@58 { +- compatible = "plx,pex8605"; +- reg = <0x58>; +- }; +- +- /* M41T0M6 real time clock on carrier board */ +- rtc_i2c: rtc@68 { +- compatible = "st,m41t0"; +- reg = <0x68>; +- }; +-}; +- +-/* +- * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier +- * board) +- */ +-&i2c3 { +- status = "okay"; +-}; +- +-&ipu1_di1_disp1 { +- remote-endpoint = <&lcd_display_in>; +-}; +- +-&ldb { +- status = "okay"; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reset_moci>; +- /* active-high meaning opposite of regular PERST# active-low polarity */ +- reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; +- reset-gpio-active-high; +- vpcie-supply = <®_pcie_switch>; +- status = "okay"; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&pwm3 { +- status = "okay"; +-}; +- +-&pwm4 { +- status = "okay"; +-}; +- +-®_usb_otg_vbus { +- status = "okay"; +-}; +- +-®_usb_host_vbus { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&sound_spdif { +- status = "okay"; +-}; +- +-&spdif { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart4 { +- status = "okay"; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_host_vbus>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- status = "okay"; +-}; +- +-/* MMC1 */ +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>; +- cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-/* SD1 */ +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; +- cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&iomuxc { +- /* +- * Mux the Apalis GPIOs +- */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 +- &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 +- &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 +- &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 +- >; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-apalis-ixora-v1.1.dts b/scripts/dtc/include-prefixes/arm/imx6q-apalis-ixora-v1.1.dts +deleted file mode 100644 +index 86e84781cf5d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-apalis-ixora-v1.1.dts ++++ /dev/null +@@ -1,274 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2014-2020 Toradex +- * Copyright 2012 Freescale Semiconductor, Inc. +- * Copyright 2011 Linaro Ltd. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include "imx6q.dtsi" +-#include "imx6qdl-apalis.dtsi" +- +-/ { +- model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.1"; +- compatible = "toradex,apalis_imx6q-ixora-v1.1", +- "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q", +- "fsl,imx6q"; +- +- aliases { +- i2c0 = &i2c1; +- i2c1 = &i2c3; +- i2c2 = &i2c2; +- rtc0 = &rtc_i2c; +- rtc1 = &snvs_rtc; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- wakeup { +- label = "Wake-Up"; +- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- lcd_display: disp0 { +- compatible = "fsl,imx-parallel-display"; +- #address-cells = <1>; +- #size-cells = <0>; +- interface-pix-fmt = "rgb24"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_lcdif>; +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- lcd_display_in: endpoint { +- remote-endpoint = <&ipu1_di1_disp1>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lcd_display_out: endpoint { +- remote-endpoint = <&lcd_panel_in>; +- }; +- }; +- }; +- +- panel: panel { +- /* +- * edt,et057090dhu: EDT 5.7" LCD TFT +- * edt,et070080dh6: EDT 7.0" LCD TFT +- */ +- compatible = "edt,et057090dhu"; +- backlight = <&backlight>; +- +- port { +- lcd_panel_in: endpoint { +- remote-endpoint = <&lcd_display_out>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds_ixora>; +- +- led4-green { +- label = "LED_4_GREEN"; +- gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; +- }; +- +- led4-red { +- label = "LED_4_RED"; +- gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; +- }; +- +- led5-green { +- label = "LED_5_GREEN"; +- gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; +- }; +- +- led5-red { +- label = "LED_5_RED"; +- gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&backlight { +- brightness-levels = <0 127 191 223 239 247 251 255>; +- default-brightness-level = <1>; +- status = "okay"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&can2 { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ +-&i2c1 { +- status = "okay"; +- +- /* +- * Touchscreen is using SODIMM 28/30, also used for PWM, PWM, +- * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms +- */ +- touchscreen@4a { +- compatible = "atmel,maxtouch"; +- reg = <0x4a>; +- interrupt-parent = <&gpio6>; +- interrupts = <10 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* SODIMM 13 */ +- status = "disabled"; +- }; +- +- /* M41T0M6 real time clock on carrier board */ +- rtc_i2c: rtc@68 { +- compatible = "st,m41t0"; +- reg = <0x68>; +- }; +-}; +- +-/* +- * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier +- * board) +- */ +-&i2c3 { +- status = "okay"; +-}; +- +-&ipu1_di1_disp1 { +- remote-endpoint = <&lcd_display_in>; +-}; +- +-&ldb { +- status = "okay"; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reset_moci>; +- /* active-high meaning opposite of regular PERST# active-low polarity */ +- reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; +- reset-gpio-active-high; +- status = "okay"; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&pwm3 { +- status = "okay"; +-}; +- +-&pwm4 { +- status = "okay"; +-}; +- +-®_usb_otg_vbus { +- status = "okay"; +-}; +- +-®_usb_host_vbus { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&sound_spdif { +- status = "okay"; +-}; +- +-&spdif { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart4 { +- status = "okay"; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_host_vbus>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- status = "okay"; +-}; +- +-/* MMC1 */ +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>; +- cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&iomuxc { +- /* +- * Mux the Apalis GPIOs +- */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 +- &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 +- &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 +- &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 +- >; +- +- pinctrl_leds_ixora: ledsixoragrp { +- fsl,pins = < +- MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 +- MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 +- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-apalis-ixora.dts b/scripts/dtc/include-prefixes/arm/imx6q-apalis-ixora.dts +deleted file mode 100644 +index 62e72773e53b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-apalis-ixora.dts ++++ /dev/null +@@ -1,275 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2014-2020 Toradex +- * Copyright 2012 Freescale Semiconductor, Inc. +- * Copyright 2011 Linaro Ltd. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include "imx6q.dtsi" +-#include "imx6qdl-apalis.dtsi" +- +-/ { +- model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board"; +- compatible = "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q", +- "fsl,imx6q"; +- +- aliases { +- i2c0 = &i2c1; +- i2c1 = &i2c3; +- i2c2 = &i2c2; +- rtc0 = &rtc_i2c; +- rtc1 = &snvs_rtc; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- wakeup { +- label = "Wake-Up"; +- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- lcd_display: disp0 { +- compatible = "fsl,imx-parallel-display"; +- #address-cells = <1>; +- #size-cells = <0>; +- interface-pix-fmt = "rgb24"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_lcdif>; +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- lcd_display_in: endpoint { +- remote-endpoint = <&ipu1_di1_disp1>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lcd_display_out: endpoint { +- remote-endpoint = <&lcd_panel_in>; +- }; +- }; +- }; +- +- panel: panel { +- /* +- * edt,et057090dhu: EDT 5.7" LCD TFT +- * edt,et070080dh6: EDT 7.0" LCD TFT +- */ +- compatible = "edt,et057090dhu"; +- backlight = <&backlight>; +- +- port { +- lcd_panel_in: endpoint { +- remote-endpoint = <&lcd_display_out>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds_ixora>; +- +- led4-green { +- label = "LED_4_GREEN"; +- gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; +- }; +- +- led4-red { +- label = "LED_4_RED"; +- gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; +- }; +- +- led5-green { +- label = "LED_5_GREEN"; +- gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; +- }; +- +- led5-red { +- label = "LED_5_RED"; +- gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&backlight { +- brightness-levels = <0 127 191 223 239 247 251 255>; +- default-brightness-level = <1>; +- status = "okay"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&can2 { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ +-&i2c1 { +- status = "okay"; +- +- /* +- * Touchscreen is using SODIMM 28/30, also used for PWM, PWM, +- * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms +- */ +- touchscreen@4a { +- compatible = "atmel,maxtouch"; +- reg = <0x4a>; +- interrupt-parent = <&gpio6>; +- interrupts = <10 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* SODIMM 13 */ +- status = "disabled"; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- }; +- +- /* M41T0M6 real time clock on carrier board */ +- rtc_i2c: rtc@68 { +- compatible = "st,m41t0"; +- reg = <0x68>; +- }; +-}; +- +-/* +- * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier +- * board) +- */ +-&i2c3 { +- status = "okay"; +-}; +- +-&ipu1_di1_disp1 { +- remote-endpoint = <&lcd_display_in>; +-}; +- +-&ldb { +- status = "okay"; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reset_moci>; +- /* active-high meaning opposite of regular PERST# active-low polarity */ +- reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; +- reset-gpio-active-high; +- status = "okay"; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&pwm3 { +- status = "okay"; +-}; +- +-&pwm4 { +- status = "okay"; +-}; +- +-®_usb_otg_vbus { +- status = "okay"; +-}; +- +-®_usb_host_vbus { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&sound_spdif { +- status = "okay"; +-}; +- +-&spdif { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart4 { +- status = "okay"; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_host_vbus>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- status = "okay"; +-}; +- +-/* SD1 */ +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; +- cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&iomuxc { +- /* Mux the Apalis GPIOs */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 +- &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 +- &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 +- &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 +- >; +- +- pinctrl_leds_ixora: ledsixoragrp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 +- MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 +- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-apf6dev.dts b/scripts/dtc/include-prefixes/arm/imx6q-apf6dev.dts +deleted file mode 100644 +index 664b0af8f0bb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-apf6dev.dts ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Copyright 2015 Armadeus Systems +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-apf6.dtsi" +-#include "imx6qdl-apf6dev.dtsi" +- +-/ { +- model = "Armadeus APF6 Quad / Dual Module on APF6Dev Board"; +- compatible = "armadeus,imx6q-apf6dev", "armadeus,imx6q-apf6", "fsl,imx6q"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-arm2.dts b/scripts/dtc/include-prefixes/arm/imx6q-arm2.dts +deleted file mode 100644 +index 0b40f52268b3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-arm2.dts ++++ /dev/null +@@ -1,225 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2011 Freescale Semiconductor, Inc. +- * Copyright 2011 Linaro Ltd. +- */ +- +-/dts-v1/; +-#include +-#include "imx6q.dtsi" +- +-/ { +- model = "Freescale i.MX6 Quad Armadillo2 Board"; +- compatible = "fsl,imx6q-arm2", "fsl,imx6q"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_3p3v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 0>; +- enable-active-high; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- debug-led { +- label = "Heartbeat"; +- gpios = <&gpio3 25 0>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- status = "disabled"; /* gpmi nand conflicts with SD */ +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx6q-arm2 { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- >; +- }; +- +- pinctrl_usdhc3_cdwp: usdhc3cdwp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 +- MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 +- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 +- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 +- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +- >; +- }; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii"; +- interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, +- <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; +- fsl,err006687-workaround-present; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc3 { +- cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; +- vmmc-supply = <®_3p3v>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3 +- &pinctrl_usdhc3_cdwp>; +- status = "okay"; +-}; +- +-&usdhc4 { +- non-removable; +- vmmc-supply = <®_3p3v>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- fsl,dte-mode; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-b450v3.dts b/scripts/dtc/include-prefixes/arm/imx6q-b450v3.dts +deleted file mode 100644 +index d994b32ad825..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-b450v3.dts ++++ /dev/null +@@ -1,157 +0,0 @@ +-/* +- * Copyright 2015 Timesys Corporation. +- * Copyright 2015 General Electric Company +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include "imx6q-bx50v3.dtsi" +- +-/ { +- model = "General Electric B450v3"; +- compatible = "ge,imx6q-b450v3", "advantech,imx6q-ba16", "fsl,imx6q"; +- +- chosen { +- stdout-path = &uart3; +- }; +- +- panel-lvds0 { +- compatible = "innolux,g121x1-l03"; +- backlight = <&backlight_lvds>; +- power-supply = <®_lvds>; +- +- port { +- panel_in_lvds0: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds0: lvds-channel@0 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <24>; +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in_lvds0>; +- }; +- }; +- }; +-}; +- +-&pca9539 { +- gpio-line-names = "AMB_P_INT1#", "AMB_P_INT2#", "BT_EN", "WLAN_EN", +- "", "SM_D_ACT", "DP1_RST#", "", +- "WD15S_EN", "WD15S_DIS#", "", "", +- "", "", "", ""; +- +- P04-hog { +- gpio-hog; +- gpios = <4 0>; +- output-low; +- line-name = "PCA9539-P04"; +- }; +- +- P07-hog { +- gpio-hog; +- gpios = <7 0>; +- output-low; +- line-name = "PCA9539-P07"; +- }; +-}; +- +-&pci_root { +- /* Intel Corporation I210 Gigabit Network Connection */ +- switch_nic: ethernet@3,0 { +- compatible = "pci8086,1533"; +- reg = <0x00010000 0 0 0 0>; +- }; +-}; +- +-&switch_ports { +- port@0 { +- reg = <0>; +- label = "enacq"; +- phy-handle = <&switchphy0>; +- }; +- +- port@1 { +- reg = <1>; +- label = "eneport1"; +- phy-handle = <&switchphy1>; +- }; +- +- port@2 { +- reg = <2>; +- label = "enix"; +- phy-handle = <&switchphy2>; +- }; +- +- port@3 { +- reg = <3>; +- label = "enid"; +- phy-handle = <&switchphy3>; +- }; +- +- port@4 { +- reg = <4>; +- label = "cpu"; +- ethernet = <&switch_nic>; +- phy-handle = <&switchphy4>; +- }; +- +- port@5 { +- reg = <5>; +- label = "enembc"; +- +- /* connected to Ethernet MAC of AT91RM9200 in MII mode */ +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-b650v3.dts b/scripts/dtc/include-prefixes/arm/imx6q-b650v3.dts +deleted file mode 100644 +index fa1a1df37cde..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-b650v3.dts ++++ /dev/null +@@ -1,156 +0,0 @@ +-/* +- * Copyright 2015 Timesys Corporation. +- * Copyright 2015 General Electric Company +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include "imx6q-bx50v3.dtsi" +- +-/ { +- model = "General Electric B650v3"; +- compatible = "ge,imx6q-b650v3", "advantech,imx6q-ba16", "fsl,imx6q"; +- +- chosen { +- stdout-path = &uart3; +- }; +- +- panel-lvds0 { +- compatible = "innolux,g121x1-l03"; +- backlight = <&backlight_lvds>; +- power-supply = <®_lvds>; +- +- port { +- panel_in_lvds0: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds0: lvds-channel@0 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <24>; +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in_lvds0>; +- }; +- }; +- }; +-}; +- +-&pca9539 { +- gpio-line-names = "AMB_P_INT1#", "AMB_P_INT2#", "BT_EN", "WLAN_EN", +- "", "SM_D_ACT", "DP1_RST#", "", +- "WD15S_EN", "WD15S_DIS#", "", "", +- "", "", "", ""; +- +- P07-hog { +- gpio-hog; +- gpios = <7 0>; +- output-low; +- line-name = "PCA9539-P07"; +- }; +-}; +- +-&usbphy1 { +- fsl,tx-cal-45-dn-ohms = <55>; +- fsl,tx-cal-45-dp-ohms = <55>; +- fsl,tx-d-cal = <100>; +-}; +- +-&pci_root { +- /* Intel Corporation I210 Gigabit Network Connection */ +- switch_nic: ethernet@3,0 { +- compatible = "pci8086,1533"; +- reg = <0x00010000 0 0 0 0>; +- }; +-}; +- +-&switch_ports { +- port@0 { +- reg = <0>; +- label = "enacq"; +- phy-handle = <&switchphy0>; +- }; +- +- port@1 { +- reg = <1>; +- label = "eneport1"; +- phy-handle = <&switchphy1>; +- }; +- +- port@2 { +- reg = <2>; +- label = "enix"; +- phy-handle = <&switchphy2>; +- }; +- +- port@3 { +- reg = <3>; +- label = "enid"; +- phy-handle = <&switchphy3>; +- }; +- +- port@4 { +- reg = <4>; +- label = "cpu"; +- ethernet = <&switch_nic>; +- phy-handle = <&switchphy4>; +- }; +- +- port@5 { +- reg = <5>; +- label = "enembc"; +- +- /* connected to Ethernet MAC of AT91RM9200 in MII mode */ +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-b850v3.dts b/scripts/dtc/include-prefixes/arm/imx6q-b850v3.dts +deleted file mode 100644 +index db8c332df6a1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-b850v3.dts ++++ /dev/null +@@ -1,295 +0,0 @@ +-/* +- * Copyright 2015 Timesys Corporation. +- * Copyright 2015 General Electric Company +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include "imx6q-bx50v3.dtsi" +- +-/ { +- model = "General Electric B850v3"; +- compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q"; +- +- chosen { +- stdout-path = &uart3; +- }; +-}; +- +-&ldb { +- fsl,dual-channel; +- status = "okay"; +- +- lvds0: lvds-channel@0 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <24>; +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&stdp4028_in>; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- pca9547_ddc: mux@70 { +- compatible = "nxp,pca9547"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- mux2_i2c1: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0>; +- }; +- +- mux2_i2c2: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x1>; +- }; +- +- mux2_i2c3: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; +- }; +- +- mux2_i2c4: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3>; +- }; +- +- mux2_i2c5: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x4>; +- }; +- +- mux2_i2c6: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x5>; +- }; +- +- mux2_i2c7: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x6>; +- }; +- +- mux2_i2c8: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x7>; +- }; +- }; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&mux2_i2c1>; +-}; +- +-&mux1_i2c1 { +- ads7830@4a { +- compatible = "ti,ads7830"; +- reg = <0x4a>; +- }; +-}; +- +-&mux2_i2c2 { +- clock-frequency = <100000>; +- +- stdp2690@72 { +- compatible = "megachips,stdp2690-ge-b850v3-fw"; +- reg = <0x72>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- stdp2690_in: endpoint { +- remote-endpoint = <&stdp4028_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- stdp2690_out: endpoint { +- /* Connector for external display */ +- }; +- }; +- }; +- }; +- +- stdp4028@73 { +- compatible = "megachips,stdp4028-ge-b850v3-fw"; +- reg = <0x73>; +- interrupt-parent = <&gpio2>; +- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- stdp4028_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- stdp4028_out: endpoint { +- remote-endpoint = <&stdp2690_in>; +- }; +- }; +- }; +- }; +-}; +- +-&pca9539 { +- gpio-line-names = "AMB_P_INT1#", "AMB_P_INT2#", "BT_EN", "WLAN_EN", +- "REMOTE_ON_PML#", "SM_D_ACT", "DP1_RST#", "DP2_RST#", +- "", "", "", "", +- "", "", "", ""; +- +- P10-hog { +- gpio-hog; +- gpios = <8 0>; +- output-low; +- line-name = "PCA9539-P10"; +- }; +- +- P11-hog { +- gpio-hog; +- gpios = <9 0>; +- output-low; +- line-name = "PCA9539-P11"; +- }; +-}; +- +-&pci_root { +- /* PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch */ +- bridge@1,0 { +- compatible = "pci10b5,8605"; +- reg = <0x00010000 0 0 0 0>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- +- bridge@2,1 { +- compatible = "pci10b5,8605"; +- reg = <0x00020800 0 0 0 0>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- +- /* Intel Corporation I210 Gigabit Network Connection */ +- ethernet@3,0 { +- compatible = "pci8086,1533"; +- reg = <0x00030000 0 0 0 0>; +- }; +- }; +- +- bridge@2,2 { +- compatible = "pci10b5,8605"; +- reg = <0x00021000 0 0 0 0>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- +- /* Intel Corporation I210 Gigabit Network Connection */ +- switch_nic: ethernet@4,0 { +- compatible = "pci8086,1533"; +- reg = <0x00040000 0 0 0 0>; +- }; +- }; +- }; +-}; +- +-&switch_ports { +- port@0 { +- reg = <0>; +- label = "eneport1"; +- phy-handle = <&switchphy0>; +- }; +- +- port@1 { +- reg = <1>; +- label = "eneport2"; +- phy-handle = <&switchphy1>; +- }; +- +- port@2 { +- reg = <2>; +- label = "enix"; +- phy-handle = <&switchphy2>; +- }; +- +- port@3 { +- reg = <3>; +- label = "enid"; +- phy-handle = <&switchphy3>; +- }; +- +- port@4 { +- reg = <4>; +- label = "cpu"; +- ethernet = <&switch_nic>; +- phy-handle = <&switchphy4>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-ba16.dtsi b/scripts/dtc/include-prefixes/arm/imx6q-ba16.dtsi +deleted file mode 100644 +index 6330d75f8f39..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-ba16.dtsi ++++ /dev/null +@@ -1,661 +0,0 @@ +-/* +- * Support for imx6 based Advantech DMS-BA16 Qseven module +- * +- * Copyright 2015 Timesys Corporation. +- * Copyright 2015 General Electric Company +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "imx6q.dtsi" +-#include +- +-/ { +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- backlight_lvds: backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_display>; +- pwms = <&pwm1 0 5000000>; +- brightness-levels = < 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100 101 102 103 104 105 106 107 108 109 +- 110 111 112 113 114 115 116 117 118 119 +- 120 121 122 123 124 125 126 127 128 129 +- 130 131 132 133 134 135 136 137 138 139 +- 140 141 142 143 144 145 146 147 148 149 +- 150 151 152 153 154 155 156 157 158 159 +- 160 161 162 163 164 165 166 167 168 169 +- 170 171 172 173 174 175 176 177 178 179 +- 180 181 182 183 184 185 186 187 188 189 +- 190 191 192 193 194 195 196 197 198 199 +- 200 201 202 203 204 205 206 207 208 209 +- 210 211 212 213 214 215 216 217 218 219 +- 220 221 222 223 224 225 226 227 228 229 +- 230 231 232 233 234 235 236 237 238 239 +- 240 241 242 243 244 245 246 247 248 249 +- 250 251 252 253 254 255>; +- default-brightness-level = <255>; +- enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_lvds: regulator-lvds { +- compatible = "regulator-fixed"; +- regulator-name = "lvds_ppen"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_h1_vbus: regulator-usbh1vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usb_otg_vbus: regulator-usbotgvbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- pinctrl-0 = <&pinctrl_usbotg_vbus>; +- gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- flash: n25q032@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <20000000>; +- reg = <0>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0x0 0xc0000>; +- }; +- +- partition@c0000 { +- label = "env"; +- reg = <0xc0000 0x10000>; +- }; +- +- partition@d0000 { +- label = "spare"; +- reg = <0xd0000 0x320000>; +- }; +- +- partition@3f0000 { +- label = "mfg"; +- reg = <0x3f0000 0x10000>; +- }; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-supply = <®_3p3v>; +- phy-handle = <&phy0>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: ethernet-phy@4 { +- reg = <4>; +- qca,clk-out-frequency = <125000000>; +- }; +- }; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- pmic@58 { +- compatible = "dlg,da9063"; +- reg = <0x58>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio7>; +- interrupts = <13 IRQ_TYPE_LEVEL_LOW>; +- +- onkey { +- compatible = "dlg,da9063-onkey"; +- }; +- +- regulators { +- vdd_bcore1: bcore1 { +- regulator-min-microvolt = <1420000>; +- regulator-max-microvolt = <1420000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_bcore2: bcore2 { +- regulator-min-microvolt = <1420000>; +- regulator-max-microvolt = <1420000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_bpro: bpro { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_bmem: bmem { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_bio: bio { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_bperi: bperi { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_ldo1: ldo1 { +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1860000>; +- }; +- +- vdd_ldo2: ldo2 { +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1860000>; +- }; +- +- vdd_ldo3: ldo3 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <3440000>; +- }; +- +- vdd_ldo4: ldo4 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <3440000>; +- }; +- +- vdd_ldo5: ldo5 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <3600000>; +- }; +- +- vdd_ldo6: ldo6 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <3600000>; +- }; +- +- vdd_ldo7: ldo7 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <3600000>; +- }; +- +- vdd_ldo8: ldo8 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <3600000>; +- }; +- +- vdd_ldo9: ldo9 { +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <3600000>; +- }; +- +- vdd_ldo10: ldo10 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <3600000>; +- }; +- +- vdd_ldo11: ldo11 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <3600000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +- +- rtc@32 { +- compatible = "epson,rx8010"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rtc>; +- reg = <0x32>; +- interrupt-parent = <&gpio4>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; +- fsl,tx-swing-full = <103>; +- fsl,tx-swing-low = <103>; +- status = "okay"; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- status = "disabled"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbh1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbhub>; +- vbus-supply = <®_usb_h1_vbus>; +- reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- keep-power-in-suspend; +- wakeup-source; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>; +- bus-width = <8>; +- vmmc-supply = <&vdd_bperi>; +- non-removable; +- keep-power-in-suspend; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 +- MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 +- MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 +- MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 +- >; +- }; +- +- pinctrl_display: dispgrp { +- fsl,pins = < +- /* BLEN_OUT */ +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 +- /* LVDS_PPEN_OUT */ +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- /* SPI1 CS */ +- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +- >; +- }; +- +- pinctrl_ecspi5: ecspi5grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b0b0 +- MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x1b0b0 +- MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x1b0b0 +- MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- /* FEC Reset */ +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +- /* AR8033 Interrupt */ +- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 +- >; +- }; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- /* GPIO 0-7 */ +- MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 +- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 +- MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 +- MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 +- MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b0 +- MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 +- MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 +- /* SUS_S3_OUT to CPLD */ +- MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- /* PCIe Reset */ +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 +- /* PCIe Wake */ +- MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- /* PMIC Interrupt */ +- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_rtc: rtcgrp { +- fsl,pins = < +- /* RTC_INT */ +- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbhub: usbhubgrp { +- fsl,pins = < +- /* HUB_RESET */ +- MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usbotg_vbus: usbotgvbusgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- /* uSDHC2 CD */ +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- >; +- }; +- +- pinctrl_usdhc3_reset: usdhc3grp-reset { +- fsl,pins = < +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9 +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 +- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 +- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 +- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +- /* uSDHC4 CD */ +- MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 +- /* uSDHC4 SDIO PWR */ +- MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 +- /* uSDHC4 SDIO WP */ +- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 +- /* uSDHC4 SDIO LED */ +- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-bx50v3.dtsi b/scripts/dtc/include-prefixes/arm/imx6q-bx50v3.dtsi +deleted file mode 100644 +index 10922375c51e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-bx50v3.dtsi ++++ /dev/null +@@ -1,409 +0,0 @@ +-/* +- * Copyright 2015 Timesys Corporation. +- * Copyright 2015 General Electric Company +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "imx6q-ba16.dtsi" +- +-/ { +- mclk: clock-mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <22000000>; +- }; +- +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; +- status = "okay"; +- }; +- +- reg_wl18xx_vmmc: regulator-wl18xx { +- compatible = "regulator-fixed"; +- regulator-name = "vwl1807"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&pca9539 3 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <70000>; +- enable-active-high; +- }; +- +- reg_wlan: regulator-wlan { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V_wlan"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio6 14 GPIO_ACTIVE_HIGH>; +- }; +- +- sound { +- compatible = "fsl,imx6q-ba16-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "imx6q-ba16-sgtl5000"; +- ssi-controller = <&ssi1>; +- audio-codec = <&sgtl5000>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "LINE_IN", "Line In Jack", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <4>; +- }; +- +- aliases { +- mdio-gpio0 = &mdio0; +- }; +- +- mdio0: mdio-gpio { +- compatible = "virtual,mdio-gpio"; +- gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>, /* mdc */ +- <&gpio2 7 GPIO_ACTIVE_HIGH>; /* mdio */ +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch: switch@0 { +- compatible = "marvell,mv88e6085"; /* 88e6240*/ +- reg = <0>; +- +- interrupt-parent = <&gpio2>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- switch_ports: ports { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switchphy0: switchphy@0 { +- reg = <0>; +- interrupt-parent = <&switch>; +- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switchphy1: switchphy@1 { +- reg = <1>; +- interrupt-parent = <&switch>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switchphy2: switchphy@2 { +- reg = <2>; +- interrupt-parent = <&switch>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switchphy3: switchphy@3 { +- reg = <3>; +- interrupt-parent = <&switch>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switchphy4: switchphy@4 { +- reg = <4>; +- interrupt-parent = <&switch>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +- }; +- }; +- }; +- }; +-}; +- +-&ecspi5 { +- cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi5>; +- status = "okay"; +- +- m25_eeprom: m25p80@0 { +- compatible = "atmel,at25"; +- spi-max-frequency = <10000000>; +- size = <0x8000>; +- pagesize = <64>; +- reg = <0>; +- address-width = <16>; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default", "gpio"; +- pinctrl-1 = <&pinctrl_i2c1_gpio>; +- sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- +- pca9547: mux@70 { +- compatible = "nxp,pca9547"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- mux1_i2c1: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0>; +- +- ads7830: ads7830@48 { +- compatible = "ti,ads7830"; +- reg = <0x48>; +- }; +- +- mma8453: mma8453@1c { +- compatible = "fsl,mma8453"; +- reg = <0x1c>; +- }; +- }; +- +- mux1_i2c2: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x1>; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c08"; +- reg = <0x50>; +- }; +- +- mpl3115: mpl3115@60 { +- compatible = "fsl,mpl3115"; +- reg = <0x60>; +- }; +- }; +- +- mux1_i2c3: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; +- }; +- +- mux1_i2c4: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3>; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&mclk>; +- VDDA-supply = <®_1p8v>; +- VDDIO-supply = <®_3p3v>; +- }; +- }; +- +- mux1_i2c5: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x4>; +- +- pca9539: pca9539@74 { +- compatible = "nxp,pca9539"; +- reg = <0x74>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- interrupt-parent = <&gpio2>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- +- P12-hog { +- gpio-hog; +- gpios = <10 0>; +- output-low; +- line-name = "PCA9539-P12"; +- }; +- +- P13-hog { +- gpio-hog; +- gpios = <11 0>; +- output-low; +- line-name = "PCA9539-P13"; +- }; +- +- P14-hog { +- gpio-hog; +- gpios = <12 0>; +- output-low; +- line-name = "PCA9539-P14"; +- }; +- +- P15-hog { +- gpio-hog; +- gpios = <13 0>; +- output-low; +- line-name = "PCA9539-P15"; +- }; +- +- P16-hog { +- gpio-hog; +- gpios = <14 0>; +- output-low; +- line-name = "PCA9539-P16"; +- }; +- +- P17-hog { +- gpio-hog; +- gpios = <15 0>; +- output-low; +- line-name = "PCA9539-P17"; +- }; +- }; +- }; +- +- mux1_i2c6: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x5>; +- }; +- +- mux1_i2c7: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x6>; +- }; +- +- mux1_i2c8: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x7>; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default", "gpio"; +- pinctrl-1 = <&pinctrl_i2c2_gpio>; +- sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +-}; +- +-&i2c3 { +- pinctrl-names = "default", "gpio"; +- pinctrl-1 = <&pinctrl_i2c3_gpio>; +- sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +-}; +- +-&iomuxc { +- pinctrl_i2c1_gpio: i2c1gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c2_gpio: i2c2gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 +- MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c3_gpio: i2c3gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 +- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 +- >; +- }; +-}; +- +-&pmu { +- secure-reg-access; +-}; +- +-&usdhc2 { +- status = "disabled"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <4>; +- vmmc-supply = <®_wl18xx_vmmc>; +- no-1-8-v; +- non-removable; +- wakeup-source; +- keep-power-in-suspend; +- cap-power-off-card; +- max-frequency = <25000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- wlcore: wlcore@2 { +- compatible = "ti,wl1837"; +- reg = <2>; +- interrupt-parent = <&gpio2>; +- interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; +- tcxo-clock-frequency = <26000000>; +- }; +-}; +- +-&pcie { +- /* Synopsys, Inc. Device */ +- pci_root: root@0,0 { +- compatible = "pci16c3,abcd"; +- reg = <0x00000000 0 0 0 0>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- }; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>, +- <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, +- <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>, +- <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>, +- <&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, +- <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, +- <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, +- <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, +- <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, +- <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-cm-fx6.dts b/scripts/dtc/include-prefixes/arm/imx6q-cm-fx6.dts +deleted file mode 100644 +index bfb530f29d9d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-cm-fx6.dts ++++ /dev/null +@@ -1,491 +0,0 @@ +-/* +- * Copyright 2013 CompuLab Ltd. +- * +- * Author: Valentin Raevsky +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include +-#include +-#include "imx6q.dtsi" +- +-/ { +- model = "CompuLab CM-FX6"; +- compatible = "compulab,cm-fx6", "fsl,imx6q"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- heartbeat-led { +- label = "Heartbeat"; +- gpios = <&gpio2 31 0>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- awnh387_pwrseq: pwrseq { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwrseq>; +- compatible = "mmc-pwrseq-sd8787"; +- powerdown-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_pcie_power_on_gpio: regulator-pcie-power-on-gpio { +- compatible = "regulator-fixed"; +- regulator-name = "regulator-pcie-power-on-gpio"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; +- }; +- +- reg_usb_h1_vbus: usb_h1_vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_otg_vbus: usb_otg_vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sound-analog { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "On-board analog audio"; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack", +- "Line", "Line Out", +- "Microphone", "Mic Jack", +- "Line", "Line In"; +- simple-audio-card,routing = +- "Headphone Jack", "RHPOUT", +- "Headphone Jack", "LHPOUT", +- "MICIN", "Mic Bias", +- "Mic Bias", "Mic Jack"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sound_master>; +- simple-audio-card,frame-master = <&sound_master>; +- simple-audio-card,bitclock-inversion; +- +- sound_master: simple-audio-card,cpu { +- sound-dai = <&ssi2>; +- system-clock-frequency = <2822400>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&wm8731>; +- }; +- }; +- +- sound-spdif { +- compatible = "fsl,imx-audio-spdif"; +- model = "imx-spdif"; +- spdif-controller = <&spdif>; +- spdif-out; +- spdif-in; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +- +- ssi2 { +- fsl,audmux-port = <1>; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_RCLKDIR | +- IMX_AUDMUX_V2_PTCR_RCSEL(3 | 0x8) | +- IMX_AUDMUX_V2_PTCR_TCLKDIR | +- IMX_AUDMUX_V2_PTCR_TCSEL(3)) +- IMX_AUDMUX_V2_PDCR_RXDSEL(3) +- >; +- }; +- +- audmux4 { +- fsl,audmux-port = <3>; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_TFSDIR | +- IMX_AUDMUX_V2_PTCR_TFSEL(1) | +- IMX_AUDMUX_V2_PTCR_RCLKDIR | +- IMX_AUDMUX_V2_PTCR_RCSEL(1 | 0x8) | +- IMX_AUDMUX_V2_PTCR_TCLKDIR | +- IMX_AUDMUX_V2_PTCR_TCSEL(1)) +- IMX_AUDMUX_V2_PDCR_RXDSEL(1) +- >; +- }; +-}; +- +-&cpu0 { +- /* +- * Although the imx6q fuse indicates that 1.2GHz operation is possible, +- * the module behaves unstable at this frequency. Hence, remove the +- * 1.2GHz operation point here. +- */ +- operating-points = < +- /* kHz uV */ +- 996000 1250000 +- 852000 1250000 +- 792000 1175000 +- 396000 975000 +- >; +- fsl,soc-operating-points = < +- /* ARM kHz SOC-PU uV */ +- 996000 1250000 +- 852000 1250000 +- 792000 1175000 +- 396000 1175000 +- >; +-}; +- +-&cpu1 { +- /* +- * Although the imx6q fuse indicates that 1.2GHz operation is possible, +- * the module behaves unstable at this frequency. Hence, remove the +- * 1.2GHz operation point here. +- */ +- operating-points = < +- /* kHz uV */ +- 996000 1250000 +- 852000 1250000 +- 792000 1175000 +- 396000 975000 +- >; +- fsl,soc-operating-points = < +- /* ARM kHz SOC-PU uV */ +- 996000 1250000 +- 852000 1250000 +- 792000 1175000 +- 396000 1175000 +- >; +-}; +- +-&cpu2 { +- /* +- * Although the imx6q fuse indicates that 1.2GHz operation is possible, +- * the module behaves unstable at this frequency. Hence, remove the +- * 1.2GHz operation point here. +- */ +- operating-points = < +- /* kHz uV */ +- 996000 1250000 +- 852000 1250000 +- 792000 1175000 +- 396000 975000 +- >; +- fsl,soc-operating-points = < +- /* ARM kHz SOC-PU uV */ +- 996000 1250000 +- 852000 1250000 +- 792000 1175000 +- 396000 1175000 +- >; +-}; +- +-&cpu3 { +- /* +- * Although the imx6q fuse indicates that 1.2GHz operation is possible, +- * the module behaves unstable at this frequency. Hence, remove the +- * 1.2GHz operation point here. +- */ +- operating-points = < +- /* kHz uV */ +- 996000 1250000 +- 852000 1250000 +- 792000 1175000 +- 396000 975000 +- >; +- fsl,soc-operating-points = < +- /* ARM kHz SOC-PU uV */ +- 996000 1250000 +- 852000 1250000 +- 792000 1175000 +- 396000 1175000 +- >; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p", "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii"; +- status = "okay"; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- status = "okay"; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- clock-frequency = <100000>; +- +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- wm8731: codec@1a { +- #sound-dai-cells = <0>; +- compatible = "wlf,wm8731"; +- reg = <0x1a>; +- }; +-}; +- +-&iomuxc { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x17059 +- MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x17059 +- MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x17059 +- MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x17059 +- MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x17059 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 +- MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 +- >; +- }; +- +- pinctrl_pwrseq: pwrseqgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 +- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 +- >; +- }; +- +- pinctrl_spdif: spdifgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 +- MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbh1: usbh1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 +- >; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>; +- vpcie-supply = <®_pcie_power_on_gpio>; +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&snvs_poweroff { +- status = "okay"; +-}; +- +-&spdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spdif>; +- status = "okay"; +-}; +- +-&ssi2 { +- assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>, +- <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; +- assigned-clock-rates = <0>, <786432000>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- mmc-pwrseq = <&awnh387_pwrseq>; +- non-removable; +- /* +- * If the OS probes the Bluetooth AMP function advertised on this bus +- * but the firmware in place does not support it, the WiFi/BT module +- * gets unresponsive. +- * Users who configured their OS properly can enable this node to gain +- * WiFi and/or plain Bluetooth support. +- */ +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-cubox-i-emmc-som-v15.dts b/scripts/dtc/include-prefixes/arm/imx6q-cubox-i-emmc-som-v15.dts +deleted file mode 100644 +index 3e59ebbb3608..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-cubox-i-emmc-som-v15.dts ++++ /dev/null +@@ -1,60 +0,0 @@ +-/* +- * Copyright (C) 2014 Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-ti.dtsi" +-#include "imx6qdl-sr-som-emmc.dtsi" +-#include "imx6qdl-cubox-i.dtsi" +- +-/ { +- model = "SolidRun Cubox-i Dual/Quad (1.5som+emmc)"; +- compatible = "solidrun,cubox-i/q", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +- fsl,transmit-level-mV = <1104>; +- fsl,transmit-boost-mdB = <0>; +- fsl,transmit-atten-16ths = <9>; +- fsl,no-spread-spectrum; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-cubox-i-som-v15.dts b/scripts/dtc/include-prefixes/arm/imx6q-cubox-i-som-v15.dts +deleted file mode 100644 +index dab70d1230a2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-cubox-i-som-v15.dts ++++ /dev/null +@@ -1,59 +0,0 @@ +-/* +- * Copyright (C) 2014 Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-ti.dtsi" +-#include "imx6qdl-cubox-i.dtsi" +- +-/ { +- model = "SolidRun Cubox-i Dual/Quad (1.5som)"; +- compatible = "solidrun,cubox-i/q", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +- fsl,transmit-level-mV = <1104>; +- fsl,transmit-boost-mdB = <0>; +- fsl,transmit-atten-16ths = <9>; +- fsl,no-spread-spectrum; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-cubox-i.dts b/scripts/dtc/include-prefixes/arm/imx6q-cubox-i.dts +deleted file mode 100644 +index 1c7b262e3709..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-cubox-i.dts ++++ /dev/null +@@ -1,59 +0,0 @@ +-/* +- * Copyright (C) 2014 Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-brcm.dtsi" +-#include "imx6qdl-cubox-i.dtsi" +- +-/ { +- model = "SolidRun Cubox-i Dual/Quad"; +- compatible = "solidrun,cubox-i/q", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +- fsl,transmit-level-mV = <1104>; +- fsl,transmit-boost-mdB = <0>; +- fsl,transmit-atten-16ths = <9>; +- fsl,no-spread-spectrum; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-dfi-fs700-m60.dts b/scripts/dtc/include-prefixes/arm/imx6q-dfi-fs700-m60.dts +deleted file mode 100644 +index 8bfe6337cd65..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-dfi-fs700-m60.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Sascha Hauer +- */ +- +-#ifndef __DTS_V1__ +-#define __DTS_V1__ +-/dts-v1/; +-#endif +- +-#include "imx6q.dtsi" +-#include "imx6qdl-dfi-fs700-m60.dtsi" +- +-/ { +- model = "DFI FS700-M60-6QD i.MX6qd Q7 Board"; +- compatible = "dfi,fs700-m60-6qd", "dfi,fs700e-m60", "fsl,imx6q"; +- +- /* Will be filled by the bootloader */ +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-dhcom-pdk2.dts b/scripts/dtc/include-prefixes/arm/imx6q-dhcom-pdk2.dts +deleted file mode 100644 +index d4d57370615d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-dhcom-pdk2.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2015-2021 DH electronics GmbH +- * Copyright (C) 2018 Marek Vasut +- * +- * DHCOM iMX6 variant: +- * DHCM-iMX6Q-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2 +- * DHCOM PCB number: 493-300 or newer +- * PDK2 PCB number: 516-400 or newer +- */ +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-dhcom-som.dtsi" +-#include "imx6qdl-dhcom-pdk2.dtsi" +- +-/ { +- model = "DH electronics i.MX6Q DHCOM on Premium Developer Kit (2)"; +- compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som", +- "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-display5-tianma-tm070-1280x768.dts b/scripts/dtc/include-prefixes/arm/imx6q-display5-tianma-tm070-1280x768.dts +deleted file mode 100644 +index 16658b76fc4e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-display5-tianma-tm070-1280x768.dts ++++ /dev/null +@@ -1,51 +0,0 @@ +-/* +- * Copyright 2017 +- * Lukasz Majewski, DENX Software Engineering, lukma@denx.de +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include "imx6q-display5.dtsi" +- +-&panel { +- compatible = "tianma,tm070jdhg30"; +-}; +- +-&ldb { +- lvds0: lvds-channel@0 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <18>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-display5.dtsi b/scripts/dtc/include-prefixes/arm/imx6q-display5.dtsi +deleted file mode 100644 +index fef5d7254536..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-display5.dtsi ++++ /dev/null +@@ -1,596 +0,0 @@ +-/* +- * Copyright 2017 +- * Lukasz Majewski, DENX Software Engineering, lukma@denx.de +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +- +-#include +-#include +-#include +- +-/ { +- model = "Liebherr (LWN) display5 i.MX6 Quad Board"; +- compatible = "lwn,display5", "fsl,imx6q"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- backlight_lvds: backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_backlight>; +- pwms = <&pwm2 0 5000000 0>; +- brightness-levels = < 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100 101 102 103 104 105 106 107 108 109 +- 110 111 112 113 114 115 116 117 118 119 +- 120 121 122 123 124 125 126 127 128 129 +- 130 131 132 133 134 135 136 137 138 139 +- 140 141 142 143 144 145 146 147 148 149 +- 150 151 152 153 154 155 156 157 158 159 +- 160 161 162 163 164 165 166 167 168 169 +- 170 171 172 173 174 175 176 177 178 179 +- 180 181 182 183 184 185 186 187 188 189 +- 190 191 192 193 194 195 196 197 198 199 +- 200 201 202 203 204 205 206 207 208 209 +- 210 211 212 213 214 215 216 217 218 219 +- 220 221 222 223 224 225 226 227 228 229 +- 230 231 232 233 234 235 236 237 238 239 +- 240 241 242 243 244 245 246 247 248 249 +- 250 251 252 253 254 255>; +- default-brightness-level = <250>; +- enable-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_lvds: regulator-lvds { +- compatible = "regulator-fixed"; +- regulator-name = "lvds_ppen"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_lvds>; +- gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usbh1_vbus: usb-h1-vbus { +- compatible = "regulator-fixed"; +- gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1_vbus>; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-enable-ramp-delay = <300000>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- label = "tfa9879-mono"; +- +- simple-audio-card,dai-link { +- /* DAC */ +- format = "i2s"; +- bitclock-master = <&dailink_master>; +- frame-master = <&dailink_master>; +- +- dailink_master: cpu { +- sound-dai = <&ssi2>; +- }; +- codec { +- sound-dai = <&codec>; +- }; +- }; +- }; +- +- panel: panel-lvds0 { +- backlight = <&backlight_lvds>; +- power-supply = <®_lvds>; +- +- port { +- panel_in_lvds0: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +- +- ssi2 { +- fsl,audmux-port = <1>; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_SYN | +- IMX_AUDMUX_V2_PTCR_TFSEL(5) | +- IMX_AUDMUX_V2_PTCR_TCSEL(5) | +- IMX_AUDMUX_V2_PTCR_TFSDIR | +- IMX_AUDMUX_V2_PTCR_TCLKDIR) +- IMX_AUDMUX_V2_PDCR_RXDSEL(5) +- >; +- }; +- +- aud6 { +- fsl,audmux-port = <5>; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_RFSEL(8) | +- IMX_AUDMUX_V2_PTCR_RCSEL(8) | +- IMX_AUDMUX_V2_PTCR_TFSEL(1) | +- IMX_AUDMUX_V2_PTCR_TCSEL(1) | +- IMX_AUDMUX_V2_PTCR_RFSDIR | +- IMX_AUDMUX_V2_PTCR_RCLKDIR | +- IMX_AUDMUX_V2_PTCR_TFSDIR | +- IMX_AUDMUX_V2_PTCR_TCLKDIR) +- IMX_AUDMUX_V2_PDCR_RXDSEL(1) +- >; +- }; +-}; +- +-&ecspi2 { +- cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs &pinctrl_ecspi2_flwp>; +- status = "okay"; +- +- s25fl256s: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <40000000>; +- reg = <0>; +- +- partition@0 { +- label = "SPL (spi)"; +- reg = <0x0 0x20000>; +- read-only; +- }; +- partition@1 { +- label = "u-boot (spi)"; +- reg = <0x20000 0x100000>; +- read-only; +- }; +- partition@2 { +- label = "uboot-env (spi)"; +- reg = <0x120000 0x10000>; +- }; +- partition@3 { +- label = "uboot-envr (spi)"; +- reg = <0x130000 0x10000>; +- }; +- partition@4 { +- label = "linux-recovery (spi)"; +- reg = <0x140000 0x800000>; +- }; +- partition@5 { +- label = "swupdate-fitImg (spi)"; +- reg = <0x940000 0x400000>; +- }; +- partition@6 { +- label = "swupdate-initramfs (spi)"; +- reg = <0xD40000 0x800000>; +- }; +- }; +-}; +- +-&ecspi3 { +- cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-handle = <ðernet_phy0>; +- phy-mode = "rgmii-id"; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- ethernet_phy0: ethernet-phy@0 { +- compatible = "marvell,88E1510"; +- device_type = "ethernet-phy"; +- /* Set LED0 control: */ +- /* On - Link, Blink - Activity, Off - No Link */ +- marvell,reg-init = <3 0x10 0 0x1011>; +- max-speed = <100>; +- reg = <0>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- codec: tfa9879@6c { +- #sound-dai-cells = <0>; +- compatible = "nxp,tfa9879"; +- reg = <0x6C>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- at24@50 { +- compatible = "atmel,24c256"; +- pagesize = <64>; +- reg = <0x50>; +- }; +- +- pfuze100: pmic@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds0: lvds-channel@0 { +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in_lvds0>; +- }; +- }; +- }; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- status = "okay"; +-}; +- +-&ssi2 { +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usbh1_vbus>; +- pinctrl-0 = <&pinctrl_usbh1>; +- status = "okay"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- /* I2S OUTPUT AUD6*/ +- MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 +- MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 +- MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 +- MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 +- >; +- }; +- +- pinctrl_backlight: dispgrp { +- fsl,pins = < +- /* BLEN_OUT */ +- MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 +- MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 +- MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 +- >; +- }; +- +- pinctrl_ecspi2_cs: ecspi2csgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 +- >; +- }; +- +- pinctrl_ecspi2_flwp: ecspi2flwpgrp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 +- >; +- }; +- +- pinctrl_ecspi3: ecspi3grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 +- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 +- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 +- >; +- }; +- +- pinctrl_ecspi3_cs: ecspi3csgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 +- >; +- }; +- +- pinctrl_ecspi3_flwp: ecspi3flwpgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 +- MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_reg_lvds: reqlvdsgrp { +- fsl,pins = < +- /* LVDS_PPEN_OUT */ +- MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbh1: usbh1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D30__USB_H1_OC 0x030b0 +- >; +- }; +- +- pinctrl_usbh1_vbus: usbh1_vbus_grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 +- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 +- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 +- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +- MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x17059 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-dmo-edmqmx6.dts b/scripts/dtc/include-prefixes/arm/imx6q-dmo-edmqmx6.dts +deleted file mode 100644 +index c713ac03b3b9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-dmo-edmqmx6.dts ++++ /dev/null +@@ -1,481 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Data Modul AG +- */ +- +-/dts-v1/; +- +-#include +-#include "imx6q.dtsi" +- +-/ { +- model = "Data Modul eDM-QMX6 Board"; +- compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q"; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- aliases { +- gpio7 = &stmpe_gpio1; +- gpio8 = &stmpe_gpio2; +- stmpe-i2c0 = &stmpe1; +- stmpe-i2c1 = &stmpe2; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_3p3v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_switch: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "usb_otg_switch"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio7 12 0>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_usb_host1: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "usb_host1_en"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 31 0>; +- enable-active-high; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- led-blue { +- label = "blue"; +- gpios = <&stmpe_gpio1 8 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-green { +- label = "green"; +- gpios = <&stmpe_gpio1 9 GPIO_ACTIVE_HIGH>; +- }; +- +- led-pink { +- label = "pink"; +- gpios = <&stmpe_gpio1 10 GPIO_ACTIVE_HIGH>; +- }; +- +- led-red { +- label = "red"; +- gpios = <&stmpe_gpio1 11 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- status = "okay"; +-}; +- +-&ecspi5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi5>; +- cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- flash: m25p80@0 { +- compatible = "m25p80", "jedec,spi-nor"; +- spi-max-frequency = <40000000>; +- reg = <0>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; +- phy-supply = <&vgen2_1v2_eth>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2 +- &pinctrl_stmpe1 +- &pinctrl_stmpe2 +- &pinctrl_pfuze>; +- status = "okay"; +- +- pmic: pfuze100@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- interrupt-parent = <&gpio3>; +- interrupts = <20 8>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- regulator-always-on; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen2_1v2_eth: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vdd_high_in: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +- +- stmpe1: stmpe1601@40 { +- compatible = "st,stmpe1601"; +- reg = <0x40>; +- interrupts = <30 0>; +- interrupt-parent = <&gpio3>; +- vcc-supply = <&sw2_reg>; +- vio-supply = <&sw2_reg>; +- +- stmpe_gpio1: stmpe_gpio { +- #gpio-cells = <2>; +- compatible = "st,stmpe-gpio"; +- }; +- }; +- +- stmpe2: stmpe1601@44 { +- compatible = "st,stmpe1601"; +- reg = <0x44>; +- interrupts = <2 0>; +- interrupt-parent = <&gpio5>; +- vcc-supply = <&sw2_reg>; +- vio-supply = <&sw2_reg>; +- +- stmpe_gpio2: stmpe_gpio { +- #gpio-cells = <2>; +- compatible = "st,stmpe-gpio"; +- }; +- }; +- +- temp1: ad7414@4c { +- compatible = "ad,ad7414"; +- reg = <0x4c>; +- }; +- +- temp2: ad7414@4d { +- compatible = "ad,ad7414"; +- reg = <0x4d>; +- }; +- +- rtc: m41t62@68 { +- compatible = "st,m41t62"; +- reg = <0x68>; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx6q-dmo-edmqmx6 { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000 +- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000 +- >; +- }; +- +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 +- MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 +- >; +- }; +- +- pinctrl_ecspi5: ecspi5rp-1 { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000 +- MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000 +- MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000 +- MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x80000000 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x100b1 +- >; +- }; +- +- pinctrl_pfuze: pfuze100grp1 { +- fsl,pins = < +- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000 +- >; +- }; +- +- pinctrl_stmpe1: stmpe1grp { +- fsl,pins = ; +- }; +- +- pinctrl_stmpe2: stmpe2grp { +- fsl,pins = ; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 +- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 +- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 +- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +- >; +- }; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_host1>; +- disable-over-current; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbotg { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- vmmc-supply = <®_3p3v>; +- non-removable; +- bus-width = <8>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-dms-ba16.dts b/scripts/dtc/include-prefixes/arm/imx6q-dms-ba16.dts +deleted file mode 100644 +index 48fb47e715f6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-dms-ba16.dts ++++ /dev/null +@@ -1,139 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-/dts-v1/; +- +-#include +-#include "imx6q-ba16.dtsi" +- +-/ { +- model = "Advantech DMS-BA16"; +- compatible = "advantech,imx6q-dms-ba16", "advantech,imx6q-ba16", "fsl,imx6q"; +- +- reg_usb_otg_vbus: regulator-usbotgvbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotgvbus>; +- gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sys_mclk: clock-sys-mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <22000000>; +- }; +- +- sound { +- compatible = "fsl,imx6q-ba16-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "imx6q-ba16-sgtl5000"; +- ssi-controller = <&ssi1>; +- audio-codec = <&sgtl5000>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <4>; +- }; +-}; +- +-&ecspi5 { +- cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi5>; +- status = "okay"; +- +- m25_eeprom: m25p80@0 { +- compatible = "atmel,at25256B", "atmel,at25"; +- spi-max-frequency = <20000000>; +- size = <0x8000>; +- pagesize = <64>; +- reg = <0>; +- address-width = <16>; +- }; +-}; +- +-&iomuxc { +- pinctrl_i2c1_gpio: i2c1gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c2_gpio: i2c2gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 +- MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c3_gpio: i2c3gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 +- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 +- >; +- }; +- +- pinctrl_usbotgvbus: usbotgvbusgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 +- >; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&sys_mclk>; +- lrclk-strength = <0x3>; +- VDDA-supply = <®_1p8v>; +- VDDIO-supply = <®_3p3v>; +- }; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- status = "okay"; +-}; +- +-&sata { +- fsl,no-spread-spectrum; +- fsl,transmit-atten-16ths = <12>; +- fsl,transmit-boost-mdB = <3330>; +- fsl,transmit-level-mV = <1133>; +- fsl,receive-dpll-mode = <1>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- dr_mode = "otg"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <8>; +- cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- keep-power-in-suspend; +- wakeup-source; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-ds.dts b/scripts/dtc/include-prefixes/arm/imx6q-ds.dts +deleted file mode 100644 +index b0a63a133977..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-ds.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2021 Dillon Min +-// +-// Based on imx6qdl-sabresd.dtsi which is: +-// Copyright 2012 Freescale Semiconductor, Inc. +-// Copyright 2011 Linaro Ltd. +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-ds.dtsi" +- +-/ { +- model = "DaSheng i.MX6 Quad Com-9xx Board"; +- compatible = "ds,imx6q-sbc", "fsl,imx6q"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-emcon-avari.dts b/scripts/dtc/include-prefixes/arm/imx6q-emcon-avari.dts +deleted file mode 100644 +index 0f582a9d4c0e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-emcon-avari.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 or MIT) +-// +-// Copyright (C) 2018 emtrion GmbH +-// +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-emcon.dtsi" +-#include "imx6qdl-emcon-avari.dtsi" +- +-/ { +- model = "emtrion SoM emCON-MX6 Dual/Quad on Avari"; +- compatible = "emtrion,emcon-mx6-avari", "fsl,imx6q"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-evi.dts b/scripts/dtc/include-prefixes/arm/imx6q-evi.dts +deleted file mode 100644 +index c63f371ede8b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-evi.dts ++++ /dev/null +@@ -1,517 +0,0 @@ +-/* +- * Copyright 2016 United Western Technologies. +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include +-#include +- +-/ { +- model = "Uniwest Evi"; +- compatible = "uniwest,imx6q-evi", "fsl,imx6q"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- reg_usbh1_vbus: regulator-usbhubreset { +- compatible = "regulator-fixed"; +- regulator-name = "usbh1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- startup-delay-us = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1_hubreset>; +- gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_usb_otg_vbus: regulator-usbotgvbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotgvbus>; +- gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- panel { +- compatible = "sharp,lq101k1ly04"; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>; +- status = "okay"; +- +- fpga: fpga@0 { +- compatible = "altr,fpga-passive-serial"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- pinctrl-0 = <&pinctrl_fpgaspi>; +- nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; +- nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&ecspi3 { +- cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>, +- <&gpio4 25 GPIO_ACTIVE_LOW>, +- <&gpio4 26 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3cs>; +- status = "okay"; +-}; +- +-&ecspi5 { +- cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>, +- <&gpio1 13 GPIO_ACTIVE_LOW>, +- <&gpio1 12 GPIO_ACTIVE_LOW>, +- <&gpio2 9 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi5 &pinctrl_ecspi5cs>; +- status = "okay"; +- +- eeprom: m95m02@1 { +- compatible = "st,m95m02", "atmel,at25"; +- size = <262144>; +- pagesize = <256>; +- address-width = <24>; +- spi-max-frequency = <5000000>; +- reg = <1>; +- }; +- +- pb_rtc: rtc@3 { +- compatible = "nxp,rtc-pcf2123"; +- spi-max-frequency = <2450000>; +- spi-cs-high; +- reg = <3>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii"; +- phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; +- interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, +- <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; +- fsl,err006687-workaround-present; +- status = "okay"; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpminand>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&i2c3 { +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c3>; +- pinctrl-1 = <&pinctrl_i2c3_gpio>; +- clock-frequency = <100000>; +- scl-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- sda-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- +- battery: sbs-battery@b { +- compatible = "sbs,sbs-battery"; +- reg = <0x0b>; +- sbs,poll-retry-count = <100>; +- sbs,i2c-retry-count = <100>; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds0: lvds-channel@0 { +- status = "okay"; +- +- port@4 { +- reg = <4>; +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usbh1_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1>; +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- non-removable; +- status = "okay"; +-}; +- +-&weim { +- ranges = <0 0 0x08000000 0x08000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_weimfpga &pinctrl_weimcs>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- /* pwr mcu alert irq */ +- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 +- /* remainder ???? */ +- MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 +- >; +- }; +- +- pinctrl_ecspi1cs: ecspi1csgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 +- >; +- }; +- +- pinctrl_ecspi3: ecspi3grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x10068 +- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x10068 +- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x1f068 +- >; +- }; +- +- pinctrl_ecspi3cs: ecspi3csgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 +- MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 +- MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 +- MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 +- >; +- }; +- +- pinctrl_ecspi5: ecspi5grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x100b1 +- MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x100b1 +- MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x100b1 +- >; +- }; +- +- pinctrl_ecspi5cs: ecspi5csgrp { +- fsl,pins = < +- MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 +- MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 +- MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 +- MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x4001b0a8 +- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 +- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 +- >; +- }; +- +- pinctrl_fpgaspi: fpgaspigrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 +- MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 +- >; +- }; +- +- pinctrl_gpminand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3_gpio: i2c3gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +- MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 +- >; +- }; +- +- pinctrl_weimcs: weimcsgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 +- MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 +- >; +- }; +- +- pinctrl_weimfpga: weimfpgagrp { +- fsl,pins = < +- /* weim misc */ +- MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 +- MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 +- MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 +- MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0xb0b1 +- MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb0b1 +- MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0xb0b1 +- MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0xb0b1 +- MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0xb0b1 +- MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0xb0b1 +- /* weim data */ +- MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 +- MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 +- MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 +- MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 +- MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 +- MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 +- MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 +- MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 +- MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 +- MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 +- MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 +- MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 +- MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 +- MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 +- MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 +- MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 +- MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 +- MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 +- /* weim address */ +- MX6QDL_PAD_EIM_A25__EIM_ADDR25 0xb0b1 +- MX6QDL_PAD_EIM_A24__EIM_ADDR24 0xb0b1 +- MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 +- MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 +- MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 +- MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 +- MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 +- MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 +- MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 +- MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 +- MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 +- MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 +- MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 +- MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 +- MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 +- MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 +- MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 +- MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 +- MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 +- MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 +- MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 +- MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 +- MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 +- MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 +- MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 +- MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x1b0b1 +- MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_usbh1: usbh1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0 +- /* usbh1_b OC */ +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 +- >; +- }; +- +- pinctrl_usbh1_hubreset: usbh1hubresetgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 +- >; +- }; +- +- pinctrl_usbotgvbus: usbotgvbusgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-gk802.dts b/scripts/dtc/include-prefixes/arm/imx6q-gk802.dts +deleted file mode 100644 +index ccc2487d47ca..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-gk802.dts ++++ /dev/null +@@ -1,179 +0,0 @@ +-/* +- * Copyright (C) 2013 Philipp Zabel +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-/dts-v1/; +-#include +-#include +-#include "imx6q.dtsi" +- +-/ { +- model = "Zealz GK802"; +- compatible = "zealz,imx6q-gk802", "fsl,imx6q"; +- +- chosen { +- stdout-path = &uart4; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_3p3v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- recovery-button { +- label = "recovery"; +- gpios = <&gpio3 16 1>; +- linux,code = ; +- wakeup-source; +- }; +- }; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- status = "okay"; +-}; +- +-/* Internal I2C */ +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clock-frequency = <100000>; +- status = "okay"; +- +- /* SDMC DM2016 1024 bit EEPROM + 128 bit OTP */ +- eeprom: dm2016@51 { +- compatible = "sdmc,dm2016"; +- reg = <0x51>; +- }; +-}; +- +-/* External I2C via HDMI */ +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx6q-gk802 { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- /* Recovery button, active-low */ +- MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x100b1 +- /* RTL8192CU enable GPIO, active-low */ +- MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +- >; +- }; +- }; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-/* External USB-A port (USBOTG) */ +-&usbotg { +- disable-over-current; +- status = "okay"; +-}; +- +-/* Internal USB port (USBH1), connected to RTL8192CU */ +-&usbh1 { +- disable-over-current; +- status = "okay"; +-}; +- +-/* External microSD */ +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <4>; +- cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-/* Internal microSD */ +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <4>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-gw51xx.dts b/scripts/dtc/include-prefixes/arm/imx6q-gw51xx.dts +deleted file mode 100644 +index f80173458e3f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-gw51xx.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Gateworks Corporation +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-gw51xx.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 Dual/Quad GW51XX"; +- compatible = "gw,imx6q-gw51xx", "gw,ventana", "fsl,imx6q"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-gw52xx.dts b/scripts/dtc/include-prefixes/arm/imx6q-gw52xx.dts +deleted file mode 100644 +index 6e1c493c9c8c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-gw52xx.dts ++++ /dev/null +@@ -1,75 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Gateworks Corporation +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-gw52xx.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 Dual/Quad GW52XX"; +- compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q"; +-}; +- +-&i2c3 { +- adv7180: camera@20 { +- compatible = "adi,adv7180"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adv7180>; +- reg = <0x20>; +- powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; +- interrupt-parent = <&gpio3>; +- interrupts = <30 IRQ_TYPE_LEVEL_LOW>; +- +- port { +- adv7180_to_ipu2_csi1_mux: endpoint { +- remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>; +- bus-width = <8>; +- }; +- }; +- }; +-}; +- +-&ipu2_csi1_from_ipu2_csi1_mux { +- bus-width = <8>; +-}; +- +-&ipu2_csi1_mux_from_parallel_sensor { +- remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; +- bus-width = <8>; +-}; +- +-&ipu2_csi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu2_csi1>; +-}; +- +-&iomuxc { +- pinctrl_adv7180: adv7180grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 +- >; +- }; +- +- pinctrl_ipu2_csi1: ipu2_csi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 +- MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0 +- MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0 +- MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0 +- MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0 +- MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0 +- MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0 +- MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 +- MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0 +- MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0 +- MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 +- >; +- }; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-gw53xx.dts b/scripts/dtc/include-prefixes/arm/imx6q-gw53xx.dts +deleted file mode 100644 +index f13df8e9c8c4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-gw53xx.dts ++++ /dev/null +@@ -1,75 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Gateworks Corporation +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-gw53xx.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 Dual/Quad GW53XX"; +- compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q"; +-}; +- +-&i2c3 { +- adv7180: camera@20 { +- compatible = "adi,adv7180"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adv7180>; +- reg = <0x20>; +- powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; +- interrupt-parent = <&gpio3>; +- interrupts = <30 IRQ_TYPE_LEVEL_LOW>; +- +- port { +- adv7180_to_ipu2_csi1_mux: endpoint { +- remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>; +- bus-width = <8>; +- }; +- }; +- }; +-}; +- +-&ipu2_csi1_from_ipu2_csi1_mux { +- bus-width = <8>; +-}; +- +-&ipu2_csi1_mux_from_parallel_sensor { +- remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; +- bus-width = <8>; +-}; +- +-&ipu2_csi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu2_csi1>; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_adv7180: adv7180grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 +- >; +- }; +- +- pinctrl_ipu2_csi1: ipu2_csi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 +- MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0 +- MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0 +- MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0 +- MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0 +- MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0 +- MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0 +- MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 +- MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0 +- MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0 +- MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-gw5400-a.dts b/scripts/dtc/include-prefixes/arm/imx6q-gw5400-a.dts +deleted file mode 100644 +index 4cde45d5c90c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-gw5400-a.dts ++++ /dev/null +@@ -1,510 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Gateworks Corporation +- */ +- +-/dts-v1/; +-#include +-#include "imx6q.dtsi" +- +-/ { +- model = "Gateworks Ventana GW5400-A"; +- compatible = "gw,imx6q-gw5400-a", "gw,ventana", "fsl,imx6q"; +- +- /* these are used by bootloader for disabling nodes */ +- aliases { +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- led0 = &led0; +- led1 = &led1; +- led2 = &led2; +- ssi0 = &ssi1; +- spi0 = &ecspi1; +- usb0 = &usbh1; +- usb1 = &usbotg; +- }; +- +- chosen { +- bootargs = "console=ttymxc1,115200"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led0: user1 { +- label = "user1"; +- gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 -> MX6_PANLEDG */ +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led1: user2 { +- label = "user2"; +- gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* 106 -> MX6_PANLEDR */ +- default-state = "off"; +- }; +- +- led2: user3 { +- label = "user3"; +- gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* 111 -> MX6_LOCLED# */ +- default-state = "off"; +- }; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- pps { +- compatible = "pps-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_1p0v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "1P0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_h1_vbus: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- }; +- +- sound { +- compatible = "fsl,imx6q-ventana-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "sgtl5000-audio"; +- ssi-controller = <&ssi1>; +- audio-codec = <&codec>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <4>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- flash: m25p80@0 { +- compatible = "sst,w25q256", "jedec,spi-nor"; +- spi-max-frequency = <30000000>; +- reg = <0>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- eeprom1: eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom2: eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- eeprom3: eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- eeprom4: eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +- +- gpio: pca9555@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- rtc: ds1672@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- pmic: pfuze100@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- accelerometer: mma8450@1c { +- compatible = "fsl,mma8450"; +- reg = <0x1c>; +- }; +- +- codec: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <&sw4_reg>; +- VDDIO-supply = <®_3p3v>; +- }; +- +- touchscreen: egalax_ts@4 { +- compatible = "eeti,egalax_ts"; +- reg = <0x04>; +- interrupt-parent = <&gpio7>; +- interrupts = <12 2>; +- wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&ldb { +- status = "okay"; +-}; +- +-&pcie { +- reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 +- MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 +- MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 +- MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */ +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* user1 led */ +- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* user2 led */ +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* user3 led */ +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ +- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ +- >; +- }; +- +- pinctrl_pps: ppsgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* GPS_PPS */ +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-gw54xx.dts b/scripts/dtc/include-prefixes/arm/imx6q-gw54xx.dts +deleted file mode 100644 +index d5d46908cf6e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-gw54xx.dts ++++ /dev/null +@@ -1,177 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Gateworks Corporation +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-gw54xx.dtsi" +-#include +- +-/ { +- model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX"; +- compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q"; +- +- sound-digital { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "tda1997x-audio"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sound_codec>; +- simple-audio-card,frame-master = <&sound_codec>; +- +- sound_cpu: simple-audio-card,cpu { +- sound-dai = <&ssi2>; +- }; +- +- sound_codec: simple-audio-card,codec { +- sound-dai = <&hdmi_receiver>; +- }; +- }; +-}; +- +-&i2c3 { +- adv7180: camera@20 { +- compatible = "adi,adv7180"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adv7180>; +- reg = <0x20>; +- powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; +- interrupt-parent = <&gpio3>; +- interrupts = <30 IRQ_TYPE_LEVEL_LOW>; +- +- port { +- adv7180_to_ipu2_csi1_mux: endpoint { +- remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>; +- bus-width = <8>; +- }; +- }; +- }; +- +- hdmi_receiver: hdmi-receiver@48 { +- compatible = "nxp,tda19971"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tda1997x>; +- reg = <0x48>; +- interrupt-parent = <&gpio1>; +- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; +- DOVDD-supply = <®_3p3v>; +- AVDD-supply = <&sw4_reg>; +- DVDD-supply = <&sw4_reg>; +- #sound-dai-cells = <0>; +- nxp,audout-format = "i2s"; +- nxp,audout-layout = <0>; +- nxp,audout-width = <16>; +- nxp,audout-mclk-fs = <128>; +- /* +- * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] +- * and Y[11:4] across 16bits in the same cycle +- * which we map to VP[15:08]<->CSI_DATA[19:12] +- */ +- nxp,vidout-portcfg = +- /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/ +- < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, +- /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/ +- < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, +- /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/ +- < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, +- /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/ +- < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; +- +- port { +- tda1997x_to_ipu1_csi0_mux: endpoint { +- remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; +- bus-width = <16>; +- hsync-active = <1>; +- vsync-active = <1>; +- data-active = <1>; +- }; +- }; +- }; +-}; +- +-&ipu1_csi0_from_ipu1_csi0_mux { +- bus-width = <16>; +-}; +- +-&ipu1_csi0_mux_from_parallel_sensor { +- remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; +- bus-width = <16>; +-}; +- +-&ipu1_csi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_csi0>; +-}; +- +-&ipu2_csi1_from_ipu2_csi1_mux { +- bus-width = <8>; +-}; +- +-&ipu2_csi1_mux_from_parallel_sensor { +- remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; +- bus-width = <8>; +-}; +- +-&ipu2_csi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu2_csi1>; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_adv7180: adv7180grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 +- >; +- }; +- +- pinctrl_ipu1_csi0: ipu1_csi0grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 +- MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 +- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 +- MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 +- >; +- }; +- +- pinctrl_ipu2_csi1: ipu2_csi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 +- MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0 +- MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0 +- MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0 +- MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0 +- MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0 +- MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0 +- MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 +- MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0 +- MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0 +- MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 +- >; +- }; +- +- pinctrl_tda1997x: tda1997xgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-gw551x.dts b/scripts/dtc/include-prefixes/arm/imx6q-gw551x.dts +deleted file mode 100644 +index 2c7feeef1b0e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-gw551x.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-/* +- * Copyright 2014 Gateworks Corporation +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-gw551x.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 Dual/Quad GW551X"; +- compatible = "gw,imx6q-gw551x", "gw,ventana", "fsl,imx6q"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-gw552x.dts b/scripts/dtc/include-prefixes/arm/imx6q-gw552x.dts +deleted file mode 100644 +index c973b7304225..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-gw552x.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2014 Gateworks Corporation +- */ +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-gw552x.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 Dual/Quad GW552X"; +- compatible = "gw,imx6q-gw552x", "gw,ventana", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-gw553x.dts b/scripts/dtc/include-prefixes/arm/imx6q-gw553x.dts +deleted file mode 100644 +index e9c224cea752..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-gw553x.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-/* +- * Copyright 2016 Gateworks Corporation +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-gw553x.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 Dual/Quad GW553X"; +- compatible = "gw,imx6q-gw553x", "gw,ventana", "fsl,imx6q"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-gw560x.dts b/scripts/dtc/include-prefixes/arm/imx6q-gw560x.dts +deleted file mode 100644 +index 735f2bbf1439..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-gw560x.dts ++++ /dev/null +@@ -1,59 +0,0 @@ +-/* +- * Copyright 2017 Gateworks Corporation +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-gw560x.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 Dual/Quad GW560X"; +- compatible = "gw,imx6q-gw560x", "gw,ventana", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-gw5903.dts b/scripts/dtc/include-prefixes/arm/imx6q-gw5903.dts +deleted file mode 100644 +index a182e4cb0e6e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-gw5903.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-/* +- * Copyright 2017 Gateworks Corporation +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-gw5903.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 Dual/Quad GW5903"; +- compatible = "gw,imx6q-gw5903", "gw,ventana", "fsl,imx6q"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-gw5904.dts b/scripts/dtc/include-prefixes/arm/imx6q-gw5904.dts +deleted file mode 100644 +index ca1e2ae3341e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-gw5904.dts ++++ /dev/null +@@ -1,59 +0,0 @@ +-/* +- * Copyright 2017 Gateworks Corporation +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-gw5904.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 Dual/Quad GW5904"; +- compatible = "gw,imx6q-gw5904", "gw,ventana", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-gw5907.dts b/scripts/dtc/include-prefixes/arm/imx6q-gw5907.dts +deleted file mode 100644 +index b25526ef5886..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-gw5907.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2019 Gateworks Corporation +- */ +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-gw5907.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 Dual/Quad GW5907"; +- compatible = "gw,imx6q-gw5907", "gw,ventana", "fsl,imx6q"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-gw5910.dts b/scripts/dtc/include-prefixes/arm/imx6q-gw5910.dts +deleted file mode 100644 +index 6aafa2fcee08..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-gw5910.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2019 Gateworks Corporation +- */ +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-gw5910.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 Dual/Quad GW5910"; +- compatible = "gw,imx6q-gw5910", "gw,ventana", "fsl,imx6q"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-gw5912.dts b/scripts/dtc/include-prefixes/arm/imx6q-gw5912.dts +deleted file mode 100644 +index 4dcbd943cd93..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-gw5912.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2019 Gateworks Corporation +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-gw5912.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 Dual/Quad GW5912"; +- compatible = "gw,imx6q-gw5912", "gw,ventana", "fsl,imx6q"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-gw5913.dts b/scripts/dtc/include-prefixes/arm/imx6q-gw5913.dts +deleted file mode 100644 +index 6f511f1665fd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-gw5913.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2019 Gateworks Corporation +- */ +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-gw5913.dtsi" +- +-/ { +- model = "Gateworks Ventana i.MX6 Dual/Quad GW5913"; +- compatible = "gw,imx6q-gw5913", "gw,ventana", "fsl,imx6q"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-h100.dts b/scripts/dtc/include-prefixes/arm/imx6q-h100.dts +deleted file mode 100644 +index b8feadbff967..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-h100.dts ++++ /dev/null +@@ -1,382 +0,0 @@ +-/* +- * Copyright (C) 2015 Lucas Stach +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-brcm.dtsi" +- +-/ { +- model = "Auvidea H100"; +- compatible = "auvidea,h100", "fsl,imx6q"; +- +- /* Will be filled by the bootloader */ +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0>; +- }; +- +- aliases { +- rtc0 = &rtc; +- rtc1 = &snvs_rtc; +- }; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- hdmi_osc: hdmi-osc { +- compatible = "fixed-clock"; +- clock-output-names = "hdmi-osc"; +- clock-frequency = <27000000>; +- #clock-cells = <0>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_h100_leds>; +- +- led0: power { +- label = "power"; +- gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- +- led1: stream { +- label = "stream"; +- gpios = <&gpio2 29 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led2: rec { +- label = "rec"; +- gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_hdmi: regulator-hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_h100_reg_hdmi>; +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; +- regulator-name = "V_HDMI"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_usbh1_vbus: regulator-usb-h1-vbus { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_h100_usbh1_vbus>; +- regulator-name = "USB_H1_VBUS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usbotg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_h100_usbotg_vbus>; +- regulator-name = "USB_OTG_VBUS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- sound-sgtl5000 { +- compatible = "fsl,imx-audio-sgtl5000"; +- model = "H100 on-board codec"; +- audio-codec = <&sgtl5000>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-ext-port = <5>; +- mux-int-port = <1>; +- ssi-controller = <&ssi1>; +- }; +-}; +- +-&audmux { +- status = "okay"; +-}; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_h100_hdmi>; +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_h100_i2c1>; +- status = "okay"; +- +- eeprom: 24c02@51 { +- compatible = "microchip,24c02", "atmel,24c02"; +- reg = <0x51>; +- }; +- +- rtc: pcf8523@68 { +- compatible = "nxp,pcf8523"; +- reg = <0x68>; +- }; +- +- sgtl5000: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_h100_sgtl5000>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; +- }; +- +- tc358743: tc358743@f { +- compatible = "toshiba,tc358743"; +- reg = <0x0f>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_h100_tc358743>; +- clocks = <&hdmi_osc>; +- clock-names = "refclk"; +- reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; +- /* IRQ has a wrong pull resistor which renders it useless */ +- +- port { +- tc358743_out: endpoint { +- remote-endpoint = <&mipi_csi2_in>; +- data-lanes = <1 2 3 4>; +- clock-lanes = <0>; +- clock-noncontinuous; +- link-frequencies = /bits/ 64 <297000000>; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_h100_i2c2>; +- status = "okay"; +-}; +- +-&iomuxc { +- h100 { +- pinctrl_h100_hdmi: h100-hdmi { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 +- >; +- }; +- +- pinctrl_h100_i2c1: h100-i2c1 { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_h100_i2c2: h100-i2c2 { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_h100_leds: pinctrl-h100-leds { +- fsl,pins = < +- MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 +- MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 +- MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 +- >; +- }; +- +- pinctrl_h100_reg_hdmi: h100-reg-hdmi { +- fsl,pins = < +- MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 +- >; +- }; +- +- pinctrl_h100_sgtl5000: h100-sgtl5000 { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 +- MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 +- MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 +- MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 +- MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 +- >; +- }; +- +- pinctrl_h100_tc358743: h100-tc358743 { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 +- >; +- }; +- +- pinctrl_h100_uart2: h100-uart2 { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_h100_usbh1_vbus: hummingboard-usbh1-vbus { +- fsl,pins = < +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 +- >; +- }; +- +- pinctrl_h100_usbotg_id: hummingboard-usbotg-id { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 +- >; +- }; +- +- pinctrl_h100_usbotg_vbus: hummingboard-usbotg-vbus { +- fsl,pins = < +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 +- >; +- }; +- +- pinctrl_h100_usdhc2: h100-usdhc2 { +- fsl,pins = < +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 +- MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 +- >; +- }; +- +- pinctrl_h100_usdhc2_100mhz: h100-usdhc2-100mhz { +- fsl,pins = < +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 +- MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 +- >; +- }; +- +- pinctrl_h100_usdhc2_200mhz: h100-usdhc2-200mhz { +- fsl,pins = < +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 +- MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 +- >; +- }; +- }; +-}; +- +-&mipi_csi { +- status = "okay"; +- +- port { +- mipi_csi2_in: endpoint { +- remote-endpoint = <&tc358743_out>; +- data-lanes = <1 2 3 4>; +- clock-lanes = <0>; +- clock-noncontinuous; +- link-frequencies = /bits/ 64 <297000000>; +- }; +- }; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_h100_uart2>; +- status = "okay"; +-}; +- +-&usbh1 { +- disable-over-current; +- vbus-supply = <®_usbh1_vbus>; +- status = "okay"; +-}; +- +-&usbotg { +- disable-over-current; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_h100_usbotg_id>; +- vbus-supply = <®_usbotg_vbus>; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_h100_usdhc2>; +- pinctrl-1 = <&pinctrl_h100_usdhc2_100mhz>; +- pinctrl-2 = <&pinctrl_h100_usdhc2_200mhz>; +- vmmc-supply = <®_3p3v>; +- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-hummingboard-emmc-som-v15.dts b/scripts/dtc/include-prefixes/arm/imx6q-hummingboard-emmc-som-v15.dts +deleted file mode 100644 +index c51b4e4fd71e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-hummingboard-emmc-som-v15.dts ++++ /dev/null +@@ -1,61 +0,0 @@ +-/* +- * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) +- * Based on dt work by Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-ti.dtsi" +-#include "imx6qdl-sr-som-emmc.dtsi" +-#include "imx6qdl-hummingboard.dtsi" +- +-/ { +- model = "SolidRun HummingBoard Dual/Quad (1.5som+emmc)"; +- compatible = "solidrun,hummingboard/q", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +- fsl,transmit-level-mV = <1025>; +- fsl,transmit-boost-mdB = <3330>; +- fsl,transmit-atten-16ths = <9>; +- fsl,receive-eq-mdB = <3000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-hummingboard-som-v15.dts b/scripts/dtc/include-prefixes/arm/imx6q-hummingboard-som-v15.dts +deleted file mode 100644 +index e4132d62ffa2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-hummingboard-som-v15.dts ++++ /dev/null +@@ -1,60 +0,0 @@ +-/* +- * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) +- * Based on dt work by Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-ti.dtsi" +-#include "imx6qdl-hummingboard.dtsi" +- +-/ { +- model = "SolidRun HummingBoard Dual/Quad (1.5som)"; +- compatible = "solidrun,hummingboard/q", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +- fsl,transmit-level-mV = <1025>; +- fsl,transmit-boost-mdB = <3330>; +- fsl,transmit-atten-16ths = <9>; +- fsl,receive-eq-mdB = <3000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-hummingboard.dts b/scripts/dtc/include-prefixes/arm/imx6q-hummingboard.dts +deleted file mode 100644 +index 8c9e94e648a7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-hummingboard.dts ++++ /dev/null +@@ -1,60 +0,0 @@ +-/* +- * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) +- * Based on dt work by Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-brcm.dtsi" +-#include "imx6qdl-hummingboard.dtsi" +- +-/ { +- model = "SolidRun HummingBoard Dual/Quad"; +- compatible = "solidrun,hummingboard/q", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +- fsl,transmit-level-mV = <1025>; +- fsl,transmit-boost-mdB = <3330>; +- fsl,transmit-atten-16ths = <9>; +- fsl,receive-eq-mdB = <3000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-hummingboard2-emmc-som-v15.dts b/scripts/dtc/include-prefixes/arm/imx6q-hummingboard2-emmc-som-v15.dts +deleted file mode 100644 +index 1998ebfa0fe0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-hummingboard2-emmc-som-v15.dts ++++ /dev/null +@@ -1,63 +0,0 @@ +-/* +- * Device Tree file for SolidRun HummingBoard2 +- * Copyright (C) 2015 Rabeeh Khoury +- * Based on work by Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License. +- * +- * This file is distributed in the hope that it will be useful +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-emmc.dtsi" +-#include "imx6qdl-sr-som-ti.dtsi" +-#include "imx6qdl-hummingboard2.dtsi" +- +-/ { +- model = "SolidRun HummingBoard2 Dual/Quad (1.5som+emmc)"; +- compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +- fsl,transmit-level-mV = <1104>; +- fsl,transmit-boost-mdB = <0>; +- fsl,transmit-atten-16ths = <9>; +- fsl,no-spread-spectrum; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-hummingboard2-som-v15.dts b/scripts/dtc/include-prefixes/arm/imx6q-hummingboard2-som-v15.dts +deleted file mode 100644 +index d3ad7329cd6d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-hummingboard2-som-v15.dts ++++ /dev/null +@@ -1,62 +0,0 @@ +-/* +- * Device Tree file for SolidRun HummingBoard2 +- * Copyright (C) 2015 Rabeeh Khoury +- * Based on work by Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License. +- * +- * This file is distributed in the hope that it will be useful +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-ti.dtsi" +-#include "imx6qdl-hummingboard2.dtsi" +- +-/ { +- model = "SolidRun HummingBoard2 Dual/Quad (1.5som)"; +- compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +- fsl,transmit-level-mV = <1104>; +- fsl,transmit-boost-mdB = <0>; +- fsl,transmit-atten-16ths = <9>; +- fsl,no-spread-spectrum; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-hummingboard2.dts b/scripts/dtc/include-prefixes/arm/imx6q-hummingboard2.dts +deleted file mode 100644 +index 5249f53dcdbc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-hummingboard2.dts ++++ /dev/null +@@ -1,61 +0,0 @@ +-/* +- * Copyright (C) 2015 Rabeeh Khoury +- * Based on dt work by Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-brcm.dtsi" +-#include "imx6qdl-hummingboard2.dtsi" +-#include "imx6qdl-hummingboard2-emmc.dtsi" +- +-/ { +- model = "SolidRun HummingBoard2 Dual/Quad"; +- compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +- fsl,transmit-level-mV = <1104>; +- fsl,transmit-boost-mdB = <0>; +- fsl,transmit-atten-16ths = <9>; +- fsl,no-spread-spectrum; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-icore-mipi.dts b/scripts/dtc/include-prefixes/arm/imx6q-icore-mipi.dts +deleted file mode 100644 +index d51745268dbf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-icore-mipi.dts ++++ /dev/null +@@ -1,33 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright (C) 2017 Engicam S.r.l. +- * Copyright (C) 2017 Amarula Solutions B.V. +- * Author: Jagan Teki +- */ +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-icore-1.5.dtsi" +- +-/ { +- model = "Engicam i.CoreM6 1.5 Quad/Dual MIPI Starter Kit"; +- compatible = "engicam,imx6-icore", "fsl,imx6q"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&mipi_csi { +- status = "okay"; +-}; +- +-&ov5640 { +- status = "okay"; +-}; +- +-&usdhc3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-icore-ofcap10.dts b/scripts/dtc/include-prefixes/arm/imx6q-icore-ofcap10.dts +deleted file mode 100644 +index 02aca1e28ce3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-icore-ofcap10.dts ++++ /dev/null +@@ -1,44 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2016 Amarula Solutions B.V. +- * Copyright (C) 2016 Engicam S.r.l. +- */ +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-icore.dtsi" +- +-/ { +- model = "Engicam i.CoreM6 Quad/Dual OpenFrame Capacitive touch 10.1 Kit"; +- compatible = "engicam,imx6-icore", "fsl,imx6q"; +- +- panel { +- compatible = "ampire,am-1280800n3tzqw-t00h"; +- backlight = <&backlight_lvds>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <24>; +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-icore-ofcap12.dts b/scripts/dtc/include-prefixes/arm/imx6q-icore-ofcap12.dts +deleted file mode 100644 +index 241811c52b62..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-icore-ofcap12.dts ++++ /dev/null +@@ -1,43 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2016 Amarula Solutions B.V. +- * Copyright (C) 2016 Engicam S.r.l. +- */ +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-icore.dtsi" +- +-/ { +- model = "Engicam i.CoreM6 Quad/Dual OpenFrame Capacitive touch 12 Kit"; +- compatible = "engicam,imx6-icore", "fsl,imx6q"; +- +- panel { +- compatible = "koe,tx31d200vm0baa"; +- backlight = <&backlight_lvds>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- reg = <0>; +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-icore-rqs.dts b/scripts/dtc/include-prefixes/arm/imx6q-icore-rqs.dts +deleted file mode 100644 +index cf6ba724f497..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-icore-rqs.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2015 Amarula Solutions B.V. +- * Copyright (C) 2015 Engicam S.r.l. +- */ +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-icore-rqs.dtsi" +- +-/ { +- model = "Engicam i.CoreM6 Quad/Dual RQS Starter Kit"; +- compatible = "engicam,imx6-icore-rqs", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-icore.dts b/scripts/dtc/include-prefixes/arm/imx6q-icore.dts +deleted file mode 100644 +index fe28c3cf54c0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-icore.dts ++++ /dev/null +@@ -1,57 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright (C) 2016 Amarula Solutions B.V. +- * Copyright (C) 2016 Engicam S.r.l. +- */ +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-icore.dtsi" +- +-/ { +- model = "Engicam i.CoreM6 Quad/Dual Starter Kit"; +- compatible = "engicam,imx6-icore", "fsl,imx6q"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&can2 { +- status = "okay"; +-}; +- +-&i2c1 { +- max11801: touchscreen@48 { +- compatible = "maxim,max11801"; +- reg = <0x48>; +- interrupt-parent = <&gpio3>; +- interrupts = <31 IRQ_TYPE_EDGE_FALLING>; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <18>; +- status = "okay"; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing0 { +- clock-frequency = <60000000>; +- hactive = <800>; +- vactive = <480>; +- hback-porch = <30>; +- hfront-porch = <30>; +- vback-porch = <5>; +- vfront-porch = <5>; +- hsync-len = <64>; +- vsync-len = <20>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-kontron-samx6i.dtsi b/scripts/dtc/include-prefixes/arm/imx6q-kontron-samx6i.dtsi +deleted file mode 100644 +index 4d6a0c3e8455..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-kontron-samx6i.dtsi ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright 2019 (C) Pengutronix, Marco Felsch +- */ +- +-#include "imx6q.dtsi" +-#include "imx6qdl-kontron-samx6i.dtsi" +-#include +- +-/ { +- model = "Kontron SMARC sAMX6i Quad/Dual"; +- compatible = "kontron,imx6q-samx6i", "fsl,imx6q"; +-}; +- +-/* Quad/Dual SoMs have 3 chip-select signals */ +-&ecspi4 { +- cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>, +- <&gpio3 29 GPIO_ACTIVE_LOW>, +- <&gpio3 25 GPIO_ACTIVE_LOW>; +-}; +- +-&pinctrl_ecspi4 { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 +- +- /* SPI4_IMX_CS2# - connected to internal flash */ +- MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0 +- /* SPI4_IMX_CS0# - connected to SMARC SPI0_CS0# */ +- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 +- /* SPI4_CS3# - connected to SMARC SPI0_CS1# */ +- MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0 +- >; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-kp-tpc.dts b/scripts/dtc/include-prefixes/arm/imx6q-kp-tpc.dts +deleted file mode 100644 +index 50fbf46d17c2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-kp-tpc.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2018 +- * Lukasz Majewski, DENX Software Engineering, lukma@denx.de +- */ +- +-/dts-v1/; +- +-#include "imx6q-kp.dtsi" +- +-/ { +- model = "Freescale i.MX6 Qwuad K+P TPC Board"; +- compatible = "kiebackpeter,imx6q-tpc", "fsl,imx6q"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&lcd_display_in>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-kp.dtsi b/scripts/dtc/include-prefixes/arm/imx6q-kp.dtsi +deleted file mode 100644 +index 1ade0bff681d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-kp.dtsi ++++ /dev/null +@@ -1,434 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2018 +- * Lukasz Majewski, DENX Software Engineering, lukma@denx.de +- */ +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +- +-#include +-#include +-#include +- +-/ { +- backlight_lcd: backlight-lcd { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 5000000>; +- brightness-levels = <0 255>; +- num-interpolated-steps = <255>; +- default-brightness-level = <250>; +- }; +- +- beeper { +- compatible = "pwm-beeper"; +- pwms = <&pwm2 0 500000>; +- }; +- +- lcd_display: display { +- compatible = "fsl,imx-parallel-display"; +- #address-cells = <1>; +- #size-cells = <0>; +- interface-pix-fmt = "rgb24"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1>; +- +- port@0 { +- reg = <0>; +- +- lcd_display_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lcd_display_out: endpoint { +- remote-endpoint = <&lcd_panel_in>; +- }; +- }; +- }; +- +- lcd_panel: lcd-panel { +- compatible = "auo,g070vvn01"; +- backlight = <&backlight_lcd>; +- power-supply = <®_display>; +- +- port { +- lcd_panel_in: endpoint { +- remote-endpoint = <&lcd_display_out>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- green { +- label = "led1"; +- gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "gpio"; +- default-state = "off"; +- }; +- +- red { +- label = "led0"; +- gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "gpio"; +- default-state = "off"; +- }; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_audio: regulator-audio { +- compatible = "regulator-fixed"; +- regulator-name = "sgtl5000-supply"; +- gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- reg_display: regulator-display { +- compatible = "regulator-fixed"; +- regulator-name = "display-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_h1_vbus: regulator-usb_h1_vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "imx6q-sgtl5000-audio"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&codec_dai>; +- simple-audio-card,frame-master = <&codec_dai>; +- +- cpu_dai: simple-audio-card,cpu { +- sound-dai = <&ssi1>; +- }; +- +- codec_dai: simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +- +- ssi1 { +- fsl,audmux-port = <0>; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_SYN | +- IMX_AUDMUX_V2_PTCR_TFSEL(2) | +- IMX_AUDMUX_V2_PTCR_TCSEL(2) | +- IMX_AUDMUX_V2_PTCR_TFSDIR | +- IMX_AUDMUX_V2_PTCR_TCLKDIR) +- IMX_AUDMUX_V2_PDCR_RXDSEL(2) +- >; +- }; +- +- aud3 { +- fsl,audmux-port = <2>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN +- IMX_AUDMUX_V2_PDCR_RXDSEL(0) +- >; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii"; +- fsl,magic-packet; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- touchscreen@5d { +- compatible = "goodix,gt911"; +- reg = <0x5d>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ts>; +- interrupt-parent = <&gpio1>; +- interrupts = <9 IRQ_TYPE_EDGE_FALLING>; +- irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; +- }; +- +- ds1307: rtc@32 { +- compatible = "dallas,ds1307"; +- reg = <0x32>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- sgtl5000: audio-codec@a { +- compatible = "fsl,sgtl5000"; +- #sound-dai-cells = <0>; +- reg = <0x0a>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_codec>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; +- }; +-}; +- +-&iomuxc { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- >; +- }; +- +- pinctrl_codec: codecgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 +- /* sgtl5000 sys_mclk clock routed to CLKO1 */ +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- >; +- }; +- +- pinctrl_flexcan1: can1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 +- MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan2: can2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_ipu1: ipu1grp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_ts: tsgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 +- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 +- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 +- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 +- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +- >; +- }; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&pwm2 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- uart-has-rtscts; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <8>; +- non-removable; +- no-1-8-v; +- keep-power-in-suspend; +- status = "okay"; +-}; +- +-&wdog1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-logicpd.dts b/scripts/dtc/include-prefixes/arm/imx6q-logicpd.dts +deleted file mode 100644 +index 46a4ddedb423..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-logicpd.dts ++++ /dev/null +@@ -1,130 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright (C) 2019 Logic PD, Inc. +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6-logicpd-som.dtsi" +-#include "imx6-logicpd-baseboard.dtsi" +- +-/ { +- model = "Logic PD i.MX6QD SOM-M3"; +- compatible = "logicpd,imx6q-logicpd", "fsl,imx6q"; +- +- backlight: backlight-lvds { +- compatible = "pwm-backlight"; +- pwms = <&pwm3 0 20000 0>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- power-supply = <®_lcd>; +- }; +- +- panel-lvds0 { +- compatible = "okaya,rs800480t-7x0gp"; +- power-supply = <®_lcd_reset>; +- backlight = <&backlight>; +- +- port { +- panel_in_lvds0: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +- +- reg_lcd: regulator-lcd { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd_reg>; +- compatible = "regulator-fixed"; +- regulator-name = "lcd_panel_pwr"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_3v3>; +- startup-delay-us = <500000>; +- }; +- +- reg_lcd_reset: regulator-lcd-reset { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd_reset>; +- compatible = "regulator-fixed"; +- regulator-name = "nLCD_RESET"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_lcd>; +- }; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>, +- <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, +- <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, +- <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, +- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, +- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- status = "okay"; +-}; +- +-&i2c1 { +- touchscreen@26 { +- compatible = "ilitek,ili2117"; +- reg = <0x26>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_touchscreen>; +- interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_RISING>; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <24>; +- status = "okay"; +- +- port@4 { +- reg = <4>; +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in_lvds0>; +- }; +- }; +- }; +- +-}; +- +-&pwm3 { +- status = "okay"; +-}; +- +-®_hdmi { +- regulator-always-on; /* Without this, the level shifter on HDMI doesn't turn on */ +-}; +- +-&iomuxc { +- pinctrl_lcd_reg: lcdreg { +- fsl,pins = < +- MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */ +- >; +- }; +- +- pinctrl_lcd_reset: lcdreset { +- fsl,pins = < +- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */ +- >; +- }; +- +- pinctrl_touchscreen: touchscreengrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* TOUCH_nPINTDAV */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-marsboard.dts b/scripts/dtc/include-prefixes/arm/imx6q-marsboard.dts +deleted file mode 100644 +index 05ee28388229..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-marsboard.dts ++++ /dev/null +@@ -1,417 +0,0 @@ +-/* +- * Copyright (C) 2016 Sergio Prado (sergio.prado@e-labworks.com) +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include +- +-/ { +- model = "Embest MarS Board i.MX6Dual"; +- compatible = "embest,imx6q-marsboard", "fsl,imx6q"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led>; +- +- user1 { +- label = "imx6:green:user1"; +- gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- linux,default-trigger = "heartbeat"; +- }; +- +- user2 { +- label = "imx6:green:user2"; +- gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- m25p80@0 { +- compatible = "microchip,sst25vf016b"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-handle = <&rgmii_phy>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Atheros AR8035 PHY */ +- rgmii_phy: ethernet-phy@4 { +- reg = <4>; +- interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- reset-deassert-us = <1000>; +- }; +- }; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- status = "okay"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "okay"; +-}; +- +-&pwm4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbh1 { +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- dr_mode = "otg"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- vmmc-supply = <®_3p3v>; +- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- vmmc-supply = <®_3p3v>; +- non-removable; +- status = "okay"; +-}; +- +-&iomuxc { +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000b1 /* CS0 */ +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 +- /* AR8035 pin strapping: IO voltage: pull up */ +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- /* AR8035 pin strapping: PHYADDR#0: pull down */ +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 +- /* AR8035 pin strapping: PHYADDR#1: pull down */ +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 +- /* AR8035 pin strapping: MODE#1: pull up */ +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- /* AR8035 pin strapping: MODE#3: pull up */ +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- /* AR8035 pin strapping: MODE#0: pull down */ +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 +- /* GPIO16 -> AR8035 25MHz */ +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- /* RGMII_nRST */ +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 +- /* AR8035 interrupt */ +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_led: ledgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* LED1 */ +- MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* LED2 */ +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +- MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* USB OTG POWER ENABLE */ +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* WP */ +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17009 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10009 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17009 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17009 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17009 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17009 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x17009 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-mccmon6.dts b/scripts/dtc/include-prefixes/arm/imx6q-mccmon6.dts +deleted file mode 100644 +index 55692c73943d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-mccmon6.dts ++++ /dev/null +@@ -1,469 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright 2016-2017 +- * Lukasz Majewski, DENX Software Engineering, lukma@denx.de +- */ +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +- +-#include +-#include +- +-/ { +- model = "Liebherr (LWN) monitor6 i.MX6 Quad Board"; +- compatible = "lwn,mccmon6", "fsl,imx6q"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +- +- backlight_lvds: backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_backlight>; +- pwms = <&pwm2 0 5000000 PWM_POLARITY_INVERTED>; +- brightness-levels = < 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100 101 102 103 104 105 106 107 108 109 +- 110 111 112 113 114 115 116 117 118 119 +- 120 121 122 123 124 125 126 127 128 129 +- 130 131 132 133 134 135 136 137 138 139 +- 140 141 142 143 144 145 146 147 148 149 +- 150 151 152 153 154 155 156 157 158 159 +- 160 161 162 163 164 165 166 167 168 169 +- 170 171 172 173 174 175 176 177 178 179 +- 180 181 182 183 184 185 186 187 188 189 +- 190 191 192 193 194 195 196 197 198 199 +- 200 201 202 203 204 205 206 207 208 209 +- 210 211 212 213 214 215 216 217 218 219 +- 220 221 222 223 224 225 226 227 228 229 +- 230 231 232 233 234 235 236 237 238 239 +- 240 241 242 243 244 245 246 247 248 249 +- 250 251 252 253 254 255>; +- default-brightness-level = <50>; +- enable-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; +- }; +- +- reg_lvds: regulator-lvds { +- compatible = "regulator-fixed"; +- regulator-name = "lvds_ppen"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_lvds>; +- gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- panel-lvds0 { +- compatible = "innolux,g121x1-l03"; +- backlight = <&backlight_lvds>; +- power-supply = <®_lvds>; +- +- port { +- panel_in_lvds0: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +-}; +- +-&ecspi3 { +- cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>; +- status = "okay"; +- +- s25sl032p: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <40000000>; +- reg = <0>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii"; +- phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; +- interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, +- <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- pfuze100: pmic@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds0: lvds-channel@0 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <24>; +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in_lvds0>; +- }; +- }; +- }; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&weim { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; +- ranges = <0 0 0x08000000 0x08000000>; +- status = "okay"; +- +- nor@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x02000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- bank-width = <2>; +- use-advanced-sector-protection; +- fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 +- 0x0000c000 0x1404a38e 0x00000000>; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- +- pinctrl_backlight: dispgrp { +- fsl,pins = < +- /* BLEN_OUT */ +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +- >; +- }; +- +- pinctrl_ecspi3: ecspi3grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 +- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 +- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 +- >; +- }; +- +- pinctrl_ecspi3_cs: ecspi3csgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 +- >; +- }; +- +- pinctrl_ecspi3_flwp: ecspi3flwpgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x80000000 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 +- MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_reg_lvds: reqlvdsgrp { +- fsl,pins = < +- /* LVDS_PPEN_OUT */ +- MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 +- >; +- }; +- +- pinctrl_weim_cs0: weimcs0grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 +- >; +- }; +- +- pinctrl_weim_nor: weimnorgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 +- MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 +- MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 +- MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 +- MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 +- MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 +- MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 +- MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 +- MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 +- MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 +- MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 +- MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 +- MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 +- MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 +- MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 +- MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 +- MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 +- MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 +- MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 +- MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 +- MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 +- MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 +- MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 +- MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 +- MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 +- MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 +- MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 +- MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 +- MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 +- MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 +- MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 +- MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 +- MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 +- MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 +- MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 +- MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 +- MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 +- MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 +- MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 +- MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 +- MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 +- MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 +- MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-nitrogen6_max.dts b/scripts/dtc/include-prefixes/arm/imx6q-nitrogen6_max.dts +deleted file mode 100644 +index 03bec0c53063..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-nitrogen6_max.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright 2015 Boundary Devices, Inc. +- */ +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-nitrogen6_max.dtsi" +- +-/ { +- model = "Boundary Devices i.MX6 Quad Nitrogen6_MAX Board"; +- compatible = "boundary,imx6q-nitrogen6_max", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-nitrogen6_som2.dts b/scripts/dtc/include-prefixes/arm/imx6q-nitrogen6_som2.dts +deleted file mode 100644 +index eb4eecb6ed22..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-nitrogen6_som2.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright 2016 Boundary Devices, Inc. +- */ +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-nitrogen6_som2.dtsi" +- +-/ { +- model = "Boundary Devices i.MX6 Quad Nitrogen6_SOM2 Board"; +- compatible = "boundary,imx6q-nitrogen6_som2", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-nitrogen6x.dts b/scripts/dtc/include-prefixes/arm/imx6q-nitrogen6x.dts +deleted file mode 100644 +index 435445a34ad0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-nitrogen6x.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright 2013 Boundary Devices, Inc. +- * Copyright 2012 Freescale Semiconductor, Inc. +- * Copyright 2011 Linaro Ltd. +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-nitrogen6x.dtsi" +- +-/ { +- model = "Boundary Devices i.MX6 Quad Nitrogen6x Board"; +- compatible = "boundary,imx6q-nitrogen6x", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-novena.dts b/scripts/dtc/include-prefixes/arm/imx6q-novena.dts +deleted file mode 100644 +index 225cf6b7a7a4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-novena.dts ++++ /dev/null +@@ -1,803 +0,0 @@ +-/* +- * Copyright 2015 Sutajio Ko-Usagi PTE LTD +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include +-#include +- +-/ { +- model = "Kosagi Novena Dual/Quad"; +- compatible = "kosagi,imx6q-novena", "fsl,imx6q"; +- +- /* Will be filled by the bootloader */ +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0>; +- }; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 10000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_backlight_novena>; +- power-supply = <®_lvds_lcd>; +- brightness-levels = <0 3 6 12 16 24 32 48 64 96 128 192 255>; +- default-brightness-level = <12>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys_novena>; +- +- user-button { +- label = "User Button"; +- gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- lid { +- label = "Lid"; +- gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; +- linux,input-type = <5>; /* EV_SW */ +- linux,code = <0>; /* SW_LID */ +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds_novena>; +- +- heartbeat { +- label = "novena:white:panel"; +- gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- }; +- +- panel: panel { +- compatible = "innolux,n133hse-ea1"; +- backlight = <&backlight>; +- }; +- +- reg_2p5v: regulator-2p5v { +- compatible = "regulator-fixed"; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_audio_codec: regulator-audio-codec { +- compatible = "regulator-fixed"; +- regulator-name = "es8328-power"; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- startup-delay-us = <400000>; +- gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_display: regulator-display { +- compatible = "regulator-fixed"; +- regulator-name = "lcd-display-power"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <200000>; +- gpio = <&gpio5 28 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_lvds_lcd: regulator-lvds-lcd { +- compatible = "regulator-fixed"; +- regulator-name = "lcd-lvds-power"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_pcie: regulator-pcie { +- compatible = "regulator-fixed"; +- regulator-name = "pcie-bus-power"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_sata: regulator-sata { +- compatible = "regulator-fixed"; +- regulator-name = "sata-power"; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <10000>; +- gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- }; +- +- sound { +- compatible = "fsl,imx-audio-es8328"; +- model = "imx-audio-es8328"; +- ssi-controller = <&ssi1>; +- audio-codec = <&codec>; +- audio-amp-supply = <®_audio_codec>; +- jack-gpio = <&gpio5 15 GPIO_ACTIVE_HIGH>; +- audio-routing = +- "Speaker", "LOUT2", +- "Speaker", "ROUT2", +- "Speaker", "audio-amp", +- "Headphone", "ROUT1", +- "Headphone", "LOUT1", +- "LINPUT1", "Mic Jack", +- "RINPUT1", "Mic Jack", +- "Mic Jack", "Mic Bias"; +- mux-int-port = <0x1>; +- mux-ext-port = <0x3>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux_novena>; +- status = "okay"; +-}; +- +-&ecspi3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi3_novena>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet_novena>; +- phy-mode = "rgmii"; +- phy-handle = <ðphy>; +- phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy { +- compatible = "ethernet-phy-ieee802.3-c22"; +- rxc-skew-ps = <3000>; +- rxdv-skew-ps = <0>; +- txc-skew-ps = <3000>; +- txen-skew-ps = <0>; +- rxd0-skew-ps = <0>; +- rxd1-skew-ps = <0>; +- rxd2-skew-ps = <0>; +- rxd3-skew-ps = <0>; +- txd0-skew-ps = <3000>; +- txd1-skew-ps = <3000>; +- txd2-skew-ps = <3000>; +- txd3-skew-ps = <3000>; +- }; +- }; +-}; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hdmi_novena>; +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1_novena>; +- status = "okay"; +- +- accel: mma8452@1c { +- compatible = "fsl,mma8452"; +- reg = <0x1c>; +- }; +- +- rtc: pcf8523@68 { +- compatible = "nxp,pcf8523"; +- reg = <0x68>; +- }; +- +- sbs_battery: bq20z75@b { +- compatible = "sbs,sbs-battery"; +- reg = <0x0b>; +- sbs,i2c-retry-count = <50>; +- }; +- +- touch: stmpe811@44 { +- compatible = "st,stmpe811"; +- reg = <0x44>; +- irq-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; +- id = <0>; +- blocks = <0x5>; +- irq-trigger = <0x1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_stmpe_novena>; +- vio-supply = <®_3p3v>; +- vcc-supply = <®_3p3v>; +- +- stmpe_touchscreen { +- compatible = "st,stmpe-ts"; +- st,sample-time = <4>; +- st,mod-12b = <1>; +- st,ref-sel = <0>; +- st,adc-freq = <1>; +- st,ave-ctrl = <1>; +- st,touch-det-delay = <2>; +- st,settling = <2>; +- st,fraction-z = <7>; +- st,i-drive = <1>; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2_novena>; +- status = "okay"; +- +- pmic: pfuze100@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- reg_sw1a: sw1a { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- reg_sw1c: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_sw2: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_sw3a: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_sw3b: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_sw4: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_swbst: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- regulator-boot-on; +- }; +- +- reg_snvs: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_vref: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_vgen1: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- reg_vgen2: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- reg_vgen3: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_vgen4: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_vgen5: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_vgen6: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3_novena>; +- status = "okay"; +- +- codec: es8328@11 { +- compatible = "everest,es8328"; +- reg = <0x11>; +- DVDD-supply = <®_audio_codec>; +- AVDD-supply = <®_audio_codec>; +- PVDD-supply = <®_audio_codec>; +- HPVDD-supply = <®_audio_codec>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sound_novena>; +- clocks = <&clks IMX6QDL_CLK_CKO1>; +- assigned-clocks = <&clks IMX6QDL_CLK_CKO>, +- <&clks IMX6QDL_CLK_CKO1_SEL>, +- <&clks IMX6QDL_CLK_PLL4_AUDIO>, +- <&clks IMX6QDL_CLK_CKO1>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_CKO1>, +- <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>, +- <&clks IMX6QDL_CLK_OSC>, +- <&clks IMX6QDL_CLK_CKO1_PODF>; +- assigned-clock-rates = <0 0 722534400 22579200>; +- }; +-}; +- +-&kpp { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_kpp_novena>; +- linux,keymap = < +- MATRIX_KEY(1, 1, KEY_CONFIG) +- >; +- status = "okay"; +-}; +- +-&ldb { +- fsl,dual-channel; +- status = "okay"; +- +- lvds-channel@0 { +- fsl,data-mapping = "jeida"; +- fsl,data-width = <24>; +- fsl,panel = <&panel>; +- status = "okay"; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie_novena>; +- reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>; +- vpcie-supply = <®_pcie>; +- status = "okay"; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- status = "okay"; +-}; +- +-&sata { +- target-supply = <®_sata>; +- fsl,transmit-level-mV = <1025>; +- fsl,transmit-boost-mdB = <0>; +- fsl,transmit-atten-16ths = <8>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2_novena>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3_novena>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4_novena>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- dr_mode = "otg"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg_novena>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_swbst>; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2_novena>; +- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3_novena>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_audmux_novena: audmuxgrp-novena { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- >; +- }; +- +- pinctrl_backlight_novena: backlightgrp-novena { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b1 +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1 +- >; +- }; +- +- pinctrl_ecspi3_novena: ecspi3grp-novena { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 +- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 +- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 +- >; +- }; +- +- pinctrl_enet_novena: enetgrp-novena { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b028 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b028 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b028 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b028 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b028 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- /* Ethernet reset */ +- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b1 +- >; +- }; +- +- pinctrl_fpga_gpio: fpgagpiogrp-novena { +- fsl,pins = < +- /* FPGA power */ +- MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1 +- /* Reset */ +- MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 +- /* FPGA GPIOs */ +- MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1 +- MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1 +- MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 +- MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1 +- MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 +- MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 +- MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1 +- MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 +- MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1 +- MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1 +- MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1 +- MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1 +- MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1 +- MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1 +- MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1 +- MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1 +- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 +- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1 +- MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 +- MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 +- MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 +- MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1 +- MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1 +- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1 +- MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1 +- MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1 +- >; +- }; +- +- pinctrl_fpga_eim: fpgaeimgrp-novena { +- fsl,pins = < +- /* FPGA power */ +- MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1 +- /* Reset */ +- MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 +- /* FPGA GPIOs */ +- MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0f1 +- MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0f1 +- MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0f1 +- MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0f1 +- MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0f1 +- MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0f1 +- MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0f1 +- MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0f1 +- MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0f1 +- MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0f1 +- MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0f1 +- MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0f1 +- MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0f1 +- MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0f1 +- MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0f1 +- MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0f1 +- MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0f1 +- MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0f1 +- MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0f1 +- MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0f1 +- MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0f1 +- MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb0f1 +- MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0f1 +- MX6QDL_PAD_EIM_RW__EIM_RW 0xb0f1 +- MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb0f1 +- MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0xb0f1 +- >; +- }; +- +- pinctrl_gpio_keys_novena: gpiokeysgrp-novena { +- fsl,pins = < +- /* User button */ +- MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 +- /* PCIe Wakeup */ +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1f0e0 +- /* Lid switch */ +- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 +- >; +- }; +- +- pinctrl_hdmi_novena: hdmigrp-novena { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 +- MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1 +- >; +- }; +- +- pinctrl_i2c1_novena: i2c1grp-novena { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2_novena: i2c2grp-novena { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3_novena: i2c3grp-novena { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_kpp_novena: kppgrp-novena { +- fsl,pins = < +- /* Front panel button */ +- MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x1b0b1 +- /* Fake column driver, not connected */ +- MX6QDL_PAD_KEY_COL1__KEY_COL1 0x1b0b1 +- >; +- }; +- +- pinctrl_leds_novena: ledsgrp-novena { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b1 +- >; +- }; +- +- pinctrl_pcie_novena: pciegrp-novena { +- fsl,pins = < +- /* Reset */ +- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 +- /* Power On */ +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 +- /* Wifi kill */ +- MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1 +- >; +- }; +- +- pinctrl_sata_novena: satagrp-novena { +- fsl,pins = < +- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b1 +- >; +- }; +- +- pinctrl_senoko_novena: senokogrp-novena { +- fsl,pins = < +- /* Senoko IRQ line */ +- MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x13048 +- /* Senoko reset line */ +- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 +- >; +- }; +- +- pinctrl_sound_novena: soundgrp-novena { +- fsl,pins = < +- /* Audio power regulator */ +- MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1 +- /* Headphone plug */ +- MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1 +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 +- >; +- }; +- +- pinctrl_stmpe_novena: stmpegrp-novena { +- fsl,pins = < +- /* Touchscreen interrupt */ +- MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2_novena: uart2grp-novena { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3_novena: uart3grp-novena { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4_novena: uart4grp-novena { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg_novena: usbotggrp-novena { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc2_novena: usdhc2grp-novena { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 +- /* Write protect */ +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 +- /* Card detect */ +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc3_novena: usdhc3grp-novena { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-phytec-mira-rdk-emmc.dts b/scripts/dtc/include-prefixes/arm/imx6q-phytec-mira-rdk-emmc.dts +deleted file mode 100644 +index 2e70ea5623c6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-phytec-mira-rdk-emmc.dts ++++ /dev/null +@@ -1,72 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2018 PHYTEC Messtechnik GmbH +- * Author: Christian Hemp +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-phytec-phycore-som.dtsi" +-#include "imx6qdl-phytec-mira.dtsi" +- +-/ { +- model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC"; +- compatible = "phytec,imx6q-pbac06-emmc", "phytec,imx6q-pbac06", +- "phytec,imx6qdl-pcm058", "fsl,imx6q"; +- +- chosen { +- stdout-path = &uart2; +- }; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&fec { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c_rtc { +- status = "okay"; +-}; +- +-&m25p80 { +- status = "okay"; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbotg { +- status = "okay"; +-}; +- +-&usdhc1 { +- status = "okay"; +-}; +- +-&usdhc4 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-phytec-mira-rdk-nand.dts b/scripts/dtc/include-prefixes/arm/imx6q-phytec-mira-rdk-nand.dts +deleted file mode 100644 +index 65d2e483c136..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-phytec-mira-rdk-nand.dts ++++ /dev/null +@@ -1,72 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2018 PHYTEC Messtechnik GmbH +- * Author: Christian Hemp +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-phytec-phycore-som.dtsi" +-#include "imx6qdl-phytec-mira.dtsi" +- +-/ { +- model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND"; +- compatible = "phytec,imx6q-pbac06-nand", "phytec,imx6q-pbac06", +- "phytec,imx6qdl-pcm058", "fsl,imx6q"; +- +- chosen { +- stdout-path = &uart2; +- }; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&fec { +- status = "okay"; +-}; +- +-&gpmi { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c_rtc { +- status = "okay"; +-}; +- +-&m25p80 { +- status = "okay"; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbotg { +- status = "okay"; +-}; +- +-&usdhc1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-phytec-pbab01.dts b/scripts/dtc/include-prefixes/arm/imx6q-phytec-pbab01.dts +deleted file mode 100644 +index affe30b02d5a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-phytec-pbab01.dts ++++ /dev/null +@@ -1,21 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH +- */ +- +-/dts-v1/; +-#include "imx6q-phytec-pfla02.dtsi" +-#include "imx6qdl-phytec-pbab01.dtsi" +- +-/ { +- model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board"; +- compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q"; +- +- chosen { +- stdout-path = &uart4; +- }; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-phytec-pfla02.dtsi b/scripts/dtc/include-prefixes/arm/imx6q-phytec-pfla02.dtsi +deleted file mode 100644 +index 500944bd2a05..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-phytec-pfla02.dtsi ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH +- */ +- +-#include "imx6q.dtsi" +-#include "imx6qdl-phytec-pfla02.dtsi" +- +-/ { +- model = "Phytec phyFLEX-i.MX6 Quad"; +- compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-pico-dwarf.dts b/scripts/dtc/include-prefixes/arm/imx6q-pico-dwarf.dts +deleted file mode 100644 +index 479a63ed42af..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-pico-dwarf.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-// +-// Copyright 2018 Technexion Ltd. +-// +-// Author: Wig Cheng +-// Richard Hu +-// Tapani Utriainen +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-pico-pi.dtsi" +- +-/ { +- model = "TechNexion PICO-IMX6 Quad Board and Dwarf baseboard"; +- compatible = "technexion,imx6q-pico-dwarf", "fsl,imx6q"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-pico-hobbit.dts b/scripts/dtc/include-prefixes/arm/imx6q-pico-hobbit.dts +deleted file mode 100644 +index b767131068f5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-pico-hobbit.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-// +-// Copyright 2018 Technexion Ltd. +-// +-// Author: Wig Cheng +-// Richard Hu +-// Tapani Utriainen +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-pico-hobbit.dtsi" +- +-/ { +- model = "TechNexion PICO-IMX6 Quad Board and Hobbit baseboard"; +- compatible = "technexion,imx6q-pico-hobbit", "fsl,imx6q"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-pico-nymph.dts b/scripts/dtc/include-prefixes/arm/imx6q-pico-nymph.dts +deleted file mode 100644 +index e8ad4c12b263..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-pico-nymph.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-// +-// Copyright 2018 Technexion Ltd. +-// +-// Author: Wig Cheng +-// Richard Hu +-// Tapani Utriainen +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-pico-pi.dtsi" +- +-/ { +- model = "TechNexion PICO-IMX6 Quad Board and Nymph baseboard"; +- compatible = "technexion,imx6q-pico-nymph", "fsl,imx6q"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-pico-pi.dts b/scripts/dtc/include-prefixes/arm/imx6q-pico-pi.dts +deleted file mode 100644 +index cc2394ddad6c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-pico-pi.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-// +-// Copyright 2018 Technexion Ltd. +-// +-// Author: Wig Cheng +-// Richard Hu +-// Tapani Utriainen +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-pico-pi.dtsi" +- +-/ { +- model = "TechNexion PICO-IMX6 Quad Board and PI baseboard"; +- compatible = "technexion,imx6q-pico-pi", "fsl,imx6q"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-pinfunc.h b/scripts/dtc/include-prefixes/arm/imx6q-pinfunc.h +deleted file mode 100644 +index e40409d04b97..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-pinfunc.h ++++ /dev/null +@@ -1,1044 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __DTS_IMX6Q_PINFUNC_H +-#define __DTS_IMX6Q_PINFUNC_H +- +-/* +- * The pin function ID is a tuple of +- * +- */ +-#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 +-#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 +-#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 +-#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 +-#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 +-#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0 +-#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0 +-#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0 +-#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0 +-#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0 +-#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0 +-#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0 +-#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0 +-#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0 +-#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0 +-#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0 +-#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0 +-#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0 +-#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0 +-#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0 +-#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0 +-#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0 +-#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0 +-#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0 +-#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0 +-#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0 +-#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0 +-#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0 +-#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0 +-#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0 +-#define MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0 +-#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0 +-#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0 +-#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0 +-#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0 +-#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0 +-#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0 +-#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0 +-#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0 +-#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0 +-#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0 +-#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0 +-#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0 +-#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0 +-#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0 +-#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0 +-#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0 +-#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0 +-#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0 +-#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1 +-#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0 +-#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0 +-#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0 +-#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0 +-#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0 +-#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0 +-#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0 +-#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0 +-#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0 +-#define MX6QDL_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0 +-#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0 +-#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1 +-#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0 +-#define MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0 +-#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0 +-#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0 +-#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0 +-#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0 +-#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1 +-#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0 +-#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0 +-#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0 +-#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0 +-#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0 +-#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0 +-#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1 +-#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0 +-#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0 +-#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0 +-#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0 +-#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x0c4 0x3d8 0x924 0x4 0x0 +-#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x0c4 0x3d8 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0 +-#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1 +-#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1 +-#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c8 0x3dc 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c8 0x3dc 0x924 0x4 0x1 +-#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0 +-#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0 +-#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2 +-#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0 +-#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0 +-#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3 +-#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0 +-#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1 +-#define MX6QDL_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0 +-#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1 +-#define MX6QDL_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0 +-#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0 +-#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1 +-#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1 +-#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1 +-#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1 +-#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1 +-#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1 +-#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1 +-#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0 +-#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0 +-#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0 +-#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0 +-#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0 +-#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1 +-#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0 +-#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1 +-#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1 +-#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1 +-#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1 +-#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0 +-#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0 +-#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0 +-#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0 +-#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0 +-#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0 +-#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0 +-#define MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0 +-#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0 +-#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0 +-#define MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0 +-#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0 +-#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0 +-#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0 +-#define MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0 +-#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0 +-#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0 +-#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0 +-#define MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0 +-#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0 +-#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0 +-#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0 +-#define MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0 +-#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0 +-#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0 +-#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0 +-#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1 +-#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1 +-#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1 +-#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1 +-#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1 +-#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0 +-#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1 +-#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0 +-#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1 +-#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0 +-#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0 +-#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1 +-#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0 +-#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0 +-#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1 +-#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0 +-#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1 +-#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1 +-#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1 +-#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1 +-#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0 +-#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0 +-#define MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0 +-#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1 +-#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1 +-#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0 +-#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0 +-#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0 +-#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0 +-#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0 +-#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0 +-#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0 +-#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x004 0x0 0xff0d0100 +-#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0 +-#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0 +-#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1 +-#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0 +-#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1 +-#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0 +-#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1 +-#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0 +-#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1 +-#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0 +-#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0 +-#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x1e4 0x4f8 0x000 0x0 0x0 +-#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1 +-#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0 +-#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0 +-#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0 +-#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0 +-#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0 +-#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0 +-#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0 +-#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0 +-#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0 +-#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0 +-#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0 +-#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0 +-#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0 +-#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0 +-#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0 +-#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0 +-#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2 +-#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1 +-#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1 +-#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0 +-#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0 +-#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0 +-#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0 +-#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2 +-#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0 +-#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1 +-#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1 +-#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0 +-#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0 +-#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0 +-#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2 +-#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1 +-#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1 +-#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0 +-#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0 +-#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0 +-#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0 +-#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2 +-#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0 +-#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1 +-#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1 +-#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0 +-#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0 +-#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0 +-#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2 +-#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1 +-#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0 +-#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0 +-#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0 +-#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0 +-#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1 +-#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0 +-#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0 +-#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0 +-#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0 +-#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1 +-#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1 +-#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0 +-#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1 +-#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1 +-#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0 +-#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2 +-#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0 +-#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1 +-#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1 +-#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0 +-#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0 +-#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0 +-#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0 +-#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1 +-#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0 +-#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0 +-#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0 +-#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0 +-#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0 +-#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0 +-#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0 +-#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0 +-#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1 +-#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0 +-#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0 +-#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1 +-#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0 +-#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0 +-#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0 +-#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1 +-#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0 +-#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0 +-#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x004 0x3 0xff0d0101 +-#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0 +-#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0 +-#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1 +-#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0 +-#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0 +-#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0 +-#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0 +-#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1 +-#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1 +-#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1 +-#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0 +-#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0 +-#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1 +-#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1 +-#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1 +-#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x230 0x600 0x03c 0x11 0xff000609 +-#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1 +-#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0 +-#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1 +-#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1 +-#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1 +-#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0 +-#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1 +-#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1 +-#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1 +-#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0 +-#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1 +-#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1 +-#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0 +-#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2 +-#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0 +-#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1 +-#define MX6QDL_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0 +-#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0 +-#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0 +-#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0 +-#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2 +-#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0 +-#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0 +-#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1 +-#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0 +-#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0 +-#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1 +-#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3 +-#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0 +-#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0 +-#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0 +-#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1 +-#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0 +-#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1 +-#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0 +-#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3 +-#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2 +-#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0 +-#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0 +-#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0 +-#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1 +-#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1 +-#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0 +-#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0 +-#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1 +-#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0 +-#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1 +-#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2 +-#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0 +-#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1 +-#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0 +-#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0 +-#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0 +-#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0 +-#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0 +-#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0 +-#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3 +-#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2 +-#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0 +-#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3 +-#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1 +-#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0 +-#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3 +-#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1 +-#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0 +-#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3 +-#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2 +-#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0 +-#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2 +-#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2 +-#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1 +-#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2 +-#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2 +-#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1 +-#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2 +-#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2 +-#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1 +-#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2 +-#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3 +-#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2 +-#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3 +-#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1 +-#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2 +-#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0 +-#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0 +-#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0 +-#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0 +-#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0 +-#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3 +-#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2 +-#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3 +-#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4 +-#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5 +-#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2 +-#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3 +-#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2 +-#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2 +-#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3 +-#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1 +-#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4 +-#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5 +-#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0 +-#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1 +-#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0 +-#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0 +-#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0 +-#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1 +-#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0 +-#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0 +-#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2 +-#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3 +-#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0 +-#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0 +-#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0 +-#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6 +-#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4 +-#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5 +-#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7 +-#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1 +-#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0 +-#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1 +-#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0 +-#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0 +-#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0 +-#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0 +-#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0 +-#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0 +-#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1 +-#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0 +-#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0 +-#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0 +-#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0 +-#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x350 0x738 0x000 0x2 0x0 +-#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0 +-#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1 +-#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3 +-#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1 +-#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1 +-#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2 +-#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1 +-#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0 +-#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0 +-#define MX6QDL_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0 +-#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2 +-#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1 +-#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0 +- +-#endif /* __DTS_IMX6Q_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-pistachio.dts b/scripts/dtc/include-prefixes/arm/imx6q-pistachio.dts +deleted file mode 100644 +index 7a33e54cc0f1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-pistachio.dts ++++ /dev/null +@@ -1,695 +0,0 @@ +-/* +- * Copyright (C) 2017 NutsBoard.Org +- * +- * Author: Wig Cheng +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "imx6q.dtsi" +- +-/ { +- model = "NutsBoard i.MX6 Quad Pistachio board"; +- compatible = "nutsboard,imx6q-pistachio", "fsl,imx6q"; +- +- chosen { +- stdout-path = &uart4; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- wlan_en_reg: regulator-wlan_en { +- compatible = "regulator-fixed"; +- regulator-name = "wlan-en-regulator"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <70000>; +- enable-active-high; +- }; +- +- reg_usb_otg_vbus: regulator-usb_vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&swbst_reg>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- power { +- label = "Power Button"; +- gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- wakeup-source; +- linux,code = ; +- }; +- }; +- +- sound { +- compatible = "fsl,imx-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "audio-sgtl5000"; +- ssi-controller = <&ssi1>; +- audio-codec = <&codec>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <3>; +- }; +- +- backlight_lvds: backlight-lvds { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 50000>; +- brightness-levels = < +- 0 /*1 2 3 4 5 6*/ 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100 +- >; +- default-brightness-level = <94>; +- status = "okay"; +- }; +- +- panel { +- compatible = "hannstar,hsd100pxn1"; +- backlight = <&backlight_lvds>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, +- <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii"; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- codec: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; +- reg = <0x0a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_1p8v>; +- VDDIO-supply = <®_1p8v>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- pmic: pfuze100@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +- +- ar1021@4d { +- compatible = "microchip,ar1021-i2c"; +- reg = <0x4d>; +- interrupt-parent = <&gpio6>; +- interrupts = <8 IRQ_TYPE_EDGE_FALLING>; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /*pcie power*/ +- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /*LCD power*/ +- MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 /*backlight power*/ +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /*SD3 CD pin*/ +- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /*codec power*/ +- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /*touch reset*/ +- MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b01 /*touch irq*/ +- MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0/*backlight pwr*/ +- MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /*gpio 5V_1*/ +- MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 /*gpio 5V_2*/ +- MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /*gpio 5V_3*/ +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /*gpio 5V_4*/ +- MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 /*AUX_5V_EN*/ +- MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 /*AUX_5VB_EN*/ +- MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 /*AUX_3V3_EN*/ +- MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /*I2C expander pwr*/ +- >; +- }; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- /* AR8035 reset */ +- MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x130b0 +- /* AR8035 interrupt */ +- MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 +- /* AR8035 pin strapping: IO voltage: pull up */ +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- /* AR8035 pin strapping: PHYADDR#0: pull down */ +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 +- /* AR8035 pin strapping: PHYADDR#1: pull down */ +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 +- /* AR8035 pin strapping: MODE#1: pull up */ +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- /* AR8035 pin strapping: MODE#3: pull up */ +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- /* AR8035 pin strapping: MODE#0: pull down */ +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_gpio_keys: gpio_keysgrp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 +- >; +- }; +- +- pinctrl_hdmi_cec: hdmicecgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ +- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x130b0 /*headphone det*/ +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 /*microphone det*/ +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 +- MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 +- MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x15059 /*BT_EN*/ +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 +- MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059 +- MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059 +- MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059 +- MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x15059 /*WL_EN_LDO*/ +- MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x15059 /*WL_EN*/ +- MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x15059 /*WL_IRQ*/ +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b00 +- >; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@1 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <18>; +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&snvs_poweroff { +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; +- fsl,dte-mode; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- srp-disable; +- hnp-disable; +- adp-disable; +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbphy1 { +- fsl,tx-d-cal = <0x5>; +-}; +- +-&usbphy2 { +- fsl,tx-d-cal = <0x5>; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- bus-width = <8>; +- keep-power-in-suspend; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- vmmc-supply = <&wlan_en_reg>; +- no-1-8-v; +- keep-power-in-suspend; +- non-removable; +- cap-power-off-card; +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1835"; +- reg = <2>; +- interrupt-parent = <&gpio5>; +- interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; +- ref-clock-frequency = <38400000>; +- tcxo-clock-frequency = <26000000>; +- }; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <4>; +- cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- keep-power-in-suspend; +- wakeup-source; +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&wdog1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-prti6q.dts b/scripts/dtc/include-prefixes/arm/imx6q-prti6q.dts +deleted file mode 100644 +index b4605edfd2ab..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-prti6q.dts ++++ /dev/null +@@ -1,543 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (c) 2014 Protonic Holland +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-prti6q.dtsi" +-#include +-#include +- +-/ { +- model = "Protonic PRTI6Q board"; +- compatible = "prt,prti6q", "fsl,imx6q"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0xf0000000>; +- }; +- +- backlight_lcd: backlight-lcd { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_backlight>; +- pwms = <&pwm1 0 5000000>; +- brightness-levels = <0 16 64 255>; +- num-interpolated-steps = <16>; +- default-brightness-level = <1>; +- power-supply = <®_3v3>; +- enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; +- }; +- +- can_osc: can-osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds>; +- +- led-debug0 { +- function = LED_FUNCTION_STATUS; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-debug1 { +- function = LED_FUNCTION_SD; +- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "disk-activity"; +- }; +- }; +- +- panel { +- compatible = "kyo,tcg121xglp"; +- backlight = <&backlight_lcd>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +- +- reg_1v8: regulator-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- reg_wifi: regulator-wifi { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wifi_npd>; +- enable-active-high; +- gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- regulator-max-microvolt = <1800000>; +- regulator-min-microvolt = <1800000>; +- regulator-name = "regulator-WL12xx"; +- startup-delay-us = <70000>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "prti6q-sgtl5000"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,widgets = +- "Microphone", "Microphone Jack", +- "Line", "Line In Jack", +- "Headphone", "Headphone Jack", +- "Speaker", "External Speaker"; +- simple-audio-card,routing = +- "MIC_IN", "Microphone Jack", +- "LINE_IN", "Line In Jack", +- "Headphone Jack", "HP_OUT", +- "External Speaker", "LINE_OUT"; +- +- simple-audio-card,cpu { +- sound-dai = <&ssi1>; +- system-clock-frequency = <0>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- bitclock-master; +- frame-master; +- }; +- }; +- +- sound-spdif { +- compatible = "fsl,imx-audio-spdif"; +- model = "imx-spdif"; +- spdif-controller = <&spdif>; +- spdif-in; +- spdif-out; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +- +- mux-ssi1 { +- fsl,audmux-port = <0>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN 0 +- IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 +- IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 +- IMX_AUDMUX_V2_PTCR_TFSDIR 0 +- IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) +- >; +- }; +- +- mux-pins3 { +- fsl,audmux-port = <2>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) +- 0 IMX_AUDMUX_V2_PDCR_TXRXEN +- >; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can2>; +- status = "okay"; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- }; +-}; +- +-&ecspi2 { +- cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio4 25 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; +- status = "okay"; +- +- can@0 { +- compatible = "microchip,mcp2515"; +- reg = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can3>; +- clocks = <&can_osc>; +- interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; +- spi-max-frequency = <5000000>; +- }; +- +- adc@1 { +- compatible = "ti,adc128s052"; +- reg = <1>; +- spi-max-frequency = <2000000>; +- vref-supply = <®_3v3>; +- }; +-}; +- +-&ecspi3 { +- cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi3>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-handle = <&rgmii_phy>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Microchip KSZ9031RNX PHY */ +- rgmii_phy: ethernet-phy@0 { +- reg = <0>; +- interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- reset-deassert-us = <300>; +- }; +- }; +-}; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hdmi>; +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- sgtl5000: audio-codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0xa>; +- #sound-dai-cells = <0>; +- clocks = <&clks 201>; +- VDDA-supply = <®_3v3>; +- VDDIO-supply = <®_3v3>; +- VDDD-supply = <®_1v8>; +- }; +-}; +- +-/* DDC */ +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- adc@49 { +- compatible = "ti,ads1015"; +- reg = <0x49>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* can2_l */ +- channel@4 { +- reg = <4>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- +- /* can2_h */ +- channel@5 { +- reg = <5>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- +- /* can1_l */ +- channel@6 { +- reg = <6>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- +- /* can1_h */ +- channel@7 { +- reg = <7>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- }; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&snvs_poweroff { +- status = "okay"; +-}; +- +-&spdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spdif>; +- status = "okay"; +-}; +- +-&ssi1 { +- #sound-dai-cells = <0>; +- fsl,mode = "ac97-slave"; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbotg { +- pinctrl-0 = <&pinctrl_usbotg &pinctrl_usbotg_id>; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- non-removable; +- vmmc-supply = <®_wifi>; +- cap-power-off-card; +- keep-power-in-suspend; +- status = "okay"; +- +- wifi { +- compatible = "ti,wl1271"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wifi>; +- interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>; +- ref-clock-frequency = "38400000"; +- tcxo-clock-frequency = "19200000"; +- }; +-}; +- +-&iomuxc { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- >; +- }; +- +- pinctrl_backlight: backlightgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 +- >; +- }; +- +- pinctrl_can2: can2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b008 +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b008 +- >; +- }; +- +- pinctrl_can3: can3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- /* CS */ +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 +- MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 +- MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 +- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 +- >; +- }; +- +- pinctrl_ecspi2_cs: ecspi2csgrp { +- fsl,pins = < +- /* ADC128S022 CS */ +- MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 +- >; +- }; +- +- pinctrl_ecspi3: ecspi3grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 +- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 +- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 +- MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 +- +- /* Phy reset */ +- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 +- >; +- }; +- +- pinctrl_hdmi: hdmigrp { +- fsl,pins = < +- /* NOTE: DDC is done via I2C2, so DON'T +- * configure DDC pins for HDMI! +- */ +- MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 +- >; +- }; +- +- /* DDC */ +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_leds: ledsgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 +- >; +- }; +- +- pinctrl_spdif: spdifgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 +- MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg_id: usbotgidgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f058 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_wifi: wifigrp { +- fsl,pins = < +- /* WL12xx IRQ */ +- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880 +- >; +- }; +- +- pinctrl_wifi_npd: wifinpd { +- fsl,pins = < +- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-prtwd2.dts b/scripts/dtc/include-prefixes/arm/imx6q-prtwd2.dts +deleted file mode 100644 +index 349959d38020..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-prtwd2.dts ++++ /dev/null +@@ -1,188 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (c) 2018 Protonic Holland +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-prti6q.dtsi" +-#include +- +-/ { +- model = "Protonic WD2 board"; +- compatible = "prt,prtwd2", "fsl,imx6q"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +- +- usdhc2_wifi_pwrseq: usdhc2_wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wifi_npd>; +- reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; +- }; +- +- /* PRTWD2 rev 1 bitbang I2C for Ethernet Switch */ +- i2c { +- compatible = "i2c-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; +- i2c-gpio,delay-us = <20>; /* ~10 kHz */ +- i2c-gpio,scl-output-only; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rmii"; +- clocks = <&clks IMX6QDL_CLK_ENET>, +- <&clks IMX6QDL_CLK_ENET>; +- clock-names = "ipg", "ahb"; +- status = "okay"; +- +- fixed-link { +- speed = <100>; +- pause; +- full-duplex; +- }; +-}; +- +-&i2c3 { +- adc@49 { +- compatible = "ti,ads1015"; +- reg = <0x49>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* V in */ +- channel@4 { +- reg = <4>; +- ti,gain = <1>; +- ti,datarate = <3>; +- }; +- +- /* I charge */ +- channel@5 { +- reg = <5>; +- ti,gain = <1>; +- ti,datarate = <3>; +- }; +- +- /* V bus */ +- channel@6 { +- reg = <6>; +- ti,gain = <1>; +- ti,datarate = <3>; +- }; +- +- /* nc */ +- channel@7 { +- reg = <7>; +- ti,gain = <1>; +- ti,datarate = <3>; +- }; +- }; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- no-1-8-v; +- non-removable; +- mmc-pwrseq = <&usdhc2_wifi_pwrseq>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- wifi@1 { +- compatible = "brcm,bcm4329-fmac"; +- reg = <1>; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_eth_chg>; +- +- pinctrl_can1phy: can1phy { +- fsl,pins = < +- /* CAN1_SR */ +- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- /* MX6QDL_ENET_PINGRP4 */ +- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x130b0 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 +- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 +- +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 +- /* Phy reset */ +- MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 +- /* nINTRP */ +- MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 +- +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1f8b0 +- MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f8b0 +- >; +- }; +- +- pinctrl_usb_eth_chg: usbethchggrp { +- fsl,pins = < +- /* USB charging control */ +- MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x130b0 +- MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x130b0 +- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x130b0 +- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x130b0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_wifi_npd: wifinpd { +- fsl,pins = < +- /* WL_REG_ON */ +- MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-rex-pro.dts b/scripts/dtc/include-prefixes/arm/imx6q-rex-pro.dts +deleted file mode 100644 +index 1767e1a3cd53..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-rex-pro.dts ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright 2014 FEDEVEL, Inc. +- * +- * Author: Robert Nelson +- */ +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-rex.dtsi" +- +-/ { +- model = "Rex Pro i.MX6 Quad Board"; +- compatible = "rex,imx6q-rex-pro", "fsl,imx6q"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +-}; +- +-&ecspi3 { +- flash: m25p80@0 { +- compatible = "sst,sst25vf032b", "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-sabreauto.dts b/scripts/dtc/include-prefixes/arm/imx6q-sabreauto.dts +deleted file mode 100644 +index 6e981a3e0a83..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-sabreauto.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2012 Freescale Semiconductor, Inc. +-// Copyright 2011 Linaro Ltd. +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-sabreauto.dtsi" +- +-/ { +- model = "Freescale i.MX6 Quad SABRE Automotive Board"; +- compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-sabrelite.dts b/scripts/dtc/include-prefixes/arm/imx6q-sabrelite.dts +deleted file mode 100644 +index dc51262e7b2f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-sabrelite.dts ++++ /dev/null +@@ -1,59 +0,0 @@ +-/* +- * Copyright 2011 Freescale Semiconductor, Inc. +- * Copyright 2011 Linaro Ltd. +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-sabrelite.dtsi" +- +-/ { +- model = "Freescale i.MX6 Quad SABRE Lite Board"; +- compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&ipu1_csi1_from_mipi_vc1 { +- clock-lanes = <0>; +- data-lanes = <1 2>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-sabresd.dts b/scripts/dtc/include-prefixes/arm/imx6q-sabresd.dts +deleted file mode 100644 +index eec944673c0b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-sabresd.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2012 Freescale Semiconductor, Inc. +-// Copyright 2011 Linaro Ltd. +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-sabresd.dtsi" +- +-/ { +- model = "Freescale i.MX6 Quad SABRE Smart Device Board"; +- compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&ipu1_csi1_from_mipi_vc1 { +- clock-lanes = <0>; +- data-lanes = <1 2>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-savageboard.dts b/scripts/dtc/include-prefixes/arm/imx6q-savageboard.dts +deleted file mode 100644 +index 717ac62fc2cf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-savageboard.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-/* +- * Copyright (C) 2017 Milo Kim +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-savageboard.dtsi" +- +-/ { +- model = "Poslab SavageBoard Quad"; +- compatible = "poslab,imx6q-savageboard", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-sbc6x.dts b/scripts/dtc/include-prefixes/arm/imx6q-sbc6x.dts +deleted file mode 100644 +index 9054c1d58b9d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-sbc6x.dts ++++ /dev/null +@@ -1,93 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright 2013 Pavel Machek +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +- +-/ { +- model = "MicroSys sbc6x board"; +- compatible = "microsys,sbc6x", "fsl,imx6q"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +-}; +- +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii"; +- status = "okay"; +-}; +- +-&iomuxc { +- imx6q-sbc6x { +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- >; +- }; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usbotg { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-skov-revc-lt2.dts b/scripts/dtc/include-prefixes/arm/imx6q-skov-revc-lt2.dts +deleted file mode 100644 +index f00add7b3048..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-skov-revc-lt2.dts ++++ /dev/null +@@ -1,36 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright (C) 2020 Pengutronix, Ulrich Oelmann +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-skov-cpu.dtsi" +-#include "imx6qdl-skov-cpu-revc.dtsi" +- +-/ { +- model = "SKOV IMX6 CPU QuadCore"; +- compatible = "skov,imx6q-skov-revc-lt2", "fsl,imx6q"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- /* internal 22 k pull up required */ +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001f878 +- /* internal 22 k pull up required */ +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001f878 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-skov-revc-lt6.dts b/scripts/dtc/include-prefixes/arm/imx6q-skov-revc-lt6.dts +deleted file mode 100644 +index 3e3b36ad362a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-skov-revc-lt6.dts ++++ /dev/null +@@ -1,128 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright (C) 2020 Pengutronix, Ulrich Oelmann +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-skov-cpu.dtsi" +-#include "imx6qdl-skov-cpu-revc.dtsi" +- +-/ { +- model = "SKOV IMX6 CPU QuadCore"; +- compatible = "skov,imx6q-skov-revc-lt6", "fsl,imx6q"; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_backlight>; +- enable-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; +- pwms = <&pwm2 0 20000 0>; +- brightness-levels = <0 255>; +- num-interpolated-steps = <17>; +- default-brightness-level = <8>; +- power-supply = <®_24v0>; +- }; +- +- display { +- #address-cells = <1>; +- #size-cells = <0>; +- +- compatible = "fsl,imx-parallel-display"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1>; +- +- port@0 { +- reg = <0>; +- +- display0_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- display0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +- +- panel { +- compatible = "logictechno,lttd800480070-l6wh-rt"; +- backlight = <&backlight>; +- power-supply = <®_3v3>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display0_out>; +- }; +- }; +- }; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&display0_in>; +-}; +- +-&iomuxc { +- pinctrl_backlight: backlightgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x58 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- /* internal 22 k pull up required */ +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001F878 +- /* internal 22 k pull up required */ +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001F878 +- >; +- }; +- +- pinctrl_ipu1: ipu1grp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-skov-reve-mi1010ait-1cp1.dts b/scripts/dtc/include-prefixes/arm/imx6q-skov-reve-mi1010ait-1cp1.dts +deleted file mode 100644 +index 7f1f19b74bfa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-skov-reve-mi1010ait-1cp1.dts ++++ /dev/null +@@ -1,127 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright (C) 2020 Pengutronix, Ulrich Oelmann +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-skov-cpu.dtsi" +- +-/ { +- model = "SKOV IMX6 CPU QuadCore"; +- compatible = "skov,imx6q-skov-reve-mi1010ait-1cp1", "fsl,imx6q"; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_backlight>; +- enable-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; +- pwms = <&pwm2 0 20000 0>; +- brightness-levels = <0 255>; +- num-interpolated-steps = <17>; +- default-brightness-level = <8>; +- power-supply = <®_24v0>; +- }; +- +- panel { +- compatible = "multi-inno,mi1010ait-1cp"; +- backlight = <&backlight>; +- power-supply = <®_3v3>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, +- <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clock-frequency = <100000>; +- status = "okay"; +- +- touchscreen@38 { +- compatible = "edt,edt-ft5406"; +- reg = <0x38>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_touchscreen>; +- interrupt-parent = <&gpio3>; +- interrupts = <19 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; +- touchscreen-size-x = <1280>; +- touchscreen-size-y = <800>; +- wakeup-source; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&iomuxc { +- pinctrl_backlight: backlightgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x58 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- /* external 1 k pull up */ +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x40010878 +- /* external 1 k pull up */ +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x40010878 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- /* internal 22 k pull up required */ +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001F878 +- /* internal 22 k pull up required */ +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001F878 +- >; +- }; +- +- pinctrl_touchscreen: touchscreengrp { +- fsl,pins = < +- /* external 10 k pull up */ +- /* CTP_INT */ +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 +- /* CTP_RST */ +- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-solidsense.dts b/scripts/dtc/include-prefixes/arm/imx6q-solidsense.dts +deleted file mode 100644 +index 0e6a325df363..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-solidsense.dts ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* +- * Copyright (C) 2015 Rabeeh Khoury +- * Based on dt work by Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-sr-som.dtsi" +-#include "imx6qdl-sr-som-emmc.dtsi" +-#include "imx6qdl-sr-som-ti.dtsi" +-#include "imx6qdl-hummingboard2.dtsi" +-#include "imx6qdl-solidsense.dtsi" +- +-/ { +- model = "SolidRun SolidSense Dual/Quad (1.5som+emmc)"; +- compatible = "solidrun,solidsense/q", "fsl,imx6q"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-tbs2910.dts b/scripts/dtc/include-prefixes/arm/imx6q-tbs2910.dts +deleted file mode 100644 +index 343364d3e4f7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-tbs2910.dts ++++ /dev/null +@@ -1,407 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Copyright 2014 Soeren Moch +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include +-#include +- +-/ { +- model = "TBS2910 Matrix ARM mini PC"; +- compatible = "tbs,imx6q-tbs2910", "fsl,imx6q"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- aliases { +- mmc0 = &usdhc2; +- mmc1 = &usdhc3; +- mmc2 = &usdhc4; +- /delete-property/ mmc3; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +- +- fan { +- compatible = "gpio-fan"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_fan>; +- gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; +- gpio-fan,speed-map = <0 0 +- 3000 1>; +- }; +- +- ir_recv { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ir>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- blue { +- label = "blue_status_led"; +- gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; +- }; +- }; +- +- reg_2p5v: regulator-2p5v { +- compatible = "regulator-fixed"; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_5p0v: regulator-5p0v { +- compatible = "regulator-fixed"; +- regulator-name = "5P0V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- sound-sgtl5000 { +- audio-codec = <&sgtl5000>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- compatible = "fsl,imx-audio-sgtl5000"; +- model = "On-board Codec"; +- mux-ext-port = <3>; +- mux-int-port = <1>; +- ssi-controller = <&ssi1>; +- }; +- +- sound-spdif { +- compatible = "fsl,imx-audio-spdif"; +- model = "On-board SPDIF"; +- spdif-controller = <&spdif>; +- spdif-out; +- }; +-}; +- +-&audmux { +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-handle = <&phy>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy: ethernet-phy@4 { +- reg = <4>; +- qca,clk-out-frequency = <125000000>; +- reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- }; +- }; +-}; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hdmi>; +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- sgtl5000: sgtl5000@a { +- clocks = <&clks IMX6QDL_CLK_CKO>; +- compatible = "fsl,sgtl5000"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sgtl5000>; +- reg = <0x0a>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_3p3v>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- rtc: ds1307@68 { +- compatible = "dallas,ds1307"; +- reg = <0x68>; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&sata { +- fsl,transmit-level-mV = <1104>; +- fsl,transmit-boost-mdB = <3330>; +- fsl,transmit-atten-16ths = <16>; +- fsl,receive-eq-mdB = <3000>; +- status = "okay"; +-}; +- +-&snvs_poweroff { +- status = "okay"; +-}; +- +-&spdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spdif>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_5p0v>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_5p0v>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_3p3v>; +- voltage-ranges = <3300 3300>; +- no-1-8-v; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <4>; +- cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_3p3v>; +- voltage-ranges = <3300 3300>; +- no-1-8-v; +- status = "okay"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <8>; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_3p3v>; +- voltage-ranges = <3300 3300>; +- non-removable; +- no-1-8-v; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059 +- >; +- }; +- +- pinctrl_gpio_fan: gpiofangrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b1 +- >; +- }; +- +- pinctrl_hdmi: hdmigrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_ir: irgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x17059 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x17059 +- >; +- }; +- +- pinctrl_sgtl5000: sgtl5000grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 +- >; +- }; +- +- pinctrl_spdif: spdifgrp { +- fsl,pins = ; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x17059 +- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x17059 +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 +- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 +- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 +- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-tqma6a.dtsi b/scripts/dtc/include-prefixes/arm/imx6q-tqma6a.dtsi +deleted file mode 100644 +index ab4c07c13a13..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-tqma6a.dtsi ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Sascha Hauer, Pengutronix +- * Copyright 2013-2017 Markus Niebel +- */ +- +-#include "imx6q.dtsi" +-#include "imx6qdl-tqma6a.dtsi" +-#include "imx6qdl-tqma6.dtsi" +- +-/ { +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-tqma6b.dtsi b/scripts/dtc/include-prefixes/arm/imx6q-tqma6b.dtsi +deleted file mode 100644 +index 7224c376c318..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-tqma6b.dtsi ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Sascha Hauer, Pengutronix +- */ +- +-#include "imx6q.dtsi" +-#include "imx6qdl-tqma6b.dtsi" +-#include "imx6qdl-tqma6.dtsi" +- +-/ { +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-ts4900.dts b/scripts/dtc/include-prefixes/arm/imx6q-ts4900.dts +deleted file mode 100644 +index dce1e8671ebe..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-ts4900.dts ++++ /dev/null +@@ -1,59 +0,0 @@ +-/* +- * Copyright 2015 Technologic Systems +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-ts4900.dtsi" +- +-/ { +- model = "Technologic Systems i.MX6 Quad TS-4900 (Default Device Tree)"; +- compatible = "technologic,imx6q-ts4900", "fsl,imx6q"; +- +- /* Will be filled by the bootloader */ +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0>; +- }; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-ts7970.dts b/scripts/dtc/include-prefixes/arm/imx6q-ts7970.dts +deleted file mode 100644 +index 570bd3c309a6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-ts7970.dts ++++ /dev/null +@@ -1,60 +0,0 @@ +-/* +- * Copyright 2015 Technologic Systems +- * Copyright 2017 Savoir-faire Linux +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-ts7970.dtsi" +- +-/ { +- model = "Technologic Systems i.MX6 Quad TS-7970 (Default Device Tree)"; +- compatible = "technologic,imx6q-ts7970", "fsl,imx6q"; +- +- /* Will be filled by the bootloader */ +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0>; +- }; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1010-comtft.dts b/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1010-comtft.dts +deleted file mode 100644 +index ac3050a835e5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1010-comtft.dts ++++ /dev/null +@@ -1,79 +0,0 @@ +-/* +- * Copyright 2014-2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-tx6.dtsi" +-#include "imx6qdl-tx6-lcd.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6Q-1010 Module on CoMpact TFT"; +- compatible = "karo,imx6q-tx6q", "fsl,imx6q"; +-}; +- +-&backlight { +- pwms = <&pwm2 0 500000 0>; +- /delete-property/ turn-on-delay-ms; +-}; +- +-&can1 { +- status = "disabled"; +-}; +- +-&can2 { +- xceiver-supply = <®_3v3>; +-}; +- +-&kpp { +- status = "disabled"; +-}; +- +-&lcd_panel { +- compatible = "edt,etm0700g0edh6"; +-}; +- +-®_can_xcvr { +- status = "disabled"; +-}; +- +-&touchscreen { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1010.dts b/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1010.dts +deleted file mode 100644 +index 4ee860b626ff..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1010.dts ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* +- * Copyright 2014-2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-tx6.dtsi" +-#include "imx6qdl-tx6-lcd.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6Q-1010/-1030 Module"; +- compatible = "karo,imx6q-tx6q", "fsl,imx6q"; +-}; +- +-&ipu2 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1020-comtft.dts b/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1020-comtft.dts +deleted file mode 100644 +index a773f252816c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1020-comtft.dts ++++ /dev/null +@@ -1,110 +0,0 @@ +-/* +- * Copyright 2014-2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-tx6.dtsi" +-#include "imx6qdl-tx6-lcd.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6Q-1020 Module on CoMpact TFT"; +- compatible = "karo,imx6q-tx6q", "fsl,imx6q"; +-}; +- +-&backlight { +- pwms = <&pwm2 0 500000 0>; +- /delete-property/ turn-on-delay-ms; +-}; +- +-&can1 { +- status = "disabled"; +-}; +- +-&can2 { +- xceiver-supply = <®_3v3>; +-}; +- +-&ds1339 { +- status = "disabled"; +-}; +- +-&gpmi { +- status = "disabled"; +-}; +- +-&kpp { +- status = "disabled"; +-}; +- +-&lcd_panel { +- compatible = "edt,etm0700g0edh6"; +-}; +- +-®_can_xcvr { +- status = "disabled"; +-}; +- +-&touchscreen { +- status = "disabled"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <4>; +- no-1-8-v; +- fsl,wp-controller; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 +- MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1020.dts b/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1020.dts +deleted file mode 100644 +index 0a4daec8d3ad..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1020.dts ++++ /dev/null +@@ -1,86 +0,0 @@ +-/* +- * Copyright 2014-2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-tx6.dtsi" +-#include "imx6qdl-tx6-lcd.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6Q-1020 Module"; +- compatible = "karo,imx6q-tx6q", "fsl,imx6q"; +-}; +- +-&ds1339 { +- status = "disabled"; +-}; +- +-&gpmi { +- status = "disabled"; +-}; +- +-&ipu2 { +- status = "disabled"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <4>; +- non-removable; +- no-1-8-v; +- fsl,wp-controller; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 +- MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1036-mb7.dts b/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1036-mb7.dts +deleted file mode 100644 +index 9ffbb0fe7df8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1036-mb7.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* +- * Copyright 2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6q-tx6q-1036.dts" +-#include "imx6qdl-tx6-mb7.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6Q-1036 Module on MB7 baseboard"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1036.dts b/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1036.dts +deleted file mode 100644 +index cb2fcb4896c6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1036.dts ++++ /dev/null +@@ -1,86 +0,0 @@ +-/* +- * Copyright 2014-2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-tx6.dtsi" +-#include "imx6qdl-tx6-lcd.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6Q-1036 Module"; +- compatible = "karo,imx6q-tx6q", "fsl,imx6q"; +-}; +- +-&ds1339 { +- status = "disabled"; +-}; +- +-&gpmi { +- status = "disabled"; +-}; +- +-&ipu2 { +- status = "disabled"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <4>; +- non-removable; +- no-1-8-v; +- fsl,wp-controller; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 +- MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-tx6q-10x0-mb7.dts b/scripts/dtc/include-prefixes/arm/imx6q-tx6q-10x0-mb7.dts +deleted file mode 100644 +index d43a5d8f1749..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-tx6q-10x0-mb7.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* +- * Copyright 2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6q-tx6q-1010.dts" +-#include "imx6qdl-tx6-mb7.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6Q-1010/-1030 Module on MB7 baseboard"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1110.dts b/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1110.dts +deleted file mode 100644 +index f7b0acb65352..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-tx6q-1110.dts ++++ /dev/null +@@ -1,58 +0,0 @@ +-/* +- * Copyright 2014-2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-tx6.dtsi" +-#include "imx6qdl-tx6-lvds.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6Q-1110/-1130 Module"; +- compatible = "karo,imx6q-tx6q", "fsl,imx6q"; +-}; +- +-&ipu2 { +- status = "disabled"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-tx6q-11x0-mb7.dts b/scripts/dtc/include-prefixes/arm/imx6q-tx6q-11x0-mb7.dts +deleted file mode 100644 +index 387edf2b3f96..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-tx6q-11x0-mb7.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* +- * Copyright 2016-2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6q-tx6q-1110.dts" +-#include "imx6qdl-tx6-mb7.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6Q-1110/-1130 Module on MB7 baseboard"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-udoo.dts b/scripts/dtc/include-prefixes/arm/imx6q-udoo.dts +deleted file mode 100644 +index 52e9f4a211d0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-udoo.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- * +- * Author: Fabio Estevam +- */ +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-udoo.dtsi" +- +-/ { +- model = "Udoo i.MX6 Quad Board"; +- compatible = "udoo,imx6q-udoo", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-utilite-pro.dts b/scripts/dtc/include-prefixes/arm/imx6q-utilite-pro.dts +deleted file mode 100644 +index d16ff2083d62..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-utilite-pro.dts ++++ /dev/null +@@ -1,355 +0,0 @@ +-/* +- * Copyright 2013 CompuLab Ltd. +- * Copyright 2016 Christopher Spinrath +- * +- * Based on the devicetree distributed with the vendor kernel for the +- * Utilite Pro: +- * Copyright 2013 CompuLab Ltd. +- * Author: Valentin Raevsky +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include "imx6q-cm-fx6.dts" +- +-/ { +- model = "CompuLab Utilite Pro"; +- compatible = "compulab,utilite-pro", "compulab,cm-fx6", "fsl,imx6q"; +- +- aliases { +- ethernet1 = ð1; +- rtc0 = &em3027; +- rtc1 = &snvs_rtc; +- }; +- +- encoder { +- compatible = "ti,tfp410"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tfp410_in: endpoint { +- remote-endpoint = <¶llel_display_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- tfp410_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- power { +- label = "Power Button"; +- gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hpd>; +- type = "a"; +- ddc-i2c-bus = <&i2c_dvi_ddc>; +- hpd-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&tfp410_out>; +- }; +- }; +- }; +- +- i2cmux { +- compatible = "i2c-mux-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1mux>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- mux-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- i2c-parent = <&i2c1>; +- +- i2c@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- em3027: rtc@56 { +- compatible = "emmicro,em3027"; +- reg = <0x56>; +- }; +- }; +- +- i2c_dvi_ddc: i2c@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- parallel-display { +- compatible = "fsl,imx-parallel-display"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1>; +- +- interface-pix-fmt = "rgb24"; +- +- port@0 { +- reg = <0>; +- +- parallel_display_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- parallel_display_out: endpoint { +- remote-endpoint = <&tfp410_in>; +- }; +- }; +- }; +-}; +- +-/* +- * A single IPU is not able to drive both display interfaces available on the +- * Utilite Pro at high resolution due to its bandwidth limitation. Since the +- * tfp410 encoder is wired up to IPU1, sever the link between IPU1 and the +- * SoC-internal Designware HDMI encoder forcing the latter to be connected to +- * IPU2 instead of IPU1. +- */ +-/delete-node/&ipu1_di0_hdmi; +-/delete-node/&hdmi_mux_0; +-/delete-node/&ipu1_di1_hdmi; +-/delete-node/&hdmi_mux_1; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hdmicec>; +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_gpio_keys: gpio_keysgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 +- >; +- }; +- +- pinctrl_hdmicec: hdmicecgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 +- >; +- }; +- +- pinctrl_hpd: hpdgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c1mux: i2c1muxgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_ipu1: ipu1grp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 +- MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9 +- >; +- }; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <¶llel_display_in>; +-}; +- +-&pcie { +- pcie@0,0 { +- reg = <0x000000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- /* non-removable i211 ethernet card */ +- eth1: intel,i211@pcie0,0 { +- reg = <0x010000 0 0 0 0>; +- }; +- }; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- no-1-8-v; +- broken-cd; +- keep-power-in-suspend; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-var-dt6customboard.dts b/scripts/dtc/include-prefixes/arm/imx6q-var-dt6customboard.dts +deleted file mode 100644 +index 63550351340d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-var-dt6customboard.dts ++++ /dev/null +@@ -1,235 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Support for Variscite DART-MX6 Carrier-board +- * +- * Copyright 2017 BayLibre, SAS +- * Author: Neil Armstrong +- */ +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-var-dart.dtsi" +-#include +- +-/ { +- model = "Variscite DART-MX6 Carrier-board"; +- compatible = "variscite,dt6customboard", "fsl,imx6q"; +- +- backlight_lvds: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm2 0 50000>; +- brightness-levels = <0 4 8 16 32 64 128 248>; +- default-brightness-level = <7>; +- status = "okay"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- +- back { +- gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "Key Back"; +- linux,input-type = <1>; +- debounce-interval = <100>; +- wakeup-source; +- }; +- +- home { +- gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "Key Home"; +- linux,input-type = <1>; +- debounce-interval = <100>; +- wakeup-source; +- }; +- +- menu { +- gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "Key Menu"; +- linux,input-type = <1>; +- debounce-interval = <100>; +- wakeup-source; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- led1 { +- gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led2 { +- gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- }; +- +- panel1: lvds-panel { +- compatible = "sgd,gktw70sdae4se", "panel-lvds"; +- backlight = <&backlight_lvds>; +- width-mm = <153>; +- height-mm = <86>; +- label = "gktw70sdae4se"; +- data-mapping = "jeida-18"; +- +- panel-timing { +- clock-frequency = <32000000>; +- hactive = <800>; +- vactive = <480>; +- hback-porch = <39>; +- hfront-porch = <39>; +- vback-porch = <29>; +- vfront-porch = <13>; +- hsync-len = <47>; +- vsync-len = <2>; +- }; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds1_out>; +- }; +- }; +- }; +- +- reg_usb_h1_vbus: regulator-usbh1vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_otg_vbus: regulator-usbotgvbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "dt6-customboard-audio"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sound_codec>; +- simple-audio-card,frame-master = <&sound_codec>; +- simple-audio-card,widgets = "Headphone", "Headphone Jack", +- "Line", "Line In"; +- simple-audio-card,routing = "Headphone Jack", "HPLOUT", +- "Headphone Jack", "HPROUT", +- "LINE1L", "Line In", +- "LINE1R", "Line In"; +- +- sound_cpu: simple-audio-card,cpu { +- sound-dai = <&ssi2>; +- }; +- +- sound_codec: simple-audio-card,codec { +- sound-dai = <&tlv320aic3106>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- }; +- }; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, +- <&gpio4 10 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&fec { +- status = "okay"; +- phy-mode = "rgmii"; +- phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- status = "okay"; +- +- touchscreen@38 { +- compatible = "edt,edt-ft5x06"; +- reg = <0x38>; +- interrupt-parent = <&gpio1>; +- interrupts = <4 IRQ_TYPE_EDGE_FALLING>; +- touchscreen-size-x = <800>; +- touchscreen-size-y = <480>; +- touchscreen-inverted-x; +- touchscreen-inverted-y; +- wakeup-source; +- }; +- +- rtc@68 { +- compatible = "isil,isl12057"; +- reg = <0x68>; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@1 { +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds1_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&pwm2 { +- #pwm-cells = <2>; +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- dr_mode = "otg"; +- srp-disable; +- hnp-disable; +- adp-disable; +- status = "okay"; +-}; +- +-&usdhc2 { +- cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-vicut1.dts b/scripts/dtc/include-prefixes/arm/imx6q-vicut1.dts +deleted file mode 100644 +index 0a4e251be162..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-vicut1.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (c) 2014 Protonic Holland +- */ +- +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-vicut1.dtsi" +- +-/ { +- model = "Kverneland UT1Q Board"; +- compatible = "kvg,vicut1q", "fsl,imx6q"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-wandboard-revb1.dts b/scripts/dtc/include-prefixes/arm/imx6q-wandboard-revb1.dts +deleted file mode 100644 +index f6ccbecff92c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-wandboard-revb1.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- * +- * Author: Fabio Estevam +- */ +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-wandboard-revb1.dtsi" +- +-/ { +- model = "Wandboard i.MX6 Quad Board rev B1"; +- compatible = "wand,imx6q-wandboard", "fsl,imx6q"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-wandboard-revd1.dts b/scripts/dtc/include-prefixes/arm/imx6q-wandboard-revd1.dts +deleted file mode 100644 +index 55331021d80c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-wandboard-revd1.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- * +- * Author: Fabio Estevam +- */ +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-wandboard-revd1.dtsi" +- +-/ { +- model = "Wandboard i.MX6 Quad Board revD1"; +- compatible = "wand,imx6q-wandboard", "fsl,imx6q"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-wandboard.dts b/scripts/dtc/include-prefixes/arm/imx6q-wandboard.dts +deleted file mode 100644 +index 0be548beef86..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-wandboard.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- * +- * Author: Fabio Estevam +- */ +-/dts-v1/; +-#include "imx6q.dtsi" +-#include "imx6qdl-wandboard-revc1.dtsi" +- +-/ { +- model = "Wandboard i.MX6 Quad Board"; +- compatible = "wand,imx6q-wandboard", "fsl,imx6q"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q-zii-rdu2.dts b/scripts/dtc/include-prefixes/arm/imx6q-zii-rdu2.dts +deleted file mode 100644 +index a1c5e69d81ba..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q-zii-rdu2.dts ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2016-2017 Zodiac Inflight Innovations +- */ +- +-/dts-v1/; +- +-#include "imx6q.dtsi" +-#include "imx6qdl-zii-rdu2.dtsi" +- +-/ { +- model = "ZII RDU2 Board"; +- compatible = "zii,imx6q-zii-rdu2", "fsl,imx6q"; +- +- /* Will be filled by the bootloader */ +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6q.dtsi b/scripts/dtc/include-prefixes/arm/imx6q.dtsi +deleted file mode 100644 +index 9caba4529c71..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6q.dtsi ++++ /dev/null +@@ -1,550 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright 2013 Freescale Semiconductor, Inc. +- +-#include +-#include "imx6q-pinfunc.h" +-#include "imx6qdl.dtsi" +- +-/ { +- aliases { +- ipu1 = &ipu2; +- spi4 = &ecspi5; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <0>; +- next-level-cache = <&L2>; +- operating-points = < +- /* kHz uV */ +- 1200000 1275000 +- 996000 1250000 +- 852000 1250000 +- 792000 1175000 +- 396000 975000 +- >; +- fsl,soc-operating-points = < +- /* ARM kHz SOC-PU uV */ +- 1200000 1275000 +- 996000 1250000 +- 852000 1250000 +- 792000 1175000 +- 396000 1175000 +- >; +- clock-latency = <61036>; /* two CLK32 periods */ +- #cooling-cells = <2>; +- clocks = <&clks IMX6QDL_CLK_ARM>, +- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, +- <&clks IMX6QDL_CLK_STEP>, +- <&clks IMX6QDL_CLK_PLL1_SW>, +- <&clks IMX6QDL_CLK_PLL1_SYS>; +- clock-names = "arm", "pll2_pfd2_396m", "step", +- "pll1_sw", "pll1_sys"; +- arm-supply = <®_arm>; +- pu-supply = <®_pu>; +- soc-supply = <®_soc>; +- nvmem-cells = <&cpu_speed_grade>; +- nvmem-cell-names = "speed_grade"; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <1>; +- next-level-cache = <&L2>; +- operating-points = < +- /* kHz uV */ +- 1200000 1275000 +- 996000 1250000 +- 852000 1250000 +- 792000 1175000 +- 396000 975000 +- >; +- fsl,soc-operating-points = < +- /* ARM kHz SOC-PU uV */ +- 1200000 1275000 +- 996000 1250000 +- 852000 1250000 +- 792000 1175000 +- 396000 1175000 +- >; +- clock-latency = <61036>; /* two CLK32 periods */ +- #cooling-cells = <2>; +- clocks = <&clks IMX6QDL_CLK_ARM>, +- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, +- <&clks IMX6QDL_CLK_STEP>, +- <&clks IMX6QDL_CLK_PLL1_SW>, +- <&clks IMX6QDL_CLK_PLL1_SYS>; +- clock-names = "arm", "pll2_pfd2_396m", "step", +- "pll1_sw", "pll1_sys"; +- arm-supply = <®_arm>; +- pu-supply = <®_pu>; +- soc-supply = <®_soc>; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <2>; +- next-level-cache = <&L2>; +- operating-points = < +- /* kHz uV */ +- 1200000 1275000 +- 996000 1250000 +- 852000 1250000 +- 792000 1175000 +- 396000 975000 +- >; +- fsl,soc-operating-points = < +- /* ARM kHz SOC-PU uV */ +- 1200000 1275000 +- 996000 1250000 +- 852000 1250000 +- 792000 1175000 +- 396000 1175000 +- >; +- clock-latency = <61036>; /* two CLK32 periods */ +- #cooling-cells = <2>; +- clocks = <&clks IMX6QDL_CLK_ARM>, +- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, +- <&clks IMX6QDL_CLK_STEP>, +- <&clks IMX6QDL_CLK_PLL1_SW>, +- <&clks IMX6QDL_CLK_PLL1_SYS>; +- clock-names = "arm", "pll2_pfd2_396m", "step", +- "pll1_sw", "pll1_sys"; +- arm-supply = <®_arm>; +- pu-supply = <®_pu>; +- soc-supply = <®_soc>; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <3>; +- next-level-cache = <&L2>; +- operating-points = < +- /* kHz uV */ +- 1200000 1275000 +- 996000 1250000 +- 852000 1250000 +- 792000 1175000 +- 396000 975000 +- >; +- fsl,soc-operating-points = < +- /* ARM kHz SOC-PU uV */ +- 1200000 1275000 +- 996000 1250000 +- 852000 1250000 +- 792000 1175000 +- 396000 1175000 +- >; +- clock-latency = <61036>; /* two CLK32 periods */ +- #cooling-cells = <2>; +- clocks = <&clks IMX6QDL_CLK_ARM>, +- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, +- <&clks IMX6QDL_CLK_STEP>, +- <&clks IMX6QDL_CLK_PLL1_SW>, +- <&clks IMX6QDL_CLK_PLL1_SYS>; +- clock-names = "arm", "pll2_pfd2_396m", "step", +- "pll1_sw", "pll1_sys"; +- arm-supply = <®_arm>; +- pu-supply = <®_pu>; +- soc-supply = <®_soc>; +- }; +- }; +- +- soc { +- ocram: sram@900000 { +- compatible = "mmio-sram"; +- reg = <0x00900000 0x40000>; +- clocks = <&clks IMX6QDL_CLK_OCRAM>; +- }; +- +- bus@2000000 { /* AIPS1 */ +- spba-bus@2000000 { +- ecspi5: spi@2018000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; +- reg = <0x02018000 0x4000>; +- interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6Q_CLK_ECSPI5>, +- <&clks IMX6Q_CLK_ECSPI5>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 11 7 1>, <&sdma 12 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- }; +- }; +- +- sata: sata@2200000 { +- compatible = "fsl,imx6q-ahci"; +- reg = <0x02200000 0x4000>; +- interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_SATA>, +- <&clks IMX6QDL_CLK_SATA_REF_100M>, +- <&clks IMX6QDL_CLK_AHB>; +- clock-names = "sata", "sata_ref", "ahb"; +- status = "disabled"; +- }; +- +- gpu_vg: gpu@2204000 { +- compatible = "vivante,gc"; +- reg = <0x02204000 0x4000>; +- interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, +- <&clks IMX6QDL_CLK_GPU2D_CORE>; +- clock-names = "bus", "core"; +- power-domains = <&pd_pu>; +- #cooling-cells = <2>; +- }; +- +- ipu2: ipu@2800000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6q-ipu"; +- reg = <0x02800000 0x400000>; +- interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, +- <0 7 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_IPU2>, +- <&clks IMX6QDL_CLK_IPU2_DI0>, +- <&clks IMX6QDL_CLK_IPU2_DI1>; +- clock-names = "bus", "di0", "di1"; +- resets = <&src 4>; +- +- ipu2_csi0: port@0 { +- reg = <0>; +- +- ipu2_csi0_from_mipi_vc2: endpoint { +- remote-endpoint = <&mipi_vc2_to_ipu2_csi0>; +- }; +- }; +- +- ipu2_csi1: port@1 { +- reg = <1>; +- +- ipu2_csi1_from_ipu2_csi1_mux: endpoint { +- remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>; +- }; +- }; +- +- ipu2_di0: port@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- ipu2_di0_disp0: endpoint@0 { +- reg = <0>; +- }; +- +- ipu2_di0_hdmi: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&hdmi_mux_2>; +- }; +- +- ipu2_di0_mipi: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&mipi_mux_2>; +- }; +- +- ipu2_di0_lvds0: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&lvds0_mux_2>; +- }; +- +- ipu2_di0_lvds1: endpoint@4 { +- reg = <4>; +- remote-endpoint = <&lvds1_mux_2>; +- }; +- }; +- +- ipu2_di1: port@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- ipu2_di1_hdmi: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&hdmi_mux_3>; +- }; +- +- ipu2_di1_mipi: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&mipi_mux_3>; +- }; +- +- ipu2_di1_lvds0: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&lvds0_mux_3>; +- }; +- +- ipu2_di1_lvds1: endpoint@4 { +- reg = <4>; +- remote-endpoint = <&lvds1_mux_3>; +- }; +- }; +- }; +- }; +- +- capture-subsystem { +- compatible = "fsl,imx-capture-subsystem"; +- ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>; +- }; +- +- display-subsystem { +- compatible = "fsl,imx-display-subsystem"; +- ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; +- }; +-}; +- +-&gpio1 { +- gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>, +- <&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>, +- <&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>, +- <&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>, +- <&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>, +- <&iomuxc 22 116 10>; +-}; +- +-&gpio2 { +- gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>, +- <&iomuxc 31 44 1>; +-}; +- +-&gpio3 { +- gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>; +-}; +- +-&gpio4 { +- gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>; +-}; +- +-&gpio5 { +- gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>, +- <&iomuxc 5 103 13>, <&iomuxc 18 150 14>; +-}; +- +-&gpio6 { +- gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>, +- <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>, +- <&iomuxc 31 86 1>; +-}; +- +-&gpio7 { +- gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>; +-}; +- +-&gpr { +- ipu1_csi0_mux { +- compatible = "video-mux"; +- mux-controls = <&mux 0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- ipu1_csi0_mux_from_mipi_vc0: endpoint { +- remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- ipu1_csi0_mux_from_parallel_sensor: endpoint { +- }; +- }; +- +- port@2 { +- reg = <2>; +- +- ipu1_csi0_mux_to_ipu1_csi0: endpoint { +- remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>; +- }; +- }; +- }; +- +- ipu2_csi1_mux { +- compatible = "video-mux"; +- mux-controls = <&mux 1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- ipu2_csi1_mux_from_mipi_vc3: endpoint { +- remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- ipu2_csi1_mux_from_parallel_sensor: endpoint { +- }; +- }; +- +- port@2 { +- reg = <2>; +- +- ipu2_csi1_mux_to_ipu2_csi1: endpoint { +- remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>; +- }; +- }; +- }; +-}; +- +-&hdmi { +- compatible = "fsl,imx6q-hdmi"; +- +- ports { +- port@2 { +- reg = <2>; +- +- hdmi_mux_2: endpoint { +- remote-endpoint = <&ipu2_di0_hdmi>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- +- hdmi_mux_3: endpoint { +- remote-endpoint = <&ipu2_di1_hdmi>; +- }; +- }; +- }; +-}; +- +-&iomuxc { +- compatible = "fsl,imx6q-iomuxc"; +-}; +- +-&ipu1_csi1 { +- ipu1_csi1_from_mipi_vc1: endpoint { +- remote-endpoint = <&mipi_vc1_to_ipu1_csi1>; +- }; +-}; +- +-&ldb { +- clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, +- <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, +- <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; +- clock-names = "di0_pll", "di1_pll", +- "di0_sel", "di1_sel", "di2_sel", "di3_sel", +- "di0", "di1"; +- +- lvds-channel@0 { +- port@2 { +- reg = <2>; +- +- lvds0_mux_2: endpoint { +- remote-endpoint = <&ipu2_di0_lvds0>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- +- lvds0_mux_3: endpoint { +- remote-endpoint = <&ipu2_di1_lvds0>; +- }; +- }; +- }; +- +- lvds-channel@1 { +- port@2 { +- reg = <2>; +- +- lvds1_mux_2: endpoint { +- remote-endpoint = <&ipu2_di0_lvds1>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- +- lvds1_mux_3: endpoint { +- remote-endpoint = <&ipu2_di1_lvds1>; +- }; +- }; +- }; +-}; +- +-&mipi_csi { +- port@1 { +- reg = <1>; +- +- mipi_vc0_to_ipu1_csi0_mux: endpoint { +- remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- +- mipi_vc1_to_ipu1_csi1: endpoint { +- remote-endpoint = <&ipu1_csi1_from_mipi_vc1>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- +- mipi_vc2_to_ipu2_csi0: endpoint { +- remote-endpoint = <&ipu2_csi0_from_mipi_vc2>; +- }; +- }; +- +- port@4 { +- reg = <4>; +- +- mipi_vc3_to_ipu2_csi1_mux: endpoint { +- remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>; +- }; +- }; +-}; +- +-&mipi_dsi { +- ports { +- port@2 { +- reg = <2>; +- +- mipi_mux_2: endpoint { +- remote-endpoint = <&ipu2_di0_mipi>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- +- mipi_mux_3: endpoint { +- remote-endpoint = <&ipu2_di1_mipi>; +- }; +- }; +- }; +-}; +- +-&mux { +- mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */ +- <0x04 0x00100000>, /* MIPI_IPU2_MUX */ +- <0x0c 0x0000000c>, /* HDMI_MUX_CTL */ +- <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */ +- <0x0c 0x00000300>, /* LVDS1_MUX_CTL */ +- <0x28 0x00000003>, /* DCIC1_MUX_CTL */ +- <0x28 0x0000000c>; /* DCIC2_MUX_CTL */ +-}; +- +-&vpu { +- compatible = "fsl,imx6q-vpu", "cnm,coda960"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-apalis.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-apalis.dtsi +deleted file mode 100644 +index 30fa349f9d05..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-apalis.dtsi ++++ /dev/null +@@ -1,953 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2014-2020 Toradex +- * Copyright 2012 Freescale Semiconductor, Inc. +- * Copyright 2011 Linaro Ltd. +- */ +- +-#include +- +-/ { +- model = "Toradex Apalis iMX6Q/D Module"; +- compatible = "toradex,apalis_imx6q", "fsl,imx6q"; +- +- /* Will be filled by the bootloader */ +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_bl_on>; +- pwms = <&pwm4 0 5000000>; +- enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; +- status = "disabled"; +- }; +- +- reg_module_3v3: regulator-module-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_module_3v3_audio: regulator-module-3v3-audio { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3_AUDIO"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- status = "disabled"; +- }; +- +- /* on module USB hub */ +- reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>; +- regulator-name = "usb_host_vbus_hub"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <2000>; +- enable-active-high; +- status = "okay"; +- }; +- +- reg_usb_host_vbus: regulator-usb-host-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; +- regulator-name = "usb_host_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_usb_host_vbus_hub>; +- status = "disabled"; +- }; +- +- sound { +- compatible = "fsl,imx-audio-sgtl5000"; +- model = "imx6q-apalis-sgtl5000"; +- ssi-controller = <&ssi1>; +- audio-codec = <&codec>; +- audio-routing = +- "LINE_IN", "Line In Jack", +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <4>; +- }; +- +- sound_spdif: sound-spdif { +- compatible = "fsl,imx-audio-spdif"; +- model = "imx-spdif"; +- spdif-controller = <&spdif>; +- spdif-in; +- spdif-out; +- status = "disabled"; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&pinctrl_flexcan1_default>; +- pinctrl-1 = <&pinctrl_flexcan1_sleep>; +- status = "disabled"; +-}; +- +-&can2 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&pinctrl_flexcan2_default>; +- pinctrl-1 = <&pinctrl_flexcan2_sleep>; +- status = "disabled"; +-}; +- +-/* Apalis SPI1 */ +-&ecspi1 { +- cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "disabled"; +-}; +- +-/* Apalis SPI2 */ +-&ecspi2 { +- cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- status = "disabled"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy>; +- phy-reset-duration = <10>; +- phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy@7 { +- interrupt-parent = <&gpio1>; +- interrupts = <30 IRQ_TYPE_LEVEL_LOW>; +- reg = <7>; +- }; +- }; +-}; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hdmi_ddc &pinctrl_hdmi_cec>; +- status = "disabled"; +-}; +- +-/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c1>; +- pinctrl-1 = <&pinctrl_i2c1_gpio>; +- scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "disabled"; +-}; +- +-/* +- * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and +- * touch screen controller +- */ +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c2>; +- pinctrl-1 = <&pinctrl_i2c2_gpio>; +- scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +- +- pmic: pfuze100@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +- +- codec: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_module_3v3_audio>; +- VDDIO-supply = <®_module_3v3>; +- VDDD-supply = <&vgen4_reg>; +- }; +- +- /* STMPE811 touch screen controller */ +- stmpe811@41 { +- compatible = "st,stmpe811"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_touch_int>; +- reg = <0x41>; +- interrupts = <10 IRQ_TYPE_LEVEL_LOW>; +- interrupt-parent = <&gpio4>; +- interrupt-controller; +- id = <0>; +- blocks = <0x5>; +- irq-trigger = <0x1>; +- /* 3.25 MHz ADC clock speed */ +- st,adc-freq = <1>; +- /* 12-bit ADC */ +- st,mod-12b = <1>; +- /* internal ADC reference */ +- st,ref-sel = <0>; +- /* ADC converstion time: 80 clocks */ +- st,sample-time = <4>; +- +- stmpe_touchscreen { +- compatible = "st,stmpe-ts"; +- /* 8 sample average control */ +- st,ave-ctrl = <3>; +- /* 7 length fractional part in z */ +- st,fraction-z = <7>; +- /* +- * 50 mA typical 80 mA max touchscreen drivers +- * current limit value +- */ +- st,i-drive = <1>; +- /* 1 ms panel driver settling time */ +- st,settling = <3>; +- /* 5 ms touch detect interrupt delay */ +- st,touch-det-delay = <5>; +- }; +- +- stmpe_adc { +- compatible = "st,stmpe-adc"; +- /* forbid to use ADC channels 3-0 (touch) */ +- st,norequest-mask = <0x0F>; +- }; +- }; +-}; +- +-/* +- * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier +- * board) +- */ +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c3>; +- pinctrl-1 = <&pinctrl_i2c3_gpio>; +- scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "disabled"; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "disabled"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- status = "disabled"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "disabled"; +-}; +- +-&pwm4 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +- status = "disabled"; +-}; +- +-&spdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spdif>; +- status = "disabled"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; +- fsl,dte-mode; +- uart-has-rtscts; +- status = "disabled"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2_dte>; +- fsl,dte-mode; +- uart-has-rtscts; +- status = "disabled"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4_dte>; +- fsl,dte-mode; +- status = "disabled"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5_dte>; +- fsl,dte-mode; +- status = "disabled"; +-}; +- +-&usbotg { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "disabled"; +-}; +- +-/* MMC1 */ +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>; +- vqmmc-supply = <®_module_3v3>; +- bus-width = <8>; +- disable-wp; +- no-1-8-v; +- status = "disabled"; +-}; +- +-/* SD1 */ +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- vqmmc-supply = <®_module_3v3>; +- bus-width = <4>; +- disable-wp; +- no-1-8-v; +- status = "disabled"; +-}; +- +-/* eMMC */ +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- vqmmc-supply = <®_module_3v3>; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- status = "okay"; +-}; +- +-&weim { +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_apalis_gpio1: gpio2io04grp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0 +- >; +- }; +- +- pinctrl_apalis_gpio2: gpio2io05grp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 +- >; +- }; +- +- pinctrl_apalis_gpio3: gpio2io06grp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0 +- >; +- }; +- +- pinctrl_apalis_gpio4: gpio2io07grp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0 +- >; +- }; +- +- pinctrl_apalis_gpio5: gpio6io10grp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0 +- >; +- }; +- +- pinctrl_apalis_gpio6: gpio6io09grp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0 +- >; +- }; +- +- pinctrl_apalis_gpio7: gpio1io02grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0 +- >; +- }; +- +- pinctrl_apalis_gpio8: gpio1io06grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0 +- >; +- }; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 +- MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 +- MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 +- MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 +- /* SGTL5000 sys_mclk */ +- MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 +- >; +- }; +- +- pinctrl_cam_mclk: cammclkgrp { +- fsl,pins = < +- /* CAM sys_mclk */ +- MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1 +- /* SPI1 cs */ +- MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 +- MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 +- MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 +- /* SPI2 cs */ +- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- /* Ethernet PHY reset */ +- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 +- /* Ethernet PHY interrupt */ +- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1 +- >; +- }; +- +- pinctrl_flexcan1_default: flexcan1defgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 +- MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan1_sleep: flexcan1slpgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0 +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0 +- >; +- }; +- +- pinctrl_flexcan2_default: flexcan2defgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 +- >; +- }; +- pinctrl_flexcan2_sleep: flexcan2slpgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0 +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0 +- >; +- }; +- +- pinctrl_gpio_bl_on: gpioblon { +- fsl,pins = < +- MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 +- >; +- }; +- +- pinctrl_gpio_keys: gpio1io04grp { +- fsl,pins = < +- /* Power button */ +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 +- >; +- }; +- +- pinctrl_hdmi_cec: hdmicecgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 +- >; +- }; +- +- pinctrl_hdmi_ddc: hdmiddcgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c1_gpio: i2c1gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1 +- MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2_gpio: i2c2gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3_gpio: i2c3gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1 +- MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1 +- >; +- }; +- +- pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */ +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1 +- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1 +- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1 +- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1 +- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1 +- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1 +- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1 +- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1 +- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 +- MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1 +- MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1 +- >; +- }; +- +- pinctrl_ipu1_lcdif: ipu1lcdifgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61 +- /* DE */ +- MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61 +- /* HSync */ +- MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61 +- /* VSync */ +- MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61 +- MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61 +- MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61 +- MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61 +- MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61 +- MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61 +- MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61 +- MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61 +- MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61 +- MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61 +- MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61 +- MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61 +- MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61 +- MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61 +- MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61 +- MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61 +- MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61 +- MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61 +- MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61 +- MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61 +- MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61 +- MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61 +- MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61 +- MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61 +- MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61 +- >; +- }; +- +- pinctrl_ipu2_vdac: ipu2vdacgrp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1 +- MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1 +- MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1 +- MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1 +- MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9 +- MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9 +- MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9 +- MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9 +- MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9 +- MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9 +- MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9 +- MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9 +- MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9 +- MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9 +- MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9 +- MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9 +- MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9 +- MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9 +- MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9 +- MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9 +- >; +- }; +- +- pinctrl_mmc_cd: gpiommccdgrp { +- fsl,pins = < +- /* MMC1 CD */ +- MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { +- fsl,pins = < +- /* USBH_EN */ +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058 +- >; +- }; +- +- pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp { +- fsl,pins = < +- /* USBH_HUB_EN */ +- MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058 +- >; +- }; +- +- pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp { +- fsl,pins = < +- /* USBO1 power en */ +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058 +- >; +- }; +- +- pinctrl_reset_moci: gpioresetmocigrp { +- fsl,pins = < +- /* RESET_MOCI control */ +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058 +- >; +- }; +- +- pinctrl_sd_cd: gpiosdcdgrp { +- fsl,pins = < +- /* SD1 CD */ +- MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0 +- >; +- }; +- +- pinctrl_spdif: spdifgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 +- MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 +- >; +- }; +- +- pinctrl_touch_int: gpiotouchintgrp { +- fsl,pins = < +- /* STMPE811 interrupt */ +- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 +- >; +- }; +- +- pinctrl_uart1_dce: uart1dcegrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- /* DTE mode */ +- pinctrl_uart1_dte: uart1dtegrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 +- >; +- }; +- +- /* Additional DTR, DSR, DCD */ +- pinctrl_uart1_ctrl: uart1ctrlgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 +- MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 +- MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 +- >; +- }; +- +- pinctrl_uart2_dce: uart2dcegrp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- >; +- }; +- +- /* DTE mode */ +- pinctrl_uart2_dte: uart2dtegrp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 +- MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4_dce: uart4dcegrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- /* DTE mode */ +- pinctrl_uart4_dte: uart4dtegrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5_dce: uart5dcegrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- /* DTE mode */ +- pinctrl_uart5_dte: uart5dtegrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc1_4bit: usdhc1grp_4bit { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 +- >; +- }; +- +- pinctrl_usdhc1_8bit: usdhc1grp_8bit { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 +- MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 +- MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 +- MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- /* eMMC reset */ +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-apf6.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-apf6.dtsi +deleted file mode 100644 +index b78ed7974ea9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-apf6.dtsi ++++ /dev/null +@@ -1,152 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Copyright 2015 Armadeus Systems +- +-#include +-#include +- +-/ { +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- vin-supply = <®_3p3v>; +- }; +- +- usdhc1_pwrseq: usdhc1-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; +- post-power-on-delay-ms = <15>; +- power-off-delay-us = <70>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-reset-duration = <10>; +- phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; +- phy-handle = <ðphy1>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy1: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- interrupt-parent = <&gpio1>; +- interrupts = <28 IRQ_TYPE_LEVEL_LOW>; +- status = "okay"; +- }; +- }; +-}; +- +-/* Bluetooth */ +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-/* Wi-Fi */ +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- bus-width = <4>; +- mmc-pwrseq = <&usdhc1_pwrseq>; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_1p8v>; +- cap-power-off-card; +- keep-power-in-suspend; +- non-removable; +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1271"; +- reg = <2>; +- interrupt-parent = <&gpio2>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; +- ref-clock-frequency = <38400000>; +- tcxo-clock-frequency = <38400000>; +- }; +-}; +- +-/* eMMC */ +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0 +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x130b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b0 +- MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b0 +- MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b0 +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b0 +- MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x130b0 /* BT_EN */ +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 +- MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x130b0 /* WL_EN */ +- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x130b0 /* WL_IRQ */ +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-apf6dev.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-apf6dev.dtsi +deleted file mode 100644 +index 2577eb4f535a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-apf6dev.dtsi ++++ /dev/null +@@ -1,451 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Copyright 2015 Armadeus Systems +- +-#include +-#include +-#include +- +-/ { +- chosen { +- stdout-path = &uart4; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm3 0 191000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <0>; +- power-supply = <®_5v>; +- }; +- +- disp0 { +- compatible = "fsl,imx-parallel-display"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_disp0>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- display_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- user-button { +- label = "User button"; +- gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- user-led { +- label = "User LED"; +- gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "on"; +- }; +- }; +- +- panel { +- compatible = "armadeus,st0700-adapt"; +- power-supply = <®_3p3v>; +- backlight = <&backlight>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- vin-supply = <®_5v>; +- }; +- +- reg_5v: regulator-5v { +- compatible = "regulator-fixed"; +- regulator-name = "5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- sound { +- compatible = "fsl,imx6-armadeus-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "imx6-armadeus-sgtl5000"; +- ssi-controller = <&ssi1>; +- audio-codec = <&codec>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <3>; +- }; +- +- sound-spdif { +- compatible = "fsl,imx-audio-spdif"; +- model = "imx-spdif"; +- spdif-controller = <&spdif>; +- spdif-out; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- xceiver-supply = <®_5v>; +- status = "okay"; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, +- <&gpio4 10 GPIO_ACTIVE_LOW>, +- <&gpio4 11 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- touchscreen@48 { +- compatible = "semtech,sx8654"; +- reg = <0x48>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_touchscreen>; +- interrupt-parent = <&gpio6>; +- interrupts = <3 IRQ_TYPE_EDGE_FALLING>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- codec: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; +- }; +- +- rtc@6f { +- compatible = "microchip,mcp7940x"; +- reg = <0x6f>; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&display_in>; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio6 2 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm3 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "okay"; +-}; +- +-/* GPS */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-/* GSM */ +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3 &pinctrl_gsm>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-/* console */ +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_5v>; +- phy_type = "utmi"; +- status = "okay"; +-}; +- +-&usbotg { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- vbus-supply = <®_usb_otg_vbus>; +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-/* microSD */ +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- status = "okay"; +-}; +- +-&spdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spdif>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpios>; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 +- MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 +- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_gpio_keys: gpiokeysgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x130b0 +- >; +- }; +- +- pinctrl_gpios: gpiosgrp { +- fsl,pins = < +- MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1 +- MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 +- MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1 +- MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1 +- MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1 +- MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1 +- MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1 +- MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1 +- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1 +- >; +- }; +- +- pinctrl_gsm: gsmgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 /* GSM_POKIN */ +- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x130b0 /* GSM_PWR_EN */ +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_ipu1_disp0: ipu1disp0grp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100b1 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100b1 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100b1 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100b1 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100b1 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100b1 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100b1 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100b1 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100b1 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100b1 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100b1 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100b1 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100b1 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100b1 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100b1 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100b1 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100b1 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100b1 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100b1 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100b1 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100b1 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100b1 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x130b0 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b0 +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0 +- MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b0 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b0 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- >; +- }; +- +- pinctrl_spdif: spdifgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 +- >; +- }; +- +- pinctrl_touchscreen: touchscreengrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-aristainetos.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-aristainetos.dtsi +deleted file mode 100644 +index e21f6ac864e5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-aristainetos.dtsi ++++ /dev/null +@@ -1,408 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * support fot the imx6 based aristainetos board +- * +- * Copyright (C) 2014 Heiko Schocher +- */ +- +-#include +- +-/ { +- +- reg_2p5v: regulator-2p5v { +- compatible = "regulator-fixed"; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usbh1_vbus: regulator-usbh1-vbus { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_aristainetos_usbh1_vbus>; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usbotg_vbus: regulator-usbotg-vbus { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_aristainetos_usbotg_vbus>; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- tmp103: tmp103@71 { +- compatible = "ti,tmp103"; +- reg = <0x71>; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- rtc@68 { +- compatible = "dallas,m41t00"; +- reg = <0x68>; +- }; +-}; +- +-&ecspi4 { +- cs-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi4>; +- status = "okay"; +- +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q128a11", "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rmii"; +- phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- status = "okay"; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usbh1_vbus>; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usbotg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- vmmc-supply = <®_3p3v>; +- cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- vmmc-supply = <®_3p3v>; +- cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog &pinctrl_gpio>; +- +- imx6qdl-aristainetos { +- pinctrl_aristainetos_usbh1_vbus: aristainetos-usbh1-vbus { +- fsl,pins = ; +- }; +- +- pinctrl_aristainetos_usbotg_vbus: aristainetos-usbotg-vbus { +- fsl,pins = ; +- }; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 +- >; +- }; +- +- pinctrl_backlight: backlightgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 +- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 +- MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 +- MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x100b1 +- >; +- }; +- +- pinctrl_ecspi4: ecspi4grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 +- MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b1 +- MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */ +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 +- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 +- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 +- MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_gpio: gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 +- MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 +- MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 +- MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x1b0b0 +- MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 +- MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 +- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 +- MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 +- MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 +- >; +- }; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x10 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_ipu_disp: ipudisp1grp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 +- MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x20000 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 +- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-aristainetos2.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-aristainetos2.dtsi +deleted file mode 100644 +index 563bf9d44fe0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-aristainetos2.dtsi ++++ /dev/null +@@ -1,637 +0,0 @@ +-/* +- * support for the imx6 based aristainetos2 board +- * +- * Copyright (C) 2015 Heiko Schocher +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-#include +-#include +- +-/ { +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- enable-gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_2p5v: regulator-2p5v { +- compatible = "regulator-fixed"; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usbh1_vbus: regulator-usbh1-vbus { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_aristainetos2_usbh1_vbus>; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usbotg_vbus: regulator-usbotg-vbus { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_aristainetos2_usbotg_vbus>; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- status = "okay"; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW +- &gpio4 10 GPIO_ACTIVE_LOW +- &gpio4 11 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +-}; +- +-&ecspi2 { +- cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW &gpio2 27 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- status = "okay"; +-}; +- +-&ecspi4 { +- cs-gpios = <&gpio3 29 GPIO_ACTIVE_LOW &gpio5 2 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi4>; +- status = "okay"; +- +- flash: m25p80@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q128a11", "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <1>; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic@58 { +- compatible = "dlg,da9063"; +- reg = <0x58>; +- interrupt-parent = <&gpio1>; +- interrupts = <04 0x8>; +- +- regulators { +- bcore1 { +- regulator-name = "bcore1"; +- regulator-always-on = <1>; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- bcore2 { +- regulator-name = "bcore2"; +- regulator-always-on = <1>; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- bpro { +- regulator-name = "bpro"; +- regulator-always-on = <1>; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- bperi { +- regulator-name = "bperi"; +- regulator-always-on = <1>; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- bmem { +- regulator-name = "bmem"; +- regulator-always-on = <1>; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo2 { +- regulator-name = "ldo2"; +- regulator-always-on = <1>; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo3 { +- regulator-name = "ldo3"; +- regulator-always-on = <1>; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo4 { +- regulator-name = "ldo4"; +- regulator-always-on = <1>; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo5 { +- regulator-name = "ldo5"; +- regulator-always-on = <1>; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo6 { +- regulator-name = "ldo6"; +- regulator-always-on = <1>; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo7 { +- regulator-name = "ldo7"; +- regulator-always-on = <1>; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo8 { +- regulator-name = "ldo8"; +- regulator-always-on = <1>; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo9 { +- regulator-name = "ldo9"; +- regulator-always-on = <1>; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo10 { +- regulator-name = "ldo10"; +- regulator-always-on = <1>; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo11 { +- regulator-name = "ldo11"; +- regulator-always-on = <1>; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- bio { +- regulator-name = "bio"; +- regulator-always-on = <1>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- }; +- }; +- +- tmp103: tmp103@71 { +- compatible = "ti,tmp103"; +- reg = <0x71>; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- expander: tca6416@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- #gpio-cells = <2>; +- gpio-controller; +- }; +- +- rtc@68 { +- compatible = "dallas,m41t00"; +- reg = <0x68>; +- }; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +- +- eeprom@50{ +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- +- eeprom@57{ +- compatible = "atmel,24c64"; +- reg = <0x57>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii"; +- phy-handle = <ðphy>; +- phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy { +- compatible = "ethernet-phy-ieee802.3-c22"; +- txd0-skew-ps = <0>; +- txd1-skew-ps = <0>; +- txd2-skew-ps = <0>; +- txd3-skew-ps = <0>; +- }; +- }; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- status = "okay"; +-}; +- +-&pcie { +- reset-gpio = <&gpio2 16 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usbh1_vbus>; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usbotg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; +- no-1-8-v; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio>; +- +- pinctrl_audmux: audmux { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */ +- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */ +- MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */ +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 +- MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 +- MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 +- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 /* SS0# */ +- MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 /* SS1# */ +- >; +- }; +- +- pinctrl_ecspi4: ecspi4grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 +- MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ +- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ +- MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */ +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 +- MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 +- MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_gpio: gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* led enable */ +- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* LCD power enable */ +- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* led yellow */ +- MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 /* led red */ +- MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /* led green */ +- MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 /* led blue */ +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* Profibus IRQ */ +- MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* FPGA IRQ */ +- MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 /* spi bus #2 SS driver enable */ +- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 /* RST_LOC# PHY reset input (has pull-down!)*/ +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b0b0 /* USB_OTG_ID = GPIO1_24*/ +- MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* Touchscreen IRQ */ +- MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b0 /* PCIe reset */ +- >; +- }; +- +- pinctrl_gpmi_nand: gpmi-nand { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 +- MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 /* backlight enable */ +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_aristainetos2_usbh1_vbus: aristainetos-usbh1-vbus { +- fsl,pins = ; +- }; +- +- pinctrl_aristainetos2_usbotg_vbus: aristainetos-usbotg-vbus { +- fsl,pins = ; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 +- MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 /* SD1 card detect input */ +- MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* SD1 write protect input */ +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 +- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 /* SD2 level shifter output enable */ +- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 /* SD2 card detect input */ +- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SD2 write protect input */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-colibri-v1_1-uhs.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-colibri-v1_1-uhs.dtsi +deleted file mode 100644 +index 7672fbfc29be..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-colibri-v1_1-uhs.dtsi ++++ /dev/null +@@ -1,44 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2020 Toradex +- */ +- +-&iomuxc { +- pinctrl_usdhc1_100mhz: usdhc1grp100mhz { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1grp200mhz { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 +- >; +- }; +-}; +- +-/* Colibri MMC */ +-&usdhc1 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; +- vmmc-supply = <®_module_3v3>; +- vqmmc-supply = <&vgen3_reg>; +- wakeup-source; +- keep-power-in-suspend; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-colibri.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-colibri.dtsi +deleted file mode 100644 +index 4e2a309c93fa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-colibri.dtsi ++++ /dev/null +@@ -1,864 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2014-2020 Toradex +- * Copyright 2012 Freescale Semiconductor, Inc. +- * Copyright 2011 Linaro Ltd. +- */ +- +-#include +- +-/ { +- model = "Toradex Colibri iMX6DL/S Module"; +- compatible = "toradex,colibri_imx6dl", "fsl,imx6dl"; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_bl_on>; +- pwms = <&pwm3 0 5000000>; +- enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ +- status = "disabled"; +- }; +- +- reg_module_3v3: regulator-module-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_module_3v3_audio: regulator-module-3v3-audio { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3_AUDIO"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_host_vbus: regulator-usb-host-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; +- regulator-name = "usb_host_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */ +- status = "disabled"; +- }; +- +- sound { +- compatible = "fsl,imx-audio-sgtl5000"; +- model = "imx6dl-colibri-sgtl5000"; +- ssi-controller = <&ssi1>; +- audio-codec = <&codec>; +- audio-routing = +- "Headphone Jack", "HP_OUT", +- "LINE_IN", "Line In Jack", +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias"; +- mux-int-port = <1>; +- mux-ext-port = <5>; +- }; +- +- /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */ +- sound_spdif: sound-spdif { +- compatible = "fsl,imx-audio-spdif"; +- model = "imx-spdif"; +- spdif-controller = <&spdif>; +- spdif-in; +- spdif-out; +- status = "disabled"; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>; +- status = "okay"; +-}; +- +-/* Optional on SODIMM 55/63 */ +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- status = "disabled"; +-}; +- +-/* Optional on SODIMM 178/188 */ +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- status = "disabled"; +-}; +- +-/* Colibri SSP */ +-&ecspi4 { +- cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi4>; +- status = "disabled"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rmii"; +- phy-handle = <ðphy>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy@0 { +- reg = <0>; +- micrel,led-mode = <0>; +- }; +- }; +-}; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hdmi_ddc>; +- status = "disabled"; +-}; +- +-/* +- * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and +- * touch screen controller +- */ +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c2>; +- pinctrl-0 = <&pinctrl_i2c2_gpio>; +- scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +- +- pmic: pfuze100@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vgen1: unused */ +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* +- * +V3.3_1.8_SD1 coming off VGEN3 and supplying +- * the i.MX 6 NVCC_SD1. +- */ +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +- +- codec: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_module_3v3_audio>; +- VDDIO-supply = <®_module_3v3>; +- VDDD-supply = <&vgen4_reg>; +- lrclk-strength = <3>; +- }; +- +- /* STMPE811 touch screen controller */ +- stmpe811@41 { +- compatible = "st,stmpe811"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_touch_int>; +- reg = <0x41>; +- interrupts = <20 IRQ_TYPE_LEVEL_LOW>; +- interrupt-parent = <&gpio6>; +- interrupt-controller; +- id = <0>; +- blocks = <0x5>; +- irq-trigger = <0x1>; +- /* 3.25 MHz ADC clock speed */ +- st,adc-freq = <1>; +- /* 12-bit ADC */ +- st,mod-12b = <1>; +- /* internal ADC reference */ +- st,ref-sel = <0>; +- /* ADC converstion time: 80 clocks */ +- st,sample-time = <4>; +- +- stmpe_touchscreen { +- compatible = "st,stmpe-ts"; +- /* 8 sample average control */ +- st,ave-ctrl = <3>; +- /* 7 length fractional part in z */ +- st,fraction-z = <7>; +- /* +- * 50 mA typical 80 mA max touchscreen drivers +- * current limit value +- */ +- st,i-drive = <1>; +- /* 1 ms panel driver settling time */ +- st,settling = <3>; +- /* 5 ms touch detect interrupt delay */ +- st,touch-det-delay = <5>; +- }; +- +- stmpe_adc { +- compatible = "st,stmpe-adc"; +- /* forbid to use ADC channels 3-0 (touch) */ +- st,norequest-mask = <0x0F>; +- }; +- }; +-}; +- +-/* +- * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) +- */ +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c3>; +- pinctrl-1 = <&pinctrl_i2c3_gpio>; +- scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "disabled"; +-}; +- +-/* Colibri PWM */ +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "disabled"; +-}; +- +-/* Colibri PWM */ +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- status = "disabled"; +-}; +- +-/* Colibri PWM */ +-&pwm3 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "disabled"; +-}; +- +-/* Colibri PWM */ +-&pwm4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +- status = "disabled"; +-}; +- +-/* Optional S/PDIF out on SODIMM 137 */ +-&spdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spdif>; +- status = "disabled"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-/* Colibri UART_A */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; +- fsl,dte-mode; +- uart-has-rtscts; +- status = "disabled"; +-}; +- +-/* Colibri UART_B */ +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2_dte>; +- fsl,dte-mode; +- uart-has-rtscts; +- status = "disabled"; +-}; +- +-/* Colibri UART_C */ +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3_dte>; +- fsl,dte-mode; +- status = "disabled"; +-}; +- +-&usbotg { +- disable-over-current; +- dr_mode = "peripheral"; +- status = "disabled"; +-}; +- +-/* Colibri MMC */ +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; +- cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ +- disable-wp; +- vqmmc-supply = <®_module_3v3>; +- bus-width = <4>; +- no-1-8-v; +- status = "disabled"; +-}; +- +-/* eMMC */ +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- vqmmc-supply = <®_module_3v3>; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- status = "okay"; +-}; +- +-&weim { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0 +- &pinctrl_weim_cs1 &pinctrl_weim_cs2 +- &pinctrl_weim_rdnwr &pinctrl_weim_npwe>; +- #address-cells = <2>; +- #size-cells = <1>; +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh_oc_1>; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 +- MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 +- MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 +- MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 +- /* SGTL5000 sys_mclk */ +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 +- >; +- }; +- +- pinctrl_cam_mclk: cammclkgrp { +- fsl,pins = < +- /* Parallel Camera CAM sys_mclk */ +- MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 +- >; +- }; +- +- pinctrl_ecspi4: ecspi4grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 +- MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 +- /* SPI CS */ +- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 +- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 +- MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_gpio_bl_on: gpioblon { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 +- >; +- }; +- +- pinctrl_gpio_keys: gpiokeys { +- fsl,pins = < +- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 +- >; +- }; +- +- pinctrl_hdmi_ddc: hdmiddcgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2_gpio: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1 +- MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3_gpio: i2c3gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 +- >; +- }; +- +- pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */ +- fsl,pins = < +- MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 +- MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 +- MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 +- MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 +- MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 +- MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 +- MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 +- MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1 +- MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1 +- MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1 +- MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1 +- /* Disable PWM pins on camera interface */ +- MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 +- MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40 +- >; +- }; +- +- pinctrl_ipu1_lcdif: ipu1lcdifgrp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1 +- >; +- }; +- +- pinctrl_mic_gnd: gpiomicgnd { +- fsl,pins = < +- /* Controls Mic GND, PU or '1' pull Mic GND to GND */ +- MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0 +- >; +- }; +- +- pinctrl_mmc_cd: gpiommccd { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 +- MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 +- MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { +- fsl,pins = < +- /* USBH_EN */ +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058 +- >; +- }; +- +- pinctrl_usbh_oc_1: usbhoc1grp { +- fsl,pins = < +- /* USBH_OC */ +- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 +- >; +- }; +- +- pinctrl_spdif: spdifgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 +- >; +- }; +- +- pinctrl_touch_int: gpiotouchintgrp { +- fsl,pins = < +- /* STMPE811 interrupt */ +- MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0 +- >; +- }; +- +- pinctrl_uart1_dce: uart1dcegrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- /* DTE mode */ +- pinctrl_uart1_dte: uart1dtegrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 +- >; +- }; +- +- /* Additional DTR, DSR, DCD */ +- pinctrl_uart1_ctrl: uart1ctrlgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 +- MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 +- MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 +- >; +- }; +- +- pinctrl_uart2_dte: uart2dtegrp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 +- MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3_dte: uart3dtegrp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbc_det: usbcdetgrp { +- fsl,pins = < +- /* USBC_DET */ +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 +- /* USBC_DET_EN */ +- MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058 +- /* USBC_DET_OVERWRITE */ +- MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058 +- >; +- }; +- +- pinctrl_usbc_id_1: usbc_id-1 { +- fsl,pins = < +- /* USBC_ID */ +- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- /* eMMC reset */ +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 +- >; +- }; +- +- pinctrl_weim_cs0: weimcs0grp { +- fsl,pins = < +- /* nEXT_CS0 */ +- MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 +- >; +- }; +- +- pinctrl_weim_cs1: weimcs1grp { +- fsl,pins = < +- /* nEXT_CS1 */ +- MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 +- >; +- }; +- +- pinctrl_weim_cs2: weimcs2grp { +- fsl,pins = < +- /* nEXT_CS2 */ +- MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1 +- >; +- }; +- +- pinctrl_weim_sram: weimsramgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 +- MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 +- /* Data */ +- MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 +- MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 +- /* Address */ +- MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 +- MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 +- MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 +- MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 +- MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 +- MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 +- MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 +- MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 +- MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 +- MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 +- MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 +- MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 +- MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 +- MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 +- MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 +- MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 +- >; +- }; +- +- pinctrl_weim_rdnwr: weimrdnwr { +- fsl,pins = < +- MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040 +- MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0 +- >; +- }; +- +- pinctrl_weim_npwe: weimnpwe { +- fsl,pins = < +- MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040 +- MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0 +- >; +- }; +- +- /* ADDRESS[16:18] [25] used as GPIO */ +- pinctrl_weim_gpio_1: weimgpio-1 { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 +- MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 +- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 +- MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 +- MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 +- MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 +- MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 +- MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 +- MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 +- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +- >; +- }; +- +- /* ADDRESS[19:24] used as GPIO */ +- pinctrl_weim_gpio_2: weimgpio-2 { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 +- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 +- MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 +- MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 +- MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 +- MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 +- MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 +- MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 +- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +- >; +- }; +- +- /* DATA[16:31] used as GPIO */ +- pinctrl_weim_gpio_3: weimgpio-3 { +- fsl,pins = < +- MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 +- MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 +- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 +- MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 +- MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 +- MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 +- MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 +- MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 +- MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 +- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 +- MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 +- MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 +- MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +- >; +- }; +- +- /* DQM[0:3] used as GPIO */ +- pinctrl_weim_gpio_4: weimgpio-4 { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 +- MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 +- MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 +- MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 +- >; +- }; +- +- /* RDY used as GPIO */ +- pinctrl_weim_gpio_5: weimgpio-5 { +- fsl,pins = < +- MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 +- >; +- }; +- +- /* ADDRESS[16] DATA[30] used as GPIO */ +- pinctrl_weim_gpio_6: weimgpio-6 { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 +- MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-cubox-i.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-cubox-i.dtsi +deleted file mode 100644 +index 1e530d892b76..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-cubox-i.dtsi ++++ /dev/null +@@ -1,270 +0,0 @@ +-/* +- * Copyright (C) 2014 Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-#include +-#include +- +-/ { +- /* Will be filled by the bootloader */ +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0>; +- }; +- +- ir_recv: ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio3 9 1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_cubox_i_ir>; +- }; +- +- led-controller { +- compatible = "pwm-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_cubox_i_pwm1>; +- +- led-1 { +- active-low; +- label = "imx6:red:front"; +- max-brightness = <248>; +- pwms = <&pwm1 0 50000>; +- }; +- }; +- +- v_5v0: regulator-v-5v0 { +- compatible = "regulator-fixed"; +- regulator-always-on; +- regulator-max-microvolt = <5000000>; +- regulator-min-microvolt = <5000000>; +- regulator-name = "v_5v0"; +- }; +- +- v_usb2: regulator-v-usb2 { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_cubox_i_usbh1_vbus>; +- regulator-max-microvolt = <5000000>; +- regulator-min-microvolt = <5000000>; +- regulator-name = "v_usb2"; +- vin-supply = <&v_5v0>; +- }; +- +- v_usb1: regulator-v-usb1 { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_cubox_i_usbotg_vbus>; +- regulator-max-microvolt = <5000000>; +- regulator-min-microvolt = <5000000>; +- regulator-name = "v_usb1"; +- vin-supply = <&v_5v0>; +- }; +- +- sound-spdif { +- compatible = "fsl,imx-audio-spdif"; +- model = "Integrated SPDIF"; +- /* IMX6 doesn't implement this yet */ +- spdif-controller = <&spdif>; +- spdif-out; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&pinctrl_gpio_key>; +- pinctrl-names = "default"; +- +- button_0 { +- label = "Button 0"; +- gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +-}; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_cubox_i_hdmi>; +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_cubox_i_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_cubox_i_i2c3>; +- +- status = "okay"; +- +- rtc@68 { +- compatible = "nxp,pcf8523"; +- reg = <0x68>; +- }; +-}; +- +-&iomuxc { +- cubox_i { +- pinctrl_cubox_i_hdmi: cubox-i-hdmi { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 +- >; +- }; +- +- pinctrl_cubox_i_i2c2: cubox-i-i2c2 { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_cubox_i_i2c3: cubox-i-i2c3 { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_cubox_i_ir: cubox-i-ir { +- fsl,pins = < +- MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 +- >; +- }; +- +- pinctrl_cubox_i_pwm1: cubox-i-pwm1-front-led { +- fsl,pins = ; +- }; +- +- pinctrl_cubox_i_spdif: cubox-i-spdif { +- fsl,pins = ; +- }; +- +- pinctrl_cubox_i_usbh1: cubox-i-usbh1 { +- fsl,pins = ; +- }; +- +- pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus { +- fsl,pins = ; +- }; +- +- pinctrl_cubox_i_usbotg: cubox-i-usbotg { +- /* +- * The Cubox-i pulls ID low, but as it's pointless +- * leaving it as a pull-up, even if it is just 10uA. +- */ +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 +- MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 +- >; +- }; +- +- pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus { +- fsl,pins = ; +- }; +- +- pinctrl_cubox_i_usdhc2_aux: cubox-i-usdhc2-aux { +- fsl,pins = < +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 +- MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 +- >; +- }; +- +- pinctrl_cubox_i_usdhc2: cubox-i-usdhc2 { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 +- >; +- }; +- +- pinctrl_gpio_key: gpio-key { +- fsl,pins = < +- MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x17059 +- >; +- }; +- }; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- status = "okay"; +-}; +- +-&spdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_cubox_i_spdif>; +- status = "okay"; +-}; +- +-&usbh1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_cubox_i_usbh1>; +- vbus-supply = <&v_usb2>; +- status = "okay"; +-}; +- +-&usbotg { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_cubox_i_usbotg>; +- vbus-supply = <&v_usb1>; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2>; +- vmmc-supply = <&vcc_3v3>; +- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&vcc_3v3 { +- vin-supply = <&v_5v0>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-dfi-fs700-m60.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-dfi-fs700-m60.dtsi +deleted file mode 100644 +index 648f5fcb72e6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-dfi-fs700-m60.dtsi ++++ /dev/null +@@ -1,201 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +- +-/ { +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- dummy_reg: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "dummy-supply"; +- }; +- +- reg_usb_otg_vbus: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 0>; +- enable-active-high; +- }; +- }; +- +- chosen { +- stdout-path = &uart1; +- }; +-}; +- +-&ecspi3 { +- cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi3>; +- status = "okay"; +- +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "sst,sst25vf040b", "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- status = "okay"; +- phy-mode = "rgmii"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx6qdl-dfi-fs700-m60 { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 +- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC irq */ +- MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 /* MAX11801 irq */ +- MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000030b0 /* Backlight enable */ +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* card detect */ +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 +- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 +- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 +- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +- >; +- }; +- +- pinctrl_ecspi3: ecspi3grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 +- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 +- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 +- MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ +- >; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc2 { /* module slot */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&usdhc3 { /* baseboard slot */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +-}; +- +-&usdhc4 { /* eMMC */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-dhcom-drc02.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-dhcom-drc02.dtsi +deleted file mode 100644 +index 3d0a50a9ab21..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-dhcom-drc02.dtsi ++++ /dev/null +@@ -1,139 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2021 DH electronics GmbH +- */ +- +-/ { +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-/* +- * Special SoM hardware required which uses the pins from micro SD card. The +- * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 +- * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD +- * card must be disabled and the uart1 rts/cts must be output on other DHCOM +- * pins, see uart1 and usdhc3 node below. +- */ +-&can2 { +- status = "okay"; +-}; +- +-&gpio1 { +- /* +- * NOTE: On DRC02, the RS485_RX_En is controlled by a separate +- * GPIO line, however the i.MX6 UART driver assumes RX happens +- * during TX anyway and that it only controls drive enable DE +- * line. Hence, the RX is always enabled here. +- */ +- rs485-rx-en-hog { +- gpio-hog; +- gpios = <18 0>; /* GPIO Q */ +- line-name = "rs485-rx-en"; +- output-low; +- }; +-}; +- +-&gpio3 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "DRC02-In1", "", "", "", ""; +-}; +- +-&gpio4 { +- gpio-line-names = +- "", "", "", "", "", "DHCOM-E", "DRC02-In2", "DHCOM-H", +- "DHCOM-I", "DRC02-HW0", "", "", "", "", "", "", +- "", "", "", "", "DRC02-Out1", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio6 { +- gpio-line-names = +- "", "", "", "DRC02-Out2", "", "", "SOM-HW1", "", +- "", "", "", "", "", "", "DRC02-HW2", "DRC02-HW1", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&i2c1 { +- eeprom@50 { +- compatible = "atmel,24c04"; +- reg = <0x50>; +- pagesize = <16>; +- }; +-}; +- +-&uart1 { +- /* +- * Due to the use of can2 the signals for can2 Tx and Rx are routed to +- * DHCOM UART1 rts/cts pins. Therefore this UART have to use DHCOM GPIOs +- * for rts/cts. So configure DHCOM GPIO I as rts and GPIO M as cts. +- */ +- /delete-property/ uart-has-rtscts; +- cts-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; /* GPIO M */ +- pinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>; +- pinctrl-names = "default"; +- rts-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ +-}; +- +-&uart5 { +- /* +- * On DRC02 this UART is used as RS485 interface and RS485_TX_En is +- * controlled by DHCOM GPIO P. So remove rts/cts pins and the property +- * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via +- * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1 +- * node above. +- */ +- /delete-property/ uart-has-rtscts; +- linux,rs485-enabled-at-boot-time; +- pinctrl-0 = <&pinctrl_uart5_core &pinctrl_dhcom_p &pinctrl_dhcom_q>; +- pinctrl-names = "default"; +- rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */ +-}; +- +-&usdhc2 { /* SD card */ +- status = "okay"; +-}; +- +-&usdhc3 { +- /* +- * Due to the use of can2 the micro SD card on module have to be +- * disabled, because the pins SD3_DAT0 and SD3_DAT1 are muxed as +- * can2 Tx and Rx. +- */ +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl-0 = < +- /* +- * The following DHCOM GPIOs are used on this board. +- * Therefore, they have been removed from the list below. +- * I: uart1 rts +- * M: uart1 cts +- * P: uart5 rs485-tx-en +- * Q: uart5 rs485-rx-en +- */ +- &pinctrl_hog_base +- &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c +- &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f +- &pinctrl_dhcom_g &pinctrl_dhcom_h +- &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l +- &pinctrl_dhcom_n &pinctrl_dhcom_o +- &pinctrl_dhcom_r +- &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u +- &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int +- >; +- pinctrl-names = "default"; +- +- pinctrl_uart5_core: uart5-core-grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-dhcom-pdk2.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-dhcom-pdk2.dtsi +deleted file mode 100644 +index dc21853706a5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-dhcom-pdk2.dtsi ++++ /dev/null +@@ -1,361 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2015-2021 DH electronics GmbH +- * Copyright (C) 2018 Marek Vasut +- */ +- +-#include +- +-/ { +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- clk_ext_audio_codec: clock-codec { +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- compatible = "fixed-clock"; +- }; +- +- display_bl: display-bl { +- brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; +- compatible = "pwm-backlight"; +- default-brightness-level = <8>; +- enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; /* GPIO G */ +- pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>; +- status = "okay"; +- }; +- +- lcd_display: disp0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx-parallel-display"; +- interface-pix-fmt = "rgb24"; +- pinctrl-0 = <&pinctrl_ipu1_lcdif &pinctrl_dhcom_g>; +- pinctrl-names = "default"; +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- lcd_display_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lcd_display_out: endpoint { +- remote-endpoint = <&lcd_panel_in>; +- }; +- }; +- }; +- +- gpio-keys { +- #size-cells = <0>; +- compatible = "gpio-keys"; +- +- button-0 { +- gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* GPIO A */ +- label = "TA1-GPIO-A"; +- linux,code = ; +- pinctrl-0 = <&pinctrl_dhcom_a>; +- pinctrl-names = "default"; +- wakeup-source; +- }; +- +- button-1 { +- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* GPIO B */ +- label = "TA2-GPIO-B"; +- linux,code = ; +- pinctrl-0 = <&pinctrl_dhcom_b>; +- pinctrl-names = "default"; +- wakeup-source; +- }; +- +- button-2 { +- gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; /* GPIO C */ +- label = "TA3-GPIO-C"; +- linux,code = ; +- pinctrl-0 = <&pinctrl_dhcom_c>; +- pinctrl-names = "default"; +- wakeup-source; +- }; +- +- button-3 { +- gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; /* GPIO D */ +- label = "TA4-GPIO-D"; +- linux,code = ; +- pinctrl-0 = <&pinctrl_dhcom_d>; +- pinctrl-names = "default"; +- wakeup-source; +- }; +- }; +- +- led { +- compatible = "gpio-leds"; +- +- /* +- * Disable led-5, because GPIO E is +- * already used as touch interrupt. +- */ +- led-5 { +- color = ; +- default-state = "off"; +- function = LED_FUNCTION_INDICATOR; +- gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */ +- pinctrl-0 = <&pinctrl_dhcom_e>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- led-6 { +- color = ; +- default-state = "off"; +- function = LED_FUNCTION_INDICATOR; +- gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */ +- pinctrl-0 = <&pinctrl_dhcom_f>; +- pinctrl-names = "default"; +- }; +- +- led-7 { +- color = ; +- default-state = "off"; +- function = LED_FUNCTION_INDICATOR; +- gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */ +- pinctrl-0 = <&pinctrl_dhcom_h>; +- pinctrl-names = "default"; +- }; +- +- led-8 { +- color = ; +- default-state = "off"; +- function = LED_FUNCTION_INDICATOR; +- gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ +- pinctrl-0 = <&pinctrl_dhcom_i>; +- pinctrl-names = "default"; +- }; +- }; +- +- panel { +- backlight = <&display_bl>; +- compatible = "edt,etm0700g0edh6"; +- +- port { +- lcd_panel_in: endpoint { +- remote-endpoint = <&lcd_display_out>; +- }; +- }; +- }; +- +- sound { +- audio-codec = <&sgtl5000>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "LINE_IN", "Line In Jack", +- "Headphone Jack", "HP_OUT"; +- compatible = "fsl,imx-audio-sgtl5000"; +- model = "imx-sgtl5000"; +- mux-ext-port = <3>; +- mux-int-port = <1>; +- ssi-controller = <&ssi1>; +- }; +-}; +- +-&audmux { +- pinctrl-0 = <&pinctrl_audmux_ext>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&can2 { +- status = "disabled"; +-}; +- +-/* 1G ethernet */ +-/delete-node/ ðphy0; +-&fec { +- phy-mode = "rgmii"; +- phy-handle = <ðphy7>; +- pinctrl-0 = <&pinctrl_enet_1G>; +- pinctrl-names = "default"; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy7: ethernet-phy@7 { /* KSZ 9021 */ +- compatible = "ethernet-phy-ieee802.3-c22"; +- interrupt-parent = <&gpio1>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-0 = <&pinctrl_ethphy7>; +- pinctrl-names = "default"; +- reg = <7>; +- reset-assert-us = <1000>; +- reset-deassert-us = <1000>; +- reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; +- rxc-skew-ps = <3000>; +- rxd0-skew-ps = <0>; +- rxd1-skew-ps = <0>; +- rxd2-skew-ps = <0>; +- rxd3-skew-ps = <0>; +- rxdv-skew-ps = <0>; +- txc-skew-ps = <3000>; +- txd0-skew-ps = <0>; +- txd1-skew-ps = <0>; +- txd2-skew-ps = <0>; +- txd3-skew-ps = <0>; +- txen-skew-ps = <0>; +- }; +- }; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c2 { +- sgtl5000: codec@a { +- #sound-dai-cells = <0>; +- clocks = <&clk_ext_audio_codec>; +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <&sw2_reg>; +- }; +- +- touchscreen@38 { +- compatible = "edt,edt-ft5406"; +- interrupt-parent = <&gpio4>; +- interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ +- pinctrl-0 = <&pinctrl_dhcom_e>; +- pinctrl-names = "default"; +- reg = <0x38>; +- }; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&lcd_display_in>; +-}; +- +-&pcie { +- pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>; +- reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; /* GPIO J */ +- status = "okay"; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&usdhc2 { /* SD card */ +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-0 = < +- /* +- * The following DHCOM GPIOs are used on this board. +- * Therefore, they have been removed from the list below. +- * A: key TA1 +- * B: key TA2 +- * C: key TA3 +- * D: key TA4 +- * E: touchscreen +- * F: led6 +- * G: backlight enable +- * H: led7 +- * I: led8 +- * J: PCIe reset +- */ +- &pinctrl_hog_base +- &pinctrl_dhcom_k &pinctrl_dhcom_l +- &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o +- &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r +- &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u +- &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int +- >; +- pinctrl-names = "default"; +- +- pinctrl_audmux_ext: audmux-ext-grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- >; +- }; +- +- pinctrl_enet_1G: enet-1G-grp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 +- >; +- }; +- +- pinctrl_ethphy7: ethphy7-grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__GPIO3_IO26 0xb1 /* WOL */ +- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0xb0 /* Reset */ +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0xb1 /* Int */ +- >; +- }; +- +- pinctrl_ipu1_lcdif: ipu1-lcdif-grp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-dhcom-picoitx.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-dhcom-picoitx.dtsi +deleted file mode 100644 +index 4cd4cb9543c8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-dhcom-picoitx.dtsi ++++ /dev/null +@@ -1,69 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2021 DH electronics GmbH +- */ +- +-#include +- +-/ { +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- led { +- compatible = "gpio-leds"; +- +- led-0 { +- color = ; +- default-state = "off"; +- function = LED_FUNCTION_INDICATOR; +- gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ +- pinctrl-0 = <&pinctrl_dhcom_i>; +- pinctrl-names = "default"; +- }; +- }; +-}; +- +-&gpio1 { +- gpio-line-names = +- "", "", "DHCOM-A", "", "DHCOM-B", "PicoITX-In2", "", "", +- "", "", "", "", "", "", "", "", +- "DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio4 { +- gpio-line-names = +- "", "", "", "", "", "PicoITX-In1", "DHCOM-INT", "DHCOM-H", +- "DHCOM-I", "PicoITX-HW2", "", "", "", "", "", "", +- "", "", "", "", "PicoITX-Out1", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio6 { +- gpio-line-names = +- "", "", "", "PicoITX-Out2", "", "", "SOM-HW1", "", +- "", "", "", "", "", "", "PicoITX-HW0", "PicoITX-HW1", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&iomuxc { +- pinctrl-0 = < +- /* +- * The following DHCOM GPIOs are used on this board. +- * Therefore, they have been removed from the list below. +- * I: yellow led +- */ +- &pinctrl_hog_base +- &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c +- &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f +- &pinctrl_dhcom_g &pinctrl_dhcom_h +- &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l +- &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o +- &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r +- &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u +- &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int +- >; +- pinctrl-names = "default"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-dhcom-som.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-dhcom-som.dtsi +deleted file mode 100644 +index 5d10c40313cb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-dhcom-som.dtsi ++++ /dev/null +@@ -1,815 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2015-2021 DH electronics GmbH +- * Copyright (C) 2018 Marek Vasut +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- aliases { +- i2c0 = &i2c2; +- i2c1 = &i2c1; +- i2c2 = &i2c3; +- mmc0 = &usdhc2; +- mmc1 = &usdhc3; +- mmc2 = &usdhc4; +- mmc3 = &usdhc1; +- rtc0 = &rtc_i2c; +- rtc1 = &snvs_rtc; +- serial0 = &uart1; +- serial1 = &uart5; +- serial2 = &uart4; +- serial3 = &uart2; +- serial4 = &uart3; +- }; +- +- memory@10000000 { /* Appropriate memory size will be filled by U-Boot */ +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +- +- reg_3p3v: regulator-3P3V { +- compatible = "regulator-fixed"; +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "3P3V"; +- }; +- +- reg_eth_vio: regulator-eth-vio { +- compatible = "regulator-fixed"; +- gpio = <&gpio1 7 0>; +- pinctrl-0 = <&pinctrl_enet_vio>; +- pinctrl-names = "default"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "eth_vio"; +- vin-supply = <&sw2_reg>; +- }; +- +- /* OE pin of the latch is low active */ +- reg_latch_oe_on: regulator-latch-oe-on { +- compatible = "regulator-fixed"; +- gpio = <&gpio3 22 0>; +- regulator-always-on; +- regulator-name = "latch_oe_on"; +- }; +- +- reg_usb_h1_vbus: regulator-usb-h1-vbus { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio3 31 0>; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-name = "usb_h1_vbus"; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-name = "usb_otg_vbus"; +- }; +-}; +- +-&can1 { +- pinctrl-0 = <&pinctrl_flexcan1>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-/* +- * Special SoM hardware required which uses the pins from micro SD card. The +- * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 +- * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. So to enable can2 on +- * the board device tree file, the micro SD card must be disabled and the uart1 +- * rts/cts must be disabled or output on other DHCOM pins. +- */ +-&can2 { +- pinctrl-0 = <&pinctrl_flexcan2>; +- pinctrl-names = "default"; +- status = "disabled"; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>; +- pinctrl-0 = <&pinctrl_ecspi1>; +- pinctrl-names = "default"; +- status = "okay"; +- +- flash@0 { /* S25FL116K */ +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- m25p,fast-read; +- reg = <0>; +- spi-max-frequency = <50000000>; +- }; +-}; +- +-&ecspi2 { +- cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; +- pinctrl-0 = <&pinctrl_ecspi2>; +- pinctrl-names = "default"; +- status = "disabled"; +-}; +- +-&fec { +- phy-mode = "rmii"; +- phy-handle = <ðphy0>; +- pinctrl-0 = <&pinctrl_enet_100M>; +- pinctrl-names = "default"; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */ +- compatible = "ethernet-phy-ieee802.3-c22"; +- interrupt-parent = <&gpio4>; +- interrupts = <15 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-0 = <&pinctrl_ethphy0>; +- pinctrl-names = "default"; +- reg = <0>; +- reset-assert-us = <1000>; +- reset-deassert-us = <1000>; +- reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; +- smsc,disable-energy-detect; /* Make plugin detection reliable */ +- }; +- }; +-}; +- +-&gpio1 { +- gpio-line-names = +- "", "", "DHCOM-A", "", "DHCOM-B", "DHCOM-C", "", "", +- "", "", "", "", "", "", "", "", +- "DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio2 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "SOM-HW2", "", "", "SOM-HW0", "", "SOM-MEM1", "SOM-MEM0", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio3 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "DHCOM-G", "", "", "", ""; +-}; +- +-&gpio4 { +- gpio-line-names = +- "", "", "", "", "", "DHCOM-E", "DHCOM-INT", "DHCOM-H", +- "DHCOM-I", "DHCOM-L", "", "", "", "", "", "", +- "", "", "", "", "DHCOM-F", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio5 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "DHCOM-V", "DHCOM-W", "", "DHCOM-O", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio6 { +- gpio-line-names = +- "", "", "", "DHCOM-D", "", "", "SOM-HW1", "", +- "", "", "", "", "", "", "DHCOM-J", "DHCOM-K", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio7 { +- gpio-line-names = +- "DHCOM-M", "DHCOM-N", "", "", "", "", "", "", +- "", "", "", "", "", "DHCOM-P", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&i2c1 { +- /* +- * Info: According to erratum ERR007805 clock frequency limit is 375000. +- * The erratum for i.MX6S/DL is here [1] and for i.MX6Q/D is here [2]. +- * [1] https://www.nxp.com/docs/en/errata/IMX6SDLCE.pdf +- * [2] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf +- */ +- clock-frequency = <100000>; +- pinctrl-0 = <&pinctrl_i2c1>; +- pinctrl-1 = <&pinctrl_i2c1_gpio>; +- pinctrl-names = "default", "gpio"; +- scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +-}; +- +-&i2c2 { +- /* Info: Clock frequency limit is 375000 (for details see i2c1) */ +- clock-frequency = <100000>; +- pinctrl-0 = <&pinctrl_i2c2>; +- pinctrl-1 = <&pinctrl_i2c2_gpio>; +- pinctrl-names = "default", "gpio"; +- scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +-}; +- +-&i2c3 { +- /* Info: Clock frequency limit is 375000 (for details see i2c1) */ +- clock-frequency = <100000>; +- pinctrl-0 = <&pinctrl_i2c3>; +- pinctrl-1 = <&pinctrl_i2c3_gpio>; +- pinctrl-names = "default", "gpio"; +- scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +- +- ltc3676: pmic@3c { +- compatible = "lltc,ltc3676"; +- interrupt-parent = <&gpio5>; +- interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +- pinctrl-0 = <&pinctrl_pmic>; +- pinctrl-names = "default"; +- reg = <0x3c>; +- +- regulators { +- sw1_reg: sw1 { +- lltc,fb-voltage-divider = <100000 110000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-max-microvolt = <1527272>; +- regulator-min-microvolt = <787500>; +- regulator-ramp-delay = <7000>; +- regulator-suspend-mem-microvolt = <1040000>; +- }; +- +- sw2_reg: sw2 { +- lltc,fb-voltage-divider = <100000 28000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-max-microvolt = <3657142>; +- regulator-min-microvolt = <1885714>; +- regulator-ramp-delay = <7000>; +- }; +- +- sw3_reg: sw3 { +- lltc,fb-voltage-divider = <100000 110000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-max-microvolt = <1527272>; +- regulator-min-microvolt = <787500>; +- regulator-ramp-delay = <7000>; +- regulator-suspend-mem-microvolt = <980000>; +- }; +- +- sw4_reg: sw4 { +- lltc,fb-voltage-divider = <100000 93100>; +- regulator-always-on; +- regulator-boot-on; +- regulator-max-microvolt = <1659291>; +- regulator-min-microvolt = <855571>; +- regulator-ramp-delay = <7000>; +- }; +- +- ldo1_reg: ldo1 { +- lltc,fb-voltage-divider = <102000 29400>; +- regulator-always-on; +- regulator-boot-on; +- regulator-max-microvolt = <3240306>; +- regulator-min-microvolt = <3240306>; +- }; +- +- ldo2_reg: ldo2 { +- lltc,fb-voltage-divider = <100000 41200>; +- regulator-always-on; +- regulator-boot-on; +- regulator-max-microvolt = <2484708>; +- regulator-min-microvolt = <2484708>; +- }; +- }; +- }; +- +- touchscreen@49 { /* TSC2004 */ +- compatible = "ti,tsc2004"; +- interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>; +- pinctrl-0 = <&pinctrl_tsc2004>; +- pinctrl-names = "default"; +- reg = <0x49>; +- vio-supply = <®_3p3v>; +- status = "disabled"; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c02"; +- pagesize = <16>; +- reg = <0x50>; +- }; +- +- rtc_i2c: rtc@56 { +- compatible = "microcrystal,rv3029"; +- interrupt-parent = <&gpio7>; +- interrupts = <12 IRQ_TYPE_EDGE_FALLING>; +- pinctrl-0 = <&pinctrl_rtc>; +- pinctrl-names = "default"; +- reg = <0x56>; +- }; +-}; +- +-&pcie { +- pinctrl-0 = <&pinctrl_pcie>; +- pinctrl-names = "default"; +-}; +- +-&pwm1 { +- pinctrl-0 = <&pinctrl_pwm1>; +- pinctrl-names = "default"; +-}; +- +-®_arm { +- vin-supply = <&sw3_reg>; +-}; +- +-®_pu { +- vin-supply = <&sw1_reg>; +-}; +- +-®_soc { +- vin-supply = <&sw1_reg>; +-}; +- +-®_vdd1p1 { +- vin-supply = <&sw2_reg>; +-}; +- +-®_vdd2p5 { +- vin-supply = <&sw2_reg>; +-}; +- +-&uart1 { /* DHCOM UART1 */ +- dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; +- dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; +- dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; +- rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>; +- pinctrl-0 = <&pinctrl_uart1>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart4 { /* DHCOM UART3 */ +- pinctrl-0 = <&pinctrl_uart4>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&uart5 { /* DHCOM UART2 */ +- pinctrl-0 = <&pinctrl_uart5>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbh1 { +- dr_mode = "host"; +- pinctrl-0 = <&pinctrl_usbh1>; +- pinctrl-names = "default"; +- vbus-supply = <®_usb_h1_vbus>; +- status = "okay"; +-}; +- +-&usbotg { +- disable-over-current; +- dr_mode = "otg"; +- pinctrl-0 = <&pinctrl_usbotg>; +- pinctrl-names = "default"; +- vbus-supply = <®_usb_otg_vbus>; +- status = "okay"; +-}; +- +-&usdhc2 { /* External SD card via DHCOM */ +- cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; +- keep-power-in-suspend; +- pinctrl-0 = <&pinctrl_usdhc2>; +- pinctrl-names = "default"; +- status = "disabled"; +-}; +- +-&usdhc3 { /* Micro SD card on module */ +- cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; +- fsl,wp-controller; +- keep-power-in-suspend; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&usdhc4 { /* eMMC on module */ +- bus-width = <8>; +- keep-power-in-suspend; +- no-1-8-v; +- non-removable; +- pinctrl-0 = <&pinctrl_usdhc4>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&weim { +- #address-cells = <2>; +- #size-cells = <1>; +- fsl,weim-cs-gpr = <&gpr>; +- pinctrl-0 = <&pinctrl_weim &pinctrl_weim_cs0 &pinctrl_weim_cs1>; +- pinctrl-names = "default"; +- /* It is necessary to setup 2x 64MB otherwise setting gpr fails */ +- ranges = <0 0 0x08000000 0x04000000>, /* CS0 */ +- <1 0 0x0c000000 0x04000000>; /* CS1 */ +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl-0 = < +- &pinctrl_hog_base +- &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c +- &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f +- &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i +- &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l +- &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o +- &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r +- &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u +- &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int +- >; +- pinctrl-names = "default"; +- +- pinctrl_hog_base: hog-base-grp { +- fsl,pins = < +- /* GPIOs for memory coding */ +- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x120b0 +- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x120b0 +- /* GPIOs for hardware coding */ +- MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x120b0 +- MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x120b0 +- MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x120b0 +- >; +- }; +- +- /* DHCOM GPIOs */ +- pinctrl_dhcom_a: dhcom-a-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_b: dhcom-b-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_c: dhcom-c-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_d: dhcom-d-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_e: dhcom-e-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_f: dhcom-f-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_g: dhcom-g-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_h: dhcom-h-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_i: dhcom-i-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_j: dhcom-j-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_k: dhcom-k-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_l: dhcom-l-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_m: dhcom-m-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_n: dhcom-n-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_o: dhcom-o-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_p: dhcom-p-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_q: dhcom-q-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_r: dhcom-r-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_s: dhcom-s-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_t: dhcom-t-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_u: dhcom-u-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_v: dhcom-v-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_w: dhcom-w-grp { +- fsl,pins = ; +- }; +- +- pinctrl_dhcom_int: dhcom-int-grp { +- fsl,pins = ; +- }; +- +- pinctrl_ecspi1: ecspi1-grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +- MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2-grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 +- MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 +- MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 +- MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 +- >; +- }; +- +- pinctrl_enet_100M: enet-100M-grp { +- fsl,pins = < +- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 +- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 +- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- >; +- }; +- +- pinctrl_enet_vio: enet-vio-grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0 +- >; +- }; +- +- pinctrl_ethphy0: ethphy0-grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0xb0 /* Reset */ +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0xb1 /* Int */ +- >; +- }; +- +- pinctrl_flexcan1: flexcan1-grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2-grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 +- MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1-grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c1_gpio: i2c1-gpio-grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2-grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2_gpio: i2c2-gpio-grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3-grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3_gpio: i2c3-gpio-grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 +- >; +- }; +- +- pinctrl_pcie: pcie-grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* Wake */ +- >; +- }; +- +- pinctrl_pmic: pmic-grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1-grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_rtc: rtc-grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x120b0 +- >; +- }; +- +- pinctrl_tsc2004: tsc2004-grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x120b0 +- >; +- }; +- +- pinctrl_uart1: uart1-grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x4001b0b1 +- MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x4001b0b1 +- MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x4001b0b1 +- MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x4001b0b1 +- MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x4001b0b1 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4-grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5-grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x4001b0b1 +- >; +- }; +- +- pinctrl_usbh1: usbh1-grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120b0 +- >; +- }; +- +- pinctrl_usbotg: usbotg-grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2-grp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x120b0 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3-grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x120b0 +- >; +- }; +- +- pinctrl_usdhc4: usdhc4-grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 +- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 +- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 +- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +- >; +- }; +- +- pinctrl_weim: weim-grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0a6 +- MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0a6 +- MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0a6 +- MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0a6 +- MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0a6 +- MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0a6 +- MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0a6 +- MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0a6 +- MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0a6 +- MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0a6 +- MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0a6 +- MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0a6 +- MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0a6 +- MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0a6 +- MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0a6 +- MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0a6 +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 +- MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb060 /* LE */ +- MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0a6 +- MX6QDL_PAD_EIM_RW__EIM_RW 0xb0a6 /* WE */ +- >; +- }; +- +- pinctrl_weim_cs0: weim-cs0-grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 +- >; +- }; +- +- pinctrl_weim_cs1: weim-cs1-grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-ds.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-ds.dtsi +deleted file mode 100644 +index f7e517555697..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-ds.dtsi ++++ /dev/null +@@ -1,458 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2021 Dillon Min +-// +-// Based on imx6qdl-sabresd.dtsi which is: +-// Copyright 2012 Freescale Semiconductor, Inc. +-// Copyright 2011 Linaro Ltd. +- +-#include +-#include +-#include +- +-/ { +- chosen { +- stdout-path = &uart4; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usb_h1_vbus: regulator-usb-h1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led-0 { +- gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-&ipu1_csi0_from_ipu1_csi0_mux { +- bus-width = <8>; +- data-shift = <12>; /* Lines 19:12 used */ +- hsync-active = <1>; +- vsync-active = <1>; +-}; +- +-&ipu1_csi0_mux_from_parallel_sensor { +- remote-endpoint = <&ov2659_to_ipu1_csi0_mux>; +-}; +- +-&ipu1_csi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_csi0>; +- status = "okay"; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_gpio>; +- status = "okay"; +- +- m25p80: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p80", "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-handle = <&phy>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy: ethernet-phy@1 { +- reg = <1>; +- qca,clk-out-frequency = <125000000>; +- reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- }; +- }; +-}; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hdmi_cec>; +- ddc-i2c-bus = <&i2c3>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- pfuze100: pmic@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- ov2659: camera@30 { +- compatible = "ovti,ov2659"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ov2659>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- clock-names = "xvclk"; +- reg = <0x30>; +- powerdown-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- port { +- ov2659_to_ipu1_csi0_mux: endpoint { +- remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; +- link-frequencies = /bits/ 64 <70000000>; +- bus-width = <8>; +- hsync-active = <1>; +- vsync-active = <1>; +- }; +- }; +- }; +-}; +- +-&iomuxc { +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- >; +- }; +- +- pinctrl_ecspi1_gpio: ecspi1grpgpiogrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 +- MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 +- >; +- }; +- +- pinctrl_hdmi_cec: hdmicecgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_ipu1_csi0: ipu1csi0grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 +- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 +- MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 +- MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 +- >; +- }; +- +- pinctrl_ov2659: ov2659grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 +- MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc1_gpio: usdhc1grpgpiogrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 +- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 +- >; +- }; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; +- bus-width = <4>; +- cd-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; +- bus-width = <4>; +- cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; +- status = "disabled"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <8>; +- non-removable; +- no-1-8-v; +- status = "okay"; +-}; +- +-&wdog1 { +- status = "disabled"; +-}; +- +-&wdog2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-emcon-avari.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-emcon-avari.dtsi +deleted file mode 100644 +index c4e146f3341b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-emcon-avari.dtsi ++++ /dev/null +@@ -1,177 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 or MIT) +-// +-// Copyright (C) 2018 emtrion GmbH +-// +- +-/ { +- aliases { +- boardid = &boardid; +- mmc0 = &usdhc3; +- mmc1 = &usdhc2; +- mmc2 = &usdhc1; +- mmc3 = &usdhc4; +- }; +- +- reg_wall_5p0: reg-wall5p0 { +- compatible = "regulator-fixed"; +- regulator-name = "Main-Supply"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_base3p3: reg-base3p3 { +- compatible = "regulator-fixed"; +- vin-supply = <®_wall_5p0>; +- regulator-name = "3V3-avari"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_base1p5: reg-base1p5 { +- compatible = "regulator-fixed"; +- vin-supply = <®_base3p3>; +- regulator-name = "1V5-avari"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_usb_otg: reg-otgvbus { +- compatible = "regulator-fixed"; +- vin-supply = <®_wall_5p0>; +- regulator-name = "OTG_VBUS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; +- regulator-always-on; +- }; +- +- clk_codec: clock-codec { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <12000000>; +- }; +- +- sound { +- compatible = "fsl,imx-audio-sgtl5000"; +- model = "emCON-avari-sgtl5000"; +- ssi-controller = <&ssi2>; +- audio-codec = <&sgtl5000>; +- audio-routing = +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <2>; +- mux-ext-port = <3>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&can2 { +- status = "okay"; +-}; +- +-&ecspi2 { +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- sgtl5000: audio-codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- clocks = <&clk_codec>; +- VDDA-supply = <®_base3p3>; +- VDDIO-supply = <®_base3p3>; +- }; +- +- captouch: touchscreen@38 { +- compatible = "edt,edt-ft5406"; +- reg = <0x38>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>; +- interrupt-parent = <&gpio6>; +- interrupts = <31 IRQ_TYPE_EDGE_FALLING>; +- wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; +- wakeup-source; +- }; +- +- boardid: gpio@3a { +- compatible = "nxp,pca8574"; +- reg = <0x3a>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&rgb_encoder { +- status = "okay"; +-}; +- +-&rgb_panel { +- compatible = "edt,etm0700g0bdh6"; +- status = "okay"; +-}; +- +-&ssi2 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +- uart-has-rtscts; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&uart4 { +- status = "okay"; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbotg { +- status = "okay"; +-}; +- +-&usdhc1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-emcon.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-emcon.dtsi +deleted file mode 100644 +index 7228b894a763..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-emcon.dtsi ++++ /dev/null +@@ -1,834 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 or MIT) +-// +-// Copyright (C) 2018 emtrion GmbH +-// +- +-#include +-#include +-#include +- +-/ { +- +- model = "emtrion SoM emCON-MX6"; +- compatible = "emtrion,emcon-mx6"; +- +- aliases { +- mmc0 = &usdhc3; +- mmc1 = &usdhc2; +- mmc2 = &usdhc1; +- rtc0 = &ds1307; +- }; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_emcon_wake>; +- +- wake { +- label = "Wake"; +- linux,code = ; +- gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; +- wakeup-source; +- }; +- }; +- +- som_leds: leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_som_leds>; +- +- green { +- label = "som:green"; +- gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "on"; +- }; +- +- red { +- label = "som:red"; +- gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- +- }; +- +- lvds_backlight: lvds-backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lvds_bl>; +- enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; +- pwms = <&pwm1 0 50000>; +- brightness-levels = < +- 0 4 8 16 32 64 80 96 112 +- 128 144 160 176 250 +- >; +- default-brightness-level = <13>; +- status = "okay"; +- }; +- +- pwm_fan: pwm-fan { +- compatible = "pwm-fan"; +- #cooling-cells = <2>; +- pwms = <&pwm4 0 50000>; +- cooling-levels = <0 64 127 191 255>; +- status = "disabled"; +- }; +- +- +- rgb_encoder: display { +- compatible = "fsl,imx-parallel-display"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgb24_display>; +- status = "disabled"; +- +- port@0 { +- reg = <0>; +- +- rgb_encoder_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- rgb_encoder_out: endpoint { +- remote-endpoint = <&rgb_panel_in>; +- }; +- }; +- }; +- +- rgb_panel: lcd { +- backlight = <&rgb_backlight>; +- power-supply = <®_parallel_disp>; +- +- port { +- rgb_panel_in: endpoint { +- remote-endpoint = <&rgb_encoder_out>; +- }; +- }; +- }; +- +- reg_parallel_disp: reg-parallel-display { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgb_bl_en>; +- regulator-name = "LCD-Supply"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_lvds_disp: reg-lvds-display { +- compatible = "regulator-fixed"; +- regulator-name = "LVDS-Supply"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- rgb_backlight: rgb-backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgb_bl>; +- enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; +- pwms = <&pwm3 0 5000000>; +- brightness-levels = < +- 250 176 160 144 128 112 +- 96 80 64 48 32 16 8 1 +- >; +- default-brightness-level = <13>; +- status = "okay"; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can2>; +-}; +- +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, +- <&gpio2 27 GPIO_ACTIVE_LOW>; +-}; +- +-&ecspi4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nor_flash>; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii"; +- phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <50>; +- phy-supply = <&vdd_1V8_reg>; +- phy-handle = <&ksz9031>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ksz9031: phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- interrupt-parent = <&gpio1>; +- interrupts = <30 IRQ_TYPE_EDGE_FALLING>; +- rxdv-skew-ps = <480>; +- txen-skew-ps = <480>; +- rxd0-skew-ps = <480>; +- rxd1-skew-ps = <480>; +- rxd2-skew-ps = <480>; +- rxd3-skew-ps = <480>; +- txd0-skew-ps = <420>; +- txd1-skew-ps = <420>; +- txd2-skew-ps = <360>; +- txd3-skew-ps = <360>; +- txc-skew-ps = <1020>; +- rxc-skew-ps = <960>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- da9063: pmic@58 { +- compatible = "dlg,da9063"; +- reg = <0x58>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio2>; +- interrupts = <8 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- +- onkey { +- compatible = "dlg,da9063-onkey"; +- wakeup-source; +- }; +- +- watchdog { +- compatible = "dlg,da9063-watchdog"; +- timeout-sec = <0>; +- }; +- +- regulators { +- vddcore_reg: bcore1 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1450000>; +- regulator-ramp-delay = <2>; +- regulator-name = "DA9063_CORE"; +- regulator-always-on; +- }; +- +- vddsoc_reg: bcore2 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1450000>; +- regulator-ramp-delay = <2>; +- regulator-name = "DA9063_SOC"; +- regulator-always-on; +- }; +- +- vdd_ddr3_reg: bpro { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <2>; +- regulator-always-on; +- }; +- +- vdd_3v3_reg: bperi { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-ramp-delay = <2>; +- regulator-always-on; +- }; +- +- vdd_sata_reg: ldo3 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- vdd_mipi_reg: ldo4 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- vdd_mx6_snvs_reg: ldo5 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_hdmi_reg: ldo6 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_pcie_reg: ldo7 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- vdd_1V8_reg: ldo8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vdd_3V3_sdc_reg: ldo9 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_1V2_reg: ldo10 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- }; +- }; +- +- ds1307: rtc@68 { +- compatible = "dallas,ds1307"; +- reg = <0x68>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +-}; +- +-&iomuxc { +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060 +- >; +- }; +- +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_can2: can2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_cpi1: csi0grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 +- MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1 +- MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1 +- >; +- }; +- +- /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/ +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 +- MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 +- MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 +- MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 +- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 +- >; +- }; +- +- pinctrl_emcon_gpio1: emcongpio1 { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1 +- >; +- }; +- +- pinctrl_emcon_gpio2: emcongpio2 { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1 +- >; +- }; +- +- pinctrl_emcon_gpio3: emcongpio3 { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1 +- >; +- }; +- +- pinctrl_emcon_gpio4: emcongpio4 { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1 +- >; +- }; +- +- pinctrl_emcon_gpio5: emcongpio5 { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1 +- >; +- }; +- +- pinctrl_emcon_gpio6: emcongpio6 { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1 +- >; +- }; +- +- pinctrl_emcon_gpio7: emcongpio7 { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1 +- >; +- }; +- +- pinctrl_emcon_gpio8: emcongpio8 { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1 +- >; +- }; +- +- pinctrl_emcon_irq_a: emconirqa { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1 +- >; +- }; +- +- pinctrl_emcon_irq_b: emconirqb { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1 +- >; +- }; +- +- pinctrl_emcon_irq_c: emconirqc { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1 +- >; +- }; +- +- pinctrl_emcon_irq_pwr: emconirqpwr { +- fsl,pins = < +- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1 +- >; +- }; +- +- pinctrl_emcon_wake: emconwake { +- fsl,pins = < +- MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058 +- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870 +- >; +- }; +- +- pinctrl_irq_touch1: irqtouch1 { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1 +- >; +- }; +- +- pinctrl_irq_touch2: irqtouch2 { +- fsl,pins = < +- MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1 +- >; +- }; +- +- pinctrl_lvds_bl: lvdsbacklightgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1 +- MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1 +- >; +- }; +- +- pinctrl_lvds_reg: lvdsreggrp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1 +- >; +- }; +- +- +- pinctrl_nor_flash: norflashgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1 +- MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 +- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 +- >; +- }; +- +- pinctrl_pcie_ctrl: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1 +- >; +- }; +- +- pinctrl_pwm_fan: pwmfan { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1 +- >; +- }; +- +- pinctrl_rgb_bl: rgbbacklightgrp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1 +- MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1 +- >; +- }; +- +- pinctrl_rgb_bl_en: rgbenable { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1 +- >; +- }; +- +- pinctrl_rgb24_display: rgbgrp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 +- >; +- }; +- +- pinctrl_secure: securegrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 +- >; +- }; +- +- pinctrl_som_leds: somledgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1 +- MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1 +- >; +- }; +- +- pinctrl_spdif_in: spdifin { +- fsl,pins = < +- MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 +- >; +- }; +- +- pinctrl_spdif_out: spdifout { +- fsl,pins = < +- MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 +- MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usb_host1: usbhgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058 +- MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058 +- >; +- }; +- +- pinctrl_usb_otg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +- MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059 +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 +- MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1 +- MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1 +- MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 +- >; +- }; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&rgb_encoder_in>; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie_ctrl>; +- reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; +- disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- status = "okay"; +-}; +- +-&pwm3 { +- #pwm-cells = <2>; +- status = "okay"; +-}; +- +-&pwm4 { +- #pwm-cells = <2>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +-}; +- +-&usbh1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_host1>; +-}; +- +-&usbotg { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_otg>; +- vbus-supply = <®_usb_otg>; +- dr_mode = "peripheral"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- fsl,wp-controller; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- fsl,wp-controller; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- non-removable; +- bus-width = <8>; +- status = "okay"; +-}; +- +-/******device power Management*********/ +- +-&cpu0 { +- voltage-tolerance = <2>; +-}; +- +-®_arm { +- vin-supply = <&vddcore_reg>; +-}; +- +-®_soc { +- vin-supply = <&vddsoc_reg>; +-}; +- +-®_pu { +- vin-supply = <&vddsoc_reg>; +-}; +- +-/*******Disabled HW following***********/ +- +-&snvs_rtc { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-gw51xx.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-gw51xx.dtsi +deleted file mode 100644 +index 069c27fab432..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-gw51xx.dtsi ++++ /dev/null +@@ -1,638 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Gateworks Corporation +- */ +- +-#include +-#include +-#include +- +-/ { +- /* these are used by bootloader for disabling nodes */ +- aliases { +- led0 = &led0; +- led1 = &led1; +- nand = &gpmi; +- usb0 = &usbh1; +- usb1 = &usbotg; +- }; +- +- chosen { +- bootargs = "console=ttymxc1,115200"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-pb { +- label = "user_pb"; +- gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- user-pb1x { +- label = "user_pb1x"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <0>; +- }; +- +- key-erased { +- label = "key-erased"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <1>; +- }; +- +- eeprom-wp { +- label = "eeprom_wp"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <2>; +- }; +- +- tamper { +- label = "tamper"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <5>; +- }; +- +- switch-hold { +- label = "switch_hold"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <7>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led0: user1 { +- label = "user1"; +- gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led1: user2 { +- label = "user2"; +- gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ +- default-state = "off"; +- }; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +- +- pps { +- compatible = "pps-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pps>; +- gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_5p0v: regulator-5p0v { +- compatible = "regulator-fixed"; +- regulator-name = "5P0V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- gsc: gsc@20 { +- compatible = "gw,gsc"; +- reg = <0x20>; +- interrupt-parent = <&gpio1>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <1>; +- #size-cells = <0>; +- +- adc { +- compatible = "gw,gsc-adc"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@0 { +- gw,mode = <0>; +- reg = <0x00>; +- label = "temp"; +- }; +- +- channel@2 { +- gw,mode = <1>; +- reg = <0x02>; +- label = "vdd_vin"; +- }; +- +- channel@5 { +- gw,mode = <1>; +- reg = <0x05>; +- label = "vdd_3p3"; +- }; +- +- channel@8 { +- gw,mode = <1>; +- reg = <0x08>; +- label = "vdd_bat"; +- }; +- +- channel@b { +- gw,mode = <1>; +- reg = <0x0b>; +- label = "vdd_5p0"; +- }; +- +- channel@e { +- gw,mode = <1>; +- reg = <0xe>; +- label = "vdd_arm"; +- }; +- +- channel@11 { +- gw,mode = <1>; +- reg = <0x11>; +- label = "vdd_soc"; +- }; +- +- channel@14 { +- gw,mode = <1>; +- reg = <0x14>; +- label = "vdd_3p0"; +- }; +- +- channel@17 { +- gw,mode = <1>; +- reg = <0x17>; +- label = "vdd_1p5"; +- }; +- +- channel@1d { +- gw,mode = <1>; +- reg = <0x1d>; +- label = "vdd_1p8"; +- }; +- +- channel@20 { +- gw,mode = <1>; +- reg = <0x20>; +- label = "vdd_an1"; +- }; +- +- channel@23 { +- gw,mode = <1>; +- reg = <0x23>; +- label = "vdd_2p5"; +- }; +- }; +- }; +- +- gsc_gpio: gpio@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gsc>; +- interrupts = <4>; +- }; +- +- eeprom1: eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom2: eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- eeprom3: eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- eeprom4: eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +- +- rtc: ds1672@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- ltc3676: pmic@3c { +- compatible = "lltc,ltc3676"; +- reg = <0x3c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio1>; +- interrupts = <8 IRQ_TYPE_EDGE_FALLING>; +- +- regulators { +- /* VDD_SOC (1+R1/R2 = 1.635) */ +- reg_vdd_soc: sw1 { +- regulator-name = "vddsoc"; +- regulator-min-microvolt = <674400>; +- regulator-max-microvolt = <1308000>; +- lltc,fb-voltage-divider = <127000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ +- reg_1p8v: sw2 { +- regulator-name = "vdd1p8"; +- regulator-min-microvolt = <1033310>; +- regulator-max-microvolt = <2004000>; +- lltc,fb-voltage-divider = <301000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_ARM (1+R1/R2 = 1.635) */ +- reg_vdd_arm: sw3 { +- regulator-name = "vddarm"; +- regulator-min-microvolt = <674400>; +- regulator-max-microvolt = <1308000>; +- lltc,fb-voltage-divider = <127000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_DDR (1+R1/R2 = 2.105) */ +- reg_vdd_ddr: sw4 { +- regulator-name = "vddddr"; +- regulator-min-microvolt = <868310>; +- regulator-max-microvolt = <1684000>; +- lltc,fb-voltage-divider = <221000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ +- reg_2p5v: ldo2 { +- regulator-name = "vdd2p5"; +- regulator-min-microvolt = <2490375>; +- regulator-max-microvolt = <2490375>; +- lltc,fb-voltage-divider = <487000 200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_HIGH (1+R1/R2 = 4.17) */ +- reg_3p0v: ldo4 { +- regulator-name = "vdd3p0"; +- regulator-min-microvolt = <3023250>; +- regulator-max-microvolt = <3023250>; +- lltc,fb-voltage-divider = <634000 200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- adv7180: camera@20 { +- compatible = "adi,adv7180"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adv7180>; +- reg = <0x20>; +- powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; +- interrupt-parent = <&gpio5>; +- interrupts = <23 IRQ_TYPE_LEVEL_LOW>; +- +- port { +- adv7180_to_ipu1_csi0_mux: endpoint { +- remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; +- bus-width = <8>; +- }; +- }; +- }; +-}; +- +-&ipu1_csi0_from_ipu1_csi0_mux { +- bus-width = <8>; +-}; +- +-&ipu1_csi0_mux_from_parallel_sensor { +- remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; +- bus-width = <8>; +-}; +- +-&ipu1_csi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_csi0>; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ +- status = "disabled"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ +- status = "disabled"; +-}; +- +-&pwm4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ +- status = "disabled"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl_adv7180: adv7180grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 +- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 +- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_ipu1_csi0: ipu1csi0grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 +- MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 +- MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 +- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ +- >; +- }; +- +- pinctrl_pps: ppsgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ +- MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-gw52xx.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-gw52xx.dtsi +deleted file mode 100644 +index b1df2beb2832..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-gw52xx.dtsi ++++ /dev/null +@@ -1,779 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Gateworks Corporation +- */ +- +-#include +-#include +-#include +- +-/ { +- /* these are used by bootloader for disabling nodes */ +- aliases { +- led0 = &led0; +- led1 = &led1; +- led2 = &led2; +- nand = &gpmi; +- ssi0 = &ssi1; +- usb0 = &usbh1; +- usb1 = &usbotg; +- }; +- +- chosen { +- bootargs = "console=ttymxc1,115200"; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm4 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-pb { +- label = "user_pb"; +- gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- user-pb1x { +- label = "user_pb1x"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <0>; +- }; +- +- key-erased { +- label = "key-erased"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <1>; +- }; +- +- eeprom-wp { +- label = "eeprom_wp"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <2>; +- }; +- +- tamper { +- label = "tamper"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <5>; +- }; +- +- switch-hold { +- label = "switch_hold"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <7>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led0: user1 { +- label = "user1"; +- gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led1: user2 { +- label = "user2"; +- gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ +- default-state = "off"; +- }; +- +- led2: user3 { +- label = "user3"; +- gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ +- default-state = "off"; +- }; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +- +- pps { +- compatible = "pps-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pps>; +- gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- reg_1p0v: regulator-1p0v { +- compatible = "regulator-fixed"; +- regulator-name = "1P0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_5p0v: regulator-5p0v { +- compatible = "regulator-fixed"; +- regulator-name = "5P0V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sound { +- compatible = "fsl,imx6q-ventana-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "sgtl5000-audio"; +- ssi-controller = <&ssi1>; +- audio-codec = <&codec>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <4>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, +- <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +-}; +- +-&ecspi3 { +- cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi3>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- gsc: gsc@20 { +- compatible = "gw,gsc"; +- reg = <0x20>; +- interrupt-parent = <&gpio1>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <1>; +- #size-cells = <0>; +- +- adc { +- compatible = "gw,gsc-adc"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@0 { +- gw,mode = <0>; +- reg = <0x00>; +- label = "temp"; +- }; +- +- channel@2 { +- gw,mode = <1>; +- reg = <0x02>; +- label = "vdd_vin"; +- }; +- +- channel@5 { +- gw,mode = <1>; +- reg = <0x05>; +- label = "vdd_3p3"; +- }; +- +- channel@8 { +- gw,mode = <1>; +- reg = <0x08>; +- label = "vdd_bat"; +- }; +- +- channel@b { +- gw,mode = <1>; +- reg = <0x0b>; +- label = "vdd_5p0"; +- }; +- +- channel@e { +- gw,mode = <1>; +- reg = <0xe>; +- label = "vdd_arm"; +- }; +- +- channel@11 { +- gw,mode = <1>; +- reg = <0x11>; +- label = "vdd_soc"; +- }; +- +- channel@14 { +- gw,mode = <1>; +- reg = <0x14>; +- label = "vdd_3p0"; +- }; +- +- channel@17 { +- gw,mode = <1>; +- reg = <0x17>; +- label = "vdd_1p5"; +- }; +- +- channel@1d { +- gw,mode = <1>; +- reg = <0x1d>; +- label = "vdd_1p8"; +- }; +- +- channel@20 { +- gw,mode = <1>; +- reg = <0x20>; +- label = "vdd_1p0"; +- }; +- +- channel@23 { +- gw,mode = <1>; +- reg = <0x23>; +- label = "vdd_2p5"; +- }; +- +- channel@29 { +- gw,mode = <1>; +- reg = <0x29>; +- label = "vdd_an1"; +- }; +- }; +- }; +- +- gsc_gpio: gpio@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gsc>; +- interrupts = <4>; +- }; +- +- eeprom1: eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom2: eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- eeprom3: eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- eeprom4: eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +- +- rtc: ds1672@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- ltc3676: pmic@3c { +- compatible = "lltc,ltc3676"; +- reg = <0x3c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio1>; +- interrupts = <8 IRQ_TYPE_EDGE_FALLING>; +- +- regulators { +- /* VDD_SOC (1+R1/R2 = 1.635) */ +- reg_vdd_soc: sw1 { +- regulator-name = "vddsoc"; +- regulator-min-microvolt = <674400>; +- regulator-max-microvolt = <1308000>; +- lltc,fb-voltage-divider = <127000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ +- reg_1p8v: sw2 { +- regulator-name = "vdd1p8"; +- regulator-min-microvolt = <1033310>; +- regulator-max-microvolt = <2004000>; +- lltc,fb-voltage-divider = <301000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_ARM (1+R1/R2 = 1.635) */ +- reg_vdd_arm: sw3 { +- regulator-name = "vddarm"; +- regulator-min-microvolt = <674400>; +- regulator-max-microvolt = <1308000>; +- lltc,fb-voltage-divider = <127000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_DDR (1+R1/R2 = 2.105) */ +- reg_vdd_ddr: sw4 { +- regulator-name = "vddddr"; +- regulator-min-microvolt = <868310>; +- regulator-max-microvolt = <1684000>; +- lltc,fb-voltage-divider = <221000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ +- reg_2p5v: ldo2 { +- regulator-name = "vdd2p5"; +- regulator-min-microvolt = <2490375>; +- regulator-max-microvolt = <2490375>; +- lltc,fb-voltage-divider = <487000 200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_AUD_1P8: Audio codec */ +- reg_aud_1p8v: ldo3 { +- regulator-name = "vdd1p8a"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- }; +- +- /* VDD_HIGH (1+R1/R2 = 4.17) */ +- reg_3p0v: ldo4 { +- regulator-name = "vdd3p0"; +- regulator-min-microvolt = <3023250>; +- regulator-max-microvolt = <3023250>; +- lltc,fb-voltage-divider = <634000 200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- codec: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_1p8v>; +- VDDIO-supply = <®_3p3v>; +- }; +- +- touchscreen: egalax_ts@4 { +- compatible = "eeti,egalax_ts"; +- reg = <0x04>; +- interrupt-parent = <&gpio7>; +- interrupts = <12 2>; +- wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; +- }; +- +- accel@1e { +- compatible = "nxp,fxos8700"; +- reg = <0x1e>; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <18>; +- status = "okay"; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: hsd100pxn1 { +- clock-frequency = <65000000>; +- hactive = <1024>; +- vactive = <768>; +- hback-porch = <220>; +- hfront-porch = <40>; +- vback-porch = <21>; +- vfront-porch = <7>; +- hsync-len = <60>; +- vsync-len = <10>; +- }; +- }; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ +- status = "disabled"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ +- status = "disabled"; +-}; +- +-&pwm4 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- no-1-8-v; /* firmware will remove if board revision supports */ +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 +- MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 +- MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 +- MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ +- >; +- }; +- +- pinctrl_ecspi3: escpi3grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 +- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 +- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 +- MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 +- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */ +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ +- >; +- }; +- +- pinctrl_pps: ppsgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ +- MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp100mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp200mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-gw53xx.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-gw53xx.dtsi +deleted file mode 100644 +index a0710d562766..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-gw53xx.dtsi ++++ /dev/null +@@ -1,768 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Gateworks Corporation +- */ +- +-#include +-#include +-#include +- +-/ { +- /* these are used by bootloader for disabling nodes */ +- aliases { +- led0 = &led0; +- led1 = &led1; +- led2 = &led2; +- nand = &gpmi; +- ssi0 = &ssi1; +- usb0 = &usbh1; +- usb1 = &usbotg; +- }; +- +- chosen { +- bootargs = "console=ttymxc1,115200"; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm4 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-pb { +- label = "user_pb"; +- gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- user-pb1x { +- label = "user_pb1x"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <0>; +- }; +- +- key-erased { +- label = "key-erased"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <1>; +- }; +- +- eeprom-wp { +- label = "eeprom_wp"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <2>; +- }; +- +- tamper { +- label = "tamper"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <5>; +- }; +- +- switch-hold { +- label = "switch_hold"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <7>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led0: user1 { +- label = "user1"; +- gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led1: user2 { +- label = "user2"; +- gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ +- default-state = "off"; +- }; +- +- led2: user3 { +- label = "user3"; +- gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ +- default-state = "off"; +- }; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- pps { +- compatible = "pps-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pps>; +- gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- reg_1p0v: regulator-1p0v { +- compatible = "regulator-fixed"; +- regulator-name = "1P0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_h1_vbus: regulator-usb-h1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sound { +- compatible = "fsl,imx6q-ventana-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "sgtl5000-audio"; +- ssi-controller = <&ssi1>; +- audio-codec = <&codec>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <4>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, +- <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- gsc: gsc@20 { +- compatible = "gw,gsc"; +- reg = <0x20>; +- interrupt-parent = <&gpio1>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <1>; +- #size-cells = <0>; +- +- adc { +- compatible = "gw,gsc-adc"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@0 { +- gw,mode = <0>; +- reg = <0x00>; +- label = "temp"; +- }; +- +- channel@2 { +- gw,mode = <1>; +- reg = <0x02>; +- label = "vdd_vin"; +- }; +- +- channel@5 { +- gw,mode = <1>; +- reg = <0x05>; +- label = "vdd_3p3"; +- }; +- +- channel@8 { +- gw,mode = <1>; +- reg = <0x08>; +- label = "vdd_bat"; +- }; +- +- channel@b { +- gw,mode = <1>; +- reg = <0x0b>; +- label = "vdd_5p0"; +- }; +- +- channel@e { +- gw,mode = <1>; +- reg = <0xe>; +- label = "vdd_arm"; +- }; +- +- channel@11 { +- gw,mode = <1>; +- reg = <0x11>; +- label = "vdd_soc"; +- }; +- +- channel@14 { +- gw,mode = <1>; +- reg = <0x14>; +- label = "vdd_3p0"; +- }; +- +- channel@17 { +- gw,mode = <1>; +- reg = <0x17>; +- label = "vdd_1p5"; +- }; +- +- channel@1d { +- gw,mode = <1>; +- reg = <0x1d>; +- label = "vdd_1p8"; +- }; +- +- channel@20 { +- gw,mode = <1>; +- reg = <0x20>; +- label = "vdd_1p0"; +- }; +- +- channel@23 { +- gw,mode = <1>; +- reg = <0x23>; +- label = "vdd_2p5"; +- }; +- +- channel@26 { +- gw,mode = <1>; +- reg = <0x26>; +- label = "vdd_gps"; +- }; +- +- channel@29 { +- gw,mode = <1>; +- reg = <0x29>; +- label = "vdd_an1"; +- }; +- }; +- }; +- +- gsc_gpio: gpio@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gsc>; +- interrupts = <4>; +- }; +- +- eeprom1: eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom2: eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- eeprom3: eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- eeprom4: eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +- +- rtc: ds1672@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- ltc3676: pmic@3c { +- compatible = "lltc,ltc3676"; +- reg = <0x3c>; +- interrupt-parent = <&gpio1>; +- interrupts = <8 IRQ_TYPE_EDGE_FALLING>; +- +- regulators { +- /* VDD_SOC (1+R1/R2 = 1.635) */ +- reg_vdd_soc: sw1 { +- regulator-name = "vddsoc"; +- regulator-min-microvolt = <674400>; +- regulator-max-microvolt = <1308000>; +- lltc,fb-voltage-divider = <127000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ +- reg_1p8v: sw2 { +- regulator-name = "vdd1p8"; +- regulator-min-microvolt = <1033310>; +- regulator-max-microvolt = <2004000>; +- lltc,fb-voltage-divider = <301000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_ARM (1+R1/R2 = 1.635) */ +- reg_vdd_arm: sw3 { +- regulator-name = "vddarm"; +- regulator-min-microvolt = <674400>; +- regulator-max-microvolt = <1308000>; +- lltc,fb-voltage-divider = <127000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_DDR (1+R1/R2 = 2.105) */ +- reg_vdd_ddr: sw4 { +- regulator-name = "vddddr"; +- regulator-min-microvolt = <868310>; +- regulator-max-microvolt = <1684000>; +- lltc,fb-voltage-divider = <221000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ +- reg_2p5v: ldo2 { +- regulator-name = "vdd2p5"; +- regulator-min-microvolt = <2490375>; +- regulator-max-microvolt = <2490375>; +- lltc,fb-voltage-divider = <487000 200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_AUD_1P8: Audio codec */ +- reg_aud_1p8v: ldo3 { +- regulator-name = "vdd1p8a"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- }; +- +- /* VDD_HIGH (1+R1/R2 = 4.17) */ +- reg_3p0v: ldo4 { +- regulator-name = "vdd3p0"; +- regulator-min-microvolt = <3023250>; +- regulator-max-microvolt = <3023250>; +- lltc,fb-voltage-divider = <634000 200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- codec: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_1p8v>; +- VDDIO-supply = <®_3p3v>; +- }; +- +- touchscreen: egalax_ts@4 { +- compatible = "eeti,egalax_ts"; +- reg = <0x04>; +- interrupt-parent = <&gpio1>; +- interrupts = <11 2>; +- wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; +- }; +- +- accel@1e { +- compatible = "nxp,fxos8700"; +- reg = <0x1e>; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <18>; +- status = "okay"; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: hsd100pxn1 { +- clock-frequency = <65000000>; +- hactive = <1024>; +- vactive = <768>; +- hback-porch = <220>; +- hfront-porch = <40>; +- vback-porch = <21>; +- vfront-porch = <7>; +- hsync-len = <60>; +- vsync-len = <10>; +- }; +- }; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ +- status = "disabled"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ +- status = "disabled"; +-}; +- +-&pwm4 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- no-1-8-v; /* firmware will remove if board revision supports */ +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 +- MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 +- MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 +- MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 +- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ +- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ +- >; +- }; +- +- pinctrl_pps: ppsgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ +- MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp100mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp200mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-gw54xx.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-gw54xx.dtsi +deleted file mode 100644 +index cda48bf2f168..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-gw54xx.dtsi ++++ /dev/null +@@ -1,863 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Gateworks Corporation +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- /* these are used by bootloader for disabling nodes */ +- aliases { +- led0 = &led0; +- led1 = &led1; +- led2 = &led2; +- nand = &gpmi; +- ssi0 = &ssi1; +- usb0 = &usbh1; +- usb1 = &usbotg; +- }; +- +- chosen { +- bootargs = "console=ttymxc1,115200"; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm4 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-pb { +- label = "user_pb"; +- gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- user-pb1x { +- label = "user_pb1x"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <0>; +- }; +- +- key-erased { +- label = "key-erased"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <1>; +- }; +- +- eeprom-wp { +- label = "eeprom_wp"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <2>; +- }; +- +- tamper { +- label = "tamper"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <5>; +- }; +- +- switch-hold { +- label = "switch_hold"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <7>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led0: user1 { +- label = "user1"; +- gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led1: user2 { +- label = "user2"; +- gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ +- default-state = "off"; +- }; +- +- led2: user3 { +- label = "user3"; +- gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ +- default-state = "off"; +- }; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- pps { +- compatible = "pps-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pps>; +- gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_1p0v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "1P0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_h1_vbus: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- }; +- +- sound-analog { +- compatible = "fsl,imx6q-ventana-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "sgtl5000-audio"; +- ssi-controller = <&ssi1>; +- audio-codec = <&sgtl5000>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <4>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */ +- status = "okay"; +- +- ssi2 { +- fsl,audmux-port = <1>; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_TFSDIR | +- IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */ +- IMX_AUDMUX_V2_PTCR_TCLKDIR | +- IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */ +- IMX_AUDMUX_V2_PTCR_SYN) +- IMX_AUDMUX_V2_PDCR_RXDSEL(4) +- >; +- }; +- +- aud5 { +- fsl,audmux-port = <4>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN +- IMX_AUDMUX_V2_PDCR_RXDSEL(1)>; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, +- <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +-}; +- +-&ecspi2 { +- cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- gsc: gsc@20 { +- compatible = "gw,gsc"; +- reg = <0x20>; +- interrupt-parent = <&gpio1>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- adc { +- compatible = "gw,gsc-adc"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@0 { +- gw,mode = <0>; +- reg = <0x00>; +- label = "temp"; +- }; +- +- channel@2 { +- gw,mode = <1>; +- reg = <0x02>; +- label = "vdd_vin"; +- }; +- +- channel@5 { +- gw,mode = <1>; +- reg = <0x05>; +- label = "vdd_3p3"; +- }; +- +- channel@8 { +- gw,mode = <1>; +- reg = <0x08>; +- label = "vdd_bat"; +- }; +- +- channel@b { +- gw,mode = <1>; +- reg = <0x0b>; +- label = "vdd_5p0"; +- }; +- +- channel@e { +- gw,mode = <1>; +- reg = <0xe>; +- label = "vdd_arm"; +- }; +- +- channel@11 { +- gw,mode = <1>; +- reg = <0x11>; +- label = "vdd_soc"; +- }; +- +- channel@14 { +- gw,mode = <1>; +- reg = <0x14>; +- label = "vdd_3p0"; +- }; +- +- channel@17 { +- gw,mode = <1>; +- reg = <0x17>; +- label = "vdd_1p5"; +- }; +- +- channel@1d { +- gw,mode = <1>; +- reg = <0x1d>; +- label = "vdd_1p8"; +- }; +- +- channel@20 { +- gw,mode = <1>; +- reg = <0x20>; +- label = "vdd_1p0"; +- }; +- +- channel@23 { +- gw,mode = <1>; +- reg = <0x23>; +- label = "vdd_2p5"; +- }; +- +- channel@26 { +- gw,mode = <1>; +- reg = <0x26>; +- label = "vdd_gps"; +- }; +- }; +- +- fan-controller@2c { +- compatible = "gw,gsc-fan"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2c>; +- }; +- }; +- +- gsc_gpio: gpio@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gsc>; +- interrupts = <4>; +- }; +- +- eeprom1: eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom2: eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- eeprom3: eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- eeprom4: eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +- +- rtc: ds1672@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- pmic: pfuze100@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- sgtl5000: audio-codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <&sw4_reg>; +- VDDIO-supply = <®_3p3v>; +- }; +- +- touchscreen: egalax_ts@4 { +- compatible = "eeti,egalax_ts"; +- reg = <0x04>; +- interrupt-parent = <&gpio7>; +- interrupts = <12 2>; +- wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; +- }; +- +- accel@1e { +- compatible = "nxp,fxos8700"; +- reg = <0x1e>; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <18>; +- status = "okay"; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: hsd100pxn1 { +- clock-frequency = <65000000>; +- hactive = <1024>; +- vactive = <768>; +- hback-porch = <220>; +- hfront-porch = <40>; +- vback-porch = <21>; +- vfront-porch = <7>; +- hsync-len = <60>; +- vsync-len = <10>; +- }; +- }; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */ +- status = "disabled"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ +- status = "disabled"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ +- status = "disabled"; +-}; +- +-&pwm4 { +- #pwm-cells = <2>; +- pinctrl-names = "default", "state_dio"; +- pinctrl-0 = <&pinctrl_pwm4_backlight>; +- pinctrl-1 = <&pinctrl_pwm4_dio>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&ssi2 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- no-1-8-v; /* firmware will remove if board revision supports */ +- status = "okay"; +-}; +- +-&wdog1 { +- status = "disabled"; +-}; +- +-&wdog2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 +- MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 +- MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 +- MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ +- MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0 +- MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 +- MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- >; +- }; +- +- pinctrl_ecspi2: escpi2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 +- MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 +- MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 +- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 +- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ +- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ +- >; +- }; +- +- pinctrl_pps: ppsgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm4_backlight: pwm4grpbacklight { +- fsl,pins = < +- /* LVDS_PWM J6.5 */ +- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm4_dio: pwm4grpdio { +- fsl,pins = < +- /* DIO3 J16.4 */ +- MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ +- MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp100mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp200mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-gw551x.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-gw551x.dtsi +deleted file mode 100644 +index 435dec6338fe..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-gw551x.dtsi ++++ /dev/null +@@ -1,695 +0,0 @@ +-/* +- * Copyright 2014 Gateworks Corporation +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- /* these are used by bootloader for disabling nodes */ +- aliases { +- led0 = &led0; +- nand = &gpmi; +- ssi0 = &ssi1; +- usb0 = &usbh1; +- usb1 = &usbotg; +- }; +- +- chosen { +- bootargs = "console=ttymxc1,115200"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-pb { +- label = "user_pb"; +- gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- user-pb1x { +- label = "user_pb1x"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <0>; +- }; +- +- key-erased { +- label = "key-erased"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <1>; +- }; +- +- eeprom-wp { +- label = "eeprom_wp"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <2>; +- }; +- +- tamper { +- label = "tamper"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <5>; +- }; +- +- switch-hold { +- label = "switch_hold"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <7>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led0: user1 { +- label = "user1"; +- gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +- +- reg_5p0v: regulator-5p0v { +- compatible = "regulator-fixed"; +- regulator-name = "5P0V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usb_h1_vbus: regulator-usb-h1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- sound-digital { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "tda1997x-audio"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sound_codec>; +- simple-audio-card,frame-master = <&sound_codec>; +- +- sound_cpu: simple-audio-card,cpu { +- sound-dai = <&ssi1>; +- }; +- +- sound_codec: simple-audio-card,codec { +- sound-dai = <&hdmi_receiver>; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */ +- status = "okay"; +- +- ssi1 { +- fsl,audmux-port = <0>; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_TFSDIR | +- IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */ +- IMX_AUDMUX_V2_PTCR_TCLKDIR | +- IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */ +- IMX_AUDMUX_V2_PTCR_SYN) +- IMX_AUDMUX_V2_PDCR_RXDSEL(4) +- >; +- }; +- +- aud5 { +- fsl,audmux-port = <4>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN +- IMX_AUDMUX_V2_PDCR_RXDSEL(0)>; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- status = "okay"; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- gsc: gsc@20 { +- compatible = "gw,gsc"; +- reg = <0x20>; +- interrupt-parent = <&gpio1>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <1>; +- #size-cells = <0>; +- +- adc { +- compatible = "gw,gsc-adc"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@0 { +- gw,mode = <0>; +- reg = <0x00>; +- label = "temp"; +- }; +- +- channel@2 { +- gw,mode = <1>; +- reg = <0x02>; +- label = "vdd_vin"; +- }; +- +- channel@5 { +- gw,mode = <1>; +- reg = <0x05>; +- label = "vdd_3p3"; +- }; +- +- channel@8 { +- gw,mode = <1>; +- reg = <0x08>; +- label = "vdd_bat"; +- }; +- +- channel@b { +- gw,mode = <1>; +- reg = <0x0b>; +- label = "vdd_5p0"; +- }; +- +- channel@e { +- gw,mode = <1>; +- reg = <0xe>; +- label = "vdd_arm"; +- }; +- +- channel@11 { +- gw,mode = <1>; +- reg = <0x11>; +- label = "vdd_soc"; +- }; +- +- channel@14 { +- gw,mode = <1>; +- reg = <0x14>; +- label = "vdd_3p0"; +- }; +- +- channel@17 { +- gw,mode = <1>; +- reg = <0x17>; +- label = "vdd_1p5"; +- }; +- +- channel@1d { +- gw,mode = <1>; +- reg = <0x1d>; +- label = "vdd_1p8a"; +- }; +- +- channel@20 { +- gw,mode = <1>; +- reg = <0x20>; +- label = "vdd_1p0b"; +- }; +- }; +- }; +- +- gsc_gpio: gpio@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gsc>; +- interrupts = <4>; +- }; +- +- eeprom1: eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom2: eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- eeprom3: eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- eeprom4: eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +- +- rtc: ds1672@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- ltc3676: pmic@3c { +- compatible = "lltc,ltc3676"; +- reg = <0x3c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio1>; +- interrupts = <8 IRQ_TYPE_EDGE_FALLING>; +- +- regulators { +- /* VDD_SOC (1+R1/R2 = 1.635) */ +- reg_vdd_soc: sw1 { +- regulator-name = "vddsoc"; +- regulator-min-microvolt = <674400>; +- regulator-max-microvolt = <1308000>; +- lltc,fb-voltage-divider = <127000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_DDR (1+R1/R2 = 2.105) */ +- reg_vdd_ddr: sw2 { +- regulator-name = "vddddr"; +- regulator-min-microvolt = <868310>; +- regulator-max-microvolt = <1684000>; +- lltc,fb-voltage-divider = <221000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_ARM (1+R1/R2 = 1.635) */ +- reg_vdd_arm: sw3 { +- regulator-name = "vddarm"; +- regulator-min-microvolt = <674400>; +- regulator-max-microvolt = <1308000>; +- lltc,fb-voltage-divider = <127000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_3P3 (1+R1/R2 = 1.281) */ +- reg_3p3: sw4 { +- regulator-name = "vdd3p3"; +- regulator-min-microvolt = <1880000>; +- regulator-max-microvolt = <3647000>; +- lltc,fb-voltage-divider = <200000 56200>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_1P8a (1+R1/R2 = 2.505): HDMI In core */ +- reg_1p8a: ldo2 { +- regulator-name = "vdd1p8a"; +- regulator-min-microvolt = <1816125>; +- regulator-max-microvolt = <1816125>; +- lltc,fb-voltage-divider = <301000 200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_1P8b: HDMI In analog */ +- reg_1p8b: ldo3 { +- regulator-name = "vdd1p8b"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- }; +- +- /* VDD_HIGH (1+R1/R2 = 4.17) */ +- reg_3p0: ldo4 { +- regulator-name = "vdd3p0"; +- regulator-min-microvolt = <3023250>; +- regulator-max-microvolt = <3023250>; +- lltc,fb-voltage-divider = <634000 200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- gpio_exp: pca9555@24 { +- compatible = "nxp,pca9555"; +- reg = <0x24>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- hdmi_receiver: hdmi-receiver@48 { +- compatible = "nxp,tda19971"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tda1997x>; +- reg = <0x48>; +- interrupt-parent = <&gpio1>; +- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; +- DOVDD-supply = <®_3p3>; +- AVDD-supply = <®_1p8b>; +- DVDD-supply = <®_1p8a>; +- #sound-dai-cells = <0>; +- nxp,audout-format = "i2s"; +- nxp,audout-layout = <0>; +- nxp,audout-width = <16>; +- nxp,audout-mclk-fs = <128>; +- /* +- * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] +- * and Y[11:4] across 16bits in the same cycle +- * which we map to VP[15:08]<->CSI_DATA[19:12] +- */ +- nxp,vidout-portcfg = +- /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/ +- < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, +- /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/ +- < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, +- /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/ +- < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, +- /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/ +- < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; +- +- port { +- tda1997x_to_ipu1_csi0_mux: endpoint { +- remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; +- bus-width = <16>; +- hsync-active = <1>; +- vsync-active = <1>; +- data-active = <1>; +- }; +- }; +- }; +-}; +- +-&ipu1_csi0_from_ipu1_csi0_mux { +- bus-width = <16>; +-}; +- +-&ipu1_csi0_mux_from_parallel_sensor { +- remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; +- bus-width = <16>; +-}; +- +-&ipu1_csi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_csi0>; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ +- status = "disabled"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ +- status = "disabled"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 +- MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x130b0 +- MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x130b0 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_ipu1_csi0: ipu1_csi0grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 +- MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 +- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 +- MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_tda1997x: tda1997xgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-gw552x.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-gw552x.dtsi +deleted file mode 100644 +index 2e61102ae694..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-gw552x.dtsi ++++ /dev/null +@@ -1,519 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2014 Gateworks Corporation +- */ +- +-#include +-#include +-#include +- +-/ { +- /* these are used by bootloader for disabling nodes */ +- aliases { +- led0 = &led0; +- led1 = &led1; +- led2 = &led2; +- nand = &gpmi; +- usb0 = &usbh1; +- usb1 = &usbotg; +- }; +- +- chosen { +- bootargs = "console=ttymxc1,115200"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-pb { +- label = "user_pb"; +- gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- user-pb1x { +- label = "user_pb1x"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <0>; +- }; +- +- key-erased { +- label = "key-erased"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <1>; +- }; +- +- eeprom-wp { +- label = "eeprom_wp"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <2>; +- }; +- +- tamper { +- label = "tamper"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <5>; +- }; +- +- switch-hold { +- label = "switch_hold"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <7>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led0: user1 { +- label = "user1"; +- gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led1: user2 { +- label = "user2"; +- gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ +- default-state = "off"; +- }; +- +- led2: user3 { +- label = "user3"; +- gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ +- default-state = "off"; +- }; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +- +- reg_1p0v: regulator-1p0v { +- compatible = "regulator-fixed"; +- regulator-name = "1P0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_5p0v: regulator-5p0v { +- compatible = "regulator-fixed"; +- regulator-name = "5P0V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- gsc: gsc@20 { +- compatible = "gw,gsc"; +- reg = <0x20>; +- interrupt-parent = <&gpio1>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <1>; +- #size-cells = <0>; +- +- adc { +- compatible = "gw,gsc-adc"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@0 { +- gw,mode = <0>; +- reg = <0x00>; +- label = "temp"; +- }; +- +- channel@2 { +- gw,mode = <1>; +- reg = <0x02>; +- label = "vdd_vin"; +- }; +- +- channel@5 { +- gw,mode = <1>; +- reg = <0x05>; +- label = "vdd_3p3"; +- }; +- +- channel@8 { +- gw,mode = <1>; +- reg = <0x08>; +- label = "vdd_bat"; +- }; +- +- channel@b { +- gw,mode = <1>; +- reg = <0x0b>; +- label = "vdd_5p0"; +- }; +- +- channel@e { +- gw,mode = <1>; +- reg = <0xe>; +- label = "vdd_arm"; +- }; +- +- channel@11 { +- gw,mode = <1>; +- reg = <0x11>; +- label = "vdd_soc"; +- }; +- +- channel@14 { +- gw,mode = <1>; +- reg = <0x14>; +- label = "vdd_3p0"; +- }; +- +- channel@17 { +- gw,mode = <1>; +- reg = <0x17>; +- label = "vdd_1p5"; +- }; +- +- channel@1d { +- gw,mode = <1>; +- reg = <0x1d>; +- label = "vdd_1p8"; +- }; +- +- channel@20 { +- gw,mode = <1>; +- reg = <0x20>; +- label = "vdd_1p0"; +- }; +- +- channel@23 { +- gw,mode = <1>; +- reg = <0x23>; +- label = "vdd_2p5"; +- }; +- }; +- }; +- +- gsc_gpio: gpio@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gsc>; +- interrupts = <4>; +- }; +- +- eeprom1: eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom2: eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- eeprom3: eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- eeprom4: eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +- +- rtc: ds1672@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- ltc3676: pmic@3c { +- compatible = "lltc,ltc3676"; +- reg = <0x3c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio1>; +- interrupts = <8 IRQ_TYPE_EDGE_FALLING>; +- +- regulators { +- /* VDD_SOC (1+R1/R2 = 1.635) */ +- reg_vdd_soc: sw1 { +- regulator-name = "vddsoc"; +- regulator-min-microvolt = <674400>; +- regulator-max-microvolt = <1308000>; +- lltc,fb-voltage-divider = <127000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_1P8 (1+R1/R2 = 2.505): ENET-PHY */ +- reg_1p8v: sw2 { +- regulator-name = "vdd1p8"; +- regulator-min-microvolt = <1033310>; +- regulator-max-microvolt = <2004000>; +- lltc,fb-voltage-divider = <301000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_ARM (1+R1/R2 = 1.635) */ +- reg_vdd_arm: sw3 { +- regulator-name = "vddarm"; +- regulator-min-microvolt = <674400>; +- regulator-max-microvolt = <1308000>; +- lltc,fb-voltage-divider = <127000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_DDR (1+R1/R2 = 2.105) */ +- reg_vdd_ddr: sw4 { +- regulator-name = "vddddr"; +- regulator-min-microvolt = <868310>; +- regulator-max-microvolt = <1684000>; +- lltc,fb-voltage-divider = <221000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ +- reg_2p5v: ldo2 { +- regulator-name = "vdd2p5"; +- regulator-min-microvolt = <2490375>; +- regulator-max-microvolt = <2490375>; +- lltc,fb-voltage-divider = <487000 200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_HIGH (1+R1/R2 = 4.17) */ +- reg_3p0v: ldo4 { +- regulator-name = "vdd3p0"; +- regulator-min-microvolt = <3023250>; +- regulator-max-microvolt = <3023250>; +- lltc,fb-voltage-divider = <634000 200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ +- status = "disabled"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ +- status = "disabled"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; }; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_5p0v>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 +- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-gw553x.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-gw553x.dtsi +deleted file mode 100644 +index 4662408b225a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-gw553x.dtsi ++++ /dev/null +@@ -1,738 +0,0 @@ +-/* +- * Copyright 2016 Gateworks Corporation +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include +- +-/ { +- /* these are used by bootloader for disabling nodes */ +- aliases { +- led0 = &led0; +- led1 = &led1; +- nand = &gpmi; +- usb0 = &usbh1; +- usb1 = &usbotg; +- }; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-pb { +- label = "user_pb"; +- gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- user-pb1x { +- label = "user_pb1x"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <0>; +- }; +- +- key-erased { +- label = "key-erased"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <1>; +- }; +- +- eeprom-wp { +- label = "eeprom_wp"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <2>; +- }; +- +- tamper { +- label = "tamper"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <5>; +- }; +- +- switch-hold { +- label = "switch_hold"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <7>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led0: user1 { +- label = "user1"; +- gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led1: user2 { +- label = "user2"; +- gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ +- default-state = "off"; +- }; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +- +- pps { +- compatible = "pps-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pps>; +- gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- reg_5p0v: regulator-5p0v { +- compatible = "regulator-fixed"; +- regulator-name = "5P0V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- status = "okay"; +-}; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hdmi>; +- ddc-i2c-bus = <&i2c3>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- gsc: gsc@20 { +- compatible = "gw,gsc"; +- reg = <0x20>; +- interrupt-parent = <&gpio1>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <1>; +- #size-cells = <0>; +- +- adc { +- compatible = "gw,gsc-adc"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@0 { +- gw,mode = <0>; +- reg = <0x00>; +- label = "temp"; +- }; +- +- channel@2 { +- gw,mode = <1>; +- reg = <0x02>; +- label = "vdd_vin"; +- }; +- +- channel@5 { +- gw,mode = <1>; +- reg = <0x05>; +- label = "vdd_3p3"; +- }; +- +- channel@8 { +- gw,mode = <1>; +- reg = <0x08>; +- label = "vdd_bat"; +- }; +- +- channel@b { +- gw,mode = <1>; +- reg = <0x0b>; +- label = "vdd_5p0"; +- }; +- +- channel@e { +- gw,mode = <1>; +- reg = <0xe>; +- label = "vdd_arm"; +- }; +- +- channel@11 { +- gw,mode = <1>; +- reg = <0x11>; +- label = "vdd_soc"; +- }; +- +- channel@14 { +- gw,mode = <1>; +- reg = <0x14>; +- label = "vdd_3p0"; +- }; +- +- channel@17 { +- gw,mode = <1>; +- reg = <0x17>; +- label = "vdd_1p5"; +- }; +- +- channel@1d { +- gw,mode = <1>; +- reg = <0x1d>; +- label = "vdd_1p8a"; +- }; +- +- channel@20 { +- gw,mode = <1>; +- reg = <0x20>; +- label = "vdd_1p0b"; +- }; +- +- channel@26 { +- gw,mode = <1>; +- reg = <0x26>; +- label = "vdd_an1"; +- }; +- }; +- }; +- +- gsc_gpio: gpio@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gsc>; +- interrupts = <4>; +- }; +- +- eeprom1: eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom2: eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- eeprom3: eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- eeprom4: eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +- +- rtc: ds1672@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- magn@1c { +- compatible = "st,lsm9ds1-magn"; +- reg = <0x1c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mag>; +- interrupt-parent = <&gpio1>; +- interrupts = <2 IRQ_TYPE_EDGE_RISING>; +- }; +- +- imu@6a { +- compatible = "st,lsm9ds1-imu"; +- reg = <0x6a>; +- st,drdy-int-pin = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_imu>; +- interrupt-parent = <&gpio7>; +- interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- ltc3676: pmic@3c { +- compatible = "lltc,ltc3676"; +- reg = <0x3c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio1>; +- interrupts = <8 IRQ_TYPE_EDGE_FALLING>; +- +- regulators { +- /* VDD_SOC (1+R1/R2 = 1.635) */ +- reg_vdd_soc: sw1 { +- regulator-name = "vddsoc"; +- regulator-min-microvolt = <674400>; +- regulator-max-microvolt = <1308000>; +- lltc,fb-voltage-divider = <127000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_DDR (1+R1/R2 = 2.105) */ +- reg_vdd_ddr: sw2 { +- regulator-name = "vddddr"; +- regulator-min-microvolt = <868310>; +- regulator-max-microvolt = <1684000>; +- lltc,fb-voltage-divider = <221000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_ARM (1+R1/R2 = 1.635) */ +- reg_vdd_arm: sw3 { +- regulator-name = "vddarm"; +- regulator-min-microvolt = <674400>; +- regulator-max-microvolt = <1308000>; +- lltc,fb-voltage-divider = <127000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_3P3 (1+R1/R2 = 1.281) */ +- reg_3p3v: sw4 { +- regulator-name = "vdd3p3"; +- regulator-min-microvolt = <1880000>; +- regulator-max-microvolt = <3647000>; +- lltc,fb-voltage-divider = <200000 56200>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_1P8a (1+R1/R2 = 2.505): Analog Video Decoder */ +- reg_1p8a: ldo2 { +- regulator-name = "vdd1p8a"; +- regulator-min-microvolt = <1816125>; +- regulator-max-microvolt = <1816125>; +- lltc,fb-voltage-divider = <301000 200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_1P8b: microSD VDD_1P8 */ +- reg_1p8b: ldo3 { +- regulator-name = "vdd1p8b"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- }; +- +- /* VDD_HIGH (1+R1/R2 = 4.17) */ +- reg_3p0v: ldo4 { +- regulator-name = "vdd3p0"; +- regulator-min-microvolt = <3023250>; +- regulator-max-microvolt = <3023250>; +- lltc,fb-voltage-divider = <634000 200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- adv7180: camera@20 { +- compatible = "adi,adv7180"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adv7180>; +- reg = <0x20>; +- powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; +- interrupt-parent = <&gpio5>; +- interrupts = <23 IRQ_TYPE_LEVEL_LOW>; +- +- port { +- adv7180_to_ipu1_csi0_mux: endpoint { +- remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; +- bus-width = <8>; +- }; +- }; +- }; +-}; +- +-&ipu1_csi0_from_ipu1_csi0_mux { +- bus-width = <8>; +-}; +- +-&ipu1_csi0_mux_from_parallel_sensor { +- remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; +- bus-width = <8>; +-}; +- +-&ipu1_csi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_csi0>; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ +- status = "disabled"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ +- status = "disabled"; +-}; +- +-&pwm4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ +- status = "disabled"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl_adv7180: adv7180grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 +- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- >; +- }; +- +- pinctrl_hdmi: hdmigrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_imu: imugrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 +- >; +- }; +- +- pinctrl_ipu1_csi0: ipu1csi0grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 +- MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 +- MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 +- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 +- MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 +- >; +- }; +- +- pinctrl_mag: maggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ +- >; +- }; +- +- pinctrl_pps: ppsgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ +- MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp100mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp200mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-gw560x.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-gw560x.dtsi +deleted file mode 100644 +index 4bc4371e6bae..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-gw560x.dtsi ++++ /dev/null +@@ -1,932 +0,0 @@ +-/* +- * Copyright 2017 Gateworks Corporation +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include +- +-/ { +- /* these are used by bootloader for disabling nodes */ +- aliases { +- led0 = &led0; +- led1 = &led1; +- led2 = &led2; +- ssi0 = &ssi1; +- usb0 = &usbh1; +- usb1 = &usbotg; +- }; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- backlight-display { +- compatible = "pwm-backlight"; +- pwms = <&pwm4 0 5000000>; +- brightness-levels = < +- 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100 +- >; +- default-brightness-level = <100>; +- }; +- +- backlight-keypad { +- compatible = "gpio-backlight"; +- gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; +- default-on; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-pb { +- label = "user_pb"; +- gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- user-pb1x { +- label = "user_pb1x"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <0>; +- }; +- +- key-erased { +- label = "key-erased"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <1>; +- }; +- +- eeprom-wp { +- label = "eeprom_wp"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <2>; +- }; +- +- tamper { +- label = "tamper"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <5>; +- }; +- +- switch-hold { +- label = "switch_hold"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <7>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led0: user1 { +- label = "user1"; +- gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led1: user2 { +- label = "user2"; +- gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ +- default-state = "off"; +- }; +- +- led2: user3 { +- label = "user3"; +- gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ +- default-state = "off"; +- }; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- pps { +- compatible = "pps-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pps>; +- gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_2p5v: regulator-2p5v { +- compatible = "regulator-fixed"; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_5p0v: regulator-5p0v { +- compatible = "regulator-fixed"; +- regulator-name = "5P0V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_12p0v: regulator-12p0v { +- compatible = "regulator-fixed"; +- regulator-name = "12P0V"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_1p4v: regulator-vddsoc { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_soc"; +- regulator-min-microvolt = <1400000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- }; +- +- reg_usb_h1_vbus: regulator-usb-h1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sound { +- compatible = "fsl,imx6q-ventana-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "sgtl5000-audio"; +- ssi-controller = <&ssi1>; +- audio-codec = <&sgtl5000>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <4>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&ecspi3 { +- cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi3>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, +- <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- gsc: gsc@20 { +- compatible = "gw,gsc"; +- reg = <0x20>; +- interrupt-parent = <&gpio1>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <1>; +- #size-cells = <0>; +- +- adc { +- compatible = "gw,gsc-adc"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@0 { +- gw,mode = <0>; +- reg = <0x00>; +- label = "temp"; +- }; +- +- channel@2 { +- gw,mode = <1>; +- reg = <0x02>; +- label = "vdd_vin"; +- }; +- +- channel@5 { +- gw,mode = <1>; +- reg = <0x05>; +- label = "vdd_3p3"; +- }; +- +- channel@8 { +- gw,mode = <1>; +- reg = <0x08>; +- label = "vdd_bat"; +- }; +- +- channel@b { +- gw,mode = <1>; +- reg = <0x0b>; +- label = "vdd_5p0"; +- }; +- +- channel@e { +- gw,mode = <1>; +- reg = <0xe>; +- label = "vdd_arm"; +- }; +- +- channel@11 { +- gw,mode = <1>; +- reg = <0x11>; +- label = "vdd_soc"; +- }; +- +- channel@14 { +- gw,mode = <1>; +- reg = <0x14>; +- label = "vdd_3p0"; +- }; +- +- channel@17 { +- gw,mode = <1>; +- reg = <0x17>; +- label = "vdd_1p5"; +- }; +- +- channel@1d { +- gw,mode = <1>; +- reg = <0x1d>; +- label = "vdd_1p8"; +- }; +- +- channel@20 { +- gw,mode = <1>; +- reg = <0x20>; +- label = "vdd_an1"; +- }; +- +- channel@23 { +- gw,mode = <1>; +- reg = <0x23>; +- label = "vdd_2p5"; +- }; +- +- channel@26 { +- gw,mode = <1>; +- reg = <0x26>; +- label = "vdd_gps"; +- }; +- +- channel@29 { +- gw,mode = <1>; +- reg = <0x29>; +- label = "vdd_an2"; +- }; +- }; +- }; +- +- gsc_gpio: gpio@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gsc>; +- interrupts = <4>; +- }; +- +- eeprom1: eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom2: eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- eeprom3: eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- eeprom4: eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +- +- ds1672: rtc@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_1p8v>; +- VDDIO-supply = <®_3p3v>; +- }; +- +- magn@1c { +- compatible = "st,lsm9ds1-magn"; +- reg = <0x1c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mag>; +- interrupt-parent = <&gpio5>; +- interrupts = <9 IRQ_TYPE_EDGE_RISING>; +- }; +- +- tca8418: keypad@34 { +- compatible = "ti,tca8418"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_keypad>; +- reg = <0x34>; +- interrupt-parent = <&gpio5>; +- interrupts = <11 IRQ_TYPE_EDGE_FALLING>; +- linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0) +- MATRIX_KEY(0x00, 0x00, BTN_1) +- MATRIX_KEY(0x01, 0x01, BTN_2) +- MATRIX_KEY(0x01, 0x00, BTN_3) +- MATRIX_KEY(0x02, 0x00, BTN_4) +- MATRIX_KEY(0x00, 0x03, BTN_5) +- MATRIX_KEY(0x00, 0x02, BTN_6) +- MATRIX_KEY(0x01, 0x03, BTN_7) +- MATRIX_KEY(0x01, 0x02, BTN_8) +- MATRIX_KEY(0x02, 0x02, BTN_9) +- >; +- keypad,num-rows = <4>; +- keypad,num-columns = <4>; +- }; +- +- ltc3676: pmic@3c { +- compatible = "lltc,ltc3676"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- reg = <0x3c>; +- interrupt-parent = <&gpio1>; +- interrupts = <8 IRQ_TYPE_EDGE_FALLING>; +- +- regulators { +- /* VDD_DDR (1+R1/R2 = 2.105) */ +- reg_vdd_ddr: sw2 { +- regulator-name = "vddddr"; +- regulator-min-microvolt = <868310>; +- regulator-max-microvolt = <1684000>; +- lltc,fb-voltage-divider = <221000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_ARM (1+R1/R2 = 1.931) */ +- reg_vdd_arm: sw3 { +- regulator-name = "vddarm"; +- regulator-min-microvolt = <796551>; +- regulator-max-microvolt = <1544827>; +- lltc,fb-voltage-divider = <243000 261000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- linux,phandle = <®_vdd_arm>; +- }; +- +- /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ +- reg_1p8v: sw4 { +- regulator-name = "vdd1p8"; +- regulator-min-microvolt = <1033310>; +- regulator-max-microvolt = <2004000>; +- lltc,fb-voltage-divider = <301000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */ +- reg_1p0v: ldo2 { +- regulator-name = "vdd1p0"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1050000>; +- lltc,fb-voltage-divider = <78700 200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_AUD_1P8: Audio codec */ +- reg_aud_1p8v: ldo3 { +- regulator-name = "vdd1p8a"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- }; +- +- /* VDD_HIGH (1+R1/R2 = 4.17) */ +- reg_3p0v: ldo4 { +- regulator-name = "vdd3p0"; +- regulator-min-microvolt = <3023250>; +- regulator-max-microvolt = <3023250>; +- lltc,fb-voltage-divider = <634000 200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +- +- imu@6a { +- compatible = "st,lsm9ds1-imu"; +- reg = <0x6a>; +- st,drdy-int-pin = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_imu>; +- interrupt-parent = <&gpio5>; +- interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- egalax_ts: touchscreen@4 { +- compatible = "eeti,egalax_ts"; +- reg = <0x04>; +- interrupt-parent = <&gpio5>; +- interrupts = <12 IRQ_TYPE_EDGE_FALLING>; +- wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&ldb { +- fsl,dual-channel; +- status = "okay"; +- +- lvds-channel@0 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <18>; +- status = "okay"; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: hsd100pxn1 { +- clock-frequency = <65000000>; +- hactive = <1024>; +- vactive = <768>; +- hback-porch = <220>; +- hfront-porch = <40>; +- vback-porch = <21>; +- vfront-porch = <7>; +- hsync-len = <60>; +- vsync-len = <10>; +- }; +- }; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio4 31 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ +- status = "disabled"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ +- status = "disabled"; +-}; +- +-&pwm4 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; +- rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1>; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <8>; +- vmmc-supply = <®_3p3v>; +- non-removable; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- /* AUD4 */ +- MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 +- MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 +- MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 +- MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ +- /* AUD6 */ +- MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 +- MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 +- MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 +- MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 +- >; +- }; +- +- pinctrl_ecspi3: escpi3grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 +- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 +- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 +- MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ +- >; +- }; +- +- pinctrl_flexcan: flexcangrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 +- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x4001b0b0 /* DIOI2C_DIS# */ +- MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0001b0b0 /* LVDS_TOUCH_IRQ# */ +- MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0001b0b0 /* LVDS_BACKEN */ +- >; +- }; +- +- pinctrl_imu: imugrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0 +- >; +- }; +- +- pinctrl_keypad: keypadgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */ +- MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0001b0b0 /* KEYPAD_LED_EN */ +- >; +- }; +- +- pinctrl_mag: maggrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */ +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ +- >; +- }; +- +- pinctrl_pps: ppsgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbh1: usbh1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* USBHUB_RST# */ +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ +- MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 +- MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x170f9 +- MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x170f9 +- MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x170f9 +- MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x170f9 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp100mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp200mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-gw5903.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-gw5903.dtsi +deleted file mode 100644 +index 1fdb7ba630f1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-gw5903.dtsi ++++ /dev/null +@@ -1,793 +0,0 @@ +-/* +- * Copyright 2017 Gateworks Corporation +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include +- +-/ { +- chosen { +- stdout-path = &uart2; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 5000000>; +- brightness-levels = < +- 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100 +- >; +- default-brightness-level = <100>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-pb { +- label = "user_pb"; +- gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- user-pb1x { +- label = "user_pb1x"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <0>; +- }; +- +- key-erased { +- label = "key-erased"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <1>; +- }; +- +- eeprom-wp { +- label = "eeprom_wp"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <2>; +- }; +- +- tamper { +- label = "tamper"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <5>; +- }; +- +- switch-hold { +- label = "switch_hold"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <7>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led0: user1 { +- label = "user1"; +- gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ +- default-state = "off"; +- }; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- reg_5p0v: regulator-5p0v { +- compatible = "regulator-fixed"; +- regulator-name = "5P0V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_2p5v: regulator-2p5v { +- compatible = "regulator-fixed"; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- reg_usb_h1_vbus: regulator-usb-h1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 30 0>; +- enable-active-high; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_12p0: regulator-12p0v { +- compatible = "regulator-fixed"; +- regulator-name = "12P0V"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sound { +- compatible = "fsl,imx-audio-tlv320"; +- model = "imx-tlv320"; +- ssi-controller = <&ssi1>; +- audio-codec = <&tlv320aic3105>; +- /* routing of sink, source */ +- audio-routing = +- /* TLV320 LINE1L pin <-> Mic Jack connector */ +- "LINE1L", "Mic Jack", +- /* board Headphone Jack <-> HPOUT */ +- "Headphone Jack", "HPLOUT", +- "Headphone Jack", "HPROUT", +- "Mic Jack", "Mic Bias"; +- mux-int-port = <1>; +- mux-ext-port = <6>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, +- <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- gsc: gsc@20 { +- compatible = "gw,gsc"; +- reg = <0x20>; +- interrupt-parent = <&gpio1>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <1>; +- #size-cells = <0>; +- +- adc { +- compatible = "gw,gsc-adc"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@0 { +- gw,mode = <0>; +- reg = <0x00>; +- label = "temp"; +- }; +- +- channel@2 { +- gw,mode = <1>; +- reg = <0x02>; +- label = "vdd_vin"; +- }; +- +- channel@5 { +- gw,mode = <1>; +- reg = <0x05>; +- label = "vdd_3p3"; +- }; +- +- channel@8 { +- gw,mode = <1>; +- reg = <0x08>; +- label = "vdd_bat"; +- }; +- +- channel@b { +- gw,mode = <1>; +- reg = <0x0b>; +- label = "vdd_5p0"; +- }; +- +- channel@e { +- gw,mode = <1>; +- reg = <0xe>; +- label = "vdd_arm"; +- }; +- +- channel@11 { +- gw,mode = <1>; +- reg = <0x11>; +- label = "vdd_soc"; +- }; +- +- channel@14 { +- gw,mode = <1>; +- reg = <0x14>; +- label = "vdd_3p0"; +- }; +- +- channel@17 { +- gw,mode = <1>; +- reg = <0x17>; +- label = "vdd_1p5"; +- }; +- +- channel@1d { +- gw,mode = <1>; +- reg = <0x1d>; +- label = "vdd_1p8"; +- }; +- +- channel@20 { +- gw,mode = <1>; +- reg = <0x20>; +- label = "vdd_an1"; +- }; +- +- channel@23 { +- gw,mode = <1>; +- reg = <0x23>; +- label = "vdd_2p5"; +- }; +- }; +- }; +- +- gsc_gpio: gpio@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gsc>; +- interrupts = <4>; +- }; +- +- eeprom1: eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom2: eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- eeprom3: eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- eeprom4: eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +- +- dts1672: rtc@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- ltc3676: pmic@3c { +- compatible = "lltc,ltc3676"; +- reg = <0x3c>; +- interrupt-parent = <&gpio1>; +- interrupts = <8 IRQ_TYPE_EDGE_FALLING>; +- +- regulators { +- /* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */ +- reg_1p8v: sw1 { +- regulator-name = "vdd1p8"; +- regulator-min-microvolt = <1033310>; +- regulator-max-microvolt = <2004000>; +- lltc,fb-voltage-divider = <301000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_DDR (1+R1/R2 = 2.105) */ +- reg_vdd_ddr: sw2 { +- regulator-name = "vddddr"; +- regulator-min-microvolt = <868310>; +- regulator-max-microvolt = <1684000>; +- lltc,fb-voltage-divider = <221000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_ARM (1+R1/R2 = 1.635) */ +- reg_vdd_arm: sw3 { +- regulator-name = "vddarm"; +- regulator-min-microvolt = <674400>; +- regulator-max-microvolt = <1308000>; +- lltc,fb-voltage-divider = <127000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- linux,phandle = <®_vdd_arm>; +- }; +- +- /* VDD_SOC (1+R1/R2 = 1.635) */ +- reg_vdd_soc: sw4 { +- regulator-name = "vddsoc"; +- regulator-min-microvolt = <674400>; +- regulator-max-microvolt = <1308000>; +- lltc,fb-voltage-divider = <127000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- linux,phandle = <®_vdd_soc>; +- }; +- +- /* VDD_1P0 (1+R1/R2 = 1.38): */ +- reg_1p0v: ldo2 { +- regulator-name = "vdd1p0"; +- regulator-min-microvolt = <1002777>; +- regulator-max-microvolt = <1002777>; +- lltc,fb-voltage-divider = <100000 261000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_HIGH (1+R1/R2 = 4.17) */ +- reg_3p0v: ldo4 { +- regulator-name = "vdd3p0"; +- regulator-min-microvolt = <3023250>; +- regulator-max-microvolt = <3023250>; +- lltc,fb-voltage-divider = <634000 200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- tlv320aic3105: codec@18 { +- compatible = "ti,tlv320aic3x"; +- reg = <0x18>; +- reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */ +- /* Regulators */ +- DRVDD-supply = <®_3p3v>; +- AVDD-supply = <®_3p3v>; +- IOVDD-supply = <®_3p3v>; +- DVDD-supply = <®_1p8v>; +- }; +- +- accelerometer@1d { +- compatible = "fsl,mma8451"; +- reg = <0x1d>; +- interrupt-parent = <&gpio7>; +- interrupts = <11 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "INT2"; +- }; +- +- /* headphone detect */ +- ts3a227e@3b { +- compatible = "ti,ts3a227e"; +- reg = <0x3b>; +- interrupt-parent = <&gpio5>; +- interrupts = <15 IRQ_TYPE_LEVEL_LOW>; +- ti,micbias = <4>; /* 2.5V micbias */ +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <18>; +- status = "okay"; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: g101evn010 { +- clock-frequency = <68930000>; +- hactive = <1280>; +- vactive = <800>; +- hback-porch = <220>; +- hfront-porch = <40>; +- vback-porch = <21>; +- vfront-porch = <7>; +- hsync-len = <60>; +- vsync-len = <10>; +- }; +- }; +- }; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1_200mhz>; +- vmmc-supply = <®_3p3v>; +- non-removable; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>; +- cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- max-frequency = <100000000>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- non-removable; +- vmmc-supply = <®_3p3v>; +- keep-power-in-suspend; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 +- MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 +- MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 +- MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* MCK */ +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ +- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 /* PHY_EN */ +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- /* I2C3 */ +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- +- /* Headphone Detect */ +- MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0001b0b0 /* HPDET_IRQ# */ +- MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0001b0b0 /* HPDET_MIC# */ +- +- /* Codec */ +- MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0001b0b0 /* CODEC_RST# */ +- +- /* Touch Controller */ +- MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* TOUCH_IRQ# */ +- MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b0b0 /* TOUCH_RST */ +- +- /* Stow Sensor */ +- MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b0b0 /* ACCEL_IRQ2 */ +- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b0b0 /* ACCEL_IRQ1 */ +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* TXEN */ +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x4001b0b0 /* PWR_EN */ +- MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1grp200mhz { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x4001b0b0 /* EMMY_EN */ +- MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x4001b0b0 /* EMMY_CFG1# */ +- MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x4001b0b0 /* EMMY_CFG2# */ +- MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0001b0b0 /* EMMY_BTWAKE# */ +- MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0001b0b0 /* EMMY_WFWAKE# */ +- +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x100f9 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x17059 /* CD */ +- MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x17059 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2grp100mhz { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 +- MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170b9 /* CD */ +- MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170b9 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2grp200mhz { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 +- MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170f9 /* CD */ +- MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170f9 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp100mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp200mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-gw5904.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-gw5904.dtsi +deleted file mode 100644 +index 612b6e068e28..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-gw5904.dtsi ++++ /dev/null +@@ -1,815 +0,0 @@ +-/* +- * Copyright 2017 Gateworks Corporation +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include +- +-/ { +- /* these are used by bootloader for disabling nodes */ +- aliases { +- led0 = &led0; +- led1 = &led1; +- led2 = &led2; +- usb0 = &usbh1; +- usb1 = &usbotg; +- }; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm4 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-pb { +- label = "user_pb"; +- gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- user-pb1x { +- label = "user_pb1x"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <0>; +- }; +- +- key-erased { +- label = "key-erased"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <1>; +- }; +- +- eeprom-wp { +- label = "eeprom_wp"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <2>; +- }; +- +- tamper { +- label = "tamper"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <5>; +- }; +- +- switch-hold { +- label = "switch_hold"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <7>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led0: user1 { +- label = "user1"; +- gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led1: user2 { +- label = "user2"; +- gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ +- default-state = "off"; +- }; +- +- led2: user3 { +- label = "user3"; +- gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ +- default-state = "off"; +- }; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- pps { +- compatible = "pps-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pps>; +- gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_1p0v: regulator-1p0v { +- compatible = "regulator-fixed"; +- regulator-name = "1P0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_h1_vbus: regulator-usb-h1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, +- <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- status = "okay"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch@0 { +- compatible = "marvell,mv88e6085"; +- reg = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan4"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan3"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan1"; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <&fec>; +- }; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- gsc: gsc@20 { +- compatible = "gw,gsc"; +- reg = <0x20>; +- interrupt-parent = <&gpio1>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <1>; +- #size-cells = <0>; +- +- adc { +- compatible = "gw,gsc-adc"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@0 { +- gw,mode = <0>; +- reg = <0x00>; +- label = "temp"; +- }; +- +- channel@2 { +- gw,mode = <1>; +- reg = <0x02>; +- label = "vdd_vin"; +- }; +- +- channel@5 { +- gw,mode = <1>; +- reg = <0x05>; +- label = "vdd_3p3"; +- }; +- +- channel@8 { +- gw,mode = <1>; +- reg = <0x08>; +- label = "vdd_bat"; +- }; +- +- channel@b { +- gw,mode = <1>; +- reg = <0x0b>; +- label = "vdd_5p0"; +- }; +- +- channel@e { +- gw,mode = <1>; +- reg = <0xe>; +- label = "vdd_arm"; +- }; +- +- channel@11 { +- gw,mode = <1>; +- reg = <0x11>; +- label = "vdd_soc"; +- }; +- +- channel@14 { +- gw,mode = <1>; +- reg = <0x14>; +- label = "vdd_3p0"; +- }; +- +- channel@17 { +- gw,mode = <1>; +- reg = <0x17>; +- label = "vdd_1p5"; +- }; +- +- channel@1d { +- gw,mode = <1>; +- reg = <0x1d>; +- label = "vdd_1p8"; +- }; +- +- channel@20 { +- gw,mode = <1>; +- reg = <0x20>; +- label = "vdd_an1"; +- }; +- +- channel@23 { +- gw,mode = <1>; +- reg = <0x23>; +- label = "vdd_2p5"; +- }; +- }; +- }; +- +- gsc_gpio: gpio@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gsc>; +- interrupts = <4>; +- }; +- +- eeprom1: eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom2: eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- eeprom3: eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- eeprom4: eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +- +- dts1672: rtc@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- magn@1c { +- compatible = "st,lsm9ds1-magn"; +- reg = <0x1c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mag>; +- interrupt-parent = <&gpio5>; +- interrupts = <17 IRQ_TYPE_EDGE_RISING>; +- }; +- +- ltc3676: pmic@3c { +- compatible = "lltc,ltc3676"; +- reg = <0x3c>; +- interrupt-parent = <&gpio1>; +- interrupts = <8 IRQ_TYPE_EDGE_FALLING>; +- +- regulators { +- /* VDD_SOC (1+R1/R2 = 1.635) */ +- reg_vdd_soc: sw1 { +- regulator-name = "vddsoc"; +- regulator-min-microvolt = <674400>; +- regulator-max-microvolt = <1308000>; +- lltc,fb-voltage-divider = <127000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */ +- reg_1p8v: sw2 { +- regulator-name = "vdd1p8"; +- regulator-min-microvolt = <1033310>; +- regulator-max-microvolt = <2004000>; +- lltc,fb-voltage-divider = <301000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_ARM (1+R1/R2 = 1.635) */ +- reg_vdd_arm: sw3 { +- regulator-name = "vddarm"; +- regulator-min-microvolt = <674400>; +- regulator-max-microvolt = <1308000>; +- lltc,fb-voltage-divider = <127000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_DDR (1+R1/R2 = 2.105) */ +- reg_vdd_ddr: sw4 { +- regulator-name = "vddddr"; +- regulator-min-microvolt = <868310>; +- regulator-max-microvolt = <1684000>; +- lltc,fb-voltage-divider = <221000 200000>; +- regulator-ramp-delay = <7000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ +- reg_2p5v: ldo2 { +- regulator-name = "vdd2p5"; +- regulator-min-microvolt = <2490375>; +- regulator-max-microvolt = <2490375>; +- lltc,fb-voltage-divider = <487000 200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* VDD_HIGH (1+R1/R2 = 4.17) */ +- reg_3p0v: ldo4 { +- regulator-name = "vdd3p0"; +- regulator-min-microvolt = <3023250>; +- regulator-max-microvolt = <3023250>; +- lltc,fb-voltage-divider = <634000 200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +- +- crypto@60 { +- compatible = "atmel,atecc508a"; +- reg = <0x60>; +- }; +- +- imu@6a { +- compatible = "st,lsm9ds1-imu"; +- reg = <0x6a>; +- st,drdy-int-pin = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_imu>; +- interrupt-parent = <&gpio4>; +- interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- egalax_ts: touchscreen@4 { +- compatible = "eeti,egalax_ts"; +- reg = <0x04>; +- interrupt-parent = <&gpio1>; +- interrupts = <11 IRQ_TYPE_EDGE_FALLING>; +- wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <18>; +- status = "okay"; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: hsd100pxn1 { +- clock-frequency = <65000000>; +- hactive = <1024>; +- vactive = <768>; +- hback-porch = <220>; +- hfront-porch = <40>; +- vback-porch = <21>; +- vfront-porch = <7>; +- hsync-len = <60>; +- vsync-len = <10>; +- }; +- }; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ +- status = "disabled"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ +- status = "disabled"; +-}; +- +-&pwm4 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- non-removable; +- vmmc-supply = <®_3p3v>; +- keep-power-in-suspend; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 +- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_imu: imugrp { +- fsl,pins = < +- MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 +- >; +- }; +- +- pinctrl_mag: maggrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* PMIC_IRQ# */ +- >; +- }; +- +- pinctrl_pps: ppsgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ +- MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp100mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp200mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-gw5907.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-gw5907.dtsi +deleted file mode 100644 +index fcd3bdfd6182..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-gw5907.dtsi ++++ /dev/null +@@ -1,536 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2019 Gateworks Corporation +- */ +- +-#include +-#include +-#include +- +-/ { +- /* these are used by bootloader for disabling nodes */ +- aliases { +- led0 = &led0; +- led1 = &led1; +- nand = &gpmi; +- usb0 = &usbh1; +- usb1 = &usbotg; +- }; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-pb { +- label = "user_pb"; +- gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- user-pb1x { +- label = "user_pb1x"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <0>; +- }; +- +- key-erased { +- label = "key-erased"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <1>; +- }; +- +- eeprom-wp { +- label = "eeprom_wp"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <2>; +- }; +- +- tamper { +- label = "tamper"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <5>; +- }; +- +- switch-hold { +- label = "switch_hold"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <7>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led0: user1 { +- label = "user1"; +- gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led1: user2 { +- label = "user2"; +- gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ +- default-state = "off"; +- }; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +- +- pps { +- compatible = "pps-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pps>; +- gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_5p0v: regulator-5p0v { +- compatible = "regulator-fixed"; +- regulator-name = "5P0V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- gsc: gsc@20 { +- compatible = "gw,gsc"; +- reg = <0x20>; +- interrupt-parent = <&gpio1>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <1>; +- #size-cells = <0>; +- +- adc { +- compatible = "gw,gsc-adc"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@0 { +- gw,mode = <0>; +- reg = <0x00>; +- label = "temp"; +- }; +- +- channel@2 { +- gw,mode = <1>; +- reg = <0x02>; +- label = "vdd_vin"; +- }; +- +- channel@5 { +- gw,mode = <1>; +- reg = <0x05>; +- label = "vdd_3p3"; +- }; +- +- channel@8 { +- gw,mode = <1>; +- reg = <0x08>; +- label = "vdd_bat"; +- }; +- +- channel@b { +- gw,mode = <1>; +- reg = <0x0b>; +- label = "vdd_5p0"; +- }; +- +- channel@e { +- gw,mode = <1>; +- reg = <0xe>; +- label = "vdd_arm"; +- }; +- +- channel@11 { +- gw,mode = <1>; +- reg = <0x11>; +- label = "vdd_soc"; +- }; +- +- channel@14 { +- gw,mode = <1>; +- reg = <0x14>; +- label = "vdd_3p0"; +- }; +- +- channel@17 { +- gw,mode = <1>; +- reg = <0x17>; +- label = "vdd_1p5"; +- }; +- +- channel@1d { +- gw,mode = <1>; +- reg = <0x1d>; +- label = "vdd_1p8"; +- }; +- +- channel@20 { +- gw,mode = <1>; +- reg = <0x20>; +- label = "vdd_an1"; +- }; +- +- channel@23 { +- gw,mode = <1>; +- reg = <0x23>; +- label = "vdd_2p5"; +- }; +- }; +- }; +- +- gsc_gpio: gpio@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gsc>; +- interrupts = <4>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +- +- ds1672@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- gpio@20 { +- compatible = "nxp,pca9555"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- adc@48 { +- compatible = "ti,ads1015"; +- reg = <0x48>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@4 { +- reg = <4>; +- ti,gain = <0>; +- ti,datarate = <5>; +- }; +- +- channel@5 { +- reg = <5>; +- ti,gain = <0>; +- ti,datarate = <5>; +- }; +- +- channel@6 { +- reg = <6>; +- ti,gain = <0>; +- ti,datarate = <5>; +- }; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ +- status = "disabled"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ +- status = "disabled"; +-}; +- +-&pwm4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ +- status = "disabled"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 +- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 +- >; +- }; +- +- pinctrl_pps: ppsgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-gw5910.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-gw5910.dtsi +deleted file mode 100644 +index 68e5ab2e27e2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-gw5910.dtsi ++++ /dev/null +@@ -1,664 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2019 Gateworks Corporation +- */ +- +-#include +-#include +-#include +- +-/ { +- /* these are used by bootloader for disabling nodes */ +- aliases { +- led0 = &led0; +- led1 = &led1; +- led2 = &led2; +- }; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-pb { +- label = "user_pb"; +- gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- user-pb1x { +- label = "user_pb1x"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <0>; +- }; +- +- key-erased { +- label = "key-erased"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <1>; +- }; +- +- eeprom-wp { +- label = "eeprom_wp"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <2>; +- }; +- +- tamper { +- label = "tamper"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <5>; +- }; +- +- switch-hold { +- label = "switch_hold"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <7>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led0: user1 { +- label = "user1"; +- gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led1: user2 { +- label = "user2"; +- gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ +- default-state = "off"; +- }; +- +- led2: user3 { +- label = "user3"; +- gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ +- default-state = "off"; +- }; +- }; +- +- pps { +- compatible = "pps-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pps>; +- gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_5p0v: regulator-5p0v { +- compatible = "regulator-fixed"; +- regulator-name = "5P0V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_wl: regulator-wl { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_wl>; +- compatible = "regulator-fixed"; +- regulator-name = "wl"; +- gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <100>; +- enable-active-high; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +- +-&ecspi3 { +- cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi3>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- gsc: gsc@20 { +- compatible = "gw,gsc"; +- reg = <0x20>; +- interrupt-parent = <&gpio1>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <1>; +- #size-cells = <0>; +- +- adc { +- compatible = "gw,gsc-adc"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@6 { +- gw,mode = <0>; +- reg = <0x06>; +- label = "temp"; +- }; +- +- channel@8 { +- gw,mode = <3>; +- reg = <0x08>; +- label = "vdd_bat"; +- }; +- +- channel@82 { +- gw,mode = <2>; +- reg = <0x82>; +- label = "vdd_vin"; +- gw,voltage-divider-ohms = <22100 1000>; +- gw,voltage-offset-microvolt = <800000>; +- }; +- +- channel@84 { +- gw,mode = <2>; +- reg = <0x84>; +- label = "vdd_5p0"; +- gw,voltage-divider-ohms = <22100 10000>; +- }; +- +- channel@86 { +- gw,mode = <2>; +- reg = <0x86>; +- label = "vdd_3p3"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- +- channel@88 { +- gw,mode = <2>; +- reg = <0x88>; +- label = "vdd_2p5"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- +- channel@8c { +- gw,mode = <2>; +- reg = <0x8c>; +- label = "vdd_3p0"; +- }; +- +- channel@8e { +- gw,mode = <2>; +- reg = <0x8e>; +- label = "vdd_arm"; +- }; +- +- channel@90 { +- gw,mode = <2>; +- reg = <0x90>; +- label = "vdd_soc"; +- }; +- +- channel@92 { +- gw,mode = <2>; +- reg = <0x92>; +- label = "vdd_1p5"; +- }; +- +- channel@98 { +- gw,mode = <2>; +- reg = <0x98>; +- label = "vdd_1p8"; +- }; +- +- channel@9a { +- gw,mode = <2>; +- reg = <0x9a>; +- label = "vdd_1p0"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- +- channel@9c { +- gw,mode = <2>; +- reg = <0x9c>; +- label = "vdd_an1"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- +- channel@a2 { +- gw,mode = <2>; +- reg = <0xa2>; +- label = "vdd_gsc"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- }; +- }; +- +- gsc_gpio: gpio@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gsc>; +- interrupts = <4>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- accel@19 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_accel>; +- compatible = "st,lis2de12"; +- reg = <0x19>; +- st,drdy-int-pin = <1>; +- interrupt-parent = <&gpio7>; +- interrupts = <13 0>; +- interrupt-names = "INT1"; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ +- status = "disabled"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ +- status = "disabled"; +-}; +- +-/* off-board RS232 */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-/* serial console */ +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-/* cc1352 */ +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-/* Sterling-LWB Bluetooth */ +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm4330-bt"; +- shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-/* GPS */ +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_5p0v>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-/* Sterling-LWB SDIO WiFi */ +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- vmmc-supply = <®_wl>; +- non-removable; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl_accel: accelmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 +- >; +- }; +- +- pinctrl_bten: btengrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 +- >; +- }; +- +- pinctrl_ecspi3: escpi3grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 +- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 +- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 +- MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 +- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 +- >; +- }; +- +- pinctrl_pps: ppsgrp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_reg_wl: regwlgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */ +- MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x4001b0b1 /* DIO14 */ +- MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x4001b0b1 /* DIO15 */ +- MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 /* TMS */ +- MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* TCK */ +- MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 /* TDO */ +- MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 /* TDI */ +- MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x4001b0b1 /* RST# */ +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp100mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp200mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-gw5912.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-gw5912.dtsi +deleted file mode 100644 +index 0415bcb41640..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-gw5912.dtsi ++++ /dev/null +@@ -1,606 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2019 Gateworks Corporation +- */ +- +-#include +-#include +-#include +- +-/ { +- /* these are used by bootloader for disabling nodes */ +- aliases { +- led0 = &led0; +- led1 = &led1; +- led2 = &led2; +- nand = &gpmi; +- usb0 = &usbh1; +- usb1 = &usbotg; +- }; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-pb { +- label = "user_pb"; +- gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- user-pb1x { +- label = "user_pb1x"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <0>; +- }; +- +- key-erased { +- label = "key-erased"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <1>; +- }; +- +- eeprom-wp { +- label = "eeprom_wp"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <2>; +- }; +- +- tamper { +- label = "tamper"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <5>; +- }; +- +- switch-hold { +- label = "switch_hold"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <7>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led0: user1 { +- label = "user1"; +- gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led1: user2 { +- label = "user2"; +- gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ +- default-state = "off"; +- }; +- +- led2: user3 { +- label = "user3"; +- gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ +- default-state = "off"; +- }; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- pps { +- compatible = "pps-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pps>; +- gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_vbus: regulator-5p0v { +- compatible = "regulator-fixed"; +- regulator-name = "usb_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- status = "okay"; +-}; +- +-&ecspi2 { +- cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- gsc: gsc@20 { +- compatible = "gw,gsc"; +- reg = <0x20>; +- interrupt-parent = <&gpio1>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- adc { +- compatible = "gw,gsc-adc"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@0 { +- gw,mode = <0>; +- reg = <0x00>; +- label = "temp"; +- }; +- +- channel@2 { +- gw,mode = <1>; +- reg = <0x02>; +- label = "vdd_vin"; +- }; +- +- channel@5 { +- gw,mode = <1>; +- reg = <0x05>; +- label = "vdd_3p3"; +- }; +- +- channel@8 { +- gw,mode = <1>; +- reg = <0x08>; +- label = "vdd_bat"; +- }; +- +- channel@b { +- gw,mode = <1>; +- reg = <0x0b>; +- label = "vdd_5p0"; +- }; +- +- channel@e { +- gw,mode = <1>; +- reg = <0xe>; +- label = "vdd_arm"; +- }; +- +- channel@11 { +- gw,mode = <1>; +- reg = <0x11>; +- label = "vdd_soc"; +- }; +- +- channel@14 { +- gw,mode = <1>; +- reg = <0x14>; +- label = "vdd_3p0"; +- }; +- +- channel@17 { +- gw,mode = <1>; +- reg = <0x17>; +- label = "vdd_1p5"; +- }; +- +- channel@1d { +- gw,mode = <1>; +- reg = <0x1d>; +- label = "vdd_1p8"; +- }; +- +- channel@20 { +- gw,mode = <1>; +- reg = <0x20>; +- label = "vdd_1p0"; +- }; +- +- channel@23 { +- gw,mode = <1>; +- reg = <0x23>; +- label = "vdd_2p5"; +- }; +- }; +- +- fan-controller@a { +- compatible = "gw,gsc-fan"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0a>; +- }; +- }; +- +- gsc_gpio: gpio@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gsc>; +- interrupts = <4>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- accel@19 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_accel>; +- compatible = "st,lis2de12"; +- reg = <0x19>; +- st,drdy-int-pin = <1>; +- interrupt-parent = <&gpio7>; +- interrupts = <13 0>; +- interrupt-names = "INT1"; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */ +- status = "disabled"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ +- status = "disabled"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ +- status = "disabled"; +-}; +- +-&pwm4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ +- status = "disabled"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_vbus>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- no-1-8-v; /* firmware will remove if board revision supports */ +- status = "okay"; +-}; +- +-&wdog1 { +- status = "disabled"; +-}; +- +-&wdog2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_accel: accelmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- >; +- }; +- +- pinctrl_ecspi2: escpi2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 +- MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 +- MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 +- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 +- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 +- >; +- }; +- +- pinctrl_pps: ppsgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp100mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp200mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-gw5913.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-gw5913.dtsi +deleted file mode 100644 +index 8e23cec7149e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-gw5913.dtsi ++++ /dev/null +@@ -1,498 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2019 Gateworks Corporation +- */ +- +-#include +-#include +-#include +- +-/ { +- /* these are used by bootloader for disabling nodes */ +- aliases { +- led0 = &led0; +- led1 = &led1; +- nand = &gpmi; +- usb0 = &usbh1; +- usb1 = &usbotg; +- }; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-pb { +- label = "user_pb"; +- gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- user-pb1x { +- label = "user_pb1x"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <0>; +- }; +- +- key-erased { +- label = "key-erased"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <1>; +- }; +- +- eeprom-wp { +- label = "eeprom_wp"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <2>; +- }; +- +- tamper { +- label = "tamper"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <5>; +- }; +- +- switch-hold { +- label = "switch_hold"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <7>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led0: user1 { +- label = "user1"; +- gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led1: user2 { +- label = "user2"; +- gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ +- default-state = "off"; +- }; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +- +- pps { +- compatible = "pps-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pps>; +- gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_5p0v: regulator-5p0v { +- compatible = "regulator-fixed"; +- regulator-name = "5P0V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- gsc: gsc@20 { +- compatible = "gw,gsc"; +- reg = <0x20>; +- interrupt-parent = <&gpio1>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <1>; +- #size-cells = <0>; +- +- adc { +- compatible = "gw,gsc-adc"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@6 { +- gw,mode = <0>; +- reg = <0x06>; +- label = "temp"; +- }; +- +- channel@8 { +- gw,mode = <3>; +- reg = <0x08>; +- label = "vdd_bat"; +- }; +- +- channel@82 { +- gw,mode = <2>; +- reg = <0x82>; +- label = "vdd_vin"; +- gw,voltage-divider-ohms = <22100 1000>; +- gw,voltage-offset-microvolt = <800000>; +- }; +- +- channel@84 { +- gw,mode = <2>; +- reg = <0x84>; +- label = "vdd_5p0"; +- gw,voltage-divider-ohms = <22100 10000>; +- }; +- +- channel@86 { +- gw,mode = <2>; +- reg = <0x86>; +- label = "vdd_3p3"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- +- channel@88 { +- gw,mode = <2>; +- reg = <0x88>; +- label = "vdd_2p5"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- +- channel@8c { +- gw,mode = <2>; +- reg = <0x8c>; +- label = "vdd_arm"; +- }; +- +- channel@8e { +- gw,mode = <2>; +- reg = <0x8e>; +- label = "vdd_soc"; +- }; +- +- channel@90 { +- gw,mode = <2>; +- reg = <0x90>; +- label = "vdd_1p5"; +- }; +- +- channel@92 { +- gw,mode = <2>; +- reg = <0x92>; +- label = "vdd_1p0"; +- }; +- +- channel@98 { +- gw,mode = <2>; +- reg = <0x98>; +- label = "vdd_3p0"; +- }; +- +- channel@9a { +- gw,mode = <2>; +- reg = <0x9a>; +- label = "vdd_an1"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- +- channel@a2 { +- gw,mode = <2>; +- reg = <0xa2>; +- label = "vdd_gsc"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- }; +- }; +- +- gsc_gpio: gpio@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gsc>; +- interrupts = <4>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ +- status = "disabled"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ +- status = "disabled"; +-}; +- +-&pwm4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ +- status = "disabled"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbotg { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 +- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 +- >; +- }; +- +- pinctrl_pps: ppsgrp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-hummingboard.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-hummingboard.dtsi +deleted file mode 100644 +index 2ffb21dd89f2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-hummingboard.dtsi ++++ /dev/null +@@ -1,368 +0,0 @@ +-/* +- * Copyright (C) 2013,2014 Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-#include +- +-/ { +- /* Will be filled by the bootloader */ +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0>; +- }; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- ir_recv: ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>; +- }; +- +- v_3v2: regulator-v-3v2 { +- compatible = "regulator-fixed"; +- regulator-always-on; +- regulator-max-microvolt = <3300000>; +- regulator-min-microvolt = <3300000>; +- regulator-name = "v_3v2"; +- vin-supply = <&v_5v0>; +- }; +- +- v_5v0: regulator-v-5v0 { +- compatible = "regulator-fixed"; +- regulator-always-on; +- regulator-max-microvolt = <5000000>; +- regulator-min-microvolt = <5000000>; +- regulator-name = "v_5v0"; +- }; +- +- v_sd: regulator-v-sd { +- compatible = "regulator-fixed"; +- gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard_vmmc>; +- regulator-boot-on; +- regulator-max-microvolt = <3300000>; +- regulator-min-microvolt = <3300000>; +- regulator-name = "v_sd"; +- startup-delay-us = <1000>; +- vin-supply = <&v_3v2>; +- }; +- +- v_usb2: regulator-v-usb2 { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>; +- regulator-max-microvolt = <5000000>; +- regulator-min-microvolt = <5000000>; +- regulator-name = "v_usb2"; +- vin-supply = <&v_5v0>; +- }; +- +- v_usb1: regulator-v-usb1 { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>; +- regulator-max-microvolt = <5000000>; +- regulator-min-microvolt = <5000000>; +- regulator-name = "v_usb1"; +- vin-supply = <&v_5v0>; +- }; +- +- audio: sound-sgtl5000 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "On-board Codec"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sound_codec>; +- simple-audio-card,frame-master = <&sound_codec>; +- simple-audio-card,widgets = +- "Microphone", "Headphone Jack", +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "MIC_IN", "Headphone Jack", +- "Headphone Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- +- sound_cpu: simple-audio-card,cpu { +- sound-dai = <&ssi1>; +- }; +- +- sound_codec: simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- }; +- }; +- +- sound-spdif { +- compatible = "fsl,imx-audio-spdif"; +- model = "On-board SPDIF"; +- /* IMX6 doesn't implement this yet */ +- spdif-controller = <&spdif>; +- spdif-out; +- }; +-}; +- +-&audmux { +- status = "okay"; +- +- ssi1 { +- fsl,audmux-port = <0>; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_SYN | +- IMX_AUDMUX_V2_PTCR_TFSEL(4) | +- IMX_AUDMUX_V2_PTCR_TCSEL(4) | +- IMX_AUDMUX_V2_PTCR_TFSDIR | +- IMX_AUDMUX_V2_PTCR_TCLKDIR) +- IMX_AUDMUX_V2_PDCR_RXDSEL(4) +- >; +- }; +- +- pins5 { +- fsl,audmux-port = <4>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN +- IMX_AUDMUX_V2_PDCR_RXDSEL(0) +- >; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard_flexcan1>; +- status = "okay"; +-}; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard_hdmi>; +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard_i2c1>; +- status = "okay"; +- +- /* Pro baseboard model */ +- rtc@68 { +- compatible = "nxp,pcf8523"; +- reg = <0x68>; +- }; +- +- /* Pro baseboard model */ +- sgtl5000: codec@a { +- clocks = <&clks IMX6QDL_CLK_CKO>; +- compatible = "fsl,sgtl5000"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard_sgtl5000>; +- #sound-dai-cells = <0>; +- reg = <0x0a>; +- VDDA-supply = <&v_3v2>; +- VDDIO-supply = <&v_3v2>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard_i2c2>; +- status = "okay"; +-}; +- +-&iomuxc { +- hummingboard { +- pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { +- fsl,pins = < +- MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000 +- MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000 +- >; +- }; +- +- pinctrl_hummingboard_gpio3_5: hummingboard-gpio3_5 { +- fsl,pins = < +- MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 +- >; +- }; +- +- pinctrl_hummingboard_hdmi: hummingboard-hdmi { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 +- >; +- }; +- +- pinctrl_hummingboard_i2c1: hummingboard-i2c1 { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_hummingboard_i2c2: hummingboard-i2c2 { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_hummingboard_pcie_reset: hummingboard-pcie-reset { +- fsl,pins = < +- MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 +- >; +- }; +- +- pinctrl_hummingboard_pwm1: pwm1grp { +- fsl,pins = ; +- }; +- +- pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 +- MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 +- MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 +- MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 +- MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 +- >; +- }; +- +- pinctrl_hummingboard_spdif: hummingboard-spdif { +- fsl,pins = ; +- }; +- +- pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus { +- fsl,pins = ; +- }; +- +- pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id { +- /* +- * We want it pulled down for a fixed host connection. +- */ +- fsl,pins = ; +- }; +- +- pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus { +- fsl,pins = ; +- }; +- +- pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux { +- fsl,pins = < +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 +- >; +- }; +- +- pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 +- >; +- }; +- pinctrl_hummingboard_vmmc: hummingboard-vmmc { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 +- >; +- }; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard_pcie_reset>; +- reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard_pwm1>; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&spdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard_spdif>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&usbh1 { +- disable-over-current; +- vbus-supply = <&v_usb2>; +- status = "okay"; +-}; +- +-&usbotg { +- disable-over-current; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>; +- vbus-supply = <&v_usb1>; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &pinctrl_hummingboard_usdhc2_aux +- &pinctrl_hummingboard_usdhc2 +- >; +- vmmc-supply = <&v_sd>; +- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&vcc_3v3 { +- vin-supply = <&v_3v2>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-hummingboard2-emmc.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-hummingboard2-emmc.dtsi +deleted file mode 100644 +index f400405381a7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-hummingboard2-emmc.dtsi ++++ /dev/null +@@ -1,72 +0,0 @@ +-/* +- * Device Tree file for SolidRun HummingBoard2 +- * Copyright (C) 2015 Rabeeh Khoury +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-&iomuxc { +- hummingboard2 { +- pinctrl_hummingboard2_usdhc3: hummingboard2-usdhc3 { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 +- >; +- }; +- }; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard2_usdhc3>; +- vmmc-supply = <&v_3v2>; +- vqmmc-supply = <&v_3v2>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-hummingboard2.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-hummingboard2.dtsi +deleted file mode 100644 +index eb1ad28946d3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-hummingboard2.dtsi ++++ /dev/null +@@ -1,577 +0,0 @@ +-/* +- * Copyright (C) 2015 Rabeeh Khoury +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-#include +- +-/ { +- /* Will be filled by the bootloader */ +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0>; +- }; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- ir_recv: ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio7 9 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard2_gpio7_9>; +- linux,rc-map-name = "rc-rc6-mce"; +- }; +- +- v_3v2: regulator-v-3v2 { +- compatible = "regulator-fixed"; +- regulator-always-on; +- regulator-max-microvolt = <3300000>; +- regulator-min-microvolt = <3300000>; +- regulator-name = "v_3v2"; +- }; +- +- v_5v0: regulator-v-5v0 { +- compatible = "regulator-fixed"; +- regulator-always-on; +- regulator-max-microvolt = <5000000>; +- regulator-min-microvolt = <5000000>; +- regulator-name = "v_5v0"; +- }; +- +- vcc_1p8: regulator-vcc-1p8 { +- compatible = "regulator-fixed"; +- regulator-always-on; +- regulator-max-microvolt = <1800000>; +- regulator-min-microvolt = <1800000>; +- regulator-name = "vcc_1p8"; +- vin-supply = <&v_3v2>; +- }; +- +- v_sd: regulator-v-sd { +- compatible = "regulator-fixed"; +- gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard2_vmmc>; +- regulator-boot-on; +- regulator-max-microvolt = <3300000>; +- regulator-min-microvolt = <3300000>; +- regulator-name = "v_sd"; +- startup-delay-us = <1000>; +- vin-supply = <&v_3v2>; +- }; +- +- v_usb1: regulator-v-usb1 { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard2_usbotg_vbus>; +- regulator-always-on; +- regulator-max-microvolt = <5000000>; +- regulator-min-microvolt = <5000000>; +- regulator-name = "v_usb1"; +- vin-supply = <&v_5v0>; +- }; +- +- v_usb2: regulator-v-usb2 { +- /* USB hub port 1 */ +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard2_usbh1_vbus>; +- regulator-always-on; +- regulator-max-microvolt = <5000000>; +- regulator-min-microvolt = <5000000>; +- regulator-name = "v_usb2"; +- vin-supply = <&v_5v0>; +- }; +- +- v_usb3: regulator-v-usb3 { +- /* USB hub port 3 */ +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard2_usbh2_vbus>; +- regulator-always-on; +- regulator-max-microvolt = <5000000>; +- regulator-min-microvolt = <5000000>; +- regulator-name = "v_usb3"; +- vin-supply = <&v_5v0>; +- }; +- +- v_usb4: regulator-v-usb4 { +- /* USB hub port 4 */ +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard2_usbh3_vbus>; +- regulator-always-on; +- regulator-max-microvolt = <5000000>; +- regulator-min-microvolt = <5000000>; +- regulator-name = "v_usb4"; +- vin-supply = <&v_5v0>; +- }; +- +- audio: sound-sgtl5000 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "On-board Codec"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sound_codec>; +- simple-audio-card,frame-master = <&sound_codec>; +- simple-audio-card,widgets = +- "Microphone", "Mic Jack", +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- +- sound_cpu: simple-audio-card,cpu { +- sound-dai = <&ssi1>; +- }; +- +- sound_codec: simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- }; +- }; +-}; +- +-&audmux { +- status = "okay"; +- +- ssi1 { +- fsl,audmux-port = <0>; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_SYN | +- IMX_AUDMUX_V2_PTCR_TFSEL(4) | +- IMX_AUDMUX_V2_PTCR_TCSEL(4) | +- IMX_AUDMUX_V2_PTCR_TFSDIR | +- IMX_AUDMUX_V2_PTCR_TCLKDIR) +- IMX_AUDMUX_V2_PDCR_RXDSEL(4) +- >; +- }; +- +- pins5 { +- fsl,audmux-port = <4>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN +- IMX_AUDMUX_V2_PDCR_RXDSEL(0) +- >; +- }; +-}; +- +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard2_ecspi2>; +- cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard2_hdmi>; +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard2_i2c1>; +- status = "okay"; +- +- pcf8523: rtc@68 { +- compatible = "nxp,pcf8523"; +- reg = <0x68>; +- }; +- +- sgtl5000: codec@a { +- clocks = <&clks IMX6QDL_CLK_CKO>; +- compatible = "fsl,sgtl5000"; +- #sound-dai-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard2_sgtl5000>; +- reg = <0x0a>; +- VDDA-supply = <&v_3v2>; +- VDDD-supply = <&vcc_1p8>; +- VDDIO-supply = <&v_3v2>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard2_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard2_i2c3>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- hummingboard2 { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- /* +- * 36 pin headers GPIO description. The pins +- * numbering as following - +- * +- * 3.2v 5v 74 75 +- * 73 72 71 70 +- * 69 68 67 66 +- * +- * 77 78 79 76 +- * 65 64 61 60 +- * 53 52 51 50 +- * 49 48 166 132 +- * 95 94 90 91 +- * GND 54 24 204 +- * +- * The GPIO numbers can be extracted using +- * signal name from below. +- * Example - +- * MX6QDL_PAD_EIM_DA10__GPIO3_IO10 is +- * GPIO(3,10) which is (3-1)*32+10 = gpio 74 +- * +- * i.e. The mapping of GPIO(X,Y) to Linux gpio +- * number is : gpio number = (X-1) * 32 + Y +- */ +- /* DI1_PIN15 */ +- MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x400130b1 +- /* DI1_PIN02 */ +- MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x400130b1 +- /* DISP1_DATA00 */ +- MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1 +- /* DISP1_DATA01 */ +- MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1 +- /* DISP1_DATA02 */ +- MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1 +- /* DISP1_DATA03 */ +- MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1 +- /* DISP1_DATA04 */ +- MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x400130b1 +- /* DISP1_DATA05 */ +- MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x400130b1 +- /* DISP1_DATA06 */ +- MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1 +- /* DISP1_DATA07 */ +- MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x400130b1 +- /* DI1_D0_CS */ +- MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x400130b1 +- /* DI1_D1_CS */ +- MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x400130b1 +- /* DI1_PIN01 */ +- MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x400130b1 +- /* DI1_PIN03 */ +- MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x400130b1 +- /* DISP1_DATA08 */ +- MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x400130b1 +- /* DISP1_DATA09 */ +- MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x400130b1 +- /* DISP1_DATA10 */ +- MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x400130b1 +- /* DISP1_DATA11 */ +- MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x400130b1 +- /* DISP1_DATA12 */ +- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x400130b1 +- /* DISP1_DATA13 */ +- MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x400130b1 +- /* DISP1_DATA14 */ +- MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x400130b1 +- /* DISP1_DATA15 */ +- MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x400130b1 +- /* DISP1_DATA16 */ +- MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x400130b1 +- /* DISP1_DATA17 */ +- MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x400130b1 +- /* DISP1_DATA18 */ +- MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x400130b1 +- /* DISP1_DATA19 */ +- MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x400130b1 +- /* DISP1_DATA20 */ +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x400130b1 +- /* DISP1_DATA21 */ +- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x400130b1 +- /* DISP1_DATA22 */ +- MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x400130b1 +- /* DISP1_DATA23 */ +- MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400130b1 +- /* DI1_DISP_CLK */ +- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x400130b1 +- /* SPDIF_IN */ +- MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x400130b1 +- /* SPDIF_OUT */ +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x400130b1 +- +- /* MikroBUS GPIO pin number 10 */ +- MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1 +- >; +- }; +- +- pinctrl_hummingboard2_ecspi2: hummingboard2-ecspi2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 +- MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 +- MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 +- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 /* CS */ +- >; +- }; +- +- pinctrl_hummingboard2_gpio7_9: hummingboard2-gpio7_9 { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x80000000 +- >; +- }; +- +- pinctrl_hummingboard2_hdmi: hummingboard2-hdmi { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 +- >; +- }; +- +- pinctrl_hummingboard2_i2c1: hummingboard2-i2c1 { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_hummingboard2_i2c2: hummingboard2-i2c2 { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_hummingboard2_i2c3: hummingboard2-i2c3 { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_hummingboard2_mipi: hummingboard2_mipi { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x4001b8b1 +- MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x4001b8b1 +- MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 +- >; +- }; +- +- pinctrl_hummingboard2_pcie_reset: hummingboard2-pcie-reset { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b1 +- >; +- }; +- +- pinctrl_hummingboard2_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_hummingboard2_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_hummingboard2_sgtl5000: hummingboard2-sgtl5000 { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 +- MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 +- MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 +- MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 +- MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 +- >; +- }; +- +- pinctrl_hummingboard2_usbh1_vbus: hummingboard2-usbh1-vbus { +- fsl,pins = ; +- }; +- +- pinctrl_hummingboard2_usbh2_vbus: hummingboard2-usbh2-vbus { +- fsl,pins = ; +- }; +- +- pinctrl_hummingboard2_usbh3_vbus: hummingboard2-usbh3-vbus { +- fsl,pins = ; +- }; +- +- pinctrl_hummingboard2_usbotg_id: hummingboard2-usbotg-id { +- /* +- * We want it pulled down for a fixed host connection. +- */ +- fsl,pins = ; +- }; +- +- pinctrl_hummingboard2_usbotg_vbus: hummingboard2-usbotg-vbus { +- fsl,pins = ; +- }; +- +- pinctrl_hummingboard2_usdhc2_aux: hummingboard2-usdhc2-aux { +- fsl,pins = < +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 +- MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 +- >; +- }; +- +- pinctrl_hummingboard2_usdhc2: hummingboard2-usdhc2 { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 +- >; +- }; +- +- pinctrl_hummingboard2_usdhc2_100mhz: hummingboard2-usdhc2-100mhz { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9 +- >; +- }; +- +- pinctrl_hummingboard2_usdhc2_200mhz: hummingboard2-usdhc2-200mhz { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9 +- >; +- }; +- +- pinctrl_hummingboard2_vmmc: hummingboard2-vmmc { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 +- >; +- }; +- +- pinctrl_hummingboard2_uart3: hummingboard2-uart3 { +- fsl,pins = < +- MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x40013000 +- >; +- }; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard2_pcie_reset>; +- reset-gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard2_pwm1>; +- status = "okay"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard2_pwm3>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&usbh1 { +- disable-over-current; +- status = "okay"; +-}; +- +-&usbotg { +- disable-over-current; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard2_usbotg_id>; +- vbus-supply = <&v_usb1>; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = < +- &pinctrl_hummingboard2_usdhc2_aux +- &pinctrl_hummingboard2_usdhc2 +- >; +- pinctrl-1 = < +- &pinctrl_hummingboard2_usdhc2_aux +- &pinctrl_hummingboard2_usdhc2_100mhz +- >; +- pinctrl-2 = < +- &pinctrl_hummingboard2_usdhc2_aux +- &pinctrl_hummingboard2_usdhc2_200mhz +- >; +- vmmc-supply = <&v_sd>; +- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hummingboard2_uart3>; +- status = "okay"; +-}; +- +-&vcc_3v3 { +- vin-supply = <&v_3v2>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-icore-1.5.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-icore-1.5.dtsi +deleted file mode 100644 +index 0fd7f2e24d9c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-icore-1.5.dtsi ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2018 Jacopo Mondi +- */ +- +-#include "imx6qdl-icore.dtsi" +- +-&iomuxc { +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 +- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 +- >; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- clocks = <&clks IMX6QDL_CLK_ENET>, +- <&clks IMX6QDL_CLK_ENET>, +- <&clks IMX6QDL_CLK_ENET_REF>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-icore-rqs.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-icore-rqs.dtsi +deleted file mode 100644 +index a4217f564a53..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-icore-rqs.dtsi ++++ /dev/null +@@ -1,466 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright (C) 2015 Amarula Solutions B.V. +- * Copyright (C) 2015 Engicam S.r.l. +- */ +- +-#include +-#include +-#include +- +-/ { +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_2p5v: regulator-2p5v { +- compatible = "regulator-fixed"; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_sd3_vmmc: regulator-sd3-vmmc { +- compatible = "regulator-fixed"; +- regulator-name = "P3V3_SD3_SWITCHED"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; +- enable-active-high; +- }; +- +- reg_sd4_vmmc: regulator-sd4-vmmc { +- compatible = "regulator-fixed"; +- regulator-name = "P3V3_SD4_SWITCHED"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_usb_h1_vbus: regulator-usb-h1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- usb_hub: usb-hub { +- compatible = "smsc,usb3503a"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbhub>; +- reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; +- clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>; +- clock-names = "refclk"; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "imx6qdl-icore-rqs-sgtl5000"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&dailink_master>; +- simple-audio-card,frame-master = <&dailink_master>; +- simple-audio-card,widgets = +- "Microphone", "Mic Jack", +- "Headphone", "Headphone Jack", +- "Line", "Line In Jack", +- "Speaker", "Line Out Jack", +- "Speaker", "Ext Spk"; +- simple-audio-card,routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- +- simple-audio-card,cpu { +- sound-dai = <&ssi1>; +- }; +- +- dailink_master: simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +- +- audmux_ssi1 { +- fsl,audmux-port = ; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_TFSDIR | +- IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | +- IMX_AUDMUX_V2_PTCR_TCLKDIR | +- IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | +- IMX_AUDMUX_V2_PTCR_SYN) +- IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) +- >; +- }; +- +- audmux_aud4 { +- fsl,audmux-port = ; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN +- IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) +- >; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- xceiver-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can2>; +- xceiver-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-handle = <ð_phy>; +- phy-mode = "rgmii"; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- eth_phy: ethernet-phy@0 { +- reg = <0x0>; +- rxc-skew-ps = <1140>; +- txc-skew-ps = <1140>; +- txen-skew-ps = <600>; +- rxdv-skew-ps = <240>; +- rxd0-skew-ps = <420>; +- rxd1-skew-ps = <600>; +- rxd2-skew-ps = <420>; +- rxd3-skew-ps = <240>; +- txd0-skew-ps = <60>; +- txd1-skew-ps = <60>; +- txd2-skew-ps = <60>; +- txd3-skew-ps = <240>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- sgtl5000: codec@a { +- #sound-dai-cells = <0>; +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_3p3v>; +- VDDD-supply = <®_1p8v>; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&ssi1 { +- fsl,mode = "i2s-slave"; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- disable-over-current; +- clocks = <&clks IMX6QDL_CLK_USBOH3>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- no-1-8-v; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- vmcc-supply = <®_sd3_vmmc>; +- cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- no-1-8-v; +- status = "okay"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- pinctrl-1 = <&pinctrl_usdhc4_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc4_200mhz>; +- vmcc-supply = <®_sd4_vmmc>; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 +- MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 +- MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 +- MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 +- >; +- }; +- +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020 +- >; +- }; +- +- pinctrl_can2: can2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020 +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f059 /* PCIe Reset */ +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbhub: usbhubgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1f059 /* HUB USB Reset */ +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070 +- MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1f059 /* CD */ +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f059 /* PWR */ +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B1 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B1 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B1 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B1 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B1 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B1 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9 +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17070 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10070 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070 +- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070 +- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070 +- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070 +- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070 +- >; +- }; +- +- pinctrl_usdhc4_100mhz: usdhc4grp_100mhz { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170B1 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100B1 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170B1 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170B1 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170B1 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170B1 +- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170B1 +- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170B1 +- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170B1 +- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170B1 +- >; +- }; +- +- pinctrl_usdhc4_200mhz: usdhc4grp_200mhz { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170F9 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100F9 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170F9 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170F9 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170F9 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170F9 +- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170F9 +- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170F9 +- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170F9 +- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170F9 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-icore.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-icore.dtsi +deleted file mode 100644 +index 23c318d9636f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-icore.dtsi ++++ /dev/null +@@ -1,431 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright (C) 2016 Amarula Solutions B.V. +- * Copyright (C) 2016 Engicam S.r.l. +- */ +- +-#include +-#include +-#include +- +-/ { +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +- +- chosen { +- stdout-path = &uart4; +- }; +- +- backlight_lvds: backlight-lvds { +- compatible = "pwm-backlight"; +- pwms = <&pwm3 0 100000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_2p5v: regulator-2p5v { +- compatible = "regulator-fixed"; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_usb_h1_vbus: regulator-usb-h1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- rmii_clk: clock-rmii-clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; /* 25MHz for example */ +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "imx6qdl-icore-sgtl5000"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&dailink_master>; +- simple-audio-card,frame-master = <&dailink_master>; +- simple-audio-card,widgets = +- "Microphone", "Mic Jack", +- "Headphone", "Headphone Jack", +- "Line", "Line In Jack", +- "Speaker", "Line Out Jack", +- "Speaker", "Ext Spk"; +- simple-audio-card,routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- +- simple-audio-card,cpu { +- sound-dai = <&ssi1>; +- }; +- +- dailink_master: simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +- +- +- audmux_ssi1 { +- fsl,audmux-port = ; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_TFSDIR | +- IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | +- IMX_AUDMUX_V2_PTCR_TCLKDIR | +- IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | +- IMX_AUDMUX_V2_PTCR_SYN) +- IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) +- >; +- }; +- +- audmux_aud4 { +- fsl,audmux-port = ; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN +- IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) +- >; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- xceiver-supply = <®_3p3v>; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- xceiver-supply = <®_3p3v>; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>; +- phy-mode = "rmii"; +- phy-handle = <ð_phy>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- eth_phy: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; +- reset-assert-us = <4000>; +- reset-deassert-us = <4000>; +- }; +- }; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- nand-on-flash-bbt; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- ov5640: camera@3c { +- compatible = "ovti,ov5640"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ov5640>; +- reg = <0x3c>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- clock-names = "xclk"; +- DOVDD-supply = <®_1p8v>; +- AVDD-supply = <®_3p3v>; +- DVDD-supply = <®_3p3v>; +- powerdown-gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>; +- status = "disabled"; +- +- port { +- ov5640_to_mipi_csi2: endpoint { +- remote-endpoint = <&mipi_csi2_in>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- }; +- }; +- }; +- +- sgtl5000: codec@a { +- #sound-dai-cells = <0>; +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_3p3v>; +- VDDD-supply = <®_1p8v>; +- }; +-}; +- +-&mipi_csi { +- status = "disabled"; +- +- port@0 { +- reg = <0>; +- +- mipi_csi2_in: endpoint { +- remote-endpoint = <&ov5640_to_mipi_csi2>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- }; +- }; +-}; +- +-&pwm3 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "okay"; +-}; +- +-&ssi1 { +- fsl,mode = "i2s-slave"; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- no-1-8-v; +- non-removable; +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 +- MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 +- MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 +- MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b1 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 +- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020 +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_ov5640: ov5640grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070 +- MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-kontron-samx6i.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-kontron-samx6i.dtsi +deleted file mode 100644 +index b167b33bd108..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-kontron-samx6i.dtsi ++++ /dev/null +@@ -1,815 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright 2017 (C) Priit Laes +- * Copyright 2018 (C) Pengutronix, Michael Grzeschik +- * Copyright 2019 (C) Pengutronix, Marco Felsch +- * +- * Based on initial work by Nikita Yushchenko +- */ +- +-#include +-#include +- +-/ { +- reg_1p0v_s0: regulator-1p0v-s0 { +- compatible = "regulator-fixed"; +- regulator-name = "V_1V0_S0"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <®_smarc_suppy>; +- }; +- +- reg_1p35v_vcoredig_s5: regulator-1p35v-vcoredig-s5 { +- compatible = "regulator-fixed"; +- regulator-name = "V_1V35_VCOREDIG_S5"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <®_3p3v_s5>; +- }; +- +- reg_1p8v_s5: regulator-1p8v-s5 { +- compatible = "regulator-fixed"; +- regulator-name = "V_1V8_S5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <®_3p3v_s5>; +- }; +- +- reg_3p3v_s0: regulator-3p3v-s0 { +- compatible = "regulator-fixed"; +- regulator-name = "V_3V3_S0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <®_3p3v_s5>; +- }; +- +- reg_3p3v_s0: regulator-3p3v-s0 { +- compatible = "regulator-fixed"; +- regulator-name = "V_3V3_S0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <®_3p3v_s5>; +- }; +- +- reg_3p3v_s5: regulator-3p3v-s5 { +- compatible = "regulator-fixed"; +- regulator-name = "V_3V3_S5"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <®_smarc_suppy>; +- }; +- +- reg_smarc_lcdbklt: regulator-smarc-lcdbklt { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcdbklt_en>; +- regulator-name = "LCD_BKLT_EN"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_smarc_lcdvdd: regulator-smarc-lcdvdd { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcdvdd_en>; +- regulator-name = "LCD_VDD_EN"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_smarc_rtc: regulator-smarc-rtc { +- compatible = "regulator-fixed"; +- regulator-name = "V_IN_RTC_BATT"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* Module supply range can be 3.00V ... 5.25V */ +- reg_smarc_suppy: regulator-smarc-supply { +- compatible = "regulator-fixed"; +- regulator-name = "V_IN_WIDE"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- lcd: lcd { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx-parallel-display"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd>; +- status = "disabled"; +- +- port@0 { +- reg = <0>; +- +- lcd_in: endpoint { +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lcd_out: endpoint { +- }; +- }; +- }; +- +- lcd_backlight: lcd-backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm4 0 5000000 0>; +- pwm-names = "LCD_BKLT_PWM"; +- +- brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; +- default-brightness-level = <4>; +- +- power-supply = <®_smarc_lcdbklt>; +- status = "disabled"; +- }; +- +- i2c_intern: i2c-gpio-intern { +- compatible = "i2c-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c_gpio_intern>; +- sda-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c_lcd: i2c-gpio-lcd { +- compatible = "i2c-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c_gpio_lcd>; +- sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio1 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c_cam: i2c-gpio-cam { +- compatible = "i2c-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c_gpio_cam>; +- sda-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +-}; +- +-/* I2S0, I2S1 */ +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- +- audmux_ssi1 { +- fsl,audmux-port = ; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT3) | +- IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT3) | +- IMX_AUDMUX_V2_PTCR_SYN | +- IMX_AUDMUX_V2_PTCR_TFSDIR | +- IMX_AUDMUX_V2_PTCR_TCLKDIR) +- IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT3) +- >; +- }; +- +- audmux_adu3 { +- fsl,audmux-port = ; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN +- IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) +- >; +- }; +- +- audmux_ssi2 { +- fsl,audmux-port = ; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | +- IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | +- IMX_AUDMUX_V2_PTCR_SYN | +- IMX_AUDMUX_V2_PTCR_TFSDIR | +- IMX_AUDMUX_V2_PTCR_TCLKDIR) +- IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) +- >; +- }; +- +- audmux_adu4 { +- fsl,audmux-port = ; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN +- IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT2_SSI1) +- >; +- }; +-}; +- +-/* CAN0 */ +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +-}; +- +-/* CAN1 */ +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +-}; +- +-/* SPI1 */ +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, +- <&gpio2 27 GPIO_ACTIVE_LOW>; +-}; +- +-/* SPI0 */ +-&ecspi4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi4>; +- cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>, +- <&gpio3 29 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- /* default boot source: workaround #1 for errata ERR006282 */ +- smarc_flash: spi-flash@0 { +- compatible = "winbond,w25q16dw", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- }; +-}; +- +-/* GBE */ +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii"; +- phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; +-}; +- +-&i2c_intern { +- pmic@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- reg_v_core_s0: sw1ab { +- regulator-name = "V_CORE_S0"; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_vddsoc_s0: sw1c { +- regulator-name = "V_VDDSOC_S0"; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_3p15v_s0: sw2 { +- regulator-name = "V_3V15_S0"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* sw3a/b is used in dual mode, but driver does not +- * support it. Although, there's no need to control +- * DDR power - so just leaving dummy entries for sw3a +- * and sw3b for now. +- */ +- sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_1p8v_s0: sw4 { +- regulator-name = "V_1V8_S0"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* Regulator for USB */ +- reg_5p0v_s0: swbst { +- regulator-name = "V_5V0_S0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- regulator-boot-on; +- }; +- +- reg_vsnvs: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_vrefddr: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* +- * Per schematics, of all VGEN's, only VGEN5 has some +- * usage ... but even that - over DNI resistor +- */ +- vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_2p5v_s0: vgen5 { +- regulator-name = "V_2V5_S0"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +- }; +-}; +- +-/* I2C_GP */ +-&i2c1 { +- clock-frequency = <375000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +-}; +- +-/* HDMI_CTRL */ +-&i2c2 { +- clock-frequency = <375000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +-}; +- +-/* I2C_PM */ +-&i2c3 { +- clock-frequency = <375000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- smarc_eeprom: eeprom@50 { +- compatible = "atmel,24c32"; +- reg = <0x50>; +- pagesize = <32>; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mgmt_gpios &pinctrl_gpio>; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- +- MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 +- MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 +- MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 +- MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 +- +- /* AUDIO MCLK */ +- MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x000b0 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 +- MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 +- MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 +- +- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 /* CS0 */ +- MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 /* CS1 */ +- >; +- }; +- +- pinctrl_ecspi4: ecspi4grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 +- +- /* SPI_IMX_CS2# - connected to internal flash */ +- MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0 +- /* SPI_IMX_CS0# - connected to SMARC SPI0_CS0# */ +- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 +- MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_gpio: gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 /* GPIO0 / CAM0_PWR# */ +- MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 /* GPIO1 / CAM1_PWR# */ +- MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 /* GPIO2 / CAM0_RST# */ +- MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 /* GPIO3 / CAM1_RST# */ +- MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 /* GPIO4 / HDA_RST# */ +- MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 /* GPIO5 / PWM_OUT */ +- MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 /* GPIO6 / TACHIN */ +- MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 /* GPIO7 / PCAM_FLD */ +- MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b0 /* GPIO8 / CAN0_ERR# */ +- MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b0 /* GPIO9 / CAN1_ERR# */ +- MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b0 /* GPIO10 */ +- MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b0 /* GPIO11 */ +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +- +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */ +- >; +- }; +- +- pinctrl_i2c_gpio_cam: i2c-gpiocamgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* SCL */ +- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* SDA */ +- >; +- }; +- +- pinctrl_i2c_gpio_intern: i2c-gpiointerngrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* SCL */ +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* SDA */ +- >; +- }; +- +- pinctrl_i2c_gpio_lcd: i2c-gpiolcdgrp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 /* SCL */ +- MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 /* SDA */ +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_lcd: lcdgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f1 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f1 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f1 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f1 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f1 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f1 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f1 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f1 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f1 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f1 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f1 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f1 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f1 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f1 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f1 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f1 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f1 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f1 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f1 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f1 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f1 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f1 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f1 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f1 +- +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f1 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f1 /* DE */ +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f1 /* HSYNC */ +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f1 /* VSYNC */ +- >; +- }; +- +- pinctrl_lcdbklt_en: lcdbkltengrp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b1 +- >; +- }; +- +- pinctrl_lcdvdd_en: lcdvddengrp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 +- >; +- }; +- +- pinctrl_mipi_csi: mipi-csigrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x000b0 /* CSI0/1 MCLK */ +- >; +- }; +- +- pinctrl_mgmt_gpios: mgmt-gpiosgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 /* LID# */ +- MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x1b0b0 /* SLEEP# */ +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* CHARGING# */ +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* CHARGER_PRSNT# */ +- MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 /* CARRIER_STBY# */ +- MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* BATLOW# */ +- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 /* TEST# */ +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 /* VDD_IO_SEL_D# */ +- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* POWER_BTN# */ +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 /* PCI_A_PRSNT# */ +- MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 /* RST_PCIE_A# */ +- MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* PCIE_WAKE# */ +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0 +- /* power, oc muxed but not used by the driver */ +- MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 /* USB power */ +- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 /* USB OC */ +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x17059 +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- +- MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* CD */ +- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* WP */ +- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PWR_EN */ +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 +- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 +- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 +- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +- >; +- }; +- +- pinctrl_wdog1: wdog1rp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 +- >; +- }; +-}; +- +-&mipi_csi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mipi_csi>; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>; +- reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; +-}; +- +-/* LCD_BKLT_PWM */ +-&pwm4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +-}; +- +-®_arm { +- vin-supply = <®_v_core_s0>; +-}; +- +-®_pu { +- vin-supply = <®_vddsoc_s0>; +-}; +- +-®_soc { +- vin-supply = <®_vddsoc_s0>; +-}; +- +-/* SER0 */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; +-}; +- +-/* SER1 */ +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +-}; +- +-/* SER2 */ +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- uart-has-rtscts; +-}; +- +-/* SER3 */ +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +-}; +- +-/* USB0 */ +-&usbotg { +- /* +- * no 'imx6-usb-charger-detection' +- * since USB_OTG_CHD_B pin is not wired +- */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +-}; +- +-/* USB1/2 via hub */ +-&usbh1 { +- vbus-supply = <®_5p0v_s0>; +-}; +- +-/* SDIO */ +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- no-1-8-v; +-}; +- +-/* SDMMC */ +-&usdhc4 { +- /* Internal eMMC, optional on some boards */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <8>; +- no-sdio; +- no-sd; +- non-removable; +- vmmc-supply = <®_3p3v_s0>; +- vqmmc-supply = <®_1p8v_s0>; +-}; +- +-&wdog1 { +- /* CPLD is feeded by watchdog (hardwired) */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog1>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-nit6xlite.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-nit6xlite.dtsi +deleted file mode 100644 +index ac34709e9741..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-nit6xlite.dtsi ++++ /dev/null +@@ -1,582 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright 2015 Boundary Devices, Inc. +- */ +-#include +-#include +- +-/ { +- chosen { +- stdout-path = &uart2; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_2p5v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_wlan_vmmc: regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wlan_vmmc>; +- regulator-name = "reg_wlan_vmmc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio6 7 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <70000>; +- enable-active-high; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- home { +- label = "Home"; +- gpios = <&gpio7 13 IRQ_TYPE_LEVEL_LOW>; +- linux,code = <102>; +- }; +- +- back { +- label = "Back"; +- gpios = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>; +- linux,code = <158>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds>; +- +- j14-pin1 { +- gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; +- retain-state-suspended; +- default-state = "off"; +- }; +- +- j14-pin3 { +- gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; +- retain-state-suspended; +- default-state = "off"; +- }; +- +- j14-pins8-9 { +- gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; +- retain-state-suspended; +- default-state = "off"; +- }; +- +- j46-pin2 { +- gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; +- retain-state-suspended; +- default-state = "off"; +- }; +- +- j46-pin3 { +- gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; +- retain-state-suspended; +- default-state = "off"; +- }; +- }; +- +- backlight-lcd { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- power-supply = <®_3p3v>; +- status = "okay"; +- }; +- +- backlight_lvds0: backlight-lvds0 { +- compatible = "pwm-backlight"; +- pwms = <&pwm4 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- power-supply = <®_3p3v>; +- status = "okay"; +- }; +- +- panel-lvds0 { +- compatible = "hannstar,hsd100pxn1"; +- backlight = <&backlight_lvds0>; +- +- port { +- panel_in_lvds0: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +- +- sound { +- compatible = "fsl,imx6dl-nit6xlite-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "imx6dl-nit6xlite-sgtl5000"; +- ssi-controller = <&ssi1>; +- audio-codec = <&codec>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <3>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, +- <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- flash: m25p80@0 { +- compatible = "microchip,sst25vf016b"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii"; +- phy-handle = <ðphy>; +- phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; +- interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, +- <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; +- fsl,err006687-workaround-present; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy { +- compatible = "ethernet-phy-ieee802.3-c22"; +- txen-skew-ps = <0>; +- txc-skew-ps = <3000>; +- rxdv-skew-ps = <0>; +- rxc-skew-ps = <3000>; +- rxd0-skew-ps = <0>; +- rxd1-skew-ps = <0>; +- rxd2-skew-ps = <0>; +- rxd3-skew-ps = <0>; +- txd0-skew-ps = <0>; +- txd1-skew-ps = <0>; +- txd2-skew-ps = <0>; +- txd3-skew-ps = <0>; +- }; +- }; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- codec: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sgtl5000>; +- reg = <0x0a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_3p3v>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- touchscreen@4 { +- compatible = "eeti,egalax_ts"; +- reg = <0x04>; +- interrupt-parent = <&gpio1>; +- interrupts = <9 IRQ_TYPE_EDGE_FALLING>; +- wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- }; +- +- touchscreen@38 { +- compatible = "edt,edt-ft5x06"; +- reg = <0x38>; +- interrupt-parent = <&gpio1>; +- interrupts = <9 IRQ_TYPE_EDGE_FALLING>; +- wakeup-source; +- }; +- +- rtc@6f { +- compatible = "isil,isl1208"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rtc>; +- reg = <0x6f>; +- interrupts-extended = <&gpio2 26 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_j10>; +- pinctrl-1 = <&pinctrl_j28>; +- +- imx6dl-nit6xlite { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- /* Phy reset */ +- MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 +- >; +- }; +- +- pinctrl_gpio_keys: gpio-keysgrp { +- fsl,pins = < +- /* Home Button: J14 pin 5 */ +- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 +- /* Back Button: J14 pin 7 */ +- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +- /* Touch IRQ: J7 pin 4 */ +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 +- /* tcs2004 IRQ */ +- MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 +- /* tsc2004 reset */ +- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0b0b0 +- >; +- }; +- +- pinctrl_j10: j10grp { +- fsl,pins = < +- /* Broadcom WiFi module pins */ +- MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 +- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +- MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 +- MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 +- MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 +- MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 +- MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 +- >; +- }; +- +- pinctrl_j28: j28grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 +- >; +- }; +- +- pinctrl_leds: ledsgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 +- MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x0b0b0 +- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x030b0 +- MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b0b0 +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_wlan_vmmc: wlan-vmmcgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0 +- >; +- }; +- +- pinctrl_rtc: rtcgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 +- >; +- }; +- +- pinctrl_sgtl5000: sgtl5000grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 +- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 +- /* power enable, high active */ +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 +- >; +- }; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in_lvds0>; +- }; +- }; +- }; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "okay"; +-}; +- +-&pwm4 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- non-removable; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_wlan_vmmc>; +- cap-power-off-card; +- keep-power-in-suspend; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-nitrogen6_max.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-nitrogen6_max.dtsi +deleted file mode 100644 +index c96f4d7e1e0d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-nitrogen6_max.dtsi ++++ /dev/null +@@ -1,848 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright 2015 Boundary Devices, Inc. +- */ +-#include +-#include +- +-/ { +- chosen { +- stdout-path = &uart2; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0xF0000000>; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_1p8v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- reg_2p5v: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_h1_vbus: regulator@4 { +- compatible = "regulator-fixed"; +- reg = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1>; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_wlan_vmmc: regulator@5 { +- compatible = "regulator-fixed"; +- reg = <5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wlan_vmmc>; +- regulator-name = "reg_wlan_vmmc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <70000>; +- enable-active-high; +- }; +- +- reg_can_xcvr: regulator@6 { +- compatible = "regulator-fixed"; +- reg = <6>; +- regulator-name = "CAN XCVR"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can_xcvr>; +- gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- power { +- label = "Power Button"; +- gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- menu { +- label = "Menu"; +- gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- home { +- label = "Home"; +- gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- back { +- label = "Back"; +- gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- volume-down { +- label = "Volume Down"; +- gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- i2c2mux { +- compatible = "i2c-mux-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2mux>; +- #address-cells = <1>; +- #size-cells = <0>; +- mux-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH +- &gpio4 15 GPIO_ACTIVE_HIGH>; +- i2c-parent = <&i2c2>; +- idle-state = <0>; +- +- i2c2mux@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c2mux@2 { +- reg = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- i2c3mux { +- compatible = "i2c-mux-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3mux>; +- #address-cells = <1>; +- #size-cells = <0>; +- mux-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; +- i2c-parent = <&i2c3>; +- idle-state = <0>; +- +- i2c3mux@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- speaker-enable { +- gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; +- retain-state-suspended; +- default-state = "off"; +- }; +- +- ttymxc4-rs232 { +- gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; +- retain-state-suspended; +- default-state = "on"; +- }; +- }; +- +- backlight_lcd: backlight-lcd { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- power-supply = <®_3p3v>; +- status = "okay"; +- }; +- +- backlight_lvds0: backlight-lvds0 { +- compatible = "pwm-backlight"; +- pwms = <&pwm4 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- power-supply = <®_3p3v>; +- status = "okay"; +- }; +- +- backlight_lvds1: backlight-lvds1 { +- compatible = "pwm-backlight"; +- pwms = <&pwm2 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- power-supply = <®_3p3v>; +- status = "okay"; +- }; +- +- lcd_display: disp0 { +- compatible = "fsl,imx-parallel-display"; +- #address-cells = <1>; +- #size-cells = <0>; +- interface-pix-fmt = "bgr666"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_j15>; +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- lcd_display_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lcd_display_out: endpoint { +- remote-endpoint = <&lcd_panel_in>; +- }; +- }; +- }; +- +- panel-lcd { +- compatible = "okaya,rs800480t-7x0gp"; +- backlight = <&backlight_lcd>; +- +- port { +- lcd_panel_in: endpoint { +- remote-endpoint = <&lcd_display_out>; +- }; +- }; +- }; +- +- panel-lvds0 { +- compatible = "hannstar,hsd100pxn1"; +- backlight = <&backlight_lvds0>; +- +- port { +- panel_in_lvds0: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +- +- panel-lvds1 { +- compatible = "hannstar,hsd100pxn1"; +- backlight = <&backlight_lvds1>; +- +- port { +- panel_in_lvds1: endpoint { +- remote-endpoint = <&lvds1_out>; +- }; +- }; +- }; +- +- sound { +- compatible = "fsl,imx6q-nitrogen6_max-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "imx6q-nitrogen6_max-sgtl5000"; +- ssi-controller = <&ssi1>; +- audio-codec = <&codec>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <3>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- xceiver-supply = <®_can_xcvr>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, +- <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- flash: m25p80@0 { +- compatible = "microchip,sst25vf016b"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii"; +- phy-handle = <ðphy>; +- phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; +- interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, +- <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; +- fsl,err006687-workaround-present; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy { +- compatible = "ethernet-phy-ieee802.3-c22"; +- txen-skew-ps = <0>; +- txc-skew-ps = <3000>; +- rxdv-skew-ps = <0>; +- rxc-skew-ps = <3000>; +- rxd0-skew-ps = <0>; +- rxd1-skew-ps = <0>; +- rxd2-skew-ps = <0>; +- rxd3-skew-ps = <0>; +- txd0-skew-ps = <0>; +- txd1-skew-ps = <0>; +- txd2-skew-ps = <0>; +- txd3-skew-ps = <0>; +- }; +- }; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- codec: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sgtl5000>; +- reg = <0x0a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_3p3v>; +- }; +- +- rtc: rtc@68 { +- compatible = "microcrystal,rv4162"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rv4162>; +- reg = <0x68>; +- interrupts-extended = <&gpio4 6 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- touchscreen@4 { +- compatible = "eeti,egalax_ts"; +- reg = <0x04>; +- interrupt-parent = <&gpio1>; +- interrupts = <9 IRQ_TYPE_EDGE_FALLING>; +- wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- }; +- +- touchscreen@38 { +- compatible = "edt,edt-ft5x06"; +- reg = <0x38>; +- interrupt-parent = <&gpio1>; +- interrupts = <9 IRQ_TYPE_EDGE_FALLING>; +- wakeup-source; +- }; +-}; +- +-&iomuxc { +- imx6q-nitrogen6-max { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- >; +- }; +- +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_can_xcvr: can-xcvrgrp { +- fsl,pins = < +- /* Flexcan XCVR enable */ +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- /* Phy reset */ +- MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 +- >; +- }; +- +- pinctrl_gpio_keys: gpio-keysgrp { +- fsl,pins = < +- /* Power Button */ +- MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 +- /* Menu Button */ +- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +- /* Home Button */ +- MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 +- /* Back Button */ +- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 +- /* Volume Up Button */ +- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 +- /* Volume Down Button */ +- MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2mux: i2c2muxgrp { +- fsl,pins = < +- /* ov5642 camera i2c enable */ +- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b0 +- /* ov5640_mipi camera i2c enable */ +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c3mux: i2c3muxgrp { +- fsl,pins = < +- /* PCIe I2C enable */ +- MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 +- >; +- }; +- +- pinctrl_j15: j15grp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- /* PCIe reset */ +- MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_rv4162: rv4162grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 +- >; +- }; +- +- pinctrl_sgtl5000: sgtl5000grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 +- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 +- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x130b1 +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x030b1 +- /* RS485 RX Enable: pull up */ +- MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b1 +- /* RS485 DEN: pull down */ +- MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b1 +- /* RS485/!RS232 Select: pull down (rs232) */ +- MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b1 +- /* ON: pull down */ +- MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b1 +- >; +- }; +- +- pinctrl_usbh1: usbh1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 +- /* power enable, high active */ +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x100b0 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 +- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 +- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 +- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +- >; +- }; +- +- pinctrl_wlan_vmmc: wlan-vmmcgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 +- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 +- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 +- MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 +- >; +- }; +- }; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&lcd_display_in>; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in_lvds0>; +- }; +- }; +- }; +- +- lvds-channel@1 { +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds1_out: endpoint { +- remote-endpoint = <&panel_in_lvds1>; +- }; +- }; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&pwm2 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- status = "okay"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "okay"; +-}; +- +-&pwm4 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- non-removable; +- vmmc-supply = <®_wlan_vmmc>; +- cap-power-off-card; +- keep-power-in-suspend; +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1271"; +- reg = <2>; +- interrupt-parent = <&gpio6>; +- interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; +- ref-clock-frequency = <38400000>; +- }; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <8>; +- non-removable; +- vmmc-supply = <®_1p8v>; +- keep-power-in-suspend; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-nitrogen6_som2.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-nitrogen6_som2.dtsi +deleted file mode 100644 +index 92d09a3ebe0e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-nitrogen6_som2.dtsi ++++ /dev/null +@@ -1,735 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright 2016 Boundary Devices, Inc. +- */ +-#include +-#include +- +-/ { +- chosen { +- stdout-path = &uart2; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- backlight_lcd: backlight-lcd { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- power-supply = <®_3p3v>; +- status = "okay"; +- }; +- +- backlight_lvds0: backlight-lvds0 { +- compatible = "pwm-backlight"; +- pwms = <&pwm4 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- power-supply = <®_3p3v>; +- status = "okay"; +- }; +- +- backlight_lvds1: backlight-lvds1 { +- compatible = "gpio-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_backlight_lvds1>; +- gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; +- default-on; +- status = "okay"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- power { +- label = "Power Button"; +- gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- menu { +- label = "Menu"; +- gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- home { +- label = "Home"; +- gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- back { +- label = "Back"; +- gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- volume-down { +- label = "Volume Down"; +- gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- lcd_display: disp0 { +- compatible = "fsl,imx-parallel-display"; +- #address-cells = <1>; +- #size-cells = <0>; +- interface-pix-fmt = "bgr666"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_j15>; +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- lcd_display_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lcd_display_out: endpoint { +- remote-endpoint = <&lcd_panel_in>; +- }; +- }; +- }; +- +- panel-lcd { +- compatible = "okaya,rs800480t-7x0gp"; +- backlight = <&backlight_lcd>; +- +- port { +- lcd_panel_in: endpoint { +- remote-endpoint = <&lcd_display_out>; +- }; +- }; +- }; +- +- panel-lvds0 { +- compatible = "hannstar,hsd100pxn1"; +- backlight = <&backlight_lvds0>; +- +- port { +- panel_in_lvds0: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +- +- panel-lvds1 { +- compatible = "hannstar,hsd100pxn1"; +- backlight = <&backlight_lvds1>; +- +- port { +- panel_in_lvds1: endpoint { +- remote-endpoint = <&lvds1_out>; +- }; +- }; +- }; +- +- reg_1p8v: regulator-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- reg_2p5v: regulator-2v5 { +- compatible = "regulator-fixed"; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_can_xcvr: regulator-can-xcvr { +- compatible = "regulator-fixed"; +- regulator-name = "CAN XCVR"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can_xcvr>; +- gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; +- }; +- +- reg_usb_h1_vbus: regulator-usb-h1-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1>; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_wlan_vmmc: regulator-wlan-vmmc { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wlan_vmmc>; +- regulator-name = "reg_wlan_vmmc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <70000>; +- enable-active-high; +- }; +- +- sound { +- compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "imx6q-nitrogen6_som2-sgtl5000"; +- ssi-controller = <&ssi1>; +- audio-codec = <&codec>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <3>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- xceiver-supply = <®_can_xcvr>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, +- <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- flash: m25p80@0 { +- compatible = "microchip,sst25vf016b"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii"; +- interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, +- <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; +- fsl,err006687-workaround-present; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- codec: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sgtl5000>; +- reg = <0x0a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_3p3v>; +- }; +- +- rtc@68 { +- compatible = "microcrystal,rv4162"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rv4162>; +- reg = <0x68>; +- interrupts-extended = <&gpio6 7 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- touchscreen@4 { +- compatible = "eeti,egalax_ts"; +- reg = <0x04>; +- interrupt-parent = <&gpio1>; +- interrupts = <9 IRQ_TYPE_EDGE_FALLING>; +- wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- }; +- +- touchscreen@38 { +- compatible = "edt,edt-ft5x06"; +- reg = <0x38>; +- interrupt-parent = <&gpio1>; +- interrupts = <9 IRQ_TYPE_EDGE_FALLING>; +- wakeup-source; +- }; +-}; +- +-&iomuxc { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- >; +- }; +- +- pinctrl_backlight_lvds1: backlight-lvds1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0b0 +- >; +- }; +- +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_can_xcvr: can-xcvrgrp { +- fsl,pins = < +- /* Flexcan XCVR enable */ +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x130b0 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 +- MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 +- >; +- }; +- +- pinctrl_gpio_keys: gpio-keysgrp { +- fsl,pins = < +- /* Power Button */ +- MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 +- /* Menu Button */ +- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +- /* Home Button */ +- MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 +- /* Back Button */ +- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 +- /* Volume Up Button */ +- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 +- /* Volume Down Button */ +- MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c3mux: i2c3muxgrp { +- fsl,pins = < +- /* PCIe I2C enable */ +- MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 +- >; +- }; +- +- pinctrl_j15: j15grp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- /* PCIe reset */ +- MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x030b0 +- MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b1 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1 +- >; +- }; +- +- pinctrl_rv4162: rv4162grp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 +- >; +- }; +- +- pinctrl_sgtl5000: sgtl5000grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 +- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 +- MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x130b0 +- MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_usbh1: usbh1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 +- /* power enable, high active */ +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 +- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 +- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 +- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +- >; +- }; +- +- pinctrl_wlan_vmmc: wlan-vmmcgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 +- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 +- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 +- MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 +- >; +- }; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&lcd_display_in>; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in_lvds0>; +- }; +- }; +- }; +- +- lvds-channel@1 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <18>; +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds1_out: endpoint { +- remote-endpoint = <&panel_in_lvds1>; +- }; +- }; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio3 0 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "okay"; +-}; +- +-&pwm4 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- non-removable; +- vmmc-supply = <®_wlan_vmmc>; +- cap-power-off-card; +- keep-power-in-suspend; +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1271"; +- reg = <2>; +- interrupt-parent = <&gpio6>; +- interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; +- ref-clock-frequency = <38400000>; +- }; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <8>; +- non-removable; +- vmmc-supply = <®_1p8v>; +- keep-power-in-suspend; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-nitrogen6x.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-nitrogen6x.dtsi +deleted file mode 100644 +index 49da30d7510c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-nitrogen6x.dtsi ++++ /dev/null +@@ -1,692 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright 2013 Boundary Devices, Inc. +- * Copyright 2011 Freescale Semiconductor, Inc. +- * Copyright 2011 Linaro Ltd. +- */ +-#include +-#include +- +-/ { +- chosen { +- stdout-path = &uart2; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_2p5v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 0>; +- enable-active-high; +- }; +- +- reg_can_xcvr: regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- regulator-name = "CAN XCVR"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can_xcvr>; +- gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; +- }; +- +- reg_wlan_vmmc: regulator@4 { +- compatible = "regulator-fixed"; +- reg = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wlan_vmmc>; +- regulator-name = "reg_wlan_vmmc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <70000>; +- enable-active-high; +- }; +- +- reg_usb_h1_vbus: regulator@5 { +- compatible = "regulator-fixed"; +- reg = <5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1>; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- power { +- label = "Power Button"; +- gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- menu { +- label = "Menu"; +- gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- home { +- label = "Home"; +- gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- back { +- label = "Back"; +- gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- volume-down { +- label = "Volume Down"; +- gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- sound { +- compatible = "fsl,imx6q-nitrogen6x-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "imx6q-nitrogen6x-sgtl5000"; +- ssi-controller = <&ssi1>; +- audio-codec = <&codec>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <3>; +- }; +- +- backlight_lcd: backlight-lcd { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- power-supply = <®_3p3v>; +- status = "okay"; +- }; +- +- backlight_lvds: backlight-lvds { +- compatible = "pwm-backlight"; +- pwms = <&pwm4 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- power-supply = <®_3p3v>; +- status = "okay"; +- }; +- +- lcd_display: disp0 { +- compatible = "fsl,imx-parallel-display"; +- #address-cells = <1>; +- #size-cells = <0>; +- interface-pix-fmt = "bgr666"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_j15>; +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- lcd_display_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lcd_display_out: endpoint { +- remote-endpoint = <&lcd_panel_in>; +- }; +- }; +- }; +- +- panel-lcd { +- compatible = "okaya,rs800480t-7x0gp"; +- backlight = <&backlight_lcd>; +- +- port { +- lcd_panel_in: endpoint { +- remote-endpoint = <&lcd_display_out>; +- }; +- }; +- }; +- +- panel-lvds0 { +- compatible = "hannstar,hsd100pxn1"; +- backlight = <&backlight_lvds>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- xceiver-supply = <®_can_xcvr>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, +- <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- flash: m25p80@0 { +- compatible = "sst,sst25vf016b", "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "bootloader"; +- reg = <0x0 0xc0000>; +- }; +- +- partition@c0000 { +- label = "env"; +- reg = <0xc0000 0x2000>; +- }; +- +- partition@c2000 { +- label = "splash"; +- reg = <0xc2000 0x13e000>; +- }; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii"; +- phy-handle = <ðphy>; +- phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; +- interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, +- <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; +- fsl,err006687-workaround-present; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy { +- compatible = "ethernet-phy-ieee802.3-c22"; +- txen-skew-ps = <0>; +- txc-skew-ps = <3000>; +- rxdv-skew-ps = <0>; +- rxc-skew-ps = <3000>; +- rxd0-skew-ps = <0>; +- rxd1-skew-ps = <0>; +- rxd2-skew-ps = <0>; +- rxd3-skew-ps = <0>; +- txd0-skew-ps = <0>; +- txd1-skew-ps = <0>; +- txd2-skew-ps = <0>; +- txd3-skew-ps = <0>; +- }; +- }; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- codec: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_3p3v>; +- }; +- +- rtc: rtc@6f { +- compatible = "isil,isl1208"; +- reg = <0x6f>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- touchscreen@4 { +- compatible = "eeti,egalax_ts"; +- reg = <0x04>; +- interrupt-parent = <&gpio1>; +- interrupts = <9 IRQ_TYPE_EDGE_FALLING>; +- wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- }; +- +- touchscreen@38 { +- compatible = "edt,edt-ft5x06"; +- reg = <0x38>; +- interrupt-parent = <&gpio1>; +- interrupts = <9 IRQ_TYPE_EDGE_FALLING>; +- wakeup-source; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx6q-nitrogen6x { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- /* SGTL5000 sys_mclk */ +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 +- >; +- }; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- >; +- }; +- +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_can_xcvr: can-xcvrgrp { +- fsl,pins = < +- /* Flexcan XCVR enable */ +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- /* Phy reset */ +- MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0 +- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 +- >; +- }; +- +- pinctrl_gpio_keys: gpio-keysgrp { +- fsl,pins = < +- /* Power Button */ +- MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 +- /* Menu Button */ +- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +- /* Home Button */ +- MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 +- /* Back Button */ +- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 +- /* Volume Up Button */ +- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 +- /* Volume Down Button */ +- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_j15: j15grp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbh1: usbh1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 +- /* power enable, high active */ +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +- MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ +- >; +- }; +- +- pinctrl_wlan_vmmc: wlan-vmmcgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 +- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 +- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 +- MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 +- >; +- }; +- }; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&lcd_display_in>; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "okay"; +-}; +- +-&pwm4 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- non-removable; +- vmmc-supply = <®_wlan_vmmc>; +- cap-power-off-card; +- keep-power-in-suspend; +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1271"; +- reg = <2>; +- interrupt-parent = <&gpio6>; +- interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; +- ref-clock-frequency = <38400000>; +- }; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-phytec-mira.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-phytec-mira.dtsi +deleted file mode 100644 +index 019938562aa9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-phytec-mira.dtsi ++++ /dev/null +@@ -1,391 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2018 PHYTEC Messtechnik GmbH +- * Author: Christian Hemp +- */ +- +- +-/ { +- aliases { +- rtc0 = &i2c_rtc; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- power-supply = <®_backlight>; +- pwms = <&pwm1 0 5000000>; +- status = "okay"; +- }; +- +- gpio_leds: leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpioleds>; +- status = "disabled"; +- +- red { +- label = "phyboard-mira:red"; +- gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; +- }; +- +- green { +- label = "phyboard-mira:green"; +- gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; +- }; +- +- blue { +- label = "phyboard-mira:blue"; +- gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- }; +- }; +- +- reg_backlight: regulator-backlight { +- compatible = "regulator-fixed"; +- regulator-name = "backlight_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_en_switch: regulator-en-switch { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_en_switch>; +- regulator-name = "Enable Switch"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- gpio = <&gpio3 4 GPIO_ACTIVE_HIGH>; +- regulator-always-on; +- }; +- +- reg_flexcan1: regulator-flexcan1 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1_en>; +- regulator-name = "flexcan1-reg"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_panel: regulator-panel { +- compatible = "regulator-fixed"; +- regulator-name = "panel-power-supply"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- }; +- +- reg_pcie: regulator-pcie { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie_reg>; +- regulator-name = "mPCIe_1V5"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- gpio = <&gpio3 0 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_h1_vbus: usb-h1-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1_vbus>; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usbotg_vbus: usbotg-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg_vbus>; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- panel { +- compatible = "auo,g104sn02"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_panel_en>; +- power-supply = <®_panel>; +- enable-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; +- backlight = <&backlight>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- xceiver-supply = <®_flexcan1>; +- status = "disabled"; +-}; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hdmicec>; +- ddc-i2c-bus = <&i2c2>; +- status = "disabled"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clock-frequency = <400000>; +- status = "disabled"; +- +- stmpe: touchctrl@44 { +- compatible = "st,stmpe811"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_stmpe>; +- reg = <0x44>; +- interrupt-parent = <&gpio7>; +- interrupts = <12 IRQ_TYPE_NONE>; +- status = "disabled"; +- +- stmpe_touchscreen { +- compatible = "st,stmpe-ts"; +- st,sample-time = <4>; +- st,mod-12b = <1>; +- st,ref-sel = <0>; +- st,adc-freq = <1>; +- st,ave-ctrl = <1>; +- st,touch-det-delay = <2>; +- st,settling = <2>; +- st,fraction-z = <7>; +- st,i-drive = <1>; +- }; +- }; +- +- i2c_rtc: rtc@68 { +- compatible = "microcrystal,rv4162"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rtc_int>; +- reg = <0x68>; +- interrupt-parent = <&gpio7>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clock-frequency = <100000>; +- status = "disabled"; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <24>; +- status = "disabled"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>; +- vpcie-supply = <®_pcie>; +- status = "disabled"; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "disabled"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- disable-over-current; +- status = "disabled"; +-}; +- +-&usbotg { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- vbus-supply = <®_usbotg_vbus>; +- disable-over-current; +- status = "disabled"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- cd-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_panel_en: panelen1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1 +- >; +- }; +- +- pinctrl_en_switch: enswitchgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0xb0b1 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 +- MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan1_en: flexcan1engrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A18__GPIO2_IO20 0xb0b1 +- >; +- }; +- +- pinctrl_gpioleds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x1b0b0 +- >; +- }; +- +- pinctrl_hdmicec: hdmicecgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_OE__GPIO2_IO25 0xb0b1 +- >; +- }; +- +- pinctrl_pcie_reg: pciereggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0xb0b1 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_rtc_int: rtcintgrp { +- fsl,pins = < +- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 +- >; +- }; +- +- pinctrl_stmpe: stmpegrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbh1_vbus: usbh1vbusgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A20__GPIO2_IO18 0xb0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usbotg_vbus: usbotgvbusgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A19__GPIO2_IO19 0xb0b1 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 +- MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1 /* CD */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-phytec-pbab01.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-phytec-pbab01.dtsi +deleted file mode 100644 +index 51d28e275aa6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-phytec-pbab01.dtsi ++++ /dev/null +@@ -1,177 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH +- */ +- +-#include +- +-/ { +- chosen { +- stdout-path = &uart4; +- }; +- +- regulators { +- sound_1v8: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "i2s-audio-1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- sound_3v3: regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- regulator-name = "i2s-audio-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +- +- tlv320_mclk: oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <19200000>; +- clock-output-names = "tlv320-mclk"; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "OnboardTLV320AIC3007"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&dailink_master>; +- simple-audio-card,frame-master = <&dailink_master>; +- simple-audio-card,widgets = +- "Microphone", "Mic Jack", +- "Line", "Line In", +- "Line", "Line Out", +- "Speaker", "Speaker", +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "Line Out", "LLOUT", +- "Line Out", "RLOUT", +- "Speaker", "SPOP", +- "Speaker", "SPOM", +- "Headphone Jack", "HPLOUT", +- "Headphone Jack", "HPROUT", +- "MIC3L", "Mic Jack", +- "MIC3R", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "LINE1L", "Line In", +- "LINE1R", "Line In"; +- +- simple-audio-card,cpu { +- sound-dai = <&ssi2>; +- }; +- +- dailink_master: simple-audio-card,codec { +- sound-dai = <&codec>; +- clocks = <&tlv320_mclk>; +- }; +- }; +- +-}; +- +-&audmux { +- status = "okay"; +- +- ssi2 { +- fsl,audmux-port = <1>; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_SYN | +- IMX_AUDMUX_V2_PTCR_TFSDIR | +- IMX_AUDMUX_V2_PTCR_TFSEL(4) | +- IMX_AUDMUX_V2_PTCR_TCLKDIR | +- IMX_AUDMUX_V2_PTCR_TCSEL(4)) +- IMX_AUDMUX_V2_PDCR_RXDSEL(4) +- >; +- }; +- +- pins5 { +- fsl,audmux-port = <4>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN +- IMX_AUDMUX_V2_PDCR_RXDSEL(1) +- >; +- }; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&fec { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +- +- codec: tlv320@18 { +- compatible = "ti,tlv320aic3007"; +- #sound-dai-cells = <0>; +- reg = <0x18>; +- ai3x-micbias-vg = <2>; +- +- AVDD-supply = <&sound_3v3>; +- IOVDD-supply = <&sound_3v3>; +- DRVDD-supply = <&sound_3v3>; +- DVDD-supply = <&sound_1v8>; +- }; +- +- stmpe@41 { +- compatible = "st,stmpe811"; +- reg = <0x41>; +- }; +- +- rtc@51 { +- compatible = "epson,rtc8564"; +- reg = <0x51>; +- }; +- +- adc@64 { +- compatible = "maxim,max1037"; +- reg = <0x64>; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&ssi2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&uart4 { +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbotg { +- status = "okay"; +- dr_mode = "peripheral"; +-}; +- +-&usdhc2 { +- status = "okay"; +-}; +- +-&usdhc3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-phytec-pfla02.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-phytec-pfla02.dtsi +deleted file mode 100644 +index f3236204cb5a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-phytec-pfla02.dtsi ++++ /dev/null +@@ -1,453 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH +- */ +- +-#include +- +-/ { +- model = "Phytec phyFLEX-i.MX6 Quad"; +- compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_usb_otg_vbus: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio4 15 0>; +- enable-active-high; +- }; +- +- reg_usb_h1_vbus: regulator@1 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1_vbus>; +- reg = <1>; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 0 0>; +- enable-active-high; +- }; +- }; +- +- gpio_leds: leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds>; +- compatible = "gpio-leds"; +- +- green { +- label = "phyflex:green"; +- gpios = <&gpio1 30 0>; +- }; +- +- red { +- label = "phyflex:red"; +- gpios = <&gpio2 31 0>; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "disabled"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- status = "disabled"; +-}; +- +-&ecspi3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi3>; +- status = "okay"; +- cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; +- +- som_flash: flash@0 { +- compatible = "m25p80", "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-handle = <ðphy>; +- phy-mode = "rgmii"; +- phy-reset-duration = <10>; /* in msecs */ +- phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; +- phy-supply = <&vdd_eth_io_reg>; +- status = "disabled"; +- +- fec_mdio: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- txc-skew-ps = <1680>; +- rxc-skew-ps = <1860>; +- }; +- }; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- nand-on-flash-bbt; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- som_eeprom: eeprom@50 { +- compatible = "catalyst,24c32", "atmel,24c32"; +- pagesize = <32>; +- reg = <0x50>; +- }; +- +- pmic@58 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- compatible = "dlg,da9063"; +- reg = <0x58>; +- interrupt-parent = <&gpio2>; +- interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */ +- interrupt-controller; +- +- regulators { +- vddcore_reg: bcore1 { +- regulator-min-microvolt = <730000>; +- regulator-max-microvolt = <1380000>; +- regulator-always-on; +- }; +- +- vddsoc_reg: bcore2 { +- regulator-min-microvolt = <730000>; +- regulator-max-microvolt = <1380000>; +- regulator-always-on; +- }; +- +- vdd_ddr3_reg: bpro { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- +- vdd_3v3_reg: bperi { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_buckmem_reg: bmem { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_eth_reg: bio { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vdd_eth_io_reg: ldo4 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- vdd_mx6_snvs_reg: ldo5 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- +- vdd_3v3_pmic_io_reg: ldo6 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_sd0_reg: ldo9 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vdd_sd1_reg: ldo10 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vdd_mx6_high_reg: ldo11 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clock-frequency = <100000>; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- clock-frequency = <100000>; +-}; +- +-&iomuxc { +- imx6q-phytec-pfla02 { +- pinctrl_ecspi3: ecspi3grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 +- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 +- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 +- MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* CS0 */ +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 +- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* Reset GPIO */ +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_leds: ledsgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ +- MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = ; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = ; /* PMIC interrupt */ +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbh1_vbus: usbh1vbusgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc3_cdwp: usdhc3cdwp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 +- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 +- >; +- }; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 +- MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0 +- MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 +- MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 +- >; +- }; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>; +- status = "disabled"; +-}; +- +-®_arm { +- vin-supply = <&vddcore_reg>; +-}; +- +-®_pu { +- vin-supply = <&vddsoc_reg>; +-}; +- +-®_soc { +- vin-supply = <&vddsoc_reg>; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "disabled"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "disabled"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- status = "disabled"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "disabled"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- vmmc-supply = <&vdd_sd1_reg>; +- status = "disabled"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3 +- &pinctrl_usdhc3_cdwp>; +- cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; +- vmmc-supply = <&vdd_sd0_reg>; +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-phytec-phycore-som.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-phytec-phycore-som.dtsi +deleted file mode 100644 +index a80aa08a37cb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-phytec-phycore-som.dtsi ++++ /dev/null +@@ -1,291 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2018 PHYTEC Messtechnik GmbH +- * Author: Christian Hemp +- */ +- +-#include +-#include +- +-/ { +- aliases { +- rtc1 = &da9062_rtc; +- rtc2 = &snvs_rtc; +- }; +- +- /* +- * Set the minimum memory size here and +- * let the bootloader set the real size. +- */ +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x8000000>; +- }; +- +- gpio_leds_som: somleds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpioleds_som>; +- +- som-led-green { +- label = "phycore:green"; +- gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- m25p80: flash@0 { +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- status = "disabled"; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-handle = <ðphy>; +- phy-mode = "rgmii"; +- phy-supply = <&vdd_eth_io>; +- phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- status = "disabled"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy@3 { +- reg = <3>; +- txc-skew-ps = <1680>; +- rxc-skew-ps = <1860>; +- }; +- }; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- nand-on-flash-bbt; +- status = "disabled"; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- clock-frequency = <400000>; +- status = "okay"; +- +- eeprom@50 { +- compatible = "st,24c32", "atmel,24c32"; +- pagesize = <32>; +- reg = <0x50>; +- }; +- +- pmic: pmic@58 { +- compatible = "dlg,da9062"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- reg = <0x58>; +- interrupt-parent = <&gpio1>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- gpio-controller; +- #gpio-cells = <2>; +- +- da9062_rtc: rtc { +- compatible = "dlg,da9062-rtc"; +- }; +- +- da9062_onkey: onkey { +- compatible = "dlg,da9062-onkey"; +- }; +- +- watchdog { +- compatible = "dlg,da9062-watchdog"; +- dlg,use-sw-pm; +- }; +- +- regulators { +- vdd_arm: buck1 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <1380000>; +- regulator-initial-mode = ; +- regulator-always-on; +- }; +- +- vdd_soc: buck2 { +- regulator-name = "vdd_soc"; +- regulator-min-microvolt = <1150000>; +- regulator-max-microvolt = <1380000>; +- regulator-initial-mode = ; +- regulator-always-on; +- }; +- +- vdd_ddr3_1p5: buck3 { +- regulator-name = "vdd_ddr3"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-initial-mode = ; +- regulator-always-on; +- }; +- +- vdd_eth_1p2: buck4 { +- regulator-name = "vdd_eth"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- regulator-always-on; +- }; +- +- vdd_snvs: ldo1 { +- regulator-name = "vdd_snvs"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- +- vdd_high: ldo2 { +- regulator-name = "vdd_high"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- +- vdd_eth_io: ldo3 { +- regulator-name = "vdd_eth_io"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- }; +- +- vdd_emmc_1p8: ldo4 { +- regulator-name = "vdd_emmc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- }; +- }; +-}; +- +-®_arm { +- vin-supply = <&vdd_arm>; +-}; +- +-®_pu { +- vin-supply = <&vdd_soc>; +-}; +- +-®_soc { +- vin-supply = <&vdd_soc>; +-}; +- +-&snvs_poweroff { +- status = "okay"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <8>; +- non-removable; +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 +- MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 +- >; +- }; +- +- pinctrl_gpioleds_som: gpioledssomgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 +- MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1 +- MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 +- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 +- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 +- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-pico-dwarf.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-pico-dwarf.dtsi +deleted file mode 100644 +index 3a968782e854..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-pico-dwarf.dtsi ++++ /dev/null +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Copyright 2017 NXP +- +-#include "imx6qdl-pico.dtsi" +- +-/ { +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led { +- label = "gpio-led"; +- gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +-}; +- +-&i2c1 { +- mpl3115@60 { +- compatible = "fsl,mpl3115"; +- reg = <0x60>; +- }; +-}; +- +-&i2c2 { +- io-expander@25 { +- compatible = "nxp,pca9554"; +- reg = <0x25>; +- gpio-controller; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- }; +- +-}; +- +-&iomuxc { +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-pico-hobbit.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-pico-hobbit.dtsi +deleted file mode 100644 +index 144c4727fbc7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-pico-hobbit.dtsi ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Copyright 2017 NXP +- +-#include "imx6qdl-pico.dtsi" +- +-/ { +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led { +- label = "gpio-led"; +- gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +-}; +- +-&i2c2 { +- status = "okay"; +- +- adc081c: adc@50 { +- compatible = "ti,adc081c"; +- reg = <0x50>; +- vref-supply = <®_3p3v>; +- }; +-}; +- +-&iomuxc { +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-pico-nymph.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-pico-nymph.dtsi +deleted file mode 100644 +index 3d56a4216448..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-pico-nymph.dtsi ++++ /dev/null +@@ -1,54 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +- +-#include "imx6qdl-pico.dtsi" +- +-/ { +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led { +- label = "gpio-led"; +- gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +-}; +- +-&i2c1 { +- adc@52 { +- compatible = "ti,adc081c"; +- reg = <0x52>; +- vref-supply = <®_2p5v>; +- }; +-}; +- +-&i2c2 { +- io-expander@25 { +- compatible = "nxp,pca9554"; +- reg = <0x25>; +- gpio-controller; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- }; +-}; +- +-&i2c3 { +- rtc@68 { +- compatible = "dallas,ds1337"; +- reg = <0x68>; +- }; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-pico-pi.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-pico-pi.dtsi +deleted file mode 100644 +index b823dce62e63..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-pico-pi.dtsi ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Copyright 2017 NXP +- +-#include "imx6qdl-pico.dtsi" +- +-/ { +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led { +- label = "gpio-led"; +- gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +-}; +- +-&hdmi { +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-pico.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-pico.dtsi +deleted file mode 100644 +index f7a56d6b160c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-pico.dtsi ++++ /dev/null +@@ -1,628 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-// +-// Copyright 2018 Technexion Ltd. +-// +-// Author: Wig Cheng +-// Richard Hu +-// Tapani Utriainen +- +-#include +- +-/ { +- chosen { +- stdout-path = &uart1; +- }; +- +- reg_2p5v: regulator-2p5v { +- compatible = "regulator-fixed"; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- reg_1p5v: regulator-1p5v { +- compatible = "regulator-fixed"; +- regulator-name = "1P5V"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- +- reg_2p8v: regulator-2p8v { +- compatible = "regulator-fixed"; +- regulator-name = "2P8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg_vbus>; +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; +- }; +- +- codec_osc: clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +- +- sound { +- compatible = "fsl,imx-audio-sgtl5000"; +- model = "imx6-pico-sgtl5000"; +- ssi-controller = <&ssi1>; +- audio-codec = <&sgtl5000>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <3>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm4 0 50000 0>; +- brightness-levels = <0 36 72 108 144 180 216 255>; +- default-brightness-level = <6>; +- status = "okay"; +- }; +- +- reg_lcd_3v3: regulator-lcd-3v3 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_lcd>; +- regulator-name = "lcd-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- lcd_display: disp0 { +- compatible = "fsl,imx-parallel-display"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1>; +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- lcd_display_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lcd_display_out: endpoint { +- remote-endpoint = <&lcd_panel_in>; +- }; +- }; +- }; +- +- panel { +- compatible = "vxt,vl050-8048nt-c01"; +- backlight = <&backlight>; +- power-supply = <®_lcd_3v3>; +- +- port { +- lcd_panel_in: endpoint { +- remote-endpoint = <&lcd_display_out>; +- }; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, +- <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +-}; +- +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- cs-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; +- phy-handle = <&phy>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy: ethernet-phy@1 { +- reg = <1>; +- qca,clk-out-frequency = <125000000>; +- }; +- }; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- sgtl5000: audio-codec@a { +- #sound-dai-cells = <0>; +- reg = <0x0a>; +- compatible = "fsl,sgtl5000"; +- clocks = <&codec_osc>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_1p8v>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- touchscreen@38 { +- compatible = "edt,edt-ft5x06"; +- reg = <0x38>; +- interrupt-parent = <&gpio5>; +- interrupts = <31 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; +- touchscreen-size-x = <800>; +- touchscreen-size-y = <480>; +- wakeup-source; +- }; +- +- camera@3c { +- compatible = "ovti,ov5645"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ov5645>; +- reg = <0x3c>; +- clocks = <&clks IMX6QDL_CLK_CKO2>; +- clock-names = "xclk"; +- clock-frequency = <24000000>; +- vdddo-supply = <®_1p8v>; +- vdda-supply = <®_2p8v>; +- vddd-supply = <®_1p5v>; +- enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; +- +- port { +- ov5645_to_mipi_csi2: endpoint { +- remote-endpoint = <&mipi_csi2_in>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&lcd_display_in>; +-}; +- +-&mipi_csi { +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- mipi_csi2_in: endpoint { +- remote-endpoint = <&ov5645_to_mipi_csi2>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- }; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie_reset>; +- reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- status = "okay"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "okay"; +-}; +- +-&pwm4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { /* Bluetooth module */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- bus-width = <8>; +- cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&usdhc2 { /* Wifi/BT */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- no-1-8-v; +- keep-power-in-suspend; +- non-removable; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x4001b0b5 /* PICO_P24 */ +- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x4001b0b5 /* PICO_P26 */ +- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b5 /* PICO_P28 */ +- MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b0b5 /* PICO_P30 */ +- MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b0b5 /* PICO_P32 */ +- MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x4001b0b5 /* PICO_P34 */ +- MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x4001b0b5 /* PICO_P42 */ +- MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x4001b0b5 /* PICO_P44 */ +- MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x4001b0b5 /* PICO_P48 */ +- >; +- }; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000f0b0 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1b0b1 +- MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x1b0b1 +- MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x1b0b1 +- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000f0b0 +- MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x000f0b0 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 +- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1f0b1 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_ipu1: ipu1grp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 +- MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 +- >; +- }; +- +- pinctrl_ov5645: ov5645grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x0b0b0 +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 +- MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 +- >; +- }; +- +- pinctrl_pcie_reset: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x130b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_reg_lcd: reglcdgrp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 +- MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usbotg_vbus: usbotgvbusgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x17071 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-prti6q.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-prti6q.dtsi +deleted file mode 100644 +index 19578f660b09..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-prti6q.dtsi ++++ /dev/null +@@ -1,163 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (c) 2014 Protonic Holland +- */ +- +-#include +-#include +- +-/ { +- chosen { +- stdout-path = &uart4; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_usb_h1_vbus: regulator-h1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "h1-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usb_otg_vbus: regulator-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "otg-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- temperature-sensor@70 { +- compatible = "ti,tmp103"; +- reg = <0x70>; +- }; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- phy_type = "utmi"; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- phy_type = "utmi"; +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b008 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b008 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 +- MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-rex.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-rex.dtsi +deleted file mode 100644 +index de514eb5aa99..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-rex.dtsi ++++ /dev/null +@@ -1,367 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright 2014 FEDEVEL, Inc. +- * +- * Author: Robert Nelson +- */ +- +-#include +-#include +- +-/ { +- chosen { +- stdout-path = &uart1; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_3p3v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usbh1_vbus: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- pinctrl-names = "default"; +- regulator-name = "usbh1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_otg_vbus: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- pinctrl-names = "default"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led>; +- +- led0: usr { +- label = "usr"; +- gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- sound { +- compatible = "fsl,imx6-rex-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "imx6-rex-sgtl5000"; +- ssi-controller = <&ssi1>; +- audio-codec = <&codec>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <3>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&ecspi2 { +- cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- status = "okay"; +-}; +- +-&ecspi3 { +- cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi3>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii"; +- phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- codec: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- pca9535: gpio-expander@27 { +- compatible = "nxp,pca9535"; +- reg = <0x27>; +- gpio-controller; +- #gpio-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pca9535>; +- interrupt-parent = <&gpio6>; +- interrupts = <16 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- eeprom@57 { +- compatible = "atmel,24c02"; +- reg = <0x57>; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx6qdl-rex { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- /* SGTL5000 sys_mclk */ +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 +- >; +- }; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 +- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 +- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 +- /* CS */ +- MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x000b1 +- >; +- }; +- +- pinctrl_ecspi3: ecspi3grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 +- MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 +- MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 +- /* CS */ +- MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- /* Phy reset */ +- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_led: ledgrp { +- fsl,pins = < +- /* user led */ +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 +- >; +- }; +- +- pinctrl_pca9535: pca9535grp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x17059 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbh1: usbh1grp { +- fsl,pins = < +- /* power enable, high active */ +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x10b0 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 +- /* power enable, high active */ +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x10b0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- /* CD */ +- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 +- /* WP */ +- MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1f0b0 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- /* CD */ +- MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 +- /* WP */ +- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1f0b0 +- >; +- }; +- }; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usbh1_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <4>; +- cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-sabreauto.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-sabreauto.dtsi +deleted file mode 100644 +index 5e58740d40c5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-sabreauto.dtsi ++++ /dev/null +@@ -1,863 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2012 Freescale Semiconductor, Inc. +-// Copyright 2011 Linaro Ltd. +- +-#include +-#include +- +-/ { +- chosen { +- stdout-path = &uart4; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- user { +- label = "debug"; +- gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- home { +- label = "Home"; +- gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- back { +- label = "Back"; +- gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- program { +- label = "Program"; +- gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- volume-down { +- label = "Volume Down"; +- gpios = <&gpio5 14 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- clocks { +- codec_osc: anaclk2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +- }; +- +- reg_audio: regulator-audio { +- compatible = "regulator-fixed"; +- regulator-name = "cs42888_supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_h1_vbus: regulator-usb-h1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_can_en: regulator-can-en { +- compatible = "regulator-fixed"; +- regulator-name = "can-en"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_can_stby: regulator-can-stby { +- compatible = "regulator-fixed"; +- regulator-name = "can-stby"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_can_en>; +- }; +- +- sound-cs42888 { +- compatible = "fsl,imx6-sabreauto-cs42888", +- "fsl,imx-audio-cs42888"; +- model = "imx-cs42888"; +- audio-cpu = <&esai>; +- audio-asrc = <&asrc>; +- audio-codec = <&codec>; +- audio-routing = +- "Line Out Jack", "AOUT1L", +- "Line Out Jack", "AOUT1R", +- "Line Out Jack", "AOUT2L", +- "Line Out Jack", "AOUT2R", +- "Line Out Jack", "AOUT3L", +- "Line Out Jack", "AOUT3R", +- "Line Out Jack", "AOUT4L", +- "Line Out Jack", "AOUT4R", +- "AIN1L", "Line In Jack", +- "AIN1R", "Line In Jack", +- "AIN2L", "Line In Jack", +- "AIN2R", "Line In Jack"; +- }; +- +- sound-spdif { +- compatible = "fsl,imx-audio-spdif", +- "fsl,imx-sabreauto-spdif"; +- model = "imx-spdif"; +- spdif-controller = <&spdif>; +- spdif-in; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm3 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- status = "okay"; +- }; +- +- i2cmux { +- compatible = "i2c-mux-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3mux>; +- mux-gpios = <&gpio5 4 0>; +- i2c-parent = <&i2c3>; +- idle-state = <0>; +- +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- adv7180: camera@21 { +- compatible = "adi,adv7180"; +- reg = <0x21>; +- powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>; +- interrupt-parent = <&gpio1>; +- interrupts = <27 IRQ_TYPE_LEVEL_LOW>; +- +- port { +- adv7180_to_ipu1_csi0_mux: endpoint { +- remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; +- bus-width = <8>; +- }; +- }; +- }; +- +- max7310_a: gpio@30 { +- compatible = "maxim,max7310"; +- reg = <0x30>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- max7310_b: gpio@32 { +- compatible = "maxim,max7310"; +- reg = <0x32>; +- gpio-controller; +- #gpio-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_max7310>; +- reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +- }; +- +- max7310_c: gpio@34 { +- compatible = "maxim,max7310"; +- reg = <0x34>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- light-sensor@44 { +- compatible = "isil,isl29023"; +- reg = <0x44>; +- interrupt-parent = <&gpio5>; +- interrupts = <17 IRQ_TYPE_EDGE_FALLING>; +- }; +- +- magnetometer@e { +- compatible = "fsl,mag3110"; +- reg = <0x0e>; +- interrupt-parent = <&gpio2>; +- interrupts = <29 IRQ_TYPE_EDGE_RISING>; +- }; +- +- accelerometer@1c { +- compatible = "fsl,mma8451"; +- reg = <0x1c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mma8451_int>; +- interrupt-parent = <&gpio6>; +- interrupts = <31 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +- }; +-}; +- +-&ipu1_csi0_from_ipu1_csi0_mux { +- bus-width = <8>; +-}; +- +-&ipu1_csi0_mux_from_parallel_sensor { +- remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; +- bus-width = <8>; +-}; +- +-&ipu1_csi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_csi0>; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>, +- <&clks IMX6QDL_PLL4_BYPASS>, +- <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>, +- <&clks IMX6QDL_CLK_PLL4_POST_DIV>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, +- <&clks IMX6QDL_PLL4_BYPASS_SRC>, +- <&clks IMX6QDL_CLK_PLL3_USB_OTG>, +- <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +- assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; +- status = "disabled"; /* pin conflict with WEIM NOR */ +- +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p32", "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +- +-&esai { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esai>; +- assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>, +- <&clks IMX6QDL_CLK_ESAI_EXTAL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; +- assigned-clock-rates = <0>, <24576000>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, +- <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; +- fsl,err006687-workaround-present; +- fsl,magic-packet; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- xceiver-supply = <®_can_stby>; +- status = "disabled"; /* pin conflict with fec */ +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- xceiver-supply = <®_can_stby>; +- status = "okay"; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- status = "okay"; +-}; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hdmi_cec>; +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- pmic: pfuze100@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +- +- codec: cs42888@48 { +- compatible = "cirrus,cs42888"; +- reg = <0x48>; +- clocks = <&codec_osc>; +- clock-names = "mclk"; +- VA-supply = <®_audio>; +- VD-supply = <®_audio>; +- VLS-supply = <®_audio>; +- VLC-supply = <®_audio>; +- }; +- +- touchscreen@4 { +- compatible = "eeti,egalax_ts"; +- reg = <0x04>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_egalax_int>; +- interrupt-parent = <&gpio2>; +- interrupts = <28 IRQ_TYPE_EDGE_FALLING>; +- wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx6qdl-sabreauto { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 +- MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 +- MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- >; +- }; +- +- pinctrl_ecspi1_cs: ecspi1cs { +- fsl,pins = < +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 +- >; +- }; +- +- pinctrl_egalax_int: egalax-intgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 +- >; +- }; +- +- pinctrl_esai: esaigrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 +- MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 +- MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 +- MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 +- MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 +- MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 +- MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 +- MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 +- MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 +- MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x17059 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x17059 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x17059 +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x17059 +- >; +- }; +- +- pinctrl_gpio_keys: gpiokeysgrp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 +- MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 +- MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 +- MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 +- MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 +- >; +- }; +- +- pinctrl_hdmi_cec: hdmicecgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3mux: i2c3muxgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1 +- >; +- }; +- +- pinctrl_ipu1_csi0: ipu1csi0grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 +- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 +- MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 +- MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 +- >; +- }; +- +- pinctrl_max7310: max7310grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 +- >; +- }; +- +- pinctrl_mma8451_int: mma8451intgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_gpt_input_capture0: gptinputcapture0grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0 +- >; +- }; +- +- pinctrl_gpt_input_capture1: gptinputcapture1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0 +- >; +- }; +- +- pinctrl_spdif: spdifgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp100mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp200mhz { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 +- >; +- }; +- +- pinctrl_weim_cs0: weimcs0grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 +- >; +- }; +- +- pinctrl_weim_nor: weimnorgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 +- MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 +- MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 +- MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 +- MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 +- MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 +- MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 +- MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 +- MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 +- MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 +- MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 +- MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 +- MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 +- MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 +- MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 +- MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 +- MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 +- MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 +- MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 +- MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 +- MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 +- MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 +- MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 +- MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 +- MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 +- MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 +- MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 +- MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 +- MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 +- MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 +- MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 +- MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 +- MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 +- MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 +- MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 +- MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 +- MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 +- MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 +- MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 +- MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 +- MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 +- MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 +- MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 +- >; +- }; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <18>; +- status = "okay"; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: hsd100pxn1 { +- clock-frequency = <65000000>; +- hactive = <1024>; +- vactive = <768>; +- hback-porch = <220>; +- hfront-porch = <40>; +- vback-porch = <21>; +- vfront-porch = <7>; +- hsync-len = <60>; +- vsync-len = <10>; +- }; +- }; +- }; +-}; +- +-&pwm3 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "okay"; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&spdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spdif>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&weim { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; +- ranges = <0 0 0x08000000 0x08000000>; +- status = "disabled"; /* pin conflict with SPI NOR */ +- +- nor@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x02000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- bank-width = <2>; +- fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 +- 0x0000c000 0x1404a38e 0x00000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-sabrelite.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-sabrelite.dtsi +deleted file mode 100644 +index eb9a0b104f1c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-sabrelite.dtsi ++++ /dev/null +@@ -1,778 +0,0 @@ +-/* +- * Copyright 2011 Freescale Semiconductor, Inc. +- * Copyright 2011 Linaro Ltd. +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include +- +-/ { +- chosen { +- stdout-path = &uart2; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_2p5v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 0>; +- enable-active-high; +- }; +- +- reg_can_xcvr: regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- regulator-name = "CAN XCVR"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can_xcvr>; +- gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; +- }; +- +- reg_1p5v: regulator@4 { +- compatible = "regulator-fixed"; +- reg = <4>; +- regulator-name = "1P5V"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- +- reg_1p8v: regulator@5 { +- compatible = "regulator-fixed"; +- reg = <5>; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- reg_2p8v: regulator@6 { +- compatible = "regulator-fixed"; +- reg = <6>; +- regulator-name = "2P8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- reg_usb_h1_vbus: regulator@7 { +- compatible = "regulator-fixed"; +- reg = <7>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1>; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- }; +- +- mipi_xclk: mipi_xclk { +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <22000000>; +- clock-output-names = "mipi_pwm3"; +- pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */ +- status = "okay"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- power { +- label = "Power Button"; +- gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- menu { +- label = "Menu"; +- gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- home { +- label = "Home"; +- gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- back { +- label = "Back"; +- gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- volume-down { +- label = "Volume Down"; +- gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- sound { +- compatible = "fsl,imx6q-sabrelite-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "imx6q-sabrelite-sgtl5000"; +- ssi-controller = <&ssi1>; +- audio-codec = <&codec>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <4>; +- }; +- +- backlight_lcd: backlight-lcd { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- power-supply = <®_3p3v>; +- status = "okay"; +- }; +- +- backlight_lvds: backlight-lvds { +- compatible = "pwm-backlight"; +- pwms = <&pwm4 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- power-supply = <®_3p3v>; +- status = "okay"; +- }; +- +- lcd_display: disp0 { +- compatible = "fsl,imx-parallel-display"; +- #address-cells = <1>; +- #size-cells = <0>; +- interface-pix-fmt = "bgr666"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_j15>; +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- lcd_display_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lcd_display_out: endpoint { +- remote-endpoint = <&lcd_panel_in>; +- }; +- }; +- }; +- +- panel-lcd { +- compatible = "okaya,rs800480t-7x0gp"; +- backlight = <&backlight_lcd>; +- +- port { +- lcd_panel_in: endpoint { +- remote-endpoint = <&lcd_display_out>; +- }; +- }; +- }; +- +- panel-lvds0 { +- compatible = "hannstar,hsd100pxn1"; +- backlight = <&backlight_lvds>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +-}; +- +-&ipu1_csi0_from_ipu1_csi0_mux { +- bus-width = <8>; +- data-shift = <12>; /* Lines 19:12 used */ +- hsync-active = <1>; +- vync-active = <1>; +-}; +- +-&ipu1_csi0_mux_from_parallel_sensor { +- remote-endpoint = <&ov5642_to_ipu1_csi0_mux>; +-}; +- +-&ipu1_csi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_csi0>; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- xceiver-supply = <®_can_xcvr>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, +- <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- flash: m25p80@0 { +- compatible = "sst,sst25vf016b", "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii"; +- phy-handle = <ðphy>; +- phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy { +- compatible = "ethernet-phy-ieee802.3-c22"; +- txen-skew-ps = <0>; +- txc-skew-ps = <3000>; +- rxdv-skew-ps = <0>; +- rxc-skew-ps = <3000>; +- rxd0-skew-ps = <0>; +- rxd1-skew-ps = <0>; +- rxd2-skew-ps = <0>; +- rxd3-skew-ps = <0>; +- txd0-skew-ps = <0>; +- txd1-skew-ps = <0>; +- txd2-skew-ps = <0>; +- txd3-skew-ps = <0>; +- }; +- }; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- codec: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_3p3v>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- ov5640: camera@40 { +- compatible = "ovti,ov5640"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ov5640>; +- reg = <0x40>; +- clocks = <&mipi_xclk>; +- clock-names = "xclk"; +- DOVDD-supply = <®_1p8v>; +- AVDD-supply = <®_2p8v>; +- DVDD-supply = <®_1p5v>; +- reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* NANDF_D5 */ +- powerdown-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* NANDF_WP_B */ +- +- port { +- ov5640_to_mipi_csi2: endpoint { +- remote-endpoint = <&mipi_csi2_in>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- }; +- }; +- }; +- +- ov5642: camera@42 { +- compatible = "ovti,ov5642"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ov5642>; +- clocks = <&clks IMX6QDL_CLK_CKO2>; +- clock-names = "xclk"; +- reg = <0x42>; +- reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; +- powerdown-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; +- gp-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; +- status = "disabled"; +- +- port { +- ov5642_to_ipu1_csi0_mux: endpoint { +- remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; +- bus-width = <8>; +- hsync-active = <1>; +- vsync-active = <1>; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx6q-sabrelite { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- /* SGTL5000 sys_mclk */ +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 +- >; +- }; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 +- MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 +- MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 +- MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 +- >; +- }; +- +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_can_xcvr: can-xcvrgrp { +- fsl,pins = < +- /* Flexcan XCVR enable */ +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- /* Phy reset */ +- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0 +- >; +- }; +- +- pinctrl_gpio_keys: gpio-keysgrp { +- fsl,pins = < +- /* Power Button */ +- MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 +- /* Menu Button */ +- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +- /* Home Button */ +- MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 +- /* Back Button */ +- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 +- /* Volume Up Button */ +- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 +- /* Volume Down Button */ +- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_ipu1_csi0: ipu1csi0grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 +- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 +- MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 +- MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 +- MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0 +- >; +- }; +- +- pinctrl_j15: j15grp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 +- >; +- }; +- +- pinctrl_ov5640: ov5640grp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0 +- MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 +- >; +- }; +- +- pinctrl_ov5642: ov5642grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 +- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 +- MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbh1: usbh1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 +- /* power enable, high active */ +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ +- MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */ +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +- MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ +- >; +- }; +- }; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&lcd_display_in>; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&pwm3 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "okay"; +-}; +- +-&pwm4 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&mipi_csi { +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- mipi_csi2_in: endpoint { +- remote-endpoint = <&ov5640_to_mipi_csi2>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-sabresd.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-sabresd.dtsi +deleted file mode 100644 +index 0c0105468a2f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-sabresd.dtsi ++++ /dev/null +@@ -1,851 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2012 Freescale Semiconductor, Inc. +-// Copyright 2011 Linaro Ltd. +- +-#include +-#include +-#include +- +-/ { +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&swbst_reg>; +- }; +- +- reg_usb_h1_vbus: regulator-usb-h1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&swbst_reg>; +- }; +- +- reg_audio: regulator-audio { +- compatible = "regulator-fixed"; +- regulator-name = "wm8962-supply"; +- gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_pcie: regulator-pcie { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie_reg>; +- regulator-name = "MPCIE_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_sensors: regulator-sensors { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sensors_reg>; +- regulator-name = "sensors-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- power { +- label = "Power Button"; +- gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; +- wakeup-source; +- linux,code = ; +- }; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- wakeup-source; +- linux,code = ; +- }; +- +- volume-down { +- label = "Volume Down"; +- gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +- wakeup-source; +- linux,code = ; +- }; +- }; +- +- sound { +- compatible = "fsl,imx6q-sabresd-wm8962", +- "fsl,imx-audio-wm8962"; +- model = "wm8962-audio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hp>; +- ssi-controller = <&ssi2>; +- audio-codec = <&codec>; +- audio-asrc = <&asrc>; +- audio-routing = +- "Headphone Jack", "HPOUTL", +- "Headphone Jack", "HPOUTR", +- "Ext Spk", "SPKOUTL", +- "Ext Spk", "SPKOUTR", +- "AMIC", "MICBIAS", +- "IN3R", "AMIC", +- "DMIC", "MICBIAS", +- "DMICDAT", "DMIC"; +- mux-int-port = <2>; +- mux-ext-port = <3>; +- hp-det-gpio = <&gpio7 8 GPIO_ACTIVE_LOW>; +- mic-det-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; +- }; +- +- backlight_lvds: backlight-lvds { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- status = "okay"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- red { +- gpios = <&gpio1 2 0>; +- default-state = "on"; +- }; +- }; +- +- panel { +- compatible = "hannstar,hsd100pxn1"; +- backlight = <&backlight_lvds>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +-}; +- +-&ipu1_csi0_from_ipu1_csi0_mux { +- bus-width = <8>; +- data-shift = <12>; /* Lines 19:12 used */ +- hsync-active = <1>; +- vsync-active = <1>; +-}; +- +-&ipu1_csi0_mux_from_parallel_sensor { +- remote-endpoint = <&ov5642_to_ipu1_csi0_mux>; +-}; +- +-&ipu1_csi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_csi0>; +-}; +- +-&mipi_csi { +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- mipi_csi2_in: endpoint { +- remote-endpoint = <&ov5640_to_mipi_csi2>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, +- <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p32", "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-handle = <&phy>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy: ethernet-phy@1 { +- reg = <1>; +- qca,clk-out-frequency = <125000000>; +- reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- }; +- }; +-}; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hdmi_cec>; +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- codec: wm8962@1a { +- compatible = "wlf,wm8962"; +- reg = <0x1a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- DCVDD-supply = <®_audio>; +- DBVDD-supply = <®_audio>; +- AVDD-supply = <®_audio>; +- CPVDD-supply = <®_audio>; +- MICVDD-supply = <®_audio>; +- PLLVDD-supply = <®_audio>; +- SPKVDD1-supply = <®_audio>; +- SPKVDD2-supply = <®_audio>; +- gpio-cfg = < +- 0x0000 /* 0:Default */ +- 0x0000 /* 1:Default */ +- 0x0013 /* 2:FN_DMICCLK */ +- 0x0000 /* 3:Default */ +- 0x8014 /* 4:FN_DMICCDAT */ +- 0x0000 /* 5:Default */ +- >; +- }; +- +- accelerometer@1c { +- compatible = "fsl,mma8451"; +- reg = <0x1c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1_mma8451_int>; +- interrupt-parent = <&gpio1>; +- interrupts = <18 IRQ_TYPE_LEVEL_LOW>; +- vdd-supply = <®_sensors>; +- vddio-supply = <®_sensors>; +- }; +- +- ov5642: camera@3c { +- compatible = "ovti,ov5642"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ov5642>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- clock-names = "xclk"; +- reg = <0x3c>; +- DOVDD-supply = <&vgen4_reg>; /* 1.8v */ +- AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 +- rev B board is VGEN5 */ +- DVDD-supply = <&vgen2_reg>; /* 1.5v*/ +- powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +- status = "disabled"; +- +- port { +- ov5642_to_ipu1_csi0_mux: endpoint { +- remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; +- bus-width = <8>; +- hsync-active = <1>; +- vsync-active = <1>; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- touchscreen@4 { +- compatible = "eeti,egalax_ts"; +- reg = <0x04>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2_egalax_int>; +- interrupt-parent = <&gpio6>; +- interrupts = <8 IRQ_TYPE_EDGE_FALLING>; +- wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; +- }; +- +- ov5640: camera@3c { +- compatible = "ovti,ov5640"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ov5640>; +- reg = <0x3c>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- clock-names = "xclk"; +- DOVDD-supply = <&vgen4_reg>; /* 1.8v */ +- AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 +- rev B board is VGEN5 */ +- DVDD-supply = <&vgen2_reg>; /* 1.5v*/ +- powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; +- +- port { +- ov5640_to_mipi_csi2: endpoint { +- remote-endpoint = <&mipi_csi2_in>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- }; +- }; +- }; +- +- pmic: pfuze100@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- egalax_ts@4 { +- compatible = "eeti,egalax_ts"; +- reg = <0x04>; +- interrupt-parent = <&gpio6>; +- interrupts = <7 2>; +- wakeup-gpios = <&gpio6 7 0>; +- }; +- +- magnetometer@e { +- compatible = "fsl,mag3110"; +- reg = <0x0e>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3_mag3110_int>; +- interrupt-parent = <&gpio3>; +- interrupts = <16 IRQ_TYPE_EDGE_RISING>; +- vdd-supply = <®_sensors>; +- vddio-supply = <®_sensors>; +- }; +- +- light-sensor@44 { +- compatible = "isil,isl29023"; +- reg = <0x44>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3_isl29023_int>; +- interrupt-parent = <&gpio3>; +- interrupts = <9 IRQ_TYPE_EDGE_FALLING>; +- vcc-supply = <®_sensors>; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx6qdl-sabresd { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 +- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 +- MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 +- MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 +- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 +- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 +- >; +- }; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- >; +- }; +- +- pinctrl_gpio_keys: gpio_keysgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 +- MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 +- >; +- }; +- +- pinctrl_hdmi_cec: hdmicecgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 +- >; +- }; +- +- pinctrl_hp: hpgrp { +- fsl,pins = < +- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c1_mma8451_int: i2c1mma8451intgrp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0xb0b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2_egalax_int: i2c2egalaxintgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3_isl29023_int: i2c3isl29023intgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1 +- >; +- }; +- +- pinctrl_i2c3_mag3110_int: i2c3mag3110intgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D16__GPIO3_IO16 0xb0b1 +- >; +- }; +- +- pinctrl_ipu1_csi0: ipu1csi0grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 +- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 +- MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 +- MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 +- >; +- }; +- +- pinctrl_ov5640: ov5640grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 +- MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 +- >; +- }; +- +- pinctrl_ov5642: ov5642grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 +- MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 +- >; +- }; +- +- pinctrl_pcie_reg: pciereggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_sensors_reg: sensorsreggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 +- MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 +- MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 +- MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 +- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 +- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 +- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 +- >; +- }; +- }; +- +- gpio_leds { +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +- >; +- }; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@1 { +- fsl,data-mapping = "spwg"; +- fsl,data-width = <18>; +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; +- vpcie-supply = <®_pcie>; +- status = "okay"; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-®_arm { +- vin-supply = <&sw1a_reg>; +-}; +- +-®_pu { +- vin-supply = <&sw1c_reg>; +-}; +- +-®_soc { +- vin-supply = <&sw1c_reg>; +-}; +- +-®_vdd1p1 { +- vin-supply = <&vgen5_reg>; +-}; +- +-®_vdd2p5 { +- vin-supply = <&vgen5_reg>; +-}; +- +-&snvs_poweroff { +- status = "okay"; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +- +-&ssi2 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usb_h1_vbus>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <8>; +- cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <8>; +- cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <8>; +- non-removable; +- no-1-8-v; +- status = "okay"; +-}; +- +-&wdog1 { +- status = "disabled"; +-}; +- +-&wdog2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-savageboard.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-savageboard.dtsi +deleted file mode 100644 +index 02e6d36e85fa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-savageboard.dtsi ++++ /dev/null +@@ -1,256 +0,0 @@ +-/* +- * Copyright (C) 2017 Milo Kim +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +- +-/ { +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- power { +- gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; +- label = "Power Button"; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- panel { +- compatible = "avic,tm097tdh02", "hannstar,hsd100pxn1"; +- backlight = <&panel_bl>; +- power-supply = <®_3p3v>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +- +- panel_bl: backlight { +- compatible = "pwm-backlight"; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <4>; +- power-supply = <®_3p3v>; +- pwms = <&pwm1 0 10000>; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, +- <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +-}; +- +-&fec { +- phy-mode = "rgmii"; +- phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- reg = <0>; +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-/* SD card */ +-&usdhc3 { +- bus-width = <4>; +- cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sd>; +- status = "okay"; +-}; +- +-/* eMMC */ +-&usdhc4 { +- bus-width = <8>; +- keep-power-in-suspend; +- no-1-8-v; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_emmc>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_emmc: emmcgrp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 +- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 +- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 +- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- /* PHY reset */ +- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 +- >; +- }; +- +- pinctrl_gpio_keys: gpiokeysgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_sd: sdgrp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- /* CD pin */ +- MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-skov-cpu-revc.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-skov-cpu-revc.dtsi +deleted file mode 100644 +index 69ae430a53bd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-skov-cpu-revc.dtsi ++++ /dev/null +@@ -1,54 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright (C) 2020 Pengutronix, Ulrich Oelmann +- +-&ecspi4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi4>; +- cs-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- touchscreen@0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_touch>; +- compatible = "ti,tsc2046"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- interrupts-extended = <&gpio3 19 IRQ_TYPE_LEVEL_LOW>; +- vcc-supply = <®_3v3>; +- pendown-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; +- ti,x-plate-ohms = /bits/ 16 <850>; +- ti,y-plate-ohms = /bits/ 16 <295>; +- ti,pressure-min = /bits/ 16 <2>; +- ti,pressure-max = /bits/ 16 <1500>; +- ti,vref-mv = /bits/ 16 <3300>; +- ti,settle-delay-usec = /bits/ 16 <15>; +- ti,vref-delay-usecs = /bits/ 16 <0>; +- ti,penirq-recheck-delay-usecs = /bits/ 16 <100>; +- ti,debounce-max = /bits/ 16 <100>; +- ti,debounce-tol = /bits/ 16 <(~0)>; +- ti,debounce-rep = /bits/ 16 <4>; +- touchscreen-swapped-x-y; +- touchscreen-inverted-y; +- wakeup-source; +- }; +-}; +- +-&iomuxc { +- pinctrl_ecspi4: ecspi4grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x000b1 +- MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x000b1 +- /* *no* external pull up */ +- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x40000058 +- >; +- }; +- +- pinctrl_touch: touchgrp { +- fsl,pins = < +- /* external pull up */ +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x10040 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-skov-cpu.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-skov-cpu.dtsi +deleted file mode 100644 +index 77a91a97e6cf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-skov-cpu.dtsi ++++ /dev/null +@@ -1,477 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright (C) 2020 Pengutronix, Ulrich Oelmann +- +-#include +-#include +- +-/ { +- chosen { +- stdout-path = &uart2; +- }; +- +- aliases { +- can0 = &can1; +- can1 = &can2; +- mdio-gpio0 = &mdio; +- nand = &gpmi; +- rtc0 = &i2c_rtc; +- rtc1 = &snvs; +- usb0 = &usbh1; +- usb1 = &usbotg; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, /* 24V */ +- <&adc 1>; /* temperature */ +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "D1"; +- gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- function = LED_FUNCTION_STATUS; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-1 { +- label = "D2"; +- gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-2 { +- label = "D3"; +- gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- mdio: mdio { +- compatible = "microchip,mdio-smi0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mdio>; +- #address-cells = <1>; +- #size-cells = <0>; +- gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>, +- <&gpio1 22 GPIO_ACTIVE_HIGH>; +- +- switch@0 { +- compatible = "microchip,ksz8873"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_switch>; +- interrupt-parent = <&gpio3>; +- interrupt = <30 IRQ_TYPE_LEVEL_HIGH>; +- reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +- reg = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports@0 { +- reg = <0>; +- phy-mode = "internal"; +- label = "lan1"; +- }; +- +- ports@1 { +- reg = <1>; +- phy-mode = "internal"; +- label = "lan2"; +- }; +- +- ports@2 { +- reg = <2>; +- label = "cpu"; +- ethernet = <&fec>; +- phy-mode = "rmii"; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +- }; +- }; +- +- }; +- +- clk50m_phy: phy-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- vin-supply = <®_5v0>; +- regulator-name = "3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_5v0: regulator-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_24v0: regulator-24v0 { +- compatible = "regulator-fixed"; +- regulator-name = "24v0"; +- regulator-min-microvolt = <24000000>; +- regulator-max-microvolt = <24000000>; +- }; +- +- reg_can1_stby: regulator-can1-stby { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1_stby>; +- regulator-name = "can1-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; +- }; +- +- reg_can2_stby: regulator-can2-stby { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can2_stby>; +- regulator-name = "can2-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio4 11 GPIO_ACTIVE_LOW>; +- }; +- +- reg_vcc_mmc: regulator-vcc-mmc { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_vcc_mmc>; +- vin-supply = <®_3v3>; +- regulator-name = "mmc_vcc_supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- startup-delay-us = <100>; +- }; +- +- reg_vcc_mmc_io: regulator-vcc-mmc-io { +- compatible = "regulator-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_vcc_mmc_io>; +- vin-supply = <®_5v0>; +- regulator-name = "mmc_io_supply"; +- regulator-type = "voltage"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- states = <1800000 0x1>, <3300000 0x0>; +- startup-delay-us = <100>; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- xceiver-supply = <®_can1_stby>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can2>; +- xceiver-supply = <®_can2_stby>; +- status = "okay"; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <54000000>; +- reg = <0>; +- }; +-}; +- +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- adc: adc@0 { +- compatible = "microchip,mcp3002"; +- reg = <0>; +- vref-supply = <®_3v3>; +- spi-max-frequency = <1000000>; +- #io-channel-cells = <1>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- clocks = <&clks IMX6QDL_CLK_ENET>, +- <&clks IMX6QDL_CLK_ENET>, +- <&clk50m_phy>; +- clock-names = "ipg", "ahb", "ptp"; +- phy-mode = "rmii"; +- phy-supply = <®_3v3>; +- status = "okay"; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- nand-on-flash-bbt; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- clock-frequency = <400000>; +- status = "okay"; +- +- i2c_rtc: rtc@51 { +- compatible = "nxp,pcf85063"; +- reg = <0x51>; +- quartz-load-femtofarads = <12500>; +- }; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- #pwm-cells = <2>; +- status = "okay"; +-}; +- +-&pwm3 { +- /* used for LCD contrast control */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_5v0>; +- disable-over-current; +- status = "okay"; +-}; +- +-/* no usbh2 */ +-&usbphynop1 { +- status = "disabled"; +-}; +- +-/* no usbh3 */ +-&usbphynop2 { +- status = "disabled"; +-}; +- +-&usbotg { +- vbus-supply = <®_5v0>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; +- cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; +- cap-power-off-card; +- full-pwr-cycle; +- bus-width = <4>; +- max-frequency = <50000000>; +- cap-sd-highspeed; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-ddr50; +- mmc-ddr-1_8v; +- vmmc-supply = <®_vcc_mmc>; +- vqmmc-supply = <®_vcc_mmc_io>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x3008 +- MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b000 +- >; +- }; +- +- pinctrl_can1_stby: can1stbygrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x13008 +- >; +- }; +- +- pinctrl_can2: can2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 +- >; +- }; +- +- pinctrl_can2_stby: can2stbygrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x13008 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb1 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb1 +- /* *no* external pull up */ +- MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x58 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 +- MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0xb1 +- MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0xb1 +- /* external pull up */ +- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x58 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- /* RMII 50 MHz */ +- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x100f5 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x100f5 +- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x100c0 +- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x100c0 +- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x100f5 +- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x100f5 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 +- MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x58 +- /* GPIO for "link active" */ +- MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x3038 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 +- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- /* external 10 k pull up */ +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x40010878 +- /* external 10 k pull up */ +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x40010878 +- >; +- }; +- +- pinctrl_mdio: mdiogrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x100b1 +- MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0xb1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__PWM2_OUT 0x58 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x58 +- >; +- }; +- +- pinctrl_switch: switchgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0xb0 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- /* SoC internal pull up required */ +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- /* SoC internal pull up required */ +- MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b040 +- /* SoC internal pull up required */ +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b040 +- >; +- }; +- +- pinctrl_vcc_mmc: vccmmcgrp { +- fsl,pins = < +- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x58 +- >; +- }; +- +- pinctrl_vcc_mmc_io: vccmmciogrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x58 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-solidsense.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-solidsense.dtsi +deleted file mode 100644 +index 234827e554d0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-solidsense.dtsi ++++ /dev/null +@@ -1,160 +0,0 @@ +-/* +- * Copyright (C) 2021 Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-#include +- +-/ { +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_solidsense_leds>; +- +- /* Red/Green LED1 - next to WiFi SMA */ +- led-11 { +- color = ; +- function = LED_FUNCTION_INDICATOR; +- function-enumerator = <0>; +- gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; +- }; +- +- led-12 { +- color = ; +- function = LED_FUNCTION_INDICATOR; +- function-enumerator = <0>; +- gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; +- }; +- +- /* Red/Green LED2 - next to GPS SMA */ +- led-21 { +- color = ; +- function = LED_FUNCTION_INDICATOR; +- function-enumerator = <1>; +- gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; +- }; +- +- led-22 { +- color = ; +- function = LED_FUNCTION_INDICATOR; +- function-enumerator = <1>; +- gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&audio { +- status = "disabled"; +-}; +- +-&ecspi2 { +- status = "disabled"; +-}; +- +-&i2c3 { +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl-0 = <&pinctrl_hog>, <&pinctrl_solidsense_hog>; +- +- solidsense { +- pinctrl_solidsense_hog: solidsense-hog { +- fsl,pins = < +- /* Nordic RESET_N */ +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x400130b1 +- /* Nordic Chip 1 SWDIO - GPIO 125 */ +- MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x400130b1 +- /* Nordic Chip 1 SWDCLK - GPIO 59 */ +- /* already claimed in the HB2 hogs */ +- /* MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1 */ +- /* Nordic Chip 2 SWDIO - GPIO 81 */ +- MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x400130b1 +- /* Nordic Chip 2 SWCLK - GPIO 82 */ +- MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x400130b1 +- >; +- }; +- +- pinctrl_solidsense_leds: solidsense-leds { +- fsl,pins = < +- /* Red LED 1 - GPIO 58 */ +- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x400130b1 +- /* Green LED 1 - GPIO 55 */ +- MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x400130b1 +- /* Red LED 2 - GPIO 57 */ +- MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x400130b1 +- /* Green LED 2 - GPIO 56 */ +- MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x400130b1 +- >; +- }; +- +- pinctrl_solidsense_uart2: solidsense-uart2 { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_solidsense_uart3: solidsense-uart3 { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- >; +- }; +- }; +-}; +- +-&pwm1 { +- status = "disabled"; +-}; +- +-&sgtl5000 { +- status = "disabled"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_solidsense_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_solidsense_uart3>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-sr-som-brcm.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-sr-som-brcm.dtsi +deleted file mode 100644 +index b55af61dfeca..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-sr-som-brcm.dtsi ++++ /dev/null +@@ -1,144 +0,0 @@ +-/* +- * Copyright (C) 2013,2014 Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-#include +-/ { +- clk_brcm: brcm-clock { +- compatible = "gpio-gate-clock"; +- #clock-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_microsom_brcm_osc>; +- enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_brcm: brcm-reg { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio3 19 0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_microsom_brcm_reg>; +- regulator-name = "brcm_reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <200000>; +- }; +- +- usdhc1_pwrseq: usdhc1_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>, +- <&gpio6 0 GPIO_ACTIVE_LOW>; +- clocks = <&clk_brcm>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&iomuxc { +- microsom { +- pinctrl_microsom_brcm_bt: microsom-brcm-bt { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 +- MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x40013070 +- MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 +- >; +- }; +- +- pinctrl_microsom_brcm_osc: microsom-brcm-osc { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 +- >; +- }; +- +- pinctrl_microsom_brcm_reg: microsom-brcm-reg { +- fsl,pins = < +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x40013070 +- >; +- }; +- +- pinctrl_microsom_brcm_wifi: microsom-brcm-wifi { +- fsl,pins = < +- MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 +- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x40013070 +- MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 +- MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x40013070 +- >; +- }; +- +- pinctrl_microsom_uart4: microsom-uart4 { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_microsom_usdhc1: microsom-usdhc1 { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 +- >; +- }; +- }; +-}; +- +-/* UART4 - Connected to optional BRCM Wifi/BT/FM */ +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_microsom_brcm_bt &pinctrl_microsom_uart4>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-/* USDHC1 - Connected to optional BRCM Wifi/BT/FM */ +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_microsom_brcm_wifi &pinctrl_microsom_usdhc1>; +- bus-width = <4>; +- mmc-pwrseq = <&usdhc1_pwrseq>; +- keep-power-in-suspend; +- no-1-8-v; +- non-removable; +- vmmc-supply = <®_brcm>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-sr-som-emmc.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-sr-som-emmc.dtsi +deleted file mode 100644 +index 5f3b8baab20f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-sr-som-emmc.dtsi ++++ /dev/null +@@ -1,70 +0,0 @@ +-/* +- * Copyright (C) 2013,2014 Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-&iomuxc { +- microsom { +- pinctrl_microsom_usdhc3: microsom-usdhc3 { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 +- >; +- }; +- }; +-}; +- +-/* USDHC3 - eMMC */ +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_microsom_usdhc3>; +- bus-width = <8>; +- non-removable; +- vmmc-supply = <&vcc_3v3>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-sr-som-ti.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-sr-som-ti.dtsi +deleted file mode 100644 +index 352ac585ca6b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-sr-som-ti.dtsi ++++ /dev/null +@@ -1,171 +0,0 @@ +-/* +- * Copyright (C) 2013,2014 Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-#include +- +-/ { +- nvcc_sd1: regulator-nvcc-sd1 { +- compatible = "regulator-fixed"; +- regulator-always-on; +- regulator-name = "nvcc_sd1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_3v3>; +- }; +- +- clk_ti_wifi: ti-wifi-clock { +- /* This is a hack around the kernel - using "fixed clock" +- * results in the "pinctrl" properties being ignored, and +- * the clock not being output. Instead, use a gated clock +- * and the unrouted WL_XTAL_PU gpio. +- */ +- compatible = "gpio-gate-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_microsom_ti_clk>; +- enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; +- }; +- +- pwrseq_ti_wifi: ti-wifi-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_microsom_ti_wifi_en>; +- reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; +- post-power-on-delay-ms = <200>; +- clocks = <&clk_ti_wifi>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&iomuxc { +- microsom { +- pinctrl_microsom_ti_bt: microsom-ti-bt { +- fsl,pins = < +- /* BT_EN_SOC */ +- MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 +- >; +- }; +- +- pinctrl_microsom_ti_clk: microsom-ti-clk { +- fsl,pins = < +- /* EXT_32K */ +- MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 +- /* WL_XTAL_PU (unrouted) */ +- MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 +- >; +- }; +- +- pinctrl_microsom_ti_wifi_en: microsom-ti-wifi-en { +- fsl,pins = < +- /* WLAN_EN_SOC */ +- MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 +- >; +- }; +- +- pinctrl_microsom_ti_wifi_irq: microsom-ti-wifi-irq { +- fsl,pins = < +- /* WLAN_IRQ */ +- MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 +- >; +- }; +- +- pinctrl_microsom_uart4: microsom-uart4 { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_microsom_usdhc1: microsom-usdhc1 { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 +- >; +- }; +- }; +-}; +- +-/* UART4 - Connected to optional TI Wi-Fi/BT/FM */ +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_microsom_uart4>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "ti,wl1837-st"; +- clocks = <&clk_ti_wifi>; +- clock-names = "ext_clock"; +- enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_microsom_ti_bt>; +- }; +-}; +- +-/* USDHC1 - Connected to optional TI Wi-Fi/BT/FM */ +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_microsom_usdhc1>; +- bus-width = <4>; +- keep-power-in-suspend; +- mmc-pwrseq = <&pwrseq_ti_wifi>; +- cap-power-off-card; +- non-removable; +- vmmc-supply = <&vcc_3v3>; +- /* vqmmc-supply = <&nvcc_sd1>; - MMC layer doesn't like it! */ +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- wlcore@2 { +- compatible = "ti,wl1837"; +- reg = <2>; +- interrupts-extended = <&gpio6 4 IRQ_TYPE_LEVEL_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_microsom_ti_wifi_irq>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-sr-som.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-sr-som.dtsi +deleted file mode 100644 +index f86efd0ccc40..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-sr-som.dtsi ++++ /dev/null +@@ -1,148 +0,0 @@ +-/* +- * Copyright (C) 2013,2014 Russell King +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-#include +- +-/ { +- vcc_3v3: regulator-vcc-3v3 { +- compatible = "regulator-fixed"; +- regulator-always-on; +- regulator-name = "vcc_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; +- phy-mode = "rgmii-id"; +- +- /* +- * The PHY seems to require a long-enough reset duration to avoid +- * some rare issues where the PHY gets stuck in an inconsistent and +- * non-functional state at boot-up. 10ms proved to be fine . +- */ +- phy-reset-duration = <10>; +- phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* +- * The PHY can appear at either address 0 or 4 due to the +- * configuration (LED) pin not being pulled sufficiently. +- */ +- ethernet-phy@0 { +- reg = <0>; +- qca,clk-out-frequency = <125000000>; +- qca,smarteee-tw-us-1g = <24>; +- }; +- +- ethernet-phy@4 { +- reg = <4>; +- qca,clk-out-frequency = <125000000>; +- qca,smarteee-tw-us-1g = <24>; +- }; +- }; +-}; +- +-&iomuxc { +- microsom { +- pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- /* AR8035 reset */ +- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 +- /* AR8035 interrupt */ +- MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 +- /* GPIO16 -> AR8035 25MHz */ +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x13030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 +- /* AR8035 pin strapping: IO voltage: pull up */ +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- /* AR8035 pin strapping: PHYADDR#0: pull down */ +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 +- /* AR8035 pin strapping: PHYADDR#1: pull down */ +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 +- /* AR8035 pin strapping: MODE#1: pull up */ +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- /* AR8035 pin strapping: MODE#3: pull up */ +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- /* AR8035 pin strapping: MODE#0: pull down */ +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 +- +- /* +- * As the RMII pins are also connected to RGMII +- * so that an AR8030 can be placed, set these +- * to high-z with the same pulls as above. +- * Use the GPIO settings to avoid changing the +- * input select registers. +- */ +- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x03000 +- MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x03000 +- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x03000 +- >; +- }; +- +- pinctrl_microsom_uart1: microsom-uart1 { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_microsom_uart1>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-tqma6.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-tqma6.dtsi +deleted file mode 100644 +index b18b83ac6aee..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-tqma6.dtsi ++++ /dev/null +@@ -1,201 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Sascha Hauer, Pengutronix +- * Copyright 2013-2017 Markus Niebel +- */ +- +-#include +-#include +- +-/ { +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "supply-3p3v"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- +- m25p80: flash@0 { +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- m25p,fast-read; +- }; +-}; +- +-&iomuxc { +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- /* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */ +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b099 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb099 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb099 +- /* eCSPI1 SS1 */ +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0xb099 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899 +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b099 /* PMIC irq */ +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- >; +- }; +-}; +- +-&pmic { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio6>; +- interrupts = <10 IRQ_TYPE_LEVEL_LOW>; +- +- regulators { +- reg_vddcore: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-always-on; +- }; +- +- reg_vddsoc: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-always-on; +- }; +- +- reg_gen_3v3: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_ddr_1v5a: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-always-on; +- }; +- +- reg_ddr_1v5b: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_5v_600mA: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- regulator-always-on; +- }; +- +- reg_snvs_3v: vsnvs { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- +- reg_vrefddr: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_vgen1_1v5: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- /* not used */ +- }; +- +- reg_vgen2_1v2_eth: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- regulator-always-on; +- }; +- +- reg_vgen3_2v8: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_vgen4_1v8: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_vgen5_1v8_eth: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_vgen6_3v3: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +-}; +- +-/* eMMC */ +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- vmmc-supply = <®_3p3v>; +- non-removable; +- disable-wp; +- no-sd; +- no-sdio; +- bus-width = <8>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- mmccard: mmccard@0 { +- reg = <0>; +- compatible = "mmc-card"; +- broken-hpi; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-tqma6a.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-tqma6a.dtsi +deleted file mode 100644 +index b679bec78e6c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-tqma6a.dtsi ++++ /dev/null +@@ -1,28 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Sascha Hauer, Pengutronix +- * Copyright 2013-2017 Markus Niebel +- */ +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clock-frequency = <100000>; +- status = "okay"; +- +- pmic: pmic@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- }; +- +- sensor@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +- +- eeprom@50 { +- compatible = "st,24c64", "atmel,24c64"; +- reg = <0x50>; +- pagesize = <32>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-tqma6b.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-tqma6b.dtsi +deleted file mode 100644 +index 49c472285c06..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-tqma6b.dtsi ++++ /dev/null +@@ -1,28 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Sascha Hauer, Pengutronix +- * Copyright 2013-2017 Markus Niebel +- */ +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- clock-frequency = <100000>; +- status = "okay"; +- +- pmic: pmic@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- }; +- +- sensor@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +- +- eeprom@50 { +- compatible = "st,24c64", "atmel,24c64"; +- reg = <0x50>; +- pagesize = <32>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-ts4900.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-ts4900.dtsi +deleted file mode 100644 +index f88da757edda..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-ts4900.dtsi ++++ /dev/null +@@ -1,479 +0,0 @@ +-/* +- * Copyright 2015 Technologic Systems +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +- +-/ { +- aliases { +- ethernet0 = &fec; +- }; +- +- leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds1>; +- compatible = "gpio-leds"; +- +- green-led { +- label = "green-led"; +- gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- +- red-led { +- label = "red-led"; +- gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3p3v"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- status = "okay"; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- n25q064: flash@0 { +- compatible = "micron,n25q064", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- }; +-}; +- +-&ecspi2 { +- cs-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii"; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c1>; +- pinctrl-1 = <&pinctrl_i2c1_gpio>; +- scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; +- sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- +- isl12022: rtc@6f { +- compatible = "isil,isl12022"; +- reg = <0x6f>; +- }; +- +- gpio8: gpio@28 { +- compatible = "technologic,ts4900-gpio"; +- reg = <0x28>; +- #gpio-cells = <2>; +- gpio-controller; +- ngpio = <32>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c2>; +- pinctrl-1 = <&pinctrl_i2c2_gpio>; +- scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; +- sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard flash CS1# */ +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 +- MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 +- MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 +- MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 /* Offboard CS0# */ +- MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x100b1 /* FPGA CS1# */ +- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 /* FPGA_RESET# */ +- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* FPGA_DONE */ +- MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */ +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 /* FPGA_IRQ */ +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001b0a8 +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 +- MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b1 /* ETH_PHY_RESET */ +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1 /* OFF_BD_RESET# */ +- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 /* EN_USB_5V# */ +- MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b1 /* EN_LCD_3.3V */ +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */ +- MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 /* DIO_1 */ +- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b1 /* DIO_2 */ +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b1 /* DIO_3 */ +- MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b1 /* DIO_4 */ +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 /* DIO_5 */ +- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b1 /* DIO_7 */ +- MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b1 /* DIO_8 */ +- MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b1 /* DIO_9 */ +- MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* DIO_0 */ +- MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b1 /* DIO_6 */ +- MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b1 /* CPU_DIO_A */ +- MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b1 /* DIO_2 */ +- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b1 /* CPU_DIO_B */ +- MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1 /* BUS_ALE# */ +- MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1 /* DIO_15 */ +- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1 /* BUS_DIR */ +- MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 /* BUS_CS# */ +- MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* DIO_14 */ +- MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b1 /* DIO_16 */ +- MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b0b1 /* DIO_12 */ +- MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1 /* DIO_18 */ +- MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b1 /* DIO_19 */ +- MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1 /* DIO_20 */ +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b1 /* BUS_BHE# */ +- MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1 /* DIO_13 */ +- MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1 /* EIM_WAIT# */ +- MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b1 /* DIO_10 */ +- MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1 /* MUX_AD_00 */ +- MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1 /* MUX_AD_01 */ +- MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 /* MUX_AD_02 */ +- MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1 /* MUX_AD_03 */ +- MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 /* MUX_AD_04 */ +- MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 /* MUX_AD_05 */ +- MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1 /* MUX_AD_06 */ +- MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 /* MUX_AD_07 */ +- MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1 /* MUX_AD_08 */ +- MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1 /* MUX_AD_09 */ +- MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1 /* MUX_AD_10 */ +- MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1 /* MUX_AD_11 */ +- MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1 /* MUX_AD_12 */ +- MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1 /* MUX_AD_13 */ +- MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1 /* MUX_AD_14 */ +- MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1 /* MUX_AD_15 */ +- MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1 /* LCD_CLK */ +- MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b1 /* DE */ +- MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b1 /* Hsync */ +- MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b1 /* Vsync */ +- MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b1 +- MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c1_gpio: i2c1gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2_gpio: i2c2gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 +- >; +- }; +- +- pinctrl_leds1: leds1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /* RED_LED# */ +- MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 /* GREEN_LED# */ +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 +- MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 +- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ */ +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b1 /* EN_SD_POWER# */ +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- >; +- }; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-/* SD */ +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- vmmc-supply = <®_3p3v>; +- bus-width = <4>; +- fsl,wp-controller; +- status = "okay"; +-}; +- +-/* eMMC */ +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- vmmc-supply = <®_3p3v>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-ts7970.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-ts7970.dtsi +deleted file mode 100644 +index fded07f370b3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-ts7970.dtsi ++++ /dev/null +@@ -1,593 +0,0 @@ +-/* +- * Copyright 2015 Technologic Systems +- * Copyright 2017 Savoir-Faire Linux +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +- +-/ { +- leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds1>; +- compatible = "gpio-leds"; +- +- green-led { +- label = "green-led"; +- gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- +- red-led { +- label = "red-led"; +- gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- yel-led { +- label = "yellow-led"; +- gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- blue-led { +- label = "blue-led"; +- gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- en-usb-5v { +- label = "en-usb-5v"; +- gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- sel_dc_usb { +- label = "sel_dc_usb"; +- gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3p3v"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_can1_3v3: reg_can1_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "reg_can1_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_can2_3v3: en-reg_can2_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "reg_can2_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_wlan_vmmc: regulator_wlan_vmmc { +- compatible = "regulator-fixed"; +- regulator-name = "wlan_vmmc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio8 14 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <70000>; +- enable-active-high; +- }; +- +- sound-sgtl5000 { +- audio-codec = <&sgtl5000>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- compatible = "fsl,imx-audio-sgtl5000"; +- model = "On-board Codec"; +- mux-ext-port = <3>; +- mux-int-port = <1>; +- ssi-controller = <&ssi1>; +- }; +-}; +- +-&audmux { +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- xceiver-supply = <®_can1_3v3>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- xceiver-supply = <®_can2_3v3>; +- status = "okay"; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- n25q064: flash@0 { +- compatible = "micron,n25q064", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- }; +-}; +- +-&ecspi2 { +- cs-gpios = < +- &gpio5 31 GPIO_ACTIVE_LOW +- &gpio7 12 GPIO_ACTIVE_LOW +- &gpio5 18 GPIO_ACTIVE_LOW +- >; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii"; +- interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, +- <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; +- fsl,err006687-workaround-present; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c1>; +- pinctrl-1 = <&pinctrl_i2c1_gpio>; +- scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; +- sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- +- m41t00s: rtc@68 { +- compatible = "m41t00"; +- reg = <0x68>; +- }; +- +- isl12022: rtc@6f { +- compatible = "isl,isl12022"; +- reg = <0x6f>; +- }; +- +- gpio8: gpio@28 { +- compatible = "technologic,ts7970-gpio"; +- reg = <0x28>; +- #gpio-cells = <2>; +- gpio-controller; +- ngpio = <32>; +- }; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sgtl5000>; +- reg = <0x0a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c2>; +- pinctrl-1 = <&pinctrl_i2c2_gpio>; +- scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; +- sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard Flash CS */ +- >; +- }; +- +- pinctrl_ecspi2: ecspi2 { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 +- MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 +- MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 +- MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x100b1 /* FPGA_SPI_CS0 */ +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x100b1 /* FPGA_SPI_CS1 */ +- MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1 /* HD1_SPI_CS */ +- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b088 /* FPGA_RESET */ +- MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */ +- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b088 /* FPGA_IRQ_0 */ +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b088 /* FPGA_IRQ_1 */ +- >; +- }; +- +- pinctrl_enet: enet { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b088 +- MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b088 /* ETH_PHY_RESET */ +- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b088 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b088 +- MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b088 /* EN_CAN_1 */ +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b088 +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b088 +- MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b088 /* EN_CAN_2 */ +- >; +- }; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- /* Onboard */ +- MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b088 /* USB_HUB_RESET */ +- MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b088 /* SEL_DC_USB */ +- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b088 /* EN_USB_5V */ +- MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b088 /* JTAG_FPGA_TMS */ +- MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b088 /* JTAG_FPGA_TCK */ +- MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b088 /* JTAG_FPGA_TDO */ +- MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b088 /* JTAG_FPGA_TDI */ +- MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b088 /* GYRO_INT */ +- MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b088 /* MODBUS_FAULT */ +- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b088 /* BUS_DIR/JP_SD_BOOT */ +- MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b088 /* EN_MODBUS_24V */ +- MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b088 /* EN_MODBUS_3V */ +- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b088 /* I210_RESET */ +- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b088 /* EN_RTC_PWR */ +- MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b088 /* REVSTRAP1 */ +- +- /* Offboard */ +- MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b088 /* LCD_D09 */ +- MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b088 /* HD1_IRQ */ +- MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b088 /* LCD_D10 */ +- MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b088 /* LCD_D11 */ +- MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b088 /* BUS_BHE */ +- MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b088 /* BUS_ALE */ +- MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b088 /* BUS_CS */ +- MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b088 /* DIO_20 */ +- MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b088 /* BUS_WAIT */ +- MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b088 /* MUX_AD_00 */ +- MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b088 /* MUX_AD_01 */ +- MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b088 /* MUX_AD_02 */ +- MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b088 /* MUX_AD_03 */ +- MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b088 /* MUX_AD_04 */ +- MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b088 /* MUX_AD_05 */ +- MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b088 /* MUX_AD_06 */ +- MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b088 /* MUX_AD_07 */ +- MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b088 /* MUX_AD_08 */ +- MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b088 /* MUX_AD_09 */ +- MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b088 /* MUX_AD_10 */ +- MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b088 /* MUX_AD_11 */ +- MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b088 /* MUX_AD_12 */ +- MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b088 /* MUX_AD_13 */ +- MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b088 /* MUX_AD_14 */ +- MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b088 /* MUX_AD_15 */ +- +- /* Strapping only */ +- MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b088 +- MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b088 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c1_gpio: i2c1gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2_gpio: i2c2gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 +- >; +- }; +- +- pinctrl_leds1: leds1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b088 /* GREEN_LED */ +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b088 /* RED_LED */ +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b088 /* YEL_LED */ +- MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b088 /* IMX6_BLUE_LED */ +- >; +- }; +- +- pinctrl_sgtl5000: sgtl5000grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */ +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b088 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b088 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b088 +- MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b088 +- MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b088 +- MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b088 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b088 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b088 +- MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b088 +- MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b088 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b088 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b088 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b088 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b088 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 +- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ */ +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b088 /* EN_SD_POWER */ +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- >; +- }; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&snvs_rtc { +- status = "disabled"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "okay"; +-}; +- +-/* WIFI */ +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- vmmc-supply = <®_wlan_vmmc>; +- bus-width = <4>; +- non-removable; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- wlcore: wlcore@2 { +- compatible = "ti,wl1271"; +- reg = <2>; +- interrupt-parent = <&gpio1>; +- interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; +- ref-clock-frequency = <38400000>; +- }; +-}; +- +-/* SD */ +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- vmmc-supply = <®_3p3v>; +- bus-width = <4>; +- fsl,wp-controller; +- status = "okay"; +-}; +- +-/* eMMC */ +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- vmmc-supply = <®_3p3v>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-tx6-lcd.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-tx6-lcd.dtsi +deleted file mode 100644 +index 79f2354886b7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-tx6-lcd.dtsi ++++ /dev/null +@@ -1,251 +0,0 @@ +-/* +- * Copyright 2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/ { +- aliases { +- display = &display; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd1_pwr>; +- enable-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; +- power-supply = <®_3v3>; +- turn-on-delay-ms = <35>; +- /* +- * a poor man's way to create a 1:1 relationship between +- * the PWM value and the actual duty cycle +- */ +- brightness-levels = < 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100>; +- default-brightness-level = <50>; +- }; +- +- lcd_panel: lcd-panel { +- compatible = "edt,etm0700g0dh6"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd0_pwr>; +- enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; +- power-supply = <®_3v3>; +- backlight = <&backlight>; +- +- port { +- lcd_panel_in: endpoint { +- remote-endpoint = <&lcd_out>; +- }; +- }; +- }; +- +- display: disp0 { +- compatible = "fsl,imx-parallel-display"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_disp0_1>; +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- lcd_in: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lcd_out: endpoint { +- remote-endpoint = <&lcd_panel_in>; +- }; +- }; +- +- display-timings { +- VGA { +- clock-frequency = <25200000>; +- hactive = <640>; +- vactive = <480>; +- hback-porch = <48>; +- hsync-len = <96>; +- hfront-porch = <16>; +- vback-porch = <31>; +- vsync-len = <2>; +- vfront-porch = <12>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- +- ETV570 { +- u-boot,panel-name = "edt,et057090dhu"; +- clock-frequency = <25200000>; +- hactive = <640>; +- vactive = <480>; +- hback-porch = <114>; +- hsync-len = <30>; +- hfront-porch = <16>; +- vback-porch = <32>; +- vsync-len = <3>; +- vfront-porch = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- +- ET0350 { +- u-boot,panel-name = "edt,et0350g0dh6"; +- clock-frequency = <6413760>; +- hactive = <320>; +- vactive = <240>; +- hback-porch = <34>; +- hsync-len = <34>; +- hfront-porch = <20>; +- vback-porch = <15>; +- vsync-len = <3>; +- vfront-porch = <4>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- +- ET0430 { +- u-boot,panel-name = "edt,et0430g0dh6"; +- clock-frequency = <9009000>; +- hactive = <480>; +- vactive = <272>; +- hback-porch = <2>; +- hsync-len = <41>; +- hfront-porch = <2>; +- vback-porch = <2>; +- vsync-len = <10>; +- vfront-porch = <2>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- +- ET0500 { +- clock-frequency = <33264000>; +- hactive = <800>; +- vactive = <480>; +- hback-porch = <88>; +- hsync-len = <128>; +- hfront-porch = <40>; +- vback-porch = <33>; +- vsync-len = <2>; +- vfront-porch = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- +- ET0700 { /* same as ET0500 */ +- u-boot,panel-name = "edt,etm0700g0dh6"; +- clock-frequency = <33264000>; +- hactive = <800>; +- vactive = <480>; +- hback-porch = <88>; +- hsync-len = <128>; +- hfront-porch = <40>; +- vback-porch = <33>; +- vsync-len = <2>; +- vfront-porch = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- +- ETQ570 { +- clock-frequency = <6596040>; +- hactive = <320>; +- vactive = <240>; +- hback-porch = <38>; +- hsync-len = <30>; +- hfront-porch = <30>; +- vback-porch = <16>; +- vsync-len = <3>; +- vfront-porch = <4>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- +- CoMTFT { /* same as ET0700 but with inverted pixel clock */ +- u-boot,panel-name = "edt,etm0700g0edh6"; +- clock-frequency = <33264000>; +- hactive = <800>; +- vactive = <480>; +- hback-porch = <88>; +- hsync-len = <128>; +- hfront-porch = <40>; +- vback-porch = <33>; +- vsync-len = <2>; +- vfront-porch = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- }; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&lcd_in>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-tx6-lvds.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-tx6-lvds.dtsi +deleted file mode 100644 +index 2ca2eb37e14f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-tx6-lvds.dtsi ++++ /dev/null +@@ -1,286 +0,0 @@ +-/* +- * Copyright 2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/ { +- aliases { +- display = &lvds0; +- lvds0 = &lvds0; +- lvds1 = &lvds1; +- }; +- +- backlight0: backlight0 { +- compatible = "pwm-backlight"; +- pwms = <&pwm2 0 500000 0>; +- power-supply = <®_lcd0_pwr>; +- brightness-levels = < 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100>; +- default-brightness-level = <50>; +- }; +- +- backlight1: backlight1 { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 500000 0>; +- power-supply = <®_lcd1_pwr>; +- brightness-levels = < 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100>; +- default-brightness-level = <50>; +- }; +- +- lvds0_panel: lvds0-panel { +- compatible = "nlt,nl12880bc20-spwg-24"; +- backlight = <&backlight0>; +- power-supply = <®_3v3>; +- +- port { +- panel_in_lvds0: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +- +- lvds1_panel: lvds1-panel { +- compatible = "nlt,nl12880bc20-spwg-24"; +- backlight = <&backlight1>; +- power-supply = <®_3v3>; +- +- port { +- panel_in_lvds1: endpoint { +- remote-endpoint = <&lvds1_out>; +- }; +- }; +- }; +-}; +- +-&kpp { +- status = "disabled"; /* pad conflict with backlight1 PWM */ +-}; +- +-&ldb { +- status = "okay"; +- +- lvds0: lvds-channel@0 { +- fsl,data-width = <18>; +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in_lvds0>; +- }; +- }; +- +- display-timings { +- hsd100pxn1 { +- u-boot,panel-name = "hannstar,hsd100pxn1"; +- clock-frequency = <65000000>; +- hactive = <1024>; +- vactive = <768>; +- hback-porch = <220>; +- hfront-porch = <40>; +- vback-porch = <21>; +- vfront-porch = <7>; +- hsync-len = <60>; +- vsync-len = <10>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- +- VGA { +- clock-frequency = <25200000>; +- hactive = <640>; +- vactive = <480>; +- hback-porch = <48>; +- hfront-porch = <16>; +- vback-porch = <31>; +- vfront-porch = <12>; +- hsync-len = <96>; +- vsync-len = <2>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- +- nl12880bc20 { +- u-boot,panel-name = "nlt,nl12880bc20-spwg-24"; +- clock-frequency = <71000000>; +- hactive = <1280>; +- vactive = <800>; +- hback-porch = <50>; +- hfront-porch = <50>; +- vback-porch = <5>; +- vfront-porch = <5>; +- hsync-len = <60>; +- vsync-len = <13>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- +- ET0700 { +- u-boot,panel-name = "edt,etm0700g0dh6"; +- clock-frequency = <33264000>; +- hactive = <800>; +- vactive = <480>; +- hback-porch = <88>; +- hsync-len = <128>; +- hfront-porch = <40>; +- vback-porch = <33>; +- vsync-len = <2>; +- vfront-porch = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- +- ETV570 { +- u-boot,panel-name = "edt,et057090dhu"; +- clock-frequency = <25200000>; +- hactive = <640>; +- vactive = <480>; +- hback-porch = <114>; +- hsync-len = <30>; +- hfront-porch = <16>; +- vback-porch = <32>; +- vsync-len = <3>; +- vfront-porch = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- }; +- }; +- +- lvds1: lvds-channel@1 { +- fsl,data-width = <18>; +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds1_out: endpoint { +- remote-endpoint = <&panel_in_lvds1>; +- }; +- }; +- +- display-timings { +- hsd100pxn1 { +- clock-frequency = <65000000>; +- hactive = <1024>; +- vactive = <768>; +- hback-porch = <220>; +- hfront-porch = <40>; +- vback-porch = <21>; +- vfront-porch = <7>; +- hsync-len = <60>; +- vsync-len = <10>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- +- VGA { +- clock-frequency = <25200000>; +- hactive = <640>; +- vactive = <480>; +- hback-porch = <48>; +- hfront-porch = <16>; +- vback-porch = <31>; +- vfront-porch = <12>; +- hsync-len = <96>; +- vsync-len = <2>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- +- nl12880bc20 { +- clock-frequency = <71000000>; +- hactive = <1280>; +- vactive = <800>; +- hback-porch = <50>; +- hfront-porch = <50>; +- vback-porch = <5>; +- vfront-porch = <5>; +- hsync-len = <60>; +- vsync-len = <13>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- }; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-®_lcd0_pwr { +- status = "okay"; +-}; +- +-®_lcd1_pwr { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-tx6-mb7.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-tx6-mb7.dtsi +deleted file mode 100644 +index 410972e1dca9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-tx6-mb7.dtsi ++++ /dev/null +@@ -1,96 +0,0 @@ +-/* +- * Copyright 2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/ { +- backlight0 { +- pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; +- turn-on-delay-ms = <35>; +- power-supply = <®_lcd1_pwr>; +- }; +- +- backlight1 { +- pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; +- turn-on-delay-ms = <35>; +- power-supply = <®_lcd1_pwr>; +- }; +- +- lcd-panel { +- compatible = "edt,et057090dhu"; +- pixelclk-active = <0>; +- }; +- +- lvds0-panel { +- compatible = "edt,etml1010g0dka"; +- pixelclk-active = <0>; +- }; +- +- lvds1-panel { +- compatible = "edt,etml1010g0dka"; +- pixelclk-active = <0>; +- }; +-}; +- +-&can1 { +- status = "disabled"; +-}; +- +-&can2 { +- xceiver-supply = <®_3v3>; +-}; +- +-&ds1339 { +- /* +- * The backup voltage of the module internal RTC is not wired +- * by default on the MB7, so disable that RTC chip. +- */ +- status = "disabled"; +-}; +- +-&i2c3 { +- rtc: mcp7940x@6f { +- compatible = "microchip,mcp7940x"; +- reg = <0x6f>; +- }; +-}; +- +-®_lcd0_pwr { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-tx6.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-tx6.dtsi +deleted file mode 100644 +index 362e65ccaa78..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-tx6.dtsi ++++ /dev/null +@@ -1,809 +0,0 @@ +-/* +- * Copyright 2014-2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- aliases { +- can0 = &can2; +- can1 = &can1; +- ethernet0 = &fec; +- lcdif-23bit-pins-a = &pinctrl_disp0_1; +- lcdif-24bit-pins-a = &pinctrl_disp0_2; +- pwm0 = &pwm1; +- pwm1 = &pwm2; +- reg-can-xcvr = ®_can_xcvr; +- stk5led = &user_led; +- usbotg = &usbotg; +- sdhc0 = &usdhc1; +- sdhc1 = &usdhc2; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0>; /* will be filled by U-Boot */ +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mclk: clock@0 { +- compatible = "fixed-clock"; +- reg = <0>; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "Power Button"; +- gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- user_led: user { +- label = "Heartbeat"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_user_led>; +- gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- reg_3v3_etn: regulator-3v3-etn { +- compatible = "regulator-fixed"; +- regulator-name = "3V3_ETN"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_etnphy_power>; +- gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_2v5: regulator-2v5 { +- compatible = "regulator-fixed"; +- regulator-name = "2V5"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_can_xcvr: regulator-can-xcvr { +- compatible = "regulator-fixed"; +- regulator-name = "CAN XCVR"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan_xcvr>; +- gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; +- }; +- +- reg_lcd0_pwr: regulator-lcd0-pwr { +- compatible = "regulator-fixed"; +- regulator-name = "LCD0 POWER"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd0_pwr>; +- gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- status = "disabled"; +- }; +- +- reg_lcd1_pwr: regulator-lcd1-pwr { +- compatible = "regulator-fixed"; +- regulator-name = "LCD1 POWER"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd1_pwr>; +- gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- status = "disabled"; +- }; +- +- reg_usbh1_vbus: regulator-usbh1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usbh1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1_vbus>; +- gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usbotg_vbus: regulator-usbotg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usbotg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg_vbus>; +- gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sound { +- compatible = "karo,imx6qdl-tx6-sgtl5000", +- "simple-audio-card"; +- simple-audio-card,name = "imx6qdl-tx6-sgtl5000-audio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&codec_dai>; +- simple-audio-card,frame-master = <&codec_dai>; +- simple-audio-card,widgets = +- "Microphone", "Mic Jack", +- "Line", "Line In", +- "Line", "Line Out", +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- +- cpu_dai: simple-audio-card,cpu { +- sound-dai = <&ssi1>; +- }; +- +- codec_dai: simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- }; +- }; +-}; +- +-&audmux { +- status = "okay"; +- +- ssi1 { +- fsl,audmux-port = <0>; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_SYN | +- IMX_AUDMUX_V2_PTCR_TFSEL(4) | +- IMX_AUDMUX_V2_PTCR_TCSEL(4) | +- IMX_AUDMUX_V2_PTCR_TFSDIR | +- IMX_AUDMUX_V2_PTCR_TCLKDIR) +- IMX_AUDMUX_V2_PDCR_RXDSEL(4) +- >; +- }; +- +- pins5 { +- fsl,audmux-port = <4>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN +- IMX_AUDMUX_V2_PDCR_RXDSEL(0) +- >; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- xceiver-supply = <®_can_xcvr>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- xceiver-supply = <®_can_xcvr>; +- status = "okay"; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = < +- &gpio2 30 GPIO_ACTIVE_HIGH +- &gpio3 19 GPIO_ACTIVE_HIGH +- >; +- status = "disabled"; +- +- spidev0: spi@0 { +- compatible = "spidev"; +- reg = <0>; +- spi-max-frequency = <54000000>; +- }; +- +- spidev1: spi@1 { +- compatible = "spidev"; +- reg = <1>; +- spi-max-frequency = <54000000>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>; +- clocks = <&clks IMX6QDL_CLK_ENET>, +- <&clks IMX6QDL_CLK_ENET>, +- <&clks IMX6QDL_CLK_ENET_REF>, +- <&clks IMX6QDL_CLK_ENET_REF>; +- clock-names = "ipg", "ahb", "ptp", "enet_out"; +- phy-mode = "rmii"; +- phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; +- phy-reset-post-delay = <10>; +- phy-handle = <&etnphy>; +- phy-supply = <®_3v3_etn>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- etnphy: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_etnphy_int>; +- interrupt-parent = <&gpio7>; +- interrupts = <1 IRQ_TYPE_EDGE_FALLING>; +- }; +- }; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- nand-on-flash-bbt; +- fsl,no-blockmark-swap; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c1>; +- pinctrl-1 = <&pinctrl_i2c1_gpio>; +- scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; +- sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; +- clock-frequency = <400000>; +- status = "okay"; +- +- ds1339: rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- trickle-resistor-ohms = <250>; +- trickle-diode-disable; +- }; +-}; +- +-&i2c3 { +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c3>; +- pinctrl-1 = <&pinctrl_i2c3_gpio>; +- scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; +- sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; +- clock-frequency = <400000>; +- status = "okay"; +- +- sgtl5000: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- #sound-dai-cells = <0>; +- reg = <0x0a>; +- VDDA-supply = <®_2v5>; +- VDDIO-supply = <®_3v3>; +- clocks = <&mclk>; +- }; +- +- polytouch: edt-ft5x06@38 { +- compatible = "edt,edt-ft5x06"; +- reg = <0x38>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_edt_ft5x06>; +- interrupt-parent = <&gpio6>; +- interrupts = <15 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; +- wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; +- wakeup-source; +- }; +- +- touchscreen: tsc2007@48 { +- compatible = "ti,tsc2007"; +- reg = <0x48>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tsc2007>; +- interrupt-parent = <&gpio3>; +- interrupts = <26 0>; +- gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; +- ti,x-plate-ohms = <660>; +- wakeup-source; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */ +- >; +- }; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */ +- MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */ +- MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */ +- MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */ +- >; +- }; +- +- pinctrl_disp0_1: disp0grp-1 { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 +- /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */ +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 +- >; +- }; +- +- pinctrl_disp0_2: disp0grp-2 { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0 +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0 +- MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0 +- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */ +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */ +- >; +- }; +- +- pinctrl_edt_ft5x06: edt-ft5x06grp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */ +- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */ +- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */ +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 +- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 +- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 +- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 +- >; +- }; +- +- pinctrl_enet_mdio: enet-mdiogrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- >; +- }; +- +- pinctrl_etnphy_int: etnphy-intgrp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */ +- >; +- }; +- +- pinctrl_etnphy_power: etnphy-pwrgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */ +- >; +- }; +- +- pinctrl_etnphy_rst: etnphy-rstgrp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */ +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 +- MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan_xcvr: flexcan-xcvrgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */ +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 +- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 +- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 +- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 +- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 +- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 +- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 +- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 +- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 +- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 +- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 +- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 +- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 +- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 +- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c1_gpio: i2c1-gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3_gpio: i2c3-gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 +- >; +- }; +- +- pinctrl_kpp: kppgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1 +- MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1 +- MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1 +- MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1 +- MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1 +- MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1 +- MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1 +- MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1 +- >; +- }; +- +- pinctrl_lcd0_pwr: lcd0-pwrgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */ +- >; +- }; +- +- pinctrl_lcd1_pwr: lcd-pwrgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */ +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_tsc2007: tsc2007grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */ +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1_rtscts: uart1_rtsctsgrp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1 +- MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2_rtscts: uart2_rtsctsgrp { +- fsl,pins = < +- MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 +- MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3_rtscts: uart3_rtsctsgrp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1 +- MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_usbh1_vbus: usbh1-vbusgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */ +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059 +- >; +- }; +- +- pinctrl_usbotg_vbus: usbotg-vbusgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */ +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1 +- MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1 +- MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */ +- >; +- }; +- +- pinctrl_user_led: user-ledgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */ +- >; +- }; +-}; +- +-&kpp { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_kpp>; +- /* sample keymap */ +- /* row/col 0,1 are mapped to KPP row/col 6,7 */ +- linux,keymap = < +- MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */ +- MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */ +- MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */ +- MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */ +- MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */ +- MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */ +- MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */ +- MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */ +- MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */ +- MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */ +- MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */ +- >; +- status = "okay"; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "disabled"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usbh1_vbus>; +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usbotg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- dr_mode = "peripheral"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- bus-width = <4>; +- no-1-8-v; +- cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; +- fsl,wp-controller; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- no-1-8-v; +- cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; +- fsl,wp-controller; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-udoo.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-udoo.dtsi +deleted file mode 100644 +index ccfa8e320be6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-udoo.dtsi ++++ /dev/null +@@ -1,327 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- * +- * Author: Fabio Estevam +- */ +- +-#include +- +-/ { +- aliases { +- backlight = &backlight; +- panelchan = &panelchan; +- panel7 = &panel7; +- touchscreenp7 = &touchscreenp7; +- }; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- backlight: backlight { +- compatible = "gpio-backlight"; +- gpios = <&gpio1 4 0>; +- default-on; +- status = "disabled"; +- }; +- +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- gpios = <&gpio2 4 0>; +- pinctrl-0 = <&pinctrl_power_off>; +- pinctrl-names = "default"; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- panel7: panel7 { +- /* +- * in reality it is a -20t (parallel) model, +- * but with LVDS bridge chip attached, +- * so it is equivalent to -19t model in drive +- * characteristics +- */ +- compatible = "urt,umsh-8596md-19t"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_panel>; +- power-supply = <®_panel>; +- backlight = <&backlight>; +- status = "disabled"; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_usb_h1_vbus: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "usb_h1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */ +- gpio = <&gpio7 12 0>; +- }; +- +- reg_panel: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "lcd_panel"; +- enable-active-high; +- gpio = <&gpio1 2 0>; +- }; +- }; +- +- sound { +- compatible = "fsl,imx6q-udoo-ac97", +- "fsl,imx-audio-ac97"; +- model = "fsl,imx6q-udoo-ac97"; +- audio-cpu = <&ssi1>; +- audio-routing = +- "RX", "Mic Jack", +- "Headphone Jack", "TX"; +- mux-int-port = <1>; +- mux-ext-port = <6>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- touchscreenp7: touchscreenp7@55 { +- compatible = "sitronix,st1232"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_touchscreenp7>; +- reg = <0x55>; +- interrupt-parent = <&gpio1>; +- interrupts = <13 8>; +- gpios = <&gpio1 15 0>; +- status = "disabled"; +- }; +-}; +- +-&iomuxc { +- imx6q-udoo { +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1 +- >; +- }; +- +- pinctrl_panel: panelgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x70 +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x70 +- >; +- }; +- +- pinctrl_power_off: poweroffgrp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30 +- >; +- }; +- +- pinctrl_touchscreenp7: touchscreenp7grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x70 +- MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbh: usbhgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 +- MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 +- >; +- }; +- +- pinctrl_usbotg: usbotg { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x17059 +- MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 +- >; +- }; +- +- pinctrl_ac97_running: ac97running { +- fsl,pins = < +- MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 +- MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x1b0b0 +- MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 +- MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 +- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +- >; +- }; +- +- pinctrl_ac97_warm_reset: ac97warmreset { +- fsl,pins = < +- MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 +- MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 +- MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 +- MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 +- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +- >; +- }; +- +- pinctrl_ac97_reset: ac97reset { +- fsl,pins = < +- MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 +- MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 +- MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 +- MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 +- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +- >; +- }; +- }; +-}; +- +-&ldb { +- status = "okay"; +- +- panelchan: lvds-channel@0 { +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbh1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh>; +- vbus-supply = <®_usb_h1_vbus>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- status = "okay"; +-}; +- +-&usbotg { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&audmux { +- status = "okay"; +-}; +- +-&ssi1 { +- cell-index = <0>; +- fsl,mode = "ac97-slave"; +- pinctrl-names = "ac97-running", "ac97-reset", "ac97-warm-reset"; +- pinctrl-0 = <&pinctrl_ac97_running>; +- pinctrl-1 = <&pinctrl_ac97_reset>; +- pinctrl-2 = <&pinctrl_ac97_warm_reset>; +- ac97-gpios = <&gpio4 19 0 &gpio4 18 0 &gpio2 30 0>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-var-dart.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-var-dart.dtsi +deleted file mode 100644 +index c41cac502bac..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-var-dart.dtsi ++++ /dev/null +@@ -1,504 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Support for Variscite DART-MX6 Module +- * +- * Copyright 2017 BayLibre, SAS +- * Author: Neil Armstrong +- */ +- +-#include +-#include +- +-/ { +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_wl18xx_vmmc: regulator-wl18xx { +- compatible = "regulator-fixed"; +- regulator-name = "vwl1807"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- startup-delay-us = <70000>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +- +- ssi2 { +- fsl,audmux-port = <1>; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_SYN | +- IMX_AUDMUX_V2_PTCR_TFSDIR | +- IMX_AUDMUX_V2_PTCR_TFSEL(2) | +- IMX_AUDMUX_V2_PTCR_TCLKDIR | +- IMX_AUDMUX_V2_PTCR_TCSEL(2)) +- IMX_AUDMUX_V2_PDCR_RXDSEL(2) +- >; +- }; +- +- aud3 { +- fsl,audmux-port = <2>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN +- IMX_AUDMUX_V2_PDCR_RXDSEL(1) +- >; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- status = "disabled"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- status = "disabled"; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "disabled"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii"; +- status = "disabled"; +-}; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hdmicec>; +- ddc-i2c-bus = <&i2c1>; +- status = "disabled"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "disabled"; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- pmic@8 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3950000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +- +- tlv320aic3106: codec@1b { +- compatible = "ti,tlv320aic3106"; +- reg = <0x1b>; +- #sound-dai-cells = <0>; +- DRVDD-supply = <®_3p3v>; +- AVDD-supply = <®_3p3v>; +- IOVDD-supply = <®_3p3v>; +- DVDD-supply = <®_3p3v>; +- ai3x-ocmv = <0>; +- reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_audmux: audmux { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- /* Audio Clock */ +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 +- >; +- }; +- +- pinctrl_bt: bt { +- fsl,pins = < +- /* Bluetooth enable */ +- MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b1 +- /* Bluetooth Slow Clock */ +- MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x000b0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 +- /* SPI1 CS0 */ +- MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 +- /* SPI1 CS1 */ +- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 +- MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_hdmicec: hdmicecgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- /* PMIC INT */ +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 +- MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 +- MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 +- /* WL_EN */ +- MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x17071 +- /* WL_IRQ */ +- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x17071 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1grp100mhz { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1grp200mhz { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170F9 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100F9 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170F9 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170F9 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170F9 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170F9 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- >; +- }; +-}; +- +-&pcie { +- fsl,tx-swing-full = <103>; +- fsl,tx-swing-low = <103>; +- reset-gpio = <&gpio4 11 GPIO_ACTIVE_LOW>; +- status = "disabled"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- status = "disabled"; +-}; +- +-®_arm { +- vin-supply = <&sw1a_reg>; +-}; +- +-®_pu { +- vin-supply = <&sw1c_reg>; +-}; +- +-®_soc { +- vin-supply = <&sw1c_reg>; +-}; +- +-&snvs_poweroff { +- status = "okay"; +-}; +- +-&ssi2 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "disabled"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2 &pinctrl_bt>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "ti,wl1835-st"; +- enable-gpios = <&gpio6 18 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "disabled"; +-}; +- +-&usbh1 { +- status = "disabled"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- status = "disabled"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- bus-width = <4>; +- vmmc-supply = <®_wl18xx_vmmc>; +- non-removable; +- wakeup-source; +- keep-power-in-suspend; +- cap-power-off-card; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- wlcore: wlcore@2 { +- compatible = "ti,wl1835"; +- reg = <2>; +- interrupt-parent = <&gpio6>; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; +- ref-clock-frequency = <38400000>; +- }; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- no-1-8-v; +- keep-power-in-suspend; +- wakeup-source; +- status = "disabled"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- non-removable; +- keep-power-in-suspend; +- wakeup-source; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-vicut1.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-vicut1.dtsi +deleted file mode 100644 +index b9e305774fed..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-vicut1.dtsi ++++ /dev/null +@@ -1,842 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (c) 2014 Protonic Holland +- * Copyright (c) 2020 Oleksij Rempel , Pengutronix +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- chosen { +- stdout-path = &uart4; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_backlight>; +- pwms = <&pwm1 0 5000000 0>; +- brightness-levels = <0 16 64 255>; +- num-interpolated-steps = <16>; +- default-brightness-level = <1>; +- power-supply = <®_3v3>; +- enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; +- }; +- +- connector { +- compatible = "composite-video-connector"; +- label = "Composite0"; +- sdtv-standards = ; +- +- port { +- comp0_out: endpoint { +- remote-endpoint = <&tvp5150_comp0_in>; +- }; +- }; +- }; +- +- counter-0 { +- compatible = "interrupt-counter"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_counter0>; +- gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +- }; +- +- counter-1 { +- compatible = "interrupt-counter"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_counter1>; +- gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +- }; +- +- counter-2 { +- compatible = "interrupt-counter"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_counter2>; +- gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- +- power { +- label = "Power Button"; +- gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds>; +- +- led-0 { +- label = "LED_DI0_DEBUG_0"; +- function = LED_FUNCTION_HEARTBEAT; +- gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-1 { +- label = "LED_DI0_DEBUG_1"; +- function = LED_FUNCTION_DISK; +- gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "disk-activity"; +- }; +- +- led-2 { +- label = "POWER_LED"; +- function = LED_FUNCTION_POWER; +- gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- panel { +- compatible = "kyo,tcg121xglp"; +- backlight = <&backlight>; +- power-supply = <®_3v3>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +- +- reg_1v8: regulator-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_h1_vbus: regulator-h1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "h1-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_otg_vbus: regulator-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "otg-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_wifi: regulator-wifi { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wifi_npd>; +- regulator-name = "wifi"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- startup-delay-us = <70000>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "prti6q-sgtl5000"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,widgets = +- "Microphone", "Microphone Jack", +- "Line", "Line In Jack", +- "Headphone", "Headphone Jack", +- "Speaker", "External Speaker"; +- simple-audio-card,routing = +- "MIC_IN", "Microphone Jack", +- "LINE_IN", "Line In Jack", +- "Headphone Jack", "HP_OUT", +- "External Speaker", "LINE_OUT"; +- +- simple-audio-card,cpu { +- sound-dai = <&ssi1>; +- system-clock-frequency = <0>; /* Do NOT call fsl_ssi_set_dai_sysclk! */ +- }; +- +- simple-audio-card,codec { +- sound-dai = <&codec>; +- bitclock-master; +- frame-master; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +- +- mux-ssi1 { +- fsl,audmux-port = <0>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN 0 +- IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 +- IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 +- IMX_AUDMUX_V2_PTCR_TFSDIR 0 +- IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) +- >; +- }; +- +- mux-pins3 { +- fsl,audmux-port = <2>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) +- 0 IMX_AUDMUX_V2_PDCR_TXRXEN +- >; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can2>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-handle = <&rgmii_phy>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Microchip KSZ9031RNX PHY */ +- rgmii_phy: ethernet-phy@0 { +- reg = <0>; +- interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- reset-deassert-us = <300>; +- }; +- }; +-}; +- +-&gpio1 { +- gpio-line-names = +- "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", +- "CAM2_MIRROR", "", "", "SMBALERT", +- "DEBUG_0", "DEBUG_1", "SDIO_SCK", "SDIO_CMD", "SDIO_D3", +- "SDIO_D2", "SDIO_D1", "SDIO_D0", +- "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", +- "SD1_DATA3", "", "", +- "", "ETH_RESET", "WIFI_PD", "WIFI_BT_RST", "ETH_INT", "", +- "WL_IRQ", "ETH_MDC"; +-}; +- +-&gpio2 { +- gpio-line-names = +- "count0", "count1", "count2", "", "", "", "", "", +- "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4", +- "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", +- "", "", "", "", "", "", "", "ON_SWITCH", +- "POWER_LED", "", "ECSPI2_SS0", "", "", "", "", ""; +-}; +- +-&gpio3 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", +- "CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio4 { +- gpio-line-names = +- "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", +- "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", +- "CAN2_SR", "CAN2_TX", "CAN2_RX", +- "LED_DI0_DEBUG_0", "LED_DI0_DEBUG_1", "", "", "", "", "", "", +- "", "", "", "", "BL_EN", "BL_PWM", "", ""; +-}; +- +-&gpio5 { +- gpio-line-names = +- "", "", "", "", "", "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_W_DIS", +- "PCIE_RESET", "", "", "", "", "", "", "", +- "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", +- "I2S_BITCLK", "I2S_DOUT", +- "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", +- "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; +-}; +- +-&gpio6 { +- gpio-line-names = +- "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", +- "ITU656_D6", "ITU656_D7", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", +- "RGMII_TD3", +- "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", +- "RGMII_RD2", "RGMII_RD3", "", ""; +-}; +- +-&gpio7 { +- gpio-line-names = +- "EMMC_DAT5", "EMMC_DAT4", "EMMC_CMD", "EMMC_CLK", "EMMC_DAT0", +- "EMMC_DAT1", "EMMC_DAT2", "EMMC_DAT3", +- "EMMC_RST", "", "", "", "CAM_DETECT", "", "", "", +- "", "EMMC_DAT7", "EMMC_DAT6", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- codec: audio-codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0xa>; +- #sound-dai-cells = <0>; +- clocks = <&clks 201>; +- VDDA-supply = <®_3v3>; +- VDDIO-supply = <®_3v3>; +- VDDD-supply = <®_1v8>; +- }; +- +- video-decoder@5c { +- compatible = "ti,tvp5150"; +- reg = <0x5c>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tvp5150_comp0_in: endpoint { +- remote-endpoint = <&comp0_out>; +- }; +- }; +- +- /* Output port 2 is video output pad */ +- port@2 { +- reg = <2>; +- +- tvp5151_to_ipu1_csi0_mux: endpoint { +- remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- adc@49 { +- compatible = "ti,ads1015"; +- reg = <0x49>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@4 { +- reg = <4>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- +- channel@5 { +- reg = <5>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- +- channel@6 { +- reg = <6>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- +- channel@7 { +- reg = <7>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- }; +- +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- +- temperature-sensor@70 { +- compatible = "ti,tmp103"; +- reg = <0x70>; +- }; +-}; +- +-&ipu1_csi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ipu1_csi0>; +- status = "okay"; +-}; +- +-&ipu1_csi0_mux_from_parallel_sensor { +- remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; +-}; +- +-&ldb { +- status = "okay"; +- +- lvds-channel@0 { +- status = "okay"; +- +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&ssi1 { +- #sound-dai-cells = <0>; +- fsl,mode = "ac97-slave"; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_h1_vbus>; +- pinctrl-names = "default"; +- phy_type = "utmi"; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- phy_type = "utmi"; +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- disable-wp; +- cap-sd-highspeed; +- no-mmc; +- no-sdio; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- vmmc-supply = <®_wifi>; +- non-removable; +- cap-power-off-card; +- keep-power-in-suspend; +- no-1-8-v; +- no-mmc; +- no-sd; +- status = "okay"; +- +- wifi { +- compatible = "ti,wl1271"; +- interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>; +- ref-clock-frequency = "38400000"; +- tcxo-clock-frequency = "19200000"; +- }; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- no-sd; +- no-sdio; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- /* SGTL5000 sys_mclk */ +- MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- >; +- }; +- +- pinctrl_backlight: backlightgrp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 +- >; +- }; +- +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 +- /* CAN1_SR */ +- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 +- /* CAN1_TERM */ +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 +- >; +- }; +- +- pinctrl_can2: can2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 +- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 +- /* CAN2_SR */ +- MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 +- >; +- }; +- +- pinctrl_counter0: counter0grp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000 +- >; +- }; +- +- pinctrl_counter1: counter1grp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000 +- >; +- }; +- +- pinctrl_counter2: counter2grp { +- fsl,pins = < +- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- /* CS */ +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 +- /* Phy reset */ +- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 +- >; +- }; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- /* ITU656_nRESET */ +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +- /* CAM1_MIRROR */ +- MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 +- /* CAM2_MIRROR */ +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 +- /* CAM_nDETECT */ +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 +- /* nON_SWITCH */ +- MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 +- /* ISB_IN1 */ +- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 +- /* ISB_nIN2 */ +- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 +- /* WARN_LIGHT */ +- MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0 +- /* ON2_FB */ +- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 +- /* YACO_nIRQ */ +- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 +- /* YACO_BOOT0 */ +- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 +- /* YACO_nRESET */ +- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 +- /* FORCE_ON1 */ +- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +- /* AUDIO_nRESET */ +- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 +- /* ITU656_nPDN */ +- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 +- +- /* HW revision detect */ +- /* REV_ID0 */ +- MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 +- /* REV_ID1 */ +- MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 +- /* REV_ID2 */ +- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 +- /* REV_ID3 */ +- MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 +- /* REV_ID4 */ +- MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 +- +- /* New in HW revision 1 */ +- /* ON1_FB */ +- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 +- /* DIP1_FB */ +- MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 +- +- /* New in UT2: FIXME: ISB PWM should start off, PD */ +- /* ISB_LED_PWM */ +- MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x130b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_ipu1_csi0: ipu1csi0grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 +- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 +- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 +- >; +- }; +- +- pinctrl_leds: ledsgrp { +- fsl,pins = < +- /* DEBUG0 */ +- MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 +- /* DEBUG1 */ +- MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 +- /* POWER_LED */ +- MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 +- >; +- }; +- +- /* YaCO AUX Uart */ +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 +- >; +- }; +- +- /* YaCO Touchscreen UART */ +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 +- /* power enable, high active */ +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 +- MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 +- /* WL12xx IRQ */ +- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 +- >; +- }; +- +- pinctrl_wifi_npd: wifinpdgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-wandboard-revb1.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-wandboard-revb1.dtsi +deleted file mode 100644 +index e781a45785ed..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-wandboard-revb1.dtsi ++++ /dev/null +@@ -1,36 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright 2013 Freescale Semiconductor, Inc. +-// +-// Author: Fabio Estevam +- +-#include "imx6qdl-wandboard.dtsi" +- +-&iomuxc { +- pinctrl-0 = <&pinctrl_hog>; +- +- imx6qdl-wandboard { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */ +- MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ +- MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x0f0b0 /* WL_REF_ON */ +- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x0f0b0 /* WL_RST_N */ +- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON */ +- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */ +- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */ +- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */ +- MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 /* BT_ON */ +- MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 /* BT_WAKE */ +- MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */ +- >; +- }; +- }; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- non-removable; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-wandboard-revc1.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-wandboard-revc1.dtsi +deleted file mode 100644 +index 3874e74703f0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-wandboard-revc1.dtsi ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright 2013 Freescale Semiconductor, Inc. +-// +-// Author: Fabio Estevam +- +-#include "imx6qdl-wandboard.dtsi" +- +-&iomuxc { +- pinctrl-0 = <&pinctrl_hog>; +- +- imx6qdl-wandboard { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */ +- MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ +- MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x0f0b0 /* WIFI_ON (reset, active low) */ +- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON (unused) */ +- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE, input */ +- MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x0f0b0 /* GPIO5_IO31 (Wifi Power Enable) */ +- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE (unused) */ +- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x80000000 /* BT_ON */ +- MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x80000000 /* BT_WAKE */ +- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x80000000 /* BT_HOST_WAKE */ +- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */ +- >; +- }; +- }; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-wandboard-revd1.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-wandboard-revd1.dtsi +deleted file mode 100644 +index bf86b639fdac..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-wandboard-revd1.dtsi ++++ /dev/null +@@ -1,193 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright 2013 Freescale Semiconductor, Inc. +-// +-// Author: Fabio Estevam +- +-#include "imx6qdl-wandboard.dtsi" +- +-/ { +- reg_eth_phy: regulator-eth-phy { +- compatible = "regulator-fixed"; +- regulator-name = "ETH_PHY"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio7 13 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- pmic: pfuze100@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&fec { +- phy-supply = <®_eth_phy>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-0 = <&pinctrl_hog>; +- +- imx6qdl-wandboard { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USDHC1 CD */ +- MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ +- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */ +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 +- MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_spdif: spdifgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 +- >; +- }; +- }; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- no-1-8-v; +- non-removable; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-wandboard.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-wandboard.dtsi +deleted file mode 100644 +index ec6fba5ee8fd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-wandboard.dtsi ++++ /dev/null +@@ -1,379 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- * +- * Author: Fabio Estevam +- */ +- +-#include +- +-/ { +- chosen { +- stdout-path = &uart1; +- }; +- +- sound { +- compatible = "fsl,imx6-wandboard-sgtl5000", +- "fsl,imx-audio-sgtl5000"; +- model = "imx6-wandboard-sgtl5000"; +- ssi-controller = <&ssi1>; +- audio-codec = <&codec>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <3>; +- }; +- +- sound-spdif { +- compatible = "fsl,imx-audio-spdif"; +- model = "imx-spdif"; +- spdif-controller = <&spdif>; +- spdif-out; +- }; +- +- reg_1p5v: regulator-1p5v { +- compatible = "regulator-fixed"; +- regulator-name = "1P5V"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- reg_2p8v: regulator-2p8v { +- compatible = "regulator-fixed"; +- regulator-name = "2P8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- reg_2p5v: regulator-2p5v { +- compatible = "regulator-fixed"; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_otg_vbus: regulator-usbotgvbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotgvbus>; +- gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c1>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c1>; +- pinctrl-1 = <&pinctrl_i2c1_gpio>; +- scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c2>; +- pinctrl-1 = <&pinctrl_i2c2_gpio>; +- scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +- +- codec: sgtl5000@a { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mclk>; +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&clks IMX6QDL_CLK_CKO>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_3p3v>; +- lrclk-strength = <3>; +- }; +- +- camera@3c { +- compatible = "ovti,ov5645"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ov5645>; +- reg = <0x3c>; +- clocks = <&clks IMX6QDL_CLK_CKO2>; +- clock-names = "xclk"; +- clock-frequency = <24000000>; +- vdddo-supply = <®_1p8v>; +- vdda-supply = <®_2p8v>; +- vddd-supply = <®_1p5v>; +- enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; +- +- port { +- ov5645_to_mipi_csi2: endpoint { +- remote-endpoint = <&mipi_csi2_in>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- }; +- }; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- +- imx6qdl-wandboard { +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 +- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c1_gpio: i2c1gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b0 +- MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b0 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2_gpio: i2c2gpiogrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b0 +- MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b0 +- >; +- }; +- +- pinctrl_mclk: mclkgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 +- >; +- }; +- +- pinctrl_ov5645: ov5645grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 +- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 +- MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 +- >; +- }; +- +- pinctrl_spdif: spdifgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 +- MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +- >; +- }; +- +- pinctrl_usbotgvbus: usbotgvbusgrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- >; +- }; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy>; +- phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy@1 { +- reg = <1>; +- qca,clk-out-frequency = <125000000>; +- }; +- }; +-}; +- +-&mipi_csi { +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- mipi_csi2_in: endpoint { +- remote-endpoint = <&ov5645_to_mipi_csi2>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- }; +- }; +-}; +- +-&spdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spdif>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- disable-over-current; +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl-zii-rdu2.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl-zii-rdu2.dtsi +deleted file mode 100644 +index 525ff62b47f5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl-zii-rdu2.dtsi ++++ /dev/null +@@ -1,1142 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2016-2017 Zodiac Inflight Innovations +- */ +- +-#include +-#include +- +-/ { +- chosen { +- stdout-path = &uart1; +- }; +- +- aliases { +- mdio-gpio0 = &mdio1; +- rtc0 = &ds1341; +- }; +- +- mdio1: mdio { +- compatible = "virtual,mdio-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mdio1>; +- gpios = <&gpio6 5 GPIO_ACTIVE_HIGH +- &gpio6 4 GPIO_ACTIVE_HIGH>; +- +- phy: ethernet-phy@0 { +- pinctrl-0 = <&pinctrl_rmii_phy_irq>; +- pinctrl-names = "default"; +- reg = <0>; +- interrupt-parent = <&gpio3>; +- interrupts = <30 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +- +- reg_28p0v: regulator-28p0v { +- compatible = "regulator-fixed"; +- regulator-name = "28V_IN"; +- regulator-min-microvolt = <28000000>; +- regulator-max-microvolt = <28000000>; +- regulator-always-on; +- }; +- +- reg_12p0v: regulator-12p0v { +- compatible = "regulator-fixed"; +- vin-supply = <®_28p0v>; +- regulator-name = "12V_MAIN"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- }; +- +- reg_5p0v_main: regulator-5p0v-main { +- compatible = "regulator-fixed"; +- vin-supply = <®_12p0v>; +- regulator-name = "5V_MAIN"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_3p3v_pmic: regulator-3p3v-pmic { +- compatible = "regulator-fixed"; +- vin-supply = <®_12p0v>; +- regulator-name = "PMIC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- vin-supply = <®_3p3v_pmic>; +- regulator-name = "GEN_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_3p3v_sd: regulator-3p3v-sd { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_3p3v_sd>; +- vin-supply = <®_3p3v>; +- regulator-name = "3V3_SD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <1000>; +- enable-active-high; +- regulator-always-on; +- }; +- +- reg_3p3v_display: regulator-3p3v-display { +- compatible = "regulator-fixed"; +- vin-supply = <®_12p0v>; +- regulator-name = "3V3_DISPLAY"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_3p3v_ssd: regulator-3p3v-ssd { +- compatible = "regulator-fixed"; +- vin-supply = <®_12p0v>; +- regulator-name = "3V3_SSD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- sound1 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "front"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sound1_codec>; +- simple-audio-card,frame-master = <&sound1_codec>; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "Headphone Jack", "HPA1 HPLEFT", +- "Headphone Jack", "HPA1 HPRIGHT", +- "HPA1 LEFTIN", "HPL", +- "HPA1 RIGHTIN", "HPR"; +- simple-audio-card,aux-devs = <&hpa1>; +- +- sound1_cpu: simple-audio-card,cpu { +- sound-dai = <&ssi2>; +- }; +- +- sound1_codec: simple-audio-card,codec { +- sound-dai = <&codec1>; +- clocks = <&cs2000>; +- }; +- }; +- +- sound2 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "periph"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sound2_codec>; +- simple-audio-card,frame-master = <&sound2_codec>; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "Headphone Jack", "HPA1 HPLEFT", +- "Headphone Jack", "HPA1 HPRIGHT", +- "HPA1 LEFTIN", "HPL", +- "HPA1 RIGHTIN", "HPR"; +- simple-audio-card,aux-devs = <&hpa2>; +- +- sound2_cpu: simple-audio-card,cpu { +- sound-dai = <&ssi1>; +- }; +- +- sound2_codec: simple-audio-card,codec { +- sound-dai = <&codec2>; +- clocks = <&cs2000>; +- }; +- }; +- +- panel { +- power-supply = <®_3p3v_display>; +- backlight = <&sp_backlight>; +- status = "disabled"; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +- +- disp0: disp0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx-parallel-display"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_disp0>; +- status = "disabled"; +- +- port@0 { +- reg = <0>; +- +- disp0_in_0: endpoint { +- remote-endpoint = <&ipu1_di0_disp0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- disp0_out: endpoint { +- remote-endpoint = <&tc358767_in>; +- }; +- }; +- }; +- +- cs2000_ref: cs2000-ref { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +- +- cs2000_in_dummy: cs2000-in-dummy { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- edp_refclk: edp-refclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <19200000>; +- }; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI1_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, +- <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; +-}; +- +-&cpu0 { +- fsl,soc-operating-points = < +- /* ARM kHz SOC-PU uV */ +- 1200000 1300000 +- 996000 1275000 +- 852000 1275000 +- 792000 1200000 +- 396000 1200000 +- >; +-}; +- +-®_arm { +- vin-supply = <&sw1a_reg>; +-}; +- +-®_pu { +- vin-supply = <&sw1c_reg>; +-}; +- +-®_soc { +- vin-supply = <&sw1c_reg>; +-}; +- +-&ldb { +- lvds-channel@0 { +- port@4 { +- reg = <4>; +- +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- linux,rs485-enabled-at-boot-time; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +- +- rave-sp { +- compatible = "zii,rave-sp-rdu2"; +- current-speed = <1000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- watchdog { +- compatible = "zii,rave-sp-watchdog"; +- }; +- +- sp_backlight: backlight { +- compatible = "zii,rave-sp-backlight"; +- }; +- +- pwrbutton { +- compatible = "zii,rave-sp-pwrbutton"; +- }; +- +- eeprom@a3 { +- compatible = "zii,rave-sp-eeprom"; +- reg = <0xa3 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- zii,eeprom-name = "dds-eeprom"; +- }; +- +- eeprom@a4 { +- compatible = "zii,rave-sp-eeprom"; +- reg = <0xa4 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- zii,eeprom-name = "main-eeprom"; +- }; +- }; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- flash@0 { +- compatible = "st,m25p128", "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +- +-&gpio3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio3_hog>; +- +- usb-emulation-hog { +- gpio-hog; +- gpios = <19 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "usb-emulation"; +- }; +- +- usb-mode1-hog { +- gpio-hog; +- gpios = <20 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "usb-mode1"; +- }; +- +- usb-pwr-hog { +- gpio-hog; +- gpios = <22 GPIO_ACTIVE_LOW>; +- output-high; +- line-name = "usb-pwr-ctrl-en-n"; +- }; +- +- usb-mode2-hog { +- gpio-hog; +- gpios = <23 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "usb-mode2"; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clock-frequency = <100000>; +- status = "okay"; +- +- codec2: codec@18 { +- compatible = "ti,tlv320dac3100"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_codec2>; +- reg = <0x18>; +- #sound-dai-cells = <0>; +- HPVDD-supply = <®_3p3v>; +- SPRVDD-supply = <®_3p3v>; +- SPLVDD-supply = <®_3p3v>; +- AVDD-supply = <®_3p3v>; +- IOVDD-supply = <®_3p3v>; +- DVDD-supply = <&vgen4_reg>; +- reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; +- }; +- +- accel@1c { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_accel>; +- compatible = "fsl,mma8451"; +- reg = <0x1c>; +- interrupt-parent = <&gpio1>; +- interrupt-names = "INT2"; +- interrupts = <20 IRQ_TYPE_LEVEL_LOW>; +- vdd-supply = <®_3p3v>; +- vddio-supply = <®_3p3v>; +- }; +- +- hpa2: amp@60 { +- compatible = "ti,tpa6130a2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tpa2>; +- reg = <0x60>; +- power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- Vdd-supply = <®_5p0v_main>; +- sound-name-prefix = "HPA1"; +- }; +- +- edp-bridge@68 { +- compatible = "toshiba,tc358767"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tc358767>; +- reg = <0x68>; +- shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- clock-names = "ref"; +- clocks = <&edp_refclk>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <1>; +- +- tc358767_in: endpoint { +- remote-endpoint = <&disp0_out>; +- }; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clock-frequency = <100000>; +- status = "okay"; +- +- pmic@8 { +- compatible = "fsl,pfuze100"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pfuze100_irq>; +- reg = <0x08>; +- interrupt-parent = <&gpio7>; +- interrupts = <13 IRQ_TYPE_LEVEL_LOW>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- }; +- }; +- +- watchdog@38 { +- compatible = "zii,rave-wdt"; +- reg = <0x38>; +- }; +- +- temp-sense@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +- +- cs2000: clkgen@4e { +- compatible = "cirrus,cs2000-cp"; +- reg = <0x4e>; +- #clock-cells = <0>; +- clock-names = "clk_in", "ref_clk"; +- clocks = <&cs2000_in_dummy>, <&cs2000_ref>; +- assigned-clocks = <&cs2000>; +- assigned-clock-rates = <24000000>; +- }; +- +- eeprom@54 { +- compatible = "atmel,24c128"; +- reg = <0x54>; +- }; +- +- ds1341: rtc@68 { +- compatible = "dallas,ds1341"; +- reg = <0x68>; +- }; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- clock-frequency = <400000>; +- status = "okay"; +- +- codec1: codec@18 { +- compatible = "ti,tlv320dac3100"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_codec1>; +- reg = <0x18>; +- #sound-dai-cells = <0>; +- HPVDD-supply = <®_3p3v>; +- SPRVDD-supply = <®_3p3v>; +- SPLVDD-supply = <®_3p3v>; +- AVDD-supply = <®_3p3v>; +- IOVDD-supply = <®_3p3v>; +- DVDD-supply = <&vgen4_reg>; +- reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; +- }; +- +- touchscreen@20 { +- compatible = "syna,rmi4-i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ts>; +- reg = <0x20>; +- interrupt-parent = <&gpio1>; +- interrupts = <8 IRQ_TYPE_LEVEL_LOW>; +- vdd-supply = <®_5p0v_main>; +- vio-supply = <®_3p3v>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- rmi4-f01@1 { +- reg = <0x1>; +- syna,nosleep-mode = <2>; +- }; +- +- rmi4-f11@11 { +- reg = <0x11>; +- touchscreen-inverted-x; +- touchscreen-swapped-x-y; +- syna,sensor-type = <1>; +- syna,delta-x-threshold = <5>; +- syna,delta-y-threshold = <10>; +- }; +- +- rmi4-f12@12 { +- reg = <0x12>; +- touchscreen-inverted-x; +- touchscreen-swapped-x-y; +- syna,sensor-type = <1>; +- }; +- }; +- +- touchscreen@2a { +- compatible = "eeti,exc3000"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ts>; +- reg = <0x2a>; +- interrupt-parent = <&gpio1>; +- interrupts = <8 IRQ_TYPE_LEVEL_LOW>; +- touchscreen-inverted-x; +- touchscreen-swapped-x-y; +- status = "disabled"; +- }; +- +- reg_5p0v_user_usb: charger@32 { +- compatible = "microchip,ucs1002"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ucs1002_pins>; +- reg = <0x32>; +- interrupts-extended = <&gpio5 2 IRQ_TYPE_EDGE_BOTH>, +- <&gpio3 21 IRQ_TYPE_EDGE_FALLING>; +- interrupt-names = "a_det", "alert"; +- }; +- +- hpa1: amp@60 { +- compatible = "ti,tpa6130a2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tpa1>; +- reg = <0x60>; +- power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; +- Vdd-supply = <®_5p0v_main>; +- sound-name-prefix = "HPA1"; +- }; +-}; +- +-&ipu1_di0_disp0 { +- remote-endpoint = <&disp0_in_0>; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- host@0 { +- reg = <0 0 0 0 0>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- i210: i210@0 { +- reg = <0 0 0 0 0>; +- }; +- }; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; +- disable-wp; +- vmmc-supply = <®_3p3v_sd>; +- vqmmc-supply = <®_3p3v>; +- no-1-8-v; +- no-sdio; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <4>; +- cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +- disable-wp; +- vmmc-supply = <®_3p3v_sd>; +- vqmmc-supply = <®_3p3v>; +- no-1-8-v; +- no-sdio; +- status = "okay"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <8>; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_3p3v>; +- no-1-8-v; +- non-removable; +- no-sdio; +- no-sd; +- status = "okay"; +-}; +- +-&sata { +- target-supply = <®_3p3v_ssd>; +- status = "okay"; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-mode = "rmii"; +- phy-handle = <&phy>; +- phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <100>; +- phy-supply = <®_3p3v>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <12500000>; +- suppress-preamble; +- status = "okay"; +- +- switch: switch@0 { +- compatible = "marvell,mv88e6085"; +- pinctrl-0 = <&pinctrl_switch_irq>; +- pinctrl-names = "default"; +- reg = <0>; +- dsa,member = <0 0>; +- eeprom-length = <512>; +- interrupt-parent = <&gpio6>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "gigabit_proc"; +- phy-handle = <&switchphy0>; +- }; +- +- port@1 { +- reg = <1>; +- label = "netaux"; +- phy-handle = <&switchphy1>; +- }; +- +- port@2 { +- reg = <2>; +- label = "cpu"; +- ethernet = <&fec>; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +- +- port@3 { +- reg = <3>; +- label = "netright"; +- phy-handle = <&switchphy3>; +- }; +- +- port@4 { +- reg = <4>; +- label = "netleft"; +- phy-handle = <&switchphy4>; +- }; +- }; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switchphy0: switchphy@0 { +- reg = <0>; +- interrupt-parent = <&switch>; +- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switchphy1: switchphy@1 { +- reg = <1>; +- interrupt-parent = <&switch>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switchphy2: switchphy@2 { +- reg = <2>; +- interrupt-parent = <&switch>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switchphy3: switchphy@3 { +- reg = <3>; +- interrupt-parent = <&switch>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switchphy4: switchphy@4 { +- reg = <4>; +- interrupt-parent = <&switch>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +- }; +- }; +- }; +- }; +-}; +- +-&usbh1 { +- vbus-supply = <®_5p0v_main>; +- disable-over-current; +- maximum-speed = "full-speed"; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_5p0v_user_usb>; +- disable-over-current; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&snvs_rtc { +- status = "disabled"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&ssi2 { +- status = "okay"; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +- +- ssi1 { +- fsl,audmux-port = <0>; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_SYN | +- IMX_AUDMUX_V2_PTCR_TFSEL(2) | +- IMX_AUDMUX_V2_PTCR_TCSEL(2) | +- IMX_AUDMUX_V2_PTCR_TFSDIR | +- IMX_AUDMUX_V2_PTCR_TCLKDIR) +- IMX_AUDMUX_V2_PDCR_RXDSEL(2) +- >; +- }; +- +- aud3 { +- fsl,audmux-port = <2>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN +- IMX_AUDMUX_V2_PDCR_RXDSEL(0) +- >; +- }; +- +- ssi2 { +- fsl,audmux-port = <1>; +- fsl,port-config = < +- (IMX_AUDMUX_V2_PTCR_SYN | +- IMX_AUDMUX_V2_PTCR_TFSEL(4) | +- IMX_AUDMUX_V2_PTCR_TCSEL(4) | +- IMX_AUDMUX_V2_PTCR_TFSDIR | +- IMX_AUDMUX_V2_PTCR_TCLKDIR) +- IMX_AUDMUX_V2_PDCR_RXDSEL(4) +- >; +- }; +- +- aud5 { +- fsl,audmux-port = <4>; +- fsl,port-config = < +- IMX_AUDMUX_V2_PTCR_SYN +- IMX_AUDMUX_V2_PDCR_RXDSEL(1) +- >; +- }; +-}; +- +-&iomuxc { +- pinctrl_accel: accelgrp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x4001b000 +- >; +- }; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 +- MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 +- MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 +- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 +- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0 +- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 +- >; +- }; +- +- pinctrl_codec1: dac1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x40000038 +- >; +- }; +- +- pinctrl_codec2: dac2grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x40000038 +- >; +- }; +- +- pinctrl_disp0: disp0grp { +- fsl,pins = < +- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9 +- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f9 +- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f9 +- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f9 +- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f9 +- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f9 +- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f9 +- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f9 +- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f9 +- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f9 +- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f9 +- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f9 +- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f9 +- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f9 +- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f9 +- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f9 +- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f9 +- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f9 +- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f9 +- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f9 +- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f9 +- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f9 +- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f9 +- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f9 +- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f9 +- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f9 +- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f9 +- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f9 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 +- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x000b1 +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b1 +- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x100f5 +- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x100f5 +- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x100c0 +- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x100c0 +- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x100f5 +- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x100f5 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x40010040 +- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x100b0 +- MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 +- >; +- }; +- +- pinctrl_gpio3_hog: gpio3hoggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 +- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 +- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b811 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b811 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b811 +- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b811 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b811 +- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b811 +- >; +- }; +- +- pinctrl_mdio1: bitbangmdiogrp { +- fsl,pins = < +- /* Bitbang MDIO for DEB Switch */ +- MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x4001b030 +- MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40018830 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x10038 +- >; +- }; +- +- pinctrl_pfuze100_irq: pfuze100grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x40010000 +- >; +- }; +- +- pinctrl_reg_3p3v_sd: mmcsupply1grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x858 +- >; +- }; +- +- pinctrl_rmii_phy_irq: phygrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x40010000 +- >; +- }; +- +- pinctrl_switch_irq: switchgrp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x4001b000 +- >; +- }; +- +- pinctrl_tc358767: tc358767grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x10 +- >; +- }; +- +- pinctrl_tpa1: tpa6130-1grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x40000038 +- >; +- }; +- +- pinctrl_tpa2: tpa6130-2grp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x40000038 +- >; +- }; +- +- pinctrl_ts: tsgrp { +- fsl,pins = < +- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 +- MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +- MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_ucs1002_pins: ucs1002grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 +- MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x10059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x40010040 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x10059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10069 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x40010040 +- +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 +- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 +- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 +- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +- MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x1b0b1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qdl.dtsi b/scripts/dtc/include-prefixes/arm/imx6qdl.dtsi +deleted file mode 100644 +index 89c342f3a7c2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qdl.dtsi ++++ /dev/null +@@ -1,1389 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Copyright 2011 Freescale Semiconductor, Inc. +-// Copyright 2011 Linaro Ltd. +- +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * The decompressor and also some bootloaders rely on a +- * pre-existing /chosen node to be available to insert the +- * command line and merge other ATAGS info. +- */ +- chosen {}; +- +- aliases { +- ethernet0 = &fec; +- can0 = &can1; +- can1 = &can2; +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- gpio3 = &gpio4; +- gpio4 = &gpio5; +- gpio5 = &gpio6; +- gpio6 = &gpio7; +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- ipu0 = &ipu1; +- mmc0 = &usdhc1; +- mmc1 = &usdhc2; +- mmc2 = &usdhc3; +- mmc3 = &usdhc4; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- serial4 = &uart5; +- spi0 = &ecspi1; +- spi1 = &ecspi2; +- spi2 = &ecspi3; +- spi3 = &ecspi4; +- usb0 = &usbotg; +- usb1 = &usbh1; +- usb2 = &usbh2; +- usb3 = &usbh3; +- usbphy0 = &usbphy1; +- usbphy1 = &usbphy2; +- }; +- +- clocks { +- ckil { +- compatible = "fsl,imx-ckil", "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- ckih1 { +- compatible = "fsl,imx-ckih1", "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- osc { +- compatible = "fsl,imx-osc", "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- }; +- }; +- +- ldb: ldb { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; +- gpr = <&gpr>; +- status = "disabled"; +- +- lvds-channel@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- status = "disabled"; +- +- port@0 { +- reg = <0>; +- +- lvds0_mux_0: endpoint { +- remote-endpoint = <&ipu1_di0_lvds0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lvds0_mux_1: endpoint { +- remote-endpoint = <&ipu1_di1_lvds0>; +- }; +- }; +- }; +- +- lvds-channel@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- status = "disabled"; +- +- port@0 { +- reg = <0>; +- +- lvds1_mux_0: endpoint { +- remote-endpoint = <&ipu1_di0_lvds1>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lvds1_mux_1: endpoint { +- remote-endpoint = <&ipu1_di1_lvds1>; +- }; +- }; +- }; +- }; +- +- pmu: pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupt-parent = <&gpc>; +- interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- usbphynop1: usbphynop1 { +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- }; +- +- usbphynop2: usbphynop2 { +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&gpc>; +- ranges; +- +- dma_apbh: dma-apbh@110000 { +- compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; +- reg = <0x00110000 0x2000>; +- interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, +- <0 13 IRQ_TYPE_LEVEL_HIGH>, +- <0 13 IRQ_TYPE_LEVEL_HIGH>, +- <0 13 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; +- #dma-cells = <1>; +- dma-channels = <4>; +- clocks = <&clks IMX6QDL_CLK_APBH_DMA>; +- }; +- +- gpmi: nand-controller@112000 { +- compatible = "fsl,imx6q-gpmi-nand"; +- reg = <0x00112000 0x2000>, <0x00114000 0x2000>; +- reg-names = "gpmi-nand", "bch"; +- interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "bch"; +- clocks = <&clks IMX6QDL_CLK_GPMI_IO>, +- <&clks IMX6QDL_CLK_GPMI_APB>, +- <&clks IMX6QDL_CLK_GPMI_BCH>, +- <&clks IMX6QDL_CLK_GPMI_BCH_APB>, +- <&clks IMX6QDL_CLK_PER1_BCH>; +- clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", +- "gpmi_bch_apb", "per1_bch"; +- dmas = <&dma_apbh 0>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- hdmi: hdmi@120000 { +- reg = <0x00120000 0x9000>; +- interrupts = <0 115 0x04>; +- gpr = <&gpr>; +- clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, +- <&clks IMX6QDL_CLK_HDMI_ISFR>; +- clock-names = "iahb", "isfr"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- hdmi_mux_0: endpoint { +- remote-endpoint = <&ipu1_di0_hdmi>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- hdmi_mux_1: endpoint { +- remote-endpoint = <&ipu1_di1_hdmi>; +- }; +- }; +- }; +- }; +- +- gpu_3d: gpu@130000 { +- compatible = "vivante,gc"; +- reg = <0x00130000 0x4000>; +- interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>, +- <&clks IMX6QDL_CLK_GPU3D_CORE>, +- <&clks IMX6QDL_CLK_GPU3D_SHADER>; +- clock-names = "bus", "core", "shader"; +- power-domains = <&pd_pu>; +- #cooling-cells = <2>; +- }; +- +- gpu_2d: gpu@134000 { +- compatible = "vivante,gc"; +- reg = <0x00134000 0x4000>; +- interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, +- <&clks IMX6QDL_CLK_GPU2D_CORE>; +- clock-names = "bus", "core"; +- power-domains = <&pd_pu>; +- #cooling-cells = <2>; +- }; +- +- timer@a00600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x00a00600 0x20>; +- interrupts = <1 13 0xf01>; +- interrupt-parent = <&intc>; +- clocks = <&clks IMX6QDL_CLK_TWD>; +- }; +- +- intc: interrupt-controller@a01000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x00a01000 0x1000>, +- <0x00a00100 0x100>; +- interrupt-parent = <&intc>; +- }; +- +- L2: cache-controller@a02000 { +- compatible = "arm,pl310-cache"; +- reg = <0x00a02000 0x1000>; +- interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; +- cache-unified; +- cache-level = <2>; +- arm,tag-latency = <4 2 3>; +- arm,data-latency = <4 2 3>; +- arm,shared-override; +- }; +- +- pcie: pcie@1ffc000 { +- compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; +- reg = <0x01ffc000 0x04000>, +- <0x01f00000 0x80000>; +- reg-names = "dbi", "config"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- bus-range = <0x00 0xff>; +- ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ +- 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ +- num-lanes = <1>; +- num-viewport = <4>; +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, +- <&clks IMX6QDL_CLK_LVDS1_GATE>, +- <&clks IMX6QDL_CLK_PCIE_REF_125M>; +- clock-names = "pcie", "pcie_bus", "pcie_phy"; +- status = "disabled"; +- }; +- +- bus@2000000 { /* AIPS1 */ +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x02000000 0x100000>; +- ranges; +- +- spba-bus@2000000 { +- compatible = "fsl,spba-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x02000000 0x40000>; +- ranges; +- +- spdif: spdif@2004000 { +- compatible = "fsl,imx35-spdif"; +- reg = <0x02004000 0x4000>; +- interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; +- dmas = <&sdma 14 18 0>, +- <&sdma 15 18 0>; +- dma-names = "rx", "tx"; +- clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, +- <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, +- <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, +- <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>, +- <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; +- clock-names = "core", "rxtx0", +- "rxtx1", "rxtx2", +- "rxtx3", "rxtx4", +- "rxtx5", "rxtx6", +- "rxtx7", "spba"; +- status = "disabled"; +- }; +- +- ecspi1: spi@2008000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; +- reg = <0x02008000 0x4000>; +- interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_ECSPI1>, +- <&clks IMX6QDL_CLK_ECSPI1>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ecspi2: spi@200c000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; +- reg = <0x0200c000 0x4000>; +- interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_ECSPI2>, +- <&clks IMX6QDL_CLK_ECSPI2>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ecspi3: spi@2010000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; +- reg = <0x02010000 0x4000>; +- interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_ECSPI3>, +- <&clks IMX6QDL_CLK_ECSPI3>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ecspi4: spi@2014000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; +- reg = <0x02014000 0x4000>; +- interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_ECSPI4>, +- <&clks IMX6QDL_CLK_ECSPI4>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart1: serial@2020000 { +- compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; +- reg = <0x02020000 0x4000>; +- interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_UART_IPG>, +- <&clks IMX6QDL_CLK_UART_SERIAL>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- esai: esai@2024000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx35-esai"; +- reg = <0x02024000 0x4000>; +- interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_ESAI_IPG>, +- <&clks IMX6QDL_CLK_ESAI_MEM>, +- <&clks IMX6QDL_CLK_ESAI_EXTAL>, +- <&clks IMX6QDL_CLK_ESAI_IPG>, +- <&clks IMX6QDL_CLK_SPBA>; +- clock-names = "core", "mem", "extal", "fsys", "spba"; +- dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ssi1: ssi@2028000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx6q-ssi", +- "fsl,imx51-ssi"; +- reg = <0x02028000 0x4000>; +- interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, +- <&clks IMX6QDL_CLK_SSI1>; +- clock-names = "ipg", "baud"; +- dmas = <&sdma 37 1 0>, +- <&sdma 38 1 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- ssi2: ssi@202c000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx6q-ssi", +- "fsl,imx51-ssi"; +- reg = <0x0202c000 0x4000>; +- interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, +- <&clks IMX6QDL_CLK_SSI2>; +- clock-names = "ipg", "baud"; +- dmas = <&sdma 41 1 0>, +- <&sdma 42 1 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- ssi3: ssi@2030000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx6q-ssi", +- "fsl,imx51-ssi"; +- reg = <0x02030000 0x4000>; +- interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, +- <&clks IMX6QDL_CLK_SSI3>; +- clock-names = "ipg", "baud"; +- dmas = <&sdma 45 1 0>, +- <&sdma 46 1 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- asrc: asrc@2034000 { +- compatible = "fsl,imx53-asrc"; +- reg = <0x02034000 0x4000>; +- interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_ASRC_IPG>, +- <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>, +- <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, +- <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, +- <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, +- <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>, +- <&clks IMX6QDL_CLK_SPBA>; +- clock-names = "mem", "ipg", "asrck_0", +- "asrck_1", "asrck_2", "asrck_3", "asrck_4", +- "asrck_5", "asrck_6", "asrck_7", "asrck_8", +- "asrck_9", "asrck_a", "asrck_b", "asrck_c", +- "asrck_d", "asrck_e", "asrck_f", "spba"; +- dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, +- <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; +- dma-names = "rxa", "rxb", "rxc", +- "txa", "txb", "txc"; +- fsl,asrc-rate = <48000>; +- fsl,asrc-width = <16>; +- status = "okay"; +- }; +- +- spba@203c000 { +- reg = <0x0203c000 0x4000>; +- }; +- }; +- +- vpu: vpu@2040000 { +- compatible = "cnm,coda960"; +- reg = <0x02040000 0x3c000>; +- interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, +- <0 3 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "bit", "jpeg"; +- clocks = <&clks IMX6QDL_CLK_VPU_AXI>, +- <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; +- clock-names = "per", "ahb"; +- power-domains = <&pd_pu>; +- resets = <&src 1>; +- iram = <&ocram>; +- }; +- +- aipstz@207c000 { /* AIPSTZ1 */ +- reg = <0x0207c000 0x4000>; +- }; +- +- pwm1: pwm@2080000 { +- #pwm-cells = <3>; +- compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; +- reg = <0x02080000 0x4000>; +- interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_IPG>, +- <&clks IMX6QDL_CLK_PWM1>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- pwm2: pwm@2084000 { +- #pwm-cells = <3>; +- compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; +- reg = <0x02084000 0x4000>; +- interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_IPG>, +- <&clks IMX6QDL_CLK_PWM2>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- pwm3: pwm@2088000 { +- #pwm-cells = <3>; +- compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; +- reg = <0x02088000 0x4000>; +- interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_IPG>, +- <&clks IMX6QDL_CLK_PWM3>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- pwm4: pwm@208c000 { +- #pwm-cells = <3>; +- compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; +- reg = <0x0208c000 0x4000>; +- interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_IPG>, +- <&clks IMX6QDL_CLK_PWM4>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- can1: can@2090000 { +- compatible = "fsl,imx6q-flexcan"; +- reg = <0x02090000 0x4000>; +- interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, +- <&clks IMX6QDL_CLK_CAN1_SERIAL>; +- clock-names = "ipg", "per"; +- fsl,stop-mode = <&gpr 0x34 28>; +- status = "disabled"; +- }; +- +- can2: can@2094000 { +- compatible = "fsl,imx6q-flexcan"; +- reg = <0x02094000 0x4000>; +- interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, +- <&clks IMX6QDL_CLK_CAN2_SERIAL>; +- clock-names = "ipg", "per"; +- fsl,stop-mode = <&gpr 0x34 29>; +- status = "disabled"; +- }; +- +- gpt: timer@2098000 { +- compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; +- reg = <0x02098000 0x4000>; +- interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_GPT_IPG>, +- <&clks IMX6QDL_CLK_GPT_IPG_PER>, +- <&clks IMX6QDL_CLK_GPT_3M>; +- clock-names = "ipg", "per", "osc_per"; +- }; +- +- gpio1: gpio@209c000 { +- compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; +- reg = <0x0209c000 0x4000>; +- interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, +- <0 67 IRQ_TYPE_LEVEL_HIGH>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@20a0000 { +- compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; +- reg = <0x020a0000 0x4000>; +- interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, +- <0 69 IRQ_TYPE_LEVEL_HIGH>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio@20a4000 { +- compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; +- reg = <0x020a4000 0x4000>; +- interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, +- <0 71 IRQ_TYPE_LEVEL_HIGH>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio4: gpio@20a8000 { +- compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; +- reg = <0x020a8000 0x4000>; +- interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, +- <0 73 IRQ_TYPE_LEVEL_HIGH>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio5: gpio@20ac000 { +- compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; +- reg = <0x020ac000 0x4000>; +- interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, +- <0 75 IRQ_TYPE_LEVEL_HIGH>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio6: gpio@20b0000 { +- compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; +- reg = <0x020b0000 0x4000>; +- interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, +- <0 77 IRQ_TYPE_LEVEL_HIGH>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio7: gpio@20b4000 { +- compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; +- reg = <0x020b4000 0x4000>; +- interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, +- <0 79 IRQ_TYPE_LEVEL_HIGH>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- kpp: keypad@20b8000 { +- compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; +- reg = <0x020b8000 0x4000>; +- interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_IPG>; +- status = "disabled"; +- }; +- +- wdog1: watchdog@20bc000 { +- compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; +- reg = <0x020bc000 0x4000>; +- interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_IPG>; +- }; +- +- wdog2: watchdog@20c0000 { +- compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; +- reg = <0x020c0000 0x4000>; +- interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_IPG>; +- status = "disabled"; +- }; +- +- clks: clock-controller@20c4000 { +- compatible = "fsl,imx6q-ccm"; +- reg = <0x020c4000 0x4000>; +- interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, +- <0 88 IRQ_TYPE_LEVEL_HIGH>; +- #clock-cells = <1>; +- }; +- +- anatop: anatop@20c8000 { +- compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd"; +- reg = <0x020c8000 0x1000>; +- interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, +- <0 54 IRQ_TYPE_LEVEL_HIGH>, +- <0 127 IRQ_TYPE_LEVEL_HIGH>; +- +- reg_vdd1p1: regulator-1p1 { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vdd1p1"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- anatop-reg-offset = <0x110>; +- anatop-vol-bit-shift = <8>; +- anatop-vol-bit-width = <5>; +- anatop-min-bit-val = <4>; +- anatop-min-voltage = <800000>; +- anatop-max-voltage = <1375000>; +- anatop-enable-bit = <0>; +- }; +- +- reg_vdd3p0: regulator-3p0 { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vdd3p0"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <3150000>; +- regulator-always-on; +- anatop-reg-offset = <0x120>; +- anatop-vol-bit-shift = <8>; +- anatop-vol-bit-width = <5>; +- anatop-min-bit-val = <0>; +- anatop-min-voltage = <2625000>; +- anatop-max-voltage = <3400000>; +- anatop-enable-bit = <0>; +- }; +- +- reg_vdd2p5: regulator-2p5 { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vdd2p5"; +- regulator-min-microvolt = <2250000>; +- regulator-max-microvolt = <2750000>; +- regulator-always-on; +- anatop-reg-offset = <0x130>; +- anatop-vol-bit-shift = <8>; +- anatop-vol-bit-width = <5>; +- anatop-min-bit-val = <0>; +- anatop-min-voltage = <2100000>; +- anatop-max-voltage = <2875000>; +- anatop-enable-bit = <0>; +- }; +- +- reg_arm: regulator-vddcore { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vddarm"; +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1450000>; +- regulator-always-on; +- anatop-reg-offset = <0x140>; +- anatop-vol-bit-shift = <0>; +- anatop-vol-bit-width = <5>; +- anatop-delay-reg-offset = <0x170>; +- anatop-delay-bit-shift = <24>; +- anatop-delay-bit-width = <2>; +- anatop-min-bit-val = <1>; +- anatop-min-voltage = <725000>; +- anatop-max-voltage = <1450000>; +- }; +- +- reg_pu: regulator-vddpu { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vddpu"; +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1450000>; +- regulator-enable-ramp-delay = <150>; +- anatop-reg-offset = <0x140>; +- anatop-vol-bit-shift = <9>; +- anatop-vol-bit-width = <5>; +- anatop-delay-reg-offset = <0x170>; +- anatop-delay-bit-shift = <26>; +- anatop-delay-bit-width = <2>; +- anatop-min-bit-val = <1>; +- anatop-min-voltage = <725000>; +- anatop-max-voltage = <1450000>; +- }; +- +- reg_soc: regulator-vddsoc { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vddsoc"; +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1450000>; +- regulator-always-on; +- anatop-reg-offset = <0x140>; +- anatop-vol-bit-shift = <18>; +- anatop-vol-bit-width = <5>; +- anatop-delay-reg-offset = <0x170>; +- anatop-delay-bit-shift = <28>; +- anatop-delay-bit-width = <2>; +- anatop-min-bit-val = <1>; +- anatop-min-voltage = <725000>; +- anatop-max-voltage = <1450000>; +- }; +- +- tempmon: tempmon { +- compatible = "fsl,imx6q-tempmon"; +- interrupt-parent = <&gpc>; +- interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; +- fsl,tempmon = <&anatop>; +- nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; +- nvmem-cell-names = "calib", "temp_grade"; +- clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +- #thermal-sensor-cells = <0>; +- }; +- }; +- +- usbphy1: usbphy@20c9000 { +- compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; +- reg = <0x020c9000 0x1000>; +- interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_USBPHY1>; +- fsl,anatop = <&anatop>; +- }; +- +- usbphy2: usbphy@20ca000 { +- compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; +- reg = <0x020ca000 0x1000>; +- interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_USBPHY2>; +- fsl,anatop = <&anatop>; +- }; +- +- snvs: snvs@20cc000 { +- compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; +- reg = <0x020cc000 0x4000>; +- +- snvs_rtc: snvs-rtc-lp { +- compatible = "fsl,sec-v4.0-mon-rtc-lp"; +- regmap = <&snvs>; +- offset = <0x34>; +- interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, +- <0 20 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- snvs_poweroff: snvs-poweroff { +- compatible = "syscon-poweroff"; +- regmap = <&snvs>; +- offset = <0x38>; +- value = <0x60>; +- mask = <0x60>; +- status = "disabled"; +- }; +- +- snvs_pwrkey: snvs-powerkey { +- compatible = "fsl,sec-v4.0-pwrkey"; +- regmap = <&snvs>; +- interrupts = ; +- linux,keycode = ; +- wakeup-source; +- status = "disabled"; +- }; +- +- snvs_lpgpr: snvs-lpgpr { +- compatible = "fsl,imx6q-snvs-lpgpr"; +- }; +- }; +- +- epit1: epit@20d0000 { /* EPIT1 */ +- reg = <0x020d0000 0x4000>; +- interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- epit2: epit@20d4000 { /* EPIT2 */ +- reg = <0x020d4000 0x4000>; +- interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- src: reset-controller@20d8000 { +- compatible = "fsl,imx6q-src", "fsl,imx51-src"; +- reg = <0x020d8000 0x4000>; +- interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, +- <0 96 IRQ_TYPE_LEVEL_HIGH>; +- #reset-cells = <1>; +- }; +- +- gpc: gpc@20dc000 { +- compatible = "fsl,imx6q-gpc"; +- reg = <0x020dc000 0x4000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&intc>; +- clocks = <&clks IMX6QDL_CLK_IPG>; +- clock-names = "ipg"; +- +- pgc { +- #address-cells = <1>; +- #size-cells = <0>; +- +- power-domain@0 { +- reg = <0>; +- #power-domain-cells = <0>; +- }; +- pd_pu: power-domain@1 { +- reg = <1>; +- #power-domain-cells = <0>; +- power-supply = <®_pu>; +- clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, +- <&clks IMX6QDL_CLK_GPU3D_SHADER>, +- <&clks IMX6QDL_CLK_GPU2D_CORE>, +- <&clks IMX6QDL_CLK_GPU2D_AXI>, +- <&clks IMX6QDL_CLK_OPENVG_AXI>, +- <&clks IMX6QDL_CLK_VPU_AXI>; +- }; +- }; +- }; +- +- gpr: iomuxc-gpr@20e0000 { +- compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; +- reg = <0x20e0000 0x38>; +- +- mux: mux-controller { +- compatible = "mmio-mux"; +- #mux-control-cells = <1>; +- }; +- }; +- +- iomuxc: pinctrl@20e0000 { +- compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; +- reg = <0x20e0000 0x4000>; +- }; +- +- dcic1: dcic@20e4000 { +- reg = <0x020e4000 0x4000>; +- interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- dcic2: dcic@20e8000 { +- reg = <0x020e8000 0x4000>; +- interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- sdma: sdma@20ec000 { +- compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; +- reg = <0x020ec000 0x4000>; +- interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_IPG>, +- <&clks IMX6QDL_CLK_SDMA>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; +- }; +- }; +- +- bus@2100000 { /* AIPS2 */ +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x02100000 0x100000>; +- ranges; +- +- crypto: crypto@2100000 { +- compatible = "fsl,sec-v4.0"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x2100000 0x10000>; +- ranges = <0 0x2100000 0x10000>; +- clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, +- <&clks IMX6QDL_CLK_CAAM_ACLK>, +- <&clks IMX6QDL_CLK_CAAM_IPG>, +- <&clks IMX6QDL_CLK_EIM_SLOW>; +- clock-names = "mem", "aclk", "ipg", "emi_slow"; +- +- sec_jr0: jr@1000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x1000 0x1000>; +- interrupts = ; +- }; +- +- sec_jr1: jr@2000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x2000 0x1000>; +- interrupts = ; +- }; +- }; +- +- aipstz@217c000 { /* AIPSTZ2 */ +- reg = <0x0217c000 0x4000>; +- }; +- +- usbotg: usb@2184000 { +- compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; +- reg = <0x02184000 0x200>; +- interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_USBOH3>; +- fsl,usbphy = <&usbphy1>; +- fsl,usbmisc = <&usbmisc 0>; +- ahb-burst-config = <0x0>; +- tx-burst-size-dword = <0x10>; +- rx-burst-size-dword = <0x10>; +- status = "disabled"; +- }; +- +- usbh1: usb@2184200 { +- compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; +- reg = <0x02184200 0x200>; +- interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_USBOH3>; +- fsl,usbphy = <&usbphy2>; +- fsl,usbmisc = <&usbmisc 1>; +- dr_mode = "host"; +- ahb-burst-config = <0x0>; +- tx-burst-size-dword = <0x10>; +- rx-burst-size-dword = <0x10>; +- status = "disabled"; +- }; +- +- usbh2: usb@2184400 { +- compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; +- reg = <0x02184400 0x200>; +- interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_USBOH3>; +- fsl,usbphy = <&usbphynop1>; +- phy_type = "hsic"; +- fsl,usbmisc = <&usbmisc 2>; +- dr_mode = "host"; +- ahb-burst-config = <0x0>; +- tx-burst-size-dword = <0x10>; +- rx-burst-size-dword = <0x10>; +- status = "disabled"; +- }; +- +- usbh3: usb@2184600 { +- compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; +- reg = <0x02184600 0x200>; +- interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_USBOH3>; +- fsl,usbphy = <&usbphynop2>; +- phy_type = "hsic"; +- fsl,usbmisc = <&usbmisc 3>; +- dr_mode = "host"; +- ahb-burst-config = <0x0>; +- tx-burst-size-dword = <0x10>; +- rx-burst-size-dword = <0x10>; +- status = "disabled"; +- }; +- +- usbmisc: usbmisc@2184800 { +- #index-cells = <1>; +- compatible = "fsl,imx6q-usbmisc"; +- reg = <0x02184800 0x200>; +- clocks = <&clks IMX6QDL_CLK_USBOH3>; +- }; +- +- fec: ethernet@2188000 { +- compatible = "fsl,imx6q-fec"; +- reg = <0x02188000 0x4000>; +- interrupt-names = "int0", "pps"; +- interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>, +- <0 119 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_ENET>, +- <&clks IMX6QDL_CLK_ENET>, +- <&clks IMX6QDL_CLK_ENET_REF>, +- <&clks IMX6QDL_CLK_ENET_REF>; +- clock-names = "ipg", "ahb", "ptp", "enet_out"; +- fsl,stop-mode = <&gpr 0x34 27>; +- status = "disabled"; +- }; +- +- mlb@218c000 { +- reg = <0x0218c000 0x4000>; +- interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, +- <0 117 IRQ_TYPE_LEVEL_HIGH>, +- <0 126 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- usdhc1: mmc@2190000 { +- compatible = "fsl,imx6q-usdhc"; +- reg = <0x02190000 0x4000>; +- interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_USDHC1>, +- <&clks IMX6QDL_CLK_USDHC1>, +- <&clks IMX6QDL_CLK_USDHC1>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usdhc2: mmc@2194000 { +- compatible = "fsl,imx6q-usdhc"; +- reg = <0x02194000 0x4000>; +- interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_USDHC2>, +- <&clks IMX6QDL_CLK_USDHC2>, +- <&clks IMX6QDL_CLK_USDHC2>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usdhc3: mmc@2198000 { +- compatible = "fsl,imx6q-usdhc"; +- reg = <0x02198000 0x4000>; +- interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_USDHC3>, +- <&clks IMX6QDL_CLK_USDHC3>, +- <&clks IMX6QDL_CLK_USDHC3>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usdhc4: mmc@219c000 { +- compatible = "fsl,imx6q-usdhc"; +- reg = <0x0219c000 0x4000>; +- interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_USDHC4>, +- <&clks IMX6QDL_CLK_USDHC4>, +- <&clks IMX6QDL_CLK_USDHC4>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- i2c1: i2c@21a0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; +- reg = <0x021a0000 0x4000>; +- interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_I2C1>; +- status = "disabled"; +- }; +- +- i2c2: i2c@21a4000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; +- reg = <0x021a4000 0x4000>; +- interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_I2C2>; +- status = "disabled"; +- }; +- +- i2c3: i2c@21a8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; +- reg = <0x021a8000 0x4000>; +- interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_I2C3>; +- status = "disabled"; +- }; +- +- romcp@21ac000 { +- reg = <0x021ac000 0x4000>; +- }; +- +- mmdc0: memory-controller@21b0000 { /* MMDC0 */ +- compatible = "fsl,imx6q-mmdc"; +- reg = <0x021b0000 0x4000>; +- clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; +- }; +- +- mmdc1: memory-controller@21b4000 { /* MMDC1 */ +- compatible = "fsl,imx6q-mmdc"; +- reg = <0x021b4000 0x4000>; +- status = "disabled"; +- }; +- +- weim: weim@21b8000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,imx6q-weim"; +- reg = <0x021b8000 0x4000>; +- interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; +- fsl,weim-cs-gpr = <&gpr>; +- status = "disabled"; +- }; +- +- ocotp: efuse@21bc000 { +- compatible = "fsl,imx6q-ocotp", "syscon"; +- reg = <0x021bc000 0x4000>; +- clocks = <&clks IMX6QDL_CLK_IIM>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpu_speed_grade: speed-grade@10 { +- reg = <0x10 4>; +- }; +- +- tempmon_calib: calib@38 { +- reg = <0x38 4>; +- }; +- +- tempmon_temp_grade: temp-grade@20 { +- reg = <0x20 4>; +- }; +- }; +- +- tzasc@21d0000 { /* TZASC1 */ +- reg = <0x021d0000 0x4000>; +- interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- tzasc@21d4000 { /* TZASC2 */ +- reg = <0x021d4000 0x4000>; +- interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- audmux: audmux@21d8000 { +- compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; +- reg = <0x021d8000 0x4000>; +- status = "disabled"; +- }; +- +- mipi_csi: mipi@21dc000 { +- compatible = "fsl,imx6-mipi-csi2"; +- reg = <0x021dc000 0x4000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 100 0x04>, <0 101 0x04>; +- clocks = <&clks IMX6QDL_CLK_HSI_TX>, +- <&clks IMX6QDL_CLK_VIDEO_27M>, +- <&clks IMX6QDL_CLK_EIM_PODF>; +- clock-names = "dphy", "ref", "pix"; +- status = "disabled"; +- }; +- +- mipi_dsi: mipi@21e0000 { +- reg = <0x021e0000 0x4000>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- mipi_mux_0: endpoint { +- remote-endpoint = <&ipu1_di0_mipi>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- mipi_mux_1: endpoint { +- remote-endpoint = <&ipu1_di1_mipi>; +- }; +- }; +- }; +- }; +- +- vdoa@21e4000 { +- compatible = "fsl,imx6q-vdoa"; +- reg = <0x021e4000 0x4000>; +- interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_VDOA>; +- }; +- +- uart2: serial@21e8000 { +- compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; +- reg = <0x021e8000 0x4000>; +- interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_UART_IPG>, +- <&clks IMX6QDL_CLK_UART_SERIAL>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart3: serial@21ec000 { +- compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; +- reg = <0x021ec000 0x4000>; +- interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_UART_IPG>, +- <&clks IMX6QDL_CLK_UART_SERIAL>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart4: serial@21f0000 { +- compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; +- reg = <0x021f0000 0x4000>; +- interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_UART_IPG>, +- <&clks IMX6QDL_CLK_UART_SERIAL>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart5: serial@21f4000 { +- compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; +- reg = <0x021f4000 0x4000>; +- interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_UART_IPG>, +- <&clks IMX6QDL_CLK_UART_SERIAL>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- }; +- +- ipu1: ipu@2400000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6q-ipu"; +- reg = <0x02400000 0x400000>; +- interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, +- <0 5 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6QDL_CLK_IPU1>, +- <&clks IMX6QDL_CLK_IPU1_DI0>, +- <&clks IMX6QDL_CLK_IPU1_DI1>; +- clock-names = "bus", "di0", "di1"; +- resets = <&src 2>; +- +- ipu1_csi0: port@0 { +- reg = <0>; +- +- ipu1_csi0_from_ipu1_csi0_mux: endpoint { +- remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>; +- }; +- }; +- +- ipu1_csi1: port@1 { +- reg = <1>; +- }; +- +- ipu1_di0: port@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- ipu1_di0_disp0: endpoint@0 { +- reg = <0>; +- }; +- +- ipu1_di0_hdmi: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&hdmi_mux_0>; +- }; +- +- ipu1_di0_mipi: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&mipi_mux_0>; +- }; +- +- ipu1_di0_lvds0: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&lvds0_mux_0>; +- }; +- +- ipu1_di0_lvds1: endpoint@4 { +- reg = <4>; +- remote-endpoint = <&lvds1_mux_0>; +- }; +- }; +- +- ipu1_di1: port@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- ipu1_di1_disp1: endpoint@0 { +- reg = <0>; +- }; +- +- ipu1_di1_hdmi: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&hdmi_mux_1>; +- }; +- +- ipu1_di1_mipi: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&mipi_mux_1>; +- }; +- +- ipu1_di1_lvds0: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&lvds0_mux_1>; +- }; +- +- ipu1_di1_lvds1: endpoint@4 { +- reg = <4>; +- remote-endpoint = <&lvds1_mux_1>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qp-nitrogen6_max.dts b/scripts/dtc/include-prefixes/arm/imx6qp-nitrogen6_max.dts +deleted file mode 100644 +index 741d1ed338ca..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qp-nitrogen6_max.dts ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright 2016 Boundary Devices, Inc. +- */ +- +-/dts-v1/; +- +-#include "imx6qp.dtsi" +-#include "imx6qdl-nitrogen6_max.dtsi" +- +-/ { +- model = "Boundary Devices i.MX6 Quad Plus Nitrogen6_MAX Board"; +- compatible = "boundary,imx6qp-nitrogen6_max", "fsl,imx6qp"; +-}; +- +-&pcie { +- status = "disabled"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qp-nitrogen6_som2.dts b/scripts/dtc/include-prefixes/arm/imx6qp-nitrogen6_som2.dts +deleted file mode 100644 +index 1593ac86b2a4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qp-nitrogen6_som2.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright 2017 Boundary Devices, Inc. +- */ +- +-/dts-v1/; +- +-#include "imx6qp.dtsi" +-#include "imx6qdl-nitrogen6_som2.dtsi" +- +-/ { +- model = "Boundary Devices i.MX6 Quad Plus Nitrogen6_SOM2 Board"; +- compatible = "boundary,imx6qp-nitrogen6_som2", "fsl,imx6qp"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qp-phytec-mira-rdk-nand.dts b/scripts/dtc/include-prefixes/arm/imx6qp-phytec-mira-rdk-nand.dts +deleted file mode 100644 +index f27d7ab42626..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qp-phytec-mira-rdk-nand.dts ++++ /dev/null +@@ -1,72 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2018 PHYTEC Messtechnik GmbH +- * Author: Enrico Scholz +- */ +- +-/dts-v1/; +-#include "imx6qp.dtsi" +-#include "imx6qdl-phytec-phycore-som.dtsi" +-#include "imx6qdl-phytec-mira.dtsi" +- +-/ { +- model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND"; +- compatible = "phytec,imx6qp-pbac06-nand", "phytec,imx6qp-pbac06", +- "phytec,imx6qdl-pcm058", "fsl,imx6qp"; +- +- chosen { +- stdout-path = &uart2; +- }; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&fec { +- status = "okay"; +-}; +- +-&gpmi { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c_rtc { +- status = "okay"; +-}; +- +-&m25p80 { +- status = "okay"; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&usbh1 { +- status = "okay"; +-}; +- +-&usbotg { +- status = "okay"; +-}; +- +-&usdhc1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qp-prtwd3.dts b/scripts/dtc/include-prefixes/arm/imx6qp-prtwd3.dts +deleted file mode 100644 +index b92e0f2748a5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qp-prtwd3.dts ++++ /dev/null +@@ -1,555 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (c) 2018 Protonic Holland +- * Copyright (c) 2020 Oleksij Rempel , Pengutronix +- */ +- +-/dts-v1/; +-#include +-#include "imx6qp.dtsi" +- +-/ { +- model = "Protonic WD3 board"; +- compatible = "prt,prtwd3", "fsl,imx6qp"; +- +- chosen { +- stdout-path = &uart4; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x20000000>; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +- +- clock_ksz8081: clock-ksz8081 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- }; +- +- clock_ksz9031: clock-ksz9031 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- clock_mcp251xfd: clock-mcp251xfd { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <20000000>; +- }; +- +- clock_sja1105: clock-sja1105 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- mdio { +- compatible = "virtual,mdio-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mdio>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- gpios = <&gpio5 6 GPIO_ACTIVE_HIGH +- &gpio5 7 GPIO_ACTIVE_HIGH>; +- +- /* Microchip KSZ8081 */ +- usbeth_phy: ethernet-phy@3 { +- reg = <0x3>; +- +- interrupts-extended = <&gpio5 12 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; +- reset-assert-us = <500>; +- reset-deassert-us = <1000>; +- clocks = <&clock_ksz8081>; +- clock-names = "rmii-ref"; +- micrel,led-mode = <0>; +- }; +- +- tja1102_phy0: ethernet-phy@4 { +- reg = <0x4>; +- +- interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; +- reset-assert-us = <20>; +- reset-deassert-us = <2000>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- tja1102_phy1: ethernet-phy@5 { +- reg = <0x5>; +- +- interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +- }; +- +- reg_5v0: regulator-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_otg_vbus: regulator-otg-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "otg-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wifi_npd>; +- reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- xceiver-supply = <®_5v0>; +- status = "okay"; +-}; +- +-&ecspi2 { +- cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- status = "okay"; +- +- switch@0 { +- compatible = "nxp,sja1105q"; +- reg = <0>; +- spi-max-frequency = <4000000>; +- spi-rx-delay-us = <1>; +- spi-tx-delay-us = <1>; +- spi-cpha; +- +- reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; +- +- clocks = <&clock_sja1105>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "usb"; +- phy-handle = <&usbeth_phy>; +- phy-mode = "rmii"; +- }; +- +- port@1 { +- reg = <1>; +- label = "t1slave"; +- phy-handle = <&tja1102_phy1>; +- phy-mode = "rmii"; +- }; +- +- port@2 { +- reg = <2>; +- label = "t1master"; +- phy-handle = <&tja1102_phy0>; +- phy-mode = "rmii"; +- +- }; +- +- port@3 { +- reg = <3>; +- label = "rj45"; +- phy-handle = <&rgmii_phy>; +- phy-mode = "rgmii-id"; +- }; +- +- port@4 { +- reg = <4>; +- label = "cpu"; +- ethernet = <&fec>; +- phy-mode = "rgmii-id"; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +- }; +- }; +-}; +- +-&ecspi3 { +- cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi3>; +- status = "okay"; +- +- can@0 { +- compatible = "microchip,mcp251xfd"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can2>; +- reg = <0>; +- clocks = <&clock_mcp251xfd>; +- spi-max-frequency = <10000000>; +- interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF>; +- assigned-clock-rates = <125000000>; +- status = "okay"; +- +- phy-mode = "rgmii"; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Microchip KSZ9031 */ +- rgmii_phy: ethernet-phy@2 { +- reg = <2>; +- +- interrupts-extended = <&gpio1 28 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- reset-deassert-us = <1000>; +- +- clocks = <&clock_ksz9031>; +- }; +- }; +-}; +- +-&gpio1 { +- gpio-line-names = +- "", "SD1_CD", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "PHY3_RESET", "", "", "PHY3_INT", "", "", ""; +-}; +- +-&gpio2 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "BOARD_ID3", +- "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", +- "", "", "", "", "", "", "", "", +- "", "", "ECSPI2_SS0", "", "", "", "", ""; +-}; +- +-&gpio3 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "USB_OTG_OC", "USB_OTG_PWR", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio4 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "CAN1_SR", "CAN2_SR", "", "", +- "", "", "", "", "", "", "", "", +- "ECSPI3_SS0", "CANFD_INT", "USB_ETH_RESET", "", "", "", "", ""; +-}; +- +-&gpio5 { +- gpio-line-names = +- "", "", "", "", "", "SW_RESET", "", "", +- "PHY12_INT", "PHY12_RESET", "PHY12_EN", "PHY0_RESET", +- "PHY0_INT", "", "", "", +- "", "", "DISP1_EN", "DISP1_LR", "DISP1_TS_IRQ", "LVDS1_PD", +- "", "", +- "", "LVDS1_INT", "", "", "DISP0_LR", "DISP0_TS_IRQ", +- "DISP0_EN", "CAM_GPIO0"; +-}; +- +-&gpio6 { +- gpio-line-names = +- "LVDS0_INT", "LVDS0_PD", "CAM_INT", "CAM_GPIO1", "CAM_PD", +- "CAM_LOCK", "", "POWER_TG", +- "POWER_VSEL", "", "WLAN_REG_ON", "USB_ETH_CHG", "", "", +- "USB_ETH_CHG_ID0", "USB_ETH_CHG_ID1", +- "USB_ETH_CHG_ID2", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- /* additional i2c devices are added automatically by the boot loader */ +-}; +- +-&i2c3 { +- adc@49 { +- compatible = "ti,ads1015"; +- reg = <0x49>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* VIN */ +- channel@4 { +- reg = <4>; +- ti,gain = <1>; +- ti,datarate = <3>; +- }; +- +- /* VBUS */ +- channel@5 { +- reg = <5>; +- ti,gain = <1>; +- ti,datarate = <3>; +- }; +- +- /* ICHG */ +- channel@6 { +- reg = <6>; +- ti,gain = <1>; +- ti,datarate = <3>; +- }; +- +- channel@7 { +- reg = <7>; +- ti,gain = <1>; +- ti,datarate = <3>; +- }; +- }; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbotg { +- vbus-supply = <®_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg>; +- phy_type = "utmi"; +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbphynop1 { +- status = "disabled"; +-}; +- +-&usbphynop2 { +- status = "disabled"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- disable-wp; +- cap-sd-highspeed; +- no-mmc; +- no-sdio; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- no-1-8-v; +- non-removable; +- mmc-pwrseq = <&usdhc2_wifi_pwrseq>; +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- brcmf: bcrmf@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- no-sd; +- no-sdio; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 +- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 +- /* CAN1_SR */ +- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 +- >; +- }; +- +- pinctrl_can2: can2grp { +- fsl,pins = < +- /* CAN2_nINT */ +- MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 +- /* CAN2_SR */ +- MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13070 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 +- MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 +- MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 +- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 +- >; +- }; +- +- pinctrl_ecspi3: ecspi3grp { +- fsl,pins = < +- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 +- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 +- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 +- /* CS */ +- MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 +- +- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 +- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 +- +- /* Configure clock provider for RGMII ref clock */ +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 +- /* Configure clock consumer for RGMII ref clock */ +- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 +- +- /* SJA1105Q switch reset */ +- MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x10030 +- +- /* phy3/rgmii_phy reset */ +- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x10030 +- /* phy3/rgmii_phy int */ +- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x40010000 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 +- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 +- >; +- }; +- +- pinctrl_mdio: mdiogrp { +- fsl,pins = < +- /* phy0/usbeth_phy reset */ +- MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x10030 +- /* phy0/usbeth_phy int */ +- MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 +- +- /* phy12/tja1102_phy0 reset */ +- MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x10030 +- /* phy12/tja1102_phy0 int */ +- MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x100b1 +- /* phy12/tja1102_phy0 enable. Set 100K pull-up */ +- MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1f030 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 +- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg: usbotggrp { +- fsl,pins = < +- MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 +- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 +- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 +- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 +- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 +- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 +- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 +- MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 +- MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 +- >; +- }; +- +- pinctrl_wifi_npd: wifinpd { +- fsl,pins = < +- /* WL_REG_ON */ +- MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qp-sabreauto.dts b/scripts/dtc/include-prefixes/arm/imx6qp-sabreauto.dts +deleted file mode 100644 +index 2bb3bfb18ec3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qp-sabreauto.dts ++++ /dev/null +@@ -1,60 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Copyright 2016 Freescale Semiconductor, Inc. +- +-/dts-v1/; +- +-#include "imx6qp.dtsi" +-#include "imx6qdl-sabreauto.dtsi" +- +-/ { +- model = "Freescale i.MX6 Quad Plus SABRE Automotive Board"; +- compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp"; +-}; +- +-&i2c2 { +- max7322: gpio@68 { +- compatible = "maxim,max7322"; +- reg = <0x68>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&iomuxc { +- imx6qdl-sabreauto { +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 +- MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 +- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b018 +- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b018 +- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b018 +- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b018 +- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b018 +- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b018 +- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b018 +- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b018 +- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b018 +- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b018 +- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b018 +- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b018 +- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 +- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 +- >; +- }; +- }; +-}; +- +-&pcie { +- reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&vgen3_reg { +- regulator-always-on; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qp-sabresd.dts b/scripts/dtc/include-prefixes/arm/imx6qp-sabresd.dts +deleted file mode 100644 +index 480e73183f6b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qp-sabresd.dts ++++ /dev/null +@@ -1,59 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Copyright 2016 Freescale Semiconductor, Inc. +- +-/dts-v1/; +- +-#include "imx6qp.dtsi" +-#include "imx6qdl-sabresd.dtsi" +- +-/ { +- model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board"; +- compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp"; +-}; +- +-®_arm { +- vin-supply = <&sw2_reg>; +-}; +- +-&iomuxc { +- imx6qdl-sabresd { +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 +- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 +- MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 +- MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 +- MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 +- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 +- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 +- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 +- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +- >; +- }; +- }; +-}; +- +-&pcie { +- status = "disabled"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qp-tqma6b.dtsi b/scripts/dtc/include-prefixes/arm/imx6qp-tqma6b.dtsi +deleted file mode 100644 +index bb6ff7c64b27..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qp-tqma6b.dtsi ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Sascha Hauer, Pengutronix +- */ +- +-#include "imx6q.dtsi" +-#include "imx6qp.dtsi" +-#include "imx6qdl-tqma6b.dtsi" +-#include "imx6qdl-tqma6.dtsi" +- +-/ { +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x40000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qp-tx6qp-8037-mb7.dts b/scripts/dtc/include-prefixes/arm/imx6qp-tx6qp-8037-mb7.dts +deleted file mode 100644 +index 92b38e6699aa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qp-tx6qp-8037-mb7.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* +- * Copyright 2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6qp-tx6qp-8037.dts" +-#include "imx6qdl-tx6-mb7.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6Q-8037 Module on MB7 baseboard"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qp-tx6qp-8037.dts b/scripts/dtc/include-prefixes/arm/imx6qp-tx6qp-8037.dts +deleted file mode 100644 +index ffc0f2ee11d2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qp-tx6qp-8037.dts ++++ /dev/null +@@ -1,86 +0,0 @@ +-/* +- * Copyright 2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6qp.dtsi" +-#include "imx6qdl-tx6.dtsi" +-#include "imx6qdl-tx6-lcd.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6QP-8037 Module"; +- compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp"; +-}; +- +-&ds1339 { +- status = "disabled"; +-}; +- +-&gpmi { +- status = "disabled"; +-}; +- +-&ipu2 { +- status = "disabled"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <4>; +- non-removable; +- no-1-8-v; +- fsl,wp-controller; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 +- MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qp-tx6qp-8137-mb7.dts b/scripts/dtc/include-prefixes/arm/imx6qp-tx6qp-8137-mb7.dts +deleted file mode 100644 +index 07ad70718aec..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qp-tx6qp-8137-mb7.dts ++++ /dev/null +@@ -1,57 +0,0 @@ +-/* +- * Copyright 2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6qp-tx6qp-8137.dts" +-#include "imx6qdl-tx6-mb7.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6Q-8137 Module on MB7 baseboard"; +- compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp"; +-}; +- +-&ipu2 { +- status = "disabled"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qp-tx6qp-8137.dts b/scripts/dtc/include-prefixes/arm/imx6qp-tx6qp-8137.dts +deleted file mode 100644 +index dd494d587014..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qp-tx6qp-8137.dts ++++ /dev/null +@@ -1,90 +0,0 @@ +-/* +- * Copyright 2017 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6qp.dtsi" +-#include "imx6qdl-tx6.dtsi" +-#include "imx6qdl-tx6-lvds.dtsi" +- +-/ { +- model = "Ka-Ro electronics TX6QP-8137 Module"; +- compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp"; +-}; +- +-&ds1339 { +- status = "disabled"; +-}; +- +-&gpmi { +- status = "disabled"; +-}; +- +-&ipu2 { +- status = "disabled"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <4>; +- non-removable; +- no-1-8-v; +- fsl,wp-controller; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 +- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 +- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 +- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 +- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 +- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 +- MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qp-vicutp.dts b/scripts/dtc/include-prefixes/arm/imx6qp-vicutp.dts +deleted file mode 100644 +index 7bad7ca6b12e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qp-vicutp.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (c) 2014 Protonic Holland +- */ +- +-/dts-v1/; +-#include "imx6qp.dtsi" +-#include "imx6qdl-vicut1.dtsi" +- +-/ { +- model = "Kverneland UT1P Board"; +- compatible = "kvg,vicutp", "fsl,imx6qp"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qp-wandboard-revd1.dts b/scripts/dtc/include-prefixes/arm/imx6qp-wandboard-revd1.dts +deleted file mode 100644 +index 08d8b78a2096..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qp-wandboard-revd1.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- * +- * Author: Fabio Estevam +- */ +-/dts-v1/; +-#include "imx6qp.dtsi" +-#include "imx6qdl-wandboard-revd1.dtsi" +- +-/ { +- model = "Wandboard i.MX6 QuadPlus Board revD1"; +- compatible = "wand,imx6qp-wandboard", "fsl,imx6qp"; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x80000000>; +- }; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qp-zii-rdu2.dts b/scripts/dtc/include-prefixes/arm/imx6qp-zii-rdu2.dts +deleted file mode 100644 +index 57de447c4609..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qp-zii-rdu2.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2016-2017 Zodiac Inflight Innovations +- */ +- +-/dts-v1/; +- +-#include "imx6qp.dtsi" +-#include "imx6qdl-zii-rdu2.dtsi" +- +-/ { +- model = "ZII RDU2+ Board"; +- compatible = "zii,imx6qp-zii-rdu2", "fsl,imx6qp"; +- +- /* Will be filled by the bootloader */ +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0>; +- }; +-}; +- +-&gpu_3d { +- assigned-clocks = <&clks IMX6QDL_CLK_GPU3D_SHADER_SEL>; +- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD1_594M>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6qp.dtsi b/scripts/dtc/include-prefixes/arm/imx6qp.dtsi +deleted file mode 100644 +index b310f13a53f2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6qp.dtsi ++++ /dev/null +@@ -1,114 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Copyright 2016 Freescale Semiconductor, Inc. +- +-#include "imx6q.dtsi" +- +-/ { +- soc { +- ocram2: sram@940000 { +- compatible = "mmio-sram"; +- reg = <0x00940000 0x20000>; +- clocks = <&clks IMX6QDL_CLK_OCRAM>; +- }; +- +- ocram3: sram@960000 { +- compatible = "mmio-sram"; +- reg = <0x00960000 0x20000>; +- clocks = <&clks IMX6QDL_CLK_OCRAM>; +- }; +- +- bus@2100000 { +- pre1: pre@21c8000 { +- compatible = "fsl,imx6qp-pre"; +- reg = <0x021c8000 0x1000>; +- interrupts = ; +- clocks = <&clks IMX6QDL_CLK_PRE0>; +- clock-names = "axi"; +- fsl,iram = <&ocram2>; +- }; +- +- pre2: pre@21c9000 { +- compatible = "fsl,imx6qp-pre"; +- reg = <0x021c9000 0x1000>; +- interrupts = ; +- clocks = <&clks IMX6QDL_CLK_PRE1>; +- clock-names = "axi"; +- fsl,iram = <&ocram2>; +- }; +- +- pre3: pre@21ca000 { +- compatible = "fsl,imx6qp-pre"; +- reg = <0x021ca000 0x1000>; +- interrupts = ; +- clocks = <&clks IMX6QDL_CLK_PRE2>; +- clock-names = "axi"; +- fsl,iram = <&ocram3>; +- }; +- +- pre4: pre@21cb000 { +- compatible = "fsl,imx6qp-pre"; +- reg = <0x021cb000 0x1000>; +- interrupts = ; +- clocks = <&clks IMX6QDL_CLK_PRE3>; +- clock-names = "axi"; +- fsl,iram = <&ocram3>; +- }; +- +- prg1: prg@21cc000 { +- compatible = "fsl,imx6qp-prg"; +- reg = <0x021cc000 0x1000>; +- clocks = <&clks IMX6QDL_CLK_PRG0_APB>, +- <&clks IMX6QDL_CLK_PRG0_AXI>; +- clock-names = "ipg", "axi"; +- fsl,pres = <&pre1>, <&pre2>, <&pre3>; +- }; +- +- prg2: prg@21cd000 { +- compatible = "fsl,imx6qp-prg"; +- reg = <0x021cd000 0x1000>; +- clocks = <&clks IMX6QDL_CLK_PRG1_APB>, +- <&clks IMX6QDL_CLK_PRG1_AXI>; +- clock-names = "ipg", "axi"; +- fsl,pres = <&pre4>, <&pre2>, <&pre3>; +- }; +- }; +- }; +-}; +- +-&fec { +- interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>, +- <0 119 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&gpc { +- compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc"; +-}; +- +-&ipu1 { +- compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; +- fsl,prg = <&prg1>; +-}; +- +-&ipu2 { +- compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; +- fsl,prg = <&prg2>; +-}; +- +-&ldb { +- clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, +- <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, +- <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, +- <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>; +- clock-names = "di0_pll", "di1_pll", +- "di0_sel", "di1_sel", "di2_sel", "di3_sel", +- "di0", "di1"; +-}; +- +-&mmdc0 { +- compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc"; +-}; +- +-&pcie { +- compatible = "fsl,imx6qp-pcie", "snps,dw-pcie"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6s-dhcom-drc02.dts b/scripts/dtc/include-prefixes/arm/imx6s-dhcom-drc02.dts +deleted file mode 100644 +index 4077b607c29e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6s-dhcom-drc02.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2021 DH electronics GmbH +- * +- * DHCOM iMX6 variant: +- * DHCM-iMX6S-C0800-R102-F0409-E-CAN2-RTC-I-01D2 +- * DHCOM PCB number: 493-400 or newer +- * DRC02 PCB number: 568-100 or newer +- */ +-/dts-v1/; +- +-/* +- * The kernel only distinguishes between i.MX6 Quad and DualLite, +- * but the Solo is actually a DualLite with only one CPU. So use +- * DualLite for the Solo and disable one CPU node. +- */ +- +-#include "imx6dl.dtsi" +-#include "imx6qdl-dhcom-som.dtsi" +-#include "imx6qdl-dhcom-drc02.dtsi" +- +-/ { +- model = "DH electronics i.MX6S DHCOM on DRC02"; +- compatible = "dh,imx6s-dhcom-drc02", "dh,imx6s-dhcom-som", +- "fsl,imx6dl"; +- +- cpus { +- /delete-node/ cpu@1; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sl-evk.dts b/scripts/dtc/include-prefixes/arm/imx6sl-evk.dts +deleted file mode 100644 +index 25f6f2fb1555..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sl-evk.dts ++++ /dev/null +@@ -1,658 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-//Copyright (C) 2013 Freescale Semiconductor, Inc. +- +-/dts-v1/; +- +-#include +-#include +-#include "imx6sl.dtsi" +- +-/ { +- model = "Freescale i.MX6 SoloLite EVK Board"; +- compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; +- }; +- +- backlight_display: backlight_display { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led>; +- +- user { +- label = "debug"; +- gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- reg_usb_otg1_vbus: regulator-usb-otg1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&swbst_reg>; +- }; +- +- reg_usb_otg2_vbus: regulator-usb-otg2-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg2_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&swbst_reg>; +- }; +- +- reg_aud3v: regulator-aud3v { +- compatible = "regulator-fixed"; +- regulator-name = "wm8962-supply-3v15"; +- regulator-min-microvolt = <3150000>; +- regulator-max-microvolt = <3150000>; +- regulator-boot-on; +- }; +- +- reg_aud4v: regulator-aud4v { +- compatible = "regulator-fixed"; +- regulator-name = "wm8962-supply-4v2"; +- regulator-min-microvolt = <4325000>; +- regulator-max-microvolt = <4325000>; +- regulator-boot-on; +- }; +- +- reg_lcd_3v3: regulator-lcd-3v3 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_lcd_3v3>; +- regulator-name = "lcd-3v3"; +- gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_lcd_5v: regulator-lcd-5v { +- compatible = "regulator-fixed"; +- regulator-name = "lcd-5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- sound { +- compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hp>; +- model = "wm8962-audio"; +- ssi-controller = <&ssi2>; +- audio-codec = <&codec>; +- audio-routing = +- "Headphone Jack", "HPOUTL", +- "Headphone Jack", "HPOUTR", +- "Ext Spk", "SPKOUTL", +- "Ext Spk", "SPKOUTR", +- "AMIC", "MICBIAS", +- "IN3R", "AMIC"; +- mux-int-port = <2>; +- mux-ext-port = <3>; +- hp-det-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; +- }; +- +- panel { +- compatible = "sii,43wvf1g"; +- backlight = <&backlight_display>; +- dvdd-supply = <®_lcd_3v3>; +- avdd-supply = <®_lcd_5v>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux3>; +- status = "okay"; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p32", "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +- +-&fec { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&pinctrl_fec>; +- pinctrl-1 = <&pinctrl_fec_sleep>; +- phy-mode = "rmii"; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic: pfuze100@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- regulator-always-on; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- codec: wm8962@1a { +- compatible = "wlf,wm8962"; +- reg = <0x1a>; +- clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>; +- DCVDD-supply = <&vgen3_reg>; +- DBVDD-supply = <®_aud3v>; +- AVDD-supply = <&vgen3_reg>; +- CPVDD-supply = <&vgen3_reg>; +- MICVDD-supply = <®_aud3v>; +- PLLVDD-supply = <&vgen3_reg>; +- SPKVDD1-supply = <®_aud4v>; +- SPKVDD2-supply = <®_aud4v>; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx6sl-evk { +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 +- MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059 +- MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059 +- MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059 +- MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 +- MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 +- MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 +- MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 +- >; +- }; +- +- pinctrl_audmux3: audmux3grp { +- fsl,pins = < +- MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 +- MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 +- MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 +- MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 +- MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 +- MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 +- MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 +- MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0 +- MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0 +- MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0 +- MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0 +- MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0 +- MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0 +- MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0 +- MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8 +- >; +- }; +- +- pinctrl_fec_sleep: fecgrp-sleep { +- fsl,pins = < +- MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080 +- MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080 +- MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080 +- MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080 +- MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080 +- MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080 +- MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080 +- MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080 +- >; +- }; +- +- pinctrl_hp: hpgrp { +- fsl,pins = < +- MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 +- MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1 +- MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_kpp: kppgrp { +- fsl,pins = < +- MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 +- MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010 +- MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0 +- MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0 +- MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0 +- MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0 +- >; +- }; +- +- pinctrl_lcd: lcdgrp { +- fsl,pins = < +- MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0 +- MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0 +- MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0 +- MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0 +- MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0 +- MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0 +- MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0 +- MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0 +- MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0 +- MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0 +- MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0 +- MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0 +- MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0 +- MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0 +- MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0 +- MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0 +- MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0 +- MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0 +- MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0 +- MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0 +- MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0 +- MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0 +- MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0 +- MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0 +- MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0 +- MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0 +- MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0 +- MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0 +- >; +- }; +- +- pinctrl_led: ledgrp { +- fsl,pins = < +- MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059 +- >; +- }; +- +- pinctrl_pwm1: pwmgrp { +- fsl,pins = < +- MX6SL_PAD_PWM1__PWM1_OUT 0x110b0 +- >; +- }; +- +- pinctrl_reg_lcd_3v3: reglcd3v3grp { +- fsl,pins = < +- MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 +- MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg1: usbotg1grp { +- fsl,pins = < +- MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 +- MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 +- MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 +- MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 +- MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 +- MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 +- MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 +- MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 +- MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 +- MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1grp100mhz { +- fsl,pins = < +- MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 +- MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9 +- MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 +- MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 +- MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 +- MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 +- MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 +- MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 +- MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 +- MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1grp200mhz { +- fsl,pins = < +- MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 +- MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9 +- MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 +- MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 +- MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 +- MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 +- MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9 +- MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9 +- MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9 +- MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059 +- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2grp100mhz { +- fsl,pins = < +- MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 +- MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9 +- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 +- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 +- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 +- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2grp200mhz { +- fsl,pins = < +- MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 +- MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9 +- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 +- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 +- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 +- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 +- MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 +- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 +- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059 +- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059 +- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp100mhz { +- fsl,pins = < +- MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 +- MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9 +- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 +- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 +- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 +- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp200mhz { +- fsl,pins = < +- MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 +- MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9 +- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 +- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 +- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 +- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 +- >; +- }; +- }; +-}; +- +-&kpp { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_kpp>; +- linux,keymap = < +- MATRIX_KEY(0x0, 0x0, KEY_UP) /* ROW0, COL0 */ +- MATRIX_KEY(0x0, 0x1, KEY_DOWN) /* ROW0, COL1 */ +- MATRIX_KEY(0x0, 0x2, KEY_ENTER) /* ROW0, COL2 */ +- MATRIX_KEY(0x1, 0x0, KEY_HOME) /* ROW1, COL0 */ +- MATRIX_KEY(0x1, 0x1, KEY_RIGHT) /* ROW1, COL1 */ +- MATRIX_KEY(0x1, 0x2, KEY_LEFT) /* ROW1, COL2 */ +- MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */ +- MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */ +- >; +- status = "okay"; +-}; +- +-&lcdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd>; +- status = "okay"; +- +- port { +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-®_vdd1p1 { +- vin-supply = <&sw2_reg>; +-}; +- +-®_vdd2p5 { +- vin-supply = <&sw2_reg>; +-}; +- +-&snvs_poweroff { +- status = "okay"; +-}; +- +-&ssi2 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usbotg1 { +- vbus-supply = <®_usb_otg1_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg1>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbotg2 { +- vbus-supply = <®_usb_otg2_vbus>; +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- bus-width = <8>; +- cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>; +- cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sl-pinfunc.h b/scripts/dtc/include-prefixes/arm/imx6sl-pinfunc.h +deleted file mode 100644 +index bcf16060ecdc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sl-pinfunc.h ++++ /dev/null +@@ -1,1073 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __DTS_IMX6SL_PINFUNC_H +-#define __DTS_IMX6SL_PINFUNC_H +- +-/* +- * The pin function ID is a tuple of +- * +- */ +-#define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 +-#define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 +-#define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 +-#define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 +-#define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 +-#define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 +-#define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 +-#define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 +-#define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 +-#define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 +-#define MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x050 0x2a8 0x80c 0x2 0x0 +-#define MX6SL_PAD_AUD_RXC__FEC_TX_CLK 0x050 0x2a8 0x70c 0x3 0x0 +-#define MX6SL_PAD_AUD_RXC__I2C3_SDA 0x050 0x2a8 0x730 0x4 0x0 +-#define MX6SL_PAD_AUD_RXC__GPIO1_IO01 0x050 0x2a8 0x000 0x5 0x0 +-#define MX6SL_PAD_AUD_RXC__ECSPI3_SS1 0x050 0x2a8 0x6c4 0x6 0x0 +-#define MX6SL_PAD_AUD_RXD__AUD3_RXD 0x054 0x2ac 0x000 0x0 0x0 +-#define MX6SL_PAD_AUD_RXD__ECSPI3_MOSI 0x054 0x2ac 0x6bc 0x1 0x0 +-#define MX6SL_PAD_AUD_RXD__UART4_RX_DATA 0x054 0x2ac 0x814 0x2 0x0 +-#define MX6SL_PAD_AUD_RXD__UART4_TX_DATA 0x054 0x2ac 0x000 0x2 0x0 +-#define MX6SL_PAD_AUD_RXD__FEC_RX_ER 0x054 0x2ac 0x708 0x3 0x0 +-#define MX6SL_PAD_AUD_RXD__SD1_LCTL 0x054 0x2ac 0x000 0x4 0x0 +-#define MX6SL_PAD_AUD_RXD__GPIO1_IO02 0x054 0x2ac 0x000 0x5 0x0 +-#define MX6SL_PAD_AUD_RXFS__AUD3_RXFS 0x058 0x2b0 0x000 0x0 0x0 +-#define MX6SL_PAD_AUD_RXFS__I2C1_SCL 0x058 0x2b0 0x71c 0x1 0x0 +-#define MX6SL_PAD_AUD_RXFS__UART3_RX_DATA 0x058 0x2b0 0x80c 0x2 0x1 +-#define MX6SL_PAD_AUD_RXFS__UART3_TX_DATA 0x058 0x2b0 0x000 0x2 0x0 +-#define MX6SL_PAD_AUD_RXFS__FEC_MDIO 0x058 0x2b0 0x6f4 0x3 0x0 +-#define MX6SL_PAD_AUD_RXFS__I2C3_SCL 0x058 0x2b0 0x72c 0x4 0x0 +-#define MX6SL_PAD_AUD_RXFS__GPIO1_IO00 0x058 0x2b0 0x000 0x5 0x0 +-#define MX6SL_PAD_AUD_RXFS__ECSPI3_SS0 0x058 0x2b0 0x6c0 0x6 0x0 +-#define MX6SL_PAD_AUD_TXC__AUD3_TXC 0x05c 0x2b4 0x000 0x0 0x0 +-#define MX6SL_PAD_AUD_TXC__ECSPI3_MISO 0x05c 0x2b4 0x6b8 0x1 0x0 +-#define MX6SL_PAD_AUD_TXC__UART4_TX_DATA 0x05c 0x2b4 0x000 0x2 0x0 +-#define MX6SL_PAD_AUD_TXC__UART4_RX_DATA 0x05c 0x2b4 0x814 0x2 0x1 +-#define MX6SL_PAD_AUD_TXC__FEC_RX_DV 0x05c 0x2b4 0x704 0x3 0x0 +-#define MX6SL_PAD_AUD_TXC__SD2_LCTL 0x05c 0x2b4 0x000 0x4 0x0 +-#define MX6SL_PAD_AUD_TXC__GPIO1_IO03 0x05c 0x2b4 0x000 0x5 0x0 +-#define MX6SL_PAD_AUD_TXD__AUD3_TXD 0x060 0x2b8 0x000 0x0 0x0 +-#define MX6SL_PAD_AUD_TXD__ECSPI3_SCLK 0x060 0x2b8 0x6b0 0x1 0x0 +-#define MX6SL_PAD_AUD_TXD__UART4_CTS_B 0x060 0x2b8 0x000 0x2 0x0 +-#define MX6SL_PAD_AUD_TXD__UART4_RTS_B 0x060 0x2b8 0x810 0x2 0x0 +-#define MX6SL_PAD_AUD_TXD__FEC_TX_DATA0 0x060 0x2b8 0x000 0x3 0x0 +-#define MX6SL_PAD_AUD_TXD__SD4_LCTL 0x060 0x2b8 0x000 0x4 0x0 +-#define MX6SL_PAD_AUD_TXD__GPIO1_IO05 0x060 0x2b8 0x000 0x5 0x0 +-#define MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x064 0x2bc 0x000 0x0 0x0 +-#define MX6SL_PAD_AUD_TXFS__PWM3_OUT 0x064 0x2bc 0x000 0x1 0x0 +-#define MX6SL_PAD_AUD_TXFS__UART4_RTS_B 0x064 0x2bc 0x810 0x2 0x1 +-#define MX6SL_PAD_AUD_TXFS__UART4_CTS_B 0x064 0x2bc 0x000 0x2 0x0 +-#define MX6SL_PAD_AUD_TXFS__FEC_RX_DATA1 0x064 0x2bc 0x6fc 0x3 0x0 +-#define MX6SL_PAD_AUD_TXFS__SD3_LCTL 0x064 0x2bc 0x000 0x4 0x0 +-#define MX6SL_PAD_AUD_TXFS__GPIO1_IO04 0x064 0x2bc 0x000 0x5 0x0 +-#define MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x068 0x358 0x684 0x0 0x0 +-#define MX6SL_PAD_ECSPI1_MISO__AUD4_TXFS 0x068 0x358 0x5f8 0x1 0x0 +-#define MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x068 0x358 0x818 0x2 0x0 +-#define MX6SL_PAD_ECSPI1_MISO__UART5_CTS_B 0x068 0x358 0x000 0x2 0x0 +-#define MX6SL_PAD_ECSPI1_MISO__EPDC_BDR0 0x068 0x358 0x000 0x3 0x0 +-#define MX6SL_PAD_ECSPI1_MISO__SD2_WP 0x068 0x358 0x834 0x4 0x0 +-#define MX6SL_PAD_ECSPI1_MISO__GPIO4_IO10 0x068 0x358 0x000 0x5 0x0 +-#define MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x06c 0x35c 0x688 0x0 0x0 +-#define MX6SL_PAD_ECSPI1_MOSI__AUD4_TXC 0x06c 0x35c 0x5f4 0x1 0x0 +-#define MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x06c 0x35c 0x000 0x2 0x0 +-#define MX6SL_PAD_ECSPI1_MOSI__UART5_RX_DATA 0x06c 0x35c 0x81c 0x2 0x0 +-#define MX6SL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x06c 0x35c 0x000 0x3 0x0 +-#define MX6SL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x06c 0x35c 0x000 0x4 0x0 +-#define MX6SL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x06c 0x35c 0x000 0x5 0x0 +-#define MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x070 0x360 0x67c 0x0 0x0 +-#define MX6SL_PAD_ECSPI1_SCLK__AUD4_TXD 0x070 0x360 0x5e8 0x1 0x0 +-#define MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x070 0x360 0x81c 0x2 0x1 +-#define MX6SL_PAD_ECSPI1_SCLK__UART5_TX_DATA 0x070 0x360 0x000 0x2 0x0 +-#define MX6SL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x070 0x360 0x000 0x3 0x0 +-#define MX6SL_PAD_ECSPI1_SCLK__SD2_RESET 0x070 0x360 0x000 0x4 0x0 +-#define MX6SL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x070 0x360 0x000 0x5 0x0 +-#define MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x070 0x360 0x820 0x6 0x0 +-#define MX6SL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x074 0x364 0x68c 0x0 0x0 +-#define MX6SL_PAD_ECSPI1_SS0__AUD4_RXD 0x074 0x364 0x5e4 0x1 0x0 +-#define MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x074 0x364 0x000 0x2 0x0 +-#define MX6SL_PAD_ECSPI1_SS0__UART5_RTS_B 0x074 0x364 0x818 0x2 0x1 +-#define MX6SL_PAD_ECSPI1_SS0__EPDC_BDR1 0x074 0x364 0x000 0x3 0x0 +-#define MX6SL_PAD_ECSPI1_SS0__SD2_CD_B 0x074 0x364 0x830 0x4 0x0 +-#define MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x074 0x364 0x000 0x5 0x0 +-#define MX6SL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x074 0x364 0x000 0x6 0x0 +-#define MX6SL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x078 0x368 0x6a0 0x0 0x0 +-#define MX6SL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x078 0x368 0x000 0x1 0x0 +-#define MX6SL_PAD_ECSPI2_MISO__UART3_RTS_B 0x078 0x368 0x808 0x2 0x0 +-#define MX6SL_PAD_ECSPI2_MISO__UART3_CTS_B 0x078 0x368 0x000 0x2 0x0 +-#define MX6SL_PAD_ECSPI2_MISO__CSI_MCLK 0x078 0x368 0x000 0x3 0x0 +-#define MX6SL_PAD_ECSPI2_MISO__SD1_WP 0x078 0x368 0x82c 0x4 0x0 +-#define MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x078 0x368 0x000 0x5 0x0 +-#define MX6SL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x078 0x368 0x824 0x6 0x0 +-#define MX6SL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x07c 0x36c 0x6a4 0x0 0x0 +-#define MX6SL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x07c 0x36c 0x000 0x1 0x0 +-#define MX6SL_PAD_ECSPI2_MOSI__UART3_TX_DATA 0x07c 0x36c 0x000 0x2 0x0 +-#define MX6SL_PAD_ECSPI2_MOSI__UART3_RX_DATA 0x07c 0x36c 0x80c 0x2 0x2 +-#define MX6SL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x07c 0x36c 0x670 0x3 0x0 +-#define MX6SL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x07c 0x36c 0x000 0x4 0x0 +-#define MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x07c 0x36c 0x000 0x5 0x0 +-#define MX6SL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x080 0x370 0x69c 0x0 0x0 +-#define MX6SL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x080 0x370 0x7f4 0x1 0x1 +-#define MX6SL_PAD_ECSPI2_SCLK__UART3_RX_DATA 0x080 0x370 0x80c 0x2 0x3 +-#define MX6SL_PAD_ECSPI2_SCLK__UART3_TX_DATA 0x080 0x370 0x000 0x2 0x0 +-#define MX6SL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x080 0x370 0x674 0x3 0x0 +-#define MX6SL_PAD_ECSPI2_SCLK__SD1_RESET 0x080 0x370 0x000 0x4 0x0 +-#define MX6SL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x080 0x370 0x000 0x5 0x0 +-#define MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x080 0x370 0x820 0x6 0x1 +-#define MX6SL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x084 0x374 0x6a8 0x0 0x0 +-#define MX6SL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x084 0x374 0x698 0x1 0x0 +-#define MX6SL_PAD_ECSPI2_SS0__UART3_CTS_B 0x084 0x374 0x000 0x2 0x0 +-#define MX6SL_PAD_ECSPI2_SS0__UART3_RTS_B 0x084 0x374 0x808 0x2 0x1 +-#define MX6SL_PAD_ECSPI2_SS0__CSI_VSYNC 0x084 0x374 0x678 0x3 0x0 +-#define MX6SL_PAD_ECSPI2_SS0__SD1_CD_B 0x084 0x374 0x828 0x4 0x0 +-#define MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x084 0x374 0x000 0x5 0x0 +-#define MX6SL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x084 0x374 0x000 0x6 0x0 +-#define MX6SL_PAD_EPDC_BDR0__EPDC_BDR0 0x088 0x378 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_BDR0__SD4_CLK 0x088 0x378 0x850 0x1 0x0 +-#define MX6SL_PAD_EPDC_BDR0__UART3_RTS_B 0x088 0x378 0x808 0x2 0x2 +-#define MX6SL_PAD_EPDC_BDR0__UART3_CTS_B 0x088 0x378 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_BDR0__EIM_ADDR26 0x088 0x378 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_BDR0__SPDC_RL 0x088 0x378 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_BDR0__GPIO2_IO05 0x088 0x378 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_BDR0__EPDC_SDCE7 0x088 0x378 0x000 0x6 0x0 +-#define MX6SL_PAD_EPDC_BDR1__EPDC_BDR1 0x08c 0x37c 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_BDR1__SD4_CMD 0x08c 0x37c 0x858 0x1 0x0 +-#define MX6SL_PAD_EPDC_BDR1__UART3_CTS_B 0x08c 0x37c 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_BDR1__UART3_RTS_B 0x08c 0x37c 0x808 0x2 0x3 +-#define MX6SL_PAD_EPDC_BDR1__EIM_CRE 0x08c 0x37c 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_BDR1__SPDC_UD 0x08c 0x37c 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_BDR1__GPIO2_IO06 0x08c 0x37c 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_BDR1__EPDC_SDCE8 0x08c 0x37c 0x000 0x6 0x0 +-#define MX6SL_PAD_EPDC_D0__EPDC_DATA00 0x090 0x380 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_D0__ECSPI4_MOSI 0x090 0x380 0x6d8 0x1 0x0 +-#define MX6SL_PAD_EPDC_D0__LCD_DATA24 0x090 0x380 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_D0__CSI_DATA00 0x090 0x380 0x630 0x3 0x0 +-#define MX6SL_PAD_EPDC_D0__SPDC_DATA00 0x090 0x380 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_D0__GPIO1_IO07 0x090 0x380 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_D1__EPDC_DATA01 0x094 0x384 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_D1__ECSPI4_MISO 0x094 0x384 0x6d4 0x1 0x0 +-#define MX6SL_PAD_EPDC_D1__LCD_DATA25 0x094 0x384 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_D1__CSI_DATA01 0x094 0x384 0x634 0x3 0x0 +-#define MX6SL_PAD_EPDC_D1__SPDC_DATA01 0x094 0x384 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_D1__GPIO1_IO08 0x094 0x384 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x098 0x388 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_D10__ECSPI3_SS0 0x098 0x388 0x6c0 0x1 0x1 +-#define MX6SL_PAD_EPDC_D10__EPDC_PWR_CTRL2 0x098 0x388 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_D10__EIM_ADDR18 0x098 0x388 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_D10__SPDC_DATA10 0x098 0x388 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_D10__GPIO1_IO17 0x098 0x388 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_D10__SD4_WP 0x098 0x388 0x87c 0x6 0x0 +-#define MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x09c 0x38c 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_D11__ECSPI3_SCLK 0x09c 0x38c 0x6b0 0x1 0x1 +-#define MX6SL_PAD_EPDC_D11__EPDC_PWR_CTRL3 0x09c 0x38c 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_D11__EIM_ADDR19 0x09c 0x38c 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_D11__SPDC_DATA11 0x09c 0x38c 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_D11__GPIO1_IO18 0x09c 0x38c 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_D11__SD4_CD_B 0x09c 0x38c 0x854 0x6 0x0 +-#define MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x0a0 0x390 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x0a0 0x390 0x804 0x1 0x0 +-#define MX6SL_PAD_EPDC_D12__UART2_TX_DATA 0x0a0 0x390 0x000 0x1 0x0 +-#define MX6SL_PAD_EPDC_D12__EPDC_PWR_COM 0x0a0 0x390 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_D12__EIM_ADDR20 0x0a0 0x390 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_D12__SPDC_DATA12 0x0a0 0x390 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_D12__GPIO1_IO19 0x0a0 0x390 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_D12__ECSPI3_SS1 0x0a0 0x390 0x6c4 0x6 0x1 +-#define MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x0a4 0x394 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x0a4 0x394 0x000 0x1 0x0 +-#define MX6SL_PAD_EPDC_D13__UART2_RX_DATA 0x0a4 0x394 0x804 0x1 0x1 +-#define MX6SL_PAD_EPDC_D13__EPDC_PWR_IRQ 0x0a4 0x394 0x6e8 0x2 0x0 +-#define MX6SL_PAD_EPDC_D13__EIM_ADDR21 0x0a4 0x394 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_D13__SPDC_DATA13 0x0a4 0x394 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_D13__GPIO1_IO20 0x0a4 0x394 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_D13__ECSPI3_SS2 0x0a4 0x394 0x6c8 0x6 0x0 +-#define MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x0a8 0x398 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x0a8 0x398 0x800 0x1 0x0 +-#define MX6SL_PAD_EPDC_D14__UART2_CTS_B 0x0a8 0x398 0x000 0x1 0x0 +-#define MX6SL_PAD_EPDC_D14__EPDC_PWR_STAT 0x0a8 0x398 0x6ec 0x2 0x0 +-#define MX6SL_PAD_EPDC_D14__EIM_ADDR22 0x0a8 0x398 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_D14__SPDC_DATA14 0x0a8 0x398 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_D14__GPIO1_IO21 0x0a8 0x398 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_D14__ECSPI3_SS3 0x0a8 0x398 0x6cc 0x6 0x0 +-#define MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x0ac 0x39c 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x0ac 0x39c 0x000 0x1 0x0 +-#define MX6SL_PAD_EPDC_D15__UART2_RTS_B 0x0ac 0x39c 0x800 0x1 0x1 +-#define MX6SL_PAD_EPDC_D15__EPDC_PWR_WAKE 0x0ac 0x39c 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_D15__EIM_ADDR23 0x0ac 0x39c 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_D15__SPDC_DATA15 0x0ac 0x39c 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_D15__GPIO1_IO22 0x0ac 0x39c 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_D15__ECSPI3_RDY 0x0ac 0x39c 0x6b4 0x6 0x1 +-#define MX6SL_PAD_EPDC_D2__EPDC_DATA02 0x0b0 0x3a0 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_D2__ECSPI4_SS0 0x0b0 0x3a0 0x6dc 0x1 0x0 +-#define MX6SL_PAD_EPDC_D2__LCD_DATA26 0x0b0 0x3a0 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_D2__CSI_DATA02 0x0b0 0x3a0 0x638 0x3 0x0 +-#define MX6SL_PAD_EPDC_D2__SPDC_DATA02 0x0b0 0x3a0 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_D2__GPIO1_IO09 0x0b0 0x3a0 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_D3__EPDC_DATA03 0x0b4 0x3a4 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_D3__ECSPI4_SCLK 0x0b4 0x3a4 0x6d0 0x1 0x0 +-#define MX6SL_PAD_EPDC_D3__LCD_DATA27 0x0b4 0x3a4 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_D3__CSI_DATA03 0x0b4 0x3a4 0x63c 0x3 0x0 +-#define MX6SL_PAD_EPDC_D3__SPDC_DATA03 0x0b4 0x3a4 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_D3__GPIO1_IO10 0x0b4 0x3a4 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_D4__EPDC_DATA04 0x0b8 0x3a8 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_D4__ECSPI4_SS1 0x0b8 0x3a8 0x6e0 0x1 0x0 +-#define MX6SL_PAD_EPDC_D4__LCD_DATA28 0x0b8 0x3a8 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_D4__CSI_DATA04 0x0b8 0x3a8 0x640 0x3 0x0 +-#define MX6SL_PAD_EPDC_D4__SPDC_DATA04 0x0b8 0x3a8 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_D4__GPIO1_IO11 0x0b8 0x3a8 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_D5__EPDC_DATA05 0x0bc 0x3ac 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_D5__ECSPI4_SS2 0x0bc 0x3ac 0x6e4 0x1 0x0 +-#define MX6SL_PAD_EPDC_D5__LCD_DATA29 0x0bc 0x3ac 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_D5__CSI_DATA05 0x0bc 0x3ac 0x644 0x3 0x0 +-#define MX6SL_PAD_EPDC_D5__SPDC_DATA05 0x0bc 0x3ac 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_D5__GPIO1_IO12 0x0bc 0x3ac 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_D6__EPDC_DATA06 0x0c0 0x3b0 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_D6__ECSPI4_SS3 0x0c0 0x3b0 0x000 0x1 0x0 +-#define MX6SL_PAD_EPDC_D6__LCD_DATA30 0x0c0 0x3b0 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_D6__CSI_DATA06 0x0c0 0x3b0 0x648 0x3 0x0 +-#define MX6SL_PAD_EPDC_D6__SPDC_DATA06 0x0c0 0x3b0 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_D6__GPIO1_IO13 0x0c0 0x3b0 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_D7__EPDC_DATA07 0x0c4 0x3b4 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_D7__ECSPI4_RDY 0x0c4 0x3b4 0x000 0x1 0x0 +-#define MX6SL_PAD_EPDC_D7__LCD_DATA31 0x0c4 0x3b4 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_D7__CSI_DATA07 0x0c4 0x3b4 0x64c 0x3 0x0 +-#define MX6SL_PAD_EPDC_D7__SPDC_DATA07 0x0c4 0x3b4 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_D7__GPIO1_IO14 0x0c4 0x3b4 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_D8__EPDC_DATA08 0x0c8 0x3b8 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_D8__ECSPI3_MOSI 0x0c8 0x3b8 0x6bc 0x1 0x1 +-#define MX6SL_PAD_EPDC_D8__EPDC_PWR_CTRL0 0x0c8 0x3b8 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_D8__EIM_ADDR16 0x0c8 0x3b8 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_D8__SPDC_DATA08 0x0c8 0x3b8 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_D8__GPIO1_IO15 0x0c8 0x3b8 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_D8__SD4_RESET 0x0c8 0x3b8 0x000 0x6 0x0 +-#define MX6SL_PAD_EPDC_D9__EPDC_DATA09 0x0cc 0x3bc 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_D9__ECSPI3_MISO 0x0cc 0x3bc 0x6b8 0x1 0x1 +-#define MX6SL_PAD_EPDC_D9__EPDC_PWR_CTRL1 0x0cc 0x3bc 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_D9__EIM_ADDR17 0x0cc 0x3bc 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_D9__SPDC_DATA09 0x0cc 0x3bc 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_D9__GPIO1_IO16 0x0cc 0x3bc 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_D9__SD4_VSELECT 0x0cc 0x3bc 0x000 0x6 0x0 +-#define MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x0d0 0x3c0 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x0d0 0x3c0 0x000 0x1 0x0 +-#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKR 0x0d0 0x3c0 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x0d0 0x3c0 0x674 0x3 0x1 +-#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKL 0x0d0 0x3c0 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_GDCLK__GPIO1_IO31 0x0d0 0x3c0 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_GDCLK__SD2_RESET 0x0d0 0x3c0 0x000 0x6 0x0 +-#define MX6SL_PAD_EPDC_GDOE__EPDC_GDOE 0x0d4 0x3c4 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_GDOE__ECSPI2_SS3 0x0d4 0x3c4 0x000 0x1 0x0 +-#define MX6SL_PAD_EPDC_GDOE__SPDC_YOER 0x0d4 0x3c4 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x0d4 0x3c4 0x670 0x3 0x1 +-#define MX6SL_PAD_EPDC_GDOE__SPDC_YOEL 0x0d4 0x3c4 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_GDOE__GPIO2_IO00 0x0d4 0x3c4 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_GDOE__SD2_VSELECT 0x0d4 0x3c4 0x000 0x6 0x0 +-#define MX6SL_PAD_EPDC_GDRL__EPDC_GDRL 0x0d8 0x3c8 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_GDRL__ECSPI2_RDY 0x0d8 0x3c8 0x000 0x1 0x0 +-#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUR 0x0d8 0x3c8 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x0d8 0x3c8 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUL 0x0d8 0x3c8 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_GDRL__GPIO2_IO01 0x0d8 0x3c8 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_GDRL__SD2_WP 0x0d8 0x3c8 0x834 0x6 0x1 +-#define MX6SL_PAD_EPDC_GDSP__EPDC_GDSP 0x0dc 0x3cc 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_GDSP__PWM4_OUT 0x0dc 0x3cc 0x000 0x1 0x0 +-#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODR 0x0dc 0x3cc 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x0dc 0x3cc 0x678 0x3 0x1 +-#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODL 0x0dc 0x3cc 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_GDSP__GPIO2_IO02 0x0dc 0x3cc 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_GDSP__SD2_CD_B 0x0dc 0x3cc 0x830 0x6 0x1 +-#define MX6SL_PAD_EPDC_PWRCOM__EPDC_PWR_COM 0x0e0 0x3d0 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_PWRCOM__SD4_DATA0 0x0e0 0x3d0 0x85c 0x1 0x0 +-#define MX6SL_PAD_EPDC_PWRCOM__LCD_DATA20 0x0e0 0x3d0 0x7c8 0x2 0x0 +-#define MX6SL_PAD_EPDC_PWRCOM__EIM_BCLK 0x0e0 0x3d0 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x0e0 0x3d0 0x5dc 0x4 0x0 +-#define MX6SL_PAD_EPDC_PWRCOM__GPIO2_IO11 0x0e0 0x3d0 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_PWRCOM__SD3_RESET 0x0e0 0x3d0 0x000 0x6 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL0__EPDC_PWR_CTRL0 0x0e4 0x3d4 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL0__AUD5_RXC 0x0e4 0x3d4 0x604 0x1 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL0__LCD_DATA16 0x0e4 0x3d4 0x7b8 0x2 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL0__EIM_RW 0x0e4 0x3d4 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL0__SPDC_YCKL 0x0e4 0x3d4 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x0e4 0x3d4 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL0__SD4_RESET 0x0e4 0x3d4 0x000 0x6 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL1__EPDC_PWR_CTRL1 0x0e8 0x3d8 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL1__AUD5_TXFS 0x0e8 0x3d8 0x610 0x1 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL1__LCD_DATA17 0x0e8 0x3d8 0x7bc 0x2 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL1__EIM_OE_B 0x0e8 0x3d8 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL1__SPDC_YOEL 0x0e8 0x3d8 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08 0x0e8 0x3d8 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL1__SD4_VSELECT 0x0e8 0x3d8 0x000 0x6 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL2__EPDC_PWR_CTRL2 0x0ec 0x3dc 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL2__AUD5_TXD 0x0ec 0x3dc 0x600 0x1 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL2__LCD_DATA18 0x0ec 0x3dc 0x7c0 0x2 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL2__EIM_CS0_B 0x0ec 0x3dc 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL2__SPDC_YDIOUL 0x0ec 0x3dc 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x0ec 0x3dc 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL2__SD4_WP 0x0ec 0x3dc 0x87c 0x6 0x1 +-#define MX6SL_PAD_EPDC_PWRCTRL3__EPDC_PWR_CTRL3 0x0f0 0x3e0 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL3__AUD5_TXC 0x0f0 0x3e0 0x60c 0x1 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL3__LCD_DATA19 0x0f0 0x3e0 0x7c4 0x2 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL3__EIM_CS1_B 0x0f0 0x3e0 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL3__SPDC_YDIODL 0x0f0 0x3e0 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x0f0 0x3e0 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_PWRCTRL3__SD4_CD_B 0x0f0 0x3e0 0x854 0x6 0x1 +-#define MX6SL_PAD_EPDC_PWRINT__EPDC_PWR_IRQ 0x0f4 0x3e4 0x6e8 0x0 0x1 +-#define MX6SL_PAD_EPDC_PWRINT__SD4_DATA1 0x0f4 0x3e4 0x860 0x1 0x0 +-#define MX6SL_PAD_EPDC_PWRINT__LCD_DATA21 0x0f4 0x3e4 0x7cc 0x2 0x0 +-#define MX6SL_PAD_EPDC_PWRINT__EIM_ACLK_FREERUN 0x0f4 0x3e4 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_PWRINT__USB_OTG2_ID 0x0f4 0x3e4 0x5e0 0x4 0x0 +-#define MX6SL_PAD_EPDC_PWRINT__GPIO2_IO12 0x0f4 0x3e4 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_PWRINT__SD3_VSELECT 0x0f4 0x3e4 0x000 0x6 0x0 +-#define MX6SL_PAD_EPDC_PWRSTAT__EPDC_PWR_STAT 0x0f8 0x3e8 0x6ec 0x0 0x1 +-#define MX6SL_PAD_EPDC_PWRSTAT__SD4_DATA2 0x0f8 0x3e8 0x864 0x1 0x0 +-#define MX6SL_PAD_EPDC_PWRSTAT__LCD_DATA22 0x0f8 0x3e8 0x7d0 0x2 0x0 +-#define MX6SL_PAD_EPDC_PWRSTAT__EIM_WAIT_B 0x0f8 0x3e8 0x884 0x3 0x0 +-#define MX6SL_PAD_EPDC_PWRSTAT__ARM_EVENTI 0x0f8 0x3e8 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x0f8 0x3e8 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_PWRSTAT__SD3_WP 0x0f8 0x3e8 0x84c 0x6 0x0 +-#define MX6SL_PAD_EPDC_PWRWAKEUP__EPDC_PWR_WAKE 0x0fc 0x3ec 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_PWRWAKEUP__SD4_DATA3 0x0fc 0x3ec 0x868 0x1 0x0 +-#define MX6SL_PAD_EPDC_PWRWAKEUP__LCD_DATA23 0x0fc 0x3ec 0x7d4 0x2 0x0 +-#define MX6SL_PAD_EPDC_PWRWAKEUP__EIM_DTACK_B 0x0fc 0x3ec 0x880 0x3 0x0 +-#define MX6SL_PAD_EPDC_PWRWAKEUP__ARM_EVENTO 0x0fc 0x3ec 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x0fc 0x3ec 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_PWRWAKEUP__SD3_CD_B 0x0fc 0x3ec 0x838 0x6 0x0 +-#define MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100 0x3f0 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x100 0x3f0 0x6ac 0x1 0x0 +-#define MX6SL_PAD_EPDC_SDCE0__PWM3_OUT 0x100 0x3f0 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_SDCE0__EIM_CS2_B 0x100 0x3f0 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_SDCE0__SPDC_YCKR 0x100 0x3f0 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_SDCE0__GPIO1_IO27 0x100 0x3f0 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x104 0x3f4 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_SDCE1__WDOG2_B 0x104 0x3f4 0x000 0x1 0x0 +-#define MX6SL_PAD_EPDC_SDCE1__PWM4_OUT 0x104 0x3f4 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_SDCE1__EIM_LBA_B 0x104 0x3f4 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_SDCE1__SPDC_YOER 0x104 0x3f4 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_SDCE1__GPIO1_IO28 0x104 0x3f4 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x108 0x3f8 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x108 0x3f8 0x72c 0x1 0x1 +-#define MX6SL_PAD_EPDC_SDCE2__PWM1_OUT 0x108 0x3f8 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_SDCE2__EIM_EB0_B 0x108 0x3f8 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_SDCE2__SPDC_YDIOUR 0x108 0x3f8 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_SDCE2__GPIO1_IO29 0x108 0x3f8 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x10c 0x3fc 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x10c 0x3fc 0x730 0x1 0x1 +-#define MX6SL_PAD_EPDC_SDCE3__PWM2_OUT 0x10c 0x3fc 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_SDCE3__EIM_EB1_B 0x10c 0x3fc 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_SDCE3__SPDC_YDIODR 0x10c 0x3fc 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_SDCE3__GPIO1_IO30 0x10c 0x3fc 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x110 0x400 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x110 0x400 0x6a4 0x1 0x1 +-#define MX6SL_PAD_EPDC_SDCLK__I2C2_SCL 0x110 0x400 0x724 0x2 0x0 +-#define MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110 0x400 0x650 0x3 0x0 +-#define MX6SL_PAD_EPDC_SDCLK__SPDC_CL 0x110 0x400 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_SDCLK__GPIO1_IO23 0x110 0x400 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_SDLE__EPDC_SDLE 0x114 0x404 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_SDLE__ECSPI2_MISO 0x114 0x404 0x6a0 0x1 0x1 +-#define MX6SL_PAD_EPDC_SDLE__I2C2_SDA 0x114 0x404 0x728 0x2 0x0 +-#define MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x114 0x404 0x654 0x3 0x0 +-#define MX6SL_PAD_EPDC_SDLE__SPDC_LD 0x114 0x404 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_SDLE__GPIO1_IO24 0x114 0x404 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_SDOE__EPDC_SDOE 0x118 0x408 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_SDOE__ECSPI2_SS0 0x118 0x408 0x6a8 0x1 0x1 +-#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOR 0x118 0x408 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_SDOE__CSI_DATA10 0x118 0x408 0x658 0x3 0x0 +-#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOL 0x118 0x408 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x118 0x408 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x11c 0x40c 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x11c 0x40c 0x69c 0x1 0x1 +-#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x11c 0x40c 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_SDSHR__CSI_DATA11 0x11c 0x40c 0x65c 0x3 0x0 +-#define MX6SL_PAD_EPDC_SDSHR__SPDC_XDIOR 0x11c 0x40c 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x11c 0x40c 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x120 0x410 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_VCOM0__AUD5_RXFS 0x120 0x410 0x608 0x1 0x0 +-#define MX6SL_PAD_EPDC_VCOM0__UART3_RX_DATA 0x120 0x410 0x80c 0x2 0x4 +-#define MX6SL_PAD_EPDC_VCOM0__UART3_TX_DATA 0x120 0x410 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_VCOM0__EIM_ADDR24 0x120 0x410 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_VCOM0__SPDC_VCOM0 0x120 0x410 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x120 0x410 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x120 0x410 0x000 0x6 0x0 +-#define MX6SL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x124 0x414 0x000 0x0 0x0 +-#define MX6SL_PAD_EPDC_VCOM1__AUD5_RXD 0x124 0x414 0x5fc 0x1 0x0 +-#define MX6SL_PAD_EPDC_VCOM1__UART3_TX_DATA 0x124 0x414 0x000 0x2 0x0 +-#define MX6SL_PAD_EPDC_VCOM1__UART3_RX_DATA 0x124 0x414 0x80c 0x2 0x5 +-#define MX6SL_PAD_EPDC_VCOM1__EIM_ADDR25 0x124 0x414 0x000 0x3 0x0 +-#define MX6SL_PAD_EPDC_VCOM1__SPDC_VCOM1 0x124 0x414 0x000 0x4 0x0 +-#define MX6SL_PAD_EPDC_VCOM1__GPIO2_IO04 0x124 0x414 0x000 0x5 0x0 +-#define MX6SL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x124 0x414 0x000 0x6 0x0 +-#define MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x128 0x418 0x704 0x0 0x1 +-#define MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x128 0x418 0x860 0x1 0x1 +-#define MX6SL_PAD_FEC_CRS_DV__AUD6_TXC 0x128 0x418 0x624 0x2 0x0 +-#define MX6SL_PAD_FEC_CRS_DV__ECSPI4_MISO 0x128 0x418 0x6d4 0x3 0x1 +-#define MX6SL_PAD_FEC_CRS_DV__GPT_COMPARE2 0x128 0x418 0x000 0x4 0x0 +-#define MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x128 0x418 0x000 0x5 0x0 +-#define MX6SL_PAD_FEC_CRS_DV__ARM_TRACE31 0x128 0x418 0x000 0x6 0x0 +-#define MX6SL_PAD_FEC_MDC__FEC_MDC 0x12c 0x41c 0x000 0x0 0x0 +-#define MX6SL_PAD_FEC_MDC__SD4_DATA4 0x12c 0x41c 0x86c 0x1 0x0 +-#define MX6SL_PAD_FEC_MDC__AUDIO_CLK_OUT 0x12c 0x41c 0x000 0x2 0x0 +-#define MX6SL_PAD_FEC_MDC__SD1_RESET 0x12c 0x41c 0x000 0x3 0x0 +-#define MX6SL_PAD_FEC_MDC__SD3_RESET 0x12c 0x41c 0x000 0x4 0x0 +-#define MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x12c 0x41c 0x000 0x5 0x0 +-#define MX6SL_PAD_FEC_MDC__ARM_TRACE29 0x12c 0x41c 0x000 0x6 0x0 +-#define MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x130 0x420 0x6f4 0x0 0x1 +-#define MX6SL_PAD_FEC_MDIO__SD4_CLK 0x130 0x420 0x850 0x1 0x1 +-#define MX6SL_PAD_FEC_MDIO__AUD6_RXFS 0x130 0x420 0x620 0x2 0x0 +-#define MX6SL_PAD_FEC_MDIO__ECSPI4_SS0 0x130 0x420 0x6dc 0x3 0x1 +-#define MX6SL_PAD_FEC_MDIO__GPT_CAPTURE1 0x130 0x420 0x710 0x4 0x0 +-#define MX6SL_PAD_FEC_MDIO__GPIO4_IO20 0x130 0x420 0x000 0x5 0x0 +-#define MX6SL_PAD_FEC_MDIO__ARM_TRACE26 0x130 0x420 0x000 0x6 0x0 +-#define MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x134 0x424 0x000 0x0 0x0 +-#define MX6SL_PAD_FEC_REF_CLK__SD4_RESET 0x134 0x424 0x000 0x1 0x0 +-#define MX6SL_PAD_FEC_REF_CLK__WDOG1_B 0x134 0x424 0x000 0x2 0x0 +-#define MX6SL_PAD_FEC_REF_CLK__PWM4_OUT 0x134 0x424 0x000 0x3 0x0 +-#define MX6SL_PAD_FEC_REF_CLK__CCM_PMIC_READY 0x134 0x424 0x62c 0x4 0x0 +-#define MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x134 0x424 0x000 0x5 0x0 +-#define MX6SL_PAD_FEC_REF_CLK__SPDIF_EXT_CLK 0x134 0x424 0x7f4 0x6 0x2 +-#define MX6SL_PAD_FEC_RX_ER__FEC_RX_ER 0x138 0x428 0x708 0x0 0x1 +-#define MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x138 0x428 0x85c 0x1 0x1 +-#define MX6SL_PAD_FEC_RX_ER__AUD6_RXD 0x138 0x428 0x614 0x2 0x0 +-#define MX6SL_PAD_FEC_RX_ER__ECSPI4_MOSI 0x138 0x428 0x6d8 0x3 0x1 +-#define MX6SL_PAD_FEC_RX_ER__GPT_COMPARE1 0x138 0x428 0x000 0x4 0x0 +-#define MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x138 0x428 0x000 0x5 0x0 +-#define MX6SL_PAD_FEC_RX_ER__ARM_TRACE25 0x138 0x428 0x000 0x6 0x0 +-#define MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x13c 0x42c 0x6f8 0x0 0x0 +-#define MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x13c 0x42c 0x870 0x1 0x0 +-#define MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x13c 0x42c 0x5dc 0x2 0x1 +-#define MX6SL_PAD_FEC_RXD0__SD1_VSELECT 0x13c 0x42c 0x000 0x3 0x0 +-#define MX6SL_PAD_FEC_RXD0__SD3_VSELECT 0x13c 0x42c 0x000 0x4 0x0 +-#define MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x13c 0x42c 0x000 0x5 0x0 +-#define MX6SL_PAD_FEC_RXD0__ARM_TRACE24 0x13c 0x42c 0x000 0x6 0x0 +-#define MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x140 0x430 0x6fc 0x0 0x1 +-#define MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x140 0x430 0x864 0x1 0x1 +-#define MX6SL_PAD_FEC_RXD1__AUD6_TXFS 0x140 0x430 0x628 0x2 0x0 +-#define MX6SL_PAD_FEC_RXD1__ECSPI4_SS1 0x140 0x430 0x6e0 0x3 0x1 +-#define MX6SL_PAD_FEC_RXD1__GPT_COMPARE3 0x140 0x430 0x000 0x4 0x0 +-#define MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x140 0x430 0x000 0x5 0x0 +-#define MX6SL_PAD_FEC_RXD1__FEC_COL 0x140 0x430 0x6f0 0x6 0x0 +-#define MX6SL_PAD_FEC_TX_CLK__FEC_TX_CLK 0x144 0x434 0x70c 0x0 0x1 +-#define MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x144 0x434 0x858 0x1 0x1 +-#define MX6SL_PAD_FEC_TX_CLK__AUD6_RXC 0x144 0x434 0x61c 0x2 0x0 +-#define MX6SL_PAD_FEC_TX_CLK__ECSPI4_SCLK 0x144 0x434 0x6d0 0x3 0x1 +-#define MX6SL_PAD_FEC_TX_CLK__GPT_CAPTURE2 0x144 0x434 0x714 0x4 0x0 +-#define MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x144 0x434 0x000 0x5 0x0 +-#define MX6SL_PAD_FEC_TX_CLK__ARM_TRACE27 0x144 0x434 0x000 0x6 0x0 +-#define MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x148 0x438 0x000 0x0 0x0 +-#define MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x148 0x438 0x874 0x1 0x0 +-#define MX6SL_PAD_FEC_TX_EN__SPDIF_IN 0x148 0x438 0x7f0 0x2 0x0 +-#define MX6SL_PAD_FEC_TX_EN__SD1_WP 0x148 0x438 0x82c 0x3 0x1 +-#define MX6SL_PAD_FEC_TX_EN__SD3_WP 0x148 0x438 0x84c 0x4 0x1 +-#define MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x148 0x438 0x000 0x5 0x0 +-#define MX6SL_PAD_FEC_TX_EN__ARM_TRACE28 0x148 0x438 0x000 0x6 0x0 +-#define MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x14c 0x43c 0x000 0x0 0x0 +-#define MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x14c 0x43c 0x868 0x1 0x1 +-#define MX6SL_PAD_FEC_TXD0__AUD6_TXD 0x14c 0x43c 0x618 0x2 0x0 +-#define MX6SL_PAD_FEC_TXD0__ECSPI4_SS2 0x14c 0x43c 0x6e4 0x3 0x1 +-#define MX6SL_PAD_FEC_TXD0__GPT_CLKIN 0x14c 0x43c 0x718 0x4 0x0 +-#define MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x14c 0x43c 0x000 0x5 0x0 +-#define MX6SL_PAD_FEC_TXD0__ARM_TRACE30 0x14c 0x43c 0x000 0x6 0x0 +-#define MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x150 0x440 0x000 0x0 0x0 +-#define MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x150 0x440 0x878 0x1 0x0 +-#define MX6SL_PAD_FEC_TXD1__SPDIF_OUT 0x150 0x440 0x000 0x2 0x0 +-#define MX6SL_PAD_FEC_TXD1__SD1_CD_B 0x150 0x440 0x828 0x3 0x1 +-#define MX6SL_PAD_FEC_TXD1__SD3_CD_B 0x150 0x440 0x838 0x4 0x1 +-#define MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x150 0x440 0x000 0x5 0x0 +-#define MX6SL_PAD_FEC_TXD1__FEC_RX_CLK 0x150 0x440 0x700 0x6 0x0 +-#define MX6SL_PAD_HSIC_DAT__USB_H_DATA 0x154 0x444 0x000 0x0 0x0 +-#define MX6SL_PAD_HSIC_DAT__I2C1_SCL 0x154 0x444 0x71c 0x1 0x1 +-#define MX6SL_PAD_HSIC_DAT__PWM1_OUT 0x154 0x444 0x000 0x2 0x0 +-#define MX6SL_PAD_HSIC_DAT__XTALOSC_REF_CLK_24M 0x154 0x444 0x000 0x3 0x0 +-#define MX6SL_PAD_HSIC_DAT__GPIO3_IO19 0x154 0x444 0x000 0x5 0x0 +-#define MX6SL_PAD_HSIC_STROBE__USB_H_STROBE 0x158 0x448 0x000 0x0 0x0 +-#define MX6SL_PAD_HSIC_STROBE__I2C1_SDA 0x158 0x448 0x720 0x1 0x1 +-#define MX6SL_PAD_HSIC_STROBE__PWM2_OUT 0x158 0x448 0x000 0x2 0x0 +-#define MX6SL_PAD_HSIC_STROBE__XTALOSC_REF_CLK_32K 0x158 0x448 0x000 0x3 0x0 +-#define MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x158 0x448 0x000 0x5 0x0 +-#define MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x15c 0x44c 0x71c 0x0 0x2 +-#define MX6SL_PAD_I2C1_SCL__UART1_RTS_B 0x15c 0x44c 0x7f8 0x1 0x0 +-#define MX6SL_PAD_I2C1_SCL__UART1_CTS_B 0x15c 0x44c 0x000 0x1 0x0 +-#define MX6SL_PAD_I2C1_SCL__ECSPI3_SS2 0x15c 0x44c 0x6c8 0x2 0x1 +-#define MX6SL_PAD_I2C1_SCL__FEC_RX_DATA0 0x15c 0x44c 0x6f8 0x3 0x1 +-#define MX6SL_PAD_I2C1_SCL__SD3_RESET 0x15c 0x44c 0x000 0x4 0x0 +-#define MX6SL_PAD_I2C1_SCL__GPIO3_IO12 0x15c 0x44c 0x000 0x5 0x0 +-#define MX6SL_PAD_I2C1_SCL__ECSPI1_SS1 0x15c 0x44c 0x690 0x6 0x0 +-#define MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x160 0x450 0x720 0x0 0x2 +-#define MX6SL_PAD_I2C1_SDA__UART1_CTS_B 0x160 0x450 0x000 0x1 0x0 +-#define MX6SL_PAD_I2C1_SDA__UART1_RTS_B 0x160 0x450 0x7f8 0x1 0x1 +-#define MX6SL_PAD_I2C1_SDA__ECSPI3_SS3 0x160 0x450 0x6cc 0x2 0x1 +-#define MX6SL_PAD_I2C1_SDA__FEC_TX_EN 0x160 0x450 0x000 0x3 0x0 +-#define MX6SL_PAD_I2C1_SDA__SD3_VSELECT 0x160 0x450 0x000 0x4 0x0 +-#define MX6SL_PAD_I2C1_SDA__GPIO3_IO13 0x160 0x450 0x000 0x5 0x0 +-#define MX6SL_PAD_I2C1_SDA__ECSPI1_SS2 0x160 0x450 0x694 0x6 0x0 +-#define MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x164 0x454 0x724 0x0 0x1 +-#define MX6SL_PAD_I2C2_SCL__AUD4_RXFS 0x164 0x454 0x5f0 0x1 0x0 +-#define MX6SL_PAD_I2C2_SCL__SPDIF_IN 0x164 0x454 0x7f0 0x2 0x1 +-#define MX6SL_PAD_I2C2_SCL__FEC_TX_DATA1 0x164 0x454 0x000 0x3 0x0 +-#define MX6SL_PAD_I2C2_SCL__SD3_WP 0x164 0x454 0x84c 0x4 0x2 +-#define MX6SL_PAD_I2C2_SCL__GPIO3_IO14 0x164 0x454 0x000 0x5 0x0 +-#define MX6SL_PAD_I2C2_SCL__ECSPI1_RDY 0x164 0x454 0x680 0x6 0x0 +-#define MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x168 0x458 0x728 0x0 0x1 +-#define MX6SL_PAD_I2C2_SDA__AUD4_RXC 0x168 0x458 0x5ec 0x1 0x0 +-#define MX6SL_PAD_I2C2_SDA__SPDIF_OUT 0x168 0x458 0x000 0x2 0x0 +-#define MX6SL_PAD_I2C2_SDA__FEC_REF_OUT 0x168 0x458 0x000 0x3 0x0 +-#define MX6SL_PAD_I2C2_SDA__SD3_CD_B 0x168 0x458 0x838 0x4 0x2 +-#define MX6SL_PAD_I2C2_SDA__GPIO3_IO15 0x168 0x458 0x000 0x5 0x0 +-#define MX6SL_PAD_KEY_COL0__KEY_COL0 0x16c 0x474 0x734 0x0 0x0 +-#define MX6SL_PAD_KEY_COL0__I2C2_SCL 0x16c 0x474 0x724 0x1 0x2 +-#define MX6SL_PAD_KEY_COL0__LCD_DATA00 0x16c 0x474 0x778 0x2 0x0 +-#define MX6SL_PAD_KEY_COL0__EIM_AD00 0x16c 0x474 0x000 0x3 0x0 +-#define MX6SL_PAD_KEY_COL0__SD1_CD_B 0x16c 0x474 0x828 0x4 0x2 +-#define MX6SL_PAD_KEY_COL0__GPIO3_IO24 0x16c 0x474 0x000 0x5 0x0 +-#define MX6SL_PAD_KEY_COL1__KEY_COL1 0x170 0x478 0x738 0x0 0x0 +-#define MX6SL_PAD_KEY_COL1__ECSPI4_MOSI 0x170 0x478 0x6d8 0x1 0x2 +-#define MX6SL_PAD_KEY_COL1__LCD_DATA02 0x170 0x478 0x780 0x2 0x0 +-#define MX6SL_PAD_KEY_COL1__EIM_AD02 0x170 0x478 0x000 0x3 0x0 +-#define MX6SL_PAD_KEY_COL1__SD3_DATA4 0x170 0x478 0x83c 0x4 0x0 +-#define MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x170 0x478 0x000 0x5 0x0 +-#define MX6SL_PAD_KEY_COL2__KEY_COL2 0x174 0x47c 0x73c 0x0 0x0 +-#define MX6SL_PAD_KEY_COL2__ECSPI4_SS0 0x174 0x47c 0x6dc 0x1 0x2 +-#define MX6SL_PAD_KEY_COL2__LCD_DATA04 0x174 0x47c 0x788 0x2 0x0 +-#define MX6SL_PAD_KEY_COL2__EIM_AD04 0x174 0x47c 0x000 0x3 0x0 +-#define MX6SL_PAD_KEY_COL2__SD3_DATA6 0x174 0x47c 0x844 0x4 0x0 +-#define MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x174 0x47c 0x000 0x5 0x0 +-#define MX6SL_PAD_KEY_COL3__KEY_COL3 0x178 0x480 0x740 0x0 0x0 +-#define MX6SL_PAD_KEY_COL3__AUD6_RXFS 0x178 0x480 0x620 0x1 0x1 +-#define MX6SL_PAD_KEY_COL3__LCD_DATA06 0x178 0x480 0x790 0x2 0x0 +-#define MX6SL_PAD_KEY_COL3__EIM_AD06 0x178 0x480 0x000 0x3 0x0 +-#define MX6SL_PAD_KEY_COL3__SD4_DATA6 0x178 0x480 0x874 0x4 0x1 +-#define MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x178 0x480 0x000 0x5 0x0 +-#define MX6SL_PAD_KEY_COL3__SD1_RESET 0x178 0x480 0x000 0x6 0x0 +-#define MX6SL_PAD_KEY_COL4__KEY_COL4 0x17c 0x484 0x744 0x0 0x0 +-#define MX6SL_PAD_KEY_COL4__AUD6_RXD 0x17c 0x484 0x614 0x1 0x1 +-#define MX6SL_PAD_KEY_COL4__LCD_DATA08 0x17c 0x484 0x798 0x2 0x0 +-#define MX6SL_PAD_KEY_COL4__EIM_AD08 0x17c 0x484 0x000 0x3 0x0 +-#define MX6SL_PAD_KEY_COL4__SD4_CLK 0x17c 0x484 0x850 0x4 0x2 +-#define MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x17c 0x484 0x000 0x5 0x0 +-#define MX6SL_PAD_KEY_COL4__USB_OTG1_PWR 0x17c 0x484 0x000 0x6 0x0 +-#define MX6SL_PAD_KEY_COL5__KEY_COL5 0x180 0x488 0x748 0x0 0x0 +-#define MX6SL_PAD_KEY_COL5__AUD6_TXFS 0x180 0x488 0x628 0x1 0x1 +-#define MX6SL_PAD_KEY_COL5__LCD_DATA10 0x180 0x488 0x7a0 0x2 0x0 +-#define MX6SL_PAD_KEY_COL5__EIM_AD10 0x180 0x488 0x000 0x3 0x0 +-#define MX6SL_PAD_KEY_COL5__SD4_DATA0 0x180 0x488 0x85c 0x4 0x2 +-#define MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x180 0x488 0x000 0x5 0x0 +-#define MX6SL_PAD_KEY_COL5__USB_OTG2_PWR 0x180 0x488 0x000 0x6 0x0 +-#define MX6SL_PAD_KEY_COL6__KEY_COL6 0x184 0x48c 0x74c 0x0 0x0 +-#define MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x184 0x48c 0x814 0x1 0x2 +-#define MX6SL_PAD_KEY_COL6__UART4_TX_DATA 0x184 0x48c 0x000 0x1 0x0 +-#define MX6SL_PAD_KEY_COL6__LCD_DATA12 0x184 0x48c 0x7a8 0x2 0x0 +-#define MX6SL_PAD_KEY_COL6__EIM_AD12 0x184 0x48c 0x000 0x3 0x0 +-#define MX6SL_PAD_KEY_COL6__SD4_DATA2 0x184 0x48c 0x864 0x4 0x2 +-#define MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x184 0x48c 0x000 0x5 0x0 +-#define MX6SL_PAD_KEY_COL6__SD3_RESET 0x184 0x48c 0x000 0x6 0x0 +-#define MX6SL_PAD_KEY_COL7__KEY_COL7 0x188 0x490 0x750 0x0 0x0 +-#define MX6SL_PAD_KEY_COL7__UART4_RTS_B 0x188 0x490 0x810 0x1 0x2 +-#define MX6SL_PAD_KEY_COL7__UART4_CTS_B 0x188 0x490 0x000 0x1 0x0 +-#define MX6SL_PAD_KEY_COL7__LCD_DATA14 0x188 0x490 0x7b0 0x2 0x0 +-#define MX6SL_PAD_KEY_COL7__EIM_AD14 0x188 0x490 0x000 0x3 0x0 +-#define MX6SL_PAD_KEY_COL7__SD4_DATA4 0x188 0x490 0x86c 0x4 0x1 +-#define MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x188 0x490 0x000 0x5 0x0 +-#define MX6SL_PAD_KEY_COL7__SD1_WP 0x188 0x490 0x82c 0x6 0x2 +-#define MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x18c 0x494 0x754 0x0 0x0 +-#define MX6SL_PAD_KEY_ROW0__I2C2_SDA 0x18c 0x494 0x728 0x1 0x2 +-#define MX6SL_PAD_KEY_ROW0__LCD_DATA01 0x18c 0x494 0x77c 0x2 0x0 +-#define MX6SL_PAD_KEY_ROW0__EIM_AD01 0x18c 0x494 0x000 0x3 0x0 +-#define MX6SL_PAD_KEY_ROW0__SD1_WP 0x18c 0x494 0x82c 0x4 0x3 +-#define MX6SL_PAD_KEY_ROW0__GPIO3_IO25 0x18c 0x494 0x000 0x5 0x0 +-#define MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x190 0x498 0x758 0x0 0x0 +-#define MX6SL_PAD_KEY_ROW1__ECSPI4_MISO 0x190 0x498 0x6d4 0x1 0x2 +-#define MX6SL_PAD_KEY_ROW1__LCD_DATA03 0x190 0x498 0x784 0x2 0x0 +-#define MX6SL_PAD_KEY_ROW1__EIM_AD03 0x190 0x498 0x000 0x3 0x0 +-#define MX6SL_PAD_KEY_ROW1__SD3_DATA5 0x190 0x498 0x840 0x4 0x0 +-#define MX6SL_PAD_KEY_ROW1__GPIO3_IO27 0x190 0x498 0x000 0x5 0x0 +-#define MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x194 0x49c 0x75c 0x0 0x0 +-#define MX6SL_PAD_KEY_ROW2__ECSPI4_SCLK 0x194 0x49c 0x6d0 0x1 0x2 +-#define MX6SL_PAD_KEY_ROW2__LCD_DATA05 0x194 0x49c 0x78c 0x2 0x0 +-#define MX6SL_PAD_KEY_ROW2__EIM_AD05 0x194 0x49c 0x000 0x3 0x0 +-#define MX6SL_PAD_KEY_ROW2__SD3_DATA7 0x194 0x49c 0x848 0x4 0x0 +-#define MX6SL_PAD_KEY_ROW2__GPIO3_IO29 0x194 0x49c 0x000 0x5 0x0 +-#define MX6SL_PAD_KEY_ROW3__KEY_ROW3 0x198 0x4a0 0x760 0x0 0x0 +-#define MX6SL_PAD_KEY_ROW3__AUD6_RXC 0x198 0x4a0 0x61c 0x1 0x1 +-#define MX6SL_PAD_KEY_ROW3__LCD_DATA07 0x198 0x4a0 0x794 0x2 0x0 +-#define MX6SL_PAD_KEY_ROW3__EIM_AD07 0x198 0x4a0 0x000 0x3 0x0 +-#define MX6SL_PAD_KEY_ROW3__SD4_DATA7 0x198 0x4a0 0x878 0x4 0x1 +-#define MX6SL_PAD_KEY_ROW3__GPIO3_IO31 0x198 0x4a0 0x000 0x5 0x0 +-#define MX6SL_PAD_KEY_ROW3__SD1_VSELECT 0x198 0x4a0 0x000 0x6 0x0 +-#define MX6SL_PAD_KEY_ROW4__KEY_ROW4 0x19c 0x4a4 0x764 0x0 0x0 +-#define MX6SL_PAD_KEY_ROW4__AUD6_TXC 0x19c 0x4a4 0x624 0x1 0x1 +-#define MX6SL_PAD_KEY_ROW4__LCD_DATA09 0x19c 0x4a4 0x79c 0x2 0x0 +-#define MX6SL_PAD_KEY_ROW4__EIM_AD09 0x19c 0x4a4 0x000 0x3 0x0 +-#define MX6SL_PAD_KEY_ROW4__SD4_CMD 0x19c 0x4a4 0x858 0x4 0x2 +-#define MX6SL_PAD_KEY_ROW4__GPIO4_IO01 0x19c 0x4a4 0x000 0x5 0x0 +-#define MX6SL_PAD_KEY_ROW4__USB_OTG1_OC 0x19c 0x4a4 0x824 0x6 0x1 +-#define MX6SL_PAD_KEY_ROW5__KEY_ROW5 0x1a0 0x4a8 0x768 0x0 0x0 +-#define MX6SL_PAD_KEY_ROW5__AUD6_TXD 0x1a0 0x4a8 0x618 0x1 0x1 +-#define MX6SL_PAD_KEY_ROW5__LCD_DATA11 0x1a0 0x4a8 0x7a4 0x2 0x0 +-#define MX6SL_PAD_KEY_ROW5__EIM_AD11 0x1a0 0x4a8 0x000 0x3 0x0 +-#define MX6SL_PAD_KEY_ROW5__SD4_DATA1 0x1a0 0x4a8 0x860 0x4 0x2 +-#define MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x1a0 0x4a8 0x000 0x5 0x0 +-#define MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x1a0 0x4a8 0x820 0x6 0x2 +-#define MX6SL_PAD_KEY_ROW6__KEY_ROW6 0x1a4 0x4ac 0x76c 0x0 0x0 +-#define MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1a4 0x4ac 0x000 0x1 0x0 +-#define MX6SL_PAD_KEY_ROW6__UART4_RX_DATA 0x1a4 0x4ac 0x814 0x1 0x3 +-#define MX6SL_PAD_KEY_ROW6__LCD_DATA13 0x1a4 0x4ac 0x7ac 0x2 0x0 +-#define MX6SL_PAD_KEY_ROW6__EIM_AD13 0x1a4 0x4ac 0x000 0x3 0x0 +-#define MX6SL_PAD_KEY_ROW6__SD4_DATA3 0x1a4 0x4ac 0x868 0x4 0x2 +-#define MX6SL_PAD_KEY_ROW6__GPIO4_IO05 0x1a4 0x4ac 0x000 0x5 0x0 +-#define MX6SL_PAD_KEY_ROW6__SD3_VSELECT 0x1a4 0x4ac 0x000 0x6 0x0 +-#define MX6SL_PAD_KEY_ROW7__KEY_ROW7 0x1a8 0x4b0 0x770 0x0 0x0 +-#define MX6SL_PAD_KEY_ROW7__UART4_CTS_B 0x1a8 0x4b0 0x000 0x1 0x0 +-#define MX6SL_PAD_KEY_ROW7__UART4_RTS_B 0x1a8 0x4b0 0x810 0x1 0x3 +-#define MX6SL_PAD_KEY_ROW7__LCD_DATA15 0x1a8 0x4b0 0x7b4 0x2 0x0 +-#define MX6SL_PAD_KEY_ROW7__EIM_AD15 0x1a8 0x4b0 0x000 0x3 0x0 +-#define MX6SL_PAD_KEY_ROW7__SD4_DATA5 0x1a8 0x4b0 0x870 0x4 0x1 +-#define MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x1a8 0x4b0 0x000 0x5 0x0 +-#define MX6SL_PAD_KEY_ROW7__SD1_CD_B 0x1a8 0x4b0 0x828 0x6 0x3 +-#define MX6SL_PAD_LCD_CLK__LCD_CLK 0x1ac 0x4b4 0x000 0x0 0x0 +-#define MX6SL_PAD_LCD_CLK__SD4_DATA4 0x1ac 0x4b4 0x86c 0x1 0x2 +-#define MX6SL_PAD_LCD_CLK__LCD_WR_RWN 0x1ac 0x4b4 0x000 0x2 0x0 +-#define MX6SL_PAD_LCD_CLK__EIM_RW 0x1ac 0x4b4 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_CLK__PWM4_OUT 0x1ac 0x4b4 0x000 0x4 0x0 +-#define MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x1ac 0x4b4 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0 0x4b8 0x778 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT0__ECSPI1_MOSI 0x1b0 0x4b8 0x688 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT0__USB_OTG2_ID 0x1b0 0x4b8 0x5e0 0x2 0x1 +-#define MX6SL_PAD_LCD_DAT0__PWM1_OUT 0x1b0 0x4b8 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT0__UART5_DTR_B 0x1b0 0x4b8 0x000 0x4 0x0 +-#define MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x1b0 0x4b8 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT0__ARM_TRACE00 0x1b0 0x4b8 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT0__SRC_BOOT_CFG00 0x1b0 0x4b8 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b4 0x4bc 0x77c 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT1__ECSPI1_MISO 0x1b4 0x4bc 0x684 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x1b4 0x4bc 0x5dc 0x2 0x2 +-#define MX6SL_PAD_LCD_DAT1__PWM2_OUT 0x1b4 0x4bc 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT1__AUD4_RXFS 0x1b4 0x4bc 0x5f0 0x4 0x1 +-#define MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x1b4 0x4bc 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT1__ARM_TRACE01 0x1b4 0x4bc 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT1__SRC_BOOT_CFG01 0x1b4 0x4bc 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b8 0x4c0 0x7a0 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT10__KEY_COL1 0x1b8 0x4c0 0x738 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT10__CSI_DATA07 0x1b8 0x4c0 0x64c 0x2 0x1 +-#define MX6SL_PAD_LCD_DAT10__EIM_DATA04 0x1b8 0x4c0 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT10__ECSPI2_MISO 0x1b8 0x4c0 0x6a0 0x4 0x2 +-#define MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x1b8 0x4c0 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT10__ARM_TRACE10 0x1b8 0x4c0 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT10__SRC_BOOT_CFG10 0x1b8 0x4c0 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1bc 0x4c4 0x7a4 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT11__KEY_ROW1 0x1bc 0x4c4 0x758 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT11__CSI_DATA06 0x1bc 0x4c4 0x648 0x2 0x1 +-#define MX6SL_PAD_LCD_DAT11__EIM_DATA05 0x1bc 0x4c4 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT11__ECSPI2_SS1 0x1bc 0x4c4 0x6ac 0x4 0x1 +-#define MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x1bc 0x4c4 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT11__ARM_TRACE11 0x1bc 0x4c4 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT11__SRC_BOOT_CFG11 0x1bc 0x4c4 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1c0 0x4c8 0x7a8 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT12__KEY_COL2 0x1c0 0x4c8 0x73c 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT12__CSI_DATA05 0x1c0 0x4c8 0x644 0x2 0x1 +-#define MX6SL_PAD_LCD_DAT12__EIM_DATA06 0x1c0 0x4c8 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT12__UART5_RTS_B 0x1c0 0x4c8 0x818 0x4 0x2 +-#define MX6SL_PAD_LCD_DAT12__UART5_CTS_B 0x1c0 0x4c8 0x000 0x4 0x0 +-#define MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x1c0 0x4c8 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT12__ARM_TRACE12 0x1c0 0x4c8 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT12__SRC_BOOT_CFG12 0x1c0 0x4c8 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1c4 0x4cc 0x7ac 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT13__KEY_ROW2 0x1c4 0x4cc 0x75c 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT13__CSI_DATA04 0x1c4 0x4cc 0x640 0x2 0x1 +-#define MX6SL_PAD_LCD_DAT13__EIM_DATA07 0x1c4 0x4cc 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT13__UART5_CTS_B 0x1c4 0x4cc 0x000 0x4 0x0 +-#define MX6SL_PAD_LCD_DAT13__UART5_RTS_B 0x1c4 0x4cc 0x818 0x4 0x3 +-#define MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x1c4 0x4cc 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT13__ARM_TRACE13 0x1c4 0x4cc 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT13__SRC_BOOT_CFG13 0x1c4 0x4cc 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1c8 0x4d0 0x7b0 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT14__KEY_COL3 0x1c8 0x4d0 0x740 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT14__CSI_DATA03 0x1c8 0x4d0 0x63c 0x2 0x1 +-#define MX6SL_PAD_LCD_DAT14__EIM_DATA08 0x1c8 0x4d0 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT14__UART5_RX_DATA 0x1c8 0x4d0 0x81c 0x4 0x2 +-#define MX6SL_PAD_LCD_DAT14__UART5_TX_DATA 0x1c8 0x4d0 0x000 0x4 0x0 +-#define MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x1c8 0x4d0 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT14__ARM_TRACE14 0x1c8 0x4d0 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT14__SRC_BOOT_CFG14 0x1c8 0x4d0 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1cc 0x4d4 0x7b4 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT15__KEY_ROW3 0x1cc 0x4d4 0x760 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT15__CSI_DATA02 0x1cc 0x4d4 0x638 0x2 0x1 +-#define MX6SL_PAD_LCD_DAT15__EIM_DATA09 0x1cc 0x4d4 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT15__UART5_TX_DATA 0x1cc 0x4d4 0x000 0x4 0x0 +-#define MX6SL_PAD_LCD_DAT15__UART5_RX_DATA 0x1cc 0x4d4 0x81c 0x4 0x3 +-#define MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x1cc 0x4d4 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT15__ARM_TRACE15 0x1cc 0x4d4 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT15__SRC_BOOT_CFG15 0x1cc 0x4d4 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1d0 0x4d8 0x7b8 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT16__KEY_COL4 0x1d0 0x4d8 0x744 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT16__CSI_DATA01 0x1d0 0x4d8 0x634 0x2 0x1 +-#define MX6SL_PAD_LCD_DAT16__EIM_DATA10 0x1d0 0x4d8 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT16__I2C2_SCL 0x1d0 0x4d8 0x724 0x4 0x3 +-#define MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x1d0 0x4d8 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT16__ARM_TRACE16 0x1d0 0x4d8 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT16__SRC_BOOT_CFG24 0x1d0 0x4d8 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1d4 0x4dc 0x7bc 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT17__KEY_ROW4 0x1d4 0x4dc 0x764 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT17__CSI_DATA00 0x1d4 0x4dc 0x630 0x2 0x1 +-#define MX6SL_PAD_LCD_DAT17__EIM_DATA11 0x1d4 0x4dc 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT17__I2C2_SDA 0x1d4 0x4dc 0x728 0x4 0x3 +-#define MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x1d4 0x4dc 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT17__ARM_TRACE17 0x1d4 0x4dc 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT17__SRC_BOOT_CFG25 0x1d4 0x4dc 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1d8 0x4e0 0x7c0 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT18__KEY_COL5 0x1d8 0x4e0 0x748 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT18__CSI_DATA15 0x1d8 0x4e0 0x66c 0x2 0x0 +-#define MX6SL_PAD_LCD_DAT18__EIM_DATA12 0x1d8 0x4e0 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT18__GPT_CAPTURE1 0x1d8 0x4e0 0x710 0x4 0x1 +-#define MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x1d8 0x4e0 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT18__ARM_TRACE18 0x1d8 0x4e0 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT18__SRC_BOOT_CFG26 0x1d8 0x4e0 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1dc 0x4e4 0x7c4 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT19__KEY_ROW5 0x1dc 0x4e4 0x768 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT19__CSI_DATA14 0x1dc 0x4e4 0x668 0x2 0x0 +-#define MX6SL_PAD_LCD_DAT19__EIM_DATA13 0x1dc 0x4e4 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT19__GPT_CAPTURE2 0x1dc 0x4e4 0x714 0x4 0x1 +-#define MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x1dc 0x4e4 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT19__ARM_TRACE19 0x1dc 0x4e4 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT19__SRC_BOOT_CFG27 0x1dc 0x4e4 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1e0 0x4e8 0x780 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT2__ECSPI1_SS0 0x1e0 0x4e8 0x68c 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT2__EPIT2_OUT 0x1e0 0x4e8 0x000 0x2 0x0 +-#define MX6SL_PAD_LCD_DAT2__PWM3_OUT 0x1e0 0x4e8 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT2__AUD4_RXC 0x1e0 0x4e8 0x5ec 0x4 0x1 +-#define MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x1e0 0x4e8 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT2__ARM_TRACE02 0x1e0 0x4e8 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT2__SRC_BOOT_CFG02 0x1e0 0x4e8 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1e4 0x4ec 0x7c8 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT20__KEY_COL6 0x1e4 0x4ec 0x74c 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT20__CSI_DATA13 0x1e4 0x4ec 0x664 0x2 0x0 +-#define MX6SL_PAD_LCD_DAT20__EIM_DATA14 0x1e4 0x4ec 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT20__GPT_COMPARE1 0x1e4 0x4ec 0x000 0x4 0x0 +-#define MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x1e4 0x4ec 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT20__ARM_TRACE20 0x1e4 0x4ec 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT20__SRC_BOOT_CFG28 0x1e4 0x4ec 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1e8 0x4f0 0x7cc 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT21__KEY_ROW6 0x1e8 0x4f0 0x76c 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT21__CSI_DATA12 0x1e8 0x4f0 0x660 0x2 0x0 +-#define MX6SL_PAD_LCD_DAT21__EIM_DATA15 0x1e8 0x4f0 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT21__GPT_COMPARE2 0x1e8 0x4f0 0x000 0x4 0x0 +-#define MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x1e8 0x4f0 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT21__ARM_TRACE21 0x1e8 0x4f0 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT21__SRC_BOOT_CFG29 0x1e8 0x4f0 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1ec 0x4f4 0x7d0 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT22__KEY_COL7 0x1ec 0x4f4 0x750 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT22__CSI_DATA11 0x1ec 0x4f4 0x65c 0x2 0x1 +-#define MX6SL_PAD_LCD_DAT22__EIM_EB3_B 0x1ec 0x4f4 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT22__GPT_COMPARE3 0x1ec 0x4f4 0x000 0x4 0x0 +-#define MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x1ec 0x4f4 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT22__ARM_TRACE22 0x1ec 0x4f4 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT22__SRC_BOOT_CFG30 0x1ec 0x4f4 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1f0 0x4f8 0x7d4 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT23__KEY_ROW7 0x1f0 0x4f8 0x770 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT23__CSI_DATA10 0x1f0 0x4f8 0x658 0x2 0x1 +-#define MX6SL_PAD_LCD_DAT23__EIM_EB2_B 0x1f0 0x4f8 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT23__GPT_CLKIN 0x1f0 0x4f8 0x718 0x4 0x1 +-#define MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x1f0 0x4f8 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT23__ARM_TRACE23 0x1f0 0x4f8 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT23__SRC_BOOT_CFG31 0x1f0 0x4f8 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1f4 0x4fc 0x784 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT3__ECSPI1_SCLK 0x1f4 0x4fc 0x67c 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT3__UART5_DSR_B 0x1f4 0x4fc 0x000 0x2 0x0 +-#define MX6SL_PAD_LCD_DAT3__PWM4_OUT 0x1f4 0x4fc 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT3__AUD4_RXD 0x1f4 0x4fc 0x5e4 0x4 0x1 +-#define MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x1f4 0x4fc 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT3__ARM_TRACE03 0x1f4 0x4fc 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT3__SRC_BOOT_CFG03 0x1f4 0x4fc 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1f8 0x500 0x788 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT4__ECSPI1_SS1 0x1f8 0x500 0x690 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT4__CSI_VSYNC 0x1f8 0x500 0x678 0x2 0x2 +-#define MX6SL_PAD_LCD_DAT4__WDOG2_RESET_B_DEB 0x1f8 0x500 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT4__AUD4_TXC 0x1f8 0x500 0x5f4 0x4 0x1 +-#define MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x1f8 0x500 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT4__ARM_TRACE04 0x1f8 0x500 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT4__SRC_BOOT_CFG04 0x1f8 0x500 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1fc 0x504 0x78c 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT5__ECSPI1_SS2 0x1fc 0x504 0x694 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT5__CSI_HSYNC 0x1fc 0x504 0x670 0x2 0x2 +-#define MX6SL_PAD_LCD_DAT5__EIM_CS3_B 0x1fc 0x504 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT5__AUD4_TXFS 0x1fc 0x504 0x5f8 0x4 0x1 +-#define MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x1fc 0x504 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT5__ARM_TRACE05 0x1fc 0x504 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT5__SRC_BOOT_CFG05 0x1fc 0x504 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x200 0x508 0x790 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT6__ECSPI1_SS3 0x200 0x508 0x698 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT6__CSI_PIXCLK 0x200 0x508 0x674 0x2 0x2 +-#define MX6SL_PAD_LCD_DAT6__EIM_DATA00 0x200 0x508 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT6__AUD4_TXD 0x200 0x508 0x5e8 0x4 0x1 +-#define MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x200 0x508 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT6__ARM_TRACE06 0x200 0x508 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT6__SRC_BOOT_CFG06 0x200 0x508 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x204 0x50c 0x794 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT7__ECSPI1_RDY 0x204 0x50c 0x680 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT7__CSI_MCLK 0x204 0x50c 0x000 0x2 0x0 +-#define MX6SL_PAD_LCD_DAT7__EIM_DATA01 0x204 0x50c 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT7__AUDIO_CLK_OUT 0x204 0x50c 0x000 0x4 0x0 +-#define MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x204 0x50c 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT7__ARM_TRACE07 0x204 0x50c 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT7__SRC_BOOT_CFG07 0x204 0x50c 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x208 0x510 0x798 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT8__KEY_COL0 0x208 0x510 0x734 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT8__CSI_DATA09 0x208 0x510 0x654 0x2 0x1 +-#define MX6SL_PAD_LCD_DAT8__EIM_DATA02 0x208 0x510 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT8__ECSPI2_SCLK 0x208 0x510 0x69c 0x4 0x2 +-#define MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x208 0x510 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT8__ARM_TRACE08 0x208 0x510 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT8__SRC_BOOT_CFG08 0x208 0x510 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x20c 0x514 0x79c 0x0 0x1 +-#define MX6SL_PAD_LCD_DAT9__KEY_ROW0 0x20c 0x514 0x754 0x1 0x1 +-#define MX6SL_PAD_LCD_DAT9__CSI_DATA08 0x20c 0x514 0x650 0x2 0x1 +-#define MX6SL_PAD_LCD_DAT9__EIM_DATA03 0x20c 0x514 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_DAT9__ECSPI2_MOSI 0x20c 0x514 0x6a4 0x4 0x2 +-#define MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x20c 0x514 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_DAT9__ARM_TRACE09 0x20c 0x514 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_DAT9__SRC_BOOT_CFG09 0x20c 0x514 0x000 0x7 0x0 +-#define MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x210 0x518 0x000 0x0 0x0 +-#define MX6SL_PAD_LCD_ENABLE__SD4_DATA5 0x210 0x518 0x870 0x1 0x2 +-#define MX6SL_PAD_LCD_ENABLE__LCD_RD_E 0x210 0x518 0x000 0x2 0x0 +-#define MX6SL_PAD_LCD_ENABLE__EIM_OE_B 0x210 0x518 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_ENABLE__UART2_RX_DATA 0x210 0x518 0x804 0x4 0x2 +-#define MX6SL_PAD_LCD_ENABLE__UART2_TX_DATA 0x210 0x518 0x000 0x4 0x0 +-#define MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x210 0x518 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x214 0x51c 0x774 0x0 0x0 +-#define MX6SL_PAD_LCD_HSYNC__SD4_DATA6 0x214 0x51c 0x874 0x1 0x2 +-#define MX6SL_PAD_LCD_HSYNC__LCD_CS 0x214 0x51c 0x000 0x2 0x0 +-#define MX6SL_PAD_LCD_HSYNC__EIM_CS0_B 0x214 0x51c 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_HSYNC__UART2_TX_DATA 0x214 0x51c 0x000 0x4 0x0 +-#define MX6SL_PAD_LCD_HSYNC__UART2_RX_DATA 0x214 0x51c 0x804 0x4 0x3 +-#define MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x214 0x51c 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x214 0x51c 0x000 0x6 0x0 +-#define MX6SL_PAD_LCD_RESET__LCD_RESET 0x218 0x520 0x000 0x0 0x0 +-#define MX6SL_PAD_LCD_RESET__EIM_DTACK_B 0x218 0x520 0x880 0x1 0x1 +-#define MX6SL_PAD_LCD_RESET__LCD_BUSY 0x218 0x520 0x774 0x2 0x1 +-#define MX6SL_PAD_LCD_RESET__EIM_WAIT_B 0x218 0x520 0x884 0x3 0x1 +-#define MX6SL_PAD_LCD_RESET__UART2_CTS_B 0x218 0x520 0x000 0x4 0x0 +-#define MX6SL_PAD_LCD_RESET__UART2_RTS_B 0x218 0x520 0x800 0x4 0x2 +-#define MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x218 0x520 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_RESET__CCM_PMIC_READY 0x218 0x520 0x62c 0x6 0x1 +-#define MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x21c 0x524 0x000 0x0 0x0 +-#define MX6SL_PAD_LCD_VSYNC__SD4_DATA7 0x21c 0x524 0x878 0x1 0x2 +-#define MX6SL_PAD_LCD_VSYNC__LCD_RS 0x21c 0x524 0x000 0x2 0x0 +-#define MX6SL_PAD_LCD_VSYNC__EIM_CS1_B 0x21c 0x524 0x000 0x3 0x0 +-#define MX6SL_PAD_LCD_VSYNC__UART2_RTS_B 0x21c 0x524 0x800 0x4 0x3 +-#define MX6SL_PAD_LCD_VSYNC__UART2_CTS_B 0x21c 0x524 0x000 0x4 0x0 +-#define MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x21c 0x524 0x000 0x5 0x0 +-#define MX6SL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x21c 0x524 0x000 0x6 0x0 +-#define MX6SL_PAD_PWM1__PWM1_OUT 0x220 0x528 0x000 0x0 0x0 +-#define MX6SL_PAD_PWM1__CCM_CLKO 0x220 0x528 0x000 0x1 0x0 +-#define MX6SL_PAD_PWM1__AUDIO_CLK_OUT 0x220 0x528 0x000 0x2 0x0 +-#define MX6SL_PAD_PWM1__FEC_REF_OUT 0x220 0x528 0x000 0x3 0x0 +-#define MX6SL_PAD_PWM1__CSI_MCLK 0x220 0x528 0x000 0x4 0x0 +-#define MX6SL_PAD_PWM1__GPIO3_IO23 0x220 0x528 0x000 0x5 0x0 +-#define MX6SL_PAD_PWM1__EPIT1_OUT 0x220 0x528 0x000 0x6 0x0 +-#define MX6SL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x224 0x52c 0x000 0x0 0x0 +-#define MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x224 0x52c 0x72c 0x1 0x2 +-#define MX6SL_PAD_REF_CLK_24M__PWM3_OUT 0x224 0x52c 0x000 0x2 0x0 +-#define MX6SL_PAD_REF_CLK_24M__USB_OTG2_ID 0x224 0x52c 0x5e0 0x3 0x2 +-#define MX6SL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x224 0x52c 0x62c 0x4 0x2 +-#define MX6SL_PAD_REF_CLK_24M__GPIO3_IO21 0x224 0x52c 0x000 0x5 0x0 +-#define MX6SL_PAD_REF_CLK_24M__SD3_WP 0x224 0x52c 0x84c 0x6 0x3 +-#define MX6SL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x228 0x530 0x000 0x0 0x0 +-#define MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x228 0x530 0x730 0x1 0x2 +-#define MX6SL_PAD_REF_CLK_32K__PWM4_OUT 0x228 0x530 0x000 0x2 0x0 +-#define MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x228 0x530 0x5dc 0x3 0x3 +-#define MX6SL_PAD_REF_CLK_32K__SD1_LCTL 0x228 0x530 0x000 0x4 0x0 +-#define MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x228 0x530 0x000 0x5 0x0 +-#define MX6SL_PAD_REF_CLK_32K__SD3_CD_B 0x228 0x530 0x838 0x6 0x3 +-#define MX6SL_PAD_SD1_CLK__SD1_CLK 0x22c 0x534 0x000 0x0 0x0 +-#define MX6SL_PAD_SD1_CLK__FEC_MDIO 0x22c 0x534 0x6f4 0x1 0x2 +-#define MX6SL_PAD_SD1_CLK__KEY_COL0 0x22c 0x534 0x734 0x2 0x2 +-#define MX6SL_PAD_SD1_CLK__EPDC_SDCE4 0x22c 0x534 0x000 0x3 0x0 +-#define MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x22c 0x534 0x000 0x5 0x0 +-#define MX6SL_PAD_SD1_CMD__SD1_CMD 0x230 0x538 0x000 0x0 0x0 +-#define MX6SL_PAD_SD1_CMD__FEC_TX_CLK 0x230 0x538 0x70c 0x1 0x2 +-#define MX6SL_PAD_SD1_CMD__KEY_ROW0 0x230 0x538 0x754 0x2 0x2 +-#define MX6SL_PAD_SD1_CMD__EPDC_SDCE5 0x230 0x538 0x000 0x3 0x0 +-#define MX6SL_PAD_SD1_CMD__GPIO5_IO14 0x230 0x538 0x000 0x5 0x0 +-#define MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x234 0x53c 0x000 0x0 0x0 +-#define MX6SL_PAD_SD1_DAT0__FEC_RX_ER 0x234 0x53c 0x708 0x1 0x2 +-#define MX6SL_PAD_SD1_DAT0__KEY_COL1 0x234 0x53c 0x738 0x2 0x2 +-#define MX6SL_PAD_SD1_DAT0__EPDC_SDCE6 0x234 0x53c 0x000 0x3 0x0 +-#define MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x234 0x53c 0x000 0x5 0x0 +-#define MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x238 0x540 0x000 0x0 0x0 +-#define MX6SL_PAD_SD1_DAT1__FEC_RX_DV 0x238 0x540 0x704 0x1 0x2 +-#define MX6SL_PAD_SD1_DAT1__KEY_ROW1 0x238 0x540 0x758 0x2 0x2 +-#define MX6SL_PAD_SD1_DAT1__EPDC_SDCE7 0x238 0x540 0x000 0x3 0x0 +-#define MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x238 0x540 0x000 0x5 0x0 +-#define MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x23c 0x544 0x000 0x0 0x0 +-#define MX6SL_PAD_SD1_DAT2__FEC_RX_DATA1 0x23c 0x544 0x6fc 0x1 0x2 +-#define MX6SL_PAD_SD1_DAT2__KEY_COL2 0x23c 0x544 0x73c 0x2 0x2 +-#define MX6SL_PAD_SD1_DAT2__EPDC_SDCE8 0x23c 0x544 0x000 0x3 0x0 +-#define MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x23c 0x544 0x000 0x5 0x0 +-#define MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x240 0x548 0x000 0x0 0x0 +-#define MX6SL_PAD_SD1_DAT3__FEC_TX_DATA0 0x240 0x548 0x000 0x1 0x0 +-#define MX6SL_PAD_SD1_DAT3__KEY_ROW2 0x240 0x548 0x75c 0x2 0x2 +-#define MX6SL_PAD_SD1_DAT3__EPDC_SDCE9 0x240 0x548 0x000 0x3 0x0 +-#define MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x240 0x548 0x000 0x5 0x0 +-#define MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x244 0x54c 0x000 0x0 0x0 +-#define MX6SL_PAD_SD1_DAT4__FEC_MDC 0x244 0x54c 0x000 0x1 0x0 +-#define MX6SL_PAD_SD1_DAT4__KEY_COL3 0x244 0x54c 0x740 0x2 0x2 +-#define MX6SL_PAD_SD1_DAT4__EPDC_SDCLK_N 0x244 0x54c 0x000 0x3 0x0 +-#define MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x244 0x54c 0x814 0x4 0x4 +-#define MX6SL_PAD_SD1_DAT4__UART4_TX_DATA 0x244 0x54c 0x000 0x4 0x0 +-#define MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x244 0x54c 0x000 0x5 0x0 +-#define MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x248 0x550 0x000 0x0 0x0 +-#define MX6SL_PAD_SD1_DAT5__FEC_RX_DATA0 0x248 0x550 0x6f8 0x1 0x2 +-#define MX6SL_PAD_SD1_DAT5__KEY_ROW3 0x248 0x550 0x760 0x2 0x2 +-#define MX6SL_PAD_SD1_DAT5__EPDC_SDOED 0x248 0x550 0x000 0x3 0x0 +-#define MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x248 0x550 0x000 0x4 0x0 +-#define MX6SL_PAD_SD1_DAT5__UART4_RX_DATA 0x248 0x550 0x814 0x4 0x5 +-#define MX6SL_PAD_SD1_DAT5__GPIO5_IO09 0x248 0x550 0x000 0x5 0x0 +-#define MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x24c 0x554 0x000 0x0 0x0 +-#define MX6SL_PAD_SD1_DAT6__FEC_TX_EN 0x24c 0x554 0x000 0x1 0x0 +-#define MX6SL_PAD_SD1_DAT6__KEY_COL4 0x24c 0x554 0x744 0x2 0x2 +-#define MX6SL_PAD_SD1_DAT6__EPDC_SDOEZ 0x24c 0x554 0x000 0x3 0x0 +-#define MX6SL_PAD_SD1_DAT6__UART4_RTS_B 0x24c 0x554 0x810 0x4 0x4 +-#define MX6SL_PAD_SD1_DAT6__UART4_CTS_B 0x24c 0x554 0x000 0x4 0x0 +-#define MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x24c 0x554 0x000 0x5 0x0 +-#define MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x250 0x558 0x000 0x0 0x0 +-#define MX6SL_PAD_SD1_DAT7__FEC_TX_DATA1 0x250 0x558 0x000 0x1 0x0 +-#define MX6SL_PAD_SD1_DAT7__KEY_ROW4 0x250 0x558 0x764 0x2 0x2 +-#define MX6SL_PAD_SD1_DAT7__CCM_PMIC_READY 0x250 0x558 0x62c 0x3 0x3 +-#define MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x250 0x558 0x000 0x4 0x0 +-#define MX6SL_PAD_SD1_DAT7__UART4_RTS_B 0x250 0x558 0x810 0x4 0x5 +-#define MX6SL_PAD_SD1_DAT7__GPIO5_IO10 0x250 0x558 0x000 0x5 0x0 +-#define MX6SL_PAD_SD2_CLK__SD2_CLK 0x254 0x55c 0x000 0x0 0x0 +-#define MX6SL_PAD_SD2_CLK__AUD4_RXFS 0x254 0x55c 0x5f0 0x1 0x2 +-#define MX6SL_PAD_SD2_CLK__ECSPI3_SCLK 0x254 0x55c 0x6b0 0x2 0x2 +-#define MX6SL_PAD_SD2_CLK__CSI_DATA00 0x254 0x55c 0x630 0x3 0x2 +-#define MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x254 0x55c 0x000 0x5 0x0 +-#define MX6SL_PAD_SD2_CMD__SD2_CMD 0x258 0x560 0x000 0x0 0x0 +-#define MX6SL_PAD_SD2_CMD__AUD4_RXC 0x258 0x560 0x5ec 0x1 0x2 +-#define MX6SL_PAD_SD2_CMD__ECSPI3_SS0 0x258 0x560 0x6c0 0x2 0x2 +-#define MX6SL_PAD_SD2_CMD__CSI_DATA01 0x258 0x560 0x634 0x3 0x2 +-#define MX6SL_PAD_SD2_CMD__EPIT1_OUT 0x258 0x560 0x000 0x4 0x0 +-#define MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x258 0x560 0x000 0x5 0x0 +-#define MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x25c 0x564 0x000 0x0 0x0 +-#define MX6SL_PAD_SD2_DAT0__AUD4_RXD 0x25c 0x564 0x5e4 0x1 0x2 +-#define MX6SL_PAD_SD2_DAT0__ECSPI3_MOSI 0x25c 0x564 0x6bc 0x2 0x2 +-#define MX6SL_PAD_SD2_DAT0__CSI_DATA02 0x25c 0x564 0x638 0x3 0x2 +-#define MX6SL_PAD_SD2_DAT0__UART5_RTS_B 0x25c 0x564 0x818 0x4 0x4 +-#define MX6SL_PAD_SD2_DAT0__UART5_CTS_B 0x25c 0x564 0x000 0x4 0x0 +-#define MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x25c 0x564 0x000 0x5 0x0 +-#define MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x260 0x568 0x000 0x0 0x0 +-#define MX6SL_PAD_SD2_DAT1__AUD4_TXC 0x260 0x568 0x5f4 0x1 0x2 +-#define MX6SL_PAD_SD2_DAT1__ECSPI3_MISO 0x260 0x568 0x6b8 0x2 0x2 +-#define MX6SL_PAD_SD2_DAT1__CSI_DATA03 0x260 0x568 0x63c 0x3 0x2 +-#define MX6SL_PAD_SD2_DAT1__UART5_CTS_B 0x260 0x568 0x000 0x4 0x0 +-#define MX6SL_PAD_SD2_DAT1__UART5_RTS_B 0x260 0x568 0x818 0x4 0x5 +-#define MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x260 0x568 0x000 0x5 0x0 +-#define MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x264 0x56c 0x000 0x0 0x0 +-#define MX6SL_PAD_SD2_DAT2__AUD4_TXFS 0x264 0x56c 0x5f8 0x1 0x2 +-#define MX6SL_PAD_SD2_DAT2__FEC_COL 0x264 0x56c 0x6f0 0x2 0x1 +-#define MX6SL_PAD_SD2_DAT2__CSI_DATA04 0x264 0x56c 0x640 0x3 0x2 +-#define MX6SL_PAD_SD2_DAT2__UART5_RX_DATA 0x264 0x56c 0x81c 0x4 0x4 +-#define MX6SL_PAD_SD2_DAT2__UART5_TX_DATA 0x264 0x56c 0x000 0x4 0x0 +-#define MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x264 0x56c 0x000 0x5 0x0 +-#define MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x268 0x570 0x000 0x0 0x0 +-#define MX6SL_PAD_SD2_DAT3__AUD4_TXD 0x268 0x570 0x5e8 0x1 0x2 +-#define MX6SL_PAD_SD2_DAT3__FEC_RX_CLK 0x268 0x570 0x700 0x2 0x1 +-#define MX6SL_PAD_SD2_DAT3__CSI_DATA05 0x268 0x570 0x644 0x3 0x2 +-#define MX6SL_PAD_SD2_DAT3__UART5_TX_DATA 0x268 0x570 0x000 0x4 0x0 +-#define MX6SL_PAD_SD2_DAT3__UART5_RX_DATA 0x268 0x570 0x81c 0x4 0x5 +-#define MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x268 0x570 0x000 0x5 0x0 +-#define MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x26c 0x574 0x000 0x0 0x0 +-#define MX6SL_PAD_SD2_DAT4__SD3_DATA4 0x26c 0x574 0x83c 0x1 0x1 +-#define MX6SL_PAD_SD2_DAT4__UART2_RX_DATA 0x26c 0x574 0x804 0x2 0x4 +-#define MX6SL_PAD_SD2_DAT4__UART2_TX_DATA 0x26c 0x574 0x000 0x2 0x0 +-#define MX6SL_PAD_SD2_DAT4__CSI_DATA06 0x26c 0x574 0x648 0x3 0x2 +-#define MX6SL_PAD_SD2_DAT4__SPDIF_OUT 0x26c 0x574 0x000 0x4 0x0 +-#define MX6SL_PAD_SD2_DAT4__GPIO5_IO02 0x26c 0x574 0x000 0x5 0x0 +-#define MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x270 0x578 0x000 0x0 0x0 +-#define MX6SL_PAD_SD2_DAT5__SD3_DATA5 0x270 0x578 0x840 0x1 0x1 +-#define MX6SL_PAD_SD2_DAT5__UART2_TX_DATA 0x270 0x578 0x000 0x2 0x0 +-#define MX6SL_PAD_SD2_DAT5__UART2_RX_DATA 0x270 0x578 0x804 0x2 0x5 +-#define MX6SL_PAD_SD2_DAT5__CSI_DATA07 0x270 0x578 0x64c 0x3 0x2 +-#define MX6SL_PAD_SD2_DAT5__SPDIF_IN 0x270 0x578 0x7f0 0x4 0x2 +-#define MX6SL_PAD_SD2_DAT5__GPIO4_IO31 0x270 0x578 0x000 0x5 0x0 +-#define MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x274 0x57c 0x000 0x0 0x0 +-#define MX6SL_PAD_SD2_DAT6__SD3_DATA6 0x274 0x57c 0x844 0x1 0x1 +-#define MX6SL_PAD_SD2_DAT6__UART2_RTS_B 0x274 0x57c 0x800 0x2 0x4 +-#define MX6SL_PAD_SD2_DAT6__UART2_CTS_B 0x274 0x57c 0x000 0x2 0x0 +-#define MX6SL_PAD_SD2_DAT6__CSI_DATA08 0x274 0x57c 0x650 0x3 0x2 +-#define MX6SL_PAD_SD2_DAT6__SD2_WP 0x274 0x57c 0x834 0x4 0x2 +-#define MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x274 0x57c 0x000 0x5 0x0 +-#define MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x278 0x580 0x000 0x0 0x0 +-#define MX6SL_PAD_SD2_DAT7__SD3_DATA7 0x278 0x580 0x848 0x1 0x1 +-#define MX6SL_PAD_SD2_DAT7__UART2_CTS_B 0x278 0x580 0x000 0x2 0x0 +-#define MX6SL_PAD_SD2_DAT7__UART2_RTS_B 0x278 0x580 0x800 0x2 0x5 +-#define MX6SL_PAD_SD2_DAT7__CSI_DATA09 0x278 0x580 0x654 0x3 0x2 +-#define MX6SL_PAD_SD2_DAT7__SD2_CD_B 0x278 0x580 0x830 0x4 0x2 +-#define MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x278 0x580 0x000 0x5 0x0 +-#define MX6SL_PAD_SD2_RST__SD2_RESET 0x27c 0x584 0x000 0x0 0x0 +-#define MX6SL_PAD_SD2_RST__FEC_REF_OUT 0x27c 0x584 0x000 0x1 0x0 +-#define MX6SL_PAD_SD2_RST__WDOG2_B 0x27c 0x584 0x000 0x2 0x0 +-#define MX6SL_PAD_SD2_RST__SPDIF_OUT 0x27c 0x584 0x000 0x3 0x0 +-#define MX6SL_PAD_SD2_RST__CSI_MCLK 0x27c 0x584 0x000 0x4 0x0 +-#define MX6SL_PAD_SD2_RST__GPIO4_IO27 0x27c 0x584 0x000 0x5 0x0 +-#define MX6SL_PAD_SD3_CLK__SD3_CLK 0x280 0x588 0x000 0x0 0x0 +-#define MX6SL_PAD_SD3_CLK__AUD5_RXFS 0x280 0x588 0x608 0x1 0x1 +-#define MX6SL_PAD_SD3_CLK__KEY_COL5 0x280 0x588 0x748 0x2 0x2 +-#define MX6SL_PAD_SD3_CLK__CSI_DATA10 0x280 0x588 0x658 0x3 0x2 +-#define MX6SL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x280 0x588 0x000 0x4 0x0 +-#define MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x280 0x588 0x000 0x5 0x0 +-#define MX6SL_PAD_SD3_CLK__USB_OTG1_PWR 0x280 0x588 0x000 0x6 0x0 +-#define MX6SL_PAD_SD3_CMD__SD3_CMD 0x284 0x58c 0x000 0x0 0x0 +-#define MX6SL_PAD_SD3_CMD__AUD5_RXC 0x284 0x58c 0x604 0x1 0x1 +-#define MX6SL_PAD_SD3_CMD__KEY_ROW5 0x284 0x58c 0x768 0x2 0x2 +-#define MX6SL_PAD_SD3_CMD__CSI_DATA11 0x284 0x58c 0x65c 0x3 0x2 +-#define MX6SL_PAD_SD3_CMD__USB_OTG2_ID 0x284 0x58c 0x5e0 0x4 0x3 +-#define MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x284 0x58c 0x000 0x5 0x0 +-#define MX6SL_PAD_SD3_CMD__USB_OTG2_PWR 0x284 0x58c 0x000 0x6 0x0 +-#define MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x288 0x590 0x000 0x0 0x0 +-#define MX6SL_PAD_SD3_DAT0__AUD5_RXD 0x288 0x590 0x5fc 0x1 0x1 +-#define MX6SL_PAD_SD3_DAT0__KEY_COL6 0x288 0x590 0x74c 0x2 0x2 +-#define MX6SL_PAD_SD3_DAT0__CSI_DATA12 0x288 0x590 0x660 0x3 0x1 +-#define MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x288 0x590 0x5dc 0x4 0x4 +-#define MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x288 0x590 0x000 0x5 0x0 +-#define MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x28c 0x594 0x000 0x0 0x0 +-#define MX6SL_PAD_SD3_DAT1__AUD5_TXC 0x28c 0x594 0x60c 0x1 0x1 +-#define MX6SL_PAD_SD3_DAT1__KEY_ROW6 0x28c 0x594 0x76c 0x2 0x2 +-#define MX6SL_PAD_SD3_DAT1__CSI_DATA13 0x28c 0x594 0x664 0x3 0x1 +-#define MX6SL_PAD_SD3_DAT1__SD1_VSELECT 0x28c 0x594 0x000 0x4 0x0 +-#define MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x28c 0x594 0x000 0x5 0x0 +-#define MX6SL_PAD_SD3_DAT1__JTAG_DE_B 0x28c 0x594 0x000 0x6 0x0 +-#define MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x290 0x598 0x000 0x0 0x0 +-#define MX6SL_PAD_SD3_DAT2__AUD5_TXFS 0x290 0x598 0x610 0x1 0x1 +-#define MX6SL_PAD_SD3_DAT2__KEY_COL7 0x290 0x598 0x750 0x2 0x2 +-#define MX6SL_PAD_SD3_DAT2__CSI_DATA14 0x290 0x598 0x668 0x3 0x1 +-#define MX6SL_PAD_SD3_DAT2__EPIT1_OUT 0x290 0x598 0x000 0x4 0x0 +-#define MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x290 0x598 0x000 0x5 0x0 +-#define MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x290 0x598 0x820 0x6 0x3 +-#define MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x294 0x59c 0x000 0x0 0x0 +-#define MX6SL_PAD_SD3_DAT3__AUD5_TXD 0x294 0x59c 0x600 0x1 0x1 +-#define MX6SL_PAD_SD3_DAT3__KEY_ROW7 0x294 0x59c 0x770 0x2 0x2 +-#define MX6SL_PAD_SD3_DAT3__CSI_DATA15 0x294 0x59c 0x66c 0x3 0x1 +-#define MX6SL_PAD_SD3_DAT3__EPIT2_OUT 0x294 0x59c 0x000 0x4 0x0 +-#define MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x294 0x59c 0x000 0x5 0x0 +-#define MX6SL_PAD_SD3_DAT3__USB_OTG1_OC 0x294 0x59c 0x824 0x6 0x2 +-#define MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x298 0x5a0 0x7fc 0x0 0x0 +-#define MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x298 0x5a0 0x000 0x0 0x0 +-#define MX6SL_PAD_UART1_RXD__PWM1_OUT 0x298 0x5a0 0x000 0x1 0x0 +-#define MX6SL_PAD_UART1_RXD__UART4_RX_DATA 0x298 0x5a0 0x814 0x2 0x6 +-#define MX6SL_PAD_UART1_RXD__UART4_TX_DATA 0x298 0x5a0 0x000 0x2 0x0 +-#define MX6SL_PAD_UART1_RXD__FEC_COL 0x298 0x5a0 0x6f0 0x3 0x2 +-#define MX6SL_PAD_UART1_RXD__UART5_RX_DATA 0x298 0x5a0 0x81c 0x4 0x6 +-#define MX6SL_PAD_UART1_RXD__UART5_TX_DATA 0x298 0x5a0 0x000 0x4 0x0 +-#define MX6SL_PAD_UART1_RXD__GPIO3_IO16 0x298 0x5a0 0x000 0x5 0x0 +-#define MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x29c 0x5a4 0x000 0x0 0x0 +-#define MX6SL_PAD_UART1_TXD__UART1_RX_DATA 0x29c 0x5a4 0x7fc 0x0 0x1 +-#define MX6SL_PAD_UART1_TXD__PWM2_OUT 0x29c 0x5a4 0x000 0x1 0x0 +-#define MX6SL_PAD_UART1_TXD__UART4_TX_DATA 0x29c 0x5a4 0x000 0x2 0x0 +-#define MX6SL_PAD_UART1_TXD__UART4_RX_DATA 0x29c 0x5a4 0x814 0x2 0x7 +-#define MX6SL_PAD_UART1_TXD__FEC_RX_CLK 0x29c 0x5a4 0x700 0x3 0x2 +-#define MX6SL_PAD_UART1_TXD__UART5_TX_DATA 0x29c 0x5a4 0x000 0x4 0x0 +-#define MX6SL_PAD_UART1_TXD__UART5_RX_DATA 0x29c 0x5a4 0x81c 0x4 0x7 +-#define MX6SL_PAD_UART1_TXD__GPIO3_IO17 0x29c 0x5a4 0x000 0x5 0x0 +-#define MX6SL_PAD_UART1_TXD__UART5_DCD_B 0x29c 0x5a4 0x000 0x7 0x0 +-#define MX6SL_PAD_WDOG_B__WDOG1_B 0x2a0 0x5a8 0x000 0x0 0x0 +-#define MX6SL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x2a0 0x5a8 0x000 0x1 0x0 +-#define MX6SL_PAD_WDOG_B__UART5_RI_B 0x2a0 0x5a8 0x000 0x2 0x0 +-#define MX6SL_PAD_WDOG_B__GPIO3_IO18 0x2a0 0x5a8 0x000 0x5 0x0 +- +-#endif /* __DTS_IMX6SL_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm/imx6sl-tolino-shine2hd.dts b/scripts/dtc/include-prefixes/arm/imx6sl-tolino-shine2hd.dts +deleted file mode 100644 +index a17b8bbbdb95..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sl-tolino-shine2hd.dts ++++ /dev/null +@@ -1,605 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device tree for the Tolino Shine 2 HD ebook reader +- * +- * Name on mainboard is: 37NB-E60QF0+4A2 or 37NB-E60QF0+4A3 +- * Serials start with: E60QF2 +- * +- * Copyright 2020 Andreas Kemnade +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "imx6sl.dtsi" +- +-/ { +- model = "Tolino Shine 2 HD"; +- compatible = "kobo,tolino-shine2hd", "fsl,imx6sl"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- gpio_keys: gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- cover { +- label = "Cover"; +- gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; +- linux,code = ; +- linux,input-type = ; +- wakeup-source; +- }; +- +- fl { +- label = "Frontlight"; +- gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- home { +- label = "Home"; +- gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- power { +- label = "Power"; +- gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds: leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led>; +- +- on { +- label = "tolinoshine2hd:white:on"; +- gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "timer"; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +- +- reg_wifi: regulator-wifi { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wifi_power>; +- regulator-name = "SD3_SPWR"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wifi_reset>; +- post-power-on-delay-ms = <20>; +- reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default","sleep"; +- pinctrl-0 = <&pinctrl_i2c1>; +- pinctrl-1 = <&pinctrl_i2c1_sleep>; +- status = "okay"; +- +- ec: embedded-controller@43 { +- compatible = "netronix,ntxec"; +- reg = <0x43>; +- #pwm-cells = <2>; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default","sleep"; +- pinctrl-0 = <&pinctrl_i2c2>; +- pinctrl-1 = <&pinctrl_i2c2_sleep>; +- clock-frequency = <100000>; +- status = "okay"; +- +- zforce: touchscreen@50 { +- compatible = "neonode,zforce"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_zforce>; +- reg = <0x50>; +- interrupt-parent = <&gpio5>; +- interrupts = <6 IRQ_TYPE_EDGE_FALLING>; +- vdd-supply = <&ldo1_reg>; +- reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; +- x-size = <1072>; +- y-size = <1448>; +- }; +- +- /* TODO: TPS65185 PMIC for E Ink at 0x68 */ +- +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- clock-frequency = <400000>; +- status = "okay"; +- +- ricoh619: pmic@32 { +- compatible = "ricoh,rc5t619"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ricoh_gpio>; +- reg = <0x32>; +- interrupt-parent = <&gpio5>; +- interrupts = <11 IRQ_TYPE_EDGE_FALLING>; +- system-power-controller; +- +- regulators { +- dcdc1_reg: DCDC1 { +- regulator-name = "DCDC1"; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-max-microvolt = <900000>; +- regulator-suspend-min-microvolt = <900000>; +- }; +- }; +- +- /* Core3_3V3 */ +- dcdc2_reg: DCDC2 { +- regulator-name = "DCDC2"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-max-microvolt = <3100000>; +- regulator-suspend-min-microvolt = <3100000>; +- }; +- }; +- +- dcdc3_reg: DCDC3 { +- regulator-name = "DCDC3"; +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-max-microvolt = <1140000>; +- regulator-suspend-min-microvolt = <1140000>; +- }; +- }; +- +- /* Core4_1V2 */ +- dcdc4_reg: DCDC4 { +- regulator-name = "DCDC4"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-max-microvolt = <1140000>; +- regulator-suspend-min-microvolt = <1140000>; +- }; +- }; +- +- /* Core4_1V8 */ +- dcdc5_reg: DCDC5 { +- regulator-name = "DCDC5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-max-microvolt = <1700000>; +- regulator-suspend-min-microvolt = <1700000>; +- }; +- }; +- +- /* IR_3V3 */ +- ldo1_reg: LDO1 { +- regulator-name = "LDO1"; +- regulator-boot-on; +- }; +- +- /* Core1_3V3 */ +- ldo2_reg: LDO2 { +- regulator-name = "LDO2"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-max-microvolt = <3000000>; +- regulator-suspend-min-microvolt = <3000000>; +- }; +- }; +- +- /* Core5_1V2 */ +- ldo3_reg: LDO3 { +- regulator-name = "LDO3"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "LDO4"; +- regulator-boot-on; +- }; +- +- /* SPD_3V3 */ +- ldo5_reg: LDO5 { +- regulator-name = "LDO5"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* DDR_0V6 */ +- ldo6_reg: LDO6 { +- regulator-name = "LDO6"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* VDD_PWM */ +- ldo7_reg: LDO7 { +- regulator-name = "LDO7"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* ldo_1v8 */ +- ldo8_reg: LDO8 { +- regulator-name = "LDO8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "LDO9"; +- regulator-boot-on; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "LDO10"; +- regulator-boot-on; +- }; +- +- ldortc1_reg: LDORTC1 { +- regulator-name = "LDORTC1"; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_gpio_keys: gpio-keysgrp { +- fsl,pins = < +- MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 +- MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059 +- MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x17059 +- MX6SL_PAD_KEY_ROW0__GPIO3_IO25 0x17059 +- >; +- }; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x79 +- MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79 +- MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x79 +- MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x79 +- MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79 +- MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79 +- MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79 +- MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79 +- MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79 +- MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79 +- MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79 +- MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79 +- MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79 +- MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79 +- MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79 +- MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79 +- MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79 +- MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79 +- MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79 +- MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79 +- MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79 +- MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79 +- MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79 +- MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79 +- MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79 +- MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 +- MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 +- MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 +- MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79 +- MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79 +- MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79 +- MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 +- MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x79 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 +- MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 +- >; +- }; +- +- pinctrl_i2c1_sleep: i2c1grp-sleep { +- fsl,pins = < +- MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 +- MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 +- MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 +- >; +- }; +- +- pinctrl_i2c2_sleep: i2c2grp-sleep { +- fsl,pins = < +- MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 +- MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 +- MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 +- >; +- }; +- +- pinctrl_led: ledgrp { +- fsl,pins = < +- MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x17059 +- >; +- }; +- +- pinctrl_ricoh_gpio: ricoh_gpiogrp { +- fsl,pins = < +- MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ +- MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ +- MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 +- MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1 +- MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg1: usbotg1grp { +- fsl,pins = < +- MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059 +- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { +- fsl,pins = < +- MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 +- MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9 +- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 +- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 +- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 +- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { +- fsl,pins = < +- MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 +- MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9 +- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 +- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 +- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 +- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 +- >; +- }; +- +- pinctrl_usdhc2_sleep: usdhc2grp-sleep { +- fsl,pins = < +- MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 +- MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 +- MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9 +- MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9 +- MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9 +- MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 +- MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 +- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 +- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 +- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 +- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { +- fsl,pins = < +- MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 +- MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 +- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 +- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 +- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 +- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { +- fsl,pins = < +- MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 +- MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 +- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 +- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 +- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 +- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 +- >; +- }; +- +- pinctrl_usdhc3_sleep: usdhc3grp-sleep { +- fsl,pins = < +- MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 +- MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 +- MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 +- MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 +- MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 +- MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 +- >; +- }; +- +- pinctrl_wifi_power: wifi-powergrp { +- fsl,pins = < +- MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ +- >; +- }; +- +- pinctrl_wifi_reset: wifi-resetgrp { +- fsl,pins = < +- MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ +- >; +- }; +- +- pinctrl_zforce: zforcegrp { +- fsl,pins = < +- MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x17059 /* TP_INT */ +- MX6SL_PAD_SD1_DAT5__GPIO5_IO09 0x10059 /* TP_RST */ +- >; +- }; +-}; +- +-®_vdd1p1 { +- vin-supply = <&dcdc2_reg>; +-}; +- +-®_vdd2p5 { +- vin-supply = <&dcdc2_reg>; +-}; +- +-®_arm { +- vin-supply = <&dcdc3_reg>; +-}; +- +-®_soc { +- vin-supply = <&dcdc1_reg>; +-}; +- +-®_pu { +- vin-supply = <&dcdc1_reg>; +-}; +- +-&snvs_rtc { +- /* +- * We are using the RTC in the PMIC, but this one is not disabled +- * in imx6sl.dtsi. +- */ +- status = "disabled"; +-}; +- +-&uart1 { +- /* J4, through-holes */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart4 { +- /* TP198, next to J4, SMD pads */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>; +- pinctrl-3 = <&pinctrl_usdhc2_sleep>; +- non-removable; +- status = "okay"; +- +- /* internal uSD card */ +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- pinctrl-3 = <&pinctrl_usdhc3_sleep>; +- vmmc-supply = <®_wifi>; +- mmc-pwrseq = <&wifi_pwrseq>; +- cap-power-off-card; +- non-removable; +- status = "okay"; +- +- /* +- * 37NB-E60QF0+4A2: CyberTan WC121 (BCM43362) SDIO WiFi +- * 37NB-E60QF0+4A3: RTL8189F SDIO WiFi +- */ +-}; +- +-&usbotg1 { +- pinctrl-names = "default"; +- disable-over-current; +- srp-disable; +- hnp-disable; +- adp-disable; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sl-tolino-shine3.dts b/scripts/dtc/include-prefixes/arm/imx6sl-tolino-shine3.dts +deleted file mode 100644 +index e3f1e8d79528..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sl-tolino-shine3.dts ++++ /dev/null +@@ -1,333 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0) +-/* +- * Device tree for the Tolino Shine 3 ebook reader +- * +- * Name on mainboard is: 37NB-E60K00+4A4 +- * Serials start with: E60K02 (a number also seen in +- * vendor kernel sources) +- * +- * This mainboard seems to be equipped with different SoCs. +- * In the Toline Shine 3 ebook reader it is a i.MX6SL +- * +- * Copyright 2019 Andreas Kemnade +- * based on works +- * Copyright 2016 Freescale Semiconductor, Inc. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "imx6sl.dtsi" +-#include "e60k02.dtsi" +- +-/ { +- model = "Tolino Shine 3"; +- compatible = "kobo,tolino-shine3", "fsl,imx6sl"; +-}; +- +-&gpio_keys { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +-}; +- +-&i2c1 { +- pinctrl-names = "default","sleep"; +- pinctrl-0 = <&pinctrl_i2c1>; +- pinctrl-1 = <&pinctrl_i2c1_sleep>; +-}; +- +-&i2c2 { +- pinctrl-names = "default","sleep"; +- pinctrl-0 = <&pinctrl_i2c2>; +- pinctrl-1 = <&pinctrl_i2c2_sleep>; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_gpio_keys: gpio-keysgrp { +- fsl,pins = < +- MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 /* PWR_SW */ +- MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059 /* HALL_EN */ +- >; +- }; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x79 +- MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79 +- MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x79 +- MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x79 +- MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79 +- MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79 +- MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79 +- MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79 +- MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79 +- MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79 +- MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79 +- MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79 +- MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79 +- MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79 +- MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79 +- MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79 +- MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79 +- MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79 +- MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79 +- MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79 +- MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79 +- MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79 +- MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79 +- MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79 +- MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79 +- MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 +- MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 +- MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 +- MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79 +- MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79 +- MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79 +- MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 +- MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x79 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 +- MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 +- >; +- }; +- +- pinctrl_i2c1_sleep: i2c1grp-sleep { +- fsl,pins = < +- MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 +- MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 +- MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 +- >; +- }; +- +- pinctrl_i2c2_sleep: i2c2grp-sleep { +- fsl,pins = < +- MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 +- MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 +- MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 +- >; +- }; +- +- pinctrl_led: ledgrp { +- fsl,pins = < +- MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x17059 +- >; +- }; +- +- pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { +- fsl,pins = < +- MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 /* HWEN */ +- >; +- }; +- +- pinctrl_ricoh_gpio: ricoh_gpiogrp { +- fsl,pins = < +- MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ +- MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ +- MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 +- MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1 +- MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg1: usbotg1grp { +- fsl,pins = < +- MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059 +- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 +- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 +- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 +- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { +- fsl,pins = < +- MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 +- MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9 +- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 +- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 +- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 +- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { +- fsl,pins = < +- MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 +- MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9 +- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 +- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 +- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 +- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 +- >; +- }; +- +- pinctrl_usdhc2_sleep: usdhc2grp-sleep { +- fsl,pins = < +- MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 +- MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 +- MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9 +- MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9 +- MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9 +- MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 +- MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 +- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 +- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 +- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 +- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { +- fsl,pins = < +- MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 +- MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 +- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 +- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 +- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 +- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { +- fsl,pins = < +- MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 +- MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 +- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 +- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 +- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 +- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 +- >; +- }; +- +- pinctrl_usdhc3_sleep: usdhc3grp-sleep { +- fsl,pins = < +- MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 +- MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 +- MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 +- MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 +- MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 +- MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 +- >; +- }; +- +- pinctrl_wifi_power: wifi-powergrp { +- fsl,pins = < +- MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ +- >; +- }; +- +- pinctrl_wifi_reset: wifi-resetgrp { +- fsl,pins = < +- MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ +- >; +- }; +-}; +- +-&leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led>; +-}; +- +-&lm3630a { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; +-}; +- +-®_wifi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wifi_power>; +-}; +- +-®_vdd1p1 { +- vin-supply = <&dcdc2_reg>; +-}; +- +-®_vdd2p5 { +- vin-supply = <&dcdc2_reg>; +-}; +- +-&ricoh619 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ricoh_gpio>; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +-}; +- +-&usdhc2 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>; +- pinctrl-3 = <&pinctrl_usdhc2_sleep>; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- pinctrl-3 = <&pinctrl_usdhc3_sleep>; +-}; +- +-&wifi_pwrseq { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wifi_reset>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sl-warp.dts b/scripts/dtc/include-prefixes/arm/imx6sl-warp.dts +deleted file mode 100644 +index 9d7c8884892a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sl-warp.dts ++++ /dev/null +@@ -1,234 +0,0 @@ +-/* +- * Copyright 2014, 2015 O.S. Systems Software LTDA. +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include +-#include "imx6sl.dtsi" +- +-/ { +- model = "Revotics WaRP Board"; +- compatible = "revotics,imx6sl-warp", "fsl,imx6sl"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +- +- usdhc3_pwrseq: usdhc3_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ +- <&gpio4 7 GPIO_ACTIVE_LOW>, /* WL_HOSTWAKE */ +- <&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */ +- <&gpio3 27 GPIO_ACTIVE_LOW>, /* BT_HOSTWAKE */ +- <&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */ +- <&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */ +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbotg1 { +- dr_mode = "peripheral"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- bus-width = <4>; +- non-removable; +- keep-power-in-suspend; +- wakeup-source; +- mmc-pwrseq = <&usdhc3_pwrseq>; +- status = "okay"; +-}; +- +-&iomuxc { +- imx6sl-warp { +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x41b0b1 +- MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x41b0b1 +- >; +- }; +- +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x41b0b1 +- MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x41b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x41b0b1 +- MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x41b0b1 +- MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x4130b1 +- MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x4130b1 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059 +- MX6SL_PAD_SD2_CLK__SD2_CLK 0x410059 +- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x417059 +- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x417059 +- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x417059 +- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x417059 +- MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x417059 +- MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059 +- MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059 +- MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059 +- MX6SL_PAD_SD2_RST__SD2_RESET 0x417059 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2grp100mhz { +- fsl,pins = < +- MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170b9 +- MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100b9 +- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170b9 +- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170b9 +- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170b9 +- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170b9 +- MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170b9 +- MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9 +- MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9 +- MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9 +- MX6SL_PAD_SD2_RST__SD2_RESET 0x4170b9 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2grp200mhz { +- fsl,pins = < +- MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170f9 +- MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100f9 +- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170f9 +- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170f9 +- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170f9 +- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170f9 +- MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170f9 +- MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9 +- MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9 +- MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9 +- MX6SL_PAD_SD2_RST__SD2_RESET 0x4170f9 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6SL_PAD_SD3_CMD__SD3_CMD 0x417059 +- MX6SL_PAD_SD3_CLK__SD3_CLK 0x410059 +- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x417059 +- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x417059 +- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x417059 +- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x417059 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp100mhz { +- fsl,pins = < +- MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170b9 +- MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100b9 +- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170b9 +- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170b9 +- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170b9 +- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170b9 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp200mhz { +- fsl,pins = < +- MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170f9 +- MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100f9 +- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170f9 +- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170f9 +- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170f9 +- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170f9 +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sl.dtsi b/scripts/dtc/include-prefixes/arm/imx6sl.dtsi +deleted file mode 100644 +index 997b96c1c47b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sl.dtsi ++++ /dev/null +@@ -1,1007 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright 2013 Freescale Semiconductor, Inc. +- +-#include +-#include "imx6sl-pinfunc.h" +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * The decompressor and also some bootloaders rely on a +- * pre-existing /chosen node to be available to insert the +- * command line and merge other ATAGS info. +- */ +- chosen {}; +- +- aliases { +- ethernet0 = &fec; +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- gpio3 = &gpio4; +- gpio4 = &gpio5; +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- mmc0 = &usdhc1; +- mmc1 = &usdhc2; +- mmc2 = &usdhc3; +- mmc3 = &usdhc4; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- serial4 = &uart5; +- spi0 = &ecspi1; +- spi1 = &ecspi2; +- spi2 = &ecspi3; +- spi3 = &ecspi4; +- usb0 = &usbotg1; +- usb1 = &usbotg2; +- usb2 = &usbh; +- usbphy0 = &usbphy1; +- usbphy1 = &usbphy2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <0x0>; +- next-level-cache = <&L2>; +- operating-points = < +- /* kHz uV */ +- 996000 1275000 +- 792000 1175000 +- 396000 975000 +- >; +- fsl,soc-operating-points = < +- /* ARM kHz SOC-PU uV */ +- 996000 1225000 +- 792000 1175000 +- 396000 1175000 +- >; +- clock-latency = <61036>; /* two CLK32 periods */ +- #cooling-cells = <2>; +- clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, +- <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, +- <&clks IMX6SL_CLK_PLL1_SYS>; +- clock-names = "arm", "pll2_pfd2_396m", "step", +- "pll1_sw", "pll1_sys"; +- arm-supply = <®_arm>; +- pu-supply = <®_pu>; +- soc-supply = <®_soc>; +- nvmem-cells = <&cpu_speed_grade>; +- nvmem-cell-names = "speed_grade"; +- }; +- }; +- +- clocks { +- ckil { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupt-parent = <&gpc>; +- interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- usbphynop1: usbphynop1 { +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&gpc>; +- ranges; +- +- ocram: sram@900000 { +- compatible = "mmio-sram"; +- reg = <0x00900000 0x20000>; +- clocks = <&clks IMX6SL_CLK_OCRAM>; +- }; +- +- intc: interrupt-controller@a01000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x00a01000 0x1000>, +- <0x00a00100 0x100>; +- interrupt-parent = <&intc>; +- }; +- +- L2: cache-controller@a02000 { +- compatible = "arm,pl310-cache"; +- reg = <0x00a02000 0x1000>; +- interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; +- cache-unified; +- cache-level = <2>; +- arm,tag-latency = <4 2 3>; +- arm,data-latency = <4 2 3>; +- }; +- +- aips1: bus@2000000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x02000000 0x100000>; +- ranges; +- +- spba: spba-bus@2000000 { +- compatible = "fsl,spba-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x02000000 0x40000>; +- ranges; +- +- spdif: spdif@2004000 { +- compatible = "fsl,imx6sl-spdif", +- "fsl,imx35-spdif"; +- reg = <0x02004000 0x4000>; +- interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; +- dmas = <&sdma 14 18 0>, +- <&sdma 15 18 0>; +- dma-names = "rx", "tx"; +- clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>, +- <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>, +- <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>, +- <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>, +- <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>; +- clock-names = "core", "rxtx0", +- "rxtx1", "rxtx2", +- "rxtx3", "rxtx4", +- "rxtx5", "rxtx6", +- "rxtx7", "spba"; +- status = "disabled"; +- }; +- +- ecspi1: spi@2008000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; +- reg = <0x02008000 0x4000>; +- interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_ECSPI1>, +- <&clks IMX6SL_CLK_ECSPI1>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- ecspi2: spi@200c000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; +- reg = <0x0200c000 0x4000>; +- interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_ECSPI2>, +- <&clks IMX6SL_CLK_ECSPI2>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- ecspi3: spi@2010000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; +- reg = <0x02010000 0x4000>; +- interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_ECSPI3>, +- <&clks IMX6SL_CLK_ECSPI3>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- ecspi4: spi@2014000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; +- reg = <0x02014000 0x4000>; +- interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_ECSPI4>, +- <&clks IMX6SL_CLK_ECSPI4>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart5: serial@2018000 { +- compatible = "fsl,imx6sl-uart", +- "fsl,imx6q-uart", "fsl,imx21-uart"; +- reg = <0x02018000 0x4000>; +- interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_UART>, +- <&clks IMX6SL_CLK_UART_SERIAL>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart1: serial@2020000 { +- compatible = "fsl,imx6sl-uart", +- "fsl,imx6q-uart", "fsl,imx21-uart"; +- reg = <0x02020000 0x4000>; +- interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_UART>, +- <&clks IMX6SL_CLK_UART_SERIAL>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart2: serial@2024000 { +- compatible = "fsl,imx6sl-uart", +- "fsl,imx6q-uart", "fsl,imx21-uart"; +- reg = <0x02024000 0x4000>; +- interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_UART>, +- <&clks IMX6SL_CLK_UART_SERIAL>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ssi1: ssi@2028000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx6sl-ssi", +- "fsl,imx51-ssi"; +- reg = <0x02028000 0x4000>; +- interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_SSI1_IPG>, +- <&clks IMX6SL_CLK_SSI1>; +- clock-names = "ipg", "baud"; +- dmas = <&sdma 37 1 0>, +- <&sdma 38 1 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- ssi2: ssi@202c000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx6sl-ssi", +- "fsl,imx51-ssi"; +- reg = <0x0202c000 0x4000>; +- interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_SSI2_IPG>, +- <&clks IMX6SL_CLK_SSI2>; +- clock-names = "ipg", "baud"; +- dmas = <&sdma 41 1 0>, +- <&sdma 42 1 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- ssi3: ssi@2030000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx6sl-ssi", +- "fsl,imx51-ssi"; +- reg = <0x02030000 0x4000>; +- interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_SSI3_IPG>, +- <&clks IMX6SL_CLK_SSI3>; +- clock-names = "ipg", "baud"; +- dmas = <&sdma 45 1 0>, +- <&sdma 46 1 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- uart3: serial@2034000 { +- compatible = "fsl,imx6sl-uart", +- "fsl,imx6q-uart", "fsl,imx21-uart"; +- reg = <0x02034000 0x4000>; +- interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_UART>, +- <&clks IMX6SL_CLK_UART_SERIAL>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart4: serial@2038000 { +- compatible = "fsl,imx6sl-uart", +- "fsl,imx6q-uart", "fsl,imx21-uart"; +- reg = <0x02038000 0x4000>; +- interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_UART>, +- <&clks IMX6SL_CLK_UART_SERIAL>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- }; +- +- pwm1: pwm@2080000 { +- #pwm-cells = <3>; +- compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; +- reg = <0x02080000 0x4000>; +- interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_PERCLK>, +- <&clks IMX6SL_CLK_PWM1>; +- clock-names = "ipg", "per"; +- }; +- +- pwm2: pwm@2084000 { +- #pwm-cells = <3>; +- compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; +- reg = <0x02084000 0x4000>; +- interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_PERCLK>, +- <&clks IMX6SL_CLK_PWM2>; +- clock-names = "ipg", "per"; +- }; +- +- pwm3: pwm@2088000 { +- #pwm-cells = <3>; +- compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; +- reg = <0x02088000 0x4000>; +- interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_PERCLK>, +- <&clks IMX6SL_CLK_PWM3>; +- clock-names = "ipg", "per"; +- }; +- +- pwm4: pwm@208c000 { +- #pwm-cells = <3>; +- compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; +- reg = <0x0208c000 0x4000>; +- interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_PERCLK>, +- <&clks IMX6SL_CLK_PWM4>; +- clock-names = "ipg", "per"; +- }; +- +- gpt: timer@2098000 { +- compatible = "fsl,imx6sl-gpt"; +- reg = <0x02098000 0x4000>; +- interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_GPT>, +- <&clks IMX6SL_CLK_GPT_SERIAL>; +- clock-names = "ipg", "per"; +- }; +- +- gpio1: gpio@209c000 { +- compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; +- reg = <0x0209c000 0x4000>; +- interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, +- <0 67 IRQ_TYPE_LEVEL_HIGH>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>, +- <&iomuxc 3 23 1>, <&iomuxc 4 25 1>, +- <&iomuxc 5 24 1>, <&iomuxc 6 19 1>, +- <&iomuxc 7 36 2>, <&iomuxc 9 44 8>, +- <&iomuxc 17 38 6>, <&iomuxc 23 68 4>, +- <&iomuxc 27 64 4>, <&iomuxc 31 52 1>; +- }; +- +- gpio2: gpio@20a0000 { +- compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; +- reg = <0x020a0000 0x4000>; +- interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, +- <0 69 IRQ_TYPE_LEVEL_HIGH>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>, +- <&iomuxc 5 34 2>, <&iomuxc 7 57 4>, +- <&iomuxc 11 56 1>, <&iomuxc 12 61 3>, +- <&iomuxc 15 107 1>, <&iomuxc 16 132 2>, +- <&iomuxc 18 135 1>, <&iomuxc 19 134 1>, +- <&iomuxc 20 108 2>, <&iomuxc 22 120 1>, +- <&iomuxc 23 125 7>, <&iomuxc 30 110 2>; +- }; +- +- gpio3: gpio@20a4000 { +- compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; +- reg = <0x020a4000 0x4000>; +- interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, +- <0 71 IRQ_TYPE_LEVEL_HIGH>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>, +- <&iomuxc 12 97 4>, <&iomuxc 16 166 3>, +- <&iomuxc 19 85 2>, <&iomuxc 21 137 2>, +- <&iomuxc 23 136 1>, <&iomuxc 24 91 1>, +- <&iomuxc 25 99 1>, <&iomuxc 26 92 1>, +- <&iomuxc 27 100 1>, <&iomuxc 28 93 1>, +- <&iomuxc 29 101 1>, <&iomuxc 30 94 1>, +- <&iomuxc 31 102 1>; +- }; +- +- gpio4: gpio@20a8000 { +- compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; +- reg = <0x020a8000 0x4000>; +- interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, +- <0 73 IRQ_TYPE_LEVEL_HIGH>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>, +- <&iomuxc 2 96 1>, <&iomuxc 3 104 1>, +- <&iomuxc 4 97 1>, <&iomuxc 5 105 1>, +- <&iomuxc 6 98 1>, <&iomuxc 7 106 1>, +- <&iomuxc 8 28 1>, <&iomuxc 9 27 1>, +- <&iomuxc 10 26 1>, <&iomuxc 11 29 1>, +- <&iomuxc 12 32 1>, <&iomuxc 13 31 1>, +- <&iomuxc 14 30 1>, <&iomuxc 15 33 1>, +- <&iomuxc 16 84 1>, <&iomuxc 17 79 2>, +- <&iomuxc 19 78 1>, <&iomuxc 20 76 1>, +- <&iomuxc 21 81 2>, <&iomuxc 23 75 1>, +- <&iomuxc 24 83 1>, <&iomuxc 25 74 1>, +- <&iomuxc 26 77 1>, <&iomuxc 27 159 1>, +- <&iomuxc 28 154 1>, <&iomuxc 29 157 1>, +- <&iomuxc 30 152 1>, <&iomuxc 31 156 1>; +- }; +- +- gpio5: gpio@20ac000 { +- compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; +- reg = <0x020ac000 0x4000>; +- interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, +- <0 75 IRQ_TYPE_LEVEL_HIGH>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>, +- <&iomuxc 2 155 1>, <&iomuxc 3 153 1>, +- <&iomuxc 4 150 1>, <&iomuxc 5 149 1>, +- <&iomuxc 6 144 1>, <&iomuxc 7 147 1>, +- <&iomuxc 8 142 1>, <&iomuxc 9 146 1>, +- <&iomuxc 10 148 1>, <&iomuxc 11 141 1>, +- <&iomuxc 12 145 1>, <&iomuxc 13 143 1>, +- <&iomuxc 14 140 1>, <&iomuxc 15 139 1>, +- <&iomuxc 16 164 2>, <&iomuxc 18 160 1>, +- <&iomuxc 19 162 1>, <&iomuxc 20 163 1>, +- <&iomuxc 21 161 1>; +- }; +- +- kpp: keypad@20b8000 { +- compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp"; +- reg = <0x020b8000 0x4000>; +- interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_IPG>; +- status = "disabled"; +- }; +- +- wdog1: watchdog@20bc000 { +- compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; +- reg = <0x020bc000 0x4000>; +- interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_IPG>; +- }; +- +- wdog2: watchdog@20c0000 { +- compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; +- reg = <0x020c0000 0x4000>; +- interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_IPG>; +- status = "disabled"; +- }; +- +- clks: clock-controller@20c4000 { +- compatible = "fsl,imx6sl-ccm"; +- reg = <0x020c4000 0x4000>; +- interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, +- <0 88 IRQ_TYPE_LEVEL_HIGH>; +- #clock-cells = <1>; +- }; +- +- anatop: anatop@20c8000 { +- compatible = "fsl,imx6sl-anatop", +- "fsl,imx6q-anatop", +- "syscon", "simple-mfd"; +- reg = <0x020c8000 0x1000>; +- interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, +- <0 54 IRQ_TYPE_LEVEL_HIGH>, +- <0 127 IRQ_TYPE_LEVEL_HIGH>; +- +- reg_vdd1p1: regulator-1p1 { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vdd1p1"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- anatop-reg-offset = <0x110>; +- anatop-vol-bit-shift = <8>; +- anatop-vol-bit-width = <5>; +- anatop-min-bit-val = <4>; +- anatop-min-voltage = <800000>; +- anatop-max-voltage = <1375000>; +- anatop-enable-bit = <0>; +- }; +- +- reg_vdd3p0: regulator-3p0 { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vdd3p0"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <3150000>; +- regulator-always-on; +- anatop-reg-offset = <0x120>; +- anatop-vol-bit-shift = <8>; +- anatop-vol-bit-width = <5>; +- anatop-min-bit-val = <0>; +- anatop-min-voltage = <2625000>; +- anatop-max-voltage = <3400000>; +- anatop-enable-bit = <0>; +- }; +- +- reg_vdd2p5: regulator-2p5 { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vdd2p5"; +- regulator-min-microvolt = <2250000>; +- regulator-max-microvolt = <2750000>; +- regulator-always-on; +- anatop-reg-offset = <0x130>; +- anatop-vol-bit-shift = <8>; +- anatop-vol-bit-width = <5>; +- anatop-min-bit-val = <0>; +- anatop-min-voltage = <2100000>; +- anatop-max-voltage = <2850000>; +- anatop-enable-bit = <0>; +- }; +- +- reg_arm: regulator-vddcore { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vddarm"; +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1450000>; +- regulator-always-on; +- anatop-reg-offset = <0x140>; +- anatop-vol-bit-shift = <0>; +- anatop-vol-bit-width = <5>; +- anatop-delay-reg-offset = <0x170>; +- anatop-delay-bit-shift = <24>; +- anatop-delay-bit-width = <2>; +- anatop-min-bit-val = <1>; +- anatop-min-voltage = <725000>; +- anatop-max-voltage = <1450000>; +- }; +- +- reg_pu: regulator-vddpu { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vddpu"; +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1450000>; +- anatop-reg-offset = <0x140>; +- anatop-vol-bit-shift = <9>; +- anatop-vol-bit-width = <5>; +- anatop-delay-reg-offset = <0x170>; +- anatop-delay-bit-shift = <26>; +- anatop-delay-bit-width = <2>; +- anatop-min-bit-val = <1>; +- anatop-min-voltage = <725000>; +- anatop-max-voltage = <1450000>; +- }; +- +- reg_soc: regulator-vddsoc { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vddsoc"; +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1450000>; +- regulator-always-on; +- anatop-reg-offset = <0x140>; +- anatop-vol-bit-shift = <18>; +- anatop-vol-bit-width = <5>; +- anatop-delay-reg-offset = <0x170>; +- anatop-delay-bit-shift = <28>; +- anatop-delay-bit-width = <2>; +- anatop-min-bit-val = <1>; +- anatop-min-voltage = <725000>; +- anatop-max-voltage = <1450000>; +- }; +- +- tempmon: tempmon { +- compatible = "fsl,imx6q-tempmon"; +- interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&gpc>; +- fsl,tempmon = <&anatop>; +- nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; +- nvmem-cell-names = "calib", "temp_grade"; +- clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; +- }; +- }; +- +- usbphy1: usbphy@20c9000 { +- compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; +- reg = <0x020c9000 0x1000>; +- interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_USBPHY1>; +- fsl,anatop = <&anatop>; +- }; +- +- usbphy2: usbphy@20ca000 { +- compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; +- reg = <0x020ca000 0x1000>; +- interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_USBPHY2>; +- fsl,anatop = <&anatop>; +- }; +- +- snvs: snvs@20cc000 { +- compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; +- reg = <0x020cc000 0x4000>; +- +- snvs_rtc: snvs-rtc-lp { +- compatible = "fsl,sec-v4.0-mon-rtc-lp"; +- regmap = <&snvs>; +- offset = <0x34>; +- interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, +- <0 20 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- snvs_poweroff: snvs-poweroff { +- compatible = "syscon-poweroff"; +- regmap = <&snvs>; +- offset = <0x38>; +- value = <0x60>; +- mask = <0x60>; +- status = "disabled"; +- }; +- }; +- +- epit1: epit@20d0000 { +- reg = <0x020d0000 0x4000>; +- interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- epit2: epit@20d4000 { +- reg = <0x020d4000 0x4000>; +- interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- src: reset-controller@20d8000 { +- compatible = "fsl,imx6sl-src", "fsl,imx51-src"; +- reg = <0x020d8000 0x4000>; +- interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, +- <0 96 IRQ_TYPE_LEVEL_HIGH>; +- #reset-cells = <1>; +- }; +- +- gpc: gpc@20dc000 { +- compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; +- reg = <0x020dc000 0x4000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&intc>; +- clocks = <&clks IMX6SL_CLK_IPG>; +- clock-names = "ipg"; +- +- pgc { +- #address-cells = <1>; +- #size-cells = <0>; +- +- power-domain@0 { +- reg = <0>; +- #power-domain-cells = <0>; +- }; +- +- pd_pu: power-domain@1 { +- reg = <1>; +- #power-domain-cells = <0>; +- power-supply = <®_pu>; +- clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, +- <&clks IMX6SL_CLK_GPU2D_PODF>; +- }; +- +- pd_disp: power-domain@2 { +- reg = <2>; +- #power-domain-cells = <0>; +- clocks = <&clks IMX6SL_CLK_LCDIF_AXI>, +- <&clks IMX6SL_CLK_LCDIF_PIX>, +- <&clks IMX6SL_CLK_EPDC_AXI>, +- <&clks IMX6SL_CLK_EPDC_PIX>, +- <&clks IMX6SL_CLK_PXP_AXI>; +- }; +- }; +- }; +- +- gpr: iomuxc-gpr@20e0000 { +- compatible = "fsl,imx6sl-iomuxc-gpr", +- "fsl,imx6q-iomuxc-gpr", "syscon"; +- reg = <0x020e0000 0x38>; +- }; +- +- iomuxc: pinctrl@20e0000 { +- compatible = "fsl,imx6sl-iomuxc"; +- reg = <0x020e0000 0x4000>; +- }; +- +- csi: csi@20e4000 { +- reg = <0x020e4000 0x4000>; +- interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- spdc: spdc@20e8000 { +- reg = <0x020e8000 0x4000>; +- interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- sdma: sdma@20ec000 { +- compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma"; +- reg = <0x020ec000 0x4000>; +- interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_SDMA>, +- <&clks IMX6SL_CLK_AHB>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- /* imx6sl reuses imx6q sdma firmware */ +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; +- }; +- +- pxp: pxp@20f0000 { +- reg = <0x020f0000 0x4000>; +- interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- epdc: epdc@20f4000 { +- reg = <0x020f4000 0x4000>; +- interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- lcdif: lcdif@20f8000 { +- compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif"; +- reg = <0x020f8000 0x4000>; +- interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_LCDIF_PIX>, +- <&clks IMX6SL_CLK_LCDIF_AXI>, +- <&clks IMX6SL_CLK_DUMMY>; +- clock-names = "pix", "axi", "disp_axi"; +- status = "disabled"; +- power-domains = <&pd_disp>; +- }; +- +- dcp: crypto@20fc000 { +- compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp"; +- reg = <0x020fc000 0x4000>; +- interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>, +- <0 100 IRQ_TYPE_LEVEL_HIGH>, +- <0 101 IRQ_TYPE_LEVEL_HIGH>; +- }; +- }; +- +- aips2: bus@2100000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x02100000 0x100000>; +- ranges; +- +- usbotg1: usb@2184000 { +- compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; +- reg = <0x02184000 0x200>; +- interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_USBOH3>; +- fsl,usbphy = <&usbphy1>; +- fsl,usbmisc = <&usbmisc 0>; +- ahb-burst-config = <0x0>; +- tx-burst-size-dword = <0x10>; +- rx-burst-size-dword = <0x10>; +- status = "disabled"; +- }; +- +- usbotg2: usb@2184200 { +- compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; +- reg = <0x02184200 0x200>; +- interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_USBOH3>; +- fsl,usbphy = <&usbphy2>; +- fsl,usbmisc = <&usbmisc 1>; +- ahb-burst-config = <0x0>; +- tx-burst-size-dword = <0x10>; +- rx-burst-size-dword = <0x10>; +- status = "disabled"; +- }; +- +- usbh: usb@2184400 { +- compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; +- reg = <0x02184400 0x200>; +- interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_USBOH3>; +- fsl,usbphy = <&usbphynop1>; +- phy_type = "hsic"; +- fsl,usbmisc = <&usbmisc 2>; +- dr_mode = "host"; +- ahb-burst-config = <0x0>; +- tx-burst-size-dword = <0x10>; +- rx-burst-size-dword = <0x10>; +- status = "disabled"; +- }; +- +- usbmisc: usbmisc@2184800 { +- #index-cells = <1>; +- compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc"; +- reg = <0x02184800 0x200>; +- clocks = <&clks IMX6SL_CLK_USBOH3>; +- }; +- +- fec: ethernet@2188000 { +- compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; +- reg = <0x02188000 0x4000>; +- interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_ENET>, +- <&clks IMX6SL_CLK_ENET_REF>; +- clock-names = "ipg", "ahb"; +- status = "disabled"; +- }; +- +- usdhc1: mmc@2190000 { +- compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; +- reg = <0x02190000 0x4000>; +- interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_USDHC1>, +- <&clks IMX6SL_CLK_USDHC1>, +- <&clks IMX6SL_CLK_USDHC1>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usdhc2: mmc@2194000 { +- compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; +- reg = <0x02194000 0x4000>; +- interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_USDHC2>, +- <&clks IMX6SL_CLK_USDHC2>, +- <&clks IMX6SL_CLK_USDHC2>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usdhc3: mmc@2198000 { +- compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; +- reg = <0x02198000 0x4000>; +- interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_USDHC3>, +- <&clks IMX6SL_CLK_USDHC3>, +- <&clks IMX6SL_CLK_USDHC3>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usdhc4: mmc@219c000 { +- compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; +- reg = <0x0219c000 0x4000>; +- interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_USDHC4>, +- <&clks IMX6SL_CLK_USDHC4>, +- <&clks IMX6SL_CLK_USDHC4>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- i2c1: i2c@21a0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; +- reg = <0x021a0000 0x4000>; +- interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_I2C1>; +- status = "disabled"; +- }; +- +- i2c2: i2c@21a4000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; +- reg = <0x021a4000 0x4000>; +- interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_I2C2>; +- status = "disabled"; +- }; +- +- i2c3: i2c@21a8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; +- reg = <0x021a8000 0x4000>; +- interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_I2C3>; +- status = "disabled"; +- }; +- +- memory-controller@21b0000 { +- compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; +- reg = <0x021b0000 0x4000>; +- clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>; +- }; +- +- rngb: rngb@21b4000 { +- compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb"; +- reg = <0x021b4000 0x4000>; +- interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_DUMMY>; +- }; +- +- weim: weim@21b8000 { +- #address-cells = <2>; +- #size-cells = <1>; +- reg = <0x021b8000 0x4000>; +- interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; +- fsl,weim-cs-gpr = <&gpr>; +- status = "disabled"; +- }; +- +- ocotp: efuse@21bc000 { +- compatible = "fsl,imx6sl-ocotp", "syscon"; +- reg = <0x021bc000 0x4000>; +- clocks = <&clks IMX6SL_CLK_OCOTP>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpu_speed_grade: speed-grade@10 { +- reg = <0x10 4>; +- }; +- +- tempmon_calib: calib@38 { +- reg = <0x38 4>; +- }; +- +- tempmon_temp_grade: temp-grade@20 { +- reg = <0x20 4>; +- }; +- }; +- +- audmux: audmux@21d8000 { +- compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux"; +- reg = <0x021d8000 0x4000>; +- status = "disabled"; +- }; +- }; +- +- gpu_2d: gpu@2200000 { +- compatible = "vivante,gc"; +- reg = <0x02200000 0x4000>; +- interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, +- <&clks IMX6SL_CLK_GPU2D_OVG>; +- clock-names = "bus", "core"; +- power-domains = <&pd_pu>; +- }; +- +- gpu_vg: gpu@2204000 { +- compatible = "vivante,gc"; +- reg = <0x02204000 0x4000>; +- interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, +- <&clks IMX6SL_CLK_GPU2D_OVG>; +- clock-names = "bus", "core"; +- power-domains = <&pd_pu>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sll-evk.dts b/scripts/dtc/include-prefixes/arm/imx6sll-evk.dts +deleted file mode 100644 +index 32b3d82fec53..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sll-evk.dts ++++ /dev/null +@@ -1,576 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2016 Freescale Semiconductor, Inc. +- * Copyright 2017-2018 NXP. +- * +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "imx6sll.dtsi" +- +-/ { +- model = "Freescale i.MX6SLL EVK Board"; +- compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x80000000>; +- }; +- +- backlight_display: backlight-display { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- status = "okay"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led>; +- +- user { +- label = "debug"; +- gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- reg_usb_otg1_vbus: regulator-otg1-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_otg1_vbus>; +- regulator-name = "usb_otg1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_otg2_vbus: regulator-otg2-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_otg2_vbus>; +- regulator-name = "usb_otg2_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_aud3v: regulator-aud3v { +- compatible = "regulator-fixed"; +- regulator-name = "wm8962-supply-3v15"; +- regulator-min-microvolt = <3150000>; +- regulator-max-microvolt = <3150000>; +- regulator-boot-on; +- }; +- +- reg_aud4v: regulator-aud4v { +- compatible = "regulator-fixed"; +- regulator-name = "wm8962-supply-4v2"; +- regulator-min-microvolt = <4325000>; +- regulator-max-microvolt = <4325000>; +- regulator-boot-on; +- }; +- +- reg_lcd_3v3: regulator-lcd-3v3 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_lcd_3v3>; +- regulator-name = "lcd-3v3"; +- gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_lcd_5v: regulator-lcd-5v { +- compatible = "regulator-fixed"; +- regulator-name = "lcd-5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_sd1_vmmc: regulator-sd1-vmmc { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_sd1_vmmc>; +- regulator-name = "SD1_SPWR"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_sd3_vmmc: regulator-sd3-vmmc { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_sd3_vmmc>; +- regulator-name = "SD3_WIFI"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- panel { +- compatible = "sii,43wvf1g"; +- backlight = <&backlight_display>; +- dvdd-supply = <®_lcd_3v3>; +- avdd-supply = <®_lcd_5v>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +- +- sound { +- compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hp>; +- model = "wm8962-audio"; +- audio-cpu = <&ssi2>; +- audio-codec = <&wm8962>; +- audio-routing = +- "Headphone Jack", "HPOUTL", +- "Headphone Jack", "HPOUTR", +- "Ext Spk", "SPKOUTL", +- "Ext Spk", "SPKOUTR", +- "AMIC", "MICBIAS", +- "IN3R", "AMIC"; +- mux-int-port = <2>; +- mux-ext-port = <3>; +- hp-det-gpio = <&gpio4 24 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux3>; +- status = "okay"; +-}; +- +-&cpu0 { +- arm-supply = <&sw1a_reg>; +- soc-supply = <&sw1c_reg>; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pfuze100: pmic@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- regulator-always-on; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- wm8962: audio-codec@1a { +- compatible = "wlf,wm8962"; +- reg = <0x1a>; +- clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>; +- DCVDD-supply = <&vgen3_reg>; +- DBVDD-supply = <®_aud3v>; +- AVDD-supply = <&vgen3_reg>; +- CPVDD-supply = <&vgen3_reg>; +- MICVDD-supply = <®_aud3v>; +- PLLVDD-supply = <&vgen3_reg>; +- SPKVDD1-supply = <®_aud4v>; +- SPKVDD2-supply = <®_aud4v>; +- }; +-}; +- +-&lcdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd>; +- status = "okay"; +- +- port { +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&snvs_poweroff { +- status = "okay"; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +- +-&ssi2 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; +- keep-power-in-suspend; +- wakeup-source; +- vmmc-supply = <®_sd1_vmmc>; +- status = "okay"; +-}; +- +-&usbotg1 { +- vbus-supply = <®_usb_otg1_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg1>; +- disable-over-current; +- srp-disable; +- hnp-disable; +- adp-disable; +- status = "okay"; +-}; +- +-&usbotg2 { +- vbus-supply = <®_usb_otg2_vbus>; +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; +- keep-power-in-suspend; +- wakeup-source; +- vmmc-supply = <®_sd3_vmmc>; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog1>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl_audmux3: audmux3grp { +- fsl,pins = < +- MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 +- MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 +- MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 +- MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 +- MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 +- >; +- }; +- +- pinctrl_hp: hpgrp { +- fsl,pins = < +- MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */ +- >; +- }; +- +- pinctrl_reg_sd3_vmmc: sd3vmmcgrp { +- fsl,pins = < +- MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 +- >; +- }; +- +- pinctrl_usb_otg1_vbus: vbus1grp { +- fsl,pins = < +- MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 +- >; +- }; +- +- pinctrl_usb_otg2_vbus: vbus2grp { +- fsl,pins = < +- MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 +- >; +- }; +- +- pinctrl_reg_lcd_3v3: reglcd3v3grp { +- fsl,pins = < +- MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 +- >; +- }; +- +- pinctrl_reg_sd1_vmmc: sd1vmmcgrp { +- fsl,pins = < +- MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 +- MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059 +- MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13059 +- MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059 +- MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059 +- MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059 +- MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { +- fsl,pins = < +- MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 +- MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9 +- MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9 +- MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9 +- MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9 +- MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { +- fsl,pins = < +- MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 +- MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9 +- MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9 +- MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9 +- MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9 +- MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9 +- >; +- }; +- +- pinctrl_usbotg1: usbotg1grp { +- fsl,pins = < +- MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17061 +- MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13061 +- MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17061 +- MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17061 +- MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17061 +- MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17061 +- MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { +- fsl,pins = < +- MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170a1 +- MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130a1 +- MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170a1 +- MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170a1 +- MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170a1 +- MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170a1 +- MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { +- fsl,pins = < +- MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170e9 +- MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9 +- MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170e9 +- MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170e9 +- MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170e9 +- MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170e9 +- MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 +- MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1 +- MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x4041b8b1 +- >; +- }; +- +- pinctrl_lcd: lcdgrp { +- fsl,pins = < +- MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79 +- MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79 +- MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79 +- MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79 +- MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79 +- MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79 +- MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79 +- MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79 +- MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79 +- MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79 +- MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79 +- MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79 +- MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79 +- MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79 +- MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79 +- MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79 +- MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79 +- MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79 +- MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79 +- MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79 +- MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79 +- MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79 +- MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79 +- MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79 +- MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79 +- MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79 +- MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79 +- MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79 +- MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79 +- >; +- }; +- +- pinctrl_led: ledgrp { +- fsl,pins = < +- MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x17059 +- >; +- }; +- +- pinctrl_pwm1: pmw1grp { +- fsl,pins = < +- MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 +- >; +- }; +- +- pinctrl_wdog1: wdog1grp { +- fsl,pins = < +- MX6SLL_PAD_WDOG_B__WDOG1_B 0x170b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sll-kobo-clarahd.dts b/scripts/dtc/include-prefixes/arm/imx6sll-kobo-clarahd.dts +deleted file mode 100644 +index 90b32f5eb529..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sll-kobo-clarahd.dts ++++ /dev/null +@@ -1,335 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0) +-/* +- * Device tree for the Kobo Clara HD ebook reader +- * +- * Name on mainboard is: 37NB-E60K00+4A4 +- * Serials start with: E60K02 (a number also seen in +- * vendor kernel sources) +- * +- * This mainboard seems to be equipped with different SoCs. +- * In the Kobo Clara HD ebook reader it is an i.MX6SLL +- * +- * Copyright 2019 Andreas Kemnade +- * based on works +- * Copyright 2016 Freescale Semiconductor, Inc. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "imx6sll.dtsi" +-#include "e60k02.dtsi" +- +-/ { +- model = "Kobo Clara HD"; +- compatible = "kobo,clarahd", "fsl,imx6sll"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>; +- assigned-clock-rates = <393216000>; +-}; +- +-&cpu0 { +- arm-supply = <&dcdc3_reg>; +- soc-supply = <&dcdc1_reg>; +-}; +- +-&gpio_keys { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +-}; +- +-&i2c1 { +- pinctrl-names = "default","sleep"; +- pinctrl-0 = <&pinctrl_i2c1>; +- pinctrl-1 = <&pinctrl_i2c1_sleep>; +-}; +- +-&i2c2 { +- pinctrl-names = "default","sleep"; +- pinctrl-0 = <&pinctrl_i2c2>; +- pinctrl-1 = <&pinctrl_i2c2_sleep>; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_gpio_keys: gpio-keysgrp { +- fsl,pins = < +- MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x17059 /* PWR_SW */ +- MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x17059 /* HALL_EN */ +- >; +- }; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x79 +- MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x79 +- MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x79 +- MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x79 +- MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x79 +- MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x79 +- MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x79 +- MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x79 +- MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x79 +- MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x79 +- MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x79 +- MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x79 +- MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x79 +- MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x79 +- MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x79 +- MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x79 +- MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x79 +- MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x79 +- MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x79 +- MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x79 +- MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x79 +- MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x79 +- MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x79 +- MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x79 +- MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x79 +- MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 +- MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 +- MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 +- MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x79 +- MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x79 +- MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x79 +- MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 +- MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x79 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 +- MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 +- >; +- }; +- +- pinctrl_i2c1_sleep: i2c1grp-sleep { +- fsl,pins = < +- MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 +- MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 +- MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 +- >; +- }; +- +- pinctrl_i2c2_sleep: i2c2grp-sleep { +- fsl,pins = < +- MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 +- MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 +- MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 +- >; +- }; +- +- pinctrl_led: ledgrp { +- fsl,pins = < +- MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x17059 +- >; +- }; +- +- pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { +- fsl,pins = < +- MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x10059 /* HWEN */ +- >; +- }; +- +- pinctrl_ricoh_gpio: ricoh-gpiogrp { +- fsl,pins = < +- MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ +- MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ +- MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 +- MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x1b0b1 +- MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg1: usbotg1grp { +- fsl,pins = < +- MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 +- MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 +- MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 +- MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 +- MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 +- MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { +- fsl,pins = < +- MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 +- MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 +- MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 +- MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 +- MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 +- MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { +- fsl,pins = < +- MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 +- MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 +- MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 +- MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 +- MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 +- MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 +- >; +- }; +- +- pinctrl_usdhc2_sleep: usdhc2grp-sleep { +- fsl,pins = < +- MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 +- MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 +- MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x100f9 +- MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x100f9 +- MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x100f9 +- MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x100f9 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6SLL_PAD_SD3_CMD__SD3_CMD 0x11059 +- MX6SLL_PAD_SD3_CLK__SD3_CLK 0x11059 +- MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x11059 +- MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x11059 +- MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x11059 +- MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x11059 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { +- fsl,pins = < +- MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 +- MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9 +- MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 +- MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 +- MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 +- MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { +- fsl,pins = < +- MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9 +- MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9 +- MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9 +- MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9 +- MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9 +- MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9 +- >; +- }; +- +- pinctrl_usdhc3_sleep: usdhc3grp-sleep { +- fsl,pins = < +- MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 +- MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 +- MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x100c1 +- MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x100c1 +- MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x100c1 +- MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x100c1 +- >; +- }; +- +- pinctrl_wifi_power: wifi-powergrp { +- fsl,pins = < +- MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ +- >; +- }; +- +- pinctrl_wifi_reset: wifi-resetgrp { +- fsl,pins = < +- MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x10059 /* WIFI_RST */ +- >; +- }; +-}; +- +-&leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led>; +-}; +- +-&lm3630a { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; +-}; +- +-®_wifi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wifi_power>; +-}; +- +-&ricoh619 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ricoh_gpio>; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +-}; +- +-&usdhc2 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>; +- pinctrl-3 = <&pinctrl_usdhc2_sleep>; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- pinctrl-3 = <&pinctrl_usdhc3_sleep>; +-}; +- +-&wifi_pwrseq { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wifi_reset>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sll-pinfunc.h b/scripts/dtc/include-prefixes/arm/imx6sll-pinfunc.h +deleted file mode 100644 +index 713a346f4c89..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sll-pinfunc.h ++++ /dev/null +@@ -1,880 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright 2016 Freescale Semiconductor, Inc. +- * Copyright 2017-2018 NXP. +- * +- */ +- +-#ifndef __DTS_IMX6SLL_PINFUNC_H +-#define __DTS_IMX6SLL_PINFUNC_H +- +-/* +- * The pin function ID is a tuple of +- * +- */ +-#define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0 +-#define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0 +-#define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0 +-#define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0 +-#define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0 +-#define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0 +-#define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0 +-#define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0 +-#define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0 +-#define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0 +-#define MX6SLL_PAD_REF_CLK_24M__SD3_WP 0x0018 0x02E0 0x0794 0x6 0x0 +-#define MX6SLL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x001C 0x02E4 0x0000 0x0 0x0 +-#define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x001C 0x02E4 0x0690 0x1 0x0 +-#define MX6SLL_PAD_REF_CLK_32K__PWM4_OUT 0x001C 0x02E4 0x0000 0x2 0x0 +-#define MX6SLL_PAD_REF_CLK_32K__USB_OTG1_ID 0x001C 0x02E4 0x055C 0x3 0x0 +-#define MX6SLL_PAD_REF_CLK_32K__SD1_LCTL 0x001C 0x02E4 0x0000 0x4 0x0 +-#define MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x001C 0x02E4 0x0000 0x5 0x0 +-#define MX6SLL_PAD_REF_CLK_32K__SD3_CD_B 0x001C 0x02E4 0x0780 0x6 0x0 +-#define MX6SLL_PAD_PWM1__PWM1_OUT 0x0020 0x02E8 0x0000 0x0 0x0 +-#define MX6SLL_PAD_PWM1__CCM_CLKO 0x0020 0x02E8 0x0000 0x1 0x0 +-#define MX6SLL_PAD_PWM1__AUDIO_CLK_OUT 0x0020 0x02E8 0x0000 0x2 0x0 +-#define MX6SLL_PAD_PWM1__CSI_MCLK 0x0020 0x02E8 0x0000 0x4 0x0 +-#define MX6SLL_PAD_PWM1__GPIO3_IO23 0x0020 0x02E8 0x0000 0x5 0x0 +-#define MX6SLL_PAD_PWM1__EPIT1_OUT 0x0020 0x02E8 0x0000 0x6 0x0 +-#define MX6SLL_PAD_KEY_COL0__KEY_COL0 0x0024 0x02EC 0x06A0 0x0 0x0 +-#define MX6SLL_PAD_KEY_COL0__I2C2_SCL 0x0024 0x02EC 0x0684 0x1 0x0 +-#define MX6SLL_PAD_KEY_COL0__LCD_DATA00 0x0024 0x02EC 0x06D8 0x2 0x0 +-#define MX6SLL_PAD_KEY_COL0__SD1_CD_B 0x0024 0x02EC 0x0770 0x4 0x1 +-#define MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x0024 0x02EC 0x0000 0x5 0x0 +-#define MX6SLL_PAD_KEY_ROW0__KEY_ROW0 0x0028 0x02F0 0x06C0 0x0 0x0 +-#define MX6SLL_PAD_KEY_ROW0__I2C2_SDA 0x0028 0x02F0 0x0688 0x1 0x0 +-#define MX6SLL_PAD_KEY_ROW0__LCD_DATA01 0x0028 0x02F0 0x06DC 0x2 0x0 +-#define MX6SLL_PAD_KEY_ROW0__SD1_WP 0x0028 0x02F0 0x0774 0x4 0x1 +-#define MX6SLL_PAD_KEY_ROW0__GPIO3_IO25 0x0028 0x02F0 0x0000 0x5 0x0 +-#define MX6SLL_PAD_KEY_COL1__KEY_COL1 0x002C 0x02F4 0x06A4 0x0 0x0 +-#define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI 0x002C 0x02F4 0x0658 0x1 0x1 +-#define MX6SLL_PAD_KEY_COL1__LCD_DATA02 0x002C 0x02F4 0x06E0 0x2 0x0 +-#define MX6SLL_PAD_KEY_COL1__SD3_DATA4 0x002C 0x02F4 0x0784 0x4 0x0 +-#define MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x002C 0x02F4 0x0000 0x5 0x0 +-#define MX6SLL_PAD_KEY_ROW1__KEY_ROW1 0x0030 0x02F8 0x06C4 0x0 0x0 +-#define MX6SLL_PAD_KEY_ROW1__ECSPI4_MISO 0x0030 0x02F8 0x0654 0x1 0x1 +-#define MX6SLL_PAD_KEY_ROW1__LCD_DATA03 0x0030 0x02F8 0x06E4 0x2 0x0 +-#define MX6SLL_PAD_KEY_ROW1__CSI_FIELD 0x0030 0x02F8 0x0000 0x3 0x0 +-#define MX6SLL_PAD_KEY_ROW1__SD3_DATA5 0x0030 0x02F8 0x0788 0x4 0x0 +-#define MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x0030 0x02F8 0x0000 0x5 0x0 +-#define MX6SLL_PAD_KEY_COL2__KEY_COL2 0x0034 0x02FC 0x06A8 0x0 0x0 +-#define MX6SLL_PAD_KEY_COL2__ECSPI4_SS0 0x0034 0x02FC 0x065C 0x1 0x1 +-#define MX6SLL_PAD_KEY_COL2__LCD_DATA04 0x0034 0x02FC 0x06E8 0x2 0x0 +-#define MX6SLL_PAD_KEY_COL2__CSI_DATA12 0x0034 0x02FC 0x05B8 0x3 0x1 +-#define MX6SLL_PAD_KEY_COL2__SD3_DATA6 0x0034 0x02FC 0x078C 0x4 0x0 +-#define MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x0034 0x02FC 0x0000 0x5 0x0 +-#define MX6SLL_PAD_KEY_ROW2__KEY_ROW2 0x0038 0x0300 0x06C8 0x0 0x0 +-#define MX6SLL_PAD_KEY_ROW2__ECSPI4_SCLK 0x0038 0x0300 0x0650 0x1 0x1 +-#define MX6SLL_PAD_KEY_ROW2__LCD_DATA05 0x0038 0x0300 0x06EC 0x2 0x0 +-#define MX6SLL_PAD_KEY_ROW2__CSI_DATA13 0x0038 0x0300 0x05BC 0x3 0x1 +-#define MX6SLL_PAD_KEY_ROW2__SD3_DATA7 0x0038 0x0300 0x0790 0x4 0x0 +-#define MX6SLL_PAD_KEY_ROW2__GPIO3_IO29 0x0038 0x0300 0x0000 0x5 0x0 +-#define MX6SLL_PAD_KEY_COL3__KEY_COL3 0x003C 0x0304 0x06AC 0x0 0x0 +-#define MX6SLL_PAD_KEY_COL3__AUD6_RXFS 0x003C 0x0304 0x05A0 0x1 0x1 +-#define MX6SLL_PAD_KEY_COL3__LCD_DATA06 0x003C 0x0304 0x06F0 0x2 0x0 +-#define MX6SLL_PAD_KEY_COL3__CSI_DATA14 0x003C 0x0304 0x05C0 0x3 0x1 +-#define MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x003C 0x0304 0x0000 0x5 0x0 +-#define MX6SLL_PAD_KEY_COL3__SD1_RESET 0x003C 0x0304 0x0000 0x6 0x0 +-#define MX6SLL_PAD_KEY_ROW3__KEY_ROW3 0x0040 0x0308 0x06CC 0x0 0x1 +-#define MX6SLL_PAD_KEY_ROW3__AUD6_RXC 0x0040 0x0308 0x059C 0x1 0x1 +-#define MX6SLL_PAD_KEY_ROW3__LCD_DATA07 0x0040 0x0308 0x06F4 0x2 0x1 +-#define MX6SLL_PAD_KEY_ROW3__CSI_DATA15 0x0040 0x0308 0x05C4 0x3 0x2 +-#define MX6SLL_PAD_KEY_ROW3__GPIO3_IO31 0x0040 0x0308 0x0000 0x5 0x0 +-#define MX6SLL_PAD_KEY_ROW3__SD1_VSELECT 0x0040 0x0308 0x0000 0x6 0x0 +-#define MX6SLL_PAD_KEY_COL4__KEY_COL4 0x0044 0x030C 0x06B0 0x0 0x1 +-#define MX6SLL_PAD_KEY_COL4__AUD6_RXD 0x0044 0x030C 0x0594 0x1 0x1 +-#define MX6SLL_PAD_KEY_COL4__LCD_DATA08 0x0044 0x030C 0x06F8 0x2 0x1 +-#define MX6SLL_PAD_KEY_COL4__CSI_DATA16 0x0044 0x030C 0x0000 0x3 0x0 +-#define MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x0044 0x030C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_KEY_COL4__USB_OTG1_PWR 0x0044 0x030C 0x0000 0x6 0x0 +-#define MX6SLL_PAD_KEY_ROW4__KEY_ROW4 0x0048 0x0310 0x06D0 0x0 0x1 +-#define MX6SLL_PAD_KEY_ROW4__AUD6_TXC 0x0048 0x0310 0x05A4 0x1 0x1 +-#define MX6SLL_PAD_KEY_ROW4__LCD_DATA09 0x0048 0x0310 0x06FC 0x2 0x1 +-#define MX6SLL_PAD_KEY_ROW4__CSI_DATA17 0x0048 0x0310 0x0000 0x3 0x0 +-#define MX6SLL_PAD_KEY_ROW4__GPIO4_IO01 0x0048 0x0310 0x0000 0x5 0x0 +-#define MX6SLL_PAD_KEY_ROW4__USB_OTG1_OC 0x0048 0x0310 0x076C 0x6 0x2 +-#define MX6SLL_PAD_KEY_COL5__KEY_COL5 0x004C 0x0314 0x0694 0x0 0x1 +-#define MX6SLL_PAD_KEY_COL5__AUD6_TXFS 0x004C 0x0314 0x05A8 0x1 0x1 +-#define MX6SLL_PAD_KEY_COL5__LCD_DATA10 0x004C 0x0314 0x0700 0x2 0x0 +-#define MX6SLL_PAD_KEY_COL5__CSI_DATA18 0x004C 0x0314 0x0000 0x3 0x0 +-#define MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x004C 0x0314 0x0000 0x5 0x0 +-#define MX6SLL_PAD_KEY_COL5__USB_OTG2_PWR 0x004C 0x0314 0x0000 0x6 0x0 +-#define MX6SLL_PAD_KEY_ROW5__KEY_ROW5 0x0050 0x0318 0x06B4 0x0 0x2 +-#define MX6SLL_PAD_KEY_ROW5__AUD6_TXD 0x0050 0x0318 0x0598 0x1 0x1 +-#define MX6SLL_PAD_KEY_ROW5__LCD_DATA11 0x0050 0x0318 0x0704 0x2 0x1 +-#define MX6SLL_PAD_KEY_ROW5__CSI_DATA19 0x0050 0x0318 0x0000 0x3 0x0 +-#define MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x0050 0x0318 0x0000 0x5 0x0 +-#define MX6SLL_PAD_KEY_ROW5__USB_OTG2_OC 0x0050 0x0318 0x0768 0x6 0x3 +-#define MX6SLL_PAD_KEY_COL6__KEY_COL6 0x0054 0x031C 0x0698 0x0 0x2 +-#define MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x0054 0x031C 0x075C 0x1 0x2 +-#define MX6SLL_PAD_KEY_COL6__UART4_DTE_TX 0x0054 0x031C 0x0000 0x1 0x0 +-#define MX6SLL_PAD_KEY_COL6__LCD_DATA12 0x0054 0x031C 0x0708 0x2 0x1 +-#define MX6SLL_PAD_KEY_COL6__CSI_DATA20 0x0054 0x031C 0x0000 0x3 0x0 +-#define MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x0054 0x031C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_KEY_COL6__SD3_RESET 0x0054 0x031C 0x0000 0x6 0x0 +-#define MX6SLL_PAD_KEY_ROW6__KEY_ROW6 0x0058 0x0320 0x06B8 0x0 0x2 +-#define MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x0058 0x0320 0x0000 0x1 0x0 +-#define MX6SLL_PAD_KEY_ROW6__UART4_DTE_RX 0x0058 0x0320 0x075C 0x1 0x3 +-#define MX6SLL_PAD_KEY_ROW6__LCD_DATA13 0x0058 0x0320 0x070C 0x2 0x1 +-#define MX6SLL_PAD_KEY_ROW6__CSI_DATA21 0x0058 0x0320 0x0000 0x3 0x0 +-#define MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 0x0058 0x0320 0x0000 0x5 0x0 +-#define MX6SLL_PAD_KEY_ROW6__SD3_VSELECT 0x0058 0x0320 0x0000 0x6 0x0 +-#define MX6SLL_PAD_KEY_COL7__KEY_COL7 0x005C 0x0324 0x069C 0x0 0x2 +-#define MX6SLL_PAD_KEY_COL7__UART4_DCE_RTS 0x005C 0x0324 0x0758 0x1 0x2 +-#define MX6SLL_PAD_KEY_COL7__UART4_DTE_CTS 0x005C 0x0324 0x0000 0x1 0x0 +-#define MX6SLL_PAD_KEY_COL7__LCD_DATA14 0x005C 0x0324 0x0710 0x2 0x1 +-#define MX6SLL_PAD_KEY_COL7__CSI_DATA22 0x005C 0x0324 0x0000 0x3 0x0 +-#define MX6SLL_PAD_KEY_COL7__GPIO4_IO06 0x005C 0x0324 0x0000 0x5 0x0 +-#define MX6SLL_PAD_KEY_COL7__SD1_WP 0x005C 0x0324 0x0774 0x6 0x3 +-#define MX6SLL_PAD_KEY_ROW7__KEY_ROW7 0x0060 0x0328 0x06BC 0x0 0x2 +-#define MX6SLL_PAD_KEY_ROW7__UART4_DCE_CTS 0x0060 0x0328 0x0000 0x1 0x0 +-#define MX6SLL_PAD_KEY_ROW7__UART4_DTE_RTS 0x0060 0x0328 0x0758 0x1 0x3 +-#define MX6SLL_PAD_KEY_ROW7__LCD_DATA15 0x0060 0x0328 0x0714 0x2 0x1 +-#define MX6SLL_PAD_KEY_ROW7__CSI_DATA23 0x0060 0x0328 0x0000 0x3 0x0 +-#define MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x0060 0x0328 0x0000 0x5 0x0 +-#define MX6SLL_PAD_KEY_ROW7__SD1_CD_B 0x0060 0x0328 0x0770 0x6 0x3 +-#define MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x0064 0x032C 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_DATA00__ECSPI4_MOSI 0x0064 0x032C 0x0658 0x1 0x2 +-#define MX6SLL_PAD_EPDC_DATA00__LCD_DATA24 0x0064 0x032C 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_DATA00__CSI_DATA00 0x0064 0x032C 0x05C8 0x3 0x2 +-#define MX6SLL_PAD_EPDC_DATA00__GPIO1_IO07 0x0064 0x032C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x0068 0x0330 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_DATA01__ECSPI4_MISO 0x0068 0x0330 0x0654 0x1 0x2 +-#define MX6SLL_PAD_EPDC_DATA01__LCD_DATA25 0x0068 0x0330 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_DATA01__CSI_DATA01 0x0068 0x0330 0x05CC 0x3 0x2 +-#define MX6SLL_PAD_EPDC_DATA01__GPIO1_IO08 0x0068 0x0330 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x006C 0x0334 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_DATA02__ECSPI4_SS0 0x006C 0x0334 0x065C 0x1 0x2 +-#define MX6SLL_PAD_EPDC_DATA02__LCD_DATA26 0x006C 0x0334 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x006C 0x0334 0x05D0 0x3 0x2 +-#define MX6SLL_PAD_EPDC_DATA02__GPIO1_IO09 0x006C 0x0334 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x0070 0x0338 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_DATA03__ECSPI4_SCLK 0x0070 0x0338 0x0650 0x1 0x2 +-#define MX6SLL_PAD_EPDC_DATA03__LCD_DATA27 0x0070 0x0338 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x0070 0x0338 0x05D4 0x3 0x2 +-#define MX6SLL_PAD_EPDC_DATA03__GPIO1_IO10 0x0070 0x0338 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x0074 0x033C 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_DATA04__ECSPI4_SS1 0x0074 0x033C 0x0660 0x1 0x1 +-#define MX6SLL_PAD_EPDC_DATA04__LCD_DATA28 0x0074 0x033C 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x0074 0x033C 0x05D8 0x3 0x2 +-#define MX6SLL_PAD_EPDC_DATA04__GPIO1_IO11 0x0074 0x033C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x0078 0x0340 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_DATA05__ECSPI4_SS2 0x0078 0x0340 0x0664 0x1 0x1 +-#define MX6SLL_PAD_EPDC_DATA05__LCD_DATA29 0x0078 0x0340 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x0078 0x0340 0x05DC 0x3 0x2 +-#define MX6SLL_PAD_EPDC_DATA05__GPIO1_IO12 0x0078 0x0340 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x007C 0x0344 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_DATA06__ECSPI4_SS3 0x007C 0x0344 0x0000 0x1 0x0 +-#define MX6SLL_PAD_EPDC_DATA06__LCD_DATA30 0x007C 0x0344 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x007C 0x0344 0x05E0 0x3 0x2 +-#define MX6SLL_PAD_EPDC_DATA06__GPIO1_IO13 0x007C 0x0344 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x0080 0x0348 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_DATA07__ECSPI4_RDY 0x0080 0x0348 0x0000 0x1 0x0 +-#define MX6SLL_PAD_EPDC_DATA07__LCD_DATA31 0x0080 0x0348 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x0080 0x0348 0x05E4 0x3 0x2 +-#define MX6SLL_PAD_EPDC_DATA07__GPIO1_IO14 0x0080 0x0348 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x0084 0x034C 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_DATA08__ECSPI3_MOSI 0x0084 0x034C 0x063C 0x1 0x2 +-#define MX6SLL_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 0x0084 0x034C 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_DATA08__GPIO1_IO15 0x0084 0x034C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x0088 0x0350 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_DATA09__ECSPI3_MISO 0x0088 0x0350 0x0638 0x1 0x2 +-#define MX6SLL_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 0x0088 0x0350 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_DATA09__GPIO1_IO16 0x0088 0x0350 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x008C 0x0354 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_DATA10__ECSPI3_SS0 0x008C 0x0354 0x0648 0x1 0x2 +-#define MX6SLL_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 0x008C 0x0354 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_DATA10__GPIO1_IO17 0x008C 0x0354 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x0090 0x0358 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_DATA11__ECSPI3_SCLK 0x0090 0x0358 0x0630 0x1 0x2 +-#define MX6SLL_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 0x0090 0x0358 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_DATA11__GPIO1_IO18 0x0090 0x0358 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x0094 0x035C 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_DATA12__UART2_DCE_RX 0x0094 0x035C 0x074C 0x1 0x4 +-#define MX6SLL_PAD_EPDC_DATA12__UART2_DTE_TX 0x0094 0x035C 0x0000 0x1 0x0 +-#define MX6SLL_PAD_EPDC_DATA12__EPDC_PWR_COM 0x0094 0x035C 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_DATA12__GPIO1_IO19 0x0094 0x035C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_DATA12__ECSPI3_SS1 0x0094 0x035C 0x064C 0x6 0x1 +-#define MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x0098 0x0360 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_DATA13__UART2_DCE_TX 0x0098 0x0360 0x0000 0x1 0x0 +-#define MX6SLL_PAD_EPDC_DATA13__UART2_DTE_RX 0x0098 0x0360 0x074C 0x1 0x5 +-#define MX6SLL_PAD_EPDC_DATA13__EPDC_PWR_IRQ 0x0098 0x0360 0x0668 0x2 0x0 +-#define MX6SLL_PAD_EPDC_DATA13__GPIO1_IO20 0x0098 0x0360 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_DATA13__ECSPI3_SS2 0x0098 0x0360 0x0640 0x6 0x1 +-#define MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x009C 0x0364 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_DATA14__UART2_DCE_RTS 0x009C 0x0364 0x0748 0x1 0x4 +-#define MX6SLL_PAD_EPDC_DATA14__UART2_DTE_CTS 0x009C 0x0364 0x0000 0x1 0x0 +-#define MX6SLL_PAD_EPDC_DATA14__EPDC_PWR_STAT 0x009C 0x0364 0x066C 0x2 0x0 +-#define MX6SLL_PAD_EPDC_DATA14__GPIO1_IO21 0x009C 0x0364 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_DATA14__ECSPI3_SS3 0x009C 0x0364 0x0644 0x6 0x1 +-#define MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x00A0 0x0368 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_DATA15__UART2_DCE_CTS 0x00A0 0x0368 0x0000 0x1 0x0 +-#define MX6SLL_PAD_EPDC_DATA15__UART2_DTE_RTS 0x00A0 0x0368 0x0748 0x1 0x5 +-#define MX6SLL_PAD_EPDC_DATA15__EPDC_PWR_WAKE 0x00A0 0x0368 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_DATA15__GPIO1_IO22 0x00A0 0x0368 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_DATA15__ECSPI3_RDY 0x00A0 0x0368 0x0634 0x6 0x1 +-#define MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x00A4 0x036C 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x00A4 0x036C 0x0624 0x1 0x2 +-#define MX6SLL_PAD_EPDC_SDCLK__I2C2_SCL 0x00A4 0x036C 0x0684 0x2 0x2 +-#define MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x00A4 0x036C 0x05E8 0x3 0x2 +-#define MX6SLL_PAD_EPDC_SDCLK__GPIO1_IO23 0x00A4 0x036C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x00A8 0x0370 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_SDLE__ECSPI2_MISO 0x00A8 0x0370 0x0620 0x1 0x2 +-#define MX6SLL_PAD_EPDC_SDLE__I2C2_SDA 0x00A8 0x0370 0x0688 0x2 0x2 +-#define MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x00A8 0x0370 0x05EC 0x3 0x2 +-#define MX6SLL_PAD_EPDC_SDLE__GPIO1_IO24 0x00A8 0x0370 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x00AC 0x0374 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_SDOE__ECSPI2_SS0 0x00AC 0x0374 0x0628 0x1 0x1 +-#define MX6SLL_PAD_EPDC_SDOE__CSI_DATA10 0x00AC 0x0374 0x05B0 0x3 0x2 +-#define MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x00AC 0x0374 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x00B0 0x0378 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x00B0 0x0378 0x061C 0x1 0x2 +-#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x00B0 0x0378 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_SDSHR__CSI_DATA11 0x00B0 0x0378 0x05B4 0x3 0x2 +-#define MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x00B0 0x0378 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x00B4 0x037C 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x00B4 0x037C 0x062C 0x1 0x1 +-#define MX6SLL_PAD_EPDC_SDCE0__PWM3_OUT 0x00B4 0x037C 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_SDCE0__GPIO1_IO27 0x00B4 0x037C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x00B8 0x0380 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_SDCE1__WDOG2_B 0x00B8 0x0380 0x0000 0x1 0x0 +-#define MX6SLL_PAD_EPDC_SDCE1__PWM4_OUT 0x00B8 0x0380 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_SDCE1__GPIO1_IO28 0x00B8 0x0380 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x00BC 0x0384 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 0x00BC 0x0384 0x068C 0x1 0x2 +-#define MX6SLL_PAD_EPDC_SDCE2__PWM1_OUT 0x00BC 0x0384 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29 0x00BC 0x0384 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x00C0 0x0388 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 0x00C0 0x0388 0x0690 0x1 0x2 +-#define MX6SLL_PAD_EPDC_SDCE3__PWM2_OUT 0x00C0 0x0388 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30 0x00C0 0x0388 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x00C4 0x038C 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x00C4 0x038C 0x0000 0x1 0x0 +-#define MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x00C4 0x038C 0x05F4 0x3 0x2 +-#define MX6SLL_PAD_EPDC_GDCLK__GPIO1_IO31 0x00C4 0x038C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_GDCLK__SD2_RESET 0x00C4 0x038C 0x0000 0x6 0x0 +-#define MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x00C8 0x0390 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_GDOE__ECSPI2_SS3 0x00C8 0x0390 0x0000 0x1 0x0 +-#define MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x00C8 0x0390 0x05F0 0x3 0x2 +-#define MX6SLL_PAD_EPDC_GDOE__GPIO2_IO00 0x00C8 0x0390 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_GDOE__SD2_VSELECT 0x00C8 0x0390 0x0000 0x6 0x0 +-#define MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x00CC 0x0394 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_GDRL__ECSPI2_RDY 0x00CC 0x0394 0x0000 0x1 0x0 +-#define MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x00CC 0x0394 0x0000 0x3 0x0 +-#define MX6SLL_PAD_EPDC_GDRL__GPIO2_IO01 0x00CC 0x0394 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_GDRL__SD2_WP 0x00CC 0x0394 0x077C 0x6 0x2 +-#define MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x00D0 0x0398 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_GDSP__PWM4_OUT 0x00D0 0x0398 0x0000 0x1 0x0 +-#define MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x00D0 0x0398 0x05F8 0x3 0x2 +-#define MX6SLL_PAD_EPDC_GDSP__GPIO2_IO02 0x00D0 0x0398 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_GDSP__SD2_CD_B 0x00D0 0x0398 0x0778 0x6 0x2 +-#define MX6SLL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x00D4 0x039C 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_VCOM0__AUD5_RXFS 0x00D4 0x039C 0x0588 0x1 0x1 +-#define MX6SLL_PAD_EPDC_VCOM0__UART3_DCE_RX 0x00D4 0x039C 0x0754 0x2 0x4 +-#define MX6SLL_PAD_EPDC_VCOM0__UART3_DTE_TX 0x00D4 0x039C 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x00D4 0x039C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x00D4 0x039C 0x0000 0x6 0x0 +-#define MX6SLL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x00D8 0x03A0 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_VCOM1__AUD5_RXD 0x00D8 0x03A0 0x057C 0x1 0x1 +-#define MX6SLL_PAD_EPDC_VCOM1__UART3_DCE_TX 0x00D8 0x03A0 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_VCOM1__UART3_DTE_RX 0x00D8 0x03A0 0x0754 0x2 0x5 +-#define MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x00D8 0x03A0 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x00D8 0x03A0 0x0000 0x6 0x0 +-#define MX6SLL_PAD_EPDC_BDR0__EPDC_BDR0 0x00DC 0x03A4 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_BDR0__UART3_DCE_RTS 0x00DC 0x03A4 0x0750 0x2 0x2 +-#define MX6SLL_PAD_EPDC_BDR0__UART3_DTE_CTS 0x00DC 0x03A4 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_BDR0__GPIO2_IO05 0x00DC 0x03A4 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_BDR0__EPDC_SDCE7 0x00DC 0x03A4 0x0000 0x6 0x0 +-#define MX6SLL_PAD_EPDC_BDR1__EPDC_BDR1 0x00E0 0x03A8 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_BDR1__UART3_DCE_CTS 0x00E0 0x03A8 0x0000 0x2 0x0 +-#define MX6SLL_PAD_EPDC_BDR1__UART3_DTE_RTS 0x00E0 0x03A8 0x0750 0x2 0x3 +-#define MX6SLL_PAD_EPDC_BDR1__GPIO2_IO06 0x00E0 0x03A8 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_BDR1__EPDC_SDCE8 0x00E0 0x03A8 0x0000 0x6 0x0 +-#define MX6SLL_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0 0x00E4 0x03AC 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_PWR_CTRL0__AUD5_RXC 0x00E4 0x03AC 0x0584 0x1 0x1 +-#define MX6SLL_PAD_EPDC_PWR_CTRL0__LCD_DATA16 0x00E4 0x03AC 0x0718 0x2 0x1 +-#define MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x00E4 0x03AC 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1 0x00E8 0x03B0 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_PWR_CTRL1__AUD5_TXFS 0x00E8 0x03B0 0x0590 0x1 0x1 +-#define MX6SLL_PAD_EPDC_PWR_CTRL1__LCD_DATA17 0x00E8 0x03B0 0x071C 0x2 0x1 +-#define MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x00E8 0x03B0 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2 0x00EC 0x03B4 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_PWR_CTRL2__AUD5_TXD 0x00EC 0x03B4 0x0580 0x1 0x1 +-#define MX6SLL_PAD_EPDC_PWR_CTRL2__LCD_DATA18 0x00EC 0x03B4 0x0720 0x2 0x1 +-#define MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0x00EC 0x03B4 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3 0x00F0 0x03B8 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_PWR_CTRL3__AUD5_TXC 0x00F0 0x03B8 0x058C 0x1 0x1 +-#define MX6SLL_PAD_EPDC_PWR_CTRL3__LCD_DATA19 0x00F0 0x03B8 0x0724 0x2 0x1 +-#define MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x00F0 0x03B8 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00F4 0x03BC 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_PWR_COM__LCD_DATA20 0x00F4 0x03BC 0x0728 0x2 0x1 +-#define MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x00F4 0x03BC 0x055C 0x4 0x4 +-#define MX6SLL_PAD_EPDC_PWR_COM__GPIO2_IO11 0x00F4 0x03BC 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_PWR_COM__SD3_RESET 0x00F4 0x03BC 0x0000 0x6 0x0 +-#define MX6SLL_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ 0x00F8 0x03C0 0x0668 0x0 0x1 +-#define MX6SLL_PAD_EPDC_PWR_IRQ__LCD_DATA21 0x00F8 0x03C0 0x072C 0x2 0x1 +-#define MX6SLL_PAD_EPDC_PWR_IRQ__USB_OTG2_ID 0x00F8 0x03C0 0x0560 0x4 0x3 +-#define MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x00F8 0x03C0 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_PWR_IRQ__SD3_VSELECT 0x00F8 0x03C0 0x0000 0x6 0x0 +-#define MX6SLL_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00FC 0x03C4 0x066C 0x0 0x1 +-#define MX6SLL_PAD_EPDC_PWR_STAT__LCD_DATA22 0x00FC 0x03C4 0x0730 0x2 0x1 +-#define MX6SLL_PAD_EPDC_PWR_STAT__ARM_EVENTI 0x00FC 0x03C4 0x0000 0x4 0x0 +-#define MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x00FC 0x03C4 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_PWR_STAT__SD3_WP 0x00FC 0x03C4 0x0794 0x6 0x2 +-#define MX6SLL_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE 0x0100 0x03C8 0x0000 0x0 0x0 +-#define MX6SLL_PAD_EPDC_PWR_WAKE__LCD_DATA23 0x0100 0x03C8 0x0734 0x2 0x1 +-#define MX6SLL_PAD_EPDC_PWR_WAKE__ARM_EVENTO 0x0100 0x03C8 0x0000 0x4 0x0 +-#define MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x0100 0x03C8 0x0000 0x5 0x0 +-#define MX6SLL_PAD_EPDC_PWR_WAKE__SD3_CD_B 0x0100 0x03C8 0x0780 0x6 0x2 +-#define MX6SLL_PAD_LCD_CLK__LCD_CLK 0x0104 0x03CC 0x0000 0x0 0x0 +-#define MX6SLL_PAD_LCD_CLK__LCD_WR_RWN 0x0104 0x03CC 0x0000 0x2 0x0 +-#define MX6SLL_PAD_LCD_CLK__PWM4_OUT 0x0104 0x03CC 0x0000 0x4 0x0 +-#define MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x0104 0x03CC 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x0108 0x03D0 0x0000 0x0 0x0 +-#define MX6SLL_PAD_LCD_ENABLE__LCD_RD_E 0x0108 0x03D0 0x0000 0x2 0x0 +-#define MX6SLL_PAD_LCD_ENABLE__UART2_DCE_RX 0x0108 0x03D0 0x0000 0x4 0x0 +-#define MX6SLL_PAD_LCD_ENABLE__UART2_DTE_TX 0x0108 0x03D0 0x0000 0x4 0x0 +-#define MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x0108 0x03D0 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x010C 0x03D4 0x06D4 0x0 0x0 +-#define MX6SLL_PAD_LCD_HSYNC__LCD_CS 0x010C 0x03D4 0x0000 0x2 0x0 +-#define MX6SLL_PAD_LCD_HSYNC__UART2_DCE_TX 0x010C 0x03D4 0x0000 0x4 0x0 +-#define MX6SLL_PAD_LCD_HSYNC__UART2_DTE_RX 0x010C 0x03D4 0x074C 0x4 0x1 +-#define MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x010C 0x03D4 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x010C 0x03D4 0x0000 0x6 0x0 +-#define MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x0110 0x03D8 0x0000 0x0 0x0 +-#define MX6SLL_PAD_LCD_VSYNC__LCD_RS 0x0110 0x03D8 0x0000 0x2 0x0 +-#define MX6SLL_PAD_LCD_VSYNC__UART2_DCE_RTS 0x0110 0x03D8 0x0748 0x4 0x0 +-#define MX6SLL_PAD_LCD_VSYNC__UART2_DTE_CTS 0x0110 0x03D8 0x0000 0x4 0x0 +-#define MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x0110 0x03D8 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x0110 0x03D8 0x0000 0x6 0x0 +-#define MX6SLL_PAD_LCD_RESET__LCD_RESET 0x0114 0x03DC 0x0000 0x0 0x0 +-#define MX6SLL_PAD_LCD_RESET__LCD_BUSY 0x0114 0x03DC 0x06D4 0x2 0x1 +-#define MX6SLL_PAD_LCD_RESET__UART2_DCE_CTS 0x0114 0x03DC 0x0000 0x4 0x0 +-#define MX6SLL_PAD_LCD_RESET__UART2_DTE_RTS 0x0114 0x03DC 0x0748 0x4 0x1 +-#define MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x0114 0x03DC 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_RESET__CCM_PMIC_READY 0x0114 0x03DC 0x05AC 0x6 0x2 +-#define MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x0118 0x03E0 0x06D8 0x0 0x1 +-#define MX6SLL_PAD_LCD_DATA00__ECSPI1_MOSI 0x0118 0x03E0 0x0608 0x1 0x0 +-#define MX6SLL_PAD_LCD_DATA00__USB_OTG2_ID 0x0118 0x03E0 0x0560 0x2 0x2 +-#define MX6SLL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03E0 0x0000 0x3 0x0 +-#define MX6SLL_PAD_LCD_DATA00__UART5_DTR_B 0x0118 0x03E0 0x0000 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x0118 0x03E0 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA00__ARM_TRACE00 0x0118 0x03E0 0x0000 0x6 0x0 +-#define MX6SLL_PAD_LCD_DATA00__SRC_BOOT_CFG00 0x0118 0x03E0 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x011C 0x03E4 0x06DC 0x0 0x1 +-#define MX6SLL_PAD_LCD_DATA01__ECSPI1_MISO 0x011C 0x03E4 0x0604 0x1 0x0 +-#define MX6SLL_PAD_LCD_DATA01__USB_OTG1_ID 0x011C 0x03E4 0x055C 0x2 0x3 +-#define MX6SLL_PAD_LCD_DATA01__PWM2_OUT 0x011C 0x03E4 0x0000 0x3 0x0 +-#define MX6SLL_PAD_LCD_DATA01__AUD4_RXFS 0x011C 0x03E4 0x0570 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x011C 0x03E4 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA01__ARM_TRACE01 0x011C 0x03E4 0x0000 0x6 0x0 +-#define MX6SLL_PAD_LCD_DATA01__SRC_BOOT_CFG01 0x011C 0x03E4 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x0120 0x03E8 0x06E0 0x0 0x1 +-#define MX6SLL_PAD_LCD_DATA02__ECSPI1_SS0 0x0120 0x03E8 0x0614 0x1 0x0 +-#define MX6SLL_PAD_LCD_DATA02__EPIT2_OUT 0x0120 0x03E8 0x0000 0x2 0x0 +-#define MX6SLL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03E8 0x0000 0x3 0x0 +-#define MX6SLL_PAD_LCD_DATA02__AUD4_RXC 0x0120 0x03E8 0x056C 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x0120 0x03E8 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA02__ARM_TRACE02 0x0120 0x03E8 0x0000 0x6 0x0 +-#define MX6SLL_PAD_LCD_DATA02__SRC_BOOT_CFG02 0x0120 0x03E8 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x0124 0x03EC 0x06E4 0x0 0x1 +-#define MX6SLL_PAD_LCD_DATA03__ECSPI1_SCLK 0x0124 0x03EC 0x05FC 0x1 0x0 +-#define MX6SLL_PAD_LCD_DATA03__UART5_DSR_B 0x0124 0x03EC 0x0000 0x2 0x0 +-#define MX6SLL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03EC 0x0000 0x3 0x0 +-#define MX6SLL_PAD_LCD_DATA03__AUD4_RXD 0x0124 0x03EC 0x0564 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x0124 0x03EC 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA03__ARM_TRACE03 0x0124 0x03EC 0x0000 0x6 0x0 +-#define MX6SLL_PAD_LCD_DATA03__SRC_BOOT_CFG03 0x0124 0x03EC 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x0128 0x03F0 0x06E8 0x0 0x1 +-#define MX6SLL_PAD_LCD_DATA04__ECSPI1_SS1 0x0128 0x03F0 0x060C 0x1 0x1 +-#define MX6SLL_PAD_LCD_DATA04__CSI_VSYNC 0x0128 0x03F0 0x05F8 0x2 0x0 +-#define MX6SLL_PAD_LCD_DATA04__WDOG2_RESET_B_DEB 0x0128 0x03F0 0x0000 0x3 0x0 +-#define MX6SLL_PAD_LCD_DATA04__AUD4_TXC 0x0128 0x03F0 0x0574 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x0128 0x03F0 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA04__ARM_TRACE04 0x0128 0x03F0 0x0000 0x6 0x0 +-#define MX6SLL_PAD_LCD_DATA04__SRC_BOOT_CFG04 0x0128 0x03F0 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x012C 0x03F4 0x06EC 0x0 0x1 +-#define MX6SLL_PAD_LCD_DATA05__ECSPI1_SS2 0x012C 0x03F4 0x0610 0x1 0x1 +-#define MX6SLL_PAD_LCD_DATA05__CSI_HSYNC 0x012C 0x03F4 0x05F0 0x2 0x0 +-#define MX6SLL_PAD_LCD_DATA05__AUD4_TXFS 0x012C 0x03F4 0x0578 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x012C 0x03F4 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA05__ARM_TRACE05 0x012C 0x03F4 0x0000 0x6 0x0 +-#define MX6SLL_PAD_LCD_DATA05__SRC_BOOT_CFG05 0x012C 0x03F4 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x0130 0x03F8 0x06F0 0x0 0x1 +-#define MX6SLL_PAD_LCD_DATA06__ECSPI1_SS3 0x0130 0x03F8 0x0618 0x1 0x0 +-#define MX6SLL_PAD_LCD_DATA06__CSI_PIXCLK 0x0130 0x03F8 0x05F4 0x2 0x0 +-#define MX6SLL_PAD_LCD_DATA06__AUD4_TXD 0x0130 0x03F8 0x0568 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x0130 0x03F8 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA06__ARM_TRACE06 0x0130 0x03F8 0x0000 0x6 0x0 +-#define MX6SLL_PAD_LCD_DATA06__SRC_BOOT_CFG06 0x0130 0x03F8 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x0134 0x03FC 0x06F4 0x0 0x0 +-#define MX6SLL_PAD_LCD_DATA07__ECSPI1_RDY 0x0134 0x03FC 0x0600 0x1 0x0 +-#define MX6SLL_PAD_LCD_DATA07__CSI_MCLK 0x0134 0x03FC 0x0000 0x2 0x0 +-#define MX6SLL_PAD_LCD_DATA07__AUDIO_CLK_OUT 0x0134 0x03FC 0x0000 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x0134 0x03FC 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA07__ARM_TRACE07 0x0134 0x03FC 0x0000 0x6 0x0 +-#define MX6SLL_PAD_LCD_DATA07__SRC_BOOT_CFG07 0x0134 0x03FC 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x0138 0x0400 0x06F8 0x0 0x0 +-#define MX6SLL_PAD_LCD_DATA08__KEY_COL0 0x0138 0x0400 0x06A0 0x1 0x1 +-#define MX6SLL_PAD_LCD_DATA08__CSI_DATA09 0x0138 0x0400 0x05EC 0x2 0x0 +-#define MX6SLL_PAD_LCD_DATA08__ECSPI2_SCLK 0x0138 0x0400 0x061C 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x0138 0x0400 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA08__ARM_TRACE08 0x0138 0x0400 0x0000 0x6 0x0 +-#define MX6SLL_PAD_LCD_DATA08__SRC_BOOT_CFG08 0x0138 0x0400 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x013C 0x0404 0x06FC 0x0 0x0 +-#define MX6SLL_PAD_LCD_DATA09__KEY_ROW0 0x013C 0x0404 0x06C0 0x1 0x1 +-#define MX6SLL_PAD_LCD_DATA09__CSI_DATA08 0x013C 0x0404 0x05E8 0x2 0x0 +-#define MX6SLL_PAD_LCD_DATA09__ECSPI2_MOSI 0x013C 0x0404 0x0624 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x013C 0x0404 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA09__ARM_TRACE09 0x013C 0x0404 0x0000 0x6 0x0 +-#define MX6SLL_PAD_LCD_DATA09__SRC_BOOT_CFG09 0x013C 0x0404 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x0140 0x0408 0x0700 0x0 0x1 +-#define MX6SLL_PAD_LCD_DATA10__KEY_COL1 0x0140 0x0408 0x06A4 0x1 0x1 +-#define MX6SLL_PAD_LCD_DATA10__CSI_DATA07 0x0140 0x0408 0x05E4 0x2 0x0 +-#define MX6SLL_PAD_LCD_DATA10__ECSPI2_MISO 0x0140 0x0408 0x0620 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x0140 0x0408 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA10__ARM_TRACE10 0x0140 0x0408 0x0000 0x6 0x0 +-#define MX6SLL_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x0140 0x0408 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x0144 0x040C 0x0704 0x0 0x0 +-#define MX6SLL_PAD_LCD_DATA11__KEY_ROW1 0x0144 0x040C 0x06C4 0x1 0x1 +-#define MX6SLL_PAD_LCD_DATA11__CSI_DATA06 0x0144 0x040C 0x05E0 0x2 0x0 +-#define MX6SLL_PAD_LCD_DATA11__ECSPI2_SS1 0x0144 0x040C 0x062C 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x0144 0x040C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA11__ARM_TRACE11 0x0144 0x040C 0x0000 0x6 0x0 +-#define MX6SLL_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x0144 0x040C 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x0148 0x0410 0x0708 0x0 0x0 +-#define MX6SLL_PAD_LCD_DATA12__KEY_COL2 0x0148 0x0410 0x06A8 0x1 0x1 +-#define MX6SLL_PAD_LCD_DATA12__CSI_DATA05 0x0148 0x0410 0x05DC 0x2 0x0 +-#define MX6SLL_PAD_LCD_DATA12__UART5_DCE_RTS 0x0148 0x0410 0x0760 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA12__UART5_DTE_CTS 0x0148 0x0410 0x0000 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x0148 0x0410 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA12__ARM_TRACE12 0x0148 0x0410 0x0000 0x6 0x0 +-#define MX6SLL_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x0148 0x0410 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x014C 0x0414 0x070C 0x0 0x0 +-#define MX6SLL_PAD_LCD_DATA13__KEY_ROW2 0x014C 0x0414 0x06C8 0x1 0x1 +-#define MX6SLL_PAD_LCD_DATA13__CSI_DATA04 0x014C 0x0414 0x05D8 0x2 0x0 +-#define MX6SLL_PAD_LCD_DATA13__UART5_DCE_CTS 0x014C 0x0414 0x0000 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA13__UART5_DTE_RTS 0x014C 0x0414 0x0760 0x4 0x1 +-#define MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x014C 0x0414 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA13__ARM_TRACE13 0x014C 0x0414 0x0000 0x6 0x0 +-#define MX6SLL_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x014C 0x0414 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x0150 0x0418 0x0710 0x0 0x0 +-#define MX6SLL_PAD_LCD_DATA14__KEY_COL3 0x0150 0x0418 0x06AC 0x1 0x1 +-#define MX6SLL_PAD_LCD_DATA14__CSI_DATA03 0x0150 0x0418 0x05D4 0x2 0x0 +-#define MX6SLL_PAD_LCD_DATA14__UART5_DCE_RX 0x0150 0x0418 0x0764 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA14__UART5_DTE_TX 0x0150 0x0418 0x0000 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x0150 0x0418 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA14__ARM_TRACE14 0x0150 0x0418 0x0000 0x6 0x0 +-#define MX6SLL_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0150 0x0418 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x0154 0x041C 0x0714 0x0 0x0 +-#define MX6SLL_PAD_LCD_DATA15__KEY_ROW3 0x0154 0x041C 0x06CC 0x1 0x0 +-#define MX6SLL_PAD_LCD_DATA15__CSI_DATA02 0x0154 0x041C 0x05D0 0x2 0x0 +-#define MX6SLL_PAD_LCD_DATA15__UART5_DCE_TX 0x0154 0x041C 0x0000 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA15__UART5_DTE_RX 0x0154 0x041C 0x0764 0x4 0x1 +-#define MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x0154 0x041C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA15__ARM_TRACE15 0x0154 0x041C 0x0000 0x6 0x0 +-#define MX6SLL_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0154 0x041C 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x0158 0x0420 0x0718 0x0 0x0 +-#define MX6SLL_PAD_LCD_DATA16__KEY_COL4 0x0158 0x0420 0x06B0 0x1 0x0 +-#define MX6SLL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x0420 0x05CC 0x2 0x0 +-#define MX6SLL_PAD_LCD_DATA16__I2C2_SCL 0x0158 0x0420 0x0684 0x4 0x1 +-#define MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x0158 0x0420 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA16__SRC_BOOT_CFG24 0x0158 0x0420 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x015C 0x0424 0x071C 0x0 0x0 +-#define MX6SLL_PAD_LCD_DATA17__KEY_ROW4 0x015C 0x0424 0x06D0 0x1 0x0 +-#define MX6SLL_PAD_LCD_DATA17__CSI_DATA00 0x015C 0x0424 0x05C8 0x2 0x0 +-#define MX6SLL_PAD_LCD_DATA17__I2C2_SDA 0x015C 0x0424 0x0688 0x4 0x1 +-#define MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x015C 0x0424 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA17__SRC_BOOT_CFG25 0x015C 0x0424 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x0160 0x0428 0x0720 0x0 0x0 +-#define MX6SLL_PAD_LCD_DATA18__KEY_COL5 0x0160 0x0428 0x0694 0x1 0x2 +-#define MX6SLL_PAD_LCD_DATA18__CSI_DATA15 0x0160 0x0428 0x05C4 0x2 0x1 +-#define MX6SLL_PAD_LCD_DATA18__GPT_CAPTURE1 0x0160 0x0428 0x0670 0x4 0x1 +-#define MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x0160 0x0428 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA18__SRC_BOOT_CFG26 0x0160 0x0428 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x0164 0x042C 0x0724 0x0 0x0 +-#define MX6SLL_PAD_LCD_DATA19__KEY_ROW5 0x0164 0x042C 0x06B4 0x1 0x1 +-#define MX6SLL_PAD_LCD_DATA19__CSI_DATA14 0x0164 0x042C 0x05C0 0x2 0x2 +-#define MX6SLL_PAD_LCD_DATA19__GPT_CAPTURE2 0x0164 0x042C 0x0674 0x4 0x1 +-#define MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x0164 0x042C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA19__SRC_BOOT_CFG27 0x0164 0x042C 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x0168 0x0430 0x0728 0x0 0x0 +-#define MX6SLL_PAD_LCD_DATA20__KEY_COL6 0x0168 0x0430 0x0698 0x1 0x1 +-#define MX6SLL_PAD_LCD_DATA20__CSI_DATA13 0x0168 0x0430 0x05BC 0x2 0x2 +-#define MX6SLL_PAD_LCD_DATA20__GPT_COMPARE1 0x0168 0x0430 0x0000 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x0168 0x0430 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA20__SRC_BOOT_CFG28 0x0168 0x0430 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x016C 0x0434 0x072C 0x0 0x0 +-#define MX6SLL_PAD_LCD_DATA21__KEY_ROW6 0x016C 0x0434 0x06B8 0x1 0x1 +-#define MX6SLL_PAD_LCD_DATA21__CSI_DATA12 0x016C 0x0434 0x05B8 0x2 0x2 +-#define MX6SLL_PAD_LCD_DATA21__GPT_COMPARE2 0x016C 0x0434 0x0000 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x016C 0x0434 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA21__SRC_BOOT_CFG29 0x016C 0x0434 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x0170 0x0438 0x0730 0x0 0x0 +-#define MX6SLL_PAD_LCD_DATA22__KEY_COL7 0x0170 0x0438 0x069C 0x1 0x1 +-#define MX6SLL_PAD_LCD_DATA22__CSI_DATA11 0x0170 0x0438 0x05B4 0x2 0x1 +-#define MX6SLL_PAD_LCD_DATA22__GPT_COMPARE3 0x0170 0x0438 0x0000 0x4 0x0 +-#define MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x0170 0x0438 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA22__SRC_BOOT_CFG30 0x0170 0x0438 0x0000 0x7 0x0 +-#define MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x0174 0x043C 0x0734 0x0 0x0 +-#define MX6SLL_PAD_LCD_DATA23__KEY_ROW7 0x0174 0x043C 0x06BC 0x1 0x1 +-#define MX6SLL_PAD_LCD_DATA23__CSI_DATA10 0x0174 0x043C 0x05B0 0x2 0x1 +-#define MX6SLL_PAD_LCD_DATA23__GPT_CLKIN 0x0174 0x043C 0x0678 0x4 0x1 +-#define MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x0174 0x043C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_LCD_DATA23__SRC_BOOT_CFG31 0x0174 0x043C 0x0000 0x7 0x0 +-#define MX6SLL_PAD_AUD_RXFS__AUD3_RXFS 0x0178 0x0440 0x0000 0x0 0x0 +-#define MX6SLL_PAD_AUD_RXFS__I2C1_SCL 0x0178 0x0440 0x067C 0x1 0x1 +-#define MX6SLL_PAD_AUD_RXFS__UART3_DCE_RX 0x0178 0x0440 0x0754 0x2 0x0 +-#define MX6SLL_PAD_AUD_RXFS__UART3_DTE_TX 0x0178 0x0440 0x0000 0x2 0x0 +-#define MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x0178 0x0440 0x068C 0x4 0x1 +-#define MX6SLL_PAD_AUD_RXFS__GPIO1_IO00 0x0178 0x0440 0x0000 0x5 0x0 +-#define MX6SLL_PAD_AUD_RXFS__ECSPI3_SS0 0x0178 0x0440 0x0648 0x6 0x0 +-#define MX6SLL_PAD_AUD_RXFS__MBIST_BEND 0x0178 0x0440 0x0000 0x7 0x0 +-#define MX6SLL_PAD_AUD_RXC__AUD3_RXC 0x017C 0x0444 0x0000 0x0 0x0 +-#define MX6SLL_PAD_AUD_RXC__I2C1_SDA 0x017C 0x0444 0x0680 0x1 0x1 +-#define MX6SLL_PAD_AUD_RXC__UART3_DCE_TX 0x017C 0x0444 0x0000 0x2 0x0 +-#define MX6SLL_PAD_AUD_RXC__UART3_DTE_RX 0x017C 0x0444 0x0754 0x2 0x1 +-#define MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x017C 0x0444 0x0690 0x4 0x1 +-#define MX6SLL_PAD_AUD_RXC__GPIO1_IO01 0x017C 0x0444 0x0000 0x5 0x0 +-#define MX6SLL_PAD_AUD_RXC__ECSPI3_SS1 0x017C 0x0444 0x064C 0x6 0x0 +-#define MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x0180 0x0448 0x0000 0x0 0x0 +-#define MX6SLL_PAD_AUD_RXD__ECSPI3_MOSI 0x0180 0x0448 0x063C 0x1 0x0 +-#define MX6SLL_PAD_AUD_RXD__UART4_DCE_RX 0x0180 0x0448 0x075C 0x2 0x0 +-#define MX6SLL_PAD_AUD_RXD__UART4_DTE_TX 0x0180 0x0448 0x0000 0x2 0x0 +-#define MX6SLL_PAD_AUD_RXD__SD1_LCTL 0x0180 0x0448 0x0000 0x4 0x0 +-#define MX6SLL_PAD_AUD_RXD__GPIO1_IO02 0x0180 0x0448 0x0000 0x5 0x0 +-#define MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x0184 0x044C 0x0000 0x0 0x0 +-#define MX6SLL_PAD_AUD_TXC__ECSPI3_MISO 0x0184 0x044C 0x0638 0x1 0x0 +-#define MX6SLL_PAD_AUD_TXC__UART4_DCE_TX 0x0184 0x044C 0x0000 0x2 0x0 +-#define MX6SLL_PAD_AUD_TXC__UART4_DTE_RX 0x0184 0x044C 0x075C 0x2 0x1 +-#define MX6SLL_PAD_AUD_TXC__SD2_LCTL 0x0184 0x044C 0x0000 0x4 0x0 +-#define MX6SLL_PAD_AUD_TXC__GPIO1_IO03 0x0184 0x044C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x0188 0x0450 0x0000 0x0 0x0 +-#define MX6SLL_PAD_AUD_TXFS__PWM3_OUT 0x0188 0x0450 0x0000 0x1 0x0 +-#define MX6SLL_PAD_AUD_TXFS__UART4_DCE_RTS 0x0188 0x0450 0x0758 0x2 0x0 +-#define MX6SLL_PAD_AUD_TXFS__UART4_DTE_CTS 0x0188 0x0450 0x0000 0x2 0x0 +-#define MX6SLL_PAD_AUD_TXFS__SD3_LCTL 0x0188 0x0450 0x0000 0x4 0x0 +-#define MX6SLL_PAD_AUD_TXFS__GPIO1_IO04 0x0188 0x0450 0x0000 0x5 0x0 +-#define MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x018C 0x0454 0x0000 0x0 0x0 +-#define MX6SLL_PAD_AUD_TXD__ECSPI3_SCLK 0x018C 0x0454 0x0630 0x1 0x0 +-#define MX6SLL_PAD_AUD_TXD__UART4_DCE_CTS 0x018C 0x0454 0x0000 0x2 0x0 +-#define MX6SLL_PAD_AUD_TXD__UART4_DTE_RTS 0x018C 0x0454 0x0758 0x2 0x1 +-#define MX6SLL_PAD_AUD_TXD__GPIO1_IO05 0x018C 0x0454 0x0000 0x5 0x0 +-#define MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x0190 0x0458 0x0000 0x0 0x0 +-#define MX6SLL_PAD_AUD_MCLK__PWM4_OUT 0x0190 0x0458 0x0000 0x1 0x0 +-#define MX6SLL_PAD_AUD_MCLK__ECSPI3_RDY 0x0190 0x0458 0x0634 0x2 0x0 +-#define MX6SLL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x0190 0x0458 0x0000 0x4 0x0 +-#define MX6SLL_PAD_AUD_MCLK__GPIO1_IO06 0x0190 0x0458 0x0000 0x5 0x0 +-#define MX6SLL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x0190 0x0458 0x073C 0x6 0x1 +-#define MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x0194 0x045C 0x0744 0x0 0x0 +-#define MX6SLL_PAD_UART1_RXD__UART1_DTE_TX 0x0194 0x045C 0x0000 0x0 0x0 +-#define MX6SLL_PAD_UART1_RXD__PWM1_OUT 0x0194 0x045C 0x0000 0x1 0x0 +-#define MX6SLL_PAD_UART1_RXD__UART4_DCE_RX 0x0194 0x045C 0x075C 0x2 0x4 +-#define MX6SLL_PAD_UART1_RXD__UART4_DTE_TX 0x0194 0x045C 0x0000 0x2 0x0 +-#define MX6SLL_PAD_UART1_RXD__UART5_DCE_RX 0x0194 0x045C 0x0764 0x4 0x6 +-#define MX6SLL_PAD_UART1_RXD__UART5_DTE_TX 0x0194 0x045C 0x0000 0x4 0x0 +-#define MX6SLL_PAD_UART1_RXD__GPIO3_IO16 0x0194 0x045C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x0198 0x0460 0x0000 0x0 0x0 +-#define MX6SLL_PAD_UART1_TXD__UART1_DTE_RX 0x0198 0x0460 0x0744 0x0 0x1 +-#define MX6SLL_PAD_UART1_TXD__PWM2_OUT 0x0198 0x0460 0x0000 0x1 0x0 +-#define MX6SLL_PAD_UART1_TXD__UART4_DCE_TX 0x0198 0x0460 0x0000 0x2 0x0 +-#define MX6SLL_PAD_UART1_TXD__UART4_DTE_RX 0x0198 0x0460 0x075C 0x2 0x5 +-#define MX6SLL_PAD_UART1_TXD__UART5_DCE_TX 0x0198 0x0460 0x0000 0x4 0x0 +-#define MX6SLL_PAD_UART1_TXD__UART5_DTE_RX 0x0198 0x0460 0x0764 0x4 0x7 +-#define MX6SLL_PAD_UART1_TXD__GPIO3_IO17 0x0198 0x0460 0x0000 0x5 0x0 +-#define MX6SLL_PAD_UART1_TXD__UART5_DCD_B 0x0198 0x0460 0x0000 0x7 0x0 +-#define MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x019C 0x0464 0x067C 0x0 0x0 +-#define MX6SLL_PAD_I2C1_SCL__UART1_DCE_RTS 0x019C 0x0464 0x0740 0x1 0x0 +-#define MX6SLL_PAD_I2C1_SCL__UART1_DTE_CTS 0x019C 0x0464 0x0000 0x1 0x0 +-#define MX6SLL_PAD_I2C1_SCL__ECSPI3_SS2 0x019C 0x0464 0x0640 0x2 0x0 +-#define MX6SLL_PAD_I2C1_SCL__SD3_RESET 0x019C 0x0464 0x0000 0x4 0x0 +-#define MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x019C 0x0464 0x0000 0x5 0x0 +-#define MX6SLL_PAD_I2C1_SCL__ECSPI1_SS1 0x019C 0x0464 0x060C 0x6 0x0 +-#define MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x01A0 0x0468 0x0680 0x0 0x0 +-#define MX6SLL_PAD_I2C1_SDA__UART1_DCE_CTS 0x01A0 0x0468 0x0000 0x1 0x0 +-#define MX6SLL_PAD_I2C1_SDA__UART1_DTE_RTS 0x01A0 0x0468 0x0740 0x1 0x1 +-#define MX6SLL_PAD_I2C1_SDA__ECSPI3_SS3 0x01A0 0x0468 0x0644 0x2 0x0 +-#define MX6SLL_PAD_I2C1_SDA__SD3_VSELECT 0x01A0 0x0468 0x0000 0x4 0x0 +-#define MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x01A0 0x0468 0x0000 0x5 0x0 +-#define MX6SLL_PAD_I2C1_SDA__ECSPI1_SS2 0x01A0 0x0468 0x0610 0x6 0x0 +-#define MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x01A4 0x046C 0x0684 0x0 0x3 +-#define MX6SLL_PAD_I2C2_SCL__AUD4_RXFS 0x01A4 0x046C 0x0570 0x1 0x2 +-#define MX6SLL_PAD_I2C2_SCL__SPDIF_IN 0x01A4 0x046C 0x0738 0x2 0x2 +-#define MX6SLL_PAD_I2C2_SCL__SD3_WP 0x01A4 0x046C 0x0794 0x4 0x3 +-#define MX6SLL_PAD_I2C2_SCL__GPIO3_IO14 0x01A4 0x046C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_I2C2_SCL__ECSPI1_RDY 0x01A4 0x046C 0x0600 0x6 0x1 +-#define MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x01A8 0x0470 0x0688 0x0 0x3 +-#define MX6SLL_PAD_I2C2_SDA__AUD4_RXC 0x01A8 0x0470 0x056C 0x1 0x2 +-#define MX6SLL_PAD_I2C2_SDA__SPDIF_OUT 0x01A8 0x0470 0x0000 0x2 0x0 +-#define MX6SLL_PAD_I2C2_SDA__SD3_CD_B 0x01A8 0x0470 0x0780 0x4 0x3 +-#define MX6SLL_PAD_I2C2_SDA__GPIO3_IO15 0x01A8 0x0470 0x0000 0x5 0x0 +-#define MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x01AC 0x0474 0x05FC 0x0 0x1 +-#define MX6SLL_PAD_ECSPI1_SCLK__AUD4_TXD 0x01AC 0x0474 0x0568 0x1 0x1 +-#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x01AC 0x0474 0x0764 0x2 0x2 +-#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x01AC 0x0474 0x0000 0x2 0x0 +-#define MX6SLL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x01AC 0x0474 0x0000 0x3 0x0 +-#define MX6SLL_PAD_ECSPI1_SCLK__SD2_RESET 0x01AC 0x0474 0x0000 0x4 0x0 +-#define MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x01AC 0x0474 0x0000 0x5 0x0 +-#define MX6SLL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x01AC 0x0474 0x0768 0x6 0x1 +-#define MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x01B0 0x0478 0x0608 0x0 0x1 +-#define MX6SLL_PAD_ECSPI1_MOSI__AUD4_TXC 0x01B0 0x0478 0x0574 0x1 0x1 +-#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x01B0 0x0478 0x0000 0x2 0x0 +-#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x01B0 0x0478 0x0764 0x2 0x3 +-#define MX6SLL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x01B0 0x0478 0x0000 0x3 0x0 +-#define MX6SLL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x01B0 0x0478 0x0000 0x4 0x0 +-#define MX6SLL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x01B0 0x0478 0x0000 0x5 0x0 +-#define MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x01B4 0x047C 0x0604 0x0 0x1 +-#define MX6SLL_PAD_ECSPI1_MISO__AUD4_TXFS 0x01B4 0x047C 0x0578 0x1 0x1 +-#define MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x01B4 0x047C 0x0760 0x2 0x2 +-#define MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x01B4 0x047C 0x0000 0x2 0x0 +-#define MX6SLL_PAD_ECSPI1_MISO__EPDC_BDR0 0x01B4 0x047C 0x0000 0x3 0x0 +-#define MX6SLL_PAD_ECSPI1_MISO__SD2_WP 0x01B4 0x047C 0x077C 0x4 0x0 +-#define MX6SLL_PAD_ECSPI1_MISO__GPIO4_IO10 0x01B4 0x047C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x01B8 0x0480 0x0614 0x0 0x1 +-#define MX6SLL_PAD_ECSPI1_SS0__AUD4_RXD 0x01B8 0x0480 0x0564 0x1 0x1 +-#define MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x01B8 0x0480 0x0000 0x2 0x0 +-#define MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x01B8 0x0480 0x0760 0x2 0x3 +-#define MX6SLL_PAD_ECSPI1_SS0__EPDC_BDR1 0x01B8 0x0480 0x0000 0x3 0x0 +-#define MX6SLL_PAD_ECSPI1_SS0__SD2_CD_B 0x01B8 0x0480 0x0778 0x4 0x0 +-#define MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 0x01B8 0x0480 0x0000 0x5 0x0 +-#define MX6SLL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x01B8 0x0480 0x0000 0x6 0x0 +-#define MX6SLL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x01BC 0x0484 0x061C 0x0 0x1 +-#define MX6SLL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x01BC 0x0484 0x073C 0x1 0x2 +-#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DCE_RX 0x01BC 0x0484 0x0754 0x2 0x2 +-#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DTE_TX 0x01BC 0x0484 0x0000 0x2 0x0 +-#define MX6SLL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x01BC 0x0484 0x05F4 0x3 0x1 +-#define MX6SLL_PAD_ECSPI2_SCLK__SD1_RESET 0x01BC 0x0484 0x0000 0x4 0x0 +-#define MX6SLL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x01BC 0x0484 0x0000 0x5 0x0 +-#define MX6SLL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x01BC 0x0484 0x0768 0x6 0x2 +-#define MX6SLL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x01C0 0x0488 0x0624 0x0 0x1 +-#define MX6SLL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x01C0 0x0488 0x0000 0x1 0x0 +-#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DCE_TX 0x01C0 0x0488 0x0000 0x2 0x0 +-#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DTE_RX 0x01C0 0x0488 0x0754 0x2 0x3 +-#define MX6SLL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x01C0 0x0488 0x05F0 0x3 0x1 +-#define MX6SLL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x01C0 0x0488 0x0000 0x4 0x0 +-#define MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x01C0 0x0488 0x0000 0x5 0x0 +-#define MX6SLL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x01C4 0x048C 0x0620 0x0 0x1 +-#define MX6SLL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x01C4 0x048C 0x0000 0x1 0x0 +-#define MX6SLL_PAD_ECSPI2_MISO__UART3_DCE_RTS 0x01C4 0x048C 0x0750 0x2 0x0 +-#define MX6SLL_PAD_ECSPI2_MISO__UART3_DTE_CTS 0x01C4 0x048C 0x0000 0x2 0x0 +-#define MX6SLL_PAD_ECSPI2_MISO__CSI_MCLK 0x01C4 0x048C 0x0000 0x3 0x0 +-#define MX6SLL_PAD_ECSPI2_MISO__SD1_WP 0x01C4 0x048C 0x0774 0x4 0x2 +-#define MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x01C4 0x048C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x01C4 0x048C 0x076C 0x6 0x1 +-#define MX6SLL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x01C8 0x0490 0x0628 0x0 0x0 +-#define MX6SLL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x01C8 0x0490 0x0618 0x1 0x1 +-#define MX6SLL_PAD_ECSPI2_SS0__UART3_DCE_CTS 0x01C8 0x0490 0x0000 0x2 0x0 +-#define MX6SLL_PAD_ECSPI2_SS0__UART3_DTE_RTS 0x01C8 0x0490 0x0750 0x2 0x1 +-#define MX6SLL_PAD_ECSPI2_SS0__CSI_VSYNC 0x01C8 0x0490 0x05F8 0x3 0x1 +-#define MX6SLL_PAD_ECSPI2_SS0__SD1_CD_B 0x01C8 0x0490 0x0770 0x4 0x2 +-#define MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x01C8 0x0490 0x0000 0x5 0x0 +-#define MX6SLL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x01C8 0x0490 0x0000 0x6 0x0 +-#define MX6SLL_PAD_SD1_CLK__SD1_CLK 0x01CC 0x0494 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD1_CLK__KEY_COL0 0x01CC 0x0494 0x06A0 0x2 0x2 +-#define MX6SLL_PAD_SD1_CLK__EPDC_SDCE4 0x01CC 0x0494 0x0000 0x3 0x0 +-#define MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x01CC 0x0494 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD1_CMD__SD1_CMD 0x01D0 0x0498 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD1_CMD__KEY_ROW0 0x01D0 0x0498 0x06C0 0x2 0x2 +-#define MX6SLL_PAD_SD1_CMD__EPDC_SDCE5 0x01D0 0x0498 0x0000 0x3 0x0 +-#define MX6SLL_PAD_SD1_CMD__GPIO5_IO14 0x01D0 0x0498 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x01D4 0x049C 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD1_DATA0__KEY_COL1 0x01D4 0x049C 0x06A4 0x2 0x2 +-#define MX6SLL_PAD_SD1_DATA0__EPDC_SDCE6 0x01D4 0x049C 0x0000 0x3 0x0 +-#define MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x01D4 0x049C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x01D8 0x04A0 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD1_DATA1__KEY_ROW1 0x01D8 0x04A0 0x06C4 0x2 0x2 +-#define MX6SLL_PAD_SD1_DATA1__EPDC_SDCE7 0x01D8 0x04A0 0x0000 0x3 0x0 +-#define MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x01D8 0x04A0 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x01DC 0x04A4 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD1_DATA2__KEY_COL2 0x01DC 0x04A4 0x06A8 0x2 0x2 +-#define MX6SLL_PAD_SD1_DATA2__EPDC_SDCE8 0x01DC 0x04A4 0x0000 0x3 0x0 +-#define MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 0x01DC 0x04A4 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x01E0 0x04A8 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD1_DATA3__KEY_ROW2 0x01E0 0x04A8 0x06C8 0x2 0x2 +-#define MX6SLL_PAD_SD1_DATA3__EPDC_SDCE9 0x01E0 0x04A8 0x0000 0x3 0x0 +-#define MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 0x01E0 0x04A8 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x01E4 0x04AC 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD1_DATA4__KEY_COL3 0x01E4 0x04AC 0x06AC 0x2 0x2 +-#define MX6SLL_PAD_SD1_DATA4__EPDC_SDCLK_N 0x01E4 0x04AC 0x0000 0x3 0x0 +-#define MX6SLL_PAD_SD1_DATA4__UART4_DCE_RX 0x01E4 0x04AC 0x075C 0x4 0x6 +-#define MX6SLL_PAD_SD1_DATA4__UART4_DTE_TX 0x01E4 0x04AC 0x0000 0x4 0x0 +-#define MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x01E4 0x04AC 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x01E8 0x04B0 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD1_DATA5__KEY_ROW3 0x01E8 0x04B0 0x06CC 0x2 0x2 +-#define MX6SLL_PAD_SD1_DATA5__EPDC_SDOED 0x01E8 0x04B0 0x0000 0x3 0x0 +-#define MX6SLL_PAD_SD1_DATA5__UART4_DCE_TX 0x01E8 0x04B0 0x0000 0x4 0x0 +-#define MX6SLL_PAD_SD1_DATA5__UART4_DTE_RX 0x01E8 0x04B0 0x075C 0x4 0x7 +-#define MX6SLL_PAD_SD1_DATA5__GPIO5_IO09 0x01E8 0x04B0 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x01EC 0x04B4 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD1_DATA6__KEY_COL4 0x01EC 0x04B4 0x06B0 0x2 0x2 +-#define MX6SLL_PAD_SD1_DATA6__EPDC_SDOEZ 0x01EC 0x04B4 0x0000 0x3 0x0 +-#define MX6SLL_PAD_SD1_DATA6__UART4_DCE_RTS 0x01EC 0x04B4 0x0758 0x4 0x4 +-#define MX6SLL_PAD_SD1_DATA6__UART4_DTE_CTS 0x01EC 0x04B4 0x0000 0x4 0x0 +-#define MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x01EC 0x04B4 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x01F0 0x04B8 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD1_DATA7__KEY_ROW4 0x01F0 0x04B8 0x06D0 0x2 0x2 +-#define MX6SLL_PAD_SD1_DATA7__CCM_PMIC_READY 0x01F0 0x04B8 0x05AC 0x3 0x3 +-#define MX6SLL_PAD_SD1_DATA7__UART4_DCE_CTS 0x01F0 0x04B8 0x0000 0x4 0x0 +-#define MX6SLL_PAD_SD1_DATA7__UART4_DTE_RTS 0x01F0 0x04B8 0x0758 0x4 0x5 +-#define MX6SLL_PAD_SD1_DATA7__GPIO5_IO10 0x01F0 0x04B8 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD2_RESET__SD2_RESET 0x01F4 0x04BC 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD2_RESET__WDOG2_B 0x01F4 0x04BC 0x0000 0x2 0x0 +-#define MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x01F4 0x04BC 0x0000 0x3 0x0 +-#define MX6SLL_PAD_SD2_RESET__CSI_MCLK 0x01F4 0x04BC 0x0000 0x4 0x0 +-#define MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x01F4 0x04BC 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD2_CLK__SD2_CLK 0x01F8 0x04C0 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD2_CLK__AUD4_RXFS 0x01F8 0x04C0 0x0570 0x1 0x1 +-#define MX6SLL_PAD_SD2_CLK__ECSPI3_SCLK 0x01F8 0x04C0 0x0630 0x2 0x1 +-#define MX6SLL_PAD_SD2_CLK__CSI_DATA00 0x01F8 0x04C0 0x05C8 0x3 0x1 +-#define MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x01F8 0x04C0 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD2_CMD__SD2_CMD 0x01FC 0x04C4 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD2_CMD__AUD4_RXC 0x01FC 0x04C4 0x056C 0x1 0x1 +-#define MX6SLL_PAD_SD2_CMD__ECSPI3_SS0 0x01FC 0x04C4 0x0648 0x2 0x1 +-#define MX6SLL_PAD_SD2_CMD__CSI_DATA01 0x01FC 0x04C4 0x05CC 0x3 0x1 +-#define MX6SLL_PAD_SD2_CMD__EPIT1_OUT 0x01FC 0x04C4 0x0000 0x4 0x0 +-#define MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x01FC 0x04C4 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x0200 0x04C8 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD2_DATA0__AUD4_RXD 0x0200 0x04C8 0x0564 0x1 0x2 +-#define MX6SLL_PAD_SD2_DATA0__ECSPI3_MOSI 0x0200 0x04C8 0x063C 0x2 0x1 +-#define MX6SLL_PAD_SD2_DATA0__CSI_DATA02 0x0200 0x04C8 0x05D0 0x3 0x1 +-#define MX6SLL_PAD_SD2_DATA0__UART5_DCE_RTS 0x0200 0x04C8 0x0760 0x4 0x4 +-#define MX6SLL_PAD_SD2_DATA0__UART5_DTE_CTS 0x0200 0x04C8 0x0000 0x4 0x0 +-#define MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x0200 0x04C8 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x0204 0x04CC 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD2_DATA1__AUD4_TXC 0x0204 0x04CC 0x0574 0x1 0x2 +-#define MX6SLL_PAD_SD2_DATA1__ECSPI3_MISO 0x0204 0x04CC 0x0638 0x2 0x1 +-#define MX6SLL_PAD_SD2_DATA1__CSI_DATA03 0x0204 0x04CC 0x05D4 0x3 0x1 +-#define MX6SLL_PAD_SD2_DATA1__UART5_DCE_CTS 0x0204 0x04CC 0x0000 0x4 0x0 +-#define MX6SLL_PAD_SD2_DATA1__UART5_DTE_RTS 0x0204 0x04CC 0x0760 0x4 0x5 +-#define MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x0204 0x04CC 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x0208 0x04D0 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD2_DATA2__AUD4_TXFS 0x0208 0x04D0 0x0578 0x1 0x2 +-#define MX6SLL_PAD_SD2_DATA2__CSI_DATA04 0x0208 0x04D0 0x05D8 0x3 0x1 +-#define MX6SLL_PAD_SD2_DATA2__UART5_DCE_RX 0x0208 0x04D0 0x0764 0x4 0x4 +-#define MX6SLL_PAD_SD2_DATA2__UART5_DTE_TX 0x0208 0x04D0 0x0000 0x4 0x0 +-#define MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x0208 0x04D0 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x020C 0x04D4 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD2_DATA3__AUD4_TXD 0x020C 0x04D4 0x0568 0x1 0x2 +-#define MX6SLL_PAD_SD2_DATA3__CSI_DATA05 0x020C 0x04D4 0x05DC 0x3 0x1 +-#define MX6SLL_PAD_SD2_DATA3__UART5_DCE_TX 0x020C 0x04D4 0x0000 0x4 0x0 +-#define MX6SLL_PAD_SD2_DATA3__UART5_DTE_RX 0x020C 0x04D4 0x0764 0x4 0x5 +-#define MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x020C 0x04D4 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x0210 0x04D8 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD2_DATA4__SD3_DATA4 0x0210 0x04D8 0x0784 0x1 0x1 +-#define MX6SLL_PAD_SD2_DATA4__UART2_DCE_RX 0x0210 0x04D8 0x074C 0x2 0x2 +-#define MX6SLL_PAD_SD2_DATA4__UART2_DTE_TX 0x0210 0x04D8 0x0000 0x2 0x0 +-#define MX6SLL_PAD_SD2_DATA4__CSI_DATA06 0x0210 0x04D8 0x05E0 0x3 0x1 +-#define MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x0210 0x04D8 0x0000 0x4 0x0 +-#define MX6SLL_PAD_SD2_DATA4__GPIO5_IO02 0x0210 0x04D8 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x0214 0x04DC 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD2_DATA5__SD3_DATA5 0x0214 0x04DC 0x0788 0x1 0x1 +-#define MX6SLL_PAD_SD2_DATA5__UART2_DCE_TX 0x0214 0x04DC 0x0000 0x2 0x0 +-#define MX6SLL_PAD_SD2_DATA5__UART2_DTE_RX 0x0214 0x04DC 0x074C 0x2 0x3 +-#define MX6SLL_PAD_SD2_DATA5__CSI_DATA07 0x0214 0x04DC 0x05E4 0x3 0x1 +-#define MX6SLL_PAD_SD2_DATA5__SPDIF_IN 0x0214 0x04DC 0x0738 0x4 0x1 +-#define MX6SLL_PAD_SD2_DATA5__GPIO4_IO31 0x0214 0x04DC 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x0218 0x04E0 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD2_DATA6__SD3_DATA6 0x0218 0x04E0 0x078C 0x1 0x1 +-#define MX6SLL_PAD_SD2_DATA6__UART2_DCE_RTS 0x0218 0x04E0 0x0748 0x2 0x2 +-#define MX6SLL_PAD_SD2_DATA6__UART2_DTE_CTS 0x0218 0x04E0 0x0000 0x2 0x0 +-#define MX6SLL_PAD_SD2_DATA6__CSI_DATA08 0x0218 0x04E0 0x05E8 0x3 0x1 +-#define MX6SLL_PAD_SD2_DATA6__SD2_WP 0x0218 0x04E0 0x077C 0x4 0x1 +-#define MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x0218 0x04E0 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x021C 0x04E4 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD2_DATA7__SD3_DATA7 0x021C 0x04E4 0x0790 0x1 0x1 +-#define MX6SLL_PAD_SD2_DATA7__UART2_DCE_CTS 0x021C 0x04E4 0x0000 0x2 0x0 +-#define MX6SLL_PAD_SD2_DATA7__UART2_DTE_RTS 0x021C 0x04E4 0x0748 0x2 0x3 +-#define MX6SLL_PAD_SD2_DATA7__CSI_DATA09 0x021C 0x04E4 0x05EC 0x3 0x1 +-#define MX6SLL_PAD_SD2_DATA7__SD2_CD_B 0x021C 0x04E4 0x0778 0x4 0x1 +-#define MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x021C 0x04E4 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD3_CLK__SD3_CLK 0x0220 0x04E8 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD3_CLK__AUD5_RXFS 0x0220 0x04E8 0x0588 0x1 0x0 +-#define MX6SLL_PAD_SD3_CLK__KEY_COL5 0x0220 0x04E8 0x0694 0x2 0x0 +-#define MX6SLL_PAD_SD3_CLK__CSI_DATA10 0x0220 0x04E8 0x05B0 0x3 0x0 +-#define MX6SLL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x0220 0x04E8 0x0000 0x4 0x0 +-#define MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x0220 0x04E8 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD3_CLK__USB_OTG1_PWR 0x0220 0x04E8 0x0000 0x6 0x0 +-#define MX6SLL_PAD_SD3_CMD__SD3_CMD 0x0224 0x04EC 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD3_CMD__AUD5_RXC 0x0224 0x04EC 0x0584 0x1 0x0 +-#define MX6SLL_PAD_SD3_CMD__KEY_ROW5 0x0224 0x04EC 0x06B4 0x2 0x0 +-#define MX6SLL_PAD_SD3_CMD__CSI_DATA11 0x0224 0x04EC 0x05B4 0x3 0x0 +-#define MX6SLL_PAD_SD3_CMD__USB_OTG2_ID 0x0224 0x04EC 0x0560 0x4 0x1 +-#define MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x0224 0x04EC 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD3_CMD__USB_OTG2_PWR 0x0224 0x04EC 0x0000 0x6 0x0 +-#define MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x0228 0x04F0 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD3_DATA0__AUD5_RXD 0x0228 0x04F0 0x057C 0x1 0x0 +-#define MX6SLL_PAD_SD3_DATA0__KEY_COL6 0x0228 0x04F0 0x0698 0x2 0x0 +-#define MX6SLL_PAD_SD3_DATA0__CSI_DATA12 0x0228 0x04F0 0x05B8 0x3 0x0 +-#define MX6SLL_PAD_SD3_DATA0__USB_OTG1_ID 0x0228 0x04F0 0x055C 0x4 0x1 +-#define MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x0228 0x04F0 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x022C 0x04F4 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD3_DATA1__AUD5_TXC 0x022C 0x04F4 0x058C 0x1 0x0 +-#define MX6SLL_PAD_SD3_DATA1__KEY_ROW6 0x022C 0x04F4 0x06B8 0x2 0x0 +-#define MX6SLL_PAD_SD3_DATA1__CSI_DATA13 0x022C 0x04F4 0x05BC 0x3 0x0 +-#define MX6SLL_PAD_SD3_DATA1__SD1_VSELECT 0x022C 0x04F4 0x0000 0x4 0x0 +-#define MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x022C 0x04F4 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD3_DATA1__JTAG_DE_B 0x022C 0x04F4 0x0000 0x6 0x0 +-#define MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x0230 0x04F8 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD3_DATA2__AUD5_TXFS 0x0230 0x04F8 0x0590 0x1 0x0 +-#define MX6SLL_PAD_SD3_DATA2__KEY_COL7 0x0230 0x04F8 0x069C 0x2 0x0 +-#define MX6SLL_PAD_SD3_DATA2__CSI_DATA14 0x0230 0x04F8 0x05C0 0x3 0x0 +-#define MX6SLL_PAD_SD3_DATA2__EPIT1_OUT 0x0230 0x04F8 0x0000 0x4 0x0 +-#define MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x0230 0x04F8 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD3_DATA2__USB_OTG2_OC 0x0230 0x04F8 0x0768 0x6 0x0 +-#define MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x0234 0x04FC 0x0000 0x0 0x0 +-#define MX6SLL_PAD_SD3_DATA3__AUD5_TXD 0x0234 0x04FC 0x0580 0x1 0x0 +-#define MX6SLL_PAD_SD3_DATA3__KEY_ROW7 0x0234 0x04FC 0x06BC 0x2 0x0 +-#define MX6SLL_PAD_SD3_DATA3__CSI_DATA15 0x0234 0x04FC 0x05C4 0x3 0x0 +-#define MX6SLL_PAD_SD3_DATA3__EPIT2_OUT 0x0234 0x04FC 0x0000 0x4 0x0 +-#define MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x0234 0x04FC 0x0000 0x5 0x0 +-#define MX6SLL_PAD_SD3_DATA3__USB_OTG1_OC 0x0234 0x04FC 0x076C 0x6 0x0 +-#define MX6SLL_PAD_GPIO4_IO20__SD1_STROBE 0x0238 0x0500 0x0000 0x0 0x0 +-#define MX6SLL_PAD_GPIO4_IO20__AUD6_RXFS 0x0238 0x0500 0x05A0 0x2 0x0 +-#define MX6SLL_PAD_GPIO4_IO20__ECSPI4_SS0 0x0238 0x0500 0x065C 0x3 0x0 +-#define MX6SLL_PAD_GPIO4_IO20__GPT_CAPTURE1 0x0238 0x0500 0x0670 0x4 0x0 +-#define MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 0x0238 0x0500 0x0000 0x5 0x0 +-#define MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x023C 0x0504 0x0000 0x0 0x0 +-#define MX6SLL_PAD_GPIO4_IO21__AUD6_RXC 0x023C 0x0504 0x059C 0x2 0x0 +-#define MX6SLL_PAD_GPIO4_IO21__ECSPI4_SCLK 0x023C 0x0504 0x0650 0x3 0x0 +-#define MX6SLL_PAD_GPIO4_IO21__GPT_CAPTURE2 0x023C 0x0504 0x0674 0x4 0x0 +-#define MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 0x023C 0x0504 0x0000 0x5 0x0 +-#define MX6SLL_PAD_GPIO4_IO19__SD3_STROBE 0x0240 0x0508 0x0000 0x0 0x0 +-#define MX6SLL_PAD_GPIO4_IO19__AUD6_RXD 0x0240 0x0508 0x0594 0x2 0x0 +-#define MX6SLL_PAD_GPIO4_IO19__ECSPI4_MOSI 0x0240 0x0508 0x0658 0x3 0x0 +-#define MX6SLL_PAD_GPIO4_IO19__GPT_COMPARE1 0x0240 0x0508 0x0000 0x4 0x0 +-#define MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0x0240 0x0508 0x0000 0x5 0x0 +-#define MX6SLL_PAD_GPIO4_IO25__AUD6_TXC 0x0244 0x050C 0x05A4 0x2 0x0 +-#define MX6SLL_PAD_GPIO4_IO25__ECSPI4_MISO 0x0244 0x050C 0x0654 0x3 0x0 +-#define MX6SLL_PAD_GPIO4_IO25__GPT_COMPARE2 0x0244 0x050C 0x0000 0x4 0x0 +-#define MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x0244 0x050C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_GPIO4_IO18__AUD6_TXFS 0x0248 0x0510 0x05A8 0x2 0x0 +-#define MX6SLL_PAD_GPIO4_IO18__ECSPI4_SS1 0x0248 0x0510 0x0660 0x3 0x0 +-#define MX6SLL_PAD_GPIO4_IO18__GPT_COMPARE3 0x0248 0x0510 0x0000 0x4 0x0 +-#define MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x0248 0x0510 0x0000 0x5 0x0 +-#define MX6SLL_PAD_GPIO4_IO24__AUD6_TXD 0x024C 0x0514 0x0598 0x2 0x0 +-#define MX6SLL_PAD_GPIO4_IO24__ECSPI4_SS2 0x024C 0x0514 0x0664 0x3 0x0 +-#define MX6SLL_PAD_GPIO4_IO24__GPT_CLKIN 0x024C 0x0514 0x0678 0x4 0x0 +-#define MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x024C 0x0514 0x0000 0x5 0x0 +-#define MX6SLL_PAD_GPIO4_IO23__AUDIO_CLK_OUT 0x0250 0x0518 0x0000 0x2 0x0 +-#define MX6SLL_PAD_GPIO4_IO23__SD1_RESET 0x0250 0x0518 0x0000 0x3 0x0 +-#define MX6SLL_PAD_GPIO4_IO23__SD3_RESET 0x0250 0x0518 0x0000 0x4 0x0 +-#define MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0x0250 0x0518 0x0000 0x5 0x0 +-#define MX6SLL_PAD_GPIO4_IO17__USB_OTG1_ID 0x0254 0x051C 0x055C 0x2 0x2 +-#define MX6SLL_PAD_GPIO4_IO17__SD1_VSELECT 0x0254 0x051C 0x0000 0x3 0x0 +-#define MX6SLL_PAD_GPIO4_IO17__SD3_VSELECT 0x0254 0x051C 0x0000 0x4 0x0 +-#define MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0x0254 0x051C 0x0000 0x5 0x0 +-#define MX6SLL_PAD_GPIO4_IO22__SPDIF_IN 0x0258 0x0520 0x0738 0x2 0x0 +-#define MX6SLL_PAD_GPIO4_IO22__SD1_WP 0x0258 0x0520 0x0774 0x3 0x0 +-#define MX6SLL_PAD_GPIO4_IO22__SD3_WP 0x0258 0x0520 0x0794 0x4 0x1 +-#define MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x0258 0x0520 0x0000 0x5 0x0 +-#define MX6SLL_PAD_GPIO4_IO16__SPDIF_OUT 0x025C 0x0524 0x0000 0x2 0x0 +-#define MX6SLL_PAD_GPIO4_IO16__SD1_CD_B 0x025C 0x0524 0x0770 0x3 0x0 +-#define MX6SLL_PAD_GPIO4_IO16__SD3_CD_B 0x025C 0x0524 0x0780 0x4 0x1 +-#define MX6SLL_PAD_GPIO4_IO16__GPIO4_IO16 0x025C 0x0524 0x0000 0x5 0x0 +-#define MX6SLL_PAD_GPIO4_IO26__WDOG1_B 0x0260 0x0528 0x0000 0x2 0x0 +-#define MX6SLL_PAD_GPIO4_IO26__PWM4_OUT 0x0260 0x0528 0x0000 0x3 0x0 +-#define MX6SLL_PAD_GPIO4_IO26__CCM_PMIC_READY 0x0260 0x0528 0x05AC 0x4 0x1 +-#define MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 0x0260 0x0528 0x0000 0x5 0x0 +-#define MX6SLL_PAD_GPIO4_IO26__SPDIF_EXT_CLK 0x0260 0x0528 0x073C 0x6 0x0 +- +-#endif /* __DTS_IMX6SLL_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm/imx6sll.dtsi b/scripts/dtc/include-prefixes/arm/imx6sll.dtsi +deleted file mode 100644 +index 04f8d637a501..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sll.dtsi ++++ /dev/null +@@ -1,838 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2016 Freescale Semiconductor, Inc. +- * Copyright 2017-2018 NXP. +- * +- */ +- +-#include +-#include +-#include +-#include "imx6sll-pinfunc.h" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- gpio3 = &gpio4; +- gpio4 = &gpio5; +- gpio5 = &gpio6; +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- mmc0 = &usdhc1; +- mmc1 = &usdhc2; +- mmc2 = &usdhc3; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- serial4 = &uart5; +- spi0 = &ecspi1; +- spi1 = &ecspi2; +- spi3 = &ecspi3; +- spi4 = &ecspi4; +- usb0 = &usbotg1; +- usb1 = &usbotg2; +- usbphy0 = &usbphy1; +- usbphy1 = &usbphy2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <0>; +- next-level-cache = <&L2>; +- operating-points = < +- /* kHz uV */ +- 996000 1275000 +- 792000 1175000 +- 396000 1075000 +- 198000 975000 +- >; +- fsl,soc-operating-points = < +- /* ARM kHz SOC-PU uV */ +- 996000 1175000 +- 792000 1175000 +- 396000 1175000 +- 198000 1175000 +- >; +- clock-latency = <61036>; /* two CLK32 periods */ +- #cooling-cells = <2>; +- clocks = <&clks IMX6SLL_CLK_ARM>, +- <&clks IMX6SLL_CLK_PLL2_PFD2>, +- <&clks IMX6SLL_CLK_STEP>, +- <&clks IMX6SLL_CLK_PLL1_SW>, +- <&clks IMX6SLL_CLK_PLL1_SYS>; +- clock-names = "arm", "pll2_pfd2_396m", "step", +- "pll1_sw", "pll1_sys"; +- nvmem-cells = <&cpu_speed_grade>; +- nvmem-cell-names = "speed_grade"; +- }; +- }; +- +- ckil: clock-ckil { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "ckil"; +- }; +- +- osc: clock-osc-24m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "osc"; +- }; +- +- ipp_di0: clock-ipp-di0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- clock-output-names = "ipp_di0"; +- }; +- +- ipp_di1: clock-ipp-di1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- clock-output-names = "ipp_di1"; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&gpc>; +- ranges; +- +- ocram: sram@900000 { +- compatible = "mmio-sram"; +- reg = <0x00900000 0x20000>; +- }; +- +- intc: interrupt-controller@a01000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x00a01000 0x1000>, +- <0x00a00100 0x100>; +- interrupt-parent = <&intc>; +- }; +- +- L2: cache-controller@a02000 { +- compatible = "arm,pl310-cache"; +- reg = <0x00a02000 0x1000>; +- interrupts = ; +- cache-unified; +- cache-level = <2>; +- arm,tag-latency = <4 2 3>; +- arm,data-latency = <4 2 3>; +- }; +- +- aips1: bus@2000000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x02000000 0x100000>; +- ranges; +- +- spba: spba-bus@2000000 { +- compatible = "fsl,spba-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x02000000 0x40000>; +- ranges; +- +- spdif: spdif@2004000 { +- compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif"; +- reg = <0x02004000 0x4000>; +- interrupts = ; +- dmas = <&sdma 14 18 0>, <&sdma 15 18 0>; +- dma-names = "rx", "tx"; +- clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>, +- <&clks IMX6SLL_CLK_OSC>, +- <&clks IMX6SLL_CLK_SPDIF>, +- <&clks IMX6SLL_CLK_DUMMY>, +- <&clks IMX6SLL_CLK_DUMMY>, +- <&clks IMX6SLL_CLK_DUMMY>, +- <&clks IMX6SLL_CLK_IPG>, +- <&clks IMX6SLL_CLK_DUMMY>, +- <&clks IMX6SLL_CLK_DUMMY>, +- <&clks IMX6SLL_CLK_SPBA>; +- clock-names = "core", "rxtx0", +- "rxtx1", "rxtx2", +- "rxtx3", "rxtx4", +- "rxtx5", "rxtx6", +- "rxtx7", "dma"; +- status = "disabled"; +- }; +- +- ecspi1: spi@2008000 { +- compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; +- reg = <0x02008000 0x4000>; +- interrupts = ; +- dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; +- dma-names = "rx", "tx"; +- clocks = <&clks IMX6SLL_CLK_ECSPI1>, +- <&clks IMX6SLL_CLK_ECSPI1>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- ecspi2: spi@200c000 { +- compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; +- reg = <0x0200c000 0x4000>; +- interrupts = ; +- dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; +- dma-names = "rx", "tx"; +- clocks = <&clks IMX6SLL_CLK_ECSPI2>, +- <&clks IMX6SLL_CLK_ECSPI2>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- ecspi3: spi@2010000 { +- compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; +- reg = <0x02010000 0x4000>; +- interrupts = ; +- dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; +- dma-names = "rx", "tx"; +- clocks = <&clks IMX6SLL_CLK_ECSPI3>, +- <&clks IMX6SLL_CLK_ECSPI3>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- ecspi4: spi@2014000 { +- compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; +- reg = <0x02014000 0x4000>; +- interrupts = ; +- dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; +- dma-names = "rx", "tx"; +- clocks = <&clks IMX6SLL_CLK_ECSPI4>, +- <&clks IMX6SLL_CLK_ECSPI4>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart4: serial@2018000 { +- compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", +- "fsl,imx21-uart"; +- reg = <0x02018000 0x4000>; +- interrupts = ; +- dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; +- dma-names = "rx", "tx"; +- clocks = <&clks IMX6SLL_CLK_UART4_IPG>, +- <&clks IMX6SLL_CLK_UART4_SERIAL>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart1: serial@2020000 { +- compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", +- "fsl,imx21-uart"; +- reg = <0x02020000 0x4000>; +- interrupts = ; +- dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; +- dma-names = "rx", "tx"; +- clocks = <&clks IMX6SLL_CLK_UART1_IPG>, +- <&clks IMX6SLL_CLK_UART1_SERIAL>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart2: serial@2024000 { +- compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", +- "fsl,imx21-uart"; +- reg = <0x02024000 0x4000>; +- interrupts = ; +- dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; +- dma-names = "rx", "tx"; +- clocks = <&clks IMX6SLL_CLK_UART2_IPG>, +- <&clks IMX6SLL_CLK_UART2_SERIAL>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- ssi1: ssi@2028000 { +- compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; +- reg = <0x02028000 0x4000>; +- interrupts = ; +- dmas = <&sdma 37 22 0>, <&sdma 38 22 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- clocks = <&clks IMX6SLL_CLK_SSI1_IPG>, +- <&clks IMX6SLL_CLK_SSI1>; +- clock-names = "ipg", "baud"; +- status = "disabled"; +- }; +- +- ssi2: ssi@202c000 { +- compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; +- reg = <0x0202c000 0x4000>; +- interrupts = ; +- dmas = <&sdma 41 22 0>, <&sdma 42 22 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- clocks = <&clks IMX6SLL_CLK_SSI2_IPG>, +- <&clks IMX6SLL_CLK_SSI2>; +- clock-names = "ipg", "baud"; +- status = "disabled"; +- }; +- +- ssi3: ssi@2030000 { +- compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; +- reg = <0x02030000 0x4000>; +- interrupts = ; +- dmas = <&sdma 45 22 0>, <&sdma 46 22 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- clocks = <&clks IMX6SLL_CLK_SSI3_IPG>, +- <&clks IMX6SLL_CLK_SSI3>; +- clock-names = "ipg", "baud"; +- status = "disabled"; +- }; +- +- uart3: serial@2034000 { +- compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", +- "fsl,imx21-uart"; +- reg = <0x02034000 0x4000>; +- interrupts = ; +- dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; +- dma-name = "rx", "tx"; +- clocks = <&clks IMX6SLL_CLK_UART3_IPG>, +- <&clks IMX6SLL_CLK_UART3_SERIAL>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- }; +- +- pwm1: pwm@2080000 { +- compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; +- reg = <0x02080000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_PWM1>, +- <&clks IMX6SLL_CLK_PWM1>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- }; +- +- pwm2: pwm@2084000 { +- compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; +- reg = <0x02084000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_PWM2>, +- <&clks IMX6SLL_CLK_PWM2>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- }; +- +- pwm3: pwm@2088000 { +- compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; +- reg = <0x02088000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_PWM3>, +- <&clks IMX6SLL_CLK_PWM3>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- }; +- +- pwm4: pwm@208c000 { +- compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; +- reg = <0x0208c000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_PWM4>, +- <&clks IMX6SLL_CLK_PWM4>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- }; +- +- gpt1: timer@2098000 { +- compatible = "fsl,imx6sl-gpt"; +- reg = <0x02098000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_GPT_BUS>, +- <&clks IMX6SLL_CLK_GPT_SERIAL>; +- clock-names = "ipg", "per"; +- }; +- +- gpio1: gpio@209c000 { +- compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; +- reg = <0x0209c000 0x4000>; +- interrupts = , +- ; +- clocks = <&clks IMX6SLL_CLK_GPIO1>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>; +- }; +- +- gpio2: gpio@20a0000 { +- compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; +- reg = <0x020a0000 0x4000>; +- interrupts = , +- ; +- clocks = <&clks IMX6SLL_CLK_GPIO2>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 50 32>; +- }; +- +- gpio3: gpio@20a4000 { +- compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; +- reg = <0x020a4000 0x4000>; +- interrupts = , +- ; +- clocks = <&clks IMX6SLL_CLK_GPIO3>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>, +- <&iomuxc 16 101 2>, <&iomuxc 18 5 1>, +- <&iomuxc 21 6 11>; +- }; +- +- gpio4: gpio@20a8000 { +- compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; +- reg = <0x020a8000 0x4000>; +- interrupts = , +- ; +- clocks = <&clks IMX6SLL_CLK_GPIO4>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>, +- <&iomuxc 16 151 1>, <&iomuxc 17 149 1>, +- <&iomuxc 18 146 1>, <&iomuxc 19 144 1>, +- <&iomuxc 20 142 1>, <&iomuxc 21 143 1>, +- <&iomuxc 22 150 1>, <&iomuxc 23 148 1>, +- <&iomuxc 24 147 1>, <&iomuxc 25 145 1>, +- <&iomuxc 26 152 1>, <&iomuxc 27 125 1>, +- <&iomuxc 28 131 1>, <&iomuxc 29 134 1>, +- <&iomuxc 30 129 1>, <&iomuxc 31 133 1>; +- }; +- +- gpio5: gpio@20ac000 { +- compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; +- reg = <0x020ac000 0x4000>; +- interrupts = , +- ; +- clocks = <&clks IMX6SLL_CLK_GPIO5>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>, +- <&iomuxc 2 132 1>, <&iomuxc 3 130 1>, +- <&iomuxc 4 127 1>, <&iomuxc 5 126 1>, +- <&iomuxc 6 120 1>, <&iomuxc 7 123 1>, +- <&iomuxc 8 118 1>, <&iomuxc 9 122 1>, +- <&iomuxc 10 124 1>, <&iomuxc 11 117 1>, +- <&iomuxc 12 121 1>, <&iomuxc 13 119 1>, +- <&iomuxc 14 116 1>, <&iomuxc 15 115 1>, +- <&iomuxc 16 140 2>, <&iomuxc 18 136 1>, +- <&iomuxc 19 138 1>, <&iomuxc 20 139 1>, +- <&iomuxc 21 137 1>; +- }; +- +- gpio6: gpio@20b0000 { +- compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; +- reg = <0x020b0000 0x4000>; +- interrupts = , +- ; +- clocks = <&clks IMX6SLL_CLK_GPIO6>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- kpp: keypad@20b8000 { +- compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp"; +- reg = <0x020b8000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_KPP>; +- status = "disabled"; +- }; +- +- wdog1: watchdog@20bc000 { +- compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; +- reg = <0x020bc000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_WDOG1>; +- }; +- +- wdog2: watchdog@20c0000 { +- compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; +- reg = <0x020c0000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_WDOG2>; +- status = "disabled"; +- }; +- +- clks: clock-controller@20c4000 { +- compatible = "fsl,imx6sll-ccm"; +- reg = <0x020c4000 0x4000>; +- interrupts = , +- ; +- #clock-cells = <1>; +- clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; +- clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; +- +- assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>; +- assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>; +- }; +- +- anatop: anatop@20c8000 { +- compatible = "fsl,imx6sll-anatop", +- "fsl,imx6q-anatop", +- "syscon", "simple-mfd"; +- reg = <0x020c8000 0x4000>; +- interrupts = , +- , +- ; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_3p0: regulator-3p0@20c8120 { +- compatible = "fsl,anatop-regulator"; +- reg = <0x20c8120>; +- regulator-name = "vdd3p0"; +- regulator-min-microvolt = <2625000>; +- regulator-max-microvolt = <3400000>; +- anatop-reg-offset = <0x120>; +- anatop-vol-bit-shift = <8>; +- anatop-vol-bit-width = <5>; +- anatop-min-bit-val = <0>; +- anatop-min-voltage = <2625000>; +- anatop-max-voltage = <3400000>; +- anatop-enable-bit = <0>; +- }; +- +- tempmon: temperature-sensor { +- compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon"; +- interrupts = ; +- interrupt-parent = <&gpc>; +- fsl,tempmon = <&anatop>; +- nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; +- nvmem-cell-names = "calib", "temp_grade"; +- clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; +- }; +- }; +- +- usbphy1: usb-phy@20c9000 { +- compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", +- "fsl,imx23-usbphy"; +- reg = <0x020c9000 0x1000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_USBPHY1>; +- phy-3p0-supply = <®_3p0>; +- fsl,anatop = <&anatop>; +- }; +- +- usbphy2: usb-phy@20ca000 { +- compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", +- "fsl,imx23-usbphy"; +- reg = <0x020ca000 0x1000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_USBPHY2>; +- phy-reg_3p0-supply = <®_3p0>; +- fsl,anatop = <&anatop>; +- }; +- +- snvs: snvs@20cc000 { +- compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; +- reg = <0x020cc000 0x4000>; +- +- snvs_rtc: snvs-rtc-lp { +- compatible = "fsl,sec-v4.0-mon-rtc-lp"; +- regmap = <&snvs>; +- offset = <0x34>; +- interrupts = , +- ; +- }; +- +- snvs_poweroff: snvs-poweroff { +- compatible = "syscon-poweroff"; +- regmap = <&snvs>; +- offset = <0x38>; +- mask = <0x61>; +- status = "disabled"; +- }; +- +- snvs_pwrkey: snvs-powerkey { +- compatible = "fsl,sec-v4.0-pwrkey"; +- regmap = <&snvs>; +- interrupts = ; +- linux,keycode = ; +- wakeup-source; +- status = "disabled"; +- }; +- }; +- +- src: reset-controller@20d8000 { +- compatible = "fsl,imx6sll-src", "fsl,imx51-src"; +- reg = <0x020d8000 0x4000>; +- interrupts = , +- ; +- #reset-cells = <1>; +- }; +- +- gpc: interrupt-controller@20dc000 { +- compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc"; +- reg = <0x020dc000 0x4000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = ; +- interrupt-parent = <&intc>; +- }; +- +- iomuxc: pinctrl@20e0000 { +- compatible = "fsl,imx6sll-iomuxc"; +- reg = <0x020e0000 0x4000>; +- }; +- +- gpr: iomuxc-gpr@20e4000 { +- compatible = "fsl,imx6sll-iomuxc-gpr", +- "fsl,imx6q-iomuxc-gpr", "syscon"; +- reg = <0x020e4000 0x4000>; +- }; +- +- csi: csi@20e8000 { +- compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi"; +- reg = <0x020e8000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_DUMMY>, +- <&clks IMX6SLL_CLK_CSI>, +- <&clks IMX6SLL_CLK_DUMMY>; +- clock-names = "disp-axi", "csi_mclk", "disp_dcic"; +- status = "disabled"; +- }; +- +- sdma: dma-controller@20ec000 { +- compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma"; +- reg = <0x020ec000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_IPG>, +- <&clks IMX6SLL_CLK_SDMA>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- iram = <&ocram>; +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; +- }; +- +- pxp: pxp@20f0000 { +- compatible = "fsl,imx6sll-pxp", "fsl,imx6ull-pxp"; +- reg = <0x20f0000 0x4000>; +- interrupts = , +- ; +- clocks = <&clks IMX6SLL_CLK_PXP>; +- clock-names = "axi"; +- }; +- +- lcdif: lcd-controller@20f8000 { +- compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif"; +- reg = <0x020f8000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>, +- <&clks IMX6SLL_CLK_LCDIF_APB>, +- <&clks IMX6SLL_CLK_DUMMY>; +- clock-names = "pix", "axi", "disp_axi"; +- status = "disabled"; +- }; +- +- dcp: crypto@20fc000 { +- compatible = "fsl,imx28-dcp"; +- reg = <0x020fc000 0x4000>; +- interrupts = , +- , +- ; +- clocks = <&clks IMX6SLL_CLK_DCP>; +- clock-names = "dcp"; +- }; +- }; +- +- aips2: bus@2100000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x02100000 0x100000>; +- ranges; +- +- usbotg1: usb@2184000 { +- compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", +- "fsl,imx27-usb"; +- reg = <0x02184000 0x200>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_USBOH3>; +- fsl,usbphy = <&usbphy1>; +- fsl,usbmisc = <&usbmisc 0>; +- fsl,anatop = <&anatop>; +- ahb-burst-config = <0x0>; +- tx-burst-size-dword = <0x10>; +- rx-burst-size-dword = <0x10>; +- status = "disabled"; +- }; +- +- usbotg2: usb@2184200 { +- compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", +- "fsl,imx27-usb"; +- reg = <0x02184200 0x200>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_USBOH3>; +- fsl,usbphy = <&usbphy2>; +- fsl,usbmisc = <&usbmisc 1>; +- ahb-burst-config = <0x0>; +- tx-burst-size-dword = <0x10>; +- rx-burst-size-dword = <0x10>; +- status = "disabled"; +- }; +- +- usbmisc: usbmisc@2184800 { +- #index-cells = <1>; +- compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc", +- "fsl,imx6q-usbmisc"; +- reg = <0x02184800 0x200>; +- }; +- +- usdhc1: mmc@2190000 { +- compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; +- reg = <0x02190000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_USDHC1>, +- <&clks IMX6SLL_CLK_USDHC1>, +- <&clks IMX6SLL_CLK_USDHC1>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- fsl,tuning-step = <2>; +- fsl,tuning-start-tap = <20>; +- status = "disabled"; +- }; +- +- usdhc2: mmc@2194000 { +- compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; +- reg = <0x02194000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_USDHC2>, +- <&clks IMX6SLL_CLK_USDHC2>, +- <&clks IMX6SLL_CLK_USDHC2>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- fsl,tuning-step = <2>; +- fsl,tuning-start-tap = <20>; +- status = "disabled"; +- }; +- +- usdhc3: mmc@2198000 { +- compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; +- reg = <0x02198000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_USDHC3>, +- <&clks IMX6SLL_CLK_USDHC3>, +- <&clks IMX6SLL_CLK_USDHC3>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- fsl,tuning-step = <2>; +- fsl,tuning-start-tap = <20>; +- status = "disabled"; +- }; +- +- i2c1: i2c@21a0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; +- reg = <0x021a0000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_I2C1>; +- status = "disabled"; +- }; +- +- i2c2: i2c@21a4000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; +- reg = <0x021a4000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_I2C2>; +- status = "disabled"; +- }; +- +- i2c3: i2c@21a8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; +- reg = <0x021a8000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_I2C3>; +- status = "disabled"; +- }; +- +- mmdc: memory-controller@21b0000 { +- compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; +- reg = <0x021b0000 0x4000>; +- clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>; +- }; +- +- rngb: rng@21b4000 { +- compatible = "fsl,imx6sll-rngb", "fsl,imx25-rngb"; +- reg = <0x021b4000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SLL_CLK_DUMMY>; +- }; +- +- ocotp: efuse@21bc000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,imx6sll-ocotp", "syscon"; +- reg = <0x021bc000 0x4000>; +- clocks = <&clks IMX6SLL_CLK_OCOTP>; +- +- cpu_speed_grade: speed-grade@10 { +- reg = <0x10 4>; +- }; +- +- tempmon_calib: calib@38 { +- reg = <0x38 4>; +- }; +- +- tempmon_temp_grade: temp-grade@20 { +- reg = <0x20 4>; +- }; +- }; +- +- audmux: audmux@21d8000 { +- compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux"; +- reg = <0x021d8000 0x4000>; +- status = "disabled"; +- }; +- +- uart5: serial@21f4000 { +- compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", +- "fsl,imx21-uart"; +- reg = <0x021f4000 0x4000>; +- interrupts = ; +- dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; +- dma-names = "rx", "tx"; +- clocks = <&clks IMX6SLL_CLK_UART5_IPG>, +- <&clks IMX6SLL_CLK_UART5_SERIAL>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sx-nitrogen6sx.dts b/scripts/dtc/include-prefixes/arm/imx6sx-nitrogen6sx.dts +deleted file mode 100644 +index 66af78e83b70..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sx-nitrogen6sx.dts ++++ /dev/null +@@ -1,603 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright (C) 2016 Boundary Devices, Inc. +- */ +- +-/dts-v1/; +- +-#include "imx6sx.dtsi" +- +-/ { +- model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board"; +- compatible = "boundary,imx6sx-nitrogen6sx", "fsl,imx6sx"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; +- }; +- +- backlight-lvds { +- compatible = "pwm-backlight"; +- pwms = <&pwm4 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- power-supply = <®_3p3v>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_can1_3v3: regulator-can1-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "can1-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; +- }; +- +- reg_can2_3v3: regulator-can2-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "can2-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio4 24 GPIO_ACTIVE_LOW>; +- }; +- +- reg_usb_otg1_vbus: regulator-usb-otg1-vbus { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg1_vbus>; +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_wlan: regulator-wlan { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_wlan>; +- compatible = "regulator-fixed"; +- clocks = <&clks IMX6SX_CLK_CKO>; +- clock-names = "slow"; +- regulator-name = "wlan-en"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <70000>; +- gpio = <&gpio7 6 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sound { +- compatible = "fsl,imx-audio-sgtl5000"; +- model = "imx6sx-nitrogen6sx-sgtl5000"; +- cpu-dai = <&ssi1>; +- audio-codec = <&codec>; +- audio-routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- mux-int-port = <1>; +- mux-ext-port = <5>; +- }; +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- flash: m25p80@0 { +- compatible = "microchip,sst25vf016b"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0x0 0xc0000>; +- read-only; +- }; +- +- partition@c0000 { +- label = "env"; +- reg = <0xc0000 0x2000>; +- read-only; +- }; +- +- partition@c2000 { +- label = "Kernel"; +- reg = <0xc2000 0x11e000>; +- }; +- +- partition@1e0000 { +- label = "M4"; +- reg = <0x1e0000 0x20000>; +- }; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- phy-mode = "rgmii"; +- phy-handle = <ðphy1>; +- phy-supply = <®_3p3v>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy1: ethernet-phy@4 { +- reg = <4>; +- }; +- +- ethphy2: ethernet-phy@5 { +- reg = <5>; +- }; +- }; +-}; +- +-&fec2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet2>; +- phy-mode = "rgmii"; +- phy-handle = <ðphy2>; +- phy-supply = <®_3p3v>; +- fsl,magic-packet; +- status = "okay"; +-}; +- +-&flexcan1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- xceiver-supply = <®_can1_3v3>; +- status = "okay"; +-}; +- +-&flexcan2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- xceiver-supply = <®_can2_3v3>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- codec: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sgtl5000>; +- reg = <0x0a>; +- clocks = <&clks IMX6SX_CLK_CKO2>; +- VDDA-supply = <®_1p8v>; +- VDDIO-supply = <®_1p8v>; +- VDDD-supply = <®_1p8v>; +- assigned-clocks = <&clks IMX6SX_CLK_CKO2_SEL>, +- <&clks IMX6SX_CLK_CKO2>; +- assigned-clock-parents = <&clks IMX6SX_CLK_OSC>; +- assigned-clock-rates = <0>, <24000000>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio4 10 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pwm4 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +- status = "okay"; +-}; +- +-&ssi1 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbotg1 { +- vbus-supply = <®_usb_otg1_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg1>; +- status = "okay"; +-}; +- +-&usbotg2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg2>; +- dr_mode = "host"; +- disable-over-current; +- reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- keep-power-in-suspend; +- wakeup-source; +- status = "okay"; +-}; +- +-&usdhc3 { +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <4>; +- non-removable; +- keep-power-in-suspend; +- vmmc-supply = <®_wlan>; +- cap-power-off-card; +- cap-sdio-irq; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&gpio7>; +- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; +- }; +- +- wlcore: wlcore@2 { +- compatible = "ti,wl1271"; +- reg = <2>; +- interrupt-parent = <&gpio7>; +- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; +- ref-clock-frequency = <38400000>; +- }; +-}; +- +-&usdhc4 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc4_50mhz>; +- pinctrl-1 = <&pinctrl_usdhc4_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc4_200mhz>; +- bus-width = <8>; +- non-removable; +- vmmc-supply = <®_1p8v>; +- keep-power-in-suspend; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x1b0b0 +- MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x1b0b0 +- MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x1b0b0 +- MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x1b0b0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 +- MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 +- MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 +- MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x0b0b1 +- >; +- }; +- +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x1b0b0 +- MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x1b0b0 +- MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x30b1 +- MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x30b1 +- MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x30b1 +- MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x30b1 +- MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x30b1 +- MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x30b1 +- MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 +- MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 +- MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 +- MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 +- MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 +- MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 +- MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0xb0b0 +- MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0xb0b0 +- MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0xb0b0 +- >; +- }; +- +- pinctrl_enet2: enet2grp { +- fsl,pins = < +- MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x30b1 +- MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x30b1 +- MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x30b1 +- MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x30b1 +- MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x30b1 +- MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x30b1 +- MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 +- MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 +- MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 +- MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 +- MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 +- MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 +- MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0xb0b0 +- MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0xb0b0 +- MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0xb0b0 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 +- MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 +- MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x1b0b0 +- MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x0b0b0 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 +- MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 +- MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x0b0b0 +- >; +- }; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x1b0b0 +- MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x1b0b0 +- MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x1b0b0 +- MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x1b0b0 +- MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x1b0b0 +- MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x1b0b0 +- MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x1b0b0 +- MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x1b0b0 +- MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x1b0b0 +- MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x1b0b0 +- MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x000b0 +- MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x1b0b0 +- /* Test points */ +- MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x1b0b0 +- MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 +- MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 +- MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 +- MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0xb0b0 +- MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0xb0b0 +- MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0xb0b0 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x110b0 +- >; +- }; +- +- pinctrl_reg_wlan: reg-wlangrp { +- fsl,pins = < +- MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x1b0b0 +- MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x000b0 +- >; +- }; +- +- pinctrl_sgtl5000: sgtl5000grp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x000b0 +- MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x1b0b0 +- MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x1b0b0 +- MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0xb0b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 +- MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1 +- MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX 0x1b0b1 +- MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1 +- MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1 +- MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x1b0b1 +- MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg1: usbotg1grp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x1b0b0 +- MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x170b1 +- >; +- }; +- +- pinctrl_usbotg1_vbus: usbotg1-vbusgrp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x1b0b0 +- >; +- }; +- +- pinctrl_usbotg2: usbotg2grp { +- fsl,pins = < +- MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0xb0b0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 +- MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 +- MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 +- MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 +- MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 +- MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 +- MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071 +- MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17071 +- MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17071 +- MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17071 +- MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17071 +- MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17071 +- >; +- }; +- +- pinctrl_usdhc4_50mhz: usdhc4-50mhzgrp { +- fsl,pins = < +- MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071 +- MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071 +- MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17071 +- MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071 +- MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071 +- MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071 +- MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071 +- MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071 +- MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071 +- MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071 +- MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071 +- >; +- }; +- +- pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp { +- fsl,pins = < +- MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 +- MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 +- MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 +- MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 +- MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 +- MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 +- MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 +- MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 +- MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 +- MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 +- >; +- }; +- +- pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp { +- fsl,pins = < +- MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 +- MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 +- MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 +- MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 +- MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 +- MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 +- MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 +- MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 +- MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 +- MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sx-pinfunc.h b/scripts/dtc/include-prefixes/arm/imx6sx-pinfunc.h +deleted file mode 100644 +index f4dc46207954..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sx-pinfunc.h ++++ /dev/null +@@ -1,1668 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2014 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __DTS_IMX6SX_PINFUNC_H +-#define __DTS_IMX6SX_PINFUNC_H +- +-/* +- * The pin function ID is a tuple of +- * +- */ +-#define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1 +-#define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0 +-#define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0 +-#define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0 +-#define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0 +-#define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0 +-#define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0 +-#define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0 +-#define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1 +-#define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0 +-#define MX6SX_PAD_GPIO1_IO01__SPDIF_SR_CLK 0x0018 0x0360 0x0000 0x2 0x0 +-#define MX6SX_PAD_GPIO1_IO01__CCM_STOP 0x0018 0x0360 0x0000 0x3 0x0 +-#define MX6SX_PAD_GPIO1_IO01__WDOG3_WDOG_B 0x0018 0x0360 0x0000 0x4 0x0 +-#define MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x0018 0x0360 0x0000 0x5 0x0 +-#define MX6SX_PAD_GPIO1_IO01__SNVS_HP_WRAPPER_VIO_5_CTL 0x0018 0x0360 0x0000 0x6 0x0 +-#define MX6SX_PAD_GPIO1_IO01__PHY_DTB_0 0x0018 0x0360 0x0000 0x7 0x0 +-#define MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x001C 0x0364 0x07B0 0x0 0x1 +-#define MX6SX_PAD_GPIO1_IO02__USDHC1_CD_B 0x001C 0x0364 0x0864 0x1 0x1 +-#define MX6SX_PAD_GPIO1_IO02__CSI2_MCLK 0x001C 0x0364 0x0000 0x2 0x0 +-#define MX6SX_PAD_GPIO1_IO02__CCM_DI0_EXT_CLK 0x001C 0x0364 0x0000 0x3 0x0 +-#define MX6SX_PAD_GPIO1_IO02__WDOG1_WDOG_B 0x001C 0x0364 0x0000 0x4 0x0 +-#define MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x001C 0x0364 0x0000 0x5 0x0 +-#define MX6SX_PAD_GPIO1_IO02__CCM_REF_EN_B 0x001C 0x0364 0x0000 0x6 0x0 +-#define MX6SX_PAD_GPIO1_IO02__PHY_TDI 0x001C 0x0364 0x0000 0x7 0x0 +-#define MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x0020 0x0368 0x07B4 0x0 0x1 +-#define MX6SX_PAD_GPIO1_IO03__USDHC1_WP 0x0020 0x0368 0x0868 0x1 0x1 +-#define MX6SX_PAD_GPIO1_IO03__ENET1_REF_CLK_25M 0x0020 0x0368 0x0000 0x2 0x0 +-#define MX6SX_PAD_GPIO1_IO03__CCM_DI1_EXT_CLK 0x0020 0x0368 0x0000 0x3 0x0 +-#define MX6SX_PAD_GPIO1_IO03__WDOG2_WDOG_B 0x0020 0x0368 0x0000 0x4 0x0 +-#define MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x0020 0x0368 0x0000 0x5 0x0 +-#define MX6SX_PAD_GPIO1_IO03__CCM_PLL3_BYP 0x0020 0x0368 0x0000 0x6 0x0 +-#define MX6SX_PAD_GPIO1_IO03__PHY_TCK 0x0020 0x0368 0x0000 0x7 0x0 +-#define MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x0024 0x036C 0x0000 0x0 0x0 +-#define MX6SX_PAD_GPIO1_IO04__UART1_DTE_RX 0x0024 0x036C 0x0830 0x0 0x0 +-#define MX6SX_PAD_GPIO1_IO04__USDHC2_RESET_B 0x0024 0x036C 0x0000 0x1 0x0 +-#define MX6SX_PAD_GPIO1_IO04__ENET1_MDC 0x0024 0x036C 0x0000 0x2 0x0 +-#define MX6SX_PAD_GPIO1_IO04__OSC32K_32K_OUT 0x0024 0x036C 0x0000 0x3 0x0 +-#define MX6SX_PAD_GPIO1_IO04__ENET2_REF_CLK2 0x0024 0x036C 0x076C 0x4 0x0 +-#define MX6SX_PAD_GPIO1_IO04__GPIO1_IO_4 0x0024 0x036C 0x0000 0x5 0x0 +-#define MX6SX_PAD_GPIO1_IO04__CCM_PLL2_BYP 0x0024 0x036C 0x0000 0x6 0x0 +-#define MX6SX_PAD_GPIO1_IO04__PHY_TMS 0x0024 0x036C 0x0000 0x7 0x0 +-#define MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x0028 0x0370 0x0830 0x0 0x1 +-#define MX6SX_PAD_GPIO1_IO05__UART1_DTE_TX 0x0028 0x0370 0x0000 0x0 0x0 +-#define MX6SX_PAD_GPIO1_IO05__USDHC2_VSELECT 0x0028 0x0370 0x0000 0x1 0x0 +-#define MX6SX_PAD_GPIO1_IO05__ENET1_MDIO 0x0028 0x0370 0x0764 0x2 0x0 +-#define MX6SX_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK 0x0028 0x0370 0x0000 0x3 0x0 +-#define MX6SX_PAD_GPIO1_IO05__ENET1_REF_CLK1 0x0028 0x0370 0x0760 0x4 0x0 +-#define MX6SX_PAD_GPIO1_IO05__GPIO1_IO_5 0x0028 0x0370 0x0000 0x5 0x0 +-#define MX6SX_PAD_GPIO1_IO05__SRC_TESTER_ACK 0x0028 0x0370 0x0000 0x6 0x0 +-#define MX6SX_PAD_GPIO1_IO05__PHY_TDO 0x0028 0x0370 0x0000 0x7 0x0 +-#define MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x002C 0x0374 0x0000 0x0 0x0 +-#define MX6SX_PAD_GPIO1_IO06__UART2_DTE_RX 0x002C 0x0374 0x0838 0x0 0x0 +-#define MX6SX_PAD_GPIO1_IO06__USDHC2_CD_B 0x002C 0x0374 0x086C 0x1 0x1 +-#define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0 +-#define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0 +-#define MX6SX_PAD_GPIO1_IO06__UART1_DCE_RTS 0x002C 0x0374 0x082C 0x4 0x0 +-#define MX6SX_PAD_GPIO1_IO06__UART1_DTE_CTS 0x002C 0x0374 0x0000 0x4 0x0 +-#define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0 +-#define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0 +-#define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0 +-#define MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x0030 0x0378 0x0838 0x0 0x1 +-#define MX6SX_PAD_GPIO1_IO07__UART2_DTE_TX 0x0030 0x0378 0x0000 0x0 0x0 +-#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1 +-#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0 +-#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0 +-#define MX6SX_PAD_GPIO1_IO07__UART1_DCE_CTS 0x0030 0x0378 0x0000 0x4 0x0 +-#define MX6SX_PAD_GPIO1_IO07__UART1_DTE_RTS 0x0030 0x0378 0x082C 0x4 0x1 +-#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0 +-#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0 +-#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0 +-#define MX6SX_PAD_GPIO1_IO07__VDEC_DEBUG_44 0x0030 0x0378 0x0000 0x8 0x0 +-#define MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x0034 0x037C 0x0860 0x0 0x0 +-#define MX6SX_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0034 0x037C 0x0000 0x1 0x0 +-#define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0 +-#define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1 +-#define MX6SX_PAD_GPIO1_IO08__UART2_DCE_RTS 0x0034 0x037C 0x0834 0x4 0x0 +-#define MX6SX_PAD_GPIO1_IO08__UART2_DTE_CTS 0x0034 0x037C 0x0000 0x4 0x0 +-#define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0 +-#define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0 +-#define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0 +-#define MX6SX_PAD_GPIO1_IO08__VDEC_DEBUG_43 0x0034 0x037C 0x0000 0x8 0x0 +-#define MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR 0x0038 0x0380 0x0000 0x0 0x0 +-#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0 +-#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0 +-#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0 +-#define MX6SX_PAD_GPIO1_IO09__UART2_DCE_CTS 0x0038 0x0380 0x0000 0x4 0x0 +-#define MX6SX_PAD_GPIO1_IO09__UART2_DTE_RTS 0x0038 0x0380 0x0834 0x4 0x1 +-#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0 +-#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0 +-#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0 +-#define MX6SX_PAD_GPIO1_IO09__VDEC_DEBUG_42 0x0038 0x0380 0x0000 0x8 0x0 +-#define MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x003C 0x0384 0x0624 0x0 0x0 +-#define MX6SX_PAD_GPIO1_IO10__SPDIF_EXT_CLK 0x003C 0x0384 0x0828 0x1 0x0 +-#define MX6SX_PAD_GPIO1_IO10__PWM1_OUT 0x003C 0x0384 0x0000 0x2 0x0 +-#define MX6SX_PAD_GPIO1_IO10__CCM_OUT1 0x003C 0x0384 0x0000 0x3 0x0 +-#define MX6SX_PAD_GPIO1_IO10__CSI1_FIELD 0x003C 0x0384 0x070C 0x4 0x1 +-#define MX6SX_PAD_GPIO1_IO10__GPIO1_IO_10 0x003C 0x0384 0x0000 0x5 0x0 +-#define MX6SX_PAD_GPIO1_IO10__CSU_CSU_INT_DEB 0x003C 0x0384 0x0000 0x6 0x0 +-#define MX6SX_PAD_GPIO1_IO10__OBSERVE_MUX_OUT_3 0x003C 0x0384 0x0000 0x7 0x0 +-#define MX6SX_PAD_GPIO1_IO10__VDEC_DEBUG_41 0x003C 0x0384 0x0000 0x8 0x0 +-#define MX6SX_PAD_GPIO1_IO11__USB_OTG2_OC 0x0040 0x0388 0x085C 0x0 0x0 +-#define MX6SX_PAD_GPIO1_IO11__SPDIF_IN 0x0040 0x0388 0x0824 0x1 0x2 +-#define MX6SX_PAD_GPIO1_IO11__PWM2_OUT 0x0040 0x0388 0x0000 0x2 0x0 +-#define MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x0040 0x0388 0x0000 0x3 0x0 +-#define MX6SX_PAD_GPIO1_IO11__MLB_DATA 0x0040 0x0388 0x07EC 0x4 0x0 +-#define MX6SX_PAD_GPIO1_IO11__GPIO1_IO_11 0x0040 0x0388 0x0000 0x5 0x0 +-#define MX6SX_PAD_GPIO1_IO11__CSU_CSU_ALARM_AUT_0 0x0040 0x0388 0x0000 0x6 0x0 +-#define MX6SX_PAD_GPIO1_IO11__OBSERVE_MUX_OUT_2 0x0040 0x0388 0x0000 0x7 0x0 +-#define MX6SX_PAD_GPIO1_IO11__VDEC_DEBUG_40 0x0040 0x0388 0x0000 0x8 0x0 +-#define MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR 0x0044 0x038C 0x0000 0x0 0x0 +-#define MX6SX_PAD_GPIO1_IO12__SPDIF_OUT 0x0044 0x038C 0x0000 0x1 0x0 +-#define MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x0044 0x038C 0x0000 0x2 0x0 +-#define MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x0044 0x038C 0x0000 0x3 0x0 +-#define MX6SX_PAD_GPIO1_IO12__MLB_CLK 0x0044 0x038C 0x07E8 0x4 0x0 +-#define MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x0044 0x038C 0x0000 0x5 0x0 +-#define MX6SX_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT_1 0x0044 0x038C 0x0000 0x6 0x0 +-#define MX6SX_PAD_GPIO1_IO12__OBSERVE_MUX_OUT_1 0x0044 0x038C 0x0000 0x7 0x0 +-#define MX6SX_PAD_GPIO1_IO12__VDEC_DEBUG_39 0x0044 0x038C 0x0000 0x8 0x0 +-#define MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x0048 0x0390 0x0000 0x0 0x0 +-#define MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x0048 0x0390 0x0628 0x1 0x0 +-#define MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x0048 0x0390 0x0000 0x2 0x0 +-#define MX6SX_PAD_GPIO1_IO13__CCM_OUT2 0x0048 0x0390 0x0000 0x3 0x0 +-#define MX6SX_PAD_GPIO1_IO13__MLB_SIG 0x0048 0x0390 0x07F0 0x4 0x0 +-#define MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 0x0048 0x0390 0x0000 0x5 0x0 +-#define MX6SX_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT_2 0x0048 0x0390 0x0000 0x6 0x0 +-#define MX6SX_PAD_GPIO1_IO13__OBSERVE_MUX_OUT_0 0x0048 0x0390 0x0000 0x7 0x0 +-#define MX6SX_PAD_GPIO1_IO13__VDEC_DEBUG_38 0x0048 0x0390 0x0000 0x8 0x0 +-#define MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x004C 0x0394 0x06A8 0x0 0x0 +-#define MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x004C 0x0394 0x078C 0x1 0x1 +-#define MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x004C 0x0394 0x0684 0x2 0x1 +-#define MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x004C 0x0394 0x07A8 0x3 0x0 +-#define MX6SX_PAD_CSI_DATA00__UART6_RI_B 0x004C 0x0394 0x0000 0x4 0x0 +-#define MX6SX_PAD_CSI_DATA00__GPIO1_IO_14 0x004C 0x0394 0x0000 0x5 0x0 +-#define MX6SX_PAD_CSI_DATA00__WEIM_DATA_23 0x004C 0x0394 0x0000 0x6 0x0 +-#define MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x004C 0x0394 0x0800 0x7 0x0 +-#define MX6SX_PAD_CSI_DATA00__VADC_DATA_4 0x004C 0x0394 0x0000 0x8 0x0 +-#define MX6SX_PAD_CSI_DATA00__MMDC_DEBUG_37 0x004C 0x0394 0x0000 0x9 0x0 +-#define MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x0050 0x0398 0x06AC 0x0 0x0 +-#define MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x0050 0x0398 0x077C 0x1 0x1 +-#define MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x0050 0x0398 0x0688 0x2 0x1 +-#define MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x0050 0x0398 0x07AC 0x3 0x0 +-#define MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x0050 0x0398 0x0000 0x4 0x0 +-#define MX6SX_PAD_CSI_DATA01__GPIO1_IO_15 0x0050 0x0398 0x0000 0x5 0x0 +-#define MX6SX_PAD_CSI_DATA01__WEIM_DATA_22 0x0050 0x0398 0x0000 0x6 0x0 +-#define MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x0050 0x0398 0x0804 0x7 0x0 +-#define MX6SX_PAD_CSI_DATA01__VADC_DATA_5 0x0050 0x0398 0x0000 0x8 0x0 +-#define MX6SX_PAD_CSI_DATA01__MMDC_DEBUG_38 0x0050 0x0398 0x0000 0x9 0x0 +-#define MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x0054 0x039C 0x06B0 0x0 0x0 +-#define MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x0054 0x039C 0x0788 0x1 0x1 +-#define MX6SX_PAD_CSI_DATA02__AUDMUX_AUD6_RXC 0x0054 0x039C 0x067C 0x2 0x1 +-#define MX6SX_PAD_CSI_DATA02__KPP_COL_5 0x0054 0x039C 0x07C8 0x3 0x0 +-#define MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x0054 0x039C 0x0000 0x4 0x0 +-#define MX6SX_PAD_CSI_DATA02__GPIO1_IO_16 0x0054 0x039C 0x0000 0x5 0x0 +-#define MX6SX_PAD_CSI_DATA02__WEIM_DATA_21 0x0054 0x039C 0x0000 0x6 0x0 +-#define MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x0054 0x039C 0x07F4 0x7 0x0 +-#define MX6SX_PAD_CSI_DATA02__VADC_DATA_6 0x0054 0x039C 0x0000 0x8 0x0 +-#define MX6SX_PAD_CSI_DATA02__MMDC_DEBUG_39 0x0054 0x039C 0x0000 0x9 0x0 +-#define MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x0058 0x03A0 0x06B4 0x0 0x0 +-#define MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x0058 0x03A0 0x0778 0x1 0x1 +-#define MX6SX_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS 0x0058 0x03A0 0x0680 0x2 0x1 +-#define MX6SX_PAD_CSI_DATA03__KPP_ROW_5 0x0058 0x03A0 0x07D4 0x3 0x0 +-#define MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x0058 0x03A0 0x0000 0x4 0x0 +-#define MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x0058 0x03A0 0x0000 0x5 0x0 +-#define MX6SX_PAD_CSI_DATA03__WEIM_DATA_20 0x0058 0x03A0 0x0000 0x6 0x0 +-#define MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x0058 0x03A0 0x07FC 0x7 0x0 +-#define MX6SX_PAD_CSI_DATA03__VADC_DATA_7 0x0058 0x03A0 0x0000 0x8 0x0 +-#define MX6SX_PAD_CSI_DATA03__MMDC_DEBUG_40 0x0058 0x03A0 0x0000 0x9 0x0 +-#define MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x005C 0x03A4 0x06B8 0x0 0x0 +-#define MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x005C 0x03A4 0x0794 0x1 0x1 +-#define MX6SX_PAD_CSI_DATA04__SPDIF_OUT 0x005C 0x03A4 0x0000 0x2 0x0 +-#define MX6SX_PAD_CSI_DATA04__KPP_COL_6 0x005C 0x03A4 0x07CC 0x3 0x0 +-#define MX6SX_PAD_CSI_DATA04__UART6_DCE_RX 0x005C 0x03A4 0x0858 0x4 0x0 +-#define MX6SX_PAD_CSI_DATA04__UART6_DTE_TX 0x005C 0x03A4 0x0000 0x4 0x0 +-#define MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x005C 0x03A4 0x0000 0x5 0x0 +-#define MX6SX_PAD_CSI_DATA04__WEIM_DATA_19 0x005C 0x03A4 0x0000 0x6 0x0 +-#define MX6SX_PAD_CSI_DATA04__PWM5_OUT 0x005C 0x03A4 0x0000 0x7 0x0 +-#define MX6SX_PAD_CSI_DATA04__VADC_DATA_8 0x005C 0x03A4 0x0000 0x8 0x0 +-#define MX6SX_PAD_CSI_DATA04__MMDC_DEBUG_41 0x005C 0x03A4 0x0000 0x9 0x0 +-#define MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x0060 0x03A8 0x06BC 0x0 0x0 +-#define MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x0060 0x03A8 0x07A0 0x1 0x1 +-#define MX6SX_PAD_CSI_DATA05__SPDIF_IN 0x0060 0x03A8 0x0824 0x2 0x1 +-#define MX6SX_PAD_CSI_DATA05__KPP_ROW_6 0x0060 0x03A8 0x07D8 0x3 0x0 +-#define MX6SX_PAD_CSI_DATA05__UART6_DCE_TX 0x0060 0x03A8 0x0000 0x4 0x0 +-#define MX6SX_PAD_CSI_DATA05__UART6_DTE_RX 0x0060 0x03A8 0x0858 0x4 0x1 +-#define MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x0060 0x03A8 0x0000 0x5 0x0 +-#define MX6SX_PAD_CSI_DATA05__WEIM_DATA_18 0x0060 0x03A8 0x0000 0x6 0x0 +-#define MX6SX_PAD_CSI_DATA05__PWM6_OUT 0x0060 0x03A8 0x0000 0x7 0x0 +-#define MX6SX_PAD_CSI_DATA05__VADC_DATA_9 0x0060 0x03A8 0x0000 0x8 0x0 +-#define MX6SX_PAD_CSI_DATA05__MMDC_DEBUG_42 0x0060 0x03A8 0x0000 0x9 0x0 +-#define MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x0064 0x03AC 0x06C0 0x0 0x0 +-#define MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x0064 0x03AC 0x0798 0x1 0x1 +-#define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2 +-#define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0 +-#define MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS 0x0064 0x03AC 0x0854 0x4 0x0 +-#define MX6SX_PAD_CSI_DATA06__UART6_DTE_CTS 0x0064 0x03AC 0x0000 0x4 0x0 +-#define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0 +-#define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0 +-#define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0 +-#define MX6SX_PAD_CSI_DATA06__VADC_DATA_10 0x0064 0x03AC 0x0000 0x8 0x0 +-#define MX6SX_PAD_CSI_DATA06__MMDC_DEBUG_43 0x0064 0x03AC 0x0000 0x9 0x0 +-#define MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x0068 0x03B0 0x06C4 0x0 0x0 +-#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1 +-#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2 +-#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0 +-#define MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS 0x0068 0x03B0 0x0000 0x4 0x0 +-#define MX6SX_PAD_CSI_DATA07__UART6_DTE_RTS 0x0068 0x03B0 0x0854 0x4 0x1 +-#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0 +-#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0 +-#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0 +-#define MX6SX_PAD_CSI_DATA07__VADC_DATA_11 0x0068 0x03B0 0x0000 0x8 0x0 +-#define MX6SX_PAD_CSI_DATA07__MMDC_DEBUG_44 0x0068 0x03B0 0x0000 0x9 0x0 +-#define MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x006C 0x03B4 0x0700 0x0 0x0 +-#define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1 +-#define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1 +-#define MX6SX_PAD_CSI_HSYNC__UART4_DCE_RTS 0x006C 0x03B4 0x0844 0x3 0x2 +-#define MX6SX_PAD_CSI_HSYNC__UART4_DTE_CTS 0x006C 0x03B4 0x0000 0x3 0x0 +-#define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0 +-#define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0 +-#define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0 +-#define MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x006C 0x03B4 0x0000 0x7 0x0 +-#define MX6SX_PAD_CSI_HSYNC__VADC_DATA_2 0x006C 0x03B4 0x0000 0x8 0x0 +-#define MX6SX_PAD_CSI_HSYNC__MMDC_DEBUG_35 0x006C 0x03B4 0x0000 0x9 0x0 +-#define MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x0070 0x03B8 0x0000 0x0 0x0 +-#define MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x0070 0x03B8 0x0784 0x1 0x1 +-#define MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT 0x0070 0x03B8 0x0000 0x2 0x0 +-#define MX6SX_PAD_CSI_MCLK__UART4_DCE_RX 0x0070 0x03B8 0x0848 0x3 0x2 +-#define MX6SX_PAD_CSI_MCLK__UART4_DTE_TX 0x0070 0x03B8 0x0000 0x3 0x0 +-#define MX6SX_PAD_CSI_MCLK__ANATOP_32K_OUT 0x0070 0x03B8 0x0000 0x4 0x0 +-#define MX6SX_PAD_CSI_MCLK__GPIO1_IO_23 0x0070 0x03B8 0x0000 0x5 0x0 +-#define MX6SX_PAD_CSI_MCLK__WEIM_DATA_26 0x0070 0x03B8 0x0000 0x6 0x0 +-#define MX6SX_PAD_CSI_MCLK__CSI1_FIELD 0x0070 0x03B8 0x070C 0x7 0x0 +-#define MX6SX_PAD_CSI_MCLK__VADC_DATA_1 0x0070 0x03B8 0x0000 0x8 0x0 +-#define MX6SX_PAD_CSI_MCLK__MMDC_DEBUG_34 0x0070 0x03B8 0x0000 0x9 0x0 +-#define MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x0074 0x03BC 0x0704 0x0 0x0 +-#define MX6SX_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK 0x0074 0x03BC 0x0780 0x1 0x1 +-#define MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x0074 0x03BC 0x0000 0x2 0x0 +-#define MX6SX_PAD_CSI_PIXCLK__UART4_DCE_TX 0x0074 0x03BC 0x0000 0x3 0x0 +-#define MX6SX_PAD_CSI_PIXCLK__UART4_DTE_RX 0x0074 0x03BC 0x0848 0x3 0x3 +-#define MX6SX_PAD_CSI_PIXCLK__ANATOP_24M_OUT 0x0074 0x03BC 0x0000 0x4 0x0 +-#define MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x0074 0x03BC 0x0000 0x5 0x0 +-#define MX6SX_PAD_CSI_PIXCLK__WEIM_DATA_27 0x0074 0x03BC 0x0000 0x6 0x0 +-#define MX6SX_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK 0x0074 0x03BC 0x0784 0x7 0x2 +-#define MX6SX_PAD_CSI_PIXCLK__VADC_CLK 0x0074 0x03BC 0x0000 0x8 0x0 +-#define MX6SX_PAD_CSI_PIXCLK__MMDC_DEBUG_33 0x0074 0x03BC 0x0000 0x9 0x0 +-#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0 +-#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1 +-#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1 +-#define MX6SX_PAD_CSI_VSYNC__UART4_DCE_CTS 0x0078 0x03C0 0x0000 0x3 0x0 +-#define MX6SX_PAD_CSI_VSYNC__UART4_DTE_RTS 0x0078 0x03C0 0x0844 0x3 0x3 +-#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0 +-#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0 +-#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0 +-#define MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x0078 0x03C0 0x07F8 0x7 0x0 +-#define MX6SX_PAD_CSI_VSYNC__VADC_DATA_3 0x0078 0x03C0 0x0000 0x8 0x0 +-#define MX6SX_PAD_CSI_VSYNC__MMDC_DEBUG_36 0x0078 0x03C0 0x0000 0x9 0x0 +-#define MX6SX_PAD_ENET1_COL__ENET1_COL 0x007C 0x03C4 0x0000 0x0 0x0 +-#define MX6SX_PAD_ENET1_COL__ENET2_MDC 0x007C 0x03C4 0x0000 0x1 0x0 +-#define MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x007C 0x03C4 0x0654 0x2 0x1 +-#define MX6SX_PAD_ENET1_COL__UART1_RI_B 0x007C 0x03C4 0x0000 0x3 0x0 +-#define MX6SX_PAD_ENET1_COL__SPDIF_EXT_CLK 0x007C 0x03C4 0x0828 0x4 0x1 +-#define MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x007C 0x03C4 0x0000 0x5 0x0 +-#define MX6SX_PAD_ENET1_COL__CSI2_DATA_23 0x007C 0x03C4 0x0000 0x6 0x0 +-#define MX6SX_PAD_ENET1_COL__LCDIF2_DATA_16 0x007C 0x03C4 0x0000 0x7 0x0 +-#define MX6SX_PAD_ENET1_COL__VDEC_DEBUG_37 0x007C 0x03C4 0x0000 0x8 0x0 +-#define MX6SX_PAD_ENET1_COL__PCIE_CTRL_DEBUG_31 0x007C 0x03C4 0x0000 0x9 0x0 +-#define MX6SX_PAD_ENET1_CRS__ENET1_CRS 0x0080 0x03C8 0x0000 0x0 0x0 +-#define MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0x0080 0x03C8 0x0770 0x1 0x1 +-#define MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x0080 0x03C8 0x0648 0x2 0x1 +-#define MX6SX_PAD_ENET1_CRS__UART1_DCD_B 0x0080 0x03C8 0x0000 0x3 0x0 +-#define MX6SX_PAD_ENET1_CRS__SPDIF_LOCK 0x0080 0x03C8 0x0000 0x4 0x0 +-#define MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x0080 0x03C8 0x0000 0x5 0x0 +-#define MX6SX_PAD_ENET1_CRS__CSI2_DATA_22 0x0080 0x03C8 0x0000 0x6 0x0 +-#define MX6SX_PAD_ENET1_CRS__LCDIF2_DATA_17 0x0080 0x03C8 0x0000 0x7 0x0 +-#define MX6SX_PAD_ENET1_CRS__VDEC_DEBUG_36 0x0080 0x03C8 0x0000 0x8 0x0 +-#define MX6SX_PAD_ENET1_CRS__PCIE_CTRL_DEBUG_30 0x0080 0x03C8 0x0000 0x9 0x0 +-#define MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x0084 0x03CC 0x0000 0x0 0x0 +-#define MX6SX_PAD_ENET1_MDC__ENET2_MDC 0x0084 0x03CC 0x0000 0x1 0x0 +-#define MX6SX_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS 0x0084 0x03CC 0x0638 0x2 0x1 +-#define MX6SX_PAD_ENET1_MDC__ANATOP_24M_OUT 0x0084 0x03CC 0x0000 0x3 0x0 +-#define MX6SX_PAD_ENET1_MDC__EPIT2_OUT 0x0084 0x03CC 0x0000 0x4 0x0 +-#define MX6SX_PAD_ENET1_MDC__GPIO2_IO_2 0x0084 0x03CC 0x0000 0x5 0x0 +-#define MX6SX_PAD_ENET1_MDC__USB_OTG1_PWR 0x0084 0x03CC 0x0000 0x6 0x0 +-#define MX6SX_PAD_ENET1_MDC__PWM7_OUT 0x0084 0x03CC 0x0000 0x7 0x0 +-#define MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x0088 0x03D0 0x0764 0x0 0x1 +-#define MX6SX_PAD_ENET1_MDIO__ENET2_MDIO 0x0088 0x03D0 0x0770 0x1 0x2 +-#define MX6SX_PAD_ENET1_MDIO__AUDMUX_MCLK 0x0088 0x03D0 0x0000 0x2 0x0 +-#define MX6SX_PAD_ENET1_MDIO__OSC32K_32K_OUT 0x0088 0x03D0 0x0000 0x3 0x0 +-#define MX6SX_PAD_ENET1_MDIO__EPIT1_OUT 0x0088 0x03D0 0x0000 0x4 0x0 +-#define MX6SX_PAD_ENET1_MDIO__GPIO2_IO_3 0x0088 0x03D0 0x0000 0x5 0x0 +-#define MX6SX_PAD_ENET1_MDIO__USB_OTG1_OC 0x0088 0x03D0 0x0860 0x6 0x1 +-#define MX6SX_PAD_ENET1_MDIO__PWM8_OUT 0x0088 0x03D0 0x0000 0x7 0x0 +-#define MX6SX_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x008C 0x03D4 0x0768 0x0 0x0 +-#define MX6SX_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M 0x008C 0x03D4 0x0000 0x1 0x0 +-#define MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x008C 0x03D4 0x0658 0x2 0x1 +-#define MX6SX_PAD_ENET1_RX_CLK__UART1_DSR_B 0x008C 0x03D4 0x0000 0x3 0x0 +-#define MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x008C 0x03D4 0x0000 0x4 0x0 +-#define MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0x008C 0x03D4 0x0000 0x5 0x0 +-#define MX6SX_PAD_ENET1_RX_CLK__CSI2_DATA_21 0x008C 0x03D4 0x0000 0x6 0x0 +-#define MX6SX_PAD_ENET1_RX_CLK__LCDIF2_DATA_18 0x008C 0x03D4 0x0000 0x7 0x0 +-#define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0 +-#define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0 +-#define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0 +-/* +- * SION bit is necessary for ENET1_REF_CLK1 (ENET2_REF_CLK2 untested) if it is +- * used as clock output of IMX6SX_CLK_ENET_REF (ENET1_TX_CLK) to e.g. supply a +- * PHY in RMII mode. This configuration is valid if: +- * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK is set +- * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK unset +- * It seems to be a silicon bug that in this configuration ENET1_TX reference +- * clock isn't provided automatically. According to i.MX6SX reference manual +- * (IOMUXC_GPR_GPR1 field descriptions: ENET1_CLK_SEL, Rev. 0 from 2/2015) it +- * should be the case. +- * So this might have unwanted side effects for other hardware units that are +- * also connected to that pin and using respective function as input (e.g. +- * UART1's DTR handling on MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B). +- */ +-#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1 +-#define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1 +-#define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0 +-#define MX6SX_PAD_ENET1_TX_CLK__SPDIF_SR_CLK 0x0090 0x03D8 0x0000 0x4 0x0 +-#define MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0x0090 0x03D8 0x0000 0x5 0x0 +-#define MX6SX_PAD_ENET1_TX_CLK__CSI2_DATA_20 0x0090 0x03D8 0x0000 0x6 0x0 +-#define MX6SX_PAD_ENET1_TX_CLK__LCDIF2_DATA_19 0x0090 0x03D8 0x0000 0x7 0x0 +-#define MX6SX_PAD_ENET1_TX_CLK__VDEC_DEBUG_34 0x0090 0x03D8 0x0000 0x8 0x0 +-#define MX6SX_PAD_ENET1_TX_CLK__PCIE_CTRL_DEBUG_28 0x0090 0x03D8 0x0000 0x9 0x0 +-#define MX6SX_PAD_ENET2_COL__ENET2_COL 0x0094 0x03DC 0x0000 0x0 0x0 +-#define MX6SX_PAD_ENET2_COL__ENET1_MDC 0x0094 0x03DC 0x0000 0x1 0x0 +-#define MX6SX_PAD_ENET2_COL__AUDMUX_AUD4_RXC 0x0094 0x03DC 0x064C 0x2 0x1 +-#define MX6SX_PAD_ENET2_COL__UART1_DCE_RX 0x0094 0x03DC 0x0830 0x3 0x2 +-#define MX6SX_PAD_ENET2_COL__UART1_DTE_TX 0x0094 0x03DC 0x0000 0x3 0x0 +-#define MX6SX_PAD_ENET2_COL__SPDIF_IN 0x0094 0x03DC 0x0824 0x4 0x3 +-#define MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x0094 0x03DC 0x0000 0x5 0x0 +-#define MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x0094 0x03DC 0x0624 0x6 0x1 +-#define MX6SX_PAD_ENET2_COL__LCDIF2_DATA_20 0x0094 0x03DC 0x0000 0x7 0x0 +-#define MX6SX_PAD_ENET2_COL__VDEC_DEBUG_33 0x0094 0x03DC 0x0000 0x8 0x0 +-#define MX6SX_PAD_ENET2_COL__PCIE_CTRL_DEBUG_27 0x0094 0x03DC 0x0000 0x9 0x0 +-#define MX6SX_PAD_ENET2_CRS__ENET2_CRS 0x0098 0x03E0 0x0000 0x0 0x0 +-#define MX6SX_PAD_ENET2_CRS__ENET1_MDIO 0x0098 0x03E0 0x0764 0x1 0x2 +-#define MX6SX_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS 0x0098 0x03E0 0x0650 0x2 0x1 +-#define MX6SX_PAD_ENET2_CRS__UART1_DCE_TX 0x0098 0x03E0 0x0000 0x3 0x0 +-#define MX6SX_PAD_ENET2_CRS__UART1_DTE_RX 0x0098 0x03E0 0x0830 0x3 0x3 +-#define MX6SX_PAD_ENET2_CRS__MLB_SIG 0x0098 0x03E0 0x07F0 0x4 0x1 +-#define MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x0098 0x03E0 0x0000 0x5 0x0 +-#define MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x0098 0x03E0 0x0628 0x6 0x1 +-#define MX6SX_PAD_ENET2_CRS__LCDIF2_DATA_21 0x0098 0x03E0 0x0000 0x7 0x0 +-#define MX6SX_PAD_ENET2_CRS__VDEC_DEBUG_32 0x0098 0x03E0 0x0000 0x8 0x0 +-#define MX6SX_PAD_ENET2_CRS__PCIE_CTRL_DEBUG_26 0x0098 0x03E0 0x0000 0x9 0x0 +-#define MX6SX_PAD_ENET2_RX_CLK__ENET2_RX_CLK 0x009C 0x03E4 0x0774 0x0 0x0 +-#define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0 +-#define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1 +-#define MX6SX_PAD_ENET2_RX_CLK__UART1_DCE_RTS 0x009C 0x03E4 0x082C 0x3 0x2 +-#define MX6SX_PAD_ENET2_RX_CLK__UART1_DTE_CTS 0x009C 0x03E4 0x0000 0x3 0x0 +-#define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1 +-#define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0 +-#define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1 +-#define MX6SX_PAD_ENET2_RX_CLK__LCDIF2_DATA_22 0x009C 0x03E4 0x0000 0x7 0x0 +-#define MX6SX_PAD_ENET2_RX_CLK__VDEC_DEBUG_31 0x009C 0x03E4 0x0000 0x8 0x0 +-#define MX6SX_PAD_ENET2_RX_CLK__PCIE_CTRL_DEBUG_25 0x009C 0x03E4 0x0000 0x9 0x0 +-#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0 +-#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1 +-#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1 +-#define MX6SX_PAD_ENET2_TX_CLK__UART1_DCE_CTS 0x00A0 0x03E8 0x0000 0x3 0x0 +-#define MX6SX_PAD_ENET2_TX_CLK__UART1_DTE_RTS 0x00A0 0x03E8 0x082C 0x3 0x3 +-#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1 +-#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0 +-#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0 +-#define MX6SX_PAD_ENET2_TX_CLK__LCDIF2_DATA_23 0x00A0 0x03E8 0x0000 0x7 0x0 +-#define MX6SX_PAD_ENET2_TX_CLK__VDEC_DEBUG_30 0x00A0 0x03E8 0x0000 0x8 0x0 +-#define MX6SX_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24 0x00A0 0x03E8 0x0000 0x9 0x0 +-#define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0 +-#define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0 +-#define MX6SX_PAD_KEY_COL0__UART6_DCE_RTS 0x00A4 0x03EC 0x0854 0x2 0x2 +-#define MX6SX_PAD_KEY_COL0__UART6_DTE_CTS 0x00A4 0x03EC 0x0000 0x2 0x0 +-#define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0 +-#define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0 +-#define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0 +-#define MX6SX_PAD_KEY_COL0__SDMA_EXT_EVENT_1 0x00A4 0x03EC 0x0820 0x6 0x1 +-#define MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x00A4 0x03EC 0x0814 0x7 0x0 +-#define MX6SX_PAD_KEY_COL0__VADC_DATA_0 0x00A4 0x03EC 0x0000 0x8 0x0 +-#define MX6SX_PAD_KEY_COL1__KPP_COL_1 0x00A8 0x03F0 0x0000 0x0 0x0 +-#define MX6SX_PAD_KEY_COL1__USDHC3_RESET_B 0x00A8 0x03F0 0x0000 0x1 0x0 +-#define MX6SX_PAD_KEY_COL1__UART6_DCE_TX 0x00A8 0x03F0 0x0000 0x2 0x0 +-#define MX6SX_PAD_KEY_COL1__UART6_DTE_RX 0x00A8 0x03F0 0x0858 0x2 0x2 +-#define MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x00A8 0x03F0 0x0714 0x3 0x0 +-#define MX6SX_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x00A8 0x03F0 0x0670 0x4 0x0 +-#define MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x00A8 0x03F0 0x0000 0x5 0x0 +-#define MX6SX_PAD_KEY_COL1__USDHC3_RESET 0x00A8 0x03F0 0x0000 0x6 0x0 +-#define MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x00A8 0x03F0 0x0818 0x7 0x0 +-#define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0 +-#define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1 +-#define MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x00AC 0x03F4 0x084C 0x2 0x2 +-#define MX6SX_PAD_KEY_COL2__UART5_DTE_CTS 0x00AC 0x03F4 0x0000 0x2 0x0 +-#define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0 +-#define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0 +-#define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0 +-#define MX6SX_PAD_KEY_COL2__WEIM_DATA_30 0x00AC 0x03F4 0x0000 0x6 0x0 +-#define MX6SX_PAD_KEY_COL2__ECSPI1_RDY 0x00AC 0x03F4 0x0000 0x7 0x0 +-#define MX6SX_PAD_KEY_COL3__KPP_COL_3 0x00B0 0x03F8 0x0000 0x0 0x0 +-#define MX6SX_PAD_KEY_COL3__USDHC4_LCTL 0x00B0 0x03F8 0x0000 0x1 0x0 +-#define MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x00B0 0x03F8 0x0000 0x2 0x0 +-#define MX6SX_PAD_KEY_COL3__UART5_DTE_RX 0x00B0 0x03F8 0x0850 0x2 0x2 +-#define MX6SX_PAD_KEY_COL3__CAN2_TX 0x00B0 0x03F8 0x0000 0x3 0x0 +-#define MX6SX_PAD_KEY_COL3__CANFD_TX2 0x00B0 0x03F8 0x0000 0x4 0x0 +-#define MX6SX_PAD_KEY_COL3__GPIO2_IO_13 0x00B0 0x03F8 0x0000 0x5 0x0 +-#define MX6SX_PAD_KEY_COL3__WEIM_DATA_28 0x00B0 0x03F8 0x0000 0x6 0x0 +-#define MX6SX_PAD_KEY_COL3__ECSPI1_SS2 0x00B0 0x03F8 0x0000 0x7 0x0 +-#define MX6SX_PAD_KEY_COL4__KPP_COL_4 0x00B4 0x03FC 0x0000 0x0 0x0 +-#define MX6SX_PAD_KEY_COL4__ENET2_MDC 0x00B4 0x03FC 0x0000 0x1 0x0 +-#define MX6SX_PAD_KEY_COL4__I2C3_SCL 0x00B4 0x03FC 0x07B8 0x2 0x2 +-#define MX6SX_PAD_KEY_COL4__USDHC2_LCTL 0x00B4 0x03FC 0x0000 0x3 0x0 +-#define MX6SX_PAD_KEY_COL4__AUDMUX_AUD5_RXC 0x00B4 0x03FC 0x0664 0x4 0x0 +-#define MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x00B4 0x03FC 0x0000 0x5 0x0 +-#define MX6SX_PAD_KEY_COL4__WEIM_CRE 0x00B4 0x03FC 0x0000 0x6 0x0 +-#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0 +-#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0 +-#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0 +-#define MX6SX_PAD_KEY_ROW0__UART6_DCE_CTS 0x00B8 0x0400 0x0000 0x2 0x0 +-#define MX6SX_PAD_KEY_ROW0__UART6_DTE_RTS 0x00B8 0x0400 0x0854 0x2 0x3 +-#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0 +-#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0 +-#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0 +-#define MX6SX_PAD_KEY_ROW0__SDMA_EXT_EVENT_0 0x00B8 0x0400 0x081C 0x6 0x1 +-#define MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x00B8 0x0400 0x0000 0x7 0x0 +-#define MX6SX_PAD_KEY_ROW0__GPU_IDLE 0x00B8 0x0400 0x0000 0x8 0x0 +-#define MX6SX_PAD_KEY_ROW1__KPP_ROW_1 0x00BC 0x0404 0x0000 0x0 0x0 +-#define MX6SX_PAD_KEY_ROW1__USDHC4_VSELECT 0x00BC 0x0404 0x0000 0x1 0x0 +-#define MX6SX_PAD_KEY_ROW1__UART6_DCE_RX 0x00BC 0x0404 0x0858 0x2 0x3 +-#define MX6SX_PAD_KEY_ROW1__UART6_DTE_TX 0x00BC 0x0404 0x0000 0x2 0x0 +-#define MX6SX_PAD_KEY_ROW1__ECSPI1_SS0 0x00BC 0x0404 0x071C 0x3 0x0 +-#define MX6SX_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x00BC 0x0404 0x065C 0x4 0x0 +-#define MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x00BC 0x0404 0x0000 0x5 0x0 +-#define MX6SX_PAD_KEY_ROW1__WEIM_DATA_31 0x00BC 0x0404 0x0000 0x6 0x0 +-#define MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x00BC 0x0404 0x080C 0x7 0x0 +-#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0 +-#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0 +-#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1 +-#define MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x00C0 0x0408 0x0000 0x2 0x0 +-#define MX6SX_PAD_KEY_ROW2__UART5_DTE_RTS 0x00C0 0x0408 0x084C 0x2 0x3 +-#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1 +-#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1 +-#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0 +-#define MX6SX_PAD_KEY_ROW2__WEIM_DATA_29 0x00C0 0x0408 0x0000 0x6 0x0 +-#define MX6SX_PAD_KEY_ROW2__ECSPI1_SS3 0x00C0 0x0408 0x0000 0x7 0x0 +-#define MX6SX_PAD_KEY_ROW3__KPP_ROW_3 0x00C4 0x040C 0x0000 0x0 0x0 +-#define MX6SX_PAD_KEY_ROW3__USDHC3_LCTL 0x00C4 0x040C 0x0000 0x1 0x0 +-#define MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x00C4 0x040C 0x0850 0x2 0x3 +-#define MX6SX_PAD_KEY_ROW3__UART5_DTE_TX 0x00C4 0x040C 0x0000 0x2 0x0 +-#define MX6SX_PAD_KEY_ROW3__CAN2_RX 0x00C4 0x040C 0x0690 0x3 0x1 +-#define MX6SX_PAD_KEY_ROW3__CANFD_RX2 0x00C4 0x040C 0x0698 0x4 0x1 +-#define MX6SX_PAD_KEY_ROW3__GPIO2_IO_18 0x00C4 0x040C 0x0000 0x5 0x0 +-#define MX6SX_PAD_KEY_ROW3__WEIM_DTACK_B 0x00C4 0x040C 0x0000 0x6 0x0 +-#define MX6SX_PAD_KEY_ROW3__ECSPI1_SS1 0x00C4 0x040C 0x0000 0x7 0x0 +-#define MX6SX_PAD_KEY_ROW4__KPP_ROW_4 0x00C8 0x0410 0x0000 0x0 0x0 +-#define MX6SX_PAD_KEY_ROW4__ENET2_MDIO 0x00C8 0x0410 0x0770 0x1 0x3 +-#define MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x00C8 0x0410 0x07BC 0x2 0x2 +-#define MX6SX_PAD_KEY_ROW4__USDHC1_LCTL 0x00C8 0x0410 0x0000 0x3 0x0 +-#define MX6SX_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS 0x00C8 0x0410 0x0668 0x4 0x0 +-#define MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x00C8 0x0410 0x0000 0x5 0x0 +-#define MX6SX_PAD_KEY_ROW4__WEIM_ACLK_FREERUN 0x00C8 0x0410 0x0000 0x6 0x0 +-#define MX6SX_PAD_KEY_ROW4__SAI2_RX_SYNC 0x00C8 0x0410 0x0810 0x7 0x0 +-#define MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x00CC 0x0414 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_CLK__LCDIF1_WR_RWN 0x00CC 0x0414 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_CLK__AUDMUX_AUD3_RXC 0x00CC 0x0414 0x0634 0x2 0x1 +-#define MX6SX_PAD_LCD1_CLK__ENET1_1588_EVENT2_IN 0x00CC 0x0414 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_CLK__CSI1_DATA_16 0x00CC 0x0414 0x06DC 0x4 0x0 +-#define MX6SX_PAD_LCD1_CLK__GPIO3_IO_0 0x00CC 0x0414 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_CLK__USDHC1_WP 0x00CC 0x0414 0x0868 0x6 0x0 +-#define MX6SX_PAD_LCD1_CLK__SIM_M_HADDR_16 0x00CC 0x0414 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_CLK__VADC_TEST_0 0x00CC 0x0414 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_CLK__MMDC_DEBUG_0 0x00CC 0x0414 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x00D0 0x0418 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA00__WEIM_CS1_B 0x00D0 0x0418 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA00__M4_TRACE_0 0x00D0 0x0418 0x0000 0x2 0x0 +-#define MX6SX_PAD_LCD1_DATA00__KITTEN_TRACE_0 0x00D0 0x0418 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA00__CSI1_DATA_20 0x00D0 0x0418 0x06EC 0x4 0x0 +-#define MX6SX_PAD_LCD1_DATA00__GPIO3_IO_1 0x00D0 0x0418 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA00__SRC_BT_CFG_0 0x00D0 0x0418 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA00__SIM_M_HADDR_21 0x00D0 0x0418 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA00__VADC_TEST_5 0x00D0 0x0418 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA00__MMDC_DEBUG_5 0x00D0 0x0418 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x00D4 0x041C 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA01__WEIM_CS2_B 0x00D4 0x041C 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA01__M4_TRACE_1 0x00D4 0x041C 0x0000 0x2 0x0 +-#define MX6SX_PAD_LCD1_DATA01__KITTEN_TRACE_1 0x00D4 0x041C 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA01__CSI1_DATA_21 0x00D4 0x041C 0x06F0 0x4 0x0 +-#define MX6SX_PAD_LCD1_DATA01__GPIO3_IO_2 0x00D4 0x041C 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA01__SRC_BT_CFG_1 0x00D4 0x041C 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA01__SIM_M_HADDR_22 0x00D4 0x041C 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA01__VADC_TEST_6 0x00D4 0x041C 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA01__MMDC_DEBUG_6 0x00D4 0x041C 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x00D8 0x0420 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA02__WEIM_CS3_B 0x00D8 0x0420 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA02__M4_TRACE_2 0x00D8 0x0420 0x0000 0x2 0x0 +-#define MX6SX_PAD_LCD1_DATA02__KITTEN_TRACE_2 0x00D8 0x0420 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA02__CSI1_DATA_22 0x00D8 0x0420 0x06F4 0x4 0x0 +-#define MX6SX_PAD_LCD1_DATA02__GPIO3_IO_3 0x00D8 0x0420 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA02__SRC_BT_CFG_2 0x00D8 0x0420 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA02__SIM_M_HADDR_23 0x00D8 0x0420 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA02__VADC_TEST_7 0x00D8 0x0420 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA02__MMDC_DEBUG_7 0x00D8 0x0420 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x00DC 0x0424 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0x00DC 0x0424 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA03__M4_TRACE_3 0x00DC 0x0424 0x0000 0x2 0x0 +-#define MX6SX_PAD_LCD1_DATA03__KITTEN_TRACE_3 0x00DC 0x0424 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA03__CSI1_DATA_23 0x00DC 0x0424 0x06F8 0x4 0x0 +-#define MX6SX_PAD_LCD1_DATA03__GPIO3_IO_4 0x00DC 0x0424 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA03__SRC_BT_CFG_3 0x00DC 0x0424 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA03__SIM_M_HADDR_24 0x00DC 0x0424 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA03__VADC_TEST_8 0x00DC 0x0424 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA03__MMDC_DEBUG_8 0x00DC 0x0424 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x00E0 0x0428 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0x00E0 0x0428 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA04__KITTEN_TRACE_4 0x00E0 0x0428 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x00E0 0x0428 0x0708 0x4 0x1 +-#define MX6SX_PAD_LCD1_DATA04__GPIO3_IO_5 0x00E0 0x0428 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA04__SRC_BT_CFG_4 0x00E0 0x0428 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA04__SIM_M_HADDR_25 0x00E0 0x0428 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA04__VADC_TEST_9 0x00E0 0x0428 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA04__MMDC_DEBUG_9 0x00E0 0x0428 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x00E4 0x042C 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0x00E4 0x042C 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA05__KITTEN_TRACE_5 0x00E4 0x042C 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x00E4 0x042C 0x0700 0x4 0x1 +-#define MX6SX_PAD_LCD1_DATA05__GPIO3_IO_6 0x00E4 0x042C 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA05__SRC_BT_CFG_5 0x00E4 0x042C 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA05__SIM_M_HADDR_26 0x00E4 0x042C 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA05__VADC_TEST_10 0x00E4 0x042C 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA05__MMDC_DEBUG_10 0x00E4 0x042C 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x00E8 0x0430 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA06__WEIM_EB_B_2 0x00E8 0x0430 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA06__KITTEN_TRACE_6 0x00E8 0x0430 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x00E8 0x0430 0x0704 0x4 0x1 +-#define MX6SX_PAD_LCD1_DATA06__GPIO3_IO_7 0x00E8 0x0430 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA06__SRC_BT_CFG_6 0x00E8 0x0430 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA06__SIM_M_HADDR_27 0x00E8 0x0430 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA06__VADC_TEST_11 0x00E8 0x0430 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA06__MMDC_DEBUG_11 0x00E8 0x0430 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x00EC 0x0434 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA07__WEIM_EB_B_3 0x00EC 0x0434 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA07__KITTEN_TRACE_7 0x00EC 0x0434 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x00EC 0x0434 0x0000 0x4 0x0 +-#define MX6SX_PAD_LCD1_DATA07__GPIO3_IO_8 0x00EC 0x0434 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA07__SRC_BT_CFG_7 0x00EC 0x0434 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA07__SIM_M_HADDR_28 0x00EC 0x0434 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA07__VADC_TEST_12 0x00EC 0x0434 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA07__MMDC_DEBUG_12 0x00EC 0x0434 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x00F0 0x0438 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0x00F0 0x0438 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA08__KITTEN_TRACE_8 0x00F0 0x0438 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x00F0 0x0438 0x06C4 0x4 0x1 +-#define MX6SX_PAD_LCD1_DATA08__GPIO3_IO_9 0x00F0 0x0438 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA08__SRC_BT_CFG_8 0x00F0 0x0438 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA08__SIM_M_HADDR_29 0x00F0 0x0438 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA08__VADC_TEST_13 0x00F0 0x0438 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA08__MMDC_DEBUG_13 0x00F0 0x0438 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x00F4 0x043C 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0x00F4 0x043C 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA09__KITTEN_TRACE_9 0x00F4 0x043C 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x00F4 0x043C 0x06C0 0x4 0x1 +-#define MX6SX_PAD_LCD1_DATA09__GPIO3_IO_10 0x00F4 0x043C 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA09__SRC_BT_CFG_9 0x00F4 0x043C 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA09__SIM_M_HADDR_30 0x00F4 0x043C 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA09__VADC_TEST_14 0x00F4 0x043C 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA09__MMDC_DEBUG_14 0x00F4 0x043C 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x00F8 0x0440 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0x00F8 0x0440 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA10__KITTEN_TRACE_10 0x00F8 0x0440 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x00F8 0x0440 0x06BC 0x4 0x1 +-#define MX6SX_PAD_LCD1_DATA10__GPIO3_IO_11 0x00F8 0x0440 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA10__SRC_BT_CFG_10 0x00F8 0x0440 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA10__SIM_M_HADDR_31 0x00F8 0x0440 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA10__VADC_TEST_15 0x00F8 0x0440 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA10__MMDC_DEBUG_15 0x00F8 0x0440 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x00FC 0x0444 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0x00FC 0x0444 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA11__KITTEN_TRACE_11 0x00FC 0x0444 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x00FC 0x0444 0x06B8 0x4 0x1 +-#define MX6SX_PAD_LCD1_DATA11__GPIO3_IO_12 0x00FC 0x0444 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA11__SRC_BT_CFG_11 0x00FC 0x0444 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA11__SIM_M_HBURST_0 0x00FC 0x0444 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA11__VADC_TEST_16 0x00FC 0x0444 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA11__MMDC_DEBUG_16 0x00FC 0x0444 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x0100 0x0448 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0x0100 0x0448 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA12__KITTEN_TRACE_12 0x0100 0x0448 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x0100 0x0448 0x06B4 0x4 0x1 +-#define MX6SX_PAD_LCD1_DATA12__GPIO3_IO_13 0x0100 0x0448 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA12__SRC_BT_CFG_12 0x0100 0x0448 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA12__SIM_M_HBURST_1 0x0100 0x0448 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA12__VADC_TEST_17 0x0100 0x0448 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA12__MMDC_DEBUG_17 0x0100 0x0448 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x0104 0x044C 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0x0104 0x044C 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA13__KITTEN_TRACE_13 0x0104 0x044C 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x0104 0x044C 0x06B0 0x4 0x1 +-#define MX6SX_PAD_LCD1_DATA13__GPIO3_IO_14 0x0104 0x044C 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA13__SRC_BT_CFG_13 0x0104 0x044C 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA13__SIM_M_HBURST_2 0x0104 0x044C 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA13__VADC_TEST_18 0x0104 0x044C 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA13__MMDC_DEBUG_18 0x0104 0x044C 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x0108 0x0450 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0x0108 0x0450 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA14__KITTEN_TRACE_14 0x0108 0x0450 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x0108 0x0450 0x06AC 0x4 0x1 +-#define MX6SX_PAD_LCD1_DATA14__GPIO3_IO_15 0x0108 0x0450 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA14__SRC_BT_CFG_14 0x0108 0x0450 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA14__SIM_M_HMASTLOCK 0x0108 0x0450 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA14__VADC_TEST_19 0x0108 0x0450 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA14__MMDC_DEBUG_19 0x0108 0x0450 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x010C 0x0454 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0x010C 0x0454 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA15__KITTEN_TRACE_15 0x010C 0x0454 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x010C 0x0454 0x06A8 0x4 0x1 +-#define MX6SX_PAD_LCD1_DATA15__GPIO3_IO_16 0x010C 0x0454 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA15__SRC_BT_CFG_15 0x010C 0x0454 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA15__SIM_M_HPROT_0 0x010C 0x0454 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA15__VDEC_DEBUG_0 0x010C 0x0454 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA15__MMDC_DEBUG_20 0x010C 0x0454 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x0110 0x0458 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0x0110 0x0458 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA16__M4_TRACE_CLK 0x0110 0x0458 0x0000 0x2 0x0 +-#define MX6SX_PAD_LCD1_DATA16__KITTEN_TRACE_CLK 0x0110 0x0458 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x0110 0x0458 0x06A4 0x4 0x0 +-#define MX6SX_PAD_LCD1_DATA16__GPIO3_IO_17 0x0110 0x0458 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA16__SRC_BT_CFG_24 0x0110 0x0458 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA16__SIM_M_HPROT_1 0x0110 0x0458 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA16__VDEC_DEBUG_1 0x0110 0x0458 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA16__MMDC_DEBUG_21 0x0110 0x0458 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x0114 0x045C 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0x0114 0x045C 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA17__KITTEN_TRACE_CTL 0x0114 0x045C 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x0114 0x045C 0x06A0 0x4 0x0 +-#define MX6SX_PAD_LCD1_DATA17__GPIO3_IO_18 0x0114 0x045C 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA17__SRC_BT_CFG_25 0x0114 0x045C 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA17__SIM_M_HPROT_2 0x0114 0x045C 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA17__VDEC_DEBUG_2 0x0114 0x045C 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA17__MMDC_DEBUG_22 0x0114 0x045C 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x0118 0x0460 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0x0118 0x0460 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA18__M4_EVENTO 0x0118 0x0460 0x0000 0x2 0x0 +-#define MX6SX_PAD_LCD1_DATA18__KITTEN_EVENTO 0x0118 0x0460 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA18__CSI1_DATA_15 0x0118 0x0460 0x06D8 0x4 0x0 +-#define MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19 0x0118 0x0460 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA18__SRC_BT_CFG_26 0x0118 0x0460 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA18__SIM_M_HPROT_3 0x0118 0x0460 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA18__VDEC_DEBUG_3 0x0118 0x0460 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA18__MMDC_DEBUG_23 0x0118 0x0460 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x011C 0x0464 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0x011C 0x0464 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA19__M4_TRACE_SWO 0x011C 0x0464 0x0000 0x2 0x0 +-#define MX6SX_PAD_LCD1_DATA19__CSI1_DATA_14 0x011C 0x0464 0x06D4 0x4 0x0 +-#define MX6SX_PAD_LCD1_DATA19__GPIO3_IO_20 0x011C 0x0464 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA19__SRC_BT_CFG_27 0x011C 0x0464 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA19__SIM_M_HREADYOUT 0x011C 0x0464 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA19__VDEC_DEBUG_4 0x011C 0x0464 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA19__MMDC_DEBUG_24 0x011C 0x0464 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x0120 0x0468 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0x0120 0x0468 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA20__PWM8_OUT 0x0120 0x0468 0x0000 0x2 0x0 +-#define MX6SX_PAD_LCD1_DATA20__ENET1_1588_EVENT2_OUT 0x0120 0x0468 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA20__CSI1_DATA_13 0x0120 0x0468 0x06D0 0x4 0x0 +-#define MX6SX_PAD_LCD1_DATA20__GPIO3_IO_21 0x0120 0x0468 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA20__SRC_BT_CFG_28 0x0120 0x0468 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA20__SIM_M_HRESP 0x0120 0x0468 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA20__VDEC_DEBUG_5 0x0120 0x0468 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA20__MMDC_DEBUG_25 0x0120 0x0468 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x0124 0x046C 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0x0124 0x046C 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA21__PWM7_OUT 0x0124 0x046C 0x0000 0x2 0x0 +-#define MX6SX_PAD_LCD1_DATA21__ENET1_1588_EVENT3_OUT 0x0124 0x046C 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA21__CSI1_DATA_12 0x0124 0x046C 0x06CC 0x4 0x0 +-#define MX6SX_PAD_LCD1_DATA21__GPIO3_IO_22 0x0124 0x046C 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA21__SRC_BT_CFG_29 0x0124 0x046C 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA21__SIM_M_HSIZE_0 0x0124 0x046C 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA21__VDEC_DEBUG_6 0x0124 0x046C 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA21__MMDC_DEBUG_26 0x0124 0x046C 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x0128 0x0470 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0x0128 0x0470 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA22__PWM6_OUT 0x0128 0x0470 0x0000 0x2 0x0 +-#define MX6SX_PAD_LCD1_DATA22__ENET2_1588_EVENT2_OUT 0x0128 0x0470 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA22__CSI1_DATA_11 0x0128 0x0470 0x06C8 0x4 0x0 +-#define MX6SX_PAD_LCD1_DATA22__GPIO3_IO_23 0x0128 0x0470 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA22__SRC_BT_CFG_30 0x0128 0x0470 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA22__SIM_M_HSIZE_1 0x0128 0x0470 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA22__VDEC_DEBUG_7 0x0128 0x0470 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA22__MMDC_DEBUG_27 0x0128 0x0470 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x012C 0x0474 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_DATA23__WEIM_ADDR_23 0x012C 0x0474 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_DATA23__PWM5_OUT 0x012C 0x0474 0x0000 0x2 0x0 +-#define MX6SX_PAD_LCD1_DATA23__ENET2_1588_EVENT3_OUT 0x012C 0x0474 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_DATA23__CSI1_DATA_10 0x012C 0x0474 0x06FC 0x4 0x0 +-#define MX6SX_PAD_LCD1_DATA23__GPIO3_IO_24 0x012C 0x0474 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_DATA23__SRC_BT_CFG_31 0x012C 0x0474 0x0000 0x6 0x0 +-#define MX6SX_PAD_LCD1_DATA23__SIM_M_HSIZE_2 0x012C 0x0474 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_DATA23__VDEC_DEBUG_8 0x012C 0x0474 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_DATA23__MMDC_DEBUG_28 0x012C 0x0474 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x0130 0x0478 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_RD_E 0x0130 0x0478 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC 0x0130 0x0478 0x063C 0x2 0x1 +-#define MX6SX_PAD_LCD1_ENABLE__ENET1_1588_EVENT3_IN 0x0130 0x0478 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_ENABLE__CSI1_DATA_17 0x0130 0x0478 0x06E0 0x4 0x0 +-#define MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x0130 0x0478 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_ENABLE__USDHC1_CD_B 0x0130 0x0478 0x0864 0x6 0x0 +-#define MX6SX_PAD_LCD1_ENABLE__SIM_M_HADDR_17 0x0130 0x0478 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_ENABLE__VADC_TEST_1 0x0130 0x0478 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_ENABLE__MMDC_DEBUG_1 0x0130 0x0478 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x0134 0x047C 0x07E0 0x0 0x0 +-#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_RS 0x0134 0x047C 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD 0x0134 0x047C 0x0630 0x2 0x1 +-#define MX6SX_PAD_LCD1_HSYNC__ENET2_1588_EVENT2_IN 0x0134 0x047C 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_HSYNC__CSI1_DATA_18 0x0134 0x047C 0x06E4 0x4 0x0 +-#define MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x0134 0x047C 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_HSYNC__USDHC2_WP 0x0134 0x047C 0x0870 0x6 0x0 +-#define MX6SX_PAD_LCD1_HSYNC__SIM_M_HADDR_18 0x0134 0x047C 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_HSYNC__VADC_TEST_2 0x0134 0x047C 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_HSYNC__MMDC_DEBUG_2 0x0134 0x047C 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_RESET__LCDIF1_RESET 0x0138 0x0480 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_RESET__LCDIF1_CS 0x0138 0x0480 0x0000 0x1 0x0 +-#define MX6SX_PAD_LCD1_RESET__AUDMUX_AUD3_RXD 0x0138 0x0480 0x062C 0x2 0x1 +-#define MX6SX_PAD_LCD1_RESET__KITTEN_EVENTI 0x0138 0x0480 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_RESET__M4_EVENTI 0x0138 0x0480 0x0000 0x4 0x0 +-#define MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x0138 0x0480 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_RESET__CCM_PMIC_RDY 0x0138 0x0480 0x069C 0x6 0x0 +-#define MX6SX_PAD_LCD1_RESET__SIM_M_HADDR_20 0x0138 0x0480 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_RESET__VADC_TEST_4 0x0138 0x0480 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_RESET__MMDC_DEBUG_4 0x0138 0x0480 0x0000 0x9 0x0 +-#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x013C 0x0484 0x0000 0x0 0x0 +-#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_BUSY 0x013C 0x0484 0x07E0 0x1 0x1 +-#define MX6SX_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS 0x013C 0x0484 0x0640 0x2 0x1 +-#define MX6SX_PAD_LCD1_VSYNC__ENET2_1588_EVENT3_IN 0x013C 0x0484 0x0000 0x3 0x0 +-#define MX6SX_PAD_LCD1_VSYNC__CSI1_DATA_19 0x013C 0x0484 0x06E8 0x4 0x0 +-#define MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x013C 0x0484 0x0000 0x5 0x0 +-#define MX6SX_PAD_LCD1_VSYNC__USDHC2_CD_B 0x013C 0x0484 0x086C 0x6 0x0 +-#define MX6SX_PAD_LCD1_VSYNC__SIM_M_HADDR_19 0x013C 0x0484 0x0000 0x7 0x0 +-#define MX6SX_PAD_LCD1_VSYNC__VADC_TEST_3 0x013C 0x0484 0x0000 0x8 0x0 +-#define MX6SX_PAD_LCD1_VSYNC__MMDC_DEBUG_3 0x013C 0x0484 0x0000 0x9 0x0 +-#define MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0x0140 0x0488 0x0000 0x0 0x0 +-#define MX6SX_PAD_NAND_ALE__I2C3_SDA 0x0140 0x0488 0x07BC 0x1 0x0 +-#define MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x0140 0x0488 0x0000 0x2 0x0 +-#define MX6SX_PAD_NAND_ALE__ECSPI2_SS0 0x0140 0x0488 0x072C 0x3 0x0 +-#define MX6SX_PAD_NAND_ALE__ESAI_TX3_RX2 0x0140 0x0488 0x079C 0x4 0x0 +-#define MX6SX_PAD_NAND_ALE__GPIO4_IO_0 0x0140 0x0488 0x0000 0x5 0x0 +-#define MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0x0140 0x0488 0x0000 0x6 0x0 +-#define MX6SX_PAD_NAND_ALE__TPSMP_HDATA_0 0x0140 0x0488 0x0000 0x7 0x0 +-#define MX6SX_PAD_NAND_ALE__ANATOP_USBPHY1_TSTI_TX_EN 0x0140 0x0488 0x0000 0x8 0x0 +-#define MX6SX_PAD_NAND_ALE__SDMA_DEBUG_PC_12 0x0140 0x0488 0x0000 0x9 0x0 +-#define MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0144 0x048C 0x0000 0x0 0x0 +-#define MX6SX_PAD_NAND_CE0_B__USDHC2_VSELECT 0x0144 0x048C 0x0000 0x1 0x0 +-#define MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x0144 0x048C 0x0000 0x2 0x0 +-#define MX6SX_PAD_NAND_CE0_B__AUDMUX_AUD4_TXC 0x0144 0x048C 0x0654 0x3 0x0 +-#define MX6SX_PAD_NAND_CE0_B__ESAI_TX_CLK 0x0144 0x048C 0x078C 0x4 0x0 +-#define MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x0144 0x048C 0x0000 0x5 0x0 +-#define MX6SX_PAD_NAND_CE0_B__WEIM_LBA_B 0x0144 0x048C 0x0000 0x6 0x0 +-#define MX6SX_PAD_NAND_CE0_B__TPSMP_HDATA_3 0x0144 0x048C 0x0000 0x7 0x0 +-#define MX6SX_PAD_NAND_CE0_B__ANATOP_USBPHY1_TSTI_TX_HIZ 0x0144 0x048C 0x0000 0x8 0x0 +-#define MX6SX_PAD_NAND_CE0_B__SDMA_DEBUG_PC_9 0x0144 0x048C 0x0000 0x9 0x0 +-#define MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0148 0x0490 0x0000 0x0 0x0 +-#define MX6SX_PAD_NAND_CE1_B__USDHC3_RESET_B 0x0148 0x0490 0x0000 0x1 0x0 +-#define MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x0148 0x0490 0x0000 0x2 0x0 +-#define MX6SX_PAD_NAND_CE1_B__AUDMUX_AUD4_TXD 0x0148 0x0490 0x0648 0x3 0x0 +-#define MX6SX_PAD_NAND_CE1_B__ESAI_TX0 0x0148 0x0490 0x0790 0x4 0x0 +-#define MX6SX_PAD_NAND_CE1_B__GPIO4_IO_2 0x0148 0x0490 0x0000 0x5 0x0 +-#define MX6SX_PAD_NAND_CE1_B__WEIM_OE 0x0148 0x0490 0x0000 0x6 0x0 +-#define MX6SX_PAD_NAND_CE1_B__TPSMP_HDATA_4 0x0148 0x0490 0x0000 0x7 0x0 +-#define MX6SX_PAD_NAND_CE1_B__ANATOP_USBPHY1_TSTI_TX_LS_MODE 0x0148 0x0490 0x0000 0x8 0x0 +-#define MX6SX_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8 0x0148 0x0490 0x0000 0x9 0x0 +-#define MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0x014C 0x0494 0x0000 0x0 0x0 +-#define MX6SX_PAD_NAND_CLE__I2C3_SCL 0x014C 0x0494 0x07B8 0x1 0x0 +-#define MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x014C 0x0494 0x0000 0x2 0x0 +-#define MX6SX_PAD_NAND_CLE__ECSPI2_SCLK 0x014C 0x0494 0x0720 0x3 0x0 +-#define MX6SX_PAD_NAND_CLE__ESAI_TX2_RX3 0x014C 0x0494 0x0798 0x4 0x0 +-#define MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x014C 0x0494 0x0000 0x5 0x0 +-#define MX6SX_PAD_NAND_CLE__WEIM_BCLK 0x014C 0x0494 0x0000 0x6 0x0 +-#define MX6SX_PAD_NAND_CLE__TPSMP_CLK 0x014C 0x0494 0x0000 0x7 0x0 +-#define MX6SX_PAD_NAND_CLE__ANATOP_USBPHY1_TSTI_TX_DP 0x014C 0x0494 0x0000 0x8 0x0 +-#define MX6SX_PAD_NAND_CLE__SDMA_DEBUG_PC_13 0x014C 0x0494 0x0000 0x9 0x0 +-#define MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0x0150 0x0498 0x0000 0x0 0x0 +-#define MX6SX_PAD_NAND_DATA00__USDHC1_DATA4 0x0150 0x0498 0x0000 0x1 0x0 +-#define MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x0150 0x0498 0x0000 0x2 0x0 +-#define MX6SX_PAD_NAND_DATA00__ECSPI5_MISO 0x0150 0x0498 0x0754 0x3 0x0 +-#define MX6SX_PAD_NAND_DATA00__ESAI_RX_CLK 0x0150 0x0498 0x0788 0x4 0x0 +-#define MX6SX_PAD_NAND_DATA00__GPIO4_IO_4 0x0150 0x0498 0x0000 0x5 0x0 +-#define MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0x0150 0x0498 0x0000 0x6 0x0 +-#define MX6SX_PAD_NAND_DATA00__TPSMP_HDATA_7 0x0150 0x0498 0x0000 0x7 0x0 +-#define MX6SX_PAD_NAND_DATA00__ANATOP_USBPHY1_TSTO_RX_DISCON_DET 0x0150 0x0498 0x0000 0x8 0x0 +-#define MX6SX_PAD_NAND_DATA00__SDMA_DEBUG_EVT_CHN_LINES_5 0x0150 0x0498 0x0000 0x9 0x0 +-#define MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0x0154 0x049C 0x0000 0x0 0x0 +-#define MX6SX_PAD_NAND_DATA01__USDHC1_DATA5 0x0154 0x049C 0x0000 0x1 0x0 +-#define MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x0154 0x049C 0x0000 0x2 0x0 +-#define MX6SX_PAD_NAND_DATA01__ECSPI5_MOSI 0x0154 0x049C 0x0758 0x3 0x0 +-#define MX6SX_PAD_NAND_DATA01__ESAI_RX_FS 0x0154 0x049C 0x0778 0x4 0x0 +-#define MX6SX_PAD_NAND_DATA01__GPIO4_IO_5 0x0154 0x049C 0x0000 0x5 0x0 +-#define MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0x0154 0x049C 0x0000 0x6 0x0 +-#define MX6SX_PAD_NAND_DATA01__TPSMP_HDATA_8 0x0154 0x049C 0x0000 0x7 0x0 +-#define MX6SX_PAD_NAND_DATA01__ANATOP_USBPHY1_TSTO_RX_HS_RXD 0x0154 0x049C 0x0000 0x8 0x0 +-#define MX6SX_PAD_NAND_DATA01__SDMA_DEBUG_EVT_CHN_LINES_4 0x0154 0x049C 0x0000 0x9 0x0 +-#define MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0x0158 0x04A0 0x0000 0x0 0x0 +-#define MX6SX_PAD_NAND_DATA02__USDHC1_DATA6 0x0158 0x04A0 0x0000 0x1 0x0 +-#define MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x0158 0x04A0 0x0000 0x2 0x0 +-#define MX6SX_PAD_NAND_DATA02__ECSPI5_SCLK 0x0158 0x04A0 0x0750 0x3 0x0 +-#define MX6SX_PAD_NAND_DATA02__ESAI_TX_HF_CLK 0x0158 0x04A0 0x0784 0x4 0x0 +-#define MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x0158 0x04A0 0x0000 0x5 0x0 +-#define MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0x0158 0x04A0 0x0000 0x6 0x0 +-#define MX6SX_PAD_NAND_DATA02__TPSMP_HDATA_9 0x0158 0x04A0 0x0000 0x7 0x0 +-#define MX6SX_PAD_NAND_DATA02__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV 0x0158 0x04A0 0x0000 0x8 0x0 +-#define MX6SX_PAD_NAND_DATA02__SDMA_DEBUG_EVT_CHN_LINES_3 0x0158 0x04A0 0x0000 0x9 0x0 +-#define MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0x015C 0x04A4 0x0000 0x0 0x0 +-#define MX6SX_PAD_NAND_DATA03__USDHC1_DATA7 0x015C 0x04A4 0x0000 0x1 0x0 +-#define MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x015C 0x04A4 0x0000 0x2 0x0 +-#define MX6SX_PAD_NAND_DATA03__ECSPI5_SS0 0x015C 0x04A4 0x075C 0x3 0x0 +-#define MX6SX_PAD_NAND_DATA03__ESAI_RX_HF_CLK 0x015C 0x04A4 0x0780 0x4 0x0 +-#define MX6SX_PAD_NAND_DATA03__GPIO4_IO_7 0x015C 0x04A4 0x0000 0x5 0x0 +-#define MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0x015C 0x04A4 0x0000 0x6 0x0 +-#define MX6SX_PAD_NAND_DATA03__TPSMP_HDATA_10 0x015C 0x04A4 0x0000 0x7 0x0 +-#define MX6SX_PAD_NAND_DATA03__ANATOP_USBPHY1_TSTO_RX_SQUELCH 0x015C 0x04A4 0x0000 0x8 0x0 +-#define MX6SX_PAD_NAND_DATA03__SDMA_DEBUG_EVT_CHN_LINES_6 0x015C 0x04A4 0x0000 0x9 0x0 +-#define MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0x0160 0x04A8 0x0000 0x0 0x0 +-#define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0 +-#define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0 +-#define MX6SX_PAD_NAND_DATA04__UART3_DCE_RTS 0x0160 0x04A8 0x083C 0x3 0x0 +-#define MX6SX_PAD_NAND_DATA04__UART3_DTE_CTS 0x0160 0x04A8 0x0000 0x3 0x0 +-#define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0 +-#define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0 +-#define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0 +-#define MX6SX_PAD_NAND_DATA04__TPSMP_HDATA_11 0x0160 0x04A8 0x0000 0x7 0x0 +-#define MX6SX_PAD_NAND_DATA04__ANATOP_USBPHY2_TSTO_RX_SQUELCH 0x0160 0x04A8 0x0000 0x8 0x0 +-#define MX6SX_PAD_NAND_DATA04__SDMA_DEBUG_CORE_STATE_0 0x0160 0x04A8 0x0000 0x9 0x0 +-#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0 +-#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0 +-#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0 +-#define MX6SX_PAD_NAND_DATA05__UART3_DCE_CTS 0x0164 0x04AC 0x0000 0x3 0x0 +-#define MX6SX_PAD_NAND_DATA05__UART3_DTE_RTS 0x0164 0x04AC 0x083C 0x3 0x1 +-#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0 +-#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0 +-#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0 +-#define MX6SX_PAD_NAND_DATA05__TPSMP_HDATA_12 0x0164 0x04AC 0x0000 0x7 0x0 +-#define MX6SX_PAD_NAND_DATA05__ANATOP_USBPHY2_TSTO_RX_DISCON_DET 0x0164 0x04AC 0x0000 0x8 0x0 +-#define MX6SX_PAD_NAND_DATA05__SDMA_DEBUG_CORE_STATE_1 0x0164 0x04AC 0x0000 0x9 0x0 +-#define MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0x0168 0x04B0 0x0000 0x0 0x0 +-#define MX6SX_PAD_NAND_DATA06__USDHC2_DATA6 0x0168 0x04B0 0x0000 0x1 0x0 +-#define MX6SX_PAD_NAND_DATA06__QSPI2_A_SS1_B 0x0168 0x04B0 0x0000 0x2 0x0 +-#define MX6SX_PAD_NAND_DATA06__UART3_DCE_RX 0x0168 0x04B0 0x0840 0x3 0x0 +-#define MX6SX_PAD_NAND_DATA06__UART3_DTE_TX 0x0168 0x04B0 0x0000 0x3 0x0 +-#define MX6SX_PAD_NAND_DATA06__PWM3_OUT 0x0168 0x04B0 0x0000 0x4 0x0 +-#define MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x0168 0x04B0 0x0000 0x5 0x0 +-#define MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0x0168 0x04B0 0x0000 0x6 0x0 +-#define MX6SX_PAD_NAND_DATA06__TPSMP_HDATA_13 0x0168 0x04B0 0x0000 0x7 0x0 +-#define MX6SX_PAD_NAND_DATA06__ANATOP_USBPHY2_TSTO_RX_FS_RXD 0x0168 0x04B0 0x0000 0x8 0x0 +-#define MX6SX_PAD_NAND_DATA06__SDMA_DEBUG_CORE_STATE_2 0x0168 0x04B0 0x0000 0x9 0x0 +-#define MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0x016C 0x04B4 0x0000 0x0 0x0 +-#define MX6SX_PAD_NAND_DATA07__USDHC2_DATA7 0x016C 0x04B4 0x0000 0x1 0x0 +-#define MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS 0x016C 0x04B4 0x0000 0x2 0x0 +-#define MX6SX_PAD_NAND_DATA07__UART3_DCE_TX 0x016C 0x04B4 0x0000 0x3 0x0 +-#define MX6SX_PAD_NAND_DATA07__UART3_DTE_RX 0x016C 0x04B4 0x0840 0x3 0x1 +-#define MX6SX_PAD_NAND_DATA07__PWM4_OUT 0x016C 0x04B4 0x0000 0x4 0x0 +-#define MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0x016C 0x04B4 0x0000 0x5 0x0 +-#define MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0x016C 0x04B4 0x0000 0x6 0x0 +-#define MX6SX_PAD_NAND_DATA07__TPSMP_HDATA_14 0x016C 0x04B4 0x0000 0x7 0x0 +-#define MX6SX_PAD_NAND_DATA07__ANATOP_USBPHY1_TSTO_RX_FS_RXD 0x016C 0x04B4 0x0000 0x8 0x0 +-#define MX6SX_PAD_NAND_DATA07__SDMA_DEBUG_CORE_STATE_3 0x016C 0x04B4 0x0000 0x9 0x0 +-#define MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0x0170 0x04B8 0x0000 0x0 0x0 +-#define MX6SX_PAD_NAND_RE_B__USDHC2_RESET_B 0x0170 0x04B8 0x0000 0x1 0x0 +-#define MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x0170 0x04B8 0x0000 0x2 0x0 +-#define MX6SX_PAD_NAND_RE_B__AUDMUX_AUD4_TXFS 0x0170 0x04B8 0x0658 0x3 0x0 +-#define MX6SX_PAD_NAND_RE_B__ESAI_TX_FS 0x0170 0x04B8 0x077C 0x4 0x0 +-#define MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x0170 0x04B8 0x0000 0x5 0x0 +-#define MX6SX_PAD_NAND_RE_B__WEIM_RW 0x0170 0x04B8 0x0000 0x6 0x0 +-#define MX6SX_PAD_NAND_RE_B__TPSMP_HDATA_5 0x0170 0x04B8 0x0000 0x7 0x0 +-#define MX6SX_PAD_NAND_RE_B__ANATOP_USBPHY2_TSTO_RX_HS_RXD 0x0170 0x04B8 0x0000 0x8 0x0 +-#define MX6SX_PAD_NAND_RE_B__SDMA_DEBUG_PC_7 0x0170 0x04B8 0x0000 0x9 0x0 +-#define MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0x0174 0x04BC 0x0000 0x0 0x0 +-#define MX6SX_PAD_NAND_READY_B__USDHC1_VSELECT 0x0174 0x04BC 0x0000 0x1 0x0 +-#define MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x0174 0x04BC 0x0000 0x2 0x0 +-#define MX6SX_PAD_NAND_READY_B__ECSPI2_MISO 0x0174 0x04BC 0x0724 0x3 0x0 +-#define MX6SX_PAD_NAND_READY_B__ESAI_TX1 0x0174 0x04BC 0x0794 0x4 0x0 +-#define MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x0174 0x04BC 0x0000 0x5 0x0 +-#define MX6SX_PAD_NAND_READY_B__WEIM_EB_B_1 0x0174 0x04BC 0x0000 0x6 0x0 +-#define MX6SX_PAD_NAND_READY_B__TPSMP_HDATA_2 0x0174 0x04BC 0x0000 0x7 0x0 +-#define MX6SX_PAD_NAND_READY_B__ANATOP_USBPHY1_TSTI_TX_DN 0x0174 0x04BC 0x0000 0x8 0x0 +-#define MX6SX_PAD_NAND_READY_B__SDMA_DEBUG_PC_10 0x0174 0x04BC 0x0000 0x9 0x0 +-#define MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0x0178 0x04C0 0x0000 0x0 0x0 +-#define MX6SX_PAD_NAND_WE_B__USDHC4_VSELECT 0x0178 0x04C0 0x0000 0x1 0x0 +-#define MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x0178 0x04C0 0x0000 0x2 0x0 +-#define MX6SX_PAD_NAND_WE_B__AUDMUX_AUD4_RXD 0x0178 0x04C0 0x0644 0x3 0x0 +-#define MX6SX_PAD_NAND_WE_B__ESAI_TX5_RX0 0x0178 0x04C0 0x07A4 0x4 0x0 +-#define MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x0178 0x04C0 0x0000 0x5 0x0 +-#define MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0x0178 0x04C0 0x0000 0x6 0x0 +-#define MX6SX_PAD_NAND_WE_B__TPSMP_HDATA_6 0x0178 0x04C0 0x0000 0x7 0x0 +-#define MX6SX_PAD_NAND_WE_B__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV 0x0178 0x04C0 0x0000 0x8 0x0 +-#define MX6SX_PAD_NAND_WE_B__SDMA_DEBUG_PC_6 0x0178 0x04C0 0x0000 0x9 0x0 +-#define MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0x017C 0x04C4 0x0000 0x0 0x0 +-#define MX6SX_PAD_NAND_WP_B__USDHC1_RESET_B 0x017C 0x04C4 0x0000 0x1 0x0 +-#define MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x017C 0x04C4 0x0000 0x2 0x0 +-#define MX6SX_PAD_NAND_WP_B__ECSPI2_MOSI 0x017C 0x04C4 0x0728 0x3 0x0 +-#define MX6SX_PAD_NAND_WP_B__ESAI_TX4_RX1 0x017C 0x04C4 0x07A0 0x4 0x0 +-#define MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x017C 0x04C4 0x0000 0x5 0x0 +-#define MX6SX_PAD_NAND_WP_B__WEIM_EB_B_0 0x017C 0x04C4 0x0000 0x6 0x0 +-#define MX6SX_PAD_NAND_WP_B__TPSMP_HDATA_1 0x017C 0x04C4 0x0000 0x7 0x0 +-#define MX6SX_PAD_NAND_WP_B__ANATOP_USBPHY1_TSTI_TX_HS_MODE 0x017C 0x04C4 0x0000 0x8 0x0 +-#define MX6SX_PAD_NAND_WP_B__SDMA_DEBUG_PC_11 0x017C 0x04C4 0x0000 0x9 0x0 +-#define MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x0180 0x04C8 0x0000 0x0 0x0 +-#define MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x0180 0x04C8 0x085C 0x1 0x2 +-#define MX6SX_PAD_QSPI1A_DATA0__ECSPI1_MOSI 0x0180 0x04C8 0x0718 0x2 0x1 +-#define MX6SX_PAD_QSPI1A_DATA0__ESAI_TX4_RX1 0x0180 0x04C8 0x07A0 0x3 0x2 +-#define MX6SX_PAD_QSPI1A_DATA0__CSI1_DATA_14 0x0180 0x04C8 0x06D4 0x4 0x1 +-#define MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x0180 0x04C8 0x0000 0x5 0x0 +-#define MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x0180 0x04C8 0x0000 0x6 0x0 +-#define MX6SX_PAD_QSPI1A_DATA0__SIM_M_HADDR_3 0x0180 0x04C8 0x0000 0x7 0x0 +-#define MX6SX_PAD_QSPI1A_DATA0__SDMA_DEBUG_BUS_DEVICE_3 0x0180 0x04C8 0x0000 0x9 0x0 +-#define MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x0184 0x04CC 0x0000 0x0 0x0 +-#define MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x0184 0x04CC 0x0624 0x1 0x2 +-#define MX6SX_PAD_QSPI1A_DATA1__ECSPI1_MISO 0x0184 0x04CC 0x0714 0x2 0x1 +-#define MX6SX_PAD_QSPI1A_DATA1__ESAI_TX1 0x0184 0x04CC 0x0794 0x3 0x2 +-#define MX6SX_PAD_QSPI1A_DATA1__CSI1_DATA_13 0x0184 0x04CC 0x06D0 0x4 0x1 +-#define MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x0184 0x04CC 0x0000 0x5 0x0 +-#define MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x0184 0x04CC 0x0000 0x6 0x0 +-#define MX6SX_PAD_QSPI1A_DATA1__SIM_M_HADDR_4 0x0184 0x04CC 0x0000 0x7 0x0 +-#define MX6SX_PAD_QSPI1A_DATA1__SDMA_DEBUG_PC_0 0x0184 0x04CC 0x0000 0x9 0x0 +-#define MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x0188 0x04D0 0x0000 0x0 0x0 +-#define MX6SX_PAD_QSPI1A_DATA2__USB_OTG1_PWR 0x0188 0x04D0 0x0000 0x1 0x0 +-#define MX6SX_PAD_QSPI1A_DATA2__ECSPI5_SS1 0x0188 0x04D0 0x0000 0x2 0x0 +-#define MX6SX_PAD_QSPI1A_DATA2__ESAI_TX_CLK 0x0188 0x04D0 0x078C 0x3 0x2 +-#define MX6SX_PAD_QSPI1A_DATA2__CSI1_DATA_12 0x0188 0x04D0 0x06CC 0x4 0x1 +-#define MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x0188 0x04D0 0x0000 0x5 0x0 +-#define MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x0188 0x04D0 0x0000 0x6 0x0 +-#define MX6SX_PAD_QSPI1A_DATA2__SIM_M_HADDR_6 0x0188 0x04D0 0x0000 0x7 0x0 +-#define MX6SX_PAD_QSPI1A_DATA2__SDMA_DEBUG_PC_1 0x0188 0x04D0 0x0000 0x9 0x0 +-#define MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x018C 0x04D4 0x0000 0x0 0x0 +-#define MX6SX_PAD_QSPI1A_DATA3__USB_OTG1_OC 0x018C 0x04D4 0x0860 0x1 0x2 +-#define MX6SX_PAD_QSPI1A_DATA3__ECSPI5_SS2 0x018C 0x04D4 0x0000 0x2 0x0 +-#define MX6SX_PAD_QSPI1A_DATA3__ESAI_TX0 0x018C 0x04D4 0x0790 0x3 0x2 +-#define MX6SX_PAD_QSPI1A_DATA3__CSI1_DATA_11 0x018C 0x04D4 0x06C8 0x4 0x1 +-#define MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x018C 0x04D4 0x0000 0x5 0x0 +-#define MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x018C 0x04D4 0x0000 0x6 0x0 +-#define MX6SX_PAD_QSPI1A_DATA3__SIM_M_HADDR_7 0x018C 0x04D4 0x0000 0x7 0x0 +-#define MX6SX_PAD_QSPI1A_DATA3__SDMA_DEBUG_PC_2 0x018C 0x04D4 0x0000 0x9 0x0 +-#define MX6SX_PAD_QSPI1A_DQS__QSPI1_A_DQS 0x0190 0x04D8 0x0000 0x0 0x0 +-#define MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x0190 0x04D8 0x0000 0x1 0x0 +-#define MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x0190 0x04D8 0x0000 0x2 0x0 +-#define MX6SX_PAD_QSPI1A_DQS__ECSPI5_MOSI 0x0190 0x04D8 0x0758 0x3 0x1 +-#define MX6SX_PAD_QSPI1A_DQS__CSI1_DATA_15 0x0190 0x04D8 0x06D8 0x4 0x1 +-#define MX6SX_PAD_QSPI1A_DQS__GPIO4_IO_20 0x0190 0x04D8 0x0000 0x5 0x0 +-#define MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x0190 0x04D8 0x0000 0x6 0x0 +-#define MX6SX_PAD_QSPI1A_DQS__SIM_M_HADDR_13 0x0190 0x04D8 0x0000 0x7 0x0 +-#define MX6SX_PAD_QSPI1A_DQS__SDMA_DEBUG_BUS_DEVICE_4 0x0190 0x04D8 0x0000 0x9 0x0 +-#define MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x0194 0x04DC 0x0000 0x0 0x0 +-#define MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x0194 0x04DC 0x0628 0x1 0x2 +-#define MX6SX_PAD_QSPI1A_SCLK__ECSPI1_SCLK 0x0194 0x04DC 0x0710 0x2 0x1 +-#define MX6SX_PAD_QSPI1A_SCLK__ESAI_TX2_RX3 0x0194 0x04DC 0x0798 0x3 0x2 +-#define MX6SX_PAD_QSPI1A_SCLK__CSI1_DATA_1 0x0194 0x04DC 0x06A4 0x4 0x1 +-#define MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21 0x0194 0x04DC 0x0000 0x5 0x0 +-#define MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x0194 0x04DC 0x0000 0x6 0x0 +-#define MX6SX_PAD_QSPI1A_SCLK__SIM_M_HADDR_0 0x0194 0x04DC 0x0000 0x7 0x0 +-#define MX6SX_PAD_QSPI1A_SCLK__SDMA_DEBUG_PC_5 0x0194 0x04DC 0x0000 0x9 0x0 +-#define MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x0198 0x04E0 0x0000 0x0 0x0 +-#define MX6SX_PAD_QSPI1A_SS0_B__USB_OTG2_PWR 0x0198 0x04E0 0x0000 0x1 0x0 +-#define MX6SX_PAD_QSPI1A_SS0_B__ECSPI1_SS0 0x0198 0x04E0 0x071C 0x2 0x1 +-#define MX6SX_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2 0x0198 0x04E0 0x079C 0x3 0x2 +-#define MX6SX_PAD_QSPI1A_SS0_B__CSI1_DATA_0 0x0198 0x04E0 0x06A0 0x4 0x1 +-#define MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x0198 0x04E0 0x0000 0x5 0x0 +-#define MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x0198 0x04E0 0x0000 0x6 0x0 +-#define MX6SX_PAD_QSPI1A_SS0_B__SIM_M_HADDR_1 0x0198 0x04E0 0x0000 0x7 0x0 +-#define MX6SX_PAD_QSPI1A_SS0_B__SDMA_DEBUG_PC_4 0x0198 0x04E0 0x0000 0x9 0x0 +-#define MX6SX_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B 0x019C 0x04E4 0x0000 0x0 0x0 +-#define MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x019C 0x04E4 0x068C 0x1 0x2 +-#define MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x019C 0x04E4 0x0694 0x2 0x2 +-#define MX6SX_PAD_QSPI1A_SS1_B__ECSPI5_MISO 0x019C 0x04E4 0x0754 0x3 0x1 +-#define MX6SX_PAD_QSPI1A_SS1_B__CSI1_DATA_10 0x019C 0x04E4 0x06FC 0x4 0x1 +-#define MX6SX_PAD_QSPI1A_SS1_B__GPIO4_IO_23 0x019C 0x04E4 0x0000 0x5 0x0 +-#define MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x019C 0x04E4 0x0000 0x6 0x0 +-#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0 +-#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0 +-#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0 +-#define MX6SX_PAD_QSPI1B_DATA0__UART3_DCE_CTS 0x01A0 0x04E8 0x0000 0x1 0x0 +-#define MX6SX_PAD_QSPI1B_DATA0__UART3_DTE_RTS 0x01A0 0x04E8 0x083C 0x1 0x4 +-#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1 +-#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2 +-#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1 +-#define MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x01A0 0x04E8 0x0000 0x5 0x0 +-#define MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x01A0 0x04E8 0x0000 0x6 0x0 +-#define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0 +-#define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0 +-#define MX6SX_PAD_QSPI1B_DATA1__UART3_DCE_RTS 0x01A4 0x04EC 0x083C 0x1 0x5 +-#define MX6SX_PAD_QSPI1B_DATA1__UART3_DTE_CTS 0x01A4 0x04EC 0x0000 0x1 0x0 +-#define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1 +-#define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2 +-#define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1 +-#define MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x01A4 0x04EC 0x0000 0x5 0x0 +-#define MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x01A4 0x04EC 0x0000 0x6 0x0 +-#define MX6SX_PAD_QSPI1B_DATA1__SIM_M_HADDR_8 0x01A4 0x04EC 0x0000 0x7 0x0 +-#define MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x01A8 0x04F0 0x0000 0x0 0x0 +-#define MX6SX_PAD_QSPI1B_DATA2__I2C2_SDA 0x01A8 0x04F0 0x07B4 0x1 0x2 +-#define MX6SX_PAD_QSPI1B_DATA2__ECSPI5_RDY 0x01A8 0x04F0 0x0000 0x2 0x0 +-#define MX6SX_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 0x01A8 0x04F0 0x07A4 0x3 0x2 +-#define MX6SX_PAD_QSPI1B_DATA2__CSI1_DATA_20 0x01A8 0x04F0 0x06EC 0x4 0x1 +-#define MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0x01A8 0x04F0 0x0000 0x5 0x0 +-#define MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x01A8 0x04F0 0x0000 0x6 0x0 +-#define MX6SX_PAD_QSPI1B_DATA2__SIM_M_HADDR_5 0x01A8 0x04F0 0x0000 0x7 0x0 +-#define MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x01AC 0x04F4 0x0000 0x0 0x0 +-#define MX6SX_PAD_QSPI1B_DATA3__I2C2_SCL 0x01AC 0x04F4 0x07B0 0x1 0x2 +-#define MX6SX_PAD_QSPI1B_DATA3__ECSPI5_SS3 0x01AC 0x04F4 0x0000 0x2 0x0 +-#define MX6SX_PAD_QSPI1B_DATA3__ESAI_TX_FS 0x01AC 0x04F4 0x077C 0x3 0x2 +-#define MX6SX_PAD_QSPI1B_DATA3__CSI1_DATA_19 0x01AC 0x04F4 0x06E8 0x4 0x1 +-#define MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x01AC 0x04F4 0x0000 0x5 0x0 +-#define MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x01AC 0x04F4 0x0000 0x6 0x0 +-#define MX6SX_PAD_QSPI1B_DATA3__SIM_M_HADDR_2 0x01AC 0x04F4 0x0000 0x7 0x0 +-#define MX6SX_PAD_QSPI1B_DQS__QSPI1_B_DQS 0x01B0 0x04F8 0x0000 0x0 0x0 +-#define MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x01B0 0x04F8 0x0000 0x1 0x0 +-#define MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x01B0 0x04F8 0x0000 0x2 0x0 +-#define MX6SX_PAD_QSPI1B_DQS__ECSPI5_SS0 0x01B0 0x04F8 0x075C 0x3 0x1 +-#define MX6SX_PAD_QSPI1B_DQS__CSI1_DATA_23 0x01B0 0x04F8 0x06F8 0x4 0x1 +-#define MX6SX_PAD_QSPI1B_DQS__GPIO4_IO_28 0x01B0 0x04F8 0x0000 0x5 0x0 +-#define MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x01B0 0x04F8 0x0000 0x6 0x0 +-#define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0 +-#define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0 +-#define MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x01B4 0x04FC 0x0840 0x1 0x4 +-#define MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX 0x01B4 0x04FC 0x0000 0x1 0x0 +-#define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1 +-#define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2 +-#define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1 +-#define MX6SX_PAD_QSPI1B_SCLK__GPIO4_IO_29 0x01B4 0x04FC 0x0000 0x5 0x0 +-#define MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x01B4 0x04FC 0x0000 0x6 0x0 +-#define MX6SX_PAD_QSPI1B_SCLK__SIM_M_HADDR_11 0x01B4 0x04FC 0x0000 0x7 0x0 +-#define MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x01B8 0x0500 0x0000 0x0 0x0 +-#define MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX 0x01B8 0x0500 0x0000 0x1 0x0 +-#define MX6SX_PAD_QSPI1B_SS0_B__UART3_DTE_RX 0x01B8 0x0500 0x0840 0x1 0x5 +-#define MX6SX_PAD_QSPI1B_SS0_B__ECSPI3_SS0 0x01B8 0x0500 0x073C 0x2 0x1 +-#define MX6SX_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK 0x01B8 0x0500 0x0784 0x3 0x3 +-#define MX6SX_PAD_QSPI1B_SS0_B__CSI1_DATA_17 0x01B8 0x0500 0x06E0 0x4 0x1 +-#define MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x01B8 0x0500 0x0000 0x5 0x0 +-#define MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x01B8 0x0500 0x0000 0x6 0x0 +-#define MX6SX_PAD_QSPI1B_SS0_B__SIM_M_HADDR_10 0x01B8 0x0500 0x0000 0x7 0x0 +-#define MX6SX_PAD_QSPI1B_SS1_B__QSPI1_B_SS1_B 0x01BC 0x0504 0x0000 0x0 0x0 +-#define MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x01BC 0x0504 0x0690 0x1 0x2 +-#define MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x01BC 0x0504 0x0698 0x2 0x2 +-#define MX6SX_PAD_QSPI1B_SS1_B__ECSPI5_SCLK 0x01BC 0x0504 0x0750 0x3 0x1 +-#define MX6SX_PAD_QSPI1B_SS1_B__CSI1_DATA_18 0x01BC 0x0504 0x06E4 0x4 0x1 +-#define MX6SX_PAD_QSPI1B_SS1_B__GPIO4_IO_31 0x01BC 0x0504 0x0000 0x5 0x0 +-#define MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x01BC 0x0504 0x0000 0x6 0x0 +-#define MX6SX_PAD_QSPI1B_SS1_B__SIM_M_HADDR_14 0x01BC 0x0504 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x01C0 0x0508 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII1_RD0__GPIO5_IO_0 0x01C0 0x0508 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII1_RD0__CSI2_DATA_10 0x01C0 0x0508 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII1_RD0__ANATOP_TESTI_0 0x01C0 0x0508 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII1_RD0__RAWNAND_TESTER_TRIGGER 0x01C0 0x0508 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII1_RD0__PCIE_CTRL_DEBUG_0 0x01C0 0x0508 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x01C4 0x050C 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII1_RD1__GPIO5_IO_1 0x01C4 0x050C 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII1_RD1__CSI2_DATA_11 0x01C4 0x050C 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII1_RD1__ANATOP_TESTI_1 0x01C4 0x050C 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII1_RD1__USDHC1_TESTER_TRIGGER 0x01C4 0x050C 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII1_RD1__PCIE_CTRL_DEBUG_1 0x01C4 0x050C 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x01C8 0x0510 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII1_RD2__GPIO5_IO_2 0x01C8 0x0510 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII1_RD2__CSI2_DATA_12 0x01C8 0x0510 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII1_RD2__ANATOP_TESTI_2 0x01C8 0x0510 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII1_RD2__USDHC2_TESTER_TRIGGER 0x01C8 0x0510 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII1_RD2__PCIE_CTRL_DEBUG_2 0x01C8 0x0510 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x01CC 0x0514 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII1_RD3__GPIO5_IO_3 0x01CC 0x0514 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII1_RD3__CSI2_DATA_13 0x01CC 0x0514 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII1_RD3__ANATOP_TESTI_3 0x01CC 0x0514 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII1_RD3__USDHC3_TESTER_TRIGGER 0x01CC 0x0514 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII1_RD3__PCIE_CTRL_DEBUG_3 0x01CC 0x0514 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x01D0 0x0518 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII1_RX_CTL__GPIO5_IO_4 0x01D0 0x0518 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII1_RX_CTL__CSI2_DATA_14 0x01D0 0x0518 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII1_RX_CTL__ANATOP_TESTO_0 0x01D0 0x0518 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII1_RX_CTL__USDHC4_TESTER_TRIGGER 0x01D0 0x0518 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII1_RX_CTL__PCIE_CTRL_DEBUG_4 0x01D0 0x0518 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x01D4 0x051C 0x0768 0x0 0x1 +-#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER 0x01D4 0x051C 0x0000 0x1 0x0 +-#define MX6SX_PAD_RGMII1_RXC__GPIO5_IO_5 0x01D4 0x051C 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII1_RXC__CSI2_DATA_15 0x01D4 0x051C 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII1_RXC__ANATOP_TESTO_1 0x01D4 0x051C 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII1_RXC__ECSPI1_TESTER_TRIGGER 0x01D4 0x051C 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII1_RXC__PCIE_CTRL_DEBUG_5 0x01D4 0x051C 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x01D8 0x0520 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII1_TD0__SAI2_RX_SYNC 0x01D8 0x0520 0x0810 0x2 0x1 +-#define MX6SX_PAD_RGMII1_TD0__GPIO5_IO_6 0x01D8 0x0520 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII1_TD0__CSI2_DATA_16 0x01D8 0x0520 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII1_TD0__ANATOP_TESTO_2 0x01D8 0x0520 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII1_TD0__ECSPI2_TESTER_TRIGGER 0x01D8 0x0520 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII1_TD0__PCIE_CTRL_DEBUG_6 0x01D8 0x0520 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x01DC 0x0524 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII1_TD1__SAI2_RX_BCLK 0x01DC 0x0524 0x0808 0x2 0x1 +-#define MX6SX_PAD_RGMII1_TD1__GPIO5_IO_7 0x01DC 0x0524 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII1_TD1__CSI2_DATA_17 0x01DC 0x0524 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII1_TD1__ANATOP_TESTO_3 0x01DC 0x0524 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII1_TD1__ECSPI3_TESTER_TRIGGER 0x01DC 0x0524 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII1_TD1__PCIE_CTRL_DEBUG_7 0x01DC 0x0524 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x01E0 0x0528 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII1_TD2__SAI2_TX_SYNC 0x01E0 0x0528 0x0818 0x2 0x1 +-#define MX6SX_PAD_RGMII1_TD2__GPIO5_IO_8 0x01E0 0x0528 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII1_TD2__CSI2_DATA_18 0x01E0 0x0528 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII1_TD2__ANATOP_TESTO_4 0x01E0 0x0528 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII1_TD2__ECSPI4_TESTER_TRIGGER 0x01E0 0x0528 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII1_TD2__PCIE_CTRL_DEBUG_8 0x01E0 0x0528 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x01E4 0x052C 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII1_TD3__SAI2_TX_BCLK 0x01E4 0x052C 0x0814 0x2 0x1 +-#define MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x01E4 0x052C 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII1_TD3__CSI2_DATA_19 0x01E4 0x052C 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII1_TD3__ANATOP_TESTO_5 0x01E4 0x052C 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII1_TD3__ECSPI5_TESTER_TRIGGER 0x01E4 0x052C 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII1_TD3__PCIE_CTRL_DEBUG_9 0x01E4 0x052C 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x01E8 0x0530 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0 0x01E8 0x0530 0x080C 0x2 0x1 +-#define MX6SX_PAD_RGMII1_TX_CTL__GPIO5_IO_10 0x01E8 0x0530 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII1_TX_CTL__CSI2_DATA_0 0x01E8 0x0530 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII1_TX_CTL__ANATOP_TESTO_6 0x01E8 0x0530 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII1_TX_CTL__QSPI1_TESTER_TRIGGER 0x01E8 0x0530 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII1_TX_CTL__PCIE_CTRL_DEBUG_10 0x01E8 0x0530 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x01EC 0x0534 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII1_TXC__ENET1_TX_ER 0x01EC 0x0534 0x0000 0x1 0x0 +-#define MX6SX_PAD_RGMII1_TXC__SAI2_TX_DATA_0 0x01EC 0x0534 0x0000 0x2 0x0 +-#define MX6SX_PAD_RGMII1_TXC__GPIO5_IO_11 0x01EC 0x0534 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII1_TXC__CSI2_DATA_1 0x01EC 0x0534 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII1_TXC__ANATOP_TESTO_7 0x01EC 0x0534 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII1_TXC__QSPI2_TESTER_TRIGGER 0x01EC 0x0534 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII1_TXC__PCIE_CTRL_DEBUG_11 0x01EC 0x0534 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x01F0 0x0538 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII2_RD0__PWM4_OUT 0x01F0 0x0538 0x0000 0x2 0x0 +-#define MX6SX_PAD_RGMII2_RD0__GPIO5_IO_12 0x01F0 0x0538 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII2_RD0__CSI2_DATA_2 0x01F0 0x0538 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII2_RD0__ANATOP_TESTO_8 0x01F0 0x0538 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII2_RD0__VDEC_DEBUG_18 0x01F0 0x0538 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII2_RD0__PCIE_CTRL_DEBUG_12 0x01F0 0x0538 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x01F4 0x053C 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII2_RD1__PWM3_OUT 0x01F4 0x053C 0x0000 0x2 0x0 +-#define MX6SX_PAD_RGMII2_RD1__GPIO5_IO_13 0x01F4 0x053C 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII2_RD1__CSI2_DATA_3 0x01F4 0x053C 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII2_RD1__ANATOP_TESTO_9 0x01F4 0x053C 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII2_RD1__VDEC_DEBUG_19 0x01F4 0x053C 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII2_RD1__PCIE_CTRL_DEBUG_13 0x01F4 0x053C 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x01F8 0x0540 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x01F8 0x0540 0x0000 0x2 0x0 +-#define MX6SX_PAD_RGMII2_RD2__GPIO5_IO_14 0x01F8 0x0540 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII2_RD2__CSI2_DATA_4 0x01F8 0x0540 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII2_RD2__ANATOP_TESTO_10 0x01F8 0x0540 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII2_RD2__VDEC_DEBUG_20 0x01F8 0x0540 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII2_RD2__PCIE_CTRL_DEBUG_14 0x01F8 0x0540 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x01FC 0x0544 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x01FC 0x0544 0x0000 0x2 0x0 +-#define MX6SX_PAD_RGMII2_RD3__GPIO5_IO_15 0x01FC 0x0544 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII2_RD3__CSI2_DATA_5 0x01FC 0x0544 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII2_RD3__ANATOP_TESTO_11 0x01FC 0x0544 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII2_RD3__VDEC_DEBUG_21 0x01FC 0x0544 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII2_RD3__PCIE_CTRL_DEBUG_15 0x01FC 0x0544 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x0200 0x0548 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII2_RX_CTL__GPIO5_IO_16 0x0200 0x0548 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII2_RX_CTL__CSI2_DATA_6 0x0200 0x0548 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII2_RX_CTL__ANATOP_TESTO_12 0x0200 0x0548 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII2_RX_CTL__VDEC_DEBUG_22 0x0200 0x0548 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII2_RX_CTL__PCIE_CTRL_DEBUG_16 0x0200 0x0548 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x0204 0x054C 0x0774 0x0 0x1 +-#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_ER 0x0204 0x054C 0x0000 0x1 0x0 +-#define MX6SX_PAD_RGMII2_RXC__GPIO5_IO_17 0x0204 0x054C 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII2_RXC__CSI2_DATA_7 0x0204 0x054C 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII2_RXC__ANATOP_TESTO_13 0x0204 0x054C 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII2_RXC__VDEC_DEBUG_23 0x0204 0x054C 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII2_RXC__PCIE_CTRL_DEBUG_17 0x0204 0x054C 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x0208 0x0550 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII2_TD0__SAI1_RX_SYNC 0x0208 0x0550 0x07FC 0x2 0x1 +-#define MX6SX_PAD_RGMII2_TD0__PWM8_OUT 0x0208 0x0550 0x0000 0x3 0x0 +-#define MX6SX_PAD_RGMII2_TD0__GPIO5_IO_18 0x0208 0x0550 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII2_TD0__CSI2_DATA_8 0x0208 0x0550 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII2_TD0__ANATOP_TESTO_14 0x0208 0x0550 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII2_TD0__VDEC_DEBUG_24 0x0208 0x0550 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII2_TD0__PCIE_CTRL_DEBUG_18 0x0208 0x0550 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x020C 0x0554 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII2_TD1__SAI1_RX_BCLK 0x020C 0x0554 0x07F4 0x2 0x1 +-#define MX6SX_PAD_RGMII2_TD1__PWM7_OUT 0x020C 0x0554 0x0000 0x3 0x0 +-#define MX6SX_PAD_RGMII2_TD1__GPIO5_IO_19 0x020C 0x0554 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII2_TD1__CSI2_DATA_9 0x020C 0x0554 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII2_TD1__ANATOP_TESTO_15 0x020C 0x0554 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII2_TD1__VDEC_DEBUG_25 0x020C 0x0554 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII2_TD1__PCIE_CTRL_DEBUG_19 0x020C 0x0554 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x0210 0x0558 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII2_TD2__SAI1_TX_SYNC 0x0210 0x0558 0x0804 0x2 0x1 +-#define MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x0210 0x0558 0x0000 0x3 0x0 +-#define MX6SX_PAD_RGMII2_TD2__GPIO5_IO_20 0x0210 0x0558 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII2_TD2__CSI2_VSYNC 0x0210 0x0558 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII2_TD2__SJC_FAIL 0x0210 0x0558 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII2_TD2__VDEC_DEBUG_26 0x0210 0x0558 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII2_TD2__PCIE_CTRL_DEBUG_20 0x0210 0x0558 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x0214 0x055C 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII2_TD3__SAI1_TX_BCLK 0x0214 0x055C 0x0800 0x2 0x1 +-#define MX6SX_PAD_RGMII2_TD3__PWM5_OUT 0x0214 0x055C 0x0000 0x3 0x0 +-#define MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x0214 0x055C 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII2_TD3__CSI2_HSYNC 0x0214 0x055C 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII2_TD3__SJC_JTAG_ACT 0x0214 0x055C 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII2_TD3__VDEC_DEBUG_27 0x0214 0x055C 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII2_TD3__PCIE_CTRL_DEBUG_21 0x0214 0x055C 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x0218 0x0560 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0 0x0218 0x0560 0x07F8 0x2 0x1 +-#define MX6SX_PAD_RGMII2_TX_CTL__GPIO5_IO_22 0x0218 0x0560 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII2_TX_CTL__CSI2_FIELD 0x0218 0x0560 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII2_TX_CTL__SJC_DE_B 0x0218 0x0560 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII2_TX_CTL__VDEC_DEBUG_28 0x0218 0x0560 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII2_TX_CTL__PCIE_CTRL_DEBUG_22 0x0218 0x0560 0x0000 0x9 0x0 +-#define MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x021C 0x0564 0x0000 0x0 0x0 +-#define MX6SX_PAD_RGMII2_TXC__ENET2_TX_ER 0x021C 0x0564 0x0000 0x1 0x0 +-#define MX6SX_PAD_RGMII2_TXC__SAI1_TX_DATA_0 0x021C 0x0564 0x0000 0x2 0x0 +-#define MX6SX_PAD_RGMII2_TXC__GPIO5_IO_23 0x021C 0x0564 0x0000 0x5 0x0 +-#define MX6SX_PAD_RGMII2_TXC__CSI2_PIXCLK 0x021C 0x0564 0x0000 0x6 0x0 +-#define MX6SX_PAD_RGMII2_TXC__SJC_DONE 0x021C 0x0564 0x0000 0x7 0x0 +-#define MX6SX_PAD_RGMII2_TXC__VDEC_DEBUG_29 0x021C 0x0564 0x0000 0x8 0x0 +-#define MX6SX_PAD_RGMII2_TXC__PCIE_CTRL_DEBUG_23 0x021C 0x0564 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x0220 0x0568 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x0220 0x0568 0x0668 0x1 0x1 +-#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_B 0x0220 0x0568 0x0000 0x2 0x0 +-#define MX6SX_PAD_SD1_CLK__GPT_CLK 0x0220 0x0568 0x0000 0x3 0x0 +-#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_RST_B_DEB 0x0220 0x0568 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD1_CLK__GPIO6_IO_0 0x0220 0x0568 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD1_CLK__ENET2_1588_EVENT1_OUT 0x0220 0x0568 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD1_CLK__CCM_OUT1 0x0220 0x0568 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD1_CLK__VADC_ADC_PROC_CLK 0x0220 0x0568 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD1_CLK__MMDC_DEBUG_45 0x0220 0x0568 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x0224 0x056C 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x0224 0x056C 0x0664 0x1 0x1 +-#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_B 0x0224 0x056C 0x0000 0x2 0x0 +-#define MX6SX_PAD_SD1_CMD__GPT_COMPARE1 0x0224 0x056C 0x0000 0x3 0x0 +-#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_RST_B_DEB 0x0224 0x056C 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD1_CMD__GPIO6_IO_1 0x0224 0x056C 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD1_CMD__ENET2_1588_EVENT1_IN 0x0224 0x056C 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x0224 0x056C 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD1_CMD__VADC_EXT_SYSCLK 0x0224 0x056C 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD1_CMD__MMDC_DEBUG_46 0x0224 0x056C 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x0228 0x0570 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x0228 0x0570 0x065C 0x1 0x1 +-#define MX6SX_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS 0x0228 0x0570 0x0000 0x2 0x0 +-#define MX6SX_PAD_SD1_DATA0__GPT_CAPTURE1 0x0228 0x0570 0x0000 0x3 0x0 +-#define MX6SX_PAD_SD1_DATA0__UART2_DCE_RX 0x0228 0x0570 0x0838 0x4 0x2 +-#define MX6SX_PAD_SD1_DATA0__UART2_DTE_TX 0x0228 0x0570 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x0228 0x0570 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN 0x0228 0x0570 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD1_DATA0__CCM_OUT2 0x0228 0x0570 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD1_DATA0__VADC_CLAMP_UP 0x0228 0x0570 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD1_DATA0__MMDC_DEBUG_48 0x0228 0x0570 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x022C 0x0574 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x022C 0x0574 0x066C 0x1 0x1 +-#define MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x022C 0x0574 0x0000 0x2 0x0 +-#define MX6SX_PAD_SD1_DATA1__GPT_CAPTURE2 0x022C 0x0574 0x0000 0x3 0x0 +-#define MX6SX_PAD_SD1_DATA1__UART2_DCE_TX 0x022C 0x0574 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD1_DATA1__UART2_DTE_RX 0x022C 0x0574 0x0838 0x4 0x3 +-#define MX6SX_PAD_SD1_DATA1__GPIO6_IO_3 0x022C 0x0574 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT 0x022C 0x0574 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD1_DATA1__CCM_CLKO2 0x022C 0x0574 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD1_DATA1__VADC_CLAMP_DOWN 0x022C 0x0574 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD1_DATA1__MMDC_DEBUG_47 0x022C 0x0574 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x0230 0x0578 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1 +-#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0 +-#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0 +-#define MX6SX_PAD_SD1_DATA2__UART2_DCE_CTS 0x0230 0x0578 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD1_DATA2__UART2_DTE_RTS 0x0230 0x0578 0x0834 0x4 0x2 +-#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD1_DATA2__VADC_EXT_PD_N 0x0230 0x0578 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x0234 0x057C 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x0234 0x057C 0x0660 0x1 0x1 +-#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2 +-#define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0 +-#define MX6SX_PAD_SD1_DATA3__UART2_DCE_RTS 0x0234 0x057C 0x0834 0x4 0x3 +-#define MX6SX_PAD_SD1_DATA3__UART2_DTE_CTS 0x0234 0x057C 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2 +-#define MX6SX_PAD_SD1_DATA3__VADC_RST_N 0x0234 0x057C 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x0238 0x0580 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD2_CLK__AUDMUX_AUD6_RXFS 0x0238 0x0580 0x0680 0x1 0x2 +-#define MX6SX_PAD_SD2_CLK__KPP_COL_5 0x0238 0x0580 0x07C8 0x2 0x1 +-#define MX6SX_PAD_SD2_CLK__ECSPI4_SCLK 0x0238 0x0580 0x0740 0x3 0x1 +-#define MX6SX_PAD_SD2_CLK__MLB_SIG 0x0238 0x0580 0x07F0 0x4 0x2 +-#define MX6SX_PAD_SD2_CLK__GPIO6_IO_6 0x0238 0x0580 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x0238 0x0580 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD2_CLK__WDOG1_WDOG_ANY 0x0238 0x0580 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD2_CLK__VADC_CLAMP_CURRENT_5 0x0238 0x0580 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD2_CLK__MMDC_DEBUG_29 0x0238 0x0580 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x023C 0x0584 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD2_CMD__AUDMUX_AUD6_RXC 0x023C 0x0584 0x067C 0x1 0x2 +-#define MX6SX_PAD_SD2_CMD__KPP_ROW_5 0x023C 0x0584 0x07D4 0x2 0x1 +-#define MX6SX_PAD_SD2_CMD__ECSPI4_MOSI 0x023C 0x0584 0x0748 0x3 0x1 +-#define MX6SX_PAD_SD2_CMD__MLB_CLK 0x023C 0x0584 0x07E8 0x4 0x2 +-#define MX6SX_PAD_SD2_CMD__GPIO6_IO_7 0x023C 0x0584 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD2_CMD__MQS_LEFT 0x023C 0x0584 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD2_CMD__WDOG3_WDOG_B 0x023C 0x0584 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD2_CMD__VADC_CLAMP_CURRENT_4 0x023C 0x0584 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD2_CMD__MMDC_DEBUG_30 0x023C 0x0584 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x0240 0x0588 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD2_DATA0__AUDMUX_AUD6_RXD 0x0240 0x0588 0x0674 0x1 0x2 +-#define MX6SX_PAD_SD2_DATA0__KPP_ROW_7 0x0240 0x0588 0x07DC 0x2 0x1 +-#define MX6SX_PAD_SD2_DATA0__PWM1_OUT 0x0240 0x0588 0x0000 0x3 0x0 +-#define MX6SX_PAD_SD2_DATA0__I2C4_SDA 0x0240 0x0588 0x07C4 0x4 0x3 +-#define MX6SX_PAD_SD2_DATA0__GPIO6_IO_8 0x0240 0x0588 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD2_DATA0__ECSPI4_SS3 0x0240 0x0588 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD2_DATA0__UART4_DCE_RX 0x0240 0x0588 0x0848 0x7 0x4 +-#define MX6SX_PAD_SD2_DATA0__UART4_DTE_TX 0x0240 0x0588 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0 0x0240 0x0588 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD2_DATA0__MMDC_DEBUG_50 0x0240 0x0588 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x0244 0x058C 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD2_DATA1__AUDMUX_AUD6_TXC 0x0244 0x058C 0x0684 0x1 0x2 +-#define MX6SX_PAD_SD2_DATA1__KPP_COL_7 0x0244 0x058C 0x07D0 0x2 0x1 +-#define MX6SX_PAD_SD2_DATA1__PWM2_OUT 0x0244 0x058C 0x0000 0x3 0x0 +-#define MX6SX_PAD_SD2_DATA1__I2C4_SCL 0x0244 0x058C 0x07C0 0x4 0x3 +-#define MX6SX_PAD_SD2_DATA1__GPIO6_IO_9 0x0244 0x058C 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD2_DATA1__ECSPI4_SS2 0x0244 0x058C 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD2_DATA1__UART4_DCE_TX 0x0244 0x058C 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD2_DATA1__UART4_DTE_RX 0x0244 0x058C 0x0848 0x7 0x5 +-#define MX6SX_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1 0x0244 0x058C 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD2_DATA1__MMDC_DEBUG_49 0x0244 0x058C 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x0248 0x0590 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS 0x0248 0x0590 0x0688 0x1 0x2 +-#define MX6SX_PAD_SD2_DATA2__KPP_ROW_6 0x0248 0x0590 0x07D8 0x2 0x1 +-#define MX6SX_PAD_SD2_DATA2__ECSPI4_SS0 0x0248 0x0590 0x074C 0x3 0x1 +-#define MX6SX_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 0x0248 0x0590 0x081C 0x4 0x2 +-#define MX6SX_PAD_SD2_DATA2__GPIO6_IO_10 0x0248 0x0590 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD2_DATA2__SPDIF_OUT 0x0248 0x0590 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD2_DATA2__UART6_DCE_RX 0x0248 0x0590 0x0858 0x7 0x4 +-#define MX6SX_PAD_SD2_DATA2__UART6_DTE_TX 0x0248 0x0590 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2 0x0248 0x0590 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD2_DATA2__MMDC_DEBUG_32 0x0248 0x0590 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x024C 0x0594 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD2_DATA3__AUDMUX_AUD6_TXD 0x024C 0x0594 0x0678 0x1 0x2 +-#define MX6SX_PAD_SD2_DATA3__KPP_COL_6 0x024C 0x0594 0x07CC 0x2 0x1 +-#define MX6SX_PAD_SD2_DATA3__ECSPI4_MISO 0x024C 0x0594 0x0744 0x3 0x1 +-#define MX6SX_PAD_SD2_DATA3__MLB_DATA 0x024C 0x0594 0x07EC 0x4 0x2 +-#define MX6SX_PAD_SD2_DATA3__GPIO6_IO_11 0x024C 0x0594 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD2_DATA3__SPDIF_IN 0x024C 0x0594 0x0824 0x6 0x4 +-#define MX6SX_PAD_SD2_DATA3__UART6_DCE_TX 0x024C 0x0594 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD2_DATA3__UART6_DTE_RX 0x024C 0x0594 0x0858 0x7 0x5 +-#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD3_CLK__UART4_DCE_CTS 0x0250 0x0598 0x0000 0x1 0x0 +-#define MX6SX_PAD_SD3_CLK__UART4_DTE_RTS 0x0250 0x0598 0x0844 0x1 0x0 +-#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0 +-#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0 +-#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD3_CLK__GPIO7_IO_0 0x0250 0x0598 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD3_CLK__LCDIF2_BUSY 0x0250 0x0598 0x07E4 0x6 0x0 +-#define MX6SX_PAD_SD3_CLK__TPSMP_HDATA_29 0x0250 0x0598 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5 0x0250 0x0598 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x0254 0x059C 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD3_CMD__UART4_DCE_TX 0x0254 0x059C 0x0000 0x1 0x0 +-#define MX6SX_PAD_SD3_CMD__UART4_DTE_RX 0x0254 0x059C 0x0848 0x1 0x0 +-#define MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x0254 0x059C 0x0748 0x2 0x0 +-#define MX6SX_PAD_SD3_CMD__AUDMUX_AUD6_RXC 0x0254 0x059C 0x067C 0x3 0x0 +-#define MX6SX_PAD_SD3_CMD__LCDIF2_HSYNC 0x0254 0x059C 0x07E4 0x4 0x1 +-#define MX6SX_PAD_SD3_CMD__GPIO7_IO_1 0x0254 0x059C 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD3_CMD__LCDIF2_RS 0x0254 0x059C 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD3_CMD__TPSMP_HDATA_28 0x0254 0x059C 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4 0x0254 0x059C 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x0258 0x05A0 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x0258 0x05A0 0x07C0 0x1 0x0 +-#define MX6SX_PAD_SD3_DATA0__ECSPI2_SS1 0x0258 0x05A0 0x0000 0x2 0x0 +-#define MX6SX_PAD_SD3_DATA0__AUDMUX_AUD6_RXD 0x0258 0x05A0 0x0674 0x3 0x0 +-#define MX6SX_PAD_SD3_DATA0__LCDIF2_DATA_1 0x0258 0x05A0 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD3_DATA0__GPIO7_IO_2 0x0258 0x05A0 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD3_DATA0__DCIC1_OUT 0x0258 0x05A0 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD3_DATA0__TPSMP_HDATA_30 0x0258 0x05A0 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD3_DATA0__GPU_DEBUG_0 0x0258 0x05A0 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0 0x0258 0x05A0 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x025C 0x05A4 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x025C 0x05A4 0x07C4 0x1 0x0 +-#define MX6SX_PAD_SD3_DATA1__ECSPI2_SS2 0x025C 0x05A4 0x0000 0x2 0x0 +-#define MX6SX_PAD_SD3_DATA1__AUDMUX_AUD6_TXC 0x025C 0x05A4 0x0684 0x3 0x0 +-#define MX6SX_PAD_SD3_DATA1__LCDIF2_DATA_0 0x025C 0x05A4 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD3_DATA1__GPIO7_IO_3 0x025C 0x05A4 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD3_DATA1__DCIC2_OUT 0x025C 0x05A4 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD3_DATA1__TPSMP_HDATA_31 0x025C 0x05A4 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD3_DATA1__GPU_DEBUG_1 0x025C 0x05A4 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD3_DATA2__UART4_DCE_RTS 0x0260 0x05A8 0x0844 0x1 0x1 +-#define MX6SX_PAD_SD3_DATA2__UART4_DTE_CTS 0x0260 0x05A8 0x0000 0x1 0x0 +-#define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0 +-#define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0 +-#define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x0260 0x05A8 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD3_DATA2__LCDIF2_WR_RWN 0x0260 0x05A8 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD3_DATA2__TPSMP_HDATA_26 0x0260 0x05A8 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD3_DATA2__GPU_DEBUG_2 0x0260 0x05A8 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2 0x0260 0x05A8 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x0264 0x05AC 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD3_DATA3__UART4_DCE_RX 0x0264 0x05AC 0x0848 0x1 0x1 +-#define MX6SX_PAD_SD3_DATA3__UART4_DTE_TX 0x0264 0x05AC 0x0000 0x1 0x0 +-#define MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x0264 0x05AC 0x0744 0x2 0x0 +-#define MX6SX_PAD_SD3_DATA3__AUDMUX_AUD6_TXD 0x0264 0x05AC 0x0678 0x3 0x0 +-#define MX6SX_PAD_SD3_DATA3__LCDIF2_ENABLE 0x0264 0x05AC 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD3_DATA3__GPIO7_IO_5 0x0264 0x05AC 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD3_DATA3__LCDIF2_RD_E 0x0264 0x05AC 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD3_DATA3__TPSMP_HDATA_27 0x0264 0x05AC 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD3_DATA3__GPU_DEBUG_3 0x0264 0x05AC 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD3_DATA3__SDMA_DEBUG_EVENT_CHANNEL_3 0x0264 0x05AC 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x0268 0x05B0 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD3_DATA4__CAN2_RX 0x0268 0x05B0 0x0690 0x1 0x0 +-#define MX6SX_PAD_SD3_DATA4__CANFD_RX2 0x0268 0x05B0 0x0698 0x2 0x0 +-#define MX6SX_PAD_SD3_DATA4__UART3_DCE_RX 0x0268 0x05B0 0x0840 0x3 0x2 +-#define MX6SX_PAD_SD3_DATA4__UART3_DTE_TX 0x0268 0x05B0 0x0000 0x3 0x0 +-#define MX6SX_PAD_SD3_DATA4__LCDIF2_DATA_3 0x0268 0x05B0 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x0268 0x05B0 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN 0x0268 0x05B0 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD3_DATA4__TPSMP_HTRANS_1 0x0268 0x05B0 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD3_DATA4__GPU_DEBUG_4 0x0268 0x05B0 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD3_DATA4__SDMA_DEBUG_BUS_DEVICE_0 0x0268 0x05B0 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x026C 0x05B4 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD3_DATA5__CAN1_TX 0x026C 0x05B4 0x0000 0x1 0x0 +-#define MX6SX_PAD_SD3_DATA5__CANFD_TX1 0x026C 0x05B4 0x0000 0x2 0x0 +-#define MX6SX_PAD_SD3_DATA5__UART3_DCE_TX 0x026C 0x05B4 0x0000 0x3 0x0 +-#define MX6SX_PAD_SD3_DATA5__UART3_DTE_RX 0x026C 0x05B4 0x0840 0x3 0x3 +-#define MX6SX_PAD_SD3_DATA5__LCDIF2_DATA_2 0x026C 0x05B4 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x026C 0x05B4 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT 0x026C 0x05B4 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD3_DATA5__SIM_M_HWRITE 0x026C 0x05B4 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD3_DATA5__GPU_DEBUG_5 0x026C 0x05B4 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD3_DATA5__SDMA_DEBUG_BUS_DEVICE_1 0x026C 0x05B4 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x0270 0x05B8 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0 +-#define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0 +-#define MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x0270 0x05B8 0x083C 0x3 0x2 +-#define MX6SX_PAD_SD3_DATA6__UART3_DTE_CTS 0x0270 0x05B8 0x0000 0x3 0x0 +-#define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD3_DATA6__TPSMP_HTRANS_0 0x0270 0x05B8 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD3_DATA6__GPU_DEBUG_7 0x0270 0x05B8 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD3_DATA6__SDMA_DEBUG_EVT_CHN_LINES_7 0x0270 0x05B8 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0 +-#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0 +-#define MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x0274 0x05BC 0x0000 0x3 0x0 +-#define MX6SX_PAD_SD3_DATA7__UART3_DTE_RTS 0x0274 0x05BC 0x083C 0x3 0x3 +-#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD3_DATA7__TPSMP_HDATA_DIR 0x0274 0x05BC 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD3_DATA7__GPU_DEBUG_6 0x0274 0x05BC 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD3_DATA7__SDMA_DEBUG_EVT_CHN_LINES_2 0x0274 0x05BC 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x0278 0x05C0 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD4_CLK__RAWNAND_DATA15 0x0278 0x05C0 0x0000 0x1 0x0 +-#define MX6SX_PAD_SD4_CLK__ECSPI2_MISO 0x0278 0x05C0 0x0724 0x2 0x1 +-#define MX6SX_PAD_SD4_CLK__AUDMUX_AUD3_RXFS 0x0278 0x05C0 0x0638 0x3 0x0 +-#define MX6SX_PAD_SD4_CLK__LCDIF2_DATA_13 0x0278 0x05C0 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD4_CLK__GPIO6_IO_12 0x0278 0x05C0 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD4_CLK__ECSPI3_SS2 0x0278 0x05C0 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD4_CLK__TPSMP_HDATA_20 0x0278 0x05C0 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD4_CLK__VDEC_DEBUG_12 0x0278 0x05C0 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD4_CLK__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x0278 0x05C0 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x027C 0x05C4 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD4_CMD__RAWNAND_DATA14 0x027C 0x05C4 0x0000 0x1 0x0 +-#define MX6SX_PAD_SD4_CMD__ECSPI2_MOSI 0x027C 0x05C4 0x0728 0x2 0x1 +-#define MX6SX_PAD_SD4_CMD__AUDMUX_AUD3_RXC 0x027C 0x05C4 0x0634 0x3 0x0 +-#define MX6SX_PAD_SD4_CMD__LCDIF2_DATA_14 0x027C 0x05C4 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD4_CMD__GPIO6_IO_13 0x027C 0x05C4 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD4_CMD__ECSPI3_SS1 0x027C 0x05C4 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD4_CMD__TPSMP_HDATA_19 0x027C 0x05C4 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD4_CMD__VDEC_DEBUG_11 0x027C 0x05C4 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD4_CMD__SDMA_DEBUG_CORE_RUN 0x027C 0x05C4 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x0280 0x05C8 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD4_DATA0__RAWNAND_DATA10 0x0280 0x05C8 0x0000 0x1 0x0 +-#define MX6SX_PAD_SD4_DATA0__ECSPI2_SS0 0x0280 0x05C8 0x072C 0x2 0x1 +-#define MX6SX_PAD_SD4_DATA0__AUDMUX_AUD3_RXD 0x0280 0x05C8 0x062C 0x3 0x0 +-#define MX6SX_PAD_SD4_DATA0__LCDIF2_DATA_12 0x0280 0x05C8 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD4_DATA0__GPIO6_IO_14 0x0280 0x05C8 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD4_DATA0__ECSPI3_SS3 0x0280 0x05C8 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD4_DATA0__TPSMP_HDATA_21 0x0280 0x05C8 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD4_DATA0__VDEC_DEBUG_13 0x0280 0x05C8 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD4_DATA0__SDMA_DEBUG_MODE 0x0280 0x05C8 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x0284 0x05CC 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD4_DATA1__RAWNAND_DATA11 0x0284 0x05CC 0x0000 0x1 0x0 +-#define MX6SX_PAD_SD4_DATA1__ECSPI2_SCLK 0x0284 0x05CC 0x0720 0x2 0x1 +-#define MX6SX_PAD_SD4_DATA1__AUDMUX_AUD3_TXC 0x0284 0x05CC 0x063C 0x3 0x0 +-#define MX6SX_PAD_SD4_DATA1__LCDIF2_DATA_11 0x0284 0x05CC 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD4_DATA1__GPIO6_IO_15 0x0284 0x05CC 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD4_DATA1__ECSPI3_RDY 0x0284 0x05CC 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD4_DATA1__TPSMP_HDATA_22 0x0284 0x05CC 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD4_DATA1__VDEC_DEBUG_14 0x0284 0x05CC 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD4_DATA1__SDMA_DEBUG_BUS_ERROR 0x0284 0x05CC 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x0288 0x05D0 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD4_DATA2__RAWNAND_DATA12 0x0288 0x05D0 0x0000 0x1 0x0 +-#define MX6SX_PAD_SD4_DATA2__I2C2_SDA 0x0288 0x05D0 0x07B4 0x2 0x0 +-#define MX6SX_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS 0x0288 0x05D0 0x0640 0x3 0x0 +-#define MX6SX_PAD_SD4_DATA2__LCDIF2_DATA_10 0x0288 0x05D0 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD4_DATA2__GPIO6_IO_16 0x0288 0x05D0 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD4_DATA2__ECSPI2_SS3 0x0288 0x05D0 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD4_DATA2__TPSMP_HDATA_23 0x0288 0x05D0 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD4_DATA2__VDEC_DEBUG_15 0x0288 0x05D0 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD4_DATA2__SDMA_DEBUG_BUS_RWB 0x0288 0x05D0 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x028C 0x05D4 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD4_DATA3__RAWNAND_DATA13 0x028C 0x05D4 0x0000 0x1 0x0 +-#define MX6SX_PAD_SD4_DATA3__I2C2_SCL 0x028C 0x05D4 0x07B0 0x2 0x0 +-#define MX6SX_PAD_SD4_DATA3__AUDMUX_AUD3_TXD 0x028C 0x05D4 0x0630 0x3 0x0 +-#define MX6SX_PAD_SD4_DATA3__LCDIF2_DATA_9 0x028C 0x05D4 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD4_DATA3__GPIO6_IO_17 0x028C 0x05D4 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD4_DATA3__ECSPI2_RDY 0x028C 0x05D4 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD4_DATA3__TPSMP_HDATA_24 0x028C 0x05D4 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD4_DATA3__VDEC_DEBUG_16 0x028C 0x05D4 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS 0x028C 0x05D4 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x0290 0x05D8 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD4_DATA4__RAWNAND_DATA09 0x0290 0x05D8 0x0000 0x1 0x0 +-#define MX6SX_PAD_SD4_DATA4__UART5_DCE_RX 0x0290 0x05D8 0x0850 0x2 0x0 +-#define MX6SX_PAD_SD4_DATA4__UART5_DTE_TX 0x0290 0x05D8 0x0000 0x2 0x0 +-#define MX6SX_PAD_SD4_DATA4__ECSPI3_SCLK 0x0290 0x05D8 0x0730 0x3 0x0 +-#define MX6SX_PAD_SD4_DATA4__LCDIF2_DATA_8 0x0290 0x05D8 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x0290 0x05D8 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x0290 0x05D8 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD4_DATA4__TPSMP_HDATA_16 0x0290 0x05D8 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD4_DATA4__USB_OTG_HOST_MODE 0x0290 0x05D8 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE 0x0290 0x05D8 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x0294 0x05DC 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD4_DATA5__RAWNAND_CE2_B 0x0294 0x05DC 0x0000 0x1 0x0 +-#define MX6SX_PAD_SD4_DATA5__UART5_DCE_TX 0x0294 0x05DC 0x0000 0x2 0x0 +-#define MX6SX_PAD_SD4_DATA5__UART5_DTE_RX 0x0294 0x05DC 0x0850 0x2 0x1 +-#define MX6SX_PAD_SD4_DATA5__ECSPI3_MOSI 0x0294 0x05DC 0x0738 0x3 0x0 +-#define MX6SX_PAD_SD4_DATA5__LCDIF2_DATA_7 0x0294 0x05DC 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD4_DATA5__GPIO6_IO_19 0x0294 0x05DC 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD4_DATA5__SPDIF_IN 0x0294 0x05DC 0x0824 0x6 0x0 +-#define MX6SX_PAD_SD4_DATA5__TPSMP_HDATA_17 0x0294 0x05DC 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD4_DATA5__VDEC_DEBUG_9 0x0294 0x05DC 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0 0x0294 0x05DC 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0 +-#define MX6SX_PAD_SD4_DATA6__UART5_DCE_RTS 0x0298 0x05E0 0x084C 0x2 0x0 +-#define MX6SX_PAD_SD4_DATA6__UART5_DTE_CTS 0x0298 0x05E0 0x0000 0x2 0x0 +-#define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0 +-#define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD4_DATA6__USDHC4_WP 0x0298 0x05E0 0x0878 0x6 0x0 +-#define MX6SX_PAD_SD4_DATA6__TPSMP_HDATA_18 0x0298 0x05E0 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD4_DATA6__VDEC_DEBUG_10 0x0298 0x05E0 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0 +-#define MX6SX_PAD_SD4_DATA7__UART5_DCE_CTS 0x029C 0x05E4 0x0000 0x2 0x0 +-#define MX6SX_PAD_SD4_DATA7__UART5_DTE_RTS 0x029C 0x05E4 0x084C 0x2 0x1 +-#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0 +-#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD4_DATA7__USDHC4_CD_B 0x029C 0x05E4 0x0874 0x6 0x0 +-#define MX6SX_PAD_SD4_DATA7__TPSMP_HDATA_15 0x029C 0x05E4 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD4_DATA7__USB_OTG_PWR_WAKE 0x029C 0x05E4 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD4_DATA7__SDMA_DEBUG_YIELD 0x029C 0x05E4 0x0000 0x9 0x0 +-#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x02A0 0x05E8 0x0000 0x0 0x0 +-#define MX6SX_PAD_SD4_RESET_B__RAWNAND_DQS 0x02A0 0x05E8 0x0000 0x1 0x0 +-#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET 0x02A0 0x05E8 0x0000 0x2 0x0 +-#define MX6SX_PAD_SD4_RESET_B__AUDMUX_MCLK 0x02A0 0x05E8 0x0000 0x3 0x0 +-#define MX6SX_PAD_SD4_RESET_B__LCDIF2_RESET 0x02A0 0x05E8 0x0000 0x4 0x0 +-#define MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x02A0 0x05E8 0x0000 0x5 0x0 +-#define MX6SX_PAD_SD4_RESET_B__LCDIF2_CS 0x02A0 0x05E8 0x0000 0x6 0x0 +-#define MX6SX_PAD_SD4_RESET_B__TPSMP_HDATA_25 0x02A0 0x05E8 0x0000 0x7 0x0 +-#define MX6SX_PAD_SD4_RESET_B__VDEC_DEBUG_17 0x02A0 0x05E8 0x0000 0x8 0x0 +-#define MX6SX_PAD_SD4_RESET_B__SDMA_DEBUG_BUS_DEVICE_2 0x02A0 0x05E8 0x0000 0x9 0x0 +-#define MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x02A4 0x05EC 0x0000 0x0 0x0 +-#define MX6SX_PAD_USB_H_DATA__PWM2_OUT 0x02A4 0x05EC 0x0000 0x1 0x0 +-#define MX6SX_PAD_USB_H_DATA__ANATOP_24M_OUT 0x02A4 0x05EC 0x0000 0x2 0x0 +-#define MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x02A4 0x05EC 0x07C4 0x3 0x1 +-#define MX6SX_PAD_USB_H_DATA__WDOG3_WDOG_B 0x02A4 0x05EC 0x0000 0x4 0x0 +-#define MX6SX_PAD_USB_H_DATA__GPIO7_IO_10 0x02A4 0x05EC 0x0000 0x5 0x0 +-#define MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x02A8 0x05F0 0x0000 0x0 0x0 +-#define MX6SX_PAD_USB_H_STROBE__PWM1_OUT 0x02A8 0x05F0 0x0000 0x1 0x0 +-#define MX6SX_PAD_USB_H_STROBE__ANATOP_32K_OUT 0x02A8 0x05F0 0x0000 0x2 0x0 +-#define MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x02A8 0x05F0 0x07C0 0x3 0x1 +-#define MX6SX_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB 0x02A8 0x05F0 0x0000 0x4 0x0 +-#define MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x02A8 0x05F0 0x0000 0x5 0x0 +- +-/* these are not supposed to be used any more and remove them after some time */ +-#define MX6SX_PAD_GPIO1_IO04__UART1_RX MX6SX_PAD_GPIO1_IO04__UART1_DTE_RX +-#define MX6SX_PAD_GPIO1_IO04__UART1_TX MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX +-#define MX6SX_PAD_GPIO1_IO05__UART1_RX MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX +-#define MX6SX_PAD_GPIO1_IO05__UART1_TX MX6SX_PAD_GPIO1_IO05__UART1_DTE_TX +-#define MX6SX_PAD_GPIO1_IO06__UART2_RX MX6SX_PAD_GPIO1_IO06__UART2_DTE_RX +-#define MX6SX_PAD_GPIO1_IO06__UART2_TX MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX +-#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B MX6SX_PAD_GPIO1_IO06__UART1_DCE_RTS +-#define MX6SX_PAD_GPIO1_IO07__UART2_RX MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX +-#define MX6SX_PAD_GPIO1_IO07__UART2_TX MX6SX_PAD_GPIO1_IO07__UART2_DTE_TX +-#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B MX6SX_PAD_GPIO1_IO07__UART1_DCE_CTS +-#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B MX6SX_PAD_GPIO1_IO08__UART2_DCE_RTS +-#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B MX6SX_PAD_GPIO1_IO09__UART2_DCE_CTS +-#define MX6SX_PAD_CSI_DATA04__UART6_RX MX6SX_PAD_CSI_DATA04__UART6_DCE_RX +-#define MX6SX_PAD_CSI_DATA04__UART6_TX MX6SX_PAD_CSI_DATA04__UART6_DTE_TX +-#define MX6SX_PAD_CSI_DATA05__UART6_RX MX6SX_PAD_CSI_DATA05__UART6_DTE_RX +-#define MX6SX_PAD_CSI_DATA05__UART6_TX MX6SX_PAD_CSI_DATA05__UART6_DCE_TX +-#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS +-#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS +-#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B MX6SX_PAD_CSI_HSYNC__UART4_DCE_RTS +-#define MX6SX_PAD_CSI_MCLK__UART4_RX MX6SX_PAD_CSI_MCLK__UART4_DCE_RX +-#define MX6SX_PAD_CSI_MCLK__UART4_TX MX6SX_PAD_CSI_MCLK__UART4_DTE_TX +-#define MX6SX_PAD_CSI_PIXCLK__UART4_RX MX6SX_PAD_CSI_PIXCLK__UART4_DTE_RX +-#define MX6SX_PAD_CSI_PIXCLK__UART4_TX MX6SX_PAD_CSI_PIXCLK__UART4_DCE_TX +-#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B MX6SX_PAD_CSI_VSYNC__UART4_DCE_CTS +-#define MX6SX_PAD_ENET2_COL__UART1_RX MX6SX_PAD_ENET2_COL__UART1_DCE_RX +-#define MX6SX_PAD_ENET2_COL__UART1_TX MX6SX_PAD_ENET2_COL__UART1_DTE_TX +-#define MX6SX_PAD_ENET2_CRS__UART1_RX MX6SX_PAD_ENET2_CRS__UART1_DTE_RX +-#define MX6SX_PAD_ENET2_CRS__UART1_TX MX6SX_PAD_ENET2_CRS__UART1_DCE_TX +-#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B MX6SX_PAD_ENET2_RX_CLK__UART1_DCE_RTS +-#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B MX6SX_PAD_ENET2_TX_CLK__UART1_DCE_CTS +-#define MX6SX_PAD_KEY_COL0__UART6_RTS_B MX6SX_PAD_KEY_COL0__UART6_DCE_RTS +-#define MX6SX_PAD_KEY_COL1__UART6_RX MX6SX_PAD_KEY_COL1__UART6_DTE_RX +-#define MX6SX_PAD_KEY_COL1__UART6_TX MX6SX_PAD_KEY_COL1__UART6_DCE_TX +-#define MX6SX_PAD_KEY_COL2__UART5_RTS_B MX6SX_PAD_KEY_COL2__UART5_DCE_RTS +-#define MX6SX_PAD_KEY_COL3__UART5_RX MX6SX_PAD_KEY_COL3__UART5_DTE_RX +-#define MX6SX_PAD_KEY_COL3__UART5_TX MX6SX_PAD_KEY_COL3__UART5_DCE_TX +-#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B MX6SX_PAD_KEY_ROW0__UART6_DCE_CTS +-#define MX6SX_PAD_KEY_ROW1__UART6_RX MX6SX_PAD_KEY_ROW1__UART6_DCE_RX +-#define MX6SX_PAD_KEY_ROW1__UART6_TX MX6SX_PAD_KEY_ROW1__UART6_DTE_TX +-#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS +-#define MX6SX_PAD_KEY_ROW3__UART5_RX MX6SX_PAD_KEY_ROW3__UART5_DCE_RX +-#define MX6SX_PAD_KEY_ROW3__UART5_TX MX6SX_PAD_KEY_ROW3__UART5_DTE_TX +-#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B MX6SX_PAD_NAND_DATA04__UART3_DCE_RTS +-#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B MX6SX_PAD_NAND_DATA05__UART3_DCE_CTS +-#define MX6SX_PAD_NAND_DATA06__UART3_RX MX6SX_PAD_NAND_DATA06__UART3_DCE_RX +-#define MX6SX_PAD_NAND_DATA06__UART3_TX MX6SX_PAD_NAND_DATA06__UART3_DTE_TX +-#define MX6SX_PAD_NAND_DATA07__UART3_RX MX6SX_PAD_NAND_DATA07__UART3_DTE_RX +-#define MX6SX_PAD_NAND_DATA07__UART3_TX MX6SX_PAD_NAND_DATA07__UART3_DCE_TX +-#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B MX6SX_PAD_QSPI1B_DATA0__UART3_DCE_CTS +-#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B MX6SX_PAD_QSPI1B_DATA1__UART3_DCE_RTS +-#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX +-#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX +-#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX MX6SX_PAD_QSPI1B_SS0_B__UART3_DTE_RX +-#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX +-#define MX6SX_PAD_SD1_DATA0__UART2_RX MX6SX_PAD_SD1_DATA0__UART2_DCE_RX +-#define MX6SX_PAD_SD1_DATA0__UART2_TX MX6SX_PAD_SD1_DATA0__UART2_DTE_TX +-#define MX6SX_PAD_SD1_DATA1__UART2_RX MX6SX_PAD_SD1_DATA1__UART2_DTE_RX +-#define MX6SX_PAD_SD1_DATA1__UART2_TX MX6SX_PAD_SD1_DATA1__UART2_DCE_TX +-#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B MX6SX_PAD_SD1_DATA2__UART2_DCE_CTS +-#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B MX6SX_PAD_SD1_DATA3__UART2_DCE_RTS +-#define MX6SX_PAD_SD2_DATA0__UART4_RX MX6SX_PAD_SD2_DATA0__UART4_DCE_RX +-#define MX6SX_PAD_SD2_DATA0__UART4_TX MX6SX_PAD_SD2_DATA0__UART4_DTE_TX +-#define MX6SX_PAD_SD2_DATA1__UART4_RX MX6SX_PAD_SD2_DATA1__UART4_DTE_RX +-#define MX6SX_PAD_SD2_DATA1__UART4_TX MX6SX_PAD_SD2_DATA1__UART4_DCE_TX +-#define MX6SX_PAD_SD2_DATA2__UART6_RX MX6SX_PAD_SD2_DATA2__UART6_DCE_RX +-#define MX6SX_PAD_SD2_DATA2__UART6_TX MX6SX_PAD_SD2_DATA2__UART6_DTE_TX +-#define MX6SX_PAD_SD2_DATA3__UART6_RX MX6SX_PAD_SD2_DATA3__UART6_DTE_RX +-#define MX6SX_PAD_SD2_DATA3__UART6_TX MX6SX_PAD_SD2_DATA3__UART6_DCE_TX +-#define MX6SX_PAD_SD3_CLK__UART4_CTS_B MX6SX_PAD_SD3_CLK__UART4_DCE_CTS +-#define MX6SX_PAD_SD3_CMD__UART4_RX MX6SX_PAD_SD3_CMD__UART4_DTE_RX +-#define MX6SX_PAD_SD3_CMD__UART4_TX MX6SX_PAD_SD3_CMD__UART4_DCE_TX +-#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B MX6SX_PAD_SD3_DATA2__UART4_DCE_RTS +-#define MX6SX_PAD_SD3_DATA3__UART4_RX MX6SX_PAD_SD3_DATA3__UART4_DCE_RX +-#define MX6SX_PAD_SD3_DATA3__UART4_TX MX6SX_PAD_SD3_DATA3__UART4_DTE_TX +-#define MX6SX_PAD_SD3_DATA4__UART3_RX MX6SX_PAD_SD3_DATA4__UART3_DCE_RX +-#define MX6SX_PAD_SD3_DATA4__UART3_TX MX6SX_PAD_SD3_DATA4__UART3_DTE_TX +-#define MX6SX_PAD_SD3_DATA5__UART3_RX MX6SX_PAD_SD3_DATA5__UART3_DTE_RX +-#define MX6SX_PAD_SD3_DATA5__UART3_TX MX6SX_PAD_SD3_DATA5__UART3_DCE_TX +-#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS +-#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS +-#define MX6SX_PAD_SD4_DATA4__UART5_RX MX6SX_PAD_SD4_DATA4__UART5_DCE_RX +-#define MX6SX_PAD_SD4_DATA4__UART5_TX MX6SX_PAD_SD4_DATA4__UART5_DTE_TX +-#define MX6SX_PAD_SD4_DATA5__UART5_RX MX6SX_PAD_SD4_DATA5__UART5_DTE_RX +-#define MX6SX_PAD_SD4_DATA5__UART5_TX MX6SX_PAD_SD4_DATA5__UART5_DCE_TX +-#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B MX6SX_PAD_SD4_DATA6__UART5_DCE_RTS +-#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B MX6SX_PAD_SD4_DATA7__UART5_DCE_CTS +- +-#endif /* __DTS_IMX6SX_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm/imx6sx-sabreauto.dts b/scripts/dtc/include-prefixes/arm/imx6sx-sabreauto.dts +deleted file mode 100644 +index 83ee97252ff1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sx-sabreauto.dts ++++ /dev/null +@@ -1,557 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright (C) 2014 Freescale Semiconductor, Inc. +- +-/dts-v1/; +- +-#include "imx6sx.dtsi" +- +-/ { +- model = "Freescale i.MX6 SoloX Sabre Auto Board"; +- compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x80000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led>; +- +- user { +- label = "debug"; +- gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- vcc_sd3: regulator-vcc-sd3 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_vcc_sd3>; +- regulator-name = "VCC_SD3"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_can_wake: regulator-can-wake { +- compatible = "regulator-fixed"; +- regulator-name = "can-wake"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_can_en: regulator-can-en { +- compatible = "regulator-fixed"; +- regulator-name = "can-en"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_can_wake>; +- }; +- +- reg_can_stby: regulator-can-stby { +- compatible = "regulator-fixed"; +- regulator-name = "can-stby"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_can_en>; +- }; +- +- reg_cs42888: cs42888_supply { +- compatible = "regulator-fixed"; +- regulator-name = "cs42888_supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- sound-cs42888 { +- compatible = "fsl,imx6-sabreauto-cs42888", +- "fsl,imx-audio-cs42888"; +- model = "imx-cs42888"; +- audio-cpu = <&esai>; +- audio-asrc = <&asrc>; +- audio-codec = <&cs42888>; +- audio-routing = +- "Line Out Jack", "AOUT1L", +- "Line Out Jack", "AOUT1R", +- "Line Out Jack", "AOUT2L", +- "Line Out Jack", "AOUT2R", +- "Line Out Jack", "AOUT3L", +- "Line Out Jack", "AOUT3R", +- "Line Out Jack", "AOUT4L", +- "Line Out Jack", "AOUT4R", +- "AIN1L", "Line In Jack", +- "AIN1R", "Line In Jack", +- "AIN2L", "Line In Jack", +- "AIN2R", "Line In Jack"; +- }; +- +- sound-spdif { +- compatible = "fsl,imx-audio-spdif"; +- model = "imx-spdif"; +- spdif-controller = <&spdif>; +- spdif-in; +- }; +-}; +- +-&anaclk2 { +- clock-frequency = <24576000>; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>, +- <&clks IMX6SX_PLL4_BYPASS>, +- <&clks IMX6SX_CLK_PLL4_POST_DIV>; +- assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>, +- <&clks IMX6SX_PLL4_BYPASS_SRC>; +- assigned-clock-rates = <0>, <0>, <24576000>; +-}; +- +-&esai { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esai>; +- assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>, +- <&clks IMX6SX_CLK_ESAI_EXTAL>; +- assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>; +- assigned-clock-rates = <0>, <24576000>; +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy1>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +- }; +-}; +- +-&fec2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet2>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- status = "okay"; +-}; +- +-&flexcan1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- xceiver-supply = <®_can_stby>; +- status = "okay"; +-}; +- +-&flexcan2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- xceiver-supply = <®_can_stby>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- bus-width = <8>; +- cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; +- keep-power-in-suspend; +- wakeup-source; +- vmmc-supply = <&vcc_sd3>; +- status = "okay"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- bus-width = <8>; +- cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- keep-power-in-suspend; +- wakeup-source; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_egalax_int: egalax-intgrp { +- fsl,pins = < +- MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x10b0 +- >; +- }; +- +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 +- MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 +- MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 +- MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 +- MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 +- MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 +- MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 +- MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 +- MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 +- MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 +- MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 +- MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 +- MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 +- MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 +- >; +- }; +- +- pinctrl_enet2: enet2grp { +- fsl,pins = < +- MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 +- MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 +- MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 +- MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 +- MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 +- MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 +- MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 +- MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 +- MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 +- MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 +- MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 +- MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 +- >; +- }; +- +- pinctrl_esai: esaigrp { +- fsl,pins = < +- MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 +- MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 +- MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 +- MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 +- MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 +- MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 +- MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 +- MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 +- MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 +- MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 +- MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 +- MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 +- MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 +- MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_led: ledgrp { +- fsl,pins = < +- MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059 +- >; +- }; +- +- pinctrl_spdif: spdifgrp { +- fsl,pins = < +- MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 +- MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 +- MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 +- MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 +- MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 +- MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 +- MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 +- MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 +- MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 +- MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 +- MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 +- MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ +- MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { +- fsl,pins = < +- MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 +- MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 +- MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 +- MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 +- MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 +- MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 +- MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 +- MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 +- MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 +- MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { +- fsl,pins = < +- MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 +- MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 +- MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 +- MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 +- MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 +- MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 +- MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 +- MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 +- MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 +- MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 +- MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 +- MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 +- MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 +- MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 +- MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 +- MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ +- MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ +- >; +- }; +- +- pinctrl_vcc_sd3: vccsd3grp { +- fsl,pins = < +- MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 +- >; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- cs42888: cs42888@48 { +- compatible = "cirrus,cs42888"; +- reg = <0x48>; +- clocks = <&anaclk2 0>; +- clock-names = "mclk"; +- VA-supply = <®_cs42888>; +- VD-supply = <®_cs42888>; +- VLS-supply = <®_cs42888>; +- VLC-supply = <®_cs42888>; +- }; +- +- touchscreen@4 { +- compatible = "eeti,egalax_ts"; +- reg = <0x04>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_egalax_int>; +- interrupt-parent = <&gpio6>; +- interrupts = <22 IRQ_TYPE_EDGE_FALLING>; +- wakeup-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; +- }; +- +- pfuze100: pmic@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- regulator-always-on; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +- +- max7322: gpio@68 { +- compatible = "maxim,max7322"; +- reg = <0x68>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- max7310_a: gpio@30 { +- compatible = "maxim,max7310"; +- reg = <0x30>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- max7310_b: gpio@32 { +- compatible = "maxim,max7310"; +- reg = <0x32>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&spdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spdif>; +- assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>; +- assigned-clock-rates = <24576000>; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sx-sdb-mqs.dts b/scripts/dtc/include-prefixes/arm/imx6sx-sdb-mqs.dts +deleted file mode 100644 +index a4ab2d3e960c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sx-sdb-mqs.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright (C) 2014 Freescale Semiconductor, Inc. +- +-#include "imx6sx-sdb.dts" +-/ { +- +- sound { +- status = "disabled"; +- }; +- +- sound-mqs { +- compatible = "fsl,imx6sx-sdb-mqs", +- "fsl,imx-audio-mqs"; +- model = "mqs-audio"; +- audio-cpu = <&sai1>; +- audio-asrc = <&asrc>; +- audio-codec = <&mqs>; +- }; +-}; +- +-&usdhc2 { +- /* pin conflict with mqs*/ +- status = "disabled"; +-}; +- +-&mqs { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mqs>; +- clocks = <&clks IMX6SX_CLK_SAI1>; +- clock-names = "mclk"; +- status = "okay"; +-}; +- +-&sai1 { +- pinctrl-0 = <>; +- status = "okay"; +-}; +- +-&ssi2 { +- status = "disabled"; +-}; +- +-&sdma { +- gpr = <&gpr>; +- /* SDMA event remap for SAI1 */ +- fsl,sdma-event-remap = <0 15 1>, <0 16 1>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sx-sdb-reva.dts b/scripts/dtc/include-prefixes/arm/imx6sx-sdb-reva.dts +deleted file mode 100644 +index dce5dcf96c25..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sx-sdb-reva.dts ++++ /dev/null +@@ -1,169 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright (C) 2015 Freescale Semiconductor, Inc. +- +-#include "imx6sx-sdb.dtsi" +- +-/ { +- model = "Freescale i.MX6 SoloX SDB RevA Board"; +- compatible = "fsl,imx6sx-sdb-reva", "fsl,imx6sx"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic: pfuze100@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- regulator-always-on; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&qspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_qspi2>; +- status = "okay"; +- +- flash0: s25fl128s@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25fl128s", "jedec,spi-nor"; +- spi-max-frequency = <66000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <4>; +- }; +- +- flash1: s25fl128s@2 { +- reg = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25fl128s", "jedec,spi-nor"; +- spi-max-frequency = <66000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <4>; +- }; +-}; +- +-®_can_en { +- /* Transceiver EN/STBY is active high on RevA board */ +- gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; +- enable-active-high; +-}; +- +-®_can_stby { +- gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_can_en>; +-}; +- +-®_vdd1p1 { +- vin-supply = <&vgen6_reg>; +-}; +- +-®_vdd2p5 { +- vin-supply = <&vgen6_reg>; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sx-sdb-sai.dts b/scripts/dtc/include-prefixes/arm/imx6sx-sdb-sai.dts +deleted file mode 100644 +index 1c4eacd68e1b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sx-sdb-sai.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright (C) 2016 Freescale Semiconductor, Inc. +- +-#include "imx6sx-sdb.dts" +- +-/ { +- sound { +- audio-cpu = <&sai1>; +- }; +-}; +- +-&audmux { +- /* pin conflict with sai */ +- status = "disabled"; +-}; +- +-&sai1 { +- status = "okay"; +-}; +- +-&sdma { +- gpr = <&gpr>; +- /* SDMA event remap for SAI1 */ +- fsl,sdma-event-remap = <0 15 1>, <0 16 1>; +-}; +- +-&ssi2 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sx-sdb.dts b/scripts/dtc/include-prefixes/arm/imx6sx-sdb.dts +deleted file mode 100644 +index 99f4cf777a38..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sx-sdb.dts ++++ /dev/null +@@ -1,155 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright (C) 2015 Freescale Semiconductor, Inc. +- +-#include "imx6sx-sdb.dtsi" +- +-/ { +- model = "Freescale i.MX6 SoloX SDB RevB Board"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic: pfuze100@8 { +- compatible = "fsl,pfuze200"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- regulator-always-on; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&qspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_qspi2>; +- status = "okay"; +- +- flash0: n25q256a@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q256a", "jedec,spi-nor"; +- spi-max-frequency = <29000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <1>; +- reg = <0>; +- }; +- +- flash1: n25q256a@2 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q256a", "jedec,spi-nor"; +- spi-max-frequency = <29000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <1>; +- reg = <2>; +- }; +-}; +- +-®_arm { +- vin-supply = <&sw1a_reg>; +-}; +- +-®_soc { +- vin-supply = <&sw1a_reg>; +-}; +- +-®_vdd1p1 { +- vin-supply = <&vgen6_reg>; +-}; +- +-®_vdd2p5 { +- vin-supply = <&vgen6_reg>; +-}; +- +-®_can_stby { +- /* Transceiver EN/STBY is active low on RevB board */ +- gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sx-sdb.dtsi b/scripts/dtc/include-prefixes/arm/imx6sx-sdb.dtsi +deleted file mode 100644 +index c6e85e4a0883..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sx-sdb.dtsi ++++ /dev/null +@@ -1,718 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright (C) 2014 Freescale Semiconductor, Inc. +- +-/dts-v1/; +- +-#include +-#include +-#include "imx6sx.dtsi" +- +-/ { +- model = "Freescale i.MX6 SoloX SDB Board"; +- compatible = "fsl,imx6sx-sdb", "fsl,imx6sx"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; +- }; +- +- backlight_display: backlight-display { +- compatible = "pwm-backlight"; +- pwms = <&pwm3 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- volume-down { +- label = "Volume Down"; +- gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- vcc_sd3: regulator-vcc-sd3 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_vcc_sd3>; +- regulator-name = "VCC_SD3"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_otg1_vbus: regulator-usb-otg1-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_otg1>; +- regulator-name = "usb_otg1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_otg2_vbus: regulator-usb-otg2-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_otg2>; +- regulator-name = "usb_otg2_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_psu_5v: regulator-psu-5v { +- compatible = "regulator-fixed"; +- regulator-name = "PSU-5V0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_lcd_3v3: regulator-lcd-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "lcd-3v3"; +- gpio = <&gpio3 27 0>; +- enable-active-high; +- }; +- +- reg_peri_3v3: regulator-peri-3v3 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_peri_3v3>; +- regulator-name = "peri_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- reg_enet_3v3: regulator-enet-3v3 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet_3v3>; +- regulator-name = "enet_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_pcie_gpio: regulator-pcie-gpio { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie_reg>; +- regulator-name = "MPCIE_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_lcd_5v: regulator-lcd-5v { +- compatible = "regulator-fixed"; +- regulator-name = "lcd-5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_can_en: regulator-can-en { +- compatible = "regulator-fixed"; +- regulator-name = "can-en"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_can_stby: regulator-can-stby { +- compatible = "regulator-fixed"; +- regulator-name = "can-stby"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- sound { +- compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hp>; +- model = "wm8962-audio"; +- ssi-controller = <&ssi2>; +- audio-codec = <&codec>; +- audio-routing = +- "Headphone Jack", "HPOUTL", +- "Headphone Jack", "HPOUTR", +- "Ext Spk", "SPKOUTL", +- "Ext Spk", "SPKOUTR", +- "AMIC", "MICBIAS", +- "IN3R", "AMIC"; +- mux-int-port = <2>; +- mux-ext-port = <6>; +- hp-det-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>; +- }; +- +- panel { +- compatible = "sii,43wvf1g"; +- backlight = <&backlight_display>; +- dvdd-supply = <®_lcd_3v3>; +- avdd-supply = <®_lcd_5v>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +- +- sound-spdif { +- compatible = "fsl,imx-audio-spdif", +- "fsl,imx6sx-sdb-spdif"; +- model = "imx-spdif"; +- spdif-controller = <&spdif>; +- spdif-out; +- }; +- +-}; +- +-&audmux { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audmux>; +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- phy-supply = <®_enet_3v3>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy1>; +- phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- }; +- +- ethphy2: ethernet-phy@2 { +- reg = <2>; +- }; +- }; +-}; +- +-&fec2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet2>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy2>; +- fsl,magic-packet; +- status = "okay"; +-}; +- +-&flexcan1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- xceiver-supply = <®_can_stby>; +- status = "okay"; +-}; +- +-&flexcan2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- xceiver-supply = <®_can_stby>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&i2c4 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +- +- codec: wm8962@1a { +- compatible = "wlf,wm8962"; +- reg = <0x1a>; +- clocks = <&clks IMX6SX_CLK_AUDIO>; +- DCVDD-supply = <&vgen4_reg>; +- DBVDD-supply = <&vgen4_reg>; +- AVDD-supply = <&vgen4_reg>; +- CPVDD-supply = <&vgen4_reg>; +- MICVDD-supply = <&vgen3_reg>; +- PLLVDD-supply = <&vgen4_reg>; +- SPKVDD1-supply = <®_psu_5v>; +- SPKVDD2-supply = <®_psu_5v>; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>; +- vpcie-supply = <®_pcie_gpio>; +- status = "okay"; +-}; +- +-&lcdif1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd>; +- status = "okay"; +- +- port { +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +-}; +- +-&pwm3 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "okay"; +-}; +- +-&snvs_poweroff { +- status = "okay"; +-}; +- +-&sai1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai1>; +- status = "disabled"; +-}; +- +-&spdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spdif>; +- assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>; +- assigned-clock-rates = <24576000>; +- status = "okay"; +-}; +- +-&ssi2 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart5 { /* for bluetooth */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbotg1 { +- vbus-supply = <®_usb_otg1_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_otg1_id>; +- status = "okay"; +-}; +- +-&usbotg2 { +- vbus-supply = <®_usb_otg2_vbus>; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbphy1 { +- fsl,tx-d-cal = <106>; +-}; +- +-&usbphy2 { +- fsl,tx-d-cal = <106>; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- non-removable; +- no-1-8-v; +- keep-power-in-suspend; +- wakeup-source; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- bus-width = <8>; +- cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; +- keep-power-in-suspend; +- wakeup-source; +- vmmc-supply = <&vcc_sd3>; +- status = "okay"; +-}; +- +-&usdhc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc4>; +- cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- imx6x-sdb { +- pinctrl_audmux: audmuxgrp { +- fsl,pins = < +- MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 +- MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0 +- MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0 +- MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0 +- MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 +- >; +- }; +- +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 +- MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 +- MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 +- MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 +- MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 +- MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 +- MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 +- MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 +- MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 +- MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 +- MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 +- MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 +- MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 +- MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 +- MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 +- /* phy reset */ +- MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x10b0 +- >; +- }; +- +- pinctrl_enet_3v3: enet3v3grp { +- fsl,pins = < +- MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000 +- >; +- }; +- +- pinctrl_enet2: enet2grp { +- fsl,pins = < +- MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 +- MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 +- MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 +- MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 +- MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 +- MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 +- MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 +- MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 +- MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 +- MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 +- MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 +- MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 +- MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 +- MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 +- >; +- }; +- +- pinctrl_gpio_keys: gpio_keysgrp { +- fsl,pins = < +- MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 +- MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059 +- >; +- }; +- +- pinctrl_hp: hpgrp { +- fsl,pins = < +- MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 +- MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 +- MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 +- MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_lcd: lcdgrp { +- fsl,pins = < +- MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 +- MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 +- MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 +- MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 +- MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 +- MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 +- MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 +- >; +- }; +- +- pinctrl_mqs: mqsgrp { +- fsl,pins = < +- MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0 +- MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0 +- >; +- }; +- +- pinctrl_pcie_reg: pciereggrp { +- fsl,pins = < +- MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0 +- >; +- }; +- +- pinctrl_peri_3v3: peri3v3grp { +- fsl,pins = < +- MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp-1 { +- fsl,pins = < +- MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 +- >; +- }; +- +- pinctrl_qspi2: qspi2grp { +- fsl,pins = < +- MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1 +- MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1 +- MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1 +- MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1 +- MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1 +- MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1 +- MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1 +- MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1 +- MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1 +- MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1 +- MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1 +- MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1 +- >; +- }; +- +- pinctrl_vcc_sd3: vccsd3grp { +- fsl,pins = < +- MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 +- >; +- }; +- +- pinctrl_sai1: sai1grp { +- fsl,pins = < +- MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0 +- MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0 +- MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0 +- MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0 +- MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 +- >; +- }; +- +- pinctrl_spdif: spdifgrp { +- fsl,pins = < +- MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 +- MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1 +- MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1 +- MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x1b0b1 +- MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x1b0b1 +- >; +- }; +- +- pinctrl_usb_otg1: usbotg1grp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 +- >; +- }; +- +- pinctrl_usb_otg1_id: usbotg1idgrp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 +- >; +- }; +- +- pinctrl_usb_otg2: usbot2ggrp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 +- MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 +- MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 +- MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 +- MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 +- MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 +- MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 +- MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 +- MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 +- MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 +- MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 +- MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 +- MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 +- MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 +- MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 +- MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ +- MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { +- fsl,pins = < +- MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 +- MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 +- MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 +- MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 +- MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 +- MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 +- MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 +- MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 +- MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 +- MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { +- fsl,pins = < +- MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 +- MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 +- MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 +- MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 +- MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 +- MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 +- MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 +- MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 +- MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 +- MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 +- >; +- }; +- +- pinctrl_usdhc4: usdhc4grp { +- fsl,pins = < +- MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 +- MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 +- MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 +- MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 +- MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 +- MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 +- MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ +- MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sx-softing-vining-2000.dts b/scripts/dtc/include-prefixes/arm/imx6sx-softing-vining-2000.dts +deleted file mode 100644 +index b9a1401e6c6d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sx-softing-vining-2000.dts ++++ /dev/null +@@ -1,587 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2016 Christoph Fritz +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "imx6sx.dtsi" +- +-/ { +- model = "Softing VIN|ING 2000"; +- compatible = "samtec,imx6sx-vining-2000", "fsl,imx6sx"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; +- }; +- +- reg_usb_otg1_vbus: regulator-usb_otg1_vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg1_vbus"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_otg1>; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_peri_3v3: regulator-peri_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "peri_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- led-controller { +- compatible = "pwm-leds"; +- +- led-1 { +- label = "red"; +- max-brightness = <255>; +- pwms = <&pwm6 0 50000>; +- }; +- +- led-2 { +- label = "green"; +- max-brightness = <255>; +- pwms = <&pwm2 0 50000>; +- }; +- +- led-3 { +- label = "blue"; +- max-brightness = <255>; +- pwms = <&pwm1 0 50000>; +- }; +- }; +-}; +- +-&adc1 { +- vref-supply = <®_peri_3v3>; +- status = "okay"; +-}; +- +-&cpu0 { +- /* +- * This board has a shared rail of reg_arm and reg_soc (supplied by +- * sw1a_reg) which is modeled below, but still this module behaves +- * unstable without higher voltages. Hence, set higher voltages here. +- */ +- operating-points = < +- /* kHz uV */ +- 996000 1250000 +- 792000 1175000 +- 396000 1175000 +- 198000 1175000 +- >; +- fsl,soc-operating-points = < +- /* ARM kHz SOC uV */ +- 996000 1250000 +- 792000 1175000 +- 396000 1175000 +- 198000 1175000 +- >; +-}; +- +-&ecspi4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi4>; +- cs-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- phy-supply = <®_peri_3v3>; +- phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <5>; +- phy-mode = "rmii"; +- phy-handle = <ðphy0>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet0-phy@0 { +- reg = <0>; +- max-speed = <100>; +- interrupt-parent = <&gpio2>; +- interrupts = <17 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +-}; +- +-&fec2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet2>; +- phy-supply = <®_peri_3v3>; +- phy-reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <5>; +- phy-mode = "rmii"; +- phy-handle = <ðphy1>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy1: ethernet1-phy@0 { +- reg = <0>; +- max-speed = <100>; +- interrupt-parent = <&gpio2>; +- interrupts = <19 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +-}; +- +-&flexcan1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- status = "okay"; +-}; +- +-&flexcan2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- proximity: sx9500@28 { +- compatible = "semtech,sx9500"; +- reg = <0x28>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sx9500>; +- interrupt-parent = <&gpio2>; +- interrupts = <16 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; +- }; +- +- pmic: pfuze100@8 { +- compatible = "fsl,pfuze200"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3a { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3b_reg: sw3b { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- regulator-always-on; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpios>; +- +- pinctrl_ecspi4: ecspi4grp { +- fsl,pins = < +- MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x130b1 +- MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x130b1 +- MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x130b1 +- MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x30b0 +- >; +- }; +- +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x30c1 +- MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x30c1 +- MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0f9 +- MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0f9 +- MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x30c1 +- MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0f9 +- MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4000a038 +- /* LAN8720 PHY Reset */ +- MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x10b0 +- /* MDIO */ +- MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0f9 +- MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0f9 +- /* IRQ from PHY */ +- MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x10b0 +- >; +- }; +- +- pinctrl_enet2: enet2grp { +- fsl,pins = < +- MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x1b0b0 +- MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x1b0b0 +- MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x1b0b0 +- MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x1b0b0 +- MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x1b0b0 +- MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x1b0b0 +- MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4000a038 +- /* LAN8720 PHY Reset */ +- MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x10b0 +- /* MDIO */ +- MX6SX_PAD_ENET1_COL__ENET2_MDC 0xa0f9 +- MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0xa0f9 +- /* IRQ from PHY */ +- MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x10b0 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 +- MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 +- MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 +- >; +- }; +- +- pinctrl_gpios: gpiosgrp { +- fsl,pins = < +- /* reset external uC */ +- MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x10b0 +- /* IRQ from external uC */ +- MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x10b0 +- /* overcurrent detection */ +- MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x10b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 +- MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6SX_PAD_NAND_ALE__I2C3_SDA 0x4001b8b1 +- MX6SX_PAD_NAND_CLE__I2C3_SCL 0x4001b8b1 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x10b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp-1 { +- fsl,pins = < +- /* blue LED */ +- MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp-1 { +- fsl,pins = < +- /* green LED */ +- MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_pwm6: pwm6grp-1 { +- fsl,pins = < +- /* red LED */ +- MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x1b0b1 +- >; +- }; +- +- pinctrl_sx9500: sx9500grp { +- fsl,pins = < +- /* Reset */ +- MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x838 +- /* IRQ */ +- MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x70e0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 +- MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1 +- MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_usb_otg1: usbotg1grp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 +- >; +- }; +- +- pinctrl_usb_otg1_id: usbotg1idgrp { +- fsl,pins = < +- MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc2_50mhz: usdhc2grp-50mhz { +- fsl,pins = < +- MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 +- MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 +- MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 +- MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 +- MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 +- MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 +- MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x1b000 +- MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x10b0 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { +- fsl,pins = < +- MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100b9 +- MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170b9 +- MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170b9 +- MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170b9 +- MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170b9 +- MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { +- fsl,pins = < +- MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100f9 +- MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170f9 +- MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170f9 +- MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170f9 +- MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170f9 +- MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170f9 +- >; +- }; +- +- pinctrl_usdhc4_50mhz: usdhc4grp-50mhz { +- fsl,pins = < +- MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 +- MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 +- MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 +- MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 +- MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 +- MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 +- MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 +- MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 +- MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 +- MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 +- MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17068 +- >; +- }; +- +- pinctrl_usdhc4_100mhz: usdhc4-100mhz { +- fsl,pins = < +- MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 +- MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 +- MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 +- MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 +- MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 +- MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 +- MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 +- MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 +- MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 +- MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 +- >; +- }; +- +- pinctrl_usdhc4_200mhz: usdhc4-200mhz { +- fsl,pins = < +- MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 +- MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 +- MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 +- MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 +- MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 +- MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 +- MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 +- MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 +- MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 +- MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 +- >; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; +- reset-gpio-active-high; +- status = "okay"; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&pwm2 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- status = "okay"; +-}; +- +-&pwm6 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm6>; +- status = "okay"; +-}; +- +-®_arm { +- vin-supply = <&sw1a_reg>; +-}; +- +-®_soc { +- vin-supply = <&sw1a_reg>; +-}; +- +-&snvs_poweroff { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usbotg1 { +- vbus-supply = <®_usb_otg1_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_otg1_id>; +- status = "okay"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2_50mhz>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>; +- cd-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; +- keep-power-in-suspend; +- status = "okay"; +-}; +- +-&usdhc4 { +- /* hs200-mode is currently unsupported because Vccq is on 3.1V, but +- * not on necessary 1.8V. +- */ +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc4_50mhz>; +- pinctrl-1 = <&pinctrl_usdhc4_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc4_200mhz>; +- bus-width = <8>; +- keep-power-in-suspend; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sx-udoo-neo-basic.dts b/scripts/dtc/include-prefixes/arm/imx6sx-udoo-neo-basic.dts +deleted file mode 100644 +index 205ea26484e3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sx-udoo-neo-basic.dts ++++ /dev/null +@@ -1,33 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "imx6sx-udoo-neo.dtsi" +- +-/ { +- model = "UDOO Neo Basic"; +- compatible = "udoo,neobasic", "fsl,imx6sx"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +-}; +- +-&fec1 { +- phy-handle = <ðphy1>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy1: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sx-udoo-neo-extended.dts b/scripts/dtc/include-prefixes/arm/imx6sx-udoo-neo-extended.dts +deleted file mode 100644 +index 5817b4985391..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sx-udoo-neo-extended.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "imx6sx-udoo-neo.dtsi" +- +-/ { +- model = "UDOO Neo Extended"; +- compatible = "udoo,neoextended", "fsl,imx6sx"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; +- }; +-}; +- +-&i2c4 { /* Onboard Motion sensors */ +- status = "okay"; +-}; +- +-&uart3 { /* Bluetooth */ +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sx-udoo-neo-full.dts b/scripts/dtc/include-prefixes/arm/imx6sx-udoo-neo-full.dts +deleted file mode 100644 +index 96f4d89848a3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sx-udoo-neo-full.dts ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "imx6sx-udoo-neo.dtsi" +- +-/ { +- model = "UDOO Neo Full"; +- compatible = "udoo,neofull", "fsl,imx6sx"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; +- }; +-}; +- +-&fec1 { +- phy-handle = <ðphy1>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy1: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +- }; +-}; +- +-&i2c4 { /* Onboard Motion sensors */ +- status = "okay"; +-}; +- +-&uart3 { /* Bluetooth */ +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sx-udoo-neo.dtsi b/scripts/dtc/include-prefixes/arm/imx6sx-udoo-neo.dtsi +deleted file mode 100644 +index ee645655090d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sx-udoo-neo.dtsi ++++ /dev/null +@@ -1,410 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Andreas Färber +- */ +- +-#include "imx6sx.dtsi" +- +-/ { +- compatible = "fsl,imx6sx"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- red { +- label = "udoo-neo:red:mmc"; +- gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "mmc0"; +- }; +- +- orange { +- label = "udoo-neo:orange:user"; +- gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; +- }; +- }; +- +- reg_sdio_pwr: regulator-sdio-pwr { +- compatible = "regulator-fixed"; +- gpio = <&gpio6 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-name = "SDIO_PWR"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- +- reg_usb_otg1_vbus: regulator-usb-otg1-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_otg1_reg>; +- regulator-name = "usb_otg1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_otg2_vbus: regulator-usb-otg2-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_otg2_reg>; +- regulator-name = "usb_otg2_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_wlan: regulator-wlan { +- compatible = "regulator-fixed"; +- regulator-name = "wlan-en-regulator"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <70000>; +- enable-active-high; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- phy-mode = "rmii"; +- phy-reset-duration = <10>; +- phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clock-frequency = <100000>; +- status = "okay"; +- +- pmic: pmic@8 { +- compatible = "fsl,pfuze3000"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1a { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1475000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1b { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1475000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1650000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen2_reg: vldo2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vccsd { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen4_reg: v33 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vldo3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vldo4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c2 { /* Brick snap in sensors connector */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&i2c4 { /* Onboard Motion sensors */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- clock-frequency = <100000>; +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_bt_reg: btreggrp { +- fsl,pins = +- ; +- }; +- +- pinctrl_enet1: enet1grp { +- fsl,pins = +- , +- , +- , +- , +- , +- , +- +- , +- , +- , +- , +- , +- , +- +- ; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = +- , +- ; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = +- , +- ; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = +- , +- ; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = +- , +- ; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = +- , +- ; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = +- , +- , +- , +- ; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = +- , +- ; +- }; +- +- pinctrl_uart6: uart6grp { +- fsl,pins = +- , +- , +- , +- , +- , +- , +- , +- ; +- }; +- +- pinctrl_otg1_reg: otg1grp { +- fsl,pins = +- ; +- }; +- +- +- pinctrl_otg2_reg: otg2grp { +- fsl,pins = +- ; +- }; +- +- pinctrl_usb_otg1: usbotg1grp { +- fsl,pins = +- , +- ; +- }; +- +- pinctrl_usb_otg2: usbot2ggrp { +- fsl,pins = +- ; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = +- , +- , +- , +- , +- , +- , +- ; /* CD */ +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-/* Cortex-M4 serial */ +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "disabled"; +-}; +- +-&uart3 { /* Bluetooth - only on Extended/Full versions */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "disabled"; +- +- bluetooth { +- compatible = "ti,wl1831-st"; +- enable-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_bt_reg>; +- max-speed = <921600>; +- }; +-}; +- +-/* Arduino serial */ +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "disabled"; +-}; +- +-&uart6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart6>; +- uart-has-rtscts; +- status = "disabled"; +-}; +- +-&usbotg1 { /* J2 micro USB port */ +- vbus-supply = <®_usb_otg1_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_otg1>; +- status = "okay"; +-}; +- +-&usbotg2 { /* J3 host USB port */ +- vbus-supply = <®_usb_otg2_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_otg2>; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- vmmc-supply = <®_sdio_pwr>; +- bus-width = <4>; +- cd-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- keep-power-in-suspend; +- wakeup-source; +- status = "okay"; +-}; +- +-&usdhc3 { /* Wi-Fi */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- non-removable; +- vmmc-supply = <®_wlan>; +- cap-power-off-card; +- wakeup-source; +- keep-power-in-suspend; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- wlcore: wlcore@2 { +- compatible = "ti,wl1831"; +- reg = <2>; +- interrupt-parent = <&gpio2>; +- interrupts = <16 IRQ_TYPE_EDGE_RISING>; +- ref-clock-frequency = <38400000>; +- tcxo-clock-frequency = <26000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6sx.dtsi b/scripts/dtc/include-prefixes/arm/imx6sx.dtsi +deleted file mode 100644 +index 8516730778df..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6sx.dtsi ++++ /dev/null +@@ -1,1426 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright 2014 Freescale Semiconductor, Inc. +- +-#include +-#include +-#include +-#include +-#include "imx6sx-pinfunc.h" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * The decompressor and also some bootloaders rely on a +- * pre-existing /chosen node to be available to insert the +- * command line and merge other ATAGS info. +- */ +- chosen {}; +- +- aliases { +- can0 = &flexcan1; +- can1 = &flexcan2; +- ethernet0 = &fec1; +- ethernet1 = &fec2; +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- gpio3 = &gpio4; +- gpio4 = &gpio5; +- gpio5 = &gpio6; +- gpio6 = &gpio7; +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- i2c3 = &i2c4; +- mmc0 = &usdhc1; +- mmc1 = &usdhc2; +- mmc2 = &usdhc3; +- mmc3 = &usdhc4; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- serial4 = &uart5; +- serial5 = &uart6; +- spi0 = &ecspi1; +- spi1 = &ecspi2; +- spi2 = &ecspi3; +- spi3 = &ecspi4; +- spi4 = &ecspi5; +- usb0 = &usbotg1; +- usb1 = &usbotg2; +- usb2 = &usbh; +- usbphy0 = &usbphy1; +- usbphy1 = &usbphy2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <0>; +- next-level-cache = <&L2>; +- operating-points = < +- /* kHz uV */ +- 996000 1250000 +- 792000 1175000 +- 396000 1075000 +- 198000 975000 +- >; +- fsl,soc-operating-points = < +- /* ARM kHz SOC uV */ +- 996000 1175000 +- 792000 1175000 +- 396000 1175000 +- 198000 1175000 +- >; +- clock-latency = <61036>; /* two CLK32 periods */ +- #cooling-cells = <2>; +- clocks = <&clks IMX6SX_CLK_ARM>, +- <&clks IMX6SX_CLK_PLL2_PFD2>, +- <&clks IMX6SX_CLK_STEP>, +- <&clks IMX6SX_CLK_PLL1_SW>, +- <&clks IMX6SX_CLK_PLL1_SYS>; +- clock-names = "arm", "pll2_pfd2_396m", "step", +- "pll1_sw", "pll1_sys"; +- arm-supply = <®_arm>; +- soc-supply = <®_soc>; +- nvmem-cells = <&cpu_speed_grade>; +- nvmem-cell-names = "speed_grade"; +- }; +- }; +- +- ckil: clock-ckil { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "ckil"; +- }; +- +- osc: clock-osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "osc"; +- }; +- +- ipp_di0: clock-ipp-di0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- clock-output-names = "ipp_di0"; +- }; +- +- ipp_di1: clock-ipp-di1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- clock-output-names = "ipp_di1"; +- }; +- +- anaclk1: clock-anaclk1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- clock-output-names = "anaclk1"; +- }; +- +- anaclk2: clock-anaclk2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- clock-output-names = "anaclk2"; +- }; +- +- mqs: mqs { +- compatible = "fsl,imx6sx-mqs"; +- gpr = <&gpr>; +- status = "disabled"; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupt-parent = <&gpc>; +- interrupts = ; +- }; +- +- usbphynop1: usbphynop1 { +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&gpc>; +- ranges; +- +- ocram_s: sram@8f8000 { +- compatible = "mmio-sram"; +- reg = <0x008f8000 0x4000>; +- clocks = <&clks IMX6SX_CLK_OCRAM_S>; +- }; +- +- ocram: sram@900000 { +- compatible = "mmio-sram"; +- reg = <0x00900000 0x20000>; +- clocks = <&clks IMX6SX_CLK_OCRAM>; +- }; +- +- intc: interrupt-controller@a01000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x00a01000 0x1000>, +- <0x00a00100 0x100>; +- interrupt-parent = <&intc>; +- }; +- +- L2: cache-controller@a02000 { +- compatible = "arm,pl310-cache"; +- reg = <0x00a02000 0x1000>; +- interrupts = ; +- cache-unified; +- cache-level = <2>; +- arm,tag-latency = <4 2 3>; +- arm,data-latency = <4 2 3>; +- }; +- +- gpu: gpu@1800000 { +- compatible = "vivante,gc"; +- reg = <0x01800000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_GPU>, +- <&clks IMX6SX_CLK_GPU>, +- <&clks IMX6SX_CLK_GPU>; +- clock-names = "bus", "core", "shader"; +- power-domains = <&pd_pu>; +- }; +- +- dma_apbh: dma-apbh@1804000 { +- compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; +- reg = <0x01804000 0x2000>; +- interrupts = , +- , +- , +- ; +- interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; +- #dma-cells = <1>; +- dma-channels = <4>; +- clocks = <&clks IMX6SX_CLK_APBH_DMA>; +- }; +- +- gpmi: nand-controller@1806000{ +- compatible = "fsl,imx6sx-gpmi-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x01806000 0x2000>, <0x01808000 0x4000>; +- reg-names = "gpmi-nand", "bch"; +- interrupts = ; +- interrupt-names = "bch"; +- clocks = <&clks IMX6SX_CLK_GPMI_IO>, +- <&clks IMX6SX_CLK_GPMI_APB>, +- <&clks IMX6SX_CLK_GPMI_BCH>, +- <&clks IMX6SX_CLK_GPMI_BCH_APB>, +- <&clks IMX6SX_CLK_PER1_BCH>; +- clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", +- "gpmi_bch_apb", "per1_bch"; +- dmas = <&dma_apbh 0>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- aips1: bus@2000000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x02000000 0x100000>; +- ranges; +- +- spba-bus@2000000 { +- compatible = "fsl,spba-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x02000000 0x40000>; +- ranges; +- +- spdif: spdif@2004000 { +- compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; +- reg = <0x02004000 0x4000>; +- interrupts = ; +- dmas = <&sdma 14 18 0>, +- <&sdma 15 18 0>; +- dma-names = "rx", "tx"; +- clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>, +- <&clks IMX6SX_CLK_OSC>, +- <&clks IMX6SX_CLK_SPDIF>, +- <&clks 0>, <&clks 0>, <&clks 0>, +- <&clks IMX6SX_CLK_IPG>, +- <&clks 0>, <&clks 0>, +- <&clks IMX6SX_CLK_SPBA>; +- clock-names = "core", "rxtx0", +- "rxtx1", "rxtx2", +- "rxtx3", "rxtx4", +- "rxtx5", "rxtx6", +- "rxtx7", "spba"; +- status = "disabled"; +- }; +- +- ecspi1: spi@2008000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; +- reg = <0x02008000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_ECSPI1>, +- <&clks IMX6SX_CLK_ECSPI1>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- ecspi2: spi@200c000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; +- reg = <0x0200c000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_ECSPI2>, +- <&clks IMX6SX_CLK_ECSPI2>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- ecspi3: spi@2010000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; +- reg = <0x02010000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_ECSPI3>, +- <&clks IMX6SX_CLK_ECSPI3>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- ecspi4: spi@2014000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; +- reg = <0x02014000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_ECSPI4>, +- <&clks IMX6SX_CLK_ECSPI4>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart1: serial@2020000 { +- compatible = "fsl,imx6sx-uart", +- "fsl,imx6q-uart", "fsl,imx21-uart"; +- reg = <0x02020000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_UART_IPG>, +- <&clks IMX6SX_CLK_UART_SERIAL>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- esai: esai@2024000 { +- compatible = "fsl,imx6sx-esai", "fsl,imx35-esai"; +- reg = <0x02024000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_ESAI_IPG>, +- <&clks IMX6SX_CLK_ESAI_MEM>, +- <&clks IMX6SX_CLK_ESAI_EXTAL>, +- <&clks IMX6SX_CLK_ESAI_IPG>, +- <&clks IMX6SX_CLK_SPBA>; +- clock-names = "core", "mem", "extal", +- "fsys", "spba"; +- dmas = <&sdma 23 21 0>, +- <&sdma 24 21 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ssi1: ssi@2028000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; +- reg = <0x02028000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_SSI1_IPG>, +- <&clks IMX6SX_CLK_SSI1>; +- clock-names = "ipg", "baud"; +- dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- ssi2: ssi@202c000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; +- reg = <0x0202c000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_SSI2_IPG>, +- <&clks IMX6SX_CLK_SSI2>; +- clock-names = "ipg", "baud"; +- dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- ssi3: ssi@2030000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; +- reg = <0x02030000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_SSI3_IPG>, +- <&clks IMX6SX_CLK_SSI3>; +- clock-names = "ipg", "baud"; +- dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; +- dma-names = "rx", "tx"; +- fsl,fifo-depth = <15>; +- status = "disabled"; +- }; +- +- asrc: asrc@2034000 { +- compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc"; +- reg = <0x02034000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_ASRC_IPG>, +- <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>, +- <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, +- <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, +- <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, +- <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>, +- <&clks IMX6SX_CLK_SPBA>; +- clock-names = "mem", "ipg", "asrck_0", +- "asrck_1", "asrck_2", "asrck_3", "asrck_4", +- "asrck_5", "asrck_6", "asrck_7", "asrck_8", +- "asrck_9", "asrck_a", "asrck_b", "asrck_c", +- "asrck_d", "asrck_e", "asrck_f", "spba"; +- dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, +- <&sdma 19 23 1>, <&sdma 20 23 1>, +- <&sdma 21 23 1>, <&sdma 22 23 1>; +- dma-names = "rxa", "rxb", "rxc", +- "txa", "txb", "txc"; +- fsl,asrc-rate = <48000>; +- fsl,asrc-width = <16>; +- status = "okay"; +- }; +- }; +- +- pwm1: pwm@2080000 { +- compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; +- reg = <0x02080000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_PWM1>, +- <&clks IMX6SX_CLK_PWM1>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- }; +- +- pwm2: pwm@2084000 { +- compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; +- reg = <0x02084000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_PWM2>, +- <&clks IMX6SX_CLK_PWM2>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- }; +- +- pwm3: pwm@2088000 { +- compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; +- reg = <0x02088000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_PWM3>, +- <&clks IMX6SX_CLK_PWM3>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- }; +- +- pwm4: pwm@208c000 { +- compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; +- reg = <0x0208c000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_PWM4>, +- <&clks IMX6SX_CLK_PWM4>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- }; +- +- flexcan1: can@2090000 { +- compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; +- reg = <0x02090000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_CAN1_IPG>, +- <&clks IMX6SX_CLK_CAN1_SERIAL>; +- clock-names = "ipg", "per"; +- fsl,stop-mode = <&gpr 0x10 1>; +- status = "disabled"; +- }; +- +- flexcan2: can@2094000 { +- compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; +- reg = <0x02094000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_CAN2_IPG>, +- <&clks IMX6SX_CLK_CAN2_SERIAL>; +- clock-names = "ipg", "per"; +- fsl,stop-mode = <&gpr 0x10 2>; +- status = "disabled"; +- }; +- +- gpt: timer@2098000 { +- compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt"; +- reg = <0x02098000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_GPT_BUS>, +- <&clks IMX6SX_CLK_GPT_3M>; +- clock-names = "ipg", "per"; +- }; +- +- gpio1: gpio@209c000 { +- compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; +- reg = <0x0209c000 0x4000>; +- interrupts = , +- ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 5 26>; +- }; +- +- gpio2: gpio@20a0000 { +- compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; +- reg = <0x020a0000 0x4000>; +- interrupts = , +- ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 31 20>; +- }; +- +- gpio3: gpio@20a4000 { +- compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; +- reg = <0x020a4000 0x4000>; +- interrupts = , +- ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 51 29>; +- }; +- +- gpio4: gpio@20a8000 { +- compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; +- reg = <0x020a8000 0x4000>; +- interrupts = , +- ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 80 32>; +- }; +- +- gpio5: gpio@20ac000 { +- compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; +- reg = <0x020ac000 0x4000>; +- interrupts = , +- ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 112 24>; +- }; +- +- gpio6: gpio@20b0000 { +- compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; +- reg = <0x020b0000 0x4000>; +- interrupts = , +- ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>; +- }; +- +- gpio7: gpio@20b4000 { +- compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; +- reg = <0x020b4000 0x4000>; +- interrupts = , +- ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; +- }; +- +- kpp: keypad@20b8000 { +- compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; +- reg = <0x020b8000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_IPG>; +- status = "disabled"; +- }; +- +- wdog1: watchdog@20bc000 { +- compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; +- reg = <0x020bc000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_IPG>; +- }; +- +- wdog2: watchdog@20c0000 { +- compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; +- reg = <0x020c0000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_IPG>; +- status = "disabled"; +- }; +- +- clks: clock-controller@20c4000 { +- compatible = "fsl,imx6sx-ccm"; +- reg = <0x020c4000 0x4000>; +- interrupts = , +- ; +- #clock-cells = <1>; +- clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>; +- clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2"; +- }; +- +- anatop: anatop@20c8000 { +- compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", +- "syscon", "simple-mfd"; +- reg = <0x020c8000 0x1000>; +- interrupts = , +- , +- ; +- +- reg_vdd1p1: regulator-1p1 { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vdd1p1"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- anatop-reg-offset = <0x110>; +- anatop-vol-bit-shift = <8>; +- anatop-vol-bit-width = <5>; +- anatop-min-bit-val = <4>; +- anatop-min-voltage = <800000>; +- anatop-max-voltage = <1375000>; +- anatop-enable-bit = <0>; +- }; +- +- reg_vdd3p0: regulator-3p0 { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vdd3p0"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <3150000>; +- regulator-always-on; +- anatop-reg-offset = <0x120>; +- anatop-vol-bit-shift = <8>; +- anatop-vol-bit-width = <5>; +- anatop-min-bit-val = <0>; +- anatop-min-voltage = <2625000>; +- anatop-max-voltage = <3400000>; +- anatop-enable-bit = <0>; +- }; +- +- reg_vdd2p5: regulator-2p5 { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vdd2p5"; +- regulator-min-microvolt = <2250000>; +- regulator-max-microvolt = <2750000>; +- regulator-always-on; +- anatop-reg-offset = <0x130>; +- anatop-vol-bit-shift = <8>; +- anatop-vol-bit-width = <5>; +- anatop-min-bit-val = <0>; +- anatop-min-voltage = <2100000>; +- anatop-max-voltage = <2875000>; +- anatop-enable-bit = <0>; +- }; +- +- reg_arm: regulator-vddcore { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vddarm"; +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1450000>; +- regulator-always-on; +- anatop-reg-offset = <0x140>; +- anatop-vol-bit-shift = <0>; +- anatop-vol-bit-width = <5>; +- anatop-delay-reg-offset = <0x170>; +- anatop-delay-bit-shift = <24>; +- anatop-delay-bit-width = <2>; +- anatop-min-bit-val = <1>; +- anatop-min-voltage = <725000>; +- anatop-max-voltage = <1450000>; +- }; +- +- reg_pcie: regulator-vddpcie { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vddpcie"; +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1450000>; +- anatop-reg-offset = <0x140>; +- anatop-vol-bit-shift = <9>; +- anatop-vol-bit-width = <5>; +- anatop-delay-reg-offset = <0x170>; +- anatop-delay-bit-shift = <26>; +- anatop-delay-bit-width = <2>; +- anatop-min-bit-val = <1>; +- anatop-min-voltage = <725000>; +- anatop-max-voltage = <1450000>; +- }; +- +- reg_soc: regulator-vddsoc { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vddsoc"; +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1450000>; +- regulator-always-on; +- anatop-reg-offset = <0x140>; +- anatop-vol-bit-shift = <18>; +- anatop-vol-bit-width = <5>; +- anatop-delay-reg-offset = <0x170>; +- anatop-delay-bit-shift = <28>; +- anatop-delay-bit-width = <2>; +- anatop-min-bit-val = <1>; +- anatop-min-voltage = <725000>; +- anatop-max-voltage = <1450000>; +- }; +- +- tempmon: tempmon { +- compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; +- interrupt-parent = <&gpc>; +- interrupts = ; +- fsl,tempmon = <&anatop>; +- nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; +- nvmem-cell-names = "calib", "temp_grade"; +- clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; +- }; +- }; +- +- usbphy1: usbphy@20c9000 { +- compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; +- reg = <0x020c9000 0x1000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_USBPHY1>; +- fsl,anatop = <&anatop>; +- }; +- +- usbphy2: usbphy@20ca000 { +- compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; +- reg = <0x020ca000 0x1000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_USBPHY2>; +- fsl,anatop = <&anatop>; +- }; +- +- snvs: snvs@20cc000 { +- compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; +- reg = <0x020cc000 0x4000>; +- +- snvs_rtc: snvs-rtc-lp { +- compatible = "fsl,sec-v4.0-mon-rtc-lp"; +- regmap = <&snvs>; +- offset = <0x34>; +- interrupts = , ; +- }; +- +- snvs_poweroff: snvs-poweroff { +- compatible = "syscon-poweroff"; +- regmap = <&snvs>; +- offset = <0x38>; +- value = <0x60>; +- mask = <0x60>; +- status = "disabled"; +- }; +- +- snvs_pwrkey: snvs-powerkey { +- compatible = "fsl,sec-v4.0-pwrkey"; +- regmap = <&snvs>; +- interrupts = ; +- linux,keycode = ; +- wakeup-source; +- status = "disabled"; +- }; +- }; +- +- epit1: epit@20d0000 { +- reg = <0x020d0000 0x4000>; +- interrupts = ; +- }; +- +- epit2: epit@20d4000 { +- reg = <0x020d4000 0x4000>; +- interrupts = ; +- }; +- +- src: reset-controller@20d8000 { +- compatible = "fsl,imx6sx-src", "fsl,imx51-src"; +- reg = <0x020d8000 0x4000>; +- interrupts = , +- ; +- #reset-cells = <1>; +- }; +- +- gpc: gpc@20dc000 { +- compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; +- reg = <0x020dc000 0x4000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = ; +- interrupt-parent = <&intc>; +- clocks = <&clks IMX6SX_CLK_IPG>; +- clock-names = "ipg"; +- +- pgc { +- #address-cells = <1>; +- #size-cells = <0>; +- +- power-domain@0 { +- reg = <0>; +- #power-domain-cells = <0>; +- }; +- +- pd_pu: power-domain@1 { +- reg = <1>; +- #power-domain-cells = <0>; +- power-supply = <®_soc>; +- clocks = <&clks IMX6SX_CLK_GPU>; +- }; +- +- pd_disp: power-domain@2 { +- reg = <2>; +- #power-domain-cells = <0>; +- clocks = <&clks IMX6SX_CLK_PXP_AXI>, +- <&clks IMX6SX_CLK_DISPLAY_AXI>, +- <&clks IMX6SX_CLK_LCDIF1_PIX>, +- <&clks IMX6SX_CLK_LCDIF_APB>, +- <&clks IMX6SX_CLK_LCDIF2_PIX>, +- <&clks IMX6SX_CLK_CSI>, +- <&clks IMX6SX_CLK_VADC>; +- }; +- +- pd_pci: power-domain@3 { +- reg = <3>; +- #power-domain-cells = <0>; +- power-supply = <®_pcie>; +- }; +- }; +- }; +- +- iomuxc: pinctrl@20e0000 { +- compatible = "fsl,imx6sx-iomuxc"; +- reg = <0x020e0000 0x4000>; +- }; +- +- gpr: iomuxc-gpr@20e4000 { +- compatible = "fsl,imx6sx-iomuxc-gpr", +- "fsl,imx6q-iomuxc-gpr", "syscon"; +- reg = <0x020e4000 0x4000>; +- }; +- +- sdma: sdma@20ec000 { +- compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; +- reg = <0x020ec000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_IPG>, +- <&clks IMX6SX_CLK_SDMA>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- /* imx6sx reuses imx6q sdma firmware */ +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; +- }; +- }; +- +- aips2: bus@2100000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x02100000 0x100000>; +- ranges; +- +- crypto: crypto@2100000 { +- compatible = "fsl,sec-v4.0"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x2100000 0x10000>; +- ranges = <0 0x2100000 0x10000>; +- interrupt-parent = <&intc>; +- clocks = <&clks IMX6SX_CLK_CAAM_MEM>, +- <&clks IMX6SX_CLK_CAAM_ACLK>, +- <&clks IMX6SX_CLK_CAAM_IPG>, +- <&clks IMX6SX_CLK_EIM_SLOW>; +- clock-names = "mem", "aclk", "ipg", "emi_slow"; +- +- sec_jr0: jr@1000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x1000 0x1000>; +- interrupts = ; +- }; +- +- sec_jr1: jr@2000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x2000 0x1000>; +- interrupts = ; +- }; +- }; +- +- usbotg1: usb@2184000 { +- compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; +- reg = <0x02184000 0x200>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_USBOH3>; +- fsl,usbphy = <&usbphy1>; +- fsl,usbmisc = <&usbmisc 0>; +- fsl,anatop = <&anatop>; +- ahb-burst-config = <0x0>; +- tx-burst-size-dword = <0x10>; +- rx-burst-size-dword = <0x10>; +- status = "disabled"; +- }; +- +- usbotg2: usb@2184200 { +- compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; +- reg = <0x02184200 0x200>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_USBOH3>; +- fsl,usbphy = <&usbphy2>; +- fsl,usbmisc = <&usbmisc 1>; +- ahb-burst-config = <0x0>; +- tx-burst-size-dword = <0x10>; +- rx-burst-size-dword = <0x10>; +- status = "disabled"; +- }; +- +- usbh: usb@2184400 { +- compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; +- reg = <0x02184400 0x200>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_USBOH3>; +- fsl,usbphy = <&usbphynop1>; +- fsl,usbmisc = <&usbmisc 2>; +- phy_type = "hsic"; +- fsl,anatop = <&anatop>; +- dr_mode = "host"; +- ahb-burst-config = <0x0>; +- tx-burst-size-dword = <0x10>; +- rx-burst-size-dword = <0x10>; +- status = "disabled"; +- }; +- +- usbmisc: usbmisc@2184800 { +- #index-cells = <1>; +- compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc"; +- reg = <0x02184800 0x200>; +- clocks = <&clks IMX6SX_CLK_USBOH3>; +- }; +- +- fec1: ethernet@2188000 { +- compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; +- reg = <0x02188000 0x4000>; +- interrupt-names = "int0", "pps"; +- interrupts = , +- ; +- clocks = <&clks IMX6SX_CLK_ENET>, +- <&clks IMX6SX_CLK_ENET_AHB>, +- <&clks IMX6SX_CLK_ENET_PTP>, +- <&clks IMX6SX_CLK_ENET_REF>, +- <&clks IMX6SX_CLK_ENET_PTP>; +- clock-names = "ipg", "ahb", "ptp", +- "enet_clk_ref", "enet_out"; +- fsl,num-tx-queues = <3>; +- fsl,num-rx-queues = <3>; +- fsl,stop-mode = <&gpr 0x10 3>; +- status = "disabled"; +- }; +- +- mlb: mlb@218c000 { +- reg = <0x0218c000 0x4000>; +- interrupts = , +- , +- ; +- clocks = <&clks IMX6SX_CLK_MLB>; +- status = "disabled"; +- }; +- +- usdhc1: mmc@2190000 { +- compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; +- reg = <0x02190000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_USDHC1>, +- <&clks IMX6SX_CLK_USDHC1>, +- <&clks IMX6SX_CLK_USDHC1>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usdhc2: mmc@2194000 { +- compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; +- reg = <0x02194000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_USDHC2>, +- <&clks IMX6SX_CLK_USDHC2>, +- <&clks IMX6SX_CLK_USDHC2>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usdhc3: mmc@2198000 { +- compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; +- reg = <0x02198000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_USDHC3>, +- <&clks IMX6SX_CLK_USDHC3>, +- <&clks IMX6SX_CLK_USDHC3>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usdhc4: mmc@219c000 { +- compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; +- reg = <0x0219c000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_USDHC4>, +- <&clks IMX6SX_CLK_USDHC4>, +- <&clks IMX6SX_CLK_USDHC4>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- i2c1: i2c@21a0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; +- reg = <0x021a0000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_I2C1>; +- status = "disabled"; +- }; +- +- i2c2: i2c@21a4000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; +- reg = <0x021a4000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_I2C2>; +- status = "disabled"; +- }; +- +- i2c3: i2c@21a8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; +- reg = <0x021a8000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_I2C3>; +- status = "disabled"; +- }; +- +- memory-controller@21b0000 { +- compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; +- reg = <0x021b0000 0x4000>; +- clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>; +- }; +- +- fec2: ethernet@21b4000 { +- compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; +- reg = <0x021b4000 0x4000>; +- interrupt-names = "int0", "pps"; +- interrupts = , +- ; +- clocks = <&clks IMX6SX_CLK_ENET>, +- <&clks IMX6SX_CLK_ENET_AHB>, +- <&clks IMX6SX_CLK_ENET_PTP>, +- <&clks IMX6SX_CLK_ENET2_REF_125M>, +- <&clks IMX6SX_CLK_ENET_PTP>; +- clock-names = "ipg", "ahb", "ptp", +- "enet_clk_ref", "enet_out"; +- fsl,stop-mode = <&gpr 0x10 4>; +- status = "disabled"; +- }; +- +- weim: weim@21b8000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; +- reg = <0x021b8000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_EIM_SLOW>; +- fsl,weim-cs-gpr = <&gpr>; +- status = "disabled"; +- }; +- +- ocotp: efuse@21bc000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,imx6sx-ocotp", "syscon"; +- reg = <0x021bc000 0x4000>; +- clocks = <&clks IMX6SX_CLK_OCOTP>; +- +- cpu_speed_grade: speed-grade@10 { +- reg = <0x10 4>; +- }; +- +- tempmon_calib: calib@38 { +- reg = <0x38 4>; +- }; +- +- tempmon_temp_grade: temp-grade@20 { +- reg = <0x20 4>; +- }; +- }; +- +- sai1: sai@21d4000 { +- compatible = "fsl,imx6sx-sai"; +- reg = <0x021d4000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_SAI1_IPG>, +- <&clks IMX6SX_CLK_SAI1>, +- <&clks 0>, <&clks 0>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dma-names = "rx", "tx"; +- dmas = <&sdma 31 24 0>, <&sdma 32 24 0>; +- status = "disabled"; +- }; +- +- audmux: audmux@21d8000 { +- compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; +- reg = <0x021d8000 0x4000>; +- status = "disabled"; +- }; +- +- sai2: sai@21dc000 { +- compatible = "fsl,imx6sx-sai"; +- reg = <0x021dc000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_SAI2_IPG>, +- <&clks IMX6SX_CLK_SAI2>, +- <&clks 0>, <&clks 0>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dma-names = "rx", "tx"; +- dmas = <&sdma 33 24 0>, <&sdma 34 24 0>; +- status = "disabled"; +- }; +- +- qspi1: spi@21e0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sx-qspi"; +- reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; +- reg-names = "QuadSPI", "QuadSPI-memory"; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_QSPI1>, +- <&clks IMX6SX_CLK_QSPI1>; +- clock-names = "qspi_en", "qspi"; +- status = "disabled"; +- }; +- +- qspi2: spi@21e4000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sx-qspi"; +- reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>; +- reg-names = "QuadSPI", "QuadSPI-memory"; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_QSPI2>, +- <&clks IMX6SX_CLK_QSPI2>; +- clock-names = "qspi_en", "qspi"; +- status = "disabled"; +- }; +- +- uart2: serial@21e8000 { +- compatible = "fsl,imx6sx-uart", +- "fsl,imx6q-uart", "fsl,imx21-uart"; +- reg = <0x021e8000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_UART_IPG>, +- <&clks IMX6SX_CLK_UART_SERIAL>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart3: serial@21ec000 { +- compatible = "fsl,imx6sx-uart", +- "fsl,imx6q-uart", "fsl,imx21-uart"; +- reg = <0x021ec000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_UART_IPG>, +- <&clks IMX6SX_CLK_UART_SERIAL>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart4: serial@21f0000 { +- compatible = "fsl,imx6sx-uart", +- "fsl,imx6q-uart", "fsl,imx21-uart"; +- reg = <0x021f0000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_UART_IPG>, +- <&clks IMX6SX_CLK_UART_SERIAL>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart5: serial@21f4000 { +- compatible = "fsl,imx6sx-uart", +- "fsl,imx6q-uart", "fsl,imx21-uart"; +- reg = <0x021f4000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_UART_IPG>, +- <&clks IMX6SX_CLK_UART_SERIAL>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c4: i2c@21f8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; +- reg = <0x021f8000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_I2C4>; +- status = "disabled"; +- }; +- }; +- +- aips3: bus@2200000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x02200000 0x100000>; +- ranges; +- +- spba-bus@2240000 { +- compatible = "fsl,spba-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x02240000 0x40000>; +- ranges; +- +- csi1: csi@2214000 { +- reg = <0x02214000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, +- <&clks IMX6SX_CLK_CSI>, +- <&clks IMX6SX_CLK_DCIC1>; +- clock-names = "disp-axi", "csi_mclk", "dcic"; +- status = "disabled"; +- }; +- +- pxp: pxp@2218000 { +- compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp"; +- reg = <0x02218000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_PXP_AXI>; +- clock-names = "axi"; +- power-domains = <&pd_disp>; +- status = "disabled"; +- }; +- +- csi2: csi@221c000 { +- reg = <0x0221c000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, +- <&clks IMX6SX_CLK_CSI>, +- <&clks IMX6SX_CLK_DCIC2>; +- clock-names = "disp-axi", "csi_mclk", "dcic"; +- status = "disabled"; +- }; +- +- lcdif1: lcdif@2220000 { +- compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; +- reg = <0x02220000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, +- <&clks IMX6SX_CLK_LCDIF_APB>, +- <&clks IMX6SX_CLK_DISPLAY_AXI>; +- clock-names = "pix", "axi", "disp_axi"; +- power-domains = <&pd_disp>; +- status = "disabled"; +- }; +- +- lcdif2: lcdif@2224000 { +- compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; +- reg = <0x02224000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, +- <&clks IMX6SX_CLK_LCDIF_APB>, +- <&clks IMX6SX_CLK_DISPLAY_AXI>; +- clock-names = "pix", "axi", "disp_axi"; +- power-domains = <&pd_disp>; +- status = "disabled"; +- }; +- +- vadc: vadc@2228000 { +- reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; +- reg-names = "vadc-vafe", "vadc-vdec"; +- clocks = <&clks IMX6SX_CLK_VADC>, +- <&clks IMX6SX_CLK_CSI>; +- clock-names = "vadc", "csi"; +- power-domains = <&pd_disp>; +- status = "disabled"; +- }; +- }; +- +- adc1: adc@2280000 { +- compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; +- reg = <0x02280000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_IPG>; +- clock-names = "adc"; +- fsl,adck-max-frequency = <30000000>, <40000000>, +- <20000000>; +- status = "disabled"; +- }; +- +- adc2: adc@2284000 { +- compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; +- reg = <0x02284000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_IPG>; +- clock-names = "adc"; +- fsl,adck-max-frequency = <30000000>, <40000000>, +- <20000000>; +- status = "disabled"; +- }; +- +- wdog3: watchdog@2288000 { +- compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; +- reg = <0x02288000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_IPG>; +- status = "disabled"; +- }; +- +- ecspi5: spi@228c000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; +- reg = <0x0228c000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_ECSPI5>, +- <&clks IMX6SX_CLK_ECSPI5>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart6: serial@22a0000 { +- compatible = "fsl,imx6sx-uart", +- "fsl,imx6q-uart", "fsl,imx21-uart"; +- reg = <0x022a0000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_UART_IPG>, +- <&clks IMX6SX_CLK_UART_SERIAL>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- pwm5: pwm@22a4000 { +- compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; +- reg = <0x022a4000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_PWM5>, +- <&clks IMX6SX_CLK_PWM5>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- }; +- +- pwm6: pwm@22a8000 { +- compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; +- reg = <0x022a8000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_PWM6>, +- <&clks IMX6SX_CLK_PWM6>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- }; +- +- pwm7: pwm@22ac000 { +- compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; +- reg = <0x022ac000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_PWM7>, +- <&clks IMX6SX_CLK_PWM7>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- }; +- +- pwm8: pwm@22b0000 { +- compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; +- reg = <0x0022b0000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6SX_CLK_PWM8>, +- <&clks IMX6SX_CLK_PWM8>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- }; +- }; +- +- pcie: pcie@8ffc000 { +- compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; +- reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>; +- reg-names = "dbi", "config"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- bus-range = <0x00 0xff>; +- ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */ +- 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */ +- num-lanes = <1>; +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX6SX_CLK_PCIE_AXI>, +- <&clks IMX6SX_CLK_LVDS1_OUT>, +- <&clks IMX6SX_CLK_PCIE_REF_125M>, +- <&clks IMX6SX_CLK_DISPLAY_AXI>; +- clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; +- power-domains = <&pd_disp>, <&pd_pci>; +- power-domain-names = "pcie", "pcie_phy"; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-14x14-evk.dts b/scripts/dtc/include-prefixes/arm/imx6ul-14x14-evk.dts +deleted file mode 100644 +index 2438669f149a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-14x14-evk.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright (C) 2015 Freescale Semiconductor, Inc. +- +-/dts-v1/; +- +-#include "imx6ul.dtsi" +-#include "imx6ul-14x14-evk.dtsi" +- +-/ { +- model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; +- compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-14x14-evk.dtsi b/scripts/dtc/include-prefixes/arm/imx6ul-14x14-evk.dtsi +deleted file mode 100644 +index a3fde3316c73..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-14x14-evk.dtsi ++++ /dev/null +@@ -1,649 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright (C) 2015 Freescale Semiconductor, Inc. +- +-/ { +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +- +- backlight_display: backlight-display { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- status = "okay"; +- }; +- +- +- reg_sd1_vmmc: regulator-sd1-vmmc { +- compatible = "regulator-fixed"; +- regulator-name = "VSD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_peri_3v3: regulator-peri-3v3 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_peri_3v3>; +- regulator-name = "VPERI_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; +- /* +- * If you want to want to make this dynamic please +- * check schematics and test all affected peripherals: +- * +- * - sensors +- * - ethernet phy +- * - can +- * - bluetooth +- * - wm8960 audio codec +- * - ov5640 camera +- */ +- regulator-always-on; +- }; +- +- reg_can_3v3: regulator-can-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "can-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; +- }; +- +- sound-wm8960 { +- compatible = "fsl,imx-audio-wm8960"; +- model = "wm8960-audio"; +- audio-cpu = <&sai2>; +- audio-codec = <&codec>; +- audio-asrc = <&asrc>; +- hp-det-gpio = <&gpio5 4 0>; +- audio-routing = +- "Headphone Jack", "HP_L", +- "Headphone Jack", "HP_R", +- "Ext Spk", "SPK_LP", +- "Ext Spk", "SPK_LN", +- "Ext Spk", "SPK_RP", +- "Ext Spk", "SPK_RN", +- "LINPUT2", "Mic Jack", +- "LINPUT3", "Mic Jack", +- "RINPUT1", "AMIC", +- "RINPUT2", "AMIC", +- "Mic Jack", "MICB", +- "AMIC", "MICB"; +- }; +- +- spi4 { +- compatible = "spi-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi4>; +- status = "okay"; +- gpio-sck = <&gpio5 11 0>; +- gpio-mosi = <&gpio5 10 0>; +- cs-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; +- num-chipselects = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpio_spi: gpio@0 { +- compatible = "fairchild,74hc595"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0>; +- registers-number = <1>; +- spi-max-frequency = <100000>; +- enable-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- panel { +- compatible = "innolux,at043tn24"; +- backlight = <&backlight_display>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; +- assigned-clock-rates = <786432000>; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- codec: wm8960@1a { +- #sound-dai-cells = <0>; +- compatible = "wlf,wm8960"; +- reg = <0x1a>; +- wlf,shared-lrclk; +- wlf,hp-cfg = <3 2 3>; +- wlf,gpio-cfg = <1 3>; +- clocks = <&clks IMX6UL_CLK_SAI2>; +- clock-names = "mclk"; +- }; +- +- camera@3c { +- compatible = "ovti,ov5640"; +- reg = <0x3c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_camera_clock>; +- clocks = <&clks IMX6UL_CLK_CSI>; +- clock-names = "xclk"; +- powerdown-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>; +- +- port { +- ov5640_to_parallel: endpoint { +- remote-endpoint = <¶llel_from_ov5640>; +- bus-width = <8>; +- data-shift = <2>; /* lines 9:2 are used */ +- hsync-active = <0>; +- vsync-active = <0>; +- pclk-sample = <1>; +- }; +- }; +- }; +-}; +- +-&csi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_csi1>; +- status = "okay"; +- +- port { +- parallel_from_ov5640: endpoint { +- remote-endpoint = <&ov5640_to_parallel>; +- bus-type = <5>; /* Parallel bus */ +- }; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- phy-mode = "rmii"; +- phy-handle = <ðphy0>; +- phy-supply = <®_peri_3v3>; +- status = "okay"; +-}; +- +-&fec2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet2>; +- phy-mode = "rmii"; +- phy-handle = <ðphy1>; +- phy-supply = <®_peri_3v3>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@2 { +- compatible = "ethernet-phy-id0022.1560"; +- reg = <2>; +- micrel,led-mode = <1>; +- clocks = <&clks IMX6UL_CLK_ENET_REF>; +- clock-names = "rmii-ref"; +- +- }; +- +- ethphy1: ethernet-phy@1 { +- compatible = "ethernet-phy-id0022.1560"; +- reg = <1>; +- micrel,led-mode = <1>; +- clocks = <&clks IMX6UL_CLK_ENET2_REF>; +- clock-names = "rmii-ref"; +- }; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- xceiver-supply = <®_can_3v3>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- xceiver-supply = <®_can_3v3>; +- status = "okay"; +-}; +- +-&gpio_spi { +- eth0-phy-hog { +- gpio-hog; +- gpios = <1 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "eth0-phy"; +- }; +- +- eth1-phy-hog { +- gpio-hog; +- gpios = <2 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "eth1-phy"; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- magnetometer@e { +- compatible = "fsl,mag3110"; +- reg = <0x0e>; +- vdd-supply = <®_peri_3v3>; +- vddio-supply = <®_peri_3v3>; +- }; +-}; +- +-&lcdif { +- assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; +- assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcdif_dat +- &pinctrl_lcdif_ctrl>; +- status = "okay"; +- +- port { +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +-}; +- +-&pwm1 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&qspi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_qspi>; +- status = "okay"; +- +- flash0: n25q256a@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q256a", "jedec,spi-nor"; +- spi-max-frequency = <29000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <1>; +- reg = <0>; +- }; +-}; +- +-&sai2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai2>; +- assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, +- <&clks IMX6UL_CLK_SAI2>; +- assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; +- assigned-clock-rates = <0>, <12288000>; +- fsl,sai-mclk-direction-output; +- status = "okay"; +-}; +- +-&snvs_poweroff { +- status = "okay"; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +- +-&tsc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tsc>; +- xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; +- measure-delay-time = <0xffff>; +- pre-charge-time = <0xfff>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbotg1 { +- dr_mode = "otg"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_otg1>; +- status = "okay"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbphy1 { +- fsl,tx-d-cal = <106>; +-}; +- +-&usbphy2 { +- fsl,tx-d-cal = <106>; +-}; +- +-&usdhc1 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; +- keep-power-in-suspend; +- wakeup-source; +- vmmc-supply = <®_sd1_vmmc>; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- no-1-8-v; +- broken-cd; +- keep-power-in-suspend; +- wakeup-source; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- +- pinctrl_camera_clock: cameraclockgrp { +- fsl,pins = < +- MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 +- >; +- }; +- +- pinctrl_csi1: csi1grp { +- fsl,pins = < +- MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 +- MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 +- MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 +- MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 +- MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 +- MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 +- MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 +- MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 +- MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 +- MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 +- MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 +- >; +- }; +- +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 +- >; +- }; +- +- pinctrl_enet2: enet2grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 +- MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 +- MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 +- MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 +- MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 +- MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 +- MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 +- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 +- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 +- MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp{ +- fsl,pins = < +- MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 +- MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp{ +- fsl,pins = < +- MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 +- MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 +- MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 +- MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 +- >; +- }; +- +- pinctrl_lcdif_dat: lcdifdatgrp { +- fsl,pins = < +- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 +- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 +- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 +- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 +- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 +- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 +- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 +- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 +- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 +- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 +- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 +- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 +- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 +- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 +- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 +- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 +- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 +- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 +- MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 +- MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 +- MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 +- MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 +- MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 +- MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 +- >; +- }; +- +- pinctrl_lcdif_ctrl: lcdifctrlgrp { +- fsl,pins = < +- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 +- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 +- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 +- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 +- /* used for lcd reset */ +- MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 +- >; +- }; +- +- pinctrl_qspi: qspigrp { +- fsl,pins = < +- MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 +- MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 +- MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 +- MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 +- MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 +- MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 +- >; +- }; +- +- pinctrl_sai2: sai2grp { +- fsl,pins = < +- MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 +- MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 +- MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 +- MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 +- MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 +- MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 +- >; +- }; +- +- pinctrl_peri_3v3: peri3v3grp { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 +- >; +- }; +- +- pinctrl_sim2: sim2grp { +- fsl,pins = < +- MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 +- MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 +- MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 +- MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 +- MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 +- MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 +- >; +- }; +- +- pinctrl_spi4: spi4grp { +- fsl,pins = < +- MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 +- MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 +- MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 +- MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 +- >; +- }; +- +- pinctrl_tsc: tscgrp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 +- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 +- MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 +- MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 +- MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 +- MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 +- >; +- }; +- +- pinctrl_usb_otg1: usbotg1grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 +- MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ +- MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ +- MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1grp100mhz { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 +- +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1grp200mhz { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 +- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 +- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 +- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 +- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 +- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-ccimx6ulsbcexpress.dts b/scripts/dtc/include-prefixes/arm/imx6ul-ccimx6ulsbcexpress.dts +deleted file mode 100644 +index 3792679c0c90..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-ccimx6ulsbcexpress.dts ++++ /dev/null +@@ -1,200 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Digi International's ConnectCore6UL SBC Express board device tree source +- * +- * Copyright 2018 Digi International, Inc. +- * +- */ +- +-/dts-v1/; +-#include +-#include +-#include "imx6ul.dtsi" +-#include "imx6ul-ccimx6ulsom.dtsi" +- +-/ { +- model = "Digi International ConnectCore 6UL SBC Express."; +- compatible = "digi,ccimx6ulsbcexpress", "digi,ccimx6ulsom", +- "fsl,imx6ul"; +-}; +- +-&adc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc1>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- xceiver-supply = <&ext_3v3>; +- status = "okay"; +-}; +- +-&ecspi3 { +- cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi3_master>; +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- phy-mode = "rmii"; +- phy-handle = <ðphy0>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- smsc,disable-energy-detect; +- reg = <0>; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbotg1 { +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- broken-cd; /* no carrier detect line (use polling) */ +- no-1-8-v; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_adc1: adc1grp { +- fsl,pins = < +- /* GPIO1_4/ADC1_IN4 (pin 7 of the expansion header) */ +- MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 +- >; +- }; +- +- pinctrl_ecspi3_master: ecspi3grp1 { +- fsl,pins = < +- MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 +- MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 +- MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 +- MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 /* Chip Select */ +- >; +- }; +- +- pinctrl_ecspi3_slave: ecspi3grp2 { +- fsl,pins = < +- MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 +- MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 +- MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 +- MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x10b0 /* Chip Select */ +- >; +- }; +- +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 +- MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 +- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp{ +- fsl,pins = < +- MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 +- MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0 +- MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x10b0 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1 +- MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 +- MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10071 +- MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 +- MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 +- MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 +- MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 +- >; +- }; +- +- /* General purpose pinctrl */ +- pinctrl_hog: hoggrp { +- fsl,pins = < +- /* GPIOs BANK 3 */ +- MX6UL_PAD_LCD_RESET__GPIO3_IO04 0xf030 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-ccimx6ulsbcpro.dts b/scripts/dtc/include-prefixes/arm/imx6ul-ccimx6ulsbcpro.dts +deleted file mode 100644 +index 3ec042bfccba..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-ccimx6ulsbcpro.dts ++++ /dev/null +@@ -1,428 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Digi International's ConnectCore6UL SBC Pro board device tree source +- * +- * Copyright 2018 Digi International, Inc. +- * +- */ +- +-/dts-v1/; +-#include +-#include +-#include "imx6ul.dtsi" +-#include "imx6ul-ccimx6ulsom.dtsi" +- +-/ { +- model = "Digi International ConnectCore 6UL SBC Pro."; +- compatible = "digi,ccimx6ulsbcpro", "digi,ccimx6ulsom", "fsl,imx6ul"; +- +- lcd_backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm5 0 50000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- status = "okay"; +- }; +- +- panel { +- compatible = "auo,g101evn010"; +- power-supply = <&ldo4_ext>; +- backlight = <&lcd_backlight>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +- +- reg_usb_otg1_vbus: regulator-usb-otg1 { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&adc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc1>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- xceiver-supply = <&ext_3v3>; +- status = "okay"; +-}; +- +-/* CAN2 is multiplexed with UART2 RTS/CTS */ +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- xceiver-supply = <&ext_3v3>; +- status = "disabled"; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1_master>; +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- phy-mode = "rmii"; +- phy-handle = <ðphy0>; +- status = "okay"; +-}; +- +-&fec2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; +- phy-mode = "rmii"; +- phy-handle = <ðphy1>; +- phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <26>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- smsc,disable-energy-detect; +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- smsc,disable-energy-detect; +- reg = <1>; +- }; +- }; +-}; +- +-&gpio5 { +- emmc-usd-mux-hog { +- gpio-hog; +- gpios = <1 GPIO_ACTIVE_LOW>; +- output-high; +- }; +-}; +- +-&i2c1 { +- touchscreen@14 { +- compatible = "goodix,gt911"; +- reg = <0x14>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_goodix_touch>; +- interrupt-parent = <&gpio5>; +- interrupts = <2 IRQ_TYPE_EDGE_RISING>; +- irq-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +-}; +- +-&lcdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcdif_dat0_17 +- &pinctrl_lcdif_clken +- &pinctrl_lcdif_hvsync>; +- lcd-supply = <&ldo4_ext>; /* BU90T82 LVDS bridge power */ +- status = "okay"; +- +- port { +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +-}; +- +-&ldo4_ext { +- regulator-max-microvolt = <1800000>; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&pwm3 { +- status = "okay"; +-}; +- +-&pwm4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +- status = "okay"; +-}; +- +-&pwm5 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm5>; +- status = "okay"; +-}; +- +-&pwm6 { +- status = "okay"; +-}; +- +-&pwm7 { +- status = "okay"; +-}; +- +-&pwm8 { +- status = "okay"; +-}; +- +-&sai2 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&pinctrl_sai2>; +- pinctrl-1 = <&pinctrl_sai2_sleep>; +- assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, +- <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>, +- <&clks IMX6UL_CLK_SAI2>; +- assigned-clock-rates = <0>, <786432000>, <12288000>; +- assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; +- status = "okay"; +-}; +- +-/* UART2 RTS/CTS muxed with CAN2 */ +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2_4wires>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-/* UART3 RTS/CTS muxed with CAN 1 */ +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3_2wires>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&usbotg1 { +- dr_mode = "otg"; +- vbus-supply = <®_usb_otg1_vbus>; +- pinctrl-0 = <&pinctrl_usbotg1>; +- status = "okay"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-/* USDHC2 (microSD conflicts with eMMC) */ +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- no-1-8-v; +- broken-cd; /* no carrier detect line (use polling) */ +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_adc1: adc1grp { +- fsl,pins = < +- /* EXP_GPIO_2 -> GPIO1_3/ADC1_IN3 */ +- MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 +- >; +- }; +- +- pinctrl_ecspi1_master: ecspi1grp1 { +- fsl,pins = < +- MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x10b0 +- MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x10b0 +- MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x10b0 +- MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0 +- >; +- }; +- +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051 +- >; +- }; +- +- pinctrl_enet2: enet2grp { +- fsl,pins = < +- MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 +- MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 +- MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 +- MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 +- MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 +- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 +- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 +- MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x40017051 +- >; +- }; +- +- pinctrl_enet2_mdio: mdioenet2grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 +- MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp{ +- fsl,pins = < +- MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 +- MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 +- >; +- }; +- pinctrl_flexcan2: flexcan2grp{ +- fsl,pins = < +- MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 +- MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 +- >; +- }; +- +- pinctrl_goodix_touch: goodixgrp{ +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1020 +- >; +- }; +- +- pinctrl_lcdif_dat0_17: lcdifdatgrp0-17 { +- fsl,pins = < +- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 +- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 +- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 +- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 +- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 +- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 +- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 +- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 +- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 +- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 +- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 +- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 +- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 +- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 +- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 +- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 +- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 +- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 +- >; +- }; +- +- pinctrl_lcdif_clken: lcdifctrlgrp1 { +- fsl,pins = < +- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x17050 +- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 +- >; +- }; +- +- pinctrl_lcdif_hvsync: lcdifctrlgrp2 { +- fsl,pins = < +- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 +- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 +- >; +- }; +- +- pinctrl_pwm5: pwm5grp { +- fsl,pins = < +- MX6UL_PAD_NAND_DQS__PWM5_OUT 0x110b0 +- >; +- }; +- +- pinctrl_sai2: sai2grp { +- fsl,pins = < +- MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 +- MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 +- MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 +- MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 +- MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 +- /* Interrupt */ +- MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10b0 +- >; +- }; +- +- pinctrl_sai2_sleep: sai2grp-sleep { +- fsl,pins = < +- MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x3000 +- MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x3000 +- MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x3000 +- MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x3000 +- /* Interrupt */ +- MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x3000 +- >; +- }; +- +- pinctrl_uart2_4wires: uart2grp-4wires { +- fsl,pins = < +- MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 +- MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 +- MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3_2wires: uart3grp-2wires { +- fsl,pins = < +- MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 +- MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10039 +- MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 +- MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 +- MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 +- MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 +- /* Mux selector between eMMC/SD# */ +- MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x79 +- >; +- }; +- +- pinctrl_usbotg1: usbotg1grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 +- MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x17059 +- MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x17059 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-ccimx6ulsom.dtsi b/scripts/dtc/include-prefixes/arm/imx6ul-ccimx6ulsom.dtsi +deleted file mode 100644 +index b5781c3656d1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-ccimx6ulsom.dtsi ++++ /dev/null +@@ -1,270 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Digi International's ConnectCore 6UL System-On-Module device tree source +- * +- * Copyright 2018 Digi International, Inc. +- * +- */ +- +-/ { +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0>; /* will be filled by U-Boot */ +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- linux,cma { +- compatible = "shared-dma-pool"; +- reusable; +- size = <0x4000000>; +- linux,cma-default; +- }; +- }; +-}; +- +-&adc1 { +- vref-supply = <&vdda_adc_3v3>; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pfuze3000: pmic@8 { +- compatible = "fsl,pfuze3000"; +- reg = <0x08>; +- +- regulators { +- int_3v3: sw1a { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <3300000>; +- regulator-ramp-delay = <6250>; +- regulator-boot-on; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_arm_soc_in: sw1b { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1475000>; +- regulator-ramp-delay = <6250>; +- regulator-boot-on; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <925000>; +- }; +- }; +- +- ext_3v3: sw2 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <3300000>; +- regulator-ramp-delay = <6250>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr3: sw3 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1650000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1300000>; +- }; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- vdd_snvs_3v3: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vrefddr: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdda_adc_3v3: vldo1 { +- compatible = "regulator-fixed"; +- regulator-name = "vref-adc-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo2_ext: vldo2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vdda_wlan: vccsd { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_high_in: v33 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo3_int: vldo3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo4_ext: vldo4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vcoin_chg: vcoin { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +- }; +-}; +- +-/* UART1 (Bluetooth) */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-/* USDHC1 (Wireless) */ +-&usdhc1 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_wifibt_ctrl>; +- pinctrl-1 = <&pinctrl_usdhc1_sleep &pinctrl_wifibt_ctrl_sleep>; +- non-removable; +- no-1-8-v; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_gpmi_nand: gpmigrp { +- fsl,pins = < +- MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 +- MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 +- MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 +- MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 +- MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 +- MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 +- MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 +- MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 +- MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 +- MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 +- MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 +- MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 +- MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 +- MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 +- MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb0b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 +- MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 +- MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x1b0b1 +- MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17051 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc1_sleep: usdhc1grp-sleep { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x3000 +- MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x3000 +- MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x3000 +- MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x3000 +- MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x3000 +- MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x3000 +- >; +- }; +- +- pinctrl_wifibt_ctrl: wifibt-ctrl-grp { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x08a0 +- MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x08a0 +- >; +- }; +- +- pinctrl_wifibt_ctrl_sleep: wifibt-ctrl-grp-sleep { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x3000 +- MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3000 +- >; +- }; +-}; +- +-®_arm { +- vin-supply = <&vdd_arm_soc_in>; +- regulator-allow-bypass; +-}; +- +-®_soc { +- vin-supply = <&vdd_arm_soc_in>; +- regulator-allow-bypass; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-geam.dts b/scripts/dtc/include-prefixes/arm/imx6ul-geam.dts +deleted file mode 100644 +index a0097da03f38..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-geam.dts ++++ /dev/null +@@ -1,447 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright (C) 2016 Amarula Solutions B.V. +- * Copyright (C) 2016 Engicam S.r.l. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "imx6ul.dtsi" +- +-/ { +- model = "Engicam GEAM6UL Starter Kit"; +- compatible = "engicam,imx6ul-geam", "fsl,imx6ul"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x08000000>; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm8 0 100000>; +- brightness-levels = < 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100>; +- default-brightness-level = <100>; +- }; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "imx6ul-geam-sgtl5000"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&dailink_master>; +- simple-audio-card,frame-master = <&dailink_master>; +- simple-audio-card,widgets = +- "Microphone", "Mic Jack", +- "Line", "Line In", +- "Line", "Line Out", +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- +- simple-audio-card,cpu { +- sound-dai = <&sai2>; +- }; +- +- dailink_master: simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- clocks = <&clks IMX6UL_CLK_SAI2>; +- }; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- xceiver-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- xceiver-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- phy-mode = "rmii"; +- phy-handle = <ðphy0>; +- status = "okay"; +-}; +- +-&fec2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet2>; +- phy-mode = "rmii"; +- phy-handle = <ðphy1>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +- }; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- nand-on-flash-bbt; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- clocks = <&clks IMX6UL_CLK_OSC>; +- clock-names = "mclk"; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; +- VDDD-supply = <®_1p8v>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&lcdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcdif_dat +- &pinctrl_lcdif_ctrl>; +- display = <&display0>; +- status = "okay"; +- +- display0: display0 { +- bits-per-pixel = <16>; +- bus-width = <18>; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing0 { +- clock-frequency = <28000000>; +- hactive = <800>; +- vactive = <480>; +- hfront-porch = <30>; +- hback-porch = <30>; +- hsync-len = <64>; +- vback-porch = <5>; +- vfront-porch = <5>; +- vsync-len = <20>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- }; +- }; +-}; +- +-&pwm8 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm8>; +- status = "okay"; +-}; +- +-&tsc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tsc>; +- xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; +-}; +- +-&sai2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai2>; +- status = "okay"; +-}; +- +-&tsc { +- measure-delay-time = <0x1ffff>; +- pre-charge-time = <0x1fff>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usbotg1 { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- bus-width = <4>; +- cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 +- >; +- }; +- +- pinctrl_enet2: enet2grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 +- MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 +- MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 +- MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */ +- MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 +- MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 +- MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 +- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 +- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 +- MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 +- MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 +- MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 +- MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 +- MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 +- MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 +- MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 +- MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 +- MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 +- MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 +- MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 +- MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 +- MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 +- MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 +- MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 +- MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 +- MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 +- MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 +- MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 +- >; +- }; +- +- pinctrl_lcdif_ctrl: lcdifctrlgrp { +- fsl,pins = < +- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 +- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 +- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 +- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 +- >; +- }; +- +- pinctrl_lcdif_dat: lcdifdatgrp { +- fsl,pins = < +- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 +- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 +- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 +- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 +- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 +- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 +- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 +- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 +- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 +- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 +- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 +- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 +- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 +- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 +- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 +- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 +- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 +- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 +- >; +- }; +- +- pinctrl_pwm8: pwm8grp { +- fsl,pins = < +- MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 +- >; +- }; +- +- pinctrl_tsc: tscgrp { +- fsl,pin = < +- MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 +- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 +- MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 +- MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 +- >; +- }; +- +- pinctrl_sai2: sai2grp { +- fsl,pins = < +- MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 +- MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031 +- MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 +- MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 +- MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 +- MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 +- MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1grp100mhz { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1grp200mhz { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070 +- MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070 +- MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070 +- MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070 +- MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070 +- MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-imx6ull-opos6ul.dtsi b/scripts/dtc/include-prefixes/arm/imx6ul-imx6ull-opos6ul.dtsi +deleted file mode 100644 +index f2386dcb9ff2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-imx6ull-opos6ul.dtsi ++++ /dev/null +@@ -1,148 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-// +-// Copyright 2019 Armadeus Systems +- +-/ { +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0>; /* will be filled by U-Boot */ +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- usdhc3_pwrseq: usdhc3-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- phy-mode = "rmii"; +- phy-reset-duration = <1>; +- phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; +- phy-handle = <ðphy1>; +- phy-supply = <®_3v3>; +- status = "okay"; +- +- mdio: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy1: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- interrupt-parent = <&gpio4>; +- interrupts = <16 IRQ_TYPE_LEVEL_LOW>; +- status = "okay"; +- }; +- }; +-}; +- +-/* Bluetooth */ +-&uart8 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart8>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-/* eMMC */ +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- status = "okay"; +-}; +- +-/* WiFi */ +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- no-1-8-v; +- non-removable; +- mmc-pwrseq = <&usdhc3_pwrseq>; +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- brcmf: wifi@1 { +- compatible = "brcm,bcm4329-fmac"; +- reg = <1>; +- interrupt-parent = <&gpio2>; +- interrupts = <8 IRQ_TYPE_LEVEL_LOW>; +- interrupt-names = "host-wake"; +- }; +-}; +- +-&iomuxc { +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 +- MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 +- MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0 +- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0 +- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0 +- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0 +- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 +- /* INT# */ +- MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0 +- /* RST# */ +- MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0 +- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 +- >; +- }; +- +- pinctrl_uart8: uart8grp { +- fsl,pins = < +- MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0 +- MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0 +- MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0 +- MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0 +- /* BT_REG_ON */ +- MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 +- MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 +- MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 +- MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 +- MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0 +- MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0 +- MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0 +- MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0 +- MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0 +- MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0 +- /* WL_REG_ON */ +- MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0 +- /* WL_IRQ */ +- MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-imx6ull-opos6uldev.dtsi b/scripts/dtc/include-prefixes/arm/imx6ul-imx6ull-opos6uldev.dtsi +deleted file mode 100644 +index 935a77d717a6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-imx6ull-opos6uldev.dtsi ++++ /dev/null +@@ -1,339 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-// +-// Copyright 2019 Armadeus Systems +- +-/ { +- chosen { +- stdout-path = &uart1; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm3 0 191000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- power-supply = <®_5v>; +- status = "okay"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- user-button { +- label = "User button"; +- gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- user-led { +- label = "User"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led>; +- gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- onewire { +- compatible = "w1-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_w1>; +- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; +- }; +- +- panel: panel { +- compatible = "armadeus,st0700-adapt"; +- power-supply = <®_3v3>; +- backlight = <&backlight>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lcdif_out>; +- }; +- }; +- }; +- +- reg_5v: regulator-5v { +- compatible = "regulator-fixed"; +- regulator-name = "5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usbotg1_vbus: regulator-usbotg1vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usbotg1vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg1_vbus>; +- gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usbotg2_vbus: regulator-usbotg2vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usbotg2vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg2_vbus>; +- gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&adc1 { +- vref-supply = <®_3v3>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- xceiver-supply = <®_5v>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- xceiver-supply = <®_5v>; +- status = "okay"; +-}; +- +-&ecspi4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi4>; +- cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- spidev0: spi@0 { +- compatible = "spidev"; +- reg = <0>; +- spi-max-frequency = <5000000>; +- }; +- +- spidev1: spi@1 { +- compatible = "spidev"; +- reg = <1>; +- spi-max-frequency = <5000000>; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clock-frequency = <400000>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clock-frequency = <400000>; +- status = "okay"; +-}; +- +-&lcdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcdif>; +- status = "okay"; +- +- port { +- lcdif_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +-}; +- +-&pwm3 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "okay"; +-}; +- +-&snvs_pwrkey { +- status = "disabled"; +-}; +- +-&tsc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tsc>; +- xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; +- measure-delay-time = <0xffff>; +- pre-charge-time = <0xffff>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usbotg1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg1_id>; +- vbus-supply = <®_usbotg1_vbus>; +- dr_mode = "otg"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbotg2 { +- vbus-supply = <®_usbotg2_vbus>; +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpios>; +- +- pinctrl_ecspi4: ecspi4grp { +- fsl,pins = < +- MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b0b0 +- MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b0b0 +- MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b0b0 +- MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x1b0b0 +- MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 +- MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 +- MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 +- >; +- }; +- +- pinctrl_gpios: gpiosgrp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0b0b0 +- MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x0b0b0 +- MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x0b0b0 +- MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0b0b0 +- MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x0b0b0 +- MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0b0b0 +- MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0b0b0 +- MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x0b0b0 +- >; +- }; +- +- pinctrl_gpio_keys: gpiokeysgrp { +- fsl,pins = < +- MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 +- MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 +- MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 +- >; +- }; +- +- pinctrl_lcdif: lcdifgrp { +- fsl,pins = < +- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x100b1 +- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x100b1 +- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x100b1 +- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x100b1 +- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x100b1 +- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x100b1 +- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x100b1 +- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x100b1 +- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x100b1 +- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x100b1 +- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x100b1 +- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x100b1 +- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x100b1 +- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x100b1 +- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x100b1 +- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x100b1 +- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x100b1 +- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x100b1 +- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x100b1 +- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x100b1 +- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x100b1 +- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x100b1 +- >; +- }; +- +- pinctrl_led: ledgrp { +- fsl,pins = < +- MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6UL_PAD_NAND_ALE__PWM3_OUT 0x1b0b0 +- >; +- }; +- +- pinctrl_tsc: tscgrp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 +- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 +- MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 +- MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg1_id: usbotg1idgrp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x1b0b0 +- >; +- }; +- +- pinctrl_usbotg1_vbus: usbotg1vbusgrp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-isiot-emmc.dts b/scripts/dtc/include-prefixes/arm/imx6ul-isiot-emmc.dts +deleted file mode 100644 +index 1df3e376ae2c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-isiot-emmc.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright (C) 2016 Amarula Solutions B.V. +- * Copyright (C) 2016 Engicam S.r.l. +- */ +- +-/dts-v1/; +- +-#include "imx6ul-isiot.dtsi" +- +-/ { +- model = "Engicam Is.IoT MX6UL eMMC Starter kit"; +- compatible = "engicam,imx6ul-isiot", "fsl,imx6ul"; +-}; +- +-&usdhc2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-isiot-nand.dts b/scripts/dtc/include-prefixes/arm/imx6ul-isiot-nand.dts +deleted file mode 100644 +index 8c26d4d1a7bf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-isiot-nand.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright (C) 2016 Amarula Solutions B.V. +- * Copyright (C) 2016 Engicam S.r.l. +- */ +- +-/dts-v1/; +- +-#include "imx6ul-isiot.dtsi" +- +-/ { +- model = "Engicam Is.IoT MX6UL NAND Starter kit"; +- compatible = "engicam,imx6ul-isiot", "fsl,imx6ul"; +-}; +- +-&gpmi { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-isiot.dtsi b/scripts/dtc/include-prefixes/arm/imx6ul-isiot.dtsi +deleted file mode 100644 +index 14fc4828ba4e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-isiot.dtsi ++++ /dev/null +@@ -1,387 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright (C) 2016 Amarula Solutions B.V. +- * Copyright (C) 2016 Engicam S.r.l. +- */ +- +-#include +-#include +-#include "imx6ul.dtsi" +- +-/ { +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm8 0 100000>; +- brightness-levels = < 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100>; +- default-brightness-level = <100>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "imx6ul-isiot-sgtl5000"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&dailink_master>; +- simple-audio-card,frame-master = <&dailink_master>; +- simple-audio-card,widgets = +- "Microphone", "Mic Jack", +- "Line", "Line In", +- "Line", "Line Out", +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- +- simple-audio-card,cpu { +- sound-dai = <&sai2>; +- }; +- +- dailink_master: simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- clocks = <&clks IMX6UL_CLK_SAI2>; +- }; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- phy-mode = "rmii"; +- phy-handle = <ðphy0>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +- }; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- nand-on-flash-bbt; +- status = "disabled"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- clocks = <&clks IMX6UL_CLK_OSC>; +- clock-names = "mclk"; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; +- VDDD-supply = <®_1p8v>; +- }; +- +- stmpe811: gpio-expander@44 { +- compatible = "st,stmpe811"; +- reg = <0x44>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_stmpe>; +- interrupt-parent = <&gpio1>; +- interrupts = <18 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- stmpe: touchscreen { +- compatible = "st,stmpe-ts"; +- st,sample-time = <4>; +- st,mod-12b = <1>; +- st,ref-sel = <0>; +- st,adc-freq = <1>; +- st,ave-ctrl = <1>; +- st,touch-det-delay = <2>; +- st,settling = <2>; +- st,fraction-z = <7>; +- st,i-drive = <1>; +- }; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&lcdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcdif_dat +- &pinctrl_lcdif_ctrl>; +- display = <&display0>; +- status = "okay"; +- +- display0: display0 { +- bits-per-pixel = <16>; +- bus-width = <18>; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing0 { +- clock-frequency = <28000000>; +- hactive = <800>; +- vactive = <480>; +- hfront-porch = <30>; +- hback-porch = <30>; +- hsync-len = <64>; +- vback-porch = <5>; +- vfront-porch = <5>; +- vsync-len = <20>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- }; +- }; +-}; +- +-&pwm8 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm8>; +- status = "okay"; +-}; +- +-&sai2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai2>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- no-1-8-v; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; +- bus-width = <8>; +- no-1-8-v; +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0 +- MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x1b0b0 +- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 +- MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 +- MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 +- MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 +- MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 +- MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 +- MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 +- MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 +- MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 +- MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 +- MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 +- MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 +- MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 +- MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 +- MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 +- MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 +- MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0 +- MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0 +- >; +- }; +- +- pinctrl_lcdif_ctrl: lcdifctrlgrp { +- fsl,pins = < +- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 +- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 +- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 +- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 +- >; +- }; +- +- pinctrl_lcdif_dat: lcdifdatgrp { +- fsl,pins = < +- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 +- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 +- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 +- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 +- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 +- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 +- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 +- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 +- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 +- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 +- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 +- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 +- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 +- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 +- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 +- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 +- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 +- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 +- >; +- }; +- +- pinctrl_pwm8: pwm8grp { +- fsl,pins = < +- MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 +- >; +- }; +- +- pinctrl_sai2: sai2grp { +- fsl,pins = < +- MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 +- MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031 +- MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 +- MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 +- MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 +- >; +- }; +- +- pinctrl_stmpe: stmpegrp { +- fsl,pins = < +- MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1grp100mhz { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1grp200mhz { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070 +- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070 +- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070 +- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070 +- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070 +- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070 +- MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070 +- MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070 +- MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070 +- MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070 +- MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6310-s-43.dts b/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6310-s-43.dts +deleted file mode 100644 +index 5bfad4655b22..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6310-s-43.dts ++++ /dev/null +@@ -1,103 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2017 exceet electronics GmbH +- * Copyright (C) 2018 Kontron Electronics GmbH +- * Copyright (c) 2019 Krzysztof Kozlowski +- */ +- +-#include "imx6ul-kontron-n6310-s.dts" +- +-/ { +- model = "Kontron N6310 S 43"; +- compatible = "kontron,imx6ul-n6310-s-43", "kontron,imx6ul-n6310-s", +- "kontron,imx6ul-n6310-som", "fsl,imx6ul"; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm7 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- status = "okay"; +- }; +-}; +- +-&i2c4 { +- touchscreen@5d { +- compatible = "goodix,gt928"; +- reg = <0x5d>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_cap_touch>; +- interrupt-parent = <&gpio5>; +- interrupts = <6 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; +- irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&lcdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; +- /* Leave status disabled because of missing display panel node */ +-}; +- +-&pwm7 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm7>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_cap_touch: captouchgrp { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* Touch Interrupt */ +- MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* Touch Reset */ +- MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Touch Wake */ +- >; +- }; +- +- pinctrl_lcdif_ctrl: lcdifctrlgrp { +- fsl,pins = < +- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 +- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 +- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 +- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 +- MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 +- >; +- }; +- +- pinctrl_lcdif_dat: lcdifdatgrp { +- fsl,pins = < +- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 +- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 +- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 +- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 +- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 +- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 +- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 +- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 +- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 +- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 +- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 +- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 +- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 +- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 +- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 +- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 +- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 +- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 +- MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 +- MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 +- MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 +- MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 +- MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 +- MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 +- >; +- }; +- +- pinctrl_pwm7: pwm7grp { +- fsl,pins = < +- MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x110b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6310-s.dts b/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6310-s.dts +deleted file mode 100644 +index 5a3e06d6219b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6310-s.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2017 exceet electronics GmbH +- * Copyright (C) 2018 Kontron Electronics GmbH +- * Copyright (c) 2019 Krzysztof Kozlowski +- */ +- +-/dts-v1/; +- +-#include "imx6ul-kontron-n6310-som.dtsi" +-#include "imx6ul-kontron-n6x1x-s.dtsi" +- +-/ { +- model = "Kontron N6310 S"; +- compatible = "kontron,imx6ul-n6310-s", "kontron,imx6ul-n6310-som", +- "fsl,imx6ul"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6310-som.dtsi b/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6310-som.dtsi +deleted file mode 100644 +index 47d3ce5d255f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6310-som.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2017 exceet electronics GmbH +- * Copyright (C) 2018 Kontron Electronics GmbH +- * Copyright (c) 2019 Krzysztof Kozlowski +- */ +- +-#include "imx6ul.dtsi" +-#include "imx6ul-kontron-n6x1x-som-common.dtsi" +- +-/ { +- model = "Kontron N6310 SOM"; +- compatible = "kontron,imx6ul-n6310-som", "fsl,imx6ul"; +- +- memory@80000000 { +- reg = <0x80000000 0x10000000>; +- device_type = "memory"; +- }; +-}; +- +-&qspi { +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spi-nand"; +- spi-max-frequency = <108000000>; +- spi-tx-bus-width = <4>; +- spi-rx-bus-width = <4>; +- reg = <0>; +- +- partition@0 { +- label = "ubi1"; +- reg = <0x00000000 0x08000000>; +- }; +- +- partition@8000000 { +- label = "ubi2"; +- reg = <0x08000000 0x08000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6311-s.dts b/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6311-s.dts +deleted file mode 100644 +index 239a1af3aeaa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6311-s.dts ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2017 exceet electronics GmbH +- * Copyright (C) 2018 Kontron Electronics GmbH +- */ +- +-/dts-v1/; +- +-#include "imx6ul-kontron-n6311-som.dtsi" +-#include "imx6ul-kontron-n6x1x-s.dtsi" +- +-/ { +- model = "Kontron N6311 S"; +- compatible = "kontron,imx6ul-n6311-s", "kontron,imx6ul-n6311-som", +- "fsl,imx6ul"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6311-som.dtsi b/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6311-som.dtsi +deleted file mode 100644 +index a095a7654ac6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6311-som.dtsi ++++ /dev/null +@@ -1,40 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2017 exceet electronics GmbH +- * Copyright (C) 2018 Kontron Electronics GmbH +- */ +- +-#include "imx6ul.dtsi" +-#include "imx6ul-kontron-n6x1x-som-common.dtsi" +- +-/ { +- model = "Kontron N6311 SOM"; +- compatible = "kontron,imx6ul-n6311-som", "fsl,imx6ul"; +- +- memory@80000000 { +- reg = <0x80000000 0x20000000>; +- device_type = "memory"; +- }; +-}; +- +-&qspi { +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spi-nand"; +- spi-max-frequency = <104000000>; +- spi-tx-bus-width = <4>; +- spi-rx-bus-width = <4>; +- reg = <0>; +- +- partition@0 { +- label = "ubi1"; +- reg = <0x00000000 0x08000000>; +- }; +- +- partition@8000000 { +- label = "ubi2"; +- reg = <0x08000000 0x18000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6x1x-s.dtsi b/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6x1x-s.dtsi +deleted file mode 100644 +index 770f59b23102..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6x1x-s.dtsi ++++ /dev/null +@@ -1,406 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2017 exceet electronics GmbH +- * Copyright (C) 2018 Kontron Electronics GmbH +- * Copyright (c) 2019 Krzysztof Kozlowski +- */ +- +-#include +- +-/ { +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led1 { +- label = "debug-led1"; +- gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led2 { +- label = "debug-led2"; +- gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led3 { +- label = "debug-led3"; +- gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- pwm-beeper { +- compatible = "pwm-beeper"; +- pwms = <&pwm8 0 5000>; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_5v: regulator-5v { +- compatible = "regulator-fixed"; +- regulator-name = "5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usb_otg1_vbus: regulator-usb-otg1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_vref_adc: regulator-vref-adc { +- compatible = "regulator-fixed"; +- regulator-name = "vref-adc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&adc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc1>; +- num-channels = <3>; +- vref-supply = <®_vref_adc>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- status = "okay"; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- eeprom@0 { +- compatible = "anvo,anv32e61w", "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- spi-cpha; +- spi-cpol; +- pagesize = <1>; +- size = <8192>; +- address-width = <16>; +- }; +-}; +- +-&fec1 { +- pinctrl-0 = <&pinctrl_enet1>; +- /delete-node/ mdio; +-}; +- +-&fec2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; +- phy-mode = "rmii"; +- phy-handle = <ðphy2>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- micrel,led-mode = <0>; +- clocks = <&clks IMX6UL_CLK_ENET_REF>; +- clock-names = "rmii-ref"; +- }; +- +- ethphy2: ethernet-phy@2 { +- reg = <2>; +- micrel,led-mode = <0>; +- clocks = <&clks IMX6UL_CLK_ENET2_REF>; +- clock-names = "rmii-ref"; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +-}; +- +-&i2c4 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +- +- rtc@32 { +- compatible = "epson,rx8900"; +- reg = <0x32>; +- }; +-}; +- +-&pwm8 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm8>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- linux,rs485-enabled-at-boot-time; +- rs485-rx-during-tx; +- rs485-rts-active-low; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- fsl,uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbotg1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg1>; +- dr_mode = "otg"; +- srp-disable; +- hnp-disable; +- adp-disable; +- over-current-active-low; +- vbus-supply = <®_usb_otg1_vbus>; +- status = "okay"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- disable-over-current; +- vbus-supply = <®_5v>; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; +- keep-power-in-suspend; +- wakeup-source; +- vmmc-supply = <®_3v3>; +- voltage-ranges = <3300 3300>; +- no-1-8-v; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>; +- non-removable; +- keep-power-in-suspend; +- wakeup-source; +- vmmc-supply = <®_3v3>; +- voltage-ranges = <3300 3300>; +- no-1-8-v; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>; +- +- pinctrl_adc1: adc1grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 +- MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 +- MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1 +- MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1 +- MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1 +- MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */ +- >; +- }; +- +- pinctrl_enet2: enet2grp { +- fsl,pins = < +- MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 +- MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 +- MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 +- MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 +- MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 +- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 +- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 +- MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009 +- >; +- }; +- +- pinctrl_enet2_mdio: enet2mdiogrp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 +- MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp{ +- fsl,pins = < +- MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 +- MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 +- >; +- }; +- +- pinctrl_gpio: gpiogrp { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ +- MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ +- MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ +- MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */ +- MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */ +- MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */ +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 +- MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0 +- MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0 +- >; +- }; +- +- pinctrl_pwm8: pwm8grp { +- fsl,pins = < +- MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1 +- MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1 +- MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1 +- /* +- * mux unused RTS to make sure it doesn't cause +- * any interrupts when it is undefined +- */ +- MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 +- MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 +- MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_usbotg1: usbotg1 { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 +- MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */ +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 +- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 +- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 +- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 +- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 +- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { +- fsl,pins = < +- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 +- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 +- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 +- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 +- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 +- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { +- fsl,pins = < +- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 +- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 +- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 +- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 +- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 +- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6x1x-som-common.dtsi b/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6x1x-som-common.dtsi +deleted file mode 100644 +index 2a449a3c1ae2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-kontron-n6x1x-som-common.dtsi ++++ /dev/null +@@ -1,122 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2017 exceet electronics GmbH +- * Copyright (C) 2018 Kontron Electronics GmbH +- * Copyright (c) 2019 Krzysztof Kozlowski +- */ +- +-#include +- +-/ { +- chosen { +- stdout-path = &uart4; +- }; +-}; +- +-&ecspi2 { +- cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- status = "okay"; +- +- spi-flash@0 { +- compatible = "mxicy,mx25v8035f", "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- reg = <0>; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>; +- phy-mode = "rmii"; +- phy-handle = <ðphy1>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- micrel,led-mode = <0>; +- clocks = <&clks IMX6UL_CLK_ENET_REF>; +- clock-names = "rmii-ref"; +- }; +- }; +-}; +- +-&fec2 { +- phy-mode = "rmii"; +- status = "disabled"; +-}; +- +-&qspi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_qspi>; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reset_out>; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1 +- MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1 +- MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1 +- MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1 +- >; +- }; +- +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009 +- >; +- }; +- +- pinctrl_enet1_mdio: enet1mdiogrp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 +- MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 +- >; +- }; +- +- pinctrl_qspi: qspigrp { +- fsl,pins = < +- MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 +- MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 +- MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 +- MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 +- MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 +- MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 +- >; +- }; +- +- pinctrl_reset_out: rstoutgrp { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x18b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-liteboard.dts b/scripts/dtc/include-prefixes/arm/imx6ul-liteboard.dts +deleted file mode 100644 +index 1d863a16bcf0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-liteboard.dts ++++ /dev/null +@@ -1,151 +0,0 @@ +-/* +- * Copyright 2016 Grinn +- * +- * Author: Marcin Niestroj +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include "imx6ul-litesom.dtsi" +- +-/ { +- model = "Grinn i.MX6UL liteBoard"; +- compatible = "grinn,imx6ul-liteboard", "grinn,imx6ul-litesom", +- "fsl,imx6ul"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- reg_usb_otg1_vbus: regulator-usb-otg1-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_otg1_vbus>; +- regulator-name = "usb_otg1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio2 8 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&iomuxc { +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 +- MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 +- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usb_otg1_vbus: usb-otg1-vbus { +- fsl,pins = < +- MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x79 +- >; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- phy-mode = "rmii"; +- phy-handle = <ðphy0>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +-}; +- +-&snvs_poweroff { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usbotg1 { +- vbus-supply = <®_usb_otg1_vbus>; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- keep-power-in-suspend; +- wakeup-source; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-litesom.dtsi b/scripts/dtc/include-prefixes/arm/imx6ul-litesom.dtsi +deleted file mode 100644 +index 8d6893210842..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-litesom.dtsi ++++ /dev/null +@@ -1,83 +0,0 @@ +-/* +- * Copyright 2016 Grinn +- * +- * Author: Marcin Niestroj +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "imx6ul.dtsi" +- +-/ { +- model = "Grinn i.MX6UL liteSOM"; +- compatible = "grinn,imx6ul-litesom", "fsl,imx6ul"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +-}; +- +-&iomuxc { +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 +- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 +- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 +- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 +- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 +- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 +- MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 +- MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 +- MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 +- MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 +- MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 +- >; +- }; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- no-1-8-v; +- non-removable; +- keep-power-in-suspend; +- wakeup-source; +- bus-width = <8>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-opos6ul.dtsi b/scripts/dtc/include-prefixes/arm/imx6ul-opos6ul.dtsi +deleted file mode 100644 +index 6ce84f92b027..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-opos6ul.dtsi ++++ /dev/null +@@ -1,6 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-// +-// Copyright 2017 Armadeus Systems +- +-#include "imx6ul.dtsi" +-#include "imx6ul-imx6ull-opos6ul.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-opos6uldev.dts b/scripts/dtc/include-prefixes/arm/imx6ul-opos6uldev.dts +deleted file mode 100644 +index 375b98d7205a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-opos6uldev.dts ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-// +-// Copyright 2017 Armadeus Systems +- +-/dts-v1/; +-#include "imx6ul-opos6ul.dtsi" +-#include "imx6ul-imx6ull-opos6uldev.dtsi" +- +-/ { +- model = "Armadeus Systems OPOS6UL SoM (i.MX6UL) on OPOS6ULDev board"; +- compatible = "armadeus,imx6ul-opos6uldev", "armadeus,imx6ul-opos6ul", "fsl,imx6ul"; +-}; +- +-&iomuxc { +- pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_tamper_gpios>; +- +- pinctrl_tamper_gpios: tampergpiosgrp { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0 +- MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0 +- MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 +- MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 +- MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 +- MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 +- MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 +- MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0 +- >; +- }; +- +- pinctrl_usbotg2_vbus: usbotg2vbusgrp { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 +- >; +- }; +- +- pinctrl_w1: w1grp { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-phytec-phycore-som.dtsi b/scripts/dtc/include-prefixes/arm/imx6ul-phytec-phycore-som.dtsi +deleted file mode 100644 +index 19a062635ff6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-phytec-phycore-som.dtsi ++++ /dev/null +@@ -1,172 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2016 PHYTEC Messtechnik GmbH +- * Author: Christian Hemp +- */ +- +-#include +-#include +-#include +- +-/ { +- model = "PHYTEC phyCORE-i.MX6 UltraLite"; +- compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- /* +- * Set the minimum memory size here and +- * let the bootloader set the real size. +- */ +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x8000000>; +- }; +- +- gpio_leds_som: leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpioleds_som>; +- compatible = "gpio-leds"; +- +- phycore-green { +- gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- phy-mode = "rmii"; +- phy-handle = <ðphy1>; +- status = "disabled"; +- +- mdio: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- interrupt-parent = <&gpio1>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- micrel,led-mode = <1>; +- clocks = <&clks IMX6UL_CLK_ENET_REF>; +- clock-names = "rmii-ref"; +- status = "disabled"; +- }; +- }; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- nand-on-flash-bbt; +- status = "disabled"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clock-frequency = <100000>; +- status = "okay"; +- +- eeprom@52 { +- compatible = "catalyst,24c32", "atmel,24c32"; +- pagesize = <32>; +- reg = <0x52>; +- }; +-}; +- +-&snvs_poweroff { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10010 +- MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10010 +- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010 +- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010 +- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010 +- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010 +- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059 +- >; +- }; +- +- pinctrl_gpioleds_som: gpioledssomgrp { +- fsl,pins = ; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 +- MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 +- MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 +- MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 +- MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 +- MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 +- MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 +- MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 +- MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 +- MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 +- MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 +- MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 +- MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 +- MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 +- MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 +- >; +- }; +- +- pinctrl_i2c1: i2cgrp { +- fsl,pins = < +- MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 +- MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 +- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 +- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 +- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 +- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 +- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 +- MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 +- MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 +- MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 +- MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 +- >; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-phytec-segin-ff-rdk-emmc.dts b/scripts/dtc/include-prefixes/arm/imx6ul-phytec-segin-ff-rdk-emmc.dts +deleted file mode 100644 +index cfc744f8fcad..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-phytec-segin-ff-rdk-emmc.dts ++++ /dev/null +@@ -1,94 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +-/* +- * Copyright (C) 2020 PHYTEC Messtechnik GmbH +- * Author: Yunus Bas +- */ +- +-/dts-v1/; +-#include "imx6ul.dtsi" +-#include "imx6ul-phytec-phycore-som.dtsi" +-#include "imx6ul-phytec-segin.dtsi" +-#include "imx6ul-phytec-segin-peb-eval-01.dtsi" +-#include "imx6ul-phytec-segin-peb-av-02.dtsi" +- +-/ { +- model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with eMMC"; +- compatible = "phytec,imx6ul-pbacd10-emmc", "phytec,imx6ul-pbacd10", +- "phytec,imx6ul-pcl063","fsl,imx6ul"; +-}; +- +-&adc1 { +- status = "okay"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&ecspi3 { +- status = "okay"; +-}; +- +-ðphy1 { +- status = "okay"; +-}; +- +-ðphy2 { +- status = "okay"; +-}; +- +-&fec1 { +- status = "okay"; +-}; +- +-&fec2 { +- status = "okay"; +-}; +- +-&i2c_rtc { +- status = "okay"; +-}; +- +-®_can1_en { +- status = "okay"; +-}; +- +-®_sound_1v8 { +- status = "okay"; +-}; +- +-®_sound_3v3 { +- status = "okay"; +-}; +- +-&sai2 { +- status = "okay"; +-}; +- +-&sound { +- status = "okay"; +-}; +- +-&tlv320 { +- status = "okay"; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&usbotg1 { +- status = "okay"; +-}; +- +-&usbotg2 { +- status = "okay"; +-}; +- +-&usdhc1 { +- status = "okay"; +-}; +- +-&usdhc2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-phytec-segin-ff-rdk-nand.dts b/scripts/dtc/include-prefixes/arm/imx6ul-phytec-segin-ff-rdk-nand.dts +deleted file mode 100644 +index bff98e676980..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-phytec-segin-ff-rdk-nand.dts ++++ /dev/null +@@ -1,94 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2016 PHYTEC Messtechnik GmbH +- * Author: Christian Hemp +- */ +- +-/dts-v1/; +-#include "imx6ul.dtsi" +-#include "imx6ul-phytec-phycore-som.dtsi" +-#include "imx6ul-phytec-segin.dtsi" +-#include "imx6ul-phytec-segin-peb-eval-01.dtsi" +-#include "imx6ul-phytec-segin-peb-av-02.dtsi" +- +-/ { +- model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND"; +- compatible = "phytec,imx6ul-pbacd10-nand", "phytec,imx6ul-pbacd10", +- "phytec,imx6ul-pcl063", "fsl,imx6ul"; +-}; +- +-&adc1 { +- status = "okay"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&tlv320 { +- status = "okay"; +-}; +- +-&ecspi3 { +- status = "okay"; +-}; +- +-ðphy1 { +- status = "okay"; +-}; +- +-ðphy2 { +- status = "okay"; +-}; +- +-&fec1 { +- status = "okay"; +-}; +- +-&fec2 { +- status = "okay"; +-}; +- +-&gpmi { +- status = "okay"; +-}; +- +-&i2c_rtc { +- status = "okay"; +-}; +- +-®_can1_en { +- status = "okay"; +-}; +- +-®_sound_1v8 { +- status = "okay"; +-}; +- +-®_sound_3v3 { +- status = "okay"; +-}; +- +-&sai2 { +- status = "okay"; +-}; +- +-&sound { +- status = "okay"; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&usbotg1 { +- status = "okay"; +-}; +- +-&usbotg2 { +- status = "okay"; +-}; +- +-&usdhc1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-phytec-segin-peb-av-02.dtsi b/scripts/dtc/include-prefixes/arm/imx6ul-phytec-segin-peb-av-02.dtsi +deleted file mode 100644 +index 7cda6944501d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-phytec-segin-peb-av-02.dtsi ++++ /dev/null +@@ -1,151 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +-/* +- * Copyright (C) 2016, 2020 PHYTEC Messtechnik +- * Author: Christian Hemp +- * Author: Stefan Riedmueller +- */ +- +-/ { +- backlight_lcd: backlight-lcd { +- compatible = "pwm-backlight"; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <5>; +- power-supply = <®_backlight_en>; +- pwms = <&pwm3 0 5000000>; +- status = "disabled"; +- }; +- +- lcd_panel: lcd-panel { +- compatible = "edt,etm0700g0edh6"; +- backlight = <&backlight_lcd>; +- status = "disabled"; +- +- port { +- lcd_panel_in: endpoint { +- remote-endpoint = <&lcdif_parallel_out>; +- }; +- }; +- }; +- +- reg_backlight_en: regulator-backlight-en { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_backlight_en>; +- regulator-name = "backlight-lcd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&i2c1 { +- edt_ft5406: touchscreen@38 { +- compatible = "edt,edt-ft5406"; +- reg = <0x38>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_edt_ft5406>; +- interrupt-parent = <&gpio5>; +- interrupts = <5 IRQ_TYPE_EDGE_FALLING>; +- wakeup-source; +- status = "disabled"; +- }; +- +- stmpe: touchscreen@44 { +- compatible = "st,stmpe811"; +- reg = <0x44>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_stmpe>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- interrupt-parent = <&gpio5>; +- wakeup-source; +- status = "disabled"; +- +- stmpe_touchscreen { +- compatible = "st,stmpe-ts"; +- st,sample-time = <4>; +- st,mod-12b = <1>; +- st,ref-sel = <0>; +- st,adc-freq = <1>; +- st,ave-ctrl = <1>; +- st,touch-det-delay = <2>; +- st,settling = <2>; +- st,fraction-z = <7>; +- st,i-drive = <1>; +- touchscreen-inverted-x = <1>; +- touchscreen-inverted-y = <1>; +- }; +- }; +-}; +- +-&lcdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcdif_dat>; +- status = "disabled"; +- +- port { +- lcdif_parallel_out: endpoint { +- remote-endpoint = <&lcd_panel_in>; +- }; +- }; +-}; +- +-&pwm3 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_edt_ft5406: edtft5406grp { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 +- >; +- }; +- +- pinctrl_backlight_en: bachlightengrp { +- fsl,pins = < +- MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0 +- >; +- }; +- +- pinctrl_lcdif_dat: lcdifdatgrp { +- fsl,pins = < +- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x59 +- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x59 +- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x59 +- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x59 +- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x59 +- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x59 +- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x59 +- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x59 +- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x59 +- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x59 +- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x59 +- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x59 +- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x59 +- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x59 +- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x59 +- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x59 +- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x59 +- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x59 +- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x59 +- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x59 +- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x59 +- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x59 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 +- >; +- }; +- +- pinctrl_stmpe: stmpegrp { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-phytec-segin-peb-eval-01.dtsi b/scripts/dtc/include-prefixes/arm/imx6ul-phytec-segin-peb-eval-01.dtsi +deleted file mode 100644 +index 2f3fd32a1167..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-phytec-segin-peb-eval-01.dtsi ++++ /dev/null +@@ -1,57 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2016 PHYTEC Messtechnik +- * Author: Christian Hemp +- */ +- +-#include +- +-/ { +- gpio_keys: gpio-keys { +- compatible = "gpio-key"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- status = "disabled"; +- +- power { +- label = "Power Button"; +- gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- user_leds: user-leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_user_leds>; +- status = "disabled"; +- +- user-led1 { +- gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "gpio"; +- default-state = "on"; +- }; +- +- user-led2 { +- gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "gpio"; +- default-state = "on"; +- }; +- }; +-}; +- +-&iomuxc { +- pinctrl_gpio_keys: gpio_keysgrp { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79 +- >; +- }; +- +- pinctrl_user_leds: user_ledsgrp { +- fsl,pins = < +- MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x79 +- MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-phytec-segin.dtsi b/scripts/dtc/include-prefixes/arm/imx6ul-phytec-segin.dtsi +deleted file mode 100644 +index 95e4080dd0a6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-phytec-segin.dtsi ++++ /dev/null +@@ -1,303 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2016 PHYTEC Messtechnik GmbH +- * Author: Christian Hemp +- */ +- +-/ { +- model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite"; +- compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul"; +- +- aliases { +- rtc0 = &i2c_rtc; +- rtc1 = &snvs_rtc; +- }; +- +- reg_sound_1v8: regulator-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "i2s-audio-1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- status = "disabled"; +- }; +- +- reg_sound_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "i2s-audio-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- status = "disabled"; +- }; +- +- reg_can1_en: regulator-can1 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&princtrl_flexcan1_en>; +- regulator-name = "Can"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- status = "disabled"; +- }; +- +- reg_adc1_vref_3v3: regulator-vref-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vref-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- sound: sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&dailink_master>; +- simple-audio-card,frame-master = <&dailink_master>; +- simple-audio-card,widgets = +- "Line", "Line In", +- "Line", "Line Out", +- "Speaker", "Speaker"; +- simple-audio-card,routing = +- "Line Out", "LLOUT", +- "Line Out", "RLOUT", +- "Speaker", "SPOP", +- "Speaker", "SPOM", +- "LINE1L", "Line In", +- "LINE1R", "Line In"; +- status = "disabled"; +- +- simple-audio-card,cpu { +- sound-dai = <&sai2>; +- }; +- +- dailink_master: simple-audio-card,codec { +- sound-dai = <&tlv320>; +- clocks = <&clks IMX6UL_CLK_SAI2>; +- }; +- }; +- +-}; +- +-&adc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc1>; +- vref-supply = <®_adc1_vref_3v3>; +- /* +- * driver can not separate a specific channel so we request 4 channels +- * here - we need only the fourth channel +- */ +- num-channels = <4>; +- status = "disabled"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- xceiver-supply = <®_can1_en>; +- status = "disabled"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; +- assigned-clock-rates = <786432000>; +-}; +- +-&ecspi3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi3>; +- cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; +- status = "disabled"; +-}; +- +-&fec2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet2>; +- phy-mode = "rmii"; +- phy-handle = <ðphy2>; +- status = "disabled"; +-}; +- +-&i2c1 { +- tlv320: codec@18 { +- compatible = "ti,tlv320aic3007"; +- #sound-dai-cells = <0>; +- reg = <0x18>; +- AVDD-supply = <®_sound_3v3>; +- IOVDD-supply = <®_sound_3v3>; +- DRVDD-supply = <®_sound_3v3>; +- DVDD-supply = <®_sound_1v8>; +- status = "disabled"; +- }; +- +- i2c_rtc: rtc@68 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rtc_int>; +- compatible = "microcrystal,rv4162"; +- reg = <0x68>; +- interrupt-parent = <&gpio5>; +- interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +- status = "disabled"; +- }; +-}; +- +-&mdio { +- ethphy2: ethernet-phy@2 { +- reg = <2>; +- micrel,led-mode = <1>; +- clocks = <&clks IMX6UL_CLK_ENET2_REF>; +- clock-names = "rmii-ref"; +- status = "disabled"; +- }; +-}; +- +-&sai2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai2>; +- assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, +- <&clks IMX6UL_CLK_SAI2>; +- assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; +- assigned-clock-rates = <0>, <19200000>; +- fsl,sai-mclk-direction-output; +- status = "disabled"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- uart-has-rtscts; +- status = "disabled"; +-}; +- +-&usbotg1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_otg1_id>; +- dr_mode = "otg"; +- status = "disabled"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- disable-over-current; +- status = "disabled"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- keep-power-in-suspend; +- wakeup-source; +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_adc1: adc1grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 +- >; +- }; +- +- pinctrl_ecspi3: ecspi3grp { +- fsl,pins = < +- MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 +- MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 +- MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 +- MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 +- >; +- }; +- +- pinctrl_enet2: enet2grp { +- fsl,pins = < +- MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 +- MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 +- MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 +- MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 +- MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 +- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 +- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 +- MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1 { +- fsl,pins = < +- MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 +- MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 +- >; +- }; +- +- princtrl_flexcan1_en: flexcan1engrp { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 +- >; +- }; +- +- pinctrl_rtc_int: rtcintgrp { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 +- >; +- }; +- +- pinctrl_sai2: sai2grp { +- fsl,pins = < +- MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 +- MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 +- MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 +- MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 +- MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 +- MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 +- MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 +- >; +- }; +- +- pinctrl_usb_otg1_id: usbotg1idgrp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 +- MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1grp100mhz { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1grp200mhz { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-pico-dwarf.dts b/scripts/dtc/include-prefixes/arm/imx6ul-pico-dwarf.dts +deleted file mode 100644 +index 162dc259edc8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-pico-dwarf.dts ++++ /dev/null +@@ -1,52 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright 2015 Technexion Ltd. +-// +-// Author: Wig Cheng +-// Richard Hu +-// Tapani Utriainen +-/dts-v1/; +- +-#include "imx6ul-pico.dtsi" +-/ { +- model = "TechNexion PICO-IMX6UL and DWARF baseboard"; +- compatible = "technexion,imx6ul-pico-dwarf", "fsl,imx6ul"; +- +- sound { +- compatible = "fsl,imx-audio-sgtl5000"; +- model = "imx6ul-sgtl5000"; +- audio-cpu = <&sai1>; +- audio-codec = <&sgtl5000>; +- audio-routing = +- "LINE_IN", "Line In Jack", +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- }; +- +- sys_mclk: clock-sys-mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +-}; +- +-&i2c2 { +- clock_frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- sgtl5000: audio-codec@a { +- reg = <0x0a>; +- compatible = "fsl,sgtl5000"; +- clocks = <&sys_mclk>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_3p3v>; +- }; +- +- pressure-sensor@60 { +- compatible = "fsl,mpl3115"; +- reg = <0x60>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-pico-hobbit.dts b/scripts/dtc/include-prefixes/arm/imx6ul-pico-hobbit.dts +deleted file mode 100644 +index 09f7ffa9ad8c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-pico-hobbit.dts ++++ /dev/null +@@ -1,100 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright 2015 Technexion Ltd. +-// +-// Author: Wig Cheng +-// Richard Hu +-// Tapani Utriainen +-/dts-v1/; +- +-#include "imx6ul-pico.dtsi" +-/ { +- model = "TechNexion PICO-IMX6UL and HOBBIT baseboard"; +- compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul"; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led { +- label = "gpio-led"; +- gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- sound { +- compatible = "fsl,imx-audio-sgtl5000"; +- model = "imx6ul-sgtl5000"; +- audio-cpu = <&sai1>; +- audio-codec = <&sgtl5000>; +- audio-routing = +- "LINE_IN", "Line In Jack", +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- }; +- +- sys_mclk: clock-sys-mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- sgtl5000: codec@a { +- reg = <0x0a>; +- compatible = "fsl,sgtl5000"; +- clocks = <&sys_mclk>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_3p3v>; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +- +- polytouch: touchscreen@38 { +- compatible = "edt,edt-ft5x06"; +- reg = <0x38>; +- interrupt-parent = <&gpio1>; +- interrupts = <29 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; +- touchscreen-size-x = <800>; +- touchscreen-size-y = <480>; +- }; +- +- adc081c: adc@50 { +- compatible = "ti,adc081c"; +- reg = <0x50>; +- vref-supply = <®_3p3v>; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 +- MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 +- MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 +- MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 +- MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x10b0 +- MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x10b0 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x10b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-pico-pi.dts b/scripts/dtc/include-prefixes/arm/imx6ul-pico-pi.dts +deleted file mode 100644 +index 6cd7d5877d20..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-pico-pi.dts ++++ /dev/null +@@ -1,97 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright 2015 Technexion Ltd. +-// +-// Author: Wig Cheng +-// Richard Hu +-// Tapani Utriainen +-/dts-v1/; +- +-#include "imx6ul-pico.dtsi" +-/ { +- model = "TechNexion PICO-IMX6UL and PI baseboard"; +- compatible = "technexion,imx6ul-pico-pi", "fsl,imx6ul"; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led { +- label = "gpio-led"; +- gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- sound { +- compatible = "fsl,imx-audio-sgtl5000"; +- model = "imx6ul-sgtl5000"; +- audio-cpu = <&sai1>; +- audio-codec = <&sgtl5000>; +- audio-routing = +- "LINE_IN", "Line In Jack", +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- }; +- +- sys_mclk: clock-sys-mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- sgtl5000: codec@a { +- reg = <0x0a>; +- compatible = "fsl,sgtl5000"; +- clocks = <&sys_mclk>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_3p3v>; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- polytouch: touchscreen@38 { +- compatible = "edt,edt-ft5x06"; +- reg = <0x38>; +- interrupt-parent = <&gpio1>; +- interrupts = <29 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; +- touchscreen-size-x = <800>; +- touchscreen-size-y = <480>; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 +- MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 +- MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 +- MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 +- MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x10b0 +- MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x10b0 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-pico.dtsi b/scripts/dtc/include-prefixes/arm/imx6ul-pico.dtsi +deleted file mode 100644 +index 357ffb2f5ad6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-pico.dtsi ++++ /dev/null +@@ -1,453 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright 2015 Technexion Ltd. +-// +-// Author: Wig Cheng +-// Richard Hu +-// Tapani Utriainen +-/dts-v1/; +- +-#include "imx6ul.dtsi" +- +-/ { +- /* Will be filled by the bootloader */ +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0>; +- }; +- +- chosen { +- stdout-path = &uart6; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm3 0 5000000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- status = "okay"; +- }; +- +- reg_2p5v: regulator-2p5v { +- compatible = "regulator-fixed"; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_sd1_vmmc: regulator-sd1-vmmc { +- compatible = "regulator-fixed"; +- regulator-name = "VSD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_otg1>; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 6 0>; +- }; +- +- reg_brcm: regulator-brcm { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_brcm_reg>; +- regulator-name = "brcm_reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <200000>; +- }; +- +- panel { +- compatible = "vxt,vl050-8048nt-c01"; +- backlight = <&backlight>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; +- assigned-clock-rates = <786432000>; +-}; +- +-&fec2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet2>; +- phy-mode = "rmii"; +- phy-handle = <ðphy1>; +- status = "okay"; +- phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <1>; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy1: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- max-speed = <100>; +- interrupt-parent = <&gpio5>; +- interrupts = <6 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic: pfuze3000@8 { +- compatible = "fsl,pfuze3000"; +- reg = <0x08>; +- +- regulators { +- /* VDD_ARM_SOC_IN*/ +- sw1b_reg: sw1b { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1475000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- /* DRAM */ +- sw3a_reg: sw3 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1650000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* DRAM */ +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&lcdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; +- status = "okay"; +- +- port { +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +-}; +- +-&pwm3 { +- #pwm-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "okay"; +-}; +- +-&pwm7 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm7>; +- status = "okay"; +-}; +- +-&pwm8 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm8>; +- status = "okay"; +-}; +- +-&sai1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai1>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart6>; +- status = "okay"; +-}; +- +-&usbotg1 { +- vbus-supply = <®_usb_otg_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_otg1_id>; +- dr_mode = "otg"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- keep-power-in-suspend; +- status = "okay"; +-}; +- +-&usdhc2 { /* Wifi SDIO */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- no-1-8-v; +- non-removable; +- keep-power-in-suspend; +- wakeup-source; +- vmmc-supply = <®_brcm>; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl_brcm_reg: brcmreggrp { +- fsl,pins = < +- MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */ +- MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */ +- >; +- }; +- +- pinctrl_enet2: enet2grp { +- fsl,pins = < +- MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0 +- MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0 +- MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 +- MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 +- MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 +- MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 +- MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 +- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 +- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 +- MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 +- MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800 +- MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 +- MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 +- MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0 +- MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 +- MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0 +- MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0 +- >; +- }; +- +- pinctrl_lcdif_dat: lcdifdatgrp { +- fsl,pins = < +- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 +- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 +- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 +- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 +- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 +- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 +- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 +- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 +- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 +- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 +- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 +- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 +- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 +- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 +- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 +- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 +- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 +- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 +- MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 +- MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 +- MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 +- MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 +- MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 +- MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 +- >; +- }; +- +- pinctrl_lcdif_ctrl: lcdifctrlgrp { +- fsl,pins = < +- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 +- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 +- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 +- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 +- /* LCD reset */ +- MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0 +- >; +- }; +- +- pinctrl_pwm7: pwm7grp { +- fsl,pins = < +- MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0 +- >; +- }; +- +- pinctrl_pwm8: pwm8grp { +- fsl,pins = < +- MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 +- >; +- }; +- +- pinctrl_sai1: sai1grp { +- fsl,pins = < +- MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0 +- MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0 +- MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 +- MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0 +- MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0 +- MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0 +- MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1 +- MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1 +- MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 +- MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 +- >; +- }; +- +- pinctrl_uart6: uart6grp { +- fsl,pins = < +- MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 +- MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_usb_otg1: usbotg1grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0 +- >; +- }; +- +- pinctrl_usb_otg1_id: usbotg1idgrp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 +- MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029 +- MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 +- MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 +- MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 +- MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 +- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 +- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 +- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 +- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 +- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-pinfunc.h b/scripts/dtc/include-prefixes/arm/imx6ul-pinfunc.h +deleted file mode 100644 +index 380d2db13a9b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-pinfunc.h ++++ /dev/null +@@ -1,959 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2014 - 2015 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __DTS_IMX6UL_PINFUNC_H +-#define __DTS_IMX6UL_PINFUNC_H +- +-/* +- * The pin function ID is a tuple of +- * +- */ +-#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0 +-#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0 +- +-#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0 +-#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0 +-#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0 +-#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0 +-#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0 +-#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0 +-#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0 +-#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0 +-#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x003c 0x02c8 0x0000 5 0 +-#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0040 0x02cc 0x0000 5 0 +- +-#define MX6UL_PAD_JTAG_MOD__SJC_MOD 0x0044 0x02d0 0x0000 0 0 +-#define MX6UL_PAD_JTAG_MOD__GPT2_CLK 0x0044 0x02d0 0x05a0 1 0 +-#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT 0x0044 0x02d0 0x0000 2 0 +-#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02d0 0x0000 3 0 +-#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02d0 0x04c0 4 0 +-#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02d0 0x0000 5 0 +-#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0610 6 0 +-#define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02d4 0x0000 0 0 +-#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02d4 0x0598 1 0 +-#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x05f0 2 0 +-#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02d4 0x0000 3 0 +-#define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02d4 0x0000 4 0 +-#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02d4 0x0000 5 0 +-#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0614 6 0 +-#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02d4 0x0000 8 0 +-#define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004c 0x02d8 0x0000 0 0 +-#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004c 0x02d8 0x059c 1 0 +-#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x004c 0x02d8 0x05fc 2 0 +-#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2 0x004c 0x02d8 0x0000 3 0 +-#define MX6UL_PAD_JTAG_TDO__CCM_STOP 0x004c 0x02d8 0x0000 4 0 +-#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x004c 0x02d8 0x0000 5 0 +-#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x004c 0x02d8 0x0000 6 0 +-#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT 0x004c 0x02d8 0x0000 8 0 +-#define MX6UL_PAD_JTAG_TDI__SJC_TDI 0x0050 0x02dc 0x0000 0 0 +-#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1 0x0050 0x02dc 0x0000 1 0 +-#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0050 0x02dc 0x05f8 2 0 +-#define MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0050 0x02dc 0x0000 4 0 +-#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x0050 0x02dc 0x0000 5 0 +-#define MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x0050 0x02dc 0x0000 6 0 +-#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL 0x0050 0x02dc 0x0000 8 0 +-#define MX6UL_PAD_JTAG_TCK__SJC_TCK 0x0054 0x02e0 0x0000 0 0 +-#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2 0x0054 0x02e0 0x0000 1 0 +-#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02e0 0x05f4 2 0 +-#define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02e0 0x0000 4 0 +-#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02e0 0x0000 5 0 +-#define MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x0054 0x02e0 0x0000 6 0 +-#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02e0 0x0000 8 0 +-#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02e4 0x0000 0 0 +-#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02e4 0x0000 1 0 +-#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02e4 0x0000 2 0 +-#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02e4 0x0000 4 0 +-#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02e4 0x0000 5 0 +-#define MX6UL_PAD_JTAG_TRST_B__REF_CLK_24M 0x0058 0x02e4 0x0000 6 0 +-#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02e4 0x0000 8 0 +-#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005c 0x02e8 0x05ac 0 1 +-#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005c 0x02e8 0x058c 1 0 +-#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x005c 0x02e8 0x04b8 2 0 +-#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1 0x005c 0x02e8 0x0574 3 0 +-#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x005c 0x02e8 0x0000 4 0 +-#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x005c 0x02e8 0x0000 5 0 +-#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN 0x005c 0x02e8 0x0000 6 0 +-#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET 0x005c 0x02e8 0x0000 7 0 +-#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B 0x005c 0x02e8 0x0000 8 0 +-#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x0060 0x02ec 0x05b0 0 1 +-#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1 0x0060 0x02ec 0x0000 1 0 +-#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0060 0x02ec 0x0664 2 0 +-#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2 0x0060 0x02ec 0x057c 3 0 +-#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x0060 0x02ec 0x0000 4 0 +-#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x0060 0x02ec 0x0000 5 0 +-#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT 0x0060 0x02ec 0x0000 6 0 +-#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET 0x0060 0x02ec 0x0000 7 0 +-#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x0060 0x02ec 0x0000 8 0 +-#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x0064 0x02f0 0x05a4 0 0 +-#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2 0x0064 0x02f0 0x0000 1 0 +-#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR 0x0064 0x02f0 0x0000 2 0 +-#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02f0 0x0000 3 0 +-#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02f0 0x066c 4 0 +-#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02f0 0x0000 5 0 +-#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0610 6 1 +-#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02f0 0x0000 7 0 +-#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02f0 0x0000 8 0 +-#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02f0 0x0624 8 0 +-#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02f4 0x05a8 0 1 +-#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02f4 0x0000 1 0 +-#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02f4 0x0660 2 0 +-#define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x0068 0x02f4 0x0000 3 0 +-#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02f4 0x0668 4 0 +-#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02f4 0x0000 5 0 +-#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK 0x0068 0x02f4 0x0000 6 0 +-#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02f4 0x0000 7 0 +-#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02f4 0x0624 8 1 +-#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0 +-#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006c 0x02f8 0x0574 0 1 +-#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006c 0x02f8 0x0000 1 0 +-#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006c 0x02f8 0x0000 2 0 +-#define MX6UL_PAD_GPIO1_IO04__REF_CLK_24M 0x006c 0x02f8 0x0000 3 0 +-#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006c 0x02f8 0x0000 4 0 +-#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006c 0x02f8 0x0000 5 0 +-#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006c 0x02f8 0x0000 6 0 +-#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x006c 0x02f8 0x0000 8 0 +-#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x006c 0x02f8 0x0644 8 2 +-#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x0070 0x02fc 0x057c 0 1 +-#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x0070 0x02fc 0x0000 1 0 +-#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID 0x0070 0x02fc 0x04bc 2 0 +-#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD 0x0070 0x02fc 0x0530 3 0 +-#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x0070 0x02fc 0x0000 4 0 +-#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x0070 0x02fc 0x0000 5 0 +-#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT 0x0070 0x02fc 0x0000 6 0 +-#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0070 0x02fc 0x0644 8 3 +-#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x0070 0x02fc 0x0000 8 0 +-#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x0074 0x0300 0x0578 0 0 +-#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x0074 0x0300 0x0580 1 0 +-#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE 0x0074 0x0300 0x0000 2 0 +-#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK 0x0074 0x0300 0x0000 3 0 +-#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP 0x0074 0x0300 0x069c 4 0 +-#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0074 0x0300 0x0000 5 0 +-#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT 0x0074 0x0300 0x0000 6 0 +-#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B 0x0074 0x0300 0x0000 7 0 +-#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS 0x0074 0x0300 0x0000 8 0 +-#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS 0x0074 0x0300 0x0620 8 0 +-#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0078 0x0304 0x0000 0 0 +-#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0078 0x0304 0x0000 1 0 +-#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE 0x0078 0x0304 0x0000 2 0 +-#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK 0x0078 0x0304 0x0528 3 0 +-#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B 0x0078 0x0304 0x0674 4 1 +-#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0078 0x0304 0x0000 5 0 +-#define MX6UL_PAD_GPIO1_IO07__CCM_STOP 0x0078 0x0304 0x0000 6 0 +-#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS 0x0078 0x0304 0x0620 8 1 +-#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS 0x0078 0x0304 0x0000 8 0 +-#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x007c 0x0308 0x0000 0 0 +-#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x007c 0x0308 0x0000 1 0 +-#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x007c 0x0308 0x0000 2 0 +-#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC 0x007c 0x0308 0x052c 3 1 +-#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x007c 0x0308 0x0000 4 0 +-#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x007c 0x0308 0x0000 5 0 +-#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x007c 0x0308 0x04c0 6 1 +-#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x007c 0x0308 0x0640 8 1 +-#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS 0x007c 0x0308 0x0000 8 0 +-#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x0080 0x030c 0x0000 0 0 +-#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x0080 0x030c 0x0000 1 0 +-#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x0080 0x030c 0x0618 2 0 +-#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC 0x0080 0x030c 0x0524 3 1 +-#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B 0x0080 0x030c 0x0000 4 0 +-#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0080 0x030c 0x0000 5 0 +-#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B 0x0080 0x030c 0x0000 6 0 +-#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0080 0x030c 0x0000 8 0 +-#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS 0x0080 0x030c 0x0640 8 2 +-#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0084 0x0310 0x0000 0 0 +-#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x0084 0x0310 0x0624 0 2 +-#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02 0x0084 0x0310 0x0000 1 0 +-#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x0084 0x0310 0x05b4 2 0 +-#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02 0x0084 0x0310 0x04c4 3 1 +-#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1 0x0084 0x0310 0x0000 4 0 +-#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16 0x0084 0x0310 0x0000 5 0 +-#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT 0x0084 0x0310 0x0000 8 0 +-#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0088 0x0314 0x0624 0 3 +-#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0088 0x0314 0x0000 0 0 +-#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x0088 0x0314 0x0000 1 0 +-#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x0088 0x0314 0x05b8 2 0 +-#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03 0x0088 0x0314 0x04c8 3 1 +-#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK 0x0088 0x0314 0x0594 4 0 +-#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17 0x0088 0x0314 0x0000 5 0 +-#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN 0x0088 0x0314 0x0618 8 1 +-#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x008c 0x0318 0x0000 0 0 +-#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x008c 0x0318 0x0620 0 2 +-#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x008c 0x0318 0x0000 1 0 +-#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP 0x008c 0x0318 0x066c 2 1 +-#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04 0x008c 0x0318 0x04d8 3 0 +-#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN 0x008c 0x0318 0x0000 4 0 +-#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x008c 0x0318 0x0000 5 0 +-#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP 0x008c 0x0318 0x069c 8 1 +-#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0090 0x031c 0x0620 0 3 +-#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x0090 0x031c 0x0000 0 0 +-#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER 0x0090 0x031c 0x0000 1 0 +-#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x0090 0x031c 0x0668 2 1 +-#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05 0x0090 0x031c 0x04cc 3 1 +-#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT 0x0090 0x031c 0x0000 4 0 +-#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0090 0x031c 0x0000 5 0 +-#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B 0x0090 0x031c 0x0674 8 2 +-#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0094 0x0320 0x0000 0 0 +-#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0094 0x0320 0x062c 0 0 +-#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x0094 0x0320 0x0000 1 0 +-#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x0094 0x0320 0x05bc 2 0 +-#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094 0x0320 0x04dc 3 0 +-#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094 0x0320 0x058c 4 1 +-#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094 0x0320 0x0000 5 0 +-#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0560 8 0 +-#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098 0x0324 0x062c 0 1 +-#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098 0x0324 0x0000 0 0 +-#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098 0x0324 0x0000 1 0 +-#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x0098 0x0324 0x05c0 2 0 +-#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07 0x0098 0x0324 0x04e0 3 0 +-#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2 0x0098 0x0324 0x0590 4 0 +-#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x0098 0x0324 0x0000 5 0 +-#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE 0x0098 0x0324 0x0000 7 0 +-#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x0098 0x0324 0x0554 8 0 +-#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x009c 0x0328 0x0000 0 0 +-#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x009c 0x0328 0x0628 0 0 +-#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x009c 0x0328 0x0000 1 0 +-#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x009c 0x0328 0x0000 2 0 +-#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08 0x009c 0x0328 0x04e4 3 0 +-#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2 0x009c 0x0328 0x0000 4 0 +-#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x009c 0x0328 0x0000 5 0 +-#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B 0x009c 0x0328 0x0000 7 0 +-#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x009c 0x0328 0x055c 8 0 +-#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x00a0 0x032c 0x0628 0 1 +-#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x00a0 0x032c 0x0000 0 0 +-#define MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x00a0 0x032c 0x0000 1 0 +-#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x00a0 0x032c 0x0588 2 0 +-#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09 0x00a0 0x032c 0x04e8 3 0 +-#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3 0x00a0 0x032c 0x0000 4 0 +-#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x00a0 0x032c 0x0000 5 0 +-#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL 0x00a0 0x032c 0x0000 7 0 +-#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x00a0 0x032c 0x0558 8 0 +-#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00a4 0x0330 0x0000 0 0 +-#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00a4 0x0330 0x0634 0 0 +-#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00a4 0x0330 0x0000 1 0 +-#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00a4 0x0330 0x0000 2 0 +-#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x04d4 3 0 +-#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00a4 0x0330 0x0000 4 0 +-#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00a4 0x0330 0x0628 4 2 +-#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00a4 0x0330 0x0000 5 0 +-#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT 0x00a4 0x0330 0x0000 7 0 +-#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x00a4 0x0330 0x04b8 8 1 +-#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x00a8 0x0334 0x0634 0 1 +-#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00a8 0x0334 0x0000 0 0 +-#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00a8 0x0334 0x0000 1 0 +-#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00a8 0x0334 0x0000 2 0 +-#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x04d0 3 0 +-#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00a8 0x0334 0x0628 4 3 +-#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00a8 0x0334 0x0000 4 0 +-#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00a8 0x0334 0x0000 5 0 +-#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT 0x00a8 0x0334 0x0000 8 0 +-#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x00ac 0x0338 0x0000 0 0 +-#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00ac 0x0338 0x0630 0 0 +-#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00ac 0x0338 0x0000 1 0 +-#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00ac 0x0338 0x0000 2 0 +-#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x04ec 3 0 +-#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00ac 0x0338 0x0000 4 0 +-#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00ac 0x0338 0x0000 5 0 +-#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00ac 0x0338 0x0000 8 0 +-#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x00b0 0x033c 0x0630 0 1 +-#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00b0 0x033c 0x0000 0 0 +-#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00b0 0x033c 0x0000 1 0 +-#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00b0 0x033c 0x0584 2 0 +-#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x04f0 3 0 +-#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT 0x00b0 0x033c 0x0000 4 0 +-#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00b0 0x033c 0x0000 5 0 +-#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00b0 0x033c 0x0000 8 0 +-#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00b4 0x0340 0x0000 0 0 +-#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00b4 0x0340 0x063c 0 0 +-#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00b4 0x0340 0x0000 1 0 +-#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00b4 0x0340 0x05a4 2 1 +-#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x04f4 3 0 +-#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 0x00b4 0x0340 0x0000 4 0 +-#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00b4 0x0340 0x0000 5 0 +-#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00b4 0x0340 0x0544 8 1 +-#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x00b8 0x0344 0x063c 0 1 +-#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00b8 0x0344 0x0000 0 0 +-#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00b8 0x0344 0x0000 1 0 +-#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00b8 0x0344 0x05a8 2 2 +-#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x04f8 3 0 +-#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 0x00b8 0x0344 0x0000 4 0 +-#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00b8 0x0344 0x0000 5 0 +-#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0550 8 1 +-#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00bc 0x0348 0x0000 5 0 +-#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00bc 0x0348 0x054c 8 0 +-#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00bc 0x0348 0x0000 0 0 +-#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00bc 0x0348 0x0644 0 4 +-#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00bc 0x0348 0x0000 1 0 +-#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00bc 0x0348 0x05ac 2 2 +-#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x04fc 3 0 +-#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 0x00bc 0x0348 0x0000 4 0 +-#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00c0 0x034c 0x0644 0 5 +-#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00c0 0x034c 0x0000 0 0 +-#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00c0 0x034c 0x0000 1 0 +-#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00c0 0x034c 0x05b0 2 2 +-#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0500 3 0 +-#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00c0 0x034c 0x0000 4 0 +-#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00c0 0x034c 0x0000 5 0 +-#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00c0 0x034c 0x0548 8 1 +-#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x00c4 0x0350 0x0000 0 0 +-#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00c4 0x0350 0x0638 1 0 +-#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00c4 0x0350 0x0000 1 0 +-#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00c4 0x0350 0x0000 2 0 +-#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0504 3 0 +-#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00c4 0x0350 0x0000 4 0 +-#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00c4 0x0350 0x0000 5 0 +-#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x05d0 6 0 +-#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00c4 0x0350 0x0000 8 0 +-#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00c8 0x0354 0x0000 0 0 +-#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00c8 0x0354 0x0000 1 0 +-#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00c8 0x0354 0x0638 1 1 +-#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00c8 0x0354 0x0000 2 0 +-#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0508 3 0 +-#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00c8 0x0354 0x0584 4 1 +-#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00c8 0x0354 0x0000 5 0 +-#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x05c4 6 0 +-#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00c8 0x0354 0x0000 8 0 +-#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00cc 0x0358 0x0000 0 0 +-#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00cc 0x0358 0x0640 1 3 +-#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00cc 0x0358 0x0000 1 0 +-#define MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x00cc 0x0358 0x0000 2 0 +-#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x050c 3 0 +-#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00cc 0x0358 0x0000 4 0 +-#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00cc 0x0358 0x0000 5 0 +-#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x05d4 6 0 +-#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00cc 0x0358 0x0000 8 0 +-#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00d0 0x035c 0x0000 0 0 +-#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00d0 0x035c 0x0000 1 0 +-#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00d0 0x035c 0x0640 1 4 +-#define MX6UL_PAD_ENET1_TX_DATA0__REF_CLK_24M 0x00d0 0x035c 0x0000 2 0 +-#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0510 3 0 +-#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00d0 0x035c 0x0588 4 1 +-#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00d0 0x035c 0x0000 5 0 +-#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x05c8 6 0 +-#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00d0 0x035c 0x0000 8 0 +-#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00d4 0x0360 0x0000 0 0 +-#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00d4 0x0360 0x0000 1 0 +-#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00d4 0x0360 0x0648 1 2 +-#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00d4 0x0360 0x0000 2 0 +-#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0514 3 0 +-#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00d4 0x0360 0x0580 4 1 +-#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00d4 0x0360 0x0000 5 0 +-#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x05d8 6 0 +-#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00d4 0x0360 0x0000 8 0 +-#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00d8 0x0364 0x0000 0 0 +-#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00d8 0x0364 0x0648 1 3 +-#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00d8 0x0364 0x0000 1 0 +-#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00d8 0x0364 0x0000 2 0 +-#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0518 3 0 +-#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00d8 0x0364 0x0000 4 0 +-#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00d8 0x0364 0x0000 5 0 +-#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x05cc 6 0 +-#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB 0x00d8 0x0364 0x0000 8 0 +-#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00dc 0x0368 0x0000 0 0 +-#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00dc 0x0368 0x0000 1 0 +-#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00dc 0x0368 0x0650 1 0 +-#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00dc 0x0368 0x0000 2 0 +-#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x051c 3 0 +-#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00dc 0x0368 0x0574 4 2 +-#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00dc 0x0368 0x0000 5 0 +-#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00dc 0x0368 0x0000 6 0 +-#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK 0x00dc 0x0368 0x0594 8 1 +-#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x00e0 0x036c 0x0000 0 0 +-#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00e0 0x036c 0x0650 1 1 +-#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00e0 0x036c 0x0000 1 0 +-#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00e0 0x036c 0x0000 2 0 +-#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0520 3 0 +-#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00e0 0x036c 0x0000 4 0 +-#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00e0 0x036c 0x0000 5 0 +-#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00e0 0x036c 0x0000 6 0 +-#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2 0x00e0 0x036c 0x0590 8 1 +-#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x00e4 0x0370 0x0000 0 0 +-#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x00e4 0x0370 0x0000 1 0 +-#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX 0x00e4 0x0370 0x064c 1 1 +-#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD 0x00e4 0x0370 0x0000 2 0 +-#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL 0x00e4 0x0370 0x05b4 3 1 +-#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00e4 0x0370 0x0578 4 1 +-#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x00e4 0x0370 0x0000 5 0 +-#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x00e4 0x0370 0x0000 6 0 +-#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR 0x00e4 0x0370 0x0000 8 0 +-#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00e8 0x0374 0x0000 0 0 +-#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00e8 0x0374 0x064c 1 2 +-#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00e8 0x0374 0x0000 1 0 +-#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK 0x00e8 0x0374 0x0000 2 0 +-#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00e8 0x0374 0x05b8 3 1 +-#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00e8 0x0374 0x0000 4 0 +-#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00e8 0x0374 0x0000 5 0 +-#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x00e8 0x0374 0x0000 6 0 +-#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC 0x00e8 0x0374 0x0664 8 1 +-#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x00ec 0x0378 0x0000 0 0 +-#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00ec 0x0378 0x0000 1 0 +-#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX 0x00ec 0x0378 0x0654 1 0 +-#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B 0x00ec 0x0378 0x0000 2 0 +-#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL 0x00ec 0x0378 0x05bc 3 1 +-#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26 0x00ec 0x0378 0x0000 4 0 +-#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x00ec 0x0378 0x0000 5 0 +-#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x00ec 0x0378 0x0000 6 0 +-#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M 0x00ec 0x0378 0x0000 8 0 +-#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x00f0 0x037c 0x0000 0 0 +-#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x00f0 0x037c 0x0654 1 1 +-#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX 0x00f0 0x037c 0x0000 1 0 +-#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN 0x00f0 0x037c 0x0000 2 0 +-#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA 0x00f0 0x037c 0x05c0 3 1 +-#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00f0 0x037c 0x0000 4 0 +-#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00f0 0x037c 0x0000 5 0 +-#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00f0 0x037c 0x0000 6 0 +-#define MX6UL_PAD_ENET2_TX_DATA0__REF_CLK_24M 0x00f0 0x037c 0x0000 8 0 +-#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00f4 0x0380 0x0000 0 0 +-#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00f4 0x0380 0x0000 1 0 +-#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00f4 0x0380 0x065c 1 0 +-#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD 0x00f4 0x0380 0x0000 2 0 +-#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x00f4 0x0380 0x0564 3 0 +-#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03 0x00f4 0x0380 0x0000 4 0 +-#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x00f4 0x0380 0x0000 5 0 +-#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x00f4 0x0380 0x0000 6 0 +-#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR 0x00f4 0x0380 0x0000 8 0 +-#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00f8 0x0384 0x0000 0 0 +-#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00f8 0x0384 0x065c 1 1 +-#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00f8 0x0384 0x0000 1 0 +-#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK 0x00f8 0x0384 0x0000 2 0 +-#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00f8 0x0384 0x056c 3 0 +-#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00f8 0x0384 0x0000 4 0 +-#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00f8 0x0384 0x0000 5 0 +-#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x00f8 0x0384 0x0000 6 0 +-#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC 0x00f8 0x0384 0x0660 8 1 +-#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00fc 0x0388 0x0000 0 0 +-#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x00fc 0x0388 0x0000 1 0 +-#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS 0x00fc 0x0388 0x0658 1 0 +-#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B 0x00fc 0x0388 0x0000 2 0 +-#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x00fc 0x0388 0x0568 3 0 +-#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00fc 0x0388 0x057c 4 2 +-#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x00fc 0x0388 0x0000 5 0 +-#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x00fc 0x0388 0x0000 6 0 +-#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID 0x00fc 0x0388 0x04bc 8 1 +-#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x0100 0x038c 0x0000 0 0 +-#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100 0x038c 0x0658 1 1 +-#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100 0x038c 0x0000 1 0 +-#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100 0x038c 0x0000 2 0 +-#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0570 3 0 +-#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100 0x038c 0x0000 4 0 +-#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038c 0x0000 5 0 +-#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038c 0x0000 6 0 +-#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x0100 0x038c 0x0000 8 0 +-#define MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x0104 0x0390 0x0000 0 0 +-#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104 0x0390 0x0000 1 0 +-#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104 0x0390 0x0000 2 0 +-#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104 0x0390 0x063c 2 2 +-#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0600 3 0 +-#define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390 0x0000 4 0 +-#define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390 0x0000 5 0 +-#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB 0x0104 0x0390 0x0000 8 0 +-#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x0108 0x0394 0x0000 0 0 +-#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E 0x0108 0x0394 0x0000 1 0 +-#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x0108 0x0394 0x063c 2 3 +-#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0x0108 0x0394 0x0000 2 0 +-#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC 0x0108 0x0394 0x060c 3 0 +-#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B 0x0108 0x0394 0x0000 4 0 +-#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x0108 0x0394 0x0000 5 0 +-#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY 0x0108 0x0394 0x0000 8 0 +-#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x010c 0x0398 0x05dc 0 0 +-#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS 0x010c 0x0398 0x0000 1 0 +-#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x010c 0x0398 0x0000 2 0 +-#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS 0x010c 0x0398 0x0638 2 2 +-#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK 0x010c 0x0398 0x0608 3 0 +-#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB 0x010c 0x0398 0x0000 4 0 +-#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x010c 0x0398 0x0000 5 0 +-#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1 0x010c 0x0398 0x0000 8 0 +-#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x0110 0x039c 0x0000 0 0 +-#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110 0x039c 0x05dc 1 1 +-#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110 0x039c 0x0638 2 3 +-#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110 0x039c 0x0000 2 0 +-#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0604 3 0 +-#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110 0x039c 0x0000 4 0 +-#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110 0x039c 0x0000 5 0 +-#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110 0x039c 0x0000 8 0 +-#define MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x0114 0x03a0 0x0000 0 0 +-#define MX6UL_PAD_LCD_RESET__LCDIF_CS 0x0114 0x03a0 0x0000 1 0 +-#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI 0x0114 0x03a0 0x0000 2 0 +-#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA 0x0114 0x03a0 0x0000 3 0 +-#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x0114 0x03a0 0x0000 4 0 +-#define MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0114 0x03a0 0x0000 5 0 +-#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114 0x03a0 0x0000 8 0 +-#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03a4 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03a4 0x0000 1 0 +-#define MX6UL_PAD_LCD_DATA00__CA7_MX6UL_TRACE0 0x0118 0x03a4 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118 0x03a4 0x0000 3 0 +-#define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03a4 0x05b8 4 2 +-#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03a4 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118 0x03a4 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x05e0 8 1 +-#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011c 0x03a8 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011c 0x03a8 0x0000 1 0 +-#define MX6UL_PAD_LCD_DATA01__CA7_MX6UL_TRACE1 0x011c 0x03a8 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011c 0x03a8 0x0000 3 0 +-#define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011c 0x03a8 0x05b4 4 2 +-#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011c 0x03a8 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01 0x011c 0x03a8 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011c 0x03a8 0x05ec 8 0 +-#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03ac 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03ac 0x0000 1 0 +-#define MX6UL_PAD_LCD_DATA02__CA7_MX6UL_TRACE2 0x0120 0x03ac 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120 0x03ac 0x0000 3 0 +-#define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03ac 0x05c0 4 2 +-#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03ac 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02 0x0120 0x03ac 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03ac 0x05e8 8 0 +-#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03b0 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03b0 0x0000 1 0 +-#define MX6UL_PAD_LCD_DATA03__CA7_MX6UL_TRACE3 0x0124 0x03b0 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124 0x03b0 0x0000 3 0 +-#define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03b0 0x05bc 4 2 +-#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03b0 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124 0x03b0 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x05e4 8 0 +-#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03b4 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128 0x03b4 0x0000 1 0 +-#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128 0x03b4 0x0658 1 2 +-#define MX6UL_PAD_LCD_DATA04__CA7_MX6UL_TRACE4 0x0128 0x03b4 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128 0x03b4 0x0000 3 0 +-#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03b4 0x0000 4 0 +-#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03b4 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04 0x0128 0x03b4 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA 0x0128 0x03b4 0x0000 8 0 +-#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012c 0x03b8 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012c 0x03b8 0x0658 1 3 +-#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012c 0x03b8 0x0000 1 0 +-#define MX6UL_PAD_LCD_DATA05__CA7_MX6UL_TRACE5 0x012c 0x03b8 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012c 0x03b8 0x0000 3 0 +-#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012c 0x03b8 0x0000 4 0 +-#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012c 0x03b8 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05 0x012c 0x03b8 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1 0x012c 0x03b8 0x0000 8 0 +-#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03bc 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130 0x03bc 0x0000 1 0 +-#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130 0x03bc 0x0650 1 2 +-#define MX6UL_PAD_LCD_DATA06__CA7_MX6UL_TRACE6 0x0130 0x03bc 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130 0x03bc 0x0000 3 0 +-#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03bc 0x0000 4 0 +-#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03bc 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06 0x0130 0x03bc 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2 0x0130 0x03bc 0x0000 8 0 +-#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03c0 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134 0x03c0 0x0650 1 3 +-#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134 0x03c0 0x0000 1 0 +-#define MX6UL_PAD_LCD_DATA07__CA7_MX6UL_TRACE7 0x0134 0x03c0 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134 0x03c0 0x0000 3 0 +-#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134 0x03c0 0x061c 4 0 +-#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03c0 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07 0x0134 0x03c0 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03c0 0x0000 8 0 +-#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03c4 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03c4 0x0618 1 2 +-#define MX6UL_PAD_LCD_DATA08__CA7_MX6UL_TRACE8 0x0138 0x03c4 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0504 3 1 +-#define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03c4 0x0000 4 0 +-#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03c4 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138 0x03c4 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03c4 0x0000 8 0 +-#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013c 0x03c8 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0600 1 1 +-#define MX6UL_PAD_LCD_DATA09__CA7_MX6UL_TRACE9 0x013c 0x03c8 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0508 3 1 +-#define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013c 0x03c8 0x0000 4 0 +-#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013c 0x03c8 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013c 0x03c8 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013c 0x03c8 0x0584 8 2 +-#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03cc 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140 0x03cc 0x0000 1 0 +-#define MX6UL_PAD_LCD_DATA10__CA7_MX6UL_TRACE10 0x0140 0x03cc 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x050c 3 1 +-#define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03cc 0x0000 4 0 +-#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03cc 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140 0x03cc 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03cc 0x0000 8 0 +-#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03d0 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03d0 0x0000 1 0 +-#define MX6UL_PAD_LCD_DATA11__CA7_MX6UL_TRACE11 0x0144 0x03d0 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0510 3 1 +-#define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03d0 0x0000 4 0 +-#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03d0 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144 0x03d0 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03d0 0x0588 8 2 +-#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03d4 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148 0x03d4 0x060c 1 1 +-#define MX6UL_PAD_LCD_DATA12__CA7_MX6UL_TRACE12 0x0148 0x03d4 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0514 3 1 +-#define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03d4 0x0000 4 0 +-#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03d4 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148 0x03d4 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03d4 0x0000 8 0 +-#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014c 0x03d8 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014c 0x03d8 0x0608 1 1 +-#define MX6UL_PAD_LCD_DATA13__CA7_MX6UL_TRACE13 0x014c 0x03d8 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0518 3 1 +-#define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014c 0x03d8 0x0000 4 0 +-#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014c 0x03d8 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014c 0x03d8 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014c 0x03d8 0x0000 8 0 +-#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03dc 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0604 1 1 +-#define MX6UL_PAD_LCD_DATA14__CA7_MX6UL_TRACE14 0x0150 0x03dc 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x051c 3 1 +-#define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03dc 0x0000 4 0 +-#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03dc 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150 0x03dc 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150 0x03dc 0x068c 8 0 +-#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03e0 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03e0 0x0000 1 0 +-#define MX6UL_PAD_LCD_DATA15__CA7_MX6UL_TRACE15 0x0154 0x03e0 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0520 3 1 +-#define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03e0 0x0000 4 0 +-#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03e0 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154 0x03e0 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5 0x0154 0x03e0 0x0690 8 0 +-#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03e4 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158 0x03e4 0x0000 1 0 +-#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158 0x03e4 0x0654 1 2 +-#define MX6UL_PAD_LCD_DATA16__CA7_MX6UL_TRACE_CLK 0x0158 0x03e4 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x04d4 3 1 +-#define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03e4 0x0000 4 0 +-#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03e4 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158 0x03e4 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6 0x0158 0x03e4 0x0694 8 0 +-#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015c 0x03e8 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015c 0x03e8 0x0654 1 3 +-#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015c 0x03e8 0x0000 1 0 +-#define MX6UL_PAD_LCD_DATA17__CA7_MX6UL_TRACE_CTL 0x015c 0x03e8 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x04d0 3 1 +-#define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015c 0x03e8 0x0000 4 0 +-#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015c 0x03e8 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015c 0x03e8 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7 0x015c 0x03e8 0x0698 8 0 +-#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03ec 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160 0x03ec 0x0000 1 0 +-#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160 0x03ec 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x04ec 3 1 +-#define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03ec 0x0000 4 0 +-#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03ec 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160 0x03ec 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x0160 0x03ec 0x0678 8 1 +-#define MX6UL_PAD_LCD_DATA19__EIM_DATA11 0x0164 0x03f0 0x0000 4 0 +-#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x0164 0x03f0 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27 0x0164 0x03f0 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x0164 0x03f0 0x0670 8 1 +-#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03f0 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03f0 0x0000 1 0 +-#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164 0x03f0 0x0000 2 0 +-#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x04f0 3 1 +-#define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03f4 0x0000 4 0 +-#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03f4 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03f4 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x0168 0x03f4 0x067c 8 1 +-#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x0168 0x03f4 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03f4 0x0000 1 0 +-#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03f4 0x065c 1 2 +-#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03f4 0x0534 2 0 +-#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x04f4 3 1 +-#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016c 0x03f8 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016c 0x03f8 0x065c 1 3 +-#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016c 0x03f8 0x0000 1 0 +-#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0540 2 0 +-#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x04f8 3 1 +-#define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016c 0x03f8 0x0000 4 0 +-#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016c 0x03f8 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016c 0x03f8 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x016c 0x03f8 0x0680 8 1 +-#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03fc 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03fc 0x0000 1 0 +-#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03fc 0x053c 2 0 +-#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x04fc 3 1 +-#define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03fc 0x0000 4 0 +-#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03fc 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03fc 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x0170 0x03fc 0x0684 8 0 +-#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400 0x0000 0 0 +-#define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174 0x0400 0x0000 1 0 +-#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400 0x0538 2 0 +-#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0500 3 1 +-#define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400 0x0000 4 0 +-#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400 0x0000 5 0 +-#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174 0x0400 0x0000 6 0 +-#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x0174 0x0400 0x0688 8 1 +-#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178 0x0404 0x0000 0 0 +-#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178 0x0404 0x0670 1 2 +-#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404 0x0000 2 0 +-#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x05d0 3 1 +-#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178 0x0404 0x0000 4 0 +-#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178 0x0404 0x0000 5 0 +-#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178 0x0404 0x0000 8 0 +-#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017c 0x0408 0x0000 0 0 +-#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017c 0x0408 0x0678 1 2 +-#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017c 0x0408 0x0000 2 0 +-#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x05c4 3 1 +-#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017c 0x0408 0x0000 4 0 +-#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017c 0x0408 0x0000 5 0 +-#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017c 0x0408 0x0000 8 0 +-#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180 0x040c 0x0000 0 0 +-#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180 0x040c 0x067c 1 2 +-#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180 0x040c 0x0000 2 0 +-#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x05d4 3 1 +-#define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180 0x040c 0x0000 4 0 +-#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180 0x040c 0x0000 5 0 +-#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040c 0x0000 8 0 +-#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184 0x0410 0x0000 0 0 +-#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184 0x0410 0x0680 1 2 +-#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184 0x0410 0x0000 2 0 +-#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x05c8 3 1 +-#define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184 0x0410 0x0000 4 0 +-#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184 0x0410 0x0000 5 0 +-#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410 0x0000 8 0 +-#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188 0x0414 0x0000 0 0 +-#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188 0x0414 0x0684 1 1 +-#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188 0x0414 0x0000 2 0 +-#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x05d8 3 1 +-#define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188 0x0414 0x0000 4 0 +-#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188 0x0414 0x0000 5 0 +-#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414 0x0000 8 0 +-#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018c 0x0418 0x0000 0 0 +-#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018c 0x0418 0x0688 1 2 +-#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018c 0x0418 0x0000 2 0 +-#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x05cc 3 1 +-#define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018c 0x0418 0x0000 4 0 +-#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018c 0x0418 0x0000 5 0 +-#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018c 0x0418 0x0000 8 0 +-#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0190 0x041c 0x0000 0 0 +-#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x0190 0x041c 0x068c 1 1 +-#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x0190 0x041c 0x0000 2 0 +-#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x0190 0x041c 0x0564 3 1 +-#define MX6UL_PAD_NAND_DATA04__EIM_AD12 0x0190 0x041c 0x0000 4 0 +-#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x0190 0x041c 0x0000 5 0 +-#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x0190 0x041c 0x0000 8 0 +-#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX 0x0190 0x041c 0x062c 8 2 +-#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0194 0x0420 0x0000 0 0 +-#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x0194 0x0420 0x0690 1 1 +-#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x0194 0x0420 0x0000 2 0 +-#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x0194 0x0420 0x056c 3 1 +-#define MX6UL_PAD_NAND_DATA05__EIM_AD13 0x0194 0x0420 0x0000 4 0 +-#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07 0x0194 0x0420 0x0000 5 0 +-#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x0194 0x0420 0x062c 8 3 +-#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX 0x0194 0x0420 0x0000 8 0 +-#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0198 0x0424 0x0000 0 0 +-#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x0198 0x0424 0x0694 1 1 +-#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK 0x0198 0x0424 0x0000 2 0 +-#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x0198 0x0424 0x0568 3 1 +-#define MX6UL_PAD_NAND_DATA06__EIM_AD14 0x0198 0x0424 0x0000 4 0 +-#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x0198 0x0424 0x0000 5 0 +-#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x0198 0x0424 0x0000 8 0 +-#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS 0x0198 0x0424 0x0628 8 4 +-#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019c 0x0428 0x0000 0 0 +-#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019c 0x0428 0x0698 1 1 +-#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019c 0x0428 0x0000 2 0 +-#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0570 3 1 +-#define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019c 0x0428 0x0000 4 0 +-#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019c 0x0428 0x0000 5 0 +-#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019c 0x0428 0x0628 8 5 +-#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS 0x019c 0x0428 0x0000 8 0 +-#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x01a0 0x042c 0x0000 0 0 +-#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x01a0 0x042c 0x0000 1 0 +-#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS 0x01a0 0x042c 0x0000 2 0 +-#define MX6UL_PAD_NAND_ALE__PWM3_OUT 0x01a0 0x042c 0x0000 3 0 +-#define MX6UL_PAD_NAND_ALE__EIM_ADDR17 0x01a0 0x042c 0x0000 4 0 +-#define MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x01a0 0x042c 0x0000 5 0 +-#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1 0x01a0 0x042c 0x0000 8 0 +-#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x01a4 0x0430 0x0000 0 0 +-#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x01a4 0x0430 0x0000 1 0 +-#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x01a4 0x0430 0x0000 2 0 +-#define MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x01a4 0x0430 0x0000 3 0 +-#define MX6UL_PAD_NAND_WP_B__EIM_BCLK 0x01a4 0x0430 0x0000 4 0 +-#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x01a4 0x0430 0x0000 5 0 +-#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY 0x01a4 0x0430 0x0000 8 0 +-#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x01a8 0x0434 0x0000 0 0 +-#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01a8 0x0434 0x0000 1 0 +-#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01a8 0x0434 0x0000 2 0 +-#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0560 3 1 +-#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01a8 0x0434 0x0000 4 0 +-#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01a8 0x0434 0x0000 5 0 +-#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01a8 0x0434 0x0000 8 0 +-#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX 0x01a8 0x0434 0x0634 8 2 +-#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x01ac 0x0438 0x0000 0 0 +-#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x01ac 0x0438 0x0000 1 0 +-#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x01ac 0x0438 0x0000 2 0 +-#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x01ac 0x0438 0x0554 3 1 +-#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B 0x01ac 0x0438 0x0000 4 0 +-#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x01ac 0x0438 0x0000 5 0 +-#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x01ac 0x0438 0x0634 8 3 +-#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX 0x01ac 0x0438 0x0000 8 0 +-#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x01b0 0x043c 0x0000 0 0 +-#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x01b0 0x043c 0x0000 1 0 +-#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x01b0 0x043c 0x0000 2 0 +-#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x01b0 0x043c 0x055c 3 1 +-#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18 0x01b0 0x043c 0x0000 4 0 +-#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x01b0 0x043c 0x0000 5 0 +-#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS 0x01b0 0x043c 0x0000 8 0 +-#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS 0x01b0 0x043c 0x0630 8 2 +-#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x01b4 0x0440 0x0000 0 0 +-#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x01b4 0x0440 0x0000 1 0 +-#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x01b4 0x0440 0x0000 2 0 +-#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x01b4 0x0440 0x0558 3 1 +-#define MX6UL_PAD_NAND_CLE__EIM_ADDR16 0x01b4 0x0440 0x0000 4 0 +-#define MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x01b4 0x0440 0x0000 5 0 +-#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS 0x01b4 0x0440 0x0630 8 3 +-#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS 0x01b4 0x0440 0x0000 8 0 +-#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x01b8 0x0444 0x0000 0 0 +-#define MX6UL_PAD_NAND_DQS__CSI_FIELD 0x01b8 0x0444 0x0530 1 1 +-#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x01b8 0x0444 0x0000 2 0 +-#define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01b8 0x0444 0x0000 3 0 +-#define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01b8 0x0444 0x0000 4 0 +-#define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01b8 0x0444 0x0000 5 0 +-#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0614 6 1 +-#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01b8 0x0444 0x061c 8 1 +-#define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01bc 0x0448 0x0000 0 0 +-#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01bc 0x0448 0x0000 1 0 +-#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC 0x01bc 0x0448 0x0000 2 0 +-#define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01bc 0x0448 0x0000 3 0 +-#define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01bc 0x0448 0x0000 4 0 +-#define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01bc 0x0448 0x0000 5 0 +-#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0610 6 2 +-#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01bc 0x0448 0x0000 8 0 +-#define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01c0 0x044c 0x0000 0 0 +-#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01c0 0x044c 0x0000 1 0 +-#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x05f0 2 1 +-#define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01c0 0x044c 0x0618 3 3 +-#define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01c0 0x044c 0x0000 4 0 +-#define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01c0 0x044c 0x0000 5 0 +-#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x01c0 0x044c 0x0664 8 2 +-#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x01c4 0x0450 0x0000 0 0 +-#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3 0x01c4 0x0450 0x0000 1 0 +-#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x01c4 0x0450 0x05fc 2 1 +-#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX 0x01c4 0x0450 0x0000 3 0 +-#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21 0x01c4 0x0450 0x0000 4 0 +-#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x01c4 0x0450 0x0000 5 0 +-#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x01c4 0x0450 0x04b8 8 2 +-#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x01c8 0x0454 0x0000 0 0 +-#define MX6UL_PAD_SD1_DATA1__GPT2_CLK 0x01c8 0x0454 0x05a0 1 1 +-#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x01c8 0x0454 0x05f8 2 1 +-#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX 0x01c8 0x0454 0x0584 3 3 +-#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22 0x01c8 0x0454 0x0000 4 0 +-#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x01c8 0x0454 0x0000 5 0 +-#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR 0x01c8 0x0454 0x0000 8 0 +-#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x01cc 0x0458 0x0000 0 0 +-#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1 0x01cc 0x0458 0x0598 1 1 +-#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x01cc 0x0458 0x05f4 2 1 +-#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX 0x01cc 0x0458 0x0000 3 0 +-#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23 0x01cc 0x0458 0x0000 4 0 +-#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x01cc 0x0458 0x0000 5 0 +-#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1 0x01cc 0x0458 0x0000 6 0 +-#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC 0x01cc 0x0458 0x0660 8 2 +-#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x01d0 0x045c 0x0000 0 0 +-#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2 0x01d0 0x045c 0x059c 1 1 +-#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x01d0 0x045c 0x0000 2 0 +-#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX 0x01d0 0x045c 0x0588 3 3 +-#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24 0x01d0 0x045c 0x0000 4 0 +-#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x01d0 0x045c 0x0000 5 0 +-#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2 0x01d0 0x045c 0x0000 6 0 +-#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID 0x01d0 0x045c 0x04bc 8 2 +-#define MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x01d4 0x0460 0x0000 0 0 +-#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B 0x01d4 0x0460 0x0674 1 0 +-#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B 0x01d4 0x0460 0x0000 2 0 +-#define MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x01d4 0x0460 0x05a8 3 0 +-#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B 0x01d4 0x0460 0x0000 4 0 +-#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x01d4 0x0460 0x0000 5 0 +-#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL 0x01d4 0x0460 0x0000 6 0 +-#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x01d4 0x0460 0x0000 8 0 +-#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x01d4 0x0460 0x064c 8 0 +-#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x01d8 0x0464 0x0528 0 1 +-#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP 0x01d8 0x0464 0x069c 1 2 +-#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B 0x01d8 0x0464 0x0000 2 0 +-#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x01d8 0x0464 0x05a4 3 2 +-#define MX6UL_PAD_CSI_PIXCLK__EIM_OE 0x01d8 0x0464 0x0000 4 0 +-#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x01d8 0x0464 0x0000 5 0 +-#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 0x01d8 0x0464 0x0000 6 0 +-#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x01d8 0x0464 0x064c 8 3 +-#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x01d8 0x0464 0x0000 8 0 +-#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x01dc 0x0468 0x052c 0 0 +-#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x01dc 0x0468 0x0670 1 0 +-#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK 0x01dc 0x0468 0x0000 2 0 +-#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x01dc 0x0468 0x05b0 3 0 +-#define MX6UL_PAD_CSI_VSYNC__EIM_RW 0x01dc 0x0468 0x0000 4 0 +-#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x01dc 0x0468 0x0000 5 0 +-#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x01dc 0x0468 0x0000 6 0 +-#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x01dc 0x0468 0x0648 8 0 +-#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x01dc 0x0468 0x0000 8 0 +-#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x01e0 0x046c 0x0524 0 0 +-#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x01e0 0x046c 0x0678 1 0 +-#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD 0x01e0 0x046c 0x0000 2 0 +-#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x01e0 0x046c 0x05ac 3 0 +-#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B 0x01e0 0x046c 0x0000 4 0 +-#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x01e0 0x046c 0x0000 5 0 +-#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x01e0 0x046c 0x0000 6 0 +-#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x01e0 0x046c 0x0000 8 0 +-#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x01e0 0x046c 0x0648 8 1 +-#define MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x01e4 0x0470 0x04c4 0 0 +-#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x01e4 0x0470 0x067c 1 0 +-#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B 0x01e4 0x0470 0x0000 2 0 +-#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x01e4 0x0470 0x0544 3 0 +-#define MX6UL_PAD_CSI_DATA00__EIM_AD00 0x01e4 0x0470 0x0000 4 0 +-#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x01e4 0x0470 0x0000 5 0 +-#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT 0x01e4 0x0470 0x0000 6 0 +-#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x01e4 0x0470 0x0000 8 0 +-#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX 0x01e4 0x0470 0x0644 8 0 +-#define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01e8 0x0474 0x04c8 0 0 +-#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01e8 0x0474 0x0680 1 0 +-#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01e8 0x0474 0x0000 2 0 +-#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0550 3 0 +-#define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01e8 0x0474 0x0000 4 0 +-#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01e8 0x0474 0x0000 5 0 +-#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x05e0 6 0 +-#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01e8 0x0474 0x0644 8 1 +-#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01e8 0x0474 0x0000 8 0 +-#define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01ec 0x0478 0x04d8 0 1 +-#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x01ec 0x0478 0x0684 1 2 +-#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD 0x01ec 0x0478 0x0000 2 0 +-#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x01ec 0x0478 0x054c 3 1 +-#define MX6UL_PAD_CSI_DATA02__EIM_AD02 0x01ec 0x0478 0x0000 4 0 +-#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x01ec 0x0478 0x0000 5 0 +-#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x01ec 0x0478 0x0000 6 0 +-#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01ec 0x0478 0x0640 8 5 +-#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS 0x01ec 0x0478 0x0000 8 0 +-#define MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x01f0 0x047c 0x04cc 0 0 +-#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x01f0 0x047c 0x0688 1 0 +-#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0x01f0 0x047c 0x0000 2 0 +-#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x01f0 0x047c 0x0548 3 0 +-#define MX6UL_PAD_CSI_DATA03__EIM_AD03 0x01f0 0x047c 0x0000 4 0 +-#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x01f0 0x047c 0x0000 5 0 +-#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x01f0 0x047c 0x0000 6 0 +-#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS 0x01f0 0x047c 0x0000 8 0 +-#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS 0x01f0 0x047c 0x0640 8 0 +-#define MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x01f4 0x0480 0x04dc 0 1 +-#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4 0x01f4 0x0480 0x068c 1 2 +-#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x01f4 0x0480 0x0000 2 0 +-#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x01f4 0x0480 0x0534 3 1 +-#define MX6UL_PAD_CSI_DATA04__EIM_AD04 0x01f4 0x0480 0x0000 4 0 +-#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x01f4 0x0480 0x0000 5 0 +-#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x01f4 0x0480 0x05ec 6 1 +-#define MX6UL_PAD_CSI_DATA04__USDHC1_WP 0x01f4 0x0480 0x066c 8 2 +-#define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01f8 0x0484 0x04e0 0 1 +-#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01f8 0x0484 0x0690 1 2 +-#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01f8 0x0484 0x0000 2 0 +-#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0540 3 1 +-#define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01f8 0x0484 0x0000 4 0 +-#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01f8 0x0484 0x0000 5 0 +-#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01f8 0x0484 0x05e8 6 1 +-#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B 0x01f8 0x0484 0x0668 8 2 +-#define MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x01fc 0x0488 0x04e4 0 1 +-#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6 0x01fc 0x0488 0x0694 1 2 +-#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0x01fc 0x0488 0x0000 2 0 +-#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01fc 0x0488 0x053c 3 1 +-#define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01fc 0x0488 0x0000 4 0 +-#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01fc 0x0488 0x0000 5 0 +-#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x05e4 6 1 +-#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01fc 0x0488 0x0000 8 0 +-#define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048c 0x04e8 0 1 +-#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200 0x048c 0x0698 1 2 +-#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0x0200 0x048c 0x0000 2 0 +-#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0200 0x048c 0x0538 3 1 +-#define MX6UL_PAD_CSI_DATA07__EIM_AD07 0x0200 0x048c 0x0000 4 0 +-#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0200 0x048c 0x0000 5 0 +-#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x0200 0x048c 0x0000 6 0 +-#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT 0x0200 0x048c 0x0000 8 0 +- +-#endif /* __DTS_IMX6UL_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-prti6g.dts b/scripts/dtc/include-prefixes/arm/imx6ul-prti6g.dts +deleted file mode 100644 +index d62015701d0a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-prti6g.dts ++++ /dev/null +@@ -1,356 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Copyright (c) 2016 Protonic Holland +- * Copyright (c) 2020 Oleksij Rempel , Pengutronix +- */ +- +-/dts-v1/; +-#include "imx6ul.dtsi" +-#include +- +-/ { +- model = "Protonic PRTI6G Board"; +- compatible = "prt,prti6g", "fsl,imx6ul"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- clock_ksz8081_in: clock-ksz8081-in { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- clock_ksz8081_out: clock-ksz8081-out { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds>; +- +- led-0 { +- label = "debug0"; +- gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- reg_3v2: regulator-3v2 { +- compatible = "regulator-fixed"; +- regulator-name = "3v2"; +- regulator-min-microvolt = <3200000>; +- regulator-max-microvolt = <3200000>; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can2>; +- status = "okay"; +-}; +- +-&ecspi1 { +- cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- }; +-}; +- +-&ecspi2 { +- cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- status = "okay"; +- +- spi@0 { +- compatible = "spidev"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_eth1>; +- phy-mode = "rmii"; +- phy-handle = <&rmii_phy>; +- clocks = <&clks IMX6UL_CLK_ENET>, +- <&clks IMX6UL_CLK_ENET_AHB>, +- <&clks IMX6UL_CLK_ENET_PTP>, +- <&clock_ksz8081_out>; +- clock-names = "ipg", "ahb", "ptp", +- "enet_clk_ref"; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Microchip KSZ8081RNA PHY */ +- rmii_phy: ethernet-phy@0 { +- reg = <0>; +- interrupts-extended = <&gpio5 1 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- reset-deassert-us = <300>; +- clocks = <&clock_ksz8081_in>; +- clock-names = "rmii-ref"; +- }; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clock-frequency = <100000>; +- status = "okay"; +- +- /* additional i2c devices are added automatically by the boot loader */ +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clock-frequency = <100000>; +- status = "okay"; +- +- adc@49 { +- compatible = "ti,ads1015"; +- reg = <0x49>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@4 { +- reg = <4>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- +- channel@5 { +- reg = <5>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- +- channel@6 { +- reg = <6>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- +- channel@7 { +- reg = <7>; +- ti,gain = <3>; +- ti,datarate = <3>; +- }; +- }; +- +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- +- temperature-sensor@70 { +- compatible = "ti,tmp103"; +- reg = <0x70>; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usbotg1 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3v2>; +- no-1-8-v; +- disable-wp; +- cap-sd-highspeed; +- no-mmc; +- no-sdio; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- no-sd; +- no-sdio; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_can1: can1grp { +- fsl,pins = < +- MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 +- MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 +- /* SR */ +- MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 +- /* TERM */ +- MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 +- /* nSMBALERT */ +- MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0 +- >; +- }; +- +- pinctrl_can2: can2grp { +- fsl,pins = < +- MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 +- MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 +- /* SR */ +- MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x0b0b0 +- MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x000b1 +- MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x0b0b0 +- MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0b0b0 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x0b0b0 +- MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x000b1 +- MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x0b0b0 +- MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x0b0b0 +- >; +- }; +- +- pinctrl_eth1: eth1grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 +- MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x100b0 +- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x100b0 +- MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 +- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x1b000 +- /* PHY ENET1_RST */ +- MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x00880 +- /* PHY ENET1_IRQ */ +- MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x00880 +- >; +- }; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- /* HW revision detect */ +- /* REV_ID0 */ +- MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 +- /* REV_ID1 */ +- MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0 +- /* REV_ID2 */ +- MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 +- /* REV_ID3 */ +- MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0 +- /* BOARD_ID0 */ +- MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 +- /* BOARD_ID1 */ +- MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0 +- /* BOARD_ID2 */ +- MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 +- /* BOARD_ID3 */ +- MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0 +- /* Safety controller IO */ +- /* WAKE_SC */ +- MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 +- /* PROGRAM_SC */ +- MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 +- MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0 +- MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0 +- >; +- }; +- +- pinctrl_leds: ledsgrp { +- fsl,pins = < +- MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1 +- /* SD1 CD */ +- MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x170b0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 +- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 +- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 +- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 +- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 +- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 +- MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 +- MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 +- MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 +- MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 +- MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-tx6ul-0010.dts b/scripts/dtc/include-prefixes/arm/imx6ul-tx6ul-0010.dts +deleted file mode 100644 +index 8c2f3df79b47..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-tx6ul-0010.dts ++++ /dev/null +@@ -1,53 +0,0 @@ +-/* +- * Copyright 2015 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6ul.dtsi" +-#include "imx6ul-tx6ul.dtsi" +- +-/ { +- model = "Ka-Ro electronics TXUL-0010 Module"; +- compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul"; +- +- aliases { +- /delete-property/ mmc1; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-tx6ul-0011.dts b/scripts/dtc/include-prefixes/arm/imx6ul-tx6ul-0011.dts +deleted file mode 100644 +index d82698e7d50f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-tx6ul-0011.dts ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * Copyright 2015 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6ul.dtsi" +-#include "imx6ul-tx6ul.dtsi" +- +-/ { +- model = "Ka-Ro electronics TXUL-0011 Module"; +- compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul"; +- +- aliases { +- mmc0 = &usdhc2; +- mmc1 = &usdhc1; +- }; +-}; +- +-&gpmi { +- status = "disabled"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- no-1-8-v; +- non-removable; +- fsl,wp-controller; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-tx6ul-mainboard.dts b/scripts/dtc/include-prefixes/arm/imx6ul-tx6ul-mainboard.dts +deleted file mode 100644 +index 97686097a86e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-tx6ul-mainboard.dts ++++ /dev/null +@@ -1,271 +0,0 @@ +-/* +- * Copyright 2015 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "imx6ul.dtsi" +-#include "imx6ul-tx6ul.dtsi" +- +-/ { +- model = "Ka-Ro electronics TXUL-0010 Module on TXUL Mainboard"; +- compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul"; +- +- aliases { +- lcdif-24bit-pins-a = &pinctrl_disp0_3; +- mmc0 = &usdhc1; +- /delete-property/ mmc1; +- serial2 = &uart3; +- serial4 = &uart5; +- }; +- /delete-node/ sound; +-}; +- +-&can1 { +- xceiver-supply = <®_3v3>; +-}; +- +-&can2 { +- xceiver-supply = <®_3v3>; +-}; +- +-&ds1339 { +- status = "disabled"; +-}; +- +-&fec1 { +- pinctrl-0 = <&pinctrl_enet1 &pinctrl_etnphy0_rst>; +- /delete-node/ mdio; +-}; +- +-&fec2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio &pinctrl_etnphy1_rst>; +- phy-mode = "rmii"; +- phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; +- phy-supply = <®_3v3_etn>; +- phy-handle = <&etnphy1>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- etnphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_etnphy0_int>; +- interrupt-parent = <&gpio5>; +- interrupts = <5 IRQ_TYPE_EDGE_FALLING>; +- interrupts-extended = <&gpio5 5 IRQ_TYPE_EDGE_FALLING>; +- status = "okay"; +- }; +- +- etnphy1: ethernet-phy@2 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_etnphy1_int>; +- interrupt-parent = <&gpio4>; +- interrupts = <27 IRQ_TYPE_EDGE_FALLING>; +- interrupts-extended = <&gpio4 27 IRQ_TYPE_EDGE_FALLING>; +- status = "okay"; +- }; +- }; +-}; +- +-&i2c_gpio { +- status = "disabled"; +-}; +- +-&i2c2 { +- /delete-node/ codec@a; +- /delete-node/ touchscreen@48; +- +- rtc: mcp7940x@6f { +- compatible = "microchip,mcp7940x"; +- reg = <0x6f>; +- }; +-}; +- +-&kpp { +- status = "disabled"; +-}; +- +-&lcdif { +- pinctrl-0 = <&pinctrl_disp0_3>; +-}; +- +-®_usbotg_vbus{ +- status = "disabled"; +-}; +- +-&usdhc1 { +- pinctrl-0 = <&pinctrl_usdhc1>; +- non-removable; +- /delete-property/ cd-gpios; +- cap-sdio-irq; +-}; +- +-&uart1 { +- pinctrl-0 = <&pinctrl_uart1>; +- /delete-property/ uart-has-rtscts; +-}; +- +-&uart2 { +- pinctrl-0 = <&pinctrl_uart2>; +- /delete-property/ uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- status = "okay"; +-}; +- +-&uart6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart6>; +- status = "okay"; +-}; +- +-&uart7 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart7>; +- status = "okay"; +-}; +- +-&uart8 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart8>; +- status = "disabled"; /* conflicts with LCDIF */ +-}; +- +-&iomuxc { +- hoggrp { +- fsl,pins = < +- MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x0b0b0 /* WLAN_RESET */ +- >; +- }; +- +- pinctrl_disp0_3: disp0grp-3 { +- fsl,pins = < +- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ +- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ +- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ +- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ +- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 +- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 +- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 +- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 +- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 +- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 +- /* LCD_DATA08..09 not wired */ +- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 +- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 +- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 +- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 +- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 +- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 +- /* LCD_DATA16..17 not wired */ +- MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 +- MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 +- MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 +- MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 +- MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 +- MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 +- >; +- }; +- +- pinctrl_enet2_mdio: enet2-mdiogrp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0b0b0 +- MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x0b0b0 +- MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x0b0b0 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x0b0b0 +- MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x0b0b0 +- >; +- }; +- +- pinctrl_uart6: uart6grp { +- fsl,pins = < +- MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x0b0b0 +- MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x0b0b0 +- >; +- }; +- +- pinctrl_uart7: uart7grp { +- fsl,pins = < +- MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0b0b0 +- MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x0b0b0 +- >; +- }; +- +- pinctrl_uart8: uart8grp { +- fsl,pins = < +- MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0b0b0 +- MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x0b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul-tx6ul.dtsi b/scripts/dtc/include-prefixes/arm/imx6ul-tx6ul.dtsi +deleted file mode 100644 +index 938a32ced88d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul-tx6ul.dtsi ++++ /dev/null +@@ -1,971 +0,0 @@ +-/* +- * Copyright 2015 Lothar Waßmann +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include +- +-/ { +- aliases { +- can0 = &can2; +- can1 = &can1; +- display = &display; +- i2c0 = &i2c2; +- i2c1 = &i2c_gpio; +- i2c2 = &i2c1; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- lcdif-23bit-pins-a = &pinctrl_disp0_1; +- lcdif-24bit-pins-a = &pinctrl_disp0_2; +- pwm0 = &pwm5; +- reg-can-xcvr = ®_can_xcvr; +- serial2 = &uart5; +- serial4 = &uart3; +- spi0 = &ecspi2; +- spi1 = &spi_gpio; +- stk5led = &user_led; +- usbh1 = &usbotg2; +- usbotg = &usbotg1; +- }; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0>; /* will be filled by U-Boot */ +- }; +- +- clocks { +- mclk: mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd_rst>; +- enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; +- pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>; +- power-supply = <®_lcd_pwr>; +- /* +- * a poor man's way to create a 1:1 relationship between +- * the PWM value and the actual duty cycle +- */ +- brightness-levels = < 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100>; +- default-brightness-level = <50>; +- }; +- +- i2c_gpio: i2c-gpio { +- compatible = "i2c-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c_gpio>; +- gpios = < +- &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */ +- &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */ +- >; +- clock-frequency = <400000>; +- status = "okay"; +- +- ds1339: rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- status = "disabled"; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- user_led: user { +- label = "Heartbeat"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led>; +- gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- reg_3v3_etn: regulator-3v3etn { +- compatible = "regulator-fixed"; +- regulator-name = "3V3_ETN"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_etnphy_power>; +- gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_2v5: regulator-2v5 { +- compatible = "regulator-fixed"; +- regulator-name = "2V5"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_can_xcvr: regulator-canxcvr { +- compatible = "regulator-fixed"; +- regulator-name = "CAN XCVR"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan_xcvr>; +- gpio = <&gpio3 5 GPIO_ACTIVE_LOW>; +- }; +- +- reg_lcd_pwr: regulator-lcdpwr { +- compatible = "regulator-fixed"; +- regulator-name = "LCD POWER"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd_pwr>; +- gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_usbh1_vbus: regulator-usbh1vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usbh1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>; +- gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usbotg_vbus: regulator-usbotgvbus { +- compatible = "regulator-fixed"; +- regulator-name = "usbotg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>; +- gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- spi_gpio: spi-gpio { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "spi-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi_gpio>; +- gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>; +- gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>; +- gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; +- num-chipselects = <2>; +- cs-gpios = < +- &gpio1 29 GPIO_ACTIVE_HIGH +- &gpio1 10 GPIO_ACTIVE_HIGH +- >; +- status = "disabled"; +- +- spi@0 { +- compatible = "spidev"; +- reg = <0>; +- spi-max-frequency = <660000>; +- }; +- +- spi@1 { +- compatible = "spidev"; +- reg = <1>; +- spi-max-frequency = <660000>; +- }; +- }; +- +- sound { +- compatible = "karo,imx6ul-tx6ul-sgtl5000", +- "simple-audio-card"; +- simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&codec_dai>; +- simple-audio-card,frame-master = <&codec_dai>; +- simple-audio-card,widgets = +- "Microphone", "Mic Jack", +- "Line", "Line In", +- "Line", "Line Out", +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- +- cpu_dai: simple-audio-card,cpu { +- sound-dai = <&sai2>; +- }; +- +- codec_dai: simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- }; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- xceiver-supply = <®_can_xcvr>; +- status = "okay"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- xceiver-supply = <®_can_xcvr>; +- status = "okay"; +-}; +- +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- cs-gpios = < +- &gpio1 29 GPIO_ACTIVE_HIGH +- &gpio1 10 GPIO_ACTIVE_HIGH +- >; +- status = "disabled"; +- +- spidev0: spi@0 { +- compatible = "spidev"; +- reg = <0>; +- spi-max-frequency = <60000000>; +- }; +- +- spidev1: spi@1 { +- compatible = "spidev"; +- reg = <1>; +- spi-max-frequency = <60000000>; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>; +- phy-mode = "rmii"; +- phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; +- phy-supply = <®_3v3_etn>; +- phy-handle = <&etnphy0>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- etnphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_etnphy0_int>; +- interrupt-parent = <&gpio5>; +- interrupts = <5 IRQ_TYPE_EDGE_FALLING>; +- status = "okay"; +- }; +- +- etnphy1: ethernet-phy@2 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_etnphy1_int>; +- interrupt-parent = <&gpio4>; +- interrupts = <27 IRQ_TYPE_EDGE_FALLING>; +- status = "okay"; +- }; +- }; +-}; +- +-&fec2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>; +- phy-mode = "rmii"; +- phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; +- phy-supply = <®_3v3_etn>; +- phy-handle = <&etnphy1>; +- status = "disabled"; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- nand-on-flash-bbt; +- fsl,no-blockmark-swap; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clock-frequency = <400000>; +- status = "okay"; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- VDDA-supply = <®_2v5>; +- VDDIO-supply = <®_3v3>; +- clocks = <&mclk>; +- }; +- +- polytouch: polytouch@38 { +- compatible = "edt,edt-ft5x06"; +- reg = <0x38>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_edt_ft5x06>; +- interrupt-parent = <&gpio5>; +- interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; +- wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; +- wakeup-source; +- }; +- +- touchscreen: touchscreen@48 { +- compatible = "ti,tsc2007"; +- reg = <0x48>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tsc2007>; +- interrupt-parent = <&gpio3>; +- interrupts = <26 IRQ_TYPE_NONE>; +- gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; +- ti,x-plate-ohms = <660>; +- wakeup-source; +- }; +-}; +- +-&kpp { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_kpp>; +- /* sample keymap */ +- /* row/col 0..3 are mapped to KPP row/col 4..7 */ +- linux,keymap = < +- MATRIX_KEY(4, 4, KEY_POWER) +- MATRIX_KEY(4, 5, KEY_KP0) +- MATRIX_KEY(4, 6, KEY_KP1) +- MATRIX_KEY(4, 7, KEY_KP2) +- MATRIX_KEY(5, 4, KEY_KP3) +- MATRIX_KEY(5, 5, KEY_KP4) +- MATRIX_KEY(5, 6, KEY_KP5) +- MATRIX_KEY(5, 7, KEY_KP6) +- MATRIX_KEY(6, 4, KEY_KP7) +- MATRIX_KEY(6, 5, KEY_KP8) +- MATRIX_KEY(6, 6, KEY_KP9) +- >; +- status = "okay"; +-}; +- +-&lcdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_disp0_1>; +- lcd-supply = <®_lcd_pwr>; +- display = <&display>; +- status = "okay"; +- +- display: disp0 { +- bits-per-pixel = <32>; +- bus-width = <24>; +- status = "okay"; +- +- display-timings { +- VGA { +- clock-frequency = <25200000>; +- hactive = <640>; +- vactive = <480>; +- hback-porch = <48>; +- hsync-len = <96>; +- hfront-porch = <16>; +- vback-porch = <31>; +- vsync-len = <2>; +- vfront-porch = <12>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- +- ETV570 { +- clock-frequency = <25200000>; +- hactive = <640>; +- vactive = <480>; +- hback-porch = <114>; +- hsync-len = <30>; +- hfront-porch = <16>; +- vback-porch = <32>; +- vsync-len = <3>; +- vfront-porch = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- +- ET0350 { +- clock-frequency = <6413760>; +- hactive = <320>; +- vactive = <240>; +- hback-porch = <34>; +- hsync-len = <34>; +- hfront-porch = <20>; +- vback-porch = <15>; +- vsync-len = <3>; +- vfront-porch = <4>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- +- ET0430 { +- clock-frequency = <9009000>; +- hactive = <480>; +- vactive = <272>; +- hback-porch = <2>; +- hsync-len = <41>; +- hfront-porch = <2>; +- vback-porch = <2>; +- vsync-len = <10>; +- vfront-porch = <2>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- +- ET0500 { +- clock-frequency = <33264000>; +- hactive = <800>; +- vactive = <480>; +- hback-porch = <88>; +- hsync-len = <128>; +- hfront-porch = <40>; +- vback-porch = <33>; +- vsync-len = <2>; +- vfront-porch = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- +- ET0700 { /* same as ET0500 */ +- clock-frequency = <33264000>; +- hactive = <800>; +- vactive = <480>; +- hback-porch = <88>; +- hsync-len = <128>; +- hfront-porch = <40>; +- vback-porch = <33>; +- vsync-len = <2>; +- vfront-porch = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- +- ETQ570 { +- clock-frequency = <6596040>; +- hactive = <320>; +- vactive = <240>; +- hback-porch = <38>; +- hsync-len = <30>; +- hfront-porch = <30>; +- vback-porch = <16>; +- vsync-len = <3>; +- vfront-porch = <4>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- }; +-}; +- +-&pwm5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm5>; +- status = "okay"; +-}; +- +-&sai2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai2>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbotg1 { +- vbus-supply = <®_usbotg_vbus>; +- dr_mode = "peripheral"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbotg2 { +- vbus-supply = <®_usbh1_vbus>; +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>; +- bus-width = <4>; +- no-1-8-v; +- cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; +- fsl,wp-controller; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- }; +- +- pinctrl_led: ledgrp { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0b0b0 /* LED */ +- >; +- }; +- +- pinctrl_disp0_1: disp0grp-1 { +- fsl,pins = < +- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ +- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ +- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ +- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ +- /* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */ +- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10 +- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 +- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 +- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 +- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 +- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 +- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 +- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10 +- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10 +- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 +- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 +- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 +- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 +- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 +- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 +- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10 +- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10 +- MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 +- MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 +- MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 +- MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 +- MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 +- MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 +- >; +- }; +- +- pinctrl_disp0_2: disp0grp-2 { +- fsl,pins = < +- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ +- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ +- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ +- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ +- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x10 +- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10 +- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 +- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 +- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 +- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 +- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 +- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 +- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10 +- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10 +- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 +- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 +- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 +- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 +- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 +- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 +- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10 +- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10 +- MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 +- MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 +- MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 +- MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 +- MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 +- MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */ +- MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */ +- MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x0b0b0 /* CSPI_MOSI */ +- MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x0b0b0 /* CSPI_MISO */ +- MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x0b0b0 /* CSPI_SCLK */ +- >; +- }; +- +- pinctrl_edt_ft5x06: edt-ft5x06grp { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* Interrupt */ +- MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* Reset */ +- MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Wake */ +- >; +- }; +- +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0 +- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0 +- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x000b0 +- MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x000b0 +- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x000b0 +- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0 +- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0 +- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1 +- >; +- }; +- +- pinctrl_enet2: enet2grp { +- fsl,pins = < +- MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0 +- MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0 +- MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x000b0 +- MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x000b0 +- MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x000b0 +- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0 +- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0 +- MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x400000b1 +- >; +- }; +- +- pinctrl_enet1_mdio: enet1-mdiogrp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0b0b0 +- MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 +- >; +- }; +- +- pinctrl_etnphy_power: etnphy-pwrgrp { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 /* ETN PHY POWER */ +- >; +- }; +- +- pinctrl_etnphy0_int: etnphy-intgrp-0 { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* ETN PHY INT */ +- >; +- }; +- +- pinctrl_etnphy0_rst: etnphy-rstgrp-0 { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 /* ETN PHY RESET */ +- >; +- }; +- +- pinctrl_etnphy1_int: etnphy-intgrp-1 { +- fsl,pins = < +- MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x0b0b0 /* ETN PHY INT */ +- >; +- }; +- +- pinctrl_etnphy1_rst: etnphy-rstgrp-1 { +- fsl,pins = < +- MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0b0b0 /* ETN PHY RESET */ +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 +- MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 +- MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 +- >; +- }; +- +- pinctrl_flexcan_xcvr: flexcan-xcvrgrp { +- fsl,pins = < +- MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0b0b0 /* Flexcan XCVR enable */ +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 +- MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 +- MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 +- MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 +- MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 +- MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 +- MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 +- MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 +- MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 +- MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 +- MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 +- MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 +- MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 +- MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 +- MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 +- >; +- }; +- +- pinctrl_i2c_gpio: i2c-gpiogrp { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x4001b8b1 /* I2C SCL */ +- MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x4001b8b1 /* I2C SDA */ +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b1 +- MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b1 +- >; +- }; +- +- pinctrl_kpp: kppgrp { +- fsl,pins = < +- MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x1b0b0 +- MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x1b0b0 +- MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x1b0b0 +- MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x1b0b0 +- MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x1b0b0 +- MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x1b0b0 +- MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x1b0b0 +- MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x1b0b0 +- >; +- }; +- +- pinctrl_lcd_pwr: lcd-pwrgrp { +- fsl,pins = < +- MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 /* LCD Power Enable */ +- >; +- }; +- +- pinctrl_lcd_rst: lcd-rstgrp { +- fsl,pins = < +- MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */ +- >; +- }; +- +- pinctrl_pwm5: pwm5grp { +- fsl,pins = < +- MX6UL_PAD_NAND_DQS__PWM5_OUT 0x0b0b0 +- >; +- }; +- +- pinctrl_sai2: sai2grp { +- fsl,pins = < +- MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0b0b0 /* SSI1_RXD */ +- MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0b0b0 /* SSI1_TXD */ +- MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0b0b0 /* SSI1_CLK */ +- MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x0b0b0 /* SSI1_FS */ +- >; +- }; +- +- pinctrl_spi_gpio: spi-gpiogrp { +- fsl,pins = < +- MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */ +- MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */ +- MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x0b0b0 /* CSPI_MOSI */ +- MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x0b0b0 /* CSPI_MISO */ +- MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x0b0b0 /* CSPI_SCLK */ +- >; +- }; +- +- pinctrl_tsc2007: tsc2007grp { +- fsl,pins = < +- MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b0b0 /* Interrupt */ +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0b0b0 +- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0b0b0 +- >; +- }; +- +- pinctrl_uart1_rtscts: uart1-rtsctsgrp { +- fsl,pins = < +- MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0b0b0 +- MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x0b0b0 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0b0b0 +- MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0b0b0 +- >; +- }; +- +- pinctrl_uart2_rtscts: uart2-rtsctsgrp { +- fsl,pins = < +- MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x0b0b0 +- MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x0b0b0 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x0b0b0 +- MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0b0b0 +- >; +- }; +- +- pinctrl_uart5_rtscts: uart5-rtsctsgrp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x0b0b0 +- MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0b0b0 +- >; +- }; +- +- pinctrl_usbh1_oc: usbh1-ocgrp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 /* USBH1_OC */ +- >; +- }; +- +- pinctrl_usbh1_vbus: usbh1-vbusgrp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0b0b0 /* USBH1_VBUSEN */ +- >; +- }; +- +- pinctrl_usbotg_oc: usbotg-ocgrp { +- fsl,pins = < +- MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x17059 /* USBOTG_OC */ +- >; +- }; +- +- pinctrl_usbotg_vbus: usbotg-vbusgrp { +- fsl,pins = < +- MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x1b0b0 /* USBOTG_VBUSEN */ +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1 +- >; +- }; +- +- pinctrl_usdhc1_cd: usdhc1cdgrp { +- fsl,pins = < +- MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x170b0 /* SD1 CD */ +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x070b1 +- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x070b1 +- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x070b1 +- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x070b1 +- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x070b1 +- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x070b1 +- /* eMMC RESET */ +- MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ul.dtsi b/scripts/dtc/include-prefixes/arm/imx6ul.dtsi +deleted file mode 100644 +index afeec01f6522..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ul.dtsi ++++ /dev/null +@@ -1,1115 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright 2015 Freescale Semiconductor, Inc. +- +-#include +-#include +-#include +-#include +-#include "imx6ul-pinfunc.h" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * The decompressor and also some bootloaders rely on a +- * pre-existing /chosen node to be available to insert the +- * command line and merge other ATAGS info. +- */ +- chosen {}; +- +- aliases { +- ethernet0 = &fec1; +- ethernet1 = &fec2; +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- gpio3 = &gpio4; +- gpio4 = &gpio5; +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- i2c3 = &i2c4; +- mmc0 = &usdhc1; +- mmc1 = &usdhc2; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- serial4 = &uart5; +- serial5 = &uart6; +- serial6 = &uart7; +- serial7 = &uart8; +- sai1 = &sai1; +- sai2 = &sai2; +- sai3 = &sai3; +- spi0 = &ecspi1; +- spi1 = &ecspi2; +- spi2 = &ecspi3; +- spi3 = &ecspi4; +- usb0 = &usbotg1; +- usb1 = &usbotg2; +- usbphy0 = &usbphy1; +- usbphy1 = &usbphy2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <0>; +- clock-frequency = <696000000>; +- clock-latency = <61036>; /* two CLK32 periods */ +- #cooling-cells = <2>; +- operating-points = < +- /* kHz uV */ +- 696000 1275000 +- 528000 1175000 +- 396000 1025000 +- 198000 950000 +- >; +- fsl,soc-operating-points = < +- /* KHz uV */ +- 696000 1275000 +- 528000 1175000 +- 396000 1175000 +- 198000 1175000 +- >; +- clocks = <&clks IMX6UL_CLK_ARM>, +- <&clks IMX6UL_CLK_PLL2_BUS>, +- <&clks IMX6UL_CLK_PLL2_PFD2>, +- <&clks IMX6UL_CA7_SECONDARY_SEL>, +- <&clks IMX6UL_CLK_STEP>, +- <&clks IMX6UL_CLK_PLL1_SW>, +- <&clks IMX6UL_CLK_PLL1_SYS>; +- clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", +- "secondary_sel", "step", "pll1_sw", +- "pll1_sys"; +- arm-supply = <®_arm>; +- soc-supply = <®_soc>; +- nvmem-cells = <&cpu_speed_grade>; +- nvmem-cell-names = "speed_grade"; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- interrupt-parent = <&intc>; +- status = "disabled"; +- }; +- +- ckil: clock-cli { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "ckil"; +- }; +- +- osc: clock-osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "osc"; +- }; +- +- ipp_di0: clock-di0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- clock-output-names = "ipp_di0"; +- }; +- +- ipp_di1: clock-di1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- clock-output-names = "ipp_di1"; +- }; +- +- pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupt-parent = <&gpc>; +- interrupts = ; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&gpc>; +- ranges; +- +- ocram: sram@900000 { +- compatible = "mmio-sram"; +- reg = <0x00900000 0x20000>; +- }; +- +- intc: interrupt-controller@a01000 { +- compatible = "arm,gic-400", "arm,cortex-a7-gic"; +- interrupts = ; +- #interrupt-cells = <3>; +- interrupt-controller; +- interrupt-parent = <&intc>; +- reg = <0x00a01000 0x1000>, +- <0x00a02000 0x2000>, +- <0x00a04000 0x2000>, +- <0x00a06000 0x2000>; +- }; +- +- dma_apbh: dma-apbh@1804000 { +- compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; +- reg = <0x01804000 0x2000>; +- interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, +- <0 13 IRQ_TYPE_LEVEL_HIGH>, +- <0 13 IRQ_TYPE_LEVEL_HIGH>, +- <0 13 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; +- #dma-cells = <1>; +- dma-channels = <4>; +- clocks = <&clks IMX6UL_CLK_APBHDMA>; +- }; +- +- gpmi: nand-controller@1806000 { +- compatible = "fsl,imx6q-gpmi-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x01806000 0x2000>, <0x01808000 0x2000>; +- reg-names = "gpmi-nand", "bch"; +- interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "bch"; +- clocks = <&clks IMX6UL_CLK_GPMI_IO>, +- <&clks IMX6UL_CLK_GPMI_APB>, +- <&clks IMX6UL_CLK_GPMI_BCH>, +- <&clks IMX6UL_CLK_GPMI_BCH_APB>, +- <&clks IMX6UL_CLK_PER_BCH>; +- clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", +- "gpmi_bch_apb", "per1_bch"; +- dmas = <&dma_apbh 0>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- aips1: bus@2000000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x02000000 0x100000>; +- ranges; +- +- spba-bus@2000000 { +- compatible = "fsl,spba-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x02000000 0x40000>; +- ranges; +- +- ecspi1: spi@2008000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; +- reg = <0x02008000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_ECSPI1>, +- <&clks IMX6UL_CLK_ECSPI1>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ecspi2: spi@200c000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; +- reg = <0x0200c000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_ECSPI2>, +- <&clks IMX6UL_CLK_ECSPI2>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ecspi3: spi@2010000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; +- reg = <0x02010000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_ECSPI3>, +- <&clks IMX6UL_CLK_ECSPI3>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ecspi4: spi@2014000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; +- reg = <0x02014000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_ECSPI4>, +- <&clks IMX6UL_CLK_ECSPI4>; +- clock-names = "ipg", "per"; +- dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart7: serial@2018000 { +- compatible = "fsl,imx6ul-uart", +- "fsl,imx6q-uart"; +- reg = <0x02018000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_UART7_IPG>, +- <&clks IMX6UL_CLK_UART7_SERIAL>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart1: serial@2020000 { +- compatible = "fsl,imx6ul-uart", +- "fsl,imx6q-uart"; +- reg = <0x02020000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_UART1_IPG>, +- <&clks IMX6UL_CLK_UART1_SERIAL>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart8: serial@2024000 { +- compatible = "fsl,imx6ul-uart", +- "fsl,imx6q-uart"; +- reg = <0x02024000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_UART8_IPG>, +- <&clks IMX6UL_CLK_UART8_SERIAL>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- sai1: sai@2028000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; +- reg = <0x02028000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_SAI1_IPG>, +- <&clks IMX6UL_CLK_SAI1>, +- <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dmas = <&sdma 35 24 0>, +- <&sdma 36 24 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sai2: sai@202c000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; +- reg = <0x0202c000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_SAI2_IPG>, +- <&clks IMX6UL_CLK_SAI2>, +- <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dmas = <&sdma 37 24 0>, +- <&sdma 38 24 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sai3: sai@2030000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; +- reg = <0x02030000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_SAI3_IPG>, +- <&clks IMX6UL_CLK_SAI3>, +- <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dmas = <&sdma 39 24 0>, +- <&sdma 40 24 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- asrc: asrc@2034000 { +- compatible = "fsl,imx6ul-asrc", "fsl,imx53-asrc"; +- reg = <0x2034000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_ASRC_IPG>, +- <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>, +- <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, +- <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, +- <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, +- <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>, +- <&clks IMX6UL_CLK_SPBA>; +- clock-names = "mem", "ipg", "asrck_0", +- "asrck_1", "asrck_2", "asrck_3", "asrck_4", +- "asrck_5", "asrck_6", "asrck_7", "asrck_8", +- "asrck_9", "asrck_a", "asrck_b", "asrck_c", +- "asrck_d", "asrck_e", "asrck_f", "spba"; +- dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, +- <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; +- dma-names = "rxa", "rxb", "rxc", +- "txa", "txb", "txc"; +- fsl,asrc-rate = <48000>; +- fsl,asrc-width = <16>; +- status = "okay"; +- }; +- }; +- +- tsc: tsc@2040000 { +- compatible = "fsl,imx6ul-tsc"; +- reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; +- interrupts = , +- ; +- clocks = <&clks IMX6UL_CLK_IPG>, +- <&clks IMX6UL_CLK_ADC2>; +- clock-names = "tsc", "adc"; +- status = "disabled"; +- }; +- +- pwm1: pwm@2080000 { +- compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; +- reg = <0x02080000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_PWM1>, +- <&clks IMX6UL_CLK_PWM1>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm2: pwm@2084000 { +- compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; +- reg = <0x02084000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_PWM2>, +- <&clks IMX6UL_CLK_PWM2>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm3: pwm@2088000 { +- compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; +- reg = <0x02088000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_PWM3>, +- <&clks IMX6UL_CLK_PWM3>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm4: pwm@208c000 { +- compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; +- reg = <0x0208c000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_PWM4>, +- <&clks IMX6UL_CLK_PWM4>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- can1: can@2090000 { +- compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; +- reg = <0x02090000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_CAN1_IPG>, +- <&clks IMX6UL_CLK_CAN1_SERIAL>; +- clock-names = "ipg", "per"; +- fsl,stop-mode = <&gpr 0x10 1>; +- status = "disabled"; +- }; +- +- can2: can@2094000 { +- compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; +- reg = <0x02094000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_CAN2_IPG>, +- <&clks IMX6UL_CLK_CAN2_SERIAL>; +- clock-names = "ipg", "per"; +- fsl,stop-mode = <&gpr 0x10 2>; +- status = "disabled"; +- }; +- +- gpt1: timer@2098000 { +- compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; +- reg = <0x02098000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_GPT1_BUS>, +- <&clks IMX6UL_CLK_GPT1_SERIAL>; +- clock-names = "ipg", "per"; +- }; +- +- gpio1: gpio@209c000 { +- compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; +- reg = <0x0209c000 0x4000>; +- interrupts = , +- ; +- clocks = <&clks IMX6UL_CLK_GPIO1>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>, +- <&iomuxc 16 33 16>; +- }; +- +- gpio2: gpio@20a0000 { +- compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; +- reg = <0x020a0000 0x4000>; +- interrupts = , +- ; +- clocks = <&clks IMX6UL_CLK_GPIO2>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>; +- }; +- +- gpio3: gpio@20a4000 { +- compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; +- reg = <0x020a4000 0x4000>; +- interrupts = , +- ; +- clocks = <&clks IMX6UL_CLK_GPIO3>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 65 29>; +- }; +- +- gpio4: gpio@20a8000 { +- compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; +- reg = <0x020a8000 0x4000>; +- interrupts = , +- ; +- clocks = <&clks IMX6UL_CLK_GPIO4>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; +- }; +- +- gpio5: gpio@20ac000 { +- compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; +- reg = <0x020ac000 0x4000>; +- interrupts = , +- ; +- clocks = <&clks IMX6UL_CLK_GPIO5>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; +- }; +- +- fec2: ethernet@20b4000 { +- compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; +- reg = <0x020b4000 0x4000>; +- interrupt-names = "int0", "pps"; +- interrupts = , +- ; +- clocks = <&clks IMX6UL_CLK_ENET>, +- <&clks IMX6UL_CLK_ENET_AHB>, +- <&clks IMX6UL_CLK_ENET_PTP>, +- <&clks IMX6UL_CLK_ENET2_REF_125M>, +- <&clks IMX6UL_CLK_ENET2_REF_125M>; +- clock-names = "ipg", "ahb", "ptp", +- "enet_clk_ref", "enet_out"; +- fsl,num-tx-queues = <1>; +- fsl,num-rx-queues = <1>; +- fsl,stop-mode = <&gpr 0x10 4>; +- fsl,magic-packet; +- status = "disabled"; +- }; +- +- kpp: keypad@20b8000 { +- compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp"; +- reg = <0x020b8000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_KPP>; +- status = "disabled"; +- }; +- +- wdog1: watchdog@20bc000 { +- compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; +- reg = <0x020bc000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_WDOG1>; +- }; +- +- wdog2: watchdog@20c0000 { +- compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; +- reg = <0x020c0000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_WDOG2>; +- status = "disabled"; +- }; +- +- clks: clock-controller@20c4000 { +- compatible = "fsl,imx6ul-ccm"; +- reg = <0x020c4000 0x4000>; +- interrupts = , +- ; +- #clock-cells = <1>; +- clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; +- clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; +- }; +- +- anatop: anatop@20c8000 { +- compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", +- "syscon", "simple-mfd"; +- reg = <0x020c8000 0x1000>; +- interrupts = , +- , +- ; +- +- reg_3p0: regulator-3p0 { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vdd3p0"; +- regulator-min-microvolt = <2625000>; +- regulator-max-microvolt = <3400000>; +- anatop-reg-offset = <0x120>; +- anatop-vol-bit-shift = <8>; +- anatop-vol-bit-width = <5>; +- anatop-min-bit-val = <0>; +- anatop-min-voltage = <2625000>; +- anatop-max-voltage = <3400000>; +- anatop-enable-bit = <0>; +- }; +- +- reg_arm: regulator-vddcore { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "cpu"; +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1450000>; +- regulator-always-on; +- anatop-reg-offset = <0x140>; +- anatop-vol-bit-shift = <0>; +- anatop-vol-bit-width = <5>; +- anatop-delay-reg-offset = <0x170>; +- anatop-delay-bit-shift = <24>; +- anatop-delay-bit-width = <2>; +- anatop-min-bit-val = <1>; +- anatop-min-voltage = <725000>; +- anatop-max-voltage = <1450000>; +- }; +- +- reg_soc: regulator-vddsoc { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vddsoc"; +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1450000>; +- regulator-always-on; +- anatop-reg-offset = <0x140>; +- anatop-vol-bit-shift = <18>; +- anatop-vol-bit-width = <5>; +- anatop-delay-reg-offset = <0x170>; +- anatop-delay-bit-shift = <28>; +- anatop-delay-bit-width = <2>; +- anatop-min-bit-val = <1>; +- anatop-min-voltage = <725000>; +- anatop-max-voltage = <1450000>; +- }; +- +- tempmon: tempmon { +- compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; +- interrupt-parent = <&gpc>; +- interrupts = ; +- fsl,tempmon = <&anatop>; +- nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; +- nvmem-cell-names = "calib", "temp_grade"; +- clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; +- }; +- }; +- +- usbphy1: usbphy@20c9000 { +- compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; +- reg = <0x020c9000 0x1000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_USBPHY1>; +- phy-3p0-supply = <®_3p0>; +- fsl,anatop = <&anatop>; +- }; +- +- usbphy2: usbphy@20ca000 { +- compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; +- reg = <0x020ca000 0x1000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_USBPHY2>; +- phy-3p0-supply = <®_3p0>; +- fsl,anatop = <&anatop>; +- }; +- +- snvs: snvs@20cc000 { +- compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; +- reg = <0x020cc000 0x4000>; +- +- snvs_rtc: snvs-rtc-lp { +- compatible = "fsl,sec-v4.0-mon-rtc-lp"; +- regmap = <&snvs>; +- offset = <0x34>; +- interrupts = , +- ; +- }; +- +- snvs_poweroff: snvs-poweroff { +- compatible = "syscon-poweroff"; +- regmap = <&snvs>; +- offset = <0x38>; +- value = <0x60>; +- mask = <0x60>; +- status = "disabled"; +- }; +- +- snvs_pwrkey: snvs-powerkey { +- compatible = "fsl,sec-v4.0-pwrkey"; +- regmap = <&snvs>; +- interrupts = ; +- linux,keycode = ; +- wakeup-source; +- status = "disabled"; +- }; +- +- snvs_lpgpr: snvs-lpgpr { +- compatible = "fsl,imx6ul-snvs-lpgpr"; +- }; +- }; +- +- epit1: epit@20d0000 { +- reg = <0x020d0000 0x4000>; +- interrupts = ; +- }; +- +- epit2: epit@20d4000 { +- reg = <0x020d4000 0x4000>; +- interrupts = ; +- }; +- +- src: reset-controller@20d8000 { +- compatible = "fsl,imx6ul-src", "fsl,imx51-src"; +- reg = <0x020d8000 0x4000>; +- interrupts = , +- ; +- #reset-cells = <1>; +- }; +- +- gpc: gpc@20dc000 { +- compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; +- reg = <0x020dc000 0x4000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = ; +- interrupt-parent = <&intc>; +- }; +- +- iomuxc: pinctrl@20e0000 { +- compatible = "fsl,imx6ul-iomuxc"; +- reg = <0x020e0000 0x4000>; +- }; +- +- gpr: iomuxc-gpr@20e4000 { +- compatible = "fsl,imx6ul-iomuxc-gpr", +- "fsl,imx6q-iomuxc-gpr", "syscon"; +- reg = <0x020e4000 0x4000>; +- }; +- +- gpt2: timer@20e8000 { +- compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; +- reg = <0x020e8000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_GPT2_BUS>, +- <&clks IMX6UL_CLK_GPT2_SERIAL>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- sdma: sdma@20ec000 { +- compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", +- "fsl,imx35-sdma"; +- reg = <0x020ec000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_IPG>, +- <&clks IMX6UL_CLK_SDMA>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; +- }; +- +- pwm5: pwm@20f0000 { +- compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; +- reg = <0x020f0000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_PWM5>, +- <&clks IMX6UL_CLK_PWM5>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm6: pwm@20f4000 { +- compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; +- reg = <0x020f4000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_PWM6>, +- <&clks IMX6UL_CLK_PWM6>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm7: pwm@20f8000 { +- compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; +- reg = <0x020f8000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_PWM7>, +- <&clks IMX6UL_CLK_PWM7>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm8: pwm@20fc000 { +- compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; +- reg = <0x020fc000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_PWM8>, +- <&clks IMX6UL_CLK_PWM8>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- }; +- +- aips2: bus@2100000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x02100000 0x100000>; +- ranges; +- +- crypto: crypto@2140000 { +- compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x2140000 0x3c000>; +- ranges = <0 0x2140000 0x3c000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>, +- <&clks IMX6UL_CLK_CAAM_MEM>; +- clock-names = "ipg", "aclk", "mem"; +- +- sec_jr0: jr@1000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x1000 0x1000>; +- interrupts = ; +- }; +- +- sec_jr1: jr@2000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x2000 0x1000>; +- interrupts = ; +- }; +- +- sec_jr2: jr@3000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x3000 0x1000>; +- interrupts = ; +- }; +- }; +- +- usbotg1: usb@2184000 { +- compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; +- reg = <0x02184000 0x200>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_USBOH3>; +- fsl,usbphy = <&usbphy1>; +- fsl,usbmisc = <&usbmisc 0>; +- fsl,anatop = <&anatop>; +- ahb-burst-config = <0x0>; +- tx-burst-size-dword = <0x10>; +- rx-burst-size-dword = <0x10>; +- status = "disabled"; +- }; +- +- usbotg2: usb@2184200 { +- compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; +- reg = <0x02184200 0x200>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_USBOH3>; +- fsl,usbphy = <&usbphy2>; +- fsl,usbmisc = <&usbmisc 1>; +- ahb-burst-config = <0x0>; +- tx-burst-size-dword = <0x10>; +- rx-burst-size-dword = <0x10>; +- status = "disabled"; +- }; +- +- usbmisc: usbmisc@2184800 { +- #index-cells = <1>; +- compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; +- reg = <0x02184800 0x200>; +- }; +- +- fec1: ethernet@2188000 { +- compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; +- reg = <0x02188000 0x4000>; +- interrupt-names = "int0", "pps"; +- interrupts = , +- ; +- clocks = <&clks IMX6UL_CLK_ENET>, +- <&clks IMX6UL_CLK_ENET_AHB>, +- <&clks IMX6UL_CLK_ENET_PTP>, +- <&clks IMX6UL_CLK_ENET_REF>, +- <&clks IMX6UL_CLK_ENET_REF>; +- clock-names = "ipg", "ahb", "ptp", +- "enet_clk_ref", "enet_out"; +- fsl,num-tx-queues = <1>; +- fsl,num-rx-queues = <1>; +- fsl,stop-mode = <&gpr 0x10 3>; +- fsl,magic-packet; +- status = "disabled"; +- }; +- +- usdhc1: mmc@2190000 { +- compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; +- reg = <0x02190000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_USDHC1>, +- <&clks IMX6UL_CLK_USDHC1>, +- <&clks IMX6UL_CLK_USDHC1>; +- clock-names = "ipg", "ahb", "per"; +- fsl,tuning-step = <2>; +- fsl,tuning-start-tap = <20>; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usdhc2: mmc@2194000 { +- compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; +- reg = <0x02194000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_USDHC2>, +- <&clks IMX6UL_CLK_USDHC2>, +- <&clks IMX6UL_CLK_USDHC2>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- fsl,tuning-step = <2>; +- fsl,tuning-start-tap = <20>; +- status = "disabled"; +- }; +- +- adc1: adc@2198000 { +- compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; +- reg = <0x02198000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_ADC1>; +- num-channels = <2>; +- clock-names = "adc"; +- fsl,adck-max-frequency = <30000000>, <40000000>, +- <20000000>; +- status = "disabled"; +- }; +- +- i2c1: i2c@21a0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; +- reg = <0x021a0000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_I2C1>; +- status = "disabled"; +- }; +- +- i2c2: i2c@21a4000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; +- reg = <0x021a4000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_I2C2>; +- status = "disabled"; +- }; +- +- i2c3: i2c@21a8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; +- reg = <0x021a8000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_I2C3>; +- status = "disabled"; +- }; +- +- memory-controller@21b0000 { +- compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; +- reg = <0x021b0000 0x4000>; +- clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>; +- }; +- +- weim: weim@21b8000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; +- reg = <0x021b8000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_EIM>; +- fsl,weim-cs-gpr = <&gpr>; +- status = "disabled"; +- }; +- +- ocotp: efuse@21bc000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,imx6ul-ocotp", "syscon"; +- reg = <0x021bc000 0x4000>; +- clocks = <&clks IMX6UL_CLK_OCOTP>; +- +- tempmon_calib: calib@38 { +- reg = <0x38 4>; +- }; +- +- tempmon_temp_grade: temp-grade@20 { +- reg = <0x20 4>; +- }; +- +- cpu_speed_grade: speed-grade@10 { +- reg = <0x10 4>; +- }; +- }; +- +- csi: csi@21c4000 { +- compatible = "fsl,imx6ul-csi", "fsl,imx7-csi"; +- reg = <0x021c4000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_CSI>; +- clock-names = "mclk"; +- status = "disabled"; +- }; +- +- lcdif: lcdif@21c8000 { +- compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; +- reg = <0x021c8000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, +- <&clks IMX6UL_CLK_LCDIF_APB>, +- <&clks IMX6UL_CLK_DUMMY>; +- clock-names = "pix", "axi", "disp_axi"; +- status = "disabled"; +- }; +- +- pxp: pxp@21cc000 { +- compatible = "fsl,imx6ul-pxp"; +- reg = <0x021cc000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_PXP>; +- clock-names = "axi"; +- }; +- +- qspi: spi@21e0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi"; +- reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; +- reg-names = "QuadSPI", "QuadSPI-memory"; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_QSPI>, +- <&clks IMX6UL_CLK_QSPI>; +- clock-names = "qspi_en", "qspi"; +- status = "disabled"; +- }; +- +- wdog3: watchdog@21e4000 { +- compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; +- reg = <0x021e4000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_WDOG3>; +- status = "disabled"; +- }; +- +- uart2: serial@21e8000 { +- compatible = "fsl,imx6ul-uart", +- "fsl,imx6q-uart"; +- reg = <0x021e8000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_UART2_IPG>, +- <&clks IMX6UL_CLK_UART2_SERIAL>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart3: serial@21ec000 { +- compatible = "fsl,imx6ul-uart", +- "fsl,imx6q-uart"; +- reg = <0x021ec000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_UART3_IPG>, +- <&clks IMX6UL_CLK_UART3_SERIAL>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart4: serial@21f0000 { +- compatible = "fsl,imx6ul-uart", +- "fsl,imx6q-uart"; +- reg = <0x021f0000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_UART4_IPG>, +- <&clks IMX6UL_CLK_UART4_SERIAL>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart5: serial@21f4000 { +- compatible = "fsl,imx6ul-uart", +- "fsl,imx6q-uart"; +- reg = <0x021f4000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_UART5_IPG>, +- <&clks IMX6UL_CLK_UART5_SERIAL>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- i2c4: i2c@21f8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; +- reg = <0x021f8000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_I2C4>; +- status = "disabled"; +- }; +- +- uart6: serial@21fc000 { +- compatible = "fsl,imx6ul-uart", +- "fsl,imx6q-uart"; +- reg = <0x021fc000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_UART6_IPG>, +- <&clks IMX6UL_CLK_UART6_SERIAL>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-14x14-evk.dts b/scripts/dtc/include-prefixes/arm/imx6ull-14x14-evk.dts +deleted file mode 100644 +index 74aaa8a56a3d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-14x14-evk.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright (C) 2016 Freescale Semiconductor, Inc. +- +-/dts-v1/; +- +-#include "imx6ull.dtsi" +-#include "imx6ul-14x14-evk.dtsi" +- +-/ { +- model = "Freescale i.MX6 UltraLiteLite 14x14 EVK Board"; +- compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>; +- assigned-clock-rates = <320000000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-colibri-eval-v3.dts b/scripts/dtc/include-prefixes/arm/imx6ull-colibri-eval-v3.dts +deleted file mode 100644 +index 08669a18349e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-colibri-eval-v3.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2018 Toradex AG +- */ +- +-/dts-v1/; +- +-#include "imx6ull-colibri-nonwifi.dtsi" +-#include "imx6ull-colibri-eval-v3.dtsi" +- +-/ { +- model = "Toradex Colibri iMX6ULL 256MB on Colibri Evaluation Board V3"; +- compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-colibri-eval-v3.dtsi b/scripts/dtc/include-prefixes/arm/imx6ull-colibri-eval-v3.dtsi +deleted file mode 100644 +index a78849fd2afa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-colibri-eval-v3.dtsi ++++ /dev/null +@@ -1,178 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2017 Toradex AG +- */ +- +-/ { +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_snvs_gpiokeys>; +- +- power { +- label = "Wake-Up"; +- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- /* fixed crystal dedicated to mcp2515 */ +- clk16m: clk16m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <16000000>; +- }; +- +- panel: panel { +- compatible = "edt,et057090dhu"; +- backlight = <&bl>; +- power-supply = <®_3v3>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lcdif_out>; +- }; +- }; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_5v0: regulator-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usbh_vbus: regulator-usbh-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh_reg>; +- regulator-name = "VCC_USB[1-4]"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; +- vin-supply = <®_5v0>; +- }; +-}; +- +-&adc1 { +- status = "okay"; +-}; +- +-&bl { +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- power-supply = <®_3v3>; +- pwms = <&pwm4 0 5000000 1>; +- status = "okay"; +-}; +- +-&ecspi1 { +- status = "okay"; +- +- mcp2515: can@0 { +- compatible = "microchip,mcp2515"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can_int>; +- reg = <0>; +- clocks = <&clk16m>; +- interrupt-parent = <&gpio2>; +- interrupts = <4 IRQ_TYPE_EDGE_FALLING>; +- spi-max-frequency = <10000000>; +- vdd-supply = <®_3v3>; +- xceiver-supply = <®_5v0>; +- status = "okay"; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- /* M41T0M6 real time clock on carrier board */ +- m41t0m6: rtc@68 { +- compatible = "st,m41t0"; +- reg = <0x68>; +- }; +-}; +- +-&lcdif { +- status = "okay"; +- +- port { +- lcdif_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +-}; +- +-/* PWM */ +-&pwm4 { +- status = "okay"; +-}; +- +-/* PWM */ +-&pwm5 { +- status = "okay"; +-}; +- +-/* PWM */ +-&pwm6 { +- status = "okay"; +-}; +- +-/* PWM */ +-&pwm7 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&usbotg1 { +- status = "okay"; +-}; +- +-&usbotg2 { +- vbus-supply = <®_usbh_vbus>; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; +- pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; +- pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>; +- cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; +- disable-wp; +- wakeup-source; +- keep-power-in-suspend; +- vmmc-supply = <®_3v3>; +- vqmmc-supply = <®_sd1_vmmc>; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-colibri-nonwifi.dtsi b/scripts/dtc/include-prefixes/arm/imx6ull-colibri-nonwifi.dtsi +deleted file mode 100644 +index 95a11b8bcbdb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-colibri-nonwifi.dtsi ++++ /dev/null +@@ -1,24 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2018 Toradex AG +- */ +- +-#include "imx6ull-colibri.dtsi" +- +-/ { +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 +- &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6 &pinctrl_gpio7>; +-}; +- +-&iomuxc_snvs { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2 &pinctrl_snvs_gpio3>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-colibri-wifi-eval-v3.dts b/scripts/dtc/include-prefixes/arm/imx6ull-colibri-wifi-eval-v3.dts +deleted file mode 100644 +index df72ce1ae2cb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-colibri-wifi-eval-v3.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2018 Toradex AG +- */ +- +-/dts-v1/; +- +-#include "imx6ull-colibri-wifi.dtsi" +-#include "imx6ull-colibri-eval-v3.dtsi" +- +-/ { +- model = "Toradex Colibri iMX6ULL 512MB on Colibri Evaluation Board V3"; +- compatible = "toradex,colibri-imx6ull-wifi-eval", "fsl,imx6ull"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-colibri-wifi.dtsi b/scripts/dtc/include-prefixes/arm/imx6ull-colibri-wifi.dtsi +deleted file mode 100644 +index 9f1e38282bee..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-colibri-wifi.dtsi ++++ /dev/null +@@ -1,53 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2018 Toradex AG +- */ +- +-#include "imx6ull-colibri.dtsi" +- +-/ { +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +- +- wifi_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_snvs_wifi_pdn>; +- reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&cpu0 { +- clock-frequency = <792000000>; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 +- &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio7>; +- +-}; +- +-&iomuxc_snvs { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2>; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; +- assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; +- assigned-clock-rates = <0>, <198000000>; +- cap-power-off-card; +- keep-power-in-suspend; +- max-frequency = <25000000>; +- mmc-pwrseq = <&wifi_pwrseq>; +- no-1-8-v; +- non-removable; +- vmmc-supply = <®_module_3v3>; +- wakeup-source; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-colibri.dtsi b/scripts/dtc/include-prefixes/arm/imx6ull-colibri.dtsi +deleted file mode 100644 +index 0cdbf7b6e728..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-colibri.dtsi ++++ /dev/null +@@ -1,607 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2018 Toradex AG +- */ +- +-#include "imx6ull.dtsi" +- +-/ { +- aliases { +- ethernet0 = &fec2; +- ethernet1 = &fec1; +- }; +- +- bl: backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_bl_on>; +- enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; +- status = "disabled"; +- }; +- +- reg_module_3v3: regulator-module-3v3 { +- compatible = "regulator-fixed"; +- regulator-always-on; +- regulator-name = "+V3.3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_module_3v3_avdd: regulator-module-3v3-avdd { +- compatible = "regulator-fixed"; +- regulator-always-on; +- regulator-name = "+V3.3_AVDD_AUDIO"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_sd1_vmmc: regulator-sd1-vmmc { +- compatible = "regulator-gpio"; +- gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_snvs_reg_sd>; +- regulator-always-on; +- regulator-name = "+V3.3_1.8_SD"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- states = <1800000 0x1 3300000 0x0>; +- vin-supply = <®_module_3v3>; +- }; +-}; +- +-&adc1 { +- num-channels = <10>; +- vref-supply = <®_module_3v3_avdd>; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- status = "disabled"; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- status = "disabled"; +-}; +- +-/* Colibri SPI */ +-&ecspi1 { +- cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; +-}; +- +-&fec2 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&pinctrl_enet2>; +- pinctrl-1 = <&pinctrl_enet2_sleep>; +- phy-mode = "rmii"; +- phy-handle = <ðphy1>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy1: ethernet-phy@2 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- max-speed = <100>; +- reg = <2>; +- }; +- }; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- nand-on-flash-bbt; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <8>; +- nand-ecc-step-size = <512>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c1>; +- pinctrl-1 = <&pinctrl_i2c1_gpio>; +- sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +-}; +- +-&i2c2 { +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c2>; +- pinctrl-1 = <&pinctrl_i2c2_gpio>; +- sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +- +- ad7879@2c { +- compatible = "adi,ad7879-1"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_snvs_ad7879_int>; +- reg = <0x2c>; +- interrupt-parent = <&gpio5>; +- interrupts = <7 IRQ_TYPE_EDGE_FALLING>; +- touchscreen-max-pressure = <4096>; +- adi,resistance-plate-x = <120>; +- adi,first-conversion-delay = /bits/ 8 <3>; +- adi,acquisition-time = /bits/ 8 <1>; +- adi,median-filter-size = /bits/ 8 <2>; +- adi,averaging = /bits/ 8 <1>; +- adi,conversion-interval = /bits/ 8 <255>; +- }; +-}; +- +-&lcdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcdif_dat +- &pinctrl_lcdif_ctrl>; +-}; +- +-&pwm4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +-}; +- +-&pwm5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm5>; +-}; +- +-&pwm6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm6>; +-}; +- +-&pwm7 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm7>; +-}; +- +-&sdma { +- status = "okay"; +-}; +- +-&snvs_pwrkey { +- status = "disabled"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; +- uart-has-rtscts; +- fsl,dte-mode; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- uart-has-rtscts; +- fsl,dte-mode; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- fsl,dte-mode; +-}; +- +-&usbotg1 { +- dr_mode = "otg"; +- srp-disable; +- hnp-disable; +- adp-disable; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +-}; +- +-&usdhc1 { +- assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; +- assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; +- assigned-clock-rates = <0>, <198000000>; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl_can_int: canint-grp { +- fsl,pins = < +- MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */ +- >; +- }; +- +- pinctrl_enet2: enet2-grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 +- MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 +- MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 +- MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 +- MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 +- MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 +- MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 +- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 +- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 +- MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 +- >; +- }; +- +- pinctrl_enet2_sleep: enet2sleepgrp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0 +- MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0 +- MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0 +- MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0 +- MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0 +- MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0 +- MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 +- MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0 +- MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0 +- MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0 +- >; +- }; +- +- pinctrl_ecspi1_cs: ecspi1-cs-grp { +- fsl,pins = < +- MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */ +- >; +- }; +- +- pinctrl_ecspi1: ecspi1-grp { +- fsl,pins = < +- MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */ +- MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */ +- MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 /* SODIMM 90 */ +- >; +- }; +- +- pinctrl_flexcan1: flexcan1-grp { +- fsl,pins = < +- MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 +- MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2-grp { +- fsl,pins = < +- MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 +- MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 +- >; +- }; +- +- pinctrl_gpio_bl_on: gpio-bl-on-grp { +- fsl,pins = < +- MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */ +- >; +- }; +- +- pinctrl_gpio1: gpio1-grp { +- fsl,pins = < +- MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */ +- MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */ +- MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x10b0 /* SODIMM 133 */ +- MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x10b0 /* SODIMM 135 */ +- MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x10b0 /* SODIMM 100 */ +- MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x70a0 /* SODIMM 102 */ +- MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 /* SODIMM 104 */ +- MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0 /* SODIMM 186 */ +- >; +- }; +- +- pinctrl_gpio2: gpio2-grp { /* Camera */ +- fsl,pins = < +- MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */ +- MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */ +- MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x10b0 /* SODIMM 85 */ +- MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x10b0 /* SODIMM 96 */ +- MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 /* SODIMM 98 */ +- >; +- }; +- +- pinctrl_gpio3: gpio3-grp { /* CAN2 */ +- fsl,pins = < +- MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */ +- MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */ +- >; +- }; +- +- pinctrl_gpio4: gpio4-grp { +- fsl,pins = < +- MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */ +- >; +- }; +- +- pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */ +- fsl,pins = < +- MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */ +- >; +- }; +- +- pinctrl_gpio6: gpio6-grp { /* Wifi pins */ +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */ +- MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */ +- MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 /* SODIMM 81 */ +- MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 /* SODIMM 97 */ +- MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 /* SODIMM 101 */ +- MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 /* SODIMM 103 */ +- MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 /* SODIMM 94 */ +- >; +- }; +- +- pinctrl_gpio7: gpio7-grp { /* CAN1 */ +- fsl,pins = < +- MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */ +- MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */ +- >; +- }; +- +- pinctrl_gpmi_nand: gpmi-nand-grp { +- fsl,pins = < +- MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 +- MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 +- MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9 +- MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9 +- MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9 +- MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9 +- MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9 +- MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9 +- MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9 +- MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9 +- MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9 +- MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9 +- MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9 +- MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9 +- >; +- }; +- +- pinctrl_i2c1: i2c1-grp { +- fsl,pins = < +- MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */ +- MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */ +- >; +- }; +- +- pinctrl_i2c1_gpio: i2c1-gpio-grp { +- fsl,pins = < +- MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */ +- MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */ +- >; +- }; +- +- pinctrl_i2c2: i2c2-grp { +- fsl,pins = < +- MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 +- MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 +- >; +- }; +- +- pinctrl_i2c2_gpio: i2c2-gpio-grp { +- fsl,pins = < +- MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0 +- MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0 +- >; +- }; +- +- pinctrl_lcdif_dat: lcdif-dat-grp { +- fsl,pins = < +- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */ +- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */ +- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 /* SODIMM 60 */ +- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 /* SODIMM 58 */ +- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 /* SODIMM 78 */ +- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 /* SODIMM 72 */ +- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 /* SODIMM 80 */ +- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 /* SODIMM 46 */ +- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 /* SODIMM 62 */ +- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 /* SODIMM 48 */ +- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 /* SODIMM 74 */ +- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 /* SODIMM 50 */ +- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 /* SODIMM 52 */ +- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 /* SODIMM 54 */ +- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 /* SODIMM 66 */ +- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 /* SODIMM 64 */ +- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 /* SODIMM 57 */ +- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 /* SODIMM 61 */ +- >; +- }; +- +- pinctrl_lcdif_ctrl: lcdif-ctrl-grp { +- fsl,pins = < +- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */ +- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */ +- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 /* SODIMM 68 */ +- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 /* SODIMM 82 */ +- >; +- }; +- +- pinctrl_pwm4: pwm4-grp { +- fsl,pins = < +- MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */ +- >; +- }; +- +- pinctrl_pwm5: pwm5-grp { +- fsl,pins = < +- MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */ +- >; +- }; +- +- pinctrl_pwm6: pwm6-grp { +- fsl,pins = < +- MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */ +- >; +- }; +- +- pinctrl_pwm7: pwm7-grp { +- fsl,pins = < +- MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */ +- >; +- }; +- +- pinctrl_uart1: uart1-grp { +- fsl,pins = < +- MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */ +- MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */ +- MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 /* SODIMM 27 */ +- MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */ +- >; +- }; +- +- pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */ +- fsl,pins = < +- MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 */ +- MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 */ +- MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 */ +- MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 */ +- >; +- }; +- +- pinctrl_uart2: uart2-grp { +- fsl,pins = < +- MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */ +- MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */ +- MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 /* SODIMM 32 */ +- MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */ +- >; +- }; +- pinctrl_uart5: uart5-grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */ +- MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */ +- >; +- }; +- +- pinctrl_usbh_reg: gpio-usbh-reg { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 */ +- >; +- }; +- +- pinctrl_usdhc1: usdhc1-grp { +- fsl,pins = < +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 /* SODIMM 47 */ +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 /* SODIMM 190 */ +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */ +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */ +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */ +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */ +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { +- fsl,pins = < +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9 +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { +- fsl,pins = < +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9 +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2-grp { +- fsl,pins = < +- MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17069 +- MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069 +- MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069 +- MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069 +- MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069 +- MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17069 +- +- MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10 +- >; +- }; +- +- pinctrl_wdog: wdog-grp { +- fsl,pins = < +- MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 +- >; +- }; +-}; +- +-&iomuxc_snvs { +- pinctrl_snvs_gpio1: snvs-gpio1-grp { +- fsl,pins = < +- MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */ +- MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */ +- MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */ +- MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 */ +- MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */ +- >; +- }; +- +- pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */ +- fsl,pins = < +- MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */ +- >; +- }; +- +- pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */ +- fsl,pins = < +- MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */ +- >; +- }; +- +- pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */ +- fsl,pins = < +- MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0 +- >; +- }; +- +- pinctrl_snvs_reg_sd: snvs-reg-sd-grp { +- fsl,pins = < +- MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0 +- >; +- }; +- +- pinctrl_snvs_usbc_det: snvs-usbc-det-grp { +- fsl,pins = < +- MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0 +- >; +- }; +- +- pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp { +- fsl,pins = < +- MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 */ +- >; +- }; +- +- pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp { +- fsl,pins = < +- MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 */ +- >; +- }; +- +- pinctrl_snvs_usdhc1_sleep_cd: snvs-usdhc1-cd-grp-slp { +- fsl,pins = < +- MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 +- >; +- }; +- +- pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp { +- fsl,pins = < +- MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-kontron-n6411-s.dts b/scripts/dtc/include-prefixes/arm/imx6ull-kontron-n6411-s.dts +deleted file mode 100644 +index 57588a5e1e34..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-kontron-n6411-s.dts ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2017 exceet electronics GmbH +- * Copyright (C) 2019 Kontron Electronics GmbH +- */ +- +-/dts-v1/; +- +-#include "imx6ull-kontron-n6411-som.dtsi" +-#include "imx6ul-kontron-n6x1x-s.dtsi" +- +-/ { +- model = "Kontron N6411 S"; +- compatible = "kontron,imx6ull-n6411-s", "kontron,imx6ull-n6411-som", +- "fsl,imx6ull"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-kontron-n6411-som.dtsi b/scripts/dtc/include-prefixes/arm/imx6ull-kontron-n6411-som.dtsi +deleted file mode 100644 +index b7e984284e1a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-kontron-n6411-som.dtsi ++++ /dev/null +@@ -1,40 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2017 exceet electronics GmbH +- * Copyright (C) 2018 Kontron Electronics GmbH +- */ +- +-#include "imx6ull.dtsi" +-#include "imx6ul-kontron-n6x1x-som-common.dtsi" +- +-/ { +- model = "Kontron N6411 SOM"; +- compatible = "kontron,imx6ull-n6311-som", "fsl,imx6ull"; +- +- memory@80000000 { +- reg = <0x80000000 0x20000000>; +- device_type = "memory"; +- }; +-}; +- +-&qspi { +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spi-nand"; +- spi-max-frequency = <104000000>; +- spi-tx-bus-width = <4>; +- spi-rx-bus-width = <4>; +- reg = <0>; +- +- partition@0 { +- label = "ubi1"; +- reg = <0x00000000 0x08000000>; +- }; +- +- partition@8000000 { +- label = "ubi2"; +- reg = <0x08000000 0x18000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-myir-mys-6ulx-eval.dts b/scripts/dtc/include-prefixes/arm/imx6ull-myir-mys-6ulx-eval.dts +deleted file mode 100644 +index 79cc45728cd2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-myir-mys-6ulx-eval.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2020 Linumiz +- * Author: Parthiban Nallathambi +- */ +- +-/dts-v1/; +-#include "imx6ull.dtsi" +-#include "imx6ull-myir-mys-6ulx.dtsi" +- +-/ { +- model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND"; +- compatible = "myir,imx6ull-mys-6ulx-eval", "fsl,imx6ull"; +-}; +- +-&gpmi { +- fsl,use-minimum-ecc; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-myir-mys-6ulx.dtsi b/scripts/dtc/include-prefixes/arm/imx6ull-myir-mys-6ulx.dtsi +deleted file mode 100644 +index d03694feaf5c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-myir-mys-6ulx.dtsi ++++ /dev/null +@@ -1,238 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2020 Linumiz +- * Author: Parthiban Nallathambi +- */ +- +-#include +-#include +-#include +- +-/ { +- model = "MYiR MYS-6ULX Single Board Computer"; +- compatible = "fsl,imx6ull"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- reg_vdd_5v: regulator-vdd-5v { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_vdd_3v3: regulator-vdd-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- vin-supply = <®_vdd_5v>; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- phy-mode = "rmii"; +- phy-handle = <ðphy0>; +- phy-supply = <®_vdd_3v3>; +- status = "okay"; +- +- mdio: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- interrupt-parent = <&gpio5>; +- interrupts = <5 IRQ_TYPE_LEVEL_LOW>; +- clocks = <&clks IMX6UL_CLK_ENET_REF>; +- clock-names = "rmii-ref"; +- }; +- }; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- nand-on-flash-bbt; +- status = "disabled"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usbotg1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_otg1_id>; +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- keep-power-in-suspend; +- wakeup-source; +- vmmc-supply = <®_vdd_3v3>; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>; +- bus-width = <8>; +- non-removable; +- keep-power-in-suspend; +- vmmc-supply = <®_vdd_3v3>; +-}; +- +-&iomuxc { +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 +- MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 +- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 +- MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 +- >; +- }; +- +- pinctrl_gpmi_nand: gpminandgrp { +- fsl,pins = < +- MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 +- MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 +- MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 +- MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 +- MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 +- MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 +- MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 +- MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 +- MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 +- MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 +- MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 +- MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 +- MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 +- MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 +- MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_usb_otg1_id: usbotg1idgrp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 +- MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1grp100mhz { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1grp200mhz { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 +- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 +- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 +- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 +- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 +- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 +- MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 +- MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 +- MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 +- MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2grp100mhz { +- fsl,pins = < +- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 +- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 +- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 +- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 +- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 +- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 +- MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 +- MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 +- MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 +- MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2grp200mhz { +- fsl,pins = < +- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 +- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 +- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 +- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 +- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 +- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 +- MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 +- MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 +- MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 +- MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-opos6ul.dtsi b/scripts/dtc/include-prefixes/arm/imx6ull-opos6ul.dtsi +deleted file mode 100644 +index 155f941f2811..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-opos6ul.dtsi ++++ /dev/null +@@ -1,6 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-// +-// Copyright 2019 Armadeus Systems +- +-#include "imx6ull.dtsi" +-#include "imx6ul-imx6ull-opos6ul.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-opos6uldev.dts b/scripts/dtc/include-prefixes/arm/imx6ull-opos6uldev.dts +deleted file mode 100644 +index 198fdb72641b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-opos6uldev.dts ++++ /dev/null +@@ -1,42 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-// +-// Copyright 2019 Armadeus Systems +- +-/dts-v1/; +-#include "imx6ull-opos6ul.dtsi" +-#include "imx6ul-imx6ull-opos6uldev.dtsi" +- +-/ { +- model = "Armadeus Systems OPOS6UL SoM (i.MX6ULL) on OPOS6ULDev board"; +- compatible = "armadeus,imx6ull-opos6uldev", "armadeus,imx6ull-opos6ul", "fsl,imx6ull"; +-}; +- +-&iomuxc_snvs { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tamper_gpios>; +- +- pinctrl_tamper_gpios: tampergpiosgrp { +- fsl,pins = < +- MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0 +- MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0 +- MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 +- MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 +- MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 +- MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 +- MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 +- MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0 +- >; +- }; +- +- pinctrl_usbotg2_vbus: usbotg2vbusgrp { +- fsl,pins = < +- MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 +- >; +- }; +- +- pinctrl_w1: w1grp { +- fsl,pins = < +- MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-phytec-phycore-som.dtsi b/scripts/dtc/include-prefixes/arm/imx6ull-phytec-phycore-som.dtsi +deleted file mode 100644 +index 56cd16e5a77f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-phytec-phycore-som.dtsi ++++ /dev/null +@@ -1,24 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 PHYTEC Messtechnik GmbH +- * Author: Stefan Riedmueller +- */ +- +-#include "imx6ul-phytec-phycore-som.dtsi" +- +-/ { +- model = "PHYTEC phyCORE-i.MX6 ULL"; +- compatible = "phytec,imx6ull-pcl063", "fsl,imx6ull"; +-}; +- +-&iomuxc { +- /delete-node/ gpioledssomgrp; +-}; +- +-&iomuxc_snvs { +- pinctrl_gpioleds_som: gpioledssomgrp { +- fsl,pins = < +- MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-phytec-segin-ff-rdk-emmc.dts b/scripts/dtc/include-prefixes/arm/imx6ull-phytec-segin-ff-rdk-emmc.dts +deleted file mode 100644 +index 8e2a4c5d7765..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-phytec-segin-ff-rdk-emmc.dts ++++ /dev/null +@@ -1,94 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 PHYTEC Messtechnik GmbH +- * Author: Stefan Riedmueller +- */ +- +-/dts-v1/; +-#include "imx6ull.dtsi" +-#include "imx6ull-phytec-phycore-som.dtsi" +-#include "imx6ull-phytec-segin.dtsi" +-#include "imx6ull-phytec-segin-peb-eval-01.dtsi" +-#include "imx6ull-phytec-segin-peb-av-02.dtsi" +- +-/ { +- model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with eMMC"; +- compatible = "phytec,imx6ull-pbacd10-emmc", "phytec,imx6ull-pbacd10", +- "phytec,imx6ull-pcl063","fsl,imx6ull"; +-}; +- +-&adc1 { +- status = "okay"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&tlv320 { +- status = "okay"; +-}; +- +-&ecspi3 { +- status = "okay"; +-}; +- +-ðphy1 { +- status = "okay"; +-}; +- +-ðphy2 { +- status = "okay"; +-}; +- +-&fec1 { +- status = "okay"; +-}; +- +-&fec2 { +- status = "okay"; +-}; +- +-&i2c_rtc { +- status = "okay"; +-}; +- +-®_can1_en { +- status = "okay"; +-}; +- +-®_sound_1v8 { +- status = "okay"; +-}; +- +-®_sound_3v3 { +- status = "okay"; +-}; +- +-&sai2 { +- status = "okay"; +-}; +- +-&sound { +- status = "okay"; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&usbotg1 { +- status = "okay"; +-}; +- +-&usbotg2 { +- status = "okay"; +-}; +- +-&usdhc1 { +- status = "okay"; +-}; +- +-&usdhc2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-phytec-segin-ff-rdk-nand.dts b/scripts/dtc/include-prefixes/arm/imx6ull-phytec-segin-ff-rdk-nand.dts +deleted file mode 100644 +index c8d3eff9ed4b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-phytec-segin-ff-rdk-nand.dts ++++ /dev/null +@@ -1,94 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 PHYTEC Messtechnik GmbH +- * Author: Stefan Riedmueller +- */ +- +-/dts-v1/; +-#include "imx6ull.dtsi" +-#include "imx6ull-phytec-phycore-som.dtsi" +-#include "imx6ull-phytec-segin.dtsi" +-#include "imx6ull-phytec-segin-peb-eval-01.dtsi" +-#include "imx6ull-phytec-segin-peb-av-02.dtsi" +- +-/ { +- model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND"; +- compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10", +- "phytec,imx6ull-pcl063", "fsl,imx6ull"; +-}; +- +-&adc1 { +- status = "okay"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&tlv320 { +- status = "okay"; +-}; +- +-&ecspi3 { +- status = "okay"; +-}; +- +-ðphy1 { +- status = "okay"; +-}; +- +-ðphy2 { +- status = "okay"; +-}; +- +-&fec1 { +- status = "okay"; +-}; +- +-&fec2 { +- status = "okay"; +-}; +- +-&gpmi { +- status = "okay"; +-}; +- +-&i2c_rtc { +- status = "okay"; +-}; +- +-®_can1_en { +- status = "okay"; +-}; +- +-®_sound_1v8 { +- status = "okay"; +-}; +- +-®_sound_3v3 { +- status = "okay"; +-}; +- +-&sai2 { +- status = "okay"; +-}; +- +-&sound { +- status = "okay"; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&usbotg1 { +- status = "okay"; +-}; +- +-&usbotg2 { +- status = "okay"; +-}; +- +-&usdhc1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-phytec-segin-lc-rdk-nand.dts b/scripts/dtc/include-prefixes/arm/imx6ull-phytec-segin-lc-rdk-nand.dts +deleted file mode 100644 +index e168494e0a6d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-phytec-segin-lc-rdk-nand.dts ++++ /dev/null +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 PHYTEC Messtechnik GmbH +- * Author: Stefan Riedmueller +- */ +- +-/dts-v1/; +-#include "imx6ull.dtsi" +-#include "imx6ull-phytec-phycore-som.dtsi" +-#include "imx6ull-phytec-segin.dtsi" +-#include "imx6ull-phytec-segin-peb-eval-01.dtsi" +- +-/ { +- model = "PHYTEC phyBOARD-Segin i.MX6 ULL Low Cost with NAND"; +- compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10", +- "phytec,imx6ull-pcl063", "fsl,imx6ull"; +-}; +- +-&adc1 { +- status = "okay"; +-}; +- +-ðphy1 { +- status = "okay"; +-}; +- +-&fec1 { +- status = "okay"; +-}; +- +-&gpmi { +- status = "okay"; +-}; +- +-&i2c_rtc { +- status = "okay"; +-}; +- +-&usbotg1 { +- status = "okay"; +-}; +- +-&usdhc1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-phytec-segin-peb-av-02.dtsi b/scripts/dtc/include-prefixes/arm/imx6ull-phytec-segin-peb-av-02.dtsi +deleted file mode 100644 +index 06bb7f327780..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-phytec-segin-peb-av-02.dtsi ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +-/* +- * Copyright (C) 2018 PHYTEC Messtechnik GmbH +- * Author: Stefan Riedmueller +- */ +- +-#include "imx6ul-phytec-segin-peb-av-02.dtsi" +- +-&iomuxc { +- /delete-node/ edtft5406grp; +- /delete-node/ stmpegrp; +-}; +- +-&iomuxc_snvs { +- pinctrl_edt_ft5406: edtft5406grp { +- fsl,pins = < +- MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 +- >; +- }; +- +- pinctrl_stmpe: stmpegrp { +- fsl,pins = < +- MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-phytec-segin-peb-eval-01.dtsi b/scripts/dtc/include-prefixes/arm/imx6ull-phytec-segin-peb-eval-01.dtsi +deleted file mode 100644 +index ff08d95a1aa2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-phytec-segin-peb-eval-01.dtsi ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 PHYTEC Messtechnik GmbH +- * Author: Stefan Riedmueller +- */ +- +-#include "imx6ul-phytec-segin-peb-eval-01.dtsi" +- +-&iomuxc { +- /delete-node/ gpio_keysgrp; +-}; +- +-&iomuxc_snvs { +- pinctrl_gpio_keys: gpio_keysgrp { +- fsl,pins = < +- MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-phytec-segin.dtsi b/scripts/dtc/include-prefixes/arm/imx6ull-phytec-segin.dtsi +deleted file mode 100644 +index e287a0453b5f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-phytec-segin.dtsi ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 PHYTEC Messtechnik GmbH +- * Author: Stefan Riedmueller +- */ +- +-#include "imx6ul-phytec-segin.dtsi" +- +-/ { +- model = "PHYTEC phyBOARD-Segin i.MX6 ULL"; +- compatible = "phytec,imx6ull-pbacd-10", "phytec,imx6ull-pcl063","fsl,imx6ull"; +-}; +- +-&iomuxc { +- /delete-node/ flexcan1engrp; +- /delete-node/ rtcintgrp; +-}; +- +-&iomuxc_snvs { +- princtrl_flexcan1_en: flexcan1engrp { +- fsl,pins = < +- MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 +- >; +- }; +- +- pinctrl_rtc_int: rtcintgrp { +- fsl,pins = < +- MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-pinfunc-snvs.h b/scripts/dtc/include-prefixes/arm/imx6ull-pinfunc-snvs.h +deleted file mode 100644 +index 54cfe72295aa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-pinfunc-snvs.h ++++ /dev/null +@@ -1,26 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2016 Freescale Semiconductor, Inc. +- * Copyright (C) 2017 NXP +- */ +- +-#ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H +-#define __DTS_IMX6ULL_PINFUNC_SNVS_H +-/* +- * The pin function ID is a tuple of +- * +- */ +-#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0 +-#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0 +-#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0 +-#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0 +-#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0 +-#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0 +-#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0 +-#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0 +-#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0 +-#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0 +-#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0028 0x006C 0x0000 0x5 0x0 +-#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x002C 0x0070 0x0000 0x5 0x0 +- +-#endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */ +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull-pinfunc.h b/scripts/dtc/include-prefixes/arm/imx6ull-pinfunc.h +deleted file mode 100644 +index 7328d4ef8559..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull-pinfunc.h ++++ /dev/null +@@ -1,87 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2016 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __DTS_IMX6ULL_PINFUNC_H +-#define __DTS_IMX6ULL_PINFUNC_H +- +-#include "imx6ul-pinfunc.h" +-/* +- * The pin function ID is a tuple of +- * +- */ +-/* signals common for i.MX6UL and i.MX6ULL */ +-#undef MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX +-#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6 +-#undef MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX +-#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7 +-#undef MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS +-#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5 +-#undef MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS +-#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6 +-#undef MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS +-#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7 +- +-/* signals for i.MX6ULL only */ +-#define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0 +-#define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4 +-#define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5 +-#define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0 +-#define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0 +-#define MX6ULL_PAD_UART1_CTS_B__UART5_DTE_RTS 0x008C 0x0318 0x0640 0x9 0x3 +-#define MX6ULL_PAD_UART1_RTS_B__UART5_DCE_RTS 0x0090 0x031C 0x0640 0x9 0x4 +-#define MX6ULL_PAD_UART1_RTS_B__UART5_DTE_CTS 0x0090 0x031C 0x0000 0x9 0x0 +-#define MX6ULL_PAD_UART4_RX_DATA__EPDC_PWRCTRL01 0x00B8 0x0344 0x0000 0x9 0x0 +-#define MX6ULL_PAD_UART5_TX_DATA__EPDC_PWRCTRL02 0x00BC 0x0348 0x0000 0x9 0x0 +-#define MX6ULL_PAD_UART5_RX_DATA__EPDC_PWRCTRL03 0x00C0 0x034C 0x0000 0x9 0x0 +-#define MX6ULL_PAD_ENET1_RX_DATA0__EPDC_SDCE04 0x00C4 0x0350 0x0000 0x9 0x0 +-#define MX6ULL_PAD_ENET1_RX_DATA1__EPDC_SDCE05 0x00C8 0x0354 0x0000 0x9 0x0 +-#define MX6ULL_PAD_ENET1_RX_EN__EPDC_SDCE06 0x00CC 0x0358 0x0000 0x9 0x0 +-#define MX6ULL_PAD_ENET1_TX_DATA0__EPDC_SDCE07 0x00D0 0x035C 0x0000 0x9 0x0 +-#define MX6ULL_PAD_ENET1_TX_DATA1__EPDC_SDCE08 0x00D4 0x0360 0x0000 0x9 0x0 +-#define MX6ULL_PAD_ENET1_TX_EN__EPDC_SDCE09 0x00D8 0x0364 0x0000 0x9 0x0 +-#define MX6ULL_PAD_ENET1_TX_CLK__EPDC_SDOED 0x00DC 0x0368 0x0000 0x9 0x0 +-#define MX6ULL_PAD_ENET1_RX_ER__EPDC_SDOEZ 0x00E0 0x036C 0x0000 0x9 0x0 +-#define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0 +-#define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0 +-#define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0 +-#define MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0 +-#define MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0 +-#define MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0 +-#define MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0 +-#define MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE 0x010C 0x0398 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0 0x0110 0x039C 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_RESET__EPDC_GDOE 0x0114 0x03A0 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00 0x0118 0x03A4 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01 0x011C 0x03A8 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02 0x0120 0x03AC 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03 0x0124 0x03B0 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04 0x0128 0x03B4 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05 0x012C 0x03B8 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06 0x0130 0x03BC 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07 0x0134 0x03C0 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR 0x0150 0x03DC 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_DATA15__EPDC_GDRL 0x0154 0x03E0 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_DATA22__EPDC_SDCE02 0x0170 0x03FC 0x0000 0x9 0x0 +-#define MX6ULL_PAD_LCD_DATA23__EPDC_SDCE03 0x0174 0x0400 0x0000 0x9 0x0 +-#define MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0 +-#define MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0 +-#define MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0 +-#define MX6ULL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0 +-#define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0 +-#define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0 +-#define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0 +-#define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0 +-#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0 +-#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0 +-#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0 +-#define MX6ULL_PAD_CSI_DATA07__ESAI_TX0 0x0200 0x048C 0x0000 0x9 0x0 +- +-#endif /* __DTS_IMX6ULL_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm/imx6ull.dtsi b/scripts/dtc/include-prefixes/arm/imx6ull.dtsi +deleted file mode 100644 +index 9bf67490ac49..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ull.dtsi ++++ /dev/null +@@ -1,95 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright 2016 Freescale Semiconductor, Inc. +- +-#include "imx6ul.dtsi" +-#include "imx6ull-pinfunc.h" +-#include "imx6ull-pinfunc-snvs.h" +- +-/* Delete UART8 in AIPS-1 (i.MX6UL specific) */ +-/delete-node/ &uart8; +-/* Delete CAAM node in AIPS-2 (i.MX6UL specific) */ +-/delete-node/ &crypto; +- +-&cpu0 { +- clock-frequency = <900000000>; +- operating-points = < +- /* kHz uV */ +- 900000 1275000 +- 792000 1225000 +- 528000 1175000 +- 396000 1025000 +- 198000 950000 +- >; +- fsl,soc-operating-points = < +- /* KHz uV */ +- 900000 1250000 +- 792000 1175000 +- 528000 1175000 +- 396000 1175000 +- 198000 1175000 +- >; +-}; +- +-&ocotp { +- compatible = "fsl,imx6ull-ocotp", "syscon"; +-}; +- +-&pxp { +- compatible = "fsl,imx6ull-pxp"; +- interrupts = , +- ; +-}; +- +-&usdhc1 { +- compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; +-}; +- +-&usdhc2 { +- compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; +-}; +- +-/ { +- soc { +- aips3: bus@2200000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x02200000 0x100000>; +- ranges; +- +- dcp: crypto@2280000 { +- compatible = "fsl,imx6ull-dcp", "fsl,imx28-dcp"; +- reg = <0x02280000 0x4000>; +- interrupts = , +- , +- ; +- clocks = <&clks IMX6ULL_CLK_DCP_CLK>; +- clock-names = "dcp"; +- }; +- +- rngb: rng@2284000 { +- compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb"; +- reg = <0x02284000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_DUMMY>; +- }; +- +- iomuxc_snvs: iomuxc-snvs@2290000 { +- compatible = "fsl,imx6ull-iomuxc-snvs"; +- reg = <0x02290000 0x4000>; +- }; +- +- uart8: serial@2288000 { +- compatible = "fsl,imx6ul-uart", +- "fsl,imx6q-uart"; +- reg = <0x02288000 0x4000>; +- interrupts = ; +- clocks = <&clks IMX6UL_CLK_UART8_IPG>, +- <&clks IMX6UL_CLK_UART8_SERIAL>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ulz-14x14-evk.dts b/scripts/dtc/include-prefixes/arm/imx6ulz-14x14-evk.dts +deleted file mode 100644 +index 483d9732c002..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ulz-14x14-evk.dts ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright 2018 NXP. +- +-/dts-v1/; +- +-#include "imx6ulz.dtsi" +-#include "imx6ul-14x14-evk.dtsi" +- +-/delete-node/ &fec1; +-/delete-node/ &fec2; +-/delete-node/ &can1; +-/delete-node/ &can2; +-/delete-node/ &lcdif; +-/delete-node/ &tsc; +- +-/ { +- model = "Freescale i.MX6 ULZ 14x14 EVK Board"; +- compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz"; +- +- /delete-node/ panel; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx6ulz.dtsi b/scripts/dtc/include-prefixes/arm/imx6ulz.dtsi +deleted file mode 100644 +index 0b5f1a763567..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx6ulz.dtsi ++++ /dev/null +@@ -1,36 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright 2018 NXP. +- +-#include "imx6ull.dtsi" +- +-/ { +- aliases { +- /delete-property/ ethernet0; +- /delete-property/ ethernet1; +- /delete-property/ i2c2; +- /delete-property/ i2c3; +- /delete-property/ serial4; +- /delete-property/ serial5; +- /delete-property/ serial6; +- /delete-property/ serial7; +- /delete-property/ spi2; +- /delete-property/ spi3; +- }; +-}; +- +-/delete-node/ &adc1; +-/delete-node/ &ecspi3; +-/delete-node/ &ecspi4; +-/delete-node/ &epit2; +-/delete-node/ &gpt2; +-/delete-node/ &i2c3; +-/delete-node/ &i2c4; +-/delete-node/ &pwm5; +-/delete-node/ &pwm6; +-/delete-node/ &pwm7; +-/delete-node/ &pwm8; +-/delete-node/ &uart5; +-/delete-node/ &uart6; +-/delete-node/ &uart7; +-/delete-node/ &uart8; +diff --git a/scripts/dtc/include-prefixes/arm/imx7-colibri-aster.dtsi b/scripts/dtc/include-prefixes/arm/imx7-colibri-aster.dtsi +deleted file mode 100644 +index 139188eb9f40..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7-colibri-aster.dtsi ++++ /dev/null +@@ -1,169 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2017-2020 Toradex AG +- * +- */ +- +- +-#include +-#include +- +-/ { +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpiokeys>; +- +- power { +- label = "Wake-Up"; +- gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- panel: panel { +- compatible = "edt,et057090dhu"; +- backlight = <&bl>; +- power-supply = <®_3v3>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lcdif_out>; +- }; +- }; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_5v0: regulator-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usbh_vbus: regulator-usbh-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh_reg>; +- regulator-name = "VCC_USB[1-4]"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; +- vin-supply = <®_5v0>; +- }; +-}; +- +-&adc1 { +- status = "okay"; +-}; +- +-/* +- * ADC2 is not available on the Aster board and +- * conflicts with AD7879 resistive touchscreen. +- */ +-&adc2 { +- status = "disabled"; +-}; +- +-&bl { +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- power-supply = <®_3v3>; +- status = "okay"; +-}; +- +-&fec1 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +- +- /* Microchip/Atmel maxtouch controller */ +- touchscreen@4a { +- compatible = "atmel,maxtouch"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpiotouch>; +- reg = <0x4a>; +- interrupt-parent = <&gpio2>; +- interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ +- reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* SODIMM 106 */ +- }; +- +- /* M41T0M6 real time clock on carrier board */ +- rtc: m41t0m6@68 { +- compatible = "st,m41t0"; +- reg = <0x68>; +- }; +-}; +- +-&iomuxc { +- pinctrl_gpiotouch: touchgpios { +- fsl,pins = < +- MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 +- MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 +- >; +- }; +-}; +- +-&lcdif { +- status = "okay"; +- +- port { +- lcdif_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&pwm3 { +- status = "okay"; +-}; +- +-&pwm4 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&usbotg1 { +- status = "okay"; +-}; +- +-&usdhc1 { +- keep-power-in-suspend; +- no-1-8-v; +- wakeup-source; +- vmmc-supply = <®_3v3>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7-colibri-eval-v3.dtsi b/scripts/dtc/include-prefixes/arm/imx7-colibri-eval-v3.dtsi +deleted file mode 100644 +index 3caf450735d7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7-colibri-eval-v3.dtsi ++++ /dev/null +@@ -1,194 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2016-2020 Toradex +- */ +- +-/ { +- aliases { +- rtc0 = &rtc; +- rtc1 = &snvs_rtc; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- /* fixed crystal dedicated to mpc258x */ +- clk16m: clk16m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <16000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpiokeys>; +- +- power { +- label = "Wake-Up"; +- gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- panel: panel { +- compatible = "edt,et057090dhu"; +- backlight = <&bl>; +- power-supply = <®_3v3>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lcdif_out>; +- }; +- }; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_5v0: regulator-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usbh_vbus: regulator-usbh-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh_reg>; +- regulator-name = "VCC_USB[1-4]"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; +- vin-supply = <®_5v0>; +- }; +-}; +- +-&bl { +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- power-supply = <®_3v3>; +- +- status = "okay"; +-}; +- +-&adc1 { +- status = "okay"; +-}; +- +-&adc2 { +- status = "okay"; +-}; +- +-&ecspi3 { +- status = "okay"; +- +- mcp2515: can@0 { +- compatible = "microchip,mcp2515"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can_int>; +- reg = <0>; +- clocks = <&clk16m>; +- interrupt-parent = <&gpio5>; +- interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +- spi-max-frequency = <10000000>; +- vdd-supply = <®_3v3>; +- xceiver-supply = <®_5v0>; +- status = "okay"; +- }; +-}; +- +-&fec1 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +- +- /* +- * Touchscreen is using SODIMM 28/30, also used for PWM, PWM, +- * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms +- */ +- touchscreen@4a { +- compatible = "atmel,maxtouch"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpiotouch>; +- reg = <0x4a>; +- interrupt-parent = <&gpio1>; +- interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */ +- reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 */ +- status = "disabled"; +- }; +- +- /* M41T0M6 real time clock on carrier board */ +- rtc: m41t0m6@68 { +- compatible = "st,m41t0"; +- reg = <0x68>; +- }; +-}; +- +-&lcdif { +- status = "okay"; +- +- port { +- lcdif_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&pwm3 { +- status = "okay"; +-}; +- +-&pwm4 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&usbotg1 { +- status = "okay"; +-}; +- +-&usdhc1 { +- keep-power-in-suspend; +- wakeup-source; +- vmmc-supply = <®_3v3>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_gpiotouch: touchgpios { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74 +- MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7-colibri.dtsi b/scripts/dtc/include-prefixes/arm/imx7-colibri.dtsi +deleted file mode 100644 +index 62b771c1d5a9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7-colibri.dtsi ++++ /dev/null +@@ -1,941 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2016-2020 Toradex +- */ +- +-/ { +- bl: backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_bl_on>; +- pwms = <&pwm1 0 5000000 0>; +- enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_module_3v3: regulator-module-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_module_3v3_avdd: regulator-module-3v3-avdd { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3_AVDD_AUDIO"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "imx7-sgtl5000"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&dailink_master>; +- simple-audio-card,frame-master = <&dailink_master>; +- simple-audio-card,cpu { +- sound-dai = <&sai1>; +- }; +- +- dailink_master: simple-audio-card,codec { +- sound-dai = <&codec>; +- clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; +- }; +- }; +-}; +- +-&adc1 { +- vref-supply = <®_DCDC3>; +-}; +- +-&adc2 { +- vref-supply = <®_DCDC3>; +-}; +- +-&cpu0 { +- cpu-supply = <®_DCDC2>; +-}; +- +-&ecspi3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; +- cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; +-}; +- +-&fec1 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&pinctrl_enet1>; +- pinctrl-1 = <&pinctrl_enet1_sleep>; +- clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, +- <&clks IMX7D_ENET_AXI_ROOT_CLK>, +- <&clks IMX7D_ENET1_TIME_ROOT_CLK>, +- <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>; +- clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; +- assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, +- <&clks IMX7D_ENET1_TIME_ROOT_CLK>; +- assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; +- assigned-clock-rates = <0>, <100000000>; +- phy-mode = "rmii"; +- phy-supply = <®_LDO1>; +- fsl,magic-packet; +-}; +- +-&flexcan1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- status = "disabled"; +-}; +- +-&flexcan2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- status = "disabled"; +-}; +- +-&gpio1 { +- gpio-line-names = "SODIMM_43", +- "SODIMM_45", +- "SODIMM_135", +- "SODIMM_22", +- "", +- "", +- "SODIMM_37", +- "SODIMM_29", +- "SODIMM_59", +- "SODIMM_28", +- "SODIMM_30", +- "SODIMM_67", +- "", +- "", +- "SODIMM_188", +- "SODIMM_178"; +-}; +- +-&gpio2 { +- gpio-line-names = "SODIMM_111", +- "SODIMM_113", +- "SODIMM_115", +- "SODIMM_117", +- "SODIMM_119", +- "SODIMM_121", +- "SODIMM_123", +- "SODIMM_125", +- "SODIMM_91", +- "SODIMM_89", +- "SODIMM_105", +- "SODIMM_152", +- "SODIMM_150", +- "SODIMM_95", +- "SODIMM_126", +- "SODIMM_107", +- "SODIMM_114", +- "SODIMM_116", +- "SODIMM_118", +- "SODIMM_120", +- "SODIMM_122", +- "SODIMM_124", +- "SODIMM_127", +- "SODIMM_130", +- "SODIMM_132", +- "SODIMM_134", +- "SODIMM_133", +- "SODIMM_104", +- "SODIMM_106", +- "SODIMM_110", +- "SODIMM_112", +- "SODIMM_128"; +-}; +- +-&gpio3 { +- gpio-line-names = "SODIMM_56", +- "SODIMM_44", +- "SODIMM_68", +- "SODIMM_82", +- "SODIMM_93", +- "SODIMM_76", +- "SODIMM_70", +- "SODIMM_60", +- "SODIMM_58", +- "SODIMM_78", +- "SODIMM_72", +- "SODIMM_80", +- "SODIMM_46", +- "SODIMM_62", +- "SODIMM_48", +- "SODIMM_74", +- "SODIMM_50", +- "SODIMM_52", +- "SODIMM_54", +- "SODIMM_66", +- "SODIMM_64", +- "SODIMM_57", +- "SODIMM_61", +- "SODIMM_136", +- "SODIMM_138", +- "SODIMM_140", +- "SODIMM_142", +- "SODIMM_144", +- "SODIMM_146"; +-}; +- +-&gpio4 { +- gpio-line-names = "SODIMM_35", +- "SODIMM_33", +- "SODIMM_38", +- "SODIMM_36", +- "SODIMM_21", +- "SODIMM_19", +- "SODIMM_131", +- "SODIMM_129", +- "SODIMM_90", +- "SODIMM_92", +- "SODIMM_88", +- "SODIMM_86", +- "SODIMM_81", +- "SODIMM_94", +- "SODIMM_96", +- "SODIMM_75", +- "SODIMM_101", +- "SODIMM_103", +- "SODIMM_79", +- "SODIMM_97", +- "SODIMM_67", +- "SODIMM_59", +- "SODIMM_85", +- "SODIMM_65"; +-}; +- +-&gpio5 { +- gpio-line-names = "SODIMM_69", +- "SODIMM_71", +- "SODIMM_73", +- "SODIMM_47", +- "SODIMM_190", +- "SODIMM_192", +- "SODIMM_49", +- "SODIMM_51", +- "SODIMM_53", +- "", +- "", +- "SODIMM_98", +- "SODIMM_184", +- "SODIMM_186", +- "SODIMM_23", +- "SODIMM_31", +- "SODIMM_100", +- "SODIMM_102"; +-}; +- +-&gpio6 { +- gpio-line-names = "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "SODIMM_169", +- "", +- "", +- "", +- "SODIMM_77", +- "SODIMM_24", +- "", +- "SODIMM_25", +- "SODIMM_27", +- "SODIMM_32", +- "SODIMM_34"; +-}; +- +-&gpio7 { +- gpio-line-names = "", +- "", +- "SODIMM_63", +- "SODIMM_55", +- "", +- "", +- "", +- "", +- "SODIMM_196", +- "SODIMM_194", +- "", +- "SODIMM_99", +- "", +- "", +- "SODIMM_137"; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- fsl,use-minimum-ecc; +- nand-on-flash-bbt; +- nand-ecc-mode = "hw"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>; +- pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>; +- scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- +- status = "okay"; +- +- codec: sgtl5000@a { +- compatible = "fsl,sgtl5000"; +- #sound-dai-cells = <0>; +- reg = <0x0a>; +- clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai1_mclk>; +- VDDA-supply = <®_module_3v3_avdd>; +- VDDIO-supply = <®_module_3v3>; +- VDDD-supply = <®_DCDC3>; +- }; +- +- ad7879@2c { +- compatible = "adi,ad7879-1"; +- reg = <0x2c>; +- interrupt-parent = <&gpio1>; +- interrupts = <13 IRQ_TYPE_EDGE_FALLING>; +- touchscreen-max-pressure = <4096>; +- adi,resistance-plate-x = <120>; +- adi,first-conversion-delay = /bits/ 8 <3>; +- adi,acquisition-time = /bits/ 8 <1>; +- adi,median-filter-size = /bits/ 8 <2>; +- adi,averaging = /bits/ 8 <1>; +- adi,conversion-interval = /bits/ 8 <255>; +- }; +- +- pmic@33 { +- compatible = "ricoh,rn5t567"; +- reg = <0x33>; +- +- regulators { +- reg_DCDC1: DCDC1 { /* V1.0_SOC */ +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1100000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_DCDC2: DCDC2 { /* V1.1_ARM */ +- regulator-min-microvolt = <975000>; +- regulator-max-microvolt = <1100000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_DCDC3: DCDC3 { /* V1.8 */ +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_DCDC4: DCDC4 { /* V1.35_DRAM */ +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */ +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- +- reg_LDO2: LDO2 { /* +V1.8_SD */ +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */ +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_LDO4: LDO4 { /* V1.8_LPSR */ +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */ +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c4 { +- clock-frequency = <100000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c4>; +- pinctrl-1 = <&pinctrl_i2c4_recovery>; +- scl-gpios = <&gpio7 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio7 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +-}; +- +-&lcdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcdif_dat +- &pinctrl_lcdif_ctrl>; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +-}; +- +-&pwm4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +-}; +- +-®_1p0d { +- vin-supply = <®_DCDC3>; +-}; +- +-&sai1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai1>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>; +- assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +- uart-has-rtscts; +- fsl,dte-mode; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +- uart-has-rtscts; +- fsl,dte-mode; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +- fsl,dte-mode; +-}; +- +-&usbotg1 { +- dr_mode = "host"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; +- cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; +- disable-wp; +- vqmmc-supply = <®_LDO2>; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; +- assigned-clock-rates = <400000000>; +- bus-width = <8>; +- fsl,tuning-step = <2>; +- vmmc-supply = <®_module_3v3>; +- vqmmc-supply = <®_DCDC3>; +- non-removable; +- sdhci-caps-mask = <0x80000000 0x0>; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4 +- &pinctrl_gpio7 &pinctrl_usbc_det>; +- +- pinctrl_gpio1: gpio1-grp { +- fsl,pins = < +- MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */ +- MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */ +- MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */ +- MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */ +- MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */ +- MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */ +- MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */ +- MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */ +- MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */ +- MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */ +- MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */ +- MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */ +- MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */ +- MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */ +- MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */ +- MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */ +- MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */ +- MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */ +- MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */ +- MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */ +- MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */ +- MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */ +- MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */ +- MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */ +- MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */ +- MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */ +- MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */ +- MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */ +- MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */ +- MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */ +- MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */ +- MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */ +- MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */ +- MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */ +- MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */ +- MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */ +- MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */ +- MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */ +- MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */ +- MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */ +- >; +- }; +- +- pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */ +- fsl,pins = < +- MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */ +- MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */ +- MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */ +- MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */ +- MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */ +- MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */ +- MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */ +- MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */ +- MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */ +- MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */ +- MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */ +- MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */ +- >; +- }; +- +- pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */ +- fsl,pins = < +- MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */ +- MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */ +- MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */ +- MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */ +- MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */ +- MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */ +- >; +- }; +- +- pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */ +- fsl,pins = < +- MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */ +- MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */ +- >; +- }; +- +- pinctrl_gpio7: gpio7-grp { /* Alternatively CAN1 */ +- fsl,pins = < +- MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */ +- MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */ +- >; +- }; +- +- pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */ +- fsl,pins = < +- MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79 +- >; +- }; +- +- pinctrl_can_int: can-int-grp { +- fsl,pins = < +- MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */ +- >; +- }; +- +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73 +- MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73 +- MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73 +- MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73 +- +- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73 +- MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73 +- MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73 +- MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x73 +- MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 +- MX7D_PAD_SD2_WP__ENET1_MDC 0x3 +- >; +- }; +- +- pinctrl_enet1_sleep: enet1sleepgrp { +- fsl,pins = < +- MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0 +- MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x0 +- MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0 +- MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0 +- +- MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0 +- MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0 +- MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0 +- MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0 +- MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x0 +- MX7D_PAD_SD2_WP__GPIO5_IO10 0x0 +- >; +- }; +- +- pinctrl_ecspi3_cs: ecspi3-cs-grp { +- fsl,pins = < +- MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 +- >; +- }; +- +- pinctrl_ecspi3: ecspi3-grp { +- fsl,pins = < +- MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 +- MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 +- MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1-grp { +- fsl,pins = < +- MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x79 /* SODIMM 55 */ +- MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x79 /* SODIMM 63 */ +- >; +- }; +- +- pinctrl_flexcan2: flexcan2-grp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x79 /* SODIMM 188 */ +- MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x79 /* SODIMM 178 */ +- >; +- }; +- +- pinctrl_gpio_bl_on: gpio-bl-on { +- fsl,pins = < +- MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */ +- >; +- }; +- +- pinctrl_gpmi_nand: gpmi-nand-grp { +- fsl,pins = < +- MX7D_PAD_SD3_CLK__NAND_CLE 0x71 +- MX7D_PAD_SD3_CMD__NAND_ALE 0x71 +- MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 +- MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 +- MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 +- MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 +- MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 +- MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 +- MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 +- MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 +- MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 +- MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 +- MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 +- MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 +- >; +- }; +- +- pinctrl_i2c4: i2c4-grp { +- fsl,pins = < +- MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f +- MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f +- >; +- }; +- +- pinctrl_i2c4_recovery: i2c4-recoverygrp { +- fsl,pins = < +- MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f +- MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f +- >; +- }; +- +- pinctrl_lcdif_dat: lcdif-dat-grp { +- fsl,pins = < +- MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 +- MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 +- MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 +- MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 +- MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 +- MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 +- MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 +- MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 +- MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 +- MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 +- MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 +- MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 +- MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 +- MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 +- MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 +- MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 +- MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 +- MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 +- >; +- }; +- +- pinctrl_lcdif_dat_24: lcdif-dat-24-grp { +- fsl,pins = < +- MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 +- MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 +- MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 +- MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 +- MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 +- MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 +- >; +- }; +- +- pinctrl_lcdif_ctrl: lcdif-ctrl-grp { +- fsl,pins = < +- MX7D_PAD_LCD_CLK__LCD_CLK 0x79 +- MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 +- MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 +- MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 +- >; +- }; +- +- pinctrl_pwm1: pwm1-grp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79 +- MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4 +- >; +- }; +- +- pinctrl_pwm2: pwm2-grp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79 +- >; +- }; +- +- pinctrl_pwm3: pwm3-grp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79 +- >; +- }; +- +- pinctrl_pwm4: pwm4-grp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79 +- MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4 +- >; +- }; +- +- pinctrl_uart1: uart1-grp { +- fsl,pins = < +- MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 +- MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 +- MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 +- MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 +- >; +- }; +- +- pinctrl_uart1_ctrl1: uart1-ctrl1-grp { +- fsl,pins = < +- MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */ +- MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */ +- >; +- }; +- +- pinctrl_uart2: uart2-grp { +- fsl,pins = < +- MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79 +- MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79 +- MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79 +- MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79 +- >; +- }; +- pinctrl_uart3: uart3-grp { +- fsl,pins = < +- MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 +- MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 +- >; +- }; +- +- pinctrl_usbc_det: gpio-usbc-det { +- fsl,pins = < +- MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 +- >; +- }; +- +- pinctrl_usbh_reg: gpio-usbh-vbus { +- fsl,pins = < +- MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */ +- >; +- }; +- +- pinctrl_usdhc1: usdhc1-grp { +- fsl,pins = < +- MX7D_PAD_SD1_CMD__SD1_CMD 0x59 +- MX7D_PAD_SD1_CLK__SD1_CLK 0x19 +- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 +- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 +- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 +- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { +- fsl,pins = < +- MX7D_PAD_SD1_CMD__SD1_CMD 0x5a +- MX7D_PAD_SD1_CLK__SD1_CLK 0x1a +- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a +- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a +- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a +- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { +- fsl,pins = < +- MX7D_PAD_SD1_CMD__SD1_CMD 0x5b +- MX7D_PAD_SD1_CLK__SD1_CLK 0x1b +- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b +- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b +- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b +- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x59 +- MX7D_PAD_SD3_CLK__SD3_CLK 0x19 +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 +- MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x5a +- MX7D_PAD_SD3_CLK__SD3_CLK 0x1a +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a +- MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x5b +- MX7D_PAD_SD3_CLK__SD3_CLK 0x1b +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b +- MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b +- >; +- }; +- +- pinctrl_sai1: sai1-grp { +- fsl,pins = < +- MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f +- MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f +- MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 +- MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f +- >; +- }; +- +- pinctrl_sai1_mclk: sai1grp_mclk { +- fsl,pins = < +- MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f +- >; +- }; +-}; +- +-&iomuxc_lpsr { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_lpsr>; +- +- pinctrl_gpio_lpsr: gpio1-grp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59 +- MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59 +- >; +- }; +- +- pinctrl_gpiokeys: gpiokeysgrp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19 +- >; +- }; +- +- pinctrl_i2c1: i2c1-grp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f +- MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f +- >; +- }; +- +- pinctrl_i2c1_recovery: i2c1-recoverygrp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f +- MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f +- >; +- }; +- +- pinctrl_cd_usdhc1: usdhc1-cd-grp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */ +- >; +- }; +- +- pinctrl_uart1_ctrl2: uart1-ctrl2-grp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 /* DSR */ +- MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 /* RI */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7-mba7.dtsi b/scripts/dtc/include-prefixes/arm/imx7-mba7.dtsi +deleted file mode 100644 +index 5e6bef230dc7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7-mba7.dtsi ++++ /dev/null +@@ -1,602 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Device Tree Include file for TQ Systems MBa7 carrier board. +- * +- * Copyright (C) 2016 TQ Systems GmbH +- * Author: Markus Niebel +- * Copyright (C) 2019 Bruno Thomsen +- * +- * Note: This file does not include nodes for all peripheral devices. +- * As device driver coverage increases additional nodes can be added. +- */ +- +-#include +-#include +- +-/ { +- aliases { +- mmc0 = &usdhc3; +- mmc1 = &usdhc1; +- /delete-property/ mmc2; +- }; +- +- beeper { +- compatible = "gpio-beeper"; +- gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>; +- }; +- +- chosen { +- stdout-path = &uart6; +- }; +- +- gpio_buttons: gpio-keys { +- compatible = "gpio-keys"; +- +- button-0 { +- /* #SWITCH_A */ +- label = "S11"; +- linux,code = ; +- gpios = <&pca9555 13 GPIO_ACTIVE_LOW>; +- }; +- +- button-1 { +- /* #SWITCH_B */ +- label = "S12"; +- linux,code = ; +- gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; +- }; +- +- button-2 { +- /* #SWITCH_C */ +- label = "S13"; +- linux,code = ; +- gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- led1 { +- label = "led1"; +- gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- +- led2 { +- label = "led2"; +- gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- reg_sd1_vmmc: regulator-sd1-vmmc { +- compatible = "regulator-fixed"; +- regulator-name = "VCC3V3_SD1"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_fec1_pwdn: regulator-fec1-pwdn { +- compatible = "regulator-fixed"; +- regulator-name = "PWDN_FEC1"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_fec2_pwdn: regulator-fec2-pwdn { +- compatible = "regulator-fixed"; +- regulator-name = "PWDN_FEC2"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_otg1_vbus: regulator-usb-otg1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "VBUS_USBOTG1"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_otg2_vbus: regulator-usb-otg2-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "VBUS_USBOTG2"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_mpcie_1v5: regulator-mpcie-1v5 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC1V5_MPCIE"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- reg_mpcie_3v3: regulator-mpcie-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC3V3_MPCIE"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- reg_mba_12v0: regulator-mba-12v0 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC12V0_MBA7"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- gpio = <&pca9555 11 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_lvds_transmitter: regulator-lvds-transmitter { +- compatible = "regulator-fixed"; +- regulator-name = "#SHTDN_LVDS"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&pca9555 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_vref_1v8: regulator-vref-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC1V8_REF"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- vin-supply = <&sw2_reg>; +- }; +- +- reg_audio_3v3: regulator-audio-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC3V3_AUDIO"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- sound { +- compatible = "fsl,imx-audio-tlv320aic32x4"; +- model = "imx-audio-tlv320aic32x4"; +- ssi-controller = <&sai1>; +- audio-codec = <&tlv320aic32x4>; +- audio-routing = +- "IN3_L", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "IN1_L", "Line In Jack", +- "IN1_R", "Line In Jack", +- "Line Out Jack", "LOL", +- "Line Out Jack", "LOR"; +- }; +-}; +- +-&adc1 { +- vref-supply = <®_vref_1v8>; +- status = "okay"; +-}; +- +-&adc2 { +- vref-supply = <®_vref_1v8>; +- status = "okay"; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>, +- <&gpio4 2 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- phy-mode = "rgmii-id"; +- phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <1>; +- phy-supply = <®_fec1_pwdn>; +- phy-handle = <ðphy1_0>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy1_0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- ti,rx-internal-delay = ; +- ti,tx-internal-delay = ; +- ti,fifo-depth = ; +- ti,clk-output-sel = ; +- }; +- }; +-}; +- +-&flexcan1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- status = "okay"; +-}; +- +-&flexcan2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- status = "okay"; +-}; +- +-&i2c1 { +- lm75: temperature-sensor@49 { +- compatible = "national,lm75"; +- reg = <0x49>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- tlv320aic32x4: audio-codec@18 { +- compatible = "ti,tlv320aic32x4"; +- reg = <0x18>; +- clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; +- clock-names = "mclk"; +- ldoin-supply = <®_audio_3v3>; +- iov-supply = <®_audio_3v3>; +- }; +- +- pca9555: gpio-expander@20 { +- compatible = "nxp,pca9555"; +- reg = <0x20>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pca9555>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gpio7>; +- interrupts = <12 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog_mba7_1>; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c +- MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74 +- MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74 +- MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74 +- MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74 +- MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c +- MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74 +- MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74 +- MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74 +- >; +- }; +- +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02 +- MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00 +- MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71 +- MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 +- MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 +- MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71 +- MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71 +- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 +- MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79 +- MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79 +- MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79 +- MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79 +- MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79 +- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79 +- /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */ +- MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070 +- /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */ +- MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a +- MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a +- MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52 +- >; +- }; +- +- pinctrl_hog_mba7_1: hogmba71grp { +- fsl,pins = < +- /* Limitation: WDOG2_B / WDOG2_RESET not usable */ +- MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c +- MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074 +- /* #BOOT_EN */ +- MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078 +- MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078 +- MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078 +- >; +- }; +- +- pinctrl_pca9555: pca95550grp { +- fsl,pins = < +- MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78 +- >; +- }; +- +- pinctrl_sai1: sai1grp { +- fsl,pins = < +- MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11 +- MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c +- MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c +- MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c +- +- MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c +- MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14 +- MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e +- MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76 +- MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76 +- MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e +- MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76 +- MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76 +- MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e +- MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76 +- >; +- }; +- +- pinctrl_uart6: uart6grp { +- fsl,pins = < +- MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d +- MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75 +- MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75 +- MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d +- >; +- }; +- +- pinctrl_uart7: uart7grp { +- fsl,pins = < +- MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e +- MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76 +- MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76 +- /* Limitation: RTS is not connected */ +- MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e +- >; +- }; +- +- pinctrl_usdhc1_gpio: usdhc1grp_gpio { +- fsl,pins = < +- /* WP */ +- MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c +- /* CD */ +- MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c +- /* VSELECT */ +- MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX7D_PAD_SD1_CMD__SD1_CMD 0x5e +- MX7D_PAD_SD1_CLK__SD1_CLK 0x57 +- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e +- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e +- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e +- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { +- fsl,pins = < +- MX7D_PAD_SD1_CMD__SD1_CMD 0x5a +- MX7D_PAD_SD1_CLK__SD1_CLK 0x57 +- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a +- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a +- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a +- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { +- fsl,pins = < +- MX7D_PAD_SD1_CMD__SD1_CMD 0x5b +- MX7D_PAD_SD1_CLK__SD1_CLK 0x57 +- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b +- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b +- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b +- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b +- >; +- }; +-}; +- +-&iomuxc_lpsr { +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- /* LCD_CONTRAST */ +- MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50 +- >; +- }; +- +- pinctrl_usbotg1: usbotg1grp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c +- MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 +- >; +- }; +- +- pinctrl_wdog1: wdog1grp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 +- >; +- }; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&sai1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai1>; +- assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, +- <&clks IMX7D_SAI1_ROOT_CLK>; +- assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; +- assigned-clock-rates = <0>, <36864000>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +- status = "okay"; +-}; +- +-&uart6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart6>; +- assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +- status = "okay"; +-}; +- +-&uart7 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart7>; +- assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +- uart-has-rtscts; +- linux,rs485-enabled-at-boot-time; +- rs485-rts-active-low; +- rs485-rx-during-tx; +- status = "okay"; +-}; +- +-&usbh { +- status = "okay"; +-}; +- +-&usbotg1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg1>; +- vbus-supply = <®_usb_otg1_vbus>; +- srp-disable; +- hnp-disable; +- adp-disable; +- over-current-active-low; +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; +- cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; +- vmmc-supply = <®_sd1_vmmc>; +- bus-width = <4>; +- no-1-8-v; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog1>; +- fsl,ext-reset-output; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7-tqma7.dtsi b/scripts/dtc/include-prefixes/arm/imx7-tqma7.dtsi +deleted file mode 100644 +index 8773344b54aa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7-tqma7.dtsi ++++ /dev/null +@@ -1,249 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Device Tree Include file for TQ Systems TQMa7x boards with full mounted PCB. +- * +- * Copyright (C) 2016 TQ Systems GmbH +- * Author: Markus Niebel +- * Copyright (C) 2019 Bruno Thomsen +- */ +- +-/ { +- memory@80000000 { +- device_type = "memory"; +- /* 512 MB - default configuration */ +- reg = <0x80000000 0x20000000>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&sw1a_reg>; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clock-frequency = <100000>; +- status = "okay"; +- +- pfuze3000: pmic@8 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic1>; +- compatible = "fsl,pfuze3000"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1a { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- /* use sw1c_reg to align with pfuze100/pfuze200 */ +- sw1c_reg: sw1b { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1475000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1650000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen2_reg: vldo2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- regulator-always-on; +- }; +- +- vgen3_reg: vccsd { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen4_reg: v33 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vldo3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vldo4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +- +- /* NXP SE97BTP with temperature sensor + eeprom */ +- se97b: temperature-sensor-eeprom@1e { +- compatible = "nxp,se97b", "jedec,jc-42.4-temp"; +- reg = <0x1e>; +- status = "okay"; +- }; +- +- /* ST M24C64 */ +- m24c64: eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- pagesize = <32>; +- status = "okay"; +- }; +- +- at24c02: eeprom@56 { +- compatible = "atmel,24c02"; +- reg = <0x56>; +- pagesize = <16>; +- status = "okay"; +- }; +- +- ds1339: rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +-}; +- +-&iomuxc { +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078 +- MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078 +- >; +- }; +- +- pinctrl_pmic1: pmic1grp { +- fsl,pins = < +- MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x59 +- MX7D_PAD_SD3_CLK__SD3_CLK 0x56 +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 +- MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x5a +- MX7D_PAD_SD3_CLK__SD3_CLK 0x51 +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a +- MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x5b +- MX7D_PAD_SD3_CLK__SD3_CLK 0x51 +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b +- MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b +- >; +- }; +-}; +- +-&iomuxc_lpsr { +- pinctrl_wdog1: wdog1grp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 +- >; +- }; +-}; +- +-&sdma { +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; +- assigned-clock-rates = <400000000>; +- bus-width = <8>; +- non-removable; +- vmmc-supply = <&vgen4_reg>; +- vqmmc-supply = <&sw2_reg>; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog1>; +- /* +- * Errata e10574: +- * WDOG reset needs to run with WDOG_RESET_B signal enabled. +- * X1-51 (WDOG1#) signal needs carrier board handling to reset +- * TQMa7 on X1-22 (RESET_IN#). +- */ +- fsl,ext-reset-output; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-cl-som-imx7.dts b/scripts/dtc/include-prefixes/arm/imx7d-cl-som-imx7.dts +deleted file mode 100644 +index 713483c39c9d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-cl-som-imx7.dts ++++ /dev/null +@@ -1,294 +0,0 @@ +-/* +- * Support for CompuLab CL-SOM-iMX7 System-on-Module +- * +- * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ +- * Author: Ilya Ledvich +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- */ +- +-/dts-v1/; +- +-#include "imx7d.dtsi" +- +-/ { +- model = "CompuLab CL-SOM-iMX7"; +- compatible = "compulab,cl-som-imx7", "fsl,imx7d"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */ +- }; +- +- reg_usb_otg1_vbus: regulator-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&sw1a_reg>; +-}; +- +-&cpu1 { +- cpu-supply = <&sw1a_reg>; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, +- <&clks IMX7D_ENET1_TIME_ROOT_CLK>; +- assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; +- assigned-clock-rates = <0>, <100000000>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +- }; +-}; +- +-&fec2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet2>; +- assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, +- <&clks IMX7D_ENET2_TIME_ROOT_CLK>; +- assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; +- assigned-clock-rates = <0>, <100000000>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy1>; +- fsl,magic-packet; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- pmic: pmic@8 { +- compatible = "fsl,pfuze3000"; +- reg = <0x8>; +- +- regulators { +- sw1a_reg: sw1a { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- /* use sw1c_reg to align with pfuze100/pfuze200 */ +- sw1c_reg: sw1b { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1475000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1650000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen2_reg: vldo2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vccsd { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen4_reg: v33 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vldo3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vldo4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +- +- pca9555: pca9555@20 { +- compatible = "nxp,pca9555"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x20>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c08"; +- reg = <0x50>; +- pagesize = <16>; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; +- status = "okay"; +-}; +- +-&usbotg1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg1>; +- vbus-supply = <®_usb_otg1_vbus>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; +- assigned-clock-rates = <400000000>; +- bus-width = <8>; +- fsl,tuning-step = <2>; +- non-removable; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x30 +- MX7D_PAD_SD2_WP__ENET1_MDC 0x30 +- MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x11 +- MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x11 +- MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x11 +- MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x11 +- MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x11 +- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x11 +- MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x11 +- MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11 +- MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11 +- MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11 +- MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x11 +- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11 +- >; +- }; +- +- pinctrl_enet2: enet2grp { +- fsl,pins = < +- MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x11 +- MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x11 +- MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x11 +- MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x11 +- MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x11 +- MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x11 +- MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x11 +- MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x11 +- MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x11 +- MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x11 +- MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x11 +- MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x11 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f +- MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 +- MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x59 +- MX7D_PAD_SD3_CLK__SD3_CLK 0x19 +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 +- MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 +- >; +- }; +-}; +- +-&iomuxc_lpsr { +- pinctrl_usbotg1: usbotg1grp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 /* OTG PWREN */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-colibri-aster.dts b/scripts/dtc/include-prefixes/arm/imx7d-colibri-aster.dts +deleted file mode 100644 +index f3f0537d5a37..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-colibri-aster.dts ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2017-2020 Toradex AG +- * +- */ +- +-/dts-v1/; +-#include "imx7d-colibri.dtsi" +-#include "imx7-colibri-aster.dtsi" +- +-/ { +- model = "Toradex Colibri iMX7D on Aster Carrier Board"; +- compatible = "toradex,colibri-imx7d-aster", "toradex,colibri-imx7d", +- "fsl,imx7d"; +-}; +- +-&usbotg2 { +- vbus-supply = <®_usbh_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-colibri-emmc-aster.dts b/scripts/dtc/include-prefixes/arm/imx7d-colibri-emmc-aster.dts +deleted file mode 100644 +index 20480276cb0e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-colibri-emmc-aster.dts ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2017-2020 Toradex AG +- * +- */ +- +-/dts-v1/; +-#include "imx7d-colibri-emmc.dtsi" +-#include "imx7-colibri-aster.dtsi" +- +-/ { +- model = "Toradex Colibri iMX7D 1GB (eMMC) on Aster Carrier Board"; +- compatible = "toradex,colibri-imx7d-emmc-aster", +- "toradex,colibri-imx7d-emmc", "fsl,imx7d"; +-}; +- +-&usbotg2 { +- vbus-supply = <®_usbh_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-colibri-emmc-eval-v3.dts b/scripts/dtc/include-prefixes/arm/imx7d-colibri-emmc-eval-v3.dts +deleted file mode 100644 +index 8ee73c870b12..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-colibri-emmc-eval-v3.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2017 Toradex AG +- */ +- +-/dts-v1/; +-#include "imx7d-colibri-emmc.dtsi" +-#include "imx7-colibri-eval-v3.dtsi" +- +-/ { +- model = "Toradex Colibri iMX7D 1GB (eMMC) on Colibri Evaluation Board V3"; +- compatible = "toradex,colibri-imx7d-emmc-eval-v3", +- "toradex,colibri-imx7d-emmc", "fsl,imx7d"; +-}; +- +-&usbotg2 { +- vbus-supply = <®_usbh_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-colibri-emmc.dtsi b/scripts/dtc/include-prefixes/arm/imx7d-colibri-emmc.dtsi +deleted file mode 100644 +index af39e5370fa1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-colibri-emmc.dtsi ++++ /dev/null +@@ -1,48 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2017 Toradex AG +- */ +- +-#include "imx7d.dtsi" +-#include "imx7-colibri.dtsi" +- +-/ { +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; +- }; +-}; +- +-&gpio6 { +- gpio-line-names = "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "SODIMM_169", +- "SODIMM_157", +- "", +- "SODIMM_163", +- "SODIMM_77", +- "SODIMM_24", +- "", +- "SODIMM_25", +- "SODIMM_27", +- "SODIMM_32", +- "SODIMM_34"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +-}; +- +-&usdhc3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-colibri-eval-v3.dts b/scripts/dtc/include-prefixes/arm/imx7d-colibri-eval-v3.dts +deleted file mode 100644 +index 87b132bcd272..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-colibri-eval-v3.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2016-2020 Toradex +- */ +- +-/dts-v1/; +-#include "imx7d-colibri.dtsi" +-#include "imx7-colibri-eval-v3.dtsi" +- +-/ { +- model = "Toradex Colibri iMX7D on Colibri Evaluation Board V3"; +- compatible = "toradex,colibri-imx7d-eval-v3", "toradex,colibri-imx7d", +- "fsl,imx7d"; +-}; +- +-&usbotg2 { +- vbus-supply = <®_usbh_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-colibri.dtsi b/scripts/dtc/include-prefixes/arm/imx7d-colibri.dtsi +deleted file mode 100644 +index 219a0404a058..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-colibri.dtsi ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2016-2020 Toradex +- */ +- +-#include "imx7d.dtsi" +-#include "imx7-colibri.dtsi" +- +-/ { +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +-}; +- +-&cpu1 { +- cpu-supply = <®_DCDC2>; +-}; +- +-&gpmi { +- status = "okay"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-flex-concentrator-mfg.dts b/scripts/dtc/include-prefixes/arm/imx7d-flex-concentrator-mfg.dts +deleted file mode 100644 +index a6d68165fb1e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-flex-concentrator-mfg.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for Kamstrup OMNIA Flex Concentrator in +- * manufacturing/debugging mode. +- * +- * Copyright (C) 2020 Kamstrup A/S +- * Author: Bruno Thomsen +- */ +- +-/dts-v1/; +- +-#include "imx7d-flex-concentrator.dts" +- +-/ { +- model = "Kamstrup OMNIA Flex Concentrator - Manufacturing"; +- compatible = "kam,imx7d-flex-concentrator-mfg", "fsl,imx7d"; +- +- chosen { +- stdout-path = &uart4; +- }; +-}; +- +-&uart4 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-flex-concentrator.dts b/scripts/dtc/include-prefixes/arm/imx7d-flex-concentrator.dts +deleted file mode 100644 +index bd6b5285aa8d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-flex-concentrator.dts ++++ /dev/null +@@ -1,315 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for Kamstrup OMNIA Flex Concentrator. +- * +- * Copyright (C) 2020 Kamstrup A/S +- * Author: Bruno Thomsen +- */ +- +-/dts-v1/; +- +-#include "imx7d-tqma7.dtsi" +- +-/* One I2C device on TQMa7 SoM is not mounted */ +-/delete-node/ &ds1339; +- +-/ { +- model = "Kamstrup OMNIA Flex Concentrator"; +- compatible = "kam,imx7d-flex-concentrator", "fsl,imx7d"; +- +- memory@80000000 { +- device_type = "memory"; +- /* 1024 MB - TQMa7D board configuration */ +- reg = <0x80000000 0x40000000>; +- }; +- +- reg_usb_otg2_vbus: regulator-usb-otg2-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "VBUS_USBOTG2"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_vref_1v8: regulator-vref-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC1V8_REF"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- vin-supply = <&sw2_reg>; +- }; +- +- /* +- * Human Machine Interface consists of 4 dual red/green LEDs. +- * hmi-a:green is controlled directly by the switch-mode power supply. +- * hmi-a:red is not used. +- */ +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds>; +- +- led-0 { +- label = "hmi-b:red:heartbeat-degraded"; +- gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>; +- }; +- +- led-1 { +- label = "hmi-b:green:heartbeat-running"; +- gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-2 { +- label = "hmi-c:red:mesh-error"; +- gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; +- }; +- +- led-3 { +- label = "hmi-c:green:mesh-activity"; +- gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; +- }; +- +- led-4 { +- label = "hmi-d:red:omnia-error"; +- gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; +- }; +- +- led-5 { +- label = "hmi-d:green:omnia-activity"; +- gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- /* +- * Errata e10574 board restart workaround. +- */ +- gpio-restart { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_restart>; +- compatible = "gpio-restart"; +- gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; +- priority = <200>; +- }; +-}; +- +-/* +- * Analog signals +- * ADC1_IN0: SMPS - 5V output monitor (voltage divider: 1/0.2806) +- */ +-&adc1 { +- vref-supply = <®_vref_1v8>; +- status = "okay"; +-}; +- +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- num-chipselects = <1>; +- cs-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- pcf2127: rtc@0 { +- compatible = "nxp,pcf2127"; +- reg = <0>; +- spi-max-frequency = <2000000>; +- reset-source; +- }; +-}; +- +-&ecspi4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi4>; +- num-chipselects = <1>; +- cs-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- /* +- * ST chip maximum SPI clock frequency is 33 MHz. +- * +- * TCG specification - Section 6.4.1 Clocking: +- * TPM shall support a SPI clock frequency range of 10-24 MHz. +- */ +- st33htph: tpm-tis@0 { +- compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; +- reg = <0>; +- spi-max-frequency = <24000000>; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- phy-mode = "rmii"; +- phy-handle = <ðphy>; +- status = "okay"; +- +- /* +- * MDIO bus reset is used to generate PHY device reset before +- * Ethernet PHY type ID auto-detection. Otherwise this communication +- * fails as device does not answer when recommended reset circuit +- * is used. +- */ +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reset-delay-us = <100000>; +- reset-post-delay-us = <500000>; +- reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; +- +- /* Microchip/Micrel KSZ8081RNB */ +- ethphy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- interrupt-parent = <&gpio1>; +- interrupts = <9 IRQ_TYPE_LEVEL_LOW>; +- reg = <1>; +- }; +- }; +-}; +- +-/* +- * Detection signals for internal USB modules. +- * Used for robust USB plug and play handling such as USB downstream port +- * power-cycle and USB hub reset in case of misbehaving or crashed modules. +- * +- * SMPS - AC input monitor based on zero crossing. +- * Used for last gasp notification. +- */ +-&gpio3 { +- gpio-line-names = "", "", "", "", "", "", "", "", +- "", "", "", "", "smps-ac-monitor", "", "usb-hub-reset", "", +- "", "", "", "", "", "", "", "", +- "", "module-b-detection", "", "module-a-detection", "", "", "", ""; +-}; +- +-/* +- * Tamper IRQ trigger timestamp reading. +- * Used for sealed cover opened/closed notification. +- */ +-&gpio5 { +- gpio-line-names = "", "", "", "", "", "", "", "", +- "", "", "", "", "rtc-tamper-irq", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_misc>; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c /* X2-15 */ +- MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74 /* X2-18 */ +- MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74 /* X2-13 */ +- MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x74 /* X2-20 */ +- /* RTC - Tamper IRQ */ +- MX7D_PAD_SD2_CLK__GPIO5_IO12 0x3c /* X1-92 */ +- >; +- }; +- +- pinctrl_ecspi4: ecspi4grp { +- fsl,pins = < +- MX7D_PAD_LCD_CLK__ECSPI4_MISO 0x7c /* X2-72 */ +- MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI 0x74 /* X2-68 */ +- MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK 0x74 /* X2-76 */ +- MX7D_PAD_LCD_VSYNC__GPIO3_IO3 0x74 /* X2-78 */ +- >; +- }; +- +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x03 /* X2-48 */ +- MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x03 /* X2-46 */ +- MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 /* X2-53 */ +- MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 /* X2-55 */ +- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 /* X2-61 */ +- MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79 /* X2-56 */ +- MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79 /* X2-58 */ +- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79 /* X2-64 */ +- MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73 /* X2-52 */ +- /* PHY reset: SRE_FAST, DSE_X1 */ +- MX7D_PAD_ENET1_COL__GPIO7_IO15 0x00 /* X1-96 */ +- /* Clock from PHY to MAC: 100kPU */ +- MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x70 /* X3-4 */ +- /* PHY interrupt: 100kPU, HYS */ +- MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x78 /* X1-80 */ +- >; +- }; +- +- pinctrl_leds: ledsgrp { +- fsl,pins = < +- MX7D_PAD_LCD_DATA01__GPIO3_IO6 0x14 /* X2-82 */ +- MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* X1-82 */ +- MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* X1-84 */ +- MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* X1-86 */ +- MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* X1-88 */ +- MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x14 /* X1-90 */ +- >; +- }; +- +- pinctrl_misc: miscgrp { +- fsl,pins = < +- /* Module A detection (low = present) */ +- MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x7c /* X2-105 */ +- /* Module B detection (low = present) */ +- MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x7c /* X2-103 */ +- /* SMPS - AC input monitor (high = failure) */ +- MX7D_PAD_LCD_DATA07__GPIO3_IO12 0x7c /* X2-88 */ +- /* USB - Hub reset */ +- MX7D_PAD_LCD_DATA09__GPIO3_IO14 0x74 /* X2-92 */ +- >; +- }; +- +- pinctrl_restart: restartgrp { +- fsl,pins = < +- MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x74 /* X1-94 */ +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e /* X3-14 */ +- MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76 /* X3-16 */ +- >; +- }; +-}; +- +-&iomuxc_lpsr { +- pinctrl_usbotg2: usbotg2grp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c /* X3-11 */ +- MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 /* X3-9 */ +- >; +- }; +- +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +-}; +- +-&usbotg2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg2>; +- vbus-supply = <®_usb_otg2_vbus>; +- srp-disable; +- hnp-disable; +- adp-disable; +- over-current-active-low; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-/* +- * External watchdog feature provided by pcf2127. +- */ +-&wdog1 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-mba7.dts b/scripts/dtc/include-prefixes/arm/imx7d-mba7.dts +deleted file mode 100644 +index 36ef6a3cdb0b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-mba7.dts ++++ /dev/null +@@ -1,113 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Device Tree Source for TQ Systems TQMa7D board on MBa7 carrier board. +- * +- * Copyright (C) 2016 TQ Systems GmbH +- * Author: Markus Niebel +- * Copyright (C) 2019 Bruno Thomsen +- */ +- +-/dts-v1/; +- +-#include "imx7d-tqma7.dtsi" +-#include "imx7-mba7.dtsi" +- +-/ { +- model = "TQ Systems TQMa7D board on MBa7 carrier board"; +- compatible = "tq,imx7d-mba7", "tq,imx7d-tqma7", "fsl,imx7d"; +-}; +- +-&fec2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet2>; +- phy-mode = "rgmii-id"; +- phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <1>; +- phy-supply = <®_fec2_pwdn>; +- phy-handle = <ðphy2_0>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy2_0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- ti,rx-internal-delay = ; +- ti,tx-internal-delay = ; +- ti,fifo-depth = ; +- ti,clk-output-sel = ; +- }; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog_mba7_1>; +- +- pinctrl_enet2: enet2grp { +- fsl,pins = < +- MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02 +- MX7D_PAD_SD2_WP__ENET2_MDC 0x00 +- MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71 +- MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71 +- MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71 +- MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71 +- MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71 +- MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71 +- MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79 +- MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79 +- MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79 +- MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79 +- MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79 +- MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79 +- /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */ +- MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070 +- /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */ +- MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078 +- >; +- }; +- +- pinctrl_pcie: pciegrp { +- fsl,pins = < +- /* #pcie_wake */ +- MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70 +- /* #pcie_rst */ +- MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70 +- /* #pcie_dis */ +- MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70 +- >; +- }; +-}; +- +-&iomuxc_lpsr { +- pinctrl_usbotg2: usbotg2grp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c +- MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 +- >; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- /* 1.5V logically from 3.3V */ +- /* probe deferral not supported */ +- /* pcie-bus-supply = <®_mpcie_1v5>; */ +- reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&usbotg2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg2>; +- vbus-supply = <®_usb_otg2_vbus>; +- srp-disable; +- hnp-disable; +- adp-disable; +- dr_mode = "host"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-meerkat96.dts b/scripts/dtc/include-prefixes/arm/imx7d-meerkat96.dts +deleted file mode 100644 +index dd8003bd1fc0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-meerkat96.dts ++++ /dev/null +@@ -1,375 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright (C) 2019 Linaro Ltd. +- */ +- +-/dts-v1/; +- +-#include "imx7d.dtsi" +- +-/ { +- model = "96Boards Meerkat96 Board"; +- compatible = "novtech,imx7d-meerkat96", "fsl,imx7d"; +- +- chosen { +- stdout-path = &uart6; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512MB */ +- }; +- +- reg_wlreg_on: regulator-wlreg-on { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wlreg_on>; +- regulator-name = "wlreg_on"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100>; +- gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_otg1_vbus: regulator-usb-otg1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usb_otg2_vbus: regulator-usb-otg2-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg2_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led1 { +- label = "green:user1"; +- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- +- led2 { +- label = "green:user2"; +- gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- +- led3 { +- label = "green:user3"; +- gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "mmc1"; +- default-state = "off"; +- }; +- +- led4 { +- label = "green:user4"; +- gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "none"; +- default-state = "off"; +- panic-indicator; +- }; +- +- led5 { +- label = "yellow:wlan"; +- gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "phy0tx"; +- default-state = "off"; +- }; +- +- led6 { +- label = "blue:bt"; +- gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "bluetooth-power"; +- default-state = "off"; +- }; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +-}; +- +-&lcdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcdif>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart6>; +- assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; +- status = "okay"; +-}; +- +-&uart7 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart7 &pinctrl_bt_gpios>; +- assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; +- uart-has-rtscts; +- fsl,dte-mode; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- device-wakeup-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&usbotg1 { +- vbus-supply = <®_usb_otg1_vbus>; +- status = "okay"; +-}; +- +-&usbotg2 { +- vbus-supply = <®_usb_otg2_vbus>; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- keep-power-in-suspend; +- fsl,tuning-step = <2>; +- vmmc-supply = <®_3p3v>; +- no-1-8-v; +- broken-cd; +- status = "okay"; +-}; +- +-&usdhc3 { +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <4>; +- no-1-8-v; +- no-mmc; +- non-removable; +- keep-power-in-suspend; +- wakeup-source; +- vmmc-supply = <®_wlreg_on>; +- vqmmc-supply =<®_3p3v>; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wlan_irq>; +- interrupt-parent = <&gpio6>; +- interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "host-wake"; +- }; +-}; +- +-&iomuxc { +- pinctrl_bt_gpios: btgpiosgrp { +- fsl,pins = < +- MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x59 +- MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x1f +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 +- MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x59 +- MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 +- MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x59 +- MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 +- MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f +- MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f +- MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x4000007f +- MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x4000007f +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f +- MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f +- >; +- }; +- +- pinctrl_lcdif: lcdifgrp { +- fsl,pins = < +- MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 +- MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 +- MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 +- MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 +- MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 +- MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 +- MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 +- MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 +- MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 +- MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 +- MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 +- MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 +- MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 +- MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 +- MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 +- MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 +- MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 +- MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 +- MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 +- MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 +- MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 +- MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 +- MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 +- MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 +- MX7D_PAD_LCD_CLK__LCD_CLK 0x79 +- MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 +- MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 +- MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 +- MX7D_PAD_LCD_RESET__LCD_RESET 0x79 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 +- MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX7D_PAD_SD3_DATA4__UART3_DCE_RX 0x79 +- MX7D_PAD_SD3_DATA5__UART3_DCE_TX 0x79 +- MX7D_PAD_SD3_DATA6__UART3_DCE_RTS 0x79 +- MX7D_PAD_SD3_DATA7__UART3_DCE_CTS 0x79 +- >; +- }; +- +- pinctrl_uart6: uart6grp { +- fsl,pins = < +- MX7D_PAD_SD1_CD_B__UART6_DCE_RX 0x79 +- MX7D_PAD_SD1_WP__UART6_DCE_TX 0x79 +- >; +- }; +- +- pinctrl_uart7: uart7grp { +- fsl,pins = < +- MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX 0x79 +- MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX 0x79 +- MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS 0x79 +- MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS 0x79 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX7D_PAD_SD1_CMD__SD1_CMD 0x59 +- MX7D_PAD_SD1_CLK__SD1_CLK 0x19 +- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 +- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 +- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 +- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x59 +- MX7D_PAD_SD3_CLK__SD3_CLK 0x0D +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 +- >; +- }; +- +- pinctrl_wlan_irq: wlanirqgrp { +- fsl,pins = < +- MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x19 +- >; +- }; +- +- pinctrl_wlreg_on: wlregongrp { +- fsl,pins = < +- MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x19 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-nitrogen7.dts b/scripts/dtc/include-prefixes/arm/imx7d-nitrogen7.dts +deleted file mode 100644 +index e0751e6ba3c0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-nitrogen7.dts ++++ /dev/null +@@ -1,699 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright 2016 Boundary Devices, Inc. +- */ +- +-/dts-v1/; +- +-#include "imx7d.dtsi" +- +-/ { +- model = "Boundary Devices i.MX7 Nitrogen7 Board"; +- compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; +- }; +- +- backlight-j9 { +- compatible = "gpio-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_backlight_j9>; +- gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- default-on; +- }; +- +- backlight_lcd: backlight-j20 { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 5000000 0>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- status = "okay"; +- }; +- +- panel-lcd { +- compatible = "okaya,rs800480t-7x0gp"; +- backlight = <&backlight_lcd>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lcdif_out>; +- }; +- }; +- }; +- +- reg_usb_otg1_vbus: regulator-usb-otg1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_otg2_vbus: regulator-usb-otg2-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg2_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_can2_3v3: regulator-can2-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "can2-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; +- }; +- +- reg_vref_1v8: regulator-vref-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "vref-1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- reg_vref_3v3: regulator-vref-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vref-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_wlan: regulator-wlan { +- compatible = "regulator-fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "reg_wlan"; +- startup-delay-us = <70000>; +- gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- usdhc2_pwrseq: usdhc2_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&adc1 { +- vref-supply = <®_vref_1v8>; +- status = "okay"; +-}; +- +-&adc2 { +- vref-supply = <®_vref_1v8>; +- status = "okay"; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>, +- <&clks IMX7D_CLKO2_ROOT_DIV>; +- assigned-clock-parents = <&clks IMX7D_CKIL>; +- assigned-clock-rates = <0>, <32768>; +-}; +- +-&cpu0 { +- cpu-supply = <&sw1a_reg>; +-}; +- +-&cpu1 { +- cpu-supply = <&sw1a_reg>; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, +- <&clks IMX7D_ENET1_TIME_ROOT_CLK>; +- assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; +- assigned-clock-rates = <0>, <100000000>; +- phy-mode = "rgmii"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@4 { +- reg = <4>; +- }; +- }; +-}; +- +-&flexcan2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- xceiver-supply = <®_can2_3v3>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic: pfuze3000@8 { +- compatible = "fsl,pfuze3000"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1a { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1475000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- /* use sw1c_reg to align with pfuze100/pfuze200 */ +- sw1c_reg: sw1b { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1475000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1650000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen2_reg: vldo2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- regulator-always-on; +- }; +- +- vgen3_reg: vccsd { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen4_reg: v33 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vldo3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vldo4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- rtc@68 { +- compatible = "microcrystal,rv4162"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2_rv4162>; +- reg = <0x68>; +- interrupts-extended = <&gpio2 15 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- touch@48 { +- compatible = "ti,tsc2004"; +- reg = <0x48>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3_tsc2004>; +- interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>; +- wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +- +- codec: wm8960@1a { +- compatible = "wlf,wm8960"; +- reg = <0x1a>; +- clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; +- clock-names = "mclk"; +- wlf,shared-lrclk; +- }; +-}; +- +-&lcdif { +- status = "okay"; +- +- port { +- lcdif_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +- status = "okay"; +-}; +- +-&uart6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart6>; +- assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbotg1 { +- vbus-supply = <®_usb_otg1_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg1>; +- status = "okay"; +-}; +- +-&usbotg2 { +- vbus-supply = <®_usb_otg2_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg2>; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; +- vmmc-supply = <&vgen3_reg>; +- bus-width = <4>; +- fsl,tuning-step = <2>; +- wakeup-source; +- keep-power-in-suspend; +- status = "okay"; +-}; +- +-&usdhc2 { +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- non-removable; +- vmmc-supply = <®_wlan>; +- mmc-pwrseq = <&usdhc2_pwrseq>; +- cap-power-off-card; +- keep-power-in-suspend; +- status = "okay"; +- +- wlcore: wlcore@2 { +- compatible = "ti,wl1271"; +- reg = <2>; +- interrupt-parent = <&gpio4>; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; +- ref-clock-frequency = <38400000>; +- }; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; +- assigned-clock-rates = <400000000>; +- bus-width = <8>; +- fsl,tuning-step = <2>; +- non-removable; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog1>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>; +- +- pinctrl_hog_1: hoggrp-1 { +- fsl,pins = < +- MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d +- MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x7d +- MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x7d +- >; +- }; +- +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 +- MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 +- MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x3 +- MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71 +- MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 +- MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 +- MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71 +- MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71 +- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 +- MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x71 +- MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11 +- MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11 +- MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11 +- MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x71 +- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11 +- MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x75 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x7d +- MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x7d +- MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x7d +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f +- MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f +- MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f +- >; +- }; +- +- pinctrl_i2c2_rv4162: i2c2-rv4162grp { +- fsl,pins = < +- MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x7d +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f +- MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f +- >; +- }; +- +- pinctrl_i2c3_tsc2004: i2c3tsc2004grp { +- fsl,pins = < +- MX7D_PAD_LCD_RESET__GPIO3_IO4 0x79 +- MX7D_PAD_SD2_WP__GPIO5_IO10 0x7d +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f +- MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f +- >; +- }; +- +- pinctrl_j2: j2grp { +- fsl,pins = < +- MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x7d +- MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x7d +- MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x7d +- MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x7d +- MX7D_PAD_SD1_WP__GPIO5_IO1 0x7d +- MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x7d +- MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x7d +- MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x7d +- MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x7d +- MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x7d +- MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x7d +- MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x7d +- MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x7d +- MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x7d +- MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x7d +- MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x7d +- MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x7d +- MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x7d +- MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x7d +- MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x7d +- MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x7d +- MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x7d +- MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x7d +- MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x7d +- MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x7d +- MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x7d +- MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x7d +- MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x7d +- MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x7d +- MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x7d +- MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x7d +- MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x7d +- MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x7d +- MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x7d +- MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x7d +- >; +- }; +- +- pinctrl_lcdif_dat: lcdifdatgrp { +- fsl,pins = < +- MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 +- MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 +- MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 +- MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 +- MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 +- MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 +- MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 +- MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 +- MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 +- MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 +- MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 +- MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 +- MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 +- MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 +- MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 +- MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 +- MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 +- MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 +- MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 +- MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 +- MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 +- MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 +- MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 +- MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 +- >; +- }; +- +- pinctrl_lcdif_ctrl: lcdifctrlgrp { +- fsl,pins = < +- MX7D_PAD_LCD_CLK__LCD_CLK 0x79 +- MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 +- MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 +- MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7d +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 +- MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 +- MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 +- MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 +- MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x7d +- >; +- }; +- +- pinctrl_uart6: uart6grp { +- fsl,pins = < +- MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 +- MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 +- MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 +- MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 +- >; +- }; +- +- pinctrl_usbotg2: usbotg2grp { +- fsl,pins = < +- MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x7d +- MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX7D_PAD_SD1_CMD__SD1_CMD 0x59 +- MX7D_PAD_SD1_CLK__SD1_CLK 0x19 +- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 +- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 +- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 +- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 +- MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x75 +- MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x75 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX7D_PAD_SD2_CMD__SD2_CMD 0x59 +- MX7D_PAD_SD2_CLK__SD2_CLK 0x19 +- MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 +- MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 +- MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 +- MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 +- MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x59 +- MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x59 +- MX7D_PAD_SD3_CLK__SD3_CLK 0x19 +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 +- >; +- }; +-}; +- +-&iomuxc_lpsr { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog_2>; +- +- pinctrl_hog_2: hoggrp-2 { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x7d +- MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d +- >; +- }; +- +- pinctrl_backlight_j9: backlightj9grp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x7d +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x7d +- >; +- }; +- +- pinctrl_usbotg1: usbotg1grp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x7d +- MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 +- >; +- }; +- +- pinctrl_wdog1: wdog1grp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x75 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-pico-dwarf.dts b/scripts/dtc/include-prefixes/arm/imx7d-pico-dwarf.dts +deleted file mode 100644 +index 5162fe227d1e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-pico-dwarf.dts ++++ /dev/null +@@ -1,87 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright 2015 Technexion Ltd. +-// +-// Author: Wig Cheng +-// Richard Hu +-// Tapani Utriainen +-/dts-v1/; +- +-#include "imx7d-pico.dtsi" +-/ { +- model = "TechNexion PICO-IMX7D and DWARF baseboard"; +- compatible = "technexion,imx7d-pico-dwarf", "fsl,imx7d"; +- +- sound { +- compatible = "fsl,imx-audio-sgtl5000"; +- model = "imx7d-sgtl5000"; +- audio-cpu = <&sai1>; +- audio-codec = <&sgtl5000>; +- audio-routing = +- "LINE_IN", "Line In Jack", +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- }; +- +- sys_mclk: clock-sys-mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +-}; +- +-&i2c1 { +- clock_frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- sgtl5000: audio-codec@a { +- reg = <0x0a>; +- compatible = "fsl,sgtl5000"; +- clocks = <&sys_mclk>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_3p3v>; +- }; +- +- pressure-sensor@60 { +- compatible = "fsl,mpl3115"; +- reg = <0x60>; +- }; +-}; +- +-&i2c4 { +- clock_frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pca9554: io-expander@25 { +- compatible = "nxp,pca9554"; +- gpio-controller; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- reg = <0x25>; +- }; +- +- touchscreen@38 { +- compatible = "edt,edt-ft5x06"; +- reg = <0x38>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_touchscreen>; +- interrupt-parent = <&gpio2>; +- interrupts = <13 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&pca9554 4 GPIO_ACTIVE_LOW>; +- touchscreen-size-x = <800>; +- touchscreen-size-y = <480>; +- }; +-}; +- +-&iomuxc { +- pinctrl_touchscreen: touchscreengrp { +- fsl,pins = < +- MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-pico-hobbit.dts b/scripts/dtc/include-prefixes/arm/imx7d-pico-hobbit.dts +deleted file mode 100644 +index 7b2198a9372c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-pico-hobbit.dts ++++ /dev/null +@@ -1,105 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// +-// Copyright 2017 NXP +- +-#include "imx7d-pico.dtsi" +- +-/ { +- model = "TechNexion PICO-IMX7D Board using Hobbit baseboard"; +- compatible = "technexion,imx7d-pico-hobbit", "fsl,imx7d"; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led { +- label = "gpio-led"; +- gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "imx7-sgtl5000"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&dailink_master>; +- simple-audio-card,frame-master = <&dailink_master>; +- simple-audio-card,cpu { +- sound-dai = <&sai1>; +- }; +- +- dailink_master: simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; +- }; +- }; +-}; +- +-&i2c1 { +- sgtl5000: codec@a { +- #sound-dai-cells = <0>; +- reg = <0x0a>; +- compatible = "fsl,sgtl5000"; +- clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_vref_1v8>; +- }; +-}; +- +-&i2c4 { +- status = "okay"; +- +- adc081c: adc@50 { +- compatible = "ti,adc081c"; +- reg = <0x50>; +- vref-supply = <®_3p3v>; +- }; +-}; +- +-&ecspi3 { +- ads7846@0 { +- reg = <0>; +- compatible = "ti,ads7846"; +- interrupt-parent = <&gpio2>; +- interrupts = <7 0>; +- spi-max-frequency = <1000000>; +- pendown-gpio = <&gpio2 7 0>; +- vcc-supply = <®_3p3v>; +- ti,x-min = /bits/ 16 <0>; +- ti,x-max = /bits/ 16 <4095>; +- ti,y-min = /bits/ 16 <0>; +- ti,y-max = /bits/ 16 <4095>; +- ti,pressure-max = /bits/ 16 <1024>; +- ti,x-plate-ohms = /bits/ 16 <90>; +- ti,y-plate-ohms = /bits/ 16 <90>; +- ti,debounce-max = /bits/ 16 <70>; +- ti,debounce-tol = /bits/ 16 <3>; +- ti,debounce-rep = /bits/ 16 <2>; +- ti,settle-delay-usec = /bits/ 16 <150>; +- wakeup-source; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 +- MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 +- MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 +- MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 +- MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 +- MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 +- MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-pico-nymph.dts b/scripts/dtc/include-prefixes/arm/imx7d-pico-nymph.dts +deleted file mode 100644 +index 104a85254adb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-pico-nymph.dts ++++ /dev/null +@@ -1,84 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright 2015 Technexion Ltd. +-// +-// Author: Wig Cheng +-// Richard Hu +-// Tapani Utriainen +-/dts-v1/; +- +-#include "imx7d-pico.dtsi" +-/ { +- model = "TechNexion PICO-IMX7 and NYMPH baseboard"; +- compatible = "technexion,imx7d-pico-nymph", "fsl,imx7d"; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led { +- label = "gpio-led"; +- gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- sound { +- compatible = "fsl,imx-audio-sgtl5000"; +- model = "imx7d-sgtl5000"; +- audio-cpu = <&sai1>; +- audio-codec = <&sgtl5000>; +- audio-routing = +- "LINE_IN", "Line In Jack", +- "MIC_IN", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "Headphone Jack", "HP_OUT"; +- }; +- +- sys_mclk: clock-sys-mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +-}; +- +-&i2c1 { +- clock_frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- sgtl5000: audio-codec@a { +- reg = <0x0a>; +- compatible = "fsl,sgtl5000"; +- clocks = <&sys_mclk>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_3p3v>; +- }; +- +- adc@52 { +- compatible = "ti,adc081c"; +- reg = <0x52>; +- vref-supply = <®_2p5v>; +- }; +-}; +- +-&i2c2 { +- clock_frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- rtc@68 { +- compatible = "dallas,ds1337"; +- reg = <0x68>; +- }; +-}; +- +-&iomuxc { +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-pico-pi.dts b/scripts/dtc/include-prefixes/arm/imx7d-pico-pi.dts +deleted file mode 100644 +index 70bea95c06d8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-pico-pi.dts ++++ /dev/null +@@ -1,93 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// +-// Copyright 2017 NXP +- +-#include "imx7d-pico.dtsi" +- +-/ { +- model = "TechNexion PICO-IMX7D Board and PI baseboard"; +- compatible = "technexion,imx7d-pico-pi", "fsl,imx7d"; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led { +- label = "gpio-led"; +- gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "imx7-sgtl5000"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&dailink_master>; +- simple-audio-card,frame-master = <&dailink_master>; +- simple-audio-card,cpu { +- sound-dai = <&sai1>; +- }; +- +- dailink_master: simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; +- }; +- }; +-}; +- +-&i2c1 { +- sgtl5000: codec@a { +- #sound-dai-cells = <0>; +- reg = <0x0a>; +- compatible = "fsl,sgtl5000"; +- clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; +- VDDA-supply = <®_2p5v>; +- VDDIO-supply = <®_vref_1v8>; +- }; +-}; +- +-&i2c4 { +- polytouch: touchscreen@38 { +- compatible = "edt,edt-ft5x06"; +- reg = <0x38>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_touchscreen>; +- interrupt-parent = <&gpio2>; +- interrupts = <13 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; +- touchscreen-size-x = <800>; +- touchscreen-size-y = <480>; +- }; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 +- MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 +- MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 +- MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 +- MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 +- MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 +- MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 +- >; +- }; +- +- pinctrl_touchscreen: touchscreengrp { +- fsl,pins = < +- MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 +- MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 +- >; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-pico.dtsi b/scripts/dtc/include-prefixes/arm/imx7d-pico.dtsi +deleted file mode 100644 +index e519897fae08..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-pico.dtsi ++++ /dev/null +@@ -1,675 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// +-// Copyright 2017 NXP +- +-/dts-v1/; +- +-#include "imx7d.dtsi" +- +-/ { +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm4 0 50000 0>; +- brightness-levels = <0 36 72 108 144 180 216 255>; +- default-brightness-level = <6>; +- }; +- +- /* Will be filled by the bootloader */ +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0>; +- }; +- +- panel { +- compatible = "vxt,vl050-8048nt-c01"; +- backlight = <&backlight>; +- power-supply = <®_lcd_3v3>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +- +- reg_lcd_3v3: regulator-lcd-3v3 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_lcdreg_on>; +- regulator-name = "lcd-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_wlreg_on: regulator-wlreg_on { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_wlreg_on>; +- regulator-name = "wlreg_on"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_2p5v: regulator-2p5v { +- compatible = "regulator-fixed"; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_otg1_vbus: regulator-usb-otg1-vbus { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg1_pwr>; +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio4 5 GPIO_ACTIVE_LOW>; +- }; +- +- reg_usb_otg2_vbus: regulator-usb-otg2-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg2_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_vref_1v8: regulator-vref-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "vref-1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- usdhc2_pwrseq: usdhc2_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>, +- <&clks IMX7D_CLKO2_ROOT_DIV>; +- assigned-clock-parents = <&clks IMX7D_CKIL>; +- assigned-clock-rates = <0>, <32768>; +-}; +- +-&ecspi3 { +- cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi3>; +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, +- <&clks IMX7D_ENET1_TIME_ROOT_CLK>; +- assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; +- assigned-clock-rates = <0>, <100000000>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- status = "okay"; +- }; +- }; +-}; +- +-&flexcan1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- status = "okay"; +-}; +- +-&flexcan2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can2>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +- +- pmic: pfuze3000@8 { +- compatible = "fsl,pfuze3000"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1a { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- /* use sw1c_reg to align with pfuze100/pfuze200 */ +- sw1c_reg: sw1b { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1475000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1650000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen2_reg: vldo2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vccsd { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen4_reg: v33 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vldo3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vldo4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&lcdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcdif>; +- status = "okay"; +- +- port { +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +-}; +- +-&sai1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai1>; +- assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, +- <&clks IMX7D_SAI1_ROOT_CLK>; +- assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; +- assigned-clock-rates = <0>, <24576000>; +- status = "okay"; +-}; +- +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- status = "okay"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "okay"; +-}; +- +-&pwm4 { /* Backlight */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart5>; +- assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; +- status = "okay"; +-}; +- +-&uart6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart6>; +- assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart7 { /* Bluetooth */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart7>; +- assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbotg1 { +- vbus-supply = <®_usb_otg1_vbus>; +- status = "okay"; +-}; +- +-&usbotg2 { +- vbus-supply = <®_usb_otg2_vbus>; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- fsl,tuning-step = <2>; +- vmmc-supply = <®_3p3v>; +- wakeup-source; +- no-1-8-v; +- keep-power-in-suspend; +- status = "okay"; +-}; +- +-&usdhc2 { /* Wifi SDIO */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>; +- no-1-8-v; +- non-removable; +- keep-power-in-suspend; +- wakeup-source; +- vmmc-supply = <®_wlreg_on>; +- mmc-pwrseq = <&usdhc2_pwrseq>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; +- assigned-clock-rates = <400000000>; +- bus-width = <8>; +- no-1-8-v; +- fsl,tuning-step = <2>; +- non-removable; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_ecspi3: ecspi3grp { +- fsl,pins = < +- MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 +- MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 +- MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 +- MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f +- MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x4000007f +- MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x4000007f +- >; +- }; +- +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 +- MX7D_PAD_SD2_WP__ENET1_MDC 0x3 +- MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 +- MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 +- MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 +- MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 +- MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 +- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 +- MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 +- MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 +- MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 +- MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 +- MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 +- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 +- MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */ +- >; +- }; +- +- pinctrl_can1: can1frp { +- fsl,pins = < +- MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59 +- MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59 +- >; +- }; +- +- pinctrl_can2: can2frp { +- fsl,pins = < +- MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59 +- MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f +- MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f +- >; +- }; +- +- pinctrl_lcdif: lcdifgrp { +- fsl,pins = < +- MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 +- MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 +- MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 +- MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 +- MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 +- MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 +- MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 +- MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 +- MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 +- MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 +- MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 +- MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 +- MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 +- MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 +- MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 +- MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 +- MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 +- MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 +- MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 +- MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 +- MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 +- MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 +- MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 +- MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 +- MX7D_PAD_LCD_CLK__LCD_CLK 0x79 +- MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x78 +- MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x78 +- MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x78 +- MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 +- >; +- }; +- +- pinctrl_pwm1: pwm1 { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f +- >; +- }; +- +- pinctrl_pwm2: pwm2 { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f +- >; +- }; +- +- pinctrl_pwm3: pwm3 { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f +- >; +- }; +- +- pinctrl_pwm4: pwm4grp{ +- fsl,pins = < +- MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x7f +- >; +- }; +- +- pinctrl_reg_wlreg_on: regregongrp { +- fsl,pins = < +- MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59 +- >; +- }; +- +- pinctrl_sai1: sai1grp { +- fsl,pins = < +- MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f +- MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f +- MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 +- MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79 +- MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79 +- >; +- }; +- +- pinctrl_uart6: uart6grp { +- fsl,pins = < +- MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79 +- MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79 +- MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x79 +- MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x79 +- >; +- }; +- +- pinctrl_uart7: uart7grp { +- fsl,pins = < +- MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x79 +- MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x79 +- MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x79 +- MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x79 +- >; +- }; +- +- pinctrl_usbotg1_pwr: usbotg_pwr { +- fsl,pins = < +- MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX7D_PAD_SD1_CMD__SD1_CMD 0x59 +- MX7D_PAD_SD1_CLK__SD1_CLK 0x19 +- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 +- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 +- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 +- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 +- MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { +- fsl,pins = < +- MX7D_PAD_SD1_CMD__SD1_CMD 0x5a +- MX7D_PAD_SD1_CLK__SD1_CLK 0x1a +- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a +- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a +- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a +- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a +- MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { +- fsl,pins = < +- MX7D_PAD_SD1_CMD__SD1_CMD 0x5b +- MX7D_PAD_SD1_CLK__SD1_CLK 0x1b +- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b +- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b +- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b +- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b +- MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX7D_PAD_SD2_CMD__SD2_CMD 0x59 +- MX7D_PAD_SD2_CLK__SD2_CLK 0x19 +- MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 +- MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 +- MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 +- MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x59 +- MX7D_PAD_SD3_CLK__SD3_CLK 0x19 +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x5a +- MX7D_PAD_SD3_CLK__SD3_CLK 0x1a +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x5b +- MX7D_PAD_SD3_CLK__SD3_CLK 0x1b +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b +- >; +- }; +-}; +- +-&iomuxc_lpsr { +- pinctrl_wifi_clk: wificlkgrp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d +- >; +- }; +- +- pinctrl_reg_lcdreg_on: reglcdongrp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x59 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-pinfunc.h b/scripts/dtc/include-prefixes/arm/imx7d-pinfunc.h +deleted file mode 100644 +index 69f2c1ec8254..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-pinfunc.h ++++ /dev/null +@@ -1,1154 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __DTS_IMX7D_PINFUNC_H +-#define __DTS_IMX7D_PINFUNC_H +- +-/* +- * The pin function ID is a tuple of +- * +- */ +- +-#define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3 +-#define MX7D_PAD_LPSR_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3 +-#define MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3 +-#define MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3 +-#define MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 +-#define MX7D_PAD_LPSR_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 +-#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4 +-#define MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2 +-#define MX7D_PAD_LPSR_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 +-#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DCE_RTS 0x0014 0x0044 0x0710 0x3 0x5 +-#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DTE_CTS 0x0014 0x0044 0x0000 0x3 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2 +-#define MX7D_PAD_LPSR_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 +-#define MX7D_PAD_LPSR_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 +-#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4 +-#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DTE_TX 0x0018 0x0048 0x0000 0x3 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2 +-#define MX7D_PAD_LPSR_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1 +-#define MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1 +-#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DCE_TX 0x001C 0x004C 0x0000 0x3 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DTE_RX 0x001C 0x004C 0x0714 0x3 0x5 +-#define MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2 +-#define MX7D_PAD_LPSR_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0 +-#define MX7D_PAD_LPSR_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1 +-#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0 +-#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0 +-#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0 +-#define MX7D_PAD_GPIO1_IO08__UART3_DCE_RX 0x0014 0x026C 0x0704 0x3 0x0 +-#define MX7D_PAD_GPIO1_IO08__UART3_DTE_TX 0x0014 0x026C 0x0000 0x3 0x0 +-#define MX7D_PAD_GPIO1_IO08__I2C3_SCL 0x0014 0x026C 0x05E4 0x4 0x0 +-#define MX7D_PAD_GPIO1_IO08__KPP_COL5 0x0014 0x026C 0x0608 0x6 0x0 +-#define MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x0014 0x026C 0x0000 0x7 0x0 +-#define MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x0018 0x0270 0x0000 0x0 0x0 +-#define MX7D_PAD_GPIO1_IO09__SD1_LCTL 0x0018 0x0270 0x0000 0x1 0x0 +-#define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 0x0018 0x0270 0x0000 0x2 0x0 +-#define MX7D_PAD_GPIO1_IO09__UART3_DCE_TX 0x0018 0x0270 0x0000 0x3 0x0 +-#define MX7D_PAD_GPIO1_IO09__UART3_DTE_RX 0x0018 0x0270 0x0704 0x3 0x1 +-#define MX7D_PAD_GPIO1_IO09__I2C3_SDA 0x0018 0x0270 0x05E8 0x4 0x0 +-#define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY 0x0018 0x0270 0x04F4 0x5 0x0 +-#define MX7D_PAD_GPIO1_IO09__KPP_ROW5 0x0018 0x0270 0x0628 0x6 0x0 +-#define MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x0018 0x0270 0x0000 0x7 0x0 +-#define MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x001C 0x0274 0x0000 0x0 0x0 +-#define MX7D_PAD_GPIO1_IO10__SD2_LCTL 0x001C 0x0274 0x0000 0x1 0x0 +-#define MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x001C 0x0274 0x0568 0x2 0x0 +-#define MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS 0x001C 0x0274 0x0700 0x3 0x0 +-#define MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS 0x001C 0x0274 0x0000 0x3 0x0 +-#define MX7D_PAD_GPIO1_IO10__I2C4_SCL 0x001C 0x0274 0x05EC 0x4 0x0 +-#define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA 0x001C 0x0274 0x05A4 0x5 0x0 +-#define MX7D_PAD_GPIO1_IO10__KPP_COL6 0x001C 0x0274 0x060C 0x6 0x0 +-#define MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x001C 0x0274 0x0000 0x7 0x0 +-#define MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x0020 0x0278 0x0000 0x0 0x0 +-#define MX7D_PAD_GPIO1_IO11__SD3_LCTL 0x0020 0x0278 0x0000 0x1 0x0 +-#define MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x0020 0x0278 0x0000 0x2 0x0 +-#define MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS 0x0020 0x0278 0x0000 0x3 0x0 +-#define MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS 0x0020 0x0278 0x0700 0x3 0x1 +-#define MX7D_PAD_GPIO1_IO11__I2C4_SDA 0x0020 0x0278 0x05F0 0x4 0x0 +-#define MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB 0x0020 0x0278 0x05A8 0x5 0x0 +-#define MX7D_PAD_GPIO1_IO11__KPP_ROW6 0x0020 0x0278 0x062C 0x6 0x0 +-#define MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x0020 0x0278 0x0000 0x7 0x0 +-#define MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0024 0x027C 0x0000 0x0 0x0 +-#define MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x0024 0x027C 0x0000 0x1 0x0 +-#define MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x0024 0x027C 0x0564 0x2 0x0 +-#define MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0024 0x027C 0x04DC 0x3 0x0 +-#define MX7D_PAD_GPIO1_IO12__CM4_NMI 0x0024 0x027C 0x0000 0x4 0x0 +-#define MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 0x0024 0x027C 0x04E4 0x5 0x0 +-#define MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 0x0024 0x027C 0x0000 0x6 0x0 +-#define MX7D_PAD_GPIO1_IO12__USB_OTG1_ID 0x0024 0x027C 0x0734 0x7 0x0 +-#define MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x0028 0x0280 0x0000 0x0 0x0 +-#define MX7D_PAD_GPIO1_IO13__SD3_VSELECT 0x0028 0x0280 0x0000 0x1 0x0 +-#define MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 0x0028 0x0280 0x0570 0x2 0x0 +-#define MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0028 0x0280 0x0000 0x3 0x0 +-#define MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY 0x0028 0x0280 0x04F4 0x4 0x1 +-#define MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 0x0028 0x0280 0x04E8 0x5 0x0 +-#define MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL 0x0028 0x0280 0x0000 0x6 0x0 +-#define MX7D_PAD_GPIO1_IO13__USB_OTG2_ID 0x0028 0x0280 0x0730 0x7 0x0 +-#define MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x002C 0x0284 0x0000 0x0 0x0 +-#define MX7D_PAD_GPIO1_IO14__SD3_CD_B 0x002C 0x0284 0x0738 0x1 0x0 +-#define MX7D_PAD_GPIO1_IO14__ENET2_MDIO 0x002C 0x0284 0x0574 0x2 0x0 +-#define MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x002C 0x0284 0x04E0 0x3 0x0 +-#define MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B 0x002C 0x0284 0x0000 0x4 0x0 +-#define MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 0x002C 0x0284 0x04EC 0x5 0x0 +-#define MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 0x002C 0x0284 0x06D8 0x6 0x0 +-#define MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x0030 0x0288 0x0000 0x0 0x0 +-#define MX7D_PAD_GPIO1_IO15__SD3_WP 0x0030 0x0288 0x073C 0x1 0x0 +-#define MX7D_PAD_GPIO1_IO15__ENET2_MDC 0x0030 0x0288 0x0000 0x2 0x0 +-#define MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0030 0x0288 0x0000 0x3 0x0 +-#define MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B 0x0030 0x0288 0x0000 0x4 0x0 +-#define MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 0x0030 0x0288 0x04F0 0x5 0x0 +-#define MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 0x0030 0x0288 0x06DC 0x6 0x0 +-#define MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x0034 0x02A4 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD 0x0034 0x02A4 0x0000 0x1 0x0 +-#define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x0034 0x02A4 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_DATA00__KPP_ROW3 0x0034 0x02A4 0x0620 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA00__EIM_AD0 0x0034 0x02A4 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x0034 0x02A4 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_DATA00__LCD_DATA0 0x0034 0x02A4 0x0638 0x6 0x0 +-#define MX7D_PAD_EPDC_DATA00__LCD_CLK 0x0034 0x02A4 0x0000 0x7 0x0 +-#define MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x0038 0x02A8 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK 0x0038 0x02A8 0x0000 0x1 0x0 +-#define MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x0038 0x02A8 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_DATA01__KPP_COL3 0x0038 0x02A8 0x0600 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA01__EIM_AD1 0x0038 0x02A8 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x0038 0x02A8 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_DATA01__LCD_DATA1 0x0038 0x02A8 0x063C 0x6 0x0 +-#define MX7D_PAD_EPDC_DATA01__LCD_ENABLE 0x0038 0x02A8 0x0000 0x7 0x0 +-#define MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x003C 0x02AC 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B 0x003C 0x02AC 0x0000 0x1 0x0 +-#define MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x003C 0x02AC 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_DATA02__KPP_ROW2 0x003C 0x02AC 0x061C 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA02__EIM_AD2 0x003C 0x02AC 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x003C 0x02AC 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_DATA02__LCD_DATA2 0x003C 0x02AC 0x0640 0x6 0x0 +-#define MX7D_PAD_EPDC_DATA02__LCD_VSYNC 0x003C 0x02AC 0x0698 0x7 0x0 +-#define MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x0040 0x02B0 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN 0x0040 0x02B0 0x0000 0x1 0x0 +-#define MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x0040 0x02B0 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_DATA03__KPP_COL2 0x0040 0x02B0 0x05FC 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA03__EIM_AD3 0x0040 0x02B0 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x0040 0x02B0 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_DATA03__LCD_DATA3 0x0040 0x02B0 0x0644 0x6 0x0 +-#define MX7D_PAD_EPDC_DATA03__LCD_HSYNC 0x0040 0x02B0 0x0000 0x7 0x0 +-#define MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x0044 0x02B4 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD 0x0044 0x02B4 0x0000 0x1 0x0 +-#define MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x0044 0x02B4 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_DATA04__KPP_ROW1 0x0044 0x02B4 0x0618 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA04__EIM_AD4 0x0044 0x02B4 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x0044 0x02B4 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_DATA04__LCD_DATA4 0x0044 0x02B4 0x0648 0x6 0x0 +-#define MX7D_PAD_EPDC_DATA04__JTAG_FAIL 0x0044 0x02B4 0x0000 0x7 0x0 +-#define MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x0048 0x02B8 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD 0x0048 0x02B8 0x0000 0x1 0x0 +-#define MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x0048 0x02B8 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_DATA05__KPP_COL1 0x0048 0x02B8 0x05F8 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA05__EIM_AD5 0x0048 0x02B8 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x0048 0x02B8 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_DATA05__LCD_DATA5 0x0048 0x02B8 0x064C 0x6 0x0 +-#define MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE 0x0048 0x02B8 0x0000 0x7 0x0 +-#define MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x004C 0x02BC 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK 0x004C 0x02BC 0x0000 0x1 0x0 +-#define MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x004C 0x02BC 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_DATA06__KPP_ROW0 0x004C 0x02BC 0x0614 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA06__EIM_AD6 0x004C 0x02BC 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x004C 0x02BC 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_DATA06__LCD_DATA6 0x004C 0x02BC 0x0650 0x6 0x0 +-#define MX7D_PAD_EPDC_DATA06__JTAG_DE_B 0x004C 0x02BC 0x0000 0x7 0x0 +-#define MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x0050 0x02C0 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B 0x0050 0x02C0 0x0000 0x1 0x0 +-#define MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x0050 0x02C0 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_DATA07__KPP_COL0 0x0050 0x02C0 0x05F4 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA07__EIM_AD7 0x0050 0x02C0 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x0050 0x02C0 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_DATA07__LCD_DATA7 0x0050 0x02C0 0x0654 0x6 0x0 +-#define MX7D_PAD_EPDC_DATA07__JTAG_DONE 0x0050 0x02C0 0x0000 0x7 0x0 +-#define MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x0054 0x02C4 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD 0x0054 0x02C4 0x06E4 0x1 0x0 +-#define MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x0054 0x02C4 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x0054 0x02C4 0x071C 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA08__UART6_DTE_TX 0x0054 0x02C4 0x0000 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA08__EIM_OE 0x0054 0x02C4 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x0054 0x02C4 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_DATA08__LCD_DATA8 0x0054 0x02C4 0x0658 0x6 0x0 +-#define MX7D_PAD_EPDC_DATA08__LCD_BUSY 0x0054 0x02C4 0x0634 0x7 0x0 +-#define MX7D_PAD_EPDC_DATA08__EPDC_SDCLK 0x0054 0x02C4 0x0000 0x8 0x0 +-#define MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x0058 0x02C8 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK 0x0058 0x02C8 0x0000 0x1 0x0 +-#define MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x0058 0x02C8 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x0058 0x02C8 0x0000 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA09__UART6_DTE_RX 0x0058 0x02C8 0x071C 0x3 0x1 +-#define MX7D_PAD_EPDC_DATA09__EIM_RW 0x0058 0x02C8 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x0058 0x02C8 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_DATA09__LCD_DATA9 0x0058 0x02C8 0x065C 0x6 0x0 +-#define MX7D_PAD_EPDC_DATA09__LCD_DATA0 0x0058 0x02C8 0x0638 0x7 0x1 +-#define MX7D_PAD_EPDC_DATA09__EPDC_SDLE 0x0058 0x02C8 0x0000 0x8 0x0 +-#define MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x005C 0x02CC 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B 0x005C 0x02CC 0x0000 0x1 0x0 +-#define MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x005C 0x02CC 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x005C 0x02CC 0x0718 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS 0x005C 0x02CC 0x0000 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA10__EIM_CS0_B 0x005C 0x02CC 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x005C 0x02CC 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_DATA10__LCD_DATA10 0x005C 0x02CC 0x0660 0x6 0x0 +-#define MX7D_PAD_EPDC_DATA10__LCD_DATA9 0x005C 0x02CC 0x065C 0x7 0x1 +-#define MX7D_PAD_EPDC_DATA10__EPDC_SDOE 0x005C 0x02CC 0x0000 0x8 0x0 +-#define MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x0060 0x02D0 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN 0x0060 0x02D0 0x0000 0x1 0x0 +-#define MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x0060 0x02D0 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x0060 0x02D0 0x0000 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS 0x0060 0x02D0 0x0718 0x3 0x1 +-#define MX7D_PAD_EPDC_DATA11__EIM_BCLK 0x0060 0x02D0 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x0060 0x02D0 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_DATA11__LCD_DATA11 0x0060 0x02D0 0x0664 0x6 0x0 +-#define MX7D_PAD_EPDC_DATA11__LCD_DATA1 0x0060 0x02D0 0x063C 0x7 0x1 +-#define MX7D_PAD_EPDC_DATA11__EPDC_SDCE0 0x0060 0x02D0 0x0000 0x8 0x0 +-#define MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x0064 0x02D4 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD 0x0064 0x02D4 0x06E0 0x1 0x0 +-#define MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x0064 0x02D4 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x0064 0x02D4 0x0724 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA12__UART7_DTE_TX 0x0064 0x02D4 0x0000 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA12__EIM_LBA_B 0x0064 0x02D4 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x0064 0x02D4 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_DATA12__LCD_DATA12 0x0064 0x02D4 0x0668 0x6 0x0 +-#define MX7D_PAD_EPDC_DATA12__LCD_DATA21 0x0064 0x02D4 0x068C 0x7 0x0 +-#define MX7D_PAD_EPDC_DATA12__EPDC_GDCLK 0x0064 0x02D4 0x0000 0x8 0x0 +-#define MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x0068 0x02D8 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD 0x0068 0x02D8 0x06EC 0x1 0x0 +-#define MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x0068 0x02D8 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x0068 0x02D8 0x0000 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA13__UART7_DTE_RX 0x0068 0x02D8 0x0724 0x3 0x1 +-#define MX7D_PAD_EPDC_DATA13__EIM_WAIT 0x0068 0x02D8 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x0068 0x02D8 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_DATA13__LCD_DATA13 0x0068 0x02D8 0x066C 0x6 0x0 +-#define MX7D_PAD_EPDC_DATA13__LCD_CS 0x0068 0x02D8 0x0000 0x7 0x0 +-#define MX7D_PAD_EPDC_DATA13__EPDC_GDOE 0x0068 0x02D8 0x0000 0x8 0x0 +-#define MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x006C 0x02DC 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK 0x006C 0x02DC 0x0000 0x1 0x0 +-#define MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x006C 0x02DC 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x006C 0x02DC 0x0720 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS 0x006C 0x02DC 0x0000 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA14__EIM_EB_B0 0x006C 0x02DC 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x006C 0x02DC 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_DATA14__LCD_DATA14 0x006C 0x02DC 0x0670 0x6 0x0 +-#define MX7D_PAD_EPDC_DATA14__LCD_DATA22 0x006C 0x02DC 0x0690 0x7 0x0 +-#define MX7D_PAD_EPDC_DATA14__EPDC_GDSP 0x006C 0x02DC 0x0000 0x8 0x0 +-#define MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x0070 0x02E0 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B 0x0070 0x02E0 0x0000 0x1 0x0 +-#define MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x0070 0x02E0 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x0070 0x02E0 0x0000 0x3 0x0 +-#define MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS 0x0070 0x02E0 0x0720 0x3 0x1 +-#define MX7D_PAD_EPDC_DATA15__EIM_CS1_B 0x0070 0x02E0 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x0070 0x02E0 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_DATA15__LCD_DATA15 0x0070 0x02E0 0x0674 0x6 0x0 +-#define MX7D_PAD_EPDC_DATA15__LCD_WR_RWN 0x0070 0x02E0 0x0000 0x7 0x0 +-#define MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM 0x0070 0x02E0 0x0000 0x8 0x0 +-#define MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x0074 0x02E4 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN 0x0074 0x02E4 0x0000 0x1 0x0 +-#define MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x0074 0x02E4 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_SDCLK__KPP_ROW4 0x0074 0x02E4 0x0624 0x3 0x0 +-#define MX7D_PAD_EPDC_SDCLK__EIM_AD10 0x0074 0x02E4 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x0074 0x02E4 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_SDCLK__LCD_CLK 0x0074 0x02E4 0x0000 0x6 0x0 +-#define MX7D_PAD_EPDC_SDCLK__LCD_DATA20 0x0074 0x02E4 0x0688 0x7 0x0 +-#define MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x0078 0x02E8 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD 0x0078 0x02E8 0x0000 0x1 0x0 +-#define MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x0078 0x02E8 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_SDLE__KPP_COL4 0x0078 0x02E8 0x0604 0x3 0x0 +-#define MX7D_PAD_EPDC_SDLE__EIM_AD11 0x0078 0x02E8 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x0078 0x02E8 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_SDLE__LCD_DATA16 0x0078 0x02E8 0x0678 0x6 0x0 +-#define MX7D_PAD_EPDC_SDLE__LCD_DATA8 0x0078 0x02E8 0x0658 0x7 0x1 +-#define MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x007C 0x02EC 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0 0x007C 0x02EC 0x0584 0x1 0x0 +-#define MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x007C 0x02EC 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_SDOE__KPP_COL5 0x007C 0x02EC 0x0608 0x3 0x1 +-#define MX7D_PAD_EPDC_SDOE__EIM_AD12 0x007C 0x02EC 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x007C 0x02EC 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_SDOE__LCD_DATA17 0x007C 0x02EC 0x067C 0x6 0x0 +-#define MX7D_PAD_EPDC_SDOE__LCD_DATA23 0x007C 0x02EC 0x0694 0x7 0x0 +-#define MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x0080 0x02F0 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1 0x0080 0x02F0 0x0588 0x1 0x0 +-#define MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x0080 0x02F0 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_SDSHR__KPP_ROW5 0x0080 0x02F0 0x0628 0x3 0x1 +-#define MX7D_PAD_EPDC_SDSHR__EIM_AD13 0x0080 0x02F0 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x0080 0x02F0 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_SDSHR__LCD_DATA18 0x0080 0x02F0 0x0680 0x6 0x0 +-#define MX7D_PAD_EPDC_SDSHR__LCD_DATA10 0x0080 0x02F0 0x0660 0x7 0x1 +-#define MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x0084 0x02F4 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2 0x0084 0x02F4 0x058C 0x1 0x0 +-#define MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x0084 0x02F4 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_SDCE0__EIM_AD14 0x0084 0x02F4 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x0084 0x02F4 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_SDCE0__LCD_DATA19 0x0084 0x02F4 0x0684 0x6 0x0 +-#define MX7D_PAD_EPDC_SDCE0__LCD_DATA5 0x0084 0x02F4 0x064C 0x7 0x1 +-#define MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x0088 0x02F8 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3 0x0088 0x02F8 0x0590 0x1 0x0 +-#define MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x0088 0x02F8 0x0578 0x2 0x0 +-#define MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER 0x0088 0x02F8 0x0000 0x3 0x0 +-#define MX7D_PAD_EPDC_SDCE1__EIM_AD15 0x0088 0x02F8 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x0088 0x02F8 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_SDCE1__LCD_DATA20 0x0088 0x02F8 0x0688 0x6 0x1 +-#define MX7D_PAD_EPDC_SDCE1__LCD_DATA4 0x0088 0x02F8 0x0648 0x7 0x1 +-#define MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 0x008C 0x02FC 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN 0x008C 0x02FC 0x0000 0x1 0x0 +-#define MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x008C 0x02FC 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_SDCE2__KPP_COL6 0x008C 0x02FC 0x060C 0x3 0x1 +-#define MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 0x008C 0x02FC 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x008C 0x02FC 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_SDCE2__LCD_DATA21 0x008C 0x02FC 0x068C 0x6 0x1 +-#define MX7D_PAD_EPDC_SDCE2__LCD_DATA3 0x008C 0x02FC 0x0644 0x7 0x1 +-#define MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 0x0090 0x0300 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD 0x0090 0x0300 0x06E8 0x1 0x0 +-#define MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x0090 0x0300 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_SDCE3__KPP_ROW6 0x0090 0x0300 0x062C 0x3 0x1 +-#define MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 0x0090 0x0300 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x0090 0x0300 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_SDCE3__LCD_DATA22 0x0090 0x0300 0x0690 0x6 0x1 +-#define MX7D_PAD_EPDC_SDCE3__LCD_DATA2 0x0090 0x0300 0x0640 0x7 0x1 +-#define MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x0094 0x0304 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0 0x0094 0x0304 0x05AC 0x1 0x0 +-#define MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x0094 0x0304 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_GDCLK__KPP_COL7 0x0094 0x0304 0x0610 0x3 0x0 +-#define MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 0x0094 0x0304 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x0094 0x0304 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_GDCLK__LCD_DATA23 0x0094 0x0304 0x0694 0x6 0x1 +-#define MX7D_PAD_EPDC_GDCLK__LCD_DATA16 0x0094 0x0304 0x0678 0x7 0x1 +-#define MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x0098 0x0308 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1 0x0098 0x0308 0x05B0 0x1 0x0 +-#define MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x0098 0x0308 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_GDOE__KPP_ROW7 0x0098 0x0308 0x0630 0x3 0x0 +-#define MX7D_PAD_EPDC_GDOE__EIM_ADDR19 0x0098 0x0308 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x0098 0x0308 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_GDOE__LCD_WR_RWN 0x0098 0x0308 0x0000 0x6 0x0 +-#define MX7D_PAD_EPDC_GDOE__LCD_DATA18 0x0098 0x0308 0x0680 0x7 0x1 +-#define MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x009C 0x030C 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2 0x009C 0x030C 0x05B4 0x1 0x0 +-#define MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x009C 0x030C 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_GDRL__EIM_ADDR20 0x009C 0x030C 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x009C 0x030C 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_GDRL__LCD_RD_E 0x009C 0x030C 0x0000 0x6 0x0 +-#define MX7D_PAD_EPDC_GDRL__LCD_DATA19 0x009C 0x030C 0x0684 0x7 0x1 +-#define MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x00A0 0x0310 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3 0x00A0 0x0310 0x05B8 0x1 0x0 +-#define MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x00A0 0x0310 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_GDSP__ENET2_TX_ER 0x00A0 0x0310 0x0000 0x3 0x0 +-#define MX7D_PAD_EPDC_GDSP__EIM_ADDR21 0x00A0 0x0310 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x00A0 0x0310 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_GDSP__LCD_BUSY 0x00A0 0x0310 0x0634 0x6 0x1 +-#define MX7D_PAD_EPDC_GDSP__LCD_DATA17 0x00A0 0x0310 0x067C 0x7 0x1 +-#define MX7D_PAD_EPDC_BDR0__EPDC_BDR0 0x00A4 0x0314 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK 0x00A4 0x0314 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 0x00A4 0x0314 0x0570 0x3 0x1 +-#define MX7D_PAD_EPDC_BDR0__EIM_ADDR22 0x00A4 0x0314 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x00A4 0x0314 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_BDR0__LCD_CS 0x00A4 0x0314 0x0000 0x6 0x0 +-#define MX7D_PAD_EPDC_BDR0__LCD_DATA7 0x00A4 0x0314 0x0654 0x7 0x1 +-#define MX7D_PAD_EPDC_BDR1__EPDC_BDR1 0x00A8 0x0318 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN 0x00A8 0x0318 0x0000 0x1 0x0 +-#define MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK 0x00A8 0x0318 0x0578 0x2 0x1 +-#define MX7D_PAD_EPDC_BDR1__EIM_AD8 0x00A8 0x0318 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x00A8 0x0318 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_BDR1__LCD_ENABLE 0x00A8 0x0318 0x0000 0x6 0x0 +-#define MX7D_PAD_EPDC_BDR1__LCD_DATA6 0x00A8 0x0318 0x0650 0x7 0x1 +-#define MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00AC 0x031C 0x0000 0x0 0x0 +-#define MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA 0x00AC 0x031C 0x05CC 0x1 0x0 +-#define MX7D_PAD_EPDC_PWR_COM__ENET2_CRS 0x00AC 0x031C 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_PWR_COM__EIM_AD9 0x00AC 0x031C 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x00AC 0x031C 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC 0x00AC 0x031C 0x0000 0x6 0x0 +-#define MX7D_PAD_EPDC_PWR_COM__LCD_DATA11 0x00AC 0x031C 0x0664 0x7 0x1 +-#define MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00B0 0x0320 0x0580 0x0 0x0 +-#define MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB 0x00B0 0x0320 0x05D0 0x1 0x0 +-#define MX7D_PAD_EPDC_PWR_STAT__ENET2_COL 0x00B0 0x0320 0x0000 0x2 0x0 +-#define MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1 0x00B0 0x0320 0x0000 0x4 0x0 +-#define MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x00B0 0x0320 0x0000 0x5 0x0 +-#define MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC 0x00B0 0x0320 0x0698 0x6 0x1 +-#define MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12 0x00B0 0x0320 0x0668 0x7 0x1 +-#define MX7D_PAD_LCD_CLK__LCD_CLK 0x00B4 0x0324 0x0000 0x0 0x0 +-#define MX7D_PAD_LCD_CLK__ECSPI4_MISO 0x00B4 0x0324 0x0558 0x1 0x0 +-#define MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN 0x00B4 0x0324 0x0000 0x2 0x0 +-#define MX7D_PAD_LCD_CLK__CSI_DATA16 0x00B4 0x0324 0x0000 0x3 0x0 +-#define MX7D_PAD_LCD_CLK__UART2_DCE_RX 0x00B4 0x0324 0x06FC 0x4 0x0 +-#define MX7D_PAD_LCD_CLK__UART2_DTE_TX 0x00B4 0x0324 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_CLK__GPIO3_IO0 0x00B4 0x0324 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x00B8 0x0328 0x0000 0x0 0x0 +-#define MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI 0x00B8 0x0328 0x055C 0x1 0x0 +-#define MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN 0x00B8 0x0328 0x0000 0x2 0x0 +-#define MX7D_PAD_LCD_ENABLE__CSI_DATA17 0x00B8 0x0328 0x0000 0x3 0x0 +-#define MX7D_PAD_LCD_ENABLE__UART2_DCE_TX 0x00B8 0x0328 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_ENABLE__UART2_DTE_RX 0x00B8 0x0328 0x06FC 0x4 0x1 +-#define MX7D_PAD_LCD_ENABLE__GPIO3_IO1 0x00B8 0x0328 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x00BC 0x032C 0x0000 0x0 0x0 +-#define MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK 0x00BC 0x032C 0x0554 0x1 0x0 +-#define MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN 0x00BC 0x032C 0x0000 0x2 0x0 +-#define MX7D_PAD_LCD_HSYNC__CSI_DATA18 0x00BC 0x032C 0x0000 0x3 0x0 +-#define MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS 0x00BC 0x032C 0x06F8 0x4 0x0 +-#define MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS 0x00BC 0x032C 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_HSYNC__GPIO3_IO2 0x00BC 0x032C 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x00C0 0x0330 0x0698 0x0 0x2 +-#define MX7D_PAD_LCD_VSYNC__ECSPI4_SS0 0x00C0 0x0330 0x0560 0x1 0x0 +-#define MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN 0x00C0 0x0330 0x0000 0x2 0x0 +-#define MX7D_PAD_LCD_VSYNC__CSI_DATA19 0x00C0 0x0330 0x0000 0x3 0x0 +-#define MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS 0x00C0 0x0330 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS 0x00C0 0x0330 0x06F8 0x4 0x1 +-#define MX7D_PAD_LCD_VSYNC__GPIO3_IO3 0x00C0 0x0330 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_RESET__LCD_RESET 0x00C4 0x0334 0x0000 0x0 0x0 +-#define MX7D_PAD_LCD_RESET__GPT1_COMPARE1 0x00C4 0x0334 0x0000 0x1 0x0 +-#define MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI 0x00C4 0x0334 0x0000 0x2 0x0 +-#define MX7D_PAD_LCD_RESET__CSI_FIELD 0x00C4 0x0334 0x0000 0x3 0x0 +-#define MX7D_PAD_LCD_RESET__EIM_DTACK_B 0x00C4 0x0334 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_RESET__GPIO3_IO4 0x00C4 0x0334 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA00__LCD_DATA0 0x00C8 0x0338 0x0638 0x0 0x2 +-#define MX7D_PAD_LCD_DATA00__GPT1_COMPARE2 0x00C8 0x0338 0x0000 0x1 0x0 +-#define MX7D_PAD_LCD_DATA00__CSI_DATA20 0x00C8 0x0338 0x0000 0x3 0x0 +-#define MX7D_PAD_LCD_DATA00__EIM_DATA0 0x00C8 0x0338 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA00__GPIO3_IO5 0x00C8 0x0338 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0 0x00C8 0x0338 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA01__LCD_DATA1 0x00CC 0x033C 0x063C 0x0 0x2 +-#define MX7D_PAD_LCD_DATA01__GPT1_COMPARE3 0x00CC 0x033C 0x0000 0x1 0x0 +-#define MX7D_PAD_LCD_DATA01__CSI_DATA21 0x00CC 0x033C 0x0000 0x3 0x0 +-#define MX7D_PAD_LCD_DATA01__EIM_DATA1 0x00CC 0x033C 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA01__GPIO3_IO6 0x00CC 0x033C 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1 0x00CC 0x033C 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA02__LCD_DATA2 0x00D0 0x0340 0x0640 0x0 0x2 +-#define MX7D_PAD_LCD_DATA02__GPT1_CLK 0x00D0 0x0340 0x0000 0x1 0x0 +-#define MX7D_PAD_LCD_DATA02__CSI_DATA22 0x00D0 0x0340 0x0000 0x3 0x0 +-#define MX7D_PAD_LCD_DATA02__EIM_DATA2 0x00D0 0x0340 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA02__GPIO3_IO7 0x00D0 0x0340 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2 0x00D0 0x0340 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA03__LCD_DATA3 0x00D4 0x0344 0x0644 0x0 0x2 +-#define MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1 0x00D4 0x0344 0x0000 0x1 0x0 +-#define MX7D_PAD_LCD_DATA03__CSI_DATA23 0x00D4 0x0344 0x0000 0x3 0x0 +-#define MX7D_PAD_LCD_DATA03__EIM_DATA3 0x00D4 0x0344 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA03__GPIO3_IO8 0x00D4 0x0344 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3 0x00D4 0x0344 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA04__LCD_DATA4 0x00D8 0x0348 0x0648 0x0 0x2 +-#define MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2 0x00D8 0x0348 0x0000 0x1 0x0 +-#define MX7D_PAD_LCD_DATA04__CSI_VSYNC 0x00D8 0x0348 0x0520 0x3 0x0 +-#define MX7D_PAD_LCD_DATA04__EIM_DATA4 0x00D8 0x0348 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA04__GPIO3_IO9 0x00D8 0x0348 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4 0x00D8 0x0348 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA05__LCD_DATA5 0x00DC 0x034C 0x064C 0x0 0x2 +-#define MX7D_PAD_LCD_DATA05__CSI_HSYNC 0x00DC 0x034C 0x0518 0x3 0x0 +-#define MX7D_PAD_LCD_DATA05__EIM_DATA5 0x00DC 0x034C 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA05__GPIO3_IO10 0x00DC 0x034C 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5 0x00DC 0x034C 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA06__LCD_DATA6 0x00E0 0x0350 0x0650 0x0 0x2 +-#define MX7D_PAD_LCD_DATA06__CSI_PIXCLK 0x00E0 0x0350 0x051C 0x3 0x0 +-#define MX7D_PAD_LCD_DATA06__EIM_DATA6 0x00E0 0x0350 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA06__GPIO3_IO11 0x00E0 0x0350 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6 0x00E0 0x0350 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA07__LCD_DATA7 0x00E4 0x0354 0x0654 0x0 0x2 +-#define MX7D_PAD_LCD_DATA07__CSI_MCLK 0x00E4 0x0354 0x0000 0x3 0x0 +-#define MX7D_PAD_LCD_DATA07__EIM_DATA7 0x00E4 0x0354 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA07__GPIO3_IO12 0x00E4 0x0354 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7 0x00E4 0x0354 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA08__LCD_DATA8 0x00E8 0x0358 0x0658 0x0 0x2 +-#define MX7D_PAD_LCD_DATA08__CSI_DATA9 0x00E8 0x0358 0x0514 0x3 0x0 +-#define MX7D_PAD_LCD_DATA08__EIM_DATA8 0x00E8 0x0358 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA08__GPIO3_IO13 0x00E8 0x0358 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8 0x00E8 0x0358 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA09__LCD_DATA9 0x00EC 0x035C 0x065C 0x0 0x2 +-#define MX7D_PAD_LCD_DATA09__CSI_DATA8 0x00EC 0x035C 0x0510 0x3 0x0 +-#define MX7D_PAD_LCD_DATA09__EIM_DATA9 0x00EC 0x035C 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA09__GPIO3_IO14 0x00EC 0x035C 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9 0x00EC 0x035C 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA10__LCD_DATA10 0x00F0 0x0360 0x0660 0x0 0x2 +-#define MX7D_PAD_LCD_DATA10__CSI_DATA7 0x00F0 0x0360 0x050C 0x3 0x0 +-#define MX7D_PAD_LCD_DATA10__EIM_DATA10 0x00F0 0x0360 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA10__GPIO3_IO15 0x00F0 0x0360 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x00F0 0x0360 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA11__LCD_DATA11 0x00F4 0x0364 0x0664 0x0 0x2 +-#define MX7D_PAD_LCD_DATA11__CSI_DATA6 0x00F4 0x0364 0x0508 0x3 0x0 +-#define MX7D_PAD_LCD_DATA11__EIM_DATA11 0x00F4 0x0364 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA11__GPIO3_IO16 0x00F4 0x0364 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x00F4 0x0364 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA12__LCD_DATA12 0x00F8 0x0368 0x0668 0x0 0x2 +-#define MX7D_PAD_LCD_DATA12__CSI_DATA5 0x00F8 0x0368 0x0504 0x3 0x0 +-#define MX7D_PAD_LCD_DATA12__EIM_DATA12 0x00F8 0x0368 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA12__GPIO3_IO17 0x00F8 0x0368 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x00F8 0x0368 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA13__LCD_DATA13 0x00FC 0x036C 0x066C 0x0 0x1 +-#define MX7D_PAD_LCD_DATA13__CSI_DATA4 0x00FC 0x036C 0x0500 0x3 0x0 +-#define MX7D_PAD_LCD_DATA13__EIM_DATA13 0x00FC 0x036C 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA13__GPIO3_IO18 0x00FC 0x036C 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x00FC 0x036C 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA14__LCD_DATA14 0x0100 0x0370 0x0670 0x0 0x1 +-#define MX7D_PAD_LCD_DATA14__CSI_DATA3 0x0100 0x0370 0x04FC 0x3 0x0 +-#define MX7D_PAD_LCD_DATA14__EIM_DATA14 0x0100 0x0370 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA14__GPIO3_IO19 0x0100 0x0370 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0100 0x0370 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA15__LCD_DATA15 0x0104 0x0374 0x0674 0x0 0x1 +-#define MX7D_PAD_LCD_DATA15__CSI_DATA2 0x0104 0x0374 0x04F8 0x3 0x0 +-#define MX7D_PAD_LCD_DATA15__EIM_DATA15 0x0104 0x0374 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA15__GPIO3_IO20 0x0104 0x0374 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0104 0x0374 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA16__LCD_DATA16 0x0108 0x0378 0x0678 0x0 0x2 +-#define MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4 0x0108 0x0378 0x0594 0x1 0x0 +-#define MX7D_PAD_LCD_DATA16__CSI_DATA1 0x0108 0x0378 0x0000 0x3 0x0 +-#define MX7D_PAD_LCD_DATA16__EIM_CRE 0x0108 0x0378 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA16__GPIO3_IO21 0x0108 0x0378 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16 0x0108 0x0378 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA17__LCD_DATA17 0x010C 0x037C 0x067C 0x0 0x2 +-#define MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5 0x010C 0x037C 0x0598 0x1 0x0 +-#define MX7D_PAD_LCD_DATA17__CSI_DATA0 0x010C 0x037C 0x0000 0x3 0x0 +-#define MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN 0x010C 0x037C 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA17__GPIO3_IO22 0x010C 0x037C 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17 0x010C 0x037C 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA18__LCD_DATA18 0x0110 0x0380 0x0680 0x0 0x2 +-#define MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6 0x0110 0x0380 0x059C 0x1 0x0 +-#define MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO 0x0110 0x0380 0x0000 0x2 0x0 +-#define MX7D_PAD_LCD_DATA18__CSI_DATA15 0x0110 0x0380 0x0000 0x3 0x0 +-#define MX7D_PAD_LCD_DATA18__EIM_CS2_B 0x0110 0x0380 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x0110 0x0380 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18 0x0110 0x0380 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA19__EIM_CS3_B 0x0114 0x0384 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x0114 0x0384 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19 0x0114 0x0384 0x0000 0x6 0x0 +-#define MX7D_PAD_LCD_DATA19__LCD_DATA19 0x0114 0x0384 0x0684 0x0 0x2 +-#define MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7 0x0114 0x0384 0x05A0 0x1 0x0 +-#define MX7D_PAD_LCD_DATA19__CSI_DATA14 0x0114 0x0384 0x0000 0x3 0x0 +-#define MX7D_PAD_LCD_DATA20__EIM_ADDR23 0x0118 0x0388 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x0118 0x0388 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA20__I2C3_SCL 0x0118 0x0388 0x05E4 0x6 0x1 +-#define MX7D_PAD_LCD_DATA20__LCD_DATA20 0x0118 0x0388 0x0688 0x0 0x2 +-#define MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4 0x0118 0x0388 0x05BC 0x1 0x0 +-#define MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT 0x0118 0x0388 0x0000 0x2 0x0 +-#define MX7D_PAD_LCD_DATA20__CSI_DATA13 0x0118 0x0388 0x0000 0x3 0x0 +-#define MX7D_PAD_LCD_DATA21__LCD_DATA21 0x011C 0x038C 0x068C 0x0 0x2 +-#define MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5 0x011C 0x038C 0x05C0 0x1 0x0 +-#define MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT 0x011C 0x038C 0x0000 0x2 0x0 +-#define MX7D_PAD_LCD_DATA21__CSI_DATA12 0x011C 0x038C 0x0000 0x3 0x0 +-#define MX7D_PAD_LCD_DATA21__EIM_ADDR24 0x011C 0x038C 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x011C 0x038C 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA21__I2C3_SDA 0x011C 0x038C 0x05E8 0x6 0x1 +-#define MX7D_PAD_LCD_DATA22__LCD_DATA22 0x0120 0x0390 0x0690 0x0 0x2 +-#define MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6 0x0120 0x0390 0x05C4 0x1 0x0 +-#define MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT 0x0120 0x0390 0x0000 0x2 0x0 +-#define MX7D_PAD_LCD_DATA22__CSI_DATA11 0x0120 0x0390 0x0000 0x3 0x0 +-#define MX7D_PAD_LCD_DATA22__EIM_ADDR25 0x0120 0x0390 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x0120 0x0390 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA22__I2C4_SCL 0x0120 0x0390 0x05EC 0x6 0x1 +-#define MX7D_PAD_LCD_DATA23__LCD_DATA23 0x0124 0x0394 0x0694 0x0 0x2 +-#define MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7 0x0124 0x0394 0x05C8 0x1 0x0 +-#define MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT 0x0124 0x0394 0x0000 0x2 0x0 +-#define MX7D_PAD_LCD_DATA23__CSI_DATA10 0x0124 0x0394 0x0000 0x3 0x0 +-#define MX7D_PAD_LCD_DATA23__EIM_ADDR26 0x0124 0x0394 0x0000 0x4 0x0 +-#define MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x0124 0x0394 0x0000 0x5 0x0 +-#define MX7D_PAD_LCD_DATA23__I2C4_SDA 0x0124 0x0394 0x05F0 0x6 0x1 +-#define MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0128 0x0398 0x06F4 0x0 0x0 +-#define MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0128 0x0398 0x0000 0x0 0x0 +-#define MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x0128 0x0398 0x05D4 0x1 0x0 +-#define MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY 0x0128 0x0398 0x0000 0x2 0x0 +-#define MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 0x0128 0x0398 0x0000 0x3 0x0 +-#define MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN 0x0128 0x0398 0x0000 0x4 0x0 +-#define MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x0128 0x0398 0x0000 0x5 0x0 +-#define MX7D_PAD_UART1_RX_DATA__ENET1_MDIO 0x0128 0x0398 0x0000 0x6 0x0 +-#define MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x012C 0x039C 0x0000 0x0 0x0 +-#define MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x012C 0x039C 0x06F4 0x0 0x1 +-#define MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x012C 0x039C 0x05D8 0x1 0x0 +-#define MX7D_PAD_UART1_TX_DATA__SAI3_MCLK 0x012C 0x039C 0x0000 0x2 0x0 +-#define MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2 0x012C 0x039C 0x0000 0x3 0x0 +-#define MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x012C 0x039C 0x0000 0x4 0x0 +-#define MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x012C 0x039C 0x0000 0x5 0x0 +-#define MX7D_PAD_UART1_TX_DATA__ENET1_MDC 0x012C 0x039C 0x0000 0x6 0x0 +-#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x06FC 0x0 0x2 +-#define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0130 0x03A0 0x0000 0x0 0x0 +-#define MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x0130 0x03A0 0x05DC 0x1 0x0 +-#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x06C4 0x2 0x0 +-#define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 0x0130 0x03A0 0x0000 0x3 0x0 +-#define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN 0x0130 0x03A0 0x0000 0x4 0x0 +-#define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0 +-#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0574 0x6 0x1 +-#define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0134 0x03A4 0x0000 0x0 0x0 +-#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x06FC 0x0 0x3 +-#define MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x0134 0x03A4 0x05E0 0x1 0x0 +-#define MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 0x0134 0x03A4 0x06C8 0x2 0x0 +-#define MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY 0x0134 0x03A4 0x0000 0x3 0x0 +-#define MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT 0x0134 0x03A4 0x0000 0x4 0x0 +-#define MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x0134 0x03A4 0x0000 0x5 0x0 +-#define MX7D_PAD_UART2_TX_DATA__ENET2_MDC 0x0134 0x03A4 0x0000 0x6 0x0 +-#define MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x0138 0x03A8 0x0704 0x0 0x2 +-#define MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x0138 0x03A8 0x0000 0x0 0x0 +-#define MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC 0x0138 0x03A8 0x072C 0x1 0x0 +-#define MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC 0x0138 0x03A8 0x06CC 0x2 0x0 +-#define MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO 0x0138 0x03A8 0x0528 0x3 0x0 +-#define MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN 0x0138 0x03A8 0x0000 0x4 0x0 +-#define MX7D_PAD_UART3_RX_DATA__GPIO4_IO4 0x0138 0x03A8 0x0000 0x5 0x0 +-#define MX7D_PAD_UART3_RX_DATA__SD1_LCTL 0x0138 0x03A8 0x0000 0x6 0x0 +-#define MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x013C 0x03AC 0x0000 0x0 0x0 +-#define MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x013C 0x03AC 0x0704 0x0 0x3 +-#define MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR 0x013C 0x03AC 0x0000 0x1 0x0 +-#define MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x013C 0x03AC 0x06D0 0x2 0x0 +-#define MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI 0x013C 0x03AC 0x052C 0x3 0x0 +-#define MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT 0x013C 0x03AC 0x0000 0x4 0x0 +-#define MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x013C 0x03AC 0x0000 0x5 0x0 +-#define MX7D_PAD_UART3_TX_DATA__SD2_LCTL 0x013C 0x03AC 0x0000 0x6 0x0 +-#define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x0140 0x03B0 0x0700 0x0 0x2 +-#define MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x0140 0x03B0 0x0000 0x0 0x0 +-#define MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x0140 0x03B0 0x0728 0x1 0x0 +-#define MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x0140 0x03B0 0x0000 0x2 0x0 +-#define MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK 0x0140 0x03B0 0x0000 0x3 0x0 +-#define MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN 0x0140 0x03B0 0x0000 0x4 0x0 +-#define MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x0140 0x03B0 0x0000 0x5 0x0 +-#define MX7D_PAD_UART3_RTS_B__SD3_LCTL 0x0140 0x03B0 0x0000 0x6 0x0 +-#define MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x0144 0x03B4 0x0000 0x0 0x0 +-#define MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x0144 0x03B4 0x0700 0x0 0x3 +-#define MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR 0x0144 0x03B4 0x0000 0x1 0x0 +-#define MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x0144 0x03B4 0x06D4 0x2 0x0 +-#define MX7D_PAD_UART3_CTS_B__ECSPI1_SS0 0x0144 0x03B4 0x0530 0x3 0x0 +-#define MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT 0x0144 0x03B4 0x0000 0x4 0x0 +-#define MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x0144 0x03B4 0x0000 0x5 0x0 +-#define MX7D_PAD_UART3_CTS_B__SD1_VSELECT 0x0144 0x03B4 0x0000 0x6 0x0 +-#define MX7D_PAD_I2C1_SCL__I2C1_SCL 0x0148 0x03B8 0x05D4 0x0 0x1 +-#define MX7D_PAD_I2C1_SCL__UART4_DCE_CTS 0x0148 0x03B8 0x0000 0x1 0x0 +-#define MX7D_PAD_I2C1_SCL__UART4_DTE_RTS 0x0148 0x03B8 0x0708 0x1 0x0 +-#define MX7D_PAD_I2C1_SCL__FLEXCAN1_RX 0x0148 0x03B8 0x04DC 0x2 0x1 +-#define MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x0148 0x03B8 0x0548 0x3 0x0 +-#define MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x0148 0x03B8 0x0000 0x5 0x0 +-#define MX7D_PAD_I2C1_SCL__SD2_VSELECT 0x0148 0x03B8 0x0000 0x6 0x0 +-#define MX7D_PAD_I2C1_SDA__I2C1_SDA 0x014C 0x03BC 0x05D8 0x0 0x1 +-#define MX7D_PAD_I2C1_SDA__UART4_DCE_RTS 0x014C 0x03BC 0x0708 0x1 0x1 +-#define MX7D_PAD_I2C1_SDA__UART4_DTE_CTS 0x014C 0x03BC 0x0000 0x1 0x0 +-#define MX7D_PAD_I2C1_SDA__FLEXCAN1_TX 0x014C 0x03BC 0x0000 0x2 0x0 +-#define MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x014C 0x03BC 0x054C 0x3 0x0 +-#define MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1 0x014C 0x03BC 0x0564 0x4 0x1 +-#define MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x014C 0x03BC 0x0000 0x5 0x0 +-#define MX7D_PAD_I2C1_SDA__SD3_VSELECT 0x014C 0x03BC 0x0000 0x6 0x0 +-#define MX7D_PAD_I2C2_SCL__I2C2_SCL 0x0150 0x03C0 0x05DC 0x0 0x1 +-#define MX7D_PAD_I2C2_SCL__UART4_DCE_RX 0x0150 0x03C0 0x070C 0x1 0x0 +-#define MX7D_PAD_I2C2_SCL__UART4_DTE_TX 0x0150 0x03C0 0x0000 0x1 0x0 +-#define MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B 0x0150 0x03C0 0x0000 0x2 0x0 +-#define MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x0150 0x03C0 0x0544 0x3 0x0 +-#define MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2 0x0150 0x03C0 0x0570 0x4 0x2 +-#define MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x0150 0x03C0 0x0000 0x5 0x0 +-#define MX7D_PAD_I2C2_SCL__SD3_CD_B 0x0150 0x03C0 0x0738 0x6 0x1 +-#define MX7D_PAD_I2C2_SDA__I2C2_SDA 0x0154 0x03C4 0x05E0 0x0 0x1 +-#define MX7D_PAD_I2C2_SDA__UART4_DCE_TX 0x0154 0x03C4 0x0000 0x1 0x0 +-#define MX7D_PAD_I2C2_SDA__UART4_DTE_RX 0x0154 0x03C4 0x070C 0x1 0x1 +-#define MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB 0x0154 0x03C4 0x0000 0x2 0x0 +-#define MX7D_PAD_I2C2_SDA__ECSPI3_SS0 0x0154 0x03C4 0x0550 0x3 0x0 +-#define MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3 0x0154 0x03C4 0x0000 0x4 0x0 +-#define MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x0154 0x03C4 0x0000 0x5 0x0 +-#define MX7D_PAD_I2C2_SDA__SD3_WP 0x0154 0x03C4 0x073C 0x6 0x1 +-#define MX7D_PAD_I2C3_SCL__I2C3_SCL 0x0158 0x03C8 0x05E4 0x0 0x2 +-#define MX7D_PAD_I2C3_SCL__UART5_DCE_CTS 0x0158 0x03C8 0x0000 0x1 0x0 +-#define MX7D_PAD_I2C3_SCL__UART5_DTE_RTS 0x0158 0x03C8 0x0710 0x1 0x0 +-#define MX7D_PAD_I2C3_SCL__FLEXCAN2_RX 0x0158 0x03C8 0x04E0 0x2 0x1 +-#define MX7D_PAD_I2C3_SCL__CSI_VSYNC 0x0158 0x03C8 0x0520 0x3 0x1 +-#define MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0 0x0158 0x03C8 0x06D8 0x4 0x1 +-#define MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x0158 0x03C8 0x0000 0x5 0x0 +-#define MX7D_PAD_I2C3_SCL__EPDC_BDR0 0x0158 0x03C8 0x0000 0x6 0x0 +-#define MX7D_PAD_I2C3_SDA__I2C3_SDA 0x015C 0x03CC 0x05E8 0x0 0x2 +-#define MX7D_PAD_I2C3_SDA__UART5_DCE_RTS 0x015C 0x03CC 0x0710 0x1 0x1 +-#define MX7D_PAD_I2C3_SDA__UART5_DTE_CTS 0x015C 0x03CC 0x0000 0x1 0x0 +-#define MX7D_PAD_I2C3_SDA__FLEXCAN2_TX 0x015C 0x03CC 0x0000 0x2 0x0 +-#define MX7D_PAD_I2C3_SDA__CSI_HSYNC 0x015C 0x03CC 0x0518 0x3 0x1 +-#define MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1 0x015C 0x03CC 0x06DC 0x4 0x1 +-#define MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x015C 0x03CC 0x0000 0x5 0x0 +-#define MX7D_PAD_I2C3_SDA__EPDC_BDR1 0x015C 0x03CC 0x0000 0x6 0x0 +-#define MX7D_PAD_I2C4_SCL__I2C4_SCL 0x0160 0x03D0 0x05EC 0x0 0x2 +-#define MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x0160 0x03D0 0x0714 0x1 0x0 +-#define MX7D_PAD_I2C4_SCL__UART5_DTE_TX 0x0160 0x03D0 0x0000 0x1 0x0 +-#define MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B 0x0160 0x03D0 0x0000 0x2 0x0 +-#define MX7D_PAD_I2C4_SCL__CSI_PIXCLK 0x0160 0x03D0 0x051C 0x3 0x1 +-#define MX7D_PAD_I2C4_SCL__USB_OTG1_ID 0x0160 0x03D0 0x0734 0x4 0x1 +-#define MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x0160 0x03D0 0x0000 0x5 0x0 +-#define MX7D_PAD_I2C4_SCL__EPDC_VCOM0 0x0160 0x03D0 0x0000 0x6 0x0 +-#define MX7D_PAD_I2C4_SDA__I2C4_SDA 0x0164 0x03D4 0x05F0 0x0 0x2 +-#define MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x0164 0x03D4 0x0000 0x1 0x0 +-#define MX7D_PAD_I2C4_SDA__UART5_DTE_RX 0x0164 0x03D4 0x0714 0x1 0x1 +-#define MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB 0x0164 0x03D4 0x0000 0x2 0x0 +-#define MX7D_PAD_I2C4_SDA__CSI_MCLK 0x0164 0x03D4 0x0000 0x3 0x0 +-#define MX7D_PAD_I2C4_SDA__USB_OTG2_ID 0x0164 0x03D4 0x0730 0x4 0x1 +-#define MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x0164 0x03D4 0x0000 0x5 0x0 +-#define MX7D_PAD_I2C4_SDA__EPDC_VCOM1 0x0164 0x03D4 0x0000 0x6 0x0 +-#define MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x0168 0x03D8 0x0524 0x0 0x1 +-#define MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x0168 0x03D8 0x071C 0x1 0x2 +-#define MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x0168 0x03D8 0x0000 0x1 0x0 +-#define MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x0168 0x03D8 0x0000 0x2 0x0 +-#define MX7D_PAD_ECSPI1_SCLK__CSI_DATA2 0x0168 0x03D8 0x04F8 0x3 0x1 +-#define MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x0168 0x03D8 0x0000 0x5 0x0 +-#define MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM 0x0168 0x03D8 0x0000 0x6 0x0 +-#define MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x016C 0x03DC 0x052C 0x0 0x1 +-#define MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x016C 0x03DC 0x0000 0x1 0x0 +-#define MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x016C 0x03DC 0x071C 0x1 0x3 +-#define MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x016C 0x03DC 0x0000 0x2 0x0 +-#define MX7D_PAD_ECSPI1_MOSI__CSI_DATA3 0x016C 0x03DC 0x04FC 0x3 0x1 +-#define MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x016C 0x03DC 0x0000 0x5 0x0 +-#define MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT 0x016C 0x03DC 0x0580 0x6 0x1 +-#define MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x0170 0x03E0 0x0528 0x0 0x1 +-#define MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x0170 0x03E0 0x0718 0x1 0x2 +-#define MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS 0x0170 0x03E0 0x0000 0x1 0x0 +-#define MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x0170 0x03E0 0x0000 0x2 0x0 +-#define MX7D_PAD_ECSPI1_MISO__CSI_DATA4 0x0170 0x03E0 0x0500 0x3 0x1 +-#define MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x0170 0x03E0 0x0000 0x5 0x0 +-#define MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ 0x0170 0x03E0 0x057C 0x6 0x0 +-#define MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 0x0174 0x03E4 0x0530 0x0 0x1 +-#define MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x0174 0x03E4 0x0000 0x1 0x0 +-#define MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS 0x0174 0x03E4 0x0718 0x1 0x3 +-#define MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x0174 0x03E4 0x0000 0x2 0x0 +-#define MX7D_PAD_ECSPI1_SS0__CSI_DATA5 0x0174 0x03E4 0x0504 0x3 0x1 +-#define MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x0174 0x03E4 0x0000 0x5 0x0 +-#define MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3 0x0174 0x03E4 0x0000 0x6 0x0 +-#define MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x0178 0x03E8 0x0534 0x0 0x0 +-#define MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x0178 0x03E8 0x0724 0x1 0x2 +-#define MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX 0x0178 0x03E8 0x0000 0x1 0x0 +-#define MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 0x0178 0x03E8 0x0000 0x2 0x0 +-#define MX7D_PAD_ECSPI2_SCLK__CSI_DATA6 0x0178 0x03E8 0x0508 0x3 0x1 +-#define MX7D_PAD_ECSPI2_SCLK__LCD_DATA13 0x0178 0x03E8 0x066C 0x4 0x2 +-#define MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x0178 0x03E8 0x0000 0x5 0x0 +-#define MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0 0x0178 0x03E8 0x0000 0x6 0x0 +-#define MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x017C 0x03EC 0x053C 0x0 0x0 +-#define MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x017C 0x03EC 0x0000 0x1 0x0 +-#define MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX 0x017C 0x03EC 0x0724 0x1 0x3 +-#define MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 0x017C 0x03EC 0x0000 0x2 0x0 +-#define MX7D_PAD_ECSPI2_MOSI__CSI_DATA7 0x017C 0x03EC 0x050C 0x3 0x1 +-#define MX7D_PAD_ECSPI2_MOSI__LCD_DATA14 0x017C 0x03EC 0x0670 0x4 0x2 +-#define MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x017C 0x03EC 0x0000 0x5 0x0 +-#define MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1 0x017C 0x03EC 0x0000 0x6 0x0 +-#define MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x0180 0x03F0 0x0000 0x5 0x0 +-#define MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2 0x0180 0x03F0 0x0000 0x6 0x0 +-#define MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x0180 0x03F0 0x0538 0x0 0x0 +-#define MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x0180 0x03F0 0x0720 0x1 0x2 +-#define MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS 0x0180 0x03F0 0x0000 0x1 0x0 +-#define MX7D_PAD_ECSPI2_MISO__SD1_DATA6 0x0180 0x03F0 0x0000 0x2 0x0 +-#define MX7D_PAD_ECSPI2_MISO__CSI_DATA8 0x0180 0x03F0 0x0510 0x3 0x1 +-#define MX7D_PAD_ECSPI2_MISO__LCD_DATA15 0x0180 0x03F0 0x0674 0x4 0x2 +-#define MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x0184 0x03F4 0x0540 0x0 0x0 +-#define MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x0184 0x03F4 0x0000 0x1 0x0 +-#define MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS 0x0184 0x03F4 0x0720 0x1 0x3 +-#define MX7D_PAD_ECSPI2_SS0__SD1_DATA7 0x0184 0x03F4 0x0000 0x2 0x0 +-#define MX7D_PAD_ECSPI2_SS0__CSI_DATA9 0x0184 0x03F4 0x0514 0x3 0x1 +-#define MX7D_PAD_ECSPI2_SS0__LCD_RESET 0x0184 0x03F4 0x0000 0x4 0x0 +-#define MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x0184 0x03F4 0x0000 0x5 0x0 +-#define MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE 0x0184 0x03F4 0x0000 0x6 0x0 +-#define MX7D_PAD_SD1_CD_B__SD1_CD_B 0x0188 0x03F8 0x0000 0x0 0x0 +-#define MX7D_PAD_SD1_CD_B__UART6_DCE_RX 0x0188 0x03F8 0x071C 0x2 0x4 +-#define MX7D_PAD_SD1_CD_B__UART6_DTE_TX 0x0188 0x03F8 0x0000 0x2 0x0 +-#define MX7D_PAD_SD1_CD_B__ECSPI4_MISO 0x0188 0x03F8 0x0558 0x3 0x1 +-#define MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0 0x0188 0x03F8 0x0584 0x4 0x1 +-#define MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x0188 0x03F8 0x0000 0x5 0x0 +-#define MX7D_PAD_SD1_CD_B__CCM_CLKO1 0x0188 0x03F8 0x0000 0x6 0x0 +-#define MX7D_PAD_SD1_WP__SD1_WP 0x018C 0x03FC 0x0000 0x0 0x0 +-#define MX7D_PAD_SD1_WP__UART6_DCE_TX 0x018C 0x03FC 0x0000 0x2 0x0 +-#define MX7D_PAD_SD1_WP__UART6_DTE_RX 0x018C 0x03FC 0x071C 0x2 0x5 +-#define MX7D_PAD_SD1_WP__ECSPI4_MOSI 0x018C 0x03FC 0x055C 0x3 0x1 +-#define MX7D_PAD_SD1_WP__FLEXTIMER1_CH1 0x018C 0x03FC 0x0588 0x4 0x1 +-#define MX7D_PAD_SD1_WP__GPIO5_IO1 0x018C 0x03FC 0x0000 0x5 0x0 +-#define MX7D_PAD_SD1_WP__CCM_CLKO2 0x018C 0x03FC 0x0000 0x6 0x0 +-#define MX7D_PAD_SD1_RESET_B__SD1_RESET_B 0x0190 0x0400 0x0000 0x0 0x0 +-#define MX7D_PAD_SD1_RESET_B__SAI3_MCLK 0x0190 0x0400 0x0000 0x1 0x0 +-#define MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS 0x0190 0x0400 0x0718 0x2 0x4 +-#define MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS 0x0190 0x0400 0x0000 0x2 0x0 +-#define MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK 0x0190 0x0400 0x0554 0x3 0x1 +-#define MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2 0x0190 0x0400 0x058C 0x4 0x1 +-#define MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x0190 0x0400 0x0000 0x5 0x0 +-#define MX7D_PAD_SD1_CLK__SD1_CLK 0x0194 0x0404 0x0000 0x0 0x0 +-#define MX7D_PAD_SD1_CLK__SAI3_RX_SYNC 0x0194 0x0404 0x06CC 0x1 0x1 +-#define MX7D_PAD_SD1_CLK__UART6_DCE_CTS 0x0194 0x0404 0x0000 0x2 0x0 +-#define MX7D_PAD_SD1_CLK__UART6_DTE_RTS 0x0194 0x0404 0x0718 0x2 0x5 +-#define MX7D_PAD_SD1_CLK__ECSPI4_SS0 0x0194 0x0404 0x0560 0x3 0x1 +-#define MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3 0x0194 0x0404 0x0590 0x4 0x1 +-#define MX7D_PAD_SD1_CLK__GPIO5_IO3 0x0194 0x0404 0x0000 0x5 0x0 +-#define MX7D_PAD_SD1_CMD__SD1_CMD 0x0198 0x0408 0x0000 0x0 0x0 +-#define MX7D_PAD_SD1_CMD__SAI3_RX_BCLK 0x0198 0x0408 0x06C4 0x1 0x1 +-#define MX7D_PAD_SD1_CMD__ECSPI4_SS1 0x0198 0x0408 0x0000 0x3 0x0 +-#define MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0 0x0198 0x0408 0x05AC 0x4 0x1 +-#define MX7D_PAD_SD1_CMD__GPIO5_IO4 0x0198 0x0408 0x0000 0x5 0x0 +-#define MX7D_PAD_SD1_DATA0__SD1_DATA0 0x019C 0x040C 0x0000 0x0 0x0 +-#define MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0 0x019C 0x040C 0x06C8 0x1 0x1 +-#define MX7D_PAD_SD1_DATA0__UART7_DCE_RX 0x019C 0x040C 0x0724 0x2 0x4 +-#define MX7D_PAD_SD1_DATA0__UART7_DTE_TX 0x019C 0x040C 0x0000 0x2 0x0 +-#define MX7D_PAD_SD1_DATA0__ECSPI4_SS2 0x019C 0x040C 0x0000 0x3 0x0 +-#define MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1 0x019C 0x040C 0x05B0 0x4 0x1 +-#define MX7D_PAD_SD1_DATA0__GPIO5_IO5 0x019C 0x040C 0x0000 0x5 0x0 +-#define MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1 0x019C 0x040C 0x04E4 0x6 0x1 +-#define MX7D_PAD_SD1_DATA1__SD1_DATA1 0x01A0 0x0410 0x0000 0x0 0x0 +-#define MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK 0x01A0 0x0410 0x06D0 0x1 0x1 +-#define MX7D_PAD_SD1_DATA1__UART7_DCE_TX 0x01A0 0x0410 0x0000 0x2 0x0 +-#define MX7D_PAD_SD1_DATA1__UART7_DTE_RX 0x01A0 0x0410 0x0724 0x2 0x5 +-#define MX7D_PAD_SD1_DATA1__ECSPI4_SS3 0x01A0 0x0410 0x0000 0x3 0x0 +-#define MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2 0x01A0 0x0410 0x05B4 0x4 0x1 +-#define MX7D_PAD_SD1_DATA1__GPIO5_IO6 0x01A0 0x0410 0x0000 0x5 0x0 +-#define MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2 0x01A0 0x0410 0x04E8 0x6 0x1 +-#define MX7D_PAD_SD1_DATA2__SD1_DATA2 0x01A4 0x0414 0x0000 0x0 0x0 +-#define MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC 0x01A4 0x0414 0x06D4 0x1 0x1 +-#define MX7D_PAD_SD1_DATA2__UART7_DCE_CTS 0x01A4 0x0414 0x0000 0x2 0x0 +-#define MX7D_PAD_SD1_DATA2__UART7_DTE_RTS 0x01A4 0x0414 0x0720 0x2 0x4 +-#define MX7D_PAD_SD1_DATA2__ECSPI4_RDY 0x01A4 0x0414 0x0000 0x3 0x0 +-#define MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3 0x01A4 0x0414 0x05B8 0x4 0x1 +-#define MX7D_PAD_SD1_DATA2__GPIO5_IO7 0x01A4 0x0414 0x0000 0x5 0x0 +-#define MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3 0x01A4 0x0414 0x04EC 0x6 0x1 +-#define MX7D_PAD_SD1_DATA3__SD1_DATA3 0x01A8 0x0418 0x0000 0x0 0x0 +-#define MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0 0x01A8 0x0418 0x0000 0x1 0x0 +-#define MX7D_PAD_SD1_DATA3__UART7_DCE_RTS 0x01A8 0x0418 0x0720 0x2 0x5 +-#define MX7D_PAD_SD1_DATA3__UART7_DTE_CTS 0x01A8 0x0418 0x0000 0x2 0x0 +-#define MX7D_PAD_SD1_DATA3__ECSPI3_SS1 0x01A8 0x0418 0x0000 0x3 0x0 +-#define MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA 0x01A8 0x0418 0x05A4 0x4 0x1 +-#define MX7D_PAD_SD1_DATA3__GPIO5_IO8 0x01A8 0x0418 0x0000 0x5 0x0 +-#define MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4 0x01A8 0x0418 0x04F0 0x6 0x1 +-#define MX7D_PAD_SD2_CD_B__SD2_CD_B 0x01AC 0x041C 0x0000 0x0 0x0 +-#define MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x01AC 0x041C 0x0568 0x1 0x2 +-#define MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x01AC 0x041C 0x0574 0x2 0x2 +-#define MX7D_PAD_SD2_CD_B__ECSPI3_SS2 0x01AC 0x041C 0x0000 0x3 0x0 +-#define MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB 0x01AC 0x041C 0x05A8 0x4 0x1 +-#define MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x01AC 0x041C 0x0000 0x5 0x0 +-#define MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0 0x01AC 0x041C 0x06D8 0x6 0x2 +-#define MX7D_PAD_SD2_WP__SD2_WP 0x01B0 0x0420 0x0000 0x0 0x0 +-#define MX7D_PAD_SD2_WP__ENET1_MDC 0x01B0 0x0420 0x0000 0x1 0x0 +-#define MX7D_PAD_SD2_WP__ENET2_MDC 0x01B0 0x0420 0x0000 0x2 0x0 +-#define MX7D_PAD_SD2_WP__ECSPI3_SS3 0x01B0 0x0420 0x0000 0x3 0x0 +-#define MX7D_PAD_SD2_WP__USB_OTG1_ID 0x01B0 0x0420 0x0734 0x4 0x2 +-#define MX7D_PAD_SD2_WP__GPIO5_IO10 0x01B0 0x0420 0x0000 0x5 0x0 +-#define MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1 0x01B0 0x0420 0x06DC 0x6 0x2 +-#define MX7D_PAD_SD2_RESET_B__SD2_RESET_B 0x01B4 0x0424 0x0000 0x0 0x0 +-#define MX7D_PAD_SD2_RESET_B__SAI2_MCLK 0x01B4 0x0424 0x0000 0x1 0x0 +-#define MX7D_PAD_SD2_RESET_B__SD2_RESET 0x01B4 0x0424 0x0000 0x2 0x0 +-#define MX7D_PAD_SD2_RESET_B__ECSPI3_RDY 0x01B4 0x0424 0x0000 0x3 0x0 +-#define MX7D_PAD_SD2_RESET_B__USB_OTG2_ID 0x01B4 0x0424 0x0730 0x4 0x2 +-#define MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x01B4 0x0424 0x0000 0x5 0x0 +-#define MX7D_PAD_SD2_CLK__SD2_CLK 0x01B8 0x0428 0x0000 0x0 0x0 +-#define MX7D_PAD_SD2_CLK__SAI2_RX_SYNC 0x01B8 0x0428 0x06B8 0x1 0x0 +-#define MX7D_PAD_SD2_CLK__MQS_RIGHT 0x01B8 0x0428 0x0000 0x2 0x0 +-#define MX7D_PAD_SD2_CLK__GPT4_CLK 0x01B8 0x0428 0x0000 0x3 0x0 +-#define MX7D_PAD_SD2_CLK__GPIO5_IO12 0x01B8 0x0428 0x0000 0x5 0x0 +-#define MX7D_PAD_SD2_CMD__SD2_CMD 0x01BC 0x042C 0x0000 0x0 0x0 +-#define MX7D_PAD_SD2_CMD__SAI2_RX_BCLK 0x01BC 0x042C 0x06B0 0x1 0x0 +-#define MX7D_PAD_SD2_CMD__MQS_LEFT 0x01BC 0x042C 0x0000 0x2 0x0 +-#define MX7D_PAD_SD2_CMD__GPT4_CAPTURE1 0x01BC 0x042C 0x0000 0x3 0x0 +-#define MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD 0x01BC 0x042C 0x06EC 0x4 0x1 +-#define MX7D_PAD_SD2_CMD__GPIO5_IO13 0x01BC 0x042C 0x0000 0x5 0x0 +-#define MX7D_PAD_SD2_DATA0__SD2_DATA0 0x01C0 0x0430 0x0000 0x0 0x0 +-#define MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0 0x01C0 0x0430 0x06B4 0x1 0x0 +-#define MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x01C0 0x0430 0x070C 0x2 0x2 +-#define MX7D_PAD_SD2_DATA0__UART4_DTE_TX 0x01C0 0x0430 0x0000 0x2 0x0 +-#define MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2 0x01C0 0x0430 0x0000 0x3 0x0 +-#define MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK 0x01C0 0x0430 0x0000 0x4 0x0 +-#define MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x01C0 0x0430 0x0000 0x5 0x0 +-#define MX7D_PAD_SD2_DATA1__SD2_DATA1 0x01C4 0x0434 0x0000 0x0 0x0 +-#define MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK 0x01C4 0x0434 0x06BC 0x1 0x0 +-#define MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x01C4 0x0434 0x0000 0x2 0x0 +-#define MX7D_PAD_SD2_DATA1__UART4_DTE_RX 0x01C4 0x0434 0x070C 0x2 0x3 +-#define MX7D_PAD_SD2_DATA1__GPT4_COMPARE1 0x01C4 0x0434 0x0000 0x3 0x0 +-#define MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B 0x01C4 0x0434 0x0000 0x4 0x0 +-#define MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x01C4 0x0434 0x0000 0x5 0x0 +-#define MX7D_PAD_SD2_DATA2__SD2_DATA2 0x01C8 0x0438 0x0000 0x0 0x0 +-#define MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC 0x01C8 0x0438 0x06C0 0x1 0x0 +-#define MX7D_PAD_SD2_DATA2__UART4_DCE_CTS 0x01C8 0x0438 0x0000 0x2 0x0 +-#define MX7D_PAD_SD2_DATA2__UART4_DTE_RTS 0x01C8 0x0438 0x0708 0x2 0x2 +-#define MX7D_PAD_SD2_DATA2__GPT4_COMPARE2 0x01C8 0x0438 0x0000 0x3 0x0 +-#define MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN 0x01C8 0x0438 0x0000 0x4 0x0 +-#define MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x01C8 0x0438 0x0000 0x5 0x0 +-#define MX7D_PAD_SD2_DATA3__SD2_DATA3 0x01CC 0x043C 0x0000 0x0 0x0 +-#define MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0 0x01CC 0x043C 0x0000 0x1 0x0 +-#define MX7D_PAD_SD2_DATA3__UART4_DCE_RTS 0x01CC 0x043C 0x0708 0x2 0x3 +-#define MX7D_PAD_SD2_DATA3__UART4_DTE_CTS 0x01CC 0x043C 0x0000 0x2 0x0 +-#define MX7D_PAD_SD2_DATA3__GPT4_COMPARE3 0x01CC 0x043C 0x0000 0x3 0x0 +-#define MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD 0x01CC 0x043C 0x06E8 0x4 0x1 +-#define MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x01CC 0x043C 0x0000 0x5 0x0 +-#define MX7D_PAD_SD3_CLK__SD3_CLK 0x01D0 0x0440 0x0000 0x0 0x0 +-#define MX7D_PAD_SD3_CLK__NAND_CLE 0x01D0 0x0440 0x0000 0x1 0x0 +-#define MX7D_PAD_SD3_CLK__ECSPI4_MISO 0x01D0 0x0440 0x0558 0x2 0x2 +-#define MX7D_PAD_SD3_CLK__SAI3_RX_SYNC 0x01D0 0x0440 0x06CC 0x3 0x2 +-#define MX7D_PAD_SD3_CLK__GPT3_CLK 0x01D0 0x0440 0x0000 0x4 0x0 +-#define MX7D_PAD_SD3_CLK__GPIO6_IO0 0x01D0 0x0440 0x0000 0x5 0x0 +-#define MX7D_PAD_SD3_CMD__SD3_CMD 0x01D4 0x0444 0x0000 0x0 0x0 +-#define MX7D_PAD_SD3_CMD__NAND_ALE 0x01D4 0x0444 0x0000 0x1 0x0 +-#define MX7D_PAD_SD3_CMD__ECSPI4_MOSI 0x01D4 0x0444 0x055C 0x2 0x2 +-#define MX7D_PAD_SD3_CMD__SAI3_RX_BCLK 0x01D4 0x0444 0x06C4 0x3 0x2 +-#define MX7D_PAD_SD3_CMD__GPT3_CAPTURE1 0x01D4 0x0444 0x0000 0x4 0x0 +-#define MX7D_PAD_SD3_CMD__GPIO6_IO1 0x01D4 0x0444 0x0000 0x5 0x0 +-#define MX7D_PAD_SD3_DATA0__SD3_DATA0 0x01D8 0x0448 0x0000 0x0 0x0 +-#define MX7D_PAD_SD3_DATA0__NAND_DATA00 0x01D8 0x0448 0x0000 0x1 0x0 +-#define MX7D_PAD_SD3_DATA0__ECSPI4_SS0 0x01D8 0x0448 0x0560 0x2 0x2 +-#define MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0 0x01D8 0x0448 0x06C8 0x3 0x2 +-#define MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2 0x01D8 0x0448 0x0000 0x4 0x0 +-#define MX7D_PAD_SD3_DATA0__GPIO6_IO2 0x01D8 0x0448 0x0000 0x5 0x0 +-#define MX7D_PAD_SD3_DATA1__SD3_DATA1 0x01DC 0x044C 0x0000 0x0 0x0 +-#define MX7D_PAD_SD3_DATA1__NAND_DATA01 0x01DC 0x044C 0x0000 0x1 0x0 +-#define MX7D_PAD_SD3_DATA1__ECSPI4_SCLK 0x01DC 0x044C 0x0554 0x2 0x2 +-#define MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK 0x01DC 0x044C 0x06D0 0x3 0x2 +-#define MX7D_PAD_SD3_DATA1__GPT3_COMPARE1 0x01DC 0x044C 0x0000 0x4 0x0 +-#define MX7D_PAD_SD3_DATA1__GPIO6_IO3 0x01DC 0x044C 0x0000 0x5 0x0 +-#define MX7D_PAD_SD3_DATA2__SD3_DATA2 0x01E0 0x0450 0x0000 0x0 0x0 +-#define MX7D_PAD_SD3_DATA2__NAND_DATA02 0x01E0 0x0450 0x0000 0x1 0x0 +-#define MX7D_PAD_SD3_DATA2__I2C3_SDA 0x01E0 0x0450 0x05E8 0x2 0x3 +-#define MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC 0x01E0 0x0450 0x06D4 0x3 0x2 +-#define MX7D_PAD_SD3_DATA2__GPT3_COMPARE2 0x01E0 0x0450 0x0000 0x4 0x0 +-#define MX7D_PAD_SD3_DATA2__GPIO6_IO4 0x01E0 0x0450 0x0000 0x5 0x0 +-#define MX7D_PAD_SD3_DATA3__SD3_DATA3 0x01E4 0x0454 0x0000 0x0 0x0 +-#define MX7D_PAD_SD3_DATA3__NAND_DATA03 0x01E4 0x0454 0x0000 0x1 0x0 +-#define MX7D_PAD_SD3_DATA3__I2C3_SCL 0x01E4 0x0454 0x05E4 0x2 0x3 +-#define MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0 0x01E4 0x0454 0x0000 0x3 0x0 +-#define MX7D_PAD_SD3_DATA3__GPT3_COMPARE3 0x01E4 0x0454 0x0000 0x4 0x0 +-#define MX7D_PAD_SD3_DATA3__GPIO6_IO5 0x01E4 0x0454 0x0000 0x5 0x0 +-#define MX7D_PAD_SD3_DATA4__SD3_DATA4 0x01E8 0x0458 0x0000 0x0 0x0 +-#define MX7D_PAD_SD3_DATA4__NAND_DATA04 0x01E8 0x0458 0x0000 0x1 0x0 +-#define MX7D_PAD_SD3_DATA4__UART3_DCE_RX 0x01E8 0x0458 0x0704 0x3 0x4 +-#define MX7D_PAD_SD3_DATA4__UART3_DTE_TX 0x01E8 0x0458 0x0000 0x3 0x0 +-#define MX7D_PAD_SD3_DATA4__FLEXCAN2_RX 0x01E8 0x0458 0x04E0 0x4 0x2 +-#define MX7D_PAD_SD3_DATA4__GPIO6_IO6 0x01E8 0x0458 0x0000 0x5 0x0 +-#define MX7D_PAD_SD3_DATA5__SD3_DATA5 0x01EC 0x045C 0x0000 0x0 0x0 +-#define MX7D_PAD_SD3_DATA5__NAND_DATA05 0x01EC 0x045C 0x0000 0x1 0x0 +-#define MX7D_PAD_SD3_DATA5__UART3_DCE_TX 0x01EC 0x045C 0x0000 0x3 0x0 +-#define MX7D_PAD_SD3_DATA5__UART3_DTE_RX 0x01EC 0x045C 0x0704 0x3 0x5 +-#define MX7D_PAD_SD3_DATA5__FLEXCAN1_TX 0x01EC 0x045C 0x0000 0x4 0x0 +-#define MX7D_PAD_SD3_DATA5__GPIO6_IO7 0x01EC 0x045C 0x0000 0x5 0x0 +-#define MX7D_PAD_SD3_DATA6__SD3_DATA6 0x01F0 0x0460 0x0000 0x0 0x0 +-#define MX7D_PAD_SD3_DATA6__NAND_DATA06 0x01F0 0x0460 0x0000 0x1 0x0 +-#define MX7D_PAD_SD3_DATA6__SD3_WP 0x01F0 0x0460 0x073C 0x2 0x2 +-#define MX7D_PAD_SD3_DATA6__UART3_DCE_RTS 0x01F0 0x0460 0x0700 0x3 0x4 +-#define MX7D_PAD_SD3_DATA6__UART3_DTE_CTS 0x01F0 0x0460 0x0000 0x3 0x0 +-#define MX7D_PAD_SD3_DATA6__FLEXCAN2_TX 0x01F0 0x0460 0x0000 0x4 0x0 +-#define MX7D_PAD_SD3_DATA6__GPIO6_IO8 0x01F0 0x0460 0x0000 0x5 0x0 +-#define MX7D_PAD_SD3_DATA7__SD3_DATA7 0x01F4 0x0464 0x0000 0x0 0x0 +-#define MX7D_PAD_SD3_DATA7__NAND_DATA07 0x01F4 0x0464 0x0000 0x1 0x0 +-#define MX7D_PAD_SD3_DATA7__SD3_CD_B 0x01F4 0x0464 0x0738 0x2 0x2 +-#define MX7D_PAD_SD3_DATA7__UART3_DCE_CTS 0x01F4 0x0464 0x0000 0x3 0x0 +-#define MX7D_PAD_SD3_DATA7__UART3_DTE_RTS 0x01F4 0x0464 0x0700 0x3 0x5 +-#define MX7D_PAD_SD3_DATA7__FLEXCAN1_RX 0x01F4 0x0464 0x04DC 0x4 0x2 +-#define MX7D_PAD_SD3_DATA7__GPIO6_IO9 0x01F4 0x0464 0x0000 0x5 0x0 +-#define MX7D_PAD_SD3_STROBE__SD3_STROBE 0x01F8 0x0468 0x0000 0x0 0x0 +-#define MX7D_PAD_SD3_STROBE__NAND_RE_B 0x01F8 0x0468 0x0000 0x1 0x0 +-#define MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x01F8 0x0468 0x0000 0x5 0x0 +-#define MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x01FC 0x046C 0x0000 0x0 0x0 +-#define MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x01FC 0x046C 0x0000 0x1 0x0 +-#define MX7D_PAD_SD3_RESET_B__SD3_RESET 0x01FC 0x046C 0x0000 0x2 0x0 +-#define MX7D_PAD_SD3_RESET_B__SAI3_MCLK 0x01FC 0x046C 0x0000 0x3 0x0 +-#define MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x01FC 0x046C 0x0000 0x5 0x0 +-#define MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x0200 0x0470 0x06A0 0x0 0x0 +-#define MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x0200 0x0470 0x0000 0x1 0x0 +-#define MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x0200 0x0470 0x0714 0x2 0x2 +-#define MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x0200 0x0470 0x0000 0x2 0x0 +-#define MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x0200 0x0470 0x04DC 0x3 0x3 +-#define MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD 0x0200 0x0470 0x06E4 0x4 0x1 +-#define MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x0200 0x0470 0x0000 0x5 0x0 +-#define MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET 0x0200 0x0470 0x0000 0x7 0x0 +-#define MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x0204 0x0474 0x06A8 0x0 0x0 +-#define MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x0204 0x0474 0x0000 0x1 0x0 +-#define MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x0204 0x0474 0x0000 0x2 0x0 +-#define MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x0204 0x0474 0x0714 0x2 0x3 +-#define MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x0204 0x0474 0x0000 0x3 0x0 +-#define MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK 0x0204 0x0474 0x0000 0x4 0x0 +-#define MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x0204 0x0474 0x0000 0x5 0x0 +-#define MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET 0x0204 0x0474 0x0000 0x7 0x0 +-#define MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x0208 0x0478 0x06AC 0x0 0x0 +-#define MX7D_PAD_SAI1_TX_SYNC__NAND_DQS 0x0208 0x0478 0x0000 0x1 0x0 +-#define MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x0208 0x0478 0x0000 0x2 0x0 +-#define MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS 0x0208 0x0478 0x0710 0x2 0x2 +-#define MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x0208 0x0478 0x04E0 0x3 0x3 +-#define MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B 0x0208 0x0478 0x0000 0x4 0x0 +-#define MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x0208 0x0478 0x0000 0x5 0x0 +-#define MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT 0x0208 0x0478 0x0000 0x7 0x0 +-#define MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x020C 0x047C 0x0000 0x0 0x0 +-#define MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x020C 0x047C 0x0000 0x1 0x0 +-#define MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x020C 0x047C 0x0710 0x2 0x3 +-#define MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS 0x020C 0x047C 0x0000 0x2 0x0 +-#define MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x020C 0x047C 0x0000 0x3 0x0 +-#define MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN 0x020C 0x047C 0x0000 0x4 0x0 +-#define MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x020C 0x047C 0x0000 0x5 0x0 +-#define MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET 0x020C 0x047C 0x0000 0x7 0x0 +-#define MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC 0x0210 0x0480 0x06A4 0x0 0x0 +-#define MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B 0x0210 0x0480 0x0000 0x1 0x0 +-#define MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x0210 0x0480 0x06B8 0x2 0x1 +-#define MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x0210 0x0480 0x05EC 0x3 0x3 +-#define MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD 0x0210 0x0480 0x06E0 0x4 0x1 +-#define MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x0210 0x0480 0x0000 0x5 0x0 +-#define MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT 0x0210 0x0480 0x0000 0x6 0x0 +-#define MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0 0x0210 0x0480 0x0000 0x7 0x0 +-#define MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x0214 0x0484 0x069C 0x0 0x0 +-#define MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B 0x0214 0x0484 0x0000 0x1 0x0 +-#define MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK 0x0214 0x0484 0x06B0 0x2 0x1 +-#define MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x0214 0x0484 0x05F0 0x3 0x3 +-#define MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA 0x0214 0x0484 0x05CC 0x4 0x1 +-#define MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x0214 0x0484 0x0000 0x5 0x0 +-#define MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT 0x0214 0x0484 0x0000 0x6 0x0 +-#define MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1 0x0214 0x0484 0x0000 0x7 0x0 +-#define MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x0218 0x0488 0x0000 0x0 0x0 +-#define MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x0218 0x0488 0x0000 0x1 0x0 +-#define MX7D_PAD_SAI1_MCLK__SAI2_MCLK 0x0218 0x0488 0x0000 0x2 0x0 +-#define MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY 0x0218 0x0488 0x04F4 0x3 0x3 +-#define MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB 0x0218 0x0488 0x05D0 0x4 0x1 +-#define MX7D_PAD_SAI1_MCLK__GPIO6_IO18 0x0218 0x0488 0x0000 0x5 0x0 +-#define MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK 0x0218 0x0488 0x0000 0x7 0x0 +-#define MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x021C 0x048C 0x06C0 0x0 0x1 +-#define MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x021C 0x048C 0x0548 0x1 0x1 +-#define MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x021C 0x048C 0x070C 0x2 0x4 +-#define MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX 0x021C 0x048C 0x0000 0x2 0x0 +-#define MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS 0x021C 0x048C 0x0000 0x3 0x0 +-#define MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x021C 0x048C 0x06F0 0x3 0x0 +-#define MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4 0x021C 0x048C 0x05BC 0x4 0x1 +-#define MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x021C 0x048C 0x0000 0x5 0x0 +-#define MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x0220 0x0490 0x06BC 0x0 0x1 +-#define MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x0220 0x0490 0x054C 0x1 0x1 +-#define MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x0220 0x0490 0x0000 0x2 0x0 +-#define MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX 0x0220 0x0490 0x070C 0x2 0x5 +-#define MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS 0x0220 0x0490 0x06F0 0x3 0x1 +-#define MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x0220 0x0490 0x0000 0x3 0x0 +-#define MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5 0x0220 0x0490 0x05C0 0x4 0x1 +-#define MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x0220 0x0490 0x0000 0x5 0x0 +-#define MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x0224 0x0494 0x06B4 0x0 0x1 +-#define MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x0224 0x0494 0x0544 0x1 0x1 +-#define MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x0224 0x0494 0x0000 0x2 0x0 +-#define MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS 0x0224 0x0494 0x0708 0x2 0x4 +-#define MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS 0x0224 0x0494 0x0000 0x3 0x0 +-#define MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x0224 0x0494 0x06F8 0x3 0x2 +-#define MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6 0x0224 0x0494 0x05C4 0x4 0x1 +-#define MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x0224 0x0494 0x0000 0x5 0x0 +-#define MX7D_PAD_SAI2_RX_DATA__KPP_COL7 0x0224 0x0494 0x0610 0x6 0x1 +-#define MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x0228 0x0498 0x0000 0x0 0x0 +-#define MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 0x0228 0x0498 0x0550 0x1 0x1 +-#define MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x0228 0x0498 0x0708 0x2 0x5 +-#define MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS 0x0228 0x0498 0x0000 0x2 0x0 +-#define MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS 0x0228 0x0498 0x06F8 0x3 0x3 +-#define MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x0228 0x0498 0x0000 0x3 0x0 +-#define MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7 0x0228 0x0498 0x05C8 0x4 0x1 +-#define MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x0228 0x0498 0x0000 0x5 0x0 +-#define MX7D_PAD_SAI2_TX_DATA__KPP_ROW7 0x0228 0x0498 0x0630 0x6 0x1 +-#define MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x022C 0x049C 0x0000 0x0 0x0 +-#define MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT 0x022C 0x049C 0x0000 0x1 0x0 +-#define MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x022C 0x049C 0x05E4 0x2 0x4 +-#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS 0x022C 0x049C 0x0000 0x3 0x0 +-#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS 0x022C 0x049C 0x06F0 0x3 0x2 +-#define MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0 0x022C 0x049C 0x0000 0x4 0x0 +-#define MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x022C 0x049C 0x0000 0x5 0x0 +-#define MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3 0x022C 0x049C 0x0620 0x6 0x1 +-#define MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x0230 0x04A0 0x0000 0x0 0x0 +-#define MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT 0x0230 0x04A0 0x0000 0x1 0x0 +-#define MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x0230 0x04A0 0x05E8 0x2 0x4 +-#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS 0x0230 0x04A0 0x06F0 0x3 0x3 +-#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS 0x0230 0x04A0 0x0000 0x3 0x0 +-#define MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1 0x0230 0x04A0 0x0000 0x4 0x0 +-#define MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0230 0x04A0 0x0000 0x5 0x0 +-#define MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3 0x0230 0x04A0 0x0600 0x6 0x1 +-#define MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x0234 0x04A4 0x0000 0x0 0x0 +-#define MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x0234 0x04A4 0x04DC 0x1 0x4 +-#define MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK 0x0234 0x04A4 0x0534 0x2 0x1 +-#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX 0x0234 0x04A4 0x06F4 0x3 0x2 +-#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX 0x0234 0x04A4 0x0000 0x3 0x0 +-#define MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4 0x0234 0x04A4 0x0000 0x4 0x0 +-#define MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x0234 0x04A4 0x0000 0x5 0x0 +-#define MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2 0x0234 0x04A4 0x061C 0x6 0x1 +-#define MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x0238 0x04A8 0x0000 0x0 0x0 +-#define MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x0238 0x04A8 0x0000 0x1 0x0 +-#define MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI 0x0238 0x04A8 0x053C 0x2 0x1 +-#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX 0x0238 0x04A8 0x0000 0x3 0x0 +-#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX 0x0238 0x04A8 0x06F4 0x3 0x3 +-#define MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5 0x0238 0x04A8 0x0000 0x4 0x0 +-#define MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x0238 0x04A8 0x0000 0x5 0x0 +-#define MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2 0x0238 0x04A8 0x05FC 0x6 0x1 +-#define MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x023C 0x04AC 0x0000 0x0 0x0 +-#define MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1 0x023C 0x04AC 0x0000 0x2 0x0 +-#define MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6 0x023C 0x04AC 0x0000 0x4 0x0 +-#define MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x023C 0x04AC 0x0000 0x5 0x0 +-#define MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1 0x023C 0x04AC 0x0618 0x6 0x1 +-#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x0240 0x04B0 0x0000 0x0 0x0 +-#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x0240 0x04B0 0x0000 0x1 0x0 +-#define MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2 0x0240 0x04B0 0x0000 0x2 0x0 +-#define MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7 0x0240 0x04B0 0x0000 0x4 0x0 +-#define MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0240 0x04B0 0x0000 0x5 0x0 +-#define MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1 0x0240 0x04B0 0x0000 0x6 0x0 +-#define MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x0244 0x04B4 0x0000 0x0 0x0 +-#define MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT 0x0244 0x04B4 0x0000 0x1 0x0 +-#define MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3 0x0244 0x04B4 0x0000 0x2 0x0 +-#define MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8 0x0244 0x04B4 0x0000 0x4 0x0 +-#define MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0244 0x04B4 0x0000 0x5 0x0 +-#define MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0 0x0244 0x04B4 0x0614 0x6 0x1 +-#define MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x0248 0x04B8 0x0000 0x0 0x0 +-#define MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT 0x0248 0x04B8 0x0000 0x1 0x0 +-#define MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY 0x0248 0x04B8 0x0000 0x2 0x0 +-#define MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9 0x0248 0x04B8 0x0000 0x4 0x0 +-#define MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0248 0x04B8 0x0000 0x5 0x0 +-#define MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0 0x0248 0x04B8 0x05F4 0x6 0x1 +-#define MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x024C 0x04BC 0x0000 0x0 0x0 +-#define MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX 0x024C 0x04BC 0x04E0 0x1 0x4 +-#define MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO 0x024C 0x04BC 0x0538 0x2 0x1 +-#define MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x024C 0x04BC 0x05EC 0x3 0x4 +-#define MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED 0x024C 0x04BC 0x0000 0x4 0x0 +-#define MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x024C 0x04BC 0x0000 0x5 0x0 +-#define MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x0250 0x04C0 0x0000 0x0 0x0 +-#define MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX 0x0250 0x04C0 0x0000 0x1 0x0 +-#define MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0 0x0250 0x04C0 0x0540 0x2 0x1 +-#define MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x0250 0x04C0 0x05F0 0x3 0x4 +-#define MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ 0x0250 0x04C0 0x0000 0x4 0x0 +-#define MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x0250 0x04C0 0x0000 0x5 0x0 +-#define MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS 0x0250 0x04C0 0x0000 0x7 0x0 +-#define MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x0254 0x04C4 0x0000 0x0 0x0 +-#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC 0x0254 0x04C4 0x06A4 0x2 0x1 +-#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 0x0254 0x04C4 0x0000 0x3 0x0 +-#define MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 0x0254 0x04C4 0x0000 0x4 0x0 +-#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0254 0x04C4 0x0000 0x5 0x0 +-#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x0258 0x04C8 0x0000 0x0 0x0 +-#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER 0x0258 0x04C8 0x0000 0x1 0x0 +-#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK 0x0258 0x04C8 0x069C 0x2 0x1 +-#define MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 0x0258 0x04C8 0x0000 0x3 0x0 +-#define MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 0x0258 0x04C8 0x0000 0x4 0x0 +-#define MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x0258 0x04C8 0x0000 0x5 0x0 +-#define MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x025C 0x04CC 0x0000 0x0 0x0 +-#define MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 0x025C 0x04CC 0x0564 0x1 0x2 +-#define MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x025C 0x04CC 0x06A0 0x2 0x1 +-#define MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3 0x025C 0x04CC 0x0000 0x3 0x0 +-#define MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ 0x025C 0x04CC 0x057C 0x4 0x1 +-#define MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x025C 0x04CC 0x0000 0x5 0x0 +-#define MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1 0x025C 0x04CC 0x04E4 0x6 0x2 +-#define MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0 0x025C 0x04CC 0x0000 0x7 0x0 +-#define MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x0260 0x04D0 0x056C 0x0 0x0 +-#define MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B 0x0260 0x04D0 0x0000 0x1 0x0 +-#define MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x0260 0x04D0 0x06A8 0x2 0x1 +-#define MX7D_PAD_ENET1_RX_CLK__GPT2_CLK 0x0260 0x04D0 0x0000 0x3 0x0 +-#define MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE 0x0260 0x04D0 0x0000 0x4 0x0 +-#define MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x0260 0x04D0 0x0000 0x5 0x0 +-#define MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2 0x0260 0x04D0 0x04E8 0x6 0x2 +-#define MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1 0x0260 0x04D0 0x0000 0x7 0x0 +-#define MX7D_PAD_ENET1_CRS__ENET1_CRS 0x0264 0x04D4 0x0000 0x0 0x0 +-#define MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB 0x0264 0x04D4 0x0000 0x1 0x0 +-#define MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x0264 0x04D4 0x06AC 0x2 0x1 +-#define MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1 0x0264 0x04D4 0x0000 0x3 0x0 +-#define MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0 0x0264 0x04D4 0x0000 0x4 0x0 +-#define MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x0264 0x04D4 0x0000 0x5 0x0 +-#define MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3 0x0264 0x04D4 0x04EC 0x6 0x2 +-#define MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2 0x0264 0x04D4 0x0000 0x7 0x0 +-#define MX7D_PAD_ENET1_COL__ENET1_COL 0x0268 0x04D8 0x0000 0x0 0x0 +-#define MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY 0x0268 0x04D8 0x0000 0x1 0x0 +-#define MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x0268 0x04D8 0x0000 0x2 0x0 +-#define MX7D_PAD_ENET1_COL__GPT2_CAPTURE2 0x0268 0x04D8 0x0000 0x3 0x0 +-#define MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1 0x0268 0x04D8 0x0000 0x4 0x0 +-#define MX7D_PAD_ENET1_COL__GPIO7_IO15 0x0268 0x04D8 0x0000 0x5 0x0 +-#define MX7D_PAD_ENET1_COL__CCM_EXT_CLK4 0x0268 0x04D8 0x04F0 0x6 0x2 +-#define MX7D_PAD_ENET1_COL__CSU_INT_DEB 0x0268 0x04D8 0x0000 0x7 0x0 +- +-#endif /* __DTS_IMX7D_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-remarkable2.dts b/scripts/dtc/include-prefixes/arm/imx7d-remarkable2.dts +deleted file mode 100644 +index 89cbf13097a4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-remarkable2.dts ++++ /dev/null +@@ -1,237 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2015 Freescale Semiconductor, Inc. +- * Copyright (C) 2019 reMarkable AS - http://www.remarkable.com/ +- * +- */ +- +-/dts-v1/; +- +-#include "imx7d.dtsi" +- +-/ { +- model = "reMarkable 2.0"; +- compatible = "remarkable,imx7d-remarkable2", "fsl,imx7d"; +- +- chosen { +- stdout-path = &uart6; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; +- }; +- +- reg_brcm: regulator-brcm { +- compatible = "regulator-fixed"; +- regulator-name = "brcm_reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_brcm_reg>; +- gpio = <&gpio6 13 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- startup-delay-us = <150>; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wifi>; +- reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; +- clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>, +- <&clks IMX7D_CLKO2_ROOT_DIV>; +- assigned-clock-parents = <&clks IMX7D_CKIL>; +- assigned-clock-rates = <0>, <32768>; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +- status = "okay"; +-}; +- +-&uart6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart6>; +- assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +- status = "okay"; +-}; +- +-&usbotg2 { +- srp-disable; +- hnp-disable; +- status = "okay"; +-}; +- +-&usdhc2 { +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>; +- mmc-pwrseq = <&wifi_pwrseq>; +- vmmc-supply = <®_brcm>; +- bus-width = <4>; +- non-removable; +- keep-power-in-suspend; +- cap-power-off-card; +- status = "okay"; +- +- brcmf: bcrmf@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- pinctrl-3 = <&pinctrl_usdhc3>; +- assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; +- assigned-clock-rates = <400000000>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl_brcm_reg: brcmreggrp { +- fsl,pins = < +- /* WIFI_PWR_EN */ +- MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x14 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 +- MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 +- >; +- }; +- +- pinctrl_uart6: uart6grp { +- fsl,pins = < +- MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79 +- MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX7D_PAD_SD2_CMD__SD2_CMD 0x59 +- MX7D_PAD_SD2_CLK__SD2_CLK 0x19 +- MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 +- MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 +- MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 +- MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { +- fsl,pins = < +- MX7D_PAD_SD2_CMD__SD2_CMD 0x5a +- MX7D_PAD_SD2_CLK__SD2_CLK 0x1a +- MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a +- MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a +- MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a +- MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { +- fsl,pins = < +- MX7D_PAD_SD2_CMD__SD2_CMD 0x5b +- MX7D_PAD_SD2_CLK__SD2_CLK 0x1b +- MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b +- MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b +- MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b +- MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x59 +- MX7D_PAD_SD3_CLK__SD3_CLK 0x19 +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 +- MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x5a +- MX7D_PAD_SD3_CLK__SD3_CLK 0x1a +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a +- MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x5b +- MX7D_PAD_SD3_CLK__SD3_CLK 0x1b +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b +- MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY 0x74 +- >; +- }; +- +- pinctrl_wifi: wifigrp { +- fsl,pins = < +- /* WiFi Reg On */ +- MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x00000014 +- /* WiFi Sleep 32k */ +- MX7D_PAD_SD1_WP__CCM_CLKO2 0x00000014 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-sbc-imx7.dts b/scripts/dtc/include-prefixes/arm/imx7d-sbc-imx7.dts +deleted file mode 100644 +index f8a868552707..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-sbc-imx7.dts ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* +- * Support for CompuLab SBC-iMX7 Single Board Computer +- * +- * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ +- * Author: Ilya Ledvich +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- */ +- +-#include "imx7d-cl-som-imx7.dts" +- +-/ { +- model = "CompuLab SBC-iMX7"; +- compatible = "compulab,sbc-imx7", "compulab,cl-som-imx7", "fsl,imx7d"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; +- wakeup-source; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX7D_PAD_SD1_CMD__SD1_CMD 0x59 +- MX7D_PAD_SD1_CLK__SD1_CLK 0x19 +- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 +- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 +- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 +- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 +- MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ +- MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-sdb-reva.dts b/scripts/dtc/include-prefixes/arm/imx7d-sdb-reva.dts +deleted file mode 100644 +index cabdaa6dc518..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-sdb-reva.dts ++++ /dev/null +@@ -1,43 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Copyright (C) 2015 Freescale Semiconductor, Inc. +- +-/dts-v1/; +- +-#include "imx7d-sdb.dts" +- +-/ { +- model = "Freescale i.MX7 SabreSD RevA Board"; +- compatible = "fsl,imx7d-sdb-reva", "fsl,imx7d"; +- +- reg_usb_otg2_vbus: regulator-usb-otg2-vbus { +- pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg_reva>; +- gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&fec2 { +- /delete-property/phy-supply; +-}; +- +-&iomuxc { +- imx7d-sdb { +- pinctrl_tsc2046_pendown: tsc2046_pendown { +- fsl,pins = < +- MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59 +- >; +- }; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ +- >; +- }; +- +- pinctrl_usb_otg2_vbus_reg_reva: usbotg2vbusregrevagrp { +- fsl,pins = < +- MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-sdb-sht11.dts b/scripts/dtc/include-prefixes/arm/imx7d-sdb-sht11.dts +deleted file mode 100644 +index 996555596d40..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-sdb-sht11.dts ++++ /dev/null +@@ -1,36 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Copyright (C) 2015 Freescale Semiconductor, Inc. +- +-#include "imx7d-sdb.dts" +- +-/ { +- sensor { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sensor>; +- compatible = "sensirion,sht15"; +- clk-gpios = <&gpio4 12 0>; +- data-gpios = <&gpio4 13 0>; +- vcc-supply = <®_sht15>; +- }; +- +- reg_sht15: regulator-sht15 { +- compatible = "regulator-fixed"; +- regulator-name = "reg_sht15"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&i2c3 { +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_sensor: sensorgrp { +- fsl,pins = < +- MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x4000007f +- MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x4000007f +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-sdb.dts b/scripts/dtc/include-prefixes/arm/imx7d-sdb.dts +deleted file mode 100644 +index 4a0d83784d7d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-sdb.dts ++++ /dev/null +@@ -1,867 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Copyright (C) 2015 Freescale Semiconductor, Inc. +- +-/dts-v1/; +- +-#include "imx7d.dtsi" +- +-/ { +- model = "Freescale i.MX7 SabreSD Board"; +- compatible = "fsl,imx7d-sdb", "fsl,imx7d"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x80000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- volume-down { +- label = "Volume Down"; +- gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- spi4 { +- compatible = "spi-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi4>; +- gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; +- gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; +- num-chipselects = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- extended_io: gpio-expander@0 { +- compatible = "fairchild,74hc595"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0>; +- registers-number = <1>; +- spi-max-frequency = <100000>; +- }; +- }; +- +- reg_usb_otg1_vbus: regulator-usb-otg1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_otg2_vbus: regulator-usb-otg2-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg2_vbus"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_vref_1v8: regulator-vref-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "vref-1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- reg_brcm: regulator-brcm { +- compatible = "regulator-fixed"; +- gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-name = "brcm_reg"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_brcm_reg>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <200000>; +- }; +- +- reg_lcd_3v3: regulator-lcd-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "lcd-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&extended_io 7 GPIO_ACTIVE_LOW>; +- }; +- +- reg_can2_3v3: regulator-can2-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "can2-3v3"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2_reg>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; +- }; +- +- reg_fec2_3v3: regulator-fec2-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "fec2-3v3"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet2_reg>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 5000000 0>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- status = "okay"; +- }; +- +- panel { +- compatible = "innolux,at043tn24"; +- backlight = <&backlight>; +- power-supply = <®_lcd_3v3>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +- +- sound { +- compatible = "fsl,imx7d-evk-wm8960", +- "fsl,imx-audio-wm8960"; +- model = "wm8960-audio"; +- audio-cpu = <&sai1>; +- audio-codec = <&codec>; +- hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>; +- audio-routing = +- "Headphone Jack", "HP_L", +- "Headphone Jack", "HP_R", +- "Ext Spk", "SPK_LP", +- "Ext Spk", "SPK_LN", +- "Ext Spk", "SPK_RP", +- "Ext Spk", "SPK_RN", +- "LINPUT1", "AMIC", +- "AMIC", "MICB"; +- }; +- +- sound-hdmi { +- compatible = "fsl,imx-audio-sii902x"; +- model = "sii902x-audio"; +- audio-cpu = <&sai3>; +- hdmi-out; +- }; +-}; +- +-&adc1 { +- vref-supply = <®_vref_1v8>; +- status = "okay"; +-}; +- +-&adc2 { +- vref-supply = <®_vref_1v8>; +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <&sw1a_reg>; +-}; +- +-&cpu1 { +- cpu-supply = <&sw1a_reg>; +-}; +- +-&ecspi3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi3>; +- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- tsc2046@0 { +- compatible = "ti,tsc2046"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- pinctrl-names ="default"; +- pinctrl-0 = <&pinctrl_tsc2046_pendown>; +- interrupt-parent = <&gpio2>; +- interrupts = <29 0>; +- pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; +- ti,x-min = /bits/ 16 <0>; +- ti,x-max = /bits/ 16 <0>; +- ti,y-min = /bits/ 16 <0>; +- ti,y-max = /bits/ 16 <0>; +- ti,pressure-max = /bits/ 16 <0>; +- ti,x-plate-ohms = /bits/ 16 <400>; +- wakeup-source; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, +- <&clks IMX7D_ENET1_TIME_ROOT_CLK>; +- assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; +- assigned-clock-rates = <0>, <100000000>; +- phy-mode = "rgmii"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- }; +- }; +-}; +- +-&fec2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet2>; +- assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, +- <&clks IMX7D_ENET2_TIME_ROOT_CLK>; +- assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; +- assigned-clock-rates = <0>, <100000000>; +- phy-mode = "rgmii"; +- phy-handle = <ðphy1>; +- phy-supply = <®_fec2_3v3>; +- fsl,magic-packet; +- status = "okay"; +-}; +- +-&flexcan2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- xceiver-supply = <®_can2_3v3>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic: pfuze3000@8 { +- compatible = "fsl,pfuze3000"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1a { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1475000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- /* use sw1c_reg to align with pfuze100/pfuze200 */ +- sw1c_reg: sw1b { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1475000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1650000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen2_reg: vldo2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vccsd { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen4_reg: v33 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vldo3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vldo4 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- mpl3115@60 { +- compatible = "fsl,mpl3115"; +- reg = <0x60>; +- }; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +- +- codec: wm8960@1a { +- compatible = "wlf,wm8960"; +- reg = <0x1a>; +- clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; +- clock-names = "mclk"; +- wlf,shared-lrclk; +- wlf,hp-cfg = <2 2 3>; +- wlf,gpio-cfg = <1 3>; +- assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, +- <&clks IMX7D_PLL_AUDIO_POST_DIV>, +- <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; +- assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; +- assigned-clock-rates = <0>, <884736000>, <12288000>; +- }; +-}; +- +-&lcdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcdif>; +- status = "okay"; +- +- port { +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +-}; +- +-&pcie { +- reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-®_1p0d { +- vin-supply = <&sw2_reg>; +-}; +- +-®_1p2 { +- vin-supply = <&sw2_reg>; +-}; +- +-&sai1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai1>; +- assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, +- <&clks IMX7D_PLL_AUDIO_POST_DIV>, +- <&clks IMX7D_SAI1_ROOT_CLK>; +- assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; +- assigned-clock-rates = <0>, <884736000>, <36864000>; +- status = "okay"; +-}; +- +-&sai3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>; +- assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, +- <&clks IMX7D_PLL_AUDIO_POST_DIV>, +- <&clks IMX7D_SAI3_ROOT_CLK>; +- assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; +- assigned-clock-rates = <0>, <884736000>, <36864000>; +- status = "okay"; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; +- status = "okay"; +-}; +- +-&uart6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart6>; +- assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbotg1 { +- vbus-supply = <®_usb_otg1_vbus>; +- status = "okay"; +-}; +- +-&usbotg2 { +- vbus-supply = <®_usb_otg2_vbus>; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; +- wakeup-source; +- keep-power-in-suspend; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>; +- wakeup-source; +- keep-power-in-suspend; +- non-removable; +- vmmc-supply = <®_brcm>; +- fsl,tuning-step = <2>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; +- assigned-clock-rates = <400000000>; +- bus-width = <8>; +- fsl,tuning-step = <2>; +- non-removable; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- imx7d-sdb { +- pinctrl_brcm_reg: brcmreggrp { +- fsl,pins = < +- MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14 +- >; +- }; +- +- pinctrl_ecspi3: ecspi3grp { +- fsl,pins = < +- MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 +- MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 +- MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 +- MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 +- >; +- }; +- +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 +- MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 +- MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 +- MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 +- MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 +- MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 +- MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 +- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 +- MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 +- MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 +- MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 +- MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 +- MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 +- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 +- >; +- }; +- +- pinctrl_enet2: enet2grp { +- fsl,pins = < +- MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 +- MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 +- MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 +- MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 +- MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 +- MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 +- MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 +- MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 +- MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 +- MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 +- MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 +- MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 +- >; +- }; +- +- pinctrl_enet2_reg: enet2reggrp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 +- MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 +- >; +- }; +- +- pinctrl_flexcan2_reg: flexcan2reggrp { +- fsl,pins = < +- MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */ +- >; +- }; +- +- pinctrl_gpio_keys: gpio_keysgrp { +- fsl,pins = < +- MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 +- MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 +- >; +- }; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ +- MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */ +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f +- MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f +- MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f +- MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f +- MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f +- >; +- }; +- +- pinctrl_lcdif: lcdifgrp { +- fsl,pins = < +- MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 +- MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 +- MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 +- MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 +- MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 +- MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 +- MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 +- MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 +- MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 +- MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 +- MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 +- MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 +- MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 +- MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 +- MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 +- MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 +- MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 +- MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 +- MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 +- MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 +- MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 +- MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 +- MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 +- MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 +- MX7D_PAD_LCD_CLK__LCD_CLK 0x79 +- MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 +- MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 +- MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 +- MX7D_PAD_LCD_RESET__LCD_RESET 0x79 +- >; +- }; +- +- pinctrl_sai1: sai1grp { +- fsl,pins = < +- MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f +- MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f +- MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f +- MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 +- MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f +- >; +- }; +- +- pinctrl_sai2: sai2grp { +- fsl,pins = < +- MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f +- MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f +- MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 +- MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f +- >; +- }; +- +- pinctrl_sai3: sai3grp { +- fsl,pins = < +- MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f +- MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f +- MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 +- >; +- }; +- +- pinctrl_spi4: spi4grp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 +- MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 +- MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 +- >; +- }; +- +- pinctrl_tsc2046_pendown: tsc2046_pendown { +- fsl,pins = < +- MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 +- MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 +- >; +- }; +- +- pinctrl_uart5: uart5grp { +- fsl,pins = < +- MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 +- MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 +- MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 +- MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 +- >; +- }; +- +- pinctrl_uart6: uart6grp { +- fsl,pins = < +- MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 +- MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 +- MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 +- MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX7D_PAD_SD1_CMD__SD1_CMD 0x59 +- MX7D_PAD_SD1_CLK__SD1_CLK 0x19 +- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 +- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 +- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 +- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 +- MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ +- MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ +- MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX7D_PAD_SD2_CMD__SD2_CMD 0x59 +- MX7D_PAD_SD2_CLK__SD2_CLK 0x19 +- MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 +- MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 +- MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 +- MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { +- fsl,pins = < +- MX7D_PAD_SD2_CMD__SD2_CMD 0x5a +- MX7D_PAD_SD2_CLK__SD2_CLK 0x1a +- MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a +- MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a +- MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a +- MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { +- fsl,pins = < +- MX7D_PAD_SD2_CMD__SD2_CMD 0x5b +- MX7D_PAD_SD2_CLK__SD2_CLK 0x1b +- MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b +- MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b +- MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b +- MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b +- >; +- }; +- +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x59 +- MX7D_PAD_SD3_CLK__SD3_CLK 0x19 +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 +- MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x5a +- MX7D_PAD_SD3_CLK__SD3_CLK 0x1a +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a +- MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x5b +- MX7D_PAD_SD3_CLK__SD3_CLK 0x1b +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b +- MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b +- >; +- }; +- }; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&iomuxc_lpsr { +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 +- >; +- }; +- +- pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 +- >; +- }; +- +- pinctrl_sai3_mclk: sai3grp_mclk { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-tqma7.dtsi b/scripts/dtc/include-prefixes/arm/imx7d-tqma7.dtsi +deleted file mode 100644 +index 598aed1ffd99..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-tqma7.dtsi ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Device Tree Include file for TQ Systems TQMa7D board with NXP i.MX7Dual SoC. +- * +- * Copyright (C) 2016 TQ Systems GmbH +- * Author: Markus Niebel +- * Copyright (C) 2019 Bruno Thomsen +- */ +- +-#include "imx7d.dtsi" +-#include "imx7-tqma7.dtsi" +- +-&cpu1 { +- cpu-supply = <&sw1a_reg>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-zii-rmu2.dts b/scripts/dtc/include-prefixes/arm/imx7d-zii-rmu2.dts +deleted file mode 100644 +index 1065941807e8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-zii-rmu2.dts ++++ /dev/null +@@ -1,357 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device tree file for ZII's RMU2 board +- * +- * RMU - Remote Modem Unit +- * +- * Copyright (C) 2019 Zodiac Inflight Innovations +- */ +- +-/dts-v1/; +-#include +-#include "imx7d.dtsi" +- +-/ { +- model = "ZII RMU2 Board"; +- compatible = "zii,imx7d-rmu2", "fsl,imx7d"; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pinctrl_leds_debug>; +- pinctrl-names = "default"; +- +- debug { +- label = "zii:green:debug1"; +- gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&sw1a_reg>; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, +- <&clks IMX7D_ENET1_TIME_ROOT_CLK>; +- assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; +- assigned-clock-rates = <0>, <100000000>; +- phy-mode = "rgmii-id"; +- phy-handle = <&fec1_phy>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- fec1_phy: ethernet-phy@0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1_phy_reset>, +- <&pinctrl_enet1_phy_interrupt>; +- reg = <0>; +- interrupt-parent = <&gpio1>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic@8 { +- compatible = "fsl,pfuze3000"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1a { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1b { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1475000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1650000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen2_reg: vldo2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- regulator-always-on; +- }; +- +- vgen3_reg: vccsd { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen4_reg: v33 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vldo3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vldo4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c04"; +- reg = <0x50>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c04"; +- reg = <0x52>; +- }; +-}; +- +-&snvs_rtc { +- status = "disabled"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; +- status = "okay"; +- +- rave-sp { +- compatible = "zii,rave-sp-rdu2"; +- current-speed = <1000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- watchdog { +- compatible = "zii,rave-sp-watchdog"; +- }; +- +- eeprom@a3 { +- compatible = "zii,rave-sp-eeprom"; +- reg = <0xa3 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- zii,eeprom-name = "main-eeprom"; +- }; +- }; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- bus-width = <4>; +- no-1-8-v; +- no-sdio; +- keep-power-in-suspend; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- no-sdio; +- no-sd; +- keep-power-in-suspend; +- status = "okay"; +-}; +- +-&wdog1 { +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 +- MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 +- MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 +- MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59 +- >; +- }; +- +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 +- MX7D_PAD_SD2_WP__ENET1_MDC 0x3 +- MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 +- MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 +- MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 +- MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 +- MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 +- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 +- MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 +- MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 +- MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 +- MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 +- MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 +- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 +- >; +- }; +- +- pinctrl_enet1_phy_reset: enet1phyresetgrp { +- fsl,pins = < +- MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 +- +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f +- MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f +- >; +- }; +- +- pinctrl_leds_debug: ledsgrp { +- fsl,pins = < +- MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59 +- >; +- }; +- +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 +- MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79 +- MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX7D_PAD_SD1_CMD__SD1_CMD 0x59 +- MX7D_PAD_SD1_CLK__SD1_CLK 0x19 +- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 +- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 +- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 +- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x59 +- MX7D_PAD_SD3_CLK__SD3_CLK 0x19 +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 +- MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59 +- >; +- }; +-}; +- +-&iomuxc_lpsr { +- pinctrl_enet1_phy_interrupt: enet1phyinterruptgrp { +- fsl,phy = < +- MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x08 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d-zii-rpu2.dts b/scripts/dtc/include-prefixes/arm/imx7d-zii-rpu2.dts +deleted file mode 100644 +index 893bd30aa2a3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d-zii-rpu2.dts ++++ /dev/null +@@ -1,923 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device tree file for ZII's RPU2 board +- * +- * RPU - Remote Peripheral Unit +- * +- * Copyright (C) 2019 Zodiac Inflight Innovations +- */ +- +-/dts-v1/; +-#include +-#include "imx7d.dtsi" +- +-/ { +- model = "ZII RPU2 Board"; +- compatible = "zii,imx7d-rpu2", "fsl,imx7d"; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- cs2000_ref: oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +- +- cs2000_in_dummy: dummy-oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pinctrl_leds_debug>; +- pinctrl-names = "default"; +- +- debug { +- label = "zii:green:debug1"; +- gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, +- <&adc2 1>; +- }; +- +- reg_can1_stby: regulator-can1-stby { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1_stby>; +- regulator-name = "can1-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_can2_stby: regulator-can2-stby { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2_stby>; +- regulator-name = "can2-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_vref_1v8: regulator-vref-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "vref-1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "GEN_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_5p0v_main: regulator-5p0v-main { +- compatible = "regulator-fixed"; +- regulator-name = "5V_MAIN"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- sound1 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "Audio Output 1"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sound1_codec>; +- simple-audio-card,frame-master = <&sound1_codec>; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "Headphone Jack", "HPLEFT", +- "Headphone Jack", "HPRIGHT", +- "LEFTIN", "HPL", +- "RIGHTIN", "HPR"; +- simple-audio-card,aux-devs = <&hpa1>; +- +- simple-audio-card,cpu { +- sound-dai = <&sai1>; +- }; +- +- sound1_codec: simple-audio-card,codec { +- sound-dai = <&codec1>; +- clocks = <&cs2000>; +- }; +- }; +- +- sound2 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "Audio Output 2"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sound2_codec>; +- simple-audio-card,frame-master = <&sound2_codec>; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "Headphone Jack", "HPLEFT", +- "Headphone Jack", "HPRIGHT", +- "LEFTIN", "HPL", +- "RIGHTIN", "HPR"; +- simple-audio-card,aux-devs = <&hpa2>; +- +- simple-audio-card,cpu { +- sound-dai = <&sai2>; +- }; +- +- sound2_codec: simple-audio-card,codec { +- sound-dai = <&codec2>; +- clocks = <&cs2000>; +- }; +- }; +- +- sound3 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "Audio Output 3"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sound3_codec>; +- simple-audio-card,frame-master = <&sound3_codec>; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "Headphone Jack", "HPLEFT", +- "Headphone Jack", "HPRIGHT", +- "LEFTIN", "HPL", +- "RIGHTIN", "HPR"; +- simple-audio-card,aux-devs = <&hpa3>; +- +- simple-audio-card,cpu { +- sound-dai = <&sai3>; +- }; +- +- sound3_codec: simple-audio-card,codec { +- sound-dai = <&codec3>; +- clocks = <&cs2000>; +- }; +- }; +-}; +- +-&adc1 { +- vref-supply = <®_vref_1v8>; +- status = "okay"; +-}; +- +-&adc2 { +- vref-supply = <®_vref_1v8>; +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <&sw1a_reg>; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; +- assigned-clock-rates = <884736000>; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, +- <&clks IMX7D_ENET1_TIME_ROOT_CLK>; +- assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; +- assigned-clock-rates = <0>, <100000000>; +- phy-mode = "rgmii"; +- status = "okay"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- +- mdio1: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- switch: switch@0 { +- compatible = "marvell,mv88e6085"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_switch>; +- reg = <0>; +- eeprom-length = <512>; +- interrupt-parent = <&gpio1>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "eth_cu_1000_1"; +- }; +- +- port@1 { +- reg = <1>; +- label = "eth_cu_1000_2"; +- }; +- +- port@2 { +- reg = <2>; +- label = "pic"; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <&fec1>; +- phy-mode = "rgmii-id"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- port@6 { +- reg = <6>; +- label = "gigabit_proc"; +- ethernet = <&fec2>; +- phy-mode = "rgmii-id"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&fec2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet2>; +- assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, +- <&clks IMX7D_ENET2_TIME_ROOT_CLK>; +- assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; +- assigned-clock-rates = <0>, <100000000>; +- phy-mode = "rgmii"; +- fsl,magic-packet; +- status = "okay"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +-}; +- +-&flexcan1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- xceiver-supply = <®_can1_stby>; +- status = "okay"; +-}; +- +-&flexcan2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- xceiver-supply = <®_can2_stby>; +- status = "okay"; +-}; +- +-&gpio1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio1>; +- +- gpio-line-names = "", "", "", "", "", "", "", "", +- "", "", +- "usb_1_en_b", +- "usb_2_en_b", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", ""; +-}; +- +-&gpio2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio2>; +- +- gpio-line-names = "12v_out_en_1", +- "12v_out_en_2", +- "12v_out_en_3", +- "28v_out_en_5", +- "28v_out_en_1", +- "28v_out_en_2", +- "28v_out_en_3", +- "28v_out_en_4", +- "", "", +- "usb_3_en_b", +- "usb_4_en_b", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", ""; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic: pmic@8 { +- compatible = "fsl,pfuze3000"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1a { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw1c_reg: sw1b { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1475000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1650000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen2_reg: vldo2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- regulator-always-on; +- }; +- +- vgen3_reg: vccsd { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen4_reg: v33 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vldo3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vldo4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +- +- cs2000: clkgen@4e { +- compatible = "cirrus,cs2000-cp"; +- reg = <0x4e>; +- #clock-cells = <0>; +- clock-names = "clk_in", "ref_clk"; +- clocks = <&cs2000_in_dummy>, <&cs2000_ref>; +- assigned-clocks = <&cs2000>; +- assigned-clock-rates = <24000000>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c04"; +- reg = <0x50>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c04"; +- reg = <0x52>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- codec2: codec@18 { +- compatible = "ti,tlv320dac3100"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_codec2>; +- reg = <0x18>; +- #sound-dai-cells = <0>; +- HPVDD-supply = <®_3p3v>; +- SPRVDD-supply = <®_3p3v>; +- SPLVDD-supply = <®_3p3v>; +- AVDD-supply = <®_3p3v>; +- IOVDD-supply = <®_3p3v>; +- DVDD-supply = <&vgen4_reg>; +- gpio-reset = <&gpio1 6 GPIO_ACTIVE_LOW>; +- }; +- +- hpa2: amp@60 { +- compatible = "ti,tpa6130a2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tpa2>; +- reg = <0x60>; +- power-gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; +- Vdd-supply = <®_5p0v_main>; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- codec3: codec@18 { +- compatible = "ti,tlv320dac3100"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_codec3>; +- reg = <0x18>; +- #sound-dai-cells = <0>; +- HPVDD-supply = <®_3p3v>; +- SPRVDD-supply = <®_3p3v>; +- SPLVDD-supply = <®_3p3v>; +- AVDD-supply = <®_3p3v>; +- IOVDD-supply = <®_3p3v>; +- DVDD-supply = <&vgen4_reg>; +- gpio-reset = <&gpio1 7 GPIO_ACTIVE_LOW>; +- }; +- +- hpa3: amp@60 { +- compatible = "ti,tpa6130a2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tpa3>; +- reg = <0x60>; +- power-gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; +- Vdd-supply = <®_5p0v_main>; +- }; +-}; +- +-&i2c4 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +- +- codec1: codec@18 { +- compatible = "ti,tlv320dac3100"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_codec1>; +- reg = <0x18>; +- #sound-dai-cells = <0>; +- HPVDD-supply = <®_3p3v>; +- SPRVDD-supply = <®_3p3v>; +- SPLVDD-supply = <®_3p3v>; +- AVDD-supply = <®_3p3v>; +- IOVDD-supply = <®_3p3v>; +- DVDD-supply = <&vgen4_reg>; +- gpio-reset = <&gpio1 5 GPIO_ACTIVE_LOW>; +- }; +- +- hpa1: amp@60 { +- compatible = "ti,tpa6130a2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tpa1>; +- reg = <0x60>; +- power-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; +- Vdd-supply = <®_5p0v_main>; +- }; +-}; +- +-&sai1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai1>; +- assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, +- <&clks IMX7D_SAI1_ROOT_CLK>; +- assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; +- assigned-clock-rates = <0>, <36864000>; +- status = "okay"; +-}; +- +-&sai2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai2>; +- assigned-clocks = <&clks IMX7D_SAI2_ROOT_SRC>, +- <&clks IMX7D_SAI2_ROOT_CLK>; +- assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; +- assigned-clock-rates = <0>, <36864000>; +- status = "okay"; +-}; +- +-&sai3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai3>; +- assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, +- <&clks IMX7D_SAI3_ROOT_CLK>; +- assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; +- assigned-clock-rates = <0>, <36864000>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; +- status = "okay"; +- +- rave-sp { +- compatible = "zii,rave-sp-rdu2"; +- current-speed = <1000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- watchdog { +- compatible = "zii,rave-sp-watchdog"; +- }; +- +- eeprom@a3 { +- compatible = "zii,rave-sp-eeprom"; +- reg = <0xa3 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- zii,eeprom-name = "main-eeprom"; +- }; +- }; +-}; +- +-&usbotg1 { +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- bus-width = <4>; +- no-1-8-v; +- no-sdio; +- keep-power-in-suspend; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- no-sdio; +- no-sd; +- keep-power-in-suspend; +- status = "okay"; +-}; +- +-&wdog1 { +- status = "disabled"; +-}; +- +-&snvs_rtc { +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 +- MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 +- MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 +- MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59 +- >; +- }; +- +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 +- MX7D_PAD_SD2_WP__ENET1_MDC 0x3 +- MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 +- MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 +- MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 +- MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 +- MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 +- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 +- MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 +- MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 +- MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 +- MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 +- MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 +- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 +- >; +- }; +- +- pinctrl_enet2: enet2grp { +- fsl,pins = < +- MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 +- MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 +- MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 +- MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 +- MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 +- MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 +- MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 +- MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 +- MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 +- MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 +- MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 +- MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 +- MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x1 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x59 +- MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x59 +- >; +- }; +- +- pinctrl_flexcan1_stby: flexcan1stbygrp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x59 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 +- MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 +- >; +- }; +- +- pinctrl_flexcan2_stby: flexcan2stbygrp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 +- >; +- }; +- +- pinctrl_gpio1: gpio1grp { +- fsl,pins = < +- MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x00 +- MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x00 +- >; +- }; +- +- pinctrl_gpio2: gpio2grp { +- fsl,pins = < +- MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x00 +- MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x00 +- MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x00 +- MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x03 +- MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x03 +- MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x03 +- MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x03 +- MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x03 +- MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x00 +- MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x00 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f +- MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f +- MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f +- MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f +- >; +- }; +- +- pinctrl_i2c3_gpio: i2c3gpiogrp { +- fsl,pins = < +- MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x4000007f +- MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x4000007f +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f +- MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f +- >; +- }; +- +- pinctrl_i2c4_gpio: i2c4gpiogrp { +- fsl,pins = < +- MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x4000007f +- MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x4000007f +- >; +- }; +- +- pinctrl_leds_debug: debuggrp { +- fsl,pins = < +- MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59 +- >; +- }; +- +- pinctrl_sai1: sai1grp { +- fsl,pins = < +- MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f +- MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f +- MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 +- >; +- }; +- +- pinctrl_sai2: sai2grp { +- fsl,pins = < +- MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f +- MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f +- MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 +- >; +- }; +- +- pinctrl_sai3: sai3grp { +- fsl,pins = < +- MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f +- MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f +- MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 +- >; +- }; +- +- pinctrl_tpa1: tpa6130-1grp { +- fsl,pins = < +- MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x40000038 +- >; +- }; +- +- pinctrl_tpa2: tpa6130-2grp { +- fsl,pins = < +- MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x40000038 +- >; +- }; +- +- pinctrl_tpa3: tpa6130-3grp { +- fsl,pins = < +- MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x40000038 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 +- MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79 +- MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX7D_PAD_SD1_CMD__SD1_CMD 0x59 +- MX7D_PAD_SD1_CLK__SD1_CLK 0x19 +- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 +- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 +- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 +- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x59 +- MX7D_PAD_SD3_CLK__SD3_CLK 0x19 +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 +- MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59 +- >; +- }; +-}; +- +-&iomuxc_lpsr { +- pinctrl_codec1: dac1grp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x40000038 +- >; +- }; +- +- pinctrl_codec2: dac2grp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x40000038 +- >; +- }; +- +- pinctrl_codec3: dac3grp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x40000038 +- >; +- }; +- +- pinctrl_switch: switchgrp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x08 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7d.dtsi b/scripts/dtc/include-prefixes/arm/imx7d.dtsi +deleted file mode 100644 +index b0bcfa9094a3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7d.dtsi ++++ /dev/null +@@ -1,221 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Copyright 2015 Freescale Semiconductor, Inc. +-// Copyright 2016 Toradex AG +- +-#include "imx7s.dtsi" +-#include +- +-/ { +- aliases { +- usb0 = &usbotg1; +- usb1 = &usbotg2; +- usb2 = &usbh; +- }; +- +- cpus { +- cpu0: cpu@0 { +- clock-frequency = <996000000>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- nvmem-cells = <&fuse_grade>; +- nvmem-cell-names = "speed_grade"; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <1>; +- clock-frequency = <996000000>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- cpu-idle-states = <&cpu_sleep_wait>; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupt-parent = <&intc>; +- interrupts = , +- , +- , +- ; +- }; +- +- cpu0_opp_table: opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-792000000 { +- opp-hz = /bits/ 64 <792000000>; +- opp-microvolt = <1000000>; +- clock-latency-ns = <150000>; +- opp-supported-hw = <0xd>, <0x7>; +- opp-suspend; +- }; +- +- opp-996000000 { +- opp-hz = /bits/ 64 <996000000>; +- opp-microvolt = <1100000>; +- clock-latency-ns = <150000>; +- opp-supported-hw = <0xc>, <0x7>; +- opp-suspend; +- }; +- +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <1225000>; +- clock-latency-ns = <150000>; +- opp-supported-hw = <0x8>, <0x3>; +- opp-suspend; +- }; +- }; +- +- usbphynop2: usbphynop2 { +- compatible = "usb-nop-xceiv"; +- clocks = <&clks IMX7D_USB_PHY2_CLK>; +- clock-names = "main_clk"; +- #phy-cells = <0>; +- }; +- +- soc { +- etm@3007d000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0x3007d000 0x1000>; +- +- /* +- * System will hang if added nosmp in kernel command line +- * without arm,primecell-periphid because amba bus try to +- * read id and core1 power off at this time. +- */ +- arm,primecell-periphid = <0xbb956>; +- cpu = <&cpu1>; +- clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etm1_out_port: endpoint { +- remote-endpoint = <&ca_funnel_in_port1>; +- }; +- }; +- }; +- }; +- +- intc: interrupt-controller@31001000 { +- compatible = "arm,cortex-a7-gic"; +- interrupts = ; +- #interrupt-cells = <3>; +- interrupt-controller; +- interrupt-parent = <&intc>; +- reg = <0x31001000 0x1000>, +- <0x31002000 0x2000>, +- <0x31004000 0x2000>, +- <0x31006000 0x2000>; +- }; +- }; +-}; +- +-&aips2 { +- pcie_phy: pcie-phy@306d0000 { +- compatible = "fsl,imx7d-pcie-phy"; +- reg = <0x306d0000 0x10000>; +- status = "disabled"; +- }; +-}; +- +-&aips3 { +- usbotg2: usb@30b20000 { +- compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; +- reg = <0x30b20000 0x200>; +- interrupts = ; +- clocks = <&clks IMX7D_USB_CTRL_CLK>; +- fsl,usbphy = <&usbphynop2>; +- fsl,usbmisc = <&usbmisc2 0>; +- phy-clkgate-delay-us = <400>; +- status = "disabled"; +- }; +- +- usbmisc2: usbmisc@30b20200 { +- #index-cells = <1>; +- compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; +- reg = <0x30b20200 0x200>; +- }; +- +- fec2: ethernet@30bf0000 { +- compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; +- reg = <0x30bf0000 0x10000>; +- interrupt-names = "int0", "int1", "int2", "pps"; +- interrupts = , +- , +- , +- ; +- clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>, +- <&clks IMX7D_ENET_AXI_ROOT_CLK>, +- <&clks IMX7D_ENET2_TIME_ROOT_CLK>, +- <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, +- <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; +- clock-names = "ipg", "ahb", "ptp", +- "enet_clk_ref", "enet_out"; +- fsl,num-tx-queues = <3>; +- fsl,num-rx-queues = <3>; +- fsl,stop-mode = <&gpr 0x10 4>; +- status = "disabled"; +- }; +- +- pcie: pcie@33800000 { +- compatible = "fsl,imx7d-pcie", "snps,dw-pcie"; +- reg = <0x33800000 0x4000>, +- <0x4ff00000 0x80000>; +- reg-names = "dbi", "config"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- bus-range = <0x00 0xff>; +- ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */ +- 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ +- num-lanes = <1>; +- num-viewport = <4>; +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- /* +- * Reference manual lists pci irqs incorrectly +- * Real hardware ordering is same as imx6: D+MSI, C, B, A +- */ +- interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, +- <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, +- <&clks IMX7D_PCIE_PHY_ROOT_CLK>; +- clock-names = "pcie", "pcie_bus", "pcie_phy"; +- assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>, +- <&clks IMX7D_PCIE_PHY_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, +- <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; +- +- fsl,max-link-speed = <2>; +- power-domains = <&pgc_pcie_phy>; +- resets = <&src IMX7_RESET_PCIEPHY>, +- <&src IMX7_RESET_PCIE_CTRL_APPS_EN>, +- <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>; +- reset-names = "pciephy", "apps", "turnoff"; +- fsl,imx7d-pcie-phy = <&pcie_phy>; +- status = "disabled"; +- }; +-}; +- +-&ca_funnel_in_ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <1>; +- ca_funnel_in_port1: endpoint { +- remote-endpoint = <&etm1_out_port>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7s-colibri-aster.dts b/scripts/dtc/include-prefixes/arm/imx7s-colibri-aster.dts +deleted file mode 100644 +index fca4e0a95c1b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7s-colibri-aster.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2017-2020 Toradex AG +- * +- */ +- +-/dts-v1/; +-#include "imx7s-colibri.dtsi" +-#include "imx7-colibri-aster.dtsi" +- +-/ { +- model = "Toradex Colibri iMX7S on Aster Carrier Board"; +- compatible = "toradex,colibri-imx7s-aster", "toradex,colibri-imx7s", +- "fsl,imx7s"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7s-colibri-eval-v3.dts b/scripts/dtc/include-prefixes/arm/imx7s-colibri-eval-v3.dts +deleted file mode 100644 +index aa70d3f2e2e2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7s-colibri-eval-v3.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2016-2020 Toradex +- */ +- +-/dts-v1/; +-#include "imx7s-colibri.dtsi" +-#include "imx7-colibri-eval-v3.dtsi" +- +-/ { +- model = "Toradex Colibri iMX7S on Colibri Evaluation Board V3"; +- compatible = "toradex,colibri-imx7s-eval-v3", "toradex,colibri-imx7s", +- "fsl,imx7s"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7s-colibri.dtsi b/scripts/dtc/include-prefixes/arm/imx7s-colibri.dtsi +deleted file mode 100644 +index 94de220a5965..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7s-colibri.dtsi ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2016-2020 Toradex +- */ +- +-#include "imx7s.dtsi" +-#include "imx7-colibri.dtsi" +- +-/ { +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; +- }; +-}; +- +-&gpmi { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7s-mba7.dts b/scripts/dtc/include-prefixes/arm/imx7s-mba7.dts +deleted file mode 100644 +index d7d3f530f843..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7s-mba7.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Device Tree Source for TQ Systems TQMa7S board on MBa7 carrier board. +- * +- * Copyright (C) 2016 TQ Systems GmbH +- * Author: Markus Niebel +- * Copyright (C) 2019 Bruno Thomsen +- */ +- +-/dts-v1/; +- +-#include "imx7s-tqma7.dtsi" +-#include "imx7-mba7.dtsi" +- +-/ { +- model = "TQ Systems TQMa7S board on MBa7 carrier board"; +- compatible = "tq,imx7s-mba7", "tq,imx7s-tqma7", "fsl,imx7s"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7s-tqma7.dtsi b/scripts/dtc/include-prefixes/arm/imx7s-tqma7.dtsi +deleted file mode 100644 +index 5f5433eb7dd7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7s-tqma7.dtsi ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Device Tree Include file for TQ Systems TQMa7S board with NXP i.MX7Solo SoC. +- * +- * Copyright (C) 2016 TQ Systems GmbH +- * Author: Markus Niebel +- * Copyright (C) 2019 Bruno Thomsen +- */ +- +-#include "imx7s.dtsi" +-#include "imx7-tqma7.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/imx7s-warp.dts b/scripts/dtc/include-prefixes/arm/imx7s-warp.dts +deleted file mode 100644 +index 569bbd84e371..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7s-warp.dts ++++ /dev/null +@@ -1,500 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2016 NXP Semiconductors. +- * Author: Fabio Estevam +- */ +- +-/dts-v1/; +- +-#include +-#include "imx7s.dtsi" +- +-/ { +- model = "Element14 Warp i.MX7 Board"; +- compatible = "element14,imx7s-warp", "fsl,imx7s"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&pinctrl_gpio>; +- autorepeat; +- +- back { +- label = "Back"; +- gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- reg_brcm: regulator-brcm { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_brcm_reg>; +- regulator-name = "brcm_reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <200000>; +- }; +- +- reg_bt: regulator-bt { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_bt_reg>; +- enable-active-high; +- gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; +- regulator-name = "bt_reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_peri_3p15v: regulator-peri-3p15v { +- compatible = "regulator-fixed"; +- regulator-name = "peri_3p15v_reg"; +- regulator-min-microvolt = <3150000>; +- regulator-max-microvolt = <3150000>; +- regulator-always-on; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "imx7-sgtl5000"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&dailink_master>; +- simple-audio-card,frame-master = <&dailink_master>; +- simple-audio-card,cpu { +- sound-dai = <&sai1>; +- }; +- +- dailink_master: simple-audio-card,codec { +- sound-dai = <&codec>; +- clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; +- }; +- }; +-}; +- +-&clks { +- assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; +- assigned-clock-rates = <884736000>; +-}; +- +-&csi { +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic: pfuze3000@8 { +- compatible = "fsl,pfuze3000"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1a { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1475000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- /* use sw1c_reg to align with pfuze100/pfuze200 */ +- sw1c_reg: sw1b { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1475000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <6250>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1650000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vgen1_reg: vldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen2_reg: vldo2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen3_reg: vccsd { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen4_reg: v33 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vldo3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vldo4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- ov2680: camera@36 { +- compatible = "ovti,ov2680"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ov2680>; +- reg = <0x36>; +- clocks = <&osc>; +- clock-names = "xvclk"; +- reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; +- DOVDD-supply = <&sw2_reg>; +- DVDD-supply = <&sw2_reg>; +- AVDD-supply = <®_peri_3p15v>; +- +- port { +- ov2680_to_mipi: endpoint { +- remote-endpoint = <&mipi_from_sensor>; +- clock-lanes = <0>; +- data-lanes = <1>; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-&i2c4 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +- +- codec: sgtl5000@a { +- #sound-dai-cells = <0>; +- reg = <0x0a>; +- compatible = "fsl,sgtl5000"; +- clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai1_mclk>; +- VDDA-supply = <&vgen4_reg>; +- VDDIO-supply = <&vgen4_reg>; +- VDDD-supply = <&vgen2_reg>; +- }; +- +- mpl3115@60 { +- compatible = "fsl,mpl3115"; +- reg = <0x60>; +- }; +-}; +- +-&mipi_csi { +- clock-frequency = <166000000>; +- fsl,csis-hs-settle = <3>; +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- mipi_from_sensor: endpoint { +- remote-endpoint = <&ov2680_to_mipi>; +- data-lanes = <1>; +- }; +- +- }; +-}; +- +-&sai1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai1>; +- assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, +- <&clks IMX7D_SAI1_ROOT_CLK>; +- assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; +- assigned-clock-rates = <0>, <36864000>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart6>; +- assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; +- fsl,dte-mode; +- status = "okay"; +-}; +- +-&usbotg1 { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- bus-width = <4>; +- keep-power-in-suspend; +- no-1-8-v; +- non-removable; +- vmmc-supply = <®_brcm>; +- status = "okay"; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; +- assigned-clock-rates = <400000000>; +- bus-width = <8>; +- no-1-8-v; +- fsl,tuning-step = <2>; +- non-removable; +- status = "okay"; +-}; +- +-&video_mux { +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_brcm_reg: brcmreggrp { +- fsl,pins = < +- MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */ +- >; +- }; +- +- pinctrl_bt_reg: btreggrp { +- fsl,pins = < +- MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */ +- >; +- }; +- +- pinctrl_gpio: gpiogrp { +- fsl,pins = < +- MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f +- MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f +- MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f +- MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f +- MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f +- >; +- }; +- +- pinctrl_ov2680: ov2660grp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14 +- >; +- }; +- +- pinctrl_sai1: sai1grp { +- fsl,pins = < +- MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f +- MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f +- MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f +- MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 +- >; +- }; +- +- pinctrl_sai1_mclk: sai1mclkgrp { +- fsl,pins = < +- MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 +- MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 +- MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 +- MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 +- MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 +- >; +- }; +- +- pinctrl_uart6: uart6grp { +- fsl,pins = < +- MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x79 +- MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x79 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX7D_PAD_SD1_CMD__SD1_CMD 0x59 +- MX7D_PAD_SD1_CLK__SD1_CLK 0x19 +- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 +- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 +- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 +- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 +- MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */ +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x59 +- MX7D_PAD_SD3_CLK__SD3_CLK 0x19 +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 +- MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x5a +- MX7D_PAD_SD3_CLK__SD3_CLK 0x1a +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a +- MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { +- fsl,pins = < +- MX7D_PAD_SD3_CMD__SD3_CMD 0x5b +- MX7D_PAD_SD3_CLK__SD3_CLK 0x1b +- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b +- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b +- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b +- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b +- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b +- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b +- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b +- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b +- MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b +- >; +- }; +-}; +- +-&iomuxc_lpsr { +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7s.dtsi b/scripts/dtc/include-prefixes/arm/imx7s.dtsi +deleted file mode 100644 +index 1843fc053870..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7s.dtsi ++++ /dev/null +@@ -1,1273 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Copyright 2015 Freescale Semiconductor, Inc. +-// Copyright 2016 Toradex AG +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include "imx7d-pinfunc.h" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * The decompressor and also some bootloaders rely on a +- * pre-existing /chosen node to be available to insert the +- * command line and merge other ATAGS info. +- */ +- chosen {}; +- +- aliases { +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- gpio3 = &gpio4; +- gpio4 = &gpio5; +- gpio5 = &gpio6; +- gpio6 = &gpio7; +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- i2c3 = &i2c4; +- mmc0 = &usdhc1; +- mmc1 = &usdhc2; +- mmc2 = &usdhc3; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- serial4 = &uart5; +- serial5 = &uart6; +- serial6 = &uart7; +- spi0 = &ecspi1; +- spi1 = &ecspi2; +- spi2 = &ecspi3; +- spi3 = &ecspi4; +- usb0 = &usbotg1; +- usb1 = &usbh; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- idle-states { +- entry-method = "psci"; +- +- cpu_sleep_wait: cpu-sleep-wait { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x0010000>; +- local-timer-stop; +- entry-latency-us = <100>; +- exit-latency-us = <50>; +- min-residency-us = <1000>; +- }; +- }; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <0>; +- clock-frequency = <792000000>; +- clock-latency = <61036>; /* two CLK32 periods */ +- clocks = <&clks IMX7D_CLK_ARM>; +- cpu-idle-states = <&cpu_sleep_wait>; +- }; +- }; +- +- ckil: clock-cki { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "ckil"; +- }; +- +- osc: clock-osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "osc"; +- }; +- +- usbphynop1: usbphynop1 { +- compatible = "usb-nop-xceiv"; +- clocks = <&clks IMX7D_USB_PHY1_CLK>; +- clock-names = "main_clk"; +- #phy-cells = <0>; +- }; +- +- usbphynop3: usbphynop3 { +- compatible = "usb-nop-xceiv"; +- clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; +- clock-names = "main_clk"; +- #phy-cells = <0>; +- }; +- +- pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupt-parent = <&gpc>; +- interrupts = ; +- interrupt-affinity = <&cpu0>; +- }; +- +- replicator { +- /* +- * non-configurable replicators don't show up on the +- * AMBA bus. As such no need to add "arm,primecell" +- */ +- compatible = "arm,coresight-static-replicator"; +- +- out-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- /* replicator output ports */ +- port@0 { +- reg = <0>; +- replicator_out_port0: endpoint { +- remote-endpoint = <&tpiu_in_port>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- replicator_out_port1: endpoint { +- remote-endpoint = <&etr_in_port>; +- }; +- }; +- }; +- +- in-ports { +- port { +- replicator_in_port0: endpoint { +- remote-endpoint = <&etf_out_port>; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- arm,cpu-registers-not-fw-configured; +- interrupt-parent = <&intc>; +- interrupts = , +- , +- , +- ; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&gpc>; +- ranges; +- +- funnel@30041000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0x30041000 0x1000>; +- clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; +- clock-names = "apb_pclk"; +- +- ca_funnel_in_ports: in-ports { +- port { +- ca_funnel_in_port0: endpoint { +- remote-endpoint = <&etm0_out_port>; +- }; +- }; +- +- /* the other input ports are not connect to anything */ +- }; +- +- out-ports { +- port { +- ca_funnel_out_port0: endpoint { +- remote-endpoint = <&hugo_funnel_in_port0>; +- }; +- }; +- +- }; +- }; +- +- etm@3007c000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0x3007c000 0x1000>; +- cpu = <&cpu0>; +- clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etm0_out_port: endpoint { +- remote-endpoint = <&ca_funnel_in_port0>; +- }; +- }; +- }; +- }; +- +- funnel@30083000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0x30083000 0x1000>; +- clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; +- clock-names = "apb_pclk"; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- hugo_funnel_in_port0: endpoint { +- remote-endpoint = <&ca_funnel_out_port0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- hugo_funnel_in_port1: endpoint { +- /* M4 input */ +- }; +- }; +- /* the other input ports are not connect to anything */ +- }; +- +- out-ports { +- port { +- hugo_funnel_out_port0: endpoint { +- remote-endpoint = <&etf_in_port>; +- }; +- }; +- }; +- }; +- +- etf@30084000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0x30084000 0x1000>; +- clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; +- clock-names = "apb_pclk"; +- +- in-ports { +- port { +- etf_in_port: endpoint { +- remote-endpoint = <&hugo_funnel_out_port0>; +- }; +- }; +- }; +- +- out-ports { +- port { +- etf_out_port: endpoint { +- remote-endpoint = <&replicator_in_port0>; +- }; +- }; +- }; +- }; +- +- etr@30086000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0x30086000 0x1000>; +- clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; +- clock-names = "apb_pclk"; +- +- in-ports { +- port { +- etr_in_port: endpoint { +- remote-endpoint = <&replicator_out_port1>; +- }; +- }; +- }; +- }; +- +- tpiu@30087000 { +- compatible = "arm,coresight-tpiu", "arm,primecell"; +- reg = <0x30087000 0x1000>; +- clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; +- clock-names = "apb_pclk"; +- +- in-ports { +- port { +- tpiu_in_port: endpoint { +- remote-endpoint = <&replicator_out_port0>; +- }; +- }; +- }; +- }; +- +- intc: interrupt-controller@31001000 { +- compatible = "arm,cortex-a7-gic"; +- interrupts = ; +- #interrupt-cells = <3>; +- interrupt-controller; +- interrupt-parent = <&intc>; +- reg = <0x31001000 0x1000>, +- <0x31002000 0x2000>, +- <0x31004000 0x2000>, +- <0x31006000 0x2000>; +- }; +- +- aips1: bus@30000000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x30000000 0x400000>; +- ranges; +- +- gpio1: gpio@30200000 { +- compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; +- reg = <0x30200000 0x10000>; +- interrupts = , /* GPIO1_INT15_0 */ +- ; /* GPIO1_INT31_16 */ +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; +- }; +- +- gpio2: gpio@30210000 { +- compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; +- reg = <0x30210000 0x10000>; +- interrupts = , +- ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 13 32>; +- }; +- +- gpio3: gpio@30220000 { +- compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; +- reg = <0x30220000 0x10000>; +- interrupts = , +- ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 45 29>; +- }; +- +- gpio4: gpio@30230000 { +- compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; +- reg = <0x30230000 0x10000>; +- interrupts = , +- ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 74 24>; +- }; +- +- gpio5: gpio@30240000 { +- compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; +- reg = <0x30240000 0x10000>; +- interrupts = , +- ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 98 18>; +- }; +- +- gpio6: gpio@30250000 { +- compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; +- reg = <0x30250000 0x10000>; +- interrupts = , +- ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 116 23>; +- }; +- +- gpio7: gpio@30260000 { +- compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; +- reg = <0x30260000 0x10000>; +- interrupts = , +- ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 139 16>; +- }; +- +- wdog1: watchdog@30280000 { +- compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; +- reg = <0x30280000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; +- }; +- +- wdog2: watchdog@30290000 { +- compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; +- reg = <0x30290000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; +- status = "disabled"; +- }; +- +- wdog3: watchdog@302a0000 { +- compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; +- reg = <0x302a0000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; +- status = "disabled"; +- }; +- +- wdog4: watchdog@302b0000 { +- compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; +- reg = <0x302b0000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; +- status = "disabled"; +- }; +- +- iomuxc_lpsr: iomuxc-lpsr@302c0000 { +- compatible = "fsl,imx7d-iomuxc-lpsr"; +- reg = <0x302c0000 0x10000>; +- fsl,input-sel = <&iomuxc>; +- }; +- +- gpt1: timer@302d0000 { +- compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; +- reg = <0x302d0000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_GPT1_ROOT_CLK>, +- <&clks IMX7D_GPT1_ROOT_CLK>; +- clock-names = "ipg", "per"; +- }; +- +- gpt2: timer@302e0000 { +- compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; +- reg = <0x302e0000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_GPT2_ROOT_CLK>, +- <&clks IMX7D_GPT2_ROOT_CLK>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- gpt3: timer@302f0000 { +- compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; +- reg = <0x302f0000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_GPT3_ROOT_CLK>, +- <&clks IMX7D_GPT3_ROOT_CLK>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- gpt4: timer@30300000 { +- compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; +- reg = <0x30300000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_GPT4_ROOT_CLK>, +- <&clks IMX7D_GPT4_ROOT_CLK>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- kpp: keypad@30320000 { +- compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; +- reg = <0x30320000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_KPP_ROOT_CLK>; +- status = "disabled"; +- }; +- +- iomuxc: pinctrl@30330000 { +- compatible = "fsl,imx7d-iomuxc"; +- reg = <0x30330000 0x10000>; +- }; +- +- gpr: iomuxc-gpr@30340000 { +- compatible = "fsl,imx7d-iomuxc-gpr", +- "fsl,imx6q-iomuxc-gpr", "syscon", +- "simple-mfd"; +- reg = <0x30340000 0x10000>; +- +- mux: mux-controller { +- compatible = "mmio-mux"; +- #mux-control-cells = <0>; +- mux-reg-masks = <0x14 0x00000010>; +- }; +- +- video_mux: csi-mux { +- compatible = "video-mux"; +- mux-controls = <&mux 0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- reg = <1>; +- +- csi_mux_from_mipi_vc0: endpoint { +- remote-endpoint = <&mipi_vc0_to_csi_mux>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- +- csi_mux_to_csi: endpoint { +- remote-endpoint = <&csi_from_csi_mux>; +- }; +- }; +- }; +- }; +- +- ocotp: efuse@30350000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,imx7d-ocotp", "syscon"; +- reg = <0x30350000 0x10000>; +- clocks = <&clks IMX7D_OCOTP_CLK>; +- +- tempmon_calib: calib@3c { +- reg = <0x3c 0x4>; +- }; +- +- fuse_grade: fuse-grade@10 { +- reg = <0x10 0x4>; +- }; +- }; +- +- anatop: anatop@30360000 { +- compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", +- "syscon", "simple-mfd"; +- reg = <0x30360000 0x10000>; +- interrupts = , +- ; +- +- reg_1p0d: regulator-vdd1p0d { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vdd1p0d"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1200000>; +- anatop-reg-offset = <0x210>; +- anatop-vol-bit-shift = <8>; +- anatop-vol-bit-width = <5>; +- anatop-min-bit-val = <8>; +- anatop-min-voltage = <800000>; +- anatop-max-voltage = <1200000>; +- anatop-enable-bit = <0>; +- }; +- +- reg_1p2: regulator-vdd1p2 { +- compatible = "fsl,anatop-regulator"; +- regulator-name = "vdd1p2"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1300000>; +- anatop-reg-offset = <0x220>; +- anatop-vol-bit-shift = <8>; +- anatop-vol-bit-width = <5>; +- anatop-min-bit-val = <0x14>; +- anatop-min-voltage = <1100000>; +- anatop-max-voltage = <1300000>; +- anatop-enable-bit = <0>; +- }; +- +- tempmon: tempmon { +- compatible = "fsl,imx7d-tempmon"; +- interrupt-parent = <&gpc>; +- interrupts = ; +- fsl,tempmon = <&anatop>; +- nvmem-cells = <&tempmon_calib>, <&fuse_grade>; +- nvmem-cell-names = "calib", "temp_grade"; +- clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; +- }; +- }; +- +- snvs: snvs@30370000 { +- compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; +- reg = <0x30370000 0x10000>; +- +- snvs_rtc: snvs-rtc-lp { +- compatible = "fsl,sec-v4.0-mon-rtc-lp"; +- regmap = <&snvs>; +- offset = <0x34>; +- interrupts = , +- ; +- clocks = <&clks IMX7D_SNVS_CLK>; +- clock-names = "snvs-rtc"; +- }; +- +- snvs_pwrkey: snvs-powerkey { +- compatible = "fsl,sec-v4.0-pwrkey"; +- regmap = <&snvs>; +- interrupts = ; +- clocks = <&clks IMX7D_SNVS_CLK>; +- clock-names = "snvs-pwrkey"; +- linux,keycode = ; +- wakeup-source; +- status = "disabled"; +- }; +- }; +- +- clks: clock-controller@30380000 { +- compatible = "fsl,imx7d-ccm"; +- reg = <0x30380000 0x10000>; +- interrupts = , +- ; +- #clock-cells = <1>; +- clocks = <&ckil>, <&osc>; +- clock-names = "ckil", "osc"; +- }; +- +- src: reset-controller@30390000 { +- compatible = "fsl,imx7d-src", "syscon"; +- reg = <0x30390000 0x10000>; +- interrupts = ; +- #reset-cells = <1>; +- }; +- +- gpc: gpc@303a0000 { +- compatible = "fsl,imx7d-gpc"; +- reg = <0x303a0000 0x10000>; +- interrupt-controller; +- interrupts = ; +- #interrupt-cells = <3>; +- interrupt-parent = <&intc>; +- #power-domain-cells = <1>; +- +- pgc { +- #address-cells = <1>; +- #size-cells = <0>; +- +- pgc_mipi_phy: power-domain@0 { +- #power-domain-cells = <0>; +- reg = <0>; +- power-supply = <®_1p0d>; +- }; +- +- pgc_pcie_phy: power-domain@1 { +- #power-domain-cells = <0>; +- reg = <1>; +- power-supply = <®_1p0d>; +- }; +- +- pgc_hsic_phy: power-domain@2 { +- #power-domain-cells = <0>; +- reg = <2>; +- power-supply = <®_1p2>; +- }; +- }; +- }; +- }; +- +- aips2: bus@30400000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x30400000 0x400000>; +- ranges; +- +- adc1: adc@30610000 { +- compatible = "fsl,imx7d-adc"; +- reg = <0x30610000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_ADC_ROOT_CLK>; +- clock-names = "adc"; +- #io-channel-cells = <1>; +- status = "disabled"; +- }; +- +- adc2: adc@30620000 { +- compatible = "fsl,imx7d-adc"; +- reg = <0x30620000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_ADC_ROOT_CLK>; +- clock-names = "adc"; +- #io-channel-cells = <1>; +- status = "disabled"; +- }; +- +- ecspi4: spi@30630000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; +- reg = <0x30630000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, +- <&clks IMX7D_ECSPI4_ROOT_CLK>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- ftm1: pwm@30640000 { +- compatible = "fsl,vf610-ftm-pwm"; +- reg = <0x30640000 0x10000>; +- #pwm-cells = <3>; +- interrupts = ; +- clock-names = "ftm_sys", "ftm_ext", +- "ftm_fix", "ftm_cnt_clk_en"; +- clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, +- <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, +- <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, +- <&clks IMX7D_FLEXTIMER1_ROOT_CLK>; +- status = "disabled"; +- }; +- +- ftm2: pwm@30650000 { +- compatible = "fsl,vf610-ftm-pwm"; +- reg = <0x30650000 0x10000>; +- #pwm-cells = <3>; +- interrupts = ; +- clock-names = "ftm_sys", "ftm_ext", +- "ftm_fix", "ftm_cnt_clk_en"; +- clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, +- <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, +- <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, +- <&clks IMX7D_FLEXTIMER2_ROOT_CLK>; +- status = "disabled"; +- }; +- +- pwm1: pwm@30660000 { +- compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; +- reg = <0x30660000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_PWM1_ROOT_CLK>, +- <&clks IMX7D_PWM1_ROOT_CLK>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm2: pwm@30670000 { +- compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; +- reg = <0x30670000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_PWM2_ROOT_CLK>, +- <&clks IMX7D_PWM2_ROOT_CLK>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm3: pwm@30680000 { +- compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; +- reg = <0x30680000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_PWM3_ROOT_CLK>, +- <&clks IMX7D_PWM3_ROOT_CLK>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm4: pwm@30690000 { +- compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; +- reg = <0x30690000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_PWM4_ROOT_CLK>, +- <&clks IMX7D_PWM4_ROOT_CLK>; +- clock-names = "ipg", "per"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- csi: csi@30710000 { +- compatible = "fsl,imx7-csi"; +- reg = <0x30710000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_CLK_DUMMY>, +- <&clks IMX7D_CSI_MCLK_ROOT_CLK>, +- <&clks IMX7D_CLK_DUMMY>; +- clock-names = "axi", "mclk", "dcic"; +- status = "disabled"; +- +- port { +- csi_from_csi_mux: endpoint { +- remote-endpoint = <&csi_mux_to_csi>; +- }; +- }; +- }; +- +- lcdif: lcdif@30730000 { +- compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; +- reg = <0x30730000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, +- <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; +- clock-names = "pix", "axi"; +- status = "disabled"; +- }; +- +- mipi_csi: mipi-csi@30750000 { +- compatible = "fsl,imx7-mipi-csi2"; +- reg = <0x30750000 0x10000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&clks IMX7D_IPG_ROOT_CLK>, +- <&clks IMX7D_MIPI_CSI_ROOT_CLK>, +- <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; +- clock-names = "pclk", "wrap", "phy"; +- power-domains = <&pgc_mipi_phy>; +- phy-supply = <®_1p0d>; +- resets = <&src IMX7_RESET_MIPI_PHY_MRST>; +- reset-names = "mrst"; +- status = "disabled"; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- reg = <1>; +- +- mipi_vc0_to_csi_mux: endpoint { +- remote-endpoint = <&csi_mux_from_mipi_vc0>; +- }; +- }; +- }; +- }; +- +- aips3: bus@30800000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x30800000 0x400000>; +- ranges; +- +- spba-bus@30800000 { +- compatible = "fsl,spba-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x30800000 0x100000>; +- ranges; +- +- ecspi1: spi@30820000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; +- reg = <0x30820000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, +- <&clks IMX7D_ECSPI1_ROOT_CLK>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- ecspi2: spi@30830000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; +- reg = <0x30830000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, +- <&clks IMX7D_ECSPI2_ROOT_CLK>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- ecspi3: spi@30840000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; +- reg = <0x30840000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, +- <&clks IMX7D_ECSPI3_ROOT_CLK>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart1: serial@30860000 { +- compatible = "fsl,imx7d-uart", +- "fsl,imx6q-uart"; +- reg = <0x30860000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_UART1_ROOT_CLK>, +- <&clks IMX7D_UART1_ROOT_CLK>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart2: serial@30890000 { +- compatible = "fsl,imx7d-uart", +- "fsl,imx6q-uart"; +- reg = <0x30890000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_UART2_ROOT_CLK>, +- <&clks IMX7D_UART2_ROOT_CLK>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart3: serial@30880000 { +- compatible = "fsl,imx7d-uart", +- "fsl,imx6q-uart"; +- reg = <0x30880000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_UART3_ROOT_CLK>, +- <&clks IMX7D_UART3_ROOT_CLK>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- sai1: sai@308a0000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; +- reg = <0x308a0000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_SAI1_IPG_CLK>, +- <&clks IMX7D_SAI1_ROOT_CLK>, +- <&clks IMX7D_CLK_DUMMY>, +- <&clks IMX7D_CLK_DUMMY>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dma-names = "rx", "tx"; +- dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; +- status = "disabled"; +- }; +- +- sai2: sai@308b0000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; +- reg = <0x308b0000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_SAI2_IPG_CLK>, +- <&clks IMX7D_SAI2_ROOT_CLK>, +- <&clks IMX7D_CLK_DUMMY>, +- <&clks IMX7D_CLK_DUMMY>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dma-names = "rx", "tx"; +- dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; +- status = "disabled"; +- }; +- +- sai3: sai@308c0000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; +- reg = <0x308c0000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_SAI3_IPG_CLK>, +- <&clks IMX7D_SAI3_ROOT_CLK>, +- <&clks IMX7D_CLK_DUMMY>, +- <&clks IMX7D_CLK_DUMMY>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dma-names = "rx", "tx"; +- dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; +- status = "disabled"; +- }; +- }; +- +- crypto: crypto@30900000 { +- compatible = "fsl,sec-v4.0"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x30900000 0x40000>; +- ranges = <0 0x30900000 0x40000>; +- interrupts = ; +- clocks = <&clks IMX7D_CAAM_CLK>, +- <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; +- clock-names = "ipg", "aclk"; +- +- sec_jr0: jr@1000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x1000 0x1000>; +- interrupts = ; +- }; +- +- sec_jr1: jr@2000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x2000 0x1000>; +- interrupts = ; +- }; +- +- sec_jr2: jr@3000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x3000 0x1000>; +- interrupts = ; +- }; +- }; +- +- flexcan1: can@30a00000 { +- compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; +- reg = <0x30a00000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_CLK_DUMMY>, +- <&clks IMX7D_CAN1_ROOT_CLK>; +- clock-names = "ipg", "per"; +- fsl,stop-mode = <&gpr 0x10 1>; +- status = "disabled"; +- }; +- +- flexcan2: can@30a10000 { +- compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; +- reg = <0x30a10000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_CLK_DUMMY>, +- <&clks IMX7D_CAN2_ROOT_CLK>; +- clock-names = "ipg", "per"; +- fsl,stop-mode = <&gpr 0x10 2>; +- status = "disabled"; +- }; +- +- i2c1: i2c@30a20000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; +- reg = <0x30a20000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_I2C1_ROOT_CLK>; +- status = "disabled"; +- }; +- +- i2c2: i2c@30a30000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; +- reg = <0x30a30000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_I2C2_ROOT_CLK>; +- status = "disabled"; +- }; +- +- i2c3: i2c@30a40000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; +- reg = <0x30a40000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_I2C3_ROOT_CLK>; +- status = "disabled"; +- }; +- +- i2c4: i2c@30a50000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; +- reg = <0x30a50000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_I2C4_ROOT_CLK>; +- status = "disabled"; +- }; +- +- uart4: serial@30a60000 { +- compatible = "fsl,imx7d-uart", +- "fsl,imx6q-uart"; +- reg = <0x30a60000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_UART4_ROOT_CLK>, +- <&clks IMX7D_UART4_ROOT_CLK>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart5: serial@30a70000 { +- compatible = "fsl,imx7d-uart", +- "fsl,imx6q-uart"; +- reg = <0x30a70000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_UART5_ROOT_CLK>, +- <&clks IMX7D_UART5_ROOT_CLK>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart6: serial@30a80000 { +- compatible = "fsl,imx7d-uart", +- "fsl,imx6q-uart"; +- reg = <0x30a80000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_UART6_ROOT_CLK>, +- <&clks IMX7D_UART6_ROOT_CLK>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart7: serial@30a90000 { +- compatible = "fsl,imx7d-uart", +- "fsl,imx6q-uart"; +- reg = <0x30a90000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_UART7_ROOT_CLK>, +- <&clks IMX7D_UART7_ROOT_CLK>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- mu0a: mailbox@30aa0000 { +- compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; +- reg = <0x30aa0000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_MU_ROOT_CLK>; +- #mbox-cells = <2>; +- status = "disabled"; +- }; +- +- mu0b: mailbox@30ab0000 { +- compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; +- reg = <0x30ab0000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_MU_ROOT_CLK>; +- #mbox-cells = <2>; +- fsl,mu-side-b; +- status = "disabled"; +- }; +- +- usbotg1: usb@30b10000 { +- compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; +- reg = <0x30b10000 0x200>; +- interrupts = ; +- clocks = <&clks IMX7D_USB_CTRL_CLK>; +- fsl,usbphy = <&usbphynop1>; +- fsl,usbmisc = <&usbmisc1 0>; +- phy-clkgate-delay-us = <400>; +- status = "disabled"; +- }; +- +- usbh: usb@30b30000 { +- compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; +- reg = <0x30b30000 0x200>; +- interrupts = ; +- power-domains = <&pgc_hsic_phy>; +- clocks = <&clks IMX7D_USB_CTRL_CLK>; +- fsl,usbphy = <&usbphynop3>; +- fsl,usbmisc = <&usbmisc3 0>; +- phy_type = "hsic"; +- dr_mode = "host"; +- phy-clkgate-delay-us = <400>; +- status = "disabled"; +- }; +- +- usbmisc1: usbmisc@30b10200 { +- #index-cells = <1>; +- compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; +- reg = <0x30b10200 0x200>; +- }; +- +- usbmisc3: usbmisc@30b30200 { +- #index-cells = <1>; +- compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; +- reg = <0x30b30200 0x200>; +- }; +- +- usdhc1: mmc@30b40000 { +- compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; +- reg = <0x30b40000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_IPG_ROOT_CLK>, +- <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, +- <&clks IMX7D_USDHC1_ROOT_CLK>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usdhc2: mmc@30b50000 { +- compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; +- reg = <0x30b50000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_IPG_ROOT_CLK>, +- <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, +- <&clks IMX7D_USDHC2_ROOT_CLK>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usdhc3: mmc@30b60000 { +- compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; +- reg = <0x30b60000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_IPG_ROOT_CLK>, +- <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, +- <&clks IMX7D_USDHC3_ROOT_CLK>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- qspi: spi@30bb0000 { +- compatible = "fsl,imx7d-qspi"; +- reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; +- reg-names = "QuadSPI", "QuadSPI-memory"; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&clks IMX7D_QSPI_ROOT_CLK>, +- <&clks IMX7D_QSPI_ROOT_CLK>; +- clock-names = "qspi_en", "qspi"; +- status = "disabled"; +- }; +- +- sdma: sdma@30bd0000 { +- compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; +- reg = <0x30bd0000 0x10000>; +- interrupts = ; +- clocks = <&clks IMX7D_IPG_ROOT_CLK>, +- <&clks IMX7D_SDMA_CORE_CLK>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; +- }; +- +- fec1: ethernet@30be0000 { +- compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; +- reg = <0x30be0000 0x10000>; +- interrupt-names = "int0", "int1", "int2", "pps"; +- interrupts = , +- , +- , +- ; +- clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>, +- <&clks IMX7D_ENET_AXI_ROOT_CLK>, +- <&clks IMX7D_ENET1_TIME_ROOT_CLK>, +- <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, +- <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; +- clock-names = "ipg", "ahb", "ptp", +- "enet_clk_ref", "enet_out"; +- fsl,num-tx-queues = <3>; +- fsl,num-rx-queues = <3>; +- fsl,stop-mode = <&gpr 0x10 3>; +- status = "disabled"; +- }; +- }; +- +- dma_apbh: dma-apbh@33000000 { +- compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; +- reg = <0x33000000 0x2000>; +- interrupts = , +- , +- , +- ; +- interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; +- #dma-cells = <1>; +- dma-channels = <4>; +- clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; +- }; +- +- gpmi: nand-controller@33002000{ +- compatible = "fsl,imx7d-gpmi-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x33002000 0x2000>, <0x33004000 0x4000>; +- reg-names = "gpmi-nand", "bch"; +- interrupts = ; +- interrupt-names = "bch"; +- clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, +- <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; +- clock-names = "gpmi_io", "gpmi_bch_apb"; +- dmas = <&dma_apbh 0>; +- dma-names = "rx-tx"; +- status = "disabled"; +- assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; +- assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7ulp-com.dts b/scripts/dtc/include-prefixes/arm/imx7ulp-com.dts +deleted file mode 100644 +index d76fea3b35c6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7ulp-com.dts ++++ /dev/null +@@ -1,79 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// +-// Copyright 2019 NXP +- +-/dts-v1/; +- +-#include "imx7ulp.dtsi" +-#include +- +-/ { +- model = "Embedded Artists i.MX7ULP COM"; +- compatible = "ea,imx7ulp-com", "fsl,imx7ulp"; +- +- chosen { +- stdout-path = &lpuart4; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x4000000>; +- }; +-}; +- +-&lpuart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lpuart4>; +- status = "okay"; +-}; +- +-&usbotg1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg1_id>; +- srp-disable; +- hnp-disable; +- adp-disable; +- status = "okay"; +-}; +- +-&usdhc0 { +- assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; +- assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc0>; +- non-removable; +- bus-width = <8>; +- no-1-8-v; +- status = "okay"; +-}; +- +-&iomuxc1 { +- pinctrl_lpuart4: lpuart4grp { +- fsl,pins = < +- IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 +- IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 +- >; +- }; +- +- pinctrl_usbotg1_id: otg1idgrp { +- fsl,pins = < +- IMX7ULP_PAD_PTC13__USB0_ID 0x10003 +- >; +- }; +- +- pinctrl_usdhc0: usdhc0grp { +- fsl,pins = < +- IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 +- IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042 +- IMX7ULP_PAD_PTD3__SDHC0_D7 0x43 +- IMX7ULP_PAD_PTD4__SDHC0_D6 0x43 +- IMX7ULP_PAD_PTD5__SDHC0_D5 0x43 +- IMX7ULP_PAD_PTD6__SDHC0_D4 0x43 +- IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 +- IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 +- IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 +- IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 +- IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7ulp-evk.dts b/scripts/dtc/include-prefixes/arm/imx7ulp-evk.dts +deleted file mode 100644 +index eff51e113db4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7ulp-evk.dts ++++ /dev/null +@@ -1,133 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2016 Freescale Semiconductor, Inc. +- * Copyright 2017-2018 NXP +- * Dong Aisheng +- */ +- +-/dts-v1/; +- +-#include "imx7ulp.dtsi" +- +-/ { +- model = "NXP i.MX7ULP EVK"; +- compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp"; +- +- chosen { +- stdout-path = &lpuart4; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x40000000>; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&tpm4 1 50000 0>; +- brightness-levels = <0 20 25 30 35 40 100>; +- default-brightness-level = <6>; +- status = "okay"; +- }; +- +- reg_usb_otg1_vbus: regulator-usb-otg1-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg1_vbus>; +- regulator-name = "usb_otg1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_vsd_3v3: regulator-vsd-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VSD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc0_rst>; +- gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&lpuart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lpuart4>; +- status = "okay"; +-}; +- +-&tpm4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0>; +- status = "okay"; +-}; +- +-&usbotg1 { +- vbus-supply = <®_usb_otg1_vbus>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg1_id>; +- srp-disable; +- hnp-disable; +- adp-disable; +- disable-over-current; +- status = "okay"; +-}; +- +-&usdhc0 { +- assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; +- assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc0>; +- cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_vsd_3v3>; +- status = "okay"; +-}; +- +-&iomuxc1 { +- pinctrl_lpuart4: lpuart4grp { +- fsl,pins = < +- IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 +- IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 +- >; +- bias-pull-up; +- }; +- +- pinctrl_pwm0: pwm0grp { +- fsl,pins = < +- IMX7ULP_PAD_PTF2__TPM4_CH1 0x2 +- >; +- }; +- +- pinctrl_usbotg1_vbus: otg1vbusgrp { +- fsl,pins = < +- IMX7ULP_PAD_PTC0__PTC0 0x20000 +- >; +- }; +- +- pinctrl_usbotg1_id: otg1idgrp { +- fsl,pins = < +- IMX7ULP_PAD_PTC13__USB0_ID 0x10003 +- >; +- }; +- +- pinctrl_usdhc0: usdhc0grp { +- fsl,pins = < +- IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 +- IMX7ULP_PAD_PTD2__SDHC0_CLK 0x40 +- IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 +- IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 +- IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 +- IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 +- IMX7ULP_PAD_PTC10__PTC10 0x3 /* CD */ +- >; +- }; +- +- pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp { +- fsl,pins = < +- IMX7ULP_PAD_PTD0__PTD0 0x3 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/imx7ulp-pinfunc.h b/scripts/dtc/include-prefixes/arm/imx7ulp-pinfunc.h +deleted file mode 100644 +index c0148d79b62d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7ulp-pinfunc.h ++++ /dev/null +@@ -1,478 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2016 Freescale Semiconductor, Inc. +- * Copyright 2017 NXP +- */ +- +-#ifndef __DTS_IMX7ULP_PINFUNC_H +-#define __DTS_IMX7ULP_PINFUNC_H +- +-/* +- * The pin function ID is a tuple of +- * +- */ +- +-#define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1 +-#define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1 +-#define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1 +-#define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0 +-#define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1 +-#define IMX7ULP_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1 +-#define IMX7ULP_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1 +-#define IMX7ULP_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1 +-#define IMX7ULP_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1 +-#define IMX7ULP_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1 +-#define IMX7ULP_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1 +-#define IMX7ULP_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1 +-#define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1 +-#define IMX7ULP_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1 +-#define IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1 +-#define IMX7ULP_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1 +-#define IMX7ULP_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1 +-#define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1 +-#define IMX7ULP_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0 +-#define IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1 +-#define IMX7ULP_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1 +-#define IMX7ULP_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1 +-#define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1 +-#define IMX7ULP_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1 +-#define IMX7ULP_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1 +-#define IMX7ULP_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1 +-#define IMX7ULP_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1 +-#define IMX7ULP_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1 +-#define IMX7ULP_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1 +-#define IMX7ULP_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1 +-#define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1 +-#define IMX7ULP_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1 +-#define IMX7ULP_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1 +-#define IMX7ULP_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1 +-#define IMX7ULP_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1 +-#define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1 +-#define IMX7ULP_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0 +-#define IMX7ULP_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1 +-#define IMX7ULP_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1 +-#define IMX7ULP_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1 +-#define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1 +-#define IMX7ULP_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1 +-#define IMX7ULP_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1 +-#define IMX7ULP_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1 +-#define IMX7ULP_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1 +-#define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1 +-#define IMX7ULP_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1 +-#define IMX7ULP_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1 +-#define IMX7ULP_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1 +-#define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1 +-#define IMX7ULP_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1 +-#define IMX7ULP_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1 +-#define IMX7ULP_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1 +-#define IMX7ULP_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1 +-#define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1 +-#define IMX7ULP_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0 +-#define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1 +-#define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1 +-#define IMX7ULP_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC13__USB0_ID 0x0034 0x0338 0xb 0x1 +-#define IMX7ULP_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1 +-#define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1 +-#define IMX7ULP_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1 +-#define IMX7ULP_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1 +-#define IMX7ULP_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1 +-#define IMX7ULP_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1 +-#define IMX7ULP_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1 +-#define IMX7ULP_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1 +-#define IMX7ULP_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1 +-#define IMX7ULP_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1 +-#define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1 +-#define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC16__USB1_OC2 0x0040 0x0334 0xb 0x1 +-#define IMX7ULP_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1 +-#define IMX7ULP_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1 +-#define IMX7ULP_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1 +-#define IMX7ULP_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1 +-#define IMX7ULP_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1 +-#define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1 +-#define IMX7ULP_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC18__USB0_ID 0x0048 0x0338 0xb 0x2 +-#define IMX7ULP_PAD_PTC18__VIU_DE 0x0048 0x033c 0xc 0x1 +-#define IMX7ULP_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1 +-#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1 +-#define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1 +-#define IMX7ULP_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTC19__USB0_ID 0x004c 0x0338 0xa 0x3 +-#define IMX7ULP_PAD_PTC19__USB1_PWR2 0x004c 0x0000 0xb 0x0 +-#define IMX7ULP_PAD_PTC19__VIU_DE 0x004c 0x033c 0xc 0x3 +-#define IMX7ULP_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2 +-#define IMX7ULP_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2 +-#define IMX7ULP_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2 +-#define IMX7ULP_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2 +-#define IMX7ULP_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0 +-#define IMX7ULP_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2 +-#define IMX7ULP_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2 +-#define IMX7ULP_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2 +-#define IMX7ULP_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0 +-#define IMX7ULP_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2 +-#define IMX7ULP_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0 +-#define IMX7ULP_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2 +-#define IMX7ULP_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0 +-#define IMX7ULP_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2 +-#define IMX7ULP_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2 +-#define IMX7ULP_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2 +-#define IMX7ULP_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0 +-#define IMX7ULP_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2 +-#define IMX7ULP_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2 +-#define IMX7ULP_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0 +-#define IMX7ULP_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2 +-#define IMX7ULP_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2 +-#define IMX7ULP_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2 +-#define IMX7ULP_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2 +-#define IMX7ULP_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0 +-#define IMX7ULP_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2 +-#define IMX7ULP_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0 +-#define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2 +-#define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2 +-#define IMX7ULP_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTE5__VIU_DE 0x0114 0x033c 0xc 0x2 +-#define IMX7ULP_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0 +-#define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2 +-#define IMX7ULP_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2 +-#define IMX7ULP_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2 +-#define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2 +-#define IMX7ULP_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTE6__USB0_OC 0x0118 0x0330 0xb 0x1 +-#define IMX7ULP_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTE7__USB0_PWR 0x011c 0x0000 0xb 0x0 +-#define IMX7ULP_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0 +-#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2 +-#define IMX7ULP_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2 +-#define IMX7ULP_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2 +-#define IMX7ULP_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0 +-#define IMX7ULP_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2 +-#define IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2 +-#define IMX7ULP_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2 +-#define IMX7ULP_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2 +-#define IMX7ULP_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1 +-#define IMX7ULP_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0 +-#define IMX7ULP_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2 +-#define IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0 +-#define IMX7ULP_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2 +-#define IMX7ULP_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2 +-#define IMX7ULP_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1 +-#define IMX7ULP_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0 +-#define IMX7ULP_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2 +-#define IMX7ULP_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2 +-#define IMX7ULP_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2 +-#define IMX7ULP_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2 +-#define IMX7ULP_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0 +-#define IMX7ULP_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0 +-#define IMX7ULP_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2 +-#define IMX7ULP_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2 +-#define IMX7ULP_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTE12__USB1_OC2 0x0130 0x0334 0xb 0x2 +-#define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0 +-#define IMX7ULP_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2 +-#define IMX7ULP_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2 +-#define IMX7ULP_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2 +-#define IMX7ULP_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2 +-#define IMX7ULP_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2 +-#define IMX7ULP_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTE13__USB1_PWR2 0x0134 0x0000 0xb 0x0 +-#define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0 +-#define IMX7ULP_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2 +-#define IMX7ULP_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0 +-#define IMX7ULP_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2 +-#define IMX7ULP_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2 +-#define IMX7ULP_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2 +-#define IMX7ULP_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTE14__USB0_OC 0x0138 0x0330 0xb 0x2 +-#define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0 +-#define IMX7ULP_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2 +-#define IMX7ULP_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2 +-#define IMX7ULP_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2 +-#define IMX7ULP_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2 +-#define IMX7ULP_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0 +-#define IMX7ULP_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0 +-#define IMX7ULP_PAD_PTE15__USB0_PWR 0x013c 0x0000 0xb 0x0 +-#define IMX7ULP_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0 +-#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2 +-#define IMX7ULP_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2 +-#define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2 +-#define IMX7ULP_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x033c 0xc 0x0 +-#define IMX7ULP_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3 +-#define IMX7ULP_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3 +-#define IMX7ULP_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3 +-#define IMX7ULP_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0 +-#define IMX7ULP_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3 +-#define IMX7ULP_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3 +-#define IMX7ULP_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3 +-#define IMX7ULP_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3 +-#define IMX7ULP_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3 +-#define IMX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3 +-#define IMX7ULP_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3 +-#define IMX7ULP_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2 +-#define IMX7ULP_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3 +-#define IMX7ULP_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3 +-#define IMX7ULP_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3 +-#define IMX7ULP_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2 +-#define IMX7ULP_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2 +-#define IMX7ULP_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3 +-#define IMX7ULP_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0 +-#define IMX7ULP_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3 +-#define IMX7ULP_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2 +-#define IMX7ULP_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2 +-#define IMX7ULP_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3 +-#define IMX7ULP_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3 +-#define IMX7ULP_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3 +-#define IMX7ULP_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2 +-#define IMX7ULP_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2 +-#define IMX7ULP_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3 +-#define IMX7ULP_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3 +-#define IMX7ULP_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0 +-#define IMX7ULP_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2 +-#define IMX7ULP_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3 +-#define IMX7ULP_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3 +-#define IMX7ULP_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3 +-#define IMX7ULP_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3 +-#define IMX7ULP_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0 +-#define IMX7ULP_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2 +-#define IMX7ULP_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3 +-#define IMX7ULP_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0 +-#define IMX7ULP_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3 +-#define IMX7ULP_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3 +-#define IMX7ULP_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0 +-#define IMX7ULP_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2 +-#define IMX7ULP_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3 +-#define IMX7ULP_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3 +-#define IMX7ULP_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3 +-#define IMX7ULP_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3 +-#define IMX7ULP_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0 +-#define IMX7ULP_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2 +-#define IMX7ULP_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3 +-#define IMX7ULP_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3 +-#define IMX7ULP_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3 +-#define IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0 +-#define IMX7ULP_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2 +-#define IMX7ULP_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3 +-#define IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3 +-#define IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3 +-#define IMX7ULP_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3 +-#define IMX7ULP_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0 +-#define IMX7ULP_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2 +-#define IMX7ULP_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3 +-#define IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0 +-#define IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3 +-#define IMX7ULP_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3 +-#define IMX7ULP_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0 +-#define IMX7ULP_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2 +-#define IMX7ULP_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3 +-#define IMX7ULP_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3 +-#define IMX7ULP_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3 +-#define IMX7ULP_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3 +-#define IMX7ULP_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0 +-#define IMX7ULP_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2 +-#define IMX7ULP_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3 +-#define IMX7ULP_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3 +-#define IMX7ULP_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0 +-#define IMX7ULP_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2 +-#define IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3 +-#define IMX7ULP_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3 +-#define IMX7ULP_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0 +-#define IMX7ULP_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2 +-#define IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3 +-#define IMX7ULP_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3 +-#define IMX7ULP_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0 +-#define IMX7ULP_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2 +-#define IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3 +-#define IMX7ULP_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3 +-#define IMX7ULP_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0 +-#define IMX7ULP_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0 +-#define IMX7ULP_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0 +-#define IMX7ULP_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0 +-#define IMX7ULP_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2 +-#define IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3 +-#define IMX7ULP_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3 +-#define IMX7ULP_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0 +- +-#endif /* __DTS_IMX7ULP_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm/imx7ulp.dtsi b/scripts/dtc/include-prefixes/arm/imx7ulp.dtsi +deleted file mode 100644 +index bcec98b96411..000000000000 +--- a/scripts/dtc/include-prefixes/arm/imx7ulp.dtsi ++++ /dev/null +@@ -1,461 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2016 Freescale Semiconductor, Inc. +- * Copyright 2017-2018 NXP +- * Dong Aisheng +- */ +- +-#include +-#include +-#include +- +-#include "imx7ulp-pinfunc.h" +- +-/ { +- interrupt-parent = <&intc>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- gpio0 = &gpio_ptc; +- gpio1 = &gpio_ptd; +- gpio2 = &gpio_pte; +- gpio3 = &gpio_ptf; +- i2c0 = &lpi2c6; +- i2c1 = &lpi2c7; +- mmc0 = &usdhc0; +- mmc1 = &usdhc1; +- serial0 = &lpuart4; +- serial1 = &lpuart5; +- serial2 = &lpuart6; +- serial3 = &lpuart7; +- usbphy0 = &usbphy1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@f00 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <0xf00>; +- }; +- }; +- +- intc: interrupt-controller@40021000 { +- compatible = "arm,cortex-a7-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x40021000 0x1000>, +- <0x40022000 0x1000>; +- }; +- +- rosc: clock-rosc { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-output-names = "rosc"; +- #clock-cells = <0>; +- }; +- +- sosc: clock-sosc { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "sosc"; +- #clock-cells = <0>; +- }; +- +- sirc: clock-sirc { +- compatible = "fixed-clock"; +- clock-frequency = <16000000>; +- clock-output-names = "sirc"; +- #clock-cells = <0>; +- }; +- +- firc: clock-firc { +- compatible = "fixed-clock"; +- clock-frequency = <48000000>; +- clock-output-names = "firc"; +- #clock-cells = <0>; +- }; +- +- upll: clock-upll { +- compatible = "fixed-clock"; +- clock-frequency = <480000000>; +- clock-output-names = "upll"; +- #clock-cells = <0>; +- }; +- +- ahbbridge0: bus@40000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x40000000 0x800000>; +- ranges; +- +- edma1: dma-controller@40080000 { +- #dma-cells = <2>; +- compatible = "fsl,imx7ulp-edma"; +- reg = <0x40080000 0x2000>, +- <0x40210000 0x1000>; +- dma-channels = <32>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clock-names = "dma", "dmamux0"; +- clocks = <&pcc2 IMX7ULP_CLK_DMA1>, +- <&pcc2 IMX7ULP_CLK_DMA_MUX1>; +- }; +- +- crypto: crypto@40240000 { +- compatible = "fsl,sec-v4.0"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x40240000 0x10000>; +- ranges = <0 0x40240000 0x10000>; +- clocks = <&pcc2 IMX7ULP_CLK_CAAM>, +- <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; +- clock-names = "aclk", "ipg"; +- +- sec_jr0: jr@1000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x1000 0x1000>; +- interrupts = ; +- }; +- +- sec_jr1: jr@2000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x2000 0x1000>; +- interrupts = ; +- }; +- }; +- +- lpuart4: serial@402d0000 { +- compatible = "fsl,imx7ulp-lpuart"; +- reg = <0x402d0000 0x1000>; +- interrupts = ; +- clocks = <&pcc2 IMX7ULP_CLK_LPUART4>; +- clock-names = "ipg"; +- assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>; +- assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; +- assigned-clock-rates = <24000000>; +- status = "disabled"; +- }; +- +- lpuart5: serial@402e0000 { +- compatible = "fsl,imx7ulp-lpuart"; +- reg = <0x402e0000 0x1000>; +- interrupts = ; +- clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; +- clock-names = "ipg"; +- assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; +- assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; +- assigned-clock-rates = <48000000>; +- status = "disabled"; +- }; +- +- tpm4: pwm@40250000 { +- compatible = "fsl,imx7ulp-pwm"; +- reg = <0x40250000 0x1000>; +- assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; +- assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; +- clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- tpm5: tpm@40260000 { +- compatible = "fsl,imx7ulp-tpm"; +- reg = <0x40260000 0x1000>; +- interrupts = ; +- clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, +- <&pcc2 IMX7ULP_CLK_LPTPM5>; +- clock-names = "ipg", "per"; +- }; +- +- usbotg1: usb@40330000 { +- compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb"; +- reg = <0x40330000 0x200>; +- interrupts = ; +- clocks = <&pcc2 IMX7ULP_CLK_USB0>; +- phys = <&usbphy1>; +- fsl,usbmisc = <&usbmisc1 0>; +- ahb-burst-config = <0x0>; +- tx-burst-size-dword = <0x8>; +- rx-burst-size-dword = <0x8>; +- status = "disabled"; +- }; +- +- usbmisc1: usbmisc@40330200 { +- compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc"; +- #index-cells = <1>; +- reg = <0x40330200 0x200>; +- }; +- +- usbphy1: usb-phy@40350000 { +- compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy"; +- reg = <0x40350000 0x1000>; +- interrupts = ; +- clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>; +- #phy-cells = <0>; +- }; +- +- usdhc0: mmc@40370000 { +- compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc"; +- reg = <0x40370000 0x10000>; +- interrupts = ; +- clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, +- <&scg1 IMX7ULP_CLK_NIC1_DIV>, +- <&pcc2 IMX7ULP_CLK_USDHC0>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- fsl,tuning-start-tap = <20>; +- fsl,tuning-step = <2>; +- status = "disabled"; +- }; +- +- usdhc1: mmc@40380000 { +- compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc"; +- reg = <0x40380000 0x10000>; +- interrupts = ; +- clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, +- <&scg1 IMX7ULP_CLK_NIC1_DIV>, +- <&pcc2 IMX7ULP_CLK_USDHC1>; +- clock-names = "ipg", "ahb", "per"; +- bus-width = <4>; +- fsl,tuning-start-tap = <20>; +- fsl,tuning-step = <2>; +- status = "disabled"; +- }; +- +- scg1: clock-controller@403e0000 { +- compatible = "fsl,imx7ulp-scg1"; +- reg = <0x403e0000 0x10000>; +- clocks = <&rosc>, <&sosc>, <&sirc>, +- <&firc>, <&upll>; +- clock-names = "rosc", "sosc", "sirc", +- "firc", "upll"; +- #clock-cells = <1>; +- }; +- +- wdog1: watchdog@403d0000 { +- compatible = "fsl,imx7ulp-wdt"; +- reg = <0x403d0000 0x10000>; +- interrupts = ; +- clocks = <&pcc2 IMX7ULP_CLK_WDG1>; +- assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; +- assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; +- timeout-sec = <40>; +- }; +- +- pcc2: clock-controller@403f0000 { +- compatible = "fsl,imx7ulp-pcc2"; +- reg = <0x403f0000 0x10000>; +- #clock-cells = <1>; +- clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, +- <&scg1 IMX7ULP_CLK_NIC1_DIV>, +- <&scg1 IMX7ULP_CLK_DDR_DIV>, +- <&scg1 IMX7ULP_CLK_APLL_PFD2>, +- <&scg1 IMX7ULP_CLK_APLL_PFD1>, +- <&scg1 IMX7ULP_CLK_APLL_PFD0>, +- <&scg1 IMX7ULP_CLK_UPLL>, +- <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, +- <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, +- <&scg1 IMX7ULP_CLK_ROSC>, +- <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; +- clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", +- "apll_pfd2", "apll_pfd1", "apll_pfd0", +- "upll", "sosc_bus_clk", +- "firc_bus_clk", "rosc", "spll_bus_clk"; +- assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>; +- assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; +- }; +- +- smc1: clock-controller@40410000 { +- compatible = "fsl,imx7ulp-smc1"; +- reg = <0x40410000 0x1000>; +- #clock-cells = <1>; +- clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>, +- <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>; +- clock-names = "divcore", "hsrun_divcore"; +- }; +- +- pcc3: clock-controller@40b30000 { +- compatible = "fsl,imx7ulp-pcc3"; +- reg = <0x40b30000 0x10000>; +- #clock-cells = <1>; +- clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, +- <&scg1 IMX7ULP_CLK_NIC1_DIV>, +- <&scg1 IMX7ULP_CLK_DDR_DIV>, +- <&scg1 IMX7ULP_CLK_APLL_PFD2>, +- <&scg1 IMX7ULP_CLK_APLL_PFD1>, +- <&scg1 IMX7ULP_CLK_APLL_PFD0>, +- <&scg1 IMX7ULP_CLK_UPLL>, +- <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, +- <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, +- <&scg1 IMX7ULP_CLK_ROSC>, +- <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; +- clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", +- "apll_pfd2", "apll_pfd1", "apll_pfd0", +- "upll", "sosc_bus_clk", +- "firc_bus_clk", "rosc", "spll_bus_clk"; +- }; +- }; +- +- ahbbridge1: bus@40800000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x40800000 0x800000>; +- ranges; +- +- lpi2c6: i2c@40a40000 { +- compatible = "fsl,imx7ulp-lpi2c"; +- reg = <0x40a40000 0x10000>; +- interrupts = ; +- clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; +- clock-names = "ipg"; +- assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; +- assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; +- assigned-clock-rates = <48000000>; +- status = "disabled"; +- }; +- +- lpi2c7: i2c@40a50000 { +- compatible = "fsl,imx7ulp-lpi2c"; +- reg = <0x40a50000 0x10000>; +- interrupts = ; +- clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; +- clock-names = "ipg"; +- assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; +- assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; +- assigned-clock-rates = <48000000>; +- status = "disabled"; +- }; +- +- lpuart6: serial@40a60000 { +- compatible = "fsl,imx7ulp-lpuart"; +- reg = <0x40a60000 0x1000>; +- interrupts = ; +- clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; +- clock-names = "ipg"; +- assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; +- assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; +- assigned-clock-rates = <48000000>; +- status = "disabled"; +- }; +- +- lpuart7: serial@40a70000 { +- compatible = "fsl,imx7ulp-lpuart"; +- reg = <0x40a70000 0x1000>; +- interrupts = ; +- clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; +- clock-names = "ipg"; +- assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; +- assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; +- assigned-clock-rates = <48000000>; +- status = "disabled"; +- }; +- +- memory-controller@40ab0000 { +- compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc"; +- reg = <0x40ab0000 0x1000>; +- clocks = <&pcc3 IMX7ULP_CLK_MMDC>; +- }; +- +- iomuxc1: pinctrl@40ac0000 { +- compatible = "fsl,imx7ulp-iomuxc1"; +- reg = <0x40ac0000 0x1000>; +- }; +- +- gpio_ptc: gpio@40ae0000 { +- compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; +- reg = <0x40ae0000 0x1000 0x400f0000 0x40>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, +- <&pcc3 IMX7ULP_CLK_PCTLC>; +- clock-names = "gpio", "port"; +- gpio-ranges = <&iomuxc1 0 0 20>; +- }; +- +- gpio_ptd: gpio@40af0000 { +- compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; +- reg = <0x40af0000 0x1000 0x400f0040 0x40>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, +- <&pcc3 IMX7ULP_CLK_PCTLD>; +- clock-names = "gpio", "port"; +- gpio-ranges = <&iomuxc1 0 32 12>; +- }; +- +- gpio_pte: gpio@40b00000 { +- compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; +- reg = <0x40b00000 0x1000 0x400f0080 0x40>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, +- <&pcc3 IMX7ULP_CLK_PCTLE>; +- clock-names = "gpio", "port"; +- gpio-ranges = <&iomuxc1 0 64 16>; +- }; +- +- gpio_ptf: gpio@40b10000 { +- compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; +- reg = <0x40b10000 0x1000 0x400f00c0 0x40>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, +- <&pcc3 IMX7ULP_CLK_PCTLF>; +- clock-names = "gpio", "port"; +- gpio-ranges = <&iomuxc1 0 96 20>; +- }; +- }; +- +- m4aips1: bus@41080000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x41080000 0x80000>; +- ranges; +- +- sim: sim@410a3000 { +- compatible = "fsl,imx7ulp-sim", "syscon"; +- reg = <0x410a3000 0x1000>; +- }; +- +- ocotp: efuse@410a6000 { +- compatible = "fsl,imx7ulp-ocotp", "syscon"; +- reg = <0x410a6000 0x4000>; +- clocks = <&scg1 IMX7ULP_CLK_DUMMY>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/integrator.dtsi b/scripts/dtc/include-prefixes/arm/integrator.dtsi +deleted file mode 100644 +index 602f74d2c758..000000000000 +--- a/scripts/dtc/include-prefixes/arm/integrator.dtsi ++++ /dev/null +@@ -1,143 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * SoC core Device Tree for the ARM Integrator platforms +- */ +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; +- }; +- +- core-module@10000000 { +- compatible = "arm,core-module-integrator", "syscon", "simple-mfd"; +- reg = <0x10000000 0x200>; +- +- /* Use core module LED to indicate CPU load */ +- led@c.0 { +- compatible = "register-bit-led"; +- offset = <0x0c>; +- mask = <0x01>; +- label = "integrator:core_module"; +- linux,default-trigger = "cpu0"; +- default-state = "on"; +- }; +- }; +- +- ebi@12000000 { +- compatible = "arm,external-bus-interface"; +- reg = <0x12000000 0x100>; +- }; +- +- timer@13000000 { +- reg = <0x13000000 0x100>; +- interrupt-parent = <&pic>; +- interrupts = <5>; +- }; +- +- timer@13000100 { +- reg = <0x13000100 0x100>; +- interrupt-parent = <&pic>; +- interrupts = <6>; +- }; +- +- timer@13000200 { +- reg = <0x13000200 0x100>; +- interrupt-parent = <&pic>; +- interrupts = <7>; +- }; +- +- pic@14000000 { +- compatible = "arm,versatile-fpga-irq"; +- #interrupt-cells = <1>; +- interrupt-controller; +- reg = <0x14000000 0x100>; +- clear-mask = <0xffffffff>; +- }; +- +- flash@24000000 { +- compatible = "arm,versatile-flash", "cfi-flash"; +- reg = <0x24000000 0x02000000>; +- bank-width = <4>; +- partitions { +- compatible = "arm,arm-firmware-suite"; +- }; +- }; +- +- fpga { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- interrupt-parent = <&pic>; +- +- /* +- * These PrimeCells are in the same locations and using the +- * same interrupts in all Integrators, however the silicon +- * version deployed is different. +- */ +- rtc@15000000 { +- reg = <0x15000000 0x1000>; +- interrupts = <8>; +- }; +- +- uart@16000000 { +- reg = <0x16000000 0x1000>; +- interrupts = <1>; +- }; +- +- uart@17000000 { +- reg = <0x17000000 0x1000>; +- interrupts = <2>; +- }; +- +- kmi@18000000 { +- reg = <0x18000000 0x1000>; +- interrupts = <3>; +- }; +- +- kmi@19000000 { +- reg = <0x19000000 0x1000>; +- interrupts = <4>; +- }; +- +- syscon { +- /* Debug registers mapped as syscon */ +- compatible = "syscon", "simple-mfd"; +- reg = <0x1a000000 0x10>; +- +- led@4.0 { +- compatible = "register-bit-led"; +- offset = <0x04>; +- mask = <0x01>; +- label = "integrator:green0"; +- linux,default-trigger = "heartbeat"; +- default-state = "on"; +- }; +- led@4.1 { +- compatible = "register-bit-led"; +- offset = <0x04>; +- mask = <0x02>; +- label = "integrator:yellow"; +- default-state = "off"; +- }; +- led@4.2 { +- compatible = "register-bit-led"; +- offset = <0x04>; +- mask = <0x04>; +- label = "integrator:red"; +- default-state = "off"; +- }; +- led@4.3 { +- compatible = "register-bit-led"; +- offset = <0x04>; +- mask = <0x08>; +- label = "integrator:green1"; +- default-state = "off"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/integratorap-im-pd1.dts b/scripts/dtc/include-prefixes/arm/integratorap-im-pd1.dts +deleted file mode 100644 +index 0614f82b808e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/integratorap-im-pd1.dts ++++ /dev/null +@@ -1,270 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree for the ARM Integrator/AP platform +- * with the IM-PD1 example logical module mounted. +- */ +- +-#include "integratorap.dts" +- +-/ { +- model = "ARM Integrator/AP with IM-PD1"; +- compatible = "arm,integrator-ap"; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- impd1_ram: vram@c2000000 { +- /* 1 MB of designated video RAM on the IM-PD1 */ +- compatible = "shared-dma-pool"; +- reg = <0xc2000000 0x00100000>; +- no-map; +- }; +- }; +-}; +- +-&lm0 { +- syscon@0 { +- compatible = "arm,im-pd1-syscon", "syscon"; +- reg = <0x00000000 0x1000>; +- +- vco1: vco1-clock { +- compatible = "arm,impd1-vco1"; +- #clock-cells = <0>; +- lock-offset = <0x08>; +- vco-offset = <0x00>; +- clocks = <&sysclk>; +- clock-output-names = "IM-PD1-VCO1"; +- }; +- +- vco2: vco2-clock { +- compatible = "arm,impd1-vco2"; +- #clock-cells = <0>; +- lock-offset = <0x08>; +- vco-offset = <0x04>; +- clocks = <&sysclk>; +- clock-output-names = "IM-PD1-VCO2"; +- }; +- }; +- +- /* Also used for the Smart Card Interface SCI */ +- impd1_uartclk: clock@1_4 { +- compatible = "fixed-factor-clock"; +- #clock-cells = <0>; +- clock-div = <4>; +- clock-mult = <1>; +- clocks = <&vco2>; +- clock-output-names = "VCO2_DIV4"; +- }; +- +- /* For the SSP the clock is divided by 64 */ +- impd1_sspclk: clock@1_64 { +- compatible = "fixed-factor-clock"; +- #clock-cells = <0>; +- clock-div = <64>; +- clock-mult = <1>; +- clocks = <&vco2>; +- clock-output-names = "VCO2_DIV64"; +- }; +- +- /* Fixed regulator for the MMC */ +- impd1_3v3: regulator { +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- /* Push buttons on the IM-PD1 */ +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- button@0 { +- debounce-interval = <50>; +- linux,code = ; +- label = "UP"; +- gpios = <&impd1_gpio1 0 GPIO_ACTIVE_HIGH>; +- }; +- button@1 { +- debounce-interval = <50>; +- linux,code = ; +- label = "DOWN"; +- gpios = <&impd1_gpio1 1 GPIO_ACTIVE_HIGH>; +- }; +- button@2 { +- debounce-interval = <50>; +- linux,code = ; +- label = "LEFT"; +- gpios = <&impd1_gpio1 2 GPIO_ACTIVE_HIGH>; +- }; +- button@3 { +- debounce-interval = <50>; +- linux,code = ; +- label = "UP"; +- gpios = <&impd1_gpio1 3 GPIO_ACTIVE_HIGH>; +- }; +- button@4 { +- debounce-interval = <50>; +- linux,code = ; +- label = "ESC"; +- gpios = <&impd1_gpio1 4 GPIO_ACTIVE_HIGH>; +- }; +- button@5 { +- debounce-interval = <50>; +- linux,code = ; +- label = "ENTER"; +- gpios = <&impd1_gpio1 5 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- +- bridge { +- compatible = "ti,ths8134b", "ti,ths8134"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- vga_bridge_in: endpoint { +- remote-endpoint = <&clcd_pads_vga_dac>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- vga_bridge_out: endpoint { +- remote-endpoint = <&vga_con_in>; +- }; +- }; +- }; +- }; +- +- vga { +- compatible = "vga-connector"; +- +- port { +- vga_con_in: endpoint { +- remote-endpoint = <&vga_bridge_out>; +- }; +- }; +- }; +- +- uart@100000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x00100000 0x1000>; +- interrupts-extended = <&impd1_vic 1>; +- clocks = <&impd1_uartclk>, <&sysclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- uart@200000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x00200000 0x1000>; +- interrupts-extended = <&impd1_vic 2>; +- clocks = <&impd1_uartclk>, <&sysclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- ssp@300000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x00300000 0x1000>; +- interrupts-extended = <&impd1_vic 3>; +- clocks = <&impd1_sspclk>, <&sysclk>; +- clock-names = "spiclk", "apb_pclk"; +- }; +- +- impd1_gpio0: gpio@400000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x00400000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts-extended = <&impd1_vic 4>; +- clocks = <&sysclk>; +- clock-names = "apb_pclk"; +- }; +- +- impd1_gpio1: gpio@500000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x00500000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts-extended = <&impd1_vic 5>; +- clocks = <&sysclk>; +- clock-names = "apb_pclk"; +- }; +- +- rtc@600000 { +- compatible = "arm,pl030", "arm,primecell"; +- reg = <0x00600000 0x1000>; +- interrupts-extended = <&impd1_vic 6>; +- clocks = <&sysclk>; +- clock-names = "apb_pclk"; +- }; +- +- mmc@700000 { +- compatible = "arm,pl181", "arm,primecell"; +- reg = <0x00700000 0x1000>; +- interrupts-extended = <&impd1_vic 7>, +- <&impd1_vic 8>; +- clocks = <&sysclk>, <&sysclk>; +- clock-names = "mclk", "apb_pclk"; +- bus-width = <1>; +- max-frequency = <515633>; +- vmmc-supply = <&impd1_3v3>; +- wp-gpios = <&impd1_gpio0 3 GPIO_ACTIVE_HIGH>; +- cd-gpios = <&impd1_gpio0 4 GPIO_ACTIVE_LOW>; +- }; +- +- aaci@800000 { +- compatible = "arm,pl041", "arm,primecell"; +- reg = <0x00800000 0x1000>; +- interrupts-extended = <&impd1_vic 9>; +- clocks = <&sysclk>; +- clock-names = "apb_pclk"; +- }; +- +- display@1000000 { +- compatible = "arm,pl110", "arm,primecell"; +- reg = <0x01000000 0x1000>; +- interrupts-extended = <&impd1_vic 11>; +- clocks = <&vco1>, <&sysclk>; +- clock-names = "clcdclk", "apb_pclk"; +- /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */ +- max-memory-bandwidth = <40000000>; +- memory-region = <&impd1_ram>; +- +- port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- clcd_pads_vga_dac: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vga_bridge_in>; +- arm,pl11x,tft-r0g0b0-pads = <0 8 16>; +- }; +- }; +- }; +- +- impd1_vic: interrupt-controller@3000000 { +- compatible = "arm,pl192-vic"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x03000000 0x1000>; +- /* Valid interrupts, 0-9 and 11 */ +- valid-mask = <0x00000bff>; +- /* LM site 0 has IRQ 9 on the PIC */ +- interrupts-extended = <&pic 9>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/integratorap.dts b/scripts/dtc/include-prefixes/arm/integratorap.dts +deleted file mode 100644 +index 67d1f9b24a52..000000000000 +--- a/scripts/dtc/include-prefixes/arm/integratorap.dts ++++ /dev/null +@@ -1,287 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree for the ARM Integrator/AP platform +- */ +- +-/dts-v1/; +-#include "integrator.dtsi" +-#include +-#include +- +-/ { +- model = "ARM Integrator/AP"; +- compatible = "arm,integrator-ap"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- /* +- * Since the board has pluggable CPU modules, we +- * cannot define a proper compatible here. Let the +- * boot loader fill in the apropriate compatible +- * string if necessary. +- */ +- /* compatible = "arm,arm926ej-s"; */ +- reg = <0>; +- /* +- * The documentation in ARM DUI 0138E page 3-12 states +- * that the maximum frequency for this clock is 200 MHz +- * but painful trial-and-error has proved to me that it +- * is actually just hanging the system above 71 MHz. +- * Sad but true. +- */ +- /* kHz uV */ +- operating-points = <71000 0 +- 66000 0 +- 60000 0 +- 48000 0 +- 36000 0 +- 24000 0 +- 12000 0>; +- clocks = <&cmosc>; +- clock-names = "cpu"; +- clock-latency = <1000000>; /* 1 ms */ +- }; +- }; +- +- aliases { +- arm,timer-primary = &timer2; +- arm,timer-secondary = &timer1; +- }; +- +- chosen { +- bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk"; +- }; +- +- /* 24 MHz chrystal on the Integrator/AP development board */ +- xtal24mhz: xtal24mhz@24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- pclk: pclk@0 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- /* The UART clock is 14.74 MHz divided by an ICS525 */ +- uartclk: uartclk@14.74M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <14745600>; +- clocks = <&xtal24mhz>; +- }; +- +- core-module@10000000 { +- /* 24 MHz chrystal on the core module */ +- cm24mhz: cm24mhz@24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- /* Oscillator on the core module, clocks the CPU core */ +- cmosc: cmosc@24M { +- compatible = "arm,syscon-icst525-integratorap-cm"; +- #clock-cells = <0>; +- lock-offset = <0x14>; +- vco-offset = <0x08>; +- clocks = <&cm24mhz>; +- }; +- +- /* Auxilary oscillator on the core module, 32.369MHz at boot */ +- auxosc: auxosc@24M { +- compatible = "arm,syscon-icst525"; +- #clock-cells = <0>; +- lock-offset = <0x14>; +- vco-offset = <0x1c>; +- clocks = <&cm24mhz>; +- }; +- }; +- +- syscon { +- compatible = "arm,integrator-ap-syscon", "syscon"; +- reg = <0x11000000 0x100>; +- +- /* +- * SYSCLK clocks PCIv3 bridge, system controller and the +- * logic modules. +- */ +- sysclk: apsys@24M { +- compatible = "arm,syscon-icst525-integratorap-sys"; +- #clock-cells = <0>; +- lock-offset = <0x1c>; +- vco-offset = <0x04>; +- clocks = <&xtal24mhz>; +- }; +- +- /* One-bit control for the PCI bus clock (33 or 25 MHz) */ +- pciclk: pciclk@24M { +- compatible = "arm,syscon-icst525-integratorap-pci"; +- #clock-cells = <0>; +- lock-offset = <0x1c>; +- vco-offset = <0x04>; +- clocks = <&xtal24mhz>; +- }; +- }; +- +- timer0: timer@13000000 { +- compatible = "arm,integrator-timer"; +- clocks = <&xtal24mhz>; +- }; +- +- timer1: timer@13000100 { +- compatible = "arm,integrator-timer"; +- clocks = <&xtal24mhz>; +- }; +- +- timer2: timer@13000200 { +- compatible = "arm,integrator-timer"; +- clocks = <&xtal24mhz>; +- }; +- +- pic: pic@14000000 { +- valid-mask = <0x003fffff>; +- }; +- +- pci: pciv3@62000000 { +- compatible = "arm,integrator-ap-pci", "v3,v360epc-pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- /* Bridge registers and config access space */ +- reg = <0x62000000 0x10000>, <0x61000000 0x01000000>; +- interrupt-parent = <&pic>; +- interrupts = <17>; /* Bus error IRQ */ +- clocks = <&pciclk>; +- bus-range = <0x00 0xff>; +- ranges = <0x01000000 0 0x0000000 /* I/O space @00000000 */ +- 0x60000000 0 0x00010000 /* 64 KB @ LB 60000000 */ +- 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */ +- 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */ +- 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */ +- 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */ +- dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */ +- 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */ +- 0x02000000 0 0x80000000 /* Core module alias memory */ +- 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */ +- interrupt-map-mask = <0xf800 0 0 0x7>; +- interrupt-map = < +- /* IDSEL 9 */ +- 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */ +- 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */ +- 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */ +- 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */ +- /* IDSEL 10 */ +- 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */ +- 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */ +- 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */ +- 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */ +- /* IDSEL 11 */ +- 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */ +- 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */ +- 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */ +- 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */ +- /* IDSEL 12 */ +- 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */ +- 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */ +- 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */ +- 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */ +- >; +- }; +- +- fpga { +- /* +- * The Integator/AP predates the idea to have magic numbers +- * identifying the PrimeCell in hardware, thus we have to +- * supply these from the device tree. +- */ +- rtc: rtc@15000000 { +- compatible = "arm,pl030", "arm,primecell"; +- arm,primecell-periphid = <0x00041030>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- uart0: uart@16000000 { +- compatible = "arm,pl010", "arm,primecell"; +- arm,primecell-periphid = <0x00041010>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- uart1: uart@17000000 { +- compatible = "arm,pl010", "arm,primecell"; +- arm,primecell-periphid = <0x00041010>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- kmi0: kmi@18000000 { +- compatible = "arm,pl050", "arm,primecell"; +- arm,primecell-periphid = <0x00041050>; +- clocks = <&xtal24mhz>, <&pclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- kmi1: kmi@19000000 { +- compatible = "arm,pl050", "arm,primecell"; +- arm,primecell-periphid = <0x00041050>; +- clocks = <&xtal24mhz>, <&pclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- }; +- +- /* +- * Logic module bus, we support up to 4 logical modules +- * They appear at 0xc0000000, 0xd0000000, 0xe0000000 and 0xf0000000 +- * and use interrupts 9, 10, 11 and 12 respectively. +- */ +- bus@c0000000 { +- compatible = "arm,integrator-ap-lm"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0xc0000000 0xc0000000 0x40000000>; +- dma-ranges; +- +- lm0: bus@c0000000 { +- compatible = "simple-bus"; +- ranges = <0x00000000 0xc0000000 0x10000000>; +- dma-ranges = <0x00000000 0x80000000 0x10000000>; +- reg = <0xc0000000 0x10000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- lm1: bus@d0000000 { +- compatible = "simple-bus"; +- ranges = <0x00000000 0xd0000000 0x10000000>; +- dma-ranges = <0x00000000 0x80000000 0x10000000>; +- reg = <0xd0000000 0x10000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- lm2: bus@e0000000 { +- compatible = "simple-bus"; +- ranges = <0x00000000 0xe0000000 0x10000000>; +- dma-ranges = <0x00000000 0x80000000 0x10000000>; +- reg = <0xe0000000 0x10000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- lm3: bus@f0000000 { +- compatible = "simple-bus"; +- ranges = <0x00000000 0xf0000000 0x10000000>; +- dma-ranges = <0x00000000 0x80000000 0x10000000>; +- reg = <0xf0000000 0x10000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/integratorcp.dts b/scripts/dtc/include-prefixes/arm/integratorcp.dts +deleted file mode 100644 +index 01fa229e1bd0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/integratorcp.dts ++++ /dev/null +@@ -1,319 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree for the ARM Integrator/CP platform +- */ +- +-/dts-v1/; +-/include/ "integrator.dtsi" +- +-/ { +- model = "ARM Integrator/CP"; +- compatible = "arm,integrator-cp"; +- +- chosen { +- bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- /* +- * Since the board has pluggable CPU modules, we +- * cannot define a proper compatible here. Let the +- * boot loader fill in the apropriate compatible +- * string if necessary. +- */ +- /* compatible = "arm,arm920t"; */ +- reg = <0>; +- /* +- * TBD comment. +- */ +- /* kHz uV */ +- operating-points = <50000 0 +- 48000 0>; +- clocks = <&cmcore>; +- clock-names = "cpu"; +- clock-latency = <1000000>; /* 1 ms */ +- }; +- }; +- +- /* +- * The Integrator/CP overall clocking architecture can be found in +- * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which +- * appear to illustrate the layout used in most configurations. +- */ +- +- /* The codec chrystal operates at 24.576 MHz */ +- xtal_codec: xtal24.576@24.576M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24576000>; +- }; +- +- /* The chrystal is divided by 2 by the codec for the AACI bit clock */ +- aaci_bitclk: aaci_bitclk@12.288M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <2>; +- clock-mult = <1>; +- clocks = <&xtal_codec>; +- }; +- +- /* This is a 25MHz chrystal on the base board */ +- xtal25mhz: xtal25mhz@25M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25000000>; +- }; +- +- /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */ +- uartclk: uartclk@14.74M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <14745600>; +- }; +- +- /* Actually sysclk I think */ +- pclk: pclk@0 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- core-module@10000000 { +- /* 24 MHz chrystal on the core module */ +- cm24mhz: cm24mhz@24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- /* Oscillator on the core module, clocks the CPU core */ +- cmcore: cmosc@24M { +- compatible = "arm,syscon-icst525-integratorcp-cm-core"; +- #clock-cells = <0>; +- lock-offset = <0x14>; +- vco-offset = <0x08>; +- clocks = <&cm24mhz>; +- }; +- +- /* Oscillator on the core module, clocks the memory bus */ +- cmmem: cmosc@24M { +- compatible = "arm,syscon-icst525-integratorcp-cm-mem"; +- #clock-cells = <0>; +- lock-offset = <0x14>; +- vco-offset = <0x08>; +- clocks = <&cm24mhz>; +- }; +- +- /* Auxilary oscillator on the core module, clocks the CLCD */ +- auxosc: auxosc@24M { +- compatible = "arm,syscon-icst525"; +- #clock-cells = <0>; +- lock-offset = <0x14>; +- vco-offset = <0x1c>; +- clocks = <&cm24mhz>; +- }; +- +- /* The KMI clock is the 24 MHz oscillator divided to 8MHz */ +- kmiclk: kmiclk@1M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <3>; +- clock-mult = <1>; +- clocks = <&cm24mhz>; +- }; +- +- /* The timer clock is the 24 MHz oscillator divided to 1MHz */ +- timclk: timclk@1M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <24>; +- clock-mult = <1>; +- clocks = <&cm24mhz>; +- }; +- }; +- +- syscon { +- compatible = "arm,integrator-cp-syscon", "syscon"; +- reg = <0xcb000000 0x100>; +- }; +- +- timer0: timer@13000000 { +- /* TIMER0 runs directly on the 25MHz chrystal */ +- compatible = "arm,integrator-cp-timer"; +- clocks = <&xtal25mhz>; +- }; +- +- timer1: timer@13000100 { +- /* TIMER1 runs @ 1MHz */ +- compatible = "arm,integrator-cp-timer"; +- clocks = <&timclk>; +- }; +- +- timer2: timer@13000200 { +- /* TIMER2 runs @ 1MHz */ +- compatible = "arm,integrator-cp-timer"; +- clocks = <&timclk>; +- }; +- +- pic: pic@14000000 { +- valid-mask = <0x1fc003ff>; +- }; +- +- cic: cic@10000040 { +- compatible = "arm,versatile-fpga-irq"; +- #interrupt-cells = <1>; +- interrupt-controller; +- reg = <0x10000040 0x100>; +- clear-mask = <0xffffffff>; +- valid-mask = <0x00000007>; +- }; +- +- /* The SIC is cascaded off IRQ 26 on the PIC */ +- sic: sic@ca000000 { +- compatible = "arm,versatile-fpga-irq"; +- interrupt-parent = <&pic>; +- interrupts = <26>; +- #interrupt-cells = <1>; +- interrupt-controller; +- reg = <0xca000000 0x100>; +- clear-mask = <0x00000fff>; +- valid-mask = <0x00000fff>; +- }; +- +- ethernet@c8000000 { +- compatible = "smsc,lan91c111"; +- reg = <0xc8000000 0x10>; +- interrupt-parent = <&pic>; +- interrupts = <27>; +- }; +- +- bridge { +- compatible = "ti,ths8134a", "ti,ths8134"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- vga_bridge_in: endpoint { +- remote-endpoint = <&clcd_pads_vga_dac>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- vga_bridge_out: endpoint { +- remote-endpoint = <&vga_con_in>; +- }; +- }; +- }; +- }; +- +- vga { +- compatible = "vga-connector"; +- +- port { +- vga_con_in: endpoint { +- remote-endpoint = <&vga_bridge_out>; +- }; +- }; +- }; +- +- fpga { +- /* +- * These PrimeCells are at the same location and using +- * the same interrupts in all Integrators, but in the CP +- * slightly newer versions are deployed. +- */ +- rtc@15000000 { +- compatible = "arm,pl031", "arm,primecell"; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- uart@16000000 { +- compatible = "arm,pl011", "arm,primecell"; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- uart@17000000 { +- compatible = "arm,pl011", "arm,primecell"; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- kmi@18000000 { +- compatible = "arm,pl050", "arm,primecell"; +- clocks = <&kmiclk>, <&pclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- kmi@19000000 { +- compatible = "arm,pl050", "arm,primecell"; +- clocks = <&kmiclk>, <&pclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- /* +- * These PrimeCells are only available on the Integrator/CP +- */ +- mmc@1c000000 { +- compatible = "arm,pl180", "arm,primecell"; +- reg = <0x1c000000 0x1000>; +- interrupts = <23 24>; +- max-frequency = <515633>; +- clocks = <&uartclk>, <&pclk>; +- clock-names = "mclk", "apb_pclk"; +- }; +- +- aaci@1d000000 { +- compatible = "arm,pl041", "arm,primecell"; +- reg = <0x1d000000 0x1000>; +- interrupts = <25>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- clcd@c0000000 { +- compatible = "arm,pl110", "arm,primecell"; +- reg = <0xC0000000 0x1000>; +- interrupts = <22>; +- clocks = <&auxosc>, <&pclk>; +- clock-names = "clcdclk", "apb_pclk"; +- /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */ +- max-memory-bandwidth = <40000000>; +- +- /* +- * This port is routed through a PLD (Programmable +- * Logic Device) that routes the output from the CLCD +- * (after transformations) to the VGA DAC and also an +- * external panel connector. The PLD is essential for +- * supporting RGB565/BGR565. +- * +- * The signals from the port thus reaches two endpoints. +- * The PLD is managed through a few special bits in the +- * FPGA "sysreg". +- * +- * This arrangement can be clearly seen in +- * ARM DUI 0225D, page 3-41, figure 3-19. +- */ +- port@0 { +- clcd_pads_vga_dac: endpoint { +- remote-endpoint = <&vga_bridge_in>; +- arm,pl11x,tft-r0g0b0-pads = <0 8 16>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp42x-adi-coyote.dts b/scripts/dtc/include-prefixes/arm/intel-ixp42x-adi-coyote.dts +deleted file mode 100644 +index 44c017b78008..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp42x-adi-coyote.dts ++++ /dev/null +@@ -1,110 +0,0 @@ +-// SPDX-License-Identifier: ISC +-/* +- * Device Tree file for ADI Engineering Coyote platform. +- * Derived from boardfiles written by MontaVista software. +- * Ethernet set-up from OpenWrt. +- */ +- +-/dts-v1/; +- +-#include "intel-ixp42x.dtsi" +-#include +- +-/ { +- model = "ADI Engineering Coyote reference design"; +- compatible = "adieng,coyote", "intel,ixp42x"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { +- /* CHECKME: 16 MB SDRAM minimum, maybe the Coyote actually has more */ +- device_type = "memory"; +- reg = <0x00000000 0x01000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait"; +- stdout-path = "uart1:115200n8"; +- }; +- +- aliases { +- /* These are switched around */ +- serial0 = &uart1; +- serial1 = &uart0; +- }; +- +- soc { +- bus@c4000000 { +- flash@0,0 { +- compatible = "intel,ixp4xx-flash", "cfi-flash"; +- bank-width = <2>; +- /* +- * 32 MB of Flash in 128 0x20000 sized blocks +- * mapped in at CS0 and CS1 +- */ +- reg = <0 0x00000000 0x2000000>; +- +- /* Configure expansion bus to allow writes */ +- intel,ixp4xx-eb-write-enable = <1>; +- +- partitions { +- compatible = "redboot-fis"; +- /* CHECKME: guess this is Redboot FIS */ +- fis-index-block = <0x1ff>; +- }; +- }; +- }; +- +- pci@c0000000 { +- status = "ok"; +- +- /* +- * Taken from Coyote PCI boardfile. +- * We have slots (IDSEL) 1 and 2 with one assigned IRQ +- * each handling all IRQs. +- */ +- interrupt-map = +- /* IDSEL 1 */ +- <0x0800 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 6 */ +- <0x0800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 6 */ +- <0x0800 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 6 */ +- <0x0800 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 6 */ +- /* IDSEL 2 */ +- <0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */ +- <0x1000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 11 */ +- <0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */ +- <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 11 */ +- }; +- +- /* EthB */ +- ethernet@c8009000 { +- status = "ok"; +- queue-rx = <&qmgr 3>; +- queue-txready = <&qmgr 20>; +- phy-mode = "rgmii"; +- phy-handle = <&phy5>; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy4: ethernet-phy@4 { +- reg = <4>; +- }; +- +- phy5: ethernet-phy@5 { +- reg = <5>; +- }; +- }; +- }; +- +- /* EthC */ +- ethernet@c800a000 { +- status = "ok"; +- queue-rx = <&qmgr 4>; +- queue-txready = <&qmgr 21>; +- phy-mode = "rgmii"; +- phy-handle = <&phy4>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp42x-arcom-vulcan.dts b/scripts/dtc/include-prefixes/arm/intel-ixp42x-arcom-vulcan.dts +deleted file mode 100644 +index 7200126cb3b5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp42x-arcom-vulcan.dts ++++ /dev/null +@@ -1,167 +0,0 @@ +-// SPDX-License-Identifier: ISC +-/* +- * Device Tree file for the Arcom/Eurotech Vulcan board. +- * This board is a single board computer in the PC/104 form factor based on +- * IXP425, and was released around 2005. It previously had the name "Mercury". +- */ +- +-/dts-v1/; +- +-#include "intel-ixp42x.dtsi" +-#include +- +-/ { +- model = "Arcom/Eurotech Vulcan"; +- compatible = "arcom,vulcan", "intel,ixp42x"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x4000000>; +- }; +- +- chosen { +- /* CHECKME: using a harddrive at /dev/sda1 as rootfs by default */ +- bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait"; +- stdout-path = "uart0:115200n8"; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- onewire { +- compatible = "w1-gpio"; +- gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- }; +- +- soc { +- bus@c4000000 { +- flash@0,0 { +- compatible = "intel,ixp4xx-flash", "cfi-flash"; +- bank-width = <2>; +- /* +- * 32 MB of Flash in 0x20000 byte blocks +- * mapped in at CS0 and CS1. +- * +- * The documentation mentions the existence +- * of a 16MB version, which we conveniently +- * ignore. Shout if you own one! +- */ +- reg = <0 0x00000000 0x2000000>; +- +- /* Expansion bus settings */ +- intel,ixp4xx-eb-t3 = <3>; +- intel,ixp4xx-eb-byte-access-on-halfword = <1>; +- intel,ixp4xx-eb-write-enable = <1>; +- +- partitions { +- compatible = "redboot-fis"; +- fis-index-block = <0x1ff>; +- }; +- }; +- sram@2,0 { +- /* 256 KB SDRAM memory at CS2 */ +- compatible = "shared-dma-pool"; +- device_type = "memory"; +- reg = <2 0x00000000 0x40000>; +- no-map; +- /* Expansion bus settings */ +- intel,ixp4xx-eb-t3 = <1>; +- intel,ixp4xx-eb-t4 = <2>; +- intel,ixp4xx-eb-ahb-split-transfers = <1>; +- intel,ixp4xx-eb-write-enable = <1>; +- intel,ixp4xx-eb-byte-access = <1>; +- }; +- serial@3,0 { +- /* +- * 8250-compatible Exar XR16L2551 2 x UART +- * +- * CHECKME: if special tweaks are needed, then fix the +- * operating system to handle it. +- */ +- compatible = "exar,xr16l2551", "ns8250"; +- reg = <3 0x00000000 0x10>; +- interrupt-parent = <&gpio0>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- clock-frequency = <1843200>; +- /* Expansion bus settings */ +- intel,ixp4xx-eb-t3 = <3>; +- intel,ixp4xx-eb-cycle-type = <1>; /* Motorola cycles */ +- intel,ixp4xx-eb-write-enable = <1>; +- intel,ixp4xx-eb-byte-access = <1>; +- }; +- gpio1: gpio@4,0 { +- /* +- * MMIO GPIO in one byte +- */ +- compatible = "arcom,vulcan-gpio"; +- reg = <4 0x00000000 0x1>; +- /* Expansion bus settings */ +- intel,ixp4xx-eb-write-enable = <1>; +- intel,ixp4xx-eb-byte-access = <1>; +- }; +- watchdog@5,0 { +- compatible = "maxim,max6369"; +- reg = <5 0x00000000 0x1>; +- /* Expansion bus settings */ +- intel,ixp4xx-eb-write-enable = <1>; +- intel,ixp4xx-eb-byte-access = <1>; +- }; +- }; +- +- pci@c0000000 { +- status = "ok"; +- +- /* +- * Taken from Vulcan PCI boardfile. +- * +- * We have 2 slots (IDSEL) 1 and 2 with one dedicated interrupt +- * per slot. This interrupt is shared (OR:ed) by all four pins. +- */ +- interrupt-map = +- /* IDSEL 1 */ +- <0x0800 0 0 1 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 2 */ +- <0x0800 0 0 2 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 2 */ +- <0x0800 0 0 3 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 2 */ +- <0x0800 0 0 4 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 2 */ +- /* IDSEL 2 */ +- <0x1000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 3 */ +- <0x1000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 3 */ +- <0x1000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 3 */ +- <0x1000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 3 */ +- }; +- +- /* EthB */ +- ethernet@c8009000 { +- status = "ok"; +- queue-rx = <&qmgr 3>; +- queue-txready = <&qmgr 20>; +- phy-mode = "rgmii"; +- phy-handle = <&phy0>; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +- }; +- }; +- +- /* EthC */ +- ethernet@c800a000 { +- status = "ok"; +- queue-rx = <&qmgr 4>; +- queue-txready = <&qmgr 21>; +- phy-mode = "rgmii"; +- phy-handle = <&phy1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp42x-dlink-dsm-g600.dts b/scripts/dtc/include-prefixes/arm/intel-ixp42x-dlink-dsm-g600.dts +deleted file mode 100644 +index 8b32e9f22d81..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp42x-dlink-dsm-g600.dts ++++ /dev/null +@@ -1,145 +0,0 @@ +-// SPDX-License-Identifier: ISC +-/* +- * Device Tree file for D-Link DSM-G600 revision A based on IXP420 +- * NOTE: revision B of this device uses PowerPC and is NOT supported by +- * this device tree. +- * +- * Inspired by the boardfile by Rod Whitby, Tower Technologies, Alessandro Zummo +- * and Michael Westerhof. +- */ +- +-/dts-v1/; +- +-#include "intel-ixp42x.dtsi" +-#include +- +-/ { +- model = "D-Link DSM-G600 rev A"; +- compatible = "dlink,dsm-g600-a", "intel,ixp42x"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { +- /* 64 MB SDRAM */ +- device_type = "memory"; +- reg = <0x00000000 0x4000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait"; +- stdout-path = "uart0:115200n8"; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-power { +- label = "dsmg600:green:power"; +- gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- led-wlan { +- label = "dsmg600:green:wlan"; +- /* CHECKME: flagged as active low in the old board file */ +- gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- /* We don't have WLAN trigger in the kernel (yet) */ +- linux,default-trigger = "netdev"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- button-reset { +- wakeup-source; +- linux,code = ; +- label = "reset"; +- gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio_keys_polled { +- compatible = "gpio-keys-polled"; +- +- /* +- * According to the board file this key cannot handle interrupts and +- * need to be polled. Investigate if this is really the case or if +- * this can be moved adjacent to the ordinary gpio-keys above. +- */ +- button-power { +- wakeup-source; +- linux,code = ; +- label = "power"; +- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- i2c { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio0 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- }; +- +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; +- timeout-ms = <5000>; +- }; +- +- soc { +- bus@c4000000 { +- /* The first 16MB region at CS0 on the expansion bus */ +- flash@0,0 { +- compatible = "intel,ixp4xx-flash", "cfi-flash"; +- bank-width = <2>; +- /* +- * 16 MB of Flash in 128 0x20000 sized blocks +- * mapped in at CS0. +- */ +- reg = <0 0x00000000 0x1000000>; +- +- partitions { +- compatible = "redboot-fis"; +- /* +- * A boot log says the directory is at 0xfe0000 +- * 0x7f * 0x20000 = 0xfe0000 +- */ +- fis-index-block = <0x7f>; +- }; +- }; +- }; +- +- pci@c0000000 { +- status = "ok"; +- +- /* +- * Taken from DSM-G600 PCI boardfile (dsmg600-pci.c) +- * We have slots (IDSEL) 1, 2, 3, 4 and pins 1, 2 and 3. +- * Only slot 3 have three IRQs. +- */ +- interrupt-map = +- /* IDSEL 1 */ +- <0x0800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT E on slot 1 is irq 7 */ +- /* IDSEL 2 */ +- <0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */ +- /* IDSEL 3 */ +- <0x1800 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 10 */ +- <0x1800 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 9 */ +- <0x1800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 8 */ +- /* IDSEL 4 */ +- <0x2000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT F on slot 4 is irq 6 */ +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp42x-freecom-fsg-3.dts b/scripts/dtc/include-prefixes/arm/intel-ixp42x-freecom-fsg-3.dts +deleted file mode 100644 +index 77e78c6dc2cd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp42x-freecom-fsg-3.dts ++++ /dev/null +@@ -1,158 +0,0 @@ +-// SPDX-License-Identifier: ISC +-/* +- * Device Tree file for the Freecom FSG-3 router. +- * This machine is based on IXP425. +- * This device tree is inspired by the board file by Rod Whitby. +- */ +- +-/dts-v1/; +- +-#include "intel-ixp42x.dtsi" +-#include +- +-/ { +- model = "Freecom FSG-3"; +- compatible = "freecom,fsg-3", "intel,ixp42x"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { +- /* 64 MB memory */ +- device_type = "memory"; +- reg = <0x00000000 0x4000000>; +- }; +- +- chosen { +- /* Boot from the first partition on the hard drive */ +- bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait"; +- stdout-path = "uart0:115200n8"; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- button-sync { +- wakeup-source; +- /* Closest approximation of what the key should do */ +- linux,code = ; +- label = "sync"; +- gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; +- }; +- button-reset { +- wakeup-source; +- linux,code = ; +- label = "reset"; +- gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; +- }; +- button-usb { +- wakeup-source; +- /* Unplug USB, closest approximation of what the key should do */ +- linux,code = ; +- label = "usb"; +- gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- i2c { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- hwmon@28 { +- /* +- * Temperature sensor and fan control chip. +- * +- * TODO: create a proper device tree binding for +- * the sensor and temperature zone and create a +- * zone with fan control. +- */ +- compatible = "winbond,w83781d"; +- reg = <0x28>; +- }; +- rtc@6f { +- compatible = "isil,isl1208"; +- reg = <0x6f>; +- }; +- }; +- +- soc { +- bus@c4000000 { +- flash@0,0 { +- compatible = "intel,ixp4xx-flash", "cfi-flash"; +- bank-width = <2>; +- /* Enable writes on the expansion bus */ +- intel,ixp4xx-eb-write-enable = <1>; +- /* 4 MB of Flash mapped in at CS0 */ +- reg = <0 0x00000000 0x400000>; +- +- partitions { +- compatible = "redboot-fis"; +- /* Eraseblock at 0x3e0000 */ +- fis-index-block = <0x1f>; +- }; +- }; +- }; +- +- pci@c0000000 { +- status = "ok"; +- +- /* +- * Written based on the FSG-3 PCI boardfile. +- * We have slots 12, 13 & 14 (IDSEL) with one IRQ each. +- */ +- interrupt-map = +- /* IDSEL 12 */ +- <0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */ +- <0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */ +- <0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */ +- <0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */ +- /* IDSEL 13 */ +- <0x6800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 7 */ +- <0x6800 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 7 */ +- <0x6800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 7 */ +- <0x6800 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 7 */ +- /* IDSEL 14 */ +- <0x7000 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 6 */ +- <0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 6 */ +- <0x7000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 6 */ +- <0x7000 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 6 */ +- }; +- +- /* EthB */ +- ethernet@c8009000 { +- status = "ok"; +- queue-rx = <&qmgr 3>; +- queue-txready = <&qmgr 20>; +- phy-mode = "rgmii"; +- phy-handle = <&phy5>; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy4: ethernet-phy@4 { +- reg = <4>; +- }; +- +- phy5: ethernet-phy@5 { +- reg = <5>; +- }; +- }; +- }; +- +- /* EthC */ +- ethernet@c800a000 { +- status = "ok"; +- queue-rx = <&qmgr 4>; +- queue-txready = <&qmgr 21>; +- phy-mode = "rgmii"; +- phy-handle = <&phy4>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp42x-gateworks-gw2348.dts b/scripts/dtc/include-prefixes/arm/intel-ixp42x-gateworks-gw2348.dts +deleted file mode 100644 +index a20277ff0420..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp42x-gateworks-gw2348.dts ++++ /dev/null +@@ -1,172 +0,0 @@ +-// SPDX-License-Identifier: ISC +-/* +- * Device Tree file for the Gateworks Avila GW2348 board. +- * This machine is based on IXP425. +- */ +- +-/dts-v1/; +- +-#include "intel-ixp42x.dtsi" +-#include +- +-/ { +- model = "Gateworks Avila GW2348"; +- compatible = "gateworks,gw2348", "intel,ixp42x"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x4000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = "uart0:115200n8"; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-user { +- label = "gw2348:green:user"; +- gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- i2c { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- hwmon@28 { +- compatible = "adi,ad7418"; +- reg = <0x28>; +- }; +- rtc: ds1672@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +- eeprom@51 { +- compatible = "atmel,24c08"; +- reg = <0x51>; +- pagesize = <16>; +- size = <1024>; +- read-only; +- }; +- }; +- +- soc { +- bus@c4000000 { +- flash@0,0 { +- compatible = "intel,ixp4xx-flash", "cfi-flash"; +- bank-width = <2>; +- /* Enable writes on the expansion bus */ +- intel,ixp4xx-eb-write-enable = <1>; +- /* 16 MB of Flash mapped in at CS0 */ +- reg = <0 0x00000000 0x1000000>; +- +- partitions { +- compatible = "redboot-fis"; +- /* Eraseblock at 0x0fe0000 */ +- fis-index-block = <0x7f>; +- }; +- }; +- ide@1,0 { +- compatible = "intel,ixp4xx-compact-flash"; +- /* +- * Set up expansion bus config to a really slow timing. +- * The CF driver will dynamically reconfigure these timings +- * depending on selected PIO mode (0-4). +- */ +- intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase +- intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase +- intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase +- intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase +- intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase +- intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type +- intel,ixp4xx-eb-byte-access-on-halfword = <1>; +- intel,ixp4xx-eb-mux-address-and-data = <0>; +- intel,ixp4xx-eb-ahb-split-transfers = <0>; +- intel,ixp4xx-eb-write-enable = <1>; +- intel,ixp4xx-eb-byte-access = <1>; +- /* First register set is CMD second is CTL (notice it uses CS2) */ +- reg = <1 0x00000000 0x1000000>, <2 0x00000000 0x1000000>; +- interrupt-parent = <&gpio0>; +- interrupts = <12 IRQ_TYPE_EDGE_RISING>; +- }; +- /* +- * FIXME: Latch LEDs or extra UARTs at CS4 +- */ +- }; +- +- pci@c0000000 { +- status = "ok"; +- +- /* +- * Taken from Avila PCI boardfile. +- * +- * We have up to 4 slots (IDSEL) with 4 swizzled IRQs. +- */ +- interrupt-map = +- /* IDSEL 1 */ +- <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ +- <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */ +- <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */ +- <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ +- /* IDSEL 2 */ +- <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ +- <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ +- <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */ +- <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */ +- /* IDSEL 3 */ +- <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ +- <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */ +- <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */ +- <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */ +- /* IDSEL 4 */ +- <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */ +- <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */ +- <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */ +- <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */ +- }; +- +- /* EthB */ +- ethernet@c8009000 { +- status = "ok"; +- queue-rx = <&qmgr 3>; +- queue-txready = <&qmgr 20>; +- phy-mode = "rgmii"; +- phy-handle = <&phy0>; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +- }; +- }; +- +- /* EthC */ +- ethernet@c800a000 { +- status = "ok"; +- queue-rx = <&qmgr 4>; +- queue-txready = <&qmgr 21>; +- phy-mode = "rgmii"; +- phy-handle = <&phy1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp42x-iomega-nas100d.dts b/scripts/dtc/include-prefixes/arm/intel-ixp42x-iomega-nas100d.dts +deleted file mode 100644 +index 8c18d802c849..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp42x-iomega-nas100d.dts ++++ /dev/null +@@ -1,146 +0,0 @@ +-// SPDX-License-Identifier: ISC +-/* +- * Device Tree file for Iomega NAS 100D +- */ +- +-/dts-v1/; +- +-#include "intel-ixp42x.dtsi" +-#include +- +-/ { +- model = "Iomega NAS 100D"; +- compatible = "iom,nas-100d", "intel,ixp42x"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { +- /* 64 MB SDRAM */ +- device_type = "memory"; +- reg = <0x00000000 0x4000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait"; +- stdout-path = "uart0:115200n8"; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-wlan { +- label = "nas100d:red:wlan"; +- gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- /* We don't have WLAN trigger in the kernel (yet) */ +- linux,default-trigger = "netdev"; +- }; +- led-disk { +- label = "nas100d:red:disk"; +- gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- linux,default-trigger = "disk-activity"; +- }; +- led-power { +- label = "nas100d:red:power"; +- gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- button-power { +- wakeup-source; +- linux,code = ; +- label = "power"; +- gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; +- }; +- button-reset { +- wakeup-source; +- linux,code = ; +- label = "reset"; +- gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- i2c { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- }; +- +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; +- timeout-ms = <5000>; +- }; +- +- soc { +- bus@c4000000 { +- /* The first 16MB region at CS0 on the expansion bus */ +- flash@0,0 { +- compatible = "intel,ixp4xx-flash", "cfi-flash"; +- bank-width = <2>; +- /* +- * 8 MB of Flash in 0x20000 byte blocks +- * mapped in at CS0. +- */ +- reg = <0 0x00000000 0x800000>; +- +- partitions { +- compatible = "redboot-fis"; +- /* Eraseblock at 0x7e0000 */ +- fis-index-block = <0x3f>; +- }; +- }; +- }; +- +- pci@c0000000 { +- status = "ok"; +- +- /* +- * Taken from NAS 100D PCI boardfile (nas100d-pci.c) +- * We have slots (IDSEL) 1, 2 and 3 and pins 1, 2 and 3. +- */ +- interrupt-map = +- /* IDSEL 1 */ +- <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ +- /* IDSEL 2 */ +- <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ +- /* IDSEL 3 */ +- <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ +- <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */ +- <0x1800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 3 is irq 7 */ +- }; +- +- ethernet@c8009000 { +- status = "ok"; +- queue-rx = <&qmgr 3>; +- queue-txready = <&qmgr 20>; +- phy-mode = "rgmii"; +- phy-handle = <&phy0>; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp42x-ixdp425.dts b/scripts/dtc/include-prefixes/arm/intel-ixp42x-ixdp425.dts +deleted file mode 100644 +index beaadda4685f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp42x-ixdp425.dts ++++ /dev/null +@@ -1,72 +0,0 @@ +-// SPDX-License-Identifier: ISC +-/* +- * Device Tree file for the Intel IXDP425 also known as IXCDP1100 Control Plane +- * processor reference design. +- * +- * This platform has the codename "Richfield". +- * +- * This machine is based on a 533 MHz IXP425. +- */ +- +-/dts-v1/; +- +-#include "intel-ixp42x.dtsi" +-#include "intel-ixp4xx-reference-design.dtsi" +-#include +- +-/ { +- model = "Intel IXDP425/IXCDP1100 Richfield Reference Design"; +- compatible = "intel,ixdp425", "intel,ixp42x"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- soc { +- bus@c4000000 { +- flash@0,0 { +- compatible = "intel,ixp4xx-flash", "cfi-flash"; +- bank-width = <2>; +- /* Enable writes on the expansion bus */ +- intel,ixp4xx-eb-write-enable = <1>; +- /* 16 MB of Flash mapped in at CS0 */ +- reg = <0 0x00000000 0x1000000>; +- +- partitions { +- compatible = "redboot-fis"; +- /* Eraseblock at 0x0fe0000 */ +- fis-index-block = <0x7f>; +- }; +- }; +- }; +- +- /* EthB */ +- ethernet@c8009000 { +- status = "ok"; +- queue-rx = <&qmgr 3>; +- queue-txready = <&qmgr 20>; +- phy-mode = "rgmii"; +- phy-handle = <&phy0>; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +- }; +- }; +- +- /* EthC */ +- ethernet@c800a000 { +- status = "ok"; +- queue-rx = <&qmgr 4>; +- queue-txready = <&qmgr 21>; +- phy-mode = "rgmii"; +- phy-handle = <&phy1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp42x-ixdpg425.dts b/scripts/dtc/include-prefixes/arm/intel-ixp42x-ixdpg425.dts +deleted file mode 100644 +index 002a8705abc9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp42x-ixdpg425.dts ++++ /dev/null +@@ -1,125 +0,0 @@ +-// SPDX-License-Identifier: ISC +-/* +- * Device Tree file for the Intel IXDPG425 reference design. +- * Derived from boardfiles written by MontaVista software. +- * Ethernet set-up from OpenWrt. +- * +- * The device has 4 x FXS RJ11 ports for analog phones for +- * internet telephony. (Not supported yet.) +- * +- * The device has 9 status LEDs we do not support yet. +- * +- * This device is very similar to ADI engingeering Coyote. +- */ +- +-/dts-v1/; +- +-#include "intel-ixp42x.dtsi" +-#include +- +-/ { +- model = "Intel IXDPG425 reference design"; +- compatible = "intel,ixdpg425", "intel,ixp42x"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { +- /* 32 MB SDRAM */ +- device_type = "memory"; +- reg = <0x00000000 0x02000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait"; +- stdout-path = "uart0:115200n8"; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- soc { +- bus@c4000000 { +- flash@0,0 { +- compatible = "intel,ixp4xx-flash", "cfi-flash"; +- bank-width = <2>; +- /* +- * CHECKME: the product brief says 16MB in a flash +- * socket. +- */ +- reg = <0 0x00000000 0x1000000>; +- +- /* Configure expansion bus to allow writes */ +- intel,ixp4xx-eb-write-enable = <1>; +- +- partitions { +- compatible = "redboot-fis"; +- /* CHECKME: guess this is Redboot FIS */ +- fis-index-block = <0x7f>; +- }; +- }; +- }; +- +- pci@c0000000 { +- status = "ok"; +- +- /* +- * Taken from IXDPG425 PCI boardfile. +- * We have slots (IDSEL) 12, 13 and 14 with one assigned IRQ +- * for 12 & 13 and one for 14. +- */ +- interrupt-map = +- /* IDSEL 12 */ +- <0x6000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 7 */ +- <0x6000 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 7 */ +- <0x6000 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 7 */ +- <0x6000 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 7 */ +- /* IDSEL 13 */ +- <0x6800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 7 */ +- <0x6800 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 7 */ +- <0x6800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 7 */ +- <0x6800 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 7 */ +- /* IDSEL 14 */ +- <0x7000 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 6 */ +- <0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 6 */ +- <0x7000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 6 */ +- <0x7000 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 6 */ +- }; +- +- /* +- * CHECKME: this ethernet setup seems dubious. Photos of the board shows some kind +- * of Realtek DSA switch on the board. +- */ +- +- /* EthB */ +- ethernet@c8009000 { +- status = "ok"; +- queue-rx = <&qmgr 3>; +- queue-txready = <&qmgr 20>; +- phy-mode = "rgmii"; +- phy-handle = <&phy5>; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy4: ethernet-phy@4 { +- reg = <4>; +- }; +- +- phy5: ethernet-phy@5 { +- reg = <5>; +- }; +- }; +- }; +- +- /* EthC */ +- ethernet@c800a000 { +- status = "ok"; +- queue-rx = <&qmgr 4>; +- queue-txready = <&qmgr 21>; +- phy-mode = "rgmii"; +- phy-handle = <&phy4>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp42x-linksys-nslu2.dts b/scripts/dtc/include-prefixes/arm/intel-ixp42x-linksys-nslu2.dts +deleted file mode 100644 +index e3a32b08d167..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp42x-linksys-nslu2.dts ++++ /dev/null +@@ -1,160 +0,0 @@ +-// SPDX-License-Identifier: ISC +-/* +- * Device Tree file for Linksys NSLU2 +- */ +- +-/dts-v1/; +- +-#include "intel-ixp42x.dtsi" +-#include +- +-/ { +- model = "Linksys NSLU2 (Network Storage Link for USB 2.0 Disk Drives)"; +- compatible = "linksys,nslu2", "intel,ixp42x"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { +- /* 32 MB SDRAM */ +- device_type = "memory"; +- reg = <0x00000000 0x2000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait"; +- stdout-path = "uart0:115200n8"; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-status { +- label = "nslu2:red:status"; +- gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- led-ready { +- label = "nslu2:green:ready"; +- gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- led-disk-1 { +- label = "nslu2:green:disk-1"; +- gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- led-disk-2 { +- label = "nslu2:green:disk-2"; +- gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- button-power { +- wakeup-source; +- linux,code = ; +- label = "power"; +- gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; +- }; +- button-reset { +- wakeup-source; +- linux,code = ; +- label = "reset"; +- gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- i2c { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtc@6f { +- compatible = "xicor,x1205"; +- reg = <0x6f>; +- }; +- }; +- +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; +- timeout-ms = <5000>; +- }; +- +- gpio-beeper { +- compatible = "gpio-beeper"; +- gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; +- }; +- +- soc { +- bus@c4000000 { +- /* The first 16MB region at CS0 on the expansion bus */ +- flash@0,0 { +- compatible = "intel,ixp4xx-flash", "cfi-flash"; +- bank-width = <2>; +- /* +- * 8 MB of Flash in 0x20000 byte blocks +- * mapped in at CS0. +- */ +- reg = <0 0x00000000 0x800000>; +- +- partitions { +- compatible = "redboot-fis"; +- /* Eraseblock at 0x7e0000 */ +- fis-index-block = <0x3f>; +- }; +- }; +- }; +- +- pci@c0000000 { +- status = "ok"; +- +- /* +- * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant +- * We have slots (IDSEL) 1, 2 and 3. +- */ +- interrupt-map = +- /* IDSEL 1 */ +- <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ +- <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */ +- <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */ +- <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ +- /* IDSEL 2 */ +- <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ +- <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ +- <0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */ +- <0x1000 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 8 */ +- /* IDSEL 3 */ +- <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ +- <0x1800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */ +- <0x1800 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */ +- <0x1800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 8 */ +- }; +- +- ethernet@c8009000 { +- status = "ok"; +- queue-rx = <&qmgr 3>; +- queue-txready = <&qmgr 20>; +- phy-mode = "rgmii"; +- phy-handle = <&phy1>; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp42x-linksys-wrv54g.dts b/scripts/dtc/include-prefixes/arm/intel-ixp42x-linksys-wrv54g.dts +deleted file mode 100644 +index 6b28dda747fd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp42x-linksys-wrv54g.dts ++++ /dev/null +@@ -1,173 +0,0 @@ +-// SPDX-License-Identifier: ISC +-/* +- * Device Tree file for the Linksys WRV54G router +- * Also known as Gemtek GTWX5715 +- * Based on a board file by George T. Joseph and other patches. +- * This machine is based on IXP425. +- */ +- +-/dts-v1/; +- +-#include "intel-ixp42x.dtsi" +-#include +- +-/ { +- model = "Linksys WRV54G / Gemtek GTWX5715"; +- compatible = "linksys,wrv54g", "gemtek,gtwx5715", "intel,ixp42x"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { +- /* 32 MB memory */ +- device_type = "memory"; +- reg = <0x00000000 0x2000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = "uart1:115200n8"; +- }; +- +- aliases { +- /* UART2 is the primary console */ +- serial0 = &uart1; +- serial1 = &uart0; +- }; +- +- /* There is an unpopulated LED slot (3) connected to GPIO 8 */ +- leds { +- compatible = "gpio-leds"; +- led-power { +- label = "wrv54g:yellow:power"; +- gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- led-wireless { +- label = "wrv54g:yellow:wireless"; +- gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- led-internet { +- label = "wrv54g:yellow:internet"; +- gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- led-dmz { +- label = "wrv54g:green:dmz"; +- gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- }; +- +- /* This set-up comes from an OpenWrt patch */ +- spi { +- compatible = "spi-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- sck-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; +- miso-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; +- mosi-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; +- num-chipselects = <1>; +- +- switch@0 { +- compatible = "micrel,ks8995"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- }; +- }; +- +- soc { +- bus@c4000000 { +- flash@0,0 { +- compatible = "intel,ixp4xx-flash", "cfi-flash"; +- bank-width = <2>; +- /* Enable writes on the expansion bus */ +- intel,ixp4xx-eb-write-enable = <1>; +- /* 8 MB of Flash mapped in at CS0 */ +- reg = <0 0x00000000 0x00800000>; +- +- partitions { +- compatible = "fixed-partitions"; +- /* +- * Partition info from a boot log +- * CHECKME: not using redboot? FIS index 0x3f @7e00000? +- */ +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "boot"; +- reg = <0x0 0x140000>; +- read-only; +- }; +- partition@140000 { +- label = "linux"; +- reg = <0x140000 0x100000>; +- read-only; +- }; +- partition@240000 { +- label = "root"; +- reg = <0x240000 0x480000>; +- read-write; +- }; +- }; +- }; +- }; +- +- pci@c0000000 { +- status = "ok"; +- +- /* +- * We have up to 2 slots (IDSEL) with 2 swizzled IRQs. +- * Derived from the GTWX5715 PCI boardfile. +- */ +- interrupt-map = +- /* IDSEL 0 */ +- <0x0000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 0 is irq 10 */ +- <0x0000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 0 is irq 11 */ +- /* IDSEL 1 */ +- <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ +- <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT B on slot 1 is irq 10 */ +- }; +- +- /* +- * EthB - connected to the KS8995 switch ports 1-4 +- * FIXME: the boardfile defines .phy_mask = 0x1e for this port to enable output to +- * all four switch ports, also using an out of tree multiphy patch. +- * Do we need a new binding and property for this? +- */ +- ethernet@c8009000 { +- status = "ok"; +- queue-rx = <&qmgr 3>; +- queue-txready = <&qmgr 20>; +- phy-mode = "rgmii"; +- phy-handle = <&phy4>; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Should be ports 1-4 on the KS8995 switch */ +- phy4: ethernet-phy@4 { +- reg = <4>; +- }; +- +- /* Should be port 5 on the KS8995 switch */ +- phy5: ethernet-phy@5 { +- reg = <5>; +- }; +- }; +- }; +- +- /* EthC - connected to KS8995 switch port 5 */ +- ethernet@c800a000 { +- status = "ok"; +- queue-rx = <&qmgr 4>; +- queue-txready = <&qmgr 21>; +- phy-mode = "rgmii"; +- phy-handle = <&phy5>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp42x-netgear-wg302v2.dts b/scripts/dtc/include-prefixes/arm/intel-ixp42x-netgear-wg302v2.dts +deleted file mode 100644 +index 04a0f7138967..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp42x-netgear-wg302v2.dts ++++ /dev/null +@@ -1,95 +0,0 @@ +-// SPDX-License-Identifier: ISC +-/* +- * Device Tree file for Netgear WG302v2 based on IXP422BB +- * Derived from boardfiles written by Imre Kaloz +- */ +- +-/dts-v1/; +- +-#include "intel-ixp42x.dtsi" +-#include +- +-/ { +- model = "Netgear WG302 v2"; +- compatible = "netgear,wg302v2", "intel,ixp42x"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { +- /* 16 MB SDRAM according to OpenWrt database */ +- device_type = "memory"; +- reg = <0x00000000 0x01000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait"; +- stdout-path = "uart1:115200n8"; +- }; +- +- aliases { +- /* These are switched around */ +- serial0 = &uart1; +- serial1 = &uart0; +- }; +- +- soc { +- bus@c4000000 { +- flash@0,0 { +- compatible = "intel,ixp4xx-flash", "cfi-flash"; +- bank-width = <2>; +- /* +- * 32 MB of Flash in 128 0x20000 sized blocks +- * mapped in at CS0 and CS1 +- */ +- reg = <0 0x00000000 0x2000000>; +- +- /* Configure expansion bus to allow writes */ +- intel,ixp4xx-eb-write-enable = <1>; +- +- partitions { +- compatible = "redboot-fis"; +- /* CHECKME: guess this is Redboot FIS */ +- fis-index-block = <0xff>; +- }; +- }; +- }; +- +- pci@c0000000 { +- status = "ok"; +- +- /* +- * Taken from WG302 v2 PCI boardfile (wg302v2-pci.c) +- * We have slots (IDSEL) 1 and 2 with one assigned IRQ +- * each handling all IRQs. +- */ +- interrupt-map = +- /* IDSEL 1 */ +- <0x0800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 8 */ +- <0x0800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 8 */ +- <0x0800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 8 */ +- <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ +- /* IDSEL 2 */ +- <0x1000 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 9 */ +- <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ +- <0x1000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 9 */ +- <0x1000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 9 */ +- }; +- +- ethernet@c8009000 { +- status = "ok"; +- queue-rx = <&qmgr 3>; +- queue-txready = <&qmgr 20>; +- phy-mode = "rgmii"; +- phy-handle = <&phy8>; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy8: ethernet-phy@8 { +- reg = <8>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp42x-welltech-epbx100.dts b/scripts/dtc/include-prefixes/arm/intel-ixp42x-welltech-epbx100.dts +deleted file mode 100644 +index f5846a50e4d4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp42x-welltech-epbx100.dts ++++ /dev/null +@@ -1,80 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2021 Corentin Labbe +- */ +- +-/dts-v1/; +- +-#include "intel-ixp42x.dtsi" +- +-/ { +- model = "Welltech EPBX100"; +- compatible = "welltech,epbx100", "intel,ixp42x"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { +- /* 64 MB SDRAM */ +- device_type = "memory"; +- reg = <0x00000000 0x4000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 root=/dev/ram0 initrd=0x00800000,9M"; +- stdout-path = "uart0:115200n8"; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- soc { +- bus@c4000000 { +- flash@0,0 { +- compatible = "intel,ixp4xx-flash", "cfi-flash"; +- bank-width = <2>; +- /* +- * 16 MB of Flash +- */ +- reg = <0 0x00000000 0x1000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "RedBoot"; +- reg = <0x00000000 0x00080000>; +- read-only; +- }; +- partition@80000 { +- label = "zImage"; +- reg = <0x00080000 0x00100000>; +- read-only; +- }; +- partition@180000 { +- label = "ramdisk"; +- reg = <0x00180000 0x00300000>; +- read-only; +- }; +- partition@480000 { +- label = "User"; +- reg = <0x00480000 0x00b60000>; +- read-only; +- }; +- partition@fe0000 { +- label = "FIS directory"; +- reg = <0x00fe0000 0x001f000>; +- read-only; +- }; +- partition@fff000 { +- label = "RedBoot config"; +- reg = <0x00fff000 0x0001000>; +- read-only; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp42x.dtsi b/scripts/dtc/include-prefixes/arm/intel-ixp42x.dtsi +deleted file mode 100644 +index d0e0f8afb7c9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp42x.dtsi ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: ISC +-/* +- * Device Tree file for Intel XScale Network Processors +- * in the IXP 42x series. This series has 32 interrupts. +- */ +-#include "intel-ixp4xx.dtsi" +- +-/ { +- soc { +- bus@c4000000 { +- compatible = "intel,ixp42x-expansion-bus-controller", "syscon"; +- reg = <0xc4000000 0x28>; +- }; +- +- pci@c0000000 { +- compatible = "intel,ixp42x-pci"; +- }; +- +- interrupt-controller@c8003000 { +- compatible = "intel,ixp42x-interrupt"; +- }; +- +- /* +- * This is the USB Device Mode (UDC) controller, which is used +- * to present the IXP4xx as a device on a USB bus. +- */ +- usb@c800b000 { +- compatible = "intel,ixp4xx-udc"; +- reg = <0xc800b000 0x1000>; +- interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp43x-gateworks-gw2358.dts b/scripts/dtc/include-prefixes/arm/intel-ixp43x-gateworks-gw2358.dts +deleted file mode 100644 +index 84e6aec8e665..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp43x-gateworks-gw2358.dts ++++ /dev/null +@@ -1,197 +0,0 @@ +-// SPDX-License-Identifier: ISC +-/* +- * Device Tree file for Gateworks IXP43x-based Cambria GW2358 +- */ +- +-/dts-v1/; +- +-#include "intel-ixp43x.dtsi" +- +-/ { +- model = "Gateworks Cambria GW2358"; +- compatible = "gateworks,gw2358", "intel,ixp43x"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { +- /* 128 MB SDRAM */ +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait"; +- stdout-path = "uart0:115200n8"; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-user { +- label = "gw2358:green:LED"; +- gpios = <&pld1 0 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- +- i2c { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- hwmon@28 { +- compatible = "adi,ad7418"; +- reg = <0x28>; +- }; +- rtc: ds1672@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +- eeprom@51 { +- compatible = "atmel,24c08"; +- reg = <0x51>; +- pagesize = <16>; +- size = <1024>; +- read-only; +- }; +- pld0: pld@56 { +- compatible = "gateworks,pld-gpio"; +- reg = <0x56>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- /* This PLD just handles the LED and user button */ +- pld1: pld@57 { +- compatible = "gateworks,pld-gpio"; +- reg = <0x57>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +- +- soc { +- bus@c4000000 { +- flash@0,0 { +- compatible = "intel,ixp4xx-flash", "cfi-flash"; +- bank-width = <2>; +- /* Enable writes on the expansion bus */ +- intel,ixp4xx-eb-write-enable = <1>; +- /* +- * 32 MB of Flash in 0x20000 byte blocks +- * mapped in at CS0 and CS1 +- */ +- reg = <0 0x00000000 0x2000000>; +- +- partitions { +- compatible = "redboot-fis"; +- /* Eraseblock at 0x1fe0000 */ +- fis-index-block = <0xff>; +- }; +- }; +- ide@3,0 { +- compatible = "intel,ixp4xx-compact-flash"; +- /* +- * Set up expansion bus config to a really slow timing. +- * The CF driver will dynamically reconfigure these timings +- * depending on selected PIO mode (0-4). +- */ +- intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase +- intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase +- intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase +- intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase +- intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase +- intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type +- intel,ixp4xx-eb-byte-access-on-halfword = <1>; +- intel,ixp4xx-eb-mux-address-and-data = <0>; +- intel,ixp4xx-eb-ahb-split-transfers = <0>; +- intel,ixp4xx-eb-write-enable = <1>; +- intel,ixp4xx-eb-byte-access = <1>; +- /* First register set is CMD second is CTL */ +- reg = <3 0xe00000 0x40000>, <3 0xe40000 0x40000>; +- interrupt-parent = <&gpio0>; +- interrupts = <12 IRQ_TYPE_EDGE_RISING>; +- }; +- }; +- +- pci@c0000000 { +- status = "ok"; +- +- /* +- * In the boardfile for the Cambria from OpenWRT the interrupts +- * are assigned one per IDSEL, so all 4 interrupts from IDSEL +- * 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2 +- * connected to IRQ 10 etc. I find this highly unlikely so I +- * have instead assumed that they are rotated (swizzled) like +- * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc. +- */ +- interrupt-map = +- /* IDSEL 1 */ +- <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ +- <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */ +- <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */ +- <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ +- /* IDSEL 2 */ +- <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ +- <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ +- <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */ +- <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */ +- /* IDSEL 3 */ +- <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ +- <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */ +- <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */ +- <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */ +- /* IDSEL 4 */ +- <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */ +- <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */ +- <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */ +- <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 9 */ +- /* IDSEL 6 */ +- <0x3000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 10 */ +- <0x3000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 9 */ +- <0x3000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 8 */ +- <0x3000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 11 */ +- /* IDSEL 15 */ +- <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */ +- <0x7800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */ +- <0x7800 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */ +- <0x7800 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 9 */ +- }; +- +- ethernet@c800a000 { +- status = "ok"; +- queue-rx = <&qmgr 4>; +- queue-txready = <&qmgr 21>; +- phy-mode = "rgmii"; +- phy-handle = <&phy1>; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +- +- phy2: ethernet-phy@2 { +- reg = <2>; +- }; +- }; +- }; +- +- ethernet@c800c000 { +- status = "ok"; +- queue-rx = <&qmgr 2>; +- queue-txready = <&qmgr 19>; +- phy-mode = "rgmii"; +- phy-handle = <&phy2>; +- intel,npe-handle = <&npe 0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp43x-kixrp435.dts b/scripts/dtc/include-prefixes/arm/intel-ixp43x-kixrp435.dts +deleted file mode 100644 +index 3d7cfa1a5ed4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp43x-kixrp435.dts ++++ /dev/null +@@ -1,68 +0,0 @@ +-// SPDX-License-Identifier: ISC +-/* +- * Device Tree file for the Intel KIXRP435 Control Plane +- * processor reference design. +- */ +- +-/dts-v1/; +- +-#include "intel-ixp43x.dtsi" +-#include "intel-ixp4xx-reference-design.dtsi" +-#include +- +-/ { +- model = "Intel KIXRP435 Reference Design"; +- compatible = "intel,kixrp435", "intel,ixp43x"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- soc { +- bus@c4000000 { +- flash@0,0 { +- compatible = "intel,ixp4xx-flash", "cfi-flash"; +- bank-width = <2>; +- /* Enable writes on the expansion bus */ +- intel,ixp4xx-eb-write-enable = <1>; +- /* 16 MB of Flash mapped in at CS0 */ +- reg = <0 0x00000000 0x1000000>; +- +- partitions { +- compatible = "redboot-fis"; +- /* Eraseblock at 0x0fe0000 */ +- fis-index-block = <0x7f>; +- }; +- }; +- }; +- +- /* CHECKME: ethernet set-up taken from Gateworks Cambria */ +- ethernet@c800a000 { +- status = "ok"; +- queue-rx = <&qmgr 4>; +- queue-txready = <&qmgr 21>; +- phy-mode = "rgmii"; +- phy-handle = <&phy1>; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +- +- phy2: ethernet-phy@2 { +- reg = <2>; +- }; +- }; +- }; +- +- ethernet@c800c000 { +- status = "ok"; +- queue-rx = <&qmgr 2>; +- queue-txready = <&qmgr 19>; +- phy-mode = "rgmii"; +- phy-handle = <&phy2>; +- intel,npe-handle = <&npe 0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp43x.dtsi b/scripts/dtc/include-prefixes/arm/intel-ixp43x.dtsi +deleted file mode 100644 +index 60bf9903e0f8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp43x.dtsi ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: ISC +-/* +- * Device Tree file for Intel XScale Network Processors +- * in the IXP 43x series. This series has 64 interrupts and adds a few more +- * peripherals over the 42x series. +- */ +-#include "intel-ixp4xx.dtsi" +- +-/ { +- soc { +- bus@c4000000 { +- compatible = "intel,ixp43x-expansion-bus-controller", "syscon"; +- /* Uses at least up to 0x230 */ +- reg = <0xc4000000 0x1000>; +- }; +- +- pci@c0000000 { +- compatible = "intel,ixp43x-pci"; +- }; +- +- interrupt-controller@c8003000 { +- compatible = "intel,ixp43x-interrupt"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp45x-ixp46x.dtsi b/scripts/dtc/include-prefixes/arm/intel-ixp45x-ixp46x.dtsi +deleted file mode 100644 +index b6ff614dadc6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp45x-ixp46x.dtsi ++++ /dev/null +@@ -1,78 +0,0 @@ +-// SPDX-License-Identifier: ISC +-/* +- * Device Tree file for Intel XScale Network Processors +- * in the IXP45x and IXP46x series. This series has 64 interrupts and adds a +- * few more peripherals over the 42x and 43x series so this extends the +- * basic IXP4xx DTSI. +- */ +-#include "intel-ixp4xx.dtsi" +- +-/ { +- soc { +- bus@c4000000 { +- compatible = "intel,ixp46x-expansion-bus-controller", "syscon"; +- /* Uses at least up to 0x124 */ +- reg = <0xc4000000 0x1000>; +- }; +- +- rng@70002100 { +- compatible = "intel,ixp46x-rng"; +- reg = <0x70002100 4>; +- }; +- +- interrupt-controller@c8003000 { +- compatible = "intel,ixp43x-interrupt"; +- }; +- +- /* +- * This is the USB Device Mode (UDC) controller, which is used +- * to present the IXP4xx as a device on a USB bus. +- */ +- usb@c800b000 { +- compatible = "intel,ixp4xx-udc"; +- reg = <0xc800b000 0x1000>; +- interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +- +- i2c@c8011000 { +- compatible = "intel,ixp4xx-i2c"; +- reg = <0xc8011000 0x18>; +- interrupts = <33 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +- +- /* This is known as EthB1 */ +- ethernet@c800d000 { +- compatible = "intel,ixp4xx-ethernet"; +- reg = <0xc800d000 0x1000>; +- status = "disabled"; +- intel,npe = <1>; +- /* Dummy values that depend on firmware */ +- queue-rx = <&qmgr 0>; +- queue-txready = <&qmgr 0>; +- }; +- +- /* This is known as EthB2 */ +- ethernet@c800e000 { +- compatible = "intel,ixp4xx-ethernet"; +- reg = <0xc800e000 0x1000>; +- status = "disabled"; +- intel,npe = <2>; +- /* Dummy values that depend on firmware */ +- queue-rx = <&qmgr 0>; +- queue-txready = <&qmgr 0>; +- }; +- +- /* This is known as EthB3 */ +- ethernet@c800f000 { +- compatible = "intel,ixp4xx-ethernet"; +- reg = <0xc800f000 0x1000>; +- status = "disabled"; +- intel,npe = <3>; +- /* Dummy values that depend on firmware */ +- queue-rx = <&qmgr 0>; +- queue-txready = <&qmgr 0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp46x-ixdp465.dts b/scripts/dtc/include-prefixes/arm/intel-ixp46x-ixdp465.dts +deleted file mode 100644 +index a062cd1a6588..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp46x-ixdp465.dts ++++ /dev/null +@@ -1,38 +0,0 @@ +-// SPDX-License-Identifier: ISC +-/* +- * Device Tree file for the Intel IXDP465 Control Plane processor reference +- * design, codename "BMP". +- */ +- +-/dts-v1/; +- +-#include "intel-ixp45x-ixp46x.dtsi" +-#include "intel-ixp4xx-reference-design.dtsi" +-#include +- +-/ { +- model = "Intel IXDP465 BMP Reference Design"; +- compatible = "intel,ixdp465", "intel,ixp46x"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- soc { +- bus@c4000000 { +- flash@0,0 { +- compatible = "intel,ixp4xx-flash", "cfi-flash"; +- bank-width = <2>; +- /* Enable writes on the expansion bus */ +- intel,ixp4xx-eb-write-enable = <1>; +- /* 32 MB of Flash mapped in at CS0 and CS1 */ +- reg = <0 0x00000000 0x2000000>; +- +- partitions { +- compatible = "redboot-fis"; +- /* Eraseblock at 0x1fe0000 */ +- fis-index-block = <0xff>; +- }; +- }; +- }; +- /* TODO: configure ethernet etc */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp4xx-reference-design.dtsi b/scripts/dtc/include-prefixes/arm/intel-ixp4xx-reference-design.dtsi +deleted file mode 100644 +index c1d9c49982b3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp4xx-reference-design.dtsi ++++ /dev/null +@@ -1,132 +0,0 @@ +-// SPDX-License-Identifier: ISC +-/* +- * Device Tree include file for Intel reference designs for the +- * XScale Network Processors in the IXP 4xx series. Common device +- * set-up for IXDP425, IXCDP1100, KIXRP435 and IXDP465. +- */ +- +-/ { +- memory@0 { +- /* +- * The board supports up to 256 MB of memory. Here we put in +- * 64 MB and this may be modified by the boot loader. +- */ +- device_type = "memory"; +- reg = <0x00000000 0x4000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = "uart0:115200n8"; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- i2c { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@50 { +- /* +- * Philips PCF8582C-2T/03 512byte I2C EEPROM +- * should behave like an Atmel 24c04. +- */ +- compatible = "atmel,24c04"; +- reg = <0x50>; +- pagesize = <16>; +- size = <512>; +- read-only; +- }; +- }; +- +- soc { +- bus@c4000000 { +- /* Flash memory defined per-variant */ +- nand-controller@3,0 { +- /* Some designs have a NAND on CS3 enable it here if present */ +- status = "disabled"; +- +- /* +- * gen_nand needs to be extended and documented to get +- * command byte = 1 and address byte = 2 from the device +- * tree. +- */ +- compatible = "gen_nand"; +- +- /* Expansion bus set-up */ +- intel,ixp4xx-eb-t1 = <0>; +- intel,ixp4xx-eb-t2 = <0>; +- intel,ixp4xx-eb-t3 = <1>; // 1 cycle extra strobe phase +- intel,ixp4xx-eb-t4 = <0>; +- intel,ixp4xx-eb-t5 = <0>; +- intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type +- intel,ixp4xx-eb-byte-access-on-halfword = <0>; +- intel,ixp4xx-eb-mux-address-and-data = <0>; +- intel,ixp4xx-eb-ahb-split-transfers = <0>; +- intel,ixp4xx-eb-write-enable = <1>; +- intel,ixp4xx-eb-byte-access = <1>; +- +- /* 512 bytes memory window */ +- reg = <3 0x00000000 0x200>; +- nand-on-flash-bbt; +- nand-ecc-mode = "soft_bch"; +- nand-ecc-step-size = <512>; +- nand-ecc-strength = <4>; +- nce-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* NCE */ +- +- label = "ixp400 NAND"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- fs@0 { +- label = "ixp400 NAND FS 0"; +- reg = <0x0 0x800000>; +- }; +- fs@800000 { +- label = "ixp400 NAND FS 1"; +- reg = <0x800000 0x0>; +- }; +- }; +- }; +- }; +- +- pci@c0000000 { +- status = "ok"; +- +- /* +- * Taken from IXDP425 PCI boardfile. +- * PCI slots on the BIXMB425BD base card. +- * We have up to 4 slots (IDSEL) with 4 swizzled IRQs. +- */ +- interrupt-map = +- /* IDSEL 1 */ +- <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ +- <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */ +- <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */ +- <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ +- /* IDSEL 2 */ +- <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ +- <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ +- <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */ +- <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */ +- /* IDSEL 3 */ +- <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ +- <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */ +- <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */ +- <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */ +- /* IDSEL 4 */ +- <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */ +- <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */ +- <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */ +- <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */ +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/intel-ixp4xx.dtsi b/scripts/dtc/include-prefixes/arm/intel-ixp4xx.dtsi +deleted file mode 100644 +index e5af2d463074..000000000000 +--- a/scripts/dtc/include-prefixes/arm/intel-ixp4xx.dtsi ++++ /dev/null +@@ -1,187 +0,0 @@ +-// SPDX-License-Identifier: ISC +-/* +- * Device Tree file for Intel XScale Network Processors +- * in the IXP 4xx series. +- */ +-#include +-#include +- +-/ { +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "simple-bus"; +- interrupt-parent = <&intcon>; +- +- /* +- * The IXP4xx expansion bus is a set of up to 7 each up to 16MB +- * windows in the 256MB space from 0x50000000 to 0x5fffffff. +- */ +- bus@c4000000 { +- /* compatible and reg filled in by per-soc device tree */ +- native-endian; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0x0 0x50000000 0x01000000>, +- <1 0x0 0x51000000 0x01000000>, +- <2 0x0 0x52000000 0x01000000>, +- <3 0x0 0x53000000 0x01000000>, +- <4 0x0 0x54000000 0x01000000>, +- <5 0x0 0x55000000 0x01000000>, +- <6 0x0 0x56000000 0x01000000>, +- <7 0x0 0x57000000 0x01000000>; +- dma-ranges = <0 0x0 0x50000000 0x01000000>, +- <1 0x0 0x51000000 0x01000000>, +- <2 0x0 0x52000000 0x01000000>, +- <3 0x0 0x53000000 0x01000000>, +- <4 0x0 0x54000000 0x01000000>, +- <5 0x0 0x55000000 0x01000000>, +- <6 0x0 0x56000000 0x01000000>, +- <7 0x0 0x57000000 0x01000000>; +- }; +- +- qmgr: queue-manager@60000000 { +- compatible = "intel,ixp4xx-ahb-queue-manager"; +- reg = <0x60000000 0x4000>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- pci@c0000000 { +- /* compatible filled in by per-soc device tree */ +- reg = <0xc0000000 0x1000>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, +- <9 IRQ_TYPE_LEVEL_HIGH>, +- <10 IRQ_TYPE_LEVEL_HIGH>; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- bus-range = <0x00 0xff>; +- status = "disabled"; +- +- ranges = +- /* +- * 64MB 32bit non-prefetchable memory 0x48000000-0x4bffffff +- * done in 4 chunks of 16MB each. +- */ +- <0x02000000 0 0x48000000 0x48000000 0 0x04000000>, +- /* 64KB I/O space at 0x4c000000 */ +- <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>; +- +- /* +- * This needs to map to the start of physical memory so +- * PCI devices can see all (hopefully) memory. This is done +- * using 4 1:1 16MB windows, so the RAM should not be more than +- * 64 MB for this to work. If your memory is anywhere else +- * than at 0x0 you need to alter this. +- */ +- dma-ranges = +- <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0xf800 0 0 7>; +- /* Each unique DTS using PCI must specify the swizzling */ +- }; +- +- uart0: serial@c8000000 { +- compatible = "intel,xscale-uart"; +- reg = <0xc8000000 0x1000>; +- /* +- * The reg-offset and reg-shift is a side effect +- * of running the platform in big endian mode. +- */ +- reg-offset = <3>; +- reg-shift = <2>; +- interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; +- clock-frequency = <14745600>; +- no-loopback-test; +- }; +- +- uart1: serial@c8001000 { +- compatible = "intel,xscale-uart"; +- reg = <0xc8001000 0x1000>; +- /* +- * The reg-offset and reg-shift is a side effect +- * of running the platform in big endian mode. +- */ +- reg-offset = <3>; +- reg-shift = <2>; +- interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; +- clock-frequency = <14745600>; +- no-loopback-test; +- }; +- +- gpio0: gpio@c8004000 { +- compatible = "intel,ixp4xx-gpio"; +- reg = <0xc8004000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- intcon: interrupt-controller@c8003000 { +- /* +- * Note: no compatible string. The subvariant of the +- * chip needs to define what version it is. The +- * location of the interrupt controller is fixed in +- * memory across all variants. +- */ +- reg = <0xc8003000 0x100>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- timer@c8005000 { +- compatible = "intel,ixp4xx-timer"; +- reg = <0xc8005000 0x100>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- npe: npe@c8006000 { +- compatible = "intel,ixp4xx-network-processing-engine"; +- reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; +- +- /* NPE-C contains a crypto accelerator */ +- crypto { +- compatible = "intel,ixp4xx-crypto"; +- intel,npe-handle = <&npe 2>; +- queue-rx = <&qmgr 30>; +- queue-txready = <&qmgr 29>; +- }; +- }; +- +- /* This is known as EthB */ +- ethernet@c8009000 { +- compatible = "intel,ixp4xx-ethernet"; +- reg = <0xc8009000 0x1000>; +- status = "disabled"; +- /* Dummy values that depend on firmware */ +- queue-rx = <&qmgr 3>; +- queue-txready = <&qmgr 20>; +- intel,npe-handle = <&npe 1>; +- }; +- +- /* This is known as EthC */ +- ethernet@c800a000 { +- compatible = "intel,ixp4xx-ethernet"; +- reg = <0xc800a000 0x1000>; +- status = "disabled"; +- /* Dummy values that depend on firmware */ +- queue-rx = <&qmgr 0>; +- queue-txready = <&qmgr 0>; +- intel,npe-handle = <&npe 2>; +- }; +- +- /* This is known as EthA */ +- ethernet@c800c000 { +- compatible = "intel,ixp4xx-ethernet"; +- reg = <0xc800c000 0x1000>; +- status = "disabled"; +- intel,npe = <0>; +- /* Dummy values that depend on firmware */ +- queue-rx = <&qmgr 0>; +- queue-txready = <&qmgr 0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/iwg20d-q7-common.dtsi b/scripts/dtc/include-prefixes/arm/iwg20d-q7-common.dtsi +deleted file mode 100644 +index bc857676d191..000000000000 +--- a/scripts/dtc/include-prefixes/arm/iwg20d-q7-common.dtsi ++++ /dev/null +@@ -1,373 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board +- * +- * Copyright (C) 2017 Renesas Electronics Corp. +- */ +- +-/* +- * SSI-SGTL5000 +- * +- * This command is required when Playback/Capture +- * +- * amixer set "DVC Out" 100% +- * amixer set "DVC In" 100% +- * +- * You can use Mute +- * +- * amixer set "DVC Out Mute" on +- * amixer set "DVC In Mute" on +- * +- * You can use Volume Ramp +- * +- * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" +- * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" +- * amixer set "DVC Out Ramp" on +- * aplay xxx.wav & +- * amixer set "DVC Out" 80% // Volume Down +- * amixer set "DVC Out" 100% // Volume Up +- */ +- +-/ { +- aliases { +- serial0 = &scif0; +- serial3 = &scifb1; +- ethernet0 = &avb; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; +- stdout-path = "serial0:115200n8"; +- }; +- +- audio_clock: audio_clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +- +- lcd_backlight: backlight { +- compatible = "pwm-backlight"; +- +- pwms = <&pwm3 0 5000000 0>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- enable-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; +- }; +- +- lvds-receiver { +- compatible = "ti,ds90cf384a", "lvds-decoder"; +- power-supply = <&vcc_3v3_tft1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds_receiver_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- port@1 { +- reg = <1>; +- lvds_receiver_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +- }; +- +- panel { +- compatible = "edt,etm0700g0dh6"; +- backlight = <&lcd_backlight>; +- power-supply = <&vcc_3v3_tft1>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds_receiver_out>; +- }; +- }; +- }; +- +- reg_1p5v: 1p5v { +- compatible = "regulator-fixed"; +- regulator-name = "1P5V"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- +- rsnd_sgtl5000: sound { +- compatible = "simple-audio-card"; +- +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sndcodec>; +- simple-audio-card,frame-master = <&sndcodec>; +- +- sndcpu: simple-audio-card,cpu { +- sound-dai = <&rcar_sound>; +- }; +- +- sndcodec: simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- }; +- }; +- +- vcc_3v3_tft1: regulator-panel { +- compatible = "regulator-fixed"; +- +- regulator-name = "vcc-3v3-tft1"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- startup-delay-us = <500>; +- gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>; +- }; +- +- vcc_sdhi1: regulator-vcc-sdhi1 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI1 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio1 16 GPIO_ACTIVE_LOW>; +- }; +- +- vccq_sdhi1: regulator-vccq-sdhi1 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI1 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +-}; +- +-&avb { +- pinctrl-0 = <&avb_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <&phy3>; +- phy-mode = "gmii"; +- renesas,no-ether-link; +- status = "okay"; +- +- phy3: ethernet-phy@3 { +- reg = <3>; +- micrel,led-mode = <1>; +- }; +-}; +- +-&can0 { +- pinctrl-0 = <&can0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&cmt0 { +- status = "okay"; +-}; +- +-&du { +- status = "okay"; +-}; +- +-&gpio2 { +- touch-interrupt { +- gpio-hog; +- gpios = <12 GPIO_ACTIVE_LOW>; +- input; +- }; +-}; +- +-&hsusb { +- status = "okay"; +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +-}; +- +-&i2c2 { +- pinctrl-0 = <&i2c2_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- rtc@68 { +- compatible = "ti,bq32000"; +- reg = <0x68>; +- }; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- #sound-dai-cells = <0>; +- reg = <0x0a>; +- clocks = <&audio_clock>; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; +- VDDD-supply = <®_1p5v>; +- }; +- +- touch: touchpanel@38 { +- compatible = "edt,edt-ft5406"; +- reg = <0x38>; +- interrupt-parent = <&gpio2>; +- interrupts = <12 IRQ_TYPE_EDGE_FALLING>; +- vcc-supply = <&vcc_3v3_tft1>; +- }; +-}; +- +-&lvds0 { +- status = "okay"; +- +- ports { +- port@1 { +- lvds0_out: endpoint { +- remote-endpoint = <&lvds_receiver_in>; +- }; +- }; +- }; +-}; +- +-&pci0 { +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +-}; +- +-&pci1 { +- status = "okay"; +- pinctrl-0 = <&usb1_pins>; +- pinctrl-names = "default"; +-}; +- +-&pcie_bus_clk { +- clock-frequency = <100000000>; +-}; +- +-&pfc { +- can0_pins: can0 { +- groups = "can0_data_d"; +- function = "can0"; +- }; +- +- avb_pins: avb { +- groups = "avb_mdio", "avb_gmii"; +- function = "avb"; +- }; +- +- i2c2_pins: i2c2 { +- groups = "i2c2"; +- function = "i2c2"; +- }; +- +- pwm3_pins: pwm3 { +- groups = "pwm3"; +- function = "pwm3"; +- }; +- +- scif0_pins: scif0 { +- groups = "scif0_data_d"; +- function = "scif0"; +- }; +- +- scifb1_pins: scifb1 { +- groups = "scifb1_data_d", "scifb1_ctrl"; +- function = "scifb1"; +- }; +- +- sdhi1_pins: sd1 { +- groups = "sdhi1_data4", "sdhi1_ctrl"; +- function = "sdhi1"; +- power-source = <3300>; +- }; +- +- sdhi1_pins_uhs: sd1_uhs { +- groups = "sdhi1_data4", "sdhi1_ctrl"; +- function = "sdhi1"; +- power-source = <1800>; +- }; +- +- sound_pins: sound { +- groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; +- function = "ssi"; +- }; +- +- usb0_pins: usb0 { +- groups = "usb0"; +- function = "usb0"; +- }; +- +- usb1_pins: usb1 { +- groups = "usb1"; +- function = "usb1"; +- }; +-}; +- +-&pwm3 { +- pinctrl-0 = <&pwm3_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&rcar_sound { +- pinctrl-0 = <&sound_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- /* Single DAI */ +- #sound-dai-cells = <0>; +- +- rcar_sound,dai { +- dai0 { +- playback = <&ssi1>, <&src3>, <&dvc1>; +- capture = <&ssi0>, <&src2>, <&dvc0>; +- }; +- }; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&scif0 { +- pinctrl-0 = <&scif0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scifb1 { +- pinctrl-0 = <&scifb1_pins>; +- pinctrl-names = "default"; +- +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&sdhi1 { +- pinctrl-0 = <&sdhi1_pins>; +- pinctrl-1 = <&sdhi1_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <&vcc_sdhi1>; +- vqmmc-supply = <&vccq_sdhi1>; +- cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; +- sd-uhs-sdr50; +- status = "okay"; +-}; +- +-&ssi1 { +- shared-pin; +-}; +- +-&usbphy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/iwg20d-q7-dbcm-ca.dtsi b/scripts/dtc/include-prefixes/arm/iwg20d-q7-dbcm-ca.dtsi +deleted file mode 100644 +index e10f99278c77..000000000000 +--- a/scripts/dtc/include-prefixes/arm/iwg20d-q7-dbcm-ca.dtsi ++++ /dev/null +@@ -1,124 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the iWave-RZ-G1M/N Daughter Board Camera Module +- * +- * Copyright (C) 2017 Renesas Electronics Corp. +- */ +- +-/ { +- aliases { +- serial1 = &scif1; +- serial4 = &hscif1; +- }; +- +- cec_clock: cec-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <12000000>; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_out: endpoint { +- remote-endpoint = <&adv7511_out>; +- }; +- }; +- }; +-}; +- +-&can1 { +- pinctrl-0 = <&can1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&du { +- pinctrl-0 = <&du_pins>; +- pinctrl-names = "default"; +- +- ports { +- port@0 { +- endpoint { +- remote-endpoint = <&adv7511_in>; +- }; +- }; +- }; +-}; +- +-&hscif1 { +- pinctrl-0 = <&hscif1_pins>; +- pinctrl-names = "default"; +- +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +- clock-frequency = <400000>; +- +- hdmi@39 { +- compatible = "adi,adv7511w"; +- reg = <0x39>; +- interrupt-parent = <&gpio0>; +- interrupts = <13 IRQ_TYPE_LEVEL_LOW>; +- clocks = <&cec_clock>; +- clock-names = "cec"; +- +- adi,input-depth = <8>; +- adi,input-colorspace = "rgb"; +- adi,input-clock = "1x"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7511_in: endpoint { +- remote-endpoint = <&du_out_rgb>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- adv7511_out: endpoint { +- remote-endpoint = <&hdmi_con_out>; +- }; +- }; +- }; +- }; +-}; +- +-&pfc { +- can1_pins: can1 { +- groups = "can1_data_d"; +- function = "can1"; +- }; +- +- du_pins: du { +- groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0"; +- function = "du"; +- }; +- +- hscif1_pins: hscif1 { +- groups = "hscif1_data_c", "hscif1_ctrl_c"; +- function = "hscif1"; +- }; +- +- scif1_pins: scif1 { +- groups = "scif1_data_d"; +- function = "scif1"; +- }; +-}; +- +-&scif1 { +- pinctrl-0 = <&scif1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/keystone-clocks.dtsi b/scripts/dtc/include-prefixes/arm/keystone-clocks.dtsi +deleted file mode 100644 +index 0397c3423d2d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/keystone-clocks.dtsi ++++ /dev/null +@@ -1,438 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for Keystone 2 clock tree +- * +- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ +- */ +- +-clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- mainmuxclk: mainmuxclk@2310108 { +- #clock-cells = <0>; +- compatible = "ti,keystone,pll-mux-clock"; +- clocks = <&mainpllclk>, <&refclksys>; +- reg = <0x02310108 4>; +- bit-shift = <23>; +- bit-mask = <1>; +- clock-output-names = "mainmuxclk"; +- }; +- +- chipclk1: chipclk1 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&mainmuxclk>; +- clock-div = <1>; +- clock-mult = <1>; +- clock-output-names = "chipclk1"; +- }; +- +- chipclk1rstiso: chipclk1rstiso { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&mainmuxclk>; +- clock-div = <1>; +- clock-mult = <1>; +- clock-output-names = "chipclk1rstiso"; +- }; +- +- gemtraceclk: gemtraceclk@2310120 { +- #clock-cells = <0>; +- compatible = "ti,keystone,pll-divider-clock"; +- clocks = <&mainmuxclk>; +- reg = <0x02310120 4>; +- bit-shift = <0>; +- bit-mask = <8>; +- clock-output-names = "gemtraceclk"; +- }; +- +- chipstmxptclk: chipstmxptclk@2310164 { +- #clock-cells = <0>; +- compatible = "ti,keystone,pll-divider-clock"; +- clocks = <&mainmuxclk>; +- reg = <0x02310164 4>; +- bit-shift = <0>; +- bit-mask = <8>; +- clock-output-names = "chipstmxptclk"; +- }; +- +- chipclk12: chipclk12 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&chipclk1>; +- clock-div = <2>; +- clock-mult = <1>; +- clock-output-names = "chipclk12"; +- }; +- +- chipclk13: chipclk13 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&chipclk1>; +- clock-div = <3>; +- clock-mult = <1>; +- clock-output-names = "chipclk13"; +- }; +- +- paclk13: paclk13 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&papllclk>; +- clock-div = <3>; +- clock-mult = <1>; +- clock-output-names = "paclk13"; +- }; +- +- chipclk14: chipclk14 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&chipclk1>; +- clock-div = <4>; +- clock-mult = <1>; +- clock-output-names = "chipclk14"; +- }; +- +- chipclk16: chipclk16 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&chipclk1>; +- clock-div = <6>; +- clock-mult = <1>; +- clock-output-names = "chipclk16"; +- }; +- +- chipclk112: chipclk112 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&chipclk1>; +- clock-div = <12>; +- clock-mult = <1>; +- clock-output-names = "chipclk112"; +- }; +- +- chipclk124: chipclk124 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&chipclk1>; +- clock-div = <24>; +- clock-mult = <1>; +- clock-output-names = "chipclk114"; +- }; +- +- chipclk1rstiso13: chipclk1rstiso13 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&chipclk1rstiso>; +- clock-div = <3>; +- clock-mult = <1>; +- clock-output-names = "chipclk1rstiso13"; +- }; +- +- chipclk1rstiso14: chipclk1rstiso14 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&chipclk1rstiso>; +- clock-div = <4>; +- clock-mult = <1>; +- clock-output-names = "chipclk1rstiso14"; +- }; +- +- chipclk1rstiso16: chipclk1rstiso16 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&chipclk1rstiso>; +- clock-div = <6>; +- clock-mult = <1>; +- clock-output-names = "chipclk1rstiso16"; +- }; +- +- chipclk1rstiso112: chipclk1rstiso112 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&chipclk1rstiso>; +- clock-div = <12>; +- clock-mult = <1>; +- clock-output-names = "chipclk1rstiso112"; +- }; +- +- clkmodrst0: clkmodrst0@2350000 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk16>; +- clock-output-names = "modrst0"; +- reg = <0x02350000 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +- +- +- clkusb: clkusb@2350008 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk16>; +- clock-output-names = "usb"; +- reg = <0x02350008 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +- +- clkaemifspi: clkaemifspi@235000c { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk16>; +- clock-output-names = "aemif-spi"; +- reg = <0x0235000c 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +- +- +- clkdebugsstrc: clkdebugsstrc@2350014 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "debugss-trc"; +- reg = <0x02350014 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <1>; +- }; +- +- clktetbtrc: clktetbtrc@2350018 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "tetb-trc"; +- reg = <0x02350018 0xb00>, <0x02350004 0x400>; +- reg-names = "control", "domain"; +- domain-id = <1>; +- }; +- +- clkpa: clkpa@235001c { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&paclk13>; +- clock-output-names = "pa"; +- reg = <0x0235001c 0xb00>, <0x02350008 0x400>; +- reg-names = "control", "domain"; +- domain-id = <2>; +- }; +- +- clkcpgmac: clkcpgmac@2350020 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&clkpa>; +- clock-output-names = "cpgmac"; +- reg = <0x02350020 0xb00>, <0x02350008 0x400>; +- reg-names = "control", "domain"; +- domain-id = <2>; +- }; +- +- clksa: clksa@2350024 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&clkpa>; +- clock-output-names = "sa"; +- reg = <0x02350024 0xb00>, <0x02350008 0x400>; +- reg-names = "control", "domain"; +- domain-id = <2>; +- }; +- +- clkpcie: clkpcie@2350028 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk12>; +- clock-output-names = "pcie"; +- reg = <0x02350028 0xb00>, <0x0235000c 0x400>; +- reg-names = "control", "domain"; +- domain-id = <3>; +- }; +- +- clksr: clksr@2350034 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk1rstiso112>; +- clock-output-names = "sr"; +- reg = <0x02350034 0xb00>, <0x02350018 0x400>; +- reg-names = "control", "domain"; +- domain-id = <6>; +- }; +- +- clkgem0: clkgem0@235003c { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk1>; +- clock-output-names = "gem0"; +- reg = <0x0235003c 0xb00>, <0x02350020 0x400>; +- reg-names = "control", "domain"; +- domain-id = <8>; +- }; +- +- clkddr30: clkddr30@235005c { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk12>; +- clock-output-names = "ddr3-0"; +- reg = <0x0235005c 0xb00>, <0x02350040 0x400>; +- reg-names = "control", "domain"; +- domain-id = <16>; +- }; +- +- clkwdtimer0: clkwdtimer0@2350000 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&clkmodrst0>; +- clock-output-names = "timer0"; +- reg = <0x02350000 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +- +- clkwdtimer1: clkwdtimer1@2350000 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&clkmodrst0>; +- clock-output-names = "timer1"; +- reg = <0x02350000 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +- +- clkwdtimer2: clkwdtimer2@2350000 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&clkmodrst0>; +- clock-output-names = "timer2"; +- reg = <0x02350000 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +- +- clkwdtimer3: clkwdtimer3@2350000 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&clkmodrst0>; +- clock-output-names = "timer3"; +- reg = <0x02350000 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +- +- clktimer15: clktimer15@2350000 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&clkmodrst0>; +- clock-output-names = "timer15"; +- reg = <0x02350000 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +- +- clkuart0: clkuart0@2350000 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&clkmodrst0>; +- clock-output-names = "uart0"; +- reg = <0x02350000 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +- +- clkuart1: clkuart1@2350000 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&clkmodrst0>; +- clock-output-names = "uart1"; +- reg = <0x02350000 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +- +- clkaemif: clkaemif@2350000 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&clkaemifspi>; +- clock-output-names = "aemif"; +- reg = <0x02350000 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +- +- clkusim: clkusim@2350000 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&clkmodrst0>; +- clock-output-names = "usim"; +- reg = <0x02350000 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +- +- clki2c: clki2c@2350000 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&clkmodrst0>; +- clock-output-names = "i2c"; +- reg = <0x02350000 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +- +- clkspi: clkspi@2350000 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&clkaemifspi>; +- clock-output-names = "spi"; +- reg = <0x02350000 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +- +- clkgpio: clkgpio@2350000 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&clkmodrst0>; +- clock-output-names = "gpio"; +- reg = <0x02350000 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +- +- clkkeymgr: clkkeymgr@2350000 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&clkmodrst0>; +- clock-output-names = "keymgr"; +- reg = <0x02350000 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +- +- /* +- * Below are set of fixed, input clocks definitions, +- * for which real frequencies have to be defined in board files. +- * Those clocks can be used as reference clocks for some HW modules +- * (as cpts, for example) by configuring corresponding clock muxes. +- */ +- timi0: timi0 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- clock-output-names = "timi0"; +- }; +- +- timi1: timi1 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- clock-output-names = "timi1"; +- }; +- +- tsrefclk: tsrefclk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- clock-output-names = "tsrefclk"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/keystone-k2e-clocks.dtsi b/scripts/dtc/include-prefixes/arm/keystone-k2e-clocks.dtsi +deleted file mode 100644 +index cf30e007fea3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/keystone-k2e-clocks.dtsi ++++ /dev/null +@@ -1,94 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Keystone 2 Edison SoC specific device tree +- * +- * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ +- */ +- +-clocks { +- mainpllclk: mainpllclk@2310110 { +- #clock-cells = <0>; +- compatible = "ti,keystone,main-pll-clock"; +- clocks = <&refclksys>; +- reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; +- reg-names = "control", "multiplier", "post-divider"; +- }; +- +- papllclk: papllclk@2620358 { +- #clock-cells = <0>; +- compatible = "ti,keystone,pll-clock"; +- clocks = <&refclkpass>; +- clock-output-names = "papllclk"; +- reg = <0x02620358 4>; +- reg-names = "control"; +- }; +- +- ddr3apllclk: ddr3apllclk@2620360 { +- #clock-cells = <0>; +- compatible = "ti,keystone,pll-clock"; +- clocks = <&refclkddr3a>; +- clock-output-names = "ddr-3a-pll-clk"; +- reg = <0x02620360 4>; +- reg-names = "control"; +- }; +- +- clkusb1: clkusb1@2350004 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk16>; +- clock-output-names = "usb1"; +- reg = <0x02350004 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +- +- clkhyperlink0: clkhyperlink0@2350030 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk12>; +- clock-output-names = "hyperlink-0"; +- reg = <0x02350030 0xb00>, <0x02350014 0x400>; +- reg-names = "control", "domain"; +- domain-id = <5>; +- }; +- +- clkpcie1: clkpcie1@235006c { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk12>; +- clock-output-names = "pcie1"; +- reg = <0x0235006c 0xb00>, <0x02350048 0x400>; +- reg-names = "control", "domain"; +- domain-id = <18>; +- }; +- +- clkxge: clkxge@23500c8 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "xge"; +- reg = <0x023500c8 0xb00>, <0x02350074 0x400>; +- reg-names = "control", "domain"; +- domain-id = <29>; +- }; +- +- /* +- * Below are set of fixed, input clocks definitions, +- * for which real frequencies have to be defined in board files. +- * Those clocks can be used as reference clocks for some HW modules +- * (as cpts, for example) by configuring corresponding clock muxes. +- */ +- tsipclka: tsipclka { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- clock-output-names = "tsipclka"; +- }; +- +- tsipclkb: tsipclkb { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- clock-output-names = "tsipclkb"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/keystone-k2e-evm.dts b/scripts/dtc/include-prefixes/arm/keystone-k2e-evm.dts +deleted file mode 100644 +index 66fec5f5d081..000000000000 +--- a/scripts/dtc/include-prefixes/arm/keystone-k2e-evm.dts ++++ /dev/null +@@ -1,177 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Keystone 2 Edison EVM device tree +- * +- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "keystone.dtsi" +-#include "keystone-k2e.dtsi" +- +-/ { +- compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"; +- model = "Texas Instruments Keystone 2 Edison EVM"; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- dsp_common_memory: dsp-common-memory@81f800000 { +- compatible = "shared-dma-pool"; +- reg = <0x00000008 0x1f800000 0x00000000 0x800000>; +- reusable; +- status = "okay"; +- }; +- }; +-}; +- +-&soc0 { +- +- clocks { +- refclksys: refclksys { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <100000000>; +- clock-output-names = "refclk-sys"; +- }; +- +- refclkpass: refclkpass { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <100000000>; +- clock-output-names = "refclk-pass"; +- }; +- +- refclkddr3a: refclkddr3a { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <100000000>; +- clock-output-names = "refclk-ddr3a"; +- }; +- }; +-}; +- +-&usb_phy { +- status = "okay"; +-}; +- +-&keystone_usb0 { +- status = "okay"; +-}; +- +-&usb0 { +- dr_mode = "host"; +-}; +- +-&usb1_phy { +- status = "okay"; +-}; +- +-&keystone_usb1 { +- status = "okay"; +-}; +- +-&usb1 { +- dr_mode = "peripheral"; +-}; +- +-&i2c0 { +- dtt@50 { +- compatible = "atmel,24c1024"; +- reg = <0x50>; +- }; +-}; +- +-&aemif { +- cs0 { +- #address-cells = <2>; +- #size-cells = <1>; +- clock-ranges; +- ranges; +- +- ti,cs-chipselect = <0>; +- /* all timings in nanoseconds */ +- ti,cs-min-turnaround-ns = <12>; +- ti,cs-read-hold-ns = <6>; +- ti,cs-read-strobe-ns = <23>; +- ti,cs-read-setup-ns = <9>; +- ti,cs-write-hold-ns = <8>; +- ti,cs-write-strobe-ns = <23>; +- ti,cs-write-setup-ns = <8>; +- +- nand@0,0 { +- compatible = "ti,keystone-nand","ti,davinci-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0 0 0x4000000 +- 1 0 0x0000100>; +- +- ti,davinci-chipselect = <0>; +- ti,davinci-mask-ale = <0x2000>; +- ti,davinci-mask-cle = <0x4000>; +- ti,davinci-mask-chipsel = <0>; +- nand-ecc-mode = "hw"; +- ti,davinci-ecc-bits = <4>; +- nand-on-flash-bbt; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0 0x100000>; +- read-only; +- }; +- +- partition@100000 { +- label = "params"; +- reg = <0x100000 0x80000>; +- read-only; +- }; +- +- partition@180000 { +- label = "ubifs"; +- reg = <0x180000 0x1FE80000>; +- }; +- }; +- }; +-}; +- +-&spi0 { +- nor_flash: n25q128a11@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "Micron,n25q128a11"; +- spi-max-frequency = <54000000>; +- m25p,fast-read; +- reg = <0>; +- +- partition@0 { +- label = "u-boot-spl"; +- reg = <0x0 0x80000>; +- read-only; +- }; +- +- partition@1 { +- label = "misc"; +- reg = <0x80000 0xf80000>; +- }; +- }; +-}; +- +-&mdio { +- status = "ok"; +- ethphy0: ethernet-phy@0 { +- compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&dsp0 { +- memory-region = <&dsp_common_memory>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/keystone-k2e-netcp.dtsi b/scripts/dtc/include-prefixes/arm/keystone-k2e-netcp.dtsi +deleted file mode 100644 +index 71064483d34f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/keystone-k2e-netcp.dtsi ++++ /dev/null +@@ -1,264 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for Keystone 2 Edison Netcp driver +- * +- * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ +- */ +- +-qmss: qmss@2a40000 { +- compatible = "ti,keystone-navigator-qmss"; +- dma-coherent; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&chipclk13>; +- ranges; +- queue-range = <0 0x2000>; +- linkram0 = <0x100000 0x4000>; +- linkram1 = <0 0x10000>; +- +- qmgrs { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- qmgr0 { +- managed-queues = <0 0x2000>; +- reg = <0x2a40000 0x20000>, +- <0x2a06000 0x400>, +- <0x2a02000 0x1000>, +- <0x2a03000 0x1000>, +- <0x23a80000 0x20000>, +- <0x2a80000 0x20000>; +- reg-names = "peek", "status", "config", +- "region", "push", "pop"; +- }; +- }; +- queue-pools { +- qpend { +- qpend-0 { +- qrange = <658 8>; +- interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 +- 0 43 0xf04 0 44 0xf04 0 45 0xf04 +- 0 46 0xf04 0 47 0xf04>; +- }; +- qpend-1 { +- qrange = <528 16>; +- interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 +- 0 51 0xf04 0 52 0xf04 0 53 0xf04 +- 0 54 0xf04 0 55 0xf04 0 56 0xf04 +- 0 57 0xf04 0 58 0xf04 0 59 0xf04 +- 0 60 0xf04 0 61 0xf04 0 62 0xf04 +- 0 63 0xf04>; +- qalloc-by-id; +- }; +- qpend-2 { +- qrange = <544 16>; +- interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 +- 0 59 0xf04 0 68 0xf04 0 69 0xf04 +- 0 70 0xf04 0 71 0xf04 0 72 0xf04 +- 0 73 0xf04 0 74 0xf04 0 75 0xf04 +- 0 76 0xf04 0 77 0xf04 0 78 0xf04 +- 0 79 0xf04>; +- }; +- }; +- general-purpose { +- gp-0 { +- qrange = <4000 64>; +- }; +- netcp-tx { +- qrange = <896 128>; +- qalloc-by-id; +- }; +- }; +- accumulator { +- acc-low-0 { +- qrange = <480 32>; +- accumulator = <0 47 16 2 50>; +- interrupts = <0 226 0xf01>; +- multi-queue; +- qalloc-by-id; +- }; +- }; +- }; +- +- descriptor-regions { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- region-12 { +- id = <12>; +- region-spec = <8192 128>; /* num_desc desc_size */ +- link-index = <0x4000>; +- }; +- }; +- +- pdsps { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- pdsp0@2a10000 { +- reg = <0x2a10000 0x1000 /*iram */ +- 0x2a0f000 0x100 /*reg*/ +- 0x2a0c000 0x3c8 /*intd */ +- 0x2a20000 0x4000>; /*cmd*/ +- id = <0>; +- }; +- }; +-}; /* qmss */ +- +-knav_dmas: knav_dmas@0 { +- compatible = "ti,keystone-navigator-dma"; +- clocks = <&papllclk>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- ti,navigator-cloud-address = <0x23a80000 0x23a90000 +- 0x23a80000 0x23a90000>; +- +- dma_gbe: dma_gbe@0 { +- reg = <0x24186000 0x100>, +- <0x24187000 0x2a0>, +- <0x24188000 0xb60>, +- <0x24186100 0x80>, +- <0x24189000 0x1000>; +- reg-names = "global", "txchan", "rxchan", +- "txsched", "rxflow"; +- }; +-}; +- +-netcp: netcp@24000000 { +- reg = <0x2620110 0x8>; +- reg-names = "efuse"; +- compatible = "ti,netcp-1.0"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* NetCP address range */ +- ranges = <0 0x24000000 0x1000000>; +- +- clocks = <&clkpa>, <&clkcpgmac>; +- clock-names = "pa_clk", "ethss_clk"; +- dma-coherent; +- +- ti,navigator-dmas = <&dma_gbe 0>, +- <&dma_gbe 8>, +- <&dma_gbe 0>; +- ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; +- +- netcp-devices { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- gbe@200000 { /* ETHSS */ +- label = "netcp-gbe"; +- compatible = "ti,netcp-gbe-9"; +- reg = <0x200000 0x900>, <0x220000 0x20000>; +- /* enable-ale; */ +- tx-queue = <896>; +- tx-channel = "nettx"; +- +- cpts { +- clocks = <&cpts_refclk_mux>; +- clock-names = "cpts"; +- +- cpts_refclk_mux: cpts-refclk-mux { +- #clock-cells = <0>; +- clocks = <&chipclk12>, <&chipclk13>, +- <&timi0>, <&timi1>, +- <&tsipclka>, <&tsrefclk>, +- <&tsipclkb>; +- ti,mux-tbl = <0x0>, <0x1>, <0x2>, +- <0x3>, <0x4>, <0x8>, <0xC>; +- assigned-clocks = <&cpts_refclk_mux>; +- assigned-clock-parents = <&chipclk12>; +- }; +- }; +- +- interfaces { +- gbe0: interface-0 { +- slave-port = <0>; +- link-interface = <1>; +- phy-handle = <ðphy0>; +- }; +- gbe1: interface-1 { +- slave-port = <1>; +- link-interface = <1>; +- phy-handle = <ðphy1>; +- }; +- }; +- +- secondary-slave-ports { +- port-2 { +- slave-port = <2>; +- link-interface = <2>; +- }; +- port-3 { +- slave-port = <3>; +- link-interface = <2>; +- }; +- port-4 { +- slave-port = <4>; +- link-interface = <2>; +- }; +- port-5 { +- slave-port = <5>; +- link-interface = <2>; +- }; +- port-6 { +- slave-port = <6>; +- link-interface = <2>; +- }; +- port-7 { +- slave-port = <7>; +- link-interface = <2>; +- }; +- }; +- }; +- }; +- +- netcp-interfaces { +- interface-0 { +- rx-channel = "netrx0"; +- rx-pool = <1024 12>; +- tx-pool = <1024 12>; +- rx-queue-depth = <128 128 0 0>; +- rx-buffer-size = <1518 4096 0 0>; +- rx-queue = <528>; +- tx-completion-queue = <530>; +- efuse-mac = <1>; +- netcp-gbe = <&gbe0>; +- +- }; +- interface-1 { +- rx-channel = "netrx1"; +- rx-pool = <1024 12>; +- tx-pool = <1024 12>; +- rx-queue-depth = <128 128 0 0>; +- rx-buffer-size = <1518 4096 0 0>; +- rx-queue = <529>; +- tx-completion-queue = <531>; +- efuse-mac = <0>; +- local-mac-address = [02 18 31 7e 3e 00]; +- netcp-gbe = <&gbe1>; +- }; +- }; +-}; +- +-sa_subsys: subsys@24080000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0 0x24080000 0x40000>; +- +- sa_config: subsys@0 { +- compatible = "syscon"; +- reg = <0x0 0x100>; +- }; +- +- rng@24000 { +- compatible = "ti,keystone-rng"; +- reg = <0x24000 0x1000>; +- ti,syscon-sa-cfg = <&sa_config>; +- clocks = <&clksa>; +- clock-names = "fck"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/keystone-k2e.dtsi b/scripts/dtc/include-prefixes/arm/keystone-k2e.dtsi +deleted file mode 100644 +index b8f152e7af7f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/keystone-k2e.dtsi ++++ /dev/null +@@ -1,198 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Keystone 2 Edison soc device tree +- * +- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ +- */ +- +-#include +- +-/ { +- compatible = "ti,k2e", "ti,keystone"; +- model = "Texas Instruments Keystone 2 Edison SoC"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- interrupt-parent = <&gic>; +- +- cpu@0 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- reg = <0>; +- }; +- +- cpu@1 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- reg = <1>; +- }; +- +- cpu@2 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- reg = <2>; +- }; +- +- cpu@3 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- reg = <3>; +- }; +- }; +- +- aliases { +- rproc0 = &dsp0; +- }; +-}; +- +-&soc0 { +- /include/ "keystone-k2e-clocks.dtsi" +- +- usb: usb@2680000 { +- interrupts = ; +- usb@2690000 { +- interrupts = ; +- }; +- }; +- +- usb1_phy: usb_phy@2620750 { +- compatible = "ti,keystone-usbphy"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x2620750 24>; +- status = "disabled"; +- }; +- +- keystone_usb1: usb@25000000 { +- compatible = "ti,keystone-dwc3"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x25000000 0x10000>; +- clocks = <&clkusb1>; +- clock-names = "usb"; +- interrupts = ; +- ranges; +- dma-coherent; +- dma-ranges; +- status = "disabled"; +- +- usb1: usb@25010000 { +- compatible = "snps,dwc3"; +- reg = <0x25010000 0x70000>; +- interrupts = ; +- usb-phy = <&usb1_phy>, <&usb1_phy>; +- }; +- }; +- +- msm_ram: sram@c000000 { +- compatible = "mmio-sram"; +- reg = <0x0c000000 0x200000>; +- ranges = <0x0 0x0c000000 0x200000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- bm-sram@1f0000 { +- reg = <0x001f0000 0x8000>; +- }; +- }; +- +- psc: power-sleep-controller@2350000 { +- pscrst: reset-controller { +- compatible = "ti,k2e-pscrst", "ti,syscon-reset"; +- #reset-cells = <1>; +- +- ti,reset-bits = < +- 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ +- >; +- }; +- }; +- +- devctrl: device-state-control@2620000 { +- dspgpio0: keystone_dsp_gpio@240 { +- compatible = "ti,keystone-dsp-gpio"; +- reg = <0x240 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio,syscon-dev = <&devctrl 0x240>; +- }; +- }; +- +- dsp0: dsp@10800000 { +- compatible = "ti,k2e-dsp"; +- reg = <0x10800000 0x00080000>, +- <0x10e00000 0x00008000>, +- <0x10f00000 0x00008000>; +- reg-names = "l2sram", "l1pram", "l1dram"; +- clocks = <&clkgem0>; +- ti,syscon-dev = <&devctrl 0x844>; +- resets = <&pscrst 0>; +- interrupt-parent = <&kirq0>; +- interrupts = <0 8>; +- interrupt-names = "vring", "exception"; +- kick-gpios = <&dspgpio0 27 0>; +- status = "disabled"; +- }; +- +- pcie1: pcie@21020000 { +- compatible = "ti,keystone-pcie","snps,dw-pcie"; +- clocks = <&clkpcie1>; +- clock-names = "pcie"; +- #address-cells = <3>; +- #size-cells = <2>; +- reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; +- ranges = <0x82000000 0 0x60000000 0x60000000 +- 0 0x10000000>; +- +- status = "disabled"; +- device_type = "pci"; +- num-lanes = <2>; +- bus-range = <0x00 0xff>; +- +- /* error interrupt */ +- interrupts = ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */ +- <0 0 0 2 &pcie_intc1 1>, /* INT B */ +- <0 0 0 3 &pcie_intc1 2>, /* INT C */ +- <0 0 0 4 &pcie_intc1 3>; /* INT D */ +- +- pcie_msi_intc1: msi-interrupt-controller { +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- }; +- +- pcie_intc1: legacy-interrupt-controller { +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- }; +- }; +- +- mdio: mdio@24200f00 { +- compatible = "ti,keystone_mdio", "ti,davinci_mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x24200f00 0x100>; +- status = "disabled"; +- clocks = <&clkcpgmac>; +- clock-names = "fck"; +- bus_freq = <2500000>; +- }; +- /include/ "keystone-k2e-netcp.dtsi" +-}; +diff --git a/scripts/dtc/include-prefixes/arm/keystone-k2g-evm.dts b/scripts/dtc/include-prefixes/arm/keystone-k2g-evm.dts +deleted file mode 100644 +index d800f26b6275..000000000000 +--- a/scripts/dtc/include-prefixes/arm/keystone-k2g-evm.dts ++++ /dev/null +@@ -1,567 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for K2G EVM +- * +- * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "keystone-k2g.dtsi" +- +-/ { +- compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone"; +- model = "Texas Instruments K2G General Purpose EVM"; +- +- memory@800000000 { +- device_type = "memory"; +- reg = <0x00000008 0x00000000 0x00000000 0x80000000>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- dsp_common_memory: dsp-common-memory@81f800000 { +- compatible = "shared-dma-pool"; +- reg = <0x00000008 0x1f800000 0x00000000 0x800000>; +- reusable; +- status = "okay"; +- }; +- }; +- +- vcc3v3_dcin_reg: fixedregulator-vcc3v3-dcin { +- compatible = "regulator-fixed"; +- regulator-name = "mmc0_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vcc1v8_ldo1_reg: fixedregulator-vcc1v8-ldo1 { +- compatible = "regulator-fixed"; +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcc1v8_ldo2_reg: fixedregulator-vcc1v8-ldo2 { +- compatible = "regulator-fixed"; +- regulator-name = "ldo2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- hdmi: connector { +- compatible = "hdmi-connector"; +- label = "hdmi"; +- +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&sii9022_out>; +- }; +- }; +- }; +- +- aud_mclk: aud_mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <12288000>; +- }; +- +- sound0: sound@0 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "K2G-EVM"; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack", +- "Line", "Line In"; +- simple-audio-card,routing = +- "Headphone Jack", "HPLOUT", +- "Headphone Jack", "HPROUT", +- "LINE1L", "Line In", +- "LINE1R", "Line In"; +- +- simple-audio-card,dai-link@0 { +- format = "i2s"; +- bitclock-master = <&sound0_0_master>; +- frame-master = <&sound0_0_master>; +- sound0_0_master: cpu { +- sound-dai = <&mcasp2>; +- clocks = <&k2g_clks 0x6 1>; +- system-clock-direction-out; +- }; +- +- codec { +- sound-dai = <&tlv320aic3106>; +- clocks = <&aud_mclk>; +- }; +- }; +- +- simple-audio-card,dai-link@1 { +- format = "i2s"; +- bitclock-master = <&sound0_1_master>; +- frame-master = <&sound0_1_master>; +- sound0_1_master: cpu { +- sound-dai = <&mcasp2>; +- clocks = <&k2g_clks 0x6 1>; +- system-clock-direction-out; +- }; +- +- codec { +- sound-dai = <&sii9022>; +- clocks = <&aud_mclk>; +- }; +- }; +- }; +-}; +- +-&k2g_pinctrl { +- uart0_pins: pinmux_uart0_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */ +- K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ +- >; +- }; +- +- mmc0_pins: pinmux_mmc0_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */ +- K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat2.mmc0_dat2 */ +- K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat1.mmc0_dat1 */ +- K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat0.mmc0_dat0 */ +- K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_clk.mmc0_clk */ +- K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_cmd.mmc0_cmd */ +- K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc0_sdcd.gpio1_12 */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat7.mmc1_dat7 */ +- K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat6.mmc1_dat6 */ +- K2G_CORE_IOPAD(0x10f4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat5.mmc1_dat5 */ +- K2G_CORE_IOPAD(0x10f8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat4.mmc1_dat4 */ +- K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ +- K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ +- K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ +- K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ +- K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ +- K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ +- >; +- }; +- +- i2c0_pins: pinmux_i2c0_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ +- K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ +- K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ +- >; +- }; +- +- ecap0_pins: ecap0_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4) /* pr1_mdio_data.ecap0_in_apwm0_out */ +- >; +- }; +- +- spi1_pins: pinmux_spi1_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_scs0.spi1_scs0 */ +- K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_clk.spi1_clk */ +- K2G_CORE_IOPAD(0x11b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_miso.spi1_miso */ +- K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_mosi.spi1_mosi */ +- >; +- }; +- +- qspi_pins: pinmux_qspi_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */ +- K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */ +- K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */ +- K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */ +- K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */ +- K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */ +- K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */ +- >; +- }; +- +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart2_rxd.uart2_rxd */ +- K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart2_txd.uart2_txd */ +- >; +- }; +- +- dcan0_pins: pinmux_dcan0_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dcan0tx.dcan0tx */ +- K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* dcan0rx.dcan0rx */ +- >; +- }; +- +- dcan1_pins: pinmux_dcan1_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* qspicsn2.dcan1tx */ +- K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE1) /* qspicsn3.dcan1rx */ +- >; +- }; +- +- emac_pins: pinmux_emac_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ +- K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ +- K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ +- K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ +- K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ +- K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ +- K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ +- K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ +- K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ +- K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ +- K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ +- K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ +- >; +- }; +- +- mdio_pins: pinmux_mdio_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ +- K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ +- >; +- }; +- +- vout_pins: pinmux_vout_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x1078) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata23.dssdata23 */ +- K2G_CORE_IOPAD(0x107c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata22.dssdata22 */ +- K2G_CORE_IOPAD(0x1080) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata21.dssdata21 */ +- K2G_CORE_IOPAD(0x1084) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata20.dssdata20 */ +- K2G_CORE_IOPAD(0x1088) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata19.dssdata19 */ +- K2G_CORE_IOPAD(0x108c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata18.dssdata18 */ +- K2G_CORE_IOPAD(0x1090) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata17.dssdata17 */ +- K2G_CORE_IOPAD(0x1094) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata16.dssdata16 */ +- K2G_CORE_IOPAD(0x1098) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata15.dssdata15 */ +- K2G_CORE_IOPAD(0x109c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata14.dssdata14 */ +- K2G_CORE_IOPAD(0x10a0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata13.dssdata13 */ +- K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata12.dssdata12 */ +- K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata11.dssdata11 */ +- K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata10.dssdata10 */ +- K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata9.dssdata9 */ +- K2G_CORE_IOPAD(0x10b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata8.dssdata8 */ +- K2G_CORE_IOPAD(0x10b8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata7.dssdata7 */ +- K2G_CORE_IOPAD(0x10bc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata6.dssdata6 */ +- K2G_CORE_IOPAD(0x10c0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata5.dssdata5 */ +- K2G_CORE_IOPAD(0x10c4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata4.dssdata4 */ +- K2G_CORE_IOPAD(0x10c8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata3.dssdata3 */ +- K2G_CORE_IOPAD(0x10cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata2.dssdata2 */ +- K2G_CORE_IOPAD(0x10d0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata1.dssdata1 */ +- K2G_CORE_IOPAD(0x10d4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata0.dssdata0 */ +- K2G_CORE_IOPAD(0x10d8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssvsync.dssvsync */ +- K2G_CORE_IOPAD(0x10dc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsshsync.dsshsync */ +- K2G_CORE_IOPAD(0x10e0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsspclk.dsspclk */ +- K2G_CORE_IOPAD(0x10e4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssde.dssde */ +- K2G_CORE_IOPAD(0x10e8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssfid.dssfid */ +- >; +- }; +- +- mcasp2_pins: pinmux_mcasp2_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x1234) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo2.mcasp2_axr2 */ +- K2G_CORE_IOPAD(0x1238) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo3.mcasp2_axr3 */ +- K2G_CORE_IOPAD(0x1254) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo10.mcasp2_afsx */ +- K2G_CORE_IOPAD(0x125c) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo12.mcasp2_aclkx */ +- >; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +-&gpio1 { +- status = "okay"; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <&vcc3v3_dcin_reg>; +- vqmmc-supply = <&vcc3v3_dcin_reg>; +- cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */ +- vqmmc-supply = <&vcc1v8_ldo1_reg>; +- ti,non-removable; +- status = "okay"; +-}; +- +-&dsp0 { +- memory-region = <&dsp_common_memory>; +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c1024"; +- reg = <0x50>; +- }; +-}; +- +-&keystone_usb0 { +- status = "okay"; +-}; +- +-&usb0_phy { +- status = "okay"; +-}; +- +-&usb0 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&keystone_usb1 { +- status = "okay"; +-}; +- +-&usb1_phy { +- status = "okay"; +-}; +- +-&usb1 { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&ecap0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ecap0_pins>; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins>; +- status = "okay"; +- +- spi_nor: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <5000000>; +- m25p,fast-read; +- reg = <0>; +- +- partition@0 { +- label = "u-boot-spl"; +- reg = <0x0 0x100000>; +- read-only; +- }; +- +- partition@1 { +- label = "misc"; +- reg = <0x100000 0xf00000>; +- }; +- }; +-}; +- +-&qspi { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&qspi_pins>; +- cdns,rclk-en; +- +- flash0: m25p80@0 { +- compatible = "s25fl512s", "jedec,spi-nor"; +- reg = <0>; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <4>; +- spi-max-frequency = <96000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- cdns,read-delay = <5>; +- cdns,tshsl-ns = <500>; +- cdns,tsd2d-ns = <500>; +- cdns,tchsh-ns = <119>; +- cdns,tslch-ns = <119>; +- +- partition@0 { +- label = "QSPI.u-boot-spl-os"; +- reg = <0x00000000 0x00100000>; +- }; +- partition@1 { +- label = "QSPI.u-boot-env"; +- reg = <0x00100000 0x00040000>; +- }; +- partition@2 { +- label = "QSPI.skern"; +- reg = <0x00140000 0x0040000>; +- }; +- partition@3 { +- label = "QSPI.pmmc-firmware"; +- reg = <0x00180000 0x0040000>; +- }; +- partition@4 { +- label = "QSPI.kernel"; +- reg = <0x001C0000 0x0800000>; +- }; +- partition@5 { +- label = "QSPI.file-system"; +- reg = <0x009C0000 0x3640000>; +- }; +- }; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "okay"; +-}; +- +-&dcan0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&dcan0_pins>; +- status = "okay"; +-}; +- +-&dcan1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&dcan1_pins>; +- status = "okay"; +-}; +- +-&qmss { +- status = "okay"; +-}; +- +-&knav_dmas { +- status = "okay"; +-}; +- +-&mdio { +- pinctrl-names = "default"; +- pinctrl-0 = <&mdio_pins>; +- status = "okay"; +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&gbe0 { +- phy-handle = <ðphy0>; +- phy-mode = "rgmii-rxid"; +- status = "okay"; +-}; +- +-&netcp { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_pins>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "okay"; +- clock-frequency = <400000>; +- +- sii9022: sii9022@3b { +- #sound-dai-cells = <0>; +- compatible = "sil,sii9022"; +- reg = <0x3b>; +- +- sil,i2s-data-lanes = < 0 >; +- clocks = <&aud_mclk>; +- clock-names = "mclk"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- sii9022_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- sii9022_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +- }; +- }; +- }; +- +- tlv320aic3106: tlv320aic3106@1b { +- #sound-dai-cells = <0>; +- compatible = "ti,tlv320aic3106"; +- reg = <0x1b>; +- status = "okay"; +- +- /* Regulators */ +- AVDD-supply = <&vcc3v3_dcin_reg>; +- IOVDD-supply = <&vcc3v3_dcin_reg>; +- DRVDD-supply = <&vcc3v3_dcin_reg>; +- DVDD-supply = <&vcc1v8_ldo2_reg>; +- }; +-}; +- +-&dss { +- pinctrl-names = "default"; +- pinctrl-0 = <&vout_pins>; +- status = "ok"; +- +- port { +- dpi_out: endpoint { +- remote-endpoint = <&sii9022_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-&mcasp2 { +- #sound-dai-cells = <0>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&mcasp2_pins>; +- +- assigned-clocks = <&k2g_clks 0x4c 2>, <&k2g_clks 0x6 1>; +- assigned-clock-parents = <0>, <&k2g_clks 0x6 2>; +- assigned-clock-rates = <22579200>, <0>; +- +- status = "okay"; +- +- op-mode = <0>; /* MCASP_IIS_MODE */ +- tdm-slots = <2>; +- /* 6 serializer */ +- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ +- 0 0 1 2 0 0 // AXR2: TX, AXR3: rx +- >; +- tx-num-evt = <32>; +- rx-num-evt = <32>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/keystone-k2g-ice.dts b/scripts/dtc/include-prefixes/arm/keystone-k2g-ice.dts +deleted file mode 100644 +index 2a2d38cf0fff..000000000000 +--- a/scripts/dtc/include-prefixes/arm/keystone-k2g-ice.dts ++++ /dev/null +@@ -1,447 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for K2G Industrial Communication Engine EVM +- * +- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "keystone-k2g.dtsi" +-#include +- +-/ { +- compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone"; +- model = "Texas Instruments K2G Industrial Communication EVM"; +- +- memory@800000000 { +- device_type = "memory"; +- reg = <0x00000008 0x00000000 0x00000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- dsp_common_memory: dsp-common-memory@81f800000 { +- compatible = "shared-dma-pool"; +- reg = <0x00000008 0x1f800000 0x00000000 0x800000>; +- reusable; +- status = "okay"; +- }; +- }; +- +- vmain: fixedregulator-vmain { +- compatible = "regulator-fixed"; +- regulator-name = "vmain_fixed"; +- regulator-min-microvolt = <24000000>; +- regulator-max-microvolt = <24000000>; +- regulator-always-on; +- }; +- +- v5_0: fixedregulator-v5_0 { +- /* TPS54531 */ +- compatible = "regulator-fixed"; +- regulator-name = "v5_0_fixed"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vmain>; +- regulator-always-on; +- }; +- +- vdd_3v3: fixedregulator-vdd_3v3 { +- /* TLV62084 */ +- compatible = "regulator-fixed"; +- regulator-name = "vdd_3v3_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&v5_0>; +- regulator-always-on; +- }; +- +- vdd_1v8: fixedregulator-vdd_1v8 { +- /* TLV62084 */ +- compatible = "regulator-fixed"; +- regulator-name = "vdd_1v8_fixed"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&v5_0>; +- regulator-always-on; +- }; +- +- vdds_ddr: fixedregulator-vdds_ddr { +- /* TLV62080 */ +- compatible = "regulator-fixed"; +- regulator-name = "vdds_ddr_fixed"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- vin-supply = <&v5_0>; +- regulator-always-on; +- }; +- +- vref_ddr: fixedregulator-vref_ddr { +- /* LP2996A */ +- compatible = "regulator-fixed"; +- regulator-name = "vref_ddr_fixed"; +- regulator-min-microvolt = <675000>; +- regulator-max-microvolt = <675000>; +- vin-supply = <&vdd_3v3>; +- regulator-always-on; +- }; +- +- vtt_ddr: fixedregulator-vtt_ddr { +- /* LP2996A */ +- compatible = "regulator-fixed"; +- regulator-name = "vtt_ddr_fixed"; +- regulator-min-microvolt = <675000>; +- regulator-max-microvolt = <675000>; +- vin-supply = <&vdd_3v3>; +- regulator-always-on; +- }; +- +- vdd_0v9: fixedregulator-vdd_0v9 { +- /* TPS62180 */ +- compatible = "regulator-fixed"; +- regulator-name = "vdd_0v9_fixed"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- vin-supply = <&v5_0>; +- regulator-always-on; +- }; +- +- vddb: fixedregulator-vddb { +- /* TPS22945 */ +- compatible = "regulator-fixed"; +- regulator-name = "vddb_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio1 53 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- gpio-decoder { +- compatible = "gpio-decoder"; +- gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>, +- <&pca9536 2 GPIO_ACTIVE_HIGH>, +- <&pca9536 1 GPIO_ACTIVE_HIGH>, +- <&pca9536 0 GPIO_ACTIVE_HIGH>; +- linux,axis = <0>; /* ABS_X */ +- decoder-max-value = <9>; +- }; +- +- leds1 { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&user_leds>; +- +- led0 { +- label = "status0:red:cpu0"; +- gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "cpu0"; +- }; +- +- led1 { +- label = "status0:green:usr"; +- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led2 { +- label = "status0:yellow:usr"; +- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led3 { +- label = "status1:red:mmc0"; +- gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "mmc0"; +- }; +- +- led4 { +- label = "status1:green:usr"; +- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led5 { +- label = "status1:yellow:usr"; +- gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led6 { +- label = "status2:red:usr"; +- gpios = <&gpio0 44 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led7 { +- label = "status2:green:usr"; +- gpios = <&gpio0 43 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led8 { +- label = "status2:yellow:usr"; +- gpios = <&gpio0 42 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led9 { +- label = "status3:red:usr"; +- gpios = <&gpio0 41 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led10 { +- label = "status3:green:usr"; +- gpios = <&gpio0 101 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led11 { +- label = "status3:yellow:usr"; +- gpios = <&gpio0 102 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led12 { +- label = "status4:green:heartbeat"; +- gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-&k2g_pinctrl { +- uart0_pins: pinmux_uart0_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */ +- K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ +- >; +- }; +- +- qspi_pins: pinmux_qspi_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */ +- K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */ +- K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */ +- K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */ +- K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */ +- K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */ +- K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x10FC) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ +- K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ +- K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ +- K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ +- K2G_CORE_IOPAD(0x110C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ +- K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ +- K2G_CORE_IOPAD(0x1114) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc1_sdcd.gpio0_69 */ +- K2G_CORE_IOPAD(0x1118) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_sdwp.mmc1_sdwp */ +- K2G_CORE_IOPAD(0x111C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_pow.mmc1_pow */ +- >; +- }; +- +- i2c0_pins: pinmux_i2c0_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ +- K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ +- K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ +- >; +- }; +- +- user_leds: pinmux_user_leds { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x102c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad11.gpio0_11 */ +- K2G_CORE_IOPAD(0x1030) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad12.gpio0_12 */ +- K2G_CORE_IOPAD(0x1034) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad13.gpio0_13 */ +- K2G_CORE_IOPAD(0x1038) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad14.gpio0_14 */ +- K2G_CORE_IOPAD(0x103c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad15.gpio0_15 */ +- K2G_CORE_IOPAD(0x1040) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_clk.gpio0_16 */ +- K2G_CORE_IOPAD(0x104c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_wen.gpio0_19 */ +- K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data9.gpio0_44 */ +- K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data10.gpio0_43 */ +- K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data11.gpio0_42 */ +- K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data12.gpio0_41 */ +- K2G_CORE_IOPAD(0x11b8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn0.gpio0_101 */ +- K2G_CORE_IOPAD(0x11bc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn1.gpio0_102 */ +- >; +- }; +- +- emac_pins: pinmux_emac_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ +- K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ +- K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ +- K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ +- K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ +- K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ +- K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ +- K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ +- K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ +- K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ +- K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ +- K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ +- >; +- }; +- +- mdio_pins: pinmux_mdio_pins { +- pinctrl-single,pins = < +- K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ +- K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ +- >; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +-&dsp0 { +- memory-region = <&dsp_common_memory>; +- status = "okay"; +-}; +- +-&qspi { +- pinctrl-names = "default"; +- pinctrl-0 = <&qspi_pins>; +- cdns,rclk-en; +- status = "okay"; +- +- flash0: m25p80@0 { +- compatible = "s25fl256s1", "jedec,spi-nor"; +- reg = <0>; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <4>; +- spi-max-frequency = <96000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- cdns,read-delay = <5>; +- cdns,tshsl-ns = <500>; +- cdns,tsd2d-ns = <500>; +- cdns,tchsh-ns = <119>; +- cdns,tslch-ns = <119>; +- +- partition@0 { +- label = "QSPI.u-boot"; +- reg = <0x00000000 0x00100000>; +- }; +- partition@1 { +- label = "QSPI.u-boot-env"; +- reg = <0x00100000 0x00040000>; +- }; +- partition@2 { +- label = "QSPI.skern"; +- reg = <0x00140000 0x0040000>; +- }; +- partition@3 { +- label = "QSPI.pmmc-firmware"; +- reg = <0x00180000 0x0040000>; +- }; +- partition@4 { +- label = "QSPI.kernel"; +- reg = <0x001c0000 0x0800000>; +- }; +- partition@5 { +- label = "QSPI.u-boot-spl-os"; +- reg = <0x009c0000 0x0040000>; +- }; +- partition@6 { +- label = "QSPI.file-system"; +- reg = <0x00a00000 0x1600000>; +- }; +- }; +-}; +- +-&gpio0 { +- status = "okay"; +-}; +- +-&gpio1 { +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <&vdd_3v3>; +- cd-gpios = <&gpio0 69 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "okay"; +- clock-frequency = <400000>; +- +- pca9536: gpio@41 { +- compatible = "ti,pca9536"; +- reg = <0x41>; +- gpio-controller; +- #gpio-cells = <2>; +- vcc-supply = <&vdd_3v3>; +- }; +-}; +- +-&qmss { +- status = "okay"; +-}; +- +-&knav_dmas { +- status = "okay"; +-}; +- +-&netcp { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_pins>; +- status = "okay"; +-}; +- +-&mdio { +- pinctrl-names = "default"; +- pinctrl-0 = <&mdio_pins>; +- status = "okay"; +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- ti,rx-internal-delay = ; +- ti,tx-internal-delay = ; +- ti,fifo-depth = ; +- ti,min-output-impedance; +- ti,dp83867-rxctrl-strap-quirk; +- }; +-}; +- +-&gbe0 { +- phy-handle = <ðphy0>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/keystone-k2g-netcp.dtsi b/scripts/dtc/include-prefixes/arm/keystone-k2g-netcp.dtsi +deleted file mode 100644 +index d0e6a9a43402..000000000000 +--- a/scripts/dtc/include-prefixes/arm/keystone-k2g-netcp.dtsi ++++ /dev/null +@@ -1,147 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for K2G Netcp driver +- * +- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ +- */ +- +-qmss: qmss@4020000 { +- compatible = "ti,66ak2g-navss-qm"; +- dma-coherent; +- #address-cells = <1>; +- #size-cells = <1>; +- power-domains = <&k2g_pds 0x0018>; +- clocks = <&k2g_clks 0x0018 0>; +- clock-names = "nss_vclk"; +- ranges; +- queue-range = <0 0x80>; +- linkram0 = <0x4020000 0x7ff>; +- status = "disabled"; +- +- qmgrs { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- qmgr0 { +- managed-queues = <0 0x80>; +- reg = <0x4100000 0x800>, +- <0x4040000 0x100>, +- <0x4080000 0x800>, +- <0x40c0000 0x800>; +- reg-names = "peek", "config", +- "region", "push"; +- }; +- +- }; +- queue-pools { +- qpend { +- qpend-0 { +- qrange = <77 8>; +- interrupts =<0 308 0xf04 0 309 0xf04 0 310 0xf04 +- 0 311 0xf04 0 312 0xf04 0 313 0xf04 +- 0 314 0xf04 0 315 0xf04>; +- qalloc-by-id; +- }; +- }; +- general-purpose { +- gp-0 { +- qrange = <112 8>; +- }; +- netcp-tx { +- qrange = <5 8>; +- qalloc-by-id; +- }; +- }; +- }; +- +- descriptor-regions { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- region-12 { +- id = <12>; +- region-spec = <1023 128>; /* num_desc desc_size */ +- link-index = <0x400>; +- }; +- }; +-}; /* qmss */ +- +-knav_dmas: knav_dmas@0 { +- compatible = "ti,keystone-navigator-dma"; +- #address-cells = <1>; +- #size-cells = <1>; +- status = "disabled"; +- power-domains = <&k2g_pds 0x0018>; +- clocks = <&k2g_clks 0x0018 0>; +- clock-names = "nss_vclk"; +- ranges; +- ti,navigator-cloud-address = <0x40c0000 0x40c0000 0x40c0000 0x40c0000>; +- +- dma_gbe: dma_gbe@0 { +- reg = <0x4010000 0x100>, +- <0x4011000 0x2a0>, /* 21 Tx channels */ +- <0x4012000 0x400>, /* 32 Rx channels */ +- <0x4010100 0x80>, +- <0x4013000 0x400>; /* 32 Rx flows */ +- reg-names = "global", "txchan", "rxchan", +- "txsched", "rxflow"; +- }; +- +-}; +- +-netcp: netcp@4000000 { +- reg = <0x2620110 0x8>; +- reg-names = "efuse"; +- compatible = "ti,netcp-1.0"; +- #address-cells = <1>; +- #size-cells = <1>; +- status = "disabled"; +- power-domains = <&k2g_pds 0x0018>; +- clocks = <&k2g_clks 0x0018 3>, <&k2g_clks 0x0018 8>; +- clock-names = "ethss_clk", "cpts"; +- +- /* NetCP address range */ +- ranges = <0 0x4000000 0x1000000>; +- +- dma-coherent; +- +- ti,navigator-dmas = <&dma_gbe 0>, <&dma_gbe 5>; +- ti,navigator-dma-names = "netrx0", "nettx"; +- +- netcp-devices { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- gbe: gbe@200000 { +- label = "netcp-gbe"; +- compatible = "ti,netcp-gbe-2"; +- reg = <0x200000 0x20>, <0x220000 0x20000>; +- enable-ale; +- tx-queue = <5>; +- tx-channel = "nettx"; +- cpts-rftclk-sel = <0>; +- cpts-ext-ts-inputs = <8>; +- +- interfaces { +- gbe0: interface-0 { +- slave-port = <0>; +- link-interface = <5>; +- }; +- }; +- }; +- }; +- +- netcp-interfaces { +- interface-0 { +- rx-channel = "netrx0"; +- rx-pool = <512 12>; +- tx-pool = <511 12>; +- rx-queue-depth = <128 128 0 0>; +- rx-buffer-size = <1518 4096 0 0>; +- rx-queue = <77>; +- tx-completion-queue = <78>; +- efuse-mac = <1>; +- netcp-gbe = <&gbe0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/keystone-k2g.dtsi b/scripts/dtc/include-prefixes/arm/keystone-k2g.dtsi +deleted file mode 100644 +index 37198294f4b2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/keystone-k2g.dtsi ++++ /dev/null +@@ -1,644 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for K2G SOC +- * +- * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "ti,k2g","ti,keystone"; +- model = "Texas Instruments K2G SoC"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&gic>; +- +- chosen { }; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- rproc0 = &dsp0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- gic: interrupt-controller@2561000 { +- compatible = "arm,gic-400", "arm,cortex-a15-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x0 0x02561000 0x0 0x1000>, +- <0x0 0x02562000 0x0 0x2000>, +- <0x0 0x02564000 0x0 0x2000>, +- <0x0 0x02566000 0x0 0x2000>; +- interrupts = ; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = +- , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,cortex-a15-pmu"; +- interrupts = ; +- }; +- +- usbphy { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "simple-bus"; +- +- usb0_phy: usb-phy@0 { +- compatible = "usb-nop-xceiv"; +- reg = <0>; +- status = "disabled"; +- }; +- +- usb1_phy: usb-phy@1 { +- compatible = "usb-nop-xceiv"; +- reg = <1>; +- status = "disabled"; +- }; +- }; +- +- soc0: soc@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- #pinctrl-cells = <1>; +- compatible = "ti,keystone","simple-bus"; +- ranges = <0x0 0x0 0x0 0xc0000000>; +- dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; +- +- msm_ram: sram@c000000 { +- compatible = "mmio-sram"; +- reg = <0x0c000000 0x100000>; +- ranges = <0x0 0x0c000000 0x100000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- bm-sram@f7000 { +- reg = <0x000f7000 0x8000>; +- }; +- }; +- +- k2g_pinctrl: pinmux@2621000 { +- compatible = "pinctrl-single"; +- reg = <0x02621000 0x410>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0x001b0007>; +- }; +- +- devctrl: device-state-control@2620000 { +- compatible = "ti,keystone-devctrl", "syscon", "simple-mfd"; +- reg = <0x02620000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x02620000 0x1000>; +- +- kirq0: keystone_irq@2a0 { +- compatible = "ti,keystone-irq"; +- reg = <0x2a0 0x10>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- ti,syscon-dev = <&devctrl 0x2a0>; +- }; +- +- dspgpio0: keystone_dsp_gpio@240 { +- compatible = "ti,keystone-dsp-gpio"; +- reg = <0x240 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio,syscon-dev = <&devctrl 0x240>; +- }; +- }; +- +- uart0: serial@2530c00 { +- compatible = "ti,da830-uart", "ns16550a"; +- current-speed = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- reg = <0x02530c00 0x100>; +- interrupts = ; +- clocks = <&k2g_clks 0x2c 0>; +- power-domains = <&k2g_pds 0x2c>; +- status = "disabled"; +- }; +- +- uart1: serial@2531000 { +- compatible = "ti,da830-uart", "ns16550a"; +- current-speed = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- reg = <0x02531000 0x100>; +- interrupts = ; +- clocks = <&k2g_clks 0x2d 0>; +- power-domains = <&k2g_pds 0x2d>; +- status = "disabled"; +- }; +- +- uart2: serial@2531400 { +- compatible = "ti,da830-uart", "ns16550a"; +- current-speed = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- reg = <0x02531400 0x100>; +- interrupts = ; +- clocks = <&k2g_clks 0x2e 0>; +- power-domains = <&k2g_pds 0x2e>; +- status = "disabled"; +- }; +- +- dcan0: can@260b200 { +- compatible = "ti,am4372-d_can", "ti,am3352-d_can"; +- reg = <0x0260B200 0x200>; +- interrupts = ; +- status = "disabled"; +- power-domains = <&k2g_pds 0x0008>; +- clocks = <&k2g_clks 0x0008 1>; +- }; +- +- dcan1: can@260b400 { +- compatible = "ti,am4372-d_can", "ti,am3352-d_can"; +- reg = <0x0260B400 0x200>; +- interrupts = ; +- status = "disabled"; +- power-domains = <&k2g_pds 0x0009>; +- clocks = <&k2g_clks 0x0009 1>; +- }; +- +- i2c0: i2c@2530000 { +- compatible = "ti,keystone-i2c"; +- reg = <0x02530000 0x400>; +- clocks = <&k2g_clks 0x003a 0>; +- power-domains = <&k2g_pds 0x003a>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@2530400 { +- compatible = "ti,keystone-i2c"; +- reg = <0x02530400 0x400>; +- clocks = <&k2g_clks 0x003b 0>; +- power-domains = <&k2g_pds 0x003b>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@2530800 { +- compatible = "ti,keystone-i2c"; +- reg = <0x02530800 0x400>; +- clocks = <&k2g_clks 0x003c 0>; +- power-domains = <&k2g_pds 0x003c>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- dsp0: dsp@10800000 { +- compatible = "ti,k2g-dsp"; +- reg = <0x10800000 0x00100000>, +- <0x10e00000 0x00008000>, +- <0x10f00000 0x00008000>; +- reg-names = "l2sram", "l1pram", "l1dram"; +- power-domains = <&k2g_pds 0x0046>; +- ti,syscon-dev = <&devctrl 0x844>; +- resets = <&k2g_reset 0x0046 0x1>; +- interrupt-parent = <&kirq0>; +- interrupts = <0 8>; +- interrupt-names = "vring", "exception"; +- kick-gpios = <&dspgpio0 27 0>; +- status = "disabled"; +- }; +- +- msgmgr: mailbox@2a00000 { +- compatible = "ti,k2g-message-manager"; +- #mbox-cells = <2>; +- reg-names = "queue_proxy_region", +- "queue_state_debug_region"; +- reg = <0x02a00000 0x400000>, <0x028c3400 0x400>; +- interrupt-names = "rx_005", +- "rx_057"; +- interrupts = , +- ; +- }; +- +- pmmc: system-controller@2921c00 { +- compatible = "ti,k2g-sci"; +- /* +- * In case of rare platforms that does not use k2g as +- * system master, use /delete-property/ +- */ +- ti,system-reboot-controller; +- mbox-names = "rx", "tx"; +- mboxes= <&msgmgr 5 2>, +- <&msgmgr 0 0>; +- reg-names = "debug_messages"; +- reg = <0x02921c00 0x400>; +- +- k2g_pds: power-controller { +- compatible = "ti,sci-pm-domain"; +- #power-domain-cells = <1>; +- }; +- +- k2g_clks: clock-controller { +- compatible = "ti,k2g-sci-clk"; +- #clock-cells = <2>; +- }; +- +- k2g_reset: reset-controller { +- compatible = "ti,sci-reset"; +- #reset-cells = <2>; +- }; +- }; +- +- gpio0: gpio@2603000 { +- compatible = "ti,k2g-gpio", "ti,keystone-gpio"; +- reg = <0x02603000 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <144>; +- ti,davinci-gpio-unbanked = <0>; +- clocks = <&k2g_clks 0x001b 0x0>; +- clock-names = "gpio"; +- }; +- +- gpio1: gpio@260a000 { +- compatible = "ti,k2g-gpio", "ti,keystone-gpio"; +- reg = <0x0260a000 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = , +- , +- , +- , +- ; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <68>; +- ti,davinci-gpio-unbanked = <0>; +- clocks = <&k2g_clks 0x001c 0x0>; +- clock-names = "gpio"; +- }; +- +- dss: dss@02540000 { +- compatible = "ti,k2g-dss"; +- reg = <0x02540000 0x400>, +- <0x02550000 0x1000>, +- <0x02557000 0x1000>, +- <0x0255a800 0x100>, +- <0x0255ac00 0x100>; +- reg-names = "cfg", "common", "vid1", "ovr1", "vp1"; +- clocks = <&k2g_clks 0x2 0>, +- <&k2g_clks 0x2 1>; +- clock-names = "fck", "vp1"; +- interrupts = ; +- +- power-domains = <&k2g_pds 0x2>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- max-memory-bandwidth = <230000000>; +- }; +- +- edma0: edma@2700000 { +- compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; +- reg = <0x02700000 0x8000>; +- reg-names = "edma3_cc"; +- interrupts = , +- , +- ; +- interrupt-names = "edma3_ccint", "emda3_mperr", +- "edma3_ccerrint"; +- dma-requests = <64>; +- #dma-cells = <2>; +- +- ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; +- +- ti,edma-memcpy-channels = <32 33 34 35>; +- +- power-domains = <&k2g_pds 0x3f>; +- }; +- +- edma0_tptc0: tptc@2760000 { +- compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; +- reg = <0x02760000 0x400>; +- power-domains = <&k2g_pds 0x3f>; +- }; +- +- edma0_tptc1: tptc@2768000 { +- compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; +- reg = <0x02768000 0x400>; +- power-domains = <&k2g_pds 0x3f>; +- }; +- +- edma1: edma@2728000 { +- compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; +- reg = <0x02728000 0x8000>; +- reg-names = "edma3_cc"; +- interrupts = , +- , +- ; +- interrupt-names = "edma3_ccint", "emda3_mperr", +- "edma3_ccerrint"; +- dma-requests = <64>; +- #dma-cells = <2>; +- +- ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>; +- +- /* +- * memcpy is disabled, can be enabled with: +- * ti,edma-memcpy-channels = <12 13 14 15>; +- * for example. +- */ +- +- power-domains = <&k2g_pds 0x4f>; +- }; +- +- edma1_tptc0: tptc@27b0000 { +- compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; +- reg = <0x027b0000 0x400>; +- power-domains = <&k2g_pds 0x4f>; +- }; +- +- edma1_tptc1: tptc@27b8000 { +- compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; +- reg = <0x027b8000 0x400>; +- power-domains = <&k2g_pds 0x4f>; +- }; +- +- mmc0: mmc@23000000 { +- compatible = "ti,k2g-sdhci"; +- reg = <0x23000000 0x400>; +- interrupts = ; +- bus-width = <4>; +- no-1-8-v; +- max-frequency = <96000000>; +- power-domains = <&k2g_pds 0xb>; +- clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>; +- clock-names = "fck", "mmchsdb_fck"; +- status = "disabled"; +- }; +- +- mmc1: mmc@23100000 { +- compatible = "ti,k2g-sdhci"; +- reg = <0x23100000 0x400>; +- interrupts = ; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- max-frequency = <96000000>; +- power-domains = <&k2g_pds 0xc>; +- clocks = <&k2g_clks 0xc 1>, <&k2g_clks 0xc 2>; +- clock-names = "fck", "mmchsdb_fck"; +- }; +- +- qspi: spi@2940000 { +- compatible = "ti,k2g-qspi", "cdns,qspi-nor"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x02940000 0x1000>, +- <0x24000000 0x4000000>; +- interrupts = ; +- cdns,fifo-depth = <256>; +- cdns,fifo-width = <4>; +- cdns,trigger-address = <0x24000000>; +- clocks = <&k2g_clks 0x43 0x0>; +- power-domains = <&k2g_pds 0x43>; +- status = "disabled"; +- }; +- +- mcasp0: mcasp@2340000 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x02340000 0x2000>, +- <0x21804000 0x1000>; +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- dmas = <&edma0 24 1>, <&edma0 25 1>; +- dma-names = "tx", "rx"; +- power-domains = <&k2g_pds 0x4>; +- clocks = <&k2g_clks 0x4 0>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- +- mcasp1: mcasp@2342000 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x02342000 0x2000>, +- <0x21804400 0x1000>; +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- dmas = <&edma1 48 1>, <&edma1 49 1>; +- dma-names = "tx", "rx"; +- power-domains = <&k2g_pds 0x5>; +- clocks = <&k2g_clks 0x5 0>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- +- mcasp2: mcasp@2344000 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x02344000 0x2000>, +- <0x21804800 0x1000>; +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- dmas = <&edma1 50 1>, <&edma1 51 1>; +- dma-names = "tx", "rx"; +- power-domains = <&k2g_pds 0x6>; +- clocks = <&k2g_clks 0x6 0>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- +- keystone_usb0: keystone-dwc3@2680000 { +- compatible = "ti,keystone-dwc3"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x2680000 0x10000>; +- interrupts = ; +- ranges; +- dma-coherent; +- dma-ranges; +- status = "disabled"; +- power-domains = <&k2g_pds 0x0016>; +- +- usb0: usb@2690000 { +- compatible = "snps,dwc3"; +- reg = <0x2690000 0x10000>; +- interrupts = ; +- maximum-speed = "high-speed"; +- dr_mode = "otg"; +- usb-phy = <&usb0_phy>; +- status = "disabled"; +- }; +- }; +- +- keystone_usb1: keystone-dwc3@2580000 { +- compatible = "ti,keystone-dwc3"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x2580000 0x10000>; +- interrupts = ; +- ranges; +- dma-coherent; +- dma-ranges; +- status = "disabled"; +- power-domains = <&k2g_pds 0x0017>; +- +- usb1: usb@2590000 { +- compatible = "snps,dwc3"; +- reg = <0x2590000 0x10000>; +- interrupts = ; +- maximum-speed = "high-speed"; +- dr_mode = "otg"; +- usb-phy = <&usb1_phy>; +- status = "disabled"; +- }; +- }; +- +- ecap0: pwm@21d1800 { +- compatible = "ti,k2g-ecap", "ti,am3352-ecap"; +- #pwm-cells = <3>; +- reg = <0x021d1800 0x60>; +- power-domains = <&k2g_pds 0x38>; +- clocks = <&k2g_clks 0x38 0>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- +- ecap1: pwm@21d1c00 { +- compatible = "ti,k2g-ecap", "ti,am3352-ecap"; +- #pwm-cells = <3>; +- reg = <0x021d1c00 0x60>; +- power-domains = <&k2g_pds 0x39>; +- clocks = <&k2g_clks 0x39 0x0>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- +- spi0: spi@21805400 { +- compatible = "ti,keystone-spi"; +- reg = <0x21805400 0x200>; +- num-cs = <4>; +- ti,davinci-spi-intr-line = <0>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&k2g_pds 0x0010>; +- clocks = <&k2g_clks 0x0010 0>; +- }; +- +- spi1: spi@21805800 { +- compatible = "ti,keystone-spi"; +- reg = <0x21805800 0x200>; +- num-cs = <4>; +- ti,davinci-spi-intr-line = <0>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&k2g_pds 0x0011>; +- clocks = <&k2g_clks 0x0011 0>; +- }; +- +- spi2: spi@21805c00 { +- compatible = "ti,keystone-spi"; +- reg = <0x21805C00 0x200>; +- num-cs = <4>; +- ti,davinci-spi-intr-line = <0>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&k2g_pds 0x0012>; +- clocks = <&k2g_clks 0x0012 0>; +- }; +- +- spi3: spi@21806000 { +- compatible = "ti,keystone-spi"; +- reg = <0x21806000 0x200>; +- num-cs = <4>; +- ti,davinci-spi-intr-line = <0>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&k2g_pds 0x0013>; +- clocks = <&k2g_clks 0x0013 0>; +- }; +- +- wdt: wdt@02250000 { +- compatible = "ti,keystone-wdt", "ti,davinci-wdt"; +- reg = <0x02250000 0x80>; +- power-domains = <&k2g_pds 0x22>; +- clocks = <&k2g_clks 0x22 0>; +- }; +- +- emif: emif@21010000 { +- compatible = "ti,emif-keystone"; +- reg = <0x21010000 0x200>; +- interrupts = ; +- }; +- +- mdio: mdio@4200f00 { +- compatible = "ti,keystone_mdio", "ti,davinci_mdio"; +- reg = <0x04200f00 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&k2g_clks 0x0018 3>; +- clock-names = "fck"; +- power-domains = <&k2g_pds 0x0018>; +- status = "disabled"; +- bus_freq = <2500000>; +- }; +- #include "keystone-k2g-netcp.dtsi" +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/keystone-k2hk-clocks.dtsi b/scripts/dtc/include-prefixes/arm/keystone-k2hk-clocks.dtsi +deleted file mode 100644 +index 4ba6912176ef..000000000000 +--- a/scripts/dtc/include-prefixes/arm/keystone-k2hk-clocks.dtsi ++++ /dev/null +@@ -1,422 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Keystone 2 Kepler/Hawking SoC clock nodes +- * +- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ +- */ +- +-clocks { +- armpllclk: armpllclk@2620370 { +- #clock-cells = <0>; +- compatible = "ti,keystone,pll-clock"; +- clocks = <&refclkarm>; +- clock-output-names = "arm-pll-clk"; +- reg = <0x02620370 4>; +- reg-names = "control"; +- }; +- +- mainpllclk: mainpllclk@2310110 { +- #clock-cells = <0>; +- compatible = "ti,keystone,main-pll-clock"; +- clocks = <&refclksys>; +- reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; +- reg-names = "control", "multiplier", "post-divider"; +- }; +- +- papllclk: papllclk@2620358 { +- #clock-cells = <0>; +- compatible = "ti,keystone,pll-clock"; +- clocks = <&refclkpass>; +- clock-output-names = "papllclk"; +- reg = <0x02620358 4>; +- reg-names = "control"; +- }; +- +- ddr3apllclk: ddr3apllclk@2620360 { +- #clock-cells = <0>; +- compatible = "ti,keystone,pll-clock"; +- clocks = <&refclkddr3a>; +- clock-output-names = "ddr-3a-pll-clk"; +- reg = <0x02620360 4>; +- reg-names = "control"; +- }; +- +- ddr3bpllclk: ddr3bpllclk@2620368 { +- #clock-cells = <0>; +- compatible = "ti,keystone,pll-clock"; +- clocks = <&refclkddr3b>; +- clock-output-names = "ddr-3b-pll-clk"; +- reg = <0x02620368 4>; +- reg-names = "control"; +- }; +- +- clktsip: clktsip@2350000 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk16>; +- clock-output-names = "tsip"; +- reg = <0x02350000 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +- +- clksrio: clksrio@235002c { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk1rstiso13>; +- clock-output-names = "srio"; +- reg = <0x0235002c 0xb00>, <0x02350010 0x400>; +- reg-names = "control", "domain"; +- domain-id = <4>; +- }; +- +- clkhyperlink0: clkhyperlink0@2350030 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk12>; +- clock-output-names = "hyperlink-0"; +- reg = <0x02350030 0xb00>, <0x02350014 0x400>; +- reg-names = "control", "domain"; +- domain-id = <5>; +- }; +- +- clkgem1: clkgem1@2350040 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk1>; +- clock-output-names = "gem1"; +- reg = <0x02350040 0xb00>, <0x02350024 0x400>; +- reg-names = "control", "domain"; +- domain-id = <9>; +- }; +- +- clkgem2: clkgem2@2350044 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk1>; +- clock-output-names = "gem2"; +- reg = <0x02350044 0xb00>, <0x02350028 0x400>; +- reg-names = "control", "domain"; +- domain-id = <10>; +- }; +- +- clkgem3: clkgem3@2350048 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk1>; +- clock-output-names = "gem3"; +- reg = <0x02350048 0xb00>, <0x0235002c 0x400>; +- reg-names = "control", "domain"; +- domain-id = <11>; +- }; +- +- clkgem4: clkgem4@235004c { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk1>; +- clock-output-names = "gem4"; +- reg = <0x0235004c 0xb00>, <0x02350030 0x400>; +- reg-names = "control", "domain"; +- domain-id = <12>; +- }; +- +- clkgem5: clkgem5@2350050 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk1>; +- clock-output-names = "gem5"; +- reg = <0x02350050 0xb00>, <0x02350034 0x400>; +- reg-names = "control", "domain"; +- domain-id = <13>; +- }; +- +- clkgem6: clkgem6@2350054 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk1>; +- clock-output-names = "gem6"; +- reg = <0x02350054 0xb00>, <0x02350038 0x400>; +- reg-names = "control", "domain"; +- domain-id = <14>; +- }; +- +- clkgem7: clkgem7@2350058 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk1>; +- clock-output-names = "gem7"; +- reg = <0x02350058 0xb00>, <0x0235003c 0x400>; +- reg-names = "control", "domain"; +- domain-id = <15>; +- }; +- +- clkddr31: clkddr31@2350060 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "ddr3-1"; +- reg = <0x02350060 0xb00>, <0x02350040 0x400>; +- reg-names = "control", "domain"; +- domain-id = <16>; +- }; +- +- clktac: clktac@2350064 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "tac"; +- reg = <0x02350064 0xb00>, <0x02350044 0x400>; +- reg-names = "control", "domain"; +- domain-id = <17>; +- }; +- +- clkrac01: clkrac01@2350068 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "rac-01"; +- reg = <0x02350068 0xb00>, <0x02350044 0x400>; +- reg-names = "control", "domain"; +- domain-id = <17>; +- }; +- +- clkrac23: clkrac23@235006c { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "rac-23"; +- reg = <0x0235006c 0xb00>, <0x02350048 0x400>; +- reg-names = "control", "domain"; +- domain-id = <18>; +- }; +- +- clkfftc0: clkfftc0@2350070 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "fftc-0"; +- reg = <0x02350070 0xb00>, <0x0235004c 0x400>; +- reg-names = "control", "domain"; +- domain-id = <19>; +- }; +- +- clkfftc1: clkfftc1@2350074 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "fftc-1"; +- reg = <0x02350074 0xb00>, <0x0235004c 0x400>; +- reg-names = "control", "domain"; +- domain-id = <19>; +- }; +- +- clkfftc2: clkfftc2@2350078 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "fftc-2"; +- reg = <0x02350078 0xb00>, <0x02350050 0x400>; +- reg-names = "control", "domain"; +- domain-id = <20>; +- }; +- +- clkfftc3: clkfftc3@235007c { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "fftc-3"; +- reg = <0x0235007c 0xb00>, <0x02350050 0x400>; +- reg-names = "control", "domain"; +- domain-id = <20>; +- }; +- +- clkfftc4: clkfftc4@2350080 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "fftc-4"; +- reg = <0x02350080 0xb00>, <0x02350050 0x400>; +- reg-names = "control", "domain"; +- domain-id = <20>; +- }; +- +- clkfftc5: clkfftc5@2350084 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "fftc-5"; +- reg = <0x02350084 0xb00>, <0x02350050 0x400>; +- reg-names = "control", "domain"; +- domain-id = <20>; +- }; +- +- clkaif: clkaif@2350088 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "aif"; +- reg = <0x02350088 0xb00>, <0x02350054 0x400>; +- reg-names = "control", "domain"; +- domain-id = <21>; +- }; +- +- clktcp3d0: clktcp3d0@235008c { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "tcp3d-0"; +- reg = <0x0235008c 0xb00>, <0x02350058 0x400>; +- reg-names = "control", "domain"; +- domain-id = <22>; +- }; +- +- clktcp3d1: clktcp3d1@2350090 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "tcp3d-1"; +- reg = <0x02350090 0xb00>, <0x02350058 0x400>; +- reg-names = "control", "domain"; +- domain-id = <22>; +- }; +- +- clktcp3d2: clktcp3d2@2350094 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "tcp3d-2"; +- reg = <0x02350094 0xb00>, <0x0235005c 0x400>; +- reg-names = "control", "domain"; +- domain-id = <23>; +- }; +- +- clktcp3d3: clktcp3d3@2350098 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "tcp3d-3"; +- reg = <0x02350098 0xb00>, <0x0235005c 0x400>; +- reg-names = "control", "domain"; +- domain-id = <23>; +- }; +- +- clkvcp0: clkvcp0@235009c { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "vcp-0"; +- reg = <0x0235009c 0xb00>, <0x02350060 0x400>; +- reg-names = "control", "domain"; +- domain-id = <24>; +- }; +- +- clkvcp1: clkvcp1@23500a0 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "vcp-1"; +- reg = <0x023500a0 0xb00>, <0x02350060 0x400>; +- reg-names = "control", "domain"; +- domain-id = <24>; +- }; +- +- clkvcp2: clkvcp2@23500a4 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "vcp-2"; +- reg = <0x023500a4 0xb00>, <0x02350060 0x400>; +- reg-names = "control", "domain"; +- domain-id = <24>; +- }; +- +- clkvcp3: clkvcp3@23500a8 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "vcp-3"; +- reg = <0x023500a8 0xb00>, <0x02350060 0x400>; +- reg-names = "control", "domain"; +- domain-id = <24>; +- }; +- +- clkvcp4: clkvcp4@23500ac { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "vcp-4"; +- reg = <0x023500ac 0xb00>, <0x02350064 0x400>; +- reg-names = "control", "domain"; +- domain-id = <25>; +- }; +- +- clkvcp5: clkvcp5@23500b0 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "vcp-5"; +- reg = <0x023500b0 0xb00>, <0x02350064 0x400>; +- reg-names = "control", "domain"; +- domain-id = <25>; +- }; +- +- clkvcp6: clkvcp6@23500b4 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "vcp-6"; +- reg = <0x023500b4 0xb00>, <0x02350064 0x400>; +- reg-names = "control", "domain"; +- domain-id = <25>; +- }; +- +- clkvcp7: clkvcp7@23500b8 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "vcp-7"; +- reg = <0x023500b8 0xb00>, <0x02350064 0x400>; +- reg-names = "control", "domain"; +- domain-id = <25>; +- }; +- +- clkbcp: clkbcp@23500bc { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "bcp"; +- reg = <0x023500bc 0xb00>, <0x02350068 0x400>; +- reg-names = "control", "domain"; +- domain-id = <26>; +- }; +- +- clkdxb: clkdxb@23500c0 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "dxb"; +- reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; +- reg-names = "control", "domain"; +- domain-id = <27>; +- }; +- +- clkhyperlink1: clkhyperlink1@23500c4 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk12>; +- clock-output-names = "hyperlink-1"; +- reg = <0x023500c4 0xb00>, <0x02350070 0x400>; +- reg-names = "control", "domain"; +- domain-id = <28>; +- }; +- +- clkxge: clkxge@23500c8 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "xge"; +- reg = <0x023500c8 0xb00>, <0x02350074 0x400>; +- reg-names = "control", "domain"; +- domain-id = <29>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/keystone-k2hk-evm.dts b/scripts/dtc/include-prefixes/arm/keystone-k2hk-evm.dts +deleted file mode 100644 +index ad4e22afe133..000000000000 +--- a/scripts/dtc/include-prefixes/arm/keystone-k2hk-evm.dts ++++ /dev/null +@@ -1,236 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Keystone 2 Kepler/Hawking EVM device tree +- * +- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "keystone.dtsi" +-#include "keystone-k2hk.dtsi" +- +-/ { +- compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone"; +- model = "Texas Instruments Keystone 2 Kepler/Hawking EVM"; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- dsp_common_memory: dsp-common-memory@81f800000 { +- compatible = "shared-dma-pool"; +- reg = <0x00000008 0x1f800000 0x00000000 0x800000>; +- reusable; +- status = "okay"; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- debug1_1 { +- label = "keystone:green:debug1"; +- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */ +- }; +- +- debug1_2 { +- label = "keystone:red:debug1"; +- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */ +- }; +- +- debug2 { +- label = "keystone:blue:debug2"; +- gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */ +- }; +- +- debug3 { +- label = "keystone:blue:debug3"; +- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */ +- }; +- }; +-}; +- +-&soc0 { +- clocks { +- refclksys: refclksys { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <122880000>; +- clock-output-names = "refclk-sys"; +- }; +- +- refclkpass: refclkpass { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <122880000>; +- clock-output-names = "refclk-pass"; +- }; +- +- refclkarm: refclkarm { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "refclk-arm"; +- }; +- +- refclkddr3a: refclkddr3a { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <100000000>; +- clock-output-names = "refclk-ddr3a"; +- }; +- +- refclkddr3b: refclkddr3b { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <100000000>; +- clock-output-names = "refclk-ddr3b"; +- }; +- }; +-}; +- +-&usb_phy { +- status = "okay"; +-}; +- +-&keystone_usb0 { +- status = "okay"; +-}; +- +-&usb0 { +- dr_mode = "host"; +-}; +- +-&aemif { +- cs0 { +- #address-cells = <2>; +- #size-cells = <1>; +- clock-ranges; +- ranges; +- +- ti,cs-chipselect = <0>; +- /* all timings in nanoseconds */ +- ti,cs-min-turnaround-ns = <12>; +- ti,cs-read-hold-ns = <6>; +- ti,cs-read-strobe-ns = <23>; +- ti,cs-read-setup-ns = <9>; +- ti,cs-write-hold-ns = <8>; +- ti,cs-write-strobe-ns = <23>; +- ti,cs-write-setup-ns = <8>; +- +- nand@0,0 { +- compatible = "ti,keystone-nand","ti,davinci-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0 0 0x4000000 +- 1 0 0x0000100>; +- +- ti,davinci-chipselect = <0>; +- ti,davinci-mask-ale = <0x2000>; +- ti,davinci-mask-cle = <0x4000>; +- ti,davinci-mask-chipsel = <0>; +- nand-ecc-mode = "hw"; +- ti,davinci-ecc-bits = <4>; +- nand-on-flash-bbt; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0 0x100000>; +- read-only; +- }; +- +- partition@100000 { +- label = "params"; +- reg = <0x100000 0x80000>; +- read-only; +- }; +- +- partition@180000 { +- label = "ubifs"; +- reg = <0x180000 0x1fe80000>; +- }; +- }; +- }; +-}; +- +-&i2c0 { +- dtt@50 { +- compatible = "atmel,24c1024"; +- reg = <0x50>; +- }; +-}; +- +-&spi0 { +- nor_flash: n25q128a11@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "Micron,n25q128a11"; +- spi-max-frequency = <54000000>; +- m25p,fast-read; +- reg = <0>; +- +- partition@0 { +- label = "u-boot-spl"; +- reg = <0x0 0x80000>; +- read-only; +- }; +- +- partition@1 { +- label = "misc"; +- reg = <0x80000 0xf80000>; +- }; +- }; +-}; +- +-&mdio { +- status = "ok"; +- ethphy0: ethernet-phy@0 { +- compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&dsp0 { +- memory-region = <&dsp_common_memory>; +- status = "okay"; +-}; +- +-&dsp1 { +- memory-region = <&dsp_common_memory>; +- status = "okay"; +-}; +- +-&dsp2 { +- memory-region = <&dsp_common_memory>; +- status = "okay"; +-}; +- +-&dsp3 { +- memory-region = <&dsp_common_memory>; +- status = "okay"; +-}; +- +-&dsp4 { +- memory-region = <&dsp_common_memory>; +- status = "okay"; +-}; +- +-&dsp5 { +- memory-region = <&dsp_common_memory>; +- status = "okay"; +-}; +- +-&dsp6 { +- memory-region = <&dsp_common_memory>; +- status = "okay"; +-}; +- +-&dsp7 { +- memory-region = <&dsp_common_memory>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/keystone-k2hk-netcp.dtsi b/scripts/dtc/include-prefixes/arm/keystone-k2hk-netcp.dtsi +deleted file mode 100644 +index 022d93c366c7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/keystone-k2hk-netcp.dtsi ++++ /dev/null +@@ -1,266 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for Keystone 2 Hawking Netcp driver +- * +- * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ +- */ +- +-qmss: qmss@2a40000 { +- compatible = "ti,keystone-navigator-qmss"; +- dma-coherent; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&chipclk13>; +- ranges; +- queue-range = <0 0x4000>; +- linkram0 = <0x100000 0x8000>; +- linkram1 = <0x0 0x10000>; +- +- qmgrs { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- qmgr0 { +- managed-queues = <0 0x2000>; +- reg = <0x2a40000 0x20000>, +- <0x2a06000 0x400>, +- <0x2a02000 0x1000>, +- <0x2a03000 0x1000>, +- <0x23a80000 0x20000>, +- <0x2a80000 0x20000>; +- reg-names = "peek", "status", "config", +- "region", "push", "pop"; +- }; +- +- qmgr1 { +- managed-queues = <0x2000 0x2000>; +- reg = <0x2a60000 0x20000>, +- <0x2a06400 0x400>, +- <0x2a04000 0x1000>, +- <0x2a05000 0x1000>, +- <0x23aa0000 0x20000>, +- <0x2aa0000 0x20000>; +- reg-names = "peek", "status", "config", +- "region", "push", "pop"; +- }; +- }; +- +- queue-pools { +- qpend { +- qpend-0 { +- qrange = <658 8>; +- interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 +- 0 43 0xf04 0 44 0xf04 0 45 0xf04 +- 0 46 0xf04 0 47 0xf04>; +- }; +- qpend-1 { +- qrange = <8704 16>; +- interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 +- 0 51 0xf04 0 52 0xf04 0 53 0xf04 +- 0 54 0xf04 0 55 0xf04 0 56 0xf04 +- 0 57 0xf04 0 58 0xf04 0 59 0xf04 +- 0 60 0xf04 0 61 0xf04 0 62 0xf04 +- 0 63 0xf04>; +- qalloc-by-id; +- }; +- qpend-2 { +- qrange = <8720 16>; +- interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 +- 0 59 0xf04 0 68 0xf04 0 69 0xf04 +- 0 70 0xf04 0 71 0xf04 0 72 0xf04 +- 0 73 0xf04 0 74 0xf04 0 75 0xf04 +- 0 76 0xf04 0 77 0xf04 0 78 0xf04 +- 0 79 0xf04>; +- }; +- }; +- general-purpose { +- gp-0 { +- qrange = <4000 64>; +- }; +- netcp-tx { +- qrange = <640 9>; +- qalloc-by-id; +- }; +- netcpx-tx { +- qrange = <8752 8>; +- qalloc-by-id; +- }; +- }; +- accumulator { +- acc-low-0 { +- qrange = <480 32>; +- accumulator = <0 47 16 2 50>; +- interrupts = <0 226 0xf01>; +- multi-queue; +- qalloc-by-id; +- }; +- }; +- }; +- +- descriptor-regions { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- region-12 { +- id = <12>; +- region-spec = <8192 128>; /* num_desc desc_size */ +- link-index = <0x4000>; +- }; +- }; +- +- pdsps { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- pdsp0@2a10000 { +- reg = <0x2a10000 0x1000 /*iram */ +- 0x2a0f000 0x100 /*reg*/ +- 0x2a0c000 0x3c8 /*intd */ +- 0x2a20000 0x4000>; /*cmd*/ +- id = <0>; +- }; +- }; +-}; /* qmss */ +- +-knav_dmas: knav_dmas@0 { +- compatible = "ti,keystone-navigator-dma"; +- clocks = <&papllclk>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- ti,navigator-cloud-address = <0x23a80000 0x23a90000 +- 0x23aa0000 0x23ab0000>; +- +- dma_gbe: dma_gbe@0 { +- reg = <0x2004000 0x100>, +- <0x2004400 0x120>, +- <0x2004800 0x300>, +- <0x2004c00 0x120>, +- <0x2005000 0x400>; +- reg-names = "global", "txchan", "rxchan", +- "txsched", "rxflow"; +- }; +-}; +- +-netcp: netcp@2000000 { +- reg = <0x2620110 0x8>; +- reg-names = "efuse"; +- compatible = "ti,netcp-1.0"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* NetCP address range */ +- ranges = <0 0x2000000 0x100000>; +- +- clocks = <&clkpa>, <&clkcpgmac>; +- clock-names = "pa_clk", "ethss_clk"; +- dma-coherent; +- +- ti,navigator-dmas = <&dma_gbe 22>, +- <&dma_gbe 23>, +- <&dma_gbe 8>; +- ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; +- +- netcp-devices { +- ranges; +- #address-cells = <1>; +- #size-cells = <1>; +- gbe@90000 { /* ETHSS */ +- #address-cells = <1>; +- #size-cells = <1>; +- label = "netcp-gbe"; +- compatible = "ti,netcp-gbe"; +- reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>; +- /* enable-ale; */ +- tx-queue = <648>; +- tx-channel = "nettx"; +- +- cpts { +- clocks = <&cpts_refclk_mux>; +- clock-names = "cpts"; +- +- cpts_refclk_mux: cpts-refclk-mux { +- #clock-cells = <0>; +- clocks = <&chipclk12>, <&chipclk13>, +- <&timi0>, <&timi1>, +- <&tsrefclk>; +- ti,mux-tbl = <0x0>, <0x1>, <0x2>, +- <0x3>, <0x8>; +- assigned-clocks = <&cpts_refclk_mux>; +- assigned-clock-parents = <&chipclk12>; +- }; +- }; +- +- interfaces { +- gbe0: interface-0 { +- slave-port = <0>; +- link-interface = <1>; +- phy-handle = <ðphy0>; +- }; +- gbe1: interface-1 { +- slave-port = <1>; +- link-interface = <1>; +- phy-handle = <ðphy1>; +- }; +- }; +- +- secondary-slave-ports { +- port-2 { +- slave-port = <2>; +- link-interface = <2>; +- }; +- port-3 { +- slave-port = <3>; +- link-interface = <2>; +- }; +- }; +- }; +- }; +- +- netcp-interfaces { +- interface-0 { +- rx-channel = "netrx0"; +- rx-pool = <1024 12>; +- tx-pool = <1024 12>; +- rx-queue-depth = <128 128 0 0>; +- rx-buffer-size = <1518 4096 0 0>; +- rx-queue = <8704>; +- tx-completion-queue = <8706>; +- efuse-mac = <1>; +- netcp-gbe = <&gbe0>; +- +- }; +- interface-1 { +- rx-channel = "netrx1"; +- rx-pool = <1024 12>; +- tx-pool = <1024 12>; +- rx-queue-depth = <128 128 0 0>; +- rx-buffer-size = <1518 4096 0 0>; +- rx-queue = <8705>; +- tx-completion-queue = <8707>; +- efuse-mac = <0>; +- local-mac-address = [02 18 31 7e 3e 6f]; +- netcp-gbe = <&gbe1>; +- }; +- }; +-}; +- +-sa_subsys: subsys@20c0000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x20c0000 0x40000>; +- +- sa_config: subsys@0 { +- compatible = "syscon"; +- reg = <0x0 0x100>; +- }; +- +- rng@24000 { +- compatible = "ti,keystone-rng"; +- reg = <0x24000 0x1000>; +- ti,syscon-sa-cfg = <&sa_config>; +- clocks = <&clksa>; +- clock-names = "fck"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/keystone-k2hk.dtsi b/scripts/dtc/include-prefixes/arm/keystone-k2hk.dtsi +deleted file mode 100644 +index 8a9447703310..000000000000 +--- a/scripts/dtc/include-prefixes/arm/keystone-k2hk.dtsi ++++ /dev/null +@@ -1,295 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Keystone 2 Kepler/Hawking soc specific device tree +- * +- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ +- */ +- +-#include +- +-/ { +- compatible = "ti,k2hk", "ti,keystone"; +- model = "Texas Instruments Keystone 2 Kepler/Hawking SoC"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- interrupt-parent = <&gic>; +- +- cpu@0 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- reg = <0>; +- }; +- +- cpu@1 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- reg = <1>; +- }; +- +- cpu@2 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- reg = <2>; +- }; +- +- cpu@3 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- reg = <3>; +- }; +- }; +- +- aliases { +- rproc0 = &dsp0; +- rproc1 = &dsp1; +- rproc2 = &dsp2; +- rproc3 = &dsp3; +- rproc4 = &dsp4; +- rproc5 = &dsp5; +- rproc6 = &dsp6; +- rproc7 = &dsp7; +- }; +-}; +- +-&soc0 { +- /include/ "keystone-k2hk-clocks.dtsi" +- +- msm_ram: sram@c000000 { +- compatible = "mmio-sram"; +- reg = <0x0c000000 0x600000>; +- ranges = <0x0 0x0c000000 0x600000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- bm-sram@5f0000 { +- reg = <0x5f0000 0x8000>; +- }; +- }; +- +- psc: power-sleep-controller@2350000 { +- pscrst: reset-controller { +- compatible = "ti,k2hk-pscrst", "ti,syscon-reset"; +- #reset-cells = <1>; +- +- ti,reset-bits = < +- 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ +- 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */ +- 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */ +- 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */ +- 0xa4c 8 0xa4c 8 0x84c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 4: dsp4 */ +- 0xa50 8 0xa50 8 0x850 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 5: dsp5 */ +- 0xa54 8 0xa54 8 0x854 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 6: dsp6 */ +- 0xa58 8 0xa58 8 0x858 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 7: dsp7 */ +- >; +- }; +- }; +- +- devctrl: device-state-control@2620000 { +- dspgpio0: keystone_dsp_gpio@240 { +- compatible = "ti,keystone-dsp-gpio"; +- reg = <0x240 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio,syscon-dev = <&devctrl 0x240>; +- }; +- +- dspgpio1: keystone_dsp_gpio@244 { +- compatible = "ti,keystone-dsp-gpio"; +- reg = <0x244 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio,syscon-dev = <&devctrl 0x244>; +- }; +- +- dspgpio2: keystone_dsp_gpio@248 { +- compatible = "ti,keystone-dsp-gpio"; +- reg = <0x248 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio,syscon-dev = <&devctrl 0x248>; +- }; +- +- dspgpio3: keystone_dsp_gpio@24c { +- compatible = "ti,keystone-dsp-gpio"; +- reg = <0x24c 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio,syscon-dev = <&devctrl 0x24c>; +- }; +- +- dspgpio4: keystone_dsp_gpio@250 { +- compatible = "ti,keystone-dsp-gpio"; +- reg = <0x250 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio,syscon-dev = <&devctrl 0x250>; +- }; +- +- dspgpio5: keystone_dsp_gpio@254 { +- compatible = "ti,keystone-dsp-gpio"; +- reg = <0x254 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio,syscon-dev = <&devctrl 0x254>; +- }; +- +- dspgpio6: keystone_dsp_gpio@258 { +- compatible = "ti,keystone-dsp-gpio"; +- reg = <0x258 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio,syscon-dev = <&devctrl 0x258>; +- }; +- +- dspgpio7: keystone_dsp_gpio@25c { +- compatible = "ti,keystone-dsp-gpio"; +- reg = <0x25c 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio,syscon-dev = <&devctrl 0x25c>; +- }; +- }; +- +- dsp0: dsp@10800000 { +- compatible = "ti,k2hk-dsp"; +- reg = <0x10800000 0x00100000>, +- <0x10e00000 0x00008000>, +- <0x10f00000 0x00008000>; +- reg-names = "l2sram", "l1pram", "l1dram"; +- clocks = <&clkgem0>; +- ti,syscon-dev = <&devctrl 0x40>; +- resets = <&pscrst 0>; +- interrupt-parent = <&kirq0>; +- interrupts = <0 8>; +- interrupt-names = "vring", "exception"; +- kick-gpios = <&dspgpio0 27 0>; +- status = "disabled"; +- }; +- +- dsp1: dsp@11800000 { +- compatible = "ti,k2hk-dsp"; +- reg = <0x11800000 0x00100000>, +- <0x11e00000 0x00008000>, +- <0x11f00000 0x00008000>; +- reg-names = "l2sram", "l1pram", "l1dram"; +- clocks = <&clkgem1>; +- ti,syscon-dev = <&devctrl 0x44>; +- resets = <&pscrst 1>; +- interrupt-parent = <&kirq0>; +- interrupts = <1 9>; +- interrupt-names = "vring", "exception"; +- kick-gpios = <&dspgpio1 27 0>; +- status = "disabled"; +- }; +- +- dsp2: dsp@12800000 { +- compatible = "ti,k2hk-dsp"; +- reg = <0x12800000 0x00100000>, +- <0x12e00000 0x00008000>, +- <0x12f00000 0x00008000>; +- reg-names = "l2sram", "l1pram", "l1dram"; +- clocks = <&clkgem2>; +- ti,syscon-dev = <&devctrl 0x48>; +- resets = <&pscrst 2>; +- interrupt-parent = <&kirq0>; +- interrupts = <2 10>; +- interrupt-names = "vring", "exception"; +- kick-gpios = <&dspgpio2 27 0>; +- status = "disabled"; +- }; +- +- dsp3: dsp@13800000 { +- compatible = "ti,k2hk-dsp"; +- reg = <0x13800000 0x00100000>, +- <0x13e00000 0x00008000>, +- <0x13f00000 0x00008000>; +- reg-names = "l2sram", "l1pram", "l1dram"; +- clocks = <&clkgem3>; +- ti,syscon-dev = <&devctrl 0x4c>; +- resets = <&pscrst 3>; +- interrupt-parent = <&kirq0>; +- interrupts = <3 11>; +- interrupt-names = "vring", "exception"; +- kick-gpios = <&dspgpio3 27 0>; +- status = "disabled"; +- }; +- +- dsp4: dsp@14800000 { +- compatible = "ti,k2hk-dsp"; +- reg = <0x14800000 0x00100000>, +- <0x14e00000 0x00008000>, +- <0x14f00000 0x00008000>; +- reg-names = "l2sram", "l1pram", "l1dram"; +- clocks = <&clkgem4>; +- ti,syscon-dev = <&devctrl 0x50>; +- resets = <&pscrst 4>; +- interrupt-parent = <&kirq0>; +- interrupts = <4 12>; +- interrupt-names = "vring", "exception"; +- kick-gpios = <&dspgpio4 27 0>; +- status = "disabled"; +- }; +- +- dsp5: dsp@15800000 { +- compatible = "ti,k2hk-dsp"; +- reg = <0x15800000 0x00100000>, +- <0x15e00000 0x00008000>, +- <0x15f00000 0x00008000>; +- reg-names = "l2sram", "l1pram", "l1dram"; +- clocks = <&clkgem5>; +- ti,syscon-dev = <&devctrl 0x54>; +- resets = <&pscrst 5>; +- interrupt-parent = <&kirq0>; +- interrupts = <5 13>; +- interrupt-names = "vring", "exception"; +- kick-gpios = <&dspgpio5 27 0>; +- status = "disabled"; +- }; +- +- dsp6: dsp@16800000 { +- compatible = "ti,k2hk-dsp"; +- reg = <0x16800000 0x00100000>, +- <0x16e00000 0x00008000>, +- <0x16f00000 0x00008000>; +- reg-names = "l2sram", "l1pram", "l1dram"; +- clocks = <&clkgem6>; +- ti,syscon-dev = <&devctrl 0x58>; +- resets = <&pscrst 6>; +- interrupt-parent = <&kirq0>; +- interrupts = <6 14>; +- interrupt-names = "vring", "exception"; +- kick-gpios = <&dspgpio6 27 0>; +- status = "disabled"; +- }; +- +- dsp7: dsp@17800000 { +- compatible = "ti,k2hk-dsp"; +- reg = <0x17800000 0x00100000>, +- <0x17e00000 0x00008000>, +- <0x17f00000 0x00008000>; +- reg-names = "l2sram", "l1pram", "l1dram"; +- clocks = <&clkgem7>; +- ti,syscon-dev = <&devctrl 0x5c>; +- resets = <&pscrst 7>; +- interrupt-parent = <&kirq0>; +- interrupts = <7 15>; +- interrupt-names = "vring", "exception"; +- kick-gpios = <&dspgpio7 27 0>; +- status = "disabled"; +- }; +- +- mdio: mdio@2090300 { +- compatible = "ti,keystone_mdio", "ti,davinci_mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x02090300 0x100>; +- status = "disabled"; +- clocks = <&clkcpgmac>; +- clock-names = "fck"; +- bus_freq = <2500000>; +- }; +- /include/ "keystone-k2hk-netcp.dtsi" +-}; +diff --git a/scripts/dtc/include-prefixes/arm/keystone-k2l-clocks.dtsi b/scripts/dtc/include-prefixes/arm/keystone-k2l-clocks.dtsi +deleted file mode 100644 +index 635528064dea..000000000000 +--- a/scripts/dtc/include-prefixes/arm/keystone-k2l-clocks.dtsi ++++ /dev/null +@@ -1,263 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Keystone 2 lamarr SoC clock nodes +- * +- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ +- */ +- +-clocks { +- armpllclk: armpllclk@2620370 { +- #clock-cells = <0>; +- compatible = "ti,keystone,pll-clock"; +- clocks = <&refclksys>; +- clock-output-names = "arm-pll-clk"; +- reg = <0x02620370 4>; +- reg-names = "control"; +- }; +- +- mainpllclk: mainpllclk@2310110 { +- #clock-cells = <0>; +- compatible = "ti,keystone,main-pll-clock"; +- clocks = <&refclksys>; +- reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; +- reg-names = "control", "multiplier", "post-divider"; +- }; +- +- papllclk: papllclk@2620358 { +- #clock-cells = <0>; +- compatible = "ti,keystone,pll-clock"; +- clocks = <&refclksys>; +- clock-output-names = "papllclk"; +- reg = <0x02620358 4>; +- reg-names = "control"; +- }; +- +- ddr3apllclk: ddr3apllclk@2620360 { +- #clock-cells = <0>; +- compatible = "ti,keystone,pll-clock"; +- clocks = <&refclksys>; +- clock-output-names = "ddr-3a-pll-clk"; +- reg = <0x02620360 4>; +- reg-names = "control"; +- }; +- +- clkdfeiqnsys: clkdfeiqnsys@2350004 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk12>; +- clock-output-names = "dfe"; +- reg-names = "control", "domain"; +- reg = <0x02350004 0xb00>, <0x02350000 0x400>; +- domain-id = <0>; +- }; +- +- clkpcie1: clkpcie1@235002c { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk12>; +- clock-output-names = "pcie"; +- reg = <0x0235002c 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <4>; +- }; +- +- clkgem1: clkgem1@2350040 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk1>; +- clock-output-names = "gem1"; +- reg = <0x02350040 0xb00>, <0x02350024 0x400>; +- reg-names = "control", "domain"; +- domain-id = <9>; +- }; +- +- clkgem2: clkgem2@2350044 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk1>; +- clock-output-names = "gem2"; +- reg = <0x02350044 0xb00>, <0x02350028 0x400>; +- reg-names = "control", "domain"; +- domain-id = <10>; +- }; +- +- clkgem3: clkgem3@2350048 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk1>; +- clock-output-names = "gem3"; +- reg = <0x02350048 0xb00>, <0x0235002c 0x400>; +- reg-names = "control", "domain"; +- domain-id = <11>; +- }; +- +- clktac: clktac@2350064 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "tac"; +- reg = <0x02350064 0xb00>, <0x02350044 0x400>; +- reg-names = "control", "domain"; +- domain-id = <17>; +- }; +- +- clkrac: clkrac@2350068 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "rac"; +- reg = <0x02350068 0xb00>, <0x02350044 0x400>; +- reg-names = "control", "domain"; +- domain-id = <17>; +- }; +- +- clkdfepd0: clkdfepd0@235006c { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "dfe-pd0"; +- reg = <0x0235006c 0xb00>, <0x02350044 0x400>; +- reg-names = "control", "domain"; +- domain-id = <18>; +- }; +- +- clkfftc0: clkfftc0@2350070 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "fftc-0"; +- reg = <0x02350070 0xb00>, <0x0235004c 0x400>; +- reg-names = "control", "domain"; +- domain-id = <19>; +- }; +- +- clkosr: clkosr@2350088 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "osr"; +- reg = <0x02350088 0xb00>, <0x0235004c 0x400>; +- reg-names = "control", "domain"; +- domain-id = <21>; +- }; +- +- clktcp3d0: clktcp3d0@235008c { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "tcp3d-0"; +- reg = <0x0235008c 0xb00>, <0x02350058 0x400>; +- reg-names = "control", "domain"; +- domain-id = <22>; +- }; +- +- clktcp3d1: clktcp3d1@2350094 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "tcp3d-1"; +- reg = <0x02350094 0xb00>, <0x02350058 0x400>; +- reg-names = "control", "domain"; +- domain-id = <23>; +- }; +- +- clkvcp0: clkvcp0@235009c { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "vcp-0"; +- reg = <0x0235009c 0xb00>, <0x02350060 0x400>; +- reg-names = "control", "domain"; +- domain-id = <24>; +- }; +- +- clkvcp1: clkvcp1@23500a0 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "vcp-1"; +- reg = <0x023500a0 0xb00>, <0x02350060 0x400>; +- reg-names = "control", "domain"; +- domain-id = <24>; +- }; +- +- clkvcp2: clkvcp2@23500a4 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "vcp-2"; +- reg = <0x023500a4 0xb00>, <0x02350060 0x400>; +- reg-names = "control", "domain"; +- domain-id = <24>; +- }; +- +- clkvcp3: clkvcp3@23500a8 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "vcp-3"; +- reg = <0x023500a8 0xb00>, <0x02350060 0x400>; +- reg-names = "control", "domain"; +- domain-id = <24>; +- }; +- +- clkbcp: clkbcp@23500bc { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "bcp"; +- reg = <0x023500bc 0xb00>, <0x02350068 0x400>; +- reg-names = "control", "domain"; +- domain-id = <26>; +- }; +- +- clkdfepd1: clkdfepd1@23500c0 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "dfe-pd1"; +- reg = <0x023500c0 0xb00>, <0x02350044 0x400>; +- reg-names = "control", "domain"; +- domain-id = <27>; +- }; +- +- clkfftc1: clkfftc1@23500c4 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "fftc-1"; +- reg = <0x023500c4 0xb00>, <0x023504c0 0x400>; +- reg-names = "control", "domain"; +- domain-id = <28>; +- }; +- +- clkiqnail: clkiqnail@23500c8 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&chipclk13>; +- clock-output-names = "iqn-ail"; +- reg = <0x023500c8 0xb00>, <0x0235004c 0x400>; +- reg-names = "control", "domain"; +- domain-id = <29>; +- }; +- +- clkuart2: clkuart2@2350000 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&clkmodrst0>; +- clock-output-names = "uart2"; +- reg = <0x02350000 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +- +- clkuart3: clkuart3@2350000 { +- #clock-cells = <0>; +- compatible = "ti,keystone,psc-clock"; +- clocks = <&clkmodrst0>; +- clock-output-names = "uart3"; +- reg = <0x02350000 0xb00>, <0x02350000 0x400>; +- reg-names = "control", "domain"; +- domain-id = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/keystone-k2l-evm.dts b/scripts/dtc/include-prefixes/arm/keystone-k2l-evm.dts +deleted file mode 100644 +index e200533d26a4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/keystone-k2l-evm.dts ++++ /dev/null +@@ -1,165 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Keystone 2 Lamarr EVM device tree +- * +- * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "keystone.dtsi" +-#include "keystone-k2l.dtsi" +- +-/ { +- compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone"; +- model = "Texas Instruments Keystone 2 Lamarr EVM"; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- dsp_common_memory: dsp-common-memory@81f800000 { +- compatible = "shared-dma-pool"; +- reg = <0x00000008 0x1f800000 0x00000000 0x800000>; +- reusable; +- status = "okay"; +- }; +- }; +-}; +- +-&soc0 { +- clocks { +- refclksys: refclksys { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <122880000>; +- clock-output-names = "refclk-sys"; +- }; +- }; +-}; +- +-&usb_phy { +- status = "okay"; +-}; +- +-&keystone_usb0 { +- status = "okay"; +-}; +- +-&usb0 { +- dr_mode = "host"; +-}; +- +-&i2c0 { +- dtt@50 { +- compatible = "atmel,24c1024"; +- reg = <0x50>; +- }; +-}; +- +-&aemif { +- cs0 { +- #address-cells = <2>; +- #size-cells = <1>; +- clock-ranges; +- ranges; +- +- ti,cs-chipselect = <0>; +- /* all timings in nanoseconds */ +- ti,cs-min-turnaround-ns = <12>; +- ti,cs-read-hold-ns = <6>; +- ti,cs-read-strobe-ns = <23>; +- ti,cs-read-setup-ns = <9>; +- ti,cs-write-hold-ns = <8>; +- ti,cs-write-strobe-ns = <23>; +- ti,cs-write-setup-ns = <8>; +- +- nand@0,0 { +- compatible = "ti,keystone-nand","ti,davinci-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0 0 0x4000000 +- 1 0 0x0000100>; +- +- ti,davinci-chipselect = <0>; +- ti,davinci-mask-ale = <0x2000>; +- ti,davinci-mask-cle = <0x4000>; +- ti,davinci-mask-chipsel = <0>; +- nand-ecc-mode = "hw"; +- ti,davinci-ecc-bits = <4>; +- nand-on-flash-bbt; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0 0x100000>; +- read-only; +- }; +- +- partition@100000 { +- label = "params"; +- reg = <0x100000 0x80000>; +- read-only; +- }; +- +- partition@180000 { +- label = "ubifs"; +- reg = <0x180000 0x7FE80000>; +- }; +- }; +- }; +-}; +- +-&spi0 { +- nor_flash: n25q128a11@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "Micron,n25q128a11"; +- spi-max-frequency = <54000000>; +- m25p,fast-read; +- reg = <0>; +- +- partition@0 { +- label = "u-boot-spl"; +- reg = <0x0 0x80000>; +- read-only; +- }; +- +- partition@1 { +- label = "misc"; +- reg = <0x80000 0xf80000>; +- }; +- }; +-}; +- +-&mdio { +- status = "ok"; +- ethphy0: ethernet-phy@0 { +- compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&dsp0 { +- memory-region = <&dsp_common_memory>; +- status = "okay"; +-}; +- +-&dsp1 { +- memory-region = <&dsp_common_memory>; +- status = "okay"; +-}; +- +-&dsp2 { +- memory-region = <&dsp_common_memory>; +- status = "okay"; +-}; +- +-&dsp3 { +- memory-region = <&dsp_common_memory>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/keystone-k2l-netcp.dtsi b/scripts/dtc/include-prefixes/arm/keystone-k2l-netcp.dtsi +deleted file mode 100644 +index e96ca664abc2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/keystone-k2l-netcp.dtsi ++++ /dev/null +@@ -1,246 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for Keystone 2 Lamarr Netcp driver +- * +- * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ +- */ +- +-qmss: qmss@2a40000 { +- compatible = "ti,keystone-navigator-qmss"; +- dma-coherent; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&chipclk13>; +- ranges; +- queue-range = <0 0x2000>; +- linkram0 = <0x100000 0x4000>; +- linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */ +- +- qmgrs { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- qmgr0 { +- managed-queues = <0 0x2000>; +- reg = <0x2a40000 0x20000>, +- <0x2a06000 0x400>, +- <0x2a02000 0x1000>, +- <0x2a03000 0x1000>, +- <0x23a80000 0x20000>, +- <0x2a80000 0x20000>; +- reg-names = "peek", "status", "config", +- "region", "push", "pop"; +- }; +- }; +- queue-pools { +- qpend { +- qpend-0 { +- qrange = <658 8>; +- interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 +- 0 43 0xf04 0 44 0xf04 0 45 0xf04 +- 0 46 0xf04 0 47 0xf04>; +- }; +- qpend-1 { +- qrange = <528 16>; +- interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 +- 0 51 0xf04 0 52 0xf04 0 53 0xf04 +- 0 54 0xf04 0 55 0xf04 0 56 0xf04 +- 0 57 0xf04 0 58 0xf04 0 59 0xf04 +- 0 60 0xf04 0 61 0xf04 0 62 0xf04 +- 0 63 0xf04>; +- qalloc-by-id; +- }; +- qpend-2 { +- qrange = <544 16>; +- interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 +- 0 59 0xf04 0 68 0xf04 0 69 0xf04 +- 0 70 0xf04 0 71 0xf04 0 72 0xf04 +- 0 73 0xf04 0 74 0xf04 0 75 0xf04 +- 0 76 0xf04 0 77 0xf04 0 78 0xf04 +- 0 79 0xf04>; +- }; +- }; +- general-purpose { +- gp-0 { +- qrange = <4000 64>; +- }; +- netcp-tx { +- qrange = <896 128>; +- qalloc-by-id; +- }; +- }; +- accumulator { +- acc-low-0 { +- qrange = <480 32>; +- accumulator = <0 47 16 2 50>; +- interrupts = <0 226 0xf01>; +- multi-queue; +- }; +- }; +- }; +- +- descriptor-regions { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- region-12 { +- id = <12>; +- region-spec = <8192 128>; /* num_desc desc_size */ +- link-index = <0x4000>; +- }; +- }; +- +- pdsps { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- pdsp0@2a10000 { +- reg = <0x2a10000 0x1000 /*iram */ +- 0x2a0f000 0x100 /*reg*/ +- 0x2a0c000 0x3c8 /*intd */ +- 0x2a20000 0x4000>; /*cmd*/ +- id = <0>; +- }; +- }; +- +-}; /* qmss */ +- +-knav_dmas: knav_dmas@0 { +- compatible = "ti,keystone-navigator-dma"; +- clocks = <&papllclk>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- ti,navigator-cloud-address = <0x23a80000 0x23a90000>; +- +- dma_gbe: dma_gbe@0 { +- reg = <0x26186000 0x100>, +- <0x26187000 0x2a0>, +- <0x26188000 0xb60>, +- <0x26186100 0x80>, +- <0x26189000 0x1000>; +- reg-names = "global", "txchan", "rxchan", +- "txsched", "rxflow"; +- }; +-}; +- +-netcp: netcp@26000000 { +- reg = <0x2620110 0x8>; +- reg-names = "efuse"; +- compatible = "ti,netcp-1.0"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* NetCP address range */ +- ranges = <0 0x26000000 0x1000000>; +- +- clocks = <&clkpa>, <&clkcpgmac>; +- clock-names = "pa_clk", "ethss_clk"; +- dma-coherent; +- +- ti,navigator-dmas = <&dma_gbe 0>, +- <&dma_gbe 8>, +- <&dma_gbe 0>; +- ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; +- +- netcp-devices { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- gbe@200000 { /* ETHSS */ +- label = "netcp-gbe"; +- compatible = "ti,netcp-gbe-5"; +- reg = <0x200000 0x900>, <0x220000 0x20000>; +- /* enable-ale; */ +- tx-queue = <896>; +- tx-channel = "nettx"; +- +- cpts { +- clocks = <&cpts_refclk_mux>; +- clock-names = "cpts"; +- +- cpts_refclk_mux: cpts-refclk-mux { +- #clock-cells = <0>; +- clocks = <&chipclk12>, <&chipclk13>, +- <&timi0>, <&timi1>, +- <&tsrefclk>; +- ti,mux-tbl = <0x0>, <0x1>, <0x2>, +- <0x3>, <0x8>; +- assigned-clocks = <&cpts_refclk_mux>; +- assigned-clock-parents = <&chipclk12>; +- }; +- }; +- +- interfaces { +- gbe0: interface-0 { +- slave-port = <0>; +- link-interface = <1>; +- phy-handle = <ðphy0>; +- }; +- gbe1: interface-1 { +- slave-port = <1>; +- link-interface = <1>; +- phy-handle = <ðphy1>; +- }; +- }; +- +- secondary-slave-ports { +- port-2 { +- slave-port = <2>; +- link-interface = <2>; +- }; +- port-3 { +- slave-port = <3>; +- link-interface = <2>; +- }; +- }; +- }; +- }; +- +- netcp-interfaces { +- interface-0 { +- rx-channel = "netrx0"; +- rx-pool = <1024 12>; +- tx-pool = <1024 12>; +- rx-queue-depth = <128 128 0 0>; +- rx-buffer-size = <1518 4096 0 0>; +- rx-queue = <528>; +- tx-completion-queue = <530>; +- efuse-mac = <1>; +- netcp-gbe = <&gbe0>; +- +- }; +- interface-1 { +- rx-channel = "netrx1"; +- rx-pool = <1024 12>; +- tx-pool = <1024 12>; +- rx-queue-depth = <128 128 0 0>; +- rx-buffer-size = <1518 4096 0 0>; +- rx-queue = <529>; +- tx-completion-queue = <531>; +- efuse-mac = <0>; +- local-mac-address = [02 18 31 7e 3e 7f]; +- netcp-gbe = <&gbe1>; +- }; +- }; +-}; +- +-sa_subsys: subsys@26080000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0 0x26080000 0x40000>; +- +- sa_config: subsys@0 { +- compatible = "syscon"; +- reg = <0x0 0x100>; +- }; +- +- rng@24000 { +- compatible = "ti,keystone-rng"; +- reg = <0x24000 0x1000>; +- ti,syscon-sa-cfg = <&sa_config>; +- clocks = <&clksa>; +- clock-names = "fck"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/keystone-k2l.dtsi b/scripts/dtc/include-prefixes/arm/keystone-k2l.dtsi +deleted file mode 100644 +index dff5fea72b2f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/keystone-k2l.dtsi ++++ /dev/null +@@ -1,415 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Keystone 2 Lamarr SoC specific device tree +- * +- * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ +- */ +- +-#include +- +-/ { +- compatible = "ti,k2l", "ti,keystone"; +- model = "Texas Instruments Keystone 2 Lamarr SoC"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- interrupt-parent = <&gic>; +- +- cpu@0 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- reg = <0>; +- }; +- +- cpu@1 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- reg = <1>; +- }; +- }; +- +- aliases { +- rproc0 = &dsp0; +- rproc1 = &dsp1; +- rproc2 = &dsp2; +- rproc3 = &dsp3; +- }; +-}; +- +-&soc0 { +- /include/ "keystone-k2l-clocks.dtsi" +- +- uart2: serial@2348400 { +- compatible = "ti,da830-uart", "ns16550a"; +- current-speed = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- reg = <0x02348400 0x100>; +- clocks = <&clkuart2>; +- interrupts = ; +- }; +- +- uart3: serial@2348800 { +- compatible = "ti,da830-uart", "ns16550a"; +- current-speed = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- reg = <0x02348800 0x100>; +- clocks = <&clkuart3>; +- interrupts = ; +- }; +- +- gpio1: gpio@2348000 { +- compatible = "ti,keystone-gpio"; +- reg = <0x02348000 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- /* HW Interrupts mapped to GPIO pins */ +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&clkgpio>; +- clock-names = "gpio"; +- ti,ngpio = <32>; +- ti,davinci-gpio-unbanked = <32>; +- }; +- +- k2l_pmx: pinmux@2620690 { +- compatible = "pinctrl-single"; +- reg = <0x02620690 0xc>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <2>; +- pinctrl-single,bit-per-mux; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0x1>; +- status = "disabled"; +- +- uart3_emifa_pins: pinmux_uart3_emifa_pins { +- pinctrl-single,bits = < +- /* UART3_EMIFA_SEL */ +- 0x0 0x0 0xc0 +- >; +- }; +- +- uart2_emifa_pins: pinmux_uart2_emifa_pins { +- pinctrl-single,bits = < +- /* UART2_EMIFA_SEL */ +- 0x0 0x0 0x30 +- >; +- }; +- +- uart01_spi2_pins: pinmux_uart01_spi2_pins { +- pinctrl-single,bits = < +- /* UART01_SPI2_SEL */ +- 0x0 0x0 0x4 +- >; +- }; +- +- dfesync_rp1_pins: pinmux_dfesync_rp1_pins{ +- pinctrl-single,bits = < +- /* DFESYNC_RP1_SEL */ +- 0x0 0x0 0x2 +- >; +- }; +- +- avsif_pins: pinmux_avsif_pins { +- pinctrl-single,bits = < +- /* AVSIF_SEL */ +- 0x0 0x0 0x1 +- >; +- }; +- +- gpio_emu_pins: pinmux_gpio_emu_pins { +- pinctrl-single,bits = < +- /* +- * GPIO_EMU_SEL[31]: 0-GPIO31, 1-EMU33 +- * GPIO_EMU_SEL[30]: 0-GPIO30, 1-EMU32 +- * GPIO_EMU_SEL[29]: 0-GPIO29, 1-EMU31 +- * GPIO_EMU_SEL[28]: 0-GPIO28, 1-EMU30 +- * GPIO_EMU_SEL[27]: 0-GPIO27, 1-EMU29 +- * GPIO_EMU_SEL[26]: 0-GPIO26, 1-EMU28 +- * GPIO_EMU_SEL[25]: 0-GPIO25, 1-EMU27 +- * GPIO_EMU_SEL[24]: 0-GPIO24, 1-EMU26 +- * GPIO_EMU_SEL[23]: 0-GPIO23, 1-EMU25 +- * GPIO_EMU_SEL[22]: 0-GPIO22, 1-EMU24 +- * GPIO_EMU_SEL[21]: 0-GPIO21, 1-EMU23 +- * GPIO_EMU_SEL[20]: 0-GPIO20, 1-EMU22 +- * GPIO_EMU_SEL[19]: 0-GPIO19, 1-EMU21 +- * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20 +- * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19 +- */ +- 0x4 0x0000 0xFFFE0000 +- >; +- }; +- +- gpio_timio_pins: pinmux_gpio_timio_pins { +- pinctrl-single,bits = < +- /* +- * GPIO_TIMIO_SEL[15]: 0-GPIO15, 1-TIMO7 +- * GPIO_TIMIO_SEL[14]: 0-GPIO14, 1-TIMO6 +- * GPIO_TIMIO_SEL[13]: 0-GPIO13, 1-TIMO5 +- * GPIO_TIMIO_SEL[12]: 0-GPIO12, 1-TIMO4 +- * GPIO_TIMIO_SEL[11]: 0-GPIO11, 1-TIMO3 +- * GPIO_TIMIO_SEL[10]: 0-GPIO10, 1-TIMO2 +- * GPIO_TIMIO_SEL[9]: 0-GPIO9, 1-TIMI7 +- * GPIO_TIMIO_SEL[8]: 0-GPIO8, 1-TIMI6 +- * GPIO_TIMIO_SEL[7]: 0-GPIO7, 1-TIMI5 +- * GPIO_TIMIO_SEL[6]: 0-GPIO6, 1-TIMI4 +- * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3 +- * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2 +- */ +- 0x4 0x0 0xFFF0 +- >; +- }; +- +- gpio_spi2cs_pins: pinmux_gpio_spi2cs_pins { +- pinctrl-single,bits = < +- /* +- * GPIO_SPI2CS_SEL[3]: 0-GPIO3, 1-SPI2CS4 +- * GPIO_SPI2CS_SEL[2]: 0-GPIO2, 1-SPI2CS3 +- * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2 +- * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1 +- */ +- 0x4 0x0 0xF +- >; +- }; +- +- gpio_dfeio_pins: pinmux_gpio_dfeio_pins { +- pinctrl-single,bits = < +- /* +- * GPIO_DFEIO_SEL[31]: 0-DFEIO17, 1-GPIO63 +- * GPIO_DFEIO_SEL[30]: 0-DFEIO16, 1-GPIO62 +- * GPIO_DFEIO_SEL[29]: 0-DFEIO15, 1-GPIO61 +- * GPIO_DFEIO_SEL[28]: 0-DFEIO14, 1-GPIO60 +- * GPIO_DFEIO_SEL[27]: 0-DFEIO13, 1-GPIO59 +- * GPIO_DFEIO_SEL[26]: 0-DFEIO12, 1-GPIO58 +- * GPIO_DFEIO_SEL[25]: 0-DFEIO11, 1-GPIO57 +- * GPIO_DFEIO_SEL[24]: 0-DFEIO10, 1-GPIO56 +- * GPIO_DFEIO_SEL[23]: 0-DFEIO9, 1-GPIO55 +- * GPIO_DFEIO_SEL[22]: 0-DFEIO8, 1-GPIO54 +- * GPIO_DFEIO_SEL[21]: 0-DFEIO7, 1-GPIO53 +- * GPIO_DFEIO_SEL[20]: 0-DFEIO6, 1-GPIO52 +- * GPIO_DFEIO_SEL[19]: 0-DFEIO5, 1-GPIO51 +- * GPIO_DFEIO_SEL[18]: 0-DFEIO4, 1-GPIO50 +- * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49 +- * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48 +- */ +- 0x8 0x0 0xFFFF0000 +- >; +- }; +- +- gpio_emifa_pins: pinmux_gpio_emifa_pins { +- pinctrl-single,bits = < +- /* +- * GPIO_EMIFA_SEL[15]: 0-EMIFA17, 1-GPIO47 +- * GPIO_EMIFA_SEL[14]: 0-EMIFA16, 1-GPIO46 +- * GPIO_EMIFA_SEL[13]: 0-EMIFA15, 1-GPIO45 +- * GPIO_EMIFA_SEL[12]: 0-EMIFA14, 1-GPIO44 +- * GPIO_EMIFA_SEL[11]: 0-EMIFA13, 1-GPIO43 +- * GPIO_EMIFA_SEL[10]: 0-EMIFA10, 1-GPIO42 +- * GPIO_EMIFA_SEL[9]: 0-EMIFA9, 1-GPIO41 +- * GPIO_EMIFA_SEL[8]: 0-EMIFA8, 1-GPIO40 +- * GPIO_EMIFA_SEL[7]: 0-EMIFA7, 1-GPIO39 +- * GPIO_EMIFA_SEL[6]: 0-EMIFA6, 1-GPIO38 +- * GPIO_EMIFA_SEL[5]: 0-EMIFA5, 1-GPIO37 +- * GPIO_EMIFA_SEL[4]: 0-EMIFA4, 1-GPIO36 +- * GPIO_EMIFA_SEL[3]: 0-EMIFA3, 1-GPIO35 +- * GPIO_EMIFA_SEL[2]: 0-EMIFA2, 1-GPIO34 +- * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33 +- * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32 +- */ +- 0x8 0x0 0xFFFF +- >; +- }; +- }; +- +- msm_ram: sram@c000000 { +- compatible = "mmio-sram"; +- reg = <0x0c000000 0x200000>; +- ranges = <0x0 0x0c000000 0x200000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- bm-sram@1f8000 { +- reg = <0x001f8000 0x8000>; +- }; +- }; +- +- psc: power-sleep-controller@2350000 { +- pscrst: reset-controller { +- compatible = "ti,k2l-pscrst", "ti,syscon-reset"; +- #reset-cells = <1>; +- +- ti,reset-bits = < +- 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ +- 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */ +- 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */ +- 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */ +- >; +- }; +- }; +- +- osr: sram@70000000 { +- compatible = "mmio-sram"; +- reg = <0x70000000 0x10000>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&clkosr>; +- }; +- +- devctrl: device-state-control@2620000 { +- dspgpio0: keystone_dsp_gpio@240 { +- compatible = "ti,keystone-dsp-gpio"; +- reg = <0x240 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio,syscon-dev = <&devctrl 0x240>; +- }; +- +- dspgpio1: keystone_dsp_gpio@244 { +- compatible = "ti,keystone-dsp-gpio"; +- reg = <0x244 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio,syscon-dev = <&devctrl 0x244>; +- }; +- +- dspgpio2: keystone_dsp_gpio@248 { +- compatible = "ti,keystone-dsp-gpio"; +- reg = <0x248 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio,syscon-dev = <&devctrl 0x248>; +- }; +- +- dspgpio3: keystone_dsp_gpio@24c { +- compatible = "ti,keystone-dsp-gpio"; +- reg = <0x24c 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio,syscon-dev = <&devctrl 0x24c>; +- }; +- }; +- +- dsp0: dsp@10800000 { +- compatible = "ti,k2l-dsp"; +- reg = <0x10800000 0x00100000>, +- <0x10e00000 0x00008000>, +- <0x10f00000 0x00008000>; +- reg-names = "l2sram", "l1pram", "l1dram"; +- clocks = <&clkgem0>; +- ti,syscon-dev = <&devctrl 0x844>; +- resets = <&pscrst 0>; +- interrupt-parent = <&kirq0>; +- interrupts = <0 8>; +- interrupt-names = "vring", "exception"; +- kick-gpios = <&dspgpio0 27 0>; +- status = "disabled"; +- }; +- +- dsp1: dsp@11800000 { +- compatible = "ti,k2l-dsp"; +- reg = <0x11800000 0x00100000>, +- <0x11e00000 0x00008000>, +- <0x11f00000 0x00008000>; +- reg-names = "l2sram", "l1pram", "l1dram"; +- clocks = <&clkgem1>; +- ti,syscon-dev = <&devctrl 0x848>; +- resets = <&pscrst 1>; +- interrupt-parent = <&kirq0>; +- interrupts = <1 9>; +- interrupt-names = "vring", "exception"; +- kick-gpios = <&dspgpio1 27 0>; +- status = "disabled"; +- }; +- +- dsp2: dsp@12800000 { +- compatible = "ti,k2l-dsp"; +- reg = <0x12800000 0x00100000>, +- <0x12e00000 0x00008000>, +- <0x12f00000 0x00008000>; +- reg-names = "l2sram", "l1pram", "l1dram"; +- clocks = <&clkgem2>; +- ti,syscon-dev = <&devctrl 0x84c>; +- resets = <&pscrst 2>; +- interrupt-parent = <&kirq0>; +- interrupts = <2 10>; +- interrupt-names = "vring", "exception"; +- kick-gpios = <&dspgpio2 27 0>; +- status = "disabled"; +- }; +- +- dsp3: dsp@13800000 { +- compatible = "ti,k2l-dsp"; +- reg = <0x13800000 0x00100000>, +- <0x13e00000 0x00008000>, +- <0x13f00000 0x00008000>; +- reg-names = "l2sram", "l1pram", "l1dram"; +- clocks = <&clkgem3>; +- ti,syscon-dev = <&devctrl 0x850>; +- resets = <&pscrst 3>; +- interrupt-parent = <&kirq0>; +- interrupts = <3 11>; +- interrupt-names = "vring", "exception"; +- kick-gpios = <&dspgpio3 27 0>; +- status = "disabled"; +- }; +- +- mdio: mdio@26200f00 { +- compatible = "ti,keystone_mdio", "ti,davinci_mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x26200f00 0x100>; +- status = "disabled"; +- clocks = <&clkcpgmac>; +- clock-names = "fck"; +- bus_freq = <2500000>; +- }; +- /include/ "keystone-k2l-netcp.dtsi" +-}; +- +-&spi0 { +- ti,davinci-spi-num-cs = <5>; +-}; +- +-&spi1 { +- ti,davinci-spi-num-cs = <3>; +-}; +- +-&spi2 { +- ti,davinci-spi-num-cs = <5>; +- /* Pin muxed. Enabled and configured by Bootloader */ +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/keystone.dtsi b/scripts/dtc/include-prefixes/arm/keystone.dtsi +deleted file mode 100644 +index fc9fdc857ae8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/keystone.dtsi ++++ /dev/null +@@ -1,354 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ +- */ +- +-#include +-#include +- +-/ { +- compatible = "ti,keystone"; +- model = "Texas Instruments Keystone 2 SoC"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&gic>; +- +- aliases { +- serial0 = &uart0; +- spi0 = &spi0; +- spi1 = &spi1; +- spi2 = &spi2; +- }; +- +- chosen { }; +- +- memory: memory@80000000 { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0x00000000 0x40000000>; +- }; +- +- gic: interrupt-controller@2561000 { +- compatible = "arm,gic-400", "arm,cortex-a15-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x0 0x02561000 0x0 0x1000>, +- <0x0 0x02562000 0x0 0x2000>, +- <0x0 0x02564000 0x0 0x2000>, +- <0x0 0x02566000 0x0 0x2000>; +- interrupts = ; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = +- , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,cortex-a15-pmu"; +- interrupts = , +- , +- , +- ; +- }; +- +- psci { +- compatible = "arm,psci"; +- method = "smc"; +- cpu_suspend = <0x84000001>; +- cpu_off = <0x84000002>; +- cpu_on = <0x84000003>; +- }; +- +- soc0: soc@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ti,keystone","simple-bus"; +- interrupt-parent = <&gic>; +- ranges = <0x0 0x0 0x0 0xc0000000>; +- dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; +- +- pllctrl: pll-controller@2310000 { +- compatible = "ti,keystone-pllctrl", "syscon"; +- reg = <0x02310000 0x200>; +- }; +- +- psc: power-sleep-controller@2350000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x02350000 0x1000>; +- }; +- +- devctrl: device-state-control@2620000 { +- compatible = "ti,keystone-devctrl", "syscon", "simple-mfd"; +- reg = <0x02620000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x02620000 0x1000>; +- +- kirq0: keystone_irq@2a0 { +- compatible = "ti,keystone-irq"; +- reg = <0x2a0 0x4>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- ti,syscon-dev = <&devctrl 0x2a0>; +- }; +- +- rstctrl: reset-controller@328 { +- compatible = "ti,keystone-reset"; +- reg = <0x328 0x10>; +- ti,syscon-pll = <&pllctrl 0xe4>; +- ti,syscon-dev = <&devctrl 0x328>; +- ti,wdt-list = <0>; +- }; +- }; +- +- /include/ "keystone-clocks.dtsi" +- +- uart0: serial@2530c00 { +- compatible = "ti,da830-uart", "ns16550a"; +- current-speed = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- reg = <0x02530c00 0x100>; +- clocks = <&clkuart0>; +- interrupts = ; +- }; +- +- uart1: serial@2531000 { +- compatible = "ti,da830-uart", "ns16550a"; +- current-speed = <115200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- reg = <0x02531000 0x100>; +- clocks = <&clkuart1>; +- interrupts = ; +- }; +- +- i2c0: i2c@2530000 { +- compatible = "ti,davinci-i2c"; +- reg = <0x02530000 0x400>; +- clock-frequency = <100000>; +- clocks = <&clki2c>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c1: i2c@2530400 { +- compatible = "ti,davinci-i2c"; +- reg = <0x02530400 0x400>; +- clock-frequency = <100000>; +- clocks = <&clki2c>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c2: i2c@2530800 { +- compatible = "ti,davinci-i2c"; +- reg = <0x02530800 0x400>; +- clock-frequency = <100000>; +- clocks = <&clki2c>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spi0: spi@21000400 { +- compatible = "ti,keystone-spi", "ti,dm6441-spi"; +- reg = <0x21000400 0x200>; +- num-cs = <4>; +- ti,davinci-spi-intr-line = <0>; +- interrupts = ; +- clocks = <&clkspi>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spi1: spi@21000600 { +- compatible = "ti,keystone-spi", "ti,dm6441-spi"; +- reg = <0x21000600 0x200>; +- num-cs = <4>; +- ti,davinci-spi-intr-line = <0>; +- interrupts = ; +- clocks = <&clkspi>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spi2: spi@21000800 { +- compatible = "ti,keystone-spi", "ti,dm6441-spi"; +- reg = <0x21000800 0x200>; +- num-cs = <4>; +- ti,davinci-spi-intr-line = <0>; +- interrupts = ; +- clocks = <&clkspi>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- usb_phy: usb_phy@2620738 { +- compatible = "ti,keystone-usbphy"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x2620738 24>; +- status = "disabled"; +- }; +- +- keystone_usb0: usb@2680000 { +- compatible = "ti,keystone-dwc3"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x2680000 0x10000>; +- clocks = <&clkusb>; +- clock-names = "usb"; +- interrupts = ; +- ranges; +- dma-coherent; +- dma-ranges; +- status = "disabled"; +- +- usb0: usb@2690000 { +- compatible = "snps,dwc3"; +- reg = <0x2690000 0x70000>; +- interrupts = ; +- usb-phy = <&usb_phy>, <&usb_phy>; +- }; +- }; +- +- wdt: wdt@22f0080 { +- compatible = "ti,keystone-wdt","ti,davinci-wdt"; +- reg = <0x022f0080 0x80>; +- clocks = <&clkwdtimer0>; +- }; +- +- clock_event: timer@22f0000 { +- compatible = "ti,keystone-timer"; +- reg = <0x022f0000 0x80>; +- interrupts = ; +- clocks = <&clktimer15>; +- }; +- +- gpio0: gpio@260bf00 { +- compatible = "ti,keystone-gpio"; +- reg = <0x0260bf00 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- /* HW Interrupts mapped to GPIO pins */ +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&clkgpio>; +- clock-names = "gpio"; +- ti,ngpio = <32>; +- ti,davinci-gpio-unbanked = <32>; +- }; +- +- aemif: aemif@21000A00 { +- compatible = "ti,keystone-aemif", "ti,davinci-aemif"; +- #address-cells = <2>; +- #size-cells = <1>; +- clocks = <&clkaemif>; +- clock-names = "aemif"; +- clock-ranges; +- +- reg = <0x21000A00 0x00000100>; +- ranges = <0 0 0x30000000 0x10000000 +- 1 0 0x21000A00 0x00000100>; +- }; +- +- pcie0: pcie@21800000 { +- compatible = "ti,keystone-pcie", "snps,dw-pcie"; +- clocks = <&clkpcie>; +- clock-names = "pcie"; +- #address-cells = <3>; +- #size-cells = <2>; +- reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; +- ranges = <0x82000000 0 0x50000000 0x50000000 +- 0 0x10000000>; +- +- status = "disabled"; +- device_type = "pci"; +- num-lanes = <2>; +- bus-range = <0x00 0xff>; +- +- /* error interrupt */ +- interrupts = ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */ +- <0 0 0 2 &pcie_intc0 1>, /* INT B */ +- <0 0 0 3 &pcie_intc0 2>, /* INT C */ +- <0 0 0 4 &pcie_intc0 3>; /* INT D */ +- +- pcie_msi_intc0: msi-interrupt-controller { +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- }; +- +- pcie_intc0: legacy-interrupt-controller { +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- }; +- }; +- +- emif: emif@21010000 { +- compatible = "ti,emif-keystone"; +- reg = <0x21010000 0x200>; +- interrupts = ; +- interrupt-parent = <&gic>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-6192.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-6192.dtsi +deleted file mode 100644 +index 396bcba08adb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-6192.dtsi ++++ /dev/null +@@ -1,88 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- mbus@f1000000 { +- pciec: pcie@82000000 { +- compatible = "marvell,kirkwood-pcie"; +- status = "disabled"; +- device_type = "pci"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- bus-range = <0x00 0xff>; +- +- ranges = +- <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 +- 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ +- 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; +- +- pcie0: pcie@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 +- 0x81000000 0 0 0x81000000 0x1 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &intc 9>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <0>; +- clocks = <&gate_clk 2>; +- status = "disabled"; +- }; +- }; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- compatible = "marvell,88f6192-pinctrl"; +- +- pmx_sata0: pmx-sata0 { +- marvell,pins = "mpp5", "mpp21", "mpp23"; +- marvell,function = "sata0"; +- }; +- pmx_sata1: pmx-sata1 { +- marvell,pins = "mpp4", "mpp20", "mpp22"; +- marvell,function = "sata1"; +- }; +- pmx_sdio: pmx-sdio { +- marvell,pins = "mpp12", "mpp13", "mpp14", +- "mpp15", "mpp16", "mpp17"; +- marvell,function = "sdio"; +- }; +- }; +- +- rtc: rtc@10300 { +- compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; +- reg = <0x10300 0x20>; +- interrupts = <53>; +- clocks = <&gate_clk 7>; +- }; +- +- sata: sata@80000 { +- compatible = "marvell,orion-sata"; +- reg = <0x80000 0x5000>; +- interrupts = <21>; +- clocks = <&gate_clk 14>, <&gate_clk 15>; +- clock-names = "0", "1"; +- phys = <&sata_phy0>, <&sata_phy1>; +- phy-names = "port0", "port1"; +- status = "disabled"; +- }; +- +- sdio: mvsdio@90000 { +- compatible = "marvell,orion-sdio"; +- reg = <0x90000 0x200>; +- interrupts = <28>; +- clocks = <&gate_clk 4>; +- bus-width = <4>; +- cap-sdio-irq; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-6281.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-6281.dtsi +deleted file mode 100644 +index faa05849a40d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-6281.dtsi ++++ /dev/null +@@ -1,90 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- mbus@f1000000 { +- pciec: pcie@82000000 { +- compatible = "marvell,kirkwood-pcie"; +- status = "disabled"; +- device_type = "pci"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- bus-range = <0x00 0xff>; +- +- ranges = +- <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 +- 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ +- 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; +- +- pcie0: pcie@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 +- 0x81000000 0 0 0x81000000 0x1 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &intc 9>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <0>; +- clocks = <&gate_clk 2>; +- status = "disabled"; +- }; +- }; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- compatible = "marvell,88f6281-pinctrl"; +- +- pmx_sata0: pmx-sata0 { +- marvell,pins = "mpp5", "mpp21", "mpp23"; +- marvell,function = "sata0"; +- }; +- pmx_sata1: pmx-sata1 { +- marvell,pins = "mpp4", "mpp20", "mpp22"; +- marvell,function = "sata1"; +- }; +- pmx_sdio: pmx-sdio { +- marvell,pins = "mpp12", "mpp13", "mpp14", +- "mpp15", "mpp16", "mpp17"; +- marvell,function = "sdio"; +- }; +- }; +- +- rtc: rtc@10300 { +- compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; +- reg = <0x10300 0x20>; +- interrupts = <53>; +- clocks = <&gate_clk 7>; +- }; +- +- sata: sata@80000 { +- compatible = "marvell,orion-sata"; +- reg = <0x80000 0x5000>; +- interrupts = <21>; +- clocks = <&gate_clk 14>, <&gate_clk 15>; +- clock-names = "0", "1"; +- phys = <&sata_phy0>, <&sata_phy1>; +- phy-names = "port0", "port1"; +- status = "disabled"; +- }; +- +- sdio: mvsdio@90000 { +- compatible = "marvell,orion-sdio"; +- reg = <0x90000 0x200>; +- interrupts = <28>; +- clocks = <&gate_clk 4>; +- pinctrl-0 = <&pmx_sdio>; +- pinctrl-names = "default"; +- bus-width = <4>; +- cap-sdio-irq; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-6282.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-6282.dtsi +deleted file mode 100644 +index e84c54b77dea..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-6282.dtsi ++++ /dev/null +@@ -1,141 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- mbus@f1000000 { +- pciec: pcie@82000000 { +- compatible = "marvell,kirkwood-pcie"; +- status = "disabled"; +- device_type = "pci"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- bus-range = <0x00 0xff>; +- +- ranges = +- <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 +- 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 +- 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 +- 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ +- 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ +- 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ +- 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; +- +- pcie0: pcie@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 +- 0x81000000 0 0 0x81000000 0x1 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &intc 9>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <0>; +- clocks = <&gate_clk 2>; +- status = "disabled"; +- }; +- +- pcie1: pcie@2,0 { +- device_type = "pci"; +- assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; +- reg = <0x1000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 +- 0x81000000 0 0 0x81000000 0x2 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &intc 10>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <0>; +- clocks = <&gate_clk 18>; +- status = "disabled"; +- }; +- }; +- }; +- ocp@f1000000 { +- +- pinctrl: pin-controller@10000 { +- compatible = "marvell,88f6282-pinctrl"; +- +- pmx_sata0: pmx-sata0 { +- marvell,pins = "mpp5", "mpp21", "mpp23"; +- marvell,function = "sata0"; +- }; +- pmx_sata1: pmx-sata1 { +- marvell,pins = "mpp4", "mpp20", "mpp22"; +- marvell,function = "sata1"; +- }; +- +- /* +- * Default I2C1 pinctrl setting on mpp36/mpp37, +- * overwrite marvell,pins on board level if required. +- */ +- pmx_twsi1: pmx-twsi1 { +- marvell,pins = "mpp36", "mpp37"; +- marvell,function = "twsi1"; +- }; +- +- pmx_sdio: pmx-sdio { +- marvell,pins = "mpp12", "mpp13", "mpp14", +- "mpp15", "mpp16", "mpp17"; +- marvell,function = "sdio"; +- }; +- }; +- +- thermal: thermal@10078 { +- compatible = "marvell,kirkwood-thermal"; +- reg = <0x10078 0x4>; +- status = "okay"; +- }; +- +- rtc: rtc@10300 { +- compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; +- reg = <0x10300 0x20>; +- interrupts = <53>; +- clocks = <&gate_clk 7>; +- }; +- +- i2c1: i2c@11100 { +- compatible = "marvell,mv64xxx-i2c"; +- reg = <0x11100 0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <32>; +- clock-frequency = <100000>; +- clocks = <&gate_clk 7>; +- pinctrl-0 = <&pmx_twsi1>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- sata: sata@80000 { +- compatible = "marvell,orion-sata"; +- reg = <0x80000 0x5000>; +- interrupts = <21>; +- clocks = <&gate_clk 14>, <&gate_clk 15>; +- clock-names = "0", "1"; +- phys = <&sata_phy0>, <&sata_phy1>; +- phy-names = "port0", "port1"; +- status = "disabled"; +- }; +- +- sdio: mvsdio@90000 { +- compatible = "marvell,orion-sdio"; +- reg = <0x90000 0x200>; +- interrupts = <28>; +- clocks = <&gate_clk 4>; +- pinctrl-0 = <&pmx_sdio>; +- pinctrl-names = "default"; +- bus-width = <4>; +- cap-sdio-irq; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-98dx4122.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-98dx4122.dtsi +deleted file mode 100644 +index 299c147298c3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-98dx4122.dtsi ++++ /dev/null +@@ -1,53 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- mbus@f1000000 { +- pciec: pcie@82000000 { +- compatible = "marvell,kirkwood-pcie"; +- status = "disabled"; +- device_type = "pci"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- bus-range = <0x00 0xff>; +- +- ranges = +- <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 +- 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ +- 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; +- +- pcie0: pcie@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 +- 0x81000000 0 0 0x81000000 0x1 0 1 0>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &intc 9>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <0>; +- clocks = <&gate_clk 2>; +- status = "disabled"; +- }; +- }; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- compatible = "marvell,98dx4122-pinctrl"; +- +- }; +- }; +-}; +- +-&sata_phy0 { +- status = "disabled"; +-}; +- +-&sata_phy1 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-b3.dts b/scripts/dtc/include-prefixes/arm/kirkwood-b3.dts +deleted file mode 100644 +index a7636fe28501..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-b3.dts ++++ /dev/null +@@ -1,195 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Device Tree file for Excito Bubba B3 +- * +- * Copyright (C) 2013, Andrew Lunn +- * +- * +- * Note: This requires a new'ish version of u-boot, which disables the +- * L2 cache. If your B3 silently fails to boot, u-boot is probably too +- * old. Either upgrade, or consider the following email: +- * +- * https://lists.debian.org/debian-arm/2012/08/msg00128.html +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- model = "Excito B3"; +- compatible = "excito,b3", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- memory { /* 512 MB */ +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_button_power: pmx-button-power { +- marvell,pins = "mpp39"; +- marvell,function = "gpio"; +- }; +- pmx_led_green: pmx-led-green { +- marvell,pins = "mpp38"; +- marvell,function = "gpio"; +- }; +- pmx_led_red: pmx-led-red { +- marvell,pins = "mpp41"; +- marvell,function = "gpio"; +- }; +- pmx_led_blue: pmx-led-blue { +- marvell,pins = "mpp42"; +- marvell,function = "gpio"; +- }; +- pmx_beeper: pmx-beeper { +- marvell,pins = "mpp40"; +- marvell,function = "gpio"; +- }; +- }; +- +- spi@10600 { +- status = "okay"; +- +- m25p16@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p16", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; +- mode = <0>; +- +- partition@0 { +- reg = <0x0 0xc0000>; +- label = "u-boot"; +- }; +- +- partition@c0000 { +- reg = <0xc0000 0x20000>; +- label = "u-boot env"; +- }; +- +- partition@e0000 { +- reg = <0xe0000 0x120000>; +- label = "data"; +- }; +- }; +- }; +- +- i2c@11000 { +- status = "okay"; +- /* +- * There is something on the bus at address 0x64. +- * Not yet identified what it is, maybe the eeprom +- * for the Atheros WiFi chip? +- */ +- }; +- +- +- serial@12000 { +- /* Internal on test pins, 3.3v TTL +- * UART0_RX = Testpoint 65 +- * UART0_TX = Testpoint 66 +- * See the Excito Wiki for more details. +- */ +- status = "okay"; +- }; +- +- sata@80000 { +- /* One internal, the second as eSATA */ +- status = "okay"; +- nr-ports = <2>; +- }; +- }; +- +- gpio-leds { +- /* +- * There is one LED "port" on the front and the colours +- * mix together giving some interesting combinations. +- */ +- compatible = "gpio-leds"; +- pinctrl-0 = < &pmx_led_green &pmx_led_red +- &pmx_led_blue >; +- pinctrl-names = "default"; +- +- programming_led { +- label = "bubba3:green:programming"; +- gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- error_led { +- label = "bubba3:red:error"; +- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- }; +- +- active_led { +- label = "bubba3:blue:active"; +- gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&pmx_button_power>; +- pinctrl-names = "default"; +- +- power-button { +- /* On the back */ +- label = "Power Button"; +- linux,code = ; +- gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- beeper: beeper { +- /* 4KHz Piezoelectric buzzer */ +- compatible = "gpio-beeper"; +- pinctrl-0 = <&pmx_beeper>; +- pinctrl-names = "default"; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@8 { +- device_type = "ethernet-phy"; +- reg = <8>; +- }; +- +- ethphy1: ethernet-phy@24 { +- device_type = "ethernet-phy"; +- reg = <24>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- +-ð1 { +- status = "okay"; +- ethernet1-port@0 { +- phy-handle = <ðphy1>; +- }; +-}; +- +-/* Wifi model has Atheros chipset on pcie port */ +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-blackarmor-nas220.dts b/scripts/dtc/include-prefixes/arm/kirkwood-blackarmor-nas220.dts +deleted file mode 100644 +index 07fbfca444d5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-blackarmor-nas220.dts ++++ /dev/null +@@ -1,172 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Device Tree file for Seagate Blackarmor NAS220 +- * +- * Copyright (C) 2014 Evgeni Dobrev +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "kirkwood.dtsi" +-#include "kirkwood-6192.dtsi" +- +-/ { +- model = "Seagate Blackarmor NAS220"; +- compatible = "seagate,blackarmor-nas220","marvell,kirkwood-88f6192", +- "marvell,kirkwood"; +- +- memory { /* 128 MB */ +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio_poweroff { +- compatible = "gpio-poweroff"; +- gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- reset { +- label = "Reset"; +- linux,code = ; +- gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; +- }; +- +- button { +- label = "Power"; +- linux,code = ; +- gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- blue-power { +- label = "nas220:blue:power"; +- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>; +- pinctrl-names = "default"; +- +- sata0_power: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "SATA0 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 24 GPIO_ACTIVE_LOW>; +- }; +- +- sata1_power: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "SATA1 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 28 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-/* +- * Serial port routed to connector CN5 +- * +- * pin 1 - TX (CPU's TX) +- * pin 4 - RX (CPU's RX) +- * pin 6 - GND +- */ +-&uart0 { +- status = "okay"; +-}; +- +-&pinctrl { +- pinctrl-0 = <&pmx_button_reset &pmx_button_power>; +- pinctrl-names = "default"; +- +- pmx_act_sata0: pmx-act-sata0 { +- marvell,pins = "mpp15"; +- marvell,function = "sata0"; +- }; +- +- pmx_act_sata1: pmx-act-sata1 { +- marvell,pins = "mpp16"; +- marvell,function = "sata1"; +- }; +- +- pmx_power_sata0: pmx-power-sata0 { +- marvell,pins = "mpp24"; +- marvell,function = "gpio"; +- }; +- +- pmx_power_sata1: pmx-power-sata1 { +- marvell,pins = "mpp28"; +- marvell,function = "gpio"; +- }; +- +- pmx_button_reset: pmx-button-reset { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- +- pmx_button_power: pmx-button-power { +- marvell,pins = "mpp26"; +- marvell,function = "gpio"; +- }; +-}; +- +-&sata { +- status = "okay"; +- nr-ports = <2>; +-}; +- +-&i2c0 { +- status = "okay"; +- +- adt7476: thermal@2e { +- compatible = "adi,adt7476"; +- reg = <0x2e>; +- }; +-}; +- +-&nand { +- status = "okay"; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@8 { +- reg = <8>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-cloudbox.dts b/scripts/dtc/include-prefixes/arm/kirkwood-cloudbox.dts +deleted file mode 100644 +index 448b0cd23b5f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-cloudbox.dts ++++ /dev/null +@@ -1,103 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- model = "LaCie CloudBox"; +- compatible = "lacie,cloudbox", "marvell,kirkwood-88f6702", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_cloudbox_sata0: pmx-cloudbox-sata0 { +- marvell,pins = "mpp15"; +- marvell,function = "sata0"; +- }; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- sata@80000 { +- pinctrl-0 = <&pmx_cloudbox_sata0>; +- pinctrl-names = "default"; +- status = "okay"; +- nr-ports = <1>; +- }; +- +- spi@10600 { +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- mode = <0>; +- +- partition@0 { +- reg = <0x0 0x80000>; +- label = "u-boot"; +- }; +- }; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- power { +- label = "Power push button"; +- linux,code = ; +- gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- red-fail { +- label = "cloudbox:red:fail"; +- gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; +- }; +- blue-sata { +- label = "cloudbox:blue:sata"; +- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio_poweroff { +- compatible = "gpio-poweroff"; +- gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-d2net.dts b/scripts/dtc/include-prefixes/arm/kirkwood-d2net.dts +deleted file mode 100644 +index bd3b266dd766..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-d2net.dts ++++ /dev/null +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree file for d2 Network v2 +- * +- * Copyright (C) 2014 Simon Guinot +- * +-*/ +- +-/dts-v1/; +- +-#include +-#include "kirkwood-netxbig.dtsi" +- +-/ { +- model = "LaCie d2 Network v2"; +- compatible = "lacie,d2net_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- ns2-leds { +- compatible = "lacie,ns2-leds"; +- +- blue-sata { +- label = "d2net_v2:blue:sata"; +- slow-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; +- cmd-gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; +- modes-map = ; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- red-fail { +- label = "d2net_v2:red:fail"; +- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-db-88f6281.dts b/scripts/dtc/include-prefixes/arm/kirkwood-db-88f6281.dts +deleted file mode 100644 +index 2adb17c955aa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-db-88f6281.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Marvell DB-88F6281-BP Development Board Setup +- * +- * Saeed Bishara +- * Thomas Petazzoni +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood-db.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- model = "Marvell DB-88F6281-BP Development Board"; +- compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-db-88f6282.dts b/scripts/dtc/include-prefixes/arm/kirkwood-db-88f6282.dts +deleted file mode 100644 +index f84a48539917..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-db-88f6282.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Marvell DB-88F6282-BP Development Board Setup +- * +- * Saeed Bishara +- * Thomas Petazzoni +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood-db.dtsi" +-#include "kirkwood-6282.dtsi" +- +-/ { +- model = "Marvell DB-88F6282-BP Development Board"; +- compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood"; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-db.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-db.dtsi +deleted file mode 100644 +index 6fe2e31534af..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-db.dtsi ++++ /dev/null +@@ -1,89 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Marvell DB-{88F6281,88F6282}-BP Development Board Setup +- * +- * Saeed Bishara +- * Thomas Petazzoni +- * +- * This file contains the definitions that are common between the 6281 +- * and 6282 variants of the Marvell Kirkwood Development Board. +- */ +- +-#include "kirkwood.dtsi" +- +-/ { +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; /* 512 MB */ +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pin-controller@10000 { +- pmx_sdio_gpios: pmx-sdio-gpios { +- marvell,pins = "mpp37", "mpp38"; +- marvell,function = "gpio"; +- }; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- sata@80000 { +- nr-ports = <2>; +- status = "okay"; +- }; +- +- ehci@50000 { +- status = "okay"; +- }; +- +- mvsdio@90000 { +- pinctrl-0 = <&pmx_sdio_gpios>; +- pinctrl-names = "default"; +- wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- }; +-}; +- +-&nand { +- chip-delay = <25>; +- status = "okay"; +- +- partition@0 { +- label = "uboot"; +- reg = <0x0 0x100000>; +- }; +- +- partition@100000 { +- label = "uImage"; +- reg = <0x100000 0x400000>; +- }; +- +- partition@500000 { +- label = "root"; +- reg = <0x500000 0x1fb00000>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@8 { +- reg = <8>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-dir665.dts b/scripts/dtc/include-prefixes/arm/kirkwood-dir665.dts +deleted file mode 100644 +index b3ad3f607d31..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-dir665.dts ++++ /dev/null +@@ -1,276 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2014 Claudio Leite +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- model = "D-Link DIR-665"; +- compatible = "dlink,dir-665", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; /* 128 MB */ +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pinctrl-0 =< &pmx_led_usb +- &pmx_led_internet_blue +- &pmx_led_internet_amber +- &pmx_led_5g &pmx_led_status_blue +- &pmx_led_wps &pmx_led_status_amber +- &pmx_led_24g +- &pmx_btn_restart &pmx_btn_wps>; +- pinctrl-names = "default"; +- +- pmx_led_usb: pmx-led-usb { +- marvell,pins = "mpp12"; +- marvell,function = "gpio"; +- }; +- pmx_led_internet_blue: pmx-led-internet-blue { +- marvell,pins = "mpp42"; +- marvell,function = "gpio"; +- }; +- pmx_led_internet_amber: pmx-led-internet-amber { +- marvell,pins = "mpp43"; +- marvell,function = "gpio"; +- }; +- pmx_led_5g: pmx-led-5g { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- pmx_led_status_blue: pmx-led-status-blue { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- pmx_led_wps: pmx-led-wps { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- pmx_led_status_amber: pmx-led-status-amber { +- marvell,pins = "mpp48"; +- marvell,function = "gpio"; +- }; +- pmx_led_24g: pmx-led-24g { +- marvell,pins = "mpp49"; +- marvell,function = "gpio"; +- }; +- pmx_btn_restart: pmx-btn-restart { +- marvell,pins = "mpp28"; +- marvell,function = "gpio"; +- }; +- pmx_btn_wps: pmx-btn-wps { +- marvell,pins = "mpp46"; +- marvell,function = "gpio"; +- }; +- }; +- +- spi@10600 { +- status = "okay"; +- m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- reg = <0>; +- +- partition@0 { +- label = "uboot"; +- reg = <0x0 0x30000>; +- read-only; +- }; +- +- partition@30000 { +- label = "nvram"; +- reg = <0x30000 0x10000>; +- read-only; +- }; +- +- partition@40000 { +- label = "kernel"; +- reg = <0x40000 0x180000>; +- }; +- +- partition@1c0000 { +- label = "rootfs"; +- reg = <0x1c0000 0xe00000>; +- }; +- +- cal_data: partition@fc0000 { +- label = "cal_data"; +- reg = <0xfc0000 0x10000>; +- read-only; +- }; +- +- partition@fd0000 { +- label = "lang_pack"; +- reg = <0xfd0000 0x30000>; +- read-only; +- }; +- }; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- i2c@11000 { +- status = "okay"; +- }; +- +- ehci@50000 { +- status = "okay"; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- blue-usb { +- label = "dir665:blue:usb"; +- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; +- }; +- blue-internet { +- /* Can only be turned on if the Internet +- * Ethernet port has Link +- */ +- label = "dir665:blue:internet"; +- gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; +- }; +- amber-internet { +- label = "dir665:amber:internet"; +- gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; +- }; +- blue-wifi5g { +- label = "dir665:blue:5g"; +- gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; +- }; +- blue-status { +- label = "dir665:blue:status"; +- gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; +- }; +- blue-wps { +- label = "dir665:blue:wps"; +- gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; +- }; +- amber-status { +- label = "dir665:amber:status"; +- gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; +- }; +- blue-24g { +- label = "dir665:blue:24g"; +- gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reset { +- label = "reset"; +- linux,code = ; +- gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; +- }; +- wps { +- label = "wps"; +- linux,code = ; +- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- switch@0 { +- compatible = "marvell,mv88e6085"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan4"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan3"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan1"; +- }; +- +- port@4 { +- reg = <4>; +- label = "wan"; +- }; +- +- port@6 { +- reg = <6>; +- label = "cpu"; +- ethernet = <ð0port>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; +-}; +- +-/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set +- * fixed speed and duplex. */ +-ð0 { +- status = "okay"; +- +- ethernet0-port@0 { +- speed = <1000>; +- duplex = <1>; +- }; +-}; +- +-/* eth1 is connected to the switch as well. However DSA only supports a +- * single CPU port. So leave this port disabled to avoid confusion. */ +- +-ð1 { +- status = "disabled"; +-}; +- +-/* There is no battery on the boards, so the RTC does not keep time +- * when there is no power, making it useless. */ +-&rtc { +- status = "disabled"; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-dns320.dts b/scripts/dtc/include-prefixes/arm/kirkwood-dns320.dts +deleted file mode 100644 +index d6b0f418fd01..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-dns320.dts ++++ /dev/null +@@ -1,59 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood-dnskw.dtsi" +- +-/ { +- model = "D-Link DNS-320 NAS (Rev A1)"; +- compatible = "dlink,dns-320-a1", "dlink,dns-320", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_320 +- &pmx_led_red_left_hdd &pmx_led_red_right_hdd +- &pmx_led_white_usb>; +- pinctrl-names = "default"; +- +- blue-power { +- label = "dns320:blue:power"; +- gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- blue-usb { +- label = "dns320:blue:usb"; +- gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; +- }; +- orange-l_hdd { +- label = "dns320:orange:l_hdd"; +- gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; +- }; +- orange-r_hdd { +- label = "dns320:orange:r_hdd"; +- gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; +- }; +- orange-usb { +- label = "dns320:orange:usb"; +- gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; /* GPIO 35 */ +- }; +- }; +- +- ocp@f1000000 { +- serial@12000 { +- status = "okay"; +- }; +- +- serial@12100 { +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-dns325.dts b/scripts/dtc/include-prefixes/arm/kirkwood-dns325.dts +deleted file mode 100644 +index 94d9c06cbbf5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-dns325.dts ++++ /dev/null +@@ -1,63 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood-dnskw.dtsi" +- +-/ { +- model = "D-Link DNS-325 NAS (Rev A1)"; +- compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_325 +- &pmx_led_red_left_hdd &pmx_led_red_right_hdd +- &pmx_led_white_usb>; +- pinctrl-names = "default"; +- +- white-power { +- label = "dns325:white:power"; +- gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- white-usb { +- label = "dns325:white:usb"; +- gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* GPIO 43 */ +- }; +- red-l_hdd { +- label = "dns325:red:l_hdd"; +- gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; +- }; +- red-r_hdd { +- label = "dns325:red:r_hdd"; +- gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; +- }; +- red-usb { +- label = "dns325:red:usb"; +- gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- ocp@f1000000 { +- i2c@11000 { +- status = "okay"; +- +- lm75: lm75@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +- }; +- serial@12000 { +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-dnskw.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-dnskw.dtsi +deleted file mode 100644 +index eb917462b219..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-dnskw.dtsi ++++ /dev/null +@@ -1,235 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- model = "D-Link DNS NASes (kirkwood-based)"; +- compatible = "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_button_power &pmx_button_unmount +- &pmx_button_reset>; +- pinctrl-names = "default"; +- +- power { +- label = "Power button"; +- linux,code = ; +- gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; +- }; +- eject { +- label = "USB unmount button"; +- linux,code = ; +- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +- }; +- reset { +- label = "Reset button"; +- linux,code = ; +- gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio_fan { +- /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */ +- compatible = "gpio-fan"; +- pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>; +- pinctrl-names = "default"; +- gpios = <&gpio1 14 GPIO_ACTIVE_HIGH +- &gpio1 13 GPIO_ACTIVE_HIGH>; +- gpio-fan,speed-map = <0 0 +- 3000 1 +- 6000 2>; +- }; +- +- gpio_poweroff { +- compatible = "gpio-poweroff"; +- pinctrl-0 = <&pmx_power_off>; +- pinctrl-names = "default"; +- gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- +- pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0 +- &pmx_present_sata1 &pmx_fan_tacho +- &pmx_temp_alarm>; +- pinctrl-names = "default"; +- +- pmx_sata0: pmx-sata0 { +- marvell,pins = "mpp20"; +- marvell,function = "sata1"; +- }; +- pmx_sata1: pmx-sata1 { +- marvell,pins = "mpp21"; +- marvell,function = "sata0"; +- }; +- pmx_led_power: pmx-led-power { +- marvell,pins = "mpp26"; +- marvell,function = "gpio"; +- }; +- pmx_led_red_right_hdd: pmx-led-red-right-hdd { +- marvell,pins = "mpp27"; +- marvell,function = "gpio"; +- }; +- pmx_led_red_left_hdd: pmx-led-red-left-hdd { +- marvell,pins = "mpp28"; +- marvell,function = "gpio"; +- }; +- pmx_led_red_usb_325: pmx-led-red-usb-325 { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- pmx_button_power: pmx-button-power { +- marvell,pins = "mpp34"; +- marvell,function = "gpio"; +- }; +- pmx_led_red_usb_320: pmx-led-red-usb-320 { +- marvell,pins = "mpp35"; +- marvell,function = "gpio"; +- }; +- pmx_power_off: pmx-power-off { +- marvell,pins = "mpp36"; +- marvell,function = "gpio"; +- }; +- pmx_power_back_on: pmx-power-back-on { +- marvell,pins = "mpp37"; +- marvell,function = "gpio"; +- }; +- pmx_power_sata0: pmx-power-sata0 { +- marvell,pins = "mpp39"; +- marvell,function = "gpio"; +- }; +- pmx_power_sata1: pmx-power-sata1 { +- marvell,pins = "mpp40"; +- marvell,function = "gpio"; +- }; +- pmx_present_sata0: pmx-present-sata0 { +- marvell,pins = "mpp41"; +- marvell,function = "gpio"; +- }; +- pmx_present_sata1: pmx-present-sata1 { +- marvell,pins = "mpp42"; +- marvell,function = "gpio"; +- }; +- pmx_led_white_usb: pmx-led-white-usb { +- marvell,pins = "mpp43"; +- marvell,function = "gpio"; +- }; +- pmx_fan_tacho: pmx-fan-tacho { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- pmx_fan_high_speed: pmx-fan-high-speed { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- pmx_fan_low_speed: pmx-fan-low-speed { +- marvell,pins = "mpp46"; +- marvell,function = "gpio"; +- }; +- pmx_button_unmount: pmx-button-unmount { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- pmx_button_reset: pmx-button-reset { +- marvell,pins = "mpp48"; +- marvell,function = "gpio"; +- }; +- pmx_temp_alarm: pmx-temp-alarm { +- marvell,pins = "mpp49"; +- marvell,function = "gpio"; +- }; +- }; +- sata@80000 { +- pinctrl-0 = <&pmx_sata0 &pmx_sata1>; +- pinctrl-names = "default"; +- status = "okay"; +- nr-ports = <2>; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>; +- pinctrl-names = "default"; +- +- sata0_power: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "SATA0 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 7 0>; +- }; +- sata1_power: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "SATA1 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 8 0>; +- }; +- }; +-}; +- +-&nand { +- status = "okay"; +- chip-delay = <35>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x100000>; +- read-only; +- }; +- +- partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x500000>; +- }; +- +- partition@600000 { +- label = "ramdisk"; +- reg = <0x0600000 0x500000>; +- }; +- +- partition@b00000 { +- label = "image"; +- reg = <0x0b00000 0x6600000>; +- }; +- +- partition@7100000 { +- label = "mini firmware"; +- reg = <0x7100000 0xa00000>; +- }; +- +- partition@7b00000 { +- label = "config"; +- reg = <0x7b00000 0x500000>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@8 { +- reg = <8>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-dockstar.dts b/scripts/dtc/include-prefixes/arm/kirkwood-dockstar.dts +deleted file mode 100644 +index 264938dfa4d9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-dockstar.dts ++++ /dev/null +@@ -1,110 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- model = "Seagate FreeAgent Dockstar"; +- compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_usb_power_enable: pmx-usb-power-enable { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- pmx_led_green: pmx-led-green { +- marvell,pins = "mpp46"; +- marvell,function = "gpio"; +- }; +- pmx_led_orange: pmx-led-orange { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- }; +- serial@12000 { +- status = "okay"; +- }; +- }; +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_led_green &pmx_led_orange>; +- pinctrl-names = "default"; +- +- health { +- label = "status:green:health"; +- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- fault { +- label = "status:orange:fault"; +- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +- }; +- }; +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_usb_power_enable>; +- pinctrl-names = "default"; +- +- usb_power: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "USB Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 29 0>; +- }; +- }; +-}; +- +-&nand { +- status = "okay"; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x100000>; +- read-only; +- }; +- +- partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x400000>; +- }; +- +- partition@500000 { +- label = "data"; +- reg = <0x0500000 0xfb00000>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- compatible = "marvell,88e1116"; +- reg = <0>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-dreamplug.dts b/scripts/dtc/include-prefixes/arm/kirkwood-dreamplug.dts +deleted file mode 100644 +index 328516351e84..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-dreamplug.dts ++++ /dev/null +@@ -1,127 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- model = "Globalscale Technologies Dreamplug"; +- compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_led_bluetooth: pmx-led-bluetooth { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- pmx_led_wifi: pmx-led-wifi { +- marvell,pins = "mpp48"; +- marvell,function = "gpio"; +- }; +- pmx_led_wifi_ap: pmx-led-wifi-ap { +- marvell,pins = "mpp49"; +- marvell,function = "gpio"; +- }; +- }; +- serial@12000 { +- status = "okay"; +- }; +- +- spi@10600 { +- status = "okay"; +- +- m25p40@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mxicy,mx25l1606e", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- mode = <0>; +- +- partition@0 { +- reg = <0x0 0x80000>; +- label = "u-boot"; +- }; +- +- partition@100000 { +- reg = <0x100000 0x10000>; +- label = "u-boot env"; +- }; +- +- partition@180000 { +- reg = <0x180000 0x10000>; +- label = "dtb"; +- }; +- }; +- }; +- +- sata@80000 { +- status = "okay"; +- nr-ports = <1>; +- }; +- +- mvsdio@90000 { +- pinctrl-0 = <&pmx_sdio>; +- pinctrl-names = "default"; +- status = "okay"; +- /* No CD or WP GPIOs */ +- broken-cd; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_led_bluetooth &pmx_led_wifi +- &pmx_led_wifi_ap >; +- pinctrl-names = "default"; +- +- bluetooth { +- label = "dreamplug:blue:bluetooth"; +- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +- }; +- wifi { +- label = "dreamplug:green:wifi"; +- gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +- }; +- wifi-ap { +- label = "dreamplug:green:wifi_ap"; +- gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- +-ð1 { +- status = "okay"; +- ethernet1-port@0 { +- phy-handle = <ðphy1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ds109.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ds109.dts +deleted file mode 100644 +index 29982e7acb7f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ds109.dts ++++ /dev/null +@@ -1,40 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Andrew Lunn +- * Ben Peddell +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +-#include "kirkwood-synology.dtsi" +- +-/ { +- model = "Synology DS109, DS110, DS110jv20"; +- compatible = "synology,ds109", "synology,ds110jv20", +- "synology,ds110", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio-fan-150-32-35 { +- status = "okay"; +- }; +- +- gpio-leds-hdd-21-1 { +- status = "okay"; +- }; +-}; +- +-&rs5c372 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ds110jv10.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ds110jv10.dts +deleted file mode 100644 +index d68c616e9309..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ds110jv10.dts ++++ /dev/null +@@ -1,40 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Andrew Lunn +- * Ben Peddell +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +-#include "kirkwood-synology.dtsi" +- +-/ { +- model = "Synology DS110j v10 and v30"; +- compatible = "synology,ds110jv10", "synology,ds110jv30", +- "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio-fan-150-32-35 { +- status = "okay"; +- }; +- +- gpio-leds-hdd-21-1 { +- status = "okay"; +- }; +-}; +- +-&s35390a { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ds111.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ds111.dts +deleted file mode 100644 +index e1420cbcd7e4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ds111.dts ++++ /dev/null +@@ -1,43 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Andrew Lunn +- * Ben Peddell +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6282.dtsi" +-#include "kirkwood-synology.dtsi" +- +-/ { +- model = "Synology DS111"; +- compatible = "synology,ds111", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio-fan-100-15-35-1 { +- status = "okay"; +- }; +- +- gpio-leds-hdd-21-1 { +- status = "okay"; +- }; +-}; +- +-&s35390a { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ds112.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ds112.dts +deleted file mode 100644 +index f48609e95afe..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ds112.dts ++++ /dev/null +@@ -1,51 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Andrew Lunn +- * Ben Peddell +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6282.dtsi" +-#include "kirkwood-synology.dtsi" +- +-/ { +- model = "Synology DS112"; +- compatible = "synology,ds111", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio-fan-100-15-35-1 { +- status = "okay"; +- }; +- +- gpio-leds-21-2 { +- status = "okay"; +- }; +- +- regulators-hdd-30 { +- status = "okay"; +- }; +-}; +- +-&s35390a { +- status = "okay"; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ds209.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ds209.dts +deleted file mode 100644 +index f41fe95e055f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ds209.dts ++++ /dev/null +@@ -1,43 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Andrew Lunn +- * Ben Peddell +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +-#include "kirkwood-synology.dtsi" +- +-/ { +- model = "Synology DS209"; +- compatible = "synology,ds209", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio-fan-150-32-35 { +- status = "okay"; +- }; +- +- gpio-leds-hdd-21-2 { +- status = "okay"; +- }; +- +- regulators-hdd-31 { +- status = "okay"; +- }; +-}; +- +-&rs5c372 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ds210.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ds210.dts +deleted file mode 100644 +index 729f959a7838..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ds210.dts ++++ /dev/null +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Andrew Lunn +- * Ben Peddell +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +-#include "kirkwood-synology.dtsi" +- +-/ { +- model = "Synology DS210 v10, v20, v30, DS211j"; +- compatible = "synology,ds210jv10", "synology,ds210jv20", +- "synology,ds210jv30", "synology,ds211j", +- "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio-fan-150-32-35 { +- status = "okay"; +- }; +- +- gpio-leds-hdd-21-2 { +- status = "okay"; +- }; +- +- regulators-hdd-31 { +- status = "okay"; +- }; +-}; +- +-&s35390a { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ds212.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ds212.dts +deleted file mode 100644 +index 416bab50d170..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ds212.dts ++++ /dev/null +@@ -1,46 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Andrew Lunn +- * Ben Peddell +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6282.dtsi" +-#include "kirkwood-synology.dtsi" +- +-/ { +- model = "Synology DS212, DS212p v10, v20, DS213air v10, DS213 v10"; +- compatible = "synology,ds212", "synology,ds212pv10", +- "synology,ds212pv10", "synology,ds212pv20", +- "synology,ds213airv10", "synology,ds213v10", +- "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio-fan-100-15-35-1 { +- status = "okay"; +- }; +- +- gpio-leds-hdd-21-2 { +- status = "okay"; +- }; +-}; +- +-&s35390a { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ds212j.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ds212j.dts +deleted file mode 100644 +index 14cf4d8afaf3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ds212j.dts ++++ /dev/null +@@ -1,40 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Andrew Lunn +- * Ben Peddell +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +-#include "kirkwood-synology.dtsi" +- +-/ { +- model = "Synology DS212j v10, v20"; +- compatible = "synology,ds212jv10", "synology,ds212jv20", +- "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio-fan-100-32-35 { +- status = "okay"; +- }; +- +- gpio-leds-hdd-21-2 { +- status = "okay"; +- }; +-}; +- +-&s35390a { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ds409.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ds409.dts +deleted file mode 100644 +index a8650f9e3eb7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ds409.dts ++++ /dev/null +@@ -1,47 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Andrew Lunn +- * Ben Peddell +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +-#include "kirkwood-synology.dtsi" +- +-/ { +- model = "Synology DS409, DS410j"; +- compatible = "synology,ds409", "synology,ds410j", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio-fan-150-15-18 { +- status = "okay"; +- }; +- +- gpio-leds-hdd-36 { +- status = "okay"; +- }; +- +- gpio-leds-alarm-12 { +- status = "okay"; +- }; +-}; +- +-ð1 { +- status = "okay"; +-}; +- +-&rs5c372 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ds409slim.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ds409slim.dts +deleted file mode 100644 +index 27a1d840bd15..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ds409slim.dts ++++ /dev/null +@@ -1,39 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Andrew Lunn +- * Ben Peddell +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +-#include "kirkwood-synology.dtsi" +- +-/ { +- model = "Synology 409slim"; +- compatible = "synology,ds409slim", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio-fan-150-32-35 { +- status = "okay"; +- }; +- +- gpio-leds-hdd-20 { +- status = "okay"; +- }; +-}; +- +-&rs5c372 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ds411.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ds411.dts +deleted file mode 100644 +index 86907be70cf9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ds411.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Andrew Lunn +- * Ben Peddell +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6282.dtsi" +-#include "kirkwood-synology.dtsi" +- +-/ { +- model = "Synology DS411, DS413jv10"; +- compatible = "synology,ds411", "synology,ds413jv10", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio-fan-100-15-35-1 { +- status = "okay"; +- }; +- +- gpio-leds-hdd-36 { +- status = "okay"; +- }; +- +- regulators-hdd-34 { +- status = "okay"; +- }; +-}; +- +-ð1 { +- status = "okay"; +-}; +- +-&s35390a { +- status = "okay"; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ds411j.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ds411j.dts +deleted file mode 100644 +index bb3200daea1e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ds411j.dts ++++ /dev/null +@@ -1,47 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Andrew Lunn +- * Ben Peddell +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +-#include "kirkwood-synology.dtsi" +- +-/ { +- model = "Synology DS411j"; +- compatible = "synology,ds411j", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio-fan-150-15-18 { +- status = "okay"; +- }; +- +- gpio-leds-hdd-36 { +- status = "okay"; +- }; +- +- gpio-leds-alarm-12 { +- status = "okay"; +- }; +-}; +- +-ð1 { +- status = "okay"; +-}; +- +-&s35390a { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ds411slim.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ds411slim.dts +deleted file mode 100644 +index 9c5364a4e0a8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ds411slim.dts ++++ /dev/null +@@ -1,47 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Andrew Lunn +- * Ben Peddell +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6282.dtsi" +-#include "kirkwood-synology.dtsi" +- +-/ { +- model = "Synology DS411slim"; +- compatible = "synology,ds411slim", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio-fan-100-15-35-1 { +- status = "okay"; +- }; +- +- gpio-leds-hdd-36 { +- status = "okay"; +- }; +-}; +- +-ð1 { +- status = "okay"; +-}; +- +-&s35390a { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-goflexnet.dts b/scripts/dtc/include-prefixes/arm/kirkwood-goflexnet.dts +deleted file mode 100644 +index d4cb3cd3e2a2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-goflexnet.dts ++++ /dev/null +@@ -1,190 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- model = "Seagate GoFlex Net"; +- compatible = "seagate,goflexnet", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_usb_power_enable: pmx-usb-power-enable { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- pmx_led_right_cap_0: pmx-led_right_cap_0 { +- marvell,pins = "mpp38"; +- marvell,function = "gpio"; +- }; +- pmx_led_right_cap_1: pmx-led_right_cap_1 { +- marvell,pins = "mpp39"; +- marvell,function = "gpio"; +- }; +- pmx_led_right_cap_2: pmx-led_right_cap_2 { +- marvell,pins = "mpp40"; +- marvell,function = "gpio"; +- }; +- pmx_led_right_cap_3: pmx-led_right_cap_3 { +- marvell,pins = "mpp41"; +- marvell,function = "gpio"; +- }; +- pmx_led_left_cap_0: pmx-led_left_cap_0 { +- marvell,pins = "mpp42"; +- marvell,function = "gpio"; +- }; +- pmx_led_left_cap_1: pmx-led_left_cap_1 { +- marvell,pins = "mpp43"; +- marvell,function = "gpio"; +- }; +- pmx_led_left_cap_2: pmx-led_left_cap_2 { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- pmx_led_left_cap_3: pmx-led_left_cap_3 { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- pmx_led_green: pmx-led_green { +- marvell,pins = "mpp46"; +- marvell,function = "gpio"; +- }; +- pmx_led_orange: pmx-led_orange { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- }; +- serial@12000 { +- status = "okay"; +- }; +- +- sata@80000 { +- status = "okay"; +- nr-ports = <2>; +- }; +- +- }; +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = < &pmx_led_orange +- &pmx_led_left_cap_0 &pmx_led_left_cap_1 +- &pmx_led_left_cap_2 &pmx_led_left_cap_3 +- &pmx_led_right_cap_0 &pmx_led_right_cap_1 +- &pmx_led_right_cap_2 &pmx_led_right_cap_3 +- >; +- pinctrl-names = "default"; +- +- health { +- label = "status:green:health"; +- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- fault { +- label = "status:orange:fault"; +- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +- }; +- left0 { +- label = "status:white:left0"; +- gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; +- }; +- left1 { +- label = "status:white:left1"; +- gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; +- }; +- left2 { +- label = "status:white:left2"; +- gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; +- }; +- left3 { +- label = "status:white:left3"; +- gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; +- }; +- right0 { +- label = "status:white:right0"; +- gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; +- }; +- right1 { +- label = "status:white:right1"; +- gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- }; +- right2 { +- label = "status:white:right2"; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- }; +- right3 { +- label = "status:white:right3"; +- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- }; +- }; +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_usb_power_enable>; +- pinctrl-names = "default"; +- +- usb_power: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "USB Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&nand { +- chip-delay = <40>; +- status = "okay"; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x100000>; +- read-only; +- }; +- +- partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x400000>; +- }; +- +- partition@500000 { +- label = "pogoplug"; +- reg = <0x0500000 0x2000000>; +- }; +- +- partition@2500000 { +- label = "root"; +- reg = <0x02500000 0xd800000>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-guruplug-server-plus.dts b/scripts/dtc/include-prefixes/arm/kirkwood-guruplug-server-plus.dts +deleted file mode 100644 +index dfb41393941d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-guruplug-server-plus.dts ++++ /dev/null +@@ -1,133 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- model = "Globalscale Technologies Guruplug Server Plus"; +- compatible = "globalscale,guruplug-server-plus", "globalscale,guruplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_led_health_r: pmx-led-health-r { +- marvell,pins = "mpp46"; +- marvell,function = "gpio"; +- }; +- pmx_led_health_g: pmx-led-health-g { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- pmx_led_wmode_r: pmx-led-wmode-r { +- marvell,pins = "mpp48"; +- marvell,function = "gpio"; +- }; +- pmx_led_wmode_g: pmx-led-wmode-g { +- marvell,pins = "mpp49"; +- marvell,function = "gpio"; +- }; +- }; +- serial@12000 { +- status = "okay"; +- }; +- +- sata@80000 { +- status = "okay"; +- nr-ports = <1>; +- }; +- +- /* AzureWave AW-GH381 WiFi/BT */ +- mvsdio@90000 { +- status = "okay"; +- non-removable; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g +- &pmx_led_wmode_r &pmx_led_wmode_g >; +- pinctrl-names = "default"; +- +- health-r { +- label = "guruplug:red:health"; +- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- }; +- health-g { +- label = "guruplug:green:health"; +- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +- }; +- wmode-r { +- label = "guruplug:red:wmode"; +- gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +- }; +- wmode-g { +- label = "guruplug:green:wmode"; +- gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&nand { +- status = "okay"; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x00000000 0x00100000>; +- read-only; +- }; +- +- partition@100000 { +- label = "uImage"; +- reg = <0x00100000 0x00400000>; +- }; +- +- partition@500000 { +- label = "data"; +- reg = <0x00500000 0x1fb00000>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- /* Marvell 88E1121R */ +- compatible = "ethernet-phy-id0141.0cb0", +- "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- /* Marvell 88E1121R */ +- compatible = "ethernet-phy-id0141.0cb0", +- "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- phy-connection-type = "rgmii-id"; +- }; +-}; +- +-ð1 { +- status = "okay"; +- ethernet1-port@0 { +- phy-handle = <ðphy1>; +- phy-connection-type = "rgmii-id"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ib62x0.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ib62x0.dts +deleted file mode 100644 +index 962a910a6f5c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ib62x0.dts ++++ /dev/null +@@ -1,146 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; +- compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_led_os_red: pmx-led-os-red { +- marvell,pins = "mpp22"; +- marvell,function = "gpio"; +- }; +- pmx_power_off: pmx-power-off { +- marvell,pins = "mpp24"; +- marvell,function = "gpio"; +- }; +- pmx_led_os_green: pmx-led-os-green { +- marvell,pins = "mpp25"; +- marvell,function = "gpio"; +- }; +- pmx_led_usb_transfer: pmx-led-usb-transfer { +- marvell,pins = "mpp27"; +- marvell,function = "gpio"; +- }; +- pmx_button_reset: pmx-button-reset { +- marvell,pins = "mpp28"; +- marvell,function = "gpio"; +- }; +- pmx_button_usb_copy: pmx-button-usb-copy { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- sata@80000 { +- status = "okay"; +- nr-ports = <2>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>; +- pinctrl-names = "default"; +- +- copy { +- label = "USB Copy"; +- linux,code = ; +- gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; +- }; +- reset { +- label = "Reset"; +- linux,code = ; +- gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green +- &pmx_led_usb_transfer>; +- pinctrl-names = "default"; +- +- green-os { +- label = "ib62x0:green:os"; +- gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; +- }; +- red-os { +- label = "ib62x0:red:os"; +- gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; +- }; +- usb-copy { +- label = "ib62x0:red:usb_copy"; +- gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio_poweroff { +- compatible = "gpio-poweroff"; +- pinctrl-0 = <&pmx_power_off>; +- pinctrl-names = "default"; +- gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&nand { +- status = "okay"; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0xe0000>; +- }; +- +- partition@e0000 { +- label = "u-boot environment"; +- reg = <0xe0000 0x20000>; +- }; +- +- partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x600000>; +- }; +- +- partition@700000 { +- label = "root"; +- reg = <0x0700000 0xf900000>; +- }; +- +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@8 { +- reg = <8>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-iconnect.dts b/scripts/dtc/include-prefixes/arm/kirkwood-iconnect.dts +deleted file mode 100644 +index 95af7aa1fdcb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-iconnect.dts ++++ /dev/null +@@ -1,195 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- model = "Iomega Iconnect"; +- compatible = "iom,iconnect-1.1", "iom,iconnect", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- linux,initrd-start = <0x4500040>; +- linux,initrd-end = <0x4800000>; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_button_reset: pmx-button-reset { +- marvell,pins = "mpp12"; +- marvell,function = "gpio"; +- }; +- pmx_button_otb: pmx-button-otb { +- marvell,pins = "mpp35"; +- marvell,function = "gpio"; +- }; +- pmx_led_level: pmx-led-level { +- marvell,pins = "mpp41"; +- marvell,function = "gpio"; +- }; +- pmx_led_power_blue: pmx-led-power-blue { +- marvell,pins = "mpp42"; +- marvell,function = "gpio"; +- }; +- pmx_led_power_red: pmx-power-red { +- marvell,pins = "mpp43"; +- marvell,function = "gpio"; +- }; +- pmx_led_usb1: pmx-led-usb1 { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- pmx_led_usb2: pmx-led-usb2 { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- pmx_led_usb3: pmx-led-usb3 { +- marvell,pins = "mpp46"; +- marvell,function = "gpio"; +- }; +- pmx_led_usb4: pmx-led-usb4 { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- pmx_led_otb: pmx-led-otb { +- marvell,pins = "mpp48"; +- marvell,function = "gpio"; +- }; +- }; +- i2c@11000 { +- status = "okay"; +- +- lm63: lm63@4c { +- compatible = "national,lm63"; +- reg = <0x4c>; +- }; +- }; +- serial@12000 { +- status = "okay"; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = < &pmx_led_level &pmx_led_power_blue +- &pmx_led_power_red &pmx_led_usb1 +- &pmx_led_usb2 &pmx_led_usb3 +- &pmx_led_usb4 &pmx_led_otb >; +- pinctrl-names = "default"; +- +- led-level { +- label = "led_level"; +- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- power-blue { +- label = "power:blue"; +- gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; +- }; +- power-red { +- label = "power:red"; +- gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; +- }; +- usb1 { +- label = "usb1:blue"; +- gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; +- }; +- usb2 { +- label = "usb2:blue"; +- gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; +- }; +- usb3 { +- label = "usb3:blue"; +- gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; +- }; +- usb4 { +- label = "usb4:blue"; +- gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; +- }; +- otb { +- label = "otb:blue"; +- gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = < &pmx_button_reset &pmx_button_otb >; +- pinctrl-names = "default"; +- +- otb { +- label = "OTB Button"; +- linux,code = ; +- gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; +- debounce-interval = <100>; +- }; +- reset { +- label = "Reset"; +- linux,code = ; +- gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; +- debounce-interval = <100>; +- }; +- }; +-}; +- +-&nand { +- status = "okay"; +- +- partition@0 { +- label = "uboot"; +- reg = <0x0000000 0xc0000>; +- }; +- +- partition@a0000 { +- label = "env"; +- reg = <0xa0000 0x20000>; +- }; +- +- partition@100000 { +- label = "zImage"; +- reg = <0x100000 0x300000>; +- }; +- +- partition@540000 { +- label = "initrd"; +- reg = <0x540000 0x300000>; +- }; +- +- partition@980000 { +- label = "boot"; +- reg = <0x980000 0x1f400000>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@11 { +- reg = <11>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-iomega_ix2_200.dts b/scripts/dtc/include-prefixes/arm/kirkwood-iomega_ix2_200.dts +deleted file mode 100644 +index 2338f495d517..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-iomega_ix2_200.dts ++++ /dev/null +@@ -1,226 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- model = "Iomega StorCenter ix2-200"; +- compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pinctrl-0 = < &pmx_led_sata_brt_ctrl_1 +- &pmx_led_sata_brt_ctrl_2 +- &pmx_led_backup_brt_ctrl_1 +- &pmx_led_backup_brt_ctrl_2 +- &pmx_led_power_brt_ctrl_1 +- &pmx_led_power_brt_ctrl_2 +- &pmx_led_health_brt_ctrl_1 +- &pmx_led_health_brt_ctrl_2 +- &pmx_led_rebuild_brt_ctrl_1 +- &pmx_led_rebuild_brt_ctrl_2 >; +- pinctrl-names = "default"; +- +- pmx_button_reset: pmx-button-reset { +- marvell,pins = "mpp12"; +- marvell,function = "gpio"; +- }; +- pmx_button_power: pmx-button-power { +- marvell,pins = "mpp14"; +- marvell,function = "gpio"; +- }; +- pmx_led_backup: pmx-led-backup { +- marvell,pins = "mpp15"; +- marvell,function = "gpio"; +- }; +- pmx_led_power: pmx-led-power { +- marvell,pins = "mpp16"; +- marvell,function = "gpio"; +- }; +- pmx_button_otb: pmx-button-otb { +- marvell,pins = "mpp35"; +- marvell,function = "gpio"; +- }; +- pmx_led_rebuild: pmx-led-rebuild { +- marvell,pins = "mpp36"; +- marvell,function = "gpio"; +- }; +- pmx_led_health: pmx-led_health { +- marvell,pins = "mpp37"; +- marvell,function = "gpio"; +- }; +- pmx_led_sata_brt_ctrl_1: pmx-led-sata-brt-ctrl-1 { +- marvell,pins = "mpp38"; +- marvell,function = "gpio"; +- }; +- pmx_led_sata_brt_ctrl_2: pmx-led-sata-brt-ctrl-2 { +- marvell,pins = "mpp39"; +- marvell,function = "gpio"; +- }; +- pmx_led_backup_brt_ctrl_1: pmx-led-backup-brt-ctrl-1 { +- marvell,pins = "mpp40"; +- marvell,function = "gpio"; +- }; +- pmx_led_backup_brt_ctrl_2: pmx-led-backup-brt-ctrl-2 { +- marvell,pins = "mpp41"; +- marvell,function = "gpio"; +- }; +- pmx_led_power_brt_ctrl_1: pmx-led-power-brt-ctrl-1 { +- marvell,pins = "mpp42"; +- marvell,function = "gpio"; +- }; +- pmx_led_power_brt_ctrl_2: pmx-led-power-brt-ctrl-2 { +- marvell,pins = "mpp43"; +- marvell,function = "gpio"; +- }; +- pmx_led_health_brt_ctrl_1: pmx-led-health-brt-ctrl-1 { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- pmx_led_health_brt_ctrl_2: pmx-led-health-brt-ctrl-2 { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 { +- marvell,pins = "mpp46"; +- marvell,function = "gpio"; +- }; +- pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- +- }; +- i2c@11000 { +- status = "okay"; +- +- lm63: lm63@4c { +- compatible = "national,lm63"; +- reg = <0x4c>; +- }; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- sata@80000 { +- status = "okay"; +- nr-ports = <2>; +- }; +- +- }; +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = < &pmx_led_backup &pmx_led_power +- &pmx_led_rebuild &pmx_led_health >; +- pinctrl-names = "default"; +- +- power_led { +- label = "status:white:power_led"; +- gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; +- }; +- rebuild_led { +- label = "status:white:rebuild_led"; +- gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; +- }; +- health_led { +- label = "status:red:health_led"; +- gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- }; +- backup_led { +- label = "status:blue:backup_led"; +- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; +- }; +- }; +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_button_reset &pmx_button_power +- &pmx_button_otb>; +- pinctrl-names = "default"; +- +- +- Power { +- label = "Power Button"; +- linux,code = ; +- gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; +- }; +- Reset { +- label = "Reset Button"; +- linux,code = ; +- gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; +- }; +- OTB { +- label = "OTB Button"; +- linux,code = ; +- gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; +- }; +- }; +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&nand { +- status = "okay"; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x100000>; +- read-only; +- }; +- +- partition@a0000 { +- label = "env"; +- reg = <0xa0000 0x20000>; +- read-only; +- }; +- +- partition@100000 { +- label = "uImage"; +- reg = <0x100000 0x300000>; +- }; +- +- partition@400000 { +- label = "rootfs"; +- reg = <0x400000 0x1C00000>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy1: ethernet-phy@11 { +- reg = <11>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- speed = <1000>; +- duplex = <1>; +- }; +-}; +- +-ð1 { +- status = "okay"; +- ethernet1-port@0 { +- phy-handle = <ðphy1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-is2.dts b/scripts/dtc/include-prefixes/arm/kirkwood-is2.dts +deleted file mode 100644 +index 1bc16a5cdbaa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-is2.dts ++++ /dev/null +@@ -1,40 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include "kirkwood-ns2-common.dtsi" +- +-/ { +- model = "LaCie Internet Space v2"; +- compatible = "lacie,inetspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- ocp@f1000000 { +- sata@80000 { +- pinctrl-0 = <&pmx_ns2_sata0>; +- pinctrl-names = "default"; +- status = "okay"; +- nr-ports = <1>; +- }; +- }; +- +- ns2-leds { +- compatible = "lacie,ns2-leds"; +- +- blue-sata { +- label = "ns2:blue:sata"; +- slow-gpio = <&gpio0 29 0>; +- cmd-gpio = <&gpio0 30 0>; +- modes-map = ; +- }; +- }; +-}; +- +-ðphy0 { reg = <8>; }; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-km_common.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-km_common.dtsi +deleted file mode 100644 +index 75dc83914f56..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-km_common.dtsi ++++ /dev/null +@@ -1,47 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >; +- pinctrl-names = "default"; +- +- pmx_i2c_gpio_sda: pmx-gpio-sda { +- marvell,pins = "mpp8"; +- marvell,function = "gpio"; +- }; +- pmx_i2c_gpio_scl: pmx-gpio-scl { +- marvell,pins = "mpp9"; +- marvell,function = "gpio"; +- }; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- }; +- +- i2c { +- compatible = "i2c-gpio"; +- gpios = < &gpio0 8 GPIO_ACTIVE_HIGH /* sda */ +- &gpio0 9 GPIO_ACTIVE_HIGH>; /* scl */ +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- }; +-}; +- +-&nand { +- status = "okay"; +- chip-delay = <25>; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-km_fixedeth.dts b/scripts/dtc/include-prefixes/arm/kirkwood-km_fixedeth.dts +deleted file mode 100644 +index 515be7bccc0a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-km_fixedeth.dts ++++ /dev/null +@@ -1,24 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-98dx4122.dtsi" +-#include "kirkwood-km_common.dtsi" +- +-/ { +- model = "Keymile Kirkwood Fixed Eth"; +- compatible = "keymile,km_fixedeth", "marvell,kirkwood-98DX4122", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- speed = <1000>; /* */ +- duplex = <1>; /* */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-km_kirkwood.dts b/scripts/dtc/include-prefixes/arm/kirkwood-km_kirkwood.dts +deleted file mode 100644 +index f035eff1c111..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-km_kirkwood.dts ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-98dx4122.dtsi" +-#include "kirkwood-km_common.dtsi" +- +-/ { +- model = "Keymile Kirkwood Reference Design"; +- compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-l-50.dts b/scripts/dtc/include-prefixes/arm/kirkwood-l-50.dts +deleted file mode 100644 +index 0d81c43a6a73..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-l-50.dts ++++ /dev/null +@@ -1,438 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Check Point L-50 Board Description +- * Copyright 2020 Pawel Dembicki +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- model = "Check Point L-50"; +- compatible = "checkpoint,l-50", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pinctrl-0 = <&pmx_led38 &pmx_sysrst &pmx_button29>; +- pinctrl-names = "default"; +- +- pmx_sysrst: pmx-sysrst { +- marvell,pins = "mpp6"; +- marvell,function = "sysrst"; +- }; +- +- pmx_button29: pmx_button29 { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- +- pmx_led38: pmx_led38 { +- marvell,pins = "mpp38"; +- marvell,function = "gpio"; +- }; +- +- pmx_sdio_cd: pmx-sdio-cd { +- marvell,pins = "mpp46"; +- marvell,function = "gpio"; +- }; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- mvsdio@90000 { +- status = "okay"; +- cd-gpios = <&gpio1 14 9>; +- }; +- +- i2c@11000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- gpio2: gpio-expander@20{ +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- compatible = "semtech,sx1505q"; +- reg = <0x20>; +- +- gpio-controller; +- }; +- +- /* Three GPIOs from 0x21 exp. are undescribed in dts: +- * 1: DSL module reset (active low) +- * 5: mPCIE reset (active low) +- * 6: Express card reset (active low) +- */ +- gpio3: gpio-expander@21{ +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- compatible = "semtech,sx1505q"; +- reg = <0x21>; +- +- gpio-controller; +- }; +- +- rtc@30 { +- compatible = "s35390a"; +- reg = <0x30>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- status_green { +- label = "l-50:green:status"; +- gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; +- }; +- +- status_red { +- label = "l-50:red:status"; +- gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; +- }; +- +- wifi { +- label = "l-50:green:wifi"; +- gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "phy0tpt"; +- }; +- +- internet_green { +- label = "l-50:green:internet"; +- gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; +- }; +- +- internet_red { +- label = "l-50:red:internet"; +- gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +- }; +- +- usb1_green { +- label = "l-50:green:usb1"; +- gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "usbport"; +- trigger-sources = <&hub_port3>; +- }; +- +- usb1_red { +- label = "l-50:red:usb1"; +- gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; +- }; +- +- usb2_green { +- label = "l-50:green:usb2"; +- gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "usbport"; +- trigger-sources = <&hub_port1>; +- }; +- +- usb2_red { +- label = "l-50:red:usb2"; +- gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- usb2_pwr { +- compatible = "regulator-fixed"; +- regulator-name = "usb2_pwr"; +- +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 3 GPIO_ACTIVE_LOW>; +- regulator-always-on; +- }; +- +- usb1_pwr { +- compatible = "regulator-fixed"; +- regulator-name = "usb1_pwr"; +- +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; +- regulator-always-on; +- }; +- +- mpcie_pwr { +- compatible = "regulator-fixed"; +- regulator-name = "mpcie_pwr"; +- +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- express_card_pwr { +- compatible = "regulator-fixed"; +- regulator-name = "express_card_pwr"; +- +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- keys { +- compatible = "gpio-keys"; +- +- factory_defaults { +- label = "factory_defaults"; +- gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy8: ethernet-phy@8 { +- reg = <0x08>; +- }; +- +- switch0: switch@10 { +- compatible = "marvell,mv88e6085"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x10>; +- dsa,member = <0 0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan5"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan1"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan6"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan2"; +- }; +- +- port@4 { +- reg = <4>; +- label = "lan7"; +- }; +- +- switch0port5: port@5 { +- reg = <5>; +- phy-mode = "rgmii-txid"; +- link = <&switch1port5>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- port@6 { +- reg = <6>; +- label = "cpu"; +- phy-mode = "rgmii-id"; +- ethernet = <ð1port>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; +- +- switch@11 { +- compatible = "marvell,mv88e6085"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x11>; +- dsa,member = <0 1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan3"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan8"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan4"; +- }; +- +- port@3 { +- reg = <3>; +- label = "dmz"; +- }; +- +- switch1port5: port@5 { +- reg = <5>; +- phy-mode = "rgmii-txid"; +- link = <&switch0port5>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- port@6 { +- reg = <6>; +- label = "dsl"; +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +- }; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy8>; +- }; +-}; +- +-ð1 { +- status = "okay"; +- ethernet1-port@0 { +- speed = <1000>; +- duplex = <1>; +- }; +-}; +- +-&nand { +- status = "okay"; +- pinctrl-0 = <&pmx_nand>; +- pinctrl-names = "default"; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x00000000 0x000c0000>; +- }; +- +- partition@a0000 { +- label = "bootldr-env"; +- reg = <0x000c0000 0x00040000>; +- }; +- +- partition@100000 { +- label = "kernel-1"; +- reg = <0x00100000 0x00800000>; +- }; +- +- partition@900000 { +- label = "rootfs-1"; +- reg = <0x00900000 0x07100000>; +- }; +- +- partition@7a00000 { +- label = "kernel-2"; +- reg = <0x07a00000 0x00800000>; +- }; +- +- partition@8200000 { +- label = "rootfs-2"; +- reg = <0x08200000 0x07100000>; +- }; +- +- partition@f300000 { +- label = "default_sw"; +- reg = <0x0f300000 0x07900000>; +- }; +- +- partition@16c00000 { +- label = "logs"; +- reg = <0x16c00000 0x01800000>; +- }; +- +- partition@18400000 { +- label = "preset_cfg"; +- reg = <0x18400000 0x00100000>; +- }; +- +- partition@18500000 { +- label = "adsl"; +- reg = <0x18500000 0x00100000>; +- }; +- +- partition@18600000 { +- label = "storage"; +- reg = <0x18600000 0x07a00000>; +- }; +-}; +- +-&rtc { +- status = "disabled"; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&sata_phy0 { +- status = "disabled"; +-}; +- +-&sata_phy1 { +- status = "disabled"; +-}; +- +-&usb0 { +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- #trigger-source-cells = <0>; +- +- hub_port1: port@1 { +- reg = <1>; +- #trigger-source-cells = <0>; +- }; +- +- hub_port3: port@3 { +- reg = <3>; +- #trigger-source-cells = <0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-laplug.dts b/scripts/dtc/include-prefixes/arm/kirkwood-laplug.dts +deleted file mode 100644 +index 6158214a939a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-laplug.dts ++++ /dev/null +@@ -1,168 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2013 Maxime Hadjinlian +- * +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "kirkwood.dtsi" +-#include "kirkwood-6192.dtsi" +- +-/ { +- model = "LaCie LaPlug"; +- compatible = "lacie,laplug", "marvell,kirkwood-88f6192", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; /* 128 MB */ +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- serial@12000 { +- status = "okay"; +- }; +- +- i2c@11000 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c04"; +- pagesize = <16>; +- reg = <0x50>; +- }; +- }; +- +- pinctrl: pin-controller@10000 { +- pmx_usb_power_enable: pmx-usb-power-enable { +- marvell,pins = "mpp14"; +- marvell,function = "gpio"; +- }; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- power { +- label = "Power push button"; +- linux,code = ; +- gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- red-fail { +- label = "laplug_v2:red:power"; +- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; +- }; +- blue-power { +- label = "laplug_v2:blue:power"; +- gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- }; +- +- gpio_poweroff { +- compatible = "gpio-poweroff"; +- gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_usb_power_enable>; +- pinctrl-names = "default"; +- +- usb_power_back1: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "USB Power Back 1"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; +- }; +- +- usb_power_back2: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "USB Power Back 2"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>; +- }; +- +- usb_power_front: regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- regulator-name = "USB Power Front"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&nand { +- /* Total size : 512MB */ +- status = "okay"; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0 0x100000>; /* 1MB */ +- read-only; +- }; +- +- partition@100000 { +- label = "uImage"; +- reg = <0x100000 0x1000000>; /* 16MB */ +- }; +- +- partition@1100000 { +- label = "rootfs"; +- reg = <0x1100000 0x1EF00000>; /* 495MB */ +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- device_type = "ethernet-phy"; +- reg = <0>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-6282.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-6282.dtsi +deleted file mode 100644 +index 377b6e970259..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-6282.dtsi ++++ /dev/null +@@ -1,155 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree common file for kirkwood-6282 based Buffalo Linkstation +- * +- * Copyright (C) 2015, 2016 +- * Roger Shimizu +- */ +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6282.dtsi" +-#include "kirkwood-linkstation.dtsi" +- +-/ { +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_power_hdd0: pmx-power-hdd0 { +- marvell,pins = "mpp8"; +- marvell,function = "gpio"; +- }; +- pmx_usb_vbus: pmx-usb-vbus { +- marvell,pins = "mpp12"; +- marvell,function = "gpio"; +- }; +- pmx_fan_high: pmx-fan-high { +- marvell,pins = "mpp16"; +- marvell,function = "gpio"; +- }; +- pmx_fan_low: pmx-fan-low { +- marvell,pins = "mpp17"; +- marvell,function = "gpio"; +- }; +- pmx_led_alarm: pmx-led-alarm { +- marvell,pins = "mpp36"; +- marvell,function = "gpio"; +- }; +- pmx_led_function_red: pmx-led-function-red { +- marvell,pins = "mpp37"; +- marvell,function = "gpio"; +- }; +- pmx_led_info: pmx-led-info { +- marvell,pins = "mpp38"; +- marvell,function = "gpio"; +- }; +- pmx_led_function_blue: pmx-led-function-blue { +- marvell,pins = "mpp39"; +- marvell,function = "gpio"; +- }; +- pmx_led_power: pmx-led-power { +- marvell,pins = "mpp40"; +- marvell,function = "gpio"; +- }; +- pmx_fan_lock: pmx-fan-lock { +- marvell,pins = "mpp43"; +- marvell,function = "gpio"; +- }; +- pmx_button_function: pmx-button-function { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- pmx_power_switch: pmx-power-switch { +- marvell,pins = "mpp46"; +- marvell,function = "gpio"; +- }; +- pmx_power_auto_switch: pmx-power-auto-switch { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- }; +- }; +- +- gpio_keys { +- function-button { +- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; +- }; +- +- power-on-switch { +- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- }; +- +- power-auto-switch { +- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio_leds { +- red-alarm-led { +- label = "linkstation:red:alarm"; +- gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; +- }; +- +- red-function-led { +- label = "linkstation:red:function"; +- gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- }; +- +- amber-info-led { +- label = "linkstation:amber:info"; +- gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; +- }; +- +- blue-function-led { +- label = "linkstation:blue:function"; +- gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- }; +- +- blue-power-led { +- label = "linkstation:blue:power"; +- gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- }; +- +- gpio_fan { +- compatible = "gpio-fan"; +- pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; +- pinctrl-names = "default"; +- +- gpios = <&gpio0 17 GPIO_ACTIVE_LOW +- &gpio0 16 GPIO_ACTIVE_LOW>; +- +- gpio-fan,speed-map = <0 3 +- 1500 2 +- 3250 1 +- 5000 0>; +- +- alarm-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; +- }; +- +- regulators { +- usb_power: regulator@1 { +- gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; +- }; +- +- hdd_power0: regulator@2 { +- gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- device_type = "ethernet-phy"; +- reg = <0>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-duo-6281.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-duo-6281.dtsi +deleted file mode 100644 +index ba629e02ba31..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-duo-6281.dtsi ++++ /dev/null +@@ -1,149 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree common file for kirkwood-6281 based 2-Bay Buffalo Linkstation +- * +- * Copyright (C) 2015, 2016 +- * Roger Shimizu +- */ +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +-#include "kirkwood-linkstation.dtsi" +- +-/ { +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_power_hdd0: pmx-power-hdd0 { +- marvell,pins = "mpp28"; +- marvell,function = "gpio"; +- }; +- pmx_power_hdd1: pmx-power-hdd1 { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- pmx_usb_vbus: pmx-usb-vbus { +- marvell,pins = "mpp37"; +- marvell,function = "gpio"; +- }; +- pmx_led_alarm: pmx-led-alarm { +- marvell,pins = "mpp49"; +- marvell,function = "gpio"; +- }; +- pmx_led_function_red: pmx-led-function-red { +- marvell,pins = "mpp34"; +- marvell,function = "gpio"; +- }; +- pmx_led_function_blue: pmx-led-function-blue { +- marvell,pins = "mpp36"; +- marvell,function = "gpio"; +- }; +- pmx_led_info: pmx-led-info { +- marvell,pins = "mpp38"; +- marvell,function = "gpio"; +- }; +- pmx_led_power: pmx-led-power { +- marvell,pins = "mpp39"; +- marvell,function = "gpio"; +- }; +- pmx_button_function: pmx-button-function { +- marvell,pins = "mpp41"; +- marvell,function = "gpio"; +- }; +- pmx_power_switch: pmx-power-switch { +- marvell,pins = "mpp42"; +- marvell,function = "gpio"; +- }; +- pmx_power_auto_switch: pmx-power-auto-switch { +- marvell,pins = "mpp43"; +- marvell,function = "gpio"; +- }; +- }; +- +- sata@80000 { +- nr-ports = <2>; +- }; +- }; +- +- gpio_keys { +- function-button { +- gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- }; +- +- power-on-switch { +- gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; +- }; +- +- power-auto-switch { +- gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio_leds { +- red-alarm-led { +- label = "linkstation:red:alarm"; +- gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +- }; +- +- red-function-led { +- label = "linkstation:red:function"; +- gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- }; +- +- amber-info-led { +- label = "linkstation:amber:info"; +- gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; +- }; +- +- blue-function-led { +- label = "linkstation:blue:function"; +- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- }; +- +- blue-power-led { +- label = "linkstation:blue:power"; +- gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; +- }; +- }; +- +- regulators { +- pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>; +- +- usb_power: regulator@1 { +- gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- }; +- +- hdd_power0: regulator@2 { +- gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>; +- }; +- +- hdd_power1: regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- regulator-name = "HDD1 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy1: ethernet-phy@8 { +- device_type = "ethernet-phy"; +- reg = <8>; +- }; +-}; +- +-ð1 { +- status = "okay"; +- +- ethernet1-port@0 { +- phy-handle = <ðphy1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-lsqvl.dts b/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-lsqvl.dts +deleted file mode 100644 +index 8bb381088910..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-lsqvl.dts ++++ /dev/null +@@ -1,98 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Buffalo Linkstation LS-QVL +- * +- * Copyright (C) 2016, Mario Lange +- * +- * Based on kirkwood-linkstation-lswvl.dts, +- * Copyright (C) 2015, 2016 +- * Roger Shimizu +- */ +- +-/dts-v1/; +-#include "kirkwood-linkstation-6282.dtsi" +- +-/ { +- model = "Buffalo Linkstation LS-QVL"; +- compatible = "buffalo,lsqvl", "marvell,kirkwood-88f6282", "marvell,kirkwood"; +- +- memory { /* 256 MB */ +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_power_hdd1: pmx-power-hdd1 { +- marvell,pins = "mpp9"; +- marvell,function = "gpio"; +- }; +- pmx_led_hdderr0: pmx-led-hdderr0 { +- marvell,pins = "mpp34"; +- marvell,function = "gpio"; +- }; +- pmx_led_hdderr1: pmx-led-hdderr1 { +- marvell,pins = "mpp35"; +- marvell,function = "gpio"; +- }; +- pmx_led_hdderr2: pmx-led-hdderr2 { +- marvell,pins = "mpp24"; +- marvell,function = "gpio"; +- }; +- pmx_led_hdderr3: pmx-led-hdderr3 { +- marvell,pins = "mpp25"; +- marvell,function = "gpio"; +- }; +- }; +- +- sata@80000 { +- nr-ports = <2>; +- }; +- }; +- +- gpio_leds { +- pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm +- &pmx_led_info &pmx_led_power +- &pmx_led_function_blue +- &pmx_led_hdderr0 +- &pmx_led_hdderr1 +- &pmx_led_hdderr2 +- &pmx_led_hdderr3>; +- +- red-hdderr0-led { +- label = "linkstation:red:hdderr0"; +- gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; +- }; +- +- red-hdderr1-led { +- label = "linkstation:red:hdderr1"; +- gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; +- }; +- +- red-hdderr2-led { +- label = "linkstation:red:hdderr2"; +- gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; +- }; +- +- red-hdderr3-led { +- label = "linkstation:red:hdderr3"; +- gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- regulators { +- pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>; +- +- hdd_power1: regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- regulator-name = "HDD1 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-lsvl.dts b/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-lsvl.dts +deleted file mode 100644 +index 3f2a0bfe03ed..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-lsvl.dts ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Buffalo Linkstation LS-VL +- * +- * Copyright (C) 2015, 2016 +- * Roger Shimizu +- */ +- +-/dts-v1/; +-#include "kirkwood-linkstation-6282.dtsi" +- +-/ { +- model = "Buffalo Linkstation LS-VL"; +- compatible = "buffalo,lsvl", "marvell,kirkwood-88f6282", "marvell,kirkwood"; +- +- memory { /* 256 MB */ +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-lswsxl.dts b/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-lswsxl.dts +deleted file mode 100644 +index c42d0da38fe7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-lswsxl.dts ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Buffalo Linkstation LS-WSXL +- * +- * Copyright (C) 2015, 2016 +- * Roger Shimizu +- */ +- +-/dts-v1/; +-#include "kirkwood-linkstation-duo-6281.dtsi" +- +-/ { +- model = "Buffalo Linkstation LS-WSXL"; +- compatible = "buffalo,lswsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { /* 128 MB */ +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-lswvl.dts b/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-lswvl.dts +deleted file mode 100644 +index e0f62adc0d5d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-lswvl.dts ++++ /dev/null +@@ -1,75 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Buffalo Linkstation LS-WVL +- * +- * Copyright (C) 2015, 2016 +- * Roger Shimizu +- */ +- +-/dts-v1/; +-#include "kirkwood-linkstation-6282.dtsi" +- +-/ { +- model = "Buffalo Linkstation LS-WVL"; +- compatible = "buffalo,lswvl","marvell,kirkwood-88f6282", "marvell,kirkwood"; +- +- memory { /* 256 MB */ +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_power_hdd1: pmx-power-hdd1 { +- marvell,pins = "mpp9"; +- marvell,function = "gpio"; +- }; +- pmx_led_hdderr0: pmx-led-hdderr0 { +- marvell,pins = "mpp34"; +- marvell,function = "gpio"; +- }; +- pmx_led_hdderr1: pmx-led-hdderr1 { +- marvell,pins = "mpp35"; +- marvell,function = "gpio"; +- }; +- }; +- +- sata@80000 { +- nr-ports = <2>; +- }; +- }; +- +- gpio_leds { +- pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm +- &pmx_led_info &pmx_led_power +- &pmx_led_function_blue +- &pmx_led_hdderr0 +- &pmx_led_hdderr1>; +- +- red-hdderr0-led { +- label = "linkstation:red:hdderr0"; +- gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- }; +- +- red-hdderr1-led { +- label = "linkstation:red:hdderr1"; +- gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- regulators { +- pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>; +- +- hdd_power1: regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- regulator-name = "HDD1 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-lswxl.dts b/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-lswxl.dts +deleted file mode 100644 +index c6024b569423..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-linkstation-lswxl.dts ++++ /dev/null +@@ -1,79 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Buffalo Linkstation LS-WXL +- * +- * Copyright (C) 2015, 2016 +- * Roger Shimizu +- */ +- +-/dts-v1/; +-#include "kirkwood-linkstation-duo-6281.dtsi" +- +-/ { +- model = "Buffalo Linkstation LS-WXL"; +- compatible = "buffalo,lswxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { /* 128 MB */ +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_led_hdderr0: pmx-led-hdderr0 { +- marvell,pins = "mpp8"; +- marvell,function = "gpio"; +- }; +- pmx_led_hdderr1: pmx-led-hdderr1 { +- marvell,pins = "mpp46"; +- marvell,function = "gpio"; +- }; +- pmx_fan_lock: pmx-fan-lock { +- marvell,pins = "mpp40"; +- marvell,function = "gpio"; +- }; +- pmx_fan_high: pmx-fan-high { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- pmx_fan_low: pmx-fan-low { +- marvell,pins = "mpp48"; +- marvell,function = "gpio"; +- }; +- }; +- }; +- +- gpio_leds { +- pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm +- &pmx_led_info &pmx_led_power +- &pmx_led_function_blue +- &pmx_led_hdderr0 +- &pmx_led_hdderr1>; +- +- red-hdderr0-led { +- label = "linkstation:red:hdderr0"; +- gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; +- }; +- +- red-hdderr1-led { +- label = "linkstation:red:hdderr1"; +- gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio_fan { +- compatible = "gpio-fan"; +- pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; +- pinctrl-names = "default"; +- +- gpios = <&gpio1 16 GPIO_ACTIVE_LOW +- &gpio1 15 GPIO_ACTIVE_LOW>; +- +- gpio-fan,speed-map = <0 3 +- 1500 2 +- 3250 1 +- 5000 0>; +- +- alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-linkstation.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-linkstation.dtsi +deleted file mode 100644 +index 407d6d8b3a7f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-linkstation.dtsi ++++ /dev/null +@@ -1,164 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree common file for kirkwood based Buffalo Linkstation +- * +- * Copyright (C) 2015, 2016 +- * Roger Shimizu +- */ +- +-/ { +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_power_hdd0: pmx-power-hdd0 { +- marvell,function = "gpio"; +- }; +- pmx_usb_vbus: pmx-usb-vbus { +- marvell,function = "gpio"; +- }; +- pmx_led_alarm: pmx-led-alarm { +- marvell,function = "gpio"; +- }; +- pmx_led_function_red: pmx-led-function-red { +- marvell,function = "gpio"; +- }; +- pmx_led_function_blue: pmx-led-function-blue { +- marvell,function = "gpio"; +- }; +- pmx_led_info: pmx-led-info { +- marvell,function = "gpio"; +- }; +- pmx_led_power: pmx-led-power { +- marvell,function = "gpio"; +- }; +- pmx_button_function: pmx-button-function { +- marvell,function = "gpio"; +- }; +- pmx_power_switch: pmx-power-switch { +- marvell,function = "gpio"; +- }; +- pmx_power_auto_switch: pmx-power-auto-switch { +- marvell,function = "gpio"; +- }; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- sata@80000 { +- status = "okay"; +- nr-ports = <1>; +- }; +- +- spi@10600 { +- status = "okay"; +- +- m25p40@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p40", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <25000000>; +- mode = <0>; +- +- partition@0 { +- reg = <0x0 0x60000>; +- label = "uboot"; +- read-only; +- }; +- +- partition@60000 { +- reg = <0x60000 0x10000>; +- label = "dtb"; +- read-only; +- }; +- +- partition@70000 { +- reg = <0x70000 0x10000>; +- label = "uboot_env"; +- }; +- }; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_button_function &pmx_power_switch +- &pmx_power_auto_switch>; +- pinctrl-names = "default"; +- +- function-button { +- label = "Function Button"; +- linux,code = ; +- }; +- +- power-on-switch { +- label = "Power-on Switch"; +- linux,code = ; +- linux,input-type = <5>; +- }; +- +- power-auto-switch { +- label = "Power-auto Switch"; +- linux,code = ; +- linux,input-type = <5>; +- }; +- }; +- +- gpio_leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm +- &pmx_led_info &pmx_led_power +- &pmx_led_function_blue>; +- pinctrl-names = "default"; +- }; +- +- restart_poweroff { +- compatible = "restart-poweroff"; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_power_hdd0 &pmx_usb_vbus>; +- pinctrl-names = "default"; +- +- usb_power: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "USB Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- hdd_power0: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "HDD0 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-linksys-viper.dts b/scripts/dtc/include-prefixes/arm/kirkwood-linksys-viper.dts +deleted file mode 100644 +index 2f9660f3b457..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-linksys-viper.dts ++++ /dev/null +@@ -1,240 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * kirkwood-viper.dts - Device Tree file for Linksys viper (E4200v2 / EA4500) +- * +- * (c) 2013 Jonas Gorski +- * (c) 2013 Deutsche Telekom Innovation Laboratories +- * (c) 2014 Luka Perkov +- * (c) 2014 Randy C. Will +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6282.dtsi" +- +-/ { +- model = "Linksys Viper (E4200v2 / EA4500)"; +- compatible = "linksys,viper", "marvell,kirkwood-88f6282", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >; +- pinctrl-names = "default"; +- +- wps { +- label = "WPS Button"; +- linux,code = ; +- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +- }; +- +- reset { +- label = "Reset Button"; +- linux,code = ; +- gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >; +- pinctrl-names = "default"; +- +- white-health { +- label = "viper:white:health"; +- gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; +- }; +- +- white-pulse { +- label = "viper:white:pulse"; +- gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&pinctrl { +- pmx_led_white_health: pmx-led-white-health { +- marvell,pins = "mpp7"; +- marvell,function = "gpo"; +- }; +- pmx_led_white_pulse: pmx-led-white-pulse { +- marvell,pins = "mpp14"; +- marvell,function = "gpio"; +- }; +- pmx_btn_wps: pmx-btn-wps { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- pmx_btn_reset: pmx-btn-reset { +- marvell,pins = "mpp48"; +- marvell,function = "gpio"; +- }; +-}; +- +-&nand { +- status = "okay"; +- pinctrl-0 = <&pmx_nand>; +- pinctrl-names = "default"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0 0x80000>; +- read-only; +- }; +- +- partition@80000 { +- label = "u_env"; +- reg = <0x80000 0x20000>; +- }; +- +- partition@a0000 { +- label = "s_env"; +- reg = <0xA0000 0x20000>; +- }; +- +- partition@200000 { +- label = "kernel"; +- reg = <0x200000 0x2A0000>; +- }; +- +- partition@4a0000 { +- label = "rootfs"; +- reg = <0x4A0000 0x1760000>; +- }; +- +- partition@1c00000 { +- label = "alt_kernel"; +- reg = <0x1C00000 0x2A0000>; +- }; +- +- partition@1ea0000 { +- label = "alt_rootfs"; +- reg = <0x1EA0000 0x1760000>; +- }; +- +- partition@3600000 { +- label = "syscfg"; +- reg = <0x3600000 0x4A00000>; +- }; +- +- partition@c0000 { +- label = "unused"; +- reg = <0xC0000 0x140000>; +- }; +- +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +- +-&mdio { +- status = "okay"; +- +- switch@10 { +- compatible = "marvell,mv88e6085"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <16>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "ethernet1"; +- }; +- +- port@1 { +- reg = <1>; +- label = "ethernet2"; +- }; +- +- port@2 { +- reg = <2>; +- label = "ethernet3"; +- }; +- +- port@3 { +- reg = <3>; +- label = "ethernet4"; +- }; +- +- port@4 { +- reg = <4>; +- label = "internet"; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <ð0port>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set +- * fixed speed and duplex. +- */ +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- speed = <1000>; +- duplex = <1>; +- }; +-}; +- +-/* eth1 is connected to the switch at port 6. However DSA only supports a +- * single CPU port. So leave this port disabled to avoid confusion. +- */ +-ð1 { +- status = "disabled"; +-}; +- +-/* There is no battery on the board, so the RTC does not keep +- * time when there is no power, making it useless. +- */ +-&rtc { +- status = "disabled"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-lschlv2.dts b/scripts/dtc/include-prefixes/arm/kirkwood-lschlv2.dts +deleted file mode 100644 +index 1d737d903f5f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-lschlv2.dts ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood-lsxl.dtsi" +- +-/ { +- model = "Buffalo Linkstation LS-CHLv2"; +- compatible = "buffalo,lschlv2", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x4000000>; +- }; +- +- ocp@f1000000 { +- serial@12000 { +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-lsxhl.dts b/scripts/dtc/include-prefixes/arm/kirkwood-lsxhl.dts +deleted file mode 100644 +index a56e0d797778..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-lsxhl.dts ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood-lsxl.dtsi" +- +-/ { +- model = "Buffalo Linkstation LS-XHL"; +- compatible = "buffalo,lsxhl", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- ocp@f1000000 { +- serial@12000 { +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-lsxl.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-lsxl.dtsi +deleted file mode 100644 +index 7b151acb9984..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-lsxl.dtsi ++++ /dev/null +@@ -1,237 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_power_hdd: pmx-power-hdd { +- marvell,pins = "mpp10"; +- marvell,function = "gpo"; +- }; +- pmx_usb_vbus: pmx-usb-vbus { +- marvell,pins = "mpp11"; +- marvell,function = "gpio"; +- }; +- pmx_fan_high: pmx-fan-high { +- marvell,pins = "mpp18"; +- marvell,function = "gpo"; +- }; +- pmx_fan_low: pmx-fan-low { +- marvell,pins = "mpp19"; +- marvell,function = "gpo"; +- }; +- pmx_led_function_blue: pmx-led-function-blue { +- marvell,pins = "mpp36"; +- marvell,function = "gpio"; +- }; +- pmx_led_alarm: pmx-led-alarm { +- marvell,pins = "mpp37"; +- marvell,function = "gpio"; +- }; +- pmx_led_info: pmx-led-info { +- marvell,pins = "mpp38"; +- marvell,function = "gpio"; +- }; +- pmx_led_power: pmx-led-power { +- marvell,pins = "mpp39"; +- marvell,function = "gpio"; +- }; +- pmx_fan_lock: pmx-fan-lock { +- marvell,pins = "mpp40"; +- marvell,function = "gpio"; +- }; +- pmx_button_function: pmx-button-function { +- marvell,pins = "mpp41"; +- marvell,function = "gpio"; +- }; +- pmx_power_switch: pmx-power-switch { +- marvell,pins = "mpp42"; +- marvell,function = "gpio"; +- }; +- pmx_power_auto_switch: pmx-power-auto-switch { +- marvell,pins = "mpp43"; +- marvell,function = "gpio"; +- }; +- pmx_led_function_red: pmx-led-function_red { +- marvell,pins = "mpp48"; +- marvell,function = "gpio"; +- }; +- +- }; +- sata@80000 { +- status = "okay"; +- nr-ports = <1>; +- }; +- +- spi@10600 { +- status = "okay"; +- +- m25p40@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p40", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <25000000>; +- mode = <0>; +- +- partition@0 { +- reg = <0x0 0x60000>; +- label = "uboot"; +- read-only; +- }; +- +- partition@60000 { +- reg = <0x60000 0x10000>; +- label = "dtb"; +- read-only; +- }; +- +- partition@70000 { +- reg = <0x70000 0x10000>; +- label = "uboot_env"; +- }; +- }; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_button_function &pmx_power_switch +- &pmx_power_auto_switch>; +- pinctrl-names = "default"; +- +- option { +- label = "Function Button"; +- linux,code = ; +- gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- }; +- reserved { +- label = "Power-on Switch"; +- linux,code = ; +- linux,input-type = <5>; +- gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; +- }; +- power { +- label = "Power-auto Switch"; +- linux,code = ; +- linux,input-type = <5>; +- gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio_leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm +- &pmx_led_info &pmx_led_power +- &pmx_led_function_blue>; +- pinctrl-names = "default"; +- +- func_blue { +- label = "lsxl:blue:func"; +- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- }; +- +- alarm { +- label = "lsxl:red:alarm"; +- gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +- }; +- +- info { +- label = "lsxl:amber:info"; +- gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; +- }; +- +- power { +- label = "lsxl:blue:power"; +- gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- +- func_red { +- label = "lsxl:red:func"; +- gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio_fan { +- compatible = "gpio-fan"; +- pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; +- pinctrl-names = "default"; +- gpios = <&gpio0 19 GPIO_ACTIVE_LOW +- &gpio0 18 GPIO_ACTIVE_LOW>; +- gpio-fan,speed-map = <0 3 +- 1500 2 +- 3250 1 +- 5000 0>; +- alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- }; +- +- restart_poweroff { +- compatible = "restart-poweroff"; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_power_hdd &pmx_usb_vbus>; +- pinctrl-names = "default"; +- +- usb_power: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "USB Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 11 0>; +- }; +- hdd_power: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "HDD Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 10 0>; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@8 { +- reg = <8>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- +-ð1 { +- status = "okay"; +- ethernet1-port@0 { +- phy-handle = <ðphy1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-mplcec4.dts b/scripts/dtc/include-prefixes/arm/kirkwood-mplcec4.dts +deleted file mode 100644 +index b80d12f6aa49..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-mplcec4.dts ++++ /dev/null +@@ -1,216 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- model = "MPL CEC4"; +- compatible = "mpl,cec4-10", "mpl,cec4", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_led_health: pmx-led-health { +- marvell,pins = "mpp7"; +- marvell,function = "gpo"; +- }; +- +- pmx_sata1: pmx-sata1 { +- marvell,pins = "mpp34"; +- marvell,function = "sata1"; +- }; +- +- pmx_sata0: pmx-sata0 { +- marvell,pins = "mpp35"; +- marvell,function = "sata0"; +- }; +- +- pmx_led_user1o: pmx-led-user1o { +- marvell,pins = "mpp40"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_user1g: pmx-led-user1g { +- marvell,pins = "mpp41"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_user0o: pmx-led-user0o { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_user0g: pmx-led-user0g { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_misc: pmx-led-misc { +- marvell,pins = "mpp46"; +- marvell,function = "gpio"; +- }; +- +- pmx_sdio_cd: pmx-sdio-cd { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- }; +- +- i2c@11000 { +- status = "okay"; +- +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- +- eeprom@57 { +- compatible = "atmel,24c02"; +- reg = <0x57>; +- }; +- +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- rtc@10300 { +- status = "disabled"; +- }; +- +- sata@80000 { +- pinctrl-0 = <&pmx_sata0 &pmx_sata1>; +- pinctrl-names = "default"; +- nr-ports = <2>; +- status = "okay"; +- }; +- +- mvsdio@90000 { +- pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; +- pinctrl-names = "default"; +- status = "okay"; +- cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +- /* No WP GPIO */ +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = < &pmx_led_health +- &pmx_led_user1o +- &pmx_led_user1g &pmx_led_user0o +- &pmx_led_user0g &pmx_led_misc +- >; +- pinctrl-names = "default"; +- +- health { +- label = "status:green:health"; +- gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; +- }; +- +- user1o { +- label = "user1:orange"; +- gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- +- user1g { +- label = "user1:green"; +- gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- +- user0o { +- label = "user0:orange"; +- gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- +- user0g { +- label = "user0:green"; +- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- +- misc { +- label = "status:orange:misc"; +- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- +- }; +-}; +- +-&nand { +- status = "okay"; +- +- partition@0 { +- label = "uboot"; +- reg = <0x0000000 0x100000>; +- }; +- +- partition@100000 { +- label = "env"; +- reg = <0x100000 0x80000>; +- }; +- +- partition@180000 { +- label = "fdt"; +- reg = <0x180000 0x80000>; +- }; +- +- partition@200000 { +- label = "kernel"; +- reg = <0x200000 0x400000>; +- }; +- +- partition@600000 { +- label = "rootfs"; +- reg = <0x600000 0x1fa00000>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@1 { +- reg = <1>; +- }; +- +- ethphy1: ethernet-phy@2 { +- reg = <2>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- +-ð1 { +- status = "okay"; +- ethernet1-port@0 { +- phy-handle = <ðphy1>; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-mv88f6281gtw-ge.dts b/scripts/dtc/include-prefixes/arm/kirkwood-mv88f6281gtw-ge.dts +deleted file mode 100644 +index 2e1a75348908..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-mv88f6281gtw-ge.dts ++++ /dev/null +@@ -1,178 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Marvell 88F6281 GTW GE Board +- * +- * Lennert Buytenhek +- * Thomas Petazzoni +- * +- * This file contains the definitions that are common between the 6281 +- * and 6282 variants of the Marvell Kirkwood Development Board. +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- model = "Marvell 88F6281 GTW GE Board"; +- compatible = "marvell,mv88f6281gtw-ge", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; /* 512 MB */ +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pin-controller@10000 { +- pmx_usb_led: pmx-usb-led { +- marvell,pins = "mpp12"; +- marvell,function = "gpo"; +- }; +- +- pmx_leds: pmx-leds { +- marvell,pins = "mpp20", "mpp21"; +- marvell,function = "gpio"; +- }; +- +- pmx_keys: pmx-keys { +- marvell,pins = "mpp46", "mpp47"; +- marvell,function = "gpio"; +- }; +- }; +- +- spi@10600 { +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- mode = <0>; +- }; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- ehci@50000 { +- status = "okay"; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_leds &pmx_usb_led>; +- pinctrl-names = "default"; +- +- green-status { +- label = "gtw:green:Status"; +- gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; +- }; +- +- red-status { +- label = "gtw:red:Status"; +- gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; +- }; +- +- green-usb { +- label = "gtw:green:USB"; +- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_keys>; +- pinctrl-names = "default"; +- +- restart { +- label = "SWR Button"; +- linux,code = ; +- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +- }; +- wps { +- label = "WPS Button"; +- linux,code = ; +- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- switch@0 { +- compatible = "marvell,mv88e6085"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan1"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan2"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan3"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan4"; +- }; +- +- port@4 { +- reg = <4>; +- label = "wan"; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <ð0port>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; +-}; +- +-ð0 { +- status = "okay"; +- +- ethernet0-port@0 { +- speed = <1000>; +- duplex = <1>; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-nas2big.dts b/scripts/dtc/include-prefixes/arm/kirkwood-nas2big.dts +deleted file mode 100644 +index 6a2934b7d0ce..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-nas2big.dts ++++ /dev/null +@@ -1,139 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree file for LaCie 2Big NAS +- * +- * Copyright (C) 2015 Seagate +- * +- * Author: Simon Guinot +- * +-*/ +- +-/dts-v1/; +- +-#include "kirkwood-netxbig.dtsi" +- +-/ { +- model = "LaCie 2Big NAS"; +- compatible = "lacie,nas2big", "lacie,netxbig", "marvell,kirkwood-88f6282", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- rtc@10300 { +- /* The on-chip RTC is not powered (no supercap). */ +- status = "disabled"; +- }; +- spi@10600 { +- /* +- * A NAND flash is used instead of an SPI flash for +- * the other netxbig-compatible boards. +- */ +- status = "disabled"; +- }; +- }; +- +- fan { +- /* +- * An I2C fan controller (GMT G762) is used but alarm is +- * wired to a separate GPIO. +- */ +- compatible = "gpio-fan"; +- alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; +- }; +- +- regulators: regulators { +- status = "okay"; +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- +- regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "hdd1power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; +- }; +- clocks { +- g762_clk: g762-oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- /* +- * An external I2C RTC (Dallas DS1337S+) is used. This allows +- * to power-up the board on an RTC alarm. The external RTC can +- * be kept powered, even when the SoC is off. +- */ +- rtc@68 { +- compatible = "dallas,ds1307"; +- reg = <0x68>; +- interrupts = <43>; +- }; +- g762@3e { +- compatible = "gmt,g762"; +- reg = <0x3e>; +- clocks = <&g762_clk>; +- }; +-}; +- +-&nand { +- chip-delay = <50>; +- status = "okay"; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0x0 0x100000>; +- }; +- +- partition@100000 { +- label = "uImage"; +- reg = <0x100000 0x1000000>; +- }; +- +- partition@1100000 { +- label = "root"; +- reg = <0x1100000 0x8000000>; +- }; +- +- partition@9100000 { +- label = "unused"; +- reg = <0x9100000 0x6f00000>; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-net2big.dts b/scripts/dtc/include-prefixes/arm/kirkwood-net2big.dts +deleted file mode 100644 +index 3e3ac289e5b0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-net2big.dts ++++ /dev/null +@@ -1,63 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree file for LaCie 2Big Network v2 +- * +- * Copyright (C) 2014 +- * +- * Andrew Lunn +- * +- * Based on netxbig_v2-setup.c, +- * Copyright (C) 2010 Simon Guinot +- * +-*/ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +-#include "kirkwood-netxbig.dtsi" +- +-/ { +- model = "LaCie 2Big Network v2"; +- compatible = "lacie,net2big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- fan { +- compatible = "gpio-fan"; +- alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-®ulators { +- regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "hdd1power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; +- }; +- +- clocks { +- g762_clk: g762-oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- }; +-}; +- +-&i2c0 { +- g762@3e { +- compatible = "gmt,g762"; +- reg = <0x3e>; +- clocks = <&g762_clk>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-net5big.dts b/scripts/dtc/include-prefixes/arm/kirkwood-net5big.dts +deleted file mode 100644 +index cba8a2b6f6d9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-net5big.dts ++++ /dev/null +@@ -1,169 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree file for LaCie 5Big Network v2 +- * +- * Copyright (C) 2014 +- * +- * Andrew Lunn +- * +- * Based on netxbig_v2-setup.c, +- * Copyright (C) 2010 Simon Guinot +- * +-*/ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +-#include "kirkwood-netxbig.dtsi" +- +-/ { +- model = "LaCie 5Big Network v2"; +- compatible = "lacie,net5big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; +- }; +- +-}; +- +-®ulators { +- regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "hdd1power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; +- }; +- +- regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- regulator-name = "hdd2power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- }; +- +- regulator@4 { +- compatible = "regulator-fixed"; +- reg = <4>; +- regulator-name = "hdd3power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; +- }; +- +- regulator@5 { +- compatible = "regulator-fixed"; +- reg = <5>; +- regulator-name = "hdd4power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; +- }; +- +- clocks { +- g762_clk: g762-oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- }; +- +- netxbig-leds { +- blue-sata2 { +- label = "netxbig:blue:sata2"; +- mode-addr = <5>; +- mode-val = ; +- bright-addr = <2>; +- max-brightness = <7>; +- }; +- red-sata2 { +- label = "netxbig:red:sata2"; +- mode-addr = <5>; +- mode-val = ; +- bright-addr = <2>; +- max-brightness = <7>; +- }; +- blue-sata3 { +- label = "netxbig:blue:sata3"; +- mode-addr = <6>; +- mode-val = ; +- bright-addr = <2>; +- max-brightness = <7>; +- }; +- red-sata3 { +- label = "netxbig:red:sata3"; +- mode-addr = <6>; +- mode-val = ; +- bright-addr = <2>; +- max-brightness = <7>; +- }; +- blue-sata4 { +- label = "netxbig:blue:sata4"; +- mode-addr = <7>; +- mode-val = ; +- bright-addr = <2>; +- max-brightness = <7>; +- }; +- red-sata4 { +- label = "netxbig:red:sata4"; +- mode-addr = <7>; +- mode-val = ; +- bright-addr = <2>; +- max-brightness = <7>; +- }; +- }; +-}; +- +-&mdio { +- ethphy1: ethernet-phy@1 { +- reg = <0>; +- }; +-}; +- +-ð1 { +- status = "okay"; +- ethernet1-port@0 { +- phy-handle = <ðphy1>; +- }; +-}; +- +- +-&i2c0 { +- g762@3e { +- compatible = "gmt,g762"; +- reg = <0x3e>; +- clocks = <&g762_clk>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-netgear_readynas_duo_v2.dts b/scripts/dtc/include-prefixes/arm/kirkwood-netgear_readynas_duo_v2.dts +deleted file mode 100644 +index cb564c3bcdc4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-netgear_readynas_duo_v2.dts ++++ /dev/null +@@ -1,247 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Device Tree file for NETGEAR ReadyNAS Duo v2 +- * +- * Copyright (C) 2013, Arnaud EBALARD +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6282.dtsi" +- +-/ { +- model = "NETGEAR ReadyNAS Duo v2"; +- compatible = "netgear,readynas-duo-v2", "netgear,readynas", "marvell,kirkwood-88f6282", "marvell,kirkwood"; +- +- memory { /* 256 MB */ +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_button_power: pmx-button-power { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- +- pmx_button_backup: pmx-button-backup { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- +- pmx_button_reset: pmx-button-reset { +- marvell,pins = "mpp13"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_blue_power: pmx-led-blue-power { +- marvell,pins = "mpp31"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_blue_activity: pmx-led-blue-activity { +- marvell,pins = "mpp38"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_blue_disk1: pmx-led-blue-disk1 { +- marvell,pins = "mpp23"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_blue_disk2: pmx-led-blue-disk2 { +- marvell,pins = "mpp22"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_blue_backup: pmx-led-blue-backup { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- +- pmx_poweroff: pmx-poweroff { +- marvell,pins = "mpp30"; +- marvell,function = "gpio"; +- }; +- }; +- +- clocks { +- g762_clk: g762-oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <8192>; +- }; +- }; +- +- i2c@11000 { +- status = "okay"; +- +- rs5c372a: rs5c372a@32 { +- compatible = "ricoh,rs5c372a"; +- reg = <0x32>; +- }; +- +- g762: g762@3e { +- compatible = "gmt,g762"; +- reg = <0x3e>; +- clocks = <&g762_clk>; /* input clock */ +- fan_gear_mode = <0>; +- fan_startv = <1>; +- pwm_polarity = <0>; +- }; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- sata@80000 { +- status = "okay"; +- nr-ports = <2>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_activity +- &pmx_led_blue_disk1 &pmx_led_blue_disk2 +- &pmx_led_blue_backup >; +- pinctrl-names = "default"; +- +- power_led { +- label = "status:blue:power_led"; +- gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- +- activity_led { +- label = "status:blue:activity_led"; +- gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; +- }; +- +- disk1_led { +- label = "status:blue:disk1_led"; +- gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; +- }; +- +- disk2_led { +- label = "status:blue:disk2_led"; +- gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; +- }; +- +- backup_led { +- label = "status:blue:backup_led"; +- gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&pmx_button_power &pmx_button_backup +- &pmx_button_reset>; +- pinctrl-names = "default"; +- +- power-button { +- label = "Power Button"; +- linux,code = ; +- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +- }; +- +- reset-button { +- label = "Reset Button"; +- linux,code = ; +- gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; +- }; +- +- backup-button { +- label = "Backup Button"; +- linux,code = ; +- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- pinctrl-0 = <&pmx_poweroff>; +- pinctrl-names = "default"; +- gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- usb3_regulator: usb3-regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "USB 3.0 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&nand { +- status = "okay"; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x180000>; +- read-only; +- }; +- +- partition@180000 { +- label = "u-boot-env"; +- reg = <0x180000 0x20000>; +- }; +- +- partition@200000 { +- label = "uImage"; +- reg = <0x0200000 0x600000>; +- }; +- +- partition@800000 { +- label = "minirootfs"; +- reg = <0x0800000 0x1000000>; +- }; +- +- partition@1800000 { +- label = "jffs2"; +- reg = <0x1800000 0x6800000>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ +- reg = <0>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-netgear_readynas_nv+_v2.dts b/scripts/dtc/include-prefixes/arm/kirkwood-netgear_readynas_nv+_v2.dts +deleted file mode 100644 +index b13aee570804..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-netgear_readynas_nv+_v2.dts ++++ /dev/null +@@ -1,274 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Device Tree file for NETGEAR ReadyNAS NV+ v2 +- * +- * Copyright (C) 2013, Arnaud EBALARD +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6282.dtsi" +- +-/ { +- model = "NETGEAR ReadyNAS NV+ v2"; +- compatible = "netgear,readynas-nv+-v2", "netgear,readynas", "marvell,kirkwood-88f6282", "marvell,kirkwood"; +- +- memory { /* 256 MB */ +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_button_power: pmx-button-power { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- +- pmx_button_backup: pmx-button-backup { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- +- pmx_button_reset: pmx-button-reset { +- marvell,pins = "mpp13"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_blue_power: pmx-led-blue-power { +- marvell,pins = "mpp31"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_blue_backup: pmx-led-blue-backup { +- marvell,pins = "mpp22"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_blue_disk1: pmx-led-blue-disk1 { +- marvell,pins = "mpp20"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_blue_disk2: pmx-led-blue-disk2 { +- marvell,pins = "mpp23"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_blue_disk3: pmx-led-blue-disk3 { +- marvell,pins = "mpp24"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_blue_disk4: pmx-led-blue-disk4 { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- +- pmx_poweroff: pmx-poweroff { +- marvell,pins = "mpp30"; +- marvell,function = "gpio"; +- }; +- }; +- +- clocks { +- g762_clk: g762-oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <8192>; +- }; +- }; +- +- i2c@11000 { +- status = "okay"; +- +- rs5c372a: rs5c372a@32 { +- compatible = "ricoh,rs5c372a"; +- reg = <0x32>; +- }; +- +- g762: g762@3e { +- compatible = "gmt,g762"; +- reg = <0x3e>; +- clocks = <&g762_clk>; /* input clock */ +- fan_gear_mode = <0>; +- fan_startv = <1>; +- pwm_polarity = <0>; +- }; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- sata@80000 { /* Connected to Marvell 88SM4140 SATA port multiplier */ +- status = "okay"; +- nr-ports = <1>; +- }; +- }; +- +- auxdisplay { +- compatible = "hit,hd44780"; +- data-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>, +- <&gpio1 1 GPIO_ACTIVE_HIGH>, +- <&gpio1 3 GPIO_ACTIVE_HIGH>, +- <&gpio1 17 GPIO_ACTIVE_HIGH>; +- enable-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; +- rs-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; +- rw-gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; +- backlight-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; +- display-height-chars = <2>; +- display-width-chars = <16>; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_backup +- &pmx_led_blue_disk1 &pmx_led_blue_disk2 +- &pmx_led_blue_disk3 &pmx_led_blue_disk3 >; +- pinctrl-names = "default"; +- +- power_led { +- label = "status:blue:power_led"; +- gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- backup_led { +- label = "status:blue:backup_led"; +- gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; +- }; +- +- disk1_led { +- label = "status:blue:disk1_led"; +- gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; +- }; +- +- disk2_led { +- label = "status:blue:disk2_led"; +- gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; +- }; +- +- disk3_led { +- label = "status:blue:disk3_led"; +- gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; +- }; +- +- disk4_led { +- label = "status:blue:disk4_led"; +- gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&pmx_button_power &pmx_button_backup +- &pmx_button_reset>; +- pinctrl-names = "default"; +- +- power-button { +- label = "Power Button"; +- linux,code = ; +- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +- }; +- +- reset-button { +- label = "Reset Button"; +- linux,code = ; +- gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; +- }; +- +- backup-button { +- label = "Backup Button"; +- linux,code = ; +- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- pinctrl-0 = <&pmx_poweroff>; +- pinctrl-names = "default"; +- gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- usb3_regulator: usb3-regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "USB 3.0 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&nand { +- status = "okay"; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x180000>; +- read-only; +- }; +- +- partition@180000 { +- label = "u-boot-env"; +- reg = <0x180000 0x20000>; +- }; +- +- partition@200000 { +- label = "uImage"; +- reg = <0x0200000 0x600000>; +- }; +- +- partition@800000 { +- label = "minirootfs"; +- reg = <0x0800000 0x1000000>; +- }; +- +- partition@1800000 { +- label = "jffs2"; +- reg = <0x1800000 0x6800000>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ +- device_type = "ethernet-phy"; +- reg = <0>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- +-/* Connected to NEC uPD720200 USB 3.0 controller */ +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-netxbig.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-netxbig.dtsi +deleted file mode 100644 +index b5737026e244..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-netxbig.dtsi ++++ /dev/null +@@ -1,232 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree common file for LaCie 2Big and 5Big Network v2 +- * +- * Copyright (C) 2014 +- * +- * Andrew Lunn +- * +- * Based on netxbig_v2-setup.c, +- * Copyright (C) 2010 Simon Guinot +- * +-*/ +- +-#include +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- serial@12000 { +- status = "okay"; +- }; +- +- spi@10600 { +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- mode = <0>; +- +- partition@0 { +- reg = <0x0 0x80000>; +- label = "u-boot"; +- }; +- }; +- }; +- +- sata@80000 { +- status = "okay"; +- nr-ports = <2>; +- }; +- +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* +- * esc and power represent a three position rocker +- * switch. Thus the conventional KEY_POWER does not fit +- */ +- exc { +- label = "Back power switch (on|auto)"; +- linux,code = ; +- linux,input-type = <5>; +- gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; +- }; +- power { +- label = "Back power switch (auto|off)"; +- linux,code = ; +- linux,input-type = <5>; +- gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; +- }; +- option { +- label = "Function button"; +- linux,code = ; +- gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; +- }; +- +- }; +- +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; +- }; +- +- regulators: regulators { +- status = "okay"; +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- +- regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "hdd0power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- netxbig_gpio_ext: netxbig-gpio-ext { +- compatible = "lacie,netxbig-gpio-ext"; +- +- addr-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH +- &gpio1 16 GPIO_ACTIVE_HIGH +- &gpio1 17 GPIO_ACTIVE_HIGH>; +- data-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH +- &gpio1 13 GPIO_ACTIVE_HIGH +- &gpio1 14 GPIO_ACTIVE_HIGH>; +- enable-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; +- }; +- +- netxbig-leds { +- compatible = "lacie,netxbig-leds"; +- +- gpio-ext = <&netxbig_gpio_ext>; +- +- timers = ; +- +- blue-power { +- label = "netxbig:blue:power"; +- mode-addr = <0>; +- mode-val = ; +- bright-addr = <1>; +- max-brightness = <7>; +- }; +- red-power { +- label = "netxbig:red:power"; +- mode-addr = <0>; +- mode-val = ; +- bright-addr = <1>; +- max-brightness = <7>; +- }; +- blue-sata0 { +- label = "netxbig:blue:sata0"; +- mode-addr = <3>; +- mode-val = ; +- bright-addr = <2>; +- max-brightness = <7>; +- }; +- red-sata0 { +- label = "netxbig:red:sata0"; +- mode-addr = <3>; +- mode-val = ; +- bright-addr = <2>; +- max-brightness = <7>; +- }; +- blue-sata1 { +- label = "netxbig:blue:sata1"; +- mode-addr = <4>; +- mode-val = ; +- bright-addr = <2>; +- max-brightness = <7>; +- }; +- red-sata1 { +- label = "netxbig:red:sata1"; +- mode-addr = <4>; +- mode-val = ; +- bright-addr = <2>; +- max-brightness = <7>; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- reg = <8>; +- }; +- +- ethphy1: ethernet-phy@1 { +- reg = <0>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- +- pmx_button_function: pmx-button-function { +- marvell,pins = "mpp34"; +- marvell,function = "gpio"; +- }; +- pmx_button_power_off: pmx-button-power-off { +- marvell,pins = "mpp15"; +- marvell,function = "gpio"; +- }; +- pmx_button_power_on: pmx-button-power-on { +- marvell,pins = "mpp13"; +- marvell,function = "gpio"; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c04"; +- pagesize = <16>; +- reg = <0x50>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ns2-common.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-ns2-common.dtsi +deleted file mode 100644 +index 51530ea86622..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ns2-common.dtsi ++++ /dev/null +@@ -1,97 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_ns2_sata0: pmx-ns2-sata0 { +- marvell,pins = "mpp21"; +- marvell,function = "sata0"; +- }; +- pmx_ns2_sata1: pmx-ns2-sata1 { +- marvell,pins = "mpp20"; +- marvell,function = "sata1"; +- }; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- spi@10600 { +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- mode = <0>; +- +- partition@0 { +- reg = <0x0 0x80000>; +- label = "u-boot"; +- }; +- }; +- }; +- +- i2c@11000 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c04"; +- pagesize = <16>; +- reg = <0x50>; +- }; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- power { +- label = "Power push button"; +- linux,code = ; +- gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- red-fail { +- label = "ns2:red:fail"; +- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio_poweroff { +- compatible = "gpio-poweroff"; +- gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; +- }; +- +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@X { +- /* overwrite reg property in board file */ +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ns2.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ns2.dts +deleted file mode 100644 +index 7b67083e1ec0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ns2.dts ++++ /dev/null +@@ -1,40 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include "kirkwood-ns2-common.dtsi" +- +-/ { +- model = "LaCie Network Space v2"; +- compatible = "lacie,netspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- ocp@f1000000 { +- sata@80000 { +- pinctrl-0 = <&pmx_ns2_sata0>; +- pinctrl-names = "default"; +- status = "okay"; +- nr-ports = <1>; +- }; +- }; +- +- ns2-leds { +- compatible = "lacie,ns2-leds"; +- +- blue-sata { +- label = "ns2:blue:sata"; +- slow-gpio = <&gpio0 29 0>; +- cmd-gpio = <&gpio0 30 0>; +- modes-map = ; +- }; +- }; +-}; +- +-ðphy0 { reg = <8>; }; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ns2lite.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ns2lite.dts +deleted file mode 100644 +index b0cb5907ed63..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ns2lite.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood-ns2-common.dtsi" +- +-/ { +- model = "LaCie Network Space Lite v2"; +- compatible = "lacie,netspace_lite_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- ocp@f1000000 { +- sata@80000 { +- pinctrl-0 = <&pmx_ns2_sata0>; +- pinctrl-names = "default"; +- status = "okay"; +- nr-ports = <1>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- blue-sata { +- label = "ns2:blue:sata"; +- gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "disk-activity"; +- }; +- }; +-}; +- +-ðphy0 { reg = <0>; }; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ns2max.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ns2max.dts +deleted file mode 100644 +index c0a087e77408..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ns2max.dts ++++ /dev/null +@@ -1,59 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include "kirkwood-ns2-common.dtsi" +- +-/ { +- model = "LaCie Network Space Max v2"; +- compatible = "lacie,netspace_max_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- ocp@f1000000 { +- sata@80000 { +- pinctrl-0 = <&pmx_ns2_sata0 &pmx_ns2_sata1>; +- pinctrl-names = "default"; +- status = "okay"; +- nr-ports = <2>; +- }; +- }; +- +- gpio_fan { +- compatible = "gpio-fan"; +- gpios = <&gpio0 22 GPIO_ACTIVE_LOW +- &gpio0 7 GPIO_ACTIVE_LOW +- &gpio1 1 GPIO_ACTIVE_LOW +- &gpio0 23 GPIO_ACTIVE_LOW>; +- gpio-fan,speed-map = +- < 0 0 +- 1500 15 +- 1700 14 +- 1800 13 +- 2100 12 +- 3100 11 +- 3300 10 +- 4300 9 +- 5500 8>; +- alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; +- }; +- +- ns2-leds { +- compatible = "lacie,ns2-leds"; +- +- blue-sata { +- label = "ns2:blue:sata"; +- slow-gpio = <&gpio0 29 0>; +- cmd-gpio = <&gpio0 30 0>; +- modes-map = ; +- }; +- }; +-}; +- +-ðphy0 { reg = <8>; }; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ns2mini.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ns2mini.dts +deleted file mode 100644 +index 5b9fa14b6428..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ns2mini.dts ++++ /dev/null +@@ -1,60 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include "kirkwood-ns2-common.dtsi" +- +-/ { +- /* This machine is embedded in the first LaCie CloudBox product. */ +- model = "LaCie Network Space Mini v2"; +- compatible = "lacie,netspace_mini_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- ocp@f1000000 { +- sata@80000 { +- pinctrl-0 = <&pmx_ns2_sata0>; +- pinctrl-names = "default"; +- status = "okay"; +- nr-ports = <1>; +- }; +- }; +- +- gpio_fan { +- compatible = "gpio-fan"; +- gpios = <&gpio0 22 GPIO_ACTIVE_LOW +- &gpio0 7 GPIO_ACTIVE_LOW +- &gpio1 1 GPIO_ACTIVE_LOW +- &gpio0 23 GPIO_ACTIVE_LOW>; +- gpio-fan,speed-map = +- < 0 0 +- 3000 15 +- 3180 14 +- 4140 13 +- 4570 12 +- 6760 11 +- 7140 10 +- 7980 9 +- 9200 8>; +- alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; +- }; +- +- ns2-leds { +- compatible = "lacie,ns2-leds"; +- +- blue-sata { +- label = "ns2:blue:sata"; +- slow-gpio = <&gpio0 29 0>; +- cmd-gpio = <&gpio0 30 0>; +- modes-map = ; +- }; +- }; +-}; +- +-ðphy0 { reg = <0>; }; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-nsa310.dts b/scripts/dtc/include-prefixes/arm/kirkwood-nsa310.dts +deleted file mode 100644 +index 9b861c2e76c5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-nsa310.dts ++++ /dev/null +@@ -1,139 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood-nsa3x0-common.dtsi" +- +-/ { +- compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pinctrl-0 = <&pmx_unknown>; +- pinctrl-names = "default"; +- +- pmx_led_esata_green: pmx-led-esata-green { +- marvell,pins = "mpp12"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_esata_red: pmx-led-esata-red { +- marvell,pins = "mpp13"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_usb_green: pmx-led-usb-green { +- marvell,pins = "mpp15"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_usb_red: pmx-led-usb-red { +- marvell,pins = "mpp16"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_sys_green: pmx-led-sys-green { +- marvell,pins = "mpp28"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_sys_red: pmx-led-sys-red { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_hdd_green: pmx-led-hdd-green { +- marvell,pins = "mpp41"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_hdd_red: pmx-led-hdd-red { +- marvell,pins = "mpp42"; +- marvell,function = "gpio"; +- }; +- +- pmx_unknown: pmx-unknown { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- +- }; +- +- i2c@11000 { +- status = "okay"; +- +- adt7476: adt7476a@2e { +- compatible = "adi,adt7476"; +- reg = <0x2e>; +- }; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_led_esata_green &pmx_led_esata_red +- &pmx_led_usb_green &pmx_led_usb_red +- &pmx_led_sys_green &pmx_led_sys_red +- &pmx_led_copy_green &pmx_led_copy_red +- &pmx_led_hdd_green &pmx_led_hdd_red>; +- pinctrl-names = "default"; +- +- green-sys { +- label = "nsa310:green:sys"; +- gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; +- }; +- red-sys { +- label = "nsa310:red:sys"; +- gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; +- }; +- green-hdd { +- label = "nsa310:green:hdd"; +- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- }; +- red-hdd { +- label = "nsa310:red:hdd"; +- gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; +- }; +- green-esata { +- label = "nsa310:green:esata"; +- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; +- }; +- red-esata { +- label = "nsa310:red:esata"; +- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; +- }; +- green-usb { +- label = "nsa310:green:usb"; +- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; +- }; +- red-usb { +- label = "nsa310:red:usb"; +- gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; +- }; +- green-copy { +- label = "nsa310:green:copy"; +- gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- }; +- red-copy { +- label = "nsa310:red:copy"; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-nsa310a.dts b/scripts/dtc/include-prefixes/arm/kirkwood-nsa310a.dts +deleted file mode 100644 +index b85e314f045a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-nsa310a.dts ++++ /dev/null +@@ -1,115 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood-nsa3x0-common.dtsi" +- +-/* +- * There are at least two different NSA310 designs. This variant does +- * not have the red USB Led. +- */ +- +-/ { +- compatible = "zyxel,nsa310a", "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pinctrl-names = "default"; +- +- pmx_led_esata_green: pmx-led-esata-green { +- marvell,pins = "mpp12"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_esata_red: pmx-led-esata-red { +- marvell,pins = "mpp13"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_usb_green: pmx-led-usb-green { +- marvell,pins = "mpp15"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_sys_green: pmx-led-sys-green { +- marvell,pins = "mpp28"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_sys_red: pmx-led-sys-red { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_hdd_green: pmx-led-hdd-green { +- marvell,pins = "mpp41"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_hdd_red: pmx-led-hdd-red { +- marvell,pins = "mpp42"; +- marvell,function = "gpio"; +- }; +- +- }; +- +- i2c@11000 { +- status = "okay"; +- +- lm85: lm85@2e { +- compatible = "national,lm85"; +- reg = <0x2e>; +- }; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- green-sys { +- label = "nsa310:green:sys"; +- gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; +- }; +- red-sys { +- label = "nsa310:red:sys"; +- gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; +- }; +- green-hdd { +- label = "nsa310:green:hdd"; +- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- }; +- red-hdd { +- label = "nsa310:red:hdd"; +- gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; +- }; +- green-esata { +- label = "nsa310:green:esata"; +- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; +- }; +- red-esata { +- label = "nsa310:red:esata"; +- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; +- }; +- green-usb { +- label = "nsa310:green:usb"; +- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; +- }; +- green-copy { +- label = "nsa310:green:copy"; +- gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- }; +- red-copy { +- label = "nsa310:red:copy"; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-nsa320.dts b/scripts/dtc/include-prefixes/arm/kirkwood-nsa320.dts +deleted file mode 100644 +index b69b096f267b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-nsa320.dts ++++ /dev/null +@@ -1,219 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* Device tree file for the Zyxel NSA 320 NAS box. +- * +- * Copyright (c) 2014, Adam Baker +- * +- * +- * Based upon the board setup file created by Peter Schildmann */ +- +-/dts-v1/; +- +-#include "kirkwood-nsa3x0-common.dtsi" +- +-/ { +- model = "Zyxel NSA320"; +- compatible = "zyxel,nsa320", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pinctrl-names = "default"; +- +- /* SATA Activity and Present pins are not connected */ +- pmx_sata0: pmx-sata0 { +- marvell,pins ; +- marvell,function = "sata0"; +- }; +- +- pmx_sata1: pmx-sata1 { +- marvell,pins ; +- marvell,function = "sata1"; +- }; +- +- pmx_led_hdd2_green: pmx-led-hdd2-green { +- marvell,pins = "mpp12"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_hdd2_red: pmx-led-hdd2-red { +- marvell,pins = "mpp13"; +- marvell,function = "gpio"; +- }; +- +- pmx_mcu_data: pmx-mcu-data { +- marvell,pins = "mpp14"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_usb_green: pmx-led-usb-green { +- marvell,pins = "mpp15"; +- marvell,function = "gpio"; +- }; +- +- pmx_mcu_clk: pmx-mcu-clk { +- marvell,pins = "mpp16"; +- marvell,function = "gpio"; +- }; +- +- pmx_mcu_act: pmx-mcu-act { +- marvell,pins = "mpp17"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_sys_green: pmx-led-sys-green { +- marvell,pins = "mpp28"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_sys_orange: pmx-led-sys-orange { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_hdd1_green: pmx-led-hdd1-green { +- marvell,pins = "mpp41"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_hdd1_red: pmx-led-hdd1-red { +- marvell,pins = "mpp42"; +- marvell,function = "gpio"; +- }; +- +- pmx_htp: pmx-htp { +- marvell,pins = "mpp43"; +- marvell,function = "gpio"; +- }; +- +- /* Buzzer needs to be switched at around 1kHz so is +- not compatible with the gpio-beeper driver. */ +- pmx_buzzer: pmx-buzzer { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- +- pmx_vid_b1: pmx-vid-b1 { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- +- pmx_power_resume_data: pmx-power-resume-data { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- +- pmx_power_resume_clk: pmx-power-resume-clk { +- marvell,pins = "mpp49"; +- marvell,function = "gpio"; +- }; +- }; +- +- i2c@11000 { +- status = "okay"; +- +- pcf8563: pcf8563@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- }; +- }; +- +- regulators { +- usb0_power: regulator@1 { +- enable-active-high; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red +- &pmx_led_usb_green +- &pmx_led_sys_green &pmx_led_sys_orange +- &pmx_led_copy_green &pmx_led_copy_red +- &pmx_led_hdd1_green &pmx_led_hdd1_red>; +- pinctrl-names = "default"; +- +- green-sys { +- label = "nsa320:green:sys"; +- gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; +- }; +- orange-sys { +- label = "nsa320:orange:sys"; +- gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; +- }; +- green-hdd1 { +- label = "nsa320:green:hdd1"; +- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- }; +- red-hdd1 { +- label = "nsa320:red:hdd1"; +- gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; +- }; +- green-hdd2 { +- label = "nsa320:green:hdd2"; +- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; +- }; +- red-hdd2 { +- label = "nsa320:red:hdd2"; +- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; +- }; +- green-usb { +- label = "nsa320:green:usb"; +- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; +- }; +- green-copy { +- label = "nsa320:green:copy"; +- gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- }; +- red-copy { +- label = "nsa320:red:copy"; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- hwmon { +- compatible = "zyxel,nsa320-mcu"; +- pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act>; +- pinctrl-names = "default"; +- +- data-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; +- clk-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; +- act-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; +- }; +- +- /* The following pins are currently not assigned to a driver, +- some of them should be configured as inputs. +- pinctrl-0 = <&pmx_htp &pmx_vid_b1 +- &pmx_power_resume_data &pmx_power_resume_clk>; */ +-}; +- +-&mdio { +- status = "okay"; +- ethphy0: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-nsa325.dts b/scripts/dtc/include-prefixes/arm/kirkwood-nsa325.dts +deleted file mode 100644 +index 6f8085dbb1f4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-nsa325.dts ++++ /dev/null +@@ -1,232 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* Device tree file for the Zyxel NSA 325 NAS box. +- * +- * Copyright (c) 2015, Hans Ulli Kroll +- * +- * +- * Based upon the board setup file created by Peter Schildmann +- */ +- +-/dts-v1/; +- +-#include "kirkwood-nsa3x0-common.dtsi" +- +-/ { +- model = "ZyXEL NSA325"; +- compatible = "zyxel,nsa325", "marvell,kirkwood-88f6282", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pinctrl-names = "default"; +- +- pmx_led_hdd2_green: pmx-led-hdd2-green { +- marvell,pins = "mpp12"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_hdd2_red: pmx-led-hdd2-red { +- marvell,pins = "mpp13"; +- marvell,function = "gpio"; +- }; +- +- pmx_mcu_data: pmx-mcu-data { +- marvell,pins = "mpp14"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_usb_green: pmx-led-usb-green { +- marvell,pins = "mpp15"; +- marvell,function = "gpio"; +- }; +- +- pmx_mcu_clk: pmx-mcu-clk { +- marvell,pins = "mpp16"; +- marvell,function = "gpio"; +- }; +- +- pmx_mcu_act: pmx-mcu-act { +- marvell,pins = "mpp17"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_sys_green: pmx-led-sys-green { +- marvell,pins = "mpp28"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_sys_orange: pmx-led-sys-orange { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_hdd1_green: pmx-led-hdd1-green { +- marvell,pins = "mpp41"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_hdd1_red: pmx-led-hdd1-red { +- marvell,pins = "mpp42"; +- marvell,function = "gpio"; +- }; +- +- pmx_htp: pmx-htp { +- marvell,pins = "mpp43"; +- marvell,function = "gpio"; +- }; +- +- /* +- * Buzzer needs to be switched at around 1kHz so is +- * not compatible with the gpio-beeper driver. +- */ +- pmx_buzzer: pmx-buzzer { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- +- pmx_vid_b1: pmx-vid-b1 { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- +- pmx_power_resume_data: pmx-power-resume-data { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- +- pmx_power_resume_clk: pmx-power-resume-clk { +- marvell,pins = "mpp49"; +- marvell,function = "gpio"; +- }; +- +- pmx_pwr_sata1: pmx-pwr-sata1 { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- }; +- +- /* This board uses the pcf8563 RTC instead of the SoC RTC */ +- rtc@10300 { +- status = "disabled"; +- }; +- +- i2c@11000 { +- status = "okay"; +- +- pcf8563: pcf8563@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_pwr_sata1>; +- pinctrl-names = "default"; +- +- usb0_power: regulator@1 { +- enable-active-high; +- }; +- +- sata1_power: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "SATA1 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red +- &pmx_led_usb_green +- &pmx_led_sys_green &pmx_led_sys_orange +- &pmx_led_copy_green &pmx_led_copy_red +- &pmx_led_hdd1_green &pmx_led_hdd1_red>; +- pinctrl-names = "default"; +- +- green-sys { +- label = "nsa325:green:sys"; +- gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; +- }; +- orange-sys { +- label = "nsa325:orange:sys"; +- gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; +- }; +- green-hdd1 { +- label = "nsa325:green:hdd1"; +- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; +- }; +- red-hdd1 { +- label = "nsa325:red:hdd1"; +- gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; +- }; +- green-hdd2 { +- label = "nsa325:green:hdd2"; +- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; +- }; +- red-hdd2 { +- label = "nsa325:red:hdd2"; +- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; +- }; +- green-usb { +- label = "nsa325:green:usb"; +- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; +- }; +- green-copy { +- label = "nsa325:green:copy"; +- gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- }; +- red-copy { +- label = "nsa325:red:copy"; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- }; +- +- /* The following pins are currently not assigned to a driver, +- some of them should be configured as inputs. +- pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act +- &pmx_htp &pmx_vid_b1 +- &pmx_power_resume_data &pmx_power_resume_clk>; */ +- }; +- +- +-}; +- +-&mdio { +- status = "okay"; +- ethphy0: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-nsa3x0-common.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-nsa3x0-common.dtsi +deleted file mode 100644 +index 8f73197f251a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-nsa3x0-common.dtsi ++++ /dev/null +@@ -1,158 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- model = "ZyXEL NSA310"; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- +- pmx_usb_power: pmx-usb-power { +- marvell,pins = "mpp21"; +- marvell,function = "gpio"; +- }; +- +- pmx_pwr_off: pmx-pwr-off { +- marvell,pins = "mpp48"; +- marvell,function = "gpio"; +- }; +- +- pmx_btn_reset: pmx-btn-reset { +- marvell,pins = "mpp36"; +- marvell,function = "gpio"; +- }; +- +- pmx_btn_copy: pmx-btn-copy { +- marvell,pins = "mpp37"; +- marvell,function = "gpio"; +- }; +- +- pmx_btn_power: pmx-btn-power { +- marvell,pins = "mpp46"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_copy_green: pmx-led-copy-green { +- marvell,pins = "mpp39"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_copy_red: pmx-led-copy-red { +- marvell,pins = "mpp40"; +- marvell,function = "gpio"; +- }; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- sata@80000 { +- status = "okay"; +- nr-ports = <2>; +- }; +- }; +- +- gpio_poweroff { +- compatible = "gpio-poweroff"; +- pinctrl-0 = <&pmx_pwr_off>; +- pinctrl-names = "default"; +- gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; +- pinctrl-names = "default"; +- +- power { +- label = "Power Button"; +- linux,code = ; +- gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; +- }; +- copy { +- label = "Copy Button"; +- linux,code = ; +- gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +- }; +- reset { +- label = "Reset Button"; +- linux,code = ; +- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_usb_power>; +- pinctrl-names = "default"; +- +- usb0_power: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "USB Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&nand { +- status = "okay"; +- chip-delay = <35>; +- +- partition@0 { +- label = "uboot"; +- reg = <0x0000000 0x0100000>; +- read-only; +- }; +- partition@100000 { +- label = "uboot_env"; +- reg = <0x0100000 0x0080000>; +- }; +- partition@180000 { +- label = "key_store"; +- reg = <0x0180000 0x0080000>; +- }; +- partition@200000 { +- label = "info"; +- reg = <0x0200000 0x0080000>; +- }; +- partition@280000 { +- label = "etc"; +- reg = <0x0280000 0x0a00000>; +- }; +- partition@c80000 { +- label = "kernel_1"; +- reg = <0x0c80000 0x0a00000>; +- }; +- partition@1680000 { +- label = "rootfs1"; +- reg = <0x1680000 0x2fc0000>; +- }; +- partition@4640000 { +- label = "kernel_2"; +- reg = <0x4640000 0x0a00000>; +- }; +- partition@5040000 { +- label = "rootfs2"; +- reg = <0x5040000 0x2fc0000>; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-openblocks_a6.dts b/scripts/dtc/include-prefixes/arm/kirkwood-openblocks_a6.dts +deleted file mode 100644 +index 8ea430168ea5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-openblocks_a6.dts ++++ /dev/null +@@ -1,184 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6282.dtsi" +- +-/ { +- model = "Plat'Home OpenBlocksA6"; +- compatible = "plathome,openblocks-a6", "marvell,kirkwood-88f6283", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- serial@12000 { +- status = "okay"; +- }; +- +- serial@12100 { +- status = "okay"; +- }; +- +- sata@80000 { +- nr-ports = <1>; +- status = "okay"; +- }; +- +- i2c@11100 { +- status = "okay"; +- +- s35390a: s35390a@30 { +- compatible = "sii,s35390a"; +- reg = <0x30>; +- }; +- }; +- +- pinctrl: pin-controller@10000 { +- pinctrl-0 = <&pmx_dip_switches>; +- pinctrl-names = "default"; +- +- pmx_uart0: pmx-uart0 { +- marvell,pins = "mpp10", "mpp11", "mpp15", +- "mpp16"; +- marvell,function = "uart0"; +- }; +- +- pmx_uart1: pmx-uart1 { +- marvell,pins = "mpp13", "mpp14", "mpp8", +- "mpp9"; +- marvell,function = "uart1"; +- }; +- +- pmx_sysrst: pmx-sysrst { +- marvell,pins = "mpp6"; +- marvell,function = "sysrst"; +- }; +- +- pmx_dip_switches: pmx-dip-switches { +- marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_header: pmx-gpio-header { +- marvell,pins = "mpp24", "mpp25", "mpp26", "mpp27", +- "mpp28", "mpp29", "mpp30", "mpp31"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_init: pmx-init { +- marvell,pins = "mpp38"; +- marvell,function = "gpio"; +- }; +- +- pmx_usb_oc: pmx-usb-oc { +- marvell,pins = "mpp39"; +- marvell,function = "gpio"; +- }; +- +- pmx_leds: pmx-leds { +- marvell,pins = "mpp41", "mpp42", "mpp43"; +- marvell,function = "gpio"; +- }; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_leds>; +- pinctrl-names = "default"; +- +- led-red { +- label = "obsa6:red:stat"; +- gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- }; +- +- led-green { +- label = "obsa6:green:stat"; +- gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; +- }; +- +- led-yellow { +- label = "obsa6:yellow:stat"; +- gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&pmx_gpio_init>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- power { +- label = "Init Button"; +- linux,code = ; +- gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&nand { +- chip-delay = <25>; +- status = "okay"; +- +- partition@0 { +- label = "uboot"; +- reg = <0x0 0x90000>; +- }; +- +- partition@90000 { +- label = "env"; +- reg = <0x90000 0x44000>; +- }; +- +- partition@d4000 { +- label = "test"; +- reg = <0xd4000 0x20000>; +- }; +- +- partition@f4000 { +- label = "conf"; +- reg = <0xf4000 0x400000>; +- }; +- +- partition@4f4000 { +- label = "linux"; +- reg = <0x4f4000 0x1d20000>; +- }; +- +- partition@2214000 { +- label = "user"; +- reg = <0x2214000 0x1dec000>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- +-&gpio0 { +- status = "okay"; +- +- pinctrl-0 = <&pmx_gpio_header>; +- pinctrl-names = "default"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-openblocks_a7.dts b/scripts/dtc/include-prefixes/arm/kirkwood-openblocks_a7.dts +deleted file mode 100644 +index 946f0f453dd1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-openblocks_a7.dts ++++ /dev/null +@@ -1,209 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree file for OpenBlocks A7 board +- * +- * Copyright (C) 2013 Free Electrons +- * +- * Thomas Petazzoni +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6282.dtsi" +- +-/ { +- model = "Plat'Home OpenBlocksA7"; +- compatible = "plathome,openblocks-a7", "marvell,kirkwood-88f6283", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x40000000>; /* 1 GB */ +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- serial@12000 { +- status = "okay"; +- }; +- +- serial@12100 { +- status = "okay"; +- }; +- +- sata@80000 { +- nr-ports = <1>; +- status = "okay"; +- }; +- +- i2c@11100 { +- status = "okay"; +- +- s24c02: s24c02@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- }; +- }; +- +- pinctrl: pin-controller@10000 { +- pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header +- &pmx_gpio_header_gpo>; +- pinctrl-names = "default"; +- +- pmx_uart0: pmx-uart0 { +- marvell,pins = "mpp10", "mpp11", "mpp15", +- "mpp16"; +- marvell,function = "uart0"; +- }; +- +- pmx_uart1: pmx-uart1 { +- marvell,pins = "mpp13", "mpp14", "mpp8", +- "mpp9"; +- marvell,function = "uart1"; +- }; +- +- pmx_sysrst: pmx-sysrst { +- marvell,pins = "mpp6"; +- marvell,function = "sysrst"; +- }; +- +- pmx_dip_switches: pmx-dip-switches { +- marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47"; +- marvell,function = "gpio"; +- }; +- +- /* +- * Accessible on connector J202. The MPP +- * listed below are pin 1-7, pin 8 is unused, +- * pin 9 is external reset input and pin 10 is +- * ground. +- */ +- pmx_gpio_header: pmx-gpio-header { +- marvell,pins = "mpp17", "mpp29", "mpp28", +- "mpp35", "mpp34", "mpp40"; +- marvell,function = "gpio"; +- }; +- +- pmx_gpio_header_gpo: pxm-gpio-header-gpo { +- marvell,pins = "mpp7"; +- marvell,function = "gpo"; +- }; +- +- pmx_gpio_init: pmx-init { +- marvell,pins = "mpp38"; +- marvell,function = "gpio"; +- }; +- +- pmx_usb_oc: pmx-usb-oc { +- marvell,pins = "mpp39"; +- marvell,function = "gpio"; +- }; +- +- pmx_leds: pmx-leds { +- marvell,pins = "mpp41", "mpp42", "mpp43"; +- marvell,function = "gpio"; +- }; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_leds>; +- pinctrl-names = "default"; +- +- led-red { +- label = "obsa7:red:stat"; +- gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- }; +- +- led-green { +- label = "obsa7:green:stat"; +- gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; +- }; +- +- led-yellow { +- label = "obsa7:yellow:stat"; +- gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&pmx_gpio_init>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- button { +- label = "Init Button"; +- linux,code = ; +- gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&nand { +- chip-delay = <25>; +- status = "okay"; +- +- partition@0 { +- label = "uboot"; +- reg = <0x0 0x1c0000>; +- }; +- +- partition@1c0000 { +- label = "env"; +- reg = <0x1c0000 0x2c0000>; +- }; +- +- partition@480000 { +- label = "test"; +- reg = <0x480000 0x160000>; +- }; +- +- partition@5e0000 { +- label = "conf"; +- reg = <0x5e0000 0x540000>; +- }; +- +- partition@b20000 { +- label = "linux"; +- reg = <0xb20000 0x3d40000>; +- }; +- +- partition@4860000 { +- label = "user"; +- reg = <0x4860000 0xb7a0000>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- +-ð1 { +- status = "okay"; +- ethernet1-port@0 { +- phy-handle = <ðphy1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-openrd-base.dts b/scripts/dtc/include-prefixes/arm/kirkwood-openrd-base.dts +deleted file mode 100644 +index 094191ece3d7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-openrd-base.dts ++++ /dev/null +@@ -1,39 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Marvell OpenRD Base Board Description +- * +- * Andrew Lunn +- * +- * This file contains the definitions that are specific to OpenRD +- * base variant of the Marvell Kirkwood Development Board. +- */ +- +-/dts-v1/; +- +-#include "kirkwood-openrd.dtsi" +- +-/ { +- model = "OpenRD Base"; +- compatible = "marvell,openrd-base", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- ocp@f1000000 { +- serial@12100 { +- status = "okay"; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@8 { +- reg = <8>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-openrd-client.dts b/scripts/dtc/include-prefixes/arm/kirkwood-openrd-client.dts +deleted file mode 100644 +index d4e0b8150a84..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-openrd-client.dts ++++ /dev/null +@@ -1,74 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Marvell OpenRD Client Board Description +- * +- * Andrew Lunn +- * +- * This file contains the definitions that are specific to OpenRD +- * client variant of the Marvell Kirkwood Development Board. +- */ +- +-/dts-v1/; +- +-#include "kirkwood-openrd.dtsi" +- +-/ { +- model = "OpenRD Client"; +- compatible = "marvell,openrd-client", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- ocp@f1000000 { +- audio-controller@a0000 { +- status = "okay"; +- }; +- i2c@11000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- cs42l51: cs42l51@4a { +- compatible = "cirrus,cs42l51"; +- reg = <0x4a>; +- #sound-dai-cells = <0>; +- }; +- }; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,mclk-fs = <256>; +- +- simple-audio-card,cpu { +- sound-dai = <&audio0 0>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&cs42l51>; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@8 { +- reg = <8>; +- }; +- ethphy1: ethernet-phy@24 { +- reg = <24>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- +-ð1 { +- status = "okay"; +- ethernet1-port@0 { +- phy-handle = <ðphy1>; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-openrd-ultimate.dts b/scripts/dtc/include-prefixes/arm/kirkwood-openrd-ultimate.dts +deleted file mode 100644 +index 888e13320c19..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-openrd-ultimate.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Marvell OpenRD Ultimate Board Description +- * +- * Andrew Lunn +- * +- * This file contains the definitions that are specific to OpenRD +- * ultimate variant of the Marvell Kirkwood Development Board. +- */ +- +-/dts-v1/; +- +-#include "kirkwood-openrd.dtsi" +- +-/ { +- model = "OpenRD Ultimate"; +- compatible = "marvell,openrd-ultimate", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- ocp@f1000000 { +- i2c@11000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- cs42l51: cs42l51@4a { +- compatible = "cirrus,cs42l51"; +- reg = <0x4a>; +- }; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- +-ð1 { +- status = "okay"; +- ethernet1-port@0 { +- phy-handle = <ðphy1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-openrd.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-openrd.dtsi +deleted file mode 100644 +index 47f03c69c55a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-openrd.dtsi ++++ /dev/null +@@ -1,122 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Marvell OpenRD (Base|Client|Ultimate) Board Description +- * +- * Andrew Lunn +- * +- * This file contains the definitions that are common between the three +- * variants of the Marvell Kirkwood Development Board. +- */ +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pinctrl-0 = <&pmx_select28 &pmx_sdio_cd &pmx_select34>; +- pinctrl-names = "default"; +- +- pmx_select28: pmx-select-rs232-rs485 { +- marvell,pins = "mpp28"; +- marvell,function = "gpio"; +- }; +- pmx_sdio_cd: pmx-sdio-cd { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- pmx_select34: pmx-select-uart-sd { +- marvell,pins = "mpp34"; +- marvell,function = "gpio"; +- }; +- }; +- serial@12000 { +- status = "okay"; +- +- }; +- sata@80000 { +- status = "okay"; +- nr-ports = <2>; +- }; +- mvsdio@90000 { +- status = "okay"; +- cd-gpios = <&gpio0 29 9>; +- }; +- gpio@10100 { +- p28 { +- gpio-hog; +- gpios = <28 GPIO_ACTIVE_HIGH>; +- /* +- * SelRS232or485 selects between RS-232 or RS-485 +- * mode for the second UART. +- * +- * Low: RS-232 +- * High: RS-485 +- * +- * To use the second UART, you need to change also +- * the SelUARTorSD. +- */ +- output-low; +- line-name = "SelRS232or485"; +- }; +- }; +- gpio@10140 { +- p2 { +- gpio-hog; +- gpios = <2 GPIO_ACTIVE_HIGH>; +- /* +- * SelUARTorSD selects between the second UART +- * (serial@12100) and SD (mvsdio@90000). +- * +- * Low: UART +- * High: SD +- * +- * When changing this line make sure the newly +- * selected device node is enabled and the +- * previously selected device node is disabled. +- */ +- output-high; /* Select SD by default */ +- line-name = "SelUARTorSD"; +- }; +- }; +- }; +-}; +- +-&nand { +- status = "okay"; +- pinctrl-0 = <&pmx_nand>; +- pinctrl-names = "default"; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x100000>; +- }; +- +- partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x400000>; +- }; +- +- partition@600000 { +- label = "root"; +- reg = <0x0600000 0x1FA00000>; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-pogo_e02.dts b/scripts/dtc/include-prefixes/arm/kirkwood-pogo_e02.dts +deleted file mode 100644 +index f9e95e55f36d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-pogo_e02.dts ++++ /dev/null +@@ -1,132 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * kirkwood-pogo_e02.dts - Device tree file for Pogoplug E02 +- * +- * Copyright (C) 2015 Christoph Junghans +- * +- * based on information of dts files from +- * Arch Linux ARM by Oleg Rakhmanov +- * OpenWrt by Felix Kaechele +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- model = "Cloud Engines Pogoplug E02"; +- compatible = "cloudengines,pogoe02", "marvell,kirkwood-88f6281", +- "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- health { +- label = "pogo_e02:green:health"; +- gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- fault { +- label = "pogo_e02:orange:fault"; +- gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_usb_power_enable>; +- pinctrl-names = "default"; +- +- usb_power: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "USB Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&pinctrl { +- pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange +- &pmx_led_green >; +- pinctrl-names = "default"; +- +- pmx_usb_power_enable: pmx-usb-power-enable { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_green: pmx-led-green { +- marvell,pins = "mpp48"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_orange: pmx-led-orange { +- marvell,pins = "mpp49"; +- marvell,function = "gpio"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&nand { +- chip-delay = <40>; +- status = "okay"; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x100000>; +- read-only; +- }; +- +- partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x400000>; +- }; +- +- partition@500000 { +- label = "pogoplug"; +- reg = <0x0500000 0x2000000>; +- }; +- +- partition@2500000 { +- label = "root"; +- reg = <0x02500000 0x5b00000>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-pogoplug-series-4.dts b/scripts/dtc/include-prefixes/arm/kirkwood-pogoplug-series-4.dts +deleted file mode 100644 +index 5aa4669ae254..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-pogoplug-series-4.dts ++++ /dev/null +@@ -1,180 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * kirkwood-pogoplug-series-4.dts - Device tree file for PogoPlug Series 4 +- * inspired by the board files made by Kevin Mihelich for ArchLinux, +- * and their DTS file. +- * +- * Copyright (C) 2015 Linus Walleij +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6192.dtsi" +-#include +- +-/ { +- model = "Cloud Engines PogoPlug Series 4"; +- compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192", +- "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +- +- chosen { +- stdout-path = "uart0:115200n8"; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_button_eject>; +- pinctrl-names = "default"; +- +- eject { +- debounce-interval = <50>; +- wakeup-source; +- linux,code = ; +- label = "Eject Button"; +- gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_led_green &pmx_led_red>; +- pinctrl-names = "default"; +- +- health { +- label = "pogoplugv4:green:health"; +- gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- fault { +- label = "pogoplugv4:red:fault"; +- gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&pinctrl { +- pmx_sata0: pmx-sata0 { +- marvell,pins = "mpp21"; +- marvell,function = "sata0"; +- }; +- +- pmx_sata1: pmx-sata1 { +- marvell,pins = "mpp20"; +- marvell,function = "sata1"; +- }; +- +- pmx_sdio_cd: pmx-sdio-cd { +- marvell,pins = "mpp27"; +- marvell,function = "gpio"; +- }; +- +- pmx_sdio_wp: pmx-sdio-wp { +- marvell,pins = "mpp28"; +- marvell,function = "gpio"; +- }; +- +- pmx_button_eject: pmx-button-eject { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_green: pmx-led-green { +- marvell,pins = "mpp22"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_red: pmx-led-red { +- marvell,pins = "mpp24"; +- marvell,function = "gpio"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-/* +- * This PCIE controller has a USB 3.0 XHCI controller at 1,0 +- */ +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +- pinctrl-0 = <&pmx_sata0 &pmx_sata1>; +- pinctrl-names = "default"; +- nr-ports = <1>; +-}; +- +-&sdio { +- status = "okay"; +- pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; +- pinctrl-names = "default"; +- cd-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; +-}; +- +-&nand { +- /* 128 MiB of NAND flash */ +- chip-delay = <40>; +- status = "okay"; +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x00000000 0x200000>; +- read-only; +- }; +- +- partition@200000 { +- label = "uImage"; +- reg = <0x00200000 0x300000>; +- }; +- +- partition@500000 { +- label = "uImage2"; +- reg = <0x00500000 0x300000>; +- }; +- +- partition@800000 { +- label = "failsafe"; +- reg = <0x00800000 0x800000>; +- }; +- +- partition@1000000 { +- label = "root"; +- reg = <0x01000000 0x7000000>; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-rd88f6192.dts b/scripts/dtc/include-prefixes/arm/kirkwood-rd88f6192.dts +deleted file mode 100644 +index 712d6042b132..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-rd88f6192.dts ++++ /dev/null +@@ -1,106 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Marvell RD88F6192 Board descrition +- * +- * Andrew Lunn +- * +- * This file contains the definitions that are common between the three +- * variants of the Marvell Kirkwood Development Board. +- */ +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6192.dtsi" +- +-/ { +- model = "Marvell RD88F6192 reference design"; +- compatible = "marvell,rd88f6192", "marvell,kirkwood-88f6192", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pinctrl-0 = <&pmx_usb_power>; +- pinctrl-names = "default"; +- +- pmx_usb_power: pmx-usb-power { +- marvell,pins = "mpp10"; +- marvell,function = "gpo"; +- }; +- }; +- +- serial@12000 { +- status = "okay"; +- +- }; +- +- spi@10600 { +- status = "okay"; +- +- m25p128@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p128", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- mode = <0>; +- }; +- }; +- +- sata@80000 { +- status = "okay"; +- nr-ports = <2>; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_usb_power>; +- pinctrl-names = "default"; +- +- usb_power: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "USB VBUS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@8 { +- reg = <8>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-rd88f6281-a.dts b/scripts/dtc/include-prefixes/arm/kirkwood-rd88f6281-a.dts +deleted file mode 100644 +index 5da163591bbf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-rd88f6281-a.dts ++++ /dev/null +@@ -1,39 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Marvell RD88F6181 A Board descrition +- * +- * Andrew Lunn +- * +- * This file contains the definitions for the board with the A0 or +- * higher stepping of the SoC. The ethernet switch does not have a +- * "wan" port. +- */ +- +-/dts-v1/; +-#include "kirkwood-rd88f6281.dtsi" +- +-/ { +- model = "Marvell RD88f6281 Reference design, with A0 or higher SoC"; +- compatible = "marvell,rd88f6281-a", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy1: ethernet-phy@11 { +- reg = <11>; +- }; +-}; +- +-&switch { +- reg = <10>; +-}; +- +-ð1 { +- status = "okay"; +- +- ethernet1-port@0 { +- phy-handle = <ðphy1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-rd88f6281-z0.dts b/scripts/dtc/include-prefixes/arm/kirkwood-rd88f6281-z0.dts +deleted file mode 100644 +index 9d88301daf0e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-rd88f6281-z0.dts ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Marvell RD88F6181 Z0 stepping descrition +- * +- * Andrew Lunn +- * +- * This file contains the definitions for the board using the Z0 +- * stepping of the SoC. The ethernet switch has a "wan" port. +-*/ +- +-/dts-v1/; +- +-#include "kirkwood-rd88f6281.dtsi" +- +-/ { +- model = "Marvell RD88f6281 Reference design, with Z0 SoC"; +- compatible = "marvell,rd88f6281-z0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +-}; +- +-ð1 { +- status = "disabled"; +-}; +- +-&switch { +- reg = <0>; +- +- ports { +- port@4 { +- reg = <4>; +- label = "wan"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-rd88f6281.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-rd88f6281.dtsi +deleted file mode 100644 +index f1f8eee132e8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-rd88f6281.dtsi ++++ /dev/null +@@ -1,134 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Marvell RD88F6181 Common Board descrition +- * +- * Andrew Lunn +- * +- * This file contains the definitions that are common between the two +- * variants of the Marvell Kirkwood Development Board. +- */ +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pinctrl-names = "default"; +- +- pmx_sdio_cd: pmx-sdio-cd { +- marvell,pins = "mpp28"; +- marvell,function = "gpio"; +- }; +- }; +- +- serial@12000 { +- status = "okay"; +- +- }; +- +- sata@80000 { +- status = "okay"; +- nr-ports = <2>; +- }; +- mvsdio@90000 { +- pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; +- pinctrl-names = "default"; +- status = "okay"; +- cd-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; +- /* No WP GPIO */ +- }; +- }; +-}; +- +-&nand { +- status = "okay"; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x100000>; +- read-only; +- }; +- +- partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x200000>; +- }; +- +- partition@300000 { +- label = "rootfs"; +- reg = <0x0300000 0x500000>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- switch: switch@0 { +- compatible = "marvell,mv88e6085"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan1"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan2"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan3"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan4"; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <ð0port>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- }; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- speed = <1000>; +- duplex = <1>; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-rs212.dts b/scripts/dtc/include-prefixes/arm/kirkwood-rs212.dts +deleted file mode 100644 +index c51cea883215..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-rs212.dts ++++ /dev/null +@@ -1,51 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Andrew Lunn +- * Ben Peddell +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6282.dtsi" +-#include "kirkwood-synology.dtsi" +- +-/ { +- model = "Synology RS212"; +- compatible = "synology,rs212", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio-fan-100-15-35-3 { +- status = "okay"; +- }; +- +- gpio-leds-hdd-38 { +- status = "okay"; +- }; +- +- regulators-hdd-30-2 { +- status = "okay"; +- }; +-}; +- +-&s35390a { +- status = "okay"; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-rs409.dts b/scripts/dtc/include-prefixes/arm/kirkwood-rs409.dts +deleted file mode 100644 +index 43673b03cb35..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-rs409.dts ++++ /dev/null +@@ -1,43 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Andrew Lunn +- * Ben Peddell +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +-#include "kirkwood-synology.dtsi" +- +-/ { +- model = "Synology RS409"; +- compatible = "synology,rs409", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio-fan-150-15-18 { +- status = "okay"; +- }; +- +- gpio-leds-hdd-36 { +- status = "okay"; +- }; +-}; +- +-ð1 { +- status = "okay"; +-}; +- +-&rs5c372 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-rs411.dts b/scripts/dtc/include-prefixes/arm/kirkwood-rs411.dts +deleted file mode 100644 +index 41fa63cec839..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-rs411.dts ++++ /dev/null +@@ -1,43 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Andrew Lunn +- * Ben Peddell +- * +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6282.dtsi" +-#include "kirkwood-synology.dtsi" +- +-/ { +- model = "Synology RS411 RS812"; +- compatible = "synology,rs411", "synology,rs812", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- gpio-fan-100-15-35-3 { +- status = "okay"; +- }; +- +- gpio-leds-hdd-36 { +- status = "okay"; +- }; +-}; +- +-ð1 { +- status = "okay"; +-}; +- +-&s35390a { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-sheevaplug-common.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-sheevaplug-common.dtsi +deleted file mode 100644 +index 0a698d3b7393..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-sheevaplug-common.dtsi ++++ /dev/null +@@ -1,104 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * kirkwood-sheevaplug-common.dtsi - Common parts for Sheevaplugs +- * +- * Copyright (C) 2013 Simon Baatz +- */ +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- +- pmx_usb_power_enable: pmx-usb-power-enable { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- pmx_led_red: pmx-led-red { +- marvell,pins = "mpp46"; +- marvell,function = "gpio"; +- }; +- pmx_led_blue: pmx-led-blue { +- marvell,pins = "mpp49"; +- marvell,function = "gpio"; +- }; +- pmx_sdio_cd: pmx-sdio-cd { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- pmx_sdio_wp: pmx-sdio-wp { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- }; +- serial@12000 { +- status = "okay"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_usb_power_enable>; +- pinctrl-names = "default"; +- +- usb_power: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "USB Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 29 0>; +- }; +- }; +-}; +- +-&nand { +- status = "okay"; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x100000>; +- }; +- +- partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x400000>; +- }; +- +- partition@500000 { +- label = "root"; +- reg = <0x0500000 0x1fb00000>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-sheevaplug-esata.dts b/scripts/dtc/include-prefixes/arm/kirkwood-sheevaplug-esata.dts +deleted file mode 100644 +index ae8f493c9a0f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-sheevaplug-esata.dts ++++ /dev/null +@@ -1,42 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * kirkwood-sheevaplug-esata.dts - Device tree file for eSATA Sheevaplug +- * +- * Copyright (C) 2013 Simon Baatz +- */ +- +-/dts-v1/; +- +-#include "kirkwood-sheevaplug-common.dtsi" +- +-/ { +- model = "Globalscale Technologies eSATA SheevaPlug"; +- compatible = "globalscale,sheevaplug-esata-rev13", "globalscale,sheevaplug-esata", "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- ocp@f1000000 { +- sata@80000 { +- status = "okay"; +- nr-ports = <2>; +- }; +- +- mvsdio@90000 { +- pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; +- pinctrl-names = "default"; +- status = "okay"; +- cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_led_blue>; +- pinctrl-names = "default"; +- +- health { +- label = "sheevaplug:blue:health"; +- gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-sheevaplug.dts b/scripts/dtc/include-prefixes/arm/kirkwood-sheevaplug.dts +deleted file mode 100644 +index c73cc904e5c4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-sheevaplug.dts ++++ /dev/null +@@ -1,42 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * kirkwood-sheevaplug.dts - Device tree file for Sheevaplug +- * +- * Copyright (C) 2013 Simon Baatz +- */ +- +-/dts-v1/; +- +-#include "kirkwood-sheevaplug-common.dtsi" +- +-/ { +- model = "Globalscale Technologies SheevaPlug"; +- compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- ocp@f1000000 { +- mvsdio@90000 { +- pinctrl-0 = <&pmx_sdio>; +- pinctrl-names = "default"; +- status = "okay"; +- /* No CD or WP GPIOs */ +- broken-cd; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_led_blue &pmx_led_red>; +- pinctrl-names = "default"; +- +- health { +- label = "sheevaplug:blue:health"; +- gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- +- misc { +- label = "sheevaplug:red:misc"; +- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-synology.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-synology.dtsi +deleted file mode 100644 +index 217bd374e52b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-synology.dtsi ++++ /dev/null +@@ -1,855 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Nodes for Marvell 628x Synology devices +- * +- * Andrew Lunn +- * Ben Peddell +- * +- */ +- +-/ { +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pmx_alarmled_12: pmx-alarmled-12 { +- marvell,pins = "mpp12"; +- marvell,function = "gpio"; +- }; +- +- pmx_fanctrl_15: pmx-fanctrl-15 { +- marvell,pins = "mpp15"; +- marvell,function = "gpio"; +- }; +- +- pmx_fanctrl_16: pmx-fanctrl-16 { +- marvell,pins = "mpp16"; +- marvell,function = "gpio"; +- }; +- +- pmx_fanctrl_17: pmx-fanctrl-17 { +- marvell,pins = "mpp17"; +- marvell,function = "gpio"; +- }; +- +- pmx_fanalarm_18: pmx-fanalarm-18 { +- marvell,pins = "mpp18"; +- marvell,function = "gpo"; +- }; +- +- pmx_hddled_20: pmx-hddled-20 { +- marvell,pins = "mpp20"; +- marvell,function = "gpio"; +- }; +- +- pmx_hddled_21: pmx-hddled-21 { +- marvell,pins = "mpp21"; +- marvell,function = "gpio"; +- }; +- +- pmx_hddled_22: pmx-hddled-22 { +- marvell,pins = "mpp22"; +- marvell,function = "gpio"; +- }; +- +- pmx_hddled_23: pmx-hddled-23 { +- marvell,pins = "mpp23"; +- marvell,function = "gpio"; +- }; +- +- pmx_hddled_24: pmx-hddled-24 { +- marvell,pins = "mpp24"; +- marvell,function = "gpio"; +- }; +- +- pmx_hddled_25: pmx-hddled-25 { +- marvell,pins = "mpp25"; +- marvell,function = "gpio"; +- }; +- +- pmx_hddled_26: pmx-hddled-26 { +- marvell,pins = "mpp26"; +- marvell,function = "gpio"; +- }; +- +- pmx_hddled_27: pmx-hddled-27 { +- marvell,pins = "mpp27"; +- marvell,function = "gpio"; +- }; +- +- pmx_hddled_28: pmx-hddled-28 { +- marvell,pins = "mpp28"; +- marvell,function = "gpio"; +- }; +- +- pmx_hdd1_pwr_29: pmx-hdd1-pwr-29 { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- +- pmx_hdd1_pwr_30: pmx-hdd-pwr-30 { +- marvell,pins = "mpp30"; +- marvell,function = "gpio"; +- }; +- +- pmx_hdd2_pwr_31: pmx-hdd2-pwr-31 { +- marvell,pins = "mpp31"; +- marvell,function = "gpio"; +- }; +- +- pmx_fanctrl_32: pmx-fanctrl-32 { +- marvell,pins = "mpp32"; +- marvell,function = "gpio"; +- }; +- +- pmx_fanctrl_33: pmx-fanctrl-33 { +- marvell,pins = "mpp33"; +- marvell,function = "gpo"; +- }; +- +- pmx_fanctrl_34: pmx-fanctrl-34 { +- marvell,pins = "mpp34"; +- marvell,function = "gpio"; +- }; +- +- pmx_hdd2_pwr_34: pmx-hdd2-pwr-34 { +- marvell,pins = "mpp34"; +- marvell,function = "gpio"; +- }; +- +- pmx_fanalarm_35: pmx-fanalarm-35 { +- marvell,pins = "mpp35"; +- marvell,function = "gpio"; +- }; +- +- pmx_hddled_36: pmx-hddled-36 { +- marvell,pins = "mpp36"; +- marvell,function = "gpio"; +- }; +- +- pmx_hddled_37: pmx-hddled-37 { +- marvell,pins = "mpp37"; +- marvell,function = "gpio"; +- }; +- +- pmx_hddled_38: pmx-hddled-38 { +- marvell,pins = "mpp38"; +- marvell,function = "gpio"; +- }; +- +- pmx_hddled_39: pmx-hddled-39 { +- marvell,pins = "mpp39"; +- marvell,function = "gpio"; +- }; +- +- pmx_hddled_40: pmx-hddled-40 { +- marvell,pins = "mpp40"; +- marvell,function = "gpio"; +- }; +- +- pmx_hddled_41: pmx-hddled-41 { +- marvell,pins = "mpp41"; +- marvell,function = "gpio"; +- }; +- +- pmx_hddled_42: pmx-hddled-42 { +- marvell,pins = "mpp42"; +- marvell,function = "gpio"; +- }; +- +- pmx_hddled_43: pmx-hddled-43 { +- marvell,pins = "mpp43"; +- marvell,function = "gpio"; +- }; +- +- pmx_hddled_44: pmx-hddled-44 { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- +- pmx_hddled_45: pmx-hddled-45 { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- +- pmx_hdd3_pwr_44: pmx-hdd3-pwr-44 { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- +- pmx_hdd4_pwr_45: pmx-hdd4-pwr-45 { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- +- pmx_fanalarm_44: pmx-fanalarm-44 { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- +- pmx_fanalarm_45: pmx-fanalarm-45 { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- }; +- +- rtc@10300 { +- status = "disabled"; +- }; +- +- spi@10600 { +- status = "okay"; +- +- m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p80", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- mode = <0>; +- +- partition@0 { +- reg = <0x00000000 0x00080000>; +- label = "RedBoot"; +- }; +- +- partition@80000 { +- reg = <0x00080000 0x00200000>; +- label = "zImage"; +- }; +- +- partition@280000 { +- reg = <0x00280000 0x00140000>; +- label = "rd.gz"; +- }; +- +- partition@3c0000 { +- reg = <0x003c0000 0x00010000>; +- label = "vendor"; +- }; +- +- partition@3d0000 { +- reg = <0x003d0000 0x00020000>; +- label = "RedBoot config"; +- }; +- +- partition@3f0000 { +- reg = <0x003f0000 0x00010000>; +- label = "FIS directory"; +- }; +- }; +- }; +- +- i2c@11000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- rs5c372: rs5c372@32 { +- status = "disabled"; +- compatible = "ricoh,rs5c372a"; +- reg = <0x32>; +- }; +- +- s35390a: s35390a@30 { +- status = "disabled"; +- compatible = "sii,s35390a"; +- reg = <0x30>; +- }; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- serial@12100 { +- status = "okay"; +- }; +- +- poweroff@12100 { +- compatible = "synology,power-off"; +- reg = <0x12100 0x100>; +- clocks = <&gate_clk 7>; +- }; +- +- sata@80000 { +- pinctrl-0 = <&pmx_sata0 &pmx_sata1>; +- pinctrl-names = "default"; +- status = "okay"; +- nr-ports = <2>; +- }; +- }; +- +- gpio-fan-150-32-35 { +- status = "disabled"; +- compatible = "gpio-fan"; +- pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 +- &pmx_fanalarm_35>; +- pinctrl-names = "default"; +- gpios = <&gpio1 0 GPIO_ACTIVE_HIGH +- &gpio1 1 GPIO_ACTIVE_HIGH +- &gpio1 2 GPIO_ACTIVE_HIGH>; +- gpio-fan,speed-map = < 0 0 +- 2200 1 +- 2500 2 +- 3000 4 +- 3300 3 +- 3700 5 +- 3800 6 +- 4200 7 >; +- }; +- +- gpio-fan-150-15-18 { +- status = "disabled"; +- compatible = "gpio-fan"; +- pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 +- &pmx_fanalarm_18>; +- pinctrl-names = "default"; +- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH +- &gpio0 16 GPIO_ACTIVE_HIGH +- &gpio0 17 GPIO_ACTIVE_HIGH>; +- alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; +- gpio-fan,speed-map = < 0 0 +- 2200 1 +- 2500 2 +- 3000 4 +- 3300 3 +- 3700 5 +- 3800 6 +- 4200 7 >; +- }; +- +- gpio-fan-100-32-35 { +- status = "disabled"; +- compatible = "gpio-fan"; +- pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 +- &pmx_fanalarm_35>; +- pinctrl-names = "default"; +- gpios = <&gpio1 0 GPIO_ACTIVE_HIGH +- &gpio1 1 GPIO_ACTIVE_HIGH +- &gpio1 2 GPIO_ACTIVE_HIGH>; +- alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; +- gpio-fan,speed-map = < 0 0 +- 2500 1 +- 3100 2 +- 3800 3 +- 4600 4 +- 4800 5 +- 4900 6 +- 5000 7 >; +- }; +- +- gpio-fan-100-15-18 { +- status = "disabled"; +- compatible = "gpio-fan"; +- pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 +- &pmx_fanalarm_18>; +- pinctrl-names = "default"; +- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH +- &gpio0 16 GPIO_ACTIVE_HIGH +- &gpio0 17 GPIO_ACTIVE_HIGH>; +- alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; +- gpio-fan,speed-map = < 0 0 +- 2500 1 +- 3100 2 +- 3800 3 +- 4600 4 +- 4800 5 +- 4900 6 +- 5000 7 >; +- }; +- +- gpio-fan-100-15-35-1 { +- status = "disabled"; +- compatible = "gpio-fan"; +- pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 +- &pmx_fanalarm_35>; +- pinctrl-names = "default"; +- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH +- &gpio0 16 GPIO_ACTIVE_HIGH +- &gpio0 17 GPIO_ACTIVE_HIGH>; +- alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; +- gpio-fan,speed-map = < 0 0 +- 2500 1 +- 3100 2 +- 3800 3 +- 4600 4 +- 4800 5 +- 4900 6 +- 5000 7 >; +- }; +- +- gpio-fan-100-15-35-3 { +- status = "disabled"; +- compatible = "gpio-fan"; +- pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 +- &pmx_fanalarm_35 &pmx_fanalarm_44 &pmx_fanalarm_45>; +- pinctrl-names = "default"; +- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH +- &gpio0 16 GPIO_ACTIVE_HIGH +- &gpio0 17 GPIO_ACTIVE_HIGH>; +- alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH +- &gpio1 12 GPIO_ACTIVE_HIGH +- &gpio1 13 GPIO_ACTIVE_HIGH>; +- gpio-fan,speed-map = < 0 0 +- 2500 1 +- 3100 2 +- 3800 3 +- 4600 4 +- 4800 5 +- 4900 6 +- 5000 7 >; +- }; +- +- gpio-leds-alarm-12 { +- status = "disabled"; +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_alarmled_12>; +- pinctrl-names = "default"; +- +- hdd1-green { +- label = "synology:alarm"; +- gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-leds-hdd-20 { +- status = "disabled"; +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_hddled_20 &pmx_hddled_21 &pmx_hddled_22 +- &pmx_hddled_23 &pmx_hddled_24 &pmx_hddled_25 +- &pmx_hddled_26 &pmx_hddled_27>; +- pinctrl-names = "default"; +- +- hdd1-green { +- label = "synology:green:hdd1"; +- gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; +- }; +- +- hdd1-amber { +- label = "synology:amber:hdd1"; +- gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; +- }; +- +- hdd2-green { +- label = "synology:green:hdd2"; +- gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; +- }; +- +- hdd2-amber { +- label = "synology:amber:hdd2"; +- gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; +- }; +- +- hdd3-green { +- label = "synology:green:hdd3"; +- gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; +- }; +- +- hdd3-amber { +- label = "synology:amber:hdd3"; +- gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; +- }; +- +- hdd4-green { +- label = "synology:green:hdd4"; +- gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; +- }; +- +- hdd4-amber { +- label = "synology:amber:hdd4"; +- gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-leds-hdd-21-1 { +- status = "disabled"; +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23>; +- pinctrl-names = "default"; +- +- hdd1-green { +- label = "synology:green:hdd1"; +- gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; +- }; +- +- hdd1-amber { +- label = "synology:amber:hdd1"; +- gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-leds-hdd-21-2 { +- status = "disabled"; +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23 &pmx_hddled_20 &pmx_hddled_22>; +- pinctrl-names = "default"; +- +- hdd1-green { +- label = "synology:green:hdd1"; +- gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; +- }; +- +- hdd1-amber { +- label = "synology:amber:hdd1"; +- gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; +- }; +- +- hdd2-green { +- label = "synology:green:hdd2"; +- gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; +- }; +- +- hdd2-amber { +- label = "synology:amber:hdd2"; +- gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-leds-hdd-36 { +- status = "disabled"; +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_hddled_36 &pmx_hddled_37 &pmx_hddled_38 +- &pmx_hddled_39 &pmx_hddled_40 &pmx_hddled_41 +- &pmx_hddled_42 &pmx_hddled_43 &pmx_hddled_44 +- &pmx_hddled_45>; +- pinctrl-names = "default"; +- +- hdd1-green { +- label = "synology:green:hdd1"; +- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- }; +- +- hdd1-amber { +- label = "synology:amber:hdd1"; +- gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +- }; +- +- hdd2-green { +- label = "synology:green:hdd2"; +- gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; +- }; +- +- hdd2-amber { +- label = "synology:amber:hdd2"; +- gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; +- }; +- +- hdd3-green { +- label = "synology:green:hdd3"; +- gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; +- }; +- +- hdd3-amber { +- label = "synology:amber:hdd3"; +- gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- }; +- +- hdd4-green { +- label = "synology:green:hdd4"; +- gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; +- }; +- +- hdd4-amber { +- label = "synology:amber:hdd4"; +- gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; +- }; +- +- hdd5-green { +- label = "synology:green:hdd5"; +- gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; +- }; +- +- hdd5-amber { +- label = "synology:amber:hdd5"; +- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-leds-hdd-38 { +- status = "disabled"; +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_hddled_38 &pmx_hddled_39 &pmx_hddled_36 &pmx_hddled_37>; +- pinctrl-names = "default"; +- +- hdd1-green { +- label = "synology:green:hdd1"; +- gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; +- }; +- +- hdd1-amber { +- label = "synology:amber:hdd1"; +- gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; +- }; +- +- hdd2-green { +- label = "synology:green:hdd2"; +- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +- }; +- +- hdd2-amber { +- label = "synology:amber:hdd2"; +- gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- regulators-hdd-29 { +- status = "disabled"; +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_hdd1_pwr_29 &pmx_hdd2_pwr_31>; +- pinctrl-names = "default"; +- +- regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "hdd1power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- startup-delay-us = <5000000>; +- gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; +- }; +- +- regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "hdd2power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- startup-delay-us = <5000000>; +- gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- regulators-hdd-30-1 { +- status = "disabled"; +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_hdd1_pwr_30>; +- pinctrl-names = "default"; +- +- regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "hdd1power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- startup-delay-us = <5000000>; +- gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- regulators-hdd-30-2 { +- status = "disabled"; +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34>; +- pinctrl-names = "default"; +- +- regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "hdd1power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- startup-delay-us = <5000000>; +- gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; +- }; +- +- regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "hdd2power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- startup-delay-us = <5000000>; +- gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- regulators-hdd-30-4 { +- status = "disabled"; +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34 +- &pmx_hdd3_pwr_44 &pmx_hdd4_pwr_45>; +- pinctrl-names = "default"; +- +- regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "hdd1power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- startup-delay-us = <5000000>; +- gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; +- }; +- +- regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "hdd2power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- startup-delay-us = <5000000>; +- gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- }; +- +- regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- regulator-name = "hdd3power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- startup-delay-us = <5000000>; +- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; +- }; +- +- regulator@4 { +- compatible = "regulator-fixed"; +- reg = <4>; +- regulator-name = "hdd4power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- startup-delay-us = <5000000>; +- gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- regulators-hdd-31 { +- status = "disabled"; +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_hdd2_pwr_31>; +- pinctrl-names = "default"; +- +- regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "hdd2power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- startup-delay-us = <5000000>; +- gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- regulators-hdd-34 { +- status = "disabled"; +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_hdd2_pwr_34 &pmx_hdd3_pwr_44 +- &pmx_hdd4_pwr_45>; +- pinctrl-names = "default"; +- +- regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "hdd2power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- startup-delay-us = <5000000>; +- gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- }; +- +- regulator@3 { +- compatible = "regulator-fixed"; +- reg = <3>; +- regulator-name = "hdd3power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- startup-delay-us = <5000000>; +- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; +- }; +- +- regulator@4 { +- compatible = "regulator-fixed"; +- reg = <4>; +- regulator-name = "hdd4power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- startup-delay-us = <5000000>; +- gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- device_type = "ethernet-phy"; +- reg = <8>; +- }; +- +- ethphy1: ethernet-phy@1 { +- device_type = "ethernet-phy"; +- reg = <9>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- +-ð1 { +- status = "disabled"; +- +- ethernet1-port@0 { +- phy-handle = <ðphy1>; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-t5325.dts b/scripts/dtc/include-prefixes/arm/kirkwood-t5325.dts +deleted file mode 100644 +index fe63b3a03a72..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-t5325.dts ++++ /dev/null +@@ -1,227 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree file for HP t5325 Thin Client" +- * +- * Copyright (C) 2014 +- * +- * Thomas Petazzoni +- * Andrew Lunn +- * +-*/ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +- +-/ { +- model = "HP t5325 Thin Client"; +- compatible = "hp,t5325", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pinctrl-0 = <&pmx_i2s &pmx_sysrst>; +- pinctrl-names = "default"; +- +- pmx_button_power: pmx-button_power { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- +- pmx_power_off: pmx-power-off { +- marvell,pins = "mpp48"; +- marvell,function = "gpio"; +- }; +- +- pmx_led: pmx-led { +- marvell,pins = "mpp21"; +- marvell,function = "gpio"; +- }; +- +- pmx_usb_sata_power_enable: pmx-usb-sata-power-enable { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- +- pmx_spi: pmx-spi { +- marvell,pins = "mpp1", "mpp2", "mpp3", "mpp7"; +- marvell,function = "spi"; +- }; +- +- pmx_sysrst: pmx-sysrst { +- marvell,pins = "mpp6"; +- marvell,function = "sysrst"; +- }; +- +- pmx_i2s: pmx-i2s { +- marvell,pins = "mpp39", "mpp40", "mpp41", "mpp42", +- "mpp43"; +- marvell,function = "audio"; +- }; +- }; +- +- spi@10600 { +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p80", "jedec,spi-nor"; +- spi-max-frequency = <86000000>; +- reg = <0>; +- mode = <0>; +- +- partition@0 { +- reg = <0x0 0x80000>; +- label = "u-boot"; +- }; +- +- partition@1 { +- reg = <0x80000 0x40000>; +- label = "SSD firmware"; +- }; +- +- partition@2 { +- reg = <0xc0000 0x10000>; +- label = "u-boot env"; +- }; +- +- partition@3 { +- reg = <0xd0000 0x10000>; +- label = "permanent u-boot env"; +- }; +- +- partition@4 { +- reg = <0xd0000 0x10000>; +- label = "permanent u-boot env"; +- }; +- }; +- }; +- +- i2c@11000 { +- status = "okay"; +- +- alc5621: alc5621@1a { +- compatible = "realtek,alc5621"; +- reg = <0x1a>; +- #sound-dai-cells = <0>; +- add-ctrl = <0x3700>; +- jack-det-ctrl = <0x4810>; +- }; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- sata@80000 { +- status = "okay"; +- nr-ports = <2>; +- }; +- +- audio: audio-controller@a0000 { +- status = "okay"; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_usb_sata_power_enable>; +- pinctrl-names = "default"; +- +- usb_power: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "USB-SATA Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_button_power>; +- pinctrl-names = "default"; +- +- power { +- label = "Power Button"; +- linux,code = ; +- gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio_poweroff { +- compatible = "gpio-poweroff"; +- pinctrl-0 = <&pmx_power_off>; +- pinctrl-names = "default"; +- gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,routing = +- "Headphone Jack", "HPL", +- "Headphone Jack", "HPR", +- "Speaker", "SPKOUT", +- "Speaker", "SPKOUTN", +- "MIC1", "Mic Jack", +- "MIC2", "Mic Jack"; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack", +- "Speaker", "Speaker", +- "Microphone", "Mic Jack"; +- +- simple-audio-card,mclk-fs = <256>; +- +- simple-audio-card,cpu { +- sound-dai = <&audio>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&alc5621>; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@8 { +- device_type = "ethernet-phy"; +- reg = <8>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-topkick.dts b/scripts/dtc/include-prefixes/arm/kirkwood-topkick.dts +deleted file mode 100644 +index a5b51e29f63e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-topkick.dts ++++ /dev/null +@@ -1,216 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6282.dtsi" +- +-/ { +- model = "Universal Scientific Industrial Co. Topkick-1281P2"; +- compatible = "usi,topkick-1281P2", "usi,topkick", "marvell,kirkwood-88f6282", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- /* +- * Switch positions +- * +- * /-SW_LEFT(2) +- * | +- * | /-SW_IDLE +- * | | +- * | | /-SW_RIGHT +- * | | | +- * PS [L] [I] [R] LEDS +- */ +- pinctrl-0 = <&pmx_sw_left &pmx_sw_right +- &pmx_sw_idle &pmx_sw_left2>; +- pinctrl-names = "default"; +- +- pmx_led_disk_yellow: pmx-led-disk-yellow { +- marvell,pins = "mpp21"; +- marvell,function = "gpio"; +- }; +- +- pmx_sata0_pwr_enable: pmx-sata0-pwr-enable { +- marvell,pins = "mpp36"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_sys_red: pmx-led-sys-red { +- marvell,pins = "mpp37"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_sys_blue: pmx-led-sys-blue { +- marvell,pins = "mpp38"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_wifi_green: pmx-led-wifi-green { +- marvell,pins = "mpp39"; +- marvell,function = "gpio"; +- }; +- +- pmx_sw_left: pmx-sw-left { +- marvell,pins = "mpp43"; +- marvell,function = "gpio"; +- }; +- +- pmx_sw_right: pmx-sw-right { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- +- pmx_sw_idle: pmx-sw-idle { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- +- pmx_sw_left2: pmx-sw-left2 { +- marvell,pins = "mpp46"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_wifi_yellow: pmx-led-wifi-yellow { +- marvell,pins = "mpp48"; +- marvell,function = "gpio"; +- }; +- }; +- +- serial@12000 { +- status = "okay"; +- }; +- +- sata@80000 { +- status = "okay"; +- nr-ports = <1>; +- }; +- +- i2c@11000 { +- status = "okay"; +- }; +- +- mvsdio@90000 { +- pinctrl-0 = <&pmx_sdio>; +- pinctrl-names = "default"; +- status = "okay"; +- /* No CD or WP GPIOs */ +- broken-cd; +- }; +- }; +- +- gpio-leds { +- /* +- * GPIO LED layout +- * +- * /-SYS_LED(2) +- * | +- * | /-DISK_LED +- * | | +- * | | /-WLAN_LED(2) +- * | | | +- * [SW] [*] [*] [*] +- */ +- +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_led_disk_yellow &pmx_led_sys_red +- &pmx_led_sys_blue &pmx_led_wifi_green +- &pmx_led_wifi_yellow>; +- pinctrl-names = "default"; +- +- disk { +- label = "topkick:yellow:disk"; +- gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "disk-activity"; +- }; +- system2 { +- label = "topkick:red:system"; +- gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +- }; +- system { +- label = "topkick:blue:system"; +- gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- wifi { +- label = "topkick:green:wifi"; +- gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; +- }; +- wifi2 { +- label = "topkick:yellow:wifi"; +- gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +- }; +- }; +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_sata0_pwr_enable>; +- pinctrl-names = "default"; +- +- sata0_power: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "SATA0 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio1 4 0>; +- }; +- }; +-}; +- +-&nand { +- status = "okay"; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x180000>; +- }; +- +- partition@180000 { +- label = "u-boot env"; +- reg = <0x0180000 0x20000>; +- }; +- +- partition@200000 { +- label = "uImage"; +- reg = <0x0200000 0x600000>; +- }; +- +- partition@800000 { +- label = "uInitrd"; +- reg = <0x0800000 0x1000000>; +- }; +- +- partition@1800000 { +- label = "rootfs"; +- reg = <0x1800000 0xe800000>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ts219-6281.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ts219-6281.dts +deleted file mode 100644 +index 30892c19aceb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ts219-6281.dts ++++ /dev/null +@@ -1,56 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +-#include "kirkwood-ts219.dtsi" +- +-/ { +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- +- pinctrl-0 = <&pmx_ram_size &pmx_board_id>; +- pinctrl-names = "default"; +- +- pmx_ram_size: pmx-ram-size { +- /* RAM: 0: 256 MB, 1: 512 MB */ +- marvell,pins = "mpp36"; +- marvell,function = "gpio"; +- }; +- pmx_USB_copy_button: pmx-USB-copy-button { +- marvell,pins = "mpp15"; +- marvell,function = "gpio"; +- }; +- pmx_reset_button: pmx-reset-button { +- marvell,pins = "mpp16"; +- marvell,function = "gpio"; +- }; +- pmx_board_id: pmx-board-id { +- /* 0: TS-11x, 1: TS-21x */ +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; +- pinctrl-names = "default"; +- +- copy { +- label = "USB Copy"; +- linux,code = ; +- gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; +- }; +- reset { +- label = "Reset"; +- linux,code = ; +- gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-ðphy0 { reg = <8>; }; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ts219-6282.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ts219-6282.dts +deleted file mode 100644 +index aba1205981f1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ts219-6282.dts ++++ /dev/null +@@ -1,58 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6282.dtsi" +-#include "kirkwood-ts219.dtsi" +- +-/ { +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- +- pinctrl-0 = <&pmx_ram_size &pmx_board_id>; +- pinctrl-names = "default"; +- +- pmx_ram_size: pmx-ram-size { +- /* RAM: 0: 256 MB, 1: 512 MB */ +- marvell,pins = "mpp36"; +- marvell,function = "gpio"; +- }; +- pmx_reset_button: pmx-reset-button { +- marvell,pins = "mpp37"; +- marvell,function = "gpio"; +- }; +- pmx_USB_copy_button: pmx-USB-copy-button { +- marvell,pins = "mpp43"; +- marvell,function = "gpio"; +- }; +- pmx_board_id: pmx-board-id { +- /* 0: TS-11x, 1: TS-21x */ +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; +- pinctrl-names = "default"; +- +- copy { +- label = "USB Copy"; +- linux,code = ; +- gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; +- }; +- reset { +- label = "Reset"; +- linux,code = ; +- gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-ðphy0 { reg = <0>; }; +- +-&pcie1 { status = "okay"; }; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ts219.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-ts219.dtsi +deleted file mode 100644 +index 994cabcf4b51..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ts219.dtsi ++++ /dev/null +@@ -1,114 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- model = "QNAP TS219 family"; +- compatible = "qnap,ts219", "marvell,kirkwood"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = &uart0; +- }; +- +- ocp@f1000000 { +- i2c@11000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- s35390a: s35390a@30 { +- compatible = "s35390a"; +- reg = <0x30>; +- }; +- }; +- serial@12000 { +- status = "okay"; +- }; +- serial@12100 { +- status = "okay"; +- }; +- poweroff@12100 { +- compatible = "qnap,power-off"; +- reg = <0x12100 0x100>; +- clocks = <&gate_clk 7>; +- }; +- spi@10600 { +- status = "okay"; +- +- m25p128@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p128", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- mode = <0>; +- +- partition@0 { +- reg = <0x00000000 0x00080000>; +- label = "U-Boot"; +- }; +- +- partition@200000 { +- reg = <0x00200000 0x00200000>; +- label = "Kernel"; +- }; +- +- partition@400000 { +- reg = <0x00400000 0x00900000>; +- label = "RootFS1"; +- }; +- partition@d00000 { +- reg = <0x00d00000 0x00300000>; +- label = "RootFS2"; +- }; +- partition@40000 { +- reg = <0x00080000 0x00040000>; +- label = "U-Boot Config"; +- }; +- partition@c0000 { +- reg = <0x000c0000 0x00140000>; +- label = "NAS Config"; +- }; +- }; +- }; +- sata@80000 { +- pinctrl-0 = <&pmx_sata0 &pmx_sata1>; +- pinctrl-names = "default"; +- status = "okay"; +- nr-ports = <2>; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy0: ethernet-phy@X { +- /* overwrite reg property in board file */ +- }; +-}; +- +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&rtc { +- /* +- * There is a s35390a available on the i2c bus, the internal rtc isn't +- * working (probably no crystal assembled). +- */ +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ts419-6281.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ts419-6281.dts +deleted file mode 100644 +index 4a42ebcca4f0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ts419-6281.dts ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Device Tree file for QNAP TS41X with 6281 SoC +- * +- * Copyright (C) 2013, Andrew Lunn +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6281.dtsi" +-#include "kirkwood-ts219.dtsi" +-#include "kirkwood-ts419.dtsi" +- +-ðphy0 { reg = <8>; }; +-ðphy1 { reg = <0>; }; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ts419-6282.dts b/scripts/dtc/include-prefixes/arm/kirkwood-ts419-6282.dts +deleted file mode 100644 +index be772e194c2b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ts419-6282.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Device Tree file for QNAP TS41X with 6282 SoC +- * +- * Copyright (C) 2013, Andrew Lunn +- */ +- +-/dts-v1/; +- +-#include "kirkwood.dtsi" +-#include "kirkwood-6282.dtsi" +-#include "kirkwood-ts219.dtsi" +-#include "kirkwood-ts419.dtsi" +- +-ðphy0 { reg = <0>; }; +-ðphy1 { reg = <1>; }; +- +-&pciec { status = "okay"; }; +-&pcie1 { status = "okay"; }; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood-ts419.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood-ts419.dtsi +deleted file mode 100644 +index 717236853e45..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood-ts419.dtsi ++++ /dev/null +@@ -1,71 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Device Tree include file for QNAP TS41X +- * +- * Copyright (C) 2013, Andrew Lunn +- */ +- +-/ { +- model = "QNAP TS419 family"; +- compatible = "qnap,ts419", "marvell,kirkwood"; +- +- ocp@f1000000 { +- pinctrl: pin-controller@10000 { +- pinctrl-names = "default"; +- +- pmx_USB_copy_button: pmx-USB-copy-button { +- marvell,pins = "mpp43"; +- marvell,function = "gpio"; +- }; +- pmx_reset_button: pmx-reset-button { +- marvell,pins = "mpp37"; +- marvell,function = "gpio"; +- }; +- /* +- * JP1 indicates if an LCD module is installed +- * on the serial port (0), or if the port is used +- * as a console (1). +- */ +- pmx_jumper_jp1: pmx-jumper_jp1 { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; +- pinctrl-names = "default"; +- +- copy { +- label = "USB Copy"; +- linux,code = ; +- gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; +- }; +- reset { +- label = "Reset"; +- linux,code = ; +- gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy1: ethernet-phy@1 { +- device_type = "ethernet-phy"; +- /* overwrite reg property in board file */ +- }; +-}; +- +-ð1 { +- status = "okay"; +- ethernet1-port@0 { +- phy-handle = <ðphy1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/kirkwood.dtsi b/scripts/dtc/include-prefixes/arm/kirkwood.dtsi +deleted file mode 100644 +index fca31a5d5ac7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/kirkwood.dtsi ++++ /dev/null +@@ -1,394 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +- +-#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "marvell,kirkwood"; +- interrupt-parent = <&intc>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "marvell,feroceon"; +- reg = <0>; +- clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>; +- clock-names = "cpu_clk", "ddrclk", "powersave"; +- }; +- }; +- +- aliases { +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- i2c0 = &i2c0; +- }; +- +- mbus@f1000000 { +- compatible = "marvell,kirkwood-mbus", "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- /* If a board file needs to change this ranges it must replace it completely */ +- ranges = ; +- controller = <&mbusc>; +- pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ +- pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ +- +- nand: nand@12f { +- #address-cells = <1>; +- #size-cells = <1>; +- cle = <0>; +- ale = <1>; +- bank-width = <1>; +- compatible = "marvell,orion-nand"; +- reg = ; +- chip-delay = <25>; +- /* set partition map and/or chip-delay in board dts */ +- clocks = <&gate_clk 7>; +- pinctrl-0 = <&pmx_nand>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- crypto_sram: sa-sram@301 { +- compatible = "mmio-sram"; +- reg = ; +- clocks = <&gate_clk 17>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- }; +- +- ocp@f1000000 { +- compatible = "simple-bus"; +- ranges = <0x00000000 0xf1000000 0x0100000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- pinctrl: pin-controller@10000 { +- /* set compatible property in SoC file */ +- reg = <0x10000 0x20>; +- +- pmx_ge1: pmx-ge1 { +- marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23", +- "mpp24", "mpp25", "mpp26", "mpp27", +- "mpp30", "mpp31", "mpp32", "mpp33"; +- marvell,function = "ge1"; +- }; +- +- pmx_nand: pmx-nand { +- marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", +- "mpp4", "mpp5", "mpp18", "mpp19"; +- marvell,function = "nand"; +- }; +- +- /* +- * Default SPI0 pinctrl setting with CSn on mpp0, +- * overwrite marvell,pins on board level if required. +- */ +- pmx_spi: pmx-spi { +- marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; +- marvell,function = "spi"; +- }; +- +- pmx_twsi0: pmx-twsi0 { +- marvell,pins = "mpp8", "mpp9"; +- marvell,function = "twsi0"; +- }; +- +- /* +- * Default UART pinctrl setting without RTS/CTS, +- * overwrite marvell,pins on board level if required. +- */ +- pmx_uart0: pmx-uart0 { +- marvell,pins = "mpp10", "mpp11"; +- marvell,function = "uart0"; +- }; +- +- pmx_uart1: pmx-uart1 { +- marvell,pins = "mpp13", "mpp14"; +- marvell,function = "uart1"; +- }; +- }; +- +- core_clk: core-clocks@10030 { +- compatible = "marvell,kirkwood-core-clock"; +- reg = <0x10030 0x4>; +- #clock-cells = <1>; +- }; +- +- spi0: spi@10600 { +- compatible = "marvell,orion-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- interrupts = <23>; +- reg = <0x10600 0x28>; +- clocks = <&gate_clk 7>; +- pinctrl-0 = <&pmx_spi>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- gpio0: gpio@10100 { +- compatible = "marvell,orion-gpio"; +- #gpio-cells = <2>; +- gpio-controller; +- reg = <0x10100 0x40>; +- ngpios = <32>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <35>, <36>, <37>, <38>; +- clocks = <&gate_clk 7>; +- }; +- +- gpio1: gpio@10140 { +- compatible = "marvell,orion-gpio"; +- #gpio-cells = <2>; +- gpio-controller; +- reg = <0x10140 0x40>; +- ngpios = <18>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <39>, <40>, <41>; +- clocks = <&gate_clk 7>; +- }; +- +- i2c0: i2c@11000 { +- compatible = "marvell,mv64xxx-i2c"; +- reg = <0x11000 0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <29>; +- clock-frequency = <100000>; +- clocks = <&gate_clk 7>; +- pinctrl-0 = <&pmx_twsi0>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- uart0: serial@12000 { +- compatible = "ns16550a"; +- reg = <0x12000 0x100>; +- reg-shift = <2>; +- interrupts = <33>; +- clocks = <&gate_clk 7>; +- pinctrl-0 = <&pmx_uart0>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- uart1: serial@12100 { +- compatible = "ns16550a"; +- reg = <0x12100 0x100>; +- reg-shift = <2>; +- interrupts = <34>; +- clocks = <&gate_clk 7>; +- pinctrl-0 = <&pmx_uart1>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- mbusc: mbus-controller@20000 { +- compatible = "marvell,mbus-controller"; +- reg = <0x20000 0x80>, <0x1500 0x20>; +- }; +- +- sysc: system-controller@20000 { +- compatible = "marvell,orion-system-controller"; +- reg = <0x20000 0x120>; +- }; +- +- bridge_intc: bridge-interrupt-ctrl@20110 { +- compatible = "marvell,orion-bridge-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x20110 0x8>; +- interrupts = <1>; +- marvell,#interrupts = <6>; +- }; +- +- gate_clk: clock-gating-control@2011c { +- compatible = "marvell,kirkwood-gating-clock"; +- reg = <0x2011c 0x4>; +- clocks = <&core_clk 0>; +- #clock-cells = <1>; +- }; +- +- l2: l2-cache@20128 { +- compatible = "marvell,kirkwood-cache"; +- reg = <0x20128 0x4>; +- }; +- +- intc: interrupt-controller@20200 { +- compatible = "marvell,orion-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x20200 0x10>, <0x20210 0x10>; +- }; +- +- timer: timer@20300 { +- compatible = "marvell,orion-timer"; +- reg = <0x20300 0x20>; +- interrupt-parent = <&bridge_intc>; +- interrupts = <1>, <2>; +- clocks = <&core_clk 0>; +- }; +- +- wdt: watchdog-timer@20300 { +- compatible = "marvell,orion-wdt"; +- reg = <0x20300 0x28>, <0x20108 0x4>; +- interrupt-parent = <&bridge_intc>; +- interrupts = <3>; +- clocks = <&gate_clk 7>; +- status = "okay"; +- }; +- +- cesa: crypto@30000 { +- compatible = "marvell,kirkwood-crypto"; +- reg = <0x30000 0x10000>; +- reg-names = "regs"; +- interrupts = <22>; +- clocks = <&gate_clk 17>; +- marvell,crypto-srams = <&crypto_sram>; +- marvell,crypto-sram-size = <0x800>; +- status = "okay"; +- }; +- +- usb0: ehci@50000 { +- compatible = "marvell,orion-ehci"; +- reg = <0x50000 0x1000>; +- interrupts = <19>; +- clocks = <&gate_clk 3>; +- status = "okay"; +- }; +- +- dma0: xor@60800 { +- compatible = "marvell,orion-xor"; +- reg = <0x60800 0x100 +- 0x60A00 0x100>; +- status = "okay"; +- clocks = <&gate_clk 8>; +- +- xor00 { +- interrupts = <5>; +- dmacap,memcpy; +- dmacap,xor; +- }; +- xor01 { +- interrupts = <6>; +- dmacap,memcpy; +- dmacap,xor; +- dmacap,memset; +- }; +- }; +- +- dma1: xor@60900 { +- compatible = "marvell,orion-xor"; +- reg = <0x60900 0x100 +- 0x60B00 0x100>; +- status = "okay"; +- clocks = <&gate_clk 16>; +- +- xor00 { +- interrupts = <7>; +- dmacap,memcpy; +- dmacap,xor; +- }; +- xor01 { +- interrupts = <8>; +- dmacap,memcpy; +- dmacap,xor; +- dmacap,memset; +- }; +- }; +- +- eth0: ethernet-controller@72000 { +- compatible = "marvell,kirkwood-eth"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x72000 0x4000>; +- clocks = <&gate_clk 0>; +- marvell,tx-checksum-limit = <1600>; +- status = "disabled"; +- +- eth0port: ethernet0-port@0 { +- compatible = "marvell,kirkwood-eth-port"; +- reg = <0>; +- interrupts = <11>; +- /* overwrite MAC address in bootloader */ +- local-mac-address = [00 00 00 00 00 00]; +- /* set phy-handle property in board file */ +- }; +- }; +- +- mdio: mdio-bus@72004 { +- compatible = "marvell,orion-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x72004 0x84>; +- interrupts = <46>; +- clocks = <&gate_clk 0>; +- status = "disabled"; +- +- /* add phy nodes in board file */ +- }; +- +- eth1: ethernet-controller@76000 { +- compatible = "marvell,kirkwood-eth"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x76000 0x4000>; +- clocks = <&gate_clk 19>; +- marvell,tx-checksum-limit = <1600>; +- pinctrl-0 = <&pmx_ge1>; +- pinctrl-names = "default"; +- status = "disabled"; +- +- eth1port: ethernet1-port@0 { +- compatible = "marvell,kirkwood-eth-port"; +- reg = <0>; +- interrupts = <15>; +- /* overwrite MAC address in bootloader */ +- local-mac-address = [00 00 00 00 00 00]; +- /* set phy-handle property in board file */ +- }; +- }; +- +- sata_phy0: sata-phy@82000 { +- compatible = "marvell,mvebu-sata-phy"; +- reg = <0x82000 0x0334>; +- clocks = <&gate_clk 14>; +- clock-names = "sata"; +- #phy-cells = <0>; +- status = "okay"; +- }; +- +- sata_phy1: sata-phy@84000 { +- compatible = "marvell,mvebu-sata-phy"; +- reg = <0x84000 0x0334>; +- clocks = <&gate_clk 15>; +- clock-names = "sata"; +- #phy-cells = <0>; +- status = "okay"; +- }; +- +- audio0: audio-controller@a0000 { +- compatible = "marvell,kirkwood-audio"; +- #sound-dai-cells = <0>; +- reg = <0xa0000 0x2210>; +- interrupts = <24>; +- clocks = <&gate_clk 9>; +- clock-names = "internal"; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/logicpd-som-lv-35xx-devkit.dts b/scripts/dtc/include-prefixes/arm/logicpd-som-lv-35xx-devkit.dts +deleted file mode 100644 +index 2a0a98fe67f0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/logicpd-som-lv-35xx-devkit.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +- +-/dts-v1/; +- +-#include "omap34xx.dtsi" +-#include "logicpd-som-lv.dtsi" +-#include "logicpd-som-lv-baseboard.dtsi" +-#include "omap-gpmc-smsc9221.dtsi" +- +-/ { +- model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit"; +- compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3430", "ti,omap3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/logicpd-som-lv-37xx-devkit.dts b/scripts/dtc/include-prefixes/arm/logicpd-som-lv-37xx-devkit.dts +deleted file mode 100644 +index a604d92221a4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/logicpd-som-lv-37xx-devkit.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +- +-/dts-v1/; +- +-#include "omap36xx.dtsi" +-#include "logicpd-som-lv.dtsi" +-#include "logicpd-som-lv-baseboard.dtsi" +-#include "omap-gpmc-smsc9221.dtsi" +- +-/ { +- model = "LogicPD Zoom DM3730 SOM-LV Development Kit"; +- compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/logicpd-som-lv-baseboard.dtsi b/scripts/dtc/include-prefixes/arm/logicpd-som-lv-baseboard.dtsi +deleted file mode 100644 +index 7d0468a23781..000000000000 +--- a/scripts/dtc/include-prefixes/arm/logicpd-som-lv-baseboard.dtsi ++++ /dev/null +@@ -1,237 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +- +-/ { +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_key_pins>; +- +- sysboot2 { +- label = "gpio3"; +- gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* gpio_111 / uP_GPIO_3 */ +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- sound { +- compatible = "ti,omap-twl4030"; +- ti,model = "omap3logic"; +- ti,mcbsp = <&mcbsp2>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins &led_pins_wkup>; +- +- led1 { +- label = "led1"; +- gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* gpio133 */ +- linux,default-trigger = "cpu0"; +- }; +- +- led2 { +- label = "led2"; +- gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* gpio11 */ +- linux,default-trigger = "none"; +- }; +- }; +-}; +- +-&vaux1 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +-}; +- +-&vaux4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +-}; +- +-&mcbsp2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp2_pins>; +-}; +- +-&charger { +- ti,bb-uvolt = <3200000>; +- ti,bb-uamp = <150>; +-}; +- +-&gpmc { +- ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ +- 1 0 0x2c000000 0x1000000 /* CS1: 16MB for LAN9221 */ +- 2 0 0x10000000 0x2000000>; /* CS2: 32MB for NOR */ +- +- ethernet@gpmc { +- pinctrl-names = "default"; +- pinctrl-0 = <&lan9221_pins>; +- interrupt-parent = <&gpio5>; +- interrupts = <24 IRQ_TYPE_LEVEL_LOW>; /* gpio_152 */ +- reg = <1 0 0xff>; +- }; +-}; +- +-&vpll2 { +- regulator-always-on; +-}; +- +-&dss { +- status = "okay"; +- vdds_dsi-supply = <&vpll2>; +- vdda_video-supply = <&video_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_dpi_pins1>; +- port { +- dpi_out: endpoint { +- remote-endpoint = <&lcd_in>; +- data-lines = <16>; +- }; +- }; +-}; +- +-/ { +- aliases { +- display0 = &lcd0; +- }; +- +- video_reg: video_reg { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- lcd0: display { +- /* This isn't the exact LCD, but the timings meet spec */ +- compatible = "logicpd,type28"; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_enable_pin>; +- backlight = <&bl>; +- enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; +- port { +- lcd_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- }; +- +- bl: backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&backlight_pins>; +- pwms = <&twl_pwm 0 5000000>; +- brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; +- default-brightness-level = <7>; +- enable-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* gpio_8 */ +- }; +-}; +- +-&mmc1 { +- interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */ +- cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* gpio_110 */ +- vmmc-supply = <&vmmc1>; +- bus-width = <4>; +- cap-power-off-card; +-}; +- +-&omap3_pmx_core { +- gpio_key_pins: pinmux_gpio_key_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_xclkb.gpio_111 / uP_GPIO_3*/ +- >; +- }; +- +- led_pins: pinmux_led_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x215e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* sdmmc2_dat1.gpio_133 / uP_GPIO_0 */ +- >; +- }; +- +- lan9221_pins: pinmux_lan9221_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ +- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ +- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ +- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ +- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ +- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ +- OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_strobe.gpio_126 */ +- OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d11.gpio_110 */ +- >; +- }; +- +- lcd_enable_pin: pinmux_lcd_enable_pin { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ +- >; +- }; +- +- dss_dpi_pins1: pinmux_dss_dpi_pins1 { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ +- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ +- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */ +- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */ +- +- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data0.dss_data0 */ +- OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data1.dss_data1 */ +- OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data2.dss_data2 */ +- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data3.dss_data3 */ +- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data4.dss_data4 */ +- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data5.dss_data5 */ +- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */ +- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */ +- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */ +- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */ +- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */ +- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */ +- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */ +- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */ +- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */ +- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */ +- >; +- }; +-}; +- +-&omap3_pmx_wkup { +- led_pins_wkup: pinmux_led_pins_wkup { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 / uP_GPIO_1 */ +- >; +- }; +- +- backlight_pins: pinmux_backlight_pins { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* sys_boot6.gpio_8 */ +- >; +- }; +-}; +- +- +-&uart1 { +- interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; +-}; +- +-/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */ +-&usb_otg_hs { +- pinctrl-names = "default"; +- pinctrl-0 = <&hsusb_otg_pins>; +- interface-type = <0>; +- usb-phy = <&usb2_phy>; +- phys = <&usb2_phy>; +- phy-names = "usb2-phy"; +- mode = <3>; +- power = <50>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/logicpd-som-lv.dtsi b/scripts/dtc/include-prefixes/arm/logicpd-som-lv.dtsi +deleted file mode 100644 +index b56524cc7fe2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/logicpd-som-lv.dtsi ++++ /dev/null +@@ -1,311 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +- +-#include +- +-/ { +- cpus { +- cpu@0 { +- cpu0-supply = <&vcc>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0>; +- }; +- +- wl12xx_vmmc: wl12xx_vmmc { +- compatible = "regulator-fixed"; +- regulator-name = "vwl1271"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio1 3 0>; /* gpio_3 */ +- startup-delay-us = <70000>; +- enable-active-high; +- vin-supply = <&vaux3>; +- }; +- +- /* HS USB Host PHY on PORT 1 */ +- hsusb2_phy: hsusb2_phy { +- compatible = "usb-nop-xceiv"; +- reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */ +- #phy-cells = <0>; +- }; +- +- /* fixed 26MHz oscillator */ +- hfclk_26m: oscillator { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- }; +-}; +- +-&gpmc { +- ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ +- +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- linux,mtd-name = "micron,mt29f4g16abbda3w"; +- nand-bus-width = <16>; +- ti,nand-ecc-opt = "bch8"; +- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- gpmc,device-width = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- clock-frequency = <2600000>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- interrupt-parent = <&intc>; +- clocks = <&hfclk_26m>; +- clock-names = "fck"; +- twl_audio: audio { +- compatible = "ti,twl4030-audio"; +- codec { +- ti,hs_extmute_gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- clock-frequency = <400000>; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- clock-frequency = <400000>; +- +- touchscreen: tsc2004@48 { +- compatible = "ti,tsc2004"; +- reg = <0x48>; +- vio-supply = <&vaux1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsc2004_pins>; +- interrupts-extended = <&gpio5 25 IRQ_TYPE_EDGE_RISING>; /* gpio 153 */ +- +- touchscreen-fuzz-x = <4>; +- touchscreen-fuzz-y = <7>; +- touchscreen-fuzz-pressure = <2>; +- touchscreen-size-x = <4096>; +- touchscreen-size-y = <4096>; +- touchscreen-max-pressure = <2048>; +- +- ti,x-plate-ohms = <280>; +- ti,esd-recovery-timeout-ms = <8000>; +- }; +-}; +- +-&mmc3 { +- interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>; +- pinctrl-0 = <&mmc3_pins &wl127x_gpio>; +- pinctrl-names = "default"; +- vmmc-supply = <&wl12xx_vmmc>; +- non-removable; +- bus-width = <4>; +- cap-power-off-card; +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1273"; +- reg = <2>; +- interrupt-parent = <&gpio1>; +- interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 2 */ +- ref-clock-frequency = <26000000>; +- }; +-}; +- +-&usbhshost { +- port2-mode = "ehci-phy"; +-}; +- +-&usbhsehci { +- phys = <0 &hsusb2_phy>; +-}; +- +- +-&omap3_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = <&hsusb2_pins>; +- +- mmc3_pins: pinmux_mm3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ +- OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ +- OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */ +- OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */ +- OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ +- OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */ +- >; +- }; +- mcbsp2_pins: pinmux_mcbsp2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ +- OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ +- OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ +- OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ +- >; +- }; +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ +- OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ +- OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ +- OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ +- OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ +- >; +- }; +- mcspi1_pins: pinmux_mcspi1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ +- OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ +- OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ +- OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ +- >; +- }; +- +- hsusb2_pins: pinmux_hsusb2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ +- OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ +- OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ +- OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ +- OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ +- OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ +- >; +- }; +- +- hsusb_otg_pins: pinmux_hsusb_otg_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ +- OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ +- OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ +- OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ +- OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ +- OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ +- OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ +- OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ +- OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ +- OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ +- OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ +- OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ +- OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ +- OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ +- >; +- }; +- +- i2c2_pins: pinmux_i2c2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ +- OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ +- >; +- }; +- +- i2c3_pins: pinmux_i2c3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ +- OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ +- >; +- }; +- +- tsc2004_pins: pinmux_tsc2004_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ +- >; +- }; +-}; +- +-&omap3_pmx_wkup { +- pinctrl-names = "default"; +- pinctrl-0 = <&hsusb2_reset_pin>; +- hsusb2_reset_pin: pinmux_hsusb1_reset_pin { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ +- >; +- }; +- wl127x_gpio: pinmux_wl127x_gpio_pin { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */ +- OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ +- >; +- }; +-}; +- +-&omap3_pmx_core2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hsusb2_2_pins>; +- hsusb2_2_pins: pinmux_hsusb2_2_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ +- OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ +- OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ +- OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ +- OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ +- OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ +- >; +- }; +-}; +- +-&uart2 { +- interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +-}; +- +-&mcspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcspi1_pins>; +-}; +- +-#include "twl4030.dtsi" +-#include "twl4030_omap3.dtsi" +- +-&vaux3 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +-}; +- +-&twl { +- twl_power: power { +- compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle"; +- ti,use_poweroff; +- }; +-}; +- +-&twl_gpio { +- ti,use-leds; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/logicpd-torpedo-35xx-devkit.dts b/scripts/dtc/include-prefixes/arm/logicpd-torpedo-35xx-devkit.dts +deleted file mode 100644 +index 57bae2aa910e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/logicpd-torpedo-35xx-devkit.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +- +-/dts-v1/; +- +-#include "omap34xx.dtsi" +-#include "logicpd-torpedo-som.dtsi" +-#include "logicpd-torpedo-baseboard.dtsi" +-#include "omap-gpmc-smsc9221.dtsi" +- +-/ { +- model = "LogicPD Zoom OMAP35xx Torpedo Development Kit"; +- compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3430", "ti,omap3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/logicpd-torpedo-37xx-devkit-28.dts b/scripts/dtc/include-prefixes/arm/logicpd-torpedo-37xx-devkit-28.dts +deleted file mode 100644 +index b5536132971f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/logicpd-torpedo-37xx-devkit-28.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/dts-v1/; +- +-/* +- * There are two types of 4.3" LCD, Type 15 and Type 28. +- * By default, type 15 was used. This device tree file +- * uses the timing for the type 28 LCD +- */ +- +-#include "logicpd-torpedo-37xx-devkit.dts" +- +-&lcd0 { +- compatible = "logicpd,type28"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/logicpd-torpedo-37xx-devkit.dts b/scripts/dtc/include-prefixes/arm/logicpd-torpedo-37xx-devkit.dts +deleted file mode 100644 +index 5532db04046c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/logicpd-torpedo-37xx-devkit.dts ++++ /dev/null +@@ -1,87 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +- +-/dts-v1/; +- +-#include "omap36xx.dtsi" +-#include "logicpd-torpedo-som.dtsi" +-#include "omap-gpmc-smsc9221.dtsi" +-#include "logicpd-torpedo-baseboard.dtsi" +- +-/ { +- model = "LogicPD Zoom DM3730 Torpedo + Wireless Development Kit"; +- compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3"; +- +- wl12xx_vmmc: wl12xx_vmmc { +- compatible = "regulator-fixed"; +- regulator-name = "vwl1271"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio5 29 0>; /* gpio157 */ +- startup-delay-us = <70000>; +- enable-active-high; +- vin-supply = <&vmmc2>; +- }; +-}; +- +-/* +- * Only found on the wireless SOM. For the SOM without wireless, the pins for +- * MMC3 can be routed with jumpers to the second MMC slot on the devkit and +- * gpio157 is not connected. So this should be OK to keep common for now, +- * probably device tree overlays is the way to go with the various SOM and +- * jumpering combinations for the long run. +- */ +-&mmc3 { +- interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>; +- pinctrl-0 = <&mmc3_pins &mmc3_core2_pins>; +- pinctrl-names = "default"; +- vmmc-supply = <&wl12xx_vmmc>; +- non-removable; +- bus-width = <4>; +- cap-power-off-card; +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1283"; +- reg = <2>; +- interrupt-parent = <&gpio5>; +- interrupts = <24 IRQ_TYPE_EDGE_RISING>; /* gpio 152 */ +- ref-clock-frequency = <26000000>; +- tcxo-clock-frequency = <26000000>; +- }; +-}; +- +-&uart2 { +- /delete-property/dma-names; +- bluetooth { +- compatible = "ti,wl1283-st"; +- enable-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* gpio 162 */ +- max-speed = <3000000>; +- }; +-}; +- +-/* The DM3730 has a faster L3 than OMAP35, so increase pixel clock */ +-&mt9p031_out { +- pixel-clock-frequency = <90000000>; +-}; +- +-&omap3_pmx_core { +- mmc3_pins: pinmux_mm3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ +- OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ +- OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */ +- OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */ +- OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ +- OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr.gpio_157 */ +- >; +- }; +-}; +- +-&omap3_pmx_core2 { +- mmc3_core2_pins: pinmux_mmc3_core2_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ +- OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/logicpd-torpedo-baseboard.dtsi b/scripts/dtc/include-prefixes/arm/logicpd-torpedo-baseboard.dtsi +deleted file mode 100644 +index 533a47bc4a53..000000000000 +--- a/scripts/dtc/include-prefixes/arm/logicpd-torpedo-baseboard.dtsi ++++ /dev/null +@@ -1,381 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +- +-/ { +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_key_pins &gpio_key_pins_wkup>; +- +- sysboot2 { +- label = "sysboot2"; +- gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* gpio2 */ +- linux,code = ; +- wakeup-source; +- }; +- +- sysboot5 { +- label = "sysboot5"; +- gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; /* gpio7 */ +- linux,code = ; +- wakeup-source; +- }; +- +- gpio1 { +- label = "gpio1"; +- gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; /* gpio181 */ +- linux,code = ; +- wakeup-source; +- }; +- +- gpio2 { +- label = "gpio2"; +- gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; /* gpio178 */ +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- sound { +- compatible = "ti,omap-twl4030"; +- ti,model = "omap3logic"; +- ti,mcbsp = <&mcbsp2>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins>; +- +- led1 { +- label = "led1"; +- gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; /* gpio180 */ +- linux,default-trigger = "cpu0"; +- }; +- +- led2 { +- label = "led2"; +- gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; /* gpio179 */ +- linux,default-trigger = "none"; +- }; +- }; +- +- pwm10: dmtimer-pwm { +- compatible = "ti,omap-dmtimer-pwm"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm_pins>; +- ti,timers = <&timer10>; +- #pwm-cells = <3>; +- ti,clock-source = <0x01>; +- }; +- +-}; +- +-&vaux1 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +-}; +- +-&vaux4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +-}; +- +-&mcbsp2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp2_pins>; +- status = "okay"; +-}; +- +-&charger { +- ti,bb-uvolt = <3200000>; +- ti,bb-uamp = <150>; +-}; +- +-&gpmc { +- ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ +- 1 0 0x2c000000 0x1000000>; /* CS1: 16MB for LAN9221 */ +- +- ethernet@gpmc { +- pinctrl-names = "default"; +- pinctrl-0 = <&lan9221_pins>; +- interrupt-parent = <&gpio5>; +- interrupts = <1 IRQ_TYPE_LEVEL_LOW>; /* gpio129 */ +- reg = <1 0 0xff>; +- }; +-}; +- +-&hdqw1w { +- pinctrl-names = "default"; +- pinctrl-0 = <&hdq_pins>; +-}; +- +- +-&vpll2 { +- regulator-always-on; +-}; +- +-&dss { +- status = "okay"; +- vdds_dsi-supply = <&vpll2>; +- vdda_video-supply = <&vpll2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_dpi_pins1>; +- port { +- dpi_out: endpoint { +- remote-endpoint = <&lcd_in>; +- data-lines = <16>; +- }; +- }; +-}; +- +-/ { +- aliases { +- display0 = &lcd0; +- }; +- +- lcd0: display { +- /* This isn't the exact LCD, but the timings meet spec */ +- compatible = "newhaven,nhd-4.3-480272ef-atxl"; +- label = "15"; +- pinctrl-names = "default"; +- pinctrl-0 = <&panel_pwr_pins>; +- backlight = <&bl>; +- enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; +- port { +- lcd_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- }; +- +- bl: backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&backlight_pins>; +- pwms = <&pwm10 0 5000000 0>; +- brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; +- default-brightness-level = <7>; +- enable-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; /* gpio_154 */ +- }; +-}; +- +-&mmc1 { +- interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins &mmc1_cd>; +- cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio127 */ +- vmmc-supply = <&vmmc1>; +- bus-width = <4>; +- cap-power-off-card; +-}; +- +-&omap3_pmx_core { +- gpio_key_pins: pinmux_gpio_key_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_clk.gpio_178 */ +- OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_cs0.gpio_181 */ +- >; +- }; +- +- hdq_pins: hdq_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* hdq_sio */ +- >; +- }; +- +- pwm_pins: pinmux_pwm_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* gpmc_ncs5.gpt_10_pwm_evt */ +- >; +- }; +- +- led_pins: pinmux_led_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21d8, PIN_OUTPUT | MUX_MODE4) /* gpio_179 */ +- OMAP3_CORE1_IOPAD(0x21da, PIN_OUTPUT | MUX_MODE4) /* gpio_180 */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ +- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ +- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ +- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ +- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ +- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ +- >; +- }; +- +- tsc2004_pins: pinmux_tsc2004_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ +- >; +- }; +- +- backlight_pins: pinmux_backlight_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_dx.gpio_154 */ +- >; +- }; +- +- isp_pins: pinmux_isp_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE0) /* cam_hs.cam_hs */ +- OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT | MUX_MODE0) /* cam_vs.cam_vs */ +- OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE0) /* cam_xclka.cam_xclka */ +- OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE0) /* cam_pclk.cam_pclk */ +- +- OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0) /* cam_d0.cam_d0 */ +- OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0) /* cam_d1.cam_d1 */ +- OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE0) /* cam_d2.cam_d2 */ +- OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE0) /* cam_d3.cam_d3 */ +- OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE0) /* cam_d4.cam_d4 */ +- OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE0) /* cam_d5.cam_d5 */ +- OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6.cam_d6 */ +- OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7.cam_d7 */ +- >; +- }; +- +- panel_pwr_pins: pinmux_panel_pwr_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ +- >; +- }; +- +- dss_dpi_pins1: pinmux_dss_dpi_pins1 { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ +- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ +- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */ +- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */ +- +- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */ +- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */ +- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */ +- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */ +- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */ +- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */ +- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */ +- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */ +- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */ +- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */ +- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data16.dss_data16 */ +- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data17.dss_data17 */ +- +- OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data18.dss_data0 */ +- OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data19.dss_data1 */ +- OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data20.dss_data2 */ +- OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data21.dss_data3 */ +- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data22.dss_data4 */ +- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data23.dss_data5 */ +- >; +- }; +-}; +- +-&omap3_pmx_wkup { +- gpio_key_pins_wkup: pinmux_gpio_key_pins_wkup { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot0.gpio_2 */ +- OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot5.gpio_7 */ +- >; +- }; +- +- lan9221_pins: pinmux_lan9221_pins { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ +- >; +- }; +- +- mmc1_cd: pinmux_mmc1_cd { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_127 */ +- >; +- }; +-}; +- +-&i2c2 { +- mt9p031@48 { +- compatible = "aptina,mt9p031"; +- reg = <0x48>; +- clocks = <&isp 0>; +- vaa-supply = <&vaux4>; +- vdd-supply = <&vaux4>; +- vdd_io-supply = <&vaux4>; +- port { +- mt9p031_out: endpoint { +- input-clock-frequency = <24000000>; +- pixel-clock-frequency = <72000000>; +- remote-endpoint = <&ccdc_ep>; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- touchscreen: tsc2004@48 { +- compatible = "ti,tsc2004"; +- reg = <0x48>; +- vio-supply = <&vaux1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsc2004_pins>; +- interrupts-extended = <&gpio5 25 IRQ_TYPE_EDGE_RISING>; /* gpio 153 */ +- +- touchscreen-fuzz-x = <4>; +- touchscreen-fuzz-y = <7>; +- touchscreen-fuzz-pressure = <2>; +- touchscreen-size-x = <4096>; +- touchscreen-size-y = <4096>; +- touchscreen-max-pressure = <2048>; +- +- ti,x-plate-ohms = <280>; +- ti,esd-recovery-timeout-ms = <8000>; +- }; +-}; +- +-&mcspi1 { +- at25@0 { +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <5000000>; +- spi-cpha; +- spi-cpol; +- +- pagesize = <64>; +- size = <32768>; +- address-width = <16>; +- }; +-}; +- +-&isp { +- pinctrl-names = "default"; +- pinctrl-0 = <&isp_pins>; +- ports { +- port@0 { +- reg = <0>; +- ccdc_ep: endpoint { +- remote-endpoint = <&mt9p031_out>; +- bus-width = <8>; +- hsync-active = <1>; +- vsync-active = <1>; +- pclk-sample = <0>; +- }; +- }; +- }; +-}; +- +-&uart1 { +- interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; +-}; +- +-/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */ +-&usb_otg_hs { +- pinctrl-names = "default"; +- pinctrl-0 = <&hsusb_otg_pins>; +- interface-type = <0>; +- usb-phy = <&usb2_phy>; +- phys = <&usb2_phy>; +- phy-names = "usb2-phy"; +- mode = <3>; +- power = <50>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/logicpd-torpedo-som.dtsi b/scripts/dtc/include-prefixes/arm/logicpd-torpedo-som.dtsi +deleted file mode 100644 +index 3a5228562b0d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/logicpd-torpedo-som.dtsi ++++ /dev/null +@@ -1,203 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +- +-#include +- +-/ { +- chosen { +- stdout-path = &uart1; +- }; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&vcc>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- user0 { +- label = "user0"; +- gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ +- linux,default-trigger = "none"; +- }; +- }; +- +- /* fixed 26MHz oscillator */ +- hfclk_26m: oscillator { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- }; +-}; +- +-/* The Torpedo doesn't route the USB host pins */ +-&usbhshost { +- status = "disabled"; +-}; +- +-&gpmc { +- ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ +- +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- linux,mtd-name = "micron,mt29f4g16abbda3w"; +- nand-bus-width = <16>; +- ti,nand-ecc-opt = "bch8"; +- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- gpmc,device-width = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- clock-frequency = <2600000>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- interrupt-parent = <&intc>; +- clocks = <&hfclk_26m>; +- clock-names = "fck"; +- +- twl_audio: audio { +- compatible = "ti,twl4030-audio"; +- codec { +- }; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- clock-frequency = <400000>; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- clock-frequency = <400000>; +- at24@50 { +- compatible = "atmel,24c64"; +- readonly; +- reg = <0x50>; +- }; +-}; +- +-&omap3_pmx_core { +- mcbsp2_pins: pinmux_mcbsp2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ +- OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ +- OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ +- OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ +- >; +- }; +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ +- OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ +- OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ +- OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ +- OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ +- >; +- }; +- mcspi1_pins: pinmux_mcspi1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ +- OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ +- OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ +- OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ +- >; +- }; +- hsusb_otg_pins: pinmux_hsusb_otg_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ +- OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ +- OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ +- OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ +- +- OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ +- OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ +- OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ +- OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ +- OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ +- OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ +- OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ +- OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ +- >; +- }; +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ +- OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ +- >; +- }; +- i2c2_pins: pinmux_i2c2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ +- OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ +- >; +- }; +- i2c3_pins: pinmux_i2c3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ +- OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ +- >; +- }; +-}; +- +-&uart2 { +- interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +-}; +- +-&mcspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcspi1_pins>; +-}; +- +-#include "twl4030.dtsi" +-#include "twl4030_omap3.dtsi" +- +-&twl { +- twl_power: power { +- compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle"; +- ti,use_poweroff; +- }; +-}; +- +-&twl_gpio { +- ti,use-leds; +-}; +- +-&twl_keypad { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/lpc18xx.dtsi b/scripts/dtc/include-prefixes/arm/lpc18xx.dtsi +deleted file mode 100644 +index 10b8249b8ab6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/lpc18xx.dtsi ++++ /dev/null +@@ -1,537 +0,0 @@ +-/* +- * Common base for NXP LPC18xx and LPC43xx devices. +- * +- * Copyright 2015 Joachim Eastwood +- * +- * This code is released using a dual license strategy: BSD/GPL +- * You can choose the licence that better fits your requirements. +- * +- * Released under the terms of 3-clause BSD License +- * Released under the terms of GNU General Public License Version 2.0 +- * +- */ +- +-#include "armv7-m.dtsi" +- +-#include "dt-bindings/clock/lpc18xx-cgu.h" +-#include "dt-bindings/clock/lpc18xx-ccu.h" +- +-#define LPC_PIN(port, pin) (0x##port * 32 + pin) +-#define LPC_GPIO(port, pin) (port * 32 + pin) +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,cortex-m3"; +- device_type = "cpu"; +- reg = <0x0>; +- clocks = <&ccu1 CLK_CPU_CORE>; +- }; +- }; +- +- clocks { +- xtal: xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <12000000>; +- }; +- +- xtal32: xtal32 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- enet_rx_clk: enet_rx_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- clock-output-names = "enet_rx_clk"; +- }; +- +- enet_tx_clk: enet_tx_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- clock-output-names = "enet_tx_clk"; +- }; +- +- gp_clkin: gp_clkin { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- clock-output-names = "gp_clkin"; +- }; +- }; +- +- soc { +- sct_pwm: pwm@40000000 { +- compatible = "nxp,lpc1850-sct-pwm"; +- reg = <0x40000000 0x1000>; +- clocks =<&ccu1 CLK_CPU_SCT>; +- clock-names = "pwm"; +- resets = <&rgu 37>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- dmac: dma-controller@40002000 { +- compatible = "arm,pl080", "arm,primecell"; +- arm,primecell-periphid = <0x00041080>; +- reg = <0x40002000 0x1000>; +- interrupts = <2>; +- clocks = <&ccu1 CLK_CPU_DMA>; +- clock-names = "apb_pclk"; +- resets = <&rgu 19>; +- #dma-cells = <2>; +- dma-channels = <8>; +- dma-requests = <16>; +- lli-bus-interface-ahb1; +- lli-bus-interface-ahb2; +- mem-bus-interface-ahb1; +- mem-bus-interface-ahb2; +- memcpy-burst-size = <256>; +- memcpy-bus-width = <32>; +- }; +- +- spifi: flash-controller@40003000 { +- compatible = "nxp,lpc1773-spifi"; +- reg = <0x40003000 0x1000>, <0x14000000 0x4000000>; +- reg-names = "spifi", "flash"; +- interrupts = <30>; +- clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>; +- clock-names = "spifi", "reg"; +- resets = <&rgu 53>; +- status = "disabled"; +- }; +- +- mmcsd: mmcsd@40004000 { +- compatible = "snps,dw-mshc"; +- reg = <0x40004000 0x1000>; +- interrupts = <6>; +- clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>; +- clock-names = "ciu", "biu"; +- resets = <&rgu 20>; +- status = "disabled"; +- }; +- +- usb0: ehci@40006100 { +- compatible = "nxp,lpc1850-ehci", "generic-ehci"; +- reg = <0x40006100 0x100>; +- interrupts = <8>; +- clocks = <&ccu1 CLK_CPU_USB0>; +- resets = <&rgu 17>; +- phys = <&usb0_otg_phy>; +- phy-names = "usb"; +- has-transaction-translator; +- status = "disabled"; +- }; +- +- usb1: ehci@40007100 { +- compatible = "nxp,lpc1850-ehci", "generic-ehci"; +- reg = <0x40007100 0x100>; +- interrupts = <9>; +- clocks = <&ccu1 CLK_CPU_USB1>; +- resets = <&rgu 18>; +- status = "disabled"; +- }; +- +- emc: memory-controller@40005000 { +- compatible = "arm,pl172", "arm,primecell"; +- reg = <0x40005000 0x1000>; +- clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; +- clock-names = "mpmcclk", "apb_pclk"; +- resets = <&rgu 21>; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0 0x1c000000 0x1000000 +- 1 0 0x1d000000 0x1000000 +- 2 0 0x1e000000 0x1000000 +- 3 0 0x1f000000 0x1000000>; +- status = "disabled"; +- }; +- +- lcdc: lcd-controller@40008000 { +- compatible = "arm,pl111", "arm,primecell"; +- reg = <0x40008000 0x1000>; +- interrupts = <7>; +- interrupt-names = "combined"; +- clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>; +- clock-names = "clcdclk", "apb_pclk"; +- resets = <&rgu 16>; +- status = "disabled"; +- }; +- +- eeprom: eeprom@4000e000 { +- compatible = "nxp,lpc1857-eeprom"; +- reg = <0x4000e000 0x1000>, <0x20040000 0x4000>; +- reg-names = "reg", "mem"; +- clocks = <&ccu1 CLK_CPU_EEPROM>; +- clock-names = "eeprom"; +- resets = <&rgu 27>; +- interrupts = <4>; +- status = "disabled"; +- }; +- +- mac: ethernet@40010000 { +- compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; +- reg = <0x40010000 0x2000>; +- interrupts = <5>; +- interrupt-names = "macirq"; +- clocks = <&ccu1 CLK_CPU_ETHERNET>; +- clock-names = "stmmaceth"; +- resets = <&rgu 22>; +- reset-names = "stmmaceth"; +- rx-fifo-depth = <256>; +- tx-fifo-depth = <256>; +- snps,pbl = <4>; /* 32 (8x mode) */ +- snps,force_thresh_dma_mode; +- status = "disabled"; +- }; +- +- creg: syscon@40043000 { +- compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; +- reg = <0x40043000 0x1000>; +- clocks = <&ccu1 CLK_CPU_CREG>; +- resets = <&rgu 5>; +- +- creg_clk: clock-controller { +- compatible = "nxp,lpc1850-creg-clk"; +- clocks = <&xtal32>; +- #clock-cells = <1>; +- }; +- +- usb0_otg_phy: phy { +- compatible = "nxp,lpc1850-usb-otg-phy"; +- clocks = <&ccu1 CLK_USB0>; +- #phy-cells = <0>; +- }; +- +- dmamux: dma-mux { +- compatible = "nxp,lpc1850-dmamux"; +- #dma-cells = <3>; +- dma-requests = <64>; +- dma-masters = <&dmac>; +- }; +- }; +- +- rtc: rtc@40046000 { +- compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc"; +- reg = <0x40046000 0x1000>; +- interrupts = <47>; +- clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>; +- clock-names = "rtc", "reg"; +- }; +- +- cgu: clock-controller@40050000 { +- compatible = "nxp,lpc1850-cgu"; +- reg = <0x40050000 0x1000>; +- #clock-cells = <1>; +- clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; +- }; +- +- ccu1: clock-controller@40051000 { +- compatible = "nxp,lpc1850-ccu"; +- reg = <0x40051000 0x1000>; +- #clock-cells = <1>; +- clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, +- <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, +- <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, +- <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; +- clock-names = "base_apb3_clk", "base_apb1_clk", +- "base_spifi_clk", "base_cpu_clk", +- "base_periph_clk", "base_usb0_clk", +- "base_usb1_clk", "base_spi_clk"; +- }; +- +- ccu2: clock-controller@40052000 { +- compatible = "nxp,lpc1850-ccu"; +- reg = <0x40052000 0x1000>; +- #clock-cells = <1>; +- clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, +- <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, +- <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, +- <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; +- clock-names = "base_audio_clk", "base_uart3_clk", +- "base_uart2_clk", "base_uart1_clk", +- "base_uart0_clk", "base_ssp1_clk", +- "base_ssp0_clk", "base_sdio_clk"; +- }; +- +- rgu: reset-controller@40053000 { +- compatible = "nxp,lpc1850-rgu"; +- reg = <0x40053000 0x1000>; +- clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>; +- clock-names = "delay", "reg"; +- #reset-cells = <1>; +- }; +- +- watchdog@40080000 { +- compatible = "nxp,lpc1850-wwdt"; +- reg = <0x40080000 0x24>; +- interrupts = <49>; +- clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>; +- clock-names = "wdtclk", "reg"; +- }; +- +- uart0: serial@40081000 { +- compatible = "nxp,lpc1850-uart", "ns16550a"; +- reg = <0x40081000 0x1000>; +- reg-shift = <2>; +- interrupts = <24>; +- clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; +- clock-names = "uartclk", "reg"; +- resets = <&rgu 44>; +- dmas = <&dmamux 1 1 2 +- &dmamux 2 1 2 +- &dmamux 11 2 2 +- &dmamux 12 2 2>; +- dma-names = "tx", "rx", "tx", "rx"; +- status = "disabled"; +- }; +- +- uart1: serial@40082000 { +- compatible = "nxp,lpc1850-uart", "ns16550a"; +- reg = <0x40082000 0x1000>; +- reg-shift = <2>; +- interrupts = <25>; +- clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; +- clock-names = "uartclk", "reg"; +- resets = <&rgu 45>; +- dmas = <&dmamux 3 1 2 +- &dmamux 4 1 2>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- ssp0: spi@40083000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x40083000 0x1000>; +- interrupts = <22>; +- clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>; +- clock-names = "sspclk", "apb_pclk"; +- resets = <&rgu 50>; +- dmas = <&dmamux 9 0 2 +- &dmamux 10 0 2>; +- dma-names = "rx", "tx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- timer0: timer@40084000 { +- compatible = "nxp,lpc3220-timer"; +- reg = <0x40084000 0x1000>; +- interrupts = <12>; +- clocks = <&ccu1 CLK_CPU_TIMER0>; +- clock-names = "timerclk"; +- resets = <&rgu 32>; +- }; +- +- timer1: timer@40085000 { +- compatible = "nxp,lpc3220-timer"; +- reg = <0x40085000 0x1000>; +- interrupts = <13>; +- clocks = <&ccu1 CLK_CPU_TIMER1>; +- clock-names = "timerclk"; +- resets = <&rgu 33>; +- }; +- +- pinctrl: pinctrl@40086000 { +- compatible = "nxp,lpc1850-scu"; +- reg = <0x40086000 0x1000>; +- clocks = <&ccu1 CLK_CPU_SCU>; +- }; +- +- i2c0: i2c@400a1000 { +- compatible = "nxp,lpc1788-i2c"; +- reg = <0x400a1000 0x1000>; +- interrupts = <18>; +- clocks = <&ccu1 CLK_APB1_I2C0>; +- resets = <&rgu 48>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- can1: can@400a4000 { +- compatible = "bosch,c_can"; +- reg = <0x400a4000 0x1000>; +- interrupts = <43>; +- clocks = <&ccu1 CLK_APB1_CAN1>; +- resets = <&rgu 54>; +- status = "disabled"; +- }; +- +- uart2: serial@400c1000 { +- compatible = "nxp,lpc1850-uart", "ns16550a"; +- reg = <0x400c1000 0x1000>; +- reg-shift = <2>; +- interrupts = <26>; +- clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>; +- clock-names = "uartclk", "reg"; +- resets = <&rgu 46>; +- dmas = <&dmamux 5 1 2 +- &dmamux 6 1 2>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- uart3: serial@400c2000 { +- compatible = "nxp,lpc1850-uart", "ns16550a"; +- reg = <0x400c2000 0x1000>; +- reg-shift = <2>; +- interrupts = <27>; +- clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>; +- clock-names = "uartclk", "reg"; +- resets = <&rgu 47>; +- dmas = <&dmamux 7 1 2 +- &dmamux 8 1 2 +- &dmamux 13 3 2 +- &dmamux 14 3 2>; +- dma-names = "tx", "rx", "rx", "tx"; +- status = "disabled"; +- }; +- +- timer2: timer@400c3000 { +- compatible = "nxp,lpc3220-timer"; +- reg = <0x400c3000 0x1000>; +- interrupts = <14>; +- clocks = <&ccu1 CLK_CPU_TIMER2>; +- clock-names = "timerclk"; +- resets = <&rgu 34>; +- }; +- +- timer3: timer@400c4000 { +- compatible = "nxp,lpc3220-timer"; +- reg = <0x400c4000 0x1000>; +- interrupts = <15>; +- clocks = <&ccu1 CLK_CPU_TIMER3>; +- clock-names = "timerclk"; +- resets = <&rgu 35>; +- }; +- +- ssp1: spi@400c5000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x400c5000 0x1000>; +- interrupts = <23>; +- clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>; +- clock-names = "sspclk", "apb_pclk"; +- resets = <&rgu 51>; +- dmas = <&dmamux 11 2 2 +- &dmamux 12 2 2 +- &dmamux 3 3 2 +- &dmamux 4 3 2 +- &dmamux 5 2 2 +- &dmamux 6 2 2 +- &dmamux 13 2 2 +- &dmamux 14 2 2>; +- dma-names = "rx", "tx", "tx", "rx", +- "tx", "rx", "rx", "tx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@400e0000 { +- compatible = "nxp,lpc1788-i2c"; +- reg = <0x400e0000 0x1000>; +- interrupts = <19>; +- clocks = <&ccu1 CLK_APB3_I2C1>; +- resets = <&rgu 49>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- dac: dac@400e1000 { +- compatible = "nxp,lpc1850-dac"; +- reg = <0x400e1000 0x1000>; +- interrupts = <0>; +- clocks = <&ccu1 CLK_APB3_DAC>; +- resets = <&rgu 42>; +- status = "disabled"; +- }; +- +- can0: can@400e2000 { +- compatible = "bosch,c_can"; +- reg = <0x400e2000 0x1000>; +- interrupts = <51>; +- clocks = <&ccu1 CLK_APB3_CAN0>; +- resets = <&rgu 55>; +- status = "disabled"; +- }; +- +- adc0: adc@400e3000 { +- compatible = "nxp,lpc1850-adc"; +- reg = <0x400e3000 0x1000>; +- interrupts = <17>; +- clocks = <&ccu1 CLK_APB3_ADC0>; +- resets = <&rgu 40>; +- status = "disabled"; +- }; +- +- adc1: adc@400e4000 { +- compatible = "nxp,lpc1850-adc"; +- reg = <0x400e4000 0x1000>; +- interrupts = <21>; +- clocks = <&ccu1 CLK_APB3_ADC1>; +- resets = <&rgu 41>; +- status = "disabled"; +- }; +- +- gpio: gpio@400f4000 { +- compatible = "nxp,lpc1850-gpio"; +- reg = <0x400f4000 0x4000>; +- clocks = <&ccu1 CLK_CPU_GPIO>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, +- <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>, +- <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>, +- <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>, +- <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>, +- <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>, +- <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>, +- <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>, +- <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>, +- <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>, +- <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>, +- <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>, +- <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>, +- <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>, +- <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>, +- <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>, +- <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>, +- <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>, +- <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>, +- <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>, +- <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>, +- <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>, +- <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>, +- <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>, +- <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>, +- <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>, +- <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>, +- <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>, +- <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>, +- <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>, +- <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>, +- <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>, +- <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>, +- <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>, +- <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>, +- <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>, +- <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>, +- <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>, +- <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>, +- <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/lpc3250-ea3250.dts b/scripts/dtc/include-prefixes/arm/lpc3250-ea3250.dts +deleted file mode 100644 +index 63c6f17bb7c9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/lpc3250-ea3250.dts ++++ /dev/null +@@ -1,273 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Embedded Artists LPC3250 board +- * +- * Copyright 2012 Roland Stigge +- */ +- +-/dts-v1/; +-#include "lpc32xx.dtsi" +- +-/ { +- model = "Embedded Artists LPC3250 board based on NXP LPC3250"; +- compatible = "ea,ea3250", "nxp,lpc3250"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x4000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- +- button { +- label = "Interrupt Key"; +- linux,code = <103>; +- gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ +- }; +- +- key1 { +- label = "KEY1"; +- linux,code = <1>; +- gpios = <&pca9532 0 0>; +- }; +- +- key2 { +- label = "KEY2"; +- linux,code = <2>; +- gpios = <&pca9532 1 0>; +- }; +- +- key3 { +- label = "KEY3"; +- linux,code = <3>; +- gpios = <&pca9532 2 0>; +- }; +- +- key4 { +- label = "KEY4"; +- linux,code = <4>; +- gpios = <&pca9532 3 0>; +- }; +- +- joy0 { +- label = "Joystick Key 0"; +- linux,code = <10>; +- gpios = <&gpio 2 0 0>; /* P2.0 */ +- }; +- +- joy1 { +- label = "Joystick Key 1"; +- linux,code = <11>; +- gpios = <&gpio 2 1 0>; /* P2.1 */ +- }; +- +- joy2 { +- label = "Joystick Key 2"; +- linux,code = <12>; +- gpios = <&gpio 2 2 0>; /* P2.2 */ +- }; +- +- joy3 { +- label = "Joystick Key 3"; +- linux,code = <13>; +- gpios = <&gpio 2 3 0>; /* P2.3 */ +- }; +- +- joy4 { +- label = "Joystick Key 4"; +- linux,code = <14>; +- gpios = <&gpio 2 4 0>; /* P2.4 */ +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- /* LEDs on OEM Board */ +- +- led1 { +- gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */ +- linux,default-trigger = "timer"; +- default-state = "off"; +- }; +- +- led2 { +- gpios = <&gpio 2 10 1>; /* P2.10, active low */ +- default-state = "off"; +- }; +- +- led3 { +- gpios = <&gpio 2 11 1>; /* P2.11, active low */ +- default-state = "off"; +- }; +- +- led4 { +- gpios = <&gpio 2 12 1>; /* P2.12, active low */ +- default-state = "off"; +- }; +- +- /* LEDs on Base Board */ +- +- lede1 { +- gpios = <&pca9532 8 0>; +- default-state = "off"; +- }; +- lede2 { +- gpios = <&pca9532 9 0>; +- default-state = "off"; +- }; +- lede3 { +- gpios = <&pca9532 10 0>; +- default-state = "off"; +- }; +- lede4 { +- gpios = <&pca9532 11 0>; +- default-state = "off"; +- }; +- lede5 { +- gpios = <&pca9532 12 0>; +- default-state = "off"; +- }; +- lede6 { +- gpios = <&pca9532 13 0>; +- default-state = "off"; +- }; +- lede7 { +- gpios = <&pca9532 14 0>; +- default-state = "off"; +- }; +- lede8 { +- gpios = <&pca9532 15 0>; +- default-state = "off"; +- }; +- }; +-}; +- +-/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */ +-&adc { +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- +- uda1380: uda1380@18 { +- compatible = "nxp,uda1380"; +- reg = <0x18>; +- power-gpio = <&gpio 3 10 0>; +- reset-gpio = <&gpio 3 2 0>; +- dac-clk = "wspll"; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- }; +- +- eeprom@57 { +- compatible = "atmel,24c64"; +- reg = <0x57>; +- }; +- +- pca9532: pca9532@60 { +- compatible = "nxp,pca9532"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x60>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +-}; +- +-&i2cusb { +- clock-frequency = <100000>; +- +- isp1301: usb-transceiver@2d { +- compatible = "nxp,isp1301"; +- reg = <0x2d>; +- }; +-}; +- +-&mac { +- phy-mode = "rmii"; +- use-iram; +- status = "okay"; +-}; +- +-/* Here, choose exactly one from: ohci, usbd */ +-&ohci /* &usbd */ { +- transceiver = <&isp1301>; +- status = "okay"; +-}; +- +-&sd { +- wp-gpios = <&pca9532 5 0>; +- cd-gpios = <&pca9532 4 0>; +- cd-inverted; +- bus-width = <4>; +- status = "okay"; +-}; +- +-/* 128MB Flash via SLC NAND controller */ +-&slc { +- status = "okay"; +- +- nxp,wdr-clks = <14>; +- nxp,wwidth = <260000000>; +- nxp,whold = <104000000>; +- nxp,wsetup = <200000000>; +- nxp,rdr-clks = <14>; +- nxp,rwidth = <34666666>; +- nxp,rhold = <104000000>; +- nxp,rsetup = <200000000>; +- nand-on-flash-bbt; +- gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- mtd0@0 { +- label = "ea3250-boot"; +- reg = <0x00000000 0x00080000>; +- read-only; +- }; +- +- mtd1@80000 { +- label = "ea3250-uboot"; +- reg = <0x00080000 0x000c0000>; +- read-only; +- }; +- +- mtd2@140000 { +- label = "ea3250-kernel"; +- reg = <0x00140000 0x00400000>; +- }; +- +- mtd3@540000 { +- label = "ea3250-rootfs"; +- reg = <0x00540000 0x07ac0000>; +- }; +- }; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&uart6 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/lpc3250-phy3250.dts b/scripts/dtc/include-prefixes/arm/lpc3250-phy3250.dts +deleted file mode 100644 +index 21a6d0bca1e8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/lpc3250-phy3250.dts ++++ /dev/null +@@ -1,236 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * PHYTEC phyCORE-LPC3250 board +- * +- * Copyright (C) 2015-2019 Vladimir Zapolskiy +- * Copyright 2012 Roland Stigge +- */ +- +-/dts-v1/; +-#include "lpc32xx.dtsi" +- +-/ { +- model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250"; +- compatible = "phytec,phy3250", "nxp,lpc3250"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x4000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led0 { /* red */ +- gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */ +- default-state = "off"; +- }; +- +- led1 { /* green */ +- gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */ +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- panel: panel { +- compatible = "sharp,lq035q7db03"; +- power-supply = <®_lcd>; +- +- port { +- panel_input: endpoint { +- remote-endpoint = <&cldc_output>; +- }; +- }; +- }; +- +- reg_backlight: regulator-backlight { +- compatible = "regulator-fixed"; +- regulator-name = "backlight"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio 5 4 0>; +- enable-active-high; +- regulator-boot-on; +- }; +- +- reg_lcd: regulator-lcd { +- compatible = "regulator-fixed"; +- regulator-name = "lcd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio 5 0 0>; +- enable-active-high; +- regulator-boot-on; +- }; +- +- reg_sd: regulator-sd { +- compatible = "regulator-fixed"; +- regulator-name = "sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio 5 5 0>; +- enable-active-high; +- regulator-boot-on; +- }; +-}; +- +-&clcd { +- max-memory-bandwidth = <18710000>; +- status = "okay"; +- +- port { +- cldc_output: endpoint { +- remote-endpoint = <&panel_input>; +- arm,pl11x,tft-r0g0b0-pads = <0 8 16>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- +- uda1380: uda1380@18 { +- compatible = "nxp,uda1380"; +- reg = <0x18>; +- power-gpio = <&gpio 3 10 0>; +- reset-gpio = <&gpio 3 2 0>; +- dac-clk = "wspll"; +- }; +- +- pcf8563: rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +-}; +- +-&i2cusb { +- clock-frequency = <100000>; +- +- isp1301: usb-transceiver@2c { +- compatible = "nxp,isp1301"; +- reg = <0x2c>; +- }; +-}; +- +-&key { +- keypad,num-rows = <1>; +- keypad,num-columns = <1>; +- nxp,debounce-delay-ms = <3>; +- nxp,scan-delay-ms = <34>; +- linux,keymap = <0x00000002>; +- status = "okay"; +-}; +- +-&mac { +- phy-mode = "rmii"; +- use-iram; +- status = "okay"; +-}; +- +-/* Here, choose exactly one from: ohci, usbd */ +-&ohci /* &usbd */ { +- transceiver = <&isp1301>; +- status = "okay"; +-}; +- +-&sd { +- wp-gpios = <&gpio 3 0 0>; +- cd-gpios = <&gpio 3 1 0>; +- cd-inverted; +- bus-width = <4>; +- vmmc-supply = <®_sd>; +- status = "okay"; +-}; +- +-/* 64MB Flash via SLC NAND controller */ +-&slc { +- status = "okay"; +- +- nxp,wdr-clks = <14>; +- nxp,wwidth = <40000000>; +- nxp,whold = <100000000>; +- nxp,wsetup = <100000000>; +- nxp,rdr-clks = <14>; +- nxp,rwidth = <40000000>; +- nxp,rhold = <66666666>; +- nxp,rsetup = <100000000>; +- nand-on-flash-bbt; +- gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- mtd0@0 { +- label = "phy3250-boot"; +- reg = <0x00000000 0x00064000>; +- read-only; +- }; +- +- mtd1@64000 { +- label = "phy3250-uboot"; +- reg = <0x00064000 0x00190000>; +- read-only; +- }; +- +- mtd2@1f4000 { +- label = "phy3250-ubt-prms"; +- reg = <0x001f4000 0x00010000>; +- }; +- +- mtd3@204000 { +- label = "phy3250-kernel"; +- reg = <0x00204000 0x00400000>; +- }; +- +- mtd4@604000 { +- label = "phy3250-rootfs"; +- reg = <0x00604000 0x039fc000>; +- }; +- }; +-}; +- +-&ssp0 { +- num-cs = <1>; +- cs-gpios = <&gpio 3 5 0>; +- status = "okay"; +- +- eeprom: at25@0 { +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <5000000>; +- +- pl022,interface = <0>; +- pl022,com-mode = <0>; +- pl022,rx-level-trig = <1>; +- pl022,tx-level-trig = <1>; +- pl022,ctrl-len = <11>; +- pl022,wait-state = <0>; +- pl022,duplex = <0>; +- +- at25,byte-len = <0x8000>; +- at25,addr-mode = <2>; +- at25,page-size = <64>; +- }; +-}; +- +-&tsc { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&uart5 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/lpc32xx.dtsi b/scripts/dtc/include-prefixes/arm/lpc32xx.dtsi +deleted file mode 100644 +index c87066d6c995..000000000000 +--- a/scripts/dtc/include-prefixes/arm/lpc32xx.dtsi ++++ /dev/null +@@ -1,508 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * NXP LPC32xx SoC +- * +- * Copyright (C) 2015-2019 Vladimir Zapolskiy +- * Copyright 2012 Roland Stigge +- */ +- +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "nxp,lpc3220"; +- interrupt-parent = <&mic>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,arm926ej-s"; +- device_type = "cpu"; +- reg = <0x0>; +- }; +- }; +- +- clocks { +- xtal_32k: xtal_32k { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "xtal_32k"; +- }; +- +- xtal: xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <13000000>; +- clock-output-names = "xtal"; +- }; +- }; +- +- ahb { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0x00000000 0x00000000 0x10000000>, +- <0x20000000 0x20000000 0x30000000>, +- <0xe0000000 0xe0000000 0x04000000>; +- +- iram: sram@8000000 { +- compatible = "mmio-sram"; +- reg = <0x08000000 0x20000>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x08000000 0x20000>; +- }; +- +- /* +- * Enable either SLC or MLC +- */ +- slc: flash@20020000 { +- compatible = "nxp,lpc3220-slc"; +- reg = <0x20020000 0x1000>; +- clocks = <&clk LPC32XX_CLK_SLC>; +- status = "disabled"; +- }; +- +- mlc: flash@200a8000 { +- compatible = "nxp,lpc3220-mlc"; +- reg = <0x200a8000 0x11000>; +- interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk LPC32XX_CLK_MLC>; +- status = "disabled"; +- }; +- +- dma: dma@31000000 { +- compatible = "arm,pl080", "arm,primecell"; +- reg = <0x31000000 0x1000>; +- interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk LPC32XX_CLK_DMA>; +- clock-names = "apb_pclk"; +- }; +- +- usb { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0x0 0x31020000 0x00001000>; +- +- /* +- * Enable either ohci or usbd (gadget)! +- */ +- ohci: ohci@0 { +- compatible = "nxp,ohci-nxp", "usb-ohci"; +- reg = <0x0 0x300>; +- interrupt-parent = <&sic1>; +- interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&usbclk LPC32XX_USB_CLK_HOST>; +- status = "disabled"; +- }; +- +- usbd: usbd@0 { +- compatible = "nxp,lpc3220-udc"; +- reg = <0x0 0x300>; +- interrupt-parent = <&sic1>; +- interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, +- <30 IRQ_TYPE_LEVEL_HIGH>, +- <28 IRQ_TYPE_LEVEL_HIGH>, +- <26 IRQ_TYPE_LEVEL_LOW>; +- clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; +- status = "disabled"; +- }; +- +- i2cusb: i2c@300 { +- compatible = "nxp,pnx-i2c"; +- reg = <0x300 0x100>; +- interrupt-parent = <&sic1>; +- interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&usbclk LPC32XX_USB_CLK_I2C>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- usbclk: clock-controller@f00 { +- compatible = "nxp,lpc3220-usb-clk"; +- reg = <0xf00 0x100>; +- #clock-cells = <1>; +- }; +- }; +- +- clcd: clcd@31040000 { +- compatible = "arm,pl111", "arm,primecell"; +- reg = <0x31040000 0x1000>; +- interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>; +- clock-names = "clcdclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- mac: ethernet@31060000 { +- compatible = "nxp,lpc-eth"; +- reg = <0x31060000 0x1000>; +- interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk LPC32XX_CLK_MAC>; +- status = "disabled"; +- }; +- +- emc: memory-controller@31080000 { +- compatible = "arm,pl175", "arm,primecell"; +- reg = <0x31080000 0x1000>; +- clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>; +- clock-names = "mpmcclk", "apb_pclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0 0xe0000000 0x01000000>, +- <1 0xe1000000 0x01000000>, +- <2 0xe2000000 0x01000000>, +- <3 0xe3000000 0x01000000>; +- status = "disabled"; +- }; +- +- apb { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0x20000000 0x20000000 0x30000000>; +- +- /* +- * ssp0 and spi1 are shared pins; +- * enable one in your board dts, as needed. +- */ +- ssp0: spi@20084000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x20084000 0x1000>; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk LPC32XX_CLK_SSP0>; +- clock-names = "apb_pclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi1: spi@20088000 { +- compatible = "nxp,lpc3220-spi"; +- reg = <0x20088000 0x1000>; +- clocks = <&clk LPC32XX_CLK_SPI1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- /* +- * ssp1 and spi2 are shared pins; +- * enable one in your board dts, as needed. +- */ +- ssp1: spi@2008c000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x2008c000 0x1000>; +- interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk LPC32XX_CLK_SSP1>; +- clock-names = "apb_pclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi2: spi@20090000 { +- compatible = "nxp,lpc3220-spi"; +- reg = <0x20090000 0x1000>; +- clocks = <&clk LPC32XX_CLK_SPI2>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2s0: i2s@20094000 { +- compatible = "nxp,lpc3220-i2s"; +- reg = <0x20094000 0x1000>; +- status = "disabled"; +- }; +- +- sd: sd@20098000 { +- compatible = "arm,pl18x", "arm,primecell"; +- reg = <0x20098000 0x1000>; +- interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, +- <13 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk LPC32XX_CLK_SD>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- i2s1: i2s@2009c000 { +- compatible = "nxp,lpc3220-i2s"; +- reg = <0x2009c000 0x1000>; +- status = "disabled"; +- }; +- +- /* UART5 first since it is the default console, ttyS0 */ +- uart5: serial@40090000 { +- /* actually, ns16550a w/ 64 byte fifos! */ +- compatible = "nxp,lpc3220-uart"; +- reg = <0x40090000 0x1000>; +- interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; +- reg-shift = <2>; +- clocks = <&clk LPC32XX_CLK_UART5>; +- status = "disabled"; +- }; +- +- uart3: serial@40080000 { +- compatible = "nxp,lpc3220-uart"; +- reg = <0x40080000 0x1000>; +- interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; +- reg-shift = <2>; +- clocks = <&clk LPC32XX_CLK_UART3>; +- status = "disabled"; +- }; +- +- uart4: serial@40088000 { +- compatible = "nxp,lpc3220-uart"; +- reg = <0x40088000 0x1000>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; +- reg-shift = <2>; +- clocks = <&clk LPC32XX_CLK_UART4>; +- status = "disabled"; +- }; +- +- uart6: serial@40098000 { +- compatible = "nxp,lpc3220-uart"; +- reg = <0x40098000 0x1000>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; +- reg-shift = <2>; +- clocks = <&clk LPC32XX_CLK_UART6>; +- status = "disabled"; +- }; +- +- i2c1: i2c@400a0000 { +- compatible = "nxp,pnx-i2c"; +- reg = <0x400a0000 0x100>; +- interrupt-parent = <&sic1>; +- interrupts = <19 IRQ_TYPE_LEVEL_LOW>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clk LPC32XX_CLK_I2C1>; +- }; +- +- i2c2: i2c@400a8000 { +- compatible = "nxp,pnx-i2c"; +- reg = <0x400a8000 0x100>; +- interrupt-parent = <&sic1>; +- interrupts = <18 IRQ_TYPE_LEVEL_LOW>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clk LPC32XX_CLK_I2C2>; +- }; +- +- mpwm: mpwm@400e8000 { +- compatible = "nxp,lpc3220-motor-pwm"; +- reg = <0x400e8000 0x78>; +- status = "disabled"; +- #pwm-cells = <2>; +- }; +- }; +- +- fab { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0x20000000 0x20000000 0x30000000>; +- +- /* System Control Block */ +- scb { +- compatible = "simple-bus"; +- ranges = <0x0 0x040004000 0x00001000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- clk: clock-controller@0 { +- compatible = "nxp,lpc3220-clk"; +- reg = <0x00 0x114>; +- #clock-cells = <1>; +- +- clocks = <&xtal_32k>, <&xtal>; +- clock-names = "xtal_32k", "xtal"; +- }; +- }; +- +- mic: interrupt-controller@40008000 { +- compatible = "nxp,lpc3220-mic"; +- reg = <0x40008000 0x4000>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- sic1: interrupt-controller@4000c000 { +- compatible = "nxp,lpc3220-sic"; +- reg = <0x4000c000 0x4000>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&mic>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>, +- <30 IRQ_TYPE_LEVEL_LOW>; +- }; +- +- sic2: interrupt-controller@40010000 { +- compatible = "nxp,lpc3220-sic"; +- reg = <0x40010000 0x4000>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&mic>; +- interrupts = <1 IRQ_TYPE_LEVEL_LOW>, +- <31 IRQ_TYPE_LEVEL_LOW>; +- }; +- +- uart1: serial@40014000 { +- compatible = "nxp,lpc3220-hsuart"; +- reg = <0x40014000 0x1000>; +- interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +- +- uart2: serial@40018000 { +- compatible = "nxp,lpc3220-hsuart"; +- reg = <0x40018000 0x1000>; +- interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +- +- uart7: serial@4001c000 { +- compatible = "nxp,lpc3220-hsuart"; +- reg = <0x4001c000 0x1000>; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +- +- rtc: rtc@40024000 { +- compatible = "nxp,lpc3220-rtc"; +- reg = <0x40024000 0x1000>; +- interrupt-parent = <&sic1>; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk LPC32XX_CLK_RTC>; +- }; +- +- gpio: gpio@40028000 { +- compatible = "nxp,lpc3220-gpio"; +- reg = <0x40028000 0x1000>; +- gpio-controller; +- #gpio-cells = <3>; /* bank, pin, flags */ +- }; +- +- timer4: timer@4002c000 { +- compatible = "nxp,lpc3220-timer"; +- reg = <0x4002c000 0x1000>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- clocks = <&clk LPC32XX_CLK_TIMER4>; +- clock-names = "timerclk"; +- status = "disabled"; +- }; +- +- timer5: timer@40030000 { +- compatible = "nxp,lpc3220-timer"; +- reg = <0x40030000 0x1000>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- clocks = <&clk LPC32XX_CLK_TIMER5>; +- clock-names = "timerclk"; +- status = "disabled"; +- }; +- +- watchdog: watchdog@4003c000 { +- compatible = "nxp,pnx4008-wdt"; +- reg = <0x4003c000 0x1000>; +- clocks = <&clk LPC32XX_CLK_WDOG>; +- }; +- +- timer0: timer@40044000 { +- compatible = "nxp,lpc3220-timer"; +- reg = <0x40044000 0x1000>; +- clocks = <&clk LPC32XX_CLK_TIMER0>; +- clock-names = "timerclk"; +- interrupts = <16 IRQ_TYPE_LEVEL_LOW>; +- }; +- +- /* +- * TSC vs. ADC: Since those two share the same +- * hardware, you need to choose from one of the +- * following two and do 'status = "okay";' for one of +- * them +- */ +- +- adc: adc@40048000 { +- compatible = "nxp,lpc3220-adc"; +- reg = <0x40048000 0x1000>; +- interrupt-parent = <&sic1>; +- interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk LPC32XX_CLK_ADC>; +- status = "disabled"; +- }; +- +- tsc: tsc@40048000 { +- compatible = "nxp,lpc3220-tsc"; +- reg = <0x40048000 0x1000>; +- interrupt-parent = <&sic1>; +- interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk LPC32XX_CLK_ADC>; +- status = "disabled"; +- }; +- +- timer1: timer@4004c000 { +- compatible = "nxp,lpc3220-timer"; +- reg = <0x4004c000 0x1000>; +- interrupts = <17 IRQ_TYPE_LEVEL_LOW>; +- clocks = <&clk LPC32XX_CLK_TIMER1>; +- clock-names = "timerclk"; +- }; +- +- key: key@40050000 { +- compatible = "nxp,lpc3220-key"; +- reg = <0x40050000 0x1000>; +- clocks = <&clk LPC32XX_CLK_KEY>; +- interrupt-parent = <&sic1>; +- interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +- +- timer2: timer@40058000 { +- compatible = "nxp,lpc3220-timer"; +- reg = <0x40058000 0x1000>; +- interrupts = <18 IRQ_TYPE_LEVEL_LOW>; +- clocks = <&clk LPC32XX_CLK_TIMER2>; +- clock-names = "timerclk"; +- status = "disabled"; +- }; +- +- pwm1: pwm@4005c000 { +- compatible = "nxp,lpc3220-pwm"; +- reg = <0x4005c000 0x4>; +- clocks = <&clk LPC32XX_CLK_PWM1>; +- assigned-clocks = <&clk LPC32XX_CLK_PWM1>; +- assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; +- status = "disabled"; +- }; +- +- pwm2: pwm@4005c004 { +- compatible = "nxp,lpc3220-pwm"; +- reg = <0x4005c004 0x4>; +- clocks = <&clk LPC32XX_CLK_PWM2>; +- assigned-clocks = <&clk LPC32XX_CLK_PWM2>; +- assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; +- status = "disabled"; +- }; +- +- timer3: timer@40060000 { +- compatible = "nxp,lpc3220-timer"; +- reg = <0x40060000 0x1000>; +- interrupts = <19 IRQ_TYPE_LEVEL_LOW>; +- clocks = <&clk LPC32XX_CLK_TIMER3>; +- clock-names = "timerclk"; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/lpc4337-ciaa.dts b/scripts/dtc/include-prefixes/arm/lpc4337-ciaa.dts +deleted file mode 100644 +index beddaba85393..000000000000 +--- a/scripts/dtc/include-prefixes/arm/lpc4337-ciaa.dts ++++ /dev/null +@@ -1,221 +0,0 @@ +-/* +- * CIAA NXP LPC4337 (http://www.proyecto-ciaa.com.ar) +- * +- * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar +- * +- * This code is released using a dual license strategy: BSD/GPL +- * You can choose the licence that better fits your requirements. +- * +- * Released under the terms of 3-clause BSD License +- * Released under the terms of GNU General Public License Version 2.0 +- */ +-/dts-v1/; +- +-#include "lpc18xx.dtsi" +-#include "lpc4357.dtsi" +- +-#include "dt-bindings/gpio/gpio.h" +- +-/ { +- model = "CIAA NXP LPC4337"; +- compatible = "ciaa,lpc4337", "nxp,lpc4337", "nxp,lpc4350"; +- +- aliases { +- serial0 = &uart2; +- serial1 = &uart3; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200 earlyprintk"; +- stdout-path = &uart2; +- }; +- +- memory@28000000 { +- device_type = "memory"; +- reg = <0x28000000 0x0800000>; /* 8 MB */ +- }; +-}; +- +-&pinctrl { +- enet_rmii_pins: enet-rmii-pins { +- enet_rmii_rxd_cfg { +- pins = "p1_15", "p0_0"; +- function = "enet"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- enet_rmii_txd_cfg { +- pins = "p1_18", "p1_20"; +- function = "enet"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- enet_rmii_rx_dv_cfg { +- pins = "p1_16"; +- function = "enet"; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- enet_rmii_tx_en_cfg { +- pins = "p0_1"; +- function = "enet"; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- enet_ref_clk_cfg { +- pins = "p1_19"; +- function = "enet"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- enet_mdio_cfg { +- pins = "p1_17"; +- function = "enet"; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- enet_mdc_cfg { +- pins = "p7_7"; +- function = "enet"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- }; +- +- i2c0_pins: i2c0-pins { +- i2c0_pins_cfg { +- pins = "i2c0_scl", "i2c0_sda"; +- function = "i2c0"; +- input-enable; +- }; +- }; +- +- ssp_pins: ssp-pins { +- ssp1_cs { +- pins = "p6_7"; +- function = "gpio"; +- bias-pull-up; +- bias-disable; +- }; +- +- ssp1_miso_mosi { +- pins = "p1_3", "p1_4"; +- function = "ssp1"; +- slew-rate = <1>; +- bias-pull-down; +- input-enable; +- input-schmitt-disable; +- }; +- +- ssp1_sck { +- pins = "pf_4"; +- function = "ssp1"; +- slew-rate = <1>; +- bias-disable; +- }; +- }; +- +- uart2_pins: uart2-pins { +- uart2_rx_cfg { +- pins = "p7_2"; +- function = "uart2"; +- bias-disable; +- input-enable; +- }; +- +- uart2_tx_cfg { +- pins = "p7_1"; +- function = "uart2"; +- bias-disable; +- }; +- }; +- +- uart3_pins: uart3-pins { +- uart3_rx_cfg { +- pins = "p2_4"; +- function = "uart3"; +- bias-disable; +- input-enable; +- }; +- +- uart3_tx_cfg { +- pins = "p2_3"; +- function = "uart3"; +- bias-disable; +- }; +- }; +-}; +- +-&enet_tx_clk { +- clock-frequency = <50000000>; +-}; +- +-&i2c0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- clock-frequency = <400000>; +- +- eeprom@50 { +- compatible = "microchip,24c512", "atmel,24c512"; +- reg = <0x50>; +- }; +- +- eeprom@51 { +- compatible = "microchip,24c02", "atmel,24c02"; +- reg = <0x51>; +- }; +- +- eeprom@54 { +- compatible = "microchip,24c512", "atmel,24c512"; +- reg = <0x54>; +- }; +-}; +- +-&mac { +- status = "okay"; +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&enet_rmii_pins>; +-}; +- +-&sct_pwm { +- status = "okay"; +-}; +- +-&ssp1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ssp_pins>; +- cs-gpios = <&gpio LPC_GPIO(5,15) GPIO_ACTIVE_HIGH>; +- num-cs = <1>; +-}; +- +-&uart2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +-}; +- +-&uart3 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/lpc4350-hitex-eval.dts b/scripts/dtc/include-prefixes/arm/lpc4350-hitex-eval.dts +deleted file mode 100644 +index 93d0c2e99e7c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/lpc4350-hitex-eval.dts ++++ /dev/null +@@ -1,481 +0,0 @@ +-/* +- * Hitex LPC4350 Evaluation Board +- * +- * Copyright 2015 Ariel D'Alessandro +- * +- * This code is released using a dual license strategy: BSD/GPL +- * You can choose the licence that better fits your requirements. +- * +- * Released under the terms of 3-clause BSD License +- * Released under the terms of GNU General Public License Version 2.0 +- * +- */ +-/dts-v1/; +- +-#include "lpc18xx.dtsi" +-#include "lpc4350.dtsi" +- +-#include "dt-bindings/input/input.h" +-#include "dt-bindings/gpio/gpio.h" +- +-/ { +- model = "Hitex LPC4350 Evaluation Board"; +- compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- }; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- memory@28000000 { +- device_type = "memory"; +- reg = <0x28000000 0x800000>; /* 8 MB */ +- }; +- +- pca_buttons { +- compatible = "gpio-keys-polled"; +- poll-interval = <100>; +- autorepeat; +- +- button0 { +- label = "joy:right"; +- linux,code = ; +- gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>; +- }; +- +- button1 { +- label = "joy:up"; +- linux,code = ; +- gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>; +- }; +- +- +- button2 { +- label = "joy:enter"; +- linux,code = ; +- gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>; +- }; +- +- button3 { +- label = "joy:left"; +- linux,code = ; +- gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>; +- }; +- +- button4 { +- label = "joy:down"; +- linux,code = ; +- gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>; +- }; +- +- button5 { +- label = "user:sw3"; +- linux,code = ; +- gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>; +- }; +- +- button6 { +- label = "user:sw4"; +- linux,code = ; +- gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>; +- }; +- +- button7 { +- label = "user:sw5"; +- linux,code = ; +- gpios = <&pca_gpio 15 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- pca_leds { +- compatible = "gpio-leds"; +- +- led0 { +- label = "ext:led0"; +- gpios = <&pca_gpio 0 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led1 { +- label = "ext:led1"; +- gpios = <&pca_gpio 1 GPIO_ACTIVE_LOW>; +- }; +- +- led2 { +- label = "ext:led2"; +- gpios = <&pca_gpio 2 GPIO_ACTIVE_LOW>; +- }; +- +- led3 { +- label = "ext:led3"; +- gpios = <&pca_gpio 3 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- vcc: vcc_fixed { +- compatible = "regulator-fixed"; +- regulator-name = "3v3io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&pinctrl { +- adc1_pins: adc1-pins { +- adc1_pins_cfg { +- pins = "pf_9"; +- function = "adc"; +- input-disable; +- bias-disable; +- }; +- }; +- +- emc_pins: emc-pins { +- emc_addr0_23_cfg { +- pins = "p2_9", "p2_10", "p2_11", "p2_12", +- "p2_13", "p1_0", "p1_1", "p1_2", +- "p2_8", "p2_7", "p2_6", "p2_2", +- "p2_1", "p2_0", "p6_8", "p6_7", +- "pd_16", "pd_15", "pe_0", "pe_1", +- "pe_2", "pe_3", "pe_4", "pa_4"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- emc_data0_15_cfg { +- pins = "p1_7", "p1_8", "p1_9", "p1_10", +- "p1_11", "p1_12", "p1_13", "p1_14", +- "p5_4", "p5_5", "p5_6", "p5_7", +- "p5_0", "p5_1", "p5_2", "p5_3"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- emc_we_oe_cfg { +- pins = "p1_6", "p1_3"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- emc_bls0_3_cfg { +- pins = "p1_4", "p6_6", "pd_13", "pd_10"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- emc_cs0_cs2_cfg { +- pins = "p1_5", "pd_12"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- emc_sdram_dqm0_3_cfg { +- pins = "p6_12", "p6_10", "pd_0", "pe_13"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- emc_sdram_ras_cas_cfg { +- pins = "p6_5", "p6_4"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- emc_sdram_dycs0_cfg { +- pins = "p6_9"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- emc_sdram_cke_cfg { +- pins = "p6_11"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- emc_sdram_clock_cfg { +- pins = "clk0", "clk1", "clk2", "clk3"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- }; +- +- enet_mii_pins: enet-mii-pins { +- enet_mii_rxd0_3_cfg { +- pins = "p1_15", "p0_0", "p9_3", "p9_2"; +- function = "enet"; +- bias-disable; +- input-enable; +- }; +- +- enet_mii_txd0_3_cfg { +- pins = "p1_18", "p1_20", "p9_4", "p9_5"; +- function = "enet"; +- bias-disable; +- }; +- +- enet_mii_crs_col_cfg { +- pins = "p9_0", "p9_6"; +- function = "enet"; +- bias-disable; +- input-enable; +- }; +- +- enet_mii_rx_clk_dv_er_cfg { +- pins = "pc_0", "p1_16", "p9_1"; +- function = "enet"; +- bias-disable; +- input-enable; +- }; +- +- enet_mii_tx_clk_en_cfg { +- pins = "p1_19", "p0_1"; +- function = "enet"; +- bias-disable; +- input-enable; +- }; +- +- enet_mdio_cfg { +- pins = "p1_17"; +- function = "enet"; +- bias-disable; +- input-enable; +- }; +- +- enet_mdc_cfg { +- pins = "pc_1"; +- function = "enet"; +- bias-disable; +- }; +- }; +- +- i2c0_pins: i2c0-pins { +- i2c0_pins_cfg { +- pins = "i2c0_scl", "i2c0_sda"; +- function = "i2c0"; +- input-enable; +- }; +- }; +- +- spifi_pins: spifi-pins { +- spifi_clk_cfg { +- pins = "p3_3"; +- function = "spifi"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- spifi_mosi_miso_sio2_3_cfg { +- pins = "p3_7", "p3_6", "p3_5", "p3_4"; +- function = "spifi"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- spifi_cs_cfg { +- pins = "p3_8"; +- function = "spifi"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- }; +- +- uart0_pins: uart0-pins { +- uart0_rx_cfg { +- pins = "pf_11"; +- function = "uart0"; +- input-schmitt-disable; +- bias-disable; +- input-enable; +- }; +- +- uart0_tx_cfg { +- pins = "pf_10"; +- function = "uart0"; +- bias-pull-down; +- }; +- }; +-}; +- +-&adc1 { +- status = "okay"; +- vref-supply = <&vcc>; +- pinctrl-names = "default"; +- pinctrl-0 = <&adc1_pins>; +-}; +- +-&emc { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&emc_pins>; +- +- cs0 { +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- +- mpmc,cs = <0>; +- mpmc,memory-width = <16>; +- mpmc,byte-lane-low; +- mpmc,write-enable-delay = <0>; +- mpmc,output-enable-delay = <0>; +- mpmc,read-access-delay = <70>; +- mpmc,page-mode-read-delay = <70>; +- +- flash@0,0 { +- compatible = "sst,sst39vf320", "cfi-flash"; +- reg = <0 0 0x400000>; +- bank-width = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "bootloader"; +- reg = <0x000000 0x040000>; /* 256 KiB */ +- }; +- +- partition@1 { +- label = "kernel"; +- reg = <0x040000 0x2C0000>; /* 2.75 MiB */ +- }; +- +- partition@2 { +- label = "rootfs"; +- reg = <0x300000 0x100000>; /* 1 MiB */ +- }; +- }; +- }; +- +- cs2 { +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- +- mpmc,cs = <2>; +- mpmc,memory-width = <16>; +- mpmc,byte-lane-low; +- mpmc,write-enable-delay = <0>; +- mpmc,output-enable-delay = <30>; +- mpmc,read-access-delay = <90>; +- mpmc,page-mode-read-delay = <55>; +- mpmc,write-access-delay = <55>; +- mpmc,turn-round-delay = <55>; +- +- ext_sram: sram@2,0 { +- compatible = "mmio-sram"; +- reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */ +- }; +- }; +-}; +- +-&enet_tx_clk { +- clock-frequency = <25000000>; +-}; +- +-&i2c0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- clock-frequency = <400000>; +- +- /* NXP SE97BTP with temperature sensor + eeprom */ +- sensor@18 { +- compatible = "nxp,se97", "jedec,jc-42.4-temp"; +- reg = <0x18>; +- }; +- +- eeprom@50 { +- compatible = "nxp,24c02", "atmel,24c02"; +- reg = <0x50>; +- }; +- +- pca_gpio: gpio@24 { +- compatible = "nxp,pca9673"; +- reg = <0x24>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&mac { +- status = "okay"; +- phy-mode = "mii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&enet_mii_pins>; +-}; +- +-&spifi { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spifi_pins>; +- +- flash { +- compatible = "jedec,spi-nor"; +- spi-rx-bus-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "bootloader"; +- reg = <0x000000 0x040000>; /* 256 KiB */ +- }; +- +- partition@1 { +- label = "kernel"; +- reg = <0x040000 0x2c0000>; /* 2.75 MiB */ +- }; +- +- partition@2 { +- label = "rootfs"; +- reg = <0x300000 0x500000>; /* 5 MiB */ +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/lpc4350.dtsi b/scripts/dtc/include-prefixes/arm/lpc4350.dtsi +deleted file mode 100644 +index c4422f587055..000000000000 +--- a/scripts/dtc/include-prefixes/arm/lpc4350.dtsi ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* +- * NXP LPC4350 and LPC4330 SoC +- * +- * Copyright 2015 Ariel D'Alessandro +- * +- * This code is released using a dual license strategy: BSD/GPL +- * You can choose the licence that better fits your requirements. +- * +- * Released under the terms of 3-clause BSD License +- * Released under the terms of GNU General Public License Version 2.0 +- * +- */ +- +-/ { +- compatible = "nxp,lpc4350", "nxp,lpc4330"; +- +- cpus { +- cpu@0 { +- compatible = "arm,cortex-m4"; +- }; +- }; +- +- soc { +- sram0: sram@10000000 { +- compatible = "mmio-sram"; +- reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */ +- }; +- +- sram1: sram@10080000 { +- compatible = "mmio-sram"; +- reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */ +- }; +- +- sram2: sram@20000000 { +- compatible = "mmio-sram"; +- reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/lpc4357-ea4357-devkit.dts b/scripts/dtc/include-prefixes/arm/lpc4357-ea4357-devkit.dts +deleted file mode 100644 +index 224f80a4a31d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/lpc4357-ea4357-devkit.dts ++++ /dev/null +@@ -1,623 +0,0 @@ +-/* +- * Embedded Artist LPC4357 Developer's Kit +- * +- * Copyright 2015 Joachim Eastwood +- * +- * This code is released using a dual license strategy: BSD/GPL +- * You can choose the licence that better fits your requirements. +- * +- * Released under the terms of 3-clause BSD License +- * Released under the terms of GNU General Public License Version 2.0 +- * +- */ +-/dts-v1/; +- +-#include "lpc18xx.dtsi" +-#include "lpc4357.dtsi" +- +-#include "dt-bindings/input/input.h" +-#include "dt-bindings/gpio/gpio.h" +- +-/ { +- model = "Embedded Artists' LPC4357 Developer's Kit"; +- compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- }; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- memory@28000000 { +- device_type = "memory"; +- reg = <0x28000000 0x2000000>; /* 32 MB */ +- }; +- +- vcc: vcc_fixed { +- compatible = "regulator-fixed"; +- regulator-name = "3v3-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- /* vmmc is controlled by sdmmc host internally */ +- vmmc: vmmc_fixed { +- compatible = "regulator-fixed"; +- regulator-name = "vmmc-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- gpio_joystick { +- compatible = "gpio-keys-polled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_joystick_pins>; +- poll-interval = <100>; +- autorepeat; +- +- button0 { +- label = "joy_enter"; +- linux,code = ; +- gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>; +- }; +- +- button1 { +- label = "joy_left"; +- linux,code = ; +- gpios = <&gpio LPC_GPIO(4,9) GPIO_ACTIVE_LOW>; +- }; +- +- button2 { +- label = "joy_up"; +- linux,code = ; +- gpios = <&gpio LPC_GPIO(4,10) GPIO_ACTIVE_LOW>; +- }; +- +- button3 { +- label = "joy_right"; +- linux,code = ; +- gpios = <&gpio LPC_GPIO(4,12) GPIO_ACTIVE_LOW>; +- }; +- +- button4 { +- label = "joy_down"; +- linux,code = ; +- gpios = <&gpio LPC_GPIO(4,13) GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds_mmio { +- compatible = "gpio-leds"; +- +- led1 { +- gpios = <&mmio_leds 15 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led2 { +- gpios = <&mmio_leds 14 GPIO_ACTIVE_HIGH>; +- }; +- +- led3 { +- gpios = <&mmio_leds 13 GPIO_ACTIVE_HIGH>; +- }; +- +- led4 { +- gpios = <&mmio_leds 12 GPIO_ACTIVE_HIGH>; +- }; +- +- led5 { +- gpios = <&mmio_leds 11 GPIO_ACTIVE_HIGH>; +- }; +- +- led6 { +- gpios = <&mmio_leds 10 GPIO_ACTIVE_HIGH>; +- }; +- +- led7 { +- gpios = <&mmio_leds 9 GPIO_ACTIVE_HIGH>; +- }; +- +- led8 { +- gpios = <&mmio_leds 8 GPIO_ACTIVE_HIGH>; +- }; +- +- led9 { +- gpios = <&mmio_leds 7 GPIO_ACTIVE_HIGH>; +- }; +- +- led10 { +- gpios = <&mmio_leds 6 GPIO_ACTIVE_HIGH>; +- }; +- +- led11 { +- gpios = <&mmio_leds 5 GPIO_ACTIVE_HIGH>; +- }; +- +- led12 { +- gpios = <&mmio_leds 4 GPIO_ACTIVE_HIGH>; +- }; +- +- led13 { +- gpios = <&mmio_leds 3 GPIO_ACTIVE_HIGH>; +- }; +- +- led14 { +- gpios = <&mmio_leds 2 GPIO_ACTIVE_HIGH>; +- }; +- +- led15 { +- gpios = <&mmio_leds 1 GPIO_ACTIVE_HIGH>; +- }; +- +- led16 { +- gpios = <&mmio_leds 0 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&pinctrl { +- emc_pins: emc-pins { +- emc_addr0_23_cfg { +- pins = "p2_9", "p2_10", "p2_11", "p2_12", +- "p2_13", "p1_0", "p1_1", "p1_2", +- "p2_8", "p2_7", "p2_6", "p2_2", +- "p2_1", "p2_0", "p6_8", "p6_7", +- "pd_16", "pd_15", "pe_0", "pe_1", +- "pe_2", "pe_3", "pe_4", "pa_4"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- emc_data0_31_cfg { +- pins = "p1_7", "p1_8", "p1_9", "p1_10", +- "p1_11", "p1_12", "p1_13", "p1_14", +- "p5_4", "p5_5", "p5_6", "p5_7", +- "p5_0", "p5_1", "p5_2", "p5_3", +- "pd_2", "pd_3", "pd_4", "pd_5", +- "pd_6", "pd_7", "pd_8", "pd_9", +- "pe_5", "pe_6", "pe_7", "pe_8", +- "pe_9", "pe_10", "pe_11", "pe_12"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- emc_we_oe_cfg { +- pins = "p1_6", "p1_3"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- emc_bls0_3_cfg { +- pins = "p1_4", "p6_6", "pd_13", "pd_10"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- emc_cs0_3_cfg { +- pins = "p1_5", "p6_3", "pd_12", "pd_11"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- emc_sdram_dqm0_3_cfg { +- pins = "p6_12", "p6_10", "pd_0", "pe_13"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- emc_sdram_ras_cas_cfg { +- pins = "p6_5", "p6_4"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- emc_sdram_dycs0_cfg { +- pins = "p6_9"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- emc_sdram_cke_cfg { +- pins = "p6_11"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- emc_sdram_clock_cfg { +- pins = "clk0", "clk1", "clk2", "clk3"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- }; +- +- enet_rmii_pins: enet-rmii-pins { +- enet_rmii_rxd_cfg { +- pins = "p1_15", "p0_0"; +- function = "enet"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- enet_rmii_txd_cfg { +- pins = "p1_18", "p1_20"; +- function = "enet"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- enet_rmii_rx_dv_cfg { +- pins = "p1_16"; +- function = "enet"; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- enet_rmii_tx_en_cfg { +- pins = "p0_1"; +- function = "enet"; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- enet_ref_clk_cfg { +- pins = "p1_19"; +- function = "enet"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- enet_mdio_cfg { +- pins = "p1_17"; +- function = "enet"; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- enet_mdc_cfg { +- pins = "pc_1"; +- function = "enet"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- }; +- +- gpio_joystick_pins: gpio-joystick-pins { +- gpio_joystick_cfg { +- pins = "p9_0", "p9_1", "pa_1", "pa_2", "pa_3"; +- function = "gpio"; +- input-enable; +- bias-disable; +- }; +- }; +- +- i2c0_pins: i2c0-pins { +- i2c0_pins_cfg { +- pins = "i2c0_scl", "i2c0_sda"; +- function = "i2c0"; +- input-enable; +- }; +- }; +- +- sdmmc_pins: sdmmc-pins { +- sdmmc_clk_cfg { +- pins = "pc_0"; +- function = "sdmmc"; +- slew-rate = <1>; +- bias-pull-down; +- }; +- +- sdmmc_cmd_dat0_3_cfg { +- pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10"; +- function = "sdmmc"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- sdmmc_cd_cfg { +- pins = "pc_8"; +- function = "sdmmc"; +- bias-pull-down; +- input-enable; +- }; +- +- sdmmc_pow_cfg { +- pins = "pc_9"; +- function = "sdmmc"; +- bias-pull-down; +- }; +- }; +- +- spifi_pins: spifi-pins { +- spifi_clk_cfg { +- pins = "p3_3"; +- function = "spifi"; +- slew-rate = <1>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- spifi_mosi_miso_sio2_3_cfg { +- pins = "p3_7", "p3_6", "p3_5", "p3_4"; +- function = "spifi"; +- slew-rate = <0>; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- spifi_cs_cfg { +- pins = "p3_8"; +- function = "spifi"; +- bias-disable; +- }; +- }; +- +- ssp0_pins: ssp0-pins { +- ssp0_sck_miso_mosi { +- pins = "pf_0", "pf_2", "pf_3"; +- function = "ssp0"; +- slew-rate = <1>; +- bias-pull-down; +- input-enable; +- input-schmitt-disable; +- }; +- +- ssp0_ssel { +- pins = "pf_1"; +- function = "ssp0"; +- bias-pull-up; +- }; +- }; +- +- uart0_pins: uart0-pins { +- uart0_rx_cfg { +- pins = "pf_11"; +- function = "uart0"; +- input-schmitt-disable; +- bias-disable; +- input-enable; +- }; +- +- uart0_tx_cfg { +- pins = "pf_10"; +- function = "uart0"; +- bias-pull-down; +- }; +- }; +- +- uart3_pins: uart3-pins { +- uart3_rx_cfg { +- pins = "p2_4"; +- function = "uart3"; +- input-schmitt-disable; +- bias-disable; +- input-enable; +- }; +- +- uart3_tx_cfg { +- pins = "p9_3"; +- function = "uart3"; +- bias-pull-down; +- }; +- }; +- +- usb0_pins: usb0-pins { +- usb0_pwr_enable { +- pins = "p2_3"; +- function = "usb0"; +- }; +- +- usb0_pwr_fault { +- pins = "p8_0"; +- function = "usb0"; +- bias-disable; +- input-enable; +- }; +- }; +-}; +- +-&adc0 { +- status = "okay"; +- vref-supply = <&vcc>; +-}; +- +-&i2c0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- clock-frequency = <400000>; +- +- mma7455@1d { +- compatible = "fsl,mma7455"; +- reg = <0x1d>; +- }; +- +- lm75@48 { +- compatible = "nxp,lm75"; +- reg = <0x48>; +- }; +- +- eeprom@57 { +- compatible = "microchip,24c64", "atmel,24c64"; +- reg = <0x57>; +- }; +-}; +- +-&dac { +- status = "okay"; +- vref-supply = <&vcc>; +-}; +- +-&emc { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&emc_pins>; +- +- cs0 { +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- +- mpmc,cs = <0>; +- mpmc,memory-width = <16>; +- mpmc,byte-lane-low; +- mpmc,write-enable-delay = <0>; +- mpmc,output-enable-delay = <0>; +- mpmc,read-access-delay = <70>; +- mpmc,page-mode-read-delay = <70>; +- +- flash@0,0 { +- compatible = "sst,sst39vf320", "cfi-flash"; +- reg = <0 0 0x400000>; +- bank-width = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "bootloader"; +- reg = <0x000000 0x040000>; /* 256 KiB */ +- }; +- +- partition@1 { +- label = "kernel"; +- reg = <0x040000 0x2c0000>; /* 2.75 MiB */ +- }; +- +- partition@2 { +- label = "rootfs"; +- reg = <0x300000 0x100000>; /* 1 MiB */ +- }; +- }; +- }; +- +- cs2 { +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- +- mpmc,cs = <2>; +- mpmc,memory-width = <16>; +- +- mmio_leds: gpio@2,0 { +- compatible = "ti,7416374"; +- reg = <2 0 0x2>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- }; +-}; +- +-&enet_tx_clk { +- clock-frequency = <50000000>; +-}; +- +-&mac { +- status = "okay"; +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&enet_rmii_pins>; +-}; +- +-&mmcsd { +- status = "okay"; +- bus-width = <4>; +- vmmc-supply = <&vmmc>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_pins>; +-}; +- +-&spifi { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spifi_pins>; +- +- flash { +- compatible = "jedec,spi-nor"; +- spi-cpol; +- spi-cpha; +- spi-rx-bus-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "data"; +- reg = <0 0x200000>; +- }; +- }; +-}; +- +-&ssp0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ssp0_pins>; +- num-cs = <1>; +-}; +- +-&uart0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +-}; +- +-&uart3 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +-}; +- +-&usb0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb0_pins>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/lpc4357-myd-lpc4357.dts b/scripts/dtc/include-prefixes/arm/lpc4357-myd-lpc4357.dts +deleted file mode 100644 +index 1f84654df50c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/lpc4357-myd-lpc4357.dts ++++ /dev/null +@@ -1,619 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel +- * +- * Copyright (C) 2016-2018 Vladimir Zapolskiy +- */ +- +-/dts-v1/; +- +-#include "lpc18xx.dtsi" +-#include "lpc4357.dtsi" +- +-#include +- +-/ { +- model = "MYIR Tech LPC4357 Development Board"; +- compatible = "myir,myd-lpc4357", "nxp,lpc4357"; +- +- chosen { +- stdout-path = "serial3:115200n8"; +- }; +- +- memory@28000000 { +- device_type = "memory"; +- reg = <0x28000000 0x2000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins>; +- +- led1 { +- gpios = <&gpio LPC_GPIO(6,15) GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led2 { +- gpios = <&gpio LPC_GPIO(6,16) GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led3 { +- gpios = <&gpio LPC_GPIO(6,17) GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led4 { +- gpios = <&gpio LPC_GPIO(6,10) GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led5 { +- gpios = <&gpio LPC_GPIO(7,14) GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led6 { +- gpios = <&gpio LPC_GPIO(6,14) GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- panel: panel { +- compatible = "innolux,at070tn92"; +- +- port { +- panel_input: endpoint { +- remote-endpoint = <&lcdc_output>; +- }; +- }; +- }; +- +- vcc: vcc_fixed { +- compatible = "regulator-fixed"; +- regulator-name = "vcc-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vmmc: vmmc_fixed { +- compatible = "regulator-fixed"; +- regulator-name = "vmmc-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&pinctrl { +- can0_pins: can0-pins { +- can_rd_cfg { +- pins = "p3_1"; +- function = "can0"; +- input-enable; +- }; +- +- can_td_cfg { +- pins = "p3_2"; +- function = "can0"; +- }; +- }; +- +- can1_pins: can1-pins { +- can_rd_cfg { +- pins = "pe_1"; +- function = "can1"; +- input-enable; +- }; +- +- can_td_cfg { +- pins = "pe_0"; +- function = "can1"; +- }; +- }; +- +- emc_pins: emc-pins { +- emc_addr0_22_cfg { +- pins = "p2_9", "p2_10", "p2_11", "p2_12", +- "p2_13", "p1_0", "p1_1", "p1_2", +- "p2_8", "p2_7", "p2_6", "p2_2", +- "p2_1", "p2_0", "p6_8", "p6_7", +- "pd_16", "pd_15", "pe_0", "pe_1", +- "pe_2", "pe_3", "pe_4"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- }; +- +- emc_data0_15_cfg { +- pins = "p1_7", "p1_8", "p1_9", "p1_10", +- "p1_11", "p1_12", "p1_13", "p1_14", +- "p5_4", "p5_5", "p5_6", "p5_7", +- "p5_0", "p5_1", "p5_2", "p5_3"; +- function = "emc"; +- input-enable; +- input-schmitt-disable; +- slew-rate = <1>; +- bias-disable; +- }; +- +- emc_we_oe_cfg { +- pins = "p1_6", "p1_3"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- }; +- +- emc_cs0_cfg { +- pins = "p1_5"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- }; +- +- emc_sdram_dqm0_1_cfg { +- pins = "p6_12", "p6_10"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- }; +- +- emc_sdram_ras_cas_cfg { +- pins = "p6_5", "p6_4"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- }; +- +- emc_sdram_dycs0_cfg { +- pins = "p6_9"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- }; +- +- emc_sdram_cke_cfg { +- pins = "p6_11"; +- function = "emc"; +- slew-rate = <1>; +- bias-disable; +- }; +- +- emc_sdram_clock_cfg { +- pins = "clk0"; +- function = "emc"; +- input-enable; +- input-schmitt-disable; +- slew-rate = <1>; +- bias-disable; +- }; +- }; +- +- enet_rmii_pins: enet-rmii-pins { +- enet_rmii_rxd_cfg { +- pins = "p1_15", "p0_0"; +- function = "enet"; +- input-enable; +- input-schmitt-disable; +- slew-rate = <1>; +- bias-disable; +- }; +- +- enet_rmii_txd_cfg { +- pins = "p1_18", "p1_20"; +- function = "enet"; +- slew-rate = <1>; +- bias-disable; +- }; +- +- enet_rmii_rx_dv_cfg { +- pins = "p1_16"; +- function = "enet"; +- input-enable; +- input-schmitt-disable; +- bias-disable; +- }; +- +- enet_mdio_cfg { +- pins = "p1_17"; +- function = "enet"; +- input-enable; +- input-schmitt-disable; +- bias-disable; +- }; +- +- enet_mdc_cfg { +- pins = "pc_1"; +- function = "enet"; +- slew-rate = <1>; +- bias-disable; +- }; +- +- enet_rmii_tx_en_cfg { +- pins = "p0_1"; +- function = "enet"; +- bias-disable; +- }; +- +- enet_ref_clk_cfg { +- pins = "p1_19"; +- function = "enet"; +- slew-rate = <1>; +- input-enable; +- input-schmitt-disable; +- bias-disable; +- }; +- }; +- +- i2c0_pins: i2c0-pins { +- i2c0_pins_cfg { +- pins = "i2c0_scl", "i2c0_sda"; +- function = "i2c0"; +- input-enable; +- }; +- }; +- +- i2c1_pins: i2c1-pins { +- i2c1_pins_cfg { +- pins = "pe_15", "pe_13"; +- function = "i2c1"; +- input-enable; +- }; +- }; +- +- lcd_pins: lcd-pins { +- lcd_vd0_23_cfg { +- pins = "p4_1", "p4_4", "p4_3", "p4_2", +- "p8_7", "p8_6", "p8_5", "p8_4", +- "p7_5", "p4_8", "p4_10", "p4_9", +- "p8_3", "pb_6", "pb_5", "pb_4", +- "p7_4", "p7_3", "p7_2", "p7_1", +- "pb_3", "pb_2", "pb_1", "pb_0"; +- function = "lcd"; +- }; +- +- lcd_vsync_en_dclk_lp_pwr_cfg { +- pins = "p4_5", "p4_6", "p4_7", "p7_6", "p7_7"; +- function = "lcd"; +- }; +- }; +- +- led_pins: led-pins { +- led_1_6_cfg { +- pins = "pd_1", "pd_2", "pd_3", "pc_11", "pe_14", "pd_0"; +- function = "gpio"; +- bias-pull-down; +- }; +- }; +- +- sdmmc_pins: sdmmc-pins { +- sdmmc_clk_cfg { +- pins = "pc_0"; +- function = "sdmmc"; +- slew-rate = <1>; +- bias-pull-down; +- }; +- +- sdmmc_cmd_dat0_3_cfg { +- pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10"; +- function = "sdmmc"; +- input-enable; +- input-schmitt-disable; +- slew-rate = <1>; +- bias-disable; +- }; +- +- sdmmc_cd_cfg { +- pins = "pc_8"; +- function = "sdmmc"; +- input-enable; +- bias-pull-down; +- }; +- }; +- +- spifi_pins: spifi-pins { +- spifi_sck_cfg { +- pins = "p3_3"; +- function = "spifi"; +- input-enable; +- input-schmitt-disable; +- slew-rate = <1>; +- bias-disable; +- }; +- +- spifi_mosi_miso_sio2_sio3_cfg { +- pins = "p3_7", "p3_6", "p3_5", "p3_4"; +- function = "spifi"; +- input-enable; +- input-schmitt-disable; +- slew-rate = <1>; +- bias-disable; +- }; +- +- spifi_cs_cfg { +- pins = "p3_8"; +- function = "spifi"; +- bias-disable; +- }; +- }; +- +- ssp1_pins: ssp1-pins { +- ssp1_sck_cfg { +- pins = "pf_4"; +- function = "ssp1"; +- slew-rate = <1>; +- bias-pull-down; +- }; +- +- ssp1_miso_cfg { +- pins = "pf_6"; +- function = "ssp1"; +- input-enable; +- input-schmitt-disable; +- slew-rate = <1>; +- bias-pull-down; +- }; +- +- ssp1_mosi_cfg { +- pins = "pf_7"; +- function = "ssp1"; +- slew-rate = <1>; +- bias-pull-down; +- }; +- +- ssp1_ssel_cfg { +- pins = "pf_5"; +- function = "gpio"; +- bias-disable; +- }; +- }; +- +- uart0_pins: uart0-pins { +- uart0_rxd_cfg { +- pins = "pf_11"; +- function = "uart0"; +- input-enable; +- input-schmitt-disable; +- bias-disable; +- }; +- +- uart0_clk_dir_txd_cfg { +- pins = "pf_8", "pf_9", "pf_10"; +- function = "uart0"; +- bias-pull-down; +- }; +- }; +- +- uart1_pins: uart1-pins { +- uart1_rxd_cfg { +- pins = "pc_14"; +- function = "uart1"; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- uart1_dtr_txd_cfg { +- pins = "pc_12", "pc_13"; +- function = "uart1"; +- bias-pull-down; +- }; +- }; +- +- uart2_pins: uart2-pins { +- uart2_rxd_cfg { +- pins = "pa_2"; +- function = "uart2"; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- uart2_txd_cfg { +- pins = "pa_1"; +- function = "uart2"; +- bias-pull-down; +- }; +- }; +- +- uart3_pins: uart3-pins { +- uart3_rx_cfg { +- pins = "p2_4"; +- function = "uart3"; +- bias-disable; +- input-enable; +- input-schmitt-disable; +- }; +- +- uart3_tx_cfg { +- pins = "p2_3"; +- function = "uart3"; +- bias-pull-down; +- }; +- }; +- +- usb0_pins: usb0-pins { +- usb0_pwr_enable_cfg { +- pins = "p6_3"; +- function = "usb0"; +- }; +- +- usb0_pwr_fault_cfg { +- pins = "p8_0"; +- function = "usb0"; +- bias-disable; +- input-enable; +- }; +- }; +-}; +- +-&adc1 { +- status = "okay"; +- vref-supply = <&vcc>; +-}; +- +-&can0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&can0_pins>; +-}; +- +-/* Pin conflict with EMC, muxed by JP5 and JP6 */ +-&can1 { +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&can1_pins>; +-}; +- +-&emc { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&emc_pins>; +- +- cs0 { +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- +- mpmc,cs = <0>; +- mpmc,memory-width = <16>; +- mpmc,byte-lane-low; +- mpmc,write-enable-delay = <0>; +- mpmc,output-enable-delay = <0>; +- mpmc,read-access-delay = <70>; +- mpmc,page-mode-read-delay = <70>; +- +- /* SST/Microchip SST39VF1601 */ +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x400000>; +- bank-width = <2>; +- }; +- }; +-}; +- +-&enet_tx_clk { +- clock-frequency = <50000000>; +-}; +- +-&i2c0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- clock-frequency = <400000>; +-}; +- +-&i2c1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- clock-frequency = <400000>; +- +- sensor@49 { +- compatible = "lm75"; +- reg = <0x49>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c512"; +- reg = <0x50>; +- }; +-}; +- +-&lcdc { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_pins>; +- +- max-memory-bandwidth = <92240000>; +- +- port { +- lcdc_output: endpoint { +- remote-endpoint = <&panel_input>; +- arm,pl11x,tft-r0g0b0-pads = <0 8 16>; +- }; +- }; +-}; +- +-&mac { +- status = "okay"; +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&enet_rmii_pins>; +- phy-handle = <&phy1>; +- +- mdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +- }; +-}; +- +-&mmcsd { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_pins>; +- bus-width = <4>; +- vmmc-supply = <&vmmc>; +-}; +- +-/* Pin conflict with SSP0, the latter is routed to J17 pin header */ +-&spifi { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spifi_pins>; +- +- /* Atmel AT25DF321A */ +- flash { +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <51000000>; +- spi-cpol; +- spi-cpha; +- }; +-}; +- +-&ssp1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ssp1_pins>; +- num-cs = <1>; +- cs-gpios = <&gpio LPC_GPIO(7,19) GPIO_ACTIVE_LOW>; +-}; +- +-/* Routed to J17 pin header */ +-&uart0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +-}; +- +-/* RS485 */ +-&uart1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +-}; +- +-/* Routed to J17 pin header */ +-&uart2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +-}; +- +-&uart3 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +-}; +- +-&usb0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb0_pins>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/lpc4357.dtsi b/scripts/dtc/include-prefixes/arm/lpc4357.dtsi +deleted file mode 100644 +index 72f12db8d53a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/lpc4357.dtsi ++++ /dev/null +@@ -1,43 +0,0 @@ +-/* +- * NXP LPC435x, LPC433x, LPC4327, LPC4325, LPC4317 and LPC4315 SoC +- * +- * Copyright 2015 Joachim Eastwood +- * +- * This code is released using a dual license strategy: BSD/GPL +- * You can choose the licence that better fits your requirements. +- * +- * Released under the terms of 3-clause BSD License +- * Released under the terms of GNU General Public License Version 2.0 +- * +- */ +- +-/ { +- compatible = "nxp,lpc4357"; +- +- cpus { +- cpu@0 { +- compatible = "arm,cortex-m4"; +- }; +- }; +- +- soc { +- sram0: sram@10000000 { +- compatible = "mmio-sram"; +- reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */ +- }; +- +- sram1: sram@10080000 { +- compatible = "mmio-sram"; +- reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */ +- }; +- +- sram2: sram@20000000 { +- compatible = "mmio-sram"; +- reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ +- }; +- }; +-}; +- +-&eeprom { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ls1021a-moxa-uc-8410a.dts b/scripts/dtc/include-prefixes/arm/ls1021a-moxa-uc-8410a.dts +deleted file mode 100644 +index f3ddea934f1b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ls1021a-moxa-uc-8410a.dts ++++ /dev/null +@@ -1,237 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2017 Moxa Inc. - https://www.moxa.com/ +- * +- * Author: Harry YJ Jhou (周亞諄) +- * Jimmy Chen (陳永達) +- * SZ Lin (林上智) +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "ls1021a.dtsi" +- +-/ { +- model = "Moxa UC-8410A"; +- compatible = "fsl,ls1021a-moxa-uc-8410a", "fsl,ls1021a"; +- +- aliases { +- enet0_rgmii_phy = &rgmii_phy0; +- enet1_rgmii_phy = &rgmii_phy1; +- enet2_rgmii_phy = &rgmii_phy2; +- }; +- +- sys_mclk: clock-mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- cel-pwr { +- label = "UC8410A:CEL-PWR"; +- gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- cel-reset { +- label = "UC8410A:CEL-RESET"; +- gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- str-led { +- label = "UC8410A:RED:PROG"; +- gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- }; +- +- sw-ready { +- label = "UC8410A:GREEN:SWRDY"; +- gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- beeper { +- label = "UC8410A:BEEP"; +- gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- prog-led0 { +- label = "UC8410A:GREEN:PROG2"; +- gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- prog-led1 { +- label = "UC8410A:GREEN:PROG1"; +- gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- prog-led2 { +- label = "UC8410A:GREEN:PROG0"; +- gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- wifi-signal0 { +- label = "UC8410A:GREEN:CEL2"; +- gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- wifi-signal1 { +- label = "UC8410A:GREEN:CEL1"; +- gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- wifi-signal2 { +- label = "UC8410A:GREEN:CEL0"; +- gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- cpu-diag-red { +- label = "UC8410A:RED:DIA"; +- gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- cpu-diag-green { +- label = "UC8410A:GREEN:DIA"; +- gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- cpu-diag-yellow { +- label = "UC8410A:YELLOW:DIA"; +- gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- pushbtn-key { +- label = "push button key"; +- gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; +- linux,code = ; +- default-state = "on"; +- }; +- }; +-}; +- +-&enet0 { +- phy-handle = <&rgmii_phy0>; +- phy-connection-type = "rgmii-id"; +- status = "okay"; +-}; +- +-&enet1 { +- phy-handle = <&rgmii_phy1>; +- phy-connection-type = "rgmii-id"; +- status = "okay"; +-}; +- +-&enet2 { +- phy-handle = <&rgmii_phy2>; +- phy-connection-type = "rgmii-id"; +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <100000>; +- status = "okay"; +- +- tpm@20 { +- compatible = "infineon,slb9635tt"; +- reg = <0x20>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1374"; +- reg = <0x68>; +- }; +-}; +- +-&lpuart0 { +- status = "okay"; +-}; +- +-&mdio0 { +- rgmii_phy0: ethernet-phy@0 { +- compatible = "marvell,88e1118"; +- reg = <0x0>; +- marvell,reg-init = +- <3 0x11 0 0x4415>, /* Reg 3,17 */ +- <3 0x10 0 0x77>; /* Reg 3,16 */ +- }; +- +- rgmii_phy1: ethernet-phy@1 { +- compatible = "marvell,88e1118"; +- reg = <0x1>; +- marvell,reg-init = +- <3 0x11 0 0x4415>, /* Reg 3,17 */ +- <3 0x10 0 0x77>; /* Reg 3,16 */ +- }; +- +- rgmii_phy2: ethernet-phy@2 { +- compatible = "marvell,88e1118"; +- reg = <0x2>; +- marvell,reg-init = +- <3 0x11 0 0x4415>, /* Reg 3,17 */ +- <3 0x10 0 0x77>; /* Reg 3,16 */ +- }; +-}; +- +-&qspi { +- status = "okay"; +- +- flash: flash@0 { +- compatible = "spansion,s25fl064l", "spansion,s25fl164k"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <20000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <4>; +- reg = <0>; +- +- partitions@0 { +- label = "U-Boot"; +- reg = <0x0 0x180000>; +- }; +- +- partitions@180000 { +- label = "U-Boot Env"; +- reg = <0x180000 0x680000>; +- }; +- }; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ls1021a-qds.dts b/scripts/dtc/include-prefixes/arm/ls1021a-qds.dts +deleted file mode 100644 +index 74a67604876c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ls1021a-qds.dts ++++ /dev/null +@@ -1,361 +0,0 @@ +-/* +- * Copyright 2013-2014 Freescale Semiconductor, Inc. +- * Copyright 2018 NXP +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "ls1021a.dtsi" +- +-/ { +- model = "LS1021A QDS Board"; +- compatible = "fsl,ls1021a-qds", "fsl,ls1021a"; +- +- aliases { +- enet0_rgmii_phy = &rgmii_phy1; +- enet1_rgmii_phy = &rgmii_phy2; +- enet2_rgmii_phy = &rgmii_phy3; +- enet0_sgmii_phy = &sgmii_phy1c; +- enet1_sgmii_phy = &sgmii_phy1d; +- }; +- +- sys_mclk: clock-mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_3p3v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,widgets = +- "Microphone", "Microphone Jack", +- "Headphone", "Headphone Jack", +- "Speaker", "Speaker Ext", +- "Line", "Line In Jack"; +- simple-audio-card,routing = +- "MIC_IN", "Microphone Jack", +- "Microphone Jack", "Mic Bias", +- "LINE_IN", "Line In Jack", +- "Headphone Jack", "HP_OUT", +- "Speaker Ext", "LINE_OUT"; +- +- simple-audio-card,cpu { +- sound-dai = <&sai2>; +- frame-master; +- bitclock-master; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&codec>; +- frame-master; +- bitclock-master; +- }; +- }; +-}; +- +-&dspi0 { +- bus-num = <0>; +- status = "okay"; +- +- dspiflash: at45db021d@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash"; +- spi-max-frequency = <16000000>; +- spi-cpol; +- spi-cpha; +- reg = <0>; +- }; +-}; +- +-&enet0 { +- tbi-handle = <&tbi0>; +- phy-handle = <&sgmii_phy1c>; +- phy-connection-type = "sgmii"; +- status = "okay"; +-}; +- +-&enet1 { +- tbi-handle = <&tbi0>; +- phy-handle = <&sgmii_phy1d>; +- phy-connection-type = "sgmii"; +- status = "okay"; +-}; +- +-&enet2 { +- phy-handle = <&rgmii_phy3>; +- phy-connection-type = "rgmii-id"; +- status = "okay"; +-}; +- +-&esdhc { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- pca9547: mux@77 { +- compatible = "nxp,pca9547"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0>; +- +- ds3232: rtc@68 { +- compatible = "dallas,ds3232"; +- reg = <0x68>; +- interrupts = ; +- }; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; +- +- ina220@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <1000>; +- }; +- +- ina220@41 { +- compatible = "ti,ina220"; +- reg = <0x41>; +- shunt-resistor = <1000>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3>; +- +- eeprom@56 { +- compatible = "atmel,24c512"; +- reg = <0x56>; +- }; +- +- eeprom@57 { +- compatible = "atmel,24c512"; +- reg = <0x57>; +- }; +- +- adt7461a@4c { +- compatible = "adi,adt7461a"; +- reg = <0x4c>; +- }; +- }; +- +- i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x4>; +- +- codec: sgtl5000@2a { +- #sound-dai-cells = <0>; +- compatible = "fsl,sgtl5000"; +- reg = <0x2a>; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; +- clocks = <&sys_mclk>; +- }; +- }; +- }; +-}; +- +-&ifc { +- #address-cells = <2>; +- #size-cells = <1>; +- /* NOR, NAND Flashes and FPGA on board */ +- ranges = <0x0 0x0 0x0 0x60000000 0x08000000 +- 0x2 0x0 0x0 0x7e800000 0x00010000 +- 0x3 0x0 0x0 0x7fb00000 0x00000100>; +- status = "okay"; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- big-endian; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@2,0 { +- compatible = "fsl,ifc-nand"; +- reg = <0x2 0x0 0x10000>; +- }; +- +- fpga: board-control@3,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- reg = <0x3 0x0 0x0000100>; +- bank-width = <1>; +- device-width = <1>; +- ranges = <0 3 0 0x100>; +- +- mdio-mux-emi1 { +- compatible = "mdio-mux-mmioreg"; +- mdio-parent-bus = <&mdio0>; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x54 1>; /* BRDCFG4 */ +- mux-mask = <0xe0>; /* EMI1[2:0] */ +- +- /* Onboard PHYs */ +- ls1021amdio0: mdio@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- rgmii_phy1: ethernet-phy@1 { +- reg = <0x1>; +- }; +- }; +- +- ls1021amdio1: mdio@20 { +- reg = <0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- rgmii_phy2: ethernet-phy@2 { +- reg = <0x2>; +- }; +- }; +- +- ls1021amdio2: mdio@40 { +- reg = <0x40>; +- #address-cells = <1>; +- #size-cells = <0>; +- rgmii_phy3: ethernet-phy@3 { +- reg = <0x3>; +- }; +- }; +- +- ls1021amdio3: mdio@60 { +- reg = <0x60>; +- #address-cells = <1>; +- #size-cells = <0>; +- sgmii_phy1c: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- }; +- +- ls1021amdio4: mdio@80 { +- reg = <0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- sgmii_phy1d: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- }; +- }; +- }; +-}; +- +-&lpuart0 { +- status = "okay"; +-}; +- +-&mdio0 { +- tbi0: tbi-phy@8 { +- reg = <0x8>; +- device_type = "tbi-phy"; +- }; +-}; +- +-&sai2 { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&can0 { +- status = "okay"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&can2 { +- status = "disabled"; +-}; +- +-&can3 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ls1021a-tsn.dts b/scripts/dtc/include-prefixes/arm/ls1021a-tsn.dts +deleted file mode 100644 +index aca78b5eddf2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ls1021a-tsn.dts ++++ /dev/null +@@ -1,293 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* Copyright 2016-2018 NXP Semiconductors +- * Copyright 2019 Vladimir Oltean +- */ +- +-/dts-v1/; +-#include "ls1021a.dtsi" +- +-/ { +- model = "NXP LS1021A-TSN Board"; +- +- sys_mclk: clock-mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +- +- reg_vdda_codec: regulator-3V3 { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_vddio_codec: regulator-2V5 { +- compatible = "regulator-fixed"; +- regulator-name = "2P5V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +-}; +- +-&dspi0 { +- bus-num = <0>; +- status = "okay"; +- +- /* ADG704BRMZ 1:4 SPI mux/demux */ +- sja1105: ethernet-switch@1 { +- reg = <0x1>; +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "nxp,sja1105t"; +- /* 12 MHz */ +- spi-max-frequency = <12000000>; +- /* Sample data on trailing clock edge */ +- spi-cpha; +- /* SPI controller settings for SJA1105 timing requirements */ +- fsl,spi-cs-sck-delay = <1000>; +- fsl,spi-sck-cs-delay = <1000>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- /* ETH5 written on chassis */ +- label = "swp5"; +- phy-handle = <&rgmii_phy6>; +- phy-mode = "rgmii-id"; +- reg = <0>; +- }; +- +- port@1 { +- /* ETH2 written on chassis */ +- label = "swp2"; +- phy-handle = <&rgmii_phy3>; +- phy-mode = "rgmii-id"; +- reg = <1>; +- }; +- +- port@2 { +- /* ETH3 written on chassis */ +- label = "swp3"; +- phy-handle = <&rgmii_phy4>; +- phy-mode = "rgmii-id"; +- reg = <2>; +- }; +- +- port@3 { +- /* ETH4 written on chassis */ +- label = "swp4"; +- phy-handle = <&rgmii_phy5>; +- phy-mode = "rgmii-id"; +- reg = <3>; +- }; +- +- port@4 { +- /* Internal port connected to eth2 */ +- ethernet = <&enet2>; +- phy-mode = "rgmii"; +- reg = <4>; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; +-}; +- +-&enet0 { +- tbi-handle = <&tbi0>; +- phy-handle = <&sgmii_phy2>; +- phy-mode = "sgmii"; +- status = "okay"; +-}; +- +-&enet1 { +- tbi-handle = <&tbi1>; +- phy-handle = <&sgmii_phy1>; +- phy-mode = "sgmii"; +- status = "okay"; +-}; +- +-/* RGMII delays added via PCB traces */ +-&enet2 { +- phy-mode = "rgmii"; +- status = "okay"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +-}; +- +-&esdhc { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- /* 3 axis accelerometer */ +- accelerometer@1e { +- compatible = "fsl,fxls8471"; +- position = <0>; +- reg = <0x1e>; +- }; +- +- /* Audio codec (SAI2) */ +- audio-codec@2a { +- compatible = "fsl,sgtl5000"; +- VDDIO-supply = <®_vddio_codec>; +- VDDA-supply = <®_vdda_codec>; +- #sound-dai-cells = <0>; +- clocks = <&sys_mclk>; +- reg = <0x2a>; +- }; +- +- /* Current sensing circuit for 1V VDDCORE PMIC rail */ +- current-sensor@44 { +- compatible = "ti,ina220"; +- shunt-resistor = <1000>; +- reg = <0x44>; +- }; +- +- /* Current sensing circuit for 12V VCC rail */ +- current-sensor@45 { +- compatible = "ti,ina220"; +- shunt-resistor = <1000>; +- reg = <0x45>; +- }; +- +- /* Thermal monitor - case */ +- temperature-sensor@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +- +- /* Thermal monitor - chip */ +- temperature-sensor@4c { +- compatible = "ti,tmp451"; +- reg = <0x4c>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c32"; +- reg = <0x51>; +- }; +- +- /* Unsupported devices: +- * - FXAS21002C Gyroscope at 0x20 +- * - TI ADS7924 4-channel ADC at 0x49 +- */ +-}; +- +-&ifc { +- status = "disabled"; +-}; +- +-&lpuart0 { +- status = "okay"; +-}; +- +-&lpuart3 { +- status = "okay"; +-}; +- +-&mdio0 { +- /* AR8031 */ +- sgmii_phy1: ethernet-phy@1 { +- reg = <0x1>; +- /* SGMII1_PHY_INT_B: connected to IRQ2, active low */ +- interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>; +- }; +- +- /* AR8031 */ +- sgmii_phy2: ethernet-phy@2 { +- reg = <0x2>; +- /* SGMII2_PHY_INT_B: connected to IRQ2, active low */ +- interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>; +- }; +- +- /* BCM5464 quad PHY */ +- rgmii_phy3: ethernet-phy@3 { +- reg = <0x3>; +- }; +- +- rgmii_phy4: ethernet-phy@4 { +- reg = <0x4>; +- }; +- +- rgmii_phy5: ethernet-phy@5 { +- reg = <0x5>; +- }; +- +- rgmii_phy6: ethernet-phy@6 { +- reg = <0x6>; +- }; +- +- /* SGMII PCS for enet0 */ +- tbi0: tbi-phy@1f { +- reg = <0x1f>; +- device_type = "tbi-phy"; +- }; +-}; +- +-&mdio1 { +- /* SGMII PCS for enet1 */ +- tbi1: tbi-phy@1f { +- reg = <0x1f>; +- device_type = "tbi-phy"; +- }; +-}; +- +-&qspi { +- status = "okay"; +- +- flash@0 { +- /* Rev. A uses 64MB flash, Rev. B & C use 32MB flash */ +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "RCW"; +- reg = <0x0 0x40000>; +- }; +- +- partition@40000 { +- label = "U-Boot"; +- reg = <0x40000 0x300000>; +- }; +- +- partition@340000 { +- label = "U-Boot Env"; +- reg = <0x340000 0x100000>; +- }; +- }; +- }; +-}; +- +-&sai2 { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ls1021a-twr.dts b/scripts/dtc/include-prefixes/arm/ls1021a-twr.dts +deleted file mode 100644 +index 5edf001f6138..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ls1021a-twr.dts ++++ /dev/null +@@ -1,289 +0,0 @@ +-/* +- * Copyright 2013-2014 Freescale Semiconductor, Inc. +- * Copyright 2018 NXP +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "ls1021a.dtsi" +- +-/ { +- model = "LS1021A TWR Board"; +- compatible = "fsl,ls1021a-twr", "fsl,ls1021a"; +- +- aliases { +- enet2_rgmii_phy = &rgmii_phy1; +- enet0_sgmii_phy = &sgmii_phy2; +- enet1_sgmii_phy = &sgmii_phy0; +- }; +- +- sys_mclk: clock-mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_3p3v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,widgets = +- "Microphone", "Microphone Jack", +- "Headphone", "Headphone Jack", +- "Speaker", "Speaker Ext", +- "Line", "Line In Jack"; +- simple-audio-card,routing = +- "MIC_IN", "Microphone Jack", +- "Microphone Jack", "Mic Bias", +- "LINE_IN", "Line In Jack", +- "Headphone Jack", "HP_OUT", +- "Speaker Ext", "LINE_OUT"; +- +- simple-audio-card,cpu { +- sound-dai = <&sai1>; +- frame-master; +- bitclock-master; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&codec>; +- frame-master; +- bitclock-master; +- }; +- }; +- +- panel: panel { +- compatible = "nec,nl4827hc19-05b"; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&dcu_out>; +- }; +- }; +- }; +-}; +- +-&dcu { +- status = "okay"; +- +- port { +- dcu_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +-}; +- +-&dspi1 { +- bus-num = <0>; +- status = "okay"; +- +- dspiflash: s25fl064k@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25fl064k"; +- spi-max-frequency = <16000000>; +- spi-cpol; +- spi-cpha; +- reg = <0>; +- }; +-}; +- +-&enet0 { +- tbi-handle = <&tbi0>; +- phy-handle = <&sgmii_phy2>; +- phy-connection-type = "sgmii"; +- status = "okay"; +-}; +- +-&enet1 { +- tbi-handle = <&tbi1>; +- phy-handle = <&sgmii_phy0>; +- phy-connection-type = "sgmii"; +- status = "okay"; +-}; +- +-&enet2 { +- phy-handle = <&rgmii_phy1>; +- phy-connection-type = "rgmii-id"; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- ina220@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <1000>; +- }; +- +- ina220@41 { +- compatible = "ti,ina220"; +- reg = <0x41>; +- shunt-resistor = <1000>; +- }; +- +-}; +- +-&i2c1 { +- status = "okay"; +- codec: sgtl5000@a { +- #sound-dai-cells = <0>; +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; +- clocks = <&sys_mclk>; +- }; +-}; +- +-&ifc { +- #address-cells = <2>; +- #size-cells = <1>; +- /* NOR Flash on board */ +- ranges = <0x0 0x0 0x0 0x60000000 0x08000000>; +- status = "okay"; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- big-endian; +- bank-width = <2>; +- device-width = <1>; +- }; +-}; +- +-&lpuart0 { +- status = "okay"; +-}; +- +-&mdio0 { +- sgmii_phy0: ethernet-phy@0 { +- reg = <0x0>; +- }; +- rgmii_phy1: ethernet-phy@1 { +- reg = <0x1>; +- }; +- sgmii_phy2: ethernet-phy@2 { +- reg = <0x2>; +- }; +- tbi0: tbi-phy@1f { +- reg = <0x1f>; +- device_type = "tbi-phy"; +- }; +-}; +- +-&mdio1 { +- tbi1: tbi-phy@1f { +- reg = <0x1f>; +- device_type = "tbi-phy"; +- }; +-}; +- +-&esdhc { +- status = "okay"; +-}; +- +-&qspi { +- status = "okay"; +- +- n25q128a130: flash@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <50000000>; +- reg = <0>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <4>; +- }; +-}; +- +-&sai1 { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&can0 { +- status = "okay"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&can2 { +- status = "disabled"; +-}; +- +-&can3 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ls1021a.dtsi b/scripts/dtc/include-prefixes/arm/ls1021a.dtsi +deleted file mode 100644 +index f3b8540750b6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ls1021a.dtsi ++++ /dev/null +@@ -1,1019 +0,0 @@ +-/* +- * Copyright 2013-2014 Freescale Semiconductor, Inc. +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "fsl,ls1021a"; +- interrupt-parent = <&gic>; +- +- aliases { +- crypto = &crypto; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- rtc1 = &ftm_alarm0; +- serial0 = &lpuart0; +- serial1 = &lpuart1; +- serial2 = &lpuart2; +- serial3 = &lpuart3; +- serial4 = &lpuart4; +- serial5 = &lpuart5; +- sysclk = &sysclk; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@f00 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <0xf00>; +- clocks = <&clockgen 1 0>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@f01 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <0xf01>; +- clocks = <&clockgen 1 0>; +- #cooling-cells = <2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x0>; +- }; +- +- sysclk: sysclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- clock-output-names = "sysclk"; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupts = , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- reboot { +- compatible = "syscon-reboot"; +- regmap = <&dcfg>; +- offset = <0xb0>; +- mask = <0x02>; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- device_type = "soc"; +- interrupt-parent = <&gic>; +- ranges; +- +- ddr: memory-controller@1080000 { +- compatible = "fsl,qoriq-memory-controller"; +- reg = <0x0 0x1080000 0x0 0x1000>; +- interrupts = ; +- big-endian; +- }; +- +- gic: interrupt-controller@1400000 { +- compatible = "arm,gic-400", "arm,cortex-a7-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x0 0x1401000 0x0 0x1000>, +- <0x0 0x1402000 0x0 0x2000>, +- <0x0 0x1404000 0x0 0x2000>, +- <0x0 0x1406000 0x0 0x2000>; +- interrupts = ; +- +- }; +- +- msi1: msi-controller@1570e00 { +- compatible = "fsl,ls1021a-msi"; +- reg = <0x0 0x1570e00 0x0 0x8>; +- msi-controller; +- interrupts = ; +- }; +- +- msi2: msi-controller@1570e08 { +- compatible = "fsl,ls1021a-msi"; +- reg = <0x0 0x1570e08 0x0 0x8>; +- msi-controller; +- interrupts = ; +- }; +- +- ifc: ifc@1530000 { +- compatible = "fsl,ifc", "simple-bus"; +- reg = <0x0 0x1530000 0x0 0x10000>; +- interrupts = ; +- }; +- +- dcfg: dcfg@1ee0000 { +- compatible = "fsl,ls1021a-dcfg", "syscon"; +- reg = <0x0 0x1ee0000 0x0 0x1000>; +- big-endian; +- }; +- +- qspi: spi@1550000 { +- compatible = "fsl,ls1021a-qspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x1550000 0x0 0x10000>, +- <0x0 0x40000000 0x0 0x20000000>; +- reg-names = "QuadSPI", "QuadSPI-memory"; +- interrupts = ; +- clock-names = "qspi_en", "qspi"; +- clocks = <&clockgen 4 1>, <&clockgen 4 1>; +- status = "disabled"; +- }; +- +- esdhc: esdhc@1560000 { +- compatible = "fsl,ls1021a-esdhc", "fsl,esdhc"; +- reg = <0x0 0x1560000 0x0 0x10000>; +- interrupts = ; +- clock-frequency = <0>; +- voltage-ranges = <1800 1800 3300 3300>; +- sdhci,auto-cmd12; +- big-endian; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- sata: sata@3200000 { +- compatible = "fsl,ls1021a-ahci"; +- reg = <0x0 0x3200000 0x0 0x10000>, +- <0x0 0x20220520 0x0 0x4>; +- reg-names = "ahci", "sata-ecc"; +- interrupts = ; +- clocks = <&clockgen 4 1>; +- dma-coherent; +- status = "disabled"; +- }; +- +- scfg: scfg@1570000 { +- compatible = "fsl,ls1021a-scfg", "syscon"; +- reg = <0x0 0x1570000 0x0 0x10000>; +- big-endian; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1570000 0x10000>; +- +- extirq: interrupt-controller@1ac { +- compatible = "fsl,ls1021a-extirq"; +- #interrupt-cells = <2>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x1ac 4>; +- interrupt-map = +- <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, +- <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, +- <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, +- <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, +- <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, +- <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-map-mask = <0xffffffff 0x0>; +- }; +- }; +- +- crypto: crypto@1700000 { +- compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; +- fsl,sec-era = <7>; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x0 0x1700000 0x0 0x100000>; +- ranges = <0x0 0x0 0x1700000 0x100000>; +- interrupts = ; +- dma-coherent; +- +- sec_jr0: jr@10000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x10000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr1: jr@20000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x20000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr2: jr@30000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x30000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr3: jr@40000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x40000 0x10000>; +- interrupts = ; +- }; +- +- }; +- +- clockgen: clocking@1ee1000 { +- compatible = "fsl,ls1021a-clockgen"; +- reg = <0x0 0x1ee1000 0x0 0x1000>; +- #clock-cells = <2>; +- clocks = <&sysclk>; +- }; +- +- tmu: tmu@1f00000 { +- compatible = "fsl,qoriq-tmu"; +- reg = <0x0 0x1f00000 0x0 0x10000>; +- interrupts = ; +- fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>; +- fsl,tmu-calibration = <0x00000000 0x00000020 +- 0x00000001 0x00000024 +- 0x00000002 0x0000002a +- 0x00000003 0x00000032 +- 0x00000004 0x00000038 +- 0x00000005 0x0000003e +- 0x00000006 0x00000043 +- 0x00000007 0x0000004a +- 0x00000008 0x00000050 +- 0x00000009 0x00000059 +- 0x0000000a 0x0000005f +- 0x0000000b 0x00000066 +- +- 0x00010000 0x00000023 +- 0x00010001 0x0000002b +- 0x00010002 0x00000033 +- 0x00010003 0x0000003a +- 0x00010004 0x00000042 +- 0x00010005 0x0000004a +- 0x00010006 0x00000054 +- 0x00010007 0x0000005c +- 0x00010008 0x00000065 +- 0x00010009 0x0000006f +- +- 0x00020000 0x00000029 +- 0x00020001 0x00000033 +- 0x00020002 0x0000003d +- 0x00020003 0x00000048 +- 0x00020004 0x00000054 +- 0x00020005 0x00000060 +- 0x00020006 0x0000006c +- +- 0x00030000 0x00000025 +- 0x00030001 0x00000033 +- 0x00030002 0x00000043 +- 0x00030003 0x00000055>; +- #thermal-sensor-cells = <1>; +- }; +- +- dspi0: spi@2100000 { +- compatible = "fsl,ls1021a-v1.0-dspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2100000 0x0 0x10000>; +- interrupts = ; +- clock-names = "dspi"; +- clocks = <&clockgen 4 1>; +- spi-num-chipselects = <6>; +- big-endian; +- status = "disabled"; +- }; +- +- dspi1: spi@2110000 { +- compatible = "fsl,ls1021a-v1.0-dspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2110000 0x0 0x10000>; +- interrupts = ; +- clock-names = "dspi"; +- clocks = <&clockgen 4 1>; +- spi-num-chipselects = <6>; +- big-endian; +- status = "disabled"; +- }; +- +- i2c0: i2c@2180000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2180000 0x0 0x10000>; +- interrupts = ; +- clock-names = "i2c"; +- clocks = <&clockgen 4 1>; +- dma-names = "tx", "rx"; +- dmas = <&edma0 1 39>, <&edma0 1 38>; +- status = "disabled"; +- }; +- +- i2c1: i2c@2190000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2190000 0x0 0x10000>; +- interrupts = ; +- clock-names = "i2c"; +- clocks = <&clockgen 4 1>; +- dma-names = "tx", "rx"; +- dmas = <&edma0 1 37>, <&edma0 1 36>; +- status = "disabled"; +- }; +- +- i2c2: i2c@21a0000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x21a0000 0x0 0x10000>; +- interrupts = ; +- clock-names = "i2c"; +- clocks = <&clockgen 4 1>; +- dma-names = "tx", "rx"; +- dmas = <&edma0 1 35>, <&edma0 1 34>; +- status = "disabled"; +- }; +- +- uart0: serial@21c0500 { +- compatible = "fsl,16550-FIFO64", "ns16550a"; +- reg = <0x0 0x21c0500 0x0 0x100>; +- interrupts = ; +- clock-frequency = <0>; +- fifo-size = <15>; +- status = "disabled"; +- }; +- +- uart1: serial@21c0600 { +- compatible = "fsl,16550-FIFO64", "ns16550a"; +- reg = <0x0 0x21c0600 0x0 0x100>; +- interrupts = ; +- clock-frequency = <0>; +- fifo-size = <15>; +- status = "disabled"; +- }; +- +- uart2: serial@21d0500 { +- compatible = "fsl,16550-FIFO64", "ns16550a"; +- reg = <0x0 0x21d0500 0x0 0x100>; +- interrupts = ; +- clock-frequency = <0>; +- fifo-size = <15>; +- status = "disabled"; +- }; +- +- uart3: serial@21d0600 { +- compatible = "fsl,16550-FIFO64", "ns16550a"; +- reg = <0x0 0x21d0600 0x0 0x100>; +- interrupts = ; +- clock-frequency = <0>; +- fifo-size = <15>; +- status = "disabled"; +- }; +- +- counter0: counter@29d0000 { +- compatible = "fsl,ftm-quaddec"; +- reg = <0x0 0x29d0000 0x0 0x10000>; +- big-endian; +- status = "disabled"; +- }; +- +- counter1: counter@29e0000 { +- compatible = "fsl,ftm-quaddec"; +- reg = <0x0 0x29e0000 0x0 0x10000>; +- big-endian; +- status = "disabled"; +- }; +- +- counter2: counter@29f0000 { +- compatible = "fsl,ftm-quaddec"; +- reg = <0x0 0x29f0000 0x0 0x10000>; +- big-endian; +- status = "disabled"; +- }; +- +- counter3: counter@2a00000 { +- compatible = "fsl,ftm-quaddec"; +- reg = <0x0 0x2a00000 0x0 0x10000>; +- big-endian; +- status = "disabled"; +- }; +- +- gpio0: gpio@2300000 { +- compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; +- reg = <0x0 0x2300000 0x0 0x10000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio@2310000 { +- compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; +- reg = <0x0 0x2310000 0x0 0x10000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@2320000 { +- compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; +- reg = <0x0 0x2320000 0x0 0x10000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio@2330000 { +- compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; +- reg = <0x0 0x2330000 0x0 0x10000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- lpuart0: serial@2950000 { +- compatible = "fsl,ls1021a-lpuart"; +- reg = <0x0 0x2950000 0x0 0x1000>; +- interrupts = ; +- clocks = <&sysclk>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- lpuart1: serial@2960000 { +- compatible = "fsl,ls1021a-lpuart"; +- reg = <0x0 0x2960000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen 4 1>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- lpuart2: serial@2970000 { +- compatible = "fsl,ls1021a-lpuart"; +- reg = <0x0 0x2970000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen 4 1>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- lpuart3: serial@2980000 { +- compatible = "fsl,ls1021a-lpuart"; +- reg = <0x0 0x2980000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen 4 1>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- lpuart4: serial@2990000 { +- compatible = "fsl,ls1021a-lpuart"; +- reg = <0x0 0x2990000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen 4 1>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- lpuart5: serial@29a0000 { +- compatible = "fsl,ls1021a-lpuart"; +- reg = <0x0 0x29a0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen 4 1>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- pwm0: pwm@29d0000 { +- compatible = "fsl,vf610-ftm-pwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x29d0000 0x0 0x10000>; +- clock-names = "ftm_sys", "ftm_ext", +- "ftm_fix", "ftm_cnt_clk_en"; +- clocks = <&clockgen 4 1>, <&clockgen 4 1>, +- <&clockgen 4 1>, <&clockgen 4 1>; +- big-endian; +- status = "disabled"; +- }; +- +- pwm1: pwm@29e0000 { +- compatible = "fsl,vf610-ftm-pwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x29e0000 0x0 0x10000>; +- clock-names = "ftm_sys", "ftm_ext", +- "ftm_fix", "ftm_cnt_clk_en"; +- clocks = <&clockgen 4 1>, <&clockgen 4 1>, +- <&clockgen 4 1>, <&clockgen 4 1>; +- big-endian; +- status = "disabled"; +- }; +- +- pwm2: pwm@29f0000 { +- compatible = "fsl,vf610-ftm-pwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x29f0000 0x0 0x10000>; +- clock-names = "ftm_sys", "ftm_ext", +- "ftm_fix", "ftm_cnt_clk_en"; +- clocks = <&clockgen 4 1>, <&clockgen 4 1>, +- <&clockgen 4 1>, <&clockgen 4 1>; +- big-endian; +- status = "disabled"; +- }; +- +- pwm3: pwm@2a00000 { +- compatible = "fsl,vf610-ftm-pwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x2a00000 0x0 0x10000>; +- clock-names = "ftm_sys", "ftm_ext", +- "ftm_fix", "ftm_cnt_clk_en"; +- clocks = <&clockgen 4 1>, <&clockgen 4 1>, +- <&clockgen 4 1>, <&clockgen 4 1>; +- big-endian; +- status = "disabled"; +- }; +- +- pwm4: pwm@2a10000 { +- compatible = "fsl,vf610-ftm-pwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x2a10000 0x0 0x10000>; +- clock-names = "ftm_sys", "ftm_ext", +- "ftm_fix", "ftm_cnt_clk_en"; +- clocks = <&clockgen 4 1>, <&clockgen 4 1>, +- <&clockgen 4 1>, <&clockgen 4 1>; +- big-endian; +- status = "disabled"; +- }; +- +- pwm5: pwm@2a20000 { +- compatible = "fsl,vf610-ftm-pwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x2a20000 0x0 0x10000>; +- clock-names = "ftm_sys", "ftm_ext", +- "ftm_fix", "ftm_cnt_clk_en"; +- clocks = <&clockgen 4 1>, <&clockgen 4 1>, +- <&clockgen 4 1>, <&clockgen 4 1>; +- big-endian; +- status = "disabled"; +- }; +- +- pwm6: pwm@2a30000 { +- compatible = "fsl,vf610-ftm-pwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x2a30000 0x0 0x10000>; +- clock-names = "ftm_sys", "ftm_ext", +- "ftm_fix", "ftm_cnt_clk_en"; +- clocks = <&clockgen 4 1>, <&clockgen 4 1>, +- <&clockgen 4 1>, <&clockgen 4 1>; +- big-endian; +- status = "disabled"; +- }; +- +- pwm7: pwm@2a40000 { +- compatible = "fsl,vf610-ftm-pwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x2a40000 0x0 0x10000>; +- clock-names = "ftm_sys", "ftm_ext", +- "ftm_fix", "ftm_cnt_clk_en"; +- clocks = <&clockgen 4 1>, <&clockgen 4 1>, +- <&clockgen 4 1>, <&clockgen 4 1>; +- big-endian; +- status = "disabled"; +- }; +- +- wdog0: watchdog@2ad0000 { +- compatible = "fsl,imx21-wdt"; +- reg = <0x0 0x2ad0000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen 4 1>; +- clock-names = "wdog-en"; +- big-endian; +- }; +- +- sai1: sai@2b50000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,vf610-sai"; +- reg = <0x0 0x2b50000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen 4 1>, <&clockgen 4 1>, +- <&clockgen 4 1>, <&clockgen 4 1>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dma-names = "tx", "rx"; +- dmas = <&edma0 1 47>, +- <&edma0 1 46>; +- status = "disabled"; +- }; +- +- sai2: sai@2b60000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,vf610-sai"; +- reg = <0x0 0x2b60000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen 4 1>, <&clockgen 4 1>, +- <&clockgen 4 1>, <&clockgen 4 1>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dma-names = "tx", "rx"; +- dmas = <&edma0 1 45>, +- <&edma0 1 44>; +- status = "disabled"; +- }; +- +- edma0: edma@2c00000 { +- #dma-cells = <2>; +- compatible = "fsl,vf610-edma"; +- reg = <0x0 0x2c00000 0x0 0x10000>, +- <0x0 0x2c10000 0x0 0x10000>, +- <0x0 0x2c20000 0x0 0x10000>; +- interrupts = , +- ; +- interrupt-names = "edma-tx", "edma-err"; +- dma-channels = <32>; +- big-endian; +- clock-names = "dmamux0", "dmamux1"; +- clocks = <&clockgen 4 1>, +- <&clockgen 4 1>; +- }; +- +- dcu: dcu@2ce0000 { +- compatible = "fsl,ls1021a-dcu"; +- reg = <0x0 0x2ce0000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen 4 0>, +- <&clockgen 4 0>; +- clock-names = "dcu", "pix"; +- big-endian; +- status = "disabled"; +- }; +- +- mdio0: mdio@2d24000 { +- compatible = "gianfar"; +- device_type = "mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2d24000 0x0 0x4000>, +- <0x0 0x2d10030 0x0 0x4>; +- }; +- +- mdio1: mdio@2d64000 { +- compatible = "gianfar"; +- device_type = "mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2d64000 0x0 0x4000>, +- <0x0 0x2d50030 0x0 0x4>; +- }; +- +- ptp_clock@2d10e00 { +- compatible = "fsl,etsec-ptp"; +- reg = <0x0 0x2d10e00 0x0 0xb0>; +- interrupts = ; +- fsl,tclk-period = <5>; +- fsl,tmr-prsc = <2>; +- fsl,tmr-add = <0xaaaaaaab>; +- fsl,tmr-fiper1 = <999999995>; +- fsl,tmr-fiper2 = <999999995>; +- fsl,max-adj = <499999999>; +- fsl,extts-fifo; +- }; +- +- enet0: ethernet@2d10000 { +- compatible = "fsl,etsec2"; +- device_type = "network"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&gic>; +- model = "eTSEC"; +- fsl,magic-packet; +- ranges; +- dma-coherent; +- +- queue-group@2d10000 { +- #address-cells = <2>; +- #size-cells = <2>; +- reg = <0x0 0x2d10000 0x0 0x1000>; +- interrupts = , +- , +- ; +- }; +- +- queue-group@2d14000 { +- #address-cells = <2>; +- #size-cells = <2>; +- reg = <0x0 0x2d14000 0x0 0x1000>; +- interrupts = , +- , +- ; +- }; +- }; +- +- enet1: ethernet@2d50000 { +- compatible = "fsl,etsec2"; +- device_type = "network"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&gic>; +- model = "eTSEC"; +- ranges; +- dma-coherent; +- +- queue-group@2d50000 { +- #address-cells = <2>; +- #size-cells = <2>; +- reg = <0x0 0x2d50000 0x0 0x1000>; +- interrupts = , +- , +- ; +- }; +- +- queue-group@2d54000 { +- #address-cells = <2>; +- #size-cells = <2>; +- reg = <0x0 0x2d54000 0x0 0x1000>; +- interrupts = , +- , +- ; +- }; +- }; +- +- enet2: ethernet@2d90000 { +- compatible = "fsl,etsec2"; +- device_type = "network"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&gic>; +- model = "eTSEC"; +- ranges; +- dma-coherent; +- +- queue-group@2d90000 { +- #address-cells = <2>; +- #size-cells = <2>; +- reg = <0x0 0x2d90000 0x0 0x1000>; +- interrupts = , +- , +- ; +- }; +- +- queue-group@2d94000 { +- #address-cells = <2>; +- #size-cells = <2>; +- reg = <0x0 0x2d94000 0x0 0x1000>; +- interrupts = , +- , +- ; +- }; +- }; +- +- usb2: usb@8600000 { +- compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; +- reg = <0x0 0x8600000 0x0 0x1000>; +- interrupts = ; +- dr_mode = "host"; +- phy_type = "ulpi"; +- }; +- +- usb3: usb@3100000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0x3100000 0x0 0x10000>; +- interrupts = ; +- dr_mode = "host"; +- snps,quirk-frame-length-adjustment = <0x20>; +- snps,dis_rxdet_inp3_quirk; +- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; +- }; +- +- pcie@3400000 { +- compatible = "fsl,ls1021a-pcie"; +- reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ +- 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "regs", "config"; +- interrupts = ; /* controller interrupt */ +- fsl,pcie-scfg = <&scfg 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- num-viewport = <6>; +- bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ +- 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&msi1>, <&msi2>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +- +- pcie@3500000 { +- compatible = "fsl,ls1021a-pcie"; +- reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */ +- 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "regs", "config"; +- interrupts = ; +- fsl,pcie-scfg = <&scfg 1>; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- num-viewport = <6>; +- bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ +- 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&msi1>, <&msi2>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +- +- can0: can@2a70000 { +- compatible = "fsl,ls1021ar2-flexcan"; +- reg = <0x0 0x2a70000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen 4 1>, <&clockgen 4 1>; +- clock-names = "ipg", "per"; +- big-endian; +- }; +- +- can1: can@2a80000 { +- compatible = "fsl,ls1021ar2-flexcan"; +- reg = <0x0 0x2a80000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen 4 1>, <&clockgen 4 1>; +- clock-names = "ipg", "per"; +- big-endian; +- }; +- +- can2: can@2a90000 { +- compatible = "fsl,ls1021ar2-flexcan"; +- reg = <0x0 0x2a90000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen 4 1>, <&clockgen 4 1>; +- clock-names = "ipg", "per"; +- big-endian; +- }; +- +- can3: can@2aa0000 { +- compatible = "fsl,ls1021ar2-flexcan"; +- reg = <0x0 0x2aa0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen 4 1>, <&clockgen 4 1>; +- clock-names = "ipg", "per"; +- big-endian; +- }; +- +- ocram1: sram@10000000 { +- compatible = "mmio-sram"; +- reg = <0x0 0x10000000 0x0 0x10000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x10000000 0x10000>; +- }; +- +- ocram2: sram@10010000 { +- compatible = "mmio-sram"; +- reg = <0x0 0x10010000 0x0 0x10000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x10010000 0x10000>; +- }; +- +- qdma: dma-controller@8390000 { +- compatible = "fsl,ls1021a-qdma"; +- reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */ +- <0x0 0x8389000 0x0 0x1000>, /* Status regs */ +- <0x0 0x838a000 0x0 0x2000>; /* Block regs */ +- interrupts = , +- , +- ; +- interrupt-names = "qdma-error", +- "qdma-queue0", "qdma-queue1"; +- dma-channels = <8>; +- block-number = <1>; +- block-offset = <0x1000>; +- fsl,dma-queues = <2>; +- status-sizes = <64>; +- queue-sizes = <64 64>; +- big-endian; +- }; +- +- rcpm: power-controller@1ee2140 { +- compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+"; +- reg = <0x0 0x1ee2140 0x0 0x8>; +- #fsl,rcpm-wakeup-cells = <2>; +- }; +- +- ftm_alarm0: timer0@29d0000 { +- compatible = "fsl,ls1021a-ftm-alarm"; +- reg = <0x0 0x29d0000 0x0 0x10000>; +- reg-names = "ftm"; +- fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>; +- interrupts = ; +- big-endian; +- }; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- +- thermal-sensors = <&tmu 0>; +- +- trips { +- cpu_alert: cpu-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu_crit: cpu-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert>; +- cooling-device = +- <&cpu0 THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/meson.dtsi b/scripts/dtc/include-prefixes/arm/meson.dtsi +deleted file mode 100644 +index 26eaba3fa96f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/meson.dtsi ++++ /dev/null +@@ -1,334 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-/* +- * Copyright 2014 Carlo Caione +- */ +- +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&gic>; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&saradc 8>; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- cbus: cbus@c1100000 { +- compatible = "simple-bus"; +- reg = <0xc1100000 0x200000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc1100000 0x200000>; +- +- hhi: system-controller@4000 { +- compatible = "amlogic,meson-hhi-sysctrl", +- "simple-mfd", +- "syscon"; +- reg = <0x4000 0x400>; +- }; +- +- aiu: audio-controller@5400 { +- compatible = "amlogic,aiu"; +- #sound-dai-cells = <2>; +- sound-name-prefix = "AIU"; +- reg = <0x5400 0x2ac>; +- interrupts = , +- ; +- interrupt-names = "i2s", "spdif"; +- status = "disabled"; +- }; +- +- assist: assist@7c00 { +- compatible = "amlogic,meson-mx-assist", "syscon"; +- reg = <0x7c00 0x200>; +- }; +- +- hwrng: rng@8100 { +- compatible = "amlogic,meson-rng"; +- reg = <0x8100 0x8>; +- }; +- +- uart_A: serial@84c0 { +- compatible = "amlogic,meson6-uart"; +- reg = <0x84c0 0x18>; +- interrupts = ; +- fifo-size = <128>; +- status = "disabled"; +- }; +- +- uart_B: serial@84dc { +- compatible = "amlogic,meson6-uart"; +- reg = <0x84dc 0x18>; +- interrupts = ; +- status = "disabled"; +- }; +- +- i2c_A: i2c@8500 { +- compatible = "amlogic,meson6-i2c"; +- reg = <0x8500 0x20>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pwm_ab: pwm@8550 { +- compatible = "amlogic,meson-pwm"; +- reg = <0x8550 0x10>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm_cd: pwm@8650 { +- compatible = "amlogic,meson-pwm"; +- reg = <0x8650 0x10>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- saradc: adc@8680 { +- compatible = "amlogic,meson-saradc"; +- reg = <0x8680 0x34>; +- #io-channel-cells = <1>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart_C: serial@8700 { +- compatible = "amlogic,meson6-uart"; +- reg = <0x8700 0x18>; +- interrupts = ; +- status = "disabled"; +- }; +- +- i2c_B: i2c@87c0 { +- compatible = "amlogic,meson6-i2c"; +- reg = <0x87c0 0x20>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- usb0_phy: phy@8800 { +- compatible = "amlogic,meson-mx-usb2-phy"; +- #phy-cells = <0>; +- reg = <0x8800 0x20>; +- status = "disabled"; +- }; +- +- usb1_phy: phy@8820 { +- compatible = "amlogic,meson-mx-usb2-phy"; +- #phy-cells = <0>; +- reg = <0x8820 0x20>; +- status = "disabled"; +- }; +- +- sdio: mmc@8c20 { +- compatible = "amlogic,meson-mx-sdio"; +- reg = <0x8c20 0x20>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spifc: spi@8c80 { +- compatible = "amlogic,meson6-spifc"; +- reg = <0x8c80 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- sdhc: mmc@8e00 { +- compatible = "amlogic,meson-mx-sdhc"; +- reg = <0x8e00 0x42>; +- interrupts = ; +- status = "disabled"; +- }; +- +- gpio_intc: interrupt-controller@9880 { +- compatible = "amlogic,meson-gpio-intc"; +- reg = <0x9880 0x10>; +- interrupt-controller; +- #interrupt-cells = <2>; +- amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; +- status = "disabled"; +- }; +- +- wdt: watchdog@9900 { +- compatible = "amlogic,meson6-wdt"; +- reg = <0x9900 0x8>; +- interrupts = ; +- }; +- +- timer_abcde: timer@9940 { +- compatible = "amlogic,meson6-timer"; +- reg = <0x9940 0x18>; +- interrupts = , +- , +- , +- ; +- }; +- }; +- +- L2: cache-controller@c4200000 { +- compatible = "arm,pl310-cache"; +- reg = <0xc4200000 0x1000>; +- cache-unified; +- cache-level = <2>; +- }; +- +- periph: bus@c4300000 { +- compatible = "simple-bus"; +- reg = <0xc4300000 0x10000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc4300000 0x10000>; +- +- gic: interrupt-controller@1000 { +- compatible = "arm,cortex-a9-gic"; +- reg = <0x1000 0x1000>, +- <0x100 0x100>; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- }; +- +- aobus: aobus@c8100000 { +- compatible = "simple-bus"; +- reg = <0xc8100000 0x100000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc8100000 0x100000>; +- +- ao_arc_rproc: remoteproc@1c { +- compatible= "amlogic,meson-mx-ao-arc"; +- reg = <0x1c 0x8>, <0x38 0x8>; +- reg-names = "remap", "cpu"; +- status = "disabled"; +- }; +- +- ir_receiver: ir-receiver@480 { +- compatible= "amlogic,meson6-ir"; +- reg = <0x480 0x20>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart_AO: serial@4c0 { +- compatible = "amlogic,meson6-uart", "amlogic,meson-ao-uart"; +- reg = <0x4c0 0x18>; +- interrupts = ; +- status = "disabled"; +- }; +- +- i2c_AO: i2c@500 { +- compatible = "amlogic,meson6-i2c"; +- reg = <0x500 0x20>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- rtc: rtc@740 { +- compatible = "amlogic,meson6-rtc"; +- reg = <0x740 0x14>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <1>; +- status = "disabled"; +- }; +- }; +- +- usb0: usb@c9040000 { +- compatible = "snps,dwc2"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xc9040000 0x40000>; +- interrupts = ; +- phys = <&usb0_phy>; +- phy-names = "usb2-phy"; +- g-rx-fifo-size = <512>; +- g-np-tx-fifo-size = <500>; +- g-tx-fifo-size = <256 192 128 128 128>; +- dr_mode = "host"; +- status = "disabled"; +- }; +- +- usb1: usb@c90c0000 { +- compatible = "snps,dwc2"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xc90c0000 0x40000>; +- interrupts = ; +- phys = <&usb1_phy>; +- phy-names = "usb2-phy"; +- dr_mode = "host"; +- status = "disabled"; +- }; +- +- ethmac: ethernet@c9410000 { +- compatible = "amlogic,meson6-dwmac", "snps,dwmac"; +- reg = <0xc9410000 0x10000 +- 0xc1108108 0x4>; +- interrupts = ; +- interrupt-names = "macirq"; +- status = "disabled"; +- }; +- +- ahb_sram: sram@d9000000 { +- compatible = "mmio-sram"; +- reg = <0xd9000000 0x20000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xd9000000 0x20000>; +- }; +- +- bootrom: bootrom@d9040000 { +- compatible = "amlogic,meson-mx-bootrom", "syscon"; +- reg = <0xd9040000 0x10000>; +- }; +- +- secbus: secbus@da000000 { +- compatible = "simple-bus"; +- reg = <0xda000000 0x6000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xda000000 0x6000>; +- +- efuse: nvmem@0 { +- compatible = "amlogic,meson6-efuse"; +- reg = <0x0 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- }; +- }; +- +- thermal_sensor: thermal-sensor { +- compatible = "generic-adc-thermal"; +- #thermal-sensor-cells = <0>; +- io-channels = <&saradc 8>; +- io-channel-names = "sensor-channel"; +- }; +- +- xtal: xtal-clk { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "xtal"; +- #clock-cells = <0>; +- }; +-}; /* end of / */ +diff --git a/scripts/dtc/include-prefixes/arm/meson6-atv1200.dts b/scripts/dtc/include-prefixes/arm/meson6-atv1200.dts +deleted file mode 100644 +index 98e1c94c0261..000000000000 +--- a/scripts/dtc/include-prefixes/arm/meson6-atv1200.dts ++++ /dev/null +@@ -1,33 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-/* +- * Copyright 2014 Carlo Caione +- */ +- +-/dts-v1/; +-#include "meson6.dtsi" +- +-/ { +- model = "Geniatech ATV1200"; +- compatible = "geniatech,atv1200", "amlogic,meson6"; +- +- aliases { +- serial0 = &uart_AO; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x40000000 0x80000000>; +- }; +-}; +- +-&uart_AO { +- status = "okay"; +-}; +- +-ðmac { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/meson6.dtsi b/scripts/dtc/include-prefixes/arm/meson6.dtsi +deleted file mode 100644 +index 4716030a48d0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/meson6.dtsi ++++ /dev/null +@@ -1,73 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-/* +- * Copyright 2014 Carlo Caione +- */ +- +-#include "meson.dtsi" +- +-/ { +- model = "Amlogic Meson6 SoC"; +- compatible = "amlogic,meson6"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- reg = <0x200>; +- }; +- +- cpu@201 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- reg = <0x201>; +- }; +- }; +- +- apb2: bus@d0000000 { +- compatible = "simple-bus"; +- reg = <0xd0000000 0x40000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xd0000000 0x40000>; +- }; +- +- clk81: clk@0 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <200000000>; +- }; +-}; /* end of / */ +- +-&efuse { +- status = "disabled"; +-}; +- +-&timer_abcde { +- clocks = <&xtal>, <&clk81>; +- clock-names = "xtal", "pclk"; +-}; +- +-&uart_AO { +- clocks = <&xtal>, <&clk81>, <&clk81>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&uart_A { +- clocks = <&xtal>, <&clk81>, <&clk81>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&uart_B { +- clocks = <&xtal>, <&clk81>, <&clk81>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&uart_C { +- clocks = <&xtal>, <&clk81>, <&clk81>; +- clock-names = "xtal", "pclk", "baud"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/meson8-minix-neo-x8.dts b/scripts/dtc/include-prefixes/arm/meson8-minix-neo-x8.dts +deleted file mode 100644 +index 61ec929ab86e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/meson8-minix-neo-x8.dts ++++ /dev/null +@@ -1,97 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-/* +- * Copyright 2014 Beniamino Galvani +- */ +- +-/dts-v1/; +-#include +-#include "meson8.dtsi" +- +-/ { +- model = "MINIX NEO-X8"; +- compatible = "minix,neo-x8", "amlogic,meson8"; +- +- aliases { +- serial0 = &uart_AO; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x40000000 0x80000000>; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- blue { +- label = "x8:blue:power"; +- gpios = <&gpio_ao GPIO_TEST_N GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&i2c_AO { +- status = "okay"; +- pinctrl-0 = <&i2c_ao_pins>; +- pinctrl-names = "default"; +- +- pmic@32 { +- compatible = "ricoh,rn5t618"; +- reg = <0x32>; +- system-power-controller; +- +- regulators { +- }; +- }; +- +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +-}; +- +-&spifc { +- status = "okay"; +- pinctrl-0 = <&spi_nor_pins>; +- pinctrl-names = "default"; +- +- spi-flash@0 { +- compatible = "mxicy,mx25l1606e"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- spi-max-frequency = <30000000>; +- +- partition@0 { +- label = "boot"; +- reg = <0x0 0x100000>; +- }; +- +- partition@100000 { +- label = "env"; +- reg = <0x100000 0x10000>; +- }; +- }; +-}; +- +-&ir_receiver { +- status = "okay"; +- pinctrl-0 = <&ir_recv_pins>; +- pinctrl-names = "default"; +-}; +- +-ðmac { +- status = "okay"; +- pinctrl-0 = <ð_pins>; +- pnictrl-names = "default"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/meson8.dtsi b/scripts/dtc/include-prefixes/arm/meson8.dtsi +deleted file mode 100644 +index 9997a5d0333a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/meson8.dtsi ++++ /dev/null +@@ -1,786 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-/* +- * Copyright 2014 Carlo Caione +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include "meson.dtsi" +- +-/ { +- model = "Amlogic Meson8 SoC"; +- compatible = "amlogic,meson8"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- reg = <0x200>; +- enable-method = "amlogic,meson8-smp"; +- resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPUCLK>; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- +- cpu1: cpu@201 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- reg = <0x201>; +- enable-method = "amlogic,meson8-smp"; +- resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPUCLK>; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- +- cpu2: cpu@202 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- reg = <0x202>; +- enable-method = "amlogic,meson8-smp"; +- resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPUCLK>; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- +- cpu3: cpu@203 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- reg = <0x203>; +- enable-method = "amlogic,meson8-smp"; +- resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPUCLK>; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- }; +- +- cpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-96000000 { +- opp-hz = /bits/ 64 <96000000>; +- opp-microvolt = <825000>; +- }; +- opp-192000000 { +- opp-hz = /bits/ 64 <192000000>; +- opp-microvolt = <825000>; +- }; +- opp-312000000 { +- opp-hz = /bits/ 64 <312000000>; +- opp-microvolt = <825000>; +- }; +- opp-408000000 { +- opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <825000>; +- }; +- opp-504000000 { +- opp-hz = /bits/ 64 <504000000>; +- opp-microvolt = <825000>; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <850000>; +- }; +- opp-720000000 { +- opp-hz = /bits/ 64 <720000000>; +- opp-microvolt = <850000>; +- }; +- opp-816000000 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <875000>; +- }; +- opp-1008000000 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <925000>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <975000>; +- }; +- opp-1416000000 { +- opp-hz = /bits/ 64 <1416000000>; +- opp-microvolt = <1025000>; +- }; +- opp-1608000000 { +- opp-hz = /bits/ 64 <1608000000>; +- opp-microvolt = <1100000>; +- }; +- opp-1800000000 { +- status = "disabled"; +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <1125000>; +- }; +- opp-1992000000 { +- status = "disabled"; +- opp-hz = /bits/ 64 <1992000000>; +- opp-microvolt = <1150000>; +- }; +- }; +- +- gpu_opp_table: gpu-opp-table { +- compatible = "operating-points-v2"; +- +- opp-182142857 { +- opp-hz = /bits/ 64 <182142857>; +- opp-microvolt = <1150000>; +- }; +- opp-318750000 { +- opp-hz = /bits/ 64 <318750000>; +- opp-microvolt = <1150000>; +- }; +- opp-425000000 { +- opp-hz = /bits/ 64 <425000000>; +- opp-microvolt = <1150000>; +- }; +- opp-510000000 { +- opp-hz = /bits/ 64 <510000000>; +- opp-microvolt = <1150000>; +- }; +- opp-637500000 { +- opp-hz = /bits/ 64 <637500000>; +- opp-microvolt = <1150000>; +- turbo-mode; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* 2 MiB reserved for Hardware ROM Firmware? */ +- hwrom@0 { +- reg = <0x0 0x200000>; +- no-map; +- }; +- +- /* +- * 1 MiB reserved for the "ARM Power Firmware": this is ARM +- * code which is responsible for system suspend. It loads a +- * piece of ARC code ("arc_power" in the vendor u-boot tree) +- * into SRAM, executes that and shuts down the (last) ARM core. +- * The arc_power firmware then checks various wakeup sources +- * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or +- * simply the power key) and re-starts the ARM core once it +- * detects a wakeup request. +- */ +- power-firmware@4f00000 { +- reg = <0x4f00000 0x100000>; +- no-map; +- }; +- }; +- +- thermal-zones { +- soc { +- polling-delay-passive = <250>; /* milliseconds */ +- polling-delay = <1000>; /* milliseconds */ +- thermal-sensors = <&thermal_sensor>; +- +- cooling-maps { +- map0 { +- trip = <&soc_passive>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- +- map1 { +- trip = <&soc_hot>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- +- trips { +- soc_passive: soc-passive { +- temperature = <80000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- +- soc_hot: soc-hot { +- temperature = <90000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "hot"; +- }; +- +- soc_critical: soc-critical { +- temperature = <110000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- }; +- }; +- +- mmcbus: bus@c8000000 { +- compatible = "simple-bus"; +- reg = <0xc8000000 0x8000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc8000000 0x8000>; +- +- ddr_clkc: clock-controller@400 { +- compatible = "amlogic,meson8-ddr-clkc"; +- reg = <0x400 0x20>; +- clocks = <&xtal>; +- clock-names = "xtal"; +- #clock-cells = <1>; +- }; +- +- dmcbus: bus@6000 { +- compatible = "simple-bus"; +- reg = <0x6000 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6000 0x400>; +- +- canvas: video-lut@20 { +- compatible = "amlogic,meson8-canvas", +- "amlogic,canvas"; +- reg = <0x20 0x14>; +- }; +- }; +- }; +- +- apb: bus@d0000000 { +- compatible = "simple-bus"; +- reg = <0xd0000000 0x200000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xd0000000 0x200000>; +- +- mali: gpu@c0000 { +- compatible = "amlogic,meson8-mali", "arm,mali-450"; +- reg = <0xc0000 0x40000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "gp", "gpmmu", "pp", "pmu", +- "pp0", "ppmmu0", "pp1", "ppmmu1", +- "pp2", "ppmmu2", "pp4", "ppmmu4", +- "pp5", "ppmmu5", "pp6", "ppmmu6"; +- resets = <&reset RESET_MALI>; +- +- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; +- clock-names = "bus", "core"; +- +- assigned-clocks = <&clkc CLKID_MALI>; +- assigned-clock-rates = <318750000>; +- +- operating-points-v2 = <&gpu_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- }; +-}; /* end of / */ +- +-&aiu { +- compatible = "amlogic,aiu-meson8", "amlogic,aiu"; +- clocks = <&clkc CLKID_AIU_GLUE>, +- <&clkc CLKID_I2S_OUT>, +- <&clkc CLKID_AOCLK_GATE>, +- <&clkc CLKID_CTS_AMCLK>, +- <&clkc CLKID_MIXER_IFACE>, +- <&clkc CLKID_IEC958>, +- <&clkc CLKID_IEC958_GATE>, +- <&clkc CLKID_CTS_MCLK_I958>, +- <&clkc CLKID_CTS_I958>; +- clock-names = "pclk", +- "i2s_pclk", +- "i2s_aoclk", +- "i2s_mclk", +- "i2s_mixer", +- "spdif_pclk", +- "spdif_aoclk", +- "spdif_mclk", +- "spdif_mclk_sel"; +- resets = <&reset RESET_AIU>; +-}; +- +-&aobus { +- pmu: pmu@e0 { +- compatible = "amlogic,meson8-pmu", "syscon"; +- reg = <0xe0 0x18>; +- }; +- +- pinctrl_aobus: pinctrl@84 { +- compatible = "amlogic,meson8-aobus-pinctrl"; +- reg = <0x84 0xc>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gpio_ao: ao-bank@14 { +- reg = <0x14 0x4>, +- <0x2c 0x4>, +- <0x24 0x8>; +- reg-names = "mux", "pull", "gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl_aobus 0 0 16>; +- }; +- +- i2s_am_clk_pins: i2s-am-clk-out { +- mux { +- groups = "i2s_am_clk_out_ao"; +- function = "i2s_ao"; +- bias-disable; +- }; +- }; +- +- i2s_out_ao_clk_pins: i2s-ao-clk-out { +- mux { +- groups = "i2s_ao_clk_out_ao"; +- function = "i2s_ao"; +- bias-disable; +- }; +- }; +- +- i2s_out_lr_clk_pins: i2s-lr-clk-out { +- mux { +- groups = "i2s_lr_clk_out_ao"; +- function = "i2s_ao"; +- bias-disable; +- }; +- }; +- +- i2s_out_ch01_ao_pins: i2s-out-ch01 { +- mux { +- groups = "i2s_out_ch01_ao"; +- function = "i2s_ao"; +- bias-disable; +- }; +- }; +- +- uart_ao_a_pins: uart_ao_a { +- mux { +- groups = "uart_tx_ao_a", "uart_rx_ao_a"; +- function = "uart_ao"; +- bias-disable; +- }; +- }; +- +- i2c_ao_pins: i2c_mst_ao { +- mux { +- groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; +- function = "i2c_mst_ao"; +- bias-disable; +- }; +- }; +- +- ir_recv_pins: remote { +- mux { +- groups = "remote_input"; +- function = "remote"; +- bias-disable; +- }; +- }; +- +- pwm_f_ao_pins: pwm-f-ao { +- mux { +- groups = "pwm_f_ao"; +- function = "pwm_f_ao"; +- bias-disable; +- }; +- }; +- }; +-}; +- +-&ao_arc_rproc { +- compatible= "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc"; +- amlogic,secbus2 = <&secbus2>; +- sram = <&ao_arc_sram>; +- resets = <&reset RESET_MEDIA_CPU>; +- clocks = <&clkc CLKID_AO_MEDIA_CPU>; +-}; +- +-&cbus { +- reset: reset-controller@4404 { +- compatible = "amlogic,meson8b-reset"; +- reg = <0x4404 0x9c>; +- #reset-cells = <1>; +- }; +- +- analog_top: analog-top@81a8 { +- compatible = "amlogic,meson8-analog-top", "syscon"; +- reg = <0x81a8 0x14>; +- }; +- +- pwm_ef: pwm@86c0 { +- compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; +- reg = <0x86c0 0x10>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- clock-measure@8758 { +- compatible = "amlogic,meson8-clk-measure"; +- reg = <0x8758 0x1c>; +- }; +- +- pinctrl_cbus: pinctrl@9880 { +- compatible = "amlogic,meson8-cbus-pinctrl"; +- reg = <0x9880 0x10>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gpio: banks@80b0 { +- reg = <0x80b0 0x28>, +- <0x80e8 0x18>, +- <0x8120 0x18>, +- <0x8030 0x30>; +- reg-names = "mux", "pull", "pull-enable", "gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl_cbus 0 0 120>; +- }; +- +- sd_a_pins: sd-a { +- mux { +- groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", +- "sd_d3_a", "sd_clk_a", "sd_cmd_a"; +- function = "sd_a"; +- bias-disable; +- }; +- }; +- +- sd_b_pins: sd-b { +- mux { +- groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", +- "sd_d3_b", "sd_clk_b", "sd_cmd_b"; +- function = "sd_b"; +- bias-disable; +- }; +- }; +- +- sd_c_pins: sd-c { +- mux { +- groups = "sd_d0_c", "sd_d1_c", "sd_d2_c", +- "sd_d3_c", "sd_clk_c", "sd_cmd_c"; +- function = "sd_c"; +- bias-disable; +- }; +- }; +- +- sdxc_b_pins: sdxc-b { +- mux { +- groups = "sdxc_d0_b", "sdxc_d13_b", +- "sdxc_clk_b", "sdxc_cmd_b"; +- function = "sdxc_b"; +- bias-pull-up; +- }; +- }; +- +- spdif_out_pins: spdif-out { +- mux { +- groups = "spdif_out"; +- function = "spdif"; +- bias-disable; +- }; +- }; +- +- spi_nor_pins: nor { +- mux { +- groups = "nor_d", "nor_q", "nor_c", "nor_cs"; +- function = "nor"; +- bias-disable; +- }; +- }; +- +- eth_pins: ethernet { +- mux { +- groups = "eth_tx_clk_50m", "eth_tx_en", +- "eth_txd1", "eth_txd0", +- "eth_rx_clk_in", "eth_rx_dv", +- "eth_rxd1", "eth_rxd0", "eth_mdio", +- "eth_mdc"; +- function = "ethernet"; +- bias-disable; +- }; +- }; +- +- pwm_e_pins: pwm-e { +- mux { +- groups = "pwm_e"; +- function = "pwm_e"; +- bias-disable; +- }; +- }; +- +- uart_a1_pins: uart-a1 { +- mux { +- groups = "uart_tx_a1", +- "uart_rx_a1"; +- function = "uart_a"; +- bias-disable; +- }; +- }; +- +- uart_a1_cts_rts_pins: uart-a1-cts-rts { +- mux { +- groups = "uart_cts_a1", +- "uart_rts_a1"; +- function = "uart_a"; +- bias-disable; +- }; +- }; +- }; +-}; +- +-&ahb_sram { +- ao_arc_sram: ao-arc-sram@0 { +- compatible = "amlogic,meson8-ao-arc-sram"; +- reg = <0x0 0x8000>; +- pool; +- }; +- +- smp-sram@1ff80 { +- compatible = "amlogic,meson8-smp-sram"; +- reg = <0x1ff80 0x8>; +- }; +-}; +- +-&efuse { +- compatible = "amlogic,meson8-efuse"; +- clocks = <&clkc CLKID_EFUSE>; +- clock-names = "core"; +- +- temperature_calib: calib@1f4 { +- /* only the upper two bytes are relevant */ +- reg = <0x1f4 0x4>; +- }; +-}; +- +-ðmac { +- clocks = <&clkc CLKID_ETH>; +- clock-names = "stmmaceth"; +- +- power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>; +-}; +- +-&gpio_intc { +- compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc"; +- status = "okay"; +-}; +- +-&hhi { +- clkc: clock-controller { +- compatible = "amlogic,meson8-clkc"; +- clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; +- clock-names = "xtal", "ddr_pll"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pwrc: power-controller { +- compatible = "amlogic,meson8-pwrc"; +- #power-domain-cells = <1>; +- amlogic,ao-sysctrl = <&pmu>; +- clocks = <&clkc CLKID_VPU>; +- clock-names = "vpu"; +- assigned-clocks = <&clkc CLKID_VPU>; +- assigned-clock-rates = <364285714>; +- }; +-}; +- +-&hwrng { +- compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; +- clocks = <&clkc CLKID_RNG0>; +- clock-names = "core"; +-}; +- +-&i2c_AO { +- clocks = <&clkc CLKID_CLK81>; +-}; +- +-&i2c_A { +- clocks = <&clkc CLKID_CLK81>; +-}; +- +-&i2c_B { +- clocks = <&clkc CLKID_CLK81>; +-}; +- +-&L2 { +- arm,data-latency = <3 3 3>; +- arm,tag-latency = <2 2 2>; +- arm,filter-ranges = <0x100000 0xc0000000>; +- prefetch-data = <1>; +- prefetch-instr = <1>; +- arm,shared-override; +-}; +- +-&periph { +- scu@0 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0x0 0x100>; +- }; +- +- timer@200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0x200 0x20>; +- interrupts = ; +- clocks = <&clkc CLKID_PERIPH>; +- +- /* +- * the arm_global_timer driver currently does not handle clock +- * rate changes. Keep it disabled for now. +- */ +- status = "disabled"; +- }; +- +- timer@600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x600 0x20>; +- interrupts = ; +- clocks = <&clkc CLKID_PERIPH>; +- }; +-}; +- +-&pwm_ab { +- compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; +-}; +- +-&pwm_cd { +- compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; +-}; +- +-&rtc { +- compatible = "amlogic,meson8-rtc"; +- resets = <&reset RESET_RTC>; +-}; +- +-&saradc { +- compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; +- clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; +- clock-names = "clkin", "core"; +- amlogic,hhi-sysctrl = <&hhi>; +- nvmem-cells = <&temperature_calib>; +- nvmem-cell-names = "temperature_calib"; +-}; +- +-&sdhc { +- compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; +- clocks = <&xtal>, +- <&clkc CLKID_FCLK_DIV4>, +- <&clkc CLKID_FCLK_DIV3>, +- <&clkc CLKID_FCLK_DIV5>, +- <&clkc CLKID_SDHC>; +- clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; +-}; +- +-&secbus { +- secbus2: system-controller@4000 { +- compatible = "amlogic,meson8-secbus2", "syscon"; +- reg = <0x4000 0x2000>; +- }; +-}; +- +-&sdio { +- compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; +- clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; +- clock-names = "core", "clkin"; +-}; +- +-&spifc { +- clocks = <&clkc CLKID_CLK81>; +-}; +- +-&timer_abcde { +- clocks = <&xtal>, <&clkc CLKID_CLK81>; +- clock-names = "xtal", "pclk"; +-}; +- +-&uart_AO { +- compatible = "amlogic,meson8-uart", "amlogic,meson-ao-uart"; +- clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&uart_A { +- compatible = "amlogic,meson8-uart"; +- clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&uart_B { +- compatible = "amlogic,meson8-uart"; +- clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&uart_C { +- compatible = "amlogic,meson8-uart"; +- clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&usb0 { +- compatible = "amlogic,meson8-usb", "snps,dwc2"; +- clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; +- clock-names = "otg"; +-}; +- +-&usb1 { +- compatible = "amlogic,meson8-usb", "snps,dwc2"; +- clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; +- clock-names = "otg"; +-}; +- +-&usb0_phy { +- compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; +- clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; +- clock-names = "usb_general", "usb"; +- resets = <&reset RESET_USB_OTG>; +-}; +- +-&usb1_phy { +- compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; +- clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; +- clock-names = "usb_general", "usb"; +- resets = <&reset RESET_USB_OTG>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/meson8b-ec100.dts b/scripts/dtc/include-prefixes/arm/meson8b-ec100.dts +deleted file mode 100644 +index 77d4beeb8010..000000000000 +--- a/scripts/dtc/include-prefixes/arm/meson8b-ec100.dts ++++ /dev/null +@@ -1,479 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Martin Blumenstingl . +- */ +- +-/dts-v1/; +- +-#include +-#include +- +-#include "meson8b.dtsi" +- +-/ { +- model = "Endless Computers Endless Mini"; +- compatible = "endless,ec100", "amlogic,meson8b"; +- +- aliases { +- serial0 = &uart_AO; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x40000000 0x40000000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys-polled"; +- #address-cells = <1>; +- #size-cells = <0>; +- poll-interval = <100>; +- +- pal-switch { +- label = "pal"; +- linux,input-type = ; +- linux,code = ; +- gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>; +- }; +- +- ntsc-switch { +- label = "ntsc"; +- linux,input-type = ; +- linux,code = ; +- gpios = <&gpio GPIOH_8 GPIO_ACTIVE_HIGH>; +- }; +- +- power-button { +- label = "power"; +- linux,code = ; +- gpios = <&gpio GPIOH_9 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- /* +- * shutdown is managed by the EC (embedded micro-controller) +- * which is configured through GPIOAO_2 (poweroff GPIO) and +- * GPIOAO_7 (power LED, which has to go LOW as well). +- */ +- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; +- timeout-ms = <20000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- power { +- label = "ec100:red:power"; +- /* +- * Needs to go LOW (together with the poweroff GPIO) +- * during shutdown to allow the EC (embedded +- * micro-controller) to shutdown the system. Setting +- * the output to LOW signals the EC to start a +- * "breathing"/pulsing effect until the power is fully +- * turned off. +- */ +- gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- rtc32k_xtal: rtc32k-xtal-clk { +- /* X2 in the schematics */ +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-output-names = "RTC32K"; +- #clock-cells = <0>; +- }; +- +- sound { +- compatible = "amlogic,gx-sound-card"; +- model = "M8B-EC100"; +- +- assigned-clocks = <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>, +- <&clkc CLKID_MPLL2>; +- assigned-clock-rates = <270950400>, +- <294912000>, +- <393216000>; +- +- dai-link-0 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; +- }; +- +- dai-link-1 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; +- dai-format = "i2s"; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&rt5640>; +- }; +- }; +- }; +- +- usb_vbus: regulator-usb-vbus { +- /* +- * Silergy SY6288CCAC-GP 2A Power Distribution Switch. +- */ +- compatible = "regulator-fixed"; +- +- regulator-name = "USB_VBUS"; +- +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- vin-supply = <&vcc_5v>; +- +- /* +- * signal name from the schematics: USB_PWR_EN +- */ +- gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vcc_5v: regulator-vcc5v { +- /* +- * supplied by the main power input which called PWR_5V_STB +- * in the schematics +- */ +- compatible = "regulator-fixed"; +- +- regulator-name = "VCC5V"; +- +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- /* +- * signal name from the schematics: 3V3_5V_EN +- */ +- gpio = <&gpio GPIODV_29 GPIO_ACTIVE_LOW>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcck: regulator-vcck { +- /* +- * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz +- * Synchronous Step Down Regulator. +- */ +- compatible = "pwm-regulator"; +- +- regulator-name = "VCCK"; +- regulator-min-microvolt = <860000>; +- regulator-max-microvolt = <1140000>; +- +- pwm-supply = <&vcc_5v>; +- +- pwms = <&pwm_cd 0 1148 0>; +- pwm-dutycycle-range = <100 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcc_1v8: regulator-vcc1v8 { +- /* +- * ABLIC S-1339D18-M5001-GP +- */ +- compatible = "regulator-fixed"; +- +- regulator-name = "VCC1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- vin-supply = <&vcc_3v3>; +- }; +- +- vcc_3v3: regulator-vcc3v3 { +- /* +- * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz +- * Synchronous Step Down Regulator. Also called +- * VDDIO_AO3.3V in the schematics. +- */ +- compatible = "regulator-fixed"; +- +- regulator-name = "VCC3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- vin-supply = <&vcc_5v>; +- }; +- +- vcc_ddr3: regulator-vcc-ddr3 { +- /* +- * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz +- * Synchronous Step Down Regulator. Also called +- * DDR3_1.5V in the schematics. +- */ +- compatible = "regulator-fixed"; +- +- regulator-name = "VCC_DDR3_1V5"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- +- vin-supply = <&vcc_5v>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcc_rtc: regulator-vcc-rtc { +- /* +- * Global Mixed-mode Technology Inc. G918T12U-GP +- */ +- compatible = "regulator-fixed"; +- +- regulator-name = "VCC_RTC"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- +- /* +- * When the board is powered then the input is VCC3V3, +- * otherwise power is taken from the coin cell battery. +- */ +- vin-supply = <&vcc_3v3>; +- }; +- +- vddee: regulator-vddee { +- /* +- * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz +- * Synchronous Step Down Regulator. Also called VDDAO +- * in a part of the schematics. +- */ +- compatible = "pwm-regulator"; +- +- regulator-name = "VDDEE"; +- regulator-min-microvolt = <860000>; +- regulator-max-microvolt = <1140000>; +- +- pwm-supply = <&vcc_5v>; +- +- pwms = <&pwm_cd 1 1148 0>; +- pwm-dutycycle-range = <100 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&aiu { +- status = "okay"; +- +- pinctrl-0 = <&i2s_am_clk_pins>, <&i2s_out_ao_clk_pins>, +- <&i2s_out_lr_clk_pins>, <&i2s_out_ch01_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&cpu0 { +- cpu-supply = <&vcck>; +-}; +- +-ðmac { +- status = "okay"; +- +- pinctrl-0 = <ð_rmii_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <ð_phy0>; +- phy-mode = "rmii"; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eth_phy0: ethernet-phy@0 { +- /* IC Plus IP101A/G (0x02430c54) */ +- reg = <0>; +- +- reset-assert-us = <10000>; +- reset-deassert-us = <10000>; +- reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; +- +- icplus,select-interrupt; +- interrupt-parent = <&gpio_intc>; +- /* GPIOH_3 */ +- interrupts = <17 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +-}; +- +-&i2c_A { +- status = "okay"; +- pinctrl-0 = <&i2c_a_pins>; +- pinctrl-names = "default"; +- +- rt5640: codec@1c { +- compatible = "realtek,rt5640"; +- +- reg = <0x1c>; +- +- #sound-dai-cells = <0>; +- +- interrupt-parent = <&gpio_intc>; +- interrupts = <13 IRQ_TYPE_EDGE_BOTH>; /* GPIOAO_13 */ +- +- /* +- * TODO: realtek,ldo1-en-gpios is connected to GPIO_BSD_EN. +- * We currently cannot configure this pin correctly. +- * Luckily for us it's in the "right" state by default. +- */ +- realtek,in1-differential; +- }; +-}; +- +-&mali { +- mali-supply = <&vddee>; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vcc_1v8>; +-}; +- +-&sdhc { +- status = "okay"; +- +- pinctrl-0 = <&sdxc_c_pins>; +- pinctrl-names = "default"; +- +- bus-width = <8>; +- max-frequency = <50000000>; +- +- cap-mmc-highspeed; +- disable-wp; +- non-removable; +- no-sdio; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&vcc_3v3>; +-}; +- +-&sdio { +- status = "okay"; +- +- pinctrl-0 = <&sd_b_pins>; +- pinctrl-names = "default"; +- +- /* SD card */ +- sd_card_slot: slot@1 { +- compatible = "mmc-slot"; +- reg = <1>; +- status = "okay"; +- +- bus-width = <4>; +- no-sdio; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&vcc_3v3>; +- }; +-}; +- +-&gpio_ao { +- gpio-line-names = "Linux_TX", "Linux_RX", +- "SLP_S5_N", "USB2_OC_FLAG#", +- "HUB_RST", "USB_PWR_EN", +- "I2S_IN", "SLP_S1_N", +- "TCK", "TMS", "TDI", "TDO", +- "HDMI_CEC", "5640_IRQ", +- "MUTE", "S805_TEST#"; +-}; +- +-&gpio { +- gpio-line-names = /* Bank GPIOX */ +- "WIFI_SD_D0", "WIFI_SD_D1", "WIFI_SD_D2", +- "WIFI_SD_D3", "BTPCM_DOUT", "BTPCM_DIN", +- "BTPCM_SYNC", "BTPCM_CLK", "WIFI_SD_CLK", +- "WIFI_SD_CMD", "WIFI_32K", "WIFI_PWREN", +- "UART_B_TX", "UART_B_RX", "UART_B_CTS_N", +- "UART_B_RTS_N", "BT_EN", "WIFI_WAKE_HOST", +- /* Bank GPIOY */ +- "", "", "", "", "", "", "", "", "", "", +- "", "", +- /* Bank GPIODV */ +- "VCCK_PWM_C", "I2C_SDA_A", "I2C_SCL_A", +- "I2C_SDA_B", "I2C_SCL_B", "VDDEE_PWM_D", +- "VDDEE_PWM 3V3_5V_EN", +- /* Bank GPIOH */ +- "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL", +- "RMII_IRQ", "RMII_RST#", "RMII_TXD1", +- "RMII_TXD0", "AV_select_1", "AV_select_2", +- "MCU_Control_S", +- /* Bank CARD */ +- "SD_D1_B", "SD_D0_B", "SD_CLK_8726MX", +- "SD_CMD_8726MX", "SD_D3_B", "SD_D2_B", +- "CARD_EN_DET (CARD_DET)", +- /* Bank BOOT */ +- "NAND_D0 (EMMC)", "NAND_D1 (EMMC)", +- "NAND_D2 (EMMC)", "NAND_D3 (EMMC)", +- "NAND_D4 (EMMC)", "NAND_D5 (EMMC)", +- "NAND_D6 (EMMC)", "NAND_D7 (EMMC)", +- "NAND_CS1 (EMMC)", "NAND_CS2 iNAND_RS1 (EMMC)", +- "NAND_nR/B iNAND_CMD (EMMC)", "NAND_ALE (EMMC)", +- "NAND_CLE (EMMC)", "nRE_S1 NAND_nRE (EMMC)", +- "nWE_S1 NAND_nWE (EMMC)", "", "", "SPI_CS", +- /* Bank DIF */ +- "RMII_RXD1", "RMII_RXD0", "RMII_CRS_DV", +- "RMII_50M_IN", "GPIODIF_4", "GPIODIF_5", +- "RMII_TXEN", "CPUETH_25MOUT", "RMII_MDC", +- "RMII_MDIO"; +-}; +- +-&pwm_cd { +- status = "okay"; +- pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>, <&xtal>; +- clock-names = "clkin0", "clkin1"; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&rtc32k_xtal>; +- vdd-supply = <&vcc_rtc>; +-}; +- +-/* exposed through the pin headers labeled "URDUG1" on the top of the PCB */ +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-/* +- * connected to the Bluetooth part of the RTL8723BS SDIO wifi / Bluetooth +- * combo chip. This is only available on the variant with 2GB RAM. +- */ +-&uart_B { +- status = "okay"; +- pinctrl-0 = <&uart_b0_pins>, <&uart_b0_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +-}; +- +-&usb1 { +- status = "okay"; +- vbus-supply = <&usb_vbus>; +-}; +- +-&usb1_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/meson8b-mxq.dts b/scripts/dtc/include-prefixes/arm/meson8b-mxq.dts +deleted file mode 100644 +index 7adedd3258c3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/meson8b-mxq.dts ++++ /dev/null +@@ -1,189 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-/* +- * Copyright 2015 Endless Mobile, Inc. +- * Author: Carlo Caione +- */ +- +-/dts-v1/; +- +-#include +- +-#include "meson8b.dtsi" +- +-/ { +- model = "TRONFY MXQ S805"; +- compatible = "tronfy,mxq", "amlogic,meson8b"; +- +- aliases { +- serial0 = &uart_AO; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x40000000 0x40000000>; +- }; +- +- vcck: regulator-vcck { +- compatible = "pwm-regulator"; +- +- regulator-name = "VCCK"; +- regulator-min-microvolt = <860000>; +- regulator-max-microvolt = <1140000>; +- +- pwm-supply = <&vcc_5v>; +- +- pwms = <&pwm_cd 0 1148 0>; +- pwm-dutycycle-range = <100 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcc_1v8: regulator-vcc1v8 { +- compatible = "regulator-fixed"; +- +- regulator-name = "VCC1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- vin-supply = <&vcc_3v3>; +- }; +- +- vcc_3v3: regulator-vcc3v3 { +- compatible = "regulator-fixed"; +- +- regulator-name = "VCC3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- vin-supply = <&vcc_5v>; +- }; +- +- vcc_5v: regulator-vcc5v { +- compatible = "regulator-fixed"; +- +- regulator-name = "VCC5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vddee: regulator-vddee { +- compatible = "pwm-regulator"; +- +- regulator-name = "VDDEE"; +- regulator-min-microvolt = <860000>; +- regulator-max-microvolt = <1140000>; +- +- pwm-supply = <&vcc_5v>; +- +- pwms = <&pwm_cd 1 1148 0>; +- pwm-dutycycle-range = <100 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vcck>; +-}; +- +-ðmac { +- status = "okay"; +- +- pinctrl-0 = <ð_rmii_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <ð_phy0>; +- phy-mode = "rmii"; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eth_phy0: ethernet-phy@0 { +- /* IC Plus IP101A/G (0x02430c54) */ +- reg = <0>; +- +- reset-assert-us = <10000>; +- reset-deassert-us = <10000>; +- reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; +- +- icplus,select-interrupt; +- interrupt-parent = <&gpio_intc>; +- /* GPIOH_3 */ +- interrupts = <17 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +-}; +- +-&mali { +- mali-supply = <&vddee>; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vcc_1v8>; +-}; +- +-&sdio { +- status = "okay"; +- +- pinctrl-0 = <&sd_b_pins>; +- pinctrl-names = "default"; +- +- /* SD card */ +- sd_card_slot: slot@1 { +- compatible = "mmc-slot"; +- reg = <1>; +- status = "okay"; +- +- bus-width = <4>; +- no-sdio; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&vcc_3v3>; +- }; +-}; +- +-&pwm_cd { +- status = "okay"; +- pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>, <&xtal>; +- clock-names = "clkin0", "clkin1"; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb0_phy { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&usb1_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/meson8b-odroidc1.dts b/scripts/dtc/include-prefixes/arm/meson8b-odroidc1.dts +deleted file mode 100644 +index 04356bc639fa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/meson8b-odroidc1.dts ++++ /dev/null +@@ -1,385 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-/* +- * Copyright 2015 Endless Mobile, Inc. +- * Author: Carlo Caione +- */ +- +-/dts-v1/; +-#include "meson8b.dtsi" +-#include +- +-/ { +- model = "Hardkernel ODROID-C1"; +- compatible = "hardkernel,odroid-c1", "amlogic,meson8b"; +- +- aliases { +- serial0 = &uart_AO; +- mmc0 = &sd_card_slot; +- mmc1 = &sdhc; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x40000000 0x40000000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- blue { +- label = "c1:blue:alive"; +- gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- }; +- +- p5v0: regulator-p5v0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "P5V0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- tflash_vdd: regulator-tflash_vdd { +- /* +- * signal name from schematics: TFLASH_VDD_EN +- */ +- compatible = "regulator-fixed"; +- +- regulator-name = "TFLASH_VDD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- vin-supply = <&vcc_3v3>; +- +- gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- tf_io: gpio-regulator-tf_io { +- compatible = "regulator-gpio"; +- +- regulator-name = "TF_IO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- vin-supply = <&vcc_3v3>; +- +- /* +- * signal name from schematics: TF_3V3N_1V8_EN +- */ +- gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; +- gpios-states = <0>; +- +- states = <3300000 0 +- 1800000 1>; +- }; +- +- rtc32k_xtal: rtc32k-xtal-clk { +- /* X3 in the schematics */ +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-output-names = "RTC32K"; +- #clock-cells = <0>; +- }; +- +- vcc_1v8: regulator-vcc-1v8 { +- /* +- * RICHTEK RT9179 configured for a fixed output voltage of +- * 1.8V. This supplies not only VCC1V8 but also IOREF_1V8 and +- * VDD1V8 according to the schematics. +- */ +- compatible = "regulator-fixed"; +- +- regulator-name = "VCC1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- vin-supply = <&p5v0>; +- }; +- +- vcc_3v3: regulator-vcc-3v3 { +- /* +- * Monolithic Power Systems MP2161 configured for a fixed +- * output voltage of 3.3V. This supplies not only VCC3V3 but +- * also VDD3V3 and VDDIO_AO3V3 according to the schematics. +- */ +- compatible = "regulator-fixed"; +- +- regulator-name = "VCC3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- vin-supply = <&p5v0>; +- }; +- +- vcck: regulator-vcck { +- /* Monolithic Power Systems MP2161 */ +- compatible = "pwm-regulator"; +- +- regulator-name = "VCCK"; +- regulator-min-microvolt = <860000>; +- regulator-max-microvolt = <1140000>; +- +- pwm-supply = <&p5v0>; +- +- pwms = <&pwm_cd 0 12218 0>; +- pwm-dutycycle-range = <91 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vddc_ddr: regulator-vddc-ddr { +- /* +- * Monolithic Power Systems MP2161 configured for a fixed +- * output voltage of 1.5V. This supplies not only DDR_VDDC but +- * also DDR3_1V5 according to the schematics. +- */ +- compatible = "regulator-fixed"; +- +- regulator-name = "DDR_VDDC"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- +- vin-supply = <&p5v0>; +- }; +- +- vddee: regulator-vddee { +- /* Monolithic Power Systems MP2161 */ +- compatible = "pwm-regulator"; +- +- regulator-name = "VDDEE"; +- regulator-min-microvolt = <860000>; +- regulator-max-microvolt = <1140000>; +- +- pwm-supply = <&p5v0>; +- +- pwms = <&pwm_cd 1 12218 0>; +- pwm-dutycycle-range = <91 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd_rtc: regulator-vdd-rtc { +- /* +- * Torex Semiconductor XC6215 configured for a fixed output of +- * 0.9V. +- */ +- compatible = "regulator-fixed"; +- +- regulator-name = "VDD_RTC"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- +- vin-supply = <&vcc_3v3>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vcck>; +-}; +- +-&efuse { +- ethernet_mac_address: mac@1b4 { +- reg = <0x1b4 0x6>; +- }; +-}; +- +-ðmac { +- status = "okay"; +- +- pinctrl-0 = <ð_rgmii_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <ð_phy>; +- phy-mode = "rgmii-id"; +- +- nvmem-cells = <ðernet_mac_address>; +- nvmem-cell-names = "mac-address"; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Realtek RTL8211F (0x001cc916) */ +- eth_phy: ethernet-phy@0 { +- reg = <0>; +- +- reset-assert-us = <10000>; +- reset-deassert-us = <80000>; +- reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; +- +- interrupt-parent = <&gpio_intc>; +- /* GPIOH_3 */ +- interrupts = <17 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +-}; +- +-&gpio { +- gpio-line-names = /* Bank GPIOX */ +- "J2 Header Pin 35", "J2 Header Pin 36", +- "J2 Header Pin 32", "J2 Header Pin 31", +- "J2 Header Pin 29", "J2 Header Pin 18", +- "J2 Header Pin 22", "J2 Header Pin 16", +- "J2 Header Pin 23", "J2 Header Pin 21", +- "J2 Header Pin 19", "J2 Header Pin 33", +- "J2 Header Pin 8", "J2 Header Pin 10", +- "J2 Header Pin 15", "J2 Header Pin 13", +- "J2 Header Pin 24", "J2 Header Pin 26", +- /* Bank GPIOY */ +- "Revision (upper)", "Revision (lower)", +- "J2 Header Pin 7", "", "J2 Header Pin 12", +- "J2 Header Pin 11", "", "", "", +- "TFLASH_VDD_EN", "", "", +- /* Bank GPIODV */ +- "VCCK_PWM (PWM_C)", "I2CA_SDA", "I2CA_SCL", +- "I2CB_SDA", "I2CB_SCL", "VDDEE_PWM (PWM_D)", +- "", +- /* Bank GPIOH */ +- "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL", +- "ETH_PHY_INTR", "ETH_PHY_NRST", "ETH_TXD1", +- "ETH_TXD0", "ETH_TXD3", "ETH_TXD2", +- "ETH_RGMII_TX_CLK", +- /* Bank CARD */ +- "SD_DATA1 (SDB_D1)", "SD_DATA0 (SDB_D0)", +- "SD_CLK", "SD_CMD", "SD_DATA3 (SDB_D3)", +- "SD_DATA2 (SDB_D2)", "SD_CDN (SD_DET_N)", +- /* Bank BOOT */ +- "SDC_D0 (EMMC)", "SDC_D1 (EMMC)", +- "SDC_D2 (EMMC)", "SDC_D3 (EMMC)", +- "SDC_D4 (EMMC)", "SDC_D5 (EMMC)", +- "SDC_D6 (EMMC)", "SDC_D7 (EMMC)", +- "SDC_CLK (EMMC)", "SDC_RSTn (EMMC)", +- "SDC_CMD (EMMC)", "BOOT_SEL", "", "", "", +- "", "", "", "", +- /* Bank DIF */ +- "ETH_RXD1", "ETH_RXD0", "ETH_RX_DV", +- "RGMII_RX_CLK", "ETH_RXD3", "ETH_RXD2", +- "ETH_TXEN", "ETH_PHY_REF_CLK_25MOUT", +- "ETH_MDC", "ETH_MDIO"; +-}; +- +-&gpio_ao { +- gpio-line-names = "UART TX", "UART RX", "", +- "TF_3V3N_1V8_EN", "USB_HUB_RST_N", +- "USB_OTG_PWREN", "J7 Header Pin 2", +- "IR_IN", "J7 Header Pin 4", +- "J7 Header Pin 6", "J7 Header Pin 5", +- "J7 Header Pin 7", "HDMI_CEC", +- "SYS_LED", "", ""; +- +- /* +- * WARNING: The USB Hub on the Odroid-C1/C1+ needs a reset signal +- * to be turned high in order to be detected by the USB Controller. +- * This signal should be handled by a USB specific power sequence +- * in order to reset the Hub when USB bus is powered down. +- */ +- usb-hub { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "usb-hub-reset"; +- }; +-}; +- +-&ir_receiver { +- status = "okay"; +- pinctrl-0 = <&ir_recv_pins>; +- pinctrl-names = "default"; +-}; +- +-&mali { +- mali-supply = <&vddee>; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vcc_1v8>; +-}; +- +-&sdhc { +- status = "okay"; +- +- pinctrl-0 = <&sdxc_c_pins>; +- pinctrl-names = "default"; +- +- bus-width = <8>; +- max-frequency = <100000000>; +- +- disable-wp; +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +- no-sdio; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&vcc_1v8>; +-}; +- +-&sdio { +- status = "okay"; +- +- pinctrl-0 = <&sd_b_pins>; +- pinctrl-names = "default"; +- +- /* SD card */ +- sd_card_slot: slot@1 { +- compatible = "mmc-slot"; +- reg = <1>; +- status = "okay"; +- +- bus-width = <4>; +- no-sdio; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&tflash_vdd>; +- vqmmc-supply = <&tf_io>; +- }; +-}; +- +-&pwm_cd { +- status = "okay"; +- pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>, <&xtal>; +- clock-names = "clkin0", "clkin1"; +-}; +- +-&rtc { +- /* needs to be enabled manually when a battery is connected */ +- clocks = <&rtc32k_xtal>; +- vdd-supply = <&vdd_rtc>; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb1_phy { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/meson8b.dtsi b/scripts/dtc/include-prefixes/arm/meson8b.dtsi +deleted file mode 100644 +index 94f1c03decce..000000000000 +--- a/scripts/dtc/include-prefixes/arm/meson8b.dtsi ++++ /dev/null +@@ -1,778 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-/* +- * Copyright 2015 Endless Mobile, Inc. +- * Author: Carlo Caione +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include "meson.dtsi" +- +-/ { +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a5"; +- next-level-cache = <&L2>; +- reg = <0x200>; +- enable-method = "amlogic,meson8b-smp"; +- resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPUCLK>; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- +- cpu1: cpu@201 { +- device_type = "cpu"; +- compatible = "arm,cortex-a5"; +- next-level-cache = <&L2>; +- reg = <0x201>; +- enable-method = "amlogic,meson8b-smp"; +- resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPUCLK>; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- +- cpu2: cpu@202 { +- device_type = "cpu"; +- compatible = "arm,cortex-a5"; +- next-level-cache = <&L2>; +- reg = <0x202>; +- enable-method = "amlogic,meson8b-smp"; +- resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPUCLK>; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- +- cpu3: cpu@203 { +- device_type = "cpu"; +- compatible = "arm,cortex-a5"; +- next-level-cache = <&L2>; +- reg = <0x203>; +- enable-method = "amlogic,meson8b-smp"; +- resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPUCLK>; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- }; +- +- cpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-96000000 { +- opp-hz = /bits/ 64 <96000000>; +- opp-microvolt = <860000>; +- }; +- opp-192000000 { +- opp-hz = /bits/ 64 <192000000>; +- opp-microvolt = <860000>; +- }; +- opp-312000000 { +- opp-hz = /bits/ 64 <312000000>; +- opp-microvolt = <860000>; +- }; +- opp-408000000 { +- opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <860000>; +- }; +- opp-504000000 { +- opp-hz = /bits/ 64 <504000000>; +- opp-microvolt = <860000>; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <860000>; +- }; +- opp-720000000 { +- opp-hz = /bits/ 64 <720000000>; +- opp-microvolt = <860000>; +- }; +- opp-816000000 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <900000>; +- }; +- opp-1008000000 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <1140000>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <1140000>; +- }; +- opp-1320000000 { +- opp-hz = /bits/ 64 <1320000000>; +- opp-microvolt = <1140000>; +- }; +- opp-1488000000 { +- opp-hz = /bits/ 64 <1488000000>; +- opp-microvolt = <1140000>; +- }; +- opp-1536000000 { +- opp-hz = /bits/ 64 <1536000000>; +- opp-microvolt = <1140000>; +- }; +- }; +- +- gpu_opp_table: gpu-opp-table { +- compatible = "operating-points-v2"; +- +- opp-255000000 { +- opp-hz = /bits/ 64 <255000000>; +- opp-microvolt = <1100000>; +- }; +- opp-364285714 { +- opp-hz = /bits/ 64 <364285714>; +- opp-microvolt = <1100000>; +- }; +- opp-425000000 { +- opp-hz = /bits/ 64 <425000000>; +- opp-microvolt = <1100000>; +- }; +- opp-510000000 { +- opp-hz = /bits/ 64 <510000000>; +- opp-microvolt = <1100000>; +- }; +- opp-637500000 { +- opp-hz = /bits/ 64 <637500000>; +- opp-microvolt = <1100000>; +- turbo-mode; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a5-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* 2 MiB reserved for Hardware ROM Firmware? */ +- hwrom@0 { +- reg = <0x0 0x200000>; +- no-map; +- }; +- }; +- +- thermal-zones { +- soc { +- polling-delay-passive = <250>; /* milliseconds */ +- polling-delay = <1000>; /* milliseconds */ +- thermal-sensors = <&thermal_sensor>; +- +- cooling-maps { +- map0 { +- trip = <&soc_passive>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- +- map1 { +- trip = <&soc_hot>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- +- trips { +- soc_passive: soc-passive { +- temperature = <80000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- +- soc_hot: soc-hot { +- temperature = <90000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "hot"; +- }; +- +- soc_critical: soc-critical { +- temperature = <110000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- }; +- }; +- +- mmcbus: bus@c8000000 { +- compatible = "simple-bus"; +- reg = <0xc8000000 0x8000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc8000000 0x8000>; +- +- ddr_clkc: clock-controller@400 { +- compatible = "amlogic,meson8b-ddr-clkc"; +- reg = <0x400 0x20>; +- clocks = <&xtal>; +- clock-names = "xtal"; +- #clock-cells = <1>; +- }; +- +- dmcbus: bus@6000 { +- compatible = "simple-bus"; +- reg = <0x6000 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6000 0x400>; +- +- canvas: video-lut@48 { +- compatible = "amlogic,meson8b-canvas", +- "amlogic,canvas"; +- reg = <0x48 0x14>; +- }; +- }; +- }; +- +- apb: bus@d0000000 { +- compatible = "simple-bus"; +- reg = <0xd0000000 0x200000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xd0000000 0x200000>; +- +- mali: gpu@c0000 { +- compatible = "amlogic,meson8b-mali", "arm,mali-450"; +- reg = <0xc0000 0x40000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "gp", "gpmmu", "pp", "pmu", +- "pp0", "ppmmu0", "pp1", "ppmmu1"; +- resets = <&reset RESET_MALI>; +- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; +- clock-names = "bus", "core"; +- operating-points-v2 = <&gpu_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- }; +-}; /* end of / */ +- +-&aiu { +- compatible = "amlogic,aiu-meson8b", "amlogic,aiu"; +- clocks = <&clkc CLKID_AIU_GLUE>, +- <&clkc CLKID_I2S_OUT>, +- <&clkc CLKID_AOCLK_GATE>, +- <&clkc CLKID_CTS_AMCLK>, +- <&clkc CLKID_MIXER_IFACE>, +- <&clkc CLKID_IEC958>, +- <&clkc CLKID_IEC958_GATE>, +- <&clkc CLKID_CTS_MCLK_I958>, +- <&clkc CLKID_CTS_I958>; +- clock-names = "pclk", +- "i2s_pclk", +- "i2s_aoclk", +- "i2s_mclk", +- "i2s_mixer", +- "spdif_pclk", +- "spdif_aoclk", +- "spdif_mclk", +- "spdif_mclk_sel"; +- resets = <&reset RESET_AIU>; +-}; +- +-&aobus { +- pmu: pmu@e0 { +- compatible = "amlogic,meson8b-pmu", "syscon"; +- reg = <0xe0 0x18>; +- }; +- +- pinctrl_aobus: pinctrl@84 { +- compatible = "amlogic,meson8b-aobus-pinctrl"; +- reg = <0x84 0xc>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gpio_ao: ao-bank@14 { +- reg = <0x14 0x4>, +- <0x2c 0x4>, +- <0x24 0x8>; +- reg-names = "mux", "pull", "gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl_aobus 0 0 16>; +- }; +- +- i2s_am_clk_pins: i2s-am-clk-out { +- mux { +- groups = "i2s_am_clk_out"; +- function = "i2s"; +- bias-disable; +- }; +- }; +- +- i2s_out_ao_clk_pins: i2s-ao-clk-out { +- mux { +- groups = "i2s_ao_clk_out"; +- function = "i2s"; +- bias-disable; +- }; +- }; +- +- i2s_out_lr_clk_pins: i2s-lr-clk-out { +- mux { +- groups = "i2s_lr_clk_out"; +- function = "i2s"; +- bias-disable; +- }; +- }; +- +- i2s_out_ch01_ao_pins: i2s-out-ch01 { +- mux { +- groups = "i2s_out_01"; +- function = "i2s"; +- bias-disable; +- }; +- }; +- +- spdif_out_1_pins: spdif-out-1 { +- mux { +- groups = "spdif_out_1"; +- function = "spdif_1"; +- bias-disable; +- }; +- }; +- +- uart_ao_a_pins: uart_ao_a { +- mux { +- groups = "uart_tx_ao_a", "uart_rx_ao_a"; +- function = "uart_ao"; +- bias-disable; +- }; +- }; +- +- ir_recv_pins: remote { +- mux { +- groups = "remote_input"; +- function = "remote"; +- bias-disable; +- }; +- }; +- }; +-}; +- +-&ao_arc_rproc { +- compatible= "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc"; +- amlogic,secbus2 = <&secbus2>; +- sram = <&ao_arc_sram>; +- resets = <&reset RESET_MEDIA_CPU>; +- clocks = <&clkc CLKID_AO_MEDIA_CPU>; +-}; +- +-&cbus { +- reset: reset-controller@4404 { +- compatible = "amlogic,meson8b-reset"; +- reg = <0x4404 0x9c>; +- #reset-cells = <1>; +- }; +- +- analog_top: analog-top@81a8 { +- compatible = "amlogic,meson8b-analog-top", "syscon"; +- reg = <0x81a8 0x14>; +- }; +- +- pwm_ef: pwm@86c0 { +- compatible = "amlogic,meson8b-pwm"; +- reg = <0x86c0 0x10>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- clock-measure@8758 { +- compatible = "amlogic,meson8b-clk-measure"; +- reg = <0x8758 0x1c>; +- }; +- +- pinctrl_cbus: pinctrl@9880 { +- compatible = "amlogic,meson8b-cbus-pinctrl"; +- reg = <0x9880 0x10>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gpio: banks@80b0 { +- reg = <0x80b0 0x28>, +- <0x80e8 0x18>, +- <0x8120 0x18>, +- <0x8030 0x38>; +- reg-names = "mux", "pull", "pull-enable", "gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl_cbus 0 0 83>; +- }; +- +- eth_rgmii_pins: eth-rgmii { +- mux { +- groups = "eth_tx_clk", +- "eth_tx_en", +- "eth_txd1_0", +- "eth_txd0_0", +- "eth_rx_clk", +- "eth_rx_dv", +- "eth_rxd1", +- "eth_rxd0", +- "eth_mdio_en", +- "eth_mdc", +- "eth_ref_clk", +- "eth_txd2", +- "eth_txd3", +- "eth_rxd3", +- "eth_rxd2"; +- function = "ethernet"; +- bias-disable; +- }; +- }; +- +- eth_rmii_pins: eth-rmii { +- mux { +- groups = "eth_tx_en", +- "eth_txd1_0", +- "eth_txd0_0", +- "eth_rx_clk", +- "eth_rx_dv", +- "eth_rxd1", +- "eth_rxd0", +- "eth_mdio_en", +- "eth_mdc"; +- function = "ethernet"; +- bias-disable; +- }; +- }; +- +- i2c_a_pins: i2c-a { +- mux { +- groups = "i2c_sda_a", "i2c_sck_a"; +- function = "i2c_a"; +- bias-disable; +- }; +- }; +- +- sd_b_pins: sd-b { +- mux { +- groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", +- "sd_d3_b", "sd_clk_b", "sd_cmd_b"; +- function = "sd_b"; +- bias-disable; +- }; +- }; +- +- sdxc_c_pins: sdxc-c { +- mux { +- groups = "sdxc_d0_c", "sdxc_d13_c", +- "sdxc_d47_c", "sdxc_clk_c", +- "sdxc_cmd_c"; +- function = "sdxc_c"; +- bias-pull-up; +- }; +- }; +- +- pwm_c1_pins: pwm-c1 { +- mux { +- groups = "pwm_c1"; +- function = "pwm_c"; +- bias-disable; +- }; +- }; +- +- pwm_d_pins: pwm-d { +- mux { +- groups = "pwm_d"; +- function = "pwm_d"; +- bias-disable; +- }; +- }; +- +- uart_b0_pins: uart-b0 { +- mux { +- groups = "uart_tx_b0", +- "uart_rx_b0"; +- function = "uart_b"; +- bias-disable; +- }; +- }; +- +- uart_b0_cts_rts_pins: uart-b0-cts-rts { +- mux { +- groups = "uart_cts_b0", +- "uart_rts_b0"; +- function = "uart_b"; +- bias-disable; +- }; +- }; +- }; +-}; +- +-&ahb_sram { +- ao_arc_sram: ao-arc-sram@0 { +- compatible = "amlogic,meson8b-ao-arc-sram"; +- reg = <0x0 0x8000>; +- pool; +- }; +- +- smp-sram@1ff80 { +- compatible = "amlogic,meson8b-smp-sram"; +- reg = <0x1ff80 0x8>; +- }; +-}; +- +- +-&efuse { +- compatible = "amlogic,meson8b-efuse"; +- clocks = <&clkc CLKID_EFUSE>; +- clock-names = "core"; +- +- temperature_calib: calib@1f4 { +- /* only the upper two bytes are relevant */ +- reg = <0x1f4 0x4>; +- }; +-}; +- +-ðmac { +- compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac"; +- +- reg = <0xc9410000 0x10000 +- 0xc1108140 0x4>; +- +- clocks = <&clkc CLKID_ETH>, +- <&clkc CLKID_MPLL2>, +- <&clkc CLKID_MPLL2>, +- <&clkc CLKID_FCLK_DIV2>; +- clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; +- rx-fifo-depth = <4096>; +- tx-fifo-depth = <2048>; +- +- resets = <&reset RESET_ETHERNET>; +- reset-names = "stmmaceth"; +- +- power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>; +-}; +- +-&gpio_intc { +- compatible = "amlogic,meson-gpio-intc", +- "amlogic,meson8b-gpio-intc"; +- status = "okay"; +-}; +- +-&hhi { +- clkc: clock-controller { +- compatible = "amlogic,meson8b-clkc"; +- clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; +- clock-names = "xtal", "ddr_pll"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pwrc: power-controller { +- compatible = "amlogic,meson8b-pwrc"; +- #power-domain-cells = <1>; +- amlogic,ao-sysctrl = <&pmu>; +- resets = <&reset RESET_DBLK>, +- <&reset RESET_PIC_DC>, +- <&reset RESET_HDMI_APB>, +- <&reset RESET_HDMI_SYSTEM_RESET>, +- <&reset RESET_VENCI>, +- <&reset RESET_VENCP>, +- <&reset RESET_VDAC_4>, +- <&reset RESET_VENCL>, +- <&reset RESET_VIU>, +- <&reset RESET_VENC>, +- <&reset RESET_RDMA>; +- reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", +- "venci", "vencp", "vdac", "vencl", "viu", +- "venc", "rdma"; +- clocks = <&clkc CLKID_VPU>; +- clock-names = "vpu"; +- assigned-clocks = <&clkc CLKID_VPU>; +- assigned-clock-rates = <182142857>; +- }; +-}; +- +-&hwrng { +- compatible = "amlogic,meson8b-rng", "amlogic,meson-rng"; +- clocks = <&clkc CLKID_RNG0>; +- clock-names = "core"; +-}; +- +-&i2c_AO { +- clocks = <&clkc CLKID_CLK81>; +-}; +- +-&i2c_A { +- clocks = <&clkc CLKID_I2C>; +-}; +- +-&i2c_B { +- clocks = <&clkc CLKID_I2C>; +-}; +- +-&L2 { +- arm,data-latency = <3 3 3>; +- arm,tag-latency = <2 2 2>; +- arm,filter-ranges = <0x100000 0xc0000000>; +- prefetch-data = <1>; +- prefetch-instr = <1>; +- arm,shared-override; +-}; +- +-&periph { +- scu@0 { +- compatible = "arm,cortex-a5-scu"; +- reg = <0x0 0x100>; +- }; +- +- timer@200 { +- compatible = "arm,cortex-a5-global-timer"; +- reg = <0x200 0x20>; +- interrupts = ; +- clocks = <&clkc CLKID_PERIPH>; +- +- /* +- * the arm_global_timer driver currently does not handle clock +- * rate changes. Keep it disabled for now. +- */ +- status = "disabled"; +- }; +- +- timer@600 { +- compatible = "arm,cortex-a5-twd-timer"; +- reg = <0x600 0x20>; +- interrupts = ; +- clocks = <&clkc CLKID_PERIPH>; +- }; +-}; +- +-&pwm_ab { +- compatible = "amlogic,meson8b-pwm"; +-}; +- +-&pwm_cd { +- compatible = "amlogic,meson8b-pwm"; +-}; +- +-&rtc { +- compatible = "amlogic,meson8b-rtc"; +- resets = <&reset RESET_RTC>; +-}; +- +-&saradc { +- compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc"; +- clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; +- clock-names = "clkin", "core"; +- amlogic,hhi-sysctrl = <&hhi>; +- nvmem-cells = <&temperature_calib>; +- nvmem-cell-names = "temperature_calib"; +-}; +- +-&sdhc { +- compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; +- clocks = <&xtal>, +- <&clkc CLKID_FCLK_DIV4>, +- <&clkc CLKID_FCLK_DIV3>, +- <&clkc CLKID_FCLK_DIV5>, +- <&clkc CLKID_SDHC>; +- clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; +-}; +- +-&secbus { +- secbus2: system-controller@4000 { +- compatible = "amlogic,meson8b-secbus2", "syscon"; +- reg = <0x4000 0x2000>; +- }; +-}; +- +-&sdio { +- compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio"; +- clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; +- clock-names = "core", "clkin"; +-}; +- +-&timer_abcde { +- clocks = <&xtal>, <&clkc CLKID_CLK81>; +- clock-names = "xtal", "pclk"; +-}; +- +-&uart_AO { +- compatible = "amlogic,meson8b-uart", "amlogic,meson-ao-uart"; +- clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&uart_A { +- compatible = "amlogic,meson8b-uart"; +- clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&uart_B { +- compatible = "amlogic,meson8b-uart"; +- clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&uart_C { +- compatible = "amlogic,meson8b-uart"; +- clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&usb0 { +- compatible = "amlogic,meson8b-usb", "snps,dwc2"; +- clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; +- clock-names = "otg"; +-}; +- +-&usb1 { +- compatible = "amlogic,meson8b-usb", "snps,dwc2"; +- clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; +- clock-names = "otg"; +-}; +- +-&usb0_phy { +- compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; +- clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; +- clock-names = "usb_general", "usb"; +- resets = <&reset RESET_USB_OTG>; +-}; +- +-&usb1_phy { +- compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; +- clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; +- clock-names = "usb_general", "usb"; +- resets = <&reset RESET_USB_OTG>; +-}; +- +-&wdt { +- compatible = "amlogic,meson8b-wdt"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/meson8m2-mxiii-plus.dts b/scripts/dtc/include-prefixes/arm/meson8m2-mxiii-plus.dts +deleted file mode 100644 +index fa6d55f1cfb9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/meson8m2-mxiii-plus.dts ++++ /dev/null +@@ -1,247 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Oleg Ivanov +- * Copyright (c) 2018 Martin Blumenstingl +- */ +- +-/dts-v1/; +- +-#include "meson8m2.dtsi" +- +-#include +-#include +- +-/ { +- model = "Tronsmart MXIII Plus"; +- compatible = "tronsmart,mxiii-plus", "amlogic,meson8m2"; +- +- aliases { +- ethernet0 = ðmac; +- i2c0 = &i2c_AO; +- serial0 = &uart_AO; +- serial1 = &uart_A; +- mmc0 = &sd_card_slot; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x40000000 0x80000000>; +- }; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 0>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1710000>; +- +- button-function { +- label = "Function"; +- linux,code = ; +- press-threshold-microvolt = <10000>; +- }; +- }; +- +- vcc_3v3: regulator-vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vcck>; +-}; +- +-ðmac { +- status = "okay"; +- +- pinctrl-0 = <ð_rgmii_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <ð_phy0>; +- phy-mode = "rgmii-id"; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eth_phy0: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- +- reset-assert-us = <10000>; +- reset-deassert-us = <80000>; +- reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&ir_receiver { +- status = "okay"; +- pinctrl-0 = <&ir_recv_pins>; +- pinctrl-names = "default"; +-}; +- +-&i2c_AO { +- status = "okay"; +- pinctrl-0 = <&i2c_ao_pins>; +- pinctrl-names = "default"; +- +- pmic@32 { +- compatible = "ricoh,rn5t618"; +- reg = <0x32>; +- system-power-controller; +- +- regulators { +- vcck: DCDC1 { +- regulator-name = "VCCK"; +- regulator-min-microvolt = <825000>; +- regulator-max-microvolt = <1150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vddee: DCDC2 { +- /* the output is also used as VDDAO */ +- regulator-name = "VDD_EE"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- DCDC3 { +- regulator-name = "VDD_DDR"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- LDO1 { +- regulator-name = "VDDIO_AO28"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vddio_ao1v8: LDO2 { +- regulator-name = "VDDIO_AO18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- LDO3 { +- regulator-name = "VCC1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- LDO4 { +- regulator-name = "VCC2V8"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- LDO5 { +- regulator-name = "AVDD1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- LDORTC1 { +- regulator-name = "VDD_LDO"; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- LDORTC2 { +- regulator-name = "RTC_0V9"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&mali { +- mali-supply = <&vddee>; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vddio_ao1v8>; +-}; +- +-&sdio { +- status = "okay"; +- +- pinctrl-0 = <&sd_b_pins>; +- pinctrl-names = "default"; +- +- /* SD card */ +- sd_card_slot: slot@1 { +- compatible = "mmc-slot"; +- reg = <1>; +- status = "okay"; +- +- bus-width = <4>; +- no-sdio; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&vcc_3v3>; +- }; +-}; +- +-/* connected to the Bluetooth module */ +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a1_pins>, <&uart_a1_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&usb0_phy { +- status = "okay"; +-}; +- +-&usb1_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/meson8m2.dtsi b/scripts/dtc/include-prefixes/arm/meson8m2.dtsi +deleted file mode 100644 +index 6725dd9fd825..000000000000 +--- a/scripts/dtc/include-prefixes/arm/meson8m2.dtsi ++++ /dev/null +@@ -1,101 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Martin Blumenstingl . +- */ +- +-#include "meson8.dtsi" +- +-/ { +- model = "Amlogic Meson8m2 SoC"; +- compatible = "amlogic,meson8m2"; +-}; /* end of / */ +- +-&clkc { +- compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc"; +-}; +- +-&dmcbus { +- /* the offset of the canvas registers has changed compared to Meson8 */ +- /delete-node/ video-lut@20; +- +- canvas: video-lut@48 { +- compatible = "amlogic,meson8m2-canvas", "amlogic,canvas"; +- reg = <0x48 0x14>; +- }; +-}; +- +-ðmac { +- compatible = "amlogic,meson8m2-dwmac", "snps,dwmac"; +- reg = <0xc9410000 0x10000 +- 0xc1108140 0x8>; +- clocks = <&clkc CLKID_ETH>, +- <&clkc CLKID_MPLL2>, +- <&clkc CLKID_MPLL2>, +- <&clkc CLKID_FCLK_DIV2>; +- clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; +- resets = <&reset RESET_ETHERNET>; +- reset-names = "stmmaceth"; +-}; +- +-&pinctrl_aobus { +- compatible = "amlogic,meson8m2-aobus-pinctrl", +- "amlogic,meson8-aobus-pinctrl"; +-}; +- +-&pinctrl_cbus { +- compatible = "amlogic,meson8m2-cbus-pinctrl", +- "amlogic,meson8-cbus-pinctrl"; +- +- eth_rgmii_pins: ethernet { +- mux { +- groups = "eth_tx_clk_50m", "eth_tx_en", +- "eth_txd3", "eth_txd2", +- "eth_txd1", "eth_txd0", +- "eth_rx_clk_in", "eth_rx_dv", +- "eth_rxd3", "eth_rxd2", +- "eth_rxd1", "eth_rxd0", +- "eth_mdio", "eth_mdc"; +- function = "ethernet"; +- bias-disable; +- }; +- }; +-}; +- +-&pwrc { +- compatible = "amlogic,meson8m2-pwrc"; +- resets = <&reset RESET_DBLK>, +- <&reset RESET_PIC_DC>, +- <&reset RESET_HDMI_APB>, +- <&reset RESET_HDMI_SYSTEM_RESET>, +- <&reset RESET_VENCI>, +- <&reset RESET_VENCP>, +- <&reset RESET_VDAC_4>, +- <&reset RESET_VENCL>, +- <&reset RESET_VIU>, +- <&reset RESET_VENC>, +- <&reset RESET_RDMA>; +- reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", "venci", +- "vencp", "vdac", "vencl", "viu", "venc", "rdma"; +- assigned-clocks = <&clkc CLKID_VPU>; +- assigned-clock-rates = <364000000>; +-}; +- +-&saradc { +- compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc"; +-}; +- +-&sdhc { +- compatible = "amlogic,meson8m2-sdhc", "amlogic,meson-mx-sdhc"; +-}; +- +-&usb0_phy { +- compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; +-}; +- +-&usb1_phy { +- compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; +-}; +- +-&wdt { +- compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/milbeaut-m10v-evb.dts b/scripts/dtc/include-prefixes/arm/milbeaut-m10v-evb.dts +deleted file mode 100644 +index 614f60c6b0a2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/milbeaut-m10v-evb.dts ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* Socionext Milbeaut M10V Evaluation Board */ +-/dts-v1/; +-#include "milbeaut-m10v.dtsi" +- +-/ { +- model = "Socionext M10V EVB"; +- compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a"; +- +- aliases { +- serial0 = &uart1; +- }; +- +- chosen { +- bootargs = "rootwait earlycon"; +- stdout-path = "serial0:115200n8"; +- }; +- +- clocks { +- uclk40xi: uclk40xi { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <40000000>; +- }; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x80000000>; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm/milbeaut-m10v.dtsi b/scripts/dtc/include-prefixes/arm/milbeaut-m10v.dtsi +deleted file mode 100644 +index aa7c6caeb750..000000000000 +--- a/scripts/dtc/include-prefixes/arm/milbeaut-m10v.dtsi ++++ /dev/null +@@ -1,95 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "socionext,sc2000a"; +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "socionext,milbeaut-m10v-smp"; +- cpu@f00 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0xf00>; +- }; +- cpu@f01 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0xf01>; +- }; +- cpu@f02 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0xf02>; +- }; +- cpu@f03 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0xf03>; +- }; +- }; +- +- timer { /* The Generic Timer */ +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- clock-frequency = <40000000>; +- always-on; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- interrupt-parent = <&gic>; +- +- gic: interrupt-controller@1d000000 { +- compatible = "arm,cortex-a7-gic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x1d001000 0x1000>, +- <0x1d002000 0x1000>; /* CPU I/f base and size */ +- }; +- +- timer@1e000050 { /* 32-bit Reload Timers */ +- compatible = "socionext,milbeaut-timer"; +- reg = <0x1e000050 0x20>; +- interrupts = <0 91 4>; +- }; +- +- uart1: serial@1e700010 { /* PE4, PE5 */ +- /* Enable this as ttyUSI0 */ +- compatible = "socionext,milbeaut-usio-uart"; +- reg = <0x1e700010 0x10>; +- interrupts = <0 141 0x4>, <0 149 0x4>; +- interrupt-names = "rx", "tx"; +- }; +- +- }; +- +- sram@0 { +- compatible = "mmio-sram"; +- reg = <0x0 0x10000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x0 0x10000>; +- smp-sram@f100 { +- compatible = "socionext,milbeaut-smp-sram"; +- reg = <0xf100 0x20>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mmp2-brownstone.dts b/scripts/dtc/include-prefixes/arm/mmp2-brownstone.dts +deleted file mode 100644 +index 04f1ae1382e7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mmp2-brownstone.dts ++++ /dev/null +@@ -1,192 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Marvell Technology Group Ltd. +- * Author: Haojian Zhuang +- */ +- +-/dts-v1/; +-#include "mmp2.dtsi" +- +-/ { +- model = "Marvell MMP2 Brownstone Development Board"; +- compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2"; +- +- chosen { +- bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&twsi1 { +- status = "okay"; +- pmic: max8925@3c { +- compatible = "maxium,max8925"; +- reg = <0x3c>; +- interrupts = <1>; +- interrupt-parent = <&intcmux4>; +- interrupt-controller; +- #interrupt-cells = <1>; +- maxim,tsc-irq = <0>; +- +- regulators { +- SDV1 { +- regulator-min-microvolt = <637500>; +- regulator-max-microvolt = <1425000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- SDV2 { +- regulator-min-microvolt = <650000>; +- regulator-max-microvolt = <2225000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- SDV3 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO1 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO2 { +- regulator-min-microvolt = <650000>; +- regulator-max-microvolt = <2250000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO3 { +- regulator-min-microvolt = <650000>; +- regulator-max-microvolt = <2250000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO4 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO5 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO6 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO7 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO8 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO9 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO10 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3900000>; +- }; +- LDO11 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO12 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO13 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO14 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO15 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO16 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO17 { +- regulator-min-microvolt = <650000>; +- regulator-max-microvolt = <2250000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO18 { +- regulator-min-microvolt = <650000>; +- regulator-max-microvolt = <2250000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO19 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO20 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <3900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- backlight { +- maxim,max8925-dual-string = <0>; +- }; +- charger { +- batt-detect = <0>; +- topoff-threshold = <1>; +- fast-charge = <7>; +- no-temp-support = <0>; +- no-insert-detect = <0>; +- }; +- }; +-}; +- +-&rtc { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mmp2-olpc-xo-1-75.dts b/scripts/dtc/include-prefixes/arm/mmp2-olpc-xo-1-75.dts +deleted file mode 100644 +index 55ea87870af3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mmp2-olpc-xo-1-75.dts ++++ /dev/null +@@ -1,277 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * OLPC XO 1.75 Laptop. +- * +- * Copyright (C) 2018,2019,2020 Lubomir Rintel +- */ +- +-/dts-v1/; +-#include "mmp2.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "OLPC XO-1.75"; +- compatible = "olpc,xo-1.75", "mrvl,mmp2"; +- +- chosen { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- framebuffer@1fc00000 { +- compatible = "simple-framebuffer"; +- reg = <0x1fc00000 (1200 * 900 * 2)>; +- width = <1200>; +- height = <900>; +- stride = <(1200 * 2)>; +- format = "r5g6b5"; +- clocks = <&soc_clocks MMP2_CLK_DISP0_LCDC>, +- <&soc_clocks MMP2_CLK_DISP0>; +- }; +- }; +- +- memory@0 { +- available = <0xcf000 0x1ef31000 0x1000 0xbf000>; +- reg = <0x0 0x20000000>; +- device_type = "memory"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- lid { +- label = "Lid"; +- gpios = <&gpio 129 GPIO_ACTIVE_LOW>; +- linux,input-type = ; +- linux,code = ; +- wakeup-source; +- }; +- +- tablet_mode { +- label = "E-Book Mode"; +- gpios = <&gpio 128 GPIO_ACTIVE_LOW>; +- linux,input-type = ; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- i2c { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio 109 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio 108 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-gpio,timeout-ms = <1000>; +- status = "okay"; +- +- camera@21 { +- compatible = "ovti,ov7670"; +- reg = <0x21>; +- reset-gpios = <&gpio 102 GPIO_ACTIVE_LOW>; +- powerdown-gpios = <&gpio 150 GPIO_ACTIVE_LOW>; +- clocks = <&camera0>; +- clock-names = "xclk"; +- +- port { +- ov7670_0: endpoint { +- hsync-active = <1>; +- vsync-active = <1>; +- remote-endpoint = <&camera0_0>; +- }; +- }; +- }; +- }; +- +- battery { +- compatible = "olpc,xo1.5-battery", "olpc,xo1-battery"; +- }; +- +- wlan_reg: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "wlan"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio 34 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- wlan_pwrseq: pwrseq0 { +- compatible = "mmc-pwrseq-sd8787"; +- powerdown-gpios = <&gpio 57 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&gpio 58 GPIO_ACTIVE_HIGH>; +- }; +- +- sound-card { +- compatible = "audio-graph-card"; +- label = "OLPC XO"; +- dais = <&sspa0_dai>; +- routing = "Headphones", "HPOL", +- "Headphones", "HPOR", +- "MIC2", "Mic Jack"; +- widgets = "Headphone", "Headphones", "Microphone", "Mic Jack"; +- hp-det-gpio = <&gpio 97 GPIO_ACTIVE_HIGH>; +- mic-det-gpio = <&gpio 96 GPIO_ACTIVE_HIGH>; +- }; +- +- soc { +- axi@d4200000 { +- ap-sp@d4290000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "olpc,ap-sp"; +- interrupts = <40>; +- reg = <0xd4290000 0x1000>; +- data-gpios = <&gpio 72 GPIO_ACTIVE_HIGH>; +- clk-gpios = <&gpio 71 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- }; +- }; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&uart4 { +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&usb_phy0 { +- status = "okay"; +-}; +- +-&usb_otg0 { +- status = "okay"; +-}; +- +-&mmc1 { +- clock-frequency = <50000000>; +- no-1-8-v; +- mrvl,clk-delay-cycles = <31>; +- broken-cd; +- status = "okay"; +-}; +- +-&mmc2 { +- clock-frequency = <50000000>; +- no-1-8-v; +- bus-width = <4>; +- non-removable; +- broken-cd; +- wakeup-source; +- keep-power-in-suspend; +- mmc-pwrseq = <&wlan_pwrseq>; +- vmmc-supply = <&wlan_reg>; +- status = "okay"; +-}; +- +-&mmc3 { +- clock-frequency = <50000000>; +- no-1-8-v; +- bus-width = <8>; +- non-removable; +- broken-cd; +- mrvl,clk-delay-cycles = <31>; +- status = "okay"; +-}; +- +-&twsi1 { +- status = "okay"; +- +- audio-codec@1a { +- compatible = "realtek,alc5631"; +- reg = <0x1a>; +- status = "okay"; +- +- port { +- rt5631_0: endpoint { +- mclk-fs = <256>; +- clocks = <&audio_clk MMP2_CLK_AUDIO_SYSCLK>; +- remote-endpoint = <&sspa0_0>; +- }; +- }; +- }; +-}; +- +-&twsi2 { +- status = "okay"; +- +- rtc@68 { +- compatible = "dallas,ds1338"; +- reg = <0x68>; +- status = "okay"; +- }; +-}; +- +-&twsi6 { +- status = "okay"; +- +- accelerometer@1d { +- compatible = "st,lis331dlh", "st,lis3lv02d"; +- reg = <0x1d>; +- status = "okay"; +- }; +-}; +- +-&ssp3 { +- #address-cells = <0>; +- spi-slave; +- status = "okay"; +- ready-gpios = <&gpio 125 GPIO_ACTIVE_HIGH>; +- +- slave { +- compatible = "olpc,xo1.75-ec"; +- spi-cpha; +- cmd-gpios = <&gpio 155 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&camera0 { +- status = "okay"; +- +- port { +- camera0_0: endpoint { +- remote-endpoint = <&ov7670_0>; +- }; +- }; +-}; +- +-&asram { +- status = "okay"; +-}; +- +-&adma0 { +- status = "okay"; +-}; +- +-&audio_clk { +- status = "okay"; +-}; +- +-&sspa0 { +- status = "okay"; +- dmas = <&adma0 0>, <&adma0 1>; +- dma-names = "tx", "rx"; +- +- sspa0_dai: port { +- sspa0_0: endpoint { +- remote-endpoint = <&rt5631_0>; +- frame-master; +- bitclock-master; +- dai-format = "i2s"; +- }; +- }; +-}; +- +-&gpu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mmp2.dtsi b/scripts/dtc/include-prefixes/arm/mmp2.dtsi +deleted file mode 100644 +index 46984d4c5224..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mmp2.dtsi ++++ /dev/null +@@ -1,514 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Marvell Technology Group Ltd. +- * Author: Haojian Zhuang +- */ +- +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- i2c0 = &twsi1; +- i2c1 = &twsi2; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&intc>; +- ranges; +- +- L2: l2-cache { +- compatible = "marvell,tauros2-cache"; +- marvell,tauros2-cache-features = <0x3>; +- }; +- +- axi@d4200000 { /* AXI */ +- compatible = "mrvl,axi-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xd4200000 0x00200000>; +- ranges; +- +- gpu: gpu@d420d000 { +- compatible = "vivante,gc"; +- reg = <0xd420d000 0x4000>; +- interrupts = <8>; +- status = "disabled"; +- clocks = <&soc_clocks MMP2_CLK_GPU_3D>, +- <&soc_clocks MMP2_CLK_GPU_BUS>; +- clock-names = "core", "bus"; +- power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>; +- }; +- +- intc: interrupt-controller@d4282000 { +- compatible = "mrvl,mmp2-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0xd4282000 0x1000>; +- mrvl,intc-nr-irqs = <64>; +- }; +- +- intcmux4: interrupt-controller@d4282150 { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = <4>; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x150 0x4>, <0x168 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <2>; +- }; +- +- intcmux5: interrupt-controller@d4282154 { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = <5>; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x154 0x4>, <0x16c 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <2>; +- mrvl,clr-mfp-irq = <1>; +- }; +- +- intcmux9: interrupt-controller@d4282180 { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = <9>; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x180 0x4>, <0x17c 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <3>; +- }; +- +- intcmux17: interrupt-controller@d4282158 { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = <17>; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x158 0x4>, <0x170 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <5>; +- }; +- +- intcmux35: interrupt-controller@d428215c { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = <35>; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x15c 0x4>, <0x174 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <15>; +- }; +- +- intcmux51: interrupt-controller@d4282160 { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = <51>; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x160 0x4>, <0x178 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <2>; +- }; +- +- intcmux55: interrupt-controller@d4282188 { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = <55>; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x188 0x4>, <0x184 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <2>; +- }; +- +- usb_phy0: usb-phy@d4207000 { +- compatible = "marvell,mmp2-usb-phy"; +- reg = <0xd4207000 0x40>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- usb_otg0: usb-otg@d4208000 { +- compatible = "marvell,pxau2o-ehci"; +- reg = <0xd4208000 0x200>; +- interrupts = <44>; +- clocks = <&soc_clocks MMP2_CLK_USB>; +- clock-names = "USBCLK"; +- phys = <&usb_phy0>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- mmc1: mmc@d4280000 { +- compatible = "mrvl,pxav3-mmc"; +- reg = <0xd4280000 0x120>; +- clocks = <&soc_clocks MMP2_CLK_SDH0>; +- clock-names = "io"; +- interrupts = <39>; +- status = "disabled"; +- }; +- +- mmc2: mmc@d4280800 { +- compatible = "mrvl,pxav3-mmc"; +- reg = <0xd4280800 0x120>; +- clocks = <&soc_clocks MMP2_CLK_SDH1>; +- clock-names = "io"; +- interrupts = <52>; +- status = "disabled"; +- }; +- +- mmc3: mmc@d4281000 { +- compatible = "mrvl,pxav3-mmc"; +- reg = <0xd4281000 0x120>; +- clocks = <&soc_clocks MMP2_CLK_SDH2>; +- clock-names = "io"; +- interrupts = <53>; +- status = "disabled"; +- }; +- +- mmc4: mmc@d4281800 { +- compatible = "mrvl,pxav3-mmc"; +- reg = <0xd4281800 0x120>; +- clocks = <&soc_clocks MMP2_CLK_SDH3>; +- clock-names = "io"; +- interrupts = <54>; +- status = "disabled"; +- }; +- +- camera0: camera@d420a000 { +- compatible = "marvell,mmp2-ccic"; +- reg = <0xd420a000 0x800>; +- interrupts = <42>; +- clocks = <&soc_clocks MMP2_CLK_CCIC0>; +- clock-names = "axi"; +- #clock-cells = <0>; +- clock-output-names = "mclk"; +- status = "disabled"; +- }; +- +- camera1: camera@d420a800 { +- compatible = "marvell,mmp2-ccic"; +- reg = <0xd420a800 0x800>; +- interrupts = <30>; +- clocks = <&soc_clocks MMP2_CLK_CCIC1>; +- clock-names = "axi"; +- #clock-cells = <0>; +- clock-output-names = "mclk"; +- status = "disabled"; +- }; +- +- adma0: dma-controller@d42a0800 { +- compatible = "marvell,adma-1.0"; +- reg = <0xd42a0800 0x100>; +- interrupts = <48>; +- #dma-cells = <1>; +- asram = <&asram>; +- iram = <&asram>; +- status = "disabled"; +- }; +- +- adma1: dma-controller@d42a0900 { +- compatible = "marvell,adma-1.0"; +- reg = <0xd42a0900 0x100>; +- interrupts = <48>; +- #dma-cells = <1>; +- status = "disabled"; +- }; +- +- audio_clk: clocks@d42a0c30 { +- compatible = "marvell,mmp2-audio-clock"; +- reg = <0xd42a0c30 0x10>; +- clock-names = "audio", "vctcxo", "i2s0", "i2s1"; +- clocks = <&soc_clocks MMP2_CLK_AUDIO>, +- <&soc_clocks MMP2_CLK_VCTCXO>, +- <&soc_clocks MMP2_CLK_I2S0>, +- <&soc_clocks MMP2_CLK_I2S1>; +- power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>; +- #clock-cells = <1>; +- status = "disabled"; +- }; +- +- sspa0: audio-controller@d42a0c00 { +- compatible = "marvell,mmp-sspa"; +- reg = <0xd42a0c00 0x30>, +- <0xd42a0c80 0x30>; +- interrupts = <2>; +- clock-names = "audio", "bitclk"; +- clocks = <&soc_clocks MMP2_CLK_AUDIO>, +- <&audio_clk MMP2_CLK_AUDIO_SSPA0>; +- power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- sspa1: audio-controller@d42a0d00 { +- compatible = "marvell,mmp-sspa"; +- reg = <0xd42a0d00 0x30>, +- <0xd42a0d80 0x30>; +- interrupts = <3>; +- clock-names = "audio", "bitclk"; +- clocks = <&soc_clocks MMP2_CLK_AUDIO>, +- <&audio_clk MMP2_CLK_AUDIO_SSPA1>; +- power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- apb@d4000000 { /* APB */ +- compatible = "mrvl,apb-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xd4000000 0x00200000>; +- ranges; +- +- dma-controller@d4000000 { +- compatible = "marvell,pdma-1.0"; +- reg = <0xd4000000 0x10000>; +- interrupts = <48>; +- #dma-channels = <16>; +- status = "disabled"; +- }; +- +- timer0: timer@d4014000 { +- compatible = "mrvl,mmp-timer"; +- reg = <0xd4014000 0x100>; +- interrupts = <13>; +- clocks = <&soc_clocks MMP2_CLK_TIMER>; +- }; +- +- uart1: serial@d4030000 { +- compatible = "mrvl,mmp-uart", "intel,xscale-uart"; +- reg = <0xd4030000 0x1000>; +- interrupts = <27>; +- clocks = <&soc_clocks MMP2_CLK_UART0>; +- resets = <&soc_clocks MMP2_CLK_UART0>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart2: serial@d4017000 { +- compatible = "mrvl,mmp-uart", "intel,xscale-uart"; +- reg = <0xd4017000 0x1000>; +- interrupts = <28>; +- clocks = <&soc_clocks MMP2_CLK_UART1>; +- resets = <&soc_clocks MMP2_CLK_UART1>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart3: serial@d4018000 { +- compatible = "mrvl,mmp-uart", "intel,xscale-uart"; +- reg = <0xd4018000 0x1000>; +- interrupts = <24>; +- clocks = <&soc_clocks MMP2_CLK_UART2>; +- resets = <&soc_clocks MMP2_CLK_UART2>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart4: serial@d4016000 { +- compatible = "mrvl,mmp-uart", "intel,xscale-uart"; +- reg = <0xd4016000 0x1000>; +- interrupts = <46>; +- clocks = <&soc_clocks MMP2_CLK_UART3>; +- resets = <&soc_clocks MMP2_CLK_UART3>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- gpio: gpio@d4019000 { +- compatible = "marvell,mmp2-gpio"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xd4019000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = <49>; +- interrupt-names = "gpio_mux"; +- clocks = <&soc_clocks MMP2_CLK_GPIO>; +- resets = <&soc_clocks MMP2_CLK_GPIO>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ranges; +- +- gcb0: gpio@d4019000 { +- reg = <0xd4019000 0x4>; +- }; +- +- gcb1: gpio@d4019004 { +- reg = <0xd4019004 0x4>; +- }; +- +- gcb2: gpio@d4019008 { +- reg = <0xd4019008 0x4>; +- }; +- +- gcb3: gpio@d4019100 { +- reg = <0xd4019100 0x4>; +- }; +- +- gcb4: gpio@d4019104 { +- reg = <0xd4019104 0x4>; +- }; +- +- gcb5: gpio@d4019108 { +- reg = <0xd4019108 0x4>; +- }; +- }; +- +- twsi1: i2c@d4011000 { +- compatible = "mrvl,mmp-twsi"; +- reg = <0xd4011000 0x1000>; +- interrupts = <7>; +- clocks = <&soc_clocks MMP2_CLK_TWSI0>; +- resets = <&soc_clocks MMP2_CLK_TWSI0>; +- #address-cells = <1>; +- #size-cells = <0>; +- mrvl,i2c-fast-mode; +- status = "disabled"; +- }; +- +- twsi2: i2c@d4031000 { +- compatible = "mrvl,mmp-twsi"; +- reg = <0xd4031000 0x1000>; +- interrupt-parent = <&intcmux17>; +- interrupts = <0>; +- clocks = <&soc_clocks MMP2_CLK_TWSI1>; +- resets = <&soc_clocks MMP2_CLK_TWSI1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- twsi3: i2c@d4032000 { +- compatible = "mrvl,mmp-twsi"; +- reg = <0xd4032000 0x1000>; +- interrupt-parent = <&intcmux17>; +- interrupts = <1>; +- clocks = <&soc_clocks MMP2_CLK_TWSI2>; +- resets = <&soc_clocks MMP2_CLK_TWSI2>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- twsi4: i2c@d4033000 { +- compatible = "mrvl,mmp-twsi"; +- reg = <0xd4033000 0x1000>; +- interrupt-parent = <&intcmux17>; +- interrupts = <2>; +- clocks = <&soc_clocks MMP2_CLK_TWSI3>; +- resets = <&soc_clocks MMP2_CLK_TWSI3>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- +- twsi5: i2c@d4033800 { +- compatible = "mrvl,mmp-twsi"; +- reg = <0xd4033800 0x1000>; +- interrupt-parent = <&intcmux17>; +- interrupts = <3>; +- clocks = <&soc_clocks MMP2_CLK_TWSI4>; +- resets = <&soc_clocks MMP2_CLK_TWSI4>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- twsi6: i2c@d4034000 { +- compatible = "mrvl,mmp-twsi"; +- reg = <0xd4034000 0x1000>; +- interrupt-parent = <&intcmux17>; +- interrupts = <4>; +- clocks = <&soc_clocks MMP2_CLK_TWSI5>; +- resets = <&soc_clocks MMP2_CLK_TWSI5>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- rtc: rtc@d4010000 { +- compatible = "mrvl,mmp-rtc"; +- reg = <0xd4010000 0x1000>; +- interrupts = <1>, <0>; +- interrupt-names = "rtc 1Hz", "rtc alarm"; +- interrupt-parent = <&intcmux5>; +- clocks = <&soc_clocks MMP2_CLK_RTC>; +- resets = <&soc_clocks MMP2_CLK_RTC>; +- status = "disabled"; +- }; +- +- ssp1: spi@d4035000 { +- compatible = "marvell,mmp2-ssp"; +- reg = <0xd4035000 0x1000>; +- clocks = <&soc_clocks MMP2_CLK_SSP0>; +- interrupts = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- ssp2: spi@d4036000 { +- compatible = "marvell,mmp2-ssp"; +- reg = <0xd4036000 0x1000>; +- clocks = <&soc_clocks MMP2_CLK_SSP1>; +- interrupts = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- ssp3: spi@d4037000 { +- compatible = "marvell,mmp2-ssp"; +- reg = <0xd4037000 0x1000>; +- clocks = <&soc_clocks MMP2_CLK_SSP2>; +- interrupts = <20>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- ssp4: spi@d4039000 { +- compatible = "marvell,mmp2-ssp"; +- reg = <0xd4039000 0x1000>; +- clocks = <&soc_clocks MMP2_CLK_SSP3>; +- interrupts = <21>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- asram: sram@e0000000 { +- compatible = "mmio-sram"; +- reg = <0xe0000000 0x10000>; +- ranges = <0 0xe0000000 0x10000>; +- #address-cells = <1>; +- #size-cells = <1>; +- status = "disabled"; +- }; +- +- soc_clocks: clocks { +- compatible = "marvell,mmp2-clock"; +- reg = <0xd4050000 0x2000>, +- <0xd4282800 0x400>, +- <0xd4015000 0x1000>; +- reg-names = "mpmu", "apmu", "apbc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mmp3-dell-ariel.dts b/scripts/dtc/include-prefixes/arm/mmp3-dell-ariel.dts +deleted file mode 100644 +index fe6df364a9eb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mmp3-dell-ariel.dts ++++ /dev/null +@@ -1,151 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * Dell Wyse 3020 a.k.a. "Ariel" a.k.a. Tx0D (T00D, T10D) +- * +- * Copyright (C) 2019 Lubomir Rintel +- */ +- +-/dts-v1/; +-#include "mmp3.dtsi" +-#include +-#include +- +-/ { +- model = "Dell Ariel"; +- compatible = "dell,wyse-ariel", "marvell,mmp3"; +- +- aliases { +- serial2 = &uart3; +- }; +- +- chosen { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- ranges; +- bootargs = "earlyprintk=ttyS2,115200 console=ttyS2,115200"; +- }; +- +- memory@0 { +- available = <0x7f700000 0x7ff00000 0x00000000 0x7f600000>; +- reg = <0x0 0x80000000>; +- device_type = "memory"; +- }; +- +- ec_input_spi: spi { +- compatible = "spi-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- num-chipselects = <0>; +- sck-gpios = <&gpio 55 GPIO_ACTIVE_HIGH>; +- miso-gpios = <&gpio 57 GPIO_ACTIVE_HIGH>; +- mosi-gpios = <&gpio 58 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&usb_otg0 { +- status = "okay"; +-}; +- +-&usb_otg_phy0 { +- status = "okay"; +-}; +- +-&hsic0 { +- status = "okay"; +- +- usb1@1 { +- compatible = "usb424,2640"; +- reg = <0x01>; +- #address-cells = <0x01>; +- #size-cells = <0x00>; +- +- mass-storage@1 { +- compatible = "usb424,4040"; +- reg = <0x01>; +- status = "disabled"; +- }; +- }; +-}; +- +-&hsic_phy0 { +- status = "okay"; +- reset-gpios = <&gpio 63 GPIO_ACTIVE_HIGH>; +-}; +- +-&mmc3 { +- status = "okay"; +- max-frequency = <50000000>; +- status = "okay"; +- bus-width = <8>; +- non-removable; +- cap-mmc-highspeed; +-}; +- +-&twsi1 { +- status = "okay"; +- +- rtc@68 { +- compatible = "dallas,ds1338"; +- reg = <0x68>; +- status = "okay"; +- }; +-}; +- +-&twsi3 { +- status = "okay"; +-}; +- +-&twsi4 { +- status = "okay"; +- +- embedded-controller@58 { +- compatible = "dell,wyse-ariel-ec", "ene,kb3930"; +- reg = <0x58>; +- system-power-controller; +- +- off-gpios = <&gpio 126 GPIO_ACTIVE_HIGH>, +- <&gpio 127 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&ssp1 { +- status = "okay"; +- cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +- +- firmware-flash@0 { +- compatible = "winbond,w25q32", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <104000000>; +- m25p,fast-read; +- }; +-}; +- +-&ec_input_spi { +- status = "okay"; +- cs-gpios = <&gpio 56 GPIO_ACTIVE_LOW>; +- +- power-button@0 { +- reg = <0>; +- interrupt-parent = <&gpio>; +- interrupts = <60 IRQ_TYPE_EDGE_RISING>; +- compatible = "dell,wyse-ariel-ec-input", "ene,kb3930-input"; +- spi-max-frequency = <33000000>; +- }; +-}; +- +-&gpu_2d { +- status = "okay"; +-}; +- +-&gpu_3d { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mmp3.dtsi b/scripts/dtc/include-prefixes/arm/mmp3.dtsi +deleted file mode 100644 +index a4fb9203ec1f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mmp3.dtsi ++++ /dev/null +@@ -1,608 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright (C) 2019 Lubomir Rintel +- */ +- +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "marvell,mmp3-smp"; +- +- cpu@0 { +- compatible = "marvell,pj4b"; +- device_type = "cpu"; +- next-level-cache = <&l2>; +- reg = <0>; +- }; +- +- cpu@1 { +- compatible = "marvell,pj4b"; +- device_type = "cpu"; +- next-level-cache = <&l2>; +- reg = <1>; +- }; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- ranges; +- +- axi@d4200000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xd4200000 0x00200000>; +- ranges; +- +- interrupt-controller@d4282000 { +- compatible = "marvell,mmp3-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0xd4282000 0x1000>, +- <0xd4284000 0x100>; +- mrvl,intc-nr-irqs = <64>; +- }; +- +- pmic_mux: interrupt-controller@d4282150 { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x150 0x4>, <0x168 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <4>; +- }; +- +- rtc_mux: interrupt-controller@d4282154 { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x154 0x4>, <0x16c 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <2>; +- }; +- +- hsi3_mux: interrupt-controller@d42821bc { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x1bc 0x4>, <0x1a4 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <3>; +- }; +- +- gpu_mux: interrupt-controller@d42821c0 { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x1c0 0x4>, <0x1a8 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <3>; +- }; +- +- twsi_mux: interrupt-controller@d4282158 { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x158 0x4>, <0x170 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <5>; +- }; +- +- hsi2_mux: interrupt-controller@d42821c4 { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x1c4 0x4>, <0x1ac 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <2>; +- }; +- +- dxo_mux: interrupt-controller@d42821c8 { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x1c8 0x4>, <0x1b0 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <2>; +- }; +- +- misc1_mux: interrupt-controller@d428215c { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x15c 0x4>, <0x174 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <31>; +- }; +- +- ci_mux: interrupt-controller@d42821cc { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x1cc 0x4>, <0x1b4 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <2>; +- }; +- +- ssp_mux: interrupt-controller@d4282160 { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x160 0x4>, <0x178 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <2>; +- }; +- +- hsi1_mux: interrupt-controller@d4282184 { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x184 0x4>, <0x17c 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <4>; +- }; +- +- misc2_mux: interrupt-controller@d4282188 { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x188 0x4>, <0x180 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <20>; +- }; +- +- hsi0_mux: interrupt-controller@d42821d0 { +- compatible = "mrvl,mmp2-mux-intc"; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x1d0 0x4>, <0x1b8 0x4>; +- reg-names = "mux status", "mux mask"; +- mrvl,intc-nr-irqs = <5>; +- }; +- +- usb_otg_phy0: usb-phy@d4207000 { +- compatible = "marvell,mmp3-usb-phy"; +- reg = <0xd4207000 0x40>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- usb_otg0: usb@d4208000 { +- compatible = "marvell,pxau2o-ehci"; +- reg = <0xd4208000 0x200>; +- interrupts = ; +- clocks = <&soc_clocks MMP2_CLK_USB>; +- clock-names = "USBCLK"; +- phys = <&usb_otg_phy0>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- hsic_phy0: usb-phy@f0001800 { +- compatible = "marvell,mmp3-hsic-phy"; +- reg = <0xf0001800 0x40>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- hsic0: usb@f0001000 { +- compatible = "marvell,pxau2o-ehci"; +- reg = <0xf0001000 0x200>; +- interrupts = ; +- clocks = <&soc_clocks MMP2_CLK_USBHSIC0>; +- clock-names = "USBCLK"; +- phys = <&hsic_phy0>; +- phy-names = "usb"; +- phy_type = "hsic"; +- #address-cells = <0x01>; +- #size-cells = <0x00>; +- status = "disabled"; +- }; +- +- hsic_phy1: usb-phy@f0002800 { +- compatible = "marvell,mmp3-hsic-phy"; +- reg = <0xf0002800 0x40>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- hsic1: usb@f0002000 { +- compatible = "marvell,pxau2o-ehci"; +- reg = <0xf0002000 0x200>; +- interrupts = ; +- clocks = <&soc_clocks MMP2_CLK_USBHSIC1>; +- clock-names = "USBCLK"; +- phys = <&hsic_phy1>; +- phy-names = "usb"; +- phy_type = "hsic"; +- #address-cells = <0x01>; +- #size-cells = <0x00>; +- status = "disabled"; +- }; +- +- mmc1: mmc@d4280000 { +- compatible = "mrvl,pxav3-mmc"; +- reg = <0xd4280000 0x120>; +- clocks = <&soc_clocks MMP2_CLK_SDH0>; +- clock-names = "io"; +- interrupts = ; +- status = "disabled"; +- }; +- +- mmc2: mmc@d4280800 { +- compatible = "mrvl,pxav3-mmc"; +- reg = <0xd4280800 0x120>; +- clocks = <&soc_clocks MMP2_CLK_SDH1>; +- clock-names = "io"; +- interrupts = ; +- status = "disabled"; +- }; +- +- mmc3: mmc@d4281000 { +- compatible = "mrvl,pxav3-mmc"; +- reg = <0xd4281000 0x120>; +- clocks = <&soc_clocks MMP2_CLK_SDH2>; +- clock-names = "io"; +- interrupts = ; +- status = "disabled"; +- }; +- +- mmc4: mmc@d4281800 { +- compatible = "mrvl,pxav3-mmc"; +- reg = <0xd4281800 0x120>; +- clocks = <&soc_clocks MMP2_CLK_SDH3>; +- clock-names = "io"; +- interrupts = ; +- status = "disabled"; +- }; +- +- mmc5: mmc@d4217000 { +- compatible = "mrvl,pxav3-mmc"; +- reg = <0xd4217000 0x120>; +- clocks = <&soc_clocks MMP3_CLK_SDH4>; +- clock-names = "io"; +- interrupt-parent = <&hsi1_mux>; +- interrupts = <0>; +- status = "disabled"; +- }; +- +- camera0: camera@d420a000 { +- compatible = "marvell,mmp2-ccic"; +- reg = <0xd420a000 0x800>; +- interrupts = <1>; +- interrupt-parent = <&ci_mux>; +- clocks = <&soc_clocks MMP2_CLK_CCIC0>; +- clock-names = "axi"; +- power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>; +- #clock-cells = <0>; +- clock-output-names = "mclk"; +- status = "disabled"; +- }; +- +- camera1: camera@d420a800 { +- compatible = "marvell,mmp2-ccic"; +- reg = <0xd420a800 0x800>; +- interrupts = <2>; +- interrupt-parent = <&ci_mux>; +- clocks = <&soc_clocks MMP2_CLK_CCIC1>; +- clock-names = "axi"; +- power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>; +- #clock-cells = <0>; +- clock-output-names = "mclk"; +- status = "disabled"; +- }; +- +- gpu_3d: gpu@d420d000 { +- compatible = "vivante,gc"; +- reg = <0xd420d000 0x2000>; +- interrupt-parent = <&gpu_mux>; +- interrupts = <0>; +- status = "disabled"; +- clocks = <&soc_clocks MMP3_CLK_GPU_3D>, +- <&soc_clocks MMP3_CLK_GPU_BUS>; +- clock-names = "core", "bus"; +- power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>; +- }; +- +- gpu_2d: gpu@d420f000 { +- compatible = "vivante,gc"; +- reg = <0xd420f000 0x2000>; +- interrupt-parent = <&gpu_mux>; +- interrupts = <2>; +- status = "disabled"; +- clocks = <&soc_clocks MMP3_CLK_GPU_2D>, +- <&soc_clocks MMP3_CLK_GPU_BUS>; +- clock-names = "core", "bus"; +- power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>; +- }; +- }; +- +- apb@d4000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xd4000000 0x00200000>; +- ranges; +- +- timer: timer@d4014000 { +- compatible = "mrvl,mmp-timer"; +- reg = <0xd4014000 0x100>; +- interrupts = ; +- clocks = <&soc_clocks MMP2_CLK_TIMER>; +- }; +- +- uart1: serial@d4030000 { +- compatible = "mrvl,mmp-uart", "intel,xscale-uart"; +- reg = <0xd4030000 0x1000>; +- interrupts = ; +- clocks = <&soc_clocks MMP2_CLK_UART0>; +- resets = <&soc_clocks MMP2_CLK_UART0>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart2: serial@d4017000 { +- compatible = "mrvl,mmp-uart", "intel,xscale-uart"; +- reg = <0xd4017000 0x1000>; +- interrupts = ; +- clocks = <&soc_clocks MMP2_CLK_UART1>; +- resets = <&soc_clocks MMP2_CLK_UART1>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart3: serial@d4018000 { +- compatible = "mrvl,mmp-uart", "intel,xscale-uart"; +- reg = <0xd4018000 0x1000>; +- interrupts = ; +- clocks = <&soc_clocks MMP2_CLK_UART2>; +- resets = <&soc_clocks MMP2_CLK_UART2>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart4: serial@d4016000 { +- compatible = "mrvl,mmp-uart", "intel,xscale-uart"; +- reg = <0xd4016000 0x1000>; +- interrupts = ; +- clocks = <&soc_clocks MMP2_CLK_UART3>; +- resets = <&soc_clocks MMP2_CLK_UART3>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- gpio: gpio@d4019000 { +- compatible = "marvell,mmp2-gpio"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xd4019000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = ; +- interrupt-names = "gpio_mux"; +- clocks = <&soc_clocks MMP2_CLK_GPIO>; +- resets = <&soc_clocks MMP2_CLK_GPIO>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ranges; +- +- gcb0: gpio@d4019000 { +- reg = <0xd4019000 0x4>; +- }; +- +- gcb1: gpio@d4019004 { +- reg = <0xd4019004 0x4>; +- }; +- +- gcb2: gpio@d4019008 { +- reg = <0xd4019008 0x4>; +- }; +- +- gcb3: gpio@d4019100 { +- reg = <0xd4019100 0x4>; +- }; +- +- gcb4: gpio@d4019104 { +- reg = <0xd4019104 0x4>; +- }; +- +- gcb5: gpio@d4019108 { +- reg = <0xd4019108 0x4>; +- }; +- }; +- +- twsi1: i2c@d4011000 { +- compatible = "mrvl,mmp-twsi"; +- reg = <0xd4011000 0x70>; +- interrupts = ; +- clocks = <&soc_clocks MMP2_CLK_TWSI0>; +- resets = <&soc_clocks MMP2_CLK_TWSI0>; +- #address-cells = <1>; +- #size-cells = <0>; +- mrvl,i2c-fast-mode; +- status = "disabled"; +- }; +- +- twsi2: i2c@d4031000 { +- compatible = "mrvl,mmp-twsi"; +- reg = <0xd4031000 0x70>; +- interrupt-parent = <&twsi_mux>; +- interrupts = <0>; +- clocks = <&soc_clocks MMP2_CLK_TWSI1>; +- resets = <&soc_clocks MMP2_CLK_TWSI1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- twsi3: i2c@d4032000 { +- compatible = "mrvl,mmp-twsi"; +- reg = <0xd4032000 0x70>; +- interrupt-parent = <&twsi_mux>; +- interrupts = <1>; +- clocks = <&soc_clocks MMP2_CLK_TWSI2>; +- resets = <&soc_clocks MMP2_CLK_TWSI2>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- twsi4: i2c@d4033000 { +- compatible = "mrvl,mmp-twsi"; +- reg = <0xd4033000 0x70>; +- interrupt-parent = <&twsi_mux>; +- interrupts = <2>; +- clocks = <&soc_clocks MMP2_CLK_TWSI3>; +- resets = <&soc_clocks MMP2_CLK_TWSI3>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- +- twsi5: i2c@d4033800 { +- compatible = "mrvl,mmp-twsi"; +- reg = <0xd4033800 0x70>; +- interrupt-parent = <&twsi_mux>; +- interrupts = <3>; +- clocks = <&soc_clocks MMP2_CLK_TWSI4>; +- resets = <&soc_clocks MMP2_CLK_TWSI4>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- twsi6: i2c@d4034000 { +- compatible = "mrvl,mmp-twsi"; +- reg = <0xd4034000 0x70>; +- interrupt-parent = <&twsi_mux>; +- interrupts = <4>; +- clocks = <&soc_clocks MMP2_CLK_TWSI5>; +- resets = <&soc_clocks MMP2_CLK_TWSI5>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- rtc: rtc@d4010000 { +- compatible = "mrvl,mmp-rtc"; +- reg = <0xd4010000 0x1000>; +- interrupts = <1>, <0>; +- interrupt-names = "rtc 1Hz", "rtc alarm"; +- interrupt-parent = <&rtc_mux>; +- clocks = <&soc_clocks MMP2_CLK_RTC>; +- resets = <&soc_clocks MMP2_CLK_RTC>; +- status = "disabled"; +- }; +- +- ssp1: spi@d4035000 { +- compatible = "marvell,mmp2-ssp"; +- reg = <0xd4035000 0x1000>; +- clocks = <&soc_clocks MMP2_CLK_SSP0>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- ssp2: spi@d4036000 { +- compatible = "marvell,mmp2-ssp"; +- reg = <0xd4036000 0x1000>; +- clocks = <&soc_clocks MMP2_CLK_SSP1>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- ssp3: spi@d4037000 { +- compatible = "marvell,mmp2-ssp"; +- reg = <0xd4037000 0x1000>; +- clocks = <&soc_clocks MMP2_CLK_SSP2>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- ssp4: spi@d4039000 { +- compatible = "marvell,mmp2-ssp"; +- reg = <0xd4039000 0x1000>; +- clocks = <&soc_clocks MMP2_CLK_SSP3>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- l2: cache-controller@d0020000 { +- compatible = "marvell,tauros3-cache", "arm,pl310-cache"; +- reg = <0xd0020000 0x1000>; +- cache-unified; +- cache-level = <2>; +- }; +- +- soc_clocks: clocks@d4050000 { +- compatible = "marvell,mmp3-clock"; +- reg = <0xd4050000 0x2000>, +- <0xd4282800 0x400>, +- <0xd4015000 0x1000>; +- reg-names = "mpmu", "apmu", "apbc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- }; +- +- snoop-control-unit@e0000000 { +- compatible = "arm,arm11mp-scu"; +- reg = <0xe0000000 0x100>; +- }; +- +- gic: interrupt-controller@e0001000 { +- compatible = "arm,arm11mp-gic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0xe0001000 0x1000>, +- <0xe0000100 0x100>; +- }; +- +- local-timer@e0000600 { +- compatible = "arm,arm11mp-twd-timer"; +- interrupts = ; +- reg = <0xe0000600 0x20>; +- }; +- +- watchdog@e0000620 { +- compatible = "arm,arm11mp-twd-wdt"; +- reg = <0xe0000620 0x20>; +- interrupts = ; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/motorola-cpcap-mapphone.dtsi b/scripts/dtc/include-prefixes/arm/motorola-cpcap-mapphone.dtsi +deleted file mode 100644 +index ea02fd403a9b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/motorola-cpcap-mapphone.dtsi ++++ /dev/null +@@ -1,272 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Common CPCAP configuration used on Motorola phones +- */ +- +-&mcspi1 { +- cpcap: pmic@0 { +- compatible = "motorola,cpcap", "st,6556002"; +- reg = <0>; /* cs0 */ +- interrupt-parent = <&gpio1>; +- interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-controller; +- #interrupt-cells = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- spi-max-frequency = <9600000>; +- spi-cs-high; +- spi-cpol; +- spi-cpha; +- +- cpcap_adc: adc { +- compatible = "motorola,mapphone-cpcap-adc"; +- interrupts-extended = <&cpcap 8 0>; +- interrupt-names = "adcdone"; +- #io-channel-cells = <1>; +- }; +- +- cpcap_battery: battery { +- compatible = "motorola,cpcap-battery"; +- interrupts-extended = +- <&cpcap 6 0>, <&cpcap 5 0>, <&cpcap 3 0>, +- <&cpcap 20 0>, <&cpcap 54 0>, <&cpcap 57 0>; +- interrupt-names = +- "eol", "lowbph", "lowbpl", +- "chrgcurr1", "battdetb", "cccal"; +- io-channels = <&cpcap_adc 0>, <&cpcap_adc 1>, +- <&cpcap_adc 5>, <&cpcap_adc 6>; +- io-channel-names = "battdetb", "battp", +- "chg_isense", "batti"; +- power-supplies = <&cpcap_charger>; +- }; +- +- cpcap_charger: charger { +- compatible = "motorola,mapphone-cpcap-charger"; +- interrupts-extended = +- <&cpcap 13 0>, <&cpcap 12 0>, <&cpcap 29 0>, +- <&cpcap 28 0>, <&cpcap 22 0>, <&cpcap 21 0>, +- <&cpcap 20 0>, <&cpcap 19 0>, <&cpcap 54 0>; +- interrupt-names = +- "chrg_det", "rvrs_chrg", "chrg_se1b", +- "se0conn", "rvrs_mode", "chrgcurr2", +- "chrgcurr1", "vbusvld", "battdetb"; +- mode-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>, +- <&gpio3 23 GPIO_ACTIVE_LOW>; +- io-channels = <&cpcap_adc 0>, <&cpcap_adc 1>, +- <&cpcap_adc 2>, <&cpcap_adc 5>, +- <&cpcap_adc 6>; +- io-channel-names = "battdetb", "battp", +- "vbus", "chg_isense", +- "batti"; +- }; +- +- cpcap_regulator: regulator { +- compatible = "motorola,mapphone-cpcap-regulator"; +- +- cpcap_regulators: regulators { +- }; +- }; +- +- cpcap_audio: audio-codec { +- #sound-dai-cells = <1>; +- +- port@0 { +- cpcap_audio_codec0: endpoint { +- }; +- }; +- port@1 { +- cpcap_audio_codec1: endpoint { +- }; +- }; +- }; +- +- cpcap_rtc: rtc { +- compatible = "motorola,cpcap-rtc"; +- +- interrupt-parent = <&cpcap>; +- interrupts = <39 IRQ_TYPE_NONE>, <26 IRQ_TYPE_NONE>; +- }; +- +- power_button: button { +- compatible = "motorola,cpcap-pwrbutton"; +- +- interrupts = <23 IRQ_TYPE_NONE>; +- }; +- +- cpcap_usb2_phy: phy { +- compatible = "motorola,mapphone-cpcap-usb-phy"; +- pinctrl-0 = <&usb_gpio_mux_sel1>, <&usb_gpio_mux_sel2>; +- pinctrl-1 = <&usb_ulpi_pins>; +- pinctrl-2 = <&usb_utmi_pins>; +- pinctrl-3 = <&uart3_pins>; +- pinctrl-names = "default", "ulpi", "utmi", "uart"; +- #phy-cells = <0>; +- interrupts-extended = +- <&cpcap 15 0>, <&cpcap 14 0>, <&cpcap 28 0>, +- <&cpcap 19 0>, <&cpcap 18 0>, <&cpcap 17 0>, +- <&cpcap 16 0>, <&cpcap 49 0>, <&cpcap 48 0>; +- interrupt-names = +- "id_ground", "id_float", "se0conn", +- "vbusvld", "sessvld", "sessend", +- "se1", "dm", "dp"; +- mode-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, +- <&gpio1 0 GPIO_ACTIVE_HIGH>; +- io-channels = <&cpcap_adc 2>, <&cpcap_adc 7>; +- io-channel-names = "vbus", "id"; +- vusb-supply = <&vusb>; +- }; +- +- led_red: led-red { +- compatible = "motorola,cpcap-led-red"; +- vdd-supply = <&sw5>; +- label = "status-led:red"; +- }; +- +- led_green: led-green { +- compatible = "motorola,cpcap-led-green"; +- vdd-supply = <&sw5>; +- label = "status-led:green"; +- }; +- +- led_blue: led-blue { +- compatible = "motorola,cpcap-led-blue"; +- vdd-supply = <&sw5>; +- label = "status-led:blue"; +- }; +- +- led_adl: led-adl { +- compatible = "motorola,cpcap-led-adl"; +- vdd-supply = <&sw5>; +- label = "button-backlight"; +- }; +- +- led_cp: led-cp { +- compatible = "motorola,cpcap-led-cp"; +- vdd-supply = <&sw5>; +- label = "shift-key-light"; +- }; +- }; +-}; +- +-&cpcap_regulators { +- sw5: SW5 { +- regulator-min-microvolt = <5050000>; +- regulator-max-microvolt = <5050000>; +- regulator-enable-ramp-delay = <50000>; +- regulator-boot-on; +- }; +- +- vcam: VCAM { +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- regulator-enable-ramp-delay = <1000>; +- }; +- +- /* Used by DSS and is the "zerov_regulator" trigger for SoC off mode */ +- vcsi: VCSI { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <1000>; +- regulator-always-on; +- }; +- +- vdac: VDAC { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <1000>; +- }; +- +- vdig: VDIG { +- regulator-min-microvolt = <1875000>; +- regulator-max-microvolt = <1875000>; +- regulator-enable-ramp-delay = <1000>; +- }; +- +- vfuse: VFUSE { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <3150000>; +- regulator-enable-ramp-delay = <1000>; +- }; +- +- vhvio: VHVIO { +- regulator-min-microvolt = <2775000>; +- regulator-max-microvolt = <2775000>; +- regulator-enable-ramp-delay = <1000>; +- regulator-always-on; +- }; +- +- /* Used by eMMC at mmc2 */ +- vsdio: VSDIO { +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- regulator-enable-ramp-delay = <1000>; +- }; +- +- vpll: VPLL { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <100>; +- }; +- +- vrf1: VRF1 { +- regulator-min-microvolt = <2775000>; +- regulator-max-microvolt = <2775000>; +- regulator-enable-ramp-delay = <1000>; +- }; +- +- vrf2: VRF2 { +- regulator-min-microvolt = <2775000>; +- regulator-max-microvolt = <2775000>; +- regulator-enable-ramp-delay = <1000>; +- }; +- +- vrfref: VRFREF { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2775000>; +- regulator-enable-ramp-delay = <100>; +- }; +- +- vwlan1: VWLAN1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1900000>; +- regulator-enable-ramp-delay = <1000>; +- }; +- +- /* Used by micro-SDIO at mmc1 */ +- vwlan2: VWLAN2 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-enable-ramp-delay = <1000>; +- }; +- +- vsim: VSIM { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2900000>; +- regulator-enable-ramp-delay = <1000>; +- }; +- +- vsimcard: VSIMCARD { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2900000>; +- regulator-enable-ramp-delay = <1000>; +- }; +- +- vvib: VVIB { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <3000000>; +- regulator-enable-ramp-delay = <500>; +- }; +- +- vusb: VUSB { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <1000>; +- }; +- +- vaudio: VAUDIO { +- regulator-min-microvolt = <2775000>; +- regulator-max-microvolt = <2775000>; +- regulator-enable-ramp-delay = <1000>; +- regulator-initial-mode = <0x00>; /* NORMAL */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/motorola-mapphone-common.dtsi b/scripts/dtc/include-prefixes/arm/motorola-mapphone-common.dtsi +deleted file mode 100644 +index a4423ff0df39..000000000000 +--- a/scripts/dtc/include-prefixes/arm/motorola-mapphone-common.dtsi ++++ /dev/null +@@ -1,737 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/dts-v1/; +- +-#include +-#include "omap443x.dtsi" +-#include "motorola-cpcap-mapphone.dtsi" +- +-/ { +- chosen { +- stdout-path = &uart3; +- }; +- +- aliases { +- display0 = &lcd0; +- display1 = &hdmi0; +- }; +- +- /* +- * We seem to have only 1021 MB accessible, 1021 - 1022 is locked, +- * then 1023 - 1024 seems to contain mbm. +- */ +- memory { +- device_type = "memory"; +- reg = <0x80000000 0x3fd00000>; /* 1021 MB */ +- }; +- +- /* Poweroff GPIO probably connected to CPCAP */ +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- pinctrl-0 = <&poweroff_gpio>; +- pinctrl-names = "default"; +- gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; /* gpio50 */ +- }; +- +- hdmi0: connector { +- compatible = "hdmi-connector"; +- pinctrl-0 = <&hdmi_hpd_gpio>; +- pinctrl-names = "default"; +- label = "hdmi"; +- type = "d"; +- +- hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio63 */ +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_out>; +- }; +- }; +- }; +- +- /* +- * HDMI 5V regulator probably sourced from battery. Let's keep +- * keep this as always enabled for HDMI to work until we've +- * figured what the encoder chip is. +- */ +- hdmi_regulator: regulator-hdmi { +- compatible = "regulator-fixed"; +- regulator-name = "hdmi"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio59 */ +- enable-active-high; +- regulator-always-on; +- }; +- +- /* FS USB Host PHY on port 1 for mdm6600 */ +- fsusb1_phy: usb-phy@1 { +- compatible = "motorola,mapphone-mdm6600"; +- pinctrl-0 = <&usb_mdm6600_pins>; +- pinctrl-names = "default"; +- enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; /* gpio_95 */ +- power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54 */ +- reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; /* gpio_49 */ +- /* mode: gpio_148 gpio_149 */ +- motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>, +- <&gpio5 21 GPIO_ACTIVE_HIGH>; +- /* cmd: gpio_103 gpio_104 gpio_142 */ +- motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>, +- <&gpio4 8 GPIO_ACTIVE_HIGH>, +- <&gpio5 14 GPIO_ACTIVE_HIGH>; +- /* status: gpio_52 gpio_53 gpio_55 */ +- motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>, +- <&gpio2 21 GPIO_ACTIVE_HIGH>, +- <&gpio2 23 GPIO_ACTIVE_HIGH>; +- #phy-cells = <0>; +- }; +- +- /* HS USB host TLL nop-phy on port 2 for w3glte */ +- hsusb2_phy: usb-phy@2 { +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- }; +- +- /* LCD regulator from sw5 source */ +- lcd_regulator: regulator-lcd { +- compatible = "regulator-fixed"; +- regulator-name = "lcd"; +- regulator-min-microvolt = <5050000>; +- regulator-max-microvolt = <5050000>; +- gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; /* gpio96 */ +- enable-active-high; +- vin-supply = <&sw5>; +- }; +- +- /* This is probably coming straight from the battery.. */ +- wl12xx_vmmc: regulator-wl12xx { +- compatible = "regulator-fixed"; +- regulator-name = "vwl1271"; +- regulator-min-microvolt = <1650000>; +- regulator-max-microvolt = <1650000>; +- gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; /* gpio94 */ +- startup-delay-us = <70000>; +- enable-active-high; +- }; +- +- soundcard { +- compatible = "audio-graph-card"; +- label = "Mapphone Audio"; +- +- widgets = +- "Speaker", "Earpiece", +- "Speaker", "Loudspeaker", +- "Headphone", "Headphone Jack", +- "Microphone", "Internal Mic"; +- +- routing = +- "Earpiece", "EP", +- "Loudspeaker", "SPKR", +- "Headphone Jack", "HSL", +- "Headphone Jack", "HSR", +- "MICR", "Internal Mic"; +- +- dais = <&mcbsp2_port>, <&mcbsp3_port>; +- }; +- +- pwm8: dmtimer-pwm-8 { +- pinctrl-names = "default"; +- pinctrl-0 = <&vibrator_direction_pin>; +- +- compatible = "ti,omap-dmtimer-pwm"; +- #pwm-cells = <3>; +- ti,timers = <&timer8>; +- ti,clock-source = <0x01>; +- }; +- +- pwm9: dmtimer-pwm-9 { +- pinctrl-names = "default"; +- pinctrl-0 = <&vibrator_enable_pin>; +- +- compatible = "ti,omap-dmtimer-pwm"; +- #pwm-cells = <3>; +- ti,timers = <&timer9>; +- ti,clock-source = <0x01>; +- }; +- +- vibrator { +- compatible = "pwm-vibrator"; +- pwms = <&pwm9 0 10000000 0>, <&pwm8 0 10000000 0>; +- pwm-names = "enable", "direction"; +- direction-duty-cycle-ns = <10000000>; +- }; +- +- backlight: backlight { +- compatible = "led-backlight"; +- +- leds = <&backlight_led>; +- brightness-levels = <31 63 95 127 159 191 223 255>; +- default-brightness-level = <6>; +- }; +-}; +- +-&cpu_thermal { +- polling-delay = <10000>; /* milliseconds */ +-}; +- +-&cpu_alert0 { +- temperature = <80000>; /* millicelsius */ +-}; +- +-&cpu0 { +- /* +- * Note that the 1.2GiHz mode is enabled for all SoC variants for +- * the Motorola Android Linux v3.0.8 based kernel. +- */ +- operating-points = < +- /* kHz uV */ +- 300000 1025000 +- 600000 1200000 +- 800000 1313000 +- 1008000 1375000 +- 1200000 1375000 +- >; +-}; +- +-&dss { +- status = "okay"; +-}; +- +-&dsi1 { +- status = "okay"; +- vdd-supply = <&vcsi>; +- +- port { +- dsi1_out_ep: endpoint { +- remote-endpoint = <&lcd0_in>; +- lanes = <0 1 2 3 4 5>; +- }; +- }; +- +- lcd0: panel@0 { +- compatible = "motorola,droid4-panel", "panel-dsi-cm"; +- reg = <0>; +- label = "lcd0"; +- vddi-supply = <&lcd_regulator>; +- reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ +- +- backlight = <&backlight>; +- +- width-mm = <50>; +- height-mm = <89>; +- rotation = <90>; +- +- panel-timing { +- clock-frequency = <0>; /* Calculated by dsi */ +- +- hback-porch = <2>; +- hactive = <540>; +- hfront-porch = <0>; +- hsync-len = <2>; +- +- vback-porch = <1>; +- vactive = <960>; +- vfront-porch = <0>; +- vsync-len = <1>; +- +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- +- port { +- lcd0_in: endpoint { +- remote-endpoint = <&dsi1_out_ep>; +- }; +- }; +- }; +-}; +- +-&hdmi { +- status = "okay"; +- pinctrl-0 = <&dss_hdmi_pins>; +- pinctrl-names = "default"; +- vdda-supply = <&vdac>; +- +- port { +- hdmi_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- lanes = <1 0 3 2 5 4 7 6>; +- }; +- }; +-}; +- +-/* Battery NVRAM on 1-wire handled by w1_ds250x driver */ +-&hdqw1w { +- pinctrl-0 = <&hdq_pins>; +- pinctrl-names = "default"; +- ti,mode = "1w"; +-}; +- +-&i2c1 { +- tmp105@48 { +- compatible = "ti,tmp105"; +- reg = <0x48>; +- pinctrl-0 = <&tmp105_irq>; +- pinctrl-names = "default"; +- /* kpd_row0.gpio_178 */ +- interrupts-extended = <&gpio6 18 IRQ_TYPE_EDGE_FALLING +- &omap4_pmx_core 0x14e>; +- interrupt-names = "irq", "wakeup"; +- wakeup-source; +- }; +-}; +- +-&mmc1 { +- vmmc-supply = <&vwlan2>; +- bus-width = <4>; +- cd-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* gpio176 */ +-}; +- +-&mmc2 { +- vmmc-supply = <&vsdio>; +- bus-width = <8>; +- ti,non-removable; +-}; +- +-&mmc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc3_pins>; +- vmmc-supply = <&wl12xx_vmmc>; +- /* uart2_tx.sdmmc3_dat1 pad as wakeirq */ +- interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH +- &omap4_pmx_core 0xde>; +- interrupt-names = "irq", "wakeup"; +- non-removable; +- bus-width = <4>; +- cap-power-off-card; +- keep-power-in-suspend; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1285", "ti,wl1283"; +- reg = <2>; +- /* gpio_100 with gpmc_wait2 pad as wakeirq */ +- interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>, +- <&omap4_pmx_core 0x4e>; +- interrupt-names = "irq", "wakeup"; +- ref-clock-frequency = <26000000>; +- tcxo-clock-frequency = <26000000>; +- }; +-}; +- +-&i2c2 { +- touchscreen@4a { +- compatible = "atmel,maxtouch"; +- reg = <0x4a>; +- pinctrl-names = "default"; +- pinctrl-0 = <&touchscreen_pins>; +- +- reset-gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; /* gpio173 */ +- +- /* gpio_183 with sys_nirq2 pad as wakeup */ +- interrupts-extended = <&gpio6 23 IRQ_TYPE_LEVEL_LOW>, +- <&omap4_pmx_core 0x160>; +- interrupt-names = "irq", "wakeup"; +- wakeup-source; +- }; +- +- isl29030@44 { +- compatible = "isil,isl29030"; +- reg = <0x44>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&als_proximity_pins>; +- +- interrupt-parent = <&gpio6>; +- interrupts = <17 IRQ_TYPE_LEVEL_LOW>; /* gpio177 */ +- }; +-}; +- +-&omap4_pmx_core { +- +- /* hdmi_hpd.gpio_63 */ +- hdmi_hpd_gpio: pinmux_hdmi_hpd_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3) +- >; +- }; +- +- hdq_pins: pinmux_hdq_pins { +- pinctrl-single,pins = < +- /* 0x4a100120 hdq_sio.hdq_sio aa27 */ +- OMAP4_IOPAD(0x120, PIN_INPUT | MUX_MODE0) +- >; +- }; +- +- /* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */ +- dss_hdmi_pins: pinmux_dss_hdmi_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) +- OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) +- OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) +- >; +- }; +- +- /* +- * Android uses PIN_OFF_INPUT_PULLDOWN | PIN_INPUT_PULLUP | MUX_MODE3 +- * for gpio_100, but the internal pull makes wlan flakey on some +- * devices. Off mode value should be tested if we have off mode working +- * later on. +- */ +- mmc3_pins: pinmux_mmc3_pins { +- pinctrl-single,pins = < +- /* 0x4a10008e gpmc_wait2.gpio_100 d23 */ +- OMAP4_IOPAD(0x08e, PIN_INPUT | MUX_MODE3) +- +- /* 0x4a100102 abe_mcbsp1_dx.sdmmc3_dat2 ab25 */ +- OMAP4_IOPAD(0x102, PIN_INPUT_PULLUP | MUX_MODE1) +- +- /* 0x4a100104 abe_mcbsp1_fsx.sdmmc3_dat3 ac27 */ +- OMAP4_IOPAD(0x104, PIN_INPUT_PULLUP | MUX_MODE1) +- +- /* 0x4a100118 uart2_cts.sdmmc3_clk ab26 */ +- OMAP4_IOPAD(0x118, PIN_INPUT | MUX_MODE1) +- +- /* 0x4a10011a uart2_rts.sdmmc3_cmd ab27 */ +- OMAP4_IOPAD(0x11a, PIN_INPUT_PULLUP | MUX_MODE1) +- +- /* 0x4a10011c uart2_rx.sdmmc3_dat0 aa25 */ +- OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE1) +- +- /* 0x4a10011e uart2_tx.sdmmc3_dat1 aa26 */ +- OMAP4_IOPAD(0x11e, PIN_INPUT_PULLUP | MUX_MODE1) +- >; +- }; +- +- /* gpmc_ncs0.gpio_50 */ +- poweroff_gpio: pinmux_poweroff_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x074, PIN_OUTPUT_PULLUP | MUX_MODE3) +- >; +- }; +- +- /* kpd_row0.gpio_178 */ +- tmp105_irq: pinmux_tmp105_irq { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x18e, PIN_INPUT_PULLUP | MUX_MODE3) +- >; +- }; +- +- usb_gpio_mux_sel1: pinmux_usb_gpio_mux_sel1_pins { +- /* gpio_60 */ +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) +- >; +- }; +- +- touchscreen_pins: pinmux_touchscreen_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3) +- OMAP4_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE3) +- >; +- }; +- +- als_proximity_pins: pinmux_als_proximity_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x18c, PIN_INPUT_PULLUP | MUX_MODE3) +- >; +- }; +- +- usb_mdm6600_pins: pinmux_usb_mdm6600_pins { +- pinctrl-single,pins = < +- /* enable 0x4a1000d8 usbb1_ulpitll_dat7.gpio_95 ag16 */ +- OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3) +- +- /* power 0x4a10007c gpmc_nwp.gpio_54 c25 */ +- OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3) +- +- /* reset 0x4a100072 gpmc_a25.gpio_49 d20 */ +- OMAP4_IOPAD(0x072, PIN_OUTPUT | MUX_MODE3) +- +- /* mode0/bpwake 0x4a10014e sdmmc5_dat1.gpio_148 af4 */ +- OMAP4_IOPAD(0x14e, PIN_OUTPUT | MUX_MODE3) +- +- /* mode1/apwake 0x4a100150 sdmmc5_dat2.gpio_149 ag3 */ +- OMAP4_IOPAD(0x150, PIN_OFF_OUTPUT_LOW | PIN_INPUT | MUX_MODE3) +- +- /* status0 0x4a10007e gpmc_clk.gpio_55 b22 */ +- OMAP4_IOPAD(0x07e, PIN_INPUT | MUX_MODE3) +- +- /* status1 0x4a10007a gpmc_ncs3.gpio_53 c22 */ +- OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) +- +- /* status2 0x4a100078 gpmc_ncs2.gpio_52 d21 */ +- OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3) +- +- /* cmd0 0x4a100094 gpmc_ncs6.gpio_103 c24 */ +- OMAP4_IOPAD(0x094, PIN_OUTPUT | MUX_MODE3) +- +- /* cmd1 0x4a100096 gpmc_ncs7.gpio_104 d24 */ +- OMAP4_IOPAD(0x096, PIN_OUTPUT | MUX_MODE3) +- +- /* cmd2 0x4a100142 uart3_rts_sd.gpio_142 f28 */ +- OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE3) +- >; +- }; +- +- usb_ulpi_pins: pinmux_usb_ulpi_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x196, MUX_MODE7) +- OMAP4_IOPAD(0x198, MUX_MODE7) +- OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE0) +- OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) +- OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE0) +- OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE0) +- OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE0) +- OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE0) +- OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE0) +- OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE0) +- OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE0) +- OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE0) +- OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE0) +- OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE0) +- >; +- }; +- +- /* usb0_otg_dp and usb0_otg_dm */ +- usb_utmi_pins: pinmux_usb_utmi_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) +- OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) +- OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7) +- >; +- }; +- +- /* +- * Note that the v3.0.8 stock userspace dynamically remuxes uart1 +- * rts pin probably for PM purposes to PIN_INPUT_PULLUP | MUX_MODE7 +- * when not used. If needed, we can add rts pin remux later based +- * on power measurements. +- */ +- uart1_pins: pinmux_uart1_pins { +- pinctrl-single,pins = < +- /* 0x4a10013c mcspi1_cs2.uart1_cts ag23 */ +- OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) +- +- /* 0x4a10013e mcspi1_cs3.uart1_rts ah23 */ +- OMAP4_IOPAD(0x13e, MUX_MODE1) +- +- /* 0x4a100140 uart3_cts_rctx.uart1_tx f27 */ +- OMAP4_IOPAD(0x140, PIN_OUTPUT | MUX_MODE1) +- +- /* 0x4a1001ca dpm_emu14.uart1_rx aa3 */ +- OMAP4_IOPAD(0x1ca, PIN_INPUT_PULLUP | MUX_MODE2) +- >; +- }; +- +- /* uart3_tx_irtx and uart3_rx_irrx */ +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x196, MUX_MODE7) +- OMAP4_IOPAD(0x198, MUX_MODE7) +- OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1ba, MUX_MODE2) +- OMAP4_IOPAD(0x1bc, PIN_INPUT | MUX_MODE2) +- OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7) +- OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7) +- >; +- }; +- +- uart4_pins: pinmux_uart4_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx */ +- OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx */ +- OMAP4_IOPAD(0x110, PIN_INPUT_PULLUP | MUX_MODE5) /* uart4_cts */ +- OMAP4_IOPAD(0x112, PIN_OUTPUT_PULLUP | MUX_MODE5) /* uart4_rts */ +- >; +- }; +- +- mcbsp2_pins: pinmux_mcbsp2_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx */ +- OMAP4_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_dr */ +- OMAP4_IOPAD(0x0fa, PIN_OUTPUT | MUX_MODE0) /* abe_mcbsp2_dx */ +- OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx */ +- >; +- }; +- +- mcbsp3_pins: pinmux_mcbsp3_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x106, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_dr */ +- OMAP4_IOPAD(0x108, PIN_OUTPUT | MUX_MODE1) /* abe_mcbsp3_dx */ +- OMAP4_IOPAD(0x10a, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_clkx */ +- OMAP4_IOPAD(0x10c, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_fsx */ +- >; +- }; +- +- vibrator_direction_pin: pinmux_vibrator_direction_pin { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */ +- >; +- }; +- +- vibrator_enable_pin: pinmux_vibrator_enable_pin { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */ +- >; +- }; +-}; +- +-&omap4_pmx_wkup { +- usb_gpio_mux_sel2: pinmux_usb_gpio_mux_sel2_pins { +- /* gpio_wk0 */ +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3) +- >; +- }; +-}; +- +-/* RNG is used by secure mode and not accessible */ +-&rng_target { +- status = "disabled"; +-}; +- +-/* Configure pwm clock source for timers 8 & 9 */ +-&timer8 { +- assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>; +- assigned-clock-parents = <&sys_clkin_ck>; +-}; +- +-&timer9 { +- assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>; +- assigned-clock-parents = <&sys_clkin_ck>; +-}; +- +-/* +- * The uart1 port is wired to mdm6600 with rts and cts. The modem uses gpio_149 +- * for wake-up events for both the USB PHY and the UART. We can use gpio_149 +- * pad as the shared wakeirq for the UART rather than the RX or CTS pad as we +- * have gpio_149 trigger before the UART transfer starts. +- */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- interrupts-extended = <&wakeupgen GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH +- &omap4_pmx_core 0x110>; +- uart-has-rtscts; +- current-speed = <115200>; +-}; +- +-&uart3 { +- interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH +- &omap4_pmx_core 0x17c>; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pins>; +- +- bluetooth { +- compatible = "ti,wl1285-st"; +- enable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; /* gpio 174 */ +- max-speed = <3686400>; +- }; +-}; +- +-&usbhsohci { +- phys = <&fsusb1_phy>; +- phy-names = "usb"; +-}; +- +-&usbhsehci { +- phys = <&hsusb2_phy>; +-}; +- +-&usbhshost { +- port1-mode = "ohci-phy-4pin-dpdm"; +- port2-mode = "ehci-tll"; +-}; +- +-/* Internal UTMI+ PHY used for OTG, CPCAP ULPI PHY for detection and charger */ +-&usb_otg_hs { +- interface-type = <1>; +- mode = <3>; +- +- /* +- * Max 300 mA steps based on similar PMIC MC13783UG.pdf "Table 10-4. +- * VBUS Regulator Main Characteristics". Binding uses 2 mA units. +- */ +- power = <150>; +-}; +- +-&i2c4 { +- ak8975: magnetometer@c { +- compatible = "asahi-kasei,ak8975"; +- reg = <0x0c>; +- +- vdd-supply = <&vhvio>; +- +- interrupt-parent = <&gpio6>; +- interrupts = <15 IRQ_TYPE_EDGE_RISING>; /* gpio175 */ +- +- rotation-matrix = "-1", "0", "0", +- "0", "1", "0", +- "0", "0", "-1"; +- +- }; +-}; +- +-&mcbsp2 { +- #sound-dai-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp2_pins>; +- status = "okay"; +- +- mcbsp2_port: port { +- cpu_dai2: endpoint { +- dai-format = "i2s"; +- remote-endpoint = <&cpcap_audio_codec0>; +- frame-master = <&cpcap_audio_codec0>; +- bitclock-master = <&cpcap_audio_codec0>; +- }; +- }; +-}; +- +-&mcbsp3 { +- #sound-dai-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp3_pins>; +- status = "okay"; +- +- mcbsp3_port: port { +- cpu_dai3: endpoint { +- dai-format = "dsp_a"; +- frame-master = <&cpcap_audio_codec1>; +- bitclock-master = <&cpcap_audio_codec1>; +- remote-endpoint = <&cpcap_audio_codec1>; +- }; +- }; +-}; +- +-&cpcap_audio_codec0 { +- remote-endpoint = <&cpu_dai2>; +-}; +- +-&cpcap_audio_codec1 { +- remote-endpoint = <&cpu_dai3>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/moxart-uc7112lx.dts b/scripts/dtc/include-prefixes/arm/moxart-uc7112lx.dts +deleted file mode 100644 +index eb5291b0ee3a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/moxart-uc7112lx.dts ++++ /dev/null +@@ -1,116 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* moxart-uc7112lx.dts - Device Tree file for MOXA UC-7112-LX +- * +- * Copyright (C) 2013 Jonas Jensen +- */ +- +-/dts-v1/; +-#include "moxart.dtsi" +- +-/ { +- model = "MOXA UC-7112-LX"; +- compatible = "moxa,moxart-uc-7112-lx", "moxa,moxart"; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x2000000>; +- }; +- +- clocks { +- ref12: ref12M { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <12000000>; +- }; +- }; +- +- flash@80000000,0 { +- compatible = "numonyx,js28f128", "cfi-flash"; +- reg = <0x80000000 0x1000000>; +- bank-width = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "bootloader"; +- reg = <0x0 0x40000>; +- }; +- partition@40000 { +- label = "linux kernel"; +- reg = <0x40000 0x1C0000>; +- }; +- partition@200000 { +- label = "root filesystem"; +- reg = <0x200000 0x800000>; +- }; +- partition@a00000 { +- label = "user filesystem"; +- reg = <0xa00000 0x600000>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- user-led { +- label = "ready-led"; +- gpios = <&gpio 27 0x1>; +- default-state = "on"; +- linux,default-trigger = "default-on"; +- }; +- }; +- +- gpio_keys_polled { +- compatible = "gpio-keys-polled"; +- #address-cells = <1>; +- #size-cells = <0>; +- poll-interval = <500>; +- button@25 { +- label = "GPIO Reset"; +- linux,code = <116>; +- gpios = <&gpio 25 1>; +- }; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p1 rw rootwait"; +- }; +-}; +- +-&clk_pll { +- clocks = <&ref12>; +-}; +- +-&sdhci { +- status = "okay"; +-}; +- +-&mdio0 { +- status = "okay"; +- +- ethphy0: ethernet-phy@1 { +- device_type = "ethernet-phy"; +- compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&mdio1 { +- status = "okay"; +- +- ethphy1: ethernet-phy@1 { +- device_type = "ethernet-phy"; +- compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&mac0 { +- status = "okay"; +-}; +- +-&mac1 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/moxart.dtsi b/scripts/dtc/include-prefixes/arm/moxart.dtsi +deleted file mode 100644 +index f5f070a87482..000000000000 +--- a/scripts/dtc/include-prefixes/arm/moxart.dtsi ++++ /dev/null +@@ -1,151 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* moxart.dtsi - Device Tree Include file for MOXA ART family SoC +- * +- * Copyright (C) 2013 Jonas Jensen +- */ +- +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "moxa,moxart"; +- model = "MOXART"; +- interrupt-parent = <&intc>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "faraday,fa526"; +- reg = <0>; +- }; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x90000000 0x10000000>; +- ranges; +- +- intc: interrupt-controller@98800000 { +- compatible = "moxa,moxart-ic", "faraday,ftintc010"; +- reg = <0x98800000 0x100>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupt-mask = <0x00080000>; +- }; +- +- clk_pll: clk_pll@98100000 { +- compatible = "moxa,moxart-pll-clock"; +- #clock-cells = <0>; +- reg = <0x98100000 0x34>; +- }; +- +- clk_apb: clk_apb@98100000 { +- compatible = "moxa,moxart-apb-clock"; +- #clock-cells = <0>; +- reg = <0x98100000 0x34>; +- clocks = <&clk_pll>; +- }; +- +- timer: timer@98400000 { +- compatible = "moxa,moxart-timer", "faraday,fttmr010"; +- reg = <0x98400000 0x42>; +- interrupts = <19 IRQ_TYPE_EDGE_FALLING>; +- clocks = <&clk_apb>; +- clock-names = "PCLK"; +- }; +- +- gpio: gpio@98700000 { +- gpio-controller; +- #gpio-cells = <2>; +- compatible = "moxa,moxart-gpio", "faraday,ftgpio010"; +- reg = <0x98700000 0x100>; +- }; +- +- rtc: rtc { +- compatible = "moxa,moxart-rtc"; +- gpio-rtc-sclk = <&gpio 5 0>; +- gpio-rtc-data = <&gpio 6 0>; +- gpio-rtc-reset = <&gpio 7 0>; +- }; +- +- dma: dma@90500000 { +- compatible = "moxa,moxart-dma"; +- reg = <0x90500080 0x40>; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; +- #dma-cells = <1>; +- }; +- +- watchdog: watchdog@98500000 { +- compatible = "moxa,moxart-watchdog", "faraday,ftwdt010"; +- reg = <0x98500000 0x10>; +- clocks = <&clk_apb>; +- clock-names = "PCLK"; +- }; +- +- sdhci: sdhci@98e00000 { +- compatible = "moxa,moxart-sdhci"; +- reg = <0x98e00000 0x5C>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk_apb>; +- dmas = <&dma 5>, +- <&dma 5>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- mdio0: mdio@90900090 { +- compatible = "moxa,moxart-mdio"; +- reg = <0x90900090 0x8>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- mdio1: mdio@92000090 { +- compatible = "moxa,moxart-mdio"; +- reg = <0x92000090 0x8>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- mac0: mac@90900000 { +- compatible = "moxa,moxart-mac"; +- reg = <0x90900000 0x90>; +- interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; +- phy-handle = <ðphy0>; +- phy-mode = "mii"; +- status = "disabled"; +- }; +- +- mac1: mac@92000000 { +- compatible = "moxa,moxart-mac"; +- reg = <0x92000000 0x90>; +- interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; +- phy-handle = <ðphy1>; +- phy-mode = "mii"; +- status = "disabled"; +- }; +- +- uart0: uart@98200000 { +- compatible = "ns16550a"; +- reg = <0x98200000 0x20>; +- interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <14745600>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mpa1600.dts b/scripts/dtc/include-prefixes/arm/mpa1600.dts +deleted file mode 100644 +index 005c2758e229..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mpa1600.dts ++++ /dev/null +@@ -1,79 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * mpa1600.dts - Device Tree file for Phontech MPA 1600 +- * +- * Copyright (C) 2013 Joachim Eastwood +- */ +-/dts-v1/; +-#include "at91rm9200.dtsi" +- +-/ { +- model = "Phontech MPA 1600"; +- compatible = "phontech,mpa1600", "atmel,at91rm9200"; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <18432000>; +- }; +- }; +- +- ahb { +- apb { +- dbgu: serial@fffff200 { +- status = "okay"; +- }; +- +- tcb0: timer@fffa0000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +- }; +- +- macb0: ethernet@fffbc000 { +- phy-mode = "rmii"; +- status = "okay"; +- }; +- +- ssc0: ssc@fffd0000 { +- status = "okay"; +- }; +- +- ssc1: ssc@fffd4000 { +- status = "okay"; +- }; +- }; +- +- usb0: ohci@300000 { +- num-ports = <1>; +- status = "okay"; +- }; +- }; +- +- i2c-gpio-0 { +- status = "okay"; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- monitor_mute { +- label = "Monitor mute"; +- gpios = <&pioC 1 GPIO_ACTIVE_LOW>; +- linux,code = <113>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mps2-an385.dts b/scripts/dtc/include-prefixes/arm/mps2-an385.dts +deleted file mode 100644 +index aebbebfc25d1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mps2-an385.dts ++++ /dev/null +@@ -1,92 +0,0 @@ +-/* +- * Copyright (C) 2015 ARM Limited +- * +- * Author: Vladimir Murzin +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include "mps2.dtsi" +- +-/ { +- model = "ARM MPS2 Application Note 385/386"; +- compatible = "arm,mps2"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "serial0:9600n8"; +- }; +- +- memory@21000000 { +- device_type = "memory"; +- reg = <0x21000000 0x1000000>; +- }; +- +- smb { +- ethernet@0,0 { +- compatible = "smsc,lan9220", "smsc,lan9115"; +- reg = <0 0x0 0x10000>; +- interrupts = <13>; +- interrupt-parent = <&nvic>; +- smsc,irq-active-high; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&timer0 { +- status = "okay"; +-}; +- +-&timer1 { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mps2-an399.dts b/scripts/dtc/include-prefixes/arm/mps2-an399.dts +deleted file mode 100644 +index 349abf70b2a5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mps2-an399.dts ++++ /dev/null +@@ -1,92 +0,0 @@ +-/* +- * Copyright (C) 2015 ARM Limited +- * +- * Author: Vladimir Murzin +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include "mps2.dtsi" +- +-/ { +- model = "ARM MPS2 Application Note 399/400"; +- compatible = "arm,mps2"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "serial0:9600n8"; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x1000000>; +- }; +- +- smb { +- ethernet@1,0 { +- compatible = "smsc,lan9220", "smsc,lan9115"; +- reg = <1 0x0 0x10000>; +- interrupts = <13>; +- interrupt-parent = <&nvic>; +- smsc,irq-active-high; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&timer0 { +- status = "okay"; +-}; +- +-&timer1 { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mps2.dtsi b/scripts/dtc/include-prefixes/arm/mps2.dtsi +deleted file mode 100644 +index 37f5023f529c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mps2.dtsi ++++ /dev/null +@@ -1,246 +0,0 @@ +-/* +- * Copyright (C) 2015 ARM Limited +- * +- * Author: Vladimir Murzin +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "armv7-m.dtsi" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- oscclk0: clk-osc0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- }; +- +- oscclk1: clk-osc1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +- +- oscclk2: clk-osc2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- cfgclk: clk-cfg { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <5000000>; +- }; +- +- spicfgclk: clk-spicfg { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <75000000>; +- }; +- +- sysclk: clk-sys { +- compatible = "fixed-factor-clock"; +- clocks = <&oscclk0>; +- #clock-cells = <0>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- audmclk: clk-audm { +- compatible = "fixed-factor-clock"; +- clocks = <&oscclk1>; +- #clock-cells = <0>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- audsclk: clk-auds { +- compatible = "fixed-factor-clock"; +- clocks = <&oscclk1>; +- #clock-cells = <0>; +- clock-div = <8>; +- clock-mult = <1>; +- }; +- +- spiclcd: clk-cpiclcd { +- compatible = "fixed-factor-clock"; +- clocks = <&oscclk0>; +- #clock-cells = <0>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- spicon: clk-spicon { +- compatible = "fixed-factor-clock"; +- clocks = <&oscclk0>; +- #clock-cells = <0>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- i2cclcd: clk-i2cclcd { +- compatible = "fixed-factor-clock"; +- clocks = <&oscclk0>; +- #clock-cells = <0>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- i2caud: clk-i2caud { +- compatible = "fixed-factor-clock"; +- clocks = <&oscclk0>; +- #clock-cells = <0>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- soc { +- compatible = "simple-bus"; +- ranges; +- +- apb@40000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x40000000 0x10000>; +- +- timer0: mps2-timer0@0 { +- compatible = "arm,mps2-timer"; +- reg = <0x0 0x1000>; +- interrupts = <8>; +- clocks = <&sysclk>; +- status = "disabled"; +- }; +- +- timer1: mps2-timer1@1000 { +- compatible = "arm,mps2-timer"; +- reg = <0x1000 0x1000>; +- interrupts = <9>; +- clocks = <&sysclk>; +- status = "disabled"; +- }; +- +- timer2: dual-timer@2000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x2000 0x1000>; +- clocks = <&sysclk>, <&sysclk>, <&sysclk>; +- clock-names = "timer0clk", "timer1clk", +- "apb_pclk"; +- interrupts = <10>; +- status = "disabled"; +- }; +- +- uart0: serial@4000 { +- compatible = "arm,mps2-uart"; +- reg = <0x4000 0x1000>; +- interrupts = <0>, <1>, <12>; +- clocks = <&sysclk>; +- status = "disabled"; +- }; +- +- uart1: serial@5000 { +- compatible = "arm,mps2-uart"; +- reg = <0x5000 0x1000>; +- interrupts = <2>, <3>, <12>; +- clocks = <&sysclk>; +- status = "disabled"; +- }; +- +- uart2: serial@6000 { +- compatible = "arm,mps2-uart"; +- reg = <0x6000 0x1000>; +- interrupts = <4>, <5>, <12>; +- clocks = <&sysclk>; +- status = "disabled"; +- }; +- +- wdt: watchdog@8000 { +- compatible = "arm,sp805", "arm,primecell"; +- arm,primecell-periphid = <0x00141805>; +- reg = <0x8000 0x1000>; +- interrupts = <0>; +- clocks = <&sysclk>, <&sysclk>; +- clock-names = "wdog_clk", "apb_pclk"; +- status = "disabled"; +- }; +- }; +- }; +- +- fpga@40020000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x40020000 0x10000>; +- +- fpgaio@8000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x8000 0x10>; +- +- led0 { +- compatible = "register-bit-led"; +- offset = <0x0>; +- mask = <0x01>; +- label = "userled:0"; +- linux,default-trigger = "heartbeat"; +- default-state = "on"; +- }; +- +- led1 { +- compatible = "register-bit-led"; +- offset = <0x0>; +- mask = <0x02>; +- label = "userled:1"; +- linux,default-trigger = "usr"; +- default-state = "off"; +- }; +- }; +- }; +- +- smb { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0 0x40200000 0x10000>, +- <1 0 0xa0000000 0x10000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mstar-infinity-breadbee-common.dtsi b/scripts/dtc/include-prefixes/arm/mstar-infinity-breadbee-common.dtsi +deleted file mode 100644 +index 507ff2fba837..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mstar-infinity-breadbee-common.dtsi ++++ /dev/null +@@ -1,49 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2020 thingy.jp. +- * Author: Daniel Palmer +- */ +- +-#include +- +-/ { +- vcc_core: fixedregulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_core"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-boot-on; +- }; +- +- vcc_dram: fixedregulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_dram"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- }; +- +- vcc_io: fixedregulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- +- leds { +- compatible = "gpio-leds"; +- red { +- gpios = <&gpio MSC313_GPIO_SR_IO16 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "activity"; +- }; +- yellow { +- gpios = <&gpio MSC313_GPIO_SR_IO17 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vcc_core>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mstar-infinity-msc313-breadbee_crust.dts b/scripts/dtc/include-prefixes/arm/mstar-infinity-msc313-breadbee_crust.dts +deleted file mode 100644 +index db4910dcb8a7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mstar-infinity-msc313-breadbee_crust.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019 thingy.jp. +- * Author: Daniel Palmer +- */ +- +-/dts-v1/; +-#include "mstar-infinity-msc313.dtsi" +-#include "mstar-infinity-breadbee-common.dtsi" +- +-/ { +- model = "BreadBee Crust"; +- compatible = "thingyjp,breadbee-crust", "mstar,infinity"; +- +- aliases { +- serial0 = &pm_uart; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&pm_uart { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mstar-infinity-msc313.dtsi b/scripts/dtc/include-prefixes/arm/mstar-infinity-msc313.dtsi +deleted file mode 100644 +index 3499fde263be..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mstar-infinity-msc313.dtsi ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (c) 2020 thingy.jp. +- * Author: Daniel Palmer +- */ +- +-#include "mstar-infinity.dtsi" +- +-/ { +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x4000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mstar-infinity.dtsi b/scripts/dtc/include-prefixes/arm/mstar-infinity.dtsi +deleted file mode 100644 +index 0bee517797f4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mstar-infinity.dtsi ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (c) 2020 thingy.jp. +- * Author: Daniel Palmer +- */ +- +-#include "mstar-v7.dtsi" +- +-#include +- +-&imi { +- reg = <0xa0000000 0x16000>; +-}; +- +-&gpio { +- compatible = "mstar,msc313-gpio"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mstar-infinity2m-ssd202d-ssd201htv2.dts b/scripts/dtc/include-prefixes/arm/mstar-infinity2m-ssd202d-ssd201htv2.dts +deleted file mode 100644 +index 5d81641414a2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mstar-infinity2m-ssd202d-ssd201htv2.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (c) 2020 thingy.jp. +- * Author: Daniel Palmer +- */ +- +-/dts-v1/; +-#include "mstar-infinity2m-ssd202d.dtsi" +- +-/ { +- model = "SSD201_HT_V2"; +- compatible = "honestar,ssd201htv2", "mstar,infinity2m"; +- +- aliases { +- serial0 = &pm_uart; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&pm_uart { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mstar-infinity2m-ssd202d-unitv2.dts b/scripts/dtc/include-prefixes/arm/mstar-infinity2m-ssd202d-unitv2.dts +deleted file mode 100644 +index a81684002e45..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mstar-infinity2m-ssd202d-unitv2.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (c) 2021 thingy.jp. +- * Author: Daniel Palmer +- */ +- +-/dts-v1/; +-#include "mstar-infinity2m-ssd202d.dtsi" +- +-/ { +- model = "UnitV2"; +- compatible = "m5stack,unitv2", "mstar,infinity2m"; +- +- aliases { +- serial0 = &pm_uart; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&pm_uart { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mstar-infinity2m-ssd202d.dtsi b/scripts/dtc/include-prefixes/arm/mstar-infinity2m-ssd202d.dtsi +deleted file mode 100644 +index 176e10a29896..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mstar-infinity2m-ssd202d.dtsi ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (c) 2020 thingy.jp. +- * Author: Daniel Palmer +- */ +- +-#include "mstar-infinity2m-ssd20xd.dtsi" +- +-/ { +- memory { +- device_type = "memory"; +- reg = <0x20000000 0x8000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mstar-infinity2m-ssd20xd.dtsi b/scripts/dtc/include-prefixes/arm/mstar-infinity2m-ssd20xd.dtsi +deleted file mode 100644 +index 7a5e28b33f96..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mstar-infinity2m-ssd20xd.dtsi ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (c) 2020 thingy.jp. +- * Author: Daniel Palmer +- */ +- +-#include "mstar-infinity2m.dtsi" +- +-&smpctrl { +- compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mstar-infinity2m.dtsi b/scripts/dtc/include-prefixes/arm/mstar-infinity2m.dtsi +deleted file mode 100644 +index 6d4d1d224e96..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mstar-infinity2m.dtsi ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (c) 2020 thingy.jp. +- * Author: Daniel Palmer +- */ +- +-#include "mstar-infinity.dtsi" +- +-&cpus { +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x1>; +- }; +-}; +- +-&riu { +- smpctrl: smpctrl@204000 { +- reg = <0x204000 0x200>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mstar-infinity3-msc313e-breadbee.dts b/scripts/dtc/include-prefixes/arm/mstar-infinity3-msc313e-breadbee.dts +deleted file mode 100644 +index e64ca4ce1830..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mstar-infinity3-msc313e-breadbee.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019 thingy.jp. +- * Author: Daniel Palmer +- */ +- +-/dts-v1/; +-#include "mstar-infinity3-msc313e.dtsi" +-#include "mstar-infinity-breadbee-common.dtsi" +- +-/ { +- model = "BreadBee"; +- compatible = "thingyjp,breadbee", "mstar,infinity3"; +- +- aliases { +- serial0 = &pm_uart; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&pm_uart { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mstar-infinity3-msc313e.dtsi b/scripts/dtc/include-prefixes/arm/mstar-infinity3-msc313e.dtsi +deleted file mode 100644 +index f581b6f89555..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mstar-infinity3-msc313e.dtsi ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (c) 2020 thingy.jp. +- * Author: Daniel Palmer +- */ +- +-#include "mstar-infinity3.dtsi" +- +-/ { +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x4000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mstar-infinity3.dtsi b/scripts/dtc/include-prefixes/arm/mstar-infinity3.dtsi +deleted file mode 100644 +index 9857e2a9934d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mstar-infinity3.dtsi ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (c) 2020 thingy.jp. +- * Author: Daniel Palmer +- */ +- +-#include "mstar-infinity.dtsi" +- +-&imi { +- reg = <0xa0000000 0x20000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mstar-mercury5-ssc8336n-midrived08.dts b/scripts/dtc/include-prefixes/arm/mstar-mercury5-ssc8336n-midrived08.dts +deleted file mode 100644 +index 7306b737d9c4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mstar-mercury5-ssc8336n-midrived08.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (c) 2020 thingy.jp. +- * Author: Daniel Palmer +- */ +- +-/dts-v1/; +-#include "mstar-mercury5-ssc8336n.dtsi" +- +-/ { +- model = "70mai Midrive D08"; +- compatible = "70mai,midrived08", "mstar,mercury5"; +- +- aliases { +- serial0 = &pm_uart; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&pm_uart { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mstar-mercury5-ssc8336n.dtsi b/scripts/dtc/include-prefixes/arm/mstar-mercury5-ssc8336n.dtsi +deleted file mode 100644 +index 3f5a4c029744..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mstar-mercury5-ssc8336n.dtsi ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (c) 2020 thingy.jp. +- * Author: Daniel Palmer +- */ +- +-#include "mstar-mercury5.dtsi" +- +-/ { +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x4000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mstar-mercury5.dtsi b/scripts/dtc/include-prefixes/arm/mstar-mercury5.dtsi +deleted file mode 100644 +index a7d0dd9d6132..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mstar-mercury5.dtsi ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (c) 2020 thingy.jp. +- * Author: Daniel Palmer +- */ +- +-#include "mstar-v7.dtsi" +- +-&imi { +- reg = <0xa0000000 0x20000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mstar-v7.dtsi b/scripts/dtc/include-prefixes/arm/mstar-v7.dtsi +deleted file mode 100644 +index 2273295e140f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mstar-v7.dtsi ++++ /dev/null +@@ -1,174 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (c) 2020 thingy.jp. +- * Author: Daniel Palmer +- */ +- +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&gic>; +- +- cpus: cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x0>; +- }; +- }; +- +- arch_timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- /* +- * we shouldn't need this but the vendor +- * u-boot is broken +- */ +- clock-frequency = <6000000>; +- }; +- +- pmu: pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupts = ; +- interrupt-affinity = <&cpu0>; +- }; +- +- clocks: clocks { +- xtal: xtal { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- rtc_xtal: rtc_xtal { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- status = "disabled"; +- }; +- +- xtal_div2: xtal_div2 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&xtal>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- }; +- +- soc: soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x16001000 0x16001000 0x00007000>, +- <0x1f000000 0x1f000000 0x00400000>, +- <0xa0000000 0xa0000000 0x20000>; +- +- gic: interrupt-controller@16001000 { +- compatible = "arm,cortex-a7-gic"; +- reg = <0x16001000 0x1000>, +- <0x16002000 0x2000>, +- <0x16004000 0x2000>, +- <0x16006000 0x2000>; +- #interrupt-cells = <3>; +- interrupt-controller; +- interrupts = ; +- }; +- +- riu: bus@1f000000 { +- compatible = "simple-bus"; +- reg = <0x1f000000 0x00400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1f000000 0x00400000>; +- +- pmsleep: syscon@1c00 { +- compatible = "mstar,msc313-pmsleep", "syscon"; +- reg = <0x1c00 0x100>; +- }; +- +- reboot { +- compatible = "syscon-reboot"; +- regmap = <&pmsleep>; +- offset = <0xb8>; +- mask = <0x79>; +- }; +- +- watchdog@6000 { +- compatible = "mstar,msc313e-wdt"; +- reg = <0x6000 0x1f>; +- clocks = <&xtal_div2>; +- }; +- +- intc_fiq: interrupt-controller@201310 { +- compatible = "mstar,mst-intc"; +- reg = <0x201310 0x40>; +- #interrupt-cells = <3>; +- interrupt-controller; +- interrupt-parent = <&gic>; +- mstar,irqs-map-range = <96 127>; +- }; +- +- intc_irq: interrupt-controller@201350 { +- compatible = "mstar,mst-intc"; +- reg = <0x201350 0x40>; +- #interrupt-cells = <3>; +- interrupt-controller; +- interrupt-parent = <&gic>; +- mstar,irqs-map-range = <32 95>; +- mstar,intc-no-eoi; +- }; +- +- l3bridge: l3bridge@204400 { +- compatible = "mstar,l3bridge"; +- reg = <0x204400 0x200>; +- }; +- +- mpll: mpll@206000 { +- compatible = "mstar,msc313-mpll"; +- #clock-cells = <1>; +- reg = <0x206000 0x200>; +- clocks = <&xtal>; +- }; +- +- gpio: gpio@207800 { +- #gpio-cells = <2>; +- reg = <0x207800 0x200>; +- gpio-controller; +- #interrupt-cells = <2>; +- interrupt-controller; +- interrupt-parent = <&intc_fiq>; +- status = "disabled"; +- }; +- +- pm_uart: uart@221000 { +- compatible = "ns16550a"; +- reg = <0x221000 0x100>; +- reg-shift = <3>; +- interrupts-extended = <&intc_irq GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; +- clock-frequency = <172000000>; +- status = "disabled"; +- }; +- }; +- +- imi: sram@a0000000 { +- compatible = "mmio-sram"; +- reg = <0xa0000000 0x10000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt2701-evb.dts b/scripts/dtc/include-prefixes/arm/mt2701-evb.dts +deleted file mode 100644 +index d1535f385f36..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt2701-evb.dts ++++ /dev/null +@@ -1,253 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2015 MediaTek Inc. +- * Author: Erin Lo +- * +- */ +- +-/dts-v1/; +-#include +-#include "mt2701.dtsi" +- +-/ { +- model = "MediaTek MT2701 evaluation board"; +- compatible = "mediatek,mt2701-evb", "mediatek,mt2701"; +- +- memory { +- device_type = "memory"; +- reg = <0 0x80000000 0 0x40000000>; +- }; +- +- sound:sound { +- compatible = "mediatek,mt2701-cs42448-machine"; +- mediatek,platform = <&afe>; +- /* CS42448 Machine name */ +- audio-routing = +- "Line Out Jack", "AOUT1L", +- "Line Out Jack", "AOUT1R", +- "Line Out Jack", "AOUT2L", +- "Line Out Jack", "AOUT2R", +- "Line Out Jack", "AOUT3L", +- "Line Out Jack", "AOUT3R", +- "Line Out Jack", "AOUT4L", +- "Line Out Jack", "AOUT4R", +- "AIN1L", "AMIC", +- "AIN1R", "AMIC", +- "AIN2L", "Tuner In", +- "AIN2R", "Tuner In", +- "AIN3L", "Satellite Tuner In", +- "AIN3R", "Satellite Tuner In", +- "AIN3L", "AUX In", +- "AIN3R", "AUX In"; +- mediatek,audio-codec = <&cs42448>; +- mediatek,audio-codec-bt-mrg = <&bt_sco_codec>; +- pinctrl-names = "default"; +- pinctrl-0 = <&aud_pins_default>; +- i2s1-in-sel-gpio1 = <&pio 53 0>; +- i2s1-in-sel-gpio2 = <&pio 54 0>; +- status = "okay"; +- }; +- +- bt_sco_codec:bt_sco_codec { +- compatible = "linux,bt-sco"; +- }; +- +- backlight_lcd: backlight_lcd { +- compatible = "pwm-backlight"; +- pwms = <&bls 0 100000>; +- brightness-levels = < +- 0 16 32 48 64 80 96 112 +- 128 144 160 176 192 208 224 240 +- 255 +- >; +- default-brightness-level = <9>; +- }; +- +- usb_vbus: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "usb_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&pio 45 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&auxadc { +- status = "okay"; +-}; +- +-&bls { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm_bls_gpio>; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_a>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins_a>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins_a>; +- status = "okay"; +- cs42448: cs42448@48 { +- compatible = "cirrus,cs42448"; +- reg = <0x48>; +- clocks = <&topckgen CLK_TOP_AUD_I2S1_MCLK>; +- clock-names = "mclk"; +- }; +-}; +- +-&pio { +- i2c0_pins_a: i2c0@0 { +- pins1 { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- i2c1_pins_a: i2c1@0 { +- pins1 { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- i2c2_pins_a: i2c2@0 { +- pins1 { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- pwm_bls_gpio: pwm_bls_gpio { +- pins_cmd_dat { +- pinmux = ; +- }; +- }; +- +- spi_pins_a: spi0@0 { +- pins_spi { +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- }; +- +- aud_pins_default: audiodefault { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- drive-strength = ; +- bias-pull-down; +- }; +- }; +- +- spi_pins_b: spi1@0 { +- pins_spi { +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- }; +- +- spi_pins_c: spi2@0 { +- pins_spi { +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- }; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_pins_a>; +- status = "disabled"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_pins_b>; +- status = "disabled"; +-}; +- +-&spi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_pins_c>; +- status = "disabled"; +-}; +- +-&nor_flash { +- pinctrl-names = "default"; +- pinctrl-0 = <&nor_pins_default>; +- status = "okay"; +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- }; +-}; +- +-&pio { +- nor_pins_default: nor { +- pins1 { +- pinmux = , +- , +- , +- , +- , +- ; +- drive-strength = ; +- bias-pull-up; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&usb2 { +- status = "okay"; +- usb-role-switch; +- connector{ +- compatible = "gpio-usb-b-connector", "usb-b-connector"; +- type = "micro"; +- id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>; +- vbus-supply = <&usb_vbus>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt2701-pinfunc.h b/scripts/dtc/include-prefixes/arm/mt2701-pinfunc.h +deleted file mode 100644 +index 136a25a0ae28..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt2701-pinfunc.h ++++ /dev/null +@@ -1,727 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2015 MediaTek Inc. +- * Author: Biao Huang +- */ +- +-#ifndef __DTS_MT2701_PINFUNC_H +-#define __DTS_MT2701_PINFUNC_H +- +-#include +- +-#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +-#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1) +-#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2) +- +-#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +-#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1) +-#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2) +- +-#define MT2701_PIN_2_PWRAP_INT__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +-#define MT2701_PIN_2_PWRAP_INT__FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1) +- +-#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +-#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1) +- +-#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +-#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1) +- +-#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +-#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1) +-#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 5) +- +-#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +-#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1) +-#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 5) +-#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_DBG_MON_A_0 (MTK_PIN_NO(6) | 7) +- +-#define MT2701_PIN_7_SPI1_CSN__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +-#define MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS (MTK_PIN_NO(7) | 1) +-#define MT2701_PIN_7_SPI1_CSN__FUNC_KCOL0 (MTK_PIN_NO(7) | 4) +-#define MT2701_PIN_7_SPI1_CSN__FUNC_DBG_MON_B_12 (MTK_PIN_NO(7) | 7) +- +-#define MT2701_PIN_8_SPI1_MI__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +-#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI (MTK_PIN_NO(8) | 1) +-#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MO (MTK_PIN_NO(8) | 2) +-#define MT2701_PIN_8_SPI1_MI__FUNC_KCOL1 (MTK_PIN_NO(8) | 4) +-#define MT2701_PIN_8_SPI1_MI__FUNC_DBG_MON_B_13 (MTK_PIN_NO(8) | 7) +- +-#define MT2701_PIN_9_SPI1_MO__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +-#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO (MTK_PIN_NO(9) | 1) +-#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MI (MTK_PIN_NO(9) | 2) +-#define MT2701_PIN_9_SPI1_MO__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3) +-#define MT2701_PIN_9_SPI1_MO__FUNC_KCOL2 (MTK_PIN_NO(9) | 4) +-#define MT2701_PIN_9_SPI1_MO__FUNC_DBG_MON_B_14 (MTK_PIN_NO(9) | 7) +- +-#define MT2701_PIN_10_RTC32K_CK__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +-#define MT2701_PIN_10_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1) +- +-#define MT2701_PIN_11_WATCHDOG__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +-#define MT2701_PIN_11_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(11) | 1) +- +-#define MT2701_PIN_12_SRCLKENA__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +-#define MT2701_PIN_12_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(12) | 1) +- +-#define MT2701_PIN_13_SRCLKENAI__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +-#define MT2701_PIN_13_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1) +- +-#define MT2701_PIN_14_URXD2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +-#define MT2701_PIN_14_URXD2__FUNC_URXD2 (MTK_PIN_NO(14) | 1) +-#define MT2701_PIN_14_URXD2__FUNC_UTXD2 (MTK_PIN_NO(14) | 2) +-#define MT2701_PIN_14_URXD2__FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5) +-#define MT2701_PIN_14_URXD2__FUNC_DBG_MON_B_30 (MTK_PIN_NO(14) | 7) +- +-#define MT2701_PIN_15_UTXD2__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +-#define MT2701_PIN_15_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(15) | 1) +-#define MT2701_PIN_15_UTXD2__FUNC_URXD2 (MTK_PIN_NO(15) | 2) +-#define MT2701_PIN_15_UTXD2__FUNC_DBG_MON_B_31 (MTK_PIN_NO(15) | 7) +- +-#define MT2701_PIN_18_PCM_CLK__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +-#define MT2701_PIN_18_PCM_CLK__FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1) +-#define MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK (MTK_PIN_NO(18) | 2) +-#define MT2701_PIN_18_PCM_CLK__FUNC_MM_TEST_CK (MTK_PIN_NO(18) | 4) +-#define MT2701_PIN_18_PCM_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5) +-#define MT2701_PIN_18_PCM_CLK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(18) | 6) +-#define MT2701_PIN_18_PCM_CLK__FUNC_DBG_MON_A_3 (MTK_PIN_NO(18) | 7) +- +-#define MT2701_PIN_19_PCM_SYNC__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +-#define MT2701_PIN_19_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1) +-#define MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(19) | 2) +-#define MT2701_PIN_19_PCM_SYNC__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5) +-#define MT2701_PIN_19_PCM_SYNC__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(19) | 6) +-#define MT2701_PIN_19_PCM_SYNC__FUNC_DBG_MON_A_5 (MTK_PIN_NO(19) | 7) +- +-#define MT2701_PIN_20_PCM_RX__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +-#define MT2701_PIN_20_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(20) | 1) +-#define MT2701_PIN_20_PCM_RX__FUNC_MRG_RX (MTK_PIN_NO(20) | 2) +-#define MT2701_PIN_20_PCM_RX__FUNC_MRG_TX (MTK_PIN_NO(20) | 3) +-#define MT2701_PIN_20_PCM_RX__FUNC_PCM_TX (MTK_PIN_NO(20) | 4) +-#define MT2701_PIN_20_PCM_RX__FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5) +-#define MT2701_PIN_20_PCM_RX__FUNC_WCN_PCM_RX (MTK_PIN_NO(20) | 6) +-#define MT2701_PIN_20_PCM_RX__FUNC_DBG_MON_A_4 (MTK_PIN_NO(20) | 7) +- +-#define MT2701_PIN_21_PCM_TX__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +-#define MT2701_PIN_21_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(21) | 1) +-#define MT2701_PIN_21_PCM_TX__FUNC_MRG_TX (MTK_PIN_NO(21) | 2) +-#define MT2701_PIN_21_PCM_TX__FUNC_MRG_RX (MTK_PIN_NO(21) | 3) +-#define MT2701_PIN_21_PCM_TX__FUNC_PCM_RX (MTK_PIN_NO(21) | 4) +-#define MT2701_PIN_21_PCM_TX__FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5) +-#define MT2701_PIN_21_PCM_TX__FUNC_WCN_PCM_TX (MTK_PIN_NO(21) | 6) +-#define MT2701_PIN_21_PCM_TX__FUNC_DBG_MON_A_2 (MTK_PIN_NO(21) | 7) +- +-#define MT2701_PIN_22_EINT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +-#define MT2701_PIN_22_EINT0__FUNC_UCTS0 (MTK_PIN_NO(22) | 1) +-#define MT2701_PIN_22_EINT0__FUNC_KCOL3 (MTK_PIN_NO(22) | 3) +-#define MT2701_PIN_22_EINT0__FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 4) +-#define MT2701_PIN_22_EINT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 5) +-#define MT2701_PIN_22_EINT0__FUNC_DBG_MON_A_30 (MTK_PIN_NO(22) | 7) +-#define MT2701_PIN_22_EINT0__FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 10) +- +-#define MT2701_PIN_23_EINT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +-#define MT2701_PIN_23_EINT1__FUNC_URTS0 (MTK_PIN_NO(23) | 1) +-#define MT2701_PIN_23_EINT1__FUNC_KCOL2 (MTK_PIN_NO(23) | 3) +-#define MT2701_PIN_23_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 4) +-#define MT2701_PIN_23_EINT1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5) +-#define MT2701_PIN_23_EINT1__FUNC_DBG_MON_A_29 (MTK_PIN_NO(23) | 7) +-#define MT2701_PIN_23_EINT1__FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 10) +- +-#define MT2701_PIN_24_EINT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +-#define MT2701_PIN_24_EINT2__FUNC_UCTS1 (MTK_PIN_NO(24) | 1) +-#define MT2701_PIN_24_EINT2__FUNC_KCOL1 (MTK_PIN_NO(24) | 3) +-#define MT2701_PIN_24_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 4) +-#define MT2701_PIN_24_EINT2__FUNC_DBG_MON_A_28 (MTK_PIN_NO(24) | 7) +-#define MT2701_PIN_24_EINT2__FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 10) +- +-#define MT2701_PIN_25_EINT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +-#define MT2701_PIN_25_EINT3__FUNC_URTS1 (MTK_PIN_NO(25) | 1) +-#define MT2701_PIN_25_EINT3__FUNC_KCOL0 (MTK_PIN_NO(25) | 3) +-#define MT2701_PIN_25_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 4) +-#define MT2701_PIN_25_EINT3__FUNC_DBG_MON_A_27 (MTK_PIN_NO(25) | 7) +- +-#define MT2701_PIN_26_EINT4__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +-#define MT2701_PIN_26_EINT4__FUNC_UCTS3 (MTK_PIN_NO(26) | 1) +-#define MT2701_PIN_26_EINT4__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(26) | 2) +-#define MT2701_PIN_26_EINT4__FUNC_KROW3 (MTK_PIN_NO(26) | 3) +-#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 4) +-#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 5) +-#define MT2701_PIN_26_EINT4__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6) +-#define MT2701_PIN_26_EINT4__FUNC_DBG_MON_A_26 (MTK_PIN_NO(26) | 7) +- +-#define MT2701_PIN_27_EINT5__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +-#define MT2701_PIN_27_EINT5__FUNC_URTS3 (MTK_PIN_NO(27) | 1) +-#define MT2701_PIN_27_EINT5__FUNC_IDDIG_P1 (MTK_PIN_NO(27) | 2) +-#define MT2701_PIN_27_EINT5__FUNC_KROW2 (MTK_PIN_NO(27) | 3) +-#define MT2701_PIN_27_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 4) +-#define MT2701_PIN_27_EINT5__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6) +-#define MT2701_PIN_27_EINT5__FUNC_DBG_MON_A_25 (MTK_PIN_NO(27) | 7) +- +-#define MT2701_PIN_28_EINT6__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +-#define MT2701_PIN_28_EINT6__FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1) +-#define MT2701_PIN_28_EINT6__FUNC_KROW1 (MTK_PIN_NO(28) | 3) +-#define MT2701_PIN_28_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 4) +-#define MT2701_PIN_28_EINT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6) +-#define MT2701_PIN_28_EINT6__FUNC_DBG_MON_A_24 (MTK_PIN_NO(28) | 7) +- +-#define MT2701_PIN_29_EINT7__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +-#define MT2701_PIN_29_EINT7__FUNC_IDDIG (MTK_PIN_NO(29) | 1) +-#define MT2701_PIN_29_EINT7__FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2) +-#define MT2701_PIN_29_EINT7__FUNC_KROW0 (MTK_PIN_NO(29) | 3) +-#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 4) +-#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 5) +-#define MT2701_PIN_29_EINT7__FUNC_DBG_MON_A_23 (MTK_PIN_NO(29) | 7) +-#define MT2701_PIN_29_EINT7__FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 14) +- +-#define MT2701_PIN_33_I2S1_DATA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +-#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1) +-#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA_BYPS (MTK_PIN_NO(33) | 2) +-#define MT2701_PIN_33_I2S1_DATA__FUNC_PCM_TX (MTK_PIN_NO(33) | 3) +-#define MT2701_PIN_33_I2S1_DATA__FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4) +-#define MT2701_PIN_33_I2S1_DATA__FUNC_G1_RXD0 (MTK_PIN_NO(33) | 5) +-#define MT2701_PIN_33_I2S1_DATA__FUNC_WCN_PCM_TX (MTK_PIN_NO(33) | 6) +-#define MT2701_PIN_33_I2S1_DATA__FUNC_DBG_MON_B_8 (MTK_PIN_NO(33) | 7) +- +-#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +-#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1) +-#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(34) | 3) +-#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_VDEC_TEST_CK (MTK_PIN_NO(34) | 4) +-#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_G1_RXD1 (MTK_PIN_NO(34) | 5) +-#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_WCN_PCM_RX (MTK_PIN_NO(34) | 6) +-#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_DBG_MON_B_7 (MTK_PIN_NO(34) | 7) +- +-#define MT2701_PIN_35_I2S1_BCK__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +-#define MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1) +-#define MT2701_PIN_35_I2S1_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3) +-#define MT2701_PIN_35_I2S1_BCK__FUNC_G1_RXD2 (MTK_PIN_NO(35) | 5) +-#define MT2701_PIN_35_I2S1_BCK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(35) | 6) +-#define MT2701_PIN_35_I2S1_BCK__FUNC_DBG_MON_B_9 (MTK_PIN_NO(35) | 7) +- +-#define MT2701_PIN_36_I2S1_LRCK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +-#define MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1) +-#define MT2701_PIN_36_I2S1_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3) +-#define MT2701_PIN_36_I2S1_LRCK__FUNC_G1_RXD3 (MTK_PIN_NO(36) | 5) +-#define MT2701_PIN_36_I2S1_LRCK__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(36) | 6) +-#define MT2701_PIN_36_I2S1_LRCK__FUNC_DBG_MON_B_10 (MTK_PIN_NO(36) | 7) +- +-#define MT2701_PIN_37_I2S1_MCLK__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +-#define MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1) +-#define MT2701_PIN_37_I2S1_MCLK__FUNC_G1_RXDV (MTK_PIN_NO(37) | 5) +-#define MT2701_PIN_37_I2S1_MCLK__FUNC_DBG_MON_B_11 (MTK_PIN_NO(37) | 7) +- +-#define MT2701_PIN_39_JTMS__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +-#define MT2701_PIN_39_JTMS__FUNC_JTMS (MTK_PIN_NO(39) | 1) +-#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2) +-#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3) +-#define MT2701_PIN_39_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 4) +- +-#define MT2701_PIN_40_JTCK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +-#define MT2701_PIN_40_JTCK__FUNC_JTCK (MTK_PIN_NO(40) | 1) +-#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2) +-#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3) +-#define MT2701_PIN_40_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 4) +- +-#define MT2701_PIN_41_JTDI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +-#define MT2701_PIN_41_JTDI__FUNC_JTDI (MTK_PIN_NO(41) | 1) +-#define MT2701_PIN_41_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2) +-#define MT2701_PIN_41_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 4) +- +-#define MT2701_PIN_42_JTDO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +-#define MT2701_PIN_42_JTDO__FUNC_JTDO (MTK_PIN_NO(42) | 1) +-#define MT2701_PIN_42_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2) +-#define MT2701_PIN_42_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(42) | 4) +- +-#define MT2701_PIN_43_NCLE__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +-#define MT2701_PIN_43_NCLE__FUNC_NCLE (MTK_PIN_NO(43) | 1) +-#define MT2701_PIN_43_NCLE__FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2) +- +-#define MT2701_PIN_44_NCEB1__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +-#define MT2701_PIN_44_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(44) | 1) +-#define MT2701_PIN_44_NCEB1__FUNC_IDDIG (MTK_PIN_NO(44) | 2) +- +-#define MT2701_PIN_45_NCEB0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +-#define MT2701_PIN_45_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(45) | 1) +-#define MT2701_PIN_45_NCEB0__FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2) +- +-#define MT2701_PIN_46_IR__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +-#define MT2701_PIN_46_IR__FUNC_IR (MTK_PIN_NO(46) | 1) +- +-#define MT2701_PIN_47_NREB__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +-#define MT2701_PIN_47_NREB__FUNC_NREB (MTK_PIN_NO(47) | 1) +-#define MT2701_PIN_47_NREB__FUNC_IDDIG_P1 (MTK_PIN_NO(47) | 2) +- +-#define MT2701_PIN_48_NRNB__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +-#define MT2701_PIN_48_NRNB__FUNC_NRNB (MTK_PIN_NO(48) | 1) +-#define MT2701_PIN_48_NRNB__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(48) | 2) +- +-#define MT2701_PIN_49_I2S0_DATA__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +-#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1) +-#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA_BYPS (MTK_PIN_NO(49) | 2) +-#define MT2701_PIN_49_I2S0_DATA__FUNC_PCM_TX (MTK_PIN_NO(49) | 3) +-#define MT2701_PIN_49_I2S0_DATA__FUNC_WCN_I2S_DO (MTK_PIN_NO(49) | 6) +-#define MT2701_PIN_49_I2S0_DATA__FUNC_DBG_MON_B_3 (MTK_PIN_NO(49) | 7) +- +-#define MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +-#define MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS (MTK_PIN_NO(53) | 1) +-#define MT2701_PIN_53_SPI0_CSN__FUNC_SPDIF (MTK_PIN_NO(53) | 3) +-#define MT2701_PIN_53_SPI0_CSN__FUNC_ADC_CK (MTK_PIN_NO(53) | 4) +-#define MT2701_PIN_53_SPI0_CSN__FUNC_PWM1 (MTK_PIN_NO(53) | 5) +-#define MT2701_PIN_53_SPI0_CSN__FUNC_DBG_MON_A_7 (MTK_PIN_NO(53) | 7) +- +-#define MT2701_PIN_54_SPI0_CK__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +-#define MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK (MTK_PIN_NO(54) | 1) +-#define MT2701_PIN_54_SPI0_CK__FUNC_SPDIF_IN1 (MTK_PIN_NO(54) | 3) +-#define MT2701_PIN_54_SPI0_CK__FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4) +-#define MT2701_PIN_54_SPI0_CK__FUNC_DBG_MON_A_10 (MTK_PIN_NO(54) | 7) +- +-#define MT2701_PIN_55_SPI0_MI__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +-#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI (MTK_PIN_NO(55) | 1) +-#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MO (MTK_PIN_NO(55) | 2) +-#define MT2701_PIN_55_SPI0_MI__FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3) +-#define MT2701_PIN_55_SPI0_MI__FUNC_ADC_WS (MTK_PIN_NO(55) | 4) +-#define MT2701_PIN_55_SPI0_MI__FUNC_PWM2 (MTK_PIN_NO(55) | 5) +-#define MT2701_PIN_55_SPI0_MI__FUNC_DBG_MON_A_8 (MTK_PIN_NO(55) | 7) +- +-#define MT2701_PIN_56_SPI0_MO__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +-#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO (MTK_PIN_NO(56) | 1) +-#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MI (MTK_PIN_NO(56) | 2) +-#define MT2701_PIN_56_SPI0_MO__FUNC_SPDIF_IN0 (MTK_PIN_NO(56) | 3) +-#define MT2701_PIN_56_SPI0_MO__FUNC_DBG_MON_A_9 (MTK_PIN_NO(56) | 7) +- +-#define MT2701_PIN_57_SDA1__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +-#define MT2701_PIN_57_SDA1__FUNC_SDA1 (MTK_PIN_NO(57) | 1) +- +-#define MT2701_PIN_58_SCL1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +-#define MT2701_PIN_58_SCL1__FUNC_SCL1 (MTK_PIN_NO(58) | 1) +- +-#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +-#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1) +-#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(72) | 3) +-#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PWM0 (MTK_PIN_NO(72) | 4) +-#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DISP_PWM (MTK_PIN_NO(72) | 5) +-#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_WCN_I2S_DI (MTK_PIN_NO(72) | 6) +-#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DBG_MON_B_2 (MTK_PIN_NO(72) | 7) +- +-#define MT2701_PIN_73_I2S0_LRCK__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +-#define MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1) +-#define MT2701_PIN_73_I2S0_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3) +-#define MT2701_PIN_73_I2S0_LRCK__FUNC_WCN_I2S_LRCK (MTK_PIN_NO(73) | 6) +-#define MT2701_PIN_73_I2S0_LRCK__FUNC_DBG_MON_B_5 (MTK_PIN_NO(73) | 7) +- +-#define MT2701_PIN_74_I2S0_BCK__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +-#define MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1) +-#define MT2701_PIN_74_I2S0_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3) +-#define MT2701_PIN_74_I2S0_BCK__FUNC_WCN_I2S_BCK (MTK_PIN_NO(74) | 6) +-#define MT2701_PIN_74_I2S0_BCK__FUNC_DBG_MON_B_4 (MTK_PIN_NO(74) | 7) +- +-#define MT2701_PIN_75_SDA0__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +-#define MT2701_PIN_75_SDA0__FUNC_SDA0 (MTK_PIN_NO(75) | 1) +- +-#define MT2701_PIN_76_SCL0__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +-#define MT2701_PIN_76_SCL0__FUNC_SCL0 (MTK_PIN_NO(76) | 1) +- +-#define MT2701_PIN_77_SDA2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +-#define MT2701_PIN_77_SDA2__FUNC_SDA2 (MTK_PIN_NO(77) | 1) +- +-#define MT2701_PIN_78_SCL2__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +-#define MT2701_PIN_78_SCL2__FUNC_SCL2 (MTK_PIN_NO(78) | 1) +- +-#define MT2701_PIN_79_URXD0__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +-#define MT2701_PIN_79_URXD0__FUNC_URXD0 (MTK_PIN_NO(79) | 1) +-#define MT2701_PIN_79_URXD0__FUNC_UTXD0 (MTK_PIN_NO(79) | 2) +-#define MT2701_PIN_79_URXD0__FUNC_ (MTK_PIN_NO(79) | 5) +- +-#define MT2701_PIN_80_UTXD0__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +-#define MT2701_PIN_80_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(80) | 1) +-#define MT2701_PIN_80_UTXD0__FUNC_URXD0 (MTK_PIN_NO(80) | 2) +- +-#define MT2701_PIN_81_URXD1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +-#define MT2701_PIN_81_URXD1__FUNC_URXD1 (MTK_PIN_NO(81) | 1) +-#define MT2701_PIN_81_URXD1__FUNC_UTXD1 (MTK_PIN_NO(81) | 2) +- +-#define MT2701_PIN_82_UTXD1__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +-#define MT2701_PIN_82_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(82) | 1) +-#define MT2701_PIN_82_UTXD1__FUNC_URXD1 (MTK_PIN_NO(82) | 2) +- +-#define MT2701_PIN_83_LCM_RST__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +-#define MT2701_PIN_83_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(83) | 1) +-#define MT2701_PIN_83_LCM_RST__FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2) +-#define MT2701_PIN_83_LCM_RST__FUNC_DBG_MON_B_1 (MTK_PIN_NO(83) | 7) +- +-#define MT2701_PIN_84_DSI_TE__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +-#define MT2701_PIN_84_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(84) | 1) +-#define MT2701_PIN_84_DSI_TE__FUNC_DBG_MON_B_0 (MTK_PIN_NO(84) | 7) +- +-#define MT2701_PIN_91_TDN3__FUNC_GPI91 (MTK_PIN_NO(91) | 0) +-#define MT2701_PIN_91_TDN3__FUNC_TDN3 (MTK_PIN_NO(91) | 1) +- +-#define MT2701_PIN_92_TDP3__FUNC_GPI92 (MTK_PIN_NO(92) | 0) +-#define MT2701_PIN_92_TDP3__FUNC_TDP3 (MTK_PIN_NO(92) | 1) +- +-#define MT2701_PIN_93_TDN2__FUNC_GPI93 (MTK_PIN_NO(93) | 0) +-#define MT2701_PIN_93_TDN2__FUNC_TDN2 (MTK_PIN_NO(93) | 1) +- +-#define MT2701_PIN_94_TDP2__FUNC_GPI94 (MTK_PIN_NO(94) | 0) +-#define MT2701_PIN_94_TDP2__FUNC_TDP2 (MTK_PIN_NO(94) | 1) +- +-#define MT2701_PIN_95_TCN__FUNC_GPI95 (MTK_PIN_NO(95) | 0) +-#define MT2701_PIN_95_TCN__FUNC_TCN (MTK_PIN_NO(95) | 1) +- +-#define MT2701_PIN_96_TCP__FUNC_GPI96 (MTK_PIN_NO(96) | 0) +-#define MT2701_PIN_96_TCP__FUNC_TCP (MTK_PIN_NO(96) | 1) +- +-#define MT2701_PIN_97_TDN1__FUNC_GPI97 (MTK_PIN_NO(97) | 0) +-#define MT2701_PIN_97_TDN1__FUNC_TDN1 (MTK_PIN_NO(97) | 1) +- +-#define MT2701_PIN_98_TDP1__FUNC_GPI98 (MTK_PIN_NO(98) | 0) +-#define MT2701_PIN_98_TDP1__FUNC_TDP1 (MTK_PIN_NO(98) | 1) +- +-#define MT2701_PIN_99_TDN0__FUNC_GPI99 (MTK_PIN_NO(99) | 0) +-#define MT2701_PIN_99_TDN0__FUNC_TDN0 (MTK_PIN_NO(99) | 1) +- +-#define MT2701_PIN_100_TDP0__FUNC_GPI100 (MTK_PIN_NO(100) | 0) +-#define MT2701_PIN_100_TDP0__FUNC_TDP0 (MTK_PIN_NO(100) | 1) +- +-#define MT2701_PIN_101_SPI2_CSN__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +-#define MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS (MTK_PIN_NO(101) | 1) +-#define MT2701_PIN_101_SPI2_CSN__FUNC_SCL3 (MTK_PIN_NO(101) | 3) +-#define MT2701_PIN_101_SPI2_CSN__FUNC_KROW0 (MTK_PIN_NO(101) | 4) +- +-#define MT2701_PIN_102_SPI2_MI__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +-#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI (MTK_PIN_NO(102) | 1) +-#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MO (MTK_PIN_NO(102) | 2) +-#define MT2701_PIN_102_SPI2_MI__FUNC_SDA3 (MTK_PIN_NO(102) | 3) +-#define MT2701_PIN_102_SPI2_MI__FUNC_KROW1 (MTK_PIN_NO(102) | 4) +- +-#define MT2701_PIN_103_SPI2_MO__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +-#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO (MTK_PIN_NO(103) | 1) +-#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MI (MTK_PIN_NO(103) | 2) +-#define MT2701_PIN_103_SPI2_MO__FUNC_SCL3 (MTK_PIN_NO(103) | 3) +-#define MT2701_PIN_103_SPI2_MO__FUNC_KROW2 (MTK_PIN_NO(103) | 4) +- +-#define MT2701_PIN_104_SPI2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +-#define MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK (MTK_PIN_NO(104) | 1) +-#define MT2701_PIN_104_SPI2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 3) +-#define MT2701_PIN_104_SPI2_CLK__FUNC_KROW3 (MTK_PIN_NO(104) | 4) +- +-#define MT2701_PIN_105_MSDC1_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +-#define MT2701_PIN_105_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1) +-#define MT2701_PIN_105_MSDC1_CMD__FUNC_ANT_SEL0 (MTK_PIN_NO(105) | 2) +-#define MT2701_PIN_105_MSDC1_CMD__FUNC_SDA1 (MTK_PIN_NO(105) | 3) +-#define MT2701_PIN_105_MSDC1_CMD__FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6) +-#define MT2701_PIN_105_MSDC1_CMD__FUNC_DBG_MON_B_27 (MTK_PIN_NO(105) | 7) +- +-#define MT2701_PIN_106_MSDC1_CLK__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +-#define MT2701_PIN_106_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1) +-#define MT2701_PIN_106_MSDC1_CLK__FUNC_ANT_SEL1 (MTK_PIN_NO(106) | 2) +-#define MT2701_PIN_106_MSDC1_CLK__FUNC_SCL1 (MTK_PIN_NO(106) | 3) +-#define MT2701_PIN_106_MSDC1_CLK__FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6) +-#define MT2701_PIN_106_MSDC1_CLK__FUNC_DBG_MON_B_28 (MTK_PIN_NO(106) | 7) +- +-#define MT2701_PIN_107_MSDC1_DAT0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +-#define MT2701_PIN_107_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1) +-#define MT2701_PIN_107_MSDC1_DAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(107) | 2) +-#define MT2701_PIN_107_MSDC1_DAT0__FUNC_UTXD0 (MTK_PIN_NO(107) | 5) +-#define MT2701_PIN_107_MSDC1_DAT0__FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6) +-#define MT2701_PIN_107_MSDC1_DAT0__FUNC_DBG_MON_B_26 (MTK_PIN_NO(107) | 7) +- +-#define MT2701_PIN_108_MSDC1_DAT1__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +-#define MT2701_PIN_108_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1) +-#define MT2701_PIN_108_MSDC1_DAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(108) | 2) +-#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM0 (MTK_PIN_NO(108) | 3) +-#define MT2701_PIN_108_MSDC1_DAT1__FUNC_URXD0 (MTK_PIN_NO(108) | 5) +-#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM1 (MTK_PIN_NO(108) | 6) +-#define MT2701_PIN_108_MSDC1_DAT1__FUNC_DBG_MON_B_25 (MTK_PIN_NO(108) | 7) +- +-#define MT2701_PIN_109_MSDC1_DAT2__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +-#define MT2701_PIN_109_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1) +-#define MT2701_PIN_109_MSDC1_DAT2__FUNC_ANT_SEL4 (MTK_PIN_NO(109) | 2) +-#define MT2701_PIN_109_MSDC1_DAT2__FUNC_SDA2 (MTK_PIN_NO(109) | 3) +-#define MT2701_PIN_109_MSDC1_DAT2__FUNC_UTXD1 (MTK_PIN_NO(109) | 5) +-#define MT2701_PIN_109_MSDC1_DAT2__FUNC_PWM2 (MTK_PIN_NO(109) | 6) +-#define MT2701_PIN_109_MSDC1_DAT2__FUNC_DBG_MON_B_24 (MTK_PIN_NO(109) | 7) +- +-#define MT2701_PIN_110_MSDC1_DAT3__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +-#define MT2701_PIN_110_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1) +-#define MT2701_PIN_110_MSDC1_DAT3__FUNC_ANT_SEL5 (MTK_PIN_NO(110) | 2) +-#define MT2701_PIN_110_MSDC1_DAT3__FUNC_SCL2 (MTK_PIN_NO(110) | 3) +-#define MT2701_PIN_110_MSDC1_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(110) | 4) +-#define MT2701_PIN_110_MSDC1_DAT3__FUNC_URXD1 (MTK_PIN_NO(110) | 5) +-#define MT2701_PIN_110_MSDC1_DAT3__FUNC_PWM3 (MTK_PIN_NO(110) | 6) +-#define MT2701_PIN_110_MSDC1_DAT3__FUNC_DBG_MON_B_23 (MTK_PIN_NO(110) | 7) +- +-#define MT2701_PIN_111_MSDC0_DAT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +-#define MT2701_PIN_111_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1) +-#define MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(111) | 4) +- +-#define MT2701_PIN_112_MSDC0_DAT6__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +-#define MT2701_PIN_112_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1) +-#define MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(112) | 4) +- +-#define MT2701_PIN_113_MSDC0_DAT5__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +-#define MT2701_PIN_113_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1) +-#define MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5 (MTK_PIN_NO(113) | 4) +- +-#define MT2701_PIN_114_MSDC0_DAT4__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +-#define MT2701_PIN_114_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1) +-#define MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4 (MTK_PIN_NO(114) | 4) +- +-#define MT2701_PIN_115_MSDC0_RSTB__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +-#define MT2701_PIN_115_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1) +-#define MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8 (MTK_PIN_NO(115) | 4) +- +-#define MT2701_PIN_116_MSDC0_CMD__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +-#define MT2701_PIN_116_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1) +-#define MT2701_PIN_116_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(116) | 4) +- +-#define MT2701_PIN_117_MSDC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +-#define MT2701_PIN_117_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1) +-#define MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(117) | 4) +- +-#define MT2701_PIN_118_MSDC0_DAT3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +-#define MT2701_PIN_118_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1) +-#define MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3 (MTK_PIN_NO(118) | 4) +- +-#define MT2701_PIN_119_MSDC0_DAT2__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +-#define MT2701_PIN_119_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1) +-#define MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2 (MTK_PIN_NO(119) | 4) +- +-#define MT2701_PIN_120_MSDC0_DAT1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +-#define MT2701_PIN_120_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1) +-#define MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1 (MTK_PIN_NO(120) | 4) +- +-#define MT2701_PIN_121_MSDC0_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +-#define MT2701_PIN_121_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1) +-#define MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0 (MTK_PIN_NO(121) | 4) +-#define MT2701_PIN_121_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(121) | 5) +- +-#define MT2701_PIN_122_CEC__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +-#define MT2701_PIN_122_CEC__FUNC_CEC (MTK_PIN_NO(122) | 1) +-#define MT2701_PIN_122_CEC__FUNC_SDA2 (MTK_PIN_NO(122) | 4) +-#define MT2701_PIN_122_CEC__FUNC_URXD0 (MTK_PIN_NO(122) | 5) +- +-#define MT2701_PIN_123_HTPLG__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +-#define MT2701_PIN_123_HTPLG__FUNC_HTPLG (MTK_PIN_NO(123) | 1) +-#define MT2701_PIN_123_HTPLG__FUNC_SCL2 (MTK_PIN_NO(123) | 4) +-#define MT2701_PIN_123_HTPLG__FUNC_UTXD0 (MTK_PIN_NO(123) | 5) +- +-#define MT2701_PIN_124_HDMISCK__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +-#define MT2701_PIN_124_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(124) | 1) +-#define MT2701_PIN_124_HDMISCK__FUNC_SDA1 (MTK_PIN_NO(124) | 4) +-#define MT2701_PIN_124_HDMISCK__FUNC_PWM3 (MTK_PIN_NO(124) | 5) +- +-#define MT2701_PIN_125_HDMISD__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +-#define MT2701_PIN_125_HDMISD__FUNC_HDMISD (MTK_PIN_NO(125) | 1) +-#define MT2701_PIN_125_HDMISD__FUNC_SCL1 (MTK_PIN_NO(125) | 4) +-#define MT2701_PIN_125_HDMISD__FUNC_PWM4 (MTK_PIN_NO(125) | 5) +- +-#define MT2701_PIN_126_I2S0_MCLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +-#define MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1) +-#define MT2701_PIN_126_I2S0_MCLK__FUNC_WCN_I2S_MCLK (MTK_PIN_NO(126) | 6) +-#define MT2701_PIN_126_I2S0_MCLK__FUNC_DBG_MON_B_6 (MTK_PIN_NO(126) | 7) +- +-#define MT2701_PIN_199_SPI1_CLK__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +-#define MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK (MTK_PIN_NO(199) | 1) +-#define MT2701_PIN_199_SPI1_CLK__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(199) | 3) +-#define MT2701_PIN_199_SPI1_CLK__FUNC_KCOL3 (MTK_PIN_NO(199) | 4) +-#define MT2701_PIN_199_SPI1_CLK__FUNC_DBG_MON_B_15 (MTK_PIN_NO(199) | 7) +- +-#define MT2701_PIN_200_SPDIF_OUT__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +-#define MT2701_PIN_200_SPDIF_OUT__FUNC_SPDIF_OUT (MTK_PIN_NO(200) | 1) +-#define MT2701_PIN_200_SPDIF_OUT__FUNC_G1_TXD3 (MTK_PIN_NO(200) | 5) +-#define MT2701_PIN_200_SPDIF_OUT__FUNC_URXD2 (MTK_PIN_NO(200) | 6) +-#define MT2701_PIN_200_SPDIF_OUT__FUNC_DBG_MON_B_16 (MTK_PIN_NO(200) | 7) +- +-#define MT2701_PIN_201_SPDIF_IN0__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +-#define MT2701_PIN_201_SPDIF_IN0__FUNC_SPDIF_IN0 (MTK_PIN_NO(201) | 1) +-#define MT2701_PIN_201_SPDIF_IN0__FUNC_G1_TXEN (MTK_PIN_NO(201) | 5) +-#define MT2701_PIN_201_SPDIF_IN0__FUNC_UTXD2 (MTK_PIN_NO(201) | 6) +-#define MT2701_PIN_201_SPDIF_IN0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(201) | 7) +- +-#define MT2701_PIN_202_SPDIF_IN1__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +-#define MT2701_PIN_202_SPDIF_IN1__FUNC_SPDIF_IN1 (MTK_PIN_NO(202) | 1) +- +-#define MT2701_PIN_203_PWM0__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) +-#define MT2701_PIN_203_PWM0__FUNC_PWM0 (MTK_PIN_NO(203) | 1) +-#define MT2701_PIN_203_PWM0__FUNC_DISP_PWM (MTK_PIN_NO(203) | 2) +-#define MT2701_PIN_203_PWM0__FUNC_G1_TXD2 (MTK_PIN_NO(203) | 5) +-#define MT2701_PIN_203_PWM0__FUNC_DBG_MON_B_18 (MTK_PIN_NO(203) | 7) +-#define MT2701_PIN_203_PWM0__FUNC_I2S2_DATA (MTK_PIN_NO(203) | 9) +- +-#define MT2701_PIN_204_PWM1__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) +-#define MT2701_PIN_204_PWM1__FUNC_PWM1 (MTK_PIN_NO(204) | 1) +-#define MT2701_PIN_204_PWM1__FUNC_CLKM3 (MTK_PIN_NO(204) | 2) +-#define MT2701_PIN_204_PWM1__FUNC_G1_TXD1 (MTK_PIN_NO(204) | 5) +-#define MT2701_PIN_204_PWM1__FUNC_DBG_MON_B_19 (MTK_PIN_NO(204) | 7) +-#define MT2701_PIN_204_PWM1__FUNC_I2S3_DATA (MTK_PIN_NO(204) | 9) +- +-#define MT2701_PIN_205_PWM2__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) +-#define MT2701_PIN_205_PWM2__FUNC_PWM2 (MTK_PIN_NO(205) | 1) +-#define MT2701_PIN_205_PWM2__FUNC_CLKM2 (MTK_PIN_NO(205) | 2) +-#define MT2701_PIN_205_PWM2__FUNC_G1_TXD0 (MTK_PIN_NO(205) | 5) +-#define MT2701_PIN_205_PWM2__FUNC_DBG_MON_B_20 (MTK_PIN_NO(205) | 7) +- +-#define MT2701_PIN_206_PWM3__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) +-#define MT2701_PIN_206_PWM3__FUNC_PWM3 (MTK_PIN_NO(206) | 1) +-#define MT2701_PIN_206_PWM3__FUNC_CLKM1 (MTK_PIN_NO(206) | 2) +-#define MT2701_PIN_206_PWM3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(206) | 3) +-#define MT2701_PIN_206_PWM3__FUNC_G1_TXC (MTK_PIN_NO(206) | 5) +-#define MT2701_PIN_206_PWM3__FUNC_DBG_MON_B_21 (MTK_PIN_NO(206) | 7) +- +-#define MT2701_PIN_207_PWM4__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) +-#define MT2701_PIN_207_PWM4__FUNC_PWM4 (MTK_PIN_NO(207) | 1) +-#define MT2701_PIN_207_PWM4__FUNC_CLKM0 (MTK_PIN_NO(207) | 2) +-#define MT2701_PIN_207_PWM4__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(207) | 3) +-#define MT2701_PIN_207_PWM4__FUNC_G1_RXC (MTK_PIN_NO(207) | 5) +-#define MT2701_PIN_207_PWM4__FUNC_DBG_MON_B_22 (MTK_PIN_NO(207) | 7) +- +-#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) +-#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1) +-#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PWM0 (MTK_PIN_NO(208) | 2) +-#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_ANT_SEL5 (MTK_PIN_NO(208) | 4) +-#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM (MTK_PIN_NO(208) | 5) +-#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(208) | 7) +-#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 11) +- +-#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) +-#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1) +-#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2) +-#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PWM1 (MTK_PIN_NO(209) | 5) +-#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_DBG_MON_A_32 (MTK_PIN_NO(209) | 7) +-#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 11) +- +-#define MT2701_PIN_236_EXT_SDIO3__FUNC_GPIO236 (MTK_PIN_NO(236) | 0) +-#define MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1) +-#define MT2701_PIN_236_EXT_SDIO3__FUNC_IDDIG (MTK_PIN_NO(236) | 2) +-#define MT2701_PIN_236_EXT_SDIO3__FUNC_DBG_MON_A_1 (MTK_PIN_NO(236) | 7) +- +-#define MT2701_PIN_237_EXT_SDIO2__FUNC_GPIO237 (MTK_PIN_NO(237) | 0) +-#define MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1) +-#define MT2701_PIN_237_EXT_SDIO2__FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2) +- +-#define MT2701_PIN_238_EXT_SDIO1__FUNC_GPIO238 (MTK_PIN_NO(238) | 0) +-#define MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1) +-#define MT2701_PIN_238_EXT_SDIO1__FUNC_IDDIG_P1 (MTK_PIN_NO(238) | 2) +- +-#define MT2701_PIN_239_EXT_SDIO0__FUNC_GPIO239 (MTK_PIN_NO(239) | 0) +-#define MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1) +-#define MT2701_PIN_239_EXT_SDIO0__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(239) | 2) +- +-#define MT2701_PIN_240_EXT_XCS__FUNC_GPIO240 (MTK_PIN_NO(240) | 0) +-#define MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS (MTK_PIN_NO(240) | 1) +- +-#define MT2701_PIN_241_EXT_SCK__FUNC_GPIO241 (MTK_PIN_NO(241) | 0) +-#define MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK (MTK_PIN_NO(241) | 1) +- +-#define MT2701_PIN_242_URTS2__FUNC_GPIO242 (MTK_PIN_NO(242) | 0) +-#define MT2701_PIN_242_URTS2__FUNC_URTS2 (MTK_PIN_NO(242) | 1) +-#define MT2701_PIN_242_URTS2__FUNC_UTXD3 (MTK_PIN_NO(242) | 2) +-#define MT2701_PIN_242_URTS2__FUNC_URXD3 (MTK_PIN_NO(242) | 3) +-#define MT2701_PIN_242_URTS2__FUNC_SCL1 (MTK_PIN_NO(242) | 4) +-#define MT2701_PIN_242_URTS2__FUNC_DBG_MON_B_32 (MTK_PIN_NO(242) | 7) +- +-#define MT2701_PIN_243_UCTS2__FUNC_GPIO243 (MTK_PIN_NO(243) | 0) +-#define MT2701_PIN_243_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(243) | 1) +-#define MT2701_PIN_243_UCTS2__FUNC_URXD3 (MTK_PIN_NO(243) | 2) +-#define MT2701_PIN_243_UCTS2__FUNC_UTXD3 (MTK_PIN_NO(243) | 3) +-#define MT2701_PIN_243_UCTS2__FUNC_SDA1 (MTK_PIN_NO(243) | 4) +-#define MT2701_PIN_243_UCTS2__FUNC_DBG_MON_A_6 (MTK_PIN_NO(243) | 7) +- +-#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_GPIO244 (MTK_PIN_NO(244) | 0) +-#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_HDMI_SDA_RX (MTK_PIN_NO(244) | 1) +- +-#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_GPIO245 (MTK_PIN_NO(245) | 0) +-#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_HDMI_SCL_RX (MTK_PIN_NO(245) | 1) +- +-#define MT2701_PIN_246_MHL_SENCE__FUNC_GPIO246 (MTK_PIN_NO(246) | 0) +- +-#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_GPIO247 (MTK_PIN_NO(247) | 0) +-#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_HDMI_HPD_RX (MTK_PIN_NO(247) | 1) +- +-#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_GPIO248 (MTK_PIN_NO(248) | 0) +-#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_HDMI_TESTOUTP_RX (MTK_PIN_NO(248) | 1) +- +-#define MT2701_PIN_249_MSDC0E_RSTB__FUNC_MSDC0E_RSTB (MTK_PIN_NO(249) | 9) +- +-#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_MSDC3_DAT7 (MTK_PIN_NO(250) | 9) +-#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 14) +- +-#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_MSDC3_DAT6 (MTK_PIN_NO(251) | 9) +-#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 14) +- +-#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_MSDC3_DAT5 (MTK_PIN_NO(252) | 9) +-#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 14) +- +-#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_MSDC3_DAT4 (MTK_PIN_NO(253) | 9) +-#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 14) +- +-#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(254) | 9) +-#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 14) +- +-#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(255) | 9) +-#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 14) +- +-#define MT2701_PIN_256_MSDC0E_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(256) | 9) +- +-#define MT2701_PIN_257_MSDC0E_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(257) | 9) +- +-#define MT2701_PIN_258_MSDC0E_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(258) | 9) +- +-#define MT2701_PIN_259_MSDC0E_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(259) | 9) +- +-#define MT2701_PIN_260_MSDC0E_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(260) | 9) +- +-#define MT2701_PIN_261_MSDC1_INS__FUNC_GPIO261 (MTK_PIN_NO(261) | 0) +-#define MT2701_PIN_261_MSDC1_INS__FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1) +-#define MT2701_PIN_261_MSDC1_INS__FUNC_DBG_MON_B_29 (MTK_PIN_NO(261) | 7) +- +-#define MT2701_PIN_262_G2_TXEN__FUNC_GPIO262 (MTK_PIN_NO(262) | 0) +-#define MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN (MTK_PIN_NO(262) | 1) +- +-#define MT2701_PIN_263_G2_TXD3__FUNC_GPIO263 (MTK_PIN_NO(263) | 0) +-#define MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1) +-#define MT2701_PIN_263_G2_TXD3__FUNC_ANT_SEL5 (MTK_PIN_NO(263) | 6) +- +-#define MT2701_PIN_264_G2_TXD2__FUNC_GPIO264 (MTK_PIN_NO(264) | 0) +-#define MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1) +-#define MT2701_PIN_264_G2_TXD2__FUNC_ANT_SEL4 (MTK_PIN_NO(264) | 6) +- +-#define MT2701_PIN_265_G2_TXD1__FUNC_GPIO265 (MTK_PIN_NO(265) | 0) +-#define MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1) +-#define MT2701_PIN_265_G2_TXD1__FUNC_ANT_SEL3 (MTK_PIN_NO(265) | 6) +- +-#define MT2701_PIN_266_G2_TXD0__FUNC_GPIO266 (MTK_PIN_NO(266) | 0) +-#define MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1) +-#define MT2701_PIN_266_G2_TXD0__FUNC_ANT_SEL2 (MTK_PIN_NO(266) | 6) +- +-#define MT2701_PIN_267_G2_TXC__FUNC_GPIO267 (MTK_PIN_NO(267) | 0) +-#define MT2701_PIN_267_G2_TXC__FUNC_G2_TXC (MTK_PIN_NO(267) | 1) +- +-#define MT2701_PIN_268_G2_RXC__FUNC_GPIO268 (MTK_PIN_NO(268) | 0) +-#define MT2701_PIN_268_G2_RXC__FUNC_G2_RXC (MTK_PIN_NO(268) | 1) +- +-#define MT2701_PIN_269_G2_RXD0__FUNC_GPIO269 (MTK_PIN_NO(269) | 0) +-#define MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1) +- +-#define MT2701_PIN_270_G2_RXD1__FUNC_GPIO270 (MTK_PIN_NO(270) | 0) +-#define MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1) +- +-#define MT2701_PIN_271_G2_RXD2__FUNC_GPIO271 (MTK_PIN_NO(271) | 0) +-#define MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1) +- +-#define MT2701_PIN_272_G2_RXD3__FUNC_GPIO272 (MTK_PIN_NO(272) | 0) +-#define MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1) +- +-#define MT2701_PIN_274_G2_RXDV__FUNC_GPIO274 (MTK_PIN_NO(274) | 0) +-#define MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV (MTK_PIN_NO(274) | 1) +- +-#define MT2701_PIN_275_MDC__FUNC_GPIO275 (MTK_PIN_NO(275) | 0) +-#define MT2701_PIN_275_MDC__FUNC_MDC (MTK_PIN_NO(275) | 1) +-#define MT2701_PIN_275_MDC__FUNC_ANT_SEL0 (MTK_PIN_NO(275) | 6) +- +-#define MT2701_PIN_276_MDIO__FUNC_GPIO276 (MTK_PIN_NO(276) | 0) +-#define MT2701_PIN_276_MDIO__FUNC_MDIO (MTK_PIN_NO(276) | 1) +-#define MT2701_PIN_276_MDIO__FUNC_ANT_SEL1 (MTK_PIN_NO(276) | 6) +- +-#define MT2701_PIN_278_JTAG_RESET__FUNC_GPIO278 (MTK_PIN_NO(278) | 0) +-#define MT2701_PIN_278_JTAG_RESET__FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1) +- +-#endif /* __DTS_MT2701_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm/mt2701.dtsi b/scripts/dtc/include-prefixes/arm/mt2701.dtsi +deleted file mode 100644 +index 4776f85d6d5b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt2701.dtsi ++++ /dev/null +@@ -1,759 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2015 MediaTek Inc. +- * Author: Erin.Lo +- * +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include "mt2701-pinfunc.h" +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "mediatek,mt2701"; +- interrupt-parent = <&cirq>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "mediatek,mt81xx-tz-smp"; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x0>; +- }; +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x1>; +- }; +- cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x2>; +- }; +- cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x3>; +- }; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- trustzone-bootinfo@80002000 { +- compatible = "mediatek,trustzone-bootinfo"; +- reg = <0 0x80002000 0 0x1000>; +- }; +- }; +- +- system_clk: dummy13m { +- compatible = "fixed-clock"; +- clock-frequency = <13000000>; +- #clock-cells = <0>; +- }; +- +- rtc_clk: dummy32k { +- compatible = "fixed-clock"; +- clock-frequency = <32000>; +- #clock-cells = <0>; +- }; +- +- clk26m: oscillator@0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- clock-output-names = "clk26m"; +- }; +- +- rtc32k: oscillator@1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32000>; +- clock-output-names = "rtc32k"; +- }; +- +- thermal-zones { +- cpu_thermal: cpu_thermal { +- polling-delay-passive = <1000>; /* milliseconds */ +- polling-delay = <1000>; /* milliseconds */ +- +- thermal-sensors = <&thermal 0>; +- sustainable-power = <1000>; +- +- trips { +- threshold: trip-point@0 { +- temperature = <68000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- target: trip-point@1 { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_crit: cpu_crit@0 { +- temperature = <115000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- }; +- +- topckgen: syscon@10000000 { +- compatible = "mediatek,mt2701-topckgen", "syscon"; +- reg = <0 0x10000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- infracfg: syscon@10001000 { +- compatible = "mediatek,mt2701-infracfg", "syscon"; +- reg = <0 0x10001000 0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pericfg: syscon@10003000 { +- compatible = "mediatek,mt2701-pericfg", "syscon"; +- reg = <0 0x10003000 0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- syscfg_pctl_a: syscfg@10005000 { +- compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon"; +- reg = <0 0x10005000 0 0x1000>; +- }; +- +- scpsys: power-controller@10006000 { +- compatible = "mediatek,mt2701-scpsys", "syscon"; +- #power-domain-cells = <1>; +- reg = <0 0x10006000 0 0x1000>; +- infracfg = <&infracfg>; +- clocks = <&topckgen CLK_TOP_MM_SEL>, +- <&topckgen CLK_TOP_MFG_SEL>, +- <&topckgen CLK_TOP_ETHIF_SEL>; +- clock-names = "mm", "mfg", "ethif"; +- }; +- +- watchdog: watchdog@10007000 { +- compatible = "mediatek,mt2701-wdt", +- "mediatek,mt6589-wdt"; +- reg = <0 0x10007000 0 0x100>; +- }; +- +- timer: timer@10008000 { +- compatible = "mediatek,mt2701-timer", +- "mediatek,mt6577-timer"; +- reg = <0 0x10008000 0 0x80>; +- interrupts = ; +- clocks = <&system_clk>, <&rtc_clk>; +- clock-names = "system-clk", "rtc-clk"; +- }; +- +- pio: pinctrl@1000b000 { +- compatible = "mediatek,mt2701-pinctrl"; +- reg = <0 0x1000b000 0 0x1000>; +- mediatek,pctl-regmap = <&syscfg_pctl_a>; +- pins-are-numbered; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = , +- ; +- }; +- +- smi_common: smi@1000c000 { +- compatible = "mediatek,mt2701-smi-common"; +- reg = <0 0x1000c000 0 0x1000>; +- clocks = <&infracfg CLK_INFRA_SMI>, +- <&mmsys CLK_MM_SMI_COMMON>, +- <&infracfg CLK_INFRA_SMI>; +- clock-names = "apb", "smi", "async"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; +- }; +- +- sysirq: interrupt-controller@10200100 { +- compatible = "mediatek,mt2701-sysirq", +- "mediatek,mt6577-sysirq"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0 0x10200100 0 0x1c>; +- }; +- +- cirq: interrupt-controller@10204000 { +- compatible = "mediatek,mt2701-cirq", +- "mediatek,mtk-cirq"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&sysirq>; +- reg = <0 0x10204000 0 0x400>; +- mediatek,ext-irq-range = <32 200>; +- }; +- +- iommu: mmsys_iommu@10205000 { +- compatible = "mediatek,mt2701-m4u"; +- reg = <0 0x10205000 0 0x1000>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_M4U>; +- clock-names = "bclk"; +- mediatek,larbs = <&larb0 &larb1 &larb2>; +- #iommu-cells = <1>; +- }; +- +- apmixedsys: syscon@10209000 { +- compatible = "mediatek,mt2701-apmixedsys", "syscon"; +- reg = <0 0x10209000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- gic: interrupt-controller@10211000 { +- compatible = "arm,cortex-a7-gic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0 0x10211000 0 0x1000>, +- <0 0x10212000 0 0x2000>, +- <0 0x10214000 0 0x2000>, +- <0 0x10216000 0 0x2000>; +- }; +- +- auxadc: adc@11001000 { +- compatible = "mediatek,mt2701-auxadc"; +- reg = <0 0x11001000 0 0x1000>; +- clocks = <&pericfg CLK_PERI_AUXADC>; +- clock-names = "main"; +- #io-channel-cells = <1>; +- status = "disabled"; +- }; +- +- uart0: serial@11002000 { +- compatible = "mediatek,mt2701-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11002000 0 0x400>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart1: serial@11003000 { +- compatible = "mediatek,mt2701-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11003000 0 0x400>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart2: serial@11004000 { +- compatible = "mediatek,mt2701-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11004000 0 0x400>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart3: serial@11005000 { +- compatible = "mediatek,mt2701-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11005000 0 0x400>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- i2c0: i2c@11007000 { +- compatible = "mediatek,mt2701-i2c", +- "mediatek,mt6577-i2c"; +- reg = <0 0x11007000 0 0x70>, +- <0 0x11000200 0 0x80>; +- interrupts = ; +- clock-div = <16>; +- clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>; +- clock-names = "main", "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@11008000 { +- compatible = "mediatek,mt2701-i2c", +- "mediatek,mt6577-i2c"; +- reg = <0 0x11008000 0 0x70>, +- <0 0x11000280 0 0x80>; +- interrupts = ; +- clock-div = <16>; +- clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>; +- clock-names = "main", "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@11009000 { +- compatible = "mediatek,mt2701-i2c", +- "mediatek,mt6577-i2c"; +- reg = <0 0x11009000 0 0x70>, +- <0 0x11000300 0 0x80>; +- interrupts = ; +- clock-div = <16>; +- clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>; +- clock-names = "main", "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi0: spi@1100a000 { +- compatible = "mediatek,mt2701-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x1100a000 0 0x100>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, +- <&topckgen CLK_TOP_SPI0_SEL>, +- <&pericfg CLK_PERI_SPI0>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- thermal: thermal@1100b000 { +- #thermal-sensor-cells = <0>; +- compatible = "mediatek,mt2701-thermal"; +- reg = <0 0x1100b000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; +- clock-names = "therm", "auxadc"; +- resets = <&pericfg MT2701_PERI_THERM_SW_RST>; +- reset-names = "therm"; +- mediatek,auxadc = <&auxadc>; +- mediatek,apmixedsys = <&apmixedsys>; +- }; +- +- nandc: nfi@1100d000 { +- compatible = "mediatek,mt2701-nfc"; +- reg = <0 0x1100d000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_NFI>, +- <&pericfg CLK_PERI_NFI_PAD>; +- clock-names = "nfi_clk", "pad_clk"; +- status = "disabled"; +- ecc-engine = <&bch>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- bch: ecc@1100e000 { +- compatible = "mediatek,mt2701-ecc"; +- reg = <0 0x1100e000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_NFI_ECC>; +- clock-names = "nfiecc_clk"; +- status = "disabled"; +- }; +- +- nor_flash: spi@11014000 { +- compatible = "mediatek,mt2701-nor", +- "mediatek,mt8173-nor"; +- reg = <0 0x11014000 0 0xe0>; +- clocks = <&pericfg CLK_PERI_FLASH>, +- <&topckgen CLK_TOP_FLASH_SEL>; +- clock-names = "spi", "sf"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi1: spi@11016000 { +- compatible = "mediatek,mt2701-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x11016000 0 0x100>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, +- <&topckgen CLK_TOP_SPI1_SEL>, +- <&pericfg CLK_PERI_SPI1>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- spi2: spi@11017000 { +- compatible = "mediatek,mt2701-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x11017000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, +- <&topckgen CLK_TOP_SPI2_SEL>, +- <&pericfg CLK_PERI_SPI2>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- audsys: clock-controller@11220000 { +- compatible = "mediatek,mt2701-audsys", "syscon"; +- reg = <0 0x11220000 0 0x2000>; +- #clock-cells = <1>; +- +- afe: audio-controller { +- compatible = "mediatek,mt2701-audio"; +- interrupts = , +- ; +- interrupt-names = "afe", "asys"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; +- +- clocks = <&infracfg CLK_INFRA_AUDIO>, +- <&topckgen CLK_TOP_AUD_MUX1_SEL>, +- <&topckgen CLK_TOP_AUD_MUX2_SEL>, +- <&topckgen CLK_TOP_AUD_48K_TIMING>, +- <&topckgen CLK_TOP_AUD_44K_TIMING>, +- <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, +- <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, +- <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, +- <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, +- <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, +- <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, +- <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, +- <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, +- <&topckgen CLK_TOP_AUD_I2S1_MCLK>, +- <&topckgen CLK_TOP_AUD_I2S2_MCLK>, +- <&topckgen CLK_TOP_AUD_I2S3_MCLK>, +- <&topckgen CLK_TOP_AUD_I2S4_MCLK>, +- <&audsys CLK_AUD_I2SO1>, +- <&audsys CLK_AUD_I2SO2>, +- <&audsys CLK_AUD_I2SO3>, +- <&audsys CLK_AUD_I2SO4>, +- <&audsys CLK_AUD_I2SIN1>, +- <&audsys CLK_AUD_I2SIN2>, +- <&audsys CLK_AUD_I2SIN3>, +- <&audsys CLK_AUD_I2SIN4>, +- <&audsys CLK_AUD_ASRCO1>, +- <&audsys CLK_AUD_ASRCO2>, +- <&audsys CLK_AUD_ASRCO3>, +- <&audsys CLK_AUD_ASRCO4>, +- <&audsys CLK_AUD_AFE>, +- <&audsys CLK_AUD_AFE_CONN>, +- <&audsys CLK_AUD_A1SYS>, +- <&audsys CLK_AUD_A2SYS>, +- <&audsys CLK_AUD_AFE_MRGIF>; +- +- clock-names = "infra_sys_audio_clk", +- "top_audio_mux1_sel", +- "top_audio_mux2_sel", +- "top_audio_a1sys_hp", +- "top_audio_a2sys_hp", +- "i2s0_src_sel", +- "i2s1_src_sel", +- "i2s2_src_sel", +- "i2s3_src_sel", +- "i2s0_src_div", +- "i2s1_src_div", +- "i2s2_src_div", +- "i2s3_src_div", +- "i2s0_mclk_en", +- "i2s1_mclk_en", +- "i2s2_mclk_en", +- "i2s3_mclk_en", +- "i2so0_hop_ck", +- "i2so1_hop_ck", +- "i2so2_hop_ck", +- "i2so3_hop_ck", +- "i2si0_hop_ck", +- "i2si1_hop_ck", +- "i2si2_hop_ck", +- "i2si3_hop_ck", +- "asrc0_out_ck", +- "asrc1_out_ck", +- "asrc2_out_ck", +- "asrc3_out_ck", +- "audio_afe_pd", +- "audio_afe_conn_pd", +- "audio_a1sys_pd", +- "audio_a2sys_pd", +- "audio_mrgif_pd"; +- +- assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, +- <&topckgen CLK_TOP_AUD_MUX2_SEL>, +- <&topckgen CLK_TOP_AUD_MUX1_DIV>, +- <&topckgen CLK_TOP_AUD_MUX2_DIV>; +- assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, +- <&topckgen CLK_TOP_AUD2PLL_90M>; +- assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; +- }; +- }; +- +- mmsys: syscon@14000000 { +- compatible = "mediatek,mt2701-mmsys", "syscon"; +- reg = <0 0x14000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- bls: pwm@1400a000 { +- compatible = "mediatek,mt2701-disp-pwm"; +- reg = <0 0x1400a000 0 0x1000>; +- #pwm-cells = <2>; +- clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>; +- clock-names = "main", "mm"; +- status = "disabled"; +- }; +- +- larb0: larb@14010000 { +- compatible = "mediatek,mt2701-smi-larb"; +- reg = <0 0x14010000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- mediatek,larb-id = <0>; +- clocks = <&mmsys CLK_MM_SMI_LARB0>, +- <&mmsys CLK_MM_SMI_LARB0>; +- clock-names = "apb", "smi"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; +- }; +- +- imgsys: syscon@15000000 { +- compatible = "mediatek,mt2701-imgsys", "syscon"; +- reg = <0 0x15000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- larb2: larb@15001000 { +- compatible = "mediatek,mt2701-smi-larb"; +- reg = <0 0x15001000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- mediatek,larb-id = <2>; +- clocks = <&imgsys CLK_IMG_SMI_COMM>, +- <&imgsys CLK_IMG_SMI_COMM>; +- clock-names = "apb", "smi"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; +- }; +- +- jpegdec: jpegdec@15004000 { +- compatible = "mediatek,mt2701-jpgdec"; +- reg = <0 0x15004000 0 0x1000>; +- interrupts = ; +- clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, +- <&imgsys CLK_IMG_JPGDEC>; +- clock-names = "jpgdec-smi", +- "jpgdec"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; +- mediatek,larb = <&larb2>; +- iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, +- <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; +- }; +- +- jpegenc: jpegenc@1500a000 { +- compatible = "mediatek,mt2701-jpgenc", +- "mediatek,mtk-jpgenc"; +- reg = <0 0x1500a000 0 0x1000>; +- interrupts = ; +- clocks = <&imgsys CLK_IMG_VENC>; +- clock-names = "jpgenc"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; +- mediatek,larb = <&larb2>; +- iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>, +- <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>; +- }; +- +- vdecsys: syscon@16000000 { +- compatible = "mediatek,mt2701-vdecsys", "syscon"; +- reg = <0 0x16000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- larb1: larb@16010000 { +- compatible = "mediatek,mt2701-smi-larb"; +- reg = <0 0x16010000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- mediatek,larb-id = <1>; +- clocks = <&vdecsys CLK_VDEC_CKGEN>, +- <&vdecsys CLK_VDEC_LARB>; +- clock-names = "apb", "smi"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; +- }; +- +- hifsys: syscon@1a000000 { +- compatible = "mediatek,mt2701-hifsys", "syscon"; +- reg = <0 0x1a000000 0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- usb0: usb@1a1c0000 { +- compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci"; +- reg = <0 0x1a1c0000 0 0x1000>, +- <0 0x1a1c4700 0 0x0100>; +- reg-names = "mac", "ippc"; +- interrupts = ; +- clocks = <&hifsys CLK_HIFSYS_USB0PHY>, +- <&topckgen CLK_TOP_ETHIF_SEL>; +- clock-names = "sys_ck", "ref_ck"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; +- phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; +- status = "disabled"; +- }; +- +- u3phy0: t-phy@1a1c4000 { +- compatible = "mediatek,mt2701-tphy", +- "mediatek,generic-tphy-v1"; +- reg = <0 0x1a1c4000 0 0x0700>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "disabled"; +- +- u2port0: usb-phy@1a1c4800 { +- reg = <0 0x1a1c4800 0 0x0100>; +- clocks = <&topckgen CLK_TOP_USB_PHY48M>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- +- u3port0: usb-phy@1a1c4900 { +- reg = <0 0x1a1c4900 0 0x0700>; +- clocks = <&clk26m>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- }; +- +- usb1: usb@1a240000 { +- compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci"; +- reg = <0 0x1a240000 0 0x1000>, +- <0 0x1a244700 0 0x0100>; +- reg-names = "mac", "ippc"; +- interrupts = ; +- clocks = <&hifsys CLK_HIFSYS_USB1PHY>, +- <&topckgen CLK_TOP_ETHIF_SEL>; +- clock-names = "sys_ck", "ref_ck"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; +- phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; +- status = "disabled"; +- }; +- +- u3phy1: t-phy@1a244000 { +- compatible = "mediatek,mt2701-tphy", +- "mediatek,generic-tphy-v1"; +- reg = <0 0x1a244000 0 0x0700>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "disabled"; +- +- u2port1: usb-phy@1a244800 { +- reg = <0 0x1a244800 0 0x0100>; +- clocks = <&topckgen CLK_TOP_USB_PHY48M>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- +- u3port1: usb-phy@1a244900 { +- reg = <0 0x1a244900 0 0x0700>; +- clocks = <&clk26m>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- }; +- +- usb2: usb@11200000 { +- compatible = "mediatek,mt2701-musb", +- "mediatek,mtk-musb"; +- reg = <0 0x11200000 0 0x1000>; +- interrupts = ; +- interrupt-names = "mc"; +- phys = <&u2port2 PHY_TYPE_USB2>; +- dr_mode = "otg"; +- clocks = <&pericfg CLK_PERI_USB0>, +- <&pericfg CLK_PERI_USB0_MCU>, +- <&pericfg CLK_PERI_USB_SLV>; +- clock-names = "main","mcu","univpll"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; +- status = "disabled"; +- }; +- +- u2phy0: t-phy@11210000 { +- compatible = "mediatek,mt2701-tphy", +- "mediatek,generic-tphy-v1"; +- reg = <0 0x11210000 0 0x0800>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "okay"; +- +- u2port2: usb-phy@1a1c4800 { +- reg = <0 0x11210800 0 0x0100>; +- clocks = <&topckgen CLK_TOP_USB_PHY48M>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- }; +- +- ethsys: syscon@1b000000 { +- compatible = "mediatek,mt2701-ethsys", "syscon"; +- reg = <0 0x1b000000 0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- eth: ethernet@1b100000 { +- compatible = "mediatek,mt2701-eth", "syscon"; +- reg = <0 0x1b100000 0 0x20000>; +- interrupts = , +- , +- ; +- clocks = <&topckgen CLK_TOP_ETHIF_SEL>, +- <ðsys CLK_ETHSYS_ESW>, +- <ðsys CLK_ETHSYS_GP1>, +- <ðsys CLK_ETHSYS_GP2>, +- <&apmixedsys CLK_APMIXED_TRGPLL>; +- clock-names = "ethif", "esw", "gp1", "gp2", "trgpll"; +- resets = <ðsys MT2701_ETHSYS_FE_RST>, +- <ðsys MT2701_ETHSYS_GMAC_RST>, +- <ðsys MT2701_ETHSYS_PPE_RST>; +- reset-names = "fe", "gmac", "ppe"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; +- mediatek,ethsys = <ðsys>; +- mediatek,pctl = <&syscfg_pctl_a>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- bdpsys: syscon@1c000000 { +- compatible = "mediatek,mt2701-bdpsys", "syscon"; +- reg = <0 0x1c000000 0 0x1000>; +- #clock-cells = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt6323.dtsi b/scripts/dtc/include-prefixes/arm/mt6323.dtsi +deleted file mode 100644 +index 7fda40ab5fe8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt6323.dtsi ++++ /dev/null +@@ -1,269 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2017-2018 MediaTek Inc. +- * Author: John Crispin +- * Sean Wang +- * +- */ +- +-&pwrap { +- pmic: mt6323 { +- compatible = "mediatek,mt6323"; +- interrupt-parent = <&pio>; +- interrupts = <150 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- mt6323_leds: leds { +- compatible = "mediatek,mt6323-led"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- mt6323regulator: mt6323regulator{ +- compatible = "mediatek,mt6323-regulator"; +- +- mt6323_vproc_reg: buck_vproc{ +- regulator-name = "vproc"; +- regulator-min-microvolt = < 700000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- mt6323_vsys_reg: buck_vsys{ +- regulator-name = "vsys"; +- regulator-min-microvolt = <1400000>; +- regulator-max-microvolt = <2987500>; +- regulator-ramp-delay = <25000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- mt6323_vpa_reg: buck_vpa{ +- regulator-name = "vpa"; +- regulator-min-microvolt = < 500000>; +- regulator-max-microvolt = <3650000>; +- }; +- +- mt6323_vtcxo_reg: ldo_vtcxo{ +- regulator-name = "vtcxo"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-enable-ramp-delay = <90>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- mt6323_vcn28_reg: ldo_vcn28{ +- regulator-name = "vcn28"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-enable-ramp-delay = <185>; +- }; +- +- mt6323_vcn33_bt_reg: ldo_vcn33_bt{ +- regulator-name = "vcn33_bt"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3600000>; +- regulator-enable-ramp-delay = <185>; +- }; +- +- mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{ +- regulator-name = "vcn33_wifi"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3600000>; +- regulator-enable-ramp-delay = <185>; +- }; +- +- mt6323_va_reg: ldo_va{ +- regulator-name = "va"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-enable-ramp-delay = <216>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- mt6323_vcama_reg: ldo_vcama{ +- regulator-name = "vcama"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <2800000>; +- regulator-enable-ramp-delay = <216>; +- }; +- +- mt6323_vio28_reg: ldo_vio28{ +- regulator-name = "vio28"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-enable-ramp-delay = <216>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- mt6323_vusb_reg: ldo_vusb{ +- regulator-name = "vusb"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <216>; +- regulator-boot-on; +- }; +- +- mt6323_vmc_reg: ldo_vmc{ +- regulator-name = "vmc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <36>; +- regulator-boot-on; +- }; +- +- mt6323_vmch_reg: ldo_vmch{ +- regulator-name = "vmch"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <36>; +- regulator-boot-on; +- }; +- +- mt6323_vemc3v3_reg: ldo_vemc3v3{ +- regulator-name = "vemc3v3"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <36>; +- regulator-boot-on; +- }; +- +- mt6323_vgp1_reg: ldo_vgp1{ +- regulator-name = "vgp1"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <216>; +- }; +- +- mt6323_vgp2_reg: ldo_vgp2{ +- regulator-name = "vgp2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3000000>; +- regulator-enable-ramp-delay = <216>; +- }; +- +- mt6323_vgp3_reg: ldo_vgp3{ +- regulator-name = "vgp3"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <216>; +- }; +- +- mt6323_vcn18_reg: ldo_vcn18{ +- regulator-name = "vcn18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <216>; +- }; +- +- mt6323_vsim1_reg: ldo_vsim1{ +- regulator-name = "vsim1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- regulator-enable-ramp-delay = <216>; +- }; +- +- mt6323_vsim2_reg: ldo_vsim2{ +- regulator-name = "vsim2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- regulator-enable-ramp-delay = <216>; +- }; +- +- mt6323_vrtc_reg: ldo_vrtc{ +- regulator-name = "vrtc"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- mt6323_vcamaf_reg: ldo_vcamaf{ +- regulator-name = "vcamaf"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <216>; +- }; +- +- mt6323_vibr_reg: ldo_vibr{ +- regulator-name = "vibr"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <36>; +- }; +- +- mt6323_vrf18_reg: ldo_vrf18{ +- regulator-name = "vrf18"; +- regulator-min-microvolt = <1825000>; +- regulator-max-microvolt = <1825000>; +- regulator-enable-ramp-delay = <187>; +- }; +- +- mt6323_vm_reg: ldo_vm{ +- regulator-name = "vm"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <216>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- mt6323_vio18_reg: ldo_vio18{ +- regulator-name = "vio18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <216>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- mt6323_vcamd_reg: ldo_vcamd{ +- regulator-name = "vcamd"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <216>; +- }; +- +- mt6323_vcamio_reg: ldo_vcamio{ +- regulator-name = "vcamio"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <216>; +- }; +- }; +- +- mt6323keys: mt6323keys { +- compatible = "mediatek,mt6323-keys"; +- mediatek,long-press-mode = <1>; +- power-off-time-sec = <0>; +- +- power { +- linux,keycodes = <116>; +- wakeup-source; +- }; +- +- home { +- linux,keycodes = <114>; +- }; +- }; +- +- codec: mt6397codec { +- compatible = "mediatek,mt6397-codec"; +- }; +- +- power-controller { +- compatible = "mediatek,mt6323-pwrc"; +- }; +- +- rtc { +- compatible = "mediatek,mt6323-rtc"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt6580-evbp1.dts b/scripts/dtc/include-prefixes/arm/mt6580-evbp1.dts +deleted file mode 100644 +index 755a0774a8ee..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt6580-evbp1.dts ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2015 MediaTek Inc. +- * Author: Mars.C +- * +- */ +- +-/dts-v1/; +-#include "mt6580.dtsi" +- +-/ { +- model = "MediaTek MT6580 evaluation board"; +- compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial0:921600n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt6580.dtsi b/scripts/dtc/include-prefixes/arm/mt6580.dtsi +deleted file mode 100644 +index 9e17698c0609..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt6580.dtsi ++++ /dev/null +@@ -1,108 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2015 MediaTek Inc. +- * Author: Mars.C +- * +- */ +- +-#include +-#include +- +-/ { +- compatible = "mediatek,mt6580"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&sysirq>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x0>; +- }; +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x1>; +- }; +- cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x2>; +- }; +- cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x3>; +- }; +- +- }; +- +- system_clk: dummy13m { +- compatible = "fixed-clock"; +- clock-frequency = <13000000>; +- #clock-cells = <0>; +- }; +- +- rtc_clk: dummy32k { +- compatible = "fixed-clock"; +- clock-frequency = <32000>; +- #clock-cells = <0>; +- }; +- +- uart_clk: dummy26m { +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- #clock-cells = <0>; +- }; +- +- timer: timer@10008000 { +- compatible = "mediatek,mt6580-timer", +- "mediatek,mt6577-timer"; +- reg = <0x10008000 0x80>; +- interrupts = ; +- clocks = <&system_clk>, <&rtc_clk>; +- clock-names = "system-clk", "rtc-clk"; +- }; +- +- sysirq: interrupt-controller@10200100 { +- compatible = "mediatek,mt6580-sysirq", +- "mediatek,mt6577-sysirq"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0x10200100 0x1c>; +- }; +- +- gic: interrupt-controller@10211000 { +- compatible = "arm,cortex-a7-gic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0x10211000 0x1000>, +- <0x10212000 0x2000>, +- <0x10214000 0x2000>, +- <0x10216000 0x2000>; +- }; +- +- uart0: serial@11005000 { +- compatible = "mediatek,mt6580-uart", +- "mediatek,mt6577-uart"; +- reg = <0x11005000 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart1: serial@11006000 { +- compatible = "mediatek,mt6580-uart", +- "mediatek,mt6577-uart"; +- reg = <0x11006000 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt6589-aquaris5.dts b/scripts/dtc/include-prefixes/arm/mt6589-aquaris5.dts +deleted file mode 100644 +index 1e7079a3b449..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt6589-aquaris5.dts ++++ /dev/null +@@ -1,33 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (c) 2014 MundoReader S.L. +- * Author: Matthias Brugger +- * +- */ +- +-/dts-v1/; +-#include "mt6589.dtsi" +- +-/ { +- model = "bq Aquaris5"; +- compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589"; +- +- chosen { +- bootargs = "console=ttyS0,921600n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; +- }; +- +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt6589.dtsi b/scripts/dtc/include-prefixes/arm/mt6589.dtsi +deleted file mode 100644 +index 70df00a7bb26..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt6589.dtsi ++++ /dev/null +@@ -1,141 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (c) 2014 MundoReader S.L. +- * Author: Matthias Brugger +- * +-*/ +- +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mediatek,mt6589"; +- interrupt-parent = <&sysirq>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "mediatek,mt6589-smp"; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x0>; +- }; +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x1>; +- }; +- cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x2>; +- }; +- cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x3>; +- }; +- +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges; +- +- system_clk: dummy13m { +- compatible = "fixed-clock"; +- clock-frequency = <13000000>; +- #clock-cells = <0>; +- }; +- +- rtc_clk: dummy32k { +- compatible = "fixed-clock"; +- clock-frequency = <32000>; +- #clock-cells = <0>; +- }; +- +- uart_clk: dummy26m { +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- #clock-cells = <0>; +- }; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges; +- +- timer: timer@10008000 { +- compatible = "mediatek,mt6577-timer"; +- reg = <0x10008000 0x80>; +- interrupts = ; +- clocks = <&system_clk>, <&rtc_clk>; +- clock-names = "system-clk", "rtc-clk"; +- }; +- +- sysirq: interrupt-controller@10200100 { +- compatible = "mediatek,mt6589-sysirq", +- "mediatek,mt6577-sysirq"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0x10200100 0x1c>; +- }; +- +- gic: interrupt-controller@10211000 { +- compatible = "arm,cortex-a7-gic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0x10211000 0x1000>, +- <0x10212000 0x2000>, +- <0x10214000 0x2000>, +- <0x10216000 0x2000>; +- }; +- +- uart0: serial@11006000 { +- compatible = "mediatek,mt6577-uart"; +- reg = <0x11006000 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart1: serial@11007000 { +- compatible = "mediatek,mt6577-uart"; +- reg = <0x11007000 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart2: serial@11008000 { +- compatible = "mediatek,mt6577-uart"; +- reg = <0x11008000 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart3: serial@11009000 { +- compatible = "mediatek,mt6577-uart"; +- reg = <0x11009000 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- wdt: watchdog@10000000 { +- compatible = "mediatek,mt6589-wdt"; +- reg = <0x10000000 0x44>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt6592-evb.dts b/scripts/dtc/include-prefixes/arm/mt6592-evb.dts +deleted file mode 100644 +index 5e00c1cca2d1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt6592-evb.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2014 MediaTek Inc. +- * Author: Howard Chen +- * +- */ +- +-/dts-v1/; +-#include "mt6592.dtsi" +- +-/ { +- model = "mt6592 evb"; +- compatible = "mediatek,mt6592-evb", "mediatek,mt6592"; +- +- memory { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt6592.dtsi b/scripts/dtc/include-prefixes/arm/mt6592.dtsi +deleted file mode 100644 +index 3716f8db951c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt6592.dtsi ++++ /dev/null +@@ -1,137 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2014 MediaTek Inc. +- * Author: Howard Chen +- * +- */ +- +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mediatek,mt6592"; +- interrupt-parent = <&sysirq>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x0>; +- }; +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x1>; +- }; +- cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x2>; +- }; +- cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x3>; +- }; +- cpu@4 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x4>; +- }; +- cpu@5 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x5>; +- }; +- cpu@6 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x6>; +- }; +- cpu@7 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x7>; +- }; +- }; +- +- system_clk: dummy13m { +- compatible = "fixed-clock"; +- clock-frequency = <13000000>; +- #clock-cells = <0>; +- }; +- +- rtc_clk: dummy32k { +- compatible = "fixed-clock"; +- clock-frequency = <32000>; +- #clock-cells = <0>; +- }; +- +- uart_clk: dummy26m { +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- #clock-cells = <0>; +- }; +- +- timer: timer@10008000 { +- compatible = "mediatek,mt6577-timer"; +- reg = <0x10008000 0x80>; +- interrupts = ; +- clocks = <&system_clk>, <&rtc_clk>; +- clock-names = "system-clk", "rtc-clk"; +- }; +- +- sysirq: interrupt-controller@10200220 { +- compatible = "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0x10200220 0x1c>; +- }; +- +- gic: interrupt-controller@10211000 { +- compatible = "arm,cortex-a7-gic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0x10211000 0x1000>, +- <0x10212000 0x1000>; +- }; +- +- uart0: serial@11002000 { +- compatible = "mediatek,mt6577-uart"; +- reg = <0x11002000 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart1: serial@11003000 { +- compatible = "mediatek,mt6577-uart"; +- reg = <0x11003000 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart2: serial@11004000 { +- compatible = "mediatek,mt6577-uart"; +- reg = <0x11004000 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart3: serial@11005000 { +- compatible = "mediatek,mt6577-uart"; +- reg = <0x11005000 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt7623.dtsi b/scripts/dtc/include-prefixes/arm/mt7623.dtsi +deleted file mode 100644 +index a7d62dbad602..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt7623.dtsi ++++ /dev/null +@@ -1,1269 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2017-2018 MediaTek Inc. +- * Author: John Crispin +- * Sean Wang +- * Ryder Lee +- * +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "mediatek,mt7623"; +- interrupt-parent = <&sysirq>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-98000000 { +- opp-hz = /bits/ 64 <98000000>; +- opp-microvolt = <1050000>; +- }; +- +- opp-198000000 { +- opp-hz = /bits/ 64 <198000000>; +- opp-microvolt = <1050000>; +- }; +- +- opp-398000000 { +- opp-hz = /bits/ 64 <398000000>; +- opp-microvolt = <1050000>; +- }; +- +- opp-598000000 { +- opp-hz = /bits/ 64 <598000000>; +- opp-microvolt = <1050000>; +- }; +- +- opp-747500000 { +- opp-hz = /bits/ 64 <747500000>; +- opp-microvolt = <1050000>; +- }; +- +- opp-1040000000 { +- opp-hz = /bits/ 64 <1040000000>; +- opp-microvolt = <1150000>; +- }; +- +- opp-1196000000 { +- opp-hz = /bits/ 64 <1196000000>; +- opp-microvolt = <1200000>; +- }; +- +- opp-1300000000 { +- opp-hz = /bits/ 64 <1300000000>; +- opp-microvolt = <1300000>; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "mediatek,mt6589-smp"; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x0>; +- clocks = <&infracfg CLK_INFRA_CPUSEL>, +- <&apmixedsys CLK_APMIXED_MAINPLL>; +- clock-names = "cpu", "intermediate"; +- operating-points-v2 = <&cpu_opp_table>; +- #cooling-cells = <2>; +- clock-frequency = <1300000000>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x1>; +- clocks = <&infracfg CLK_INFRA_CPUSEL>, +- <&apmixedsys CLK_APMIXED_MAINPLL>; +- clock-names = "cpu", "intermediate"; +- operating-points-v2 = <&cpu_opp_table>; +- #cooling-cells = <2>; +- clock-frequency = <1300000000>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x2>; +- clocks = <&infracfg CLK_INFRA_CPUSEL>, +- <&apmixedsys CLK_APMIXED_MAINPLL>; +- clock-names = "cpu", "intermediate"; +- operating-points-v2 = <&cpu_opp_table>; +- #cooling-cells = <2>; +- clock-frequency = <1300000000>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x3>; +- clocks = <&infracfg CLK_INFRA_CPUSEL>, +- <&apmixedsys CLK_APMIXED_MAINPLL>; +- clock-names = "cpu", "intermediate"; +- operating-points-v2 = <&cpu_opp_table>; +- #cooling-cells = <2>; +- clock-frequency = <1300000000>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- system_clk: dummy13m { +- compatible = "fixed-clock"; +- clock-frequency = <13000000>; +- #clock-cells = <0>; +- }; +- +- rtc32k: oscillator-1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32000>; +- clock-output-names = "rtc32k"; +- }; +- +- clk26m: oscillator-0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- clock-output-names = "clk26m"; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <1000>; +- polling-delay = <1000>; +- +- thermal-sensors = <&thermal 0>; +- +- trips { +- cpu_passive: cpu-passive { +- temperature = <57000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_active: cpu-active { +- temperature = <67000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- cpu_hot: cpu-hot { +- temperature = <87000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- cpu-crit { +- temperature = <107000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_passive>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- +- map1 { +- trip = <&cpu_active>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- +- map2 { +- trip = <&cpu_hot>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- clock-frequency = <13000000>; +- arm,cpu-registers-not-fw-configured; +- }; +- +- topckgen: syscon@10000000 { +- compatible = "mediatek,mt7623-topckgen", +- "mediatek,mt2701-topckgen", +- "syscon"; +- reg = <0 0x10000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- infracfg: syscon@10001000 { +- compatible = "mediatek,mt7623-infracfg", +- "mediatek,mt2701-infracfg", +- "syscon"; +- reg = <0 0x10001000 0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pericfg: syscon@10003000 { +- compatible = "mediatek,mt7623-pericfg", +- "mediatek,mt2701-pericfg", +- "syscon"; +- reg = <0 0x10003000 0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pio: pinctrl@10005000 { +- compatible = "mediatek,mt7623-pinctrl"; +- reg = <0 0x1000b000 0 0x1000>; +- mediatek,pctl-regmap = <&syscfg_pctl_a>; +- pins-are-numbered; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- interrupt-parent = <&gic>; +- #interrupt-cells = <2>; +- interrupts = , +- ; +- }; +- +- syscfg_pctl_a: syscfg@10005000 { +- compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon"; +- reg = <0 0x10005000 0 0x1000>; +- }; +- +- scpsys: power-controller@10006000 { +- compatible = "mediatek,mt7623-scpsys", +- "mediatek,mt2701-scpsys", +- "syscon"; +- #power-domain-cells = <1>; +- reg = <0 0x10006000 0 0x1000>; +- infracfg = <&infracfg>; +- clocks = <&topckgen CLK_TOP_MM_SEL>, +- <&topckgen CLK_TOP_MFG_SEL>, +- <&topckgen CLK_TOP_ETHIF_SEL>; +- clock-names = "mm", "mfg", "ethif"; +- }; +- +- watchdog: watchdog@10007000 { +- compatible = "mediatek,mt7623-wdt", +- "mediatek,mt6589-wdt"; +- reg = <0 0x10007000 0 0x100>; +- }; +- +- timer: timer@10008000 { +- compatible = "mediatek,mt7623-timer", +- "mediatek,mt6577-timer"; +- reg = <0 0x10008000 0 0x80>; +- interrupts = ; +- clocks = <&system_clk>, <&rtc32k>; +- clock-names = "system-clk", "rtc-clk"; +- }; +- +- pwrap: pwrap@1000d000 { +- compatible = "mediatek,mt7623-pwrap", +- "mediatek,mt2701-pwrap"; +- reg = <0 0x1000d000 0 0x1000>; +- reg-names = "pwrap"; +- interrupts = ; +- resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>; +- reset-names = "pwrap"; +- clocks = <&infracfg CLK_INFRA_PMICSPI>, +- <&infracfg CLK_INFRA_PMICWRAP>; +- clock-names = "spi", "wrap"; +- }; +- +- cir: cir@10013000 { +- compatible = "mediatek,mt7623-cir"; +- reg = <0 0x10013000 0 0x1000>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_IRRX>; +- clock-names = "clk"; +- status = "disabled"; +- }; +- +- sysirq: interrupt-controller@10200100 { +- compatible = "mediatek,mt7623-sysirq", +- "mediatek,mt6577-sysirq"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0 0x10200100 0 0x1c>; +- }; +- +- efuse: efuse@10206000 { +- compatible = "mediatek,mt7623-efuse", +- "mediatek,mt8173-efuse"; +- reg = <0 0x10206000 0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- thermal_calibration_data: calib@424 { +- reg = <0x424 0xc>; +- }; +- }; +- +- apmixedsys: syscon@10209000 { +- compatible = "mediatek,mt7623-apmixedsys", +- "mediatek,mt2701-apmixedsys", +- "syscon"; +- reg = <0 0x10209000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- rng: rng@1020f000 { +- compatible = "mediatek,mt7623-rng"; +- reg = <0 0x1020f000 0 0x1000>; +- clocks = <&infracfg CLK_INFRA_TRNG>; +- clock-names = "rng"; +- }; +- +- gic: interrupt-controller@10211000 { +- compatible = "arm,cortex-a7-gic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0 0x10211000 0 0x1000>, +- <0 0x10212000 0 0x2000>, +- <0 0x10214000 0 0x2000>, +- <0 0x10216000 0 0x2000>; +- }; +- +- auxadc: adc@11001000 { +- compatible = "mediatek,mt7623-auxadc", +- "mediatek,mt2701-auxadc"; +- reg = <0 0x11001000 0 0x1000>; +- clocks = <&pericfg CLK_PERI_AUXADC>; +- clock-names = "main"; +- #io-channel-cells = <1>; +- }; +- +- uart0: serial@11002000 { +- compatible = "mediatek,mt7623-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11002000 0 0x400>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_UART0_SEL>, +- <&pericfg CLK_PERI_UART0>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart1: serial@11003000 { +- compatible = "mediatek,mt7623-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11003000 0 0x400>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_UART1_SEL>, +- <&pericfg CLK_PERI_UART1>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart2: serial@11004000 { +- compatible = "mediatek,mt7623-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11004000 0 0x400>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_UART2_SEL>, +- <&pericfg CLK_PERI_UART2>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart3: serial@11005000 { +- compatible = "mediatek,mt7623-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11005000 0 0x400>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_UART3_SEL>, +- <&pericfg CLK_PERI_UART3>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- pwm: pwm@11006000 { +- compatible = "mediatek,mt7623-pwm"; +- reg = <0 0x11006000 0 0x1000>; +- #pwm-cells = <2>; +- clocks = <&topckgen CLK_TOP_PWM_SEL>, +- <&pericfg CLK_PERI_PWM>, +- <&pericfg CLK_PERI_PWM1>, +- <&pericfg CLK_PERI_PWM2>, +- <&pericfg CLK_PERI_PWM3>, +- <&pericfg CLK_PERI_PWM4>, +- <&pericfg CLK_PERI_PWM5>; +- clock-names = "top", "main", "pwm1", "pwm2", +- "pwm3", "pwm4", "pwm5"; +- status = "disabled"; +- }; +- +- i2c0: i2c@11007000 { +- compatible = "mediatek,mt7623-i2c", +- "mediatek,mt6577-i2c"; +- reg = <0 0x11007000 0 0x70>, +- <0 0x11000200 0 0x80>; +- interrupts = ; +- clock-div = <16>; +- clocks = <&pericfg CLK_PERI_I2C0>, +- <&pericfg CLK_PERI_AP_DMA>; +- clock-names = "main", "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@11008000 { +- compatible = "mediatek,mt7623-i2c", +- "mediatek,mt6577-i2c"; +- reg = <0 0x11008000 0 0x70>, +- <0 0x11000280 0 0x80>; +- interrupts = ; +- clock-div = <16>; +- clocks = <&pericfg CLK_PERI_I2C1>, +- <&pericfg CLK_PERI_AP_DMA>; +- clock-names = "main", "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@11009000 { +- compatible = "mediatek,mt7623-i2c", +- "mediatek,mt6577-i2c"; +- reg = <0 0x11009000 0 0x70>, +- <0 0x11000300 0 0x80>; +- interrupts = ; +- clock-div = <16>; +- clocks = <&pericfg CLK_PERI_I2C2>, +- <&pericfg CLK_PERI_AP_DMA>; +- clock-names = "main", "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi0: spi@1100a000 { +- compatible = "mediatek,mt7623-spi", +- "mediatek,mt2701-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x1100a000 0 0x100>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, +- <&topckgen CLK_TOP_SPI0_SEL>, +- <&pericfg CLK_PERI_SPI0>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- thermal: thermal@1100b000 { +- #thermal-sensor-cells = <1>; +- compatible = "mediatek,mt7623-thermal", +- "mediatek,mt2701-thermal"; +- reg = <0 0x1100b000 0 0x1000>; +- interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; +- clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; +- clock-names = "therm", "auxadc"; +- resets = <&pericfg MT2701_PERI_THERM_SW_RST>; +- reset-names = "therm"; +- mediatek,auxadc = <&auxadc>; +- mediatek,apmixedsys = <&apmixedsys>; +- nvmem-cells = <&thermal_calibration_data>; +- nvmem-cell-names = "calibration-data"; +- }; +- +- btif: serial@1100c000 { +- compatible = "mediatek,mt7623-btif", +- "mediatek,mtk-btif"; +- reg = <0 0x1100c000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_BTIF>; +- clock-names = "main"; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- nandc: nfi@1100d000 { +- compatible = "mediatek,mt7623-nfc", +- "mediatek,mt2701-nfc"; +- reg = <0 0x1100d000 0 0x1000>; +- interrupts = ; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; +- clocks = <&pericfg CLK_PERI_NFI>, +- <&pericfg CLK_PERI_NFI_PAD>; +- clock-names = "nfi_clk", "pad_clk"; +- status = "disabled"; +- ecc-engine = <&bch>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- bch: ecc@1100e000 { +- compatible = "mediatek,mt7623-ecc", +- "mediatek,mt2701-ecc"; +- reg = <0 0x1100e000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_NFI_ECC>; +- clock-names = "nfiecc_clk"; +- status = "disabled"; +- }; +- +- nor_flash: spi@11014000 { +- compatible = "mediatek,mt7623-nor", +- "mediatek,mt8173-nor"; +- reg = <0 0x11014000 0 0x1000>; +- clocks = <&pericfg CLK_PERI_FLASH>, +- <&topckgen CLK_TOP_FLASH_SEL>; +- clock-names = "spi", "sf"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi1: spi@11016000 { +- compatible = "mediatek,mt7623-spi", +- "mediatek,mt2701-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x11016000 0 0x100>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, +- <&topckgen CLK_TOP_SPI1_SEL>, +- <&pericfg CLK_PERI_SPI1>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- spi2: spi@11017000 { +- compatible = "mediatek,mt7623-spi", +- "mediatek,mt2701-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x11017000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, +- <&topckgen CLK_TOP_SPI2_SEL>, +- <&pericfg CLK_PERI_SPI2>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- audsys: clock-controller@11220000 { +- compatible = "mediatek,mt7623-audsys", +- "mediatek,mt2701-audsys", +- "syscon"; +- reg = <0 0x11220000 0 0x2000>; +- #clock-cells = <1>; +- +- afe: audio-controller { +- compatible = "mediatek,mt7623-audio", +- "mediatek,mt2701-audio"; +- interrupts = , +- ; +- interrupt-names = "afe", "asys"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; +- +- clocks = <&infracfg CLK_INFRA_AUDIO>, +- <&topckgen CLK_TOP_AUD_MUX1_SEL>, +- <&topckgen CLK_TOP_AUD_MUX2_SEL>, +- <&topckgen CLK_TOP_AUD_48K_TIMING>, +- <&topckgen CLK_TOP_AUD_44K_TIMING>, +- <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, +- <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, +- <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, +- <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, +- <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, +- <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, +- <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, +- <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, +- <&topckgen CLK_TOP_AUD_I2S1_MCLK>, +- <&topckgen CLK_TOP_AUD_I2S2_MCLK>, +- <&topckgen CLK_TOP_AUD_I2S3_MCLK>, +- <&topckgen CLK_TOP_AUD_I2S4_MCLK>, +- <&audsys CLK_AUD_I2SO1>, +- <&audsys CLK_AUD_I2SO2>, +- <&audsys CLK_AUD_I2SO3>, +- <&audsys CLK_AUD_I2SO4>, +- <&audsys CLK_AUD_I2SIN1>, +- <&audsys CLK_AUD_I2SIN2>, +- <&audsys CLK_AUD_I2SIN3>, +- <&audsys CLK_AUD_I2SIN4>, +- <&audsys CLK_AUD_ASRCO1>, +- <&audsys CLK_AUD_ASRCO2>, +- <&audsys CLK_AUD_ASRCO3>, +- <&audsys CLK_AUD_ASRCO4>, +- <&audsys CLK_AUD_AFE>, +- <&audsys CLK_AUD_AFE_CONN>, +- <&audsys CLK_AUD_A1SYS>, +- <&audsys CLK_AUD_A2SYS>, +- <&audsys CLK_AUD_AFE_MRGIF>; +- +- clock-names = "infra_sys_audio_clk", +- "top_audio_mux1_sel", +- "top_audio_mux2_sel", +- "top_audio_a1sys_hp", +- "top_audio_a2sys_hp", +- "i2s0_src_sel", +- "i2s1_src_sel", +- "i2s2_src_sel", +- "i2s3_src_sel", +- "i2s0_src_div", +- "i2s1_src_div", +- "i2s2_src_div", +- "i2s3_src_div", +- "i2s0_mclk_en", +- "i2s1_mclk_en", +- "i2s2_mclk_en", +- "i2s3_mclk_en", +- "i2so0_hop_ck", +- "i2so1_hop_ck", +- "i2so2_hop_ck", +- "i2so3_hop_ck", +- "i2si0_hop_ck", +- "i2si1_hop_ck", +- "i2si2_hop_ck", +- "i2si3_hop_ck", +- "asrc0_out_ck", +- "asrc1_out_ck", +- "asrc2_out_ck", +- "asrc3_out_ck", +- "audio_afe_pd", +- "audio_afe_conn_pd", +- "audio_a1sys_pd", +- "audio_a2sys_pd", +- "audio_mrgif_pd"; +- +- assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, +- <&topckgen CLK_TOP_AUD_MUX2_SEL>, +- <&topckgen CLK_TOP_AUD_MUX1_DIV>, +- <&topckgen CLK_TOP_AUD_MUX2_DIV>; +- assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, +- <&topckgen CLK_TOP_AUD2PLL_90M>; +- assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; +- }; +- }; +- +- mmc0: mmc@11230000 { +- compatible = "mediatek,mt7623-mmc", +- "mediatek,mt2701-mmc"; +- reg = <0 0x11230000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_MSDC30_0>, +- <&topckgen CLK_TOP_MSDC30_0_SEL>; +- clock-names = "source", "hclk"; +- status = "disabled"; +- }; +- +- mmc1: mmc@11240000 { +- compatible = "mediatek,mt7623-mmc", +- "mediatek,mt2701-mmc"; +- reg = <0 0x11240000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_MSDC30_1>, +- <&topckgen CLK_TOP_MSDC30_1_SEL>; +- clock-names = "source", "hclk"; +- status = "disabled"; +- }; +- +- vdecsys: syscon@16000000 { +- compatible = "mediatek,mt7623-vdecsys", +- "mediatek,mt2701-vdecsys", +- "syscon"; +- reg = <0 0x16000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- hifsys: syscon@1a000000 { +- compatible = "mediatek,mt7623-hifsys", +- "mediatek,mt2701-hifsys", +- "syscon"; +- reg = <0 0x1a000000 0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pcie: pcie@1a140000 { +- compatible = "mediatek,mt7623-pcie"; +- device_type = "pci"; +- reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ +- <0 0x1a142000 0 0x1000>, /* Port0 registers */ +- <0 0x1a143000 0 0x1000>, /* Port1 registers */ +- <0 0x1a144000 0 0x1000>; /* Port2 registers */ +- reg-names = "subsys", "port0", "port1", "port2"; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0xf800 0 0 0>; +- interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, +- <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, +- <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; +- clocks = <&topckgen CLK_TOP_ETHIF_SEL>, +- <&hifsys CLK_HIFSYS_PCIE0>, +- <&hifsys CLK_HIFSYS_PCIE1>, +- <&hifsys CLK_HIFSYS_PCIE2>; +- clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; +- resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, +- <&hifsys MT2701_HIFSYS_PCIE1_RST>, +- <&hifsys MT2701_HIFSYS_PCIE2_RST>; +- reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; +- phys = <&pcie0_port PHY_TYPE_PCIE>, +- <&pcie1_port PHY_TYPE_PCIE>, +- <&u3port1 PHY_TYPE_PCIE>; +- phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; +- bus-range = <0x00 0xff>; +- status = "disabled"; +- ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 +- 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; +- +- pcie@0,0 { +- reg = <0x0000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; +- ranges; +- status = "disabled"; +- }; +- +- pcie@1,0 { +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; +- ranges; +- status = "disabled"; +- }; +- +- pcie@2,0 { +- reg = <0x1000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; +- ranges; +- status = "disabled"; +- }; +- }; +- +- pcie0_phy: t-phy@1a149000 { +- compatible = "mediatek,mt7623-tphy", +- "mediatek,generic-tphy-v1"; +- reg = <0 0x1a149000 0 0x0700>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "disabled"; +- +- pcie0_port: pcie-phy@1a149900 { +- reg = <0 0x1a149900 0 0x0700>; +- clocks = <&clk26m>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- }; +- +- pcie1_phy: t-phy@1a14a000 { +- compatible = "mediatek,mt7623-tphy", +- "mediatek,generic-tphy-v1"; +- reg = <0 0x1a14a000 0 0x0700>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "disabled"; +- +- pcie1_port: pcie-phy@1a14a900 { +- reg = <0 0x1a14a900 0 0x0700>; +- clocks = <&clk26m>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- }; +- +- usb1: usb@1a1c0000 { +- compatible = "mediatek,mt7623-xhci", +- "mediatek,mtk-xhci"; +- reg = <0 0x1a1c0000 0 0x1000>, +- <0 0x1a1c4700 0 0x0100>; +- reg-names = "mac", "ippc"; +- interrupts = ; +- clocks = <&hifsys CLK_HIFSYS_USB0PHY>, +- <&topckgen CLK_TOP_ETHIF_SEL>; +- clock-names = "sys_ck", "ref_ck"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; +- phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; +- status = "disabled"; +- }; +- +- u3phy1: t-phy@1a1c4000 { +- compatible = "mediatek,mt7623-tphy", +- "mediatek,generic-tphy-v1"; +- reg = <0 0x1a1c4000 0 0x0700>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "disabled"; +- +- u2port0: usb-phy@1a1c4800 { +- reg = <0 0x1a1c4800 0 0x0100>; +- clocks = <&topckgen CLK_TOP_USB_PHY48M>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- +- u3port0: usb-phy@1a1c4900 { +- reg = <0 0x1a1c4900 0 0x0700>; +- clocks = <&clk26m>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- }; +- +- usb2: usb@1a240000 { +- compatible = "mediatek,mt7623-xhci", +- "mediatek,mtk-xhci"; +- reg = <0 0x1a240000 0 0x1000>, +- <0 0x1a244700 0 0x0100>; +- reg-names = "mac", "ippc"; +- interrupts = ; +- clocks = <&hifsys CLK_HIFSYS_USB1PHY>, +- <&topckgen CLK_TOP_ETHIF_SEL>; +- clock-names = "sys_ck", "ref_ck"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; +- phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; +- status = "disabled"; +- }; +- +- u3phy2: t-phy@1a244000 { +- compatible = "mediatek,mt7623-tphy", +- "mediatek,generic-tphy-v1"; +- reg = <0 0x1a244000 0 0x0700>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "disabled"; +- +- u2port1: usb-phy@1a244800 { +- reg = <0 0x1a244800 0 0x0100>; +- clocks = <&topckgen CLK_TOP_USB_PHY48M>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- +- u3port1: usb-phy@1a244900 { +- reg = <0 0x1a244900 0 0x0700>; +- clocks = <&clk26m>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- }; +- +- ethsys: syscon@1b000000 { +- compatible = "mediatek,mt7623-ethsys", +- "mediatek,mt2701-ethsys", +- "syscon"; +- reg = <0 0x1b000000 0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- hsdma: dma-controller@1b007000 { +- compatible = "mediatek,mt7623-hsdma"; +- reg = <0 0x1b007000 0 0x1000>; +- interrupts = ; +- clocks = <ðsys CLK_ETHSYS_HSDMA>; +- clock-names = "hsdma"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; +- #dma-cells = <1>; +- }; +- +- eth: ethernet@1b100000 { +- compatible = "mediatek,mt7623-eth", +- "mediatek,mt2701-eth", +- "syscon"; +- reg = <0 0x1b100000 0 0x20000>; +- interrupts = , +- , +- ; +- clocks = <&topckgen CLK_TOP_ETHIF_SEL>, +- <ðsys CLK_ETHSYS_ESW>, +- <ðsys CLK_ETHSYS_GP1>, +- <ðsys CLK_ETHSYS_GP2>, +- <&apmixedsys CLK_APMIXED_TRGPLL>; +- clock-names = "ethif", "esw", "gp1", "gp2", "trgpll"; +- resets = <ðsys MT2701_ETHSYS_FE_RST>, +- <ðsys MT2701_ETHSYS_GMAC_RST>, +- <ðsys MT2701_ETHSYS_PPE_RST>; +- reset-names = "fe", "gmac", "ppe"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; +- mediatek,ethsys = <ðsys>; +- mediatek,pctl = <&syscfg_pctl_a>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- crypto: crypto@1b240000 { +- compatible = "mediatek,eip97-crypto"; +- reg = <0 0x1b240000 0 0x20000>; +- interrupts = , +- , +- , +- , +- ; +- clocks = <ðsys CLK_ETHSYS_CRYPTO>; +- clock-names = "cryp"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; +- status = "disabled"; +- }; +- +- bdpsys: syscon@1c000000 { +- compatible = "mediatek,mt7623-bdpsys", +- "mediatek,mt2701-bdpsys", +- "syscon"; +- reg = <0 0x1c000000 0 0x1000>; +- #clock-cells = <1>; +- }; +-}; +- +-&pio { +- cir_pins_a:cir-default { +- pins-cir { +- pinmux = ; +- bias-disable; +- }; +- }; +- +- i2c0_pins_a: i2c0-default { +- pins-i2c0 { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- i2c1_pins_a: i2c1-default { +- pin-i2c1 { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- i2c1_pins_b: i2c1-alt { +- pin-i2c1 { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- i2c2_pins_a: i2c2-default { +- pin-i2c2 { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- i2c2_pins_b: i2c2-alt { +- pin-i2c2 { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- i2s0_pins_a: i2s0-default { +- pin-i2s0 { +- pinmux = , +- , +- , +- , +- ; +- drive-strength = ; +- bias-pull-down; +- }; +- }; +- +- i2s1_pins_a: i2s1-default { +- pin-i2s1 { +- pinmux = , +- , +- , +- , +- ; +- drive-strength = ; +- bias-pull-down; +- }; +- }; +- +- key_pins_a: keys-alt { +- pins-keys { +- pinmux = , +- ; +- input-enable; +- }; +- }; +- +- led_pins_a: leds-alt { +- pins-leds { +- pinmux = , +- , +- ; +- }; +- }; +- +- mmc0_pins_default: mmc0default { +- pins-cmd-dat { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- ; +- input-enable; +- bias-pull-up; +- }; +- +- pins-clk { +- pinmux = ; +- bias-pull-down; +- }; +- +- pins-rst { +- pinmux = ; +- bias-pull-up; +- }; +- }; +- +- mmc0_pins_uhs: mmc0 { +- pins-cmd-dat { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- ; +- input-enable; +- drive-strength = ; +- bias-pull-up = ; +- }; +- +- pins-clk { +- pinmux = ; +- drive-strength = ; +- bias-pull-down = ; +- }; +- +- pins-rst { +- pinmux = ; +- bias-pull-up; +- }; +- }; +- +- mmc1_pins_default: mmc1default { +- pins-cmd-dat { +- pinmux = , +- , +- , +- , +- ; +- input-enable; +- drive-strength = ; +- bias-pull-up = ; +- }; +- +- pins-clk { +- pinmux = ; +- bias-pull-down; +- drive-strength = ; +- }; +- +- pins-wp { +- pinmux = ; +- input-enable; +- bias-pull-up; +- }; +- +- pins-insert { +- pinmux = ; +- bias-pull-up; +- }; +- }; +- +- mmc1_pins_uhs: mmc1 { +- pins-cmd-dat { +- pinmux = , +- , +- , +- , +- ; +- input-enable; +- drive-strength = ; +- bias-pull-up = ; +- }; +- +- pins-clk { +- pinmux = ; +- drive-strength = ; +- bias-pull-down = ; +- }; +- }; +- +- nand_pins_default: nanddefault { +- pins-ale { +- pinmux = ; +- drive-strength = ; +- bias-pull-down = ; +- }; +- +- pins-dat { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- ; +- input-enable; +- drive-strength = ; +- bias-pull-up; +- }; +- +- pins-we { +- pinmux = ; +- drive-strength = ; +- bias-pull-up = ; +- }; +- }; +- +- pcie_default: pcie_pin_default { +- pins_cmd_dat { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- pwm_pins_a: pwm-default { +- pins-pwm { +- pinmux = , +- , +- , +- , +- ; +- }; +- }; +- +- spi0_pins_a: spi0-default { +- pins-spi { +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- }; +- +- spi1_pins_a: spi1-default { +- pins-spi { +- pinmux = , +- , +- , +- ; +- }; +- }; +- +- spi2_pins_a: spi2-default { +- pins-spi { +- pinmux = , +- , +- , +- ; +- }; +- }; +- +- uart0_pins_a: uart0-default { +- pins-dat { +- pinmux = , +- ; +- }; +- }; +- +- uart1_pins_a: uart1-default { +- pins-dat { +- pinmux = , +- ; +- }; +- }; +- +- uart2_pins_a: uart2-default { +- pins-dat { +- pinmux = , +- ; +- }; +- }; +- +- uart2_pins_b: uart2-alt { +- pins-dat { +- pinmux = , +- ; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt7623a-rfb-emmc.dts b/scripts/dtc/include-prefixes/arm/mt7623a-rfb-emmc.dts +deleted file mode 100644 +index 13c86936d1c8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt7623a-rfb-emmc.dts ++++ /dev/null +@@ -1,291 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2017-2018 MediaTek Inc. +- * Author: Sean Wang +- * +- */ +- +-/dts-v1/; +-#include +-#include "mt7623a.dtsi" +-#include "mt6323.dtsi" +- +-/ { +- model = "MediaTek MT7623A with eMMC reference board"; +- compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623"; +- +- aliases { +- serial2 = &uart2; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- cpus { +- cpu@0 { +- proc-supply = <&mt6323_vproc_reg>; +- }; +- +- cpu@1 { +- proc-supply = <&mt6323_vproc_reg>; +- }; +- +- cpu@2 { +- proc-supply = <&mt6323_vproc_reg>; +- }; +- +- cpu@3 { +- proc-supply = <&mt6323_vproc_reg>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&key_pins_a>; +- +- factory { +- label = "factory"; +- linux,code = ; +- gpios = <&pio 256 GPIO_ACTIVE_LOW>; +- }; +- +- wps { +- label = "wps"; +- linux,code = ; +- gpios = <&pio 257 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0 0x80000000 0 0x20000000>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_5v: regulator-5v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sound { +- compatible = "mediatek,mt2701-wm8960-machine"; +- mediatek,platform = <&afe>; +- audio-routing = +- "Headphone", "HP_L", +- "Headphone", "HP_R", +- "LINPUT1", "AMIC", +- "RINPUT1", "AMIC"; +- mediatek,audio-codec = <&wm8960>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s0_pins_a>; +- }; +-}; +- +-&btif { +- status = "okay"; +-}; +- +-&crypto { +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "trgmii"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- pause; +- }; +- }; +- +- mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch@0 { +- compatible = "mediatek,mt7530"; +- reg = <0>; +- mediatek,mcm; +- resets = <ðsys MT2701_ETHSYS_MCM_RST>; +- reset-names = "mcm"; +- core-supply = <&mt6323_vpa_reg>; +- io-supply = <&mt6323_vemc3v3_reg>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan0"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan1"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan3"; +- }; +- +- port@4 { +- reg = <4>; +- label = "wan"; +- }; +- +- port@6 { +- reg = <6>; +- label = "cpu"; +- ethernet = <&gmac0>; +- phy-mode = "trgmii"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_a>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins_b>; +- status = "okay"; +- +- wm8960: wm8960@1a { +- compatible = "wlf,wm8960"; +- reg = <0x1a>; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins_b>; +- status = "okay"; +-}; +- +-&mmc0 { +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc0_pins_default>; +- pinctrl-1 = <&mmc0_pins_uhs>; +- status = "okay"; +- bus-width = <8>; +- max-frequency = <50000000>; +- cap-mmc-highspeed; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_1p8v>; +- non-removable; +-}; +- +-&mmc1 { +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc1_pins_default>; +- pinctrl-1 = <&mmc1_pins_uhs>; +- status = "okay"; +- bus-width = <4>; +- max-frequency = <50000000>; +- cap-sd-highspeed; +- cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_3p3v>; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_default>; +- status = "okay"; +- +- pcie@0,0 { +- status = "okay"; +- }; +- +- pcie@1,0 { +- status = "okay"; +- }; +-}; +- +-&pcie0_phy { +- status = "okay"; +-}; +- +-&pcie1_phy { +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm_pins_a>; +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins_a>; +- status = "okay"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins_a>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins_b>; +- status = "okay"; +-}; +- +-&usb1 { +- vusb33-supply = <®_3p3v>; +- vbus-supply = <®_5v>; +- status = "okay"; +-}; +- +-&u3phy1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt7623a-rfb-nand.dts b/scripts/dtc/include-prefixes/arm/mt7623a-rfb-nand.dts +deleted file mode 100644 +index 88d8f0b2f4c2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt7623a-rfb-nand.dts ++++ /dev/null +@@ -1,337 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2017-2018 MediaTek Inc. +- * Author: Sean Wang +- * +- */ +- +-/dts-v1/; +-#include +-#include "mt7623a.dtsi" +-#include "mt6323.dtsi" +- +-/ { +- model = "MediaTek MT7623A with NAND reference board"; +- compatible = "mediatek,mt7623a-rfb-nand", "mediatek,mt7623"; +- +- aliases { +- serial2 = &uart2; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- cpus { +- cpu@0 { +- proc-supply = <&mt6323_vproc_reg>; +- }; +- +- cpu@1 { +- proc-supply = <&mt6323_vproc_reg>; +- }; +- +- cpu@2 { +- proc-supply = <&mt6323_vproc_reg>; +- }; +- +- cpu@3 { +- proc-supply = <&mt6323_vproc_reg>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&key_pins_a>; +- +- factory { +- label = "factory"; +- linux,code = ; +- gpios = <&pio 256 GPIO_ACTIVE_LOW>; +- }; +- +- wps { +- label = "wps"; +- linux,code = ; +- gpios = <&pio 257 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0 0x80000000 0 0x20000000>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_5v: regulator-5v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sound { +- compatible = "mediatek,mt2701-wm8960-machine"; +- mediatek,platform = <&afe>; +- audio-routing = +- "Headphone", "HP_L", +- "Headphone", "HP_R", +- "LINPUT1", "AMIC", +- "RINPUT1", "AMIC"; +- mediatek,audio-codec = <&wm8960>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s0_pins_a>; +- }; +-}; +- +-&bch { +- status = "okay"; +-}; +- +-&btif { +- status = "okay"; +-}; +- +-&crypto { +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "trgmii"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- pause; +- }; +- }; +- +- mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch@0 { +- compatible = "mediatek,mt7530"; +- reg = <0>; +- mediatek,mcm; +- resets = <ðsys MT2701_ETHSYS_MCM_RST>; +- reset-names = "mcm"; +- core-supply = <&mt6323_vpa_reg>; +- io-supply = <&mt6323_vemc3v3_reg>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan0"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan1"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan3"; +- }; +- +- port@4 { +- reg = <4>; +- label = "wan"; +- }; +- +- port@6 { +- reg = <6>; +- label = "cpu"; +- ethernet = <&gmac0>; +- phy-mode = "trgmii"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_a>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins_b>; +- status = "okay"; +- +- wm8960: wm8960@1a { +- compatible = "wlf,wm8960"; +- reg = <0x1a>; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins_b>; +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc1_pins_default>; +- pinctrl-1 = <&mmc1_pins_uhs>; +- status = "okay"; +- bus-width = <4>; +- max-frequency = <50000000>; +- cap-sd-highspeed; +- cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_3p3v>; +-}; +- +-&nandc { +- pinctrl-names = "default"; +- pinctrl-0 = <&nand_pins_default>; +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- spare_per_sector = <64>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <12>; +- nand-ecc-step-size = <1024>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "preloader"; +- reg = <0x0 0x40000>; +- }; +- +- partition@40000 { +- label = "uboot"; +- reg = <0x40000 0x80000>; +- }; +- +- partition@c0000 { +- label = "uboot-env"; +- reg = <0xC0000 0x40000>; +- }; +- +- partition@140000 { +- label = "bootimg"; +- reg = <0x140000 0x2000000>; +- }; +- +- partition@2140000 { +- label = "recovery"; +- reg = <0x2140000 0x2000000>; +- }; +- +- partition@4140000 { +- label = "rootfs"; +- reg = <0x4140000 0x1000000>; +- }; +- +- partition@5140000 { +- label = "usrdata"; +- reg = <0x5140000 0x1000000>; +- }; +- }; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_default>; +- status = "okay"; +- +- pcie@0,0 { +- status = "okay"; +- }; +- +- pcie@1,0 { +- status = "okay"; +- }; +-}; +- +-&pcie0_phy { +- status = "okay"; +-}; +- +-&pcie1_phy { +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm_pins_a>; +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins_a>; +- status = "okay"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins_a>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins_b>; +- status = "okay"; +-}; +- +-&usb1 { +- vusb33-supply = <®_3p3v>; +- vbus-supply = <®_5v>; +- status = "okay"; +-}; +- +-&u3phy1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt7623a.dtsi b/scripts/dtc/include-prefixes/arm/mt7623a.dtsi +deleted file mode 100644 +index 0735a1fb8ad9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt7623a.dtsi ++++ /dev/null +@@ -1,44 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2017-2018 MediaTek Inc. +- * Author: Sean Wang +- * +- */ +- +-/dts-v1/; +-#include +-#include "mt7623.dtsi" +- +-&afe { +- power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; +-}; +- +-&crypto { +- power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>; +-}; +- +-ð { +- power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>; +-}; +- +-&nandc { +- power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; +-}; +- +-&pcie { +- power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; +-}; +- +-&scpsys { +- compatible = "mediatek,mt7623a-scpsys"; +- clocks = <&topckgen CLK_TOP_ETHIF_SEL>; +- clock-names = "ethif"; +-}; +- +-&usb1 { +- power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; +-}; +- +-&usb2 { +- power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt7623n-bananapi-bpi-r2.dts b/scripts/dtc/include-prefixes/arm/mt7623n-bananapi-bpi-r2.dts +deleted file mode 100644 +index e96aa0ed1ebd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt7623n-bananapi-bpi-r2.dts ++++ /dev/null +@@ -1,417 +0,0 @@ +-/* +- * Copyright 2017-2018 Sean Wang +- * +- * SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- */ +- +-/dts-v1/; +-#include +-#include "mt7623n.dtsi" +-#include "mt6323.dtsi" +- +-/ { +- model = "Bananapi BPI-R2"; +- compatible = "bananapi,bpi-r2", "mediatek,mt7623"; +- +- aliases { +- serial2 = &uart2; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- label = "hdmi"; +- type = "d"; +- ddc-i2c-bus = <&hdmiddc0>; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi0_out>; +- }; +- }; +- }; +- +- cpus { +- cpu@0 { +- proc-supply = <&mt6323_vproc_reg>; +- }; +- +- cpu@1 { +- proc-supply = <&mt6323_vproc_reg>; +- }; +- +- cpu@2 { +- proc-supply = <&mt6323_vproc_reg>; +- }; +- +- cpu@3 { +- proc-supply = <&mt6323_vproc_reg>; +- }; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_5v: regulator-5v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_vgpu: fixedregulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_fixed_vgpu"; +- regulator-min-microvolt = <1150000>; +- regulator-max-microvolt = <1150000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&key_pins_a>; +- +- factory { +- label = "factory"; +- linux,code = ; +- gpios = <&pio 256 GPIO_ACTIVE_LOW>; +- }; +- +- wps { +- label = "wps"; +- linux,code = ; +- gpios = <&pio 257 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins_a>; +- +- blue { +- label = "bpi-r2:pio:blue"; +- gpios = <&pio 240 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- green { +- label = "bpi-r2:pio:green"; +- gpios = <&pio 241 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- red { +- label = "bpi-r2:pio:red"; +- gpios = <&pio 239 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0 0x80000000 0 0x80000000>; +- }; +-}; +- +-&bls { +- status = "okay"; +-}; +- +-&btif { +- status = "okay"; +-}; +- +-&cec { +- status = "okay"; +-}; +- +-&cir { +- pinctrl-names = "default"; +- pinctrl-0 = <&cir_pins_a>; +- status = "okay"; +-}; +- +-&crypto { +- status = "okay"; +-}; +- +-&dpi0 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- dpi0_out: endpoint { +- remote-endpoint = <&hdmi0_in>; +- }; +- }; +- }; +-}; +- +-ð { +- status = "okay"; +- +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "trgmii"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- pause; +- }; +- }; +- +- mdio: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch@0 { +- compatible = "mediatek,mt7530"; +- reg = <0>; +- reset-gpios = <&pio 33 0>; +- core-supply = <&mt6323_vpa_reg>; +- io-supply = <&mt6323_vemc3v3_reg>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "wan"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan0"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan1"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan2"; +- }; +- +- port@4 { +- reg = <4>; +- label = "lan3"; +- }; +- +- port@6 { +- reg = <6>; +- label = "cpu"; +- ethernet = <&gmac0>; +- phy-mode = "trgmii"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- pause; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&hdmi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_pins_a>; +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- hdmi0_in: endpoint { +- remote-endpoint = <&dpi0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- hdmi0_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +- }; +- }; +-}; +- +-&hdmiddc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_ddc_pins_a>; +- status = "okay"; +-}; +- +-&hdmi_phy { +- mediatek,ibias = <0xa>; +- mediatek,ibias_up = <0x1c>; +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_a>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins_a>; +- status = "okay"; +-}; +- +-&mali { +- mali-supply = <®_vgpu>; +- status = "okay"; +-}; +- +-&mmc0 { +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc0_pins_default>; +- pinctrl-1 = <&mmc0_pins_uhs>; +- status = "okay"; +- bus-width = <8>; +- max-frequency = <50000000>; +- cap-mmc-highspeed; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_1p8v>; +- non-removable; +-}; +- +-&mmc1 { +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc1_pins_default>; +- pinctrl-1 = <&mmc1_pins_uhs>; +- status = "okay"; +- bus-width = <4>; +- max-frequency = <50000000>; +- cap-sd-highspeed; +- cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_3p3v>; +-}; +- +-&mt6323_leds { +- status = "okay"; +- +- led@0 { +- reg = <0>; +- label = "bpi-r2:isink:green"; +- default-state = "off"; +- }; +- +- led@1 { +- reg = <1>; +- label = "bpi-r2:isink:red"; +- default-state = "off"; +- }; +- +- led@2 { +- reg = <2>; +- label = "bpi-r2:isink:blue"; +- default-state = "off"; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_default>; +- status = "okay"; +- +- pcie@0,0 { +- status = "okay"; +- }; +- +- pcie@1,0 { +- status = "okay"; +- }; +-}; +- +-&pcie0_phy { +- status = "okay"; +-}; +- +-&pcie1_phy { +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm_pins_a>; +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins_a>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins_a>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins_a>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins_a>; +- status = "okay"; +-}; +- +-&usb1 { +- vusb33-supply = <®_3p3v>; +- vbus-supply = <®_5v>; +- status = "okay"; +-}; +- +-&usb2 { +- vusb33-supply = <®_3p3v>; +- vbus-supply = <®_5v>; +- status = "okay"; +-}; +- +-&u3phy1 { +- status = "okay"; +-}; +- +-&u3phy2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt7623n-rfb-emmc.dts b/scripts/dtc/include-prefixes/arm/mt7623n-rfb-emmc.dts +deleted file mode 100644 +index 1b9b9a8145a7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt7623n-rfb-emmc.dts ++++ /dev/null +@@ -1,399 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2017-2018 MediaTek Inc. +- * Author: Sean Wang +- * +- */ +- +-/dts-v1/; +-#include +-#include "mt7623n.dtsi" +-#include "mt6323.dtsi" +- +-/ { +- model = "MediaTek MT7623N with eMMC reference board"; +- compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- label = "hdmi"; +- type = "d"; +- ddc-i2c-bus = <&hdmiddc0>; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi0_out>; +- }; +- }; +- }; +- +- cpus { +- cpu@0 { +- proc-supply = <&mt6323_vproc_reg>; +- }; +- +- cpu@1 { +- proc-supply = <&mt6323_vproc_reg>; +- }; +- +- cpu@2 { +- proc-supply = <&mt6323_vproc_reg>; +- }; +- +- cpu@3 { +- proc-supply = <&mt6323_vproc_reg>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&key_pins_a>; +- +- factory { +- label = "factory"; +- linux,code = ; +- gpios = <&pio 256 GPIO_ACTIVE_LOW>; +- }; +- +- wps { +- label = "wps"; +- linux,code = ; +- gpios = <&pio 257 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0 0x80000000 0 0x40000000>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_5v: regulator-5v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sound { +- compatible = "mediatek,mt2701-wm8960-machine"; +- mediatek,platform = <&afe>; +- audio-routing = +- "Headphone", "HP_L", +- "Headphone", "HP_R", +- "LINPUT1", "AMIC", +- "RINPUT1", "AMIC"; +- mediatek,audio-codec = <&wm8960>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s0_pins_a>; +- }; +-}; +- +-&bls { +- status = "okay"; +-}; +- +-&btif { +- status = "okay"; +-}; +- +-&cec { +- status = "okay"; +-}; +- +-&cir { +- pinctrl-names = "default"; +- pinctrl-0 = <&cir_pins_a>; +- status = "okay"; +-}; +- +-&crypto { +- status = "okay"; +-}; +- +-&dpi0 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- dpi0_out: endpoint { +- remote-endpoint = <&hdmi0_in>; +- }; +- }; +- }; +-}; +- +-ð { +- status = "okay"; +- +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "trgmii"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- pause; +- }; +- }; +- +- mac@1 { +- compatible = "mediatek,eth-mac"; +- reg = <1>; +- phy-mode = "rgmii"; +- phy-handle = <&phy5>; +- }; +- +- mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy5: ethernet-phy@5 { +- reg = <5>; +- phy-mode = "rgmii-rxid"; +- }; +- +- switch@0 { +- compatible = "mediatek,mt7530"; +- reg = <0>; +- reset-gpios = <&pio 33 0>; +- core-supply = <&mt6323_vpa_reg>; +- io-supply = <&mt6323_vemc3v3_reg>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan0"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan1"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan3"; +- }; +- +- port@4 { +- reg = <4>; +- label = "wan"; +- }; +- +- port@6 { +- reg = <6>; +- label = "cpu"; +- ethernet = <&gmac0>; +- phy-mode = "trgmii"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&hdmi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_pins_a>; +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- hdmi0_in: endpoint { +- remote-endpoint = <&dpi0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- hdmi0_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +- }; +- }; +-}; +- +-&hdmiddc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_ddc_pins_a>; +- status = "okay"; +-}; +- +-&hdmi_phy { +- mediatek,ibias = <0xa>; +- mediatek,ibias_up = <0x1c>; +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_a>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins_b>; +- status = "okay"; +- +- wm8960: wm8960@1a { +- compatible = "wlf,wm8960"; +- reg = <0x1a>; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins_a>; +- status = "okay"; +-}; +- +-&mmc0 { +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc0_pins_default>; +- pinctrl-1 = <&mmc0_pins_uhs>; +- status = "okay"; +- bus-width = <8>; +- max-frequency = <50000000>; +- cap-mmc-highspeed; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_1p8v>; +- non-removable; +-}; +- +-&mmc1 { +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc1_pins_default>; +- pinctrl-1 = <&mmc1_pins_uhs>; +- status = "okay"; +- bus-width = <4>; +- max-frequency = <50000000>; +- cap-sd-highspeed; +- cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_3p3v>; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_default>; +- status = "okay"; +- +- pcie@0,0 { +- status = "okay"; +- }; +- +- pcie@1,0 { +- status = "okay"; +- }; +-}; +- +-&pcie0_phy { +- status = "okay"; +-}; +- +-&pcie1_phy { +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm_pins_a>; +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins_a>; +- status = "okay"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins_a>; +- status = "okay"; +-}; +- +-&spi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pins_a>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins_a>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins_a>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins_a>; +- status = "okay"; +-}; +- +-&usb1 { +- vusb33-supply = <®_3p3v>; +- vbus-supply = <®_5v>; +- status = "okay"; +-}; +- +-&u3phy1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt7623n.dtsi b/scripts/dtc/include-prefixes/arm/mt7623n.dtsi +deleted file mode 100644 +index bcb0846e29fd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt7623n.dtsi ++++ /dev/null +@@ -1,306 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright © 2017-2020 MediaTek Inc. +- * Author: Sean Wang +- * Ryder Lee +- * +- */ +- +-#include "mt7623.dtsi" +-#include +- +-/ { +- aliases { +- rdma0 = &rdma0; +- rdma1 = &rdma1; +- }; +- +- g3dsys: syscon@13000000 { +- compatible = "mediatek,mt7623-g3dsys", +- "mediatek,mt2701-g3dsys", +- "syscon"; +- reg = <0 0x13000000 0 0x200>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- mali: gpu@13040000 { +- compatible = "mediatek,mt7623-mali", "arm,mali-450"; +- reg = <0 0x13040000 0 0x30000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", +- "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3", +- "pp"; +- clocks = <&topckgen CLK_TOP_MMPLL>, +- <&g3dsys CLK_G3DSYS_CORE>; +- clock-names = "bus", "core"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>; +- resets = <&g3dsys MT2701_G3DSYS_CORE_RST>; +- }; +- +- mmsys: syscon@14000000 { +- compatible = "mediatek,mt7623-mmsys", +- "mediatek,mt2701-mmsys", +- "syscon"; +- reg = <0 0x14000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- larb0: larb@14010000 { +- compatible = "mediatek,mt7623-smi-larb", +- "mediatek,mt2701-smi-larb"; +- reg = <0 0x14010000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- mediatek,larb-id = <0>; +- clocks = <&mmsys CLK_MM_SMI_LARB0>, +- <&mmsys CLK_MM_SMI_LARB0>; +- clock-names = "apb", "smi"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; +- }; +- +- larb1: larb@16010000 { +- compatible = "mediatek,mt7623-smi-larb", +- "mediatek,mt2701-smi-larb"; +- reg = <0 0x16010000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- mediatek,larb-id = <1>; +- clocks = <&vdecsys CLK_VDEC_CKGEN>, +- <&vdecsys CLK_VDEC_LARB>; +- clock-names = "apb", "smi"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; +- }; +- +- larb2: larb@15001000 { +- compatible = "mediatek,mt7623-smi-larb", +- "mediatek,mt2701-smi-larb"; +- reg = <0 0x15001000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- mediatek,larb-id = <2>; +- clocks = <&imgsys CLK_IMG_SMI_COMM>, +- <&imgsys CLK_IMG_SMI_COMM>; +- clock-names = "apb", "smi"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; +- }; +- +- imgsys: syscon@15000000 { +- compatible = "mediatek,mt7623-imgsys", +- "mediatek,mt2701-imgsys", +- "syscon"; +- reg = <0 0x15000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- iommu: mmsys_iommu@10205000 { +- compatible = "mediatek,mt7623-m4u", +- "mediatek,mt2701-m4u"; +- reg = <0 0x10205000 0 0x1000>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_M4U>; +- clock-names = "bclk"; +- mediatek,larbs = <&larb0 &larb1 &larb2>; +- #iommu-cells = <1>; +- }; +- +- jpegdec: jpegdec@15004000 { +- compatible = "mediatek,mt7623-jpgdec", +- "mediatek,mt2701-jpgdec"; +- reg = <0 0x15004000 0 0x1000>; +- interrupts = ; +- clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, +- <&imgsys CLK_IMG_JPGDEC>; +- clock-names = "jpgdec-smi", +- "jpgdec"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; +- mediatek,larb = <&larb2>; +- iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, +- <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; +- }; +- +- smi_common: smi@1000c000 { +- compatible = "mediatek,mt7623-smi-common", +- "mediatek,mt2701-smi-common"; +- reg = <0 0x1000c000 0 0x1000>; +- clocks = <&infracfg CLK_INFRA_SMI>, +- <&mmsys CLK_MM_SMI_COMMON>, +- <&infracfg CLK_INFRA_SMI>; +- clock-names = "apb", "smi", "async"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; +- }; +- +- ovl: ovl@14007000 { +- compatible = "mediatek,mt7623-disp-ovl", +- "mediatek,mt2701-disp-ovl"; +- reg = <0 0x14007000 0 0x1000>; +- interrupts = ; +- clocks = <&mmsys CLK_MM_DISP_OVL>; +- iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>; +- mediatek,larb = <&larb0>; +- }; +- +- rdma0: rdma@14008000 { +- compatible = "mediatek,mt7623-disp-rdma", +- "mediatek,mt2701-disp-rdma"; +- reg = <0 0x14008000 0 0x1000>; +- interrupts = ; +- clocks = <&mmsys CLK_MM_DISP_RDMA>; +- iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>; +- mediatek,larb = <&larb0>; +- }; +- +- wdma@14009000 { +- compatible = "mediatek,mt7623-disp-wdma", +- "mediatek,mt2701-disp-wdma"; +- reg = <0 0x14009000 0 0x1000>; +- interrupts = ; +- clocks = <&mmsys CLK_MM_DISP_WDMA>; +- iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>; +- mediatek,larb = <&larb0>; +- }; +- +- bls: pwm@1400a000 { +- compatible = "mediatek,mt7623-disp-pwm", +- "mediatek,mt2701-disp-pwm"; +- reg = <0 0x1400a000 0 0x1000>; +- #pwm-cells = <2>; +- clocks = <&mmsys CLK_MM_MDP_BLS_26M>, +- <&mmsys CLK_MM_DISP_BLS>; +- clock-names = "main", "mm"; +- status = "disabled"; +- }; +- +- color: color@1400b000 { +- compatible = "mediatek,mt7623-disp-color", +- "mediatek,mt2701-disp-color"; +- reg = <0 0x1400b000 0 0x1000>; +- interrupts = ; +- clocks = <&mmsys CLK_MM_DISP_COLOR>; +- }; +- +- dsi: dsi@1400c000 { +- compatible = "mediatek,mt7623-dsi", +- "mediatek,mt2701-dsi"; +- reg = <0 0x1400c000 0 0x1000>; +- interrupts = ; +- clocks = <&mmsys CLK_MM_DSI_ENGINE>, +- <&mmsys CLK_MM_DSI_DIG>, +- <&mipi_tx0>; +- clock-names = "engine", "digital", "hs"; +- phys = <&mipi_tx0>; +- phy-names = "dphy"; +- status = "disabled"; +- }; +- +- mutex: mutex@1400e000 { +- compatible = "mediatek,mt7623-disp-mutex", +- "mediatek,mt2701-disp-mutex"; +- reg = <0 0x1400e000 0 0x1000>; +- interrupts = ; +- clocks = <&mmsys CLK_MM_MUTEX_32K>; +- }; +- +- rdma1: rdma@14012000 { +- compatible = "mediatek,mt7623-disp-rdma", +- "mediatek,mt2701-disp-rdma"; +- reg = <0 0x14012000 0 0x1000>; +- interrupts = ; +- clocks = <&mmsys CLK_MM_DISP_RDMA1>; +- iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>; +- mediatek,larb = <&larb0>; +- }; +- +- dpi0: dpi@14014000 { +- compatible = "mediatek,mt7623-dpi", +- "mediatek,mt2701-dpi"; +- reg = <0 0x14014000 0 0x1000>; +- interrupts = ; +- clocks = <&mmsys CLK_MM_DPI1_DIGL>, +- <&mmsys CLK_MM_DPI1_ENGINE>, +- <&apmixedsys CLK_APMIXED_TVDPLL>; +- clock-names = "pixel", "engine", "pll"; +- status = "disabled"; +- }; +- +- hdmi0: hdmi@14015000 { +- compatible = "mediatek,mt7623-hdmi", +- "mediatek,mt2701-hdmi"; +- reg = <0 0x14015000 0 0x400>; +- clocks = <&mmsys CLK_MM_HDMI_PIXEL>, +- <&mmsys CLK_MM_HDMI_PLL>, +- <&mmsys CLK_MM_HDMI_AUDIO>, +- <&mmsys CLK_MM_HDMI_SPDIF>; +- clock-names = "pixel", "pll", "bclk", "spdif"; +- phys = <&hdmi_phy>; +- phy-names = "hdmi"; +- mediatek,syscon-hdmi = <&mmsys 0x900>; +- cec = <&cec>; +- status = "disabled"; +- }; +- +- mipi_tx0: dsi-phy@10010000 { +- compatible = "mediatek,mt7623-mipi-tx", +- "mediatek,mt2701-mipi-tx"; +- reg = <0 0x10010000 0 0x90>; +- clocks = <&clk26m>; +- clock-output-names = "mipi_tx0_pll"; +- #clock-cells = <0>; +- #phy-cells = <0>; +- }; +- +- cec: cec@10012000 { +- compatible = "mediatek,mt7623-cec", +- "mediatek,mt8173-cec"; +- reg = <0 0x10012000 0 0xbc>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_CEC>; +- status = "disabled"; +- }; +- +- hdmi_phy: hdmi-phy@10209100 { +- compatible = "mediatek,mt7623-hdmi-phy", +- "mediatek,mt2701-hdmi-phy"; +- reg = <0 0x10209100 0 0x24>; +- clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; +- clock-names = "pll_ref"; +- clock-output-names = "hdmitx_dig_cts"; +- #clock-cells = <0>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- hdmiddc0: i2c@11013000 { +- compatible = "mediatek,mt7623-hdmi-ddc", +- "mediatek,mt8173-hdmi-ddc"; +- interrupts = ; +- reg = <0 0x11013000 0 0x1C>; +- clocks = <&pericfg CLK_PERI_I2C3>; +- clock-names = "ddc-i2c"; +- status = "disabled"; +- }; +-}; +- +-&pio { +- hdmi_pins_a: hdmi-default { +- pins-hdmi { +- pinmux = ; +- input-enable; +- bias-pull-down; +- }; +- }; +- +- hdmi_ddc_pins_a: hdmi_ddc-default { +- pins-hdmi-ddc { +- pinmux = , +- ; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt7629-rfb.dts b/scripts/dtc/include-prefixes/arm/mt7629-rfb.dts +deleted file mode 100644 +index 9980c10c6e29..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt7629-rfb.dts ++++ /dev/null +@@ -1,274 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019 MediaTek Inc. +- * Author: Ryder Lee +- */ +- +-/dts-v1/; +-#include +-#include "mt7629.dtsi" +- +-/ { +- model = "MediaTek MT7629 reference board"; +- compatible = "mediatek,mt7629-rfb", "mediatek,mt7629"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- reset { +- label = "factory"; +- linux,code = ; +- gpios = <&pio 60 GPIO_ACTIVE_LOW>; +- }; +- +- wps { +- label = "wps"; +- linux,code = ; +- gpios = <&pio 58 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x10000000>; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_5v: regulator-5v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-ð { +- pinctrl-names = "default"; +- pinctrl-0 = <ð_pins>; +- pinctrl-1 = <&ephy_leds_pins>; +- status = "okay"; +- +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "2500base-x"; +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- +- gmac1: mac@1 { +- compatible = "mediatek,eth-mac"; +- reg = <1>; +- phy-mode = "gmii"; +- phy-handle = <&phy0>; +- }; +- +- mdio: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +-}; +- +-&i2c { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_pins>; +- status = "okay"; +-}; +- +-&qspi { +- pinctrl-names = "default"; +- pinctrl-0 = <&qspi_pins>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x00000 0x60000>; +- read-only; +- }; +- +- partition@60000 { +- label = "u-boot-env"; +- reg = <0x60000 0x10000>; +- read-only; +- }; +- +- factory: partition@70000 { +- label = "factory"; +- reg = <0x70000 0x40000>; +- read-only; +- }; +- +- partition@b0000 { +- label = "kernel"; +- reg = <0xb0000 0xb50000>; +- }; +- }; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_pins>; +-}; +- +-&pciephy1 { +- status = "okay"; +-}; +- +-&pio { +- eth_pins: eth-pins { +- mux { +- function = "eth"; +- groups = "mdc_mdio"; +- }; +- }; +- +- ephy_leds_pins: ephy-leds-pins { +- mux { +- function = "led"; +- groups = "gphy_leds_0", "ephy_leds"; +- }; +- }; +- +- i2c_pins: i2c-pins { +- mux { +- function = "i2c"; +- groups = "i2c_0"; +- }; +- +- conf { +- pins = "I2C_SDA", "I2C_SCL"; +- drive-strength = <4>; +- bias-disable; +- }; +- }; +- +- pcie_pins: pcie-pins { +- mux { +- function = "pcie"; +- groups = "pcie_clkreq", +- "pcie_pereset", +- "pcie_wake"; +- }; +- }; +- +- pwm_pins: pwm-pins { +- mux { +- function = "pwm"; +- groups = "pwm_0"; +- }; +- }; +- +- /* SPI-NOR is shared pin with serial NAND */ +- qspi_pins: qspi-pins { +- mux { +- function = "flash"; +- groups = "spi_nor"; +- }; +- }; +- +- /* Serial NAND is shared pin with SPI-NOR */ +- serial_nand_pins: serial-nand-pins { +- mux { +- function = "flash"; +- groups = "snfi"; +- }; +- }; +- +- spi_pins: spi-pins { +- mux { +- function = "spi"; +- groups = "spi_0"; +- }; +- }; +- +- uart0_pins: uart0-pins { +- mux { +- function = "uart"; +- groups = "uart0_txd_rxd" ; +- }; +- }; +- +- uart1_pins: uart1-pins { +- mux { +- function = "uart"; +- groups = "uart1_0_tx_rx" ; +- }; +- }; +- +- uart2_pins: uart2-pins { +- mux { +- function = "uart"; +- groups = "uart2_0_txd_rxd" ; +- }; +- }; +- +- watchdog_pins: watchdog-pins { +- mux { +- function = "watchdog"; +- groups = "watchdog"; +- }; +- }; +-}; +- +-&spi { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_pins>; +- status = "okay"; +-}; +- +-&ssusb { +- vusb33-supply = <®_3p3v>; +- vbus-supply = <®_5v>; +- status = "okay"; +-}; +- +-&u3phy0 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +-&watchdog { +- pinctrl-names = "default"; +- pinctrl-0 = <&watchdog_pins>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt7629.dtsi b/scripts/dtc/include-prefixes/arm/mt7629.dtsi +deleted file mode 100644 +index 874043f0490d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt7629.dtsi ++++ /dev/null +@@ -1,495 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019 MediaTek Inc. +- * +- * Author: Ryder Lee +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "mediatek,mt7629"; +- interrupt-parent = <&sysirq>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "mediatek,mt6589-smp"; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x0>; +- clock-frequency = <1250000000>; +- cci-control-port = <&cci_control2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x1>; +- clock-frequency = <1250000000>; +- cci-control-port = <&cci_control2>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupts = , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- clk20m: oscillator-0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <20000000>; +- clock-output-names = "clk20m"; +- }; +- +- clk40m: oscillator-1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <40000000>; +- clock-output-names = "clkxtal"; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- clock-frequency = <20000000>; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- infracfg: syscon@10000000 { +- compatible = "mediatek,mt7629-infracfg", "syscon"; +- reg = <0x10000000 0x1000>; +- #clock-cells = <1>; +- }; +- +- pericfg: syscon@10002000 { +- compatible = "mediatek,mt7629-pericfg", "syscon"; +- reg = <0x10002000 0x1000>; +- #clock-cells = <1>; +- }; +- +- scpsys: power-controller@10006000 { +- compatible = "mediatek,mt7629-scpsys", +- "mediatek,mt7622-scpsys"; +- #power-domain-cells = <1>; +- reg = <0x10006000 0x1000>; +- clocks = <&topckgen CLK_TOP_HIF_SEL>; +- clock-names = "hif_sel"; +- assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; +- infracfg = <&infracfg>; +- }; +- +- timer: timer@10009000 { +- compatible = "mediatek,mt7629-timer", +- "mediatek,mt6765-timer"; +- reg = <0x10009000 0x60>; +- interrupts = , +- ; +- clocks = <&clk20m>; +- clock-names = "clk20m"; +- }; +- +- sysirq: interrupt-controller@10200a80 { +- compatible = "mediatek,mt7629-sysirq", +- "mediatek,mt6577-sysirq"; +- reg = <0x10200a80 0x20>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- }; +- +- apmixedsys: syscon@10209000 { +- compatible = "mediatek,mt7629-apmixedsys", "syscon"; +- reg = <0x10209000 0x1000>; +- #clock-cells = <1>; +- }; +- +- rng: rng@1020f000 { +- compatible = "mediatek,mt7629-rng", +- "mediatek,mt7623-rng"; +- reg = <0x1020f000 0x100>; +- clocks = <&infracfg CLK_INFRA_TRNG_PD>; +- clock-names = "rng"; +- }; +- +- topckgen: syscon@10210000 { +- compatible = "mediatek,mt7629-topckgen", "syscon"; +- reg = <0x10210000 0x1000>; +- #clock-cells = <1>; +- }; +- +- watchdog: watchdog@10212000 { +- compatible = "mediatek,mt7629-wdt", +- "mediatek,mt6589-wdt"; +- reg = <0x10212000 0x100>; +- }; +- +- pio: pinctrl@10217000 { +- compatible = "mediatek,mt7629-pinctrl"; +- reg = <0x10217000 0x8000>, +- <0x10005000 0x1000>; +- reg-names = "base", "eint"; +- gpio-controller; +- gpio-ranges = <&pio 0 0 79>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- interrupt-controller; +- interrupts = ; +- interrupt-parent = <&gic>; +- }; +- +- gic: interrupt-controller@10300000 { +- compatible = "arm,gic-400"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0x10310000 0x1000>, +- <0x10320000 0x1000>, +- <0x10340000 0x2000>, +- <0x10360000 0x2000>; +- }; +- +- cci: cci@10390000 { +- compatible = "arm,cci-400"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x10390000 0x1000>; +- ranges = <0 0x10390000 0x10000>; +- +- cci_control0: slave-if@1000 { +- compatible = "arm,cci-400-ctrl-if"; +- interface-type = "ace-lite"; +- reg = <0x1000 0x1000>; +- }; +- +- cci_control1: slave-if@4000 { +- compatible = "arm,cci-400-ctrl-if"; +- interface-type = "ace"; +- reg = <0x4000 0x1000>; +- }; +- +- cci_control2: slave-if@5000 { +- compatible = "arm,cci-400-ctrl-if"; +- interface-type = "ace"; +- reg = <0x5000 0x1000>; +- }; +- +- pmu@9000 { +- compatible = "arm,cci-400-pmu,r1"; +- reg = <0x9000 0x5000>; +- interrupts = , +- , +- , +- , +- ; +- }; +- }; +- +- uart0: serial@11002000 { +- compatible = "mediatek,mt7629-uart", +- "mediatek,mt6577-uart"; +- reg = <0x11002000 0x400>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_UART_SEL>, +- <&pericfg CLK_PERI_UART0_PD>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart1: serial@11003000 { +- compatible = "mediatek,mt7629-uart", +- "mediatek,mt6577-uart"; +- reg = <0x11003000 0x400>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_UART_SEL>, +- <&pericfg CLK_PERI_UART1_PD>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart2: serial@11004000 { +- compatible = "mediatek,mt7629-uart", +- "mediatek,mt6577-uart"; +- reg = <0x11004000 0x400>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_UART_SEL>, +- <&pericfg CLK_PERI_UART2_PD>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- pwm: pwm@11006000 { +- compatible = "mediatek,mt7629-pwm"; +- reg = <0x11006000 0x1000>; +- #pwm-cells = <2>; +- clocks = <&topckgen CLK_TOP_PWM_SEL>, +- <&pericfg CLK_PERI_PWM_PD>, +- <&pericfg CLK_PERI_PWM1_PD>; +- clock-names = "top", "main", "pwm1"; +- assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>; +- assigned-clock-parents = +- <&topckgen CLK_TOP_UNIVPLL2_D4>; +- status = "disabled"; +- }; +- +- i2c: i2c@11007000 { +- compatible = "mediatek,mt7629-i2c", +- "mediatek,mt2712-i2c"; +- reg = <0x11007000 0x90>, +- <0x11000100 0x80>; +- interrupts = ; +- clock-div = <4>; +- clocks = <&pericfg CLK_PERI_I2C0_PD>, +- <&pericfg CLK_PERI_AP_DMA_PD>; +- clock-names = "main", "dma"; +- assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi: spi@1100a000 { +- compatible = "mediatek,mt7629-spi", +- "mediatek,mt7622-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x1100a000 0x100>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, +- <&topckgen CLK_TOP_SPI0_SEL>, +- <&pericfg CLK_PERI_SPI0_PD>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- qspi: spi@11014000 { +- compatible = "mediatek,mt7629-nor", +- "mediatek,mt8173-nor"; +- reg = <0x11014000 0xe0>; +- clocks = <&pericfg CLK_PERI_FLASH_PD>, +- <&topckgen CLK_TOP_FLASH_SEL>; +- clock-names = "spi", "sf"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- ssusbsys: syscon@1a000000 { +- compatible = "mediatek,mt7629-ssusbsys", "syscon"; +- reg = <0x1a000000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- ssusb: usb@1a0c0000 { +- compatible = "mediatek,mt7629-xhci", +- "mediatek,mtk-xhci"; +- reg = <0x1a0c0000 0x01000>, +- <0x1a0c3e00 0x0100>; +- reg-names = "mac", "ippc"; +- interrupts = ; +- clocks = <&ssusbsys CLK_SSUSB_SYS_EN>, +- <&ssusbsys CLK_SSUSB_REF_EN>, +- <&ssusbsys CLK_SSUSB_MCU_EN>, +- <&ssusbsys CLK_SSUSB_DMA_EN>; +- clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; +- assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>, +- <&topckgen CLK_TOP_SATA_SEL>, +- <&topckgen CLK_TOP_HIF_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>, +- <&topckgen CLK_TOP_UNIVPLL2_D4>, +- <&topckgen CLK_TOP_UNIVPLL1_D2>; +- power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>; +- phys = <&u2port0 PHY_TYPE_USB2>, +- <&u3port0 PHY_TYPE_USB3>; +- status = "disabled"; +- }; +- +- u3phy0: t-phy@1a0c4000 { +- compatible = "mediatek,mt7629-tphy", +- "mediatek,generic-tphy-v2"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1a0c4000 0xe00>; +- status = "disabled"; +- +- u2port0: usb-phy@0 { +- reg = <0 0x700>; +- clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- +- u3port0: usb-phy@700 { +- reg = <0x700 0x700>; +- clocks = <&clk20m>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- }; +- +- pciesys: syscon@1a100800 { +- compatible = "mediatek,mt7629-pciesys", "syscon"; +- reg = <0x1a100800 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pcie: pcie@1a140000 { +- compatible = "mediatek,mt7629-pcie"; +- device_type = "pci"; +- reg = <0x1a140000 0x1000>, +- <0x1a145000 0x1000>; +- reg-names = "subsys","port1"; +- #address-cells = <3>; +- #size-cells = <2>; +- interrupts = , +- ; +- clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, +- <&pciesys CLK_PCIE_P0_AHB_EN>, +- <&pciesys CLK_PCIE_P1_AUX_EN>, +- <&pciesys CLK_PCIE_P1_AXI_EN>, +- <&pciesys CLK_PCIE_P1_OBFF_EN>, +- <&pciesys CLK_PCIE_P1_PIPE_EN>; +- clock-names = "sys_ck1", "ahb_ck1", +- "aux_ck1", "axi_ck1", +- "obff_ck1", "pipe_ck1"; +- assigned-clocks = <&topckgen CLK_TOP_SATA_SEL>, +- <&topckgen CLK_TOP_AXI_SEL>, +- <&topckgen CLK_TOP_HIF_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>, +- <&topckgen CLK_TOP_SYSPLL1_D2>, +- <&topckgen CLK_TOP_UNIVPLL1_D2>; +- phys = <&pcieport1 PHY_TYPE_PCIE>; +- phy-names = "pcie-phy1"; +- power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; +- bus-range = <0x00 0xff>; +- ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>; +- +- pcie1: pcie@1,0 { +- device_type = "pci"; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- num-lanes = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie_intc1 0>, +- <0 0 0 2 &pcie_intc1 1>, +- <0 0 0 3 &pcie_intc1 2>, +- <0 0 0 4 &pcie_intc1 3>; +- +- pcie_intc1: interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- }; +- }; +- }; +- +- pciephy1: t-phy@1a14a000 { +- compatible = "mediatek,mt7629-tphy", +- "mediatek,generic-tphy-v2"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1a14a000 0x1000>; +- status = "disabled"; +- +- pcieport1: pcie-phy@0 { +- reg = <0 0x1000>; +- clocks = <&clk20m>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- }; +- +- ethsys: syscon@1b000000 { +- compatible = "mediatek,mt7629-ethsys", "syscon"; +- reg = <0x1b000000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- eth: ethernet@1b100000 { +- compatible = "mediatek,mt7629-eth","syscon"; +- reg = <0x1b100000 0x20000>; +- interrupts = , +- , +- ; +- clocks = <&topckgen CLK_TOP_ETH_SEL>, +- <&topckgen CLK_TOP_F10M_REF_SEL>, +- <ðsys CLK_ETH_ESW_EN>, +- <ðsys CLK_ETH_GP0_EN>, +- <ðsys CLK_ETH_GP1_EN>, +- <ðsys CLK_ETH_GP2_EN>, +- <ðsys CLK_ETH_FE_EN>, +- <&sgmiisys0 CLK_SGMII_TX_EN>, +- <&sgmiisys0 CLK_SGMII_RX_EN>, +- <&sgmiisys0 CLK_SGMII_CDR_REF>, +- <&sgmiisys0 CLK_SGMII_CDR_FB>, +- <&sgmiisys1 CLK_SGMII_TX_EN>, +- <&sgmiisys1 CLK_SGMII_RX_EN>, +- <&sgmiisys1 CLK_SGMII_CDR_REF>, +- <&sgmiisys1 CLK_SGMII_CDR_FB>, +- <&apmixedsys CLK_APMIXED_SGMIPLL>, +- <&apmixedsys CLK_APMIXED_ETH2PLL>; +- clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1", +- "gp2", "fe", "sgmii_tx250m", "sgmii_rx250m", +- "sgmii_cdr_ref", "sgmii_cdr_fb", +- "sgmii2_tx250m", "sgmii2_rx250m", +- "sgmii2_cdr_ref", "sgmii2_cdr_fb", +- "sgmii_ck", "eth2pll"; +- assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>, +- <&topckgen CLK_TOP_F10M_REF_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>, +- <&topckgen CLK_TOP_SGMIIPLL_D2>; +- power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; +- mediatek,ethsys = <ðsys>; +- mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; +- mediatek,infracfg = <&infracfg>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- sgmiisys0: syscon@1b128000 { +- compatible = "mediatek,mt7629-sgmiisys", "syscon"; +- reg = <0x1b128000 0x3000>; +- #clock-cells = <1>; +- }; +- +- sgmiisys1: syscon@1b130000 { +- compatible = "mediatek,mt7629-sgmiisys", "syscon"; +- reg = <0x1b130000 0x3000>; +- #clock-cells = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt8127-moose.dts b/scripts/dtc/include-prefixes/arm/mt8127-moose.dts +deleted file mode 100644 +index 560687af87dc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt8127-moose.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2014 MediaTek Inc. +- * Author: Joe.C +- * +- */ +- +-/dts-v1/; +-#include "mt8127.dtsi" +- +-/ { +- model = "MediaTek MT8127 Moose Board"; +- compatible = "mediatek,mt8127-moose", "mediatek,mt8127"; +- +- memory { +- device_type = "memory"; +- reg = <0 0x80000000 0 0x40000000>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt8127.dtsi b/scripts/dtc/include-prefixes/arm/mt8127.dtsi +deleted file mode 100644 +index aced173c2a52..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt8127.dtsi ++++ /dev/null +@@ -1,163 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2014 MediaTek Inc. +- * Author: Joe.C +- * +- */ +- +-#include +-#include +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "mediatek,mt8127"; +- interrupt-parent = <&sysirq>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "mediatek,mt81xx-tz-smp"; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x0>; +- }; +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x1>; +- }; +- cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x2>; +- }; +- cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x3>; +- }; +- +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- trustzone-bootinfo@80002000 { +- compatible = "mediatek,trustzone-bootinfo"; +- reg = <0 0x80002000 0 0x1000>; +- }; +- }; +- +- clocks { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "simple-bus"; +- ranges; +- +- system_clk: dummy13m { +- compatible = "fixed-clock"; +- clock-frequency = <13000000>; +- #clock-cells = <0>; +- }; +- +- rtc_clk: dummy32k { +- compatible = "fixed-clock"; +- clock-frequency = <32000>; +- #clock-cells = <0>; +- }; +- +- uart_clk: dummy26m { +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- #clock-cells = <0>; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- clock-frequency = <13000000>; +- arm,cpu-registers-not-fw-configured; +- }; +- +- soc { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "simple-bus"; +- ranges; +- +- timer: timer@10008000 { +- compatible = "mediatek,mt8127-timer", +- "mediatek,mt6577-timer"; +- reg = <0 0x10008000 0 0x80>; +- interrupts = ; +- clocks = <&system_clk>, <&rtc_clk>; +- clock-names = "system-clk", "rtc-clk"; +- }; +- +- sysirq: interrupt-controller@10200100 { +- compatible = "mediatek,mt8127-sysirq", +- "mediatek,mt6577-sysirq"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0 0x10200100 0 0x1c>; +- }; +- +- gic: interrupt-controller@10211000 { +- compatible = "arm,cortex-a7-gic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0 0x10211000 0 0x1000>, +- <0 0x10212000 0 0x2000>, +- <0 0x10214000 0 0x2000>, +- <0 0x10216000 0 0x2000>; +- }; +- +- uart0: serial@11002000 { +- compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; +- reg = <0 0x11002000 0 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart1: serial@11003000 { +- compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; +- reg = <0 0x11003000 0 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart2: serial@11004000 { +- compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; +- reg = <0 0x11004000 0 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart3: serial@11005000 { +- compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; +- reg = <0 0x11005000 0 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt8135-evbp1.dts b/scripts/dtc/include-prefixes/arm/mt8135-evbp1.dts +deleted file mode 100644 +index f6147fe62f41..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt8135-evbp1.dts ++++ /dev/null +@@ -1,193 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2014 MediaTek Inc. +- * Author: Joe.C +- * +- */ +- +-/dts-v1/; +-#include "mt8135.dtsi" +- +-/ { +- model = "MediaTek MT8135 evaluation board"; +- compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135"; +- +- memory { +- device_type = "memory"; +- reg = <0 0x80000000 0 0x40000000>; +- }; +-}; +- +-&pwrap { +- pmic: mt6397 { +- compatible = "mediatek,mt6397"; +- +- mt6397regulator: mt6397regulator { +- compatible = "mediatek,mt6397-regulator"; +- +- mt6397_vpca15_reg: buck_vpca15 { +- regulator-name = "vpca15"; +- regulator-min-microvolt = < 850000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- }; +- +- mt6397_vpca7_reg: buck_vpca7 { +- regulator-name = "vpca7"; +- regulator-min-microvolt = < 850000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- }; +- +- mt6397_vsramca15_reg: buck_vsramca15 { +- regulator-name = "vsramca15"; +- regulator-min-microvolt = < 850000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- }; +- +- mt6397_vsramca7_reg: buck_vsramca7 { +- regulator-name = "vsramca7"; +- regulator-min-microvolt = < 850000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- }; +- +- mt6397_vcore_reg: buck_vcore { +- regulator-name = "vcore"; +- regulator-min-microvolt = < 850000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- }; +- +- mt6397_vgpu_reg: buck_vgpu { +- regulator-name = "vgpu"; +- regulator-min-microvolt = < 700000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <12500>; +- regulator-enable-ramp-delay = <115>; +- }; +- +- mt6397_vdrm_reg: buck_vdrm { +- regulator-name = "vdrm"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1400000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- }; +- +- mt6397_vio18_reg: buck_vio18 { +- regulator-name = "vio18"; +- regulator-min-microvolt = <1620000>; +- regulator-max-microvolt = <1980000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- }; +- +- mt6397_vtcxo_reg: ldo_vtcxo { +- regulator-name = "vtcxo"; +- regulator-always-on; +- }; +- +- mt6397_va28_reg: ldo_va28 { +- regulator-name = "va28"; +- regulator-always-on; +- }; +- +- mt6397_vcama_reg: ldo_vcama { +- regulator-name = "vcama"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <2800000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vio28_reg: ldo_vio28 { +- regulator-name = "vio28"; +- regulator-always-on; +- }; +- +- mt6397_vusb_reg: ldo_vusb { +- regulator-name = "vusb"; +- }; +- +- mt6397_vmc_reg: ldo_vmc { +- regulator-name = "vmc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vmch_reg: ldo_vmch { +- regulator-name = "vmch"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vemc_3v3_reg: ldo_vemc3v3 { +- regulator-name = "vemc_3v3"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vgp1_reg: ldo_vgp1 { +- regulator-name = "vcamd"; +- regulator-min-microvolt = <1220000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <240>; +- }; +- +- mt6397_vgp2_reg: ldo_vgp2 { +- regulator-name = "vcamio"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vgp3_reg: ldo_vgp3 { +- regulator-name = "vcamaf"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vgp4_reg: ldo_vgp4 { +- regulator-name = "vgp4"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vgp5_reg: ldo_vgp5 { +- regulator-name = "vgp5"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3000000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vgp6_reg: ldo_vgp6 { +- regulator-name = "vgp6"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vibr_reg: ldo_vibr { +- regulator-name = "vibr"; +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- }; +- }; +-}; +- +-&uart3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mt8135.dtsi b/scripts/dtc/include-prefixes/arm/mt8135.dtsi +deleted file mode 100644 +index a031b3636318..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mt8135.dtsi ++++ /dev/null +@@ -1,260 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2014 MediaTek Inc. +- * Author: Joe.C +- * +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "mediatek,mt8135"; +- interrupt-parent = <&sysirq>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&cpu2>; +- }; +- core1 { +- cpu = <&cpu3>; +- }; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "mediatek,mt81xx-tz-smp"; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x000>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x001>; +- }; +- +- cpu2: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x100>; +- }; +- +- cpu3: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x101>; +- }; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- trustzone-bootinfo@80002000 { +- compatible = "mediatek,trustzone-bootinfo"; +- reg = <0 0x80002000 0 0x1000>; +- }; +- }; +- +- clocks { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "simple-bus"; +- ranges; +- +- system_clk: dummy13m { +- compatible = "fixed-clock"; +- clock-frequency = <13000000>; +- #clock-cells = <0>; +- }; +- +- rtc_clk: dummy32k { +- compatible = "fixed-clock"; +- clock-frequency = <32000>; +- #clock-cells = <0>; +- }; +- +- clk26m: clk26m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- clock-frequency = <13000000>; +- arm,cpu-registers-not-fw-configured; +- }; +- +- soc { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "simple-bus"; +- ranges; +- +- topckgen: topckgen@10000000 { +- compatible = "mediatek,mt8135-topckgen"; +- reg = <0 0x10000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- infracfg: infracfg@10001000 { +- #reset-cells = <1>; +- #clock-cells = <1>; +- compatible = "mediatek,mt8135-infracfg", "syscon"; +- reg = <0 0x10001000 0 0x1000>; +- }; +- +- pericfg: pericfg@10003000 { +- #reset-cells = <1>; +- #clock-cells = <1>; +- compatible = "mediatek,mt8135-pericfg", "syscon"; +- reg = <0 0x10003000 0 0x1000>; +- }; +- +- /* +- * Pinctrl access register at 0x10005000 and 0x1020c000 through +- * regmap. Register 0x1000b000 is used by EINT. +- */ +- pio: pinctrl@10005000 { +- compatible = "mediatek,mt8135-pinctrl"; +- reg = <0 0x1000b000 0 0x1000>; +- mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; +- pins-are-numbered; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = , +- , +- ; +- }; +- +- syscfg_pctl_a: syscfg_pctl_a@10005000 { +- compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon"; +- reg = <0 0x10005000 0 0x1000>; +- }; +- +- timer: timer@10008000 { +- compatible = "mediatek,mt8135-timer", +- "mediatek,mt6577-timer"; +- reg = <0 0x10008000 0 0x80>; +- interrupts = ; +- clocks = <&system_clk>, <&rtc_clk>; +- clock-names = "system-clk", "rtc-clk"; +- }; +- +- pwrap: pwrap@1000f000 { +- compatible = "mediatek,mt8135-pwrap"; +- reg = <0 0x1000f000 0 0x1000>, +- <0 0x11017000 0 0x1000>; +- reg-names = "pwrap", "pwrap-bridge"; +- interrupts = ; +- resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, +- <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; +- reset-names = "pwrap", "pwrap-bridge"; +- clocks = <&clk26m>, <&clk26m>; +- clock-names = "spi", "wrap"; +- }; +- +- sysirq: interrupt-controller@10200030 { +- compatible = "mediatek,mt8135-sysirq", +- "mediatek,mt6577-sysirq"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0 0x10200030 0 0x1c>; +- }; +- +- apmixedsys: apmixedsys@10209000 { +- compatible = "mediatek,mt8135-apmixedsys"; +- reg = <0 0x10209000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- syscfg_pctl_b: syscfg_pctl_b@1020c000 { +- compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; +- reg = <0 0x1020c000 0 0x1000>; +- }; +- +- gic: interrupt-controller@10211000 { +- compatible = "arm,cortex-a15-gic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0 0x10211000 0 0x1000>, +- <0 0x10212000 0 0x2000>, +- <0 0x10214000 0 0x2000>, +- <0 0x10216000 0 0x2000>; +- }; +- +- uart0: serial@11006000 { +- compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; +- reg = <0 0x11006000 0 0x400>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart1: serial@11007000 { +- compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; +- reg = <0 0x11007000 0 0x400>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart2: serial@11008000 { +- compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; +- reg = <0 0x11008000 0 0x400>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart3: serial@11009000 { +- compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; +- reg = <0 0x11009000 0 0x400>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mvebu-linkstation-fan.dtsi b/scripts/dtc/include-prefixes/arm/mvebu-linkstation-fan.dtsi +deleted file mode 100644 +index e172029a0c4d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mvebu-linkstation-fan.dtsi ++++ /dev/null +@@ -1,72 +0,0 @@ +-/* +- * Device Tree common file for gpio-fan on Buffalo Linkstation +- * +- * Copyright (C) 2015, 2016 +- * Roger Shimizu +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/ { +- gpio_fan { +- compatible = "gpio-fan"; +- pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; +- pinctrl-names = "default"; +- +- gpio-fan,speed-map = +- <0 3 +- 1500 2 +- 3250 1 +- 5000 0>; +- }; +-}; +- +-&pinctrl { +- pmx_fan_low: pmx-fan-low { +- marvell,function = "gpio"; +- }; +- +- pmx_fan_high: pmx-fan-high { +- marvell,function = "gpio"; +- }; +- +- pmx_fan_lock: pmx-fan-lock { +- marvell,function = "gpio"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mvebu-linkstation-gpio-simple.dtsi b/scripts/dtc/include-prefixes/arm/mvebu-linkstation-gpio-simple.dtsi +deleted file mode 100644 +index c2d87ba6190a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mvebu-linkstation-gpio-simple.dtsi ++++ /dev/null +@@ -1,105 +0,0 @@ +-/* +- * Device Tree common file for gpio-{keys,leds} on Buffalo Linkstation +- * +- * Copyright (C) 2015, 2016 +- * Roger Shimizu +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +- +-/ { +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_power_switch>; +- pinctrl-names = "default"; +- +- power-on-switch { +- label = "Power-on Switch"; +- linux,code = ; +- linux,input-type = <5>; +- }; +- +- power-auto-switch { +- label = "Power-auto Switch"; +- linux,code = ; +- linux,input-type = <5>; +- }; +- }; +- +- gpio_leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_led_power &pmx_led_alarm &pmx_led_info>; +- pinctrl-names = "default"; +- +- blue-power-led { +- label = "linkstation:blue:power"; +- default-state = "keep"; +- }; +- +- red-alarm-led { +- label = "linkstation:red:alarm"; +- }; +- +- amber-info-led { +- label = "linkstation:amber:info"; +- }; +- }; +-}; +- +-&pinctrl { +- pmx_power_switch: pmx-power-switch { +- marvell,function = "gpio"; +- }; +- +- pmx_led_power: pmx-leds { +- marvell,function = "gpio"; +- }; +- +- pmx_led_alarm: pmx-leds { +- marvell,function = "gpio"; +- }; +- +- pmx_led_info: pmx-leds { +- marvell,function = "gpio"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/mxs-pinfunc.h b/scripts/dtc/include-prefixes/arm/mxs-pinfunc.h +deleted file mode 100644 +index c6da987b20cb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/mxs-pinfunc.h ++++ /dev/null +@@ -1,31 +0,0 @@ +-/* +- * Header providing constants for i.MX28 pinctrl bindings. +- * +- * Copyright (C) 2013 Lothar Waßmann +- * +- * The code contained herein is licensed under the GNU General Public +- * License. You may obtain a copy of the GNU General Public License +- * Version 2 at the following locations: +- * +- * http://www.opensource.org/licenses/gpl-license.html +- * http://www.gnu.org/copyleft/gpl.html +- */ +- +-#ifndef __DT_BINDINGS_MXS_PINCTRL_H__ +-#define __DT_BINDINGS_MXS_PINCTRL_H__ +- +-/* fsl,drive-strength property */ +-#define MXS_DRIVE_4mA 0 +-#define MXS_DRIVE_8mA 1 +-#define MXS_DRIVE_12mA 2 +-#define MXS_DRIVE_16mA 3 +- +-/* fsl,voltage property */ +-#define MXS_VOLTAGE_LOW 0 +-#define MXS_VOLTAGE_HIGH 1 +- +-/* fsl,pull-up property */ +-#define MXS_PULL_DISABLE 0 +-#define MXS_PULL_ENABLE 1 +- +-#endif /* __DT_BINDINGS_MXS_PINCTRL_H__ */ +diff --git a/scripts/dtc/include-prefixes/arm/nspire-classic.dtsi b/scripts/dtc/include-prefixes/arm/nspire-classic.dtsi +deleted file mode 100644 +index 41744cc2bc72..000000000000 +--- a/scripts/dtc/include-prefixes/arm/nspire-classic.dtsi ++++ /dev/null +@@ -1,88 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * linux/arch/arm/boot/nspire-classic.dts +- * +- * Copyright (C) 2013 Daniel Tang +- */ +- +-/include/ "nspire.dtsi" +- +-&lcd { +- port { +- clcd_pads: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +-}; +- +-&fast_timer { +- /* compatible = "lsi,zevio-timer"; */ +- reg = <0x90010000 0x1000>, <0x900A0010 0x8>; +-}; +- +-&uart { +- compatible = "ns16550"; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&apb_pclk>; +- no-loopback-test; +-}; +- +-&timer0 { +- /* compatible = "lsi,zevio-timer"; */ +- reg = <0x900C0000 0x1000>, <0x900A0018 0x8>; +-}; +- +-&timer1 { +- compatible = "lsi,zevio-timer"; +- reg = <0x900D0000 0x1000>, <0x900A0020 0x8>; +-}; +- +-&keypad { +- active-low; +- +-}; +- +-&base_clk { +- compatible = "lsi,nspire-classic-clock"; +-}; +- +-&ahb_clk { +- compatible = "lsi,nspire-classic-ahb-divider"; +-}; +- +- +-&vbus_reg { +- gpio = <&gpio 5 0>; +-}; +- +-/ { +- memory { +- device_type = "memory"; +- reg = <0x10000000 0x2000000>; /* 32 MB */ +- }; +- +- ahb { +- #address-cells = <1>; +- #size-cells = <1>; +- +- intc: interrupt-controller@DC000000 { +- compatible = "lsi,zevio-intc"; +- interrupt-controller; +- reg = <0xDC000000 0x1000>; +- #interrupt-cells = <1>; +- }; +- }; +- +- panel { +- compatible = "ti,nspire-classic-lcd-panel"; +- port { +- panel_in: endpoint { +- remote-endpoint = <&clcd_pads>; +- }; +- }; +- }; +- chosen { +- bootargs = "debug earlyprintk console=tty0 console=ttyS0,115200n8 root=/dev/ram0"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/nspire-clp.dts b/scripts/dtc/include-prefixes/arm/nspire-clp.dts +deleted file mode 100644 +index f52f38c61588..000000000000 +--- a/scripts/dtc/include-prefixes/arm/nspire-clp.dts ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * linux/arch/arm/boot/nspire-clp.dts +- * +- * Copyright (C) 2013 Daniel Tang +- */ +-/dts-v1/; +- +-/include/ "nspire-classic.dtsi" +- +-&keypad { +- linux,keymap = < +- 0x0000001c 0x0001001c 0x00020039 +- 0x0004002c 0x00050034 0x00060015 +- 0x0007000b 0x0008002d 0x01000033 +- 0x0101004e 0x01020011 0x01030004 +- 0x0104002f 0x01050003 0x01060016 +- 0x01070002 0x01080014 0x02000062 +- 0x0201000c 0x0202001f 0x02030007 +- 0x02040013 0x02050006 0x02060010 +- 0x02070005 0x02080019 0x03000027 +- 0x03010037 0x03020018 0x0303000a +- 0x03040031 0x03050009 0x03060032 +- 0x03070008 0x03080026 0x04000028 +- 0x04010035 0x04020025 0x04040024 +- 0x04060017 0x04080023 0x05000028 +- 0x05020022 0x0503001b 0x05040021 +- 0x0505001a 0x05060012 0x0507006f +- 0x05080020 0x0509002a 0x0601001c +- 0x0602002e 0x06030068 0x06040030 +- 0x0605006d 0x0606001e 0x06070001 +- 0x0608002b 0x0609000f 0x07000067 +- 0x0702006a 0x0704006c 0x07060069 +- 0x0707000e 0x0708001d 0x070a000d +- >; +-}; +- +-/ { +- model = "TI-NSPIRE Clickpad"; +- compatible = "ti,nspire-clp"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/nspire-cx.dts b/scripts/dtc/include-prefixes/arm/nspire-cx.dts +deleted file mode 100644 +index 0c16b04e2744..000000000000 +--- a/scripts/dtc/include-prefixes/arm/nspire-cx.dts ++++ /dev/null +@@ -1,125 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * linux/arch/arm/boot/nspire-cx.dts +- * +- * Copyright (C) 2013 Daniel Tang +- */ +-/dts-v1/; +- +-/include/ "nspire.dtsi" +- +-&lcd { +- port { +- clcd_pads: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +-}; +- +-&fast_timer { +- /* compatible = "arm,sp804", "arm,primecell"; */ +-}; +- +-&uart { +- compatible = "arm,pl011", "arm,primecell"; +- +- clocks = <&uart_clk>, <&apb_pclk>; +- clock-names = "uart_clk", "apb_pclk"; +-}; +- +-&timer0 { +- compatible = "arm,sp804", "arm,primecell"; +-}; +- +-&timer1 { +- compatible = "arm,sp804", "arm,primecell"; +-}; +- +-&base_clk { +- compatible = "lsi,nspire-cx-clock"; +-}; +- +-&ahb_clk { +- compatible = "lsi,nspire-cx-ahb-divider"; +-}; +- +-&keypad { +- linux,keymap = < +- 0x0000001c 0x0001001c 0x00040039 +- 0x0005002c 0x00060015 0x0007000b +- 0x0008000f 0x0100002d 0x01010011 +- 0x0102002f 0x01030004 0x01040016 +- 0x01050014 0x0106001f 0x01070002 +- 0x010a006a 0x02000013 0x02010010 +- 0x02020019 0x02030007 0x02040018 +- 0x02050031 0x02060032 0x02070005 +- 0x02080028 0x0209006c 0x03000026 +- 0x03010025 0x03020024 0x0303000a +- 0x03040017 0x03050023 0x03060022 +- 0x03070008 0x03080035 0x03090069 +- 0x04000021 0x04010012 0x04020020 +- 0x0404002e 0x04050030 0x0406001e +- 0x0407000d 0x04080037 0x04090067 +- 0x05010038 0x0502000c 0x0503001b +- 0x05040034 0x0505001a 0x05060006 +- 0x05080027 0x0509000e 0x050a006f +- 0x0600002b 0x0602004e 0x06030068 +- 0x06040003 0x0605006d 0x06060009 +- 0x06070001 0x0609000f 0x0708002a +- 0x0709001d 0x070a0033 >; +-}; +- +-&vbus_reg { +- gpio = <&gpio 2 0>; +-}; +- +-/ { +- model = "TI-NSPIRE CX"; +- compatible = "ti,nspire-cx"; +- +- memory { +- device_type = "memory"; +- reg = <0x10000000 0x4000000>; /* 64 MB */ +- }; +- +- uart_clk: uart_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <12000000>; +- }; +- +- ahb { +- #address-cells = <1>; +- #size-cells = <1>; +- +- intc: interrupt-controller@DC000000 { +- compatible = "arm,pl190-vic"; +- interrupt-controller; +- reg = <0xDC000000 0x1000>; +- #interrupt-cells = <1>; +- }; +- +- apb@90000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- +- i2c@90050000 { +- compatible = "snps,designware-i2c"; +- reg = <0x90050000 0x1000>; +- interrupts = <20>; +- }; +- }; +- }; +- +- panel { +- compatible = "ti,nspire-cx-lcd-panel"; +- port { +- panel_in: endpoint { +- remote-endpoint = <&clcd_pads>; +- }; +- }; +- }; +- chosen { +- bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/nspire-tp.dts b/scripts/dtc/include-prefixes/arm/nspire-tp.dts +deleted file mode 100644 +index f7d0faacd4cc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/nspire-tp.dts ++++ /dev/null +@@ -1,40 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * linux/arch/arm/boot/nspire-tp.dts +- * +- * Copyright (C) 2013 Daniel Tang +- */ +-/dts-v1/; +- +-/include/ "nspire-classic.dtsi" +- +-&keypad { +- linux,keymap = < +- 0x0000001c 0x0001001c 0x00040039 +- 0x0005002c 0x00060015 0x0007000b +- 0x0008000f 0x0100002d 0x01010011 +- 0x0102002f 0x01030004 0x01040016 +- 0x01050014 0x0106001f 0x01070002 +- 0x010a006a 0x02000013 0x02010010 +- 0x02020019 0x02030007 0x02040018 +- 0x02050031 0x02060032 0x02070005 +- 0x02080028 0x0209006c 0x03000026 +- 0x03010025 0x03020024 0x0303000a +- 0x03040017 0x03050023 0x03060022 +- 0x03070008 0x03080035 0x03090069 +- 0x04000021 0x04010012 0x04020020 +- 0x0404002e 0x04050030 0x0406001e +- 0x0407000d 0x04080037 0x04090067 +- 0x05010038 0x0502000c 0x0503001b +- 0x05040034 0x0505001a 0x05060006 +- 0x05080027 0x0509000e 0x050a006f +- 0x0600002b 0x0602004e 0x06030068 +- 0x06040003 0x0605006d 0x06060009 +- 0x06070001 0x0609000f 0x0708002a +- 0x0709001d 0x070a0033 >; +-}; +- +-/ { +- model = "TI-NSPIRE Touchpad"; +- compatible = "ti,nspire-tp"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/nspire.dtsi b/scripts/dtc/include-prefixes/arm/nspire.dtsi +deleted file mode 100644 +index 90e033d9141f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/nspire.dtsi ++++ /dev/null +@@ -1,203 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * linux/arch/arm/boot/nspire.dtsi +- * +- * Copyright (C) 2013 Daniel Tang +- */ +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&intc>; +- +- cpus { +- cpu@0 { +- compatible = "arm,arm926ej-s"; +- }; +- }; +- +- bootrom: bootrom@0 { +- reg = <0x00000000 0x80000>; +- }; +- +- sram: sram@A4000000 { +- device = "memory"; +- reg = <0xA4000000 0x20000>; +- }; +- +- timer_clk: timer_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- base_clk: base_clk { +- #clock-cells = <0>; +- reg = <0x900B0024 0x4>; +- }; +- +- ahb_clk: ahb_clk { +- #clock-cells = <0>; +- reg = <0x900B0024 0x4>; +- clocks = <&base_clk>; +- }; +- +- apb_pclk: apb_pclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <2>; +- clock-mult = <1>; +- clocks = <&ahb_clk>; +- }; +- +- usb_phy: usb_phy { +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- }; +- +- vbus_reg: vbus_reg { +- compatible = "regulator-fixed"; +- +- regulator-name = "USB VBUS output"; +- regulator-type = "voltage"; +- +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- ahb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- spi: spi@A9000000 { +- reg = <0xA9000000 0x1000>; +- }; +- +- usb0: usb@B0000000 { +- compatible = "lsi,zevio-usb"; +- reg = <0xB0000000 0x1000>; +- interrupts = <8>; +- +- usb-phy = <&usb_phy>; +- vbus-supply = <&vbus_reg>; +- }; +- +- usb1: usb@B4000000 { +- reg = <0xB4000000 0x1000>; +- interrupts = <9>; +- status = "disabled"; +- }; +- +- lcd: lcd@C0000000 { +- compatible = "arm,pl111", "arm,primecell"; +- reg = <0xC0000000 0x1000>; +- interrupts = <21>; +- +- /* +- * We assume the same clock is fed to APB and CLCDCLK. +- * There is some code to scale the clock down by a factor +- * 48 for the display so likely the frequency to the +- * display is 1MHz and the CLCDCLK is 48 MHz. +- */ +- clocks = <&apb_pclk>, <&apb_pclk>; +- clock-names = "clcdclk", "apb_pclk"; +- }; +- +- adc: adc@C4000000 { +- reg = <0xC4000000 0x1000>; +- interrupts = <11>; +- }; +- +- tdes: crypto@C8010000 { +- reg = <0xC8010000 0x1000>; +- }; +- +- sha256: crypto@CC000000 { +- reg = <0xCC000000 0x1000>; +- }; +- +- apb@90000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- clock-ranges; +- ranges; +- +- gpio: gpio@90000000 { +- compatible = "lsi,zevio-gpio"; +- reg = <0x90000000 0x1000>; +- interrupts = <7>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- fast_timer: timer@90010000 { +- reg = <0x90010000 0x1000>; +- interrupts = <17>; +- }; +- +- uart: serial@90020000 { +- reg = <0x90020000 0x1000>; +- interrupts = <1>; +- }; +- +- timer0: timer@900C0000 { +- reg = <0x900C0000 0x1000>; +- clocks = <&timer_clk>, <&timer_clk>, +- <&timer_clk>; +- clock-names = "timer0clk", "timer1clk", +- "apb_pclk"; +- }; +- +- timer1: timer@900D0000 { +- reg = <0x900D0000 0x1000>; +- interrupts = <19>; +- clocks = <&timer_clk>, <&timer_clk>, +- <&timer_clk>; +- clock-names = "timer0clk", "timer1clk", +- "apb_pclk"; +- }; +- +- watchdog: watchdog@90060000 { +- compatible = "arm,amba-primecell"; +- reg = <0x90060000 0x1000>; +- interrupts = <3>; +- }; +- +- rtc: rtc@90090000 { +- reg = <0x90090000 0x1000>; +- interrupts = <4>; +- }; +- +- misc: misc@900A0000 { +- reg = <0x900A0000 0x1000>; +- }; +- +- pwr: pwr@900B0000 { +- reg = <0x900B0000 0x1000>; +- interrupts = <15>; +- }; +- +- keypad: input@900E0000 { +- compatible = "ti,nspire-keypad"; +- reg = <0x900E0000 0x1000>; +- interrupts = <16>; +- +- scan-interval = <1000>; +- row-delay = <200>; +- +- clocks = <&apb_pclk>; +- }; +- +- contrast: contrast@900F0000 { +- reg = <0x900F0000 0x1000>; +- }; +- +- led: led@90110000 { +- reg = <0x90110000 0x1000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/nuvoton-common-npcm7xx.dtsi b/scripts/dtc/include-prefixes/arm/nuvoton-common-npcm7xx.dtsi +deleted file mode 100644 +index 3696980a3da1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/nuvoton-common-npcm7xx.dtsi ++++ /dev/null +@@ -1,1122 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com +-// Copyright 2018 Google, Inc. +- +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&gic>; +- +- /* external reference clock */ +- clk_refclk: clk_refclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- clock-output-names = "refclk"; +- }; +- +- /* external reference clock for cpu. float in normal operation */ +- clk_sysbypck: clk_sysbypck { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <800000000>; +- clock-output-names = "sysbypck"; +- }; +- +- /* external reference clock for MC. float in normal operation */ +- clk_mcbypck: clk_mcbypck { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <800000000>; +- clock-output-names = "mcbypck"; +- }; +- +- /* external clock signal rg1refck, supplied by the phy */ +- clk_rg1refck: clk_rg1refck { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- clock-output-names = "clk_rg1refck"; +- }; +- +- /* external clock signal rg2refck, supplied by the phy */ +- clk_rg2refck: clk_rg2refck { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- clock-output-names = "clk_rg2refck"; +- }; +- +- clk_xin: clk_xin { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- clock-output-names = "clk_xin"; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- ranges = <0x0 0xf0000000 0x00900000>; +- +- scu: scu@3fe000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0x3fe000 0x1000>; +- }; +- +- l2: cache-controller@3fc000 { +- compatible = "arm,pl310-cache"; +- reg = <0x3fc000 0x1000>; +- interrupts = ; +- cache-unified; +- cache-level = <2>; +- clocks = <&clk NPCM7XX_CLK_AXI>; +- arm,shared-override; +- }; +- +- gic: interrupt-controller@3ff000 { +- compatible = "arm,cortex-a9-gic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x3ff000 0x1000>, +- <0x3fe100 0x100>; +- }; +- +- gcr: gcr@800000 { +- compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd"; +- reg = <0x800000 0x1000>; +- }; +- +- rst: rst@801000 { +- compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd"; +- reg = <0x801000 0x6C>; +- }; +- }; +- +- ahb { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- ranges; +- +- rstc: rstc@f0801000 { +- compatible = "nuvoton,npcm750-reset"; +- reg = <0xf0801000 0x70>; +- #reset-cells = <2>; +- }; +- +- clk: clock-controller@f0801000 { +- compatible = "nuvoton,npcm750-clk", "syscon"; +- #clock-cells = <1>; +- clock-controller; +- reg = <0xf0801000 0x1000>; +- clock-names = "refclk", "sysbypck", "mcbypck"; +- clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; +- }; +- +- gmac0: eth@f0802000 { +- device_type = "network"; +- compatible = "snps,dwmac"; +- reg = <0xf0802000 0x2000>; +- interrupts = ; +- interrupt-names = "macirq"; +- ethernet = <0>; +- clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; +- clock-names = "stmmaceth", "clk_gmac"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rg1_pins +- &rg1mdio_pins>; +- status = "disabled"; +- }; +- +- ehci1: usb@f0806000 { +- compatible = "nuvoton,npcm750-ehci"; +- reg = <0xf0806000 0x1000>; +- interrupts = ; +- status = "disabled"; +- }; +- +- fiu0: spi@fb000000 { +- compatible = "nuvoton,npcm750-fiu"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xfb000000 0x1000>; +- reg-names = "control", "memory"; +- clocks = <&clk NPCM7XX_CLK_SPI0>; +- clock-names = "clk_spi0"; +- status = "disabled"; +- }; +- +- fiu3: spi@c0000000 { +- compatible = "nuvoton,npcm750-fiu"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xc0000000 0x1000>; +- reg-names = "control", "memory"; +- clocks = <&clk NPCM7XX_CLK_SPI3>; +- clock-names = "clk_spi3"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi3_pins>; +- status = "disabled"; +- }; +- +- fiux: spi@fb001000 { +- compatible = "nuvoton,npcm750-fiu"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xfb001000 0x1000>; +- reg-names = "control", "memory"; +- clocks = <&clk NPCM7XX_CLK_SPIX>; +- clock-names = "clk_spix"; +- status = "disabled"; +- }; +- +- apb { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- ranges = <0x0 0xf0000000 0x00300000>; +- +- lpc_kcs: lpc_kcs@7000 { +- compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon"; +- reg = <0x7000 0x40>; +- reg-io-width = <1>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x7000 0x40>; +- +- kcs1: kcs1@0 { +- compatible = "nuvoton,npcm750-kcs-bmc"; +- reg = <0x0 0x40>; +- interrupts = ; +- kcs_chan = <1>; +- status = "disabled"; +- }; +- +- kcs2: kcs2@0 { +- compatible = "nuvoton,npcm750-kcs-bmc"; +- reg = <0x0 0x40>; +- interrupts = ; +- kcs_chan = <2>; +- status = "disabled"; +- }; +- +- kcs3: kcs3@0 { +- compatible = "nuvoton,npcm750-kcs-bmc"; +- reg = <0x0 0x40>; +- interrupts = ; +- kcs_chan = <3>; +- status = "disabled"; +- }; +- }; +- +- spi0: spi@200000 { +- compatible = "nuvoton,npcm750-pspi"; +- reg = <0x200000 0x1000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pspi1_pins>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&clk NPCM7XX_CLK_APB5>; +- clock-names = "clk_apb5"; +- resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>; +- status = "disabled"; +- }; +- +- spi1: spi@201000 { +- compatible = "nuvoton,npcm750-pspi"; +- reg = <0x201000 0x1000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pspi2_pins>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&clk NPCM7XX_CLK_APB5>; +- clock-names = "clk_apb5"; +- resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI2>; +- status = "disabled"; +- }; +- +- timer0: timer@8000 { +- compatible = "nuvoton,npcm750-timer"; +- interrupts = ; +- reg = <0x8000 0x1C>; +- clocks = <&clk NPCM7XX_CLK_TIMER>; +- }; +- +- watchdog0: watchdog@801C { +- compatible = "nuvoton,npcm750-wdt"; +- interrupts = ; +- reg = <0x801C 0x4>; +- status = "disabled"; +- clocks = <&clk NPCM7XX_CLK_TIMER>; +- }; +- +- watchdog1: watchdog@901C { +- compatible = "nuvoton,npcm750-wdt"; +- interrupts = ; +- reg = <0x901C 0x4>; +- status = "disabled"; +- clocks = <&clk NPCM7XX_CLK_TIMER>; +- }; +- +- watchdog2: watchdog@a01C { +- compatible = "nuvoton,npcm750-wdt"; +- interrupts = ; +- reg = <0xa01C 0x4>; +- status = "disabled"; +- clocks = <&clk NPCM7XX_CLK_TIMER>; +- }; +- +- serial0: serial@1000 { +- compatible = "nuvoton,npcm750-uart"; +- reg = <0x1000 0x1000>; +- clocks = <&clk NPCM7XX_CLK_UART>; +- interrupts = ; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- serial1: serial@2000 { +- compatible = "nuvoton,npcm750-uart"; +- reg = <0x2000 0x1000>; +- clocks = <&clk NPCM7XX_CLK_UART>; +- interrupts = ; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- serial2: serial@3000 { +- compatible = "nuvoton,npcm750-uart"; +- reg = <0x3000 0x1000>; +- clocks = <&clk NPCM7XX_CLK_UART>; +- interrupts = ; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- serial3: serial@4000 { +- compatible = "nuvoton,npcm750-uart"; +- reg = <0x4000 0x1000>; +- clocks = <&clk NPCM7XX_CLK_UART>; +- interrupts = ; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- rng: rng@b000 { +- compatible = "nuvoton,npcm750-rng"; +- reg = <0xb000 0x8>; +- status = "disabled"; +- }; +- +- adc: adc@c000 { +- compatible = "nuvoton,npcm750-adc"; +- reg = <0xc000 0x8>; +- interrupts = ; +- clocks = <&clk NPCM7XX_CLK_ADC>; +- resets = <&rstc NPCM7XX_RESET_IPSRST1 NPCM7XX_RESET_ADC>; +- status = "disabled"; +- }; +- +- pwm_fan: pwm-fan-controller@103000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "nuvoton,npcm750-pwm-fan"; +- reg = <0x103000 0x2000>, <0x180000 0x8000>; +- reg-names = "pwm", "fan"; +- clocks = <&clk NPCM7XX_CLK_APB3>, +- <&clk NPCM7XX_CLK_APB4>; +- clock-names = "pwm","fan"; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pins &pwm1_pins +- &pwm2_pins &pwm3_pins +- &pwm4_pins &pwm5_pins +- &pwm6_pins &pwm7_pins +- &fanin0_pins &fanin1_pins +- &fanin2_pins &fanin3_pins +- &fanin4_pins &fanin5_pins +- &fanin6_pins &fanin7_pins +- &fanin8_pins &fanin9_pins +- &fanin10_pins &fanin11_pins +- &fanin12_pins &fanin13_pins +- &fanin14_pins &fanin15_pins>; +- status = "disabled"; +- }; +- +- i2c0: i2c@80000 { +- reg = <0x80000 0x1000>; +- compatible = "nuvoton,npcm750-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clk NPCM7XX_CLK_APB2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&smb0_pins>; +- status = "disabled"; +- }; +- +- i2c1: i2c@81000 { +- reg = <0x81000 0x1000>; +- compatible = "nuvoton,npcm750-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clk NPCM7XX_CLK_APB2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&smb1_pins>; +- status = "disabled"; +- }; +- +- i2c2: i2c@82000 { +- reg = <0x82000 0x1000>; +- compatible = "nuvoton,npcm750-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clk NPCM7XX_CLK_APB2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&smb2_pins>; +- status = "disabled"; +- }; +- +- i2c3: i2c@83000 { +- reg = <0x83000 0x1000>; +- compatible = "nuvoton,npcm750-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clk NPCM7XX_CLK_APB2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&smb3_pins>; +- status = "disabled"; +- }; +- +- i2c4: i2c@84000 { +- reg = <0x84000 0x1000>; +- compatible = "nuvoton,npcm750-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clk NPCM7XX_CLK_APB2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&smb4_pins>; +- status = "disabled"; +- }; +- +- i2c5: i2c@85000 { +- reg = <0x85000 0x1000>; +- compatible = "nuvoton,npcm750-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clk NPCM7XX_CLK_APB2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&smb5_pins>; +- status = "disabled"; +- }; +- +- i2c6: i2c@86000 { +- reg = <0x86000 0x1000>; +- compatible = "nuvoton,npcm750-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clk NPCM7XX_CLK_APB2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&smb6_pins>; +- status = "disabled"; +- }; +- +- i2c7: i2c@87000 { +- reg = <0x87000 0x1000>; +- compatible = "nuvoton,npcm750-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clk NPCM7XX_CLK_APB2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&smb7_pins>; +- status = "disabled"; +- }; +- +- i2c8: i2c@88000 { +- reg = <0x88000 0x1000>; +- compatible = "nuvoton,npcm750-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clk NPCM7XX_CLK_APB2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&smb8_pins>; +- status = "disabled"; +- }; +- +- i2c9: i2c@89000 { +- reg = <0x89000 0x1000>; +- compatible = "nuvoton,npcm750-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clk NPCM7XX_CLK_APB2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&smb9_pins>; +- status = "disabled"; +- }; +- +- i2c10: i2c@8a000 { +- reg = <0x8a000 0x1000>; +- compatible = "nuvoton,npcm750-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clk NPCM7XX_CLK_APB2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&smb10_pins>; +- status = "disabled"; +- }; +- +- i2c11: i2c@8b000 { +- reg = <0x8b000 0x1000>; +- compatible = "nuvoton,npcm750-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clk NPCM7XX_CLK_APB2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&smb11_pins>; +- status = "disabled"; +- }; +- +- i2c12: i2c@8c000 { +- reg = <0x8c000 0x1000>; +- compatible = "nuvoton,npcm750-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clk NPCM7XX_CLK_APB2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&smb12_pins>; +- status = "disabled"; +- }; +- +- i2c13: i2c@8d000 { +- reg = <0x8d000 0x1000>; +- compatible = "nuvoton,npcm750-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clk NPCM7XX_CLK_APB2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&smb13_pins>; +- status = "disabled"; +- }; +- +- i2c14: i2c@8e000 { +- reg = <0x8e000 0x1000>; +- compatible = "nuvoton,npcm750-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clk NPCM7XX_CLK_APB2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&smb14_pins>; +- status = "disabled"; +- }; +- +- i2c15: i2c@8f000 { +- reg = <0x8f000 0x1000>; +- compatible = "nuvoton,npcm750-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clk NPCM7XX_CLK_APB2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&smb15_pins>; +- status = "disabled"; +- }; +- }; +- }; +- +- pinctrl: pinctrl@f0800000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd"; +- ranges = <0 0xf0010000 0x8000>; +- gpio0: gpio@f0010000 { +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x0 0x80>; +- interrupts = ; +- gpio-ranges = <&pinctrl 0 0 32>; +- }; +- gpio1: gpio@f0011000 { +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x1000 0x80>; +- interrupts = ; +- gpio-ranges = <&pinctrl 0 32 32>; +- }; +- gpio2: gpio@f0012000 { +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x2000 0x80>; +- interrupts = ; +- gpio-ranges = <&pinctrl 0 64 32>; +- }; +- gpio3: gpio@f0013000 { +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x3000 0x80>; +- interrupts = ; +- gpio-ranges = <&pinctrl 0 96 32>; +- }; +- gpio4: gpio@f0014000 { +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x4000 0x80>; +- interrupts = ; +- gpio-ranges = <&pinctrl 0 128 32>; +- }; +- gpio5: gpio@f0015000 { +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x5000 0x80>; +- interrupts = ; +- gpio-ranges = <&pinctrl 0 160 32>; +- }; +- gpio6: gpio@f0016000 { +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x6000 0x80>; +- interrupts = ; +- gpio-ranges = <&pinctrl 0 192 32>; +- }; +- gpio7: gpio@f0017000 { +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x7000 0x80>; +- interrupts = ; +- gpio-ranges = <&pinctrl 0 224 32>; +- }; +- +- iox1_pins: iox1-pins { +- groups = "iox1"; +- function = "iox1"; +- }; +- iox2_pins: iox2-pins { +- groups = "iox2"; +- function = "iox2"; +- }; +- smb1d_pins: smb1d-pins { +- groups = "smb1d"; +- function = "smb1d"; +- }; +- smb2d_pins: smb2d-pins { +- groups = "smb2d"; +- function = "smb2d"; +- }; +- lkgpo1_pins: lkgpo1-pins { +- groups = "lkgpo1"; +- function = "lkgpo1"; +- }; +- lkgpo2_pins: lkgpo2-pins { +- groups = "lkgpo2"; +- function = "lkgpo2"; +- }; +- ioxh_pins: ioxh-pins { +- groups = "ioxh"; +- function = "ioxh"; +- }; +- gspi_pins: gspi-pins { +- groups = "gspi"; +- function = "gspi"; +- }; +- smb5b_pins: smb5b-pins { +- groups = "smb5b"; +- function = "smb5b"; +- }; +- smb5c_pins: smb5c-pins { +- groups = "smb5c"; +- function = "smb5c"; +- }; +- lkgpo0_pins: lkgpo0-pins { +- groups = "lkgpo0"; +- function = "lkgpo0"; +- }; +- pspi2_pins: pspi2-pins { +- groups = "pspi2"; +- function = "pspi2"; +- }; +- smb4den_pins: smb4den-pins { +- groups = "smb4den"; +- function = "smb4den"; +- }; +- smb4b_pins: smb4b-pins { +- groups = "smb4b"; +- function = "smb4b"; +- }; +- smb4c_pins: smb4c-pins { +- groups = "smb4c"; +- function = "smb4c"; +- }; +- smb15_pins: smb15-pins { +- groups = "smb15"; +- function = "smb15"; +- }; +- smb4d_pins: smb4d-pins { +- groups = "smb4d"; +- function = "smb4d"; +- }; +- smb14_pins: smb14-pins { +- groups = "smb14"; +- function = "smb14"; +- }; +- smb5_pins: smb5-pins { +- groups = "smb5"; +- function = "smb5"; +- }; +- smb4_pins: smb4-pins { +- groups = "smb4"; +- function = "smb4"; +- }; +- smb3_pins: smb3-pins { +- groups = "smb3"; +- function = "smb3"; +- }; +- spi0cs1_pins: spi0cs1-pins { +- groups = "spi0cs1"; +- function = "spi0cs1"; +- }; +- spi0cs2_pins: spi0cs2-pins { +- groups = "spi0cs2"; +- function = "spi0cs2"; +- }; +- spi0cs3_pins: spi0cs3-pins { +- groups = "spi0cs3"; +- function = "spi0cs3"; +- }; +- smb3c_pins: smb3c-pins { +- groups = "smb3c"; +- function = "smb3c"; +- }; +- smb3b_pins: smb3b-pins { +- groups = "smb3b"; +- function = "smb3b"; +- }; +- bmcuart0a_pins: bmcuart0a-pins { +- groups = "bmcuart0a"; +- function = "bmcuart0a"; +- }; +- uart1_pins: uart1-pins { +- groups = "uart1"; +- function = "uart1"; +- }; +- jtag2_pins: jtag2-pins { +- groups = "jtag2"; +- function = "jtag2"; +- }; +- bmcuart1_pins: bmcuart1-pins { +- groups = "bmcuart1"; +- function = "bmcuart1"; +- }; +- uart2_pins: uart2-pins { +- groups = "uart2"; +- function = "uart2"; +- }; +- bmcuart0b_pins: bmcuart0b-pins { +- groups = "bmcuart0b"; +- function = "bmcuart0b"; +- }; +- r1err_pins: r1err-pins { +- groups = "r1err"; +- function = "r1err"; +- }; +- r1md_pins: r1md-pins { +- groups = "r1md"; +- function = "r1md"; +- }; +- smb3d_pins: smb3d-pins { +- groups = "smb3d"; +- function = "smb3d"; +- }; +- fanin0_pins: fanin0-pins { +- groups = "fanin0"; +- function = "fanin0"; +- }; +- fanin1_pins: fanin1-pins { +- groups = "fanin1"; +- function = "fanin1"; +- }; +- fanin2_pins: fanin2-pins { +- groups = "fanin2"; +- function = "fanin2"; +- }; +- fanin3_pins: fanin3-pins { +- groups = "fanin3"; +- function = "fanin3"; +- }; +- fanin4_pins: fanin4-pins { +- groups = "fanin4"; +- function = "fanin4"; +- }; +- fanin5_pins: fanin5-pins { +- groups = "fanin5"; +- function = "fanin5"; +- }; +- fanin6_pins: fanin6-pins { +- groups = "fanin6"; +- function = "fanin6"; +- }; +- fanin7_pins: fanin7-pins { +- groups = "fanin7"; +- function = "fanin7"; +- }; +- fanin8_pins: fanin8-pins { +- groups = "fanin8"; +- function = "fanin8"; +- }; +- fanin9_pins: fanin9-pins { +- groups = "fanin9"; +- function = "fanin9"; +- }; +- fanin10_pins: fanin10-pins { +- groups = "fanin10"; +- function = "fanin10"; +- }; +- fanin11_pins: fanin11-pins { +- groups = "fanin11"; +- function = "fanin11"; +- }; +- fanin12_pins: fanin12-pins { +- groups = "fanin12"; +- function = "fanin12"; +- }; +- fanin13_pins: fanin13-pins { +- groups = "fanin13"; +- function = "fanin13"; +- }; +- fanin14_pins: fanin14-pins { +- groups = "fanin14"; +- function = "fanin14"; +- }; +- fanin15_pins: fanin15-pins { +- groups = "fanin15"; +- function = "fanin15"; +- }; +- pwm0_pins: pwm0-pins { +- groups = "pwm0"; +- function = "pwm0"; +- }; +- pwm1_pins: pwm1-pins { +- groups = "pwm1"; +- function = "pwm1"; +- }; +- pwm2_pins: pwm2-pins { +- groups = "pwm2"; +- function = "pwm2"; +- }; +- pwm3_pins: pwm3-pins { +- groups = "pwm3"; +- function = "pwm3"; +- }; +- r2_pins: r2-pins { +- groups = "r2"; +- function = "r2"; +- }; +- r2err_pins: r2err-pins { +- groups = "r2err"; +- function = "r2err"; +- }; +- r2md_pins: r2md-pins { +- groups = "r2md"; +- function = "r2md"; +- }; +- ga20kbc_pins: ga20kbc-pins { +- groups = "ga20kbc"; +- function = "ga20kbc"; +- }; +- smb5d_pins: smb5d-pins { +- groups = "smb5d"; +- function = "smb5d"; +- }; +- lpc_pins: lpc-pins { +- groups = "lpc"; +- function = "lpc"; +- }; +- espi_pins: espi-pins { +- groups = "espi"; +- function = "espi"; +- }; +- rg1_pins: rg1-pins { +- groups = "rg1"; +- function = "rg1"; +- }; +- rg1mdio_pins: rg1mdio-pins { +- groups = "rg1mdio"; +- function = "rg1mdio"; +- }; +- rg2_pins: rg2-pins { +- groups = "rg2"; +- function = "rg2"; +- }; +- ddr_pins: ddr-pins { +- groups = "ddr"; +- function = "ddr"; +- }; +- smb0_pins: smb0-pins { +- groups = "smb0"; +- function = "smb0"; +- }; +- smb1_pins: smb1-pins { +- groups = "smb1"; +- function = "smb1"; +- }; +- smb2_pins: smb2-pins { +- groups = "smb2"; +- function = "smb2"; +- }; +- smb2c_pins: smb2c-pins { +- groups = "smb2c"; +- function = "smb2c"; +- }; +- smb2b_pins: smb2b-pins { +- groups = "smb2b"; +- function = "smb2b"; +- }; +- smb1c_pins: smb1c-pins { +- groups = "smb1c"; +- function = "smb1c"; +- }; +- smb1b_pins: smb1b-pins { +- groups = "smb1b"; +- function = "smb1b"; +- }; +- smb8_pins: smb8-pins { +- groups = "smb8"; +- function = "smb8"; +- }; +- smb9_pins: smb9-pins { +- groups = "smb9"; +- function = "smb9"; +- }; +- smb10_pins: smb10-pins { +- groups = "smb10"; +- function = "smb10"; +- }; +- smb11_pins: smb11-pins { +- groups = "smb11"; +- function = "smb11"; +- }; +- sd1_pins: sd1-pins { +- groups = "sd1"; +- function = "sd1"; +- }; +- sd1pwr_pins: sd1pwr-pins { +- groups = "sd1pwr"; +- function = "sd1pwr"; +- }; +- pwm4_pins: pwm4-pins { +- groups = "pwm4"; +- function = "pwm4"; +- }; +- pwm5_pins: pwm5-pins { +- groups = "pwm5"; +- function = "pwm5"; +- }; +- pwm6_pins: pwm6-pins { +- groups = "pwm6"; +- function = "pwm6"; +- }; +- pwm7_pins: pwm7-pins { +- groups = "pwm7"; +- function = "pwm7"; +- }; +- mmc8_pins: mmc8-pins { +- groups = "mmc8"; +- function = "mmc8"; +- }; +- mmc_pins: mmc-pins { +- groups = "mmc"; +- function = "mmc"; +- }; +- mmcwp_pins: mmcwp-pins { +- groups = "mmcwp"; +- function = "mmcwp"; +- }; +- mmccd_pins: mmccd-pins { +- groups = "mmccd"; +- function = "mmccd"; +- }; +- mmcrst_pins: mmcrst-pins { +- groups = "mmcrst"; +- function = "mmcrst"; +- }; +- clkout_pins: clkout-pins { +- groups = "clkout"; +- function = "clkout"; +- }; +- serirq_pins: serirq-pins { +- groups = "serirq"; +- function = "serirq"; +- }; +- lpcclk_pins: lpcclk-pins { +- groups = "lpcclk"; +- function = "lpcclk"; +- }; +- scipme_pins: scipme-pins { +- groups = "scipme"; +- function = "scipme"; +- }; +- sci_pins: sci-pins { +- groups = "sci"; +- function = "sci"; +- }; +- smb6_pins: smb6-pins { +- groups = "smb6"; +- function = "smb6"; +- }; +- smb7_pins: smb7-pins { +- groups = "smb7"; +- function = "smb7"; +- }; +- pspi1_pins: pspi1-pins { +- groups = "pspi1"; +- function = "pspi1"; +- }; +- faninx_pins: faninx-pins { +- groups = "faninx"; +- function = "faninx"; +- }; +- r1_pins: r1-pins { +- groups = "r1"; +- function = "r1"; +- }; +- spi3_pins: spi3-pins { +- groups = "spi3"; +- function = "spi3"; +- }; +- spi3cs1_pins: spi3cs1-pins { +- groups = "spi3cs1"; +- function = "spi3cs1"; +- }; +- spi3quad_pins: spi3quad-pins { +- groups = "spi3quad"; +- function = "spi3quad"; +- }; +- spi3cs2_pins: spi3cs2-pins { +- groups = "spi3cs2"; +- function = "spi3cs2"; +- }; +- spi3cs3_pins: spi3cs3-pins { +- groups = "spi3cs3"; +- function = "spi3cs3"; +- }; +- nprd_smi_pins: nprd-smi-pins { +- groups = "nprd_smi"; +- function = "nprd_smi"; +- }; +- smb0b_pins: smb0b-pins { +- groups = "smb0b"; +- function = "smb0b"; +- }; +- smb0c_pins: smb0c-pins { +- groups = "smb0c"; +- function = "smb0c"; +- }; +- smb0den_pins: smb0den-pins { +- groups = "smb0den"; +- function = "smb0den"; +- }; +- smb0d_pins: smb0d-pins { +- groups = "smb0d"; +- function = "smb0d"; +- }; +- ddc_pins: ddc-pins { +- groups = "ddc"; +- function = "ddc"; +- }; +- rg2mdio_pins: rg2mdio-pins { +- groups = "rg2mdio"; +- function = "rg2mdio"; +- }; +- wdog1_pins: wdog1-pins { +- groups = "wdog1"; +- function = "wdog1"; +- }; +- wdog2_pins: wdog2-pins { +- groups = "wdog2"; +- function = "wdog2"; +- }; +- smb12_pins: smb12-pins { +- groups = "smb12"; +- function = "smb12"; +- }; +- smb13_pins: smb13-pins { +- groups = "smb13"; +- function = "smb13"; +- }; +- spix_pins: spix-pins { +- groups = "spix"; +- function = "spix"; +- }; +- spixcs1_pins: spixcs1-pins { +- groups = "spixcs1"; +- function = "spixcs1"; +- }; +- clkreq_pins: clkreq-pins { +- groups = "clkreq"; +- function = "clkreq"; +- }; +- hgpio0_pins: hgpio0-pins { +- groups = "hgpio0"; +- function = "hgpio0"; +- }; +- hgpio1_pins: hgpio1-pins { +- groups = "hgpio1"; +- function = "hgpio1"; +- }; +- hgpio2_pins: hgpio2-pins { +- groups = "hgpio2"; +- function = "hgpio2"; +- }; +- hgpio3_pins: hgpio3-pins { +- groups = "hgpio3"; +- function = "hgpio3"; +- }; +- hgpio4_pins: hgpio4-pins { +- groups = "hgpio4"; +- function = "hgpio4"; +- }; +- hgpio5_pins: hgpio5-pins { +- groups = "hgpio5"; +- function = "hgpio5"; +- }; +- hgpio6_pins: hgpio6-pins { +- groups = "hgpio6"; +- function = "hgpio6"; +- }; +- hgpio7_pins: hgpio7-pins { +- groups = "hgpio7"; +- function = "hgpio7"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/nuvoton-npcm730-gbs.dts b/scripts/dtc/include-prefixes/arm/nuvoton-npcm730-gbs.dts +deleted file mode 100644 +index eb6eb21cb2a4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/nuvoton-npcm730-gbs.dts ++++ /dev/null +@@ -1,1135 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2020 Quanta Computer Inc. George.Hung@quantatw.com +- +-/dts-v1/; +-#include "nuvoton-npcm730.dtsi" +-#include +- +-/ { +- model = "Quanta GBS Board (Device Tree)"; +- compatible = "quanta,gbs-bmc","nuvoton,npcm730"; +- +- aliases { +- ethernet1 = &gmac0; +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c7; +- i2c8 = &i2c8; +- i2c9 = &i2c9; +- i2c10 = &i2c10; +- i2c11 = &i2c11; +- i2c12 = &i2c12; +- i2c13 = &i2c13; +- i2c14 = &i2c14; +- i2c15 = &i2c15; +- i2c16 = &i2c0_slotPE0_0; +- i2c17 = &i2c0_slotPE1_1; +- i2c18 = &i2c0_slotUSB_2; +- i2c19 = &i2c0_3; +- i2c20 = &i2c5_i2cool_0; +- i2c21 = &i2c5_i2cool_1; +- i2c22 = &i2c5_i2cool_2; +- i2c23 = &i2c5_hsbp_fru_3; +- i2c24 = &i2c6_u2_15_0; +- i2c25 = &i2c6_u2_14_1; +- i2c26 = &i2c6_u2_13_2; +- i2c27 = &i2c6_u2_12_3; +- i2c28 = &i2c7_u2_11_0; +- i2c29 = &i2c7_u2_10_1; +- i2c30 = &i2c7_u2_9_2; +- i2c31 = &i2c7_u2_8_3; +- i2c32 = &i2c9_vddcr_cpu; +- i2c33 = &i2c9_vddcr_soc; +- i2c34 = &i2c9_vddio_efgh; +- i2c35 = &i2c9_vddio_abcd; +- i2c36 = &i2c10_u2_7_0; +- i2c37 = &i2c10_u2_6_1; +- i2c38 = &i2c10_u2_5_2; +- i2c39 = &i2c10_u2_4_3; +- i2c40 = &i2c11_clk_buf0_0; +- i2c41 = &i2c11_clk_buf1_1; +- i2c42 = &i2c11_clk_buf2_2; +- i2c43 = &i2c11_clk_buf3_3; +- i2c44 = &i2c14_u2_3_0; +- i2c45 = &i2c14_u2_2_1; +- i2c46 = &i2c14_u2_1_2; +- i2c47 = &i2c14_u2_0_3; +- fiu0 = &fiu0; +- fiu1 = &fiu3; +- }; +- +- chosen { +- stdout-path = &serial0; +- }; +- +- memory { +- reg = <0 0x40000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- sas-cable0 { +- label = "sas-cable0"; +- gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; +- linux,code = <73>; +- }; +- +- sas-cable1 { +- label = "sas-cable1"; +- gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; +- linux,code = <72>; +- }; +- +- sas-cable2 { +- label = "sas-cable2"; +- gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; +- linux,code = <71>; +- }; +- +- sas-cable3 { +- label = "sas-cable3"; +- gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; +- linux,code = <70>; +- }; +- +- sata0 { +- label = "sata0"; +- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; +- linux,code = <5>; +- }; +- +- hsbp-cable { +- label = "hsbp-cable"; +- gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; +- linux,code = <57>; +- }; +- +- fanbd-cable { +- label = "fanbd-cable"; +- gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- linux,code = <58>; +- }; +- +- bp12v-cable { +- label = "bp12v-cable"; +- gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; +- linux,code = <69>; +- }; +- +- pe-slot0 { +- label = "pe-slot0"; +- gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; +- linux,code = <120>; +- }; +- +- pe-slot1 { +- label = "pe-slot1"; +- gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; +- linux,code = <121>; +- }; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 1>, <&adc 2>; +- }; +- +- iio-hwmon-battery { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- heartbeat { /* gpio153 */ +- gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- +- attention { /* gpio215 */ +- gpios = <&gpio6 23 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- sys_boot_status { /* gpio216 */ +- gpios = <&gpio6 24 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; +- retain-state-shutdown; +- }; +- +- bmc_fault { /* gpio217 */ +- gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "panic"; +- panic-indicator; +- }; +- +- led_u2_0_locate { +- gpios = <&pca9535_ledlocate 3 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_1_locate { +- gpios = <&pca9535_ledlocate 2 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_2_locate { +- gpios = <&pca9535_ledlocate 1 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_3_locate { +- gpios = <&pca9535_ledlocate 0 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_4_locate { +- gpios = <&pca9535_ledlocate 7 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_5_locate { +- gpios = <&pca9535_ledlocate 6 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_6_locate { +- gpios = <&pca9535_ledlocate 5 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_7_locate { +- gpios = <&pca9535_ledlocate 4 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_8_locate { +- gpios = <&pca9535_ledlocate 11 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_9_locate { +- gpios = <&pca9535_ledlocate 10 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_10_locate { +- gpios = <&pca9535_ledlocate 9 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_11_locate { +- gpios = <&pca9535_ledlocate 8 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_12_locate { +- gpios = <&pca9535_ledlocate 15 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_13_locate { +- gpios = <&pca9535_ledlocate 14 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_14_locate { +- gpios = <&pca9535_ledlocate 13 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_15_locate { +- gpios = <&pca9535_ledlocate 12 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_0_fault { +- gpios = <&pca9535_ledfault 3 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_1_fault { +- gpios = <&pca9535_ledfault 2 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_2_fault { +- gpios = <&pca9535_ledfault 1 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_3_fault { +- gpios = <&pca9535_ledfault 0 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_4_fault { +- gpios = <&pca9535_ledfault 7 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_5_fault { +- gpios = <&pca9535_ledfault 6 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_6_fault { +- gpios = <&pca9535_ledfault 5 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_7_fault { +- gpios = <&pca9535_ledfault 4 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_8_fault { +- gpios = <&pca9535_ledfault 11 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_9_fault { +- gpios = <&pca9535_ledfault 10 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_10_fault { +- gpios = <&pca9535_ledfault 9 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_11_fault { +- gpios = <&pca9535_ledfault 8 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_12_fault { +- gpios = <&pca9535_ledfault 15 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_13_fault { +- gpios = <&pca9535_ledfault 14 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_14_fault { +- gpios = <&pca9535_ledfault 13 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led_u2_15_fault { +- gpios = <&pca9535_ledfault 12 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- }; +- +- seven-seg-disp { +- compatible = "seven-seg-gpio-dev"; +- refresh-interval-ms = /bits/ 16 <600>; +- clock-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; +- data-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; +- clear-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; +- }; +- +- pcie-slot { +- pcie1: pcie-slot@1 { +- label = "PE0"; +- }; +- pcie2: pcie-slot@2 { +- label = "PE1"; +- }; +- }; +-}; +- +-&fiu0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0cs1_pins>; +- status = "okay"; +- spi-nor@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- spi-max-frequency = <20000000>; +- spi-rx-bus-width = <2>; +- label = "bmc"; +- partitions@80000000 { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- u-boot@0 { +- label = "u-boot"; +- reg = <0x0000000 0xf0000>; +- }; +- image-descriptor@f0000 { +- label = "image-descriptor"; +- reg = <0xf0000 0x10000>; +- }; +- hoth-update@100000 { +- label = "hoth-update"; +- reg = <0x100000 0x100000>; +- }; +- kernel@200000 { +- label = "kernel"; +- reg = <0x200000 0x500000>; +- }; +- rofs@700000 { +- label = "rofs"; +- reg = <0x700000 0x35f0000>; +- }; +- rwfs@3cf0000 { +- label = "rwfs"; +- reg = <0x3cf0000 0x300000>; +- }; +- hoth-mailbox@3ff0000 { +- label = "hoth-mailbox"; +- reg = <0x3ff0000 0x10000>; +- }; +- }; +- }; +-}; +- +-&fiu3 { +- pinctrl-0 = <&spi3_pins>, <&spi3cs1_pins>; +- status = "okay"; +- +- spi-nor@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- spi-max-frequency = <50000000>; +- spi-rx-bus-width = <2>; +- m25p,fast-read; +- label = "pnor"; +- }; +- spi-nor@1 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <1>; +- spi-max-frequency = <50000000>; +- spi-rx-bus-width = <2>; +- m25p,fast-read; +- }; +-}; +- +-&gcr { +- serial_port_mux: uart-mux-controller { +- compatible = "mmio-mux"; +- #mux-control-cells = <1>; +- mux-reg-masks = <0x38 0x07>; +- idle-states = <2>; /* Serial port mode 3 (takeover) */ +- }; +- +- uart1_mode_mux: uart1-mode-mux-controller { +- compatible = "mmio-mux"; +- #mux-control-cells = <1>; +- mux-reg-masks = <0x64 0x01000000>; +- idle-states = <0>; /* Set UART1 mode to normal (follow SPMOD) */ +- }; +-}; +- +-&gmac0 { +- status = "okay"; +- phy-mode = "rgmii-id"; +- snps,eee-force-disable; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&watchdog1 { +- status = "okay"; +-}; +- +-&rng { +- status = "okay"; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&serial1 { +- status = "okay"; +-}; +- +-&serial2 { +- status = "okay"; +-}; +- +-&serial3 { +- status = "okay"; +-}; +- +-&adc { +- #io-channel-cells = <1>; +- status = "okay"; +-}; +- +-&lpc_kcs { +- kcs1: kcs1@0 { +- status = "okay"; +- }; +- +- kcs2: kcs2@0 { +- status = "okay"; +- }; +- +- kcs3: kcs3@0 { +- status = "okay"; +- }; +-}; +- +-&spi1 { +- cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; /* dummy - gpio147 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio224ol_pins &gpio227o_pins +- &gpio228_pins>; +- status = "okay"; +- +- jtag_master@0 { +- compatible = "nuvoton,npcm750-jtag-master"; +- spi-max-frequency = <25000000>; +- reg = <0>; +- status = "okay"; +- +- pinctrl-names = "pspi", "gpio"; +- pinctrl-0 = <&pspi2_pins>; +- pinctrl-1 = <&gpio224ol_pins &gpio227o_pins +- &gpio228_pins>; +- +- tck-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; +- tdi-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; +- tdo-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; +- tms-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&i2c0 { +- clock-frequency = <100000>; +- status = "okay"; +- +- i2c-switch@71 { +- compatible = "nxp,pca9546"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x71>; +- i2c-mux-idle-disconnect; +- reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; +- +- i2c0_slotPE0_0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- pcie-slot = &pcie1; +- }; +- +- i2c0_slotPE1_1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- pcie-slot = &pcie2; +- }; +- +- i2c0_slotUSB_2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c0_3: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- status = "okay"; +- +- pca9535_ifdet: pca9535-ifdet@24 { +- compatible = "nxp,pca9535"; +- reg = <0x24>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- pca9535_pwren: pca9535-pwren@20 { +- compatible = "nxp,pca9535"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio-line-names = +- "pwr_u2_3_en","pwr_u2_2_en", +- "pwr_u2_1_en","pwr_u2_0_en", +- "pwr_u2_7_en","pwr_u2_6_en", +- "pwr_u2_5_en","pwr_u2_4_en", +- "pwr_u2_11_en","pwr_u2_10_en", +- "pwr_u2_9_en","pwr_u2_8_en", +- "pwr_u2_15_en","pwr_u2_14_en", +- "pwr_u2_13_en","pwr_u2_12_en"; +- }; +- +- pca9535_pwrgd: pca9535-pwrgd@21 { +- compatible = "nxp,pca9535"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- pca9535_ledlocate: pca9535-ledlocate@22 { +- compatible = "nxp,pca9535"; +- reg = <0x22>; +- gpio-controller; +- #gpio-cells = <2>; +- +- }; +- +- pca9535_ledfault: pca9535-ledfault@23 { +- compatible = "nxp,pca9535"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- +- }; +- +- pca9535_pwrdisable: pca9535-pwrdisable@25 { +- compatible = "nxp,pca9535"; +- reg = <0x25>; +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio-line-names = +- "u2_3_pwr_dis","u2_2_pwr_dis", +- "u2_1_pwr_dis","u2_0_pwr_dis", +- "u2_7_pwr_dis","u2_6_pwr_dis", +- "u2_5_pwr_dis","u2_4_pwr_dis", +- "u2_11_pwr_dis","u2_10_pwr_dis", +- "u2_9_pwr_dis","u2_8_pwr_dis", +- "u2_15_pwr_dis","u2_14_pwr_dis", +- "u2_13_pwr_dis","u2_12_pwr_dis"; +- }; +- +- pca9535_perst: pca9535-perst@26 { +- compatible = "nxp,pca9535"; +- reg = <0x26>; +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio-line-names = +- "u2_15_perst","u2_14_perst", +- "u2_13_perst","u2_12_perst", +- "u2_11_perst","u2_10_perst", +- "u2_9_perst","u2_8_perst", +- "u2_7_perst","u2_6_perst", +- "u2_5_perst","u2_4_perst", +- "u2_3_perst","u2_2_perst", +- "u2_1_perst","u2_0_perst"; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- status = "okay"; +- +- sbtsi@4c { +- compatible = "amd,sbtsi"; +- reg = <0x4c>; +- }; +-}; +- +-&i2c5 { +- clock-frequency = <100000>; +- status = "okay"; +- +- mb_fru@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- +- i2c-switch@71 { +- compatible = "nxp,pca9546"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x71>; +- i2c-mux-idle-disconnect; +- +- i2c5_i2cool_0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- max31725@54 { +- compatible = "maxim,max31725"; +- reg = <0x54>; +- status = "okay"; +- }; +- }; +- +- i2c5_i2cool_1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- max31725@55 { +- compatible = "maxim,max31725"; +- reg = <0x55>; +- status = "okay"; +- }; +- }; +- +- i2c5_i2cool_2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- max31725@5d { +- compatible = "maxim,max31725"; +- reg = <0x5d>; +- status = "okay"; +- }; +- fan_fru@51 { +- compatible = "atmel,24c64"; +- reg = <0x51>; +- }; +- }; +- +- i2c5_hsbp_fru_3: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- hsbp_fru@52 { +- compatible = "atmel,24c64"; +- reg = <0x52>; +- status = "okay"; +- }; +- }; +- }; +-}; +- +-&i2c6 { +- clock-frequency = <100000>; +- status = "okay"; +- +- i2c-switch@73 { +- compatible = "nxp,pca9545"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x73>; +- i2c-mux-idle-disconnect; +- +- i2c6_u2_15_0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c6_u2_14_1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- i2c6_u2_13_2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c6_u2_12_3: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +-}; +- +-&i2c7 { +- clock-frequency = <100000>; +- status = "okay"; +- +- i2c-switch@72 { +- compatible = "nxp,pca9545"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x72>; +- i2c-mux-idle-disconnect; +- +- i2c7_u2_11_0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c7_u2_10_1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- i2c7_u2_9_2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c7_u2_8_3: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +-}; +- +-&i2c8 { +- clock-frequency = <100000>; +- status = "okay"; +- +- i2c8_adm1272: adm1272@10 { +- compatible = "adi,adm1272"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x10>; +- shunt-resistor-micro-ohms = <300>; +- }; +-}; +- +-&i2c9 { +- clock-frequency = <100000>; +- status = "okay"; +- +- i2c-switch@71 { +- compatible = "nxp,pca9546"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x71>; +- i2c-mux-idle-disconnect; +- reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; +- +- i2c9_vddcr_cpu: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- vrm@60 { +- compatible = "isil,isl68137"; +- reg = <0x60>; +- }; +- }; +- +- i2c9_vddcr_soc: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- vrm@61 { +- compatible = "isil,isl68137"; +- reg = <0x61>; +- }; +- }; +- +- i2c9_vddio_efgh: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- vrm@63 { +- compatible = "isil,isl68137"; +- reg = <0x63>; +- }; +- }; +- +- i2c9_vddio_abcd: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- vrm@45 { +- compatible = "isil,isl68137"; +- reg = <0x45>; +- }; +- }; +- }; +-}; +- +-&i2c10 { +- clock-frequency = <100000>; +- status = "okay"; +- +- i2c-switch@71 { +- compatible = "nxp,pca9545"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x71>; +- i2c-mux-idle-disconnect; +- +- i2c10_u2_7_0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c10_u2_6_1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- i2c10_u2_5_2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c10_u2_4_3: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +-}; +- +-&i2c11 { +- clock-frequency = <100000>; +- status = "okay"; +- +- i2c-switch@76 { +- compatible = "nxp,pca9545"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x76>; +- i2c-mux-idle-disconnect; +- +- i2c11_clk_buf0_0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c11_clk_buf1_1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- i2c11_clk_buf2_2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c11_clk_buf3_3: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +-}; +- +-&i2c12 { +- clock-frequency = <100000>; +- status = "okay"; +- +- max34451@4e { +- compatible = "maxim,max34451"; +- reg = <0x4e>; +- }; +- vrm@5d { +- compatible = "isil,isl68137"; +- reg = <0x5d>; +- }; +- vrm@5e { +- compatible = "isil,isl68137"; +- reg = <0x5e>; +- }; +-}; +- +-&i2c13 { +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&i2c14 { +- clock-frequency = <100000>; +- status = "okay"; +- +- i2c-switch@70 { +- compatible = "nxp,pca9545"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- i2c14_u2_3_0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c14_u2_2_1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- i2c14_u2_1_2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c14_u2_0_3: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +-}; +- +-&pwm_fan { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &pwm0_pins &pwm1_pins +- &pwm2_pins &pwm3_pins +- &pwm4_pins +- &fanin0_pins &fanin1_pins +- &fanin2_pins &fanin3_pins +- &fanin4_pins +- >; +- status = "okay"; +- +- fan@0 { +- reg = <0x00>; +- fan-tach-ch = /bits/ 8 <0x00>; +- }; +- fan@1 { +- reg = <0x01>; +- fan-tach-ch = /bits/ 8 <0x01>; +- }; +- fan@2 { +- reg = <0x02>; +- fan-tach-ch = /bits/ 8 <0x02>; +- }; +- fan@3 { +- reg = <0x04>; +- fan-tach-ch = /bits/ 8 <0x04>; +- }; +- fan@4 { +- reg = <0x03>; +- fan-tach-ch = /bits/ 8 <0x03>; +- }; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- +- gpio0: gpio@f0010000 { +- /* POWER_OUT=gpio07, RESET_OUT=gpio06, PS_PWROK=gpio13 */ +- gpio-line-names = +- /*0-31*/ +- "","","","","","","RESET_OUT","POWER_OUT", +- "","","","","","PS_PWROK","","", +- "","","","","","","","", +- "","","","","","","",""; +- }; +- gpio1: gpio@f0011000 { +- /* SIO_POWER_GOOD=gpio59 */ +- gpio-line-names = +- /*32-63*/ +- "","","","","","","","", +- "","","","","","","","", +- "","","","","","","","", +- "","","","SIO_POWER_GOOD","","","",""; +- }; +- gpio2: gpio@f0012000 { +- bmc_usb_mux_oe_n { +- gpio-hog; +- gpios = <25 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "bmc-usb-mux-oe-n"; +- }; +- bmc_usb_mux_sel { +- gpio-hog; +- gpios = <26 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "bmc-usb-mux-sel"; +- }; +- bmc_usb2517_reset_n { +- gpio-hog; +- gpios = <27 GPIO_ACTIVE_LOW>; +- output-low; +- line-name = "bmc-usb2517-reset-n"; +- }; +- }; +- gpio3: gpio@f0013000 { +- assert_cpu0_reset { +- gpio-hog; +- gpios = <14 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "assert-cpu0-reset"; +- }; +- assert_pwrok_cpu0_n { +- gpio-hog; +- gpios = <15 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "assert-pwrok-cpu0-n"; +- }; +- assert_cpu0_prochot { +- gpio-hog; +- gpios = <16 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "assert-cpu0-prochot"; +- }; +- }; +- gpio4: gpio@f0014000 { +- /* POST_COMPLETE=gpio143 */ +- gpio-line-names = +- /*128-159*/ +- "","","","","","","","", +- "","","","","","","","POST_COMPLETE", +- "","","","","","","","", +- "","","","","","","",""; +- }; +- gpio5: gpio@f0015000 { +- /* POWER_BUTTON=gpio177 */ +- gpio-line-names = +- /*160-191*/ +- "","","","","","","","", +- "","","","","","","","", +- "","POWER_BUTTON","","","","","","", +- "","","","","","","",""; +- }; +- gpio6: gpio@f0016000 { +- /* SIO_S5=gpio199, RESET_BUTTON=gpio203 */ +- gpio-line-names = +- /*192-223*/ +- "","","","","","","","SIO_S5", +- "","","","RESET_BUTTON","","","","", +- "","","","","","","","", +- "","","","","","","",""; +- }; +- +- gpio224ol_pins: gpio224ol-pins { +- pins = "GPIO224/SPIXCK"; +- bias-disable; +- output-low; +- }; +- gpio227o_pins: gpio227o-pins { +- pins = "GPIO227/nSPIXCS0"; +- bias-disable; +- output-high; +- }; +- gpio228_pins: gpio228-pins { +- pins = "GPIO228/nSPIXCS1"; +- bias-disable; +- input-enable; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/nuvoton-npcm730-gsj-gpio.dtsi b/scripts/dtc/include-prefixes/arm/nuvoton-npcm730-gsj-gpio.dtsi +deleted file mode 100644 +index 53cfd15fa03f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/nuvoton-npcm730-gsj-gpio.dtsi ++++ /dev/null +@@ -1,477 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com +- +-/ { +- pinctrl: pinctrl@f0800000 { +- gpio0pp_pins: gpio0pp-pins { +- pins = "GPIO0/IOX1DI"; +- bias-disable; +- drive-push-pull; +- }; +- gpio1pp_pins: gpio1pp-pins { +- pins = "GPIO1/IOX1LD"; +- bias-disable; +- drive-push-pull; +- }; +- gpio2pp_pins: gpio2pp-pins { +- pins = "GPIO2/IOX1CK"; +- bias-disable; +- drive-push-pull; +- }; +- gpio3pp_pins: gpio3pp-pins { +- pins = "GPIO3/IOX1D0"; +- bias-disable; +- drive-push-pull; +- }; +- gpio4pp_pins: gpio4pp-pins { +- pins = "GPIO4/IOX2DI/SMB1DSDA"; +- bias-disable; +- drive-push-pull; +- }; +- gpio5pp_pins: gpio5pp-pins { +- pins = "GPIO5/IOX2LD/SMB1DSCL"; +- bias-disable; +- drive-push-pull; +- }; +- gpio6pp_pins: gpio6pp-pins { +- pins = "GPIO6/IOX2CK/SMB2DSDA"; +- bias-disable; +- drive-push-pull; +- }; +- gpio7pp_pins: gpio7pp-pins { +- pins = "GPIO7/IOX2D0/SMB2DSCL"; +- bias-disable; +- drive-push-pull; +- }; +- gpio8_pins: gpio8-pins { +- pins = "GPIO8/LKGPO1"; +- bias-disable; +- input-enable; +- }; +- gpio9_pins: gpio9-pins { +- pins = "GPIO9/LKGPO2"; +- bias-disable; +- input-enable; +- }; +- gpio10pp_pins: gpio10pp-pins { +- pins = "GPIO10/IOXHLD"; +- bias-disable; +- drive-push-pull; +- }; +- gpio11pp_pins: gpio11pp-pins { +- pins = "GPIO11/IOXHCK"; +- bias-disable; +- drive-push-pull; +- }; +- gpio12_pins: gpio12-pins { +- pins = "GPIO12/GSPICK/SMB5BSCL"; +- bias-disable; +- input-enable; +- }; +- gpio13_pins: gpio13-pins { +- pins = "GPIO13/GSPIDO/SMB5BSDA"; +- bias-disable; +- input-enable; +- }; +- gpio14_pins: gpio14-pins { +- pins = "GPIO14/GSPIDI/SMB5CSCL"; +- bias-disable; +- input-enable; +- }; +- gpio15od_pins: gpio15od-pins { +- pins = "GPIO15/GSPICS/SMB5CSDA"; +- bias-disable; +- drive-open-drain; +- }; +- gpio17pp_pins: gpio17pp-pins { +- pins = "GPIO17/PSPI2DI/SMB4DEN"; +- bias-disable; +- drive-push-pull; +- }; +- gpio18pp_pins: gpio18pp-pins { +- pins = "GPIO18/PSPI2D0/SMB4BSDA"; +- bias-disable; +- drive-push-pull; +- }; +- gpio19pp_pins: gpio19pp-pins { +- pins = "GPIO19/PSPI2CK/SMB4BSCL"; +- bias-disable; +- drive-push-pull; +- }; +- gpio24pp_pins: gpio24pp-pins { +- pins = "GPIO24/IOXHDO"; +- bias-disable; +- drive-push-pull; +- }; +- gpio25pp_pins: gpio25pp-pins { +- pins = "GPIO25/IOXHDI"; +- bias-disable; +- drive-push-pull; +- }; +- gpio37od_pins: gpio37od-pins { +- pins = "GPIO37/SMB3CSDA"; +- bias-disable; +- drive-open-drain; +- }; +- gpio59pp_pins: gpio59pp-pins { +- pins = "GPIO59/SMB3DSDA"; +- bias-disable; +- drive-push-pull; +- }; +- gpio60_pins: gpio60-pins { +- pins = "GPIO60/SMB3DSCL"; +- bias-disable; +- input-enable; +- }; +- gpio72od_pins: gpio72od-pins { +- pins = "GPIO72/FANIN8"; +- bias-disable; +- drive-open-drain; +- }; +- gpio73od_pins: gpio73od-pins { +- pins = "GPIO73/FANIN9"; +- bias-disable; +- drive-open-drain; +- }; +- gpio74od_pins: gpio74od-pins { +- pins = "GPIO74/FANIN10"; +- bias-disable; +- drive-open-drain; +- }; +- gpio75od_pins: gpio75od-pins { +- pins = "GPIO75/FANIN11"; +- bias-disable; +- drive-open-drain; +- }; +- gpio76od_pins: gpio76od-pins { +- pins = "GPIO76/FANIN12"; +- bias-disable; +- drive-open-drain; +- }; +- gpio77od_pins: gpio77od-pins { +- pins = "GPIO77/FANIN13"; +- bias-disable; +- drive-open-drain; +- }; +- gpio78od_pins: gpio78od-pins { +- pins = "GPIO78/FANIN14"; +- bias-disable; +- drive-open-drain; +- }; +- gpio79od_pins: gpio79od-pins { +- pins = "GPIO79/FANIN15"; +- bias-disable; +- drive-open-drain; +- }; +- gpio83_pins: gpio83-pins { +- pins = "GPIO83/PWM3"; +- bias-disable; +- input-enable; +- }; +- gpio84pp_pins: gpio84pp-pins { +- pins = "GPIO84/R2TXD0"; +- bias-disable; +- drive-push-pull; +- }; +- gpio85pp_pins: gpio85pp-pins { +- pins = "GPIO85/R2TXD1"; +- bias-disable; +- drive-push-pull; +- }; +- gpio86pp_pins: gpio86pp-pins { +- pins = "GPIO86/R2TXEN"; +- bias-disable; +- drive-push-pull; +- }; +- gpio87pp_pins: gpio87pp-pins { +- pins = "GPIO87/R2RXD0"; +- bias-disable; +- drive-push-pull; +- }; +- gpio88pp_pins: gpio88pp-pins { +- pins = "GPIO88/R2RXD1"; +- bias-disable; +- drive-push-pull; +- }; +- gpio89pp_pins: gpio89pp-pins { +- pins = "GPIO89/R2CRSDV"; +- bias-disable; +- drive-push-pull; +- }; +- gpio90pp_pins: gpio90pp-pins { +- pins = "GPIO90/R2RXERR"; +- bias-disable; +- drive-push-pull; +- }; +- gpio91_pins: gpio91-pins { +- pins = "GPIO91/R2MDC"; +- bias-disable; +- input-enable; +- }; +- gpio92_pins: gpio92-pins { +- pins = "GPIO92/R2MDIO"; +- bias-disable; +- input-enable; +- }; +- gpio93pp_pins: gpio93pp-pins { +- pins = "GPIO93/GA20/SMB5DSCL"; +- bias-disable; +- drive-push-pull; +- }; +- gpio94pp_pins: gpio94pp-pins { +- pins = "GPIO94/nKBRST/SMB5DSDA"; +- bias-disable; +- drive-push-pull; +- }; +- gpio95_pins: gpio95-pins { +- pins = "GPIO95/nLRESET/nESPIRST"; +- bias-disable; +- input-enable; +- }; +- gpio125pp_pins: gpio125pp-pins { +- pins = "GPIO125/SMB1CSCL"; +- bias-disable; +- drive-push-pull; +- }; +- gpio126od_pins: gpio126od-pins { +- pins = "GPIO126/SMB1BSDA"; +- bias-disable; +- drive-open-drain; +- }; +- gpio127od_pins: gpio127od-pins { +- pins = "GPIO127/SMB1BSCL"; +- bias-disable; +- drive-open-drain; +- }; +- gpio136_pins: gpio136-pins { +- pins = "GPIO136/SD1DT0"; +- bias-disable; +- input-enable; +- }; +- gpio137_pins: gpio137-pins { +- pins = "GPIO137/SD1DT1"; +- bias-disable; +- input-enable; +- }; +- gpio141_pins: gpio141-pins { +- pins = "GPIO141/SD1WP"; +- bias-disable; +- input-enable; +- }; +- gpio142od_pins: gpio142od-pins { +- pins = "GPIO142/SD1CMD"; +- bias-disable; +- drive-open-drain; +- }; +- gpio143ol_pins: gpio143ol-pins { +- pins = "GPIO143/SD1CD/SD1PWR"; +- bias-disable; +- output-low; +- }; +- gpio144_pins: gpio144-pins { +- pins = "GPIO144/PWM4"; +- bias-disable; +- input-enable; +- }; +- gpio145_pins: gpio145-pins { +- pins = "GPIO145/PWM5"; +- bias-disable; +- input-enable; +- }; +- gpio146_pins: gpio146-pins { +- pins = "GPIO146/PWM6"; +- bias-disable; +- input-enable; +- }; +- gpio147_pins: gpio147-pins { +- pins = "GPIO147/PWM7"; +- bias-disable; +- input-enable; +- }; +- gpio148_pins: gpio148-pins { +- pins = "GPIO148/MMCDT4"; +- bias-disable; +- input-enable; +- }; +- gpio149_pins: gpio149-pins { +- pins = "GPIO149/MMCDT5"; +- bias-disable; +- input-enable; +- }; +- gpio150_pins: gpio150-pins { +- pins = "GPIO150/MMCDT6"; +- bias-disable; +- input-enable; +- }; +- gpio151_pins: gpio151-pins { +- pins = "GPIO151/MMCDT7"; +- bias-disable; +- input-enable; +- }; +- gpio152_pins: gpio152-pins { +- pins = "GPIO152/MMCCLK"; +- bias-disable; +- input-enable; +- }; +- gpio153_pins: gpio153-pins { +- pins = "GPIO153/MMCWP"; +- bias-disable; +- input-enable; +- }; +- gpio154_pins: gpio154-pins { +- pins = "GPIO154/MMCCMD"; +- bias-disable; +- input-enable; +- }; +- gpio155_pins: gpio155-pins { +- pins = "GPIO155/nMMCCD/nMMCRST"; +- bias-disable; +- input-enable; +- }; +- gpio156_pins: gpio156-pins { +- pins = "GPIO156/MMCDT0"; +- bias-disable; +- input-enable; +- }; +- gpio157_pins: gpio157-pins { +- pins = "GPIO157/MMCDT1"; +- bias-disable; +- input-enable; +- }; +- gpio158_pins: gpio158-pins { +- pins = "GPIO158/MMCDT2"; +- bias-disable; +- input-enable; +- }; +- gpio159_pins: gpio159-pins { +- pins = "GPIO159/MMCDT3"; +- bias-disable; +- input-enable; +- }; +- gpio161_pins: gpio161-pins { +- pins = "GPIO161/nLFRAME/nESPICS"; +- bias-disable; +- input-enable; +- }; +- gpio162_pins: gpio162-pins { +- pins = "GPIO162/SERIRQ"; +- bias-disable; +- input-enable; +- }; +- gpio163_pins: gpio163-pins { +- pins = "GPIO163/LCLK/ESPICLK"; +- bias-disable; +- input-enable; +- }; +- gpio164_pins: gpio164-pins { +- pins = "GPIO164/LAD0/ESPI_IO0"; +- bias-disable; +- input-enable; +- }; +- gpio165_pins: gpio165-pins { +- pins = "GPIO165/LAD1/ESPI_IO1"; +- bias-disable; +- input-enable; +- }; +- gpio166_pins: gpio166-pins { +- pins = "GPIO166/LAD2/ESPI_IO2"; +- bias-disable; +- input-enable; +- }; +- gpio167_pins: gpio167-pins { +- pins = "GPIO167/LAD3/ESPI_IO3"; +- bias-disable; +- input-enable; +- }; +- gpio168_pins: gpio168-pins { +- pins = "GPIO168/nCLKRUN/nESPIALERT"; +- bias-disable; +- input-enable; +- }; +- gpio169_pins: gpio169-pins { +- pins = "GPIO169/nSCIPME"; +- bias-disable; +- input-enable; +- }; +- gpio170_pins: gpio170-pins { +- pins = "GPIO170/nSMI"; +- bias-disable; +- input-enable; +- }; +- gpio175od_pins: gpio175od-pins { +- pins = "GPIO175/PSPI1CK/FANIN19"; +- bias-disable; +- drive-open-drain; +- }; +- gpio176od_pins: gpio176od-pins { +- pins = "GPIO176/PSPI1DO/FANIN18"; +- bias-disable; +- drive-open-drain; +- }; +- gpio177_pins: gpio177-pins { +- pins = "GPIO177/PSPI1DI/FANIN17"; +- bias-disable; +- input-enable; +- }; +- gpio190od_pins: gpio190od-pins { +- pins = "GPIO190/nPRD_SMI"; +- bias-disable; +- drive-open-drain; +- }; +- gpio191_pins: gpio191-pins { +- pins = "GPIO191"; +- bias-disable; +- input-enable; +- }; +- gpio192_pins: gpio192-pins { +- pins = "GPIO192"; +- bias-disable; +- input-enable; +- }; +- gpio194pp_pins: gpio194pp-pins { +- pins = "GPIO194/SMB0BSCL"; +- bias-disable; +- drive-push-pull; +- }; +- gpio195od_pins: gpio195od-pins { +- pins = "GPIO195/SMB0BSDA"; +- bias-disable; +- drive-open-drain; +- }; +- gpio196od_pins: gpio196od-pins { +- pins = "GPIO196/SMB0CSCL"; +- bias-disable; +- drive-open-drain; +- }; +- gpio197od_pins: gpio197od-pins { +- pins = "GPIO197/SMB0DEN"; +- bias-disable; +- drive-open-drain; +- }; +- gpio198od_pins: gpio198od-pins { +- pins = "GPIO198/SMB0DSDA"; +- bias-disable; +- drive-open-drain; +- }; +- gpio199od_pins: gpio199od-pins { +- pins = "GPIO199/SMB0DSCL"; +- bias-disable; +- drive-open-drain; +- }; +- gpio200pp_pins: gpio200pp-pins { +- pins = "GPIO200/R2CK"; +- bias-disable; +- drive-push-pull; +- }; +- gpio202od_pins: gpio202od-pins { +- pins = "GPIO202/SMB0CSDA"; +- bias-disable; +- drive-open-drain; +- }; +- gpio203_pins: gpio203-pins { +- pins = "GPIO203/FANIN16"; +- bias-disable; +- input-enable; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/nuvoton-npcm730-gsj.dts b/scripts/dtc/include-prefixes/arm/nuvoton-npcm730-gsj.dts +deleted file mode 100644 +index d4ff49939a3d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/nuvoton-npcm730-gsj.dts ++++ /dev/null +@@ -1,490 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2019 Quanta Computer lnc. Fran.Hsu@quantatw.com +- +-/dts-v1/; +-#include "nuvoton-npcm730.dtsi" +-#include "nuvoton-npcm730-gsj-gpio.dtsi" +- +-#include +- +-/ { +- model = "Quanta GSJ Board (Device Tree v12)"; +- compatible = "nuvoton,npcm750"; +- +- aliases { +- ethernet1 = &gmac0; +- serial3 = &serial3; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c8 = &i2c8; +- i2c9 = &i2c9; +- i2c10 = &i2c10; +- i2c11 = &i2c11; +- i2c12 = &i2c12; +- i2c15 = &i2c15; +- fiu0 = &fiu0; +- }; +- +- chosen { +- stdout-path = &serial3; +- }; +- +- memory { +- reg = <0 0x40000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-bmc-live { +- gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- LED_U2_0_LOCATE { +- gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- LED_U2_1_LOCATE { +- gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- LED_U2_2_LOCATE { +- gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- LED_U2_3_LOCATE { +- gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- LED_U2_4_LOCATE { +- gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- LED_U2_5_LOCATE { +- gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- LED_BMC_TRAY_PWRGD { +- gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- LED_U2_7_FAULT { +- gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- LED_U2_6_LOCATE { +- gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- LED_U2_7_LOCATE { +- gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- LED_U2_0_FAULT { +- gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- LED_U2_1_FAULT { +- gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- LED_U2_2_FAULT { +- gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- LED_U2_3_FAULT { +- gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- LED_U2_4_FAULT { +- gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- LED_U2_5_FAULT { +- gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- LED_U2_6_FAULT { +- gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +-}; +- +-&fiu0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0cs1_pins>; +- status = "okay"; +- +- spi-nor@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- spi-rx-bus-width = <2>; +- +- partitions@80000000 { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- bmc@0{ +- label = "bmc"; +- reg = <0x000000 0x2000000>; +- }; +- u-boot@0 { +- label = "u-boot"; +- reg = <0x0000000 0x80000>; +- read-only; +- }; +- u-boot-env@100000{ +- label = "u-boot-env"; +- reg = <0x00100000 0x40000>; +- }; +- kernel@200000 { +- label = "kernel"; +- reg = <0x0200000 0x600000>; +- }; +- rofs@800000 { +- label = "rofs"; +- reg = <0x800000 0x1400000>; +- }; +- rwfs@1c00000 { +- label = "rwfs"; +- reg = <0x1c00000 0x300000>; +- }; +- reserved@1f00000 { +- label = "reserved"; +- reg = <0x1f00000 0x100000>; +- }; +- }; +- }; +-}; +- +-&gmac0 { +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&watchdog1 { +- status = "okay"; +-}; +- +-&rng { +- status = "okay"; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&serial1 { +- status = "okay"; +-}; +- +-&serial2 { +- status = "okay"; +-}; +- +-&serial3 { +- status = "okay"; +-}; +- +-&adc { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- +- lm75@5c { +- compatible = "maxim,max31725"; +- reg = <0x5c>; +- status = "okay"; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- +- lm75@5c { +- compatible = "maxim,max31725"; +- reg = <0x5c>; +- status = "okay"; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +- +- lm75@5c { +- compatible = "maxim,max31725"; +- reg = <0x5c>; +- }; +-}; +- +-&i2c4 { +- status = "okay"; +- +- lm75@5c { +- compatible = "maxim,max31725"; +- reg = <0x5c>; +- }; +-}; +- +-&i2c8 { +- status = "okay"; +-}; +- +-&i2c9 { +- status = "okay"; +- +- eeprom@55 { +- compatible = "atmel,24c64"; +- reg = <0x55>; +- }; +-}; +- +-&i2c10 { +- status = "okay"; +- +- eeprom@55 { +- compatible = "atmel,24c64"; +- reg = <0x55>; +- }; +-}; +- +-&i2c11 { +- status = "okay"; +- +- /* P12V Quarter Brick DC/DC Power Module Q54SH12050 @60 */ +- power-brick@36 { +- compatible = "delta,dps800"; +- reg = <0x36>; +- }; +- +- hotswap@15 { +- compatible = "ti,lm5066i"; +- reg = <0x15>; +- }; +-}; +- +-&i2c12 { +- status = "okay"; +- +- ucd90160@6b { +- compatible = "ti,ucd90160"; +- reg = <0x6b>; +- }; +-}; +- +-&i2c15 { +- status = "okay"; +- +- i2c-switch@75 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x75>; +- i2c-mux-idle-disconnect; +- +- i2c_u20: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c_u21: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- i2c_u22: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c_u23: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- i2c_u24: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- i2c_u25: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- i2c_u26: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- i2c_u27: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +-}; +- +-&pwm_fan { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pins &pwm1_pins &pwm2_pins +- &fanin0_pins &fanin1_pins +- &fanin2_pins &fanin3_pins +- &fanin4_pins &fanin5_pins>; +- status = "okay"; +- +- fan@0 { +- reg = <0x00>; +- fan-tach-ch = /bits/ 8 <0x00 0x01>; +- cooling-levels = <127 255>; +- }; +- +- fan@1 { +- reg = <0x01>; +- fan-tach-ch = /bits/ 8 <0x02 0x03>; +- cooling-levels = /bits/ 8 <127 255>; +- }; +- +- fan@2 { +- reg = <0x02>; +- fan-tach-ch = /bits/ 8 <0x04 0x05>; +- cooling-levels = /bits/ 8 <127 255>; +- }; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = < +- /* GPI pins*/ +- &gpio8_pins +- &gpio9_pins +- &gpio12_pins +- &gpio13_pins +- &gpio14_pins +- &gpio60_pins +- &gpio83_pins +- &gpio91_pins +- &gpio92_pins +- &gpio95_pins +- &gpio136_pins +- &gpio137_pins +- &gpio141_pins +- &gpio144_pins +- &gpio145_pins +- &gpio146_pins +- &gpio147_pins +- &gpio148_pins +- &gpio149_pins +- &gpio150_pins +- &gpio151_pins +- &gpio152_pins +- &gpio153_pins +- &gpio154_pins +- &gpio155_pins +- &gpio156_pins +- &gpio157_pins +- &gpio158_pins +- &gpio159_pins +- &gpio161_pins +- &gpio162_pins +- &gpio163_pins +- &gpio164_pins +- &gpio165_pins +- &gpio166_pins +- &gpio167_pins +- &gpio168_pins +- &gpio169_pins +- &gpio170_pins +- &gpio177_pins +- &gpio191_pins +- &gpio192_pins +- &gpio203_pins +- /* GPO pins*/ +- &gpio0pp_pins +- &gpio1pp_pins +- &gpio2pp_pins +- &gpio3pp_pins +- &gpio4pp_pins +- &gpio5pp_pins +- &gpio6pp_pins +- &gpio7pp_pins +- &gpio10pp_pins +- &gpio11pp_pins +- &gpio15od_pins +- &gpio17pp_pins +- &gpio18pp_pins +- &gpio19pp_pins +- &gpio24pp_pins +- &gpio25pp_pins +- &gpio37od_pins +- &gpio59pp_pins +- &gpio72od_pins +- &gpio73od_pins +- &gpio74od_pins +- &gpio75od_pins +- &gpio76od_pins +- &gpio77od_pins +- &gpio78od_pins +- &gpio79od_pins +- &gpio84pp_pins +- &gpio85pp_pins +- &gpio86pp_pins +- &gpio87pp_pins +- &gpio88pp_pins +- &gpio89pp_pins +- &gpio90pp_pins +- &gpio93pp_pins +- &gpio94pp_pins +- &gpio125pp_pins +- &gpio126od_pins +- &gpio127od_pins +- &gpio142od_pins +- &gpio143ol_pins +- &gpio175od_pins +- &gpio176od_pins +- &gpio190od_pins +- &gpio194pp_pins +- &gpio195od_pins +- &gpio196od_pins +- &gpio197od_pins +- &gpio198od_pins +- &gpio199od_pins +- &gpio200pp_pins +- &gpio202od_pins +- >; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/nuvoton-npcm730-kudo.dts b/scripts/dtc/include-prefixes/arm/nuvoton-npcm730-kudo.dts +deleted file mode 100644 +index 82a104b2a65f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/nuvoton-npcm730-kudo.dts ++++ /dev/null +@@ -1,826 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2020 Fii USA Inc. +- +-/dts-v1/; +-#include "nuvoton-npcm730.dtsi" +- +-#include +- +-/ { +- model = "Fii Kudo Board"; +- compatible = "fii,kudo", "nuvoton,npcm730"; +- +- aliases { +- ethernet1 = &gmac0; +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c7; +- i2c8 = &i2c8; +- i2c9 = &i2c9; +- i2c10 = &i2c10; +- i2c11 = &i2c11; +- i2c12 = &i2c12; +- i2c13 = &i2c13; +- i2c14 = &i2c14; +- i2c15 = &i2c15; +- spi0 = &spi0; +- spi1 = &spi1; +- fiu0 = &fiu0; +- fiu1 = &fiu3; +- }; +- +- chosen { +- stdout-path = &serial3; +- }; +- +- memory { +- reg = <0 0x40000000>; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, +- <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; +- }; +- +- jtag_master { +- compatible = "nuvoton,npcm750-jtag-master"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- // dev/jtag0 +- dev-num = <0>; +- // pspi or gpio +- mode = "pspi"; +- +- // pspi2 +- pspi-controller = <2>; +- reg = <0xf0201000 0x1000>; +- interrupts = ; +- clocks = <&clk NPCM7XX_CLK_APB5>; +- +- // TCK, TDI, TDO, TMS +- jtag-gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>, +- <&gpio0 18 GPIO_ACTIVE_HIGH>, +- <&gpio0 17 GPIO_ACTIVE_HIGH>, +- <&gpio0 16 GPIO_ACTIVE_HIGH>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- heartbeat { +- label = "heartbeat"; +- gpios = <&gpio0 14 1>; +- }; +- }; +- +- pinctrl: pinctrl@f0800000 { +- gpio61oh_pins: gpio61oh-pins { +- pins = "GPO61/nDTR1_BOUT1/STRAP6"; +- bias-disable; +- output-high; +- }; +- gpio62oh_pins: gpio62oh-pins { +- pins = "GPO62/nRTST1/STRAP5"; +- bias-disable; +- output-high; +- }; +- gpio161ol_pins: gpio161ol-pins { +- pins = "GPIO161/nLFRAME/nESPICS"; +- bias-disable; +- output-low; +- }; +- gpio163i_pins: gpio163i-pins { +- pins = "GPIO163/LCLK/ESPICLK"; +- bias-disable; +- input-enable; +- }; +- gpio167ol_pins: gpio167ol-pins { +- pins = "GPIO167/LAD3/ESPI_IO3"; +- bias-disable; +- output-low; +- }; +- gpio95i_pins: gpio95i-pins { +- pins = "GPIO95/nLRESET/nESPIRST"; +- bias-disable; +- input-enable; +- }; +- gpio65ol_pins: gpio65ol-pins { +- pins = "GPIO65/FANIN1"; +- bias-disable; +- output-low; +- }; +- gpio66oh_pins: gpio66oh-pins { +- pins = "GPIO66/FANIN2"; +- bias-disable; +- output-high; +- }; +- gpio67oh_pins: gpio67oh-pins { +- pins = "GPIO67/FANIN3"; +- bias-disable; +- output-high; +- }; +- gpio68ol_pins: gpio68ol-pins { +- pins = "GPIO68/FANIN4"; +- bias-disable; +- output-low; +- }; +- gpio69i_pins: gpio69i-pins { +- pins = "GPIO69/FANIN5"; +- bias-disable; +- input-enable; +- }; +- gpio70ol_pins: gpio70ol-pins { +- pins = "GPIO70/FANIN6"; +- bias-disable; +- output-low; +- }; +- gpio71i_pins: gpio71i-pins { +- pins = "GPIO71/FANIN7"; +- bias-disable; +- input-enable; +- }; +- gpio72i_pins: gpio72i-pins { +- pins = "GPIO72/FANIN8"; +- bias-disable; +- input-enable; +- }; +- gpio73i_pins: gpio73i-pins { +- pins = "GPIO73/FANIN9"; +- bias-disable; +- input-enable; +- }; +- gpio74i_pins: gpio74i-pins { +- pins = "GPIO74/FANIN10"; +- bias-disable; +- input-enable; +- }; +- gpio75i_pins: gpio75i-pins { +- pins = "GPIO75/FANIN11"; +- bias-disable; +- input-enable; +- }; +- gpio76i_pins: gpio76i-pins { +- pins = "GPIO76/FANIN12"; +- bias-disable; +- input-enable; +- }; +- gpio77i_pins: gpio77i-pins { +- pins = "GPIO77/FANIN13"; +- bias-disable; +- input-enable; +- }; +- gpio78i_pins: gpio78i-pins { +- pins = "GPIO78/FANIN14"; +- bias-disable; +- input-enable; +- }; +- gpio79ol_pins: gpio79ol-pins { +- pins = "GPIO79/FANIN15"; +- bias-disable; +- output-low; +- }; +- gpio80oh_pins: gpio80oh-pins { +- pins = "GPIO80/PWM0"; +- bias-disable; +- output-high; +- }; +- gpio81i_pins: gpio81i-pins { +- pins = "GPIO81/PWM1"; +- bias-disable; +- input-enable; +- }; +- gpio82i_pins: gpio82i-pins { +- pins = "GPIO82/PWM2"; +- bias-disable; +- input-enable; +- }; +- gpio83i_pins: gpio83i-pins { +- pins = "GPIO83/PWM3"; +- bias-disable; +- input-enable; +- }; +- gpio144i_pins: gpio144i-pins { +- pins = "GPIO144/PWM4"; +- bias-disable; +- input-enable; +- }; +- gpio145i_pins: gpio145i-pins { +- pins = "GPIO145/PWM5"; +- bias-disable; +- input-enable; +- }; +- gpio146i_pins: gpio146i-pins { +- pins = "GPIO146/PWM6"; +- bias-disable; +- input-enable; +- }; +- gpio147oh_pins: gpio147oh-pins { +- pins = "GPIO147/PWM7"; +- bias-disable; +- output-high; +- }; +- gpio168ol_pins: gpio168ol-pins { +- pins = "GPIO168/nCLKRUN/nESPIALERT"; +- bias-disable; +- output-low; +- }; +- gpio169oh_pins: gpio169oh-pins { +- pins = "GPIO169/nSCIPME"; +- bias-disable; +- output-high; +- }; +- gpio170ol_pins: gpio170ol-pins { +- pins = "GPIO170/nSMI"; +- bias-disable; +- output-low; +- }; +- gpio218oh_pins: gpio218oh-pins { +- pins = "GPIO218/nWDO1"; +- bias-disable; +- output-high; +- }; +- gpio37i_pins: gpio37i-pins { +- pins = "GPIO37/SMB3CSDA"; +- bias-disable; +- input-enable; +- }; +- gpio38i_pins: gpio38i-pins { +- pins = "GPIO38/SMB3CSCL"; +- bias-disable; +- input-enable; +- }; +- gpio39i_pins: gpio39i-pins { +- pins = "GPIO39/SMB3BSDA"; +- bias-disable; +- input-enable; +- }; +- gpio40i_pins: gpio40i-pins { +- pins = "GPIO40/SMB3BSCL"; +- bias-disable; +- input-enable; +- }; +- gpio121i_pins: gpio121i-pins { +- pins = "GPIO121/SMB2CSCL"; +- bias-disable; +- input-enable; +- }; +- gpio122i_pins: gpio122i-pins { +- pins = "GPIO122/SMB2BSDA"; +- bias-disable; +- input-enable; +- }; +- gpio123i_pins: gpio123i-pins { +- pins = "GPIO123/SMB2BSCL"; +- bias-disable; +- input-enable; +- }; +- gpio124i_pins: gpio124i-pins { +- pins = "GPIO124/SMB1CSDA"; +- bias-disable; +- input-enable; +- }; +- gpio125i_pins: gpio125i-pins { +- pins = "GPIO125/SMB1CSCL"; +- bias-disable; +- input-enable; +- }; +- gpio126i_pins: gpio126i-pins { +- pins = "GPIO126/SMB1BSDA"; +- bias-disable; +- input-enable; +- }; +- gpio127i_pins: gpio127i-pins { +- pins = "GPIO127/SMB1BSCL"; +- bias-disable; +- input-enable; +- }; +- gpio136i_pins: gpio136i-pins { +- pins = "GPIO136/SD1DT0"; +- bias-disable; +- input-enable; +- }; +- gpio137oh_pins: gpio137oh-pins { +- pins = "GPIO137/SD1DT1"; +- bias-disable; +- output-high; +- }; +- gpio138i_pins: gpio138i-pins { +- pins = "GPIO138/SD1DT2"; +- bias-disable; +- input-enable; +- }; +- gpio139i_pins: gpio139i-pins { +- pins = "GPIO139/SD1DT3"; +- bias-disable; +- input-enable; +- }; +- gpio140i_pins: gpio140i-pins { +- pins = "GPIO140/SD1CLK"; +- bias-disable; +- input-enable; +- }; +- gpio141i_pins: gpio141i-pins { +- pins = "GPIO141/SD1WP"; +- bias-disable; +- input-enable; +- }; +- gpio190oh_pins: gpio190oh-pins { +- pins = "GPIO190/nPRD_SMI"; +- bias-disable; +- output-high; +- }; +- gpio191oh_pins: gpio191oh-pins { +- pins = "GPIO191"; +- bias-disable; +- output-high; +- }; +- gpio195ol_pins: gpio195ol-pins { +- pins = "GPIO195/SMB0BSDA"; +- bias-disable; +- output-low; +- }; +- gpio196ol_pins: gpio196ol-pins { +- pins = "GPIO196/SMB0CSCL"; +- bias-disable; +- output-low; +- }; +- gpio199i_pins: gpio199i-pins { +- pins = "GPIO199/SMB0DSCL"; +- bias-disable; +- input-enable; +- }; +- gpio202ol_pins: gpio202ol-pins { +- pins = "GPIO202/SMB0CSDA"; +- bias-disable; +- output-low; +- }; +- }; +-}; +- +-&gmac0 { +- phy-mode = "rgmii-id"; +- snps,eee-force-disable; +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&fiu0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0cs1_pins>; +- status = "okay"; +- spi-nor@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- spi-max-frequency = <5000000>; +- spi-rx-bus-width = <2>; +- label = "bmc"; +- partitions@80000000 { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- u-boot@0 { +- label = "u-boot"; +- reg = <0x0000000 0xC0000>; +- read-only; +- }; +- u-boot-env@100000{ +- label = "u-boot-env"; +- reg = <0x00100000 0x40000>; +- }; +- kernel@200000 { +- label = "kernel"; +- reg = <0x0200000 0x600000>; +- }; +- rofs@800000 { +- label = "rofs"; +- reg = <0x800000 0x3500000>; +- }; +- rwfs@3d00000 { +- label = "rwfs"; +- reg = <0x3d00000 0x300000>; +- }; +- }; +- }; +- spi-nor@1 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <1>; +- spi-max-frequency = <5000000>; +- spi-rx-bus-width = <2>; +- partitions@88000000 { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- spare1@0 { +- label = "spi0-cs1-spare1"; +- reg = <0x0 0x800000>; +- }; +- spare2@800000 { +- label = "spi0-cs1-spare2"; +- reg = <0x800000 0x0>; +- }; +- }; +- }; +-}; +- +-&fiu3 { +- pinctrl-0 = <&spi3_pins>; +- spi-nor@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- spi-max-frequency = <5000000>; +- spi-rx-bus-width = <2>; +- partitions@A0000000 { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- system1@0 { +- label = "bios"; +- reg = <0x0 0x0>; +- }; +- system2@800000 { +- label = "spi3-system2"; +- reg = <0x800000 0x0>; +- }; +- }; +- }; +-}; +- +-&watchdog1 { +- status = "okay"; +-}; +- +-&rng { +- status = "okay"; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&serial1 { +- status = "okay"; +-}; +- +-&serial2 { +- status = "okay"; +-}; +- +-&serial3 { +- status = "okay"; +-}; +- +-&adc { +- #io-channel-cells = <1>; +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- i2c-switch@75 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x75>; +- i2c-mux-idle-disconnect; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- // Rear-Fan +- max31790@58 { +- compatible = "maxim,max31790"; +- reg = <0x58>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- // Mid-Fan +- max31790@58 { +- compatible = "maxim,max31790"; +- reg = <0x58>; +- }; +- }; +- +- i2c-bus@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- +- // INLET1_T +- lm75@5c { +- compatible = "ti,lm75"; +- reg = <0x5c>; +- }; +- }; +- +- i2c-bus@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- +- // OUTLET1_T +- lm75@5c { +- compatible = "ti,lm75"; +- reg = <0x5c>; +- }; +- }; +- +- i2c-bus@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- +- // OUTLET2_T +- lm75@5c { +- compatible = "ti,lm75"; +- reg = <0x5c>; +- }; +- }; +- +- i2c-bus@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- +- // OUTLET3_T +- lm75@5c { +- compatible = "ti,lm75"; +- reg = <0x5c>; +- }; +- }; +- }; +- i2c-switch@77 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x77>; +- i2c-mux-idle-disconnect; +- +- i2c-bus@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- // STB-T +- pmbus@74 { +- compatible = "pmbus"; +- reg = <0x74>; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- smpro@4f { +- compatible = "ampere,smpro"; +- reg = <0x4f>; +- }; +- +- smpro@4e { +- compatible = "ampere,smpro"; +- reg = <0x4e>; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +- i2c-switch@77 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x77>; +- i2c-mux-idle-disconnect; +- +- i2c-bus@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- // ADC sensors +- adm1266@40 { +- compatible = "adi,adm1266"; +- reg = <0x40>; +- }; +- }; +- +- i2c-bus@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- // ADC sensors +- adm1266@41 { +- compatible = "adi,adm1266"; +- reg = <0x41>; +- }; +- }; +- }; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2c6 { +- status = "okay"; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&i2c8 { +- status = "okay"; +-}; +- +-&i2c9 { +- status = "okay"; +-}; +- +-&i2c10 { +- status = "okay"; +-}; +- +-&i2c11 { +- status = "okay"; +-}; +- +-&i2c12 { +- status = "okay"; +- ssif-bmc@10 { +- compatible = "ssif-bmc"; +- reg = <0x10>; +- }; +-}; +- +-&i2c13 { +- status = "okay"; +- i2c-switch@77 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x77>; +- i2c-mux-idle-disconnect; +- +- i2c-bus@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- // M2_ZONE_T +- lm75@28 { +- compatible = "ti,lm75"; +- reg = <0x28>; +- }; +- }; +- +- i2c-bus@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- +- // BATT_ZONE_T +- lm75@29 { +- compatible = "ti,lm75"; +- reg = <0x29>; +- }; +- }; +- +- i2c-bus@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- +- // NBM1_ZONE_T +- lm75@28 { +- compatible = "ti,lm75"; +- reg = <0x28>; +- }; +- }; +- i2c-bus@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- +- // NBM2_ZONE_T +- lm75@29 { +- compatible = "ti,lm75"; +- reg = <0x29>; +- }; +- }; +- }; +-}; +- +-&i2c14 { +- status = "okay"; +-}; +- +-&i2c15 { +- status = "okay"; +-}; +- +-&spi0 { +- cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &gpio61oh_pins +- &gpio62oh_pins +- &gpio161ol_pins +- &gpio163i_pins +- &gpio167ol_pins +- &gpio95i_pins +- &gpio65ol_pins +- &gpio66oh_pins +- &gpio67oh_pins +- &gpio68ol_pins +- &gpio69i_pins +- &gpio70ol_pins +- &gpio71i_pins +- &gpio72i_pins +- &gpio73i_pins +- &gpio74i_pins +- &gpio75i_pins +- &gpio76i_pins +- &gpio77i_pins +- &gpio78i_pins +- &gpio79ol_pins +- &gpio80oh_pins +- &gpio81i_pins +- &gpio82i_pins +- &gpio83i_pins +- &gpio144i_pins +- &gpio145i_pins +- &gpio146i_pins +- &gpio147oh_pins +- &gpio168ol_pins +- &gpio169oh_pins +- &gpio170ol_pins +- &gpio218oh_pins +- &gpio37i_pins +- &gpio38i_pins +- &gpio39i_pins +- &gpio40i_pins +- &gpio121i_pins +- &gpio122i_pins +- &gpio123i_pins +- &gpio124i_pins +- &gpio125i_pins +- &gpio126i_pins +- &gpio127i_pins +- &gpio136i_pins +- &gpio137oh_pins +- &gpio138i_pins +- &gpio139i_pins +- &gpio140i_pins +- &gpio141i_pins +- &gpio190oh_pins +- &gpio191oh_pins +- &gpio195ol_pins +- &gpio196ol_pins +- &gpio199i_pins +- &gpio202ol_pins +- >; +-}; +- +-&gcr { +- serial_port_mux: mux-controller { +- compatible = "mmio-mux"; +- #mux-control-cells = <1>; +- +- mux-reg-masks = <0x38 0x07>; +- idle-states = <2>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/nuvoton-npcm730.dtsi b/scripts/dtc/include-prefixes/arm/nuvoton-npcm730.dtsi +deleted file mode 100644 +index 86ec12ec2b50..000000000000 +--- a/scripts/dtc/include-prefixes/arm/nuvoton-npcm730.dtsi ++++ /dev/null +@@ -1,44 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2020 Nuvoton Technology +- +-#include "nuvoton-common-npcm7xx.dtsi" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&gic>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "nuvoton,npcm750-smp"; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- clocks = <&clk NPCM7XX_CLK_CPU>; +- clock-names = "clk_cpu"; +- reg = <0>; +- next-level-cache = <&l2>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- clocks = <&clk NPCM7XX_CLK_CPU>; +- clock-names = "clk_cpu"; +- reg = <1>; +- next-level-cache = <&l2>; +- }; +- }; +- +- soc { +- timer@3fe600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x3fe600 0x20>; +- interrupts = ; +- clocks = <&clk NPCM7XX_CLK_AHB>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/nuvoton-npcm750-evb.dts b/scripts/dtc/include-prefixes/arm/nuvoton-npcm750-evb.dts +deleted file mode 100644 +index 0334641f8829..000000000000 +--- a/scripts/dtc/include-prefixes/arm/nuvoton-npcm750-evb.dts ++++ /dev/null +@@ -1,404 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com +-// Copyright 2018 Google, Inc. +- +-/dts-v1/; +-#include "nuvoton-npcm750.dtsi" +-#include "dt-bindings/gpio/gpio.h" +-#include "nuvoton-npcm750-pincfg-evb.dtsi" +- +-/ { +- model = "Nuvoton npcm750 Development Board (Device Tree)"; +- compatible = "nuvoton,npcm750-evb", "nuvoton,npcm750"; +- +- aliases { +- ethernet2 = &gmac0; +- ethernet3 = &gmac1; +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c7; +- i2c8 = &i2c8; +- i2c9 = &i2c9; +- i2c10 = &i2c10; +- i2c11 = &i2c11; +- i2c12 = &i2c12; +- i2c13 = &i2c13; +- i2c14 = &i2c14; +- i2c15 = &i2c15; +- spi0 = &spi0; +- spi1 = &spi1; +- fiu0 = &fiu0; +- fiu1 = &fiu3; +- fiu2 = &fiux; +- }; +- +- chosen { +- stdout-path = &serial3; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x20000000>; +- }; +-}; +- +-&gmac0 { +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&gmac1 { +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&fiu0 { +- status = "okay"; +- spi-nor@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-rx-bus-width = <2>; +- reg = <0>; +- spi-max-frequency = <5000000>; +- partitions@80000000 { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- bbuboot1@0 { +- label = "bb-uboot-1"; +- reg = <0x0000000 0x80000>; +- read-only; +- }; +- bbuboot2@80000 { +- label = "bb-uboot-2"; +- reg = <0x0080000 0x80000>; +- read-only; +- }; +- envparam@100000 { +- label = "env-param"; +- reg = <0x0100000 0x40000>; +- read-only; +- }; +- spare@140000 { +- label = "spare"; +- reg = <0x0140000 0xC0000>; +- }; +- kernel@200000 { +- label = "kernel"; +- reg = <0x0200000 0x400000>; +- }; +- rootfs@600000 { +- label = "rootfs"; +- reg = <0x0600000 0x700000>; +- }; +- spare1@d00000 { +- label = "spare1"; +- reg = <0x0D00000 0x200000>; +- }; +- spare2@f00000 { +- label = "spare2"; +- reg = <0x0F00000 0x200000>; +- }; +- spare3@1100000 { +- label = "spare3"; +- reg = <0x1100000 0x200000>; +- }; +- spare4@1300000 { +- label = "spare4"; +- reg = <0x1300000 0x0>; +- }; +- }; +- }; +-}; +- +-&fiu3 { +- pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>; +- status = "okay"; +- spi-nor@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-rx-bus-width = <2>; +- reg = <0>; +- spi-max-frequency = <5000000>; +- partitions@A0000000 { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- system1@0 { +- label = "spi3-system1"; +- reg = <0x0 0x0>; +- }; +- }; +- }; +-}; +- +-&fiux { +- spix-mode; +-}; +- +-&watchdog1 { +- status = "okay"; +-}; +- +-&rng { +- status = "okay"; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&serial1 { +- status = "okay"; +-}; +- +-&serial2 { +- status = "okay"; +-}; +- +-&serial3 { +- status = "okay"; +-}; +- +-&adc { +- status = "okay"; +-}; +- +-&lpc_kcs { +- kcs1: kcs1@0 { +- status = "okay"; +- }; +- +- kcs2: kcs2@0 { +- status = "okay"; +- }; +- +- kcs3: kcs3@0 { +- status = "okay"; +- }; +-}; +- +-/* lm75 on SVB */ +-&i2c0 { +- clock-frequency = <100000>; +- status = "okay"; +- lm75@48 { +- compatible = "lm75"; +- reg = <0x48>; +- status = "okay"; +- }; +-}; +- +-/* lm75 on EB */ +-&i2c1 { +- clock-frequency = <100000>; +- status = "okay"; +- lm75@48 { +- compatible = "lm75"; +- reg = <0x48>; +- status = "okay"; +- }; +-}; +- +-/* tmp100 on EB */ +-&i2c2 { +- clock-frequency = <100000>; +- status = "okay"; +- tmp100@48 { +- compatible = "tmp100"; +- reg = <0x48>; +- status = "okay"; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&i2c5 { +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-/* tmp100 on SVB */ +-&i2c6 { +- clock-frequency = <100000>; +- status = "okay"; +- tmp100@48 { +- compatible = "tmp100"; +- reg = <0x48>; +- status = "okay"; +- }; +-}; +- +-&i2c7 { +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&i2c8 { +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&i2c9 { +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&i2c10 { +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&i2c11 { +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&i2c14 { +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +-&pwm_fan { +- status = "okay"; +- fan@0 { +- reg = <0x00>; +- fan-tach-ch = /bits/ 8 <0x00 0x01>; +- cooling-levels = <127 255>; +- }; +- fan@1 { +- reg = <0x01>; +- fan-tach-ch = /bits/ 8 <0x02 0x03>; +- cooling-levels = /bits/ 8 <127 255>; +- }; +- fan@2 { +- reg = <0x02>; +- fan-tach-ch = /bits/ 8 <0x04 0x05>; +- cooling-levels = /bits/ 8 <127 255>; +- }; +- fan@3 { +- reg = <0x03>; +- fan-tach-ch = /bits/ 8 <0x06 0x07>; +- cooling-levels = /bits/ 8 <127 255>; +- }; +- fan@4 { +- reg = <0x04>; +- fan-tach-ch = /bits/ 8 <0x08 0x09>; +- cooling-levels = /bits/ 8 <127 255>; +- }; +- fan@5 { +- reg = <0x05>; +- fan-tach-ch = /bits/ 8 <0x0A 0x0B>; +- cooling-levels = /bits/ 8 <127 255>; +- }; +- fan@6 { +- reg = <0x06>; +- fan-tach-ch = /bits/ 8 <0x0C 0x0D>; +- cooling-levels = /bits/ 8 <127 255>; +- }; +- fan@7 { +- reg = <0x07>; +- fan-tach-ch = /bits/ 8 <0x0E 0x0F>; +- cooling-levels = /bits/ 8 <127 255>; +- }; +-}; +- +-&spi0 { +- cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; +- status = "okay"; +- Flash@0 { +- compatible = "winbond,w25q128", +- "jedec,spi-nor"; +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <5000000>; +- partition@0 { +- label = "spi0_spare1"; +- reg = <0x0000000 0x800000>; +- }; +- partition@1 { +- label = "spi0_spare2"; +- reg = <0x800000 0x0>; +- }; +- }; +-}; +- +-&spi1 { +- cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; +- status = "okay"; +- Flash@0 { +- compatible = "winbond,w25q128fw", +- "jedec,spi-nor"; +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <5000000>; +- partition@0 { +- label = "spi1_spare1"; +- reg = <0x0000000 0x800000>; +- }; +- partition@1 { +- label = "spi1_spare2"; +- reg = <0x800000 0x0>; +- }; +- }; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = < &iox1_pins +- &pin8_input +- &pin9_output_high +- &pin10_input +- &pin11_output_high +- &pin16_input +- &pin24_output_high +- &pin25_output_low +- &pin32_output_high +- &jtag2_pins +- &pin61_output_high +- &pin62_output_high +- &pin63_output_high +- &lpc_pins +- &pin160_input +- &pin162_input +- &pin168_input +- &pin169_input +- &pin170_input +- &pin187_output_high +- &pin190_input +- &pin191_output_high +- &pin192_output_high +- &pin197_output_low +- &ddc_pins +- &pin218_input +- &pin219_output_low +- &pin220_output_low +- &pin221_output_high +- &pin222_input +- &pin223_output_low +- &spix_pins +- &pin228_output_low +- &pin231_output_high +- &pin255_input>; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/nuvoton-npcm750-pincfg-evb.dtsi b/scripts/dtc/include-prefixes/arm/nuvoton-npcm750-pincfg-evb.dtsi +deleted file mode 100644 +index 3b3806274adf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/nuvoton-npcm750-pincfg-evb.dtsi ++++ /dev/null +@@ -1,157 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2018 Nuvoton Technology +- +-/ { +- pinctrl: pinctrl@f0800000 { +- pin8_input: pin8-input { +- pins = "GPIO8/LKGPO1"; +- bias-disable; +- input-enable; +- }; +- pin9_output_high: pin9-output-high { +- pins = "GPIO9/LKGPO2"; +- bias-disable; +- output-high; +- }; +- pin10_input: pin10-input { +- pins = "GPIO10/IOXHLD"; +- bias-disable; +- input-enable; +- }; +- pin11_output_high: pin11-output-high { +- pins = "GPIO11/IOXHCK"; +- bias-disable; +- output-high; +- }; +- pin16_input: pin16-input { +- pins = "GPIO16/LKGPO0"; +- bias-disable; +- input-enable; +- }; +- pin24_output_high: pin24-output-high { +- pins = "GPIO24/IOXHDO"; +- bias-disable; +- output-high; +- }; +- pin25_output_low: pin25-output-low { +- pins = "GPIO25/IOXHDI"; +- bias-disable; +- output-low; +- }; +- pin32_output_high: pin32-output-high { +- pins = "GPIO32/nSPI0CS1"; +- bias-disable; +- output-high; +- }; +- pin61_output_high: pin61-output-high { +- pins = "GPO61/nDTR1_BOUT1/STRAP6"; +- bias-disable; +- output-high; +- }; +- pin62_output_high: pin62-output-high { +- pins = "GPO62/nRTST1/STRAP5"; +- bias-disable; +- output-high; +- }; +- pin63_output_high: pin63-output-high { +- pins = "GPO63/TXD1/STRAP4"; +- bias-disable; +- output-high; +- }; +- pin160_input: pin160-input { +- pins = "GPIO160/CLKOUT/RNGOSCOUT"; +- bias-disable; +- input-enable; +- }; +- pin162_input: pin162-input { +- pins = "GPIO162/SERIRQ"; +- bias-disable; +- input-enable; +- }; +- pin168_input: pin168-input { +- pins = "GPIO168/nCLKRUN/nESPIALERT"; +- bias-disable; +- input-enable; +- }; +- pin169_input: pin169-input { +- pins = "GPIO169/nSCIPME"; +- bias-disable; +- input-enable; +- }; +- pin170_input: pin170-input { +- pins = "GPIO170/nSMI"; +- bias-disable; +- input-enable; +- }; +- pin187_output_high: pin187-output-high { +- pins = "GPIO187/nSPI3CS1"; +- bias-disable; +- output-high; +- }; +- pin190_input: pin190-input { +- pins = "GPIO190/nPRD_SMI"; +- bias-disable; +- input-enable; +- }; +- pin191_output_high: pin191-output-high { +- pins = "GPIO191"; +- bias-disable; +- output-high; +- }; +- pin192_output_high: pin192-output-high { +- pins = "GPIO192"; +- bias-disable; +- output-high; +- }; +- pin197_output_low: pin197-output-low { +- pins = "GPIO197/SMB0DEN"; +- bias-disable; +- output-low; +- }; +- pin218_input: pin218-input { +- pins = "GPIO218/nWDO1"; +- bias-disable; +- input-enable; +- }; +- pin219_output_low: pin219-output-low { +- pins = "GPIO219/nWDO2"; +- bias-disable; +- output-low; +- }; +- pin220_output_low: pin220-output-low { +- pins = "GPIO220/SMB12SCL"; +- bias-disable; +- output-low; +- }; +- pin221_output_high: pin221-output-high { +- pins = "GPIO221/SMB12SDA"; +- bias-disable; +- output-high; +- }; +- pin222_input: pin222-input { +- pins = "GPIO222/SMB13SCL"; +- bias-disable; +- input-enable; +- }; +- pin223_output_low: pin223-output-low { +- pins = "GPIO223/SMB13SDA"; +- bias-disable; +- output-low; +- }; +- pin228_output_low: pin228-output-low { +- pins = "GPIO228/nSPIXCS1"; +- bias-disable; +- output-low; +- }; +- pin231_output_high: pin231-output-high { +- pins = "GPIO230/SPIXD3"; +- bias-disable; +- output-high; +- }; +- pin255_input: pin255-input { +- pins = "GPI255/DACOSEL"; +- bias-disable; +- input-enable; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi b/scripts/dtc/include-prefixes/arm/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi +deleted file mode 100644 +index 230cb344b2e1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi ++++ /dev/null +@@ -1,517 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2019 Quanta Computer Inc. Samuel.Jiang@quantatw.com +- +-/ { +- pinctrl: pinctrl@f0800000 { +- gpio0ol_pins: gpio0ol-pins { +- pins = "GPIO0/IOX1DI"; +- bias-disable; +- output-low; +- }; +- gpio1ol_pins: gpio1ol-pins { +- pins = "GPIO1/IOX1LD"; +- bias-disable; +- output-low; +- }; +- gpio2ol_pins: gpio2ol-pins { +- pins = "GPIO2/IOX1CK"; +- bias-disable; +- output-low; +- }; +- gpio3ol_pins: gpio3ol-pins { +- pins = "GPIO3/IOX1D0"; +- bias-disable; +- output-low; +- }; +- gpio5_pins: gpio5-pins { +- pins = "GPIO5/IOX2LD/SMB1DSCL"; +- bias-disable; +- input-enable; +- }; +- gpio6_pins: gpio6-pins { +- pins = "GPIO6/IOX2CK/SMB2DSDA"; +- bias-disable; +- input-enable; +- }; +- gpio7_pins: gpio7-pins { +- pins = "GPIO7/IOX2D0/SMB2DSCL"; +- bias-disable; +- input-enable; +- }; +- gpio8o_pins: gpio8o-pins { +- pins = "GPIO8/LKGPO1"; +- bias-disable; +- output-high; +- }; +- gpio9ol_pins: gpio9ol-pins { +- pins = "GPIO9/LKGPO2"; +- bias-disable; +- output-low; +- }; +- gpio10_pins: gpio10-pins { +- pins = "GPIO10/IOXHLD"; +- bias-disable; +- input-enable; +- }; +- gpio11_pins: gpio11-pins { +- pins = "GPIO11/IOXHCK"; +- bias-disable; +- input-enable; +- }; +- gpio12ol_pins: gpio12ol-pins { +- pins = "GPIO12/GSPICK/SMB5BSCL"; +- bias-disable; +- output-low; +- }; +- gpio13ol_pins: gpio13ol-pins { +- pins = "GPIO13/GSPIDO/SMB5BSDA"; +- bias-disable; +- output-low; +- }; +- gpio14ol_pins: gpio14ol-pins { +- pins = "GPIO14/GSPIDI/SMB5CSCL"; +- bias-disable; +- output-low; +- }; +- gpio15ol_pins: gpio15ol-pins { +- pins = "GPIO15/GSPICS/SMB5CSDA"; +- bias-disable; +- output-low; +- }; +- gpio20_pins: gpio20-pins { +- pins = "GPIO20/SMB4CSDA/SMB15SDA"; +- bias-disable; +- input-enable; +- }; +- gpio21_pins: gpio21-pins { +- pins = "GPIO21/SMB4CSCL/SMB15SCL"; +- bias-disable; +- input-enable; +- }; +- gpio22o_pins: gpio22o-pins { +- pins = "GPIO22/SMB4DSDA/SMB14SDA"; +- bias-disable; +- output-high; +- }; +- gpio23_pins: gpio23-pins { +- pins = "GPIO23/SMB4DSCL/SMB14SCL"; +- bias-disable; +- input-enable; +- }; +- gpio24_pins: gpio24-pins { +- pins = "GPIO24/IOXHDO"; +- bias-disable; +- input-enable; +- }; +- gpio25_pins: gpio25-pins { +- pins = "GPIO25/IOXHDI"; +- bias-disable; +- input-enable; +- }; +- gpio30_pins: gpio30-pins { +- pins = "GPIO30/SMB3SDA"; +- bias-disable; +- input-enable; +- }; +- gpio31_pins: gpio31-pins { +- pins = "GPIO31/SMB3SCL"; +- bias-disable; +- input-enable; +- }; +- gpio37o_pins: gpio37o-pins { +- pins = "GPIO37/SMB3CSDA"; +- bias-disable; +- output-high; +- }; +- gpio38_pins: gpio38-pins { +- pins = "GPIO38/SMB3CSCL"; +- bias-disable; +- input-enable; +- }; +- gpio39_pins: gpio39-pins { +- pins = "GPIO39/SMB3BSDA"; +- bias-disable; +- input-enable; +- }; +- gpio40o_pins: gpio40o-pins { +- pins = "GPIO40/SMB3BSCL"; +- bias-disable; +- output-high; +- }; +- gpio59_pins: gpio59-pins { +- pins = "GPIO59/SMB3DSDA"; +- bias-disable; +- input-enable; +- }; +- gpio76_pins: gpio76-pins { +- pins = "GPIO76/FANIN12"; +- bias-disable; +- input-enable; +- }; +- gpio77_pins: gpio77-pins { +- pins = "GPIO77/FANIN13"; +- bias-disable; +- input-enable; +- }; +- gpio78o_pins: gpio78o-pins { +- pins = "GPIO78/FANIN14"; +- bias-disable; +- output-high; +- }; +- gpio79_pins: gpio79-pins { +- pins = "GPIO79/FANIN15"; +- bias-disable; +- input-enable; +- }; +- gpio82_pins: gpio82-pins { +- pins = "GPIO82/PWM2"; +- bias-disable; +- input-enable; +- }; +- gpio83_pins: gpio83-pins { +- pins = "GPIO83/PWM3"; +- bias-disable; +- input-enable; +- }; +- gpio84_pins: gpio84-pins { +- pins = "GPIO84/R2TXD0"; +- bias-disable; +- input-enable; +- }; +- gpio85o_pins: gpio85o-pins { +- pins = "GPIO85/R2TXD1"; +- bias-disable; +- output-high; +- }; +- gpio86ol_pins: gpio86ol-pins { +- pins = "GPIO86/R2TXEN"; +- bias-disable; +- output-low; +- }; +- gpio87_pins: gpio87-pins { +- pins = "GPIO87/R2RXD0"; +- bias-disable; +- input-enable; +- }; +- gpio88_pins: gpio88-pins { +- pins = "GPIO88/R2RXD1"; +- bias-disable; +- input-enable; +- }; +- gpio89_pins: gpio89-pins { +- pins = "GPIO89/R2CRSDV"; +- bias-disable; +- input-enable; +- }; +- gpio90_pins: gpio90-pins { +- pins = "GPIO90/R2RXERR"; +- bias-disable; +- input-enable; +- }; +- gpio93_pins: gpio93-pins { +- pins = "GPIO93/GA20/SMB5DSCL"; +- bias-disable; +- input-enable; +- }; +- gpio94ol_pins: gpio94ol-pins { +- pins = "GPIO94/nKBRST/SMB5DSDA"; +- bias-disable; +- output-low; +- }; +- gpio108ol_pins: gpio108ol-pins { +- pins = "GPIO108/RG1MDC"; +- bias-disable; +- output-low; +- }; +- gpio109ol_pins: gpio109ol-pins { +- pins = "GPIO109/RG1MDIO"; +- bias-disable; +- output-low; +- }; +- gpio110ol_pins: gpio110ol-pins { +- pins = "GPIO110/RG2TXD0/DDRV0"; +- bias-disable; +- output-low; +- }; +- gpio111ol_pins: gpio111ol-pins { +- pins = "GPIO111/RG2TXD1/DDRV1"; +- bias-disable; +- output-low; +- }; +- gpio112ol_pins: gpio112ol-pins { +- pins = "GPIO112/RG2TXD2/DDRV2"; +- bias-disable; +- output-low; +- }; +- gpio113ol_pins: gpio113ol-pins { +- pins = "GPIO113/RG2TXD3/DDRV3"; +- bias-disable; +- output-low; +- }; +- gpio114o_pins: gpio114o-pins { +- pins = "GPIO114/SMB0SCL"; +- bias-disable; +- output-high; +- }; +- gpio115_pins: gpio115-pins { +- pins = "GPIO115/SMB0SDA"; +- bias-disable; +- input-enable; +- }; +- gpio120_pins: gpio120-pins { +- pins = "GPIO120/SMB2CSDA"; +- bias-disable; +- input-enable; +- }; +- gpio121_pins: gpio121-pins { +- pins = "GPIO121/SMB2CSCL"; +- bias-disable; +- input-enable; +- }; +- gpio122_pins: gpio122-pins { +- pins = "GPIO122/SMB2BSDA"; +- bias-disable; +- input-enable; +- }; +- gpio123_pins: gpio123-pins { +- pins = "GPIO123/SMB2BSCL"; +- bias-disable; +- input-enable; +- }; +- gpio124_pins: gpio124-pins { +- pins = "GPIO124/SMB1CSDA"; +- bias-disable; +- input-enable; +- }; +- gpio125_pins: gpio125-pins { +- pins = "GPIO125/SMB1CSCL"; +- bias-disable; +- input-enable; +- }; +- gpio126_pins: gpio126-pins { +- pins = "GPIO126/SMB1BSDA"; +- bias-disable; +- input-enable; +- }; +- gpio127o_pins: gpio127o-pins { +- pins = "GPIO127/SMB1BSCL"; +- bias-disable; +- output-high; +- }; +- gpio136_pins: gpio136-pins { +- pins = "GPIO136/SD1DT0"; +- bias-disable; +- input-enable; +- }; +- gpio137_pins: gpio137-pins { +- pins = "GPIO137/SD1DT1"; +- bias-disable; +- input-enable; +- }; +- gpio138_pins: gpio138-pins { +- pins = "GPIO138/SD1DT2"; +- bias-disable; +- input-enable; +- }; +- gpio139_pins: gpio139-pins { +- pins = "GPIO139/SD1DT3"; +- bias-disable; +- input-enable; +- }; +- gpio140_pins: gpio140-pins { +- pins = "GPIO140/SD1CLK"; +- bias-disable; +- input-enable; +- }; +- gpio141_pins: gpio141-pins { +- pins = "GPIO141/SD1WP"; +- bias-disable; +- input-enable; +- }; +- gpio142_pins: gpio142-pins { +- pins = "GPIO142/SD1CMD"; +- bias-disable; +- input-enable; +- }; +- gpio143_pins: gpio143-pins { +- pins = "GPIO143/SD1CD/SD1PWR"; +- bias-disable; +- input-enable; +- }; +- gpio144_pins: gpio144-pins { +- pins = "GPIO144/PWM4"; +- bias-disable; +- input-enable; +- }; +- gpio145_pins: gpio145-pins { +- pins = "GPIO145/PWM5"; +- bias-disable; +- input-enable; +- }; +- gpio146_pins: gpio146-pins { +- pins = "GPIO146/PWM6"; +- bias-disable; +- input-enable; +- }; +- gpio147_pins: gpio147-pins { +- pins = "GPIO147/PWM7"; +- bias-disable; +- input-enable; +- }; +- gpio153o_pins: gpio153o-pins { +- pins = "GPIO153/MMCWP"; +- bias-disable; +- output-high; +- }; +- gpio155_pins: gpio155-pins { +- pins = "GPIO155/nMMCCD/nMMCRST"; +- bias-disable; +- input-enable; +- }; +- gpio160o_pins: gpio160o-pins { +- pins = "GPIO160/CLKOUT/RNGOSCOUT"; +- bias-disable; +- output-high; +- }; +- gpio169o_pins: gpio169o-pins { +- pins = "GPIO169/nSCIPME"; +- bias-disable; +- output-high; +- }; +- gpio188o_pins: gpio188o-pins { +- pins = "GPIO188/SPI3D2/nSPI3CS2"; +- bias-disable; +- output-high; +- }; +- gpio189_pins: gpio189-pins { +- pins = "GPIO189/SPI3D3/nSPI3CS3"; +- bias-disable; +- input-enable; +- }; +- gpio196_pins: gpio196-pins { +- pins = "GPIO196/SMB0CSCL"; +- bias-disable; +- input-enable; +- }; +- gpio197_pins: gpio197-pins { +- pins = "GPIO197/SMB0DEN"; +- bias-disable; +- input-enable; +- }; +- gpio198o_pins: gpio198o-pins { +- pins = "GPIO198/SMB0DSDA"; +- bias-disable; +- output-high; +- }; +- gpio199o_pins: gpio199o-pins { +- pins = "GPIO199/SMB0DSCL"; +- bias-disable; +- output-high; +- }; +- gpio200_pins: gpio200-pins { +- pins = "GPIO200/R2CK"; +- input-enable; +- bias-disable; +- }; +- gpio202_pins: gpio202-pins { +- pins = "GPIO202/SMB0CSDA"; +- bias-disable; +- input-enable; +- }; +- gpio203o_pins: gpio203o-pins { +- pins = "GPIO203/FANIN16"; +- bias-disable; +- output-high; +- }; +- gpio208_pins: gpio208-pins { +- pins = "GPIO208/RG2TXC/DVCK"; +- bias-disable; +- input-enable; +- }; +- gpio209ol_pins: gpio209ol-pins { +- pins = "GPIO209/RG2TXCTL/DDRV4"; +- bias-disable; +- output-low; +- }; +- gpio210ol_pins: gpio210ol-pins { +- pins = "GPIO210/RG2RXD0/DDRV5"; +- bias-disable; +- output-low; +- }; +- gpio211ol_pins: gpio211ol-pins { +- pins = "GPIO211/RG2RXD1/DDRV6"; +- bias-disable; +- output-low; +- }; +- gpio212ol_pins: gpio212ol-pins { +- pins = "GPIO212/RG2RXD2/DDRV7"; +- bias-disable; +- output-low; +- }; +- gpio213ol_pins: gpio213ol-pins { +- pins = "GPIO213/RG2RXD3/DDRV8"; +- bias-disable; +- output-low; +- }; +- gpio214ol_pins: gpio214ol-pins { +- pins = "GPIO214/RG2RXC/DDRV9"; +- bias-disable; +- output-low; +- }; +- gpio215ol_pins: gpio215ol-pins { +- pins = "GPIO215/RG2RXCTL/DDRV10"; +- bias-disable; +- output-low; +- }; +- gpio216ol_pins: gpio216ol-pins { +- pins = "GPIO216/RG2MDC/DDRV11"; +- bias-disable; +- output-low; +- }; +- gpio217ol_pins: gpio217ol-pins { +- pins = "GPIO217/RG2MDIO/DVHSYNC"; +- bias-disable; +- output-low; +- }; +- gpio224_pins: gpio224-pins { +- pins = "GPIO224/SPIXCK"; +- bias-disable; +- input-enable; +- }; +- gpio225ol_pins: gpio225ol-pins { +- pins = "GPO225/SPIXD0/STRAP12"; +- bias-disable; +- output-low; +- }; +- gpio226ol_pins: gpio226ol-pins { +- pins = "GPO226/SPIXD1/STRAP13"; +- bias-disable; +- output-low; +- }; +- gpio227ol_pins: gpio227ol-pins { +- pins = "GPIO227/nSPIXCS0"; +- bias-disable; +- output-low; +- }; +- gpio228o_pins: gpio228ol-pins { +- pins = "GPIO228/nSPIXCS1"; +- bias-disable; +- output-high; +- }; +- gpio229o_pins: gpio229o-pins { +- pins = "GPO229/SPIXD2/STRAP3"; +- bias-disable; +- output-high; +- }; +- gpio230_pins: gpio230-pins { +- pins = "GPIO230/SPIXD3"; +- bias-disable; +- input-enable; +- }; +- gpio231o_pins: gpio231o-pins { +- pins = "GPIO231/nCLKREQ"; +- bias-disable; +- output-high; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/nuvoton-npcm750-runbmc-olympus.dts b/scripts/dtc/include-prefixes/arm/nuvoton-npcm750-runbmc-olympus.dts +deleted file mode 100644 +index 767e0ac0df7c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/nuvoton-npcm750-runbmc-olympus.dts ++++ /dev/null +@@ -1,1052 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2019 Nuvoton Technology +-// Copyright (c) 2019 Quanta Computer Inc. +- +-/dts-v1/; +-#include "nuvoton-npcm750.dtsi" +-#include "nuvoton-npcm750-runbmc-olympus-pincfg.dtsi" +- +-#include +-#include +- +-/ { +- model = "Nuvoton npcm750 RunBMC Olympus"; +- compatible = "nuvoton,npcm750"; +- +- aliases { +- ethernet1 = &gmac0; +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c7; +- i2c8 = &i2c8; +- i2c9 = &i2c9; +- i2c10 = &i2c10; +- i2c11 = &i2c11; +- i2c12 = &i2c12; +- i2c13 = &i2c13; +- spi0 = &spi0; +- spi1 = &spi1; +- fiu0 = &fiu0; +- fiu1 = &fiu3; +- }; +- +- chosen { +- stdout-path = &serial3; +- }; +- +- memory { +- reg = <0 0x40000000>; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, +- <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- heartbeat { +- label = "heartbeat"; +- gpios = <&gpio3 14 1>; +- }; +- +- identify { +- label = "identify"; +- gpios = <&gpio3 15 1>; +- }; +- }; +- +- jtag { +- compatible = "nuvoton,npcm750-jtag"; +- enable_pspi_jtag = <1>; +- pspi-index = <2>; +- tck { +- label = "tck"; +- gpios = <&gpio0 19 0>; /* gpio19 */ +- regbase = <0xf0010000 0x1000>; +- }; +- +- tdi { +- label = "tdi"; +- gpios = <&gpio0 18 0>; /* gpio18 */ +- regbase = <0xf0010000 0x1000>; +- }; +- +- tdo { +- label = "tdo"; +- gpios = <&gpio0 17 0>; /* gpio17 */ +- regbase = <0xf0010000 0x1000>; +- }; +- tms { +- label = "tms"; +- gpios = <&gpio0 16 0>; /* gpio16 */ +- regbase = <0xf0010000 0x1000>; +- }; +- }; +-}; +- +-&fiu0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0cs1_pins>; +- status = "okay"; +- +- spi-nor@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- spi-rx-bus-width = <2>; +- +- partitions@80000000 { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- bmc@0{ +- label = "bmc"; +- reg = <0x000000 0x2000000>; +- }; +- u-boot@0 { +- label = "u-boot"; +- reg = <0x0000000 0x80000>; +- read-only; +- }; +- u-boot-env@100000{ +- label = "u-boot-env"; +- reg = <0x00100000 0x40000>; +- }; +- kernel@200000 { +- label = "kernel"; +- reg = <0x0200000 0x600000>; +- }; +- rofs@800000 { +- label = "rofs"; +- reg = <0x800000 0x1500000>; +- }; +- rwfs@1d00000 { +- label = "rwfs"; +- reg = <0x1d00000 0x300000>; +- }; +- }; +- }; +- +- spi-nor@1 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <1>; +- npcm,fiu-rx-bus-width = <2>; +- +- partitions@88000000 { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- spare1@0 { +- label = "spi0-cs1-spare1"; +- reg = <0x0 0x800000>; +- }; +- spare2@800000 { +- label = "spi0-cs1-spare2"; +- reg = <0x800000 0x0>; +- }; +- }; +- }; +-}; +- +-&fiu3 { +- pinctrl-0 = <&spi3_pins>; +- status = "okay"; +- +- spi-nor@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- spi-rx-bus-width = <2>; +- +- partitions@A0000000 { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- system1@0 { +- label = "spi3-system1"; +- reg = <0x0 0x800000>; +- }; +- system2@800000 { +- label = "spi3-system2"; +- reg = <0x800000 0x0>; +- }; +- }; +- }; +-}; +- +-&gcr { +- mux-controller { +- compatible = "mmio-mux"; +- #mux-control-cells = <1>; +- +- mux-reg-masks = <0x38 0x07>; +- idle-states = <6>; +- }; +-}; +- +-&gmac0 { +- phy-mode = "rgmii-id"; +- snps,eee-force-disable; +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- i2c_slot1a: i2c-bus@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c_slot1b: i2c-bus@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- i2c_slot2a: i2c-bus@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c_slot2b: i2c-bus@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- i2c_slot3: i2c-bus@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- i2c_slot4: i2c-bus@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- i2c_slot5: i2c-bus@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- }; +- +- i2c-switch@71 { +- compatible = "nxp,pca9546"; +- reg = <0x71>; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-mux-idle-disconnect; +- +- i2c_m2_s1: i2c-bus@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c_m2_s2: i2c-bus@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- i2c_m2_s3: i2c-bus@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c_m2_s4: i2c-bus@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- +- tmp421@4c { +- compatible = "ti,tmp421"; +- reg = <0x4c>; +- }; +- +- power-supply@58 { +- compatible = "delta,dps800"; +- reg = <0x58>; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +- +- eeprom@54 { +- compatible = "atmel,24c64"; +- reg = <0x54>; +- }; +-}; +- +-&i2c5 { +- status = "okay"; +- +- i2c-slave-mqueue@10 { +- compatible = "i2c-slave-mqueue"; +- reg = <(I2C_OWN_SLAVE_ADDRESS | 0x10)>; +- }; +-}; +- +-&i2c6 { +- status = "okay"; +- +- ina219@40 { +- compatible = "ti,ina219"; +- reg = <0x40>; +- }; +- ina219@41 { +- compatible = "ti,ina219"; +- reg = <0x41>; +- }; +- ina219@44 { +- compatible = "ti,ina219"; +- reg = <0x44>; +- }; +- ina219@45 { +- compatible = "ti,ina219"; +- reg = <0x45>; +- }; +- tps53679@60 { +- compatible = "ti,tps53679"; +- reg = <0x60>; +- }; +- tps53659@62 { +- compatible = "ti,tps53659"; +- reg = <0x62>; +- }; +- tps53659@64 { +- compatible = "ti,tps53659"; +- reg = <0x64>; +- }; +- tps53622@67 { +- compatible = "ti,tps53622"; +- reg = <0x67>; +- }; +- tps53622@69 { +- compatible = "ti,tps53622"; +- reg = <0x69>; +- }; +- tps53679@70 { +- compatible = "ti,tps53679"; +- reg = <0x70>; +- }; +- tps53659@72 { +- compatible = "ti,tps53659"; +- reg = <0x72>; +- }; +- tps53659@74 { +- compatible = "ti,tps53659"; +- reg = <0x74>; +- }; +- tps53622@77 { +- compatible = "ti,tps53622"; +- reg = <0x77>; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +- +- tmp421@4c { +- compatible = "ti,tmp421"; +- reg = <0x4c>; +- }; +-}; +- +-&i2c8 { +- status = "okay"; +- +- adm1278@11 { +- compatible = "adm1278"; +- reg = <0x11>; +- Rsense = <500>; +- }; +-}; +- +-&i2c9 { +- status = "okay"; +-}; +- +-&i2c10 { +- status = "okay"; +- +- gpio: pca9555@27 { +- compatible = "nxp,pca9555"; +- reg = <0x27>; +- +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&i2c11 { +- status = "okay"; +- +- pca9539_g1a: pca9539-g1a@74 { +- compatible = "nxp,pca9539"; +- reg = <0x74>; +- gpio-controller; +- #gpio-cells = <2>; +- reset-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; +- G1A_P0_0 { +- gpio-hog; +- gpios = <0 0>; +- output-high; +- line-name = "TPM_BMC_ALERT_N"; +- }; +- G1A_P0_1 { +- gpio-hog; +- gpios = <1 0>; +- input; +- line-name = "FM_BIOS_TOP_SWAP"; +- }; +- G1A_P0_2 { +- gpio-hog; +- gpios = <2 0>; +- input; +- line-name = "FM_BIOS_PREFRB2_GOOD"; +- }; +- G1A_P0_3 { +- gpio-hog; +- gpios = <3 0>; +- input; +- line-name = "BMC_SATAXPCIE_0TO3_SEL"; +- }; +- G1A_P0_4 { +- gpio-hog; +- gpios = <4 0>; +- input; +- line-name = "BMC_SATAXPCIE_4TO7_SEL"; +- }; +- G1A_P0_5 { +- gpio-hog; +- gpios = <5 0>; +- output-low; +- line-name = "FM_UV_ADR_TRIGGER_EN_N"; +- }; +- G1A_P0_6 { +- gpio-hog; +- gpios = <6 0>; +- input; +- line-name = "RM_THROTTLE_EN_N"; +- }; +- G1A_P1_0 { +- gpio-hog; +- gpios = <8 0>; +- input; +- line-name = "FM_BMC_TPM_PRES_N"; +- }; +- G1A_P1_1 { +- gpio-hog; +- gpios = <9 0>; +- input; +- line-name = "FM_CPU0_SKTOCC_LVT3_N"; +- }; +- G1A_P1_2 { +- gpio-hog; +- gpios = <10 0>; +- input; +- line-name = "FM_CPU1_SKTOCC_LVT3_N"; +- }; +- G1A_P1_3 { +- gpio-hog; +- gpios = <11 0>; +- input; +- line-name = "PSU1_ALERT_N"; +- }; +- G1A_P1_4 { +- gpio-hog; +- gpios = <12 0>; +- input; +- line-name = "PSU2_ALERT_N"; +- }; +- G1A_P1_5 { +- gpio-hog; +- gpios = <13 0>; +- input; +- line-name = "H_CPU0_FAST_WAKE_LVT3_N"; +- }; +- G1A_P1_6 { +- gpio-hog; +- gpios = <14 0>; +- output-high; +- line-name = "I2C_MUX1_RESET_N"; +- }; +- G1A_P1_7 { +- gpio-hog; +- gpios = <15 0>; +- input; +- line-name = "FM_CPU_CATERR_LVT3_N"; +- }; +- }; +- +- pca9539_g1b: pca9539-g1b@75 { +- compatible = "nxp,pca9539"; +- reg = <0x75>; +- gpio-controller; +- #gpio-cells = <2>; +- G1B_P0_0 { +- gpio-hog; +- gpios = <0 0>; +- input; +- line-name = "PVDDQ_ABC_PINALERT_N"; +- }; +- G1B_P0_1 { +- gpio-hog; +- gpios = <1 0>; +- input; +- line-name = "PVDDQ_DEF_PINALERT_N"; +- }; +- G1B_P0_2 { +- gpio-hog; +- gpios = <2 0>; +- input; +- line-name = "PVDDQ_GHJ_PINALERT_N"; +- }; +- G1B_P0_3 { +- gpio-hog; +- gpios = <3 0>; +- input; +- line-name = "PVDDQ_KLM_PINALERT_N"; +- }; +- G1B_P0_5 { +- gpio-hog; +- gpios = <5 0>; +- input; +- line-name = "FM_BOARD_REV_ID0"; +- }; +- G1B_P0_6 { +- gpio-hog; +- gpios = <6 0>; +- input; +- line-name = "FM_BOARD_REV_ID1"; +- }; +- G1B_P0_7 { +- gpio-hog; +- gpios = <7 0>; +- input; +- line-name = "FM_BOARD_REV_ID2"; +- }; +- G1B_P1_0 { +- gpio-hog; +- gpios = <8 0>; +- input; +- line-name = "FM_OC_DETECT_EN_N"; +- }; +- G1B_P1_1 { +- gpio-hog; +- gpios = <9 0>; +- input; +- line-name = "FM_FLASH_DESC_OVERRIDE"; +- }; +- G1B_P1_2 { +- gpio-hog; +- gpios = <10 0>; +- output-low; +- line-name = "FP_PWR_ID_LED_N"; +- }; +- G1B_P1_3 { +- gpio-hog; +- gpios = <11 0>; +- output-low; +- line-name = "BMC_LED_PWR_GRN"; +- }; +- G1B_P1_4 { +- gpio-hog; +- gpios = <12 0>; +- output-low; +- line-name = "BMC_LED_PWR_AMBER"; +- }; +- G1B_P1_5 { +- gpio-hog; +- gpios = <13 0>; +- output-high; +- line-name = "FM_BMC_FAULT_LED_N"; +- }; +- G1B_P1_6 { +- gpio-hog; +- gpios = <14 0>; +- output-high; +- line-name = "FM_CPLD_BMC_PWRDN_N"; +- }; +- G1B_P1_7 { +- gpio-hog; +- gpios = <15 0>; +- output-high; +- line-name = "BMC_LED_CATERR_N"; +- }; +- }; +-}; +- +-&i2c12 { +- status = "okay"; +- +- pca9539_g2a: pca9539-g2a@74 { +- compatible = "nxp,pca9539"; +- reg = <0x74>; +- gpio-controller; +- #gpio-cells = <2>; +- reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; +- G2A_P0_0 { +- gpio-hog; +- gpios = <0 0>; +- output-high; +- line-name = "BMC_PON_RST_REQ_N"; +- }; +- G2A_P0_1 { +- gpio-hog; +- gpios = <1 0>; +- output-high; +- line-name = "BMC_RST_IND_REQ_N"; +- }; +- G2A_P0_2 { +- gpio-hog; +- gpios = <2 0>; +- input; +- line-name = "RST_BMC_RTCRST"; +- }; +- G2A_P0_3 { +- gpio-hog; +- gpios = <3 0>; +- output-high; +- line-name = "FM_BMC_PWRBTN_OUT_N"; +- }; +- G2A_P0_4 { +- gpio-hog; +- gpios = <4 0>; +- output-high; +- line-name = "RST_BMC_SYSRST_BTN_OUT_N"; +- }; +- G2A_P0_5 { +- gpio-hog; +- gpios = <5 0>; +- output-high; +- line-name = "FM_BATTERY_SENSE_EN_N"; +- }; +- G2A_P0_6 { +- gpio-hog; +- gpios = <6 0>; +- output-high; +- line-name = "FM_BMC_READY_N"; +- }; +- G2A_P0_7 { +- gpio-hog; +- gpios = <7 0>; +- input; +- line-name = "IRQ_BMC_PCH_SMI_LPC_N"; +- }; +- G2A_P1_0 { +- gpio-hog; +- gpios = <8 0>; +- input; +- line-name = "FM_SLOT4_CFG0"; +- }; +- G2A_P1_1 { +- gpio-hog; +- gpios = <9 0>; +- input; +- line-name = "FM_SLOT4_CFG1"; +- }; +- G2A_P1_2 { +- gpio-hog; +- gpios = <10 0>; +- input; +- line-name = "FM_NVDIMM_EVENT_N"; +- }; +- G2A_P1_3 { +- gpio-hog; +- gpios = <11 0>; +- input; +- line-name = "PSU1_BLADE_EN_N"; +- }; +- G2A_P1_4 { +- gpio-hog; +- gpios = <12 0>; +- input; +- line-name = "BMC_PCH_FNM"; +- }; +- G2A_P1_5 { +- gpio-hog; +- gpios = <13 0>; +- input; +- line-name = "FM_SOL_UART_CH_SEL"; +- }; +- G2A_P1_6 { +- gpio-hog; +- gpios = <14 0>; +- input; +- line-name = "FM_BIOS_POST_CMPLT_N"; +- }; +- }; +- +- pca9539_g2b: pca9539-g2b@75 { +- compatible = "nxp,pca9539"; +- reg = <0x75>; +- gpio-controller; +- #gpio-cells = <2>; +- G2B_P0_0 { +- gpio-hog; +- gpios = <0 0>; +- input; +- line-name = "FM_CPU_MSMI_LVT3_N"; +- }; +- G2B_P0_1 { +- gpio-hog; +- gpios = <1 0>; +- input; +- line-name = "FM_BIOS_MRC_DEBUG_MSG_DIS"; +- }; +- G2B_P0_2 { +- gpio-hog; +- gpios = <2 0>; +- input; +- line-name = "FM_CPU1_DISABLE_BMC_N"; +- }; +- G2B_P0_3 { +- gpio-hog; +- gpios = <3 0>; +- output-low; +- line-name = "BMC_JTAG_SELECT"; +- }; +- G2B_P0_4 { +- gpio-hog; +- gpios = <4 0>; +- output-high; +- line-name = "PECI_MUX_SELECT"; +- }; +- G2B_P0_5 { +- gpio-hog; +- gpios = <5 0>; +- output-high; +- line-name = "I2C_MUX2_RESET_N"; +- }; +- G2B_P0_6 { +- gpio-hog; +- gpios = <6 0>; +- input; +- line-name = "FM_BMC_CPLD_PSU2_ON"; +- }; +- G2B_P0_7 { +- gpio-hog; +- gpios = <7 0>; +- output-high; +- line-name = "PSU2_ALERT_EN_N"; +- }; +- G2B_P1_0 { +- gpio-hog; +- gpios = <8 0>; +- output-high; +- line-name = "FM_CPU_BMC_INIT"; +- }; +- G2B_P1_1 { +- gpio-hog; +- gpios = <9 0>; +- output-high; +- line-name = "IRQ_BMC_PCH_SCI_LPC_N"; +- }; +- G2B_P1_2 { +- gpio-hog; +- gpios = <10 0>; +- output-low; +- line-name = "PMB_ALERT_EN_N"; +- }; +- G2B_P1_3 { +- gpio-hog; +- gpios = <11 0>; +- output-high; +- line-name = "FM_FAST_PROCHOT_EN_N"; +- }; +- G2B_P1_4 { +- gpio-hog; +- gpios = <12 0>; +- output-high; +- line-name = "BMC_NVDIMM_PRSNT_N"; +- }; +- G2B_P1_5 { +- gpio-hog; +- gpios = <13 0>; +- output-low; +- line-name = "FM_BACKUP_BIOS_SEL_H_BMC"; +- }; +- G2B_P1_6 { +- gpio-hog; +- gpios = <14 0>; +- output-high; +- line-name = "FM_PWRBRK_N"; +- }; +- }; +-}; +- +-&i2c13 { +- status = "okay"; +- +- tmp75@4a { +- compatible = "ti,tmp75"; +- reg = <0x4a>; +- status = "okay"; +- }; +- m24128_fru@51 { +- compatible = "atmel,24c128"; +- reg = <0x51>; +- pagesize = <64>; +- status = "okay"; +- }; +-}; +- +-&pwm_fan { +- pinctrl-names = "default"; +- pinctrl-0 = < &pwm0_pins &pwm1_pins +- &fanin0_pins &fanin1_pins +- &fanin2_pins &fanin3_pins +- &fanin4_pins &fanin5_pins +- &fanin6_pins &fanin7_pins +- &fanin8_pins &fanin9_pins +- &fanin10_pins &fanin11_pins>; +- status = "okay"; +- +- fan@0 { +- reg = <0x00>; +- fan-tach-ch = /bits/ 8 <0x00 0x01>; +- cooling-levels = <127 255>; +- }; +- fan@1 { +- reg = <0x01>; +- fan-tach-ch = /bits/ 8 <0x02 0x03>; +- cooling-levels = /bits/ 8 <127 255>; +- }; +- fan@2 { +- reg = <0x02>; +- fan-tach-ch = /bits/ 8 <0x04 0x05>; +- cooling-levels = /bits/ 8 <127 255>; +- }; +- fan@3 { +- reg = <0x03>; +- fan-tach-ch = /bits/ 8 <0x06 0x07>; +- cooling-levels = /bits/ 8 <127 255>; +- }; +- fan@4 { +- reg = <0x04>; +- fan-tach-ch = /bits/ 8 <0x08 0x09>; +- cooling-levels = /bits/ 8 <127 255>; +- }; +- fan@5 { +- reg = <0x05>; +- fan-tach-ch = /bits/ 8 <0x0A 0x0B>; +- cooling-levels = /bits/ 8 <127 255>; +- }; +- fan@6 { +- reg = <0x06>; +- fan-tach-ch = /bits/ 8 <0x0C 0x0D>; +- cooling-levels = /bits/ 8 <127 255>; +- }; +- fan@7 { +- reg = <0x07>; +- fan-tach-ch = /bits/ 8 <0x0E 0x0F>; +- cooling-levels = /bits/ 8 <127 255>; +- }; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&watchdog1 { +- status = "okay"; +-}; +- +-&rng { +- status = "okay"; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&serial1 { +- status = "okay"; +-}; +- +-&serial2 { +- status = "okay"; +-}; +- +-&serial3 { +- status = "okay"; +-}; +- +-&adc { +- #io-channel-cells = <1>; +- status = "okay"; +-}; +- +-&kcs1 { +- status = "okay"; +-}; +- +-&kcs2 { +- status = "okay"; +-}; +- +-&kcs3 { +- status = "okay"; +-}; +- +-&spi0 { +- cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&spi1 { +- status = "okay"; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = < +- /******* RunBMC inside Module pins *******/ +- &gpio0ol_pins +- &gpio1ol_pins +- &gpio2ol_pins +- &gpio3ol_pins +- &gpio8o_pins +- &gpio9ol_pins +- &gpio12ol_pins +- &gpio13ol_pins +- &gpio14ol_pins +- &gpio15ol_pins +- &gpio37o_pins +- &gpio38_pins +- &gpio39_pins +- &gpio94ol_pins +- &gpio108ol_pins +- &gpio109ol_pins +- &gpio111ol_pins +- &gpio112ol_pins +- &gpio113ol_pins +- &gpio208_pins +- &gpio209ol_pins +- &gpio210ol_pins +- &gpio211ol_pins +- &gpio212ol_pins +- &gpio213ol_pins +- &gpio214ol_pins +- &gpio215ol_pins +- &gpio216ol_pins +- &gpio217ol_pins +- /******* RunBMC outside Connector pins *******/ +- &gpio5_pins +- &gpio6_pins +- &gpio7_pins +- &gpio10_pins +- &gpio11_pins +- &gpio20_pins +- &gpio21_pins +- &gpio22o_pins +- &gpio23_pins +- &gpio24_pins +- &gpio25_pins +- &gpio30_pins +- &gpio31_pins +- &gpio40o_pins +- &gpio59_pins +- &gpio76_pins +- &gpio77_pins +- &gpio78o_pins +- &gpio79_pins +- &gpio82_pins +- &gpio83_pins +- &gpio84_pins +- &gpio85o_pins +- &gpio86ol_pins +- &gpio87_pins +- &gpio88_pins +- &gpio89_pins +- &gpio90_pins +- &gpio93_pins +- &gpio114o_pins +- &gpio115_pins +- &gpio120_pins +- &gpio121_pins +- &gpio122_pins +- &gpio123_pins +- &gpio124_pins +- &gpio125_pins +- &gpio126_pins +- &gpio127o_pins +- &gpio136_pins +- &gpio137_pins +- &gpio138_pins +- &gpio139_pins +- &gpio140_pins +- &gpio141_pins +- &gpio142_pins +- &gpio143_pins +- &gpio144_pins +- &gpio146_pins +- &gpio145_pins +- &gpio147_pins +- &gpio153o_pins +- &gpio155_pins +- &gpio160o_pins +- &gpio169o_pins +- &gpio188o_pins +- &gpio189_pins +- &gpio196_pins +- &gpio197_pins +- &gpio198o_pins +- &gpio199o_pins +- &gpio200_pins +- &gpio202_pins +- &gpio203o_pins +- &gpio224_pins +- &gpio225ol_pins +- &gpio226ol_pins +- &gpio227ol_pins +- &gpio228o_pins +- &gpio229o_pins +- &gpio230_pins +- &gpio231o_pins +- &ddc_pins +- &wdog1_pins +- &wdog2_pins +- >; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/nuvoton-npcm750.dtsi b/scripts/dtc/include-prefixes/arm/nuvoton-npcm750.dtsi +deleted file mode 100644 +index 13eee0fe5642..000000000000 +--- a/scripts/dtc/include-prefixes/arm/nuvoton-npcm750.dtsi ++++ /dev/null +@@ -1,62 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com +-// Copyright 2018 Google, Inc. +- +-#include "nuvoton-common-npcm7xx.dtsi" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&gic>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "nuvoton,npcm750-smp"; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- clocks = <&clk NPCM7XX_CLK_CPU>; +- clock-names = "clk_cpu"; +- reg = <0>; +- next-level-cache = <&l2>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- clocks = <&clk NPCM7XX_CLK_CPU>; +- clock-names = "clk_cpu"; +- reg = <1>; +- next-level-cache = <&l2>; +- }; +- }; +- +- soc { +- timer@3fe600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x3fe600 0x20>; +- interrupts = ; +- clocks = <&clk NPCM7XX_CLK_AHB>; +- }; +- }; +- +- ahb { +- gmac1: eth@f0804000 { +- device_type = "network"; +- compatible = "snps,dwmac"; +- reg = <0xf0804000 0x2000>; +- interrupts = ; +- interrupt-names = "macirq"; +- ethernet = <1>; +- clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>; +- clock-names = "stmmaceth", "clk_gmac"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rg2_pins +- &rg2mdio_pins>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts b/scripts/dtc/include-prefixes/arm/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts +deleted file mode 100644 +index 83f27fbf4e93..000000000000 +--- a/scripts/dtc/include-prefixes/arm/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts ++++ /dev/null +@@ -1,40 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +-// Copyright 2021 Jonathan Neuschäfer +- +-/dts-v1/; +- +-/* The last 16 MiB are dedicated to the GPU */ +-/memreserve/ 0x07000000 0x01000000; +- +-#include "nuvoton-wpcm450.dtsi" +- +-/ { +- model = "Supermicro X9SCi-LN4F BMC"; +- compatible = "supermicro,x9sci-ln4f-bmc", "nuvoton,wpcm450"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0x08000000>; /* 128 MiB */ +- }; +-}; +- +-&serial0 { +- /* +- * Debug serial port. TX is exposed on the right pad of unpopulated +- * resistor R1247, RX on the right pad of R1162. +- */ +- status = "okay"; +-}; +- +-&serial1 { +- /* "Serial over LAN" port. Connected to ttyS2 of the host system. */ +- status = "okay"; +-}; +- +-&watchdog0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/nuvoton-wpcm450.dtsi b/scripts/dtc/include-prefixes/arm/nuvoton-wpcm450.dtsi +deleted file mode 100644 +index d7cbeb187484..000000000000 +--- a/scripts/dtc/include-prefixes/arm/nuvoton-wpcm450.dtsi ++++ /dev/null +@@ -1,76 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +-// Copyright 2021 Jonathan Neuschäfer +- +-#include +- +-/ { +- compatible = "nuvoton,wpcm450"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,arm926ej-s"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- clk24m: clock-24mhz { +- /* 24 MHz dummy clock */ +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- #clock-cells = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&aic>; +- ranges; +- +- serial0: serial@b8000000 { +- compatible = "nuvoton,wpcm450-uart"; +- reg = <0xb8000000 0x20>; +- reg-shift = <2>; +- interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk24m>; +- status = "disabled"; +- }; +- +- serial1: serial@b8000100 { +- compatible = "nuvoton,wpcm450-uart"; +- reg = <0xb8000100 0x20>; +- reg-shift = <2>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk24m>; +- status = "disabled"; +- }; +- +- timer0: timer@b8001000 { +- compatible = "nuvoton,wpcm450-timer"; +- interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; +- reg = <0xb8001000 0x1c>; +- clocks = <&clk24m>; +- }; +- +- watchdog0: watchdog@b800101c { +- compatible = "nuvoton,wpcm450-wdt"; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; +- reg = <0xb800101c 0x4>; +- clocks = <&clk24m>; +- status = "disabled"; +- }; +- +- aic: interrupt-controller@b8002000 { +- compatible = "nuvoton,wpcm450-aic"; +- reg = <0xb8002000 0x1000>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap-gpmc-smsc911x.dtsi b/scripts/dtc/include-prefixes/arm/omap-gpmc-smsc911x.dtsi +deleted file mode 100644 +index ded7e8fec9eb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap-gpmc-smsc911x.dtsi ++++ /dev/null +@@ -1,55 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Common file for GPMC connected smsc911x on omaps +- * +- * Note that the board specifc DTS file needs to specify +- * ranges, pinctrl, reg, interrupt parent and interrupts. +- */ +- +-/ { +- vddvario: regulator-vddvario { +- compatible = "regulator-fixed"; +- regulator-name = "vddvario"; +- regulator-always-on; +- }; +- +- vdd33a: regulator-vdd33a { +- compatible = "regulator-fixed"; +- regulator-name = "vdd33a"; +- regulator-always-on; +- }; +-}; +- +-&gpmc { +- ethernet@gpmc { +- compatible = "smsc,lan9221", "smsc,lan9115"; +- bank-width = <2>; +- gpmc,device-width = <1>; +- gpmc,cycle2cycle-samecsen = <1>; +- gpmc,cycle2cycle-diffcsen = <1>; +- gpmc,cs-on-ns = <5>; +- gpmc,cs-rd-off-ns = <150>; +- gpmc,cs-wr-off-ns = <150>; +- gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <15>; +- gpmc,adv-wr-off-ns = <40>; +- gpmc,oe-on-ns = <45>; +- gpmc,oe-off-ns = <140>; +- gpmc,we-on-ns = <45>; +- gpmc,we-off-ns = <140>; +- gpmc,rd-cycle-ns = <155>; +- gpmc,wr-cycle-ns = <155>; +- gpmc,access-ns = <120>; +- gpmc,page-burst-access-ns = <20>; +- gpmc,bus-turnaround-ns = <75>; +- gpmc,cycle2cycle-delay-ns = <75>; +- gpmc,wait-monitoring-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-data-mux-bus-ns = <0>; +- gpmc,wr-access-ns = <0>; +- vddvario-supply = <&vddvario>; +- vdd33a-supply = <&vdd33a>; +- reg-io-width = <4>; +- smsc,save-mac-address; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap-gpmc-smsc9221.dtsi b/scripts/dtc/include-prefixes/arm/omap-gpmc-smsc9221.dtsi +deleted file mode 100644 +index e7534fe9c53c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap-gpmc-smsc9221.dtsi ++++ /dev/null +@@ -1,59 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Common file for GPMC connected smsc9221 on omaps +- * +- * Compared to smsc911x, smsc9221 (and others like smsc9217 +- * or smsc 9218) has faster timings, leading to higher +- * bandwidth. +- * +- * Note that the board specifc DTS file needs to specify +- * ranges, pinctrl, reg, interrupt parent and interrupts. +- */ +- +-/ { +- vddvario: regulator-vddvario { +- compatible = "regulator-fixed"; +- regulator-name = "vddvario"; +- regulator-always-on; +- }; +- +- vdd33a: regulator-vdd33a { +- compatible = "regulator-fixed"; +- regulator-name = "vdd33a"; +- regulator-always-on; +- }; +-}; +- +-&gpmc { +- ethernet@gpmc { +- compatible = "smsc,lan9221","smsc,lan9115"; +- bank-width = <2>; +- +- gpmc,mux-add-data = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <42>; +- gpmc,cs-wr-off-ns = <36>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <12>; +- gpmc,adv-wr-off-ns = <12>; +- gpmc,oe-on-ns = <0>; +- gpmc,oe-off-ns = <42>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <36>; +- gpmc,rd-cycle-ns = <60>; +- gpmc,wr-cycle-ns = <54>; +- gpmc,access-ns = <36>; +- gpmc,page-burst-access-ns = <0>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,wr-data-mux-bus-ns = <18>; +- gpmc,wr-access-ns = <42>; +- gpmc,cycle2cycle-samecsen; +- gpmc,cycle2cycle-diffcsen; +- +- vddvario-supply = <&vddvario>; +- vdd33a-supply = <&vdd33a>; +- reg-io-width = <4>; +- smsc,save-mac-address; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap-zoom-common.dtsi b/scripts/dtc/include-prefixes/arm/omap-zoom-common.dtsi +deleted file mode 100644 +index d4ad9e58b199..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap-zoom-common.dtsi ++++ /dev/null +@@ -1,92 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Common features on the Zoom debug board +- */ +- +-#include "omap-gpmc-smsc911x.dtsi" +- +-&gpmc { +- ranges = <3 0 0x10000000 0x1000000>, /* CS3: 16MB for UART */ +- <7 0 0x2c000000 0x01000000>; +- +- /* +- * Four port TL16CP754C serial port on GPMC, +- * they probably share the same GPIO IRQ +- * REVISIT: Add timing support from slls644g.pdf +- */ +- uart@3,0 { +- compatible = "ns16550a"; +- reg = <3 0 8>; /* CS3, offset 0, IO size 8 */ +- bank-width = <2>; +- reg-shift = <1>; +- reg-io-width = <1>; +- interrupt-parent = <&gpio4>; +- interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ +- clock-frequency = <1843200>; +- current-speed = <115200>; +- gpmc,mux-add-data = <0>; +- gpmc,device-width = <1>; +- gpmc,wait-pin = <1>; +- gpmc,cycle2cycle-samecsen = <1>; +- gpmc,cycle2cycle-diffcsen = <1>; +- gpmc,cs-on-ns = <5>; +- gpmc,cs-rd-off-ns = <155>; +- gpmc,cs-wr-off-ns = <155>; +- gpmc,adv-on-ns = <15>; +- gpmc,adv-rd-off-ns = <40>; +- gpmc,adv-wr-off-ns = <40>; +- gpmc,oe-on-ns = <45>; +- gpmc,oe-off-ns = <145>; +- gpmc,we-on-ns = <45>; +- gpmc,we-off-ns = <145>; +- gpmc,rd-cycle-ns = <155>; +- gpmc,wr-cycle-ns = <155>; +- gpmc,access-ns = <145>; +- gpmc,page-burst-access-ns = <20>; +- gpmc,bus-turnaround-ns = <20>; +- gpmc,cycle2cycle-delay-ns = <20>; +- gpmc,wait-monitoring-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-data-mux-bus-ns = <45>; +- gpmc,wr-access-ns = <145>; +- }; +- uart@3,1 { +- compatible = "ns16550a"; +- reg = <3 0x100 8>; /* CS3, offset 0x100, IO size 8 */ +- bank-width = <2>; +- reg-shift = <1>; +- reg-io-width = <1>; +- interrupt-parent = <&gpio4>; +- interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ +- clock-frequency = <1843200>; +- current-speed = <115200>; +- }; +- uart@3,2 { +- compatible = "ns16550a"; +- reg = <3 0x200 8>; /* CS3, offset 0x200, IO size 8 */ +- bank-width = <2>; +- reg-shift = <1>; +- reg-io-width = <1>; +- interrupt-parent = <&gpio4>; +- interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ +- clock-frequency = <1843200>; +- current-speed = <115200>; +- }; +- uart@3,3 { +- compatible = "ns16550a"; +- reg = <3 0x300 8>; /* CS3, offset 0x300, IO size 8 */ +- bank-width = <2>; +- reg-shift = <1>; +- reg-io-width = <1>; +- interrupt-parent = <&gpio4>; +- interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ +- clock-frequency = <1843200>; +- current-speed = <115200>; +- }; +- +- ethernet@gpmc { +- reg = <7 0 0xff>; +- interrupt-parent = <&gpio5>; +- interrupts = <30 IRQ_TYPE_LEVEL_LOW>; /* gpio158 */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap2.dtsi b/scripts/dtc/include-prefixes/arm/omap2.dtsi +deleted file mode 100644 +index 5750ca1233cc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap2.dtsi ++++ /dev/null +@@ -1,337 +0,0 @@ +-/* +- * Device Tree Source for OMAP2 SoC +- * +- * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; +- interrupt-parent = <&intc>; +- #address-cells = <1>; +- #size-cells = <1>; +- chosen { }; +- +- aliases { +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- }; +- +- cpus { +- #address-cells = <0>; +- #size-cells = <0>; +- +- cpu { +- compatible = "arm,arm1136jf-s"; +- device_type = "cpu"; +- }; +- }; +- +- pmu { +- compatible = "arm,arm1136-pmu"; +- interrupts = <3>; +- }; +- +- soc { +- compatible = "ti,omap-infra"; +- mpu { +- compatible = "ti,omap2-mpu"; +- ti,hwmods = "mpu"; +- }; +- }; +- +- ocp { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- ti,hwmods = "l3_main"; +- +- aes: aes@480a6000 { +- compatible = "ti,omap2-aes"; +- ti,hwmods = "aes"; +- reg = <0x480a6000 0x50>; +- dmas = <&sdma 9 &sdma 10>; +- dma-names = "tx", "rx"; +- }; +- +- hdq1w: 1w@480b2000 { +- compatible = "ti,omap2420-1w"; +- ti,hwmods = "hdq1w"; +- reg = <0x480b2000 0x1000>; +- interrupts = <58>; +- }; +- +- intc: interrupt-controller@1 { +- compatible = "ti,omap2-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x480FE000 0x1000>; +- }; +- +- target-module@48056000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x48056000 0x4>, +- <0x4805602c 0x4>, +- <0x48056028 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-midle = , +- , +- ; +- ti,syss-mask = <1>; +- clocks = <&core_l3_ck>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x48056000 0x1000>; +- +- sdma: dma-controller@0 { +- compatible = "ti,omap2420-sdma", "ti,omap-sdma"; +- reg = <0 0x1000>; +- interrupts = <12>, +- <13>, +- <14>, +- <15>; +- #dma-cells = <1>; +- dma-channels = <32>; +- dma-requests = <64>; +- }; +- }; +- +- i2c1: i2c@48070000 { +- compatible = "ti,omap2-i2c"; +- ti,hwmods = "i2c1"; +- reg = <0x48070000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <56>; +- }; +- +- i2c2: i2c@48072000 { +- compatible = "ti,omap2-i2c"; +- ti,hwmods = "i2c2"; +- reg = <0x48072000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <57>; +- }; +- +- mcspi1: spi@48098000 { +- compatible = "ti,omap2-mcspi"; +- ti,hwmods = "mcspi1"; +- reg = <0x48098000 0x100>; +- interrupts = <65>; +- dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38 +- &sdma 39 &sdma 40 &sdma 41 &sdma 42>; +- dma-names = "tx0", "rx0", "tx1", "rx1", +- "tx2", "rx2", "tx3", "rx3"; +- }; +- +- mcspi2: spi@4809a000 { +- compatible = "ti,omap2-mcspi"; +- ti,hwmods = "mcspi2"; +- reg = <0x4809a000 0x100>; +- interrupts = <66>; +- dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>; +- dma-names = "tx0", "rx0", "tx1", "rx1"; +- }; +- +- rng: rng@480a0000 { +- compatible = "ti,omap2-rng"; +- ti,hwmods = "rng"; +- reg = <0x480a0000 0x50>; +- interrupts = <52>; +- }; +- +- sham: sham@480a4000 { +- compatible = "ti,omap2-sham"; +- ti,hwmods = "sham"; +- reg = <0x480a4000 0x64>; +- interrupts = <51>; +- dmas = <&sdma 13>; +- dma-names = "rx"; +- }; +- +- uart1: serial@4806a000 { +- compatible = "ti,omap2-uart"; +- ti,hwmods = "uart1"; +- reg = <0x4806a000 0x2000>; +- interrupts = <72>; +- dmas = <&sdma 49 &sdma 50>; +- dma-names = "tx", "rx"; +- clock-frequency = <48000000>; +- }; +- +- uart2: serial@4806c000 { +- compatible = "ti,omap2-uart"; +- ti,hwmods = "uart2"; +- reg = <0x4806c000 0x400>; +- interrupts = <73>; +- dmas = <&sdma 51 &sdma 52>; +- dma-names = "tx", "rx"; +- clock-frequency = <48000000>; +- }; +- +- uart3: serial@4806e000 { +- compatible = "ti,omap2-uart"; +- ti,hwmods = "uart3"; +- reg = <0x4806e000 0x400>; +- interrupts = <74>; +- dmas = <&sdma 53 &sdma 54>; +- dma-names = "tx", "rx"; +- clock-frequency = <48000000>; +- }; +- +- timer2_target: target-module@4802a000 { +- compatible = "ti,sysc-omap2-timer", "ti,sysc"; +- reg = <0x4802a000 0x4>, +- <0x4802a010 0x4>, +- <0x4802a014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- clocks = <&gpt2_fck>, <&gpt2_ick>; +- clock-names = "fck", "ick"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4802a000 0x1000>; +- +- timer2: timer@0 { +- compatible = "ti,omap2420-timer"; +- reg = <0 0x400>; +- interrupts = <38>; +- }; +- }; +- +- timer3: timer@48078000 { +- compatible = "ti,omap2420-timer"; +- reg = <0x48078000 0x400>; +- interrupts = <39>; +- ti,hwmods = "timer3"; +- }; +- +- timer4: timer@4807a000 { +- compatible = "ti,omap2420-timer"; +- reg = <0x4807a000 0x400>; +- interrupts = <40>; +- ti,hwmods = "timer4"; +- }; +- +- timer5: timer@4807c000 { +- compatible = "ti,omap2420-timer"; +- reg = <0x4807c000 0x400>; +- interrupts = <41>; +- ti,hwmods = "timer5"; +- ti,timer-dsp; +- }; +- +- timer6: timer@4807e000 { +- compatible = "ti,omap2420-timer"; +- reg = <0x4807e000 0x400>; +- interrupts = <42>; +- ti,hwmods = "timer6"; +- ti,timer-dsp; +- }; +- +- timer7: timer@48080000 { +- compatible = "ti,omap2420-timer"; +- reg = <0x48080000 0x400>; +- interrupts = <43>; +- ti,hwmods = "timer7"; +- ti,timer-dsp; +- }; +- +- timer8: timer@48082000 { +- compatible = "ti,omap2420-timer"; +- reg = <0x48082000 0x400>; +- interrupts = <44>; +- ti,hwmods = "timer8"; +- ti,timer-dsp; +- }; +- +- timer9: timer@48084000 { +- compatible = "ti,omap2420-timer"; +- reg = <0x48084000 0x400>; +- interrupts = <45>; +- ti,hwmods = "timer9"; +- ti,timer-pwm; +- }; +- +- timer10: timer@48086000 { +- compatible = "ti,omap2420-timer"; +- reg = <0x48086000 0x400>; +- interrupts = <46>; +- ti,hwmods = "timer10"; +- ti,timer-pwm; +- }; +- +- timer11: timer@48088000 { +- compatible = "ti,omap2420-timer"; +- reg = <0x48088000 0x400>; +- interrupts = <47>; +- ti,hwmods = "timer11"; +- ti,timer-pwm; +- }; +- +- timer12: timer@4808a000 { +- compatible = "ti,omap2420-timer"; +- reg = <0x4808a000 0x400>; +- interrupts = <48>; +- ti,hwmods = "timer12"; +- ti,timer-pwm; +- }; +- +- dss: dss@48050000 { +- compatible = "ti,omap2-dss"; +- reg = <0x48050000 0x400>; +- status = "disabled"; +- ti,hwmods = "dss_core"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- dispc@48050400 { +- compatible = "ti,omap2-dispc"; +- reg = <0x48050400 0x400>; +- interrupts = <25>; +- ti,hwmods = "dss_dispc"; +- }; +- +- rfbi: encoder@48050800 { +- compatible = "ti,omap2-rfbi"; +- reg = <0x48050800 0x400>; +- status = "disabled"; +- ti,hwmods = "dss_rfbi"; +- }; +- +- venc: encoder@48050c00 { +- compatible = "ti,omap2-venc"; +- reg = <0x48050c00 0x400>; +- status = "disabled"; +- ti,hwmods = "dss_venc"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap2420-clocks.dtsi b/scripts/dtc/include-prefixes/arm/omap2420-clocks.dtsi +deleted file mode 100644 +index 00a7a199a91c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap2420-clocks.dtsi ++++ /dev/null +@@ -1,267 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for OMAP2420 clock data +- * +- * Copyright (C) 2014 Texas Instruments, Inc. +- */ +- +-&prcm_clocks { +- sys_clkout2_src_gate: sys_clkout2_src_gate@70 { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&core_ck>; +- ti,bit-shift = <15>; +- reg = <0x0070>; +- }; +- +- sys_clkout2_src_mux: sys_clkout2_src_mux@70 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>; +- ti,bit-shift = <8>; +- reg = <0x0070>; +- }; +- +- sys_clkout2_src: sys_clkout2_src { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>; +- }; +- +- sys_clkout2: sys_clkout2@70 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&sys_clkout2_src>; +- ti,bit-shift = <11>; +- ti,max-div = <64>; +- reg = <0x0070>; +- ti,index-power-of-two; +- }; +- +- dsp_gate_ick: dsp_gate_ick@810 { +- #clock-cells = <0>; +- compatible = "ti,composite-interface-clock"; +- clocks = <&dsp_fck>; +- ti,bit-shift = <1>; +- reg = <0x0810>; +- }; +- +- dsp_div_ick: dsp_div_ick@840 { +- #clock-cells = <0>; +- compatible = "ti,composite-divider-clock"; +- clocks = <&dsp_fck>; +- ti,bit-shift = <5>; +- ti,max-div = <3>; +- reg = <0x0840>; +- ti,index-starts-at-one; +- }; +- +- dsp_ick: dsp_ick { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&dsp_gate_ick>, <&dsp_div_ick>; +- }; +- +- iva1_gate_ifck: iva1_gate_ifck@800 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&core_ck>; +- ti,bit-shift = <10>; +- reg = <0x0800>; +- }; +- +- iva1_div_ifck: iva1_div_ifck@840 { +- #clock-cells = <0>; +- compatible = "ti,composite-divider-clock"; +- clocks = <&core_ck>; +- ti,bit-shift = <8>; +- reg = <0x0840>; +- ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>; +- }; +- +- iva1_ifck: iva1_ifck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>; +- }; +- +- iva1_ifck_div: iva1_ifck_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&iva1_ifck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- iva1_mpu_int_ifck: iva1_mpu_int_ifck@800 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&iva1_ifck_div>; +- ti,bit-shift = <8>; +- reg = <0x0800>; +- }; +- +- wdt3_ick: wdt3_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <28>; +- reg = <0x0210>; +- }; +- +- wdt3_fck: wdt3_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_32k_ck>; +- ti,bit-shift = <28>; +- reg = <0x0200>; +- }; +- +- mmc_ick: mmc_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <26>; +- reg = <0x0210>; +- }; +- +- mmc_fck: mmc_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_96m_ck>; +- ti,bit-shift = <26>; +- reg = <0x0200>; +- }; +- +- eac_ick: eac_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <24>; +- reg = <0x0210>; +- }; +- +- eac_fck: eac_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_96m_ck>; +- ti,bit-shift = <24>; +- reg = <0x0200>; +- }; +- +- i2c1_fck: i2c1_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_12m_ck>; +- ti,bit-shift = <19>; +- reg = <0x0200>; +- }; +- +- i2c2_fck: i2c2_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_12m_ck>; +- ti,bit-shift = <20>; +- reg = <0x0200>; +- }; +- +- vlynq_ick: vlynq_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l3_ck>; +- ti,bit-shift = <3>; +- reg = <0x0210>; +- }; +- +- vlynq_gate_fck: vlynq_gate_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&core_ck>; +- ti,bit-shift = <3>; +- reg = <0x0200>; +- }; +- +- core_d18_ck: core_d18_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&core_ck>; +- clock-mult = <1>; +- clock-div = <18>; +- }; +- +- vlynq_mux_fck: vlynq_mux_fck@240 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>; +- ti,bit-shift = <15>; +- reg = <0x0240>; +- }; +- +- vlynq_fck: vlynq_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>; +- }; +-}; +- +-&prcm_clockdomains { +- gfx_clkdm: gfx_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&gfx_ick>; +- }; +- +- core_l3_clkdm: core_l3_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>; +- }; +- +- wkup_clkdm: wkup_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>, +- <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>, +- <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>; +- }; +- +- iva1_clkdm: iva1_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&iva1_mpu_int_ifck>; +- }; +- +- dss_clkdm: dss_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&dss_ick>, <&dss_54m_fck>; +- }; +- +- core_l4_clkdm: core_l4_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>, +- <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>, +- <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>, +- <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>, +- <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>, +- <&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, +- <&uart3_ick>, <&uart3_fck>, <&cam_ick>, +- <&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>, +- <&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>, +- <&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>, +- <&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>, +- <&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>, +- <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>, +- <&pka_ick>; +- }; +-}; +- +-&func_96m_ck { +- compatible = "fixed-factor-clock"; +- clocks = <&apll96_ck>; +- clock-mult = <1>; +- clock-div = <1>; +-}; +- +-&dsp_div_fck { +- ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>; +-}; +- +-&ssi_ssr_sst_div_fck { +- ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap2420-h4.dts b/scripts/dtc/include-prefixes/arm/omap2420-h4.dts +deleted file mode 100644 +index af964f139abf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap2420-h4.dts ++++ /dev/null +@@ -1,63 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "omap2420.dtsi" +- +-/ { +- model = "TI OMAP2420 H4 board"; +- compatible = "ti,omap2420-h4", "ti,omap2420", "ti,omap2"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x4000000>; /* 64 MB */ +- }; +-}; +- +-&gpmc { +- ranges = <0 0 0x08000000 0x04000000>; +- +- nor@0,0 { +- compatible = "cfi-flash"; +- linux,mtd-name= "intel,ge28f256l18b85"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0 0 0x04000000>; +- bank-width = <2>; +- +- gpmc,mux-add-data = <2>; +- gpmc,cs-on-ns = <10>; +- gpmc,cs-rd-off-ns = <160>; +- gpmc,cs-wr-off-ns = <160>; +- gpmc,adv-on-ns = <20>; +- gpmc,adv-rd-off-ns = <50>; +- gpmc,adv-wr-off-ns = <50>; +- gpmc,oe-on-ns = <60>; +- gpmc,oe-off-ns = <120>; +- gpmc,we-on-ns = <60>; +- gpmc,we-off-ns = <120>; +- gpmc,rd-cycle-ns = <170>; +- gpmc,wr-cycle-ns = <170>; +- gpmc,access-ns = <150>; +- gpmc,page-burst-access-ns = <10>; +- +- partition@0 { +- label = "bootloader"; +- reg = <0 0x20000>; +- }; +- partition@20000 { +- label = "params"; +- reg = <0x20000 0x20000>; +- }; +- partition@40000 { +- label = "kernel"; +- reg = <0x40000 0x200000>; +- }; +- partition@240000 { +- label = "file-system"; +- reg = <0x240000 0x3dc0000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap2420-n800.dts b/scripts/dtc/include-prefixes/arm/omap2420-n800.dts +deleted file mode 100644 +index f06d767e818b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap2420-n800.dts ++++ /dev/null +@@ -1,9 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "omap2420-n8x0-common.dtsi" +- +-/ { +- model = "Nokia N800"; +- compatible = "nokia,n800", "nokia,n8x0", "ti,omap2420", "ti,omap2"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap2420-n810-wimax.dts b/scripts/dtc/include-prefixes/arm/omap2420-n810-wimax.dts +deleted file mode 100644 +index ac9acbd609b6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap2420-n810-wimax.dts ++++ /dev/null +@@ -1,9 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "omap2420-n8x0-common.dtsi" +- +-/ { +- model = "Nokia N810 WiMax"; +- compatible = "nokia,n810-wimax", "nokia,n8x0", "ti,omap2420", "ti,omap2"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap2420-n810.dts b/scripts/dtc/include-prefixes/arm/omap2420-n810.dts +deleted file mode 100644 +index 09c1dbc0bb69..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap2420-n810.dts ++++ /dev/null +@@ -1,75 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "omap2420-n8x0-common.dtsi" +- +-/ { +- model = "Nokia N810"; +- compatible = "nokia,n810", "nokia,n8x0", "ti,omap2420", "ti,omap2"; +- +- vio_ape: vio_ape { +- compatible = "regulator-fixed"; +- regulator-name = "vio_ape"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- v28_aic: v28_aic { +- compatible = "regulator-fixed"; +- regulator-name = "v28_aic"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +-}; +- +-&omap2420_pmx { +- mcbsp2_pins: mcbsp2_pins { +- pinctrl-single,pins = < +- OMAP2420_CORE_IOPAD(0x0124, PIN_INPUT | MUX_MODE1) /* eac_ac_sclk.mcbsp2_clkx */ +- OMAP2420_CORE_IOPAD(0x0125, PIN_INPUT | MUX_MODE1) /* eac_ac_fs.mcbsp2_fsx */ +- OMAP2420_CORE_IOPAD(0x0126, PIN_INPUT | MUX_MODE1) /* eac_ac_din.mcbsp2_dr */ +- OMAP2420_CORE_IOPAD(0x0127, PIN_OUTPUT | MUX_MODE1) /* eac_ac_dout.mcbsp2_dx */ +- >; +- }; +- +- aic33_pins: aic33_pins { +- pinctrl-single,pins = < +- OMAP2420_CORE_IOPAD(0x0129, PIN_OUTPUT | MUX_MODE3) /* eac_ac_rst.gpio118 */ +- OMAP2420_CORE_IOPAD(0x00e8, PIN_OUTPUT | MUX_MODE2) /* vlynq_tx1.sys_clkout2 */ +- >; +- }; +-}; +- +-&i2c2 { +- aic33@18 { +- compatible = "ti,tlv320aic33"; +- reg = <0x18>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&aic33_pins>; +- +- reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; /* gpio118 */ +- +- ai3x-gpio-func = < +- 10 /* AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK */ +- 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */ +- >; +- ai3x-micbias-vg = <1>; /* 2V */ +- +- AVDD-supply = <&v28_aic>; +- DRVDD-supply = <&v28_aic>; +- IOVDD-supply = <&vio_ape>; +- DVDD-supply = <&vio_ape>; +- +- assigned-clocks = <&sys_clkout2_src>, <&sys_clkout2>; +- assigned-clock-parents = <&func_96m_ck>; +- assigned-clock-rates = <0>, <12000000>; +- }; +-}; +- +-&mcbsp2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp2_pins>; +- +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap2420-n8x0-common.dtsi b/scripts/dtc/include-prefixes/arm/omap2420-n8x0-common.dtsi +deleted file mode 100644 +index 63b0b4921e4e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap2420-n8x0-common.dtsi ++++ /dev/null +@@ -1,111 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "omap2420.dtsi" +- +-/ { +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x8000000>; /* 128 MB */ +- }; +- +- chosen { +- stdout-path = &uart3; +- }; +- +- ocp { +- i2c0 { +- compatible = "i2c-cbus-gpio"; +- gpios = <&gpio3 2 GPIO_ACTIVE_HIGH /* gpio66 clk */ +- &gpio3 1 GPIO_ACTIVE_HIGH /* gpio65 dat */ +- &gpio3 0 GPIO_ACTIVE_HIGH /* gpio64 sel */ +- >; +- #address-cells = <1>; +- #size-cells = <0>; +- retu: retu@1 { +- compatible = "nokia,retu"; +- interrupt-parent = <&gpio4>; +- interrupts = <12 IRQ_TYPE_EDGE_RISING>; +- reg = <0x1>; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- +- pmic@72 { +- compatible = "menelaus"; +- reg = <0x72>; +- interrupts = <7 IRQ_TYPE_EDGE_RISING>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +-}; +- +-&gpmc { +- ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ +- +- /* gpio-irq for dma: 26 */ +- +- onenand@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ti,omap2-onenand"; +- reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ +- +- gpmc,sync-read; +- gpmc,burst-length = <16>; +- gpmc,burst-read; +- gpmc,burst-wrap; +- gpmc,device-width = <2>; +- gpmc,mux-add-data = <2>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <127>; +- gpmc,cs-wr-off-ns = <109>; +- gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <18>; +- gpmc,adv-wr-off-ns = <18>; +- gpmc,oe-on-ns = <27>; +- gpmc,oe-off-ns = <127>; +- gpmc,we-on-ns = <27>; +- gpmc,we-off-ns = <72>; +- gpmc,rd-cycle-ns = <145>; +- gpmc,wr-cycle-ns = <136>; +- gpmc,access-ns = <118>; +- gpmc,page-burst-access-ns = <27>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,wait-monitoring-ns = <0>; +- gpmc,clk-activation-ns = <9>; +- gpmc,sync-clk-ps = <27000>; +- +- /* MTD partition table corresponding to old board-n8x0 file. */ +- partition@0 { +- label = "bootloader"; +- reg = <0x00000000 0x00020000>; +- read-only; +- }; +- partition@1 { +- label = "config"; +- reg = <0x00020000 0x00060000>; +- }; +- partition@2 { +- label = "kernel"; +- reg = <0x00080000 0x00200000>; +- }; +- partition@3 { +- label = "initfs"; +- reg = <0x00280000 0x00400000>; +- }; +- partition@4 { +- label = "rootfs"; +- reg = <0x00680000 0x0f980000>; +- }; +- partition@5 { +- label = "omap2-onenand"; +- reg = <0x00000000 0x10000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap2420.dtsi b/scripts/dtc/include-prefixes/arm/omap2420.dtsi +deleted file mode 100644 +index bb529a2a295d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap2420.dtsi ++++ /dev/null +@@ -1,265 +0,0 @@ +-/* +- * Device Tree Source for OMAP2420 SoC +- * +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-#include "omap2.dtsi" +- +-/ { +- compatible = "ti,omap2420", "ti,omap2"; +- +- ocp { +- l4: l4@48000000 { +- compatible = "ti,omap2-l4", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x48000000 0x100000>; +- +- prcm: prcm@8000 { +- compatible = "ti,omap2-prcm"; +- reg = <0x8000 0x1000>; +- +- prcm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- prcm_clockdomains: clockdomains { +- }; +- }; +- +- scm: scm@0 { +- compatible = "ti,omap2-scm", "simple-bus"; +- reg = <0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- #pinctrl-cells = <1>; +- ranges = <0 0x0 0x1000>; +- +- omap2420_pmx: pinmux@30 { +- compatible = "ti,omap2420-padconf", +- "pinctrl-single"; +- reg = <0x30 0x0113>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <8>; +- pinctrl-single,function-mask = <0x3f>; +- }; +- +- scm_conf: scm_conf@270 { +- compatible = "syscon"; +- reg = <0x270 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- scm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- scm_clockdomains: clockdomains { +- }; +- }; +- +- target-module@4000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4000 0x4>, +- <0x4004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- ; +- clocks = <&func_32k_ck>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4000 0x1000>; +- +- counter32k: counter@0 { +- compatible = "ti,omap-counter32k"; +- reg = <0 0x20>; +- }; +- }; +- }; +- +- gpio1: gpio@48018000 { +- compatible = "ti,omap2-gpio"; +- reg = <0x48018000 0x200>; +- interrupts = <29>; +- ti,hwmods = "gpio1"; +- ti,gpio-always-on; +- #gpio-cells = <2>; +- gpio-controller; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gpio2: gpio@4801a000 { +- compatible = "ti,omap2-gpio"; +- reg = <0x4801a000 0x200>; +- interrupts = <30>; +- ti,hwmods = "gpio2"; +- ti,gpio-always-on; +- #gpio-cells = <2>; +- gpio-controller; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gpio3: gpio@4801c000 { +- compatible = "ti,omap2-gpio"; +- reg = <0x4801c000 0x200>; +- interrupts = <31>; +- ti,hwmods = "gpio3"; +- ti,gpio-always-on; +- #gpio-cells = <2>; +- gpio-controller; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gpio4: gpio@4801e000 { +- compatible = "ti,omap2-gpio"; +- reg = <0x4801e000 0x200>; +- interrupts = <32>; +- ti,hwmods = "gpio4"; +- ti,gpio-always-on; +- #gpio-cells = <2>; +- gpio-controller; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gpmc: gpmc@6800a000 { +- compatible = "ti,omap2420-gpmc"; +- reg = <0x6800a000 0x1000>; +- #address-cells = <2>; +- #size-cells = <1>; +- interrupts = <20>; +- gpmc,num-cs = <8>; +- gpmc,num-waitpins = <4>; +- ti,hwmods = "gpmc"; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- mcbsp1: mcbsp@48074000 { +- compatible = "ti,omap2420-mcbsp"; +- reg = <0x48074000 0xff>; +- reg-names = "mpu"; +- interrupts = <59>, /* TX interrupt */ +- <60>; /* RX interrupt */ +- interrupt-names = "tx", "rx"; +- ti,hwmods = "mcbsp1"; +- dmas = <&sdma 31>, +- <&sdma 32>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- mcbsp2: mcbsp@48076000 { +- compatible = "ti,omap2420-mcbsp"; +- reg = <0x48076000 0xff>; +- reg-names = "mpu"; +- interrupts = <62>, /* TX interrupt */ +- <63>; /* RX interrupt */ +- interrupt-names = "tx", "rx"; +- ti,hwmods = "mcbsp2"; +- dmas = <&sdma 33>, +- <&sdma 34>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- msdi1: mmc@4809c000 { +- compatible = "ti,omap2420-mmc"; +- ti,hwmods = "msdi1"; +- reg = <0x4809c000 0x80>; +- interrupts = <83>; +- dmas = <&sdma 61 &sdma 62>; +- dma-names = "tx", "rx"; +- }; +- +- mailbox: mailbox@48094000 { +- compatible = "ti,omap2-mailbox"; +- reg = <0x48094000 0x200>; +- interrupts = <26>, <34>; +- ti,hwmods = "mailbox"; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <6>; +- mbox_dsp: mbox-dsp { +- ti,mbox-tx = <0 0 0>; +- ti,mbox-rx = <1 0 0>; +- }; +- mbox_iva: mbox-iva { +- ti,mbox-tx = <2 1 3>; +- ti,mbox-rx = <3 1 3>; +- }; +- }; +- +- timer1_target: target-module@48028000 { +- compatible = "ti,sysc-omap2-timer", "ti,sysc"; +- reg = <0x48028000 0x4>, +- <0x48028010 0x4>, +- <0x48028014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- clocks = <&gpt1_fck>, <&gpt1_ick>; +- clock-names = "fck", "ick"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x48028000 0x1000>; +- +- timer1: timer@0 { +- compatible = "ti,omap2420-timer"; +- reg = <0 0x400>; +- interrupts = <37>; +- ti,timer-alwon; +- }; +- }; +- +- wd_timer2: wdt@48022000 { +- compatible = "ti,omap2-wdt"; +- ti,hwmods = "wd_timer2"; +- reg = <0x48022000 0x80>; +- }; +- }; +-}; +- +-&i2c1 { +- compatible = "ti,omap2420-i2c"; +-}; +- +-&i2c2 { +- compatible = "ti,omap2420-i2c"; +-}; +- +-#include "omap24xx-clocks.dtsi" +-#include "omap2420-clocks.dtsi" +- +-/* Preferred always-on timer for clockevent */ +-&timer1_target { +- ti,no-reset-on-init; +- ti,no-idle; +- timer@0 { +- assigned-clocks = <&gpt1_fck>; +- assigned-clock-parents = <&func_32k_ck>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap2430-clocks.dtsi b/scripts/dtc/include-prefixes/arm/omap2430-clocks.dtsi +deleted file mode 100644 +index 4e5ab5189476..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap2430-clocks.dtsi ++++ /dev/null +@@ -1,341 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for OMAP2430 clock data +- * +- * Copyright (C) 2014 Texas Instruments, Inc. +- */ +- +-&scm_clocks { +- mcbsp3_mux_fck: mcbsp3_mux_fck@78 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&func_96m_ck>, <&mcbsp_clks>; +- reg = <0x78>; +- }; +- +- mcbsp3_fck: mcbsp3_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; +- }; +- +- mcbsp4_mux_fck: mcbsp4_mux_fck@78 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&func_96m_ck>, <&mcbsp_clks>; +- ti,bit-shift = <2>; +- reg = <0x78>; +- }; +- +- mcbsp4_fck: mcbsp4_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; +- }; +- +- mcbsp5_mux_fck: mcbsp5_mux_fck@78 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&func_96m_ck>, <&mcbsp_clks>; +- ti,bit-shift = <4>; +- reg = <0x78>; +- }; +- +- mcbsp5_fck: mcbsp5_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; +- }; +-}; +- +-&prcm_clocks { +- iva2_1_gate_ick: iva2_1_gate_ick@800 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&dsp_fck>; +- ti,bit-shift = <0>; +- reg = <0x0800>; +- }; +- +- iva2_1_div_ick: iva2_1_div_ick@840 { +- #clock-cells = <0>; +- compatible = "ti,composite-divider-clock"; +- clocks = <&dsp_fck>; +- ti,bit-shift = <5>; +- ti,max-div = <3>; +- reg = <0x0840>; +- ti,index-starts-at-one; +- }; +- +- iva2_1_ick: iva2_1_ick { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>; +- }; +- +- mdm_gate_ick: mdm_gate_ick@c10 { +- #clock-cells = <0>; +- compatible = "ti,composite-interface-clock"; +- clocks = <&core_ck>; +- ti,bit-shift = <0>; +- reg = <0x0c10>; +- }; +- +- mdm_div_ick: mdm_div_ick@c40 { +- #clock-cells = <0>; +- compatible = "ti,composite-divider-clock"; +- clocks = <&core_ck>; +- reg = <0x0c40>; +- ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>; +- }; +- +- mdm_ick: mdm_ick { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&mdm_gate_ick>, <&mdm_div_ick>; +- }; +- +- mdm_osc_ck: mdm_osc_ck@c00 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&osc_ck>; +- ti,bit-shift = <1>; +- reg = <0x0c00>; +- }; +- +- mcbsp3_ick: mcbsp3_ick@214 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <3>; +- reg = <0x0214>; +- }; +- +- mcbsp3_gate_fck: mcbsp3_gate_fck@204 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&mcbsp_clks>; +- ti,bit-shift = <3>; +- reg = <0x0204>; +- }; +- +- mcbsp4_ick: mcbsp4_ick@214 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <4>; +- reg = <0x0214>; +- }; +- +- mcbsp4_gate_fck: mcbsp4_gate_fck@204 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&mcbsp_clks>; +- ti,bit-shift = <4>; +- reg = <0x0204>; +- }; +- +- mcbsp5_ick: mcbsp5_ick@214 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <5>; +- reg = <0x0214>; +- }; +- +- mcbsp5_gate_fck: mcbsp5_gate_fck@204 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&mcbsp_clks>; +- ti,bit-shift = <5>; +- reg = <0x0204>; +- }; +- +- mcspi3_ick: mcspi3_ick@214 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <9>; +- reg = <0x0214>; +- }; +- +- mcspi3_fck: mcspi3_fck@204 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_48m_ck>; +- ti,bit-shift = <9>; +- reg = <0x0204>; +- }; +- +- icr_ick: icr_ick@410 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <6>; +- reg = <0x0410>; +- }; +- +- i2chs1_fck: i2chs1_fck@204 { +- #clock-cells = <0>; +- compatible = "ti,omap2430-interface-clock"; +- clocks = <&func_96m_ck>; +- ti,bit-shift = <19>; +- reg = <0x0204>; +- }; +- +- i2chs2_fck: i2chs2_fck@204 { +- #clock-cells = <0>; +- compatible = "ti,omap2430-interface-clock"; +- clocks = <&func_96m_ck>; +- ti,bit-shift = <20>; +- reg = <0x0204>; +- }; +- +- usbhs_ick: usbhs_ick@214 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l3_ck>; +- ti,bit-shift = <6>; +- reg = <0x0214>; +- }; +- +- mmchs1_ick: mmchs1_ick@214 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <7>; +- reg = <0x0214>; +- }; +- +- mmchs1_fck: mmchs1_fck@204 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_96m_ck>; +- ti,bit-shift = <7>; +- reg = <0x0204>; +- }; +- +- mmchs2_ick: mmchs2_ick@214 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <8>; +- reg = <0x0214>; +- }; +- +- mmchs2_fck: mmchs2_fck@204 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_96m_ck>; +- ti,bit-shift = <8>; +- reg = <0x0204>; +- }; +- +- gpio5_ick: gpio5_ick@214 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <10>; +- reg = <0x0214>; +- }; +- +- gpio5_fck: gpio5_fck@204 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_32k_ck>; +- ti,bit-shift = <10>; +- reg = <0x0204>; +- }; +- +- mdm_intc_ick: mdm_intc_ick@214 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <11>; +- reg = <0x0214>; +- }; +- +- mmchsdb1_fck: mmchsdb1_fck@204 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_32k_ck>; +- ti,bit-shift = <16>; +- reg = <0x0204>; +- }; +- +- mmchsdb2_fck: mmchsdb2_fck@204 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_32k_ck>; +- ti,bit-shift = <17>; +- reg = <0x0204>; +- }; +-}; +- +-&prcm_clockdomains { +- gfx_clkdm: gfx_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&gfx_ick>; +- }; +- +- core_l3_clkdm: core_l3_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>; +- }; +- +- wkup_clkdm: wkup_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>, +- <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>, +- <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>, +- <&icr_ick>; +- }; +- +- dss_clkdm: dss_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&dss_ick>, <&dss_54m_fck>; +- }; +- +- core_l4_clkdm: core_l4_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>, +- <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>, +- <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>, +- <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, +- <&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>, +- <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>, +- <&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>, +- <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>, +- <&uart3_fck>, <&cam_ick>, <&mailboxes_ick>, +- <&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>, +- <&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>, +- <&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>, +- <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>, +- <&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>, +- <&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>, +- <&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>, +- <&mmchsdb2_fck>; +- }; +- +- mdm_clkdm: mdm_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&mdm_osc_ck>; +- }; +-}; +- +-&func_96m_ck { +- compatible = "ti,mux-clock"; +- clocks = <&apll96_ck>, <&alt_ck>; +- ti,bit-shift = <4>; +- reg = <0x0540>; +-}; +- +-&dsp_div_fck { +- ti,max-div = <4>; +- ti,index-starts-at-one; +-}; +- +-&ssi_ssr_sst_div_fck { +- ti,max-div = <5>; +- ti,index-starts-at-one; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap2430-sdp.dts b/scripts/dtc/include-prefixes/arm/omap2430-sdp.dts +deleted file mode 100644 +index 7d27e907533f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap2430-sdp.dts ++++ /dev/null +@@ -1,70 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "omap2430.dtsi" +- +-/ { +- model = "TI OMAP2430 SDP"; +- compatible = "ti,omap2430-sdp", "ti,omap2430", "ti,omap2"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x8000000>; /* 128 MB */ +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- }; +-}; +- +-#include "twl4030.dtsi" +- +-&mmc1 { +- vmmc-supply = <&vmmc1>; +- bus-width = <4>; +-}; +- +-&gpmc { +- ranges = <5 0 0x08000000 0x01000000>; +- ethernet@gpmc { +- compatible = "smsc,lan91c94"; +- interrupt-parent = <&gpio5>; +- interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */ +- reg = <5 0x300 0xf>; +- bank-width = <2>; +- gpmc,sync-clk-ps = <0>; +- gpmc,mux-add-data = <2>; +- gpmc,device-width = <1>; +- gpmc,cycle2cycle-samecsen = <1>; +- gpmc,cycle2cycle-diffcsen = <1>; +- gpmc,cs-on-ns = <6>; +- gpmc,cs-rd-off-ns = <187>; +- gpmc,cs-wr-off-ns = <187>; +- gpmc,adv-on-ns = <18>; +- gpmc,adv-rd-off-ns = <48>; +- gpmc,adv-wr-off-ns = <48>; +- gpmc,oe-on-ns = <60>; +- gpmc,oe-off-ns = <169>; +- gpmc,we-on-ns = <66>; +- gpmc,we-off-ns = <169>; +- gpmc,rd-cycle-ns = <187>; +- gpmc,wr-cycle-ns = <187>; +- gpmc,access-ns = <187>; +- gpmc,page-burst-access-ns = <24>; +- gpmc,bus-turnaround-ns = <24>; +- gpmc,cycle2cycle-delay-ns = <24>; +- gpmc,wait-monitoring-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-data-mux-bus-ns = <0>; +- gpmc,wr-access-ns = <0>; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap2430.dtsi b/scripts/dtc/include-prefixes/arm/omap2430.dtsi +deleted file mode 100644 +index 23115ba61bc0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap2430.dtsi ++++ /dev/null +@@ -1,369 +0,0 @@ +-/* +- * Device Tree Source for OMAP243x SoC +- * +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-#include "omap2.dtsi" +- +-/ { +- compatible = "ti,omap2430", "ti,omap2"; +- +- ocp { +- l4_wkup: l4_wkup@49000000 { +- compatible = "ti,omap2-l4-wkup", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x49000000 0x31000>; +- +- prcm: prcm@6000 { +- compatible = "ti,omap2-prcm"; +- reg = <0x6000 0x1000>; +- +- prcm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- prcm_clockdomains: clockdomains { +- }; +- }; +- +- scm: scm@2000 { +- compatible = "ti,omap2-scm", "simple-bus"; +- reg = <0x2000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- #pinctrl-cells = <1>; +- ranges = <0 0x2000 0x1000>; +- +- omap2430_pmx: pinmux@30 { +- compatible = "ti,omap2430-padconf", +- "pinctrl-single"; +- reg = <0x30 0x0154>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <8>; +- pinctrl-single,function-mask = <0x3f>; +- }; +- +- scm_conf: scm_conf@270 { +- compatible = "syscon", +- "simple-bus"; +- reg = <0x270 0x240>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x270 0x240>; +- +- scm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- pbias_regulator: pbias_regulator@230 { +- compatible = "ti,pbias-omap2", "ti,pbias-omap"; +- reg = <0x230 0x4>; +- syscon = <&scm_conf>; +- pbias_mmc_reg: pbias_mmc_omap2430 { +- regulator-name = "pbias_mmc_omap2430"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- }; +- }; +- }; +- +- scm_clockdomains: clockdomains { +- }; +- }; +- +- target-module@20000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x20000 0x4>, +- <0x20004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- ; +- clocks = <&func_32k_ck>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x20000 0x1000>; +- +- counter32k: counter@0 { +- compatible = "ti,omap-counter32k"; +- reg = <0 0x20>; +- }; +- }; +- }; +- +- gpio1: gpio@4900c000 { +- compatible = "ti,omap2-gpio"; +- reg = <0x4900c000 0x200>; +- interrupts = <29>; +- ti,hwmods = "gpio1"; +- ti,gpio-always-on; +- #gpio-cells = <2>; +- gpio-controller; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gpio2: gpio@4900e000 { +- compatible = "ti,omap2-gpio"; +- reg = <0x4900e000 0x200>; +- interrupts = <30>; +- ti,hwmods = "gpio2"; +- ti,gpio-always-on; +- #gpio-cells = <2>; +- gpio-controller; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gpio3: gpio@49010000 { +- compatible = "ti,omap2-gpio"; +- reg = <0x49010000 0x200>; +- interrupts = <31>; +- ti,hwmods = "gpio3"; +- ti,gpio-always-on; +- #gpio-cells = <2>; +- gpio-controller; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gpio4: gpio@49012000 { +- compatible = "ti,omap2-gpio"; +- reg = <0x49012000 0x200>; +- interrupts = <32>; +- ti,hwmods = "gpio4"; +- ti,gpio-always-on; +- #gpio-cells = <2>; +- gpio-controller; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gpio5: gpio@480b6000 { +- compatible = "ti,omap2-gpio"; +- reg = <0x480b6000 0x200>; +- interrupts = <33>; +- ti,hwmods = "gpio5"; +- #gpio-cells = <2>; +- gpio-controller; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gpmc: gpmc@6e000000 { +- compatible = "ti,omap2430-gpmc"; +- reg = <0x6e000000 0x1000>; +- #address-cells = <2>; +- #size-cells = <1>; +- interrupts = <20>; +- gpmc,num-cs = <8>; +- gpmc,num-waitpins = <4>; +- ti,hwmods = "gpmc"; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- mcbsp1: mcbsp@48074000 { +- compatible = "ti,omap2430-mcbsp"; +- reg = <0x48074000 0xff>; +- reg-names = "mpu"; +- interrupts = <64>, /* OCP compliant interrupt */ +- <59>, /* TX interrupt */ +- <60>, /* RX interrupt */ +- <61>; /* RX overflow interrupt */ +- interrupt-names = "common", "tx", "rx", "rx_overflow"; +- ti,buffer-size = <128>; +- ti,hwmods = "mcbsp1"; +- dmas = <&sdma 31>, +- <&sdma 32>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- mcbsp2: mcbsp@48076000 { +- compatible = "ti,omap2430-mcbsp"; +- reg = <0x48076000 0xff>; +- reg-names = "mpu"; +- interrupts = <16>, /* OCP compliant interrupt */ +- <62>, /* TX interrupt */ +- <63>; /* RX interrupt */ +- interrupt-names = "common", "tx", "rx"; +- ti,buffer-size = <128>; +- ti,hwmods = "mcbsp2"; +- dmas = <&sdma 33>, +- <&sdma 34>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- mcbsp3: mcbsp@4808c000 { +- compatible = "ti,omap2430-mcbsp"; +- reg = <0x4808c000 0xff>; +- reg-names = "mpu"; +- interrupts = <17>, /* OCP compliant interrupt */ +- <89>, /* TX interrupt */ +- <90>; /* RX interrupt */ +- interrupt-names = "common", "tx", "rx"; +- ti,buffer-size = <128>; +- ti,hwmods = "mcbsp3"; +- dmas = <&sdma 17>, +- <&sdma 18>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- mcbsp4: mcbsp@4808e000 { +- compatible = "ti,omap2430-mcbsp"; +- reg = <0x4808e000 0xff>; +- reg-names = "mpu"; +- interrupts = <18>, /* OCP compliant interrupt */ +- <54>, /* TX interrupt */ +- <55>; /* RX interrupt */ +- interrupt-names = "common", "tx", "rx"; +- ti,buffer-size = <128>; +- ti,hwmods = "mcbsp4"; +- dmas = <&sdma 19>, +- <&sdma 20>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- mcbsp5: mcbsp@48096000 { +- compatible = "ti,omap2430-mcbsp"; +- reg = <0x48096000 0xff>; +- reg-names = "mpu"; +- interrupts = <19>, /* OCP compliant interrupt */ +- <81>, /* TX interrupt */ +- <82>; /* RX interrupt */ +- interrupt-names = "common", "tx", "rx"; +- ti,buffer-size = <128>; +- ti,hwmods = "mcbsp5"; +- dmas = <&sdma 21>, +- <&sdma 22>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- mmc1: mmc@4809c000 { +- compatible = "ti,omap2-hsmmc"; +- reg = <0x4809c000 0x200>; +- interrupts = <83>; +- ti,hwmods = "mmc1"; +- ti,dual-volt; +- dmas = <&sdma 61>, <&sdma 62>; +- dma-names = "tx", "rx"; +- pbias-supply = <&pbias_mmc_reg>; +- }; +- +- mmc2: mmc@480b4000 { +- compatible = "ti,omap2-hsmmc"; +- reg = <0x480b4000 0x200>; +- interrupts = <86>; +- ti,hwmods = "mmc2"; +- dmas = <&sdma 47>, <&sdma 48>; +- dma-names = "tx", "rx"; +- }; +- +- mailbox: mailbox@48094000 { +- compatible = "ti,omap2-mailbox"; +- reg = <0x48094000 0x200>; +- interrupts = <26>; +- ti,hwmods = "mailbox"; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <6>; +- mbox_dsp: mbox-dsp { +- ti,mbox-tx = <0 0 0>; +- ti,mbox-rx = <1 0 0>; +- }; +- }; +- +- timer1_target: target-module@49018000 { +- compatible = "ti,sysc-omap2-timer", "ti,sysc"; +- reg = <0x49018000 0x4>, +- <0x49018010 0x4>, +- <0x49018014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- clocks = <&gpt1_fck>, <&gpt1_ick>; +- clock-names = "fck", "ick"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49018000 0x1000>; +- +- timer1: timer@0 { +- compatible = "ti,omap2420-timer"; +- reg = <0 0x400>; +- interrupts = <37>; +- ti,timer-alwon; +- }; +- }; +- +- mcspi3: spi@480b8000 { +- compatible = "ti,omap2-mcspi"; +- ti,hwmods = "mcspi3"; +- reg = <0x480b8000 0x100>; +- interrupts = <91>; +- dmas = <&sdma 15 &sdma 16 &sdma 23 &sdma 24>; +- dma-names = "tx0", "rx0", "tx1", "rx1"; +- }; +- +- usb_otg_hs: usb_otg_hs@480ac000 { +- compatible = "ti,omap2-musb"; +- ti,hwmods = "usb_otg_hs"; +- reg = <0x480ac000 0x1000>; +- interrupts = <93>; +- }; +- +- wd_timer2: wdt@49016000 { +- compatible = "ti,omap2-wdt"; +- ti,hwmods = "wd_timer2"; +- reg = <0x49016000 0x80>; +- }; +- }; +-}; +- +-&sdma { +- compatible = "ti,omap2430-sdma", "ti,omap-sdma"; +-}; +- +-&i2c1 { +- compatible = "ti,omap2430-i2c"; +-}; +- +-&i2c2 { +- compatible = "ti,omap2430-i2c"; +-}; +- +-#include "omap24xx-clocks.dtsi" +-#include "omap2430-clocks.dtsi" +- +-/* Preferred always-on timer for clockevent */ +-&timer1_target { +- ti,no-reset-on-init; +- ti,no-idle; +- timer@0 { +- assigned-clocks = <&gpt1_fck>; +- assigned-clock-parents = <&func_32k_ck>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap24xx-clocks.dtsi b/scripts/dtc/include-prefixes/arm/omap24xx-clocks.dtsi +deleted file mode 100644 +index 07af87edf0e2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap24xx-clocks.dtsi ++++ /dev/null +@@ -1,1241 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for OMAP24xx clock data +- * +- * Copyright (C) 2014 Texas Instruments, Inc. +- */ +-&scm_clocks { +- mcbsp1_mux_fck: mcbsp1_mux_fck@4 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&func_96m_ck>, <&mcbsp_clks>; +- ti,bit-shift = <2>; +- reg = <0x4>; +- }; +- +- mcbsp1_fck: mcbsp1_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; +- }; +- +- mcbsp2_mux_fck: mcbsp2_mux_fck@4 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&func_96m_ck>, <&mcbsp_clks>; +- ti,bit-shift = <6>; +- reg = <0x4>; +- }; +- +- mcbsp2_fck: mcbsp2_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; +- }; +-}; +- +-&prcm_clocks { +- func_32k_ck: func_32k_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- secure_32k_ck: secure_32k_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- virt_12m_ck: virt_12m_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <12000000>; +- }; +- +- virt_13m_ck: virt_13m_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <13000000>; +- }; +- +- virt_19200000_ck: virt_19200000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <19200000>; +- }; +- +- virt_26m_ck: virt_26m_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- }; +- +- aplls_clkin_ck: aplls_clkin_ck@540 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>; +- ti,bit-shift = <23>; +- reg = <0x0540>; +- }; +- +- aplls_clkin_x2_ck: aplls_clkin_x2_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&aplls_clkin_ck>; +- clock-mult = <2>; +- clock-div = <1>; +- }; +- +- osc_ck: osc_ck@60 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>; +- ti,bit-shift = <6>; +- reg = <0x0060>; +- ti,index-starts-at-one; +- }; +- +- sys_ck: sys_ck@60 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&osc_ck>; +- ti,bit-shift = <6>; +- ti,max-div = <3>; +- reg = <0x0060>; +- ti,index-starts-at-one; +- }; +- +- alt_ck: alt_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <54000000>; +- }; +- +- mcbsp_clks: mcbsp_clks { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0x0>; +- }; +- +- dpll_ck: dpll_ck@500 { +- #clock-cells = <0>; +- compatible = "ti,omap2-dpll-core-clock"; +- clocks = <&sys_ck>, <&sys_ck>; +- reg = <0x0500>, <0x0540>; +- }; +- +- apll96_ck: apll96_ck@500 { +- #clock-cells = <0>; +- compatible = "ti,omap2-apll-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <2>; +- ti,idlest-shift = <8>; +- ti,clock-frequency = <96000000>; +- reg = <0x0500>, <0x0530>, <0x0520>; +- }; +- +- apll54_ck: apll54_ck@500 { +- #clock-cells = <0>; +- compatible = "ti,omap2-apll-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <6>; +- ti,idlest-shift = <9>; +- ti,clock-frequency = <54000000>; +- reg = <0x0500>, <0x0530>, <0x0520>; +- }; +- +- func_54m_ck: func_54m_ck@540 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&apll54_ck>, <&alt_ck>; +- ti,bit-shift = <5>; +- reg = <0x0540>; +- }; +- +- core_ck: core_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- func_96m_ck: func_96m_ck@540 { +- #clock-cells = <0>; +- }; +- +- apll96_d2_ck: apll96_d2_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&apll96_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- func_48m_ck: func_48m_ck@540 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&apll96_d2_ck>, <&alt_ck>; +- ti,bit-shift = <3>; +- reg = <0x0540>; +- }; +- +- func_12m_ck: func_12m_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&func_48m_ck>; +- clock-mult = <1>; +- clock-div = <4>; +- }; +- +- sys_clkout_src_gate: sys_clkout_src_gate@70 { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&core_ck>; +- ti,bit-shift = <7>; +- reg = <0x0070>; +- }; +- +- sys_clkout_src_mux: sys_clkout_src_mux@70 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>; +- reg = <0x0070>; +- }; +- +- sys_clkout_src: sys_clkout_src { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>; +- }; +- +- sys_clkout: sys_clkout@70 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&sys_clkout_src>; +- ti,bit-shift = <3>; +- ti,max-div = <64>; +- reg = <0x0070>; +- ti,index-power-of-two; +- }; +- +- emul_ck: emul_ck@78 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&func_54m_ck>; +- ti,bit-shift = <0>; +- reg = <0x0078>; +- }; +- +- mpu_ck: mpu_ck@140 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&core_ck>; +- ti,max-div = <31>; +- reg = <0x0140>; +- ti,index-starts-at-one; +- }; +- +- dsp_gate_fck: dsp_gate_fck@800 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&core_ck>; +- ti,bit-shift = <0>; +- reg = <0x0800>; +- }; +- +- dsp_div_fck: dsp_div_fck@840 { +- #clock-cells = <0>; +- compatible = "ti,composite-divider-clock"; +- clocks = <&core_ck>; +- reg = <0x0840>; +- }; +- +- dsp_fck: dsp_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&dsp_gate_fck>, <&dsp_div_fck>; +- }; +- +- core_l3_ck: core_l3_ck@240 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&core_ck>; +- ti,max-div = <31>; +- reg = <0x0240>; +- ti,index-starts-at-one; +- }; +- +- gfx_3d_gate_fck: gfx_3d_gate_fck@300 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&core_l3_ck>; +- ti,bit-shift = <2>; +- reg = <0x0300>; +- }; +- +- gfx_3d_div_fck: gfx_3d_div_fck@340 { +- #clock-cells = <0>; +- compatible = "ti,composite-divider-clock"; +- clocks = <&core_l3_ck>; +- ti,max-div = <4>; +- reg = <0x0340>; +- ti,index-starts-at-one; +- }; +- +- gfx_3d_fck: gfx_3d_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>; +- }; +- +- gfx_2d_gate_fck: gfx_2d_gate_fck@300 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&core_l3_ck>; +- ti,bit-shift = <1>; +- reg = <0x0300>; +- }; +- +- gfx_2d_div_fck: gfx_2d_div_fck@340 { +- #clock-cells = <0>; +- compatible = "ti,composite-divider-clock"; +- clocks = <&core_l3_ck>; +- ti,max-div = <4>; +- reg = <0x0340>; +- ti,index-starts-at-one; +- }; +- +- gfx_2d_fck: gfx_2d_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>; +- }; +- +- gfx_ick: gfx_ick@310 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&core_l3_ck>; +- ti,bit-shift = <0>; +- reg = <0x0310>; +- }; +- +- l4_ck: l4_ck@240 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&core_l3_ck>; +- ti,bit-shift = <5>; +- ti,max-div = <3>; +- reg = <0x0240>; +- ti,index-starts-at-one; +- }; +- +- dss_ick: dss_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-no-wait-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <0>; +- reg = <0x0210>; +- }; +- +- dss1_gate_fck: dss1_gate_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&core_ck>; +- ti,bit-shift = <0>; +- reg = <0x0200>; +- }; +- +- core_d2_ck: core_d2_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&core_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- core_d3_ck: core_d3_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&core_ck>; +- clock-mult = <1>; +- clock-div = <3>; +- }; +- +- core_d4_ck: core_d4_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&core_ck>; +- clock-mult = <1>; +- clock-div = <4>; +- }; +- +- core_d5_ck: core_d5_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&core_ck>; +- clock-mult = <1>; +- clock-div = <5>; +- }; +- +- core_d6_ck: core_d6_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&core_ck>; +- clock-mult = <1>; +- clock-div = <6>; +- }; +- +- dummy_ck: dummy_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- core_d8_ck: core_d8_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&core_ck>; +- clock-mult = <1>; +- clock-div = <8>; +- }; +- +- core_d9_ck: core_d9_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&core_ck>; +- clock-mult = <1>; +- clock-div = <9>; +- }; +- +- core_d12_ck: core_d12_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&core_ck>; +- clock-mult = <1>; +- clock-div = <12>; +- }; +- +- core_d16_ck: core_d16_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&core_ck>; +- clock-mult = <1>; +- clock-div = <16>; +- }; +- +- dss1_mux_fck: dss1_mux_fck@240 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>; +- ti,bit-shift = <8>; +- reg = <0x0240>; +- }; +- +- dss1_fck: dss1_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&dss1_gate_fck>, <&dss1_mux_fck>; +- }; +- +- dss2_gate_fck: dss2_gate_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&func_48m_ck>; +- ti,bit-shift = <1>; +- reg = <0x0200>; +- }; +- +- dss2_mux_fck: dss2_mux_fck@240 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&sys_ck>, <&func_48m_ck>; +- ti,bit-shift = <13>; +- reg = <0x0240>; +- }; +- +- dss2_fck: dss2_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&dss2_gate_fck>, <&dss2_mux_fck>; +- }; +- +- dss_54m_fck: dss_54m_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_54m_ck>; +- ti,bit-shift = <2>; +- reg = <0x0200>; +- }; +- +- ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck@204 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&core_ck>; +- ti,bit-shift = <1>; +- reg = <0x0204>; +- }; +- +- ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck@240 { +- #clock-cells = <0>; +- compatible = "ti,composite-divider-clock"; +- clocks = <&core_ck>; +- ti,bit-shift = <20>; +- reg = <0x0240>; +- }; +- +- ssi_ssr_sst_fck: ssi_ssr_sst_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>; +- }; +- +- usb_l4_gate_ick: usb_l4_gate_ick@214 { +- #clock-cells = <0>; +- compatible = "ti,composite-interface-clock"; +- clocks = <&core_l3_ck>; +- ti,bit-shift = <0>; +- reg = <0x0214>; +- }; +- +- usb_l4_div_ick: usb_l4_div_ick@240 { +- #clock-cells = <0>; +- compatible = "ti,composite-divider-clock"; +- clocks = <&core_l3_ck>; +- ti,bit-shift = <25>; +- reg = <0x0240>; +- ti,dividers = <0>, <1>, <2>, <0>, <4>; +- }; +- +- usb_l4_ick: usb_l4_ick { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; +- }; +- +- ssi_l4_ick: ssi_l4_ick@214 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <1>; +- reg = <0x0214>; +- }; +- +- gpt1_ick: gpt1_ick@410 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <0>; +- reg = <0x0410>; +- }; +- +- gpt1_gate_fck: gpt1_gate_fck@400 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&func_32k_ck>; +- ti,bit-shift = <0>; +- reg = <0x0400>; +- }; +- +- gpt1_mux_fck: gpt1_mux_fck@440 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; +- reg = <0x0440>; +- }; +- +- gpt1_fck: gpt1_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; +- }; +- +- gpt2_ick: gpt2_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <4>; +- reg = <0x0210>; +- }; +- +- gpt2_gate_fck: gpt2_gate_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&func_32k_ck>; +- ti,bit-shift = <4>; +- reg = <0x0200>; +- }; +- +- gpt2_mux_fck: gpt2_mux_fck@244 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; +- ti,bit-shift = <2>; +- reg = <0x0244>; +- }; +- +- gpt2_fck: gpt2_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; +- }; +- +- gpt3_ick: gpt3_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <5>; +- reg = <0x0210>; +- }; +- +- gpt3_gate_fck: gpt3_gate_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&func_32k_ck>; +- ti,bit-shift = <5>; +- reg = <0x0200>; +- }; +- +- gpt3_mux_fck: gpt3_mux_fck@244 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; +- ti,bit-shift = <4>; +- reg = <0x0244>; +- }; +- +- gpt3_fck: gpt3_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; +- }; +- +- gpt4_ick: gpt4_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <6>; +- reg = <0x0210>; +- }; +- +- gpt4_gate_fck: gpt4_gate_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&func_32k_ck>; +- ti,bit-shift = <6>; +- reg = <0x0200>; +- }; +- +- gpt4_mux_fck: gpt4_mux_fck@244 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; +- ti,bit-shift = <6>; +- reg = <0x0244>; +- }; +- +- gpt4_fck: gpt4_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; +- }; +- +- gpt5_ick: gpt5_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <7>; +- reg = <0x0210>; +- }; +- +- gpt5_gate_fck: gpt5_gate_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&func_32k_ck>; +- ti,bit-shift = <7>; +- reg = <0x0200>; +- }; +- +- gpt5_mux_fck: gpt5_mux_fck@244 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; +- ti,bit-shift = <8>; +- reg = <0x0244>; +- }; +- +- gpt5_fck: gpt5_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; +- }; +- +- gpt6_ick: gpt6_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <8>; +- reg = <0x0210>; +- }; +- +- gpt6_gate_fck: gpt6_gate_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&func_32k_ck>; +- ti,bit-shift = <8>; +- reg = <0x0200>; +- }; +- +- gpt6_mux_fck: gpt6_mux_fck@244 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; +- ti,bit-shift = <10>; +- reg = <0x0244>; +- }; +- +- gpt6_fck: gpt6_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; +- }; +- +- gpt7_ick: gpt7_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <9>; +- reg = <0x0210>; +- }; +- +- gpt7_gate_fck: gpt7_gate_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&func_32k_ck>; +- ti,bit-shift = <9>; +- reg = <0x0200>; +- }; +- +- gpt7_mux_fck: gpt7_mux_fck@244 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; +- ti,bit-shift = <12>; +- reg = <0x0244>; +- }; +- +- gpt7_fck: gpt7_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; +- }; +- +- gpt8_ick: gpt8_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <10>; +- reg = <0x0210>; +- }; +- +- gpt8_gate_fck: gpt8_gate_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&func_32k_ck>; +- ti,bit-shift = <10>; +- reg = <0x0200>; +- }; +- +- gpt8_mux_fck: gpt8_mux_fck@244 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; +- ti,bit-shift = <14>; +- reg = <0x0244>; +- }; +- +- gpt8_fck: gpt8_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; +- }; +- +- gpt9_ick: gpt9_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <11>; +- reg = <0x0210>; +- }; +- +- gpt9_gate_fck: gpt9_gate_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&func_32k_ck>; +- ti,bit-shift = <11>; +- reg = <0x0200>; +- }; +- +- gpt9_mux_fck: gpt9_mux_fck@244 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; +- ti,bit-shift = <16>; +- reg = <0x0244>; +- }; +- +- gpt9_fck: gpt9_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>; +- }; +- +- gpt10_ick: gpt10_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <12>; +- reg = <0x0210>; +- }; +- +- gpt10_gate_fck: gpt10_gate_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&func_32k_ck>; +- ti,bit-shift = <12>; +- reg = <0x0200>; +- }; +- +- gpt10_mux_fck: gpt10_mux_fck@244 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; +- ti,bit-shift = <18>; +- reg = <0x0244>; +- }; +- +- gpt10_fck: gpt10_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; +- }; +- +- gpt11_ick: gpt11_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <13>; +- reg = <0x0210>; +- }; +- +- gpt11_gate_fck: gpt11_gate_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&func_32k_ck>; +- ti,bit-shift = <13>; +- reg = <0x0200>; +- }; +- +- gpt11_mux_fck: gpt11_mux_fck@244 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; +- ti,bit-shift = <20>; +- reg = <0x0244>; +- }; +- +- gpt11_fck: gpt11_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>; +- }; +- +- gpt12_ick: gpt12_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <14>; +- reg = <0x0210>; +- }; +- +- gpt12_gate_fck: gpt12_gate_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&func_32k_ck>; +- ti,bit-shift = <14>; +- reg = <0x0200>; +- }; +- +- gpt12_mux_fck: gpt12_mux_fck@244 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; +- ti,bit-shift = <22>; +- reg = <0x0244>; +- }; +- +- gpt12_fck: gpt12_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>; +- }; +- +- mcbsp1_ick: mcbsp1_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <15>; +- reg = <0x0210>; +- }; +- +- mcbsp1_gate_fck: mcbsp1_gate_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&mcbsp_clks>; +- ti,bit-shift = <15>; +- reg = <0x0200>; +- }; +- +- mcbsp2_ick: mcbsp2_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <16>; +- reg = <0x0210>; +- }; +- +- mcbsp2_gate_fck: mcbsp2_gate_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&mcbsp_clks>; +- ti,bit-shift = <16>; +- reg = <0x0200>; +- }; +- +- mcspi1_ick: mcspi1_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <17>; +- reg = <0x0210>; +- }; +- +- mcspi1_fck: mcspi1_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_48m_ck>; +- ti,bit-shift = <17>; +- reg = <0x0200>; +- }; +- +- mcspi2_ick: mcspi2_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <18>; +- reg = <0x0210>; +- }; +- +- mcspi2_fck: mcspi2_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_48m_ck>; +- ti,bit-shift = <18>; +- reg = <0x0200>; +- }; +- +- uart1_ick: uart1_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <21>; +- reg = <0x0210>; +- }; +- +- uart1_fck: uart1_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_48m_ck>; +- ti,bit-shift = <21>; +- reg = <0x0200>; +- }; +- +- uart2_ick: uart2_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <22>; +- reg = <0x0210>; +- }; +- +- uart2_fck: uart2_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_48m_ck>; +- ti,bit-shift = <22>; +- reg = <0x0200>; +- }; +- +- uart3_ick: uart3_ick@214 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <2>; +- reg = <0x0214>; +- }; +- +- uart3_fck: uart3_fck@204 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_48m_ck>; +- ti,bit-shift = <2>; +- reg = <0x0204>; +- }; +- +- gpios_ick: gpios_ick@410 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <2>; +- reg = <0x0410>; +- }; +- +- gpios_fck: gpios_fck@400 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_32k_ck>; +- ti,bit-shift = <2>; +- reg = <0x0400>; +- }; +- +- mpu_wdt_ick: mpu_wdt_ick@410 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <3>; +- reg = <0x0410>; +- }; +- +- mpu_wdt_fck: mpu_wdt_fck@400 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_32k_ck>; +- ti,bit-shift = <3>; +- reg = <0x0400>; +- }; +- +- sync_32k_ick: sync_32k_ick@410 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <1>; +- reg = <0x0410>; +- }; +- +- wdt1_ick: wdt1_ick@410 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <4>; +- reg = <0x0410>; +- }; +- +- omapctrl_ick: omapctrl_ick@410 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <5>; +- reg = <0x0410>; +- }; +- +- cam_fck: cam_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&func_96m_ck>; +- ti,bit-shift = <31>; +- reg = <0x0200>; +- }; +- +- cam_ick: cam_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-no-wait-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <31>; +- reg = <0x0210>; +- }; +- +- mailboxes_ick: mailboxes_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <30>; +- reg = <0x0210>; +- }; +- +- wdt4_ick: wdt4_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <29>; +- reg = <0x0210>; +- }; +- +- wdt4_fck: wdt4_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_32k_ck>; +- ti,bit-shift = <29>; +- reg = <0x0200>; +- }; +- +- mspro_ick: mspro_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <27>; +- reg = <0x0210>; +- }; +- +- mspro_fck: mspro_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_96m_ck>; +- ti,bit-shift = <27>; +- reg = <0x0200>; +- }; +- +- fac_ick: fac_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <25>; +- reg = <0x0210>; +- }; +- +- fac_fck: fac_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_12m_ck>; +- ti,bit-shift = <25>; +- reg = <0x0200>; +- }; +- +- hdq_ick: hdq_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <23>; +- reg = <0x0210>; +- }; +- +- hdq_fck: hdq_fck@200 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_12m_ck>; +- ti,bit-shift = <23>; +- reg = <0x0200>; +- }; +- +- i2c1_ick: i2c1_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <19>; +- reg = <0x0210>; +- }; +- +- i2c2_ick: i2c2_ick@210 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <20>; +- reg = <0x0210>; +- }; +- +- gpmc_fck: gpmc_fck@238 { +- #clock-cells = <0>; +- compatible = "ti,fixed-factor-clock"; +- clocks = <&core_l3_ck>; +- ti,clock-div = <1>; +- ti,autoidle-shift = <1>; +- reg = <0x0238>; +- ti,clock-mult = <1>; +- }; +- +- sdma_fck: sdma_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&core_l3_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- sdma_ick: sdma_ick@238 { +- #clock-cells = <0>; +- compatible = "ti,fixed-factor-clock"; +- clocks = <&core_l3_ck>; +- ti,clock-div = <1>; +- ti,autoidle-shift = <0>; +- reg = <0x0238>; +- ti,clock-mult = <1>; +- }; +- +- sdrc_ick: sdrc_ick@238 { +- #clock-cells = <0>; +- compatible = "ti,fixed-factor-clock"; +- clocks = <&core_l3_ck>; +- ti,clock-div = <1>; +- ti,autoidle-shift = <2>; +- reg = <0x0238>; +- ti,clock-mult = <1>; +- }; +- +- des_ick: des_ick@21c { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <0>; +- reg = <0x021c>; +- }; +- +- sha_ick: sha_ick@21c { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <1>; +- reg = <0x021c>; +- }; +- +- rng_ick: rng_ick@21c { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <2>; +- reg = <0x021c>; +- }; +- +- aes_ick: aes_ick@21c { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <3>; +- reg = <0x021c>; +- }; +- +- pka_ick: pka_ick@21c { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l4_ck>; +- ti,bit-shift = <4>; +- reg = <0x021c>; +- }; +- +- usb_fck: usb_fck@204 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&func_48m_ck>; +- ti,bit-shift = <0>; +- reg = <0x0204>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-beagle-ab4.dts b/scripts/dtc/include-prefixes/arm/omap3-beagle-ab4.dts +deleted file mode 100644 +index 990ff2d84686..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-beagle-ab4.dts ++++ /dev/null +@@ -1,47 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/dts-v1/; +- +-#include "omap3-beagle.dts" +- +-/ { +- model = "TI OMAP3 BeagleBoard A to B4"; +- compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3"; +-}; +- +-/* +- * Workaround for capacitor C70 issue, see "Boards revision A and < B5" +- * section at https://elinux.org/BeagleBoard_Community +- */ +- +-/* Unusable as clocksource because of unreliable oscillator */ +-&counter32k { +- status = "disabled"; +-}; +- +-/* Unusable as clockevent because of unreliable oscillator, allow to idle */ +-&timer1_target { +- /delete-property/ti,no-reset-on-init; +- /delete-property/ti,no-idle; +- timer@0 { +- /delete-property/ti,timer-alwon; +- }; +-}; +- +-/* Preferred always-on timer for clocksource */ +-&timer12_target { +- ti,no-reset-on-init; +- ti,no-idle; +- timer@0 { +- /* Always clocked by secure_32k_fck */ +- }; +-}; +- +-/* Preferred timer for clockevent */ +-&timer2_target { +- ti,no-reset-on-init; +- ti,no-idle; +- timer@0 { +- assigned-clocks = <&gpt2_fck>; +- assigned-clock-parents = <&sys_ck>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-beagle-xm-ab.dts b/scripts/dtc/include-prefixes/arm/omap3-beagle-xm-ab.dts +deleted file mode 100644 +index cb6968a8bce8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-beagle-xm-ab.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include "omap3-beagle-xm.dts" +- +-/ { +- /* HS USB Port 2 Power enable was inverted with the xM C */ +- hsusb2_power: hsusb2_power_reg { +- enable-active-high; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-beagle-xm.dts b/scripts/dtc/include-prefixes/arm/omap3-beagle-xm.dts +deleted file mode 100644 +index a858ebfa1500..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-beagle-xm.dts ++++ /dev/null +@@ -1,419 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "omap36xx.dtsi" +- +-/ { +- model = "TI OMAP3 BeagleBoard xM"; +- compatible = "ti,omap3-beagle-xm", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&vcc>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512 MB */ +- }; +- +- aliases { +- display0 = &dvi0; +- display1 = &tv0; +- ethernet = ðernet; +- }; +- +- /* fixed 26MHz oscillator */ +- hfclk_26m: oscillator { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- }; +- +- led-controller-1 { +- compatible = "gpio-leds"; +- +- led-1 { +- label = "beagleboard::usr0"; +- gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ +- linux,default-trigger = "heartbeat"; +- }; +- +- led-2 { +- label = "beagleboard::usr1"; +- gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ +- linux,default-trigger = "mmc0"; +- }; +- }; +- +- led-controller-2 { +- compatible = "pwm-leds"; +- +- led-3 { +- label = "beagleboard::pmu_stat"; +- pwms = <&twl_pwmled 1 7812500>; +- max-brightness = <127>; +- }; +- }; +- +- sound { +- compatible = "ti,omap-twl4030"; +- ti,model = "omap3beagle"; +- +- ti,mcbsp = <&mcbsp2>; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- user { +- label = "user"; +- gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; +- linux,code = <0x114>; +- wakeup-source; +- }; +- +- }; +- +- /* HS USB Port 2 Power */ +- hsusb2_power: hsusb2_power_reg { +- compatible = "regulator-fixed"; +- regulator-name = "hsusb2_vbus"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ +- startup-delay-us = <70000>; +- }; +- +- /* HS USB Host PHY on PORT 2 */ +- hsusb2_phy: hsusb2_phy { +- compatible = "usb-nop-xceiv"; +- reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ +- vcc-supply = <&hsusb2_power>; +- #phy-cells = <0>; +- }; +- +- tfp410: encoder0 { +- compatible = "ti,tfp410"; +- powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>; +- +- /* XXX pinctrl from twl */ +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tfp410_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- tfp410_out: endpoint { +- remote-endpoint = <&dvi_connector_in>; +- }; +- }; +- }; +- }; +- +- dvi0: connector0 { +- compatible = "dvi-connector"; +- label = "dvi"; +- +- digital; +- +- ddc-i2c-bus = <&i2c3>; +- +- port { +- dvi_connector_in: endpoint { +- remote-endpoint = <&tfp410_out>; +- }; +- }; +- }; +- +- tv0: connector1 { +- compatible = "svideo-connector"; +- label = "tv"; +- +- port { +- tv_connector_in: endpoint { +- remote-endpoint = <&venc_out>; +- }; +- }; +- }; +- +- etb@5401b000 { +- compatible = "arm,coresight-etb10", "arm,primecell"; +- reg = <0x5401b000 0x1000>; +- +- clocks = <&emu_src_ck>; +- clock-names = "apb_pclk"; +- in-ports { +- port { +- etb_in: endpoint { +- remote-endpoint = <&etm_out>; +- }; +- }; +- }; +- }; +- +- etm@54010000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0x54010000 0x1000>; +- +- clocks = <&emu_src_ck>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- etm_out: endpoint { +- remote-endpoint = <&etb_in>; +- }; +- }; +- }; +- }; +-}; +- +-&omap3_pmx_wkup { +- gpio1_pins: pinmux_gpio1_pins { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a0e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */ +- >; +- }; +- +- dss_dpi_pins2: pinmux_dss_dpi_pins1 { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ +- OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ +- OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ +- OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ +- OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ +- OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ +- >; +- }; +-}; +- +-&omap3_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &hsusb2_pins +- >; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ +- OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ +- >; +- }; +- +- hsusb2_pins: pinmux_hsusb2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ +- OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ +- OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ +- OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ +- OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ +- OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ +- >; +- }; +- +- dss_dpi_pins1: pinmux_dss_dpi_pins2 { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ +- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ +- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ +- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ +- +- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ +- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ +- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ +- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ +- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ +- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ +- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ +- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ +- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ +- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ +- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ +- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ +- +- OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ +- OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ +- OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ +- OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ +- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ +- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ +- >; +- }; +-}; +- +-&omap3_pmx_core2 { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &hsusb2_2_pins +- >; +- +- hsusb2_2_pins: pinmux_hsusb2_2_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ +- OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ +- OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ +- OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ +- OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ +- OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ +- >; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <2600000>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- interrupt-parent = <&intc>; +- +- clocks = <&hfclk_26m>; +- clock-names = "fck"; +- +- twl_audio: audio { +- compatible = "ti,twl4030-audio"; +- codec { +- }; +- }; +- +- twl_power: power { +- compatible = "ti,twl4030-power-beagleboard-xm", "ti,twl4030-power-idle-osc-off"; +- ti,use_poweroff; +- }; +- }; +-}; +- +-#include "twl4030.dtsi" +-#include "twl4030_omap3.dtsi" +- +-&i2c2 { +- clock-frequency = <400000>; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +-}; +- +-&mmc1 { +- vmmc-supply = <&vmmc1>; +- vqmmc-supply = <&vsim>; +- bus-width = <8>; +-}; +- +-&mmc2 { +- status = "disabled"; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-&twl_gpio { +- ti,use-leds; +- /* pullups: BIT(1) */ +- ti,pullups = <0x000002>; +- /* +- * pulldowns: +- * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) +- * BIT(15), BIT(16), BIT(17) +- */ +- ti,pulldowns = <0x03a1c4>; +-}; +- +-&usb_otg_hs { +- interface-type = <0>; +- usb-phy = <&usb2_phy>; +- phys = <&usb2_phy>; +- phy-names = "usb2-phy"; +- mode = <3>; +- power = <50>; +-}; +- +-&uart3 { +- interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +-}; +- +-&gpio1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio1_pins>; +-}; +- +-&usbhshost { +- port2-mode = "ehci-phy"; +-}; +- +-&usbhsehci { +- phys = <0 &hsusb2_phy>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- hub@2 { +- compatible = "usb424,9514"; +- reg = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethernet: usbether@1 { +- compatible = "usb424,ec00"; +- reg = <1>; +- }; +- }; +-}; +- +-&vaux2 { +- regulator-name = "usb_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +-}; +- +-&mcbsp2 { +- status = "okay"; +-}; +- +-&dss { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = < +- &dss_dpi_pins1 +- &dss_dpi_pins2 +- >; +- +- port { +- dpi_out: endpoint { +- remote-endpoint = <&tfp410_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-&venc { +- status = "okay"; +- +- vdda-supply = <&vdac>; +- +- port { +- venc_out: endpoint { +- remote-endpoint = <&tv_connector_in>; +- ti,channels = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-beagle.dts b/scripts/dtc/include-prefixes/arm/omap3-beagle.dts +deleted file mode 100644 +index 0548b391334f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-beagle.dts ++++ /dev/null +@@ -1,436 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "omap34xx.dtsi" +- +-/ { +- model = "TI OMAP3 BeagleBoard"; +- compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3"; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&vcc>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +- +- aliases { +- display0 = &dvi0; +- display1 = &tv0; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pmu_stat { +- label = "beagleboard::pmu_stat"; +- gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ +- }; +- +- heartbeat { +- label = "beagleboard::usr0"; +- gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ +- linux,default-trigger = "heartbeat"; +- }; +- +- mmc { +- label = "beagleboard::usr1"; +- gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ +- linux,default-trigger = "mmc0"; +- }; +- }; +- +- /* HS USB Port 2 Power */ +- hsusb2_power: hsusb2_power_reg { +- compatible = "regulator-fixed"; +- regulator-name = "hsusb2_vbus"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ +- startup-delay-us = <70000>; +- }; +- +- /* HS USB Host PHY on PORT 2 */ +- hsusb2_phy: hsusb2_phy { +- compatible = "usb-nop-xceiv"; +- reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ +- vcc-supply = <&hsusb2_power>; +- #phy-cells = <0>; +- }; +- +- sound { +- compatible = "ti,omap-twl4030"; +- ti,model = "omap3beagle"; +- +- ti,mcbsp = <&mcbsp2>; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- user { +- label = "user"; +- gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- linux,code = <0x114>; +- wakeup-source; +- }; +- +- }; +- +- tfp410: encoder0 { +- compatible = "ti,tfp410"; +- powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ +- +- pinctrl-names = "default"; +- pinctrl-0 = <&tfp410_pins>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tfp410_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- tfp410_out: endpoint { +- remote-endpoint = <&dvi_connector_in>; +- }; +- }; +- }; +- }; +- +- dvi0: connector0 { +- compatible = "dvi-connector"; +- label = "dvi"; +- +- digital; +- +- ddc-i2c-bus = <&i2c3>; +- +- port { +- dvi_connector_in: endpoint { +- remote-endpoint = <&tfp410_out>; +- }; +- }; +- }; +- +- tv0: connector1 { +- compatible = "svideo-connector"; +- label = "tv"; +- +- port { +- tv_connector_in: endpoint { +- remote-endpoint = <&venc_out>; +- }; +- }; +- }; +- +- etb@540000000 { +- compatible = "arm,coresight-etb10", "arm,primecell"; +- reg = <0x5401b000 0x1000>; +- +- clocks = <&emu_src_ck>; +- clock-names = "apb_pclk"; +- in-ports { +- port { +- etb_in: endpoint { +- remote-endpoint = <&etm_out>; +- }; +- }; +- }; +- }; +- +- etm@54010000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0x54010000 0x1000>; +- +- clocks = <&emu_src_ck>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- etm_out: endpoint { +- remote-endpoint = <&etb_in>; +- }; +- }; +- }; +- }; +-}; +- +-&omap3_pmx_wkup { +- gpio1_pins: pinmux_gpio1_pins { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ +- >; +- }; +-}; +- +-&omap3_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &hsusb2_pins +- >; +- +- hsusb2_pins: pinmux_hsusb2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ +- OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ +- OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ +- OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ +- OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ +- OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ +- >; +- }; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ +- OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ +- >; +- }; +- +- tfp410_pins: pinmux_tfp410_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ +- >; +- }; +- +- dss_dpi_pins: pinmux_dss_dpi_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ +- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ +- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ +- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ +- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ +- OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ +- OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ +- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ +- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ +- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ +- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ +- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ +- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ +- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ +- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ +- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ +- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ +- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ +- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ +- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ +- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ +- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ +- OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ +- OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ +- OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ +- OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ +- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ +- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ +- >; +- }; +-}; +- +-&omap3_pmx_core2 { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &hsusb2_2_pins +- >; +- +- hsusb2_2_pins: pinmux_hsusb2_2_pins { +- pinctrl-single,pins = < +- OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ +- OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ +- OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ +- OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ +- OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ +- OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ +- >; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <2600000>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- interrupt-parent = <&intc>; +- +- twl_audio: audio { +- compatible = "ti,twl4030-audio"; +- codec { +- }; +- }; +- }; +-}; +- +-#include "twl4030.dtsi" +-#include "twl4030_omap3.dtsi" +- +-&i2c3 { +- clock-frequency = <100000>; +-}; +- +-&mmc1 { +- vmmc-supply = <&vmmc1>; +- vqmmc-supply = <&vsim>; +- bus-width = <8>; +-}; +- +-&mmc2 { +- status = "disabled"; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-&usbhshost { +- port2-mode = "ehci-phy"; +-}; +- +-&usbhsehci { +- phys = <0 &hsusb2_phy>; +-}; +- +-&twl_gpio { +- ti,use-leds; +- /* pullups: BIT(1) */ +- ti,pullups = <0x000002>; +- /* +- * pulldowns: +- * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) +- * BIT(15), BIT(16), BIT(17) +- */ +- ti,pulldowns = <0x03a1c4>; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; +-}; +- +-&gpio1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio1_pins>; +-}; +- +-&usb_otg_hs { +- interface-type = <0>; +- usb-phy = <&usb2_phy>; +- phys = <&usb2_phy>; +- phy-names = "usb2-phy"; +- mode = <3>; +- power = <50>; +-}; +- +-&vaux2 { +- regulator-name = "vdd_ehci"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +-}; +- +-&mcbsp2 { +- status = "okay"; +-}; +- +-/* Needed to power the DPI pins */ +-&vpll2 { +- regulator-always-on; +-}; +- +-&dss { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_dpi_pins>; +- +- port { +- dpi_out: endpoint { +- remote-endpoint = <&tfp410_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-&venc { +- status = "okay"; +- +- vdda-supply = <&vdac>; +- +- port { +- venc_out: endpoint { +- remote-endpoint = <&tv_connector_in>; +- ti,channels = <2>; +- }; +- }; +-}; +- +-&gpmc { +- status = "okay"; +- ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */ +- +- /* Chip select 0 */ +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* NAND I/O window, 4 bytes */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- ti,nand-ecc-opt = "ham1"; +- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ +- nand-bus-width = <16>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- gpmc,device-width = <2>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <36>; +- gpmc,cs-wr-off-ns = <36>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <24>; +- gpmc,adv-wr-off-ns = <36>; +- gpmc,oe-on-ns = <6>; +- gpmc,oe-off-ns = <48>; +- gpmc,we-on-ns = <6>; +- gpmc,we-off-ns = <30>; +- gpmc,rd-cycle-ns = <72>; +- gpmc,wr-cycle-ns = <72>; +- gpmc,access-ns = <54>; +- gpmc,wr-access-ns = <30>; +- +- partition@0 { +- label = "X-Loader"; +- reg = <0 0x80000>; +- }; +- partition@80000 { +- label = "U-Boot"; +- reg = <0x80000 0x1e0000>; +- }; +- partition@1c0000 { +- label = "U-Boot Env"; +- reg = <0x260000 0x20000>; +- }; +- partition@280000 { +- label = "Kernel"; +- reg = <0x280000 0x400000>; +- }; +- partition@780000 { +- label = "Filesystem"; +- reg = <0x680000 0xf980000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-cm-t3517.dts b/scripts/dtc/include-prefixes/arm/omap3-cm-t3517.dts +deleted file mode 100644 +index 3b8349094baa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-cm-t3517.dts ++++ /dev/null +@@ -1,158 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Support for CompuLab CM-T3517 +- */ +-/dts-v1/; +- +-#include "am3517.dtsi" +-#include "omap3-cm-t3x.dtsi" +- +-/ { +- model = "CompuLab CM-T3517"; +- compatible = "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; +- +- vmmc: regulator-vmmc { +- compatible = "regulator-fixed"; +- regulator-name = "vmmc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- wl12xx_vmmc2: wl12xx_vmmc2 { +- compatible = "regulator-fixed"; +- regulator-name = "vw1271"; +- pinctrl-names = "default"; +- pinctrl-0 = < +- &wl12xx_wkup_pins +- &wl12xx_core_pins +- >; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio1 6 GPIO_ACTIVE_HIGH >; /* gpio6 */ +- startup-delay-us = <20000>; +- enable-active-high; +- }; +- +- wl12xx_vaux2: wl12xx_vaux2 { +- compatible = "regulator-fixed"; +- regulator-name = "vwl1271_vaux2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +-}; +- +-&omap3_pmx_wkup { +- +- wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ +- OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE4) /* sys_boot4.gpio_6 */ +- >; +- }; +-}; +- +-&omap3_pmx_core { +- +- phy1_reset_pins: pinmux_hsusb1_phy_reset_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE4) /* uart2_tx.gpio_146 */ +- >; +- }; +- +- phy2_reset_pins: pinmux_hsusb2_phy_reset_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x217a, PIN_OUTPUT | MUX_MODE4) /* uart2_rx.gpio_147 */ +- >; +- }; +- +- otg_drv_vbus: pinmux_otg_drv_vbus { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50MHz_clk.usb0_drvvbus */ +- >; +- }; +- +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ +- OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ +- OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ +- OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ +- OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ +- OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ +- >; +- }; +- +- wl12xx_core_pins: pinmux_wl12xx_core_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs5.gpio_56 */ +- OMAP3_CORE1_IOPAD(0x2176, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_rts.gpio_145 */ +- >; +- }; +- +- usb_hub_pins: pinmux_usb_hub_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2184, PIN_OUTPUT | MUX_MODE4) /* mcbsp4_clkx.gpio_152 - USB HUB RST */ +- >; +- }; +-}; +- +-&hsusb1_phy { +- pinctrl-names = "default"; +- pinctrl-0 = <&phy1_reset_pins>; +- reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>; +-}; +- +-&hsusb2_phy { +- pinctrl-names = "default"; +- pinctrl-0 = <&phy2_reset_pins>; +- reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; +-}; +- +-&davinci_emac { +- status = "okay"; +-}; +- +-&davinci_mdio { +- status = "okay"; +-}; +- +-&am35x_otg_hs { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&otg_drv_vbus>; +-}; +- +-&mmc1 { +- vmmc-supply = <&vmmc>; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- vmmc-supply = <&wl12xx_vmmc2>; +- vqmmc-supply = <&wl12xx_vaux2>; +- non-removable; +- bus-width = <4>; +- cap-power-off-card; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1271"; +- reg = <2>; +- interrupt-parent = <&gpio5>; +- interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* gpio 145 */ +- ref-clock-frequency = <38400000>; +- }; +-}; +- +-&dss { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = < +- &dss_dpi_pins_common +- &dss_dpi_pins_cm_t35x +- >; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-cm-t3530.dts b/scripts/dtc/include-prefixes/arm/omap3-cm-t3530.dts +deleted file mode 100644 +index bc545ee23e71..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-cm-t3530.dts ++++ /dev/null +@@ -1,60 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Support for CompuLab CM-T3530 +- */ +-/dts-v1/; +- +-#include "omap34xx.dtsi" +-#include "omap3-cm-t3x30.dtsi" +- +-/ { +- model = "CompuLab CM-T3530"; +- compatible = "compulab,omap3-cm-t3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; +- +- /* Regulator to trigger the reset signal of the Wifi module */ +- mmc2_sdio_reset: regulator-mmc2-sdio-reset { +- compatible = "regulator-fixed"; +- regulator-name = "regulator-mmc2-sdio-reset"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&twl_gpio 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&omap3_pmx_core { +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ +- OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ +- OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ +- OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ +- OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ +- OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ +- OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ +- OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ +- OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ +- OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ +- >; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- vmmc-supply = <&mmc2_sdio_reset>; +- non-removable; +- bus-width = <4>; +- cap-power-off-card; +-}; +- +-&dss { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = < +- &dss_dpi_pins_common +- &dss_dpi_pins_cm_t35x +- >; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-cm-t3730.dts b/scripts/dtc/include-prefixes/arm/omap3-cm-t3730.dts +deleted file mode 100644 +index 48e48b0c8190..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-cm-t3730.dts ++++ /dev/null +@@ -1,98 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Support for CompuLab CM-T3730 +- */ +-/dts-v1/; +- +-#include "omap36xx.dtsi" +-#include "omap3-cm-t3x30.dtsi" +- +-/ { +- model = "CompuLab CM-T3730"; +- compatible = "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +- +- wl12xx_vmmc2: wl12xx_vmmc2 { +- compatible = "regulator-fixed"; +- regulator-name = "vw1271"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wl12xx_gpio>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; /* gpio73 */ +- startup-delay-us = <20000>; +- enable-active-high; +- }; +- +- wl12xx_vaux2: wl12xx_vaux2 { +- compatible = "regulator-fixed"; +- regulator-name = "vwl1271_vaux2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vaux2>; +- }; +-}; +- +-&omap3_pmx_wkup { +- dss_dpi_pins_cm_t3730: pinmux_dss_dpi_pins_cm_t3730 { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a08, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ +- OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ +- OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ +- OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ +- OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ +- OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ +- >; +- }; +-}; +- +-&omap3_pmx_core { +- +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ +- OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ +- OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ +- OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ +- OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ +- OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ +- >; +- }; +- +- wl12xx_gpio: pinmux_wl12xx_gpio { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* dss_data3.gpio_73 */ +- OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 */ +- >; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- vmmc-supply = <&wl12xx_vmmc2>; +- vqmmc-supply = <&wl12xx_vaux2>; +- non-removable; +- bus-width = <4>; +- cap-power-off-card; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1271"; +- reg = <2>; +- interrupt-parent = <&gpio5>; +- interrupts = <8 IRQ_TYPE_EDGE_RISING>; /* gpio 136 */ +- ref-clock-frequency = <38400000>; +- }; +-}; +- +-&dss { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = < +- &dss_dpi_pins_common +- &dss_dpi_pins_cm_t3730 +- >; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-cm-t3x.dtsi b/scripts/dtc/include-prefixes/arm/omap3-cm-t3x.dtsi +deleted file mode 100644 +index e61b8a2bfb7d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-cm-t3x.dtsi ++++ /dev/null +@@ -1,326 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Common support for CompuLab CM-T3x CoMs +- */ +- +-/ { +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&green_led_pins>; +- ledb { +- label = "cm-t3x:green"; +- gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* gpio186 */ +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- /* HS USB Port 1 Power */ +- hsusb1_power: hsusb1_power_reg { +- compatible = "regulator-fixed"; +- regulator-name = "hsusb1_vbus"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <70000>; +- }; +- +- /* HS USB Port 2 Power */ +- hsusb2_power: hsusb2_power_reg { +- compatible = "regulator-fixed"; +- regulator-name = "hsusb2_vbus"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <70000>; +- }; +- +- /* HS USB Host PHY on PORT 1 */ +- hsusb1_phy: hsusb1_phy { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <&hsusb1_power>; +- #phy-cells = <0>; +- }; +- +- /* HS USB Host PHY on PORT 2 */ +- hsusb2_phy: hsusb2_phy { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <&hsusb2_power>; +- #phy-cells = <0>; +- }; +- +- ads7846reg: ads7846-reg { +- compatible = "regulator-fixed"; +- regulator-name = "ads7846-reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- tv0: svideo-connector { +- compatible = "svideo-connector"; +- label = "tv"; +- +- port { +- tv_connector_in: endpoint { +- remote-endpoint = <&venc_out>; +- }; +- }; +- }; +-}; +- +-&omap3_pmx_core { +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ +- OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ +- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ +- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ +- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ +- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ +- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ +- >; +- }; +- +- green_led_pins: pinmux_green_led_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */ +- >; +- }; +- +- dss_dpi_pins_common: pinmux_dss_dpi_pins_common { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ +- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ +- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ +- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ +- +- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ +- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ +- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ +- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ +- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ +- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ +- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ +- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ +- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ +- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ +- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ +- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ +- OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ +- OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ +- OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ +- OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ +- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ +- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ +- >; +- }; +- +- dss_dpi_pins_cm_t35x: pinmux_dss_dpi_pins_cm_t35x { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ +- OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ +- OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ +- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ +- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ +- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ +- >; +- }; +- +- ads7846_pins: pinmux_ads7846_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20ba, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ +- >; +- }; +- +- mcspi1_pins: pinmux_mcspi1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk */ +- OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo */ +- OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi */ +- OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0 */ +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ +- OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ +- >; +- }; +- +- mcbsp2_pins: pinmux_mcbsp2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ +- OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ +- OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ +- OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ +- >; +- }; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- bus-width = <4>; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- +- clock-frequency = <400000>; +- +- at24@50 { +- compatible = "atmel,24c02"; +- pagesize = <16>; +- reg = <0x50>; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +-}; +- +-&usbhshost { +- port1-mode = "ehci-phy"; +- port2-mode = "ehci-phy"; +-}; +- +-&usbhsehci { +- phys = <&hsusb1_phy &hsusb2_phy>; +-}; +- +-&mcspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcspi1_pins>; +- +- /* touch controller */ +- ads7846@0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ads7846_pins>; +- +- compatible = "ti,ads7846"; +- vcc-supply = <&ads7846reg>; +- +- reg = <0>; /* CS0 */ +- spi-max-frequency = <1500000>; +- +- interrupt-parent = <&gpio2>; +- interrupts = <25 0>; /* gpio_57 */ +- pendown-gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; +- +- ti,x-min = /bits/ 16 <0x0>; +- ti,x-max = /bits/ 16 <0x0fff>; +- ti,y-min = /bits/ 16 <0x0>; +- ti,y-max = /bits/ 16 <0x0fff>; +- +- ti,x-plate-ohms = /bits/ 16 <180>; +- ti,pressure-max = /bits/ 16 <255>; +- +- ti,debounce-max = /bits/ 16 <30>; +- ti,debounce-tol = /bits/ 16 <10>; +- ti,debounce-rep = /bits/ 16 <1>; +- +- wakeup-source; +- }; +-}; +- +-&venc { +- status = "okay"; +- +- port { +- venc_out: endpoint { +- remote-endpoint = <&tv_connector_in>; +- ti,channels = <2>; +- }; +- }; +-}; +- +-&mcbsp2 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp2_pins>; +-}; +- +-&gpmc { +- ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ +- +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- nand-bus-width = <8>; +- gpmc,device-width = <1>; +- ti,nand-ecc-opt = "sw"; +- +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <120>; +- gpmc,cs-wr-off-ns = <120>; +- +- gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <120>; +- gpmc,adv-wr-off-ns = <120>; +- +- gpmc,we-on-ns = <6>; +- gpmc,we-off-ns = <90>; +- +- gpmc,oe-on-ns = <6>; +- gpmc,oe-off-ns = <90>; +- +- gpmc,page-burst-access-ns = <6>; +- gpmc,access-ns = <72>; +- gpmc,cycle2cycle-delay-ns = <60>; +- +- gpmc,rd-cycle-ns = <120>; +- gpmc,wr-cycle-ns = <120>; +- gpmc,wr-access-ns = <186>; +- gpmc,wr-data-mux-bus-ns = <90>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "xloader"; +- reg = <0 0x80000>; +- }; +- partition@80000 { +- label = "uboot"; +- reg = <0x80000 0x1e0000>; +- }; +- partition@260000 { +- label = "uboot environment"; +- reg = <0x260000 0x40000>; +- }; +- partition@2a0000 { +- label = "linux"; +- reg = <0x2a0000 0x400000>; +- }; +- partition@6a0000 { +- label = "rootfs"; +- reg = <0x6a0000 0x1f880000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-cm-t3x30.dtsi b/scripts/dtc/include-prefixes/arm/omap3-cm-t3x30.dtsi +deleted file mode 100644 +index 5e8943539fcc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-cm-t3x30.dtsi ++++ /dev/null +@@ -1,131 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Common support for CompuLab CM-T3x30 CoMs +- */ +- +-#include "omap3-cm-t3x.dtsi" +- +-/ { +- cpus { +- cpu@0 { +- cpu0-supply = <&vcc>; +- }; +- }; +- +- sound { +- compatible = "ti,omap-twl4030"; +- ti,model = "cm-t35"; +- +- ti,mcbsp = <&mcbsp2>; +- }; +-}; +- +-&omap3_pmx_core { +- +- smsc1_pins: pinmux_smsc1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs5.gpmc_ncs5 */ +- OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 */ +- >; +- }; +- +- hsusb0_pins: pinmux_hsusb0_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ +- OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ +- OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ +- OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ +- OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data0.hsusb2_data0 */ +- OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ +- OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ +- OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data3 */ +- OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data4 */ +- OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data5 */ +- OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data6 */ +- OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ +- >; +- }; +-}; +- +-#include "omap-gpmc-smsc911x.dtsi" +- +-&gpmc { +- ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */ +- <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ +- +- smsc1: ethernet@gpmc { +- compatible = "smsc,lan9221", "smsc,lan9115"; +- pinctrl-names = "default"; +- pinctrl-0 = <&smsc1_pins>; +- interrupt-parent = <&gpio6>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- reg = <5 0 0xff>; +- }; +-}; +- +-&i2c1 { +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- interrupt-parent = <&intc>; +- +- twl_audio: audio { +- compatible = "ti,twl4030-audio"; +- codec { +- }; +- }; +- }; +-}; +- +-#include "twl4030.dtsi" +-#include "twl4030_omap3.dtsi" +-#include +- +-&venc { +- vdda-supply = <&vdac>; +-}; +- +-&mmc1 { +- vmmc-supply = <&vmmc1>; +-}; +- +-&twl_gpio { +- ti,use-leds; +- /* pullups: BIT(0) */ +- ti,pullups = <0x000001>; +-}; +- +-&twl_keypad { +- linux,keymap = < +- MATRIX_KEY(0x00, 0x01, KEY_A) +- MATRIX_KEY(0x00, 0x02, KEY_B) +- MATRIX_KEY(0x00, 0x03, KEY_LEFT) +- +- MATRIX_KEY(0x01, 0x01, KEY_UP) +- MATRIX_KEY(0x01, 0x02, KEY_ENTER) +- MATRIX_KEY(0x01, 0x03, KEY_DOWN) +- +- MATRIX_KEY(0x02, 0x01, KEY_RIGHT) +- MATRIX_KEY(0x02, 0x02, KEY_C) +- MATRIX_KEY(0x02, 0x03, KEY_D) +- >; +-}; +- +-&hsusb1_phy { +- reset-gpios = <&twl_gpio 6 GPIO_ACTIVE_LOW>; +-}; +- +-&hsusb2_phy { +- reset-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>; +-}; +- +-&usb_otg_hs { +- pinctrl-names = "default"; +- pinctrl-0 = <&hsusb0_pins>; +- interface-type = <0>; +- usb-phy = <&usb2_phy>; +- phys = <&usb2_phy>; +- phy-names = "usb2-phy"; +- mode = <3>; +- power = <50>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-cpu-thermal.dtsi b/scripts/dtc/include-prefixes/arm/omap3-cpu-thermal.dtsi +deleted file mode 100644 +index 1ed837859374..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-cpu-thermal.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * Device Tree Source for OMAP3 SoC CPU thermal +- * +- * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-#include +- +-cpu_thermal: cpu_thermal { +- polling-delay-passive = <250>; /* milliseconds */ +- polling-delay = <1000>; /* milliseconds */ +- coefficients = <0 20000>; +- +- /* sensor ID */ +- thermal-sensors = <&bandgap 0>; +- +- cpu_trips: trips { +- cpu_alert0: cpu_alert { +- temperature = <80000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu_crit: cpu_crit { +- temperature = <90000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- +- cpu_cooling_maps: cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- cooling-device = +- <&cpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-devkit8000-common.dtsi b/scripts/dtc/include-prefixes/arm/omap3-devkit8000-common.dtsi +deleted file mode 100644 +index 6883ccb45600..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-devkit8000-common.dtsi ++++ /dev/null +@@ -1,392 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Author: Anil Kumar +- */ +- +-#include +- +-#include "omap34xx.dtsi" +-/ { +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- heartbeat { +- label = "devkit8000::led1"; +- gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* 186 -> LED1 */ +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- mmc { +- label = "devkit8000::led2"; +- gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 -> LED2 */ +- default-state = "on"; +- linux,default-trigger = "none"; +- }; +- +- usr { +- label = "devkit8000::led3"; +- gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* 164 -> LED3 */ +- default-state = "on"; +- linux,default-trigger = "usr"; +- }; +- +- pmu_stat { +- label = "devkit8000::pmu_stat"; +- gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ +- }; +- }; +- +- sound { +- compatible = "ti,omap-twl4030"; +- ti,model = "devkit8000"; +- +- ti,mcbsp = <&mcbsp2>; +- ti,audio-routing = +- "Ext Spk", "PREDRIVEL", +- "Ext Spk", "PREDRIVER", +- "MAINMIC", "Main Mic", +- "Main Mic", "Mic Bias 1"; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- user { +- label = "user"; +- gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- tfp410: encoder0 { +- compatible = "ti,tfp410"; +- powerdown-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tfp410_in: endpoint { +- remote-endpoint = <&dpi_dvi_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- tfp410_out: endpoint { +- remote-endpoint = <&dvi_connector_in>; +- }; +- }; +- }; +- }; +- +- dvi0: connector0 { +- compatible = "dvi-connector"; +- label = "dvi"; +- +- digital; +- +- ddc-i2c-bus = <&i2c2>; +- +- port { +- dvi_connector_in: endpoint { +- remote-endpoint = <&tfp410_out>; +- }; +- }; +- }; +- +- tv0: connector1 { +- compatible = "svideo-connector"; +- label = "tv"; +- +- port { +- tv_connector_in: endpoint { +- remote-endpoint = <&venc_out>; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <2600000>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- +- twl_audio: audio { +- compatible = "ti,twl4030-audio"; +- codec { +- }; +- }; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +-}; +- +-&i2c3 { +- status = "disabled"; +-}; +- +-#include "twl4030.dtsi" +-#include "twl4030_omap3.dtsi" +- +-&mmc1 { +- vmmc-supply = <&vmmc1>; +- vqmmc-supply = <&vsim>; +- bus-width = <8>; +-}; +- +-&mmc2 { +- status = "disabled"; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-/* Unusable as clockevent because if unreliable oscillator, allow to idle */ +-&timer1_target { +- /delete-property/ti,no-reset-on-init; +- /delete-property/ti,no-idle; +- timer@0 { +- /delete-property/ti,timer-alwon; +- }; +-}; +- +-/* Preferred timer for clockevent */ +-&timer12_target { +- ti,no-reset-on-init; +- ti,no-idle; +- timer@0 { +- /* Always clocked by secure_32k_fck */ +- }; +-}; +- +-&twl_gpio { +- ti,use-leds; +- /* +- * pulldowns: +- * BIT(1), BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) +- * BIT(15), BIT(16), BIT(17) +- */ +- ti,pulldowns = <0x03a1c6>; +-}; +- +-&twl_keypad { +- linux,keymap = ; +-}; +- +-&wdt2 { +- status = "disabled"; +-}; +- +-&mcbsp2 { +- status = "okay"; +-}; +- +-&gpmc { +- ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ +- 6 0 0x2c000000 0x1000000>; /* CS6: 16MB for DM9000 */ +- +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- nand-bus-width = <16>; +- gpmc,device-width = <2>; +- ti,nand-ecc-opt = "sw"; +- +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- x-loader@0 { +- label = "X-Loader"; +- reg = <0 0x80000>; +- }; +- +- bootloaders@80000 { +- label = "U-Boot"; +- reg = <0x80000 0x1e0000>; +- }; +- +- bootloaders_env@260000 { +- label = "U-Boot Env"; +- reg = <0x260000 0x20000>; +- }; +- +- kernel@280000 { +- label = "Kernel"; +- reg = <0x280000 0x400000>; +- }; +- +- filesystem@680000 { +- label = "File System"; +- reg = <0x680000 0xf980000>; +- }; +- }; +- +- ethernet@6,0 { +- compatible = "davicom,dm9000"; +- reg = <6 0x000 2 +- 6 0x400 2>; /* CS6, offset 0 and 0x400, IO size 2 */ +- bank-width = <2>; +- interrupt-parent = <&gpio1>; +- interrupts = <25 IRQ_TYPE_LEVEL_LOW>; +- davicom,no-eeprom; +- +- gpmc,mux-add-data = <0>; +- gpmc,device-width = <1>; +- gpmc,wait-pin = <0>; +- gpmc,cycle2cycle-samecsen = <1>; +- gpmc,cycle2cycle-diffcsen = <1>; +- +- gpmc,cs-on-ns = <6>; +- gpmc,cs-rd-off-ns = <180>; +- gpmc,cs-wr-off-ns = <180>; +- gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <18>; +- gpmc,adv-wr-off-ns = <48>; +- gpmc,oe-on-ns = <54>; +- gpmc,oe-off-ns = <168>; +- gpmc,we-on-ns = <54>; +- gpmc,we-off-ns = <168>; +- gpmc,rd-cycle-ns = <186>; +- gpmc,wr-cycle-ns = <186>; +- gpmc,access-ns = <144>; +- gpmc,page-burst-access-ns = <24>; +- gpmc,bus-turnaround-ns = <90>; +- gpmc,cycle2cycle-delay-ns = <90>; +- gpmc,wait-monitoring-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-data-mux-bus-ns = <0>; +- gpmc,wr-access-ns = <0>; +- }; +-}; +- +-&omap3_pmx_core { +- dss_dpi_pins: pinmux_dss_dpi_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ +- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ +- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ +- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ +- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ +- OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ +- OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ +- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ +- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ +- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ +- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ +- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ +- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ +- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ +- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ +- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ +- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ +- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ +- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ +- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ +- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ +- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ +- OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ +- OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ +- OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ +- OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ +- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ +- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ +- >; +- }; +-}; +- +-&vpll1 { +- /* Needed for DSS */ +- regulator-name = "vdds_dsi"; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +-}; +- +-&dss { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_dpi_pins>; +- +- vdds_dsi-supply = <&vpll1>; +- vdda_dac-supply = <&vdac>; +- +- port { +- #address-cells = <1>; +- #size-cells = <0>; +- dpi_dvi_out: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&tfp410_in>; +- data-lines = <24>; +- }; +- +- endpoint@1 { +- reg = <1>; +- }; +- }; +-}; +- +-&venc { +- status = "okay"; +- +- vdda-supply = <&vdac>; +- +- port { +- venc_out: endpoint { +- remote-endpoint = <&tv_connector_in>; +- ti,channels = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-devkit8000-lcd-common.dtsi b/scripts/dtc/include-prefixes/arm/omap3-devkit8000-lcd-common.dtsi +deleted file mode 100644 +index 3decc2d78a6c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-devkit8000-lcd-common.dtsi ++++ /dev/null +@@ -1,73 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Author: Anthoine Bourgeois +- */ +- +-#include "omap3-devkit8000-common.dtsi" +-/ { +- aliases { +- display0 = &lcd0; +- display1 = &dvi0; +- display2 = &tv0; +- }; +- +- lcd0: display { +- compatible = "panel-dpi"; +- label = "lcd"; +- +- enable-gpios = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; +- +- port { +- lcd_in: endpoint { +- remote-endpoint = <&dpi_lcd_out>; +- }; +- }; +- }; +-}; +- +-&dss { +- port { +- #address-cells = <1>; +- #size-cells = <0>; +- dpi_lcd_out: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&lcd_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-&vio { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +-}; +- +-&mcspi2 { +- +- /* touch controller */ +- ads7846@0 { +- compatible = "ti,ads7846"; +- vcc-supply = <&vio>; +- +- reg = <0>; /* CS0 */ +- spi-max-frequency = <1500000>; +- +- interrupt-parent = <&gpio1>; +- interrupts = <27 0>; /* gpio_27 */ +- pendown-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; +- +- ti,x-min = /bits/ 16 <0x0>; +- ti,x-max = /bits/ 16 <0x0fff>; +- ti,y-min = /bits/ 16 <0x0>; +- ti,y-max = /bits/ 16 <0x0fff>; +- ti,x-plate-ohms = /bits/ 16 <180>; +- ti,pressure-max = /bits/ 16 <255>; +- ti,debounce-max = /bits/ 16 <10>; +- ti,debounce-tol = /bits/ 16 <5>; +- ti,debounce-rep = /bits/ 16 <1>; +- ti,keep-vref-on = <1>; +- ti,settle-delay-usec = /bits/ 16 <150>; +- +- wakeup-source; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-devkit8000-lcd43.dts b/scripts/dtc/include-prefixes/arm/omap3-devkit8000-lcd43.dts +deleted file mode 100644 +index afed85078ad8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-devkit8000-lcd43.dts ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Author: Anthoine Bourgeois +- */ +-/dts-v1/; +- +-/* +- * 4.3'' LCD panel sold with devkit8000 board +- */ +- +-#include "omap3-devkit8000-lcd-common.dtsi" +-/ { +- model = "TimLL OMAP3 Devkit8000 with 4.3'' LCD panel"; +- compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3"; +- +- lcd0: display { +- panel-timing { +- clock-frequency = <10164705>; +- hactive = <480>; +- vactive = <272>; +- hfront-porch = <2>; +- hback-porch = <2>; +- hsync-len = <41>; +- vback-porch = <2>; +- vfront-porch = <2>; +- vsync-len = <10>; +- +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-devkit8000-lcd70.dts b/scripts/dtc/include-prefixes/arm/omap3-devkit8000-lcd70.dts +deleted file mode 100644 +index 07c51a105c0d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-devkit8000-lcd70.dts ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Author: Anthoine Bourgeois +- */ +-/dts-v1/; +- +-/* +- * 7.0'' LCD panel sold with some devkit8000 board +- */ +- +-#include "omap3-devkit8000-lcd-common.dtsi" +-/ { +- model = "TimLL OMAP3 Devkit8000 with 7.0'' LCD panel"; +- compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3"; +- +- lcd0: display { +- panel-timing { +- clock-frequency = <40000000>; +- hactive = <800>; +- vactive = <480>; +- hfront-porch = <1>; +- hback-porch = <1>; +- hsync-len = <48>; +- vback-porch = <25>; +- vfront-porch = <12>; +- vsync-len = <3>; +- +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-devkit8000.dts b/scripts/dtc/include-prefixes/arm/omap3-devkit8000.dts +deleted file mode 100644 +index 162d0726b008..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-devkit8000.dts ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Author: Anthoine Bourgeois +- */ +-/dts-v1/; +- +-#include "omap3-devkit8000-common.dtsi" +-/ { +- model = "TimLL OMAP3 Devkit8000"; +- compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3"; +- +- aliases { +- display1 = &dvi0; +- display2 = &tv0; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-echo.dts b/scripts/dtc/include-prefixes/arm/omap3-echo.dts +deleted file mode 100644 +index 8f02ff5e7da6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-echo.dts ++++ /dev/null +@@ -1,724 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2019 André Hentschel +- */ +-/dts-v1/; +- +-#include "dm3725.dtsi" +- +-#include +-#include +- +-/ { +- model = "Amazon Echo (first generation)"; +- compatible = "amazon,omap3-echo", "ti,omap3630", "ti,omap3"; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&vdd1_reg>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0xc600000>; /* 198 MB */ +- }; +- +- vcc5v: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcc3v3: fixedregulator1 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcc1v8: fixedregulator2 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; +- post-power-on-delay-ms = <40>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&button_pins>; +- +- mute-button { +- label = "mute"; +- linux,code = ; +- gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; /* GPIO_70 */ +- wakeup-source; +- }; +- +- help-button { +- label = "help"; +- linux,code = ; +- gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; /* GPIO_72 */ +- wakeup-source; +- }; +- }; +- +- rotary: rotary-encoder { +- compatible = "rotary-encoder"; +- gpios = < +- &gpio3 5 GPIO_ACTIVE_HIGH /* GPIO_69 */ +- &gpio3 12 GPIO_ACTIVE_HIGH /* GPIO_76 */ +- >; +- linux,axis = ; +- rotary-encoder,relative-axis; +- }; +- +- speaker_amp: speaker-amplifier { +- compatible = "simple-audio-amplifier"; +- enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* gpio_129 */ +- sound-name-prefix = "Speaker Amp"; +- VCC-supply = <&vcc1v8>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "Misto Speaker"; +- simple-audio-card,widgets = +- "Speaker", "Speaker"; +- simple-audio-card,routing = +- "Speaker Amp INL", "HPL", +- "Speaker Amp INR", "HPR", +- "Speaker", "Speaker Amp OUTL", +- "Speaker", "Speaker Amp OUTR"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sound_master>; +- simple-audio-card,frame-master = <&sound_master>; +- simple-audio-card,aux-devs = <&speaker_amp>; +- +- simple-audio-card,cpu { +- sound-dai = <&mcbsp2>; +- }; +- +- sound_master: simple-audio-card,codec { +- sound-dai = <&codec0>; +- system-clock-frequency = <19200000>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- +- tps: tps@2d { +- reg = <0x2d>; +- }; +-}; +- +-&mcbsp2 { +- status = "okay"; +- #sound-dai-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp2_pins>; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- +- lp5523A: lp5523A@32 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "national,lp5523"; +- label = "q1"; +- reg = <0x32>; +- clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ +- enable-gpio = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* GPIO_109 */ +- +- multi-led@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0>; +- color = ; +- +- led@0 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x0>; +- color = ; +- }; +- +- led@1 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x1>; +- color = ; +- }; +- +- led@6 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x6>; +- color = ; +- }; +- }; +- multi-led@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x1>; +- color = ; +- +- led@2 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x2>; +- color = ; +- }; +- +- led@3 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x3>; +- color = ; +- }; +- +- led@7 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x7>; +- color = ; +- }; +- }; +- multi-led@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; +- color = ; +- +- led@4 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x4>; +- color = ; +- }; +- +- led@5 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x5>; +- color = ; +- }; +- +- led@8 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x8>; +- color = ; +- }; +- }; +- }; +- +- lp5523B: lp5523B@33 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "national,lp5523"; +- label = "q3"; +- reg = <0x33>; +- clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ +- +- multi-led@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0>; +- color = ; +- +- led@0 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x0>; +- color = ; +- }; +- +- led@1 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x1>; +- color = ; +- }; +- +- led@6 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x6>; +- color = ; +- }; +- }; +- multi-led@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x1>; +- color = ; +- +- led@2 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x2>; +- color = ; +- }; +- +- led@3 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x3>; +- color = ; +- }; +- +- led@7 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x7>; +- color = ; +- }; +- }; +- multi-led@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; +- color = ; +- +- led@4 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x4>; +- color = ; +- }; +- +- led@5 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x5>; +- color = ; +- }; +- +- led@8 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x8>; +- color = ; +- }; +- }; +- }; +- +- lp5523C: lp5523C@34 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "national,lp5523"; +- label = "q4"; +- reg = <0x34>; +- clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ +- +- multi-led@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0>; +- color = ; +- +- led@0 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x0>; +- color = ; +- }; +- +- led@1 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x1>; +- color = ; +- }; +- +- led@6 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x6>; +- color = ; +- }; +- }; +- multi-led@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x1>; +- color = ; +- +- led@2 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x2>; +- color = ; +- }; +- +- led@3 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x3>; +- color = ; +- }; +- +- led@7 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x7>; +- color = ; +- }; +- }; +- multi-led@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; +- color = ; +- +- led@4 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x4>; +- color = ; +- }; +- +- led@5 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x5>; +- color = ; +- }; +- +- led@8 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x8>; +- color = ; +- }; +- }; +- }; +- +- lp5523D: lp552D@35 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "national,lp5523"; +- label = "q2"; +- reg = <0x35>; +- clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ +- +- multi-led@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0>; +- color = ; +- +- led@0 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x0>; +- color = ; +- }; +- +- led@1 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x1>; +- color = ; +- }; +- +- led@6 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x6>; +- color = ; +- }; +- }; +- multi-led@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x1>; +- color = ; +- +- led@2 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x2>; +- color = ; +- }; +- +- led@3 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x3>; +- color = ; +- }; +- +- led@7 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x7>; +- color = ; +- }; +- }; +- multi-led@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; +- color = ; +- +- led@4 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x4>; +- color = ; +- }; +- +- led@5 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x5>; +- color = ; +- }; +- +- led@8 { +- led-cur = /bits/ 8 <12>; +- max-cur = /bits/ 8 <15>; +- reg = <0x8>; +- color = ; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +- +- codec0: codec@18 { +- #sound-dai-cells = <0>; +- compatible = "ti,tlv320aic32x4"; +- reg = <0x18>; +- clocks = <&sys_clkout1>; +- clock-names = "mclk"; +- ldoin-supply = <&vcc1v8>; +- iov-supply = <&vcc1v8>; +- reset-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; /* gpio_74 */ +- }; +-}; +- +- +-#include "tps65910.dtsi" +- +-&omap3_pmx_core { +- tps_pins: pinmux_tps_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | PIN_OFF_INPUT_PULLUP | PIN_OFF_OUTPUT_LOW | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */ +- >; +- }; +- +- button_pins: pinmux_button_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20dc, PIN_INPUT | MUX_MODE4) /* dss_data0.gpio_70 */ +- OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* dss_data2.gpio_72 */ +- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* dss_data4.gpio_74 */ +- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data15.gpio_85 */ +- OMAP3_CORE1_IOPAD(0x2a1a, PIN_OUTPUT | MUX_MODE0) /* sys_clkout1.sys_clkout1 */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ +- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ +- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ +- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ +- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ +- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ +- >; +- }; +- +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ +- OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ +- OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ +- OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ +- OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ +- OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ +- OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */ +- OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */ +- OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */ +- OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */ +- >; +- }; +- +- mcbsp2_pins: pinmux_mcbsp2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ +- OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ +- OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */ +- OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */ +- >; +- }; +-}; +- +-&omap3_pmx_core2 { +- mmc3_pins: pinmux_mmc3_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ +- OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ +- OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ +- OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ +- OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ +- OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ +- >; +- }; +-}; +- +-&mmc1 { +- status = "okay"; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <&vmmc_reg>; +-}; +- +-&mmc2 { +- status = "okay"; +- bus-width = <8>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- vmmc-supply = <&vmmc_reg>; +-}; +- +-&mmc3 { +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc3_pins>; +- non-removable; +- disable-wp; +- mmc-pwrseq = <&sdio_pwrseq>; +- vmmc-supply = <&vcc3v3>; +- vqmmc-supply = <&vcc1v8>; +- atheros@0 { +- compatible = "atheros,ath6kl"; +- reg = <0>; +- bus-width = <4>; +- }; +-}; +- +-&tps { +- pinctrl-names = "default"; +- pinctrl-0 = <&tps_pins>; +- +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- interrupt-parent = <&intc>; +- +- ti,en-ck32k-xtal; +- ti,system-power-controller; +- +- vcc1-supply = <&vcc5v>; +- vcc2-supply = <&vcc5v>; +- vcc3-supply = <&vcc5v>; +- vcc4-supply = <&vcc5v>; +- vcc5-supply = <&vcc5v>; +- vcc6-supply = <&vcc5v>; +- vcc7-supply = <&vcc5v>; +- vccio-supply = <&vcc5v>; +- +- regulators { +- +- vio_reg: regulator@1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vdd1_reg: regulator@2 { +- regulator-name = "vdd_mpu"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd2_reg: regulator@3 { +- regulator-name = "vdd_dsp"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- +- vdd3_reg: regulator@4 { +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- vdig1_reg: regulator@5 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <2700000>; +- regulator-always-on; +- }; +- +- vdig2_reg: regulator@6 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vpll_reg: regulator@7 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- vdac_reg: regulator@8 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vaux1_reg: regulator@9 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- }; +- +- vaux2_reg: regulator@10 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vaux33_reg: regulator@11 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vmmc_reg: regulator@12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-evm-37xx.dts b/scripts/dtc/include-prefixes/arm/omap3-evm-37xx.dts +deleted file mode 100644 +index c9332195d096..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-evm-37xx.dts ++++ /dev/null +@@ -1,107 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "omap36xx.dtsi" +-#include "omap3-evm-common.dtsi" +-#include "omap3-evm-processor-common.dtsi" +- +-/ { +- model = "TI OMAP37XX EVM (TMDSEVM3730)"; +- compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3"; +-}; +- +-&omap3_pmx_core2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hsusb2_2_pins>; +- +- ehci_phy_pins: pinmux_ehci_phy_pins { +- pinctrl-single,pins = < +- +- /* EHCI PHY reset GPIO etk_d7.gpio_21 */ +- OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) +- +- /* EHCI VBUS etk_d8.gpio_22 */ +- OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) +- >; +- }; +- +- /* Used by OHCI and EHCI. OHCI won't work without external phy */ +- hsusb2_2_pins: pinmux_hsusb2_2_pins { +- pinctrl-single,pins = < +- +- /* etk_d10.hsusb2_clk */ +- OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) +- +- /* etk_d11.hsusb2_stp */ +- OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) +- +- /* etk_d12.hsusb2_dir */ +- OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) +- +- /* etk_d13.hsusb2_nxt */ +- OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) +- +- /* etk_d14.hsusb2_data0 */ +- OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) +- +- /* etk_d15.hsusb2_data1 */ +- OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) +- >; +- }; +-}; +- +-&gpmc { +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- linux,mtd-name= "hynix,h8kds0un0mer-4em"; +- nand-bus-width = <16>; +- gpmc,device-width = <2>; +- ti,nand-ecc-opt = "bch8"; +- +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "X-Loader"; +- reg = <0 0x80000>; +- }; +- partition@80000 { +- label = "U-Boot"; +- reg = <0x80000 0x1c0000>; +- }; +- partition@1c0000 { +- label = "Environment"; +- reg = <0x240000 0x40000>; +- }; +- partition@280000 { +- label = "Kernel"; +- reg = <0x280000 0x500000>; +- }; +- partition@780000 { +- label = "Filesystem"; +- reg = <0x780000 0x1f880000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-evm-common.dtsi b/scripts/dtc/include-prefixes/arm/omap3-evm-common.dtsi +deleted file mode 100644 +index 17c89df6ce6b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-evm-common.dtsi ++++ /dev/null +@@ -1,198 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Common support for omap3 EVM boards +- */ +- +-#include +-#include "omap-gpmc-smsc911x.dtsi" +- +-/ { +- cpus { +- cpu@0 { +- cpu0-supply = <&vcc>; +- }; +- }; +- +- /* HS USB Port 2 Power */ +- hsusb2_power: hsusb2_power_reg { +- compatible = "regulator-fixed"; +- regulator-name = "hsusb2_vbus"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; /* gpio_22 */ +- startup-delay-us = <70000>; +- enable-active-high; +- }; +- +- /* HS USB Host PHY on PORT 2 */ +- hsusb2_phy: hsusb2_phy { +- compatible = "usb-nop-xceiv"; +- reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ +- vcc-supply = <&hsusb2_power>; +- #phy-cells = <0>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- ledb { +- label = "omap3evm::ledb"; +- gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ +- linux,default-trigger = "default-on"; +- }; +- }; +- +- wl12xx_vmmc: wl12xx_vmmc { +- compatible = "regulator-fixed"; +- regulator-name = "vwl1271"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* gpio150 */ +- startup-delay-us = <70000>; +- enable-active-high; +- vin-supply = <&vmmc2>; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <2600000>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- interrupt-parent = <&intc>; +- }; +-}; +- +-#include "twl4030.dtsi" +-#include "twl4030_omap3.dtsi" +-#include "omap3-panel-sharp-ls037v7dw01.dtsi" +- +-&backlight0 { +- gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; +-}; +- +-&twl { +- twl_power: power { +- compatible = "ti,twl4030-power-omap3-evm", "ti,twl4030-power-idle"; +- ti,use_poweroff; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +- +- /* +- * TVP5146 Video decoder-in for analog input support. +- */ +- tvp5146@5c { +- compatible = "ti,tvp5146m2"; +- reg = <0x5c>; +- }; +-}; +- +-&lcd_3v3 { +- gpio = <&gpio5 25 GPIO_ACTIVE_LOW>; /* gpio153 */ +-}; +- +-&lcd0 { +- enable-gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>; /* gpio152, lcd INI */ +- reset-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd RESB */ +- mode-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH /* gpio154, lcd MO */ +- &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */ +- &gpio1 3 GPIO_ACTIVE_HIGH>; /* gpio3, lcd UD */ +-}; +- +-&mcspi1 { +- tsc2046@0 { +- interrupt-parent = <&gpio6>; +- interrupts = <15 0>; /* gpio175 */ +- pendown-gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&mmc1 { +- interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; +- vmmc-supply = <&vmmc1>; +- vqmmc-supply = <&vsim>; +- bus-width = <8>; +-}; +- +-&mmc2 { +- interrupts-extended = <&intc 86 &omap3_pmx_core 0x12e>; +- vmmc-supply = <&wl12xx_vmmc>; +- non-removable; +- bus-width = <4>; +- cap-power-off-card; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1271"; +- reg = <2>; +- /* gpio_149 with uart1_rts pad as wakeirq */ +- interrupts-extended = <&gpio5 21 IRQ_TYPE_EDGE_RISING>, +- <&omap3_pmx_core 0x14e>; +- interrupt-names = "irq", "wakeup"; +- ref-clock-frequency = <38400000>; +- }; +-}; +- +-&twl_gpio { +- ti,use-leds; +-}; +- +-&twl_keypad { +- linux,keymap = < +- MATRIX_KEY(2, 2, KEY_1) +- MATRIX_KEY(1, 1, KEY_2) +- MATRIX_KEY(0, 0, KEY_3) +- MATRIX_KEY(3, 2, KEY_4) +- MATRIX_KEY(2, 1, KEY_5) +- MATRIX_KEY(1, 0, KEY_6) +- MATRIX_KEY(1, 3, KEY_7) +- MATRIX_KEY(3, 1, KEY_8) +- MATRIX_KEY(2, 0, KEY_9) +- MATRIX_KEY(2, 3, KEY_KPASTERISK) +- MATRIX_KEY(0, 2, KEY_0) +- MATRIX_KEY(3, 0, KEY_KPDOT) +- /* s4 not wired */ +- MATRIX_KEY(1, 2, KEY_BACKSPACE) +- MATRIX_KEY(0, 1, KEY_ENTER) +- >; +-}; +- +-&usbhshost { +- port2-mode = "ehci-phy"; +-}; +- +-&usbhsehci { +- phys = <0 &hsusb2_phy>; +-}; +- +-&usb_otg_hs { +- interface-type = <0>; +- usb-phy = <&usb2_phy>; +- phys = <&usb2_phy>; +- phy-names = "usb2-phy"; +- mode = <3>; +- power = <50>; +-}; +- +-&gpmc { +- ethernet@gpmc { +- interrupt-parent = <&gpio6>; +- interrupts = <16 8>; +- reg = <5 0 0xff>; +- }; +-}; +- +-&vaux2 { +- regulator-name = "usb_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-evm-processor-common.dtsi b/scripts/dtc/include-prefixes/arm/omap3-evm-processor-common.dtsi +deleted file mode 100644 +index e6ba30a21166..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-evm-processor-common.dtsi ++++ /dev/null +@@ -1,224 +0,0 @@ +-/* +- * Common support for omap3 EVM 35xx/37xx processor modules +- */ +- +-/ { +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +- +- wl12xx_vmmc: wl12xx_vmmc { +- pinctrl-names = "default"; +- pinctrl-0 = <&wl12xx_gpio>; +- }; +-}; +- +-&dss { +- vdds_dsi-supply = <&vpll2>; +- vdda_video-supply = <&lcd_3v3>; +- pinctrl-names = "default"; +- pinctrl-0 = < +- &dss_dpi_pins1 +- &dss_dpi_pins2 +- >; +-}; +- +-&hsusb2_phy { +- pinctrl-names = "default"; +- pinctrl-0 = <&ehci_phy_pins>; +-}; +- +-&omap3_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>; +- +- dss_dpi_pins1: pinmux_dss_dpi_pins2 { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ +- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ +- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ +- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ +- +- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ +- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ +- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ +- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ +- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ +- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ +- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ +- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ +- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ +- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ +- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ +- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ +- +- OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ +- OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ +- OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ +- OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ +- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ +- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ +- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ +- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ +- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ +- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ +- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ +- OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ +- OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ +- OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ +- OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ +- >; +- }; +- +- /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */ +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ +- OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ +- OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ +- OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ +- OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ +- OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ +- OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ +- OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ +- OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ +- OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ +- >; +- }; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ +- OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ +- >; +- }; +- +- /* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */ +- on_board_gpio_61: pinmux_ehci_port_select_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) +- >; +- }; +- +- /* Used by OHCI and EHCI. OHCI won't work without external phy */ +- hsusb2_pins: pinmux_hsusb2_pins { +- pinctrl-single,pins = < +- +- /* mcspi1_cs3.hsusb2_data2 */ +- OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) +- +- /* mcspi2_clk.hsusb2_data7 */ +- OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) +- +- /* mcspi2_simo.hsusb2_data4 */ +- OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) +- +- /* mcspi2_somi.hsusb2_data5 */ +- OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) +- +- /* mcspi2_cs0.hsusb2_data6 */ +- OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) +- +- /* mcspi2_cs1.hsusb2_data3 */ +- OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) +- >; +- }; +- +- /* +- * Note that gpio_150 pulled high with internal pull to prevent wlcore +- * reset on return from off mode in idle. +- */ +- wl12xx_gpio: pinmux_wl12xx_gpio { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_cts.gpio_150 */ +- OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ +- >; +- }; +- +- smsc911x_pins: pinmux_smsc911x_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ +- >; +- }; +-}; +- +-&omap3_pmx_wkup { +- dss_dpi_pins2: pinmux_dss_dpi_pins1 { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ +- OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ +- OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ +- OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ +- OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ +- OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ +- >; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-&uart1 { +- interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; +-}; +- +-&uart2 { +- interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; +-}; +- +-&uart3 { +- interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +-}; +- +-/* +- * GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface +- * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V. +- */ +-&gpio2 { +- en-usb2-port-hog { +- gpio-hog; +- gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */ +- output-low; +- line-name = "enable usb2 port"; +- }; +-}; +- +-/* T2_GPIO_2 low to route GPIO_61 to on-board devices */ +-&twl_gpio { +- en_on_board_gpio_61 { +- gpio-hog; +- gpios = <2 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "en_hsusb2_clk"; +- }; +-}; +- +-&gpmc { +- ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */ +- <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for LAN9220 */ +- +- ethernet@gpmc { +- pinctrl-names = "default"; +- pinctrl-0 = <&smsc911x_pins>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-evm.dts b/scripts/dtc/include-prefixes/arm/omap3-evm.dts +deleted file mode 100644 +index 5cc0cf7cd16c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-evm.dts ++++ /dev/null +@@ -1,86 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "omap34xx.dtsi" +-#include "omap3-evm-common.dtsi" +-#include "omap3-evm-processor-common.dtsi" +- +-/ { +- model = "TI OMAP35XX EVM (TMDSEVM3530)"; +- compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3"; +-}; +- +-&omap3_pmx_core2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hsusb2_2_pins>; +- +- ehci_phy_pins: pinmux_ehci_phy_pins { +- pinctrl-single,pins = < +- +- /* EHCI PHY reset GPIO etk_d7.gpio_21 */ +- OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) +- +- /* EHCI VBUS etk_d8.gpio_22 */ +- OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) +- >; +- }; +- +- /* Used by OHCI and EHCI. OHCI won't work without external phy */ +- hsusb2_2_pins: pinmux_hsusb2_2_pins { +- pinctrl-single,pins = < +- +- /* etk_d10.hsusb2_clk */ +- OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) +- +- /* etk_d11.hsusb2_stp */ +- OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) +- +- /* etk_d12.hsusb2_dir */ +- OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) +- +- /* etk_d13.hsusb2_nxt */ +- OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) +- +- /* etk_d14.hsusb2_data0 */ +- OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) +- +- /* etk_d15.hsusb2_data1 */ +- OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) +- >; +- }; +-}; +- +-&gpmc { +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- linux,mtd-name= "micron,mt29f2g16abdhc"; +- nand-bus-width = <16>; +- gpmc,device-width = <2>; +- ti,nand-ecc-opt = "bch8"; +- +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-gta04.dtsi b/scripts/dtc/include-prefixes/arm/omap3-gta04.dtsi +deleted file mode 100644 +index 23ab27fe4ee5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-gta04.dtsi ++++ /dev/null +@@ -1,873 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013 Marek Belisko +- * +- * Based on omap3-beagle-xm.dts +- */ +-/dts-v1/; +- +-#include "omap36xx.dtsi" +-#include +- +-/ { +- model = "OMAP3 GTA04"; +- compatible = "ti,omap3-gta04", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&vcc>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512 MB */ +- }; +- +- chosen { +- stdout-path = &uart3; +- }; +- +- aliases { +- display0 = &lcd; +- display1 = &tv0; +- }; +- +- ldo_3v3: fixedregulator { +- compatible = "regulator-fixed"; +- regulator-name = "ldo_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- /* fixed 26MHz oscillator */ +- hfclk_26m: oscillator { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- aux-button { +- label = "aux"; +- linux,code = ; +- gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- wakeup-source; +- }; +- }; +- +- antenna-detect { +- compatible = "gpio-keys"; +- +- gps_antenna_button: gps-antenna-button { +- label = "GPS_EXT_ANT"; +- linux,input-type = ; +- linux,code = ; +- gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* GPIO144 */ +- interrupt-parent = <&gpio5>; +- interrupts = <16 IRQ_TYPE_EDGE_BOTH>; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- sound { +- compatible = "ti,omap-twl4030"; +- ti,model = "gta04"; +- +- ti,mcbsp = <&mcbsp2>; +- }; +- +- /* GSM audio */ +- sound_telephony { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "GTA04 voice"; +- simple-audio-card,bitclock-master = <&telephony_link_master>; +- simple-audio-card,frame-master = <&telephony_link_master>; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-inversion; +- simple-audio-card,frame-inversion; +- simple-audio-card,cpu { +- sound-dai = <&mcbsp4>; +- }; +- +- telephony_link_master: simple-audio-card,codec { +- sound-dai = <>m601_codec>; +- }; +- }; +- +- gtm601_codec: gsm_codec { +- compatible = "option,gtm601"; +- #sound-dai-cells = <0>; +- }; +- +- spi_lcd: spi_lcd { +- compatible = "spi-gpio"; +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_gpio_pins>; +- +- gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>; +- gpio-miso = <&gpio1 18 GPIO_ACTIVE_HIGH>; +- gpio-mosi = <&gpio1 20 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; +- num-chipselects = <1>; +- +- /* lcd panel */ +- lcd: td028ttec1@0 { +- compatible = "tpo,td028ttec1"; +- reg = <0>; +- spi-max-frequency = <100000>; +- spi-cpol; +- spi-cpha; +- +- backlight= <&backlight>; +- label = "lcd"; +- port { +- lcd_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- }; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm11 0 12000000 0>; +- pwm-names = "backlight"; +- brightness-levels = <0 11 20 30 40 50 60 70 80 90 100>; +- default-brightness-level = <9>; /* => 90 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&backlight_pins>; +- }; +- +- pwm11: dmtimer-pwm { +- compatible = "ti,omap-dmtimer-pwm"; +- ti,timers = <&timer11>; +- #pwm-cells = <3>; +- ti,clock-source = <0x01>; +- }; +- +- hsusb2_phy: hsusb2_phy { +- compatible = "usb-nop-xceiv"; +- reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; +- #phy-cells = <0>; +- }; +- +- tv0: connector { +- compatible = "composite-video-connector"; +- label = "tv"; +- +- port { +- tv_connector_in: endpoint { +- remote-endpoint = <&opa_out>; +- }; +- }; +- }; +- +- tv_amp: opa362 { +- compatible = "ti,opa362"; +- enable-gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; /* GPIO_23 to enable video out amplifier */ +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- opa_in: endpoint { +- remote-endpoint = <&venc_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- opa_out: endpoint { +- remote-endpoint = <&tv_connector_in>; +- }; +- }; +- }; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&tca6507 0 GPIO_ACTIVE_LOW>; /* W2CBW003 reset through tca6507 */ +- }; +- +- /* devconf0 setup for mcbsp1 clock pins */ +- pinmux_mcbsp1@48002274 { +- compatible = "pinctrl-single"; +- reg = <0x48002274 4>; /* CONTROL_DEVCONF0 */ +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-single,bit-per-mux; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0x7>; /* MCBSP1 CLK pinmux */ +- #pinctrl-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp1_devconf0_pins>; +- mcbsp1_devconf0_pins: pinmux_mcbsp1_devconf0_pins { +- /* offset bits mask */ +- pinctrl-single,bits = <0x00 0x08 0x1c>; /* set MCBSP1_CLKR */ +- }; +- }; +- +- /* devconf1 setup for tvout pins */ +- pinmux_tv_out@480022d8 { +- compatible = "pinctrl-single"; +- reg = <0x480022d8 4>; /* CONTROL_DEVCONF1 */ +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-single,bit-per-mux; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0x81>; /* TV out pin control */ +- #pinctrl-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tv_acbias_devconf1_pins>; +- tv_acbias_devconf1_pins: pinmux_tv_acbias_devconf1_pins { +- /* offset bits mask */ +- pinctrl-single,bits = <0x00 0x40800 0x40800>; /* set TVOUTBYPASS and TVOUTACEN */ +- }; +- }; +-}; +- +-&omap3_pmx_wkup { +- gpio1_pins: pinmux_gpio1_pins { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ +- OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_clkout.gpio_10 */ +- >; +- }; +-}; +- +-&omap3_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &hsusb2_pins +- >; +- +- hsusb2_pins: pinmux_hsusb2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ +- OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ +- OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ +- OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ +- OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ +- OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ +- >; +- }; +- +- uart1_pins: pinmux_uart1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ +- OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ +- >; +- }; +- +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ +- OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ +- >; +- }; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ +- OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ +- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ +- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ +- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ +- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ +- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ +- >; +- }; +- +- backlight_pins: backlight_pins_pinmux { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20ba, MUX_MODE3) /* gpt11/gpio57 */ +- >; +- }; +- +- dss_dpi_pins: pinmux_dss_dpi_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ +- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ +- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ +- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ +- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ +- OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ +- OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ +- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ +- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ +- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ +- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ +- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ +- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ +- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ +- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ +- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ +- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ +- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ +- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ +- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ +- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ +- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ +- OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ +- OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ +- OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ +- OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ +- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ +- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ +- >; +- }; +- +- gps_pins: pinmux_gps_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* gpio145 */ +- >; +- }; +- +- hdq_pins: hdq_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.hdq */ +- >; +- }; +- +- bmp085_pins: pinmux_bmp085_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2136, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio113 */ +- >; +- }; +- +- bma180_pins: pinmux_bma180_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x213a, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio115 */ +- >; +- }; +- +- itg3200_pins: pinmux_itg3200_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio56 */ +- >; +- }; +- +- hmc5843_pins: pinmux_hmc5843_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2134, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio112 */ +- >; +- }; +- +- penirq_pins: pinmux_penirq_pins { +- pinctrl-single,pins = < +- /* here we could enable to wakeup the cpu from suspend by a pen touch */ +- OMAP3_CORE1_IOPAD(0x2194, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio160 */ +- >; +- }; +- +- camera_pins: pinmux_camera_pins { +- pinctrl-single,pins = < +- /* set up parallel camera interface */ +- OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_hs */ +- OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_vs */ +- OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */ +- OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_pclk */ +- OMAP3_CORE1_IOPAD(0x2114, PIN_OUTPUT | MUX_MODE4) /* cam_fld = gpio_98 */ +- OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d0 */ +- OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d1 */ +- OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d2 */ +- OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d3 */ +- OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d4 */ +- OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d5 */ +- OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d6 */ +- OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d7 */ +- OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d8 */ +- OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d9 */ +- OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d10 */ +- OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d10 */ +- OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE0) /* cam_xclkb */ +- OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* cam_wen = gpio_167 */ +- OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLDOWN | MUX_MODE4) /* cam_strobe */ +- >; +- }; +- +- mcbsp1_pins: pinmux_mcbsp1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkr.mcbsp1_clkr - gpio_156 FM interrupt */ +- OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_clkr.mcbsp1_fsr */ +- OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dx */ +- OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dr */ +- /* mcbsp_clks is used as PENIRQ */ +- /* OMAP3_CORE1_IOPAD(0x2194, PIN_INPUT | MUX_MODE0) mcbsp_clks.mcbsp_clks */ +- OMAP3_CORE1_IOPAD(0x2196, PIN_INPUT | MUX_MODE0) /* mcbsp_clks.mcbsp1_fsx */ +- OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE0) /* mcbsp1_clkx.mcbsp1_clkx */ +- >; +- }; +- +- mcbsp2_pins: pinmux_mcbsp2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ +- OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_clkx */ +- OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2_dr */ +- OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2_dx */ +- >; +- }; +- +- mcbsp3_pins: pinmux_mcbsp3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.mcbsp3_dx */ +- OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dx.mcbsp3_dr */ +- OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0) /* mcbsp3_clkx.mcbsp3_clkx */ +- OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0) /* mcbsp3_clkx.mcbsp3_fsx */ +- >; +- }; +- +- mcbsp4_pins: pinmux_mcbsp4_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcbsp4_clkx.mcbsp4_clkx */ +- OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcbsp4_clkx.mcbsp4_dr */ +- OMAP3_CORE1_IOPAD(0x218a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcbsp4_dx.mcbsp4_fsx */ +- >; +- }; +-}; +- +-&omap3_pmx_core2 { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &hsusb2_2_pins +- >; +- +- hsusb2_2_pins: pinmux_hsusb2_2_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ +- OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ +- OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ +- OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ +- OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ +- OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ +- >; +- }; +- +- spi_gpio_pins: spi_gpio_pinmux { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */ +- OMAP3630_CORE2_IOPAD(0x25e6, PIN_OUTPUT | MUX_MODE4) /* cs */ +- OMAP3630_CORE2_IOPAD(0x25e8, PIN_OUTPUT | MUX_MODE4) /* tx */ +- OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE4) /* rx */ +- >; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <2600000>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- interrupt-parent = <&intc>; +- +- clocks = <&hfclk_26m>; +- clock-names = "fck"; +- +- twl_audio: audio { +- compatible = "ti,twl4030-audio"; +- ti,enable-vibra = <1>; +- codec { +- ti,ramp_delay_value = <3>; +- }; +- }; +- +- twl_power: power { +- compatible = "ti,twl4030-power-idle"; +- ti,system-power-controller; +- }; +- }; +-}; +- +-#include "twl4030.dtsi" +-#include "twl4030_omap3.dtsi" +- +-&i2c2 { +- clock-frequency = <400000>; +- +- /* pressure sensor */ +- bmp085@77 { +- compatible = "bosch,bmp085"; +- reg = <0x77>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bmp085_pins>; +- interrupt-parent = <&gpio4>; +- interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* GPIO_113 */ +- }; +- +- /* accelerometer */ +- bma180@41 { +- compatible = "bosch,bma180"; +- reg = <0x41>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bma180_pins>; +- interrupt-parent = <&gpio4>; +- interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_115 */ +- }; +- +- /* gyroscope */ +- itg3200@68 { +- compatible = "invensense,itg3200"; +- reg = <0x68>; +- pinctrl-names = "default"; +- pinctrl-0 = <&itg3200_pins>; +- interrupt-parent = <&gpio2>; +- interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* GPIO_56 */ +- }; +- +- /* leds + gpios */ +- tca6507: tca6507@45 { +- compatible = "ti,tca6507"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x45>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- gta04_led0: red_aux@0 { +- label = "gta04:red:aux"; +- reg = <0x0>; +- }; +- +- gta04_led1: green_aux@1 { +- label = "gta04:green:aux"; +- reg = <0x1>; +- }; +- +- gta04_led3: red_power@3 { +- label = "gta04:red:power"; +- reg = <0x3>; +- linux,default-trigger = "default-on"; +- }; +- +- gta04_led4: green_power@4 { +- label = "gta04:green:power"; +- reg = <0x4>; +- }; +- +- wifi_reset: wifi_reset@6 { /* reference as <&tca_gpios 0 0> since it is currently the only GPIO */ +- reg = <0x6>; +- compatible = "gpio"; +- }; +- }; +- +- /* compass aka magnetometer */ +- hmc5843@1e { +- compatible = "honeywell,hmc5883l"; +- reg = <0x1e>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hmc5843_pins>; +- interrupt-parent = <&gpio4>; +- interrupts = <16 IRQ_TYPE_EDGE_FALLING>; /* gpio112 */ +- }; +- +- /* touchscreen */ +- tsc2007@48 { +- compatible = "ti,tsc2007"; +- reg = <0x48>; +- pinctrl-names = "default"; +- pinctrl-0 = <&penirq_pins>; +- interrupt-parent = <&gpio6>; +- interrupts = <0 IRQ_TYPE_EDGE_FALLING>; /* GPIO_160 */ +- gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* GPIO_160 */ +- ti,x-plate-ohms = <600>; +- touchscreen-size-x = <480>; +- touchscreen-size-y = <640>; +- touchscreen-max-pressure = <1000>; +- touchscreen-fuzz-x = <3>; +- touchscreen-fuzz-y = <8>; +- touchscreen-fuzz-pressure = <10>; +- touchscreen-inverted-y; +- }; +- +- /* RFID EEPROM */ +- m24lr64@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +-}; +- +-&usb_otg_hs { +- interface-type = <0>; +- usb-phy = <&usb2_phy>; +- phys = <&usb2_phy>; +- phy-names = "usb2-phy"; +- mode = <3>; +- power = <50>; +-}; +- +-&usbhshost { +- port2-mode = "ehci-phy"; +-}; +- +-&usbhsehci { +- phys = <0 &hsusb2_phy>; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <&vmmc1>; +- bus-width = <4>; +- ti,non-removable; +- broken-cd; /* hardware has no CD */ +-}; +- +-&mmc2 { +- vmmc-supply = <&vaux4>; +- bus-width = <4>; +- ti,non-removable; +- cap-power-off-card; +- mmc-pwrseq = <&wifi_pwrseq>; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-#define BIT(x) (1 << (x)) +-&twl_gpio { +- /* pullups: BIT(2) */ +- ti,pullups = ; +- /* +- * pulldowns: +- * BIT(0), BIT(1), BIT(6), BIT(7), BIT(8), BIT(13) +- * BIT(15), BIT(16), BIT(17) +- */ +- ti,pulldowns = <(BIT(0) | BIT(1) | BIT(6) | BIT(7) | BIT(8) | +- BIT(13) | BIT(15) | BIT(16) | BIT(17))>; +-}; +- +-&twl_keypad { +- status = "disabled"; +-}; +- +-&gpio1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio1_pins>; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- gnss: gnss { +- compatible = "wi2wi,w2sg0004"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gps_pins>; +- sirf,onoff-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; +- lna-supply = <&vsim>; +- vcc-supply = <&ldo_3v3>; +- }; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; +-}; +- +-&charger { +- ti,bb-uvolt = <3200000>; +- ti,bb-uamp = <150>; +-}; +- +-/* spare */ +-&vaux1 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <3000000>; +-}; +- +-/* sensors */ +-&vaux2 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; /* we should never switch off while vio is on! */ +-}; +- +-/* camera */ +-&vaux3 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +-}; +- +-/* WLAN/BT */ +-&vaux4 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <3150000>; +-}; +- +-/* GPS LNA */ +-&vsim { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <3150000>; +-}; +- +-/* Needed to power the DPI pins */ +- +-&vpll2 { +- regulator-always-on; +-}; +- +-&dss { +- pinctrl-names = "default"; +- pinctrl-0 = < &dss_dpi_pins >; +- +- status = "okay"; +- vdds_dsi-supply = <&vpll2>; +- +- port { +- dpi_out: endpoint { +- remote-endpoint = <&lcd_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-&venc { +- status = "okay"; +- +- vdda-supply = <&vdac>; +- +- port { +- venc_out: endpoint { +- remote-endpoint = <&opa_in>; +- ti,channels = <1>; +- ti,invert-polarity; +- }; +- }; +-}; +- +-&gpmc { +- ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ +- +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- ti,nand-ecc-opt = "ham1"; +- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ +- nand-bus-width = <16>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- gpmc,device-width = <2>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,oe-off-ns = <54>; +- gpmc,we-off-ns = <40>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- gpmc,sync-clk-ps = <0>; +- +- x-loader@0 { +- label = "X-Loader"; +- reg = <0 0x80000>; +- }; +- +- bootloaders@80000 { +- label = "U-Boot"; +- reg = <0x80000 0x1c0000>; +- }; +- +- bootloaders_env@240000 { +- label = "U-Boot Env"; +- reg = <0x240000 0x40000>; +- }; +- +- kernel@280000 { +- label = "Kernel"; +- reg = <0x280000 0x600000>; +- }; +- +- filesystem@880000 { +- label = "File System"; +- reg = <0x880000 0>; /* 0 = MTDPART_SIZ_FULL */ +- }; +- }; +-}; +- +-&mcbsp1 { /* FM Transceiver PCM */ +- status = "okay"; +- #sound-dai-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp1_pins>; +-}; +- +-&mcbsp2 { /* TPS65950 I2S */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp2_pins>; +-}; +- +-&mcbsp3 { /* Bluetooth PCM */ +- status = "okay"; +- #sound-dai-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp3_pins>; +-}; +- +-&mcbsp4 { /* GSM voice PCM */ +- status = "okay"; +- #sound-dai-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp4_pins>; +-}; +- +-&hdqw1w { +- pinctrl-names = "default"; +- pinctrl-0 = <&hdq_pins>; +-}; +- +-/* image signal processor within OMAP3 SoC */ +-&isp { +- ports { +- port@0 { +- reg = <0>; +- parallel_ep: endpoint { +- ti,isp-clock-divisor = <1>; +- ti,strobe-mode; +- bus-width = <8>;/* Used data lines */ +- data-shift = <2>; /* Lines 9:2 are used */ +- hsync-active = <0>; /* Active low */ +- vsync-active = <1>; /* Active high */ +- data-active = <1>;/* Active high */ +- pclk-sample = <1>;/* Falling */ +- }; +- }; +- /* port@1 and port@2 are not used by GTA04 */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-gta04a3.dts b/scripts/dtc/include-prefixes/arm/omap3-gta04a3.dts +deleted file mode 100644 +index bfae1a9ceeac..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-gta04a3.dts ++++ /dev/null +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 H. Nikolaus Schaller +- */ +- +-#include "omap3-gta04.dtsi" +- +-/ { +- model = "Goldelico GTA04A3/Letux 2804"; +-}; +- +-&i2c2 { +- +- /* alternate accelerometer that might be installed on some GTA04A3 boards */ +- lis302@1d { +- compatible = "st,lis331dlh", "st,lis3lv02d"; +- reg = <0x1d>; +- interrupt-parent = <&gpio3>; +- interrupts = <18 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; +- Vdd-supply = <&vaux2>; +- Vdd_IO-supply = <&vaux2>; +- +- st,click-single-x; +- st,click-single-y; +- st,click-single-z; +- st,click-thresh-x = <8>; +- st,click-thresh-y = <8>; +- st,click-thresh-z = <10>; +- st,click-click-time-limit = <9>; +- st,click-latency = <50>; +- st,irq1-click; +- st,wakeup-x-lo; +- st,wakeup-x-hi; +- st,wakeup-y-lo; +- st,wakeup-y-hi; +- st,wakeup-z-lo; +- st,wakeup-z-hi; +- st,min-limit-x = <32>; +- st,min-limit-y = <3>; +- st,min-limit-z = <3>; +- st,max-limit-x = <3>; +- st,max-limit-y = <32>; +- st,max-limit-z = <32>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-gta04a4.dts b/scripts/dtc/include-prefixes/arm/omap3-gta04a4.dts +deleted file mode 100644 +index f1cf24d55e6f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-gta04a4.dts ++++ /dev/null +@@ -1,10 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Marek Belisko +- */ +- +-#include "omap3-gta04.dtsi" +- +-/ { +- model = "Goldelico GTA04A4/Letux 2804"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-gta04a5.dts b/scripts/dtc/include-prefixes/arm/omap3-gta04a5.dts +deleted file mode 100644 +index 9ce8d81250aa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-gta04a5.dts ++++ /dev/null +@@ -1,137 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014-18 H. Nikolaus Schaller +- */ +- +-#include "omap3-gta04.dtsi" +- +-/ { +- model = "Goldelico GTA04A5/Letux 2804"; +- +- sound { +- ti,jack-det-gpio = <&twl_gpio 2 GPIO_ACTIVE_HIGH>; /* GTA04A5 only */ +- }; +- +- wlan_en: wlan_en_regulator { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_pins>; +- regulator-name = "wlan-en-regulator"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* GPIO_138 */ +- +- startup-delay-us = <70000>; +- enable-active-high; +- }; +- +- pps { +- compatible = "pps-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pps_pins>; +- +- gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; /* GPIN_114 */ +- }; +- +-}; +- +-&gpio5 { +- irda-en-hog { +- gpio-hog; +- gpios = <(175-160) GPIO_ACTIVE_HIGH>; +- output-high; /* activate gpio_175 to disable IrDA receiver */ +- }; +-}; +- +-&omap3_pmx_core { +- bt_pins: pinmux_bt_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* mmc2_dat5 = mmc3_dat1 = gpio137 */ +- >; +- }; +- +- wlan_pins: pinmux_wlan_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* mmc2_dat6 = mmc3_dat2 = gpio138 */ +- >; +- }; +- +- wlan_irq_pin: pinmux_wlan_irq_pin { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE4) /* mmc2_dat7 = mmc3_dat3 = gpio139 */ +- >; +- }; +- +- irda_pins: pinmux_irda { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21d0, PIN_OUTPUT_PULLUP | MUX_MODE4) /* mcspi1_cs1 = gpio175 */ +- >; +- }; +- +- pps_pins: pinmux_pps_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT | MUX_MODE4) /* gpin114 */ +- >; +- }; +- +-}; +- +-/* +- * for WL183x module see +- * Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt +- */ +- +-&wifi_pwrseq { +- /delete-property/ reset-gpios; +-}; +- +-&mmc2 { +- vmmc-supply = <&wlan_en>; +- bus-width = <4>; +- cap-power-off-card; +- non-removable; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_irq_pin>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- /delete-property/ mmc-pwrseq; +- +- wlcore: wlcore@2 { +- compatible = "ti,wl1837"; +- reg = <2>; +- interrupt-parent = <&gpio5>; +- interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_139 */ +- ref-clock-frequency = <26000000>; +- }; +-}; +- +-&i2c2 { +- /delete-node/ bmp085@77; +- /delete-node/ bma180@41; +- /delete-node/ itg3200@68; +- /delete-node/ hmc5843@1e; +- +- bmg160@69 { +- compatible = "bosch,bmg160"; +- reg = <0x69>; +- }; +- +- bmc150@10 { +- compatible = "bosch,bmc150_accel"; +- reg = <0x10>; +- }; +- +- bmc150@12 { +- compatible = "bosch,bmc150_magn"; +- reg = <0x12>; +- }; +- +- bme280@76 { +- compatible = "bosch,bme280"; +- reg = <0x76>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-gta04a5one.dts b/scripts/dtc/include-prefixes/arm/omap3-gta04a5one.dts +deleted file mode 100644 +index 9db9fe67cd63..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-gta04a5one.dts ++++ /dev/null +@@ -1,111 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014-18 H. Nikolaus Schaller +- */ +- +-#include "omap3-gta04a5.dts" +- +-&omap3_pmx_core { +- model = "Goldelico GTA04A5/Letux 2804 with OneNAND"; +- +- gpmc_pins: pinmux_gpmc_pins { +- pinctrl-single,pins = < +- +- /* address lines */ +- OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ +- OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ +- OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ +- +- /* data lines, gpmc_d0..d7 not muxable according to TRM */ +- OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ +- OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ +- OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ +- OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ +- OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ +- OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ +- OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ +- OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ +- +- /* +- * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable +- * according to TRM. OneNAND seems to require PIN_INPUT on clock. +- */ +- OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ +- OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ +- >; +- }; +-}; +- +-&gpmc { +- /* switch inherited setup to OneNAND */ +- +- ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ +- pinctrl-names = "default"; +- pinctrl-0 = <&gpmc_pins>; +- +- /delete-node/ nand@0,0; +- +- onenand@0,0 { +- +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ti,omap2-onenand"; +- reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ +- +- gpmc,sync-read; +- gpmc,sync-write; +- gpmc,burst-length = <16>; +- gpmc,burst-read; +- gpmc,burst-wrap; +- gpmc,burst-write; +- gpmc,device-width = <2>; +- gpmc,mux-add-data = <2>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <87>; +- gpmc,cs-wr-off-ns = <87>; +- gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <10>; +- gpmc,adv-wr-off-ns = <10>; +- gpmc,oe-on-ns = <15>; +- gpmc,oe-off-ns = <87>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <87>; +- gpmc,rd-cycle-ns = <112>; +- gpmc,wr-cycle-ns = <112>; +- gpmc,access-ns = <81>; +- gpmc,page-burst-access-ns = <15>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,wait-monitoring-ns = <0>; +- gpmc,clk-activation-ns = <5>; +- gpmc,wr-data-mux-bus-ns = <30>; +- gpmc,wr-access-ns = <81>; +- gpmc,sync-clk-ps = <15000>; +- +- x-loader@0 { +- label = "X-Loader"; +- reg = <0 0x80000>; +- }; +- +- bootloaders@80000 { +- label = "U-Boot"; +- reg = <0x80000 0x1c0000>; +- }; +- +- bootloaders_env@240000 { +- label = "U-Boot Env"; +- reg = <0x240000 0x40000>; +- }; +- +- kernel@280000 { +- label = "Kernel"; +- reg = <0x280000 0x600000>; +- }; +- +- filesystem@880000 { +- label = "File System"; +- reg = <0x880000 0>; /* 0 = MTDPART_SIZ_FULL */ +- }; +- +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-ha-common.dtsi b/scripts/dtc/include-prefixes/arm/omap3-ha-common.dtsi +deleted file mode 100644 +index a010585d0302..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-ha-common.dtsi ++++ /dev/null +@@ -1,85 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- * Copyright (C) 2014 Stefan Roese +- */ +- +-#include "omap3-tao3530.dtsi" +- +-/ { +- gpio_poweroff { +- pinctrl-names = "default"; +- pinctrl-0 = <&poweroff_pins>; +- +- compatible = "gpio-poweroff"; +- gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; /* GPIO 168 */ +- }; +-}; +- +-&omap3_pmx_core { +- sound2_pins: pinmux_sound2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x209e, PIN_OUTPUT | MUX_MODE4) /* gpmc_d8 gpio_44 */ +- >; +- }; +- +- led_blue_pins: pinmux_led_blue_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE4) /* cam_xclka gpio_96, LED blue */ +- >; +- }; +- +- led_green_pins: pinmux_led_green_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2126, PIN_OUTPUT | MUX_MODE4) /* cam_d8 gpio_107, LED green */ +- >; +- }; +- +- led_red_pins: pinmux_led_red_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* cam_xclkb gpio_111, LED red */ +- >; +- }; +- +- poweroff_pins: pinmux_poweroff_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT_PULLUP | MUX_MODE4) /* i2c2_scl gpio_168 */ +- >; +- }; +- +- powerdown_input_pins: pinmux_powerdown_input_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE4) /* i2c2_sda gpio_183 */ +- >; +- }; +- +- fpga_boot0_pins: fpga_boot0_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2 gpio_101 */ +- OMAP3_CORE1_IOPAD(0x211c, PIN_OUTPUT | MUX_MODE4) /* cam_d3 gpio_102 */ +- OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE4) /* cam_d4 gpio_103 */ +- OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d5 gpio_104 */ +- >; +- }; +- +- fpga_boot1_pins: fpga_boot1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE4) /* gpmc_d10 gpio_46 */ +- OMAP3_CORE1_IOPAD(0x20a4, PIN_OUTPUT | MUX_MODE4) /* gpmc_d11 gpio_47 */ +- OMAP3_CORE1_IOPAD(0x20a6, PIN_OUTPUT | MUX_MODE4) /* gpmc_d12 gpio_48 */ +- OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_d13 gpio_49 */ +- >; +- }; +-}; +- +-/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */ +-&i2c2 { +- status = "disabled"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-ha-lcd.dts b/scripts/dtc/include-prefixes/arm/omap3-ha-lcd.dts +deleted file mode 100644 +index 643283f0c3db..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-ha-lcd.dts ++++ /dev/null +@@ -1,162 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- * Copyright (C) 2014 Stefan Roese +- */ +- +-#include "omap3-ha-common.dtsi" +- +-/ { +- model = "TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOM"; +- compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; +-}; +- +-&omap3_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &hsusbb2_pins +- &powerdown_input_pins +- &fpga_boot0_pins +- &fpga_boot1_pins +- &led_blue_pins +- &led_green_pins +- &led_red_pins +- &touchscreen_wake_pins +- >; +- +- touchscreen_irq_pins: pinmux_touchscreen_irq_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio_136, Touchscreen IRQ */ +- >; +- }; +- +- touchscreen_wake_pins: pinmux_touchscreen_wake_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x212c, PIN_OUTPUT_PULLUP | MUX_MODE4) /* gpio_110, Touchscreen Wake */ +- >; +- }; +- +- dss_dpi_pins: pinmux_dss_dpi_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ +- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ +- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ +- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ +- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ +- OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ +- OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ +- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ +- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ +- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ +- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ +- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ +- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ +- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ +- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ +- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ +- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ +- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ +- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ +- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ +- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ +- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ +- OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ +- OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ +- OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ +- OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ +- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ +- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ +- >; +- }; +- +- lte430_pins: pinmux_lte430_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ +- >; +- }; +- +- backlight_pins: pinmux_backlight_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ +- >; +- }; +-}; +- +-/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */ +-&i2c2 { +- status = "disabled"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +-}; +- +-/* Needed to power the DPI pins */ +-&vpll2 { +- regulator-always-on; +-}; +- +-&dss { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_dpi_pins>; +- +- port { +- dpi_out: endpoint { +- remote-endpoint = <&lcd_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-/ { +- aliases { +- display0 = &lcd0; +- }; +- +- lcd0: display { +- compatible = "panel-dpi"; +- label = "lcd"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <<e430_pins>; +- enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */ +- +- port { +- lcd_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- +- panel-timing { +- clock-frequency = <31250000>; +- hactive = <800>; +- vactive = <480>; +- hfront-porch = <40>; +- hback-porch = <86>; +- hsync-len = <1>; +- vback-porch = <30>; +- vfront-porch = <13>; +- vsync-len = <3>; +- +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- +- backlight { +- compatible = "gpio-backlight"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&backlight_pins>; +- gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */ +- +- default-on; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-ha.dts b/scripts/dtc/include-prefixes/arm/omap3-ha.dts +deleted file mode 100644 +index 19e471eb3b4e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-ha.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- * Copyright (C) 2014 Stefan Roese +- */ +- +-#include "omap3-ha-common.dtsi" +- +-/ { +- model = "TI OMAP3 HEAD acoustics baseboard with TAO3530 SOM"; +- compatible = "headacoustics,omap3-ha", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; +-}; +- +-&omap3_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &hsusbb2_pins +- &powerdown_input_pins +- &fpga_boot0_pins +- &fpga_boot1_pins +- &led_blue_pins +- &led_green_pins +- &led_red_pins +- >; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-igep.dtsi b/scripts/dtc/include-prefixes/arm/omap3-igep.dtsi +deleted file mode 100644 +index 99f5585097a1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-igep.dtsi ++++ /dev/null +@@ -1,247 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Common device tree for IGEP boards based on AM/DM37x +- * +- * Copyright (C) 2012 Javier Martinez Canillas +- * Copyright (C) 2012 Enric Balletbo i Serra +- */ +-/dts-v1/; +- +-#include "omap36xx.dtsi" +- +-/ { +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512 MB */ +- }; +- +- chosen { +- stdout-path = &uart3; +- }; +- +- sound { +- compatible = "ti,omap-twl4030"; +- ti,model = "igep2"; +- ti,mcbsp = <&mcbsp2>; +- }; +- +- vdd33: regulator-vdd33 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd33"; +- regulator-always-on; +- }; +- +-}; +- +-&omap3_pmx_core { +- gpmc_pins: pinmux_gpmc_pins { +- pinctrl-single,pins = < +- /* OneNAND seems to require PIN_INPUT on clock. */ +- OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ +- >; +- }; +- +- uart1_pins: pinmux_uart1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ +- OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ +- >; +- }; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ +- OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ +- >; +- }; +- +- mcbsp2_pins: pinmux_mcbsp2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ +- OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ +- OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */ +- OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ +- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ +- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ +- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ +- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ +- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ +- >; +- }; +- +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ +- OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ +- OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ +- OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ +- OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ +- OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ +- OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ +- >; +- }; +- +- i2c3_pins: pinmux_i2c3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ +- OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ +- >; +- }; +-}; +- +-&gpmc { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpmc_pins>; +- +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- linux,mtd-name= "micron,mt29c4g96maz"; +- nand-bus-width = <16>; +- gpmc,device-width = <2>; +- ti,nand-ecc-opt = "bch8"; +- +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- status = "okay"; +- }; +- +- onenand@0,0 { +- compatible = "ti,omap2-onenand"; +- reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ +- +- gpmc,sync-read; +- gpmc,sync-write; +- gpmc,burst-length = <16>; +- gpmc,burst-wrap; +- gpmc,burst-read; +- gpmc,burst-write; +- gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ +- gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */ +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <96>; +- gpmc,cs-wr-off-ns = <96>; +- gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <12>; +- gpmc,adv-wr-off-ns = <12>; +- gpmc,oe-on-ns = <18>; +- gpmc,oe-off-ns = <96>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <96>; +- gpmc,rd-cycle-ns = <114>; +- gpmc,wr-cycle-ns = <114>; +- gpmc,access-ns = <90>; +- gpmc,page-burst-access-ns = <12>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,wait-monitoring-ns = <0>; +- gpmc,clk-activation-ns = <6>; +- gpmc,wr-data-mux-bus-ns = <30>; +- gpmc,wr-access-ns = <90>; +- gpmc,sync-clk-ps = <12000>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- status = "disabled"; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- clock-frequency = <2600000>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- interrupt-parent = <&intc>; +- +- twl_audio: audio { +- compatible = "ti,twl4030-audio"; +- codec { +- }; +- }; +- }; +-}; +- +-#include "twl4030.dtsi" +-#include "twl4030_omap3.dtsi" +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +-}; +- +-&mcbsp2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp2_pins>; +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <&vmmc1>; +- vmmc_aux-supply = <&vsim>; +- bus-width = <4>; +- cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +-}; +- +-&twl_gpio { +- ti,use-leds; +-}; +- +-&usb_otg_hs { +- interface-type = <0>; +- usb-phy = <&usb2_phy>; +- phys = <&usb2_phy>; +- phy-names = "usb2-phy"; +- mode = <3>; +- power = <50>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-igep0020-common.dtsi b/scripts/dtc/include-prefixes/arm/omap3-igep0020-common.dtsi +deleted file mode 100644 +index 73d8f471b9ec..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-igep0020-common.dtsi ++++ /dev/null +@@ -1,261 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Common Device Tree Source for IGEPv2 +- * +- * Copyright (C) 2014 Javier Martinez Canillas +- * Copyright (C) 2014 Enric Balletbo i Serra +- */ +- +-#include "omap3-igep.dtsi" +-#include "omap-gpmc-smsc9221.dtsi" +- +-/ { +- +- leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&leds_pins>; +- compatible = "gpio-leds"; +- +- boot { +- label = "omap3:green:boot"; +- gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- user0 { +- label = "omap3:red:user0"; +- gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- user1 { +- label = "omap3:red:user1"; +- gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- user2 { +- label = "omap3:green:user1"; +- gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- /* HS USB Port 1 Power */ +- hsusb1_power: hsusb1_power_reg { +- compatible = "regulator-fixed"; +- regulator-name = "hsusb1_vbus"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */ +- startup-delay-us = <70000>; +- }; +- +- /* HS USB Host PHY on PORT 1 */ +- hsusb1_phy: hsusb1_phy { +- compatible = "usb-nop-xceiv"; +- reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */ +- vcc-supply = <&hsusb1_power>; +- #phy-cells = <0>; +- }; +- +- tfp410: encoder { +- compatible = "ti,tfp410"; +- powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tfp410_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- tfp410_out: endpoint { +- remote-endpoint = <&dvi_connector_in>; +- }; +- }; +- }; +- }; +- +- dvi0: connector { +- compatible = "dvi-connector"; +- label = "dvi"; +- +- digital; +- +- ddc-i2c-bus = <&i2c3>; +- +- port { +- dvi_connector_in: endpoint { +- remote-endpoint = <&tfp410_out>; +- }; +- }; +- }; +-}; +- +-&omap3_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &tfp410_pins +- &dss_dpi_pins +- >; +- +- tfp410_pins: pinmux_tfp410_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ +- >; +- }; +- +- dss_dpi_pins: pinmux_dss_dpi_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ +- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ +- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ +- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ +- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ +- OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ +- OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ +- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ +- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ +- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ +- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ +- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ +- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ +- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ +- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ +- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ +- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ +- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ +- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ +- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ +- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ +- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ +- OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ +- OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ +- OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ +- OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ +- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ +- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ +- >; +- }; +- +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ +- OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ +- OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ +- OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ +- >; +- }; +- +- smsc9221_pins: pinmux_smsc9221_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ +- >; +- }; +-}; +- +-&omap3_pmx_core2 { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &hsusbb1_pins +- >; +- +- hsusbb1_pins: pinmux_hsusbb1_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ +- OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ +- OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */ +- OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */ +- OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */ +- OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */ +- OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */ +- OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */ +- OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */ +- OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */ +- OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */ +- OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */ +- >; +- }; +- +- leds_pins: pinmux_leds_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */ +- OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */ +- OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ +- >; +- }; +- +- mmc1_wp_pins: pinmux_mmc1_cd_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4) /* etk_d15.gpio_29 */ +- >; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- +- /* +- * Display monitor features are burnt in the EEPROM +- * as EDID data. +- */ +- eeprom@50 { +- compatible = "ti,eeprom"; +- reg = <0x50>; +- }; +-}; +- +-&gpmc { +- ranges = <0 0 0x30000000 0x01000000>, /* CS0: 16MB for NAND */ +- <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for ethernet */ +- +- ethernet@gpmc { +- pinctrl-names = "default"; +- pinctrl-0 = <&smsc9221_pins>; +- reg = <5 0 0xff>; +- interrupt-parent = <&gpio6>; +- interrupts = <16 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +-}; +- +-&usbhshost { +- port1-mode = "ehci-phy"; +-}; +- +-&usbhsehci { +- phys = <&hsusb1_phy>; +-}; +- +-&vpll2 { +- /* Needed for DSS */ +- regulator-name = "vdds_dsi"; +-}; +- +-&dss { +- status = "okay"; +- +- port { +- dpi_out: endpoint { +- remote-endpoint = <&tfp410_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-&mmc1 { +- pinctrl-0 = <&mmc1_pins &mmc1_wp_pins>; +- wp-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; /* gpio_29 */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-igep0020-rev-f.dts b/scripts/dtc/include-prefixes/arm/omap3-igep0020-rev-f.dts +deleted file mode 100644 +index 9dca5bfc87ab..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-igep0020-rev-f.dts ++++ /dev/null +@@ -1,59 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for IGEPv2 Rev. F (TI OMAP AM/DM37x) +- * +- * Copyright (C) Javier Martinez Canillas +- * Copyright (C) 2012 Enric Balletbo i Serra +- */ +- +-#include "omap3-igep0020-common.dtsi" +- +-/ { +- model = "IGEPv2 Rev. F (TI OMAP AM/DM37x)"; +- compatible = "isee,omap3-igep0020-rev-f", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +- +- /* Regulator to trigger the WL_EN signal of the Wifi module */ +- lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { +- compatible = "regulator-fixed"; +- regulator-name = "regulator-lbep5clwmc-wlen"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */ +- enable-active-high; +- }; +-}; +- +-&omap3_pmx_core { +- lbep5clwmc_pins: pinmux_lbep5clwmc_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT | MUX_MODE4) /* mcspi1_cs3.gpio_177 - W_IRQ */ +- OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ +- OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */ +- >; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>; +- vmmc-supply = <&lbep5clwmc_wlen>; +- bus-width = <4>; +- non-removable; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1835"; +- reg = <2>; +- interrupt-parent = <&gpio6>; +- interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* gpio 177 */ +- }; +-}; +- +-&uart2 { +- bluetooth { +- compatible = "ti,wl1835-st"; +- enable-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; /* gpio 137 */ +- max-speed = <300000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-igep0020.dts b/scripts/dtc/include-prefixes/arm/omap3-igep0020.dts +deleted file mode 100644 +index c6f863bc03ad..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-igep0020.dts ++++ /dev/null +@@ -1,47 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x) +- * +- * Copyright (C) 2012 Javier Martinez Canillas +- * Copyright (C) 2012 Enric Balletbo i Serra +- */ +- +-#include "omap3-igep0020-common.dtsi" +- +-/ { +- model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)"; +- compatible = "isee,omap3-igep0020", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +- +- vmmcsdio_fixed: fixedregulator-mmcsdio { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsdio_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- mmc2_pwrseq: mmc2_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>, /* gpio_139 - RESET_N_W */ +- <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 - WIFI_PDN */ +- }; +-}; +- +-&omap3_pmx_core { +- lbee1usjyc_pins: pinmux_lbee1usjyc_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ +- OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ +- OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */ +- >; +- }; +-}; +- +-/* On board Wifi module */ +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>; +- vmmc-supply = <&vmmcsdio_fixed>; +- mmc-pwrseq = <&mmc2_pwrseq>; +- bus-width = <4>; +- non-removable; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-igep0030-common.dtsi b/scripts/dtc/include-prefixes/arm/omap3-igep0030-common.dtsi +deleted file mode 100644 +index 742e3e147063..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-igep0030-common.dtsi ++++ /dev/null +@@ -1,103 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Common Device Tree Source for IGEP COM MODULE +- * +- * Copyright (C) 2014 Javier Martinez Canillas +- * Copyright (C) 2014 Enric Balletbo i Serra +- */ +- +-#include "omap3-igep.dtsi" +- +-/ { +- leds: gpio_leds { +- compatible = "gpio-leds"; +- +- user0 { +- label = "omap3:red:user0"; +- gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ +- default-state = "off"; +- }; +- +- user1 { +- label = "omap3:green:user1"; +- gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */ +- default-state = "off"; +- }; +- +- user2 { +- label = "omap3:red:user1"; +- gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* gpio_16 */ +- default-state = "off"; +- }; +- }; +- +- hsusb2_phy: hsusb2_phy { +- compatible = "usb-nop-xceiv"; +- reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */ +- #phy-cells = <0>; +- }; +-}; +- +-&omap3_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = <&hsusb2_pins>; +- +- hsusb2_pins: pinmux_hsusb2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ +- OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ +- OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ +- OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ +- OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ +- OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ +- >; +- }; +- +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */ +- OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */ +- OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */ +- OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ +- >; +- }; +-}; +- +-&omap3_pmx_core2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hsusb2_core2_pins>; +- +- hsusb2_core2_pins: pinmux_hsusb2_core2_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ +- OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ +- OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ +- OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ +- OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ +- OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ +- >; +- }; +- +- leds_core2_pins: pinmux_leds_core2_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ +- >; +- }; +-}; +- +-&usbhshost { +- port2-mode = "ehci-phy"; +-}; +- +-&usbhsehci { +- phys = <0 &hsusb2_phy>; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +-}; +- +-&gpmc { +- ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-igep0030-rev-g.dts b/scripts/dtc/include-prefixes/arm/omap3-igep0030-rev-g.dts +deleted file mode 100644 +index 8e9c12cf51a7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-igep0030-rev-g.dts ++++ /dev/null +@@ -1,81 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for IGEP COM MODULE Rev. G (TI OMAP AM/DM37x) +- * +- * Copyright (C) 2014 Javier Martinez Canillas +- * Copyright (C) 2014 Enric Balletbo i Serra +- */ +- +-#include "omap3-igep0030-common.dtsi" +- +-/ { +- model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)"; +- compatible = "isee,omap3-igep0030-rev-g", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +- +- /* Regulator to trigger the WL_EN signal of the Wifi module */ +- lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { +- compatible = "regulator-fixed"; +- regulator-name = "regulator-lbep5clwmc-wlen"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */ +- enable-active-high; +- }; +-}; +- +-&omap3_pmx_core { +- lbep5clwmc_pins: pinmux_lbep5clwmc_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 - W_IRQ */ +- OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ +- OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */ +- >; +- }; +- +- leds_pins: pinmux_leds_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */ +- >; +- }; +- +-}; +- +-&i2c2 { +- status = "disabled"; +-}; +- +-&leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&leds_pins &leds_core2_pins>; +- +- boot { +- label = "omap3:green:boot"; +- gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>; +- vmmc-supply = <&lbep5clwmc_wlen>; +- bus-width = <4>; +- non-removable; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1835"; +- reg = <2>; +- interrupt-parent = <&gpio5>; +- interrupts = <8 IRQ_TYPE_EDGE_RISING>; /* gpio 136 */ +- }; +-}; +- +-&uart2 { +- bluetooth { +- compatible = "ti,wl1835-st"; +- enable-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; /* gpio 137 */ +- max-speed = <300000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-igep0030.dts b/scripts/dtc/include-prefixes/arm/omap3-igep0030.dts +deleted file mode 100644 +index 5188f96f431e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-igep0030.dts ++++ /dev/null +@@ -1,59 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for IGEP COM MODULE Rev. E (TI OMAP AM/DM37x) +- * +- * Copyright (C) 2012 Javier Martinez Canillas +- * Copyright (C) 2012 Enric Balletbo i Serra +- */ +- +-#include "omap3-igep0030-common.dtsi" +- +-/ { +- model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)"; +- compatible = "isee,omap3-igep0030", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +- +- vmmcsdio_fixed: fixedregulator-mmcsdio { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsdio_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- mmc2_pwrseq: mmc2_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>, /* gpio_139 - RESET_N_W */ +- <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 - WIFI_PDN */ +- }; +-}; +- +-&omap3_pmx_core { +- lbee1usjyc_pins: pinmux_lbee1usjyc_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ +- OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ +- OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */ +- >; +- }; +-}; +- +-&leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&leds_core2_pins>; +- +- boot { +- label = "omap3:green:boot"; +- gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; /* LEDSYNC */ +- default-state = "on"; +- }; +-}; +- +-/* On board Wifi module */ +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>; +- vmmc-supply = <&vmmcsdio_fixed>; +- mmc-pwrseq = <&mmc2_pwrseq>; +- bus-width = <4>; +- non-removable; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-ldp.dts b/scripts/dtc/include-prefixes/arm/omap3-ldp.dts +deleted file mode 100644 +index 9c6a92724590..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-ldp.dts ++++ /dev/null +@@ -1,305 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include +-#include "omap34xx.dtsi" +-#include "omap-gpmc-smsc911x.dtsi" +- +-/ { +- model = "TI OMAP3430 LDP (Zoom1 Labrador)"; +- compatible = "ti,omap3-ldp", "ti,omap3430", "ti,omap3"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x8000000>; /* 128 MB */ +- }; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&vcc>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_key_pins>; +- +- key_enter { +- label = "enter"; +- gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; /* gpio101 */ +- linux,code = ; +- wakeup-source; +- }; +- +- key_f1 { +- label = "f1"; +- gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; /* gpio102 */ +- linux,code = ; +- wakeup-source; +- }; +- +- key_f2 { +- label = "f2"; +- gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; /* gpio103 */ +- linux,code = ; +- wakeup-source; +- }; +- +- key_f3 { +- label = "f3"; +- gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; /* gpio104 */ +- linux,code = ; +- wakeup-source; +- }; +- +- key_f4 { +- label = "f4"; +- gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; /* gpio105 */ +- linux,code = ; +- wakeup-source; +- }; +- +- key_left { +- label = "left"; +- gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* gpio106 */ +- linux,code = ; +- wakeup-source; +- }; +- +- key_right { +- label = "right"; +- gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* gpio107 */ +- linux,code = ; +- wakeup-source; +- }; +- +- key_up { +- label = "up"; +- gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; /* gpio108 */ +- linux,code = ; +- wakeup-source; +- }; +- +- key_down { +- label = "down"; +- gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* gpio109 */ +- linux,code = ; +- wakeup-source; +- }; +- }; +-}; +- +-&gpmc { +- ranges = <0 0 0x30000000 0x1000000>, /* CS0 space, 16MB */ +- <1 0 0x08000000 0x1000000>; /* CS1 space, 16MB */ +- +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- linux,mtd-name= "micron,nand"; +- nand-bus-width = <16>; +- gpmc,device-width = <2>; +- ti,nand-ecc-opt = "bch8"; +- +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "X-Loader"; +- reg = <0 0x80000>; +- }; +- partition@80000 { +- label = "U-Boot"; +- reg = <0x80000 0x140000>; +- }; +- partition@1c0000 { +- label = "Environment"; +- reg = <0x1c0000 0x40000>; +- }; +- partition@200000 { +- label = "Kernel"; +- reg = <0x200000 0x1e00000>; +- }; +- partition@2000000 { +- label = "Filesystem"; +- reg = <0x2000000 0x6000000>; +- }; +- }; +- +- ethernet@gpmc { +- interrupt-parent = <&gpio5>; +- interrupts = <24 IRQ_TYPE_LEVEL_LOW>; +- reg = <1 0 0xff>; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <2600000>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- interrupt-parent = <&intc>; +- +- twl_power: power { +- compatible = "ti,twl4030-power-idle"; +- ti,use_poweroff; +- }; +- }; +-}; +- +-#include "twl4030.dtsi" +-#include "twl4030_omap3.dtsi" +-#include "omap3-panel-sharp-ls037v7dw01.dtsi" +- +-&backlight0 { +- gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +-}; +- +-/* tps61130rsa enabled by twl4030 regen */ +-&lcd_3v3 { +- regulator-always-on; +-}; +- +-&lcd0 { +- enable-gpios = <&twl_gpio 15 GPIO_ACTIVE_HIGH>; /* lcd INI */ +- reset-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; /* gpio55, lcd RESB */ +- mode-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio56, lcd MO */ +-}; +- +-&mcspi1 { +- tsc2046@0 { +- interrupt-parent = <&gpio2>; +- interrupts = <22 0>; /* gpio54 */ +- pendown-gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&mmc1 { +- /* See 35xx errata 2.1.1.128 in SPRZ278F */ +- compatible = "ti,omap3-pre-es3-hsmmc"; +- vmmc-supply = <&vmmc1>; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +-}; +- +-&mmc2 { +- status="disabled"; +-}; +- +-&mmc3 { +- status="disabled"; +-}; +- +-&omap3_pmx_core { +- gpio_key_pins: pinmux_gpio_key_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2.gpio_101 */ +- OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE4) /* cam_d3.gpio_102 */ +- OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE4) /* cam_d4.gpio_103 */ +- OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE4) /* cam_d5.gpio_104 */ +- OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE4) /* cam_d6.gpio_105 */ +- OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE4) /* cam_d7.gpio_106 */ +- OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE4) /* cam_d8.gpio_107 */ +- OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE4) /* cam_d9.gpio_108 */ +- OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */ +- >; +- }; +- +- musb_pins: pinmux_musb_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ +- OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ +- OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ +- OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ +- OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ +- OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ +- OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ +- OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ +- OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ +- OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ +- OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ +- OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ +- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ +- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ +- OMAP3_CORE1_IOPAD(0x214A, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ +- OMAP3_CORE1_IOPAD(0x214C, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ +- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ +- >; +- }; +-}; +- +-&twl_keypad { +- linux,keymap = ; +-}; +- +-&uart3 { +- interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; +-}; +- +-&usb_otg_hs { +- pinctrl-names = "default"; +- pinctrl-0 = <&musb_pins>; +- interface-type = <0>; +- usb-phy = <&usb2_phy>; +- mode = <3>; +- power = <50>; +-}; +- +-&vaux1 { +- /* Needed for ads7846 */ +- regulator-name = "vcc"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-lilly-a83x.dtsi b/scripts/dtc/include-prefixes/arm/omap3-lilly-a83x.dtsi +deleted file mode 100644 +index 73d477898ec2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-lilly-a83x.dtsi ++++ /dev/null +@@ -1,459 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2014 Christoph Fritz +- */ +- +-#include "omap36xx.dtsi" +- +-/ { +- model = "INCOstartec LILLY-A83X module (DM3730)"; +- compatible = "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +- +- chosen { +- bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x8000000>; /* 128 MB */ +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led1 { +- label = "lilly-a83x::led1"; +- gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- +- }; +- +- sound { +- compatible = "ti,omap-twl4030"; +- ti,model = "lilly-a83x"; +- +- ti,mcbsp = <&mcbsp2>; +- }; +- +- reg_vcc3: vcc3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- hsusb1_phy: hsusb1_phy { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <®_vcc3>; +- #phy-cells = <0>; +- }; +-}; +- +-&omap3_pmx_wkup { +- pinctrl-names = "default"; +- +- lan9221_pins: pinmux_lan9221_pins { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ +- >; +- }; +- +- tsc2048_pins: pinmux_tsc2048_pins { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a16, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot6.gpio_8 */ +- >; +- }; +- +- mmc1cd_pins: pinmux_mmc1cd_pins { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 */ +- >; +- }; +-}; +- +-&omap3_pmx_core { +- pinctrl-names = "default"; +- +- uart1_pins: pinmux_uart1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ +- OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ +- OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ +- OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ +- >; +- }; +- +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clkx.uart2_tx */ +- OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ +- >; +- }; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ +- OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21ba ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ +- OMAP3_CORE1_IOPAD(0x21bc ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ +- >; +- }; +- +- i2c2_pins: pinmux_i2c2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */ +- OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */ +- >; +- }; +- +- i2c3_pins: pinmux_i2c3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ +- OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ +- >; +- }; +- +- hsusb1_pins: pinmux_hsusb1_pins { +- pinctrl-single,pins = < +- +- /* GPIO 182 controls USB-Hub reset. But USB-Phy its +- * reset can't be controlled. So we clamp this GPIO to +- * high (PIN_OFF_OUTPUT_HIGH) to always enable USB-Hub. +- */ +- +- OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT_PULLUP | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcspi2_cs1.gpio_182 */ +- >; +- }; +- +- hsusb_otg_pins: pinmux_hsusb_otg_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ +- OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ +- OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ +- OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ +- OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ +- OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ +- OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ +- OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ +- OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ +- OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ +- OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ +- OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ +- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ +- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ +- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ +- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ +- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ +- >; +- }; +- +- spi2_pins: pinmux_spi2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_clk.mcspi2_clk */ +- OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_simo.mcspi2_simo */ +- OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_somi.mcspi2_somi */ +- OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0.mcspi2_cs0 */ +- >; +- }; +-}; +- +-&omap3_pmx_core2 { +- pinctrl-names = "default"; +- +- hsusb1_2_pins: pinmux_hsusb1_2_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ +- OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ +- OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */ +- OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */ +- OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */ +- OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */ +- OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */ +- OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */ +- OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */ +- OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */ +- OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */ +- OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */ +- >; +- }; +- +- gpio1_pins: pinmux_gpio1_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25fa, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* etk_d15.gpio_29 */ +- >; +- }; +- +-}; +- +-&gpio1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio1_pins>; +-}; +- +-&gpio6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&hsusb1_pins>; +-}; +- +-&i2c1 { +- clock-frequency = <2600000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- interrupt-parent = <&intc>; +- +- twl_audio: audio { +- compatible = "ti,twl4030-audio"; +- codec { +- }; +- }; +- }; +-}; +- +-#include "twl4030.dtsi" +-#include "twl4030_omap3.dtsi" +- +-&twl { +- vmmc1: regulator-vmmc1 { +- regulator-always-on; +- }; +- +- vdd1: regulator-vdd1 { +- regulator-always-on; +- }; +- +- vdd2: regulator-vdd2 { +- regulator-always-on; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <2600000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +-}; +- +-&i2c3 { +- clock-frequency = <2600000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- gpiom1: gpio@20 { +- compatible = "microchip,mcp23017"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x20>; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +-}; +- +-&uart4 { +- status = "disabled"; +-}; +- +-&mmc1 { +- cd-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; +- cd-inverted; +- vmmc-supply = <&vmmc1>; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins &mmc1cd_pins>; +- cap-sdio-irq; +- cap-sd-highspeed; +- cap-mmc-highspeed; +-}; +- +-&mmc2 { +- status = "disabled"; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-&mcspi2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pins>; +- +- tsc2046@0 { +- reg = <0>; /* CS0 */ +- compatible = "ti,tsc2046"; +- interrupt-parent = <&gpio1>; +- interrupts = <8 0>; /* boot6 / gpio_8 */ +- spi-max-frequency = <1000000>; +- pendown-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- vcc-supply = <®_vcc3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsc2048_pins>; +- +- ti,x-min = /bits/ 16 <300>; +- ti,x-max = /bits/ 16 <3000>; +- ti,y-min = /bits/ 16 <600>; +- ti,y-max = /bits/ 16 <3600>; +- ti,x-plate-ohms = /bits/ 16 <80>; +- ti,pressure-max = /bits/ 16 <255>; +- ti,swap-xy; +- +- wakeup-source; +- }; +-}; +- +-&usbhsehci { +- phys = <&hsusb1_phy>; +-}; +- +-&usbhshost { +- pinctrl-names = "default"; +- pinctrl-0 = <&hsusb1_2_pins>; +- num-ports = <2>; +- port1-mode = "ehci-phy"; +-}; +- +-&usb_otg_hs { +- pinctrl-names = "default"; +- pinctrl-0 = <&hsusb_otg_pins>; +- interface-type = <0>; +- usb-phy = <&usb2_phy>; +- phys = <&usb2_phy>; +- phy-names = "usb2-phy"; +- mode = <3>; +- power = <50>; +-}; +- +-&mcbsp2 { +- status = "okay"; +-}; +- +-&gpmc { +- ranges = <0 0 0x30000000 0x1000000>, +- <7 0 0x15000000 0x01000000>; +- +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- nand-bus-width = <16>; +- ti,nand-ecc-opt = "bch8"; +- /* no elm on omap3 */ +- +- gpmc,mux-add-data = <0>; +- gpmc,device-width = <2>; +- gpmc,wait-pin = <0>; +- gpmc,wait-monitoring-ns = <0>; +- gpmc,burst-length= <4>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <100>; +- gpmc,cs-wr-off-ns = <100>; +- gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <100>; +- gpmc,adv-wr-off-ns = <100>; +- gpmc,oe-on-ns = <5>; +- gpmc,oe-off-ns = <75>; +- gpmc,we-on-ns = <5>; +- gpmc,we-off-ns = <75>; +- gpmc,rd-cycle-ns = <100>; +- gpmc,wr-cycle-ns = <100>; +- gpmc,access-ns = <60>; +- gpmc,page-burst-access-ns = <5>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-samecsen; +- gpmc,cycle2cycle-delay-ns = <50>; +- gpmc,wr-data-mux-bus-ns = <75>; +- gpmc,wr-access-ns = <155>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "MLO"; +- reg = <0 0x80000>; +- }; +- +- partition@80000 { +- label = "u-boot"; +- reg = <0x80000 0x1e0000>; +- }; +- +- partition@260000 { +- label = "u-boot-environment"; +- reg = <0x260000 0x20000>; +- }; +- +- partition@280000 { +- label = "kernel"; +- reg = <0x280000 0x500000>; +- }; +- +- partition@780000 { +- label = "filesystem"; +- reg = <0x780000 0xf880000>; +- }; +- }; +- +- ethernet@7,0 { +- compatible = "smsc,lan9221", "smsc,lan9115"; +- bank-width = <2>; +- gpmc,mux-add-data = <2>; +- gpmc,cs-on-ns = <10>; +- gpmc,cs-rd-off-ns = <60>; +- gpmc,cs-wr-off-ns = <60>; +- gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <10>; +- gpmc,adv-wr-off-ns = <10>; +- gpmc,oe-on-ns = <10>; +- gpmc,oe-off-ns = <60>; +- gpmc,we-on-ns = <10>; +- gpmc,we-off-ns = <60>; +- gpmc,rd-cycle-ns = <100>; +- gpmc,wr-cycle-ns = <100>; +- gpmc,access-ns = <50>; +- gpmc,page-burst-access-ns = <5>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <75>; +- gpmc,wr-data-mux-bus-ns = <15>; +- gpmc,wr-access-ns = <75>; +- gpmc,cycle2cycle-samecsen; +- gpmc,cycle2cycle-diffcsen; +- vddvario-supply = <®_vcc3>; +- vdd33a-supply = <®_vcc3>; +- reg-io-width = <4>; +- interrupt-parent = <&gpio5>; +- interrupts = <1 0x2>; +- reg = <7 0 0xff>; +- pinctrl-names = "default"; +- pinctrl-0 = <&lan9221_pins>; +- phy-mode = "mii"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-lilly-dbb056.dts b/scripts/dtc/include-prefixes/arm/omap3-lilly-dbb056.dts +deleted file mode 100644 +index ecb4ef738e07..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-lilly-dbb056.dts ++++ /dev/null +@@ -1,166 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2014 Christoph Fritz +- */ +-/dts-v1/; +- +-#include "omap3-lilly-a83x.dtsi" +- +-/ { +- model = "INCOstartec LILLY-DBB056 (DM3730)"; +- compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +-}; +- +-&twl { +- vaux2: regulator-vaux2 { +- compatible = "ti,twl4030-vaux2"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +-}; +- +-&omap3_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_pins>; +- +- lan9117_pins: pinmux_lan9117_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* cam_fld.gpio_98 */ +- >; +- }; +- +- gpio4_pins: pinmux_gpio4_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* cam_xclkb.gpio_111 -> sja1000 IRQ */ +- >; +- }; +- +- gpio5_pins: pinmux_gpio5_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x218c, PIN_OUTPUT | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcbsp1_clk.gpio_156 -> enable DSS */ +- >; +- }; +- +- lcd_pins: pinmux_lcd_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ +- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ +- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ +- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ +- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ +- OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ +- OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ +- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ +- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ +- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ +- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ +- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ +- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ +- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ +- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ +- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ +- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ +- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ +- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ +- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ +- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ +- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ +- >; +- }; +- +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ +- OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ +- OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ +- OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ +- OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ +- OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ +- OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ +- OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ +- OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ +- OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ +- OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 -> wp */ +- OMAP3_CORE1_IOPAD(0x219c, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_rts_sd.gpio_164 -> cd */ +- >; +- }; +- +- spi1_pins: pinmux_spi1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ +- OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ +- OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ +- OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ +- >; +- }; +-}; +- +-&gpio4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio4_pins>; +-}; +- +-&gpio5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio5_pins>; +-}; +- +-&mmc2 { +- status = "okay"; +- bus-width = <4>; +- vmmc-supply = <&vmmc1>; +- cd-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio_164 */ +- wp-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* gpio_163 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- ti,dual-volt; +-}; +- +-&mcspi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins>; +-}; +- +-&gpmc { +- ranges = <0 0 0x30000000 0x1000000>, /* nand assigned by COM a83x */ +- <4 0 0x20000000 0x01000000>, +- <7 0 0x15000000 0x01000000>; /* eth assigend by COM a83x */ +- +- ethernet@4,0 { +- compatible = "smsc,lan9117", "smsc,lan9115"; +- bank-width = <2>; +- gpmc,mux-add-data = <2>; +- gpmc,cs-on-ns = <10>; +- gpmc,cs-rd-off-ns = <65>; +- gpmc,cs-wr-off-ns = <65>; +- gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <10>; +- gpmc,adv-wr-off-ns = <10>; +- gpmc,oe-on-ns = <10>; +- gpmc,oe-off-ns = <65>; +- gpmc,we-on-ns = <10>; +- gpmc,we-off-ns = <65>; +- gpmc,rd-cycle-ns = <100>; +- gpmc,wr-cycle-ns = <100>; +- gpmc,access-ns = <60>; +- gpmc,page-burst-access-ns = <5>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <75>; +- gpmc,wr-data-mux-bus-ns = <15>; +- gpmc,wr-access-ns = <75>; +- gpmc,cycle2cycle-samecsen; +- gpmc,cycle2cycle-diffcsen; +- vddvario-supply = <®_vcc3>; +- vdd33a-supply = <®_vcc3>; +- reg-io-width = <4>; +- interrupt-parent = <&gpio4>; +- interrupts = <2 0x2>; +- reg = <4 0 0xff>; +- pinctrl-names = "default"; +- pinctrl-0 = <&lan9117_pins>; +- phy-mode = "mii"; +- smsc,force-internal-phy; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-n9.dts b/scripts/dtc/include-prefixes/arm/omap3-n9.dts +deleted file mode 100644 +index d211bcc31174..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-n9.dts ++++ /dev/null +@@ -1,84 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * omap3-n9.dts - Device Tree file for Nokia N9 +- * +- * Written by: Aaro Koskinen +- */ +- +-/dts-v1/; +- +-#include "omap3-n950-n9.dtsi" +-#include +- +-/ { +- model = "Nokia N9"; +- compatible = "nokia,omap3-n9", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +-}; +- +-&i2c2 { +- smia_1: camera@10 { +- compatible = "nokia,smia"; +- reg = <0x10>; +- /* No reset gpio */ +- vana-supply = <&vaux3>; +- clocks = <&isp 0>; +- clock-frequency = <9600000>; +- flash-leds = <&as3645a_flash &as3645a_indicator>; +- port { +- smia_1_1: endpoint { +- link-frequencies = /bits/ 64 <199200000 210000000 499200000>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- remote-endpoint = <&csi2a_ep>; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- ak8975@f { +- compatible = "asahi-kasei,ak8975"; +- reg = <0x0f>; +- }; +-}; +- +-&isp { +- vdd-csiphy1-supply = <&vaux2>; +- vdd-csiphy2-supply = <&vaux2>; +- ports { +- port@2 { +- reg = <2>; +- csi2a_ep: endpoint { +- remote-endpoint = <&smia_1_1>; +- clock-lanes = <2>; +- data-lanes = <1 3>; +- crc = <1>; +- lane-polarities = <1 1 1>; +- }; +- }; +- }; +-}; +- +-&modem { +- compatible = "nokia,n9-modem"; +-}; +- +-&lis302 { +- st,axis-x = <1>; /* LIS3_DEV_X */ +- st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */ +- st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ +- +- st,min-limit-x = <(-46)>; +- st,min-limit-y = <3>; +- st,min-limit-z = <3>; +- +- st,max-limit-x = <(-3)>; +- st,max-limit-y = <46>; +- st,max-limit-z = <46>; +-}; +- +-&twl_keypad { +- linux,keymap = < MATRIX_KEY(6, 8, KEY_VOLUMEUP) +- MATRIX_KEY(7, 8, KEY_VOLUMEDOWN) +- >; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-n900.dts b/scripts/dtc/include-prefixes/arm/omap3-n900.dts +deleted file mode 100644 +index d40c3d2c4914..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-n900.dts ++++ /dev/null +@@ -1,1194 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2013 Pavel Machek +- * Copyright (C) 2013-2014 Aaro Koskinen +- */ +- +-/dts-v1/; +- +-#include "omap34xx.dtsi" +-#include +-#include +- +-/* +- * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall +- * for omap AES HW crypto support. When linux kernel try to access memory of AES +- * blocks then kernel receive "Unhandled fault: external abort on non-linefetch" +- * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no +- * crash anymore) omap AES support will be disabled for all Nokia N900 devices. +- * There is "unofficial" version of bootloader which enables AES in L3 firewall +- * but it is not widely used and to prevent kernel crash rather AES is disabled. +- * There is also no runtime detection code if AES is disabled in L3 firewall... +- */ +-&aes1_target { +- status = "disabled"; +-}; +- +-&aes2_target { +- status = "disabled"; +-}; +- +-/ { +- model = "Nokia N900"; +- compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3"; +- +- aliases { +- i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- display0 = &lcd; +- display1 = &tv; +- }; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&vcc>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- heartbeat { +- label = "debug::sleep"; +- gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* 162 */ +- linux,default-trigger = "default-on"; +- pinctrl-names = "default"; +- pinctrl-0 = <&debug_leds>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- camera_lens_cover { +- label = "Camera Lens Cover"; +- gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */ +- linux,input-type = ; +- linux,code = ; +- linux,can-disable; +- }; +- +- camera_focus { +- label = "Camera Focus"; +- gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */ +- linux,code = ; +- linux,can-disable; +- }; +- +- camera_capture { +- label = "Camera Capture"; +- gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */ +- linux,code = ; +- linux,can-disable; +- }; +- +- lock_button { +- label = "Lock Button"; +- gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */ +- linux,code = ; +- linux,can-disable; +- }; +- +- keypad_slide { +- label = "Keypad Slide"; +- gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */ +- linux,input-type = ; +- linux,code = ; +- linux,can-disable; +- }; +- +- proximity_sensor { +- label = "Proximity Sensor"; +- gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */ +- linux,input-type = ; +- linux,code = ; +- linux,can-disable; +- }; +- +- machine_cover { +- label = "Machine Cover"; +- gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* 160 */ +- linux,input-type = ; +- linux,code = ; +- linux,can-disable; +- }; +- }; +- +- isp1707: isp1707 { +- compatible = "nxp,isp1707"; +- nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; +- usb-phy = <&usb2_phy>; +- }; +- +- tv: connector { +- compatible = "composite-video-connector"; +- label = "tv"; +- +- port { +- tv_connector_in: endpoint { +- remote-endpoint = <&venc_out>; +- }; +- }; +- }; +- +- sound: n900-audio { +- compatible = "nokia,n900-audio"; +- +- nokia,cpu-dai = <&mcbsp2>; +- nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>; +- nokia,headphone-amplifier = <&tpa6130a2>; +- +- tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */ +- jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */ +- eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */ +- speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>; +- }; +- +- battery: n900-battery { +- compatible = "nokia,n900-battery"; +- io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>; +- io-channel-names = "temp", "bsi", "vbat"; +- }; +- +- pwm9: dmtimer-pwm { +- compatible = "ti,omap-dmtimer-pwm"; +- #pwm-cells = <3>; +- ti,timers = <&timer9>; +- ti,clock-source = <0x00>; /* timer_sys_ck */ +- }; +- +- ir: n900-ir { +- compatible = "nokia,n900-ir"; +- pwms = <&pwm9 0 26316 0>; /* 38000 Hz */ +- }; +- +- rom_rng: rng { +- compatible = "nokia,n900-rom-rng"; +- clocks = <&rng_ick>; +- clock-names = "ick"; +- }; +- +- /* controlled (enabled/disabled) directly by bcm2048 and wl1251 */ +- vctcxo: vctcxo { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <38400000>; +- }; +-}; +- +-&isp { +- vdds_csib-supply = <&vaux2>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&camera_pins>; +- +- ports { +- port@1 { +- reg = <1>; +- +- csi_isp: endpoint { +- remote-endpoint = <&csi_cam1>; +- bus-type = <3>; /* CCP2 */ +- clock-lanes = <1>; +- data-lanes = <0>; +- lane-polarity = <0 0>; +- /* Select strobe = <1> for back camera, <0> for front camera */ +- strobe = <1>; +- }; +- }; +- }; +-}; +- +-&omap3_pmx_core { +- pinctrl-names = "default"; +- +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ +- OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */ +- OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ +- OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ +- >; +- }; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx */ +- OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx */ +- >; +- }; +- +- ethernet_pins: pinmux_ethernet_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ +- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */ +- OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ +- >; +- }; +- +- gpmc_pins: pinmux_gpmc_pins { +- pinctrl-single,pins = < +- +- /* address lines */ +- OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ +- OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ +- OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ +- +- /* data lines, gpmc_d0..d7 not muxable according to TRM */ +- OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ +- OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ +- OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ +- OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ +- OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ +- OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ +- OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ +- OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ +- +- /* +- * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable +- * according to TRM. OneNAND seems to require PIN_INPUT on clock. +- */ +- OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ +- OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ +- OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ +- >; +- }; +- +- i2c2_pins: pinmux_i2c2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ +- OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ +- >; +- }; +- +- i2c3_pins: pinmux_i2c3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ +- OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ +- >; +- }; +- +- debug_leds: pinmux_debug_led_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */ +- >; +- }; +- +- mcspi4_pins: pinmux_mcspi4_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ +- OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */ +- OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */ +- OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ +- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */ +- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0 */ +- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ +- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ +- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ +- >; +- }; +- +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ +- OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ +- OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */ +- OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */ +- OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */ +- OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */ +- OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */ +- OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */ +- OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */ +- OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */ +- >; +- }; +- +- acx565akm_pins: pinmux_acx565akm_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */ +- >; +- }; +- +- dss_sdi_pins: pinmux_dss_sdi_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */ +- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */ +- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE1) /* dss_data12.sdi_dat2n */ +- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE1) /* dss_data13.sdi_dat2p */ +- +- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE1) /* dss_data22.sdi_clkp */ +- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */ +- >; +- }; +- +- wl1251_pins: pinmux_wl1251 { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */ +- OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */ +- >; +- }; +- +- ssi_pins: pinmux_ssi { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ +- OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ +- OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ +- OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ +- OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ +- OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ +- OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ +- OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ +- >; +- }; +- +- modem_pins: pinmux_modem { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */ +- OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */ +- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */ +- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */ +- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */ +- OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */ +- >; +- }; +- +- camera_pins: pinmux_camera { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x210c, PIN_OUTPUT | MUX_MODE7) /* cam_hs */ +- OMAP3_CORE1_IOPAD(0x210e, PIN_OUTPUT | MUX_MODE7) /* cam_vs */ +- OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */ +- OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE7) /* cam_d4 */ +- OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6 */ +- OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7 */ +- OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE0) /* cam_d8 */ +- OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE0) /* cam_d9 */ +- OMAP3_CORE1_IOPAD(0x212a, PIN_OUTPUT | MUX_MODE7) /* cam_d10 */ +- OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE7) /* cam_xclkb */ +- OMAP3_CORE1_IOPAD(0x2132, PIN_OUTPUT | MUX_MODE0) /* cam_strobe */ +- >; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- +- clock-frequency = <2200000>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- interrupt-parent = <&intc>; +- }; +-}; +- +-#include "twl4030.dtsi" +-#include "twl4030_omap3.dtsi" +- +-&vaux1 { +- regulator-name = "V28"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ +- regulator-always-on; /* due to battery cover sensor */ +-}; +- +-&vaux2 { +- regulator-name = "VCSI"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ +-}; +- +-&vaux3 { +- regulator-name = "VMMC2_30"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <3000000>; +- regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ +-}; +- +-&vaux4 { +- regulator-name = "VCAM_ANA_28"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ +-}; +- +-&vmmc1 { +- regulator-name = "VMMC1"; +- regulator-min-microvolt = <1850000>; +- regulator-max-microvolt = <3150000>; +- regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ +-}; +- +-&vmmc2 { +- regulator-name = "V28_A"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <3000000>; +- regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ +- regulator-always-on; /* due VIO leak to AIC34 VDDs */ +-}; +- +-&vpll1 { +- regulator-name = "VPLL"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ +- regulator-always-on; +-}; +- +-&vpll2 { +- regulator-name = "VSDI_CSI"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ +- regulator-always-on; +-}; +- +-&vsim { +- regulator-name = "VMMC2_IO_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ +-}; +- +-&vio { +- regulator-name = "VIO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +-}; +- +-&vintana1 { +- regulator-name = "VINTANA1"; +- /* fixed to 1500000 */ +- regulator-always-on; +-}; +- +-&vintana2 { +- regulator-name = "VINTANA2"; +- regulator-min-microvolt = <2750000>; +- regulator-max-microvolt = <2750000>; +- regulator-always-on; +-}; +- +-&vintdig { +- regulator-name = "VINTDIG"; +- /* fixed to 1500000 */ +- regulator-always-on; +-}; +- +-/* First two dma channels are reserved on secure omap3 */ +-&sdma { +- dma-channel-mask = <0xfffffffc>; +-}; +- +-&twl { +- twl_audio: audio { +- compatible = "ti,twl4030-audio"; +- ti,enable-vibra = <1>; +- }; +- +- twl_power: power { +- compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off"; +- ti,use_poweroff; +- }; +-}; +- +-&twl_keypad { +- linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q) +- MATRIX_KEY(0x00, 0x01, KEY_O) +- MATRIX_KEY(0x00, 0x02, KEY_P) +- MATRIX_KEY(0x00, 0x03, KEY_COMMA) +- MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE) +- MATRIX_KEY(0x00, 0x06, KEY_A) +- MATRIX_KEY(0x00, 0x07, KEY_S) +- +- MATRIX_KEY(0x01, 0x00, KEY_W) +- MATRIX_KEY(0x01, 0x01, KEY_D) +- MATRIX_KEY(0x01, 0x02, KEY_F) +- MATRIX_KEY(0x01, 0x03, KEY_G) +- MATRIX_KEY(0x01, 0x04, KEY_H) +- MATRIX_KEY(0x01, 0x05, KEY_J) +- MATRIX_KEY(0x01, 0x06, KEY_K) +- MATRIX_KEY(0x01, 0x07, KEY_L) +- +- MATRIX_KEY(0x02, 0x00, KEY_E) +- MATRIX_KEY(0x02, 0x01, KEY_DOT) +- MATRIX_KEY(0x02, 0x02, KEY_UP) +- MATRIX_KEY(0x02, 0x03, KEY_ENTER) +- MATRIX_KEY(0x02, 0x05, KEY_Z) +- MATRIX_KEY(0x02, 0x06, KEY_X) +- MATRIX_KEY(0x02, 0x07, KEY_C) +- MATRIX_KEY(0x02, 0x08, KEY_F9) +- +- MATRIX_KEY(0x03, 0x00, KEY_R) +- MATRIX_KEY(0x03, 0x01, KEY_V) +- MATRIX_KEY(0x03, 0x02, KEY_B) +- MATRIX_KEY(0x03, 0x03, KEY_N) +- MATRIX_KEY(0x03, 0x04, KEY_M) +- MATRIX_KEY(0x03, 0x05, KEY_SPACE) +- MATRIX_KEY(0x03, 0x06, KEY_SPACE) +- MATRIX_KEY(0x03, 0x07, KEY_LEFT) +- +- MATRIX_KEY(0x04, 0x00, KEY_T) +- MATRIX_KEY(0x04, 0x01, KEY_DOWN) +- MATRIX_KEY(0x04, 0x02, KEY_RIGHT) +- MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL) +- MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT) +- MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT) +- MATRIX_KEY(0x04, 0x08, KEY_F10) +- +- MATRIX_KEY(0x05, 0x00, KEY_Y) +- MATRIX_KEY(0x05, 0x08, KEY_F11) +- +- MATRIX_KEY(0x06, 0x00, KEY_U) +- +- MATRIX_KEY(0x07, 0x00, KEY_I) +- MATRIX_KEY(0x07, 0x01, KEY_F7) +- MATRIX_KEY(0x07, 0x02, KEY_F8) +- >; +-}; +- +-&twl_gpio { +- ti,pullups = <0x0>; +- ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */ +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- +- clock-frequency = <100000>; +- +- tlv320aic3x: tlv320aic3x@18 { +- compatible = "ti,tlv320aic3x"; +- reg = <0x18>; +- reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* 60 */ +- ai3x-gpio-func = < +- 0 /* AIC3X_GPIO1_FUNC_DISABLED */ +- 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */ +- >; +- +- AVDD-supply = <&vmmc2>; +- DRVDD-supply = <&vmmc2>; +- IOVDD-supply = <&vio>; +- DVDD-supply = <&vio>; +- +- ai3x-micbias-vg = <1>; +- }; +- +- tlv320aic3x_aux: tlv320aic3x@19 { +- compatible = "ti,tlv320aic3x"; +- reg = <0x19>; +- reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* 60 */ +- +- AVDD-supply = <&vmmc2>; +- DRVDD-supply = <&vmmc2>; +- IOVDD-supply = <&vio>; +- DVDD-supply = <&vio>; +- +- ai3x-micbias-vg = <2>; +- }; +- +- tsl2563: tsl2563@29 { +- compatible = "amstaos,tsl2563"; +- reg = <0x29>; +- +- amstaos,cover-comp-gain = <16>; +- }; +- +- adp1653: led-controller@30 { +- compatible = "adi,adp1653"; +- reg = <0x30>; +- enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */ +- +- flash { +- flash-timeout-us = <500000>; +- flash-max-microamp = <320000>; +- led-max-microamp = <50000>; +- }; +- indicator { +- led-max-microamp = <17500>; +- }; +- }; +- +- lp5523: lp5523@32 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "national,lp5523"; +- reg = <0x32>; +- clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ +- enable-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */ +- +- led@0 { +- reg = <0>; +- chan-name = "lp5523:kb1"; +- led-cur = /bits/ 8 <50>; +- max-cur = /bits/ 8 <100>; +- color = ; +- function = LED_FUNCTION_KBD_BACKLIGHT; +- }; +- +- led@1 { +- reg = <1>; +- chan-name = "lp5523:kb2"; +- led-cur = /bits/ 8 <50>; +- max-cur = /bits/ 8 <100>; +- color = ; +- function = LED_FUNCTION_KBD_BACKLIGHT; +- }; +- +- led@2 { +- reg = <2>; +- chan-name = "lp5523:kb3"; +- led-cur = /bits/ 8 <50>; +- max-cur = /bits/ 8 <100>; +- color = ; +- function = LED_FUNCTION_KBD_BACKLIGHT; +- }; +- +- led@3 { +- reg = <3>; +- chan-name = "lp5523:kb4"; +- led-cur = /bits/ 8 <50>; +- max-cur = /bits/ 8 <100>; +- color = ; +- function = LED_FUNCTION_KBD_BACKLIGHT; +- }; +- +- led@4 { +- reg = <4>; +- chan-name = "lp5523:b"; +- led-cur = /bits/ 8 <50>; +- max-cur = /bits/ 8 <100>; +- color = ; +- function = LED_FUNCTION_STATUS; +- }; +- +- led@5 { +- reg = <5>; +- chan-name = "lp5523:g"; +- led-cur = /bits/ 8 <50>; +- max-cur = /bits/ 8 <100>; +- color = ; +- function = LED_FUNCTION_STATUS; +- }; +- +- led@6 { +- reg = <6>; +- chan-name = "lp5523:r"; +- led-cur = /bits/ 8 <50>; +- max-cur = /bits/ 8 <100>; +- color = ; +- function = LED_FUNCTION_STATUS; +- }; +- +- led@7 { +- reg = <7>; +- chan-name = "lp5523:kb5"; +- led-cur = /bits/ 8 <50>; +- max-cur = /bits/ 8 <100>; +- color = ; +- function = LED_FUNCTION_KBD_BACKLIGHT; +- }; +- +- led@8 { +- reg = <8>; +- chan-name = "lp5523:kb6"; +- led-cur = /bits/ 8 <50>; +- max-cur = /bits/ 8 <100>; +- color = ; +- function = LED_FUNCTION_KBD_BACKLIGHT; +- }; +- }; +- +- bq27200: bq27200@55 { +- compatible = "ti,bq27200"; +- reg = <0x55>; +- power-supplies = <&bq24150a>; +- }; +- +- /* Stereo headphone amplifier */ +- tpa6130a2: tpa6130a2@60 { +- compatible = "ti,tpa6130a2"; +- reg = <0x60>; +- +- Vdd-supply = <&vmmc2>; +- +- power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */ +- }; +- +- si4713: si4713@63 { +- compatible = "silabs,si4713"; +- reg = <0x63>; +- +- interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */ +- reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */ +- vio-supply = <&vio>; +- vdd-supply = <&vaux1>; +- }; +- +- bq24150a: bq24150a@6b { +- compatible = "ti,bq24150a"; +- reg = <0x6b>; +- +- ti,current-limit = <100>; +- ti,weak-battery-voltage = <3400>; +- ti,battery-regulation-voltage = <4200>; +- ti,charge-current = <650>; +- ti,termination-current = <100>; +- ti,resistor-sense = <68>; +- +- ti,usb-charger-detection = <&isp1707>; +- }; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- +- clock-frequency = <400000>; +- +- lis302dl: lis3lv02d@1d { +- compatible = "st,lis3lv02d"; +- reg = <0x1d>; +- +- Vdd-supply = <&vaux1>; +- Vdd_IO-supply = <&vio>; +- +- interrupt-parent = <&gpio6>; +- interrupts = <21 20>; /* 181 and 180 */ +- +- /* click flags */ +- st,click-single-x; +- st,click-single-y; +- st,click-single-z; +- +- /* Limits are 0.5g * value */ +- st,click-threshold-x = <8>; +- st,click-threshold-y = <8>; +- st,click-threshold-z = <10>; +- +- /* Click must be longer than time limit */ +- st,click-time-limit = <9>; +- +- /* Kind of debounce filter */ +- st,click-latency = <50>; +- +- /* Interrupt line 2 for click detection */ +- st,irq2-click; +- +- st,wakeup-x-hi; +- st,wakeup-y-hi; +- st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */ +- +- st,wakeup2-z-hi; +- st,wakeup2-threshold = <(900/18)>; /* millig-value / 18 to get HW values */ +- +- st,hipass1-disable; +- st,hipass2-disable; +- +- st,axis-x = <1>; /* LIS3_DEV_X */ +- st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */ +- st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ +- +- st,min-limit-x = <(-32)>; +- st,min-limit-y = <3>; +- st,min-limit-z = <3>; +- +- st,max-limit-x = <(-3)>; +- st,max-limit-y = <32>; +- st,max-limit-z = <32>; +- }; +- +- cam1: camera@3e { +- compatible = "toshiba,et8ek8"; +- reg = <0x3e>; +- +- vana-supply = <&vaux4>; +- +- clocks = <&isp 0>; +- clock-names = "extclk"; +- clock-frequency = <9600000>; +- +- reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ +- +- lens-focus = <&ad5820>; +- +- port { +- csi_cam1: endpoint { +- bus-type = <3>; /* CCP2 */ +- strobe = <1>; +- clock-inv = <0>; +- crc = <1>; +- +- remote-endpoint = <&csi_isp>; +- }; +- }; +- }; +- +- /* D/A converter for auto-focus */ +- ad5820: dac@c { +- compatible = "adi,ad5820"; +- reg = <0x0c>; +- +- VANA-supply = <&vaux4>; +- +- #io-channel-cells = <0>; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <&vmmc1>; +- bus-width = <4>; +-}; +- +-/* most boards use vaux3, only some old versions use vmmc2 instead */ +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- vmmc-supply = <&vaux3>; +- vqmmc-supply = <&vsim>; +- bus-width = <8>; +- non-removable; +- no-sdio; +- no-sd; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-&gpmc { +- ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */ +- <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&gpmc_pins>; +- +- /* sys_ndmareq1 could be used by the driver, not as gpio65 though */ +- onenand@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ti,omap2-onenand"; +- reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ +- +- /* +- * These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported +- * bootloader set values when booted with v5.1 +- * (OneNAND Manufacturer: Samsung): +- * +- * cs0 GPMC_CS_CONFIG1: 0xfb001202 +- * cs0 GPMC_CS_CONFIG2: 0x00111100 +- * cs0 GPMC_CS_CONFIG3: 0x00020200 +- * cs0 GPMC_CS_CONFIG4: 0x11001102 +- * cs0 GPMC_CS_CONFIG5: 0x03101616 +- * cs0 GPMC_CS_CONFIG6: 0x90060000 +- */ +- gpmc,sync-read; +- gpmc,sync-write; +- gpmc,burst-length = <16>; +- gpmc,burst-read; +- gpmc,burst-wrap; +- gpmc,burst-write; +- gpmc,device-width = <2>; +- gpmc,mux-add-data = <2>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <102>; +- gpmc,cs-wr-off-ns = <102>; +- gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <12>; +- gpmc,adv-wr-off-ns = <12>; +- gpmc,oe-on-ns = <12>; +- gpmc,oe-off-ns = <102>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <102>; +- gpmc,rd-cycle-ns = <132>; +- gpmc,wr-cycle-ns = <132>; +- gpmc,access-ns = <96>; +- gpmc,page-burst-access-ns = <18>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,wait-monitoring-ns = <0>; +- gpmc,clk-activation-ns = <6>; +- gpmc,wr-data-mux-bus-ns = <36>; +- gpmc,wr-access-ns = <96>; +- gpmc,sync-clk-ps = <15000>; +- +- /* +- * MTD partition table corresponding to Nokia's +- * Maemo 5 (Fremantle) release. +- */ +- partition@0 { +- label = "bootloader"; +- reg = <0x00000000 0x00020000>; +- read-only; +- }; +- partition@1 { +- label = "config"; +- reg = <0x00020000 0x00060000>; +- }; +- partition@2 { +- label = "log"; +- reg = <0x00080000 0x00040000>; +- }; +- partition@3 { +- label = "kernel"; +- reg = <0x000c0000 0x00200000>; +- }; +- partition@4 { +- label = "initfs"; +- reg = <0x002c0000 0x00200000>; +- }; +- partition@5 { +- label = "rootfs"; +- reg = <0x004c0000 0x0fb40000>; +- }; +- }; +- +- /* Ethernet is on some early development boards and qemu */ +- ethernet@gpmc { +- compatible = "smsc,lan91c94"; +- interrupt-parent = <&gpio2>; +- interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */ +- reg = <1 0 0xf>; /* 16 byte IO range */ +- bank-width = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <ðernet_pins>; +- power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* gpio86 */ +- reset-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio164 */ +- gpmc,device-width = <2>; +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <48>; +- gpmc,cs-wr-off-ns = <24>; +- gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <0>; +- gpmc,adv-wr-off-ns = <0>; +- gpmc,we-on-ns = <12>; +- gpmc,we-off-ns = <18>; +- gpmc,oe-on-ns = <12>; +- gpmc,oe-off-ns = <48>; +- gpmc,page-burst-access-ns = <0>; +- gpmc,access-ns = <42>; +- gpmc,rd-cycle-ns = <180>; +- gpmc,wr-cycle-ns = <180>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,wait-monitoring-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-access-ns = <0>; +- gpmc,wr-data-mux-bus-ns = <12>; +- }; +-}; +- +-&mcspi1 { +- /* +- * For some reason, touchscreen is necessary for screen to work at +- * all on real hw. It works well without it on emulator. +- * +- * Also... order in the device tree actually matters here. +- */ +- tsc2005@0 { +- compatible = "ti,tsc2005"; +- spi-max-frequency = <6000000>; +- reg = <0>; +- +- vio-supply = <&vio>; +- +- reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */ +- interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>; /* 100 */ +- +- touchscreen-fuzz-x = <4>; +- touchscreen-fuzz-y = <7>; +- touchscreen-fuzz-pressure = <2>; +- touchscreen-size-x = <4096>; +- touchscreen-size-y = <4096>; +- touchscreen-max-pressure = <2048>; +- +- ti,x-plate-ohms = <280>; +- ti,esd-recovery-timeout-ms = <8000>; +- }; +- +- lcd: acx565akm@2 { +- compatible = "sony,acx565akm"; +- spi-max-frequency = <6000000>; +- reg = <2>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&acx565akm_pins>; +- +- label = "lcd"; +- reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */ +- +- port { +- lcd_in: endpoint { +- remote-endpoint = <&sdi_out>; +- }; +- }; +- }; +-}; +- +-&mcspi4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcspi4_pins>; +- +- wl1251@0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&wl1251_pins>; +- +- vio-supply = <&vio>; +- +- compatible = "ti,wl1251"; +- reg = <0>; +- spi-max-frequency = <48000000>; +- +- spi-cpol; +- spi-cpha; +- +- ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */ +- +- interrupt-parent = <&gpio2>; +- interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */ +- +- clocks = <&vctcxo>; +- }; +-}; +- +-/* RNG not directly accessible on n900, see omap3-rom-rng instead */ +-&rng_target { +- status = "disabled"; +-}; +- +-&usb_otg_hs { +- interface-type = <0>; +- usb-phy = <&usb2_phy>; +- phys = <&usb2_phy>; +- phy-names = "usb2-phy"; +- mode = <2>; +- power = <50>; +-}; +- +-&uart1 { +- status = "disabled"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- +- bcm2048: bluetooth { +- compatible = "brcm,bcm2048-nokia", "nokia,h4p-bluetooth"; +- reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; /* 91 */ +- host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* 101 */ +- bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* 37 */ +- clocks = <&vctcxo>; +- clock-names = "sysclk"; +- }; +-}; +- +-&uart3 { +- interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +-}; +- +-&dss { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_sdi_pins>; +- +- vdds_sdi-supply = <&vaux1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <1>; +- +- sdi_out: endpoint { +- remote-endpoint = <&lcd_in>; +- datapairs = <2>; +- }; +- }; +- }; +-}; +- +-&venc { +- status = "okay"; +- +- vdda-supply = <&vdac>; +- +- port { +- venc_out: endpoint { +- remote-endpoint = <&tv_connector_in>; +- ti,channels = <1>; +- }; +- }; +-}; +- +-&mcbsp2 { +- status = "okay"; +-}; +- +-&ssi_port1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ssi_pins>; +- +- ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ +- +- modem: hsi-client { +- compatible = "nokia,n900-modem"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&modem_pins>; +- +- hsi-channel-ids = <0>, <1>, <2>, <3>; +- hsi-channel-names = "mcsaab-control", +- "speech-control", +- "speech-data", +- "mcsaab-data"; +- hsi-speed-kbps = <55000>; +- hsi-mode = "frame"; +- hsi-flow = "synchronized"; +- hsi-arb-mode = "round-robin"; +- +- interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */ +- +- gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */ +- <&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */ +- <&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */ +- <&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */ +- <&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */ +- gpio-names = "cmt_apeslpx", +- "cmt_rst_rq", +- "cmt_en", +- "cmt_rst", +- "cmt_bsi"; +- }; +-}; +- +-&ssi_port2 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-n950-n9.dtsi b/scripts/dtc/include-prefixes/arm/omap3-n950-n9.dtsi +deleted file mode 100644 +index 7dde9fbb06d3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-n950-n9.dtsi ++++ /dev/null +@@ -1,504 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff) +- * +- * Written by: Aaro Koskinen +- */ +- +-#include "omap36xx.dtsi" +- +-/ { +- cpus { +- cpu@0 { +- cpu0-supply = <&vcc>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; /* 1 GB */ +- }; +- +- vemmc: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "VEMMC"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- gpio = <&gpio5 29 GPIO_ACTIVE_HIGH>; /* gpio line 157 */ +- startup-delay-us = <150>; +- enable-active-high; +- }; +- +- vwlan_fixed: fixedregulator2 { +- compatible = "regulator-fixed"; +- regulator-name = "VWLAN"; +- gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; /* gpio 35 */ +- enable-active-high; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- heartbeat { +- label = "debug::sleep"; +- gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; /* gpio92 */ +- linux,default-trigger = "default-on"; +- pinctrl-names = "default"; +- pinctrl-0 = <&debug_leds>; +- }; +- }; +- +- /* controlled (enabled/disabled) directly by wl1271 */ +- vctcxo: vctcxo { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <38400000>; +- }; +-}; +- +-&omap3_pmx_core { +- accelerator_pins: pinmux_accelerator_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT | MUX_MODE4) /* mcspi2_somi.gpio_180 -> LIS302 INT1 */ +- OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT | MUX_MODE4) /* mcspi2_cs0.gpio_181 -> LIS302 INT2 */ +- >; +- }; +- +- debug_leds: pinmux_debug_led_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE4) /* dss_data22.gpio_92 */ +- >; +- }; +- +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ +- OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ +- OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */ +- OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */ +- OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */ +- OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */ +- >; +- }; +- +- wlan_pins: pinmux_wlan_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE4) /* gpio 35 - wlan enable */ +- OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 - wlan irq */ +- >; +- }; +- +- ssi_pins: pinmux_ssi_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ +- OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ +- OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ +- OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ +- OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ +- OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ +- OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ +- OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ +- >; +- }; +- +- ssi_pins_idle: pinmux_ssi_pins_idle { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7) /* ssi1_dat_tx */ +- OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7) /* ssi1_flag_tx */ +- OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLDOWN | MUX_MODE7) /* ssi1_rdy_tx */ +- OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ +- OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE7) /* ssi1_dat_rx */ +- OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE7) /* ssi1_flag_rx */ +- OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4) /* ssi1_rdy_rx */ +- OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE7) /* ssi1_wake */ +- >; +- }; +- +- modem_pins1: pinmux_modem_core1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | MUX_MODE4) /* gpio_34 (ape_rst_rq) */ +- OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4) /* gpio_88 (cmt_rst_rq) */ +- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4) /* gpio_93 (cmt_apeslpx) */ +- >; +- }; +- +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ +- OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */ +- OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ +- OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ +- >; +- }; +-}; +- +-&omap3_pmx_core2 { +- modem_pins2: pinmux_modem_core2_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* gpio_23 (cmt_en) */ +- >; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <2900000>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- interrupt-parent = <&intc>; +- }; +-}; +- +-/include/ "twl4030.dtsi" +- +-&twl { +- compatible = "ti,twl5031"; +- +- twl_power: power { +- compatible = "ti,twl4030-power"; +- ti,use_poweroff; +- }; +-}; +- +-&twl_gpio { +- ti,pullups = <0x000001>; /* BIT(0) */ +- ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */ +-}; +- +-&vdac { +- regulator-name = "vdac"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +-}; +- +-&vpll1 { +- regulator-name = "vpll1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +-}; +- +-&vpll2 { +- regulator-name = "vpll2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +-}; +- +-&vaux1 { +- regulator-name = "vaux1"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +-}; +- +-/* CSI-2 receiver */ +-&vaux2 { +- regulator-name = "vaux2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +-}; +- +-/* Cameras */ +-&vaux3 { +- regulator-name = "vaux3"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +-}; +- +-&vaux4 { +- regulator-name = "vaux4"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +-}; +- +-&vmmc1 { +- regulator-name = "vmmc1"; +- regulator-min-microvolt = <1850000>; +- regulator-max-microvolt = <3150000>; +-}; +- +-&vmmc2 { +- regulator-name = "vmmc2"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +-}; +- +-&vintana1 { +- regulator-name = "vintana1"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +-}; +- +-&vintana2 { +- regulator-name = "vintana2"; +- regulator-min-microvolt = <2750000>; +- regulator-max-microvolt = <2750000>; +-}; +- +-&vintdig { +- regulator-name = "vintdig"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +-}; +- +-&vsim { +- regulator-name = "vsim"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +-}; +- +-&vio { +- regulator-name = "vio"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- +- as3645a@30 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x30>; +- compatible = "ams,as3645a"; +- as3645a_flash: flash@0 { +- reg = <0x0>; +- flash-timeout-us = <150000>; +- flash-max-microamp = <320000>; +- led-max-microamp = <60000>; +- ams,input-max-microamp = <1750000>; +- }; +- as3645a_indicator: indicator@1 { +- reg = <0x1>; +- led-max-microamp = <10000>; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +- +- lis302: lis302@1d { +- compatible = "st,lis3lv02d"; +- reg = <0x1d>; +- +- Vdd-supply = <&vaux1>; +- Vdd_IO-supply = <&vio>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&accelerator_pins>; +- +- interrupts-extended = <&gpio6 20 IRQ_TYPE_EDGE_FALLING>, <&gpio6 21 IRQ_TYPE_EDGE_FALLING>; /* 180, 181 */ +- +- /* click flags */ +- st,click-single-x; +- st,click-single-y; +- st,click-single-z; +- +- /* Limits are 0.5g * value */ +- st,click-threshold-x = <8>; +- st,click-threshold-y = <8>; +- st,click-threshold-z = <10>; +- +- /* Click must be longer than time limit */ +- st,click-time-limit = <9>; +- +- /* Kind of debounce filter */ +- st,click-latency = <50>; +- +- st,wakeup-x-hi; +- st,wakeup-y-hi; +- st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */ +- +- st,wakeup2-z-hi; +- st,wakeup2-threshold = <(1000/18)>; /* millig-value / 18 to get HW values */ +- +- st,highpass-cutoff-hz = <2>; +- +- /* Interrupt line 1 for thresholds */ +- st,irq1-ff-wu-1; +- st,irq1-ff-wu-2; +- /* Interrupt line 2 for click detection */ +- st,irq2-click; +- +- st,wu-duration-1 = <8>; +- st,wu-duration-2 = <8>; +- }; +-}; +- +-&mmc1 { +- status = "disabled"; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- vmmc-supply = <&vemmc>; +- bus-width = <4>; +- ti,non-removable; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-/* RNG not directly accessible on N950/N9. */ +-&rng_target { +- status = "disabled"; +-}; +- +-&usb_otg_hs { +- interface-type = <0>; +- usb-phy = <&usb2_phy>; +- phys = <&usb2_phy>; +- phy-names = "usb2-phy"; +- mode = <3>; +- power = <50>; +-}; +- +-&gpmc { +- ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ +- +- onenand@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ti,omap2-onenand"; +- reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ +- +- /* +- * These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported +- * bootloader set values when booted with v4.19 using both N950 +- * and N9 devices (OneNAND Manufacturer: Samsung): +- * +- * gpmc cs0 before gpmc_cs_program_settings: +- * cs0 GPMC_CS_CONFIG1: 0xfd001202 +- * cs0 GPMC_CS_CONFIG2: 0x00181800 +- * cs0 GPMC_CS_CONFIG3: 0x00030300 +- * cs0 GPMC_CS_CONFIG4: 0x18001804 +- * cs0 GPMC_CS_CONFIG5: 0x03171d1d +- * cs0 GPMC_CS_CONFIG6: 0x97080000 +- */ +- gpmc,sync-read; +- gpmc,sync-write; +- gpmc,burst-length = <16>; +- gpmc,burst-read; +- gpmc,burst-wrap; +- gpmc,burst-write; +- gpmc,device-width = <2>; +- gpmc,mux-add-data = <2>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <122>; +- gpmc,cs-wr-off-ns = <122>; +- gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <15>; +- gpmc,adv-wr-off-ns = <15>; +- gpmc,oe-on-ns = <20>; +- gpmc,oe-off-ns = <122>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <122>; +- gpmc,rd-cycle-ns = <148>; +- gpmc,wr-cycle-ns = <148>; +- gpmc,access-ns = <117>; +- gpmc,page-burst-access-ns = <15>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,wait-monitoring-ns = <0>; +- gpmc,clk-activation-ns = <10>; +- gpmc,wr-data-mux-bus-ns = <40>; +- gpmc,wr-access-ns = <117>; +- +- gpmc,sync-clk-ps = <15000>; /* TBC; Where this value came? */ +- +- /* +- * MTD partition table corresponding to Nokia's MeeGo 1.2 +- * Harmattan release. +- */ +- partition@0 { +- label = "bootloader"; +- reg = <0x00000000 0x00100000>; +- }; +- partition@1 { +- label = "config"; +- reg = <0x00100000 0x002c0000>; +- }; +- partition@2 { +- label = "kernel"; +- reg = <0x003c0000 0x01000000>; +- }; +- partition@3 { +- label = "log"; +- reg = <0x013c0000 0x00200000>; +- }; +- partition@4 { +- label = "var"; +- reg = <0x015c0000 0x1ca40000>; +- }; +- partition@5 { +- label = "moslo"; +- reg = <0x1e000000 0x02000000>; +- }; +- partition@6 { +- label = "omap2-onenand"; +- reg = <0x00000000 0x20000000>; +- }; +- }; +-}; +- +-&ssi_port1 { +- pinctrl-names = "default", "idle"; +- pinctrl-0 = <&ssi_pins>; +- pinctrl-1 = <&ssi_pins_idle>; +- +- ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ +- +- modem: hsi-client { +- pinctrl-names = "default"; +- pinctrl-0 = <&modem_pins1 &modem_pins2>; +- +- hsi-channel-ids = <0>, <1>, <2>, <3>; +- hsi-channel-names = "mcsaab-control", +- "speech-control", +- "speech-data", +- "mcsaab-data"; +- hsi-speed-kbps = <96000>; +- hsi-mode = "frame"; +- hsi-flow = "synchronized"; +- hsi-arb-mode = "round-robin"; +- +- interrupts-extended = <&gpio2 2 IRQ_TYPE_EDGE_RISING>; /* gpio 34 */ +- +- gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>, /* gpio 93 */ +- <&gpio3 24 GPIO_ACTIVE_HIGH>, /* gpio 88 */ +- <&gpio1 23 GPIO_ACTIVE_HIGH>; /* gpio 23 */ +- gpio-names = "cmt_apeslpx", +- "cmt_rst_rq", +- "cmt_en"; +- }; +-}; +- +-&ssi_port2 { +- status = "disabled"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- +- bluetooth { +- compatible = "ti,wl1271-bluetooth-nokia", "nokia,h4p-bluetooth"; +- +- reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; /* 26 */ +- host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* 101 */ +- bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* 37 */ +- +- clocks = <&vctcxo>; +- clock-names = "sysclk"; +- }; +-}; +- +-&aes1_target { +- status = "disabled"; +-}; +- +-&aes2_target { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-n950.dts b/scripts/dtc/include-prefixes/arm/omap3-n950.dts +deleted file mode 100644 +index b2f480022ff6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-n950.dts ++++ /dev/null +@@ -1,273 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * omap3-n950.dts - Device Tree file for Nokia N950 +- * +- * Written by: Aaro Koskinen +- */ +- +-/dts-v1/; +- +-#include "omap3-n950-n9.dtsi" +-#include +- +-/ { +- model = "Nokia N950"; +- compatible = "nokia,omap3-n950", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +- +- keys { +- compatible = "gpio-keys"; +- +- keypad_slide { +- label = "Keypad Slide"; +- gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* 109 */ +- linux,input-type = ; +- linux,code = ; +- wakeup-source; +- pinctrl-names = "default"; +- pinctrl-0 = <&keypad_slide_pins>; +- }; +- }; +-}; +- +-&omap3_pmx_core { +- keypad_slide_pins: pinmux_debug_led_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */ +- >; +- }; +-}; +- +-&omap3_pmx_core { +- spi4_pins: pinmux_spi4_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ +- OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */ +- OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */ +- OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */ +- >; +- }; +-}; +- +-&omap3_pmx_core { +- dsi_pins: pinmux_dsi_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE1) /* dsi_dx0 - data0+ */ +- OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE1) /* dsi_dy0 - data0- */ +- OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE1) /* dsi_dx1 - clk+ */ +- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE1) /* dsi_dy1 - clk- */ +- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE1) /* dsi_dx2 - data1+ */ +- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE1) /* dsi_dy2 - data1- */ +- >; +- }; +- +- display_pins: pinmux_display_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20ca, PIN_INPUT | MUX_MODE4) /* gpio 62 - display te */ +- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 - display reset */ +- >; +- }; +-}; +- +-&i2c2 { +- smia_1: camera@10 { +- compatible = "nokia,smia"; +- reg = <0x10>; +- /* No reset gpio */ +- vana-supply = <&vaux3>; +- clocks = <&isp 0>; +- clock-frequency = <9600000>; +- flash-leds = <&as3645a_flash &as3645a_indicator>; +- port { +- smia_1_1: endpoint { +- link-frequencies = /bits/ 64 <210000000 333600000 398400000>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- remote-endpoint = <&csi2a_ep>; +- }; +- }; +- }; +-}; +- +-&isp { +- vdd-csiphy1-supply = <&vaux2>; +- vdd-csiphy2-supply = <&vaux2>; +- ports { +- port@2 { +- reg = <2>; +- csi2a_ep: endpoint { +- remote-endpoint = <&smia_1_1>; +- clock-lanes = <2>; +- data-lanes = <3 1>; +- crc = <1>; +- lane-polarities = <1 1 1>; +- }; +- }; +- }; +-}; +- +-&mcspi4 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi4_pins>; +- +- wlcore: wlcore@0 { +- compatible = "ti,wl1271"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_pins>; +- reg = <0>; +- spi-max-frequency = <48000000>; +- clock-xtal; +- ref-clock-frequency = <38400000>; +- interrupts-extended = <&gpio2 10 IRQ_TYPE_LEVEL_HIGH>; /* gpio 42 */ +- vwlan-supply = <&vwlan_fixed>; +- }; +-}; +- +-&modem { +- compatible = "nokia,n950-modem"; +-}; +- +-&twl { +- twl_audio: audio { +- compatible = "ti,twl4030-audio"; +- ti,enable-vibra = <1>; +- }; +-}; +- +-&twl_keypad { +- linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_BACKSLASH) +- MATRIX_KEY(0x01, 0x00, KEY_LEFTSHIFT) +- MATRIX_KEY(0x02, 0x00, KEY_COMPOSE) +- MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA) +- MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) +- MATRIX_KEY(0x05, 0x00, KEY_BACKSPACE) +- MATRIX_KEY(0x06, 0x00, KEY_VOLUMEDOWN) +- MATRIX_KEY(0x07, 0x00, KEY_VOLUMEUP) +- +- MATRIX_KEY(0x03, 0x01, KEY_Z) +- MATRIX_KEY(0x04, 0x01, KEY_A) +- MATRIX_KEY(0x05, 0x01, KEY_Q) +- MATRIX_KEY(0x06, 0x01, KEY_W) +- MATRIX_KEY(0x07, 0x01, KEY_E) +- +- MATRIX_KEY(0x03, 0x02, KEY_X) +- MATRIX_KEY(0x04, 0x02, KEY_S) +- MATRIX_KEY(0x05, 0x02, KEY_D) +- MATRIX_KEY(0x06, 0x02, KEY_C) +- MATRIX_KEY(0x07, 0x02, KEY_V) +- +- MATRIX_KEY(0x03, 0x03, KEY_O) +- MATRIX_KEY(0x04, 0x03, KEY_I) +- MATRIX_KEY(0x05, 0x03, KEY_U) +- MATRIX_KEY(0x06, 0x03, KEY_L) +- MATRIX_KEY(0x07, 0x03, KEY_APOSTROPHE) +- +- MATRIX_KEY(0x03, 0x04, KEY_Y) +- MATRIX_KEY(0x04, 0x04, KEY_K) +- MATRIX_KEY(0x05, 0x04, KEY_J) +- MATRIX_KEY(0x06, 0x04, KEY_H) +- MATRIX_KEY(0x07, 0x04, KEY_G) +- +- MATRIX_KEY(0x03, 0x05, KEY_B) +- MATRIX_KEY(0x04, 0x05, KEY_COMMA) +- MATRIX_KEY(0x05, 0x05, KEY_M) +- MATRIX_KEY(0x06, 0x05, KEY_N) +- MATRIX_KEY(0x07, 0x05, KEY_DOT) +- +- MATRIX_KEY(0x00, 0x06, KEY_SPACE) +- MATRIX_KEY(0x03, 0x06, KEY_T) +- MATRIX_KEY(0x04, 0x06, KEY_UP) +- MATRIX_KEY(0x05, 0x06, KEY_LEFT) +- MATRIX_KEY(0x06, 0x06, KEY_RIGHT) +- MATRIX_KEY(0x07, 0x06, KEY_DOWN) +- +- MATRIX_KEY(0x03, 0x07, KEY_P) +- MATRIX_KEY(0x04, 0x07, KEY_ENTER) +- MATRIX_KEY(0x05, 0x07, KEY_SLASH) +- MATRIX_KEY(0x06, 0x07, KEY_F) +- MATRIX_KEY(0x07, 0x07, KEY_R) +- >; +-}; +- +-&lis302 { +- st,axis-x = <(-2)>; /* LIS3_INV_DEV_Y */ +- st,axis-y = <(-1)>; /* LIS3_INV_DEV_X */ +- st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ +- +- st,min-limit-x = <(-32)>; +- st,min-limit-y = <3>; +- st,min-limit-z = <3>; +- +- st,max-limit-x = <(-3)>; +- st,max-limit-y = <32>; +- st,max-limit-z = <32>; +-}; +- +-&dss { +- status = "okay"; +- +- vdda_video-supply = <&vdac>; +-}; +- +-&dsi { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dsi_pins>; +- +- vdd-supply = <&vpll2>; +- +- port { +- dsi_out_ep: endpoint { +- remote-endpoint = <&lcd0_in>; +- lanes = <2 3 0 1 4 5>; +- }; +- }; +- +- lcd0: panel@0 { +- compatible = "nokia,himalaya", "panel-dsi-cm"; +- reg = <0>; +- label = "lcd0"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&display_pins>; +- +- vpnl-supply = <&vmmc2>; +- vddi-supply = <&vio>; +- +- reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */ +- te-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; /* 62 */ +- +- width-mm = <49>; /* 48.960 mm */ +- height-mm = <88>; /* 88.128 mm */ +- +- /* TODO: +- * - panel is upside-down +- * - top + bottom 5px are not visible +- */ +- panel-timing { +- clock-frequency = <0>; /* Calculated by dsi */ +- +- hback-porch = <2>; +- hactive = <480>; +- hfront-porch = <0>; +- hsync-len = <2>; +- +- vback-porch = <1>; +- vactive = <864>; +- vfront-porch = <0>; +- vsync-len = <1>; +- +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- +- port { +- lcd0_in: endpoint { +- remote-endpoint = <&dsi_out_ep>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-alto35-common.dtsi b/scripts/dtc/include-prefixes/arm/omap3-overo-alto35-common.dtsi +deleted file mode 100644 +index bb932913c9e3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-alto35-common.dtsi ++++ /dev/null +@@ -1,75 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * Alto35 expansion board is manufactured by Gumstix Inc. +- */ +- +-#include "omap3-overo-common-peripherals.dtsi" +-#include "omap3-overo-common-lcd35.dtsi" +- +-#include +- +-/ { +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins>; +- gpio148 { +- label = "overo:red:gpio148"; +- gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>; /* gpio 148 */ +- }; +- gpio150 { +- label = "overo:yellow:gpio150"; +- gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* gpio 150 */ +- }; +- gpio151 { +- label = "overo:blue:gpio151"; +- gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* gpio 151 */ +- }; +- gpio170 { +- label = "overo:green:gpio170"; +- gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* gpio 170 */ +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&button_pins>; +- button0 { +- label = "button0"; +- linux,code = ; +- gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* gpio_10 */ +- wakeup-source; +- }; +- }; +-}; +- +-&omap3_pmx_core { +- led_pins: pinmux_led_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE4) /* uart1_tx.gpio_148 */ +- OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ +- OMAP3_CORE1_IOPAD(0x2182, PIN_OUTPUT | MUX_MODE4) /* uart1_rx.gpio_151 */ +- OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ +- >; +- }; +-}; +- +-&omap3_pmx_wkup { +- button_pins: pinmux_button_pins { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a18, PIN_INPUT | MUX_MODE4) /* sys_clkout1.gpio_10 */ +- >; +- }; +-}; +- +-&usbhshost { +- status = "disabled"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-alto35.dts b/scripts/dtc/include-prefixes/arm/omap3-overo-alto35.dts +deleted file mode 100644 +index 37c64dd5f672..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-alto35.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * Alto35 expansion board is manufactured by Gumstix Inc. +- */ +- +-/dts-v1/; +- +-#include "omap3-overo.dtsi" +-#include "omap3-overo-alto35-common.dtsi" +- +-/ { +- model = "OMAP35xx Gumstix Overo on Alto35"; +- compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-base.dtsi b/scripts/dtc/include-prefixes/arm/omap3-overo-base.dtsi +deleted file mode 100644 +index 006a6d97231c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-base.dtsi ++++ /dev/null +@@ -1,274 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * The Gumstix Overo must be combined with an expansion board. +- */ +- +-/ { +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0>; +- }; +- +- led-controller { +- compatible = "pwm-leds"; +- +- led-1 { +- label = "overo:blue:COM"; +- pwms = <&twl_pwmled 1 7812500>; +- max-brightness = <127>; +- linux,default-trigger = "mmc0"; +- }; +- }; +- +- sound { +- compatible = "ti,omap-twl4030"; +- ti,model = "overo"; +- +- ti,mcbsp = <&mcbsp2>; +- }; +- +- /* HS USB Port 2 Power */ +- hsusb2_power: hsusb2_power_reg { +- compatible = "regulator-fixed"; +- regulator-name = "hsusb2_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio6 8 GPIO_ACTIVE_HIGH>; /* gpio_168: vbus enable */ +- startup-delay-us = <70000>; +- enable-active-high; +- }; +- +- /* HS USB Host PHY on PORT 2 */ +- hsusb2_phy: hsusb2_phy { +- compatible = "usb-nop-xceiv"; +- reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; /* gpio_183 */ +- vcc-supply = <&hsusb2_power>; +- #phy-cells = <0>; +- }; +- +- /* Regulator to trigger the nPoweron signal of the Wifi module */ +- w3cbw003c_npoweron: regulator-w3cbw003c-npoweron { +- compatible = "regulator-fixed"; +- regulator-name = "regulator-w3cbw003c-npoweron"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54: nPoweron */ +- enable-active-high; +- }; +- +- /* Regulator to trigger the nReset signal of the Wifi module */ +- w3cbw003c_wifi_nreset: regulator-w3cbw003c-wifi-nreset { +- pinctrl-names = "default"; +- pinctrl-0 = <&w3cbw003c_pins &w3cbw003c_2_pins>; +- compatible = "regulator-fixed"; +- regulator-name = "regulator-w3cbw003c-wifi-nreset"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* gpio_16: WiFi nReset */ +- startup-delay-us = <10000>; +- }; +-}; +- +-&omap3_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &hsusb2_pins +- >; +- +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */ +- OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */ +- OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */ +- OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ +- OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ +- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ +- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ +- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ +- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ +- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ +- >; +- }; +- +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ +- OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ +- OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ +- OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ +- OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ +- OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ +- >; +- }; +- +- /* WiFi/BT combo */ +- w3cbw003c_pins: pinmux_w3cbw003c_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ +- OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ +- >; +- }; +- +- hsusb2_pins: pinmux_hsusb2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ +- OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ +- OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ +- OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ +- OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ +- OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ +- OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */ +- OMAP3_CORE1_IOPAD(0x21c0, PIN_OUTPUT | MUX_MODE4) /* i2c2_sda.gpio_183 */ +- >; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- clock-frequency = <2600000>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- interrupt-parent = <&intc>; +- +- twl_audio: audio { +- compatible = "ti,twl4030-audio"; +- codec { +- }; +- }; +- }; +-}; +- +-#include "twl4030.dtsi" +-#include "twl4030_omap3.dtsi" +- +-/* i2c2 pins are used for gpio */ +-&i2c2 { +- status = "disabled"; +-}; +- +-/* on board microSD slot */ +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <&vmmc1>; +- bus-width = <4>; +-}; +- +-/* optional on board WiFi */ +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- vmmc-supply = <&w3cbw003c_npoweron>; +- vqmmc-supply = <&w3cbw003c_wifi_nreset>; +- bus-width = <4>; +- cap-sdio-irq; +- non-removable; +-}; +- +-&twl_gpio { +- ti,use-leds; +-}; +- +-&usb_otg_hs { +- interface-type = <0>; +- usb-phy = <&usb2_phy>; +- phys = <&usb2_phy>; +- phy-names = "usb2-phy"; +- mode = <3>; +- power = <50>; +-}; +- +-&usbhshost { +- port2-mode = "ehci-phy"; +-}; +- +-&usbhsehci { +- phys = <0 &hsusb2_phy>; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +-}; +- +-&mcbsp2 { +- status = "okay"; +-}; +- +-&gpmc { +- ranges = <0 0 0x30000000 0x1000000>, /* CS0 */ +- <4 0 0x2b000000 0x1000000>, /* CS4 */ +- <5 0 0x2c000000 0x1000000>; /* CS5 */ +- +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- linux,mtd-name= "micron,mt29c4g96maz"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- nand-bus-width = <16>; +- gpmc,device-width = <2>; +- ti,nand-ecc-opt = "bch8"; +- +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "SPL"; +- reg = <0 0x80000>; /* 512KiB */ +- }; +- partition@80000 { +- label = "U-Boot"; +- reg = <0x80000 0x1C0000>; /* 1792KiB */ +- }; +- partition@1c0000 { +- label = "Environment"; +- reg = <0x240000 0x40000>; /* 256KiB */ +- }; +- partition@280000 { +- label = "Kernel"; +- reg = <0x280000 0x800000>; /* 8192KiB */ +- }; +- partition@780000 { +- label = "Filesystem"; +- reg = <0xA80000 0>; +- /* HACK: MTDPART_SIZ_FULL=0 so fill to end */ +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-chestnut43-common.dtsi b/scripts/dtc/include-prefixes/arm/omap3-overo-chestnut43-common.dtsi +deleted file mode 100644 +index 2d2c61d7aa86..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-chestnut43-common.dtsi ++++ /dev/null +@@ -1,65 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * Chestnut43 expansion board is manufactured by Gumstix Inc. +- */ +- +-#include "omap3-overo-common-peripherals.dtsi" +-#include "omap3-overo-common-lcd43.dtsi" +- +-#include +- +-/ { +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins>; +- heartbeat { +- label = "overo:red:gpio21"; +- gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ +- linux,default-trigger = "heartbeat"; +- }; +- gpio22 { +- label = "overo:blue:gpio22"; +- gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&button_pins>; +- #address-cells = <1>; +- #size-cells = <0>; +- button0 { +- label = "button0"; +- linux,code = ; +- gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ +- wakeup-source; +- }; +- button1 { +- label = "button1"; +- linux,code = ; +- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ +- wakeup-source; +- }; +- }; +-}; +- +-#include "omap-gpmc-smsc9221.dtsi" +- +-&gpmc { +- ethernet@gpmc { +- reg = <5 0 0xff>; +- interrupt-parent = <&gpio6>; +- interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ +- }; +-}; +- +-&lis33de { +- status = "disabled"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-chestnut43.dts b/scripts/dtc/include-prefixes/arm/omap3-overo-chestnut43.dts +deleted file mode 100644 +index d147d704b89f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-chestnut43.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * Chestnut43 expansion board is manufactured by Gumstix Inc. +- */ +- +-/dts-v1/; +- +-#include "omap3-overo.dtsi" +-#include "omap3-overo-chestnut43-common.dtsi" +- +-/ { +- model = "OMAP35xx Gumstix Overo on Chestnut43"; +- compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +-}; +- +-&omap3_pmx_core2 { +- led_pins: pinmux_led_pins { +- pinctrl-single,pins = < +- OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ +- OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ +- >; +- }; +- +- button_pins: pinmux_button_pins { +- pinctrl-single,pins = < +- OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ +- OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ +- >; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-common-dvi.dtsi b/scripts/dtc/include-prefixes/arm/omap3-overo-common-dvi.dtsi +deleted file mode 100644 +index 339a51fa4119..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-common-dvi.dtsi ++++ /dev/null +@@ -1,108 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * DVI output for some Gumstix Overo boards (Tobi and Summit) +- */ +- +-&omap3_pmx_core { +- dss_dpi_pins: pinmux_dss_dpi_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ +- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ +- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ +- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ +- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ +- OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ +- OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ +- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ +- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ +- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ +- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ +- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ +- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ +- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ +- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ +- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ +- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ +- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ +- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ +- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ +- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ +- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ +- OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ +- OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ +- OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ +- OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ +- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ +- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ +- >; +- }; +-}; +- +-/* Needed to power the DPI pins */ +-&vpll2 { +- regulator-always-on; +-}; +- +-&dss { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_dpi_pins>; +- +- port { +- dpi_out: endpoint { +- remote-endpoint = <&tfp410_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-/ { +- aliases { +- display0 = &dvi0; +- }; +- +- tfp410: encoder { +- compatible = "ti,tfp410"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tfp410_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- tfp410_out: endpoint { +- remote-endpoint = <&dvi_connector_in>; +- }; +- }; +- }; +- }; +- +- dvi0: connector { +- compatible = "dvi-connector"; +- label = "dvi"; +- +- digital; +- ddc-i2c-bus = <&i2c3>; +- +- port { +- dvi_connector_in: endpoint { +- remote-endpoint = <&tfp410_out>; +- }; +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-common-lcd35.dtsi b/scripts/dtc/include-prefixes/arm/omap3-overo-common-lcd35.dtsi +deleted file mode 100644 +index 1d6e88f99eb3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-common-lcd35.dtsi ++++ /dev/null +@@ -1,163 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * 4.3'' LCD panel output for some Gumstix Overo boards (Gallop43, Chestnut43) +- */ +- +-&omap3_pmx_core { +- dss_dpi_pins: pinmux_dss_dpi_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ +- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ +- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ +- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ +- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ +- OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ +- OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ +- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ +- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ +- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ +- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ +- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ +- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ +- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ +- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ +- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ +- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ +- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ +- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ +- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ +- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ +- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ +- OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ +- OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ +- OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ +- OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ +- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ +- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ +- >; +- }; +- +- lb035_pins: pinmux_lb035_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2174, PIN_OUTPUT | MUX_MODE4) /* uart2_cts.gpio_144 */ +- >; +- }; +- +- backlight_pins: pinmux_backlight_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE4) /* uart2_rts.gpio_145 */ +- >; +- }; +- +- mcspi1_pins: pinmux_mcspi1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ +- OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ +- OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ +- OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ +- OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT | MUX_MODE0) /* mcspi1_cs1.mcspi1_cs1 */ +- >; +- }; +- +- ads7846_pins: pinmux_ads7846_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT_PULLDOWN | MUX_MODE4) /* csi2_dx1.gpio_114 */ +- >; +- }; +-}; +- +-/* Needed to power the DPI pins */ +-&vpll2 { +- regulator-always-on; +-}; +- +-&dss { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_dpi_pins>; +- +- port { +- dpi_out: endpoint { +- remote-endpoint = <&lcd_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-/ { +- aliases { +- display0 = &lcd0; +- }; +- +- ads7846reg: ads7846-reg { +- compatible = "regulator-fixed"; +- regulator-name = "ads7846-reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- backlight { +- compatible = "gpio-backlight"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&backlight_pins>; +- gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; /* gpio_145 */ +- +- default-on; +- }; +-}; +- +-&mcspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcspi1_pins>; +- +- lcd0: display@1 { +- compatible = "lgphilips,lb035q02"; +- label = "lcd35"; +- +- reg = <1>; /* CS1 */ +- spi-max-frequency = <500000>; +- spi-cpol; +- spi-cpha; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&lb035_pins>; +- enable-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ +- +- port { +- lcd_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- }; +- +- /* touch controller */ +- ads7846@0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ads7846_pins>; +- +- compatible = "ti,ads7846"; +- vcc-supply = <&ads7846reg>; +- +- reg = <0>; /* CS0 */ +- spi-max-frequency = <1500000>; +- +- interrupt-parent = <&gpio4>; +- interrupts = <18 0>; /* gpio_114 */ +- pendown-gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>; +- +- ti,x-min = /bits/ 16 <0x0>; +- ti,x-max = /bits/ 16 <0x0fff>; +- ti,y-min = /bits/ 16 <0x0>; +- ti,y-max = /bits/ 16 <0x0fff>; +- ti,x-plate-ohms = /bits/ 16 <180>; +- ti,pressure-max = /bits/ 16 <255>; +- +- wakeup-source; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-common-lcd43.dtsi b/scripts/dtc/include-prefixes/arm/omap3-overo-common-lcd43.dtsi +deleted file mode 100644 +index 7e30f9d45790..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-common-lcd43.dtsi ++++ /dev/null +@@ -1,175 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * 4.3'' LCD panel output for some Gumstix Overo boards (Gallop43, Chestnut43) +- */ +- +-&omap3_pmx_core { +- dss_dpi_pins: pinmux_dss_dpi_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ +- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ +- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ +- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ +- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ +- OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ +- OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ +- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ +- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ +- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ +- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ +- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ +- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ +- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ +- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ +- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ +- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ +- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ +- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ +- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ +- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ +- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ +- OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ +- OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ +- OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ +- OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ +- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ +- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ +- >; +- }; +- +- lte430_pins: pinmux_lte430_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2174, PIN_OUTPUT | MUX_MODE4) /* uart2_cts.gpio_144 */ +- >; +- }; +- +- backlight_pins: pinmux_backlight_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE4) /* uart2_rts.gpio_145 */ +- >; +- }; +- +- mcspi1_pins: pinmux_mcspi1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ +- OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ +- OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ +- OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ +- >; +- }; +- +- ads7846_pins: pinmux_ads7846_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT_PULLDOWN | MUX_MODE4) /* csi2_dx1.gpio_114 */ +- >; +- }; +-}; +- +-/* Needed to power the DPI pins */ +-&vpll2 { +- regulator-always-on; +-}; +- +-&dss { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_dpi_pins>; +- +- port { +- dpi_out: endpoint { +- remote-endpoint = <&lcd_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-/ { +- aliases { +- display0 = &lcd0; +- }; +- +- lcd0: display { +- compatible = "samsung,lte430wq-f0c", "panel-dpi"; +- label = "lcd43"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <<e430_pins>; +- enable-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ +- +- port { +- lcd_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- +- panel-timing { +- clock-frequency = <9200000>; +- hactive = <480>; +- vactive = <272>; +- hfront-porch = <8>; +- hback-porch = <4>; +- hsync-len = <41>; +- vback-porch = <2>; +- vfront-porch = <4>; +- vsync-len = <10>; +- +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- +- ads7846reg: ads7846-reg { +- compatible = "regulator-fixed"; +- regulator-name = "ads7846-reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- backlight { +- compatible = "gpio-backlight"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&backlight_pins>; +- gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; /* gpio_145 */ +- +- default-on; +- }; +-}; +- +-&mcspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcspi1_pins>; +- +- /* touch controller */ +- ads7846@0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ads7846_pins>; +- +- compatible = "ti,ads7846"; +- vcc-supply = <&ads7846reg>; +- +- reg = <0>; /* CS0 */ +- spi-max-frequency = <1500000>; +- +- interrupt-parent = <&gpio4>; +- interrupts = <18 0>; /* gpio_114 */ +- pendown-gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>; +- +- ti,x-min = /bits/ 16 <0x0>; +- ti,x-max = /bits/ 16 <0x0fff>; +- ti,y-min = /bits/ 16 <0x0>; +- ti,y-max = /bits/ 16 <0x0fff>; +- ti,x-plate-ohms = /bits/ 16 <180>; +- ti,pressure-max = /bits/ 16 <255>; +- +- wakeup-source; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-common-peripherals.dtsi b/scripts/dtc/include-prefixes/arm/omap3-overo-common-peripherals.dtsi +deleted file mode 100644 +index 8a4a02472c9a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-common-peripherals.dtsi ++++ /dev/null +@@ -1,92 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * Peripherals common to all Gumstix Overo boards (Tobi, Summit, Palo43,...) +- */ +- +-/ { +- lis33_3v3: lis33-3v3-reg { +- compatible = "regulator-fixed"; +- regulator-name = "lis33-3v3-reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- lis33_1v8: lis33-1v8-reg { +- compatible = "regulator-fixed"; +- regulator-name = "lis33-1v8-reg"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +-}; +- +-&omap3_pmx_core { +- i2c3_pins: pinmux_i2c3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ +- OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ +- >; +- }; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ +- OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ +- >; +- }; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- clock-frequency = <100000>; +- +- /* optional 1K EEPROM with revision information */ +- eeprom@51 { +- compatible = "atmel,24c01"; +- reg = <0x51>; +- pagesize = <8>; +- }; +- +- lis33de: lis33de@1d { +- compatible = "st,lis33de", "st,lis3lv02d"; +- reg = <0x1d>; +- Vdd-supply = <&lis33_1v8>; +- Vdd_IO-supply = <&lis33_3v3>; +- +- st,click-single-x; +- st,click-single-y; +- st,click-single-z; +- st,click-thresh-x = <10>; +- st,click-thresh-y = <10>; +- st,click-thresh-z = <10>; +- st,irq1-click; +- st,irq2-click; +- st,wakeup-x-lo; +- st,wakeup-x-hi; +- st,wakeup-y-lo; +- st,wakeup-y-hi; +- st,wakeup-z-lo; +- st,wakeup-z-hi; +- st,min-limit-x = <120>; +- st,min-limit-y = <120>; +- st,min-limit-z = <140>; +- st,max-limit-x = <550>; +- st,max-limit-y = <550>; +- st,max-limit-z = <750>; +- }; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-&uart3 { +- interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-gallop43-common.dtsi b/scripts/dtc/include-prefixes/arm/omap3-overo-gallop43-common.dtsi +deleted file mode 100644 +index 155aec121400..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-gallop43-common.dtsi ++++ /dev/null +@@ -1,55 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * Gallop43 expansion board is manufactured by Gumstix Inc. +- */ +- +-#include "omap3-overo-common-peripherals.dtsi" +-#include "omap3-overo-common-lcd43.dtsi" +- +-#include +- +-/ { +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins>; +- heartbeat { +- label = "overo:red:gpio21"; +- gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ +- linux,default-trigger = "heartbeat"; +- }; +- gpio22 { +- label = "overo:blue:gpio22"; +- gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&button_pins>; +- #address-cells = <1>; +- #size-cells = <0>; +- button0 { +- label = "button0"; +- linux,code = ; +- gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ +- wakeup-source; +- }; +- button1 { +- label = "button1"; +- linux,code = ; +- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ +- wakeup-source; +- }; +- }; +-}; +- +-&usbhshost { +- status = "disabled"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-gallop43.dts b/scripts/dtc/include-prefixes/arm/omap3-overo-gallop43.dts +deleted file mode 100644 +index 24b40bdf7ea1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-gallop43.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * Gallop43 expansion board is manufactured by Gumstix Inc. +- */ +- +-/dts-v1/; +- +-#include "omap3-overo.dtsi" +-#include "omap3-overo-gallop43-common.dtsi" +- +-/ { +- model = "OMAP35xx Gumstix Overo on Gallop43"; +- compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +-}; +- +-&omap3_pmx_core2 { +- led_pins: pinmux_led_pins { +- pinctrl-single,pins = < +- OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ +- OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ +- >; +- }; +- +- button_pins: pinmux_button_pins { +- pinctrl-single,pins = < +- OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ +- OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ +- >; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-palo35-common.dtsi b/scripts/dtc/include-prefixes/arm/omap3-overo-palo35-common.dtsi +deleted file mode 100644 +index 82a04466747a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-palo35-common.dtsi ++++ /dev/null +@@ -1,50 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 Ash Charles, Gumstix Inc. +- */ +- +-/* +- * Palo35 expansion board is manufactured by Gumstix Inc. +- */ +- +-#include "omap3-overo-common-peripherals.dtsi" +-#include "omap3-overo-common-lcd35.dtsi" +- +-#include +- +-/ { +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins>; +- heartbeat { +- label = "overo:red:gpio21"; +- gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ +- linux,default-trigger = "heartbeat"; +- }; +- gpio22 { +- label = "overo:blue:gpio22"; +- gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&button_pins>; +- #address-cells = <1>; +- #size-cells = <0>; +- button0 { +- label = "button0"; +- linux,code = ; +- gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ +- wakeup-source; +- }; +- button1 { +- label = "button1"; +- linux,code = ; +- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ +- wakeup-source; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-palo35.dts b/scripts/dtc/include-prefixes/arm/omap3-overo-palo35.dts +deleted file mode 100644 +index 55e08d56b18b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-palo35.dts ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 Ash Charles, Gumstix Inc. +- */ +- +-/* +- * Palo35 expansion board is manufactured by Gumstix Inc. +- */ +- +-/dts-v1/; +- +-#include "omap3-overo.dtsi" +-#include "omap3-overo-palo35-common.dtsi" +- +-/ { +- model = "OMAP35xx Gumstix Overo on Palo35"; +- compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +-}; +- +-&omap3_pmx_core2 { +- led_pins: pinmux_led_pins { +- pinctrl-single,pins = < +- OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ +- OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ +- >; +- }; +- +- button_pins: pinmux_button_pins { +- pinctrl-single,pins = < +- OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ +- OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-palo43-common.dtsi b/scripts/dtc/include-prefixes/arm/omap3-overo-palo43-common.dtsi +deleted file mode 100644 +index 453a55324fa1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-palo43-common.dtsi ++++ /dev/null +@@ -1,51 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * Palo43 expansion board is manufactured by Gumstix Inc. +- */ +- +-#include "omap3-overo-common-peripherals.dtsi" +-#include "omap3-overo-common-lcd43.dtsi" +- +-#include +- +-/ { +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins>; +- heartbeat { +- label = "overo:red:gpio21"; +- gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ +- linux,default-trigger = "heartbeat"; +- }; +- gpio22 { +- label = "overo:blue:gpio22"; +- gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&button_pins>; +- #address-cells = <1>; +- #size-cells = <0>; +- button0 { +- label = "button0"; +- linux,code = ; +- gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ +- wakeup-source; +- }; +- button1 { +- label = "button1"; +- linux,code = ; +- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ +- wakeup-source; +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-palo43.dts b/scripts/dtc/include-prefixes/arm/omap3-overo-palo43.dts +deleted file mode 100644 +index 092c8325a133..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-palo43.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * Palo43 expansion board is manufactured by Gumstix Inc. +- */ +- +-/dts-v1/; +- +-#include "omap3-overo.dtsi" +-#include "omap3-overo-palo43-common.dtsi" +- +-/ { +- model = "OMAP35xx Gumstix Overo on Palo43"; +- compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +-}; +- +-&omap3_pmx_core2 { +- led_pins: pinmux_led_pins { +- pinctrl-single,pins = < +- OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ +- OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ +- >; +- }; +- +- button_pins: pinmux_button_pins { +- pinctrl-single,pins = < +- OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ +- OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ +- >; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-storm-alto35.dts b/scripts/dtc/include-prefixes/arm/omap3-overo-storm-alto35.dts +deleted file mode 100644 +index 7f04dfad8203..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-storm-alto35.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * Alto35 expansion board is manufactured by Gumstix Inc. +- */ +- +-/dts-v1/; +- +-#include "omap3-overo-storm.dtsi" +-#include "omap3-overo-alto35-common.dtsi" +- +-/ { +- model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Alto35"; +- compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-storm-chestnut43.dts b/scripts/dtc/include-prefixes/arm/omap3-overo-storm-chestnut43.dts +deleted file mode 100644 +index bc5a04e03336..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-storm-chestnut43.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * Chestnut43 expansion board is manufactured by Gumstix Inc. +- */ +- +-/dts-v1/; +- +-#include "omap3-overo-storm.dtsi" +-#include "omap3-overo-chestnut43-common.dtsi" +- +-/ { +- model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Chestnut43"; +- compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +-}; +- +-&omap3_pmx_core2 { +- led_pins: pinmux_led_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ +- OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ +- >; +- }; +- +- button_pins: pinmux_button_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ +- OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ +- >; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-storm-gallop43.dts b/scripts/dtc/include-prefixes/arm/omap3-overo-storm-gallop43.dts +deleted file mode 100644 +index 065c31cbf0e2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-storm-gallop43.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * Gallop43 expansion board is manufactured by Gumstix Inc. +- */ +- +-/dts-v1/; +- +-#include "omap3-overo-storm.dtsi" +-#include "omap3-overo-gallop43-common.dtsi" +- +-/ { +- model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Gallop43"; +- compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +-}; +- +-&omap3_pmx_core2 { +- led_pins: pinmux_led_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ +- OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ +- >; +- }; +- +- button_pins: pinmux_button_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ +- OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ +- >; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-storm-palo35.dts b/scripts/dtc/include-prefixes/arm/omap3-overo-storm-palo35.dts +deleted file mode 100644 +index e38c1c51392c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-storm-palo35.dts ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 Ash Charles, Gumstix, Inc. +- */ +- +-/* +- * Palo35 expansion board is manufactured by Gumstix Inc. +- */ +- +-/dts-v1/; +- +-#include "omap3-overo-storm.dtsi" +-#include "omap3-overo-palo35-common.dtsi" +- +-/ { +- model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo35"; +- compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +-}; +- +-&omap3_pmx_core2 { +- led_pins: pinmux_led_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ +- OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ +- >; +- }; +- +- button_pins: pinmux_button_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ +- OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-storm-palo43.dts b/scripts/dtc/include-prefixes/arm/omap3-overo-storm-palo43.dts +deleted file mode 100644 +index e6dc23159c4d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-storm-palo43.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * Palo43 expansion board is manufactured by Gumstix Inc. +- */ +- +-/dts-v1/; +- +-#include "omap3-overo-storm.dtsi" +-#include "omap3-overo-palo43-common.dtsi" +- +-/ { +- model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo43"; +- compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +-}; +- +-&omap3_pmx_core2 { +- led_pins: pinmux_led_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ +- OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ +- >; +- }; +- +- button_pins: pinmux_button_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ +- OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ +- >; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-storm-summit.dts b/scripts/dtc/include-prefixes/arm/omap3-overo-storm-summit.dts +deleted file mode 100644 +index 587c08ce282d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-storm-summit.dts ++++ /dev/null +@@ -1,27 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * Summit expansion board is manufactured by Gumstix Inc. +- */ +- +-/dts-v1/; +- +-#include "omap3-overo-storm.dtsi" +-#include "omap3-overo-summit-common.dtsi" +- +-/ { +- model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Summit"; +- compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +-}; +- +-&omap3_pmx_core2 { +- led_pins: pinmux_led_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ +- >; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-storm-tobi.dts b/scripts/dtc/include-prefixes/arm/omap3-overo-storm-tobi.dts +deleted file mode 100644 +index f57de6010994..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-storm-tobi.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * Tobi expansion board is manufactured by Gumstix Inc. +- */ +- +-/dts-v1/; +- +-#include "omap3-overo-storm.dtsi" +-#include "omap3-overo-tobi-common.dtsi" +- +-/ { +- model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Tobi"; +- compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-storm-tobiduo.dts b/scripts/dtc/include-prefixes/arm/omap3-overo-storm-tobiduo.dts +deleted file mode 100644 +index 281af6c113be..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-storm-tobiduo.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 Ash Charles, Gumstix, Inc. +- */ +- +-/* +- * TobiDuo expansion board is manufactured by Gumstix Inc. +- */ +- +-/dts-v1/; +- +-#include "omap3-overo-storm.dtsi" +-#include "omap3-overo-tobiduo-common.dtsi" +- +-/ { +- model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on TobiDuo"; +- compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-storm.dtsi b/scripts/dtc/include-prefixes/arm/omap3-overo-storm.dtsi +deleted file mode 100644 +index 2af15d5f61f9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-storm.dtsi ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-#include "omap36xx.dtsi" +-#include "omap3-overo-base.dtsi" +- +-&omap3_pmx_core2 { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &hsusb2_2_pins +- >; +- +- hsusb2_2_pins: pinmux_hsusb2_2_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ +- OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ +- OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ +- OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ +- OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ +- OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ +- >; +- }; +- +- w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ +- >; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-summit-common.dtsi b/scripts/dtc/include-prefixes/arm/omap3-overo-summit-common.dtsi +deleted file mode 100644 +index df7450f17ffd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-summit-common.dtsi ++++ /dev/null +@@ -1,29 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * Summit expansion board is manufactured by Gumstix Inc. +- */ +- +-#include "omap3-overo-common-peripherals.dtsi" +-#include "omap3-overo-common-dvi.dtsi" +- +-/ { +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins>; +- heartbeat { +- label = "overo:red:gpio21"; +- gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-&lis33de { +- status = "disabled"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-summit.dts b/scripts/dtc/include-prefixes/arm/omap3-overo-summit.dts +deleted file mode 100644 +index a6c9799fe491..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-summit.dts ++++ /dev/null +@@ -1,27 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * Summit expansion board is manufactured by Gumstix Inc. +- */ +- +-/dts-v1/; +- +-#include "omap3-overo.dtsi" +-#include "omap3-overo-summit-common.dtsi" +- +-/ { +- model = "OMAP35xx Gumstix Overo on Summit"; +- compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +-}; +- +-&omap3_pmx_core2 { +- led_pins: pinmux_led_pins { +- pinctrl-single,pins = < +- OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ +- >; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-tobi-common.dtsi b/scripts/dtc/include-prefixes/arm/omap3-overo-tobi-common.dtsi +deleted file mode 100644 +index 9bf4b88a4b50..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-tobi-common.dtsi ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * Tobi expansion board is manufactured by Gumstix Inc. +- */ +- +-#include "omap3-overo-common-peripherals.dtsi" +-#include "omap3-overo-common-dvi.dtsi" +- +-/ { +- leds { +- compatible = "gpio-leds"; +- heartbeat { +- label = "overo:red:gpio21"; +- gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-#include "omap-gpmc-smsc9221.dtsi" +- +-&gpmc { +- ethernet@gpmc { +- reg = <5 0 0xff>; +- interrupt-parent = <&gpio6>; +- interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ +- }; +-}; +- +-&lis33de { +- status = "disabled"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-tobi.dts b/scripts/dtc/include-prefixes/arm/omap3-overo-tobi.dts +deleted file mode 100644 +index ce3f2404f329..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-tobi.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group +- */ +- +-/* +- * Tobi expansion board is manufactured by Gumstix Inc. +- */ +- +-/dts-v1/; +- +-#include "omap3-overo.dtsi" +-#include "omap3-overo-tobi-common.dtsi" +- +-/ { +- model = "OMAP35xx Gumstix Overo on Tobi"; +- compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-tobiduo-common.dtsi b/scripts/dtc/include-prefixes/arm/omap3-overo-tobiduo-common.dtsi +deleted file mode 100644 +index 218a10c0d815..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-tobiduo-common.dtsi ++++ /dev/null +@@ -1,59 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 Ash Charles, Gumstix, Inc. +- */ +- +-/* +- * TobiDuo expansion board is manufactured by Gumstix Inc. +- */ +- +-#include "omap3-overo-common-peripherals.dtsi" +- +-#include "omap-gpmc-smsc9221.dtsi" +- +-&gpmc { +- smsc1: ethernet@gpmc { +- reg = <5 0 0xff>; +- interrupt-parent = <&gpio6>; +- interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ +- }; +- +- smsc2: ethernet@4,0 { +- compatible = "smsc,lan9221","smsc,lan9115"; +- bank-width = <2>; +- +- gpmc,mux-add-data = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <42>; +- gpmc,cs-wr-off-ns = <36>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <12>; +- gpmc,adv-wr-off-ns = <12>; +- gpmc,oe-on-ns = <0>; +- gpmc,oe-off-ns = <42>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <36>; +- gpmc,rd-cycle-ns = <60>; +- gpmc,wr-cycle-ns = <54>; +- gpmc,access-ns = <36>; +- gpmc,page-burst-access-ns = <0>; +- gpmc,bus-turnaround-ns = <0>; +- gpmc,cycle2cycle-delay-ns = <0>; +- gpmc,wr-data-mux-bus-ns = <18>; +- gpmc,wr-access-ns = <42>; +- gpmc,cycle2cycle-samecsen; +- gpmc,cycle2cycle-diffcsen; +- vddvario-supply = <&vddvario>; +- vdd33a-supply = <&vdd33a>; +- reg-io-width = <4>; +- smsc,save-mac-address; +- +- reg = <4 0 0xff>; +- interrupt-parent = <&gpio3>; +- interrupts = <1 IRQ_TYPE_LEVEL_LOW>; /* GPIO 65 */ +- }; +-}; +- +-&lis33de { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo-tobiduo.dts b/scripts/dtc/include-prefixes/arm/omap3-overo-tobiduo.dts +deleted file mode 100644 +index fc6163eae45e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo-tobiduo.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 Ash Charles, Gumstix, Inc. +- */ +- +-/* +- * TobiDuo expansion board is manufactured by Gumstix Inc. +- */ +- +-/dts-v1/; +- +-#include "omap3-overo.dtsi" +-#include "omap3-overo-tobiduo-common.dtsi" +- +-/ { +- model = "OMAP35xx Gumstix Overo on TobiDuo"; +- compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-overo.dtsi b/scripts/dtc/include-prefixes/arm/omap3-overo.dtsi +deleted file mode 100644 +index cc9263e99254..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-overo.dtsi ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-#include "omap34xx.dtsi" +-#include "omap3-overo-base.dtsi" +- +-&omap3_pmx_core2 { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &hsusb2_2_pins +- >; +- +- hsusb2_2_pins: pinmux_hsusb2_2_pins { +- pinctrl-single,pins = < +- OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ +- OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ +- OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ +- OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ +- OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ +- OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ +- >; +- }; +- +- w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins { +- pinctrl-single,pins = < +- OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-pandora-1ghz.dts b/scripts/dtc/include-prefixes/arm/omap3-pandora-1ghz.dts +deleted file mode 100644 +index ea509956d7ac..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-pandora-1ghz.dts ++++ /dev/null +@@ -1,67 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 +- * Nikolaus Schaller +- */ +- +-/* +- * device tree for OpenPandora 1GHz with DM3730 +- */ +- +-/dts-v1/; +- +-#include "omap36xx.dtsi" +-#include "omap3-pandora-common.dtsi" +- +-/ { +- model = "Pandora Handheld Console 1GHz"; +- +- compatible = "openpandora,omap3-pandora-1ghz", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +-}; +- +-&omap3_pmx_core2 { +- +- pinctrl-names = "default"; +- pinctrl-0 = < +- &hsusb2_2_pins +- &control_pins +- >; +- +- hsusb2_2_pins: pinmux_hsusb2_2_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ +- OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ +- OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ +- OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ +- OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ +- OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ +- >; +- }; +- +- mmc3_pins: pinmux_mmc3_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ +- OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ +- OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ +- OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ +- OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ +- OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ +- >; +- }; +- +- control_pins: pinmux_control_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* etk_d0.gpio_14 = HP_SHUTDOWN */ +- OMAP3630_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4) /* etk_d1.gpio_15 = BT_SHUTDOWN */ +- OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 = RESET_USB_HOST */ +- OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4) /* etk_d7.gpio_21 = WIFI IRQ */ +- OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 = MSECURE */ +- OMAP3630_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4) /* etk_d9.gpio_23 = WIFI_POWER */ +- OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT | MUX_MODE4) /* reserved.gpio_127 = MMC2_WP */ +- OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 = MMC1_WP */ +- OMAP3_WKUP_IOPAD(0x2a58, PIN_OUTPUT | MUX_MODE4) /* reserved.gpio_128 = LED_MMC1 */ +- OMAP3_WKUP_IOPAD(0x2a5a, PIN_OUTPUT | MUX_MODE4) /* reserved.gpio_129 = LED_MMC2 */ +- +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-pandora-600mhz.dts b/scripts/dtc/include-prefixes/arm/omap3-pandora-600mhz.dts +deleted file mode 100644 +index 6bd9041942f2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-pandora-600mhz.dts ++++ /dev/null +@@ -1,62 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 +- * Nikolaus Schaller +- */ +- +-/* +- * device tree for OpenPandora with OMAP3530 +- */ +- +-/dts-v1/; +- +-#include "omap34xx.dtsi" +-#include "omap3-pandora-common.dtsi" +- +-/ { +- model = "Pandora Handheld Console"; +- +- compatible = "openpandora,omap3-pandora-600mhz", "ti,omap3430", "ti,omap3"; +-}; +- +-&omap3_pmx_core2 { +- +- pinctrl-names = "default"; +- pinctrl-0 = < +- &hsusb2_2_pins +- &control_pins +- >; +- +- hsusb2_2_pins: pinmux_hsusb2_2_pins { +- pinctrl-single,pins = < +- OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ +- OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ +- OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ +- OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ +- OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ +- OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ +- >; +- }; +- +- mmc3_pins: pinmux_mmc3_pins { +- pinctrl-single,pins = < +- OMAP3430_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ +- OMAP3430_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ +- OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ +- OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ +- OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ +- OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ +- >; +- }; +- +- control_pins: pinmux_control_pins { +- pinctrl-single,pins = < +- OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* etk_d0.gpio_14 = HP_SHUTDOWN */ +- OMAP3430_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4) /* etk_d1.gpio_15 = BT_SHUTDOWN */ +- OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 = RESET_USB_HOST */ +- OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4) /* etk_d7.gpio_21 = WIFI IRQ */ +- OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 = MSECURE */ +- OMAP3430_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4) /* etk_d9.gpio_23 = WIFI_POWER */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-pandora-common.dtsi b/scripts/dtc/include-prefixes/arm/omap3-pandora-common.dtsi +deleted file mode 100644 +index 37608af6c07f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-pandora-common.dtsi ++++ /dev/null +@@ -1,730 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 +- * Nikolaus Schaller +- * +- * Common device tree include for OpenPandora devices. +- */ +- +-#include +- +-/ { +- cpus { +- cpu@0 { +- cpu0-supply = <&vcc>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512 MB */ +- }; +- +- aliases { +- display0 = &lcd; +- }; +- +- /* fixed 26MHz oscillator */ +- hfclk_26m: oscillator { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- }; +- +- tv: connector { +- compatible = "connector-analog-tv"; +- label = "tv"; +- +- port { +- tv_connector_in: endpoint { +- remote-endpoint = <&venc_out>; +- }; +- }; +- }; +- +- gpio-leds { +- +- compatible = "gpio-leds"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins>; +- +- led1 { +- label = "pandora::sd1"; +- gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* GPIO_128 */ +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- +- led2 { +- label = "pandora::sd2"; +- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* GPIO_129 */ +- linux,default-trigger = "mmc1"; +- default-state = "off"; +- }; +- +- led3 { +- label = "pandora::bluetooth"; +- gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; /* GPIO_158 */ +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- +- led4 { +- label = "pandora::wifi"; +- gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; /* GPIO_159 */ +- linux,default-trigger = "mmc2"; +- default-state = "off"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&button_pins>; +- +- up-button { +- label = "up"; +- linux,code = ; +- gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* GPIO_110 */ +- wakeup-source; +- }; +- +- down-button { +- label = "down"; +- linux,code = ; +- gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; /* GPIO_103 */ +- wakeup-source; +- }; +- +- left-button { +- label = "left"; +- linux,code = ; +- gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; /* GPIO_96 */ +- wakeup-source; +- }; +- +- right-button { +- label = "right"; +- linux,code = ; +- gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; /* GPIO_98 */ +- wakeup-source; +- }; +- +- pageup-button { +- label = "game 1"; +- linux,code = ; +- gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* GPIO_109 */ +- wakeup-source; +- }; +- +- pagedown-button { +- label = "game 3"; +- linux,code = ; +- gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* GPIO_106 */ +- wakeup-source; +- }; +- +- home-button { +- label = "game 4"; +- linux,code = ; +- gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; /* GPIO_101 */ +- wakeup-source; +- }; +- +- end-button { +- label = "game 2"; +- linux,code = ; +- gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* GPIO_111 */ +- wakeup-source; +- }; +- +- right-shift { +- label = "l"; +- linux,code = ; +- gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; /* GPIO_102 */ +- wakeup-source; +- }; +- +- kp-plus { +- label = "l2"; +- linux,code = ; +- gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; /* GPIO_97 */ +- wakeup-source; +- }; +- +- right-ctrl { +- label = "r"; +- linux,code = ; +- gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; /* GPIO_105 */ +- wakeup-source; +- }; +- +- kp-minus { +- label = "r2"; +- linux,code = ; +- gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* GPIO_107 */ +- wakeup-source; +- }; +- +- left-ctrl { +- label = "ctrl"; +- linux,code = ; +- gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; /* GPIO_104 */ +- wakeup-source; +- }; +- +- menu { +- label = "menu"; +- linux,code = ; +- gpios = <&gpio4 3 GPIO_ACTIVE_LOW>; /* GPIO_99 */ +- wakeup-source; +- }; +- +- hold { +- label = "hold"; +- linux,code = ; +- gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* GPIO_176 */ +- wakeup-source; +- }; +- +- left-alt { +- label = "alt"; +- linux,code = ; +- gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; /* GPIO_100 */ +- wakeup-source; +- }; +- +- lid { +- label = "lid"; +- linux,code = <0x00>; /* SW_LID lid shut */ +- linux,input-type = <0x05>; /* EV_SW */ +- gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; /* GPIO_108 */ +- }; +- }; +- +- /* HS USB Host PHY on PORT 2 */ +- hsusb2_phy: hsusb2_phy { +- compatible = "usb-nop-xceiv"; +- reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* GPIO_16 */ +- vcc-supply = <&vaux2>; +- #phy-cells = <0>; +- }; +- +- /* HS USB Host VBUS supply +- * disabling this regulator causes current leakage, and LCD flicker +- * on earlier (CC) board revisions, so keep it always on */ +- usb_host_5v: fixed-regulator-usb_host_5v { +- compatible = "regulator-fixed"; +- regulator-name = "usb_host_5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* GPIO_164 */ +- }; +- +- /* wl1251 wifi+bt module */ +- wlan_en: fixed-regulator-wg7210_en { +- compatible = "regulator-fixed"; +- regulator-name = "vwlan"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- startup-delay-us = <50000>; +- enable-active-high; +- gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; +- }; +- +- /* wg7210 (wifi+bt module) 32k clock buffer */ +- wg7210_32k: fixed-regulator-wg7210_32k { +- compatible = "regulator-fixed"; +- regulator-name = "wg7210_32k"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- enable-active-high; +- gpio = <&twl_gpio 13 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&omap3_pmx_core { +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ +- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ +- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ +- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ +- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ +- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ +- >; +- }; +- +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ +- OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ +- OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ +- OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ +- OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ +- OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ +- OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dirdat0 */ +- OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dirdat1 */ +- OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dircmd */ +- OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ +- >; +- }; +- +- dss_dpi_pins: pinmux_dss_dpi_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ +- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ +- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ +- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ +- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ +- OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ +- OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ +- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ +- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ +- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ +- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ +- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ +- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ +- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ +- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ +- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ +- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ +- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ +- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ +- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ +- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ +- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ +- OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ +- OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ +- OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ +- OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ +- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ +- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ +- OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* GPIO_157 = lcd reset */ +- >; +- }; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ +- OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ +- >; +- }; +- +- led_pins: pinmux_leds_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2154, PIN_OUTPUT | MUX_MODE4) /* GPIO_128 */ +- OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* GPIO_129 */ +- OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE4) /* GPIO_158 */ +- OMAP3_CORE1_IOPAD(0x2192, PIN_OUTPUT | MUX_MODE4) /* GPIO_159 */ +- >; +- }; +- +- button_pins: pinmux_button_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE4) /* GPIO_96 */ +- OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE4) /* GPIO_97 */ +- OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* GPIO_98 */ +- OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE4) /* GPIO_99 */ +- OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE4) /* GPIO_100 */ +- OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* GPIO_101 */ +- OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE4) /* GPIO_102 */ +- OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE4) /* GPIO_103 */ +- OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE4) /* GPIO_104 */ +- OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE4) /* GPIO_105 */ +- OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE4) /* GPIO_106 */ +- OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE4) /* GPIO_107 */ +- OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE4) /* GPIO_108 */ +- OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* GPIO_109 */ +- OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT | MUX_MODE4) /* GPIO_110 */ +- OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* GPIO_111 */ +- OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* GPIO_176 */ +- >; +- }; +- +- penirq_pins: pinmux_penirq_pins { +- pinctrl-single,pins = < +- /* here we could enable to wakeup the cpu from suspend by a pen touch */ +- OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE4) /* GPIO_94 */ +- >; +- }; +- +-}; +- +-&omap3_pmx_core2 { +- /* define in CPU specific file that includes this one +- * use either OMAP3430_CORE2_IOPAD() or OMAP3630_CORE2_IOPAD() +- */ +-}; +- +-&i2c1 { +- clock-frequency = <2600000>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- interrupt-parent = <&intc>; +- +- clocks = <&hfclk_26m>; +- clock-names = "fck"; +- +- twl_power: power { +- compatible = "ti,twl4030-power-reset"; +- ti,use_poweroff; +- }; +- +- twl_audio: audio { +- compatible = "ti,twl4030-audio"; +- +- codec { +- ti,ramp_delay_value = <3>; +- }; +- }; +- }; +-}; +- +-#include "twl4030.dtsi" +-#include "twl4030_omap3.dtsi" +- +-&twl_keypad { +- keypad,num-rows = <8>; +- keypad,num-columns = <6>; +- linux,keymap = < +- MATRIX_KEY(0, 0, KEY_9) +- MATRIX_KEY(0, 1, KEY_8) +- MATRIX_KEY(0, 2, KEY_I) +- MATRIX_KEY(0, 3, KEY_J) +- MATRIX_KEY(0, 4, KEY_N) +- MATRIX_KEY(0, 5, KEY_M) +- MATRIX_KEY(1, 0, KEY_0) +- MATRIX_KEY(1, 1, KEY_7) +- MATRIX_KEY(1, 2, KEY_U) +- MATRIX_KEY(1, 3, KEY_H) +- MATRIX_KEY(1, 4, KEY_B) +- MATRIX_KEY(1, 5, KEY_SPACE) +- MATRIX_KEY(2, 0, KEY_BACKSPACE) +- MATRIX_KEY(2, 1, KEY_6) +- MATRIX_KEY(2, 2, KEY_Y) +- MATRIX_KEY(2, 3, KEY_G) +- MATRIX_KEY(2, 4, KEY_V) +- MATRIX_KEY(2, 5, KEY_FN) +- MATRIX_KEY(3, 0, KEY_O) +- MATRIX_KEY(3, 1, KEY_5) +- MATRIX_KEY(3, 2, KEY_T) +- MATRIX_KEY(3, 3, KEY_F) +- MATRIX_KEY(3, 4, KEY_C) +- MATRIX_KEY(4, 0, KEY_P) +- MATRIX_KEY(4, 1, KEY_4) +- MATRIX_KEY(4, 2, KEY_R) +- MATRIX_KEY(4, 3, KEY_D) +- MATRIX_KEY(4, 4, KEY_X) +- MATRIX_KEY(5, 0, KEY_K) +- MATRIX_KEY(5, 1, KEY_3) +- MATRIX_KEY(5, 2, KEY_E) +- MATRIX_KEY(5, 3, KEY_S) +- MATRIX_KEY(5, 4, KEY_Z) +- MATRIX_KEY(6, 0, KEY_L) +- MATRIX_KEY(6, 1, KEY_2) +- MATRIX_KEY(6, 2, KEY_W) +- MATRIX_KEY(6, 3, KEY_A) +- MATRIX_KEY(6, 4, KEY_RIGHTBRACE) +- MATRIX_KEY(7, 0, KEY_ENTER) +- MATRIX_KEY(7, 1, KEY_1) +- MATRIX_KEY(7, 2, KEY_Q) +- MATRIX_KEY(7, 3, KEY_LEFTSHIFT) +- MATRIX_KEY(7, 4, KEY_LEFTBRACE ) +- >; +-}; +- +-/* backup battery charger */ +-&charger { +- ti,bb-uvolt = <3200000>; +- ti,bb-uamp = <150>; +-}; +- +-/* MMC2 */ +-&vmmc2 { +- regulator-min-microvolt = <1850000>; +- regulator-max-microvolt = <3150000>; +-}; +- +-/* LCD */ +-&vaux1 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +-}; +- +-/* USB Host PHY */ +-&vaux2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +-}; +- +-/* available on expansion connector */ +-&vaux3 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +-}; +- +-/* ADS7846 and nubs */ +-&vaux4 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +-}; +- +-/* power audio DAC and LID sensor */ +-&vsim { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- /* no clients so we should disable clock */ +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- +- bq27500@55 { +- compatible = "ti,bq27500"; +- reg = <0x55>; +- }; +- +-}; +- +-&usb_otg_hs { +- interface-type = <0>; +- usb-phy = <&usb2_phy>; +- phys = <&usb2_phy>; +- phy-names = "usb2-phy"; +- mode = <3>; +- power = <50>; +-}; +- +-/* +- * Many pandora boards have been produced with defective write-protect switches +- * on either slot, so it was decided not to use this feature. If you know +- * your board has good switches, feel free to uncomment wp-gpios below. +- */ +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <&vmmc1>; +- bus-width = <4>; +- cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; +- /*wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;*/ /* GPIO_126 */ +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- vmmc-supply = <&vmmc2>; +- bus-width = <4>; +- cd-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>; +- /*wp-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;*/ /* GPIO_127 */ +-}; +- +-&mmc3 { +- vmmc-supply = <&wlan_en>; +- +- bus-width = <4>; +- non-removable; +- ti,non-removable; +- cap-power-off-card; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc3_pins>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- wlan: wifi@1 { +- compatible = "ti,wl1251"; +- +- reg = <1>; +- +- interrupt-parent = <&gpio1>; +- interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_21 */ +- +- ti,wl1251-has-eeprom; +- }; +-}; +- +-/* bluetooth*/ +-&uart1 { +-}; +- +-/* spare (expansion connector) */ +-&uart2 { +-}; +- +-/* console (expansion connector) */ +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; +-}; +- +-&usbhshost { +- port2-mode = "ehci-phy"; +-}; +- +-&usbhsehci { +- phys = <0 &hsusb2_phy>; +-}; +- +-&gpmc { +- ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ +- +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- nand-bus-width = <16>; +- ti,nand-ecc-opt = "sw"; +- +- gpmc,sync-clk-ps = <0>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <44>; +- gpmc,cs-wr-off-ns = <44>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <34>; +- gpmc,adv-wr-off-ns = <44>; +- gpmc,we-off-ns = <40>; +- gpmc,oe-off-ns = <54>; +- gpmc,access-ns = <64>; +- gpmc,rd-cycle-ns = <82>; +- gpmc,wr-cycle-ns = <82>; +- gpmc,wr-access-ns = <40>; +- gpmc,wr-data-mux-bus-ns = <0>; +- gpmc,device-width = <2>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* u-boot uses mtdparts=nand:512k(xloader),1920k(uboot),128k(uboot-env),10m(boot),-(rootfs) */ +- +- x-loader@0 { +- label = "xloader"; +- reg = <0 0x80000>; +- }; +- +- bootloaders@80000 { +- label = "uboot"; +- reg = <0x80000 0x1e0000>; +- }; +- +- bootloaders_env@260000 { +- label = "uboot-env"; +- reg = <0x260000 0x20000>; +- }; +- +- kernel@280000 { +- label = "boot"; +- reg = <0x280000 0xa00000>; +- }; +- +- filesystem@c80000 { +- label = "rootfs"; +- reg = <0xc80000 0>; /* 0 = MTDPART_SIZ_FULL */ +- }; +- }; +-}; +- +-&mcspi1 { +- tsc2046@0 { +- reg = <0>; /* CS0 */ +- compatible = "ti,tsc2046"; +- spi-max-frequency = <1000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&penirq_pins>; +- interrupt-parent = <&gpio3>; +- interrupts = <30 IRQ_TYPE_NONE>; /* GPIO_94 */ +- pendown-gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; +- vcc-supply = <&vaux4>; +- +- ti,x-min = /bits/ 16 <0>; +- ti,x-max = /bits/ 16 <8000>; +- ti,y-min = /bits/ 16 <0>; +- ti,y-max = /bits/ 16 <4800>; +- ti,x-plate-ohms = /bits/ 16 <40>; +- ti,pressure-max = /bits/ 16 <255>; +- +- wakeup-source; +- }; +- +- lcd: lcd@1 { +- reg = <1>; /* CS1 */ +- compatible = "tpo,td043mtea1"; +- spi-max-frequency = <100000>; +- spi-cpol; +- spi-cpha; +- +- label = "lcd"; +- reset-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; /* GPIO_157 */ +- vcc-supply = <&vaux1>; +- +- port { +- lcd_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- }; +- +- +-}; +- +-/* n/a - used as GPIOs */ +-&mcbsp1 { +-}; +- +-/* audio DAC */ +-&mcbsp2 { +-}; +- +-/* bluetooth */ +-&mcbsp3 { +-}; +- +-/* to twl4030*/ +-&mcbsp4 { +-}; +- +-&venc { +- status = "okay"; +- +- vdda-supply = <&vdac>; +- +- port { +- venc_out: endpoint { +- remote-endpoint = <&tv_connector_in>; +- ti,channels = <2>; +- }; +- }; +-}; +- +-&dss { +- pinctrl-names = "default"; +- pinctrl-0 = < &dss_dpi_pins >; +- +- status = "okay"; +- vdds_dsi-supply = <&vpll2>; +- +- port { +- dpi_out: endpoint { +- remote-endpoint = <&lcd_in>; +- data-lines = <24>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-panel-sharp-ls037v7dw01.dtsi b/scripts/dtc/include-prefixes/arm/omap3-panel-sharp-ls037v7dw01.dtsi +deleted file mode 100644 +index 2dbb687d4df2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-panel-sharp-ls037v7dw01.dtsi ++++ /dev/null +@@ -1,73 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Common file for omap dpi panels with QVGA and reset pins +- * +- * Note that the board specifc DTS file needs to specify +- * at minimum the GPIO enable-gpios for display, and +- * gpios for gpio-backlight. +- */ +- +-/ { +- aliases { +- display0 = &lcd0; +- }; +- +- backlight0: backlight { +- compatible = "gpio-backlight"; +- default-on; +- }; +- +- /* 3.3V GPIO controlled regulator for LCD_ENVDD */ +- lcd_3v3: regulator-lcd-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "lcd_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <70000>; +- }; +- +- lcd0: display { +- compatible = "sharp,ls037v7dw01"; +- label = "lcd"; +- power-supply = <&lcd_3v3>; +- envdd-supply = <&lcd_3v3>; +- +- port { +- lcd_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- }; +-}; +- +-/* Needed to power the DPI pins */ +-&vpll2 { +- regulator-always-on; +-}; +- +-&dss { +- status = "okay"; +- port { +- dpi_out: endpoint { +- remote-endpoint = <&lcd_in>; +- data-lines = <18>; +- }; +- }; +-}; +- +-&mcspi1 { +- tsc2046@0 { +- reg = <0>; /* CS0 */ +- compatible = "ti,tsc2046"; +- spi-max-frequency = <1000000>; +- vcc-supply = <&lcd_3v3>; +- ti,x-min = /bits/ 16 <0>; +- ti,x-max = /bits/ 16 <8000>; +- ti,y-min = /bits/ 16 <0>; +- ti,y-max = /bits/ 16 <4800>; +- ti,x-plate-ohms = /bits/ 16 <40>; +- ti,pressure-max = /bits/ 16 <255>; +- ti,swap-xy; +- wakeup-source; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-sb-t35.dtsi b/scripts/dtc/include-prefixes/arm/omap3-sb-t35.dtsi +deleted file mode 100644 +index fb9842fa922c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-sb-t35.dtsi ++++ /dev/null +@@ -1,138 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730 +- */ +- +-/ { +- tfp410: encoder { +- compatible = "ti,tfp410"; +- +- powerdown-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */ +- +- pinctrl-names = "default"; +- pinctrl-0 = <&tfp410_pins>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tfp410_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- tfp410_out: endpoint { +- remote-endpoint = <&dvi_connector_in>; +- }; +- }; +- }; +- }; +- +- dvi0: dvi-connector { +- compatible = "dvi-connector"; +- label = "dvi"; +- +- port { +- dvi_connector_in: endpoint { +- remote-endpoint = <&tfp410_out>; +- }; +- }; +- }; +- +- audio_amp: audio_amp { +- compatible = "regulator-fixed"; +- regulator-name = "audio_amp"; +- pinctrl-names = "default"; +- pinctrl-0 = <&sb_t35_audio_amp>; +- gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; /* gpio_61 */ +- regulator-always-on; +- }; +-}; +- +-&omap3_pmx_core { +- smsc2_pins: pinmux_smsc2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20b6, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs4.gpmc_ncs4 */ +- OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */ +- >; +- }; +- +- tfp410_pins: pinmux_tfp410_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ +- >; +- }; +- +- i2c3_pins: pinmux_i2c3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ +- OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ +- >; +- }; +- +- sb_t35_audio_amp: pinmux_sb_t35_audio_amp { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) /* gpmc_nbe1.gpio_61 */ +- >; +- }; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- +- clock-frequency = <400000>; +- +- at24@50 { +- compatible = "atmel,24c02"; +- pagesize = <16>; +- reg = <0x50>; +- }; +-}; +- +-&gpmc { +- ranges = <4 0 0x2d000000 0x01000000>; +- +- smsc2: ethernet@4,0 { +- compatible = "smsc,lan9221", "smsc,lan9115"; +- pinctrl-names = "default"; +- pinctrl-0 = <&smsc2_pins>; +- interrupt-parent = <&gpio3>; +- interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +- reg = <4 0 0xff>; +- bank-width = <2>; +- gpmc,device-width = <1>; +- gpmc,cycle2cycle-samecsen = <1>; +- gpmc,cycle2cycle-diffcsen = <1>; +- gpmc,cs-on-ns = <5>; +- gpmc,cs-rd-off-ns = <150>; +- gpmc,cs-wr-off-ns = <150>; +- gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <15>; +- gpmc,adv-wr-off-ns = <40>; +- gpmc,oe-on-ns = <45>; +- gpmc,oe-off-ns = <140>; +- gpmc,we-on-ns = <45>; +- gpmc,we-off-ns = <140>; +- gpmc,rd-cycle-ns = <155>; +- gpmc,wr-cycle-ns = <155>; +- gpmc,access-ns = <120>; +- gpmc,page-burst-access-ns = <20>; +- gpmc,bus-turnaround-ns = <75>; +- gpmc,cycle2cycle-delay-ns = <75>; +- gpmc,wait-monitoring-ns = <0>; +- gpmc,clk-activation-ns = <0>; +- gpmc,wr-data-mux-bus-ns = <0>; +- gpmc,wr-access-ns = <0>; +- vddvario-supply = <&vddvario>; +- vdd33a-supply = <&vdd33a>; +- reg-io-width = <4>; +- smsc,save-mac-address; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-sbc-t3517.dts b/scripts/dtc/include-prefixes/arm/omap3-sbc-t3517.dts +deleted file mode 100644 +index a69d32860421..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-sbc-t3517.dts ++++ /dev/null +@@ -1,76 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Suppport for CompuLab SBC-T3517 with CM-T3517 +- */ +- +-#include "omap3-cm-t3517.dts" +-#include "omap3-sb-t35.dtsi" +- +-/ { +- model = "CompuLab SBC-T3517 with CM-T3517"; +- compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; +- +- aliases { +- display0 = &dvi0; +- display1 = &tv0; +- }; +- +- /* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */ +- vddvario: regulator-vddvario-sb-t35 { +- compatible = "regulator-fixed"; +- regulator-name = "vddvario"; +- regulator-always-on; +- }; +- +- vdd33a: regulator-vdd33a-sb-t35 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd33a"; +- regulator-always-on; +- }; +-}; +- +-&omap3_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &sb_t35_usb_hub_pins +- &usb_hub_pins +- >; +- +- mmc1_aux_pins: pinmux_mmc1_aux_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20c0, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_clk.gpio_59 */ +- OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_cts.gpio_144 */ +- >; +- }; +- +- sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21ec, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_98 - SB-T35 USB HUB RST */ +- >; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &mmc1_pins +- &mmc1_aux_pins +- >; +- +- wp-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59 */ +- cd-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ +-}; +- +-&dss { +- port { +- dpi_out: endpoint { +- remote-endpoint = <&tfp410_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-&gpmc { +- ranges = <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ +- <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-sbc-t3530.dts b/scripts/dtc/include-prefixes/arm/omap3-sbc-t3530.dts +deleted file mode 100644 +index 24bf3fd86641..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-sbc-t3530.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Suppport for CompuLab SBC-T3530 with CM-T3530 +- */ +- +-#include "omap3-cm-t3530.dts" +-#include "omap3-sb-t35.dtsi" +- +-/ { +- model = "CompuLab SBC-T3530 with CM-T3530"; +- compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; +- +- aliases { +- display0 = &dvi0; +- display1 = &tv0; +- }; +-}; +- +-&omap3_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = <&sb_t35_usb_hub_pins>; +- +- sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ +- >; +- }; +-}; +- +-&gpmc { +- ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */ +- <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ +- <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ +-}; +- +-&mmc1 { +- cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>; +-}; +- +-&dss { +- port { +- dpi_out: endpoint { +- remote-endpoint = <&tfp410_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-sbc-t3730.dts b/scripts/dtc/include-prefixes/arm/omap3-sbc-t3730.dts +deleted file mode 100644 +index eb3893b9535e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-sbc-t3730.dts ++++ /dev/null +@@ -1,44 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Suppport for CompuLab SBC-T3730 with CM-T3730 +- */ +- +-#include "omap3-cm-t3730.dts" +-#include "omap3-sb-t35.dtsi" +- +-/ { +- model = "CompuLab SBC-T3730 with CM-T3730"; +- compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +- +- aliases { +- display0 = &dvi0; +- display1 = &tv0; +- }; +-}; +- +-&omap3_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = <&sb_t35_usb_hub_pins>; +- +- sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ +- >; +- }; +-}; +- +-&gpmc { +- ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */ +- <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ +- <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ +-}; +- +-&dss { +- port { +- dpi_out: endpoint { +- remote-endpoint = <&tfp410_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap3-sniper.dts b/scripts/dtc/include-prefixes/arm/omap3-sniper.dts +deleted file mode 100644 +index b6879cdc5c13..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-sniper.dts ++++ /dev/null +@@ -1,251 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015-2016 Paul Kocialkowski +- */ +-/dts-v1/; +- +-#include "omap36xx.dtsi" +-#include +- +-/ { +- model = "LG Optimus Black"; +- compatible = "lg,omap3-sniper", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&vcc>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512 MB */ +- }; +-}; +- +-&omap3_pmx_core { +- pinctrl-names = "default"; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ +- OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ +- >; +- }; +- +- dp3t_sel_pins: pinmux_dp3t_sel_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE4) /* gpio_161 */ +- OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* gpio_162 */ +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ +- OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ +- >; +- }; +- +- i2c2_pins: pinmux_i2c2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ +- OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ +- >; +- }; +- +- i2c3_pins: pinmux_i2c3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ +- OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ +- >; +- }; +- +- lp8720_en_pin: pinmux_lp8720_en_pin { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2080, PIN_OUTPUT | MUX_MODE4) /* gpio_37 */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT | MUX_MODE0) /* sdmmc1_clk */ +- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd */ +- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0 */ +- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1 */ +- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2 */ +- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3 */ +- >; +- }; +- +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT | MUX_MODE0) /* sdmmc2_clk */ +- OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT | MUX_MODE0) /* sdmmc2_cmd */ +- OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat0 */ +- OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat1 */ +- OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat2 */ +- OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat3 */ +- OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat4 */ +- OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat5 */ +- OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat6 */ +- OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7 */ +- >; +- }; +- +- usb_otg_hs_pins: pinmux_usb_otg_hs_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk */ +- OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp */ +- OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir */ +- OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt */ +- OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0 */ +- OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1 */ +- OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2 */ +- OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3 */ +- OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4 */ +- OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5 */ +- OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6 */ +- OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7 */ +- >; +- }; +-}; +- +-&omap3_pmx_wkup { +- pinctrl-names = "default"; +- +- mmc1_cd_pin: pinmux_mmc1_cd_pin { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | MUX_MODE4) /* gpio_10 */ +- >; +- }; +-}; +- +-&gpio2 { +- ti,no-reset-on-init; +-}; +- +-&gpio5 { +- ti,no-reset-on-init; +-}; +- +-&gpio6 { +- ti,no-reset-on-init; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins &dp3t_sel_pins>; +- +- interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- +- clock-frequency = <2600000>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- interrupt-parent = <&intc>; +- +- power { +- compatible = "ti,twl4030-power"; +- ti,use_poweroff; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- +- clock-frequency = <400000>; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- +- clock-frequency = <400000>; +- +- lp8720@7d { +- pinctrl-names = "default"; +- pinctrl-0 = <&lp8720_en_pin>; +- +- compatible = "ti,lp8720"; +- reg = <0x7d>; +- +- enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* gpio_37 */ +- +- lp8720_ldo1: ldo1 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins &mmc1_cd_pin>; +- +- vmmc-supply = <&lp8720_ldo1>; +- cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* gpio 10 */ +- bus-width = <4>; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- +- vmmc-supply = <&vmmc2>; +- ti,non-removable; +- bus-width = <8>; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-&usb_otg_hs { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_otg_hs_pins>; +- +- interface-type = <0>; +- usb-phy = <&usb2_phy>; +- phys = <&usb2_phy>; +- phy-names = "usb2-phy"; +- mode = <3>; +- power = <50>; +-}; +- +-#include "twl4030.dtsi" +-#include "twl4030_omap3.dtsi" +- +-&twl_keypad { +- linux,keymap = < +- MATRIX_KEY(0x00, 0x00, KEY_VOLUMEUP) +- MATRIX_KEY(0x01, 0x00, KEY_VOLUMEDOWN) +- MATRIX_KEY(0x02, 0x00, KEY_SELECT) +- >; +-}; +- +-/* +- * The TWL4030 VAUX2 and VDAC regulators power sensors that are slaves on I2C3. +- * When not powered, these sensors cause the I2C3 clock to stay low at all times, +- * making it impossible to reach other devices on I2C3. +- */ +- +-&vaux2 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +-}; +- +-&vdac { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-tao3530.dtsi b/scripts/dtc/include-prefixes/arm/omap3-tao3530.dtsi +deleted file mode 100644 +index 580bfa1931c8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-tao3530.dtsi ++++ /dev/null +@@ -1,350 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- * Copyright (C) 2014 Stefan Roese +- */ +-/dts-v1/; +- +-#include "omap34xx.dtsi" +- +-/* Secure omaps have some devices inaccessible depending on the firmware */ +-&aes1_target { +- status = "disabled"; +-}; +- +-&aes2_target { +- status = "disabled"; +-}; +- +-&sham { +- status = "disabled"; +-}; +- +-/ { +- cpus { +- cpu@0 { +- cpu0-supply = <&vcc>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +- +- /* HS USB Port 2 Power */ +- hsusb2_power: hsusb2_power_reg { +- compatible = "regulator-fixed"; +- regulator-name = "hsusb2_vbus"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ +- startup-delay-us = <70000>; +- }; +- +- /* HS USB Host PHY on PORT 2 */ +- hsusb2_phy: hsusb2_phy { +- compatible = "usb-nop-xceiv"; +- reset-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* gpio_162 */ +- vcc-supply = <&hsusb2_power>; +- #phy-cells = <0>; +- }; +- +- sound { +- compatible = "ti,omap-twl4030"; +- ti,model = "omap3beagle"; +- +- /* McBSP2 is used for onboard sound, same as on beagle */ +- ti,mcbsp = <&mcbsp2>; +- }; +- +- /* Regulator to enable/switch the vcc of the Wifi module */ +- mmc2_sdio_poweron: regulator-mmc2-sdio-poweron { +- compatible = "regulator-fixed"; +- regulator-name = "regulator-mmc2-sdio-poweron"; +- regulator-min-microvolt = <3150000>; +- regulator-max-microvolt = <3150000>; +- gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; /* gpio_157 */ +- startup-delay-us = <10000>; +- }; +-}; +- +-&omap3_pmx_core { +- hsusbb2_pins: pinmux_hsusbb2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ +- OMAP3_CORE1_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ +- OMAP3_CORE1_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ +- OMAP3_CORE1_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ +- OMAP3_CORE1_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ +- OMAP3_CORE1_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ +- OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ +- OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ +- OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ +- OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ +- OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ +- OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ +- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ +- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ +- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ +- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ +- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ +- OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ +- OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ +- OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ +- OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ +- >; +- }; +- +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ +- OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ +- OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ +- OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ +- OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ +- OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ +- >; +- }; +- +- /* wlan GPIO output for WLAN_EN */ +- wlan_gpio: pinmux_wlan_gpio { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr gpio_157 */ +- >; +- }; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ +- OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ +- >; +- }; +- +- i2c3_pins: pinmux_i2c3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl.i2c3_scl */ +- OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.i2c3_sda */ +- >; +- }; +- +- mcspi1_pins: pinmux_mcspi1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ +- OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ +- OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ +- OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ +- >; +- }; +- +- mcspi3_pins: pinmux_mcspi3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x25dc, PIN_OUTPUT | MUX_MODE1) /* etk_d0.mcspi3_simo gpio14 INPUT | MODE1 */ +- OMAP3_CORE1_IOPAD(0x25de, PIN_INPUT_PULLUP | MUX_MODE1) /* etk_d1.mcspi3_somi gpio15 INPUT | MODE1 */ +- OMAP3_CORE1_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE1) /* etk_d2.mcspi3_cs0 gpio16 INPUT | MODE1 */ +- OMAP3_CORE1_IOPAD(0x25e2, PIN_INPUT | MUX_MODE1) /* etk_d3.mcspi3_clk gpio17 INPUT | MODE1 */ +- >; +- }; +- +- mcbsp3_pins: pinmux_mcbsp3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.uart2_cts */ +- OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dr.uart2_rts */ +- OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0) /* mcbsp3_clk.uart2_tx */ +- OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0) /* mcbsp3_fsx.uart2_rx */ +- >; +- }; +-}; +- +-/* McBSP1: mux'ed with GPIO158 as clock for HA-DSP */ +-&mcbsp1 { +- status = "disabled"; +-}; +- +-&mcbsp2 { +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <2600000>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- interrupt-parent = <&intc>; +- +- twl_audio: audio { +- compatible = "ti,twl4030-audio"; +- codec { +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +-}; +- +-&mcspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcspi1_pins>; +- +- spidev@0 { +- compatible = "spidev"; +- spi-max-frequency = <48000000>; +- reg = <0>; +- spi-cpha; +- }; +-}; +- +-&mcspi3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcspi3_pins>; +- +- spidev@0 { +- compatible = "spidev"; +- spi-max-frequency = <48000000>; +- reg = <0>; +- spi-cpha; +- }; +-}; +- +-#include "twl4030.dtsi" +-#include "twl4030_omap3.dtsi" +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <&vmmc1>; +- vqmmc-supply = <&vsim>; +- cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; +- bus-width = <8>; +-}; +- +-// WiFi (Marvell 88W8686) on MMC2/SDIO +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- vmmc-supply = <&mmc2_sdio_poweron>; +- non-removable; +- bus-width = <4>; +- cap-power-off-card; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-&usbhshost { +- port2-mode = "ehci-phy"; +-}; +- +-&usbhsehci { +- phys = <0 &hsusb2_phy>; +-}; +- +-&twl_gpio { +- ti,use-leds; +- /* pullups: BIT(1) */ +- ti,pullups = <0x000002>; +- /* +- * pulldowns: +- * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) +- * BIT(15), BIT(16), BIT(17) +- */ +- ti,pulldowns = <0x03a1c4>; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +-}; +- +-&mcbsp3 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp3_pins>; +-}; +- +-&gpmc { +- ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ +- +- nand@0,0 { +- compatible = "ti,omap2-nand"; +- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- nand-bus-width = <16>; +- gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ +- ti,nand-ecc-opt = "sw"; +- +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <36>; +- gpmc,cs-wr-off-ns = <36>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <24>; +- gpmc,adv-wr-off-ns = <36>; +- gpmc,oe-on-ns = <6>; +- gpmc,oe-off-ns = <48>; +- gpmc,we-on-ns = <6>; +- gpmc,we-off-ns = <30>; +- gpmc,rd-cycle-ns = <72>; +- gpmc,wr-cycle-ns = <72>; +- gpmc,access-ns = <54>; +- gpmc,wr-access-ns = <30>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- x-loader@0 { +- label = "X-Loader"; +- reg = <0 0x80000>; +- }; +- +- bootloaders@80000 { +- label = "U-Boot"; +- reg = <0x80000 0x1e0000>; +- }; +- +- bootloaders_env@260000 { +- label = "U-Boot Env"; +- reg = <0x260000 0x20000>; +- }; +- +- kernel@280000 { +- label = "Kernel"; +- reg = <0x280000 0x400000>; +- }; +- +- filesystem@680000 { +- label = "File System"; +- reg = <0x680000 0xf980000>; +- }; +- }; +-}; +- +-&usb_otg_hs { +- interface-type = <0>; +- usb-phy = <&usb2_phy>; +- phys = <&usb2_phy>; +- phy-names = "usb2-phy"; +- mode = <3>; +- power = <50>; +-}; +- +-&vaux2 { +- regulator-name = "vdd_ehci"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-thunder.dts b/scripts/dtc/include-prefixes/arm/omap3-thunder.dts +deleted file mode 100644 +index d82cab8e213a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-thunder.dts ++++ /dev/null +@@ -1,126 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- * Copyright (C) 2014 Stefan Roese +- */ +- +-#include "omap3-tao3530.dtsi" +- +-/ { +- model = "TI OMAP3 Thunder baseboard with TAO3530 SOM"; +- compatible = "technexion,omap3-thunder", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; +-}; +- +-&omap3_pmx_core { +- dss_dpi_pins: pinmux_dss_dpi_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ +- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ +- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ +- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ +- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ +- OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ +- OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ +- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ +- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ +- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ +- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ +- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ +- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ +- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ +- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ +- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ +- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ +- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ +- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ +- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ +- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ +- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ +- OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ +- OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ +- OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ +- OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ +- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ +- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ +- >; +- }; +- +- lte430_pins: pinmux_lte430_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ +- >; +- }; +- +- backlight_pins: pinmux_backlight_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ +- >; +- }; +-}; +- +-/* Needed to power the DPI pins */ +-&vpll2 { +- regulator-always-on; +-}; +- +-&dss { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_dpi_pins>; +- +- port { +- dpi_out: endpoint { +- remote-endpoint = <&lcd_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-/ { +- aliases { +- display0 = &lcd0; +- }; +- +- lcd0: display { +- compatible = "samsung,lte430wq-f0c", "panel-dpi"; +- label = "lcd"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <<e430_pins>; +- enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */ +- +- port { +- lcd_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- +- panel-timing { +- clock-frequency = <9000000>; +- hactive = <480>; +- vactive = <272>; +- hfront-porch = <3>; +- hback-porch = <2>; +- hsync-len = <42>; +- vback-porch = <2>; +- vfront-porch = <3>; +- vsync-len = <11>; +- +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- +- backlight { +- compatible = "gpio-backlight"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&backlight_pins>; +- gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */ +- +- default-on; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3-zoom3.dts b/scripts/dtc/include-prefixes/arm/omap3-zoom3.dts +deleted file mode 100644 +index 0482676d1830..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3-zoom3.dts ++++ /dev/null +@@ -1,231 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "omap36xx.dtsi" +-#include "omap-zoom-common.dtsi" +- +-/ { +- model = "TI Zoom3"; +- compatible = "ti,omap3-zoom3", "ti,omap3630", "ti,omap36xx", "ti,omap3"; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&vcc>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512 MB */ +- }; +- +- vddvario: regulator-vddvario { +- compatible = "regulator-fixed"; +- regulator-name = "vddvario"; +- regulator-always-on; +- }; +- +- vdd33a: regulator-vdd33a { +- compatible = "regulator-fixed"; +- regulator-name = "vdd33a"; +- regulator-always-on; +- }; +- +- wl12xx_vmmc: wl12xx_vmmc { +- pinctrl-names = "default"; +- pinctrl-0 = <&wl12xx_gpio>; +- compatible = "regulator-fixed"; +- regulator-name = "vwl1271"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ +- startup-delay-us = <70000>; +- enable-active-high; +- }; +-}; +- +-&omap3_pmx_core { +- /* REVISIT: twl gpio0 is mmc0_cd */ +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ +- OMAP3_CORE1_IOPAD(0x2146, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ +- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ +- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ +- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ +- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ +- >; +- }; +- +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ +- OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ +- OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ +- OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ +- OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ +- OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ +- OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */ +- OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */ +- OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */ +- OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */ +- >; +- }; +- +- mmc3_pins: pinmux_mmc3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 WLAN IRQ */ +- OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ +- >; +- }; +- +- uart1_pins: pinmux_uart1_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ +- OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ +- OMAP3_CORE1_IOPAD(0x2182, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ +- OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ +- >; +- }; +- +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ +- OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ +- OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ +- OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ +- >; +- }; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ +- OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ +- OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ +- OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ +- >; +- }; +- +- /* wl12xx GPIO output for WLAN_EN */ +- wl12xx_gpio: pinmux_wl12xx_gpio { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x211a, PIN_OUTPUT| MUX_MODE4) /* cam_d2.gpio_101 */ +- >; +- }; +-}; +- +-&omap3_pmx_core2 { +- mmc3_2_pins: pinmux_mmc3_2_pins { +- pinctrl-single,pins = < +- OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ +- OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ +- OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ +- OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ +- OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ +- >; +- }; +-}; +- +-&omap3_pmx_wkup { +- wlan_host_wkup: pinmux_wlan_host_wkup_pins { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_clkout1.gpio_10 WLAN_HOST_WKUP */ +- >; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <2600000>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- interrupt-parent = <&intc>; +- }; +-}; +- +-#include "twl4030.dtsi" +- +-&i2c2 { +- clock-frequency = <400000>; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +- +- /* +- * TVP5146 Video decoder-in for analog input support. +- */ +- tvp5146@5c { +- compatible = "ti,tvp5146m2"; +- reg = <0x5c>; +- }; +-}; +- +-&twl_gpio { +- ti,use-leds; +-}; +- +-&mmc1 { +- vmmc-supply = <&vmmc1>; +- vqmmc-supply = <&vsim>; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +-}; +-/* +-&mmc2 { +- vmmc-supply = <&vmmc2>; +- ti,non-removable; +- bus-width = <8>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +-}; +-*/ +-&mmc3 { +- vmmc-supply = <&wl12xx_vmmc>; +- non-removable; +- bus-width = <4>; +- cap-power-off-card; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc3_pins &mmc3_2_pins>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1271"; +- reg = <2>; +- interrupt-parent = <&gpio6>; +- interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 162 */ +- ref-clock-frequency = <26000000>; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +-}; +- +-&uart4 { +- status = "disabled"; +-}; +- +-&usb_otg_hs { +- interface-type = <0>; +- usb-phy = <&usb2_phy>; +- mode = <3>; +- power = <50>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3.dtsi b/scripts/dtc/include-prefixes/arm/omap3.dtsi +deleted file mode 100644 +index 64b7e6fddd1b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3.dtsi ++++ /dev/null +@@ -1,1020 +0,0 @@ +-/* +- * Device Tree Source for OMAP3 SoC +- * +- * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "ti,omap3430", "ti,omap3"; +- interrupt-parent = <&intc>; +- #address-cells = <1>; +- #size-cells = <1>; +- chosen { }; +- +- aliases { +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- mmc0 = &mmc1; +- mmc1 = &mmc2; +- mmc2 = &mmc3; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,cortex-a8"; +- device_type = "cpu"; +- reg = <0x0>; +- +- clocks = <&dpll1_ck>; +- clock-names = "cpu"; +- +- clock-latency = <300000>; /* From omap-cpufreq driver */ +- }; +- }; +- +- pmu@54000000 { +- compatible = "arm,cortex-a8-pmu"; +- reg = <0x54000000 0x800000>; +- interrupts = <3>; +- ti,hwmods = "debugss"; +- }; +- +- /* +- * The soc node represents the soc top level view. It is used for IPs +- * that are not memory mapped in the MPU view or for the MPU itself. +- */ +- soc { +- compatible = "ti,omap-infra"; +- mpu { +- compatible = "ti,omap3-mpu"; +- ti,hwmods = "mpu"; +- }; +- +- iva: iva { +- compatible = "ti,iva2.2"; +- ti,hwmods = "iva"; +- +- dsp { +- compatible = "ti,omap3-c64"; +- }; +- }; +- }; +- +- /* +- * XXX: Use a flat representation of the OMAP3 interconnect. +- * The real OMAP interconnect network is quite complex. +- * Since it will not bring real advantage to represent that in DT for +- * the moment, just use a fake OCP bus entry to represent the whole bus +- * hierarchy. +- */ +- ocp@68000000 { +- compatible = "ti,omap3-l3-smx", "simple-bus"; +- reg = <0x68000000 0x10000>; +- interrupts = <9 10>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- ti,hwmods = "l3_main"; +- +- l4_core: l4@48000000 { +- compatible = "ti,omap3-l4-core", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x48000000 0x1000000>; +- +- scm: scm@2000 { +- compatible = "ti,omap3-scm", "simple-bus"; +- reg = <0x2000 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x2000 0x2000>; +- +- omap3_pmx_core: pinmux@30 { +- compatible = "ti,omap3-padconf", +- "pinctrl-single"; +- reg = <0x30 0x238>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <1>; +- #interrupt-cells = <1>; +- interrupt-controller; +- pinctrl-single,register-width = <16>; +- pinctrl-single,function-mask = <0xff1f>; +- }; +- +- scm_conf: scm_conf@270 { +- compatible = "syscon", "simple-bus"; +- reg = <0x270 0x330>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x270 0x330>; +- +- pbias_regulator: pbias_regulator@2b0 { +- compatible = "ti,pbias-omap3", "ti,pbias-omap"; +- reg = <0x2b0 0x4>; +- syscon = <&scm_conf>; +- pbias_mmc_reg: pbias_mmc_omap2430 { +- regulator-name = "pbias_mmc_omap2430"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- }; +- }; +- +- scm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- scm_clockdomains: clockdomains { +- }; +- +- omap3_pmx_wkup: pinmux@a00 { +- compatible = "ti,omap3-padconf", +- "pinctrl-single"; +- reg = <0xa00 0x5c>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <1>; +- #interrupt-cells = <1>; +- interrupt-controller; +- pinctrl-single,register-width = <16>; +- pinctrl-single,function-mask = <0xff1f>; +- }; +- }; +- }; +- +- aes1_target: target-module@480a6000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x480a6044 0x4>, +- <0x480a6048 0x4>, +- <0x480a604c 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- clocks = <&aes1_ick>; +- clock-names = "ick"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x480a6000 0x2000>; +- +- aes1: aes1@0 { +- compatible = "ti,omap3-aes"; +- reg = <0 0x50>; +- interrupts = <0>; +- dmas = <&sdma 9 &sdma 10>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- aes2_target: target-module@480c5000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x480c5044 0x4>, +- <0x480c5048 0x4>, +- <0x480c504c 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- clocks = <&aes2_ick>; +- clock-names = "ick"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x480c5000 0x2000>; +- +- aes2: aes2@0 { +- compatible = "ti,omap3-aes"; +- reg = <0 0x50>; +- interrupts = <0>; +- dmas = <&sdma 65 &sdma 66>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- prm: prm@48306000 { +- compatible = "ti,omap3-prm"; +- reg = <0x48306000 0x4000>; +- interrupts = <11>; +- +- prm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- prm_clockdomains: clockdomains { +- }; +- }; +- +- cm: cm@48004000 { +- compatible = "ti,omap3-cm"; +- reg = <0x48004000 0x4000>; +- +- cm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- cm_clockdomains: clockdomains { +- }; +- }; +- +- target-module@48320000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x48320000 0x4>, +- <0x48320004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- ; +- clocks = <&wkup_32k_fck>, <&omap_32ksync_ick>; +- clock-names = "fck", "ick"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x48320000 0x1000>; +- +- counter32k: counter@0 { +- compatible = "ti,omap-counter32k"; +- reg = <0x0 0x20>; +- }; +- }; +- +- intc: interrupt-controller@48200000 { +- compatible = "ti,omap3-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x48200000 0x1000>; +- }; +- +- target-module@48056000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x48056000 0x4>, +- <0x4805602c 0x4>, +- <0x48056028 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */ +- clocks = <&core_l3_ick>; +- clock-names = "ick"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x48056000 0x1000>; +- +- sdma: dma-controller@0 { +- compatible = "ti,omap3430-sdma", "ti,omap-sdma"; +- reg = <0x0 0x1000>; +- interrupts = <12>, +- <13>, +- <14>, +- <15>; +- #dma-cells = <1>; +- dma-channels = <32>; +- dma-requests = <96>; +- }; +- }; +- +- gpio1: gpio@48310000 { +- compatible = "ti,omap3-gpio"; +- reg = <0x48310000 0x200>; +- interrupts = <29>; +- ti,hwmods = "gpio1"; +- ti,gpio-always-on; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@49050000 { +- compatible = "ti,omap3-gpio"; +- reg = <0x49050000 0x200>; +- interrupts = <30>; +- ti,hwmods = "gpio2"; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio@49052000 { +- compatible = "ti,omap3-gpio"; +- reg = <0x49052000 0x200>; +- interrupts = <31>; +- ti,hwmods = "gpio3"; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio4: gpio@49054000 { +- compatible = "ti,omap3-gpio"; +- reg = <0x49054000 0x200>; +- interrupts = <32>; +- ti,hwmods = "gpio4"; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio5: gpio@49056000 { +- compatible = "ti,omap3-gpio"; +- reg = <0x49056000 0x200>; +- interrupts = <33>; +- ti,hwmods = "gpio5"; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio6: gpio@49058000 { +- compatible = "ti,omap3-gpio"; +- reg = <0x49058000 0x200>; +- interrupts = <34>; +- ti,hwmods = "gpio6"; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- uart1: serial@4806a000 { +- compatible = "ti,omap3-uart"; +- reg = <0x4806a000 0x2000>; +- interrupts-extended = <&intc 72>; +- dmas = <&sdma 49 &sdma 50>; +- dma-names = "tx", "rx"; +- ti,hwmods = "uart1"; +- clock-frequency = <48000000>; +- }; +- +- uart2: serial@4806c000 { +- compatible = "ti,omap3-uart"; +- reg = <0x4806c000 0x400>; +- interrupts-extended = <&intc 73>; +- dmas = <&sdma 51 &sdma 52>; +- dma-names = "tx", "rx"; +- ti,hwmods = "uart2"; +- clock-frequency = <48000000>; +- }; +- +- uart3: serial@49020000 { +- compatible = "ti,omap3-uart"; +- reg = <0x49020000 0x400>; +- interrupts-extended = <&intc 74>; +- dmas = <&sdma 53 &sdma 54>; +- dma-names = "tx", "rx"; +- ti,hwmods = "uart3"; +- clock-frequency = <48000000>; +- }; +- +- i2c1: i2c@48070000 { +- compatible = "ti,omap3-i2c"; +- reg = <0x48070000 0x80>; +- interrupts = <56>; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,hwmods = "i2c1"; +- }; +- +- i2c2: i2c@48072000 { +- compatible = "ti,omap3-i2c"; +- reg = <0x48072000 0x80>; +- interrupts = <57>; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,hwmods = "i2c2"; +- }; +- +- i2c3: i2c@48060000 { +- compatible = "ti,omap3-i2c"; +- reg = <0x48060000 0x80>; +- interrupts = <61>; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,hwmods = "i2c3"; +- }; +- +- mailbox: mailbox@48094000 { +- compatible = "ti,omap3-mailbox"; +- ti,hwmods = "mailbox"; +- reg = <0x48094000 0x200>; +- interrupts = <26>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <2>; +- ti,mbox-num-fifos = <2>; +- mbox_dsp: mbox-dsp { +- ti,mbox-tx = <0 0 0>; +- ti,mbox-rx = <1 0 0>; +- }; +- }; +- +- mcspi1: spi@48098000 { +- compatible = "ti,omap2-mcspi"; +- reg = <0x48098000 0x100>; +- interrupts = <65>; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,hwmods = "mcspi1"; +- ti,spi-num-cs = <4>; +- dmas = <&sdma 35>, +- <&sdma 36>, +- <&sdma 37>, +- <&sdma 38>, +- <&sdma 39>, +- <&sdma 40>, +- <&sdma 41>, +- <&sdma 42>; +- dma-names = "tx0", "rx0", "tx1", "rx1", +- "tx2", "rx2", "tx3", "rx3"; +- }; +- +- mcspi2: spi@4809a000 { +- compatible = "ti,omap2-mcspi"; +- reg = <0x4809a000 0x100>; +- interrupts = <66>; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,hwmods = "mcspi2"; +- ti,spi-num-cs = <2>; +- dmas = <&sdma 43>, +- <&sdma 44>, +- <&sdma 45>, +- <&sdma 46>; +- dma-names = "tx0", "rx0", "tx1", "rx1"; +- }; +- +- mcspi3: spi@480b8000 { +- compatible = "ti,omap2-mcspi"; +- reg = <0x480b8000 0x100>; +- interrupts = <91>; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,hwmods = "mcspi3"; +- ti,spi-num-cs = <2>; +- dmas = <&sdma 15>, +- <&sdma 16>, +- <&sdma 23>, +- <&sdma 24>; +- dma-names = "tx0", "rx0", "tx1", "rx1"; +- }; +- +- mcspi4: spi@480ba000 { +- compatible = "ti,omap2-mcspi"; +- reg = <0x480ba000 0x100>; +- interrupts = <48>; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,hwmods = "mcspi4"; +- ti,spi-num-cs = <1>; +- dmas = <&sdma 70>, <&sdma 71>; +- dma-names = "tx0", "rx0"; +- }; +- +- hdqw1w: 1w@480b2000 { +- compatible = "ti,omap3-1w"; +- reg = <0x480b2000 0x1000>; +- interrupts = <58>; +- ti,hwmods = "hdq1w"; +- }; +- +- mmc1: mmc@4809c000 { +- compatible = "ti,omap3-hsmmc"; +- reg = <0x4809c000 0x200>; +- interrupts = <83>; +- ti,hwmods = "mmc1"; +- ti,dual-volt; +- dmas = <&sdma 61>, <&sdma 62>; +- dma-names = "tx", "rx"; +- pbias-supply = <&pbias_mmc_reg>; +- }; +- +- mmc2: mmc@480b4000 { +- compatible = "ti,omap3-hsmmc"; +- reg = <0x480b4000 0x200>; +- interrupts = <86>; +- ti,hwmods = "mmc2"; +- dmas = <&sdma 47>, <&sdma 48>; +- dma-names = "tx", "rx"; +- }; +- +- mmc3: mmc@480ad000 { +- compatible = "ti,omap3-hsmmc"; +- reg = <0x480ad000 0x200>; +- interrupts = <94>; +- ti,hwmods = "mmc3"; +- dmas = <&sdma 77>, <&sdma 78>; +- dma-names = "tx", "rx"; +- }; +- +- mmu_isp: mmu@480bd400 { +- #iommu-cells = <0>; +- compatible = "ti,omap2-iommu"; +- reg = <0x480bd400 0x80>; +- interrupts = <24>; +- ti,hwmods = "mmu_isp"; +- ti,#tlb-entries = <8>; +- }; +- +- mmu_iva: mmu@5d000000 { +- #iommu-cells = <0>; +- compatible = "ti,omap2-iommu"; +- reg = <0x5d000000 0x80>; +- interrupts = <28>; +- ti,hwmods = "mmu_iva"; +- status = "disabled"; +- }; +- +- wdt2: wdt@48314000 { +- compatible = "ti,omap3-wdt"; +- reg = <0x48314000 0x80>; +- ti,hwmods = "wd_timer2"; +- }; +- +- mcbsp1: mcbsp@48074000 { +- compatible = "ti,omap3-mcbsp"; +- reg = <0x48074000 0xff>; +- reg-names = "mpu"; +- interrupts = <16>, /* OCP compliant interrupt */ +- <59>, /* TX interrupt */ +- <60>; /* RX interrupt */ +- interrupt-names = "common", "tx", "rx"; +- ti,buffer-size = <128>; +- ti,hwmods = "mcbsp1"; +- dmas = <&sdma 31>, +- <&sdma 32>; +- dma-names = "tx", "rx"; +- clocks = <&mcbsp1_fck>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- +- /* Likely needs to be tagged disabled on HS devices */ +- rng_target: target-module@480a0000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x480a003c 0x4>, +- <0x480a0040 0x4>, +- <0x480a0044 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- ; +- ti,syss-mask = <1>; +- clocks = <&rng_ick>; +- clock-names = "ick"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x480a0000 0x2000>; +- +- rng: rng@0 { +- compatible = "ti,omap2-rng"; +- reg = <0x0 0x2000>; +- interrupts = <52>; +- }; +- }; +- +- mcbsp2: mcbsp@49022000 { +- compatible = "ti,omap3-mcbsp"; +- reg = <0x49022000 0xff>, +- <0x49028000 0xff>; +- reg-names = "mpu", "sidetone"; +- interrupts = <17>, /* OCP compliant interrupt */ +- <62>, /* TX interrupt */ +- <63>, /* RX interrupt */ +- <4>; /* Sidetone */ +- interrupt-names = "common", "tx", "rx", "sidetone"; +- ti,buffer-size = <1280>; +- ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; +- dmas = <&sdma 33>, +- <&sdma 34>; +- dma-names = "tx", "rx"; +- clocks = <&mcbsp2_fck>, <&mcbsp2_ick>; +- clock-names = "fck", "ick"; +- status = "disabled"; +- }; +- +- mcbsp3: mcbsp@49024000 { +- compatible = "ti,omap3-mcbsp"; +- reg = <0x49024000 0xff>, +- <0x4902a000 0xff>; +- reg-names = "mpu", "sidetone"; +- interrupts = <22>, /* OCP compliant interrupt */ +- <89>, /* TX interrupt */ +- <90>, /* RX interrupt */ +- <5>; /* Sidetone */ +- interrupt-names = "common", "tx", "rx", "sidetone"; +- ti,buffer-size = <128>; +- ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; +- dmas = <&sdma 17>, +- <&sdma 18>; +- dma-names = "tx", "rx"; +- clocks = <&mcbsp3_fck>, <&mcbsp3_ick>; +- clock-names = "fck", "ick"; +- status = "disabled"; +- }; +- +- mcbsp4: mcbsp@49026000 { +- compatible = "ti,omap3-mcbsp"; +- reg = <0x49026000 0xff>; +- reg-names = "mpu"; +- interrupts = <23>, /* OCP compliant interrupt */ +- <54>, /* TX interrupt */ +- <55>; /* RX interrupt */ +- interrupt-names = "common", "tx", "rx"; +- ti,buffer-size = <128>; +- ti,hwmods = "mcbsp4"; +- dmas = <&sdma 19>, +- <&sdma 20>; +- dma-names = "tx", "rx"; +- clocks = <&mcbsp4_fck>; +- clock-names = "fck"; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- mcbsp5: mcbsp@48096000 { +- compatible = "ti,omap3-mcbsp"; +- reg = <0x48096000 0xff>; +- reg-names = "mpu"; +- interrupts = <27>, /* OCP compliant interrupt */ +- <81>, /* TX interrupt */ +- <82>; /* RX interrupt */ +- interrupt-names = "common", "tx", "rx"; +- ti,buffer-size = <128>; +- ti,hwmods = "mcbsp5"; +- dmas = <&sdma 21>, +- <&sdma 22>; +- dma-names = "tx", "rx"; +- clocks = <&mcbsp5_fck>; +- clock-names = "fck"; +- status = "disabled"; +- }; +- +- sham: sham@480c3000 { +- compatible = "ti,omap3-sham"; +- ti,hwmods = "sham"; +- reg = <0x480c3000 0x64>; +- interrupts = <49>; +- dmas = <&sdma 69>; +- dma-names = "rx"; +- }; +- +- timer1_target: target-module@48318000 { +- compatible = "ti,sysc-omap2-timer", "ti,sysc"; +- reg = <0x48318000 0x4>, +- <0x48318010 0x4>, +- <0x48318014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- clocks = <&gpt1_fck>, <&gpt1_ick>; +- clock-names = "fck", "ick"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x48318000 0x1000>; +- +- timer1: timer@0 { +- compatible = "ti,omap3430-timer"; +- reg = <0x0 0x80>; +- clocks = <&gpt1_fck>; +- clock-names = "fck"; +- interrupts = <37>; +- ti,timer-alwon; +- }; +- }; +- +- timer2_target: target-module@49032000 { +- compatible = "ti,sysc-omap2-timer", "ti,sysc"; +- reg = <0x49032000 0x4>, +- <0x49032010 0x4>, +- <0x49032014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- clocks = <&gpt2_fck>, <&gpt2_ick>; +- clock-names = "fck", "ick"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x49032000 0x1000>; +- +- timer2: timer@0 { +- compatible = "ti,omap3430-timer"; +- reg = <0 0x400>; +- interrupts = <38>; +- }; +- }; +- +- timer3: timer@49034000 { +- compatible = "ti,omap3430-timer"; +- reg = <0x49034000 0x400>; +- interrupts = <39>; +- ti,hwmods = "timer3"; +- }; +- +- timer4: timer@49036000 { +- compatible = "ti,omap3430-timer"; +- reg = <0x49036000 0x400>; +- interrupts = <40>; +- ti,hwmods = "timer4"; +- }; +- +- timer5: timer@49038000 { +- compatible = "ti,omap3430-timer"; +- reg = <0x49038000 0x400>; +- interrupts = <41>; +- ti,hwmods = "timer5"; +- ti,timer-dsp; +- }; +- +- timer6: timer@4903a000 { +- compatible = "ti,omap3430-timer"; +- reg = <0x4903a000 0x400>; +- interrupts = <42>; +- ti,hwmods = "timer6"; +- ti,timer-dsp; +- }; +- +- timer7: timer@4903c000 { +- compatible = "ti,omap3430-timer"; +- reg = <0x4903c000 0x400>; +- interrupts = <43>; +- ti,hwmods = "timer7"; +- ti,timer-dsp; +- }; +- +- timer8: timer@4903e000 { +- compatible = "ti,omap3430-timer"; +- reg = <0x4903e000 0x400>; +- interrupts = <44>; +- ti,hwmods = "timer8"; +- ti,timer-pwm; +- ti,timer-dsp; +- }; +- +- timer9: timer@49040000 { +- compatible = "ti,omap3430-timer"; +- reg = <0x49040000 0x400>; +- interrupts = <45>; +- ti,hwmods = "timer9"; +- ti,timer-pwm; +- }; +- +- timer10: timer@48086000 { +- compatible = "ti,omap3430-timer"; +- reg = <0x48086000 0x400>; +- interrupts = <46>; +- ti,hwmods = "timer10"; +- ti,timer-pwm; +- }; +- +- timer11: timer@48088000 { +- compatible = "ti,omap3430-timer"; +- reg = <0x48088000 0x400>; +- interrupts = <47>; +- ti,hwmods = "timer11"; +- ti,timer-pwm; +- }; +- +- timer12_target: target-module@48304000 { +- compatible = "ti,sysc-omap2-timer", "ti,sysc"; +- reg = <0x48304000 0x4>, +- <0x48304010 0x4>, +- <0x48304014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- clocks = <&gpt12_fck>, <&gpt12_ick>; +- clock-names = "fck", "ick"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x48304000 0x1000>; +- +- timer12: timer@0 { +- compatible = "ti,omap3430-timer"; +- reg = <0 0x400>; +- interrupts = <95>; +- ti,timer-alwon; +- ti,timer-secure; +- }; +- }; +- +- usbhstll: usbhstll@48062000 { +- compatible = "ti,usbhs-tll"; +- reg = <0x48062000 0x1000>; +- interrupts = <78>; +- ti,hwmods = "usb_tll_hs"; +- }; +- +- usbhshost: usbhshost@48064000 { +- compatible = "ti,usbhs-host"; +- reg = <0x48064000 0x400>; +- ti,hwmods = "usb_host_hs"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- usbhsohci: ohci@48064400 { +- compatible = "ti,ohci-omap3"; +- reg = <0x48064400 0x400>; +- interrupts = <76>; +- remote-wakeup-connected; +- }; +- +- usbhsehci: ehci@48064800 { +- compatible = "ti,ehci-omap"; +- reg = <0x48064800 0x400>; +- interrupts = <77>; +- }; +- }; +- +- gpmc: gpmc@6e000000 { +- compatible = "ti,omap3430-gpmc"; +- ti,hwmods = "gpmc"; +- reg = <0x6e000000 0x02d0>; +- interrupts = <20>; +- dmas = <&sdma 4>; +- dma-names = "rxtx"; +- gpmc,num-cs = <8>; +- gpmc,num-waitpins = <4>; +- #address-cells = <2>; +- #size-cells = <1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- usb_otg_hs: usb_otg_hs@480ab000 { +- compatible = "ti,omap3-musb"; +- reg = <0x480ab000 0x1000>; +- interrupts = <92>, <93>; +- interrupt-names = "mc", "dma"; +- ti,hwmods = "usb_otg_hs"; +- multipoint = <1>; +- num-eps = <16>; +- ram-bits = <12>; +- }; +- +- dss: dss@48050000 { +- compatible = "ti,omap3-dss"; +- reg = <0x48050000 0x200>; +- status = "disabled"; +- ti,hwmods = "dss_core"; +- clocks = <&dss1_alwon_fck>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- dispc@48050400 { +- compatible = "ti,omap3-dispc"; +- reg = <0x48050400 0x400>; +- interrupts = <25>; +- ti,hwmods = "dss_dispc"; +- clocks = <&dss1_alwon_fck>; +- clock-names = "fck"; +- }; +- +- dsi: encoder@4804fc00 { +- compatible = "ti,omap3-dsi"; +- reg = <0x4804fc00 0x200>, +- <0x4804fe00 0x40>, +- <0x4804ff00 0x20>; +- reg-names = "proto", "phy", "pll"; +- interrupts = <25>; +- status = "disabled"; +- ti,hwmods = "dss_dsi1"; +- clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; +- clock-names = "fck", "sys_clk"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- rfbi: encoder@48050800 { +- compatible = "ti,omap3-rfbi"; +- reg = <0x48050800 0x100>; +- status = "disabled"; +- ti,hwmods = "dss_rfbi"; +- clocks = <&dss1_alwon_fck>, <&dss_ick>; +- clock-names = "fck", "ick"; +- }; +- +- venc: encoder@48050c00 { +- compatible = "ti,omap3-venc"; +- reg = <0x48050c00 0x100>; +- status = "disabled"; +- ti,hwmods = "dss_venc"; +- clocks = <&dss_tv_fck>; +- clock-names = "fck"; +- }; +- }; +- +- ssi: ssi-controller@48058000 { +- compatible = "ti,omap3-ssi"; +- ti,hwmods = "ssi"; +- +- status = "disabled"; +- +- reg = <0x48058000 0x1000>, +- <0x48059000 0x1000>; +- reg-names = "sys", +- "gdd"; +- +- interrupts = <71>; +- interrupt-names = "gdd_mpu"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- ssi_port1: ssi-port@4805a000 { +- compatible = "ti,omap3-ssi-port"; +- +- reg = <0x4805a000 0x800>, +- <0x4805a800 0x800>; +- reg-names = "tx", +- "rx"; +- +- interrupts = <67>, +- <68>; +- }; +- +- ssi_port2: ssi-port@4805b000 { +- compatible = "ti,omap3-ssi-port"; +- +- reg = <0x4805b000 0x800>, +- <0x4805b800 0x800>; +- reg-names = "tx", +- "rx"; +- +- interrupts = <69>, +- <70>; +- }; +- }; +- }; +-}; +- +-#include "omap3xxx-clocks.dtsi" +- +-/* Preferred always-on timer for clockevent. Some boards must use dmtimer12 */ +-&timer1_target { +- ti,no-reset-on-init; +- ti,no-idle; +- timer@0 { +- assigned-clocks = <&gpt1_fck>; +- assigned-clock-parents = <&omap_32k_fck>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3430-sdp.dts b/scripts/dtc/include-prefixes/arm/omap3430-sdp.dts +deleted file mode 100644 +index 7d530ae3483b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3430-sdp.dts ++++ /dev/null +@@ -1,195 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "omap34xx.dtsi" +- +-/ { +- model = "TI OMAP3430 SDP"; +- compatible = "ti,omap3430-sdp", "ti,omap3430", "ti,omap3"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256 MB */ +- }; +-}; +- +-&i2c1 { +- clock-frequency = <2600000>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = <7>; /* SYS_NIRQ cascaded to intc */ +- }; +-}; +- +-#include "twl4030.dtsi" +-#include "twl4030_omap3.dtsi" +- +-&mmc1 { +- vmmc-supply = <&vmmc1>; +- vqmmc-supply = <&vsim>; +- /* +- * S6-3 must be in ON position for 8 bit mode to function +- * Else, use 4 bit mode +- */ +- bus-width = <8>; +-}; +- +-&mmc2 { +- status = "disabled"; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-&gpmc { +- ranges = <0 0 0x10000000 0x08000000>, +- <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */ +- <2 0 0x20000000 0x1000000>; /* CS2: 16MB for OneNAND */ +- +- nor@0,0 { +- compatible = "cfi-flash"; +- linux,mtd-name= "intel,pf48f6000m0y1be"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0 0 0x08000000>; +- bank-width = <2>; +- +- gpmc,mux-add-data = <2>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <186>; +- gpmc,cs-wr-off-ns = <186>; +- gpmc,adv-on-ns = <12>; +- gpmc,adv-rd-off-ns = <48>; +- gpmc,adv-wr-off-ns = <48>; +- gpmc,oe-on-ns = <54>; +- gpmc,oe-off-ns = <168>; +- gpmc,we-on-ns = <54>; +- gpmc,we-off-ns = <168>; +- gpmc,rd-cycle-ns = <186>; +- gpmc,wr-cycle-ns = <186>; +- gpmc,access-ns = <114>; +- gpmc,page-burst-access-ns = <6>; +- gpmc,bus-turnaround-ns = <12>; +- gpmc,cycle2cycle-delay-ns = <18>; +- gpmc,wr-data-mux-bus-ns = <90>; +- gpmc,wr-access-ns = <186>; +- gpmc,cycle2cycle-samecsen; +- gpmc,cycle2cycle-diffcsen; +- +- partition@0 { +- label = "bootloader-nor"; +- reg = <0 0x40000>; +- }; +- partition@40000 { +- label = "params-nor"; +- reg = <0x40000 0x40000>; +- }; +- partition@80000 { +- label = "kernel-nor"; +- reg = <0x80000 0x200000>; +- }; +- partition@280000 { +- label = "filesystem-nor"; +- reg = <0x240000 0x7d80000>; +- }; +- }; +- +- nand@1,0 { +- compatible = "ti,omap2-nand"; +- reg = <1 0 4>; /* CS1, offset 0, IO size 4 */ +- interrupt-parent = <&gpmc>; +- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ +- <1 IRQ_TYPE_NONE>; /* termcount */ +- linux,mtd-name= "micron,mt29f1g08abb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ti,nand-ecc-opt = "sw"; +- nand-bus-width = <8>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <36>; +- gpmc,cs-wr-off-ns = <36>; +- gpmc,adv-on-ns = <6>; +- gpmc,adv-rd-off-ns = <24>; +- gpmc,adv-wr-off-ns = <36>; +- gpmc,oe-on-ns = <6>; +- gpmc,oe-off-ns = <48>; +- gpmc,we-on-ns = <6>; +- gpmc,we-off-ns = <30>; +- gpmc,rd-cycle-ns = <72>; +- gpmc,wr-cycle-ns = <72>; +- gpmc,access-ns = <54>; +- gpmc,wr-access-ns = <30>; +- +- partition@0 { +- label = "xloader-nand"; +- reg = <0 0x80000>; +- }; +- partition@80000 { +- label = "bootloader-nand"; +- reg = <0x80000 0x140000>; +- }; +- partition@1c0000 { +- label = "params-nand"; +- reg = <0x1c0000 0xc0000>; +- }; +- partition@280000 { +- label = "kernel-nand"; +- reg = <0x280000 0x500000>; +- }; +- partition@780000 { +- label = "filesystem-nand"; +- reg = <0x780000 0x7880000>; +- }; +- }; +- +- onenand@2,0 { +- linux,mtd-name= "samsung,kfm2g16q2m-deb8"; +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ti,omap2-onenand"; +- reg = <2 0 0x20000>; /* CS2, offset 0, IO size 4 */ +- +- gpmc,device-width = <2>; +- gpmc,mux-add-data = <2>; +- gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <84>; +- gpmc,cs-wr-off-ns = <72>; +- gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <18>; +- gpmc,adv-wr-off-ns = <18>; +- gpmc,oe-on-ns = <30>; +- gpmc,oe-off-ns = <84>; +- gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <42>; +- gpmc,rd-cycle-ns = <108>; +- gpmc,wr-cycle-ns = <96>; +- gpmc,access-ns = <78>; +- gpmc,wr-data-mux-bus-ns = <30>; +- +- partition@0 { +- label = "xloader-onenand"; +- reg = <0 0x80000>; +- }; +- partition@80000 { +- label = "bootloader-onenand"; +- reg = <0x80000 0x40000>; +- }; +- partition@c0000 { +- label = "params-onenand"; +- reg = <0xc0000 0x20000>; +- }; +- partition@e0000 { +- label = "kernel-onenand"; +- reg = <0xe0000 0x200000>; +- }; +- partition@2e0000 { +- label = "filesystem-onenand"; +- reg = <0x2e0000 0xfd20000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap3430es1-clocks.dtsi b/scripts/dtc/include-prefixes/arm/omap3430es1-clocks.dtsi +deleted file mode 100644 +index 2ec3628d3315..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3430es1-clocks.dtsi ++++ /dev/null +@@ -1,205 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for OMAP3430 ES1 clock data +- * +- * Copyright (C) 2013 Texas Instruments, Inc. +- */ +-&cm_clocks { +- gfx_l3_ck: gfx_l3_ck@b10 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&l3_ick>; +- reg = <0x0b10>; +- ti,bit-shift = <0>; +- }; +- +- gfx_l3_fck: gfx_l3_fck@b40 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&l3_ick>; +- ti,max-div = <7>; +- reg = <0x0b40>; +- ti,index-starts-at-one; +- }; +- +- gfx_l3_ick: gfx_l3_ick { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&gfx_l3_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- gfx_cg1_ck: gfx_cg1_ck@b00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&gfx_l3_fck>; +- reg = <0x0b00>; +- ti,bit-shift = <1>; +- }; +- +- gfx_cg2_ck: gfx_cg2_ck@b00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&gfx_l3_fck>; +- reg = <0x0b00>; +- ti,bit-shift = <2>; +- }; +- +- d2d_26m_fck: d2d_26m_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&sys_ck>; +- reg = <0x0a00>; +- ti,bit-shift = <3>; +- }; +- +- fshostusb_fck: fshostusb_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&core_48m_fck>; +- reg = <0x0a00>; +- ti,bit-shift = <5>; +- }; +- +- ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1@a00 { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&corex2_fck>; +- ti,bit-shift = <0>; +- reg = <0x0a00>; +- }; +- +- ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 { +- #clock-cells = <0>; +- compatible = "ti,composite-divider-clock"; +- clocks = <&corex2_fck>; +- ti,bit-shift = <8>; +- reg = <0x0a40>; +- ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; +- }; +- +- ssi_ssr_fck: ssi_ssr_fck_3430es1 { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>; +- }; +- +- ssi_sst_fck: ssi_sst_fck_3430es1 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&ssi_ssr_fck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- hsotgusb_ick_3430es1: hsotgusb_ick_3430es1@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-no-wait-interface-clock"; +- clocks = <&core_l3_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <4>; +- }; +- +- fac_ick: fac_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <8>; +- }; +- +- ssi_l4_ick: ssi_l4_ick { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&l4_ick>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- ssi_ick: ssi_ick_3430es1@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-no-wait-interface-clock"; +- clocks = <&ssi_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <0>; +- }; +- +- usb_l4_gate_ick: usb_l4_gate_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,composite-interface-clock"; +- clocks = <&l4_ick>; +- ti,bit-shift = <5>; +- reg = <0x0a10>; +- }; +- +- usb_l4_div_ick: usb_l4_div_ick@a40 { +- #clock-cells = <0>; +- compatible = "ti,composite-divider-clock"; +- clocks = <&l4_ick>; +- ti,bit-shift = <4>; +- ti,max-div = <1>; +- reg = <0x0a40>; +- ti,index-starts-at-one; +- }; +- +- usb_l4_ick: usb_l4_ick { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; +- }; +- +- dss1_alwon_fck: dss1_alwon_fck_3430es1@e00 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&dpll4_m4x2_ck>; +- ti,bit-shift = <0>; +- reg = <0x0e00>; +- ti,set-rate-parent; +- }; +- +- dss_ick: dss_ick_3430es1@e10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-no-wait-interface-clock"; +- clocks = <&l4_ick>; +- reg = <0x0e10>; +- ti,bit-shift = <0>; +- }; +-}; +- +-&cm_clockdomains { +- core_l3_clkdm: core_l3_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>; +- }; +- +- gfx_3430es1_clkdm: gfx_3430es1_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>; +- }; +- +- dss_clkdm: dss_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, +- <&dss1_alwon_fck>, <&dss_ick>; +- }; +- +- d2d_clkdm: d2d_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&d2d_26m_fck>; +- }; +- +- core_l4_clkdm: core_l4_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, +- <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, +- <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, +- <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, +- <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, +- <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, +- <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, +- <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, +- <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, +- <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap34xx-omap36xx-clocks.dtsi b/scripts/dtc/include-prefixes/arm/omap34xx-omap36xx-clocks.dtsi +deleted file mode 100644 +index 21079cdf2663..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap34xx-omap36xx-clocks.dtsi ++++ /dev/null +@@ -1,265 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for OMAP34XX/OMAP36XX clock data +- * +- * Copyright (C) 2013 Texas Instruments, Inc. +- */ +-&cm_clocks { +- security_l4_ick2: security_l4_ick2 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&l4_ick>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- aes1_ick: aes1_ick@a14 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&security_l4_ick2>; +- ti,bit-shift = <3>; +- reg = <0x0a14>; +- }; +- +- rng_ick: rng_ick@a14 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&security_l4_ick2>; +- reg = <0x0a14>; +- ti,bit-shift = <2>; +- }; +- +- sha11_ick: sha11_ick@a14 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&security_l4_ick2>; +- reg = <0x0a14>; +- ti,bit-shift = <1>; +- }; +- +- des1_ick: des1_ick@a14 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&security_l4_ick2>; +- reg = <0x0a14>; +- ti,bit-shift = <0>; +- }; +- +- cam_mclk: cam_mclk@f00 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&dpll4_m5x2_ck>; +- ti,bit-shift = <0>; +- reg = <0x0f00>; +- ti,set-rate-parent; +- }; +- +- cam_ick: cam_ick@f10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-no-wait-interface-clock"; +- clocks = <&l4_ick>; +- reg = <0x0f10>; +- ti,bit-shift = <0>; +- }; +- +- csi2_96m_fck: csi2_96m_fck@f00 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&core_96m_fck>; +- reg = <0x0f00>; +- ti,bit-shift = <1>; +- }; +- +- security_l3_ick: security_l3_ick { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&l3_ick>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- pka_ick: pka_ick@a14 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&security_l3_ick>; +- reg = <0x0a14>; +- ti,bit-shift = <4>; +- }; +- +- icr_ick: icr_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <29>; +- }; +- +- des2_ick: des2_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <26>; +- }; +- +- mspro_ick: mspro_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <23>; +- }; +- +- mailboxes_ick: mailboxes_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <7>; +- }; +- +- ssi_l4_ick: ssi_l4_ick { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&l4_ick>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- sr1_fck: sr1_fck@c00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&sys_ck>; +- reg = <0x0c00>; +- ti,bit-shift = <6>; +- }; +- +- sr2_fck: sr2_fck@c00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&sys_ck>; +- reg = <0x0c00>; +- ti,bit-shift = <7>; +- }; +- +- sr_l4_ick: sr_l4_ick { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&l4_ick>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dpll2_fck: dpll2_fck@40 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&core_ck>; +- ti,bit-shift = <19>; +- ti,max-div = <7>; +- reg = <0x0040>; +- ti,index-starts-at-one; +- }; +- +- dpll2_ck: dpll2_ck@4 { +- #clock-cells = <0>; +- compatible = "ti,omap3-dpll-clock"; +- clocks = <&sys_ck>, <&dpll2_fck>; +- reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>; +- ti,low-power-stop; +- ti,lock; +- ti,low-power-bypass; +- }; +- +- dpll2_m2_ck: dpll2_m2_ck@44 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll2_ck>; +- ti,max-div = <31>; +- reg = <0x0044>; +- ti,index-starts-at-one; +- }; +- +- iva2_ck: iva2_ck@0 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&dpll2_m2_ck>; +- reg = <0x0000>; +- ti,bit-shift = <0>; +- }; +- +- modem_fck: modem_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&sys_ck>; +- reg = <0x0a00>; +- ti,bit-shift = <31>; +- }; +- +- sad2d_ick: sad2d_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l3_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <3>; +- }; +- +- mad2d_ick: mad2d_ick@a18 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&l3_ick>; +- reg = <0x0a18>; +- ti,bit-shift = <3>; +- }; +- +- mspro_fck: mspro_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&core_96m_fck>; +- reg = <0x0a00>; +- ti,bit-shift = <23>; +- }; +-}; +- +-&cm_clockdomains { +- cam_clkdm: cam_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&cam_ick>, <&csi2_96m_fck>; +- }; +- +- iva2_clkdm: iva2_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&iva2_ck>; +- }; +- +- dpll2_clkdm: dpll2_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&dpll2_ck>; +- }; +- +- wkup_clkdm: wkup_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, +- <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, +- <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>; +- }; +- +- d2d_clkdm: d2d_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>; +- }; +- +- core_l4_clkdm: core_l4_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, +- <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, +- <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, +- <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, +- <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, +- <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, +- <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, +- <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, +- <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>, +- <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>, +- <&rng_ick>, <&mspro_fck>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap34xx.dtsi b/scripts/dtc/include-prefixes/arm/omap34xx.dtsi +deleted file mode 100644 +index 8b8451399784..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap34xx.dtsi ++++ /dev/null +@@ -1,197 +0,0 @@ +-/* +- * Device Tree Source for OMAP34xx/OMAP35xx SoC +- * +- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-#include +-#include +- +-#include "omap3.dtsi" +- +-/ { +- cpus { +- cpu: cpu@0 { +- /* OMAP343x/OMAP35xx variants OPP1-6 */ +- operating-points-v2 = <&cpu0_opp_table>; +- +- clock-latency = <300000>; /* From legacy driver */ +- #cooling-cells = <2>; +- }; +- }; +- +- cpu0_opp_table: opp-table { +- compatible = "operating-points-v2-ti-cpu"; +- syscon = <&scm_conf>; +- +- opp1-125000000 { +- opp-hz = /bits/ 64 <125000000>; +- /* +- * we currently only select the max voltage from table +- * Table 3-3 of the omap3530 Data sheet (SPRS507F). +- * Format is: +- */ +- opp-microvolt = <975000 975000 975000>; +- /* +- * first value is silicon revision bit mask +- * second one 720MHz Device Identification bit mask +- */ +- opp-supported-hw = <0xffffffff 3>; +- }; +- +- opp2-250000000 { +- opp-hz = /bits/ 64 <250000000>; +- opp-microvolt = <1075000 1075000 1075000>; +- opp-supported-hw = <0xffffffff 3>; +- opp-suspend; +- }; +- +- opp3-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <1200000 1200000 1200000>; +- opp-supported-hw = <0xffffffff 3>; +- }; +- +- opp4-550000000 { +- opp-hz = /bits/ 64 <550000000>; +- opp-microvolt = <1275000 1275000 1275000>; +- opp-supported-hw = <0xffffffff 3>; +- }; +- +- opp5-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <1350000 1350000 1350000>; +- opp-supported-hw = <0xffffffff 3>; +- }; +- +- opp6-720000000 { +- opp-hz = /bits/ 64 <720000000>; +- opp-microvolt = <1350000 1350000 1350000>; +- /* only high-speed grade omap3530 devices */ +- opp-supported-hw = <0xffffffff 2>; +- turbo-mode; +- }; +- }; +- +- ocp@68000000 { +- omap3_pmx_core2: pinmux@480025d8 { +- compatible = "ti,omap3-padconf", "pinctrl-single"; +- reg = <0x480025d8 0x24>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <1>; +- #interrupt-cells = <1>; +- interrupt-controller; +- pinctrl-single,register-width = <16>; +- pinctrl-single,function-mask = <0xff1f>; +- }; +- +- isp: isp@480bc000 { +- compatible = "ti,omap3-isp"; +- reg = <0x480bc000 0x12fc +- 0x480bd800 0x017c>; +- interrupts = <24>; +- iommus = <&mmu_isp>; +- syscon = <&scm_conf 0x6c>; +- ti,phy-type = ; +- #clock-cells = <1>; +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- bandgap: bandgap@48002524 { +- reg = <0x48002524 0x4>; +- compatible = "ti,omap34xx-bandgap"; +- #thermal-sensor-cells = <0>; +- }; +- +- target-module@480cb000 { +- compatible = "ti,sysc-omap3430-sr", "ti,sysc"; +- ti,hwmods = "smartreflex_core"; +- reg = <0x480cb024 0x4>; +- reg-names = "sysc"; +- ti,sysc-mask = ; +- clocks = <&sr2_fck>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x480cb000 0x001000>; +- +- smartreflex_core: smartreflex@0 { +- compatible = "ti,omap3-smartreflex-core"; +- reg = <0 0x400>; +- interrupts = <19>; +- }; +- }; +- +- target-module@480c9000 { +- compatible = "ti,sysc-omap3430-sr", "ti,sysc"; +- ti,hwmods = "smartreflex_mpu_iva"; +- reg = <0x480c9024 0x4>; +- reg-names = "sysc"; +- ti,sysc-mask = ; +- clocks = <&sr1_fck>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x480c9000 0x001000>; +- +- smartreflex_mpu_iva: smartreflex@480c9000 { +- compatible = "ti,omap3-smartreflex-mpu-iva"; +- reg = <0 0x400>; +- interrupts = <18>; +- }; +- }; +- +- /* +- * On omap34xx the OCP registers do not seem to be accessible +- * at all unlike on 36xx. Maybe SGX is permanently set to +- * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is +- * write-only at 0x50000e10. We detect SGX based on the SGX +- * revision register instead of the unreadable OCP revision +- * register. Also note that on early 34xx es1 revision there +- * are also different clocks, but we do not have any dts users +- * for it. +- */ +- sgx_module: target-module@50000000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x50000014 0x4>; +- reg-names = "rev"; +- clocks = <&sgx_fck>, <&sgx_ick>; +- clock-names = "fck", "ick"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x50000000 0x4000>; +- +- /* +- * Closed source PowerVR driver, no child device +- * binding or driver in mainline +- */ +- }; +- }; +- +- thermal_zones: thermal-zones { +- #include "omap3-cpu-thermal.dtsi" +- }; +-}; +- +-&ssi { +- status = "okay"; +- +- clocks = <&ssi_ssr_fck>, +- <&ssi_sst_fck>, +- <&ssi_ick>; +- clock-names = "ssi_ssr_fck", +- "ssi_sst_fck", +- "ssi_ick"; +-}; +- +-/include/ "omap34xx-omap36xx-clocks.dtsi" +-/include/ "omap36xx-omap3430es2plus-clocks.dtsi" +-/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/scripts/dtc/include-prefixes/arm/omap36xx-am35xx-omap3430es2plus-clocks.dtsi +deleted file mode 100644 +index 9974d5226971..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap36xx-am35xx-omap3430es2plus-clocks.dtsi ++++ /dev/null +@@ -1,239 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data +- * +- * Copyright (C) 2013 Texas Instruments, Inc. +- */ +-&prm_clocks { +- corex2_d3_fck: corex2_d3_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&corex2_fck>; +- clock-mult = <1>; +- clock-div = <3>; +- }; +- +- corex2_d5_fck: corex2_d5_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&corex2_fck>; +- clock-mult = <1>; +- clock-div = <5>; +- }; +-}; +-&cm_clocks { +- dpll5_ck: dpll5_ck@d04 { +- #clock-cells = <0>; +- compatible = "ti,omap3-dpll-clock"; +- clocks = <&sys_ck>, <&sys_ck>; +- reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>; +- ti,low-power-stop; +- ti,lock; +- }; +- +- dpll5_m2_ck: dpll5_m2_ck@d50 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll5_ck>; +- ti,max-div = <31>; +- reg = <0x0d50>; +- ti,index-starts-at-one; +- }; +- +- sgx_gate_fck: sgx_gate_fck@b00 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&core_ck>; +- ti,bit-shift = <1>; +- reg = <0x0b00>; +- }; +- +- core_d3_ck: core_d3_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&core_ck>; +- clock-mult = <1>; +- clock-div = <3>; +- }; +- +- core_d4_ck: core_d4_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&core_ck>; +- clock-mult = <1>; +- clock-div = <4>; +- }; +- +- core_d6_ck: core_d6_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&core_ck>; +- clock-mult = <1>; +- clock-div = <6>; +- }; +- +- omap_192m_alwon_fck: omap_192m_alwon_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll4_m2x2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- core_d2_ck: core_d2_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&core_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- sgx_mux_fck: sgx_mux_fck@b40 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>; +- reg = <0x0b40>; +- }; +- +- sgx_fck: sgx_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&sgx_gate_fck>, <&sgx_mux_fck>; +- }; +- +- sgx_ick: sgx_ick@b10 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&l3_ick>; +- reg = <0x0b10>; +- ti,bit-shift = <0>; +- }; +- +- cpefuse_fck: cpefuse_fck@a08 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&sys_ck>; +- reg = <0x0a08>; +- ti,bit-shift = <0>; +- }; +- +- ts_fck: ts_fck@a08 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&omap_32k_fck>; +- reg = <0x0a08>; +- ti,bit-shift = <1>; +- }; +- +- usbtll_fck: usbtll_fck@a08 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&dpll5_m2_ck>; +- reg = <0x0a08>; +- ti,bit-shift = <2>; +- }; +- +- usbtll_ick: usbtll_ick@a18 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a18>; +- ti,bit-shift = <2>; +- }; +- +- mmchs3_ick: mmchs3_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <30>; +- }; +- +- mmchs3_fck: mmchs3_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&core_96m_fck>; +- reg = <0x0a00>; +- ti,bit-shift = <30>; +- }; +- +- dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 { +- #clock-cells = <0>; +- compatible = "ti,dss-gate-clock"; +- clocks = <&dpll4_m4x2_ck>; +- ti,bit-shift = <0>; +- reg = <0x0e00>; +- ti,set-rate-parent; +- }; +- +- dss_ick: dss_ick_3430es2@e10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-dss-interface-clock"; +- clocks = <&l4_ick>; +- reg = <0x0e10>; +- ti,bit-shift = <0>; +- }; +- +- usbhost_120m_fck: usbhost_120m_fck@1400 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&dpll5_m2_ck>; +- reg = <0x1400>; +- ti,bit-shift = <1>; +- }; +- +- usbhost_48m_fck: usbhost_48m_fck@1400 { +- #clock-cells = <0>; +- compatible = "ti,dss-gate-clock"; +- clocks = <&omap_48m_fck>; +- reg = <0x1400>; +- ti,bit-shift = <0>; +- }; +- +- usbhost_ick: usbhost_ick@1410 { +- #clock-cells = <0>; +- compatible = "ti,omap3-dss-interface-clock"; +- clocks = <&l4_ick>; +- reg = <0x1410>; +- ti,bit-shift = <0>; +- }; +-}; +- +-&cm_clockdomains { +- dpll5_clkdm: dpll5_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&dpll5_ck>; +- }; +- +- sgx_clkdm: sgx_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&sgx_ick>; +- }; +- +- dss_clkdm: dss_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, +- <&dss1_alwon_fck>, <&dss_ick>; +- }; +- +- core_l4_clkdm: core_l4_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, +- <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, +- <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, +- <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, +- <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, +- <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, +- <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, +- <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, +- <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, +- <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, +- <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>; +- }; +- +- usbhost_clkdm: usbhost_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>, +- <&usbhost_ick>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap36xx-clocks.dtsi b/scripts/dtc/include-prefixes/arm/omap36xx-clocks.dtsi +deleted file mode 100644 +index 4e9cc9003594..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap36xx-clocks.dtsi ++++ /dev/null +@@ -1,111 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for OMAP36xx clock data +- * +- * Copyright (C) 2013 Texas Instruments, Inc. +- */ +-&cm_clocks { +- dpll4_ck: dpll4_ck@d00 { +- #clock-cells = <0>; +- compatible = "ti,omap3-dpll-per-j-type-clock"; +- clocks = <&sys_ck>, <&sys_ck>; +- reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; +- }; +- +- dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { +- #clock-cells = <0>; +- compatible = "ti,hsdiv-gate-clock"; +- clocks = <&dpll4_m5x2_mul_ck>; +- ti,bit-shift = <0x1e>; +- reg = <0x0d00>; +- ti,set-rate-parent; +- ti,set-bit-to-disable; +- }; +- +- dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { +- #clock-cells = <0>; +- compatible = "ti,hsdiv-gate-clock"; +- clocks = <&dpll4_m2x2_mul_ck>; +- ti,bit-shift = <0x1b>; +- reg = <0x0d00>; +- ti,set-bit-to-disable; +- }; +- +- dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { +- #clock-cells = <0>; +- compatible = "ti,hsdiv-gate-clock"; +- clocks = <&dpll3_m3x2_mul_ck>; +- ti,bit-shift = <0xc>; +- reg = <0x0d00>; +- ti,set-bit-to-disable; +- }; +- +- dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { +- #clock-cells = <0>; +- compatible = "ti,hsdiv-gate-clock"; +- clocks = <&dpll4_m3x2_mul_ck>; +- ti,bit-shift = <0x1c>; +- reg = <0x0d00>; +- ti,set-bit-to-disable; +- }; +- +- dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { +- #clock-cells = <0>; +- compatible = "ti,hsdiv-gate-clock"; +- clocks = <&dpll4_m6x2_mul_ck>; +- ti,bit-shift = <0x1f>; +- reg = <0x0d00>; +- ti,set-bit-to-disable; +- }; +- +- uart4_fck: uart4_fck@1000 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&per_48m_fck>; +- reg = <0x1000>; +- ti,bit-shift = <18>; +- }; +-}; +- +-&dpll4_m2x2_mul_ck { +- clock-mult = <1>; +-}; +- +-&dpll4_m3x2_mul_ck { +- clock-mult = <1>; +-}; +- +-&dpll4_m4x2_mul_ck { +- ti,clock-mult = <1>; +-}; +- +-&dpll4_m5x2_mul_ck { +- ti,clock-mult = <1>; +-}; +- +-&dpll4_m6x2_mul_ck { +- clock-mult = <1>; +-}; +- +-&cm_clockdomains { +- dpll4_clkdm: dpll4_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&dpll4_ck>; +- }; +- +- per_clkdm: per_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, +- <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, +- <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, +- <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, +- <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, +- <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, +- <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, +- <&mcbsp4_ick>, <&uart4_fck>; +- }; +-}; +- +-&dpll4_m4_ck { +- ti,max-div = <31>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap36xx-omap3430es2plus-clocks.dtsi b/scripts/dtc/include-prefixes/arm/omap36xx-omap3430es2plus-clocks.dtsi +deleted file mode 100644 +index 945537aee3ca..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap36xx-omap3430es2plus-clocks.dtsi ++++ /dev/null +@@ -1,195 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for OMAP34xx/OMAP36xx clock data +- * +- * Copyright (C) 2013 Texas Instruments, Inc. +- */ +-&cm_clocks { +- ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&corex2_fck>; +- ti,bit-shift = <0>; +- reg = <0x0a00>; +- }; +- +- ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 { +- #clock-cells = <0>; +- compatible = "ti,composite-divider-clock"; +- clocks = <&corex2_fck>; +- ti,bit-shift = <8>; +- reg = <0x0a40>; +- ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; +- }; +- +- ssi_ssr_fck: ssi_ssr_fck_3430es2 { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>; +- }; +- +- ssi_sst_fck: ssi_sst_fck_3430es2 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&ssi_ssr_fck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-hsotgusb-interface-clock"; +- clocks = <&core_l3_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <4>; +- }; +- +- ssi_l4_ick: ssi_l4_ick { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&l4_ick>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- ssi_ick: ssi_ick_3430es2@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-ssi-interface-clock"; +- clocks = <&ssi_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <0>; +- }; +- +- usim_gate_fck: usim_gate_fck@c00 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&omap_96m_fck>; +- ti,bit-shift = <9>; +- reg = <0x0c00>; +- }; +- +- sys_d2_ck: sys_d2_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- omap_96m_d2_fck: omap_96m_d2_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&omap_96m_fck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- omap_96m_d4_fck: omap_96m_d4_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&omap_96m_fck>; +- clock-mult = <1>; +- clock-div = <4>; +- }; +- +- omap_96m_d8_fck: omap_96m_d8_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&omap_96m_fck>; +- clock-mult = <1>; +- clock-div = <8>; +- }; +- +- omap_96m_d10_fck: omap_96m_d10_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&omap_96m_fck>; +- clock-mult = <1>; +- clock-div = <10>; +- }; +- +- dpll5_m2_d4_ck: dpll5_m2_d4_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll5_m2_ck>; +- clock-mult = <1>; +- clock-div = <4>; +- }; +- +- dpll5_m2_d8_ck: dpll5_m2_d8_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll5_m2_ck>; +- clock-mult = <1>; +- clock-div = <8>; +- }; +- +- dpll5_m2_d16_ck: dpll5_m2_d16_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll5_m2_ck>; +- clock-mult = <1>; +- clock-div = <16>; +- }; +- +- dpll5_m2_d20_ck: dpll5_m2_d20_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll5_m2_ck>; +- clock-mult = <1>; +- clock-div = <20>; +- }; +- +- usim_mux_fck: usim_mux_fck@c40 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; +- ti,bit-shift = <3>; +- reg = <0x0c40>; +- ti,index-starts-at-one; +- }; +- +- usim_fck: usim_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&usim_gate_fck>, <&usim_mux_fck>; +- }; +- +- usim_ick: usim_ick@c10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&wkup_l4_ick>; +- reg = <0x0c10>; +- ti,bit-shift = <9>; +- }; +-}; +- +-&cm_clockdomains { +- core_l3_clkdm: core_l3_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>; +- }; +- +- wkup_clkdm: wkup_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, +- <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, +- <&gpt1_ick>, <&usim_ick>; +- }; +- +- core_l4_clkdm: core_l4_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, +- <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>, +- <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, +- <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, +- <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, +- <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, +- <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, +- <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, +- <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, +- <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, +- <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, +- <&ssi_ick>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap36xx.dtsi b/scripts/dtc/include-prefixes/arm/omap36xx.dtsi +deleted file mode 100644 +index 22b33098b1a2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap36xx.dtsi ++++ /dev/null +@@ -1,249 +0,0 @@ +-/* +- * Device Tree Source for OMAP3 SoC +- * +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-#include +-#include +- +-#include "omap3.dtsi" +- +-/ { +- aliases { +- serial3 = &uart4; +- }; +- +- cpus { +- /* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */ +- cpu: cpu@0 { +- operating-points-v2 = <&cpu0_opp_table>; +- +- vbb-supply = <&abb_mpu_iva>; +- clock-latency = <300000>; /* From omap-cpufreq driver */ +- #cooling-cells = <2>; +- }; +- }; +- +- cpu0_opp_table: opp-table { +- compatible = "operating-points-v2-ti-cpu"; +- syscon = <&scm_conf>; +- +- opp50-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- /* +- * we currently only select the max voltage from table +- * Table 4-19 of the DM3730 Data sheet (SPRS685B) +- * Format is: cpu0-supply: +- * vbb-supply: +- */ +- opp-microvolt = <1012500 1012500 1012500>, +- <1012500 1012500 1012500>; +- /* +- * first value is silicon revision bit mask +- * second one is "speed binned" bit mask +- */ +- opp-supported-hw = <0xffffffff 3>; +- opp-suspend; +- }; +- +- opp100-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <1200000 1200000 1200000>, +- <1200000 1200000 1200000>; +- opp-supported-hw = <0xffffffff 3>; +- }; +- +- opp130-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <1325000 1325000 1325000>, +- <1325000 1325000 1325000>; +- opp-supported-hw = <0xffffffff 3>; +- }; +- +- opp1g-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <1375000 1375000 1375000>, +- <1375000 1375000 1375000>; +- /* only on am/dm37x with speed-binned bit set */ +- opp-supported-hw = <0xffffffff 2>; +- }; +- }; +- +- opp_supply_mpu_iva: opp_supply { +- compatible = "ti,omap-opp-supply"; +- ti,absolute-max-voltage-uv = <1375000>; +- }; +- +- ocp@68000000 { +- uart4: serial@49042000 { +- compatible = "ti,omap3-uart"; +- reg = <0x49042000 0x400>; +- interrupts = <80>; +- dmas = <&sdma 81 &sdma 82>; +- dma-names = "tx", "rx"; +- ti,hwmods = "uart4"; +- clock-frequency = <48000000>; +- }; +- +- abb_mpu_iva: regulator-abb-mpu { +- compatible = "ti,abb-v1"; +- regulator-name = "abb_mpu_iva"; +- #address-cells = <0>; +- #size-cells = <0>; +- reg = <0x483072f0 0x8>, <0x48306818 0x4>; +- reg-names = "base-address", "int-address"; +- ti,tranxdone-status-mask = <0x4000000>; +- clocks = <&sys_ck>; +- ti,settling-time = <30>; +- ti,clock-cycles = <8>; +- ti,abb_info = < +- /*uV ABB efuse rbb_m fbb_m vset_m*/ +- 1012500 0 0 0 0 0 +- 1200000 0 0 0 0 0 +- 1325000 0 0 0 0 0 +- 1375000 1 0 0 0 0 +- >; +- }; +- +- omap3_pmx_core2: pinmux@480025a0 { +- compatible = "ti,omap3-padconf", "pinctrl-single"; +- reg = <0x480025a0 0x5c>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <1>; +- #interrupt-cells = <1>; +- interrupt-controller; +- pinctrl-single,register-width = <16>; +- pinctrl-single,function-mask = <0xff1f>; +- }; +- +- isp: isp@480bc000 { +- compatible = "ti,omap3-isp"; +- reg = <0x480bc000 0x12fc +- 0x480bd800 0x0600>; +- interrupts = <24>; +- iommus = <&mmu_isp>; +- syscon = <&scm_conf 0x2f0>; +- ti,phy-type = ; +- #clock-cells = <1>; +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- bandgap: bandgap@48002524 { +- reg = <0x48002524 0x4>; +- compatible = "ti,omap36xx-bandgap"; +- #thermal-sensor-cells = <0>; +- }; +- +- target-module@480cb000 { +- compatible = "ti,sysc-omap3630-sr", "ti,sysc"; +- ti,hwmods = "smartreflex_core"; +- reg = <0x480cb038 0x4>; +- reg-names = "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- clocks = <&sr2_fck>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x480cb000 0x001000>; +- +- smartreflex_core: smartreflex@0 { +- compatible = "ti,omap3-smartreflex-core"; +- reg = <0 0x400>; +- interrupts = <19>; +- }; +- }; +- +- target-module@480c9000 { +- compatible = "ti,sysc-omap3630-sr", "ti,sysc"; +- ti,hwmods = "smartreflex_mpu_iva"; +- reg = <0x480c9038 0x4>; +- reg-names = "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- clocks = <&sr1_fck>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x480c9000 0x001000>; +- +- +- smartreflex_mpu_iva: smartreflex@480c9000 { +- compatible = "ti,omap3-smartreflex-mpu-iva"; +- reg = <0 0x400>; +- interrupts = <18>; +- }; +- }; +- +- /* +- * Note that the sysconfig register layout is a subset of the +- * "ti,sysc-omap4" type register with just sidle and midle bits +- * available while omap34xx has "ti,sysc-omap2" type sysconfig. +- */ +- sgx_module: target-module@50000000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x5000fe00 0x4>, +- <0x5000fe10 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- clocks = <&sgx_fck>, <&sgx_ick>; +- clock-names = "fck", "ick"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x50000000 0x2000000>; +- +- /* +- * Closed source PowerVR driver, no child device +- * binding or driver in mainline +- */ +- }; +- }; +- +- thermal_zones: thermal-zones { +- #include "omap3-cpu-thermal.dtsi" +- }; +-}; +- +-&sdma { +- compatible = "ti,omap3630-sdma", "ti,omap-sdma"; +-}; +- +-/* OMAP3630 needs dss_96m_fck for VENC */ +-&venc { +- clocks = <&dss_tv_fck>, <&dss_96m_fck>; +- clock-names = "fck", "tv_dac_clk"; +-}; +- +-&ssi { +- status = "okay"; +- +- clocks = <&ssi_ssr_fck>, +- <&ssi_sst_fck>, +- <&ssi_ick>; +- clock-names = "ssi_ssr_fck", +- "ssi_sst_fck", +- "ssi_ick"; +-}; +- +-/include/ "omap34xx-omap36xx-clocks.dtsi" +-/include/ "omap36xx-omap3430es2plus-clocks.dtsi" +-/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" +-/include/ "omap36xx-clocks.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/omap3xxx-clocks.dtsi b/scripts/dtc/include-prefixes/arm/omap3xxx-clocks.dtsi +deleted file mode 100644 +index 0656c32439d2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap3xxx-clocks.dtsi ++++ /dev/null +@@ -1,1662 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for OMAP3 clock data +- * +- * Copyright (C) 2013 Texas Instruments, Inc. +- */ +-&prm_clocks { +- virt_16_8m_ck: virt_16_8m_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <16800000>; +- }; +- +- osc_sys_ck: osc_sys_ck@d40 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>; +- reg = <0x0d40>; +- }; +- +- sys_ck: sys_ck@1270 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&osc_sys_ck>; +- ti,bit-shift = <6>; +- ti,max-div = <3>; +- reg = <0x1270>; +- ti,index-starts-at-one; +- }; +- +- sys_clkout1: sys_clkout1@d70 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&osc_sys_ck>; +- reg = <0x0d70>; +- ti,bit-shift = <7>; +- }; +- +- dpll3_x2_ck: dpll3_x2_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll3_ck>; +- clock-mult = <2>; +- clock-div = <1>; +- }; +- +- dpll3_m2x2_ck: dpll3_m2x2_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll3_m2_ck>; +- clock-mult = <2>; +- clock-div = <1>; +- }; +- +- dpll4_x2_ck: dpll4_x2_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll4_ck>; +- clock-mult = <2>; +- clock-div = <1>; +- }; +- +- corex2_fck: corex2_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll3_m2x2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- wkup_l4_ick: wkup_l4_ick { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +-}; +- +-&scm_clocks { +- mcbsp5_mux_fck: mcbsp5_mux_fck@68 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&core_96m_fck>, <&mcbsp_clks>; +- ti,bit-shift = <4>; +- reg = <0x68>; +- }; +- +- mcbsp5_fck: mcbsp5_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; +- }; +- +- mcbsp1_mux_fck: mcbsp1_mux_fck@4 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&core_96m_fck>, <&mcbsp_clks>; +- ti,bit-shift = <2>; +- reg = <0x04>; +- }; +- +- mcbsp1_fck: mcbsp1_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; +- }; +- +- mcbsp2_mux_fck: mcbsp2_mux_fck@4 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&per_96m_fck>, <&mcbsp_clks>; +- ti,bit-shift = <6>; +- reg = <0x04>; +- }; +- +- mcbsp2_fck: mcbsp2_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; +- }; +- +- mcbsp3_mux_fck: mcbsp3_mux_fck@68 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&per_96m_fck>, <&mcbsp_clks>; +- reg = <0x68>; +- }; +- +- mcbsp3_fck: mcbsp3_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; +- }; +- +- mcbsp4_mux_fck: mcbsp4_mux_fck@68 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&per_96m_fck>, <&mcbsp_clks>; +- ti,bit-shift = <2>; +- reg = <0x68>; +- }; +- +- mcbsp4_fck: mcbsp4_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; +- }; +-}; +-&cm_clocks { +- dummy_apb_pclk: dummy_apb_pclk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0x0>; +- }; +- +- omap_32k_fck: omap_32k_fck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- virt_12m_ck: virt_12m_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <12000000>; +- }; +- +- virt_13m_ck: virt_13m_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <13000000>; +- }; +- +- virt_19200000_ck: virt_19200000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <19200000>; +- }; +- +- virt_26000000_ck: virt_26000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- }; +- +- virt_38_4m_ck: virt_38_4m_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <38400000>; +- }; +- +- dpll4_ck: dpll4_ck@d00 { +- #clock-cells = <0>; +- compatible = "ti,omap3-dpll-per-clock"; +- clocks = <&sys_ck>, <&sys_ck>; +- reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; +- }; +- +- dpll4_m2_ck: dpll4_m2_ck@d48 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll4_ck>; +- ti,max-div = <63>; +- reg = <0x0d48>; +- ti,index-starts-at-one; +- }; +- +- dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll4_m2_ck>; +- clock-mult = <2>; +- clock-div = <1>; +- }; +- +- dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&dpll4_m2x2_mul_ck>; +- ti,bit-shift = <0x1b>; +- reg = <0x0d00>; +- ti,set-bit-to-disable; +- }; +- +- omap_96m_alwon_fck: omap_96m_alwon_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll4_m2x2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dpll3_ck: dpll3_ck@d00 { +- #clock-cells = <0>; +- compatible = "ti,omap3-dpll-core-clock"; +- clocks = <&sys_ck>, <&sys_ck>; +- reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>; +- }; +- +- dpll3_m3_ck: dpll3_m3_ck@1140 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll3_ck>; +- ti,bit-shift = <16>; +- ti,max-div = <31>; +- reg = <0x1140>; +- ti,index-starts-at-one; +- }; +- +- dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll3_m3_ck>; +- clock-mult = <2>; +- clock-div = <1>; +- }; +- +- dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&dpll3_m3x2_mul_ck>; +- ti,bit-shift = <0xc>; +- reg = <0x0d00>; +- ti,set-bit-to-disable; +- }; +- +- emu_core_alwon_ck: emu_core_alwon_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll3_m3x2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- sys_altclk: sys_altclk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0x0>; +- }; +- +- mcbsp_clks: mcbsp_clks { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0x0>; +- }; +- +- dpll3_m2_ck: dpll3_m2_ck@d40 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll3_ck>; +- ti,bit-shift = <27>; +- ti,max-div = <31>; +- reg = <0x0d40>; +- ti,index-starts-at-one; +- }; +- +- core_ck: core_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll3_m2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dpll1_fck: dpll1_fck@940 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&core_ck>; +- ti,bit-shift = <19>; +- ti,max-div = <7>; +- reg = <0x0940>; +- ti,index-starts-at-one; +- }; +- +- dpll1_ck: dpll1_ck@904 { +- #clock-cells = <0>; +- compatible = "ti,omap3-dpll-clock"; +- clocks = <&sys_ck>, <&dpll1_fck>; +- reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>; +- }; +- +- dpll1_x2_ck: dpll1_x2_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll1_ck>; +- clock-mult = <2>; +- clock-div = <1>; +- }; +- +- dpll1_x2m2_ck: dpll1_x2m2_ck@944 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll1_x2_ck>; +- ti,max-div = <31>; +- reg = <0x0944>; +- ti,index-starts-at-one; +- }; +- +- cm_96m_fck: cm_96m_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&omap_96m_alwon_fck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- omap_96m_fck: omap_96m_fck@d40 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&cm_96m_fck>, <&sys_ck>; +- ti,bit-shift = <6>; +- reg = <0x0d40>; +- }; +- +- dpll4_m3_ck: dpll4_m3_ck@e40 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll4_ck>; +- ti,bit-shift = <8>; +- ti,max-div = <32>; +- reg = <0x0e40>; +- ti,index-starts-at-one; +- }; +- +- dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll4_m3_ck>; +- clock-mult = <2>; +- clock-div = <1>; +- }; +- +- dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&dpll4_m3x2_mul_ck>; +- ti,bit-shift = <0x1c>; +- reg = <0x0d00>; +- ti,set-bit-to-disable; +- }; +- +- omap_54m_fck: omap_54m_fck@d40 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; +- ti,bit-shift = <5>; +- reg = <0x0d40>; +- }; +- +- cm_96m_d2_fck: cm_96m_d2_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&cm_96m_fck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- omap_48m_fck: omap_48m_fck@d40 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&cm_96m_d2_fck>, <&sys_altclk>; +- ti,bit-shift = <3>; +- reg = <0x0d40>; +- }; +- +- omap_12m_fck: omap_12m_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&omap_48m_fck>; +- clock-mult = <1>; +- clock-div = <4>; +- }; +- +- dpll4_m4_ck: dpll4_m4_ck@e40 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll4_ck>; +- ti,max-div = <16>; +- reg = <0x0e40>; +- ti,index-starts-at-one; +- }; +- +- dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { +- #clock-cells = <0>; +- compatible = "ti,fixed-factor-clock"; +- clocks = <&dpll4_m4_ck>; +- ti,clock-mult = <2>; +- ti,clock-div = <1>; +- ti,set-rate-parent; +- }; +- +- dpll4_m4x2_ck: dpll4_m4x2_ck@d00 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&dpll4_m4x2_mul_ck>; +- ti,bit-shift = <0x1d>; +- reg = <0x0d00>; +- ti,set-bit-to-disable; +- ti,set-rate-parent; +- }; +- +- dpll4_m5_ck: dpll4_m5_ck@f40 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll4_ck>; +- ti,max-div = <63>; +- reg = <0x0f40>; +- ti,index-starts-at-one; +- }; +- +- dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck { +- #clock-cells = <0>; +- compatible = "ti,fixed-factor-clock"; +- clocks = <&dpll4_m5_ck>; +- ti,clock-mult = <2>; +- ti,clock-div = <1>; +- ti,set-rate-parent; +- }; +- +- dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&dpll4_m5x2_mul_ck>; +- ti,bit-shift = <0x1e>; +- reg = <0x0d00>; +- ti,set-bit-to-disable; +- ti,set-rate-parent; +- }; +- +- dpll4_m6_ck: dpll4_m6_ck@1140 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll4_ck>; +- ti,bit-shift = <24>; +- ti,max-div = <63>; +- reg = <0x1140>; +- ti,index-starts-at-one; +- }; +- +- dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll4_m6_ck>; +- clock-mult = <2>; +- clock-div = <1>; +- }; +- +- dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&dpll4_m6x2_mul_ck>; +- ti,bit-shift = <0x1f>; +- reg = <0x0d00>; +- ti,set-bit-to-disable; +- }; +- +- emu_per_alwon_ck: emu_per_alwon_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll4_m6x2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- clkout2_src_gate_ck: clkout2_src_gate_ck@d70 { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&core_ck>; +- ti,bit-shift = <7>; +- reg = <0x0d70>; +- }; +- +- clkout2_src_mux_ck: clkout2_src_mux_ck@d70 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; +- reg = <0x0d70>; +- }; +- +- clkout2_src_ck: clkout2_src_ck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>; +- }; +- +- sys_clkout2: sys_clkout2@d70 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&clkout2_src_ck>; +- ti,bit-shift = <3>; +- ti,max-div = <64>; +- reg = <0x0d70>; +- ti,index-power-of-two; +- }; +- +- mpu_ck: mpu_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll1_x2m2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- arm_fck: arm_fck@924 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&mpu_ck>; +- reg = <0x0924>; +- ti,max-div = <2>; +- }; +- +- emu_mpu_alwon_ck: emu_mpu_alwon_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&mpu_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- l3_ick: l3_ick@a40 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&core_ck>; +- ti,max-div = <3>; +- reg = <0x0a40>; +- ti,index-starts-at-one; +- }; +- +- l4_ick: l4_ick@a40 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&l3_ick>; +- ti,bit-shift = <2>; +- ti,max-div = <3>; +- reg = <0x0a40>; +- ti,index-starts-at-one; +- }; +- +- rm_ick: rm_ick@c40 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&l4_ick>; +- ti,bit-shift = <1>; +- ti,max-div = <3>; +- reg = <0x0c40>; +- ti,index-starts-at-one; +- }; +- +- gpt10_gate_fck: gpt10_gate_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <11>; +- reg = <0x0a00>; +- }; +- +- gpt10_mux_fck: gpt10_mux_fck@a40 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&omap_32k_fck>, <&sys_ck>; +- ti,bit-shift = <6>; +- reg = <0x0a40>; +- }; +- +- gpt10_fck: gpt10_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; +- }; +- +- gpt11_gate_fck: gpt11_gate_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <12>; +- reg = <0x0a00>; +- }; +- +- gpt11_mux_fck: gpt11_mux_fck@a40 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&omap_32k_fck>, <&sys_ck>; +- ti,bit-shift = <7>; +- reg = <0x0a40>; +- }; +- +- gpt11_fck: gpt11_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>; +- }; +- +- core_96m_fck: core_96m_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&omap_96m_fck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- mmchs2_fck: mmchs2_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&core_96m_fck>; +- reg = <0x0a00>; +- ti,bit-shift = <25>; +- }; +- +- mmchs1_fck: mmchs1_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&core_96m_fck>; +- reg = <0x0a00>; +- ti,bit-shift = <24>; +- }; +- +- i2c3_fck: i2c3_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&core_96m_fck>; +- reg = <0x0a00>; +- ti,bit-shift = <17>; +- }; +- +- i2c2_fck: i2c2_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&core_96m_fck>; +- reg = <0x0a00>; +- ti,bit-shift = <16>; +- }; +- +- i2c1_fck: i2c1_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&core_96m_fck>; +- reg = <0x0a00>; +- ti,bit-shift = <15>; +- }; +- +- mcbsp5_gate_fck: mcbsp5_gate_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&mcbsp_clks>; +- ti,bit-shift = <10>; +- reg = <0x0a00>; +- }; +- +- mcbsp1_gate_fck: mcbsp1_gate_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&mcbsp_clks>; +- ti,bit-shift = <9>; +- reg = <0x0a00>; +- }; +- +- core_48m_fck: core_48m_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&omap_48m_fck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- mcspi4_fck: mcspi4_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&core_48m_fck>; +- reg = <0x0a00>; +- ti,bit-shift = <21>; +- }; +- +- mcspi3_fck: mcspi3_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&core_48m_fck>; +- reg = <0x0a00>; +- ti,bit-shift = <20>; +- }; +- +- mcspi2_fck: mcspi2_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&core_48m_fck>; +- reg = <0x0a00>; +- ti,bit-shift = <19>; +- }; +- +- mcspi1_fck: mcspi1_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&core_48m_fck>; +- reg = <0x0a00>; +- ti,bit-shift = <18>; +- }; +- +- uart2_fck: uart2_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&core_48m_fck>; +- reg = <0x0a00>; +- ti,bit-shift = <14>; +- }; +- +- uart1_fck: uart1_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&core_48m_fck>; +- reg = <0x0a00>; +- ti,bit-shift = <13>; +- }; +- +- core_12m_fck: core_12m_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&omap_12m_fck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- hdq_fck: hdq_fck@a00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&core_12m_fck>; +- reg = <0x0a00>; +- ti,bit-shift = <22>; +- }; +- +- core_l3_ick: core_l3_ick { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&l3_ick>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- sdrc_ick: sdrc_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&core_l3_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <1>; +- }; +- +- gpmc_fck: gpmc_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&core_l3_ick>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- core_l4_ick: core_l4_ick { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&l4_ick>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- mmchs2_ick: mmchs2_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <25>; +- }; +- +- mmchs1_ick: mmchs1_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <24>; +- }; +- +- hdq_ick: hdq_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <22>; +- }; +- +- mcspi4_ick: mcspi4_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <21>; +- }; +- +- mcspi3_ick: mcspi3_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <20>; +- }; +- +- mcspi2_ick: mcspi2_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <19>; +- }; +- +- mcspi1_ick: mcspi1_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <18>; +- }; +- +- i2c3_ick: i2c3_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <17>; +- }; +- +- i2c2_ick: i2c2_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <16>; +- }; +- +- i2c1_ick: i2c1_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <15>; +- }; +- +- uart2_ick: uart2_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <14>; +- }; +- +- uart1_ick: uart1_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <13>; +- }; +- +- gpt11_ick: gpt11_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <12>; +- }; +- +- gpt10_ick: gpt10_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <11>; +- }; +- +- mcbsp5_ick: mcbsp5_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <10>; +- }; +- +- mcbsp1_ick: mcbsp1_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <9>; +- }; +- +- omapctrl_ick: omapctrl_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <6>; +- }; +- +- dss_tv_fck: dss_tv_fck@e00 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&omap_54m_fck>; +- reg = <0x0e00>; +- ti,bit-shift = <2>; +- }; +- +- dss_96m_fck: dss_96m_fck@e00 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&omap_96m_fck>; +- reg = <0x0e00>; +- ti,bit-shift = <2>; +- }; +- +- dss2_alwon_fck: dss2_alwon_fck@e00 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&sys_ck>; +- reg = <0x0e00>; +- ti,bit-shift = <1>; +- }; +- +- dummy_ck: dummy_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- gpt1_gate_fck: gpt1_gate_fck@c00 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <0>; +- reg = <0x0c00>; +- }; +- +- gpt1_mux_fck: gpt1_mux_fck@c40 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&omap_32k_fck>, <&sys_ck>; +- reg = <0x0c40>; +- }; +- +- gpt1_fck: gpt1_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; +- }; +- +- aes2_ick: aes2_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- ti,bit-shift = <28>; +- reg = <0x0a10>; +- }; +- +- wkup_32k_fck: wkup_32k_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&omap_32k_fck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- gpio1_dbck: gpio1_dbck@c00 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&wkup_32k_fck>; +- reg = <0x0c00>; +- ti,bit-shift = <3>; +- }; +- +- sha12_ick: sha12_ick@a10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&core_l4_ick>; +- reg = <0x0a10>; +- ti,bit-shift = <27>; +- }; +- +- wdt2_fck: wdt2_fck@c00 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&wkup_32k_fck>; +- reg = <0x0c00>; +- ti,bit-shift = <5>; +- }; +- +- wdt2_ick: wdt2_ick@c10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&wkup_l4_ick>; +- reg = <0x0c10>; +- ti,bit-shift = <5>; +- }; +- +- wdt1_ick: wdt1_ick@c10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&wkup_l4_ick>; +- reg = <0x0c10>; +- ti,bit-shift = <4>; +- }; +- +- gpio1_ick: gpio1_ick@c10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&wkup_l4_ick>; +- reg = <0x0c10>; +- ti,bit-shift = <3>; +- }; +- +- omap_32ksync_ick: omap_32ksync_ick@c10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&wkup_l4_ick>; +- reg = <0x0c10>; +- ti,bit-shift = <2>; +- }; +- +- gpt12_ick: gpt12_ick@c10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&wkup_l4_ick>; +- reg = <0x0c10>; +- ti,bit-shift = <1>; +- }; +- +- gpt1_ick: gpt1_ick@c10 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&wkup_l4_ick>; +- reg = <0x0c10>; +- ti,bit-shift = <0>; +- }; +- +- per_96m_fck: per_96m_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&omap_96m_alwon_fck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- per_48m_fck: per_48m_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&omap_48m_fck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- uart3_fck: uart3_fck@1000 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&per_48m_fck>; +- reg = <0x1000>; +- ti,bit-shift = <11>; +- }; +- +- gpt2_gate_fck: gpt2_gate_fck@1000 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <3>; +- reg = <0x1000>; +- }; +- +- gpt2_mux_fck: gpt2_mux_fck@1040 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&omap_32k_fck>, <&sys_ck>; +- reg = <0x1040>; +- }; +- +- gpt2_fck: gpt2_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; +- }; +- +- gpt3_gate_fck: gpt3_gate_fck@1000 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <4>; +- reg = <0x1000>; +- }; +- +- gpt3_mux_fck: gpt3_mux_fck@1040 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&omap_32k_fck>, <&sys_ck>; +- ti,bit-shift = <1>; +- reg = <0x1040>; +- }; +- +- gpt3_fck: gpt3_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; +- }; +- +- gpt4_gate_fck: gpt4_gate_fck@1000 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <5>; +- reg = <0x1000>; +- }; +- +- gpt4_mux_fck: gpt4_mux_fck@1040 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&omap_32k_fck>, <&sys_ck>; +- ti,bit-shift = <2>; +- reg = <0x1040>; +- }; +- +- gpt4_fck: gpt4_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; +- }; +- +- gpt5_gate_fck: gpt5_gate_fck@1000 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <6>; +- reg = <0x1000>; +- }; +- +- gpt5_mux_fck: gpt5_mux_fck@1040 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&omap_32k_fck>, <&sys_ck>; +- ti,bit-shift = <3>; +- reg = <0x1040>; +- }; +- +- gpt5_fck: gpt5_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; +- }; +- +- gpt6_gate_fck: gpt6_gate_fck@1000 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <7>; +- reg = <0x1000>; +- }; +- +- gpt6_mux_fck: gpt6_mux_fck@1040 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&omap_32k_fck>, <&sys_ck>; +- ti,bit-shift = <4>; +- reg = <0x1040>; +- }; +- +- gpt6_fck: gpt6_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; +- }; +- +- gpt7_gate_fck: gpt7_gate_fck@1000 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <8>; +- reg = <0x1000>; +- }; +- +- gpt7_mux_fck: gpt7_mux_fck@1040 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&omap_32k_fck>, <&sys_ck>; +- ti,bit-shift = <5>; +- reg = <0x1040>; +- }; +- +- gpt7_fck: gpt7_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; +- }; +- +- gpt8_gate_fck: gpt8_gate_fck@1000 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <9>; +- reg = <0x1000>; +- }; +- +- gpt8_mux_fck: gpt8_mux_fck@1040 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&omap_32k_fck>, <&sys_ck>; +- ti,bit-shift = <6>; +- reg = <0x1040>; +- }; +- +- gpt8_fck: gpt8_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; +- }; +- +- gpt9_gate_fck: gpt9_gate_fck@1000 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&sys_ck>; +- ti,bit-shift = <10>; +- reg = <0x1000>; +- }; +- +- gpt9_mux_fck: gpt9_mux_fck@1040 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&omap_32k_fck>, <&sys_ck>; +- ti,bit-shift = <7>; +- reg = <0x1040>; +- }; +- +- gpt9_fck: gpt9_fck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>; +- }; +- +- per_32k_alwon_fck: per_32k_alwon_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&omap_32k_fck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- gpio6_dbck: gpio6_dbck@1000 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&per_32k_alwon_fck>; +- reg = <0x1000>; +- ti,bit-shift = <17>; +- }; +- +- gpio5_dbck: gpio5_dbck@1000 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&per_32k_alwon_fck>; +- reg = <0x1000>; +- ti,bit-shift = <16>; +- }; +- +- gpio4_dbck: gpio4_dbck@1000 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&per_32k_alwon_fck>; +- reg = <0x1000>; +- ti,bit-shift = <15>; +- }; +- +- gpio3_dbck: gpio3_dbck@1000 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&per_32k_alwon_fck>; +- reg = <0x1000>; +- ti,bit-shift = <14>; +- }; +- +- gpio2_dbck: gpio2_dbck@1000 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&per_32k_alwon_fck>; +- reg = <0x1000>; +- ti,bit-shift = <13>; +- }; +- +- wdt3_fck: wdt3_fck@1000 { +- #clock-cells = <0>; +- compatible = "ti,wait-gate-clock"; +- clocks = <&per_32k_alwon_fck>; +- reg = <0x1000>; +- ti,bit-shift = <12>; +- }; +- +- per_l4_ick: per_l4_ick { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&l4_ick>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- gpio6_ick: gpio6_ick@1010 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&per_l4_ick>; +- reg = <0x1010>; +- ti,bit-shift = <17>; +- }; +- +- gpio5_ick: gpio5_ick@1010 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&per_l4_ick>; +- reg = <0x1010>; +- ti,bit-shift = <16>; +- }; +- +- gpio4_ick: gpio4_ick@1010 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&per_l4_ick>; +- reg = <0x1010>; +- ti,bit-shift = <15>; +- }; +- +- gpio3_ick: gpio3_ick@1010 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&per_l4_ick>; +- reg = <0x1010>; +- ti,bit-shift = <14>; +- }; +- +- gpio2_ick: gpio2_ick@1010 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&per_l4_ick>; +- reg = <0x1010>; +- ti,bit-shift = <13>; +- }; +- +- wdt3_ick: wdt3_ick@1010 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&per_l4_ick>; +- reg = <0x1010>; +- ti,bit-shift = <12>; +- }; +- +- uart3_ick: uart3_ick@1010 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&per_l4_ick>; +- reg = <0x1010>; +- ti,bit-shift = <11>; +- }; +- +- uart4_ick: uart4_ick@1010 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&per_l4_ick>; +- reg = <0x1010>; +- ti,bit-shift = <18>; +- }; +- +- gpt9_ick: gpt9_ick@1010 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&per_l4_ick>; +- reg = <0x1010>; +- ti,bit-shift = <10>; +- }; +- +- gpt8_ick: gpt8_ick@1010 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&per_l4_ick>; +- reg = <0x1010>; +- ti,bit-shift = <9>; +- }; +- +- gpt7_ick: gpt7_ick@1010 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&per_l4_ick>; +- reg = <0x1010>; +- ti,bit-shift = <8>; +- }; +- +- gpt6_ick: gpt6_ick@1010 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&per_l4_ick>; +- reg = <0x1010>; +- ti,bit-shift = <7>; +- }; +- +- gpt5_ick: gpt5_ick@1010 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&per_l4_ick>; +- reg = <0x1010>; +- ti,bit-shift = <6>; +- }; +- +- gpt4_ick: gpt4_ick@1010 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&per_l4_ick>; +- reg = <0x1010>; +- ti,bit-shift = <5>; +- }; +- +- gpt3_ick: gpt3_ick@1010 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&per_l4_ick>; +- reg = <0x1010>; +- ti,bit-shift = <4>; +- }; +- +- gpt2_ick: gpt2_ick@1010 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&per_l4_ick>; +- reg = <0x1010>; +- ti,bit-shift = <3>; +- }; +- +- mcbsp2_ick: mcbsp2_ick@1010 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&per_l4_ick>; +- reg = <0x1010>; +- ti,bit-shift = <0>; +- }; +- +- mcbsp3_ick: mcbsp3_ick@1010 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&per_l4_ick>; +- reg = <0x1010>; +- ti,bit-shift = <1>; +- }; +- +- mcbsp4_ick: mcbsp4_ick@1010 { +- #clock-cells = <0>; +- compatible = "ti,omap3-interface-clock"; +- clocks = <&per_l4_ick>; +- reg = <0x1010>; +- ti,bit-shift = <2>; +- }; +- +- mcbsp2_gate_fck: mcbsp2_gate_fck@1000 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&mcbsp_clks>; +- ti,bit-shift = <0>; +- reg = <0x1000>; +- }; +- +- mcbsp3_gate_fck: mcbsp3_gate_fck@1000 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&mcbsp_clks>; +- ti,bit-shift = <1>; +- reg = <0x1000>; +- }; +- +- mcbsp4_gate_fck: mcbsp4_gate_fck@1000 { +- #clock-cells = <0>; +- compatible = "ti,composite-gate-clock"; +- clocks = <&mcbsp_clks>; +- ti,bit-shift = <2>; +- reg = <0x1000>; +- }; +- +- emu_src_mux_ck: emu_src_mux_ck@1140 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; +- reg = <0x1140>; +- }; +- +- emu_src_ck: emu_src_ck { +- #clock-cells = <0>; +- compatible = "ti,clkdm-gate-clock"; +- clocks = <&emu_src_mux_ck>; +- }; +- +- pclk_fck: pclk_fck@1140 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&emu_src_ck>; +- ti,bit-shift = <8>; +- ti,max-div = <7>; +- reg = <0x1140>; +- ti,index-starts-at-one; +- }; +- +- pclkx2_fck: pclkx2_fck@1140 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&emu_src_ck>; +- ti,bit-shift = <6>; +- ti,max-div = <3>; +- reg = <0x1140>; +- ti,index-starts-at-one; +- }; +- +- atclk_fck: atclk_fck@1140 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&emu_src_ck>; +- ti,bit-shift = <4>; +- ti,max-div = <3>; +- reg = <0x1140>; +- ti,index-starts-at-one; +- }; +- +- traceclk_src_fck: traceclk_src_fck@1140 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; +- ti,bit-shift = <2>; +- reg = <0x1140>; +- }; +- +- traceclk_fck: traceclk_fck@1140 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&traceclk_src_fck>; +- ti,bit-shift = <11>; +- ti,max-div = <7>; +- reg = <0x1140>; +- ti,index-starts-at-one; +- }; +- +- secure_32k_fck: secure_32k_fck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- gpt12_fck: gpt12_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&secure_32k_fck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- wdt1_fck: wdt1_fck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&secure_32k_fck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +-}; +- +-&cm_clockdomains { +- core_l3_clkdm: core_l3_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&sdrc_ick>; +- }; +- +- dpll3_clkdm: dpll3_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&dpll3_ck>; +- }; +- +- dpll1_clkdm: dpll1_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&dpll1_ck>; +- }; +- +- per_clkdm: per_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, +- <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, +- <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, +- <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, +- <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, +- <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, +- <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, +- <&mcbsp4_ick>; +- }; +- +- emu_clkdm: emu_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&emu_src_ck>; +- }; +- +- dpll4_clkdm: dpll4_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&dpll4_ck>; +- }; +- +- wkup_clkdm: wkup_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, +- <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, +- <&gpt1_ick>; +- }; +- +- dss_clkdm: dss_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>; +- }; +- +- core_l4_clkdm: core_l4_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, +- <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, +- <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, +- <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, +- <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, +- <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, +- <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, +- <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, +- <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap4-cpu-thermal.dtsi b/scripts/dtc/include-prefixes/arm/omap4-cpu-thermal.dtsi +deleted file mode 100644 +index 03d054b2bf9a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-cpu-thermal.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * Device Tree Source for OMAP4/5 SoC CPU thermal +- * +- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ +- * Contact: Eduardo Valentin +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-#include +- +-cpu_thermal: cpu_thermal { +- polling-delay-passive = <250>; /* milliseconds */ +- polling-delay = <1000>; /* milliseconds */ +- +- /* sensor ID */ +- thermal-sensors = <&bandgap 0>; +- +- cpu_trips: trips { +- cpu_alert0: cpu_alert { +- temperature = <100000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu_crit: cpu_crit { +- temperature = <125000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- +- cpu_cooling_maps: cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- cooling-device = +- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap4-droid-bionic-xt875.dts b/scripts/dtc/include-prefixes/arm/omap4-droid-bionic-xt875.dts +deleted file mode 100644 +index ccf03a743678..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-droid-bionic-xt875.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/dts-v1/; +- +-#include "motorola-mapphone-common.dtsi" +- +-/ { +- model = "Motorola Droid Bionic XT875"; +- compatible = "motorola,droid-bionic", "ti,omap4430", "ti,omap4"; +-}; +- +-&keypad { +- keypad,num-rows = <8>; +- keypad,num-columns = <8>; +- linux,keymap = < +- MATRIX_KEY(5, 0, KEY_VOLUMEUP) +- MATRIX_KEY(3, 0, KEY_VOLUMEDOWN) +- >; +-}; +- +-&i2c1 { +- led-controller@38 { +- compatible = "ti,lm3532"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x38>; +- +- enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; +- +- ramp-up-us = <1024>; +- ramp-down-us = <8193>; +- +- backlight_led: led@0 { +- reg = <0>; +- led-sources = <2>; +- ti,led-mode = <0>; +- label = ":backlight"; +- }; +- }; +-}; +- +-&i2c4 { +- kxtf9: accelerometer@f { +- compatible = "kionix,kxtf9"; +- reg = <0x0f>; +- +- vdd-supply = <&vhvio>; +- +- interrupt-parent = <&gpio2>; +- interrupts = <2 IRQ_TYPE_EDGE_RISING>; +- +- rotation-matrix = "0", "-1", "0", +- "1", "0", "0", +- "0", "0", "1"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap4-droid4-xt894.dts b/scripts/dtc/include-prefixes/arm/omap4-droid4-xt894.dts +deleted file mode 100644 +index e833c21f1c01..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-droid4-xt894.dts ++++ /dev/null +@@ -1,157 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/dts-v1/; +- +-#include "motorola-mapphone-common.dtsi" +- +-/ { +- gpio_keys { +- compatible = "gpio-keys"; +- +- volume_down { +- label = "Volume Down"; +- gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */ +- linux,code = ; +- linux,can-disable; +- /* Value above 7.95ms for no GPIO hardware debounce */ +- debounce-interval = <10>; +- }; +- +- /* +- * We use pad 0x4a100116 abe_dmic_din3.gpio_122 as the irq instead +- * of the gpio interrupt to avoid lost events in deeper idle states. +- */ +- slider { +- label = "Keypad Slide"; +- interrupts-extended = <&omap4_pmx_core 0xd6>; +- gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio122 */ +- linux,input-type = ; +- linux,code = ; +- linux,can-disable; +- /* Value above 7.95ms for no GPIO hardware debounce */ +- debounce-interval = <10>; +- }; +- }; +-}; +- +-/ { +- model = "Motorola Droid 4 XT894"; +- compatible = "motorola,droid4", "ti,omap4430", "ti,omap4"; +-}; +- +-&keypad { +- keypad,num-rows = <8>; +- keypad,num-columns = <8>; +- linux,keymap = < +- +- /* Row 1 */ +- MATRIX_KEY(0, 2, KEY_1) +- MATRIX_KEY(0, 6, KEY_2) +- MATRIX_KEY(2, 3, KEY_3) +- MATRIX_KEY(0, 7, KEY_4) +- MATRIX_KEY(0, 4, KEY_5) +- MATRIX_KEY(5, 5, KEY_6) +- MATRIX_KEY(0, 1, KEY_7) +- MATRIX_KEY(0, 5, KEY_8) +- MATRIX_KEY(0, 0, KEY_9) +- MATRIX_KEY(1, 6, KEY_0) +- +- /* Row 2 */ +- MATRIX_KEY(3, 4, KEY_APOSTROPHE) +- MATRIX_KEY(7, 6, KEY_Q) +- MATRIX_KEY(7, 7, KEY_W) +- MATRIX_KEY(7, 2, KEY_E) +- MATRIX_KEY(1, 0, KEY_R) +- MATRIX_KEY(4, 4, KEY_T) +- MATRIX_KEY(1, 2, KEY_Y) +- MATRIX_KEY(6, 7, KEY_U) +- MATRIX_KEY(2, 2, KEY_I) +- MATRIX_KEY(5, 6, KEY_O) +- MATRIX_KEY(3, 7, KEY_P) +- MATRIX_KEY(6, 5, KEY_BACKSPACE) +- +- /* Row 3 */ +- MATRIX_KEY(5, 4, KEY_TAB) +- MATRIX_KEY(5, 7, KEY_A) +- MATRIX_KEY(2, 7, KEY_S) +- MATRIX_KEY(7, 0, KEY_D) +- MATRIX_KEY(2, 6, KEY_F) +- MATRIX_KEY(6, 2, KEY_G) +- MATRIX_KEY(6, 6, KEY_H) +- MATRIX_KEY(1, 4, KEY_J) +- MATRIX_KEY(3, 1, KEY_K) +- MATRIX_KEY(2, 1, KEY_L) +- MATRIX_KEY(4, 6, KEY_ENTER) +- +- /* Row 4 */ +- MATRIX_KEY(3, 6, KEY_LEFTSHIFT) /* KEY_CAPSLOCK */ +- MATRIX_KEY(6, 1, KEY_Z) +- MATRIX_KEY(7, 4, KEY_X) +- MATRIX_KEY(5, 1, KEY_C) +- MATRIX_KEY(1, 7, KEY_V) +- MATRIX_KEY(2, 4, KEY_B) +- MATRIX_KEY(4, 1, KEY_N) +- MATRIX_KEY(1, 1, KEY_M) +- MATRIX_KEY(3, 5, KEY_COMMA) +- MATRIX_KEY(5, 2, KEY_DOT) +- MATRIX_KEY(6, 3, KEY_UP) +- MATRIX_KEY(7, 3, KEY_OK) +- +- /* Row 5 */ +- MATRIX_KEY(2, 5, KEY_LEFTCTRL) /* KEY_LEFTSHIFT */ +- MATRIX_KEY(4, 5, KEY_LEFTALT) /* SYM */ +- MATRIX_KEY(6, 0, KEY_MINUS) +- MATRIX_KEY(4, 7, KEY_EQUAL) +- MATRIX_KEY(1, 5, KEY_SPACE) +- MATRIX_KEY(3, 2, KEY_SLASH) +- MATRIX_KEY(4, 3, KEY_LEFT) +- MATRIX_KEY(5, 3, KEY_DOWN) +- MATRIX_KEY(3, 3, KEY_RIGHT) +- +- /* Side buttons, KEY_VOLUMEDOWN and KEY_PWER are on CPCAP? */ +- MATRIX_KEY(5, 0, KEY_VOLUMEUP) +- >; +-}; +- +-&i2c1 { +- led-controller@38 { +- compatible = "ti,lm3532"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x38>; +- +- enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; +- +- ramp-up-us = <1024>; +- ramp-down-us = <8193>; +- +- backlight_led: led@0 { +- reg = <0>; +- led-sources = <2>; +- ti,led-mode = <0>; +- label = ":backlight"; +- }; +- +- led@1 { +- reg = <1>; +- led-sources = <1>; +- ti,led-mode = <0>; +- label = ":kbd_backlight"; +- }; +- }; +-}; +- +-&i2c4 { +- lis3dh: accelerometer@18 { +- compatible = "st,lis3dh-accel"; +- reg = <0x18>; +- +- vdd-supply = <&vhvio>; +- +- interrupt-parent = <&gpio2>; +- interrupts = <2 IRQ_TYPE_EDGE_BOTH>; /* gpio34 */ +- +- rotation-matrix = "0", "-1", "0", +- "1", "0", "0", +- "0", "0", "1"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap4-duovero-parlor.dts b/scripts/dtc/include-prefixes/arm/omap4-duovero-parlor.dts +deleted file mode 100644 +index b294c22177cb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-duovero-parlor.dts ++++ /dev/null +@@ -1,194 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +-/dts-v1/; +- +-#include "omap4-duovero.dtsi" +- +-#include +- +-/ { +- model = "OMAP4430 Gumstix Duovero on Parlor"; +- compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; +- +- aliases { +- display0 = &hdmi0; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led0 { +- label = "duovero:blue:led0"; +- gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio_122 */ +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- button0 { +- label = "button0"; +- linux,code = ; +- gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */ +- /* Value above 7.95ms for no GPIO hardware debounce */ +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- hdmi0: connector { +- compatible = "hdmi-connector"; +- label = "hdmi"; +- +- type = "d"; +- +- hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio_63 */ +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_out>; +- }; +- }; +- }; +-}; +- +-&omap4_pmx_core { +- pinctrl-0 = < +- &led_pins +- &button_pins +- &smsc_pins +- >; +- +- led_pins: pinmux_led_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ +- >; +- }; +- +- button_pins: pinmux_button_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* abe_dmic_din2.gpio_121 */ +- >; +- }; +- +- i2c2_pins: pinmux_i2c2_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ +- OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ +- >; +- }; +- +- i2c3_pins: pinmux_i2c3_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ +- OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ +- >; +- }; +- +- smsc_pins: pinmux_smsc_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x068, PIN_INPUT | MUX_MODE3) /* gpmc_a20.gpio_44: IRQ */ +- OMAP4_IOPAD(0x06a, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a21.gpio_45: nReset */ +- OMAP4_IOPAD(0x070, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48: amdix enabled */ +- >; +- }; +- +- dss_hdmi_pins: pinmux_dss_hdmi_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3) /* hdmi_hpd.gpio_63 */ +- OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ +- OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */ +- OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */ +- >; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- +- clock-frequency = <400000>; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- +- clock-frequency = <100000>; +- +- /* optional 1K EEPROM with revision information */ +- eeprom@51 { +- compatible = "atmel,24c01"; +- reg = <0x51>; +- pagesize = <8>; +- }; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-#include "omap-gpmc-smsc911x.dtsi" +- +-&gpmc { +- ranges = <5 0 0x2c000000 0x1000000>; /* CS5 */ +- +- ethernet@gpmc { +- reg = <5 0 0xff>; +- interrupt-parent = <&gpio2>; +- interrupts = <12 IRQ_TYPE_LEVEL_LOW>; /* gpio_44 */ +- +- phy-mode = "mii"; +- +- gpmc,cs-on-ns = <10>; +- gpmc,cs-rd-off-ns = <50>; +- gpmc,cs-wr-off-ns = <50>; +- gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <10>; +- gpmc,adv-wr-off-ns = <10>; +- gpmc,oe-on-ns = <15>; +- gpmc,oe-off-ns = <50>; +- gpmc,we-on-ns = <15>; +- gpmc,we-off-ns = <50>; +- gpmc,rd-cycle-ns = <50>; +- gpmc,wr-cycle-ns = <50>; +- gpmc,access-ns = <50>; +- gpmc,page-burst-access-ns = <0>; +- gpmc,bus-turnaround-ns = <35>; +- gpmc,cycle2cycle-delay-ns = <35>; +- gpmc,wr-data-mux-bus-ns = <35>; +- gpmc,wr-access-ns = <50>; +- +- gpmc,mux-add-data = <2>; +- gpmc,sync-read; +- gpmc,sync-write; +- gpmc,clk-activation-ns = <5>; +- gpmc,sync-clk-ps = <20000>; +- }; +-}; +- +-&dss { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +- vdda-supply = <&vdac>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_hdmi_pins>; +- +- port { +- hdmi_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +- }; +-}; +- +-&uart3 { +- interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH +- &omap4_pmx_core OMAP4_UART3_RX>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap4-duovero.dtsi b/scripts/dtc/include-prefixes/arm/omap4-duovero.dtsi +deleted file mode 100644 +index 805dfd40030d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-duovero.dtsi ++++ /dev/null +@@ -1,249 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group +- */ +- +-#include "omap443x.dtsi" +-#include "omap4-mcpdm.dtsi" +- +-/ { +- model = "Gumstix Duovero"; +- compatible = "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; +- +- chosen { +- stdout-path = &uart3; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; /* 1 GB */ +- }; +- +- sound { +- compatible = "ti,abe-twl6040"; +- ti,model = "DuoVero"; +- +- ti,mclk-freq = <38400000>; +- +- ti,mcpdm = <&mcpdm>; +- +- ti,twl6040 = <&twl6040>; +- +- /* Audio routing */ +- ti,audio-routing = +- "Headset Stereophone", "HSOL", +- "Headset Stereophone", "HSOR", +- "HSMIC", "Headset Mic", +- "Headset Mic", "Headset Mic Bias"; +- }; +- +- /* HS USB Host PHY on PORT 1 */ +- hsusb1_phy: hsusb1_phy { +- compatible = "usb-nop-xceiv"; +- reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ +- #phy-cells = <0>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&hsusb1phy_pins>; +- +- clocks = <&auxclk3_ck>; +- clock-names = "main_clk"; +- clock-frequency = <19200000>; +- }; +- +- /* regulator for w2cbw0015 on sdio5 */ +- w2cbw0015_vmmc: w2cbw0015_vmmc { +- pinctrl-names = "default"; +- pinctrl-0 = <&w2cbw0015_pins>; +- compatible = "regulator-fixed"; +- regulator-name = "w2cbw0015"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; /* gpio_43 */ +- startup-delay-us = <70000>; +- enable-active-high; +- regulator-boot-on; +- }; +-}; +- +-&omap4_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &twl6040_pins +- &hsusbb1_pins +- >; +- +- twl6040_pins: pinmux_twl6040_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_nxt.gpio_160 */ +- OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ +- >; +- }; +- +- mcbsp1_pins: pinmux_mcbsp1_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ +- OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ +- OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ +- OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ +- >; +- }; +- +- hsusbb1_pins: pinmux_hsusbb1_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ +- OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ +- OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ +- OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ +- OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ +- OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ +- OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ +- OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ +- OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ +- OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ +- OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ +- OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ +- >; +- }; +- +- hsusb1phy_pins: pinmux_hsusb1phy_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x08c, PIN_OUTPUT | MUX_MODE3) /* gpmc_wait1.gpio_62 */ +- >; +- }; +- +- w2cbw0015_pins: pinmux_w2cbw0015_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ +- OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ +- OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ +- >; +- }; +- +- i2c4_pins: pinmux_i2c4_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ +- OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ +- OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_cmd */ +- OMAP4_IOPAD(0x0e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_dat0 */ +- OMAP4_IOPAD(0x0e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ +- OMAP4_IOPAD(0x0ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ +- OMAP4_IOPAD(0x0ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ +- >; +- }; +- +- mmc5_pins: pinmux_mmc5_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk */ +- OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_cmd */ +- OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_dat0 */ +- OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1 */ +- OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2 */ +- OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3 */ +- >; +- }; +-}; +- +-/* PMIC */ +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- +- clock-frequency = <400000>; +- +- twl: twl@48 { +- reg = <0x48>; +- interrupts = ; /* IRQ_SYS_1N cascaded to gic */ +- }; +- +- twl6040: twl@4b { +- compatible = "ti,twl6040"; +- #clock-cells = <0>; +- reg = <0x4b>; +- interrupts = ; /* IRQ_SYS_2N cascaded to gic */ +- ti,audpwron-gpio = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* gpio_160 */ +- +- vio-supply = <&v1v8>; +- v2v1-supply = <&v2v1>; +- enable-active-high; +- }; +-}; +- +-#include "twl6030.dtsi" +-#include "twl6030_omap4.dtsi" +- +-/* on-board bluetooth / WiFi module */ +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pins>; +- +- clock-frequency = <400000>; +-}; +- +-&mcbsp1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp1_pins>; +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- +- vmmc-supply = <&vmmc>; +- ti,bus-width = <4>; +- ti,non-removable; /* FIXME: use PMIC_MMC detect */ +-}; +- +-&mmc2 { +- status = "disabled"; +-}; +- +-/* mmc3 is available to the expansion board */ +- +-&mmc4 { +- status = "disabled"; +-}; +- +-/* on-board WiFi module */ +-&mmc5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc5_pins>; +- +- vmmc-supply = <&w2cbw0015_vmmc>; +- ti,bus-width = <4>; +- ti,non-removable; +- cap-power-off-card; +- keep-power-in-suspend; +-}; +- +-&twl_usb_comparator { +- usb-supply = <&vusb>; +-}; +- +-&usb_otg_hs { +- interface-type = <1>; +- mode = <3>; +- power = <50>; +-}; +- +-&usbhshost { +- port1-mode = "ehci-phy"; +-}; +- +-&usbhsehci { +- phys = <&hsusb1_phy>; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap4-kc1.dts b/scripts/dtc/include-prefixes/arm/omap4-kc1.dts +deleted file mode 100644 +index e59d17b25a1d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-kc1.dts ++++ /dev/null +@@ -1,179 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2016 Paul Kocialkowski +- */ +-/dts-v1/; +- +-#include "omap443x.dtsi" +- +-/ { +- model = "Amazon Kindle Fire (first generation)"; +- compatible = "amazon,omap4-kc1", "ti,omap4430", "ti,omap4"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512 MB */ +- }; +- +- led-controller { +- compatible = "pwm-leds"; +- +- led-1 { +- label = "green"; +- pwms = <&twl_pwm 0 7812500>; +- max-brightness = <127>; +- }; +- +- led-2 { +- label = "orange"; +- pwms = <&twl_pwm 1 7812500>; +- max-brightness = <127>; +- }; +- }; +-}; +- +-&omap4_pmx_core { +- pinctrl-names = "default"; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ +- OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ +- OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ +- >; +- }; +- +- i2c2_pins: pinmux_i2c2_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ +- OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ +- >; +- }; +- +- i2c3_pins: pinmux_i2c3_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ +- OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ +- >; +- }; +- +- i2c4_pins: pinmux_i2c4_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ +- OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ +- >; +- }; +- +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x040, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat0 */ +- OMAP4_IOPAD(0x042, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat1 */ +- OMAP4_IOPAD(0x044, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat2 */ +- OMAP4_IOPAD(0x046, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat3 */ +- OMAP4_IOPAD(0x048, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat4 */ +- OMAP4_IOPAD(0x04a, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat5 */ +- OMAP4_IOPAD(0x04c, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat6 */ +- OMAP4_IOPAD(0x04e, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat7 */ +- OMAP4_IOPAD(0x082, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_clk */ +- OMAP4_IOPAD(0x084, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_cmd */ +- >; +- }; +- +- usb_otg_hs_pins: pinmux_usb_otg_hs_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x194, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usba0_otg_ce */ +- OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) /* usba0_otg_dp */ +- OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* usba0_otg_dm */ +- >; +- }; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- +- interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH +- &omap4_pmx_core OMAP4_UART3_RX>; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- +- clock-frequency = <400000>; +- +- twl: twl@48 { +- reg = <0x48>; +- /* IRQ# = 7 */ +- interrupts = ; /* IRQ_SYS_1N cascaded to gic */ +- +- twl_power: power { +- compatible = "ti,twl6030-power"; +- ti,system-power-controller; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- +- clock-frequency = <400000>; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- +- clock-frequency = <400000>; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pins>; +- +- clock-frequency = <400000>; +-}; +- +-&mmc1 { +- status = "disabled"; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- +- vmmc-supply = <&vaux1>; +- ti,non-removable; +- bus-width = <8>; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-&mmc4 { +- status = "disabled"; +-}; +- +-&usb_otg_hs { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_otg_hs_pins>; +- +- interface-type = <1>; +- mode = <3>; +- power = <50>; +-}; +- +-#include "twl6030.dtsi" +-#include "twl6030_omap4.dtsi" +- +-&twl_usb_comparator { +- usb-supply = <&vusb>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap4-l4-abe.dtsi b/scripts/dtc/include-prefixes/arm/omap4-l4-abe.dtsi +deleted file mode 100644 +index 7ae8b620515c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-l4-abe.dtsi ++++ /dev/null +@@ -1,497 +0,0 @@ +-&l4_abe { /* 0x40100000 */ +- compatible = "ti,omap4-l4-abe", "simple-pm-bus"; +- reg = <0x40100000 0x400>, +- <0x40100400 0x400>; +- reg-names = "la", "ap"; +- power-domains = <&prm_abe>; +- /* OMAP4_L4_ABE_CLKCTRL is read-only */ +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ +- <0x49000000 0x49000000 0x100000>; +- segment@0 { /* 0x40100000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = +- /* CPU to L4 ABE mapping */ +- <0x00000000 0x00000000 0x000400>, /* ap 0 */ +- <0x00000400 0x00000400 0x000400>, /* ap 1 */ +- <0x00022000 0x00022000 0x001000>, /* ap 2 */ +- <0x00023000 0x00023000 0x001000>, /* ap 3 */ +- <0x00024000 0x00024000 0x001000>, /* ap 4 */ +- <0x00025000 0x00025000 0x001000>, /* ap 5 */ +- <0x00026000 0x00026000 0x001000>, /* ap 6 */ +- <0x00027000 0x00027000 0x001000>, /* ap 7 */ +- <0x00028000 0x00028000 0x001000>, /* ap 8 */ +- <0x00029000 0x00029000 0x001000>, /* ap 9 */ +- <0x0002a000 0x0002a000 0x001000>, /* ap 10 */ +- <0x0002b000 0x0002b000 0x001000>, /* ap 11 */ +- <0x0002e000 0x0002e000 0x001000>, /* ap 12 */ +- <0x0002f000 0x0002f000 0x001000>, /* ap 13 */ +- <0x00030000 0x00030000 0x001000>, /* ap 14 */ +- <0x00031000 0x00031000 0x001000>, /* ap 15 */ +- <0x00032000 0x00032000 0x001000>, /* ap 16 */ +- <0x00033000 0x00033000 0x001000>, /* ap 17 */ +- <0x00038000 0x00038000 0x001000>, /* ap 18 */ +- <0x00039000 0x00039000 0x001000>, /* ap 19 */ +- <0x0003a000 0x0003a000 0x001000>, /* ap 20 */ +- <0x0003b000 0x0003b000 0x001000>, /* ap 21 */ +- <0x0003c000 0x0003c000 0x001000>, /* ap 22 */ +- <0x0003d000 0x0003d000 0x001000>, /* ap 23 */ +- <0x0003e000 0x0003e000 0x001000>, /* ap 24 */ +- <0x0003f000 0x0003f000 0x001000>, /* ap 25 */ +- <0x00080000 0x00080000 0x010000>, /* ap 26 */ +- <0x00080000 0x00080000 0x001000>, /* ap 27 */ +- <0x000a0000 0x000a0000 0x010000>, /* ap 28 */ +- <0x000a0000 0x000a0000 0x001000>, /* ap 29 */ +- <0x000c0000 0x000c0000 0x010000>, /* ap 30 */ +- <0x000c0000 0x000c0000 0x001000>, /* ap 31 */ +- <0x000f1000 0x000f1000 0x001000>, /* ap 32 */ +- <0x000f2000 0x000f2000 0x001000>, /* ap 33 */ +- +- /* L3 to L4 ABE mapping */ +- <0x49000000 0x49000000 0x000400>, /* ap 0 */ +- <0x49000400 0x49000400 0x000400>, /* ap 1 */ +- <0x49022000 0x49022000 0x001000>, /* ap 2 */ +- <0x49023000 0x49023000 0x001000>, /* ap 3 */ +- <0x49024000 0x49024000 0x001000>, /* ap 4 */ +- <0x49025000 0x49025000 0x001000>, /* ap 5 */ +- <0x49026000 0x49026000 0x001000>, /* ap 6 */ +- <0x49027000 0x49027000 0x001000>, /* ap 7 */ +- <0x49028000 0x49028000 0x001000>, /* ap 8 */ +- <0x49029000 0x49029000 0x001000>, /* ap 9 */ +- <0x4902a000 0x4902a000 0x001000>, /* ap 10 */ +- <0x4902b000 0x4902b000 0x001000>, /* ap 11 */ +- <0x4902e000 0x4902e000 0x001000>, /* ap 12 */ +- <0x4902f000 0x4902f000 0x001000>, /* ap 13 */ +- <0x49030000 0x49030000 0x001000>, /* ap 14 */ +- <0x49031000 0x49031000 0x001000>, /* ap 15 */ +- <0x49032000 0x49032000 0x001000>, /* ap 16 */ +- <0x49033000 0x49033000 0x001000>, /* ap 17 */ +- <0x49038000 0x49038000 0x001000>, /* ap 18 */ +- <0x49039000 0x49039000 0x001000>, /* ap 19 */ +- <0x4903a000 0x4903a000 0x001000>, /* ap 20 */ +- <0x4903b000 0x4903b000 0x001000>, /* ap 21 */ +- <0x4903c000 0x4903c000 0x001000>, /* ap 22 */ +- <0x4903d000 0x4903d000 0x001000>, /* ap 23 */ +- <0x4903e000 0x4903e000 0x001000>, /* ap 24 */ +- <0x4903f000 0x4903f000 0x001000>, /* ap 25 */ +- <0x49080000 0x49080000 0x010000>, /* ap 26 */ +- <0x49080000 0x49080000 0x001000>, /* ap 27 */ +- <0x490a0000 0x490a0000 0x010000>, /* ap 28 */ +- <0x490a0000 0x490a0000 0x001000>, /* ap 29 */ +- <0x490c0000 0x490c0000 0x010000>, /* ap 30 */ +- <0x490c0000 0x490c0000 0x001000>, /* ap 31 */ +- <0x490f1000 0x490f1000 0x001000>, /* ap 32 */ +- <0x490f2000 0x490f2000 0x001000>; /* ap 33 */ +- +- target-module@22000 { /* 0x40122000, ap 2 02.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x2208c 0x4>; +- reg-names = "sysc"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x22000 0x1000>, +- <0x49022000 0x49022000 0x1000>; +- +- mcbsp1: mcbsp@0 { +- compatible = "ti,omap4-mcbsp"; +- reg = <0x0 0xff>, /* MPU private access */ +- <0x49022000 0xff>; /* L3 Interconnect */ +- reg-names = "mpu", "dma"; +- interrupts = ; +- interrupt-names = "common"; +- ti,buffer-size = <128>; +- dmas = <&sdma 33>, +- <&sdma 34>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- }; +- +- target-module@24000 { /* 0x40124000, ap 4 04.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x2408c 0x4>; +- reg-names = "sysc"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x24000 0x1000>, +- <0x49024000 0x49024000 0x1000>; +- +- mcbsp2: mcbsp@0 { +- compatible = "ti,omap4-mcbsp"; +- reg = <0x0 0xff>, /* MPU private access */ +- <0x49024000 0xff>; /* L3 Interconnect */ +- reg-names = "mpu", "dma"; +- interrupts = ; +- interrupt-names = "common"; +- ti,buffer-size = <128>; +- dmas = <&sdma 17>, +- <&sdma 18>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- }; +- +- target-module@26000 { /* 0x40126000, ap 6 06.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x2608c 0x4>; +- reg-names = "sysc"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x26000 0x1000>, +- <0x49026000 0x49026000 0x1000>; +- +- mcbsp3: mcbsp@0 { +- compatible = "ti,omap4-mcbsp"; +- reg = <0x0 0xff>, /* MPU private access */ +- <0x49026000 0xff>; /* L3 Interconnect */ +- reg-names = "mpu", "dma"; +- interrupts = ; +- interrupt-names = "common"; +- ti,buffer-size = <128>; +- dmas = <&sdma 19>, +- <&sdma 20>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- }; +- +- target-module@28000 { /* 0x40128000, ap 8 08.0 */ +- /* 0x4012a000, ap 10 0a.0 */ +- compatible = "ti,sysc-mcasp", "ti,sysc"; +- reg = <0x28000 0x4>, +- <0x28004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x28000 0x1000>, +- <0x49028000 0x49028000 0x1000>, +- <0x2000 0x2a000 0x1000>, +- <0x4902a000 0x4902a000 0x1000>; +- +- mcasp0: mcasp@0 { +- compatible = "ti,omap4-mcasp-audio"; +- reg = <0x0 0x2000>, +- <0x4902a000 0x1000>; /* L3 data port */ +- reg-names = "mpu","dat"; +- interrupts = ; +- interrupt-names = "tx"; +- dmas = <&sdma 8>; +- dma-names = "tx"; +- clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; +- clock-names = "fck"; +- op-mode = <1>; /* MCASP_DIT_MODE */ +- serial-dir = < 1 >; /* 1 TX serializers */ +- status = "disabled"; +- }; +- }; +- +- target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x2e000 0x4>, +- <0x2e010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2e000 0x1000>, +- <0x4902e000 0x4902e000 0x1000>; +- +- dmic: dmic@0 { +- compatible = "ti,omap4-dmic"; +- reg = <0x0 0x7f>, /* MPU private access */ +- <0x4902e000 0x7f>; /* L3 Interconnect */ +- reg-names = "mpu", "dma"; +- interrupts = ; +- dmas = <&sdma 67>; +- dma-names = "up_link"; +- status = "disabled"; +- }; +- }; +- +- target-module@30000 { /* 0x40130000, ap 14 0e.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x30000 0x4>, +- <0x30010 0x4>, +- <0x30014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x30000 0x1000>, +- <0x49030000 0x49030000 0x1000>; +- +- wdt3: wdt@0 { +- compatible = "ti,omap4-wdt", "ti,omap3-wdt"; +- reg = <0x0 0x80>; +- interrupts = ; +- }; +- }; +- +- mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x32000 0x4>, +- <0x32010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x32000 0x1000>, +- <0x49032000 0x49032000 0x1000>; +- +- /* Must be only enabled for boards with pdmclk wired */ +- status = "disabled"; +- +- mcpdm: mcpdm@0 { +- compatible = "ti,omap4-mcpdm"; +- reg = <0x0 0x7f>, /* MPU private access */ +- <0x49032000 0x7f>; /* L3 Interconnect */ +- reg-names = "mpu", "dma"; +- interrupts = ; +- dmas = <&sdma 65>, +- <&sdma 66>; +- dma-names = "up_link", "dn_link"; +- }; +- }; +- +- target-module@38000 { /* 0x40138000, ap 18 12.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x38000 0x4>, +- <0x38010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x38000 0x1000>, +- <0x49038000 0x49038000 0x1000>; +- +- timer5: timer@0 { +- compatible = "ti,omap4430-timer"; +- reg = <0x00000000 0x80>, +- <0x49038000 0x80>; +- clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>, +- <&syc_clk_div_ck>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-dsp; +- }; +- }; +- +- target-module@3a000 { /* 0x4013a000, ap 20 14.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x3a000 0x4>, +- <0x3a010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3a000 0x1000>, +- <0x4903a000 0x4903a000 0x1000>; +- +- timer6: timer@0 { +- compatible = "ti,omap4430-timer"; +- reg = <0x00000000 0x80>, +- <0x4903a000 0x80>; +- clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>, +- <&syc_clk_div_ck>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-dsp; +- }; +- }; +- +- target-module@3c000 { /* 0x4013c000, ap 22 16.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x3c000 0x4>, +- <0x3c010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3c000 0x1000>, +- <0x4903c000 0x4903c000 0x1000>; +- +- timer7: timer@0 { +- compatible = "ti,omap4430-timer"; +- reg = <0x00000000 0x80>, +- <0x4903c000 0x80>; +- clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>, +- <&syc_clk_div_ck>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-dsp; +- }; +- }; +- +- target-module@3e000 { /* 0x4013e000, ap 24 18.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x3e000 0x4>, +- <0x3e010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3e000 0x1000>, +- <0x4903e000 0x4903e000 0x1000>; +- +- timer8: timer@0 { +- compatible = "ti,omap4430-timer"; +- reg = <0x00000000 0x80>, +- <0x4903e000 0x80>; +- clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>, +- <&syc_clk_div_ck>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-pwm; +- ti,timer-dsp; +- }; +- }; +- +- target-module@80000 { /* 0x40180000, ap 26 1a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x80000 0x10000>, +- <0x49080000 0x49080000 0x10000>; +- }; +- +- target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa0000 0x10000>, +- <0x490a0000 0x490a0000 0x10000>; +- }; +- +- target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc0000 0x10000>, +- <0x490c0000 0x490c0000 0x10000>; +- }; +- +- target-module@f1000 { /* 0x401f1000, ap 32 20.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xf1000 0x4>, +- <0xf1010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf1000 0x1000>, +- <0x490f1000 0x490f1000 0x1000>; +- +- /* +- * No child device binding or driver in mainline. +- * See Android tree and related upstreaming efforts +- * for the old driver. +- */ +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap4-l4.dtsi b/scripts/dtc/include-prefixes/arm/omap4-l4.dtsi +deleted file mode 100644 +index 46b8f9efd413..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-l4.dtsi ++++ /dev/null +@@ -1,2483 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-&l4_cfg { /* 0x4a000000 */ +- compatible = "ti,omap4-l4-cfg", "simple-pm-bus"; +- power-domains = <&prm_core>; +- clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>; +- clock-names = "fck"; +- reg = <0x4a000000 0x800>, +- <0x4a000800 0x800>, +- <0x4a001000 0x1000>; +- reg-names = "ap", "la", "ia0"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ +- <0x00080000 0x4a080000 0x080000>, /* segment 1 */ +- <0x00100000 0x4a100000 0x080000>, /* segment 2 */ +- <0x00180000 0x4a180000 0x080000>, /* segment 3 */ +- <0x00200000 0x4a200000 0x080000>, /* segment 4 */ +- <0x00280000 0x4a280000 0x080000>, /* segment 5 */ +- <0x00300000 0x4a300000 0x080000>; /* segment 6 */ +- +- segment@0 { /* 0x4a000000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ +- <0x00001000 0x00001000 0x001000>, /* ap 1 */ +- <0x00000800 0x00000800 0x000800>, /* ap 2 */ +- <0x00002000 0x00002000 0x001000>, /* ap 3 */ +- <0x00003000 0x00003000 0x001000>, /* ap 4 */ +- <0x00004000 0x00004000 0x001000>, /* ap 5 */ +- <0x00005000 0x00005000 0x001000>, /* ap 6 */ +- <0x00056000 0x00056000 0x001000>, /* ap 7 */ +- <0x00057000 0x00057000 0x001000>, /* ap 8 */ +- <0x0005c000 0x0005c000 0x001000>, /* ap 9 */ +- <0x00058000 0x00058000 0x004000>, /* ap 10 */ +- <0x00062000 0x00062000 0x001000>, /* ap 11 */ +- <0x00063000 0x00063000 0x001000>, /* ap 12 */ +- <0x00008000 0x00008000 0x002000>, /* ap 23 */ +- <0x0000a000 0x0000a000 0x001000>, /* ap 24 */ +- <0x00066000 0x00066000 0x001000>, /* ap 25 */ +- <0x00067000 0x00067000 0x001000>, /* ap 26 */ +- <0x0005e000 0x0005e000 0x002000>, /* ap 80 */ +- <0x00060000 0x00060000 0x001000>, /* ap 81 */ +- <0x00064000 0x00064000 0x001000>, /* ap 86 */ +- <0x00065000 0x00065000 0x001000>; /* ap 87 */ +- +- target-module@2000 { /* 0x4a002000, ap 3 06.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x2000 0x4>, +- <0x2010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2000 0x1000>; +- +- omap4_scm_core: scm@0 { +- compatible = "ti,omap4-scm-core", "simple-bus"; +- reg = <0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x1000>; +- +- scm_conf: scm_conf@0 { +- compatible = "syscon"; +- reg = <0x0 0x800>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- omap_control_usb2phy: control-phy@300 { +- compatible = "ti,control-phy-usb2"; +- reg = <0x300 0x4>; +- reg-names = "power"; +- }; +- +- omap_control_usbotg: control-phy@33c { +- compatible = "ti,control-phy-otghs"; +- reg = <0x33c 0x4>; +- reg-names = "otghs_control"; +- }; +- }; +- }; +- +- target-module@4000 { /* 0x4a004000, ap 5 02.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x4000 0x4>; +- reg-names = "rev"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4000 0x1000>; +- +- cm1: cm1@0 { +- compatible = "ti,omap4-cm1", "simple-bus"; +- reg = <0x0 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x2000>; +- +- cm1_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- cm1_clockdomains: clockdomains { +- }; +- }; +- }; +- +- target-module@8000 { /* 0x4a008000, ap 23 32.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x8000 0x4>; +- reg-names = "rev"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x8000 0x2000>; +- +- cm2: cm2@0 { +- compatible = "ti,omap4-cm2", "simple-bus"; +- reg = <0x0 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x2000>; +- +- cm2_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- cm2_clockdomains: clockdomains { +- }; +- }; +- }; +- +- target-module@56000 { /* 0x4a056000, ap 7 0a.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x56000 0x4>, +- <0x5602c 0x4>, +- <0x56028 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l3_dma_clkdm */ +- clocks = <&l3_dma_clkctrl OMAP4_DMA_SYSTEM_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x56000 0x1000>; +- +- sdma: dma-controller@0 { +- compatible = "ti,omap4430-sdma", "ti,omap-sdma"; +- reg = <0x0 0x1000>; +- interrupts = , +- , +- , +- ; +- #dma-cells = <1>; +- dma-channels = <32>; +- dma-requests = <127>; +- }; +- }; +- +- target-module@58000 { /* 0x4a058000, ap 10 0e.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x58000 0x4>, +- <0x58010 0x4>, +- <0x58014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ +- clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x58000 0x5000>; +- +- hsi: hsi@0 { +- compatible = "ti,omap4-hsi"; +- reg = <0x0 0x4000>, +- <0x5000 0x1000>; +- reg-names = "sys", "gdd"; +- +- clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; +- clock-names = "hsi_fck"; +- +- interrupts = ; +- interrupt-names = "gdd_mpu"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x4000>; +- +- hsi_port1: hsi-port@2000 { +- compatible = "ti,omap4-hsi-port"; +- reg = <0x2000 0x800>, +- <0x2800 0x800>; +- reg-names = "tx", "rx"; +- interrupts = ; +- }; +- +- hsi_port2: hsi-port@3000 { +- compatible = "ti,omap4-hsi-port"; +- reg = <0x3000 0x800>, +- <0x3800 0x800>; +- reg-names = "tx", "rx"; +- interrupts = ; +- }; +- }; +- }; +- +- target-module@5e000 { /* 0x4a05e000, ap 80 68.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5e000 0x2000>; +- }; +- +- target-module@62000 { /* 0x4a062000, ap 11 16.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x62000 0x4>, +- <0x62010 0x4>, +- <0x62014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ +- clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x62000 0x1000>; +- +- usbhstll: usbhstll@0 { +- compatible = "ti,usbhs-tll"; +- reg = <0x0 0x1000>; +- interrupts = ; +- }; +- }; +- +- target-module@64000 { /* 0x4a064000, ap 86 1e.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x64000 0x4>, +- <0x64010 0x4>, +- <0x64014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = ; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ +- clocks = <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x64000 0x1000>; +- +- usbhshost: usbhshost@0 { +- compatible = "ti,usbhs-host"; +- reg = <0x0 0x800>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x1000>; +- clocks = <&init_60m_fclk>, +- <&xclk60mhsp1_ck>, +- <&xclk60mhsp2_ck>; +- clock-names = "refclk_60m_int", +- "refclk_60m_ext_p1", +- "refclk_60m_ext_p2"; +- +- usbhsohci: ohci@800 { +- compatible = "ti,ohci-omap3"; +- reg = <0x800 0x400>; +- interrupts = ; +- remote-wakeup-connected; +- }; +- +- usbhsehci: ehci@c00 { +- compatible = "ti,ehci-omap"; +- reg = <0xc00 0x400>; +- interrupts = ; +- }; +- }; +- }; +- +- target-module@66000 { /* 0x4a066000, ap 25 26.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x66000 0x4>, +- <0x66010 0x4>, +- <0x66014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */ +- clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; +- clock-names = "fck"; +- power-domains = <&prm_tesla>; +- resets = <&prm_tesla 1>; +- reset-names = "rstctrl"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x66000 0x1000>; +- +- mmu_dsp: mmu@0 { +- compatible = "ti,omap4-iommu"; +- reg = <0x0 0x100>; +- interrupts = ; +- #iommu-cells = <0>; +- }; +- }; +- }; +- +- segment@80000 { /* 0x4a080000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ +- <0x0005a000 0x000da000 0x001000>, /* ap 14 */ +- <0x0005b000 0x000db000 0x001000>, /* ap 15 */ +- <0x0005c000 0x000dc000 0x001000>, /* ap 16 */ +- <0x0005d000 0x000dd000 0x001000>, /* ap 17 */ +- <0x0005e000 0x000de000 0x001000>, /* ap 18 */ +- <0x00060000 0x000e0000 0x001000>, /* ap 19 */ +- <0x00061000 0x000e1000 0x001000>, /* ap 20 */ +- <0x00074000 0x000f4000 0x001000>, /* ap 27 */ +- <0x00075000 0x000f5000 0x001000>, /* ap 28 */ +- <0x00076000 0x000f6000 0x001000>, /* ap 29 */ +- <0x00077000 0x000f7000 0x001000>, /* ap 30 */ +- <0x00036000 0x000b6000 0x001000>, /* ap 69 */ +- <0x00037000 0x000b7000 0x001000>, /* ap 70 */ +- <0x0004d000 0x000cd000 0x001000>, /* ap 78 */ +- <0x0004e000 0x000ce000 0x001000>, /* ap 79 */ +- <0x00029000 0x000a9000 0x001000>, /* ap 82 */ +- <0x0002a000 0x000aa000 0x001000>, /* ap 83 */ +- <0x0002b000 0x000ab000 0x001000>, /* ap 84 */ +- <0x0002c000 0x000ac000 0x001000>, /* ap 85 */ +- <0x0002d000 0x000ad000 0x001000>, /* ap 88 */ +- <0x0002e000 0x000ae000 0x001000>; /* ap 89 */ +- +- target-module@29000 { /* 0x4a0a9000, ap 82 04.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x29000 0x1000>; +- }; +- +- target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x2b400 0x4>, +- <0x2b404 0x4>, +- <0x2b408 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ +- clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2b000 0x1000>; +- +- usb_otg_hs: usb_otg_hs@0 { +- compatible = "ti,omap4-musb"; +- reg = <0x0 0x7ff>; +- interrupts = , ; +- interrupt-names = "mc", "dma"; +- usb-phy = <&usb2_phy>; +- phys = <&usb2_phy>; +- phy-names = "usb2-phy"; +- multipoint = <1>; +- num-eps = <16>; +- ram-bits = <12>; +- ctrl-module = <&omap_control_usbotg>; +- }; +- }; +- +- target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x2d000 0x4>, +- <0x2d010 0x4>, +- <0x2d014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ +- clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2d000 0x1000>; +- +- ocp2scp@0 { +- compatible = "ti,omap-ocp2scp"; +- reg = <0x0 0x1f>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x1000>; +- usb2_phy: usb2phy@80 { +- compatible = "ti,omap-usb2"; +- reg = <0x80 0x58>; +- ctrl-module = <&omap_control_usb2phy>; +- clocks = <&usb_phy_cm_clk32k>; +- clock-names = "wkupclk"; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- /* d2d mdm */ +- target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x36000 0x4>, +- <0x36010 0x4>, +- <0x36014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */ +- clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x36000 0x1000>; +- }; +- +- /* d2d mpu */ +- target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4d000 0x4>, +- <0x4d010 0x4>, +- <0x4d014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */ +- clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4d000 0x1000>; +- }; +- +- target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */ +- compatible = "ti,sysc-omap4-sr", "ti,sysc"; +- reg = <0x59038 0x4>; +- reg-names = "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ +- clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x59000 0x1000>; +- +- smartreflex_mpu: smartreflex@0 { +- compatible = "ti,omap4-smartreflex-mpu"; +- reg = <0x0 0x80>; +- interrupts = ; +- }; +- }; +- +- target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */ +- compatible = "ti,sysc-omap4-sr", "ti,sysc"; +- reg = <0x5b038 0x4>; +- reg-names = "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ +- clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5b000 0x1000>; +- +- smartreflex_iva: smartreflex@0 { +- compatible = "ti,omap4-smartreflex-iva"; +- reg = <0x0 0x80>; +- interrupts = ; +- }; +- }; +- +- target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */ +- compatible = "ti,sysc-omap4-sr", "ti,sysc"; +- reg = <0x5d038 0x4>; +- reg-names = "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ +- clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5d000 0x1000>; +- +- smartreflex_core: smartreflex@0 { +- compatible = "ti,omap4-smartreflex-core"; +- reg = <0x0 0x80>; +- interrupts = ; +- }; +- }; +- +- target-module@60000 { /* 0x4a0e0000, ap 19 1c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x60000 0x1000>; +- }; +- +- target-module@74000 { /* 0x4a0f4000, ap 27 24.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x74000 0x4>, +- <0x74010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ +- clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x74000 0x1000>; +- +- mailbox: mailbox@0 { +- compatible = "ti,omap4-mailbox"; +- reg = <0x0 0x200>; +- interrupts = ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <3>; +- ti,mbox-num-fifos = <8>; +- mbox_ipu: mbox-ipu { +- ti,mbox-tx = <0 0 0>; +- ti,mbox-rx = <1 0 0>; +- }; +- mbox_dsp: mbox-dsp { +- ti,mbox-tx = <3 0 0>; +- ti,mbox-rx = <2 0 0>; +- }; +- }; +- }; +- +- target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x76000 0x4>, +- <0x76010 0x4>, +- <0x76014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ +- clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x76000 0x1000>; +- +- hwspinlock: spinlock@0 { +- compatible = "ti,omap4-hwspinlock"; +- reg = <0x0 0x1000>; +- #hwlock-cells = <1>; +- }; +- }; +- }; +- +- segment@100000 { /* 0x4a100000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */ +- <0x00001000 0x00101000 0x001000>, /* ap 22 */ +- <0x00002000 0x00102000 0x001000>, /* ap 61 */ +- <0x00003000 0x00103000 0x001000>, /* ap 62 */ +- <0x00008000 0x00108000 0x001000>, /* ap 63 */ +- <0x00009000 0x00109000 0x001000>, /* ap 64 */ +- <0x0000a000 0x0010a000 0x001000>, /* ap 65 */ +- <0x0000b000 0x0010b000 0x001000>; /* ap 66 */ +- +- target-module@0 { /* 0x4a100000, ap 21 2a.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x0 0x4>, +- <0x10 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1000>; +- +- omap4_pmx_core: pinmux@40 { +- compatible = "ti,omap4-padconf", +- "pinctrl-single"; +- reg = <0x40 0x0196>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <1>; +- #interrupt-cells = <1>; +- interrupt-controller; +- pinctrl-single,register-width = <16>; +- pinctrl-single,function-mask = <0x7fff>; +- }; +- +- omap4_padconf_global: omap4_padconf_global@5a0 { +- compatible = "syscon", +- "simple-bus"; +- reg = <0x5a0 0x170>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x5a0 0x170>; +- +- pbias_regulator: pbias_regulator@60 { +- compatible = "ti,pbias-omap4", "ti,pbias-omap"; +- reg = <0x60 0x4>; +- syscon = <&omap4_padconf_global>; +- pbias_mmc_reg: pbias_mmc_omap4 { +- regulator-name = "pbias_mmc_omap4"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- }; +- }; +- }; +- }; +- +- target-module@2000 { /* 0x4a102000, ap 61 3c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2000 0x1000>; +- }; +- +- target-module@8000 { /* 0x4a108000, ap 63 62.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x8000 0x1000>; +- }; +- +- target-module@a000 { /* 0x4a10a000, ap 65 50.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xa000 0x4>, +- <0xa010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-delay-us = <2>; +- /* Domains (V, P, C): core, cam_pwrdm, iss_clkdm */ +- clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa000 0x1000>; +- +- /* No child device binding or driver in mainline */ +- }; +- }; +- +- segment@180000 { /* 0x4a180000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- segment@200000 { /* 0x4a200000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */ +- <0x0001f000 0x0021f000 0x001000>, /* ap 32 */ +- <0x0000a000 0x0020a000 0x001000>, /* ap 33 */ +- <0x0000b000 0x0020b000 0x001000>, /* ap 34 */ +- <0x00004000 0x00204000 0x001000>, /* ap 35 */ +- <0x00005000 0x00205000 0x001000>, /* ap 36 */ +- <0x00006000 0x00206000 0x001000>, /* ap 37 */ +- <0x00007000 0x00207000 0x001000>, /* ap 38 */ +- <0x00012000 0x00212000 0x001000>, /* ap 39 */ +- <0x00013000 0x00213000 0x001000>, /* ap 40 */ +- <0x0000c000 0x0020c000 0x001000>, /* ap 41 */ +- <0x0000d000 0x0020d000 0x001000>, /* ap 42 */ +- <0x00010000 0x00210000 0x001000>, /* ap 43 */ +- <0x00011000 0x00211000 0x001000>, /* ap 44 */ +- <0x00016000 0x00216000 0x001000>, /* ap 45 */ +- <0x00017000 0x00217000 0x001000>, /* ap 46 */ +- <0x00014000 0x00214000 0x001000>, /* ap 47 */ +- <0x00015000 0x00215000 0x001000>, /* ap 48 */ +- <0x00018000 0x00218000 0x001000>, /* ap 49 */ +- <0x00019000 0x00219000 0x001000>, /* ap 50 */ +- <0x00020000 0x00220000 0x001000>, /* ap 51 */ +- <0x00021000 0x00221000 0x001000>, /* ap 52 */ +- <0x00026000 0x00226000 0x001000>, /* ap 53 */ +- <0x00027000 0x00227000 0x001000>, /* ap 54 */ +- <0x00028000 0x00228000 0x001000>, /* ap 55 */ +- <0x00029000 0x00229000 0x001000>, /* ap 56 */ +- <0x0002a000 0x0022a000 0x001000>, /* ap 57 */ +- <0x0002b000 0x0022b000 0x001000>, /* ap 58 */ +- <0x0001c000 0x0021c000 0x001000>, /* ap 59 */ +- <0x0001d000 0x0021d000 0x001000>; /* ap 60 */ +- +- target-module@4000 { /* 0x4a204000, ap 35 42.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4000 0x1000>; +- }; +- +- target-module@6000 { /* 0x4a206000, ap 37 4a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6000 0x1000>; +- }; +- +- target-module@a000 { /* 0x4a20a000, ap 33 2c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa000 0x1000>; +- }; +- +- target-module@c000 { /* 0x4a20c000, ap 41 20.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc000 0x1000>; +- }; +- +- target-module@10000 { /* 0x4a210000, ap 43 52.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10000 0x1000>; +- }; +- +- target-module@12000 { /* 0x4a212000, ap 39 18.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x12000 0x1000>; +- }; +- +- target-module@14000 { /* 0x4a214000, ap 47 30.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x14000 0x1000>; +- }; +- +- target-module@16000 { /* 0x4a216000, ap 45 28.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x16000 0x1000>; +- }; +- +- target-module@18000 { /* 0x4a218000, ap 49 38.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x18000 0x1000>; +- }; +- +- target-module@1c000 { /* 0x4a21c000, ap 59 5a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1c000 0x1000>; +- }; +- +- target-module@1e000 { /* 0x4a21e000, ap 31 10.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1e000 0x1000>; +- }; +- +- target-module@20000 { /* 0x4a220000, ap 51 40.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x20000 0x1000>; +- }; +- +- target-module@26000 { /* 0x4a226000, ap 53 34.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x26000 0x1000>; +- }; +- +- target-module@28000 { /* 0x4a228000, ap 55 2e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x28000 0x1000>; +- }; +- +- target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2a000 0x1000>; +- }; +- }; +- +- segment@280000 { /* 0x4a280000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */ +- <0x00040000 0x00340000 0x001000>, /* ap 68 */ +- <0x00020000 0x00320000 0x004000>, /* ap 71 */ +- <0x00024000 0x00324000 0x002000>, /* ap 72 */ +- <0x00026000 0x00326000 0x001000>, /* ap 73 */ +- <0x00027000 0x00327000 0x001000>, /* ap 74 */ +- <0x00028000 0x00328000 0x001000>, /* ap 75 */ +- <0x00029000 0x00329000 0x001000>, /* ap 76 */ +- <0x00030000 0x00330000 0x010000>, /* ap 77 */ +- <0x0002a000 0x0032a000 0x002000>, /* ap 90 */ +- <0x0002c000 0x0032c000 0x004000>; /* ap 91 */ +- +- l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x00020000>, +- <0x00020000 0x00020000 0x00004000>, +- <0x00024000 0x00024000 0x00002000>, +- <0x00026000 0x00026000 0x00001000>, +- <0x00027000 0x00027000 0x00001000>, +- <0x00028000 0x00028000 0x00001000>, +- <0x00029000 0x00029000 0x00001000>, +- <0x0002a000 0x0002a000 0x00002000>, +- <0x0002c000 0x0002c000 0x00004000>, +- <0x00030000 0x00030000 0x00010000>; +- }; +- }; +-}; +- +-&l4_wkup { /* 0x4a300000 */ +- compatible = "ti,omap4-l4-wkup", "simple-pm-bus"; +- power-domains = <&prm_wkup>; +- clocks = <&l4_wkup_clkctrl OMAP4_L4_WKUP_CLKCTRL 0>; +- clock-names = "fck"; +- reg = <0x4a300000 0x800>, +- <0x4a300800 0x800>, +- <0x4a301000 0x1000>; +- reg-names = "ap", "la", "ia0"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x4a300000 0x010000>, /* segment 0 */ +- <0x00010000 0x4a310000 0x010000>, /* segment 1 */ +- <0x00020000 0x4a320000 0x010000>; /* segment 2 */ +- +- segment@0 { /* 0x4a300000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ +- <0x00001000 0x00001000 0x001000>, /* ap 1 */ +- <0x00000800 0x00000800 0x000800>, /* ap 2 */ +- <0x00006000 0x00006000 0x002000>, /* ap 3 */ +- <0x00008000 0x00008000 0x001000>, /* ap 4 */ +- <0x0000a000 0x0000a000 0x001000>, /* ap 15 */ +- <0x0000b000 0x0000b000 0x001000>, /* ap 16 */ +- <0x00004000 0x00004000 0x001000>, /* ap 17 */ +- <0x00005000 0x00005000 0x001000>, /* ap 18 */ +- <0x0000c000 0x0000c000 0x001000>, /* ap 19 */ +- <0x0000d000 0x0000d000 0x001000>; /* ap 20 */ +- +- target-module@4000 { /* 0x4a304000, ap 17 24.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4000 0x4>, +- <0x4004 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- ; +- /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ +- clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4000 0x1000>; +- +- counter32k: counter@0 { +- compatible = "ti,omap-counter32k"; +- reg = <0x0 0x20>; +- }; +- }; +- +- target-module@6000 { /* 0x4a306000, ap 3 08.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x6000 0x4>; +- reg-names = "rev"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6000 0x2000>; +- +- prm: prm@0 { +- compatible = "ti,omap4-prm", "simple-bus"; +- reg = <0x0 0x2000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x2000>; +- +- prm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- prm_clockdomains: clockdomains { +- }; +- }; +- }; +- +- target-module@a000 { /* 0x4a30a000, ap 15 34.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xa000 0x4>; +- reg-names = "rev"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa000 0x1000>; +- +- scrm: scrm@0 { +- compatible = "ti,omap4-scrm"; +- reg = <0x0 0x2000>; +- +- scrm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- scrm_clockdomains: clockdomains { +- }; +- }; +- }; +- +- target-module@c000 { /* 0x4a30c000, ap 19 2c.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xc000 0x4>, +- <0xc010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc000 0x1000>; +- +- omap4_scm_wkup: scm@c000 { +- compatible = "ti,omap4-scm-wkup"; +- reg = <0xc000 0x1000>; +- }; +- }; +- }; +- +- segment@10000 { /* 0x4a310000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ +- <0x00001000 0x00011000 0x001000>, /* ap 6 */ +- <0x00004000 0x00014000 0x001000>, /* ap 7 */ +- <0x00005000 0x00015000 0x001000>, /* ap 8 */ +- <0x00008000 0x00018000 0x001000>, /* ap 9 */ +- <0x00009000 0x00019000 0x001000>, /* ap 10 */ +- <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ +- <0x0000d000 0x0001d000 0x001000>, /* ap 12 */ +- <0x0000e000 0x0001e000 0x001000>, /* ap 21 */ +- <0x0000f000 0x0001f000 0x001000>; /* ap 22 */ +- +- gpio1_target: target-module@0 { /* 0x4a310000, ap 5 14.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x0 0x4>, +- <0x10 0x4>, +- <0x114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ +- clocks = <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 0>, +- <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1000>; +- +- gpio1: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- ti,gpio-always-on; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@4000 { /* 0x4a314000, ap 7 18.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4000 0x4>, +- <0x4010 0x4>, +- <0x4014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ +- clocks = <&l4_wkup_clkctrl OMAP4_WD_TIMER2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4000 0x1000>; +- +- wdt2: wdt@0 { +- compatible = "ti,omap4-wdt", "ti,omap3-wdt"; +- reg = <0x0 0x80>; +- interrupts = ; +- }; +- }; +- +- timer1_target: target-module@8000 { /* 0x4a318000, ap 9 1c.0 */ +- compatible = "ti,sysc-omap2-timer", "ti,sysc"; +- reg = <0x8000 0x4>, +- <0x8010 0x4>, +- <0x8014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ +- clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x8000 0x1000>; +- +- timer1: timer@0 { +- compatible = "ti,omap3430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>, +- <&sys_clkin_ck>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-alwon; +- }; +- }; +- +- target-module@c000 { /* 0x4a31c000, ap 11 20.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xc000 0x4>, +- <0xc010 0x4>, +- <0xc014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ +- clocks = <&l4_wkup_clkctrl OMAP4_KBD_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc000 0x1000>; +- +- keypad: keypad@0 { +- compatible = "ti,omap4-keypad"; +- reg = <0x0 0x80>; +- interrupts = ; +- reg-names = "mpu"; +- }; +- }; +- +- target-module@e000 { /* 0x4a31e000, ap 21 30.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xe000 0x4>, +- <0xe010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xe000 0x1000>; +- +- omap4_pmx_wkup: pinmux@40 { +- compatible = "ti,omap4-padconf", +- "pinctrl-single"; +- reg = <0x40 0x0038>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <1>; +- #interrupt-cells = <1>; +- interrupt-controller; +- pinctrl-single,register-width = <16>; +- pinctrl-single,function-mask = <0x7fff>; +- }; +- }; +- }; +- +- segment@20000 { /* 0x4a320000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ +- <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ +- <0x00000000 0x00020000 0x001000>, /* ap 23 */ +- <0x00001000 0x00021000 0x001000>, /* ap 24 */ +- <0x00002000 0x00022000 0x001000>, /* ap 25 */ +- <0x00003000 0x00023000 0x001000>, /* ap 26 */ +- <0x00004000 0x00024000 0x001000>, /* ap 27 */ +- <0x00005000 0x00025000 0x001000>, /* ap 28 */ +- <0x00007000 0x00027000 0x000400>, /* ap 29 */ +- <0x00008000 0x00028000 0x000800>, /* ap 30 */ +- <0x00009000 0x00029000 0x000400>; /* ap 31 */ +- +- target-module@0 { /* 0x4a320000, ap 23 04.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1000>; +- }; +- +- target-module@2000 { /* 0x4a322000, ap 25 0c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2000 0x1000>; +- }; +- +- target-module@4000 { /* 0x4a324000, ap 27 10.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4000 0x1000>; +- }; +- +- target-module@6000 { /* 0x4a326000, ap 13 28.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00006000 0x00001000>, +- <0x00001000 0x00007000 0x00000400>, +- <0x00002000 0x00008000 0x00000800>, +- <0x00003000 0x00009000 0x00000400>; +- }; +- }; +-}; +- +-&l4_per { /* 0x48000000 */ +- compatible = "ti,omap4-l4-per", "simple-pm-bus"; +- power-domains = <&prm_l4per>; +- clocks = <&l4_per_clkctrl OMAP4_L4_PER_CLKCTRL 0>; +- clock-names = "fck"; +- reg = <0x48000000 0x800>, +- <0x48000800 0x800>, +- <0x48001000 0x400>, +- <0x48001400 0x400>, +- <0x48001800 0x400>, +- <0x48001c00 0x400>; +- reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ +- <0x00200000 0x48200000 0x200000>; /* segment 1 */ +- +- segment@0 { /* 0x48000000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ +- <0x00001000 0x00001000 0x000400>, /* ap 1 */ +- <0x00000800 0x00000800 0x000800>, /* ap 2 */ +- <0x00020000 0x00020000 0x001000>, /* ap 3 */ +- <0x00021000 0x00021000 0x001000>, /* ap 4 */ +- <0x00032000 0x00032000 0x001000>, /* ap 5 */ +- <0x00033000 0x00033000 0x001000>, /* ap 6 */ +- <0x00034000 0x00034000 0x001000>, /* ap 7 */ +- <0x00035000 0x00035000 0x001000>, /* ap 8 */ +- <0x00036000 0x00036000 0x001000>, /* ap 9 */ +- <0x00037000 0x00037000 0x001000>, /* ap 10 */ +- <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ +- <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ +- <0x00040000 0x00040000 0x010000>, /* ap 13 */ +- <0x00050000 0x00050000 0x001000>, /* ap 14 */ +- <0x00055000 0x00055000 0x001000>, /* ap 15 */ +- <0x00056000 0x00056000 0x001000>, /* ap 16 */ +- <0x00057000 0x00057000 0x001000>, /* ap 17 */ +- <0x00058000 0x00058000 0x001000>, /* ap 18 */ +- <0x00059000 0x00059000 0x001000>, /* ap 19 */ +- <0x0005a000 0x0005a000 0x001000>, /* ap 20 */ +- <0x0005b000 0x0005b000 0x001000>, /* ap 21 */ +- <0x0005c000 0x0005c000 0x001000>, /* ap 22 */ +- <0x0005d000 0x0005d000 0x001000>, /* ap 23 */ +- <0x0005e000 0x0005e000 0x001000>, /* ap 24 */ +- <0x00060000 0x00060000 0x001000>, /* ap 25 */ +- <0x0006a000 0x0006a000 0x001000>, /* ap 26 */ +- <0x0006b000 0x0006b000 0x001000>, /* ap 27 */ +- <0x0006c000 0x0006c000 0x001000>, /* ap 28 */ +- <0x0006d000 0x0006d000 0x001000>, /* ap 29 */ +- <0x0006e000 0x0006e000 0x001000>, /* ap 30 */ +- <0x0006f000 0x0006f000 0x001000>, /* ap 31 */ +- <0x00070000 0x00070000 0x001000>, /* ap 32 */ +- <0x00071000 0x00071000 0x001000>, /* ap 33 */ +- <0x00072000 0x00072000 0x001000>, /* ap 34 */ +- <0x00073000 0x00073000 0x001000>, /* ap 35 */ +- <0x00061000 0x00061000 0x001000>, /* ap 36 */ +- <0x00096000 0x00096000 0x001000>, /* ap 37 */ +- <0x00097000 0x00097000 0x001000>, /* ap 38 */ +- <0x00076000 0x00076000 0x001000>, /* ap 39 */ +- <0x00077000 0x00077000 0x001000>, /* ap 40 */ +- <0x00078000 0x00078000 0x001000>, /* ap 41 */ +- <0x00079000 0x00079000 0x001000>, /* ap 42 */ +- <0x00086000 0x00086000 0x001000>, /* ap 43 */ +- <0x00087000 0x00087000 0x001000>, /* ap 44 */ +- <0x00088000 0x00088000 0x001000>, /* ap 45 */ +- <0x00089000 0x00089000 0x001000>, /* ap 46 */ +- <0x000b0000 0x000b0000 0x001000>, /* ap 47 */ +- <0x000b1000 0x000b1000 0x001000>, /* ap 48 */ +- <0x00098000 0x00098000 0x001000>, /* ap 49 */ +- <0x00099000 0x00099000 0x001000>, /* ap 50 */ +- <0x0009a000 0x0009a000 0x001000>, /* ap 51 */ +- <0x0009b000 0x0009b000 0x001000>, /* ap 52 */ +- <0x0009c000 0x0009c000 0x001000>, /* ap 53 */ +- <0x0009d000 0x0009d000 0x001000>, /* ap 54 */ +- <0x0009e000 0x0009e000 0x001000>, /* ap 55 */ +- <0x0009f000 0x0009f000 0x001000>, /* ap 56 */ +- <0x00090000 0x00090000 0x002000>, /* ap 57 */ +- <0x00092000 0x00092000 0x001000>, /* ap 58 */ +- <0x000a4000 0x000a4000 0x001000>, /* ap 59 */ +- <0x000a6000 0x000a6000 0x001000>, /* ap 60 */ +- <0x000a8000 0x000a8000 0x004000>, /* ap 61 */ +- <0x000ac000 0x000ac000 0x001000>, /* ap 62 */ +- <0x000ad000 0x000ad000 0x001000>, /* ap 63 */ +- <0x000ae000 0x000ae000 0x001000>, /* ap 64 */ +- <0x000b2000 0x000b2000 0x001000>, /* ap 65 */ +- <0x000b3000 0x000b3000 0x001000>, /* ap 66 */ +- <0x000b4000 0x000b4000 0x001000>, /* ap 67 */ +- <0x000b5000 0x000b5000 0x001000>, /* ap 68 */ +- <0x000b8000 0x000b8000 0x001000>, /* ap 69 */ +- <0x000b9000 0x000b9000 0x001000>, /* ap 70 */ +- <0x000ba000 0x000ba000 0x001000>, /* ap 71 */ +- <0x000bb000 0x000bb000 0x001000>, /* ap 72 */ +- <0x000d1000 0x000d1000 0x001000>, /* ap 73 */ +- <0x000d2000 0x000d2000 0x001000>, /* ap 74 */ +- <0x000d5000 0x000d5000 0x001000>, /* ap 75 */ +- <0x000d6000 0x000d6000 0x001000>, /* ap 76 */ +- <0x000a2000 0x000a2000 0x001000>, /* ap 79 */ +- <0x000a3000 0x000a3000 0x001000>, /* ap 80 */ +- <0x00001400 0x00001400 0x000400>, /* ap 81 */ +- <0x00001800 0x00001800 0x000400>, /* ap 82 */ +- <0x00001c00 0x00001c00 0x000400>, /* ap 83 */ +- <0x000a5000 0x000a5000 0x001000>; /* ap 84 */ +- +- target-module@20000 { /* 0x48020000, ap 3 06.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x20050 0x4>, +- <0x20054 0x4>, +- <0x20058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_UART3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x20000 0x1000>; +- +- uart3: serial@0 { +- compatible = "ti,omap4-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- }; +- }; +- +- target-module@32000 { /* 0x48032000, ap 5 02.0 */ +- compatible = "ti,sysc-omap2-timer", "ti,sysc"; +- reg = <0x32000 0x4>, +- <0x32010 0x4>, +- <0x32014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x32000 0x1000>; +- +- timer2: timer@0 { +- compatible = "ti,omap3430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>, +- <&sys_clkin_ck>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- }; +- }; +- +- target-module@34000 { /* 0x48034000, ap 7 04.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x34000 0x4>, +- <0x34010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x34000 0x1000>; +- +- timer3: timer@0 { +- compatible = "ti,omap4430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>, +- <&sys_clkin_ck>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- }; +- }; +- +- target-module@36000 { /* 0x48036000, ap 9 0e.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x36000 0x4>, +- <0x36010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x36000 0x1000>; +- +- timer4: timer@0 { +- compatible = "ti,omap4430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>, +- <&sys_clkin_ck>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- }; +- }; +- +- target-module@3e000 { /* 0x4803e000, ap 11 08.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x3e000 0x4>, +- <0x3e010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3e000 0x1000>; +- +- timer9: timer@0 { +- compatible = "ti,omap4430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>, +- <&sys_clkin_ck>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-pwm; +- }; +- }; +- +- /* Unused DSS L4 access, see L3 instead */ +- target-module@40000 { /* 0x48040000, ap 13 0a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x40000 0x10000>; +- }; +- +- target-module@55000 { /* 0x48055000, ap 15 0c.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x55000 0x4>, +- <0x55010 0x4>, +- <0x55114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 0>, +- <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x55000 0x1000>; +- +- gpio2: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@57000 { /* 0x48057000, ap 17 16.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x57000 0x4>, +- <0x57010 0x4>, +- <0x57114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 0>, +- <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x57000 0x1000>; +- +- gpio3: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@59000 { /* 0x48059000, ap 19 10.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x59000 0x4>, +- <0x59010 0x4>, +- <0x59114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 0>, +- <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x59000 0x1000>; +- +- gpio4: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@5b000 { /* 0x4805b000, ap 21 12.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x5b000 0x4>, +- <0x5b010 0x4>, +- <0x5b114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 0>, +- <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5b000 0x1000>; +- +- gpio5: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@5d000 { /* 0x4805d000, ap 23 14.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x5d000 0x4>, +- <0x5d010 0x4>, +- <0x5d114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 0>, +- <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5d000 0x1000>; +- +- gpio6: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@60000 { /* 0x48060000, ap 25 1e.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x60000 0x8>, +- <0x60010 0x8>, +- <0x60090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_I2C3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x60000 0x1000>; +- +- i2c3: i2c@0 { +- compatible = "ti,omap4-i2c"; +- reg = <0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- target-module@6a000 { /* 0x4806a000, ap 26 18.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x6a050 0x4>, +- <0x6a054 0x4>, +- <0x6a058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_UART1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6a000 0x1000>; +- +- uart1: serial@0 { +- compatible = "ti,omap4-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- }; +- }; +- +- target-module@6c000 { /* 0x4806c000, ap 28 20.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x6c050 0x4>, +- <0x6c054 0x4>, +- <0x6c058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_UART2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6c000 0x1000>; +- +- uart2: serial@0 { +- compatible = "ti,omap4-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- }; +- }; +- +- target-module@6e000 { /* 0x4806e000, ap 30 1c.1 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x6e050 0x4>, +- <0x6e054 0x4>, +- <0x6e058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_UART4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6e000 0x1000>; +- +- uart4: serial@0 { +- compatible = "ti,omap4-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- }; +- }; +- +- target-module@70000 { /* 0x48070000, ap 32 28.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x70000 0x8>, +- <0x70010 0x8>, +- <0x70090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_I2C1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x70000 0x1000>; +- +- i2c1: i2c@0 { +- compatible = "ti,omap4-i2c"; +- reg = <0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- target-module@72000 { /* 0x48072000, ap 34 30.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x72000 0x8>, +- <0x72010 0x8>, +- <0x72090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_I2C2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x72000 0x1000>; +- +- i2c2: i2c@0 { +- compatible = "ti,omap4-i2c"; +- reg = <0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- target-module@76000 { /* 0x48076000, ap 39 38.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x76000 0x4>, +- <0x76010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x76000 0x1000>; +- +- /* No child device binding or driver in mainline */ +- }; +- +- target-module@78000 { /* 0x48078000, ap 41 1a.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x78000 0x4>, +- <0x78010 0x4>, +- <0x78014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_ELM_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x78000 0x1000>; +- +- elm: elm@0 { +- compatible = "ti,am3352-elm"; +- reg = <0x0 0x2000>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- target-module@86000 { /* 0x48086000, ap 43 24.0 */ +- compatible = "ti,sysc-omap2-timer", "ti,sysc"; +- reg = <0x86000 0x4>, +- <0x86010 0x4>, +- <0x86014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x86000 0x1000>; +- +- timer10: timer@0 { +- compatible = "ti,omap3430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>, +- <&sys_clkin_ck>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-pwm; +- }; +- }; +- +- target-module@88000 { /* 0x48088000, ap 45 2e.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x88000 0x4>, +- <0x88010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x88000 0x1000>; +- +- timer11: timer@0 { +- compatible = "ti,omap4430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>, +- <&sys_clkin_ck>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-pwm; +- }; +- }; +- +- rng_target: target-module@90000 { /* 0x48090000, ap 57 2a.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x91fe0 0x4>, +- <0x91fe4 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- ; +- /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ +- clocks = <&l4_secure_clkctrl OMAP4_RNG_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x90000 0x2000>; +- +- rng: rng@0 { +- compatible = "ti,omap4-rng"; +- reg = <0x0 0x2000>; +- interrupts = ; +- }; +- }; +- +- target-module@96000 { /* 0x48096000, ap 37 26.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x9608c 0x4>; +- reg-names = "sysc"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x96000 0x1000>; +- +- mcbsp4: mcbsp@0 { +- compatible = "ti,omap4-mcbsp"; +- reg = <0x0 0xff>; /* L4 Interconnect */ +- reg-names = "mpu"; +- interrupts = ; +- interrupt-names = "common"; +- ti,buffer-size = <128>; +- dmas = <&sdma 31>, +- <&sdma 32>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- }; +- +- target-module@98000 { /* 0x48098000, ap 49 22.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x98000 0x4>, +- <0x98010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_MCSPI1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x98000 0x1000>; +- +- mcspi1: spi@0 { +- compatible = "ti,omap4-mcspi"; +- reg = <0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,spi-num-cs = <4>; +- dmas = <&sdma 35>, +- <&sdma 36>, +- <&sdma 37>, +- <&sdma 38>, +- <&sdma 39>, +- <&sdma 40>, +- <&sdma 41>, +- <&sdma 42>; +- dma-names = "tx0", "rx0", "tx1", "rx1", +- "tx2", "rx2", "tx3", "rx3"; +- }; +- }; +- +- target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x9a000 0x4>, +- <0x9a010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_MCSPI2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x9a000 0x1000>; +- +- mcspi2: spi@0 { +- compatible = "ti,omap4-mcspi"; +- reg = <0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,spi-num-cs = <2>; +- dmas = <&sdma 43>, +- <&sdma 44>, +- <&sdma 45>, +- <&sdma 46>; +- dma-names = "tx0", "rx0", "tx1", "rx1"; +- }; +- }; +- +- target-module@9c000 { /* 0x4809c000, ap 53 36.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x9c000 0x4>, +- <0x9c010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ +- clocks = <&l3_init_clkctrl OMAP4_MMC1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x9c000 0x1000>; +- +- mmc1: mmc@0 { +- compatible = "ti,omap4-hsmmc"; +- reg = <0x0 0x400>; +- interrupts = ; +- ti,dual-volt; +- ti,needs-special-reset; +- dmas = <&sdma 61>, <&sdma 62>; +- dma-names = "tx", "rx"; +- pbias-supply = <&pbias_mmc_reg>; +- }; +- }; +- +- target-module@9e000 { /* 0x4809e000, ap 55 48.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x9e000 0x1000>; +- }; +- +- target-module@a2000 { /* 0x480a2000, ap 79 3a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa2000 0x1000>; +- }; +- +- target-module@a4000 { /* 0x480a4000, ap 59 34.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x000a4000 0x00001000>, +- <0x00001000 0x000a5000 0x00001000>; +- }; +- +- des_target: target-module@a5000 { /* 0x480a5000 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xa5030 0x4>, +- <0xa5034 0x4>, +- <0xa5038 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ +- clocks = <&l4_secure_clkctrl OMAP4_DES3DES_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xa5000 0x00001000>; +- +- des: des@0 { +- compatible = "ti,omap4-des"; +- reg = <0 0xa0>; +- interrupts = ; +- dmas = <&sdma 117>, <&sdma 116>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa8000 0x4000>; +- }; +- +- target-module@ad000 { /* 0x480ad000, ap 63 50.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xad000 0x4>, +- <0xad010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_MMC3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xad000 0x1000>; +- +- mmc3: mmc@0 { +- compatible = "ti,omap4-hsmmc"; +- reg = <0x0 0x400>; +- interrupts = ; +- ti,needs-special-reset; +- dmas = <&sdma 77>, <&sdma 78>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@b0000 { /* 0x480b0000, ap 47 40.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xb0000 0x1000>; +- }; +- +- target-module@b2000 { /* 0x480b2000, ap 65 3c.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xb2000 0x4>, +- <0xb2014 0x4>, +- <0xb2018 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,syss-mask = <1>; +- ti,no-reset-on-init; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_HDQ1W_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xb2000 0x1000>; +- +- hdqw1w: 1w@0 { +- compatible = "ti,omap3-1w"; +- reg = <0x0 0x1000>; +- interrupts = ; +- }; +- }; +- +- target-module@b4000 { /* 0x480b4000, ap 67 46.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xb4000 0x4>, +- <0xb4010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ +- clocks = <&l3_init_clkctrl OMAP4_MMC2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xb4000 0x1000>; +- +- mmc2: mmc@0 { +- compatible = "ti,omap4-hsmmc"; +- reg = <0x0 0x400>; +- interrupts = ; +- ti,needs-special-reset; +- dmas = <&sdma 47>, <&sdma 48>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@b8000 { /* 0x480b8000, ap 69 58.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xb8000 0x4>, +- <0xb8010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_MCSPI3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xb8000 0x1000>; +- +- mcspi3: spi@0 { +- compatible = "ti,omap4-mcspi"; +- reg = <0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,spi-num-cs = <2>; +- dmas = <&sdma 15>, <&sdma 16>; +- dma-names = "tx0", "rx0"; +- }; +- }; +- +- target-module@ba000 { /* 0x480ba000, ap 71 32.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xba000 0x4>, +- <0xba010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_MCSPI4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xba000 0x1000>; +- +- mcspi4: spi@0 { +- compatible = "ti,omap4-mcspi"; +- reg = <0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,spi-num-cs = <1>; +- dmas = <&sdma 70>, <&sdma 71>; +- dma-names = "tx0", "rx0"; +- }; +- }; +- +- target-module@d1000 { /* 0x480d1000, ap 73 44.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xd1000 0x4>, +- <0xd1010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_MMC4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xd1000 0x1000>; +- +- mmc4: mmc@0 { +- compatible = "ti,omap4-hsmmc"; +- reg = <0x0 0x400>; +- interrupts = ; +- ti,needs-special-reset; +- dmas = <&sdma 57>, <&sdma 58>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@d5000 { /* 0x480d5000, ap 75 4e.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xd5000 0x4>, +- <0xd5010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_MMC5_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xd5000 0x1000>; +- +- mmc5: mmc@0 { +- compatible = "ti,omap4-hsmmc"; +- reg = <0x0 0x400>; +- interrupts = ; +- ti,needs-special-reset; +- dmas = <&sdma 59>, <&sdma 60>; +- dma-names = "tx", "rx"; +- }; +- }; +- }; +- +- segment@200000 { /* 0x48200000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00150000 0x00350000 0x001000>, /* ap 77 */ +- <0x00151000 0x00351000 0x001000>; /* ap 78 */ +- +- target-module@150000 { /* 0x48350000, ap 77 4c.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x150000 0x8>, +- <0x150010 0x8>, +- <0x150090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ +- clocks = <&l4_per_clkctrl OMAP4_I2C4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x150000 0x1000>; +- +- i2c4: i2c@0 { +- compatible = "ti,omap4-i2c"; +- reg = <0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap4-mcpdm.dtsi b/scripts/dtc/include-prefixes/arm/omap4-mcpdm.dtsi +deleted file mode 100644 +index 915a9b31a33b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-mcpdm.dtsi ++++ /dev/null +@@ -1,44 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Common omap4 mcpdm configuration +- * +- * Only include this file if your board has pdmclk wired from the +- * pmic to ABE as mcpdm uses an external clock for the module. +- */ +- +-&omap4_pmx_core { +- mcpdm_pins: pinmux_mcpdm_pins { +- pinctrl-single,pins = < +- /* 0x4a100106 abe_pdm_ul_data.abe_pdm_ul_data ag25 */ +- OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) +- +- /* 0x4a100108 abe_pdm_dl_data.abe_pdm_dl_data af25 */ +- OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0) +- +- /* 0x4a10010a abe_pdm_frame.abe_pdm_frame ae25 */ +- OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0) +- +- /* 0x4a10010c abe_pdm_lb_clk.abe_pdm_lb_clk af26 */ +- OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0) +- +- /* 0x4a10010e abe_clks.abe_clks ah26 */ +- OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0) +- >; +- }; +-}; +- +-&mcpdm_module { +- /* +- * McPDM pads must be muxed at the interconnect target module +- * level as the module on the SoC needs external clock from +- * the PMIC +- */ +- pinctrl-names = "default"; +- pinctrl-0 = <&mcpdm_pins>; +- status = "okay"; +-}; +- +-&mcpdm { +- clocks = <&twl6040>; +- clock-names = "pdmclk"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap4-panda-a4.dts b/scripts/dtc/include-prefixes/arm/omap4-panda-a4.dts +deleted file mode 100644 +index 8fd076e5d1b0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-panda-a4.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "omap443x.dtsi" +-#include "omap4-panda-common.dtsi" +- +-/* Pandaboard Rev A4+ have external pullups on SCL & SDA */ +-&dss_hdmi_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ +- OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ +- OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ +- >; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap4-panda-common.dtsi b/scripts/dtc/include-prefixes/arm/omap4-panda-common.dtsi +deleted file mode 100644 +index 609a8dea946b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-panda-common.dtsi ++++ /dev/null +@@ -1,607 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2011-2013 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-#include +-#include "elpida_ecb240abacn.dtsi" +-#include "omap4-mcpdm.dtsi" +- +-/ { +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; /* 1 GB */ +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- dsp_memory_region: dsp-memory@98000000 { +- compatible = "shared-dma-pool"; +- reg = <0x98000000 0x800000>; +- reusable; +- status = "okay"; +- }; +- +- ipu_memory_region: ipu-memory@98800000 { +- compatible = "shared-dma-pool"; +- reg = <0x98800000 0x7000000>; +- reusable; +- status = "okay"; +- }; +- }; +- +- chosen { +- stdout-path = &uart3; +- }; +- +- aliases { +- display0 = &dvi0; +- display1 = &hdmi0; +- ethernet = ðernet; +- }; +- +- leds: leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = < +- &led_wkgpio_pins +- >; +- +- heartbeat { +- label = "pandaboard::status1"; +- gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- mmc { +- label = "pandaboard::status2"; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- }; +- }; +- +- gpio_keys: gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = < +- &button_pins +- >; +- +- buttonS2 { +- label = "button S2"; +- gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */ +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- sound: sound { +- compatible = "ti,abe-twl6040"; +- ti,model = "PandaBoard"; +- +- ti,mclk-freq = <38400000>; +- +- ti,mcpdm = <&mcpdm>; +- +- ti,twl6040 = <&twl6040>; +- +- /* Audio routing */ +- ti,audio-routing = +- "Headset Stereophone", "HSOL", +- "Headset Stereophone", "HSOR", +- "Ext Spk", "HFL", +- "Ext Spk", "HFR", +- "Line Out", "AUXL", +- "Line Out", "AUXR", +- "HSMIC", "Headset Mic", +- "Headset Mic", "Headset Mic Bias", +- "AFML", "Line In", +- "AFMR", "Line In"; +- }; +- +- /* HS USB Port 1 Power */ +- hsusb1_power: hsusb1_power_reg { +- compatible = "regulator-fixed"; +- regulator-name = "hsusb1_vbus"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; /* gpio_1 */ +- startup-delay-us = <70000>; +- enable-active-high; +- /* +- * boot-on is required along with always-on as the +- * regulator framework doesn't enable the regulator +- * if boot-on is not there. +- */ +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* HS USB Host PHY on PORT 1 */ +- hsusb1_phy: hsusb1_phy { +- compatible = "usb-nop-xceiv"; +- reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ +- #phy-cells = <0>; +- vcc-supply = <&hsusb1_power>; +- clocks = <&auxclk3_ck>; +- clock-names = "main_clk"; +- clock-frequency = <19200000>; +- }; +- +- /* regulator for wl12xx on sdio5 */ +- wl12xx_vmmc: wl12xx_vmmc { +- pinctrl-names = "default"; +- pinctrl-0 = <&wl12xx_gpio>; +- compatible = "regulator-fixed"; +- regulator-name = "vwl1271"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <70000>; +- enable-active-high; +- }; +- +- tfp410: encoder0 { +- compatible = "ti,tfp410"; +- powerdown-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; /* gpio_0 */ +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tfp410_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- tfp410_out: endpoint { +- remote-endpoint = <&dvi_connector_in>; +- }; +- }; +- }; +- }; +- +- dvi0: connector0 { +- compatible = "dvi-connector"; +- label = "dvi"; +- +- digital; +- +- ddc-i2c-bus = <&i2c3>; +- +- port { +- dvi_connector_in: endpoint { +- remote-endpoint = <&tfp410_out>; +- }; +- }; +- }; +- +- tpd12s015: encoder1 { +- compatible = "ti,tpd12s015"; +- +- gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */ +- <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */ +- <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */ +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tpd12s015_in: endpoint { +- remote-endpoint = <&hdmi_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- tpd12s015_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +- }; +- }; +- }; +- +- hdmi0: connector1 { +- compatible = "hdmi-connector"; +- label = "hdmi"; +- +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&tpd12s015_out>; +- }; +- }; +- }; +-}; +- +-&omap4_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &dss_dpi_pins +- &tfp410_pins +- &dss_hdmi_pins +- &tpd12s015_pins +- &hsusbb1_pins +- >; +- +- twl6040_pins: pinmux_twl6040_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ +- OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ +- >; +- }; +- +- mcbsp1_pins: pinmux_mcbsp1_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ +- OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ +- OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ +- OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ +- >; +- }; +- +- dss_dpi_pins: pinmux_dss_dpi_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */ +- OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */ +- OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */ +- OMAP4_IOPAD(0x168, PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */ +- OMAP4_IOPAD(0x16a, PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */ +- OMAP4_IOPAD(0x16c, PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */ +- OMAP4_IOPAD(0x16e, PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */ +- OMAP4_IOPAD(0x170, PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */ +- OMAP4_IOPAD(0x172, PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */ +- OMAP4_IOPAD(0x174, PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */ +- OMAP4_IOPAD(0x176, PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */ +- +- OMAP4_IOPAD(0x1b4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */ +- OMAP4_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */ +- OMAP4_IOPAD(0x1b8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */ +- OMAP4_IOPAD(0x1ba, PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */ +- OMAP4_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */ +- OMAP4_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */ +- OMAP4_IOPAD(0x1c0, PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */ +- OMAP4_IOPAD(0x1c2, PIN_OUTPUT | MUX_MODE5) /* dispc2_de */ +- OMAP4_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */ +- OMAP4_IOPAD(0x1c6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */ +- OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */ +- OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */ +- OMAP4_IOPAD(0x1cc, PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */ +- OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */ +- +- OMAP4_IOPAD(0x1d0, PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */ +- OMAP4_IOPAD(0x1d2, PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */ +- OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */ +- >; +- }; +- +- tfp410_pins: pinmux_tfp410_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x184, PIN_OUTPUT | MUX_MODE3) /* gpio_0 */ +- >; +- }; +- +- dss_hdmi_pins: pinmux_dss_hdmi_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ +- OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ +- OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ +- >; +- }; +- +- tpd12s015_pins: pinmux_tpd12s015_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */ +- OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */ +- OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ +- >; +- }; +- +- hsusbb1_pins: pinmux_hsusbb1_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ +- OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ +- OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ +- OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ +- OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ +- OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ +- OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ +- OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ +- OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ +- OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ +- OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ +- OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ +- OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ +- >; +- }; +- +- i2c2_pins: pinmux_i2c2_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ +- OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ +- >; +- }; +- +- i2c3_pins: pinmux_i2c3_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ +- OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ +- >; +- }; +- +- i2c4_pins: pinmux_i2c4_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ +- OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ +- >; +- }; +- +- /* +- * wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP +- * REVISIT: Are the pull-ups needed for GPIO 48 and 49? +- */ +- wl12xx_gpio: pinmux_wl12xx_gpio { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ +- OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 */ +- OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48 */ +- OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 */ +- >; +- }; +- +- /* wl12xx GPIO inputs and SDIO pins */ +- wl12xx_pins: pinmux_wl12xx_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */ +- OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ +- OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ +- OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ +- OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ +- OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ +- OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */ +- OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ +- >; +- }; +- +- button_pins: pinmux_button_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_121 */ +- >; +- }; +-}; +- +-&omap4_pmx_wkup { +- led_wkgpio_pins: pinmux_leds_wkpins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */ +- OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */ +- >; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- +- clock-frequency = <400000>; +- +- twl: twl@48 { +- reg = <0x48>; +- /* IRQ# = 7 */ +- interrupts = ; /* IRQ_SYS_1N cascaded to gic */ +- }; +- +- twl6040: twl@4b { +- compatible = "ti,twl6040"; +- #clock-cells = <0>; +- reg = <0x4b>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&twl6040_pins>; +- +- /* IRQ# = 119 */ +- interrupts = ; /* IRQ_SYS_2N cascaded to gic */ +- ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */ +- +- vio-supply = <&v1v8>; +- v2v1-supply = <&v2v1>; +- enable-active-high; +- }; +-}; +- +-#include "twl6030.dtsi" +-#include "twl6030_omap4.dtsi" +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- +- clock-frequency = <400000>; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- +- clock-frequency = <100000>; +- +- /* +- * Display monitor features are burnt in their EEPROM as EDID data. +- * The EEPROM is connected as I2C slave device. +- */ +- eeprom@50 { +- compatible = "ti,eeprom"; +- reg = <0x50>; +- }; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pins>; +- +- clock-frequency = <400000>; +-}; +- +-&mmc1 { +- vmmc-supply = <&vmmc>; +- bus-width = <8>; +-}; +- +-&mmc2 { +- status = "disabled"; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-&mmc4 { +- status = "disabled"; +-}; +- +-&mmc5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&wl12xx_pins>; +- vmmc-supply = <&wl12xx_vmmc>; +- interrupts-extended = <&wakeupgen GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH +- &omap4_pmx_core 0x10e>; +- non-removable; +- bus-width = <4>; +- cap-power-off-card; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1271"; +- reg = <2>; +- /* gpio_53 with gpmc_ncs3 pad as wakeup */ +- interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_HIGH>, +- <&omap4_pmx_core 0x3a>; +- interrupt-names = "irq", "wakeup"; +- ref-clock-frequency = <38400000>; +- }; +-}; +- +-&emif1 { +- cs1-used; +- device-handle = <&elpida_ECB240ABACN>; +-}; +- +-&emif2 { +- cs1-used; +- device-handle = <&elpida_ECB240ABACN>; +-}; +- +-&mcbsp1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp1_pins>; +- status = "okay"; +-}; +- +-&twl_usb_comparator { +- usb-supply = <&vusb>; +-}; +- +-&uart2 { +- interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH +- &omap4_pmx_core OMAP4_UART2_RX>; +-}; +- +-&uart3 { +- interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH +- &omap4_pmx_core OMAP4_UART3_RX>; +-}; +- +-&uart4 { +- interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH +- &omap4_pmx_core OMAP4_UART4_RX>; +-}; +- +-&usb_otg_hs { +- interface-type = <1>; +- mode = <3>; +- power = <50>; +-}; +- +-&usbhshost { +- port1-mode = "ehci-phy"; +-}; +- +-&usbhsehci { +- phys = <&hsusb1_phy>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- hub@1 { +- compatible = "usb424,9514"; +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethernet: usbether@1 { +- compatible = "usb424,ec00"; +- reg = <1>; +- }; +- }; +-}; +- +-&dss { +- status = "okay"; +- +- port { +- dpi_out: endpoint { +- remote-endpoint = <&tfp410_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-&dsi2 { +- status = "okay"; +- vdd-supply = <&vcxio>; +-}; +- +-&hdmi { +- status = "okay"; +- vdda-supply = <&vdac>; +- +- port { +- hdmi_out: endpoint { +- remote-endpoint = <&tpd12s015_in>; +- }; +- }; +-}; +- +-&dsp { +- status = "okay"; +- memory-region = <&dsp_memory_region>; +- ti,timers = <&timer5>; +- ti,watchdog-timers = <&timer6>; +-}; +- +-&ipu { +- status = "okay"; +- memory-region = <&ipu_memory_region>; +- ti,timers = <&timer3>; +- ti,watchdog-timers = <&timer9>, <&timer11>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap4-panda-es.dts b/scripts/dtc/include-prefixes/arm/omap4-panda-es.dts +deleted file mode 100644 +index 7c6886cd738f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-panda-es.dts ++++ /dev/null +@@ -1,114 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "omap4460.dtsi" +-#include "omap4-panda-common.dtsi" +- +-/ { +- model = "TI OMAP4 PandaBoard-ES"; +- compatible = "ti,omap4-panda-es", "ti,omap4-panda", "ti,omap4460", "ti,omap4430", "ti,omap4"; +-}; +- +-/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */ +-&sound { +- ti,model = "PandaBoardES"; +- +- /* Audio routing */ +- ti,audio-routing = +- "Headset Stereophone", "HSOL", +- "Headset Stereophone", "HSOR", +- "Ext Spk", "HFL", +- "Ext Spk", "HFR", +- "Line Out", "AUXL", +- "Line Out", "AUXR", +- "AFML", "Line In", +- "AFMR", "Line In"; +-}; +- +-/* PandaboardES has external pullups on SCL & SDA */ +-&dss_hdmi_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ +- OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ +- OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ +- >; +-}; +- +-&omap4_pmx_core { +- led_gpio_pins: gpio_led_pmx { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x0f6, PIN_OUTPUT | MUX_MODE3) /* gpio_110 */ +- >; +- }; +- +- button_pins: pinmux_button_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x0fc, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */ +- >; +- }; +- +- bt_pins: pinmux_bt_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 - BTEN */ +- OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 - BTWAKEUP */ +- >; +- }; +- +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts - HCI */ +- OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ +- OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ +- OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ +- >; +- }; +-}; +- +-&led_wkgpio_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */ +- >; +-}; +- +-&leds { +- pinctrl-0 = < +- &led_gpio_pins +- &led_wkgpio_pins +- >; +- +- heartbeat { +- gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; +- }; +- mmc { +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&gpio_keys { +- buttonS2 { +- gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* gpio_113 */ +- }; +-}; +- +-&gpio1_target { +- ti,no-reset-on-init; +-}; +- +-&wl12xx_gpio { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ +- OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48 */ +- >; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins &bt_pins>; +- bluetooth: tiwi { +- compatible = "ti,wl1271-st"; +- enable-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* GPIO_46 */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap4-panda.dts b/scripts/dtc/include-prefixes/arm/omap4-panda.dts +deleted file mode 100644 +index 529d5bcceaaf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-panda.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "omap443x.dtsi" +-#include "omap4-panda-common.dtsi" +- +-/ { +- model = "TI OMAP4 PandaBoard"; +- compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap4-sdp-es23plus.dts b/scripts/dtc/include-prefixes/arm/omap4-sdp-es23plus.dts +deleted file mode 100644 +index 869f6279b5be..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-sdp-es23plus.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-#include "omap4-sdp.dts" +- +-/* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */ +-&dss_hdmi_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ +- OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ +- OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ +- >; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap4-sdp.dts b/scripts/dtc/include-prefixes/arm/omap4-sdp.dts +deleted file mode 100644 +index 9e976140f34a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-sdp.dts ++++ /dev/null +@@ -1,717 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "omap443x.dtsi" +-#include "elpida_ecb240abacn.dtsi" +-#include "omap4-mcpdm.dtsi" +- +-/ { +- model = "TI OMAP4 SDP board"; +- compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; /* 1 GB */ +- }; +- +- aliases { +- display0 = &lcd0; +- display1 = &lcd1; +- display2 = &hdmi0; +- }; +- +- vdd_eth: fixedregulator-vdd-eth { +- pinctrl-names = "default"; +- pinctrl-0 = <&enet_enable_gpio>; +- +- compatible = "regulator-fixed"; +- regulator-name = "VDD_ETH"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; /* gpio line 48 */ +- enable-active-high; +- regulator-boot-on; +- startup-delay-us = <25000>; +- }; +- +- vbat: fixedregulator-vbat { +- compatible = "regulator-fixed"; +- regulator-name = "VBAT"; +- regulator-min-microvolt = <3750000>; +- regulator-max-microvolt = <3750000>; +- regulator-boot-on; +- }; +- +- led-controller-1 { +- compatible = "gpio-leds"; +- +- led-1 { +- label = "omap4:green:debug0"; +- gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */ +- }; +- +- led-2 { +- label = "omap4:green:debug1"; +- gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */ +- }; +- +- led-3 { +- label = "omap4:green:debug2"; +- gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */ +- }; +- +- led-4 { +- label = "omap4:green:debug3"; +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */ +- }; +- +- led-5 { +- label = "omap4:green:debug4"; +- gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */ +- }; +- +- led-6 { +- label = "omap4:blue:user"; +- gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */ +- }; +- +- led-7 { +- label = "omap4:red:user"; +- gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */ +- }; +- +- led-8 { +- label = "omap4:green:user"; +- gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */ +- }; +- }; +- +- led-controller-2 { +- compatible = "pwm-leds"; +- +- led-9 { +- label = "omap4::keypad"; +- pwms = <&twl_pwm 0 7812500>; +- max-brightness = <127>; +- }; +- +- led-10 { +- label = "omap4:green:chrg"; +- pwms = <&twl_pwmled 0 7812500>; +- max-brightness = <255>; +- }; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&twl_pwm 1 7812500>; +- brightness-levels = < +- 0 10 20 30 40 +- 50 60 70 80 90 +- 100 110 120 127 +- >; +- default-brightness-level = <13>; +- }; +- +- sound { +- compatible = "ti,abe-twl6040"; +- ti,model = "SDP4430"; +- +- ti,jack-detection = <1>; +- ti,mclk-freq = <38400000>; +- +- ti,mcpdm = <&mcpdm>; +- ti,dmic = <&dmic>; +- +- ti,twl6040 = <&twl6040>; +- +- /* Audio routing */ +- ti,audio-routing = +- "Headset Stereophone", "HSOL", +- "Headset Stereophone", "HSOR", +- "Earphone Spk", "EP", +- "Ext Spk", "HFL", +- "Ext Spk", "HFR", +- "Line Out", "AUXL", +- "Line Out", "AUXR", +- "Vibrator", "VIBRAL", +- "Vibrator", "VIBRAR", +- "HSMIC", "Headset Mic", +- "Headset Mic", "Headset Mic Bias", +- "MAINMIC", "Main Handset Mic", +- "Main Handset Mic", "Main Mic Bias", +- "SUBMIC", "Sub Handset Mic", +- "Sub Handset Mic", "Main Mic Bias", +- "AFML", "Line In", +- "AFMR", "Line In", +- "DMic", "Digital Mic", +- "Digital Mic", "Digital Mic1 Bias"; +- }; +- +- /* regulator for wl12xx on sdio5 */ +- wl12xx_vmmc: wl12xx_vmmc { +- pinctrl-names = "default"; +- pinctrl-0 = <&wl12xx_gpio>; +- compatible = "regulator-fixed"; +- regulator-name = "vwl1271"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <70000>; +- enable-active-high; +- }; +- +- tpd12s015: encoder { +- compatible = "ti,tpd12s015"; +- +- gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */ +- <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */ +- <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */ +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tpd12s015_in: endpoint { +- remote-endpoint = <&hdmi_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- tpd12s015_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +- }; +- }; +- }; +- +- hdmi0: connector { +- compatible = "hdmi-connector"; +- label = "hdmi"; +- +- type = "c"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&tpd12s015_out>; +- }; +- }; +- }; +-}; +- +-&omap4_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &dss_hdmi_pins +- &tpd12s015_pins +- >; +- +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ +- OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ +- OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ +- OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ +- >; +- }; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ +- OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ +- OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ +- OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ +- >; +- }; +- +- uart4_pins: pinmux_uart4_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx.uart4_rx */ +- OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx.uart4_tx */ +- >; +- }; +- +- twl6040_pins: pinmux_twl6040_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ +- OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ +- >; +- }; +- +- dmic_pins: pinmux_dmic_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x110, PIN_OUTPUT | MUX_MODE0) /* abe_dmic_clk1.abe_dmic_clk1 */ +- OMAP4_IOPAD(0x112, PIN_INPUT | MUX_MODE0) /* abe_dmic_din1.abe_dmic_din1 */ +- OMAP4_IOPAD(0x114, PIN_INPUT | MUX_MODE0) /* abe_dmic_din2.abe_dmic_din2 */ +- OMAP4_IOPAD(0x116, PIN_INPUT | MUX_MODE0) /* abe_dmic_din3.abe_dmic_din3 */ +- >; +- }; +- +- mcbsp1_pins: pinmux_mcbsp1_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ +- OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ +- OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ +- OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ +- >; +- }; +- +- mcbsp2_pins: pinmux_mcbsp2_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx.abe_mcbsp2_clkx */ +- OMAP4_IOPAD(0x0f8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dr.abe_mcbsp2_dr */ +- OMAP4_IOPAD(0x0fa, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dx.abe_mcbsp2_dx */ +- OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx.abe_mcbsp2_fsx */ +- >; +- }; +- +- mcspi1_pins: pinmux_mcspi1_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ +- OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ +- OMAP4_IOPAD(0x136, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ +- OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ +- >; +- }; +- +- dss_hdmi_pins: pinmux_dss_hdmi_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ +- OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ +- OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ +- >; +- }; +- +- tpd12s015_pins: pinmux_tpd12s015_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */ +- OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */ +- OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ +- OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ +- >; +- }; +- +- i2c2_pins: pinmux_i2c2_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ +- OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ +- >; +- }; +- +- i2c3_pins: pinmux_i2c3_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ +- OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ +- >; +- }; +- +- i2c4_pins: pinmux_i2c4_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ +- OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ +- >; +- }; +- +- /* wl12xx GPIO output for WLAN_EN */ +- wl12xx_gpio: pinmux_wl12xx_gpio { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3) /* gpmc_nwp.gpio_54 */ +- >; +- }; +- +- /* wl12xx GPIO inputs and SDIO pins */ +- wl12xx_pins: pinmux_wl12xx_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ +- OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ +- OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ +- OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ +- OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ +- OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */ +- OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ +- >; +- }; +- +- /* gpio_48 for ENET_ENABLE */ +- enet_enable_gpio: pinmux_enet_enable_gpio { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a24.gpio_48 */ +- >; +- }; +- +- ks8851_pins: pinmux_ks8851_pins { +- pinctrl-single,pins = < +- /* ENET_INT */ +- OMAP4_IOPAD(0x054, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad10.gpio_34 */ +- /* +- * Misterious pin which makes the ethernet working +- * The legacy board file requested this pin on boot +- * (ETH_KS8851_QUART) and set it to high, similarly to +- * the ENET_ENABLE pin. +- * We could use gpio-hog to keep it high, but let's use +- * it as a reset GPIO for ks8851. +- */ +- OMAP4_IOPAD(0x13a, PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.gpio_138 */ +- >; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- +- clock-frequency = <400000>; +- +- twl: twl@48 { +- reg = <0x48>; +- /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ +- interrupts = ; /* IRQ_SYS_1N cascaded to gic */ +- }; +- +- twl6040: twl@4b { +- compatible = "ti,twl6040"; +- #clock-cells = <0>; +- reg = <0x4b>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&twl6040_pins>; +- +- /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ +- interrupts = ; /* IRQ_SYS_2N cascaded to gic */ +- ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */ +- +- vio-supply = <&v1v8>; +- v2v1-supply = <&v2v1>; +- enable-active-high; +- +- /* regulators for vibra motor */ +- vddvibl-supply = <&vbat>; +- vddvibr-supply = <&vbat>; +- +- vibra { +- /* Vibra driver, motor resistance parameters */ +- ti,vibldrv-res = <8>; +- ti,vibrdrv-res = <3>; +- ti,viblmotor-res = <10>; +- ti,vibrmotor-res = <10>; +- }; +- }; +-}; +- +-#include "twl6030.dtsi" +-#include "twl6030_omap4.dtsi" +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- +- clock-frequency = <400000>; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- +- clock-frequency = <400000>; +- +- /* +- * Temperature Sensor +- * https://www.ti.com/lit/ds/symlink/tmp105.pdf +- */ +- tmp105@48 { +- compatible = "ti,tmp105"; +- reg = <0x48>; +- }; +- +- /* +- * Ambient Light Sensor +- * http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf +- */ +- bh1780@29 { +- compatible = "rohm,bh1780"; +- reg = <0x29>; +- }; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pins>; +- +- clock-frequency = <400000>; +- +- /* +- * 3-Axis Digital Compass +- * https://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf +- */ +- hmc5843@1e { +- compatible = "honeywell,hmc5843"; +- reg = <0x1e>; +- }; +-}; +- +-&mcspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcspi1_pins>; +- +- eth@0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ks8851_pins>; +- +- compatible = "ks8851"; +- spi-max-frequency = <24000000>; +- reg = <0>; +- interrupt-parent = <&gpio2>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34 */ +- vdd-supply = <&vdd_eth>; +- reset-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&mmc1 { +- vmmc-supply = <&vmmc>; +- bus-width = <8>; +-}; +- +-&mmc2 { +- vmmc-supply = <&vaux1>; +- bus-width = <8>; +- ti,non-removable; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-&mmc4 { +- status = "disabled"; +-}; +- +-&mmc5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&wl12xx_pins>; +- vmmc-supply = <&wl12xx_vmmc>; +- non-removable; +- bus-width = <4>; +- cap-power-off-card; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1281"; +- reg = <2>; +- interrupt-parent = <&gpio1>; +- interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */ +- ref-clock-frequency = <26000000>; +- tcxo-clock-frequency = <26000000>; +- }; +-}; +- +-&emif1 { +- cs1-used; +- device-handle = <&elpida_ECB240ABACN>; +-}; +- +-&emif2 { +- cs1-used; +- device-handle = <&elpida_ECB240ABACN>; +-}; +- +-&keypad { +- keypad,num-rows = <8>; +- keypad,num-columns = <8>; +- linux,keymap = <0x00000012 /* KEY_E */ +- 0x00010013 /* KEY_R */ +- 0x00020014 /* KEY_T */ +- 0x00030066 /* KEY_HOME */ +- 0x0004003f /* KEY_F5 */ +- 0x000500f0 /* KEY_UNKNOWN */ +- 0x00060017 /* KEY_I */ +- 0x0007002a /* KEY_LEFTSHIFT */ +- 0x01000020 /* KEY_D*/ +- 0x01010021 /* KEY_F */ +- 0x01020022 /* KEY_G */ +- 0x010300e7 /* KEY_SEND */ +- 0x01040040 /* KEY_F6 */ +- 0x010500f0 /* KEY_UNKNOWN */ +- 0x01060025 /* KEY_K */ +- 0x0107001c /* KEY_ENTER */ +- 0x0200002d /* KEY_X */ +- 0x0201002e /* KEY_C */ +- 0x0202002f /* KEY_V */ +- 0x0203006b /* KEY_END */ +- 0x02040041 /* KEY_F7 */ +- 0x020500f0 /* KEY_UNKNOWN */ +- 0x02060034 /* KEY_DOT */ +- 0x0207003a /* KEY_CAPSLOCK */ +- 0x0300002c /* KEY_Z */ +- 0x0301004e /* KEY_KPLUS */ +- 0x03020030 /* KEY_B */ +- 0x0303003b /* KEY_F1 */ +- 0x03040042 /* KEY_F8 */ +- 0x030500f0 /* KEY_UNKNOWN */ +- 0x03060018 /* KEY_O */ +- 0x03070039 /* KEY_SPACE */ +- 0x04000011 /* KEY_W */ +- 0x04010015 /* KEY_Y */ +- 0x04020016 /* KEY_U */ +- 0x0403003c /* KEY_F2 */ +- 0x04040073 /* KEY_VOLUMEUP */ +- 0x040500f0 /* KEY_UNKNOWN */ +- 0x04060026 /* KEY_L */ +- 0x04070069 /* KEY_LEFT */ +- 0x0500001f /* KEY_S */ +- 0x05010023 /* KEY_H */ +- 0x05020024 /* KEY_J */ +- 0x0503003d /* KEY_F3 */ +- 0x05040043 /* KEY_F9 */ +- 0x05050072 /* KEY_VOLUMEDOWN */ +- 0x05060032 /* KEY_M */ +- 0x0507006a /* KEY_RIGHT */ +- 0x06000010 /* KEY_Q */ +- 0x0601001e /* KEY_A */ +- 0x06020031 /* KEY_N */ +- 0x0603009e /* KEY_BACK */ +- 0x0604000e /* KEY_BACKSPACE */ +- 0x060500f0 /* KEY_UNKNOWN */ +- 0x06060019 /* KEY_P */ +- 0x06070067 /* KEY_UP */ +- 0x07000094 /* KEY_PROG1 */ +- 0x07010095 /* KEY_PROG2 */ +- 0x070200ca /* KEY_PROG3 */ +- 0x070300cb /* KEY_PROG4 */ +- 0x0704003e /* KEY_F4 */ +- 0x070500f0 /* KEY_UNKNOWN */ +- 0x07060160 /* KEY_OK */ +- 0x0707006c>; /* KEY_DOWN */ +- linux,input-no-autorepeat; +-}; +- +-&uart2 { +- interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH +- &omap4_pmx_core OMAP4_UART2_RX>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +-}; +- +-&uart3 { +- interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH +- &omap4_pmx_core OMAP4_UART3_RX>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +-}; +- +-&uart4 { +- interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH +- &omap4_pmx_core OMAP4_UART4_RX>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pins>; +-}; +- +-&mcbsp1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp1_pins>; +- status = "okay"; +-}; +- +-&mcbsp2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp2_pins>; +- status = "okay"; +-}; +- +-&dmic { +- pinctrl-names = "default"; +- pinctrl-0 = <&dmic_pins>; +- status = "okay"; +-}; +- +-&twl_usb_comparator { +- usb-supply = <&vusb>; +-}; +- +-&usb_otg_hs { +- interface-type = <1>; +- mode = <3>; +- power = <50>; +-}; +- +-&dss { +- status = "okay"; +-}; +- +-&dsi1 { +- status = "okay"; +- vdd-supply = <&vcxio>; +- +- port { +- dsi1_out_ep: endpoint { +- remote-endpoint = <&lcd0_in>; +- lanes = <0 1 2 3 4 5>; +- }; +- }; +- +- lcd0: panel@0 { +- compatible = "tpo,taal", "panel-dsi-cm"; +- reg = <0>; +- label = "lcd0"; +- +- reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ +- +- port { +- lcd0_in: endpoint { +- remote-endpoint = <&dsi1_out_ep>; +- }; +- }; +- }; +-}; +- +-&dsi2 { +- status = "okay"; +- vdd-supply = <&vcxio>; +- +- port { +- dsi2_out_ep: endpoint { +- remote-endpoint = <&lcd1_in>; +- lanes = <0 1 2 3 4 5>; +- }; +- }; +- +- lcd1: panel@0 { +- compatible = "tpo,taal", "panel-dsi-cm"; +- reg = <0>; +- label = "lcd1"; +- +- reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */ +- +- port { +- lcd1_in: endpoint { +- remote-endpoint = <&dsi2_out_ep>; +- }; +- }; +- }; +-}; +- +-&hdmi { +- status = "okay"; +- vdda-supply = <&vdac>; +- +- port { +- hdmi_out: endpoint { +- remote-endpoint = <&tpd12s015_in>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap4-var-dvk-om44.dts b/scripts/dtc/include-prefixes/arm/omap4-var-dvk-om44.dts +deleted file mode 100644 +index 84fd17fb0822..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-var-dvk-om44.dts ++++ /dev/null +@@ -1,68 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Joachim Eastwood +- */ +-/dts-v1/; +- +-#include "omap4-var-som-om44.dtsi" +-#include "omap4-var-som-om44-wlan.dtsi" +-#include "omap4-var-om44customboard.dtsi" +- +-/ { +- model = "Variscite VAR-DVK-OM44"; +- compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; +- +- aliases { +- display0 = &lcd0; +- display1 = &hdmi0; +- }; +- +- lcd0: display { +- compatible = "innolux,at070tn83", "panel-dpi"; +- label = "lcd"; +- panel-timing { +- clock-frequency = <33333333>; +- +- hback-porch = <40>; +- hactive = <800>; +- hfront-porch = <40>; +- hsync-len = <48>; +- +- vback-porch = <29>; +- vactive = <480>; +- vfront-porch = <13>; +- vsync-len = <3>; +- }; +- +- port { +- lcd_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- }; +- +- backlight { +- compatible = "gpio-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&backlight_pins>; +- +- gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio 122 */ +- }; +-}; +- +-&dss { +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_dpi_pins>; +- +- port { +- dpi_out: endpoint { +- remote-endpoint = <&lcd_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-&dsi2 { +- status = "okay"; +- vdd-supply = <&vcxio>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap4-var-om44customboard.dtsi b/scripts/dtc/include-prefixes/arm/omap4-var-om44customboard.dtsi +deleted file mode 100644 +index 458cb53dd3d1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-var-om44customboard.dtsi ++++ /dev/null +@@ -1,232 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Joachim Eastwood +- */ +- +-#include +- +-/ { +- aliases { +- display0 = &hdmi0; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_led_pins>; +- +- led0 { +- label = "var:green:led0"; +- gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio 173 */ +- linux,default-trigger = "heartbeat"; +- }; +- +- led1 { +- label = "var:green:led1"; +- gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; /* gpio 172 */ +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_key_pins>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- user-key@184 { +- label = "user"; +- gpios = <&gpio6 24 GPIO_ACTIVE_HIGH>; /* gpio 184 */ +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- hdmi0: connector { +- compatible = "hdmi-connector"; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_hpd_pins>; +- label = "hdmi"; +- type = "a"; +- +- hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio_63 */ +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_out>; +- }; +- }; +- }; +-}; +- +-&omap4_pmx_core { +- uart1_pins: pinmux_uart1_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi1_cs2.uart1_cts */ +- OMAP4_IOPAD(0x13e, PIN_OUTPUT | MUX_MODE1) /* mcspi1_cs3.uart1_rts */ +- OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE1) /* i2c2_scl.uart1_rx */ +- OMAP4_IOPAD(0x128, PIN_OUTPUT | MUX_MODE1) /* i2c2_sda.uart1_tx */ +- >; +- }; +- +- mcspi1_pins: pinmux_mcspi1_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ +- OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ +- OMAP4_IOPAD(0x136, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ +- OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ +- >; +- }; +- +- mcasp_pins: pinmux_mcsasp_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x0f8, PIN_OUTPUT | MUX_MODE2) /* mcbsp2_dr.abe_mcasp_axr */ +- >; +- }; +- +- dss_dpi_pins: pinmux_dss_dpi_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */ +- OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */ +- OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */ +- OMAP4_IOPAD(0x168, PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */ +- OMAP4_IOPAD(0x16a, PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */ +- OMAP4_IOPAD(0x16c, PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */ +- OMAP4_IOPAD(0x16e, PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */ +- OMAP4_IOPAD(0x170, PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */ +- OMAP4_IOPAD(0x172, PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */ +- OMAP4_IOPAD(0x174, PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */ +- OMAP4_IOPAD(0x176, PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */ +- OMAP4_IOPAD(0x1b4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */ +- OMAP4_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */ +- OMAP4_IOPAD(0x1b8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */ +- OMAP4_IOPAD(0x1ba, PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */ +- OMAP4_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */ +- OMAP4_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */ +- OMAP4_IOPAD(0x1c0, PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */ +- OMAP4_IOPAD(0x1c2, PIN_OUTPUT | MUX_MODE5) /* dispc2_de */ +- OMAP4_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */ +- OMAP4_IOPAD(0x1c6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */ +- OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */ +- OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */ +- OMAP4_IOPAD(0x1cc, PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */ +- OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */ +- OMAP4_IOPAD(0x1d0, PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */ +- OMAP4_IOPAD(0x1d2, PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */ +- OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */ +- >; +- }; +- +- dss_hdmi_pins: pinmux_dss_hdmi_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ +- OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ +- OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ +- >; +- }; +- +- i2c4_pins: pinmux_i2c4_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ +- OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ +- >; +- }; +- +- mmc5_pins: pinmux_mmc5_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE3) /* abe_mcbsp2_clkx.gpio_110 */ +- OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ +- OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ +- OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ +- OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ +- OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */ +- OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ +- >; +- }; +- +- gpio_led_pins: pinmux_gpio_led_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x17e, PIN_OUTPUT | MUX_MODE3) /* kpd_col4.gpio_172 */ +- OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3) /* kpd_col5.gpio_173 */ +- >; +- }; +- +- gpio_key_pins: pinmux_gpio_key_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x1a2, PIN_INPUT | MUX_MODE3) /* sys_boot0.gpio_184 */ +- >; +- }; +- +- ks8851_irq_pins: pinmux_ks8851_irq_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x17c, PIN_INPUT_PULLUP | MUX_MODE3) /* kpd_col3.gpio_171 */ +- >; +- }; +- +- hdmi_hpd_pins: pinmux_hdmi_hpd_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ +- >; +- }; +- +- backlight_pins: pinmux_backlight_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ +- >; +- }; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pins>; +- clock-frequency = <400000>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- status = "okay"; +-}; +- +-&mcspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcspi1_pins>; +- status = "okay"; +- +- eth@0 { +- compatible = "ks8851"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ks8851_irq_pins>; +- spi-max-frequency = <24000000>; +- reg = <0>; +- interrupt-parent = <&gpio6>; +- interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio 171 */ +- }; +-}; +- +-&mmc5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc5_pins>; +- vmmc-supply = <&vbat>; +- bus-width = <4>; +- cd-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; /* gpio 110 */ +- status = "okay"; +-}; +- +-&dss { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_hdmi_pins>; +- vdda-supply = <&vdac>; +- +- port { +- hdmi_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap4-var-som-om44-wlan.dtsi b/scripts/dtc/include-prefixes/arm/omap4-var-som-om44-wlan.dtsi +deleted file mode 100644 +index d0032213101e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-var-som-om44-wlan.dtsi ++++ /dev/null +@@ -1,75 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Joachim Eastwood +- */ +- +-/ { +- /* regulator for wl12xx on sdio4 */ +- wl12xx_vmmc: wl12xx_vmmc { +- pinctrl-names = "default"; +- pinctrl-0 = <&wl12xx_ctrl_pins>; +- compatible = "regulator-fixed"; +- regulator-name = "vwl1271"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* gpio 43 */ +- startup-delay-us = <70000>; +- enable-active-high; +- }; +-}; +- +-&omap4_pmx_core { +- uart2_pins: pinmux_uart2_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ +- OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ +- OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ +- OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ +- >; +- }; +- +- wl12xx_ctrl_pins: pinmux_wl12xx_ctrl_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x062, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a17.gpio_41 (WLAN_IRQ) */ +- OMAP4_IOPAD(0x064, PIN_OUTPUT | MUX_MODE3) /* gpmc_a18.gpio_42 (BT_EN) */ +- OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 (WLAN_EN) */ +- >; +- }; +- +- mmc4_pins: pinmux_mmc4_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x154, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_clk.sdmmc4_clk */ +- OMAP4_IOPAD(0x156, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_simo.sdmmc4_cmd */ +- OMAP4_IOPAD(0x158, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_somi.sdmmc4_dat0 */ +- OMAP4_IOPAD(0x15e, PIN_INPUT_PULLUP | MUX_MODE1) /* uart4_tx.sdmmc4_dat1 */ +- OMAP4_IOPAD(0x15c, PIN_INPUT_PULLUP | MUX_MODE1) /* uart4_rx.sdmmc4_dat2 */ +- OMAP4_IOPAD(0x15a, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_cs0.sdmmc4_dat3 */ +- >; +- }; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "okay"; +-}; +- +-&mmc4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc4_pins>; +- vmmc-supply = <&wl12xx_vmmc>; +- non-removable; +- bus-width = <4>; +- cap-power-off-card; +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1271"; +- reg = <2>; +- interrupt-parent = <&gpio2>; +- interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */ +- ref-clock-frequency = <38400000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap4-var-som-om44.dtsi b/scripts/dtc/include-prefixes/arm/omap4-var-som-om44.dtsi +deleted file mode 100644 +index 334cbbaa5b8b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-var-som-om44.dtsi ++++ /dev/null +@@ -1,325 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Joachim Eastwood +- * Copyright (C) 2012 Variscite Ltd. - https://www.variscite.com +- */ +-#include "omap4460.dtsi" +-#include "omap4-mcpdm.dtsi" +- +-/ { +- model = "Variscite VAR-SOM-OM44"; +- compatible = "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; /* 1 GB */ +- }; +- +- sound: sound { +- compatible = "ti,abe-twl6040"; +- ti,model = "VAR-SOM-OM44"; +- +- ti,mclk-freq = <38400000>; +- ti,mcpdm = <&mcpdm>; +- ti,twl6040 = <&twl6040>; +- +- /* Audio routing */ +- ti,audio-routing = +- "Headset Stereophone", "HSOL", +- "Headset Stereophone", "HSOR", +- "AFML", "Line In", +- "AFMR", "Line In"; +- }; +- +- /* HS USB Host PHY on PORT 1 */ +- hsusb1_phy: hsusb1_phy { +- compatible = "usb-nop-xceiv"; +- pinctrl-names = "default"; +- pinctrl-0 = < +- &hsusbb1_phy_clk_pins +- &hsusbb1_phy_rst_pins +- >; +- +- reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; /* gpio 177 */ +- vcc-supply = <&vbat>; +- #phy-cells = <0>; +- +- clocks = <&auxclk3_ck>; +- clock-names = "main_clk"; +- clock-frequency = <19200000>; +- }; +- +- vbat: fixedregulator-vbat { +- compatible = "regulator-fixed"; +- regulator-name = "VBAT"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&omap4_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &hsusbb1_pins +- >; +- +- twl6040_pins: pinmux_twl6040_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x19c, PIN_OUTPUT | MUX_MODE3) /* fref_clk2_out.gpio_182 */ +- OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ +- >; +- }; +- +- tsc2004_pins: pinmux_tsc2004_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x090, PIN_INPUT | MUX_MODE3) /* gpmc_ncs4.gpio_101 (irq) */ +- OMAP4_IOPAD(0x092, PIN_OUTPUT | MUX_MODE3) /* gpmc_ncs5.gpio_102 (rst) */ +- >; +- }; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ +- OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ +- OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ +- OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ +- >; +- }; +- +- hsusbb1_pins: pinmux_hsusbb1_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ +- OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ +- OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ +- OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ +- OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ +- OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ +- OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ +- OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ +- OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ +- OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ +- OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ +- OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ +- >; +- }; +- +- hsusbb1_phy_rst_pins: pinmux_hsusbb1_phy_rst_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x18c, PIN_OUTPUT | MUX_MODE3) /* kpd_row2.gpio_177 */ +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ +- OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ +- >; +- }; +- +- i2c3_pins: pinmux_i2c3_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ +- OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ +- OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ +- OMAP4_IOPAD(0x0e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ +- OMAP4_IOPAD(0x0e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ +- OMAP4_IOPAD(0x0ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ +- OMAP4_IOPAD(0x0ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ +- >; +- }; +-}; +- +-&omap4_pmx_wkup { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &hsusbb1_hub_rst_pins +- &lan7500_rst_pins +- >; +- +- hsusbb1_phy_clk_pins: pinmux_hsusbb1_phy_clk_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x058, PIN_OUTPUT | MUX_MODE0) /* fref_clk3_out */ +- >; +- }; +- +- hsusbb1_hub_rst_pins: pinmux_hsusbb1_hub_rst_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x042, PIN_OUTPUT | MUX_MODE3) /* gpio_wk1 */ +- >; +- }; +- +- lan7500_rst_pins: pinmux_lan7500_rst_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x040, PIN_OUTPUT | MUX_MODE3) /* gpio_wk0 */ +- >; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "okay"; +- +- clock-frequency = <400000>; +- +- twl: twl@48 { +- reg = <0x48>; +- /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ +- interrupts = ; /* IRQ_SYS_1N cascaded to gic */ +- }; +- +- twl6040: twl@4b { +- compatible = "ti,twl6040"; +- #clock-cells = <0>; +- reg = <0x4b>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&twl6040_pins>; +- +- /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ +- interrupts = ; /* IRQ_SYS_2N cascaded to gic */ +- ti,audpwron-gpio = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* gpio 182 */ +- +- vio-supply = <&v1v8>; +- v2v1-supply = <&v2v1>; +- enable-active-high; +- }; +-}; +- +-#include "twl6030.dtsi" +-#include "twl6030_omap4.dtsi" +- +-&vusim { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +-}; +- +-&i2c2 { +- status = "disabled"; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- status = "okay"; +- +- clock-frequency = <400000>; +- +- touchscreen: tsc2004@48 { +- compatible = "ti,tsc2004"; +- reg = <0x48>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsc2004_pins>; +- interrupt-parent = <&gpio4>; +- interrupts = <5 IRQ_TYPE_LEVEL_LOW>; /* gpio 101 */ +- status = "disabled"; +- }; +- +- tmp105@49 { +- compatible = "ti,tmp105"; +- reg = <0x49>; +- }; +- +- eeprom@50 { +- compatible = "microchip,24c32", "atmel,24c32"; +- reg = <0x50>; +- }; +-}; +- +-&i2c4 { +- status = "disabled"; +-}; +- +-&gpmc { +- status = "disabled"; +-}; +- +-&mcspi1 { +- status = "disabled"; +-}; +- +-&mcspi2 { +- status = "disabled"; +-}; +- +-&mcspi3 { +- status = "disabled"; +-}; +- +-&mcspi4 { +- status = "disabled"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <&vmmc>; +- bus-width = <4>; +- ti,non-removable; +- status = "okay"; +-}; +- +-&mmc2 { +- status = "disabled"; +-}; +- +-&mmc3 { +- status = "disabled"; +-}; +- +-&mmc4 { +- status = "disabled"; +-}; +- +-&mmc5 { +- status = "disabled"; +-}; +- +-&uart1 { +- status = "disabled"; +-}; +- +-&uart2 { +- status = "disabled"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- status = "okay"; +-}; +- +-&uart4 { +- status = "disabled"; +-}; +- +-&keypad { +- status = "disabled"; +-}; +- +-&twl_usb_comparator { +- usb-supply = <&vusb>; +-}; +- +-&usb_otg_hs { +- interface-type = <1>; +- mode = <3>; +- power = <50>; +-}; +- +-&usbhshost { +- port1-mode = "ehci-phy"; +-}; +- +-&usbhsehci { +- phys = <&hsusb1_phy>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap4-var-stk-om44.dts b/scripts/dtc/include-prefixes/arm/omap4-var-stk-om44.dts +deleted file mode 100644 +index 656fb29c2a15..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4-var-stk-om44.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 Joachim Eastwood +- */ +-/dts-v1/; +- +-#include "omap4-var-som-om44.dtsi" +-#include "omap4-var-som-om44-wlan.dtsi" +-#include "omap4-var-om44customboard.dtsi" +- +-/ { +- model = "Variscite VAR-STK-OM44"; +- compatible = "variscite,var-stk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap4.dtsi b/scripts/dtc/include-prefixes/arm/omap4.dtsi +deleted file mode 100644 +index 2bbff9032be3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4.dtsi ++++ /dev/null +@@ -1,868 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "ti,omap4430", "ti,omap4"; +- interrupt-parent = <&wakeupgen>; +- #address-cells = <1>; +- #size-cells = <1>; +- chosen { }; +- +- aliases { +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- i2c3 = &i2c4; +- mmc0 = &mmc1; +- mmc1 = &mmc2; +- mmc2 = &mmc3; +- mmc3 = &mmc4; +- mmc4 = &mmc5; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- rproc0 = &dsp; +- rproc1 = &ipu; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- next-level-cache = <&L2>; +- reg = <0x0>; +- +- clocks = <&dpll_mpu_ck>; +- clock-names = "cpu"; +- +- clock-latency = <300000>; /* From omap-cpufreq driver */ +- }; +- cpu@1 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- next-level-cache = <&L2>; +- reg = <0x1>; +- }; +- }; +- +- /* +- * Needed early by omap4_sram_init() for barrier, do not move to l3 +- * interconnect as simple-pm-bus probes at module_init() time. +- */ +- ocmcram: sram@40304000 { +- compatible = "mmio-sram"; +- reg = <0x40304000 0xa000>; /* 40k */ +- }; +- +- gic: interrupt-controller@48241000 { +- compatible = "arm,cortex-a9-gic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x48241000 0x1000>, +- <0x48240100 0x0100>; +- interrupt-parent = <&gic>; +- }; +- +- L2: cache-controller@48242000 { +- compatible = "arm,pl310-cache"; +- reg = <0x48242000 0x1000>; +- cache-unified; +- cache-level = <2>; +- }; +- +- local-timer@48240600 { +- compatible = "arm,cortex-a9-twd-timer"; +- clocks = <&mpu_periphclk>; +- reg = <0x48240600 0x20>; +- interrupts = ; +- interrupt-parent = <&gic>; +- }; +- +- wakeupgen: interrupt-controller@48281000 { +- compatible = "ti,omap4-wugen-mpu"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x48281000 0x1000>; +- interrupt-parent = <&gic>; +- }; +- +- /* +- * XXX: Use a flat representation of the OMAP4 interconnect. +- * The real OMAP interconnect network is quite complex. +- * Since it will not bring real advantage to represent that in DT for +- * the moment, just use a fake OCP bus entry to represent the whole bus +- * hierarchy. +- */ +- ocp { +- compatible = "simple-pm-bus"; +- power-domains = <&prm_l4per>; +- clocks = <&l3_1_clkctrl OMAP4_L3_MAIN_1_CLKCTRL 0>, +- <&l3_2_clkctrl OMAP4_L3_MAIN_2_CLKCTRL 0>, +- <&l3_instr_clkctrl OMAP4_L3_MAIN_3_CLKCTRL 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- l3-noc@44000000 { +- compatible = "ti,omap4-l3-noc"; +- reg = <0x44000000 0x1000>, +- <0x44800000 0x2000>, +- <0x45000000 0x1000>; +- interrupts = , +- ; +- }; +- +- l4_wkup: interconnect@4a300000 { +- }; +- +- l4_cfg: interconnect@4a000000 { +- }; +- +- l4_per: interconnect@48000000 { +- }; +- +- target-module@48210000 { +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- power-domains = <&prm_mpu>; +- clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x48210000 0x1f0000>; +- +- mpu { +- compatible = "ti,omap4-mpu"; +- sram = <&ocmcram>; +- }; +- }; +- +- l4_abe: interconnect@40100000 { +- }; +- +- target-module@50000000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x50000000 4>, +- <0x50000010 4>, +- <0x50000014 4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- ti,no-idle-on-init; +- clocks = <&l3_2_clkctrl OMAP4_GPMC_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ +- <0x00000000 0x00000000 0x40000000>; /* data */ +- +- gpmc: gpmc@50000000 { +- compatible = "ti,omap4430-gpmc"; +- reg = <0x50000000 0x1000>; +- #address-cells = <2>; +- #size-cells = <1>; +- interrupts = ; +- dmas = <&sdma 4>; +- dma-names = "rxtx"; +- gpmc,num-cs = <8>; +- gpmc,num-waitpins = <4>; +- clocks = <&l3_div_ck>; +- clock-names = "fck"; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +- +- target-module@52000000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x52000000 0x4>, +- <0x52000010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,sysc-delay-us = <2>; +- power-domains = <&prm_cam>; +- clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x52000000 0x1000000>; +- +- /* No child device binding, driver in staging */ +- }; +- +- /* +- * Note that 4430 needs cross trigger interface (CTI) supported +- * before we can configure the interrupts. This means sampling +- * events are not supported for pmu. Note that 4460 does not use +- * CTI, see also 4460.dtsi. +- */ +- target-module@54000000 { +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- power-domains = <&prm_emu>; +- clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x54000000 0x1000000>; +- +- pmu: pmu { +- compatible = "arm,cortex-a9-pmu"; +- }; +- }; +- +- target-module@55082000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x55082000 0x4>, +- <0x55082010 0x4>, +- <0x55082014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>; +- clock-names = "fck"; +- resets = <&prm_core 2>; +- reset-names = "rstctrl"; +- ranges = <0x0 0x55082000 0x100>; +- #size-cells = <1>; +- #address-cells = <1>; +- +- mmu_ipu: mmu@0 { +- compatible = "ti,omap4-iommu"; +- reg = <0x0 0x100>; +- interrupts = ; +- #iommu-cells = <0>; +- ti,iommu-bus-err-back; +- }; +- }; +- +- target-module@4012c000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x4012c000 0x4>, +- <0x4012c010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- , +- ; +- clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */ +- <0x4902c000 0x4902c000 0x1000>; /* L3 */ +- +- /* No child device binding or driver in mainline */ +- }; +- +- target-module@4e000000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4e000000 0x4>, +- <0x4e000010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- ; +- ranges = <0x0 0x4e000000 0x2000000>; +- #size-cells = <1>; +- #address-cells = <1>; +- +- dmm@0 { +- compatible = "ti,omap4-dmm"; +- reg = <0 0x800>; +- interrupts = ; +- }; +- }; +- +- target-module@4c000000 { +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- reg = <0x4c000000 0x4>; +- reg-names = "rev"; +- clocks = <&l3_emif_clkctrl OMAP4_EMIF1_CLKCTRL 0>; +- clock-names = "fck"; +- ti,no-idle; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4c000000 0x1000000>; +- +- emif1: emif@0 { +- compatible = "ti,emif-4d"; +- reg = <0 0x100>; +- interrupts = ; +- phy-type = <1>; +- hw-caps-read-idle-ctrl; +- hw-caps-ll-interface; +- hw-caps-temp-alert; +- }; +- }; +- +- target-module@4d000000 { +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- reg = <0x4d000000 0x4>; +- reg-names = "rev"; +- clocks = <&l3_emif_clkctrl OMAP4_EMIF2_CLKCTRL 0>; +- clock-names = "fck"; +- ti,no-idle; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4d000000 0x1000000>; +- +- emif2: emif@0 { +- compatible = "ti,emif-4d"; +- reg = <0 0x100>; +- interrupts = ; +- phy-type = <1>; +- hw-caps-read-idle-ctrl; +- hw-caps-ll-interface; +- hw-caps-temp-alert; +- }; +- }; +- +- dsp: dsp { +- compatible = "ti,omap4-dsp"; +- ti,bootreg = <&scm_conf 0x304 0>; +- iommus = <&mmu_dsp>; +- resets = <&prm_tesla 0>; +- clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; +- firmware-name = "omap4-dsp-fw.xe64T"; +- mboxes = <&mailbox &mbox_dsp>; +- status = "disabled"; +- }; +- +- ipu: ipu@55020000 { +- compatible = "ti,omap4-ipu"; +- reg = <0x55020000 0x10000>; +- reg-names = "l2ram"; +- iommus = <&mmu_ipu>; +- resets = <&prm_core 0>, <&prm_core 1>; +- clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>; +- firmware-name = "omap4-ipu-fw.xem3"; +- mboxes = <&mailbox &mbox_ipu>; +- status = "disabled"; +- }; +- +- aes1_target: target-module@4b501000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4b501080 0x4>, +- <0x4b501084 0x4>, +- <0x4b501088 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ +- clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4b501000 0x1000>; +- +- aes1: aes@0 { +- compatible = "ti,omap4-aes"; +- reg = <0 0xa0>; +- interrupts = ; +- dmas = <&sdma 111>, <&sdma 110>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- aes2_target: target-module@4b701000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4b701080 0x4>, +- <0x4b701084 0x4>, +- <0x4b701088 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ +- clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4b701000 0x1000>; +- +- aes2: aes@0 { +- compatible = "ti,omap4-aes"; +- reg = <0 0xa0>; +- interrupts = ; +- dmas = <&sdma 114>, <&sdma 113>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- sham_target: target-module@4b100000 { +- compatible = "ti,sysc-omap3-sham", "ti,sysc"; +- reg = <0x4b100100 0x4>, +- <0x4b100110 0x4>, +- <0x4b100114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ +- clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4b100000 0x1000>; +- +- sham: sham@0 { +- compatible = "ti,omap4-sham"; +- reg = <0 0x300>; +- interrupts = ; +- dmas = <&sdma 119>; +- dma-names = "rx"; +- }; +- }; +- +- abb_mpu: regulator-abb-mpu { +- compatible = "ti,abb-v2"; +- regulator-name = "abb_mpu"; +- #address-cells = <0>; +- #size-cells = <0>; +- ti,tranxdone-status-mask = <0x80>; +- clocks = <&sys_clkin_ck>; +- ti,settling-time = <50>; +- ti,clock-cycles = <16>; +- +- status = "disabled"; +- }; +- +- abb_iva: regulator-abb-iva { +- compatible = "ti,abb-v2"; +- regulator-name = "abb_iva"; +- #address-cells = <0>; +- #size-cells = <0>; +- ti,tranxdone-status-mask = <0x80000000>; +- clocks = <&sys_clkin_ck>; +- ti,settling-time = <50>; +- ti,clock-cycles = <16>; +- +- status = "disabled"; +- }; +- +- sgx_module: target-module@56000000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x5600fe00 0x4>, +- <0x5600fe10 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- power-domains = <&prm_gfx>; +- clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x56000000 0x2000000>; +- +- /* +- * Closed source PowerVR driver, no child device +- * binding or driver in mainline +- */ +- }; +- +- /* +- * DSS is only using l3 mapping without l4 as noted in the TRM +- * "10.1.3 DSS Register Manual" for omap4460. +- */ +- target-module@58000000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x58000000 4>, +- <0x58000014 4>; +- reg-names = "rev", "syss"; +- ti,syss-mask = <1>; +- power-domains = <&prm_dss>; +- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>, +- <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, +- <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>, +- <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>; +- clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x58000000 0x1000000>; +- +- dss: dss@0 { +- compatible = "ti,omap4-dss"; +- reg = <0 0x80>; +- status = "disabled"; +- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x1000000>; +- +- target-module@1000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x1000 0x4>, +- <0x1010 0x4>, +- <0x1014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,syss-mask = <1>; +- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, +- <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; +- clock-names = "fck", "sys_clk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1000 0x1000>; +- +- dispc@0 { +- compatible = "ti,omap4-dispc"; +- reg = <0 0x1000>; +- interrupts = ; +- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; +- clock-names = "fck"; +- }; +- }; +- +- target-module@2000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x2000 0x4>, +- <0x2010 0x4>, +- <0x2014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,syss-mask = <1>; +- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, +- <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; +- clock-names = "fck", "sys_clk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x2000 0x1000>; +- +- rfbi: encoder@0 { +- reg = <0 0x1000>; +- status = "disabled"; +- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>; +- clock-names = "fck", "ick"; +- }; +- }; +- +- target-module@3000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x3000 0x4>; +- reg-names = "rev"; +- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; +- clock-names = "sys_clk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x3000 0x1000>; +- +- venc: encoder@0 { +- compatible = "ti,omap4-venc"; +- reg = <0 0x1000>; +- status = "disabled"; +- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>; +- clock-names = "fck"; +- }; +- }; +- +- target-module@4000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4000 0x4>, +- <0x4010 0x4>, +- <0x4014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,syss-mask = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x4000 0x1000>; +- +- dsi1: encoder@0 { +- compatible = "ti,omap4-dsi"; +- reg = <0 0x200>, +- <0x200 0x40>, +- <0x300 0x20>; +- reg-names = "proto", "phy", "pll"; +- interrupts = ; +- status = "disabled"; +- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, +- <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; +- clock-names = "fck", "sys_clk"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- target-module@5000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x5000 0x4>, +- <0x5010 0x4>, +- <0x5014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,syss-mask = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x5000 0x1000>; +- +- dsi2: encoder@0 { +- compatible = "ti,omap4-dsi"; +- reg = <0 0x200>, +- <0x200 0x40>, +- <0x300 0x20>; +- reg-names = "proto", "phy", "pll"; +- interrupts = ; +- status = "disabled"; +- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, +- <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; +- clock-names = "fck", "sys_clk"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- target-module@6000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x6000 0x4>, +- <0x6010 0x4>; +- reg-names = "rev", "sysc"; +- /* +- * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP +- * but HDMI audio will fail with them. +- */ +- ti,sysc-sidle = , +- ; +- ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; +- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, +- <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; +- clock-names = "fck", "dss_clk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x6000 0x2000>; +- +- hdmi: encoder@0 { +- compatible = "ti,omap4-hdmi"; +- reg = <0 0x200>, +- <0x200 0x100>, +- <0x300 0x100>, +- <0x400 0x1000>; +- reg-names = "wp", "pll", "phy", "core"; +- interrupts = ; +- status = "disabled"; +- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, +- <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; +- clock-names = "fck", "sys_clk"; +- dmas = <&sdma 76>; +- dma-names = "audio_tx"; +- }; +- }; +- }; +- }; +- +- iva_hd_target: target-module@5a000000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x5a05a400 0x4>, +- <0x5a05a410 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- power-domains = <&prm_ivahd>; +- resets = <&prm_ivahd 2>; +- reset-names = "rstctrl"; +- clocks = <&ivahd_clkctrl OMAP4_IVA_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x5a000000 0x5a000000 0x1000000>, +- <0x5b000000 0x5b000000 0x1000000>; +- +- iva { +- compatible = "ti,ivahd"; +- }; +- }; +- }; +-}; +- +-#include "omap4-l4.dtsi" +-#include "omap4-l4-abe.dtsi" +-#include "omap44xx-clocks.dtsi" +- +-&prm { +- prm_mpu: prm@300 { +- compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x300 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_tesla: prm@400 { +- compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x400 0x100>; +- #reset-cells = <1>; +- #power-domain-cells = <0>; +- }; +- +- prm_abe: prm@500 { +- compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x500 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_always_on_core: prm@600 { +- compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x600 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_core: prm@700 { +- compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x700 0x100>; +- #reset-cells = <1>; +- #power-domain-cells = <0>; +- }; +- +- prm_ivahd: prm@f00 { +- compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; +- reg = <0xf00 0x100>; +- #reset-cells = <1>; +- #power-domain-cells = <0>; +- }; +- +- prm_cam: prm@1000 { +- compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1000 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_dss: prm@1100 { +- compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1100 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_gfx: prm@1200 { +- compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1200 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_l3init: prm@1300 { +- compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1300 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_l4per: prm@1400 { +- compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1400 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_cefuse: prm@1600 { +- compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1600 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_wkup: prm@1700 { +- compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1700 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_emu: prm@1900 { +- compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1900 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_dss: prm@1100 { +- compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1100 0x40>; +- #power-domain-cells = <0>; +- }; +- +- prm_device: prm@1b00 { +- compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1b00 0x40>; +- #reset-cells = <1>; +- }; +-}; +- +-/* Preferred always-on timer for clockevent */ +-&timer1_target { +- ti,no-reset-on-init; +- ti,no-idle; +- timer@0 { +- assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>; +- assigned-clock-parents = <&sys_32k_ck>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap443x-clocks.dtsi b/scripts/dtc/include-prefixes/arm/omap443x-clocks.dtsi +deleted file mode 100644 +index 39297868ec85..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap443x-clocks.dtsi ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for OMAP4 clock data +- * +- * Copyright (C) 2013 Texas Instruments, Inc. +- */ +-&prm_clocks { +- bandgap_fclk: bandgap_fclk@1888 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&sys_32k_ck>; +- ti,bit-shift = <8>; +- reg = <0x1888>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap443x.dtsi b/scripts/dtc/include-prefixes/arm/omap443x.dtsi +deleted file mode 100644 +index 8466161197ae..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap443x.dtsi ++++ /dev/null +@@ -1,88 +0,0 @@ +-/* +- * Device Tree Source for OMAP443x SoC +- * +- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-#include "omap4.dtsi" +- +-/ { +- cpus { +- cpu0: cpu@0 { +- /* OMAP443x variants OPP50-OPPNT */ +- operating-points = < +- /* kHz uV */ +- 300000 1025000 +- 600000 1200000 +- 800000 1313000 +- 1008000 1375000 +- >; +- clock-latency = <300000>; /* From legacy driver */ +- +- /* cooling options */ +- #cooling-cells = <2>; /* min followed by max */ +- }; +- }; +- +- thermal-zones { +- #include "omap4-cpu-thermal.dtsi" +- }; +- +- ocp { +- /* 4430 has only gpio_86 tshut and no talert interrupt */ +- bandgap: bandgap@4a002260 { +- reg = <0x4a002260 0x4 +- 0x4a00232C 0x4>; +- compatible = "ti,omap4430-bandgap"; +- gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- +- #thermal-sensor-cells = <0>; +- }; +- }; +- +- ocp { +- abb_mpu: regulator-abb-mpu { +- status = "okay"; +- +- reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>; +- reg-names = "base-address", "int-address"; +- +- ti,abb_info = < +- /*uV ABB efuse rbb_m fbb_m vset_m*/ +- 1025000 0 0 0 0 0 +- 1200000 0 0 0 0 0 +- 1313000 0 0 0 0 0 +- 1375000 1 0 0 0 0 +- 1389000 1 0 0 0 0 +- >; +- }; +- +- /* Default unused, just provide register info for record */ +- abb_iva: regulator-abb-iva { +- reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>; +- reg-names = "base-address", "int-address"; +- }; +- +- }; +- +-}; +- +-&cpu_thermal { +- coefficients = <0 20000>; +-}; +- +-/include/ "omap443x-clocks.dtsi" +- +-/* +- * Use dpll_per for sgx at 307.2MHz like droid4 stock v3.0.8 Android kernel +- */ +-&sgx_module { +- assigned-clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 24>, +- <&dpll_per_m7x2_ck>; +- assigned-clock-rates = <0>, <307200000>; +- assigned-clock-parents = <&dpll_per_m7x2_ck>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap4460.dtsi b/scripts/dtc/include-prefixes/arm/omap4460.dtsi +deleted file mode 100644 +index 3d6db1db94e0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap4460.dtsi ++++ /dev/null +@@ -1,130 +0,0 @@ +-/* +- * Device Tree Source for OMAP4460 SoC +- * +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +-#include "omap4.dtsi" +- +-/ { +- cpus { +- /* OMAP446x 'standard device' variants OPP50 to OPPTurbo */ +- cpu0: cpu@0 { +- operating-points = < +- /* kHz uV */ +- 350000 1025000 +- 700000 1200000 +- 920000 1313000 +- >; +- clock-latency = <300000>; /* From legacy driver */ +- +- /* cooling options */ +- #cooling-cells = <2>; /* min followed by max */ +- }; +- }; +- +- thermal-zones { +- #include "omap4-cpu-thermal.dtsi" +- }; +- +- ocp { +- bandgap: bandgap@4a002260 { +- reg = <0x4a002260 0x4 +- 0x4a00232C 0x4 +- 0x4a002378 0x18>; +- compatible = "ti,omap4460-bandgap"; +- interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */ +- gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* tshut */ +- +- #thermal-sensor-cells = <0>; +- }; +- +- abb_mpu: regulator-abb-mpu { +- status = "okay"; +- +- reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>, +- <0x4A002268 0x4>; +- reg-names = "base-address", "int-address", +- "efuse-address"; +- +- ti,abb_info = < +- /*uV ABB efuse rbb_m fbb_m vset_m*/ +- 1025000 0 0 0 0 0 +- 1200000 0 0 0 0 0 +- 1313000 0 0 0x100000 0x40000 0 +- 1375000 1 0 0 0 0 +- 1389000 1 0 0 0 0 +- >; +- }; +- +- abb_iva: regulator-abb-iva { +- status = "okay"; +- +- reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>, +- <0x4A002268 0x4>; +- reg-names = "base-address", "int-address", +- "efuse-address"; +- +- ti,abb_info = < +- /*uV ABB efuse rbb_m fbb_m vset_m*/ +- 950000 0 0 0 0 0 +- 1140000 0 0 0 0 0 +- 1291000 0 0 0x200000 0 0 +- 1375000 1 0 0 0 0 +- 1376000 1 0 0 0 0 +- >; +- }; +- }; +- +-}; +- +-&cpu_thermal { +- coefficients = <348 (-9301)>; +-}; +- +-/* Only some L4 CFG interconnect ranges are different on 4460 */ +-&l4_cfg_segment_300000 { +- ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */ +- <0x00040000 0x00340000 0x001000>, /* ap 68 */ +- <0x00020000 0x00320000 0x004000>, /* ap 71 */ +- <0x00024000 0x00324000 0x002000>, /* ap 72 */ +- <0x00026000 0x00326000 0x001000>, /* ap 73 */ +- <0x00027000 0x00327000 0x001000>, /* ap 74 */ +- <0x00028000 0x00328000 0x001000>, /* ap 75 */ +- <0x00029000 0x00329000 0x001000>, /* ap 76 */ +- <0x00030000 0x00330000 0x010000>, /* ap 77 */ +- <0x0002a000 0x0032a000 0x002000>, /* ap 90 */ +- <0x0002c000 0x0032c000 0x004000>, /* ap 91 */ +- <0x00010000 0x00310000 0x008000>, /* ap 92 */ +- <0x00018000 0x00318000 0x004000>, /* ap 93 */ +- <0x0001c000 0x0031c000 0x002000>, /* ap 94 */ +- <0x0001e000 0x0031e000 0x002000>; /* ap 95 */ +-}; +- +-&l4_cfg_target_0 { +- ranges = <0x00000000 0x00000000 0x00010000>, +- <0x00010000 0x00010000 0x00008000>, +- <0x00018000 0x00018000 0x00004000>, +- <0x0001c000 0x0001c000 0x00002000>, +- <0x0001e000 0x0001e000 0x00002000>, +- <0x00020000 0x00020000 0x00004000>, +- <0x00024000 0x00024000 0x00002000>, +- <0x00026000 0x00026000 0x00001000>, +- <0x00027000 0x00027000 0x00001000>, +- <0x00028000 0x00028000 0x00001000>, +- <0x00029000 0x00029000 0x00001000>, +- <0x0002a000 0x0002a000 0x00002000>, +- <0x0002c000 0x0002c000 0x00004000>, +- <0x00030000 0x00030000 0x00010000>; +-}; +- +-&pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = , +- ; +-}; +- +-/include/ "omap446x-clocks.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/omap446x-clocks.dtsi b/scripts/dtc/include-prefixes/arm/omap446x-clocks.dtsi +deleted file mode 100644 +index 0f41714cffbb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap446x-clocks.dtsi ++++ /dev/null +@@ -1,24 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for OMAP4 clock data +- * +- * Copyright (C) 2013 Texas Instruments, Inc. +- */ +-&prm_clocks { +- div_ts_ck: div_ts_ck@1888 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&l4_wkup_clk_mux_ck>; +- ti,bit-shift = <24>; +- reg = <0x1888>; +- ti,dividers = <8>, <16>, <32>; +- }; +- +- bandgap_ts_fclk: bandgap_ts_fclk@1888 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&div_ts_ck>; +- ti,bit-shift = <8>; +- reg = <0x1888>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap44xx-clocks.dtsi b/scripts/dtc/include-prefixes/arm/omap44xx-clocks.dtsi +deleted file mode 100644 +index 1f1c04d8f472..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap44xx-clocks.dtsi ++++ /dev/null +@@ -1,1316 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for OMAP4 clock data +- * +- * Copyright (C) 2013 Texas Instruments, Inc. +- */ +-&cm1_clocks { +- extalt_clkin_ck: extalt_clkin_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <59000000>; +- }; +- +- pad_clks_src_ck: pad_clks_src_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <12000000>; +- }; +- +- pad_clks_ck: pad_clks_ck@108 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&pad_clks_src_ck>; +- ti,bit-shift = <8>; +- reg = <0x0108>; +- }; +- +- pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <12000000>; +- }; +- +- secure_32k_clk_src_ck: secure_32k_clk_src_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- slimbus_src_clk: slimbus_src_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <12000000>; +- }; +- +- slimbus_clk: slimbus_clk@108 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&slimbus_src_clk>; +- ti,bit-shift = <10>; +- reg = <0x0108>; +- }; +- +- sys_32k_ck: sys_32k_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- virt_12000000_ck: virt_12000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <12000000>; +- }; +- +- virt_13000000_ck: virt_13000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <13000000>; +- }; +- +- virt_16800000_ck: virt_16800000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <16800000>; +- }; +- +- virt_19200000_ck: virt_19200000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <19200000>; +- }; +- +- virt_26000000_ck: virt_26000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- }; +- +- virt_27000000_ck: virt_27000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <27000000>; +- }; +- +- virt_38400000_ck: virt_38400000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <38400000>; +- }; +- +- tie_low_clock_ck: tie_low_clock_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- utmi_phy_clkout_ck: utmi_phy_clkout_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <60000000>; +- }; +- +- xclk60mhsp1_ck: xclk60mhsp1_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <60000000>; +- }; +- +- xclk60mhsp2_ck: xclk60mhsp2_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <60000000>; +- }; +- +- xclk60motg_ck: xclk60motg_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <60000000>; +- }; +- +- dpll_abe_ck: dpll_abe_ck@1e0 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-m4xen-clock"; +- clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>; +- reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; +- }; +- +- dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-x2-clock"; +- clocks = <&dpll_abe_ck>; +- reg = <0x01f0>; +- }; +- +- dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_abe_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x01f0>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- abe_24m_fclk: abe_24m_fclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_abe_m2x2_ck>; +- clock-mult = <1>; +- clock-div = <8>; +- }; +- +- abe_clk: abe_clk@108 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_abe_m2x2_ck>; +- ti,max-div = <4>; +- reg = <0x0108>; +- ti,index-power-of-two; +- }; +- +- +- dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_abe_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x01f4>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>; +- ti,bit-shift = <23>; +- reg = <0x012c>; +- }; +- +- dpll_core_ck: dpll_core_ck@120 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-core-clock"; +- clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>; +- reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; +- }; +- +- dpll_core_x2_ck: dpll_core_x2_ck { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-x2-clock"; +- clocks = <&dpll_core_ck>; +- }; +- +- dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x0140>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_core_m2_ck: dpll_core_m2_ck@130 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x0130>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- ddrphy_ck: ddrphy_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_m2_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x013c>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- div_core_ck: div_core_ck@100 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_m5x2_ck>; +- reg = <0x0100>; +- ti,max-div = <2>; +- }; +- +- div_iva_hs_clk: div_iva_hs_clk@1dc { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_m5x2_ck>; +- ti,max-div = <4>; +- reg = <0x01dc>; +- ti,index-power-of-two; +- }; +- +- div_mpu_hs_clk: div_mpu_hs_clk@19c { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_m5x2_ck>; +- ti,max-div = <4>; +- reg = <0x019c>; +- ti,index-power-of-two; +- }; +- +- dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x0138>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dll_clk_div_ck: dll_clk_div_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_m4x2_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_abe_ck>; +- ti,max-div = <31>; +- reg = <0x01f0>; +- ti,index-starts-at-one; +- }; +- +- dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,bit-shift = <8>; +- reg = <0x0134>; +- }; +- +- dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 { +- #clock-cells = <0>; +- compatible = "ti,composite-divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <31>; +- reg = <0x0134>; +- ti,index-starts-at-one; +- }; +- +- dpll_core_m3x2_ck: dpll_core_m3x2_ck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>; +- }; +- +- dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x0144>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>; +- ti,bit-shift = <23>; +- reg = <0x01ac>; +- }; +- +- dpll_iva_ck: dpll_iva_ck@1a0 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-clock"; +- clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; +- reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; +- assigned-clocks = <&dpll_iva_ck>; +- assigned-clock-rates = <931200000>; +- }; +- +- dpll_iva_x2_ck: dpll_iva_x2_ck { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-x2-clock"; +- clocks = <&dpll_iva_ck>; +- }; +- +- dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_iva_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x01b8>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- assigned-clocks = <&dpll_iva_m4x2_ck>; +- assigned-clock-rates = <465600000>; +- }; +- +- dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_iva_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x01bc>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- assigned-clocks = <&dpll_iva_m5x2_ck>; +- assigned-clock-rates = <266100000>; +- }; +- +- dpll_mpu_ck: dpll_mpu_ck@160 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-clock"; +- clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>; +- reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; +- }; +- +- dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_mpu_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x0170>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- per_hs_clk_div_ck: per_hs_clk_div_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_abe_m3x2_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- usb_hs_clk_div_ck: usb_hs_clk_div_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_abe_m3x2_ck>; +- clock-mult = <1>; +- clock-div = <3>; +- }; +- +- l3_div_ck: l3_div_ck@100 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&div_core_ck>; +- ti,bit-shift = <4>; +- ti,max-div = <2>; +- reg = <0x0100>; +- }; +- +- l4_div_ck: l4_div_ck@100 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&l3_div_ck>; +- ti,bit-shift = <8>; +- ti,max-div = <2>; +- reg = <0x0100>; +- }; +- +- lp_clk_div_ck: lp_clk_div_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_abe_m2x2_ck>; +- clock-mult = <1>; +- clock-div = <16>; +- }; +- +- mpu_periphclk: mpu_periphclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_mpu_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- ocp_abe_iclk: ocp_abe_iclk@528 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>; +- ti,bit-shift = <24>; +- reg = <0x0528>; +- ti,dividers = <2>, <1>; +- }; +- +- per_abe_24m_fclk: per_abe_24m_fclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_abe_m2_ck>; +- clock-mult = <1>; +- clock-div = <4>; +- }; +- +- dummy_ck: dummy_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +-}; +- +-&prm_clocks { +- sys_clkin_ck: sys_clkin_ck@110 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; +- reg = <0x0110>; +- ti,index-starts-at-one; +- }; +- +- abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin_ck>, <&sys_32k_ck>; +- ti,bit-shift = <24>; +- reg = <0x0108>; +- }; +- +- abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin_ck>, <&sys_32k_ck>; +- reg = <0x010c>; +- }; +- +- dbgclk_mux_ck: dbgclk_mux_ck { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>; +- reg = <0x0108>; +- }; +- +- syc_clk_div_ck: syc_clk_div_ck@100 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&sys_clkin_ck>; +- reg = <0x0100>; +- ti,max-div = <2>; +- }; +- +- usim_ck: usim_ck@1858 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_m4x2_ck>; +- ti,bit-shift = <24>; +- reg = <0x1858>; +- ti,dividers = <14>, <18>; +- }; +- +- usim_fclk: usim_fclk@1858 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&usim_ck>; +- ti,bit-shift = <8>; +- reg = <0x1858>; +- }; +- +- trace_clk_div_ck: trace_clk_div_ck { +- #clock-cells = <0>; +- compatible = "ti,clkdm-gate-clock"; +- clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>; +- }; +-}; +- +-&prm_clockdomains { +- emu_sys_clkdm: emu_sys_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&trace_clk_div_ck>; +- }; +-}; +- +-&cm2_clocks { +- per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>; +- ti,bit-shift = <23>; +- reg = <0x014c>; +- }; +- +- dpll_per_ck: dpll_per_ck@140 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-clock"; +- clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>; +- reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; +- }; +- +- dpll_per_m2_ck: dpll_per_m2_ck@150 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_ck>; +- ti,max-div = <31>; +- reg = <0x0150>; +- ti,index-starts-at-one; +- }; +- +- dpll_per_x2_ck: dpll_per_x2_ck@150 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-x2-clock"; +- clocks = <&dpll_per_ck>; +- reg = <0x0150>; +- }; +- +- dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x0150>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&dpll_per_x2_ck>; +- ti,bit-shift = <8>; +- reg = <0x0154>; +- }; +- +- dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 { +- #clock-cells = <0>; +- compatible = "ti,composite-divider-clock"; +- clocks = <&dpll_per_x2_ck>; +- ti,max-div = <31>; +- reg = <0x0154>; +- ti,index-starts-at-one; +- }; +- +- dpll_per_m3x2_ck: dpll_per_m3x2_ck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>; +- }; +- +- dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x0158>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x015c>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x0160>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_x2_ck>; +- ti,max-div = <31>; +- ti,autoidle-shift = <8>; +- reg = <0x0164>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- dpll_usb_ck: dpll_usb_ck@180 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-j-type-clock"; +- clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>; +- reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; +- }; +- +- dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 { +- #clock-cells = <0>; +- compatible = "ti,fixed-factor-clock"; +- clocks = <&dpll_usb_ck>; +- ti,clock-div = <1>; +- ti,autoidle-shift = <8>; +- reg = <0x01b4>; +- ti,clock-mult = <1>; +- ti,invert-autoidle-bit; +- }; +- +- dpll_usb_m2_ck: dpll_usb_m2_ck@190 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_usb_ck>; +- ti,max-div = <127>; +- ti,autoidle-shift = <8>; +- reg = <0x0190>; +- ti,index-starts-at-one; +- ti,invert-autoidle-bit; +- }; +- +- ducati_clk_mux_ck: ducati_clk_mux_ck@100 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>; +- reg = <0x0100>; +- }; +- +- func_12m_fclk: func_12m_fclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2x2_ck>; +- clock-mult = <1>; +- clock-div = <16>; +- }; +- +- func_24m_clk: func_24m_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2_ck>; +- clock-mult = <1>; +- clock-div = <4>; +- }; +- +- func_24mc_fclk: func_24mc_fclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2x2_ck>; +- clock-mult = <1>; +- clock-div = <8>; +- }; +- +- func_48m_fclk: func_48m_fclk@108 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_m2x2_ck>; +- reg = <0x0108>; +- ti,dividers = <4>, <8>; +- }; +- +- func_48mc_fclk: func_48mc_fclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2x2_ck>; +- clock-mult = <1>; +- clock-div = <4>; +- }; +- +- func_64m_fclk: func_64m_fclk@108 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_m4x2_ck>; +- reg = <0x0108>; +- ti,dividers = <2>, <4>; +- }; +- +- func_96m_fclk: func_96m_fclk@108 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_m2x2_ck>; +- reg = <0x0108>; +- ti,dividers = <2>, <4>; +- }; +- +- init_60m_fclk: init_60m_fclk@104 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_usb_m2_ck>; +- reg = <0x0104>; +- ti,dividers = <1>, <8>; +- }; +- +- per_abe_nc_fclk: per_abe_nc_fclk@108 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_abe_m2_ck>; +- reg = <0x0108>; +- ti,max-div = <2>; +- }; +- +- usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&sys_32k_ck>; +- ti,bit-shift = <8>; +- reg = <0x0640>; +- }; +-}; +- +-&cm2_clockdomains { +- l3_init_clkdm: l3_init_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&dpll_usb_ck>; +- }; +-}; +- +-&scrm_clocks { +- auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&dpll_core_m3x2_ck>; +- ti,bit-shift = <8>; +- reg = <0x0310>; +- }; +- +- auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; +- ti,bit-shift = <1>; +- reg = <0x0310>; +- }; +- +- auxclk0_src_ck: auxclk0_src_ck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; +- }; +- +- auxclk0_ck: auxclk0_ck@310 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&auxclk0_src_ck>; +- ti,bit-shift = <16>; +- ti,max-div = <16>; +- reg = <0x0310>; +- }; +- +- auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&dpll_core_m3x2_ck>; +- ti,bit-shift = <8>; +- reg = <0x0314>; +- }; +- +- auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; +- ti,bit-shift = <1>; +- reg = <0x0314>; +- }; +- +- auxclk1_src_ck: auxclk1_src_ck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; +- }; +- +- auxclk1_ck: auxclk1_ck@314 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&auxclk1_src_ck>; +- ti,bit-shift = <16>; +- ti,max-div = <16>; +- reg = <0x0314>; +- }; +- +- auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&dpll_core_m3x2_ck>; +- ti,bit-shift = <8>; +- reg = <0x0318>; +- }; +- +- auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; +- ti,bit-shift = <1>; +- reg = <0x0318>; +- }; +- +- auxclk2_src_ck: auxclk2_src_ck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; +- }; +- +- auxclk2_ck: auxclk2_ck@318 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&auxclk2_src_ck>; +- ti,bit-shift = <16>; +- ti,max-div = <16>; +- reg = <0x0318>; +- }; +- +- auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&dpll_core_m3x2_ck>; +- ti,bit-shift = <8>; +- reg = <0x031c>; +- }; +- +- auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; +- ti,bit-shift = <1>; +- reg = <0x031c>; +- }; +- +- auxclk3_src_ck: auxclk3_src_ck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; +- }; +- +- auxclk3_ck: auxclk3_ck@31c { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&auxclk3_src_ck>; +- ti,bit-shift = <16>; +- ti,max-div = <16>; +- reg = <0x031c>; +- }; +- +- auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&dpll_core_m3x2_ck>; +- ti,bit-shift = <8>; +- reg = <0x0320>; +- }; +- +- auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; +- ti,bit-shift = <1>; +- reg = <0x0320>; +- }; +- +- auxclk4_src_ck: auxclk4_src_ck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; +- }; +- +- auxclk4_ck: auxclk4_ck@320 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&auxclk4_src_ck>; +- ti,bit-shift = <16>; +- ti,max-div = <16>; +- reg = <0x0320>; +- }; +- +- auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&dpll_core_m3x2_ck>; +- ti,bit-shift = <8>; +- reg = <0x0324>; +- }; +- +- auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; +- ti,bit-shift = <1>; +- reg = <0x0324>; +- }; +- +- auxclk5_src_ck: auxclk5_src_ck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>; +- }; +- +- auxclk5_ck: auxclk5_ck@324 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&auxclk5_src_ck>; +- ti,bit-shift = <16>; +- ti,max-div = <16>; +- reg = <0x0324>; +- }; +- +- auxclkreq0_ck: auxclkreq0_ck@210 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; +- ti,bit-shift = <2>; +- reg = <0x0210>; +- }; +- +- auxclkreq1_ck: auxclkreq1_ck@214 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; +- ti,bit-shift = <2>; +- reg = <0x0214>; +- }; +- +- auxclkreq2_ck: auxclkreq2_ck@218 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; +- ti,bit-shift = <2>; +- reg = <0x0218>; +- }; +- +- auxclkreq3_ck: auxclkreq3_ck@21c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; +- ti,bit-shift = <2>; +- reg = <0x021c>; +- }; +- +- auxclkreq4_ck: auxclkreq4_ck@220 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; +- ti,bit-shift = <2>; +- reg = <0x0220>; +- }; +- +- auxclkreq5_ck: auxclkreq5_ck@224 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; +- ti,bit-shift = <2>; +- reg = <0x0224>; +- }; +-}; +- +-&cm1 { +- mpuss_cm: mpuss_cm@300 { +- compatible = "ti,omap4-cm"; +- reg = <0x300 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x300 0x100>; +- +- mpuss_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- tesla_cm: tesla_cm@400 { +- compatible = "ti,omap4-cm"; +- reg = <0x400 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x400 0x100>; +- +- tesla_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- abe_cm: abe_cm@500 { +- compatible = "ti,omap4-cm"; +- reg = <0x500 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x500 0x100>; +- +- abe_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x6c>; +- #clock-cells = <2>; +- }; +- }; +- +-}; +- +-&cm2 { +- l4_ao_cm: l4_ao_cm@600 { +- compatible = "ti,omap4-cm"; +- reg = <0x600 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x600 0x100>; +- +- l4_ao_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x1c>; +- #clock-cells = <2>; +- }; +- }; +- +- l3_1_cm: l3_1_cm@700 { +- compatible = "ti,omap4-cm"; +- reg = <0x700 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x700 0x100>; +- +- l3_1_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- l3_2_cm: l3_2_cm@800 { +- compatible = "ti,omap4-cm"; +- reg = <0x800 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x800 0x100>; +- +- l3_2_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x14>; +- #clock-cells = <2>; +- }; +- }; +- +- ducati_cm: ducati_cm@900 { +- compatible = "ti,omap4-cm"; +- reg = <0x900 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x900 0x100>; +- +- ducati_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- l3_dma_cm: l3_dma_cm@a00 { +- compatible = "ti,omap4-cm"; +- reg = <0xa00 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xa00 0x100>; +- +- l3_dma_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- l3_emif_cm: l3_emif_cm@b00 { +- compatible = "ti,omap4-cm"; +- reg = <0xb00 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xb00 0x100>; +- +- l3_emif_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x1c>; +- #clock-cells = <2>; +- }; +- }; +- +- d2d_cm: d2d_cm@c00 { +- compatible = "ti,omap4-cm"; +- reg = <0xc00 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xc00 0x100>; +- +- d2d_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- l4_cfg_cm: l4_cfg_cm@d00 { +- compatible = "ti,omap4-cm"; +- reg = <0xd00 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xd00 0x100>; +- +- l4_cfg_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x14>; +- #clock-cells = <2>; +- }; +- }; +- +- l3_instr_cm: l3_instr_cm@e00 { +- compatible = "ti,omap4-cm"; +- reg = <0xe00 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xe00 0x100>; +- +- l3_instr_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x24>; +- #clock-cells = <2>; +- }; +- }; +- +- ivahd_cm: ivahd_cm@f00 { +- compatible = "ti,omap4-cm"; +- reg = <0xf00 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xf00 0x100>; +- +- ivahd_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0xc>; +- #clock-cells = <2>; +- }; +- }; +- +- iss_cm: iss_cm@1000 { +- compatible = "ti,omap4-cm"; +- reg = <0x1000 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1000 0x100>; +- +- iss_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0xc>; +- #clock-cells = <2>; +- }; +- }; +- +- l3_dss_cm: l3_dss_cm@1100 { +- compatible = "ti,omap4-cm"; +- reg = <0x1100 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1100 0x100>; +- +- l3_dss_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- l3_gfx_cm: l3_gfx_cm@1200 { +- compatible = "ti,omap4-cm"; +- reg = <0x1200 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1200 0x100>; +- +- l3_gfx_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- l3_init_cm: l3_init_cm@1300 { +- compatible = "ti,omap4-cm"; +- reg = <0x1300 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1300 0x100>; +- +- l3_init_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0xc4>; +- #clock-cells = <2>; +- }; +- }; +- +- l4_per_cm: l4_per_cm@1400 { +- compatible = "ti,omap4-cm"; +- reg = <0x1400 0x200>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1400 0x200>; +- +- l4_per_clkctrl: clock@20 { +- compatible = "ti,clkctrl-l4-per", "ti,clkctrl"; +- reg = <0x20 0x144>; +- #clock-cells = <2>; +- }; +- +- l4_secure_clkctrl: clock@1a0 { +- compatible = "ti,clkctrl-l4-secure", "ti,clkctrl"; +- reg = <0x1a0 0x3c>; +- #clock-cells = <2>; +- }; +- }; +-}; +- +-&prm { +- l4_wkup_cm: l4_wkup_cm@1800 { +- compatible = "ti,omap4-cm"; +- reg = <0x1800 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1800 0x100>; +- +- l4_wkup_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x5c>; +- #clock-cells = <2>; +- }; +- }; +- +- emu_sys_cm: emu_sys_cm@1a00 { +- compatible = "ti,omap4-cm"; +- reg = <0x1a00 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1a00 0x100>; +- +- emu_sys_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap5-board-common.dtsi b/scripts/dtc/include-prefixes/arm/omap5-board-common.dtsi +deleted file mode 100644 +index 373984c130e0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap5-board-common.dtsi ++++ /dev/null +@@ -1,755 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-#include "omap5.dtsi" +-#include +-#include +- +-/ { +- aliases { +- display0 = &hdmi0; +- }; +- +- chosen { +- stdout-path = &uart3; +- }; +- +- vmain: fixedregulator-vmain { +- compatible = "regulator-fixed"; +- regulator-name = "vmain"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- vsys_cobra: fixedregulator-vsys_cobra { +- compatible = "regulator-fixed"; +- regulator-name = "vsys_cobra"; +- vin-supply = <&vmain>; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- vmmcsd_fixed: fixedregulator-mmcsd { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsd_fixed"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- mmc3_pwrseq: sdhci0_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&clk32kgaudio>; +- clock-names = "ext_clock"; +- }; +- +- vmmcsdio_fixed: fixedregulator-mmcsdio { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsdio_fixed"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio5 12 GPIO_ACTIVE_HIGH>; /* gpio140 WLAN_EN */ +- enable-active-high; +- startup-delay-us = <70000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_pins>; +- }; +- +- /* HS USB Host PHY on PORT 2 */ +- hsusb2_phy: hsusb2_phy { +- compatible = "usb-nop-xceiv"; +- reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */ +- clocks = <&auxclk1_ck>; +- clock-names = "main_clk"; +- clock-frequency = <19200000>; +- #phy-cells = <0>; +- }; +- +- /* HS USB Host PHY on PORT 3 */ +- hsusb3_phy: hsusb3_phy { +- compatible = "usb-nop-xceiv"; +- reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */ +- #phy-cells = <0>; +- }; +- +- tpd12s015: encoder { +- compatible = "ti,tpd12s015"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&tpd12s015_pins>; +- +- /* gpios defined in the board specific dts */ +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tpd12s015_in: endpoint { +- remote-endpoint = <&hdmi_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- tpd12s015_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +- }; +- }; +- }; +- +- hdmi0: connector { +- compatible = "hdmi-connector"; +- label = "hdmi"; +- +- type = "b"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&tpd12s015_out>; +- }; +- }; +- }; +- +- sound: sound { +- compatible = "ti,abe-twl6040"; +- ti,model = "omap5-uevm"; +- +- ti,jack-detection; +- ti,mclk-freq = <19200000>; +- +- ti,mcpdm = <&mcpdm>; +- +- ti,twl6040 = <&twl6040>; +- +- /* Audio routing */ +- ti,audio-routing = +- "Headset Stereophone", "HSOL", +- "Headset Stereophone", "HSOR", +- "Line Out", "AUXL", +- "Line Out", "AUXR", +- "HSMIC", "Headset Mic", +- "Headset Mic", "Headset Mic Bias", +- "AFML", "Line In", +- "AFMR", "Line In"; +- }; +-}; +- +-&gpio8 { +- /* TI trees use GPIO instead of msecure, see also muxing */ +- msecure-hog { +- gpio-hog; +- gpios = <10 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "gpio8_234/msecure"; +- }; +-}; +- +-&omap5_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &usbhost_pins +- &led_gpio_pins +- >; +- +- twl6040_pins: pinmux_twl6040_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ +- >; +- }; +- +- mcpdm_pins: pinmux_mcpdm_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x182, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ +- OMAP5_IOPAD(0x19c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */ +- OMAP5_IOPAD(0x19e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */ +- OMAP5_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */ +- OMAP5_IOPAD(0x1a2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */ +- >; +- }; +- +- mcbsp1_pins: pinmux_mcbsp1_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x18c, PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */ +- OMAP5_IOPAD(0x18e, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */ +- OMAP5_IOPAD(0x190, PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */ +- OMAP5_IOPAD(0x192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */ +- >; +- }; +- +- mcbsp2_pins: pinmux_mcbsp2_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x194, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */ +- OMAP5_IOPAD(0x196, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */ +- OMAP5_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */ +- OMAP5_IOPAD(0x19a, PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */ +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x1f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ +- OMAP5_IOPAD(0x1f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ +- >; +- }; +- +- mcspi2_pins: pinmux_mcspi2_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ +- OMAP5_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ +- OMAP5_IOPAD(0x100, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */ +- OMAP5_IOPAD(0x102, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */ +- >; +- }; +- +- mcspi3_pins: pinmux_mcspi3_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x0b8, PIN_INPUT | MUX_MODE1) /* mcspi3_somi */ +- OMAP5_IOPAD(0x0ba, PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */ +- OMAP5_IOPAD(0x0bc, PIN_INPUT | MUX_MODE1) /* mcspi3_simo */ +- OMAP5_IOPAD(0x0be, PIN_INPUT | MUX_MODE1) /* mcspi3_clk */ +- >; +- }; +- +- mmc3_pins: pinmux_mmc3_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */ +- OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */ +- OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */ +- OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */ +- OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */ +- OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */ +- >; +- }; +- +- wlan_pins: pinmux_wlan_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE6) /* mcspi1_clk.gpio5_140 */ +- >; +- }; +- +- /* TI trees use GPIO mode; msecure mode does not work reliably? */ +- palmas_msecure_pins: palmas_msecure_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x180, PIN_OUTPUT | MUX_MODE6) /* gpio8_234 */ +- >; +- }; +- +- usbhost_pins: pinmux_usbhost_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x0c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ +- OMAP5_IOPAD(0x0c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ +- +- OMAP5_IOPAD(0x1de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ +- OMAP5_IOPAD(0x1e0, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ +- +- OMAP5_IOPAD(0x0b0, PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */ +- OMAP5_IOPAD(0x0ae, PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */ +- >; +- }; +- +- led_gpio_pins: pinmux_led_gpio_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x1d6, PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */ +- >; +- }; +- +- uart1_pins: pinmux_uart1_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x0a0, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */ +- OMAP5_IOPAD(0x0a2, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */ +- OMAP5_IOPAD(0x0a4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */ +- OMAP5_IOPAD(0x0a6, PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */ +- >; +- }; +- +- uart3_pins: pinmux_uart3_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x1da, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */ +- OMAP5_IOPAD(0x1dc, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */ +- >; +- }; +- +- uart5_pins: pinmux_uart5_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x1b0, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */ +- OMAP5_IOPAD(0x1b2, PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */ +- OMAP5_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */ +- OMAP5_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */ +- >; +- }; +- +- dss_hdmi_pins: pinmux_dss_hdmi_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x13c, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ +- OMAP5_IOPAD(0x140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */ +- OMAP5_IOPAD(0x142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */ +- >; +- }; +- +- tpd12s015_pins: pinmux_tpd12s015_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x13e, PIN_INPUT_PULLDOWN | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ +- >; +- }; +-}; +- +-&omap5_pmx_wkup { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &usbhost_wkup_pins +- >; +- +- palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins { +- pinctrl-single,pins = < +- /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */ +- OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) +- >; +- }; +- +- usbhost_wkup_pins: pinmux_usbhost_wkup_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */ +- >; +- }; +- +- wlcore_irq_pin: pinmux_wlcore_irq_pin { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */ +- >; +- }; +-}; +- +-&mmc1 { +- vmmc-supply = <&ldo9_reg>; +- bus-width = <4>; +-}; +- +-&mmc2 { +- vmmc-supply = <&vmmcsd_fixed>; +- bus-width = <8>; +- ti,non-removable; +-}; +- +-&mmc3 { +- vmmc-supply = <&vmmcsdio_fixed>; +- mmc-pwrseq = <&mmc3_pwrseq>; +- bus-width = <4>; +- non-removable; +- cap-power-off-card; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc3_pins>; +- interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH +- &omap5_pmx_core 0x16a>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1271"; +- reg = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&wlcore_irq_pin>; +- interrupt-parent = <&gpio1>; +- interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */ +- ref-clock-frequency = <26000000>; +- }; +-}; +- +-&mmc4 { +- status = "disabled"; +-}; +- +-&mmc5 { +- status = "disabled"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- +- clock-frequency = <400000>; +- +- palmas: palmas@48 { +- compatible = "ti,palmas"; +- /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */ +- interrupts = ; +- reg = <0x48>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,system-power-controller; +- ti,mux-pad1 = <0xa1>; +- ti,mux-pad2 = <0x1b>; +- pinctrl-names = "default"; +- pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>; +- +- palmas_gpio: gpio { +- compatible = "ti,palmas-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- extcon_usb3: palmas_usb { +- compatible = "ti,palmas-usb-vid"; +- ti,enable-vbus-detection; +- ti,enable-id-detection; +- ti,wakeup; +- id-gpios = <&palmas_gpio 0 GPIO_ACTIVE_HIGH>; +- }; +- +- clk32kgaudio: palmas_clk32k@1 { +- compatible = "ti,palmas-clk32kgaudio"; +- #clock-cells = <0>; +- }; +- +- rtc { +- compatible = "ti,palmas-rtc"; +- interrupt-parent = <&palmas>; +- interrupts = <8 IRQ_TYPE_NONE>; +- ti,backup-battery-chargeable; +- ti,backup-battery-charge-high-current; +- }; +- +- gpadc: gpadc { +- compatible = "ti,palmas-gpadc"; +- interrupts = <18 0 +- 16 0 +- 17 0>; +- #io-channel-cells = <1>; +- ti,channel0-current-microamp = <5>; +- ti,channel3-current-microamp = <10>; +- }; +- +- palmas_pmic { +- compatible = "ti,palmas-pmic"; +- interrupt-parent = <&palmas>; +- interrupts = <14 IRQ_TYPE_NONE>; +- interrupt-names = "short-irq"; +- +- ti,ldo6-vibrator; +- +- smps123-in-supply = <&vsys_cobra>; +- smps45-in-supply = <&vsys_cobra>; +- smps6-in-supply = <&vsys_cobra>; +- smps7-in-supply = <&vsys_cobra>; +- smps8-in-supply = <&vsys_cobra>; +- smps9-in-supply = <&vsys_cobra>; +- smps10_out2-in-supply = <&vsys_cobra>; +- smps10_out1-in-supply = <&vsys_cobra>; +- ldo1-in-supply = <&vsys_cobra>; +- ldo2-in-supply = <&vsys_cobra>; +- ldo3-in-supply = <&vdds_1v8_main>; +- ldo4-in-supply = <&vdds_1v8_main>; +- ldo5-in-supply = <&vsys_cobra>; +- ldo6-in-supply = <&vdds_1v8_main>; +- ldo7-in-supply = <&vsys_cobra>; +- ldo8-in-supply = <&vsys_cobra>; +- ldo9-in-supply = <&vmmcsd_fixed>; +- ldoln-in-supply = <&vsys_cobra>; +- ldousb-in-supply = <&vsys_cobra>; +- +- regulators { +- smps123_reg: smps123 { +- /* VDD_OPP_MPU */ +- regulator-name = "smps123"; +- regulator-min-microvolt = < 600000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps45_reg: smps45 { +- /* VDD_OPP_MM */ +- regulator-name = "smps45"; +- regulator-min-microvolt = < 600000>; +- regulator-max-microvolt = <1310000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps6_reg: smps6 { +- /* VDD_DDR3 - over VDD_SMPS6 */ +- regulator-name = "smps6"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdds_1v8_main: +- smps7_reg: smps7 { +- /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */ +- regulator-name = "smps7"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps8_reg: smps8 { +- /* VDD_OPP_CORE */ +- regulator-name = "smps8"; +- regulator-min-microvolt = < 600000>; +- regulator-max-microvolt = <1310000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps9_reg: smps9 { +- /* VDDA_2v1_AUD over VDD_2v1 */ +- regulator-name = "smps9"; +- regulator-min-microvolt = <2100000>; +- regulator-max-microvolt = <2100000>; +- ti,smps-range = <0x80>; +- }; +- +- smps10_out2_reg: smps10_out2 { +- /* VBUS_5V_OTG */ +- regulator-name = "smps10_out2"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps10_out1_reg: smps10_out1 { +- /* VBUS_5V_OTG */ +- regulator-name = "smps10_out1"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- ldo1_reg: ldo1 { +- /* VDDAPHY_CAM: vdda_csiport */ +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo2_reg: ldo2 { +- /* VCC_2V8_DISP: Does not go anywhere */ +- regulator-name = "ldo2"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- /* Unused */ +- status = "disabled"; +- }; +- +- ldo3_reg: ldo3 { +- /* VDDAPHY_MDM: vdda_lli */ +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- /* Only if Modem is used */ +- status = "disabled"; +- }; +- +- ldo4_reg: ldo4 { +- /* VDDAPHY_DISP: vdda_dsiport/hdmi */ +- regulator-name = "ldo4"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo5_reg: ldo5 { +- /* VDDA_1V8_PHY: usb/sata/hdmi.. */ +- regulator-name = "ldo5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo6_reg: ldo6 { +- /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */ +- regulator-name = "ldo6"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo7_reg: ldo7 { +- /* VDD_VPP: vpp1 */ +- regulator-name = "ldo7"; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- /* Only for efuse reprograming! */ +- status = "disabled"; +- }; +- +- ldo8_reg: ldo8 { +- /* VDD_3v0: Does not go anywhere */ +- regulator-name = "ldo8"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- /* Unused */ +- status = "disabled"; +- }; +- +- ldo9_reg: ldo9 { +- /* VCC_DV_SDIO: vdds_sdcard */ +- regulator-name = "ldo9"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- }; +- +- ldoln_reg: ldoln { +- /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */ +- regulator-name = "ldoln"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldousb_reg: ldousb { +- /* VDDA_3V_USB: VDDA_USBHS33 */ +- regulator-name = "ldousb"; +- regulator-min-microvolt = <3250000>; +- regulator-max-microvolt = <3250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- regen3_reg: regen3 { +- /* REGEN3 controls LDO9 supply to card */ +- regulator-name = "regen3"; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +- +- palmas_power_button: palmas_power_button { +- compatible = "ti,palmas-pwrbutton"; +- interrupt-parent = <&palmas>; +- interrupts = <1 IRQ_TYPE_EDGE_FALLING>; +- wakeup-source; +- }; +- }; +- +- twl6040: twl@4b { +- compatible = "ti,twl6040"; +- #clock-cells = <0>; +- reg = <0x4b>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&twl6040_pins>; +- +- /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */ +- interrupts = ; +- +- /* audpwron gpio defined in the board specific dts */ +- +- vio-supply = <&smps7_reg>; +- v2v1-supply = <&smps9_reg>; +- enable-active-high; +- +- clocks = <&clk32kgaudio>, <&fref_xtal_ck>; +- clock-names = "clk32k", "mclk"; +- }; +-}; +- +-&mcpdm_module { +- /* Module on the SoC needs external clock from the PMIC */ +- pinctrl-names = "default"; +- pinctrl-0 = <&mcpdm_pins>; +- status = "okay"; +-}; +- +-&mcpdm { +- clocks = <&twl6040>; +- clock-names = "pdmclk"; +-}; +- +-&mcbsp1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp1_pins>; +- status = "okay"; +-}; +- +-&mcbsp2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcbsp2_pins>; +- status = "okay"; +-}; +- +-&usbhshost { +- port2-mode = "ehci-hsic"; +- port3-mode = "ehci-hsic"; +-}; +- +-&usbhsehci { +- phys = <0 &hsusb2_phy &hsusb3_phy>; +-}; +- +-&usb3 { +- extcon = <&extcon_usb3>; +- vbus-supply = <&smps10_out1_reg>; +-}; +- +-&dwc3 { +- extcon = <&extcon_usb3>; +- dr_mode = "otg"; +-}; +- +-&mcspi1 { +- +-}; +- +-&mcspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcspi2_pins>; +-}; +- +-&mcspi3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcspi3_pins>; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, +- <&omap5_pmx_core 0x19c>; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart5_pins>; +-}; +- +-&cpu0 { +- cpu0-supply = <&smps123_reg>; +-}; +- +-&dss { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +- +- /* vdda-supply populated in board specific dts file */ +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_hdmi_pins>; +- +- port { +- hdmi_out: endpoint { +- remote-endpoint = <&tpd12s015_in>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap5-cm-t54.dts b/scripts/dtc/include-prefixes/arm/omap5-cm-t54.dts +deleted file mode 100644 +index ca759b7b8a58..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap5-cm-t54.dts ++++ /dev/null +@@ -1,697 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Support for CompuLab CM-T54 +- */ +-/dts-v1/; +- +-#include "omap5.dtsi" +-#include +-#include +- +-/ { +- model = "CompuLab CM-T54"; +- compatible = "compulab,omap5-cm-t54", "ti,omap5"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0 0x80000000 0 0x7f000000>; /* 2048 MB */ +- }; +- +- aliases { +- display0 = &hdmi0; +- display1 = &dvi0; +- display2 = &lcd0; +- }; +- +- vmmcsd_fixed: fixed-regulator-mmcsd { +- compatible = "regulator-fixed"; +- regulator-name = "vmmcsd_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vwlan_pdn_fixed: fixed-regulator-vwlan-pdn { +- compatible = "regulator-fixed"; +- regulator-name = "vwlan_pdn_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&ldo2_reg>; +- gpio = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* gpio4_109 */ +- startup-delay-us = <1000>; +- enable-active-high; +- }; +- +- vwlan_fixed: fixed-regulator-vwlan { +- compatible = "regulator-fixed"; +- regulator-name = "vwlan_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vwlan_pdn_fixed>; +- gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>; /* gpio4_110 */ +- startup-delay-us = <1000>; +- enable-active-high; +- }; +- +- ads7846reg: ads7846-reg { +- compatible = "regulator-fixed"; +- regulator-name = "ads7846-reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- /* HS USB Host PHY on PORT 2 */ +- hsusb2_phy: hsusb2_phy { +- compatible = "usb-nop-xceiv"; +- reset-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; /* gpio3_76 HUB_RESET */ +- #phy-cells = <0>; +- }; +- +- /* HS USB Host PHY on PORT 3 */ +- hsusb3_phy: hsusb3_phy { +- compatible = "usb-nop-xceiv"; +- reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 ETH_RESET */ +- #phy-cells = <0>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led1 { +- label = "Heartbeat"; +- gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 ACT_LED */ +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- }; +- +- lcd0: display { +- compatible = "startek,startek-kd050c", "panel-dpi"; +- label = "lcd"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_pins>; +- +- enable-gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; +- +- panel-timing { +- clock-frequency = <33000000>; +- hactive = <800>; +- vactive = <480>; +- hfront-porch = <40>; +- hback-porch = <40>; +- hsync-len = <43>; +- vback-porch = <29>; +- vfront-porch = <13>; +- vsync-len = <3>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- +- port { +- lcd_in: endpoint { +- remote-endpoint = <&dpi_lcd_out>; +- }; +- }; +- }; +- +- hdmi0: connector0 { +- compatible = "hdmi-connector"; +- label = "hdmi"; +- +- type = "a"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_conn_pins>; +- +- hpd-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */ +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_out>; +- }; +- }; +- }; +- +- tfp410: encoder0 { +- compatible = "ti,tfp410"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- tfp410_in: endpoint { +- remote-endpoint = <&dpi_dvi_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- tfp410_out: endpoint { +- remote-endpoint = <&dvi_connector_in>; +- }; +- }; +- }; +- }; +- +- dvi0: connector1 { +- compatible = "dvi-connector"; +- label = "dvi"; +- +- digital; +- +- ddc-i2c-bus = <&i2c2>; +- +- port { +- dvi_connector_in: endpoint { +- remote-endpoint = <&tfp410_out>; +- }; +- }; +- }; +-}; +- +-&omap5_pmx_wkup { +- +- ads7846_pins: pinmux_ads7846_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x0042, PIN_INPUT_PULLDOWN | MUX_MODE6) /* llib_wakereqin.gpio1_wk15 */ +- >; +- }; +- +- palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins { +- pinctrl-single,pins = < +- /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */ +- OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) +- >; +- }; +-}; +- +-&omap5_pmx_core { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &led_gpio_pins +- &usbhost_pins +- >; +- +- led_gpio_pins: pinmux_led_gpio_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x00b0, PIN_OUTPUT | MUX_MODE6) /* hsi2_caflag.gpio3_80 */ +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x01f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_scl */ +- OMAP5_IOPAD(0x01f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_sda */ +- >; +- }; +- +- i2c2_pins: pinmux_i2c2_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x01b8, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ +- OMAP5_IOPAD(0x01ba, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x01e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_clk */ +- OMAP5_IOPAD(0x01e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_cmd */ +- OMAP5_IOPAD(0x01e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data2 */ +- OMAP5_IOPAD(0x01e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data3 */ +- OMAP5_IOPAD(0x01ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data0 */ +- OMAP5_IOPAD(0x01ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data1 */ +- >; +- }; +- +- mmc2_pins: pinmux_mmc2_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x0040, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_clk */ +- OMAP5_IOPAD(0x0042, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_cmd */ +- OMAP5_IOPAD(0x0044, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data0 */ +- OMAP5_IOPAD(0x0046, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data1 */ +- OMAP5_IOPAD(0x0048, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data2 */ +- OMAP5_IOPAD(0x004a, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data3 */ +- OMAP5_IOPAD(0x004c, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data4 */ +- OMAP5_IOPAD(0x004e, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data5 */ +- OMAP5_IOPAD(0x0050, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data6 */ +- OMAP5_IOPAD(0x0052, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data7 */ +- >; +- }; +- +- mmc3_pins: pinmux_mmc3_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */ +- OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */ +- OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */ +- OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */ +- OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */ +- OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */ +- >; +- }; +- +- wlan_gpios_pins: pinmux_wlan_gpios_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_ul_data.gpio4_109 */ +- OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_dl_data.gpio4_110 */ +- >; +- }; +- +- usbhost_pins: pinmux_usbhost_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x00c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ +- OMAP5_IOPAD(0x00c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ +- +- OMAP5_IOPAD(0x01dc, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ +- OMAP5_IOPAD(0x01de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ +- +- OMAP5_IOPAD(0x00a8, PIN_OUTPUT | MUX_MODE6) /* hsi2_caready.gpio3_76 */ +- OMAP5_IOPAD(0x00b6, PIN_OUTPUT | MUX_MODE6) /* hsi2_acdata.gpio3_83 */ +- >; +- }; +- +- dss_hdmi_pins: pinmux_dss_hdmi_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x013c, PIN_INPUT | MUX_MODE0) /* hdmi_cec */ +- OMAP5_IOPAD(0x0140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl */ +- OMAP5_IOPAD(0x0142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda */ +- >; +- }; +- +- lcd_pins: pinmux_lcd_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x0172, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* timer11_pwm_evt.gpio8_227 */ +- >; +- }; +- +- hdmi_conn_pins: pinmux_hdmi_conn_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x013e, PIN_INPUT | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ +- >; +- }; +- +- dss_dpi_pins: pinmux_dss_dpi_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x0104, PIN_OUTPUT | MUX_MODE3) /* rfbi_data15.dispc_data15 */ +- OMAP5_IOPAD(0x0106, PIN_OUTPUT | MUX_MODE3) /* rfbi_data14.dispc_data14 */ +- OMAP5_IOPAD(0x0108, PIN_OUTPUT | MUX_MODE3) /* rfbi_data13.dispc_data13 */ +- OMAP5_IOPAD(0x010a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data12.dispc_data12 */ +- OMAP5_IOPAD(0x010c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data11.dispc_data11 */ +- OMAP5_IOPAD(0x010e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data10.dispc_data10 */ +- OMAP5_IOPAD(0x0110, PIN_OUTPUT | MUX_MODE3) /* rfbi_data9.dispc_data9 */ +- OMAP5_IOPAD(0x0112, PIN_OUTPUT | MUX_MODE3) /* rfbi_data8.dispc_data8 */ +- OMAP5_IOPAD(0x0114, PIN_OUTPUT | MUX_MODE3) /* rfbi_data7.dispc_data7 */ +- OMAP5_IOPAD(0x0116, PIN_OUTPUT | MUX_MODE3) /* rfbi_data6.dispc_data6 */ +- OMAP5_IOPAD(0x0118, PIN_OUTPUT | MUX_MODE3) /* rfbi_data5.dispc_data5 */ +- OMAP5_IOPAD(0x011a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data4.dispc_data4 */ +- OMAP5_IOPAD(0x011c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data3.dispc_data3 */ +- OMAP5_IOPAD(0x011e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data2.dispc_data2 */ +- OMAP5_IOPAD(0x0120, PIN_OUTPUT | MUX_MODE3) /* rfbi_data1.dispc_data1 */ +- OMAP5_IOPAD(0x0122, PIN_OUTPUT | MUX_MODE3) /* rfbi_data0.dispc_data0 */ +- OMAP5_IOPAD(0x0124, PIN_OUTPUT | MUX_MODE3) /* rfbi_we.dispc_vsync */ +- OMAP5_IOPAD(0x0126, PIN_OUTPUT | MUX_MODE3) /* rfbi_cs0.dispc_hsync */ +- OMAP5_IOPAD(0x0128, PIN_OUTPUT | MUX_MODE3) /* rfbi_a0.dispc_de */ +- OMAP5_IOPAD(0x012a, PIN_OUTPUT | MUX_MODE3) /* rfbi_re.dispc_pclk */ +- OMAP5_IOPAD(0x012c, PIN_OUTPUT | MUX_MODE3) /* rfbi_hsync0.dispc_data17 */ +- OMAP5_IOPAD(0x012e, PIN_OUTPUT | MUX_MODE3) /* rfbi_te_vsync0.dispc_data16 */ +- OMAP5_IOPAD(0x0130, PIN_OUTPUT | MUX_MODE3) /* gpio6_182.dispc_data18 */ +- OMAP5_IOPAD(0x0132, PIN_OUTPUT | MUX_MODE3) /* gpio6_183.dispc_data19 */ +- OMAP5_IOPAD(0x0134, PIN_OUTPUT | MUX_MODE3) /* gpio6_184.dispc_data20 */ +- OMAP5_IOPAD(0x0136, PIN_OUTPUT | MUX_MODE3) /* gpio6_185.dispc_data21 */ +- OMAP5_IOPAD(0x0138, PIN_OUTPUT | MUX_MODE3) /* gpio6_186.dispc_data22 */ +- OMAP5_IOPAD(0x013a, PIN_OUTPUT | MUX_MODE3) /* gpio6_187.dispc_data23 */ +- >; +- }; +- +- mcspi2_pins: pinmux_mcspi1_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x00fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ +- OMAP5_IOPAD(0x00fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ +- OMAP5_IOPAD(0x0100, PIN_INPUT | MUX_MODE0) /* mcspi2_somi */ +- OMAP5_IOPAD(0x0102, PIN_INPUT | MUX_MODE0) /* mcspi2_cs0 */ +- >; +- }; +-}; +- +-&mcspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcspi2_pins>; +- +- /* touch controller */ +- ads7846@0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ads7846_pins>; +- +- compatible = "ti,ads7846"; +- vcc-supply = <&ads7846reg>; +- +- reg = <0>; /* CS0 */ +- spi-max-frequency = <1500000>; +- +- interrupt-parent = <&gpio1>; +- interrupts = <15 0>; /* gpio1_wk15 */ +- pendown-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; +- +- +- ti,x-min = /bits/ 16 <0x0>; +- ti,x-max = /bits/ 16 <0x0fff>; +- ti,y-min = /bits/ 16 <0x0>; +- ti,y-max = /bits/ 16 <0x0fff>; +- +- ti,x-plate-ohms = /bits/ 16 <180>; +- ti,pressure-max = /bits/ 16 <255>; +- +- ti,debounce-max = /bits/ 16 <30>; +- ti,debounce-tol = /bits/ 16 <10>; +- ti,debounce-rep = /bits/ 16 <1>; +- +- wakeup-source; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <&ldo9_reg>; +- bus-width = <4>; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- vmmc-supply = <&vmmcsd_fixed>; +- bus-width = <8>; +- ti,non-removable; +-}; +- +-&mmc3 { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &mmc3_pins +- &wlan_gpios_pins +- >; +- vmmc-supply = <&vwlan_fixed>; +- bus-width = <4>; +- ti,non-removable; +-}; +- +-&mmc4 { +- status = "disabled"; +-}; +- +-&mmc5 { +- status = "disabled"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- +- clock-frequency = <400000>; +- +- at24@50 { +- compatible = "atmel,24c02"; +- pagesize = <16>; +- reg = <0x50>; +- }; +- +- palmas: palmas@48 { +- compatible = "ti,palmas"; +- reg = <0x48>; +- pinctrl-0 = <&palmas_sys_nirq_pins>; +- pinctrl-names = "default"; +- /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */ +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,system-power-controller; +- +- extcon_usb3: palmas_usb { +- compatible = "ti,palmas-usb-vid"; +- ti,enable-vbus-detection; +- ti,enable-id-detection; +- ti,wakeup; +- }; +- +- rtc { +- compatible = "ti,palmas-rtc"; +- interrupt-parent = <&palmas>; +- interrupts = <8 IRQ_TYPE_NONE>; +- }; +- +- palmas_pmic { +- compatible = "ti,palmas-pmic"; +- interrupt-parent = <&palmas>; +- interrupts = <14 IRQ_TYPE_NONE>; +- interrupt-names = "short-irq"; +- +- ti,ldo6-vibrator; +- +- regulators { +- smps123_reg: smps123 { +- /* VDD_OPP_MPU */ +- regulator-name = "smps123"; +- regulator-min-microvolt = < 600000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps45_reg: smps45 { +- /* VDD_OPP_MM */ +- regulator-name = "smps45"; +- regulator-min-microvolt = < 600000>; +- regulator-max-microvolt = <1310000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps6_reg: smps6 { +- /* VDD_DDR3 - over VDD_SMPS6 */ +- regulator-name = "smps6"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps7_reg: smps7 { +- /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */ +- regulator-name = "smps7"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps8_reg: smps8 { +- /* VDD_OPP_CORE */ +- regulator-name = "smps8"; +- regulator-min-microvolt = < 600000>; +- regulator-max-microvolt = <1310000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps9_reg: smps9 { +- /* VDDA_2v1_AUD over VDD_2v1 */ +- regulator-name = "smps9"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- ti,smps-range = <0x80>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps10_out2_reg: smps10_out2 { +- /* VBUS_5V_OTG */ +- regulator-name = "smps10_out2"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps10_out1_reg: smps10_out1 { +- /* VBUS_5V_OTG */ +- regulator-name = "smps10_out1"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- ldo1_reg: ldo1 { +- /* VDDAPHY_CAM: vdda_csiport */ +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo2_reg: ldo2 { +- /* VDD_3V3_WLAN */ +- regulator-name = "ldo2"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <1000>; +- }; +- +- ldo3_reg: ldo3 { +- /* VCC_1V5_AUD */ +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo4_reg: ldo4 { +- /* VDDAPHY_DISP: vdda_dsiport/hdmi */ +- regulator-name = "ldo4"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo5_reg: ldo5 { +- /* VDDA_1V8_PHY: usb/sata/hdmi.. */ +- regulator-name = "ldo5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo6_reg: ldo6 { +- /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */ +- regulator-name = "ldo6"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo7_reg: ldo7 { +- /* VDD_VPP: vpp1 */ +- regulator-name = "ldo7"; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- /* Only for efuse reprograming! */ +- status = "disabled"; +- }; +- +- ldo8_reg: ldo8 { +- /* VDD_3V_GP: act led/serial console */ +- regulator-name = "ldo8"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo9_reg: ldo9 { +- /* VCC_DV_SDIO: vdds_sdcard */ +- regulator-name = "ldo9"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- }; +- +- ldoln_reg: ldoln { +- /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */ +- regulator-name = "ldoln"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldousb_reg: ldousb { +- /* VDDA_3V_USB: VDDA_USBHS33 */ +- regulator-name = "ldousb"; +- regulator-min-microvolt = <3250000>; +- regulator-max-microvolt = <3250000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- regen3_reg: regen3 { +- /* REGEN3 controls LDO9 supply to card */ +- regulator-name = "regen3"; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- +- clock-frequency = <100000>; +-}; +- +-&usbhshost { +- port2-mode = "ehci-hsic"; +- port3-mode = "ehci-hsic"; +-}; +- +-&usbhsehci { +- phys = <0 &hsusb2_phy &hsusb3_phy>; +-}; +- +-&usb3 { +- extcon = <&extcon_usb3>; +- vbus-supply = <&smps10_out1_reg>; +-}; +- +-&cpu0 { +- cpu0-supply = <&smps123_reg>; +-}; +- +-&dss { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_dpi_pins>; +- +- port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- dpi_dvi_out: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&tfp410_in>; +- data-lines = <24>; +- }; +- +- dpi_lcd_out: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&lcd_in>; +- data-lines = <24>; +- }; +- }; +-}; +- +-&dsi2 { +- status = "okay"; +- vdd-supply = <&ldo4_reg>; +-}; +- +-&hdmi { +- status = "okay"; +- vdda-supply = <&ldo4_reg>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_hdmi_pins>; +- +- port { +- hdmi_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- lanes = <1 0 3 2 5 4 7 6>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap5-core-thermal.dtsi b/scripts/dtc/include-prefixes/arm/omap5-core-thermal.dtsi +deleted file mode 100644 +index 02e76338bfbc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap5-core-thermal.dtsi ++++ /dev/null +@@ -1,28 +0,0 @@ +-/* +- * Device Tree Source for OMAP543x SoC CORE thermal +- * +- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ +- * Contact: Eduardo Valentin +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-#include +- +-core_thermal: core_thermal { +- polling-delay-passive = <250>; /* milliseconds */ +- polling-delay = <500>; /* milliseconds */ +- +- /* sensor ID */ +- thermal-sensors = <&bandgap 2>; +- +- trips { +- core_crit: core_crit { +- temperature = <125000>; /* milliCelsius */ +- hysteresis = <2000>; /* milliCelsius */ +- type = "critical"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap5-gpu-thermal.dtsi b/scripts/dtc/include-prefixes/arm/omap5-gpu-thermal.dtsi +deleted file mode 100644 +index bf8fa9372e57..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap5-gpu-thermal.dtsi ++++ /dev/null +@@ -1,28 +0,0 @@ +-/* +- * Device Tree Source for OMAP543x SoC GPU thermal +- * +- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ +- * Contact: Eduardo Valentin +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-#include +- +-gpu_thermal: gpu_thermal { +- polling-delay-passive = <250>; /* milliseconds */ +- polling-delay = <500>; /* milliseconds */ +- +- /* sensor ID */ +- thermal-sensors = <&bandgap 1>; +- +- trips { +- gpu_crit: gpu_crit { +- temperature = <125000>; /* milliCelsius */ +- hysteresis = <2000>; /* milliCelsius */ +- type = "critical"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap5-igep0050.dts b/scripts/dtc/include-prefixes/arm/omap5-igep0050.dts +deleted file mode 100644 +index 76e499d89d24..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap5-igep0050.dts ++++ /dev/null +@@ -1,136 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz/ +- */ +-/dts-v1/; +- +-#include +-#include "omap5-board-common.dtsi" +- +-/ { +- model = "IGEPv5"; +- compatible = "isee,omap5-igep0050", "ti,omap5"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0 0x7f000000>; /* 2032 MB */ +- }; +- +- aliases { +- ethernet = ðernet; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&power_button_pin>; +- pinctrl-names = "default"; +- +- power-button { +- label = "Power Button"; +- linux,code = ; +- gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led@1 { +- label = "board:green:usr0"; +- gpios = <&tca6416 1 0>; +- default-state = "off"; +- }; +- led@2 { +- label = "board:red:usr1"; +- gpios = <&tca6416 2 0>; +- default-state = "off"; +- }; +- led@3 { +- label = "board:blue:usr1"; +- gpios = <&tca6416 3 0>; +- default-state = "off"; +- }; +- }; +-}; +- +-&hdmi { +- vdda-supply = <&ldo7_reg>; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pins>; +- +- tca6416: tca6416@21 { +- compatible = "ti,tca6416"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-/* LDO4 is VPP1 - ball AD9 */ +-&ldo4_reg { +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +-}; +- +-/* +- * LDO7 is used for HDMI: VDDA_DSIPORTA - ball AA33, VDDA_DSIPORTC - ball AE33, +- * VDDA_HDMI - ball AN25 +- */ +-&ldo7_reg { +- status = "okay"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +-}; +- +-&omap5_pmx_core { +- i2c4_pins: pinmux_i2c4_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* i2c4_scl */ +- OMAP5_IOPAD(0x0fa, PIN_INPUT | MUX_MODE0) /* i2c4_sda */ +- >; +- }; +- +- power_button_pin: pinctrl_power_button_pin { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x086, PIN_INPUT | MUX_MODE6) /* gpio4_118 */ +- >; +- }; +-}; +- +-&tpd12s015 { +- gpios = <&tca6416 11 0>, /* TCA6416 P01, CT_CP_HDP */ +- <&tca6416 12 0>, /* TCA6416 P00, LS_OE*/ +- <&gpio7 1 0>, /* 193, HPD */ +- <&gpio7 2 0>, /* 194, SCL */ +- <&gpio7 3 0>; /* 195, SDA */ +-}; +- +-&twl6040 { +- ti,audpwron-gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio line 144 */ +-}; +- +-&twl6040_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_144 */ +- OMAP5_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */ +- >; +-}; +- +-&usbhsehci { +- #address-cells = <1>; +- #size-cells = <0>; +- +- hub@2 { +- compatible = "usb424,3503"; +- reg = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethernet: usbether@3 { +- compatible = "usb424,7500"; +- reg = <3>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap5-l4-abe.dtsi b/scripts/dtc/include-prefixes/arm/omap5-l4-abe.dtsi +deleted file mode 100644 +index a03bca5a3584..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap5-l4-abe.dtsi ++++ /dev/null +@@ -1,456 +0,0 @@ +-&l4_abe { /* 0x40100000 */ +- compatible = "ti,omap5-l4-abe", "simple-pm-bus"; +- reg = <0x40100000 0x400>, +- <0x40100400 0x400>; +- reg-names = "la", "ap"; +- power-domains = <&prm_abe>; +- /* OMAP5_L4_ABE_CLKCTRL is read-only */ +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ +- <0x49000000 0x49000000 0x100000>; +- segment@0 { /* 0x40100000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = +- /* CPU to L4 ABE mapping */ +- <0x00000000 0x00000000 0x000400>, /* ap 0 */ +- <0x00000400 0x00000400 0x000400>, /* ap 1 */ +- <0x00022000 0x00022000 0x001000>, /* ap 2 */ +- <0x00023000 0x00023000 0x001000>, /* ap 3 */ +- <0x00024000 0x00024000 0x001000>, /* ap 4 */ +- <0x00025000 0x00025000 0x001000>, /* ap 5 */ +- <0x00026000 0x00026000 0x001000>, /* ap 6 */ +- <0x00027000 0x00027000 0x001000>, /* ap 7 */ +- <0x00028000 0x00028000 0x001000>, /* ap 8 */ +- <0x00029000 0x00029000 0x001000>, /* ap 9 */ +- <0x0002a000 0x0002a000 0x001000>, /* ap 10 */ +- <0x0002b000 0x0002b000 0x001000>, /* ap 11 */ +- <0x0002e000 0x0002e000 0x001000>, /* ap 12 */ +- <0x0002f000 0x0002f000 0x001000>, /* ap 13 */ +- <0x00030000 0x00030000 0x001000>, /* ap 14 */ +- <0x00031000 0x00031000 0x001000>, /* ap 15 */ +- <0x00032000 0x00032000 0x001000>, /* ap 16 */ +- <0x00033000 0x00033000 0x001000>, /* ap 17 */ +- <0x00038000 0x00038000 0x001000>, /* ap 18 */ +- <0x00039000 0x00039000 0x001000>, /* ap 19 */ +- <0x0003a000 0x0003a000 0x001000>, /* ap 20 */ +- <0x0003b000 0x0003b000 0x001000>, /* ap 21 */ +- <0x0003c000 0x0003c000 0x001000>, /* ap 22 */ +- <0x0003d000 0x0003d000 0x001000>, /* ap 23 */ +- <0x0003e000 0x0003e000 0x001000>, /* ap 24 */ +- <0x0003f000 0x0003f000 0x001000>, /* ap 25 */ +- <0x00080000 0x00080000 0x010000>, /* ap 26 */ +- <0x00080000 0x00080000 0x001000>, /* ap 27 */ +- <0x000a0000 0x000a0000 0x010000>, /* ap 28 */ +- <0x000a0000 0x000a0000 0x001000>, /* ap 29 */ +- <0x000c0000 0x000c0000 0x010000>, /* ap 30 */ +- <0x000c0000 0x000c0000 0x001000>, /* ap 31 */ +- <0x000f1000 0x000f1000 0x001000>, /* ap 32 */ +- <0x000f2000 0x000f2000 0x001000>, /* ap 33 */ +- +- /* L3 to L4 ABE mapping */ +- <0x49000000 0x49000000 0x000400>, /* ap 0 */ +- <0x49000400 0x49000400 0x000400>, /* ap 1 */ +- <0x49022000 0x49022000 0x001000>, /* ap 2 */ +- <0x49023000 0x49023000 0x001000>, /* ap 3 */ +- <0x49024000 0x49024000 0x001000>, /* ap 4 */ +- <0x49025000 0x49025000 0x001000>, /* ap 5 */ +- <0x49026000 0x49026000 0x001000>, /* ap 6 */ +- <0x49027000 0x49027000 0x001000>, /* ap 7 */ +- <0x49028000 0x49028000 0x001000>, /* ap 8 */ +- <0x49029000 0x49029000 0x001000>, /* ap 9 */ +- <0x4902a000 0x4902a000 0x001000>, /* ap 10 */ +- <0x4902b000 0x4902b000 0x001000>, /* ap 11 */ +- <0x4902e000 0x4902e000 0x001000>, /* ap 12 */ +- <0x4902f000 0x4902f000 0x001000>, /* ap 13 */ +- <0x49030000 0x49030000 0x001000>, /* ap 14 */ +- <0x49031000 0x49031000 0x001000>, /* ap 15 */ +- <0x49032000 0x49032000 0x001000>, /* ap 16 */ +- <0x49033000 0x49033000 0x001000>, /* ap 17 */ +- <0x49038000 0x49038000 0x001000>, /* ap 18 */ +- <0x49039000 0x49039000 0x001000>, /* ap 19 */ +- <0x4903a000 0x4903a000 0x001000>, /* ap 20 */ +- <0x4903b000 0x4903b000 0x001000>, /* ap 21 */ +- <0x4903c000 0x4903c000 0x001000>, /* ap 22 */ +- <0x4903d000 0x4903d000 0x001000>, /* ap 23 */ +- <0x4903e000 0x4903e000 0x001000>, /* ap 24 */ +- <0x4903f000 0x4903f000 0x001000>, /* ap 25 */ +- <0x49080000 0x49080000 0x010000>, /* ap 26 */ +- <0x49080000 0x49080000 0x001000>, /* ap 27 */ +- <0x490a0000 0x490a0000 0x010000>, /* ap 28 */ +- <0x490a0000 0x490a0000 0x001000>, /* ap 29 */ +- <0x490c0000 0x490c0000 0x010000>, /* ap 30 */ +- <0x490c0000 0x490c0000 0x001000>, /* ap 31 */ +- <0x490f1000 0x490f1000 0x001000>, /* ap 32 */ +- <0x490f2000 0x490f2000 0x001000>; /* ap 33 */ +- +- target-module@22000 { /* 0x40122000, ap 2 02.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x2208c 0x4>; +- reg-names = "sysc"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x22000 0x1000>, +- <0x49022000 0x49022000 0x1000>; +- +- mcbsp1: mcbsp@0 { +- compatible = "ti,omap4-mcbsp"; +- reg = <0x0 0xff>, /* MPU private access */ +- <0x49022000 0xff>; /* L3 Interconnect */ +- reg-names = "mpu", "dma"; +- interrupts = ; +- interrupt-names = "common"; +- ti,buffer-size = <128>; +- dmas = <&sdma 33>, +- <&sdma 34>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- }; +- +- target-module@24000 { /* 0x40124000, ap 4 04.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x2408c 0x4>; +- reg-names = "sysc"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x24000 0x1000>, +- <0x49024000 0x49024000 0x1000>; +- +- mcbsp2: mcbsp@0 { +- compatible = "ti,omap4-mcbsp"; +- reg = <0x0 0xff>, /* MPU private access */ +- <0x49024000 0xff>; /* L3 Interconnect */ +- reg-names = "mpu", "dma"; +- interrupts = ; +- interrupt-names = "common"; +- ti,buffer-size = <128>; +- dmas = <&sdma 17>, +- <&sdma 18>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- }; +- +- target-module@26000 { /* 0x40126000, ap 6 06.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x2608c 0x4>; +- reg-names = "sysc"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x26000 0x1000>, +- <0x49026000 0x49026000 0x1000>; +- +- mcbsp3: mcbsp@0 { +- compatible = "ti,omap4-mcbsp"; +- reg = <0x0 0xff>, /* MPU private access */ +- <0x49026000 0xff>; /* L3 Interconnect */ +- reg-names = "mpu", "dma"; +- interrupts = ; +- interrupt-names = "common"; +- ti,buffer-size = <128>; +- dmas = <&sdma 19>, +- <&sdma 20>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- }; +- +- target-module@28000 { /* 0x40128000, ap 8 08.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x28000 0x1000>, +- <0x49028000 0x49028000 0x1000>; +- }; +- +- target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2a000 0x1000>, +- <0x4902a000 0x4902a000 0x1000>; +- }; +- +- target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x2e000 0x4>, +- <0x2e010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2e000 0x1000>, +- <0x4902e000 0x4902e000 0x1000>; +- +- dmic: dmic@0 { +- compatible = "ti,omap4-dmic"; +- reg = <0x0 0x7f>, /* MPU private access */ +- <0x4902e000 0x7f>; /* L3 Interconnect */ +- reg-names = "mpu", "dma"; +- interrupts = ; +- dmas = <&sdma 67>; +- dma-names = "up_link"; +- status = "disabled"; +- }; +- }; +- +- target-module@30000 { /* 0x40130000, ap 14 0e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x30000 0x1000>, +- <0x49030000 0x49030000 0x1000>; +- }; +- +- mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x32000 0x4>, +- <0x32010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x32000 0x1000>, +- <0x49032000 0x49032000 0x1000>; +- +- /* Must be only enabled for boards with pdmclk wired */ +- status = "disabled"; +- +- mcpdm: mcpdm@0 { +- compatible = "ti,omap4-mcpdm"; +- reg = <0x0 0x7f>, /* MPU private access */ +- <0x49032000 0x7f>; /* L3 Interconnect */ +- reg-names = "mpu", "dma"; +- interrupts = ; +- dmas = <&sdma 65>, +- <&sdma 66>; +- dma-names = "up_link", "dn_link"; +- }; +- }; +- +- target-module@38000 { /* 0x40138000, ap 18 12.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x38000 0x4>, +- <0x38010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x38000 0x1000>, +- <0x49038000 0x49038000 0x1000>; +- +- timer5: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>, +- <0x49038000 0x80>; +- clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>, +- <&dss_syc_gfclk_div>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-dsp; +- ti,timer-pwm; +- }; +- }; +- +- target-module@3a000 { /* 0x4013a000, ap 20 14.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x3a000 0x4>, +- <0x3a010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3a000 0x1000>, +- <0x4903a000 0x4903a000 0x1000>; +- +- timer6: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>, +- <0x4903a000 0x80>; +- clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>, +- <&dss_syc_gfclk_div>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-dsp; +- ti,timer-pwm; +- }; +- }; +- +- target-module@3c000 { /* 0x4013c000, ap 22 16.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x3c000 0x4>, +- <0x3c010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3c000 0x1000>, +- <0x4903c000 0x4903c000 0x1000>; +- +- timer7: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>, +- <0x4903c000 0x80>; +- clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>, +- <&dss_syc_gfclk_div>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-dsp; +- }; +- }; +- +- target-module@3e000 { /* 0x4013e000, ap 24 18.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x3e000 0x4>, +- <0x3e010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3e000 0x1000>, +- <0x4903e000 0x4903e000 0x1000>; +- +- timer8: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>, +- <0x4903e000 0x80>; +- clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>, +- <&dss_syc_gfclk_div>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-dsp; +- ti,timer-pwm; +- }; +- }; +- +- target-module@80000 { /* 0x40180000, ap 26 1a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x80000 0x10000>, +- <0x49080000 0x49080000 0x10000>; +- }; +- +- target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa0000 0x10000>, +- <0x490a0000 0x490a0000 0x10000>; +- }; +- +- target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc0000 0x10000>, +- <0x490c0000 0x490c0000 0x10000>; +- }; +- +- target-module@f1000 { /* 0x401f1000, ap 32 20.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xf1000 0x4>, +- <0xf1010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ +- clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf1000 0x1000>, +- <0x490f1000 0x490f1000 0x1000>; +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap5-l4.dtsi b/scripts/dtc/include-prefixes/arm/omap5-l4.dtsi +deleted file mode 100644 +index 06cc3a19ddaa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap5-l4.dtsi ++++ /dev/null +@@ -1,2502 +0,0 @@ +-&l4_cfg { /* 0x4a000000 */ +- compatible = "ti,omap5-l4-cfg", "simple-pm-bus"; +- power-domains = <&prm_core>; +- clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>; +- clock-names = "fck"; +- reg = <0x4a000000 0x800>, +- <0x4a000800 0x800>, +- <0x4a001000 0x1000>; +- reg-names = "ap", "la", "ia0"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ +- <0x00080000 0x4a080000 0x080000>, /* segment 1 */ +- <0x00100000 0x4a100000 0x080000>, /* segment 2 */ +- <0x00180000 0x4a180000 0x080000>, /* segment 3 */ +- <0x00200000 0x4a200000 0x080000>, /* segment 4 */ +- <0x00280000 0x4a280000 0x080000>, /* segment 5 */ +- <0x00300000 0x4a300000 0x080000>; /* segment 6 */ +- +- segment@0 { /* 0x4a000000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ +- <0x00001000 0x00001000 0x001000>, /* ap 1 */ +- <0x00000800 0x00000800 0x000800>, /* ap 2 */ +- <0x00002000 0x00002000 0x001000>, /* ap 3 */ +- <0x00003000 0x00003000 0x001000>, /* ap 4 */ +- <0x00004000 0x00004000 0x001000>, /* ap 5 */ +- <0x00005000 0x00005000 0x001000>, /* ap 6 */ +- <0x00056000 0x00056000 0x001000>, /* ap 7 */ +- <0x00057000 0x00057000 0x001000>, /* ap 8 */ +- <0x0005c000 0x0005c000 0x001000>, /* ap 9 */ +- <0x00058000 0x00058000 0x001000>, /* ap 10 */ +- <0x00062000 0x00062000 0x001000>, /* ap 11 */ +- <0x00063000 0x00063000 0x001000>, /* ap 12 */ +- <0x00008000 0x00008000 0x002000>, /* ap 21 */ +- <0x0000a000 0x0000a000 0x001000>, /* ap 22 */ +- <0x00066000 0x00066000 0x001000>, /* ap 23 */ +- <0x00067000 0x00067000 0x001000>, /* ap 24 */ +- <0x0005e000 0x0005e000 0x002000>, /* ap 69 */ +- <0x00060000 0x00060000 0x001000>, /* ap 70 */ +- <0x00064000 0x00064000 0x001000>, /* ap 71 */ +- <0x00065000 0x00065000 0x001000>, /* ap 72 */ +- <0x0005a000 0x0005a000 0x001000>, /* ap 77 */ +- <0x0005b000 0x0005b000 0x001000>, /* ap 78 */ +- <0x00070000 0x00070000 0x004000>, /* ap 79 */ +- <0x00074000 0x00074000 0x001000>, /* ap 80 */ +- <0x00075000 0x00075000 0x001000>, /* ap 81 */ +- <0x00076000 0x00076000 0x001000>, /* ap 82 */ +- <0x00020000 0x00020000 0x020000>, /* ap 109 */ +- <0x00040000 0x00040000 0x001000>, /* ap 110 */ +- <0x00059000 0x00059000 0x001000>; /* ap 111 */ +- +- target-module@2000 { /* 0x4a002000, ap 3 44.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x2000 0x4>; +- reg-names = "rev"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2000 0x1000>; +- +- scm_core: scm@0 { +- compatible = "ti,omap5-scm-core", "simple-bus"; +- reg = <0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x800>; +- +- scm_conf: scm_conf@0 { +- compatible = "syscon"; +- reg = <0x0 0x800>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- }; +- +- scm_padconf_core: scm@800 { +- compatible = "ti,omap5-scm-padconf-core", +- "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x800 0x800>; +- +- omap5_pmx_core: pinmux@40 { +- compatible = "ti,omap5-padconf", +- "pinctrl-single"; +- reg = <0x40 0x01b6>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <1>; +- #interrupt-cells = <1>; +- interrupt-controller; +- pinctrl-single,register-width = <16>; +- pinctrl-single,function-mask = <0x7fff>; +- }; +- +- omap5_padconf_global: omap5_padconf_global@5a0 { +- compatible = "syscon", +- "simple-bus"; +- reg = <0x5a0 0xec>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x5a0 0xec>; +- +- pbias_regulator: pbias_regulator@60 { +- compatible = "ti,pbias-omap5", "ti,pbias-omap"; +- reg = <0x60 0x4>; +- syscon = <&omap5_padconf_global>; +- pbias_mmc_reg: pbias_mmc_omap5 { +- regulator-name = "pbias_mmc_omap5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +- }; +- }; +- }; +- +- target-module@4000 { /* 0x4a004000, ap 5 5c.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x4000 0x4>; +- reg-names = "rev"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4000 0x1000>; +- +- cm_core_aon: cm_core_aon@0 { +- compatible = "ti,omap5-cm-core-aon", +- "simple-bus"; +- reg = <0x0 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x1000>; +- +- cm_core_aon_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- cm_core_aon_clockdomains: clockdomains { +- }; +- }; +- }; +- +- target-module@8000 { /* 0x4a008000, ap 21 4c.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x8000 0x4>; +- reg-names = "rev"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x8000 0x2000>; +- +- cm_core: cm_core@0 { +- compatible = "ti,omap5-cm-core", "simple-bus"; +- reg = <0x0 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x2000>; +- +- cm_core_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- cm_core_clockdomains: clockdomains { +- }; +- }; +- }; +- +- target-module@20000 { /* 0x4a020000, ap 109 08.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x20000 0x4>, +- <0x20010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ +- clocks = <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x20000 0x20000>; +- +- usb3: omap_dwc3@0 { +- compatible = "ti,dwc3"; +- reg = <0x0 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <1>; +- utmi-mode = <2>; +- ranges = <0 0 0x20000>; +- dwc3: usb@10000 { +- compatible = "snps,dwc3"; +- reg = <0x10000 0x10000>; +- interrupts = , +- , +- ; +- interrupt-names = "peripheral", +- "host", +- "otg"; +- phys = <&usb2_phy>, <&usb3_phy>; +- phy-names = "usb2-phy", "usb3-phy"; +- dr_mode = "peripheral"; +- }; +- }; +- }; +- +- target-module@56000 { /* 0x4a056000, ap 7 02.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x56000 0x4>, +- <0x5602c 0x4>, +- <0x56028 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, dma_clkdm */ +- clocks = <&dma_clkctrl OMAP5_DMA_SYSTEM_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x56000 0x1000>; +- +- sdma: dma-controller@0 { +- compatible = "ti,omap4430-sdma", "ti,omap-sdma"; +- reg = <0x0 0x1000>; +- interrupts = , +- , +- , +- ; +- #dma-cells = <1>; +- dma-channels = <32>; +- dma-requests = <127>; +- }; +- }; +- +- target-module@58000 { /* 0x4a058000, ap 10 06.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00058000 0x00001000>, +- <0x00001000 0x00059000 0x00001000>, +- <0x00002000 0x0005a000 0x00001000>, +- <0x00003000 0x0005b000 0x00001000>; +- }; +- +- target-module@5e000 { /* 0x4a05e000, ap 69 2a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5e000 0x2000>; +- }; +- +- target-module@62000 { /* 0x4a062000, ap 11 0e.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x62000 0x4>, +- <0x62010 0x4>, +- <0x62014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ +- clocks = <&l3init_clkctrl OMAP5_USB_TLL_HS_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x62000 0x1000>; +- +- usbhstll: usbhstll@0 { +- compatible = "ti,usbhs-tll"; +- reg = <0x0 0x1000>; +- interrupts = ; +- }; +- }; +- +- target-module@64000 { /* 0x4a064000, ap 71 1e.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x64000 0x4>, +- <0x64010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ +- clocks = <&l3init_clkctrl OMAP5_USB_HOST_HS_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x64000 0x1000>; +- +- usbhshost: usbhshost@0 { +- compatible = "ti,usbhs-host"; +- reg = <0x0 0x800>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x1000>; +- clocks = <&l3init_60m_fclk>, +- <&xclk60mhsp1_ck>, +- <&xclk60mhsp2_ck>; +- clock-names = "refclk_60m_int", +- "refclk_60m_ext_p1", +- "refclk_60m_ext_p2"; +- +- usbhsohci: ohci@800 { +- compatible = "ti,ohci-omap3"; +- reg = <0x800 0x400>; +- interrupts = ; +- remote-wakeup-connected; +- }; +- +- usbhsehci: ehci@c00 { +- compatible = "ti,ehci-omap"; +- reg = <0xc00 0x400>; +- interrupts = ; +- }; +- }; +- }; +- +- target-module@66000 { /* 0x4a066000, ap 23 0a.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x66000 0x4>, +- <0x66010 0x4>, +- <0x66014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */ +- clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; +- clock-names = "fck"; +- resets = <&prm_dsp 1>; +- reset-names = "rstctrl"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x66000 0x1000>; +- +- mmu_dsp: mmu@0 { +- compatible = "ti,omap4-iommu"; +- reg = <0x0 0x100>; +- interrupts = ; +- #iommu-cells = <0>; +- }; +- }; +- +- target-module@70000 { /* 0x4a070000, ap 79 2e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x70000 0x4000>; +- }; +- +- target-module@75000 { /* 0x4a075000, ap 81 32.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x75000 0x1000>; +- }; +- }; +- +- segment@80000 { /* 0x4a080000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ +- <0x0005a000 0x000da000 0x001000>, /* ap 14 */ +- <0x0005b000 0x000db000 0x001000>, /* ap 15 */ +- <0x0005c000 0x000dc000 0x001000>, /* ap 16 */ +- <0x0005d000 0x000dd000 0x001000>, /* ap 17 */ +- <0x0005e000 0x000de000 0x001000>, /* ap 18 */ +- <0x00060000 0x000e0000 0x001000>, /* ap 19 */ +- <0x00061000 0x000e1000 0x001000>, /* ap 20 */ +- <0x00074000 0x000f4000 0x001000>, /* ap 25 */ +- <0x00075000 0x000f5000 0x001000>, /* ap 26 */ +- <0x00076000 0x000f6000 0x001000>, /* ap 27 */ +- <0x00077000 0x000f7000 0x001000>, /* ap 28 */ +- <0x00036000 0x000b6000 0x001000>, /* ap 65 */ +- <0x00037000 0x000b7000 0x001000>, /* ap 66 */ +- <0x0004d000 0x000cd000 0x001000>, /* ap 67 */ +- <0x0004e000 0x000ce000 0x001000>, /* ap 68 */ +- <0x00000000 0x00080000 0x004000>, /* ap 83 */ +- <0x00004000 0x00084000 0x001000>, /* ap 84 */ +- <0x00005000 0x00085000 0x001000>, /* ap 85 */ +- <0x00006000 0x00086000 0x001000>, /* ap 86 */ +- <0x00007000 0x00087000 0x001000>, /* ap 87 */ +- <0x00008000 0x00088000 0x001000>, /* ap 88 */ +- <0x00010000 0x00090000 0x004000>, /* ap 89 */ +- <0x00014000 0x00094000 0x001000>, /* ap 90 */ +- <0x00015000 0x00095000 0x001000>, /* ap 91 */ +- <0x00016000 0x00096000 0x001000>, /* ap 92 */ +- <0x00017000 0x00097000 0x001000>, /* ap 93 */ +- <0x00018000 0x00098000 0x001000>, /* ap 94 */ +- <0x00020000 0x000a0000 0x004000>, /* ap 95 */ +- <0x00024000 0x000a4000 0x001000>, /* ap 96 */ +- <0x00025000 0x000a5000 0x001000>, /* ap 97 */ +- <0x00026000 0x000a6000 0x001000>, /* ap 98 */ +- <0x00027000 0x000a7000 0x001000>, /* ap 99 */ +- <0x00028000 0x000a8000 0x001000>; /* ap 100 */ +- +- target-module@0 { /* 0x4a080000, ap 83 28.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x0 0x4>, +- <0x10 0x4>, +- <0x14 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ +- clocks = <&l3init_clkctrl OMAP5_OCP2SCP1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x00004000>, +- <0x00004000 0x00004000 0x00001000>, +- <0x00005000 0x00005000 0x00001000>, +- <0x00006000 0x00006000 0x00001000>, +- <0x00007000 0x00007000 0x00001000>; +- +- ocp2scp@0 { +- compatible = "ti,omap-ocp2scp"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0 0x20>; +- }; +- +- usb2_phy: usb2phy@4000 { +- compatible = "ti,omap-usb2"; +- reg = <0x4000 0x7c>; +- syscon-phy-power = <&scm_conf 0x300>; +- clocks = <&usb_phy_cm_clk32k>, +- <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; +- clock-names = "wkupclk", "refclk"; +- #phy-cells = <0>; +- }; +- +- usb3_phy: usb3phy@4400 { +- compatible = "ti,omap-usb3"; +- reg = <0x4400 0x80>, +- <0x4800 0x64>, +- <0x4c00 0x40>; +- reg-names = "phy_rx", "phy_tx", "pll_ctrl"; +- syscon-phy-power = <&scm_conf 0x370>; +- clocks = <&usb_phy_cm_clk32k>, +- <&sys_clkin>, +- <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; +- clock-names = "wkupclk", +- "sysclk", +- "refclk"; +- #phy-cells = <0>; +- }; +- }; +- +- target-module@10000 { /* 0x4a090000, ap 89 36.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x10000 0x4>, +- <0x10010 0x4>, +- <0x10014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ +- clocks = <&l3init_clkctrl OMAP5_OCP2SCP3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00010000 0x00004000>, +- <0x00004000 0x00014000 0x00001000>, +- <0x00005000 0x00015000 0x00001000>, +- <0x00006000 0x00016000 0x00001000>, +- <0x00007000 0x00017000 0x00001000>; +- +- ocp2scp@0 { +- compatible = "ti,omap-ocp2scp"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x0 0x20>; +- }; +- +- sata_phy: phy@6000 { +- compatible = "ti,phy-pipe3-sata"; +- reg = <0x6000 0x80>, /* phy_rx */ +- <0x6400 0x64>, /* phy_tx */ +- <0x6800 0x40>; /* pll_ctrl */ +- reg-names = "phy_rx", "phy_tx", "pll_ctrl"; +- syscon-phy-power = <&scm_conf 0x374>; +- clocks = <&sys_clkin>, +- <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; +- clock-names = "sysclk", "refclk"; +- #phy-cells = <0>; +- }; +- }; +- +- target-module@20000 { /* 0x4a0a0000, ap 95 50.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00020000 0x00004000>, +- <0x00004000 0x00024000 0x00001000>, +- <0x00005000 0x00025000 0x00001000>, +- <0x00006000 0x00026000 0x00001000>, +- <0x00007000 0x00027000 0x00001000>; +- }; +- +- target-module@36000 { /* 0x4a0b6000, ap 65 6c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x36000 0x1000>; +- }; +- +- target-module@4d000 { /* 0x4a0cd000, ap 67 64.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4d000 0x1000>; +- }; +- +- target-module@59000 { /* 0x4a0d9000, ap 13 20.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x59000 0x1000>; +- }; +- +- target-module@5b000 { /* 0x4a0db000, ap 15 10.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5b000 0x1000>; +- }; +- +- target-module@5d000 { /* 0x4a0dd000, ap 17 18.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5d000 0x1000>; +- }; +- +- target-module@60000 { /* 0x4a0e0000, ap 19 54.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x60000 0x1000>; +- }; +- +- target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x74000 0x4>, +- <0x74010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = ; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ +- clocks = <&l4cfg_clkctrl OMAP5_MAILBOX_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x74000 0x1000>; +- +- mailbox: mailbox@0 { +- compatible = "ti,omap4-mailbox"; +- reg = <0x0 0x200>; +- interrupts = ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <3>; +- ti,mbox-num-fifos = <8>; +- mbox_ipu: mbox-ipu { +- ti,mbox-tx = <0 0 0>; +- ti,mbox-rx = <1 0 0>; +- }; +- mbox_dsp: mbox-dsp { +- ti,mbox-tx = <3 0 0>; +- ti,mbox-rx = <2 0 0>; +- }; +- }; +- }; +- +- target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x76000 0x4>, +- <0x76010 0x4>, +- <0x76014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ +- clocks = <&l4cfg_clkctrl OMAP5_SPINLOCK_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x76000 0x1000>; +- +- hwspinlock: spinlock@0 { +- compatible = "ti,omap4-hwspinlock"; +- reg = <0x0 0x1000>; +- #hwlock-cells = <1>; +- }; +- }; +- }; +- +- segment@100000 { /* 0x4a100000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */ +- <0x00003000 0x00103000 0x001000>, /* ap 60 */ +- <0x00008000 0x00108000 0x001000>, /* ap 61 */ +- <0x00009000 0x00109000 0x001000>, /* ap 62 */ +- <0x0000a000 0x0010a000 0x001000>, /* ap 63 */ +- <0x0000b000 0x0010b000 0x001000>, /* ap 64 */ +- <0x00040000 0x00140000 0x010000>, /* ap 101 */ +- <0x00050000 0x00150000 0x001000>; /* ap 102 */ +- +- target-module@2000 { /* 0x4a102000, ap 59 2c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2000 0x1000>; +- }; +- +- target-module@8000 { /* 0x4a108000, ap 61 26.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x8000 0x1000>; +- }; +- +- target-module@a000 { /* 0x4a10a000, ap 63 22.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa000 0x1000>; +- }; +- +- target-module@40000 { /* 0x4a140000, ap 101 16.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x400fc 4>, +- <0x41100 4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- power-domains = <&prm_l3init>; +- clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 0>; +- clock-names = "fck"; +- #size-cells = <1>; +- #address-cells = <1>; +- ranges = <0x0 0x40000 0x10000>; +- +- sata: sata@0 { +- compatible = "snps,dwc-ahci"; +- reg = <0 0x1100>, <0x1100 0x8>; +- interrupts = ; +- phys = <&sata_phy>; +- phy-names = "sata-phy"; +- clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; +- ports-implemented = <0x1>; +- }; +- }; +- }; +- +- segment@180000 { /* 0x4a180000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- segment@200000 { /* 0x4a200000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */ +- <0x0001f000 0x0021f000 0x001000>, /* ap 30 */ +- <0x0000a000 0x0020a000 0x001000>, /* ap 31 */ +- <0x0000b000 0x0020b000 0x001000>, /* ap 32 */ +- <0x00006000 0x00206000 0x001000>, /* ap 33 */ +- <0x00007000 0x00207000 0x001000>, /* ap 34 */ +- <0x00004000 0x00204000 0x001000>, /* ap 35 */ +- <0x00005000 0x00205000 0x001000>, /* ap 36 */ +- <0x00012000 0x00212000 0x001000>, /* ap 37 */ +- <0x00013000 0x00213000 0x001000>, /* ap 38 */ +- <0x0000c000 0x0020c000 0x001000>, /* ap 39 */ +- <0x0000d000 0x0020d000 0x001000>, /* ap 40 */ +- <0x00010000 0x00210000 0x001000>, /* ap 41 */ +- <0x00011000 0x00211000 0x001000>, /* ap 42 */ +- <0x00016000 0x00216000 0x001000>, /* ap 43 */ +- <0x00017000 0x00217000 0x001000>, /* ap 44 */ +- <0x00014000 0x00214000 0x001000>, /* ap 45 */ +- <0x00015000 0x00215000 0x001000>, /* ap 46 */ +- <0x00018000 0x00218000 0x001000>, /* ap 47 */ +- <0x00019000 0x00219000 0x001000>, /* ap 48 */ +- <0x00020000 0x00220000 0x001000>, /* ap 49 */ +- <0x00021000 0x00221000 0x001000>, /* ap 50 */ +- <0x00026000 0x00226000 0x001000>, /* ap 51 */ +- <0x00027000 0x00227000 0x001000>, /* ap 52 */ +- <0x00028000 0x00228000 0x001000>, /* ap 53 */ +- <0x00029000 0x00229000 0x001000>, /* ap 54 */ +- <0x0002a000 0x0022a000 0x001000>, /* ap 55 */ +- <0x0002b000 0x0022b000 0x001000>, /* ap 56 */ +- <0x0001c000 0x0021c000 0x001000>, /* ap 57 */ +- <0x0001d000 0x0021d000 0x001000>, /* ap 58 */ +- <0x0001a000 0x0021a000 0x001000>, /* ap 73 */ +- <0x0001b000 0x0021b000 0x001000>, /* ap 74 */ +- <0x00024000 0x00224000 0x001000>, /* ap 75 */ +- <0x00025000 0x00225000 0x001000>, /* ap 76 */ +- <0x00002000 0x00202000 0x001000>, /* ap 103 */ +- <0x00003000 0x00203000 0x001000>, /* ap 104 */ +- <0x00008000 0x00208000 0x001000>, /* ap 105 */ +- <0x00009000 0x00209000 0x001000>, /* ap 106 */ +- <0x00022000 0x00222000 0x001000>, /* ap 107 */ +- <0x00023000 0x00223000 0x001000>; /* ap 108 */ +- +- target-module@2000 { /* 0x4a202000, ap 103 3c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2000 0x1000>; +- }; +- +- target-module@4000 { /* 0x4a204000, ap 35 46.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4000 0x1000>; +- }; +- +- target-module@6000 { /* 0x4a206000, ap 33 4e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6000 0x1000>; +- }; +- +- target-module@8000 { /* 0x4a208000, ap 105 34.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x8000 0x1000>; +- }; +- +- target-module@a000 { /* 0x4a20a000, ap 31 30.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa000 0x1000>; +- }; +- +- target-module@c000 { /* 0x4a20c000, ap 39 14.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc000 0x1000>; +- }; +- +- target-module@10000 { /* 0x4a210000, ap 41 56.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10000 0x1000>; +- }; +- +- target-module@12000 { /* 0x4a212000, ap 37 52.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x12000 0x1000>; +- }; +- +- target-module@14000 { /* 0x4a214000, ap 45 1c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x14000 0x1000>; +- }; +- +- target-module@16000 { /* 0x4a216000, ap 43 42.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x16000 0x1000>; +- }; +- +- target-module@18000 { /* 0x4a218000, ap 47 1a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x18000 0x1000>; +- }; +- +- target-module@1a000 { /* 0x4a21a000, ap 73 3e.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1a000 0x1000>; +- }; +- +- target-module@1c000 { /* 0x4a21c000, ap 57 40.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1c000 0x1000>; +- }; +- +- target-module@1e000 { /* 0x4a21e000, ap 29 12.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1e000 0x1000>; +- }; +- +- target-module@20000 { /* 0x4a220000, ap 49 4a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x20000 0x1000>; +- }; +- +- target-module@22000 { /* 0x4a222000, ap 107 3a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x22000 0x1000>; +- }; +- +- target-module@24000 { /* 0x4a224000, ap 75 48.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x24000 0x1000>; +- }; +- +- target-module@26000 { /* 0x4a226000, ap 51 24.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x26000 0x1000>; +- }; +- +- target-module@28000 { /* 0x4a228000, ap 53 38.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x28000 0x1000>; +- }; +- +- target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2a000 0x1000>; +- }; +- }; +- +- segment@280000 { /* 0x4a280000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- segment@300000 { /* 0x4a300000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&l4_per { /* 0x48000000 */ +- compatible = "ti,omap5-l4-per", "simple-pm-bus"; +- power-domains = <&prm_core>; +- clocks = <&l4per_clkctrl OMAP5_L4_PER_CLKCTRL 0>; +- clock-names = "fck"; +- reg = <0x48000000 0x800>, +- <0x48000800 0x800>, +- <0x48001000 0x400>, +- <0x48001400 0x400>, +- <0x48001800 0x400>, +- <0x48001c00 0x400>; +- reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ +- <0x00200000 0x48200000 0x200000>; /* segment 1 */ +- +- segment@0 { /* 0x48000000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ +- <0x00001000 0x00001000 0x000400>, /* ap 1 */ +- <0x00000800 0x00000800 0x000800>, /* ap 2 */ +- <0x00020000 0x00020000 0x001000>, /* ap 3 */ +- <0x00021000 0x00021000 0x001000>, /* ap 4 */ +- <0x00032000 0x00032000 0x001000>, /* ap 5 */ +- <0x00033000 0x00033000 0x001000>, /* ap 6 */ +- <0x00034000 0x00034000 0x001000>, /* ap 7 */ +- <0x00035000 0x00035000 0x001000>, /* ap 8 */ +- <0x00036000 0x00036000 0x001000>, /* ap 9 */ +- <0x00037000 0x00037000 0x001000>, /* ap 10 */ +- <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ +- <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ +- <0x00055000 0x00055000 0x001000>, /* ap 13 */ +- <0x00056000 0x00056000 0x001000>, /* ap 14 */ +- <0x00057000 0x00057000 0x001000>, /* ap 15 */ +- <0x00058000 0x00058000 0x001000>, /* ap 16 */ +- <0x00059000 0x00059000 0x001000>, /* ap 17 */ +- <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ +- <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ +- <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ +- <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ +- <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ +- <0x00060000 0x00060000 0x001000>, /* ap 23 */ +- <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ +- <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ +- <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ +- <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ +- <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ +- <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ +- <0x00070000 0x00070000 0x001000>, /* ap 30 */ +- <0x00071000 0x00071000 0x001000>, /* ap 31 */ +- <0x00072000 0x00072000 0x001000>, /* ap 32 */ +- <0x00073000 0x00073000 0x001000>, /* ap 33 */ +- <0x00061000 0x00061000 0x001000>, /* ap 34 */ +- <0x00053000 0x00053000 0x001000>, /* ap 35 */ +- <0x00054000 0x00054000 0x001000>, /* ap 36 */ +- <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ +- <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ +- <0x00078000 0x00078000 0x001000>, /* ap 39 */ +- <0x00079000 0x00079000 0x001000>, /* ap 40 */ +- <0x00086000 0x00086000 0x001000>, /* ap 41 */ +- <0x00087000 0x00087000 0x001000>, /* ap 42 */ +- <0x00088000 0x00088000 0x001000>, /* ap 43 */ +- <0x00089000 0x00089000 0x001000>, /* ap 44 */ +- <0x00051000 0x00051000 0x001000>, /* ap 45 */ +- <0x00052000 0x00052000 0x001000>, /* ap 46 */ +- <0x00098000 0x00098000 0x001000>, /* ap 47 */ +- <0x00099000 0x00099000 0x001000>, /* ap 48 */ +- <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ +- <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ +- <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ +- <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ +- <0x00068000 0x00068000 0x001000>, /* ap 53 */ +- <0x00069000 0x00069000 0x001000>, /* ap 54 */ +- <0x00090000 0x00090000 0x002000>, /* ap 55 */ +- <0x00092000 0x00092000 0x001000>, /* ap 56 */ +- <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ +- <0x000a5000 0x000a5000 0x001000>, +- <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ +- <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ +- <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ +- <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ +- <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ +- <0x00066000 0x00066000 0x001000>, /* ap 63 */ +- <0x00067000 0x00067000 0x001000>, /* ap 64 */ +- <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ +- <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ +- <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ +- <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ +- <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ +- <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ +- <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ +- <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ +- <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ +- <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ +- <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ +- <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ +- <0x00001400 0x00001400 0x000400>, /* ap 77 */ +- <0x00001800 0x00001800 0x000400>, /* ap 78 */ +- <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ +- <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ +- <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ +- <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ +- <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ +- <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ +- +- target-module@20000 { /* 0x48020000, ap 3 04.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x20050 0x4>, +- <0x20054 0x4>, +- <0x20058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x20000 0x1000>; +- +- uart3: serial@0 { +- compatible = "ti,omap4-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- }; +- }; +- +- target-module@32000 { /* 0x48032000, ap 5 3e.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x32000 0x4>, +- <0x32010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x32000 0x1000>; +- +- timer2: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>, +- <&sys_clkin>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- }; +- }; +- +- target-module@34000 { /* 0x48034000, ap 7 46.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x34000 0x4>, +- <0x34010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x34000 0x1000>; +- +- timer3: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>, +- <&sys_clkin>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- }; +- }; +- +- target-module@36000 { /* 0x48036000, ap 9 4e.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x36000 0x4>, +- <0x36010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x36000 0x1000>; +- +- timer4: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>, +- <&sys_clkin>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- }; +- }; +- +- target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x3e000 0x4>, +- <0x3e010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x3e000 0x1000>; +- +- timer9: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>, +- <&sys_clkin>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-pwm; +- }; +- }; +- +- target-module@51000 { /* 0x48051000, ap 45 2e.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x51000 0x4>, +- <0x51010 0x4>, +- <0x51114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 0>, +- <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x51000 0x1000>; +- +- gpio7: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@53000 { /* 0x48053000, ap 35 36.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x53000 0x4>, +- <0x53010 0x4>, +- <0x53114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 0>, +- <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x53000 0x1000>; +- +- gpio8: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@55000 { /* 0x48055000, ap 13 0e.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x55000 0x4>, +- <0x55010 0x4>, +- <0x55114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 0>, +- <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x55000 0x1000>; +- +- gpio2: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@57000 { /* 0x48057000, ap 15 06.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x57000 0x4>, +- <0x57010 0x4>, +- <0x57114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 0>, +- <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x57000 0x1000>; +- +- gpio3: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@59000 { /* 0x48059000, ap 17 16.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x59000 0x4>, +- <0x59010 0x4>, +- <0x59114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 0>, +- <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x59000 0x1000>; +- +- gpio4: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x5b000 0x4>, +- <0x5b010 0x4>, +- <0x5b114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 0>, +- <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5b000 0x1000>; +- +- gpio5: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x5d000 0x4>, +- <0x5d010 0x4>, +- <0x5d114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 0>, +- <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x5d000 0x1000>; +- +- gpio6: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@60000 { /* 0x48060000, ap 23 24.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x60000 0x8>, +- <0x60010 0x8>, +- <0x60090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_I2C3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x60000 0x1000>; +- +- i2c3: i2c@0 { +- compatible = "ti,omap4-i2c"; +- reg = <0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- target-module@66000 { /* 0x48066000, ap 63 4c.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x66050 0x4>, +- <0x66054 0x4>, +- <0x66058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_UART5_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x66000 0x1000>; +- +- uart5: serial@0 { +- compatible = "ti,omap4-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- }; +- }; +- +- target-module@68000 { /* 0x48068000, ap 53 54.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x68050 0x4>, +- <0x68054 0x4>, +- <0x68058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_UART6_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x68000 0x1000>; +- +- uart6: serial@0 { +- compatible = "ti,omap4-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- }; +- }; +- +- target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x6a050 0x4>, +- <0x6a054 0x4>, +- <0x6a058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_UART1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6a000 0x1000>; +- +- uart1: serial@0 { +- compatible = "ti,omap4-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- }; +- }; +- +- target-module@6c000 { /* 0x4806c000, ap 26 22.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x6c050 0x4>, +- <0x6c054 0x4>, +- <0x6c058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_UART2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6c000 0x1000>; +- +- uart2: serial@0 { +- compatible = "ti,omap4-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- }; +- }; +- +- target-module@6e000 { /* 0x4806e000, ap 28 44.1 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x6e050 0x4>, +- <0x6e054 0x4>, +- <0x6e058 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_UART4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6e000 0x1000>; +- +- uart4: serial@0 { +- compatible = "ti,omap4-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- }; +- }; +- +- target-module@70000 { /* 0x48070000, ap 30 14.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x70000 0x8>, +- <0x70010 0x8>, +- <0x70090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_I2C1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x70000 0x1000>; +- +- i2c1: i2c@0 { +- compatible = "ti,omap4-i2c"; +- reg = <0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- target-module@72000 { /* 0x48072000, ap 32 1c.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x72000 0x8>, +- <0x72010 0x8>, +- <0x72090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_I2C2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x72000 0x1000>; +- +- i2c2: i2c@0 { +- compatible = "ti,omap4-i2c"; +- reg = <0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- target-module@78000 { /* 0x48078000, ap 39 12.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x78000 0x1000>; +- }; +- +- target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x7a000 0x8>, +- <0x7a010 0x8>, +- <0x7a090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_I2C4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x7a000 0x1000>; +- +- i2c4: i2c@0 { +- compatible = "ti,omap4-i2c"; +- reg = <0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- target-module@7c000 { /* 0x4807c000, ap 83 34.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x7c000 0x8>, +- <0x7c010 0x8>, +- <0x7c090 0x8>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_I2C5_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x7c000 0x1000>; +- +- i2c5: i2c@0 { +- compatible = "ti,omap4-i2c"; +- reg = <0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- target-module@86000 { /* 0x48086000, ap 41 5e.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x86000 0x4>, +- <0x86010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x86000 0x1000>; +- +- timer10: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>, +- <&sys_clkin>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-pwm; +- }; +- }; +- +- target-module@88000 { /* 0x48088000, ap 43 66.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x88000 0x4>, +- <0x88010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x88000 0x1000>; +- +- timer11: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>, +- <&sys_clkin>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-pwm; +- }; +- }; +- +- rng_target: target-module@90000 { /* 0x48090000, ap 55 1a.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x91fe0 0x4>, +- <0x91fe4 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- ; +- /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ +- clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x90000 0x2000>; +- +- rng: rng@0 { +- compatible = "ti,omap4-rng"; +- reg = <0x0 0x2000>; +- interrupts = ; +- }; +- }; +- +- target-module@98000 { /* 0x48098000, ap 47 08.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x98000 0x4>, +- <0x98010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_MCSPI1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x98000 0x1000>; +- +- mcspi1: spi@0 { +- compatible = "ti,omap4-mcspi"; +- reg = <0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,spi-num-cs = <4>; +- dmas = <&sdma 35>, +- <&sdma 36>, +- <&sdma 37>, +- <&sdma 38>, +- <&sdma 39>, +- <&sdma 40>, +- <&sdma 41>, +- <&sdma 42>; +- dma-names = "tx0", "rx0", "tx1", "rx1", +- "tx2", "rx2", "tx3", "rx3"; +- }; +- }; +- +- target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x9a000 0x4>, +- <0x9a010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_MCSPI2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x9a000 0x1000>; +- +- mcspi2: spi@0 { +- compatible = "ti,omap4-mcspi"; +- reg = <0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,spi-num-cs = <2>; +- dmas = <&sdma 43>, +- <&sdma 44>, +- <&sdma 45>, +- <&sdma 46>; +- dma-names = "tx0", "rx0", "tx1", "rx1"; +- }; +- }; +- +- target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x9c000 0x4>, +- <0x9c010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ +- clocks = <&l3init_clkctrl OMAP5_MMC1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x9c000 0x1000>; +- +- mmc1: mmc@0 { +- compatible = "ti,omap4-hsmmc"; +- reg = <0x0 0x400>; +- interrupts = ; +- ti,dual-volt; +- ti,needs-special-reset; +- dmas = <&sdma 61>, <&sdma 62>; +- dma-names = "tx", "rx"; +- pbias-supply = <&pbias_mmc_reg>; +- }; +- }; +- +- target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa2000 0x1000>; +- }; +- +- target-module@a4000 { /* 0x480a4000, ap 57 3c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x000a4000 0x00001000>, +- <0x00001000 0x000a5000 0x00001000>; +- }; +- +- des_target: target-module@a5000 { /* 0x480a5000 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xa5030 0x4>, +- <0xa5034 0x4>, +- <0xa5038 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ +- clocks = <&l4sec_clkctrl OMAP5_DES3DES_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xa5000 0x00001000>; +- status = "disabled"; +- +- des: des@0 { +- compatible = "ti,omap4-des"; +- reg = <0 0xa0>; +- interrupts = ; +- dmas = <&sdma 117>, <&sdma 116>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa8000 0x4000>; +- }; +- +- target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xad000 0x4>, +- <0xad010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_MMC3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xad000 0x1000>; +- +- mmc3: mmc@0 { +- compatible = "ti,omap4-hsmmc"; +- reg = <0x0 0x400>; +- interrupts = ; +- ti,needs-special-reset; +- dmas = <&sdma 77>, <&sdma 78>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@b2000 { /* 0x480b2000, ap 37 0c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xb2000 0x1000>; +- }; +- +- target-module@b4000 { /* 0x480b4000, ap 65 42.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xb4000 0x4>, +- <0xb4010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ +- clocks = <&l3init_clkctrl OMAP5_MMC2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xb4000 0x1000>; +- +- mmc2: mmc@0 { +- compatible = "ti,omap4-hsmmc"; +- reg = <0x0 0x400>; +- interrupts = ; +- ti,needs-special-reset; +- dmas = <&sdma 47>, <&sdma 48>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@b8000 { /* 0x480b8000, ap 67 32.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xb8000 0x4>, +- <0xb8010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_MCSPI3_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xb8000 0x1000>; +- +- mcspi3: spi@0 { +- compatible = "ti,omap4-mcspi"; +- reg = <0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,spi-num-cs = <2>; +- dmas = <&sdma 15>, <&sdma 16>; +- dma-names = "tx0", "rx0"; +- }; +- }; +- +- target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xba000 0x4>, +- <0xba010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_MCSPI4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xba000 0x1000>; +- +- mcspi4: spi@0 { +- compatible = "ti,omap4-mcspi"; +- reg = <0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- ti,spi-num-cs = <1>; +- dmas = <&sdma 70>, <&sdma 71>; +- dma-names = "tx0", "rx0"; +- }; +- }; +- +- target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xd1000 0x4>, +- <0xd1010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_MMC4_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xd1000 0x1000>; +- +- mmc4: mmc@0 { +- compatible = "ti,omap4-hsmmc"; +- reg = <0x0 0x400>; +- interrupts = ; +- ti,needs-special-reset; +- dmas = <&sdma 57>, <&sdma 58>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xd5000 0x4>, +- <0xd5010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-midle = , +- , +- , +- ; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ +- clocks = <&l4per_clkctrl OMAP5_MMC5_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xd5000 0x1000>; +- +- mmc5: mmc@0 { +- compatible = "ti,omap4-hsmmc"; +- reg = <0x0 0x400>; +- interrupts = ; +- ti,needs-special-reset; +- dmas = <&sdma 59>, <&sdma 60>; +- dma-names = "tx", "rx"; +- }; +- }; +- }; +- +- segment@200000 { /* 0x48200000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&l4_wkup { /* 0x4ae00000 */ +- compatible = "ti,omap5-l4-wkup", "simple-pm-bus"; +- power-domains = <&prm_wkupaon>; +- clocks = <&wkupaon_clkctrl OMAP5_L4_WKUP_CLKCTRL 0>; +- clock-names = "fck"; +- reg = <0x4ae00000 0x800>, +- <0x4ae00800 0x800>, +- <0x4ae01000 0x1000>; +- reg-names = "ap", "la", "ia0"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ +- <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ +- <0x00020000 0x4ae20000 0x010000>; /* segment 2 */ +- +- segment@0 { /* 0x4ae00000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ +- <0x00001000 0x00001000 0x001000>, /* ap 1 */ +- <0x00000800 0x00000800 0x000800>, /* ap 2 */ +- <0x00006000 0x00006000 0x002000>, /* ap 3 */ +- <0x00008000 0x00008000 0x001000>, /* ap 4 */ +- <0x0000a000 0x0000a000 0x001000>, /* ap 15 */ +- <0x0000b000 0x0000b000 0x001000>, /* ap 16 */ +- <0x00004000 0x00004000 0x001000>, /* ap 17 */ +- <0x00005000 0x00005000 0x001000>, /* ap 18 */ +- <0x0000c000 0x0000c000 0x001000>, /* ap 19 */ +- <0x0000d000 0x0000d000 0x001000>; /* ap 20 */ +- +- target-module@4000 { /* 0x4ae04000, ap 17 20.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4000 0x4>, +- <0x4010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- ; +- /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ +- clocks = <&wkupaon_clkctrl OMAP5_COUNTER_32K_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4000 0x1000>; +- +- counter32k: counter@0 { +- compatible = "ti,omap-counter32k"; +- reg = <0x0 0x40>; +- }; +- }; +- +- target-module@6000 { /* 0x4ae06000, ap 3 08.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x6000 0x4>; +- reg-names = "rev"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x6000 0x2000>; +- +- prm: prm@0 { +- compatible = "ti,omap5-prm", "simple-bus"; +- reg = <0x0 0x2000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x2000>; +- +- prm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- prm_clockdomains: clockdomains { +- }; +- }; +- }; +- +- target-module@a000 { /* 0x4ae0a000, ap 15 2c.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xa000 0x4>; +- reg-names = "rev"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xa000 0x1000>; +- +- scrm: scrm@0 { +- compatible = "ti,omap5-scrm"; +- reg = <0x0 0x1000>; +- +- scrm_clocks: clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- scrm_clockdomains: clockdomains { +- }; +- }; +- }; +- +- target-module@c000 { /* 0x4ae0c000, ap 19 28.0 */ +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0xc000 0x4>; +- reg-names = "rev"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc000 0x1000>; +- +- omap5_pmx_wkup: pinmux@840 { +- compatible = "ti,omap5-padconf", +- "pinctrl-single"; +- reg = <0x840 0x003c>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <1>; +- #interrupt-cells = <1>; +- interrupt-controller; +- pinctrl-single,register-width = <16>; +- pinctrl-single,function-mask = <0x7fff>; +- }; +- +- omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@da0 { +- compatible = "ti,omap5-scm-wkup-pad-conf", +- "simple-bus"; +- reg = <0xda0 0x60>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x60>; +- +- scm_wkup_pad_conf: scm_conf@0 { +- compatible = "syscon", "simple-bus"; +- reg = <0x0 0x60>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x0 0x60>; +- +- scm_wkup_pad_conf_clocks: clocks@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- }; +- }; +- }; +- +- segment@10000 { /* 0x4ae10000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ +- <0x00001000 0x00011000 0x001000>, /* ap 6 */ +- <0x00004000 0x00014000 0x001000>, /* ap 7 */ +- <0x00005000 0x00015000 0x001000>, /* ap 8 */ +- <0x00008000 0x00018000 0x001000>, /* ap 9 */ +- <0x00009000 0x00019000 0x001000>, /* ap 10 */ +- <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ +- <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ +- +- target-module@0 { /* 0x4ae10000, ap 5 10.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x0 0x4>, +- <0x10 0x4>, +- <0x114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ +- clocks = <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 0>, +- <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 8>; +- clock-names = "fck", "dbclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1000>; +- +- gpio1: gpio@0 { +- compatible = "ti,omap4-gpio"; +- reg = <0x0 0x200>; +- interrupts = ; +- ti,gpio-always-on; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- target-module@4000 { /* 0x4ae14000, ap 7 14.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4000 0x4>, +- <0x4010 0x4>, +- <0x4014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ +- clocks = <&wkupaon_clkctrl OMAP5_WD_TIMER2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4000 0x1000>; +- +- wdt2: wdt@0 { +- compatible = "ti,omap5-wdt", "ti,omap3-wdt"; +- reg = <0x0 0x80>; +- interrupts = ; +- }; +- }; +- +- timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 18.0 */ +- compatible = "ti,sysc-omap4-timer", "ti,sysc"; +- reg = <0x8000 0x4>, +- <0x8010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | +- SYSC_OMAP4_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- , +- ; +- /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ +- clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x8000 0x1000>; +- +- timer1: timer@0 { +- compatible = "ti,omap5430-timer"; +- reg = <0x0 0x80>; +- clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>, +- <&sys_clkin>; +- clock-names = "fck", "timer_sys_ck"; +- interrupts = ; +- ti,timer-alwon; +- }; +- }; +- +- target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */ +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0xc000 0x4>, +- <0xc010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | +- SYSC_OMAP2_SOFTRESET)>; +- ti,sysc-sidle = , +- , +- ; +- /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ +- clocks = <&wkupaon_clkctrl OMAP5_KBD_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xc000 0x1000>; +- +- keypad: keypad@0 { +- compatible = "ti,omap4-keypad"; +- reg = <0x0 0x400>; +- }; +- }; +- }; +- +- segment@20000 { /* 0x4ae20000 */ +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ +- <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ +- <0x00000000 0x00020000 0x001000>, /* ap 21 */ +- <0x00001000 0x00021000 0x001000>, /* ap 22 */ +- <0x00002000 0x00022000 0x001000>, /* ap 23 */ +- <0x00003000 0x00023000 0x001000>, /* ap 24 */ +- <0x00007000 0x00027000 0x000400>, /* ap 25 */ +- <0x00008000 0x00028000 0x000800>, /* ap 26 */ +- <0x00009000 0x00029000 0x000100>, /* ap 27 */ +- <0x00008800 0x00028800 0x000200>, /* ap 28 */ +- <0x00008a00 0x00028a00 0x000100>; /* ap 29 */ +- +- target-module@0 { /* 0x4ae20000, ap 21 04.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1000>; +- }; +- +- target-module@2000 { /* 0x4ae22000, ap 23 0c.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2000 0x1000>; +- }; +- +- target-module@6000 { /* 0x4ae26000, ap 13 24.0 */ +- compatible = "ti,sysc"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00006000 0x00001000>, +- <0x00001000 0x00007000 0x00000400>, +- <0x00002000 0x00008000 0x00000800>, +- <0x00002800 0x00008800 0x00000200>, +- <0x00002a00 0x00008a00 0x00000100>, +- <0x00003000 0x00009000 0x00000100>; +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/omap5-sbc-t54.dts b/scripts/dtc/include-prefixes/arm/omap5-sbc-t54.dts +deleted file mode 100644 +index 657df46251c2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap5-sbc-t54.dts ++++ /dev/null +@@ -1,52 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Suppport for CompuLab CM-T54 on SB-T54 baseboard +- */ +- +-#include "omap5-cm-t54.dts" +- +-/ { +- model = "CompuLab CM-T54 on SB-T54"; +- compatible = "compulab,omap5-sbc-t54", "compulab,omap5-cm-t54", "ti,omap5"; +-}; +- +-&omap5_pmx_core { +- i2c4_pins: pinmux_i2c4_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x00f8, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ +- OMAP5_IOPAD(0x00fa, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ +- >; +- }; +- +- mmc1_aux_pins: pinmux_mmc1_aux_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* timer5_pwm_evt.gpio8_228 */ +- OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* timer6_pwm_evt.gpio8_229 */ +- >; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &mmc1_pins +- &mmc1_aux_pins +- >; +- cd-inverted; +- wp-inverted; +- cd-gpios = <&gpio8 4 GPIO_ACTIVE_LOW>; /* gpio8_228 */ +- wp-gpios = <&gpio8 5 GPIO_ACTIVE_LOW>; /* gpio8_229 */ +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pins>; +- +- clock-frequency = <400000>; +- +- at24@50 { +- compatible = "atmel,24c02"; +- pagesize = <16>; +- reg = <0x50>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap5-uevm.dts b/scripts/dtc/include-prefixes/arm/omap5-uevm.dts +deleted file mode 100644 +index 51d5fcae5081..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap5-uevm.dts ++++ /dev/null +@@ -1,234 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-/dts-v1/; +- +-#include "omap5-board-common.dtsi" +- +-/ { +- model = "TI OMAP5 uEVM board"; +- compatible = "ti,omap5-uevm", "ti,omap5"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */ +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- dsp_memory_region: dsp-memory@95000000 { +- compatible = "shared-dma-pool"; +- reg = <0 0x95000000 0 0x800000>; +- reusable; +- status = "okay"; +- }; +- +- ipu_memory_region: ipu-memory@95800000 { +- compatible = "shared-dma-pool"; +- reg = <0 0x95800000 0 0x3800000>; +- reusable; +- status = "okay"; +- }; +- }; +- +- aliases { +- ethernet = ðernet; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led1 { +- label = "omap5:blue:usr1"; +- gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */ +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- }; +- +- evm_keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&evm_keys_pins>; +- +- #address-cells = <7>; +- #size-cells = <0>; +- +- btn1 { +- label = "BTN1"; +- linux,code = <169>; +- gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 */ +- wakeup-source; +- autorepeat; +- debounce-interval = <50>; +- }; +- }; +- +- evm_leds { +- compatible = "gpio-leds"; +- +- led1 { +- label = "omap5:red:led"; +- gpios = <&gpio9 17 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- +- led2 { +- label = "omap5:green:led"; +- gpios = <&gpio9 18 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc1"; +- default-state = "off"; +- }; +- +- led3 { +- label = "omap5:blue:led"; +- gpios = <&gpio9 19 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc2"; +- default-state = "off"; +- }; +- +- led4 { +- label = "omap5:green:led1"; +- gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- +- led5 { +- label = "omap5:green:led2"; +- gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- default-state = "off"; +- }; +- +- led6 { +- label = "omap5:green:led3"; +- gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- +- led7 { +- label = "omap5:green:led4"; +- gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- default-state = "off"; +- }; +- +- led8 { +- label = "omap5:green:led5"; +- gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- }; +-}; +- +-&hdmi { +- vdda-supply = <&ldo4_reg>; +-}; +- +-&i2c1 { +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- }; +-}; +- +-&i2c5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_pins>; +- +- clock-frequency = <400000>; +- +- gpio9: gpio@22 { +- compatible = "ti,tca6424"; +- reg = <0x22>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- +- cd-gpios = <&gpio5 24 GPIO_ACTIVE_LOW>; /* gpio5_152 */ +-}; +- +-&omap5_pmx_core { +- evm_keys_pins: pinmux_evm_keys_gpio_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x0b6, PIN_INPUT | MUX_MODE6) /* gpio3_83 */ +- >; +- }; +- +- i2c5_pins: pinmux_i2c5_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x1c6, PIN_INPUT | MUX_MODE0) /* i2c5_scl */ +- OMAP5_IOPAD(0x1c8, PIN_INPUT | MUX_MODE0) /* i2c5_sda */ +- >; +- }; +- +- mmc1_pins: pinmux_mmc1_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x1d4, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio5_152 */ +- >; +- }; +-}; +- +-&tpd12s015 { +- gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>, /* TCA6424A P01, CT CP HPD */ +- <&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */ +- <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */ +-}; +- +-&twl6040 { +- ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */ +-}; +- +-&twl6040_pins { +- pinctrl-single,pins = < +- OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ +- >; +-}; +- +-&usbhsehci { +- #address-cells = <1>; +- #size-cells = <0>; +- +- hub@2 { +- compatible = "usb424,3503"; +- reg = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- ethernet: usbether@3 { +- compatible = "usb424,9730"; +- reg = <3>; +- }; +-}; +- +-&wlcore { +- compatible = "ti,wl1837"; +-}; +- +-&dsp { +- status = "okay"; +- memory-region = <&dsp_memory_region>; +- ti,timers = <&timer5>; +- ti,watchdog-timers = <&timer6>; +-}; +- +-&ipu { +- status = "okay"; +- memory-region = <&ipu_memory_region>; +- ti,timers = <&timer3>; +- ti,watchdog-timers = <&timer9>, <&timer11>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap5.dtsi b/scripts/dtc/include-prefixes/arm/omap5.dtsi +deleted file mode 100644 +index bac6fa838793..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap5.dtsi ++++ /dev/null +@@ -1,831 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ +- * +- * Based on "omap4.dtsi" +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- +- compatible = "ti,omap5"; +- interrupt-parent = <&wakeupgen>; +- chosen { }; +- +- aliases { +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- i2c3 = &i2c4; +- i2c4 = &i2c5; +- mmc0 = &mmc1; +- mmc1 = &mmc2; +- mmc2 = &mmc3; +- mmc3 = &mmc4; +- mmc4 = &mmc5; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- serial4 = &uart5; +- serial5 = &uart6; +- rproc0 = &dsp; +- rproc1 = &ipu; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x0>; +- +- operating-points = < +- /* kHz uV */ +- 1000000 1060000 +- 1500000 1250000 +- >; +- +- clocks = <&dpll_mpu_ck>; +- clock-names = "cpu"; +- +- clock-latency = <300000>; /* From omap-cpufreq driver */ +- +- /* cooling options */ +- #cooling-cells = <2>; /* min followed by max */ +- }; +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0x1>; +- +- operating-points = < +- /* kHz uV */ +- 1000000 1060000 +- 1500000 1250000 +- >; +- +- clocks = <&dpll_mpu_ck>; +- clock-names = "cpu"; +- +- clock-latency = <300000>; /* From omap-cpufreq driver */ +- +- /* cooling options */ +- #cooling-cells = <2>; /* min followed by max */ +- }; +- }; +- +- thermal-zones { +- #include "omap4-cpu-thermal.dtsi" +- #include "omap5-gpu-thermal.dtsi" +- #include "omap5-core-thermal.dtsi" +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- /* PPI secure/nonsecure IRQ */ +- interrupts = , +- , +- , +- ; +- interrupt-parent = <&gic>; +- }; +- +- pmu { +- compatible = "arm,cortex-a15-pmu"; +- interrupts = , +- ; +- }; +- +- /* +- * Needed early by omap4_sram_init() for barrier, do not move to l3 +- * interconnect as simple-pm-bus probes at module_init() time. +- */ +- ocmcram: sram@40300000 { +- compatible = "mmio-sram"; +- reg = <0 0x40300000 0 0x20000>; /* 128k */ +- }; +- +- gic: interrupt-controller@48211000 { +- compatible = "arm,cortex-a15-gic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0 0x48211000 0 0x1000>, +- <0 0x48212000 0 0x2000>, +- <0 0x48214000 0 0x2000>, +- <0 0x48216000 0 0x2000>; +- interrupt-parent = <&gic>; +- }; +- +- wakeupgen: interrupt-controller@48281000 { +- compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0 0x48281000 0 0x1000>; +- interrupt-parent = <&gic>; +- }; +- +- /* +- * XXX: Use a flat representation of the OMAP3 interconnect. +- * The real OMAP interconnect network is quite complex. +- * Since it will not bring real advantage to represent that in DT for +- * the moment, just use a fake OCP bus entry to represent the whole bus +- * hierarchy. +- */ +- ocp { +- compatible = "simple-pm-bus"; +- power-domains = <&prm_core>; +- clocks = <&l3main1_clkctrl OMAP5_L3_MAIN_1_CLKCTRL 0>, +- <&l3main2_clkctrl OMAP5_L3_MAIN_2_CLKCTRL 0>, +- <&l3instr_clkctrl OMAP5_L3_MAIN_3_CLKCTRL 0>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0 0xc0000000>; +- dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; +- +- l3-noc@44000000 { +- compatible = "ti,omap5-l3-noc"; +- reg = <0x44000000 0x2000>, +- <0x44800000 0x3000>, +- <0x45000000 0x4000>; +- interrupts = , +- ; +- }; +- +- l4_wkup: interconnect@4ae00000 { +- }; +- +- l4_cfg: interconnect@4a000000 { +- }; +- +- l4_per: interconnect@48000000 { +- }; +- +- target-module@48210000 { +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- power-domains = <&prm_mpu>; +- clocks = <&mpu_clkctrl OMAP5_MPU_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x48210000 0x1f0000>; +- +- mpu { +- compatible = "ti,omap4-mpu"; +- sram = <&ocmcram>; +- }; +- }; +- +- l4_abe: interconnect@40100000 { +- }; +- +- target-module@50000000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x50000000 4>, +- <0x50000010 4>, +- <0x50000014 4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- ti,no-idle-on-init; +- clocks = <&l3main2_clkctrl OMAP5_L3_MAIN_2_GPMC_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ +- <0x00000000 0x00000000 0x40000000>; /* data */ +- +- gpmc: gpmc@50000000 { +- compatible = "ti,omap4430-gpmc"; +- reg = <0x50000000 0x1000>; +- #address-cells = <2>; +- #size-cells = <1>; +- interrupts = ; +- dmas = <&sdma 4>; +- dma-names = "rxtx"; +- gpmc,num-cs = <8>; +- gpmc,num-waitpins = <4>; +- clock-names = "fck"; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +- +- target-module@55082000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x55082000 0x4>, +- <0x55082010 0x4>, +- <0x55082014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; +- clock-names = "fck"; +- resets = <&prm_core 2>; +- reset-names = "rstctrl"; +- ranges = <0x0 0x55082000 0x100>; +- #size-cells = <1>; +- #address-cells = <1>; +- +- mmu_ipu: mmu@0 { +- compatible = "ti,omap4-iommu"; +- reg = <0x0 0x100>; +- interrupts = ; +- #iommu-cells = <0>; +- ti,iommu-bus-err-back; +- }; +- }; +- +- dsp: dsp { +- compatible = "ti,omap5-dsp"; +- ti,bootreg = <&scm_conf 0x304 0>; +- iommus = <&mmu_dsp>; +- resets = <&prm_dsp 0>; +- clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; +- firmware-name = "omap5-dsp-fw.xe64T"; +- mboxes = <&mailbox &mbox_dsp>; +- status = "disabled"; +- }; +- +- ipu: ipu@55020000 { +- compatible = "ti,omap5-ipu"; +- reg = <0x55020000 0x10000>; +- reg-names = "l2ram"; +- iommus = <&mmu_ipu>; +- resets = <&prm_core 0>, <&prm_core 1>; +- clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; +- firmware-name = "omap5-ipu-fw.xem4"; +- mboxes = <&mailbox &mbox_ipu>; +- status = "disabled"; +- }; +- +- target-module@4e000000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4e000000 0x4>, +- <0x4e000010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- ; +- ranges = <0x0 0x4e000000 0x2000000>; +- #size-cells = <1>; +- #address-cells = <1>; +- +- dmm@0 { +- compatible = "ti,omap5-dmm"; +- reg = <0 0x800>; +- interrupts = ; +- }; +- }; +- +- target-module@4c000000 { +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- reg = <0x4c000000 0x4>; +- reg-names = "rev"; +- clocks = <&emif_clkctrl OMAP5_EMIF1_CLKCTRL 0>; +- clock-names = "fck"; +- ti,no-idle; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4c000000 0x1000000>; +- +- emif1: emif@0 { +- compatible = "ti,emif-4d5"; +- reg = <0 0x400>; +- interrupts = ; +- phy-type = <2>; /* DDR PHY type: Intelli PHY */ +- hw-caps-read-idle-ctrl; +- hw-caps-ll-interface; +- hw-caps-temp-alert; +- }; +- }; +- +- target-module@4d000000 { +- compatible = "ti,sysc-omap4-simple", "ti,sysc"; +- reg = <0x4d000000 0x4>; +- reg-names = "rev"; +- clocks = <&emif_clkctrl OMAP5_EMIF2_CLKCTRL 0>; +- clock-names = "fck"; +- ti,no-idle; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4d000000 0x1000000>; +- +- emif2: emif@0 { +- compatible = "ti,emif-4d5"; +- reg = <0 0x400>; +- interrupts = ; +- phy-type = <2>; /* DDR PHY type: Intelli PHY */ +- hw-caps-read-idle-ctrl; +- hw-caps-ll-interface; +- hw-caps-temp-alert; +- }; +- }; +- +- aes1_target: target-module@4b501000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4b501080 0x4>, +- <0x4b501084 0x4>, +- <0x4b501088 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ +- clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4b501000 0x1000>; +- +- aes1: aes@0 { +- compatible = "ti,omap4-aes"; +- reg = <0 0xa0>; +- interrupts = ; +- dmas = <&sdma 111>, <&sdma 110>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- aes2_target: target-module@4b701000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4b701080 0x4>, +- <0x4b701084 0x4>, +- <0x4b701088 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ +- clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4b701000 0x1000>; +- +- aes2: aes@0 { +- compatible = "ti,omap4-aes"; +- reg = <0 0xa0>; +- interrupts = ; +- dmas = <&sdma 114>, <&sdma 113>; +- dma-names = "tx", "rx"; +- }; +- }; +- +- sham_target: target-module@4b100000 { +- compatible = "ti,sysc-omap3-sham", "ti,sysc"; +- reg = <0x4b100100 0x4>, +- <0x4b100110 0x4>, +- <0x4b100114 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,sysc-sidle = , +- , +- ; +- ti,syss-mask = <1>; +- /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ +- clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x4b100000 0x1000>; +- +- sham: sham@0 { +- compatible = "ti,omap4-sham"; +- reg = <0 0x300>; +- interrupts = ; +- dmas = <&sdma 119>; +- dma-names = "rx"; +- }; +- }; +- +- bandgap: bandgap@4a0021e0 { +- reg = <0x4a0021e0 0xc +- 0x4a00232c 0xc +- 0x4a002380 0x2c +- 0x4a0023C0 0x3c>; +- interrupts = ; +- compatible = "ti,omap5430-bandgap"; +- +- #thermal-sensor-cells = <1>; +- }; +- +- target-module@56000000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x5600fe00 0x4>, +- <0x5600fe10 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-sidle = , +- , +- ; +- clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x56000000 0x2000000>; +- +- /* +- * Closed source PowerVR driver, no child device +- * binding or driver in mainline +- */ +- }; +- +- target-module@58000000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x58000000 4>, +- <0x58000014 4>; +- reg-names = "rev", "syss"; +- ti,syss-mask = <1>; +- power-domains = <&prm_dss>; +- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>, +- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, +- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>, +- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>; +- clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x58000000 0x1000000>; +- +- dss: dss@0 { +- compatible = "ti,omap5-dss"; +- reg = <0 0x80>; +- status = "disabled"; +- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x1000000>; +- +- target-module@1000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x1000 0x4>, +- <0x1010 0x4>, +- <0x1014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-midle = , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,syss-mask = <1>; +- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1000 0x1000>; +- +- dispc@0 { +- compatible = "ti,omap5-dispc"; +- reg = <0 0x1000>; +- interrupts = ; +- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; +- clock-names = "fck"; +- }; +- }; +- +- target-module@2000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x2000 0x4>, +- <0x2010 0x4>, +- <0x2014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,syss-mask = <1>; +- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x2000 0x1000>; +- +- rfbi: encoder@0 { +- compatible = "ti,omap5-rfbi"; +- reg = <0 0x100>; +- status = "disabled"; +- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>; +- clock-names = "fck", "ick"; +- }; +- }; +- +- target-module@4000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x4000 0x4>, +- <0x4010 0x4>, +- <0x4014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,syss-mask = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x4000 0x1000>; +- +- dsi1: encoder@0 { +- compatible = "ti,omap5-dsi"; +- reg = <0 0x200>, +- <0x200 0x40>, +- <0x300 0x40>; +- reg-names = "proto", "phy", "pll"; +- interrupts = ; +- status = "disabled"; +- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, +- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; +- clock-names = "fck", "sys_clk"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- target-module@9000 { +- compatible = "ti,sysc-omap2", "ti,sysc"; +- reg = <0x9000 0x4>, +- <0x9010 0x4>, +- <0x9014 0x4>; +- reg-names = "rev", "sysc", "syss"; +- ti,sysc-sidle = , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | +- SYSC_OMAP2_ENAWAKEUP | +- SYSC_OMAP2_SOFTRESET | +- SYSC_OMAP2_AUTOIDLE)>; +- ti,syss-mask = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x9000 0x1000>; +- +- dsi2: encoder@0 { +- compatible = "ti,omap5-dsi"; +- reg = <0 0x200>, +- <0x200 0x40>, +- <0x300 0x40>; +- reg-names = "proto", "phy", "pll"; +- interrupts = ; +- status = "disabled"; +- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, +- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; +- clock-names = "fck", "sys_clk"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- target-module@40000 { +- compatible = "ti,sysc-omap4", "ti,sysc"; +- reg = <0x40000 0x4>, +- <0x40010 0x4>; +- reg-names = "rev", "sysc"; +- ti,sysc-sidle = , +- , +- , +- ; +- ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; +- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, +- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; +- clock-names = "fck", "dss_clk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x40000 0x40000>; +- +- hdmi: encoder@0 { +- compatible = "ti,omap5-hdmi"; +- reg = <0 0x200>, +- <0x200 0x80>, +- <0x300 0x80>, +- <0x20000 0x19000>; +- reg-names = "wp", "pll", "phy", "core"; +- interrupts = ; +- status = "disabled"; +- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, +- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; +- clock-names = "fck", "sys_clk"; +- dmas = <&sdma 76>; +- dma-names = "audio_tx"; +- }; +- }; +- }; +- }; +- +- abb_mpu: regulator-abb-mpu { +- compatible = "ti,abb-v2"; +- regulator-name = "abb_mpu"; +- #address-cells = <0>; +- #size-cells = <0>; +- clocks = <&sys_clkin>; +- ti,settling-time = <50>; +- ti,clock-cycles = <16>; +- +- reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>, +- <0x4a0021c4 0x8>, <0x4ae0c318 0x4>; +- reg-names = "base-address", "int-address", +- "efuse-address", "ldo-address"; +- ti,tranxdone-status-mask = <0x80>; +- /* LDOVBBMPU_MUX_CTRL */ +- ti,ldovbb-override-mask = <0x400>; +- /* LDOVBBMPU_VSET_OUT */ +- ti,ldovbb-vset-mask = <0x1F>; +- +- /* +- * NOTE: only FBB mode used but actual vset will +- * determine final biasing +- */ +- ti,abb_info = < +- /*uV ABB efuse rbb_m fbb_m vset_m*/ +- 1060000 0 0x0 0 0x02000000 0x01F00000 +- 1250000 0 0x4 0 0x02000000 0x01F00000 +- >; +- }; +- +- abb_mm: regulator-abb-mm { +- compatible = "ti,abb-v2"; +- regulator-name = "abb_mm"; +- #address-cells = <0>; +- #size-cells = <0>; +- clocks = <&sys_clkin>; +- ti,settling-time = <50>; +- ti,clock-cycles = <16>; +- +- reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, +- <0x4a0021a4 0x8>, <0x4ae0c314 0x4>; +- reg-names = "base-address", "int-address", +- "efuse-address", "ldo-address"; +- ti,tranxdone-status-mask = <0x80000000>; +- /* LDOVBBMM_MUX_CTRL */ +- ti,ldovbb-override-mask = <0x400>; +- /* LDOVBBMM_VSET_OUT */ +- ti,ldovbb-vset-mask = <0x1F>; +- +- /* +- * NOTE: only FBB mode used but actual vset will +- * determine final biasing +- */ +- ti,abb_info = < +- /*uV ABB efuse rbb_m fbb_m vset_m*/ +- 1025000 0 0x0 0 0x02000000 0x01F00000 +- 1120000 0 0x4 0 0x02000000 0x01F00000 +- >; +- }; +- }; +-}; +- +-&cpu_thermal { +- polling-delay = <500>; /* milliseconds */ +- coefficients = <65 (-1791)>; +-}; +- +-#include "omap5-l4.dtsi" +-#include "omap54xx-clocks.dtsi" +- +-&gpu_thermal { +- coefficients = <117 (-2992)>; +-}; +- +-&core_thermal { +- coefficients = <0 2000>; +-}; +- +-#include "omap5-l4-abe.dtsi" +-#include "omap54xx-clocks.dtsi" +- +-&prm { +- prm_mpu: prm@300 { +- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; +- reg = <0x300 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_dsp: prm@400 { +- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; +- reg = <0x400 0x100>; +- #reset-cells = <1>; +- #power-domain-cells = <0>; +- }; +- +- prm_abe: prm@500 { +- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; +- reg = <0x500 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_coreaon: prm@600 { +- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; +- reg = <0x600 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_core: prm@700 { +- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; +- reg = <0x700 0x100>; +- #reset-cells = <1>; +- #power-domain-cells = <0>; +- }; +- +- prm_iva: prm@1200 { +- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1200 0x100>; +- #reset-cells = <1>; +- #power-domain-cells = <0>; +- }; +- +- prm_cam: prm@1300 { +- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1300 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_dss: prm@1400 { +- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1400 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_gpu: prm@1500 { +- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1500 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_l3init: prm@1600 { +- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1600 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_custefuse: prm@1700 { +- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1700 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_wkupaon: prm@1800 { +- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1800 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_emu: prm@1a00 { +- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1a00 0x100>; +- #power-domain-cells = <0>; +- }; +- +- prm_device: prm@1c00 { +- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; +- reg = <0x1c00 0x100>; +- #reset-cells = <1>; +- }; +-}; +- +-/* Preferred always-on timer for clockevent */ +-&timer1_target { +- ti,no-reset-on-init; +- ti,no-idle; +- timer@0 { +- assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; +- assigned-clock-parents = <&sys_32k_ck>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/omap54xx-clocks.dtsi b/scripts/dtc/include-prefixes/arm/omap54xx-clocks.dtsi +deleted file mode 100644 +index 42f2c447727d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/omap54xx-clocks.dtsi ++++ /dev/null +@@ -1,1208 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device Tree Source for OMAP5 clock data +- * +- * Copyright (C) 2013 Texas Instruments, Inc. +- */ +-&cm_core_aon_clocks { +- pad_clks_src_ck: pad_clks_src_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <12000000>; +- }; +- +- pad_clks_ck: pad_clks_ck@108 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&pad_clks_src_ck>; +- ti,bit-shift = <8>; +- reg = <0x0108>; +- }; +- +- secure_32k_clk_src_ck: secure_32k_clk_src_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- slimbus_src_clk: slimbus_src_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <12000000>; +- }; +- +- slimbus_clk: slimbus_clk@108 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&slimbus_src_clk>; +- ti,bit-shift = <10>; +- reg = <0x0108>; +- }; +- +- sys_32k_ck: sys_32k_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- virt_12000000_ck: virt_12000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <12000000>; +- }; +- +- virt_13000000_ck: virt_13000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <13000000>; +- }; +- +- virt_16800000_ck: virt_16800000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <16800000>; +- }; +- +- virt_19200000_ck: virt_19200000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <19200000>; +- }; +- +- virt_26000000_ck: virt_26000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- }; +- +- virt_27000000_ck: virt_27000000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <27000000>; +- }; +- +- virt_38400000_ck: virt_38400000_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <38400000>; +- }; +- +- xclk60mhsp1_ck: xclk60mhsp1_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <60000000>; +- }; +- +- xclk60mhsp2_ck: xclk60mhsp2_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <60000000>; +- }; +- +- dpll_abe_ck: dpll_abe_ck@1e0 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-m4xen-clock"; +- clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; +- reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; +- }; +- +- dpll_abe_x2_ck: dpll_abe_x2_ck { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-x2-clock"; +- clocks = <&dpll_abe_ck>; +- }; +- +- dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_abe_x2_ck>; +- ti,max-div = <31>; +- reg = <0x01f0>; +- ti,index-starts-at-one; +- }; +- +- abe_24m_fclk: abe_24m_fclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_abe_m2x2_ck>; +- clock-mult = <1>; +- clock-div = <8>; +- }; +- +- abe_clk: abe_clk@108 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_abe_m2x2_ck>; +- ti,max-div = <4>; +- reg = <0x0108>; +- ti,index-power-of-two; +- }; +- +- abe_iclk: abe_iclk@528 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&aess_fclk>; +- ti,bit-shift = <24>; +- reg = <0x0528>; +- ti,dividers = <2>, <1>; +- }; +- +- abe_lp_clk_div: abe_lp_clk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_abe_m2x2_ck>; +- clock-mult = <1>; +- clock-div = <16>; +- }; +- +- dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_abe_x2_ck>; +- ti,max-div = <31>; +- reg = <0x01f4>; +- ti,index-starts-at-one; +- }; +- +- dpll_core_byp_mux: dpll_core_byp_mux@12c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; +- ti,bit-shift = <23>; +- reg = <0x012c>; +- }; +- +- dpll_core_ck: dpll_core_ck@120 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-core-clock"; +- clocks = <&sys_clkin>, <&dpll_core_byp_mux>; +- reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; +- }; +- +- dpll_core_x2_ck: dpll_core_x2_ck { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-x2-clock"; +- clocks = <&dpll_core_ck>; +- }; +- +- dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <63>; +- reg = <0x0150>; +- ti,index-starts-at-one; +- }; +- +- c2c_fclk: c2c_fclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_h21x2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- c2c_iclk: c2c_iclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&c2c_fclk>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <63>; +- reg = <0x0138>; +- ti,index-starts-at-one; +- }; +- +- dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <63>; +- reg = <0x013c>; +- ti,index-starts-at-one; +- }; +- +- dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <63>; +- reg = <0x0140>; +- ti,index-starts-at-one; +- }; +- +- dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <63>; +- reg = <0x0144>; +- ti,index-starts-at-one; +- }; +- +- dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <63>; +- reg = <0x0154>; +- ti,index-starts-at-one; +- }; +- +- dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <63>; +- reg = <0x0158>; +- ti,index-starts-at-one; +- }; +- +- dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <63>; +- reg = <0x015c>; +- ti,index-starts-at-one; +- }; +- +- dpll_core_m2_ck: dpll_core_m2_ck@130 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_ck>; +- ti,max-div = <31>; +- reg = <0x0130>; +- ti,index-starts-at-one; +- }; +- +- dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_core_x2_ck>; +- ti,max-div = <31>; +- reg = <0x0134>; +- ti,index-starts-at-one; +- }; +- +- iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_h12x2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; +- ti,bit-shift = <23>; +- reg = <0x01ac>; +- }; +- +- dpll_iva_ck: dpll_iva_ck@1a0 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-clock"; +- clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; +- reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; +- assigned-clocks = <&dpll_iva_ck>; +- assigned-clock-rates = <1165000000>; +- }; +- +- dpll_iva_x2_ck: dpll_iva_x2_ck { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-x2-clock"; +- clocks = <&dpll_iva_ck>; +- }; +- +- dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_iva_x2_ck>; +- ti,max-div = <63>; +- reg = <0x01b8>; +- ti,index-starts-at-one; +- assigned-clocks = <&dpll_iva_h11x2_ck>; +- assigned-clock-rates = <465920000>; +- }; +- +- dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_iva_x2_ck>; +- ti,max-div = <63>; +- reg = <0x01bc>; +- ti,index-starts-at-one; +- assigned-clocks = <&dpll_iva_h12x2_ck>; +- assigned-clock-rates = <388300000>; +- }; +- +- mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_core_h12x2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dpll_mpu_ck: dpll_mpu_ck@160 { +- #clock-cells = <0>; +- compatible = "ti,omap5-mpu-dpll-clock"; +- clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; +- reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; +- }; +- +- dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_mpu_ck>; +- ti,max-div = <31>; +- reg = <0x0170>; +- ti,index-starts-at-one; +- }; +- +- per_dpll_hs_clk_div: per_dpll_hs_clk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_abe_m3x2_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_abe_m3x2_ck>; +- clock-mult = <1>; +- clock-div = <3>; +- }; +- +- l3_iclk_div: l3_iclk_div@100 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- ti,max-div = <2>; +- ti,bit-shift = <4>; +- reg = <0x100>; +- clocks = <&dpll_core_h12x2_ck>; +- ti,index-power-of-two; +- }; +- +- gpu_l3_iclk: gpu_l3_iclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&l3_iclk_div>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- l4_root_clk_div: l4_root_clk_div@100 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- ti,max-div = <2>; +- ti,bit-shift = <8>; +- reg = <0x100>; +- clocks = <&l3_iclk_div>; +- ti,index-power-of-two; +- }; +- +- slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&slimbus_clk>; +- ti,bit-shift = <11>; +- reg = <0x0560>; +- }; +- +- aess_fclk: aess_fclk@528 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&abe_clk>; +- ti,bit-shift = <24>; +- ti,max-div = <2>; +- reg = <0x0528>; +- }; +- +- mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; +- ti,bit-shift = <26>; +- reg = <0x0540>; +- }; +- +- mcasp_gfclk: mcasp_gfclk@540 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; +- ti,bit-shift = <24>; +- reg = <0x0540>; +- }; +- +- dummy_ck: dummy_ck { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +-}; +-&prm_clocks { +- sys_clkin: sys_clkin@110 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; +- reg = <0x0110>; +- ti,index-starts-at-one; +- }; +- +- abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin>, <&sys_32k_ck>; +- reg = <0x0108>; +- }; +- +- abe_dpll_clk_mux: abe_dpll_clk_mux@10c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin>, <&sys_32k_ck>; +- reg = <0x010c>; +- }; +- +- custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- dss_syc_gfclk_div: dss_syc_gfclk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&sys_clkin>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- wkupaon_iclk_mux: wkupaon_iclk_mux@108 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin>, <&abe_lp_clk_div>; +- reg = <0x0108>; +- }; +- +- l3instr_ts_gclk_div: l3instr_ts_gclk_div { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&wkupaon_iclk_mux>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +-}; +- +-&cm_core_clocks { +- +- dpll_per_byp_mux: dpll_per_byp_mux@14c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; +- ti,bit-shift = <23>; +- reg = <0x014c>; +- }; +- +- dpll_per_ck: dpll_per_ck@140 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-clock"; +- clocks = <&sys_clkin>, <&dpll_per_byp_mux>; +- reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; +- }; +- +- dpll_per_x2_ck: dpll_per_x2_ck { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-x2-clock"; +- clocks = <&dpll_per_ck>; +- }; +- +- dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_x2_ck>; +- ti,max-div = <63>; +- reg = <0x0158>; +- ti,index-starts-at-one; +- }; +- +- dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_x2_ck>; +- ti,max-div = <63>; +- reg = <0x015c>; +- ti,index-starts-at-one; +- }; +- +- dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_x2_ck>; +- ti,max-div = <63>; +- reg = <0x0164>; +- ti,index-starts-at-one; +- }; +- +- dpll_per_m2_ck: dpll_per_m2_ck@150 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_ck>; +- ti,max-div = <31>; +- reg = <0x0150>; +- ti,index-starts-at-one; +- }; +- +- dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_x2_ck>; +- ti,max-div = <31>; +- reg = <0x0150>; +- ti,index-starts-at-one; +- }; +- +- dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_x2_ck>; +- ti,max-div = <31>; +- reg = <0x0154>; +- ti,index-starts-at-one; +- }; +- +- dpll_unipro1_ck: dpll_unipro1_ck@200 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-clock"; +- clocks = <&sys_clkin>, <&sys_clkin>; +- reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; +- }; +- +- dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_unipro1_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_unipro1_ck>; +- ti,max-div = <127>; +- reg = <0x0210>; +- ti,index-starts-at-one; +- }; +- +- dpll_unipro2_ck: dpll_unipro2_ck@1c0 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-clock"; +- clocks = <&sys_clkin>, <&sys_clkin>; +- reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>; +- }; +- +- dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_unipro2_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_unipro2_ck>; +- ti,max-div = <127>; +- reg = <0x01d0>; +- ti,index-starts-at-one; +- }; +- +- dpll_usb_byp_mux: dpll_usb_byp_mux@18c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; +- ti,bit-shift = <23>; +- reg = <0x018c>; +- }; +- +- dpll_usb_ck: dpll_usb_ck@180 { +- #clock-cells = <0>; +- compatible = "ti,omap4-dpll-j-type-clock"; +- clocks = <&sys_clkin>, <&dpll_usb_byp_mux>; +- reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; +- }; +- +- dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_usb_ck>; +- clock-mult = <1>; +- clock-div = <1>; +- }; +- +- dpll_usb_m2_ck: dpll_usb_m2_ck@190 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_usb_ck>; +- ti,max-div = <127>; +- reg = <0x0190>; +- ti,index-starts-at-one; +- }; +- +- func_128m_clk: func_128m_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_h11x2_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- func_12m_fclk: func_12m_fclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2x2_ck>; +- clock-mult = <1>; +- clock-div = <16>; +- }; +- +- func_24m_clk: func_24m_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2_ck>; +- clock-mult = <1>; +- clock-div = <4>; +- }; +- +- func_48m_fclk: func_48m_fclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2x2_ck>; +- clock-mult = <1>; +- clock-div = <4>; +- }; +- +- func_96m_fclk: func_96m_fclk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&dpll_per_m2x2_ck>; +- clock-mult = <1>; +- clock-div = <2>; +- }; +- +- l3init_60m_fclk: l3init_60m_fclk@104 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_usb_m2_ck>; +- reg = <0x0104>; +- ti,dividers = <1>, <8>; +- }; +- +- iss_ctrlclk: iss_ctrlclk@1320 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&func_96m_fclk>; +- ti,bit-shift = <8>; +- reg = <0x1320>; +- }; +- +- lli_txphy_clk: lli_txphy_clk@f20 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&dpll_unipro1_clkdcoldo>; +- ti,bit-shift = <8>; +- reg = <0x0f20>; +- }; +- +- lli_txphy_ls_clk: lli_txphy_ls_clk@f20 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&dpll_unipro1_m2_ck>; +- ti,bit-shift = <9>; +- reg = <0x0f20>; +- }; +- +- usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&sys_32k_ck>; +- ti,bit-shift = <8>; +- reg = <0x0640>; +- }; +- +- fdif_fclk: fdif_fclk@1328 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_h11x2_ck>; +- ti,bit-shift = <24>; +- ti,max-div = <2>; +- reg = <0x1328>; +- }; +- +- gpu_core_gclk_mux: gpu_core_gclk_mux@1520 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; +- ti,bit-shift = <24>; +- reg = <0x1520>; +- }; +- +- gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; +- ti,bit-shift = <25>; +- reg = <0x1520>; +- }; +- +- hsi_fclk: hsi_fclk@1638 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&dpll_per_m2x2_ck>; +- ti,bit-shift = <24>; +- ti,max-div = <2>; +- reg = <0x1638>; +- }; +-}; +- +-&cm_core_clockdomains { +- l3init_clkdm: l3init_clkdm { +- compatible = "ti,clockdomain"; +- clocks = <&dpll_usb_ck>; +- }; +-}; +- +-&scrm_clocks { +- auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&dpll_core_m3x2_ck>; +- ti,bit-shift = <8>; +- reg = <0x0310>; +- }; +- +- auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; +- ti,bit-shift = <1>; +- reg = <0x0310>; +- }; +- +- auxclk0_src_ck: auxclk0_src_ck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; +- }; +- +- auxclk0_ck: auxclk0_ck@310 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&auxclk0_src_ck>; +- ti,bit-shift = <16>; +- ti,max-div = <16>; +- reg = <0x0310>; +- }; +- +- auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&dpll_core_m3x2_ck>; +- ti,bit-shift = <8>; +- reg = <0x0314>; +- }; +- +- auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; +- ti,bit-shift = <1>; +- reg = <0x0314>; +- }; +- +- auxclk1_src_ck: auxclk1_src_ck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; +- }; +- +- auxclk1_ck: auxclk1_ck@314 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&auxclk1_src_ck>; +- ti,bit-shift = <16>; +- ti,max-div = <16>; +- reg = <0x0314>; +- }; +- +- auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&dpll_core_m3x2_ck>; +- ti,bit-shift = <8>; +- reg = <0x0318>; +- }; +- +- auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; +- ti,bit-shift = <1>; +- reg = <0x0318>; +- }; +- +- auxclk2_src_ck: auxclk2_src_ck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; +- }; +- +- auxclk2_ck: auxclk2_ck@318 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&auxclk2_src_ck>; +- ti,bit-shift = <16>; +- ti,max-div = <16>; +- reg = <0x0318>; +- }; +- +- auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&dpll_core_m3x2_ck>; +- ti,bit-shift = <8>; +- reg = <0x031c>; +- }; +- +- auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; +- ti,bit-shift = <1>; +- reg = <0x031c>; +- }; +- +- auxclk3_src_ck: auxclk3_src_ck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; +- }; +- +- auxclk3_ck: auxclk3_ck@31c { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&auxclk3_src_ck>; +- ti,bit-shift = <16>; +- ti,max-div = <16>; +- reg = <0x031c>; +- }; +- +- auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { +- #clock-cells = <0>; +- compatible = "ti,composite-no-wait-gate-clock"; +- clocks = <&dpll_core_m3x2_ck>; +- ti,bit-shift = <8>; +- reg = <0x0320>; +- }; +- +- auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { +- #clock-cells = <0>; +- compatible = "ti,composite-mux-clock"; +- clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; +- ti,bit-shift = <1>; +- reg = <0x0320>; +- }; +- +- auxclk4_src_ck: auxclk4_src_ck { +- #clock-cells = <0>; +- compatible = "ti,composite-clock"; +- clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; +- }; +- +- auxclk4_ck: auxclk4_ck@320 { +- #clock-cells = <0>; +- compatible = "ti,divider-clock"; +- clocks = <&auxclk4_src_ck>; +- ti,bit-shift = <16>; +- ti,max-div = <16>; +- reg = <0x0320>; +- }; +- +- auxclkreq0_ck: auxclkreq0_ck@210 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; +- ti,bit-shift = <2>; +- reg = <0x0210>; +- }; +- +- auxclkreq1_ck: auxclkreq1_ck@214 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; +- ti,bit-shift = <2>; +- reg = <0x0214>; +- }; +- +- auxclkreq2_ck: auxclkreq2_ck@218 { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; +- ti,bit-shift = <2>; +- reg = <0x0218>; +- }; +- +- auxclkreq3_ck: auxclkreq3_ck@21c { +- #clock-cells = <0>; +- compatible = "ti,mux-clock"; +- clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; +- ti,bit-shift = <2>; +- reg = <0x021c>; +- }; +-}; +- +-&cm_core_aon { +- mpu_cm: mpu_cm@300 { +- compatible = "ti,omap4-cm"; +- reg = <0x300 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x300 0x100>; +- +- mpu_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- dsp_cm: dsp_cm@400 { +- compatible = "ti,omap4-cm"; +- reg = <0x400 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x400 0x100>; +- +- dsp_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- abe_cm: abe_cm@500 { +- compatible = "ti,omap4-cm"; +- reg = <0x500 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x500 0x100>; +- +- abe_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x64>; +- #clock-cells = <2>; +- }; +- }; +- +-}; +- +-&cm_core { +- l3main1_cm: l3main1_cm@700 { +- compatible = "ti,omap4-cm"; +- reg = <0x700 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x700 0x100>; +- +- l3main1_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- l3main2_cm: l3main2_cm@800 { +- compatible = "ti,omap4-cm"; +- reg = <0x800 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x800 0x100>; +- +- l3main2_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- ipu_cm: ipu_cm@900 { +- compatible = "ti,omap4-cm"; +- reg = <0x900 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x900 0x100>; +- +- ipu_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- dma_cm: dma_cm@a00 { +- compatible = "ti,omap4-cm"; +- reg = <0xa00 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xa00 0x100>; +- +- dma_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- emif_cm: emif_cm@b00 { +- compatible = "ti,omap4-cm"; +- reg = <0xb00 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xb00 0x100>; +- +- emif_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x1c>; +- #clock-cells = <2>; +- }; +- }; +- +- l4cfg_cm: l4cfg_cm@d00 { +- compatible = "ti,omap4-cm"; +- reg = <0xd00 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xd00 0x100>; +- +- l4cfg_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x14>; +- #clock-cells = <2>; +- }; +- }; +- +- l3instr_cm: l3instr_cm@e00 { +- compatible = "ti,omap4-cm"; +- reg = <0xe00 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xe00 0x100>; +- +- l3instr_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0xc>; +- #clock-cells = <2>; +- }; +- }; +- +- l4per_cm: l4per_cm@1000 { +- compatible = "ti,omap4-cm"; +- reg = <0x1000 0x200>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1000 0x200>; +- +- l4per_clkctrl: clock@20 { +- compatible = "ti,clkctrl-l4per", "ti,clkctrl"; +- reg = <0x20 0x15c>; +- #clock-cells = <2>; +- }; +- +- l4sec_clkctrl: clock@1a0 { +- compatible = "ti,clkctrl-l4sec", "ti,clkctrl"; +- reg = <0x1a0 0x3c>; +- #clock-cells = <2>; +- }; +- }; +- +- dss_cm: dss_cm@1400 { +- compatible = "ti,omap4-cm"; +- reg = <0x1400 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1400 0x100>; +- +- dss_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- gpu_cm: gpu_cm@1500 { +- compatible = "ti,omap4-cm"; +- reg = <0x1500 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1500 0x100>; +- +- gpu_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x4>; +- #clock-cells = <2>; +- }; +- }; +- +- l3init_cm: l3init_cm@1600 { +- compatible = "ti,omap4-cm"; +- reg = <0x1600 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1600 0x100>; +- +- l3init_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0xd4>; +- #clock-cells = <2>; +- }; +- }; +-}; +- +-&prm { +- wkupaon_cm: wkupaon_cm@1900 { +- compatible = "ti,omap4-cm"; +- reg = <0x1900 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1900 0x100>; +- +- wkupaon_clkctrl: clk@20 { +- compatible = "ti,clkctrl"; +- reg = <0x20 0x5c>; +- #clock-cells = <2>; +- }; +- }; +-}; +- +-&scm_wkup_pad_conf_clocks { +- fref_xtal_ck: fref_xtal_ck { +- #clock-cells = <0>; +- compatible = "ti,gate-clock"; +- clocks = <&sys_clkin>; +- ti,bit-shift = <28>; +- reg = <0x14>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/openbmc-flash-layout-128.dtsi b/scripts/dtc/include-prefixes/arm/openbmc-flash-layout-128.dtsi +deleted file mode 100644 +index 05101a38c5bd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/openbmc-flash-layout-128.dtsi ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +- +-partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- u-boot@0 { +- reg = <0x0 0xe0000>; // 896KB +- label = "u-boot"; +- }; +- +- u-boot-env@e0000 { +- reg = <0xe0000 0x20000>; // 128KB +- label = "u-boot-env"; +- }; +- +- kernel@100000 { +- reg = <0x100000 0x900000>; // 9MB +- label = "kernel"; +- }; +- +- rofs@a00000 { +- reg = <0xa00000 0x5600000>; // 86MB +- label = "rofs"; +- }; +- +- rwfs@6000000 { +- reg = <0x6000000 0x2000000>; // 32MB +- label = "rwfs"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/openbmc-flash-layout-64.dtsi b/scripts/dtc/include-prefixes/arm/openbmc-flash-layout-64.dtsi +deleted file mode 100644 +index 31f59de5190b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/openbmc-flash-layout-64.dtsi ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2020 Bytedance. +- */ +- +-partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- u-boot@0 { +- reg = <0x0 0xe0000>; // 896KB +- label = "u-boot"; +- }; +- +- u-boot-env@e0000 { +- reg = <0xe0000 0x20000>; // 128KB +- label = "u-boot-env"; +- }; +- +- kernel@100000 { +- reg = <0x100000 0x900000>; // 9MB +- label = "kernel"; +- }; +- +- rofs@a00000 { +- reg = <0xa00000 0x2000000>; // 32MB +- label = "rofs"; +- }; +- +- rwfs@6000000 { +- reg = <0x2a00000 0x1600000>; // 22MB +- label = "rwfs"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/openbmc-flash-layout.dtsi b/scripts/dtc/include-prefixes/arm/openbmc-flash-layout.dtsi +deleted file mode 100644 +index 6c26524e93e1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/openbmc-flash-layout.dtsi ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +- +-partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- u-boot@0 { +- reg = <0x0 0x60000>; +- label = "u-boot"; +- }; +- +- u-boot-env@60000 { +- reg = <0x60000 0x20000>; +- label = "u-boot-env"; +- }; +- +- kernel@80000 { +- reg = <0x80000 0x440000>; +- label = "kernel"; +- }; +- +- rofs@c0000 { +- reg = <0x4c0000 0x1740000>; +- label = "rofs"; +- }; +- +- rwfs@1c00000 { +- reg = <0x1c00000 0x400000>; +- label = "rwfs"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/orion5x-kuroboxpro.dts b/scripts/dtc/include-prefixes/arm/orion5x-kuroboxpro.dts +deleted file mode 100644 +index e28b568e741a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/orion5x-kuroboxpro.dts ++++ /dev/null +@@ -1,127 +0,0 @@ +-/* +- * Device Tree file for Buffalo/Revogear Kurobox Pro +- * +- * Copyright (C) 2016 +- * Roger Shimizu +- * +- * Based on the board file arch/arm/mach-orion5x/kurobox_pro-setup.c +- * Copyright (C) Ronen Shitrit +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include "orion5x-linkstation.dtsi" +-#include +- +-/ { +- model = "Buffalo/Revogear Kurobox Pro"; +- compatible = "buffalo,kurobox-pro", "marvell,orion5x-88f5182", "marvell,orion5x"; +- +- soc { +- ranges = , +- , +- , +- ; +- }; +- +- memory { /* 128 MB */ +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +-}; +- +-&pinctrl { +- pmx_power_hdd: pmx-power-hdd { +- marvell,pins = "mpp1"; +- marvell,function = "gpio"; +- }; +- +- pmx_power_usb: pmx-power-usb { +- marvell,pins = "mpp9"; +- marvell,function = "gpio"; +- }; +-}; +- +-&devbus_cs0 { +- status = "okay"; +- compatible = "marvell,orion-nand"; +- reg = ; +- cle = <0>; +- ale = <1>; +- bank-width = <1>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- uImage@0 { /* 4 MB */ +- reg = <0 0x400000>; +- read-only; +- }; +- +- rootfs@400000 { /* 64 MB */ +- reg = <0x400000 0x4000000>; +- read-only; +- }; +- +- extra@4400000 { /* 188 MB */ +- reg = <0x4400000 0xBC00000>; +- read-only; +- }; +- }; +-}; +- +-&hdd_power { +- gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; +-}; +- +-&usb_power { +- gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; +-}; +- +-&sata { +- nr-ports = <2>; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/orion5x-lacie-d2-network.dts b/scripts/dtc/include-prefixes/arm/orion5x-lacie-d2-network.dts +deleted file mode 100644 +index 422958d13d42..000000000000 +--- a/scripts/dtc/include-prefixes/arm/orion5x-lacie-d2-network.dts ++++ /dev/null +@@ -1,237 +0,0 @@ +-/* +- * Copyright (C) 2014 Thomas Petazzoni +- * Copyright (C) 2009 Simon Guinot +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without any +- * warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include "orion5x-mv88f5182.dtsi" +- +-/ { +- model = "LaCie d2 Network"; +- compatible = "lacie,d2-network", "marvell,orion5x-88f5182", "marvell,orion5x"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x4000000>; /* 64 MB */ +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- soc { +- ranges = , +- , +- ; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&pmx_buttons>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- front_button { +- label = "Front Push Button"; +- linux,code = ; +- gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; +- }; +- +- power_rocker_sw_on { +- label = "Power rocker switch (on|auto)"; +- linux,input-type = <5>; /* EV_SW */ +- linux,code = <1>; /* D2NET_SWITCH_POWER_ON */ +- gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; +- }; +- +- power_rocker_sw_off { +- label = "Power rocker switch (auto|off)"; +- linux,input-type = <5>; /* EV_SW */ +- linux,code = <2>; /* D2NET_SWITCH_POWER_OFF */ +- gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power>; +- pinctrl-names = "default"; +- +- sata0_power: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "SATA0 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; +- }; +- +- sata1_power: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "SATA1 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&devbus_bootcs { +- status = "okay"; +- +- devbus,keep-config; +- +- /* +- * Currently the MTD code does not recognize the MX29LV400CBCT +- * as a bottom-type device. This could cause risks of +- * accidentally erasing critical flash sectors. We thus define +- * a single, write-protected partition covering the whole +- * flash. TODO: once the flash part TOP/BOTTOM detection +- * issue is sorted out in the MTD code, break this into at +- * least three partitions: 'u-boot code', 'u-boot environment' +- * and 'whatever is left'. +- */ +- flash@0 { +- compatible = "cfi-flash"; +- reg = <0 0x80000>; +- bank-width = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "Full512Kb"; +- reg = <0 0x80000>; +- read-only; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy: ethernet-phy { +- reg = <8>; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- +- ethernet-port@0 { +- phy-handle = <ðphy>; +- }; +-}; +- +-&i2c { +- status = "okay"; +- clock-frequency = <100000>; +- #address-cells = <1>; +- +- rtc@32 { +- compatible = "ricoh,rs5c372b"; +- reg = <0x32>; +- }; +- +- fan@3e { +- compatible = "gmt,g762"; +- reg = <0x3e>; +- +- /* Not enough HW info */ +- status = "disabled"; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c08"; +- reg = <0x50>; +- }; +-}; +- +-&pinctrl { +- pinctrl-0 = <&pmx_leds &pmx_board_id &pmx_fan_fail>; +- pinctrl-names = "default"; +- +- pmx_board_id: pmx-board-id { +- marvell,pins = "mpp0", "mpp1", "mpp2"; +- marvell,function = "gpio"; +- }; +- +- pmx_buttons: pmx-buttons { +- marvell,pins = "mpp8", "mpp9", "mpp18"; +- marvell,function = "gpio"; +- }; +- +- pmx_fan_fail: pmx-fan-fail { +- marvell,pins = "mpp5"; +- marvell,function = "gpio"; +- }; +- +- /* +- * MPP6: Red front LED +- * MPP16: Blue front LED blink control +- */ +- pmx_leds: pmx-leds { +- marvell,pins = "mpp6", "mpp16"; +- marvell,function = "gpio"; +- }; +- +- pmx_sata0_led_active: pmx-sata0-led-active { +- marvell,pins = "mpp14"; +- marvell,function = "sata0"; +- }; +- +- pmx_sata0_power: pmx-sata0-power { +- marvell,pins = "mpp3"; +- marvell,function = "gpio"; +- }; +- +- pmx_sata1_led_active: pmx-sata1-led-active { +- marvell,pins = "mpp15"; +- marvell,function = "sata1"; +- }; +- +- pmx_sata1_power: pmx-sata1-power { +- marvell,pins = "mpp12"; +- marvell,function = "gpio"; +- }; +- +- /* +- * Non MPP GPIOs: +- * GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok) +- * GPIO 23: Blue front LED off +- * GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled) +- */ +-}; +- +-&sata { +- pinctrl-0 = <&pmx_sata0_led_active +- &pmx_sata1_led_active>; +- pinctrl-names = "default"; +- status = "okay"; +- nr-ports = <2>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/orion5x-lacie-ethernet-disk-mini-v2.dts b/scripts/dtc/include-prefixes/arm/orion5x-lacie-ethernet-disk-mini-v2.dts +deleted file mode 100644 +index 0043e0040153..000000000000 +--- a/scripts/dtc/include-prefixes/arm/orion5x-lacie-ethernet-disk-mini-v2.dts ++++ /dev/null +@@ -1,175 +0,0 @@ +-/* +- * Copyright (C) 2012 Thomas Petazzoni +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without any +- * warranty of any kind, whether express or implied. +- */ +- +-/* +- * TODO: add Orion USB device port init when kernel.org support is added. +- * TODO: add flash write support: see below. +- * TODO: add power-off support. +- * TODO: add I2C EEPROM support. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include "orion5x-mv88f5182.dtsi" +- +-/ { +- model = "LaCie Ethernet Disk mini V2"; +- compatible = "lacie,ethernet-disk-mini-v2", "marvell,orion5x-88f5182", "marvell,orion5x"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x4000000>; /* 64 MB */ +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- soc { +- ranges = , +- , +- ; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&pmx_power_button>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- button@1 { +- label = "Power-on Switch"; +- linux,code = ; +- gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_power_led>; +- pinctrl-names = "default"; +- +- led@1 { +- label = "power:blue"; +- gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&devbus_bootcs { +- status = "okay"; +- +- /* Read parameters */ +- devbus,bus-width = <8>; +- devbus,turn-off-ps = <90000>; +- devbus,badr-skew-ps = <0>; +- devbus,acc-first-ps = <186000>; +- devbus,acc-next-ps = <186000>; +- +- /* Write parameters */ +- devbus,wr-high-ps = <90000>; +- devbus,wr-low-ps = <90000>; +- devbus,ale-wr-ps = <90000>; +- +- /* +- * Currently the MTD code does not recognize the MX29LV400CBCT +- * as a bottom-type device. This could cause risks of +- * accidentally erasing critical flash sectors. We thus define +- * a single, write-protected partition covering the whole +- * flash. TODO: once the flash part TOP/BOTTOM detection +- * issue is sorted out in the MTD code, break this into at +- * least three partitions: 'u-boot code', 'u-boot environment' +- * and 'whatever is left'. +- */ +- flash@0 { +- compatible = "cfi-flash"; +- reg = <0 0x80000>; +- bank-width = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "Full512Kb"; +- reg = <0 0x80000>; +- read-only; +- }; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- +- ethernet-port@0 { +- phy-handle = <ðphy>; +- }; +-}; +- +-&i2c { +- status = "okay"; +- clock-frequency = <100000>; +- #address-cells = <1>; +- +- rtc@32 { +- compatible = "ricoh,rs5c372a"; +- reg = <0x32>; +- interrupt-parent = <&gpio0>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy: ethernet-phy { +- reg = <8>; +- }; +-}; +- +-&pinctrl { +- pinctrl-0 = <&pmx_rtc &pmx_power_led_ctrl>; +- pinctrl-names = "default"; +- +- pmx_power_button: pmx-power-button { +- marvell,pins = "mpp18"; +- marvell,function = "gpio"; +- }; +- +- pmx_power_led: pmx-power-led { +- marvell,pins = "mpp16"; +- marvell,function = "gpio"; +- }; +- +- pmx_power_led_ctrl: pmx-power-led-ctrl { +- marvell,pins = "mpp17"; +- marvell,function = "gpio"; +- }; +- +- pmx_rtc: pmx-rtc { +- marvell,pins = "mpp3"; +- marvell,function = "gpio"; +- }; +-}; +- +-&sata { +- pinctrl-0 = <&pmx_sata0 &pmx_sata1>; +- pinctrl-names = "default"; +- status = "okay"; +- nr-ports = <2>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/orion5x-linkstation-lschl.dts b/scripts/dtc/include-prefixes/arm/orion5x-linkstation-lschl.dts +deleted file mode 100644 +index ee751995c8d0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/orion5x-linkstation-lschl.dts ++++ /dev/null +@@ -1,171 +0,0 @@ +-/* +- * Device Tree file for Buffalo Linkstation LS-CHLv3 +- * +- * Copyright (C) 2016 Ash Hughes +- * Copyright (C) 2015-2017 +- * Roger Shimizu +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include "orion5x-linkstation.dtsi" +-#include "mvebu-linkstation-gpio-simple.dtsi" +-#include "mvebu-linkstation-fan.dtsi" +-#include +- +-/ { +- model = "Buffalo Linkstation LiveV3 (LS-CHL)"; +- compatible = "buffalo,lschl", "marvell,orion5x-88f5182", "marvell,orion5x"; +- +- memory { /* 128 MB */ +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +- +- gpio_keys { +- func { +- label = "Function Button"; +- linux,code = ; +- gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; +- }; +- +- power-on-switch { +- gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; +- }; +- +- power-auto-switch { +- gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio_leds { +- pinctrl-0 = <&pmx_led_power &pmx_led_alarm &pmx_led_info &pmx_led_func>; +- blue-power-led { +- gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; +- }; +- +- red-alarm-led { +- gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; +- }; +- +- amber-info-led { +- gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; +- }; +- +- func { +- label = "lschl:func:blue:top"; +- gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio_fan { +- gpios = <&gpio0 14 GPIO_ACTIVE_LOW +- &gpio0 16 GPIO_ACTIVE_LOW>; +- +- alarm-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&pinctrl { +- pmx_led_power: pmx-leds { +- marvell,pins = "mpp0"; +- marvell,function = "gpio"; +- }; +- +- pmx_power_hdd: pmx-power-hdd { +- marvell,pins = "mpp1"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_alarm: pmx-leds { +- marvell,pins = "mpp2"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_info: pmx-leds { +- marvell,pins = "mpp3"; +- marvell,function = "gpio"; +- }; +- +- pmx_fan_lock: pmx-fan-lock { +- marvell,pins = "mpp6"; +- marvell,function = "gpio"; +- }; +- +- pmx_power_switch: pmx-power-switch { +- marvell,pins = "mpp8", "mpp10", "mpp15"; +- marvell,function = "gpio"; +- }; +- +- pmx_power_usb: pmx-power-usb { +- marvell,pins = "mpp9"; +- marvell,function = "gpio"; +- }; +- +- pmx_fan_high: pmx-fan-high { +- marvell,pins = "mpp14"; +- marvell,function = "gpio"; +- }; +- +- pmx_fan_low: pmx-fan-low { +- marvell,pins = "mpp16"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_func: pmx-leds { +- marvell,pins = "mpp17"; +- marvell,function = "gpio"; +- }; +- +- pmx_sw_init: pmx-sw-init { +- marvell,pins = "mpp7"; +- marvell,function = "gpio"; +- }; +-}; +- +-&hdd_power { +- gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; +-}; +- +-&usb_power { +- gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/orion5x-linkstation-lsgl.dts b/scripts/dtc/include-prefixes/arm/orion5x-linkstation-lsgl.dts +deleted file mode 100644 +index 9f6fedd39170..000000000000 +--- a/scripts/dtc/include-prefixes/arm/orion5x-linkstation-lsgl.dts ++++ /dev/null +@@ -1,91 +0,0 @@ +-/* +- * Device Tree file for Buffalo Linkstation LS-GL +- * (also known as Buffalo Linkstation Pro/Live) +- * +- * Copyright (C) 2016 +- * Roger Shimizu +- * +- * Based on the board file arch/arm/mach-orion5x/kurobox_pro-setup.c +- * Copyright (C) Ronen Shitrit +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include "orion5x-linkstation.dtsi" +-#include +- +-/ { +- model = "Buffalo Linkstation Pro/Live"; +- compatible = "buffalo,lsgl", "marvell,orion5x-88f5182", "marvell,orion5x"; +- +- memory { /* 128 MB */ +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; +- }; +-}; +- +-&pinctrl { +- pmx_power_hdd: pmx-power-hdd { +- marvell,pins = "mpp1"; +- marvell,function = "gpio"; +- }; +- +- pmx_power_usb: pmx-power-usb { +- marvell,pins = "mpp9"; +- marvell,function = "gpio"; +- }; +-}; +- +-&hdd_power { +- gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; +-}; +- +-&usb_power { +- gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; +-}; +- +-&sata { +- nr-ports = <2>; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/orion5x-linkstation-lswtgl.dts b/scripts/dtc/include-prefixes/arm/orion5x-linkstation-lswtgl.dts +deleted file mode 100644 +index 7f77ce8cc1fc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/orion5x-linkstation-lswtgl.dts ++++ /dev/null +@@ -1,151 +0,0 @@ +-/* +- * Device Tree file for Buffalo Linkstation LS-WTGL +- * +- * Copyright (C) 2015, 2016 +- * Roger Shimizu +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include "orion5x-linkstation.dtsi" +-#include "mvebu-linkstation-gpio-simple.dtsi" +-#include "mvebu-linkstation-fan.dtsi" +-#include +- +-/ { +- model = "Buffalo Linkstation LS-WTGL"; +- compatible = "buffalo,lswtgl", "marvell,orion5x-88f5182", "marvell,orion5x"; +- +- memory { /* 64 MB */ +- device_type = "memory"; +- reg = <0x00000000 0x4000000>; +- }; +- +- gpio_keys { +- power-on-switch { +- gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; +- }; +- +- power-auto-switch { +- gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio_leds { +- blue-power-led { +- gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; +- }; +- +- red-alarm-led { +- gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; +- }; +- +- amber-info-led { +- gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio_fan { +- gpios = <&gpio0 14 GPIO_ACTIVE_LOW +- &gpio0 17 GPIO_ACTIVE_LOW>; +- +- alarm-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&pinctrl { +- pmx_led_power: pmx-leds { +- marvell,pins = "mpp0"; +- marvell,function = "gpio"; +- }; +- +- pmx_power_hdd: pmx-power-hdd { +- marvell,pins = "mpp1"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_alarm: pmx-leds { +- marvell,pins = "mpp2"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_info: pmx-leds { +- marvell,pins = "mpp3"; +- marvell,function = "gpio"; +- }; +- +- pmx_fan_lock: pmx-fan-lock { +- marvell,pins = "mpp6"; +- marvell,function = "gpio"; +- }; +- +- pmx_power_switch: pmx-power-switch { +- marvell,pins = "mpp8", "mpp10"; +- marvell,function = "gpio"; +- }; +- +- pmx_power_usb: pmx-power-usb { +- marvell,pins = "mpp9"; +- marvell,function = "gpio"; +- }; +- +- pmx_fan_high: pmx-fan-high { +- marvell,pins = "mpp14"; +- marvell,function = "gpio"; +- }; +- +- pmx_fan_low: pmx-fan-low { +- marvell,pins = "mpp17"; +- marvell,function = "gpio"; +- }; +-}; +- +-&hdd_power { +- gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; +-}; +- +-&usb_power { +- gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; +-}; +- +-&sata { +- nr-ports = <2>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/orion5x-linkstation.dtsi b/scripts/dtc/include-prefixes/arm/orion5x-linkstation.dtsi +deleted file mode 100644 +index b6c9b85951ea..000000000000 +--- a/scripts/dtc/include-prefixes/arm/orion5x-linkstation.dtsi ++++ /dev/null +@@ -1,180 +0,0 @@ +-/* +- * Device Tree common file for orion5x based Buffalo Linkstation +- * +- * Copyright (C) 2015, 2016 +- * Roger Shimizu +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "orion5x-mv88f5182.dtsi" +- +-/ { +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- soc { +- ranges = , +- , +- ; +- }; +- +- restart_poweroff { +- compatible = "restart-poweroff"; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_power_usb &pmx_power_hdd>; +- pinctrl-names = "default"; +- +- usb_power: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "USB Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- hdd_power: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "HDD Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +-}; +- +-&pinctrl { +- pmx_power_hdd: pmx-power-hdd { +- marvell,function = "gpio"; +- }; +- +- pmx_power_usb: pmx-power-usb { +- marvell,function = "gpio"; +- }; +-}; +- +-&devbus_bootcs { +- status = "okay"; +- devbus,keep-config; +- +- flash@0 { +- compatible = "jedec-flash"; +- reg = <0 0x40000>; +- bank-width = <1>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- header@0 { +- reg = <0 0x30000>; +- read-only; +- }; +- +- uboot@30000 { +- reg = <0x30000 0xF000>; +- read-only; +- }; +- +- uboot_env@3F000 { +- reg = <0x3F000 0x1000>; +- }; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy: ethernet-phy { +- reg = <8>; +- }; +-}; +- +-ð { +- status = "okay"; +- +- ethernet-port@0 { +- phy-handle = <ðphy>; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&i2c { +- status = "okay"; +- +- rtc@32 { +- compatible = "ricoh,rs5c372a"; +- reg = <0x32>; +- }; +-}; +- +-&wdt { +- status = "disabled"; +-}; +- +-&sata { +- status = "okay"; +- nr-ports = <1>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/orion5x-lswsgl.dts b/scripts/dtc/include-prefixes/arm/orion5x-lswsgl.dts +deleted file mode 100644 +index 2fbc17d6dfa4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/orion5x-lswsgl.dts ++++ /dev/null +@@ -1,277 +0,0 @@ +-/* +- * Copyright (C) 2015 Benjamin Cama +- * Copyright (C) 2014 Thomas Petazzoni +- * Based on the board file arch/arm/mach-orion5x/lsmini-setup.c, +- * Copyright (C) 2008 Alexey Kopytko +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include "orion5x-mv88f5182.dtsi" +- +-/ { +- model = "Buffalo Linkstation Mini (LS-WSGL)"; +- compatible = "buffalo,lswsgl", "marvell,orion5x-88f5182", "marvell,orion5x"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; /* 128 MB */ +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- soc { +- ranges = , +- , +- ; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&pmx_buttons>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- func { +- label = "Function Button"; +- linux,code = ; +- gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; +- }; +- +- power { +- label = "Power-on Switch"; +- linux,input-type = <5>; /* EV_SW */ +- linux,code = ; /* LSMINI_SW_POWER */ +- gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; +- }; +- +- autopower { +- label = "Power-auto Switch"; +- linux,input-type = <5>; /* EV_SW */ +- linux,code = ; /* LSMINI_SW_AUTOPOWER */ +- gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_led_alarm &pmx_led_info &pmx_led_func +- &pmx_led_power>; +- pinctrl-names = "default"; +- +- alarm { +- label = "lswsgl:alarm:red"; +- gpio = <&gpio0 2 GPIO_ACTIVE_LOW>; +- }; +- +- info { +- label = "lswsgl:info:amber"; +- gpio = <&gpio0 3 GPIO_ACTIVE_LOW>; +- }; +- +- func { +- label = "lswsgl:func:blue:top"; +- gpio = <&gpio0 9 GPIO_ACTIVE_LOW>; +- }; +- +- power { +- label = "lswsgl:power:blue:bottom"; +- gpio = <&gpio0 14 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- }; +- +- restart_poweroff { +- compatible = "restart-poweroff"; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power &pmx_usb_power>; +- pinctrl-names = "default"; +- +- sata0_power: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "SATA0 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 1 GPIO_ACTIVE_HIGH>; +- }; +- +- sata1_power: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "SATA1 Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>; +- }; +- +- usb_power: regulator@2 { +- compatible = "regulator-fixed"; +- reg = <2>; +- regulator-name = "USB Power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&devbus_bootcs { +- status = "okay"; +- +- devbus,keep-config; +- +- flash@0 { +- compatible = "cfi-flash"; +- reg = <0 0x40000>; +- bank-width = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "Full256Kb"; +- reg = <0 0x40000>; +- read-only; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy: ethernet-phy { +- reg = <8>; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- +- ethernet-port@0 { +- phy-handle = <ðphy>; +- }; +-}; +- +-&i2c { +- status = "okay"; +- clock-frequency = <100000>; +- #address-cells = <1>; +- +- rtc@32 { +- compatible = "ricoh,rs5c372a"; +- reg = <0x32>; +- }; +-}; +- +-&pinctrl { +- pmx_buttons: pmx-buttons { +- marvell,pins = "mpp15", "mpp17", "mpp18"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_alarm: pmx-leds { +- marvell,pins = "mpp2"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_info: pmx-leds { +- marvell,pins = "mpp3"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_func: pmx-leds { +- marvell,pins = "mpp9"; +- marvell,function = "gpio"; +- }; +- +- pmx_led_power: pmx-leds { +- marvell,pins = "mpp14"; +- marvell,function = "gpio"; +- }; +- +- pmx_sata0_power: pmx-sata0-power { +- marvell,pins = "mpp1"; +- marvell,function = "gpio"; +- }; +- +- pmx_sata1_power: pmx-sata1-power { +- marvell,pins = "mpp19"; +- marvell,function = "gpio"; +- }; +- +- pmx_usb_power: pmx-usb-power { +- marvell,pins = "mpp16"; +- marvell,function = "gpio"; +- }; +-}; +- +-&sata { +- status = "okay"; +- nr-ports = <2>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/orion5x-maxtor-shared-storage-2.dts b/scripts/dtc/include-prefixes/arm/orion5x-maxtor-shared-storage-2.dts +deleted file mode 100644 +index 0ca6208a267d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/orion5x-maxtor-shared-storage-2.dts ++++ /dev/null +@@ -1,179 +0,0 @@ +-/* +- * Copyright (C) 2014 Thomas Petazzoni +- * Copyright (C) Sylver Bruneau +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without any +- * warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include "orion5x-mv88f5182.dtsi" +- +-/ { +- model = "Maxtor Shared Storage II"; +- compatible = "maxtor,shared-storage-2", "marvell,orion5x-88f5182", "marvell,orion5x"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x4000000>; /* 64 MB */ +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- soc { +- ranges = , +- , +- ; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&pmx_buttons>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- power { +- label = "Power"; +- linux,code = ; +- gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; +- }; +- +- reset { +- label = "Reset"; +- linux,code = ; +- gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&devbus_bootcs { +- status = "okay"; +- +- devbus,keep-config; +- +- /* +- * Currently the MTD code does not recognize the MX29LV400CBCT +- * as a bottom-type device. This could cause risks of +- * accidentally erasing critical flash sectors. We thus define +- * a single, write-protected partition covering the whole +- * flash. TODO: once the flash part TOP/BOTTOM detection +- * issue is sorted out in the MTD code, break this into at +- * least three partitions: 'u-boot code', 'u-boot environment' +- * and 'whatever is left'. +- */ +- flash@0 { +- compatible = "cfi-flash"; +- reg = <0 0x40000>; +- bank-width = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy: ethernet-phy { +- reg = <8>; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- +- ethernet-port@0 { +- phy-handle = <ðphy>; +- }; +-}; +- +-&i2c { +- status = "okay"; +- clock-frequency = <100000>; +- #address-cells = <1>; +- +- rtc@68 { +- compatible = "st,m41t81"; +- reg = <0x68>; +- pinctrl-0 = <&pmx_rtc>; +- pinctrl-names = "default"; +- interrupt-parent = <&gpio0>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&pinctrl { +- pinctrl-0 = <&pmx_leds &pmx_misc>; +- pinctrl-names = "default"; +- +- pmx_buttons: pmx-buttons { +- marvell,pins = "mpp11", "mpp12"; +- marvell,function = "gpio"; +- }; +- +- /* +- * MPP0: Power LED +- * MPP1: Error LED +- */ +- pmx_leds: pmx-leds { +- marvell,pins = "mpp0", "mpp1"; +- marvell,function = "gpio"; +- }; +- +- /* +- * MPP4: HDD ind. (Single/Dual) +- * MPP5: HD0 5V control +- * MPP6: HD0 12V control +- * MPP7: HD1 5V control +- * MPP8: HD1 12V control +- */ +- pmx_misc: pmx-misc { +- marvell,pins = "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp10"; +- marvell,function = "gpio"; +- }; +- +- pmx_rtc: pmx-rtc { +- marvell,pins = "mpp3"; +- marvell,function = "gpio"; +- }; +- +- pmx_sata0_led_active: pmx-sata0-led-active { +- marvell,pins = "mpp14"; +- marvell,function = "sata0"; +- }; +- +- pmx_sata1_led_active: pmx-sata1-led-active { +- marvell,pins = "mpp15"; +- marvell,function = "sata1"; +- }; +- +- /* +- * Non MPP GPIOs: +- * GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok) +- * GPIO 23: Blue front LED off +- * GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled) +- */ +-}; +- +-&sata { +- pinctrl-0 = <&pmx_sata0_led_active +- &pmx_sata1_led_active>; +- pinctrl-names = "default"; +- status = "okay"; +- nr-ports = <2>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/orion5x-mv88f5181.dtsi b/scripts/dtc/include-prefixes/arm/orion5x-mv88f5181.dtsi +deleted file mode 100644 +index f667012b26ca..000000000000 +--- a/scripts/dtc/include-prefixes/arm/orion5x-mv88f5181.dtsi ++++ /dev/null +@@ -1,49 +0,0 @@ +-/* +- * Copyright (C) 2016 Jamie Lentin +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without any +- * warranty of any kind, whether express or implied. +- */ +- +-#include "orion5x.dtsi" +- +-/ { +- compatible = "marvell,orion5x-88f5181", "marvell,orion5x"; +- +- soc { +- compatible = "marvell,orion5x-88f5181-mbus", "simple-bus"; +- +- internal-regs { +- pinctrl: pinctrl@10000 { +- compatible = "marvell,88f5181-pinctrl"; +- reg = <0x10000 0x8>, <0x10050 0x4>; +- }; +- +- core_clk: core-clocks@10030 { +- compatible = "marvell,mv88f5181-core-clock"; +- reg = <0x10010 0x4>; +- #clock-cells = <1>; +- }; +- +- mbusc: mbus-controller@20000 { +- compatible = "marvell,mbus-controller"; +- reg = <0x20000 0x100>, <0x1500 0x20>; +- }; +- }; +- }; +-}; +- +-&pinctrl { +- pmx_ge: pmx-ge { +- marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11", +- "mpp12", "mpp13", "mpp14", "mpp15", +- "mpp16", "mpp17", "mpp18", "mpp19"; +- marvell,function = "ge"; +- }; +-}; +- +-ð { +- pinctrl-0 = <&pmx_ge>; +- pinctrl-names = "default"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/orion5x-mv88f5182.dtsi b/scripts/dtc/include-prefixes/arm/orion5x-mv88f5182.dtsi +deleted file mode 100644 +index d1ed71c60209..000000000000 +--- a/scripts/dtc/include-prefixes/arm/orion5x-mv88f5182.dtsi ++++ /dev/null +@@ -1,45 +0,0 @@ +-/* +- * Copyright (C) 2014 Thomas Petazzoni +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without any +- * warranty of any kind, whether express or implied. +- */ +- +-#include "orion5x.dtsi" +- +-/ { +- compatible = "marvell,orion5x-88f5182", "marvell,orion5x"; +- +- soc { +- compatible = "marvell,orion5x-88f5182-mbus", "simple-bus"; +- +- internal-regs { +- pinctrl: pinctrl@10000 { +- compatible = "marvell,88f5182-pinctrl"; +- reg = <0x10000 0x8>, <0x10050 0x4>; +- +- pmx_sata0: pmx-sata0 { +- marvell,pins = "mpp12", "mpp14"; +- marvell,function = "sata0"; +- }; +- +- pmx_sata1: pmx-sata1 { +- marvell,pins = "mpp13", "mpp15"; +- marvell,function = "sata1"; +- }; +- }; +- +- core_clk: core-clocks@10030 { +- compatible = "marvell,mv88f5182-core-clock"; +- reg = <0x10010 0x4>; +- #clock-cells = <1>; +- }; +- +- mbusc: mbus-controller@20000 { +- compatible = "marvell,mbus-controller"; +- reg = <0x20000 0x100>, <0x1500 0x20>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/orion5x-netgear-wnr854t.dts b/scripts/dtc/include-prefixes/arm/orion5x-netgear-wnr854t.dts +deleted file mode 100644 +index ea081afa469d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/orion5x-netgear-wnr854t.dts ++++ /dev/null +@@ -1,252 +0,0 @@ +-/* +- * Copyright (C) 2016 Jamie Lentin +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without any +- * warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "orion5x-mv88f5181.dtsi" +- +-/ { +- model = "Netgear WNR854-t"; +- compatible = "netgear,wnr854t", "marvell,orion5x-88f5181", +- "marvell,orion5x"; +- aliases { +- serial0 = &uart0; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x2000000>; /* 32 MB */ +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- soc { +- ranges = , +- , +- ; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&pmx_reset_button>; +- pinctrl-names = "default"; +- +- reset { +- label = "Reset Button"; +- linux,code = ; +- gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>; +- pinctrl-names = "default"; +- +- led@0 { +- label = "wnr854t:green:power"; +- gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; +- }; +- +- led@1 { +- label = "wnr854t:blink:power"; +- gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; +- }; +- +- led@2 { +- label = "wnr854t:green:wan"; +- gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&devbus_bootcs { +- status = "okay"; +- +- devbus,keep-config; +- +- flash@0 { +- compatible = "cfi-flash"; +- reg = <0 0x800000>; +- bank-width = <2>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "kernel"; +- reg = <0x0 0x100000>; +- }; +- +- partition@100000 { +- label = "rootfs"; +- reg = <0x100000 0x660000>; +- }; +- +- partition@760000 { +- label = "uboot_env"; +- reg = <0x760000 0x20000>; +- }; +- +- partition@780000 { +- label = "uboot"; +- reg = <0x780000 0x80000>; +- read-only; +- }; +- }; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- switch: switch@0 { +- compatible = "marvell,mv88e6085"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- dsa,member = <0 0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan3"; +- phy-handle = <&lan3phy>; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan4"; +- phy-handle = <&lan4phy>; +- }; +- +- port@2 { +- reg = <2>; +- label = "wan"; +- phy-handle = <&wanphy>; +- }; +- +- port@3 { +- reg = <3>; +- label = "cpu"; +- ethernet = <ðport>; +- }; +- +- port@5 { +- reg = <5>; +- label = "lan1"; +- phy-handle = <&lan1phy>; +- }; +- +- port@7 { +- reg = <7>; +- label = "lan2"; +- phy-handle = <&lan2phy>; +- }; +- }; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- lan3phy: ethernet-phy@0 { +- /* Marvell 88E1121R (port 1) */ +- compatible = "ethernet-phy-id0141.0cb0", +- "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; +- }; +- +- lan4phy: ethernet-phy@1 { +- /* Marvell 88E1121R (port 2) */ +- compatible = "ethernet-phy-id0141.0cb0", +- "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; +- }; +- +- wanphy: ethernet-phy@2 { +- /* Marvell 88E1121R (port 1) */ +- compatible = "ethernet-phy-id0141.0cb0", +- "ethernet-phy-ieee802.3-c22"; +- reg = <2>; +- marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; +- }; +- +- lan1phy: ethernet-phy@5 { +- /* Marvell 88E1112 */ +- compatible = "ethernet-phy-id0141.0cb0", +- "ethernet-phy-ieee802.3-c22"; +- reg = <5>; +- marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; +- }; +- +- lan2phy: ethernet-phy@7 { +- /* Marvell 88E1112 */ +- compatible = "ethernet-phy-id0141.0cb0", +- "ethernet-phy-ieee802.3-c22"; +- reg = <7>; +- marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; +- }; +- }; +- }; +-}; +- +-ð { +- status = "okay"; +- +- ethernet-port@0 { +- /* Hardwired to DSA switch */ +- speed = <1000>; +- duplex = <1>; +- }; +-}; +- +-&pinctrl { +- pinctrl-0 = <&pmx_pci_gpios>; +- pinctrl-names = "default"; +- +- pmx_power_led: pmx-power-led { +- marvell,pins = "mpp0"; +- marvell,function = "gpio"; +- }; +- +- pmx_reset_button: pmx-reset-button { +- marvell,pins = "mpp1"; +- marvell,function = "gpio"; +- }; +- +- pmx_power_led_blink: pmx-power-led-blink { +- marvell,pins = "mpp2"; +- marvell,function = "gpio"; +- }; +- +- pmx_wan_led: pmx-wan-led { +- marvell,pins = "mpp3"; +- marvell,function = "gpio"; +- }; +- +- pmx_pci_gpios: pmx-pci-gpios { +- marvell,pins = "mpp4"; +- marvell,function = "gpio"; +- }; +-}; +- +-&uart0 { +- /* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */ +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/orion5x-rd88f5182-nas.dts b/scripts/dtc/include-prefixes/arm/orion5x-rd88f5182-nas.dts +deleted file mode 100644 +index 487324f7c54e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/orion5x-rd88f5182-nas.dts ++++ /dev/null +@@ -1,178 +0,0 @@ +-/* +- * Copyright (C) 2014 Thomas Petazzoni +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without any +- * warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-#include +-#include "orion5x-mv88f5182.dtsi" +- +-/ { +- model = "Marvell Reference Design 88F5182 NAS"; +- compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x4000000>; /* 64 MB */ +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlyprintk"; +- stdout-path = &uart0; +- }; +- +- soc { +- ranges = , +- , +- , +- ; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pmx_debug_led>; +- pinctrl-names = "default"; +- +- led@0 { +- label = "rd88f5182:cpu"; +- linux,default-trigger = "heartbeat"; +- gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&devbus_bootcs { +- status = "okay"; +- +- /* Read parameters */ +- devbus,bus-width = <8>; +- devbus,turn-off-ps = <90000>; +- devbus,badr-skew-ps = <0>; +- devbus,acc-first-ps = <186000>; +- devbus,acc-next-ps = <186000>; +- +- /* Write parameters */ +- devbus,wr-high-ps = <90000>; +- devbus,wr-low-ps = <90000>; +- devbus,ale-wr-ps = <90000>; +- +- flash@0 { +- compatible = "cfi-flash"; +- reg = <0 0x80000>; +- bank-width = <1>; +- }; +-}; +- +-&devbus_cs1 { +- status = "okay"; +- +- /* Read parameters */ +- devbus,bus-width = <8>; +- devbus,turn-off-ps = <90000>; +- devbus,badr-skew-ps = <0>; +- devbus,acc-first-ps = <186000>; +- devbus,acc-next-ps = <186000>; +- +- /* Write parameters */ +- devbus,wr-high-ps = <90000>; +- devbus,wr-low-ps = <90000>; +- devbus,ale-wr-ps = <90000>; +- +- flash@0 { +- compatible = "cfi-flash"; +- reg = <0 0x1000000>; +- bank-width = <1>; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- +- ethernet-port@0 { +- phy-handle = <ðphy>; +- }; +-}; +- +-&i2c { +- status = "okay"; +- clock-frequency = <100000>; +- #address-cells = <1>; +- +- rtc@68 { +- pinctrl-0 = <&pmx_rtc>; +- pinctrl-names = "default"; +- compatible = "dallas,ds1338"; +- reg = <0x68>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- ethphy: ethernet-phy { +- reg = <8>; +- }; +-}; +- +-&pinctrl { +- pinctrl-0 = <&pmx_reset_switch &pmx_misc_gpios +- &pmx_pci_gpios>; +- pinctrl-names = "default"; +- +- /* +- * MPP[20] PCI Clock to MV88F5182 +- * MPP[21] PCI Clock to mini PCI CON11 +- * MPP[22] USB 0 over current indication +- * MPP[23] USB 1 over current indication +- * MPP[24] USB 1 over current enable +- * MPP[25] USB 0 over current enable +- */ +- +- pmx_debug_led: pmx-debug_led { +- marvell,pins = "mpp0"; +- marvell,function = "gpio"; +- }; +- +- pmx_reset_switch: pmx-reset-switch { +- marvell,pins = "mpp1"; +- marvell,function = "gpio"; +- }; +- +- pmx_rtc: pmx-rtc { +- marvell,pins = "mpp3"; +- marvell,function = "gpio"; +- }; +- +- pmx_misc_gpios: pmx-misc-gpios { +- marvell,pins = "mpp4", "mpp5"; +- marvell,function = "gpio"; +- }; +- +- pmx_pci_gpios: pmx-pci-gpios { +- marvell,pins = "mpp6", "mpp7"; +- marvell,function = "gpio"; +- }; +-}; +- +-&sata { +- pinctrl-0 = <&pmx_sata0 &pmx_sata1>; +- pinctrl-names = "default"; +- status = "okay"; +- nr-ports = <2>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/orion5x.dtsi b/scripts/dtc/include-prefixes/arm/orion5x.dtsi +deleted file mode 100644 +index 61e631b3fd8b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/orion5x.dtsi ++++ /dev/null +@@ -1,241 +0,0 @@ +-/* +- * Copyright (C) 2012 Thomas Petazzoni +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without any +- * warranty of any kind, whether express or implied. +- */ +- +-#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Marvell Orion5x SoC"; +- compatible = "marvell,orion5x"; +- interrupt-parent = <&intc>; +- +- aliases { +- gpio0 = &gpio0; +- }; +- +- soc { +- #address-cells = <2>; +- #size-cells = <1>; +- controller = <&mbusc>; +- +- devbus_bootcs: devbus-bootcs { +- compatible = "marvell,orion-devbus"; +- reg = ; +- ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&core_clk 0>; +- status = "disabled"; +- }; +- +- devbus_cs0: devbus-cs0 { +- compatible = "marvell,orion-devbus"; +- reg = ; +- ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&core_clk 0>; +- status = "disabled"; +- }; +- +- devbus_cs1: devbus-cs1 { +- compatible = "marvell,orion-devbus"; +- reg = ; +- ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&core_clk 0>; +- status = "disabled"; +- }; +- +- devbus_cs2: devbus-cs2 { +- compatible = "marvell,orion-devbus"; +- reg = ; +- ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&core_clk 0>; +- status = "disabled"; +- }; +- +- internal-regs { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; +- +- gpio0: gpio@10100 { +- compatible = "marvell,orion-gpio"; +- #gpio-cells = <2>; +- gpio-controller; +- reg = <0x10100 0x40>; +- ngpios = <32>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <6>, <7>, <8>, <9>; +- }; +- +- spi: spi@10600 { +- compatible = "marvell,orion-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- reg = <0x10600 0x28>; +- status = "disabled"; +- }; +- +- i2c: i2c@11000 { +- compatible = "marvell,mv64xxx-i2c"; +- reg = <0x11000 0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <5>; +- clocks = <&core_clk 0>; +- status = "disabled"; +- }; +- +- uart0: serial@12000 { +- compatible = "ns16550a"; +- reg = <0x12000 0x100>; +- reg-shift = <2>; +- interrupts = <3>; +- clocks = <&core_clk 0>; +- status = "disabled"; +- }; +- +- uart1: serial@12100 { +- compatible = "ns16550a"; +- reg = <0x12100 0x100>; +- reg-shift = <2>; +- interrupts = <4>; +- clocks = <&core_clk 0>; +- status = "disabled"; +- }; +- +- bridge_intc: bridge-interrupt-ctrl@20110 { +- compatible = "marvell,orion-bridge-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x20110 0x8>; +- interrupts = <0>; +- marvell,#interrupts = <4>; +- }; +- +- intc: interrupt-controller@20200 { +- compatible = "marvell,orion-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x20200 0x08>; +- }; +- +- timer: timer@20300 { +- compatible = "marvell,orion-timer"; +- reg = <0x20300 0x20>; +- interrupt-parent = <&bridge_intc>; +- interrupts = <1>, <2>; +- clocks = <&core_clk 0>; +- }; +- +- wdt: wdt@20300 { +- compatible = "marvell,orion-wdt"; +- reg = <0x20300 0x28>, <0x20108 0x4>; +- interrupt-parent = <&bridge_intc>; +- interrupts = <3>; +- clocks = <&core_clk 0>; +- status = "okay"; +- }; +- +- ehci0: ehci@50000 { +- compatible = "marvell,orion-ehci"; +- reg = <0x50000 0x1000>; +- interrupts = <17>; +- status = "disabled"; +- }; +- +- xor: dma-controller@60900 { +- compatible = "marvell,orion-xor"; +- reg = <0x60900 0x100 +- 0x60b00 0x100>; +- status = "okay"; +- +- xor00 { +- interrupts = <30>; +- dmacap,memcpy; +- dmacap,xor; +- }; +- xor01 { +- interrupts = <31>; +- dmacap,memcpy; +- dmacap,xor; +- dmacap,memset; +- }; +- }; +- +- eth: ethernet-controller@72000 { +- compatible = "marvell,orion-eth"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x72000 0x4000>; +- marvell,tx-checksum-limit = <1600>; +- status = "disabled"; +- +- ethport: ethernet-port@0 { +- compatible = "marvell,orion-eth-port"; +- reg = <0>; +- interrupts = <21>; +- /* overwrite MAC address in bootloader */ +- local-mac-address = [00 00 00 00 00 00]; +- /* set phy-handle property in board file */ +- }; +- }; +- +- mdio: mdio-bus@72004 { +- compatible = "marvell,orion-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x72004 0x84>; +- interrupts = <22>; +- status = "disabled"; +- +- /* add phy nodes in board file */ +- }; +- +- sata: sata@80000 { +- compatible = "marvell,orion-sata"; +- reg = <0x80000 0x5000>; +- interrupts = <29>; +- status = "disabled"; +- }; +- +- cesa: crypto@90000 { +- compatible = "marvell,orion-crypto"; +- reg = <0x90000 0x10000>; +- reg-names = "regs"; +- interrupts = <28>; +- marvell,crypto-srams = <&crypto_sram>; +- marvell,crypto-sram-size = <0x800>; +- status = "okay"; +- }; +- +- ehci1: ehci@a0000 { +- compatible = "marvell,orion-ehci"; +- reg = <0xa0000 0x1000>; +- interrupts = <12>; +- status = "disabled"; +- }; +- }; +- +- crypto_sram: sa-sram { +- compatible = "mmio-sram"; +- reg = ; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/owl-s500-cubieboard6.dts b/scripts/dtc/include-prefixes/arm/owl-s500-cubieboard6.dts +deleted file mode 100644 +index c2b02895910c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/owl-s500-cubieboard6.dts ++++ /dev/null +@@ -1,36 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Cubietech CubieBoard6 +- * +- * Copyright (c) 2017 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "owl-s500.dtsi" +- +-/ { +- compatible = "cubietech,cubieboard6", "actions,s500"; +- model = "CubieBoard6"; +- +- aliases { +- serial3 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial3:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x80000000>; +- }; +-}; +- +-&timer { +- clocks = <&hosc>; +-}; +- +-&uart3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/owl-s500-guitar-bb-rev-b.dts b/scripts/dtc/include-prefixes/arm/owl-s500-guitar-bb-rev-b.dts +deleted file mode 100644 +index 7ae34a23e320..000000000000 +--- a/scripts/dtc/include-prefixes/arm/owl-s500-guitar-bb-rev-b.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016-2017 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "owl-s500-guitar.dtsi" +- +-/ { +- compatible = "lemaker,guitar-bb-rev-b", "lemaker,guitar", "actions,s500"; +- model = "LeMaker Guitar Base Board rev. B"; +- +- aliases { +- serial3 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial3:115200n8"; +- }; +-}; +- +-&uart3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/owl-s500-guitar.dtsi b/scripts/dtc/include-prefixes/arm/owl-s500-guitar.dtsi +deleted file mode 100644 +index 81cc39871f17..000000000000 +--- a/scripts/dtc/include-prefixes/arm/owl-s500-guitar.dtsi ++++ /dev/null +@@ -1,21 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * LeMaker Guitar SoM +- * +- * Copyright (c) 2016-2017 Andreas Färber +- */ +- +-#include "owl-s500.dtsi" +- +-/ { +- compatible = "lemaker,guitar", "actions,s500"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x40000000>; +- }; +-}; +- +-&timer { +- clocks = <&hosc>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/owl-s500-labrador-base-m.dts b/scripts/dtc/include-prefixes/arm/owl-s500-labrador-base-m.dts +deleted file mode 100644 +index 1585e33f703b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/owl-s500-labrador-base-m.dts ++++ /dev/null +@@ -1,28 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Caninos Labrador Base Board +- * +- * Copyright (c) 2019-2020 Matheus Castello +- */ +- +-/dts-v1/; +- +-#include "owl-s500-labrador-v2.dtsi" +- +-/ { +- model = "Caninos Labrador Core v2 on Labrador Base-M v1"; +- compatible = "caninos,labrador-base-m", +- "caninos,labrador-v2", "actions,s500"; +- +- aliases { +- serial3 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial3:115200n8"; +- }; +-}; +- +-&uart3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/owl-s500-labrador-v2.dtsi b/scripts/dtc/include-prefixes/arm/owl-s500-labrador-v2.dtsi +deleted file mode 100644 +index 883ff2f9886d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/owl-s500-labrador-v2.dtsi ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Caninos Labrador SoM V2 +- * +- * Copyright (c) 2019-2020 Matheus Castello +- */ +- +-#include "owl-s500.dtsi" +- +-/ { +- model = "Caninos Labrador Core V2.1"; +- compatible = "caninos,labrador-v2", "actions,s500"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x80000000>; +- }; +-}; +- +-&timer { +- clocks = <&hosc>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/owl-s500-roseapplepi.dts b/scripts/dtc/include-prefixes/arm/owl-s500-roseapplepi.dts +deleted file mode 100644 +index eb555f385283..000000000000 +--- a/scripts/dtc/include-prefixes/arm/owl-s500-roseapplepi.dts ++++ /dev/null +@@ -1,299 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Roseapple Pi +- * +- * Copyright (C) 2020-2021 Cristian Ciocaltea +- */ +- +-/dts-v1/; +- +-#include "owl-s500.dtsi" +- +-/ { +- compatible = "roseapplepi,roseapplepi", "actions,s500"; +- model = "Roseapple Pi"; +- +- aliases { +- mmc0 = &mmc0; +- serial2 = &uart2; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x80000000>; /* 2GB */ +- }; +- +- syspwr: regulator-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "SYSPWR"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +-}; +- +-&cpu0 { +- cpu0-supply = <&vdd_cpu>; +-}; +- +-&i2c0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- +- atc260x: pmic@65 { +- compatible = "actions,atc2603c"; +- reg = <0x65>; +- interrupt-parent = <&sirq>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; +- +- reset-time-sec = <6>; +- +- regulators { +- compatible = "actions,atc2603c-regulator"; +- +- dcdc1-supply = <&syspwr>; +- dcdc2-supply = <&syspwr>; +- dcdc3-supply = <&syspwr>; +- ldo1-supply = <&syspwr>; +- ldo2-supply = <&syspwr>; +- ldo3-supply = <&syspwr>; +- ldo5-supply = <&syspwr>; +- ldo6-supply = <&syspwr>; +- ldo7-supply = <&syspwr>; +- ldo8-supply = <&syspwr>; +- ldo11-supply = <&syspwr>; +- ldo12-supply = <&syspwr>; +- switchldo1-supply = <&vcc>; +- +- vdd_cpu: dcdc1 { +- regulator-name = "VDD_CPU"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- }; +- +- vddq: dcdc2 { +- regulator-name = "VDDQ"; +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <2150000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc: dcdc3 { +- regulator-name = "VCC"; +- regulator-min-microvolt = <2600000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vcc_3v3: ldo1 { +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <2600000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- avcc: ldo2 { +- regulator-name = "AVCC"; +- regulator-min-microvolt = <2600000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_1v8: ldo3 { +- regulator-name = "VDD_1V8"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <2000000>; +- regulator-always-on; +- }; +- +- vcc_3v1: ldo5 { +- regulator-name = "VCC_3V1"; +- regulator-min-microvolt = <2600000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- avdd: ldo6 { +- regulator-name = "AVDD"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- }; +- +- sens_1v8: ldo7 { +- regulator-name = "SENS_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo8: ldo8 { +- regulator-name = "LDO8"; +- regulator-min-microvolt = <2300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- svcc: ldo11 { +- regulator-name = "SVCC"; +- regulator-min-microvolt = <2600000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- rtc_vdd: ldo12 { +- regulator-name = "RTC_VDD"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- sd_vcc: switchldo1 { +- regulator-name = "SD_VCC"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +-}; +- +-&i2c2 { +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +-}; +- +-&pinctrl { +- i2c0_pins: i2c0-pins { +- pinmux { +- groups = "i2c0_mfp"; +- function = "i2c0"; +- }; +- +- pinconf { +- pins = "i2c0_sclk", "i2c0_sdata"; +- bias-pull-up; +- }; +- }; +- +- i2c1_pins: i2c1-pins { +- pinconf { +- pins = "i2c1_sclk", "i2c1_sdata"; +- bias-pull-up; +- }; +- }; +- +- i2c2_pins: i2c2-pins { +- pinconf { +- pins = "i2c2_sclk", "i2c2_sdata"; +- bias-pull-up; +- }; +- }; +- +- mmc0_pins: mmc0-pins { +- pinmux { +- groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp", +- "sd0_cmd_mfp", "sd0_clk_mfp"; +- function = "sd0"; +- }; +- +- drv-pinconf { +- groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv"; +- drive-strength = <8>; +- }; +- +- bias0-pinconf { +- pins = "sd0_d0", "sd0_d1", "sd0_d2", +- "sd0_d3", "sd0_cmd"; +- bias-pull-up; +- }; +- +- bias1-pinconf { +- pins = "sd0_clk"; +- bias-pull-down; +- }; +- }; +- +- ethernet_pins: ethernet-pins { +- eth_rmii-pinmux { +- groups = "rmii_txd0_mfp", "rmii_txd1_mfp", +- "rmii_rxd0_mfp", "rmii_rxd1_mfp", +- "rmii_txen_mfp", "rmii_rxen_mfp", +- "rmii_crs_dv_mfp", "rmii_ref_clk_mfp"; +- function = "eth_rmii"; +- }; +- +- phy_clk-pinmux { +- groups = "clko_25m_mfp"; +- function = "clko_25m"; +- }; +- +- ref_clk-pinconf { +- groups = "rmii_ref_clk_drv"; +- drive-strength = <2>; +- }; +- +- }; +-}; +- +-/* uSD */ +-&mmc0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- no-sdio; +- no-mmc; +- no-1-8-v; +- cd-gpios = <&pinctrl 117 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- vmmc-supply = <&sd_vcc>; +- vqmmc-supply = <&sd_vcc>; +-}; +- +-ðernet { +- pinctrl-names = "default"; +- pinctrl-0 = <ðernet_pins>; +- phy-mode = "rmii"; +- phy-handle = <ð_phy>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reset-gpios = <&pinctrl 88 GPIO_ACTIVE_LOW>; /* GPIOC24 */ +- reset-delay-us = <10000>; +- reset-post-delay-us = <150000>; +- +- eth_phy: ethernet-phy@3 { +- reg = <0x3>; +- max-speed = <100>; +- interrupt-parent = <&sirq>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +-}; +- +-&twd_timer { +- status = "okay"; +-}; +- +-&timer { +- clocks = <&hosc>; +-}; +- +-&uart2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/owl-s500-sparky.dts b/scripts/dtc/include-prefixes/arm/owl-s500-sparky.dts +deleted file mode 100644 +index 9d8f7336bec0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/owl-s500-sparky.dts ++++ /dev/null +@@ -1,36 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Allo.com Sparky +- * +- * Copyright (c) 2017 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "owl-s500.dtsi" +- +-/ { +- compatible = "allo,sparky", "actions,s500"; +- model = "Allo.com Sparky"; +- +- aliases { +- serial3 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial3:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x40000000>; /* 1 or 2 GiB */ +- }; +-}; +- +-&timer { +- clocks = <&hosc>; +-}; +- +-&uart3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/owl-s500.dtsi b/scripts/dtc/include-prefixes/arm/owl-s500.dtsi +deleted file mode 100644 +index 739b4b9cec8c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/owl-s500.dtsi ++++ /dev/null +@@ -1,338 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Actions Semi S500 SoC +- * +- * Copyright (c) 2016-2017 Andreas Färber +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "actions,s500"; +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- }; +- +- chosen { +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0x0>; +- enable-method = "actions,s500-smp"; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0x1>; +- enable-method = "actions,s500-smp"; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0x2>; +- enable-method = "actions,s500-smp"; +- power-domains = <&sps S500_PD_CPU2>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0x3>; +- enable-method = "actions,s500-smp"; +- power-domains = <&sps S500_PD_CPU3>; +- }; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- hosc: hosc { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- #clock-cells = <0>; +- }; +- +- losc: losc { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- scu: scu@b0020000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0xb0020000 0x100>; +- }; +- +- global_timer: timer@b0020200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0xb0020200 0x100>; +- interrupts = ; +- status = "disabled"; +- }; +- +- twd_timer: timer@b0020600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0xb0020600 0x20>; +- interrupts = ; +- status = "disabled"; +- }; +- +- twd_wdt: wdt@b0020620 { +- compatible = "arm,cortex-a9-twd-wdt"; +- reg = <0xb0020620 0xe0>; +- interrupts = ; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@b0021000 { +- compatible = "arm,cortex-a9-gic"; +- reg = <0xb0021000 0x1000>, +- <0xb0020100 0x0100>; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- +- l2: cache-controller@b0022000 { +- compatible = "arm,pl310-cache"; +- reg = <0xb0022000 0x1000>; +- cache-unified; +- cache-level = <2>; +- interrupts = ; +- arm,tag-latency = <3 3 2>; +- arm,data-latency = <5 3 3>; +- }; +- +- uart0: serial@b0120000 { +- compatible = "actions,s500-uart", "actions,owl-uart"; +- reg = <0xb0120000 0x2000>; +- interrupts = ; +- clocks = <&cmu CLK_UART0>; +- status = "disabled"; +- }; +- +- uart1: serial@b0122000 { +- compatible = "actions,s500-uart", "actions,owl-uart"; +- reg = <0xb0122000 0x2000>; +- interrupts = ; +- clocks = <&cmu CLK_UART1>; +- status = "disabled"; +- }; +- +- uart2: serial@b0124000 { +- compatible = "actions,s500-uart", "actions,owl-uart"; +- reg = <0xb0124000 0x2000>; +- interrupts = ; +- clocks = <&cmu CLK_UART2>; +- status = "disabled"; +- }; +- +- uart3: serial@b0126000 { +- compatible = "actions,s500-uart", "actions,owl-uart"; +- reg = <0xb0126000 0x2000>; +- interrupts = ; +- clocks = <&cmu CLK_UART3>; +- status = "disabled"; +- }; +- +- uart4: serial@b0128000 { +- compatible = "actions,s500-uart", "actions,owl-uart"; +- reg = <0xb0128000 0x2000>; +- interrupts = ; +- clocks = <&cmu CLK_UART4>; +- status = "disabled"; +- }; +- +- uart5: serial@b012a000 { +- compatible = "actions,s500-uart", "actions,owl-uart"; +- reg = <0xb012a000 0x2000>; +- interrupts = ; +- clocks = <&cmu CLK_UART5>; +- status = "disabled"; +- }; +- +- uart6: serial@b012c000 { +- compatible = "actions,s500-uart", "actions,owl-uart"; +- reg = <0xb012c000 0x2000>; +- interrupts = ; +- clocks = <&cmu CLK_UART6>; +- status = "disabled"; +- }; +- +- cmu: clock-controller@b0160000 { +- compatible = "actions,s500-cmu"; +- reg = <0xb0160000 0x8000>; +- clocks = <&hosc>, <&losc>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- i2c0: i2c@b0170000 { +- compatible = "actions,s500-i2c"; +- reg = <0xb0170000 0x4000>; +- clocks = <&cmu CLK_I2C0>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@b0174000 { +- compatible = "actions,s500-i2c"; +- reg = <0xb0174000 0x4000>; +- clocks = <&cmu CLK_I2C1>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@b0178000 { +- compatible = "actions,s500-i2c"; +- reg = <0xb0178000 0x4000>; +- clocks = <&cmu CLK_I2C2>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@b017c000 { +- compatible = "actions,s500-i2c"; +- reg = <0xb017c000 0x4000>; +- clocks = <&cmu CLK_I2C3>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- sirq: interrupt-controller@b01b0200 { +- compatible = "actions,s500-sirq"; +- reg = <0xb01b0200 0x4>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = , /* SIRQ0 */ +- , /* SIRQ1 */ +- ; /* SIRQ2 */ +- }; +- +- timer: timer@b0168000 { +- compatible = "actions,s500-timer"; +- reg = <0xb0168000 0x8000>; +- interrupts = , +- , +- , +- ; +- interrupt-names = "2hz0", "2hz1", "timer0", "timer1"; +- }; +- +- sps: power-controller@b01b0100 { +- compatible = "actions,s500-sps"; +- reg = <0xb01b0100 0x100>; +- #power-domain-cells = <1>; +- }; +- +- pinctrl: pinctrl@b01b0000 { +- compatible = "actions,s500-pinctrl"; +- reg = <0xb01b0000 0x40>, /* GPIO */ +- <0xb01b0040 0x10>, /* Multiplexing Control */ +- <0xb01b0060 0x18>, /* PAD Control */ +- <0xb01b0080 0xc>; /* PAD Drive Capacity */ +- clocks = <&cmu CLK_GPIO>; +- gpio-controller; +- gpio-ranges = <&pinctrl 0 0 132>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = , /* GPIOA */ +- , /* GPIOB */ +- , /* GPIOC */ +- , /* GPIOD */ +- ; /* GPIOE */ +- }; +- +- dma: dma-controller@b0260000 { +- compatible = "actions,s500-dma"; +- reg = <0xb0260000 0xd00>; +- interrupts = , +- , +- , +- ; +- #dma-cells = <1>; +- dma-channels = <12>; +- dma-requests = <46>; +- clocks = <&cmu CLK_DMAC>; +- power-domains = <&sps S500_PD_DMA>; +- }; +- +- mmc0: mmc@b0230000 { +- compatible = "actions,s500-mmc", "actions,owl-mmc"; +- reg = <0xb0230000 0x38>; +- interrupts = ; +- clocks = <&cmu CLK_SD0>; +- resets = <&cmu RESET_SD0>; +- dmas = <&dma 2>; +- dma-names = "mmc"; +- status = "disabled"; +- }; +- +- mmc1: mmc@b0234000 { +- compatible = "actions,s500-mmc", "actions,owl-mmc"; +- reg = <0xb0234000 0x38>; +- interrupts = ; +- clocks = <&cmu CLK_SD1>; +- resets = <&cmu RESET_SD1>; +- dmas = <&dma 3>; +- dma-names = "mmc"; +- status = "disabled"; +- }; +- +- mmc2: mmc@b0238000 { +- compatible = "actions,s500-mmc", "actions,owl-mmc"; +- reg = <0xb0238000 0x38>; +- interrupts = ; +- clocks = <&cmu CLK_SD2>; +- resets = <&cmu RESET_SD2>; +- dmas = <&dma 4>; +- dma-names = "mmc"; +- status = "disabled"; +- }; +- +- ethernet: ethernet@b0310000 { +- compatible = "actions,s500-emac", "actions,owl-emac"; +- reg = <0xb0310000 0x10000>; +- interrupts = ; +- clocks = <&cmu CLK_ETHERNET>, <&cmu CLK_RMII_REF>; +- clock-names = "eth", "rmii"; +- resets = <&cmu RESET_ETHERNET>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ox810se-wd-mbwe.dts b/scripts/dtc/include-prefixes/arm/ox810se-wd-mbwe.dts +deleted file mode 100644 +index 7e2fcb220aea..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ox810se-wd-mbwe.dts ++++ /dev/null +@@ -1,111 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * wd-mbwe.dtsi - Device tree file for Western Digital My Book World Edition +- * +- * Copyright (C) 2016 Neil Armstrong +- */ +- +-/dts-v1/; +-#include "ox810se.dtsi" +- +-/ { +- model = "Western Digital My Book World Edition"; +- +- compatible = "wd,mbwe", "oxsemi,ox810se"; +- +- chosen { +- bootargs = "console=ttyS1,115200n8 earlyprintk=serial"; +- }; +- +- memory { +- /* 128Mbytes DDR */ +- reg = <0x48000000 0x8000000>; +- }; +- +- aliases { +- serial1 = &uart1; +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- #address-cells = <1>; +- #size-cells = <0>; +- poll-interval = <100>; +- +- power { +- label = "power"; +- gpios = <&gpio0 0 1>; +- linux,code = <0x198>; +- }; +- +- recovery { +- label = "recovery"; +- gpios = <&gpio0 4 1>; +- linux,code = <0xab>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- a0 { +- label = "activity0"; +- gpios = <&gpio0 25 0>; +- default-state = "keep"; +- }; +- +- a1 { +- label = "activity1"; +- gpios = <&gpio0 26 0>; +- default-state = "keep"; +- }; +- +- a2 { +- label = "activity2"; +- gpios = <&gpio0 5 0>; +- default-state = "keep"; +- }; +- +- a3 { +- label = "activity3"; +- gpios = <&gpio0 6 0>; +- default-state = "keep"; +- }; +- +- a4 { +- label = "activity4"; +- gpios = <&gpio0 7 0>; +- default-state = "keep"; +- }; +- +- a5 { +- label = "activity5"; +- gpios = <&gpio1 2 0>; +- default-state = "keep"; +- }; +- }; +- +- i2c-gpio { +- compatible = "i2c-gpio"; +- gpios = <&gpio0 3 0 /* sda */ +- &gpio0 2 0 /* scl */ +- >; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtc0: rtc@48 { +- compatible = "st,m41t00"; +- reg = <0x68>; +- }; +- }; +-}; +- +-&uart1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ox810se.dtsi b/scripts/dtc/include-prefixes/arm/ox810se.dtsi +deleted file mode 100644 +index 0755e5864c4a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ox810se.dtsi ++++ /dev/null +@@ -1,339 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC +- * +- * Copyright (C) 2016 Neil Armstrong +- */ +- +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "oxsemi,ox810se"; +- +- cpus { +- #address-cells = <0>; +- #size-cells = <0>; +- +- cpu { +- device_type = "cpu"; +- compatible = "arm,arm926ej-s"; +- clocks = <&armclk>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- /* Max 256MB @ 0x48000000 */ +- reg = <0x48000000 0x10000000>; +- }; +- +- clocks { +- osc: oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- gmacclk: gmacclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- }; +- +- rpsclk: rpsclk { +- compatible = "fixed-factor-clock"; +- #clock-cells = <0>; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&osc>; +- }; +- +- pll400: pll400 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <733333333>; +- }; +- +- sysclk: sysclk { +- compatible = "fixed-factor-clock"; +- #clock-cells = <0>; +- clock-div = <4>; +- clock-mult = <1>; +- clocks = <&pll400>; +- }; +- +- armclk: armclk { +- compatible = "fixed-factor-clock"; +- #clock-cells = <0>; +- clock-div = <2>; +- clock-mult = <1>; +- clocks = <&pll400>; +- }; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges; +- interrupt-parent = <&intc>; +- +- apb-bridge@44000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0 0x44000000 0x1000000>; +- +- pinctrl: pinctrl { +- compatible = "oxsemi,ox810se-pinctrl"; +- +- /* Regmap for sys registers */ +- oxsemi,sys-ctrl = <&sys>; +- +- pinctrl_uart0: uart0 { +- uart0a { +- pins = "gpio31"; +- function = "fct3"; +- }; +- uart0b { +- pins = "gpio32"; +- function = "fct3"; +- }; +- }; +- +- pinctrl_uart0_modem: uart0_modem { +- uart0c { +- pins = "gpio27"; +- function = "fct3"; +- }; +- uart0d { +- pins = "gpio28"; +- function = "fct3"; +- }; +- uart0e { +- pins = "gpio29"; +- function = "fct3"; +- }; +- uart0f { +- pins = "gpio30"; +- function = "fct3"; +- }; +- uart0g { +- pins = "gpio33"; +- function = "fct3"; +- }; +- uart0h { +- pins = "gpio34"; +- function = "fct3"; +- }; +- }; +- +- pinctrl_uart1: uart1 { +- uart1a { +- pins = "gpio20"; +- function = "fct3"; +- }; +- uart1b { +- pins = "gpio22"; +- function = "fct3"; +- }; +- }; +- +- pinctrl_uart1_modem: uart1_modem { +- uart1c { +- pins = "gpio8"; +- function = "fct3"; +- }; +- uart1d { +- pins = "gpio9"; +- function = "fct3"; +- }; +- uart1e { +- pins = "gpio23"; +- function = "fct3"; +- }; +- uart1f { +- pins = "gpio24"; +- function = "fct3"; +- }; +- uart1g { +- pins = "gpio25"; +- function = "fct3"; +- }; +- uart1h { +- pins = "gpio26"; +- function = "fct3"; +- }; +- }; +- +- pinctrl_uart2: uart2 { +- uart2a { +- pins = "gpio6"; +- function = "fct3"; +- }; +- uart2b { +- pins = "gpio7"; +- function = "fct3"; +- }; +- }; +- +- pinctrl_uart2_modem: uart2_modem { +- uart2c { +- pins = "gpio0"; +- function = "fct3"; +- }; +- uart2d { +- pins = "gpio1"; +- function = "fct3"; +- }; +- uart2e { +- pins = "gpio2"; +- function = "fct3"; +- }; +- uart2f { +- pins = "gpio3"; +- function = "fct3"; +- }; +- uart2g { +- pins = "gpio4"; +- function = "fct3"; +- }; +- uart2h { +- pins = "gpio5"; +- function = "fct3"; +- }; +- }; +- }; +- +- gpio0: gpio@0 { +- compatible = "oxsemi,ox810se-gpio"; +- reg = <0x000000 0x100000>; +- interrupts = <21>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- ngpios = <32>; +- oxsemi,gpio-bank = <0>; +- gpio-ranges = <&pinctrl 0 0 32>; +- }; +- +- gpio1: gpio@100000 { +- compatible = "oxsemi,ox810se-gpio"; +- reg = <0x100000 0x100000>; +- interrupts = <22>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- ngpios = <3>; +- oxsemi,gpio-bank = <1>; +- gpio-ranges = <&pinctrl 0 32 3>; +- }; +- +- uart0: serial@200000 { +- compatible = "ns16550a"; +- reg = <0x200000 0x100000>; +- clocks = <&sysclk>; +- interrupts = <23>; +- reg-shift = <0>; +- fifo-size = <16>; +- reg-io-width = <1>; +- current-speed = <115200>; +- no-loopback-test; +- status = "disabled"; +- resets = <&reset RESET_UART1>; +- }; +- +- uart1: serial@300000 { +- compatible = "ns16550a"; +- reg = <0x300000 0x100000>; +- clocks = <&sysclk>; +- interrupts = <24>; +- reg-shift = <0>; +- fifo-size = <16>; +- reg-io-width = <1>; +- current-speed = <115200>; +- no-loopback-test; +- status = "disabled"; +- resets = <&reset RESET_UART2>; +- }; +- +- uart2: serial@900000 { +- compatible = "ns16550a"; +- reg = <0x900000 0x100000>; +- clocks = <&sysclk>; +- interrupts = <29>; +- reg-shift = <0>; +- fifo-size = <16>; +- reg-io-width = <1>; +- current-speed = <115200>; +- no-loopback-test; +- status = "disabled"; +- resets = <&reset RESET_UART3>; +- }; +- +- uart3: serial@a00000 { +- compatible = "ns16550a"; +- reg = <0xa00000 0x100000>; +- clocks = <&sysclk>; +- interrupts = <30>; +- reg-shift = <0>; +- fifo-size = <16>; +- reg-io-width = <1>; +- current-speed = <115200>; +- no-loopback-test; +- status = "disabled"; +- resets = <&reset RESET_UART4>; +- }; +- }; +- +- apb-bridge@45000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0 0x45000000 0x1000000>; +- +- sys: sys-ctrl@0 { +- compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; +- reg = <0x000000 0x100000>; +- +- reset: reset-controller { +- compatible = "oxsemi,ox810se-reset"; +- #reset-cells = <1>; +- }; +- +- stdclk: stdclk { +- compatible = "oxsemi,ox810se-stdclk"; +- #clock-cells = <1>; +- }; +- }; +- +- rps@300000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0 0x300000 0x100000>; +- +- intc: interrupt-controller@0 { +- compatible = "oxsemi,ox810se-rps-irq"; +- interrupt-controller; +- reg = <0 0x200>; +- #interrupt-cells = <1>; +- valid-mask = <0xffffffff>; +- clear-mask = <0xffffffff>; +- }; +- +- timer0: timer@200 { +- compatible = "oxsemi,ox810se-rps-timer"; +- reg = <0x200 0x40>; +- clocks = <&rpsclk>; +- interrupts = <4 5>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ox820-cloudengines-pogoplug-series-3.dts b/scripts/dtc/include-prefixes/arm/ox820-cloudengines-pogoplug-series-3.dts +deleted file mode 100644 +index c3daceccde55..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ox820-cloudengines-pogoplug-series-3.dts ++++ /dev/null +@@ -1,93 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3 +- * +- * Copyright (C) 2016 Neil Armstrong +- */ +- +-/dts-v1/; +-#include "ox820.dtsi" +- +-/ { +- model = "Cloud Engines PogoPlug Series 3"; +- +- compatible = "cloudengines,pogoplugv3", "oxsemi,ox820"; +- +- chosen { +- bootargs = "earlyprintk"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- /* 128Mbytes DDR */ +- reg = <0x60000000 0x8000000>; +- }; +- +- aliases { +- serial0 = &uart0; +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- blue { +- label = "pogoplug:blue"; +- gpios = <&gpio0 2 0>; +- default-state = "keep"; +- }; +- +- orange { +- label = "pogoplug:orange"; +- gpios = <&gpio1 16 1>; +- default-state = "keep"; +- }; +- +- green { +- label = "pogoplug:green"; +- gpios = <&gpio1 17 1>; +- default-state = "keep"; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +-}; +- +-&nandc { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nand>; +- +- nand@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- nand-ecc-mode = "soft"; +- nand-ecc-algo = "hamming"; +- +- partition@0 { +- label = "boot"; +- reg = <0x00000000 0x00e00000>; +- read-only; +- }; +- +- partition@e00000 { +- label = "ubi"; +- reg = <0x00e00000 0x07200000>; +- }; +- }; +-}; +- +-ða { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_etha_mdio>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ox820.dtsi b/scripts/dtc/include-prefixes/arm/ox820.dtsi +deleted file mode 100644 +index 90846a7655b4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ox820.dtsi ++++ /dev/null +@@ -1,299 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC +- * +- * Copyright (C) 2016 Neil Armstrong +- */ +- +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "oxsemi,ox820"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "oxsemi,ox820-smp"; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,arm11mpcore"; +- clocks = <&armclk>; +- reg = <0>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,arm11mpcore"; +- clocks = <&armclk>; +- reg = <1>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- /* Max 512MB @ 0x60000000 */ +- reg = <0x60000000 0x20000000>; +- }; +- +- clocks { +- osc: oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- gmacclk: gmacclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- }; +- +- sysclk: sysclk { +- compatible = "fixed-factor-clock"; +- #clock-cells = <0>; +- clock-div = <4>; +- clock-mult = <1>; +- clocks = <&osc>; +- }; +- +- plla: plla { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <850000000>; +- }; +- +- armclk: armclk { +- compatible = "fixed-factor-clock"; +- #clock-cells = <0>; +- clock-div = <2>; +- clock-mult = <1>; +- clocks = <&plla>; +- }; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges; +- interrupt-parent = <&gic>; +- +- nandc: nand-controller@41000000 { +- compatible = "oxsemi,ox820-nand"; +- reg = <0x41000000 0x100000>; +- clocks = <&stdclk CLK_820_NAND>; +- resets = <&reset RESET_NAND>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- etha: ethernet@40400000 { +- compatible = "oxsemi,ox820-dwmac", "snps,dwmac"; +- reg = <0x40400000 0x2000>; +- interrupts = , +- ; +- interrupt-names = "macirq", "eth_wake_irq"; +- mac-address = [000000000000]; /* Filled in by U-Boot */ +- phy-mode = "rgmii"; +- +- clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>; +- clock-names = "gmac", "stmmaceth"; +- resets = <&reset RESET_MAC>; +- +- /* Regmap for sys registers */ +- oxsemi,sys-ctrl = <&sys>; +- +- status = "disabled"; +- }; +- +- apb-bridge@44000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0 0x44000000 0x1000000>; +- +- pinctrl: pinctrl { +- compatible = "oxsemi,ox820-pinctrl"; +- +- /* Regmap for sys registers */ +- oxsemi,sys-ctrl = <&sys>; +- +- pinctrl_uart0: uart0 { +- uart0 { +- pins = "gpio30", "gpio31"; +- function = "fct5"; +- }; +- }; +- +- pinctrl_uart0_modem: uart0_modem { +- uart0_modem_a { +- pins = "gpio24", "gpio24", "gpio26", "gpio27"; +- function = "fct4"; +- }; +- uart0_modem_b { +- pins = "gpio28", "gpio29"; +- function = "fct5"; +- }; +- }; +- +- pinctrl_uart1: uart1 { +- uart1 { +- pins = "gpio7", "gpio8"; +- function = "fct4"; +- }; +- }; +- +- pinctrl_uart1_modem: uart1_modem { +- uart1_modem { +- pins = "gpio5", "gpio6", "gpio40", "gpio41", "gpio42", "gpio43"; +- function = "fct4"; +- }; +- }; +- +- pinctrl_etha_mdio: etha_mdio { +- etha_mdio { +- pins = "gpio3", "gpio4"; +- function = "fct1"; +- }; +- }; +- +- pinctrl_nand: nand { +- nand { +- pins = "gpio12", "gpio13", "gpio14", "gpio15", +- "gpio16", "gpio17", "gpio18", "gpio19", +- "gpio20", "gpio21", "gpio22", "gpio23", +- "gpio24"; +- function = "fct1"; +- }; +- }; +- }; +- +- gpio0: gpio@0 { +- compatible = "oxsemi,ox820-gpio"; +- reg = <0x000000 0x100000>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- ngpios = <32>; +- oxsemi,gpio-bank = <0>; +- gpio-ranges = <&pinctrl 0 0 32>; +- }; +- +- gpio1: gpio@100000 { +- compatible = "oxsemi,ox820-gpio"; +- reg = <0x100000 0x100000>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- ngpios = <18>; +- oxsemi,gpio-bank = <1>; +- gpio-ranges = <&pinctrl 0 32 18>; +- }; +- +- uart0: serial@200000 { +- compatible = "ns16550a"; +- reg = <0x200000 0x100000>; +- interrupts = ; +- reg-shift = <0>; +- fifo-size = <16>; +- reg-io-width = <1>; +- current-speed = <115200>; +- no-loopback-test; +- status = "disabled"; +- clocks = <&sysclk>; +- resets = <&reset RESET_UART1>; +- }; +- +- uart1: serial@300000 { +- compatible = "ns16550a"; +- reg = <0x200000 0x100000>; +- interrupts = ; +- reg-shift = <0>; +- fifo-size = <16>; +- reg-io-width = <1>; +- current-speed = <115200>; +- no-loopback-test; +- status = "disabled"; +- clocks = <&sysclk>; +- resets = <&reset RESET_UART2>; +- }; +- +- rps@400000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0 0x400000 0x100000>; +- +- intc: interrupt-controller@0 { +- compatible = "oxsemi,ox820-rps-irq", "oxsemi,ox810se-rps-irq"; +- interrupt-controller; +- reg = <0 0x200>; +- interrupts = ; +- #interrupt-cells = <1>; +- valid-mask = <0xffffffff>; +- clear-mask = <0xffffffff>; +- }; +- +- timer0: timer@200 { +- compatible = "oxsemi,ox820-rps-timer"; +- reg = <0x200 0x40>; +- clocks = <&sysclk>; +- interrupt-parent = <&intc>; +- interrupts = <4>; +- }; +- }; +- +- sys: sys-ctrl@e00000 { +- compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"; +- reg = <0xe00000 0x200000>; +- +- reset: reset-controller { +- compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset"; +- #reset-cells = <1>; +- }; +- +- stdclk: stdclk { +- compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk"; +- #clock-cells = <1>; +- }; +- }; +- }; +- +- apb-bridge@47000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0 0x47000000 0x1000000>; +- +- scu: scu@0 { +- compatible = "arm,arm11mp-scu"; +- reg = <0x0 0x100>; +- }; +- +- local-timer@600 { +- compatible = "arm,arm11mp-twd-timer"; +- reg = <0x600 0x20>; +- interrupts = ; +- clocks = <&armclk>; +- }; +- +- gic: gic@1000 { +- compatible = "arm,arm11mp-gic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x1000 0x1000>, +- <0x100 0x500>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/pm9g45.dts b/scripts/dtc/include-prefixes/arm/pm9g45.dts +deleted file mode 100644 +index c349fd3758a6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/pm9g45.dts ++++ /dev/null +@@ -1,185 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * pm9g45.dts - Device Tree file for Ronetix pm9g45 board +- * +- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +-/dts-v1/; +-#include "at91sam9g45.dtsi" +- +-/ { +- model = "Ronetix pm9g45"; +- compatible = "ronetix,pm9g45", "atmel,at91sam9g45", "atmel,at91sam9"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- }; +- +- memory@70000000 { +- reg = <0x70000000 0x8000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- ahb { +- apb { +- dbgu: serial@ffffee00 { +- status = "okay"; +- }; +- +- pinctrl@fffff200 { +- nand { +- pinctrl_nand_rb: nand-rb-0 { +- atmel,pins = +- ; +- }; +- }; +- +- mmc { +- pinctrl_board_mmc: mmc0-board { +- atmel,pins = +- ; /* PD6 gpio CD pin pull_up and deglitch */ +- }; +- }; +- }; +- +- tcb0: timer@fff7c000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +- }; +- +- mmc0: mmc@fff80000 { +- pinctrl-0 = < +- &pinctrl_board_mmc +- &pinctrl_mmc0_slot0_clk_cmd_dat0 +- &pinctrl_mmc0_slot0_dat1_3>; +- pinctrl-names = "default"; +- status = "okay"; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioD 6 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- macb0: ethernet@fffbc000 { +- phy-mode = "rmii"; +- status = "okay"; +- }; +- }; +- +- ebi: ebi@10000000 { +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; +- pinctrl-names = "default"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioD 3 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "soft"; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x20000>; +- }; +- +- barebox@20000 { +- label = "barebox"; +- reg = <0x20000 0x40000>; +- }; +- +- bareboxenv@60000 { +- label = "bareboxenv"; +- reg = <0x60000 0x1A0000>; +- }; +- +- kernel@200000 { +- label = "bareboxenv2"; +- reg = <0x200000 0x300000>; +- }; +- +- kernel@500000 { +- label = "root"; +- reg = <0x500000 0x400000>; +- }; +- +- data@900000 { +- label = "data"; +- reg = <0x900000 0x8340000>; +- }; +- }; +- }; +- }; +- }; +- +- usb0: ohci@700000 { +- status = "okay"; +- num-ports = <2>; +- }; +- +- usb1: ehci@800000 { +- status = "okay"; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led0 { +- label = "led0"; +- gpios = <&pioD 0 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "nand-disk"; +- }; +- +- led1 { +- label = "led1"; +- gpios = <&pioD 31 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- right { +- label = "SW4"; +- gpios = <&pioE 7 GPIO_ACTIVE_LOW>; +- linux,code = <106>; +- }; +- +- up { +- label = "SW3"; +- gpios = <&pioE 8 GPIO_ACTIVE_LOW>; +- linux,code = <103>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/pxa168-aspenite.dts b/scripts/dtc/include-prefixes/arm/pxa168-aspenite.dts +deleted file mode 100644 +index 8bade6bf395b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/pxa168-aspenite.dts ++++ /dev/null +@@ -1,33 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Marvell Technology Group Ltd. +- * Author: Haojian Zhuang +- */ +- +-/dts-v1/; +-#include "pxa168.dtsi" +- +-/ { +- model = "Marvell PXA168 Aspenite Development Board"; +- compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168"; +- +- chosen { +- bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; +- }; +- +- memory { +- reg = <0x00000000 0x04000000>; +- }; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&twsi1 { +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/pxa168.dtsi b/scripts/dtc/include-prefixes/arm/pxa168.dtsi +deleted file mode 100644 +index 4fe7735c7c58..000000000000 +--- a/scripts/dtc/include-prefixes/arm/pxa168.dtsi ++++ /dev/null +@@ -1,164 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Marvell Technology Group Ltd. +- * Author: Haojian Zhuang +- */ +- +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- i2c0 = &twsi1; +- i2c1 = &twsi2; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&intc>; +- ranges; +- +- axi@d4200000 { /* AXI */ +- compatible = "mrvl,axi-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xd4200000 0x00200000>; +- ranges; +- +- intc: interrupt-controller@d4282000 { +- compatible = "mrvl,mmp-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0xd4282000 0x1000>; +- mrvl,intc-nr-irqs = <64>; +- }; +- +- }; +- +- apb@d4000000 { /* APB */ +- compatible = "mrvl,apb-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xd4000000 0x00200000>; +- ranges; +- +- timer0: timer@d4014000 { +- compatible = "mrvl,mmp-timer"; +- reg = <0xd4014000 0x100>; +- interrupts = <13>; +- }; +- +- uart1: serial@d4017000 { +- compatible = "mrvl,mmp-uart", "intel,xscale-uart"; +- reg = <0xd4017000 0x1000>; +- reg-shift = <2>; +- interrupts = <27>; +- clocks = <&soc_clocks PXA168_CLK_UART0>; +- resets = <&soc_clocks PXA168_CLK_UART0>; +- status = "disabled"; +- }; +- +- uart2: serial@d4018000 { +- compatible = "mrvl,mmp-uart", "intel,xscale-uart"; +- reg = <0xd4018000 0x1000>; +- reg-shift = <2>; +- interrupts = <28>; +- clocks = <&soc_clocks PXA168_CLK_UART1>; +- resets = <&soc_clocks PXA168_CLK_UART1>; +- status = "disabled"; +- }; +- +- uart3: serial@d4026000 { +- compatible = "mrvl,mmp-uart", "intel,xscale-uart"; +- reg = <0xd4026000 0x1000>; +- reg-shift = <2>; +- interrupts = <29>; +- clocks = <&soc_clocks PXA168_CLK_UART2>; +- resets = <&soc_clocks PXA168_CLK_UART2>; +- status = "disabled"; +- }; +- +- gpio@d4019000 { +- compatible = "marvell,mmp-gpio"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xd4019000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = <49>; +- clocks = <&soc_clocks PXA168_CLK_GPIO>; +- resets = <&soc_clocks PXA168_CLK_GPIO>; +- interrupt-names = "gpio_mux"; +- interrupt-controller; +- #interrupt-cells = <2>; +- ranges; +- +- gcb0: gpio@d4019000 { +- reg = <0xd4019000 0x4>; +- }; +- +- gcb1: gpio@d4019004 { +- reg = <0xd4019004 0x4>; +- }; +- +- gcb2: gpio@d4019008 { +- reg = <0xd4019008 0x4>; +- }; +- +- gcb3: gpio@d4019100 { +- reg = <0xd4019100 0x4>; +- }; +- }; +- +- twsi1: i2c@d4011000 { +- compatible = "mrvl,mmp-twsi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xd4011000 0x1000>; +- interrupts = <7>; +- clocks = <&soc_clocks PXA168_CLK_TWSI0>; +- resets = <&soc_clocks PXA168_CLK_TWSI0>; +- mrvl,i2c-fast-mode; +- status = "disabled"; +- }; +- +- twsi2: i2c@d4025000 { +- compatible = "mrvl,mmp-twsi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xd4025000 0x1000>; +- interrupts = <58>; +- clocks = <&soc_clocks PXA168_CLK_TWSI1>; +- resets = <&soc_clocks PXA168_CLK_TWSI1>; +- status = "disabled"; +- }; +- +- rtc: rtc@d4010000 { +- compatible = "mrvl,mmp-rtc"; +- reg = <0xd4010000 0x1000>; +- interrupts = <5>, <6>; +- interrupt-names = "rtc 1Hz", "rtc alarm"; +- clocks = <&soc_clocks PXA168_CLK_RTC>; +- resets = <&soc_clocks PXA168_CLK_RTC>; +- status = "disabled"; +- }; +- }; +- +- soc_clocks: clocks{ +- compatible = "marvell,pxa168-clock"; +- reg = <0xd4050000 0x1000>, +- <0xd4282800 0x400>, +- <0xd4015000 0x1000>; +- reg-names = "mpmu", "apmu", "apbc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/pxa25x.dtsi b/scripts/dtc/include-prefixes/arm/pxa25x.dtsi +deleted file mode 100644 +index a248bf038033..000000000000 +--- a/scripts/dtc/include-prefixes/arm/pxa25x.dtsi ++++ /dev/null +@@ -1,115 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2016 Robert Jarzmik +- */ +-#include "pxa2xx.dtsi" +-#include "dt-bindings/clock/pxa-clock.h" +- +-/ { +- model = "Marvell PXA25x family SoC"; +- compatible = "marvell,pxa250"; +- +- clocks { +- /* +- * The muxing of external clocks/internal dividers for osc* clock +- * sources has been hidden under the carpet by now. +- */ +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clks: pxa2xx_clks@41300004 { +- compatible = "marvell,pxa250-core-clocks"; +- #clock-cells = <1>; +- status = "okay"; +- }; +- +- /* timer oscillator */ +- clktimer: oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <3686400>; +- clock-output-names = "ostimer"; +- }; +- }; +- +- pxabus { +- pdma: dma-controller@40000000 { +- compatible = "marvell,pdma-1.0"; +- reg = <0x40000000 0x10000>; +- interrupts = <25>; +- #dma-channels = <16>; +- #dma-cells = <2>; +- #dma-requests = <40>; +- status = "okay"; +- }; +- +- pxairq: interrupt-controller@40d00000 { +- marvell,intc-priority; +- marvell,intc-nr-irqs = <32>; +- }; +- +- pinctrl: pinctrl@40e00000 { +- reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4 +- 0x40f00020 0x10>; +- compatible = "marvell,pxa25x-pinctrl"; +- }; +- +- gpio: gpio@40e00000 { +- compatible = "intel,pxa25x-gpio"; +- gpio-ranges = <&pinctrl 0 0 84>; +- clocks = <&clks CLK_NONE>; +- }; +- +- pwm0: pwm@40b00000 { +- compatible = "marvell,pxa250-pwm"; +- reg = <0x40b00000 0x10>; +- #pwm-cells = <1>; +- clocks = <&clks CLK_PWM0>; +- }; +- +- pwm1: pwm@40b00010 { +- compatible = "marvell,pxa250-pwm"; +- reg = <0x40b00010 0x10>; +- #pwm-cells = <1>; +- clocks = <&clks CLK_PWM1>; +- }; +- +- rtc@40900000 { +- clocks = <&clks CLK_OSC32k768>; +- }; +- }; +- +- timer@40a00000 { +- compatible = "marvell,pxa-timer"; +- reg = <0x40a00000 0x20>; +- interrupts = <26>; +- clocks = <&clktimer>; +- status = "okay"; +- }; +- +- pxa250_opp_table: opp_table0 { +- compatible = "operating-points-v2"; +- +- opp-99532800 { +- opp-hz = /bits/ 64 <99532800>; +- opp-microvolt = <1000000 950000 1650000>; +- clock-latency-ns = <20>; +- }; +- opp-199065600 { +- opp-hz = /bits/ 64 <199065600>; +- opp-microvolt = <1000000 950000 1650000>; +- clock-latency-ns = <20>; +- }; +- opp-298598400 { +- opp-hz = /bits/ 64 <298598400>; +- opp-microvolt = <1100000 1045000 1650000>; +- clock-latency-ns = <20>; +- }; +- opp-398131200 { +- opp-hz = /bits/ 64 <398131200>; +- opp-microvolt = <1300000 1235000 1650000>; +- clock-latency-ns = <20>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/pxa27x.dtsi b/scripts/dtc/include-prefixes/arm/pxa27x.dtsi +deleted file mode 100644 +index ccbecad9c5c7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/pxa27x.dtsi ++++ /dev/null +@@ -1,185 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* The pxa3xx skeleton simply augments the 2xx version */ +-#include "pxa2xx.dtsi" +-#include "dt-bindings/clock/pxa-clock.h" +- +-/ { +- model = "Marvell PXA27x familiy SoC"; +- compatible = "marvell,pxa27x"; +- +- pxabus { +- pdma: dma-controller@40000000 { +- compatible = "marvell,pdma-1.0"; +- reg = <0x40000000 0x10000>; +- interrupts = <25>; +- #dma-channels = <32>; +- #dma-cells = <2>; +- #dma-requests = <75>; +- status = "okay"; +- }; +- +- pxairq: interrupt-controller@40d00000 { +- marvell,intc-priority; +- marvell,intc-nr-irqs = <34>; +- }; +- +- pinctrl: pinctrl@40e00000 { +- reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4 +- 0x40f00020 0x10>; +- compatible = "marvell,pxa27x-pinctrl"; +- }; +- +- gpio: gpio@40e00000 { +- compatible = "intel,pxa27x-gpio"; +- gpio-ranges = <&pinctrl 0 0 128>; +- clocks = <&clks CLK_NONE>; +- }; +- +- usb0: usb@4c000000 { +- compatible = "marvell,pxa-ohci"; +- reg = <0x4c000000 0x10000>; +- interrupts = <3>; +- clocks = <&clks CLK_USBHOST>; +- status = "disabled"; +- }; +- +- pwm0: pwm@40b00000 { +- compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; +- reg = <0x40b00000 0x10>; +- #pwm-cells = <1>; +- clocks = <&clks CLK_PWM0>; +- }; +- +- pwm1: pwm@40b00010 { +- compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; +- reg = <0x40b00010 0x10>; +- #pwm-cells = <1>; +- clocks = <&clks CLK_PWM1>; +- }; +- +- pwm2: pwm@40c00000 { +- compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; +- reg = <0x40c00000 0x10>; +- #pwm-cells = <1>; +- clocks = <&clks CLK_PWM0>; +- }; +- +- pwm3: pwm@40c00010 { +- compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; +- reg = <0x40c00010 0x10>; +- #pwm-cells = <1>; +- clocks = <&clks CLK_PWM1>; +- }; +- +- pwri2c: i2c@40f00180 { +- compatible = "mrvl,pxa-i2c"; +- reg = <0x40f00180 0x24>; +- interrupts = <6>; +- clocks = <&clks CLK_PWRI2C>; +- #address-cells = <0x1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pxa27x_udc: udc@40600000 { +- compatible = "marvell,pxa270-udc"; +- reg = <0x40600000 0x10000>; +- interrupts = <11>; +- clocks = <&clks CLK_USB>; +- status = "disabled"; +- }; +- +- keypad: keypad@41500000 { +- compatible = "marvell,pxa27x-keypad"; +- reg = <0x41500000 0x4c>; +- interrupts = <4>; +- clocks = <&clks CLK_KEYPAD>; +- status = "disabled"; +- }; +- +- pxa_camera: imaging@50000000 { +- compatible = "marvell,pxa270-qci"; +- reg = <0x50000000 0x1000>; +- interrupts = <33>; +- dmas = <&pdma 68 0 /* Y channel */ +- &pdma 69 0 /* U channel */ +- &pdma 70 0>; /* V channel */ +- dma-names = "CI_Y", "CI_U", "CI_V"; +- +- clocks = <&clks CLK_CAMERA>; +- clock-names = "ciclk"; +- clock-frequency = <5000000>; +- clock-output-names = "qci_mclk"; +- +- status = "disabled"; +- }; +- +- rtc@40900000 { +- clocks = <&clks CLK_OSC32k768>; +- }; +- }; +- +- clocks { +- /* +- * The muxing of external clocks/internal dividers for osc* clock +- * sources has been hidden under the carpet by now. +- */ +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clks: pxa2xx_clks@41300004 { +- compatible = "marvell,pxa270-clocks"; +- #clock-cells = <1>; +- status = "okay"; +- }; +- }; +- +- timer@40a00000 { +- compatible = "marvell,pxa-timer"; +- reg = <0x40a00000 0x20>; +- interrupts = <26>; +- clocks = <&clks CLK_OSTIMER>; +- status = "okay"; +- }; +- +- pxa270_opp_table: opp_table0 { +- compatible = "operating-points-v2"; +- +- opp-104000000 { +- opp-hz = /bits/ 64 <104000000>; +- opp-microvolt = <900000 900000 1705000>; +- clock-latency-ns = <20>; +- }; +- opp-156000000 { +- opp-hz = /bits/ 64 <156000000>; +- opp-microvolt = <1000000 1000000 1705000>; +- clock-latency-ns = <20>; +- }; +- opp-208000000 { +- opp-hz = /bits/ 64 <208000000>; +- opp-microvolt = <1180000 1180000 1705000>; +- clock-latency-ns = <20>; +- }; +- opp-312000000 { +- opp-hz = /bits/ 64 <312000000>; +- opp-microvolt = <1250000 1250000 1705000>; +- clock-latency-ns = <20>; +- }; +- opp-416000000 { +- opp-hz = /bits/ 64 <416000000>; +- opp-microvolt = <1350000 1350000 1705000>; +- clock-latency-ns = <20>; +- }; +- opp-520000000 { +- opp-hz = /bits/ 64 <520000000>; +- opp-microvolt = <1450000 1450000 1705000>; +- clock-latency-ns = <20>; +- }; +- opp-624000000 { +- opp-hz = /bits/ 64 <624000000>; +- opp-microvolt = <1550000 1550000 1705000>; +- clock-latency-ns = <20>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/pxa2xx.dtsi b/scripts/dtc/include-prefixes/arm/pxa2xx.dtsi +deleted file mode 100644 +index 84154c43fe65..000000000000 +--- a/scripts/dtc/include-prefixes/arm/pxa2xx.dtsi ++++ /dev/null +@@ -1,162 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC +- * +- * Copyright (C) 2011 Marek Vasut +- */ +- +-#include "dt-bindings/clock/pxa-clock.h" +- +-#define PMGROUP(pin) #pin +-#define PMMUX(func, pin, af) \ +- mux- ## func { \ +- groups = PMGROUP(P ## pin); \ +- function = #af; \ +- } +-#define PMMUX_LPM_LOW(func, pin, af) \ +- mux- ## func { \ +- groups = PMGROUP(P ## pin); \ +- function = #af; \ +- low-power-disable; \ +- } +-#define PMMUX_LPM_HIGH(func, pin, af) \ +- mux- ## func { \ +- groups = PMGROUP(P ## pin); \ +- function = #af; \ +- low-power-enable; \ +- } +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Marvell PXA2xx family SoC"; +- compatible = "marvell,pxa2xx"; +- interrupt-parent = <&pxairq>; +- +- aliases { +- serial0 = &ffuart; +- serial1 = &btuart; +- serial2 = &stuart; +- serial3 = &hwuart; +- i2c0 = &pwri2c; +- i2c1 = &pxai2c1; +- }; +- +- cpus { +- cpu { +- compatible = "marvell,xscale"; +- device_type = "cpu"; +- }; +- }; +- +- pxabus { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- pxairq: interrupt-controller@40d00000 { +- #interrupt-cells = <1>; +- compatible = "marvell,pxa-intc"; +- interrupt-controller; +- interrupt-parent; +- marvell,intc-nr-irqs = <32>; +- reg = <0x40d00000 0xd0>; +- }; +- +- gpio: gpio@40e00000 { +- compatible = "mrvl,pxa-gpio"; +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- reg = <0x40e00000 0x10000>; +- gpio-controller; +- #gpio-cells = <0x2>; +- interrupts = <8>, <9>, <10>; +- interrupt-names = "gpio0", "gpio1", "gpio_mux"; +- interrupt-controller; +- #interrupt-cells = <0x2>; +- ranges; +- +- gcb0: gpio@40e00000 { +- reg = <0x40e00000 0x4>; +- }; +- +- gcb1: gpio@40e00004 { +- reg = <0x40e00004 0x4>; +- }; +- +- gcb2: gpio@40e00008 { +- reg = <0x40e00008 0x4>; +- }; +- gcb3: gpio@40e0000c { +- reg = <0x40e0000c 0x4>; +- }; +- }; +- +- ffuart: serial@40100000 { +- compatible = "mrvl,pxa-uart"; +- reg = <0x40100000 0x30>; +- interrupts = <22>; +- clocks = <&clks CLK_FFUART>; +- status = "disabled"; +- }; +- +- btuart: serial@40200000 { +- compatible = "mrvl,pxa-uart"; +- reg = <0x40200000 0x30>; +- interrupts = <21>; +- clocks = <&clks CLK_BTUART>; +- status = "disabled"; +- }; +- +- stuart: serial@40700000 { +- compatible = "mrvl,pxa-uart"; +- reg = <0x40700000 0x30>; +- interrupts = <20>; +- clocks = <&clks CLK_STUART>; +- status = "disabled"; +- }; +- +- hwuart: serial@41600000 { +- compatible = "mrvl,pxa-uart"; +- reg = <0x41600000 0x30>; +- interrupts = <7>; +- status = "disabled"; +- }; +- +- pxai2c1: i2c@40301680 { +- compatible = "mrvl,pxa-i2c"; +- reg = <0x40301680 0x30>; +- interrupts = <18>; +- clocks = <&clks CLK_I2C>; +- #address-cells = <0x1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- mmc0: mmc@41100000 { +- compatible = "marvell,pxa-mmc"; +- reg = <0x41100000 0x1000>; +- interrupts = <23>; +- clocks = <&clks CLK_MMC>; +- dmas = <&pdma 21 3 +- &pdma 22 3>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- rtc@40900000 { +- compatible = "marvell,pxa-rtc"; +- reg = <0x40900000 0x3c>; +- interrupts = <30 31>; +- }; +- +- lcdc: lcd-controller@40500000 { +- compatible = "marvell,pxa2xx-lcdc"; +- reg = <0x44000000 0x10000>; +- interrupts = <17>; +- clocks = <&clks CLK_LCD>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-common.dtsi b/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-common.dtsi +deleted file mode 100644 +index 8a6721d436bd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-common.dtsi ++++ /dev/null +@@ -1,405 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include "pxa3xx.dtsi" +-#include +-#include +-#include +- +-/ { +- /* Will be overridden by bootloader */ +- hw-revision = <0>; +- +- chosen { +- bootargs = "root=ubi0:RootFS rootfstype=ubifs rw ubi.mtd=3"; +- stdout-path = &ffuart; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0xa0000000 0x8000000>; /* 128 MB */ +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3v3-fixed-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_1v8: regulator-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "1v8-fixed-supply"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- reg_va_5v0: regulator-va-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "va-5v0-fixed-supply"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio 124 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- ssp_dai0: ssp-dai0 { +- compatible = "mrvl,pxa-ssp-dai"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ssp0_dai_pins>; +- port = <&ssp1>; +- #sound-dai-cells = <0>; +- dmas = <&pdma 13 3 +- &pdma 14 3>; +- dma-names = "rx", "tx"; +- clock-names = "extclk"; +- }; +- +- ssp_dai1: ssp-dai1 { +- compatible = "mrvl,pxa-ssp-dai"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ssp1_dai_pins>; +- port = <&ssp2>; +- #sound-dai-cells = <0>; +- dmas = <&pdma 15 3 +- &pdma 16 3>; +- dma-names = "rx", "tx"; +- clock-names = "extclk"; +- }; +- +- spi: spi { +- compatible = "spi-gpio"; +- #address-cells = <0x1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_pins>; +- gpio-sck = <&gpio 95 GPIO_ACTIVE_HIGH>; +- gpio-miso = <&gpio 98 GPIO_ACTIVE_HIGH>; +- gpio-mosi = <&gpio 97 GPIO_ACTIVE_HIGH>; +- cs-gpios = < +- &gpio 34 GPIO_ACTIVE_HIGH +- &gpio 125 GPIO_ACTIVE_HIGH +- &gpio 96 GPIO_ACTIVE_HIGH +- >; +- num-chipselects = <3>; +- +- dac: dac@2 { +- compatible = "ti,dac7512"; +- reg = <2>; +- spi-max-frequency = <1000000>; +- vcc-supply = <®_3v3>; +- }; +- }; +- +- keys: gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_pins>; +- +- on-off { +- label = "on_off button"; +- gpios = <&gpio 14 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- rescue-boot { +- label = "rescue boot button"; +- gpios = <&gpio 115 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- }; +- +- setup { +- label = "setup"; +- gpios = <&gpio 119 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- }; +- }; +- +- rotary: rotary-encoder { +- compatible = "rotary-encoder"; +- gpios = < +- &gpio 19 GPIO_ACTIVE_LOW +- &gpio 20 GPIO_ACTIVE_HIGH +- >; +- linux,axis = ; +- rotary-encoder,relative-axis; +- }; +- +- leds: leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins_a &led_pins_b>; +- +- left { +- label = "raumfeld:1"; +- gpios = <&gpio 36 GPIO_ACTIVE_LOW>; +- }; +- +- right { +- label = "raumfeld:2"; +- gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- poweroff { +- compatible = "gpio-poweroff"; +- pinctrl-names = "default"; +- pinctrl-0 = <&poweroff_pins>; +- gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; +- }; +- +- mmc0_pwrseq: mmc-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pwrseq_pins>; +- reset-gpios = < +- &gpio 113 GPIO_ACTIVE_LOW /* W2W_RESET */ +- &gpio 114 GPIO_ACTIVE_LOW /* W2W_PDN */ +- >; +- }; +- +- ethernet: ethernet@10000000 { +- compatible = "smsc,lan9115"; +- pinctrl-names = "default"; +- pinctrl-0 = <&smsc_pins &smsc_bus_pins>; +- reg = <0x10000000 0x100000>; +- phy-mode = "mii"; +- interrupt-parent = <&gpio>; +- interrupts = <40 IRQ_TYPE_EDGE_FALLING>; +- vdd33a-supply = <®_3v3>; +- vddvario-supply = <®_1v8>; +- reset-gpios = <&gpio 39 GPIO_ACTIVE_LOW>; +- reg-io-width = <4>; +- smsc,save-mac-address; +- smsc,irq-push-pull; +- }; +-}; +- +-&ffuart { +- status = "okay"; +-}; +- +-&pwri2c { +- status = "okay"; +- +- max8660: regulator@34 { +- compatible = "maxim,max8660"; +- reg = <0x34>; +- +- regulators { +- regulator-v3 { +- regulator-compatible= "V3(DCDC)"; +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- regulator-v4 { +- regulator-compatible= "V4(DCDC)"; +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- regulator-v5 { +- regulator-compatible= "V5(LDO)"; +- regulator-min-microvolt = <1700000>; +- regulator-max-microvolt = <2000000>; +- }; +- +- reg_vcc_sdio: regulator-v6 { +- regulator-compatible= "V6(LDO)"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- regulator-v7 { +- regulator-compatible= "V7(LDO)"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +- }; +-}; +- +-&pxai2c1 { +- status = "okay"; +- mrvl,i2c-fast-mode; +- pinctrl-names = "default"; +- pinctrl-0 = <&pxai2c1_pins>; +-}; +- +-&ssp1 { +- status = "okay"; +-}; +- +-&ssp2 { +- status = "okay"; +-}; +- +-&nand_controller { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- nand-rb = <0>; +- nand-ecc-mode = "hw"; +- marvell,nand-keep-config; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "Bootloader"; +- reg = <0x0000000 0xa0000>; +- read-only; +- }; +- +- partition@a0000 { +- label = "BootloaderEnvironment"; +- reg = <0x0a0000 0x20000>; +- }; +- +- partition@c0000 { +- label = "BootloaderSplashScreen"; +- reg = <0x0c0000 0x60000>; +- }; +- +- partition@120000 { +- label = "UBI"; +- reg = <0x120000 0x7ee0000>; +- }; +- }; +- }; +-}; +- +-&usb0 { +- status = "okay"; +- marvell,enable-port1; +- marvell,port-mode = <2>; /* PMM_GLOBAL_MODE */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pxa3xx_ohci_pins>; +-}; +- +-&mmc0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- pxa-mmc,detect-delay-ms = <200>; +- vmmc-supply = <®_vcc_sdio>; +- mmc-pwrseq = <&mmc0_pwrseq>; +- non-removable; +- bus-width = <4>; +-}; +- +-&pinctrl { +- poweroff_pins: poweroff-pins { +- pinctrl-single,pins = ; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); +- }; +- +- led_pins_a: led-pins-a { +- pinctrl-single,pins = ; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); +- }; +- +- led_pins_b: led-pins-b { +- pinctrl-single,pins = ; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_DRIVE_HIGH); +- }; +- +- pxai2c1_pins: pxai2c1-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(21) MFP_AF1 /* I2C_SCL */ +- MFP_PIN_PXA300(22) MFP_AF1 /* I2C_SDA */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_HIGH); +- }; +- +- gpio_keys_pins: gpio-keys-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(14) MFP_AF0 /* on-off */ +- MFP_PIN_PXA300(115) MFP_AF0 /* rescue boot */ +- MFP_PIN_PXA300(119) MFP_AF0 /* setup */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); +- }; +- +- spi_pins: spi-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(95) MFP_AF0 /* SCK */ +- MFP_PIN_PXA300(97) MFP_AF0 /* MOSI */ +- MFP_PIN_PXA300(98) MFP_AF0 /* MISO */ +- MFP_PIN_PXA300(34) MFP_AF0 /* CS#0 */ +- MFP_PIN_PXA300(125) MFP_AF0 /* CS#1 */ +- MFP_PIN_PXA300(96) MFP_AF0 /* CS#2 */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); +- }; +- +- pxa3xx_ohci_pins: pxa3xx-ohci-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300_2(0) MFP_AF1 /* USBHPEN */ +- MFP_PIN_PXA300_2(1) MFP_AF1 /* USBHPWR */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); +- }; +- +- smsc_pins: smsc-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(39) MFP_AF0 /* RESET */ +- MFP_PIN_PXA300(40) MFP_AF0 /* IRQ */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); +- }; +- +- smsc_bus_pins: smsc-bus-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(1) MFP_AF1 /* nCS2 */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); +- }; +- +- mmc0_pins: mmc0-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(3) MFP_AF4 /* MMC1_DAT0 */ +- MFP_PIN_PXA300(4) MFP_AF4 /* MMC1_DAT1 */ +- MFP_PIN_PXA300(5) MFP_AF4 /* MMC1_DAT2 */ +- MFP_PIN_PXA300(6) MFP_AF4 /* MMC1_DAT3 */ +- MFP_PIN_PXA300(7) MFP_AF4 /* MMC1_CLK */ +- MFP_PIN_PXA300(8) MFP_AF4 /* MMC1_CMD */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_DRIVE_HIGH); +- }; +- +- mmc0_pwrseq_pins: mmc0-pwrseq-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(113) MFP_AF0 /* W2W_RESET */ +- MFP_PIN_PXA300(114) MFP_AF0 /* W2W_PDN */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); +- }; +- +- ssp0_dai_pins: ssp0-dai-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(85) MFP_AF1 /* SSP1_SCLK */ +- MFP_PIN_PXA300(86) MFP_AF1 /* SSP1_FRM */ +- MFP_PIN_PXA300(87) MFP_AF1 /* SSP1_TXD */ +- MFP_PIN_PXA300(88) MFP_AF1 /* SSP1_RXD */ +- MFP_PIN_PXA300(89) MFP_AF1 /* SSP1_EXTCLK */ +- MFP_PIN_PXA300(90) MFP_AF1 /* SSP1_SYSCLK */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); +- }; +- +- ssp1_dai_pins: ssp1-dai-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(25) MFP_AF2 /* SSP2_SCLK */ +- MFP_PIN_PXA300(26) MFP_AF2 /* SSP2_FRM */ +- MFP_PIN_PXA300(27) MFP_AF2 /* SSP2_TXD */ +- MFP_PIN_PXA300(29) MFP_AF2 /* SSP2_EXTCLK */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-connector.dts b/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-connector.dts +deleted file mode 100644 +index 3e9445419e39..000000000000 +--- a/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-connector.dts ++++ /dev/null +@@ -1,73 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/dts-v1/; +- +-#include "pxa300-raumfeld-common.dtsi" +-#include "pxa300-raumfeld-tuneable-clock.dtsi" +- +-/ { +- model = "Raumfeld Connector (PXA3xx)"; +- compatible = "raumfeld,raumfeld-connector-pxa303", "marvell,pxa300"; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "Raumfeld Connector"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- simple-audio-card,dai-link@0 { +- reg = <0>; +- format = "i2s"; +- bitclock-master = <&dailink_master_analog>; +- frame-master = <&dailink_master_analog>; +- mclk-fs = <256>; +- +- dailink_master_analog: cpu { +- sound-dai = <&ssp_dai0>; +- }; +- +- codec { +- sound-dai = <&cs4270>; +- }; +- }; +- +- simple-audio-card,dai-link@1 { +- reg = <1>; +- format = "i2s"; +- bitclock-master = <&dailink_master_digital>; +- frame-master = <&dailink_master_digital>; +- mclk-fs = <256>; +- +- dailink_master_digital: cpu { +- sound-dai = <&ssp_dai1>; +- }; +- +- codec { +- sound-dai = <&ak4104>; +- }; +- }; +- }; +-}; +- +-&ssp1 { +- status = "okay"; +-}; +- +-&ssp2 { +- status = "okay"; +-}; +- +-&spi { +- ak4104: optical-transmitter@0 { +- compatible = "asahi-kasei,ak4104"; +- reg = <0>; +- vdd-supply = <®_3v3>; +- spi-max-frequency = <5000000>; +- reset-gpios = <&gpio 38 GPIO_ACTIVE_HIGH>; +- #sound-dai-cells = <0>; +- }; +-}; +- +-&rotary { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-controller.dts b/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-controller.dts +deleted file mode 100644 +index 12b15945ac6d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-controller.dts ++++ /dev/null +@@ -1,285 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/dts-v1/; +- +-#include "pxa300-raumfeld-common.dtsi" +- +-/ { +- model = "Raumfeld Controller (PXA3xx)"; +- compatible = "raumfeld,raumfeld-controller-pxa303", "marvell,pxa300"; +- +- reg_vbatt: regulator-vbatt { +- compatible = "regulator-fixed"; +- regulator-name = "vbatt-fixed-supply"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- regulator-always-on; +- }; +- +- lcd_supply: regulator-va-tft { +- compatible = "regulator-fixed"; +- regulator-name = "va-tft-fixed-supply"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- onewire { +- compatible = "w1-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&w1_pins>; +- gpios = < +- &gpio 126 GPIO_OPEN_DRAIN /* W1 I/O */ +- &gpio 105 GPIO_ACTIVE_HIGH /* pullup */ +- >; +- +- w1_ds2760: slave-ds2760 { +- compatible = "maxim,ds2760"; +- power-supplies = <&charger>; +- }; +- }; +- +- charger: charger { +- pinctrl-names = "default"; +- pinctrl-0 = <&charger_pins>; +- compatible = "gpio-charger"; +- charger-type = "mains"; +- gpios = <&gpio 101 GPIO_ACTIVE_LOW>; +- }; +- +- /* +- * One of the following two will be set to "okay" by the bootloader, +- * depending on the hardware revision. +- */ +- backlight-controller-pwm { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pins>; +- pwms = <&pwm0 10000>; +- power-supply = <®_vbatt>; +- status = "disabled"; +- +- brightness-levels = < +- 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100 +- >; +- default-brightness-level = <100>; +- }; +- +- backlight-controller { +- compatible = "lltc,lt3593"; +- pinctrl-names = "default"; +- pinctrl-0 = <<3593_pins>; +- lltc,ctrl-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; +- status = "disabled"; +- +- led { +- label = "backlight"; +- default-state = "on"; +- }; +- }; +-}; +- +-®_va_5v0 { +- status = "disabled"; +-}; +- +-ðernet { +- status = "disabled"; +-}; +- +-&leds { +- status = "disabled"; +-}; +- +-&dac { +- status = "disabled"; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&keys { +- pinctrl-0 = <&gpio_keys_pins &dock_detect_pins>; +- dock-detect { +- label = "dock detect"; +- gpios = <&gpio 116 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +-}; +- +-&spi { +- accelerometer@1 { +- compatible = "st,lis302dl-spi"; +- pinctrl-names = "default"; +- pinctrl-0 = <&lis302_pins>; +- reg = <1>; +- spi-max-frequency = <1000000>; +- interrupt-parent = <&gpio>; +- interrupts = <104 IRQ_TYPE_EDGE_FALLING>; +- +- st,click-single-x; +- st,click-single-y; +- st,click-single-z; +- st,click-thresh-x = <10>; +- st,click-thresh-y = <10>; +- st,click-thresh-z = <10>; +- st,irq1-click; +- st,irq2-click; +- st,wakeup-x-lo; +- st,wakeup-x-hi; +- st,wakeup-y-lo; +- st,wakeup-y-hi; +- st,wakeup-z-lo; +- st,wakeup-z-hi; +- }; +-}; +- +-&lcdc { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcdc_pins>; +- lcd-supply = <&lcd_supply>; +- +- port { +- lcdc_out: endpoint { +- remote-endpoint = <&panel_in>; +- bus-width = <16>; +- }; +- }; +- +- panel { +- compatible = "sharp,lq043t3dx0-panel"; +- display-timings { +- native-mode = <&timing0>; +- timing0: timing { +- clock-frequency = <9009000>; +- pixelclk-active = <0>; /* negative edge */ +- hactive = <480>; +- vactive = <272>; +- hsync-len = <41>; +- hback-porch = <2>; +- hfront-porch = <1>; +- vsync-len = <10>; +- vback-porch = <3>; +- vfront-porch = <1>; +- }; +- }; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lcdc_out>; +- }; +- }; +- }; +-}; +- +-&gcu { +- status = "okay"; +-}; +- +-&pxai2c1 { +- touchscreen@a { +- compatible = "eeti,exc3000-i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&eeti_ts_pins>; +- reg = <0xa>; +- interrupt-parent = <&gpio>; +- interrupts = <32 IRQ_TYPE_EDGE_RISING>; +- attn-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>; +- touchscreen-inverted-y; +- }; +-}; +- +-&pinctrl { +- lis302_pins: lis302-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(104) MFP_AF0 /* IRQ */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); +- }; +- +- eeti_ts_pins: eeti-ts-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(32) MFP_AF0 /* IRQ */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); +- }; +- +- lt3593_pins: lt3593-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(17) MFP_AF0 /* Backlight */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); +- }; +- +- pwm0_pins: pwm0-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(17) MFP_AF1 /* PWM */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); +- }; +- +- w1_pins: w1-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(126) MFP_AF0 /* PWM */ +- MFP_PIN_PXA300(105) MFP_AF0 /* PWM */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); +- }; +- +- charger_pins: charger_pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(31) MFP_AF0 /* PEN2 */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_HIGH); +- pinctrl-single,bias-pullup = MPF_PULL_UP; +- }; +- +- dock_detect_pins: dock_detect_pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(116) MFP_AF0 /* DOCK_DETECT */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_HIGH); +- pinctrl-single,bias-pullup = MPF_PULL_UP; +- }; +- +- lcdc_pins: lcdc-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(54) MFP_AF1 /* LDD_0 */ +- MFP_PIN_PXA300(55) MFP_AF1 /* LDD_1 */ +- MFP_PIN_PXA300(56) MFP_AF1 /* LDD_2 */ +- MFP_PIN_PXA300(57) MFP_AF1 /* LDD_3 */ +- MFP_PIN_PXA300(58) MFP_AF1 /* LDD_4 */ +- MFP_PIN_PXA300(59) MFP_AF1 /* LDD_5 */ +- MFP_PIN_PXA300(60) MFP_AF1 /* LDD_6 */ +- MFP_PIN_PXA300(61) MFP_AF1 /* LDD_7 */ +- MFP_PIN_PXA300(62) MFP_AF1 /* LDD_8 */ +- MFP_PIN_PXA300(63) MFP_AF1 /* LDD_9 */ +- MFP_PIN_PXA300(64) MFP_AF1 /* LDD_10 */ +- MFP_PIN_PXA300(65) MFP_AF1 /* LDD_11 */ +- MFP_PIN_PXA300(66) MFP_AF1 /* LDD_12 */ +- MFP_PIN_PXA300(67) MFP_AF1 /* LDD_13 */ +- MFP_PIN_PXA300(68) MFP_AF1 /* LDD_14 */ +- MFP_PIN_PXA300(69) MFP_AF1 /* LDD_15 */ +- MFP_PIN_PXA300(70) MFP_AF1 /* LDD_16 */ +- MFP_PIN_PXA300(71) MFP_AF1 /* LDD_17 */ +- MFP_PIN_PXA300(72) MFP_AF1 /* LCD_FCLK */ +- MFP_PIN_PXA300(73) MFP_AF1 /* LCD_LCLK */ +- MFP_PIN_PXA300(74) MFP_AF1 /* LCD_PCLK */ +- MFP_PIN_PXA300(75) MFP_AF1 /* LCD_BIAS */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-speaker-l.dts b/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-speaker-l.dts +deleted file mode 100644 +index 5a0f7f17856f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-speaker-l.dts ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/dts-v1/; +- +-#include "pxa300-raumfeld-common.dtsi" +-#include "pxa300-raumfeld-tuneable-clock.dtsi" +- +-/ { +- model = "Raumfeld Speaker L (PXA3xx)"; +- compatible = "raumfeld,raumfeld-speaker-l-pxa303", "marvell,pxa300"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-speaker-m.dts b/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-speaker-m.dts +deleted file mode 100644 +index fa10d896282c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-speaker-m.dts ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/dts-v1/; +- +-#include "pxa300-raumfeld-common.dtsi" +-#include "pxa300-raumfeld-tuneable-clock.dtsi" +- +-/ { +- model = "Raumfeld Speaker M (PXA3xx)"; +- compatible = "raumfeld,raumfeld-speaker-m-pxa303", "marvell,pxa300"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-speaker-one.dts b/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-speaker-one.dts +deleted file mode 100644 +index a70560a8ea92..000000000000 +--- a/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-speaker-one.dts ++++ /dev/null +@@ -1,140 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/dts-v1/; +- +-#include "pxa300-raumfeld-common.dtsi" +- +-/ { +- model = "Raumfeld Speaker One (PXA3xx)"; +- compatible = "raumfeld,raumfeld-speaker-one-pxa303", "marvell,pxa300"; +- +- wm8782: wm8782 { +- compatible = "wm8782"; +- #sound-dai-cells = <0>; +- Vdd-supply = <®_3v3>; +- Vdda-supply = <®_va_5v0>; +- }; +- +- xo_11mhz: oscillator-11mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <11289600>; +- clock-accuracy = <100>; +- }; +- +- xo_audio: clock-gate { +- compatible = "gpio-gate-clock"; +- pinctrlnames = "default"; +- pinctrl-0 = <&xo_audio_pins>; +- clocks = <&xo_11mhz>; +- #clock-cells = <0>; +- enable-gpios = <&gpio 111 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_va_30v0: regulator-va-30v0 { +- compatible = "regulator-fixed"; +- regulator-name = "va-30v0-fixed-supply"; +- regulator-min-microvolt = <30000000>; +- regulator-max-microvolt = <30000000>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "Raumfeld Speaker"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- simple-audio-card,dai-link@0 { +- reg = <0>; +- format = "i2s"; +- bitclock-master = <&dailink_master_analog_out>; +- frame-master = <&dailink_master_analog_out>; +- mclk-fs = <256>; +- +- dailink_master_analog_out: cpu { +- sound-dai = <&ssp_dai0>; +- }; +- +- codec { +- sound-dai = <&sta320>; +- }; +- }; +- +- simple-audio-card,dai-link@1 { +- reg = <1>; +- format = "i2s"; +- bitclock-master = <&dailink_master_analog_in>; +- frame-master = <&dailink_master_analog_in>; +- mclk-fs = <256>; +- +- dailink_master_analog_in: cpu { +- sound-dai = <&ssp_dai0>; +- }; +- +- codec { +- sound-dai = <&wm8782>; +- }; +- }; +- }; +-}; +- +-&ssp_dai0 { +- clocks = <&xo_audio>; +-}; +- +-&spi { +- dac@2 { +- compatible = "ti,dac7512"; +- reg = <2>; +- spi-max-frequency = <1000000>; +- vcc-supply = <®_3v3>; +- }; +-}; +- +-&rotary { +- status = "okay"; +-}; +- +-&pxai2c1 { +- sta320: codec@1a { +- compatible = "st,sta32x"; +- reg = <0x1a>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sta320_pins>; +- clocks = <&xo_audio>; +- clock-names = "xti"; +- reset-gpios = <&gpio 120 GPIO_ACTIVE_HIGH>; +- Vdda-supply = <®_3v3>; +- Vdd3-supply = <®_3v3>; +- Vcc-supply = <®_va_30v0>; +- #sound-dai-cells = <0>; +- st,thermal-warning-adjustment; +- st,thermal-warning-recovery; +- st,fault-detect-recovery; +- st,drop-compensation-ns = <80>; +- st,max-power-use-mpcc; +- st,invalid-input-detect-mute; +- /* 2 (half-bridge) and 1 (full-bridge) on-board power */ +- st,output-conf = /bits/ 8 <0x1>; +- st,ch1-output-mapping = /bits/ 8 <0>; +- st,ch2-output-mapping = /bits/ 8 <1>; +- st,ch3-output-mapping = /bits/ 8 <2>; +- st,needs_esd_watchdog; +- }; +-}; +- +-&pinctrl { +- xo_audio_pins: xo-audio-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(111) MFP_AF0 /* ENABLE */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); +- }; +- +- sta320_pins: sta320-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(120) MFP_AF0 /* CODEC_RESET */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-speaker-s.dts b/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-speaker-s.dts +deleted file mode 100644 +index 36e20cbf8704..000000000000 +--- a/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-speaker-s.dts ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/dts-v1/; +- +-#include "pxa300-raumfeld-common.dtsi" +-#include "pxa300-raumfeld-tuneable-clock.dtsi" +- +-/ { +- model = "Raumfeld Speaker S (PXA3xx)"; +- compatible = "raumfeld,raumfeld-speaker-s-pxa303", "marvell,pxa300"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-tuneable-clock.dtsi b/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-tuneable-clock.dtsi +deleted file mode 100644 +index 561483b93989..000000000000 +--- a/scripts/dtc/include-prefixes/arm/pxa300-raumfeld-tuneable-clock.dtsi ++++ /dev/null +@@ -1,85 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include +- +-/ { +- xo_27mhz: oscillator-27mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- clock-accuracy = <100>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "Raumfeld Speaker"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- simple-audio-card,dai-link@0 { +- reg = <0>; +- format = "i2s"; +- bitclock-master = <&dailink_master_analog>; +- frame-master = <&dailink_master_analog>; +- mclk-fs = <256>; +- +- dailink_master_analog: cpu { +- sound-dai = <&ssp_dai0>; +- }; +- +- codec { +- sound-dai = <&cs4270>; +- }; +- }; +- }; +-}; +- +-&ssp_dai0 { +- clocks = <&max9485 MAX9485_CLKOUT1>; +-}; +- +-&ssp_dai1 { +- clocks = <&max9485 MAX9485_CLKOUT1>; +-}; +- +-&pxai2c1 { +- cs4270: codec@48 { +- compatible = "cirrus,cs4270"; +- pinctrl-names = "default"; +- pinctrl-0 = <&cs4270_pins>; +- reg = <0x48>; +- va-supply = <®_va_5v0>; +- vd-supply = <®_3v3>; +- vlc-supply = <®_3v3>; +- reset-gpios = <&gpio 120 GPIO_ACTIVE_HIGH>; +- #sound-dai-cells = <0>; +- }; +- +- max9485: clock-generator@63 { +- compatible = "maxim,max9485"; +- pinctrl-names = "default"; +- pinctrl-0 = <&max9485_pins>; +- reg = <0x63>; +- vdd-supply = <®_3v3>; +- clock-names = "xclk"; +- clocks = <&xo_27mhz>; +- reset-gpios = <&gpio 111 GPIO_ACTIVE_HIGH>; +- #clock-cells = <1>; +- }; +-}; +- +-&pinctrl { +- cs4270_pins: cs4270-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(120) MFP_AF0 /* RESET */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); +- }; +- +- max9485_pins: max9485-pins { +- pinctrl-single,pins = < +- MFP_PIN_PXA300(111) MFP_AF0 /* RESET */ +- >; +- pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/pxa3xx.dtsi b/scripts/dtc/include-prefixes/arm/pxa3xx.dtsi +deleted file mode 100644 +index d19674812cd2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/pxa3xx.dtsi ++++ /dev/null +@@ -1,317 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* The pxa3xx skeleton simply augments the 2xx version */ +-#include "pxa2xx.dtsi" +- +-#define MFP_PIN_PXA300(gpio) \ +- ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ +- (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ +- (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \ +- (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ +- 0) +-#define MFP_PIN_PXA300_2(gpio) \ +- ((gpio <= 1) ? (0x674 + 4 * gpio) : \ +- (gpio <= 6) ? (0x2dc + 4 * gpio) : \ +- 0) +- +-#define MFP_PIN_PXA310(gpio) \ +- ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ +- (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ +- (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \ +- (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \ +- (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ +- (gpio <= 262) ? 0 : \ +- (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \ +- 0) +-#define MFP_PIN_PXA310_2(gpio) \ +- ((gpio <= 1) ? (0x674 + 4 * gpio) : \ +- (gpio <= 6) ? (0x2dc + 4 * gpio) : \ +- (gpio <= 10) ? (0x52c + 4 * gpio) : \ +- 0) +- +-#define MFP_PIN_PXA320(gpio) \ +- ((gpio <= 4) ? (0x0124 + 4 * gpio) : \ +- (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \ +- (gpio <= 10) ? (0x0458 + 4 * (gpio - 10)) : \ +- (gpio <= 26) ? (0x02a0 + 4 * (gpio - 11)) : \ +- (gpio <= 48) ? (0x0400 + 4 * (gpio - 27)) : \ +- (gpio <= 62) ? (0x045c + 4 * (gpio - 49)) : \ +- (gpio <= 73) ? (0x04b4 + 4 * (gpio - 63)) : \ +- (gpio <= 98) ? (0x04f0 + 4 * (gpio - 74)) : \ +- (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ +- 0) +-#define MFP_PIN_PXA320_2(gpio) \ +- ((gpio <= 3) ? (0x674 + 4 * gpio) : \ +- (gpio <= 5) ? (0x284 + 4 * gpio) : \ +- 0) +- +-/* +- * MFP Alternate functions for pins having a gpio. +- * Example of use: pinctrl-single,pins = < MFP_PIN_PXA310(21) MFP_AF1 > +- */ +-#define MFP_AF0 (0 << 0) +-#define MFP_AF1 (1 << 0) +-#define MFP_AF2 (2 << 0) +-#define MFP_AF3 (3 << 0) +-#define MFP_AF4 (4 << 0) +-#define MFP_AF5 (5 << 0) +-#define MFP_AF6 (6 << 0) +- +-/* +- * MFP drive strength functions for pins. +- * Example of use: pinctrl-single,drive-strength = MFP_DS03X; +- */ +-#define MFP_DSMSK (0x7 << 10) +-#define MFP_DS01X < (0x0 << 10) MFP_DSMSK > +-#define MFP_DS02X < (0x1 << 10) MFP_DSMSK > +-#define MFP_DS03X < (0x2 << 10) MFP_DSMSK > +-#define MFP_DS04X < (0x3 << 10) MFP_DSMSK > +-#define MFP_DS06X < (0x4 << 10) MFP_DSMSK > +-#define MFP_DS08X < (0x5 << 10) MFP_DSMSK > +-#define MFP_DS10X < (0x6 << 10) MFP_DSMSK > +-#define MFP_DS13X < (0x7 << 10) MFP_DSMSK > +- +-/* +- * MFP bias pull mode for pins. +- * Example of use: pinctrl-single,bias-pullup = MPF_PULL_UP; +- */ +-#define MPF_PULL_MSK (0x7 << 13) +-#define MPF_PULL_DOWN < (0x5 << 13) (0x5 << 13) 0 MPF_PULL_MSK > +-#define MPF_PULL_UP < (0x6 << 13) (0x6 << 13) 0 MPF_PULL_MSK > +- +-/* +- * MFP low power mode for pins. +- * Example of use: +- * pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW|MFP_LPM_EDGE_FALL); +- * +- * Table that determines the low power modes outputs, with actual settings +- * used in parentheses for don't-care values. Except for the float output, +- * the configured driven and pulled levels match, so if there is a need for +- * non-LPM pulled output, the same configuration could probably be used. +- * +- * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel +- * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) +- * +- * Input 0 X(0) X(0) X(0) 0 +- * Drive 0 0 0 0 X(1) 0 +- * Drive 1 0 1 X(1) 0 0 +- * Pull hi (1) 1 X(1) 1 0 0 +- * Pull lo (0) 1 X(0) 0 1 0 +- * Z (float) 1 X(0) 0 0 0 +- */ +-#define MFP_LPM(x) < (x) MFP_LPM_MSK > +- +-#define MFP_LPM_MSK 0xe1f0 +-#define MFP_LPM_INPUT 0x0000 +-#define MFP_LPM_DRIVE_LOW 0x2000 +-#define MFP_LPM_DRIVE_HIGH 0x4100 +-#define MFP_LPM_PULL_LOW 0x2080 +-#define MFP_LPM_PULL_HIGH 0x4180 +-#define MFP_LPM_FLOAT 0x0080 +- +-#define MFP_LPM_EDGE_NONE 0x0000 +-#define MFP_LPM_EDGE_RISE 0x0010 +-#define MFP_LPM_EDGE_FALL 0x0020 +-#define MFP_LPM_EDGE_BOTH 0x0030 +- +-/ { +- model = "Marvell PXA3xx familiy SoC"; +- compatible = "marvell,pxa3xx"; +- +- pxabus { +- pdma: dma-controller@40000000 { +- compatible = "marvell,pdma-1.0"; +- reg = <0x40000000 0x10000>; +- interrupts = <25>; +- #dma-channels = <32>; +- #dma-cells = <2>; +- #dma-requests = <100>; +- status = "okay"; +- }; +- +- pwri2c: i2c@40f500c0 { +- compatible = "mrvl,pwri2c"; +- reg = <0x40f500c0 0x30>; +- interrupts = <6>; +- clocks = <&clks CLK_PWRI2C>; +- #address-cells = <0x1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- nand_controller: nand-controller@43100000 { +- compatible = "marvell,pxa3xx-nand-controller"; +- reg = <0x43100000 90>; +- interrupts = <45>; +- clocks = <&clks CLK_NAND>; +- clock-names = "core"; +- dmas = <&pdma 97 3>; +- dma-names = "data"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pxairq: interrupt-controller@40d00000 { +- marvell,intc-priority; +- marvell,intc-nr-irqs = <56>; +- }; +- +- pinctrl: pinctrl@40e10000 { +- compatible = "pinconf-single"; +- reg = <0x40e10000 0xffff>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0x7>; +- }; +- +- gpio: gpio@40e00000 { +- compatible = "intel,pxa3xx-gpio"; +- reg = <0x40e00000 0x10000>; +- clocks = <&clks CLK_GPIO>; +- gpio-ranges = <&pinctrl 0 0 128>; +- interrupt-names = "gpio0", "gpio1", "gpio_mux"; +- interrupts = <8>, <9>, <10>; +- gpio-controller; +- #gpio-cells = <0x2>; +- interrupt-controller; +- #interrupt-cells = <0x2>; +- }; +- +- mmc0: mmc@41100000 { +- compatible = "marvell,pxa-mmc"; +- reg = <0x41100000 0x1000>; +- interrupts = <23>; +- clocks = <&clks CLK_MMC1>; +- dmas = <&pdma 21 3 +- &pdma 22 3>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- mmc1: mmc@42000000 { +- compatible = "marvell,pxa-mmc"; +- reg = <0x42000000 0x1000>; +- interrupts = <41>; +- clocks = <&clks CLK_MMC2>; +- dmas = <&pdma 93 3 +- &pdma 94 3>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- mmc2: mmc@42500000 { +- compatible = "marvell,pxa-mmc"; +- reg = <0x42500000 0x1000>; +- interrupts = <55>; +- clocks = <&clks CLK_MMC3>; +- dmas = <&pdma 46 3 +- &pdma 47 3>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- usb0: usb@4c000000 { +- compatible = "marvell,pxa-ohci"; +- reg = <0x4c000000 0x10000>; +- interrupts = <3>; +- clocks = <&clks CLK_USBH>; +- status = "disabled"; +- }; +- +- pwm0: pwm@40b00000 { +- compatible = "marvell,pxa270-pwm"; +- reg = <0x40b00000 0x10>; +- #pwm-cells = <1>; +- clocks = <&clks CLK_PWM0>; +- status = "disabled"; +- }; +- +- pwm1: pwm@40b00010 { +- compatible = "marvell,pxa270-pwm"; +- reg = <0x40b00010 0x10>; +- #pwm-cells = <1>; +- clocks = <&clks CLK_PWM1>; +- status = "disabled"; +- }; +- +- pwm2: pwm@40c00000 { +- compatible = "marvell,pxa270-pwm"; +- reg = <0x40c00000 0x10>; +- #pwm-cells = <1>; +- clocks = <&clks CLK_PWM0>; +- status = "disabled"; +- }; +- +- pwm3: pwm@40c00010 { +- compatible = "marvell,pxa270-pwm"; +- reg = <0x40c00010 0x10>; +- #pwm-cells = <1>; +- clocks = <&clks CLK_PWM1>; +- status = "disabled"; +- }; +- +- ssp1: ssp@41000000 { +- compatible = "mrvl,pxa3xx-ssp"; +- reg = <0x41000000 0x40>; +- interrupts = <24>; +- clocks = <&clks CLK_SSP1>; +- status = "disabled"; +- }; +- +- ssp2: ssp@41700000 { +- compatible = "mrvl,pxa3xx-ssp"; +- reg = <0x41700000 0x40>; +- interrupts = <16>; +- clocks = <&clks CLK_SSP2>; +- status = "disabled"; +- }; +- +- ssp3: ssp@41900000 { +- compatible = "mrvl,pxa3xx-ssp"; +- reg = <0x41900000 0x40>; +- interrupts = <0>; +- clocks = <&clks CLK_SSP3>; +- status = "disabled"; +- }; +- +- ssp4: ssp@41a00000 { +- compatible = "mrvl,pxa3xx-ssp"; +- reg = <0x41a00000 0x40>; +- interrupts = <13>; +- clocks = <&clks CLK_SSP4>; +- status = "disabled"; +- }; +- +- timer@40a00000 { +- compatible = "marvell,pxa-timer"; +- reg = <0x40a00000 0x20>; +- interrupts = <26>; +- clocks = <&clks CLK_OSTIMER>; +- status = "okay"; +- }; +- +- gcu: display-controller@54000000 { +- compatible = "marvell,pxa300-gcu"; +- reg = <0x54000000 0x1000>; +- interrupts = <39>; +- clocks = <&clks CLK_PXA300_GCU>; +- status = "disabled"; +- }; +- }; +- +- clocks { +- /* +- * The muxing of external clocks/internal dividers for osc* clock +- * sources has been hidden under the carpet by now. +- */ +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clks: clocks { +- compatible = "marvell,pxa300-clocks"; +- #clock-cells = <1>; +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/pxa910-dkb.dts b/scripts/dtc/include-prefixes/arm/pxa910-dkb.dts +deleted file mode 100644 +index ce76158867c7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/pxa910-dkb.dts ++++ /dev/null +@@ -1,170 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Marvell Technology Group Ltd. +- * Author: Haojian Zhuang +- */ +- +-/dts-v1/; +-#include "pxa910.dtsi" +- +-/ { +- model = "Marvell PXA910 DKB Development Board"; +- compatible = "mrvl,pxa910-dkb", "mrvl,pxa910"; +- +- chosen { +- bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; +- }; +- +- memory { +- reg = <0x00000000 0x10000000>; +- }; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&twsi1 { +- status = "okay"; +- +- pmic: 88pm860x@34 { +- compatible = "marvell,88pm860x"; +- reg = <0x34>; +- interrupts = <4>; +- interrupt-parent = <&intc>; +- interrupt-controller; +- #interrupt-cells = <1>; +- +- marvell,88pm860x-irq-read-clr; +- marvell,88pm860x-slave-addr = <0x11>; +- +- regulators { +- BUCK1 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- BUCK2 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- BUCK3 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <2800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- LDO5 { +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO9 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO10 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- LDO12 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- LDO13 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- LDO14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- rtc { +- marvell,88pm860x-vrtc = <1>; +- }; +- touch { +- marvell,88pm860x-gpadc-prebias = <1>; +- marvell,88pm860x-gpadc-slot-cycle = <1>; +- marvell,88pm860x-tsi-prebias = <6>; +- marvell,88pm860x-pen-prebias = <16>; +- marvell,88pm860x-pen-prechg = <2>; +- marvell,88pm860x-resistor-X = <300>; +- }; +- backlights { +- backlight-0 { +- marvell,88pm860x-iset = <4>; +- marvell,88pm860x-pwm = <3>; +- }; +- backlight-2 { +- }; +- }; +- leds { +- led0-red { +- marvell,88pm860x-iset = <12>; +- }; +- led0-green { +- marvell,88pm860x-iset = <12>; +- }; +- led0-blue { +- marvell,88pm860x-iset = <12>; +- }; +- }; +- }; +-}; +- +-&rtc { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/pxa910.dtsi b/scripts/dtc/include-prefixes/arm/pxa910.dtsi +deleted file mode 100644 +index 352a39357810..000000000000 +--- a/scripts/dtc/include-prefixes/arm/pxa910.dtsi ++++ /dev/null +@@ -1,177 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Marvell Technology Group Ltd. +- * Author: Haojian Zhuang +- */ +- +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- i2c0 = &twsi1; +- i2c1 = &twsi2; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&intc>; +- ranges; +- +- L2: l2-cache { +- compatible = "marvell,tauros2-cache"; +- marvell,tauros2-cache-features = <0x3>; +- }; +- +- axi@d4200000 { /* AXI */ +- compatible = "mrvl,axi-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xd4200000 0x00200000>; +- ranges; +- +- intc: interrupt-controller@d4282000 { +- compatible = "mrvl,mmp-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0xd4282000 0x1000>; +- mrvl,intc-nr-irqs = <64>; +- }; +- +- }; +- +- apb@d4000000 { /* APB */ +- compatible = "mrvl,apb-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xd4000000 0x00200000>; +- ranges; +- +- timer0: timer@d4014000 { +- compatible = "mrvl,mmp-timer"; +- reg = <0xd4014000 0x100>; +- interrupts = <13>; +- }; +- +- timer1: timer@d4016000 { +- compatible = "mrvl,mmp-timer"; +- reg = <0xd4016000 0x100>; +- interrupts = <29>; +- status = "disabled"; +- }; +- +- uart1: serial@d4017000 { +- compatible = "mrvl,mmp-uart", "intel,xscale-uart"; +- reg = <0xd4017000 0x1000>; +- reg-shift = <2>; +- interrupts = <27>; +- clocks = <&soc_clocks PXA910_CLK_UART0>; +- resets = <&soc_clocks PXA910_CLK_UART0>; +- status = "disabled"; +- }; +- +- uart2: serial@d4018000 { +- compatible = "mrvl,mmp-uart", "intel,xscale-uart"; +- reg = <0xd4018000 0x1000>; +- reg-shift = <2>; +- interrupts = <28>; +- clocks = <&soc_clocks PXA910_CLK_UART1>; +- resets = <&soc_clocks PXA910_CLK_UART1>; +- status = "disabled"; +- }; +- +- uart3: serial@d4036000 { +- compatible = "mrvl,mmp-uart", "intel,xscale-uart"; +- reg = <0xd4036000 0x1000>; +- reg-shift = <2>; +- interrupts = <59>; +- clocks = <&soc_clocks PXA910_CLK_UART2>; +- resets = <&soc_clocks PXA910_CLK_UART2>; +- status = "disabled"; +- }; +- +- gpio@d4019000 { +- compatible = "marvell,mmp-gpio"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xd4019000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = <49>; +- interrupt-names = "gpio_mux"; +- clocks = <&soc_clocks PXA910_CLK_GPIO>; +- resets = <&soc_clocks PXA910_CLK_GPIO>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ranges; +- +- gcb0: gpio@d4019000 { +- reg = <0xd4019000 0x4>; +- }; +- +- gcb1: gpio@d4019004 { +- reg = <0xd4019004 0x4>; +- }; +- +- gcb2: gpio@d4019008 { +- reg = <0xd4019008 0x4>; +- }; +- +- gcb3: gpio@d4019100 { +- reg = <0xd4019100 0x4>; +- }; +- }; +- +- twsi1: i2c@d4011000 { +- compatible = "mrvl,mmp-twsi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xd4011000 0x1000>; +- interrupts = <7>; +- clocks = <&soc_clocks PXA910_CLK_TWSI0>; +- resets = <&soc_clocks PXA910_CLK_TWSI0>; +- mrvl,i2c-fast-mode; +- status = "disabled"; +- }; +- +- twsi2: i2c@d4037000 { +- compatible = "mrvl,mmp-twsi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xd4037000 0x1000>; +- interrupts = <54>; +- clocks = <&soc_clocks PXA910_CLK_TWSI1>; +- resets = <&soc_clocks PXA910_CLK_TWSI1>; +- status = "disabled"; +- }; +- +- rtc: rtc@d4010000 { +- compatible = "mrvl,mmp-rtc"; +- reg = <0xd4010000 0x1000>; +- interrupts = <5>, <6>; +- interrupt-names = "rtc 1Hz", "rtc alarm"; +- clocks = <&soc_clocks PXA910_CLK_RTC>; +- resets = <&soc_clocks PXA910_CLK_RTC>; +- status = "disabled"; +- }; +- }; +- +- soc_clocks: clocks{ +- compatible = "marvell,pxa910-clock"; +- reg = <0xd4050000 0x1000>, +- <0xd4282800 0x400>, +- <0xd4015000 0x1000>, +- <0xd403b000 0x1000>; +- reg-names = "mpmu", "apmu", "apbc", "apbcp"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-apq8060-dragonboard.dts b/scripts/dtc/include-prefixes/arm/qcom-apq8060-dragonboard.dts +deleted file mode 100644 +index e1189e929ee6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-apq8060-dragonboard.dts ++++ /dev/null +@@ -1,937 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +-#include +-#include +-#include +-#include +-#include "qcom-msm8660.dtsi" +- +-/ { +- model = "Qualcomm APQ8060 Dragonboard"; +- compatible = "qcom,apq8060-dragonboard", "qcom,msm8660"; +- +- aliases { +- serial0 = &gsbi12_serial; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- regulators { +- compatible = "simple-bus"; +- +- /* Main power of the board: 3.7V */ +- vph: regulator-fixed { +- compatible = "regulator-fixed"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- regulator-name = "VPH"; +- regulator-type = "voltage"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* GPIO controlled ethernet power regulator */ +- dragon_veth: xc622a331mrg { +- compatible = "regulator-fixed"; +- regulator-name = "XC6222A331MR-G"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vph>; +- gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&dragon_veth_gpios>; +- regulator-always-on; +- }; +- +- /* VDDvario fixed regulator */ +- dragon_vario: nds332p { +- compatible = "regulator-fixed"; +- regulator-name = "NDS332P"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&pm8058_s3>; +- }; +- +- /* This is a levelshifter for SDCC5 */ +- dragon_vio_txb: txb0104rgyr { +- compatible = "regulator-fixed"; +- regulator-name = "Dragon SDCC levelshifter"; +- vin-supply = <&pm8058_l14>; +- regulator-always-on; +- }; +- }; +- +- /* +- * Capella CM3605 light and proximity sensor mounted directly +- * on the sensor board. +- */ +- cm3605 { +- compatible = "capella,cm3605"; +- vdd-supply = <&pm8058_l14>; // 2.85V +- aset-gpios = <&pm8058_gpio 35 GPIO_ACTIVE_LOW>; +- capella,aset-resistance-ohms = <100000>; +- /* Trig on both edges - getting close or far away */ +- interrupts-extended = <&pm8058_gpio 34 IRQ_TYPE_EDGE_BOTH>; +- /* MPP05 analog input to the XOADC */ +- io-channels = <&xoadc 0x00 0x05>; +- io-channel-names = "aout"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dragon_cm3605_gpios>, <&dragon_cm3605_mpps>; +- }; +- +- soc { +- pinctrl@800000 { +- /* eMMMC pins, all 8 data lines connected */ +- dragon_sdcc1_pins: sdcc1 { +- mux { +- pins = "gpio159", "gpio160", "gpio161", +- "gpio162", "gpio163", "gpio164", +- "gpio165", "gpio166", "gpio167", +- "gpio168"; +- function = "sdc1"; +- }; +- clk { +- pins = "gpio167"; /* SDC1 CLK */ +- drive-strength = <16>; +- bias-disable; +- }; +- cmd { +- pins = "gpio168"; /* SDC1 CMD */ +- drive-strength = <10>; +- bias-pull-up; +- }; +- data { +- /* SDC1 D0 to D7 */ +- pins = "gpio159", "gpio160", "gpio161", "gpio162", +- "gpio163", "gpio164", "gpio165", "gpio166"; +- drive-strength = <10>; +- bias-pull-up; +- }; +- }; +- +- /* +- * The SDCC3 pins are hardcoded (non-muxable) but need some pin +- * configuration. +- */ +- dragon_sdcc3_pins: sdcc3 { +- clk { +- pins = "sdc3_clk"; +- drive-strength = <8>; +- bias-disable; +- }; +- cmd { +- pins = "sdc3_cmd"; +- drive-strength = <8>; +- bias-pull-up; +- }; +- data { +- pins = "sdc3_data"; +- drive-strength = <8>; +- bias-pull-up; +- }; +- }; +- +- /* Second SD card slot pins */ +- dragon_sdcc5_pins: sdcc5 { +- mux { +- pins = "gpio95", "gpio96", "gpio97", +- "gpio98", "gpio99", "gpio100"; +- function = "sdc5"; +- }; +- clk { +- pins = "gpio97"; /* SDC5 CLK */ +- drive-strength = <16>; +- bias-disable; +- }; +- cmd { +- pins = "gpio95"; /* SDC5 CMD */ +- drive-strength = <10>; +- bias-pull-up; +- }; +- data { +- /* SDC5 D0 to D3 */ +- pins = "gpio96", "gpio98", "gpio99", "gpio100"; +- drive-strength = <10>; +- bias-pull-up; +- }; +- }; +- +- dragon_gsbi8_i2c_pins: gsbi8_i2c { +- mux { +- pins = "gpio64", "gpio65"; +- function = "gsbi8"; +- }; +- pinconf { +- pins = "gpio64", "gpio65"; +- drive-strength = <16>; +- /* These have external pull-up 2.2kOhm to 1.8V */ +- bias-disable; +- }; +- }; +- +- dragon_gsbi12_i2c_pins: gsbi12_i2c { +- mux { +- pins = "gpio115", "gpio116"; +- function = "gsbi12"; +- }; +- pinconf { +- pins = "gpio115", "gpio116"; +- drive-strength = <16>; +- /* These have external pull-up 4.7kOhm to 1.8V */ +- bias-disable; +- }; +- }; +- +- /* Primary serial port uart 0 pins */ +- dragon_gsbi12_serial_pins: gsbi12_serial { +- mux { +- pins = "gpio117", "gpio118"; +- function = "gsbi12"; +- }; +- tx { +- pins = "gpio117"; +- drive-strength = <8>; +- bias-disable; +- }; +- rx { +- pins = "gpio118"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- }; +- +- dragon_ebi2_pins: ebi2 { +- /* +- * Pins used by EBI2 on the Dragonboard, actually only +- * CS2 is used by a real peripheral. CS0 is just +- * routed to a test point. +- */ +- mux0 { +- pins = +- /* "gpio39", CS1A_N this is not good to mux */ +- "gpio40", /* CS2A_N */ +- "gpio134"; /* CS0_N testpoint TP29 */ +- function = "ebi2cs"; +- }; +- mux1 { +- pins = +- /* EBI2_ADDR_7 downto EBI2_ADDR_0 address bus */ +- "gpio123", "gpio124", "gpio125", "gpio126", +- "gpio127", "gpio128", "gpio129", "gpio130", +- /* EBI2_DATA_15 downto EBI2_DATA_0 data bus */ +- "gpio135", "gpio136", "gpio137", "gpio138", +- "gpio139", "gpio140", "gpio141", "gpio142", +- "gpio143", "gpio144", "gpio145", "gpio146", +- "gpio147", "gpio148", "gpio149", "gpio150", +- "gpio151", /* EBI2_OE_N */ +- "gpio153", /* EBI2_ADV */ +- "gpio157"; /* EBI2_WE_N */ +- function = "ebi2"; +- }; +- }; +- +- /* Interrupt line for the KXSD9 accelerometer */ +- dragon_kxsd9_gpios: kxsd9 { +- irq { +- pins = "gpio57"; /* IRQ line */ +- bias-pull-up; +- }; +- }; +- }; +- +- qcom,ssbi@500000 { +- pmic@0 { +- keypad@148 { +- linux,keymap = < +- MATRIX_KEY(0, 0, KEY_MENU) +- MATRIX_KEY(0, 2, KEY_1) +- MATRIX_KEY(0, 3, KEY_4) +- MATRIX_KEY(0, 4, KEY_7) +- MATRIX_KEY(1, 0, KEY_UP) +- MATRIX_KEY(1, 1, KEY_LEFT) +- MATRIX_KEY(1, 2, KEY_DOWN) +- MATRIX_KEY(1, 3, KEY_5) +- MATRIX_KEY(1, 3, KEY_8) +- MATRIX_KEY(2, 0, KEY_HOME) +- MATRIX_KEY(2, 1, KEY_REPLY) +- MATRIX_KEY(2, 2, KEY_2) +- MATRIX_KEY(2, 3, KEY_6) +- MATRIX_KEY(3, 0, KEY_VOLUMEUP) +- MATRIX_KEY(3, 1, KEY_RIGHT) +- MATRIX_KEY(3, 2, KEY_3) +- MATRIX_KEY(3, 3, KEY_9) +- MATRIX_KEY(3, 4, KEY_SWITCHVIDEOMODE) +- MATRIX_KEY(4, 0, KEY_VOLUMEDOWN) +- MATRIX_KEY(4, 1, KEY_BACK) +- MATRIX_KEY(4, 2, KEY_CAMERA) +- MATRIX_KEY(4, 3, KEY_KBDILLUMTOGGLE) +- >; +- keypad,num-rows = <6>; +- keypad,num-columns = <5>; +- }; +- +- gpio@150 { +- dragon_ethernet_gpios: ethernet-gpios { +- pinconf { +- pins = "gpio7"; +- function = "normal"; +- input-enable; +- bias-disable; +- power-source = ; +- }; +- }; +- dragon_bmp085_gpios: bmp085-gpios { +- pinconf { +- pins = "gpio16"; +- function = "normal"; +- input-enable; +- bias-disable; +- power-source = ; +- }; +- }; +- dragon_mpu3050_gpios: mpu3050-gpios { +- pinconf { +- pins = "gpio17"; +- function = "normal"; +- input-enable; +- bias-disable; +- power-source = ; +- }; +- }; +- dragon_sdcc3_gpios: sdcc3-gpios { +- pinconf { +- pins = "gpio22"; +- function = "normal"; +- input-enable; +- bias-disable; +- power-source = ; +- }; +- }; +- dragon_sdcc5_gpios: sdcc5-gpios { +- pinconf { +- pins = "gpio26"; +- function = "normal"; +- input-enable; +- bias-pull-up; +- qcom,pull-up-strength = ; +- power-source = ; +- }; +- }; +- dragon_ak8975_gpios: ak8975-gpios { +- pinconf { +- pins = "gpio33"; +- function = "normal"; +- input-enable; +- bias-disable; +- power-source = ; +- }; +- }; +- dragon_cm3605_gpios: cm3605-gpios { +- /* Pin 34 connected to the proxy IRQ */ +- pinconf_gpio34 { +- pins = "gpio34"; +- function = "normal"; +- input-enable; +- bias-disable; +- power-source = ; +- }; +- /* Pin 35 connected to ASET */ +- pinconf_gpio35 { +- pins = "gpio35"; +- function = "normal"; +- output-high; +- bias-disable; +- power-source = ; +- }; +- }; +- dragon_veth_gpios: veth-gpios { +- pinconf { +- pins = "gpio40"; +- function = "normal"; +- bias-disable; +- drive-push-pull; +- }; +- }; +- }; +- +- mpps@50 { +- dragon_cm3605_mpps: cm3605-mpps { +- pinconf { +- pins = "mpp5"; +- function = "analog"; +- input-enable; +- bias-high-impedance; +- /* Let's use channel 5 */ +- qcom,amux-route = ; +- power-source = ; +- }; +- }; +- }; +- +- xoadc@197 { +- /* Reference voltage 2.2 V */ +- xoadc-ref-supply = <&pm8058_l18>; +- +- /* Board-specific channels */ +- mpp5@5 { +- /* Connected to AOUT of ALS sensor */ +- reg = <0x00 0x05>; +- }; +- mpp6@6 { +- /* Connected to test point TP43 */ +- reg = <0x00 0x06>; +- }; +- mpp7@7 { +- /* Connected to battery thermistor */ +- reg = <0x00 0x07>; +- }; +- mpp8@8 { +- /* Connected to battery ID detector */ +- reg = <0x00 0x08>; +- }; +- mpp9@9 { +- /* Connected to XO thermistor */ +- reg = <0x00 0x09>; +- }; +- }; +- +- led@48 { +- /* +- * The keypad LED @0x48 is routed to +- * the sensor board where it is +- * connected to an infrared LED +- * SFH4650 (60mW, @850nm) next to the +- * ambient light and proximity sensor +- * Capella Microsystems CM3605. +- */ +- compatible = "qcom,pm8058-keypad-led"; +- reg = <0x48>; +- label = "pm8058:infrared:proximitysensor"; +- default-state = "off"; +- linux,default-trigger = "cm3605"; +- }; +- led@131 { +- compatible = "qcom,pm8058-led"; +- reg = <0x131>; +- label = "pm8058:red"; +- default-state = "off"; +- }; +- led@132 { +- /* +- * This is actually green too on my +- * board, but documented as yellow. +- */ +- compatible = "qcom,pm8058-led"; +- reg = <0x132>; +- label = "pm8058:yellow"; +- default-state = "off"; +- linux,default-trigger = "mmc0"; +- }; +- led@133 { +- compatible = "qcom,pm8058-led"; +- reg = <0x133>; +- label = "pm8058:green"; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- }; +- +- gsbi@19800000 { +- status = "okay"; +- qcom,mode = ; +- +- i2c@19880000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dragon_gsbi8_i2c_pins>; +- +- eeprom@52 { +- /* A 16KiB Platform ID EEPROM on the CPU carrier board */ +- compatible = "atmel,24c128"; +- reg = <0x52>; +- vcc-supply = <&pm8058_s3>; +- pagesize = <64>; +- }; +- wm8903: wm8903@1a { +- /* This Woolfson Micro device has an unrouted interrupt line */ +- compatible = "wlf,wm8903"; +- reg = <0x1a>; +- +- AVDD-supply = <&pm8058_l16>; +- CPVDD-supply = <&pm8058_l16>; +- DBVDD-supply = <&pm8058_s3>; +- DCVDD-supply = <&pm8058_l0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- micdet-cfg = <0>; +- micdet-delay = <100>; +- gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; +- }; +- }; +- }; +- +- gsbi@19c00000 { +- status = "okay"; +- qcom,mode = ; +- +- serial@19c40000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dragon_gsbi12_serial_pins>; +- }; +- +- i2c@19c80000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dragon_gsbi12_i2c_pins>; +- +- ak8975@c { +- compatible = "asahi-kasei,ak8975"; +- reg = <0x0c>; +- interrupt-parent = <&pm8058_gpio>; +- interrupts = <33 IRQ_TYPE_EDGE_RISING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&dragon_ak8975_gpios>; +- vid-supply = <&pm8058_lvs0>; // 1.8V +- vdd-supply = <&pm8058_l14>; // 2.85V +- }; +- bmp085@77 { +- compatible = "bosch,bmp085"; +- reg = <0x77>; +- interrupt-parent = <&pm8058_gpio>; +- interrupts = <16 IRQ_TYPE_EDGE_RISING>; +- reset-gpios = <&tlmm 86 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&dragon_bmp085_gpios>; +- vddd-supply = <&pm8058_lvs0>; // 1.8V +- vdda-supply = <&pm8058_l14>; // 2.85V +- }; +- mpu3050@68 { +- compatible = "invensense,mpu3050"; +- reg = <0x68>; +- /* +- * GPIO17 is pulled high by a 10k +- * resistor to VLOGIC so needs to be +- * active low/falling edge. +- */ +- interrupts-extended = <&pm8058_gpio 17 IRQ_TYPE_EDGE_FALLING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&dragon_mpu3050_gpios>; +- vlogic-supply = <&pm8058_lvs0>; // 1.8V +- vdd-supply = <&pm8058_l14>; // 2.85V +- +- /* +- * The MPU-3050 acts as a hub for the +- * accelerometer. +- */ +- i2c-gate { +- #address-cells = <1>; +- #size-cells = <0>; +- +- kxsd9@18 { +- compatible = "kionix,kxsd9"; +- reg = <0x18>; +- interrupt-parent = <&tlmm>; +- interrupts = <57 IRQ_TYPE_EDGE_FALLING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&dragon_kxsd9_gpios>; +- iovdd-supply = <&pm8058_lvs0>; // 1.8V +- vdd-supply = <&pm8058_l14>; // 2.85V +- }; +- }; +- }; +- }; +- }; +- +- external-bus@1a100000 { +- /* The EBI2 will instantiate first, then populate its children */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dragon_ebi2_pins>; +- +- /* +- * An on-board SMSC LAN9221 chip for "debug ethernet", +- * which is actually just an ordinary ethernet on the +- * EBI2. This has a 25MHz chrystal next to it, so no +- * clocking is needed. +- */ +- ethernet@2,0 { +- compatible = "smsc,lan9221", "smsc,lan9115"; +- reg = <2 0x0 0x100>; +- /* +- * The second interrupt is the PME interrupt +- * for network wakeup, connected to the TLMM. +- */ +- interrupts-extended = <&pm8058_gpio 7 IRQ_TYPE_EDGE_FALLING>, +- <&tlmm 29 IRQ_TYPE_EDGE_RISING>; +- reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; +- vdd33a-supply = <&dragon_veth>; +- vddvario-supply = <&dragon_vario>; +- pinctrl-names = "default"; +- pinctrl-0 = <&dragon_ethernet_gpios>; +- phy-mode = "mii"; +- reg-io-width = <2>; +- smsc,force-external-phy; +- smsc,irq-push-pull; +- +- /* +- * SLOW chipselect config +- * Delay 9 cycles (140ns@64MHz) between SMSC +- * LAN9221 Ethernet controller reads and writes +- * on CS2. +- */ +- qcom,xmem-recovery-cycles = <0>; +- qcom,xmem-write-hold-cycles = <3>; +- qcom,xmem-write-delta-cycles = <31>; +- qcom,xmem-read-delta-cycles = <28>; +- qcom,xmem-write-wait-cycles = <9>; +- qcom,xmem-read-wait-cycles = <9>; +- }; +- }; +- +- rpm@104000 { +- /* +- * Set up of the PMIC RPM regulators for this board +- * PM8901 supplies "preliminary regulators" whatever +- * that means +- */ +- pm8901-regulators { +- vdd_l0-supply = <&pm8901_s4>; +- vdd_l1-supply = <&vph>; +- vdd_l2-supply = <&vph>; +- vdd_l3-supply = <&vph>; +- vdd_l4-supply = <&vph>; +- vdd_l5-supply = <&vph>; +- vdd_l6-supply = <&vph>; +- /* vdd_s0-supply, vdd_s1-supply: SAW regulators */ +- vdd_s2-supply = <&vph>; +- vdd_s3-supply = <&vph>; +- vdd_s4-supply = <&vph>; +- lvs0_in-supply = <&pm8058_s3>; +- lvs1_in-supply = <&pm8901_s4>; +- lvs2_in-supply = <&pm8058_l0>; +- lvs3_in-supply = <&pm8058_s2>; +- mvs_in-supply = <&pm8058_s3>; +- +- l0 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- bias-pull-down; +- }; +- l1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- bias-pull-down; +- }; +- l2 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3300000>; +- bias-pull-down; +- }; +- l3 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- bias-pull-down; +- }; +- l4 { +- regulator-min-microvolt = <2600000>; +- regulator-max-microvolt = <2600000>; +- bias-pull-down; +- }; +- l5 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- bias-pull-down; +- }; +- l6 { +- regulator-min-microvolt = <2200000>; +- regulator-max-microvolt = <2200000>; +- bias-pull-down; +- }; +- +- /* s0 and s1 are SAW regulators controlled over SPM */ +- s2 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- qcom,switch-mode-frequency = <1600000>; +- bias-pull-down; +- }; +- s3 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- qcom,switch-mode-frequency = <1600000>; +- bias-pull-down; +- }; +- s4 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- qcom,switch-mode-frequency = <1600000>; +- bias-pull-down; +- }; +- +- /* LVS0 thru 3 and mvs0 are just switches */ +- lvs0 { +- regulator-always-on; +- }; +- lvs1 { }; +- lvs2 { }; +- lvs3 { }; +- mvs0 {}; +- +- }; +- +- pm8058-regulators { +- vdd_l0_l1_lvs-supply = <&pm8058_s3>; +- vdd_l2_l11_l12-supply = <&vph>; +- vdd_l3_l4_l5-supply = <&vph>; +- vdd_l6_l7-supply = <&vph>; +- vdd_l8-supply = <&vph>; +- vdd_l9-supply = <&vph>; +- vdd_l10-supply = <&vph>; +- vdd_l13_l16-supply = <&pm8058_s4>; +- vdd_l14_l15-supply = <&vph>; +- vdd_l17_l18-supply = <&vph>; +- vdd_l19_l20-supply = <&vph>; +- vdd_l21-supply = <&pm8058_s3>; +- vdd_l22-supply = <&pm8058_s3>; +- vdd_l23_l24_l25-supply = <&pm8058_s3>; +- vdd_s0-supply = <&vph>; +- vdd_s1-supply = <&vph>; +- vdd_s2-supply = <&vph>; +- vdd_s3-supply = <&vph>; +- vdd_s4-supply = <&vph>; +- vdd_ncp-supply = <&vph>; +- +- l0 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- bias-pull-down; +- }; +- l1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- bias-pull-down; +- }; +- l2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2600000>; +- bias-pull-down; +- }; +- l3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- bias-pull-down; +- }; +- l4 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- bias-pull-down; +- }; +- l5 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- bias-pull-down; +- }; +- l6 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3600000>; +- bias-pull-down; +- }; +- l7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- bias-pull-down; +- }; +- l8 { +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <3050000>; +- bias-pull-down; +- }; +- l9 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- bias-pull-down; +- }; +- l10 { +- regulator-min-microvolt = <2600000>; +- regulator-max-microvolt = <2600000>; +- bias-pull-down; +- }; +- l11 { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- bias-pull-down; +- }; +- l12 { +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- bias-pull-down; +- }; +- l13 { +- regulator-min-microvolt = <2050000>; +- regulator-max-microvolt = <2050000>; +- bias-pull-down; +- }; +- l14 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- l15 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- bias-pull-down; +- }; +- l16 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- bias-pull-down; +- regulator-always-on; +- }; +- l17 { +- // 1.5V according to schematic +- regulator-min-microvolt = <2600000>; +- regulator-max-microvolt = <2600000>; +- bias-pull-down; +- }; +- l18 { +- regulator-min-microvolt = <2200000>; +- regulator-max-microvolt = <2200000>; +- bias-pull-down; +- }; +- l19 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- bias-pull-down; +- }; +- l20 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- bias-pull-down; +- }; +- l21 { +- // 1.1 V according to schematic +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- bias-pull-down; +- regulator-always-on; +- }; +- l22 { +- // 1.2 V according to schematic +- regulator-min-microvolt = <1150000>; +- regulator-max-microvolt = <1150000>; +- bias-pull-down; +- }; +- l23 { +- // Unused +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- bias-pull-down; +- }; +- l24 { +- // Unused +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- bias-pull-down; +- }; +- l25 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- bias-pull-down; +- }; +- +- s0 { +- // regulator-min-microvolt = <500000>; +- // regulator-max-microvolt = <1325000>; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- qcom,switch-mode-frequency = <1600000>; +- bias-pull-down; +- }; +- s1 { +- // regulator-min-microvolt = <500000>; +- // regulator-max-microvolt = <1250000>; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- qcom,switch-mode-frequency = <1600000>; +- bias-pull-down; +- }; +- s2 { +- // 1.3 V according to schematic +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1400000>; +- qcom,switch-mode-frequency = <1600000>; +- bias-pull-down; +- }; +- s3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- qcom,switch-mode-frequency = <1600000>; +- regulator-always-on; +- bias-pull-down; +- }; +- s4 { +- regulator-min-microvolt = <2200000>; +- regulator-max-microvolt = <2200000>; +- qcom,switch-mode-frequency = <1600000>; +- regulator-always-on; +- bias-pull-down; +- }; +- +- /* LVS0 and LVS1 are just switches */ +- lvs0 { +- bias-pull-down; +- }; +- lvs1 { +- bias-pull-down; +- }; +- +- ncp { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- qcom,switch-mode-frequency = <1600000>; +- }; +- }; +- }; +- amba { +- /* Internal 3.69 GiB eMMC */ +- sdcc@12400000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dragon_sdcc1_pins>; +- vmmc-supply = <&pm8901_l5>; +- vqmmc-supply = <&pm8901_lvs0>; +- }; +- +- /* External micro SD card, directly connected, pulled up to 2.85 V */ +- sdcc@12180000 { +- status = "okay"; +- /* Enable SSBI GPIO 22 as input, use for card detect */ +- pinctrl-names = "default"; +- pinctrl-0 = <&dragon_sdcc3_pins>, <&dragon_sdcc3_gpios>; +- cd-gpios = <&pm8058_gpio 22 GPIO_ACTIVE_LOW>; +- wp-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; +- vmmc-supply = <&pm8058_l14>; +- }; +- +- /* +- * Second external micro SD card, using two TXB104RGYR levelshifters +- * to lift from 1.8 V to 2.85 V +- */ +- sdcc@12200000 { +- status = "okay"; +- /* Enable SSBI GPIO 26 as input, use for card detect */ +- pinctrl-names = "default"; +- pinctrl-0 = <&dragon_sdcc5_pins>, <&dragon_sdcc5_gpios>; +- cd-gpios = <&pm8058_gpio 26 GPIO_ACTIVE_LOW>; +- wp-gpios = <&tlmm 106 GPIO_ACTIVE_HIGH>; +- vmmc-supply = <&pm8058_l14>; +- vqmmc-supply = <&dragon_vio_txb>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-apq8064-asus-nexus7-flo.dts b/scripts/dtc/include-prefixes/arm/qcom-apq8064-asus-nexus7-flo.dts +deleted file mode 100644 +index 3bce47d16ab3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-apq8064-asus-nexus7-flo.dts ++++ /dev/null +@@ -1,359 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "qcom-apq8064-v2.0.dtsi" +-#include +-#include +-#include +-/ { +- model = "Asus Nexus7(flo)"; +- compatible = "asus,nexus7-flo", "qcom,apq8064"; +- +- aliases { +- serial0 = &gsbi7_serial; +- serial1 = &gsbi6_serial; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- ramoops@88d00000{ +- compatible = "ramoops"; +- reg = <0x88d00000 0x100000>; +- record-size = <0x00020000>; +- console-size = <0x00020000>; +- ftrace-size = <0x00020000>; +- }; +- }; +- +- ext_3p3v: regulator-fixed@1 { +- compatible = "regulator-fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "ext_3p3v"; +- regulator-type = "voltage"; +- startup-delay-us = <0>; +- gpio = <&tlmm_pinmux 77 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-boot-on; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- volume_up { +- label = "Volume Up"; +- gpios = <&pm8921_gpio 4 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- }; +- volume_down { +- label = "Volume Down"; +- gpios = <&pm8921_gpio 38 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- }; +- }; +- +- soc { +- rpm@108000 { +- regulators { +- vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; +- vin_lvs1_3_6-supply = <&pm8921_s4>; +- vin_lvs4_5_7-supply = <&pm8921_s4>; +- +- +- vdd_l24-supply = <&pm8921_s1>; +- vdd_l25-supply = <&pm8921_s1>; +- vin_lvs2-supply = <&pm8921_s1>; +- +- vdd_l26-supply = <&pm8921_s7>; +- vdd_l27-supply = <&pm8921_s7>; +- vdd_l28-supply = <&pm8921_s7>; +- +- vdd_ncp-supply = <&pm8921_l6>; +- +- /* Buck SMPS */ +- s1 { +- regulator-always-on; +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- qcom,switch-mode-frequency = <3200000>; +- bias-pull-down; +- }; +- +- /* msm otg HSUSB_VDDCX */ +- s3 { +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1150000>; +- qcom,switch-mode-frequency = <4800000>; +- }; +- +- /* +- * msm_sdcc.1-sdc-vdd_io +- * tabla2x-slim-CDC_VDDA_RX +- * tabla2x-slim-CDC_VDDA_TX +- * tabla2x-slim-CDC_VDD_CP +- * tabla2x-slim-VDDIO_CDC +- */ +- s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- qcom,switch-mode-frequency = <3200000>; +- regulator-always-on; +- }; +- +- s7 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- qcom,switch-mode-frequency = <3200000>; +- }; +- +- /* mipi_dsi.1-dsi1_pll_vdda */ +- l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- /* msm_otg-HSUSB_3p3 */ +- l3 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- bias-pull-down; +- }; +- +- /* msm_otg-HSUSB_1p8 */ +- l4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- bias-pull-down; +- }; +- +- /* msm_sdcc.1-sdc_vdd */ +- l5 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- regulator-always-on; +- bias-pull-down; +- }; +- +- l6 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- /* mipi_dsi.1-dsi1_avdd */ +- l11 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- bias-pull-down; +- regulator-always-on; +- }; +- +- /* pwm_power for backlight */ +- l17 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- +- /* camera, qdsp6 */ +- l23 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- bias-pull-down; +- }; +- +- /* +- * tabla2x-slim-CDC_VDDA_A_1P2V +- * tabla2x-slim-VDDD_CDC_D +- */ +- l25 { +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- bias-pull-down; +- }; +- +- lvs1 { +- bias-pull-down; +- }; +- +- lvs4 { +- bias-pull-down; +- }; +- +- lvs5 { +- bias-pull-down; +- }; +- +- lvs6 { +- bias-pull-down; +- }; +- /* +- * mipi_dsi.1-dsi1_vddio +- * pil_riva-pll_vdd +- */ +- lvs7 { +- bias-pull-down; +- }; +- }; +- }; +- +- mdp@5100000 { +- status = "okay"; +- ports { +- port@1 { +- mdp_dsi1_out: endpoint { +- remote-endpoint = <&dsi0_in>; +- }; +- }; +- }; +- }; +- +- dsi0: mdss_dsi@4700000 { +- status = "okay"; +- vdda-supply = <&pm8921_l2>;/*VDD_MIPI1 to 4*/ +- vdd-supply = <&pm8921_l8>; +- vddio-supply = <&pm8921_lvs7>; +- avdd-supply = <&pm8921_l11>; +- vcss-supply = <&ext_3p3v>; +- +- panel@0 { +- reg = <0>; +- compatible = "jdi,lt070me05000"; +- +- vddp-supply = <&pm8921_l17>; +- iovcc-supply = <&pm8921_lvs7>; +- +- enable-gpios = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&tlmm_pinmux 54 GPIO_ACTIVE_LOW>; +- dcdc-en-gpios = <&pm8921_gpio 23 GPIO_ACTIVE_HIGH>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&dsi0_out>; +- }; +- }; +- }; +- ports { +- port@0 { +- dsi0_in: endpoint { +- remote-endpoint = <&mdp_dsi1_out>; +- }; +- }; +- +- port@1 { +- dsi0_out: endpoint { +- remote-endpoint = <&panel_in>; +- data-lanes = <0 1 2 3>; +- }; +- }; +- }; +- }; +- +- dsi-phy@4700200 { +- status = "okay"; +- vddio-supply = <&pm8921_lvs7>;/*VDD_PLL2_1 to 7*/ +- }; +- +- gsbi@16200000 { +- status = "okay"; +- qcom,mode = ; +- i2c@16280000 { +- status = "okay"; +- clock-frequency = <200000>; +- pinctrl-0 = <&i2c3_pins>; +- pinctrl-names = "default"; +- +- trackpad@10 { +- compatible = "elan,ekth3500"; +- reg = <0x10>; +- interrupt-parent = <&tlmm_pinmux>; +- interrupts = <6 IRQ_TYPE_EDGE_FALLING>; +- }; +- }; +- }; +- +- +- gsbi@12440000 { +- status = "okay"; +- qcom,mode = ; +- +- i2c@12460000 { +- status = "okay"; +- clock-frequency = <200000>; +- pinctrl-0 = <&i2c1_pins>; +- pinctrl-names = "default"; +- +- eeprom@52 { +- compatible = "atmel,24c128"; +- reg = <0x52>; +- pagesize = <32>; +- }; +- +- bq27541@55 { +- compatible = "ti,bq27541"; +- reg = <0x55>; +- }; +- +- }; +- }; +- +- gsbi@16500000 { +- status = "okay"; +- qcom,mode = ; +- +- serial@16540000 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gsbi6_uart_4pins>; +- }; +- }; +- +- gsbi@16600000 { +- status = "okay"; +- qcom,mode = ; +- serial@16640000 { +- status = "okay"; +- }; +- }; +- +- /* OTG */ +- usb@12500000 { +- status = "okay"; +- dr_mode = "otg"; +- ulpi { +- phy { +- v3p3-supply = <&pm8921_l3>; +- v1p8-supply = <&pm8921_l4>; +- }; +- }; +- }; +- +- amba { +- /* eMMC */ +- sdcc@12400000 { +- status = "okay"; +- vmmc-supply = <&pm8921_l5>; +- vqmmc-supply = <&pm8921_s4>; +- }; +- }; +- +- imem@2a03f000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x2a03f000 0x1000>; +- +- reboot-mode { +- compatible = "syscon-reboot-mode"; +- offset = <0x65c>; +- +- mode-normal = <0x77665501>; +- mode-bootloader = <0x77665500>; +- mode-recovery = <0x77665502>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-apq8064-cm-qs600.dts b/scripts/dtc/include-prefixes/arm/qcom-apq8064-cm-qs600.dts +deleted file mode 100644 +index 0148148a8e0a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-apq8064-cm-qs600.dts ++++ /dev/null +@@ -1,246 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "qcom-apq8064-v2.0.dtsi" +-#include +-#include +- +-/ { +- model = "CompuLab CM-QS600"; +- compatible = "qcom,apq8064-cm-qs600", "qcom,apq8064"; +- +- aliases { +- serial0 = &gsbi7_serial; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- pwrseq { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "simple-bus"; +- +- sdcc4_pwrseq: sdcc4_pwrseq { +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_default_gpios>; +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- soc { +- pinctrl@800000 { +- card_detect: card_detect { +- mux { +- pins = "gpio26"; +- function = "gpio"; +- bias-disable; +- }; +- }; +- +- pcie_pins: pcie_pinmux { +- mux { +- pins = "gpio27"; +- function = "gpio"; +- }; +- conf { +- pins = "gpio27"; +- drive-strength = <12>; +- bias-disable; +- }; +- }; +- }; +- +- rpm@108000 { +- regulators { +- vin_lvs1_3_6-supply = <&pm8921_s4>; +- vin_lvs2-supply = <&pm8921_s1>; +- vin_lvs4_5_7-supply = <&pm8921_s4>; +- +- vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; +- vdd_l24-supply = <&pm8921_s1>; +- vdd_l25-supply = <&pm8921_s1>; +- vdd_l26-supply = <&pm8921_s7>; +- vdd_l27-supply = <&pm8921_s7>; +- vdd_l28-supply = <&pm8921_s7>; +- +- +- /* Buck SMPS */ +- s1 { +- regulator-always-on; +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- qcom,switch-mode-frequency = <3200000>; +- bias-pull-down; +- }; +- +- s3 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- qcom,switch-mode-frequency = <4800000>; +- }; +- +- s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- qcom,switch-mode-frequency = <3200000>; +- }; +- +- s7 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- qcom,switch-mode-frequency = <3200000>; +- }; +- +- l3 { +- regulator-min-microvolt = <3050000>; +- regulator-max-microvolt = <3300000>; +- bias-pull-down; +- }; +- +- l4 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1800000>; +- bias-pull-down; +- }; +- +- l5 { +- regulator-min-microvolt = <2750000>; +- regulator-max-microvolt = <3000000>; +- bias-pull-down; +- }; +- +- l23 { +- regulator-min-microvolt = <1700000>; +- regulator-max-microvolt = <1900000>; +- bias-pull-down; +- }; +- +- pm8921_lvs6: lvs6 { +- bias-pull-down; +- }; +- +- }; +- }; +- +- gsbi@12440000 { +- status = "okay"; +- qcom,mode = ; +- +- i2c@12460000 { +- status = "okay"; +- clock-frequency = <200000>; +- +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <32>; +- }; +- }; +- }; +- +- gsbi@16600000 { +- status = "okay"; +- qcom,mode = ; +- serial@16640000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gsbi7_uart_2pins>; +- }; +- }; +- +- /* OTG */ +- usb@12500000 { +- status = "okay"; +- dr_mode = "otg"; +- ulpi { +- phy { +- v3p3-supply = <&pm8921_l3>; +- v1p8-supply = <&pm8921_l4>; +- }; +- }; +- }; +- +- usb@12520000 { +- status = "okay"; +- dr_mode = "host"; +- ulpi { +- phy { +- v3p3-supply = <&pm8921_l3>; +- v1p8-supply = <&pm8921_l23>; +- }; +- }; +- }; +- +- usb@12530000 { +- status = "okay"; +- dr_mode = "host"; +- ulpi { +- phy { +- v3p3-supply = <&pm8921_l3>; +- v1p8-supply = <&pm8921_l23>; +- }; +- }; +- }; +- +- /* on board fixed 3.3v supply */ +- v3p3_fixed: v3p3 { +- compatible = "regulator-fixed"; +- regulator-name = "PCIE V3P3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- qcom,ssbi@500000 { +- pmic@0 { +- gpio@150 { +- wlan_default_gpios: wlan-gpios { +- pios { +- pins = "gpio43"; +- function = "normal"; +- bias-disable; +- power-source = ; +- }; +- }; +- }; +- }; +- }; +- +- pci@1b500000 { +- status = "okay"; +- vdda-supply = <&pm8921_s3>; +- vdda_phy-supply = <&pm8921_lvs6>; +- vdda_refclk-supply = <&v3p3_fixed>; +- pinctrl-0 = <&pcie_pins>; +- pinctrl-names = "default"; +- perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; +- }; +- +- amba { +- /* eMMC */ +- sdcc1: sdcc@12400000 { +- status = "okay"; +- vmmc-supply = <&pm8921_l5>; +- vqmmc-supply = <&pm8921_s4>; +- }; +- +- /* External micro SD card */ +- sdcc3: sdcc@12180000 { +- status = "okay"; +- vmmc-supply = <&v3p3_fixed>; +- pinctrl-names = "default"; +- pinctrl-0 = <&card_detect>; +- cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; +- }; +- /* WLAN */ +- sdcc4: sdcc@121c0000 { +- status = "okay"; +- vmmc-supply = <&v3p3_fixed>; +- vqmmc-supply = <&v3p3_fixed>; +- mmc-pwrseq = <&sdcc4_pwrseq>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-apq8064-ifc6410.dts b/scripts/dtc/include-prefixes/arm/qcom-apq8064-ifc6410.dts +deleted file mode 100644 +index d0a17b5a5fa3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-apq8064-ifc6410.dts ++++ /dev/null +@@ -1,381 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "qcom-apq8064-v2.0.dtsi" +-#include +-#include +- +-/ { +- model = "Qualcomm APQ8064/IFC6410"; +- compatible = "qcom,apq8064-ifc6410", "qcom,apq8064"; +- +- aliases { +- serial0 = &gsbi7_serial; +- serial1 = &gsbi6_serial; +- i2c0 = &gsbi1_i2c; +- i2c1 = &gsbi2_i2c; +- i2c2 = &gsbi3_i2c; +- i2c3 = &gsbi4_i2c; +- spi0 = &gsbi5_spi; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- pwrseq { +- compatible = "simple-bus"; +- +- sdcc4_pwrseq: sdcc4_pwrseq { +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_default_gpios>; +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <¬ify_led>; +- +- led@1 { +- label = "apq8064:green:user1"; +- gpios = <&pm8921_gpio 18 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "d"; +- +- port { +- hdmi_con: endpoint { +- remote-endpoint = <&hdmi_out>; +- }; +- }; +- }; +- +- soc { +- pinctrl@800000 { +- card_detect: card_detect { +- mux { +- pins = "gpio26"; +- function = "gpio"; +- bias-disable; +- }; +- }; +- +- pcie_pins: pcie_pinmux { +- mux { +- pins = "gpio27"; +- function = "gpio"; +- }; +- conf { +- pins = "gpio27"; +- drive-strength = <12>; +- bias-disable; +- }; +- }; +- }; +- +- rpm@108000 { +- regulators { +- vin_lvs1_3_6-supply = <&pm8921_s4>; +- vin_lvs2-supply = <&pm8921_s1>; +- vin_lvs4_5_7-supply = <&pm8921_s4>; +- +- vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; +- vdd_l24-supply = <&pm8921_s1>; +- vdd_l25-supply = <&pm8921_s1>; +- vdd_l26-supply = <&pm8921_s7>; +- vdd_l27-supply = <&pm8921_s7>; +- vdd_l28-supply = <&pm8921_s7>; +- +- +- /* Buck SMPS */ +- s1 { +- regulator-always-on; +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- qcom,switch-mode-frequency = <3200000>; +- bias-pull-down; +- }; +- +- s3 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- qcom,switch-mode-frequency = <4800000>; +- }; +- +- s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- qcom,switch-mode-frequency = <3200000>; +- }; +- +- s7 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- qcom,switch-mode-frequency = <3200000>; +- }; +- +- l3 { +- regulator-min-microvolt = <3050000>; +- regulator-max-microvolt = <3300000>; +- bias-pull-down; +- }; +- +- l4 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1800000>; +- bias-pull-down; +- }; +- +- l5 { +- regulator-min-microvolt = <2750000>; +- regulator-max-microvolt = <3000000>; +- bias-pull-down; +- }; +- +- l6 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- bias-pull-down; +- }; +- +- l23 { +- regulator-min-microvolt = <1700000>; +- regulator-max-microvolt = <1900000>; +- bias-pull-down; +- }; +- +- lvs1 { +- bias-pull-down; +- }; +- +- lvs6 { +- bias-pull-down; +- }; +- }; +- }; +- +- ext_3p3v: regulator-fixed@1 { +- compatible = "regulator-fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "ext_3p3v"; +- regulator-type = "voltage"; +- startup-delay-us = <0>; +- gpio = <&tlmm_pinmux 77 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-boot-on; +- }; +- +- gsbi3: gsbi@16200000 { +- status = "okay"; +- qcom,mode = ; +- i2c@16280000 { +- status = "okay"; +- }; +- }; +- +- gsbi@16300000 { +- status = "okay"; +- qcom,mode = ; +- /* CAM I2C MIPI-CSI connector */ +- i2c@16380000 { +- status = "okay"; +- }; +- }; +- +- gsbi@12440000 { +- status = "okay"; +- qcom,mode = ; +- +- i2c@12460000 { +- status = "okay"; +- clock-frequency = <200000>; +- +- eeprom@52 { +- compatible = "atmel,24c128"; +- reg = <0x52>; +- pagesize = <32>; +- }; +- }; +- }; +- +- gsbi@1a200000 { +- qcom,mode = ; +- status = "okay"; +- spi4: spi@1a280000 { +- status = "okay"; +- num-cs = <1>; +- cs-gpios = <&tlmm_pinmux 53 0>; +- }; +- }; +- +- gsbi@16500000 { +- status = "okay"; +- qcom,mode = ; +- +- serial@16540000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gsbi6_uart_4pins>; +- }; +- }; +- +- gsbi@16600000 { +- status = "okay"; +- qcom,mode = ; +- serial@16640000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gsbi7_uart_2pins>; +- }; +- }; +- +- sata_phy0: phy@1b400000 { +- status = "okay"; +- }; +- +- sata0: sata@29000000 { +- status = "okay"; +- target-supply = <&pm8921_s4>; +- }; +- +- /* OTG */ +- usb@12500000 { +- status = "okay"; +- dr_mode = "otg"; +- ulpi { +- phy { +- v3p3-supply = <&pm8921_l3>; +- v1p8-supply = <&pm8921_l4>; +- }; +- }; +- }; +- +- usb@12520000 { +- status = "okay"; +- dr_mode = "host"; +- ulpi { +- phy { +- v3p3-supply = <&pm8921_l3>; +- v1p8-supply = <&pm8921_l23>; +- }; +- }; +- }; +- +- usb@12530000 { +- status = "okay"; +- dr_mode = "host"; +- ulpi { +- phy { +- v3p3-supply = <&pm8921_l3>; +- v1p8-supply = <&pm8921_l23>; +- }; +- }; +- }; +- +- pci@1b500000 { +- status = "okay"; +- vdda-supply = <&pm8921_s3>; +- vdda_phy-supply = <&pm8921_lvs6>; +- vdda_refclk-supply = <&ext_3p3v>; +- pinctrl-0 = <&pcie_pins>; +- pinctrl-names = "default"; +- perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; +- }; +- +- qcom,ssbi@500000 { +- pmic@0 { +- gpio@150 { +- wlan_default_gpios: wlan-gpios { +- pios { +- pins = "gpio43"; +- function = "normal"; +- bias-disable; +- power-source = ; +- }; +- }; +- +- notify_led: nled { +- pios { +- pins = "gpio18"; +- function = "normal"; +- bias-disable; +- power-source = ; +- }; +- }; +- }; +- }; +- }; +- +- amba { +- /* eMMC */ +- sdcc1: sdcc@12400000 { +- status = "okay"; +- vmmc-supply = <&pm8921_l5>; +- vqmmc-supply = <&pm8921_s4>; +- }; +- +- /* External micro SD card */ +- sdcc3: sdcc@12180000 { +- status = "okay"; +- vmmc-supply = <&pm8921_l6>; +- pinctrl-names = "default"; +- pinctrl-0 = <&card_detect>; +- cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; +- }; +- /* WLAN */ +- sdcc4: sdcc@121c0000 { +- status = "okay"; +- vmmc-supply = <&ext_3p3v>; +- vqmmc-supply = <&pm8921_lvs1>; +- mmc-pwrseq = <&sdcc4_pwrseq>; +- }; +- }; +- +- hdmi-tx@4a00000 { +- status = "okay"; +- +- core-vdda-supply = <&pm8921_hdmi_switch>; +- hdmi-mux-supply = <&ext_3p3v>; +- +- hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>; +- +- ports { +- port@0 { +- endpoint { +- remote-endpoint = <&mdp_dtv_out>; +- }; +- }; +- +- port@1 { +- endpoint { +- remote-endpoint = <&hdmi_con>; +- }; +- }; +- }; +- }; +- +- hdmi-phy@4a00400 { +- status = "okay"; +- +- core-vdda-supply = <&pm8921_hdmi_switch>; +- }; +- +- mdp@5100000 { +- status = "okay"; +- +- ports { +- port@3 { +- endpoint { +- remote-endpoint = <&hdmi_in>; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-apq8064-pins.dtsi b/scripts/dtc/include-prefixes/arm/qcom-apq8064-pins.dtsi +deleted file mode 100644 +index cbe42c4153a0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-apq8064-pins.dtsi ++++ /dev/null +@@ -1,325 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-&tlmm_pinmux { +- sdc4_gpios: sdc4-gpios { +- pios { +- pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; +- function = "sdc4"; +- }; +- }; +- +- sdcc1_pins: sdcc1-pin-active { +- clk { +- pins = "sdc1_clk"; +- drive-strengh = <16>; +- bias-disable; +- }; +- +- cmd { +- pins = "sdc1_cmd"; +- drive-strengh = <10>; +- bias-pull-up; +- }; +- +- data { +- pins = "sdc1_data"; +- drive-strengh = <10>; +- bias-pull-up; +- }; +- }; +- +- sdcc3_pins: sdcc3-pin-active { +- clk { +- pins = "sdc3_clk"; +- drive-strengh = <8>; +- bias-disable; +- }; +- +- cmd { +- pins = "sdc3_cmd"; +- drive-strengh = <8>; +- bias-pull-up; +- }; +- +- data { +- pins = "sdc3_data"; +- drive-strengh = <8>; +- bias-pull-up; +- }; +- }; +- +- ps_hold: ps_hold { +- mux { +- pins = "gpio78"; +- function = "ps_hold"; +- }; +- }; +- +- i2c1_pins: i2c1 { +- mux { +- pins = "gpio20", "gpio21"; +- function = "gsbi1"; +- }; +- +- pinconf { +- pins = "gpio20", "gpio21"; +- drive-strength = <16>; +- bias-disable; +- }; +- }; +- +- i2c1_pins_sleep: i2c1_pins_sleep { +- mux { +- pins = "gpio20", "gpio21"; +- function = "gpio"; +- }; +- pinconf { +- pins = "gpio20", "gpio21"; +- drive-strength = <2>; +- bias-disable = <0>; +- }; +- }; +- +- gsbi1_uart_2pins: gsbi1_uart_2pins { +- mux { +- pins = "gpio18", "gpio19"; +- function = "gsbi1"; +- }; +- }; +- +- gsbi1_uart_4pins: gsbi1_uart_4pins { +- mux { +- pins = "gpio18", "gpio19", "gpio20", "gpio21"; +- function = "gsbi1"; +- }; +- }; +- +- i2c2_pins: i2c2 { +- mux { +- pins = "gpio24", "gpio25"; +- function = "gsbi2"; +- }; +- +- pinconf { +- pins = "gpio24", "gpio25"; +- drive-strength = <16>; +- bias-disable; +- }; +- }; +- +- i2c2_pins_sleep: i2c2_pins_sleep { +- mux { +- pins = "gpio24", "gpio25"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio24", "gpio25"; +- drive-strength = <2>; +- bias-disable = <0>; +- }; +- }; +- +- i2c3_pins: i2c3 { +- mux { +- pins = "gpio8", "gpio9"; +- function = "gsbi3"; +- }; +- +- pinconf { +- pins = "gpio8", "gpio9"; +- drive-strength = <16>; +- bias-disable; +- }; +- }; +- +- i2c3_pins_sleep: i2c3_pins_sleep { +- mux { +- pins = "gpio8", "gpio9"; +- function = "gpio"; +- }; +- pinconf { +- pins = "gpio8", "gpio9"; +- drive-strength = <2>; +- bias-disable = <0>; +- }; +- }; +- +- i2c4_pins: i2c4 { +- mux { +- pins = "gpio12", "gpio13"; +- function = "gsbi4"; +- }; +- +- pinconf { +- pins = "gpio12", "gpio13"; +- drive-strength = <16>; +- bias-disable; +- }; +- }; +- +- i2c4_pins_sleep: i2c4_pins_sleep { +- mux { +- pins = "gpio12", "gpio13"; +- function = "gpio"; +- }; +- pinconf { +- pins = "gpio12", "gpio13"; +- drive-strength = <2>; +- bias-disable = <0>; +- }; +- }; +- +- spi5_default: spi5_default { +- pinmux { +- pins = "gpio51", "gpio52", "gpio54"; +- function = "gsbi5"; +- }; +- +- pinmux_cs { +- function = "gpio"; +- pins = "gpio53"; +- }; +- +- pinconf { +- pins = "gpio51", "gpio52", "gpio54"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- pinconf_cs { +- pins = "gpio53"; +- drive-strength = <16>; +- bias-disable; +- output-high; +- }; +- }; +- +- spi5_sleep: spi5_sleep { +- pinmux { +- function = "gpio"; +- pins = "gpio51", "gpio52", "gpio53", "gpio54"; +- }; +- +- pinconf { +- pins = "gpio51", "gpio52", "gpio53", "gpio54"; +- drive-strength = <2>; +- bias-pull-down; +- }; +- }; +- +- i2c6_pins: i2c6 { +- mux { +- pins = "gpio16", "gpio17"; +- function = "gsbi6"; +- }; +- +- pinconf { +- pins = "gpio16", "gpio17"; +- drive-strength = <16>; +- bias-disable; +- }; +- }; +- +- i2c6_pins_sleep: i2c6_pins_sleep { +- mux { +- pins = "gpio16", "gpio17"; +- function = "gpio"; +- }; +- pinconf { +- pins = "gpio16", "gpio17"; +- drive-strength = <2>; +- bias-disable = <0>; +- }; +- }; +- +- gsbi6_uart_2pins: gsbi6_uart_2pins { +- mux { +- pins = "gpio14", "gpio15"; +- function = "gsbi6"; +- }; +- }; +- +- gsbi6_uart_4pins: gsbi6_uart_4pins { +- mux { +- pins = "gpio14", "gpio15", "gpio16", "gpio17"; +- function = "gsbi6"; +- }; +- }; +- +- gsbi7_uart_2pins: gsbi7_uart_2pins { +- mux { +- pins = "gpio82", "gpio83"; +- function = "gsbi7"; +- }; +- }; +- +- gsbi7_uart_4pins: gsbi7_uart_4pins { +- mux { +- pins = "gpio82", "gpio83", "gpio84", "gpio85"; +- function = "gsbi7"; +- }; +- }; +- +- i2c7_pins: i2c7 { +- mux { +- pins = "gpio84", "gpio85"; +- function = "gsbi7"; +- }; +- +- pinconf { +- pins = "gpio84", "gpio85"; +- drive-strength = <16>; +- bias-disable; +- }; +- }; +- +- i2c7_pins_sleep: i2c7_pins_sleep { +- mux { +- pins = "gpio84", "gpio85"; +- function = "gpio"; +- }; +- pinconf { +- pins = "gpio84", "gpio85"; +- drive-strength = <2>; +- bias-disable = <0>; +- }; +- }; +- +- riva_fm_pin_a: riva-fm-active { +- pins = "gpio14", "gpio15"; +- function = "riva_fm"; +- }; +- +- riva_bt_pin_a: riva-bt-active { +- pins = "gpio16", "gpio17"; +- function = "riva_bt"; +- }; +- +- riva_wlan_pin_a: riva-wlan-active { +- pins = "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; +- function = "riva_wlan"; +- +- drive-strength = <6>; +- bias-pull-down; +- }; +- +- hdmi_pinctrl: hdmi-pinctrl { +- mux { +- pins = "gpio70", "gpio71", "gpio72"; +- function = "hdmi"; +- }; +- +- pinconf_ddc { +- pins = "gpio70", "gpio71"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- pinconf_hpd { +- pins = "gpio72"; +- bias-pull-down; +- drive-strength = <16>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-apq8064-sony-xperia-yuga.dts b/scripts/dtc/include-prefixes/arm/qcom-apq8064-sony-xperia-yuga.dts +deleted file mode 100644 +index 72e47bdc5c12..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-apq8064-sony-xperia-yuga.dts ++++ /dev/null +@@ -1,402 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "qcom-apq8064-v2.0.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "Sony Xperia Z"; +- compatible = "sony,xperia-yuga", "qcom,apq8064"; +- +- aliases { +- serial0 = &gsbi5_serial; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- input-name = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_pin_a>; +- +- camera-focus { +- label = "camera_focus"; +- gpios = <&pm8921_gpio 3 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- }; +- +- camera-snapshot { +- label = "camera_snapshot"; +- gpios = <&pm8921_gpio 4 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- }; +- +- volume-down { +- label = "volume_down"; +- gpios = <&pm8921_gpio 29 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- }; +- +- volume-up { +- label = "volume_up"; +- gpios = <&pm8921_gpio 35 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- }; +- }; +- +- soc { +- pinctrl@800000 { +- gsbi5_uart_pin_a: gsbi5-uart-pin-active { +- rx { +- pins = "gpio52"; +- function = "gsbi5"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- tx { +- pins = "gpio51"; +- function = "gsbi5"; +- drive-strength = <4>; +- bias-disable; +- }; +- }; +- +- +- sdcc3_cd_pin_a: sdcc3-cd-pin-active { +- pins = "gpio26"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- +- rpm@108000 { +- regulators { +- vin_l1_l2_l12_l18-supply = <&pm8921_s4>; +- vin_lvs_1_3_6-supply = <&pm8921_s4>; +- vin_lvs_4_5_7-supply = <&pm8921_s4>; +- vin_ncp-supply = <&pm8921_l6>; +- vin_lvs2-supply = <&pm8921_s4>; +- vin_l24-supply = <&pm8921_s1>; +- vin_l25-supply = <&pm8921_s1>; +- vin_l27-supply = <&pm8921_s7>; +- vin_l28-supply = <&pm8921_s7>; +- +- /* Buck SMPS */ +- s1 { +- regulator-always-on; +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- qcom,switch-mode-frequency = <3200000>; +- bias-pull-down; +- }; +- +- s2 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- qcom,switch-mode-frequency = <1600000>; +- bias-pull-down; +- }; +- +- s3 { +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1150000>; +- qcom,switch-mode-frequency = <4800000>; +- bias-pull-down; +- }; +- +- s4 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- qcom,switch-mode-frequency = <1600000>; +- bias-pull-down; +- qcom,force-mode = ; +- }; +- +- s7 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- qcom,switch-mode-frequency = <3200000>; +- }; +- +- s8 { +- regulator-min-microvolt = <2200000>; +- regulator-max-microvolt = <2200000>; +- qcom,switch-mode-frequency = <1600000>; +- }; +- +- /* PMOS LDO */ +- l1 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- bias-pull-down; +- }; +- +- l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- bias-pull-down; +- }; +- +- l3 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- bias-pull-down; +- }; +- +- l4 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- bias-pull-down; +- }; +- +- l5 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- bias-pull-down; +- }; +- +- l6 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- bias-pull-down; +- }; +- +- l7 { +- regulator-min-microvolt = <1850000>; +- regulator-max-microvolt = <2950000>; +- bias-pull-down; +- }; +- +- l8 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- bias-pull-down; +- }; +- +- l9 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- bias-pull-down; +- }; +- +- l10 { +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- bias-pull-down; +- }; +- +- l11 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- bias-pull-down; +- }; +- +- l12 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- bias-pull-down; +- }; +- +- l14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- bias-pull-down; +- }; +- +- l15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- bias-pull-down; +- }; +- +- l16 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- bias-pull-down; +- }; +- +- l17 { +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- bias-pull-down; +- }; +- +- l18 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- bias-pull-down; +- }; +- +- l21 { +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- bias-pull-down; +- }; +- +- l22 { +- regulator-min-microvolt = <2600000>; +- regulator-max-microvolt = <2600000>; +- bias-pull-down; +- }; +- +- l23 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- bias-pull-down; +- }; +- +- l24 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1150000>; +- bias-pull-down; +- }; +- +- l25 { +- regulator-always-on; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- bias-pull-down; +- }; +- +- l27 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- l28 { +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- bias-pull-down; +- }; +- +- l29 { +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- bias-pull-down; +- }; +- +- /* Low Voltage Switch */ +- lvs1 { +- bias-pull-down; +- }; +- +- lvs2 { +- bias-pull-down; +- }; +- +- lvs3 { +- bias-pull-down; +- }; +- +- lvs4 { +- bias-pull-down; +- }; +- +- lvs5 { +- bias-pull-down; +- }; +- +- lvs6 { +- bias-pull-down; +- }; +- +- lvs7 { +- bias-pull-down; +- }; +- +- usb-switch {}; +- +- hdmi-switch {}; +- +- ncp { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- qcom,switch-mode-frequency = <1600000>; +- }; +- }; +- }; +- +- qcom,ssbi@500000 { +- pmic@0 { +- gpio@150 { +- gpio_keys_pin_a: gpio-keys-pin-active { +- pins = "gpio3", "gpio4", "gpio29", "gpio35"; +- function = "normal"; +- +- bias-pull-up; +- drive-push-pull; +- input-enable; +- power-source = <2>; +- qcom,drive-strength = ; +- qcom,pull-up-strength = <0>; +- }; +- }; +- }; +- }; +- +- usb@12500000 { +- status = "okay"; +- dr_mode = "otg"; +- ulpi { +- phy { +- v3p3-supply = <&pm8921_l3>; +- v1p8-supply = <&pm8921_l4>; +- }; +- }; +- }; +- +- gsbi@1a200000 { +- status = "okay"; +- qcom,mode = ; +- +- serial@1a240000 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gsbi5_uart_pin_a>; +- }; +- }; +- +- amba { +- sdcc1: sdcc@12400000 { +- status = "okay"; +- +- vmmc-supply = <&pm8921_l5>; +- vqmmc-supply = <&pm8921_s4>; +- }; +- +- sdcc3: sdcc@12180000 { +- status = "okay"; +- +- vmmc-supply = <&pm8921_l6>; +- cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdcc3_pins>, <&sdcc3_cd_pin_a>; +- }; +- }; +- +- riva-pil@3204000 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-apq8064-v2.0.dtsi b/scripts/dtc/include-prefixes/arm/qcom-apq8064-v2.0.dtsi +deleted file mode 100644 +index 46ed48f0244f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-apq8064-v2.0.dtsi ++++ /dev/null +@@ -1,2 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "qcom-apq8064.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/qcom-apq8064.dtsi b/scripts/dtc/include-prefixes/arm/qcom-apq8064.dtsi +deleted file mode 100644 +index d1c1c6aab2b8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-apq8064.dtsi ++++ /dev/null +@@ -1,1764 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Qualcomm APQ8064"; +- compatible = "qcom,apq8064"; +- interrupt-parent = <&intc>; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- smem_region: smem@80000000 { +- reg = <0x80000000 0x200000>; +- no-map; +- }; +- +- wcnss_mem: wcnss@8f000000 { +- reg = <0x8f000000 0x700000>; +- no-map; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- CPU0: cpu@0 { +- compatible = "qcom,krait"; +- enable-method = "qcom,kpss-acc-v1"; +- device_type = "cpu"; +- reg = <0>; +- next-level-cache = <&L2>; +- qcom,acc = <&acc0>; +- qcom,saw = <&saw0>; +- cpu-idle-states = <&CPU_SPC>; +- }; +- +- CPU1: cpu@1 { +- compatible = "qcom,krait"; +- enable-method = "qcom,kpss-acc-v1"; +- device_type = "cpu"; +- reg = <1>; +- next-level-cache = <&L2>; +- qcom,acc = <&acc1>; +- qcom,saw = <&saw1>; +- cpu-idle-states = <&CPU_SPC>; +- }; +- +- CPU2: cpu@2 { +- compatible = "qcom,krait"; +- enable-method = "qcom,kpss-acc-v1"; +- device_type = "cpu"; +- reg = <2>; +- next-level-cache = <&L2>; +- qcom,acc = <&acc2>; +- qcom,saw = <&saw2>; +- cpu-idle-states = <&CPU_SPC>; +- }; +- +- CPU3: cpu@3 { +- compatible = "qcom,krait"; +- enable-method = "qcom,kpss-acc-v1"; +- device_type = "cpu"; +- reg = <3>; +- next-level-cache = <&L2>; +- qcom,acc = <&acc3>; +- qcom,saw = <&saw3>; +- cpu-idle-states = <&CPU_SPC>; +- }; +- +- L2: l2-cache { +- compatible = "cache"; +- cache-level = <2>; +- }; +- +- idle-states { +- CPU_SPC: spc { +- compatible = "qcom,idle-state-spc", +- "arm,idle-state"; +- entry-latency-us = <400>; +- exit-latency-us = <900>; +- min-residency-us = <3000>; +- }; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; +- }; +- +- thermal-zones { +- cpu-thermal0 { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&gcc 7>; +- coefficients = <1199 0>; +- +- trips { +- cpu_alert0: trip0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu_crit0: trip1 { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu-thermal1 { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&gcc 8>; +- coefficients = <1132 0>; +- +- trips { +- cpu_alert1: trip0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu_crit1: trip1 { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu-thermal2 { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&gcc 9>; +- coefficients = <1199 0>; +- +- trips { +- cpu_alert2: trip0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu_crit2: trip1 { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu-thermal3 { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&gcc 10>; +- coefficients = <1132 0>; +- +- trips { +- cpu_alert3: trip0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu_crit3: trip1 { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- cpu-pmu { +- compatible = "qcom,krait-pmu"; +- interrupts = <1 10 0x304>; +- }; +- +- clocks { +- cxo_board: cxo_board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <19200000>; +- }; +- +- pxo_board: pxo_board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- }; +- +- sleep_clk: sleep_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- }; +- +- sfpb_mutex: hwmutex { +- compatible = "qcom,sfpb-mutex"; +- syscon = <&sfpb_wrapper_mutex 0x604 0x4>; +- #hwlock-cells = <1>; +- }; +- +- smem { +- compatible = "qcom,smem"; +- memory-region = <&smem_region>; +- +- hwlocks = <&sfpb_mutex 3>; +- }; +- +- smd { +- compatible = "qcom,smd"; +- +- modem@0 { +- interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; +- +- qcom,ipc = <&l2cc 8 3>; +- qcom,smd-edge = <0>; +- +- status = "disabled"; +- }; +- +- q6@1 { +- interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; +- +- qcom,ipc = <&l2cc 8 15>; +- qcom,smd-edge = <1>; +- +- status = "disabled"; +- }; +- +- dsps@3 { +- interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; +- +- qcom,ipc = <&sps_sic_non_secure 0x4080 0>; +- qcom,smd-edge = <3>; +- +- status = "disabled"; +- }; +- +- riva@6 { +- interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; +- +- qcom,ipc = <&l2cc 8 25>; +- qcom,smd-edge = <6>; +- +- status = "disabled"; +- }; +- }; +- +- smsm { +- compatible = "qcom,smsm"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- qcom,ipc-1 = <&l2cc 8 4>; +- qcom,ipc-2 = <&l2cc 8 14>; +- qcom,ipc-3 = <&l2cc 8 23>; +- qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; +- +- apps_smsm: apps@0 { +- reg = <0>; +- #qcom,smem-state-cells = <1>; +- }; +- +- modem_smsm: modem@1 { +- reg = <1>; +- interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- q6_smsm: q6@2 { +- reg = <2>; +- interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- wcnss_smsm: wcnss@3 { +- reg = <3>; +- interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- dsps_smsm: dsps@4 { +- reg = <4>; +- interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- firmware { +- scm { +- compatible = "qcom,scm-apq8064"; +- +- clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; +- clock-names = "core"; +- }; +- }; +- +- +- /* +- * These channels from the ADC are simply hardware monitors. +- * That is why the ADC is referred to as "HKADC" - HouseKeeping +- * ADC. +- */ +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&xoadc 0x00 0x01>, /* Battery */ +- <&xoadc 0x00 0x02>, /* DC in (charger) */ +- <&xoadc 0x00 0x04>, /* VPH the main system voltage */ +- <&xoadc 0x00 0x0b>, /* Die temperature */ +- <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ +- <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ +- <&xoadc 0x00 0x0e>; /* Charger temperature */ +- }; +- +- soc: soc { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "simple-bus"; +- +- tlmm_pinmux: pinctrl@800000 { +- compatible = "qcom,apq8064-pinctrl"; +- reg = <0x800000 0x4000>; +- +- gpio-controller; +- gpio-ranges = <&tlmm_pinmux 0 0 90>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&ps_hold>; +- }; +- +- sfpb_wrapper_mutex: syscon@1200000 { +- compatible = "syscon"; +- reg = <0x01200000 0x8000>; +- }; +- +- intc: interrupt-controller@2000000 { +- compatible = "qcom,msm-qgic2"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x02000000 0x1000>, +- <0x02002000 0x1000>; +- }; +- +- timer@200a000 { +- compatible = "qcom,kpss-timer", +- "qcom,kpss-wdt-apq8064", "qcom,msm-timer"; +- interrupts = <1 1 0x301>, +- <1 2 0x301>, +- <1 3 0x301>; +- reg = <0x0200a000 0x100>; +- clock-frequency = <27000000>, +- <32768>; +- cpu-offset = <0x80000>; +- }; +- +- acc0: clock-controller@2088000 { +- compatible = "qcom,kpss-acc-v1"; +- reg = <0x02088000 0x1000>, <0x02008000 0x1000>; +- }; +- +- acc1: clock-controller@2098000 { +- compatible = "qcom,kpss-acc-v1"; +- reg = <0x02098000 0x1000>, <0x02008000 0x1000>; +- }; +- +- acc2: clock-controller@20a8000 { +- compatible = "qcom,kpss-acc-v1"; +- reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; +- }; +- +- acc3: clock-controller@20b8000 { +- compatible = "qcom,kpss-acc-v1"; +- reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; +- }; +- +- saw0: power-controller@2089000 { +- compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; +- reg = <0x02089000 0x1000>, <0x02009000 0x1000>; +- regulator; +- }; +- +- saw1: power-controller@2099000 { +- compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; +- reg = <0x02099000 0x1000>, <0x02009000 0x1000>; +- regulator; +- }; +- +- saw2: power-controller@20a9000 { +- compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; +- reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; +- regulator; +- }; +- +- saw3: power-controller@20b9000 { +- compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; +- reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; +- regulator; +- }; +- +- sps_sic_non_secure: sps-sic-non-secure@12100000 { +- compatible = "syscon"; +- reg = <0x12100000 0x10000>; +- }; +- +- gsbi1: gsbi@12440000 { +- status = "disabled"; +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <1>; +- reg = <0x12440000 0x100>; +- clocks = <&gcc GSBI1_H_CLK>; +- clock-names = "iface"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- syscon-tcsr = <&tcsr>; +- +- gsbi1_serial: serial@12450000 { +- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; +- reg = <0x12450000 0x100>, +- <0x12400000 0x03>; +- interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- gsbi1_i2c: i2c@12460000 { +- compatible = "qcom,i2c-qup-v1.1.1"; +- pinctrl-0 = <&i2c1_pins>; +- pinctrl-1 = <&i2c1_pins_sleep>; +- pinctrl-names = "default", "sleep"; +- reg = <0x12460000 0x1000>; +- interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; +- clock-names = "core", "iface"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- }; +- +- gsbi2: gsbi@12480000 { +- status = "disabled"; +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <2>; +- reg = <0x12480000 0x100>; +- clocks = <&gcc GSBI2_H_CLK>; +- clock-names = "iface"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- syscon-tcsr = <&tcsr>; +- +- gsbi2_i2c: i2c@124a0000 { +- compatible = "qcom,i2c-qup-v1.1.1"; +- reg = <0x124a0000 0x1000>; +- pinctrl-0 = <&i2c2_pins>; +- pinctrl-1 = <&i2c2_pins_sleep>; +- pinctrl-names = "default", "sleep"; +- interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; +- clock-names = "core", "iface"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- gsbi3: gsbi@16200000 { +- status = "disabled"; +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <3>; +- reg = <0x16200000 0x100>; +- clocks = <&gcc GSBI3_H_CLK>; +- clock-names = "iface"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- gsbi3_i2c: i2c@16280000 { +- compatible = "qcom,i2c-qup-v1.1.1"; +- pinctrl-0 = <&i2c3_pins>; +- pinctrl-1 = <&i2c3_pins_sleep>; +- pinctrl-names = "default", "sleep"; +- reg = <0x16280000 0x1000>; +- interrupts = ; +- clocks = <&gcc GSBI3_QUP_CLK>, +- <&gcc GSBI3_H_CLK>; +- clock-names = "core", "iface"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- gsbi4: gsbi@16300000 { +- status = "disabled"; +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <4>; +- reg = <0x16300000 0x03>; +- clocks = <&gcc GSBI4_H_CLK>; +- clock-names = "iface"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gsbi4_i2c: i2c@16380000 { +- compatible = "qcom,i2c-qup-v1.1.1"; +- pinctrl-0 = <&i2c4_pins>; +- pinctrl-1 = <&i2c4_pins_sleep>; +- pinctrl-names = "default", "sleep"; +- reg = <0x16380000 0x1000>; +- interrupts = ; +- clocks = <&gcc GSBI4_QUP_CLK>, +- <&gcc GSBI4_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- }; +- +- gsbi5: gsbi@1a200000 { +- status = "disabled"; +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <5>; +- reg = <0x1a200000 0x03>; +- clocks = <&gcc GSBI5_H_CLK>; +- clock-names = "iface"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gsbi5_serial: serial@1a240000 { +- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; +- reg = <0x1a240000 0x100>, +- <0x1a200000 0x03>; +- interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- gsbi5_spi: spi@1a280000 { +- compatible = "qcom,spi-qup-v1.1.1"; +- reg = <0x1a280000 0x1000>; +- interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; +- pinctrl-0 = <&spi5_default>; +- pinctrl-1 = <&spi5_sleep>; +- pinctrl-names = "default", "sleep"; +- clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- gsbi6: gsbi@16500000 { +- status = "disabled"; +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <6>; +- reg = <0x16500000 0x03>; +- clocks = <&gcc GSBI6_H_CLK>; +- clock-names = "iface"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gsbi6_serial: serial@16540000 { +- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; +- reg = <0x16540000 0x100>, +- <0x16500000 0x03>; +- interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- gsbi6_i2c: i2c@16580000 { +- compatible = "qcom,i2c-qup-v1.1.1"; +- pinctrl-0 = <&i2c6_pins>; +- pinctrl-1 = <&i2c6_pins_sleep>; +- pinctrl-names = "default", "sleep"; +- reg = <0x16580000 0x1000>; +- interrupts = ; +- clocks = <&gcc GSBI6_QUP_CLK>, +- <&gcc GSBI6_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- }; +- +- gsbi7: gsbi@16600000 { +- status = "disabled"; +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <7>; +- reg = <0x16600000 0x100>; +- clocks = <&gcc GSBI7_H_CLK>; +- clock-names = "iface"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- syscon-tcsr = <&tcsr>; +- +- gsbi7_serial: serial@16640000 { +- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; +- reg = <0x16640000 0x1000>, +- <0x16600000 0x1000>; +- interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- gsbi7_i2c: i2c@16680000 { +- compatible = "qcom,i2c-qup-v1.1.1"; +- pinctrl-0 = <&i2c7_pins>; +- pinctrl-1 = <&i2c7_pins_sleep>; +- pinctrl-names = "default", "sleep"; +- reg = <0x16680000 0x1000>; +- interrupts = ; +- clocks = <&gcc GSBI7_QUP_CLK>, +- <&gcc GSBI7_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- }; +- +- rng@1a500000 { +- compatible = "qcom,prng"; +- reg = <0x1a500000 0x200>; +- clocks = <&gcc PRNG_CLK>; +- clock-names = "core"; +- }; +- +- ssbi@c00000 { +- compatible = "qcom,ssbi"; +- reg = <0x00c00000 0x1000>; +- qcom,controller-type = "pmic-arbiter"; +- +- pm8821: pmic@1 { +- compatible = "qcom,pm8821"; +- interrupt-parent = <&tlmm_pinmux>; +- interrupts = <76 IRQ_TYPE_LEVEL_LOW>; +- #interrupt-cells = <2>; +- interrupt-controller; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm8821_mpps: mpps@50 { +- compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp"; +- reg = <0x50>; +- interrupts = <24 IRQ_TYPE_NONE>, +- <25 IRQ_TYPE_NONE>, +- <26 IRQ_TYPE_NONE>, +- <27 IRQ_TYPE_NONE>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +- }; +- +- qcom,ssbi@500000 { +- compatible = "qcom,ssbi"; +- reg = <0x00500000 0x1000>; +- qcom,controller-type = "pmic-arbiter"; +- +- pmicintc: pmic@0 { +- compatible = "qcom,pm8921"; +- interrupt-parent = <&tlmm_pinmux>; +- interrupts = <74 8>; +- #interrupt-cells = <2>; +- interrupt-controller; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm8921_gpio: gpio@150 { +- +- compatible = "qcom,pm8921-gpio", +- "qcom,ssbi-gpio"; +- reg = <0x150>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pm8921_gpio 0 0 44>; +- #gpio-cells = <2>; +- +- }; +- +- pm8921_mpps: mpps@50 { +- compatible = "qcom,pm8921-mpp", +- "qcom,ssbi-mpp"; +- reg = <0x50>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = +- <128 IRQ_TYPE_NONE>, +- <129 IRQ_TYPE_NONE>, +- <130 IRQ_TYPE_NONE>, +- <131 IRQ_TYPE_NONE>, +- <132 IRQ_TYPE_NONE>, +- <133 IRQ_TYPE_NONE>, +- <134 IRQ_TYPE_NONE>, +- <135 IRQ_TYPE_NONE>, +- <136 IRQ_TYPE_NONE>, +- <137 IRQ_TYPE_NONE>, +- <138 IRQ_TYPE_NONE>, +- <139 IRQ_TYPE_NONE>; +- }; +- +- rtc@11d { +- compatible = "qcom,pm8921-rtc"; +- interrupt-parent = <&pmicintc>; +- interrupts = <39 1>; +- reg = <0x11d>; +- allow-set-time; +- }; +- +- pwrkey@1c { +- compatible = "qcom,pm8921-pwrkey"; +- reg = <0x1c>; +- interrupt-parent = <&pmicintc>; +- interrupts = <50 1>, <51 1>; +- debounce = <15625>; +- pull-up; +- }; +- +- xoadc: xoadc@197 { +- compatible = "qcom,pm8921-adc"; +- reg = <197>; +- interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>; +- #address-cells = <2>; +- #size-cells = <0>; +- #io-channel-cells = <2>; +- +- vcoin: adc-channel@0 { +- reg = <0x00 0x00>; +- }; +- vbat: adc-channel@1 { +- reg = <0x00 0x01>; +- }; +- dcin: adc-channel@2 { +- reg = <0x00 0x02>; +- }; +- vph_pwr: adc-channel@4 { +- reg = <0x00 0x04>; +- }; +- batt_therm: adc-channel@8 { +- reg = <0x00 0x08>; +- }; +- batt_id: adc-channel@9 { +- reg = <0x00 0x09>; +- }; +- usb_vbus: adc-channel@a { +- reg = <0x00 0x0a>; +- }; +- die_temp: adc-channel@b { +- reg = <0x00 0x0b>; +- }; +- ref_625mv: adc-channel@c { +- reg = <0x00 0x0c>; +- }; +- ref_1250mv: adc-channel@d { +- reg = <0x00 0x0d>; +- }; +- chg_temp: adc-channel@e { +- reg = <0x00 0x0e>; +- }; +- ref_muxoff: adc-channel@f { +- reg = <0x00 0x0f>; +- }; +- }; +- }; +- }; +- +- qfprom: qfprom@700000 { +- compatible = "qcom,qfprom"; +- reg = <0x00700000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- tsens_calib: calib { +- reg = <0x404 0x10>; +- }; +- tsens_backup: backup_calib { +- reg = <0x414 0x10>; +- }; +- }; +- +- gcc: clock-controller@900000 { +- compatible = "qcom,gcc-apq8064"; +- reg = <0x00900000 0x4000>; +- nvmem-cells = <&tsens_calib>, <&tsens_backup>; +- nvmem-cell-names = "calib", "calib_backup"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #thermal-sensor-cells = <1>; +- }; +- +- lcc: clock-controller@28000000 { +- compatible = "qcom,lcc-apq8064"; +- reg = <0x28000000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- mmcc: clock-controller@4000000 { +- compatible = "qcom,mmcc-apq8064"; +- reg = <0x4000000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- l2cc: clock-controller@2011000 { +- compatible = "syscon"; +- reg = <0x2011000 0x1000>; +- }; +- +- rpm@108000 { +- compatible = "qcom,rpm-apq8064"; +- reg = <0x108000 0x1000>; +- qcom,ipc = <&l2cc 0x8 2>; +- +- interrupts = , +- , +- ; +- interrupt-names = "ack", "err", "wakeup"; +- +- rpmcc: clock-controller { +- compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; +- #clock-cells = <1>; +- }; +- +- regulators { +- compatible = "qcom,rpm-pm8921-regulators"; +- +- pm8921_s1: s1 {}; +- pm8921_s2: s2 {}; +- pm8921_s3: s3 {}; +- pm8921_s4: s4 {}; +- pm8921_s7: s7 {}; +- pm8921_s8: s8 {}; +- +- pm8921_l1: l1 {}; +- pm8921_l2: l2 {}; +- pm8921_l3: l3 {}; +- pm8921_l4: l4 {}; +- pm8921_l5: l5 {}; +- pm8921_l6: l6 {}; +- pm8921_l7: l7 {}; +- pm8921_l8: l8 {}; +- pm8921_l9: l9 {}; +- pm8921_l10: l10 {}; +- pm8921_l11: l11 {}; +- pm8921_l12: l12 {}; +- pm8921_l14: l14 {}; +- pm8921_l15: l15 {}; +- pm8921_l16: l16 {}; +- pm8921_l17: l17 {}; +- pm8921_l18: l18 {}; +- pm8921_l21: l21 {}; +- pm8921_l22: l22 {}; +- pm8921_l23: l23 {}; +- pm8921_l24: l24 {}; +- pm8921_l25: l25 {}; +- pm8921_l26: l26 {}; +- pm8921_l27: l27 {}; +- pm8921_l28: l28 {}; +- pm8921_l29: l29 {}; +- +- pm8921_lvs1: lvs1 {}; +- pm8921_lvs2: lvs2 {}; +- pm8921_lvs3: lvs3 {}; +- pm8921_lvs4: lvs4 {}; +- pm8921_lvs5: lvs5 {}; +- pm8921_lvs6: lvs6 {}; +- pm8921_lvs7: lvs7 {}; +- +- pm8921_usb_switch: usb-switch {}; +- +- pm8921_hdmi_switch: hdmi-switch { +- bias-pull-down; +- }; +- +- pm8921_ncp: ncp {}; +- }; +- }; +- +- usb1: usb@12500000 { +- compatible = "qcom,ci-hdrc"; +- reg = <0x12500000 0x200>, +- <0x12500200 0x200>; +- interrupts = ; +- clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; +- clock-names = "core", "iface"; +- assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; +- assigned-clock-rates = <60000000>; +- resets = <&gcc USB_HS1_RESET>; +- reset-names = "core"; +- phy_type = "ulpi"; +- ahb-burst-config = <0>; +- phys = <&usb_hs1_phy>; +- phy-names = "usb-phy"; +- status = "disabled"; +- #reset-cells = <1>; +- +- ulpi { +- usb_hs1_phy: phy { +- compatible = "qcom,usb-hs-phy-apq8064", +- "qcom,usb-hs-phy"; +- clocks = <&sleep_clk>, <&cxo_board>; +- clock-names = "sleep", "ref"; +- resets = <&usb1 0>; +- reset-names = "por"; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- usb3: usb@12520000 { +- compatible = "qcom,ci-hdrc"; +- reg = <0x12520000 0x200>, +- <0x12520200 0x200>; +- interrupts = ; +- clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>; +- clock-names = "core", "iface"; +- assigned-clocks = <&gcc USB_HS3_XCVR_CLK>; +- assigned-clock-rates = <60000000>; +- resets = <&gcc USB_HS3_RESET>; +- reset-names = "core"; +- phy_type = "ulpi"; +- ahb-burst-config = <0>; +- phys = <&usb_hs3_phy>; +- phy-names = "usb-phy"; +- status = "disabled"; +- #reset-cells = <1>; +- +- ulpi { +- usb_hs3_phy: phy { +- compatible = "qcom,usb-hs-phy-apq8064", +- "qcom,usb-hs-phy"; +- #phy-cells = <0>; +- clocks = <&sleep_clk>, <&cxo_board>; +- clock-names = "sleep", "ref"; +- resets = <&usb3 0>; +- reset-names = "por"; +- }; +- }; +- }; +- +- usb4: usb@12530000 { +- compatible = "qcom,ci-hdrc"; +- reg = <0x12530000 0x200>, +- <0x12530200 0x200>; +- interrupts = ; +- clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>; +- clock-names = "core", "iface"; +- assigned-clocks = <&gcc USB_HS4_XCVR_CLK>; +- assigned-clock-rates = <60000000>; +- resets = <&gcc USB_HS4_RESET>; +- reset-names = "core"; +- phy_type = "ulpi"; +- ahb-burst-config = <0>; +- phys = <&usb_hs4_phy>; +- phy-names = "usb-phy"; +- status = "disabled"; +- #reset-cells = <1>; +- +- ulpi { +- usb_hs4_phy: phy { +- compatible = "qcom,usb-hs-phy-apq8064", +- "qcom,usb-hs-phy"; +- #phy-cells = <0>; +- clocks = <&sleep_clk>, <&cxo_board>; +- clock-names = "sleep", "ref"; +- resets = <&usb4 0>; +- reset-names = "por"; +- }; +- }; +- }; +- +- sata_phy0: phy@1b400000 { +- compatible = "qcom,apq8064-sata-phy"; +- status = "disabled"; +- reg = <0x1b400000 0x200>; +- reg-names = "phy_mem"; +- clocks = <&gcc SATA_PHY_CFG_CLK>; +- clock-names = "cfg"; +- #phy-cells = <0>; +- }; +- +- sata0: sata@29000000 { +- compatible = "qcom,apq8064-ahci", "generic-ahci"; +- status = "disabled"; +- reg = <0x29000000 0x180>; +- interrupts = ; +- +- clocks = <&gcc SFAB_SATA_S_H_CLK>, +- <&gcc SATA_H_CLK>, +- <&gcc SATA_A_CLK>, +- <&gcc SATA_RXOOB_CLK>, +- <&gcc SATA_PMALIVE_CLK>; +- clock-names = "slave_iface", +- "iface", +- "bus", +- "rxoob", +- "core_pmalive"; +- +- assigned-clocks = <&gcc SATA_RXOOB_CLK>, +- <&gcc SATA_PMALIVE_CLK>; +- assigned-clock-rates = <100000000>, <100000000>; +- +- phys = <&sata_phy0>; +- phy-names = "sata-phy"; +- ports-implemented = <0x1>; +- }; +- +- /* Temporary fixed regulator */ +- sdcc1bam:dma@12402000{ +- compatible = "qcom,bam-v1.3.0"; +- reg = <0x12402000 0x8000>; +- interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&gcc SDC1_H_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- }; +- +- sdcc3bam:dma@12182000{ +- compatible = "qcom,bam-v1.3.0"; +- reg = <0x12182000 0x8000>; +- interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&gcc SDC3_H_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- }; +- +- sdcc4bam:dma@121c2000{ +- compatible = "qcom,bam-v1.3.0"; +- reg = <0x121c2000 0x8000>; +- interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&gcc SDC4_H_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- }; +- +- amba { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- sdcc1: sdcc@12400000 { +- status = "disabled"; +- compatible = "arm,pl18x", "arm,primecell"; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdcc1_pins>; +- arm,primecell-periphid = <0x00051180>; +- reg = <0x12400000 0x2000>; +- interrupts = ; +- interrupt-names = "cmd_irq"; +- clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; +- clock-names = "mclk", "apb_pclk"; +- bus-width = <8>; +- max-frequency = <96000000>; +- non-removable; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; +- dma-names = "tx", "rx"; +- }; +- +- sdcc3: sdcc@12180000 { +- compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00051180>; +- status = "disabled"; +- reg = <0x12180000 0x2000>; +- interrupts = ; +- interrupt-names = "cmd_irq"; +- clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; +- clock-names = "mclk", "apb_pclk"; +- bus-width = <4>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <192000000>; +- no-1-8-v; +- dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; +- dma-names = "tx", "rx"; +- }; +- +- sdcc4: sdcc@121c0000 { +- compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00051180>; +- status = "disabled"; +- reg = <0x121c0000 0x2000>; +- interrupts = ; +- interrupt-names = "cmd_irq"; +- clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; +- clock-names = "mclk", "apb_pclk"; +- bus-width = <4>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <48000000>; +- dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdc4_gpios>; +- }; +- }; +- +- tcsr: syscon@1a400000 { +- compatible = "qcom,tcsr-apq8064", "syscon"; +- reg = <0x1a400000 0x100>; +- }; +- +- gpu: adreno-3xx@4300000 { +- compatible = "qcom,adreno-320.2", "qcom,adreno"; +- reg = <0x04300000 0x20000>; +- reg-names = "kgsl_3d0_reg_memory"; +- interrupts = ; +- interrupt-names = "kgsl_3d0_irq"; +- clock-names = +- "core", +- "iface", +- "mem", +- "mem_iface"; +- clocks = +- <&mmcc GFX3D_CLK>, +- <&mmcc GFX3D_AHB_CLK>, +- <&mmcc GFX3D_AXI_CLK>, +- <&mmcc MMSS_IMEM_AHB_CLK>; +- +- iommus = <&gfx3d 0 +- &gfx3d 1 +- &gfx3d 2 +- &gfx3d 3 +- &gfx3d 4 +- &gfx3d 5 +- &gfx3d 6 +- &gfx3d 7 +- &gfx3d 8 +- &gfx3d 9 +- &gfx3d 10 +- &gfx3d 11 +- &gfx3d 12 +- &gfx3d 13 +- &gfx3d 14 +- &gfx3d 15 +- &gfx3d 16 +- &gfx3d 17 +- &gfx3d 18 +- &gfx3d 19 +- &gfx3d 20 +- &gfx3d 21 +- &gfx3d 22 +- &gfx3d 23 +- &gfx3d 24 +- &gfx3d 25 +- &gfx3d 26 +- &gfx3d 27 +- &gfx3d 28 +- &gfx3d 29 +- &gfx3d 30 +- &gfx3d 31 +- &gfx3d1 0 +- &gfx3d1 1 +- &gfx3d1 2 +- &gfx3d1 3 +- &gfx3d1 4 +- &gfx3d1 5 +- &gfx3d1 6 +- &gfx3d1 7 +- &gfx3d1 8 +- &gfx3d1 9 +- &gfx3d1 10 +- &gfx3d1 11 +- &gfx3d1 12 +- &gfx3d1 13 +- &gfx3d1 14 +- &gfx3d1 15 +- &gfx3d1 16 +- &gfx3d1 17 +- &gfx3d1 18 +- &gfx3d1 19 +- &gfx3d1 20 +- &gfx3d1 21 +- &gfx3d1 22 +- &gfx3d1 23 +- &gfx3d1 24 +- &gfx3d1 25 +- &gfx3d1 26 +- &gfx3d1 27 +- &gfx3d1 28 +- &gfx3d1 29 +- &gfx3d1 30 +- &gfx3d1 31>; +- +- qcom,gpu-pwrlevels { +- compatible = "qcom,gpu-pwrlevels"; +- qcom,gpu-pwrlevel@0 { +- qcom,gpu-freq = <450000000>; +- }; +- qcom,gpu-pwrlevel@1 { +- qcom,gpu-freq = <27000000>; +- }; +- }; +- }; +- +- mmss_sfpb: syscon@5700000 { +- compatible = "syscon"; +- reg = <0x5700000 0x70>; +- }; +- +- dsi0: mdss_dsi@4700000 { +- compatible = "qcom,mdss-dsi-ctrl"; +- label = "MDSS DSI CTRL->0"; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- reg = <0x04700000 0x200>; +- reg-names = "dsi_ctrl"; +- +- clocks = <&mmcc DSI_M_AHB_CLK>, +- <&mmcc DSI_S_AHB_CLK>, +- <&mmcc AMP_AHB_CLK>, +- <&mmcc DSI_CLK>, +- <&mmcc DSI1_BYTE_CLK>, +- <&mmcc DSI_PIXEL_CLK>, +- <&mmcc DSI1_ESC_CLK>; +- clock-names = "iface", "bus", "core_mmss", +- "src", "byte", "pixel", +- "core"; +- +- assigned-clocks = <&mmcc DSI1_BYTE_SRC>, +- <&mmcc DSI1_ESC_SRC>, +- <&mmcc DSI_SRC>, +- <&mmcc DSI_PIXEL_SRC>; +- assigned-clock-parents = <&dsi0_phy 0>, +- <&dsi0_phy 0>, +- <&dsi0_phy 1>, +- <&dsi0_phy 1>; +- syscon-sfpb = <&mmss_sfpb>; +- phys = <&dsi0_phy>; +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dsi0_in: endpoint { +- }; +- }; +- +- port@1 { +- reg = <1>; +- dsi0_out: endpoint { +- }; +- }; +- }; +- }; +- +- +- dsi0_phy: dsi-phy@4700200 { +- compatible = "qcom,dsi-phy-28nm-8960"; +- #clock-cells = <1>; +- #phy-cells = <0>; +- +- reg = <0x04700200 0x100>, +- <0x04700300 0x200>, +- <0x04700500 0x5c>; +- reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; +- clock-names = "iface_clk", "ref"; +- clocks = <&mmcc DSI_M_AHB_CLK>, +- <&pxo_board>; +- }; +- +- +- mdp_port0: iommu@7500000 { +- compatible = "qcom,apq8064-iommu"; +- #iommu-cells = <1>; +- clock-names = +- "smmu_pclk", +- "iommu_clk"; +- clocks = +- <&mmcc SMMU_AHB_CLK>, +- <&mmcc MDP_AXI_CLK>; +- reg = <0x07500000 0x100000>; +- interrupts = +- , +- ; +- qcom,ncb = <2>; +- }; +- +- mdp_port1: iommu@7600000 { +- compatible = "qcom,apq8064-iommu"; +- #iommu-cells = <1>; +- clock-names = +- "smmu_pclk", +- "iommu_clk"; +- clocks = +- <&mmcc SMMU_AHB_CLK>, +- <&mmcc MDP_AXI_CLK>; +- reg = <0x07600000 0x100000>; +- interrupts = +- , +- ; +- qcom,ncb = <2>; +- }; +- +- gfx3d: iommu@7c00000 { +- compatible = "qcom,apq8064-iommu"; +- #iommu-cells = <1>; +- clock-names = +- "smmu_pclk", +- "iommu_clk"; +- clocks = +- <&mmcc SMMU_AHB_CLK>, +- <&mmcc GFX3D_AXI_CLK>; +- reg = <0x07c00000 0x100000>; +- interrupts = +- , +- ; +- qcom,ncb = <3>; +- }; +- +- gfx3d1: iommu@7d00000 { +- compatible = "qcom,apq8064-iommu"; +- #iommu-cells = <1>; +- clock-names = +- "smmu_pclk", +- "iommu_clk"; +- clocks = +- <&mmcc SMMU_AHB_CLK>, +- <&mmcc GFX3D_AXI_CLK>; +- reg = <0x07d00000 0x100000>; +- interrupts = +- , +- ; +- qcom,ncb = <3>; +- }; +- +- pcie: pci@1b500000 { +- compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; +- reg = <0x1b500000 0x1000 +- 0x1b502000 0x80 +- 0x1b600000 0x100 +- 0x0ff00000 0x100000>; +- reg-names = "dbi", "elbi", "parf", "config"; +- device_type = "pci"; +- linux,pci-domain = <0>; +- bus-range = <0x00 0xff>; +- num-lanes = <1>; +- #address-cells = <3>; +- #size-cells = <2>; +- ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ +- 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* memory */ +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ +- <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ +- <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ +- <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ +- clocks = <&gcc PCIE_A_CLK>, +- <&gcc PCIE_H_CLK>, +- <&gcc PCIE_PHY_REF_CLK>; +- clock-names = "core", "iface", "phy"; +- resets = <&gcc PCIE_ACLK_RESET>, +- <&gcc PCIE_HCLK_RESET>, +- <&gcc PCIE_POR_RESET>, +- <&gcc PCIE_PCI_RESET>, +- <&gcc PCIE_PHY_RESET>; +- reset-names = "axi", "ahb", "por", "pci", "phy"; +- status = "disabled"; +- }; +- +- hdmi: hdmi-tx@4a00000 { +- compatible = "qcom,hdmi-tx-8960"; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_pinctrl>; +- reg = <0x04a00000 0x2f0>; +- reg-names = "core_physical"; +- interrupts = ; +- clocks = <&mmcc HDMI_APP_CLK>, +- <&mmcc HDMI_M_AHB_CLK>, +- <&mmcc HDMI_S_AHB_CLK>; +- clock-names = "core_clk", +- "master_iface_clk", +- "slave_iface_clk"; +- +- phys = <&hdmi_phy>; +- phy-names = "hdmi-phy"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- hdmi_in: endpoint { +- }; +- }; +- +- port@1 { +- reg = <1>; +- hdmi_out: endpoint { +- }; +- }; +- }; +- }; +- +- hdmi_phy: hdmi-phy@4a00400 { +- compatible = "qcom,hdmi-phy-8960"; +- reg = <0x4a00400 0x60>, +- <0x4a00500 0x100>; +- reg-names = "hdmi_phy", +- "hdmi_pll"; +- +- clocks = <&mmcc HDMI_S_AHB_CLK>; +- clock-names = "slave_iface_clk"; +- #phy-cells = <0>; +- }; +- +- mdp: mdp@5100000 { +- compatible = "qcom,mdp4"; +- reg = <0x05100000 0xf0000>; +- interrupts = ; +- clocks = <&mmcc MDP_CLK>, +- <&mmcc MDP_AHB_CLK>, +- <&mmcc MDP_AXI_CLK>, +- <&mmcc MDP_LUT_CLK>, +- <&mmcc HDMI_TV_CLK>, +- <&mmcc MDP_TV_CLK>; +- clock-names = "core_clk", +- "iface_clk", +- "bus_clk", +- "lut_clk", +- "hdmi_clk", +- "tv_clk"; +- +- iommus = <&mdp_port0 0 +- &mdp_port0 2 +- &mdp_port1 0 +- &mdp_port1 2>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- mdp_lvds_out: endpoint { +- }; +- }; +- +- port@1 { +- reg = <1>; +- mdp_dsi1_out: endpoint { +- }; +- }; +- +- port@2 { +- reg = <2>; +- mdp_dsi2_out: endpoint { +- }; +- }; +- +- port@3 { +- reg = <3>; +- mdp_dtv_out: endpoint { +- }; +- }; +- }; +- }; +- +- riva: riva-pil@3204000 { +- compatible = "qcom,riva-pil"; +- +- reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>; +- reg-names = "ccu", "dxe", "pmu"; +- +- interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, +- <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal"; +- +- memory-region = <&wcnss_mem>; +- +- vddcx-supply = <&pm8921_s3>; +- vddmx-supply = <&pm8921_l24>; +- vddpx-supply = <&pm8921_s4>; +- +- status = "disabled"; +- +- iris { +- compatible = "qcom,wcn3660"; +- +- clocks = <&cxo_board>; +- clock-names = "xo"; +- +- vddxo-supply = <&pm8921_l4>; +- vddrfa-supply = <&pm8921_s2>; +- vddpa-supply = <&pm8921_l10>; +- vdddig-supply = <&pm8921_lvs2>; +- }; +- +- smd-edge { +- interrupts = ; +- +- qcom,ipc = <&l2cc 8 25>; +- qcom,smd-edge = <6>; +- +- label = "riva"; +- +- wcnss { +- compatible = "qcom,wcnss"; +- qcom,smd-channels = "WCNSS_CTRL"; +- +- qcom,mmio = <&riva>; +- +- bt { +- compatible = "qcom,wcnss-bt"; +- }; +- +- wifi { +- compatible = "qcom,wcnss-wlan"; +- +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- +- qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; +- qcom,smem-state-names = "tx-enable", "tx-rings-empty"; +- }; +- }; +- }; +- }; +- +- etb@1a01000 { +- compatible = "coresight-etb10", "arm,primecell"; +- reg = <0x1a01000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- +- in-ports { +- port { +- etb_in: endpoint { +- remote-endpoint = <&replicator_out0>; +- }; +- }; +- }; +- }; +- +- tpiu@1a03000 { +- compatible = "arm,coresight-tpiu", "arm,primecell"; +- reg = <0x1a03000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- +- in-ports { +- port { +- tpiu_in: endpoint { +- remote-endpoint = <&replicator_out1>; +- }; +- }; +- }; +- }; +- +- replicator { +- compatible = "arm,coresight-static-replicator"; +- +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- +- out-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- replicator_out0: endpoint { +- remote-endpoint = <&etb_in>; +- }; +- }; +- port@1 { +- reg = <1>; +- replicator_out1: endpoint { +- remote-endpoint = <&tpiu_in>; +- }; +- }; +- }; +- +- in-ports { +- port { +- replicator_in: endpoint { +- remote-endpoint = <&funnel_out>; +- }; +- }; +- }; +- }; +- +- funnel@1a04000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0x1a04000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* +- * Not described input ports: +- * 2 - connected to STM component +- * 3 - not-connected +- * 6 - not-connected +- * 7 - not-connected +- */ +- port@0 { +- reg = <0>; +- funnel_in0: endpoint { +- remote-endpoint = <&etm0_out>; +- }; +- }; +- port@1 { +- reg = <1>; +- funnel_in1: endpoint { +- remote-endpoint = <&etm1_out>; +- }; +- }; +- port@4 { +- reg = <4>; +- funnel_in4: endpoint { +- remote-endpoint = <&etm2_out>; +- }; +- }; +- port@5 { +- reg = <5>; +- funnel_in5: endpoint { +- remote-endpoint = <&etm3_out>; +- }; +- }; +- }; +- +- out-ports { +- port { +- funnel_out: endpoint { +- remote-endpoint = <&replicator_in>; +- }; +- }; +- }; +- }; +- +- etm@1a1c000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0x1a1c000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- +- cpu = <&CPU0>; +- +- out-ports { +- port { +- etm0_out: endpoint { +- remote-endpoint = <&funnel_in0>; +- }; +- }; +- }; +- }; +- +- etm@1a1d000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0x1a1d000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- +- cpu = <&CPU1>; +- +- out-ports { +- port { +- etm1_out: endpoint { +- remote-endpoint = <&funnel_in1>; +- }; +- }; +- }; +- }; +- +- etm@1a1e000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0x1a1e000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- +- cpu = <&CPU2>; +- +- out-ports { +- port { +- etm2_out: endpoint { +- remote-endpoint = <&funnel_in4>; +- }; +- }; +- }; +- }; +- +- etm@1a1f000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0x1a1f000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- +- cpu = <&CPU3>; +- +- out-ports { +- port { +- etm3_out: endpoint { +- remote-endpoint = <&funnel_in5>; +- }; +- }; +- }; +- }; +- }; +-}; +-#include "qcom-apq8064-pins.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/qcom-apq8074-dragonboard.dts b/scripts/dtc/include-prefixes/arm/qcom-apq8074-dragonboard.dts +deleted file mode 100644 +index 83793b835d40..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-apq8074-dragonboard.dts ++++ /dev/null +@@ -1,346 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "qcom-msm8974.dtsi" +-#include "qcom-pm8841.dtsi" +-#include "qcom-pm8941.dtsi" +- +-/ { +- model = "Qualcomm APQ8074 Dragonboard"; +- compatible = "qcom,apq8074-dragonboard", "qcom,apq8074"; +- +- aliases { +- serial0 = &blsp1_uart2; +- usid0 = &pm8941_0; +- usid4 = &pm8841_0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- soc { +- serial@f991e000 { +- status = "okay"; +- }; +- +- sdhci@f9824900 { +- bus-width = <8>; +- non-removable; +- status = "okay"; +- +- vmmc-supply = <&pm8941_l20>; +- vqmmc-supply = <&pm8941_s3>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhc1_pin_a>; +- }; +- +- sdhci@f98a4900 { +- cd-gpios = <&msmgpio 62 0x1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; +- bus-width = <4>; +- status = "okay"; +- +- vmmc-supply = <&pm8941_l21>; +- vqmmc-supply = <&pm8941_l13>; +- }; +- +- usb@f9a55000 { +- status = "okay"; +- phys = <&usb_hs2_phy>; +- phy-select = <&tcsr 0xb000 1>; +- extcon = <&smbb>, <&usb_id>; +- vbus-supply = <&chg_otg>; +- hnp-disable; +- srp-disable; +- adp-disable; +- ulpi { +- phy@b { +- status = "okay"; +- v3p3-supply = <&pm8941_l24>; +- v1p8-supply = <&pm8941_l6>; +- extcon = <&smbb>; +- qcom,init-seq = /bits/ 8 <0x1 0x63>; +- }; +- }; +- }; +- +- +- pinctrl@fd510000 { +- i2c11_pins: i2c11 { +- mux { +- pins = "gpio83", "gpio84"; +- function = "blsp_i2c11"; +- }; +- }; +- +- spi8_default: spi8_default { +- mosi { +- pins = "gpio45"; +- function = "blsp_spi8"; +- }; +- miso { +- pins = "gpio46"; +- function = "blsp_spi8"; +- }; +- cs { +- pins = "gpio47"; +- function = "blsp_spi8"; +- }; +- clk { +- pins = "gpio48"; +- function = "blsp_spi8"; +- }; +- }; +- +- sdhc1_pin_a: sdhc1-pin-active { +- clk { +- pins = "sdc1_clk"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- cmd-data { +- pins = "sdc1_cmd", "sdc1_data"; +- drive-strength = <10>; +- bias-pull-up; +- }; +- }; +- +- sdhc2_cd_pin_a: sdhc2-cd-pin-active { +- pins = "gpio62"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- sdhc2_pin_a: sdhc2-pin-active { +- clk { +- pins = "sdc2_clk"; +- drive-strength = <10>; +- bias-disable; +- }; +- +- cmd-data { +- pins = "sdc2_cmd", "sdc2_data"; +- drive-strength = <6>; +- bias-pull-up; +- }; +- }; +- }; +- +- i2c@f9967000 { +- status = "okay"; +- clock-frequency = <200000>; +- pinctrl-0 = <&i2c11_pins>; +- pinctrl-names = "default"; +- +- eeprom: eeprom@52 { +- compatible = "atmel,24c128"; +- reg = <0x52>; +- pagesize = <32>; +- read-only; +- }; +- }; +- }; +- +- smd { +- rpm { +- rpm_requests { +- pm8841-regulators { +- s1 { +- regulator-min-microvolt = <675000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- s2 { +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- s3 { +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- s4 { +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1050000>; +- }; +- }; +- +- pm8941-regulators { +- vdd_l1_l3-supply = <&pm8941_s1>; +- vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; +- vdd_l4_l11-supply = <&pm8941_s1>; +- vdd_l5_l7-supply = <&pm8941_s2>; +- vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; +- vin_5vs-supply = <&pm8941_5v>; +- +- s1 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- s2 { +- regulator-min-microvolt = <2150000>; +- regulator-max-microvolt = <2150000>; +- regulator-boot-on; +- }; +- +- s3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- l1 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- +- regulator-always-on; +- regulator-boot-on; +- }; +- +- l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- l3 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- l4 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- l5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-boot-on; +- }; +- +- l7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-boot-on; +- }; +- +- l8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l9 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- l10 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- l11 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- }; +- +- l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-always-on; +- regulator-boot-on; +- }; +- +- l13 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-boot-on; +- }; +- +- l14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l15 { +- regulator-min-microvolt = <2050000>; +- regulator-max-microvolt = <2050000>; +- }; +- +- l16 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- l17 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- l18 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- l19 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- l20 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-allow-set-load; +- regulator-boot-on; +- regulator-system-load = <200000>; +- }; +- +- l21 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-boot-on; +- }; +- +- l22 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- l23 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- l24 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- +- regulator-boot-on; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-apq8084-ifc6540.dts b/scripts/dtc/include-prefixes/arm/qcom-apq8084-ifc6540.dts +deleted file mode 100644 +index 44cd72f1b1be..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-apq8084-ifc6540.dts ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "qcom-apq8084.dtsi" +-#include "qcom-pma8084.dtsi" +- +-/ { +- model = "Qualcomm APQ8084/IFC6540"; +- compatible = "qcom,apq8084-sbc", "qcom,apq8084"; +- +- aliases { +- serial0 = &blsp2_uart2; +- usid0 = &pma8084_0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- soc { +- serial@f995e000 { +- status = "okay"; +- }; +- +- sdhci@f9824900 { +- bus-width = <8>; +- non-removable; +- status = "okay"; +- }; +- +- sdhci@f98a4900 { +- cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-apq8084-mtp.dts b/scripts/dtc/include-prefixes/arm/qcom-apq8084-mtp.dts +deleted file mode 100644 +index c6b6680248a6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-apq8084-mtp.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "qcom-apq8084.dtsi" +-#include "qcom-pma8084.dtsi" +- +-/ { +- model = "Qualcomm APQ 8084-MTP"; +- compatible = "qcom,apq8084-mtp", "qcom,apq8084"; +- +- aliases { +- serial0 = &blsp2_uart2; +- usid0 = &pma8084_0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- soc { +- serial@f995e000 { +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-apq8084.dtsi b/scripts/dtc/include-prefixes/arm/qcom-apq8084.dtsi +deleted file mode 100644 +index bf6a03506b45..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-apq8084.dtsi ++++ /dev/null +@@ -1,531 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Qualcomm APQ 8084"; +- compatible = "qcom,apq8084"; +- interrupt-parent = <&intc>; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- smem_mem: smem_region@fa00000 { +- reg = <0xfa00000 0x200000>; +- no-map; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "qcom,krait"; +- reg = <0>; +- enable-method = "qcom,kpss-acc-v2"; +- next-level-cache = <&L2>; +- qcom,acc = <&acc0>; +- qcom,saw = <&saw0>; +- cpu-idle-states = <&CPU_SPC>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "qcom,krait"; +- reg = <1>; +- enable-method = "qcom,kpss-acc-v2"; +- next-level-cache = <&L2>; +- qcom,acc = <&acc1>; +- qcom,saw = <&saw1>; +- cpu-idle-states = <&CPU_SPC>; +- }; +- +- cpu@2 { +- device_type = "cpu"; +- compatible = "qcom,krait"; +- reg = <2>; +- enable-method = "qcom,kpss-acc-v2"; +- next-level-cache = <&L2>; +- qcom,acc = <&acc2>; +- qcom,saw = <&saw2>; +- cpu-idle-states = <&CPU_SPC>; +- }; +- +- cpu@3 { +- device_type = "cpu"; +- compatible = "qcom,krait"; +- reg = <3>; +- enable-method = "qcom,kpss-acc-v2"; +- next-level-cache = <&L2>; +- qcom,acc = <&acc3>; +- qcom,saw = <&saw3>; +- cpu-idle-states = <&CPU_SPC>; +- }; +- +- L2: l2-cache { +- compatible = "qcom,arch-cache"; +- cache-level = <2>; +- qcom,saw = <&saw_l2>; +- }; +- +- idle-states { +- CPU_SPC: spc { +- compatible = "qcom,idle-state-spc", +- "arm,idle-state"; +- entry-latency-us = <150>; +- exit-latency-us = <200>; +- min-residency-us = <2000>; +- }; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; +- }; +- +- firmware { +- scm { +- compatible = "qcom,scm"; +- clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; +- clock-names = "core", "bus", "iface"; +- }; +- }; +- +- thermal-zones { +- cpu-thermal0 { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 5>; +- +- trips { +- cpu_alert0: trip0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu_crit0: trip1 { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu-thermal1 { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 6>; +- +- trips { +- cpu_alert1: trip0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu_crit1: trip1 { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu-thermal2 { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 7>; +- +- trips { +- cpu_alert2: trip0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu_crit2: trip1 { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu-thermal3 { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 8>; +- +- trips { +- cpu_alert3: trip0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu_crit3: trip1 { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- cpu-pmu { +- compatible = "qcom,krait-pmu"; +- interrupts = ; +- }; +- +- clocks { +- xo_board: xo_board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <19200000>; +- }; +- +- sleep_clk: sleep_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- clock-frequency = <19200000>; +- }; +- +- smem { +- compatible = "qcom,smem"; +- +- qcom,rpm-msg-ram = <&rpm_msg_ram>; +- memory-region = <&smem_mem>; +- +- hwlocks = <&tcsr_mutex 3>; +- }; +- +- soc: soc { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "simple-bus"; +- +- intc: interrupt-controller@f9000000 { +- compatible = "qcom,msm-qgic2"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0xf9000000 0x1000>, +- <0xf9002000 0x1000>; +- }; +- +- apcs: syscon@f9011000 { +- compatible = "syscon"; +- reg = <0xf9011000 0x1000>; +- }; +- +- qfprom: qfprom@fc4bc000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "qcom,qfprom"; +- reg = <0xfc4bc000 0x1000>; +- tsens_calib: calib@d0 { +- reg = <0xd0 0x18>; +- }; +- tsens_backup: backup@440 { +- reg = <0x440 0x10>; +- }; +- }; +- +- tsens: thermal-sensor@fc4a8000 { +- compatible = "qcom,msm8974-tsens"; +- reg = <0xfc4a9000 0x1000>, /* TM */ +- <0xfc4a8000 0x1000>; /* SROT */ +- nvmem-cells = <&tsens_calib>, <&tsens_backup>; +- nvmem-cell-names = "calib", "calib_backup"; +- #qcom,sensors = <11>; +- #thermal-sensor-cells = <1>; +- }; +- timer@f9020000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "arm,armv7-timer-mem"; +- reg = <0xf9020000 0x1000>; +- clock-frequency = <19200000>; +- +- frame@f9021000 { +- frame-number = <0>; +- interrupts = , +- ; +- reg = <0xf9021000 0x1000>, +- <0xf9022000 0x1000>; +- }; +- +- frame@f9023000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0xf9023000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9024000 { +- frame-number = <2>; +- interrupts = ; +- reg = <0xf9024000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9025000 { +- frame-number = <3>; +- interrupts = ; +- reg = <0xf9025000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9026000 { +- frame-number = <4>; +- interrupts = ; +- reg = <0xf9026000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9027000 { +- frame-number = <5>; +- interrupts = ; +- reg = <0xf9027000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9028000 { +- frame-number = <6>; +- interrupts = ; +- reg = <0xf9028000 0x1000>; +- status = "disabled"; +- }; +- }; +- +- saw0: power-controller@f9089000 { +- compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; +- reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; +- }; +- +- saw1: power-controller@f9099000 { +- compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; +- reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; +- }; +- +- saw2: power-controller@f90a9000 { +- compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; +- reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; +- }; +- +- saw3: power-controller@f90b9000 { +- compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; +- reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; +- }; +- +- saw_l2: power-controller@f9012000 { +- compatible = "qcom,saw2"; +- reg = <0xf9012000 0x1000>; +- regulator; +- }; +- +- acc0: clock-controller@f9088000 { +- compatible = "qcom,kpss-acc-v2"; +- reg = <0xf9088000 0x1000>, +- <0xf9008000 0x1000>; +- }; +- +- acc1: clock-controller@f9098000 { +- compatible = "qcom,kpss-acc-v2"; +- reg = <0xf9098000 0x1000>, +- <0xf9008000 0x1000>; +- }; +- +- acc2: clock-controller@f90a8000 { +- compatible = "qcom,kpss-acc-v2"; +- reg = <0xf90a8000 0x1000>, +- <0xf9008000 0x1000>; +- }; +- +- acc3: clock-controller@f90b8000 { +- compatible = "qcom,kpss-acc-v2"; +- reg = <0xf90b8000 0x1000>, +- <0xf9008000 0x1000>; +- }; +- +- restart@fc4ab000 { +- compatible = "qcom,pshold"; +- reg = <0xfc4ab000 0x4>; +- }; +- +- gcc: clock-controller@fc400000 { +- compatible = "qcom,gcc-apq8084"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- reg = <0xfc400000 0x4000>; +- }; +- +- tcsr_mutex_regs: syscon@fd484000 { +- compatible = "syscon"; +- reg = <0xfd484000 0x2000>; +- }; +- +- tcsr_mutex: hwlock { +- compatible = "qcom,tcsr-mutex"; +- syscon = <&tcsr_mutex_regs 0 0x80>; +- #hwlock-cells = <1>; +- }; +- +- rpm_msg_ram: memory@fc428000 { +- compatible = "qcom,rpm-msg-ram"; +- reg = <0xfc428000 0x4000>; +- }; +- +- tlmm: pinctrl@fd510000 { +- compatible = "qcom,apq8084-pinctrl"; +- reg = <0xfd510000 0x4000>; +- gpio-controller; +- gpio-ranges = <&tlmm 0 0 147>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- +- blsp2_uart2: serial@f995e000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0xf995e000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- sdhci@f9824900 { +- compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; +- reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; +- reg-names = "hc_mem", "core_mem"; +- interrupts = , ; +- interrupt-names = "hc_irq", "pwr_irq"; +- clocks = <&gcc GCC_SDCC1_APPS_CLK>, +- <&gcc GCC_SDCC1_AHB_CLK>, +- <&xo_board>; +- clock-names = "core", "iface", "xo"; +- status = "disabled"; +- }; +- +- sdhci@f98a4900 { +- compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; +- reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; +- reg-names = "hc_mem", "core_mem"; +- interrupts = , ; +- interrupt-names = "hc_irq", "pwr_irq"; +- clocks = <&gcc GCC_SDCC2_APPS_CLK>, +- <&gcc GCC_SDCC2_AHB_CLK>, +- <&xo_board>; +- clock-names = "core", "iface", "xo"; +- status = "disabled"; +- }; +- +- spmi_bus: spmi@fc4cf000 { +- compatible = "qcom,spmi-pmic-arb"; +- reg-names = "core", "intr", "cnfg"; +- reg = <0xfc4cf000 0x1000>, +- <0xfc4cb000 0x1000>, +- <0xfc4ca000 0x1000>; +- interrupt-names = "periph_irq"; +- interrupts = ; +- qcom,ee = <0>; +- qcom,channel = <0>; +- #address-cells = <2>; +- #size-cells = <0>; +- interrupt-controller; +- #interrupt-cells = <4>; +- }; +- }; +- +- smd { +- compatible = "qcom,smd"; +- +- rpm { +- interrupts = ; +- qcom,ipc = <&apcs 8 0>; +- qcom,smd-edge = <15>; +- +- rpm_requests { +- compatible = "qcom,rpm-apq8084"; +- qcom,smd-channels = "rpm_requests"; +- +- pma8084-regulators { +- compatible = "qcom,rpm-pma8084-regulators"; +- +- pma8084_s1: s1 {}; +- pma8084_s2: s2 {}; +- pma8084_s3: s3 {}; +- pma8084_s4: s4 {}; +- pma8084_s5: s5 {}; +- pma8084_s6: s6 {}; +- pma8084_s7: s7 {}; +- pma8084_s8: s8 {}; +- pma8084_s9: s9 {}; +- pma8084_s10: s10 {}; +- pma8084_s11: s11 {}; +- pma8084_s12: s12 {}; +- +- pma8084_l1: l1 {}; +- pma8084_l2: l2 {}; +- pma8084_l3: l3 {}; +- pma8084_l4: l4 {}; +- pma8084_l5: l5 {}; +- pma8084_l6: l6 {}; +- pma8084_l7: l7 {}; +- pma8084_l8: l8 {}; +- pma8084_l9: l9 {}; +- pma8084_l10: l10 {}; +- pma8084_l11: l11 {}; +- pma8084_l12: l12 {}; +- pma8084_l13: l13 {}; +- pma8084_l14: l14 {}; +- pma8084_l15: l15 {}; +- pma8084_l16: l16 {}; +- pma8084_l17: l17 {}; +- pma8084_l18: l18 {}; +- pma8084_l19: l19 {}; +- pma8084_l20: l20 {}; +- pma8084_l21: l21 {}; +- pma8084_l22: l22 {}; +- pma8084_l23: l23 {}; +- pma8084_l24: l24 {}; +- pma8084_l25: l25 {}; +- pma8084_l26: l26 {}; +- pma8084_l27: l27 {}; +- +- pma8084_lvs1: lvs1 {}; +- pma8084_lvs2: lvs2 {}; +- pma8084_lvs3: lvs3 {}; +- pma8084_lvs4: lvs4 {}; +- +- pma8084_5vs1: 5vs1 {}; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-ipq4018-ap120c-ac-bit.dts b/scripts/dtc/include-prefixes/arm/qcom-ipq4018-ap120c-ac-bit.dts +deleted file mode 100644 +index 028ac8e24797..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-ipq4018-ap120c-ac-bit.dts ++++ /dev/null +@@ -1,28 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +- +-#include "qcom-ipq4018-ap120c-ac.dtsi" +- +-/ { +- model = "ALFA Network AP120C-AC Bit"; +- +- leds { +- compatible = "gpio-leds"; +- +- power { +- label = "ap120c-ac:green:power"; +- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- +- wlan { +- label = "ap120c-ac:green:wlan"; +- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; +- }; +- +- support { +- label = "ap120c-ac:green:support"; +- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; +- panic-indicator; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-ipq4018-ap120c-ac.dts b/scripts/dtc/include-prefixes/arm/qcom-ipq4018-ap120c-ac.dts +deleted file mode 100644 +index b7916fc26d68..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-ipq4018-ap120c-ac.dts ++++ /dev/null +@@ -1,27 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +- +-#include "qcom-ipq4018-ap120c-ac.dtsi" +- +-/ { +- leds { +- compatible = "gpio-leds"; +- +- status: status { +- label = "ap120c-ac:blue:status"; +- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; +- default-state = "keep"; +- }; +- +- wlan2g { +- label = "ap120c-ac:green:wlan2g"; +- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "phy0tpt"; +- }; +- +- wlan5g { +- label = "ap120c-ac:red:wlan5g"; +- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "phy1tpt"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-ipq4018-ap120c-ac.dtsi b/scripts/dtc/include-prefixes/arm/qcom-ipq4018-ap120c-ac.dtsi +deleted file mode 100644 +index 1f3b1ce82108..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-ipq4018-ap120c-ac.dtsi ++++ /dev/null +@@ -1,254 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +- +-#include "qcom-ipq4019.dtsi" +-#include +-#include +- +-/ { +- model = "ALFA Network AP120C-AC"; +- compatible = "alfa-network,ap120c-ac"; +- +- keys { +- compatible = "gpio-keys"; +- +- reset { +- label = "reset"; +- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +-}; +- +-&tlmm { +- i2c0_pins: i2c0_pinmux { +- mux_i2c { +- function = "blsp_i2c0"; +- pins = "gpio58", "gpio59"; +- drive-strength = <16>; +- bias-disable; +- }; +- }; +- +- mdio_pins: mdio_pinmux { +- mux_mdio { +- pins = "gpio53"; +- function = "mdio"; +- bias-pull-up; +- }; +- +- mux_mdc { +- pins = "gpio52"; +- function = "mdc"; +- bias-pull-up; +- }; +- }; +- +- serial0_pins: serial0_pinmux { +- mux_uart { +- pins = "gpio60", "gpio61"; +- function = "blsp_uart0"; +- bias-disable; +- }; +- }; +- +- spi0_pins: spi0_pinmux { +- mux_spi { +- function = "blsp_spi0"; +- pins = "gpio55", "gpio56", "gpio57"; +- drive-strength = <12>; +- bias-disable; +- }; +- +- mux_cs { +- function = "gpio"; +- pins = "gpio54", "gpio4"; +- drive-strength = <2>; +- bias-disable; +- output-high; +- }; +- }; +- +- usb-power { +- line-name = "USB-power"; +- gpios = <1 GPIO_ACTIVE_HIGH>; +- gpio-hog; +- output-high; +- }; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-&prng { +- status = "okay"; +-}; +- +-&blsp_dma { +- status = "okay"; +-}; +- +-&blsp1_i2c3 { +- status = "okay"; +- +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +- +- tpm@29 { +- compatible = "atmel,at97sc3204t"; +- reg = <0x29>; +- }; +-}; +- +-&blsp1_spi1 { +- status = "okay"; +- +- pinctrl-0 = <&spi0_pins>; +- pinctrl-names = "default"; +- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 4 GPIO_ACTIVE_HIGH>; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <24000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "SBL1"; +- reg = <0x00000000 0x00040000>; +- read-only; +- }; +- +- partition@40000 { +- label = "MIBIB"; +- reg = <0x00040000 0x00020000>; +- read-only; +- }; +- +- partition@60000 { +- label = "QSEE"; +- reg = <0x00060000 0x00060000>; +- read-only; +- }; +- +- partition@c0000 { +- label = "CDT"; +- reg = <0x000c0000 0x00010000>; +- read-only; +- }; +- +- partition@d0000 { +- label = "DDRPARAMS"; +- reg = <0x000d0000 0x00010000>; +- read-only; +- }; +- +- partition@e0000 { +- label = "u-boot-env"; +- reg = <0x000e0000 0x00010000>; +- }; +- +- partition@f0000 { +- label = "u-boot"; +- reg = <0x000f0000 0x00080000>; +- read-only; +- }; +- +- partition@170000 { +- label = "ART"; +- reg = <0x00170000 0x00010000>; +- read-only; +- }; +- +- partition@180000 { +- label = "priv_data1"; +- reg = <0x00180000 0x00010000>; +- read-only; +- }; +- +- partition@190000 { +- label = "priv_data2"; +- reg = <0x00190000 0x00010000>; +- read-only; +- }; +- }; +- }; +- +- nand@1 { +- compatible = "spi-nand"; +- reg = <1>; +- spi-max-frequency = <40000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "ubi1"; +- reg = <0x00000000 0x04000000>; +- }; +- +- partition@4000000 { +- label = "ubi2"; +- reg = <0x04000000 0x04000000>; +- }; +- }; +- }; +-}; +- +-&blsp1_uart1 { +- status = "okay"; +- +- pinctrl-0 = <&serial0_pins>; +- pinctrl-names = "default"; +-}; +- +-&cryptobam { +- status = "okay"; +-}; +- +-&crypto { +- status = "okay"; +-}; +- +-&mdio { +- status = "okay"; +- +- pinctrl-0 = <&mdio_pins>; +- pinctrl-names = "default"; +-}; +- +-&wifi0 { +- status = "okay"; +-}; +- +-&wifi1 { +- status = "okay"; +- qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC"; +-}; +- +-&usb3_hs_phy { +- status = "okay"; +-}; +- +-&usb3 { +- status = "okay"; +- +- dwc3@8a00000 { +- phys = <&usb3_hs_phy>; +- phy-names = "usb2-phy"; +- }; +-}; +- +-&usb2_hs_phy { +- status = "okay"; +-}; +- +-&usb2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-ipq4018-jalapeno.dts b/scripts/dtc/include-prefixes/arm/qcom-ipq4018-jalapeno.dts +deleted file mode 100644 +index 394412619894..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-ipq4018-jalapeno.dts ++++ /dev/null +@@ -1,214 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-// Copyright (c) 2018, Robert Marko +- +-#include "qcom-ipq4019.dtsi" +-#include +-#include +- +-/ { +- model = "8devices Jalapeno"; +- compatible = "8dev,jalapeno"; +-}; +- +-&tlmm { +- mdio_pins: mdio_pinmux { +- pinmux_1 { +- pins = "gpio53"; +- function = "mdio"; +- }; +- +- pinmux_2 { +- pins = "gpio52"; +- function = "mdc"; +- }; +- +- pinconf { +- pins = "gpio52", "gpio53"; +- bias-pull-up; +- }; +- }; +- +- serial_pins: serial_pinmux { +- mux { +- pins = "gpio60", "gpio61"; +- function = "blsp_uart0"; +- bias-disable; +- }; +- }; +- +- spi_0_pins: spi_0_pinmux { +- pin { +- function = "blsp_spi0"; +- pins = "gpio55", "gpio56", "gpio57"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- pin_cs { +- function = "gpio"; +- pins = "gpio54", "gpio59"; +- drive-strength = <2>; +- bias-disable; +- output-high; +- }; +- }; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-&prng { +- status = "okay"; +-}; +- +-&blsp_dma { +- status = "okay"; +-}; +- +-&blsp1_spi1 { +- status = "okay"; +- +- pinctrl-0 = <&spi_0_pins>; +- pinctrl-names = "default"; +- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>; +- +- flash@0 { +- status = "okay"; +- +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <24000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "SBL1"; +- reg = <0x00000000 0x00040000>; +- read-only; +- }; +- +- partition@40000 { +- label = "MIBIB"; +- reg = <0x00040000 0x00020000>; +- read-only; +- }; +- +- partition@60000 { +- label = "QSEE"; +- reg = <0x00060000 0x00060000>; +- read-only; +- }; +- +- partition@c0000 { +- label = "CDT"; +- reg = <0x000c0000 0x00010000>; +- read-only; +- }; +- +- partition@d0000 { +- label = "DDRPARAMS"; +- reg = <0x000d0000 0x00010000>; +- read-only; +- }; +- +- partition@e0000 { +- label = "u-boot-env"; +- reg = <0x000e0000 0x00010000>; +- }; +- +- partition@f0000 { +- label = "u-boot"; +- reg = <0x000f0000 0x00080000>; +- read-only; +- }; +- +- partition@170000 { +- label = "ART"; +- reg = <0x00170000 0x00010000>; +- read-only; +- }; +- }; +- }; +- +- spi-nand@1 { +- status = "okay"; +- +- compatible = "spi-nand"; +- reg = <1>; +- spi-max-frequency = <24000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "ubi1"; +- reg = <0x00000000 0x04000000>; +- }; +- +- partition@4000000 { +- label = "ubi2"; +- reg = <0x04000000 0x04000000>; +- }; +- }; +- }; +-}; +- +-&blsp1_uart1 { +- status = "okay"; +- +- pinctrl-0 = <&serial_pins>; +- pinctrl-names = "default"; +-}; +- +-&cryptobam { +- status = "okay"; +-}; +- +-&crypto { +- status = "okay"; +-}; +- +-&mdio { +- status = "okay"; +- +- pinctrl-0 = <&mdio_pins>; +- pinctrl-names = "default"; +-}; +- +-&wifi0 { +- status = "okay"; +- +- qcom,ath10k-calibration-variant = "8devices-Jalapeno"; +-}; +- +-&wifi1 { +- status = "okay"; +- +- qcom,ath10k-calibration-variant = "8devices-Jalapeno"; +-}; +- +-&usb3_ss_phy { +- status = "okay"; +-}; +- +-&usb3_hs_phy { +- status = "okay"; +-}; +- +-&usb3 { +- status = "okay"; +-}; +- +-&usb2_hs_phy { +- status = "okay"; +-}; +- +-&usb2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk01.1-c1.dts b/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk01.1-c1.dts +deleted file mode 100644 +index 0d92f1bc3a13..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk01.1-c1.dts ++++ /dev/null +@@ -1,22 +0,0 @@ +-/* Copyright (c) 2015, The Linux Foundation. All rights reserved. +- * +- * Permission to use, copy, modify, and/or distribute this software for any +- * purpose with or without fee is hereby granted, provided that the above +- * copyright notice and this permission notice appear in all copies. +- * +- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +- * +- */ +- +-#include "qcom-ipq4019-ap.dk01.1.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1"; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk01.1.dtsi b/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk01.1.dtsi +deleted file mode 100644 +index c93b2164db44..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk01.1.dtsi ++++ /dev/null +@@ -1,113 +0,0 @@ +-/* Copyright (c) 2015, The Linux Foundation. All rights reserved. +- * +- * Permission to use, copy, modify, and/or distribute this software for any +- * purpose with or without fee is hereby granted, provided that the above +- * copyright notice and this permission notice appear in all copies. +- * +- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +- * +- */ +- +-#include "qcom-ipq4019.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1"; +- compatible = "qcom,ipq4019"; +- +- aliases { +- serial0 = &blsp1_uart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- soc { +- rng@22000 { +- status = "okay"; +- }; +- +- pinctrl@1000000 { +- serial_pins: serial_pinmux { +- mux { +- pins = "gpio60", "gpio61"; +- function = "blsp_uart0"; +- bias-disable; +- }; +- }; +- +- spi_0_pins: spi_0_pinmux { +- pinmux { +- function = "blsp_spi0"; +- pins = "gpio55", "gpio56", "gpio57"; +- }; +- pinmux_cs { +- function = "gpio"; +- pins = "gpio54"; +- }; +- pinconf { +- pins = "gpio55", "gpio56", "gpio57"; +- drive-strength = <12>; +- bias-disable; +- }; +- pinconf_cs { +- pins = "gpio54"; +- drive-strength = <2>; +- bias-disable; +- output-high; +- }; +- }; +- }; +- +- blsp_dma: dma@7884000 { +- status = "okay"; +- }; +- +- spi@78b5000 { +- pinctrl-0 = <&spi_0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- cs-gpios = <&tlmm 54 0>; +- +- mx25l25635e@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- compatible = "mx25l25635e"; +- spi-max-frequency = <24000000>; +- }; +- }; +- +- serial@78af000 { +- pinctrl-0 = <&serial_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- +- cryptobam: dma@8e04000 { +- status = "okay"; +- }; +- +- crypto@8e3a000 { +- status = "okay"; +- }; +- +- watchdog@b017000 { +- status = "okay"; +- }; +- +- wifi@a000000 { +- status = "okay"; +- }; +- +- wifi@a800000 { +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk04.1-c1.dts b/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk04.1-c1.dts +deleted file mode 100644 +index b0f476ff017f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk04.1-c1.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2018, The Linux Foundation. All rights reserved. +- +-#include "qcom-ipq4019-ap.dk04.1.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1"; +- compatible = "qcom,ipq4019-dk04.1-c1"; +- +- soc { +- dma@7984000 { +- status = "okay"; +- }; +- +- qpic-nand@79b0000 { +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk04.1-c3.dts b/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk04.1-c3.dts +deleted file mode 100644 +index 2d1c4c6e42f1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk04.1-c3.dts ++++ /dev/null +@@ -1,9 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2018, The Linux Foundation. All rights reserved. +- +-#include "qcom-ipq4019-ap.dk04.1.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3"; +- compatible = "qcom,ipq4019-ap-dk04.1-c3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk04.1.dtsi b/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk04.1.dtsi +deleted file mode 100644 +index 7a337dc08741..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk04.1.dtsi ++++ /dev/null +@@ -1,111 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2018, The Linux Foundation. All rights reserved. +- +-#include "qcom-ipq4019.dtsi" +-#include +-#include +- +-/ { +- model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1"; +- +- aliases { +- serial0 = &blsp1_uart1; +- serial1 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256MB */ +- }; +- +- soc { +- pinctrl@1000000 { +- serial_0_pins: serial0-pinmux { +- pins = "gpio16", "gpio17"; +- function = "blsp_uart0"; +- bias-disable; +- }; +- +- serial_1_pins: serial1-pinmux { +- pins = "gpio8", "gpio9", +- "gpio10", "gpio11"; +- function = "blsp_uart1"; +- bias-disable; +- }; +- +- spi_0_pins: spi-0-pinmux { +- pinmux { +- function = "blsp_spi0"; +- pins = "gpio13", "gpio14", "gpio15"; +- bias-disable; +- }; +- pinmux_cs { +- function = "gpio"; +- pins = "gpio12"; +- bias-disable; +- output-high; +- }; +- }; +- +- i2c_0_pins: i2c-0-pinmux { +- pins = "gpio20", "gpio21"; +- function = "blsp_i2c0"; +- bias-disable; +- }; +- +- nand_pins: nand-pins { +- pins = "gpio53", "gpio55", "gpio56", +- "gpio57", "gpio58", "gpio59", +- "gpio60", "gpio62", "gpio63", +- "gpio64", "gpio65", "gpio66", +- "gpio67", "gpio68", "gpio69"; +- function = "qpic"; +- }; +- }; +- +- serial@78af000 { +- pinctrl-0 = <&serial_0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- +- serial@78b0000 { +- pinctrl-0 = <&serial_1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- +- dma@7884000 { +- status = "okay"; +- }; +- +- spi@78b5000 { /* BLSP1 QUP1 */ +- pinctrl-0 = <&spi_0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- cs-gpios = <&tlmm 12 0>; +- +- m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- compatible = "n25q128a11"; +- spi-max-frequency = <24000000>; +- }; +- }; +- +- pci@40000000 { +- status = "okay"; +- perst-gpio = <&tlmm 38 0x1>; +- }; +- +- qpic-nand@79b0000 { +- pinctrl-0 = <&nand_pins>; +- pinctrl-names = "default"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk07.1-c1.dts b/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk07.1-c1.dts +deleted file mode 100644 +index f343a2244386..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk07.1-c1.dts ++++ /dev/null +@@ -1,64 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2018, The Linux Foundation. All rights reserved. +- +-#include "qcom-ipq4019-ap.dk07.1.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1"; +- compatible = "qcom,ipq4019-ap-dk07.1-c1"; +- +- soc { +- pci@40000000 { +- status = "okay"; +- perst-gpio = <&tlmm 38 0x1>; +- }; +- +- spi@78b6000 { +- status = "okay"; +- }; +- +- pinctrl@1000000 { +- serial_1_pins: serial1-pinmux { +- pins = "gpio8", "gpio9", +- "gpio10", "gpio11"; +- function = "blsp_uart1"; +- bias-disable; +- }; +- +- spi_0_pins: spi-0-pinmux { +- pinmux { +- function = "blsp_spi0"; +- pins = "gpio13", "gpio14", "gpio15"; +- bias-disable; +- }; +- pinmux_cs { +- function = "gpio"; +- pins = "gpio12"; +- bias-disable; +- output-high; +- }; +- }; +- }; +- +- serial@78b0000 { +- pinctrl-0 = <&serial_1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- +- spi@78b5000 { +- pinctrl-0 = <&spi_0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- cs-gpios = <&tlmm 12 0>; +- +- m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- compatible = "n25q128a11"; +- spi-max-frequency = <24000000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk07.1-c2.dts b/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk07.1-c2.dts +deleted file mode 100644 +index 582acb681a98..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk07.1-c2.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2018, The Linux Foundation. All rights reserved. +- +-#include "qcom-ipq4019-ap.dk07.1.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2"; +- compatible = "qcom,ipq4019-ap-dk07.1-c2"; +- +- soc { +- pinctrl@1000000 { +- serial_1_pins: serial1-pinmux { +- pins = "gpio8", "gpio9"; +- function = "blsp_uart1"; +- bias-disable; +- }; +- }; +- +- serial@78b0000 { +- pinctrl-0 = <&serial_1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk07.1.dtsi b/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk07.1.dtsi +deleted file mode 100644 +index 94872518b5a2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-ipq4019-ap.dk07.1.dtsi ++++ /dev/null +@@ -1,75 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2018, The Linux Foundation. All rights reserved. +- +-#include "qcom-ipq4019.dtsi" +-#include +-#include +- +-/ { +- model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1"; +- +- memory { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; /* 512MB */ +- }; +- +- aliases { +- serial0 = &blsp1_uart1; +- serial1 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- soc { +- pinctrl@1000000 { +- serial_0_pins: serial0-pinmux { +- pins = "gpio16", "gpio17"; +- function = "blsp_uart0"; +- bias-disable; +- }; +- +- i2c_0_pins: i2c-0-pinmux { +- pins = "gpio20", "gpio21"; +- function = "blsp_i2c0"; +- bias-disable; +- }; +- +- nand_pins: nand-pins { +- pins = "gpio53", "gpio55", "gpio56", +- "gpio57", "gpio58", "gpio59", +- "gpio60", "gpio62", "gpio63", +- "gpio64", "gpio65", "gpio66", +- "gpio67", "gpio68", "gpio69"; +- function = "qpic"; +- }; +- }; +- +- serial@78af000 { +- pinctrl-0 = <&serial_0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- +- dma@7884000 { +- status = "okay"; +- }; +- +- i2c@78b7000 { /* BLSP1 QUP2 */ +- pinctrl-0 = <&i2c_0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- +- dma@7984000 { +- status = "okay"; +- }; +- +- qpic-nand@79b0000 { +- pinctrl-0 = <&nand_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-ipq4019.dtsi b/scripts/dtc/include-prefixes/arm/qcom-ipq4019.dtsi +deleted file mode 100644 +index ff1bdb10ad19..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-ipq4019.dtsi ++++ /dev/null +@@ -1,693 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2015, The Linux Foundation. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- model = "Qualcomm Technologies, Inc. IPQ4019"; +- compatible = "qcom,ipq4019"; +- interrupt-parent = <&intc>; +- +- reserved-memory { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- ranges; +- +- smem_region: smem@87e00000 { +- reg = <0x87e00000 0x080000>; +- no-map; +- }; +- +- tz@87e80000 { +- reg = <0x87e80000 0x180000>; +- no-map; +- }; +- }; +- +- aliases { +- spi0 = &blsp1_spi1; +- spi1 = &blsp1_spi2; +- i2c0 = &blsp1_i2c3; +- i2c1 = &blsp1_i2c4; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- enable-method = "qcom,kpss-acc-v2"; +- next-level-cache = <&L2>; +- qcom,acc = <&acc0>; +- qcom,saw = <&saw0>; +- reg = <0x0>; +- clocks = <&gcc GCC_APPS_CLK_SRC>; +- clock-frequency = <0>; +- clock-latency = <256000>; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- enable-method = "qcom,kpss-acc-v2"; +- next-level-cache = <&L2>; +- qcom,acc = <&acc1>; +- qcom,saw = <&saw1>; +- reg = <0x1>; +- clocks = <&gcc GCC_APPS_CLK_SRC>; +- clock-frequency = <0>; +- clock-latency = <256000>; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- enable-method = "qcom,kpss-acc-v2"; +- next-level-cache = <&L2>; +- qcom,acc = <&acc2>; +- qcom,saw = <&saw2>; +- reg = <0x2>; +- clocks = <&gcc GCC_APPS_CLK_SRC>; +- clock-frequency = <0>; +- clock-latency = <256000>; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- enable-method = "qcom,kpss-acc-v2"; +- next-level-cache = <&L2>; +- qcom,acc = <&acc3>; +- qcom,saw = <&saw3>; +- reg = <0x3>; +- clocks = <&gcc GCC_APPS_CLK_SRC>; +- clock-frequency = <0>; +- clock-latency = <256000>; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- L2: l2-cache { +- compatible = "cache"; +- cache-level = <2>; +- qcom,saw = <&saw_l2>; +- }; +- }; +- +- cpu0_opp_table: opp_table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-48000000 { +- opp-hz = /bits/ 64 <48000000>; +- clock-latency-ns = <256000>; +- }; +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- clock-latency-ns = <256000>; +- }; +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- clock-latency-ns = <256000>; +- }; +- opp-716000000 { +- opp-hz = /bits/ 64 <716000000>; +- clock-latency-ns = <256000>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; +- }; +- +- pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupts = ; +- }; +- +- clocks { +- sleep_clk: sleep_clk { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- xo: xo { +- compatible = "fixed-clock"; +- clock-frequency = <48000000>; +- #clock-cells = <0>; +- }; +- }; +- +- firmware { +- scm { +- compatible = "qcom,scm-ipq4019"; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = <1 2 0xf08>, +- <1 3 0xf08>, +- <1 4 0xf08>, +- <1 1 0xf08>; +- clock-frequency = <48000000>; +- always-on; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "simple-bus"; +- +- intc: interrupt-controller@b000000 { +- compatible = "qcom,msm-qgic2"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x0b000000 0x1000>, +- <0x0b002000 0x1000>; +- }; +- +- gcc: clock-controller@1800000 { +- compatible = "qcom,gcc-ipq4019"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- reg = <0x1800000 0x60000>; +- }; +- +- prng: rng@22000 { +- compatible = "qcom,prng"; +- reg = <0x22000 0x140>; +- clocks = <&gcc GCC_PRNG_AHB_CLK>; +- clock-names = "core"; +- status = "disabled"; +- }; +- +- tlmm: pinctrl@1000000 { +- compatible = "qcom,ipq4019-pinctrl"; +- reg = <0x01000000 0x300000>; +- gpio-controller; +- gpio-ranges = <&tlmm 0 0 100>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- +- vqmmc: regulator@1948000 { +- compatible = "qcom,vqmmc-ipq4019-regulator"; +- reg = <0x01948000 0x4>; +- regulator-name = "vqmmc"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- status = "disabled"; +- }; +- +- sdhci: sdhci@7824900 { +- compatible = "qcom,sdhci-msm-v4"; +- reg = <0x7824900 0x11c>, <0x7824000 0x800>; +- interrupts = , ; +- interrupt-names = "hc_irq", "pwr_irq"; +- bus-width = <8>; +- clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, +- <&gcc GCC_DCD_XO_CLK>; +- clock-names = "core", "iface", "xo"; +- status = "disabled"; +- }; +- +- blsp_dma: dma@7884000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0x07884000 0x23000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- status = "disabled"; +- }; +- +- blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */ +- compatible = "qcom,spi-qup-v2.2.1"; +- reg = <0x78b5000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- #address-cells = <1>; +- #size-cells = <0>; +- dmas = <&blsp_dma 5>, <&blsp_dma 4>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */ +- compatible = "qcom,spi-qup-v2.2.1"; +- reg = <0x78b6000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- #address-cells = <1>; +- #size-cells = <0>; +- dmas = <&blsp_dma 7>, <&blsp_dma 6>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */ +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x78b7000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- #address-cells = <1>; +- #size-cells = <0>; +- dmas = <&blsp_dma 9>, <&blsp_dma 8>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */ +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x78b8000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- #address-cells = <1>; +- #size-cells = <0>; +- dmas = <&blsp_dma 11>, <&blsp_dma 10>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- cryptobam: dma@8e04000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0x08e04000 0x20000>; +- interrupts = ; +- clocks = <&gcc GCC_CRYPTO_AHB_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <1>; +- qcom,controlled-remotely; +- status = "disabled"; +- }; +- +- crypto: crypto@8e3a000 { +- compatible = "qcom,crypto-v5.1"; +- reg = <0x08e3a000 0x6000>; +- clocks = <&gcc GCC_CRYPTO_AHB_CLK>, +- <&gcc GCC_CRYPTO_AXI_CLK>, +- <&gcc GCC_CRYPTO_CLK>; +- clock-names = "iface", "bus", "core"; +- dmas = <&cryptobam 2>, <&cryptobam 3>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- acc0: clock-controller@b088000 { +- compatible = "qcom,kpss-acc-v2"; +- reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; +- }; +- +- acc1: clock-controller@b098000 { +- compatible = "qcom,kpss-acc-v2"; +- reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; +- }; +- +- acc2: clock-controller@b0a8000 { +- compatible = "qcom,kpss-acc-v2"; +- reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; +- }; +- +- acc3: clock-controller@b0b8000 { +- compatible = "qcom,kpss-acc-v2"; +- reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; +- }; +- +- saw0: regulator@b089000 { +- compatible = "qcom,saw2"; +- reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; +- regulator; +- }; +- +- saw1: regulator@b099000 { +- compatible = "qcom,saw2"; +- reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; +- regulator; +- }; +- +- saw2: regulator@b0a9000 { +- compatible = "qcom,saw2"; +- reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; +- regulator; +- }; +- +- saw3: regulator@b0b9000 { +- compatible = "qcom,saw2"; +- reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; +- regulator; +- }; +- +- saw_l2: regulator@b012000 { +- compatible = "qcom,saw2"; +- reg = <0xb012000 0x1000>; +- regulator; +- }; +- +- blsp1_uart1: serial@78af000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x78af000 0x200>; +- interrupts = ; +- status = "disabled"; +- clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp_dma 1>, <&blsp_dma 0>; +- dma-names = "rx", "tx"; +- }; +- +- blsp1_uart2: serial@78b0000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x78b0000 0x200>; +- interrupts = ; +- status = "disabled"; +- clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp_dma 3>, <&blsp_dma 2>; +- dma-names = "rx", "tx"; +- }; +- +- watchdog: watchdog@b017000 { +- compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019"; +- reg = <0xb017000 0x40>; +- clocks = <&sleep_clk>; +- timeout-sec = <10>; +- status = "disabled"; +- }; +- +- restart@4ab000 { +- compatible = "qcom,pshold"; +- reg = <0x4ab000 0x4>; +- }; +- +- pcie0: pci@40000000 { +- compatible = "qcom,pcie-ipq4019", "snps,dw-pcie"; +- reg = <0x40000000 0xf1d +- 0x40000f20 0xa8 +- 0x80000 0x2000 +- 0x40100000 0x1000>; +- reg-names = "dbi", "elbi", "parf", "config"; +- device_type = "pci"; +- linux,pci-domain = <0>; +- bus-range = <0x00 0xff>; +- num-lanes = <1>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>, +- <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>; +- +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ +- <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ +- <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ +- <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ +- clocks = <&gcc GCC_PCIE_AHB_CLK>, +- <&gcc GCC_PCIE_AXI_M_CLK>, +- <&gcc GCC_PCIE_AXI_S_CLK>; +- clock-names = "aux", +- "master_bus", +- "slave_bus"; +- +- resets = <&gcc PCIE_AXI_M_ARES>, +- <&gcc PCIE_AXI_S_ARES>, +- <&gcc PCIE_PIPE_ARES>, +- <&gcc PCIE_AXI_M_VMIDMT_ARES>, +- <&gcc PCIE_AXI_S_XPU_ARES>, +- <&gcc PCIE_PARF_XPU_ARES>, +- <&gcc PCIE_PHY_ARES>, +- <&gcc PCIE_AXI_M_STICKY_ARES>, +- <&gcc PCIE_PIPE_STICKY_ARES>, +- <&gcc PCIE_PWR_ARES>, +- <&gcc PCIE_AHB_ARES>, +- <&gcc PCIE_PHY_AHB_ARES>; +- reset-names = "axi_m", +- "axi_s", +- "pipe", +- "axi_m_vmid", +- "axi_s_xpu", +- "parf", +- "phy", +- "axi_m_sticky", +- "pipe_sticky", +- "pwr", +- "ahb", +- "phy_ahb"; +- +- status = "disabled"; +- }; +- +- qpic_bam: dma@7984000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0x7984000 0x1a000>; +- interrupts = ; +- clocks = <&gcc GCC_QPIC_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- status = "disabled"; +- }; +- +- nand: nand-controller@79b0000 { +- compatible = "qcom,ipq4019-nand"; +- reg = <0x79b0000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&gcc GCC_QPIC_CLK>, +- <&gcc GCC_QPIC_AHB_CLK>; +- clock-names = "core", "aon"; +- +- dmas = <&qpic_bam 0>, +- <&qpic_bam 1>, +- <&qpic_bam 2>; +- dma-names = "tx", "rx", "cmd"; +- status = "disabled"; +- +- nand@0 { +- reg = <0>; +- +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- nand-bus-width = <8>; +- }; +- }; +- +- wifi0: wifi@a000000 { +- compatible = "qcom,ipq4019-wifi"; +- reg = <0xa000000 0x200000>; +- resets = <&gcc WIFI0_CPU_INIT_RESET>, +- <&gcc WIFI0_RADIO_SRIF_RESET>, +- <&gcc WIFI0_RADIO_WARM_RESET>, +- <&gcc WIFI0_RADIO_COLD_RESET>, +- <&gcc WIFI0_CORE_WARM_RESET>, +- <&gcc WIFI0_CORE_COLD_RESET>; +- reset-names = "wifi_cpu_init", "wifi_radio_srif", +- "wifi_radio_warm", "wifi_radio_cold", +- "wifi_core_warm", "wifi_core_cold"; +- clocks = <&gcc GCC_WCSS2G_CLK>, +- <&gcc GCC_WCSS2G_REF_CLK>, +- <&gcc GCC_WCSS2G_RTC_CLK>; +- clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", +- "wifi_wcss_rtc"; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "msi0", "msi1", "msi2", "msi3", +- "msi4", "msi5", "msi6", "msi7", +- "msi8", "msi9", "msi10", "msi11", +- "msi12", "msi13", "msi14", "msi15", +- "legacy"; +- status = "disabled"; +- }; +- +- wifi1: wifi@a800000 { +- compatible = "qcom,ipq4019-wifi"; +- reg = <0xa800000 0x200000>; +- resets = <&gcc WIFI1_CPU_INIT_RESET>, +- <&gcc WIFI1_RADIO_SRIF_RESET>, +- <&gcc WIFI1_RADIO_WARM_RESET>, +- <&gcc WIFI1_RADIO_COLD_RESET>, +- <&gcc WIFI1_CORE_WARM_RESET>, +- <&gcc WIFI1_CORE_COLD_RESET>; +- reset-names = "wifi_cpu_init", "wifi_radio_srif", +- "wifi_radio_warm", "wifi_radio_cold", +- "wifi_core_warm", "wifi_core_cold"; +- clocks = <&gcc GCC_WCSS5G_CLK>, +- <&gcc GCC_WCSS5G_REF_CLK>, +- <&gcc GCC_WCSS5G_RTC_CLK>; +- clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", +- "wifi_wcss_rtc"; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "msi0", "msi1", "msi2", "msi3", +- "msi4", "msi5", "msi6", "msi7", +- "msi8", "msi9", "msi10", "msi11", +- "msi12", "msi13", "msi14", "msi15", +- "legacy"; +- status = "disabled"; +- }; +- +- mdio: mdio@90000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "qcom,ipq4019-mdio"; +- reg = <0x90000 0x64>; +- status = "disabled"; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- }; +- +- ethphy2: ethernet-phy@2 { +- reg = <2>; +- }; +- +- ethphy3: ethernet-phy@3 { +- reg = <3>; +- }; +- +- ethphy4: ethernet-phy@4 { +- reg = <4>; +- }; +- }; +- +- usb3_ss_phy: ssphy@9a000 { +- compatible = "qcom,usb-ss-ipq4019-phy"; +- #phy-cells = <0>; +- reg = <0x9a000 0x800>; +- reg-names = "phy_base"; +- resets = <&gcc USB3_UNIPHY_PHY_ARES>; +- reset-names = "por_rst"; +- status = "disabled"; +- }; +- +- usb3_hs_phy: hsphy@a6000 { +- compatible = "qcom,usb-hs-ipq4019-phy"; +- #phy-cells = <0>; +- reg = <0xa6000 0x40>; +- reg-names = "phy_base"; +- resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; +- reset-names = "por_rst", "srif_rst"; +- status = "disabled"; +- }; +- +- usb3: usb3@8af8800 { +- compatible = "qcom,dwc3"; +- reg = <0x8af8800 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&gcc GCC_USB3_MASTER_CLK>, +- <&gcc GCC_USB3_SLEEP_CLK>, +- <&gcc GCC_USB3_MOCK_UTMI_CLK>; +- clock-names = "master", "sleep", "mock_utmi"; +- ranges; +- status = "disabled"; +- +- dwc3@8a00000 { +- compatible = "snps,dwc3"; +- reg = <0x8a00000 0xf8000>; +- interrupts = ; +- phys = <&usb3_hs_phy>, <&usb3_ss_phy>; +- phy-names = "usb2-phy", "usb3-phy"; +- dr_mode = "host"; +- }; +- }; +- +- usb2_hs_phy: hsphy@a8000 { +- compatible = "qcom,usb-hs-ipq4019-phy"; +- #phy-cells = <0>; +- reg = <0xa8000 0x40>; +- reg-names = "phy_base"; +- resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; +- reset-names = "por_rst", "srif_rst"; +- status = "disabled"; +- }; +- +- usb2: usb2@60f8800 { +- compatible = "qcom,dwc3"; +- reg = <0x60f8800 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&gcc GCC_USB2_MASTER_CLK>, +- <&gcc GCC_USB2_SLEEP_CLK>, +- <&gcc GCC_USB2_MOCK_UTMI_CLK>; +- clock-names = "master", "sleep", "mock_utmi"; +- ranges; +- status = "disabled"; +- +- dwc3@6000000 { +- compatible = "snps,dwc3"; +- reg = <0x6000000 0xf8000>; +- interrupts = ; +- phys = <&usb2_hs_phy>; +- phy-names = "usb2-phy"; +- dr_mode = "host"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-ipq8064-ap148.dts b/scripts/dtc/include-prefixes/arm/qcom-ipq8064-ap148.dts +deleted file mode 100644 +index e5b9b9cf6097..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-ipq8064-ap148.dts ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "qcom-ipq8064-v1.0.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. IPQ8064/AP-148"; +- compatible = "qcom,ipq8064-ap148"; +- +- soc { +- pinmux@800000 { +- i2c4_pins: i2c4_pinmux { +- pins = "gpio12", "gpio13"; +- function = "gsbi4"; +- bias-disable; +- }; +- +- buttons_pins: buttons_pins { +- mux { +- pins = "gpio54", "gpio65"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- }; +- }; +- +- gsbi@16300000 { +- i2c@16380000 { +- status = "okay"; +- clock-frequency = <200000>; +- pinctrl-0 = <&i2c4_pins>; +- pinctrl-names = "default"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-ipq8064-rb3011.dts b/scripts/dtc/include-prefixes/arm/qcom-ipq8064-rb3011.dts +deleted file mode 100644 +index 971d2e229260..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-ipq8064-rb3011.dts ++++ /dev/null +@@ -1,366 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "qcom-ipq8064.dtsi" +-#include +- +-/ { +- model = "MikroTik RB3011UiAS-RM"; +- compatible = "mikrotik,rb3011"; +- +- aliases { +- serial0 = &gsbi7_serial; +- ethernet0 = &gmac0; +- ethernet1 = &gmac3; +- mdio-gpio0 = &mdio0; +- mdio-gpio1 = &mdio1; +- }; +- +- chosen { +- bootargs = "loglevel=8 console=ttyMSM0,115200"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@42000000 { +- reg = <0x42000000 0x3e000000>; +- device_type = "memory"; +- }; +- +- mdio0: mdio-0 { +- status = "okay"; +- compatible = "virtual,mdio-gpio"; +- gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, +- <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pinctrl-0 = <&mdio0_pins>; +- pinctrl-names = "default"; +- +- switch0: switch@10 { +- compatible = "qca,qca8337"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- dsa,member = <0 0>; +- +- pinctrl-0 = <&sw0_reset_pin>; +- pinctrl-names = "default"; +- +- reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; +- reg = <0x10>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch0cpu: port@0 { +- reg = <0>; +- label = "cpu"; +- ethernet = <&gmac0>; +- phy-mode = "rgmii-id"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- port@1 { +- reg = <1>; +- label = "sw1"; +- }; +- +- port@2 { +- reg = <2>; +- label = "sw2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "sw3"; +- }; +- +- port@4 { +- reg = <4>; +- label = "sw4"; +- }; +- +- port@5 { +- reg = <5>; +- label = "sw5"; +- }; +- }; +- }; +- }; +- +- mdio1: mdio-1 { +- status = "okay"; +- compatible = "virtual,mdio-gpio"; +- gpios = <&qcom_pinmux 11 GPIO_ACTIVE_HIGH>, +- <&qcom_pinmux 10 GPIO_ACTIVE_HIGH>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pinctrl-0 = <&mdio1_pins>; +- pinctrl-names = "default"; +- +- switch1: switch@14 { +- compatible = "qca,qca8337"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- dsa,member = <1 0>; +- +- pinctrl-0 = <&sw1_reset_pin>; +- pinctrl-names = "default"; +- +- reset-gpios = <&qcom_pinmux 17 GPIO_ACTIVE_LOW>; +- reg = <0x10>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch1cpu: port@0 { +- reg = <0>; +- label = "cpu"; +- ethernet = <&gmac3>; +- phy-mode = "sgmii"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- port@1 { +- reg = <1>; +- label = "sw6"; +- }; +- +- port@2 { +- reg = <2>; +- label = "sw7"; +- }; +- +- port@3 { +- reg = <3>; +- label = "sw8"; +- }; +- +- port@4 { +- reg = <4>; +- label = "sw9"; +- }; +- +- port@5 { +- reg = <5>; +- label = "sw10"; +- }; +- }; +- }; +- }; +- +- soc { +- gsbi5: gsbi@1a200000 { +- qcom,mode = ; +- status = "okay"; +- +- spi4: spi@1a280000 { +- status = "okay"; +- spi-max-frequency = <50000000>; +- +- pinctrl-0 = <&spi_pins>; +- pinctrl-names = "default"; +- +- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; +- +- norflash: s25fl016k@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <50000000>; +- reg = <0>; +- +- partition@0 { +- label = "RouterBoot"; +- reg = <0x0 0x40000>; +- }; +- }; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&buttons_pins>; +- pinctrl-names = "default"; +- +- button@1 { +- label = "reset"; +- linux,code = ; +- gpios = <&qcom_pinmux 66 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- debounce-interval = <60>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&leds_pins>; +- pinctrl-names = "default"; +- +- led@7 { +- label = "rb3011:green:user"; +- gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- }; +-}; +- +-&adm_dma { +- status = "okay"; +-}; +- +-&gmac0 { +- status = "okay"; +- +- phy-mode = "rgmii"; +- qcom,id = <0>; +- phy-handle = <&switch0cpu>; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +-}; +- +-&gmac3 { +- status = "okay"; +- +- phy-mode = "sgmii"; +- qcom,id = <3>; +- phy-handle = <&switch1cpu>; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +-}; +- +-&gsbi7 { +- status = "okay"; +- qcom,mode = ; +-}; +- +-&gsbi7_serial { +- status = "okay"; +-}; +- +-&hs_phy_1 { +- status = "okay"; +-}; +- +-&nand { +- status = "okay"; +- +- nandcs@0 { +- compatible = "qcom,nandcs"; +- reg = <0>; +- +- nand-ecc-strength = <4>; +- nand-bus-width = <8>; +- nand-ecc-step-size = <512>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- boot@0 { +- label = "RouterBoard NAND 1 Boot"; +- reg = <0x0000000 0x0800000>; +- }; +- +- main@800000 { +- label = "RouterBoard NAND 1 Main"; +- reg = <0x0800000 0x7800000>; +- }; +- }; +- }; +-}; +- +-&qcom_pinmux { +- buttons_pins: buttons_pins { +- mux { +- pins = "gpio66"; +- drive-strength = <16>; +- bias-disable; +- }; +- }; +- +- leds_pins: leds_pins { +- mux { +- pins = "gpio33"; +- drive-strength = <16>; +- bias-disable; +- }; +- }; +- +- mdio0_pins: mdio0_pins { +- mux { +- pins = "gpio0", "gpio1"; +- function = "gpio"; +- drive-strength = <8>; +- bias-disable; +- }; +- }; +- +- mdio1_pins: mdio1_pins { +- mux { +- pins = "gpio10", "gpio11"; +- function = "gpio"; +- drive-strength = <8>; +- bias-disable; +- }; +- }; +- +- sw0_reset_pin: sw0_reset_pin { +- mux { +- pins = "gpio16"; +- drive-strength = <16>; +- function = "gpio"; +- bias-disable; +- input-disable; +- }; +- }; +- +- sw1_reset_pin: sw1_reset_pin { +- mux { +- pins = "gpio17"; +- drive-strength = <16>; +- function = "gpio"; +- bias-disable; +- input-disable; +- }; +- }; +- +- usb1_pwr_en_pins: usb1_pwr_en_pins { +- mux { +- pins = "gpio4"; +- function = "gpio"; +- drive-strength = <16>; +- bias-disable; +- output-high; +- }; +- }; +-}; +- +-&ss_phy_1 { +- status = "okay"; +-}; +- +-&usb3_1 { +- pinctrl-0 = <&usb1_pwr_en_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-ipq8064-v1.0.dtsi b/scripts/dtc/include-prefixes/arm/qcom-ipq8064-v1.0.dtsi +deleted file mode 100644 +index 65330065390a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-ipq8064-v1.0.dtsi ++++ /dev/null +@@ -1,127 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "qcom-ipq8064.dtsi" +-#include +- +-/ { +- model = "Qualcomm Technologies, Inc. IPQ8064-v1.0"; +- +- aliases { +- serial0 = &gsbi4_serial; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- soc { +- gsbi@16300000 { +- qcom,mode = ; +- status = "okay"; +- +- serial@16340000 { +- status = "okay"; +- }; +- }; +- +- gsbi5: gsbi@1a200000 { +- qcom,mode = ; +- status = "okay"; +- +- spi4: spi@1a280000 { +- status = "okay"; +- spi-max-frequency = <50000000>; +- +- pinctrl-0 = <&spi_pins>; +- pinctrl-names = "default"; +- +- cs-gpios = <&qcom_pinmux 20 0>; +- +- flash: m25p80@0 { +- compatible = "s25fl256s1"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <50000000>; +- reg = <0>; +- +- partition@0 { +- label = "rootfs"; +- reg = <0x0 0x1000000>; +- }; +- +- partition@1 { +- label = "scratch"; +- reg = <0x1000000 0x1000000>; +- }; +- }; +- }; +- }; +- +- sata-phy@1b400000 { +- status = "okay"; +- }; +- +- sata@29000000 { +- ports-implemented = <0x1>; +- status = "okay"; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&buttons_pins>; +- pinctrl-names = "default"; +- +- button@1 { +- label = "reset"; +- linux,code = ; +- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- debounce-interval = <60>; +- }; +- button@2 { +- label = "wps"; +- linux,code = ; +- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- debounce-interval = <60>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&leds_pins>; +- pinctrl-names = "default"; +- +- led@7 { +- label = "led_usb1"; +- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "usbdev"; +- default-state = "off"; +- }; +- +- led@8 { +- label = "led_usb3"; +- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "usbdev"; +- default-state = "off"; +- }; +- +- led@9 { +- label = "status_led_fail"; +- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led@26 { +- label = "sata_led"; +- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led@53 { +- label = "status_led_pass"; +- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-ipq8064.dtsi b/scripts/dtc/include-prefixes/arm/qcom-ipq8064.dtsi +deleted file mode 100644 +index 4139d3817bd6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-ipq8064.dtsi ++++ /dev/null +@@ -1,1225 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Qualcomm IPQ8064"; +- compatible = "qcom,ipq8064"; +- interrupt-parent = <&intc>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "qcom,krait"; +- enable-method = "qcom,kpss-acc-v1"; +- device_type = "cpu"; +- reg = <0>; +- next-level-cache = <&L2>; +- qcom,acc = <&acc0>; +- qcom,saw = <&saw0>; +- }; +- +- cpu1: cpu@1 { +- compatible = "qcom,krait"; +- enable-method = "qcom,kpss-acc-v1"; +- device_type = "cpu"; +- reg = <1>; +- next-level-cache = <&L2>; +- qcom,acc = <&acc1>; +- qcom,saw = <&saw1>; +- }; +- +- L2: l2-cache { +- compatible = "cache"; +- cache-level = <2>; +- }; +- }; +- +- thermal-zones { +- tsens_tz_sensor0 { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&tsens 0>; +- +- trips { +- cpu-critical { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- +- cpu-hot { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- tsens_tz_sensor1 { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&tsens 1>; +- +- trips { +- cpu-critical { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- +- cpu-hot { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- tsens_tz_sensor2 { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&tsens 2>; +- +- trips { +- cpu-critical { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- +- cpu-hot { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- tsens_tz_sensor3 { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&tsens 3>; +- +- trips { +- cpu-critical { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- +- cpu-hot { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- tsens_tz_sensor4 { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&tsens 4>; +- +- trips { +- cpu-critical { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- +- cpu-hot { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- tsens_tz_sensor5 { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&tsens 5>; +- +- trips { +- cpu-critical { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- +- cpu-hot { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- tsens_tz_sensor6 { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&tsens 6>; +- +- trips { +- cpu-critical { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- +- cpu-hot { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- tsens_tz_sensor7 { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&tsens 7>; +- +- trips { +- cpu-critical { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- +- cpu-hot { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- tsens_tz_sensor8 { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&tsens 8>; +- +- trips { +- cpu-critical { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- +- cpu-hot { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- tsens_tz_sensor9 { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&tsens 9>; +- +- trips { +- cpu-critical { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- +- cpu-hot { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- tsens_tz_sensor10 { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&tsens 10>; +- +- trips { +- cpu-critical { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- +- cpu-hot { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; +- }; +- +- cpu-pmu { +- compatible = "qcom,krait-pmu"; +- interrupts = ; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- nss@40000000 { +- reg = <0x40000000 0x1000000>; +- no-map; +- }; +- +- smem: smem@41000000 { +- reg = <0x41000000 0x200000>; +- no-map; +- }; +- }; +- +- clocks { +- cxo_board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- pxo_board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- sleep_clk: sleep_clk { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- }; +- +- firmware { +- scm { +- compatible = "qcom,scm-ipq806x", "qcom,scm"; +- }; +- }; +- +- soc: soc { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "simple-bus"; +- +- lpass@28100000 { +- compatible = "qcom,lpass-cpu"; +- status = "disabled"; +- clocks = <&lcc AHBIX_CLK>, +- <&lcc MI2S_OSR_CLK>, +- <&lcc MI2S_BIT_CLK>; +- clock-names = "ahbix-clk", +- "mi2s-osr-clk", +- "mi2s-bit-clk"; +- interrupts = ; +- interrupt-names = "lpass-irq-lpaif"; +- reg = <0x28100000 0x10000>; +- reg-names = "lpass-lpaif"; +- }; +- +- qcom_pinmux: pinmux@800000 { +- compatible = "qcom,ipq8064-pinctrl"; +- reg = <0x800000 0x4000>; +- +- gpio-controller; +- gpio-ranges = <&qcom_pinmux 0 0 69>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- +- pcie0_pins: pcie0_pinmux { +- mux { +- pins = "gpio3"; +- function = "pcie1_rst"; +- drive-strength = <12>; +- bias-disable; +- }; +- }; +- +- pcie1_pins: pcie1_pinmux { +- mux { +- pins = "gpio48"; +- function = "pcie2_rst"; +- drive-strength = <12>; +- bias-disable; +- }; +- }; +- +- pcie2_pins: pcie2_pinmux { +- mux { +- pins = "gpio63"; +- function = "pcie3_rst"; +- drive-strength = <12>; +- bias-disable; +- }; +- }; +- +- spi_pins: spi_pins { +- mux { +- pins = "gpio18", "gpio19", "gpio21"; +- function = "gsbi5"; +- drive-strength = <10>; +- bias-none; +- }; +- }; +- +- leds_pins: leds_pins { +- mux { +- pins = "gpio7", "gpio8", "gpio9", +- "gpio26", "gpio53"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-down; +- output-low; +- }; +- }; +- +- buttons_pins: buttons_pins { +- mux { +- pins = "gpio54"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- }; +- +- nand_pins: nand_pins { +- mux { +- pins = "gpio34", "gpio35", "gpio36", +- "gpio37", "gpio38", "gpio39", +- "gpio40", "gpio41", "gpio42", +- "gpio43", "gpio44", "gpio45", +- "gpio46", "gpio47"; +- function = "nand"; +- drive-strength = <10>; +- bias-disable; +- }; +- +- pullups { +- pins = "gpio39"; +- bias-pull-up; +- }; +- +- hold { +- pins = "gpio40", "gpio41", "gpio42", +- "gpio43", "gpio44", "gpio45", +- "gpio46", "gpio47"; +- bias-bus-hold; +- }; +- }; +- }; +- +- intc: interrupt-controller@2000000 { +- compatible = "qcom,msm-qgic2"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x02000000 0x1000>, +- <0x02002000 0x1000>; +- }; +- +- timer@200a000 { +- compatible = "qcom,kpss-timer", +- "qcom,kpss-wdt-ipq8064", "qcom,msm-timer"; +- interrupts = , +- , +- , +- , +- ; +- reg = <0x0200a000 0x100>; +- clock-frequency = <25000000>, +- <32768>; +- clocks = <&sleep_clk>; +- clock-names = "sleep"; +- cpu-offset = <0x80000>; +- }; +- +- acc0: clock-controller@2088000 { +- compatible = "qcom,kpss-acc-v1"; +- reg = <0x02088000 0x1000>, <0x02008000 0x1000>; +- }; +- +- acc1: clock-controller@2098000 { +- compatible = "qcom,kpss-acc-v1"; +- reg = <0x02098000 0x1000>, <0x02008000 0x1000>; +- }; +- +- adm_dma: dma-controller@18300000 { +- compatible = "qcom,adm"; +- reg = <0x18300000 0x100000>; +- interrupts = ; +- #dma-cells = <1>; +- +- clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; +- clock-names = "core", "iface"; +- +- resets = <&gcc ADM0_RESET>, +- <&gcc ADM0_PBUS_RESET>, +- <&gcc ADM0_C0_RESET>, +- <&gcc ADM0_C1_RESET>, +- <&gcc ADM0_C2_RESET>; +- reset-names = "clk", "pbus", "c0", "c1", "c2"; +- qcom,ee = <0>; +- +- status = "disabled"; +- }; +- +- saw0: regulator@2089000 { +- compatible = "qcom,saw2"; +- reg = <0x02089000 0x1000>, <0x02009000 0x1000>; +- regulator; +- }; +- +- saw1: regulator@2099000 { +- compatible = "qcom,saw2"; +- reg = <0x02099000 0x1000>, <0x02009000 0x1000>; +- regulator; +- }; +- +- gsbi2: gsbi@12480000 { +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <2>; +- reg = <0x12480000 0x100>; +- clocks = <&gcc GSBI2_H_CLK>; +- clock-names = "iface"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- +- syscon-tcsr = <&tcsr>; +- +- gsbi2_serial: serial@12490000 { +- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; +- reg = <0x12490000 0x1000>, +- <0x12480000 0x1000>; +- interrupts = ; +- clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- i2c@124a0000 { +- compatible = "qcom,i2c-qup-v1.1.1"; +- reg = <0x124a0000 0x1000>; +- interrupts = ; +- +- clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- gsbi4: gsbi@16300000 { +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <4>; +- reg = <0x16300000 0x100>; +- clocks = <&gcc GSBI4_H_CLK>; +- clock-names = "iface"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- +- syscon-tcsr = <&tcsr>; +- +- gsbi4_serial: serial@16340000 { +- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; +- reg = <0x16340000 0x1000>, +- <0x16300000 0x1000>; +- interrupts = ; +- clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- i2c@16380000 { +- compatible = "qcom,i2c-qup-v1.1.1"; +- reg = <0x16380000 0x1000>; +- interrupts = ; +- +- clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- gsbi5: gsbi@1a200000 { +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <5>; +- reg = <0x1a200000 0x100>; +- clocks = <&gcc GSBI5_H_CLK>; +- clock-names = "iface"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- +- syscon-tcsr = <&tcsr>; +- +- gsbi5_serial: serial@1a240000 { +- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; +- reg = <0x1a240000 0x1000>, +- <0x1a200000 0x1000>; +- interrupts = ; +- clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- i2c@1a280000 { +- compatible = "qcom,i2c-qup-v1.1.1"; +- reg = <0x1a280000 0x1000>; +- interrupts = ; +- +- clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spi@1a280000 { +- compatible = "qcom,spi-qup-v1.1.1"; +- reg = <0x1a280000 0x1000>; +- interrupts = ; +- +- clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- gsbi7: gsbi@16600000 { +- status = "disabled"; +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <7>; +- reg = <0x16600000 0x100>; +- clocks = <&gcc GSBI7_H_CLK>; +- clock-names = "iface"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- syscon-tcsr = <&tcsr>; +- +- gsbi7_serial: serial@16640000 { +- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; +- reg = <0x16640000 0x1000>, +- <0x16600000 0x1000>; +- interrupts = ; +- clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- }; +- +- rng@1a500000 { +- compatible = "qcom,prng"; +- reg = <0x1a500000 0x200>; +- clocks = <&gcc PRNG_CLK>; +- clock-names = "core"; +- }; +- +- sata_phy: sata-phy@1b400000 { +- compatible = "qcom,ipq806x-sata-phy"; +- reg = <0x1b400000 0x200>; +- +- clocks = <&gcc SATA_PHY_CFG_CLK>; +- clock-names = "cfg"; +- +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- nand: nand-controller@1ac00000 { +- compatible = "qcom,ipq806x-nand"; +- reg = <0x1ac00000 0x800>; +- +- pinctrl-0 = <&nand_pins>; +- pinctrl-names = "default"; +- +- clocks = <&gcc EBI2_CLK>, +- <&gcc EBI2_AON_CLK>; +- clock-names = "core", "aon"; +- +- dmas = <&adm_dma 3>; +- dma-names = "rxtx"; +- qcom,cmd-crci = <15>; +- qcom,data-crci = <3>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- +- sata: sata@29000000 { +- compatible = "qcom,ipq806x-ahci", "generic-ahci"; +- reg = <0x29000000 0x180>; +- +- interrupts = ; +- +- clocks = <&gcc SFAB_SATA_S_H_CLK>, +- <&gcc SATA_H_CLK>, +- <&gcc SATA_A_CLK>, +- <&gcc SATA_RXOOB_CLK>, +- <&gcc SATA_PMALIVE_CLK>; +- clock-names = "slave_face", "iface", "core", +- "rxoob", "pmalive"; +- +- assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; +- assigned-clock-rates = <100000000>, <100000000>; +- +- phys = <&sata_phy>; +- phy-names = "sata-phy"; +- status = "disabled"; +- }; +- +- qcom,ssbi@500000 { +- compatible = "qcom,ssbi"; +- reg = <0x00500000 0x1000>; +- qcom,controller-type = "pmic-arbiter"; +- }; +- +- qfprom: qfprom@700000 { +- compatible = "qcom,qfprom"; +- reg = <0x00700000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- tsens_calib: calib@400 { +- reg = <0x400 0xb>; +- }; +- tsens_calib_backup: calib_backup@410 { +- reg = <0x410 0xb>; +- }; +- }; +- +- gcc: clock-controller@900000 { +- compatible = "qcom,gcc-ipq8064"; +- reg = <0x00900000 0x4000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- +- tsens: thermal-sensor@900000 { +- compatible = "qcom,ipq8064-tsens"; +- +- nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; +- nvmem-cell-names = "calib", "calib_backup"; +- interrupts = ; +- interrupt-names = "uplow"; +- +- #qcom,sensors = <11>; +- #thermal-sensor-cells = <1>; +- }; +- }; +- +- rpm: rpm@108000 { +- compatible = "qcom,rpm-ipq8064"; +- reg = <0x108000 0x1000>; +- qcom,ipc = <&l2cc 0x8 2>; +- +- interrupts = , +- , +- ; +- interrupt-names = "ack", "err", "wakeup"; +- +- clocks = <&gcc RPM_MSG_RAM_H_CLK>; +- clock-names = "ram"; +- +- rpmcc: clock-controller { +- compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; +- #clock-cells = <1>; +- }; +- }; +- +- tcsr: syscon@1a400000 { +- compatible = "qcom,tcsr-ipq8064", "syscon"; +- reg = <0x1a400000 0x100>; +- }; +- +- l2cc: clock-controller@2011000 { +- compatible = "qcom,kpss-gcc", "syscon"; +- reg = <0x2011000 0x1000>; +- clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; +- clock-names = "pll8_vote", "pxo"; +- clock-output-names = "acpu_l2_aux"; +- }; +- +- lcc: clock-controller@28000000 { +- compatible = "qcom,lcc-ipq8064"; +- reg = <0x28000000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pcie0: pci@1b500000 { +- compatible = "qcom,pcie-ipq8064"; +- reg = <0x1b500000 0x1000 +- 0x1b502000 0x80 +- 0x1b600000 0x100 +- 0x0ff00000 0x100000>; +- reg-names = "dbi", "elbi", "parf", "config"; +- device_type = "pci"; +- linux,pci-domain = <0>; +- bus-range = <0x00 0xff>; +- num-lanes = <1>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */ +- 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ +- +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ +- <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ +- <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ +- <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ +- +- clocks = <&gcc PCIE_A_CLK>, +- <&gcc PCIE_H_CLK>, +- <&gcc PCIE_PHY_CLK>, +- <&gcc PCIE_AUX_CLK>, +- <&gcc PCIE_ALT_REF_CLK>; +- clock-names = "core", "iface", "phy", "aux", "ref"; +- +- assigned-clocks = <&gcc PCIE_ALT_REF_CLK>; +- assigned-clock-rates = <100000000>; +- +- resets = <&gcc PCIE_ACLK_RESET>, +- <&gcc PCIE_HCLK_RESET>, +- <&gcc PCIE_POR_RESET>, +- <&gcc PCIE_PCI_RESET>, +- <&gcc PCIE_PHY_RESET>, +- <&gcc PCIE_EXT_RESET>; +- reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; +- +- pinctrl-0 = <&pcie0_pins>; +- pinctrl-names = "default"; +- +- status = "disabled"; +- perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; +- }; +- +- pcie1: pci@1b700000 { +- compatible = "qcom,pcie-ipq8064"; +- reg = <0x1b700000 0x1000 +- 0x1b702000 0x80 +- 0x1b800000 0x100 +- 0x31f00000 0x100000>; +- reg-names = "dbi", "elbi", "parf", "config"; +- device_type = "pci"; +- linux,pci-domain = <1>; +- bus-range = <0x00 0xff>; +- num-lanes = <1>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */ +- 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ +- +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ +- <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ +- <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ +- <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ +- +- clocks = <&gcc PCIE_1_A_CLK>, +- <&gcc PCIE_1_H_CLK>, +- <&gcc PCIE_1_PHY_CLK>, +- <&gcc PCIE_1_AUX_CLK>, +- <&gcc PCIE_1_ALT_REF_CLK>; +- clock-names = "core", "iface", "phy", "aux", "ref"; +- +- assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>; +- assigned-clock-rates = <100000000>; +- +- resets = <&gcc PCIE_1_ACLK_RESET>, +- <&gcc PCIE_1_HCLK_RESET>, +- <&gcc PCIE_1_POR_RESET>, +- <&gcc PCIE_1_PCI_RESET>, +- <&gcc PCIE_1_PHY_RESET>, +- <&gcc PCIE_1_EXT_RESET>; +- reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; +- +- pinctrl-0 = <&pcie1_pins>; +- pinctrl-names = "default"; +- +- status = "disabled"; +- perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; +- }; +- +- pcie2: pci@1b900000 { +- compatible = "qcom,pcie-ipq8064"; +- reg = <0x1b900000 0x1000 +- 0x1b902000 0x80 +- 0x1ba00000 0x100 +- 0x35f00000 0x100000>; +- reg-names = "dbi", "elbi", "parf", "config"; +- device_type = "pci"; +- linux,pci-domain = <2>; +- bus-range = <0x00 0xff>; +- num-lanes = <1>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */ +- 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ +- +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ +- <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ +- <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ +- <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ +- +- clocks = <&gcc PCIE_2_A_CLK>, +- <&gcc PCIE_2_H_CLK>, +- <&gcc PCIE_2_PHY_CLK>, +- <&gcc PCIE_2_AUX_CLK>, +- <&gcc PCIE_2_ALT_REF_CLK>; +- clock-names = "core", "iface", "phy", "aux", "ref"; +- +- assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>; +- assigned-clock-rates = <100000000>; +- +- resets = <&gcc PCIE_2_ACLK_RESET>, +- <&gcc PCIE_2_HCLK_RESET>, +- <&gcc PCIE_2_POR_RESET>, +- <&gcc PCIE_2_PCI_RESET>, +- <&gcc PCIE_2_PHY_RESET>, +- <&gcc PCIE_2_EXT_RESET>; +- reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; +- +- pinctrl-0 = <&pcie2_pins>; +- pinctrl-names = "default"; +- +- status = "disabled"; +- perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; +- }; +- +- nss_common: syscon@03000000 { +- compatible = "syscon"; +- reg = <0x03000000 0x0000FFFF>; +- }; +- +- qsgmii_csr: syscon@1bb00000 { +- compatible = "syscon"; +- reg = <0x1bb00000 0x000001FF>; +- }; +- +- stmmac_axi_setup: stmmac-axi-config { +- snps,wr_osr_lmt = <7>; +- snps,rd_osr_lmt = <7>; +- snps,blen = <16 0 0 0 0 0 0>; +- }; +- +- gmac0: ethernet@37000000 { +- device_type = "network"; +- compatible = "qcom,ipq806x-gmac"; +- reg = <0x37000000 0x200000>; +- interrupts = ; +- interrupt-names = "macirq"; +- +- snps,axi-config = <&stmmac_axi_setup>; +- snps,pbl = <32>; +- snps,aal = <1>; +- +- qcom,nss-common = <&nss_common>; +- qcom,qsgmii-csr = <&qsgmii_csr>; +- +- clocks = <&gcc GMAC_CORE1_CLK>; +- clock-names = "stmmaceth"; +- +- resets = <&gcc GMAC_CORE1_RESET>, +- <&gcc GMAC_AHB_RESET>; +- reset-names = "stmmaceth", "ahb"; +- +- status = "disabled"; +- }; +- +- gmac1: ethernet@37200000 { +- device_type = "network"; +- compatible = "qcom,ipq806x-gmac"; +- reg = <0x37200000 0x200000>; +- interrupts = ; +- interrupt-names = "macirq"; +- +- snps,axi-config = <&stmmac_axi_setup>; +- snps,pbl = <32>; +- snps,aal = <1>; +- +- qcom,nss-common = <&nss_common>; +- qcom,qsgmii-csr = <&qsgmii_csr>; +- +- clocks = <&gcc GMAC_CORE2_CLK>; +- clock-names = "stmmaceth"; +- +- resets = <&gcc GMAC_CORE2_RESET>, +- <&gcc GMAC_AHB_RESET>; +- reset-names = "stmmaceth", "ahb"; +- +- status = "disabled"; +- }; +- +- gmac2: ethernet@37400000 { +- device_type = "network"; +- compatible = "qcom,ipq806x-gmac"; +- reg = <0x37400000 0x200000>; +- interrupts = ; +- interrupt-names = "macirq"; +- +- snps,axi-config = <&stmmac_axi_setup>; +- snps,pbl = <32>; +- snps,aal = <1>; +- +- qcom,nss-common = <&nss_common>; +- qcom,qsgmii-csr = <&qsgmii_csr>; +- +- clocks = <&gcc GMAC_CORE3_CLK>; +- clock-names = "stmmaceth"; +- +- resets = <&gcc GMAC_CORE3_RESET>, +- <&gcc GMAC_AHB_RESET>; +- reset-names = "stmmaceth", "ahb"; +- +- status = "disabled"; +- }; +- +- gmac3: ethernet@37600000 { +- device_type = "network"; +- compatible = "qcom,ipq806x-gmac"; +- reg = <0x37600000 0x200000>; +- interrupts = ; +- interrupt-names = "macirq"; +- +- snps,axi-config = <&stmmac_axi_setup>; +- snps,pbl = <32>; +- snps,aal = <1>; +- +- qcom,nss-common = <&nss_common>; +- qcom,qsgmii-csr = <&qsgmii_csr>; +- +- clocks = <&gcc GMAC_CORE4_CLK>; +- clock-names = "stmmaceth"; +- +- resets = <&gcc GMAC_CORE4_RESET>, +- <&gcc GMAC_AHB_RESET>; +- reset-names = "stmmaceth", "ahb"; +- +- status = "disabled"; +- }; +- +- hs_phy_0: phy@100f8800 { +- compatible = "qcom,ipq806x-usb-phy-hs"; +- reg = <0x100f8800 0x30>; +- clocks = <&gcc USB30_0_UTMI_CLK>; +- clock-names = "ref"; +- #phy-cells = <0>; +- +- status = "disabled"; +- }; +- +- ss_phy_0: phy@100f8830 { +- compatible = "qcom,ipq806x-usb-phy-ss"; +- reg = <0x100f8830 0x30>; +- clocks = <&gcc USB30_0_MASTER_CLK>; +- clock-names = "ref"; +- #phy-cells = <0>; +- +- status = "disabled"; +- }; +- +- usb3_0: usb3@100f8800 { +- compatible = "qcom,dwc3", "syscon"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x100f8800 0x8000>; +- clocks = <&gcc USB30_0_MASTER_CLK>; +- clock-names = "core"; +- +- ranges; +- +- resets = <&gcc USB30_0_MASTER_RESET>; +- reset-names = "master"; +- +- status = "disabled"; +- +- dwc3_0: dwc3@10000000 { +- compatible = "snps,dwc3"; +- reg = <0x10000000 0xcd00>; +- interrupts = ; +- phys = <&hs_phy_0>, <&ss_phy_0>; +- phy-names = "usb2-phy", "usb3-phy"; +- dr_mode = "host"; +- snps,dis_u3_susphy_quirk; +- }; +- }; +- +- hs_phy_1: phy@110f8800 { +- compatible = "qcom,ipq806x-usb-phy-hs"; +- reg = <0x110f8800 0x30>; +- clocks = <&gcc USB30_1_UTMI_CLK>; +- clock-names = "ref"; +- #phy-cells = <0>; +- }; +- +- ss_phy_1: phy@110f8830 { +- compatible = "qcom,ipq806x-usb-phy-ss"; +- reg = <0x110f8830 0x30>; +- clocks = <&gcc USB30_1_MASTER_CLK>; +- clock-names = "ref"; +- #phy-cells = <0>; +- }; +- +- usb3_1: usb3@110f8800 { +- compatible = "qcom,dwc3", "syscon"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x110f8800 0x8000>; +- clocks = <&gcc USB30_1_MASTER_CLK>; +- clock-names = "core"; +- +- ranges; +- +- resets = <&gcc USB30_1_MASTER_RESET>; +- reset-names = "master"; +- +- status = "disabled"; +- +- dwc3_1: dwc3@11000000 { +- compatible = "snps,dwc3"; +- reg = <0x11000000 0xcd00>; +- interrupts = ; +- phys = <&hs_phy_1>, <&ss_phy_1>; +- phy-names = "usb2-phy", "usb3-phy"; +- dr_mode = "host"; +- snps,dis_u3_susphy_quirk; +- }; +- }; +- +- vsdcc_fixed: vsdcc-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "SDCC Power"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- sdcc1bam: dma@12402000 { +- compatible = "qcom,bam-v1.3.0"; +- reg = <0x12402000 0x8000>; +- interrupts = ; +- clocks = <&gcc SDC1_H_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- }; +- +- sdcc3bam: dma@12182000 { +- compatible = "qcom,bam-v1.3.0"; +- reg = <0x12182000 0x8000>; +- interrupts = ; +- clocks = <&gcc SDC3_H_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- }; +- +- amba: amba { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- sdcc1: sdcc@12400000 { +- status = "disabled"; +- compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00051180>; +- reg = <0x12400000 0x2000>; +- interrupts = ; +- interrupt-names = "cmd_irq"; +- clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; +- clock-names = "mclk", "apb_pclk"; +- bus-width = <8>; +- max-frequency = <96000000>; +- non-removable; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- vmmc-supply = <&vsdcc_fixed>; +- dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; +- dma-names = "tx", "rx"; +- }; +- +- sdcc3: sdcc@12180000 { +- compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00051180>; +- status = "disabled"; +- reg = <0x12180000 0x2000>; +- interrupts = ; +- interrupt-names = "cmd_irq"; +- clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; +- clock-names = "mclk", "apb_pclk"; +- bus-width = <8>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <192000000>; +- sd-uhs-sdr104; +- sd-uhs-ddr50; +- vqmmc-supply = <&vsdcc_fixed>; +- dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; +- dma-names = "tx", "rx"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-mdm9615-wp8548-mangoh-green.dts b/scripts/dtc/include-prefixes/arm/qcom-mdm9615-wp8548-mangoh-green.dts +deleted file mode 100644 +index 942e3a2cac35..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-mdm9615-wp8548-mangoh-green.dts ++++ /dev/null +@@ -1,281 +0,0 @@ +-/* +- * Device Tree Source for mangOH Green Board with WP8548 Module +- * +- * Copyright (C) 2016 BayLibre, SAS. +- * Author : Neil Armstrong +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +- +-#include "qcom-mdm9615-wp8548.dtsi" +-#include +-#include +- +-/ { +- model = "MangOH Green with WP8548 Module"; +- compatible = "swir,mangoh-green-wp8548", "swir,wp8548", "qcom,mdm9615"; +- +- aliases { +- spi0 = &gsbi3_spi; +- serial0 = &gsbi4_serial; +- serial1 = &gsbi5_serial; +- i2c0 = &gsbi5_i2c; +- mmc0 = &sdcc1; +- }; +- +- chosen { +- stdout-path = "serial1:115200n8"; +- }; +-}; +- +-&msmgpio { +- /* MangOH GPIO Mapping : +- * - 2 : GPIOEXP_INT2 +- * - 7 : IOT1_GPIO2 +- * - 8 : IOT0_GPIO4 +- * - 13: IOT0_GPIO3 +- * - 21: IOT1_GPIO4 +- * - 22: IOT2_GPIO1 +- * - 23: IOT2_GPIO2 +- * - 24: IOT2_GPIO3 +- * - 25: IOT1_GPIO1 +- * - 32: IOT1_GPIO3 +- * - 33: IOT0_GPIO2 +- * - 42: IOT0_GPIO1 and SD Card Detect +- */ +- +- gpioext1_pins: gpioext1_pins { +- pins { +- pins = "gpio2"; +- function = "gpio"; +- input-enable; +- bias-disable; +- }; +- }; +- +- sdc_cd_pins: sdc_cd_pins { +- pins { +- pins = "gpio42"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- }; +-}; +- +-&gsbi3_spi { +- spi@0 { +- compatible = "swir,mangoh-iotport-spi", "spidev"; +- spi-max-frequency = <24000000>; +- reg = <0>; +- }; +-}; +- +-&gsbi5_i2c { +- mux@71 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x71>; +- +- i2c_iot0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c_iot1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- i2c_iot2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- usbhub: hub@8 { +- compatible = "smsc,usb3503a"; +- reg = <0x8>; +- connect-gpios = <&gpioext2 1 GPIO_ACTIVE_HIGH>; +- intn-gpios = <&gpioext2 0 GPIO_ACTIVE_HIGH>; +- initial-mode = <1>; +- }; +- }; +- +- i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- +- gpioext0: gpio@3e { +- /* GPIO Expander 0 Mapping : +- * - 0: ARDUINO_RESET_Level shift +- * - 1: BattChrgr_PG_N +- * - 2: BattGauge_GPIO +- * - 3: LED_ON (out active high) +- * - 4: ATmega_reset_GPIO +- * - 5: X +- * - 6: PCM_ANALOG_SELECT (out active high) +- * - 7: X +- * - 8: Board_rev_res1 (in) +- * - 9: Board_rev_res2 (in) +- * - 10: UART_EXP1_ENn (out active low / pull-down) +- * - 11: UART_EXP1_IN (out pull-down) +- * - 12: UART_EXP2_IN (out pull-down) +- * - 13: SDIO_SEL (out pull-down) +- * - 14: SPI_EXP1_ENn (out active low / pull-down) +- * - 15: SPI_EXP1_IN (out pull-down) +- */ +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- compatible = "semtech,sx1509q"; +- reg = <0x3e>; +- interrupt-parent = <&gpioext1>; +- interrupts = <0 IRQ_TYPE_EDGE_FALLING>; +- +- probe-reset; +- +- gpio-controller; +- interrupt-controller; +- }; +- }; +- +- i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- +- gpioext1: gpio@3f { +- /* GPIO Expander 1 Mapping : +- * - 0: GPIOEXP_INT1 +- * - 1: Battery detect +- * - 2: GPIO_SCF3_RESET +- * - 3: LED_CARD_DETECT_IOT0 (in) +- * - 4: LED_CARD_DETECT_IOT1 (in) +- * - 5: LED_CARD_DETECT_IOT2 (in) +- * - 6: UIM2_PWM_SELECT +- * - 7: UIM2_M2_S_SELECT +- * - 8: TP900 +- * - 9: SENSOR_INT1 (in) +- * - 10: SENSOR_INT2 (in) +- * - 11: CARD_DETECT_IOT0 (in pull-up) +- * - 12: CARD_DETECT_IOT2 (in pull-up) +- * - 13: CARD_DETECT_IOT1 (in pull-up) +- * - 14: GPIOEXP_INT3 (in active low / pull-up) +- * - 15: BattChrgr_INT_N +- */ +- pinctrl-0 = <&gpioext1_pins>; +- pinctrl-names = "default"; +- +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- compatible = "semtech,sx1509q"; +- reg = <0x3f>; +- interrupt-parent = <&msmgpio>; +- interrupts = <0 IRQ_TYPE_EDGE_FALLING>; +- +- probe-reset; +- +- gpio-controller; +- interrupt-controller; +- }; +- }; +- +- i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- +- gpioext2: gpio@70 { +- /* GPIO Expander 2 Mapping : +- * - 0: USB_HUB_INTn +- * - 1: HUB_CONNECT +- * - 2: GPIO_IOT2_RESET (out active low / pull-up) +- * - 3: GPIO_IOT1_RESET (out active low / pull-up) +- * - 4: GPIO_IOT0_RESET (out active low / pull-up) +- * - 5: TP901 +- * - 6: TP902 +- * - 7: TP903 +- * - 8: UART_EXP2_ENn (out active low / pull-down) +- * - 9: PCM_EXP1_ENn (out active low) +- * - 10: PCM_EXP1_SEL (out) +- * - 11: ARD_FTDI +- * - 12: TP904 +- * - 13: TP905 +- * - 14: TP906 +- * - 15: RS232_Enable (out active high / pull-up) +- */ +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- compatible = "semtech,sx1509q"; +- reg = <0x70>; +- interrupt-parent = <&gpioext1>; +- interrupts = <14 IRQ_TYPE_EDGE_FALLING>; +- +- probe-reset; +- +- gpio-controller; +- interrupt-controller; +- }; +- }; +- +- i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +-}; +- +-&sdcc1 { +- pinctrl-0 = <&sdc_cd_pins>; +- pinctrl-names = "default"; +- disable-wp; +- cd-gpios = <&msmgpio 42 GPIO_ACTIVE_LOW>; /* Active low CD */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-mdm9615-wp8548.dtsi b/scripts/dtc/include-prefixes/arm/qcom-mdm9615-wp8548.dtsi +deleted file mode 100644 +index a725b73b5a2e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-mdm9615-wp8548.dtsi ++++ /dev/null +@@ -1,171 +0,0 @@ +-/* +- * Device Tree Source for Sierra Wireless WP8548 Module +- * +- * Copyright (C) 2016 BayLibre, SAS. +- * Author : Neil Armstrong +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "qcom-mdm9615.dtsi" +- +-/ { +- model = "Sierra Wireless WP8548 Module"; +- compatible = "swir,wp8548", "qcom,mdm9615"; +- +- memory { +- device_type = "memory"; +- reg = <0x48000000 0x7F00000>; +- }; +-}; +- +-&msmgpio { +- pinctrl-0 = <&reset_out_pins>; +- pinctrl-names = "default"; +- +- gsbi3_pins: gsbi3_pins { +- mux { +- pins = "gpio8", "gpio9", "gpio10", "gpio11"; +- function = "gsbi3"; +- drive-strength = <8>; +- bias-disable; +- }; +- }; +- +- gsbi4_pins: gsbi4_pins { +- mux { +- pins = "gpio12", "gpio13", "gpio14", "gpio15"; +- function = "gsbi4"; +- drive-strength = <8>; +- bias-disable; +- }; +- }; +- +- gsbi5_i2c_pins: gsbi5_i2c_pins { +- pin16 { +- pins = "gpio16"; +- function = "gsbi5_i2c"; +- drive-strength = <8>; +- bias-disable; +- }; +- +- pin17 { +- pins = "gpio17"; +- function = "gsbi5_i2c"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- gsbi5_uart_pins: gsbi5_uart_pins { +- mux { +- pins = "gpio18", "gpio19"; +- function = "gsbi5_uart"; +- drive-strength = <8>; +- bias-disable; +- }; +- }; +- +- reset_out_pins: reset_out_pins { +- pins { +- pins = "gpio66"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-up; +- output-high; +- }; +- }; +-}; +- +-&pmicgpio { +- usb_vbus_5v_pins: usb_vbus_5v_pins { +- pins = "gpio4"; +- function = "normal"; +- output-high; +- bias-disable; +- qcom,drive-strength = <1>; +- power-source = <2>; +- }; +-}; +- +-&gsbi3 { +- status = "okay"; +- qcom,mode = ; +-}; +- +-&gsbi3_spi { +- status = "okay"; +- pinctrl-0 = <&gsbi3_pins>; +- pinctrl-names = "default"; +- assigned-clocks = <&gcc GSBI3_QUP_CLK>; +- assigned-clock-rates = <24000000>; +-}; +- +-&gsbi4 { +- status = "okay"; +- qcom,mode = ; +-}; +- +-&gsbi4_serial { +- status = "okay"; +- pinctrl-0 = <&gsbi4_pins>; +- pinctrl-names = "default"; +-}; +- +-&gsbi5 { +- status = "okay"; +- qcom,mode = ; +-}; +- +-&gsbi5_i2c { +- status = "okay"; +- clock-frequency = <200000>; +- pinctrl-0 = <&gsbi5_i2c_pins>; +- pinctrl-names = "default"; +-}; +- +-&gsbi5_serial { +- status = "okay"; +- pinctrl-0 = <&gsbi5_uart_pins>; +- pinctrl-names = "default"; +-}; +- +-&sdcc1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-mdm9615.dtsi b/scripts/dtc/include-prefixes/arm/qcom-mdm9615.dtsi +deleted file mode 100644 +index dda2ceec6591..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-mdm9615.dtsi ++++ /dev/null +@@ -1,554 +0,0 @@ +-/* +- * Device Tree Source for Qualcomm MDM9615 SoC +- * +- * Copyright (C) 2016 BayLibre, SAS. +- * Author : Neil Armstrong +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Qualcomm MDM9615"; +- compatible = "qcom,mdm9615"; +- interrupt-parent = <&intc>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a5"; +- device_type = "cpu"; +- next-level-cache = <&L2>; +- }; +- }; +- +- cpu-pmu { +- compatible = "arm,cortex-a5-pmu"; +- interrupts = ; +- }; +- +- clocks { +- cxo_board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <19200000>; +- }; +- }; +- +- regulators { +- vsdcc_fixed: vsdcc-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "SDCC Power"; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- regulator-always-on; +- }; +- }; +- +- soc: soc { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "simple-bus"; +- +- L2: cache-controller@2040000 { +- compatible = "arm,pl310-cache"; +- reg = <0x02040000 0x1000>; +- arm,data-latency = <2 2 0>; +- cache-unified; +- cache-level = <2>; +- }; +- +- intc: interrupt-controller@2000000 { +- compatible = "qcom,msm-qgic2"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x02000000 0x1000>, +- <0x02002000 0x1000>; +- }; +- +- timer@200a000 { +- compatible = "qcom,kpss-timer", "qcom,msm-timer"; +- interrupts = , +- , +- ; +- reg = <0x0200a000 0x100>; +- clock-frequency = <27000000>, +- <32768>; +- cpu-offset = <0x80000>; +- }; +- +- msmgpio: pinctrl@800000 { +- compatible = "qcom,mdm9615-pinctrl"; +- gpio-controller; +- gpio-ranges = <&msmgpio 0 0 88>; +- #gpio-cells = <2>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x800000 0x4000>; +- }; +- +- gcc: clock-controller@900000 { +- compatible = "qcom,gcc-mdm9615"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- reg = <0x900000 0x4000>; +- }; +- +- lcc: clock-controller@28000000 { +- compatible = "qcom,lcc-mdm9615"; +- reg = <0x28000000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- l2cc: clock-controller@2011000 { +- compatible = "syscon"; +- reg = <0x02011000 0x1000>; +- }; +- +- rng@1a500000 { +- compatible = "qcom,prng"; +- reg = <0x1a500000 0x200>; +- clocks = <&gcc PRNG_CLK>; +- clock-names = "core"; +- assigned-clocks = <&gcc PRNG_CLK>; +- assigned-clock-rates = <32000000>; +- }; +- +- gsbi2: gsbi@16100000 { +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <2>; +- reg = <0x16100000 0x100>; +- clocks = <&gcc GSBI2_H_CLK>; +- clock-names = "iface"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gsbi2_i2c: i2c@16180000 { +- compatible = "qcom,i2c-qup-v1.1.1"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x16180000 0x1000>; +- interrupts = ; +- +- clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- }; +- +- gsbi3: gsbi@16200000 { +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <3>; +- reg = <0x16200000 0x100>; +- clocks = <&gcc GSBI3_H_CLK>; +- clock-names = "iface"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gsbi3_spi: spi@16280000 { +- compatible = "qcom,spi-qup-v1.1.1"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x16280000 0x1000>; +- interrupts = ; +- spi-max-frequency = <24000000>; +- +- clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- }; +- +- gsbi4: gsbi@16300000 { +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <4>; +- reg = <0x16300000 0x100>; +- clocks = <&gcc GSBI4_H_CLK>; +- clock-names = "iface"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- syscon-tcsr = <&tcsr>; +- +- gsbi4_serial: serial@16340000 { +- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; +- reg = <0x16340000 0x1000>, +- <0x16300000 0x1000>; +- interrupts = ; +- clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- }; +- +- gsbi5: gsbi@16400000 { +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <5>; +- reg = <0x16400000 0x100>; +- clocks = <&gcc GSBI5_H_CLK>; +- clock-names = "iface"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- syscon-tcsr = <&tcsr>; +- +- gsbi5_i2c: i2c@16480000 { +- compatible = "qcom,i2c-qup-v1.1.1"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x16480000 0x1000>; +- interrupts = ; +- +- /* QUP clock is not initialized, set rate */ +- assigned-clocks = <&gcc GSBI5_QUP_CLK>; +- assigned-clock-rates = <24000000>; +- +- clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- gsbi5_serial: serial@16440000 { +- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; +- reg = <0x16440000 0x1000>, +- <0x16400000 0x1000>; +- interrupts = ; +- clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- }; +- +- qcom,ssbi@500000 { +- compatible = "qcom,ssbi"; +- reg = <0x500000 0x1000>; +- qcom,controller-type = "pmic-arbiter"; +- +- pmicintc: pmic@0 { +- compatible = "qcom,pm8018", "qcom,pm8921"; +- interrupts = ; +- #interrupt-cells = <2>; +- interrupt-controller; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pwrkey@1c { +- compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey"; +- reg = <0x1c>; +- interrupt-parent = <&pmicintc>; +- interrupts = <50 IRQ_TYPE_EDGE_RISING>, +- <51 IRQ_TYPE_EDGE_RISING>; +- debounce = <15625>; +- pull-up; +- }; +- +- pmicmpp: mpp@50 { +- compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp"; +- interrupt-parent = <&pmicintc>; +- interrupts = <24 IRQ_TYPE_NONE>, +- <25 IRQ_TYPE_NONE>, +- <26 IRQ_TYPE_NONE>, +- <27 IRQ_TYPE_NONE>, +- <28 IRQ_TYPE_NONE>, +- <29 IRQ_TYPE_NONE>; +- reg = <0x50>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- rtc@11d { +- compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc"; +- interrupt-parent = <&pmicintc>; +- interrupts = <39 IRQ_TYPE_EDGE_RISING>; +- reg = <0x11d>; +- allow-set-time; +- }; +- +- pmicgpio: gpio@150 { +- compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio"; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pmicgpio 0 0 6>; +- #gpio-cells = <2>; +- }; +- }; +- }; +- +- sdcc1bam: dma@12182000{ +- compatible = "qcom,bam-v1.3.0"; +- reg = <0x12182000 0x8000>; +- interrupts = ; +- clocks = <&gcc SDC1_H_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- }; +- +- sdcc2bam: dma@12142000{ +- compatible = "qcom,bam-v1.3.0"; +- reg = <0x12142000 0x8000>; +- interrupts = ; +- clocks = <&gcc SDC2_H_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- }; +- +- amba { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- sdcc1: sdcc@12180000 { +- status = "disabled"; +- compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00051180>; +- reg = <0x12180000 0x2000>; +- interrupts = ; +- interrupt-names = "cmd_irq"; +- clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; +- clock-names = "mclk", "apb_pclk"; +- bus-width = <8>; +- max-frequency = <48000000>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- vmmc-supply = <&vsdcc_fixed>; +- dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; +- dma-names = "tx", "rx"; +- assigned-clocks = <&gcc SDC1_CLK>; +- assigned-clock-rates = <400000>; +- }; +- +- sdcc2: sdcc@12140000 { +- compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00051180>; +- status = "disabled"; +- reg = <0x12140000 0x2000>; +- interrupts = ; +- interrupt-names = "cmd_irq"; +- clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; +- clock-names = "mclk", "apb_pclk"; +- bus-width = <4>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <48000000>; +- no-1-8-v; +- vmmc-supply = <&vsdcc_fixed>; +- dmas = <&sdcc2bam 2>, <&sdcc2bam 1>; +- dma-names = "tx", "rx"; +- assigned-clocks = <&gcc SDC2_CLK>; +- assigned-clock-rates = <400000>; +- }; +- }; +- +- tcsr: syscon@1a400000 { +- compatible = "qcom,tcsr-mdm9615", "syscon"; +- reg = <0x1a400000 0x100>; +- }; +- +- rpm: rpm@108000 { +- compatible = "qcom,rpm-mdm9615"; +- reg = <0x108000 0x1000>; +- +- qcom,ipc = <&l2cc 0x8 2>; +- +- interrupts = , +- , +- ; +- interrupt-names = "ack", "err", "wakeup"; +- +- regulators { +- compatible = "qcom,rpm-pm8018-regulators"; +- +- vin_lvs1-supply = <&pm8018_s3>; +- +- vdd_l7-supply = <&pm8018_s4>; +- vdd_l8-supply = <&pm8018_s3>; +- vdd_l9_l10_l11_l12-supply = <&pm8018_s5>; +- +- /* Buck SMPS */ +- pm8018_s1: s1 { +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1150000>; +- qcom,switch-mode-frequency = <1600000>; +- bias-pull-down; +- }; +- +- pm8018_s2: s2 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1300000>; +- qcom,switch-mode-frequency = <1600000>; +- bias-pull-down; +- }; +- +- pm8018_s3: s3 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- qcom,switch-mode-frequency = <1600000>; +- bias-pull-down; +- }; +- +- pm8018_s4: s4 { +- regulator-min-microvolt = <2100000>; +- regulator-max-microvolt = <2200000>; +- qcom,switch-mode-frequency = <1600000>; +- bias-pull-down; +- }; +- +- pm8018_s5: s5 { +- regulator-always-on; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- qcom,switch-mode-frequency = <1600000>; +- bias-pull-down; +- }; +- +- /* PMOS LDO */ +- pm8018_l2: l2 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- bias-pull-down; +- }; +- +- pm8018_l3: l3 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- bias-pull-down; +- }; +- +- pm8018_l4: l4 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- bias-pull-down; +- }; +- +- pm8018_l5: l5 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- bias-pull-down; +- }; +- +- pm8018_l6: l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2850000>; +- bias-pull-down; +- }; +- +- pm8018_l7: l7 { +- regulator-min-microvolt = <1850000>; +- regulator-max-microvolt = <1900000>; +- bias-pull-down; +- }; +- +- pm8018_l8: l8 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- bias-pull-down; +- }; +- +- pm8018_l9: l9 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1150000>; +- bias-pull-down; +- }; +- +- pm8018_l10: l10 { +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- bias-pull-down; +- }; +- +- pm8018_l11: l11 { +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- bias-pull-down; +- }; +- +- pm8018_l12: l12 { +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- bias-pull-down; +- }; +- +- pm8018_l13: l13 { +- regulator-min-microvolt = <1850000>; +- regulator-max-microvolt = <2950000>; +- bias-pull-down; +- }; +- +- pm8018_l14: l14 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- bias-pull-down; +- }; +- +- /* Low Voltage Switch */ +- pm8018_lvs1: lvs1 { +- bias-pull-down; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-msm8226-samsung-s3ve3g.dts b/scripts/dtc/include-prefixes/arm/qcom-msm8226-samsung-s3ve3g.dts +deleted file mode 100644 +index d159188c8b95..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-msm8226-samsung-s3ve3g.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-#include "qcom-msm8226.dtsi" +- +-/ { +- model = "Samsung Galaxy S III Neo"; +- compatible = "samsung,s3ve3g", "qcom,msm8226"; +- +- aliases { +- serial0 = &blsp1_uart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&soc { +- serial@f991f000 { +- status = "ok"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-msm8226.dtsi b/scripts/dtc/include-prefixes/arm/qcom-msm8226.dtsi +deleted file mode 100644 +index 2de69d56870d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-msm8226.dtsi ++++ /dev/null +@@ -1,147 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&intc>; +- +- chosen { }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0>; +- }; +- +- soc: soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- intc: interrupt-controller@f9000000 { +- compatible = "qcom,msm-qgic2"; +- reg = <0xf9000000 0x1000>, +- <0xf9002000 0x1000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- +- gcc: clock-controller@fc400000 { +- compatible = "qcom,gcc-msm8226"; +- reg = <0xfc400000 0x4000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- }; +- +- tlmm: pinctrl@fd510000 { +- compatible = "qcom,msm8226-pinctrl"; +- reg = <0xfd510000 0x4000>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&tlmm 0 0 117>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- +- blsp1_uart3: serial@f991f000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0xf991f000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- restart@fc4ab000 { +- compatible = "qcom,pshold"; +- reg = <0xfc4ab000 0x4>; +- }; +- +- rng@f9bff000 { +- compatible = "qcom,prng"; +- reg = <0xf9bff000 0x200>; +- clocks = <&gcc GCC_PRNG_AHB_CLK>; +- clock-names = "core"; +- }; +- +- timer@f9020000 { +- compatible = "arm,armv7-timer-mem"; +- reg = <0xf9020000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- frame@f9021000 { +- frame-number = <0>; +- interrupts = , +- ; +- reg = <0xf9021000 0x1000>, +- <0xf9022000 0x1000>; +- }; +- +- frame@f9023000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0xf9023000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9024000 { +- frame-number = <2>; +- interrupts = ; +- reg = <0xf9024000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9025000 { +- frame-number = <3>; +- interrupts = ; +- reg = <0xf9025000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9026000 { +- frame-number = <4>; +- interrupts = ; +- reg = <0xf9026000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9027000 { +- frame-number = <5>; +- interrupts = ; +- reg = <0xf9027000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9028000 { +- frame-number = <6>; +- interrupts = ; +- reg = <0xf9028000 0x1000>; +- status = "disabled"; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-msm8660-surf.dts b/scripts/dtc/include-prefixes/arm/qcom-msm8660-surf.dts +deleted file mode 100644 +index 6a321ccb0bd0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-msm8660-surf.dts ++++ /dev/null +@@ -1,78 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +- +-#include "qcom-msm8660.dtsi" +- +-/ { +- model = "Qualcomm MSM8660 SURF"; +- compatible = "qcom,msm8660-surf", "qcom,msm8660"; +- +- aliases { +- serial0 = &gsbi12_serial; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- soc { +- gsbi@19c00000 { +- status = "okay"; +- qcom,mode = ; +- serial@19c40000 { +- status = "okay"; +- }; +- }; +- +- /* Temporary fixed regulator */ +- vsdcc_fixed: vsdcc-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "SDCC Power"; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- regulator-always-on; +- }; +- +- amba { +- /* eMMC */ +- sdcc1: sdcc@12400000 { +- status = "okay"; +- vmmc-supply = <&vsdcc_fixed>; +- }; +- +- /* External micro SD card */ +- sdcc3: sdcc@12180000 { +- status = "okay"; +- vmmc-supply = <&vsdcc_fixed>; +- }; +- }; +- }; +-}; +- +-&pm8058 { +- keypad@148 { +- linux,keymap = < +- MATRIX_KEY(0, 0, KEY_FN_F1) +- MATRIX_KEY(0, 1, KEY_UP) +- MATRIX_KEY(0, 2, KEY_LEFT) +- MATRIX_KEY(0, 3, KEY_VOLUMEUP) +- MATRIX_KEY(1, 0, KEY_FN_F2) +- MATRIX_KEY(1, 1, KEY_RIGHT) +- MATRIX_KEY(1, 2, KEY_DOWN) +- MATRIX_KEY(1, 3, KEY_VOLUMEDOWN) +- MATRIX_KEY(2, 3, KEY_ENTER) +- MATRIX_KEY(4, 0, KEY_CAMERA_FOCUS) +- MATRIX_KEY(4, 1, KEY_UP) +- MATRIX_KEY(4, 2, KEY_LEFT) +- MATRIX_KEY(4, 3, KEY_HOME) +- MATRIX_KEY(4, 4, KEY_FN_F3) +- MATRIX_KEY(5, 0, KEY_CAMERA) +- MATRIX_KEY(5, 1, KEY_RIGHT) +- MATRIX_KEY(5, 2, KEY_DOWN) +- MATRIX_KEY(5, 3, KEY_BACK) +- MATRIX_KEY(5, 4, KEY_MENU) +- >; +- keypad,num-rows = <6>; +- keypad,num-columns = <5>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-msm8660.dtsi b/scripts/dtc/include-prefixes/arm/qcom-msm8660.dtsi +deleted file mode 100644 +index 480fc08cbe8e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-msm8660.dtsi ++++ /dev/null +@@ -1,581 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Qualcomm MSM8660"; +- compatible = "qcom,msm8660"; +- interrupt-parent = <&intc>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "qcom,scorpion"; +- enable-method = "qcom,gcc-msm8660"; +- device_type = "cpu"; +- reg = <0>; +- next-level-cache = <&L2>; +- }; +- +- cpu@1 { +- compatible = "qcom,scorpion"; +- enable-method = "qcom,gcc-msm8660"; +- device_type = "cpu"; +- reg = <1>; +- next-level-cache = <&L2>; +- }; +- +- L2: l2-cache { +- compatible = "cache"; +- cache-level = <2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; +- }; +- +- cpu-pmu { +- compatible = "qcom,scorpion-mp-pmu"; +- interrupts = <1 9 0x304>; +- }; +- +- clocks { +- cxo_board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <19200000>; +- }; +- +- pxo_board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- }; +- +- sleep_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- }; +- +- /* +- * These channels from the ADC are simply hardware monitors. +- * That is why the ADC is referred to as "HKADC" - HouseKeeping +- * ADC. +- */ +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&xoadc 0x00 0x01>, /* Battery */ +- <&xoadc 0x00 0x02>, /* DC in (charger) */ +- <&xoadc 0x00 0x04>, /* VPH the main system voltage */ +- <&xoadc 0x00 0x0b>, /* Die temperature */ +- <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ +- <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ +- <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */ +- }; +- +- soc: soc { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "simple-bus"; +- +- intc: interrupt-controller@2080000 { +- compatible = "qcom,msm-8660-qgic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = < 0x02080000 0x1000 >, +- < 0x02081000 0x1000 >; +- }; +- +- timer@2000000 { +- compatible = "qcom,scss-timer", "qcom,msm-timer"; +- interrupts = <1 0 0x301>, +- <1 1 0x301>, +- <1 2 0x301>; +- reg = <0x02000000 0x100>; +- clock-frequency = <27000000>, +- <32768>; +- cpu-offset = <0x40000>; +- }; +- +- tlmm: pinctrl@800000 { +- compatible = "qcom,msm8660-pinctrl"; +- reg = <0x800000 0x4000>; +- +- gpio-controller; +- gpio-ranges = <&tlmm 0 0 173>; +- #gpio-cells = <2>; +- interrupts = <0 16 0x4>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- }; +- +- gcc: clock-controller@900000 { +- compatible = "qcom,gcc-msm8660"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- reg = <0x900000 0x4000>; +- }; +- +- gsbi6: gsbi@16500000 { +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <12>; +- reg = <0x16500000 0x100>; +- clocks = <&gcc GSBI6_H_CLK>; +- clock-names = "iface"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- +- syscon-tcsr = <&tcsr>; +- +- gsbi6_serial: serial@16540000 { +- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; +- reg = <0x16540000 0x1000>, +- <0x16500000 0x1000>; +- interrupts = ; +- clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- gsbi6_i2c: i2c@16580000 { +- compatible = "qcom,i2c-qup-v1.1.1"; +- reg = <0x16580000 0x1000>; +- interrupts = ; +- clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; +- clock-names = "core", "iface"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- gsbi7: gsbi@16600000 { +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <12>; +- reg = <0x16600000 0x100>; +- clocks = <&gcc GSBI7_H_CLK>; +- clock-names = "iface"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- +- syscon-tcsr = <&tcsr>; +- +- gsbi7_serial: serial@16640000 { +- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; +- reg = <0x16640000 0x1000>, +- <0x16600000 0x1000>; +- interrupts = ; +- clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- gsbi7_i2c: i2c@16680000 { +- compatible = "qcom,i2c-qup-v1.1.1"; +- reg = <0x16680000 0x1000>; +- interrupts = ; +- clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; +- clock-names = "core", "iface"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- gsbi8: gsbi@19800000 { +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <12>; +- reg = <0x19800000 0x100>; +- clocks = <&gcc GSBI8_H_CLK>; +- clock-names = "iface"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- syscon-tcsr = <&tcsr>; +- +- gsbi8_i2c: i2c@19880000 { +- compatible = "qcom,i2c-qup-v1.1.1"; +- reg = <0x19880000 0x1000>; +- interrupts = ; +- clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>; +- clock-names = "core", "iface"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- gsbi12: gsbi@19c00000 { +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <12>; +- reg = <0x19c00000 0x100>; +- clocks = <&gcc GSBI12_H_CLK>; +- clock-names = "iface"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- syscon-tcsr = <&tcsr>; +- +- gsbi12_serial: serial@19c40000 { +- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; +- reg = <0x19c40000 0x1000>, +- <0x19c00000 0x1000>; +- interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- gsbi12_i2c: i2c@19c80000 { +- compatible = "qcom,i2c-qup-v1.1.1"; +- reg = <0x19c80000 0x1000>; +- interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; +- clock-names = "core", "iface"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- external-bus@1a100000 { +- compatible = "qcom,msm8660-ebi2"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0x0 0x1a800000 0x00800000>, +- <1 0x0 0x1b000000 0x00800000>, +- <2 0x0 0x1b800000 0x00800000>, +- <3 0x0 0x1d000000 0x08000000>, +- <4 0x0 0x1c800000 0x00800000>, +- <5 0x0 0x1c000000 0x00800000>; +- reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>; +- reg-names = "ebi2", "xmem"; +- clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>; +- clock-names = "ebi2x", "ebi2"; +- status = "disabled"; +- }; +- +- qcom,ssbi@500000 { +- compatible = "qcom,ssbi"; +- reg = <0x500000 0x1000>; +- qcom,controller-type = "pmic-arbiter"; +- +- pm8058: pmic@0 { +- compatible = "qcom,pm8058"; +- interrupt-parent = <&tlmm>; +- interrupts = <88 8>; +- #interrupt-cells = <2>; +- interrupt-controller; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm8058_gpio: gpio@150 { +- compatible = "qcom,pm8058-gpio", +- "qcom,ssbi-gpio"; +- reg = <0x150>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pm8058_gpio 0 0 44>; +- #gpio-cells = <2>; +- +- }; +- +- pm8058_mpps: mpps@50 { +- compatible = "qcom,pm8058-mpp", +- "qcom,ssbi-mpp"; +- reg = <0x50>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&pm8058>; +- interrupts = +- <128 IRQ_TYPE_NONE>, +- <129 IRQ_TYPE_NONE>, +- <130 IRQ_TYPE_NONE>, +- <131 IRQ_TYPE_NONE>, +- <132 IRQ_TYPE_NONE>, +- <133 IRQ_TYPE_NONE>, +- <134 IRQ_TYPE_NONE>, +- <135 IRQ_TYPE_NONE>, +- <136 IRQ_TYPE_NONE>, +- <137 IRQ_TYPE_NONE>, +- <138 IRQ_TYPE_NONE>, +- <139 IRQ_TYPE_NONE>; +- }; +- +- pwrkey@1c { +- compatible = "qcom,pm8058-pwrkey"; +- reg = <0x1c>; +- interrupt-parent = <&pm8058>; +- interrupts = <50 1>, <51 1>; +- debounce = <15625>; +- pull-up; +- }; +- +- keypad@148 { +- compatible = "qcom,pm8058-keypad"; +- reg = <0x148>; +- interrupt-parent = <&pm8058>; +- interrupts = <74 1>, <75 1>; +- debounce = <15>; +- scan-delay = <32>; +- row-hold = <91500>; +- }; +- +- xoadc: xoadc@197 { +- compatible = "qcom,pm8058-adc"; +- reg = <0x197>; +- interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>; +- #address-cells = <2>; +- #size-cells = <0>; +- #io-channel-cells = <2>; +- +- vcoin: adc-channel@0 { +- reg = <0x00 0x00>; +- }; +- vbat: adc-channel@1 { +- reg = <0x00 0x01>; +- }; +- dcin: adc-channel@2 { +- reg = <0x00 0x02>; +- }; +- ichg: adc-channel@3 { +- reg = <0x00 0x03>; +- }; +- vph_pwr: adc-channel@4 { +- reg = <0x00 0x04>; +- }; +- usb_vbus: adc-channel@a { +- reg = <0x00 0x0a>; +- }; +- die_temp: adc-channel@b { +- reg = <0x00 0x0b>; +- }; +- ref_625mv: adc-channel@c { +- reg = <0x00 0x0c>; +- }; +- ref_1250mv: adc-channel@d { +- reg = <0x00 0x0d>; +- }; +- ref_325mv: adc-channel@e { +- reg = <0x00 0x0e>; +- }; +- ref_muxoff: adc-channel@f { +- reg = <0x00 0x0f>; +- }; +- }; +- +- rtc@1e8 { +- compatible = "qcom,pm8058-rtc"; +- reg = <0x1e8>; +- interrupt-parent = <&pm8058>; +- interrupts = <39 1>; +- allow-set-time; +- }; +- +- vibrator@4a { +- compatible = "qcom,pm8058-vib"; +- reg = <0x4a>; +- }; +- }; +- }; +- +- l2cc: clock-controller@2082000 { +- compatible = "syscon"; +- reg = <0x02082000 0x1000>; +- }; +- +- rpm: rpm@104000 { +- compatible = "qcom,rpm-msm8660"; +- reg = <0x00104000 0x1000>; +- qcom,ipc = <&l2cc 0x8 2>; +- +- interrupts = , +- , +- ; +- interrupt-names = "ack", "err", "wakeup"; +- clocks = <&gcc RPM_MSG_RAM_H_CLK>; +- clock-names = "ram"; +- +- rpmcc: clock-controller { +- compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; +- #clock-cells = <1>; +- }; +- +- pm8901-regulators { +- compatible = "qcom,rpm-pm8901-regulators"; +- +- pm8901_l0: l0 {}; +- pm8901_l1: l1 {}; +- pm8901_l2: l2 {}; +- pm8901_l3: l3 {}; +- pm8901_l4: l4 {}; +- pm8901_l5: l5 {}; +- pm8901_l6: l6 {}; +- +- /* S0 and S1 Handled as SAW regulators by SPM */ +- pm8901_s2: s2 {}; +- pm8901_s3: s3 {}; +- pm8901_s4: s4 {}; +- +- pm8901_lvs0: lvs0 {}; +- pm8901_lvs1: lvs1 {}; +- pm8901_lvs2: lvs2 {}; +- pm8901_lvs3: lvs3 {}; +- +- pm8901_mvs: mvs {}; +- }; +- +- pm8058-regulators { +- compatible = "qcom,rpm-pm8058-regulators"; +- +- pm8058_l0: l0 {}; +- pm8058_l1: l1 {}; +- pm8058_l2: l2 {}; +- pm8058_l3: l3 {}; +- pm8058_l4: l4 {}; +- pm8058_l5: l5 {}; +- pm8058_l6: l6 {}; +- pm8058_l7: l7 {}; +- pm8058_l8: l8 {}; +- pm8058_l9: l9 {}; +- pm8058_l10: l10 {}; +- pm8058_l11: l11 {}; +- pm8058_l12: l12 {}; +- pm8058_l13: l13 {}; +- pm8058_l14: l14 {}; +- pm8058_l15: l15 {}; +- pm8058_l16: l16 {}; +- pm8058_l17: l17 {}; +- pm8058_l18: l18 {}; +- pm8058_l19: l19 {}; +- pm8058_l20: l20 {}; +- pm8058_l21: l21 {}; +- pm8058_l22: l22 {}; +- pm8058_l23: l23 {}; +- pm8058_l24: l24 {}; +- pm8058_l25: l25 {}; +- +- pm8058_s0: s0 {}; +- pm8058_s1: s1 {}; +- pm8058_s2: s2 {}; +- pm8058_s3: s3 {}; +- pm8058_s4: s4 {}; +- +- pm8058_lvs0: lvs0 {}; +- pm8058_lvs1: lvs1 {}; +- +- pm8058_ncp: ncp {}; +- }; +- }; +- +- amba { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- sdcc1: sdcc@12400000 { +- status = "disabled"; +- compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00051180>; +- reg = <0x12400000 0x8000>; +- interrupts = ; +- interrupt-names = "cmd_irq"; +- clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; +- clock-names = "mclk", "apb_pclk"; +- bus-width = <8>; +- max-frequency = <48000000>; +- non-removable; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- }; +- +- sdcc2: sdcc@12140000 { +- status = "disabled"; +- compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00051180>; +- reg = <0x12140000 0x8000>; +- interrupts = ; +- interrupt-names = "cmd_irq"; +- clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; +- clock-names = "mclk", "apb_pclk"; +- bus-width = <8>; +- max-frequency = <48000000>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- }; +- +- sdcc3: sdcc@12180000 { +- compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00051180>; +- status = "disabled"; +- reg = <0x12180000 0x8000>; +- interrupts = ; +- interrupt-names = "cmd_irq"; +- clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; +- clock-names = "mclk", "apb_pclk"; +- bus-width = <4>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <48000000>; +- no-1-8-v; +- }; +- +- sdcc4: sdcc@121c0000 { +- compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00051180>; +- status = "disabled"; +- reg = <0x121c0000 0x8000>; +- interrupts = ; +- interrupt-names = "cmd_irq"; +- clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; +- clock-names = "mclk", "apb_pclk"; +- bus-width = <4>; +- max-frequency = <48000000>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- }; +- +- sdcc5: sdcc@12200000 { +- compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00051180>; +- status = "disabled"; +- reg = <0x12200000 0x8000>; +- interrupts = ; +- interrupt-names = "cmd_irq"; +- clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; +- clock-names = "mclk", "apb_pclk"; +- bus-width = <4>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <48000000>; +- }; +- }; +- +- tcsr: syscon@1a400000 { +- compatible = "qcom,tcsr-msm8660", "syscon"; +- reg = <0x1a400000 0x100>; +- }; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-msm8960-cdp.dts b/scripts/dtc/include-prefixes/arm/qcom-msm8960-cdp.dts +deleted file mode 100644 +index e7d2e937ea4c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-msm8960-cdp.dts ++++ /dev/null +@@ -1,354 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +- +-#include "qcom-msm8960.dtsi" +- +-/ { +- model = "Qualcomm MSM8960 CDP"; +- compatible = "qcom,msm8960-cdp", "qcom,msm8960"; +- +- aliases { +- serial0 = &gsbi5_serial; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- soc { +- gsbi@16400000 { +- status = "okay"; +- qcom,mode = ; +- serial@16440000 { +- status = "okay"; +- }; +- }; +- +- amba { +- /* eMMC */ +- sdcc1: sdcc@12400000 { +- status = "okay"; +- }; +- +- /* External micro SD card */ +- sdcc3: sdcc@12180000 { +- status = "okay"; +- }; +- }; +- +- rpm@108000 { +- regulators { +- compatible = "qcom,rpm-pm8921-regulators"; +- vin_lvs1_3_6-supply = <&pm8921_s4>; +- vin_lvs2-supply = <&pm8921_s4>; +- vin_lvs4_5_7-supply = <&pm8921_s4>; +- vdd_ncp-supply = <&pm8921_l6>; +- vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; +- vdd_l21_l23_l29-supply = <&pm8921_s8>; +- vdd_l24-supply = <&pm8921_s1>; +- vdd_l25-supply = <&pm8921_s1>; +- vdd_l27-supply = <&pm8921_s7>; +- vdd_l28-supply = <&pm8921_s7>; +- +- /* Buck SMPS */ +- pm8921_s1: s1 { +- regulator-always-on; +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- qcom,switch-mode-frequency = <3200000>; +- bias-pull-down; +- }; +- +- pm8921_s2: s2 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- qcom,switch-mode-frequency = <1600000>; +- bias-pull-down; +- }; +- +- pm8921_s3: s3 { +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1150000>; +- qcom,switch-mode-frequency = <4800000>; +- bias-pull-down; +- }; +- +- pm8921_s4: s4 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- qcom,switch-mode-frequency = <1600000>; +- bias-pull-down; +- qcom,force-mode = ; +- }; +- +- pm8921_s7: s7 { +- regulator-min-microvolt = <1150000>; +- regulator-max-microvolt = <1150000>; +- qcom,switch-mode-frequency = <3200000>; +- bias-pull-down; +- }; +- +- pm8921_s8: s8 { +- regulator-always-on; +- regulator-min-microvolt = <2050000>; +- regulator-max-microvolt = <2050000>; +- qcom,switch-mode-frequency = <1600000>; +- bias-pull-down; +- }; +- +- /* PMOS LDO */ +- pm8921_l1: l1 { +- regulator-always-on; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- bias-pull-down; +- }; +- +- pm8921_l2: l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- bias-pull-down; +- }; +- +- pm8921_l3: l3 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- bias-pull-down; +- }; +- +- pm8921_l4: l4 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- bias-pull-down; +- }; +- +- pm8921_l5: l5 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- bias-pull-down; +- }; +- +- pm8921_l6: l6 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- bias-pull-down; +- }; +- +- pm8921_l7: l7 { +- regulator-always-on; +- regulator-min-microvolt = <1850000>; +- regulator-max-microvolt = <2950000>; +- bias-pull-down; +- }; +- +- pm8921_l8: l8 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <3000000>; +- bias-pull-down; +- }; +- +- pm8921_l9: l9 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- bias-pull-down; +- }; +- +- pm8921_l10: l10 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- bias-pull-down; +- }; +- +- pm8921_l11: l11 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- bias-pull-down; +- }; +- +- pm8921_l12: l12 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- bias-pull-down; +- }; +- +- pm8921_l14: l14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- bias-pull-down; +- }; +- +- pm8921_l15: l15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- bias-pull-down; +- }; +- +- pm8921_l16: l16 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- bias-pull-down; +- }; +- +- pm8921_l17: l17 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- bias-pull-down; +- }; +- +- pm8921_l18: l18 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- bias-pull-down; +- }; +- +- pm8921_l21: l21 { +- regulator-min-microvolt = <1900000>; +- regulator-max-microvolt = <1900000>; +- bias-pull-down; +- }; +- +- pm8921_l22: l22 { +- regulator-min-microvolt = <2750000>; +- regulator-max-microvolt = <2750000>; +- bias-pull-down; +- }; +- +- pm8921_l23: l23 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- bias-pull-down; +- }; +- +- pm8921_l24: l24 { +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1150000>; +- bias-pull-down; +- }; +- +- pm8921_l25: l25 { +- regulator-always-on; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- bias-pull-down; +- }; +- +- /* Low Voltage Switch */ +- pm8921_lvs1: lvs1 { +- bias-pull-down; +- }; +- +- pm8921_lvs2: lvs2 { +- bias-pull-down; +- }; +- +- pm8921_lvs3: lvs3 { +- bias-pull-down; +- }; +- +- pm8921_lvs4: lvs4 { +- bias-pull-down; +- }; +- +- pm8921_lvs5: lvs5 { +- bias-pull-down; +- }; +- +- pm8921_lvs6: lvs6 { +- bias-pull-down; +- }; +- +- pm8921_lvs7: lvs7 { +- bias-pull-down; +- }; +- +- pm8921_ncp: ncp { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- qcom,switch-mode-frequency = <1600000>; +- }; +- }; +- }; +- +- gsbi@16000000 { +- status = "okay"; +- qcom,mode = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_default>; +- spi@16080000 { +- status = "okay"; +- eth@0 { +- compatible = "micrel,ks8851"; +- reg = <0>; +- interrupt-parent = <&msmgpio>; +- interrupts = <90 8>; +- spi-max-frequency = <5400000>; +- vdd-supply = <&ext_l2>; +- vdd-io-supply = <&pm8921_lvs6>; +- reset-gpios = <&msmgpio 89 0>; +- }; +- }; +- }; +- +- pinctrl@800000 { +- spi1_default: spi1_default { +- mux { +- pins = "gpio6", "gpio7", "gpio9"; +- function = "gsbi1"; +- }; +- +- mosi { +- pins = "gpio6"; +- drive-strength = <12>; +- bias-disable; +- }; +- +- miso { +- pins = "gpio7"; +- drive-strength = <12>; +- bias-disable; +- }; +- +- cs { +- pins = "gpio8"; +- drive-strength = <12>; +- bias-disable; +- output-low; +- }; +- +- clk { +- pins = "gpio9"; +- drive-strength = <12>; +- bias-disable; +- }; +- }; +- }; +- }; +- +- regulators { +- compatible = "simple-bus"; +- +- ext_l2: gpio-regulator@91 { +- compatible = "regulator-fixed"; +- regulator-name = "ext_l2"; +- gpio = <&msmgpio 91 0>; +- startup-delay-us = <10000>; +- enable-active-high; +- }; +- }; +-}; +- +-&pmicintc { +- keypad@148 { +- linux,keymap = < +- MATRIX_KEY(0, 0, KEY_VOLUMEUP) +- MATRIX_KEY(0, 1, KEY_VOLUMEDOWN) +- MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS) +- MATRIX_KEY(0, 3, KEY_CAMERA) +- >; +- keypad,num-rows = <1>; +- keypad,num-columns = <5>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-msm8960.dtsi b/scripts/dtc/include-prefixes/arm/qcom-msm8960.dtsi +deleted file mode 100644 +index 172ea3c70eac..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-msm8960.dtsi ++++ /dev/null +@@ -1,331 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Qualcomm MSM8960"; +- compatible = "qcom,msm8960"; +- interrupt-parent = <&intc>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <1 14 0x304>; +- +- cpu@0 { +- compatible = "qcom,krait"; +- enable-method = "qcom,kpss-acc-v1"; +- device_type = "cpu"; +- reg = <0>; +- next-level-cache = <&L2>; +- qcom,acc = <&acc0>; +- qcom,saw = <&saw0>; +- }; +- +- cpu@1 { +- compatible = "qcom,krait"; +- enable-method = "qcom,kpss-acc-v1"; +- device_type = "cpu"; +- reg = <1>; +- next-level-cache = <&L2>; +- qcom,acc = <&acc1>; +- qcom,saw = <&saw1>; +- }; +- +- L2: l2-cache { +- compatible = "cache"; +- cache-level = <2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; +- }; +- +- cpu-pmu { +- compatible = "qcom,krait-pmu"; +- interrupts = <1 10 0x304>; +- qcom,no-pc-write; +- }; +- +- clocks { +- cxo_board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <19200000>; +- clock-output-names = "cxo_board"; +- }; +- +- pxo_board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- clock-output-names = "pxo_board"; +- }; +- +- sleep_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "sleep_clk"; +- }; +- }; +- +- soc: soc { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "simple-bus"; +- +- intc: interrupt-controller@2000000 { +- compatible = "qcom,msm-qgic2"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x02000000 0x1000>, +- <0x02002000 0x1000>; +- }; +- +- timer@200a000 { +- compatible = "qcom,kpss-timer", +- "qcom,kpss-wdt-msm8960", "qcom,msm-timer"; +- interrupts = <1 1 0x301>, +- <1 2 0x301>, +- <1 3 0x301>; +- reg = <0x0200a000 0x100>; +- clock-frequency = <27000000>, +- <32768>; +- cpu-offset = <0x80000>; +- }; +- +- msmgpio: pinctrl@800000 { +- compatible = "qcom,msm8960-pinctrl"; +- gpio-controller; +- gpio-ranges = <&msmgpio 0 0 152>; +- #gpio-cells = <2>; +- interrupts = <0 16 0x4>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x800000 0x4000>; +- }; +- +- gcc: clock-controller@900000 { +- compatible = "qcom,gcc-msm8960"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- reg = <0x900000 0x4000>; +- }; +- +- lcc: clock-controller@28000000 { +- compatible = "qcom,lcc-msm8960"; +- reg = <0x28000000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- clock-controller@4000000 { +- compatible = "qcom,mmcc-msm8960"; +- reg = <0x4000000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- l2cc: clock-controller@2011000 { +- compatible = "syscon"; +- reg = <0x2011000 0x1000>; +- }; +- +- rpm@108000 { +- compatible = "qcom,rpm-msm8960"; +- reg = <0x108000 0x1000>; +- qcom,ipc = <&l2cc 0x8 2>; +- +- interrupts = <0 19 0>, <0 21 0>, <0 22 0>; +- interrupt-names = "ack", "err", "wakeup"; +- +- regulators { +- compatible = "qcom,rpm-pm8921-regulators"; +- }; +- }; +- +- acc0: clock-controller@2088000 { +- compatible = "qcom,kpss-acc-v1"; +- reg = <0x02088000 0x1000>, <0x02008000 0x1000>; +- }; +- +- acc1: clock-controller@2098000 { +- compatible = "qcom,kpss-acc-v1"; +- reg = <0x02098000 0x1000>, <0x02008000 0x1000>; +- }; +- +- saw0: regulator@2089000 { +- compatible = "qcom,saw2"; +- reg = <0x02089000 0x1000>, <0x02009000 0x1000>; +- regulator; +- }; +- +- saw1: regulator@2099000 { +- compatible = "qcom,saw2"; +- reg = <0x02099000 0x1000>, <0x02009000 0x1000>; +- regulator; +- }; +- +- gsbi5: gsbi@16400000 { +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <5>; +- reg = <0x16400000 0x100>; +- clocks = <&gcc GSBI5_H_CLK>; +- clock-names = "iface"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- syscon-tcsr = <&tcsr>; +- +- gsbi5_serial: serial@16440000 { +- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; +- reg = <0x16440000 0x1000>, +- <0x16400000 0x1000>; +- interrupts = <0 154 0x0>; +- clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- }; +- +- qcom,ssbi@500000 { +- compatible = "qcom,ssbi"; +- reg = <0x500000 0x1000>; +- qcom,controller-type = "pmic-arbiter"; +- +- pmicintc: pmic@0 { +- compatible = "qcom,pm8921"; +- interrupt-parent = <&msmgpio>; +- interrupts = <104 8>; +- #interrupt-cells = <2>; +- interrupt-controller; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pwrkey@1c { +- compatible = "qcom,pm8921-pwrkey"; +- reg = <0x1c>; +- interrupt-parent = <&pmicintc>; +- interrupts = <50 1>, <51 1>; +- debounce = <15625>; +- pull-up; +- }; +- +- keypad@148 { +- compatible = "qcom,pm8921-keypad"; +- reg = <0x148>; +- interrupt-parent = <&pmicintc>; +- interrupts = <74 1>, <75 1>; +- debounce = <15>; +- scan-delay = <32>; +- row-hold = <91500>; +- }; +- +- rtc@11d { +- compatible = "qcom,pm8921-rtc"; +- interrupt-parent = <&pmicintc>; +- interrupts = <39 1>; +- reg = <0x11d>; +- allow-set-time; +- }; +- }; +- }; +- +- rng@1a500000 { +- compatible = "qcom,prng"; +- reg = <0x1a500000 0x200>; +- clocks = <&gcc PRNG_CLK>; +- clock-names = "core"; +- }; +- +- /* Temporary fixed regulator */ +- vsdcc_fixed: vsdcc-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "SDCC Power"; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- regulator-always-on; +- }; +- +- amba { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- sdcc1: sdcc@12400000 { +- status = "disabled"; +- compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00051180>; +- reg = <0x12400000 0x8000>; +- interrupts = ; +- interrupt-names = "cmd_irq"; +- clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; +- clock-names = "mclk", "apb_pclk"; +- bus-width = <8>; +- max-frequency = <96000000>; +- non-removable; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- vmmc-supply = <&vsdcc_fixed>; +- }; +- +- sdcc3: sdcc@12180000 { +- compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00051180>; +- status = "disabled"; +- reg = <0x12180000 0x8000>; +- interrupts = ; +- interrupt-names = "cmd_irq"; +- clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; +- clock-names = "mclk", "apb_pclk"; +- bus-width = <4>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <192000000>; +- no-1-8-v; +- vmmc-supply = <&vsdcc_fixed>; +- }; +- }; +- +- tcsr: syscon@1a400000 { +- compatible = "qcom,tcsr-msm8960", "syscon"; +- reg = <0x1a400000 0x100>; +- }; +- +- gsbi@16000000 { +- compatible = "qcom,gsbi-v1.0.0"; +- cell-index = <1>; +- reg = <0x16000000 0x100>; +- clocks = <&gcc GSBI1_H_CLK>; +- clock-names = "iface"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- spi@16080000 { +- compatible = "qcom,spi-qup-v1.1.1"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x16080000 0x1000>; +- interrupts = <0 147 0>; +- spi-max-frequency = <24000000>; +- cs-gpios = <&msmgpio 8 0>; +- +- clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-msm8974-fairphone-fp2.dts b/scripts/dtc/include-prefixes/arm/qcom-msm8974-fairphone-fp2.dts +deleted file mode 100644 +index ea15b645b229..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-msm8974-fairphone-fp2.dts ++++ /dev/null +@@ -1,410 +0,0 @@ +-#include "qcom-msm8974.dtsi" +-#include "qcom-pm8841.dtsi" +-#include "qcom-pm8941.dtsi" +-#include +-#include +-#include +- +- +-/ { +- model = "Fairphone 2"; +- compatible = "fairphone,fp2", "qcom,msm8974"; +- +- aliases { +- serial0 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- input-name = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_pin_a>; +- +- camera-snapshot { +- label = "camera_snapshot"; +- gpios = <&pm8941_gpios 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- debounce-interval = <15>; +- }; +- +- volume-down { +- label = "volume_down"; +- gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- debounce-interval = <15>; +- }; +- +- volume-up { +- label = "volume_up"; +- gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- debounce-interval = <15>; +- }; +- }; +- +- vibrator { +- compatible = "gpio-vibrator"; +- enable-gpios = <&msmgpio 86 GPIO_ACTIVE_HIGH>; +- vcc-supply = <&pm8941_l18>; +- }; +- +- smd { +- rpm { +- rpm_requests { +- pm8841-regulators { +- s1 { +- regulator-min-microvolt = <675000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- s2 { +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- s3 { +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- }; +- +- pm8941-regulators { +- vdd_l1_l3-supply = <&pm8941_s1>; +- vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; +- vdd_l4_l11-supply = <&pm8941_s1>; +- vdd_l5_l7-supply = <&pm8941_s2>; +- vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; +- vdd_l9_l10_l17_l22-supply = <&vreg_boost>; +- vdd_l13_l20_l23_l24-supply = <&vreg_boost>; +- vdd_l21-supply = <&vreg_boost>; +- +- s1 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- +- regulator-always-on; +- regulator-boot-on; +- }; +- +- s2 { +- regulator-min-microvolt = <2150000>; +- regulator-max-microvolt = <2150000>; +- +- regulator-boot-on; +- }; +- +- s3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-always-on; +- regulator-boot-on; +- }; +- +- l1 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- +- regulator-always-on; +- regulator-boot-on; +- }; +- +- l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- l3 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- l4 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- l5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-boot-on; +- }; +- +- l7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-boot-on; +- }; +- +- l8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l9 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- l10 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- l11 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1350000>; +- }; +- +- l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-always-on; +- regulator-boot-on; +- }; +- +- l13 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-boot-on; +- }; +- +- l14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l15 { +- regulator-min-microvolt = <2050000>; +- regulator-max-microvolt = <2050000>; +- }; +- +- l16 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- l17 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- l18 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- l19 { +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <3350000>; +- }; +- +- l20 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-boot-on; +- regulator-system-load = <200000>; +- regulator-allow-set-load; +- }; +- +- l21 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-boot-on; +- }; +- +- l22 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l23 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- l24 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- +- regulator-boot-on; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&soc { +- serial@f991e000 { +- status = "okay"; +- }; +- +- remoteproc@fb21b000 { +- status = "okay"; +- +- vddmx-supply = <&pm8841_s1>; +- vddcx-supply = <&pm8841_s2>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&wcnss_pin_a>; +- +- smd-edge { +- qcom,remote-pid = <4>; +- label = "pronto"; +- +- wcnss { +- status = "okay"; +- }; +- }; +- }; +- +- pinctrl@fd510000 { +- sdhc1_pin_a: sdhc1-pin-active { +- clk { +- pins = "sdc1_clk"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- cmd-data { +- pins = "sdc1_cmd", "sdc1_data"; +- drive-strength = <10>; +- bias-pull-up; +- }; +- }; +- +- sdhc2_pin_a: sdhc2-pin-active { +- clk { +- pins = "sdc2_clk"; +- drive-strength = <10>; +- bias-disable; +- }; +- +- cmd-data { +- pins = "sdc2_cmd", "sdc2_data"; +- drive-strength = <6>; +- bias-pull-up; +- }; +- }; +- +- wcnss_pin_a: wcnss-pin-active { +- wlan { +- pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; +- function = "wlan"; +- +- drive-strength = <6>; +- bias-pull-down; +- }; +- +- bt { +- pins = "gpio35", "gpio43", "gpio44"; +- function = "bt"; +- +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- fm { +- pins = "gpio41", "gpio42"; +- function = "fm"; +- +- drive-strength = <2>; +- bias-pull-down; +- }; +- }; +- }; +- +- sdhci@f9824900 { +- status = "okay"; +- +- vmmc-supply = <&pm8941_l20>; +- vqmmc-supply = <&pm8941_s3>; +- +- bus-width = <8>; +- non-removable; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhc1_pin_a>; +- }; +- +- sdhci@f98a4900 { +- status = "okay"; +- +- vmmc-supply = <&pm8941_l21>; +- vqmmc-supply = <&pm8941_l13>; +- +- bus-width = <4>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhc2_pin_a>; +- }; +- +- usb@f9a55000 { +- status = "okay"; +- +- phys = <&usb_hs1_phy>; +- phy-select = <&tcsr 0xb000 0>; +- extcon = <&smbb>, <&usb_id>; +- vbus-supply = <&chg_otg>; +- +- hnp-disable; +- srp-disable; +- adp-disable; +- +- ulpi { +- phy@a { +- status = "okay"; +- +- v1p8-supply = <&pm8941_l6>; +- v3p3-supply = <&pm8941_l24>; +- +- extcon = <&smbb>; +- qcom,init-seq = /bits/ 8 <0x1 0x64>; +- }; +- }; +- }; +- +- imem@fe805000 { +- status = "okay"; +- +- reboot-mode { +- mode-normal = <0x77665501>; +- mode-bootloader = <0x77665500>; +- mode-recovery = <0x77665502>; +- }; +- }; +-}; +- +-&spmi_bus { +- pm8941@0 { +- gpios@c000 { +- gpio_keys_pin_a: gpio-keys-active { +- pins = "gpio1", "gpio2", "gpio5"; +- function = "normal"; +- +- bias-pull-up; +- power-source = ; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-msm8974-lge-nexus5-hammerhead.dts b/scripts/dtc/include-prefixes/arm/qcom-msm8974-lge-nexus5-hammerhead.dts +deleted file mode 100644 +index 30ee913faae6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-msm8974-lge-nexus5-hammerhead.dts ++++ /dev/null +@@ -1,762 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "qcom-msm8974.dtsi" +-#include "qcom-pm8841.dtsi" +-#include "qcom-pm8941.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "LGE MSM 8974 HAMMERHEAD"; +- compatible = "lge,hammerhead", "qcom,msm8974"; +- +- aliases { +- serial0 = &blsp1_uart1; +- serial1 = &blsp2_uart10; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- smd { +- rpm { +- rpm_requests { +- pm8841-regulators { +- s1 { +- regulator-min-microvolt = <675000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- s2 { +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- s3 { +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- s4 { +- regulator-min-microvolt = <815000>; +- regulator-max-microvolt = <900000>; +- }; +- }; +- +- pm8941-regulators { +- vdd_l1_l3-supply = <&pm8941_s1>; +- vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; +- vdd_l4_l11-supply = <&pm8941_s1>; +- vdd_l5_l7-supply = <&pm8941_s2>; +- vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; +- vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>; +- vdd_l9_l10_l17_l22-supply = <&vreg_boost>; +- vdd_l13_l20_l23_l24-supply = <&vreg_boost>; +- vdd_l21-supply = <&vreg_boost>; +- +- s1 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- +- regulator-always-on; +- regulator-boot-on; +- }; +- +- s2 { +- regulator-min-microvolt = <2150000>; +- regulator-max-microvolt = <2150000>; +- +- regulator-boot-on; +- }; +- +- s3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-always-on; +- regulator-boot-on; +- }; +- +- l1 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- +- regulator-always-on; +- regulator-boot-on; +- }; +- +- l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- l3 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- l4 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- l5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-boot-on; +- }; +- +- l7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-boot-on; +- }; +- +- l8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l9 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- l10 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- l11 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- }; +- +- l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-always-on; +- regulator-boot-on; +- }; +- +- l13 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-boot-on; +- }; +- +- l14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l15 { +- regulator-min-microvolt = <2050000>; +- regulator-max-microvolt = <2050000>; +- }; +- +- l16 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- l17 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- l18 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- l19 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l20 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-boot-on; +- regulator-system-load = <200000>; +- regulator-allow-set-load; +- }; +- +- l21 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-boot-on; +- }; +- +- l22 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l23 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- l24 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- +- regulator-boot-on; +- }; +- }; +- }; +- }; +- }; +- +- vreg_wlan: wlan-regulator { +- compatible = "regulator-fixed"; +- +- regulator-name = "wl-reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&msmgpio 26 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_regulator_pin>; +- }; +-}; +- +-&soc { +- serial@f991d000 { +- status = "okay"; +- }; +- +- pinctrl@fd510000 { +- sdhc1_pin_a: sdhc1-pin-active { +- clk { +- pins = "sdc1_clk"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- cmd-data { +- pins = "sdc1_cmd", "sdc1_data"; +- drive-strength = <10>; +- bias-pull-up; +- }; +- }; +- +- sdhc2_pin_a: sdhc2-pin-active { +- clk { +- pins = "sdc2_clk"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- cmd-data { +- pins = "sdc2_cmd", "sdc2_data"; +- drive-strength = <6>; +- bias-pull-up; +- }; +- }; +- +- i2c1_pins: i2c1 { +- mux { +- pins = "gpio2", "gpio3"; +- function = "blsp_i2c1"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- i2c2_pins: i2c2 { +- mux { +- pins = "gpio6", "gpio7"; +- function = "blsp_i2c2"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- i2c3_pins: i2c3 { +- mux { +- pins = "gpio10", "gpio11"; +- function = "blsp_i2c3"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- i2c11_pins: i2c11 { +- mux { +- pins = "gpio83", "gpio84"; +- function = "blsp_i2c11"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- i2c12_pins: i2c12 { +- mux { +- pins = "gpio87", "gpio88"; +- function = "blsp_i2c12"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- mpu6515_pin: mpu6515 { +- irq { +- pins = "gpio73"; +- function = "gpio"; +- bias-disable; +- input-enable; +- }; +- }; +- +- touch_pin: touch { +- int { +- pins = "gpio5"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- input-enable; +- }; +- +- reset { +- pins = "gpio8"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-up; +- }; +- }; +- +- panel_pin: panel { +- te { +- pins = "gpio12"; +- function = "mdp_vsync"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- bt_pin: bt { +- hostwake { +- pins = "gpio42"; +- function = "gpio"; +- }; +- +- devwake { +- pins = "gpio62"; +- function = "gpio"; +- }; +- +- shutdown { +- pins = "gpio41"; +- function = "gpio"; +- }; +- }; +- +- blsp2_uart10_pin_a: blsp2-uart10-pin-active { +- tx { +- pins = "gpio53"; +- function = "blsp_uart10"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- rx { +- pins = "gpio54"; +- function = "blsp_uart10"; +- +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- cts { +- pins = "gpio55"; +- function = "blsp_uart10"; +- +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- rts { +- pins = "gpio56"; +- function = "blsp_uart10"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- }; +- +- sdhci@f9824900 { +- status = "okay"; +- +- vmmc-supply = <&pm8941_l20>; +- vqmmc-supply = <&pm8941_s3>; +- +- bus-width = <8>; +- non-removable; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhc1_pin_a>; +- }; +- +- sdhci@f98a4900 { +- status = "okay"; +- +- max-frequency = <100000000>; +- bus-width = <4>; +- non-removable; +- vmmc-supply = <&vreg_wlan>; +- vqmmc-supply = <&pm8941_s3>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhc2_pin_a>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- bcrmf@1 { +- compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; +- reg = <1>; +- +- brcm,drive-strength = <10>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_sleep_clk_pin>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- input-name = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_pin_a>; +- +- volume-up { +- label = "volume_up"; +- gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- }; +- +- volume-down { +- label = "volume_down"; +- gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- }; +- }; +- +- serial@f9960000 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp2_uart10_pin_a>; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- max-speed = <3000000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_pin>; +- +- host-wakeup-gpios = <&msmgpio 42 GPIO_ACTIVE_HIGH>; +- device-wakeup-gpios = <&msmgpio 62 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&msmgpio 41 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- i2c@f9967000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c11_pins>; +- clock-frequency = <355000>; +- qcom,src-freq = <50000000>; +- +- led-controller@38 { +- compatible = "ti,lm3630a"; +- status = "okay"; +- reg = <0x38>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- led@0 { +- reg = <0>; +- led-sources = <0 1>; +- label = "lcd-backlight"; +- default-brightness = <200>; +- }; +- }; +- }; +- +- i2c@f9968000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c12_pins>; +- clock-frequency = <100000>; +- qcom,src-freq = <50000000>; +- +- mpu6515@68 { +- compatible = "invensense,mpu6515"; +- reg = <0x68>; +- interrupts-extended = <&msmgpio 73 IRQ_TYPE_EDGE_FALLING>; +- vddio-supply = <&pm8941_lvs1>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&mpu6515_pin>; +- +- mount-matrix = "0", "-1", "0", +- "-1", "0", "0", +- "0", "0", "1"; +- +- i2c-gate { +- #address-cells = <1>; +- #size-cells = <0>; +- ak8963@f { +- compatible = "asahi-kasei,ak8963"; +- reg = <0x0f>; +- gpios = <&msmgpio 67 0>; +- vid-supply = <&pm8941_lvs1>; +- vdd-supply = <&pm8941_l17>; +- }; +- +- bmp280@76 { +- compatible = "bosch,bmp280"; +- reg = <0x76>; +- vdda-supply = <&pm8941_lvs1>; +- vddd-supply = <&pm8941_l17>; +- }; +- }; +- }; +- }; +- +- i2c@f9923000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- clock-frequency = <100000>; +- qcom,src-freq = <50000000>; +- +- charger: bq24192@6b { +- compatible = "ti,bq24192"; +- reg = <0x6b>; +- interrupts-extended = <&spmi_bus 0 0xd5 0 IRQ_TYPE_EDGE_FALLING>; +- +- omit-battery-class; +- +- usb_otg_vbus: usb-otg-vbus { }; +- }; +- +- fuelgauge: max17048@36 { +- compatible = "maxim,max17048"; +- reg = <0x36>; +- +- maxim,double-soc; +- maxim,rcomp = /bits/ 8 <0x4d>; +- +- interrupt-parent = <&msmgpio>; +- interrupts = <9 IRQ_TYPE_LEVEL_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&fuelgauge_pin>; +- +- maxim,alert-low-soc-level = <2>; +- }; +- }; +- +- i2c@f9924000 { +- status = "okay"; +- +- clock-frequency = <355000>; +- qcom,src-freq = <50000000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- +- synaptics@70 { +- compatible = "syna,rmi4-i2c"; +- reg = <0x70>; +- +- interrupts-extended = <&msmgpio 5 IRQ_TYPE_EDGE_FALLING>; +- vdd-supply = <&pm8941_l22>; +- vio-supply = <&pm8941_lvs3>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&touch_pin>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- rmi4-f01@1 { +- reg = <0x1>; +- syna,nosleep-mode = <1>; +- }; +- +- rmi4-f12@12 { +- reg = <0x12>; +- syna,sensor-type = <1>; +- }; +- }; +- }; +- +- i2c@f9925000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- clock-frequency = <100000>; +- qcom,src-freq = <50000000>; +- +- avago_apds993@39 { +- compatible = "avago,apds9930"; +- reg = <0x39>; +- interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>; +- vdd-supply = <&pm8941_l17>; +- vddio-supply = <&pm8941_lvs1>; +- led-max-microamp = <100000>; +- amstaos,proximity-diodes = <0>; +- }; +- }; +- +- usb@f9a55000 { +- status = "okay"; +- +- phys = <&usb_hs1_phy>; +- phy-select = <&tcsr 0xb000 0>; +- +- extcon = <&charger>, <&usb_id>; +- vbus-supply = <&usb_otg_vbus>; +- +- hnp-disable; +- srp-disable; +- adp-disable; +- +- ulpi { +- phy@a { +- status = "okay"; +- +- v1p8-supply = <&pm8941_l6>; +- v3p3-supply = <&pm8941_l24>; +- +- qcom,init-seq = /bits/ 8 <0x1 0x64>; +- }; +- }; +- }; +- +- mdss@fd900000 { +- status = "okay"; +- +- mdp@fd900000 { +- status = "okay"; +- }; +- +- dsi@fd922800 { +- status = "okay"; +- +- vdda-supply = <&pm8941_l2>; +- vdd-supply = <&pm8941_lvs3>; +- vddio-supply = <&pm8941_l12>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports { +- port@1 { +- endpoint { +- remote-endpoint = <&panel_in>; +- data-lanes = <0 1 2 3>; +- }; +- }; +- }; +- +- panel: panel@0 { +- reg = <0>; +- compatible = "lg,acx467akm-7"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&panel_pin>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&dsi0_out>; +- }; +- }; +- }; +- }; +- +- dsi-phy@fd922a00 { +- status = "okay"; +- +- vddio-supply = <&pm8941_l12>; +- }; +- }; +-}; +- +-&spmi_bus { +- pm8941@0 { +- gpios@c000 { +- gpio_keys_pin_a: gpio-keys-active { +- pins = "gpio2", "gpio3"; +- function = "normal"; +- +- bias-pull-up; +- power-source = ; +- }; +- +- fuelgauge_pin: fuelgauge-int { +- pins = "gpio9"; +- function = "normal"; +- +- bias-disable; +- input-enable; +- power-source = ; +- }; +- +- wlan_sleep_clk_pin: wl-sleep-clk { +- pins = "gpio16"; +- function = "func2"; +- +- output-high; +- power-source = ; +- }; +- +- wlan_regulator_pin: wl-reg-active { +- pins = "gpio17"; +- function = "normal"; +- +- bias-disable; +- power-source = ; +- }; +- +- otg { +- gpio-hog; +- gpios = <35 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "otg-gpio"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-msm8974-samsung-klte.dts b/scripts/dtc/include-prefixes/arm/qcom-msm8974-samsung-klte.dts +deleted file mode 100644 +index 003f0fa9c857..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-msm8974-samsung-klte.dts ++++ /dev/null +@@ -1,909 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "qcom-msm8974pro.dtsi" +-#include "qcom-pma8084.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "Samsung Galaxy S5"; +- compatible = "samsung,klte", "qcom,msm8974"; +- +- aliases { +- serial0 = &blsp1_uart1; +- mmc0 = &sdhc_1; /* SDC1 eMMC slot */ +- mmc1 = &sdhc_2; /* SDC2 SD card slot */ +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- smd { +- rpm { +- rpm_requests { +- pma8084-regulators { +- compatible = "qcom,rpm-pma8084-regulators"; +- status = "okay"; +- +- pma8084_s1: s1 { +- regulator-min-microvolt = <675000>; +- regulator-max-microvolt = <1050000>; +- regulator-always-on; +- }; +- +- pma8084_s2: s2 { +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- pma8084_s3: s3 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- }; +- +- pma8084_s4: s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pma8084_s5: s5 { +- regulator-min-microvolt = <2150000>; +- regulator-max-microvolt = <2150000>; +- }; +- +- pma8084_s6: s6 { +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- pma8084_l1: l1 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- pma8084_l2: l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- pma8084_l3: l3 { +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- pma8084_l4: l4 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- pma8084_l5: l5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pma8084_l6: l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pma8084_l7: l7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pma8084_l8: l8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pma8084_l9: l9 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- pma8084_l10: l10 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- pma8084_l11: l11 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- }; +- +- pma8084_l12: l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- pma8084_l13: l13 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- pma8084_l14: l14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pma8084_l15: l15 { +- regulator-min-microvolt = <2050000>; +- regulator-max-microvolt = <2050000>; +- }; +- +- pma8084_l16: l16 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- pma8084_l17: l17 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- pma8084_l18: l18 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- pma8084_l19: l19 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- pma8084_l20: l20 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-allow-set-load; +- regulator-system-load = <200000>; +- }; +- +- pma8084_l21: l21 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-allow-set-load; +- regulator-system-load = <200000>; +- }; +- +- pma8084_l22: l22 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- pma8084_l23: l23 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- pma8084_l24: l24 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- }; +- +- pma8084_l25: l25 { +- regulator-min-microvolt = <2100000>; +- regulator-max-microvolt = <2100000>; +- }; +- +- pma8084_l26: l26 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2050000>; +- }; +- +- pma8084_l27: l27 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- pma8084_lvs1: lvs1 {}; +- pma8084_lvs2: lvs2 {}; +- pma8084_lvs3: lvs3 {}; +- pma8084_lvs4: lvs4 {}; +- +- pma8084_5vs1: 5vs1 {}; +- }; +- }; +- }; +- }; +- +- i2c-gpio-touchkey { +- compatible = "i2c-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- sda-gpios = <&msmgpio 95 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&msmgpio 96 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_touchkey_pins>; +- +- touchkey@20 { +- compatible = "cypress,tm2-touchkey"; +- reg = <0x20>; +- +- interrupt-parent = <&pma8084_gpios>; +- interrupts = <6 IRQ_TYPE_EDGE_FALLING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&touchkey_pin>; +- +- vcc-supply = <&max77826_ldo15>; +- vdd-supply = <&pma8084_l19>; +- +- linux,keycodes = ; +- }; +- }; +- +- i2c-gpio-led { +- compatible = "i2c-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- scl-gpios = <&msmgpio 121 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&msmgpio 120 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_led_gpioex_pins>; +- +- i2c-gpio,delay-us = <2>; +- +- gpio_expander: gpio@20 { +- compatible = "nxp,pcal6416"; +- reg = <0x20>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- vcc-supply = <&pma8084_s4>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gpioex_pin>; +- +- reset-gpios = <&msmgpio 145 GPIO_ACTIVE_LOW>; +- }; +- +- led-controller@30 { +- compatible = "panasonic,an30259a"; +- reg = <0x30>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- led@1 { +- reg = <1>; +- function = LED_FUNCTION_STATUS; +- color = ; +- }; +- +- led@2 { +- reg = <2>; +- function = LED_FUNCTION_STATUS; +- color = ; +- }; +- +- led@3 { +- reg = <3>; +- function = LED_FUNCTION_STATUS; +- color = ; +- }; +- }; +- }; +- +- vreg_wlan: wlan-regulator { +- compatible = "regulator-fixed"; +- +- regulator-name = "wl-reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio_expander 8 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vreg_panel: panel-regulator { +- compatible = "regulator-fixed"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&panel_en_pin>; +- +- regulator-name = "panel-vddr-reg"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- +- gpio = <&pma8084_gpios 14 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- /delete-node/ vreg-boost; +- +- adsp-pil { +- cx-supply = <&pma8084_s2>; +- }; +-}; +- +-&soc { +- serial@f991e000 { +- status = "okay"; +- }; +- +- /* blsp2_uart8 */ +- serial@f995e000 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp2_uart8_pins_active>; +- pinctrl-1 = <&blsp2_uart8_pins_sleep>; +- +- bluetooth { +- compatible = "brcm,bcm43540-bt"; +- max-speed = <3000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_pins>; +- device-wakeup-gpios = <&msmgpio 91 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpio_expander 9 GPIO_ACTIVE_HIGH>; +- interrupt-parent = <&msmgpio>; +- interrupts = <75 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "host-wakeup"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- input-name = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_pin_a>; +- +- volume-down { +- label = "volume_down"; +- gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- debounce-interval = <15>; +- }; +- +- home-key { +- label = "home_key"; +- gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- wakeup-source; +- debounce-interval = <15>; +- }; +- +- volume-up { +- label = "volume_up"; +- gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- debounce-interval = <15>; +- }; +- }; +- +- pinctrl@fd510000 { +- blsp2_uart8_pins_active: blsp2-uart8-pins-active { +- pins = "gpio45", "gpio46", "gpio47", "gpio48"; +- function = "blsp_uart8"; +- drive-strength = <8>; +- bias-disable; +- }; +- +- blsp2_uart8_pins_sleep: blsp2-uart8-pins-sleep { +- pins = "gpio45", "gpio46", "gpio47", "gpio48"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- bt_pins: bt-pins { +- hostwake { +- pins = "gpio75"; +- function = "gpio"; +- drive-strength = <16>; +- input-enable; +- }; +- +- devwake { +- pins = "gpio91"; +- function = "gpio"; +- drive-strength = <2>; +- }; +- }; +- +- sdhc1_pin_a: sdhc1-pin-active { +- clk { +- pins = "sdc1_clk"; +- drive-strength = <4>; +- bias-disable; +- }; +- +- cmd-data { +- pins = "sdc1_cmd", "sdc1_data"; +- drive-strength = <4>; +- bias-pull-up; +- }; +- }; +- +- sdhc2_pin_a: sdhc2-pin-active { +- clk-cmd-data { +- pins = "gpio35", "gpio36", "gpio37", "gpio38", +- "gpio39", "gpio40"; +- function = "sdc3"; +- drive-strength = <8>; +- bias-disable; +- }; +- }; +- +- sdhc2_cd_pin: sdhc2-cd { +- pins = "gpio62"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- sdhc3_pin_a: sdhc3-pin-active { +- clk { +- pins = "sdc2_clk"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- cmd-data { +- pins = "sdc2_cmd", "sdc2_data"; +- drive-strength = <6>; +- bias-pull-up; +- }; +- }; +- +- i2c2_pins: i2c2 { +- mux { +- pins = "gpio6", "gpio7"; +- function = "blsp_i2c2"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- i2c6_pins: i2c6 { +- mux { +- pins = "gpio29", "gpio30"; +- function = "blsp_i2c6"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- i2c12_pins: i2c12 { +- mux { +- pins = "gpio87", "gpio88"; +- function = "blsp_i2c12"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- i2c_touchkey_pins: i2c-touchkey { +- mux { +- pins = "gpio95", "gpio96"; +- function = "gpio"; +- input-enable; +- bias-pull-up; +- }; +- }; +- +- i2c_led_gpioex_pins: i2c-led-gpioex { +- mux { +- pins = "gpio120", "gpio121"; +- function = "gpio"; +- input-enable; +- bias-pull-down; +- }; +- }; +- +- gpioex_pin: gpioex { +- res { +- pins = "gpio145"; +- function = "gpio"; +- +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +- +- wifi_pin: wifi { +- int { +- pins = "gpio92"; +- function = "gpio"; +- +- input-enable; +- bias-pull-down; +- }; +- }; +- +- panel_te_pin: panel { +- te { +- pins = "gpio12"; +- function = "mdp_vsync"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- }; +- +- sdhc_1: sdhci@f9824900 { +- status = "okay"; +- +- vmmc-supply = <&pma8084_l20>; +- vqmmc-supply = <&pma8084_s4>; +- +- bus-width = <8>; +- non-removable; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhc1_pin_a>; +- }; +- +- sdhc_2: sdhci@f9864900 { +- status = "okay"; +- +- max-frequency = <100000000>; +- +- vmmc-supply = <&pma8084_l21>; +- vqmmc-supply = <&pma8084_l13>; +- +- bus-width = <4>; +- +- /* cd-gpio is intentionally disabled. If enabled, an SD card +- * present during boot is not initialized correctly. Without +- * cd-gpios the driver resorts to polling, so hotplug works. +- */ +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhc2_pin_a /* &sdhc2_cd_pin */>; +- // cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; +- }; +- +- sdhci@f98a4900 { +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- max-frequency = <100000000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhc3_pin_a>; +- +- vmmc-supply = <&vreg_wlan>; +- vqmmc-supply = <&pma8084_s4>; +- +- bus-width = <4>; +- non-removable; +- +- wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- +- interrupt-parent = <&msmgpio>; +- interrupts = <92 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "host-wake"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_sleep_clk_pin &wifi_pin>; +- }; +- }; +- +- usb@f9a55000 { +- status = "okay"; +- +- phys = <&usb_hs1_phy>; +- phy-select = <&tcsr 0xb000 0>; +- /*extcon = <&smbb>, <&usb_id>;*/ +- /*vbus-supply = <&chg_otg>;*/ +- +- hnp-disable; +- srp-disable; +- adp-disable; +- +- ulpi { +- phy@a { +- status = "okay"; +- +- v1p8-supply = <&pma8084_l6>; +- v3p3-supply = <&pma8084_l24>; +- +- /*extcon = <&smbb>;*/ +- qcom,init-seq = /bits/ 8 <0x1 0x64>; +- }; +- }; +- }; +- +- i2c@f9924000 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- +- touchscreen@20 { +- compatible = "syna,rmi4-i2c"; +- reg = <0x20>; +- +- interrupt-parent = <&pma8084_gpios>; +- interrupts = <8 IRQ_TYPE_EDGE_FALLING>; +- +- vdd-supply = <&max77826_ldo13>; +- vio-supply = <&pma8084_lvs2>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&touch_pin>; +- +- syna,startup-delay-ms = <100>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- rmi4-f01@1 { +- reg = <0x1>; +- syna,nosleep-mode = <1>; +- }; +- +- rmi4-f12@12 { +- reg = <0x12>; +- syna,sensor-type = <1>; +- }; +- }; +- }; +- +- i2c@f9928000 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c6_pins>; +- +- pmic@60 { +- reg = <0x60>; +- compatible = "maxim,max77826"; +- +- regulators { +- max77826_ldo1: LDO1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- max77826_ldo2: LDO2 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- max77826_ldo3: LDO3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- max77826_ldo4: LDO4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- max77826_ldo5: LDO5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- max77826_ldo6: LDO6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- max77826_ldo7: LDO7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- max77826_ldo8: LDO8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- max77826_ldo9: LDO9 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- max77826_ldo10: LDO10 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- max77826_ldo11: LDO11 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- max77826_ldo12: LDO12 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- max77826_ldo13: LDO13 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- max77826_ldo14: LDO14 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- max77826_ldo15: LDO15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- max77826_buck: BUCK { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- max77826_buckboost: BUCKBOOST { +- regulator-min-microvolt = <3400000>; +- regulator-max-microvolt = <3400000>; +- }; +- }; +- }; +- }; +- +- i2c@f9968000 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c12_pins>; +- +- fuelgauge@36 { +- compatible = "maxim,max17048"; +- reg = <0x36>; +- +- maxim,double-soc; +- maxim,rcomp = /bits/ 8 <0x56>; +- +- interrupt-parent = <&pma8084_gpios>; +- interrupts = <21 IRQ_TYPE_LEVEL_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&fuelgauge_pin>; +- }; +- }; +- +- adreno@fdb00000 { +- status = "ok"; +- }; +- +- mdss@fd900000 { +- status = "ok"; +- +- mdp@fd900000 { +- status = "ok"; +- }; +- +- dsi@fd922800 { +- status = "ok"; +- +- vdda-supply = <&pma8084_l2>; +- vdd-supply = <&pma8084_l22>; +- vddio-supply = <&pma8084_l12>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports { +- port@1 { +- endpoint { +- remote-endpoint = <&panel_in>; +- data-lanes = <0 1 2 3>; +- }; +- }; +- }; +- +- panel: panel@0 { +- reg = <0>; +- compatible = "samsung,s6e3fa2"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&panel_te_pin &panel_rst_pin>; +- +- iovdd-supply = <&pma8084_lvs4>; +- vddr-supply = <&vreg_panel>; +- +- reset-gpios = <&pma8084_gpios 17 GPIO_ACTIVE_LOW>; +- te-gpios = <&msmgpio 12 GPIO_ACTIVE_HIGH>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&dsi0_out>; +- }; +- }; +- }; +- }; +- +- dsi-phy@fd922a00 { +- status = "ok"; +- +- vddio-supply = <&pma8084_l12>; +- }; +- }; +- +- remoteproc@fc880000 { +- cx-supply = <&pma8084_s2>; +- mss-supply = <&pma8084_s6>; +- mx-supply = <&pma8084_s1>; +- pll-supply = <&pma8084_l12>; +- }; +-}; +- +-&spmi_bus { +- pma8084@0 { +- gpios@c000 { +- gpio_keys_pin_a: gpio-keys-active { +- pins = "gpio2", "gpio3", "gpio5"; +- function = "normal"; +- +- bias-pull-up; +- power-source = ; +- }; +- +- touchkey_pin: touchkey-int-pin { +- pins = "gpio6"; +- function = "normal"; +- bias-disable; +- input-enable; +- power-source = ; +- }; +- +- touch_pin: touchscreen-int-pin { +- pins = "gpio8"; +- function = "normal"; +- bias-disable; +- input-enable; +- power-source = ; +- }; +- +- panel_en_pin: panel-en-pin { +- pins = "gpio14"; +- function = "normal"; +- bias-pull-up; +- power-source = ; +- qcom,drive-strength = ; +- }; +- +- wlan_sleep_clk_pin: wlan-sleep-clk-pin { +- pins = "gpio16"; +- function = "func2"; +- +- output-high; +- power-source = ; +- qcom,drive-strength = ; +- }; +- +- panel_rst_pin: panel-rst-pin { +- pins = "gpio17"; +- function = "normal"; +- bias-disable; +- power-source = ; +- qcom,drive-strength = ; +- }; +- +- +- fuelgauge_pin: fuelgauge-int-pin { +- pins = "gpio21"; +- function = "normal"; +- bias-disable; +- input-enable; +- power-source = ; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-msm8974-sony-xperia-amami.dts b/scripts/dtc/include-prefixes/arm/qcom-msm8974-sony-xperia-amami.dts +deleted file mode 100644 +index 398a3eaf306b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-msm8974-sony-xperia-amami.dts ++++ /dev/null +@@ -1,436 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "qcom-msm8974.dtsi" +-#include "qcom-pm8841.dtsi" +-#include "qcom-pm8941.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "Sony Xperia Z1 Compact"; +- compatible = "sony,xperia-amami", "qcom,msm8974"; +- +- aliases { +- serial0 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- input-name = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_pin_a>; +- +- volume-down { +- label = "volume_down"; +- gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- }; +- +- camera-snapshot { +- label = "camera_snapshot"; +- gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- }; +- +- camera-focus { +- label = "camera_focus"; +- gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- }; +- +- volume-up { +- label = "volume_up"; +- gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- }; +- }; +- +- memory@0 { +- reg = <0 0x40000000>, <0x40000000 0x40000000>; +- device_type = "memory"; +- }; +- +- smd { +- rpm { +- rpm_requests { +- pm8841-regulators { +- s1 { +- regulator-min-microvolt = <675000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- s2 { +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- s3 { +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- s4 { +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1050000>; +- }; +- }; +- +- pm8941-regulators { +- vdd_l1_l3-supply = <&pm8941_s1>; +- vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; +- vdd_l4_l11-supply = <&pm8941_s1>; +- vdd_l5_l7-supply = <&pm8941_s2>; +- vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; +- vdd_l9_l10_l17_l22-supply = <&vreg_boost>; +- vdd_l13_l20_l23_l24-supply = <&vreg_boost>; +- vdd_l21-supply = <&vreg_boost>; +- +- s1 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- s2 { +- regulator-min-microvolt = <2150000>; +- regulator-max-microvolt = <2150000>; +- regulator-boot-on; +- }; +- +- s3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- s4 { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- l1 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- +- regulator-always-on; +- regulator-boot-on; +- }; +- +- l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- l3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- l4 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- l5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-boot-on; +- }; +- +- l7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-boot-on; +- }; +- +- l8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l9 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- l11 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1350000>; +- }; +- +- l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-always-on; +- regulator-boot-on; +- }; +- +- l13 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-boot-on; +- }; +- +- l14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l15 { +- regulator-min-microvolt = <2050000>; +- regulator-max-microvolt = <2050000>; +- }; +- +- l16 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- l17 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- l18 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- l19 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l20 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-allow-set-load; +- regulator-boot-on; +- regulator-system-load = <200000>; +- }; +- +- l21 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-boot-on; +- }; +- +- l22 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- l23 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- l24 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- +- regulator-boot-on; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&soc { +- sdhci@f9824900 { +- status = "okay"; +- +- vmmc-supply = <&pm8941_l20>; +- vqmmc-supply = <&pm8941_s3>; +- +- bus-width = <8>; +- non-removable; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhc1_pin_a>; +- }; +- +- sdhci@f98a4900 { +- status = "okay"; +- +- bus-width = <4>; +- +- vmmc-supply = <&pm8941_l21>; +- vqmmc-supply = <&pm8941_l13>; +- +- cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; +- }; +- +- serial@f991e000 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp1_uart2_pin_a>; +- }; +- +- +- pinctrl@fd510000 { +- blsp1_uart2_pin_a: blsp1-uart2-pin-active { +- rx { +- pins = "gpio5"; +- function = "blsp_uart2"; +- +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- tx { +- pins = "gpio4"; +- function = "blsp_uart2"; +- +- drive-strength = <4>; +- bias-disable; +- }; +- }; +- +- i2c2_pins: i2c2 { +- mux { +- pins = "gpio6", "gpio7"; +- function = "blsp_i2c2"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- sdhc1_pin_a: sdhc1-pin-active { +- clk { +- pins = "sdc1_clk"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- cmd-data { +- pins = "sdc1_cmd", "sdc1_data"; +- drive-strength = <10>; +- bias-pull-up; +- }; +- }; +- +- sdhc2_cd_pin_a: sdhc2-cd-pin-active { +- pins = "gpio62"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- sdhc2_pin_a: sdhc2-pin-active { +- clk { +- pins = "sdc2_clk"; +- drive-strength = <10>; +- bias-disable; +- }; +- +- cmd-data { +- pins = "sdc2_cmd", "sdc2_data"; +- drive-strength = <6>; +- bias-pull-up; +- }; +- }; +- }; +- +- dma-controller@f9944000 { +- qcom,controlled-remotely; +- }; +- +- usb@f9a55000 { +- status = "okay"; +- +- phys = <&usb_hs1_phy>; +- phy-select = <&tcsr 0xb000 0>; +- extcon = <&smbb>, <&usb_id>; +- vbus-supply = <&chg_otg>; +- +- hnp-disable; +- srp-disable; +- adp-disable; +- +- ulpi { +- phy@a { +- status = "okay"; +- +- v1p8-supply = <&pm8941_l6>; +- v3p3-supply = <&pm8941_l24>; +- +- extcon = <&smbb>; +- qcom,init-seq = /bits/ 8 <0x1 0x64>; +- }; +- }; +- }; +-}; +- +-&spmi_bus { +- pm8941@0 { +- charger@1000 { +- qcom,fast-charge-safe-current = <1300000>; +- qcom,fast-charge-current-limit = <1300000>; +- qcom,dc-current-limit = <1300000>; +- qcom,fast-charge-safe-voltage = <4400000>; +- qcom,fast-charge-high-threshold-voltage = <4350000>; +- qcom,fast-charge-low-threshold-voltage = <3400000>; +- qcom,auto-recharge-threshold-voltage = <4200000>; +- qcom,minimum-input-voltage = <4300000>; +- }; +- +- gpios@c000 { +- gpio_keys_pin_a: gpio-keys-active { +- pins = "gpio2", "gpio3", "gpio4", "gpio5"; +- function = "normal"; +- +- bias-pull-up; +- power-source = ; +- }; +- }; +- +- coincell@2800 { +- status = "okay"; +- qcom,rset-ohms = <2100>; +- qcom,vset-millivolts = <3000>; +- }; +- }; +- +- pm8941@1 { +- wled@d800 { +- status = "okay"; +- +- qcom,cs-out; +- qcom,current-limit = <20>; +- qcom,current-boost-limit = <805>; +- qcom,switching-freq = <1600>; +- qcom,ovp = <29>; +- qcom,num-strings = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-msm8974-sony-xperia-castor.dts b/scripts/dtc/include-prefixes/arm/qcom-msm8974-sony-xperia-castor.dts +deleted file mode 100644 +index b4dd85bd4faf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-msm8974-sony-xperia-castor.dts ++++ /dev/null +@@ -1,724 +0,0 @@ +-#include "qcom-msm8974pro.dtsi" +-#include "qcom-pm8841.dtsi" +-#include "qcom-pm8941.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "Sony Xperia Z2 Tablet"; +- compatible = "sony,xperia-castor", "qcom,msm8974"; +- +- aliases { +- serial0 = &blsp1_uart2; +- serial1 = &blsp2_uart7; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- input-name = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_pin_a>; +- +- volume-down { +- label = "volume_down"; +- gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- }; +- +- camera-snapshot { +- label = "camera_snapshot"; +- gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- }; +- +- camera-focus { +- label = "camera_focus"; +- gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- }; +- +- volume-up { +- label = "volume_up"; +- gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- }; +- }; +- +- smd { +- rpm { +- rpm_requests { +- pm8941-regulators { +- vdd_l1_l3-supply = <&pm8941_s1>; +- vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; +- vdd_l4_l11-supply = <&pm8941_s1>; +- vdd_l5_l7-supply = <&pm8941_s2>; +- vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; +- vdd_l9_l10_l17_l22-supply = <&vreg_boost>; +- vdd_l13_l20_l23_l24-supply = <&vreg_boost>; +- vdd_l21-supply = <&vreg_boost>; +- +- s1 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- s2 { +- regulator-min-microvolt = <2150000>; +- regulator-max-microvolt = <2150000>; +- regulator-boot-on; +- }; +- +- s3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-system-load = <154000>; +- }; +- +- s4 { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- l1 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- +- regulator-always-on; +- regulator-boot-on; +- }; +- +- l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- l3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- l4 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- l5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-boot-on; +- }; +- +- l7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-boot-on; +- }; +- +- l8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l9 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- l11 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1350000>; +- }; +- +- l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-always-on; +- regulator-boot-on; +- }; +- +- l13 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-boot-on; +- }; +- +- l14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l15 { +- regulator-min-microvolt = <2050000>; +- regulator-max-microvolt = <2050000>; +- }; +- +- l16 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- l17 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- l18 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- l19 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- l20 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-allow-set-load; +- regulator-boot-on; +- regulator-allow-set-load; +- regulator-system-load = <500000>; +- }; +- +- l21 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-boot-on; +- }; +- +- l22 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- l23 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- l24 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- +- regulator-boot-on; +- }; +- }; +- }; +- }; +- }; +- +- vreg_bl_vddio: lcd-backlight-vddio { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_bl_vddio"; +- regulator-min-microvolt = <3150000>; +- regulator-max-microvolt = <3150000>; +- +- gpio = <&msmgpio 69 0>; +- enable-active-high; +- +- vin-supply = <&pm8941_s3>; +- startup-delay-us = <70000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_backlight_en_pin_a>; +- }; +- +- vreg_vsp: lcd-dcdc-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_vsp"; +- regulator-min-microvolt = <5600000>; +- regulator-max-microvolt = <5600000>; +- +- gpio = <&pm8941_gpios 20 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_dcdc_en_pin_a>; +- }; +- +- vreg_wlan: wlan-regulator { +- compatible = "regulator-fixed"; +- +- regulator-name = "wl-reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&pm8941_gpios 18 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_regulator_pin>; +- }; +-}; +- +-&soc { +- sdhci@f9824900 { +- status = "okay"; +- +- vmmc-supply = <&pm8941_l20>; +- vqmmc-supply = <&pm8941_s3>; +- +- bus-width = <8>; +- non-removable; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhc1_pin_a>; +- }; +- +- sdhci@f9864900 { +- status = "okay"; +- +- max-frequency = <100000000>; +- non-removable; +- vmmc-supply = <&vreg_wlan>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhc3_pin_a>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- bcrmf@1 { +- compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; +- reg = <1>; +- +- brcm,drive-strength = <10>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_sleep_clk_pin>; +- }; +- }; +- +- sdhci@f98a4900 { +- status = "okay"; +- +- bus-width = <4>; +- +- vmmc-supply = <&pm8941_l21>; +- vqmmc-supply = <&pm8941_l13>; +- +- cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; +- }; +- +- serial@f991e000 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp1_uart2_pin_a>; +- }; +- +- serial@f995d000 { +- status = "ok"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp2_uart7_pin_a>; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- max-speed = <3000000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_host_wake_pin>, +- <&bt_dev_wake_pin>, +- <&bt_reg_on_pin>; +- +- host-wakeup-gpios = <&msmgpio 95 GPIO_ACTIVE_HIGH>; +- device-wakeup-gpios = <&msmgpio 96 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&pm8941_gpios 16 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- usb@f9a55000 { +- status = "okay"; +- +- phys = <&usb_hs1_phy>; +- phy-select = <&tcsr 0xb000 0>; +- extcon = <&smbb>, <&usb_id>; +- vbus-supply = <&chg_otg>; +- +- hnp-disable; +- srp-disable; +- adp-disable; +- +- ulpi { +- phy@a { +- status = "okay"; +- +- v1p8-supply = <&pm8941_l6>; +- v3p3-supply = <&pm8941_l24>; +- +- extcon = <&smbb>; +- qcom,init-seq = /bits/ 8 <0x1 0x64>; +- }; +- }; +- }; +- +- pinctrl@fd510000 { +- blsp1_uart2_pin_a: blsp1-uart2-pin-active { +- rx { +- pins = "gpio5"; +- function = "blsp_uart2"; +- +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- tx { +- pins = "gpio4"; +- function = "blsp_uart2"; +- +- drive-strength = <4>; +- bias-disable; +- }; +- }; +- +- blsp2_uart7_pin_a: blsp2-uart7-pin-active { +- tx { +- pins = "gpio41"; +- function = "blsp_uart7"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- rx { +- pins = "gpio42"; +- function = "blsp_uart7"; +- +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- cts { +- pins = "gpio43"; +- function = "blsp_uart7"; +- +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- rts { +- pins = "gpio44"; +- function = "blsp_uart7"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- i2c8_pins: i2c8 { +- mux { +- pins = "gpio47", "gpio48"; +- function = "blsp_i2c8"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- i2c11_pins: i2c11 { +- mux { +- pins = "gpio83", "gpio84"; +- function = "blsp_i2c11"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- lcd_backlight_en_pin_a: lcd-backlight-vddio { +- pins = "gpio69"; +- drive-strength = <10>; +- output-low; +- bias-disable; +- }; +- +- sdhc1_pin_a: sdhc1-pin-active { +- clk { +- pins = "sdc1_clk"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- cmd-data { +- pins = "sdc1_cmd", "sdc1_data"; +- drive-strength = <10>; +- bias-pull-up; +- }; +- }; +- +- sdhc2_cd_pin_a: sdhc2-cd-pin-active { +- pins = "gpio62"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- sdhc2_pin_a: sdhc2-pin-active { +- clk { +- pins = "sdc2_clk"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- cmd-data { +- pins = "sdc2_cmd", "sdc2_data"; +- drive-strength = <6>; +- bias-pull-up; +- }; +- }; +- +- sdhc3_pin_a: sdhc3-pin-active { +- clk { +- pins = "gpio40"; +- function = "sdc3"; +- +- drive-strength = <10>; +- bias-disable; +- }; +- +- cmd { +- pins = "gpio39"; +- function = "sdc3"; +- +- drive-strength = <10>; +- bias-pull-up; +- }; +- +- data { +- pins = "gpio35", "gpio36", "gpio37", "gpio38"; +- function = "sdc3"; +- +- drive-strength = <10>; +- bias-pull-up; +- }; +- }; +- +- ts_int_pin: synaptics { +- pin { +- pins = "gpio86"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- input-enable; +- }; +- }; +- +- bt_host_wake_pin: bt-host-wake { +- pins = "gpio95"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- output-low; +- }; +- +- bt_dev_wake_pin: bt-dev-wake { +- pins = "gpio96"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- i2c@f9964000 { +- status = "okay"; +- +- clock-frequency = <355000>; +- qcom,src-freq = <50000000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c8_pins>; +- +- synaptics@2c { +- compatible = "syna,rmi4-i2c"; +- reg = <0x2c>; +- +- interrupt-parent = <&msmgpio>; +- interrupts = <86 IRQ_TYPE_EDGE_FALLING>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- vdd-supply = <&pm8941_l22>; +- vio-supply = <&pm8941_lvs3>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&ts_int_pin>; +- +- syna,startup-delay-ms = <10>; +- +- rmi-f01@1 { +- reg = <0x1>; +- syna,nosleep = <1>; +- }; +- +- rmi-f11@11 { +- reg = <0x11>; +- syna,f11-flip-x = <1>; +- syna,sensor-type = <1>; +- }; +- }; +- }; +- +- i2c@f9967000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c11_pins>; +- clock-frequency = <355000>; +- qcom,src-freq = <50000000>; +- +- lp8566_wled: backlight@2c { +- compatible = "ti,lp8556"; +- reg = <0x2c>; +- power-supply = <&vreg_bl_vddio>; +- +- bl-name = "backlight"; +- dev-ctrl = /bits/ 8 <0x05>; +- init-brt = /bits/ 8 <0x3f>; +- rom_a0h { +- rom-addr = /bits/ 8 <0xa0>; +- rom-val = /bits/ 8 <0xff>; +- }; +- rom_a1h { +- rom-addr = /bits/ 8 <0xa1>; +- rom-val = /bits/ 8 <0x3f>; +- }; +- rom_a2h { +- rom-addr = /bits/ 8 <0xa2>; +- rom-val = /bits/ 8 <0x20>; +- }; +- rom_a3h { +- rom-addr = /bits/ 8 <0xa3>; +- rom-val = /bits/ 8 <0x5e>; +- }; +- rom_a4h { +- rom-addr = /bits/ 8 <0xa4>; +- rom-val = /bits/ 8 <0x02>; +- }; +- rom_a5h { +- rom-addr = /bits/ 8 <0xa5>; +- rom-val = /bits/ 8 <0x04>; +- }; +- rom_a6h { +- rom-addr = /bits/ 8 <0xa6>; +- rom-val = /bits/ 8 <0x80>; +- }; +- rom_a7h { +- rom-addr = /bits/ 8 <0xa7>; +- rom-val = /bits/ 8 <0xf7>; +- }; +- rom_a9h { +- rom-addr = /bits/ 8 <0xa9>; +- rom-val = /bits/ 8 <0x80>; +- }; +- rom_aah { +- rom-addr = /bits/ 8 <0xaa>; +- rom-val = /bits/ 8 <0x0f>; +- }; +- rom_aeh { +- rom-addr = /bits/ 8 <0xae>; +- rom-val = /bits/ 8 <0x0f>; +- }; +- }; +- }; +-}; +- +-&spmi_bus { +- pm8941@0 { +- charger@1000 { +- qcom,fast-charge-safe-current = <1500000>; +- qcom,fast-charge-current-limit = <1500000>; +- qcom,dc-current-limit = <1800000>; +- qcom,fast-charge-safe-voltage = <4400000>; +- qcom,fast-charge-high-threshold-voltage = <4350000>; +- qcom,fast-charge-low-threshold-voltage = <3400000>; +- qcom,auto-recharge-threshold-voltage = <4200000>; +- qcom,minimum-input-voltage = <4300000>; +- }; +- +- gpios@c000 { +- gpio_keys_pin_a: gpio-keys-active { +- pins = "gpio2", "gpio5"; +- function = "normal"; +- +- bias-pull-up; +- power-source = ; +- }; +- +- bt_reg_on_pin: bt-reg-on { +- pins = "gpio16"; +- function = "normal"; +- +- output-low; +- power-source = ; +- }; +- +- wlan_sleep_clk_pin: wl-sleep-clk { +- pins = "gpio17"; +- function = "func2"; +- +- output-high; +- power-source = ; +- }; +- +- wlan_regulator_pin: wl-reg-active { +- pins = "gpio18"; +- function = "normal"; +- +- bias-disable; +- power-source = ; +- }; +- +- lcd_dcdc_en_pin_a: lcd-dcdc-en-active { +- pins = "gpio20"; +- function = "normal"; +- +- bias-disable; +- power-source = ; +- input-disable; +- output-low; +- }; +- +- }; +- +- coincell@2800 { +- status = "okay"; +- qcom,rset-ohms = <2100>; +- qcom,vset-millivolts = <3000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-msm8974-sony-xperia-honami.dts b/scripts/dtc/include-prefixes/arm/qcom-msm8974-sony-xperia-honami.dts +deleted file mode 100644 +index 9743beebd84d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-msm8974-sony-xperia-honami.dts ++++ /dev/null +@@ -1,485 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "qcom-msm8974.dtsi" +-#include "qcom-pm8841.dtsi" +-#include "qcom-pm8941.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "Sony Xperia Z1"; +- compatible = "sony,xperia-honami", "qcom,msm8974"; +- +- aliases { +- serial0 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- input-name = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_pin_a>; +- +- volume-down { +- label = "volume_down"; +- gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- }; +- +- camera-snapshot { +- label = "camera_snapshot"; +- gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- }; +- +- camera-focus { +- label = "camera_focus"; +- gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- }; +- +- volume-up { +- label = "volume_up"; +- gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- }; +- }; +- +- memory@0 { +- reg = <0 0x40000000>, <0x40000000 0x40000000>; +- device_type = "memory"; +- }; +- +- smd { +- rpm { +- rpm_requests { +- pm8841-regulators { +- s1 { +- regulator-min-microvolt = <675000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- s2 { +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- s3 { +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- s4 { +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1050000>; +- }; +- }; +- +- pm8941-regulators { +- vdd_l1_l3-supply = <&pm8941_s1>; +- vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; +- vdd_l4_l11-supply = <&pm8941_s1>; +- vdd_l5_l7-supply = <&pm8941_s2>; +- vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; +- vdd_l9_l10_l17_l22-supply = <&vreg_boost>; +- vdd_l13_l20_l23_l24-supply = <&vreg_boost>; +- vdd_l21-supply = <&vreg_boost>; +- +- s1 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- s2 { +- regulator-min-microvolt = <2150000>; +- regulator-max-microvolt = <2150000>; +- regulator-boot-on; +- }; +- +- s3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- s4 { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- l1 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- +- regulator-always-on; +- regulator-boot-on; +- }; +- +- l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- l3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- l4 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- l5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-boot-on; +- }; +- +- l7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-boot-on; +- }; +- +- l8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l9 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- l11 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1350000>; +- }; +- +- l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-always-on; +- regulator-boot-on; +- }; +- +- l13 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-boot-on; +- }; +- +- l14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l15 { +- regulator-min-microvolt = <2050000>; +- regulator-max-microvolt = <2050000>; +- }; +- +- l16 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- l17 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- l18 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- l19 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l20 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-allow-set-load; +- regulator-boot-on; +- regulator-system-load = <200000>; +- }; +- +- l21 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- +- regulator-boot-on; +- }; +- +- l22 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- l23 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- l24 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- +- regulator-boot-on; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&soc { +- usb@f9a55000 { +- status = "okay"; +- +- phys = <&usb_hs1_phy>; +- phy-select = <&tcsr 0xb000 0>; +- extcon = <&smbb>, <&usb_id>; +- vbus-supply = <&chg_otg>; +- +- hnp-disable; +- srp-disable; +- adp-disable; +- +- ulpi { +- phy@a { +- status = "okay"; +- +- v1p8-supply = <&pm8941_l6>; +- v3p3-supply = <&pm8941_l24>; +- +- extcon = <&smbb>; +- qcom,init-seq = /bits/ 8 <0x1 0x64>; +- }; +- }; +- }; +- +- sdhci@f9824900 { +- status = "okay"; +- +- vmmc-supply = <&pm8941_l20>; +- vqmmc-supply = <&pm8941_s3>; +- +- bus-width = <8>; +- non-removable; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhc1_pin_a>; +- }; +- +- sdhci@f98a4900 { +- status = "okay"; +- +- bus-width = <4>; +- +- vmmc-supply = <&pm8941_l21>; +- vqmmc-supply = <&pm8941_l13>; +- +- cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; +- }; +- +- serial@f991e000 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp1_uart2_pin_a>; +- }; +- +- i2c@f9924000 { +- status = "okay"; +- +- clock-frequency = <355000>; +- qcom,src-freq = <50000000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- +- synaptics@2c { +- compatible = "syna,rmi4-i2c"; +- reg = <0x2c>; +- +- interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- vdd-supply = <&pm8941_l22>; +- vio-supply = <&pm8941_lvs3>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&ts_int_pin>; +- +- syna,startup-delay-ms = <10>; +- +- rmi4-f01@1 { +- reg = <0x1>; +- syna,nosleep-mode = <1>; +- }; +- +- rmi4-f11@11 { +- reg = <0x11>; +- touchscreen-inverted-x; +- syna,sensor-type = <1>; +- }; +- }; +- }; +- +- pinctrl@fd510000 { +- blsp1_uart2_pin_a: blsp1-uart2-pin-active { +- rx { +- pins = "gpio5"; +- function = "blsp_uart2"; +- +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- tx { +- pins = "gpio4"; +- function = "blsp_uart2"; +- +- drive-strength = <4>; +- bias-disable; +- }; +- }; +- +- i2c2_pins: i2c2 { +- mux { +- pins = "gpio6", "gpio7"; +- function = "blsp_i2c2"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- sdhc1_pin_a: sdhc1-pin-active { +- clk { +- pins = "sdc1_clk"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- cmd-data { +- pins = "sdc1_cmd", "sdc1_data"; +- drive-strength = <10>; +- bias-pull-up; +- }; +- }; +- +- sdhc2_cd_pin_a: sdhc2-cd-pin-active { +- pins = "gpio62"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- sdhc2_pin_a: sdhc2-pin-active { +- clk { +- pins = "sdc2_clk"; +- drive-strength = <10>; +- bias-disable; +- }; +- +- cmd-data { +- pins = "sdc2_cmd", "sdc2_data"; +- drive-strength = <6>; +- bias-pull-up; +- }; +- }; +- +- ts_int_pin: touch-int { +- pin { +- pins = "gpio61"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- input-enable; +- }; +- }; +- }; +- +- dma-controller@f9944000 { +- qcom,controlled-remotely; +- }; +-}; +- +-&spmi_bus { +- pm8941@0 { +- charger@1000 { +- qcom,fast-charge-safe-current = <1500000>; +- qcom,fast-charge-current-limit = <1500000>; +- qcom,dc-current-limit = <1800000>; +- qcom,fast-charge-safe-voltage = <4400000>; +- qcom,fast-charge-high-threshold-voltage = <4350000>; +- qcom,fast-charge-low-threshold-voltage = <3400000>; +- qcom,auto-recharge-threshold-voltage = <4200000>; +- qcom,minimum-input-voltage = <4300000>; +- }; +- +- gpios@c000 { +- gpio_keys_pin_a: gpio-keys-active { +- pins = "gpio2", "gpio3", "gpio4", "gpio5"; +- function = "normal"; +- +- bias-pull-up; +- power-source = ; +- }; +- }; +- +- coincell@2800 { +- status = "okay"; +- qcom,rset-ohms = <2100>; +- qcom,vset-millivolts = <3000>; +- }; +- }; +- +- pm8941@1 { +- wled@d800 { +- status = "okay"; +- +- qcom,cs-out; +- qcom,current-limit = <20>; +- qcom,current-boost-limit = <805>; +- qcom,switching-freq = <1600>; +- qcom,ovp = <29>; +- qcom,num-strings = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-msm8974.dtsi b/scripts/dtc/include-prefixes/arm/qcom-msm8974.dtsi +deleted file mode 100644 +index 2b01bc29ddf2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-msm8974.dtsi ++++ /dev/null +@@ -1,1704 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Qualcomm MSM8974"; +- compatible = "qcom,msm8974"; +- interrupt-parent = <&intc>; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- mpss_region: mpss@8000000 { +- reg = <0x08000000 0x5100000>; +- no-map; +- }; +- +- mba_region: mba@d100000 { +- reg = <0x0d100000 0x100000>; +- no-map; +- }; +- +- wcnss_region: wcnss@d200000 { +- reg = <0x0d200000 0xa00000>; +- no-map; +- }; +- +- adsp_region: adsp@dc00000 { +- reg = <0x0dc00000 0x1900000>; +- no-map; +- }; +- +- venus@f500000 { +- reg = <0x0f500000 0x500000>; +- no-map; +- }; +- +- smem_region: smem@fa00000 { +- reg = <0xfa00000 0x200000>; +- no-map; +- }; +- +- tz@fc00000 { +- reg = <0x0fc00000 0x160000>; +- no-map; +- }; +- +- rfsa@fd60000 { +- reg = <0x0fd60000 0x20000>; +- no-map; +- }; +- +- rmtfs@fd80000 { +- compatible = "qcom,rmtfs-mem"; +- reg = <0x0fd80000 0x180000>; +- no-map; +- +- qcom,client-id = <1>; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- +- CPU0: cpu@0 { +- compatible = "qcom,krait"; +- enable-method = "qcom,kpss-acc-v2"; +- device_type = "cpu"; +- reg = <0>; +- next-level-cache = <&L2>; +- qcom,acc = <&acc0>; +- qcom,saw = <&saw0>; +- cpu-idle-states = <&CPU_SPC>; +- }; +- +- CPU1: cpu@1 { +- compatible = "qcom,krait"; +- enable-method = "qcom,kpss-acc-v2"; +- device_type = "cpu"; +- reg = <1>; +- next-level-cache = <&L2>; +- qcom,acc = <&acc1>; +- qcom,saw = <&saw1>; +- cpu-idle-states = <&CPU_SPC>; +- }; +- +- CPU2: cpu@2 { +- compatible = "qcom,krait"; +- enable-method = "qcom,kpss-acc-v2"; +- device_type = "cpu"; +- reg = <2>; +- next-level-cache = <&L2>; +- qcom,acc = <&acc2>; +- qcom,saw = <&saw2>; +- cpu-idle-states = <&CPU_SPC>; +- }; +- +- CPU3: cpu@3 { +- compatible = "qcom,krait"; +- enable-method = "qcom,kpss-acc-v2"; +- device_type = "cpu"; +- reg = <3>; +- next-level-cache = <&L2>; +- qcom,acc = <&acc3>; +- qcom,saw = <&saw3>; +- cpu-idle-states = <&CPU_SPC>; +- }; +- +- L2: l2-cache { +- compatible = "cache"; +- cache-level = <2>; +- qcom,saw = <&saw_l2>; +- }; +- +- idle-states { +- CPU_SPC: spc { +- compatible = "qcom,idle-state-spc", +- "arm,idle-state"; +- entry-latency-us = <150>; +- exit-latency-us = <200>; +- min-residency-us = <2000>; +- }; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; +- }; +- +- thermal-zones { +- cpu-thermal0 { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 5>; +- +- trips { +- cpu_alert0: trip0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu_crit0: trip1 { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu-thermal1 { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 6>; +- +- trips { +- cpu_alert1: trip0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu_crit1: trip1 { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu-thermal2 { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 7>; +- +- trips { +- cpu_alert2: trip0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu_crit2: trip1 { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu-thermal3 { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 8>; +- +- trips { +- cpu_alert3: trip0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu_crit3: trip1 { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- q6-dsp-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 1>; +- +- trips { +- q6_dsp_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- modemtx-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 2>; +- +- trips { +- modemtx_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- video-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 3>; +- +- trips { +- video_alert0: trip-point0 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- wlan-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 4>; +- +- trips { +- wlan_alert0: trip-point0 { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- gpu-thermal-top { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 9>; +- +- trips { +- gpu1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- gpu-thermal-bottom { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 10>; +- +- trips { +- gpu2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- }; +- +- cpu-pmu { +- compatible = "qcom,krait-pmu"; +- interrupts = ; +- }; +- +- clocks { +- xo_board: xo_board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <19200000>; +- }; +- +- sleep_clk: sleep_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- clock-frequency = <19200000>; +- }; +- +- adsp-pil { +- compatible = "qcom,msm8974-adsp-pil"; +- +- interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; +- +- cx-supply = <&pm8841_s2>; +- +- clocks = <&xo_board>; +- clock-names = "xo"; +- +- memory-region = <&adsp_region>; +- +- qcom,smem-states = <&adsp_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- smd-edge { +- interrupts = ; +- +- qcom,ipc = <&apcs 8 8>; +- qcom,smd-edge = <1>; +- +- label = "lpass"; +- }; +- }; +- +- smem { +- compatible = "qcom,smem"; +- +- memory-region = <&smem_region>; +- qcom,rpm-msg-ram = <&rpm_msg_ram>; +- +- hwlocks = <&tcsr_mutex 3>; +- }; +- +- smp2p-adsp { +- compatible = "qcom,smp2p"; +- qcom,smem = <443>, <429>; +- +- interrupt-parent = <&intc>; +- interrupts = ; +- +- qcom,ipc = <&apcs 8 10>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <2>; +- +- adsp_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- adsp_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-modem { +- compatible = "qcom,smp2p"; +- qcom,smem = <435>, <428>; +- +- interrupt-parent = <&intc>; +- interrupts = ; +- +- qcom,ipc = <&apcs 8 14>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <1>; +- +- modem_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- modem_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-wcnss { +- compatible = "qcom,smp2p"; +- qcom,smem = <451>, <431>; +- +- interrupt-parent = <&intc>; +- interrupts = ; +- +- qcom,ipc = <&apcs 8 18>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <4>; +- +- wcnss_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- +- #qcom,smem-state-cells = <1>; +- }; +- +- wcnss_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smsm { +- compatible = "qcom,smsm"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- qcom,ipc-1 = <&apcs 8 13>; +- qcom,ipc-2 = <&apcs 8 9>; +- qcom,ipc-3 = <&apcs 8 19>; +- +- apps_smsm: apps@0 { +- reg = <0>; +- +- #qcom,smem-state-cells = <1>; +- }; +- +- modem_smsm: modem@1 { +- reg = <1>; +- interrupts = ; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- adsp_smsm: adsp@2 { +- reg = <2>; +- interrupts = ; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- wcnss_smsm: wcnss@7 { +- reg = <7>; +- interrupts = ; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- firmware { +- scm { +- compatible = "qcom,scm"; +- clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; +- clock-names = "core", "bus", "iface"; +- }; +- }; +- +- soc: soc { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "simple-bus"; +- +- intc: interrupt-controller@f9000000 { +- compatible = "qcom,msm-qgic2"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0xf9000000 0x1000>, +- <0xf9002000 0x1000>; +- }; +- +- apcs: syscon@f9011000 { +- compatible = "syscon"; +- reg = <0xf9011000 0x1000>; +- }; +- +- qfprom: qfprom@fc4bc000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "qcom,qfprom"; +- reg = <0xfc4bc000 0x1000>; +- tsens_calib: calib@d0 { +- reg = <0xd0 0x18>; +- }; +- tsens_backup: backup@440 { +- reg = <0x440 0x10>; +- }; +- }; +- +- tsens: thermal-sensor@fc4a9000 { +- compatible = "qcom,msm8974-tsens"; +- reg = <0xfc4a9000 0x1000>, /* TM */ +- <0xfc4a8000 0x1000>; /* SROT */ +- nvmem-cells = <&tsens_calib>, <&tsens_backup>; +- nvmem-cell-names = "calib", "calib_backup"; +- #qcom,sensors = <11>; +- interrupts = ; +- interrupt-names = "uplow"; +- #thermal-sensor-cells = <1>; +- }; +- +- timer@f9020000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "arm,armv7-timer-mem"; +- reg = <0xf9020000 0x1000>; +- clock-frequency = <19200000>; +- +- frame@f9021000 { +- frame-number = <0>; +- interrupts = , +- ; +- reg = <0xf9021000 0x1000>, +- <0xf9022000 0x1000>; +- }; +- +- frame@f9023000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0xf9023000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9024000 { +- frame-number = <2>; +- interrupts = ; +- reg = <0xf9024000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9025000 { +- frame-number = <3>; +- interrupts = ; +- reg = <0xf9025000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9026000 { +- frame-number = <4>; +- interrupts = ; +- reg = <0xf9026000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9027000 { +- frame-number = <5>; +- interrupts = ; +- reg = <0xf9027000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9028000 { +- frame-number = <6>; +- interrupts = ; +- reg = <0xf9028000 0x1000>; +- status = "disabled"; +- }; +- }; +- +- saw0: power-controller@f9089000 { +- compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; +- reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; +- }; +- +- saw1: power-controller@f9099000 { +- compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; +- reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; +- }; +- +- saw2: power-controller@f90a9000 { +- compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; +- reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; +- }; +- +- saw3: power-controller@f90b9000 { +- compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; +- reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; +- }; +- +- saw_l2: power-controller@f9012000 { +- compatible = "qcom,saw2"; +- reg = <0xf9012000 0x1000>; +- regulator; +- }; +- +- acc0: clock-controller@f9088000 { +- compatible = "qcom,kpss-acc-v2"; +- reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; +- }; +- +- acc1: clock-controller@f9098000 { +- compatible = "qcom,kpss-acc-v2"; +- reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; +- }; +- +- acc2: clock-controller@f90a8000 { +- compatible = "qcom,kpss-acc-v2"; +- reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; +- }; +- +- acc3: clock-controller@f90b8000 { +- compatible = "qcom,kpss-acc-v2"; +- reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; +- }; +- +- restart@fc4ab000 { +- compatible = "qcom,pshold"; +- reg = <0xfc4ab000 0x4>; +- }; +- +- gcc: clock-controller@fc400000 { +- compatible = "qcom,gcc-msm8974"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- reg = <0xfc400000 0x4000>; +- }; +- +- tcsr: syscon@fd4a0000 { +- compatible = "syscon"; +- reg = <0xfd4a0000 0x10000>; +- }; +- +- tcsr_mutex_block: syscon@fd484000 { +- compatible = "syscon"; +- reg = <0xfd484000 0x2000>; +- }; +- +- mmcc: clock-controller@fd8c0000 { +- compatible = "qcom,mmcc-msm8974"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- reg = <0xfd8c0000 0x6000>; +- }; +- +- tcsr_mutex: tcsr-mutex { +- compatible = "qcom,tcsr-mutex"; +- syscon = <&tcsr_mutex_block 0 0x80>; +- +- #hwlock-cells = <1>; +- }; +- +- rpm_msg_ram: memory@fc428000 { +- compatible = "qcom,rpm-msg-ram"; +- reg = <0xfc428000 0x4000>; +- }; +- +- blsp1_uart1: serial@f991d000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0xf991d000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- blsp1_uart2: serial@f991e000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0xf991e000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- blsp2_uart7: serial@f995d000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0xf995d000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- blsp2_uart8: serial@f995e000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0xf995e000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- blsp2_uart10: serial@f9960000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0xf9960000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- sdhci@f9824900 { +- compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; +- reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; +- reg-names = "hc_mem", "core_mem"; +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- clocks = <&gcc GCC_SDCC1_APPS_CLK>, +- <&gcc GCC_SDCC1_AHB_CLK>, +- <&xo_board>; +- clock-names = "core", "iface", "xo"; +- status = "disabled"; +- }; +- +- sdhci@f9864900 { +- compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; +- reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; +- reg-names = "hc_mem", "core_mem"; +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- clocks = <&gcc GCC_SDCC3_APPS_CLK>, +- <&gcc GCC_SDCC3_AHB_CLK>, +- <&xo_board>; +- clock-names = "core", "iface", "xo"; +- status = "disabled"; +- }; +- +- sdhci@f98a4900 { +- compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; +- reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; +- reg-names = "hc_mem", "core_mem"; +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- clocks = <&gcc GCC_SDCC2_APPS_CLK>, +- <&gcc GCC_SDCC2_AHB_CLK>, +- <&xo_board>; +- clock-names = "core", "iface", "xo"; +- status = "disabled"; +- }; +- +- otg: usb@f9a55000 { +- compatible = "qcom,ci-hdrc"; +- reg = <0xf9a55000 0x200>, +- <0xf9a55200 0x200>; +- interrupts = ; +- clocks = <&gcc GCC_USB_HS_AHB_CLK>, +- <&gcc GCC_USB_HS_SYSTEM_CLK>; +- clock-names = "iface", "core"; +- assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; +- assigned-clock-rates = <75000000>; +- resets = <&gcc GCC_USB_HS_BCR>; +- reset-names = "core"; +- phy_type = "ulpi"; +- dr_mode = "otg"; +- ahb-burst-config = <0>; +- phy-names = "usb-phy"; +- status = "disabled"; +- #reset-cells = <1>; +- +- ulpi { +- usb_hs1_phy: phy@a { +- compatible = "qcom,usb-hs-phy-msm8974", +- "qcom,usb-hs-phy"; +- #phy-cells = <0>; +- clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; +- clock-names = "ref", "sleep"; +- resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; +- reset-names = "phy", "por"; +- status = "disabled"; +- }; +- +- usb_hs2_phy: phy@b { +- compatible = "qcom,usb-hs-phy-msm8974", +- "qcom,usb-hs-phy"; +- #phy-cells = <0>; +- clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; +- clock-names = "ref", "sleep"; +- resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>; +- reset-names = "phy", "por"; +- status = "disabled"; +- }; +- }; +- }; +- +- rng@f9bff000 { +- compatible = "qcom,prng"; +- reg = <0xf9bff000 0x200>; +- clocks = <&gcc GCC_PRNG_AHB_CLK>; +- clock-names = "core"; +- }; +- +- remoteproc@fc880000 { +- compatible = "qcom,msm8974-mss-pil"; +- reg = <0xfc880000 0x100>, <0xfc820000 0x020>; +- reg-names = "qdsp6", "rmb"; +- +- interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; +- +- clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, +- <&gcc GCC_MSS_CFG_AHB_CLK>, +- <&gcc GCC_BOOT_ROM_AHB_CLK>, +- <&xo_board>; +- clock-names = "iface", "bus", "mem", "xo"; +- +- resets = <&gcc GCC_MSS_RESTART>; +- reset-names = "mss_restart"; +- +- cx-supply = <&pm8841_s2>; +- mss-supply = <&pm8841_s3>; +- mx-supply = <&pm8841_s1>; +- pll-supply = <&pm8941_l12>; +- +- qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>; +- +- qcom,smem-states = <&modem_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- mba { +- memory-region = <&mba_region>; +- }; +- +- mpss { +- memory-region = <&mpss_region>; +- }; +- +- smd-edge { +- interrupts = ; +- +- qcom,ipc = <&apcs 8 12>; +- qcom,smd-edge = <0>; +- +- label = "modem"; +- }; +- }; +- +- pronto: remoteproc@fb21b000 { +- compatible = "qcom,pronto-v2-pil", "qcom,pronto"; +- reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; +- reg-names = "ccu", "dxe", "pmu"; +- +- memory-region = <&wcnss_region>; +- +- interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, +- <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; +- +- vddpx-supply = <&pm8941_s3>; +- +- qcom,smem-states = <&wcnss_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- status = "disabled"; +- +- iris { +- compatible = "qcom,wcn3680"; +- +- clocks = <&rpmcc RPM_SMD_CXO_A2>; +- clock-names = "xo"; +- +- vddxo-supply = <&pm8941_l6>; +- vddrfa-supply = <&pm8941_l11>; +- vddpa-supply = <&pm8941_l19>; +- vdddig-supply = <&pm8941_s3>; +- }; +- +- smd-edge { +- interrupts = ; +- +- qcom,ipc = <&apcs 8 17>; +- qcom,smd-edge = <6>; +- +- wcnss { +- compatible = "qcom,wcnss"; +- qcom,smd-channels = "WCNSS_CTRL"; +- status = "disabled"; +- +- qcom,mmio = <&pronto>; +- +- bt { +- compatible = "qcom,wcnss-bt"; +- }; +- +- wifi { +- compatible = "qcom,wcnss-wlan"; +- +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- +- qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; +- qcom,smem-state-names = "tx-enable", "tx-rings-empty"; +- }; +- }; +- }; +- }; +- +- msmgpio: pinctrl@fd510000 { +- compatible = "qcom,msm8974-pinctrl"; +- reg = <0xfd510000 0x4000>; +- gpio-controller; +- gpio-ranges = <&msmgpio 0 0 146>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- +- i2c@f9923000 { +- status = "disabled"; +- compatible = "qcom,i2c-qup-v2.1.1"; +- reg = <0xf9923000 0x1000>; +- interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c@f9924000 { +- status = "disabled"; +- compatible = "qcom,i2c-qup-v2.1.1"; +- reg = <0xf9924000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- blsp_i2c3: i2c@f9925000 { +- status = "disabled"; +- compatible = "qcom,i2c-qup-v2.1.1"; +- reg = <0xf9925000 0x1000>; +- interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- blsp_i2c6: i2c@f9928000 { +- status = "disabled"; +- compatible = "qcom,i2c-qup-v2.1.1"; +- reg = <0xf9928000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- blsp_i2c8: i2c@f9964000 { +- status = "disabled"; +- compatible = "qcom,i2c-qup-v2.1.1"; +- reg = <0xf9964000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- blsp_i2c11: i2c@f9967000 { +- status = "disabled"; +- compatible = "qcom,i2c-qup-v2.1.1"; +- reg = <0xf9967000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- #address-cells = <1>; +- #size-cells = <0>; +- dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; +- dma-names = "tx", "rx"; +- }; +- +- blsp_i2c12: i2c@f9968000 { +- status = "disabled"; +- compatible = "qcom,i2c-qup-v2.1.1"; +- reg = <0xf9968000 0x1000>; +- interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spmi_bus: spmi@fc4cf000 { +- compatible = "qcom,spmi-pmic-arb"; +- reg-names = "core", "intr", "cnfg"; +- reg = <0xfc4cf000 0x1000>, +- <0xfc4cb000 0x1000>, +- <0xfc4ca000 0x1000>; +- interrupt-names = "periph_irq"; +- interrupts = ; +- qcom,ee = <0>; +- qcom,channel = <0>; +- #address-cells = <2>; +- #size-cells = <0>; +- interrupt-controller; +- #interrupt-cells = <4>; +- }; +- +- blsp2_dma: dma-controller@f9944000 { +- compatible = "qcom,bam-v1.4.0"; +- reg = <0xf9944000 0x19000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- }; +- +- etr@fc322000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0xfc322000 0x1000>; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- in-ports { +- port { +- etr_in: endpoint { +- remote-endpoint = <&replicator_out0>; +- }; +- }; +- }; +- }; +- +- tpiu@fc318000 { +- compatible = "arm,coresight-tpiu", "arm,primecell"; +- reg = <0xfc318000 0x1000>; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- in-ports { +- port { +- tpiu_in: endpoint { +- remote-endpoint = <&replicator_out1>; +- }; +- }; +- }; +- }; +- +- replicator@fc31c000 { +- compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; +- reg = <0xfc31c000 0x1000>; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- out-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- replicator_out0: endpoint { +- remote-endpoint = <&etr_in>; +- }; +- }; +- port@1 { +- reg = <1>; +- replicator_out1: endpoint { +- remote-endpoint = <&tpiu_in>; +- }; +- }; +- }; +- +- in-ports { +- port { +- replicator_in: endpoint { +- remote-endpoint = <&etf_out>; +- }; +- }; +- }; +- }; +- +- etf@fc307000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0xfc307000 0x1000>; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- out-ports { +- port { +- etf_out: endpoint { +- remote-endpoint = <&replicator_in>; +- }; +- }; +- }; +- +- in-ports { +- port { +- etf_in: endpoint { +- remote-endpoint = <&merger_out>; +- }; +- }; +- }; +- }; +- +- funnel@fc31b000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0xfc31b000 0x1000>; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* +- * Not described input ports: +- * 0 - connected trought funnel to Audio, Modem and +- * Resource and Power Manager CPU's +- * 2...7 - not-connected +- */ +- port@1 { +- reg = <1>; +- merger_in1: endpoint { +- remote-endpoint = <&funnel1_out>; +- }; +- }; +- }; +- +- out-ports { +- port { +- merger_out: endpoint { +- remote-endpoint = <&etf_in>; +- }; +- }; +- }; +- }; +- +- funnel@fc31a000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0xfc31a000 0x1000>; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* +- * Not described input ports: +- * 0 - not-connected +- * 1 - connected trought funnel to Multimedia CPU +- * 2 - connected to Wireless CPU +- * 3 - not-connected +- * 4 - not-connected +- * 6 - not-connected +- * 7 - connected to STM +- */ +- port@5 { +- reg = <5>; +- funnel1_in5: endpoint { +- remote-endpoint = <&kpss_out>; +- }; +- }; +- }; +- +- out-ports { +- port { +- funnel1_out: endpoint { +- remote-endpoint = <&merger_in1>; +- }; +- }; +- }; +- }; +- +- funnel@fc345000 { /* KPSS funnel only 4 inputs are used */ +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0xfc345000 0x1000>; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- kpss_in0: endpoint { +- remote-endpoint = <&etm0_out>; +- }; +- }; +- port@1 { +- reg = <1>; +- kpss_in1: endpoint { +- remote-endpoint = <&etm1_out>; +- }; +- }; +- port@2 { +- reg = <2>; +- kpss_in2: endpoint { +- remote-endpoint = <&etm2_out>; +- }; +- }; +- port@3 { +- reg = <3>; +- kpss_in3: endpoint { +- remote-endpoint = <&etm3_out>; +- }; +- }; +- }; +- +- out-ports { +- port { +- kpss_out: endpoint { +- remote-endpoint = <&funnel1_in5>; +- }; +- }; +- }; +- }; +- +- etm@fc33c000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0xfc33c000 0x1000>; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- cpu = <&CPU0>; +- +- out-ports { +- port { +- etm0_out: endpoint { +- remote-endpoint = <&kpss_in0>; +- }; +- }; +- }; +- }; +- +- etm@fc33d000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0xfc33d000 0x1000>; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- cpu = <&CPU1>; +- +- out-ports { +- port { +- etm1_out: endpoint { +- remote-endpoint = <&kpss_in1>; +- }; +- }; +- }; +- }; +- +- etm@fc33e000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0xfc33e000 0x1000>; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- cpu = <&CPU2>; +- +- out-ports { +- port { +- etm2_out: endpoint { +- remote-endpoint = <&kpss_in2>; +- }; +- }; +- }; +- }; +- +- etm@fc33f000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0xfc33f000 0x1000>; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- cpu = <&CPU3>; +- +- out-ports { +- port { +- etm3_out: endpoint { +- remote-endpoint = <&kpss_in3>; +- }; +- }; +- }; +- }; +- +- ocmem@fdd00000 { +- compatible = "qcom,msm8974-ocmem"; +- reg = <0xfdd00000 0x2000>, +- <0xfec00000 0x180000>; +- reg-names = "ctrl", +- "mem"; +- clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, +- <&mmcc OCMEMCX_OCMEMNOC_CLK>; +- clock-names = "core", +- "iface"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- gmu_sram: gmu-sram@0 { +- reg = <0x0 0x100000>; +- }; +- }; +- +- bimc: interconnect@fc380000 { +- reg = <0xfc380000 0x6a000>; +- compatible = "qcom,msm8974-bimc"; +- #interconnect-cells = <1>; +- clock-names = "bus", "bus_a"; +- clocks = <&rpmcc RPM_SMD_BIMC_CLK>, +- <&rpmcc RPM_SMD_BIMC_A_CLK>; +- }; +- +- snoc: interconnect@fc460000 { +- reg = <0xfc460000 0x4000>; +- compatible = "qcom,msm8974-snoc"; +- #interconnect-cells = <1>; +- clock-names = "bus", "bus_a"; +- clocks = <&rpmcc RPM_SMD_SNOC_CLK>, +- <&rpmcc RPM_SMD_SNOC_A_CLK>; +- }; +- +- pnoc: interconnect@fc468000 { +- reg = <0xfc468000 0x4000>; +- compatible = "qcom,msm8974-pnoc"; +- #interconnect-cells = <1>; +- clock-names = "bus", "bus_a"; +- clocks = <&rpmcc RPM_SMD_PNOC_CLK>, +- <&rpmcc RPM_SMD_PNOC_A_CLK>; +- }; +- +- ocmemnoc: interconnect@fc470000 { +- reg = <0xfc470000 0x4000>; +- compatible = "qcom,msm8974-ocmemnoc"; +- #interconnect-cells = <1>; +- clock-names = "bus", "bus_a"; +- clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, +- <&rpmcc RPM_SMD_OCMEMGX_A_CLK>; +- }; +- +- mmssnoc: interconnect@fc478000 { +- reg = <0xfc478000 0x4000>; +- compatible = "qcom,msm8974-mmssnoc"; +- #interconnect-cells = <1>; +- clock-names = "bus", "bus_a"; +- clocks = <&mmcc MMSS_S0_AXI_CLK>, +- <&mmcc MMSS_S0_AXI_CLK>; +- }; +- +- cnoc: interconnect@fc480000 { +- reg = <0xfc480000 0x4000>; +- compatible = "qcom,msm8974-cnoc"; +- #interconnect-cells = <1>; +- clock-names = "bus", "bus_a"; +- clocks = <&rpmcc RPM_SMD_CNOC_CLK>, +- <&rpmcc RPM_SMD_CNOC_A_CLK>; +- }; +- +- gpu: adreno@fdb00000 { +- status = "disabled"; +- +- compatible = "qcom,adreno-330.1", +- "qcom,adreno"; +- reg = <0xfdb00000 0x10000>; +- reg-names = "kgsl_3d0_reg_memory"; +- interrupts = ; +- interrupt-names = "kgsl_3d0_irq"; +- clock-names = "core", +- "iface", +- "mem_iface"; +- clocks = <&mmcc OXILI_GFX3D_CLK>, +- <&mmcc OXILICX_AHB_CLK>, +- <&mmcc OXILICX_AXI_CLK>; +- sram = <&gmu_sram>; +- power-domains = <&mmcc OXILICX_GDSC>; +- operating-points-v2 = <&gpu_opp_table>; +- +- interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, +- <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; +- interconnect-names = "gfx-mem", +- "ocmem"; +- +- // iommus = <&gpu_iommu 0>; +- +- gpu_opp_table: opp_table { +- compatible = "operating-points-v2"; +- +- opp-320000000 { +- opp-hz = /bits/ 64 <320000000>; +- }; +- +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- }; +- +- opp-27000000 { +- opp-hz = /bits/ 64 <27000000>; +- }; +- }; +- }; +- +- mdss: mdss@fd900000 { +- status = "disabled"; +- +- compatible = "qcom,mdss"; +- reg = <0xfd900000 0x100>, +- <0xfd924000 0x1000>; +- reg-names = "mdss_phys", +- "vbif_phys"; +- +- power-domains = <&mmcc MDSS_GDSC>; +- +- clocks = <&mmcc MDSS_AHB_CLK>, +- <&mmcc MDSS_AXI_CLK>, +- <&mmcc MDSS_VSYNC_CLK>; +- clock-names = "iface", +- "bus", +- "vsync"; +- +- interrupts = ; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- mdp: mdp@fd900000 { +- status = "disabled"; +- +- compatible = "qcom,mdp5"; +- reg = <0xfd900100 0x22000>; +- reg-names = "mdp_phys"; +- +- interrupt-parent = <&mdss>; +- interrupts = <0 0>; +- +- clocks = <&mmcc MDSS_AHB_CLK>, +- <&mmcc MDSS_AXI_CLK>, +- <&mmcc MDSS_MDP_CLK>, +- <&mmcc MDSS_VSYNC_CLK>; +- clock-names = "iface", +- "bus", +- "core", +- "vsync"; +- +- interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; +- interconnect-names = "mdp0-mem"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- mdp5_intf1_out: endpoint { +- remote-endpoint = <&dsi0_in>; +- }; +- }; +- }; +- }; +- +- dsi0: dsi@fd922800 { +- status = "disabled"; +- +- compatible = "qcom,mdss-dsi-ctrl"; +- reg = <0xfd922800 0x1f8>; +- reg-names = "dsi_ctrl"; +- +- interrupt-parent = <&mdss>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +- +- assigned-clocks = <&mmcc BYTE0_CLK_SRC>, +- <&mmcc PCLK0_CLK_SRC>; +- assigned-clock-parents = <&dsi_phy0 0>, +- <&dsi_phy0 1>; +- +- clocks = <&mmcc MDSS_MDP_CLK>, +- <&mmcc MDSS_AHB_CLK>, +- <&mmcc MDSS_AXI_CLK>, +- <&mmcc MDSS_BYTE0_CLK>, +- <&mmcc MDSS_PCLK0_CLK>, +- <&mmcc MDSS_ESC0_CLK>, +- <&mmcc MMSS_MISC_AHB_CLK>; +- clock-names = "mdp_core", +- "iface", +- "bus", +- "byte", +- "pixel", +- "core", +- "core_mmss"; +- +- phys = <&dsi_phy0>; +- phy-names = "dsi-phy"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dsi0_in: endpoint { +- remote-endpoint = <&mdp5_intf1_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- dsi0_out: endpoint { +- }; +- }; +- }; +- }; +- +- dsi_phy0: dsi-phy@fd922a00 { +- status = "disabled"; +- +- compatible = "qcom,dsi-phy-28nm-hpm"; +- reg = <0xfd922a00 0xd4>, +- <0xfd922b00 0x280>, +- <0xfd922d80 0x30>; +- reg-names = "dsi_pll", +- "dsi_phy", +- "dsi_phy_regulator"; +- +- #clock-cells = <1>; +- #phy-cells = <0>; +- qcom,dsi-phy-index = <0>; +- +- clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; +- clock-names = "iface", "ref"; +- }; +- }; +- +- imem@fe805000 { +- status = "disabled"; +- compatible = "syscon", "simple-mfd"; +- reg = <0xfe805000 0x1000>; +- +- reboot-mode { +- compatible = "syscon-reboot-mode"; +- offset = <0x65c>; +- }; +- }; +- }; +- +- smd { +- compatible = "qcom,smd"; +- +- rpm { +- interrupts = ; +- qcom,ipc = <&apcs 8 0>; +- qcom,smd-edge = <15>; +- +- rpm_requests { +- compatible = "qcom,rpm-msm8974"; +- qcom,smd-channels = "rpm_requests"; +- +- rpmcc: clock-controller { +- compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; +- #clock-cells = <1>; +- }; +- +- pm8841-regulators { +- compatible = "qcom,rpm-pm8841-regulators"; +- +- pm8841_s1: s1 {}; +- pm8841_s2: s2 {}; +- pm8841_s3: s3 {}; +- pm8841_s4: s4 {}; +- pm8841_s5: s5 {}; +- pm8841_s6: s6 {}; +- pm8841_s7: s7 {}; +- pm8841_s8: s8 {}; +- }; +- +- pm8941-regulators { +- compatible = "qcom,rpm-pm8941-regulators"; +- +- pm8941_s1: s1 {}; +- pm8941_s2: s2 {}; +- pm8941_s3: s3 {}; +- +- pm8941_l1: l1 {}; +- pm8941_l2: l2 {}; +- pm8941_l3: l3 {}; +- pm8941_l4: l4 {}; +- pm8941_l5: l5 {}; +- pm8941_l6: l6 {}; +- pm8941_l7: l7 {}; +- pm8941_l8: l8 {}; +- pm8941_l9: l9 {}; +- pm8941_l10: l10 {}; +- pm8941_l11: l11 {}; +- pm8941_l12: l12 {}; +- pm8941_l13: l13 {}; +- pm8941_l14: l14 {}; +- pm8941_l15: l15 {}; +- pm8941_l16: l16 {}; +- pm8941_l17: l17 {}; +- pm8941_l18: l18 {}; +- pm8941_l19: l19 {}; +- pm8941_l20: l20 {}; +- pm8941_l21: l21 {}; +- pm8941_l22: l22 {}; +- pm8941_l23: l23 {}; +- pm8941_l24: l24 {}; +- +- pm8941_lvs1: lvs1 {}; +- pm8941_lvs2: lvs2 {}; +- pm8941_lvs3: lvs3 {}; +- }; +- }; +- }; +- }; +- +- vreg_boost: vreg-boost { +- compatible = "regulator-fixed"; +- +- regulator-name = "vreg-boost"; +- regulator-min-microvolt = <3150000>; +- regulator-max-microvolt = <3150000>; +- +- regulator-always-on; +- regulator-boot-on; +- +- gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&boost_bypass_n_pin>; +- }; +- vreg_vph_pwr: vreg-vph-pwr { +- compatible = "regulator-fixed"; +- regulator-name = "vph-pwr"; +- +- regulator-min-microvolt = <3600000>; +- regulator-max-microvolt = <3600000>; +- +- regulator-always-on; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-msm8974pro.dtsi b/scripts/dtc/include-prefixes/arm/qcom-msm8974pro.dtsi +deleted file mode 100644 +index b64c28036dd0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-msm8974pro.dtsi ++++ /dev/null +@@ -1,23 +0,0 @@ +-#include "qcom-msm8974.dtsi" +- +-/ { +- soc { +- sdhci@f9824900 { +- clocks = <&gcc GCC_SDCC1_APPS_CLK>, +- <&gcc GCC_SDCC1_AHB_CLK>, +- <&xo_board>, +- <&gcc GCC_SDCC1_CDCCAL_FF_CLK>, +- <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>; +- clock-names = "core", "iface", "xo", "cal", "sleep"; +- }; +- +- clock-controller@fc400000 { +- compatible = "qcom,gcc-msm8974pro"; +- }; +- +- adreno@fdb00000 { +- compatible = "qcom,adreno-330.2", +- "qcom,adreno"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-pm8841.dtsi b/scripts/dtc/include-prefixes/arm/qcom-pm8841.dtsi +deleted file mode 100644 +index 2fd59c440903..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-pm8841.dtsi ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +- +-&spmi_bus { +- +- pm8841_0: pm8841@4 { +- compatible = "qcom,pm8841", "qcom,spmi-pmic"; +- reg = <0x4 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm8841_mpps: mpps@a000 { +- compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp"; +- reg = <0xa000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = <4 0xa0 0 IRQ_TYPE_NONE>, +- <4 0xa1 0 IRQ_TYPE_NONE>, +- <4 0xa2 0 IRQ_TYPE_NONE>, +- <4 0xa3 0 IRQ_TYPE_NONE>; +- }; +- +- temp-alarm@2400 { +- compatible = "qcom,spmi-temp-alarm"; +- reg = <0x2400>; +- interrupts = <4 0x24 0 IRQ_TYPE_EDGE_RISING>; +- }; +- }; +- +- pm8841_1: pm8841@5 { +- compatible = "qcom,pm8841", "qcom,spmi-pmic"; +- reg = <0x5 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-pm8941.dtsi b/scripts/dtc/include-prefixes/arm/qcom-pm8941.dtsi +deleted file mode 100644 +index c1f2012d1c8b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-pm8941.dtsi ++++ /dev/null +@@ -1,193 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +-#include +- +-&spmi_bus { +- +- pm8941_0: pm8941@0 { +- compatible = "qcom,pm8941", "qcom,spmi-pmic"; +- reg = <0x0 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtc@6000 { +- compatible = "qcom,pm8941-rtc"; +- reg = <0x6000>, +- <0x6100>; +- reg-names = "rtc", "alarm"; +- interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; +- }; +- +- pwrkey@800 { +- compatible = "qcom,pm8941-pwrkey"; +- reg = <0x800>; +- interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; +- debounce = <15625>; +- bias-pull-up; +- }; +- +- usb_id: misc@900 { +- compatible = "qcom,pm8941-misc"; +- reg = <0x900>; +- interrupts = <0x0 0x9 0 IRQ_TYPE_EDGE_BOTH>; +- interrupt-names = "usb_id"; +- }; +- +- smbb: charger@1000 { +- compatible = "qcom,pm8941-charger"; +- reg = <0x1000>; +- interrupts = <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>, +- <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>, +- <0x0 0x10 4 IRQ_TYPE_EDGE_BOTH>, +- <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>, +- <0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>, +- <0x0 0x13 2 IRQ_TYPE_EDGE_BOTH>, +- <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>, +- <0x0 0x14 1 IRQ_TYPE_EDGE_BOTH>; +- interrupt-names = "chg-done", +- "chg-fast", +- "chg-trkl", +- "bat-temp-ok", +- "bat-present", +- "chg-gone", +- "usb-valid", +- "dc-valid"; +- +- usb-otg-in-supply = <&pm8941_5vs1>; +- +- chg_otg: otg-vbus { }; +- }; +- +- pm8941_gpios: gpios@c000 { +- compatible = "qcom,pm8941-gpio", "qcom,spmi-gpio"; +- reg = <0xc000>; +- gpio-controller; +- gpio-ranges = <&pm8941_gpios 0 0 36>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- boost_bypass_n_pin: boost-bypass { +- pins = "gpio21"; +- function = "normal"; +- }; +- }; +- +- pm8941_mpps: mpps@a000 { +- compatible = "qcom,pm8941-mpp", "qcom,spmi-mpp"; +- reg = <0xa000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, +- <0 0xa1 0 IRQ_TYPE_NONE>, +- <0 0xa2 0 IRQ_TYPE_NONE>, +- <0 0xa3 0 IRQ_TYPE_NONE>, +- <0 0xa4 0 IRQ_TYPE_NONE>, +- <0 0xa5 0 IRQ_TYPE_NONE>, +- <0 0xa6 0 IRQ_TYPE_NONE>, +- <0 0xa7 0 IRQ_TYPE_NONE>; +- }; +- +- pm8941_temp: temp-alarm@2400 { +- compatible = "qcom,spmi-temp-alarm"; +- reg = <0x2400>; +- interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; +- io-channels = <&pm8941_vadc VADC_DIE_TEMP>; +- io-channel-names = "thermal"; +- #thermal-sensor-cells = <0>; +- }; +- +- pm8941_vadc: vadc@3100 { +- compatible = "qcom,spmi-vadc"; +- reg = <0x3100>; +- interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; +- #address-cells = <1>; +- #size-cells = <0>; +- #io-channel-cells = <1>; +- +- bat_temp { +- reg = ; +- }; +- die_temp { +- reg = ; +- }; +- ref_625mv { +- reg = ; +- }; +- ref_1250v { +- reg = ; +- }; +- ref_gnd { +- reg = ; +- }; +- ref_vdd { +- reg = ; +- }; +- vbat_sns { +- reg = ; +- }; +- }; +- +- pm8941_iadc: iadc@3600 { +- compatible = "qcom,pm8941-iadc", "qcom,spmi-iadc"; +- reg = <0x3600>; +- interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>; +- qcom,external-resistor-micro-ohms = <10000>; +- }; +- +- coincell@2800 { +- compatible = "qcom,pm8941-coincell"; +- reg = <0x2800>; +- status = "disabled"; +- }; +- }; +- +- pm8941_1: pm8941@1 { +- compatible = "qcom,pm8941", "qcom,spmi-pmic"; +- reg = <0x1 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm8941_wled: wled@d800 { +- compatible = "qcom,pm8941-wled"; +- reg = <0xd800>; +- label = "backlight"; +- +- status = "disabled"; +- }; +- +- regulators { +- compatible = "qcom,pm8941-regulators"; +- interrupts = <0x1 0x83 0x2 0>, <0x1 0x84 0x2 0>; +- interrupt-names = "ocp-5vs1", "ocp-5vs2"; +- vin_5vs-supply = <&pm8941_5v>; +- +- pm8941_5v: s4 { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-enable-ramp-delay = <500>; +- }; +- +- pm8941_5vs1: 5vs1 { +- regulator-enable-ramp-delay = <1000>; +- regulator-pull-down; +- regulator-over-current-protection; +- qcom,ocp-max-retries = <10>; +- qcom,ocp-retry-delay = <30>; +- qcom,vs-soft-start-strength = <0>; +- regulator-initial-mode = <1>; +- }; +- +- pm8941_5vs2: 5vs2 { +- regulator-enable-ramp-delay = <1000>; +- regulator-pull-down; +- regulator-over-current-protection; +- qcom,ocp-max-retries = <10>; +- qcom,ocp-retry-delay = <30>; +- qcom,vs-soft-start-strength = <0>; +- regulator-initial-mode = <1>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-pma8084.dtsi b/scripts/dtc/include-prefixes/arm/qcom-pma8084.dtsi +deleted file mode 100644 +index e921c5e93a5d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-pma8084.dtsi ++++ /dev/null +@@ -1,99 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +-#include +- +-&spmi_bus { +- +- pma8084_0: pma8084@0 { +- compatible = "qcom,pma8084", "qcom,spmi-pmic"; +- reg = <0x0 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtc@6000 { +- compatible = "qcom,pm8941-rtc"; +- reg = <0x6000>, +- <0x6100>; +- reg-names = "rtc", "alarm"; +- interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; +- }; +- +- pwrkey@800 { +- compatible = "qcom,pm8941-pwrkey"; +- reg = <0x800>; +- interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; +- debounce = <15625>; +- bias-pull-up; +- }; +- +- pma8084_gpios: gpios@c000 { +- compatible = "qcom,pma8084-gpio", "qcom,spmi-gpio"; +- reg = <0xc000>; +- gpio-controller; +- gpio-ranges = <&pma8084_gpios 0 0 22>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pma8084_mpps: mpps@a000 { +- compatible = "qcom,pma8084-mpp", "qcom,spmi-mpp"; +- reg = <0xa000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, +- <0 0xa1 0 IRQ_TYPE_NONE>, +- <0 0xa2 0 IRQ_TYPE_NONE>, +- <0 0xa3 0 IRQ_TYPE_NONE>, +- <0 0xa4 0 IRQ_TYPE_NONE>, +- <0 0xa5 0 IRQ_TYPE_NONE>, +- <0 0xa6 0 IRQ_TYPE_NONE>, +- <0 0xa7 0 IRQ_TYPE_NONE>; +- }; +- +- pma8084_temp: temp-alarm@2400 { +- compatible = "qcom,spmi-temp-alarm"; +- reg = <0x2400>; +- interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; +- #thermal-sensor-cells = <0>; +- io-channels = <&pma8084_vadc VADC_DIE_TEMP>; +- io-channel-names = "thermal"; +- }; +- +- pma8084_vadc: vadc@3100 { +- compatible = "qcom,spmi-vadc"; +- reg = <0x3100>; +- interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; +- #address-cells = <1>; +- #size-cells = <0>; +- #io-channel-cells = <1>; +- +- die_temp { +- reg = ; +- }; +- ref_625mv { +- reg = ; +- }; +- ref_1250v { +- reg = ; +- }; +- ref_buf_625mv { +- reg = ; +- }; +- ref_gnd { +- reg = ; +- }; +- ref_vdd { +- reg = ; +- }; +- }; +- }; +- +- pma8084_1: pma8084@1 { +- compatible = "qcom,pma8084", "qcom,spmi-pmic"; +- reg = <0x1 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-pmx55.dtsi b/scripts/dtc/include-prefixes/arm/qcom-pmx55.dtsi +deleted file mode 100644 +index 6571b88d018a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-pmx55.dtsi ++++ /dev/null +@@ -1,84 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +- +-/* +- * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. +- * Copyright (c) 2020, Linaro Limited +- */ +- +-#include +-#include +-#include +- +-&spmi_bus { +- pmic@8 { +- compatible = "qcom,pmx55", "qcom,spmi-pmic"; +- reg = <0x8 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- power-on@800 { +- compatible = "qcom,pm8916-pon"; +- reg = <0x0800>; +- +- status = "disabled"; +- }; +- +- pmx55_temp: temp-alarm@2400 { +- compatible = "qcom,spmi-temp-alarm"; +- reg = <0x2400>; +- interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; +- io-channels = <&pmx55_adc ADC5_DIE_TEMP>; +- io-channel-names = "thermal"; +- #thermal-sensor-cells = <0>; +- }; +- +- pmx55_adc: adc@3100 { +- compatible = "qcom,spmi-adc5"; +- reg = <0x3100>; +- #address-cells = <1>; +- #size-cells = <0>; +- #io-channel-cells = <1>; +- interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>; +- +- ref-gnd@0 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "ref_gnd"; +- }; +- +- vref-1p25@1 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "vref_1p25"; +- }; +- +- die-temp@6 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "die_temp"; +- }; +- +- chg-temp@9 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "chg_temp"; +- }; +- }; +- +- pmx55_gpios: gpio@c000 { +- compatible = "qcom,pmx55-gpio", "qcom,spmi-gpio"; +- reg = <0xc000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- pmic@9 { +- compatible = "qcom,pmx55", "qcom,spmi-pmic"; +- reg = <0x9 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-sdx55-mtp.dts b/scripts/dtc/include-prefixes/arm/qcom-sdx55-mtp.dts +deleted file mode 100644 +index 9649c1e11311..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-sdx55-mtp.dts ++++ /dev/null +@@ -1,251 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. +- * Copyright (c) 2020, Linaro Ltd. +- */ +- +-/dts-v1/; +- +-#include "qcom-sdx55.dtsi" +-#include +-#include +-#include "qcom-pmx55.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. SDX55 MTP"; +- compatible = "qcom,sdx55-mtp", "qcom,sdx55"; +- qcom,board-id = <0x5010008 0x0>; +- +- aliases { +- serial0 = &blsp1_uart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- mpss_debug_mem: memory@8ef00000 { +- no-map; +- reg = <0x8ef00000 0x800000>; +- }; +- +- ipa_fw_mem: memory@8fced000 { +- no-map; +- reg = <0x8fced000 0x10000>; +- }; +- +- mpss_adsp_mem: memory@90c00000 { +- no-map; +- reg = <0x90c00000 0xd400000>; +- }; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- }; +- +- vreg_bob_3p3: pmx55-bob { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_bob_3p3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-always-on; +- regulator-boot-on; +- +- vin-supply = <&vph_pwr>; +- }; +- +- vreg_s7e_mx_0p752: pmx55-s7e { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_s7e_mx_0p752"; +- regulator-min-microvolt = <752000>; +- regulator-max-microvolt = <752000>; +- +- vin-supply = <&vph_pwr>; +- }; +-}; +- +-&apps_rsc { +- pmx55-rpmh-regulators { +- compatible = "qcom,pmx55-rpmh-regulators"; +- qcom,pmic-id = "e"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-l1-l2-supply = <&vreg_s2e_1p224>; +- vdd-l3-l9-supply = <&vreg_s3e_0p824>; +- vdd-l4-l12-supply = <&vreg_s4e_1p904>; +- vdd-l5-l6-supply = <&vreg_s4e_1p904>; +- vdd-l7-l8-supply = <&vreg_s3e_0p824>; +- vdd-l10-l11-l13-supply = <&vreg_bob_3p3>; +- vdd-l14-supply = <&vreg_s7e_mx_0p752>; +- vdd-l15-supply = <&vreg_s2e_1p224>; +- vdd-l16-supply = <&vreg_s4e_1p904>; +- +- vreg_s2e_1p224: smps2 { +- regulator-min-microvolt = <1280000>; +- regulator-max-microvolt = <1400000>; +- }; +- +- vreg_s3e_0p824: smps3 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- vreg_s4e_1p904: smps4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1960000>; +- }; +- +- vreg_l1e_bb_1p2: ldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- ldo2 { +- regulator-min-microvolt = <1128000>; +- regulator-max-microvolt = <1128000>; +- regulator-initial-mode = ; +- }; +- +- ldo3 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l4e_bb_0p875: ldo4 { +- regulator-min-microvolt = <872000>; +- regulator-max-microvolt = <872000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5e_bb_1p7: ldo5 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <1900000>; +- regulator-initial-mode = ; +- }; +- +- ldo6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- ldo7 { +- regulator-min-microvolt = <480000>; +- regulator-max-microvolt = <900000>; +- regulator-initial-mode = ; +- }; +- +- ldo8 { +- regulator-min-microvolt = <480000>; +- regulator-max-microvolt = <900000>; +- regulator-initial-mode = ; +- }; +- +- ldo9 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10e_3p1: ldo10 { +- regulator-min-microvolt = <3088000>; +- regulator-max-microvolt = <3088000>; +- regulator-initial-mode = ; +- }; +- +- ldo11 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- ldo12 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- ldo13 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- ldo14 { +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- ldo15 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- ldo16 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <1904000>; +- regulator-initial-mode = ; +- }; +- }; +-}; +- +-&blsp1_uart3 { +- status = "okay"; +-}; +- +-&qpic_bam { +- status = "okay"; +-}; +- +-&qpic_nand { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- +- nand-ecc-strength = <8>; +- nand-ecc-step-size = <512>; +- nand-bus-width = <8>; +- }; +-}; +- +-&usb { +- status = "okay"; +-}; +- +-&usb_dwc3 { +- dr_mode = "peripheral"; +-}; +- +-&usb_hsphy { +- status = "okay"; +- vdda-pll-supply = <&vreg_l4e_bb_0p875>; +- vdda33-supply = <&vreg_l10e_3p1>; +- vdda18-supply = <&vreg_l5e_bb_1p7>; +-}; +- +-&usb_qmpphy { +- status = "okay"; +- vdda-phy-supply = <&vreg_l4e_bb_0p875>; +- vdda-pll-supply = <&vreg_l1e_bb_1p2>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-sdx55-t55.dts b/scripts/dtc/include-prefixes/arm/qcom-sdx55-t55.dts +deleted file mode 100644 +index 2ffcd085904d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-sdx55-t55.dts ++++ /dev/null +@@ -1,281 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Linaro Ltd. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "qcom-sdx55.dtsi" +-#include "qcom-pmx55.dtsi" +- +-/ { +- model = "Thundercomm T55 Development Kit"; +- compatible = "qcom,sdx55-t55", "qcom,sdx55"; +- qcom,board-id = <0xb010008 0x4>; +- +- aliases { +- serial0 = &blsp1_uart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- mpss_debug_mem: memory@8ef00000 { +- no-map; +- reg = <0x8ef00000 0x800000>; +- }; +- +- ipa_fw_mem: memory@8fced000 { +- no-map; +- reg = <0x8fced000 0x10000>; +- }; +- +- mpss_adsp_mem: memory@90800000 { +- no-map; +- reg = <0x90800000 0xf800000>; +- }; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- }; +- +- vreg_bob_3p3: pmx55-bob { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_bob_3p3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-always-on; +- regulator-boot-on; +- +- vin-supply = <&vph_pwr>; +- }; +- +- vreg_s7e_mx_0p752: pmx55-s7e { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_s7e_mx_0p752"; +- regulator-min-microvolt = <752000>; +- regulator-max-microvolt = <752000>; +- +- vin-supply = <&vph_pwr>; +- }; +- +- vreg_sd_vdd: sd-vdd { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_sd_vdd"; +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- +- vin-supply = <&vreg_vddpx_2>; +- }; +- +- vreg_vddpx_2: vddpx-2 { +- compatible = "regulator-gpio"; +- regulator-name = "vreg_vddpx_2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2850000>; +- enable-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; +- gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; +- states = <1800000 0>, <2850000 1>; +- startup-delay-us = <200000>; +- enable-active-high; +- regulator-boot-on; +- +- vin-supply = <&vph_pwr>; +- }; +-}; +- +-&apps_rsc { +- pmx55-rpmh-regulators { +- compatible = "qcom,pmx55-rpmh-regulators"; +- qcom,pmic-id = "e"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-l1-l2-supply = <&vreg_s2e_1p224>; +- vdd-l3-l9-supply = <&vreg_s3e_0p824>; +- vdd-l4-l12-supply = <&vreg_s4e_1p904>; +- vdd-l5-l6-supply = <&vreg_s4e_1p904>; +- vdd-l7-l8-supply = <&vreg_s3e_0p824>; +- vdd-l10-l11-l13-supply = <&vreg_bob_3p3>; +- vdd-l14-supply = <&vreg_s7e_mx_0p752>; +- vdd-l15-supply = <&vreg_s2e_1p224>; +- vdd-l16-supply = <&vreg_s4e_1p904>; +- +- vreg_s2e_1p224: smps2 { +- regulator-min-microvolt = <1280000>; +- regulator-max-microvolt = <1400000>; +- }; +- +- vreg_s3e_0p824: smps3 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- vreg_s4e_1p904: smps4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1960000>; +- }; +- +- vreg_l1e_bb_1p2: ldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- ldo2 { +- regulator-min-microvolt = <1128000>; +- regulator-max-microvolt = <1128000>; +- regulator-initial-mode = ; +- }; +- +- ldo3 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l4e_bb_0p875: ldo4 { +- regulator-min-microvolt = <872000>; +- regulator-max-microvolt = <872000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5e_bb_1p7: ldo5 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <1900000>; +- regulator-initial-mode = ; +- }; +- +- ldo6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- ldo7 { +- regulator-min-microvolt = <480000>; +- regulator-max-microvolt = <900000>; +- regulator-initial-mode = ; +- }; +- +- ldo8 { +- regulator-min-microvolt = <480000>; +- regulator-max-microvolt = <900000>; +- regulator-initial-mode = ; +- }; +- +- ldo9 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10e_3p1: ldo10 { +- regulator-min-microvolt = <3088000>; +- regulator-max-microvolt = <3088000>; +- regulator-initial-mode = ; +- }; +- +- ldo11 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- ldo12 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- ldo13 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- ldo14 { +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- ldo15 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- ldo16 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <1904000>; +- regulator-initial-mode = ; +- }; +- }; +-}; +- +-&blsp1_uart3 { +- status = "ok"; +-}; +- +-&qpic_bam { +- status = "ok"; +-}; +- +-&qpic_nand { +- status = "ok"; +- +- nand@0 { +- reg = <0>; +- +- nand-ecc-strength = <8>; +- nand-ecc-step-size = <512>; +- nand-bus-width = <8>; +- /* efs2 partition is secured */ +- secure-regions = /bits/ 64 <0x500000 0xb00000>; +- }; +-}; +- +-&remoteproc_mpss { +- status = "okay"; +- memory-region = <&mpss_adsp_mem>; +-}; +- +-&usb_hsphy { +- status = "okay"; +- vdda-pll-supply = <&vreg_l4e_bb_0p875>; +- vdda33-supply = <&vreg_l10e_3p1>; +- vdda18-supply = <&vreg_l5e_bb_1p7>; +-}; +- +-&usb_qmpphy { +- status = "okay"; +- vdda-phy-supply = <&vreg_l4e_bb_0p875>; +- vdda-pll-supply = <&vreg_l1e_bb_1p2>; +-}; +- +-&usb { +- status = "okay"; +-}; +- +-&usb_dwc3 { +- dr_mode = "peripheral"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-sdx55-telit-fn980-tlb.dts b/scripts/dtc/include-prefixes/arm/qcom-sdx55-telit-fn980-tlb.dts +deleted file mode 100644 +index 80c40da79604..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-sdx55-telit-fn980-tlb.dts ++++ /dev/null +@@ -1,282 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Linaro Ltd. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "qcom-sdx55.dtsi" +-#include "qcom-pmx55.dtsi" +- +-/ { +- model = "Telit FN980 TLB"; +- compatible = "qcom,sdx55-telit-fn980-tlb", "qcom,sdx55"; +- qcom,board-id = <0xb010008 0x0>; +- +- aliases { +- serial0 = &blsp1_uart3; +- }; +- +- chosen { +- stdout-path = "serial0:921600n8"; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- mpss_debug_mem: memory@8ef00000 { +- no-map; +- reg = <0x8ef00000 0x800000>; +- }; +- +- ipa_fw_mem: memory@8fced000 { +- no-map; +- reg = <0x8fced000 0x10000>; +- }; +- +- mpss_adsp_mem: memory@90800000 { +- no-map; +- reg = <0x90800000 0xf800000>; +- }; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- }; +- +- vreg_bob_3p3: pmx55-bob { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_bob_3p3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-always-on; +- regulator-boot-on; +- +- vin-supply = <&vph_pwr>; +- }; +- +- vreg_s7e_mx_0p752: pmx55-s7e { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_s7e_mx_0p752"; +- regulator-min-microvolt = <752000>; +- regulator-max-microvolt = <752000>; +- +- vin-supply = <&vph_pwr>; +- }; +- +- vreg_sd_vdd: sd-vdd { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_sd_vdd"; +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- +- vin-supply = <&vreg_vddpx_2>; +- }; +- +- vreg_vddpx_2: vddpx-2 { +- compatible = "regulator-gpio"; +- regulator-name = "vreg_vddpx_2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2850000>; +- enable-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; +- gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; +- states = <1800000 0>, <2850000 1>; +- startup-delay-us = <200000>; +- enable-active-high; +- regulator-boot-on; +- +- vin-supply = <&vph_pwr>; +- }; +-}; +- +-&apps_rsc { +- pmx55-rpmh-regulators { +- compatible = "qcom,pmx55-rpmh-regulators"; +- qcom,pmic-id = "e"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-l1-l2-supply = <&vreg_s2e_1p224>; +- vdd-l3-l9-supply = <&vreg_s3e_0p824>; +- vdd-l4-l12-supply = <&vreg_s4e_1p904>; +- vdd-l5-l6-supply = <&vreg_s4e_1p904>; +- vdd-l7-l8-supply = <&vreg_s3e_0p824>; +- vdd-l10-l11-l13-supply = <&vreg_bob_3p3>; +- vdd-l14-supply = <&vreg_s7e_mx_0p752>; +- vdd-l15-supply = <&vreg_s2e_1p224>; +- vdd-l16-supply = <&vreg_s4e_1p904>; +- +- vreg_s2e_1p224: smps2 { +- regulator-min-microvolt = <1280000>; +- regulator-max-microvolt = <1400000>; +- }; +- +- vreg_s3e_0p824: smps3 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- vreg_s4e_1p904: smps4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1960000>; +- }; +- +- vreg_l1e_bb_1p2: ldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- ldo2 { +- regulator-min-microvolt = <1128000>; +- regulator-max-microvolt = <1128000>; +- regulator-initial-mode = ; +- }; +- +- ldo3 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l4e_bb_0p875: ldo4 { +- regulator-min-microvolt = <872000>; +- regulator-max-microvolt = <872000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5e_bb_1p7: ldo5 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <1900000>; +- regulator-initial-mode = ; +- }; +- +- ldo6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- ldo7 { +- regulator-min-microvolt = <480000>; +- regulator-max-microvolt = <900000>; +- regulator-initial-mode = ; +- }; +- +- ldo8 { +- regulator-min-microvolt = <480000>; +- regulator-max-microvolt = <900000>; +- regulator-initial-mode = ; +- }; +- +- ldo9 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10e_3p1: ldo10 { +- regulator-min-microvolt = <3088000>; +- regulator-max-microvolt = <3088000>; +- regulator-initial-mode = ; +- }; +- +- ldo11 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- ldo12 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- ldo13 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- ldo14 { +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- ldo15 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- ldo16 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <1904000>; +- regulator-initial-mode = ; +- }; +- }; +-}; +- +-&blsp1_uart3 { +- status = "ok"; +-}; +- +-&qpic_bam { +- status = "ok"; +-}; +- +-&qpic_nand { +- status = "ok"; +- +- nand@0 { +- reg = <0>; +- +- nand-ecc-strength = <8>; +- nand-ecc-step-size = <512>; +- nand-bus-width = <8>; +- /* ico and efs2 partitions are secured */ +- secure-regions = /bits/ 64 <0x500000 0x500000 +- 0xa00000 0xb00000>; +- }; +-}; +- +-&remoteproc_mpss { +- status = "okay"; +- memory-region = <&mpss_adsp_mem>; +-}; +- +-&usb_hsphy { +- status = "okay"; +- vdda-pll-supply = <&vreg_l4e_bb_0p875>; +- vdda33-supply = <&vreg_l10e_3p1>; +- vdda18-supply = <&vreg_l5e_bb_1p7>; +-}; +- +-&usb_qmpphy { +- status = "okay"; +- vdda-phy-supply = <&vreg_l4e_bb_0p875>; +- vdda-pll-supply = <&vreg_l1e_bb_1p2>; +-}; +- +-&usb { +- status = "okay"; +-}; +- +-&usb_dwc3 { +- dr_mode = "peripheral"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/qcom-sdx55.dtsi b/scripts/dtc/include-prefixes/arm/qcom-sdx55.dtsi +deleted file mode 100644 +index b5b784c5c65e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/qcom-sdx55.dtsi ++++ /dev/null +@@ -1,708 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * SDX55 SoC device tree source +- * +- * Copyright (c) 2018, The Linux Foundation. All rights reserved. +- * Copyright (c) 2020, Linaro Ltd. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>; +- interrupt-parent = <&intc>; +- +- memory { +- device_type = "memory"; +- reg = <0 0>; +- }; +- +- clocks { +- xo_board: xo-board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <38400000>; +- clock-output-names = "xo_board"; +- }; +- +- sleep_clk: sleep-clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32000>; +- }; +- +- nand_clk_dummy: nand-clk-dummy { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32000>; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x0>; +- enable-method = "psci"; +- clocks = <&apcs>; +- power-domains = <&rpmhpd SDX55_CX>; +- power-domain-names = "rpmhpd"; +- operating-points-v2 = <&cpu_opp_table>; +- }; +- }; +- +- cpu_opp_table: cpu-opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-345600000 { +- opp-hz = /bits/ 64 <345600000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- }; +- +- opp-576000000 { +- opp-hz = /bits/ 64 <576000000>; +- required-opps = <&rpmhpd_opp_svs>; +- }; +- +- opp-1094400000 { +- opp-hz = /bits/ 64 <1094400000>; +- required-opps = <&rpmhpd_opp_nom>; +- }; +- +- opp-1555200000 { +- opp-hz = /bits/ 64 <1555200000>; +- required-opps = <&rpmhpd_opp_turbo>; +- }; +- }; +- +- firmware { +- scm { +- compatible = "qcom,scm-sdx55", "qcom,scm"; +- }; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- hyp_mem: memory@8fc00000 { +- no-map; +- reg = <0x8fc00000 0x80000>; +- }; +- +- ac_db_mem: memory@8fc80000 { +- no-map; +- reg = <0x8fc80000 0x40000>; +- }; +- +- secdata_mem: memory@8fcfd000 { +- no-map; +- reg = <0x8fcfd000 0x1000>; +- }; +- +- sbl_mem: memory@8fd00000 { +- no-map; +- reg = <0x8fd00000 0x100000>; +- }; +- +- aop_image: memory@8fe00000 { +- no-map; +- reg = <0x8fe00000 0x20000>; +- }; +- +- aop_cmd_db: memory@8fe20000 { +- compatible = "qcom,cmd-db"; +- reg = <0x8fe20000 0x20000>; +- no-map; +- }; +- +- smem_mem: memory@8fe40000 { +- no-map; +- reg = <0x8fe40000 0xc0000>; +- }; +- +- tz_mem: memory@8ff00000 { +- no-map; +- reg = <0x8ff00000 0x100000>; +- }; +- +- tz_apps_mem: memory@90000000 { +- no-map; +- reg = <0x90000000 0x500000>; +- }; +- }; +- +- smem { +- compatible = "qcom,smem"; +- memory-region = <&smem_mem>; +- hwlocks = <&tcsr_mutex 3>; +- }; +- +- smp2p-mpss { +- compatible = "qcom,smp2p"; +- qcom,smem = <435>, <428>; +- interrupts = ; +- mboxes = <&apcs 14>; +- qcom,local-pid = <0>; +- qcom,remote-pid = <1>; +- +- modem_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- modem_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- ipa_smp2p_out: ipa-ap-to-modem { +- qcom,entry-name = "ipa"; +- #qcom,smem-state-cells = <1>; +- }; +- +- ipa_smp2p_in: ipa-modem-to-ap { +- qcom,entry-name = "ipa"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- soc: soc { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "simple-bus"; +- +- gcc: clock-controller@100000 { +- compatible = "qcom,gcc-sdx55"; +- reg = <0x100000 0x1f0000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- clock-names = "bi_tcxo", "sleep_clk"; +- clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; +- }; +- +- blsp1_uart3: serial@831000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x00831000 0x200>; +- interrupts = ; +- clocks = <&gcc 30>, +- <&gcc 9>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- usb_hsphy: phy@ff4000 { +- compatible = "qcom,usb-snps-hs-7nm-phy"; +- reg = <0x00ff4000 0x114>; +- status = "disabled"; +- #phy-cells = <0>; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "ref"; +- +- resets = <&gcc GCC_QUSB2PHY_BCR>; +- }; +- +- usb_qmpphy: phy@ff6000 { +- compatible = "qcom,sdx55-qmp-usb3-uni-phy"; +- reg = <0x00ff6000 0x1c0>; +- status = "disabled"; +- #clock-cells = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, +- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, +- <&gcc GCC_USB3_PRIM_CLKREF_CLK>; +- clock-names = "aux", "cfg_ahb", "ref"; +- +- resets = <&gcc GCC_USB3PHY_PHY_BCR>, +- <&gcc GCC_USB3_PHY_BCR>; +- reset-names = "phy", "common"; +- +- usb_ssphy: phy@ff6200 { +- reg = <0x00ff6200 0x170>, +- <0x00ff6400 0x200>, +- <0x00ff6800 0x800>; +- #phy-cells = <0>; +- #clock-cells = <0>; +- clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; +- clock-names = "pipe0"; +- clock-output-names = "usb3_uni_phy_pipe_clk_src"; +- }; +- }; +- +- mc_virt: interconnect@1100000 { +- compatible = "qcom,sdx55-mc-virt"; +- reg = <0x01100000 0x400000>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- mem_noc: interconnect@9680000 { +- compatible = "qcom,sdx55-mem-noc"; +- reg = <0x09680000 0x40000>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- system_noc: interconnect@162c000 { +- compatible = "qcom,sdx55-system-noc"; +- reg = <0x0162c000 0x31200>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- ipa_virt: interconnect@1e00000 { +- compatible = "qcom,sdx55-ipa-virt"; +- reg = <0x01e00000 0x100000>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- qpic_bam: dma-controller@1b04000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0x01b04000 0x1c000>; +- interrupts = ; +- clocks = <&rpmhcc RPMH_QPIC_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- qcom,controlled-remotely; +- status = "disabled"; +- }; +- +- qpic_nand: nand-controller@1b30000 { +- compatible = "qcom,sdx55-nand"; +- reg = <0x01b30000 0x10000>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&rpmhcc RPMH_QPIC_CLK>, +- <&nand_clk_dummy>; +- clock-names = "core", "aon"; +- +- dmas = <&qpic_bam 0>, +- <&qpic_bam 1>, +- <&qpic_bam 2>; +- dma-names = "tx", "rx", "cmd"; +- status = "disabled"; +- }; +- +- ipa: ipa@1e40000 { +- compatible = "qcom,sdx55-ipa"; +- +- iommus = <&apps_smmu 0x5e0 0x0>, +- <&apps_smmu 0x5e2 0x0>; +- reg = <0x1e40000 0x7000>, +- <0x1e50000 0x4b20>, +- <0x1e04000 0x2c000>; +- reg-names = "ipa-reg", +- "ipa-shared", +- "gsi"; +- +- interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, +- <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, +- <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "ipa", +- "gsi", +- "ipa-clock-query", +- "ipa-setup-ready"; +- +- clocks = <&rpmhcc RPMH_IPA_CLK>; +- clock-names = "core"; +- +- interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI_CH0>, +- <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>, +- <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_IPA_CFG>; +- interconnect-names = "memory", +- "imem", +- "config"; +- +- qcom,smem-states = <&ipa_smp2p_out 0>, +- <&ipa_smp2p_out 1>; +- qcom,smem-state-names = "ipa-clock-enabled-valid", +- "ipa-clock-enabled"; +- +- status = "disabled"; +- }; +- +- tcsr_mutex: hwlock@1f40000 { +- compatible = "qcom,tcsr-mutex"; +- reg = <0x01f40000 0x40000>; +- #hwlock-cells = <1>; +- }; +- +- sdhc_1: sdhci@8804000 { +- compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; +- reg = <0x08804000 0x1000>; +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- clocks = <&gcc GCC_SDCC1_AHB_CLK>, +- <&gcc GCC_SDCC1_APPS_CLK>; +- clock-names = "iface", "core"; +- status = "disabled"; +- }; +- +- remoteproc_mpss: remoteproc@4080000 { +- compatible = "qcom,sdx55-mpss-pas"; +- reg = <0x04080000 0x4040>; +- +- interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", "handover", +- "stop-ack", "shutdown-ack"; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "xo"; +- +- power-domains = <&rpmhpd SDX55_CX>, +- <&rpmhpd SDX55_MSS>; +- power-domain-names = "cx", "mss"; +- +- qcom,smem-states = <&modem_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- status = "disabled"; +- +- glink-edge { +- interrupts = ; +- label = "mpss"; +- qcom,remote-pid = <1>; +- mboxes = <&apcs 15>; +- }; +- }; +- +- usb: usb@a6f8800 { +- compatible = "qcom,sdx55-dwc3", "qcom,dwc3"; +- reg = <0x0a6f8800 0x400>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, +- <&gcc GCC_USB30_MASTER_CLK>, +- <&gcc GCC_USB30_MSTR_AXI_CLK>, +- <&gcc GCC_USB30_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_SLEEP_CLK>; +- clock-names = "cfg_noc", "core", "iface", "mock_utmi", +- "sleep"; +- +- assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_MASTER_CLK>; +- assigned-clock-rates = <19200000>, <200000000>; +- +- interrupts = , +- , +- , +- ; +- interrupt-names = "hs_phy_irq", "ss_phy_irq", +- "dm_hs_phy_irq", "dp_hs_phy_irq"; +- +- power-domains = <&gcc USB30_GDSC>; +- +- resets = <&gcc GCC_USB30_BCR>; +- +- usb_dwc3: dwc3@a600000 { +- compatible = "snps,dwc3"; +- reg = <0x0a600000 0xcd00>; +- interrupts = ; +- iommus = <&apps_smmu 0x1a0 0x0>; +- snps,dis_u2_susphy_quirk; +- snps,dis_enblslpm_quirk; +- phys = <&usb_hsphy>, <&usb_ssphy>; +- phy-names = "usb2-phy", "usb3-phy"; +- }; +- }; +- +- pdc: interrupt-controller@b210000 { +- compatible = "qcom,sdx55-pdc", "qcom,pdc"; +- reg = <0x0b210000 0x30000>; +- qcom,pdc-ranges = <0 179 52>; +- #interrupt-cells = <3>; +- interrupt-parent = <&intc>; +- interrupt-controller; +- }; +- +- restart@c264000 { +- compatible = "qcom,pshold"; +- reg = <0x0c264000 0x1000>; +- }; +- +- spmi_bus: qcom,spmi@c440000 { +- compatible = "qcom,spmi-pmic-arb"; +- reg = <0x0c440000 0x0000d00>, +- <0x0c600000 0x2000000>, +- <0x0e600000 0x0100000>, +- <0x0e700000 0x00a0000>, +- <0x0c40a000 0x0000700>; +- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; +- interrupt-names = "periph_irq"; +- interrupts = ; +- qcom,ee = <0>; +- qcom,channel = <0>; +- #address-cells = <2>; +- #size-cells = <0>; +- interrupt-controller; +- #interrupt-cells = <4>; +- cell-index = <0>; +- }; +- +- tlmm: pinctrl@f100000 { +- compatible = "qcom,sdx55-pinctrl"; +- reg = <0xf100000 0x300000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- imem@1468f000 { +- compatible = "simple-mfd"; +- reg = <0x1468f000 0x1000>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0x0 0x1468f000 0x1000>; +- +- pil-reloc@94c { +- compatible = "qcom,pil-reloc-info"; +- reg = <0x94c 0x200>; +- }; +- }; +- +- apps_smmu: iommu@15000000 { +- compatible = "qcom,sdx55-smmu-500", "arm,mmu-500"; +- reg = <0x15000000 0x20000>; +- #iommu-cells = <2>; +- #global-interrupts = <1>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- }; +- +- intc: interrupt-controller@17800000 { +- compatible = "qcom,msm-qgic2"; +- interrupt-controller; +- interrupt-parent = <&intc>; +- #interrupt-cells = <3>; +- reg = <0x17800000 0x1000>, +- <0x17802000 0x1000>; +- }; +- +- a7pll: clock@17808000 { +- compatible = "qcom,sdx55-a7pll"; +- reg = <0x17808000 0x1000>; +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "bi_tcxo"; +- #clock-cells = <0>; +- }; +- +- apcs: mailbox@17810000 { +- compatible = "qcom,sdx55-apcs-gcc", "syscon"; +- reg = <0x17810000 0x2000>; +- #mbox-cells = <1>; +- clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; +- clock-names = "ref", "pll", "aux"; +- #clock-cells = <0>; +- }; +- +- watchdog@17817000 { +- compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt"; +- reg = <0x17817000 0x1000>; +- clocks = <&sleep_clk>; +- }; +- +- timer@17820000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "arm,armv7-timer-mem"; +- reg = <0x17820000 0x1000>; +- clock-frequency = <19200000>; +- +- frame@17821000 { +- frame-number = <0>; +- interrupts = , +- ; +- reg = <0x17821000 0x1000>, +- <0x17822000 0x1000>; +- }; +- +- frame@17823000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0x17823000 0x1000>; +- status = "disabled"; +- }; +- +- frame@17824000 { +- frame-number = <2>; +- interrupts = ; +- reg = <0x17824000 0x1000>; +- status = "disabled"; +- }; +- +- frame@17825000 { +- frame-number = <3>; +- interrupts = ; +- reg = <0x17825000 0x1000>; +- status = "disabled"; +- }; +- +- frame@17826000 { +- frame-number = <4>; +- interrupts = ; +- reg = <0x17826000 0x1000>; +- status = "disabled"; +- }; +- +- frame@17827000 { +- frame-number = <5>; +- interrupts = ; +- reg = <0x17827000 0x1000>; +- status = "disabled"; +- }; +- +- frame@17828000 { +- frame-number = <6>; +- interrupts = ; +- reg = <0x17828000 0x1000>; +- status = "disabled"; +- }; +- +- frame@17829000 { +- frame-number = <7>; +- interrupts = ; +- reg = <0x17829000 0x1000>; +- status = "disabled"; +- }; +- }; +- +- apps_rsc: rsc@17840000 { +- compatible = "qcom,rpmh-rsc"; +- reg = <0x17830000 0x10000>, <0x17840000 0x10000>; +- reg-names = "drv-0", "drv-1"; +- interrupts = , +- ; +- qcom,tcs-offset = <0xd00>; +- qcom,drv-id = <1>; +- qcom,tcs-config = , , +- , ; +- +- rpmhcc: clock-controller { +- compatible = "qcom,sdx55-rpmh-clk"; +- #clock-cells = <1>; +- clock-names = "xo"; +- clocks = <&xo_board>; +- }; +- +- rpmhpd: power-controller { +- compatible = "qcom,sdx55-rpmhpd"; +- #power-domain-cells = <1>; +- operating-points-v2 = <&rpmhpd_opp_table>; +- +- rpmhpd_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- rpmhpd_opp_ret: opp1 { +- opp-level = ; +- }; +- +- rpmhpd_opp_min_svs: opp2 { +- opp-level = ; +- }; +- +- rpmhpd_opp_low_svs: opp3 { +- opp-level = ; +- }; +- +- rpmhpd_opp_svs: opp4 { +- opp-level = ; +- }; +- +- rpmhpd_opp_svs_l1: opp5 { +- opp-level = ; +- }; +- +- rpmhpd_opp_nom: opp6 { +- opp-level = ; +- }; +- +- rpmhpd_opp_nom_l1: opp7 { +- opp-level = ; +- }; +- +- rpmhpd_opp_nom_l2: opp8 { +- opp-level = ; +- }; +- +- rpmhpd_opp_turbo: opp9 { +- opp-level = ; +- }; +- +- rpmhpd_opp_turbo_l1: opp10 { +- opp-level = ; +- }; +- }; +- }; +- +- apps_bcm_voter: bcm_voter { +- compatible = "qcom,bcm-voter"; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- clock-frequency = <19200000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r7s72100-genmai.dts b/scripts/dtc/include-prefixes/arm/r7s72100-genmai.dts +deleted file mode 100644 +index 07d611d2b7b5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r7s72100-genmai.dts ++++ /dev/null +@@ -1,148 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Genmai board +- * +- * Copyright (C) 2013-14 Renesas Solutions Corp. +- * Copyright (C) 2014 Wolfram Sang, Sang Engineering +- */ +- +-/dts-v1/; +-#include "r7s72100.dtsi" +-#include +-#include +- +-/ { +- model = "Genmai"; +- compatible = "renesas,genmai", "renesas,r7s72100"; +- +- aliases { +- serial0 = &scif2; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@8000000 { +- device_type = "memory"; +- reg = <0x08000000 0x08000000>; +- }; +- +- lbsc { +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- leds { +- status = "okay"; +- compatible = "gpio-leds"; +- +- led1 { +- gpios = <&port4 10 GPIO_ACTIVE_LOW>; +- }; +- +- led2 { +- gpios = <&port4 11 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&pinctrl { +- +- scif2_pins: serial2 { +- /* P3_0 as TxD2; P3_2 as RxD2 */ +- pinmux = , ; +- }; +- +- i2c2_pins: i2c2 { +- /* RIIC2: P1_4 as SCL, P1_5 as SDA */ +- pinmux = , ; +- }; +- +- ether_pins: ether { +- /* Ethernet on Ports 1,2,3,5 */ +- pinmux = ,/* P1_14 = ET_COL */ +- , /* P5_9 = ET_MDC */ +- , /* P3_3 = ET_MDIO */ +- , /* P3_4 = ET_RXCLK */ +- , /* P3_5 = ET_RXER */ +- , /* P3_6 = ET_RXDV */ +- , /* P2_0 = ET_TXCLK */ +- , /* P2_1 = ET_TXER */ +- , /* P2_2 = ET_TXEN */ +- , /* P2_3 = ET_CRS */ +- , /* P2_4 = ET_TXD0 */ +- , /* P2_5 = ET_TXD1 */ +- , /* P2_6 = ET_TXD2 */ +- , /* P2_7 = ET_TXD3 */ +- , /* P2_8 = ET_RXD0 */ +- , /* P2_9 = ET_RXD1 */ +- ,/* P2_10 = ET_RXD2 */ +- ;/* P2_11 = ET_RXD3 */ +- }; +-}; +- +-&extal_clk { +- clock-frequency = <13330000>; +-}; +- +-&usb_x1_clk { +- clock-frequency = <48000000>; +-}; +- +-&rtc_x1_clk { +- clock-frequency = <32768>; +-}; +- +-&mtu2 { +- status = "okay"; +-}; +- +-ðer { +- pinctrl-names = "default"; +- pinctrl-0 = <ðer_pins>; +- +- status = "okay"; +- +- renesas,no-ether-link; +- phy-handle = <&phy0>; +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- clock-frequency = <400000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- +- eeprom@50 { +- compatible = "renesas,r1ex24128", "atmel,24c128"; +- reg = <0x50>; +- pagesize = <64>; +- }; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&scif2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&scif2_pins>; +- +- status = "okay"; +-}; +- +-&spi4 { +- status = "okay"; +- +- codec: codec@0 { +- compatible = "wlf,wm8978"; +- reg = <0>; +- spi-max-frequency = <5000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r7s72100-gr-peach.dts b/scripts/dtc/include-prefixes/arm/r7s72100-gr-peach.dts +deleted file mode 100644 +index 2562cc9b5356..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r7s72100-gr-peach.dts ++++ /dev/null +@@ -1,137 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the GR-Peach board +- * +- * Copyright (C) 2017 Jacopo Mondi +- * Copyright (C) 2016 Renesas Electronics +- */ +- +-/dts-v1/; +-#include "r7s72100.dtsi" +-#include +-#include +- +-/ { +- model = "GR-Peach"; +- compatible = "renesas,gr-peach", "renesas,r7s72100"; +- +- aliases { +- serial0 = &scif2; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/mtdblock0"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x00a00000>; +- }; +- +- lbsc { +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- flash@18000000 { +- compatible = "mtd-rom"; +- probe-type = "map_rom"; +- reg = <0x18000000 0x00800000>; +- bank-width = <4>; +- device-width = <1>; +- +- clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>; +- power-domains = <&cpg_clocks>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- rootfs@600000 { +- label = "rootfs"; +- reg = <0x00600000 0x00200000>; +- }; +- }; +- +- leds { +- status = "okay"; +- compatible = "gpio-leds"; +- +- led1 { +- gpios = <&port6 12 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&pinctrl { +- scif2_pins: serial2 { +- /* P6_2 as RxD2; P6_3 as TxD2 */ +- pinmux = , ; +- }; +- +- ether_pins: ether { +- /* Ethernet on Ports 1,3,5,10 */ +- pinmux = , /* P1_14 = ET_COL */ +- , /* P3_0 = ET_TXCLK */ +- , /* P3_3 = ET_MDIO */ +- , /* P3_4 = ET_RXCLK */ +- , /* P3_5 = ET_RXER */ +- , /* P3_6 = ET_RXDV */ +- , /* P5_9 = ET_MDC */ +- , /* P10_1 = ET_TXER */ +- , /* P10_2 = ET_TXEN */ +- , /* P10_3 = ET_CRS */ +- , /* P10_4 = ET_TXD0 */ +- , /* P10_5 = ET_TXD1 */ +- , /* P10_6 = ET_TXD2 */ +- , /* P10_7 = ET_TXD3 */ +- , /* P10_8 = ET_RXD0 */ +- , /* P10_9 = ET_RXD1 */ +- ,/* P10_10 = ET_RXD2 */ +- ;/* P10_11 = ET_RXD3 */ +- }; +-}; +- +-&extal_clk { +- clock-frequency = <13333000>; +-}; +- +-&usb_x1_clk { +- clock-frequency = <48000000>; +-}; +- +-&mtu2 { +- status = "okay"; +-}; +- +-&ostm0 { +- status = "okay"; +-}; +- +-&ostm1 { +- status = "okay"; +-}; +- +-&scif2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&scif2_pins>; +- +- status = "okay"; +-}; +- +-ðer { +- pinctrl-names = "default"; +- pinctrl-0 = <ðer_pins>; +- +- status = "okay"; +- +- renesas,no-ether-link; +- phy-handle = <&phy0>; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- +- reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>; +- reset-delay-us = <5>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r7s72100-rskrza1.dts b/scripts/dtc/include-prefixes/arm/r7s72100-rskrza1.dts +deleted file mode 100644 +index 99acfe4fe11a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r7s72100-rskrza1.dts ++++ /dev/null +@@ -1,222 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the RZ/A1H RSK board +- * +- * Copyright (C) 2016 Renesas Electronics +- */ +- +-/dts-v1/; +-#include "r7s72100.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "RSKRZA1"; +- compatible = "renesas,rskrza1", "renesas,r7s72100"; +- +- aliases { +- serial0 = &scif2; +- }; +- +- chosen { +- bootargs = "ignore_loglevel"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@8000000 { +- device_type = "memory"; +- reg = <0x08000000 0x02000000>; +- }; +- +- keyboard { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&keyboard_pins>; +- +- key-1 { +- interrupt-parent = <&irqc>; +- interrupts = <3 IRQ_TYPE_EDGE_BOTH>; +- linux,code = ; +- label = "SW1"; +- wakeup-source; +- }; +- +- key-2 { +- interrupt-parent = <&irqc>; +- interrupts = <2 IRQ_TYPE_EDGE_BOTH>; +- linux,code = ; +- label = "SW2"; +- wakeup-source; +- }; +- +- key-3 { +- interrupt-parent = <&irqc>; +- interrupts = <5 IRQ_TYPE_EDGE_BOTH>; +- linux,code = ; +- label = "SW3"; +- wakeup-source; +- }; +- }; +- +- lbsc { +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led0 { +- gpios = <&port7 1 GPIO_ACTIVE_LOW>; +- }; +- +- led1 { +- gpios = <&io_expander1 0 GPIO_ACTIVE_LOW>; +- }; +- +- led2 { +- gpios = <&io_expander1 1 GPIO_ACTIVE_LOW>; +- }; +- +- led3 { +- gpios = <&io_expander1 2 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&extal_clk { +- clock-frequency = <13330000>; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- status = "okay"; +- +- clock-frequency = <400000>; +- +- io_expander1: gpio@20 { +- compatible = "onnn,cat9554"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- io_expander2: gpio@21 { +- compatible = "onnn,cat9554"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- eeprom@50 { +- compatible = "renesas,r1ex24016", "atmel,24c16"; +- reg = <0x50>; +- pagesize = <16>; +- }; +-}; +- +-&usb_x1_clk { +- clock-frequency = <48000000>; +-}; +- +-&rtc_x1_clk { +- clock-frequency = <32768>; +-}; +- +-&pinctrl { +- /* RIIC ch3 (Port Expander, EEPROM (MAC Addr), Audio Codec) */ +- i2c3_pins: i2c3 { +- pinmux = , /* RIIC3SCL */ +- ; /* RIIC3SDA */ +- }; +- +- keyboard_pins: keyboard { +- pinmux = , /* IRQ3 */ +- , /* IRQ2 */ +- ; /* IRQ5 */ +- }; +- +- /* Serial Console */ +- scif2_pins: serial2 { +- pinmux = , /* TxD2 */ +- ; /* RxD2 */ +- }; +- +- /* Ethernet */ +- ether_pins: ether { +- /* Ethernet on Ports 1,2,3,5 */ +- pinmux = , /* ET_COL */ +- , /* ET_MDC */ +- , /* ET_MDIO */ +- , /* ET_RXCLK */ +- , /* ET_RXER */ +- , /* ET_RXDV */ +- , /* ET_TXCLK */ +- , /* ET_TXER */ +- , /* ET_TXEN */ +- , /* ET_CRS */ +- , /* ET_TXD0 */ +- , /* ET_TXD1 */ +- , /* ET_TXD2 */ +- , /* ET_TXD3 */ +- , /* ET_RXD0 */ +- , /* ET_RXD1 */ +- , /* ET_RXD2 */ +- ; /* ET_RXD3 */ +- }; +- +- /* SDHI ch1 on CN1 */ +- sdhi1_pins: sdhi1 { +- pinmux = , /* SD_CD_1 */ +- , /* SD_WP_1 */ +- , /* SD_D1_1 */ +- , /* SD_D0_1 */ +- , /* SD_CLK_1 */ +- , /* SD_CMD_1 */ +- , /* SD_D3_1 */ +- ; /* SD_D2_1 */ +- }; +-}; +- +-&mtu2 { +- status = "okay"; +-}; +- +-ðer { +- pinctrl-names = "default"; +- pinctrl-0 = <ðer_pins>; +- status = "okay"; +- renesas,no-ether-link; +- phy-handle = <&phy0>; +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&sdhi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhi1_pins>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&ostm0 { +- status = "okay"; +-}; +- +-&ostm1 { +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&scif2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&scif2_pins>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r7s72100.dtsi b/scripts/dtc/include-prefixes/arm/r7s72100.dtsi +deleted file mode 100644 +index b07b71307f24..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r7s72100.dtsi ++++ /dev/null +@@ -1,733 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the r7s72100 SoC +- * +- * Copyright (C) 2013-14 Renesas Solutions Corp. +- * Copyright (C) 2014 Wolfram Sang, Sang Engineering +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r7s72100"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- spi0 = &spi0; +- spi1 = &spi1; +- spi2 = &spi2; +- spi3 = &spi3; +- spi4 = &spi4; +- }; +- +- /* Fixed factor clocks */ +- b_clk: b { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks R7S72100_CLK_PLL>; +- clock-mult = <1>; +- clock-div = <3>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- clock-frequency = <400000000>; +- clocks = <&cpg_clocks R7S72100_CLK_I>; +- next-level-cache = <&L2>; +- }; +- }; +- +- /* External clocks */ +- extal_clk: extal { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- /* If clk present, value must be set by board */ +- clock-frequency = <0>; +- }; +- +- p0_clk: p0 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks R7S72100_CLK_PLL>; +- clock-mult = <1>; +- clock-div = <12>; +- }; +- +- p1_clk: p1 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks R7S72100_CLK_PLL>; +- clock-mult = <1>; +- clock-div = <6>; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- rtc_x1_clk: rtc_x1 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- /* If clk present, value must be set by board to 32678 */ +- clock-frequency = <0>; +- }; +- +- rtc_x3_clk: rtc_x3 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- /* If clk present, value must be set by board to 4000000 */ +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- L2: cache-controller@3ffff000 { +- compatible = "arm,pl310-cache"; +- reg = <0x3ffff000 0x1000>; +- interrupts = ; +- arm,early-bresp-disable; +- arm,full-line-zero-disable; +- cache-unified; +- cache-level = <2>; +- }; +- +- scif0: serial@e8007000 { +- compatible = "renesas,scif-r7s72100", "renesas,scif"; +- reg = <0xe8007000 64>; +- interrupts = , +- , +- , +- ; +- clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; +- clock-names = "fck"; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- scif1: serial@e8007800 { +- compatible = "renesas,scif-r7s72100", "renesas,scif"; +- reg = <0xe8007800 64>; +- interrupts = , +- , +- , +- ; +- clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; +- clock-names = "fck"; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- scif2: serial@e8008000 { +- compatible = "renesas,scif-r7s72100", "renesas,scif"; +- reg = <0xe8008000 64>; +- interrupts = , +- , +- , +- ; +- clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; +- clock-names = "fck"; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- scif3: serial@e8008800 { +- compatible = "renesas,scif-r7s72100", "renesas,scif"; +- reg = <0xe8008800 64>; +- interrupts = , +- , +- , +- ; +- clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; +- clock-names = "fck"; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- scif4: serial@e8009000 { +- compatible = "renesas,scif-r7s72100", "renesas,scif"; +- reg = <0xe8009000 64>; +- interrupts = , +- , +- , +- ; +- clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; +- clock-names = "fck"; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- scif5: serial@e8009800 { +- compatible = "renesas,scif-r7s72100", "renesas,scif"; +- reg = <0xe8009800 64>; +- interrupts = , +- , +- , +- ; +- clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; +- clock-names = "fck"; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- scif6: serial@e800a000 { +- compatible = "renesas,scif-r7s72100", "renesas,scif"; +- reg = <0xe800a000 64>; +- interrupts = , +- , +- , +- ; +- clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; +- clock-names = "fck"; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- scif7: serial@e800a800 { +- compatible = "renesas,scif-r7s72100", "renesas,scif"; +- reg = <0xe800a800 64>; +- interrupts = , +- , +- , +- ; +- clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; +- clock-names = "fck"; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- spi0: spi@e800c800 { +- compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; +- reg = <0xe800c800 0x24>; +- interrupts = , +- , +- ; +- interrupt-names = "error", "rx", "tx"; +- clocks = <&mstp10_clks R7S72100_CLK_SPI0>; +- power-domains = <&cpg_clocks>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi1: spi@e800d000 { +- compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; +- reg = <0xe800d000 0x24>; +- interrupts = , +- , +- ; +- interrupt-names = "error", "rx", "tx"; +- clocks = <&mstp10_clks R7S72100_CLK_SPI1>; +- power-domains = <&cpg_clocks>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi2: spi@e800d800 { +- compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; +- reg = <0xe800d800 0x24>; +- interrupts = , +- , +- ; +- interrupt-names = "error", "rx", "tx"; +- clocks = <&mstp10_clks R7S72100_CLK_SPI2>; +- power-domains = <&cpg_clocks>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi3: spi@e800e000 { +- compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; +- reg = <0xe800e000 0x24>; +- interrupts = , +- , +- ; +- interrupt-names = "error", "rx", "tx"; +- clocks = <&mstp10_clks R7S72100_CLK_SPI3>; +- power-domains = <&cpg_clocks>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi4: spi@e800e800 { +- compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; +- reg = <0xe800e800 0x24>; +- interrupts = , +- , +- ; +- interrupt-names = "error", "rx", "tx"; +- clocks = <&mstp10_clks R7S72100_CLK_SPI4>; +- power-domains = <&cpg_clocks>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- usbhs0: usb@e8010000 { +- compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; +- reg = <0xe8010000 0x1a0>; +- interrupts = ; +- clocks = <&mstp7_clks R7S72100_CLK_USB0>; +- renesas,buswait = <4>; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- usbhs1: usb@e8207000 { +- compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; +- reg = <0xe8207000 0x1a0>; +- interrupts = ; +- clocks = <&mstp7_clks R7S72100_CLK_USB1>; +- renesas,buswait = <4>; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- mmcif: mmc@e804c800 { +- compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif"; +- reg = <0xe804c800 0x80>; +- interrupts = , +- , +- ; +- clocks = <&mstp8_clks R7S72100_CLK_MMCIF>; +- power-domains = <&cpg_clocks>; +- reg-io-width = <4>; +- bus-width = <8>; +- status = "disabled"; +- }; +- +- sdhi0: mmc@e804e000 { +- compatible = "renesas,sdhi-r7s72100"; +- reg = <0xe804e000 0x100>; +- interrupts = , +- , +- ; +- +- clocks = <&mstp12_clks R7S72100_CLK_SDHI00>, +- <&mstp12_clks R7S72100_CLK_SDHI01>; +- clock-names = "core", "cd"; +- power-domains = <&cpg_clocks>; +- cap-sd-highspeed; +- cap-sdio-irq; +- status = "disabled"; +- }; +- +- sdhi1: mmc@e804e800 { +- compatible = "renesas,sdhi-r7s72100"; +- reg = <0xe804e800 0x100>; +- interrupts = , +- , +- ; +- +- clocks = <&mstp12_clks R7S72100_CLK_SDHI10>, +- <&mstp12_clks R7S72100_CLK_SDHI11>; +- clock-names = "core", "cd"; +- power-domains = <&cpg_clocks>; +- cap-sd-highspeed; +- cap-sdio-irq; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@e8201000 { +- compatible = "arm,pl390"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0xe8201000 0x1000>, +- <0xe8202000 0x1000>; +- }; +- +- ether: ethernet@e8203000 { +- compatible = "renesas,ether-r7s72100"; +- reg = <0xe8203000 0x800>, +- <0xe8204800 0x200>; +- interrupts = ; +- clocks = <&mstp7_clks R7S72100_CLK_ETHER>; +- power-domains = <&cpg_clocks>; +- phy-mode = "mii"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- ceu: camera@e8210000 { +- reg = <0xe8210000 0x3000>; +- compatible = "renesas,r7s72100-ceu"; +- interrupts = ; +- clocks = <&mstp6_clks R7S72100_CLK_CEU>; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- wdt: watchdog@fcfe0000 { +- compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt"; +- reg = <0xfcfe0000 0x6>; +- interrupts = ; +- clocks = <&p0_clk>; +- }; +- +- /* Special CPG clocks */ +- cpg_clocks: cpg_clocks@fcfe0000 { +- #clock-cells = <1>; +- compatible = "renesas,r7s72100-cpg-clocks", +- "renesas,rz-cpg-clocks"; +- reg = <0xfcfe0000 0x18>; +- clocks = <&extal_clk>, <&usb_x1_clk>; +- clock-output-names = "pll", "i", "g"; +- #power-domain-cells = <0>; +- }; +- +- /* MSTP clocks */ +- mstp3_clks: mstp3_clks@fcfe0420 { +- #clock-cells = <1>; +- compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xfcfe0420 4>; +- clocks = <&p0_clk>; +- clock-indices = ; +- clock-output-names = "mtu2"; +- }; +- +- mstp4_clks: mstp4_clks@fcfe0424 { +- #clock-cells = <1>; +- compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xfcfe0424 4>; +- clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, +- <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; +- clock-indices = < +- R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3 +- R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7 +- >; +- clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; +- }; +- +- mstp5_clks: mstp5_clks@fcfe0428 { +- #clock-cells = <1>; +- compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xfcfe0428 4>; +- clocks = <&p0_clk>, <&p0_clk>; +- clock-indices = ; +- clock-output-names = "ostm0", "ostm1"; +- }; +- +- mstp6_clks: mstp6_clks@fcfe042c { +- #clock-cells = <1>; +- compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xfcfe042c 4>; +- clocks = <&b_clk>, <&p0_clk>; +- clock-indices = ; +- clock-output-names = "ceu", "rtc"; +- }; +- +- mstp7_clks: mstp7_clks@fcfe0430 { +- #clock-cells = <1>; +- compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xfcfe0430 4>; +- clocks = <&b_clk>, <&p1_clk>, <&p1_clk>; +- clock-indices = ; +- clock-output-names = "ether", "usb0", "usb1"; +- }; +- +- mstp8_clks: mstp8_clks@fcfe0434 { +- #clock-cells = <1>; +- compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xfcfe0434 4>; +- clocks = <&p1_clk>; +- clock-indices = ; +- clock-output-names = "mmcif"; +- }; +- +- mstp9_clks: mstp9_clks@fcfe0438 { +- #clock-cells = <1>; +- compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xfcfe0438 4>; +- clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>; +- clock-indices = < +- R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3 +- R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1 +- >; +- clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1"; +- }; +- +- mstp10_clks: mstp10_clks@fcfe043c { +- #clock-cells = <1>; +- compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xfcfe043c 4>; +- clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, +- <&p1_clk>; +- clock-indices = < +- R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3 +- R7S72100_CLK_SPI4 +- >; +- clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4"; +- }; +- mstp12_clks: mstp12_clks@fcfe0444 { +- #clock-cells = <1>; +- compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xfcfe0444 4>; +- clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; +- clock-indices = < +- R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01 +- R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11 +- >; +- clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; +- }; +- +- pinctrl: pinctrl@fcfe3000 { +- compatible = "renesas,r7s72100-ports"; +- +- reg = <0xfcfe3000 0x4230>; +- +- port0: gpio-0 { +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 0 6>; +- }; +- +- port1: gpio-1 { +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 16 16>; +- }; +- +- port2: gpio-2 { +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 32 16>; +- }; +- +- port3: gpio-3 { +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 48 16>; +- }; +- +- port4: gpio-4 { +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 64 16>; +- }; +- +- port5: gpio-5 { +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 80 11>; +- }; +- +- port6: gpio-6 { +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 96 16>; +- }; +- +- port7: gpio-7 { +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 112 16>; +- }; +- +- port8: gpio-8 { +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 128 16>; +- }; +- +- port9: gpio-9 { +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 144 8>; +- }; +- +- port10: gpio-10 { +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 160 16>; +- }; +- +- port11: gpio-11 { +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 176 16>; +- }; +- }; +- +- ostm0: timer@fcfec000 { +- compatible = "renesas,r7s72100-ostm", "renesas,ostm"; +- reg = <0xfcfec000 0x30>; +- interrupts = ; +- clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- ostm1: timer@fcfec400 { +- compatible = "renesas,r7s72100-ostm", "renesas,ostm"; +- reg = <0xfcfec400 0x30>; +- interrupts = ; +- clocks = <&mstp5_clks R7S72100_CLK_OSTM1>; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- i2c0: i2c@fcfee000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; +- reg = <0xfcfee000 0x44>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "tei", "ri", "ti", "spi", "sti", +- "naki", "ali", "tmoi"; +- clocks = <&mstp9_clks R7S72100_CLK_I2C0>; +- clock-frequency = <100000>; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- i2c1: i2c@fcfee400 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; +- reg = <0xfcfee400 0x44>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "tei", "ri", "ti", "spi", "sti", +- "naki", "ali", "tmoi"; +- clocks = <&mstp9_clks R7S72100_CLK_I2C1>; +- clock-frequency = <100000>; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- i2c2: i2c@fcfee800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; +- reg = <0xfcfee800 0x44>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "tei", "ri", "ti", "spi", "sti", +- "naki", "ali", "tmoi"; +- clocks = <&mstp9_clks R7S72100_CLK_I2C2>; +- clock-frequency = <100000>; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- i2c3: i2c@fcfeec00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; +- reg = <0xfcfeec00 0x44>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "tei", "ri", "ti", "spi", "sti", +- "naki", "ali", "tmoi"; +- clocks = <&mstp9_clks R7S72100_CLK_I2C3>; +- clock-frequency = <100000>; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- irqc: interrupt-controller@fcfef800 { +- compatible = "renesas,r7s72100-irqc", +- "renesas,rza1-irqc"; +- #interrupt-cells = <2>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0xfcfef800 0x6>; +- interrupt-map = +- <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, +- <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, +- <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, +- <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, +- <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, +- <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, +- <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, +- <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-map-mask = <7 0>; +- }; +- +- mtu2: timer@fcff0000 { +- compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; +- reg = <0xfcff0000 0x400>; +- interrupts = ; +- interrupt-names = "tgi0a"; +- clocks = <&mstp3_clks R7S72100_CLK_MTU2>; +- clock-names = "fck"; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- rtc: rtc@fcff1000 { +- compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; +- reg = <0xfcff1000 0x2e>; +- interrupts = , +- , +- ; +- interrupt-names = "alarm", "period", "carry"; +- clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, +- <&rtc_x3_clk>, <&extal_clk>; +- clock-names = "fck", "rtc_x1", "rtc_x3", "extal"; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- }; +- +- usb_x1_clk: usb_x1 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- /* If clk present, value must be set by board */ +- clock-frequency = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r7s9210-rza2mevb.dts b/scripts/dtc/include-prefixes/arm/r7s9210-rza2mevb.dts +deleted file mode 100644 +index 68498ce2aec0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r7s9210-rza2mevb.dts ++++ /dev/null +@@ -1,228 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the RZA2MEVB board +- * +- * Copyright (C) 2018 Renesas Electronics +- * +- * As upstream Linux does not support XIP, it cannot run in 8 MiB of HyperRAM. +- * Hence the 64 MiB of SDRAM on the sub-board needs to be enabled, which has +- * the following ramifications: +- * - SCIF4 connected to the on-board USB-serial can no longer be used as the +- * serial console, +- * - Instead, SCIF2 is used as the serial console, by connecting a 3.3V TTL +- * USB-to-Serial adapter to the CMOS camera connector: +- * - RXD = CN17-9, +- * - TXD = CN17-10, +- * - GND = CN17-2 or CN17-17, +- * - The first Ethernet channel can no longer be used, +- * - USB Channel 1 loses the overcurrent input signal. +- * +- * Please make sure your sub-board matches the following switch settings: +- * +- * SW6 SW6-1 set to SDRAM +- * ON SW6-2 set to Audio +- * +---------------------+ SW6-3 set to DRP +- * | = = = = = | SW6-4 set to CEU +- * | = = | SW6-5 set to Ether2 +- * | 1 2 3 4 5 6 7 8 9 0 | SW6-6 set to VDC6 +- * +---------------------+ SW6-7 set to VDC6 +- */ +- +-/dts-v1/; +-#include "r7s9210.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "RZA2MEVB"; +- compatible = "renesas,rza2mevb", "renesas,r7s9210"; +- +- aliases { +- serial0 = &scif2; +- ethernet0 = ðer1; +- }; +- +- chosen { +- bootargs = "ignore_loglevel"; +- stdout-path = "serial0:115200n8"; +- }; +- +- keyboard { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&keyboard_pins>; +- +- key-3 { +- interrupt-parent = <&irqc>; +- interrupts = <0 IRQ_TYPE_EDGE_BOTH>; +- linux,code = ; +- label = "SW3"; +- wakeup-source; +- }; +- }; +- +- lbsc { +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- red { +- gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>; +- }; +- green { +- gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- memory@c000000 { +- device_type = "memory"; +- reg = <0x0c000000 0x04000000>; /* SDRAM */ +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-ðer1 { +- pinctrl-names = "default"; +- pinctrl-0 = <ð1_pins>; +- status = "okay"; +- renesas,no-ether-link; +- phy-handle = <&phy1>; +- phy1: ethernet-phy@1 { +- reg = <0>; +- }; +-}; +- +-/* EXTAL */ +-&extal_clk { +- clock-frequency = <24000000>; /* 24MHz */ +-}; +- +-/* High resolution System tick timers */ +-&ostm0 { +- status = "okay"; +-}; +- +-&ostm1 { +- status = "okay"; +-}; +- +-&pinctrl { +- eth0_pins: eth0 { +- pinmux = , /* REF50CK0 */ +- , /* RMMI0_TXDEN */ +- , /* RMII0_TXD0 */ +- , /* RMII0_TXD1 */ +- , /* RMII0_CRSDV */ +- , /* RMII0_RXD0 */ +- , /* RMII0_RXD1 */ +- , /* RMII0_RXER */ +- , /* ET0_MDC */ +- , /* ET0_MDIO */ +- ; /* IRQ4 */ +- }; +- +- eth1_pins: eth1 { +- pinmux = , /* REF50CK1 */ +- , /* RMMI1_TXDEN */ +- , /* RMII1_TXD0 */ +- , /* RMII1_TXD1 */ +- , /* RMII1_CRSDV */ +- , /* RMII1_RXD0 */ +- , /* RMII1_RXD1 */ +- , /* RMII1_RXER */ +- , /* ET1_MDC */ +- , /* ET1_MDIO */ +- ; /* IRQ5 */ +- }; +- +- keyboard_pins: keyboard { +- pinmux = ; /* IRQ0 */ +- }; +- +- /* Serial Console */ +- scif2_pins: serial2 { +- pinmux = , /* TxD2 */ +- ; /* RxD2 */ +- }; +- +- sdhi0_pins: sdhi0 { +- pinmux = , /* SD0_CD */ +- ; /* SD0_WP */ +- }; +- +- sdhi1_pins: sdhi1 { +- pinmux = , /* SD1_CD */ +- ; /* SD1_WP */ +- }; +- +- usb0_pins: usb0 { +- pinmux = , /* VBUSIN0 */ +- , /* VBUSEN0 */ +- ; /* OVRCUR0 */ +- }; +- +- usb1_pins: usb1 { +- pinmux = , /* VBUSIN1 */ +- ; /* VBUSEN1 */ +- }; +-}; +- +-/* RTC_X1 */ +-&rtc_x1_clk { +- clock-frequency = <32768>; +-}; +- +-/* Serial Console */ +-&scif2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&scif2_pins>; +- +- status = "okay"; +-}; +- +-&sdhi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhi0_pins>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&sdhi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhi1_pins>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-/* USB-0 as Host */ +-&usb2_phy0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb0_pins>; +- dr_mode = "host"; /* Requires JP3 to be fitted */ +- status = "okay"; +-}; +- +-/* USB-1 as Host */ +-&usb2_phy1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb1_pins>; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-/* USB_X1 */ +-&usb_x1_clk { +- clock-frequency = <48000000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r7s9210.dtsi b/scripts/dtc/include-prefixes/arm/r7s9210.dtsi +deleted file mode 100644 +index fdeb0bc12cb7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r7s9210.dtsi ++++ /dev/null +@@ -1,509 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R7S9210 SoC +- * +- * Copyright (C) 2018 Renesas Electronics Corporation +- * +- */ +- +-#include +-#include +- +-/ { +- compatible = "renesas,r7s9210"; +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* External clocks */ +- extal_clk: extal { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- /* Value must be set by board */ +- clock-frequency = <0>; +- }; +- +- rtc_x1_clk: rtc_x1 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- /* If clk present, value (32678) must be set by board */ +- clock-frequency = <0>; +- }; +- +- usb_x1_clk: usb_x1 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- /* If clk present, value (48000000) must be set by board */ +- clock-frequency = <0>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- clock-frequency = <528000000>; +- next-level-cache = <&L2>; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- L2: cache-controller@1f003000 { +- compatible = "arm,pl310-cache"; +- reg = <0x1f003000 0x1000>; +- interrupts = ; +- arm,early-bresp-disable; +- arm,full-line-zero-disable; +- cache-unified; +- cache-level = <2>; +- }; +- +- scif0: serial@e8007000 { +- compatible = "renesas,scif-r7s9210"; +- reg = <0xe8007000 0x18>; +- interrupts = , +- , +- , +- , +- , +- ; +- interrupt-names = "eri", "rxi", "txi", +- "bri", "dri", "tei"; +- clocks = <&cpg CPG_MOD 47>; +- clock-names = "fck"; +- power-domains = <&cpg>; +- status = "disabled"; +- }; +- +- scif1: serial@e8007800 { +- compatible = "renesas,scif-r7s9210"; +- reg = <0xe8007800 0x18>; +- interrupts = , +- , +- , +- , +- , +- ; +- interrupt-names = "eri", "rxi", "txi", +- "bri", "dri", "tei"; +- clocks = <&cpg CPG_MOD 46>; +- clock-names = "fck"; +- power-domains = <&cpg>; +- status = "disabled"; +- }; +- +- scif2: serial@e8008000 { +- compatible = "renesas,scif-r7s9210"; +- reg = <0xe8008000 0x18>; +- interrupts = , +- , +- , +- , +- , +- ; +- interrupt-names = "eri", "rxi", "txi", +- "bri", "dri", "tei"; +- clocks = <&cpg CPG_MOD 45>; +- clock-names = "fck"; +- power-domains = <&cpg>; +- status = "disabled"; +- }; +- +- scif3: serial@e8008800 { +- compatible = "renesas,scif-r7s9210"; +- reg = <0xe8008800 0x18>; +- interrupts = , +- , +- , +- , +- , +- ; +- interrupt-names = "eri", "rxi", "txi", +- "bri", "dri", "tei"; +- clocks = <&cpg CPG_MOD 44>; +- clock-names = "fck"; +- power-domains = <&cpg>; +- status = "disabled"; +- }; +- +- scif4: serial@e8009000 { +- compatible = "renesas,scif-r7s9210"; +- reg = <0xe8009000 0x18>; +- interrupts = , +- , +- , +- , +- , +- ; +- interrupt-names = "eri", "rxi", "txi", +- "bri", "dri", "tei"; +- clocks = <&cpg CPG_MOD 43>; +- clock-names = "fck"; +- power-domains = <&cpg>; +- status = "disabled"; +- }; +- +- spi0: spi@e800c800 { +- compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz"; +- reg = <0xe800c800 0x24>; +- interrupts = , +- , +- ; +- interrupt-names = "error", "rx", "tx"; +- clocks = <&cpg CPG_MOD 97>; +- power-domains = <&cpg>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi1: spi@e800d000 { +- compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz"; +- reg = <0xe800d000 0x24>; +- interrupts = , +- , +- ; +- interrupt-names = "error", "rx", "tx"; +- clocks = <&cpg CPG_MOD 96>; +- power-domains = <&cpg>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi2: spi@e800d800 { +- compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz"; +- reg = <0xe800d800 0x24>; +- interrupts = , +- , +- ; +- interrupt-names = "error", "rx", "tx"; +- clocks = <&cpg CPG_MOD 95>; +- power-domains = <&cpg>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- ether0: ethernet@e8204000 { +- compatible = "renesas,ether-r7s9210"; +- reg = <0xe8204000 0x200>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 65>; +- power-domains = <&cpg>; +- +- phy-mode = "rmii"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- ether1: ethernet@e8204200 { +- compatible = "renesas,ether-r7s9210"; +- reg = <0xe8204200 0x200>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 64>; +- power-domains = <&cpg>; +- phy-mode = "rmii"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c0: i2c@e803a000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; +- reg = <0xe803a000 0x44>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "tei", "ri", "ti", "spi", "sti", +- "naki", "ali", "tmoi"; +- clocks = <&cpg CPG_MOD 87>; +- power-domains = <&cpg>; +- clock-frequency = <100000>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e803a400 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; +- reg = <0xe803a400 0x44>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "tei", "ri", "ti", "spi", "sti", +- "naki", "ali", "tmoi"; +- clocks = <&cpg CPG_MOD 86>; +- power-domains = <&cpg>; +- clock-frequency = <100000>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e803a800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; +- reg = <0xe803a800 0x44>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "tei", "ri", "ti", "spi", "sti", +- "naki", "ali", "tmoi"; +- clocks = <&cpg CPG_MOD 85>; +- power-domains = <&cpg>; +- clock-frequency = <100000>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e803ac00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; +- reg = <0xe803ac00 0x44>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "tei", "ri", "ti", "spi", "sti", +- "naki", "ali", "tmoi"; +- clocks = <&cpg CPG_MOD 84>; +- power-domains = <&cpg>; +- clock-frequency = <100000>; +- status = "disabled"; +- }; +- +- ostm0: timer@e803b000 { +- compatible = "renesas,r7s9210-ostm", "renesas,ostm"; +- reg = <0xe803b000 0x30>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 36>; +- power-domains = <&cpg>; +- status = "disabled"; +- }; +- +- ostm1: timer@e803c000 { +- compatible = "renesas,r7s9210-ostm", "renesas,ostm"; +- reg = <0xe803c000 0x30>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 35>; +- power-domains = <&cpg>; +- status = "disabled"; +- }; +- +- ostm2: timer@e803d000 { +- compatible = "renesas,r7s9210-ostm", "renesas,ostm"; +- reg = <0xe803d000 0x30>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 34>; +- power-domains = <&cpg>; +- status = "disabled"; +- }; +- +- ohci0: usb@e8218000 { +- compatible = "generic-ohci"; +- reg = <0xe8218000 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 61>; +- phys = <&usb2_phy0>; +- phy-names = "usb"; +- power-domains = <&cpg>; +- status = "disabled"; +- }; +- +- ehci0: usb@e8218100 { +- compatible = "generic-ehci"; +- reg = <0xe8218100 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 61>; +- phys = <&usb2_phy0>; +- phy-names = "usb"; +- power-domains = <&cpg>; +- status = "disabled"; +- }; +- +- usb2_phy0: usb-phy@e8218200 { +- compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy"; +- reg = <0xe8218200 0x700>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 61>, <&usb_x1_clk>; +- clock-names = "fck", "usb_x1"; +- power-domains = <&cpg>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- usbhs0: usb@e8219000 { +- compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs"; +- reg = <0xe8219000 0x724>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 61>; +- renesas,buswait = <7>; +- phys = <&usb2_phy0>; +- phy-names = "usb"; +- power-domains = <&cpg>; +- status = "disabled"; +- }; +- +- ohci1: usb@e821a000 { +- compatible = "generic-ohci"; +- reg = <0xe821a000 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 60>; +- phys = <&usb2_phy1>; +- phy-names = "usb"; +- power-domains = <&cpg>; +- status = "disabled"; +- }; +- +- ehci1: usb@e821a100 { +- compatible = "generic-ehci"; +- reg = <0xe821a100 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 60>; +- phys = <&usb2_phy1>; +- phy-names = "usb"; +- power-domains = <&cpg>; +- status = "disabled"; +- }; +- +- usb2_phy1: usb-phy@e821a200 { +- compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy"; +- reg = <0xe821a200 0x700>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 60>, <&usb_x1_clk>; +- clock-names = "fck", "usb_x1"; +- power-domains = <&cpg>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- usbhs1: usb@e821b000 { +- compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs"; +- reg = <0xe821b000 0x724>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 60>; +- renesas,buswait = <7>; +- phys = <&usb2_phy1>; +- phy-names = "usb"; +- power-domains = <&cpg>; +- status = "disabled"; +- }; +- +- sdhi0: mmc@e8228000 { +- compatible = "renesas,sdhi-r7s9210"; +- reg = <0xe8228000 0x8c0>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 103>, <&cpg CPG_MOD 102>; +- clock-names = "core", "cd"; +- power-domains = <&cpg>; +- cap-sd-highspeed; +- cap-sdio-irq; +- status = "disabled"; +- }; +- +- sdhi1: mmc@e822a000 { +- compatible = "renesas,sdhi-r7s9210"; +- reg = <0xe822a000 0x8c0>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 101>, <&cpg CPG_MOD 100>; +- clock-names = "core", "cd"; +- power-domains = <&cpg>; +- cap-sd-highspeed; +- cap-sdio-irq; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@e8221000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0xe8221000 0x1000>, +- <0xe8222000 0x1000>; +- }; +- +- cpg: clock-controller@fcfe0010 { +- compatible = "renesas,r7s9210-cpg-mssr"; +- reg = <0xfcfe0010 0x455>; +- clocks = <&extal_clk>; +- clock-names = "extal"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- }; +- +- wdt: watchdog@fcfe7000 { +- compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt"; +- reg = <0xfcfe7000 0x26>; +- interrupts = ; +- clocks = <&cpg CPG_CORE R7S9210_CLK_P0>; +- }; +- +- bsid: chipid@fcfe8004 { +- compatible = "renesas,bsid"; +- reg = <0xfcfe8004 4>; +- }; +- +- irqc: interrupt-controller@fcfef800 { +- compatible = "renesas,r7s9210-irqc", +- "renesas,rza1-irqc"; +- #interrupt-cells = <2>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0xfcfef800 0x6>; +- interrupt-map = +- <0 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, +- <1 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, +- <2 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, +- <3 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, +- <4 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, +- <5 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, +- <6 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, +- <7 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-map-mask = <7 0>; +- }; +- +- pinctrl: pinctrl@fcffe000 { +- compatible = "renesas,r7s9210-pinctrl"; +- reg = <0xfcffe000 0x1000>; +- +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 0 176>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a73a4-ape6evm.dts b/scripts/dtc/include-prefixes/arm/r8a73a4-ape6evm.dts +deleted file mode 100644 +index b088e8e351d5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a73a4-ape6evm.dts ++++ /dev/null +@@ -1,272 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the APE6EVM board +- * +- * Copyright (C) 2013 Renesas Solutions Corp. +- */ +- +-/dts-v1/; +-#include "r8a73a4.dtsi" +-#include +-#include +- +-/ { +- model = "APE6EVM"; +- compatible = "renesas,ape6evm", "renesas,r8a73a4"; +- +- aliases { +- serial0 = &scifa0; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x40000000>; +- }; +- +- memory@200000000 { +- device_type = "memory"; +- reg = <2 0x00000000 0 0x40000000>; +- }; +- +- vcc_mmc0: regulator-mmc0 { +- compatible = "regulator-fixed"; +- regulator-name = "MMC0 Vcc"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- vcc_sdhi0: regulator-sdhi0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI0 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&pfc 76 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- /* Common 1.8V and 3.3V rails, used by several devices on APE6EVM */ +- ape6evm_fixed_1v8: regulator-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ape6evm_fixed_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led1 { +- gpios = <&pfc 28 GPIO_ACTIVE_HIGH>; +- label = "GNSS_EN"; +- }; +- led2 { +- gpios = <&pfc 126 GPIO_ACTIVE_HIGH>; +- label = "NFC_NRST"; +- }; +- led3 { +- gpios = <&pfc 132 GPIO_ACTIVE_HIGH>; +- label = "GNSS_NRST"; +- }; +- led4 { +- gpios = <&pfc 232 GPIO_ACTIVE_HIGH>; +- label = "BT_WAKEUP"; +- }; +- led5 { +- gpios = <&pfc 250 GPIO_ACTIVE_HIGH>; +- label = "STROBE"; +- }; +- led6 { +- gpios = <&pfc 288 GPIO_ACTIVE_HIGH>; +- label = "BBRESETOUT"; +- }; +- }; +- +- keyboard { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&keyboard_pins>; +- +- zero-key { +- gpios = <&pfc 324 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "S16"; +- wakeup-source; +- }; +- +- menu-key { +- gpios = <&pfc 325 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "S17"; +- }; +- +- home-key { +- gpios = <&pfc 326 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "S18"; +- }; +- +- back-key { +- gpios = <&pfc 327 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "S19"; +- }; +- +- volup-key { +- gpios = <&pfc 328 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "S20"; +- }; +- +- voldown-key { +- gpios = <&pfc 329 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "S21"; +- }; +- }; +-}; +- +-&i2c5 { +- status = "okay"; +- vdd_dvfs: regulator@1b { +- compatible = "maxim,max8973"; +- reg = <0x1b>; +- +- regulator-min-microvolt = <935000>; +- regulator-max-microvolt = <1200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&cpu0 { +- cpu0-supply = <&vdd_dvfs>; +- operating-points = <1950000 1115000>, /* kHz uV */ +- <1462500 995000>; +- voltage-tolerance = <1>; /* 1% */ +-}; +- +-&bsc { +- flash@0 { +- compatible = "cfi-flash", "mtd-rom"; +- reg = <0x0 0x08000000>; +- bank-width = <2>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "uboot"; +- reg = <0x00000000 0x00040000>; +- read-only; +- }; +- partition@40000 { +- label = "uboot-env"; +- reg = <0x00040000 0x00040000>; +- read-only; +- }; +- partition@80000 { +- label = "flash"; +- reg = <0x00080000 0x07f80000>; +- }; +- }; +- }; +- +- ethernet@8000000 { +- compatible = "smsc,lan9220", "smsc,lan9115"; +- reg = <0x08000000 0x1000>; +- interrupt-parent = <&irqc1>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; +- phy-mode = "mii"; +- reg-io-width = <4>; +- smsc,irq-active-high; +- smsc,irq-push-pull; +- vdd33a-supply = <&ape6evm_fixed_3v3>; +- vddvario-supply = <&ape6evm_fixed_1v8>; +- }; +-}; +- +-&cmt1 { +- status = "okay"; +-}; +- +-&pfc { +- scifa0_pins: scifa0 { +- groups = "scifa0_data"; +- function = "scifa0"; +- }; +- +- mmc0_pins: mmc0 { +- groups = "mmc0_data8", "mmc0_ctrl"; +- function = "mmc0"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; +- function = "sdhi0"; +- }; +- +- sdhi1_pins: sd1 { +- groups = "sdhi1_data4", "sdhi1_ctrl"; +- function = "sdhi1"; +- }; +- +- keyboard_pins: keyboard { +- pins = "PORT324", "PORT325", "PORT326", "PORT327", "PORT328", +- "PORT329"; +- bias-pull-up; +- }; +-}; +- +-&mmcif0 { +- vmmc-supply = <&vcc_mmc0>; +- bus-width = <8>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- status = "okay"; +-}; +- +-&scifa0 { +- pinctrl-0 = <&scifa0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&sdhi0 { +- vmmc-supply = <&vcc_sdhi0>; +- bus-width = <4>; +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhi0_pins>; +- status = "okay"; +-}; +- +-&sdhi1 { +- vmmc-supply = <&ape6evm_fixed_3v3>; +- bus-width = <4>; +- broken-cd; +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhi1_pins>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a73a4.dtsi b/scripts/dtc/include-prefixes/arm/r8a73a4.dtsi +deleted file mode 100644 +index c39066967053..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a73a4.dtsi ++++ /dev/null +@@ -1,861 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the r8a73a4 SoC +- * +- * Copyright (C) 2013 Renesas Solutions Corp. +- * Copyright (C) 2013 Magnus Damm +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r8a73a4"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0>; +- clocks = <&cpg_clocks R8A73A4_CLK_Z>; +- clock-frequency = <1500000000>; +- power-domains = <&pd_a2sl>; +- next-level-cache = <&L2_CA15>; +- }; +- +- L2_CA15: cache-controller-0 { +- compatible = "cache"; +- clocks = <&cpg_clocks R8A73A4_CLK_Z>; +- power-domains = <&pd_a3sm>; +- cache-unified; +- cache-level = <2>; +- }; +- +- L2_CA7: cache-controller-1 { +- compatible = "cache"; +- clocks = <&cpg_clocks R8A73A4_CLK_Z2>; +- power-domains = <&pd_a3km>; +- cache-unified; +- cache-level = <2>; +- }; +- }; +- +- ptm { +- compatible = "arm,coresight-etm3x"; +- power-domains = <&pd_d4>; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- dbsc1: memory-controller@e6790000 { +- compatible = "renesas,dbsc-r8a73a4"; +- reg = <0 0xe6790000 0 0x10000>; +- power-domains = <&pd_a3bc>; +- }; +- +- dbsc2: memory-controller@e67a0000 { +- compatible = "renesas,dbsc-r8a73a4"; +- reg = <0 0xe67a0000 0 0x10000>; +- power-domains = <&pd_a3bc>; +- }; +- +- i2c5: i2c@e60b0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; +- reg = <0 0xe60b0000 0 0x428>; +- interrupts = ; +- clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; +- power-domains = <&pd_a3sp>; +- +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; +- clock-names = "fck"; +- power-domains = <&pd_c5>; +- status = "disabled"; +- }; +- +- irqc0: interrupt-controller@e61c0000 { +- compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; +- power-domains = <&pd_c4>; +- }; +- +- irqc1: interrupt-controller@e61c0200 { +- compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0200 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; +- power-domains = <&pd_c4>; +- }; +- +- pfc: pinctrl@e6050000 { +- compatible = "renesas,pfc-r8a73a4"; +- reg = <0 0xe6050000 0 0x9000>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = +- <&pfc 0 0 31>, <&pfc 32 32 9>, +- <&pfc 64 64 22>, <&pfc 96 96 31>, +- <&pfc 128 128 7>, <&pfc 160 160 19>, +- <&pfc 192 192 31>, <&pfc 224 224 27>, +- <&pfc 256 256 28>, <&pfc 288 288 21>, +- <&pfc 320 320 10>; +- interrupts-extended = +- <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, +- <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, +- <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, +- <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, +- <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, +- <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, +- <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, +- <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, +- <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, +- <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, +- <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, +- <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, +- <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, +- <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, +- <&irqc1 24 0>, <&irqc1 25 0>; +- power-domains = <&pd_c5>; +- }; +- +- thermal@e61f0000 { +- compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; +- reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, +- <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; +- interrupts = ; +- clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; +- power-domains = <&pd_c5>; +- }; +- +- i2c0: i2c@e6500000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; +- reg = <0 0xe6500000 0 0x428>; +- interrupts = ; +- clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6510000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; +- reg = <0 0xe6510000 0 0x428>; +- interrupts = ; +- clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6520000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; +- reg = <0 0xe6520000 0 0x428>; +- interrupts = ; +- clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e6530000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; +- reg = <0 0xe6530000 0 0x428>; +- interrupts = ; +- clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e6540000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; +- reg = <0 0xe6540000 0 0x428>; +- interrupts = ; +- clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- i2c6: i2c@e6550000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; +- reg = <0 0xe6550000 0 0x428>; +- interrupts = ; +- clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- i2c7: i2c@e6560000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; +- reg = <0 0xe6560000 0 0x428>; +- interrupts = ; +- clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- i2c8: i2c@e6570000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; +- reg = <0 0xe6570000 0 0x428>; +- interrupts = ; +- clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifb0: serial@e6c20000 { +- compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; +- reg = <0 0xe6c20000 0 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifb1: serial@e6c30000 { +- compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; +- reg = <0 0xe6c30000 0 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifa0: serial@e6c40000 { +- compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; +- reg = <0 0xe6c40000 0 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifa1: serial@e6c50000 { +- compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; +- reg = <0 0xe6c50000 0 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifb2: serial@e6ce0000 { +- compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; +- reg = <0 0xe6ce0000 0 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifb3: serial@e6cf0000 { +- compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; +- reg = <0 0xe6cf0000 0 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; +- clock-names = "fck"; +- power-domains = <&pd_c4>; +- status = "disabled"; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a73a4"; +- reg = <0 0xee100000 0 0x100>; +- interrupts = ; +- clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; +- power-domains = <&pd_a3sp>; +- cap-sd-highspeed; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ee120000 { +- compatible = "renesas,sdhi-r8a73a4"; +- reg = <0 0xee120000 0 0x100>; +- interrupts = ; +- clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; +- power-domains = <&pd_a3sp>; +- cap-sd-highspeed; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a73a4"; +- reg = <0 0xee140000 0 0x100>; +- interrupts = ; +- clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; +- power-domains = <&pd_a3sp>; +- cap-sd-highspeed; +- status = "disabled"; +- }; +- +- mmcif0: mmc@ee200000 { +- compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; +- reg = <0 0xee200000 0 0x80>; +- interrupts = ; +- clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; +- power-domains = <&pd_a3sp>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- mmcif1: mmc@ee220000 { +- compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; +- reg = <0 0xee220000 0 0x80>; +- interrupts = ; +- clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; +- power-domains = <&pd_a3sp>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1001000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0 0xf1001000 0 0x1000>, +- <0 0xf1002000 0 0x2000>, +- <0 0xf1004000 0 0x2000>, +- <0 0xf1006000 0 0x2000>; +- interrupts = ; +- clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>; +- clock-names = "clk"; +- power-domains = <&pd_c4>; +- }; +- +- bsc: bus@fec10000 { +- compatible = "renesas,bsc-r8a73a4", "renesas,bsc", +- "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0 0x20000000>; +- reg = <0 0xfec10000 0 0x400>; +- clocks = <&zb_clk>; +- power-domains = <&pd_c4>; +- }; +- +- clocks { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- /* External root clocks */ +- extalr_clk: extalr { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- extal1_clk: extal1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- extal2_clk: extal2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <48000000>; +- }; +- fsiack_clk: fsiack { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- fsibck_clk: fsibck { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- /* Special CPG clocks */ +- cpg_clocks: cpg_clocks@e6150000 { +- compatible = "renesas,r8a73a4-cpg-clocks"; +- reg = <0 0xe6150000 0 0x10000>; +- clocks = <&extal1_clk>, <&extal2_clk>; +- #clock-cells = <1>; +- clock-output-names = "main", "pll0", "pll1", "pll2", +- "pll2s", "pll2h", "z", "z2", +- "i", "m3", "b", "m1", "m2", +- "zx", "zs", "hp"; +- }; +- +- /* Variable factor clocks (DIV6) */ +- zb_clk: zb_clk@e6150010 { +- compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0 0xe6150010 0 4>; +- clocks = <&pll1_div2_clk>, <0>, +- <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; +- #clock-cells = <0>; +- clock-output-names = "zb"; +- }; +- sdhi0_clk: sdhi0ck@e6150074 { +- compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0 0xe6150074 0 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, +- <0>, <&extal2_clk>; +- #clock-cells = <0>; +- }; +- sdhi1_clk: sdhi1ck@e6150078 { +- compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0 0xe6150078 0 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, +- <0>, <&extal2_clk>; +- #clock-cells = <0>; +- }; +- sdhi2_clk: sdhi2ck@e615007c { +- compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0 0xe615007c 0 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, +- <0>, <&extal2_clk>; +- #clock-cells = <0>; +- }; +- mmc0_clk: mmc0@e6150240 { +- compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0 0xe6150240 0 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, +- <0>, <&extal2_clk>; +- #clock-cells = <0>; +- }; +- mmc1_clk: mmc1@e6150244 { +- compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0 0xe6150244 0 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, +- <0>, <&extal2_clk>; +- #clock-cells = <0>; +- }; +- vclk1_clk: vclk1@e6150008 { +- compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0 0xe6150008 0 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, +- <0>, <&extal2_clk>, <&main_div2_clk>, +- <&extalr_clk>, <0>, <0>; +- #clock-cells = <0>; +- }; +- vclk2_clk: vclk2@e615000c { +- compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0 0xe615000c 0 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, +- <0>, <&extal2_clk>, <&main_div2_clk>, +- <&extalr_clk>, <0>, <0>; +- #clock-cells = <0>; +- }; +- vclk3_clk: vclk3@e615001c { +- compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0 0xe615001c 0 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, +- <0>, <&extal2_clk>, <&main_div2_clk>, +- <&extalr_clk>, <0>, <0>; +- #clock-cells = <0>; +- }; +- vclk4_clk: vclk4@e6150014 { +- compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0 0xe6150014 0 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, +- <0>, <&extal2_clk>, <&main_div2_clk>, +- <&extalr_clk>, <0>, <0>; +- #clock-cells = <0>; +- }; +- vclk5_clk: vclk5@e6150034 { +- compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0 0xe6150034 0 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, +- <0>, <&extal2_clk>, <&main_div2_clk>, +- <&extalr_clk>, <0>, <0>; +- #clock-cells = <0>; +- }; +- fsia_clk: fsia@e6150018 { +- compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0 0xe6150018 0 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, +- <&fsiack_clk>, <0>; +- #clock-cells = <0>; +- }; +- fsib_clk: fsib@e6150090 { +- compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0 0xe6150090 0 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, +- <&fsibck_clk>, <0>; +- #clock-cells = <0>; +- }; +- mp_clk: mp@e6150080 { +- compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0 0xe6150080 0 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, +- <&extal2_clk>, <&extal2_clk>; +- #clock-cells = <0>; +- }; +- m4_clk: m4@e6150098 { +- compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0 0xe6150098 0 4>; +- clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; +- #clock-cells = <0>; +- }; +- hsi_clk: hsi@e615026c { +- compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0 0xe615026c 0 4>; +- clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, +- <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; +- #clock-cells = <0>; +- }; +- spuv_clk: spuv@e6150094 { +- compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0 0xe6150094 0 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, +- <&extal2_clk>, <&extal2_clk>; +- #clock-cells = <0>; +- }; +- +- /* Fixed factor clocks */ +- main_div2_clk: main_div2 { +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; +- #clock-cells = <0>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- pll0_div2_clk: pll0_div2 { +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; +- #clock-cells = <0>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- pll1_div2_clk: pll1_div2 { +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; +- #clock-cells = <0>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- extal1_div2_clk: extal1_div2 { +- compatible = "fixed-factor-clock"; +- clocks = <&extal1_clk>; +- #clock-cells = <0>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- /* Gate clocks */ +- mstp2_clks: mstp2_clks@e6150138 { +- compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; +- clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, +- <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; +- #clock-cells = <1>; +- clock-indices = < +- R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 +- R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 +- R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 +- R8A73A4_CLK_DMAC +- >; +- clock-output-names = +- "scifa0", "scifa1", "scifb0", "scifb1", +- "scifb2", "scifb3", "dmac"; +- }; +- mstp3_clks: mstp3_clks@e615013c { +- compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; +- clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>, +- <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>, +- <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>, +- <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks +- R8A73A4_CLK_HP>, <&cpg_clocks +- R8A73A4_CLK_HP>, <&extalr_clk>; +- #clock-cells = <1>; +- clock-indices = < +- R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1 +- R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1 +- R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0 +- R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7 +- R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1 +- R8A73A4_CLK_CMT1 +- >; +- clock-output-names = +- "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0", +- "mmcif0", "iic6", "iic7", "iic0", "iic1", +- "cmt1"; +- }; +- mstp4_clks: mstp4_clks@e6150140 { +- compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; +- clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, +- <&main_div2_clk>, +- <&cpg_clocks R8A73A4_CLK_HP>, +- <&cpg_clocks R8A73A4_CLK_HP>; +- #clock-cells = <1>; +- clock-indices = < +- R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS +- R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4 +- R8A73A4_CLK_IIC3 +- >; +- clock-output-names = +- "irqc", "intc-sys", "iic5", "iic4", "iic3"; +- }; +- mstp5_clks: mstp5_clks@e6150144 { +- compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; +- clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; +- #clock-cells = <1>; +- clock-indices = < +- R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 +- >; +- clock-output-names = +- "thermal", "iic8"; +- }; +- }; +- +- prr: chipid@ff000044 { +- compatible = "renesas,prr"; +- reg = <0 0xff000044 0 4>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile"; +- reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>; +- +- pm-domains { +- pd_c5: c5 { +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- pd_c4: c4@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- pd_a3sg: a3sg@16 { +- reg = <16>; +- #power-domain-cells = <0>; +- }; +- +- pd_a3ex: a3ex@17 { +- reg = <17>; +- #power-domain-cells = <0>; +- }; +- +- pd_a3sp: a3sp@18 { +- reg = <18>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- pd_a2us: a2us@19 { +- reg = <19>; +- #power-domain-cells = <0>; +- }; +- }; +- +- pd_a3sm: a3sm@20 { +- reg = <20>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- pd_a2sl: a2sl@21 { +- reg = <21>; +- #power-domain-cells = <0>; +- }; +- }; +- +- pd_a3km: a3km@22 { +- reg = <22>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- pd_a2kl: a2kl@23 { +- reg = <23>; +- #power-domain-cells = <0>; +- }; +- }; +- }; +- +- pd_c4ma: c4ma@1 { +- reg = <1>; +- #power-domain-cells = <0>; +- }; +- +- pd_c4cl: c4cl@2 { +- reg = <2>; +- #power-domain-cells = <0>; +- }; +- +- pd_d4: d4@3 { +- reg = <3>; +- #power-domain-cells = <0>; +- }; +- +- pd_a4bc: a4bc@4 { +- reg = <4>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- pd_a3bc: a3bc@5 { +- reg = <5>; +- #power-domain-cells = <0>; +- }; +- }; +- +- pd_a4l: a4l@6 { +- reg = <6>; +- #power-domain-cells = <0>; +- }; +- +- pd_a4lc: a4lc@7 { +- reg = <7>; +- #power-domain-cells = <0>; +- }; +- +- pd_a4mp: a4mp@8 { +- reg = <8>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- pd_a3mp: a3mp@9 { +- reg = <9>; +- #power-domain-cells = <0>; +- }; +- +- pd_a3vc: a3vc@10 { +- reg = <10>; +- #power-domain-cells = <0>; +- }; +- }; +- +- pd_a4sf: a4sf@11 { +- reg = <11>; +- #power-domain-cells = <0>; +- }; +- +- pd_a3r: a3r@12 { +- reg = <12>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- pd_a2rv: a2rv@13 { +- reg = <13>; +- #power-domain-cells = <0>; +- }; +- +- pd_a2is: a2is@14 { +- reg = <14>; +- #power-domain-cells = <0>; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7740-armadillo800eva.dts b/scripts/dtc/include-prefixes/arm/r8a7740-armadillo800eva.dts +deleted file mode 100644 +index d960c2767f61..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7740-armadillo800eva.dts ++++ /dev/null +@@ -1,315 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the armadillo 800 eva board +- * +- * Copyright (C) 2012 Renesas Solutions Corp. +- */ +- +-/dts-v1/; +-#include "r8a7740.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "armadillo 800 eva"; +- compatible = "renesas,armadillo800eva", "renesas,r8a7740"; +- +- aliases { +- serial0 = &scifa1; +- }; +- +- chosen { +- bootargs = "earlyprintk ignore_loglevel root=/dev/nfs ip=on rw"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x20000000>; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc_sdhi0: regulator-vcc-sdhi0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI0 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&pfc 75 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhi0: regulator-vccq-sdhi0 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI0 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc_sdhi0>; +- +- enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>; +- gpios = <&pfc 17 GPIO_ACTIVE_HIGH>; +- states = <3300000 0>, <1800000 1>; +- +- enable-active-high; +- }; +- +- reg_5p0v: regulator-5p0v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-5.0V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- keyboard { +- compatible = "gpio-keys"; +- +- power-key { +- gpios = <&pfc 99 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW3"; +- wakeup-source; +- }; +- +- back-key { +- gpios = <&pfc 100 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW4"; +- }; +- +- menu-key { +- gpios = <&pfc 97 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW5"; +- }; +- +- home-key { +- gpios = <&pfc 98 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW6"; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led3 { +- gpios = <&pfc 102 GPIO_ACTIVE_HIGH>; +- label = "LED3"; +- }; +- led4 { +- gpios = <&pfc 111 GPIO_ACTIVE_HIGH>; +- label = "LED4"; +- }; +- led5 { +- gpios = <&pfc 110 GPIO_ACTIVE_HIGH>; +- label = "LED5"; +- }; +- led6 { +- gpios = <&pfc 177 GPIO_ACTIVE_HIGH>; +- label = "LED6"; +- }; +- }; +- +- i2c2: i2c-2 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "i2c-gpio"; +- sda-gpios = <&pfc 208 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&pfc 91 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <5>; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>; +- brightness-levels = <0 1 2 4 8 16 32 64 128 255>; +- default-brightness-level = <9>; +- pinctrl-0 = <&backlight_pins>; +- pinctrl-names = "default"; +- power-supply = <®_5p0v>; +- enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- +- simple-audio-card,format = "i2s"; +- +- simple-audio-card,cpu { +- sound-dai = <&sh_fsi2 0>; +- bitclock-inversion; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&wm8978>; +- bitclock-master; +- frame-master; +- system-clock-frequency = <12288000>; +- }; +- }; +-}; +- +-ðer { +- pinctrl-0 = <ðer_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <&phy0>; +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&extal1_clk { +- clock-frequency = <24000000>; +-}; +-&extal2_clk { +- clock-frequency = <48000000>; +-}; +-&fsibck_clk { +- clock-frequency = <12288000>; +-}; +-&cpg_clocks { +- renesas,mode = <0x05>; /* MD_CK0 | MD_CK2 */ +-}; +- +-&cmt1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- touchscreen@55 { +- compatible = "sitronix,st1232"; +- reg = <0x55>; +- interrupt-parent = <&irqpin1>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-0 = <&st1232_pins>; +- pinctrl-names = "default"; +- gpios = <&pfc 166 GPIO_ACTIVE_LOW>; +- }; +- +- wm8978: codec@1a { +- #sound-dai-cells = <0>; +- compatible = "wlf,wm8978"; +- reg = <0x1a>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- rtc@30 { +- compatible = "sii,s35390a"; +- reg = <0x30>; +- }; +-}; +- +-&pfc { +- pinctrl-0 = <&lcd0_pins>; +- pinctrl-names = "default"; +- +- ether_pins: ether { +- groups = "gether_mii", "gether_int"; +- function = "gether"; +- }; +- +- scifa1_pins: scifa1 { +- groups = "scifa1_data"; +- function = "scifa1"; +- }; +- +- st1232_pins: touchscreen { +- groups = "intc_irq10"; +- function = "intc"; +- }; +- +- backlight_pins: backlight { +- groups = "tpu0_to2_1"; +- function = "tpu0"; +- }; +- +- mmc0_pins: mmc0 { +- groups = "mmc0_data8_1", "mmc0_ctrl_1"; +- function = "mmc0"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp"; +- function = "sdhi0"; +- }; +- +- fsia_pins: sounda { +- groups = "fsia_sclk_in", "fsia_mclk_out", +- "fsia_data_in_1", "fsia_data_out_0"; +- function = "fsia"; +- }; +- +- lcd0_pins: lcd0 { +- groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync"; +- function = "lcd0"; +- }; +- +- lcd0_mux { +- /* DBGMD/LCDC0/FSIA MUX */ +- gpio-hog; +- gpios = <176 0>; +- output-high; +- }; +-}; +- +-&tpu { +- status = "okay"; +-}; +- +-&mmcif0 { +- pinctrl-0 = <&mmc0_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <®_3p3v>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&scifa1 { +- pinctrl-0 = <&scifa1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <&vcc_sdhi0>; +- vqmmc-supply = <&vccq_sdhi0>; +- bus-width = <4>; +- cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&sh_fsi2 { +- pinctrl-0 = <&fsia_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&tmu0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7740.dtsi b/scripts/dtc/include-prefixes/arm/r8a7740.dtsi +deleted file mode 100644 +index 1b2cf5fa322b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7740.dtsi ++++ /dev/null +@@ -1,736 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Mobile A1 (R8A77400) SoC +- * +- * Copyright (C) 2012 Renesas Solutions Corp. +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r8a7740"; +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <0x0>; +- clock-frequency = <800000000>; +- power-domains = <&pd_a3sm>; +- next-level-cache = <&L2>; +- }; +- }; +- +- gic: interrupt-controller@c2800000 { +- compatible = "arm,pl390"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0xc2800000 0x1000>, +- <0xc2000000 0x1000>; +- }; +- +- L2: cache-controller@f0100000 { +- compatible = "arm,pl310-cache"; +- reg = <0xf0100000 0x1000>; +- interrupts = ; +- power-domains = <&pd_a3sm>; +- arm,data-latency = <3 3 3>; +- arm,tag-latency = <2 2 2>; +- arm,shared-override; +- cache-unified; +- cache-level = <2>; +- }; +- +- dbsc3: memory-controller@fe400000 { +- compatible = "renesas,dbsc3-r8a7740"; +- reg = <0xfe400000 0x400>; +- power-domains = <&pd_a4s>; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = ; +- }; +- +- ptm { +- compatible = "arm,coresight-etm3x"; +- power-domains = <&pd_d4>; +- }; +- +- ceu0: ceu@fe910000 { +- reg = <0xfe910000 0x3000>; +- compatible = "renesas,r8a7740-ceu"; +- interrupts = ; +- clocks = <&mstp1_clks R8A7740_CLK_CEU20>; +- power-domains = <&pd_a4r>; +- status = "disabled"; +- }; +- +- ceu1: ceu@fe914000 { +- reg = <0xfe914000 0x3000>; +- compatible = "renesas,r8a7740-ceu"; +- interrupts = ; +- clocks = <&mstp1_clks R8A7740_CLK_CEU21>; +- power-domains = <&pd_a4r>; +- status = "disabled"; +- }; +- +- cmt1: timer@e6138000 { +- compatible = "renesas,r8a7740-cmt1"; +- reg = <0xe6138000 0x170>; +- interrupts = ; +- clocks = <&mstp3_clks R8A7740_CLK_CMT1>; +- clock-names = "fck"; +- power-domains = <&pd_c5>; +- status = "disabled"; +- }; +- +- /* irqpin0: IRQ0 - IRQ7 */ +- irqpin0: interrupt-controller@e6900000 { +- compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0xe6900000 4>, +- <0xe6900010 4>, +- <0xe6900020 1>, +- <0xe6900040 1>, +- <0xe6900060 1>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&mstp2_clks R8A7740_CLK_INTCA>; +- power-domains = <&pd_a4s>; +- }; +- +- /* irqpin1: IRQ8 - IRQ15 */ +- irqpin1: interrupt-controller@e6900004 { +- compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0xe6900004 4>, +- <0xe6900014 4>, +- <0xe6900024 1>, +- <0xe6900044 1>, +- <0xe6900064 1>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&mstp2_clks R8A7740_CLK_INTCA>; +- power-domains = <&pd_a4s>; +- }; +- +- /* irqpin2: IRQ16 - IRQ23 */ +- irqpin2: interrupt-controller@e6900008 { +- compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0xe6900008 4>, +- <0xe6900018 4>, +- <0xe6900028 1>, +- <0xe6900048 1>, +- <0xe6900068 1>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&mstp2_clks R8A7740_CLK_INTCA>; +- power-domains = <&pd_a4s>; +- }; +- +- /* irqpin3: IRQ24 - IRQ31 */ +- irqpin3: interrupt-controller@e690000c { +- compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0xe690000c 4>, +- <0xe690001c 4>, +- <0xe690002c 1>, +- <0xe690004c 1>, +- <0xe690006c 1>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&mstp2_clks R8A7740_CLK_INTCA>; +- power-domains = <&pd_a4s>; +- }; +- +- ether: ethernet@e9a00000 { +- compatible = "renesas,gether-r8a7740"; +- reg = <0xe9a00000 0x800>, +- <0xe9a01800 0x800>; +- interrupts = ; +- clocks = <&mstp3_clks R8A7740_CLK_GETHER>; +- power-domains = <&pd_a4s>; +- phy-mode = "mii"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c0: i2c@fff20000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; +- reg = <0xfff20000 0x425>; +- interrupts = , +- , +- , +- ; +- clocks = <&mstp1_clks R8A7740_CLK_IIC0>; +- power-domains = <&pd_a4r>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6c20000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; +- reg = <0xe6c20000 0x425>; +- interrupts = , +- , +- , +- ; +- clocks = <&mstp3_clks R8A7740_CLK_IIC1>; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifa0: serial@e6c40000 { +- compatible = "renesas,scifa-r8a7740", "renesas,scifa"; +- reg = <0xe6c40000 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifa1: serial@e6c50000 { +- compatible = "renesas,scifa-r8a7740", "renesas,scifa"; +- reg = <0xe6c50000 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifa2: serial@e6c60000 { +- compatible = "renesas,scifa-r8a7740", "renesas,scifa"; +- reg = <0xe6c60000 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifa3: serial@e6c70000 { +- compatible = "renesas,scifa-r8a7740", "renesas,scifa"; +- reg = <0xe6c70000 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifa4: serial@e6c80000 { +- compatible = "renesas,scifa-r8a7740", "renesas,scifa"; +- reg = <0xe6c80000 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifa5: serial@e6cb0000 { +- compatible = "renesas,scifa-r8a7740", "renesas,scifa"; +- reg = <0xe6cb0000 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifa6: serial@e6cc0000 { +- compatible = "renesas,scifa-r8a7740", "renesas,scifa"; +- reg = <0xe6cc0000 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifa7: serial@e6cd0000 { +- compatible = "renesas,scifa-r8a7740", "renesas,scifa"; +- reg = <0xe6cd0000 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifb: serial@e6c30000 { +- compatible = "renesas,scifb-r8a7740", "renesas,scifb"; +- reg = <0xe6c30000 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- pfc: pinctrl@e6050000 { +- compatible = "renesas,pfc-r8a7740"; +- reg = <0xe6050000 0x8000>, +- <0xe605800c 0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pfc 0 0 212>; +- interrupts-extended = +- <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, +- <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, +- <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, +- <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, +- <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, +- <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, +- <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, +- <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; +- power-domains = <&pd_c5>; +- }; +- +- tpu: pwm@e6600000 { +- compatible = "renesas,tpu-r8a7740", "renesas,tpu"; +- reg = <0xe6600000 0x148>; +- clocks = <&mstp3_clks R8A7740_CLK_TPU0>; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- #pwm-cells = <3>; +- }; +- +- mmcif0: mmc@e6bd0000 { +- compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif"; +- reg = <0xe6bd0000 0x100>; +- interrupts = , +- ; +- clocks = <&mstp3_clks R8A7740_CLK_MMC>; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- sdhi0: mmc@e6850000 { +- compatible = "renesas,sdhi-r8a7740"; +- reg = <0xe6850000 0x100>; +- interrupts = , +- , +- ; +- clocks = <&mstp3_clks R8A7740_CLK_SDHI0>; +- power-domains = <&pd_a3sp>; +- cap-sd-highspeed; +- cap-sdio-irq; +- status = "disabled"; +- }; +- +- sdhi1: mmc@e6860000 { +- compatible = "renesas,sdhi-r8a7740"; +- reg = <0xe6860000 0x100>; +- interrupts = , +- , +- ; +- clocks = <&mstp3_clks R8A7740_CLK_SDHI1>; +- power-domains = <&pd_a3sp>; +- cap-sd-highspeed; +- cap-sdio-irq; +- status = "disabled"; +- }; +- +- sdhi2: mmc@e6870000 { +- compatible = "renesas,sdhi-r8a7740"; +- reg = <0xe6870000 0x100>; +- interrupts = , +- , +- ; +- clocks = <&mstp4_clks R8A7740_CLK_SDHI2>; +- power-domains = <&pd_a3sp>; +- cap-sd-highspeed; +- cap-sdio-irq; +- status = "disabled"; +- }; +- +- sh_fsi2: sound@fe1f0000 { +- #sound-dai-cells = <1>; +- compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; +- reg = <0xfe1f0000 0x400>; +- interrupts = ; +- clocks = <&mstp3_clks R8A7740_CLK_FSI>; +- power-domains = <&pd_a4mp>; +- status = "disabled"; +- }; +- +- tmu0: timer@fff80000 { +- compatible = "renesas,tmu-r8a7740", "renesas,tmu"; +- reg = <0xfff80000 0x2c>; +- interrupts = , +- , +- ; +- clocks = <&mstp1_clks R8A7740_CLK_TMU0>; +- clock-names = "fck"; +- power-domains = <&pd_a4r>; +- +- #renesas,channels = <3>; +- +- status = "disabled"; +- }; +- +- tmu1: timer@fff90000 { +- compatible = "renesas,tmu-r8a7740", "renesas,tmu"; +- reg = <0xfff90000 0x2c>; +- interrupts = , +- , +- ; +- clocks = <&mstp1_clks R8A7740_CLK_TMU1>; +- clock-names = "fck"; +- power-domains = <&pd_a4r>; +- +- #renesas,channels = <3>; +- +- status = "disabled"; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* External root clock */ +- extalr_clk: extalr { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- extal1_clk: extal1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- extal2_clk: extal2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- dv_clk: dv { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- }; +- fmsick_clk: fmsick { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- fmsock_clk: fmsock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- fsiack_clk: fsiack { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- fsibck_clk: fsibck { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* Special CPG clocks */ +- cpg_clocks: cpg_clocks@e6150000 { +- compatible = "renesas,r8a7740-cpg-clocks"; +- reg = <0xe6150000 0x10000>; +- clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>; +- #clock-cells = <1>; +- clock-output-names = "system", "pllc0", "pllc1", +- "pllc2", "r", +- "usb24s", +- "i", "zg", "b", "m1", "hp", +- "hpp", "usbp", "s", "zb", "m3", +- "cp"; +- }; +- +- /* Variable factor clocks (DIV6) */ +- vclk1_clk: vclk1@e6150008 { +- compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150008 4>; +- clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, +- <&cpg_clocks R8A7740_CLK_USB24S>, +- <&extal1_div2_clk>, <&extalr_clk>, <0>, +- <0>; +- #clock-cells = <0>; +- }; +- vclk2_clk: vclk2@e615000c { +- compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe615000c 4>; +- clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, +- <&cpg_clocks R8A7740_CLK_USB24S>, +- <&extal1_div2_clk>, <&extalr_clk>, <0>, +- <0>; +- #clock-cells = <0>; +- }; +- fmsi_clk: fmsi@e6150010 { +- compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150010 4>; +- clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>; +- #clock-cells = <0>; +- }; +- fmso_clk: fmso@e6150014 { +- compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150014 4>; +- clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>; +- #clock-cells = <0>; +- }; +- fsia_clk: fsia@e6150018 { +- compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150018 4>; +- clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>; +- #clock-cells = <0>; +- }; +- sub_clk: sub@e6150080 { +- compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150080 4>; +- clocks = <&pllc1_div2_clk>, +- <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; +- #clock-cells = <0>; +- }; +- spu_clk: spu@e6150084 { +- compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150084 4>; +- clocks = <&pllc1_div2_clk>, +- <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; +- #clock-cells = <0>; +- }; +- vou_clk: vou@e6150088 { +- compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150088 4>; +- clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>, +- <0>; +- #clock-cells = <0>; +- }; +- stpro_clk: stpro@e615009c { +- compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe615009c 4>; +- clocks = <&cpg_clocks R8A7740_CLK_PLLC0>; +- #clock-cells = <0>; +- }; +- +- /* Fixed factor clocks */ +- pllc1_div2_clk: pllc1_div2 { +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks R8A7740_CLK_PLLC1>; +- #clock-cells = <0>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- extal1_div2_clk: extal1_div2 { +- compatible = "fixed-factor-clock"; +- clocks = <&extal1_clk>; +- #clock-cells = <0>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- /* Gate clocks */ +- subck_clks: subck_clks@e6150080 { +- compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xe6150080 4>; +- clocks = <&sub_clk>, <&sub_clk>; +- #clock-cells = <1>; +- clock-indices = < +- R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2 +- >; +- clock-output-names = +- "subck", "subck2"; +- }; +- mstp1_clks: mstp1_clks@e6150134 { +- compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xe6150134 4>, <0xe6150038 4>; +- clocks = <&cpg_clocks R8A7740_CLK_S>, +- <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>, +- <&cpg_clocks R8A7740_CLK_B>, +- <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>, +- <&cpg_clocks R8A7740_CLK_B>; +- #clock-cells = <1>; +- clock-indices = < +- R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0 +- R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1 +- R8A7740_CLK_LCDC0 +- >; +- clock-output-names = +- "ceu21", "ceu20", "tmu0", "lcdc1", "iic0", +- "tmu1", "lcdc0"; +- }; +- mstp2_clks: mstp2_clks@e6150138 { +- compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xe6150138 4>, <0xe6150040 4>; +- clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, +- <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, +- <&cpg_clocks R8A7740_CLK_HP>, +- <&cpg_clocks R8A7740_CLK_HP>, +- <&cpg_clocks R8A7740_CLK_HP>, +- <&sub_clk>, <&sub_clk>, <&sub_clk>, +- <&sub_clk>, <&sub_clk>, <&sub_clk>, +- <&sub_clk>; +- #clock-cells = <1>; +- clock-indices = < +- R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA +- R8A7740_CLK_SCIFA7 +- R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2 +- R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC +- R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB +- R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1 +- R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3 +- R8A7740_CLK_SCIFA4 +- >; +- clock-output-names = +- "scifa6", "intca", +- "scifa7", "dmac1", "dmac2", "dmac3", +- "usbdmac", "scifa5", "scifb", "scifa0", "scifa1", +- "scifa2", "scifa3", "scifa4"; +- }; +- mstp3_clks: mstp3_clks@e615013c { +- compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xe615013c 4>, <0xe6150048 4>; +- clocks = <&cpg_clocks R8A7740_CLK_R>, +- <&cpg_clocks R8A7740_CLK_HP>, +- <&sub_clk>, +- <&cpg_clocks R8A7740_CLK_HP>, +- <&cpg_clocks R8A7740_CLK_HP>, +- <&cpg_clocks R8A7740_CLK_HP>, +- <&cpg_clocks R8A7740_CLK_HP>, +- <&cpg_clocks R8A7740_CLK_HP>, +- <&cpg_clocks R8A7740_CLK_HP>; +- #clock-cells = <1>; +- clock-indices = < +- R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1 +- R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1 +- R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0 +- >; +- clock-output-names = +- "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1", +- "mmc", "gether", "tpu0"; +- }; +- mstp4_clks: mstp4_clks@e6150140 { +- compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xe6150140 4>, <0xe615004c 4>; +- clocks = <&cpg_clocks R8A7740_CLK_HP>, +- <&cpg_clocks R8A7740_CLK_HP>, +- <&cpg_clocks R8A7740_CLK_HP>, +- <&cpg_clocks R8A7740_CLK_HP>; +- #clock-cells = <1>; +- clock-indices = < +- R8A7740_CLK_USBH R8A7740_CLK_SDHI2 +- R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY +- >; +- clock-output-names = +- "usbhost", "sdhi2", "usbfunc", "usphy"; +- }; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile"; +- reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; +- +- pm-domains { +- pd_c5: c5 { +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- pd_a4lc: a4lc@1 { +- reg = <1>; +- #power-domain-cells = <0>; +- }; +- +- pd_a4mp: a4mp@2 { +- reg = <2>; +- #power-domain-cells = <0>; +- }; +- +- pd_d4: d4@3 { +- reg = <3>; +- #power-domain-cells = <0>; +- }; +- +- pd_a4r: a4r@5 { +- reg = <5>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- pd_a3rv: a3rv@6 { +- reg = <6>; +- #power-domain-cells = <0>; +- }; +- }; +- +- pd_a4s: a4s@10 { +- reg = <10>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- pd_a3sp: a3sp@11 { +- reg = <11>; +- #power-domain-cells = <0>; +- }; +- +- pd_a3sm: a3sm@12 { +- reg = <12>; +- #power-domain-cells = <0>; +- }; +- +- pd_a3sg: a3sg@13 { +- reg = <13>; +- #power-domain-cells = <0>; +- }; +- }; +- +- pd_a4su: a4su@20 { +- reg = <20>; +- #power-domain-cells = <0>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7742-iwg21d-q7-dbcm-ca.dts b/scripts/dtc/include-prefixes/arm/r8a7742-iwg21d-q7-dbcm-ca.dts +deleted file mode 100644 +index 2bcb229844ab..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7742-iwg21d-q7-dbcm-ca.dts ++++ /dev/null +@@ -1,329 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the iWave-RZ/G1H Qseven board development +- * platform with camera daughter board +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a7742-iwg21d-q7.dts" +- +-/ { +- model = "iWave Systems RZ/G1H Qseven development platform with camera add-on"; +- compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742"; +- +- aliases { +- serial0 = &scif0; +- serial1 = &scif1; +- serial3 = &scifb1; +- serial5 = &hscif0; +- ethernet1 = ðer; +- }; +- +- mclk_cam1: mclk-cam1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +- +- mclk_cam2: mclk-cam2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +- +- mclk_cam3: mclk-cam3 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +- +- mclk_cam4: mclk-cam4 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +-}; +- +-&avb { +- /* Pins shared with VIN0, keep status disabled */ +- status = "disabled"; +-}; +- +-&can0 { +- pinctrl-0 = <&can0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-ðer { +- pinctrl-0 = <ðer_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <&phy1>; +- renesas,ether-link-active-low; +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- micrel,led-mode = <1>; +- }; +-}; +- +-&gpio0 { +- /* Disable hogging GP0_18 to output LOW */ +- /delete-node/ qspi_en; +- +- /* Hog GP0_18 to output HIGH to enable VIN2 */ +- vin2_en { +- gpio-hog; +- gpios = <18 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "VIN2_EN"; +- }; +-}; +- +-&hscif0 { +- pinctrl-0 = <&hscif0_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-0 = <&i2c1_pins>; +- pinctrl-names = "default"; +- +- /* status set to "okay" when needed by camera configuration below */ +- clock-frequency = <400000>; +-}; +- +-&i2c3 { +- pinctrl-0 = <&i2c3_pins>; +- pinctrl-names = "default"; +- +- /* status set to "okay" when needed by camera configuration below */ +- clock-frequency = <400000>; +-}; +- +-&pfc { +- can0_pins: can0 { +- groups = "can0_data_d"; +- function = "can0"; +- }; +- +- ether_pins: ether { +- groups = "eth_mdio", "eth_rmii"; +- function = "eth"; +- }; +- +- hscif0_pins: hscif0 { +- groups = "hscif0_data", "hscif0_ctrl"; +- function = "hscif0"; +- }; +- +- i2c1_pins: i2c1 { +- groups = "i2c1_c"; +- function = "i2c1"; +- }; +- +- i2c3_pins: i2c3 { +- groups = "i2c3"; +- function = "i2c3"; +- }; +- +- scif0_pins: scif0 { +- groups = "scif0_data"; +- function = "scif0"; +- }; +- +- scif1_pins: scif1 { +- groups = "scif1_data"; +- function = "scif1"; +- }; +- +- scifb1_pins: scifb1 { +- groups = "scifb1_data"; +- function = "scifb1"; +- }; +- +- vin0_8bit_pins: vin0 { +- groups = "vin0_data8", "vin0_clk", "vin0_sync"; +- function = "vin0"; +- }; +- +- vin1_8bit_pins: vin1 { +- groups = "vin1_data8_b", "vin1_clk_b", "vin1_sync_b"; +- function = "vin1"; +- }; +- +- vin2_pins: vin2 { +- groups = "vin2_g8", "vin2_clk"; +- function = "vin2"; +- }; +- +- vin3_pins: vin3 { +- groups = "vin3_data8", "vin3_clk", "vin3_sync"; +- function = "vin3"; +- }; +-}; +- +-&qspi { +- /* Pins shared with VIN2, keep status disabled */ +- status = "disabled"; +-}; +- +-&scif0 { +- pinctrl-0 = <&scif0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&scif1 { +- pinctrl-0 = <&scif1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&scifb1 { +- pinctrl-0 = <&scifb1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- rts-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; +- cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; +-}; +- +-/* +- * Below configuration ties VINx endpoints to ov5640/ov7725 camera endpoints +- * +- * (un)comment the #include statements to change configuration +- */ +- +-/* 8bit CMOS Camera 1 (J13) */ +-#define CAM_PARENT_I2C i2c0 +-#define MCLK_CAM mclk_cam1 +-#define CAM_EP cam0ep +-#define VIN_EP vin0ep +-#undef CAM_ENABLED +-#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi" +-//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi" +- +-#ifdef CAM_ENABLED +-&vin0 { +- /* +- * Set SW2 switch on the SOM to 'ON' +- * Set SW1 switch on camera board to 'OFF' as we are using 8bit mode +- */ +- status = "okay"; +- pinctrl-0 = <&vin0_8bit_pins>; +- pinctrl-names = "default"; +- +- port { +- vin0ep: endpoint { +- remote-endpoint = <&cam0ep>; +- bus-width = <8>; +- bus-type = <6>; +- }; +- }; +-}; +-#endif /* CAM_ENABLED */ +- +-#undef CAM_PARENT_I2C +-#undef MCLK_CAM +-#undef CAM_EP +-#undef VIN_EP +- +-/* 8bit CMOS Camera 2 (J14) */ +-#define CAM_PARENT_I2C i2c1 +-#define MCLK_CAM mclk_cam2 +-#define CAM_EP cam1ep +-#define VIN_EP vin1ep +-#undef CAM_ENABLED +-#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi" +-//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi" +- +-#ifdef CAM_ENABLED +-&vin1 { +- /* Set SW1 switch on the SOM to 'ON' */ +- status = "okay"; +- pinctrl-0 = <&vin1_8bit_pins>; +- pinctrl-names = "default"; +- +- port { +- vin1ep: endpoint { +- remote-endpoint = <&cam1ep>; +- bus-width = <8>; +- bus-type = <6>; +- }; +- }; +-}; +- +-#endif /* CAM_ENABLED */ +- +-#undef CAM_PARENT_I2C +-#undef MCLK_CAM +-#undef CAM_EP +-#undef VIN_EP +- +-/* 8bit CMOS Camera 3 (J12) */ +-#define CAM_PARENT_I2C i2c2 +-#define MCLK_CAM mclk_cam3 +-#define CAM_EP cam2ep +-#define VIN_EP vin2ep +-#undef CAM_ENABLED +-#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi" +-//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi" +- +-#ifdef CAM_ENABLED +-&vin2 { +- status = "okay"; +- pinctrl-0 = <&vin2_pins>; +- pinctrl-names = "default"; +- +- port { +- vin2ep: endpoint { +- remote-endpoint = <&cam2ep>; +- bus-width = <8>; +- data-shift = <8>; +- bus-type = <6>; +- }; +- }; +-}; +-#endif /* CAM_ENABLED */ +- +-#undef CAM_PARENT_I2C +-#undef MCLK_CAM +-#undef CAM_EP +-#undef VIN_EP +- +-/* 8bit CMOS Camera 4 (J11) */ +-#define CAM_PARENT_I2C i2c3 +-#define MCLK_CAM mclk_cam4 +-#define CAM_EP cam3ep +-#define VIN_EP vin3ep +-#undef CAM_ENABLED +-#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi" +-//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi" +- +-#ifdef CAM_ENABLED +-&vin3 { +- status = "okay"; +- pinctrl-0 = <&vin3_pins>; +- pinctrl-names = "default"; +- +- port { +- vin3ep: endpoint { +- remote-endpoint = <&cam3ep>; +- bus-width = <8>; +- bus-type = <6>; +- }; +- }; +-}; +-#endif /* CAM_ENABLED */ +- +-#undef CAM_PARENT_I2C +-#undef MCLK_CAM +-#undef CAM_EP +-#undef VIN_EP +diff --git a/scripts/dtc/include-prefixes/arm/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi b/scripts/dtc/include-prefixes/arm/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi +deleted file mode 100644 +index 70c72ba4fe72..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * This include file ties a VIN interface with a single ov5640 sensor on +- * the iWave-RZ/G1H Qseven board development platform connected with the +- * camera daughter board. +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-#define CAM_ENABLED 1 +- +-&CAM_PARENT_I2C { +- status = "okay"; +- +- ov5640@3c { +- compatible = "ovti,ov5640"; +- reg = <0x3c>; +- clocks = <&MCLK_CAM>; +- clock-names = "xclk"; +- status = "okay"; +- +- port { +- CAM_EP: endpoint { +- bus-width = <8>; +- data-shift = <2>; +- bus-type = <6>; +- pclk-sample = <1>; +- remote-endpoint = <&VIN_EP>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi b/scripts/dtc/include-prefixes/arm/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi +deleted file mode 100644 +index f5e77f024251..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi ++++ /dev/null +@@ -1,29 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * This include file ties a VIN interface with a single ov7725 sensor on +- * the iWave-RZ/G1H Qseven board development platform connected with the +- * camera daughter board. +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-#define CAM_ENABLED 1 +- +-&CAM_PARENT_I2C { +- status = "okay"; +- +- ov7725@21 { +- compatible = "ovti,ov7725"; +- reg = <0x21>; +- clocks = <&MCLK_CAM>; +- status = "okay"; +- +- port { +- CAM_EP: endpoint { +- bus-width = <8>; +- bus-type = <6>; +- remote-endpoint = <&VIN_EP>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7742-iwg21d-q7.dts b/scripts/dtc/include-prefixes/arm/r8a7742-iwg21d-q7.dts +deleted file mode 100644 +index 94bf8a116b52..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7742-iwg21d-q7.dts ++++ /dev/null +@@ -1,443 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the iWave-RZ/G1H Qseven board +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-/* +- * SSI-SGTL5000 +- * +- * This command is required when Playback/Capture +- * +- * amixer set "DVC Out" 100% +- * amixer set "DVC In" 100% +- * +- * You can use Mute +- * +- * amixer set "DVC Out Mute" on +- * amixer set "DVC In Mute" on +- * +- * You can use Volume Ramp +- * +- * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" +- * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" +- * amixer set "DVC Out Ramp" on +- * aplay xxx.wav & +- * amixer set "DVC Out" 80% // Volume Down +- * amixer set "DVC Out" 100% // Volume Up +- */ +- +-/dts-v1/; +-#include "r8a7742-iwg21m.dtsi" +-#include +- +-/ { +- model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H"; +- compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742"; +- +- aliases { +- serial2 = &scifa2; +- serial4 = &scifb2; +- ethernet0 = &avb; +- }; +- +- chosen { +- bootargs = "ignore_loglevel root=/dev/mmcblk0p1 rw rootwait"; +- stdout-path = "serial2:115200n8"; +- }; +- +- audio_clock: audio_clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +- +- lcd_backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&tpu 2 5000000 0>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- pinctrl-0 = <&backlight_pins>; +- pinctrl-names = "default"; +- default-brightness-level = <7>; +- enable-gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- sdhi2_led { +- label = "sdio-led"; +- gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc1"; +- }; +- }; +- +- lvds-receiver { +- compatible = "ti,ds90cf384a", "lvds-decoder"; +- power-supply = <&vcc_3v3_tft1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds_receiver_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- port@1 { +- reg = <1>; +- lvds_receiver_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +- }; +- +- panel { +- compatible = "edt,etm0700g0dh6"; +- backlight = <&lcd_backlight>; +- power-supply = <&vcc_3v3_tft1>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds_receiver_out>; +- }; +- }; +- }; +- +- reg_1p5v: 1p5v { +- compatible = "regulator-fixed"; +- regulator-name = "1P5V"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- +- rsnd_sgtl5000: sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sndcodec>; +- simple-audio-card,frame-master = <&sndcodec>; +- +- sndcpu: simple-audio-card,cpu { +- sound-dai = <&rcar_sound>; +- }; +- +- sndcodec: simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- }; +- }; +- +- vcc_3v3_tft1: regulator-panel { +- compatible = "regulator-fixed"; +- +- regulator-name = "vcc-3v3-tft1"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- startup-delay-us = <500>; +- gpio = <&gpio5 28 GPIO_ACTIVE_HIGH>; +- }; +- +- vcc_sdhi2: regulator-vcc-sdhi2 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI2 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio1 27 GPIO_ACTIVE_LOW>; +- }; +- +- vccq_sdhi2: regulator-vccq-sdhi2 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI2 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +-}; +- +-&avb { +- pinctrl-0 = <&avb_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <&phy3>; +- phy-mode = "gmii"; +- renesas,no-ether-link; +- status = "okay"; +- +- phy3: ethernet-phy@3 { +- reg = <3>; +- micrel,led-mode = <1>; +- }; +-}; +- +-&i2c2 { +- pinctrl-0 = <&i2c2_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- #sound-dai-cells = <0>; +- reg = <0x0a>; +- clocks = <&audio_clock>; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; +- VDDD-supply = <®_1p5v>; +- }; +- +- touch: touchpanel@38 { +- compatible = "edt,edt-ft5406"; +- reg = <0x38>; +- interrupt-parent = <&gpio0>; +- interrupts = <24 IRQ_TYPE_EDGE_FALLING>; +- /* GP1_29 is also shared with audio codec reset pin */ +- reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; +- vcc-supply = <&vcc_3v3_tft1>; +- }; +-}; +- +-&can1 { +- pinctrl-0 = <&can1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&cmt0 { +- status = "okay"; +-}; +- +-&du { +- status = "okay"; +-}; +- +-&gpio0 { +- touch-interrupt { +- gpio-hog; +- gpios = <24 GPIO_ACTIVE_LOW>; +- input; +- }; +-}; +- +-&gpio1 { +- can-trx-en-gpio{ +- gpio-hog; +- gpios = <28 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "can-trx-en-gpio"; +- }; +-}; +- +-&hsusb { +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&lvds0 { +- status = "okay"; +- ports { +- port@1 { +- lvds0_out: endpoint { +- remote-endpoint = <&lvds_receiver_in>; +- }; +- }; +- }; +-}; +- +-&msiof0 { +- pinctrl-0 = <&msiof0_pins>; +- pinctrl-names = "default"; +- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; +- +- status = "okay"; +- +- flash1: flash@0 { +- compatible = "sst,sst25vf016b", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- m25p,fast-read; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "user"; +- reg = <0x00000000 0x00200000>; +- }; +- }; +- }; +-}; +- +-&pci0 { +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +- /* Disable hsusb to enable USB2.0 host mode support on J2 */ +- /* status = "okay"; */ +-}; +- +-&pci1 { +- pinctrl-0 = <&usb1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&pci2 { +- /* Disable xhci to enable USB2.0 host mode support on J23 bottom port */ +- /* status = "okay"; */ +-}; +- +-&pcie_bus_clk { +- clock-frequency = <100000000>; +-}; +- +-&pciec { +- /* SW2[6] determines which connector is activated +- * ON = PCIe X4 (connector-J7) +- * OFF = mini-PCIe (connector-J26) +- */ +- status = "okay"; +-}; +- +-&pfc { +- avb_pins: avb { +- groups = "avb_mdio", "avb_gmii"; +- function = "avb"; +- }; +- +- backlight_pins: backlight { +- groups = "tpu0_to2"; +- function = "tpu0"; +- }; +- +- can1_pins: can1 { +- groups = "can1_data_b"; +- function = "can1"; +- }; +- +- i2c2_pins: i2c2 { +- groups = "i2c2_b"; +- function = "i2c2"; +- }; +- +- msiof0_pins: msiof0 { +- groups = "msiof0_clk", "msiof0_sync", "msiof0_tx", "msiof0_rx"; +- function = "msiof0"; +- }; +- +- scifa2_pins: scifa2 { +- groups = "scifa2_data_c"; +- function = "scifa2"; +- }; +- +- scifb2_pins: scifb2 { +- groups = "scifb2_data", "scifb2_ctrl"; +- function = "scifb2"; +- }; +- +- sdhi2_pins: sd2 { +- groups = "sdhi2_data4", "sdhi2_ctrl"; +- function = "sdhi2"; +- power-source = <3300>; +- }; +- +- sdhi2_pins_uhs: sd2_uhs { +- groups = "sdhi2_data4", "sdhi2_ctrl"; +- function = "sdhi2"; +- power-source = <1800>; +- }; +- +- sound_pins: sound { +- groups = "ssi34_ctrl", "ssi3_data", "ssi4_data"; +- function = "ssi"; +- }; +- +- usb0_pins: usb0 { +- groups = "usb0"; +- function = "usb0"; +- }; +- +- usb1_pins: usb1 { +- groups = "usb1_pwen"; +- function = "usb1"; +- }; +-}; +- +-&rcar_sound { +- pinctrl-0 = <&sound_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- /* Single DAI */ +- #sound-dai-cells = <0>; +- +- rcar_sound,dai { +- dai0 { +- playback = <&ssi4>, <&src4>, <&dvc1>; +- capture = <&ssi3>, <&src3>, <&dvc0>; +- }; +- }; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&scifa2 { +- pinctrl-0 = <&scifa2_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scifb2 { +- pinctrl-0 = <&scifb2_pins>; +- pinctrl-names = "default"; +- +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&sdhi2 { +- pinctrl-0 = <&sdhi2_pins>; +- pinctrl-1 = <&sdhi2_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <&vcc_sdhi2>; +- vqmmc-supply = <&vccq_sdhi2>; +- cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; +- sd-uhs-sdr50; +- status = "okay"; +-}; +- +-&ssi4 { +- shared-pin; +-}; +- +-&tpu { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&xhci { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7742-iwg21m.dtsi b/scripts/dtc/include-prefixes/arm/r8a7742-iwg21m.dtsi +deleted file mode 100644 +index 5621c9ed698f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7742-iwg21m.dtsi ++++ /dev/null +@@ -1,124 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the iWave RZ/G1H Qseven SOM +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-#include "r8a7742.dtsi" +-#include +- +-/ { +- compatible = "iwave,g21m", "renesas,r8a7742"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x40000000>; +- }; +- +- memory@200000000 { +- device_type = "memory"; +- reg = <2 0x00000000 0 0x40000000>; +- }; +- +- reg_3p3v: 3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&extal_clk { +- clock-frequency = <20000000>; +-}; +- +-&gpio0 { +- /* GP0_18 set low to select QSPI. Doing so will disable VIN2 */ +- qspi_en { +- gpio-hog; +- gpios = <18 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "QSPI_EN"; +- }; +-}; +- +-&i2c0 { +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- rtc@68 { +- compatible = "ti,bq32000"; +- reg = <0x68>; +- interrupt-parent = <&gpio1>; +- interrupts = <1 IRQ_TYPE_EDGE_FALLING>; +- }; +-}; +- +-&mmcif1 { +- pinctrl-0 = <&mmc1_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <®_3p3v>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&pfc { +- i2c0_pins: i2c0 { +- groups = "i2c0"; +- function = "i2c0"; +- }; +- +- mmc1_pins: mmc1 { +- groups = "mmc1_data4", "mmc1_ctrl"; +- function = "mmc1"; +- }; +- +- qspi_pins: qspi { +- groups = "qspi_ctrl", "qspi_data2"; +- function = "qspi"; +- }; +-}; +- +-&qspi { +- pinctrl-0 = <&qspi_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- flash: flash@0 { +- compatible = "sst,sst25vf016b", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- m25p,fast-read; +- spi-cpol; +- spi-cpha; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "bootloader"; +- reg = <0x00000000 0x000c0000>; +- read-only; +- }; +- partition@c0000 { +- label = "env"; +- reg = <0x000c0000 0x00002000>; +- }; +- partition@c2000 { +- label = "user"; +- reg = <0x000c2000 0x0013e000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7742.dtsi b/scripts/dtc/include-prefixes/arm/r8a7742.dtsi +deleted file mode 100644 +index 420e0b3259d4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7742.dtsi ++++ /dev/null +@@ -1,1891 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the r8a7742 SoC +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r8a7742"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- /* +- * The external audio clocks are configured as 0 Hz fixed frequency +- * clocks by default. +- * Boards that provide audio clocks should override them. +- */ +- audio_clk_a: audio_clk_a { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- audio_clk_b: audio_clk_b { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- audio_clk_c: audio_clk_c { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* External CAN clock */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0>; +- clock-frequency = <1400000000>; +- clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; +- power-domains = <&sysc R8A7742_PD_CA15_CPU0>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA15>; +- capacity-dmips-mhz = <1024>; +- voltage-tolerance = <1>; /* 1% */ +- clock-latency = <300000>; /* 300 us */ +- +- /* kHz - uV - OPPs unknown yet */ +- operating-points = <1400000 1000000>, +- <1225000 1000000>, +- <1050000 1000000>, +- < 875000 1000000>, +- < 700000 1000000>, +- < 350000 1000000>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <1>; +- clock-frequency = <1400000000>; +- clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; +- power-domains = <&sysc R8A7742_PD_CA15_CPU1>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA15>; +- capacity-dmips-mhz = <1024>; +- voltage-tolerance = <1>; /* 1% */ +- clock-latency = <300000>; /* 300 us */ +- +- /* kHz - uV - OPPs unknown yet */ +- operating-points = <1400000 1000000>, +- <1225000 1000000>, +- <1050000 1000000>, +- < 875000 1000000>, +- < 700000 1000000>, +- < 350000 1000000>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <2>; +- clock-frequency = <1400000000>; +- clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; +- power-domains = <&sysc R8A7742_PD_CA15_CPU2>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA15>; +- capacity-dmips-mhz = <1024>; +- voltage-tolerance = <1>; /* 1% */ +- clock-latency = <300000>; /* 300 us */ +- +- /* kHz - uV - OPPs unknown yet */ +- operating-points = <1400000 1000000>, +- <1225000 1000000>, +- <1050000 1000000>, +- < 875000 1000000>, +- < 700000 1000000>, +- < 350000 1000000>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <3>; +- clock-frequency = <1400000000>; +- clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; +- power-domains = <&sysc R8A7742_PD_CA15_CPU3>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA15>; +- capacity-dmips-mhz = <1024>; +- voltage-tolerance = <1>; /* 1% */ +- clock-latency = <300000>; /* 300 us */ +- +- /* kHz - uV - OPPs unknown yet */ +- operating-points = <1400000 1000000>, +- <1225000 1000000>, +- <1050000 1000000>, +- < 875000 1000000>, +- < 700000 1000000>, +- < 350000 1000000>; +- }; +- +- cpu4: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x100>; +- clock-frequency = <780000000>; +- clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; +- power-domains = <&sysc R8A7742_PD_CA7_CPU0>; +- next-level-cache = <&L2_CA7>; +- }; +- +- cpu5: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x101>; +- clock-frequency = <780000000>; +- clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; +- power-domains = <&sysc R8A7742_PD_CA7_CPU1>; +- next-level-cache = <&L2_CA7>; +- }; +- +- cpu6: cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x102>; +- clock-frequency = <780000000>; +- clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; +- power-domains = <&sysc R8A7742_PD_CA7_CPU2>; +- next-level-cache = <&L2_CA7>; +- }; +- +- cpu7: cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x103>; +- clock-frequency = <780000000>; +- clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; +- power-domains = <&sysc R8A7742_PD_CA7_CPU3>; +- next-level-cache = <&L2_CA7>; +- }; +- +- L2_CA15: cache-controller-0 { +- compatible = "cache"; +- power-domains = <&sysc R8A7742_PD_CA15_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- +- L2_CA7: cache-controller-1 { +- compatible = "cache"; +- power-domains = <&sysc R8A7742_PD_CA7_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- }; +- +- /* External root clock */ +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- /* External PCIe clock - can be overridden by the board */ +- pcie_bus_clk: pcie_bus { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- pmu-0 { +- compatible = "arm,cortex-a15-pmu"; +- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- pmu-1 { +- compatible = "arm,cortex-a7-pmu"; +- interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; +- }; +- +- /* External SCIF clock */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a7742-wdt", +- "renesas,rcar-gen2-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a7742", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a7742", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 30>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a7742", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 30>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a7742", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a7742", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a7742", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a7742"; +- reg = <0 0xe6060000 0 0x250>; +- }; +- +- tpu: pwm@e60f0000 { +- compatible = "renesas,tpu-r8a7742", "renesas,tpu"; +- reg = <0 0xe60f0000 0 0x148>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 304>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 304>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a7742-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>, <&usb_extal_clk>; +- clock-names = "extal", "usb_extal"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- apmu@e6151000 { +- compatible = "renesas,r8a7742-apmu", "renesas,apmu"; +- reg = <0 0xe6151000 0 0x188>; +- cpus = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; +- }; +- +- apmu@e6152000 { +- compatible = "renesas,r8a7742-apmu", "renesas,apmu"; +- reg = <0 0xe6152000 0 0x188>; +- cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a7742-rst"; +- reg = <0 0xe6160000 0 0x0100>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a7742-sysc"; +- reg = <0 0xe6180000 0 0x0200>; +- #power-domain-cells = <1>; +- }; +- +- irqc: interrupt-controller@e61c0000 { +- compatible = "renesas,irqc-r8a7742", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- thermal: thermal@e61f0000 { +- compatible = "renesas,thermal-r8a7742", +- "renesas,rcar-gen2-thermal"; +- reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 522>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 522>; +- #thermal-sensor-cells = <0>; +- }; +- +- ipmmu_sy0: iommu@e6280000 { +- compatible = "renesas,ipmmu-r8a7742", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6280000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_sy1: iommu@e6290000 { +- compatible = "renesas,ipmmu-r8a7742", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6290000 0 0x1000>; +- interrupts = ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_ds: iommu@e6740000 { +- compatible = "renesas,ipmmu-r8a7742", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6740000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_mp: iommu@ec680000 { +- compatible = "renesas,ipmmu-r8a7742", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xec680000 0 0x1000>; +- interrupts = ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_mx: iommu@fe951000 { +- compatible = "renesas,ipmmu-r8a7742", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xfe951000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- icram0: sram@e63a0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63a0000 0 0x12000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63a0000 0x12000>; +- }; +- +- icram1: sram@e63c0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63c0000 0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63c0000 0x1000>; +- +- smp-sram@0 { +- compatible = "renesas,smp-sram"; +- reg = <0 0x100>; +- }; +- }; +- +- icram2: sram@e6300000 { +- compatible = "mmio-sram"; +- reg = <0 0xe6300000 0 0x40000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe6300000 0x40000>; +- }; +- +- i2c0: i2c@e6508000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7742", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6518000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7742", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6518000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6530000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7742", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6530000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e6540000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7742", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6540000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- iic0: i2c@e6500000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7742", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe6500000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 318>; +- dmas = <&dmac0 0x61>, <&dmac0 0x62>, +- <&dmac1 0x61>, <&dmac1 0x62>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 318>; +- status = "disabled"; +- }; +- +- iic1: i2c@e6510000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7742", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe6510000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 323>; +- dmas = <&dmac0 0x65>, <&dmac0 0x66>, +- <&dmac1 0x65>, <&dmac1 0x66>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 323>; +- status = "disabled"; +- }; +- +- iic2: i2c@e6520000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7742", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe6520000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 300>; +- dmas = <&dmac0 0x69>, <&dmac0 0x6a>, +- <&dmac1 0x69>, <&dmac1 0x6a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 300>; +- status = "disabled"; +- }; +- +- iic3: i2c@e60b0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7742", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe60b0000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 926>; +- dmas = <&dmac0 0x77>, <&dmac0 0x78>, +- <&dmac1 0x77>, <&dmac1 0x78>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 926>; +- status = "disabled"; +- }; +- +- hsusb: usb@e6590000 { +- compatible = "renesas,usbhs-r8a7742", +- "renesas,rcar-gen2-usbhs"; +- reg = <0 0xe6590000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 704>; +- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, +- <&usb_dmac1 0>, <&usb_dmac1 1>; +- dma-names = "ch0", "ch1", "ch2", "ch3"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 704>; +- renesas,buswait = <4>; +- phys = <&usb0 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usbphy: usb-phy@e6590100 { +- compatible = "renesas,usb-phy-r8a7742", +- "renesas,rcar-gen2-usb-phy"; +- reg = <0 0xe6590100 0 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cpg CPG_MOD 704>; +- clock-names = "usbhs"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 704>; +- status = "disabled"; +- +- usb0: usb-channel@0 { +- reg = <0>; +- #phy-cells = <1>; +- }; +- usb2: usb-channel@2 { +- reg = <2>; +- #phy-cells = <1>; +- }; +- }; +- +- usb_dmac0: dma-controller@e65a0000 { +- compatible = "renesas,r8a7742-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65a0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 330>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 330>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac1: dma-controller@e65b0000 { +- compatible = "renesas,r8a7742-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65b0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 331>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 331>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a7742", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- dmac1: dma-controller@e6720000 { +- compatible = "renesas,dmac-r8a7742", +- "renesas,rcar-dmac"; +- reg = <0 0xe6720000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a7742", +- "renesas,etheravb-rcar-gen2"; +- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- qspi: spi@e6b10000 { +- compatible = "renesas,qspi-r8a7742", "renesas,qspi"; +- reg = <0 0xe6b10000 0 0x2c>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 917>; +- dmas = <&dmac0 0x17>, <&dmac0 0x18>, +- <&dmac1 0x17>, <&dmac1 0x18>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 917>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- scifa0: serial@e6c40000 { +- compatible = "renesas,scifa-r8a7742", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c40000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>; +- clock-names = "fck"; +- dmas = <&dmac0 0x21>, <&dmac0 0x22>, +- <&dmac1 0x21>, <&dmac1 0x22>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scifa1: serial@e6c50000 { +- compatible = "renesas,scifa-r8a7742", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c50000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>; +- clock-names = "fck"; +- dmas = <&dmac0 0x25>, <&dmac0 0x26>, +- <&dmac1 0x25>, <&dmac1 0x26>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- scifa2: serial@e6c60000 { +- compatible = "renesas,scifa-r8a7742", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c60000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 202>; +- clock-names = "fck"; +- dmas = <&dmac0 0x27>, <&dmac0 0x28>, +- <&dmac1 0x27>, <&dmac1 0x28>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 202>; +- status = "disabled"; +- }; +- +- scifb0: serial@e6c20000 { +- compatible = "renesas,scifb-r8a7742", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6c20000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>; +- clock-names = "fck"; +- dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, +- <&dmac1 0x3d>, <&dmac1 0x3e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scifb1: serial@e6c30000 { +- compatible = "renesas,scifb-r8a7742", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6c30000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>; +- clock-names = "fck"; +- dmas = <&dmac0 0x19>, <&dmac0 0x1a>, +- <&dmac1 0x19>, <&dmac1 0x1a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scifb2: serial@e6ce0000 { +- compatible = "renesas,scifb-r8a7742", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6ce0000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 216>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, +- <&dmac1 0x1d>, <&dmac1 0x1e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 216>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a7742", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e60000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 721>, +- <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x29>, <&dmac0 0x2a>, +- <&dmac1 0x29>, <&dmac1 0x2a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 721>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a7742", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e68000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 720>, +- <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, +- <&dmac1 0x2d>, <&dmac1 0x2e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 720>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e56000 { +- compatible = "renesas,scif-r8a7742", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e56000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 310>, +- <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, +- <&dmac1 0x2b>, <&dmac1 0x2c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 310>; +- status = "disabled"; +- }; +- +- hscif0: serial@e62c0000 { +- compatible = "renesas,hscif-r8a7742", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 717>, +- <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x39>, <&dmac0 0x3a>, +- <&dmac1 0x39>, <&dmac1 0x3a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 717>; +- status = "disabled"; +- }; +- +- hscif1: serial@e62c8000 { +- compatible = "renesas,hscif-r8a7742", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c8000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>, +- <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, +- <&dmac1 0x4d>, <&dmac1 0x4e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e20000 { +- compatible = "renesas,msiof-r8a7742", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e20000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 0>; +- dmas = <&dmac0 0x51>, <&dmac0 0x52>, +- <&dmac1 0x51>, <&dmac1 0x52>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6e10000 { +- compatible = "renesas,msiof-r8a7742", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e10000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 208>; +- dmas = <&dmac0 0x55>, <&dmac0 0x56>, +- <&dmac1 0x55>, <&dmac1 0x56>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 208>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6e00000 { +- compatible = "renesas,msiof-r8a7742", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e00000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 205>; +- dmas = <&dmac0 0x41>, <&dmac0 0x42>, +- <&dmac1 0x41>, <&dmac1 0x42>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 205>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof3: spi@e6c90000 { +- compatible = "renesas,msiof-r8a7742", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6c90000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 215>; +- dmas = <&dmac0 0x45>, <&dmac0 0x46>, +- <&dmac1 0x45>, <&dmac1 0x46>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 215>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- can0: can@e6e80000 { +- compatible = "renesas,can-r8a7742", +- "renesas,rcar-gen2-can"; +- reg = <0 0xe6e80000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>, +- <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- status = "disabled"; +- }; +- +- can1: can@e6e88000 { +- compatible = "renesas,can-r8a7742", +- "renesas,rcar-gen2-can"; +- reg = <0 0xe6e88000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>, +- <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- status = "disabled"; +- }; +- +- pwm0: pwm@e6e30000 { +- compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; +- reg = <0 0xe6e30000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm1: pwm@e6e31000 { +- compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; +- reg = <0 0xe6e31000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm2: pwm@e6e32000 { +- compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; +- reg = <0 0xe6e32000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm3: pwm@e6e33000 { +- compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; +- reg = <0 0xe6e33000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm4: pwm@e6e34000 { +- compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; +- reg = <0 0xe6e34000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm5: pwm@e6e35000 { +- compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; +- reg = <0 0xe6e35000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm6: pwm@e6e36000 { +- compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; +- reg = <0 0xe6e36000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a7742", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef0000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 811>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 811>; +- status = "disabled"; +- }; +- +- vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a7742", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef1000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 810>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 810>; +- status = "disabled"; +- }; +- +- vin2: video@e6ef2000 { +- compatible = "renesas,vin-r8a7742", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef2000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 809>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 809>; +- status = "disabled"; +- }; +- +- vin3: video@e6ef3000 { +- compatible = "renesas,vin-r8a7742", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef3000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 808>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 808>; +- status = "disabled"; +- }; +- +- rcar_sound: sound@ec500000 { +- /* +- * #sound-dai-cells is required +- * +- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; +- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; +- */ +- compatible = "renesas,rcar_sound-r8a7742", +- "renesas,rcar_sound-gen2"; +- reg = <0 0xec500000 0 0x1000>, /* SCU */ +- <0 0xec5a0000 0 0x100>, /* ADG */ +- <0 0xec540000 0 0x1000>, /* SSIU */ +- <0 0xec541000 0 0x280>, /* SSI */ +- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ +- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; +- +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, +- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, +- <&cpg CPG_CORE R8A7742_CLK_M2>; +- clock-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0", +- "src.9", "src.8", "src.7", "src.6", +- "src.5", "src.4", "src.3", "src.2", +- "src.1", "src.0", +- "ctu.0", "ctu.1", +- "mix.0", "mix.1", +- "dvc.0", "dvc.1", +- "clk_a", "clk_b", "clk_c", "clk_i"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 1005>, +- <&cpg 1006>, <&cpg 1007>, +- <&cpg 1008>, <&cpg 1009>, +- <&cpg 1010>, <&cpg 1011>, +- <&cpg 1012>, <&cpg 1013>, +- <&cpg 1014>, <&cpg 1015>; +- reset-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0"; +- +- status = "disabled"; +- +- rcar_sound,dvc { +- dvc0: dvc-0 { +- dmas = <&audma1 0xbc>; +- dma-names = "tx"; +- }; +- dvc1: dvc-1 { +- dmas = <&audma1 0xbe>; +- dma-names = "tx"; +- }; +- }; +- +- rcar_sound,mix { +- mix0: mix-0 { }; +- mix1: mix-1 { }; +- }; +- +- rcar_sound,ctu { +- ctu00: ctu-0 { }; +- ctu01: ctu-1 { }; +- ctu02: ctu-2 { }; +- ctu03: ctu-3 { }; +- ctu10: ctu-4 { }; +- ctu11: ctu-5 { }; +- ctu12: ctu-6 { }; +- ctu13: ctu-7 { }; +- }; +- +- rcar_sound,src { +- src0: src-0 { +- interrupts = ; +- dmas = <&audma0 0x85>, <&audma1 0x9a>; +- dma-names = "rx", "tx"; +- }; +- src1: src-1 { +- interrupts = ; +- dmas = <&audma0 0x87>, <&audma1 0x9c>; +- dma-names = "rx", "tx"; +- }; +- src2: src-2 { +- interrupts = ; +- dmas = <&audma0 0x89>, <&audma1 0x9e>; +- dma-names = "rx", "tx"; +- }; +- src3: src-3 { +- interrupts = ; +- dmas = <&audma0 0x8b>, <&audma1 0xa0>; +- dma-names = "rx", "tx"; +- }; +- src4: src-4 { +- interrupts = ; +- dmas = <&audma0 0x8d>, <&audma1 0xb0>; +- dma-names = "rx", "tx"; +- }; +- src5: src-5 { +- interrupts = ; +- dmas = <&audma0 0x8f>, <&audma1 0xb2>; +- dma-names = "rx", "tx"; +- }; +- src6: src-6 { +- interrupts = ; +- dmas = <&audma0 0x91>, <&audma1 0xb4>; +- dma-names = "rx", "tx"; +- }; +- src7: src-7 { +- interrupts = ; +- dmas = <&audma0 0x93>, <&audma1 0xb6>; +- dma-names = "rx", "tx"; +- }; +- src8: src-8 { +- interrupts = ; +- dmas = <&audma0 0x95>, <&audma1 0xb8>; +- dma-names = "rx", "tx"; +- }; +- src9: src-9 { +- interrupts = ; +- dmas = <&audma0 0x97>, <&audma1 0xba>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssi { +- ssi0: ssi-0 { +- interrupts = ; +- dmas = <&audma0 0x01>, <&audma1 0x02>, +- <&audma0 0x15>, <&audma1 0x16>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi1: ssi-1 { +- interrupts = ; +- dmas = <&audma0 0x03>, <&audma1 0x04>, +- <&audma0 0x49>, <&audma1 0x4a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi2: ssi-2 { +- interrupts = ; +- dmas = <&audma0 0x05>, <&audma1 0x06>, +- <&audma0 0x63>, <&audma1 0x64>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi3: ssi-3 { +- interrupts = ; +- dmas = <&audma0 0x07>, <&audma1 0x08>, +- <&audma0 0x6f>, <&audma1 0x70>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi4: ssi-4 { +- interrupts = ; +- dmas = <&audma0 0x09>, <&audma1 0x0a>, +- <&audma0 0x71>, <&audma1 0x72>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi5: ssi-5 { +- interrupts = ; +- dmas = <&audma0 0x0b>, <&audma1 0x0c>, +- <&audma0 0x73>, <&audma1 0x74>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi6: ssi-6 { +- interrupts = ; +- dmas = <&audma0 0x0d>, <&audma1 0x0e>, +- <&audma0 0x75>, <&audma1 0x76>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi7: ssi-7 { +- interrupts = ; +- dmas = <&audma0 0x0f>, <&audma1 0x10>, +- <&audma0 0x79>, <&audma1 0x7a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi8: ssi-8 { +- interrupts = ; +- dmas = <&audma0 0x11>, <&audma1 0x12>, +- <&audma0 0x7b>, <&audma1 0x7c>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi9: ssi-9 { +- interrupts = ; +- dmas = <&audma0 0x13>, <&audma1 0x14>, +- <&audma0 0x7d>, <&audma1 0x7e>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- }; +- }; +- +- audma0: dma-controller@ec700000 { +- compatible = "renesas,dmac-r8a7742", +- "renesas,rcar-dmac"; +- reg = <0 0xec700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12"; +- clocks = <&cpg CPG_MOD 502>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 502>; +- #dma-cells = <1>; +- dma-channels = <13>; +- }; +- +- audma1: dma-controller@ec720000 { +- compatible = "renesas,dmac-r8a7742", +- "renesas,rcar-dmac"; +- reg = <0 0xec720000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12"; +- clocks = <&cpg CPG_MOD 501>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 501>; +- #dma-cells = <1>; +- dma-channels = <13>; +- }; +- +- xhci: usb@ee000000 { +- compatible = "renesas,xhci-r8a7742", +- "renesas,rcar-gen2-xhci"; +- reg = <0 0xee000000 0 0xc00>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- phys = <&usb2 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- pci0: pci@ee090000 { +- compatible = "renesas,pci-r8a7742", +- "renesas,pci-rcar-gen2"; +- device_type = "pci"; +- reg = <0 0xee090000 0 0xc00>, +- <0 0xee080000 0 0x1100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- status = "disabled"; +- +- bus-range = <0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; +- interrupt-map-mask = <0xf800 0 0 0x7>; +- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, +- <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, +- <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; +- +- usb@1,0 { +- reg = <0x800 0 0 0 0>; +- phys = <&usb0 0>; +- phy-names = "usb"; +- }; +- +- usb@2,0 { +- reg = <0x1000 0 0 0 0>; +- phys = <&usb0 0>; +- phy-names = "usb"; +- }; +- }; +- +- pci1: pci@ee0b0000 { +- compatible = "renesas,pci-r8a7742", +- "renesas,pci-rcar-gen2"; +- device_type = "pci"; +- reg = <0 0xee0b0000 0 0xc00>, +- <0 0xee0a0000 0 0x1100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- status = "disabled"; +- +- bus-range = <1 1>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; +- interrupt-map-mask = <0xf800 0 0 0x7>; +- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, +- <0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, +- <0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- pci2: pci@ee0d0000 { +- compatible = "renesas,pci-r8a7742", +- "renesas,pci-rcar-gen2"; +- device_type = "pci"; +- clocks = <&cpg CPG_MOD 703>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- reg = <0 0xee0d0000 0 0xc00>, +- <0 0xee0c0000 0 0x1100>; +- interrupts = ; +- status = "disabled"; +- +- bus-range = <2 2>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; +- interrupt-map-mask = <0xf800 0 0 0x7>; +- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, +- <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, +- <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; +- +- usb@1,0 { +- reg = <0x20800 0 0 0 0>; +- phys = <&usb2 0>; +- phy-names = "usb"; +- }; +- +- usb@2,0 { +- reg = <0x21000 0 0 0 0>; +- phys = <&usb2 0>; +- phy-names = "usb"; +- }; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a7742", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee100000 0 0x328>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- dmas = <&dmac0 0xcd>, <&dmac0 0xce>, +- <&dmac1 0xcd>, <&dmac1 0xce>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <195000000>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ee120000 { +- compatible = "renesas,sdhi-r8a7742", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee120000 0 0x328>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 313>; +- dmas = <&dmac0 0xc9>, <&dmac0 0xca>, +- <&dmac1 0xc9>, <&dmac1 0xca>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <195000000>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 313>; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a7742", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee140000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 312>; +- dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, +- <&dmac1 0xc1>, <&dmac1 0xc2>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <97500000>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 312>; +- status = "disabled"; +- }; +- +- sdhi3: mmc@ee160000 { +- compatible = "renesas,sdhi-r8a7742", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee160000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 311>; +- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, +- <&dmac1 0xd3>, <&dmac1 0xd4>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <97500000>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 311>; +- status = "disabled"; +- }; +- +- mmcif0: mmc@ee200000 { +- compatible = "renesas,mmcif-r8a7742", +- "renesas,sh-mmcif"; +- reg = <0 0xee200000 0 0x80>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 315>; +- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, +- <&dmac1 0xd1>, <&dmac1 0xd2>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 315>; +- reg-io-width = <4>; +- status = "disabled"; +- max-frequency = <97500000>; +- }; +- +- mmcif1: mmc@ee220000 { +- compatible = "renesas,mmcif-r8a7742", +- "renesas,sh-mmcif"; +- reg = <0 0xee220000 0 0x80>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 305>; +- dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, +- <&dmac1 0xe1>, <&dmac1 0xe2>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 305>; +- reg-io-width = <4>; +- status = "disabled"; +- max-frequency = <97500000>; +- }; +- +- sata0: sata@ee300000 { +- compatible = "renesas,sata-r8a7742", +- "renesas,rcar-gen2-sata"; +- reg = <0 0xee300000 0 0x200000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 815>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 815>; +- status = "disabled"; +- }; +- +- sata1: sata@ee500000 { +- compatible = "renesas,sata-r8a7742", +- "renesas,rcar-gen2-sata"; +- reg = <0 0xee500000 0 0x200000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 814>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 814>; +- status = "disabled"; +- }; +- +- ether: ethernet@ee700000 { +- compatible = "renesas,ether-r8a7742", +- "renesas,rcar-gen2-ether"; +- reg = <0 0xee700000 0 0x400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 813>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 813>; +- phy-mode = "rmii"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1001000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, +- <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- pciec: pcie@fe000000 { +- compatible = "renesas,pcie-r8a7742", +- "renesas,pcie-rcar-gen2"; +- reg = <0 0xfe000000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, +- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, +- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, +- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, +- <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 319>; +- status = "disabled"; +- }; +- +- vsp@fe920000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe920000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 130>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 130>; +- }; +- +- vsp@fe928000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe928000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 131>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 131>; +- }; +- +- vsp@fe930000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe930000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 128>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 128>; +- }; +- +- vsp@fe938000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe938000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 127>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 127>; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a7742"; +- reg = <0 0xfeb00000 0 0x70000>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>; +- clock-names = "du.0", "du.1", "du.2"; +- resets = <&cpg 724>; +- reset-names = "du.0"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb: endpoint { +- }; +- }; +- port@1 { +- reg = <1>; +- du_out_lvds0: endpoint { +- remote-endpoint = <&lvds0_in>; +- }; +- }; +- port@2 { +- reg = <2>; +- du_out_lvds1: endpoint { +- remote-endpoint = <&lvds1_in>; +- }; +- }; +- }; +- }; +- +- lvds0: lvds@feb90000 { +- compatible = "renesas,r8a7742-lvds"; +- reg = <0 0xfeb90000 0 0x14>; +- clocks = <&cpg CPG_MOD 726>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 726>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds0_in: endpoint { +- remote-endpoint = <&du_out_lvds0>; +- }; +- }; +- port@1 { +- reg = <1>; +- lvds0_out: endpoint { +- }; +- }; +- }; +- }; +- +- lvds1: lvds@feb94000 { +- compatible = "renesas,r8a7742-lvds"; +- reg = <0 0xfeb94000 0 0x14>; +- clocks = <&cpg CPG_MOD 725>; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 725>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds1_in: endpoint { +- remote-endpoint = <&du_out_lvds1>; +- }; +- }; +- port@1 { +- reg = <1>; +- lvds1_out: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@ff000044 { +- compatible = "renesas,prr"; +- reg = <0 0xff000044 0 4>; +- }; +- +- cmt0: timer@ffca0000 { +- compatible = "renesas,r8a7742-cmt0", +- "renesas,rcar-gen2-cmt0"; +- reg = <0 0xffca0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a7742-cmt1", +- "renesas,rcar-gen2-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 329>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; +- resets = <&cpg 329>; +- status = "disabled"; +- }; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&thermal>; +- +- trips { +- cpu-crit { +- temperature = <95000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- cooling-maps { +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; +- }; +- +- /* External USB clock - can be overridden by the board */ +- usb_extal_clk: usb_extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <48000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7743-iwg20d-q7-dbcm-ca.dts b/scripts/dtc/include-prefixes/arm/r8a7743-iwg20d-q7-dbcm-ca.dts +deleted file mode 100644 +index 0d006aea99da..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7743-iwg20d-q7-dbcm-ca.dts ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the iWave-RZ/G1M Qseven board + camera daughter board +- * +- * Copyright (C) 2017 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a7743-iwg20m.dtsi" +-#include "iwg20d-q7-common.dtsi" +-#include "iwg20d-q7-dbcm-ca.dtsi" +- +-/ { +- model = "iW-RainboW-G20D-Q7 RZ/G1M based plus camera daughter board"; +- compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"; +-}; +- +-&pciec { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7743-iwg20d-q7.dts b/scripts/dtc/include-prefixes/arm/r8a7743-iwg20d-q7.dts +deleted file mode 100644 +index 498e223a5f93..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7743-iwg20d-q7.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the iWave-RZ/G1M Qseven board +- * +- * Copyright (C) 2017 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a7743-iwg20m.dtsi" +-#include "iwg20d-q7-common.dtsi" +- +-/ { +- model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M"; +- compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"; +-}; +- +-&pciec { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7743-iwg20m.dtsi b/scripts/dtc/include-prefixes/arm/r8a7743-iwg20m.dtsi +deleted file mode 100644 +index b3fee1d61c87..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7743-iwg20m.dtsi ++++ /dev/null +@@ -1,95 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the iWave-RZG1M-20M Qseven SOM +- * +- * Copyright (C) 2017 Renesas Electronics Corp. +- */ +- +-#include "r8a7743.dtsi" +-#include +- +-/ { +- compatible = "iwave,g20m", "renesas,r8a7743"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x20000000>; +- }; +- +- memory@200000000 { +- device_type = "memory"; +- reg = <2 0x00000000 0 0x20000000>; +- }; +- +- reg_3p3v: 3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&extal_clk { +- clock-frequency = <20000000>; +-}; +- +-&pfc { +- mmcif0_pins: mmc { +- groups = "mmc_data8_b", "mmc_ctrl"; +- function = "mmc"; +- }; +- +- qspi_pins: qspi { +- groups = "qspi_ctrl", "qspi_data2"; +- function = "qspi"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <3300>; +- }; +-}; +- +-&mmcif0 { +- pinctrl-0 = <&mmcif0_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <®_3p3v>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&qspi { +- pinctrl-0 = <&qspi_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- /* WARNING - This device contains the bootloader. Handle with care. */ +- flash: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "sst,sst25vf016b", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <1>; +- m25p,fast-read; +- spi-cpol; +- spi-cpha; +- }; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_3p3v>; +- cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7743-sk-rzg1m.dts b/scripts/dtc/include-prefixes/arm/r8a7743-sk-rzg1m.dts +deleted file mode 100644 +index 4ace117470e8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7743-sk-rzg1m.dts ++++ /dev/null +@@ -1,77 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the SK-RZG1M board +- * +- * Copyright (C) 2016-2017 Cogent Embedded, Inc. +- */ +- +-/dts-v1/; +-#include "r8a7743.dtsi" +- +-/ { +- model = "SK-RZG1M"; +- compatible = "renesas,sk-rzg1m", "renesas,r8a7743"; +- +- aliases { +- serial0 = &scif0; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x40000000>; +- }; +- +- memory@200000000 { +- device_type = "memory"; +- reg = <2 0x00000000 0 0x40000000>; +- }; +-}; +- +-&extal_clk { +- clock-frequency = <20000000>; +-}; +- +-&pfc { +- scif0_pins: scif0 { +- groups = "scif0_data_d"; +- function = "scif0"; +- }; +- +- ether_pins: ether { +- groups = "eth_link", "eth_mdio", "eth_rmii"; +- function = "eth"; +- }; +- +- phy1_pins: phy1 { +- groups = "intc_irq0"; +- function = "intc"; +- }; +-}; +- +-&scif0 { +- pinctrl-0 = <&scif0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-ðer { +- pinctrl-0 = <ðer_pins>, <&phy1_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <&phy1>; +- renesas,ether-link-active-low; +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- interrupt-parent = <&irqc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- micrel,led-mode = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7743.dtsi b/scripts/dtc/include-prefixes/arm/r8a7743.dtsi +deleted file mode 100644 +index 3502b5dcc04f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7743.dtsi ++++ /dev/null +@@ -1,1798 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the r8a7743 SoC +- * +- * Copyright (C) 2016-2017 Cogent Embedded Inc. +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r8a7743"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- /* +- * The external audio clocks are configured as 0 Hz fixed frequency +- * clocks by default. +- * Boards that provide audio clocks should override them. +- */ +- audio_clk_a: audio_clk_a { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_b: audio_clk_b { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_c: audio_clk_c { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* External CAN clock */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0>; +- clock-frequency = <1500000000>; +- clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; +- clock-latency = <300000>; /* 300 us */ +- power-domains = <&sysc R8A7743_PD_CA15_CPU0>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA15>; +- +- /* kHz - uV - OPPs unknown yet */ +- operating-points = <1500000 1000000>, +- <1312500 1000000>, +- <1125000 1000000>, +- < 937500 1000000>, +- < 750000 1000000>, +- < 375000 1000000>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <1>; +- clock-frequency = <1500000000>; +- clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; +- clock-latency = <300000>; /* 300 us */ +- power-domains = <&sysc R8A7743_PD_CA15_CPU1>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA15>; +- +- /* kHz - uV - OPPs unknown yet */ +- operating-points = <1500000 1000000>, +- <1312500 1000000>, +- <1125000 1000000>, +- < 937500 1000000>, +- < 750000 1000000>, +- < 375000 1000000>; +- }; +- +- L2_CA15: cache-controller-0 { +- compatible = "cache"; +- cache-unified; +- cache-level = <2>; +- power-domains = <&sysc R8A7743_PD_CA15_SCU>; +- }; +- }; +- +- /* External root clock */ +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- /* External PCIe clock - can be overridden by the board */ +- pcie_bus_clk: pcie_bus { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- pmu { +- compatible = "arm,cortex-a15-pmu"; +- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- /* External SCIF clock */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a7743-wdt", +- "renesas,rcar-gen2-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a7743", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a7743", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a7743", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a7743", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a7743", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a7743", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- gpio6: gpio@e6055400 { +- compatible = "renesas,gpio-r8a7743", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055400 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 192 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 905>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 905>; +- }; +- +- gpio7: gpio@e6055800 { +- compatible = "renesas,gpio-r8a7743", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055800 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 224 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 904>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 904>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a7743"; +- reg = <0 0xe6060000 0 0x250>; +- }; +- +- tpu: pwm@e60f0000 { +- compatible = "renesas,tpu-r8a7743", "renesas,tpu"; +- reg = <0 0xe60f0000 0 0x148>; +- clocks = <&cpg CPG_MOD 304>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 304>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a7743-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>, <&usb_extal_clk>; +- clock-names = "extal", "usb_extal"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- apmu@e6152000 { +- compatible = "renesas,r8a7743-apmu", "renesas,apmu"; +- reg = <0 0xe6152000 0 0x188>; +- cpus = <&cpu0>, <&cpu1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a7743-rst"; +- reg = <0 0xe6160000 0 0x100>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a7743-sysc"; +- reg = <0 0xe6180000 0 0x200>; +- #power-domain-cells = <1>; +- }; +- +- irqc: interrupt-controller@e61c0000 { +- compatible = "renesas,irqc-r8a7743", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- thermal: thermal@e61f0000 { +- compatible = "renesas,thermal-r8a7743", +- "renesas,rcar-gen2-thermal"; +- reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 522>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 522>; +- #thermal-sensor-cells = <0>; +- }; +- +- ipmmu_sy0: iommu@e6280000 { +- compatible = "renesas,ipmmu-r8a7743", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6280000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_sy1: iommu@e6290000 { +- compatible = "renesas,ipmmu-r8a7743", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6290000 0 0x1000>; +- interrupts = ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_ds: iommu@e6740000 { +- compatible = "renesas,ipmmu-r8a7743", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6740000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_mp: iommu@ec680000 { +- compatible = "renesas,ipmmu-r8a7743", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xec680000 0 0x1000>; +- interrupts = ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_mx: iommu@fe951000 { +- compatible = "renesas,ipmmu-r8a7743", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xfe951000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_gp: iommu@e62a0000 { +- compatible = "renesas,ipmmu-r8a7743", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe62a0000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- icram0: sram@e63a0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63a0000 0 0x12000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63a0000 0x12000>; +- }; +- +- icram1: sram@e63c0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63c0000 0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63c0000 0x1000>; +- +- smp-sram@0 { +- compatible = "renesas,smp-sram"; +- reg = <0 0x100>; +- }; +- }; +- +- icram2: sram@e6300000 { +- compatible = "mmio-sram"; +- reg = <0 0xe6300000 0 0x40000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe6300000 0x40000>; +- }; +- +- /* The memory map in the User's Manual maps the cores to +- * bus numbers +- */ +- i2c0: i2c@e6508000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7743", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6518000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7743", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6518000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6530000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7743", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6530000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e6540000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7743", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6540000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e6520000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7743", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6520000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 927>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 927>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c5: i2c@e6528000 { +- /* doesn't need pinmux */ +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7743", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6528000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 925>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 925>; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- iic0: i2c@e6500000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7743", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe6500000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 318>; +- dmas = <&dmac0 0x61>, <&dmac0 0x62>, +- <&dmac1 0x61>, <&dmac1 0x62>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 318>; +- status = "disabled"; +- }; +- +- iic1: i2c@e6510000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7743", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe6510000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 323>; +- dmas = <&dmac0 0x65>, <&dmac0 0x66>, +- <&dmac1 0x65>, <&dmac1 0x66>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 323>; +- status = "disabled"; +- }; +- +- iic3: i2c@e60b0000 { +- /* doesn't need pinmux */ +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7743", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe60b0000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 926>; +- dmas = <&dmac0 0x77>, <&dmac0 0x78>, +- <&dmac1 0x77>, <&dmac1 0x78>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 926>; +- status = "disabled"; +- }; +- +- hsusb: usb@e6590000 { +- compatible = "renesas,usbhs-r8a7743", +- "renesas,rcar-gen2-usbhs"; +- reg = <0 0xe6590000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 704>; +- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, +- <&usb_dmac1 0>, <&usb_dmac1 1>; +- dma-names = "ch0", "ch1", "ch2", "ch3"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 704>; +- renesas,buswait = <4>; +- phys = <&usb0 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usbphy: usb-phy@e6590100 { +- compatible = "renesas,usb-phy-r8a7743", +- "renesas,rcar-gen2-usb-phy"; +- reg = <0 0xe6590100 0 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cpg CPG_MOD 704>; +- clock-names = "usbhs"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 704>; +- status = "disabled"; +- +- usb0: usb-channel@0 { +- reg = <0>; +- #phy-cells = <1>; +- }; +- usb2: usb-channel@2 { +- reg = <2>; +- #phy-cells = <1>; +- }; +- }; +- +- usb_dmac0: dma-controller@e65a0000 { +- compatible = "renesas,r8a7743-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65a0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 330>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 330>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac1: dma-controller@e65b0000 { +- compatible = "renesas,r8a7743-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65b0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 331>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 331>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a7743", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- dmac1: dma-controller@e6720000 { +- compatible = "renesas,dmac-r8a7743", +- "renesas,rcar-dmac"; +- reg = <0 0xe6720000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a7743", +- "renesas,etheravb-rcar-gen2"; +- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- qspi: spi@e6b10000 { +- compatible = "renesas,qspi-r8a7743", "renesas,qspi"; +- reg = <0 0xe6b10000 0 0x2c>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 917>; +- dmas = <&dmac0 0x17>, <&dmac0 0x18>, +- <&dmac1 0x17>, <&dmac1 0x18>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- resets = <&cpg 917>; +- status = "disabled"; +- }; +- +- scifa0: serial@e6c40000 { +- compatible = "renesas,scifa-r8a7743", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c40000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>; +- clock-names = "fck"; +- dmas = <&dmac0 0x21>, <&dmac0 0x22>, +- <&dmac1 0x21>, <&dmac1 0x22>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scifa1: serial@e6c50000 { +- compatible = "renesas,scifa-r8a7743", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c50000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>; +- clock-names = "fck"; +- dmas = <&dmac0 0x25>, <&dmac0 0x26>, +- <&dmac1 0x25>, <&dmac1 0x26>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- scifa2: serial@e6c60000 { +- compatible = "renesas,scifa-r8a7743", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c60000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 202>; +- clock-names = "fck"; +- dmas = <&dmac0 0x27>, <&dmac0 0x28>, +- <&dmac1 0x27>, <&dmac1 0x28>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 202>; +- status = "disabled"; +- }; +- +- scifa3: serial@e6c70000 { +- compatible = "renesas,scifa-r8a7743", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c70000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1106>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, +- <&dmac1 0x1b>, <&dmac1 0x1c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 1106>; +- status = "disabled"; +- }; +- +- scifa4: serial@e6c78000 { +- compatible = "renesas,scifa-r8a7743", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c78000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1107>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1f>, <&dmac0 0x20>, +- <&dmac1 0x1f>, <&dmac1 0x20>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 1107>; +- status = "disabled"; +- }; +- +- scifa5: serial@e6c80000 { +- compatible = "renesas,scifa-r8a7743", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c80000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1108>; +- clock-names = "fck"; +- dmas = <&dmac0 0x23>, <&dmac0 0x24>, +- <&dmac1 0x23>, <&dmac1 0x24>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 1108>; +- status = "disabled"; +- }; +- +- scifb0: serial@e6c20000 { +- compatible = "renesas,scifb-r8a7743", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6c20000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>; +- clock-names = "fck"; +- dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, +- <&dmac1 0x3d>, <&dmac1 0x3e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scifb1: serial@e6c30000 { +- compatible = "renesas,scifb-r8a7743", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6c30000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>; +- clock-names = "fck"; +- dmas = <&dmac0 0x19>, <&dmac0 0x1a>, +- <&dmac1 0x19>, <&dmac1 0x1a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scifb2: serial@e6ce0000 { +- compatible = "renesas,scifb-r8a7743", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6ce0000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 216>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, +- <&dmac1 0x1d>, <&dmac1 0x1e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 216>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a7743", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e60000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 721>, +- <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x29>, <&dmac0 0x2a>, +- <&dmac1 0x29>, <&dmac1 0x2a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 721>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a7743", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e68000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 720>, +- <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, +- <&dmac1 0x2d>, <&dmac1 0x2e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 720>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e58000 { +- compatible = "renesas,scif-r8a7743", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e58000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 719>, +- <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, +- <&dmac1 0x2b>, <&dmac1 0x2c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 719>; +- status = "disabled"; +- }; +- +- scif3: serial@e6ea8000 { +- compatible = "renesas,scif-r8a7743", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ea8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 718>, +- <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2f>, <&dmac0 0x30>, +- <&dmac1 0x2f>, <&dmac1 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 718>; +- status = "disabled"; +- }; +- +- scif4: serial@e6ee0000 { +- compatible = "renesas,scif-r8a7743", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ee0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 715>, +- <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, +- <&dmac1 0xfb>, <&dmac1 0xfc>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 715>; +- status = "disabled"; +- }; +- +- scif5: serial@e6ee8000 { +- compatible = "renesas,scif-r8a7743", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ee8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 714>, +- <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, +- <&dmac1 0xfd>, <&dmac1 0xfe>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 714>; +- status = "disabled"; +- }; +- +- hscif0: serial@e62c0000 { +- compatible = "renesas,hscif-r8a7743", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 717>, +- <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x39>, <&dmac0 0x3a>, +- <&dmac1 0x39>, <&dmac1 0x3a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 717>; +- status = "disabled"; +- }; +- +- hscif1: serial@e62c8000 { +- compatible = "renesas,hscif-r8a7743", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c8000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>, +- <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, +- <&dmac1 0x4d>, <&dmac1 0x4e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- }; +- +- hscif2: serial@e62d0000 { +- compatible = "renesas,hscif-r8a7743", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62d0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 713>, +- <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, +- <&dmac1 0x3b>, <&dmac1 0x3c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 713>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e20000 { +- compatible = "renesas,msiof-r8a7743", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e20000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 000>; +- dmas = <&dmac0 0x51>, <&dmac0 0x52>, +- <&dmac1 0x51>, <&dmac1 0x52>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- #address-cells = <1>; +- #size-cells = <0>; +- resets = <&cpg 000>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6e10000 { +- compatible = "renesas,msiof-r8a7743", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e10000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 208>; +- dmas = <&dmac0 0x55>, <&dmac0 0x56>, +- <&dmac1 0x55>, <&dmac1 0x56>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- #address-cells = <1>; +- #size-cells = <0>; +- resets = <&cpg 208>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6e00000 { +- compatible = "renesas,msiof-r8a7743", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e00000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 205>; +- dmas = <&dmac0 0x41>, <&dmac0 0x42>, +- <&dmac1 0x41>, <&dmac1 0x42>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- #address-cells = <1>; +- #size-cells = <0>; +- resets = <&cpg 205>; +- status = "disabled"; +- }; +- +- pwm0: pwm@e6e30000 { +- compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; +- reg = <0 0xe6e30000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm1: pwm@e6e31000 { +- compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; +- reg = <0 0xe6e31000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm2: pwm@e6e32000 { +- compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; +- reg = <0 0xe6e32000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm3: pwm@e6e33000 { +- compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; +- reg = <0 0xe6e33000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm4: pwm@e6e34000 { +- compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; +- reg = <0 0xe6e34000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm5: pwm@e6e35000 { +- compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; +- reg = <0 0xe6e35000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm6: pwm@e6e36000 { +- compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; +- reg = <0 0xe6e36000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- can0: can@e6e80000 { +- compatible = "renesas,can-r8a7743", +- "renesas,rcar-gen2-can"; +- reg = <0 0xe6e80000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>, +- <&cpg CPG_CORE R8A7743_CLK_RCAN>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- status = "disabled"; +- }; +- +- can1: can@e6e88000 { +- compatible = "renesas,can-r8a7743", +- "renesas,rcar-gen2-can"; +- reg = <0 0xe6e88000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>, +- <&cpg CPG_CORE R8A7743_CLK_RCAN>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- status = "disabled"; +- }; +- +- vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a7743", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef0000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 811>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 811>; +- status = "disabled"; +- }; +- +- vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a7743", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef1000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 810>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 810>; +- status = "disabled"; +- }; +- +- vin2: video@e6ef2000 { +- compatible = "renesas,vin-r8a7743", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef2000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 809>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 809>; +- status = "disabled"; +- }; +- +- rcar_sound: sound@ec500000 { +- /* +- * #sound-dai-cells is required +- * +- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; +- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; +- */ +- compatible = "renesas,rcar_sound-r8a7743", +- "renesas,rcar_sound-gen2"; +- reg = <0 0xec500000 0 0x1000>, /* SCU */ +- <0 0xec5a0000 0 0x100>, /* ADG */ +- <0 0xec540000 0 0x1000>, /* SSIU */ +- <0 0xec541000 0 0x280>, /* SSI */ +- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ +- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; +- +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, +- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, +- <&cpg CPG_CORE R8A7743_CLK_M2>; +- clock-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", +- "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", +- "src.9", "src.8", "src.7", "src.6", "src.5", +- "src.4", "src.3", "src.2", "src.1", "src.0", +- "ctu.0", "ctu.1", +- "mix.0", "mix.1", +- "dvc.0", "dvc.1", +- "clk_a", "clk_b", "clk_c", "clk_i"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 1005>, +- <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, +- <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, +- <&cpg 1014>, <&cpg 1015>; +- reset-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", +- "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; +- status = "disabled"; +- +- rcar_sound,dvc { +- dvc0: dvc-0 { +- dmas = <&audma1 0xbc>; +- dma-names = "tx"; +- }; +- dvc1: dvc-1 { +- dmas = <&audma1 0xbe>; +- dma-names = "tx"; +- }; +- }; +- +- rcar_sound,mix { +- mix0: mix-0 { }; +- mix1: mix-1 { }; +- }; +- +- rcar_sound,ctu { +- ctu00: ctu-0 { }; +- ctu01: ctu-1 { }; +- ctu02: ctu-2 { }; +- ctu03: ctu-3 { }; +- ctu10: ctu-4 { }; +- ctu11: ctu-5 { }; +- ctu12: ctu-6 { }; +- ctu13: ctu-7 { }; +- }; +- +- rcar_sound,src { +- src0: src-0 { +- interrupts = ; +- dmas = <&audma0 0x85>, <&audma1 0x9a>; +- dma-names = "rx", "tx"; +- }; +- src1: src-1 { +- interrupts = ; +- dmas = <&audma0 0x87>, <&audma1 0x9c>; +- dma-names = "rx", "tx"; +- }; +- src2: src-2 { +- interrupts = ; +- dmas = <&audma0 0x89>, <&audma1 0x9e>; +- dma-names = "rx", "tx"; +- }; +- src3: src-3 { +- interrupts = ; +- dmas = <&audma0 0x8b>, <&audma1 0xa0>; +- dma-names = "rx", "tx"; +- }; +- src4: src-4 { +- interrupts = ; +- dmas = <&audma0 0x8d>, <&audma1 0xb0>; +- dma-names = "rx", "tx"; +- }; +- src5: src-5 { +- interrupts = ; +- dmas = <&audma0 0x8f>, <&audma1 0xb2>; +- dma-names = "rx", "tx"; +- }; +- src6: src-6 { +- interrupts = ; +- dmas = <&audma0 0x91>, <&audma1 0xb4>; +- dma-names = "rx", "tx"; +- }; +- src7: src-7 { +- interrupts = ; +- dmas = <&audma0 0x93>, <&audma1 0xb6>; +- dma-names = "rx", "tx"; +- }; +- src8: src-8 { +- interrupts = ; +- dmas = <&audma0 0x95>, <&audma1 0xb8>; +- dma-names = "rx", "tx"; +- }; +- src9: src-9 { +- interrupts = ; +- dmas = <&audma0 0x97>, <&audma1 0xba>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssi { +- ssi0: ssi-0 { +- interrupts = ; +- dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi1: ssi-1 { +- interrupts = ; +- dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi2: ssi-2 { +- interrupts = ; +- dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi3: ssi-3 { +- interrupts = ; +- dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi4: ssi-4 { +- interrupts = ; +- dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi5: ssi-5 { +- interrupts = ; +- dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi6: ssi-6 { +- interrupts = ; +- dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi7: ssi-7 { +- interrupts = ; +- dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi8: ssi-8 { +- interrupts = ; +- dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi9: ssi-9 { +- interrupts = ; +- dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- }; +- }; +- +- audma0: dma-controller@ec700000 { +- compatible = "renesas,dmac-r8a7743", +- "renesas,rcar-dmac"; +- reg = <0 0xec700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12"; +- clocks = <&cpg CPG_MOD 502>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 502>; +- #dma-cells = <1>; +- dma-channels = <13>; +- }; +- +- audma1: dma-controller@ec720000 { +- compatible = "renesas,dmac-r8a7743", +- "renesas,rcar-dmac"; +- reg = <0 0xec720000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12"; +- clocks = <&cpg CPG_MOD 501>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 501>; +- #dma-cells = <1>; +- dma-channels = <13>; +- }; +- +- /* +- * pci1 and xhci share the same phy, therefore only one of them +- * can be active at any one time. If both of them are enabled, +- * a race condition will determine who'll control the phy. +- * A firmware file is needed by the xhci driver in order for +- * USB 3.0 to work properly. +- */ +- xhci: usb@ee000000 { +- compatible = "renesas,xhci-r8a7743", +- "renesas,rcar-gen2-xhci"; +- reg = <0 0xee000000 0 0xc00>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- phys = <&usb2 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- pci0: pci@ee090000 { +- compatible = "renesas,pci-r8a7743", +- "renesas,pci-rcar-gen2"; +- device_type = "pci"; +- reg = <0 0xee090000 0 0xc00>, +- <0 0xee080000 0 0x1100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- status = "disabled"; +- +- bus-range = <0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; +- interrupt-map-mask = <0xf800 0 0 0x7>; +- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, +- <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, +- <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; +- +- usb@1,0 { +- reg = <0x800 0 0 0 0>; +- phys = <&usb0 0>; +- phy-names = "usb"; +- }; +- +- usb@2,0 { +- reg = <0x1000 0 0 0 0>; +- phys = <&usb0 0>; +- phy-names = "usb"; +- }; +- }; +- +- pci1: pci@ee0d0000 { +- compatible = "renesas,pci-r8a7743", +- "renesas,pci-rcar-gen2"; +- device_type = "pci"; +- reg = <0 0xee0d0000 0 0xc00>, +- <0 0xee0c0000 0 0x1100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- status = "disabled"; +- +- bus-range = <1 1>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; +- interrupt-map-mask = <0xf800 0 0 0x7>; +- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, +- <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, +- <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; +- +- usb@1,0 { +- reg = <0x10800 0 0 0 0>; +- phys = <&usb2 0>; +- phy-names = "usb"; +- }; +- +- usb@2,0 { +- reg = <0x11000 0 0 0 0>; +- phys = <&usb2 0>; +- phy-names = "usb"; +- }; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a7743", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee100000 0 0x328>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- dmas = <&dmac0 0xcd>, <&dmac0 0xce>, +- <&dmac1 0xcd>, <&dmac1 0xce>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <195000000>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a7743", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee140000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 312>; +- dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, +- <&dmac1 0xc1>, <&dmac1 0xc2>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <97500000>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 312>; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ee160000 { +- compatible = "renesas,sdhi-r8a7743", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee160000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 311>; +- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, +- <&dmac1 0xd3>, <&dmac1 0xd4>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <97500000>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 311>; +- status = "disabled"; +- }; +- +- mmcif0: mmc@ee200000 { +- compatible = "renesas,mmcif-r8a7743", +- "renesas,sh-mmcif"; +- reg = <0 0xee200000 0 0x80>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 315>; +- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, +- <&dmac1 0xd1>, <&dmac1 0xd2>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 315>; +- reg-io-width = <4>; +- max-frequency = <97500000>; +- status = "disabled"; +- }; +- +- ether: ethernet@ee700000 { +- compatible = "renesas,ether-r8a7743", +- "renesas,rcar-gen2-ether"; +- reg = <0 0xee700000 0 0x400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 813>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 813>; +- phy-mode = "rmii"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1001000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, +- <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- pciec: pcie@fe000000 { +- compatible = "renesas,pcie-r8a7743", +- "renesas,pcie-rcar-gen2"; +- reg = <0 0xfe000000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, +- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, +- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, +- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, +- <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 319>; +- status = "disabled"; +- }; +- +- vsp@fe928000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe928000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 131>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 131>; +- }; +- +- vsp@fe930000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe930000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 128>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 128>; +- }; +- +- vsp@fe938000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe938000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 127>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 127>; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a7743"; +- reg = <0 0xfeb00000 0 0x40000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; +- clock-names = "du.0", "du.1"; +- resets = <&cpg 724>; +- reset-names = "du.0"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb: endpoint { +- }; +- }; +- port@1 { +- reg = <1>; +- du_out_lvds0: endpoint { +- remote-endpoint = <&lvds0_in>; +- }; +- }; +- }; +- }; +- +- lvds0: lvds@feb90000 { +- compatible = "renesas,r8a7743-lvds"; +- reg = <0 0xfeb90000 0 0x1c>; +- clocks = <&cpg CPG_MOD 726>; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 726>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds0_in: endpoint { +- remote-endpoint = <&du_out_lvds0>; +- }; +- }; +- port@1 { +- reg = <1>; +- lvds0_out: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@ff000044 { +- compatible = "renesas,prr"; +- reg = <0 0xff000044 0 4>; +- }; +- +- cmt0: timer@ffca0000 { +- compatible = "renesas,r8a7743-cmt0", +- "renesas,rcar-gen2-cmt0"; +- reg = <0 0xffca0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a7743-cmt1", +- "renesas,rcar-gen2-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 329>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; +- resets = <&cpg 329>; +- status = "disabled"; +- }; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&thermal>; +- +- trips { +- cpu-crit { +- temperature = <95000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +- }; +- +- /* External USB clock - can be overridden by the board */ +- usb_extal_clk: usb_extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <48000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7744-iwg20d-q7-dbcm-ca.dts b/scripts/dtc/include-prefixes/arm/r8a7744-iwg20d-q7-dbcm-ca.dts +deleted file mode 100644 +index 3e58c2e92e03..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7744-iwg20d-q7-dbcm-ca.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the iWave Systems RZ/G1N Qseven board development +- * platform with camera daughter board +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a7744-iwg20m.dtsi" +-#include "iwg20d-q7-common.dtsi" +-#include "iwg20d-q7-dbcm-ca.dtsi" +- +-/ { +- model = "iWave Systems RZ/G1N Qseven development platform with camera add-on"; +- compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7744-iwg20d-q7.dts b/scripts/dtc/include-prefixes/arm/r8a7744-iwg20d-q7.dts +deleted file mode 100644 +index 1fdac528f274..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7744-iwg20d-q7.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the iWave-RZ/G1N Qseven board +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a7744-iwg20m.dtsi" +-#include "iwg20d-q7-common.dtsi" +- +-/ { +- model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1N"; +- compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7744-iwg20m.dtsi b/scripts/dtc/include-prefixes/arm/r8a7744-iwg20m.dtsi +deleted file mode 100644 +index 82ee3c1140ef..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7744-iwg20m.dtsi ++++ /dev/null +@@ -1,90 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the iWave RZ/G1N Qseven SOM +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +- +-#include "r8a7744.dtsi" +-#include +- +-/ { +- compatible = "iwave,g20m", "renesas,r8a7744"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x40000000>; +- }; +- +- reg_3p3v: 3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&extal_clk { +- clock-frequency = <20000000>; +-}; +- +-&pfc { +- mmcif0_pins: mmc { +- groups = "mmc_data8_b", "mmc_ctrl"; +- function = "mmc"; +- }; +- +- qspi_pins: qspi { +- groups = "qspi_ctrl", "qspi_data2"; +- function = "qspi"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <3300>; +- }; +-}; +- +-&mmcif0 { +- pinctrl-0 = <&mmcif0_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <®_3p3v>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&qspi { +- pinctrl-0 = <&qspi_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- /* WARNING - This device contains the bootloader. Handle with care. */ +- flash: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- spi-tx-bus-width = <2>; +- spi-rx-bus-width = <2>; +- m25p,fast-read; +- spi-cpol; +- spi-cpha; +- }; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_3p3v>; +- cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7744.dtsi b/scripts/dtc/include-prefixes/arm/r8a7744.dtsi +deleted file mode 100644 +index f5d4b8b85b6d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7744.dtsi ++++ /dev/null +@@ -1,1784 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the r8a7744 SoC +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r8a7744"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- /* +- * The external audio clocks are configured as 0 Hz fixed frequency +- * clocks by default. +- * Boards that provide audio clocks should override them. +- */ +- audio_clk_a: audio_clk_a { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_b: audio_clk_b { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_c: audio_clk_c { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* External CAN clock */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0>; +- clock-frequency = <1500000000>; +- clocks = <&cpg CPG_CORE R8A7744_CLK_Z>; +- clock-latency = <300000>; /* 300 us */ +- power-domains = <&sysc R8A7744_PD_CA15_CPU0>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA15>; +- +- /* kHz - uV - OPPs unknown yet */ +- operating-points = <1500000 1000000>, +- <1312500 1000000>, +- <1125000 1000000>, +- < 937500 1000000>, +- < 750000 1000000>, +- < 375000 1000000>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <1>; +- clock-frequency = <1500000000>; +- clocks = <&cpg CPG_CORE R8A7744_CLK_Z>; +- clock-latency = <300000>; /* 300 us */ +- power-domains = <&sysc R8A7744_PD_CA15_CPU1>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA15>; +- +- /* kHz - uV - OPPs unknown yet */ +- operating-points = <1500000 1000000>, +- <1312500 1000000>, +- <1125000 1000000>, +- < 937500 1000000>, +- < 750000 1000000>, +- < 375000 1000000>; +- }; +- +- L2_CA15: cache-controller-0 { +- compatible = "cache"; +- cache-unified; +- cache-level = <2>; +- power-domains = <&sysc R8A7744_PD_CA15_SCU>; +- }; +- }; +- +- /* External root clock */ +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- /* External PCIe clock - can be overridden by the board */ +- pcie_bus_clk: pcie_bus { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- pmu { +- compatible = "arm,cortex-a15-pmu"; +- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- /* External SCIF clock */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a7744-wdt", +- "renesas,rcar-gen2-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a7744", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a7744", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a7744", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a7744", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a7744", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a7744", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- gpio6: gpio@e6055400 { +- compatible = "renesas,gpio-r8a7744", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055400 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 192 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 905>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 905>; +- }; +- +- gpio7: gpio@e6055800 { +- compatible = "renesas,gpio-r8a7744", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055800 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 224 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 904>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 904>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a7744"; +- reg = <0 0xe6060000 0 0x250>; +- }; +- +- tpu: pwm@e60f0000 { +- compatible = "renesas,tpu-r8a7744", "renesas,tpu"; +- reg = <0 0xe60f0000 0 0x148>; +- clocks = <&cpg CPG_MOD 304>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 304>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a7744-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>, <&usb_extal_clk>; +- clock-names = "extal", "usb_extal"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- apmu@e6152000 { +- compatible = "renesas,r8a7744-apmu", "renesas,apmu"; +- reg = <0 0xe6152000 0 0x188>; +- cpus = <&cpu0>, <&cpu1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a7744-rst"; +- reg = <0 0xe6160000 0 0x100>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a7744-sysc"; +- reg = <0 0xe6180000 0 0x200>; +- #power-domain-cells = <1>; +- }; +- +- irqc: interrupt-controller@e61c0000 { +- compatible = "renesas,irqc-r8a7744", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- thermal: thermal@e61f0000 { +- compatible = "renesas,thermal-r8a7744", +- "renesas,rcar-gen2-thermal"; +- reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 522>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 522>; +- #thermal-sensor-cells = <0>; +- }; +- +- ipmmu_sy0: iommu@e6280000 { +- compatible = "renesas,ipmmu-r8a7744", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6280000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_sy1: iommu@e6290000 { +- compatible = "renesas,ipmmu-r8a7744", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6290000 0 0x1000>; +- interrupts = ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_ds: iommu@e6740000 { +- compatible = "renesas,ipmmu-r8a7744", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6740000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_mp: iommu@ec680000 { +- compatible = "renesas,ipmmu-r8a7744", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xec680000 0 0x1000>; +- interrupts = ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_mx: iommu@fe951000 { +- compatible = "renesas,ipmmu-r8a7744", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xfe951000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_gp: iommu@e62a0000 { +- compatible = "renesas,ipmmu-r8a7744", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe62a0000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- icram0: sram@e63a0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63a0000 0 0x12000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63a0000 0x12000>; +- }; +- +- icram1: sram@e63c0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63c0000 0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63c0000 0x1000>; +- +- smp-sram@0 { +- compatible = "renesas,smp-sram"; +- reg = <0 0x100>; +- }; +- }; +- +- icram2: sram@e6300000 { +- compatible = "mmio-sram"; +- reg = <0 0xe6300000 0 0x40000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe6300000 0x40000>; +- }; +- +- /* The memory map in the User's Manual maps the cores to +- * bus numbers +- */ +- i2c0: i2c@e6508000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7744", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6518000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7744", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6518000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6530000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7744", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6530000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e6540000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7744", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6540000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e6520000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7744", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6520000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 927>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 927>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c5: i2c@e6528000 { +- /* doesn't need pinmux */ +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7744", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6528000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 925>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 925>; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- iic0: i2c@e6500000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7744", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe6500000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 318>; +- dmas = <&dmac0 0x61>, <&dmac0 0x62>, +- <&dmac1 0x61>, <&dmac1 0x62>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 318>; +- status = "disabled"; +- }; +- +- iic1: i2c@e6510000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7744", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe6510000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 323>; +- dmas = <&dmac0 0x65>, <&dmac0 0x66>, +- <&dmac1 0x65>, <&dmac1 0x66>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 323>; +- status = "disabled"; +- }; +- +- iic3: i2c@e60b0000 { +- /* doesn't need pinmux */ +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7744", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe60b0000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 926>; +- dmas = <&dmac0 0x77>, <&dmac0 0x78>, +- <&dmac1 0x77>, <&dmac1 0x78>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 926>; +- status = "disabled"; +- }; +- +- hsusb: usb@e6590000 { +- compatible = "renesas,usbhs-r8a7744", +- "renesas,rcar-gen2-usbhs"; +- reg = <0 0xe6590000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 704>; +- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, +- <&usb_dmac1 0>, <&usb_dmac1 1>; +- dma-names = "ch0", "ch1", "ch2", "ch3"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 704>; +- renesas,buswait = <4>; +- phys = <&usb0 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usbphy: usb-phy@e6590100 { +- compatible = "renesas,usb-phy-r8a7744", +- "renesas,rcar-gen2-usb-phy"; +- reg = <0 0xe6590100 0 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cpg CPG_MOD 704>; +- clock-names = "usbhs"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 704>; +- status = "disabled"; +- +- usb0: usb-channel@0 { +- reg = <0>; +- #phy-cells = <1>; +- }; +- usb2: usb-channel@2 { +- reg = <2>; +- #phy-cells = <1>; +- }; +- }; +- +- usb_dmac0: dma-controller@e65a0000 { +- compatible = "renesas,r8a7744-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65a0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 330>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 330>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac1: dma-controller@e65b0000 { +- compatible = "renesas,r8a7744-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65b0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 331>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 331>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a7744", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- dmac1: dma-controller@e6720000 { +- compatible = "renesas,dmac-r8a7744", +- "renesas,rcar-dmac"; +- reg = <0 0xe6720000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a7744", +- "renesas,etheravb-rcar-gen2"; +- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- qspi: spi@e6b10000 { +- compatible = "renesas,qspi-r8a7744", "renesas,qspi"; +- reg = <0 0xe6b10000 0 0x2c>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 917>; +- dmas = <&dmac0 0x17>, <&dmac0 0x18>, +- <&dmac1 0x17>, <&dmac1 0x18>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- resets = <&cpg 917>; +- status = "disabled"; +- }; +- +- scifa0: serial@e6c40000 { +- compatible = "renesas,scifa-r8a7744", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c40000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>; +- clock-names = "fck"; +- dmas = <&dmac0 0x21>, <&dmac0 0x22>, +- <&dmac1 0x21>, <&dmac1 0x22>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scifa1: serial@e6c50000 { +- compatible = "renesas,scifa-r8a7744", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c50000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>; +- clock-names = "fck"; +- dmas = <&dmac0 0x25>, <&dmac0 0x26>, +- <&dmac1 0x25>, <&dmac1 0x26>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- scifa2: serial@e6c60000 { +- compatible = "renesas,scifa-r8a7744", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c60000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 202>; +- clock-names = "fck"; +- dmas = <&dmac0 0x27>, <&dmac0 0x28>, +- <&dmac1 0x27>, <&dmac1 0x28>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 202>; +- status = "disabled"; +- }; +- +- scifa3: serial@e6c70000 { +- compatible = "renesas,scifa-r8a7744", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c70000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1106>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, +- <&dmac1 0x1b>, <&dmac1 0x1c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 1106>; +- status = "disabled"; +- }; +- +- scifa4: serial@e6c78000 { +- compatible = "renesas,scifa-r8a7744", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c78000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1107>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1f>, <&dmac0 0x20>, +- <&dmac1 0x1f>, <&dmac1 0x20>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 1107>; +- status = "disabled"; +- }; +- +- scifa5: serial@e6c80000 { +- compatible = "renesas,scifa-r8a7744", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c80000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1108>; +- clock-names = "fck"; +- dmas = <&dmac0 0x23>, <&dmac0 0x24>, +- <&dmac1 0x23>, <&dmac1 0x24>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 1108>; +- status = "disabled"; +- }; +- +- scifb0: serial@e6c20000 { +- compatible = "renesas,scifb-r8a7744", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6c20000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>; +- clock-names = "fck"; +- dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, +- <&dmac1 0x3d>, <&dmac1 0x3e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scifb1: serial@e6c30000 { +- compatible = "renesas,scifb-r8a7744", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6c30000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>; +- clock-names = "fck"; +- dmas = <&dmac0 0x19>, <&dmac0 0x1a>, +- <&dmac1 0x19>, <&dmac1 0x1a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scifb2: serial@e6ce0000 { +- compatible = "renesas,scifb-r8a7744", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6ce0000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 216>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, +- <&dmac1 0x1d>, <&dmac1 0x1e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 216>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a7744", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e60000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 721>, +- <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x29>, <&dmac0 0x2a>, +- <&dmac1 0x29>, <&dmac1 0x2a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 721>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a7744", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e68000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 720>, +- <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, +- <&dmac1 0x2d>, <&dmac1 0x2e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 720>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e58000 { +- compatible = "renesas,scif-r8a7744", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e58000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 719>, +- <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, +- <&dmac1 0x2b>, <&dmac1 0x2c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 719>; +- status = "disabled"; +- }; +- +- scif3: serial@e6ea8000 { +- compatible = "renesas,scif-r8a7744", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ea8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 718>, +- <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2f>, <&dmac0 0x30>, +- <&dmac1 0x2f>, <&dmac1 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 718>; +- status = "disabled"; +- }; +- +- scif4: serial@e6ee0000 { +- compatible = "renesas,scif-r8a7744", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ee0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 715>, +- <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, +- <&dmac1 0xfb>, <&dmac1 0xfc>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 715>; +- status = "disabled"; +- }; +- +- scif5: serial@e6ee8000 { +- compatible = "renesas,scif-r8a7744", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ee8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 714>, +- <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, +- <&dmac1 0xfd>, <&dmac1 0xfe>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 714>; +- status = "disabled"; +- }; +- +- hscif0: serial@e62c0000 { +- compatible = "renesas,hscif-r8a7744", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 717>, +- <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x39>, <&dmac0 0x3a>, +- <&dmac1 0x39>, <&dmac1 0x3a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 717>; +- status = "disabled"; +- }; +- +- hscif1: serial@e62c8000 { +- compatible = "renesas,hscif-r8a7744", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c8000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>, +- <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, +- <&dmac1 0x4d>, <&dmac1 0x4e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- }; +- +- hscif2: serial@e62d0000 { +- compatible = "renesas,hscif-r8a7744", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62d0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 713>, +- <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, +- <&dmac1 0x3b>, <&dmac1 0x3c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 713>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e20000 { +- compatible = "renesas,msiof-r8a7744", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e20000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 000>; +- dmas = <&dmac0 0x51>, <&dmac0 0x52>, +- <&dmac1 0x51>, <&dmac1 0x52>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- #address-cells = <1>; +- #size-cells = <0>; +- resets = <&cpg 000>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6e10000 { +- compatible = "renesas,msiof-r8a7744", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e10000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 208>; +- dmas = <&dmac0 0x55>, <&dmac0 0x56>, +- <&dmac1 0x55>, <&dmac1 0x56>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- #address-cells = <1>; +- #size-cells = <0>; +- resets = <&cpg 208>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6e00000 { +- compatible = "renesas,msiof-r8a7744", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e00000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 205>; +- dmas = <&dmac0 0x41>, <&dmac0 0x42>, +- <&dmac1 0x41>, <&dmac1 0x42>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- #address-cells = <1>; +- #size-cells = <0>; +- resets = <&cpg 205>; +- status = "disabled"; +- }; +- +- pwm0: pwm@e6e30000 { +- compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; +- reg = <0 0xe6e30000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm1: pwm@e6e31000 { +- compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; +- reg = <0 0xe6e31000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm2: pwm@e6e32000 { +- compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; +- reg = <0 0xe6e32000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm3: pwm@e6e33000 { +- compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; +- reg = <0 0xe6e33000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm4: pwm@e6e34000 { +- compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; +- reg = <0 0xe6e34000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm5: pwm@e6e35000 { +- compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; +- reg = <0 0xe6e35000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm6: pwm@e6e36000 { +- compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; +- reg = <0 0xe6e36000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- can0: can@e6e80000 { +- compatible = "renesas,can-r8a7744", +- "renesas,rcar-gen2-can"; +- reg = <0 0xe6e80000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>, +- <&cpg CPG_CORE R8A7744_CLK_RCAN>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- status = "disabled"; +- }; +- +- can1: can@e6e88000 { +- compatible = "renesas,can-r8a7744", +- "renesas,rcar-gen2-can"; +- reg = <0 0xe6e88000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>, +- <&cpg CPG_CORE R8A7744_CLK_RCAN>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- status = "disabled"; +- }; +- +- vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a7744", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef0000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 811>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 811>; +- status = "disabled"; +- }; +- +- vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a7744", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef1000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 810>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 810>; +- status = "disabled"; +- }; +- +- vin2: video@e6ef2000 { +- compatible = "renesas,vin-r8a7744", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef2000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 809>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 809>; +- status = "disabled"; +- }; +- +- rcar_sound: sound@ec500000 { +- /* +- * #sound-dai-cells is required +- * +- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; +- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; +- */ +- compatible = "renesas,rcar_sound-r8a7744", +- "renesas,rcar_sound-gen2"; +- reg = <0 0xec500000 0 0x1000>, /* SCU */ +- <0 0xec5a0000 0 0x100>, /* ADG */ +- <0 0xec540000 0 0x1000>, /* SSIU */ +- <0 0xec541000 0 0x280>, /* SSI */ +- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ +- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; +- +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, +- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, +- <&cpg CPG_CORE R8A7744_CLK_M2>; +- clock-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", +- "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", +- "src.9", "src.8", "src.7", "src.6", "src.5", +- "src.4", "src.3", "src.2", "src.1", "src.0", +- "ctu.0", "ctu.1", +- "mix.0", "mix.1", +- "dvc.0", "dvc.1", +- "clk_a", "clk_b", "clk_c", "clk_i"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 1005>, +- <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, +- <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, +- <&cpg 1014>, <&cpg 1015>; +- reset-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", +- "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; +- status = "disabled"; +- +- rcar_sound,dvc { +- dvc0: dvc-0 { +- dmas = <&audma1 0xbc>; +- dma-names = "tx"; +- }; +- dvc1: dvc-1 { +- dmas = <&audma1 0xbe>; +- dma-names = "tx"; +- }; +- }; +- +- rcar_sound,mix { +- mix0: mix-0 { }; +- mix1: mix-1 { }; +- }; +- +- rcar_sound,ctu { +- ctu00: ctu-0 { }; +- ctu01: ctu-1 { }; +- ctu02: ctu-2 { }; +- ctu03: ctu-3 { }; +- ctu10: ctu-4 { }; +- ctu11: ctu-5 { }; +- ctu12: ctu-6 { }; +- ctu13: ctu-7 { }; +- }; +- +- rcar_sound,src { +- src0: src-0 { +- interrupts = ; +- dmas = <&audma0 0x85>, <&audma1 0x9a>; +- dma-names = "rx", "tx"; +- }; +- src1: src-1 { +- interrupts = ; +- dmas = <&audma0 0x87>, <&audma1 0x9c>; +- dma-names = "rx", "tx"; +- }; +- src2: src-2 { +- interrupts = ; +- dmas = <&audma0 0x89>, <&audma1 0x9e>; +- dma-names = "rx", "tx"; +- }; +- src3: src-3 { +- interrupts = ; +- dmas = <&audma0 0x8b>, <&audma1 0xa0>; +- dma-names = "rx", "tx"; +- }; +- src4: src-4 { +- interrupts = ; +- dmas = <&audma0 0x8d>, <&audma1 0xb0>; +- dma-names = "rx", "tx"; +- }; +- src5: src-5 { +- interrupts = ; +- dmas = <&audma0 0x8f>, <&audma1 0xb2>; +- dma-names = "rx", "tx"; +- }; +- src6: src-6 { +- interrupts = ; +- dmas = <&audma0 0x91>, <&audma1 0xb4>; +- dma-names = "rx", "tx"; +- }; +- src7: src-7 { +- interrupts = ; +- dmas = <&audma0 0x93>, <&audma1 0xb6>; +- dma-names = "rx", "tx"; +- }; +- src8: src-8 { +- interrupts = ; +- dmas = <&audma0 0x95>, <&audma1 0xb8>; +- dma-names = "rx", "tx"; +- }; +- src9: src-9 { +- interrupts = ; +- dmas = <&audma0 0x97>, <&audma1 0xba>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssi { +- ssi0: ssi-0 { +- interrupts = ; +- dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi1: ssi-1 { +- interrupts = ; +- dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi2: ssi-2 { +- interrupts = ; +- dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi3: ssi-3 { +- interrupts = ; +- dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi4: ssi-4 { +- interrupts = ; +- dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi5: ssi-5 { +- interrupts = ; +- dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi6: ssi-6 { +- interrupts = ; +- dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi7: ssi-7 { +- interrupts = ; +- dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi8: ssi-8 { +- interrupts = ; +- dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi9: ssi-9 { +- interrupts = ; +- dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- }; +- }; +- +- audma0: dma-controller@ec700000 { +- compatible = "renesas,dmac-r8a7744", +- "renesas,rcar-dmac"; +- reg = <0 0xec700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12"; +- clocks = <&cpg CPG_MOD 502>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 502>; +- #dma-cells = <1>; +- dma-channels = <13>; +- }; +- +- audma1: dma-controller@ec720000 { +- compatible = "renesas,dmac-r8a7744", +- "renesas,rcar-dmac"; +- reg = <0 0xec720000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12"; +- clocks = <&cpg CPG_MOD 501>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 501>; +- #dma-cells = <1>; +- dma-channels = <13>; +- }; +- +- /* +- * pci1 and xhci share the same phy, therefore only one of them +- * can be active at any one time. If both of them are enabled, +- * a race condition will determine who'll control the phy. +- * A firmware file is needed by the xhci driver in order for +- * USB 3.0 to work properly. +- */ +- xhci: usb@ee000000 { +- compatible = "renesas,xhci-r8a7744", +- "renesas,rcar-gen2-xhci"; +- reg = <0 0xee000000 0 0xc00>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- phys = <&usb2 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- pci0: pci@ee090000 { +- compatible = "renesas,pci-r8a7744", +- "renesas,pci-rcar-gen2"; +- device_type = "pci"; +- reg = <0 0xee090000 0 0xc00>, +- <0 0xee080000 0 0x1100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- status = "disabled"; +- +- bus-range = <0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; +- interrupt-map-mask = <0xf800 0 0 0x7>; +- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, +- <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, +- <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; +- +- usb@1,0 { +- reg = <0x800 0 0 0 0>; +- phys = <&usb0 0>; +- phy-names = "usb"; +- }; +- +- usb@2,0 { +- reg = <0x1000 0 0 0 0>; +- phys = <&usb0 0>; +- phy-names = "usb"; +- }; +- }; +- +- pci1: pci@ee0d0000 { +- compatible = "renesas,pci-r8a7744", +- "renesas,pci-rcar-gen2"; +- device_type = "pci"; +- reg = <0 0xee0d0000 0 0xc00>, +- <0 0xee0c0000 0 0x1100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- status = "disabled"; +- +- bus-range = <1 1>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; +- interrupt-map-mask = <0xf800 0 0 0x7>; +- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, +- <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, +- <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; +- +- usb@1,0 { +- reg = <0x10800 0 0 0 0>; +- phys = <&usb2 0>; +- phy-names = "usb"; +- }; +- +- usb@2,0 { +- reg = <0x11000 0 0 0 0>; +- phys = <&usb2 0>; +- phy-names = "usb"; +- }; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a7744", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee100000 0 0x328>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- dmas = <&dmac0 0xcd>, <&dmac0 0xce>, +- <&dmac1 0xcd>, <&dmac1 0xce>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <195000000>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a7744", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee140000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 312>; +- dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, +- <&dmac1 0xc1>, <&dmac1 0xc2>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <97500000>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 312>; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ee160000 { +- compatible = "renesas,sdhi-r8a7744", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee160000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 311>; +- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, +- <&dmac1 0xd3>, <&dmac1 0xd4>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <97500000>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 311>; +- status = "disabled"; +- }; +- +- mmcif0: mmc@ee200000 { +- compatible = "renesas,mmcif-r8a7744", +- "renesas,sh-mmcif"; +- reg = <0 0xee200000 0 0x80>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 315>; +- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, +- <&dmac1 0xd1>, <&dmac1 0xd2>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 315>; +- reg-io-width = <4>; +- max-frequency = <97500000>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1001000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, +- <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- pciec: pcie@fe000000 { +- compatible = "renesas,pcie-r8a7744", +- "renesas,pcie-rcar-gen2"; +- reg = <0 0xfe000000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, +- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, +- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, +- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, +- <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 319>; +- status = "disabled"; +- }; +- +- vsp@fe928000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe928000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 131>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 131>; +- }; +- +- vsp@fe930000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe930000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 128>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 128>; +- }; +- +- vsp@fe938000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe938000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 127>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 127>; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a7744"; +- reg = <0 0xfeb00000 0 0x40000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; +- clock-names = "du.0", "du.1"; +- resets = <&cpg 724>; +- reset-names = "du.0"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb: endpoint { +- }; +- }; +- port@1 { +- reg = <1>; +- du_out_lvds0: endpoint { +- remote-endpoint = <&lvds0_in>; +- }; +- }; +- }; +- }; +- +- lvds0: lvds@feb90000 { +- compatible = "renesas,r8a7744-lvds"; +- reg = <0 0xfeb90000 0 0x1c>; +- clocks = <&cpg CPG_MOD 726>; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 726>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds0_in: endpoint { +- remote-endpoint = <&du_out_lvds0>; +- }; +- }; +- port@1 { +- reg = <1>; +- lvds0_out: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@ff000044 { +- compatible = "renesas,prr"; +- reg = <0 0xff000044 0 4>; +- }; +- +- cmt0: timer@ffca0000 { +- compatible = "renesas,r8a7744-cmt0", +- "renesas,rcar-gen2-cmt0"; +- reg = <0 0xffca0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a7744-cmt1", +- "renesas,rcar-gen2-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 329>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; +- resets = <&cpg 329>; +- status = "disabled"; +- }; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&thermal>; +- +- trips { +- cpu-crit { +- temperature = <95000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +- }; +- +- /* External USB clock - can be overridden by the board */ +- usb_extal_clk: usb_extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <48000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7745-iwg22d-sodimm-dbhd-ca.dts b/scripts/dtc/include-prefixes/arm/r8a7745-iwg22d-sodimm-dbhd-ca.dts +deleted file mode 100644 +index b1f679da36b2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7745-iwg22d-sodimm-dbhd-ca.dts ++++ /dev/null +@@ -1,159 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the iWave-RZG1E SODIMM carrier board + HDMI daughter +- * board +- * +- * Copyright (C) 2017 Renesas Electronics Corp. +- */ +- +-#include "r8a7745-iwg22d-sodimm.dts" +- +-/ { +- model = "iWave RainboW-G22D-SODIMM RZ/G1E based board with HDMI add-on"; +- compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"; +- +- aliases { +- serial0 = &scif1; +- serial4 = &scif5; +- serial6 = &hscif2; +- }; +- +- cec_clock: cec-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <12000000>; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con: endpoint { +- remote-endpoint = <&adv7511_out>; +- }; +- }; +- }; +-}; +- +-&du { +- pinctrl-0 = <&du0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- ports { +- port@0 { +- endpoint { +- remote-endpoint = <&adv7511_in>; +- }; +- }; +- }; +-}; +- +-&can1 { +- pinctrl-0 = <&can1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&hscif2 { +- pinctrl-0 = <&hscif2_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-0 = <&i2c1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- hdmi@39 { +- compatible = "adi,adv7511w"; +- reg = <0x39>; +- interrupt-parent = <&gpio1>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- clocks = <&cec_clock>; +- clock-names = "cec"; +- pd-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; +- +- adi,input-depth = <8>; +- adi,input-colorspace = "rgb"; +- adi,input-clock = "1x"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7511_in: endpoint { +- remote-endpoint = <&du_out_rgb0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- adv7511_out: endpoint { +- remote-endpoint = <&hdmi_con>; +- }; +- }; +- }; +- }; +-}; +- +-&lcd_panel { +- status = "disabled"; +- +- /delete-node/ port; +-}; +- +-&pfc { +- can1_pins: can1 { +- groups = "can1_data_b"; +- function = "can1"; +- }; +- +- du0_pins: du0 { +- groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out"; +- function = "du0"; +- }; +- +- hscif2_pins: hscif2 { +- groups = "hscif2_data"; +- function = "hscif2"; +- }; +- +- i2c1_pins: i2c1 { +- groups = "i2c1_d"; +- function = "i2c1"; +- }; +- +- scif1_pins: scif1 { +- groups = "scif1_data"; +- function = "scif1"; +- }; +- +- scif5_pins: scif5 { +- groups = "scif5_data_d"; +- function = "scif5"; +- }; +-}; +- +-&scif1 { +- pinctrl-0 = <&scif1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scif5 { +- pinctrl-0 = <&scif5_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7745-iwg22d-sodimm.dts b/scripts/dtc/include-prefixes/arm/r8a7745-iwg22d-sodimm.dts +deleted file mode 100644 +index 73bd62d8a929..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7745-iwg22d-sodimm.dts ++++ /dev/null +@@ -1,327 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the iWave-RZG1E SODIMM carrier board +- * +- * Copyright (C) 2017 Renesas Electronics Corp. +- */ +- +-/* +- * SSI-SGTL5000 +- * +- * This command is required when Playback/Capture +- * +- * amixer set "DVC Out" 100% +- * amixer set "DVC In" 100% +- * +- * You can use Mute +- * +- * amixer set "DVC Out Mute" on +- * amixer set "DVC In Mute" on +- * +- * You can use Volume Ramp +- * +- * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" +- * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" +- * amixer set "DVC Out Ramp" on +- * aplay xxx.wav & +- * amixer set "DVC Out" 80% // Volume Down +- * amixer set "DVC Out" 100% // Volume Up +- */ +- +-/dts-v1/; +-#include "r8a7745-iwg22m.dtsi" +-#include +- +-/ { +- model = "iWave Systems RainboW-G22D-SODIMM board based on RZ/G1E"; +- compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"; +- +- aliases { +- ethernet0 = &avb; +- serial3 = &scif4; +- serial5 = &hscif1; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial3:115200n8"; +- }; +- +- audio_clock: audio_clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +- +- backlight_lcd: backlight { +- compatible = "pwm-backlight"; +- pwms = <&tpu 3 5000000 PWM_POLARITY_INVERTED>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <7>; +- }; +- +- lcd_panel: lcd { +- compatible = "edt,etm043080dh6gp"; +- power-supply = <&vccq_panel>; +- backlight = <&backlight_lcd>; +- +- port { +- lcd_in: endpoint { +- remote-endpoint = <&du_out_rgb0>; +- }; +- }; +- }; +- +- vccq_panel: regulator-vccq-panel { +- compatible = "regulator-fixed"; +- regulator-name = "Panel VccQ"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; +- enable-active-high; +- }; +- +- vccq_sdhi0: regulator-vccq-sdhi0 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI0 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- rsnd_sgtl5000: sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sndcodec>; +- simple-audio-card,frame-master = <&sndcodec>; +- +- sndcpu: simple-audio-card,cpu { +- sound-dai = <&rcar_sound>; +- }; +- +- sndcodec: simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- }; +- }; +-}; +- +-&avb { +- pinctrl-0 = <&avb_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <&phy3>; +- phy-mode = "gmii"; +- renesas,no-ether-link; +- status = "okay"; +- +- phy3: ethernet-phy@3 { +- /* +- * On some older versions of the platform (before R4.0) the phy address +- * may be 1 or 3. The address is fixed to 3 for R4.0 onwards. +- */ +- reg = <3>; +- micrel,led-mode = <1>; +- }; +-}; +- +-&can0 { +- pinctrl-0 = <&can0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&du { +- pinctrl-0 = <&du0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- ports { +- port@0 { +- endpoint { +- remote-endpoint = <&lcd_in>; +- }; +- }; +- }; +-}; +- +-&hscif1 { +- pinctrl-0 = <&hscif1_pins>; +- pinctrl-names = "default"; +- +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&hsusb { +- status = "okay"; +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +-}; +- +-&i2c5 { +- pinctrl-0 = <&i2c5_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- #sound-dai-cells = <0>; +- reg = <0x0a>; +- clocks = <&audio_clock>; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; +- }; +- +- stmpe811@44 { +- compatible = "st,stmpe811"; +- reg = <0x44>; +- interrupt-parent = <&gpio4>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- +- /* 3.25 MHz ADC clock speed */ +- st,adc-freq = <1>; +- /* ADC conversion time: 80 clocks */ +- st,sample-time = <4>; +- /* 12-bit ADC */ +- st,mod-12b = <1>; +- /* internal ADC reference */ +- st,ref-sel = <0>; +- +- stmpe_touchscreen { +- compatible = "st,stmpe-ts"; +- /* 8 sample average control */ +- st,ave-ctrl = <3>; +- /* 7 length fractional part in z */ +- st,fraction-z = <7>; +- /* +- * 50 mA typical 80 mA max touchscreen drivers +- * current limit value +- */ +- st,i-drive = <1>; +- /* 1 ms panel driver settling time */ +- st,settling = <3>; +- /* 5 ms touch detect interrupt delay */ +- st,touch-det-delay = <5>; +- }; +- }; +-}; +- +-&pci1 { +- status = "okay"; +- pinctrl-0 = <&usb1_pins>; +- pinctrl-names = "default"; +-}; +- +-&pfc { +- avb_pins: avb { +- groups = "avb_mdio", "avb_gmii"; +- function = "avb"; +- }; +- +- backlight_pins: backlight { +- groups = "tpu_to3_c"; +- function = "tpu"; +- }; +- +- can0_pins: can0 { +- groups = "can0_data"; +- function = "can0"; +- }; +- +- du0_pins: du0 { +- groups = "du0_rgb666", "du0_sync", "du0_disp", "du0_clk0_out"; +- function = "du0"; +- }; +- +- hscif1_pins: hscif1 { +- groups = "hscif1_data", "hscif1_ctrl"; +- function = "hscif1"; +- }; +- +- i2c5_pins: i2c5 { +- groups = "i2c5_b"; +- function = "i2c5"; +- }; +- +- scif4_pins: scif4 { +- groups = "scif4_data_b"; +- function = "scif4"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <3300>; +- }; +- +- sound_pins: sound { +- groups = "ssi34_ctrl", "ssi3_data", "ssi4_data"; +- function = "ssi"; +- }; +- +- usb0_pins: usb0 { +- groups = "usb0"; +- function = "usb0"; +- }; +- +- usb1_pins: usb1 { +- groups = "usb1"; +- function = "usb1"; +- }; +-}; +- +-&rcar_sound { +- pinctrl-0 = <&sound_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- /* Single DAI */ +- +- #sound-dai-cells = <0>; +- +- rcar_sound,dai { +- dai0 { +- playback = <&ssi3>, <&src3>, <&dvc0>; +- capture = <&ssi4>, <&src4>, <&dvc1>; +- }; +- }; +-}; +- +-&scif4 { +- pinctrl-0 = <&scif4_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <&vccq_sdhi0>; +- cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&ssi4 { +- shared-pin; +-}; +- +-&tpu { +- pinctrl-0 = <&backlight_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7745-iwg22m.dtsi b/scripts/dtc/include-prefixes/arm/r8a7745-iwg22m.dtsi +deleted file mode 100644 +index 41f111b99a75..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7745-iwg22m.dtsi ++++ /dev/null +@@ -1,117 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the iWave-RZG1E-G22M SODIMM SOM +- * +- * Copyright (C) 2017 Renesas Electronics Corp. +- */ +- +-#include "r8a7745.dtsi" +-#include +- +-/ { +- compatible = "iwave,g22m", "renesas,r8a7745"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x20000000>; +- }; +- +- reg_3p3v: 3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&cmt0 { +- status = "okay"; +-}; +- +-&extal_clk { +- clock-frequency = <20000000>; +-}; +- +-&pfc { +- mmcif0_pins: mmc { +- groups = "mmc_data8", "mmc_ctrl"; +- function = "mmc"; +- }; +- +- qspi_pins: qspi { +- groups = "qspi_ctrl", "qspi_data2"; +- function = "qspi"; +- }; +- +- sdhi1_pins: sd1 { +- groups = "sdhi1_data4", "sdhi1_ctrl"; +- function = "sdhi1"; +- power-source = <3300>; +- }; +- +- i2c3_pins: i2c3 { +- groups = "i2c3_b"; +- function = "i2c3"; +- }; +-}; +- +-&mmcif0 { +- pinctrl-0 = <&mmcif0_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <®_3p3v>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&qspi { +- pinctrl-0 = <&qspi_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- /* WARNING - This device contains the bootloader. Handle with care. */ +- flash: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "sst,sst25vf016b", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <1>; +- m25p,fast-read; +- spi-cpol; +- spi-cpha; +- }; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&sdhi1 { +- pinctrl-0 = <&sdhi1_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_3p3v>; +- cd-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&i2c3 { +- pinctrl-0 = <&i2c3_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- rtc@68 { +- compatible = "ti,bq32000"; +- reg = <0x68>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7745-sk-rzg1e.dts b/scripts/dtc/include-prefixes/arm/r8a7745-sk-rzg1e.dts +deleted file mode 100644 +index 59d1a9bfab05..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7745-sk-rzg1e.dts ++++ /dev/null +@@ -1,72 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the SK-RZG1E board +- * +- * Copyright (C) 2016-2017 Cogent Embedded, Inc. +- */ +- +-/dts-v1/; +-#include "r8a7745.dtsi" +- +-/ { +- model = "SK-RZG1E"; +- compatible = "renesas,sk-rzg1e", "renesas,r8a7745"; +- +- aliases { +- serial0 = &scif2; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x40000000>; +- }; +-}; +- +-&extal_clk { +- clock-frequency = <20000000>; +-}; +- +-&pfc { +- scif2_pins: scif2 { +- groups = "scif2_data"; +- function = "scif2"; +- }; +- +- ether_pins: ether { +- groups = "eth_link", "eth_mdio", "eth_rmii"; +- function = "eth"; +- }; +- +- phy1_pins: phy1 { +- groups = "intc_irq8"; +- function = "intc"; +- }; +-}; +- +-&scif2 { +- pinctrl-0 = <&scif2_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-ðer { +- pinctrl-0 = <ðer_pins>, <&phy1_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <&phy1>; +- renesas,ether-link-active-low; +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- interrupt-parent = <&irqc>; +- interrupts = <8 IRQ_TYPE_LEVEL_LOW>; +- micrel,led-mode = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7745.dtsi b/scripts/dtc/include-prefixes/arm/r8a7745.dtsi +deleted file mode 100644 +index f877c51f769c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7745.dtsi ++++ /dev/null +@@ -1,1588 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the r8a7745 SoC +- * +- * Copyright (C) 2016-2017 Cogent Embedded Inc. +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r8a7745"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &iic0; +- i2c7 = &iic1; +- spi0 = &qspi; +- spi1 = &msiof0; +- spi2 = &msiof1; +- spi3 = &msiof2; +- vin0 = &vin0; +- vin1 = &vin1; +- }; +- +- /* +- * The external audio clocks are configured as 0 Hz fixed +- * frequency clocks by default. Boards that provide audio +- * clocks should override them. +- */ +- audio_clka: audio_clka { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- audio_clkb: audio_clkb { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- audio_clkc: audio_clkc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* External CAN clock */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0>; +- clock-frequency = <1000000000>; +- clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; +- power-domains = <&sysc R8A7745_PD_CA7_CPU0>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA7>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <1>; +- clock-frequency = <1000000000>; +- clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; +- power-domains = <&sysc R8A7745_PD_CA7_CPU1>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA7>; +- }; +- +- L2_CA7: cache-controller-0 { +- compatible = "cache"; +- cache-unified; +- cache-level = <2>; +- power-domains = <&sysc R8A7745_PD_CA7_SCU>; +- }; +- }; +- +- /* External root clock */ +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- /* External SCIF clock */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a7745", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a7745", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a7745", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a7745", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a7745", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a7745", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 28>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- gpio6: gpio@e6055400 { +- compatible = "renesas,gpio-r8a7745", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055400 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 192 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 905>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 905>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a7745"; +- reg = <0 0xe6060000 0 0x11c>; +- }; +- +- tpu: pwm@e60f0000 { +- compatible = "renesas,tpu-r8a7745", "renesas,tpu"; +- reg = <0 0xe60f0000 0 0x148>; +- clocks = <&cpg CPG_MOD 304>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 304>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a7745-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>, <&usb_extal_clk>; +- clock-names = "extal", "usb_extal"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- apmu@e6151000 { +- compatible = "renesas,r8a7745-apmu", "renesas,apmu"; +- reg = <0 0xe6151000 0 0x188>; +- cpus = <&cpu0>, <&cpu1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a7745-rst"; +- reg = <0 0xe6160000 0 0x100>; +- }; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a7745-wdt", +- "renesas,rcar-gen2-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a7745-sysc"; +- reg = <0 0xe6180000 0 0x200>; +- #power-domain-cells = <1>; +- }; +- +- irqc: interrupt-controller@e61c0000 { +- compatible = "renesas,irqc-r8a7745", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- ipmmu_sy0: iommu@e6280000 { +- compatible = "renesas,ipmmu-r8a7745", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6280000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_sy1: iommu@e6290000 { +- compatible = "renesas,ipmmu-r8a7745", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6290000 0 0x1000>; +- interrupts = ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_ds: iommu@e6740000 { +- compatible = "renesas,ipmmu-r8a7745", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6740000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_mp: iommu@ec680000 { +- compatible = "renesas,ipmmu-r8a7745", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xec680000 0 0x1000>; +- interrupts = ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_mx: iommu@fe951000 { +- compatible = "renesas,ipmmu-r8a7745", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xfe951000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_gp: iommu@e62a0000 { +- compatible = "renesas,ipmmu-r8a7745", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe62a0000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- icram0: sram@e63a0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63a0000 0 0x12000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63a0000 0x12000>; +- }; +- +- icram1: sram@e63c0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63c0000 0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63c0000 0x1000>; +- +- smp-sram@0 { +- compatible = "renesas,smp-sram"; +- reg = <0 0x100>; +- }; +- }; +- +- icram2: sram@e6300000 { +- compatible = "mmio-sram"; +- reg = <0 0xe6300000 0 0x40000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe6300000 0x40000>; +- }; +- i2c0: i2c@e6508000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7745", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6518000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7745", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6518000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6530000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7745", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6530000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e6540000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7745", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6540000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e6520000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7745", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6520000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 927>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 927>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c5: i2c@e6528000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7745", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6528000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 925>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 925>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- iic0: i2c@e6500000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7745", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe6500000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 318>; +- dmas = <&dmac0 0x61>, <&dmac0 0x62>, +- <&dmac1 0x61>, <&dmac1 0x62>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 318>; +- status = "disabled"; +- }; +- +- iic1: i2c@e6510000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7745", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe6510000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 323>; +- dmas = <&dmac0 0x65>, <&dmac0 0x66>, +- <&dmac1 0x65>, <&dmac1 0x66>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 323>; +- status = "disabled"; +- }; +- +- hsusb: usb@e6590000 { +- compatible = "renesas,usbhs-r8a7745", +- "renesas,rcar-gen2-usbhs"; +- reg = <0 0xe6590000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 704>; +- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, +- <&usb_dmac1 0>, <&usb_dmac1 1>; +- dma-names = "ch0", "ch1", "ch2", "ch3"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 704>; +- renesas,buswait = <4>; +- phys = <&usb0 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usbphy: usb-phy@e6590100 { +- compatible = "renesas,usb-phy-r8a7745", +- "renesas,rcar-gen2-usb-phy"; +- reg = <0 0xe6590100 0 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cpg CPG_MOD 704>; +- clock-names = "usbhs"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 704>; +- status = "disabled"; +- +- usb0: usb-channel@0 { +- reg = <0>; +- #phy-cells = <1>; +- }; +- usb2: usb-channel@2 { +- reg = <2>; +- #phy-cells = <1>; +- }; +- }; +- +- usb_dmac0: dma-controller@e65a0000 { +- compatible = "renesas,r8a7745-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65a0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 330>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 330>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac1: dma-controller@e65b0000 { +- compatible = "renesas,r8a7745-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65b0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 331>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 331>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a7745", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- dmac1: dma-controller@e6720000 { +- compatible = "renesas,dmac-r8a7745", +- "renesas,rcar-dmac"; +- reg = <0 0xe6720000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a7745", +- "renesas,etheravb-rcar-gen2"; +- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- qspi: spi@e6b10000 { +- compatible = "renesas,qspi-r8a7745", "renesas,qspi"; +- reg = <0 0xe6b10000 0 0x2c>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 917>; +- dmas = <&dmac0 0x17>, <&dmac0 0x18>, +- <&dmac1 0x17>, <&dmac1 0x18>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- resets = <&cpg 917>; +- status = "disabled"; +- }; +- +- scifa0: serial@e6c40000 { +- compatible = "renesas,scifa-r8a7745", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c40000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>; +- clock-names = "fck"; +- dmas = <&dmac0 0x21>, <&dmac0 0x22>, +- <&dmac1 0x21>, <&dmac1 0x22>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scifa1: serial@e6c50000 { +- compatible = "renesas,scifa-r8a7745", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c50000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>; +- clock-names = "fck"; +- dmas = <&dmac0 0x25>, <&dmac0 0x26>, +- <&dmac1 0x25>, <&dmac1 0x26>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- scifa2: serial@e6c60000 { +- compatible = "renesas,scifa-r8a7745", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c60000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 202>; +- clock-names = "fck"; +- dmas = <&dmac0 0x27>, <&dmac0 0x28>, +- <&dmac1 0x27>, <&dmac1 0x28>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 202>; +- status = "disabled"; +- }; +- +- scifa3: serial@e6c70000 { +- compatible = "renesas,scifa-r8a7745", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c70000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1106>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, +- <&dmac1 0x1b>, <&dmac1 0x1c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 1106>; +- status = "disabled"; +- }; +- +- scifa4: serial@e6c78000 { +- compatible = "renesas,scifa-r8a7745", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c78000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1107>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1f>, <&dmac0 0x20>, +- <&dmac1 0x1f>, <&dmac1 0x20>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 1107>; +- status = "disabled"; +- }; +- +- scifa5: serial@e6c80000 { +- compatible = "renesas,scifa-r8a7745", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c80000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1108>; +- clock-names = "fck"; +- dmas = <&dmac0 0x23>, <&dmac0 0x24>, +- <&dmac1 0x23>, <&dmac1 0x24>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 1108>; +- status = "disabled"; +- }; +- +- scifb0: serial@e6c20000 { +- compatible = "renesas,scifb-r8a7745", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6c20000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>; +- clock-names = "fck"; +- dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, +- <&dmac1 0x3d>, <&dmac1 0x3e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scifb1: serial@e6c30000 { +- compatible = "renesas,scifb-r8a7745", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6c30000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>; +- clock-names = "fck"; +- dmas = <&dmac0 0x19>, <&dmac0 0x1a>, +- <&dmac1 0x19>, <&dmac1 0x1a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scifb2: serial@e6ce0000 { +- compatible = "renesas,scifb-r8a7745", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6ce0000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 216>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, +- <&dmac1 0x1d>, <&dmac1 0x1e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 216>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a7745", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e60000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 721>, +- <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x29>, <&dmac0 0x2a>, +- <&dmac1 0x29>, <&dmac1 0x2a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 721>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a7745", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e68000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 720>, +- <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, +- <&dmac1 0x2d>, <&dmac1 0x2e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 720>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e58000 { +- compatible = "renesas,scif-r8a7745", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e58000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 719>, +- <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, +- <&dmac1 0x2b>, <&dmac1 0x2c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 719>; +- status = "disabled"; +- }; +- +- scif3: serial@e6ea8000 { +- compatible = "renesas,scif-r8a7745", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ea8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 718>, +- <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2f>, <&dmac0 0x30>, +- <&dmac1 0x2f>, <&dmac1 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 718>; +- status = "disabled"; +- }; +- +- scif4: serial@e6ee0000 { +- compatible = "renesas,scif-r8a7745", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ee0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 715>, +- <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, +- <&dmac1 0xfb>, <&dmac1 0xfc>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 715>; +- status = "disabled"; +- }; +- +- scif5: serial@e6ee8000 { +- compatible = "renesas,scif-r8a7745", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ee8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 714>, +- <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, +- <&dmac1 0xfd>, <&dmac1 0xfe>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 714>; +- status = "disabled"; +- }; +- +- hscif0: serial@e62c0000 { +- compatible = "renesas,hscif-r8a7745", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 717>, +- <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x39>, <&dmac0 0x3a>, +- <&dmac1 0x39>, <&dmac1 0x3a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 717>; +- status = "disabled"; +- }; +- +- hscif1: serial@e62c8000 { +- compatible = "renesas,hscif-r8a7745", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c8000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>, +- <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, +- <&dmac1 0x4d>, <&dmac1 0x4e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- }; +- +- hscif2: serial@e62d0000 { +- compatible = "renesas,hscif-r8a7745", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62d0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 713>, +- <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, +- <&dmac1 0x3b>, <&dmac1 0x3c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 713>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e20000 { +- compatible = "renesas,msiof-r8a7745", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e20000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 000>; +- dmas = <&dmac0 0x51>, <&dmac0 0x52>, +- <&dmac1 0x51>, <&dmac1 0x52>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- #address-cells = <1>; +- #size-cells = <0>; +- resets = <&cpg 000>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6e10000 { +- compatible = "renesas,msiof-r8a7745", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e10000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 208>; +- dmas = <&dmac0 0x55>, <&dmac0 0x56>, +- <&dmac1 0x55>, <&dmac1 0x56>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- #address-cells = <1>; +- #size-cells = <0>; +- resets = <&cpg 208>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6e00000 { +- compatible = "renesas,msiof-r8a7745", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e00000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 205>; +- dmas = <&dmac0 0x41>, <&dmac0 0x42>, +- <&dmac1 0x41>, <&dmac1 0x42>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- #address-cells = <1>; +- #size-cells = <0>; +- resets = <&cpg 205>; +- status = "disabled"; +- }; +- +- pwm0: pwm@e6e30000 { +- compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; +- reg = <0 0xe6e30000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm1: pwm@e6e31000 { +- compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; +- reg = <0 0xe6e31000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm2: pwm@e6e32000 { +- compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; +- reg = <0 0xe6e32000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm3: pwm@e6e33000 { +- compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; +- reg = <0 0xe6e33000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm4: pwm@e6e34000 { +- compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; +- reg = <0 0xe6e34000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm5: pwm@e6e35000 { +- compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; +- reg = <0 0xe6e35000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm6: pwm@e6e36000 { +- compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; +- reg = <0 0xe6e36000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- can0: can@e6e80000 { +- compatible = "renesas,can-r8a7745", +- "renesas,rcar-gen2-can"; +- reg = <0 0xe6e80000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>, +- <&cpg CPG_CORE R8A7745_CLK_RCAN>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- status = "disabled"; +- }; +- +- can1: can@e6e88000 { +- compatible = "renesas,can-r8a7745", +- "renesas,rcar-gen2-can"; +- reg = <0 0xe6e88000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>, +- <&cpg CPG_CORE R8A7745_CLK_RCAN>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- status = "disabled"; +- }; +- +- vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a7745", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef0000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 811>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 811>; +- status = "disabled"; +- }; +- +- vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a7745", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef1000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 810>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 810>; +- status = "disabled"; +- }; +- +- rcar_sound: sound@ec500000 { +- /* +- * #sound-dai-cells is required +- * +- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; +- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; +- */ +- compatible = "renesas,rcar_sound-r8a7745", +- "renesas,rcar_sound-gen2"; +- reg = <0 0xec500000 0 0x1000>, /* SCU */ +- <0 0xec5a0000 0 0x100>, /* ADG */ +- <0 0xec540000 0 0x1000>, /* SSIU */ +- <0 0xec541000 0 0x280>, /* SSI */ +- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ +- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; +- +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, +- <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, +- <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, +- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, +- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clka>, <&audio_clkb>, <&audio_clkc>, +- <&cpg CPG_CORE R8A7745_CLK_M2>; +- clock-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0", +- "src.6", "src.5", "src.4", "src.3", +- "src.2", "src.1", +- "ctu.0", "ctu.1", +- "mix.0", "mix.1", +- "dvc.0", "dvc.1", +- "clk_a", "clk_b", "clk_c", "clk_i"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 1005>, +- <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, +- <&cpg 1009>, <&cpg 1010>, <&cpg 1011>, +- <&cpg 1012>, <&cpg 1013>, <&cpg 1014>, +- <&cpg 1015>; +- reset-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0"; +- +- status = "disabled"; +- +- rcar_sound,dvc { +- dvc0: dvc-0 { +- dmas = <&audma0 0xbc>; +- dma-names = "tx"; +- }; +- dvc1: dvc-1 { +- dmas = <&audma0 0xbe>; +- dma-names = "tx"; +- }; +- }; +- +- rcar_sound,mix { +- mix0: mix-0 { }; +- mix1: mix-1 { }; +- }; +- +- rcar_sound,ctu { +- ctu00: ctu-0 { }; +- ctu01: ctu-1 { }; +- ctu02: ctu-2 { }; +- ctu03: ctu-3 { }; +- ctu10: ctu-4 { }; +- ctu11: ctu-5 { }; +- ctu12: ctu-6 { }; +- ctu13: ctu-7 { }; +- }; +- +- rcar_sound,src { +- src-0 { +- status = "disabled"; +- }; +- src1: src-1 { +- interrupts = ; +- dmas = <&audma0 0x87>, <&audma0 0x9c>; +- dma-names = "rx", "tx"; +- }; +- src2: src-2 { +- interrupts = ; +- dmas = <&audma0 0x89>, <&audma0 0x9e>; +- dma-names = "rx", "tx"; +- }; +- src3: src-3 { +- interrupts = ; +- dmas = <&audma0 0x8b>, <&audma0 0xa0>; +- dma-names = "rx", "tx"; +- }; +- src4: src-4 { +- interrupts = ; +- dmas = <&audma0 0x8d>, <&audma0 0xb0>; +- dma-names = "rx", "tx"; +- }; +- src5: src-5 { +- interrupts = ; +- dmas = <&audma0 0x8f>, <&audma0 0xb2>; +- dma-names = "rx", "tx"; +- }; +- src6: src-6 { +- interrupts = ; +- dmas = <&audma0 0x91>, <&audma0 0xb4>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssi { +- ssi0: ssi-0 { +- interrupts = ; +- dmas = <&audma0 0x01>, <&audma0 0x02>, +- <&audma0 0x15>, <&audma0 0x16>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi1: ssi-1 { +- interrupts = ; +- dmas = <&audma0 0x03>, <&audma0 0x04>, +- <&audma0 0x49>, <&audma0 0x4a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi2: ssi-2 { +- interrupts = ; +- dmas = <&audma0 0x05>, <&audma0 0x06>, +- <&audma0 0x63>, <&audma0 0x64>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi3: ssi-3 { +- interrupts = ; +- dmas = <&audma0 0x07>, <&audma0 0x08>, +- <&audma0 0x6f>, <&audma0 0x70>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi4: ssi-4 { +- interrupts = ; +- dmas = <&audma0 0x09>, <&audma0 0x0a>, +- <&audma0 0x71>, <&audma0 0x72>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi5: ssi-5 { +- interrupts = ; +- dmas = <&audma0 0x0b>, <&audma0 0x0c>, +- <&audma0 0x73>, <&audma0 0x74>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi6: ssi-6 { +- interrupts = ; +- dmas = <&audma0 0x0d>, <&audma0 0x0e>, +- <&audma0 0x75>, <&audma0 0x76>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi7: ssi-7 { +- interrupts = ; +- dmas = <&audma0 0x0f>, <&audma0 0x10>, +- <&audma0 0x79>, <&audma0 0x7a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi8: ssi-8 { +- interrupts = ; +- dmas = <&audma0 0x11>, <&audma0 0x12>, +- <&audma0 0x7b>, <&audma0 0x7c>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi9: ssi-9 { +- interrupts = ; +- dmas = <&audma0 0x13>, <&audma0 0x14>, +- <&audma0 0x7d>, <&audma0 0x7e>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- }; +- }; +- +- audma0: dma-controller@ec700000 { +- compatible = "renesas,dmac-r8a7745", +- "renesas,rcar-dmac"; +- reg = <0 0xec700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12"; +- clocks = <&cpg CPG_MOD 502>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 502>; +- #dma-cells = <1>; +- dma-channels = <13>; +- }; +- +- pci0: pci@ee090000 { +- compatible = "renesas,pci-r8a7745", +- "renesas,pci-rcar-gen2"; +- device_type = "pci"; +- reg = <0 0xee090000 0 0xc00>, +- <0 0xee080000 0 0x1100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- status = "disabled"; +- +- bus-range = <0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; +- interrupt-map-mask = <0xf800 0 0 0x7>; +- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, +- <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, +- <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; +- +- usb@1,0 { +- reg = <0x800 0 0 0 0>; +- phys = <&usb0 0>; +- phy-names = "usb"; +- }; +- +- usb@2,0 { +- reg = <0x1000 0 0 0 0>; +- phys = <&usb0 0>; +- phy-names = "usb"; +- }; +- }; +- +- pci1: pci@ee0d0000 { +- compatible = "renesas,pci-r8a7745", +- "renesas,pci-rcar-gen2"; +- device_type = "pci"; +- reg = <0 0xee0d0000 0 0xc00>, +- <0 0xee0c0000 0 0x1100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- status = "disabled"; +- +- bus-range = <1 1>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; +- interrupt-map-mask = <0xf800 0 0 0x7>; +- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, +- <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, +- <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; +- +- usb@1,0 { +- reg = <0x10800 0 0 0 0>; +- phys = <&usb2 0>; +- phy-names = "usb"; +- }; +- +- usb@2,0 { +- reg = <0x11000 0 0 0 0>; +- phys = <&usb2 0>; +- phy-names = "usb"; +- }; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a7745", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee100000 0 0x328>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- dmas = <&dmac0 0xcd>, <&dmac0 0xce>, +- <&dmac1 0xcd>, <&dmac1 0xce>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <195000000>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a7745", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee140000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 312>; +- dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, +- <&dmac1 0xc1>, <&dmac1 0xc2>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <97500000>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 312>; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ee160000 { +- compatible = "renesas,sdhi-r8a7745", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee160000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 311>; +- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, +- <&dmac1 0xd3>, <&dmac1 0xd4>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <97500000>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 311>; +- status = "disabled"; +- }; +- +- mmcif0: mmc@ee200000 { +- compatible = "renesas,mmcif-r8a7745", +- "renesas,sh-mmcif"; +- reg = <0 0xee200000 0 0x80>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 315>; +- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, +- <&dmac1 0xd1>, <&dmac1 0xd2>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 315>; +- reg-io-width = <4>; +- max-frequency = <97500000>; +- status = "disabled"; +- }; +- +- ether: ethernet@ee700000 { +- compatible = "renesas,ether-r8a7745", +- "renesas,rcar-gen2-ether"; +- reg = <0 0xee700000 0 0x400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 813>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 813>; +- phy-mode = "rmii"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1001000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, +- <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- vsp@fe928000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe928000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 131>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 131>; +- }; +- +- vsp@fe930000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe930000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 128>; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 128>; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a7745"; +- reg = <0 0xfeb00000 0 0x40000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; +- clock-names = "du.0", "du.1"; +- resets = <&cpg 724>; +- reset-names = "du.0"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb0: endpoint { +- }; +- }; +- port@1 { +- reg = <1>; +- du_out_rgb1: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@ff000044 { +- compatible = "renesas,prr"; +- reg = <0 0xff000044 0 4>; +- }; +- +- cmt0: timer@ffca0000 { +- compatible = "renesas,r8a7745-cmt0", +- "renesas,rcar-gen2-cmt0"; +- reg = <0 0xffca0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a7745-cmt1", +- "renesas,rcar-gen2-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 329>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; +- resets = <&cpg 329>; +- status = "disabled"; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +- }; +- +- /* External USB clock - can be overridden by the board */ +- usb_extal_clk: usb_extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <48000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a77470-iwg23s-sbc.dts b/scripts/dtc/include-prefixes/arm/r8a77470-iwg23s-sbc.dts +deleted file mode 100644 +index 8ac61b50aec0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a77470-iwg23s-sbc.dts ++++ /dev/null +@@ -1,319 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the iWave-RZ/G1C single board computer +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include +-#include "r8a77470.dtsi" +-/ { +- model = "iWave iW-RainboW-G23S single board computer based on RZ/G1C"; +- compatible = "iwave,g23s", "renesas,r8a77470"; +- +- aliases { +- ethernet0 = &avb; +- serial1 = &scif1; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial1:115200n8"; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con: endpoint { +- remote-endpoint = <&bridge_out>; +- }; +- }; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x20000000>; +- }; +- +- reg_1p8v: reg-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_3p3v: reg-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vccq_sdhi2: regulator-vccq-sdhi2 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI2 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +-}; +- +-&avb { +- pinctrl-0 = <&avb_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <&phy3>; +- phy-mode = "gmii"; +- renesas,no-ether-link; +- status = "okay"; +- +- phy3: ethernet-phy@3 { +- reg = <3>; +- interrupt-parent = <&gpio5>; +- interrupts = <16 IRQ_TYPE_LEVEL_LOW>; +- micrel,led-mode = <1>; +- }; +-}; +- +-&cmt0 { +- status = "okay"; +-}; +- +-&du { +- pinctrl-0 = <&du0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- ports { +- port@0 { +- endpoint { +- remote-endpoint = <&bridge_in>; +- }; +- }; +- }; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&extal_clk { +- clock-frequency = <20000000>; +-}; +- +-&gpio2 { +- interrupt-fixup { +- gpio-hog; +- gpios = <29 GPIO_ACTIVE_HIGH>; +- line-name = "hdmi-hpd-int"; +- input; +- }; +-}; +- +-&hsusb0 { +- status = "okay"; +-}; +- +-&i2c3 { +- pinctrl-0 = <&i2c3_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- rtc@51 { +- compatible = "nxp,pcf85263"; +- reg = <0x51>; +- }; +-}; +- +-&i2c4 { +- pinctrl-0 = <&i2c4_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- clock-frequency = <100000>; +- +- hdmi@39 { +- compatible = "sil,sii9022"; +- reg = <0x39>; +- interrupt-parent = <&gpio2>; +- interrupts = <29 IRQ_TYPE_LEVEL_LOW>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- bridge_in: endpoint { +- remote-endpoint = <&du_out_rgb0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- bridge_out: endpoint { +- remote-endpoint = <&hdmi_con>; +- }; +- }; +- }; +- }; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&pfc { +- avb_pins: avb { +- groups = "avb_mdio", "avb_gmii_tx_rx"; +- function = "avb"; +- }; +- +- du0_pins: du0 { +- groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out"; +- function = "du0"; +- }; +- +- i2c4_pins: i2c4 { +- groups = "i2c4_e"; +- function = "i2c4"; +- }; +- +- i2c3_pins: i2c3 { +- groups = "i2c3_c"; +- function = "i2c3"; +- }; +- +- mmc_pins_uhs: mmc_uhs { +- groups = "mmc_data8", "mmc_ctrl"; +- function = "mmc"; +- power-source = <1800>; +- }; +- +- qspi0_pins: qspi0 { +- groups = "qspi0_ctrl", "qspi0_data2"; +- function = "qspi0"; +- }; +- +- scif1_pins: scif1 { +- groups = "scif1_data_b"; +- function = "scif1"; +- }; +- +- sdhi2_pins: sd2 { +- groups = "sdhi2_data4", "sdhi2_ctrl"; +- function = "sdhi2"; +- power-source = <3300>; +- }; +- +- sdhi2_pins_uhs: sd2_uhs { +- groups = "sdhi2_data4", "sdhi2_ctrl"; +- function = "sdhi2"; +- power-source = <1800>; +- }; +- +- usb0_pins: usb0 { +- groups = "usb0"; +- function = "usb0"; +- }; +- +- usb1_pins: usb1 { +- groups = "usb1"; +- function = "usb1"; +- }; +-}; +- +-&qspi0 { +- pinctrl-0 = <&qspi0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- /* WARNING - This device contains the bootloader. Handle with care. */ +- flash: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "issi,is25lp016d", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <133000000>; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <1>; +- m25p,fast-read; +- spi-cpol; +- spi-cpha; +- }; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&scif1 { +- pinctrl-0 = <&scif1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&sdhi1 { +- pinctrl-0 = <&mmc_pins_uhs>; +- pinctrl-names = "state_uhs"; +- +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_1p8v>; +- bus-width = <8>; +- mmc-hs200-1_8v; +- non-removable; +- fixed-emmc-driver-type = <1>; +- status = "okay"; +-}; +- +-&sdhi2 { +- pinctrl-0 = <&sdhi2_pins>; +- pinctrl-1 = <&sdhi2_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <&vccq_sdhi2>; +- bus-width = <4>; +- cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; +- sd-uhs-sdr50; +- status = "okay"; +-}; +- +-&usb2_phy0 { +- status = "okay"; +-}; +- +-&usb2_phy1 { +- status = "okay"; +-}; +- +-&usbphy0 { +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&usbphy1 { +- pinctrl-0 = <&usb1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a77470.dtsi b/scripts/dtc/include-prefixes/arm/r8a77470.dtsi +deleted file mode 100644 +index 13ef1e9bf4d5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a77470.dtsi ++++ /dev/null +@@ -1,1027 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the r8a77470 SoC +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +- +-#include +-#include +-#include +-#include +-/ { +- compatible = "renesas,r8a77470"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0>; +- clock-frequency = <1000000000>; +- clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; +- power-domains = <&sysc R8A77470_PD_CA7_CPU0>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA7>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <1>; +- clock-frequency = <1000000000>; +- clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; +- power-domains = <&sysc R8A77470_PD_CA7_CPU1>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA7>; +- }; +- +- L2_CA7: cache-controller-0 { +- compatible = "cache"; +- cache-unified; +- cache-level = <2>; +- power-domains = <&sysc R8A77470_PD_CA7_SCU>; +- }; +- }; +- +- /* External root clock */ +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- /* External SCIF clock */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a77470-wdt", +- "renesas,rcar-gen2-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a77470", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 23>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a77470", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 23>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a77470", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a77470", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 30>; +- gpio-reserved-ranges = <17 10>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a77470", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a77470", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a77470"; +- reg = <0 0xe6060000 0 0x118>; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a77470-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>, <&usb_extal_clk>; +- clock-names = "extal", "usb_extal"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- apmu@e6151000 { +- compatible = "renesas,r8a77470-apmu", "renesas,apmu"; +- reg = <0 0xe6151000 0 0x188>; +- cpus = <&cpu0>, <&cpu1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a77470-rst"; +- reg = <0 0xe6160000 0 0x100>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a77470-sysc"; +- reg = <0 0xe6180000 0 0x200>; +- #power-domain-cells = <1>; +- }; +- +- irqc: interrupt-controller@e61c0000 { +- compatible = "renesas,irqc-r8a77470", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- icram0: sram@e63a0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63a0000 0 0x12000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63a0000 0x12000>; +- }; +- +- icram1: sram@e63c0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63c0000 0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63c0000 0x1000>; +- +- smp-sram@0 { +- compatible = "renesas,smp-sram"; +- reg = <0 0x100>; +- }; +- }; +- +- icram2: sram@e6300000 { +- compatible = "mmio-sram"; +- reg = <0 0xe6300000 0 0x20000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe6300000 0x20000>; +- }; +- +- i2c0: i2c@e6508000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77470", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6518000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77470", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6518000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6530000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77470", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6530000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e6540000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77470", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6540000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e6520000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77470", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6520000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 927>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 927>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- hsusb0: hsusb@e6590000 { +- compatible = "renesas,usbhs-r8a77470", +- "renesas,rcar-gen2-usbhs"; +- reg = <0 0xe6590000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 704>; +- dmas = <&usb_dmac00 0>, <&usb_dmac00 1>, +- <&usb_dmac10 0>, <&usb_dmac10 1>; +- dma-names = "ch0", "ch1", "ch2", "ch3"; +- renesas,buswait = <4>; +- phys = <&usb0 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 704>; +- status = "disabled"; +- }; +- +- usbphy0: usb-phy@e6590100 { +- compatible = "renesas,usb-phy-r8a77470", +- "renesas,rcar-gen2-usb-phy"; +- reg = <0 0xe6590100 0 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cpg CPG_MOD 704>; +- clock-names = "usbhs"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 704>; +- status = "disabled"; +- +- usb0: usb-channel@0 { +- reg = <0>; +- #phy-cells = <1>; +- }; +- }; +- +- hsusb1: hsusb@e6598000 { +- compatible = "renesas,usbhs-r8a77470", +- "renesas,rcar-gen2-usbhs"; +- reg = <0 0xe6598000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 706>; +- dmas = <&usb_dmac01 0>, <&usb_dmac01 1>, +- <&usb_dmac11 0>, <&usb_dmac11 1>; +- dma-names = "ch0", "ch1", "ch2", "ch3"; +- renesas,buswait = <4>; +- /* We need to turn on usbphy0 to make usbphy1 to work */ +- phys = <&usb1 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 706>; +- status = "disabled"; +- }; +- +- usbphy1: usb-phy@e6598100 { +- compatible = "renesas,usb-phy-r8a77470", +- "renesas,rcar-gen2-usb-phy"; +- reg = <0 0xe6598100 0 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cpg CPG_MOD 706>; +- clock-names = "usbhs"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 706>; +- status = "disabled"; +- +- usb1: usb-channel@0 { +- reg = <0>; +- #phy-cells = <1>; +- }; +- }; +- +- usb_dmac00: dma-controller@e65a0000 { +- compatible = "renesas,r8a77470-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65a0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 330>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 330>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac10: dma-controller@e65b0000 { +- compatible = "renesas,r8a77470-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65b0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 331>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 331>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac01: dma-controller@e65a8000 { +- compatible = "renesas,r8a77470-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65a8000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 326>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 326>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac11: dma-controller@e65b8000 { +- compatible = "renesas,r8a77470-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65b8000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 327>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 327>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a77470", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- dmac1: dma-controller@e6720000 { +- compatible = "renesas,dmac-r8a77470", +- "renesas,rcar-dmac"; +- reg = <0 0xe6720000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a77470", +- "renesas,etheravb-rcar-gen2"; +- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- qspi0: spi@e6b10000 { +- compatible = "renesas,qspi-r8a77470", "renesas,qspi"; +- reg = <0 0xe6b10000 0 0x2c>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 918>; +- dmas = <&dmac0 0x17>, <&dmac0 0x18>, +- <&dmac1 0x17>, <&dmac1 0x18>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- resets = <&cpg 918>; +- status = "disabled"; +- }; +- +- qspi1: spi@ee200000 { +- compatible = "renesas,qspi-r8a77470", "renesas,qspi"; +- reg = <0 0xee200000 0 0x2c>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 917>; +- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, +- <&dmac1 0xd1>, <&dmac1 0xd2>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- resets = <&cpg 917>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a77470", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e60000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 721>, +- <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x29>, <&dmac0 0x2a>, +- <&dmac1 0x29>, <&dmac1 0x2a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 721>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a77470", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e68000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 720>, +- <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, +- <&dmac1 0x2d>, <&dmac1 0x2e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 720>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e58000 { +- compatible = "renesas,scif-r8a77470", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e58000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 719>, +- <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, +- <&dmac1 0x2b>, <&dmac1 0x2c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 719>; +- status = "disabled"; +- }; +- +- scif3: serial@e6ea8000 { +- compatible = "renesas,scif-r8a77470", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ea8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 718>, +- <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2f>, <&dmac0 0x30>, +- <&dmac1 0x2f>, <&dmac1 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 718>; +- status = "disabled"; +- }; +- +- scif4: serial@e6ee0000 { +- compatible = "renesas,scif-r8a77470", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ee0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 715>, +- <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, +- <&dmac1 0xfb>, <&dmac1 0xfc>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 715>; +- status = "disabled"; +- }; +- +- scif5: serial@e6ee8000 { +- compatible = "renesas,scif-r8a77470", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ee8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 714>, +- <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, +- <&dmac1 0xfd>, <&dmac1 0xfe>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 714>; +- status = "disabled"; +- }; +- +- hscif0: serial@e62c0000 { +- compatible = "renesas,hscif-r8a77470", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 717>, +- <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x39>, <&dmac0 0x3a>, +- <&dmac1 0x39>, <&dmac1 0x3a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 717>; +- status = "disabled"; +- }; +- +- hscif1: serial@e62c8000 { +- compatible = "renesas,hscif-r8a77470", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c8000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>, +- <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, +- <&dmac1 0x4d>, <&dmac1 0x4e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- }; +- +- hscif2: serial@e62d0000 { +- compatible = "renesas,hscif-r8a77470", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62d0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 713>, +- <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, +- <&dmac1 0x3b>, <&dmac1 0x3c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 713>; +- status = "disabled"; +- }; +- +- pwm0: pwm@e6e30000 { +- compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; +- reg = <0 0xe6e30000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm1: pwm@e6e31000 { +- compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; +- reg = <0 0xe6e31000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm2: pwm@e6e32000 { +- compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; +- reg = <0 0xe6e32000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm3: pwm@e6e33000 { +- compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; +- reg = <0 0xe6e33000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm4: pwm@e6e34000 { +- compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; +- reg = <0 0xe6e34000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm5: pwm@e6e35000 { +- compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; +- reg = <0 0xe6e35000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm6: pwm@e6e36000 { +- compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; +- reg = <0 0xe6e36000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a77470", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef0000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 811>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 811>; +- status = "disabled"; +- }; +- +- vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a77470", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef1000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 810>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 810>; +- status = "disabled"; +- }; +- +- ohci0: usb@ee080000 { +- compatible = "generic-ohci"; +- reg = <0 0xee080000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>; +- phys = <&usb0 0>, <&usb2_phy0>; +- phy-names = "usb"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- status = "disabled"; +- }; +- +- ehci0: usb@ee080100 { +- compatible = "generic-ehci"; +- reg = <0 0xee080100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>; +- phys = <&usb0 0>, <&usb2_phy0>; +- phy-names = "usb"; +- companion = <&ohci0>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- status = "disabled"; +- }; +- +- usb2_phy0: usb-phy@ee080200 { +- compatible = "renesas,usb2-phy-r8a77470"; +- reg = <0 0xee080200 0 0x700>; +- clocks = <&cpg CPG_MOD 703>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- ohci1: usb@ee0c0000 { +- compatible = "generic-ohci"; +- reg = <0 0xee0c0000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 705>; +- phys = <&usb0 1>, <&usb2_phy1>, <&usb1 0>; +- phy-names = "usb"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 705>; +- status = "disabled"; +- }; +- +- ehci1: usb@ee0c0100 { +- compatible = "generic-ehci"; +- reg = <0 0xee0c0100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 705>; +- phys = <&usb0 1>, <&usb2_phy1>, <&usb1 0>; +- phy-names = "usb"; +- companion = <&ohci1>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 705>; +- status = "disabled"; +- }; +- +- usb2_phy1: usb-phy@ee0c0200 { +- compatible = "renesas,usb2-phy-r8a77470"; +- reg = <0 0xee0c0200 0 0x700>; +- clocks = <&cpg CPG_MOD 705>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 705>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a77470", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee100000 0 0x328>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- dmas = <&dmac0 0xcd>, <&dmac0 0xce>, +- <&dmac1 0xcd>, <&dmac1 0xce>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <156000000>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ee300000 { +- compatible = "renesas,sdhi-mmc-r8a77470"; +- reg = <0 0xee300000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 313>; +- max-frequency = <156000000>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 313>; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ee160000 { +- compatible = "renesas,sdhi-r8a77470", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee160000 0 0x328>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 312>; +- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, +- <&dmac1 0xd3>, <&dmac1 0xd4>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <78000000>; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 312>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1001000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, +- <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a77470"; +- reg = <0 0xfeb00000 0 0x40000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; +- clock-names = "du.0", "du.1"; +- resets = <&cpg 724>; +- reset-names = "du.0"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb0: endpoint { +- }; +- }; +- port@1 { +- reg = <1>; +- du_out_rgb1: endpoint { +- }; +- }; +- port@2 { +- reg = <2>; +- du_out_lvds0: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@ff000044 { +- compatible = "renesas,prr"; +- reg = <0 0xff000044 0 4>; +- }; +- +- cmt0: timer@ffca0000 { +- compatible = "renesas,r8a77470-cmt0", +- "renesas,rcar-gen2-cmt0"; +- reg = <0 0xffca0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a77470-cmt1", +- "renesas,rcar-gen2-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 329>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; +- resets = <&cpg 329>; +- status = "disabled"; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +- }; +- +- /* External USB clock - can be overridden by the board */ +- usb_extal_clk: usb_extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <48000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7778-bockw.dts b/scripts/dtc/include-prefixes/arm/r8a7778-bockw.dts +deleted file mode 100644 +index 6c7b07c4b9d3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7778-bockw.dts ++++ /dev/null +@@ -1,229 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Reference Device Tree Source for the R-Car M1A (R8A77781) Bock-W board +- * +- * Copyright (C) 2013 Renesas Solutions Corp. +- * Copyright (C) 2013 Kuninori Morimoto +- * +- * based on r8a7779 +- * +- * Copyright (C) 2013 Renesas Solutions Corp. +- * Copyright (C) 2013 Simon Horman +- */ +- +-/dts-v1/; +-#include "r8a7778.dtsi" +-#include +-#include +- +-/ { +- model = "bockw"; +- compatible = "renesas,bockw", "renesas,r8a7778"; +- +- aliases { +- serial0 = &scif0; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x10000000>; +- }; +- +- fixedregulator3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- +- simple-audio-card,format = "left_j"; +- simple-audio-card,bitclock-master = <&sndcodec>; +- simple-audio-card,frame-master = <&sndcodec>; +- +- sndcpu: simple-audio-card,cpu { +- sound-dai = <&rcar_sound>; +- }; +- +- sndcodec: simple-audio-card,codec { +- sound-dai = <&ak4643>; +- system-clock-frequency = <11289600>; +- }; +- }; +-}; +- +-&bsc { +- ethernet@18300000 { +- compatible = "smsc,lan9220", "smsc,lan9115"; +- reg = <0x18300000 0x1000>; +- +- phy-mode = "mii"; +- interrupt-parent = <&irqpin>; +- interrupts = <0 IRQ_TYPE_EDGE_FALLING>; +- reg-io-width = <4>; +- vddvario-supply = <&fixedregulator3v3>; +- vdd33a-supply = <&fixedregulator3v3>; +- }; +-}; +- +-&extal_clk { +- clock-frequency = <33333333>; +-}; +- +-&i2c0 { +- status = "okay"; +- +- ak4643: codec@12 { +- compatible = "asahi-kasei,ak4643"; +- #sound-dai-cells = <0>; +- reg = <0x12>; +- }; +- +- camera@41 { +- compatible = "oki,ml86v7667"; +- reg = <0x41>; +- }; +- +- camera@43 { +- compatible = "oki,ml86v7667"; +- reg = <0x43>; +- }; +- +- rx8581: rtc@51 { +- compatible = "epson,rx8581"; +- reg = <0x51>; +- }; +-}; +- +-&mmcif { +- pinctrl-0 = <&mmc_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <&fixedregulator3v3>; +- bus-width = <8>; +- broken-cd; +- status = "okay"; +-}; +- +-&irqpin { +- status = "okay"; +-}; +- +-&tmu0 { +- status = "okay"; +-}; +- +-&pfc { +- pinctrl-0 = <&scif_clk_pins>; +- pinctrl-names = "default"; +- +- scif0_pins: scif0 { +- groups = "scif0_data_a", "scif0_ctrl"; +- function = "scif0"; +- }; +- +- scif_clk_pins: scif_clk { +- groups = "scif_clk"; +- function = "scif_clk"; +- }; +- +- mmc_pins: mmc { +- groups = "mmc_data8", "mmc_ctrl"; +- function = "mmc"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- }; +- sdhi0_pup_pins: sd0_pup { +- groups = "sdhi0_cd", "sdhi0_wp"; +- function = "sdhi0"; +- bias-pull-up; +- }; +- +- hspi0_pins: hspi0 { +- groups = "hspi0_a"; +- function = "hspi0"; +- }; +- +- usb0_pins: usb0 { +- groups = "usb0"; +- function = "usb0"; +- }; +- +- usb1_pins: usb1 { +- groups = "usb1"; +- function = "usb1"; +- }; +- +- vin0_pins: vin0 { +- groups = "vin0_data8", "vin0_clk"; +- function = "vin0"; +- }; +- +- vin1_pins: vin1 { +- groups = "vin1_data8", "vin1_clk"; +- function = "vin1"; +- }; +-}; +- +-&rcar_sound { +- /* Single DAI */ +- #sound-dai-cells = <0>; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>, <&sdhi0_pup_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <&fixedregulator3v3>; +- bus-width = <4>; +- status = "okay"; +- wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; +-}; +- +-&hspi0 { +- pinctrl-0 = <&hspi0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- flash: flash@0 { +- compatible = "spansion,s25fl008k", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <104000000>; +- m25p,fast-read; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "data(spi)"; +- reg = <0x00000000 0x00100000>; +- }; +- }; +- }; +-}; +- +-&scif0 { +- pinctrl-0 = <&scif0_pins>; +- pinctrl-names = "default"; +- +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&scif_clk { +- clock-frequency = <14745600>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7778.dtsi b/scripts/dtc/include-prefixes/arm/r8a7778.dtsi +deleted file mode 100644 +index 95efbafb0b70..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7778.dtsi ++++ /dev/null +@@ -1,671 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Car M1A (R8A77781) SoC +- * +- * Copyright (C) 2013 Renesas Solutions Corp. +- * Copyright (C) 2013 Kuninori Morimoto +- * +- * based on r8a7779 +- * +- * Copyright (C) 2013 Renesas Solutions Corp. +- * Copyright (C) 2013 Simon Horman +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r8a7778"; +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- clock-frequency = <800000000>; +- clocks = <&z_clk>; +- }; +- }; +- +- aliases { +- spi0 = &hspi0; +- spi1 = &hspi1; +- spi2 = &hspi2; +- }; +- +- bsc: bus@1c000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x1c000000>; +- }; +- +- ether: ethernet@fde00000 { +- compatible = "renesas,ether-r8a7778", +- "renesas,rcar-gen1-ether"; +- reg = <0xfde00000 0x400>; +- interrupts = ; +- clocks = <&mstp1_clks R8A7778_CLK_ETHER>; +- power-domains = <&cpg_clocks>; +- phy-mode = "rmii"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@fe438000 { +- compatible = "arm,pl390"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0xfe438000 0x1000>, +- <0xfe430000 0x100>; +- }; +- +- /* irqpin: IRQ0 - IRQ3 */ +- irqpin: interrupt-controller@fe78001c { +- compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin"; +- #interrupt-cells = <2>; +- interrupt-controller; +- status = "disabled"; /* default off */ +- reg = <0xfe78001c 4>, +- <0xfe780010 4>, +- <0xfe780024 4>, +- <0xfe780044 4>, +- <0xfe780064 4>, +- <0xfe780000 4>; +- interrupts = , +- , +- , +- ; +- sense-bitfield-width = <2>; +- }; +- +- gpio0: gpio@ffc40000 { +- compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; +- reg = <0xffc40000 0x2c>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gpio1: gpio@ffc41000 { +- compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; +- reg = <0xffc41000 0x2c>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gpio2: gpio@ffc42000 { +- compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; +- reg = <0xffc42000 0x2c>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gpio3: gpio@ffc43000 { +- compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; +- reg = <0xffc43000 0x2c>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gpio4: gpio@ffc44000 { +- compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; +- reg = <0xffc44000 0x2c>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 27>; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- pfc: pinctrl@fffc0000 { +- compatible = "renesas,pfc-r8a7778"; +- reg = <0xfffc0000 0x118>; +- }; +- +- i2c0: i2c@ffc70000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; +- reg = <0xffc70000 0x1000>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7778_CLK_I2C0>; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- i2c1: i2c@ffc71000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; +- reg = <0xffc71000 0x1000>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7778_CLK_I2C1>; +- power-domains = <&cpg_clocks>; +- i2c-scl-internal-delay-ns = <5>; +- status = "disabled"; +- }; +- +- i2c2: i2c@ffc72000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; +- reg = <0xffc72000 0x1000>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7778_CLK_I2C2>; +- power-domains = <&cpg_clocks>; +- i2c-scl-internal-delay-ns = <5>; +- status = "disabled"; +- }; +- +- i2c3: i2c@ffc73000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; +- reg = <0xffc73000 0x1000>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7778_CLK_I2C3>; +- power-domains = <&cpg_clocks>; +- i2c-scl-internal-delay-ns = <5>; +- status = "disabled"; +- }; +- +- tmu0: timer@ffd80000 { +- compatible = "renesas,tmu-r8a7778", "renesas,tmu"; +- reg = <0xffd80000 0x30>; +- interrupts = , +- , +- ; +- clocks = <&mstp0_clks R8A7778_CLK_TMU0>; +- clock-names = "fck"; +- power-domains = <&cpg_clocks>; +- +- #renesas,channels = <3>; +- +- status = "disabled"; +- }; +- +- tmu1: timer@ffd81000 { +- compatible = "renesas,tmu-r8a7778", "renesas,tmu"; +- reg = <0xffd81000 0x30>; +- interrupts = , +- , +- ; +- clocks = <&mstp0_clks R8A7778_CLK_TMU1>; +- clock-names = "fck"; +- power-domains = <&cpg_clocks>; +- +- #renesas,channels = <3>; +- +- status = "disabled"; +- }; +- +- tmu2: timer@ffd82000 { +- compatible = "renesas,tmu-r8a7778", "renesas,tmu"; +- reg = <0xffd82000 0x30>; +- interrupts = , +- , +- ; +- clocks = <&mstp0_clks R8A7778_CLK_TMU2>; +- clock-names = "fck"; +- power-domains = <&cpg_clocks>; +- +- #renesas,channels = <3>; +- +- status = "disabled"; +- }; +- +- rcar_sound: sound@ffd90000 { +- /* +- * #sound-dai-cells is required +- * +- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; +- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; +- */ +- compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1"; +- reg = <0xffd90000 0x1000>, /* SRU */ +- <0xffd91000 0x240>, /* SSI */ +- <0xfffe0000 0x24>; /* ADG */ +- clocks = <&mstp3_clks R8A7778_CLK_SSI8>, +- <&mstp3_clks R8A7778_CLK_SSI7>, +- <&mstp3_clks R8A7778_CLK_SSI6>, +- <&mstp3_clks R8A7778_CLK_SSI5>, +- <&mstp3_clks R8A7778_CLK_SSI4>, +- <&mstp0_clks R8A7778_CLK_SSI3>, +- <&mstp0_clks R8A7778_CLK_SSI2>, +- <&mstp0_clks R8A7778_CLK_SSI1>, +- <&mstp0_clks R8A7778_CLK_SSI0>, +- <&mstp5_clks R8A7778_CLK_SRU_SRC8>, +- <&mstp5_clks R8A7778_CLK_SRU_SRC7>, +- <&mstp5_clks R8A7778_CLK_SRU_SRC6>, +- <&mstp5_clks R8A7778_CLK_SRU_SRC5>, +- <&mstp5_clks R8A7778_CLK_SRU_SRC4>, +- <&mstp5_clks R8A7778_CLK_SRU_SRC3>, +- <&mstp5_clks R8A7778_CLK_SRU_SRC2>, +- <&mstp5_clks R8A7778_CLK_SRU_SRC1>, +- <&mstp5_clks R8A7778_CLK_SRU_SRC0>, +- <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, +- <&cpg_clocks R8A7778_CLK_S1>; +- clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", +- "ssi.3", "ssi.2", "ssi.1", "ssi.0", +- "src.8", "src.7", "src.6", "src.5", "src.4", +- "src.3", "src.2", "src.1", "src.0", +- "clk_a", "clk_b", "clk_c", "clk_i"; +- +- status = "disabled"; +- +- rcar_sound,src { +- src3: src-3 { }; +- src4: src-4 { }; +- src5: src-5 { }; +- src6: src-6 { }; +- src7: src-7 { }; +- src8: src-8 { }; +- src9: src-9 { }; +- }; +- +- rcar_sound,ssi { +- ssi3: ssi-3 { interrupts = ; }; +- ssi4: ssi-4 { interrupts = ; }; +- ssi5: ssi-5 { interrupts = ; }; +- ssi6: ssi-6 { interrupts = ; }; +- ssi7: ssi-7 { interrupts = ; }; +- ssi8: ssi-8 { interrupts = ; }; +- ssi9: ssi-9 { interrupts = ; }; +- }; +- }; +- +- scif0: serial@ffe40000 { +- compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", +- "renesas,scif"; +- reg = <0xffe40000 0x100>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7778_CLK_SCIF0>, +- <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- scif1: serial@ffe41000 { +- compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", +- "renesas,scif"; +- reg = <0xffe41000 0x100>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7778_CLK_SCIF1>, +- <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- scif2: serial@ffe42000 { +- compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", +- "renesas,scif"; +- reg = <0xffe42000 0x100>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7778_CLK_SCIF2>, +- <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- scif3: serial@ffe43000 { +- compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", +- "renesas,scif"; +- reg = <0xffe43000 0x100>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7778_CLK_SCIF3>, +- <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- scif4: serial@ffe44000 { +- compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", +- "renesas,scif"; +- reg = <0xffe44000 0x100>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7778_CLK_SCIF4>, +- <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- scif5: serial@ffe45000 { +- compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", +- "renesas,scif"; +- reg = <0xffe45000 0x100>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7778_CLK_SCIF5>, +- <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- hscif0: serial@ffe48000 { +- compatible = "renesas,hscif-r8a7778", +- "renesas,rcar-gen1-hscif", "renesas,hscif"; +- reg = <0xffe48000 96>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>, +- <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- hscif1: serial@ffe49000 { +- compatible = "renesas,hscif-r8a7778", +- "renesas,rcar-gen1-hscif", "renesas,hscif"; +- reg = <0xffe49000 96>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>, +- <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- mmcif: mmc@ffe4e000 { +- compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif"; +- reg = <0xffe4e000 0x100>; +- interrupts = ; +- clocks = <&mstp3_clks R8A7778_CLK_MMC>; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- sdhi0: mmc@ffe4c000 { +- compatible = "renesas,sdhi-r8a7778", +- "renesas,rcar-gen1-sdhi"; +- reg = <0xffe4c000 0x100>; +- interrupts = ; +- clocks = <&mstp3_clks R8A7778_CLK_SDHI0>; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ffe4d000 { +- compatible = "renesas,sdhi-r8a7778", +- "renesas,rcar-gen1-sdhi"; +- reg = <0xffe4d000 0x100>; +- interrupts = ; +- clocks = <&mstp3_clks R8A7778_CLK_SDHI1>; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ffe4f000 { +- compatible = "renesas,sdhi-r8a7778", +- "renesas,rcar-gen1-sdhi"; +- reg = <0xffe4f000 0x100>; +- interrupts = ; +- clocks = <&mstp3_clks R8A7778_CLK_SDHI2>; +- power-domains = <&cpg_clocks>; +- status = "disabled"; +- }; +- +- hspi0: spi@fffc7000 { +- compatible = "renesas,hspi-r8a7778", "renesas,hspi"; +- reg = <0xfffc7000 0x18>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7778_CLK_HSPI>; +- power-domains = <&cpg_clocks>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- hspi1: spi@fffc8000 { +- compatible = "renesas,hspi-r8a7778", "renesas,hspi"; +- reg = <0xfffc8000 0x18>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7778_CLK_HSPI>; +- power-domains = <&cpg_clocks>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- hspi2: spi@fffc6000 { +- compatible = "renesas,hspi-r8a7778", "renesas,hspi"; +- reg = <0xfffc6000 0x18>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7778_CLK_HSPI>; +- power-domains = <&cpg_clocks>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* External input clock */ +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* External SCIF clock */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- /* Special CPG clocks */ +- cpg_clocks: cpg_clocks@ffc80000 { +- compatible = "renesas,r8a7778-cpg-clocks"; +- reg = <0xffc80000 0x80>; +- #clock-cells = <1>; +- clocks = <&extal_clk>; +- clock-output-names = "plla", "pllb", "b", +- "out", "p", "s", "s1"; +- #power-domain-cells = <0>; +- }; +- +- /* Audio clocks; frequencies are set by boards if applicable. */ +- audio_clk_a: audio_clk_a { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- audio_clk_b: audio_clk_b { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- audio_clk_c: audio_clk_c { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* Fixed ratio clocks */ +- g_clk: g { +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks R8A7778_CLK_PLLA>; +- #clock-cells = <0>; +- clock-div = <12>; +- clock-mult = <1>; +- }; +- i_clk: i { +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks R8A7778_CLK_PLLA>; +- #clock-cells = <0>; +- clock-div = <1>; +- clock-mult = <1>; +- }; +- s3_clk: s3 { +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks R8A7778_CLK_PLLA>; +- #clock-cells = <0>; +- clock-div = <4>; +- clock-mult = <1>; +- }; +- s4_clk: s4 { +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks R8A7778_CLK_PLLA>; +- #clock-cells = <0>; +- clock-div = <8>; +- clock-mult = <1>; +- }; +- z_clk: z { +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks R8A7778_CLK_PLLB>; +- #clock-cells = <0>; +- clock-div = <1>; +- clock-mult = <1>; +- }; +- +- /* Gate clocks */ +- mstp0_clks: mstp0_clks@ffc80030 { +- compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xffc80030 4>; +- clocks = <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_S>, +- <&cpg_clocks R8A7778_CLK_S>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_S>; +- #clock-cells = <1>; +- clock-indices = < +- R8A7778_CLK_I2C0 R8A7778_CLK_I2C1 +- R8A7778_CLK_I2C2 R8A7778_CLK_I2C3 +- R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1 +- R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3 +- R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5 +- R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1 +- R8A7778_CLK_TMU0 R8A7778_CLK_TMU1 +- R8A7778_CLK_TMU2 R8A7778_CLK_SSI0 +- R8A7778_CLK_SSI1 R8A7778_CLK_SSI2 +- R8A7778_CLK_SSI3 R8A7778_CLK_SRU +- R8A7778_CLK_HSPI +- >; +- clock-output-names = +- "i2c0", "i2c1", "i2c2", "i2c3", "scif0", +- "scif1", "scif2", "scif3", "scif4", "scif5", +- "hscif0", "hscif1", +- "tmu0", "tmu1", "tmu2", "ssi0", "ssi1", +- "ssi2", "ssi3", "sru", "hspi"; +- }; +- mstp1_clks: mstp1_clks@ffc80034 { +- compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xffc80034 4>, <0xffc80044 4>; +- clocks = <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_S>, +- <&cpg_clocks R8A7778_CLK_S>, +- <&cpg_clocks R8A7778_CLK_P>; +- #clock-cells = <1>; +- clock-indices = < +- R8A7778_CLK_ETHER R8A7778_CLK_VIN0 +- R8A7778_CLK_VIN1 R8A7778_CLK_USB +- >; +- clock-output-names = +- "ether", "vin0", "vin1", "usb"; +- }; +- mstp3_clks: mstp3_clks@ffc8003c { +- compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xffc8003c 4>; +- clocks = <&s4_clk>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>; +- #clock-cells = <1>; +- clock-indices = < +- R8A7778_CLK_MMC R8A7778_CLK_SDHI0 +- R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2 +- R8A7778_CLK_SSI4 R8A7778_CLK_SSI5 +- R8A7778_CLK_SSI6 R8A7778_CLK_SSI7 +- R8A7778_CLK_SSI8 +- >; +- clock-output-names = +- "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4", +- "ssi5", "ssi6", "ssi7", "ssi8"; +- }; +- mstp5_clks: mstp5_clks@ffc80054 { +- compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xffc80054 4>; +- clocks = <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>, +- <&cpg_clocks R8A7778_CLK_P>; +- #clock-cells = <1>; +- clock-indices = < +- R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1 +- R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3 +- R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5 +- R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7 +- R8A7778_CLK_SRU_SRC8 +- >; +- clock-output-names = +- "sru-src0", "sru-src1", "sru-src2", +- "sru-src3", "sru-src4", "sru-src5", +- "sru-src6", "sru-src7", "sru-src8"; +- }; +- }; +- +- rst: reset-controller@ffcc0000 { +- compatible = "renesas,r8a7778-reset-wdt"; +- reg = <0xffcc0000 0x40>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7779-marzen.dts b/scripts/dtc/include-prefixes/arm/r8a7779-marzen.dts +deleted file mode 100644 +index 465845323495..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7779-marzen.dts ++++ /dev/null +@@ -1,264 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Car H1 (R8A77790) Marzen board +- * +- * Copyright (C) 2013 Renesas Solutions Corp. +- * Copyright (C) 2013 Simon Horman +- */ +- +-/dts-v1/; +-#include "r8a7779.dtsi" +-#include +-#include +- +-/ { +- model = "marzen"; +- compatible = "renesas,marzen", "renesas,r8a7779"; +- +- aliases { +- serial0 = &scif2; +- serial1 = &scif4; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x40000000>; +- }; +- +- fixedregulator3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vccq_sdhi0: regulator-vccq-sdhi0 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI0 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- ethernet@18000000 { +- compatible = "smsc,lan9220", "smsc,lan9115"; +- reg = <0x18000000 0x100>; +- pinctrl-0 = <ðernet_pins>; +- pinctrl-names = "default"; +- +- phy-mode = "mii"; +- interrupt-parent = <&irqpin0>; +- interrupts = <1 IRQ_TYPE_EDGE_FALLING>; +- smsc,irq-push-pull; +- reg-io-width = <4>; +- vddvario-supply = <&fixedregulator3v3>; +- vdd33a-supply = <&fixedregulator3v3>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led2 { +- gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; +- }; +- led3 { +- gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; +- }; +- led4 { +- gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- vga-encoder { +- compatible = "adi,adv7123"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- vga_enc_in: endpoint { +- remote-endpoint = <&du_out_rgb0>; +- }; +- }; +- port@1 { +- reg = <1>; +- vga_enc_out: endpoint { +- remote-endpoint = <&vga_in>; +- }; +- }; +- }; +- }; +- +- vga { +- compatible = "vga-connector"; +- +- port { +- vga_in: endpoint { +- remote-endpoint = <&vga_enc_out>; +- }; +- }; +- }; +- +- lvds-encoder { +- compatible = "thine,thc63lvdm83d"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds_enc_in: endpoint { +- remote-endpoint = <&du_out_rgb1>; +- }; +- }; +- port@1 { +- reg = <1>; +- lvds_connector: endpoint { +- }; +- }; +- }; +- }; +- +- x3_clk: x3-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <65000000>; +- }; +-}; +- +-&du { +- pinctrl-0 = <&du_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>; +- clock-names = "du.0", "dclkin.0"; +- +- ports { +- port@0 { +- endpoint { +- remote-endpoint = <&vga_enc_in>; +- }; +- }; +- port@1 { +- endpoint { +- remote-endpoint = <&lvds_enc_in>; +- }; +- }; +- }; +-}; +- +-&irqpin0 { +- status = "okay"; +-}; +- +-&extal_clk { +- clock-frequency = <31250000>; +-}; +- +-&tmu0 { +- status = "okay"; +-}; +- +-&pfc { +- pinctrl-0 = <&scif_clk_pins>; +- pinctrl-names = "default"; +- +- du_pins: du { +- du0 { +- groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0", "du0_clk_in"; +- function = "du0"; +- }; +- du1 { +- groups = "du1_rgb666", "du1_sync_1", "du1_clk_out"; +- function = "du1"; +- }; +- }; +- +- scif_clk_pins: scif_clk { +- groups = "scif_clk_b"; +- function = "scif_clk"; +- }; +- +- ethernet_pins: ethernet { +- intc { +- groups = "intc_irq1_b"; +- function = "intc"; +- }; +- lbsc { +- groups = "lbsc_ex_cs0"; +- function = "lbsc"; +- }; +- }; +- +- scif2_pins: scif2 { +- groups = "scif2_data_c"; +- function = "scif2"; +- }; +- +- scif4_pins: scif4 { +- groups = "scif4_data"; +- function = "scif4"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; +- function = "sdhi0"; +- }; +- +- hspi0_pins: hspi0 { +- groups = "hspi0"; +- function = "hspi0"; +- }; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&scif2 { +- pinctrl-0 = <&scif2_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scif4 { +- pinctrl-0 = <&scif4_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scif_clk { +- clock-frequency = <14745600>; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <&fixedregulator3v3>; +- vqmmc-supply = <&vccq_sdhi0>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&hspi0 { +- pinctrl-0 = <&hspi0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7779.dtsi b/scripts/dtc/include-prefixes/arm/r8a7779.dtsi +deleted file mode 100644 +index 39fc58f32df6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7779.dtsi ++++ /dev/null +@@ -1,652 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Car H1 (R8A77790) SoC +- * +- * Copyright (C) 2013 Renesas Solutions Corp. +- * Copyright (C) 2013 Simon Horman +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r8a7779"; +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- clock-frequency = <1000000000>; +- clocks = <&cpg_clocks R8A7779_CLK_Z>; +- }; +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <1>; +- clock-frequency = <1000000000>; +- clocks = <&cpg_clocks R8A7779_CLK_Z>; +- power-domains = <&sysc R8A7779_PD_ARM1>; +- }; +- cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <2>; +- clock-frequency = <1000000000>; +- clocks = <&cpg_clocks R8A7779_CLK_Z>; +- power-domains = <&sysc R8A7779_PD_ARM2>; +- }; +- cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <3>; +- clock-frequency = <1000000000>; +- clocks = <&cpg_clocks R8A7779_CLK_Z>; +- power-domains = <&sysc R8A7779_PD_ARM3>; +- }; +- }; +- +- aliases { +- spi0 = &hspi0; +- spi1 = &hspi1; +- spi2 = &hspi2; +- }; +- +- gic: interrupt-controller@f0001000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0xf0001000 0x1000>, +- <0xf0000100 0x100>; +- }; +- +- timer@f0000200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0xf0000200 0x100>; +- interrupts = ; +- clocks = <&cpg_clocks R8A7779_CLK_ZS>; +- }; +- +- timer@f0000600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0xf0000600 0x20>; +- interrupts = ; +- clocks = <&cpg_clocks R8A7779_CLK_ZS>; +- }; +- +- gpio0: gpio@ffc40000 { +- compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; +- reg = <0xffc40000 0x2c>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gpio1: gpio@ffc41000 { +- compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; +- reg = <0xffc41000 0x2c>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gpio2: gpio@ffc42000 { +- compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; +- reg = <0xffc42000 0x2c>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gpio3: gpio@ffc43000 { +- compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; +- reg = <0xffc43000 0x2c>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gpio4: gpio@ffc44000 { +- compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; +- reg = <0xffc44000 0x2c>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gpio5: gpio@ffc45000 { +- compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; +- reg = <0xffc45000 0x2c>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gpio6: gpio@ffc46000 { +- compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; +- reg = <0xffc46000 0x2c>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 192 9>; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- irqpin0: interrupt-controller@fe78001c { +- compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin"; +- #interrupt-cells = <2>; +- status = "disabled"; +- interrupt-controller; +- reg = <0xfe78001c 4>, +- <0xfe780010 4>, +- <0xfe780024 4>, +- <0xfe780044 4>, +- <0xfe780064 4>, +- <0xfe780000 4>; +- interrupts = , +- , +- , +- ; +- sense-bitfield-width = <2>; +- }; +- +- i2c0: i2c@ffc70000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; +- reg = <0xffc70000 0x1000>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7779_CLK_I2C0>; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- i2c1: i2c@ffc71000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; +- reg = <0xffc71000 0x1000>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7779_CLK_I2C1>; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- i2c-scl-internal-delay-ns = <5>; +- status = "disabled"; +- }; +- +- i2c2: i2c@ffc72000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; +- reg = <0xffc72000 0x1000>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7779_CLK_I2C2>; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- i2c-scl-internal-delay-ns = <5>; +- status = "disabled"; +- }; +- +- i2c3: i2c@ffc73000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; +- reg = <0xffc73000 0x1000>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7779_CLK_I2C3>; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- i2c-scl-internal-delay-ns = <5>; +- status = "disabled"; +- }; +- +- scif0: serial@ffe40000 { +- compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", +- "renesas,scif"; +- reg = <0xffe40000 0x100>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7779_CLK_SCIF0>, +- <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- scif1: serial@ffe41000 { +- compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", +- "renesas,scif"; +- reg = <0xffe41000 0x100>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7779_CLK_SCIF1>, +- <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- scif2: serial@ffe42000 { +- compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", +- "renesas,scif"; +- reg = <0xffe42000 0x100>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7779_CLK_SCIF2>, +- <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- scif3: serial@ffe43000 { +- compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", +- "renesas,scif"; +- reg = <0xffe43000 0x100>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7779_CLK_SCIF3>, +- <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- scif4: serial@ffe44000 { +- compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", +- "renesas,scif"; +- reg = <0xffe44000 0x100>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7779_CLK_SCIF4>, +- <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- scif5: serial@ffe45000 { +- compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", +- "renesas,scif"; +- reg = <0xffe45000 0x100>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7779_CLK_SCIF5>, +- <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- hscif0: serial@ffe48000 { +- compatible = "renesas,hscif-r8a7779", +- "renesas,rcar-gen1-hscif", "renesas,hscif"; +- reg = <0xffe48000 96>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7779_CLK_HSCIF0>, +- <&cpg_clocks R8A7779_CLK_S>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- hscif1: serial@ffe49000 { +- compatible = "renesas,hscif-r8a7779", +- "renesas,rcar-gen1-hscif", "renesas,hscif"; +- reg = <0xffe49000 96>; +- interrupts = ; +- clocks = <&mstp0_clks R8A7779_CLK_HSCIF1>, +- <&cpg_clocks R8A7779_CLK_S>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pfc: pinctrl@fffc0000 { +- compatible = "renesas,pfc-r8a7779"; +- reg = <0xfffc0000 0x23c>; +- }; +- +- thermal@ffc48000 { +- compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; +- reg = <0xffc48000 0x38>; +- }; +- +- tmu0: timer@ffd80000 { +- compatible = "renesas,tmu-r8a7779", "renesas,tmu"; +- reg = <0xffd80000 0x30>; +- interrupts = , +- , +- ; +- clocks = <&mstp0_clks R8A7779_CLK_TMU0>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- +- #renesas,channels = <3>; +- +- status = "disabled"; +- }; +- +- tmu1: timer@ffd81000 { +- compatible = "renesas,tmu-r8a7779", "renesas,tmu"; +- reg = <0xffd81000 0x30>; +- interrupts = , +- , +- ; +- clocks = <&mstp0_clks R8A7779_CLK_TMU1>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- +- #renesas,channels = <3>; +- +- status = "disabled"; +- }; +- +- tmu2: timer@ffd82000 { +- compatible = "renesas,tmu-r8a7779", "renesas,tmu"; +- reg = <0xffd82000 0x30>; +- interrupts = , +- , +- ; +- clocks = <&mstp0_clks R8A7779_CLK_TMU2>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- +- #renesas,channels = <3>; +- +- status = "disabled"; +- }; +- +- sata: sata@fc600000 { +- compatible = "renesas,sata-r8a7779"; +- reg = <0xfc600000 0x200000>; +- interrupts = ; +- clocks = <&mstp1_clks R8A7779_CLK_SATA>; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- sdhi0: mmc@ffe4c000 { +- compatible = "renesas,sdhi-r8a7779", +- "renesas,rcar-gen1-sdhi"; +- reg = <0xffe4c000 0x100>; +- interrupts = ; +- clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ffe4d000 { +- compatible = "renesas,sdhi-r8a7779", +- "renesas,rcar-gen1-sdhi"; +- reg = <0xffe4d000 0x100>; +- interrupts = ; +- clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ffe4e000 { +- compatible = "renesas,sdhi-r8a7779", +- "renesas,rcar-gen1-sdhi"; +- reg = <0xffe4e000 0x100>; +- interrupts = ; +- clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- sdhi3: mmc@ffe4f000 { +- compatible = "renesas,sdhi-r8a7779", +- "renesas,rcar-gen1-sdhi"; +- reg = <0xffe4f000 0x100>; +- interrupts = ; +- clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- hspi0: spi@fffc7000 { +- compatible = "renesas,hspi-r8a7779", "renesas,hspi"; +- reg = <0xfffc7000 0x18>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&mstp0_clks R8A7779_CLK_HSPI>; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- hspi1: spi@fffc8000 { +- compatible = "renesas,hspi-r8a7779", "renesas,hspi"; +- reg = <0xfffc8000 0x18>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&mstp0_clks R8A7779_CLK_HSPI>; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- hspi2: spi@fffc6000 { +- compatible = "renesas,hspi-r8a7779", "renesas,hspi"; +- reg = <0xfffc6000 0x18>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&mstp0_clks R8A7779_CLK_HSPI>; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- du: display@fff80000 { +- compatible = "renesas,du-r8a7779"; +- reg = <0xfff80000 0x40000>; +- interrupts = ; +- clocks = <&mstp1_clks R8A7779_CLK_DU>; +- clock-names = "du.0"; +- power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb0: endpoint { +- }; +- }; +- port@1 { +- reg = <1>; +- du_out_rgb1: endpoint { +- }; +- }; +- }; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* External root clock */ +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overriden by the board. */ +- clock-frequency = <0>; +- }; +- +- /* External SCIF clock */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- /* Special CPG clocks */ +- cpg_clocks: clocks@ffc80000 { +- compatible = "renesas,r8a7779-cpg-clocks"; +- reg = <0xffc80000 0x30>; +- clocks = <&extal_clk>; +- #clock-cells = <1>; +- clock-output-names = "plla", "z", "zs", "s", +- "s1", "p", "b", "out"; +- #power-domain-cells = <0>; +- }; +- +- /* Fixed factor clocks */ +- i_clk: i { +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks R8A7779_CLK_PLLA>; +- #clock-cells = <0>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- s3_clk: s3 { +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks R8A7779_CLK_PLLA>; +- #clock-cells = <0>; +- clock-div = <8>; +- clock-mult = <1>; +- }; +- s4_clk: s4 { +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks R8A7779_CLK_PLLA>; +- #clock-cells = <0>; +- clock-div = <16>; +- clock-mult = <1>; +- }; +- g_clk: g { +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks R8A7779_CLK_PLLA>; +- #clock-cells = <0>; +- clock-div = <24>; +- clock-mult = <1>; +- }; +- +- /* Gate clocks */ +- mstp0_clks: clocks@ffc80030 { +- compatible = "renesas,r8a7779-mstp-clocks", +- "renesas,cpg-mstp-clocks"; +- reg = <0xffc80030 4>; +- clocks = <&cpg_clocks R8A7779_CLK_S>, +- <&cpg_clocks R8A7779_CLK_P>, +- <&cpg_clocks R8A7779_CLK_P>, +- <&cpg_clocks R8A7779_CLK_P>, +- <&cpg_clocks R8A7779_CLK_S>, +- <&cpg_clocks R8A7779_CLK_S>, +- <&cpg_clocks R8A7779_CLK_P>, +- <&cpg_clocks R8A7779_CLK_P>, +- <&cpg_clocks R8A7779_CLK_P>, +- <&cpg_clocks R8A7779_CLK_P>, +- <&cpg_clocks R8A7779_CLK_P>, +- <&cpg_clocks R8A7779_CLK_P>, +- <&cpg_clocks R8A7779_CLK_P>, +- <&cpg_clocks R8A7779_CLK_P>, +- <&cpg_clocks R8A7779_CLK_P>, +- <&cpg_clocks R8A7779_CLK_P>; +- #clock-cells = <1>; +- clock-indices = < +- R8A7779_CLK_HSPI R8A7779_CLK_TMU2 +- R8A7779_CLK_TMU1 R8A7779_CLK_TMU0 +- R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0 +- R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4 +- R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 +- R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0 +- R8A7779_CLK_I2C3 R8A7779_CLK_I2C2 +- R8A7779_CLK_I2C1 R8A7779_CLK_I2C0 +- >; +- clock-output-names = +- "hspi", "tmu2", "tmu1", "tmu0", "hscif1", +- "hscif0", "scif5", "scif4", "scif3", "scif2", +- "scif1", "scif0", "i2c3", "i2c2", "i2c1", +- "i2c0"; +- }; +- mstp1_clks: clocks@ffc80034 { +- compatible = "renesas,r8a7779-mstp-clocks", +- "renesas,cpg-mstp-clocks"; +- reg = <0xffc80034 4>, <0xffc80044 4>; +- clocks = <&cpg_clocks R8A7779_CLK_P>, +- <&cpg_clocks R8A7779_CLK_P>, +- <&cpg_clocks R8A7779_CLK_S>, +- <&cpg_clocks R8A7779_CLK_S>, +- <&cpg_clocks R8A7779_CLK_S>, +- <&cpg_clocks R8A7779_CLK_S>, +- <&cpg_clocks R8A7779_CLK_P>, +- <&cpg_clocks R8A7779_CLK_P>, +- <&cpg_clocks R8A7779_CLK_P>, +- <&cpg_clocks R8A7779_CLK_S>; +- #clock-cells = <1>; +- clock-indices = < +- R8A7779_CLK_USB01 R8A7779_CLK_USB2 +- R8A7779_CLK_DU R8A7779_CLK_VIN2 +- R8A7779_CLK_VIN1 R8A7779_CLK_VIN0 +- R8A7779_CLK_ETHER R8A7779_CLK_SATA +- R8A7779_CLK_PCIE R8A7779_CLK_VIN3 +- >; +- clock-output-names = +- "usb01", "usb2", +- "du", "vin2", +- "vin1", "vin0", +- "ether", "sata", +- "pcie", "vin3"; +- }; +- mstp3_clks: clocks@ffc8003c { +- compatible = "renesas,r8a7779-mstp-clocks", +- "renesas,cpg-mstp-clocks"; +- reg = <0xffc8003c 4>; +- clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, +- <&s4_clk>, <&s4_clk>; +- #clock-cells = <1>; +- clock-indices = < +- R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2 +- R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0 +- R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 +- >; +- clock-output-names = +- "sdhi3", "sdhi2", "sdhi1", "sdhi0", +- "mmc1", "mmc0"; +- }; +- }; +- +- prr: chipid@ff000044 { +- compatible = "renesas,prr"; +- reg = <0xff000044 4>; +- }; +- +- rst: reset-controller@ffcc0000 { +- compatible = "renesas,r8a7779-reset-wdt"; +- reg = <0xffcc0000 0x48>; +- }; +- +- sysc: system-controller@ffd85000 { +- compatible = "renesas,r8a7779-sysc"; +- reg = <0xffd85000 0x0200>; +- #power-domain-cells = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7790-lager.dts b/scripts/dtc/include-prefixes/arm/r8a7790-lager.dts +deleted file mode 100644 +index fa6d986b5d46..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7790-lager.dts ++++ /dev/null +@@ -1,945 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Lager board +- * +- * Copyright (C) 2013-2014 Renesas Solutions Corp. +- * Copyright (C) 2014 Cogent Embedded, Inc. +- * Copyright (C) 2015-2016 Renesas Electronics Corporation +- */ +- +-/* +- * SSI-AK4643 +- * +- * SW1: 1: AK4643 +- * 2: CN22 +- * 3: ADV7511 +- * +- * This command is required when Playback/Capture +- * +- * amixer set "LINEOUT Mixer DACL" on +- * amixer set "DVC Out" 100% +- * amixer set "DVC In" 100% +- * +- * You can use Mute +- * +- * amixer set "DVC Out Mute" on +- * amixer set "DVC In Mute" on +- * +- * You can use Volume Ramp +- * +- * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" +- * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" +- * amixer set "DVC Out Ramp" on +- * aplay xxx.wav & +- * amixer set "DVC Out" 80% // Volume Down +- * amixer set "DVC Out" 100% // Volume Up +- */ +- +-/dts-v1/; +-#include "r8a7790.dtsi" +-#include +-#include +- +-/ { +- model = "Lager"; +- compatible = "renesas,lager", "renesas,r8a7790"; +- +- aliases { +- serial0 = &scif0; +- serial1 = &scifa1; +- i2c8 = &gpioi2c1; +- i2c9 = &gpioi2c2; +- i2c10 = &i2cexio0; +- i2c11 = &i2cexio1; +- i2c12 = &i2chdmi; +- i2c13 = &i2cpwr; +- mmc0 = &mmcif1; +- mmc1 = &sdhi0; +- mmc2 = &sdhi2; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x40000000>; +- }; +- +- memory@140000000 { +- device_type = "memory"; +- reg = <1 0x40000000 0 0xc0000000>; +- }; +- +- lbsc { +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- keyboard { +- compatible = "gpio-keys"; +- +- pinctrl-0 = <&keyboard_pins>; +- pinctrl-names = "default"; +- +- one { +- linux,code = ; +- label = "SW2-1"; +- wakeup-source; +- debounce-interval = <20>; +- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- }; +- two { +- linux,code = ; +- label = "SW2-2"; +- wakeup-source; +- debounce-interval = <20>; +- gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; +- }; +- three { +- linux,code = ; +- label = "SW2-3"; +- wakeup-source; +- debounce-interval = <20>; +- gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; +- }; +- four { +- linux,code = ; +- label = "SW2-4"; +- wakeup-source; +- debounce-interval = <20>; +- gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led6 { +- gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; +- }; +- led7 { +- gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; +- }; +- led8 { +- gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- fixedregulator3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcc_sdhi0: regulator-vcc-sdhi0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI0 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhi0: regulator-vccq-sdhi0 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI0 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- vcc_sdhi2: regulator-vcc-sdhi2 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI2 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhi2: regulator-vccq-sdhi2 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI2 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- audio_clock: audio_clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <11289600>; +- }; +- +- rsnd_ak4643: sound { +- compatible = "simple-audio-card"; +- +- simple-audio-card,format = "left_j"; +- simple-audio-card,bitclock-master = <&sndcodec>; +- simple-audio-card,frame-master = <&sndcodec>; +- +- sndcpu: simple-audio-card,cpu { +- sound-dai = <&rcar_sound>; +- }; +- +- sndcodec: simple-audio-card,codec { +- sound-dai = <&ak4643>; +- clocks = <&audio_clock>; +- }; +- }; +- +- vga-encoder { +- compatible = "adi,adv7123"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7123_in: endpoint { +- remote-endpoint = <&du_out_rgb>; +- }; +- }; +- port@1 { +- reg = <1>; +- adv7123_out: endpoint { +- remote-endpoint = <&vga_in>; +- }; +- }; +- }; +- }; +- +- vga { +- compatible = "vga-connector"; +- +- port { +- vga_in: endpoint { +- remote-endpoint = <&adv7123_out>; +- }; +- }; +- }; +- +- hdmi-in { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&adv7612_in>; +- }; +- }; +- }; +- +- cec_clock: cec-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <12000000>; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_out: endpoint { +- remote-endpoint = <&adv7511_out>; +- }; +- }; +- }; +- +- x2_clk: x2-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <148500000>; +- }; +- +- x13_clk: x13-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <148500000>; +- }; +- +- gpioi2c1: i2c-8 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "i2c-gpio"; +- status = "disabled"; +- scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <5>; +- }; +- +- gpioi2c2: i2c-9 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "i2c-gpio"; +- status = "disabled"; +- scl-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio5 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <5>; +- }; +- +- /* +- * IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only. +- * We use the I2C demuxer, so the desired IP core can be selected at runtime +- * depending on the use case (e.g. DMA with IIC0 or slave support with I2C0). +- * Note: For testing the I2C slave feature, it is convenient to connect this +- * bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and +- * instantiate the slave device at runtime according to the documentation. +- * You can then communicate with the slave via IIC3. +- * +- * IIC0/I2C0 does not appear to support fallback to GPIO. +- */ +- i2cexio0: i2c-10 { +- compatible = "i2c-demux-pinctrl"; +- i2c-parent = <&iic0>, <&i2c0>; +- i2c-bus-name = "i2c-exio0"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- /* +- * IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA). +- * This is similar to the arangement described for i2cexio0 (above) +- * with a fallback to GPIO also provided. +- */ +- i2cexio1: i2c-11 { +- compatible = "i2c-demux-pinctrl"; +- i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>; +- i2c-bus-name = "i2c-exio1"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- /* +- * IIC2 and I2C2 may be switched using pinmux. +- * A fallback to GPIO is also provided. +- */ +- i2chdmi: i2c-12 { +- compatible = "i2c-demux-pinctrl"; +- i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>; +- i2c-bus-name = "i2c-hdmi"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ak4643: codec@12 { +- compatible = "asahi-kasei,ak4643"; +- #sound-dai-cells = <0>; +- reg = <0x12>; +- }; +- +- composite-in@20 { +- compatible = "adi,adv7180"; +- reg = <0x20>; +- +- port { +- adv7180: endpoint { +- bus-width = <8>; +- remote-endpoint = <&vin1ep0>; +- }; +- }; +- }; +- +- hdmi@39 { +- compatible = "adi,adv7511w"; +- reg = <0x39>; +- interrupt-parent = <&gpio1>; +- interrupts = <15 IRQ_TYPE_LEVEL_LOW>; +- clocks = <&cec_clock>; +- clock-names = "cec"; +- +- adi,input-depth = <8>; +- adi,input-colorspace = "rgb"; +- adi,input-clock = "1x"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7511_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- adv7511_out: endpoint { +- remote-endpoint = <&hdmi_con_out>; +- }; +- }; +- }; +- }; +- +- hdmi-in@4c { +- compatible = "adi,adv7612"; +- reg = <0x4c>; +- interrupt-parent = <&gpio1>; +- interrupts = <20 IRQ_TYPE_LEVEL_LOW>; +- default-input = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7612_in: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- adv7612_out: endpoint { +- remote-endpoint = <&vin0ep2>; +- }; +- }; +- }; +- }; +- }; +- +- /* +- * IIC3 and I2C3 may be switched using pinmux. +- * IIC3/I2C3 does not appear to support fallback to GPIO. +- */ +- i2cpwr: i2c-13 { +- compatible = "i2c-demux-pinctrl"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_irq_pins>; +- i2c-parent = <&iic3>, <&i2c3>; +- i2c-bus-name = "i2c-pwr"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pmic@58 { +- compatible = "dlg,da9063"; +- reg = <0x58>; +- interrupt-parent = <&irqc0>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- +- rtc { +- compatible = "dlg,da9063-rtc"; +- }; +- +- wdt { +- compatible = "dlg,da9063-watchdog"; +- }; +- }; +- +- vdd_dvfs: regulator@68 { +- compatible = "dlg,da9210"; +- reg = <0x68>; +- interrupt-parent = <&irqc0>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +-}; +- +-&du { +- pinctrl-0 = <&du_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, +- <&x13_clk>, <&x2_clk>; +- clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1"; +- +- ports { +- port@0 { +- endpoint { +- remote-endpoint = <&adv7123_in>; +- }; +- }; +- }; +-}; +- +-&lvds0 { +- status = "okay"; +- +- ports { +- port@1 { +- endpoint { +- remote-endpoint = <&adv7511_in>; +- }; +- }; +- }; +-}; +- +-&lvds1 { +- ports { +- port@1 { +- lvds_connector: endpoint { +- }; +- }; +- }; +-}; +- +-&extal_clk { +- clock-frequency = <20000000>; +-}; +- +-&pfc { +- pinctrl-0 = <&scif_clk_pins>; +- pinctrl-names = "default"; +- +- du_pins: du { +- groups = "du_rgb666", "du_sync_1", "du_clk_out_0"; +- function = "du"; +- }; +- +- scif0_pins: scif0 { +- groups = "scif0_data"; +- function = "scif0"; +- }; +- +- scif_clk_pins: scif_clk { +- groups = "scif_clk"; +- function = "scif_clk"; +- }; +- +- ether_pins: ether { +- groups = "eth_link", "eth_mdio", "eth_rmii"; +- function = "eth"; +- }; +- +- phy1_pins: phy1 { +- groups = "intc_irq0"; +- function = "intc"; +- }; +- +- scifa1_pins: scifa1 { +- groups = "scifa1_data"; +- function = "scifa1"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <3300>; +- }; +- +- sdhi0_pins_uhs: sd0_uhs { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <1800>; +- }; +- +- sdhi2_pins: sd2 { +- groups = "sdhi2_data4", "sdhi2_ctrl"; +- function = "sdhi2"; +- power-source = <3300>; +- }; +- +- sdhi2_pins_uhs: sd2_uhs { +- groups = "sdhi2_data4", "sdhi2_ctrl"; +- function = "sdhi2"; +- power-source = <1800>; +- }; +- +- mmc1_pins: mmc1 { +- groups = "mmc1_data8", "mmc1_ctrl"; +- function = "mmc1"; +- }; +- +- qspi_pins: qspi { +- groups = "qspi_ctrl", "qspi_data4"; +- function = "qspi"; +- }; +- +- msiof1_pins: msiof1 { +- groups = "msiof1_clk", "msiof1_sync", "msiof1_rx", +- "msiof1_tx"; +- function = "msiof1"; +- }; +- +- i2c0_pins: i2c0 { +- groups = "i2c0"; +- function = "i2c0"; +- }; +- +- iic0_pins: iic0 { +- groups = "iic0"; +- function = "iic0"; +- }; +- +- i2c1_pins: i2c1 { +- groups = "i2c1"; +- function = "i2c1"; +- }; +- +- iic1_pins: iic1 { +- groups = "iic1"; +- function = "iic1"; +- }; +- +- i2c2_pins: i2c2 { +- groups = "i2c2"; +- function = "i2c2"; +- }; +- +- iic2_pins: iic2 { +- groups = "iic2"; +- function = "iic2"; +- }; +- +- i2c3_pins: i2c3 { +- groups = "i2c3"; +- function = "i2c3"; +- }; +- +- iic3_pins: iic3 { +- groups = "iic3"; +- function = "iic3"; +- }; +- +- pmic_irq_pins: pmicirq { +- groups = "intc_irq2"; +- function = "intc"; +- }; +- +- hsusb_pins: hsusb { +- groups = "usb0_ovc_vbus"; +- function = "usb0"; +- }; +- +- usb0_pins: usb0 { +- groups = "usb0"; +- function = "usb0"; +- }; +- +- usb1_pins: usb1 { +- groups = "usb1"; +- function = "usb1"; +- }; +- +- usb2_pins: usb2 { +- groups = "usb2"; +- function = "usb2"; +- }; +- +- vin0_pins: vin0 { +- groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; +- function = "vin0"; +- }; +- +- vin1_pins: vin1 { +- groups = "vin1_data8", "vin1_clk"; +- function = "vin1"; +- }; +- +- sound_pins: sound { +- groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; +- function = "ssi"; +- }; +- +- sound_clk_pins: sound_clk { +- groups = "audio_clk_a"; +- function = "audio_clk"; +- }; +- +- keyboard_pins: keyboard { +- pins = "GP_1_14", "GP_1_24", "GP_1_26", "GP_1_28"; +- bias-pull-up; +- }; +-}; +- +-ðer { +- pinctrl-0 = <ðer_pins>, <&phy1_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <&phy1>; +- renesas,ether-link-active-low; +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- interrupt-parent = <&irqc0>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- micrel,led-mode = <1>; +- reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&cmt0 { +- status = "okay"; +-}; +- +-&mmcif1 { +- pinctrl-0 = <&mmc1_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <&fixedregulator3v3>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&sata1 { +- status = "okay"; +-}; +- +-&qspi { +- pinctrl-0 = <&qspi_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- flash: flash@0 { +- compatible = "spansion,s25fl512s", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <30000000>; +- spi-tx-bus-width = <4>; +- spi-rx-bus-width = <4>; +- spi-cpha; +- spi-cpol; +- m25p,fast-read; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "loader"; +- reg = <0x00000000 0x00040000>; +- read-only; +- }; +- partition@40000 { +- label = "user"; +- reg = <0x00040000 0x00400000>; +- read-only; +- }; +- partition@440000 { +- label = "flash"; +- reg = <0x00440000 0x03bc0000>; +- }; +- }; +- }; +-}; +- +-&scif0 { +- pinctrl-0 = <&scif0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scifa1 { +- pinctrl-0 = <&scifa1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scif_clk { +- clock-frequency = <14745600>; +-}; +- +-&msiof1 { +- pinctrl-0 = <&msiof1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- pmic: pmic@0 { +- compatible = "renesas,r2a11302ft"; +- reg = <0>; +- spi-max-frequency = <6000000>; +- spi-cpol; +- spi-cpha; +- }; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-1 = <&sdhi0_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <&vcc_sdhi0>; +- vqmmc-supply = <&vccq_sdhi0>; +- cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- status = "okay"; +-}; +- +-&sdhi2 { +- pinctrl-0 = <&sdhi2_pins>; +- pinctrl-1 = <&sdhi2_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <&vcc_sdhi2>; +- vqmmc-supply = <&vccq_sdhi2>; +- cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; +- sd-uhs-sdr50; +- status = "okay"; +-}; +- +-&cpu0 { +- cpu0-supply = <&vdd_dvfs>; +-}; +- +-&i2c0 { +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "i2c-exio0"; +-}; +- +-&iic0 { +- pinctrl-0 = <&iic0_pins>; +- pinctrl-names = "i2c-exio0"; +-}; +- +-&i2c1 { +- pinctrl-0 = <&i2c1_pins>; +- pinctrl-names = "i2c-exio1"; +-}; +- +-&iic1 { +- pinctrl-0 = <&iic1_pins>; +- pinctrl-names = "i2c-exio1"; +-}; +- +-&i2c2 { +- pinctrl-0 = <&i2c2_pins>; +- pinctrl-names = "i2c-hdmi"; +- +- clock-frequency = <100000>; +-}; +- +-&iic2 { +- pinctrl-0 = <&iic2_pins>; +- pinctrl-names = "i2c-hdmi"; +- +- clock-frequency = <100000>; +-}; +- +-&i2c3 { +- pinctrl-0 = <&i2c3_pins>; +- pinctrl-names = "i2c-pwr"; +-}; +- +-&iic3 { +- pinctrl-0 = <&iic3_pins>; +- pinctrl-names = "i2c-pwr"; +-}; +- +-&pci0 { +- status = "okay"; +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +-}; +- +-&pci1 { +- status = "okay"; +- pinctrl-0 = <&usb1_pins>; +- pinctrl-names = "default"; +-}; +- +-&xhci { +- status = "okay"; +- pinctrl-0 = <&usb2_pins>; +- pinctrl-names = "default"; +-}; +- +-&pci2 { +- status = "okay"; +- pinctrl-0 = <&usb2_pins>; +- pinctrl-names = "default"; +-}; +- +-&hsusb { +- status = "okay"; +- pinctrl-0 = <&hsusb_pins>; +- pinctrl-names = "default"; +- renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-/* HDMI video input */ +-&vin0 { +- pinctrl-0 = <&vin0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- port { +- vin0ep2: endpoint { +- remote-endpoint = <&adv7612_out>; +- bus-width = <24>; +- hsync-active = <0>; +- vsync-active = <0>; +- pclk-sample = <1>; +- data-active = <1>; +- }; +- }; +-}; +- +-/* composite video input */ +-&vin1 { +- pinctrl-0 = <&vin1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- port { +- vin1ep0: endpoint { +- remote-endpoint = <&adv7180>; +- bus-width = <8>; +- }; +- }; +-}; +- +-&rcar_sound { +- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; +- pinctrl-names = "default"; +- +- /* Single DAI */ +- #sound-dai-cells = <0>; +- +- status = "okay"; +- +- rcar_sound,dai { +- dai0 { +- playback = <&ssi0>, <&src2>, <&dvc0>; +- capture = <&ssi1>, <&src3>, <&dvc1>; +- }; +- }; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&ssi1 { +- shared-pin; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7790-stout.dts b/scripts/dtc/include-prefixes/arm/r8a7790-stout.dts +deleted file mode 100644 +index d51f23572d7f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7790-stout.dts ++++ /dev/null +@@ -1,380 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Stout board +- * +- * Copyright (C) 2018 Marek Vasut +- */ +- +-/dts-v1/; +-#include "r8a7790.dtsi" +-#include +-#include +- +-/ { +- model = "Stout"; +- compatible = "renesas,stout", "renesas,r8a7790"; +- +- aliases { +- serial0 = &scifa0; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x40000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led1 { +- gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; +- }; +- led2 { +- gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; +- }; +- led3 { +- gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; +- }; +- led5 { +- gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- fixedregulator3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcc_sdhi0: regulator-vcc-sdhi0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI0 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_out: endpoint { +- remote-endpoint = <&adv7511_out>; +- }; +- }; +- }; +- +- osc1_clk: osc1-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <148500000>; +- }; +- +- osc4_clk: osc4-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <12000000>; +- }; +-}; +- +-&du { +- pinctrl-0 = <&du_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, +- <&osc1_clk>; +- clock-names = "du.0", "du.1", "du.2", "dclkin.0"; +- +- ports { +- port@0 { +- endpoint { +- remote-endpoint = <&adv7511_in>; +- }; +- }; +- }; +-}; +- +-&lvds0 { +- ports { +- port@1 { +- lvds_connector0: endpoint { +- }; +- }; +- }; +-}; +- +-&lvds1 { +- ports { +- port@1 { +- lvds_connector1: endpoint { +- }; +- }; +- }; +-}; +- +-&extal_clk { +- clock-frequency = <20000000>; +-}; +- +-&pfc { +- +- pinctrl-0 = <&scif_clk_pins>; +- pinctrl-names = "default"; +- +- du_pins: du { +- groups = "du_rgb888", "du_sync_1", "du_clk_out_0"; +- function = "du"; +- }; +- +- scifa0_pins: scifa0 { +- groups = "scifa0_data_b"; +- function = "scifa0"; +- }; +- +- scif_clk_pins: scif_clk { +- groups = "scif_clk"; +- function = "scif_clk"; +- }; +- +- ether_pins: ether { +- groups = "eth_link", "eth_mdio", "eth_rmii"; +- function = "eth"; +- }; +- +- phy1_pins: phy1 { +- groups = "intc_irq1"; +- function = "intc"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <3300>; +- }; +- +- qspi_pins: qspi { +- groups = "qspi_ctrl", "qspi_data4"; +- function = "qspi"; +- }; +- +- iic2_pins: iic2 { +- groups = "iic2_b"; +- function = "iic2"; +- }; +- +- iic3_pins: iic3 { +- groups = "iic3"; +- function = "iic3"; +- }; +- +- pmic_irq_pins: pmicirq { +- groups = "intc_irq2"; +- function = "intc"; +- }; +- +- usb0_pins: usb0 { +- groups = "usb0"; +- function = "usb0"; +- }; +-}; +- +-ðer { +- pinctrl-0 = <ðer_pins>, <&phy1_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <&phy1>; +- renesas,ether-link-active-low; +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- interrupt-parent = <&irqc0>; +- interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +- micrel,led-mode = <1>; +- reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&cmt0 { +- status = "okay"; +-}; +- +-&qspi { +- pinctrl-0 = <&qspi_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- flash: flash@0 { +- compatible = "spansion,s25fl512s", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <30000000>; +- spi-tx-bus-width = <4>; +- spi-rx-bus-width = <4>; +- spi-cpha; +- spi-cpol; +- m25p,fast-read; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "loader"; +- reg = <0x00000000 0x00080000>; +- read-only; +- }; +- partition@80000 { +- label = "uboot"; +- reg = <0x00080000 0x00040000>; +- read-only; +- }; +- partition@c0000 { +- label = "uboot-env"; +- reg = <0x000c0000 0x00040000>; +- read-only; +- }; +- partition@100000 { +- label = "flash"; +- reg = <0x00100000 0x03f00000>; +- }; +- }; +- }; +-}; +- +-&scifa0 { +- pinctrl-0 = <&scifa0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scif_clk { +- clock-frequency = <14745600>; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <&vcc_sdhi0>; +- cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&cpu0 { +- cpu0-supply = <&vdd_dvfs>; +-}; +- +-&iic2 { +- status = "okay"; +- pinctrl-0 = <&iic2_pins>; +- pinctrl-names = "default"; +- +- clock-frequency = <100000>; +- +- hdmi@39 { +- compatible = "adi,adv7511w"; +- reg = <0x39>; +- interrupt-parent = <&gpio1>; +- interrupts = <15 IRQ_TYPE_LEVEL_LOW>; +- clocks = <&osc4_clk>; +- clock-names = "cec"; +- +- adi,input-depth = <8>; +- adi,input-colorspace = "rgb"; +- adi,input-clock = "1x"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7511_in: endpoint { +- remote-endpoint = <&du_out_rgb>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- adv7511_out: endpoint { +- remote-endpoint = <&hdmi_con_out>; +- }; +- }; +- }; +- }; +-}; +- +-&iic3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&iic3_pins>, <&pmic_irq_pins>; +- status = "okay"; +- +- pmic@58 { +- compatible = "dlg,da9063"; +- reg = <0x58>; +- interrupt-parent = <&irqc0>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- +- onkey { +- compatible = "dlg,da9063-onkey"; +- }; +- +- rtc { +- compatible = "dlg,da9063-rtc"; +- }; +- +- wdt { +- compatible = "dlg,da9063-watchdog"; +- }; +- }; +- +- vdd_dvfs: regulator@68 { +- compatible = "dlg,da9210"; +- reg = <0x68>; +- interrupt-parent = <&irqc0>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd: regulator@70 { +- compatible = "dlg,da9210"; +- reg = <0x70>; +- interrupt-parent = <&irqc0>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&pci0 { +- status = "okay"; +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7790.dtsi b/scripts/dtc/include-prefixes/arm/r8a7790.dtsi +deleted file mode 100644 +index ed6dd4fcc503..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7790.dtsi ++++ /dev/null +@@ -1,1883 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Car H2 (R8A77900) SoC +- * +- * Copyright (C) 2015 Renesas Electronics Corporation +- * Copyright (C) 2013-2014 Renesas Solutions Corp. +- * Copyright (C) 2014 Cogent Embedded Inc. +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r8a7790"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &iic0; +- i2c5 = &iic1; +- i2c6 = &iic2; +- i2c7 = &iic3; +- spi0 = &qspi; +- spi1 = &msiof0; +- spi2 = &msiof1; +- spi3 = &msiof2; +- spi4 = &msiof3; +- vin0 = &vin0; +- vin1 = &vin1; +- vin2 = &vin2; +- vin3 = &vin3; +- }; +- +- /* +- * The external audio clocks are configured as 0 Hz fixed frequency +- * clocks by default. +- * Boards that provide audio clocks should override them. +- */ +- audio_clk_a: audio_clk_a { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- audio_clk_b: audio_clk_b { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- audio_clk_c: audio_clk_c { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* External CAN clock */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0>; +- clock-frequency = <1300000000>; +- clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; +- power-domains = <&sysc R8A7790_PD_CA15_CPU0>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA15>; +- capacity-dmips-mhz = <1024>; +- voltage-tolerance = <1>; /* 1% */ +- clock-latency = <300000>; /* 300 us */ +- +- /* kHz - uV - OPPs unknown yet */ +- operating-points = <1400000 1000000>, +- <1225000 1000000>, +- <1050000 1000000>, +- < 875000 1000000>, +- < 700000 1000000>, +- < 350000 1000000>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <1>; +- clock-frequency = <1300000000>; +- clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; +- power-domains = <&sysc R8A7790_PD_CA15_CPU1>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA15>; +- capacity-dmips-mhz = <1024>; +- voltage-tolerance = <1>; /* 1% */ +- clock-latency = <300000>; /* 300 us */ +- +- /* kHz - uV - OPPs unknown yet */ +- operating-points = <1400000 1000000>, +- <1225000 1000000>, +- <1050000 1000000>, +- < 875000 1000000>, +- < 700000 1000000>, +- < 350000 1000000>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <2>; +- clock-frequency = <1300000000>; +- clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; +- power-domains = <&sysc R8A7790_PD_CA15_CPU2>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA15>; +- capacity-dmips-mhz = <1024>; +- voltage-tolerance = <1>; /* 1% */ +- clock-latency = <300000>; /* 300 us */ +- +- /* kHz - uV - OPPs unknown yet */ +- operating-points = <1400000 1000000>, +- <1225000 1000000>, +- <1050000 1000000>, +- < 875000 1000000>, +- < 700000 1000000>, +- < 350000 1000000>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <3>; +- clock-frequency = <1300000000>; +- clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; +- power-domains = <&sysc R8A7790_PD_CA15_CPU3>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA15>; +- capacity-dmips-mhz = <1024>; +- voltage-tolerance = <1>; /* 1% */ +- clock-latency = <300000>; /* 300 us */ +- +- /* kHz - uV - OPPs unknown yet */ +- operating-points = <1400000 1000000>, +- <1225000 1000000>, +- <1050000 1000000>, +- < 875000 1000000>, +- < 700000 1000000>, +- < 350000 1000000>; +- }; +- +- cpu4: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x100>; +- clock-frequency = <780000000>; +- clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; +- power-domains = <&sysc R8A7790_PD_CA7_CPU0>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA7>; +- capacity-dmips-mhz = <539>; +- }; +- +- cpu5: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x101>; +- clock-frequency = <780000000>; +- clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; +- power-domains = <&sysc R8A7790_PD_CA7_CPU1>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA7>; +- capacity-dmips-mhz = <539>; +- }; +- +- cpu6: cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x102>; +- clock-frequency = <780000000>; +- clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; +- power-domains = <&sysc R8A7790_PD_CA7_CPU2>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA7>; +- capacity-dmips-mhz = <539>; +- }; +- +- cpu7: cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x103>; +- clock-frequency = <780000000>; +- clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; +- power-domains = <&sysc R8A7790_PD_CA7_CPU3>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA7>; +- capacity-dmips-mhz = <539>; +- }; +- +- L2_CA15: cache-controller-0 { +- compatible = "cache"; +- power-domains = <&sysc R8A7790_PD_CA15_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- +- L2_CA7: cache-controller-1 { +- compatible = "cache"; +- power-domains = <&sysc R8A7790_PD_CA7_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- }; +- +- /* External root clock */ +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- /* External PCIe clock - can be overridden by the board */ +- pcie_bus_clk: pcie_bus { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- pmu-0 { +- compatible = "arm,cortex-a15-pmu"; +- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- pmu-1 { +- compatible = "arm,cortex-a7-pmu"; +- interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; +- }; +- +- /* External SCIF clock */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a7790-wdt", +- "renesas,rcar-gen2-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a7790", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a7790", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 30>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a7790", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 30>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a7790", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a7790", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a7790", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a7790"; +- reg = <0 0xe6060000 0 0x250>; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a7790-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>, <&usb_extal_clk>; +- clock-names = "extal", "usb_extal"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- apmu@e6151000 { +- compatible = "renesas,r8a7790-apmu", "renesas,apmu"; +- reg = <0 0xe6151000 0 0x188>; +- cpus = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; +- }; +- +- apmu@e6152000 { +- compatible = "renesas,r8a7790-apmu", "renesas,apmu"; +- reg = <0 0xe6152000 0 0x188>; +- cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a7790-rst"; +- reg = <0 0xe6160000 0 0x0100>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a7790-sysc"; +- reg = <0 0xe6180000 0 0x0200>; +- #power-domain-cells = <1>; +- }; +- +- irqc0: interrupt-controller@e61c0000 { +- compatible = "renesas,irqc-r8a7790", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- thermal: thermal@e61f0000 { +- compatible = "renesas,thermal-r8a7790", +- "renesas,rcar-gen2-thermal", +- "renesas,rcar-thermal"; +- reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 522>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 522>; +- #thermal-sensor-cells = <0>; +- }; +- +- ipmmu_sy0: iommu@e6280000 { +- compatible = "renesas,ipmmu-r8a7790", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6280000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_sy1: iommu@e6290000 { +- compatible = "renesas,ipmmu-r8a7790", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6290000 0 0x1000>; +- interrupts = ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_ds: iommu@e6740000 { +- compatible = "renesas,ipmmu-r8a7790", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6740000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_mp: iommu@ec680000 { +- compatible = "renesas,ipmmu-r8a7790", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xec680000 0 0x1000>; +- interrupts = ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_mx: iommu@fe951000 { +- compatible = "renesas,ipmmu-r8a7790", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xfe951000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_rt: iommu@ffc80000 { +- compatible = "renesas,ipmmu-r8a7790", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xffc80000 0 0x1000>; +- interrupts = ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- icram0: sram@e63a0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63a0000 0 0x12000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63a0000 0x12000>; +- }; +- +- icram1: sram@e63c0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63c0000 0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63c0000 0x1000>; +- +- smp-sram@0 { +- compatible = "renesas,smp-sram"; +- reg = <0 0x100>; +- }; +- }; +- +- i2c0: i2c@e6508000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7790", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6518000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7790", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6518000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6530000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7790", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6530000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e6540000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7790", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6540000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- iic0: i2c@e6500000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7790", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe6500000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 318>; +- dmas = <&dmac0 0x61>, <&dmac0 0x62>, +- <&dmac1 0x61>, <&dmac1 0x62>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 318>; +- status = "disabled"; +- }; +- +- iic1: i2c@e6510000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7790", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe6510000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 323>; +- dmas = <&dmac0 0x65>, <&dmac0 0x66>, +- <&dmac1 0x65>, <&dmac1 0x66>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 323>; +- status = "disabled"; +- }; +- +- iic2: i2c@e6520000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7790", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe6520000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 300>; +- dmas = <&dmac0 0x69>, <&dmac0 0x6a>, +- <&dmac1 0x69>, <&dmac1 0x6a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 300>; +- status = "disabled"; +- }; +- +- iic3: i2c@e60b0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7790", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe60b0000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 926>; +- dmas = <&dmac0 0x77>, <&dmac0 0x78>, +- <&dmac1 0x77>, <&dmac1 0x78>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 926>; +- status = "disabled"; +- }; +- +- hsusb: usb@e6590000 { +- compatible = "renesas,usbhs-r8a7790", +- "renesas,rcar-gen2-usbhs"; +- reg = <0 0xe6590000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 704>; +- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, +- <&usb_dmac1 0>, <&usb_dmac1 1>; +- dma-names = "ch0", "ch1", "ch2", "ch3"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 704>; +- renesas,buswait = <4>; +- phys = <&usb0 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usbphy: usb-phy@e6590100 { +- compatible = "renesas,usb-phy-r8a7790", +- "renesas,rcar-gen2-usb-phy"; +- reg = <0 0xe6590100 0 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cpg CPG_MOD 704>; +- clock-names = "usbhs"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 704>; +- status = "disabled"; +- +- usb0: usb-channel@0 { +- reg = <0>; +- #phy-cells = <1>; +- }; +- usb2: usb-channel@2 { +- reg = <2>; +- #phy-cells = <1>; +- }; +- }; +- +- usb_dmac0: dma-controller@e65a0000 { +- compatible = "renesas,r8a7790-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65a0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 330>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 330>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac1: dma-controller@e65b0000 { +- compatible = "renesas,r8a7790-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65b0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 331>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 331>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a7790", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- dmac1: dma-controller@e6720000 { +- compatible = "renesas,dmac-r8a7790", +- "renesas,rcar-dmac"; +- reg = <0 0xe6720000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a7790", +- "renesas,etheravb-rcar-gen2"; +- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- qspi: spi@e6b10000 { +- compatible = "renesas,qspi-r8a7790", "renesas,qspi"; +- reg = <0 0xe6b10000 0 0x2c>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 917>; +- dmas = <&dmac0 0x17>, <&dmac0 0x18>, +- <&dmac1 0x17>, <&dmac1 0x18>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 917>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- scifa0: serial@e6c40000 { +- compatible = "renesas,scifa-r8a7790", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c40000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>; +- clock-names = "fck"; +- dmas = <&dmac0 0x21>, <&dmac0 0x22>, +- <&dmac1 0x21>, <&dmac1 0x22>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scifa1: serial@e6c50000 { +- compatible = "renesas,scifa-r8a7790", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c50000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>; +- clock-names = "fck"; +- dmas = <&dmac0 0x25>, <&dmac0 0x26>, +- <&dmac1 0x25>, <&dmac1 0x26>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- scifa2: serial@e6c60000 { +- compatible = "renesas,scifa-r8a7790", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c60000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 202>; +- clock-names = "fck"; +- dmas = <&dmac0 0x27>, <&dmac0 0x28>, +- <&dmac1 0x27>, <&dmac1 0x28>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 202>; +- status = "disabled"; +- }; +- +- scifb0: serial@e6c20000 { +- compatible = "renesas,scifb-r8a7790", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6c20000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>; +- clock-names = "fck"; +- dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, +- <&dmac1 0x3d>, <&dmac1 0x3e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scifb1: serial@e6c30000 { +- compatible = "renesas,scifb-r8a7790", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6c30000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>; +- clock-names = "fck"; +- dmas = <&dmac0 0x19>, <&dmac0 0x1a>, +- <&dmac1 0x19>, <&dmac1 0x1a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scifb2: serial@e6ce0000 { +- compatible = "renesas,scifb-r8a7790", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6ce0000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 216>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, +- <&dmac1 0x1d>, <&dmac1 0x1e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 216>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a7790", +- "renesas,rcar-gen2-scif", +- "renesas,scif"; +- reg = <0 0xe6e60000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 721>, +- <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x29>, <&dmac0 0x2a>, +- <&dmac1 0x29>, <&dmac1 0x2a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 721>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a7790", +- "renesas,rcar-gen2-scif", +- "renesas,scif"; +- reg = <0 0xe6e68000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 720>, +- <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, +- <&dmac1 0x2d>, <&dmac1 0x2e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 720>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e56000 { +- compatible = "renesas,scif-r8a7790", +- "renesas,rcar-gen2-scif", +- "renesas,scif"; +- reg = <0 0xe6e56000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 310>, +- <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, +- <&dmac1 0x2b>, <&dmac1 0x2c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 310>; +- status = "disabled"; +- }; +- +- hscif0: serial@e62c0000 { +- compatible = "renesas,hscif-r8a7790", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c0000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 717>, +- <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x39>, <&dmac0 0x3a>, +- <&dmac1 0x39>, <&dmac1 0x3a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 717>; +- status = "disabled"; +- }; +- +- hscif1: serial@e62c8000 { +- compatible = "renesas,hscif-r8a7790", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c8000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>, +- <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, +- <&dmac1 0x4d>, <&dmac1 0x4e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e20000 { +- compatible = "renesas,msiof-r8a7790", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e20000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 0>; +- dmas = <&dmac0 0x51>, <&dmac0 0x52>, +- <&dmac1 0x51>, <&dmac1 0x52>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6e10000 { +- compatible = "renesas,msiof-r8a7790", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e10000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 208>; +- dmas = <&dmac0 0x55>, <&dmac0 0x56>, +- <&dmac1 0x55>, <&dmac1 0x56>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 208>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6e00000 { +- compatible = "renesas,msiof-r8a7790", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e00000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 205>; +- dmas = <&dmac0 0x41>, <&dmac0 0x42>, +- <&dmac1 0x41>, <&dmac1 0x42>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 205>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof3: spi@e6c90000 { +- compatible = "renesas,msiof-r8a7790", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6c90000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 215>; +- dmas = <&dmac0 0x45>, <&dmac0 0x46>, +- <&dmac1 0x45>, <&dmac1 0x46>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 215>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- can0: can@e6e80000 { +- compatible = "renesas,can-r8a7790", +- "renesas,rcar-gen2-can"; +- reg = <0 0xe6e80000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>, +- <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- status = "disabled"; +- }; +- +- can1: can@e6e88000 { +- compatible = "renesas,can-r8a7790", +- "renesas,rcar-gen2-can"; +- reg = <0 0xe6e88000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>, +- <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- status = "disabled"; +- }; +- +- vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a7790", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef0000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 811>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 811>; +- status = "disabled"; +- }; +- +- vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a7790", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef1000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 810>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 810>; +- status = "disabled"; +- }; +- +- vin2: video@e6ef2000 { +- compatible = "renesas,vin-r8a7790", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef2000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 809>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 809>; +- status = "disabled"; +- }; +- +- vin3: video@e6ef3000 { +- compatible = "renesas,vin-r8a7790", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef3000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 808>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 808>; +- status = "disabled"; +- }; +- +- rcar_sound: sound@ec500000 { +- /* +- * #sound-dai-cells is required +- * +- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; +- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; +- */ +- compatible = "renesas,rcar_sound-r8a7790", +- "renesas,rcar_sound-gen2"; +- reg = <0 0xec500000 0 0x1000>, /* SCU */ +- <0 0xec5a0000 0 0x100>, /* ADG */ +- <0 0xec540000 0 0x1000>, /* SSIU */ +- <0 0xec541000 0 0x280>, /* SSI */ +- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ +- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; +- +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, +- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, +- <&cpg CPG_CORE R8A7790_CLK_M2>; +- clock-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0", +- "src.9", "src.8", "src.7", "src.6", +- "src.5", "src.4", "src.3", "src.2", +- "src.1", "src.0", +- "ctu.0", "ctu.1", +- "mix.0", "mix.1", +- "dvc.0", "dvc.1", +- "clk_a", "clk_b", "clk_c", "clk_i"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 1005>, +- <&cpg 1006>, <&cpg 1007>, +- <&cpg 1008>, <&cpg 1009>, +- <&cpg 1010>, <&cpg 1011>, +- <&cpg 1012>, <&cpg 1013>, +- <&cpg 1014>, <&cpg 1015>; +- reset-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0"; +- +- status = "disabled"; +- +- rcar_sound,dvc { +- dvc0: dvc-0 { +- dmas = <&audma1 0xbc>; +- dma-names = "tx"; +- }; +- dvc1: dvc-1 { +- dmas = <&audma1 0xbe>; +- dma-names = "tx"; +- }; +- }; +- +- rcar_sound,mix { +- mix0: mix-0 { }; +- mix1: mix-1 { }; +- }; +- +- rcar_sound,ctu { +- ctu00: ctu-0 { }; +- ctu01: ctu-1 { }; +- ctu02: ctu-2 { }; +- ctu03: ctu-3 { }; +- ctu10: ctu-4 { }; +- ctu11: ctu-5 { }; +- ctu12: ctu-6 { }; +- ctu13: ctu-7 { }; +- }; +- +- rcar_sound,src { +- src0: src-0 { +- interrupts = ; +- dmas = <&audma0 0x85>, <&audma1 0x9a>; +- dma-names = "rx", "tx"; +- }; +- src1: src-1 { +- interrupts = ; +- dmas = <&audma0 0x87>, <&audma1 0x9c>; +- dma-names = "rx", "tx"; +- }; +- src2: src-2 { +- interrupts = ; +- dmas = <&audma0 0x89>, <&audma1 0x9e>; +- dma-names = "rx", "tx"; +- }; +- src3: src-3 { +- interrupts = ; +- dmas = <&audma0 0x8b>, <&audma1 0xa0>; +- dma-names = "rx", "tx"; +- }; +- src4: src-4 { +- interrupts = ; +- dmas = <&audma0 0x8d>, <&audma1 0xb0>; +- dma-names = "rx", "tx"; +- }; +- src5: src-5 { +- interrupts = ; +- dmas = <&audma0 0x8f>, <&audma1 0xb2>; +- dma-names = "rx", "tx"; +- }; +- src6: src-6 { +- interrupts = ; +- dmas = <&audma0 0x91>, <&audma1 0xb4>; +- dma-names = "rx", "tx"; +- }; +- src7: src-7 { +- interrupts = ; +- dmas = <&audma0 0x93>, <&audma1 0xb6>; +- dma-names = "rx", "tx"; +- }; +- src8: src-8 { +- interrupts = ; +- dmas = <&audma0 0x95>, <&audma1 0xb8>; +- dma-names = "rx", "tx"; +- }; +- src9: src-9 { +- interrupts = ; +- dmas = <&audma0 0x97>, <&audma1 0xba>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssi { +- ssi0: ssi-0 { +- interrupts = ; +- dmas = <&audma0 0x01>, <&audma1 0x02>, +- <&audma0 0x15>, <&audma1 0x16>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi1: ssi-1 { +- interrupts = ; +- dmas = <&audma0 0x03>, <&audma1 0x04>, +- <&audma0 0x49>, <&audma1 0x4a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi2: ssi-2 { +- interrupts = ; +- dmas = <&audma0 0x05>, <&audma1 0x06>, +- <&audma0 0x63>, <&audma1 0x64>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi3: ssi-3 { +- interrupts = ; +- dmas = <&audma0 0x07>, <&audma1 0x08>, +- <&audma0 0x6f>, <&audma1 0x70>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi4: ssi-4 { +- interrupts = ; +- dmas = <&audma0 0x09>, <&audma1 0x0a>, +- <&audma0 0x71>, <&audma1 0x72>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi5: ssi-5 { +- interrupts = ; +- dmas = <&audma0 0x0b>, <&audma1 0x0c>, +- <&audma0 0x73>, <&audma1 0x74>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi6: ssi-6 { +- interrupts = ; +- dmas = <&audma0 0x0d>, <&audma1 0x0e>, +- <&audma0 0x75>, <&audma1 0x76>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi7: ssi-7 { +- interrupts = ; +- dmas = <&audma0 0x0f>, <&audma1 0x10>, +- <&audma0 0x79>, <&audma1 0x7a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi8: ssi-8 { +- interrupts = ; +- dmas = <&audma0 0x11>, <&audma1 0x12>, +- <&audma0 0x7b>, <&audma1 0x7c>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi9: ssi-9 { +- interrupts = ; +- dmas = <&audma0 0x13>, <&audma1 0x14>, +- <&audma0 0x7d>, <&audma1 0x7e>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- }; +- }; +- +- audma0: dma-controller@ec700000 { +- compatible = "renesas,dmac-r8a7790", +- "renesas,rcar-dmac"; +- reg = <0 0xec700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12"; +- clocks = <&cpg CPG_MOD 502>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 502>; +- #dma-cells = <1>; +- dma-channels = <13>; +- }; +- +- audma1: dma-controller@ec720000 { +- compatible = "renesas,dmac-r8a7790", +- "renesas,rcar-dmac"; +- reg = <0 0xec720000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12"; +- clocks = <&cpg CPG_MOD 501>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 501>; +- #dma-cells = <1>; +- dma-channels = <13>; +- }; +- +- xhci: usb@ee000000 { +- compatible = "renesas,xhci-r8a7790", +- "renesas,rcar-gen2-xhci"; +- reg = <0 0xee000000 0 0xc00>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- phys = <&usb2 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- pci0: pci@ee090000 { +- compatible = "renesas,pci-r8a7790", +- "renesas,pci-rcar-gen2"; +- device_type = "pci"; +- reg = <0 0xee090000 0 0xc00>, +- <0 0xee080000 0 0x1100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- status = "disabled"; +- +- bus-range = <0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; +- interrupt-map-mask = <0xf800 0 0 0x7>; +- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, +- <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, +- <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; +- +- usb@1,0 { +- reg = <0x800 0 0 0 0>; +- phys = <&usb0 0>; +- phy-names = "usb"; +- }; +- +- usb@2,0 { +- reg = <0x1000 0 0 0 0>; +- phys = <&usb0 0>; +- phy-names = "usb"; +- }; +- }; +- +- pci1: pci@ee0b0000 { +- compatible = "renesas,pci-r8a7790", +- "renesas,pci-rcar-gen2"; +- device_type = "pci"; +- reg = <0 0xee0b0000 0 0xc00>, +- <0 0xee0a0000 0 0x1100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- status = "disabled"; +- +- bus-range = <1 1>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; +- interrupt-map-mask = <0xf800 0 0 0x7>; +- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, +- <0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, +- <0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- pci2: pci@ee0d0000 { +- compatible = "renesas,pci-r8a7790", +- "renesas,pci-rcar-gen2"; +- device_type = "pci"; +- clocks = <&cpg CPG_MOD 703>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- reg = <0 0xee0d0000 0 0xc00>, +- <0 0xee0c0000 0 0x1100>; +- interrupts = ; +- status = "disabled"; +- +- bus-range = <2 2>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; +- interrupt-map-mask = <0xf800 0 0 0x7>; +- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, +- <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, +- <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; +- +- usb@1,0 { +- reg = <0x20800 0 0 0 0>; +- phys = <&usb2 0>; +- phy-names = "usb"; +- }; +- +- usb@2,0 { +- reg = <0x21000 0 0 0 0>; +- phys = <&usb2 0>; +- phy-names = "usb"; +- }; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a7790", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee100000 0 0x328>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- dmas = <&dmac0 0xcd>, <&dmac0 0xce>, +- <&dmac1 0xcd>, <&dmac1 0xce>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <195000000>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ee120000 { +- compatible = "renesas,sdhi-r8a7790", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee120000 0 0x328>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 313>; +- dmas = <&dmac0 0xc9>, <&dmac0 0xca>, +- <&dmac1 0xc9>, <&dmac1 0xca>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <195000000>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 313>; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a7790", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee140000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 312>; +- dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, +- <&dmac1 0xc1>, <&dmac1 0xc2>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <97500000>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 312>; +- status = "disabled"; +- }; +- +- sdhi3: mmc@ee160000 { +- compatible = "renesas,sdhi-r8a7790", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee160000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 311>; +- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, +- <&dmac1 0xd3>, <&dmac1 0xd4>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <97500000>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 311>; +- status = "disabled"; +- }; +- +- mmcif0: mmc@ee200000 { +- compatible = "renesas,mmcif-r8a7790", +- "renesas,sh-mmcif"; +- reg = <0 0xee200000 0 0x80>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 315>; +- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, +- <&dmac1 0xd1>, <&dmac1 0xd2>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 315>; +- reg-io-width = <4>; +- status = "disabled"; +- max-frequency = <97500000>; +- }; +- +- mmcif1: mmc@ee220000 { +- compatible = "renesas,mmcif-r8a7790", +- "renesas,sh-mmcif"; +- reg = <0 0xee220000 0 0x80>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 305>; +- dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, +- <&dmac1 0xe1>, <&dmac1 0xe2>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 305>; +- reg-io-width = <4>; +- status = "disabled"; +- max-frequency = <97500000>; +- }; +- +- sata0: sata@ee300000 { +- compatible = "renesas,sata-r8a7790", +- "renesas,rcar-gen2-sata"; +- reg = <0 0xee300000 0 0x200000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 815>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 815>; +- status = "disabled"; +- }; +- +- sata1: sata@ee500000 { +- compatible = "renesas,sata-r8a7790", +- "renesas,rcar-gen2-sata"; +- reg = <0 0xee500000 0 0x200000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 814>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 814>; +- status = "disabled"; +- }; +- +- ether: ethernet@ee700000 { +- compatible = "renesas,ether-r8a7790", +- "renesas,rcar-gen2-ether"; +- reg = <0 0xee700000 0 0x400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 813>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 813>; +- phy-mode = "rmii"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1001000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, +- <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- pciec: pcie@fe000000 { +- compatible = "renesas,pcie-r8a7790", +- "renesas,pcie-rcar-gen2"; +- reg = <0 0xfe000000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, +- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, +- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, +- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, +- <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 319>; +- status = "disabled"; +- }; +- +- vsp@fe920000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe920000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 130>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 130>; +- }; +- +- vsp@fe928000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe928000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 131>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 131>; +- }; +- +- vsp@fe930000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe930000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 128>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 128>; +- }; +- +- vsp@fe938000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe938000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 127>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 127>; +- }; +- +- fdp1@fe940000 { +- compatible = "renesas,fdp1"; +- reg = <0 0xfe940000 0 0x2400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 119>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 119>; +- }; +- +- fdp1@fe944000 { +- compatible = "renesas,fdp1"; +- reg = <0 0xfe944000 0 0x2400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 118>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 118>; +- }; +- +- fdp1@fe948000 { +- compatible = "renesas,fdp1"; +- reg = <0 0xfe948000 0 0x2400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 117>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 117>; +- }; +- +- jpu: jpeg-codec@fe980000 { +- compatible = "renesas,jpu-r8a7790", +- "renesas,rcar-gen2-jpu"; +- reg = <0 0xfe980000 0 0x10300>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 106>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 106>; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a7790"; +- reg = <0 0xfeb00000 0 0x70000>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>; +- clock-names = "du.0", "du.1", "du.2"; +- resets = <&cpg 724>; +- reset-names = "du.0"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb: endpoint { +- }; +- }; +- port@1 { +- reg = <1>; +- du_out_lvds0: endpoint { +- remote-endpoint = <&lvds0_in>; +- }; +- }; +- port@2 { +- reg = <2>; +- du_out_lvds1: endpoint { +- remote-endpoint = <&lvds1_in>; +- }; +- }; +- }; +- }; +- +- lvds0: lvds@feb90000 { +- compatible = "renesas,r8a7790-lvds"; +- reg = <0 0xfeb90000 0 0x1c>; +- clocks = <&cpg CPG_MOD 726>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 726>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds0_in: endpoint { +- remote-endpoint = <&du_out_lvds0>; +- }; +- }; +- port@1 { +- reg = <1>; +- lvds0_out: endpoint { +- }; +- }; +- }; +- }; +- +- lvds1: lvds@feb94000 { +- compatible = "renesas,r8a7790-lvds"; +- reg = <0 0xfeb94000 0 0x1c>; +- clocks = <&cpg CPG_MOD 725>; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 725>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds1_in: endpoint { +- remote-endpoint = <&du_out_lvds1>; +- }; +- }; +- port@1 { +- reg = <1>; +- lvds1_out: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@ff000044 { +- compatible = "renesas,prr"; +- reg = <0 0xff000044 0 4>; +- }; +- +- cmt0: timer@ffca0000 { +- compatible = "renesas,r8a7790-cmt0", +- "renesas,rcar-gen2-cmt0"; +- reg = <0 0xffca0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a7790-cmt1", +- "renesas,rcar-gen2-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 329>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; +- resets = <&cpg 329>; +- +- status = "disabled"; +- }; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&thermal>; +- +- trips { +- cpu-crit { +- temperature = <95000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- cooling-maps { +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; +- }; +- +- /* External USB clock - can be overridden by the board */ +- usb_extal_clk: usb_extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <48000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7791-koelsch.dts b/scripts/dtc/include-prefixes/arm/r8a7791-koelsch.dts +deleted file mode 100644 +index 2a8b6fd9095c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7791-koelsch.dts ++++ /dev/null +@@ -1,910 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Koelsch board +- * +- * Copyright (C) 2013 Renesas Electronics Corporation +- * Copyright (C) 2013-2014 Renesas Solutions Corp. +- * Copyright (C) 2014 Cogent Embedded, Inc. +- */ +- +-/* +- * SSI-AK4643 +- * +- * SW1: 1: AK4643 +- * 2: CN22 +- * 3: ADV7511 +- * +- * This command is required when Playback/Capture +- * +- * amixer set "LINEOUT Mixer DACL" on +- * amixer set "DVC Out" 100% +- * amixer set "DVC In" 100% +- * +- * You can use Mute +- * +- * amixer set "DVC Out Mute" on +- * amixer set "DVC In Mute" on +- * +- * You can use Volume Ramp +- * +- * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" +- * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" +- * amixer set "DVC Out Ramp" on +- * aplay xxx.wav & +- * amixer set "DVC Out" 80% // Volume Down +- * amixer set "DVC Out" 100% // Volume Up +- */ +- +-/dts-v1/; +-#include "r8a7791.dtsi" +-#include +-#include +- +-/ { +- model = "Koelsch"; +- compatible = "renesas,koelsch", "renesas,r8a7791"; +- +- aliases { +- serial0 = &scif0; +- serial1 = &scif1; +- i2c9 = &gpioi2c1; +- i2c10 = &gpioi2c2; +- i2c11 = &gpioi2c4; +- i2c12 = &i2cexio1; +- i2c13 = &i2chdmi; +- i2c14 = &i2cexio4; +- mmc0 = &sdhi0; +- mmc1 = &sdhi1; +- mmc2 = &sdhi2; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x40000000>; +- }; +- +- memory@200000000 { +- device_type = "memory"; +- reg = <2 0x00000000 0 0x40000000>; +- }; +- +- lbsc { +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- keyboard { +- compatible = "gpio-keys"; +- +- pinctrl-0 = <&keyboard_pins>; +- pinctrl-names = "default"; +- +- key-1 { +- gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW2-1"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-2 { +- gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW2-2"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-3 { +- gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW2-3"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-4 { +- gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW2-4"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-a { +- gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW30"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-b { +- gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW31"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-c { +- gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW32"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-d { +- gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW33"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-e { +- gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW34"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-f { +- gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW35"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-g { +- gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW36"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led6 { +- gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- label = "LED6"; +- }; +- led7 { +- gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; +- label = "LED7"; +- }; +- led8 { +- gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; +- label = "LED8"; +- }; +- }; +- +- vcc_sdhi0: regulator-vcc-sdhi0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI0 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhi0: regulator-vccq-sdhi0 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI0 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- vcc_sdhi1: regulator-vcc-sdhi1 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI1 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhi1: regulator-vccq-sdhi1 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI1 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- vcc_sdhi2: regulator-vcc-sdhi2 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI2 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhi2: regulator-vccq-sdhi2 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI2 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- audio_clock: audio_clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <11289600>; +- }; +- +- rsnd_ak4643: sound { +- compatible = "simple-audio-card"; +- +- simple-audio-card,format = "left_j"; +- simple-audio-card,bitclock-master = <&sndcodec>; +- simple-audio-card,frame-master = <&sndcodec>; +- +- sndcpu: simple-audio-card,cpu { +- sound-dai = <&rcar_sound>; +- }; +- +- sndcodec: simple-audio-card,codec { +- sound-dai = <&ak4643>; +- clocks = <&audio_clock>; +- }; +- }; +- +- hdmi-in { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&adv7612_in>; +- }; +- }; +- }; +- +- cec_clock: cec-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <12000000>; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_out: endpoint { +- remote-endpoint = <&adv7511_out>; +- }; +- }; +- }; +- +- x2_clk: x2-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <74250000>; +- }; +- +- x13_clk: x13-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <148500000>; +- }; +- +- gpioi2c1: i2c-9 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "i2c-gpio"; +- status = "disabled"; +- scl-gpios = <&gpio7 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <5>; +- }; +- +- gpioi2c2: i2c-10 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "i2c-gpio"; +- status = "disabled"; +- scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <5>; +- }; +- +- gpioi2c4: i2c-11 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "i2c-gpio"; +- status = "disabled"; +- scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <5>; +- }; +- +- /* +- * I2C1 is routed to EXIO connector B, pins 64 (SCL) + 66 (SDA). +- * A fallback to GPIO is provided. +- */ +- i2cexio1: i2c-12 { +- compatible = "i2c-demux-pinctrl"; +- i2c-parent = <&i2c1>, <&gpioi2c1>; +- i2c-bus-name = "i2c-exio1"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- /* +- * A fallback to GPIO is provided for I2C2. +- */ +- i2chdmi: i2c-13 { +- compatible = "i2c-demux-pinctrl"; +- i2c-parent = <&i2c2>, <&gpioi2c2>; +- i2c-bus-name = "i2c-hdmi"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ak4643: codec@12 { +- compatible = "asahi-kasei,ak4643"; +- #sound-dai-cells = <0>; +- reg = <0x12>; +- }; +- +- composite-in@20 { +- compatible = "adi,adv7180"; +- reg = <0x20>; +- +- port { +- adv7180: endpoint { +- bus-width = <8>; +- remote-endpoint = <&vin1ep>; +- }; +- }; +- }; +- +- hdmi@39 { +- compatible = "adi,adv7511w"; +- reg = <0x39>; +- interrupt-parent = <&gpio3>; +- interrupts = <29 IRQ_TYPE_LEVEL_LOW>; +- clocks = <&cec_clock>; +- clock-names = "cec"; +- +- adi,input-depth = <8>; +- adi,input-colorspace = "rgb"; +- adi,input-clock = "1x"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7511_in: endpoint { +- remote-endpoint = <&du_out_rgb>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- adv7511_out: endpoint { +- remote-endpoint = <&hdmi_con_out>; +- }; +- }; +- }; +- }; +- +- hdmi-in@4c { +- compatible = "adi,adv7612"; +- reg = <0x4c>; +- interrupt-parent = <&gpio4>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- default-input = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7612_in: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- adv7612_out: endpoint { +- remote-endpoint = <&vin0ep2>; +- }; +- }; +- }; +- }; +- +- eeprom@50 { +- compatible = "renesas,r1ex24002", "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- }; +- +- /* +- * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA). +- * A fallback to GPIO is provided. +- */ +- i2cexio4: i2c-14 { +- compatible = "i2c-demux-pinctrl"; +- i2c-parent = <&i2c4>, <&gpioi2c4>; +- i2c-bus-name = "i2c-exio4"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +- +-&du { +- pinctrl-0 = <&du_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, +- <&x13_clk>, <&x2_clk>; +- clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; +- +- ports { +- port@0 { +- endpoint { +- remote-endpoint = <&adv7511_in>; +- }; +- }; +- }; +-}; +- +-&lvds0 { +- ports { +- port@1 { +- lvds_connector: endpoint { +- }; +- }; +- }; +-}; +- +-&extal_clk { +- clock-frequency = <20000000>; +-}; +- +-&pfc { +- pinctrl-0 = <&scif_clk_pins>; +- pinctrl-names = "default"; +- +- i2c1_pins: i2c1 { +- groups = "i2c1"; +- function = "i2c1"; +- }; +- +- i2c2_pins: i2c2 { +- groups = "i2c2"; +- function = "i2c2"; +- }; +- +- i2c4_pins: i2c4 { +- groups = "i2c4_c"; +- function = "i2c4"; +- }; +- +- du_pins: du { +- groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; +- function = "du"; +- }; +- +- scif0_pins: scif0 { +- groups = "scif0_data_d"; +- function = "scif0"; +- }; +- +- scif1_pins: scif1 { +- groups = "scif1_data_d"; +- function = "scif1"; +- }; +- +- scif_clk_pins: scif_clk { +- groups = "scif_clk"; +- function = "scif_clk"; +- }; +- +- ether_pins: ether { +- groups = "eth_link", "eth_mdio", "eth_rmii"; +- function = "eth"; +- }; +- +- phy1_pins: phy1 { +- groups = "intc_irq0"; +- function = "intc"; +- }; +- +- pmic_irq_pins: pmicirq { +- groups = "intc_irq2"; +- function = "intc"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <3300>; +- }; +- +- sdhi0_pins_uhs: sd0_uhs { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <1800>; +- }; +- +- sdhi1_pins: sd1 { +- groups = "sdhi1_data4", "sdhi1_ctrl"; +- function = "sdhi1"; +- power-source = <3300>; +- }; +- +- sdhi1_pins_uhs: sd1_uhs { +- groups = "sdhi1_data4", "sdhi1_ctrl"; +- function = "sdhi1"; +- power-source = <1800>; +- }; +- +- sdhi2_pins: sd2 { +- groups = "sdhi2_data4", "sdhi2_ctrl"; +- function = "sdhi2"; +- power-source = <3300>; +- }; +- +- sdhi2_pins_uhs: sd2_uhs { +- groups = "sdhi2_data4", "sdhi2_ctrl"; +- function = "sdhi2"; +- power-source = <1800>; +- }; +- +- qspi_pins: qspi { +- groups = "qspi_ctrl", "qspi_data4"; +- function = "qspi"; +- }; +- +- msiof0_pins: msiof0 { +- groups = "msiof0_clk", "msiof0_sync", "msiof0_rx", +- "msiof0_tx"; +- function = "msiof0"; +- }; +- +- usb0_pins: usb0 { +- groups = "usb0"; +- function = "usb0"; +- }; +- +- usb1_pins: usb1 { +- groups = "usb1"; +- function = "usb1"; +- }; +- +- vin0_pins: vin0 { +- groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; +- function = "vin0"; +- }; +- +- vin1_pins: vin1 { +- groups = "vin1_data8", "vin1_clk"; +- function = "vin1"; +- }; +- +- sound_pins: sound { +- groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; +- function = "ssi"; +- }; +- +- sound_clk_pins: sound_clk { +- groups = "audio_clk_a"; +- function = "audio_clk"; +- }; +- +- keyboard_pins: keyboard { +- pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3"; +- bias-pull-up; +- }; +-}; +- +-ðer { +- pinctrl-0 = <ðer_pins>, <&phy1_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <&phy1>; +- renesas,ether-link-active-low; +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- interrupt-parent = <&irqc0>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- micrel,led-mode = <1>; +- reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&cmt0 { +- status = "okay"; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&sata0 { +- status = "okay"; +-}; +- +-&scif0 { +- pinctrl-0 = <&scif0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scif1 { +- pinctrl-0 = <&scif1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scif_clk { +- clock-frequency = <14745600>; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-1 = <&sdhi0_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <&vcc_sdhi0>; +- vqmmc-supply = <&vccq_sdhi0>; +- cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- status = "okay"; +-}; +- +-&sdhi1 { +- pinctrl-0 = <&sdhi1_pins>; +- pinctrl-1 = <&sdhi1_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <&vcc_sdhi1>; +- vqmmc-supply = <&vccq_sdhi1>; +- cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; +- sd-uhs-sdr50; +- status = "okay"; +-}; +- +-&sdhi2 { +- pinctrl-0 = <&sdhi2_pins>; +- pinctrl-1 = <&sdhi2_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <&vcc_sdhi2>; +- vqmmc-supply = <&vccq_sdhi2>; +- cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; +- sd-uhs-sdr50; +- status = "okay"; +-}; +- +-&qspi { +- pinctrl-0 = <&qspi_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- flash: flash@0 { +- compatible = "spansion,s25fl512s", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <30000000>; +- spi-tx-bus-width = <4>; +- spi-rx-bus-width = <4>; +- spi-cpha; +- spi-cpol; +- m25p,fast-read; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "loader"; +- reg = <0x00000000 0x00080000>; +- read-only; +- }; +- partition@80000 { +- label = "user"; +- reg = <0x00080000 0x00580000>; +- read-only; +- }; +- partition@600000 { +- label = "flash"; +- reg = <0x00600000 0x03a00000>; +- }; +- }; +- }; +-}; +- +-&msiof0 { +- pinctrl-0 = <&msiof0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- pmic: pmic@0 { +- compatible = "renesas,r2a11302ft"; +- reg = <0>; +- spi-max-frequency = <6000000>; +- spi-cpol; +- spi-cpha; +- }; +-}; +- +-&i2c1 { +- pinctrl-0 = <&i2c1_pins>; +- pinctrl-names = "i2c-exio1"; +-}; +- +-&i2c2 { +- pinctrl-0 = <&i2c2_pins>; +- pinctrl-names = "i2c-hdmi"; +- +- clock-frequency = <100000>; +-}; +- +-&i2c4 { +- pinctrl-0 = <&i2c4_pins>; +- pinctrl-names = "i2c-exio4"; +-}; +- +-&i2c6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_irq_pins>; +- status = "okay"; +- clock-frequency = <100000>; +- +- pmic@58 { +- compatible = "dlg,da9063"; +- reg = <0x58>; +- interrupt-parent = <&irqc0>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- +- rtc { +- compatible = "dlg,da9063-rtc"; +- }; +- +- wdt { +- compatible = "dlg,da9063-watchdog"; +- }; +- }; +- +- vdd_dvfs: regulator@68 { +- compatible = "dlg,da9210"; +- reg = <0x68>; +- interrupt-parent = <&irqc0>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&pci0 { +- status = "okay"; +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +-}; +- +-&pci1 { +- status = "okay"; +- pinctrl-0 = <&usb1_pins>; +- pinctrl-names = "default"; +-}; +- +-&hsusb { +- status = "okay"; +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +- renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&pcie_bus_clk { +- clock-frequency = <100000000>; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu0-supply = <&vdd_dvfs>; +-}; +- +-/* HDMI video input */ +-&vin0 { +- status = "okay"; +- pinctrl-0 = <&vin0_pins>; +- pinctrl-names = "default"; +- +- port { +- vin0ep2: endpoint { +- remote-endpoint = <&adv7612_out>; +- bus-width = <24>; +- hsync-active = <0>; +- vsync-active = <0>; +- pclk-sample = <1>; +- data-active = <1>; +- }; +- }; +-}; +- +-/* composite video input */ +-&vin1 { +- status = "okay"; +- pinctrl-0 = <&vin1_pins>; +- pinctrl-names = "default"; +- +- port { +- vin1ep: endpoint { +- remote-endpoint = <&adv7180>; +- bus-width = <8>; +- }; +- }; +-}; +- +-&rcar_sound { +- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; +- pinctrl-names = "default"; +- +- /* Single DAI */ +- #sound-dai-cells = <0>; +- +- status = "okay"; +- +- rcar_sound,dai { +- dai0 { +- playback = <&ssi0>, <&src2>, <&dvc0>; +- capture = <&ssi1>, <&src3>, <&dvc1>; +- }; +- }; +-}; +- +-&ssi1 { +- shared-pin; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7791-porter.dts b/scripts/dtc/include-prefixes/arm/r8a7791-porter.dts +deleted file mode 100644 +index c6ef636965c1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7791-porter.dts ++++ /dev/null +@@ -1,521 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Porter board +- * +- * Copyright (C) 2015 Cogent Embedded, Inc. +- */ +- +-/* +- * SSI-AK4642 +- * +- * JP3: 2-1: AK4642 +- * 2-3: ADV7511 +- * +- * This command is required before playback/capture: +- * +- * amixer set "LINEOUT Mixer DACL" on +- */ +- +-/dts-v1/; +-#include "r8a7791.dtsi" +-#include +- +-/ { +- model = "Porter"; +- compatible = "renesas,porter", "renesas,r8a7791"; +- +- aliases { +- serial0 = &scif0; +- i2c9 = &gpioi2c2; +- i2c10 = &i2chdmi; +- mmc0 = &sdhi0; +- mmc1 = &sdhi2; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x40000000>; +- }; +- +- memory@200000000 { +- device_type = "memory"; +- reg = <2 0x00000000 0 0x40000000>; +- }; +- +- vcc_sdhi0: regulator-vcc-sdhi0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI0 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vccq_sdhi0: regulator-vccq-sdhi0 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI0 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- vcc_sdhi2: regulator-vcc-sdhi2 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI2 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vccq_sdhi2: regulator-vccq-sdhi2 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI2 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con: endpoint { +- remote-endpoint = <&adv7511_out>; +- }; +- }; +- }; +- +- x3_clk: x3-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <148500000>; +- }; +- +- x16_clk: x16-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <74250000>; +- }; +- +- x14_clk: audio_clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <11289600>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- +- simple-audio-card,format = "left_j"; +- simple-audio-card,bitclock-master = <&soundcodec>; +- simple-audio-card,frame-master = <&soundcodec>; +- +- simple-audio-card,cpu { +- sound-dai = <&rcar_sound>; +- }; +- +- soundcodec: simple-audio-card,codec { +- sound-dai = <&ak4642>; +- clocks = <&x14_clk>; +- }; +- }; +- +- gpioi2c2: i2c-9 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "i2c-gpio"; +- status = "disabled"; +- scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <5>; +- }; +- +- /* +- * A fallback to GPIO is provided for I2C2. +- */ +- i2chdmi: i2c-10 { +- compatible = "i2c-demux-pinctrl"; +- i2c-parent = <&i2c2>, <&gpioi2c2>; +- i2c-bus-name = "i2c-hdmi"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ak4642: codec@12 { +- compatible = "asahi-kasei,ak4642"; +- #sound-dai-cells = <0>; +- reg = <0x12>; +- }; +- +- composite-in@20 { +- compatible = "adi,adv7180"; +- reg = <0x20>; +- +- port { +- adv7180: endpoint { +- bus-width = <8>; +- remote-endpoint = <&vin0ep>; +- }; +- }; +- }; +- +- hdmi@39 { +- compatible = "adi,adv7511w"; +- reg = <0x39>; +- interrupt-parent = <&gpio3>; +- interrupts = <29 IRQ_TYPE_LEVEL_LOW>; +- +- adi,input-depth = <8>; +- adi,input-colorspace = "rgb"; +- adi,input-clock = "1x"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7511_in: endpoint { +- remote-endpoint = <&du_out_rgb>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- adv7511_out: endpoint { +- remote-endpoint = <&hdmi_con>; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&extal_clk { +- clock-frequency = <20000000>; +-}; +- +-&pfc { +- scif0_pins: scif0 { +- groups = "scif0_data_d"; +- function = "scif0"; +- }; +- +- ether_pins: ether { +- groups = "eth_link", "eth_mdio", "eth_rmii"; +- function = "eth"; +- }; +- +- phy1_pins: phy1 { +- groups = "intc_irq0"; +- function = "intc"; +- }; +- +- pmic_irq_pins: pmicirq { +- groups = "intc_irq2"; +- function = "intc"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- }; +- +- sdhi2_pins: sd2 { +- groups = "sdhi2_data4", "sdhi2_ctrl"; +- function = "sdhi2"; +- }; +- +- qspi_pins: qspi { +- groups = "qspi_ctrl", "qspi_data4"; +- function = "qspi"; +- }; +- +- i2c2_pins: i2c2 { +- groups = "i2c2"; +- function = "i2c2"; +- }; +- +- usb0_pins: usb0 { +- groups = "usb0"; +- function = "usb0"; +- }; +- +- usb1_pins: usb1 { +- groups = "usb1"; +- function = "usb1"; +- }; +- +- vin0_pins: vin0 { +- groups = "vin0_data8", "vin0_clk"; +- function = "vin0"; +- }; +- +- can0_pins: can0 { +- groups = "can0_data"; +- function = "can0"; +- }; +- +- du_pins: du { +- groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; +- function = "du"; +- }; +- +- ssi_pins: sound { +- groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; +- function = "ssi"; +- }; +- +- audio_clk_pins: audio_clk { +- groups = "audio_clk_a"; +- function = "audio_clk"; +- }; +-}; +- +-&scif0 { +- pinctrl-0 = <&scif0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-ðer { +- pinctrl-0 = <ðer_pins>, <&phy1_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <&phy1>; +- renesas,ether-link-active-low; +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- interrupt-parent = <&irqc0>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- micrel,led-mode = <1>; +- reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <&vcc_sdhi0>; +- vqmmc-supply = <&vccq_sdhi0>; +- cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&sdhi2 { +- pinctrl-0 = <&sdhi2_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <&vcc_sdhi2>; +- vqmmc-supply = <&vccq_sdhi2>; +- cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&qspi { +- pinctrl-0 = <&qspi_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- flash@0 { +- compatible = "spansion,s25fl512s", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <30000000>; +- spi-tx-bus-width = <4>; +- spi-rx-bus-width = <4>; +- m25p,fast-read; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "loader_prg"; +- reg = <0x00000000 0x00040000>; +- read-only; +- }; +- partition@40000 { +- label = "user_prg"; +- reg = <0x00040000 0x00400000>; +- read-only; +- }; +- partition@440000 { +- label = "flash_fs"; +- reg = <0x00440000 0x03bc0000>; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-0 = <&i2c2_pins>; +- pinctrl-names = "i2c-hdmi"; +- +- clock-frequency = <400000>; +-}; +- +-&i2c6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_irq_pins>; +- status = "okay"; +- clock-frequency = <100000>; +- +- pmic@5a { +- compatible = "dlg,da9063l"; +- reg = <0x5a>; +- interrupt-parent = <&irqc0>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- +- wdt { +- compatible = "dlg,da9063-watchdog"; +- }; +- }; +- +- vdd_dvfs: regulator@68 { +- compatible = "dlg,da9210"; +- reg = <0x68>; +- interrupt-parent = <&irqc0>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&sata0 { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu0-supply = <&vdd_dvfs>; +-}; +- +-/* composite video input */ +-&vin0 { +- status = "okay"; +- pinctrl-0 = <&vin0_pins>; +- pinctrl-names = "default"; +- +- port { +- vin0ep: endpoint { +- remote-endpoint = <&adv7180>; +- bus-width = <8>; +- }; +- }; +-}; +- +-&pci0 { +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&pci1 { +- pinctrl-0 = <&usb1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&hsusb { +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&pcie_bus_clk { +- clock-frequency = <100000000>; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&can0 { +- pinctrl-0 = <&can0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&du { +- pinctrl-0 = <&du_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, +- <&x3_clk>, <&x16_clk>; +- clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; +- +- ports { +- port@0 { +- endpoint { +- remote-endpoint = <&adv7511_in>; +- }; +- }; +- }; +-}; +- +-&lvds0 { +- ports { +- port@1 { +- lvds_connector: endpoint { +- }; +- }; +- }; +-}; +- +-&rcar_sound { +- pinctrl-0 = <&ssi_pins>, <&audio_clk_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- /* Single DAI */ +- #sound-dai-cells = <0>; +- +- rcar_sound,dai { +- dai0 { +- playback = <&ssi0>; +- capture = <&ssi1>; +- }; +- }; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&ssi1 { +- shared-pin; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7791.dtsi b/scripts/dtc/include-prefixes/arm/r8a7791.dtsi +deleted file mode 100644 +index 0ccc162d3c2c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7791.dtsi ++++ /dev/null +@@ -1,1890 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Car M2-W (R8A77910) SoC +- * +- * Copyright (C) 2013-2015 Renesas Electronics Corporation +- * Copyright (C) 2013-2014 Renesas Solutions Corp. +- * Copyright (C) 2014 Cogent Embedded Inc. +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r8a7791"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c7; +- i2c8 = &i2c8; +- spi0 = &qspi; +- spi1 = &msiof0; +- spi2 = &msiof1; +- spi3 = &msiof2; +- vin0 = &vin0; +- vin1 = &vin1; +- vin2 = &vin2; +- }; +- +- /* +- * The external audio clocks are configured as 0 Hz fixed frequency +- * clocks by default. +- * Boards that provide audio clocks should override them. +- */ +- audio_clk_a: audio_clk_a { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- audio_clk_b: audio_clk_b { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- audio_clk_c: audio_clk_c { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* External CAN clock */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0>; +- clock-frequency = <1500000000>; +- clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; +- power-domains = <&sysc R8A7791_PD_CA15_CPU0>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA15>; +- voltage-tolerance = <1>; /* 1% */ +- clock-latency = <300000>; /* 300 us */ +- +- /* kHz - uV - OPPs unknown yet */ +- operating-points = <1500000 1000000>, +- <1312500 1000000>, +- <1125000 1000000>, +- < 937500 1000000>, +- < 750000 1000000>, +- < 375000 1000000>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <1>; +- clock-frequency = <1500000000>; +- clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; +- power-domains = <&sysc R8A7791_PD_CA15_CPU1>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA15>; +- voltage-tolerance = <1>; /* 1% */ +- clock-latency = <300000>; /* 300 us */ +- +- /* kHz - uV - OPPs unknown yet */ +- operating-points = <1500000 1000000>, +- <1312500 1000000>, +- <1125000 1000000>, +- < 937500 1000000>, +- < 750000 1000000>, +- < 375000 1000000>; +- }; +- +- L2_CA15: cache-controller-0 { +- compatible = "cache"; +- power-domains = <&sysc R8A7791_PD_CA15_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- }; +- +- /* External root clock */ +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- /* External PCIe clock - can be overridden by the board */ +- pcie_bus_clk: pcie_bus { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- pmu { +- compatible = "arm,cortex-a15-pmu"; +- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- /* External SCIF clock */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a7791-wdt", +- "renesas,rcar-gen2-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a7791", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a7791", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a7791", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a7791", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a7791", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a7791", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- gpio6: gpio@e6055400 { +- compatible = "renesas,gpio-r8a7791", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055400 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 192 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 905>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 905>; +- }; +- +- gpio7: gpio@e6055800 { +- compatible = "renesas,gpio-r8a7791", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055800 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 224 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 904>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 904>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a7791"; +- reg = <0 0xe6060000 0 0x250>; +- }; +- +- tpu: pwm@e60f0000 { +- compatible = "renesas,tpu-r8a7791", "renesas,tpu"; +- reg = <0 0xe60f0000 0 0x148>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 304>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 304>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a7791-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>, <&usb_extal_clk>; +- clock-names = "extal", "usb_extal"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- apmu@e6152000 { +- compatible = "renesas,r8a7791-apmu", "renesas,apmu"; +- reg = <0 0xe6152000 0 0x188>; +- cpus = <&cpu0>, <&cpu1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a7791-rst"; +- reg = <0 0xe6160000 0 0x0100>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a7791-sysc"; +- reg = <0 0xe6180000 0 0x0200>; +- #power-domain-cells = <1>; +- }; +- +- irqc0: interrupt-controller@e61c0000 { +- compatible = "renesas,irqc-r8a7791", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- thermal: thermal@e61f0000 { +- compatible = "renesas,thermal-r8a7791", +- "renesas,rcar-gen2-thermal", +- "renesas,rcar-thermal"; +- reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 522>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 522>; +- #thermal-sensor-cells = <0>; +- }; +- +- ipmmu_sy0: iommu@e6280000 { +- compatible = "renesas,ipmmu-r8a7791", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6280000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_sy1: iommu@e6290000 { +- compatible = "renesas,ipmmu-r8a7791", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6290000 0 0x1000>; +- interrupts = ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_ds: iommu@e6740000 { +- compatible = "renesas,ipmmu-r8a7791", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6740000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_mp: iommu@ec680000 { +- compatible = "renesas,ipmmu-r8a7791", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xec680000 0 0x1000>; +- interrupts = ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_mx: iommu@fe951000 { +- compatible = "renesas,ipmmu-r8a7791", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xfe951000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_rt: iommu@ffc80000 { +- compatible = "renesas,ipmmu-r8a7791", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xffc80000 0 0x1000>; +- interrupts = ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_gp: iommu@e62a0000 { +- compatible = "renesas,ipmmu-r8a7791", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe62a0000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- icram0: sram@e63a0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63a0000 0 0x12000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63a0000 0x12000>; +- }; +- +- icram1: sram@e63c0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63c0000 0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63c0000 0x1000>; +- +- smp-sram@0 { +- compatible = "renesas,smp-sram"; +- reg = <0 0x100>; +- }; +- }; +- +- /* The memory map in the User's Manual maps the cores to +- * bus numbers +- */ +- i2c0: i2c@e6508000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7791", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6518000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7791", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6518000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6530000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7791", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6530000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e6540000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7791", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6540000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e6520000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7791", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6520000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 927>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 927>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c5: i2c@e6528000 { +- /* doesn't need pinmux */ +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7791", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6528000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 925>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 925>; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c6: i2c@e60b0000 { +- /* doesn't need pinmux */ +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7791", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe60b0000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 926>; +- dmas = <&dmac0 0x77>, <&dmac0 0x78>, +- <&dmac1 0x77>, <&dmac1 0x78>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 926>; +- status = "disabled"; +- }; +- +- i2c7: i2c@e6500000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7791", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe6500000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 318>; +- dmas = <&dmac0 0x61>, <&dmac0 0x62>, +- <&dmac1 0x61>, <&dmac1 0x62>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 318>; +- status = "disabled"; +- }; +- +- i2c8: i2c@e6510000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7791", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe6510000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 323>; +- dmas = <&dmac0 0x65>, <&dmac0 0x66>, +- <&dmac1 0x65>, <&dmac1 0x66>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 323>; +- status = "disabled"; +- }; +- +- hsusb: usb@e6590000 { +- compatible = "renesas,usbhs-r8a7791", +- "renesas,rcar-gen2-usbhs"; +- reg = <0 0xe6590000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 704>; +- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, +- <&usb_dmac1 0>, <&usb_dmac1 1>; +- dma-names = "ch0", "ch1", "ch2", "ch3"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 704>; +- renesas,buswait = <4>; +- phys = <&usb0 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usbphy: usb-phy@e6590100 { +- compatible = "renesas,usb-phy-r8a7791", +- "renesas,rcar-gen2-usb-phy"; +- reg = <0 0xe6590100 0 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cpg CPG_MOD 704>; +- clock-names = "usbhs"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 704>; +- status = "disabled"; +- +- usb0: usb-channel@0 { +- reg = <0>; +- #phy-cells = <1>; +- }; +- usb2: usb-channel@2 { +- reg = <2>; +- #phy-cells = <1>; +- }; +- }; +- +- usb_dmac0: dma-controller@e65a0000 { +- compatible = "renesas,r8a7791-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65a0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 330>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 330>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac1: dma-controller@e65b0000 { +- compatible = "renesas,r8a7791-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65b0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 331>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 331>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a7791", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- dmac1: dma-controller@e6720000 { +- compatible = "renesas,dmac-r8a7791", +- "renesas,rcar-dmac"; +- reg = <0 0xe6720000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a7791", +- "renesas,etheravb-rcar-gen2"; +- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- qspi: spi@e6b10000 { +- compatible = "renesas,qspi-r8a7791", "renesas,qspi"; +- reg = <0 0xe6b10000 0 0x2c>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 917>; +- dmas = <&dmac0 0x17>, <&dmac0 0x18>, +- <&dmac1 0x17>, <&dmac1 0x18>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 917>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- scifa0: serial@e6c40000 { +- compatible = "renesas,scifa-r8a7791", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c40000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>; +- clock-names = "fck"; +- dmas = <&dmac0 0x21>, <&dmac0 0x22>, +- <&dmac1 0x21>, <&dmac1 0x22>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scifa1: serial@e6c50000 { +- compatible = "renesas,scifa-r8a7791", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c50000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>; +- clock-names = "fck"; +- dmas = <&dmac0 0x25>, <&dmac0 0x26>, +- <&dmac1 0x25>, <&dmac1 0x26>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- scifa2: serial@e6c60000 { +- compatible = "renesas,scifa-r8a7791", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c60000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 202>; +- clock-names = "fck"; +- dmas = <&dmac0 0x27>, <&dmac0 0x28>, +- <&dmac1 0x27>, <&dmac1 0x28>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 202>; +- status = "disabled"; +- }; +- +- scifa3: serial@e6c70000 { +- compatible = "renesas,scifa-r8a7791", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c70000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1106>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, +- <&dmac1 0x1b>, <&dmac1 0x1c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 1106>; +- status = "disabled"; +- }; +- +- scifa4: serial@e6c78000 { +- compatible = "renesas,scifa-r8a7791", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c78000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1107>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1f>, <&dmac0 0x20>, +- <&dmac1 0x1f>, <&dmac1 0x20>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 1107>; +- status = "disabled"; +- }; +- +- scifa5: serial@e6c80000 { +- compatible = "renesas,scifa-r8a7791", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c80000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1108>; +- clock-names = "fck"; +- dmas = <&dmac0 0x23>, <&dmac0 0x24>, +- <&dmac1 0x23>, <&dmac1 0x24>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 1108>; +- status = "disabled"; +- }; +- +- scifb0: serial@e6c20000 { +- compatible = "renesas,scifb-r8a7791", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6c20000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>; +- clock-names = "fck"; +- dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, +- <&dmac1 0x3d>, <&dmac1 0x3e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scifb1: serial@e6c30000 { +- compatible = "renesas,scifb-r8a7791", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6c30000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>; +- clock-names = "fck"; +- dmas = <&dmac0 0x19>, <&dmac0 0x1a>, +- <&dmac1 0x19>, <&dmac1 0x1a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scifb2: serial@e6ce0000 { +- compatible = "renesas,scifb-r8a7791", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6ce0000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 216>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, +- <&dmac1 0x1d>, <&dmac1 0x1e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 216>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a7791", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e60000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x29>, <&dmac0 0x2a>, +- <&dmac1 0x29>, <&dmac1 0x2a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 721>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a7791", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e68000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, +- <&dmac1 0x2d>, <&dmac1 0x2e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 720>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e58000 { +- compatible = "renesas,scif-r8a7791", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e58000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, +- <&dmac1 0x2b>, <&dmac1 0x2c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 719>; +- status = "disabled"; +- }; +- +- scif3: serial@e6ea8000 { +- compatible = "renesas,scif-r8a7791", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ea8000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2f>, <&dmac0 0x30>, +- <&dmac1 0x2f>, <&dmac1 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 718>; +- status = "disabled"; +- }; +- +- scif4: serial@e6ee0000 { +- compatible = "renesas,scif-r8a7791", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ee0000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, +- <&dmac1 0xfb>, <&dmac1 0xfc>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 715>; +- status = "disabled"; +- }; +- +- scif5: serial@e6ee8000 { +- compatible = "renesas,scif-r8a7791", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ee8000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, +- <&dmac1 0xfd>, <&dmac1 0xfe>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 714>; +- status = "disabled"; +- }; +- +- hscif0: serial@e62c0000 { +- compatible = "renesas,hscif-r8a7791", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c0000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x39>, <&dmac0 0x3a>, +- <&dmac1 0x39>, <&dmac1 0x3a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 717>; +- status = "disabled"; +- }; +- +- hscif1: serial@e62c8000 { +- compatible = "renesas,hscif-r8a7791", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c8000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, +- <&dmac1 0x4d>, <&dmac1 0x4e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- }; +- +- hscif2: serial@e62d0000 { +- compatible = "renesas,hscif-r8a7791", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62d0000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, +- <&dmac1 0x3b>, <&dmac1 0x3c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 713>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e20000 { +- compatible = "renesas,msiof-r8a7791", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e20000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 000>; +- dmas = <&dmac0 0x51>, <&dmac0 0x52>, +- <&dmac1 0x51>, <&dmac1 0x52>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6e10000 { +- compatible = "renesas,msiof-r8a7791", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e10000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 208>; +- dmas = <&dmac0 0x55>, <&dmac0 0x56>, +- <&dmac1 0x55>, <&dmac1 0x56>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 208>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6e00000 { +- compatible = "renesas,msiof-r8a7791", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e00000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 205>; +- dmas = <&dmac0 0x41>, <&dmac0 0x42>, +- <&dmac1 0x41>, <&dmac1 0x42>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 205>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pwm0: pwm@e6e30000 { +- compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; +- reg = <0 0xe6e30000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm1: pwm@e6e31000 { +- compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; +- reg = <0 0xe6e31000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm2: pwm@e6e32000 { +- compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; +- reg = <0 0xe6e32000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm3: pwm@e6e33000 { +- compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; +- reg = <0 0xe6e33000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm4: pwm@e6e34000 { +- compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; +- reg = <0 0xe6e34000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm5: pwm@e6e35000 { +- compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; +- reg = <0 0xe6e35000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm6: pwm@e6e36000 { +- compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; +- reg = <0 0xe6e36000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- adc: adc@e6e54000 { +- compatible = "renesas,r8a7791-gyroadc", +- "renesas,rcar-gyroadc"; +- reg = <0 0xe6e54000 0 64>; +- clocks = <&cpg CPG_MOD 901>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 901>; +- status = "disabled"; +- }; +- +- can0: can@e6e80000 { +- compatible = "renesas,can-r8a7791", +- "renesas,rcar-gen2-can"; +- reg = <0 0xe6e80000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>, +- <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- status = "disabled"; +- }; +- +- can1: can@e6e88000 { +- compatible = "renesas,can-r8a7791", +- "renesas,rcar-gen2-can"; +- reg = <0 0xe6e88000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>, +- <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- status = "disabled"; +- }; +- +- vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a7791", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef0000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 811>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 811>; +- status = "disabled"; +- }; +- +- vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a7791", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef1000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 810>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 810>; +- status = "disabled"; +- }; +- +- vin2: video@e6ef2000 { +- compatible = "renesas,vin-r8a7791", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef2000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 809>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 809>; +- status = "disabled"; +- }; +- +- rcar_sound: sound@ec500000 { +- /* +- * #sound-dai-cells is required +- * +- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; +- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; +- */ +- compatible = "renesas,rcar_sound-r8a7791", +- "renesas,rcar_sound-gen2"; +- reg = <0 0xec500000 0 0x1000>, /* SCU */ +- <0 0xec5a0000 0 0x100>, /* ADG */ +- <0 0xec540000 0 0x1000>, /* SSIU */ +- <0 0xec541000 0 0x280>, /* SSI */ +- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ +- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; +- +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, +- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, +- <&cpg CPG_CORE R8A7791_CLK_M2>; +- clock-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0", "src.9", "src.8", +- "src.7", "src.6", "src.5", "src.4", +- "src.3", "src.2", "src.1", "src.0", +- "ctu.0", "ctu.1", +- "mix.0", "mix.1", +- "dvc.0", "dvc.1", +- "clk_a", "clk_b", "clk_c", "clk_i"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 1005>, +- <&cpg 1006>, <&cpg 1007>, +- <&cpg 1008>, <&cpg 1009>, +- <&cpg 1010>, <&cpg 1011>, +- <&cpg 1012>, <&cpg 1013>, +- <&cpg 1014>, <&cpg 1015>; +- reset-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0"; +- +- status = "disabled"; +- +- rcar_sound,dvc { +- dvc0: dvc-0 { +- dmas = <&audma1 0xbc>; +- dma-names = "tx"; +- }; +- dvc1: dvc-1 { +- dmas = <&audma1 0xbe>; +- dma-names = "tx"; +- }; +- }; +- +- rcar_sound,mix { +- mix0: mix-0 { }; +- mix1: mix-1 { }; +- }; +- +- rcar_sound,ctu { +- ctu00: ctu-0 { }; +- ctu01: ctu-1 { }; +- ctu02: ctu-2 { }; +- ctu03: ctu-3 { }; +- ctu10: ctu-4 { }; +- ctu11: ctu-5 { }; +- ctu12: ctu-6 { }; +- ctu13: ctu-7 { }; +- }; +- +- rcar_sound,src { +- src0: src-0 { +- interrupts = ; +- dmas = <&audma0 0x85>, <&audma1 0x9a>; +- dma-names = "rx", "tx"; +- }; +- src1: src-1 { +- interrupts = ; +- dmas = <&audma0 0x87>, <&audma1 0x9c>; +- dma-names = "rx", "tx"; +- }; +- src2: src-2 { +- interrupts = ; +- dmas = <&audma0 0x89>, <&audma1 0x9e>; +- dma-names = "rx", "tx"; +- }; +- src3: src-3 { +- interrupts = ; +- dmas = <&audma0 0x8b>, <&audma1 0xa0>; +- dma-names = "rx", "tx"; +- }; +- src4: src-4 { +- interrupts = ; +- dmas = <&audma0 0x8d>, <&audma1 0xb0>; +- dma-names = "rx", "tx"; +- }; +- src5: src-5 { +- interrupts = ; +- dmas = <&audma0 0x8f>, <&audma1 0xb2>; +- dma-names = "rx", "tx"; +- }; +- src6: src-6 { +- interrupts = ; +- dmas = <&audma0 0x91>, <&audma1 0xb4>; +- dma-names = "rx", "tx"; +- }; +- src7: src-7 { +- interrupts = ; +- dmas = <&audma0 0x93>, <&audma1 0xb6>; +- dma-names = "rx", "tx"; +- }; +- src8: src-8 { +- interrupts = ; +- dmas = <&audma0 0x95>, <&audma1 0xb8>; +- dma-names = "rx", "tx"; +- }; +- src9: src-9 { +- interrupts = ; +- dmas = <&audma0 0x97>, <&audma1 0xba>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssi { +- ssi0: ssi-0 { +- interrupts = ; +- dmas = <&audma0 0x01>, <&audma1 0x02>, +- <&audma0 0x15>, <&audma1 0x16>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi1: ssi-1 { +- interrupts = ; +- dmas = <&audma0 0x03>, <&audma1 0x04>, +- <&audma0 0x49>, <&audma1 0x4a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi2: ssi-2 { +- interrupts = ; +- dmas = <&audma0 0x05>, <&audma1 0x06>, +- <&audma0 0x63>, <&audma1 0x64>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi3: ssi-3 { +- interrupts = ; +- dmas = <&audma0 0x07>, <&audma1 0x08>, +- <&audma0 0x6f>, <&audma1 0x70>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi4: ssi-4 { +- interrupts = ; +- dmas = <&audma0 0x09>, <&audma1 0x0a>, +- <&audma0 0x71>, <&audma1 0x72>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi5: ssi-5 { +- interrupts = ; +- dmas = <&audma0 0x0b>, <&audma1 0x0c>, +- <&audma0 0x73>, <&audma1 0x74>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi6: ssi-6 { +- interrupts = ; +- dmas = <&audma0 0x0d>, <&audma1 0x0e>, +- <&audma0 0x75>, <&audma1 0x76>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi7: ssi-7 { +- interrupts = ; +- dmas = <&audma0 0x0f>, <&audma1 0x10>, +- <&audma0 0x79>, <&audma1 0x7a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi8: ssi-8 { +- interrupts = ; +- dmas = <&audma0 0x11>, <&audma1 0x12>, +- <&audma0 0x7b>, <&audma1 0x7c>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi9: ssi-9 { +- interrupts = ; +- dmas = <&audma0 0x13>, <&audma1 0x14>, +- <&audma0 0x7d>, <&audma1 0x7e>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- }; +- }; +- +- audma0: dma-controller@ec700000 { +- compatible = "renesas,dmac-r8a7791", +- "renesas,rcar-dmac"; +- reg = <0 0xec700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12"; +- clocks = <&cpg CPG_MOD 502>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 502>; +- #dma-cells = <1>; +- dma-channels = <13>; +- }; +- +- audma1: dma-controller@ec720000 { +- compatible = "renesas,dmac-r8a7791", +- "renesas,rcar-dmac"; +- reg = <0 0xec720000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12"; +- clocks = <&cpg CPG_MOD 501>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 501>; +- #dma-cells = <1>; +- dma-channels = <13>; +- }; +- +- xhci: usb@ee000000 { +- compatible = "renesas,xhci-r8a7791", +- "renesas,rcar-gen2-xhci"; +- reg = <0 0xee000000 0 0xc00>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- phys = <&usb2 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- pci0: pci@ee090000 { +- compatible = "renesas,pci-r8a7791", +- "renesas,pci-rcar-gen2"; +- device_type = "pci"; +- reg = <0 0xee090000 0 0xc00>, +- <0 0xee080000 0 0x1100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- status = "disabled"; +- +- bus-range = <0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; +- interrupt-map-mask = <0xf800 0 0 0x7>; +- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, +- <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, +- <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; +- +- usb@1,0 { +- reg = <0x800 0 0 0 0>; +- phys = <&usb0 0>; +- phy-names = "usb"; +- }; +- +- usb@2,0 { +- reg = <0x1000 0 0 0 0>; +- phys = <&usb0 0>; +- phy-names = "usb"; +- }; +- }; +- +- pci1: pci@ee0d0000 { +- compatible = "renesas,pci-r8a7791", +- "renesas,pci-rcar-gen2"; +- device_type = "pci"; +- reg = <0 0xee0d0000 0 0xc00>, +- <0 0xee0c0000 0 0x1100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- status = "disabled"; +- +- bus-range = <1 1>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; +- interrupt-map-mask = <0xf800 0 0 0x7>; +- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, +- <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, +- <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; +- +- usb@1,0 { +- reg = <0x10800 0 0 0 0>; +- phys = <&usb2 0>; +- phy-names = "usb"; +- }; +- +- usb@2,0 { +- reg = <0x11000 0 0 0 0>; +- phys = <&usb2 0>; +- phy-names = "usb"; +- }; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a7791", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee100000 0 0x328>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- dmas = <&dmac0 0xcd>, <&dmac0 0xce>, +- <&dmac1 0xcd>, <&dmac1 0xce>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <195000000>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a7791", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee140000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 312>; +- dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, +- <&dmac1 0xc1>, <&dmac1 0xc2>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <97500000>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 312>; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ee160000 { +- compatible = "renesas,sdhi-r8a7791", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee160000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 311>; +- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, +- <&dmac1 0xd3>, <&dmac1 0xd4>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <97500000>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 311>; +- status = "disabled"; +- }; +- +- mmcif0: mmc@ee200000 { +- compatible = "renesas,mmcif-r8a7791", +- "renesas,sh-mmcif"; +- reg = <0 0xee200000 0 0x80>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 315>; +- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, +- <&dmac1 0xd1>, <&dmac1 0xd2>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 315>; +- reg-io-width = <4>; +- status = "disabled"; +- max-frequency = <97500000>; +- }; +- +- sata0: sata@ee300000 { +- compatible = "renesas,sata-r8a7791", +- "renesas,rcar-gen2-sata"; +- reg = <0 0xee300000 0 0x200000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 815>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 815>; +- status = "disabled"; +- }; +- +- sata1: sata@ee500000 { +- compatible = "renesas,sata-r8a7791", +- "renesas,rcar-gen2-sata"; +- reg = <0 0xee500000 0 0x200000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 814>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 814>; +- status = "disabled"; +- }; +- +- ether: ethernet@ee700000 { +- compatible = "renesas,ether-r8a7791", +- "renesas,rcar-gen2-ether"; +- reg = <0 0xee700000 0 0x400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 813>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 813>; +- phy-mode = "rmii"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1001000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, +- <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- pciec: pcie@fe000000 { +- compatible = "renesas,pcie-r8a7791", +- "renesas,pcie-rcar-gen2"; +- reg = <0 0xfe000000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, +- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, +- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, +- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, +- <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 319>; +- status = "disabled"; +- }; +- +- vsp@fe928000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe928000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 131>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 131>; +- }; +- +- vsp@fe930000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe930000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 128>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 128>; +- }; +- +- vsp@fe938000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe938000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 127>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 127>; +- }; +- +- fdp1@fe940000 { +- compatible = "renesas,fdp1"; +- reg = <0 0xfe940000 0 0x2400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 119>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 119>; +- }; +- +- fdp1@fe944000 { +- compatible = "renesas,fdp1"; +- reg = <0 0xfe944000 0 0x2400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 118>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 118>; +- }; +- +- jpu: jpeg-codec@fe980000 { +- compatible = "renesas,jpu-r8a7791", +- "renesas,rcar-gen2-jpu"; +- reg = <0 0xfe980000 0 0x10300>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 106>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 106>; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a7791"; +- reg = <0 0xfeb00000 0 0x40000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; +- clock-names = "du.0", "du.1"; +- resets = <&cpg 724>; +- reset-names = "du.0"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb: endpoint { +- }; +- }; +- port@1 { +- reg = <1>; +- du_out_lvds0: endpoint { +- remote-endpoint = <&lvds0_in>; +- }; +- }; +- }; +- }; +- +- lvds0: lvds@feb90000 { +- compatible = "renesas,r8a7791-lvds"; +- reg = <0 0xfeb90000 0 0x1c>; +- clocks = <&cpg CPG_MOD 726>; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 726>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds0_in: endpoint { +- remote-endpoint = <&du_out_lvds0>; +- }; +- }; +- port@1 { +- reg = <1>; +- lvds0_out: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@ff000044 { +- compatible = "renesas,prr"; +- reg = <0 0xff000044 0 4>; +- }; +- +- cmt0: timer@ffca0000 { +- compatible = "renesas,r8a7791-cmt0", +- "renesas,rcar-gen2-cmt0"; +- reg = <0 0xffca0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a7791-cmt1", +- "renesas,rcar-gen2-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 329>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; +- resets = <&cpg 329>; +- +- status = "disabled"; +- }; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&thermal>; +- +- trips { +- cpu-crit { +- temperature = <95000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- cooling-maps { +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +- }; +- +- /* External USB clock - can be overridden by the board */ +- usb_extal_clk: usb_extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <48000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7792-blanche.dts b/scripts/dtc/include-prefixes/arm/r8a7792-blanche.dts +deleted file mode 100644 +index 62aa9f61321b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7792-blanche.dts ++++ /dev/null +@@ -1,364 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Blanche board +- * +- * Copyright (C) 2014 Renesas Electronics Corporation +- * Copyright (C) 2016 Cogent Embedded, Inc. +- */ +- +-/dts-v1/; +-#include "r8a7792.dtsi" +-#include +-#include +- +-/ { +- model = "Blanche"; +- compatible = "renesas,blanche", "renesas,r8a7792"; +- +- aliases { +- serial0 = &scif0; +- serial1 = &scif3; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x40000000>; +- }; +- +- d3_3v: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "D3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ethernet@18000000 { +- compatible = "smsc,lan89218", "smsc,lan9115"; +- reg = <0 0x18000000 0 0x100>; +- phy-mode = "mii"; +- interrupt-parent = <&irqc>; +- interrupts = <0 IRQ_TYPE_EDGE_FALLING>; +- smsc,irq-push-pull; +- reg-io-width = <4>; +- vddvario-supply = <&d3_3v>; +- vdd33a-supply = <&d3_3v>; +- +- pinctrl-0 = <&lan89218_pins>; +- pinctrl-names = "default"; +- }; +- +- vga-encoder { +- compatible = "adi,adv7123"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7123_in: endpoint { +- remote-endpoint = <&du_out_rgb1>; +- }; +- }; +- port@1 { +- reg = <1>; +- adv7123_out: endpoint { +- remote-endpoint = <&vga_in>; +- }; +- }; +- }; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con: endpoint { +- remote-endpoint = <&adv7511_out>; +- }; +- }; +- }; +- +- vga { +- compatible = "vga-connector"; +- +- port { +- vga_in: endpoint { +- remote-endpoint = <&adv7123_out>; +- }; +- }; +- }; +- +- x1_clk: x1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <74250000>; +- }; +- +- x2_clk: x2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <65000000>; +- }; +- +- keyboard { +- compatible = "gpio-keys"; +- +- pinctrl-0 = <&keyboard_pins>; +- pinctrl-names = "default"; +- +- key-1 { +- linux,code = ; +- label = "SW2-1"; +- wakeup-source; +- debounce-interval = <20>; +- gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; +- }; +- key-2 { +- linux,code = ; +- label = "SW2-2"; +- wakeup-source; +- debounce-interval = <20>; +- gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; +- }; +- key-3 { +- linux,code = ; +- label = "SW2-3"; +- wakeup-source; +- debounce-interval = <20>; +- gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; +- }; +- key-4 { +- linux,code = ; +- label = "SW2-4"; +- wakeup-source; +- debounce-interval = <20>; +- gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; +- }; +- key-a { +- linux,code = ; +- label = "SW24"; +- wakeup-source; +- debounce-interval = <20>; +- gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; +- }; +- key-b { +- linux,code = ; +- label = "SW25"; +- wakeup-source; +- debounce-interval = <20>; +- gpios = <&gpio11 2 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led17 { +- gpios = <&gpio10 10 GPIO_ACTIVE_HIGH>; +- }; +- led18 { +- gpios = <&gpio10 11 GPIO_ACTIVE_HIGH>; +- }; +- led19 { +- gpios = <&gpio10 12 GPIO_ACTIVE_HIGH>; +- }; +- led20 { +- gpios = <&gpio10 23 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- vcc_sdhi0: regulator-vcc-sdhi0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI0 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&extal_clk { +- clock-frequency = <20000000>; +-}; +- +-&can_clk { +- clock-frequency = <48000000>; +-}; +- +-&pfc { +- scif0_pins: scif0 { +- groups = "scif0_data"; +- function = "scif0"; +- }; +- +- scif3_pins: scif3 { +- groups = "scif3_data"; +- function = "scif3"; +- }; +- +- lan89218_pins: lan89218 { +- intc { +- groups = "intc_irq0"; +- function = "intc"; +- }; +- lbsc { +- groups = "lbsc_ex_cs0"; +- function = "lbsc"; +- }; +- }; +- +- can0_pins: can0 { +- groups = "can0_data", "can_clk"; +- function = "can0"; +- }; +- +- sdhi0_pins: sdhi0 { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- }; +- +- du0_pins: du0 { +- groups = "du0_rgb888", "du0_sync", "du0_disp"; +- function = "du0"; +- }; +- +- du1_pins: du1 { +- groups = "du1_rgb666", "du1_sync", "du1_disp"; +- function = "du1"; +- }; +- +- keyboard_pins: keyboard { +- pins = "GP_3_10", "GP_3_11", "GP_3_12", "GP_3_15", "GP_11_02"; +- bias-pull-up; +- }; +- +- pmic_irq_pins: pmicirq { +- groups = "intc_irq2"; +- function = "intc"; +- }; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&scif0 { +- pinctrl-0 = <&scif0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scif3 { +- pinctrl-0 = <&scif3_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&can0 { +- pinctrl-0 = <&can0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <&vcc_sdhi0>; +- cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- hdmi@39 { +- compatible = "adi,adv7511w"; +- reg = <0x39>; +- interrupt-parent = <&irqc>; +- interrupts = <3 IRQ_TYPE_EDGE_FALLING>; +- +- adi,input-depth = <8>; +- adi,input-colorspace = "rgb"; +- adi,input-clock = "1x"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7511_in: endpoint { +- remote-endpoint = <&du_out_rgb0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- adv7511_out: endpoint { +- remote-endpoint = <&hdmi_con>; +- }; +- }; +- }; +- }; +-}; +- +-&iic3 { +- status = "okay"; +- +- pmic@58 { +- compatible = "dlg,da9063"; +- reg = <0x58>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_irq_pins>; +- interrupt-parent = <&irqc>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- +- rtc { +- compatible = "dlg,da9063-rtc"; +- }; +- +- wdt { +- compatible = "dlg,da9063-watchdog"; +- }; +- }; +-}; +- +-&du { +- pinctrl-0 = <&du0_pins>, <&du1_pins>; +- pinctrl-names = "default"; +- +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>; +- clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; +- status = "okay"; +- +- ports { +- port@0 { +- endpoint { +- remote-endpoint = <&adv7511_in>; +- }; +- }; +- port@1 { +- endpoint { +- remote-endpoint = <&adv7123_in>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7792-wheat.dts b/scripts/dtc/include-prefixes/arm/r8a7792-wheat.dts +deleted file mode 100644 +index 434e4655be9d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7792-wheat.dts ++++ /dev/null +@@ -1,329 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Wheat board +- * +- * Copyright (C) 2016 Renesas Electronics Corporation +- * Copyright (C) 2016 Cogent Embedded, Inc. +- */ +- +-/dts-v1/; +-#include "r8a7792.dtsi" +-#include +-#include +- +-/ { +- model = "Wheat"; +- compatible = "renesas,wheat", "renesas,r8a7792"; +- +- aliases { +- serial0 = &scif0; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x40000000>; +- }; +- +- d3_3v: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "D3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ethernet@18000000 { +- compatible = "smsc,lan89218", "smsc,lan9115"; +- reg = <0 0x18000000 0 0x100>; +- phy-mode = "mii"; +- interrupt-parent = <&irqc>; +- interrupts = <0 IRQ_TYPE_EDGE_FALLING>; +- smsc,irq-push-pull; +- smsc,save-mac-address; +- reg-io-width = <4>; +- vddvario-supply = <&d3_3v>; +- vdd33a-supply = <&d3_3v>; +- +- pinctrl-0 = <&lan89218_pins>; +- pinctrl-names = "default"; +- }; +- +- keyboard { +- compatible = "gpio-keys"; +- +- key-a { +- linux,code = ; +- label = "SW2"; +- wakeup-source; +- debounce-interval = <20>; +- gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; +- }; +- key-b { +- linux,code = ; +- label = "SW3"; +- wakeup-source; +- debounce-interval = <20>; +- gpios = <&gpio11 2 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- vcc_sdhi0: regulator-vcc-sdhi0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI0 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- hdmi-out0 { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con0: endpoint { +- remote-endpoint = <&adv7513_0_out>; +- }; +- }; +- }; +- +- hdmi-out1 { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con1: endpoint { +- remote-endpoint = <&adv7513_1_out>; +- }; +- }; +- }; +- +- osc2_clk: osc2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <74250000>; +- }; +-}; +- +-&extal_clk { +- clock-frequency = <20000000>; +-}; +- +-&pfc { +- scif0_pins: scif0 { +- groups = "scif0_data"; +- function = "scif0"; +- }; +- +- lan89218_pins: lan89218 { +- intc { +- groups = "intc_irq0"; +- function = "intc"; +- }; +- lbsc { +- groups = "lbsc_ex_cs0"; +- function = "lbsc"; +- }; +- }; +- +- can0_pins: can0 { +- groups = "can0_data"; +- function = "can0"; +- }; +- +- can1_pins: can1 { +- groups = "can1_data"; +- function = "can1"; +- }; +- +- sdhi0_pins: sdhi0 { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- }; +- +- qspi_pins: qspi { +- groups = "qspi_ctrl", "qspi_data4"; +- function = "qspi"; +- }; +- +- du0_pins: du0 { +- groups = "du0_rgb888", "du0_sync", "du0_disp"; +- function = "du0"; +- }; +- +- du1_pins: du1 { +- groups = "du1_rgb666", "du1_sync", "du1_disp"; +- function = "du1"; +- }; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&scif0 { +- pinctrl-0 = <&scif0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&can0 { +- pinctrl-0 = <&can0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-0 = <&can1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <&vcc_sdhi0>; +- cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&qspi { +- pinctrl-0 = <&qspi_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- flash@0 { +- compatible = "spansion,s25fl512s", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <30000000>; +- spi-tx-bus-width = <4>; +- spi-rx-bus-width = <4>; +- spi-cpol; +- spi-cpha; +- m25p,fast-read; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "loader"; +- reg = <0x00000000 0x00040000>; +- read-only; +- }; +- partition@40000 { +- label = "user"; +- reg = <0x00040000 0x00400000>; +- read-only; +- }; +- partition@440000 { +- label = "flash"; +- reg = <0x00440000 0x03bc0000>; +- }; +- }; +- }; +-}; +- +-&i2c4 { +- status = "okay"; +- clock-frequency = <400000>; +- +- /* +- * The adv75xx resets its addresses to defaults during low power mode. +- * Because we have two ADV7513 devices on the same bus, we must change +- * both of them away from the defaults so that they do not conflict. +- */ +- hdmi@3d { +- compatible = "adi,adv7513"; +- reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>; +- reg-names = "main", "edid", "cec", "packet"; +- +- adi,input-depth = <8>; +- adi,input-colorspace = "rgb"; +- adi,input-clock = "1x"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7513_0_in: endpoint { +- remote-endpoint = <&du_out_rgb0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- adv7513_0_out: endpoint { +- remote-endpoint = <&hdmi_con0>; +- }; +- }; +- }; +- }; +- +- hdmi@39 { +- compatible = "adi,adv7513"; +- reg = <0x39>, <0x49>, <0x29>, <0x59>; +- reg-names = "main", "edid", "cec", "packet"; +- +- adi,input-depth = <8>; +- adi,input-colorspace = "rgb"; +- adi,input-clock = "1x"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7513_1_in: endpoint { +- remote-endpoint = <&du_out_rgb1>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- adv7513_1_out: endpoint { +- remote-endpoint = <&hdmi_con1>; +- }; +- }; +- }; +- }; +-}; +- +-&du { +- pinctrl-0 = <&du0_pins>, <&du1_pins>; +- pinctrl-names = "default"; +- +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&osc2_clk>; +- clock-names = "du.0", "du.1", "dclkin.0"; +- status = "okay"; +- +- ports { +- port@0 { +- endpoint { +- remote-endpoint = <&adv7513_0_in>; +- }; +- }; +- port@1 { +- endpoint { +- remote-endpoint = <&adv7513_1_in>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7792.dtsi b/scripts/dtc/include-prefixes/arm/r8a7792.dtsi +deleted file mode 100644 +index 9cdb73894ac2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7792.dtsi ++++ /dev/null +@@ -1,927 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Car V2H (R8A77920) SoC +- * +- * Copyright (C) 2016 Cogent Embedded Inc. +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r8a7792"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &iic3; +- spi0 = &qspi; +- spi1 = &msiof0; +- spi2 = &msiof1; +- vin0 = &vin0; +- vin1 = &vin1; +- vin2 = &vin2; +- vin3 = &vin3; +- vin4 = &vin4; +- vin5 = &vin5; +- }; +- +- /* External CAN clock */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0>; +- clock-frequency = <1000000000>; +- clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; +- power-domains = <&sysc R8A7792_PD_CA15_CPU0>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA15>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <1>; +- clock-frequency = <1000000000>; +- clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; +- power-domains = <&sysc R8A7792_PD_CA15_CPU1>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA15>; +- }; +- +- L2_CA15: cache-controller-0 { +- compatible = "cache"; +- cache-unified; +- cache-level = <2>; +- power-domains = <&sysc R8A7792_PD_CA15_SCU>; +- }; +- }; +- +- /* External root clock */ +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- pmu { +- compatible = "arm,cortex-a15-pmu"; +- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- /* External SCIF clock */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a7792-wdt", +- "renesas,rcar-gen2-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a7792", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 29>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a7792", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 23>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a7792", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a7792", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 28>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a7792", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 17>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a7792", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 17>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- gpio6: gpio@e6055100 { +- compatible = "renesas,gpio-r8a7792", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055100 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 192 17>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 905>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 905>; +- }; +- +- gpio7: gpio@e6055200 { +- compatible = "renesas,gpio-r8a7792", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055200 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 224 17>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 904>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 904>; +- }; +- +- gpio8: gpio@e6055300 { +- compatible = "renesas,gpio-r8a7792", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055300 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 256 17>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 921>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 921>; +- }; +- +- gpio9: gpio@e6055400 { +- compatible = "renesas,gpio-r8a7792", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055400 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 288 17>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 919>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 919>; +- }; +- +- gpio10: gpio@e6055500 { +- compatible = "renesas,gpio-r8a7792", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055500 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 320 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 914>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 914>; +- }; +- +- gpio11: gpio@e6055600 { +- compatible = "renesas,gpio-r8a7792", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055600 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 352 30>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 913>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 913>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a7792"; +- reg = <0 0xe6060000 0 0x144>; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a7792-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>; +- clock-names = "extal"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- apmu@e6152000 { +- compatible = "renesas,r8a7792-apmu", "renesas,apmu"; +- reg = <0 0xe6152000 0 0x188>; +- cpus = <&cpu0>, <&cpu1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a7792-rst"; +- reg = <0 0xe6160000 0 0x0100>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a7792-sysc"; +- reg = <0 0xe6180000 0 0x0200>; +- #power-domain-cells = <1>; +- }; +- +- irqc: interrupt-controller@e61c0000 { +- compatible = "renesas,irqc-r8a7792", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- icram0: sram@e63a0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63a0000 0 0x12000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63a0000 0x12000>; +- }; +- +- icram1: sram@e63c0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63c0000 0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63c0000 0x1000>; +- +- smp-sram@0 { +- compatible = "renesas,smp-sram"; +- reg = <0 0x100>; +- }; +- }; +- +- /* I2C doesn't need pinmux */ +- i2c0: i2c@e6508000 { +- compatible = "renesas,i2c-r8a7792", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- i2c-scl-internal-delay-ns = <6>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6518000 { +- compatible = "renesas,i2c-r8a7792", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6518000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- i2c-scl-internal-delay-ns = <6>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6530000 { +- compatible = "renesas,i2c-r8a7792", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6530000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- i2c-scl-internal-delay-ns = <6>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e6540000 { +- compatible = "renesas,i2c-r8a7792", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6540000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- i2c-scl-internal-delay-ns = <6>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e6520000 { +- compatible = "renesas,i2c-r8a7792", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6520000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 927>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 927>; +- i2c-scl-internal-delay-ns = <6>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c5: i2c@e6528000 { +- compatible = "renesas,i2c-r8a7792", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6528000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 925>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 925>; +- i2c-scl-internal-delay-ns = <110>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- iic3: i2c@e60b0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7792", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe60b0000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 926>; +- dmas = <&dmac0 0x77>, <&dmac0 0x78>, +- <&dmac1 0x77>, <&dmac1 0x78>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 926>; +- status = "disabled"; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a7792", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- dmac1: dma-controller@e6720000 { +- compatible = "renesas,dmac-r8a7792", +- "renesas,rcar-dmac"; +- reg = <0 0xe6720000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a7792", +- "renesas,etheravb-rcar-gen2"; +- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- qspi: spi@e6b10000 { +- compatible = "renesas,qspi-r8a7792", "renesas,qspi"; +- reg = <0 0xe6b10000 0 0x2c>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 917>; +- dmas = <&dmac0 0x17>, <&dmac0 0x18>, +- <&dmac1 0x17>, <&dmac1 0x18>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 917>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a7792", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e60000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 721>, +- <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x29>, <&dmac0 0x2a>, +- <&dmac1 0x29>, <&dmac1 0x2a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 721>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a7792", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e68000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 720>, +- <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, +- <&dmac1 0x2d>, <&dmac1 0x2e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 720>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e58000 { +- compatible = "renesas,scif-r8a7792", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e58000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 719>, +- <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, +- <&dmac1 0x2b>, <&dmac1 0x2c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 719>; +- status = "disabled"; +- }; +- +- scif3: serial@e6ea8000 { +- compatible = "renesas,scif-r8a7792", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ea8000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 718>, +- <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2f>, <&dmac0 0x30>, +- <&dmac1 0x2f>, <&dmac1 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 718>; +- status = "disabled"; +- }; +- +- hscif0: serial@e62c0000 { +- compatible = "renesas,hscif-r8a7792", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c0000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 717>, +- <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x39>, <&dmac0 0x3a>, +- <&dmac1 0x39>, <&dmac1 0x3a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 717>; +- status = "disabled"; +- }; +- +- hscif1: serial@e62c8000 { +- compatible = "renesas,hscif-r8a7792", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c8000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>, +- <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, +- <&dmac1 0x4d>, <&dmac1 0x4e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e20000 { +- compatible = "renesas,msiof-r8a7792", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e20000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 000>; +- dmas = <&dmac0 0x51>, <&dmac0 0x52>, +- <&dmac1 0x51>, <&dmac1 0x52>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6e10000 { +- compatible = "renesas,msiof-r8a7792", +- "renesas,rcar-gen2-msiof"; +- reg = <0 0xe6e10000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 208>; +- dmas = <&dmac0 0x55>, <&dmac0 0x56>, +- <&dmac1 0x55>, <&dmac1 0x56>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 208>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- can0: can@e6e80000 { +- compatible = "renesas,can-r8a7792", +- "renesas,rcar-gen2-can"; +- reg = <0 0xe6e80000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>, +- <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- status = "disabled"; +- }; +- +- can1: can@e6e88000 { +- compatible = "renesas,can-r8a7792", +- "renesas,rcar-gen2-can"; +- reg = <0 0xe6e88000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>, +- <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- status = "disabled"; +- }; +- +- vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a7792", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef0000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 811>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 811>; +- status = "disabled"; +- }; +- +- vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a7792", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef1000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 810>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 810>; +- status = "disabled"; +- }; +- +- vin2: video@e6ef2000 { +- compatible = "renesas,vin-r8a7792", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef2000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 809>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 809>; +- status = "disabled"; +- }; +- +- vin3: video@e6ef3000 { +- compatible = "renesas,vin-r8a7792", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef3000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 808>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 808>; +- status = "disabled"; +- }; +- +- vin4: video@e6ef4000 { +- compatible = "renesas,vin-r8a7792", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef4000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 805>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 805>; +- status = "disabled"; +- }; +- +- vin5: video@e6ef5000 { +- compatible = "renesas,vin-r8a7792", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef5000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 804>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 804>; +- status = "disabled"; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a7792", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee100000 0 0x328>; +- interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; +- dmas = <&dmac0 0xcd>, <&dmac0 0xce>, +- <&dmac1 0xcd>, <&dmac1 0xce>; +- dma-names = "tx", "rx", "tx", "rx"; +- clocks = <&cpg CPG_MOD 314>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1001000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0 0xf1001000 0 0x1000>, +- <0 0xf1002000 0 0x2000>, +- <0 0xf1004000 0 0x2000>, +- <0 0xf1006000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- vsp@fe928000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe928000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 131>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 131>; +- }; +- +- vsp@fe930000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe930000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 128>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 128>; +- }; +- +- vsp@fe938000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe938000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 127>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 127>; +- }; +- +- jpu: jpeg-codec@fe980000 { +- compatible = "renesas,jpu-r8a7792", +- "renesas,rcar-gen2-jpu"; +- reg = <0 0xfe980000 0 0x10300>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 106>; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 106>; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a7792"; +- reg = <0 0xfeb00000 0 0x40000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; +- clock-names = "du.0", "du.1"; +- resets = <&cpg 724>; +- reset-names = "du.0"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb0: endpoint { +- }; +- }; +- port@1 { +- reg = <1>; +- du_out_rgb1: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@ff000044 { +- compatible = "renesas,prr"; +- reg = <0 0xff000044 0 4>; +- }; +- +- cmt0: timer@ffca0000 { +- compatible = "renesas,r8a7792-cmt0", +- "renesas,rcar-gen2-cmt0"; +- reg = <0 0xffca0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a7792-cmt1", +- "renesas,rcar-gen2-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 329>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; +- resets = <&cpg 329>; +- +- status = "disabled"; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7793-gose.dts b/scripts/dtc/include-prefixes/arm/r8a7793-gose.dts +deleted file mode 100644 +index 479e0fdf0c37..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7793-gose.dts ++++ /dev/null +@@ -1,816 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Gose board +- * +- * Copyright (C) 2014-2015 Renesas Electronics Corporation +- */ +- +-/* +- * SSI-AK4643 +- * +- * SW1: 1: AK4643 +- * 2: CN22 +- * 3: ADV7511 +- * +- * This command is required when Playback/Capture +- * +- * amixer set "LINEOUT Mixer DACL" on +- * amixer set "DVC Out" 100% +- * amixer set "DVC In" 100% +- * +- * You can use Mute +- * +- * amixer set "DVC Out Mute" on +- * amixer set "DVC In Mute" on +- * +- * You can use Volume Ramp +- * +- * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" +- * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" +- * amixer set "DVC Out Ramp" on +- * aplay xxx.wav & +- * amixer set "DVC Out" 80% // Volume Down +- * amixer set "DVC Out" 100% // Volume Up +- */ +- +-/dts-v1/; +-#include "r8a7793.dtsi" +-#include +-#include +- +-/ { +- model = "Gose"; +- compatible = "renesas,gose", "renesas,r8a7793"; +- +- aliases { +- serial0 = &scif0; +- serial1 = &scif1; +- i2c9 = &gpioi2c2; +- i2c10 = &gpioi2c4; +- i2c11 = &i2chdmi; +- i2c12 = &i2cexio4; +- mmc0 = &sdhi0; +- mmc1 = &sdhi1; +- mmc2 = &sdhi2; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x40000000>; +- }; +- +- keyboard { +- compatible = "gpio-keys"; +- +- pinctrl-0 = <&keyboard_pins>; +- pinctrl-names = "default"; +- +- key-1 { +- gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW2-1"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-2 { +- gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW2-2"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-3 { +- gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW2-3"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-4 { +- gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW2-4"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-a { +- gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW30"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-b { +- gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW31"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-c { +- gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW32"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-d { +- gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW33"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-e { +- gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW34"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-f { +- gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW35"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-g { +- gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW36"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led6 { +- gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- label = "LED6"; +- }; +- led7 { +- gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; +- label = "LED7"; +- }; +- led8 { +- gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; +- label = "LED8"; +- }; +- }; +- +- vcc_sdhi0: regulator-vcc-sdhi0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI0 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhi0: regulator-vccq-sdhi0 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI0 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- vcc_sdhi1: regulator-vcc-sdhi1 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI1 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhi1: regulator-vccq-sdhi1 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI1 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- vcc_sdhi2: regulator-vcc-sdhi2 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI2 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhi2: regulator-vccq-sdhi2 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI2 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- audio_clock: audio_clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <11289600>; +- }; +- +- rsnd_ak4643: sound { +- compatible = "simple-audio-card"; +- +- simple-audio-card,format = "left_j"; +- simple-audio-card,bitclock-master = <&sndcodec>; +- simple-audio-card,frame-master = <&sndcodec>; +- +- sndcpu: simple-audio-card,cpu { +- sound-dai = <&rcar_sound>; +- }; +- +- sndcodec: simple-audio-card,codec { +- sound-dai = <&ak4643>; +- clocks = <&audio_clock>; +- }; +- }; +- +- hdmi-in { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&adv7612_in>; +- }; +- }; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_out: endpoint { +- remote-endpoint = <&adv7511_out>; +- }; +- }; +- }; +- +- composite-in { +- compatible = "composite-video-connector"; +- +- port { +- composite_con_in: endpoint { +- remote-endpoint = <&adv7180_in>; +- }; +- }; +- }; +- +- x2_clk: x2-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <74250000>; +- }; +- +- x13_clk: x13-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <148500000>; +- }; +- +- gpioi2c2: i2c-9 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "i2c-gpio"; +- status = "disabled"; +- scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <5>; +- }; +- +- gpioi2c4: i2c-10 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "i2c-gpio"; +- status = "disabled"; +- scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <5>; +- }; +- +- /* +- * A fallback to GPIO is provided for I2C2. +- */ +- i2chdmi: i2c-11 { +- compatible = "i2c-demux-pinctrl"; +- i2c-parent = <&i2c2>, <&gpioi2c2>; +- i2c-bus-name = "i2c-hdmi"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ak4643: codec@12 { +- compatible = "asahi-kasei,ak4643"; +- #sound-dai-cells = <0>; +- reg = <0x12>; +- }; +- +- composite-in@20 { +- compatible = "adi,adv7180cp"; +- reg = <0x20>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7180_in: endpoint { +- remote-endpoint = <&composite_con_in>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- adv7180_out: endpoint { +- bus-width = <8>; +- remote-endpoint = <&vin1ep>; +- }; +- }; +- }; +- }; +- +- hdmi@39 { +- compatible = "adi,adv7511w"; +- reg = <0x39>; +- interrupt-parent = <&gpio3>; +- interrupts = <29 IRQ_TYPE_LEVEL_LOW>; +- +- adi,input-depth = <8>; +- adi,input-colorspace = "rgb"; +- adi,input-clock = "1x"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7511_in: endpoint { +- remote-endpoint = <&du_out_rgb>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- adv7511_out: endpoint { +- remote-endpoint = <&hdmi_con_out>; +- }; +- }; +- }; +- }; +- +- hdmi-in@4c { +- compatible = "adi,adv7612"; +- reg = <0x4c>; +- interrupt-parent = <&gpio4>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- default-input = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7612_in: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- adv7612_out: endpoint { +- remote-endpoint = <&vin0ep2>; +- }; +- }; +- }; +- }; +- +- eeprom@50 { +- compatible = "renesas,r1ex24002", "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- }; +- +- /* +- * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA). +- * A fallback to GPIO is provided. +- */ +- i2cexio4: i2c-12 { +- compatible = "i2c-demux-pinctrl"; +- i2c-parent = <&i2c4>, <&gpioi2c4>; +- i2c-bus-name = "i2c-exio4"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +- +-&du { +- pinctrl-0 = <&du_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, +- <&x13_clk>, <&x2_clk>; +- clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; +- +- ports { +- port@0 { +- endpoint { +- remote-endpoint = <&adv7511_in>; +- }; +- }; +- }; +-}; +- +-&lvds0 { +- ports { +- port@1 { +- lvds_connector: endpoint { +- }; +- }; +- }; +-}; +- +-&extal_clk { +- clock-frequency = <20000000>; +-}; +- +-&pfc { +- pinctrl-0 = <&scif_clk_pins>; +- pinctrl-names = "default"; +- +- i2c2_pins: i2c2 { +- groups = "i2c2"; +- function = "i2c2"; +- }; +- +- i2c4_pins: i2c4 { +- groups = "i2c4_c"; +- function = "i2c4"; +- }; +- +- du_pins: du { +- groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; +- function = "du"; +- }; +- +- scif0_pins: scif0 { +- groups = "scif0_data_d"; +- function = "scif0"; +- }; +- +- scif1_pins: scif1 { +- groups = "scif1_data_d"; +- function = "scif1"; +- }; +- +- scif_clk_pins: scif_clk { +- groups = "scif_clk"; +- function = "scif_clk"; +- }; +- +- ether_pins: ether { +- groups = "eth_link", "eth_mdio", "eth_rmii"; +- function = "eth"; +- }; +- +- phy1_pins: phy1 { +- groups = "intc_irq0"; +- function = "intc"; +- }; +- +- pmic_irq_pins: pmicirq { +- groups = "intc_irq2"; +- function = "intc"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <3300>; +- }; +- +- sdhi0_pins_uhs: sd0_uhs { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <1800>; +- }; +- +- sdhi1_pins: sd1 { +- groups = "sdhi1_data4", "sdhi1_ctrl"; +- function = "sdhi1"; +- power-source = <3300>; +- }; +- +- sdhi1_pins_uhs: sd1_uhs { +- groups = "sdhi1_data4", "sdhi1_ctrl"; +- function = "sdhi1"; +- power-source = <1800>; +- }; +- +- sdhi2_pins: sd2 { +- groups = "sdhi2_data4", "sdhi2_ctrl"; +- function = "sdhi2"; +- power-source = <3300>; +- }; +- +- sdhi2_pins_uhs: sd2_uhs { +- groups = "sdhi2_data4", "sdhi2_ctrl"; +- function = "sdhi2"; +- power-source = <1800>; +- }; +- +- qspi_pins: qspi { +- groups = "qspi_ctrl", "qspi_data4"; +- function = "qspi"; +- }; +- +- sound_pins: sound { +- groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; +- function = "ssi"; +- }; +- +- sound_clk_pins: sound_clk { +- groups = "audio_clk_a"; +- function = "audio_clk"; +- }; +- +- keyboard_pins: keyboard { +- pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3"; +- bias-pull-up; +- }; +- +- vin0_pins: vin0 { +- groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; +- function = "vin0"; +- }; +- +- vin1_pins: vin1 { +- groups = "vin1_data8", "vin1_clk"; +- function = "vin1"; +- }; +-}; +- +-ðer { +- pinctrl-0 = <ðer_pins>, <&phy1_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <&phy1>; +- renesas,ether-link-active-low; +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- interrupt-parent = <&irqc0>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- micrel,led-mode = <1>; +- reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&cmt0 { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu0-supply = <&vdd_dvfs>; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&scif0 { +- pinctrl-0 = <&scif0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scif1 { +- pinctrl-0 = <&scif1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scif_clk { +- clock-frequency = <14745600>; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-1 = <&sdhi0_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <&vcc_sdhi0>; +- vqmmc-supply = <&vccq_sdhi0>; +- cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- status = "okay"; +-}; +- +-&sdhi1 { +- pinctrl-0 = <&sdhi1_pins>; +- pinctrl-1 = <&sdhi1_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <&vcc_sdhi1>; +- vqmmc-supply = <&vccq_sdhi1>; +- cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; +- sd-uhs-sdr50; +- status = "okay"; +-}; +- +-&sdhi2 { +- pinctrl-0 = <&sdhi2_pins>; +- pinctrl-1 = <&sdhi2_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <&vcc_sdhi2>; +- vqmmc-supply = <&vccq_sdhi2>; +- cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; +- sd-uhs-sdr50; +- status = "okay"; +-}; +- +-&qspi { +- pinctrl-0 = <&qspi_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- flash@0 { +- compatible = "spansion,s25fl512s", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <30000000>; +- spi-tx-bus-width = <4>; +- spi-rx-bus-width = <4>; +- spi-cpol; +- spi-cpha; +- m25p,fast-read; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "loader"; +- reg = <0x00000000 0x00040000>; +- read-only; +- }; +- partition@40000 { +- label = "user"; +- reg = <0x00040000 0x00400000>; +- read-only; +- }; +- partition@440000 { +- label = "flash"; +- reg = <0x00440000 0x03bc0000>; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-0 = <&i2c2_pins>; +- pinctrl-names = "i2c-hdmi"; +- +- status = "okay"; +- clock-frequency = <100000>; +- +-}; +- +-&i2c6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_irq_pins>; +- status = "okay"; +- clock-frequency = <100000>; +- +- pmic@58 { +- compatible = "dlg,da9063"; +- reg = <0x58>; +- interrupt-parent = <&irqc0>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- +- rtc { +- compatible = "dlg,da9063-rtc"; +- }; +- +- wdt { +- compatible = "dlg,da9063-watchdog"; +- }; +- }; +- +- vdd_dvfs: regulator@68 { +- compatible = "dlg,da9210"; +- reg = <0x68>; +- interrupt-parent = <&irqc0>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&i2c4 { +- pinctrl-0 = <&i2c4_pins>; +- pinctrl-names = "i2c-exio4"; +-}; +- +-&rcar_sound { +- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; +- pinctrl-names = "default"; +- +- /* Single DAI */ +- #sound-dai-cells = <0>; +- +- status = "okay"; +- +- rcar_sound,dai { +- dai0 { +- playback = <&ssi0>, <&src2>, <&dvc0>; +- capture = <&ssi1>, <&src3>, <&dvc1>; +- }; +- }; +-}; +- +-&ssi1 { +- shared-pin; +-}; +- +-/* HDMI video input */ +-&vin0 { +- status = "okay"; +- pinctrl-0 = <&vin0_pins>; +- pinctrl-names = "default"; +- +- port { +- vin0ep2: endpoint { +- remote-endpoint = <&adv7612_out>; +- bus-width = <24>; +- hsync-active = <0>; +- vsync-active = <0>; +- pclk-sample = <1>; +- data-active = <1>; +- }; +- }; +-}; +- +-/* composite video input */ +-&vin1 { +- pinctrl-0 = <&vin1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- port { +- vin1ep: endpoint { +- remote-endpoint = <&adv7180_out>; +- bus-width = <8>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7793.dtsi b/scripts/dtc/include-prefixes/arm/r8a7793.dtsi +deleted file mode 100644 +index dea4b1e108af..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7793.dtsi ++++ /dev/null +@@ -1,1469 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Car M2-N (R8A77930) SoC +- * +- * Copyright (C) 2014-2015 Renesas Electronics Corporation +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r8a7793"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c7; +- i2c8 = &i2c8; +- spi0 = &qspi; +- }; +- +- /* +- * The external audio clocks are configured as 0 Hz fixed frequency +- * clocks by default. +- * Boards that provide audio clocks should override them. +- */ +- audio_clk_a: audio_clk_a { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- audio_clk_b: audio_clk_b { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- audio_clk_c: audio_clk_c { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* External CAN clock */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0>; +- clock-frequency = <1500000000>; +- clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; +- power-domains = <&sysc R8A7793_PD_CA15_CPU0>; +- enable-method = "renesas,apmu"; +- voltage-tolerance = <1>; /* 1% */ +- clock-latency = <300000>; /* 300 us */ +- +- /* kHz - uV - OPPs unknown yet */ +- operating-points = <1500000 1000000>, +- <1312500 1000000>, +- <1125000 1000000>, +- < 937500 1000000>, +- < 750000 1000000>, +- < 375000 1000000>; +- next-level-cache = <&L2_CA15>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <1>; +- clock-frequency = <1500000000>; +- clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; +- power-domains = <&sysc R8A7793_PD_CA15_CPU1>; +- enable-method = "renesas,apmu"; +- voltage-tolerance = <1>; /* 1% */ +- clock-latency = <300000>; /* 300 us */ +- +- /* kHz - uV - OPPs unknown yet */ +- operating-points = <1500000 1000000>, +- <1312500 1000000>, +- <1125000 1000000>, +- < 937500 1000000>, +- < 750000 1000000>, +- < 375000 1000000>; +- next-level-cache = <&L2_CA15>; +- }; +- +- L2_CA15: cache-controller-0 { +- compatible = "cache"; +- power-domains = <&sysc R8A7793_PD_CA15_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- }; +- +- /* External root clock */ +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- pmu { +- compatible = "arm,cortex-a15-pmu"; +- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- /* External SCIF clock */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a7793-wdt", +- "renesas,rcar-gen2-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a7793", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a7793", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a7793", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a7793", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a7793", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a7793", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- gpio6: gpio@e6055400 { +- compatible = "renesas,gpio-r8a7793", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055400 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 192 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 905>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 905>; +- }; +- +- gpio7: gpio@e6055800 { +- compatible = "renesas,gpio-r8a7793", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055800 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 224 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 904>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 904>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a7793"; +- reg = <0 0xe6060000 0 0x250>; +- }; +- +- /* Special CPG clocks */ +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a7793-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>, <&usb_extal_clk>; +- clock-names = "extal", "usb_extal"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- apmu@e6152000 { +- compatible = "renesas,r8a7793-apmu", "renesas,apmu"; +- reg = <0 0xe6152000 0 0x188>; +- cpus = <&cpu0>, <&cpu1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a7793-rst"; +- reg = <0 0xe6160000 0 0x0100>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a7793-sysc"; +- reg = <0 0xe6180000 0 0x0200>; +- #power-domain-cells = <1>; +- }; +- +- irqc0: interrupt-controller@e61c0000 { +- compatible = "renesas,irqc-r8a7793", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- thermal: thermal@e61f0000 { +- compatible = "renesas,thermal-r8a7793", +- "renesas,rcar-gen2-thermal", +- "renesas,rcar-thermal"; +- reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 522>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 522>; +- #thermal-sensor-cells = <0>; +- }; +- +- ipmmu_sy0: iommu@e6280000 { +- compatible = "renesas,ipmmu-r8a7793", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6280000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_sy1: iommu@e6290000 { +- compatible = "renesas,ipmmu-r8a7793", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6290000 0 0x1000>; +- interrupts = ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_ds: iommu@e6740000 { +- compatible = "renesas,ipmmu-r8a7793", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6740000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_mp: iommu@ec680000 { +- compatible = "renesas,ipmmu-r8a7793", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xec680000 0 0x1000>; +- interrupts = ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_mx: iommu@fe951000 { +- compatible = "renesas,ipmmu-r8a7793", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xfe951000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_rt: iommu@ffc80000 { +- compatible = "renesas,ipmmu-r8a7793", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xffc80000 0 0x1000>; +- interrupts = ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_gp: iommu@e62a0000 { +- compatible = "renesas,ipmmu-r8a7793", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe62a0000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- icram0: sram@e63a0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63a0000 0 0x12000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63a0000 0x12000>; +- }; +- +- icram1: sram@e63c0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63c0000 0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63c0000 0x1000>; +- +- smp-sram@0 { +- compatible = "renesas,smp-sram"; +- reg = <0 0x100>; +- }; +- }; +- +- /* The memory map in the User's Manual maps the cores to +- * bus numbers +- */ +- i2c0: i2c@e6508000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7793", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6518000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7793", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6518000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6530000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7793", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6530000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e6540000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7793", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6540000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e6520000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7793", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6520000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 927>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 927>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c5: i2c@e6528000 { +- /* doesn't need pinmux */ +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7793", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6528000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 925>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 925>; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c6: i2c@e60b0000 { +- /* doesn't need pinmux */ +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7793", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe60b0000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 926>; +- dmas = <&dmac0 0x77>, <&dmac0 0x78>, +- <&dmac1 0x77>, <&dmac1 0x78>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 926>; +- status = "disabled"; +- }; +- +- i2c7: i2c@e6500000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7793", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe6500000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 318>; +- dmas = <&dmac0 0x61>, <&dmac0 0x62>, +- <&dmac1 0x61>, <&dmac1 0x62>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 318>; +- status = "disabled"; +- }; +- +- i2c8: i2c@e6510000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7793", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe6510000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 323>; +- dmas = <&dmac0 0x65>, <&dmac0 0x66>, +- <&dmac1 0x65>, <&dmac1 0x66>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 323>; +- status = "disabled"; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a7793", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- dmac1: dma-controller@e6720000 { +- compatible = "renesas,dmac-r8a7793", +- "renesas,rcar-dmac"; +- reg = <0 0xe6720000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- qspi: spi@e6b10000 { +- compatible = "renesas,qspi-r8a7793", "renesas,qspi"; +- reg = <0 0xe6b10000 0 0x2c>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 917>; +- dmas = <&dmac0 0x17>, <&dmac0 0x18>, +- <&dmac1 0x17>, <&dmac1 0x18>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 917>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- scifa0: serial@e6c40000 { +- compatible = "renesas,scifa-r8a7793", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c40000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>; +- clock-names = "fck"; +- dmas = <&dmac0 0x21>, <&dmac0 0x22>, +- <&dmac1 0x21>, <&dmac1 0x22>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scifa1: serial@e6c50000 { +- compatible = "renesas,scifa-r8a7793", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c50000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>; +- clock-names = "fck"; +- dmas = <&dmac0 0x25>, <&dmac0 0x26>, +- <&dmac1 0x25>, <&dmac1 0x26>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- scifa2: serial@e6c60000 { +- compatible = "renesas,scifa-r8a7793", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c60000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 202>; +- clock-names = "fck"; +- dmas = <&dmac0 0x27>, <&dmac0 0x28>, +- <&dmac1 0x27>, <&dmac1 0x28>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 202>; +- status = "disabled"; +- }; +- +- scifa3: serial@e6c70000 { +- compatible = "renesas,scifa-r8a7793", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c70000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1106>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, +- <&dmac1 0x1b>, <&dmac1 0x1c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 1106>; +- status = "disabled"; +- }; +- +- scifa4: serial@e6c78000 { +- compatible = "renesas,scifa-r8a7793", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c78000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1107>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1f>, <&dmac0 0x20>, +- <&dmac1 0x1f>, <&dmac1 0x20>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 1107>; +- status = "disabled"; +- }; +- +- scifa5: serial@e6c80000 { +- compatible = "renesas,scifa-r8a7793", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c80000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1108>; +- clock-names = "fck"; +- dmas = <&dmac0 0x23>, <&dmac0 0x24>, +- <&dmac1 0x23>, <&dmac1 0x24>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 1108>; +- status = "disabled"; +- }; +- +- scifb0: serial@e6c20000 { +- compatible = "renesas,scifb-r8a7793", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6c20000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>; +- clock-names = "fck"; +- dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, +- <&dmac1 0x3d>, <&dmac1 0x3e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scifb1: serial@e6c30000 { +- compatible = "renesas,scifb-r8a7793", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6c30000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>; +- clock-names = "fck"; +- dmas = <&dmac0 0x19>, <&dmac0 0x1a>, +- <&dmac1 0x19>, <&dmac1 0x1a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scifb2: serial@e6ce0000 { +- compatible = "renesas,scifb-r8a7793", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6ce0000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 216>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, +- <&dmac1 0x1d>, <&dmac1 0x1e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 216>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a7793", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e60000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x29>, <&dmac0 0x2a>, +- <&dmac1 0x29>, <&dmac1 0x2a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 721>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a7793", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e68000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, +- <&dmac1 0x2d>, <&dmac1 0x2e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 720>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e58000 { +- compatible = "renesas,scif-r8a7793", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e58000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, +- <&dmac1 0x2b>, <&dmac1 0x2c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 719>; +- status = "disabled"; +- }; +- +- scif3: serial@e6ea8000 { +- compatible = "renesas,scif-r8a7793", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ea8000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2f>, <&dmac0 0x30>, +- <&dmac1 0x2f>, <&dmac1 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 718>; +- status = "disabled"; +- }; +- +- scif4: serial@e6ee0000 { +- compatible = "renesas,scif-r8a7793", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ee0000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, +- <&dmac1 0xfb>, <&dmac1 0xfc>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 715>; +- status = "disabled"; +- }; +- +- scif5: serial@e6ee8000 { +- compatible = "renesas,scif-r8a7793", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ee8000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, +- <&dmac1 0xfd>, <&dmac1 0xfe>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 714>; +- status = "disabled"; +- }; +- +- hscif0: serial@e62c0000 { +- compatible = "renesas,hscif-r8a7793", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c0000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x39>, <&dmac0 0x3a>, +- <&dmac1 0x39>, <&dmac1 0x3a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 717>; +- status = "disabled"; +- }; +- +- hscif1: serial@e62c8000 { +- compatible = "renesas,hscif-r8a7793", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c8000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, +- <&dmac1 0x4d>, <&dmac1 0x4e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- }; +- +- hscif2: serial@e62d0000 { +- compatible = "renesas,hscif-r8a7793", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62d0000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, +- <&dmac1 0x3b>, <&dmac1 0x3c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 713>; +- status = "disabled"; +- }; +- +- can0: can@e6e80000 { +- compatible = "renesas,can-r8a7793", +- "renesas,rcar-gen2-can"; +- reg = <0 0xe6e80000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- status = "disabled"; +- }; +- +- can1: can@e6e88000 { +- compatible = "renesas,can-r8a7793", +- "renesas,rcar-gen2-can"; +- reg = <0 0xe6e88000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- status = "disabled"; +- }; +- +- vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a7793", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef0000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 811>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 811>; +- status = "disabled"; +- }; +- +- vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a7793", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef1000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 810>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 810>; +- status = "disabled"; +- }; +- +- vin2: video@e6ef2000 { +- compatible = "renesas,vin-r8a7793", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef2000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 809>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 809>; +- status = "disabled"; +- }; +- +- rcar_sound: sound@ec500000 { +- /* +- * #sound-dai-cells is required +- * +- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; +- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; +- */ +- compatible = "renesas,rcar_sound-r8a7793", +- "renesas,rcar_sound-gen2"; +- reg = <0 0xec500000 0 0x1000>, /* SCU */ +- <0 0xec5a0000 0 0x100>, /* ADG */ +- <0 0xec540000 0 0x1000>, /* SSIU */ +- <0 0xec541000 0 0x280>, /* SSI */ +- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ +- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; +- +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, +- <&cpg CPG_CORE R8A7793_CLK_M2>; +- clock-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0", +- "src.9", "src.8", "src.7", "src.6", +- "src.5", "src.4", "src.3", "src.2", +- "src.1", "src.0", +- "dvc.0", "dvc.1", +- "clk_a", "clk_b", "clk_c", "clk_i"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 1005>, +- <&cpg 1006>, <&cpg 1007>, +- <&cpg 1008>, <&cpg 1009>, +- <&cpg 1010>, <&cpg 1011>, +- <&cpg 1012>, <&cpg 1013>, +- <&cpg 1014>, <&cpg 1015>; +- reset-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0"; +- +- status = "disabled"; +- +- rcar_sound,dvc { +- dvc0: dvc-0 { +- dmas = <&audma1 0xbc>; +- dma-names = "tx"; +- }; +- dvc1: dvc-1 { +- dmas = <&audma1 0xbe>; +- dma-names = "tx"; +- }; +- }; +- +- rcar_sound,src { +- src0: src-0 { +- interrupts = ; +- dmas = <&audma0 0x85>, <&audma1 0x9a>; +- dma-names = "rx", "tx"; +- }; +- src1: src-1 { +- interrupts = ; +- dmas = <&audma0 0x87>, <&audma1 0x9c>; +- dma-names = "rx", "tx"; +- }; +- src2: src-2 { +- interrupts = ; +- dmas = <&audma0 0x89>, <&audma1 0x9e>; +- dma-names = "rx", "tx"; +- }; +- src3: src-3 { +- interrupts = ; +- dmas = <&audma0 0x8b>, <&audma1 0xa0>; +- dma-names = "rx", "tx"; +- }; +- src4: src-4 { +- interrupts = ; +- dmas = <&audma0 0x8d>, <&audma1 0xb0>; +- dma-names = "rx", "tx"; +- }; +- src5: src-5 { +- interrupts = ; +- dmas = <&audma0 0x8f>, <&audma1 0xb2>; +- dma-names = "rx", "tx"; +- }; +- src6: src-6 { +- interrupts = ; +- dmas = <&audma0 0x91>, <&audma1 0xb4>; +- dma-names = "rx", "tx"; +- }; +- src7: src-7 { +- interrupts = ; +- dmas = <&audma0 0x93>, <&audma1 0xb6>; +- dma-names = "rx", "tx"; +- }; +- src8: src-8 { +- interrupts = ; +- dmas = <&audma0 0x95>, <&audma1 0xb8>; +- dma-names = "rx", "tx"; +- }; +- src9: src-9 { +- interrupts = ; +- dmas = <&audma0 0x97>, <&audma1 0xba>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssi { +- ssi0: ssi-0 { +- interrupts = ; +- dmas = <&audma0 0x01>, <&audma1 0x02>, +- <&audma0 0x15>, <&audma1 0x16>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi1: ssi-1 { +- interrupts = ; +- dmas = <&audma0 0x03>, <&audma1 0x04>, +- <&audma0 0x49>, <&audma1 0x4a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi2: ssi-2 { +- interrupts = ; +- dmas = <&audma0 0x05>, <&audma1 0x06>, +- <&audma0 0x63>, <&audma1 0x64>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi3: ssi-3 { +- interrupts = ; +- dmas = <&audma0 0x07>, <&audma1 0x08>, +- <&audma0 0x6f>, <&audma1 0x70>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi4: ssi-4 { +- interrupts = ; +- dmas = <&audma0 0x09>, <&audma1 0x0a>, +- <&audma0 0x71>, <&audma1 0x72>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi5: ssi-5 { +- interrupts = ; +- dmas = <&audma0 0x0b>, <&audma1 0x0c>, +- <&audma0 0x73>, <&audma1 0x74>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi6: ssi-6 { +- interrupts = ; +- dmas = <&audma0 0x0d>, <&audma1 0x0e>, +- <&audma0 0x75>, <&audma1 0x76>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi7: ssi-7 { +- interrupts = ; +- dmas = <&audma0 0x0f>, <&audma1 0x10>, +- <&audma0 0x79>, <&audma1 0x7a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi8: ssi-8 { +- interrupts = ; +- dmas = <&audma0 0x11>, <&audma1 0x12>, +- <&audma0 0x7b>, <&audma1 0x7c>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi9: ssi-9 { +- interrupts = ; +- dmas = <&audma0 0x13>, <&audma1 0x14>, +- <&audma0 0x7d>, <&audma1 0x7e>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- }; +- }; +- +- audma0: dma-controller@ec700000 { +- compatible = "renesas,dmac-r8a7793", +- "renesas,rcar-dmac"; +- reg = <0 0xec700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12"; +- clocks = <&cpg CPG_MOD 502>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 502>; +- #dma-cells = <1>; +- dma-channels = <13>; +- }; +- +- audma1: dma-controller@ec720000 { +- compatible = "renesas,dmac-r8a7793", +- "renesas,rcar-dmac"; +- reg = <0 0xec720000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12"; +- clocks = <&cpg CPG_MOD 501>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 501>; +- #dma-cells = <1>; +- dma-channels = <13>; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a7793", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee100000 0 0x328>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- dmas = <&dmac0 0xcd>, <&dmac0 0xce>, +- <&dmac1 0xcd>, <&dmac1 0xce>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <195000000>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a7793", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee140000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 312>; +- dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, +- <&dmac1 0xc1>, <&dmac1 0xc2>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <97500000>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 312>; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ee160000 { +- compatible = "renesas,sdhi-r8a7793", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee160000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 311>; +- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, +- <&dmac1 0xd3>, <&dmac1 0xd4>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <97500000>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 311>; +- status = "disabled"; +- }; +- +- mmcif0: mmc@ee200000 { +- compatible = "renesas,mmcif-r8a7793", +- "renesas,sh-mmcif"; +- reg = <0 0xee200000 0 0x80>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 315>; +- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, +- <&dmac1 0xd1>, <&dmac1 0xd2>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 315>; +- reg-io-width = <4>; +- status = "disabled"; +- max-frequency = <97500000>; +- }; +- +- ether: ethernet@ee700000 { +- compatible = "renesas,ether-r8a7793", +- "renesas,rcar-gen2-ether"; +- reg = <0 0xee700000 0 0x400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 813>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 813>; +- phy-mode = "rmii"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1001000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0 0xf1001000 0 0x1000>, +- <0 0xf1002000 0 0x2000>, +- <0 0xf1004000 0 0x2000>, +- <0 0xf1006000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- fdp1@fe940000 { +- compatible = "renesas,fdp1"; +- reg = <0 0xfe940000 0 0x2400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 119>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 119>; +- }; +- +- fdp1@fe944000 { +- compatible = "renesas,fdp1"; +- reg = <0 0xfe944000 0 0x2400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 118>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 118>; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a7793"; +- reg = <0 0xfeb00000 0 0x40000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; +- clock-names = "du.0", "du.1"; +- resets = <&cpg 724>; +- reset-names = "du.0"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb: endpoint { +- }; +- }; +- port@1 { +- reg = <1>; +- du_out_lvds0: endpoint { +- remote-endpoint = <&lvds0_in>; +- }; +- }; +- }; +- }; +- +- lvds0: lvds@feb90000 { +- compatible = "renesas,r8a7793-lvds"; +- reg = <0 0xfeb90000 0 0x1c>; +- clocks = <&cpg CPG_MOD 726>; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 726>; +- +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds0_in: endpoint { +- remote-endpoint = <&du_out_lvds0>; +- }; +- }; +- port@1 { +- reg = <1>; +- lvds0_out: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@ff000044 { +- compatible = "renesas,prr"; +- reg = <0 0xff000044 0 4>; +- }; +- +- cmt0: timer@ffca0000 { +- compatible = "renesas,r8a7793-cmt0", +- "renesas,rcar-gen2-cmt0"; +- reg = <0 0xffca0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a7793-cmt1", +- "renesas,rcar-gen2-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 329>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; +- resets = <&cpg 329>; +- +- status = "disabled"; +- }; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&thermal>; +- +- trips { +- cpu-crit { +- temperature = <95000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- cooling-maps { +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +- }; +- +- /* External USB clock - can be overridden by the board */ +- usb_extal_clk: usb_extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <48000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7794-alt.dts b/scripts/dtc/include-prefixes/arm/r8a7794-alt.dts +deleted file mode 100644 +index f330d796a772..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7794-alt.dts ++++ /dev/null +@@ -1,531 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Alt board +- * +- * Copyright (C) 2014 Renesas Electronics Corporation +- */ +- +-/dts-v1/; +-#include "r8a7794.dtsi" +-#include +-#include +- +-/ { +- model = "Alt"; +- compatible = "renesas,alt", "renesas,r8a7794"; +- +- aliases { +- serial0 = &scif2; +- i2c9 = &gpioi2c1; +- i2c10 = &gpioi2c4; +- i2c11 = &i2chdmi; +- i2c12 = &i2cexio4; +- mmc0 = &mmcif0; +- mmc1 = &sdhi0; +- mmc2 = &sdhi1; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x40000000>; +- }; +- +- d3_3v: regulator-d3-3v { +- compatible = "regulator-fixed"; +- regulator-name = "D3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcc_sdhi0: regulator-vcc-sdhi0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI0 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhi0: regulator-vccq-sdhi0 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI0 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- vcc_sdhi1: regulator-vcc-sdhi1 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI1 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhi1: regulator-vccq-sdhi1 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI1 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- lbsc { +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- keyboard { +- compatible = "gpio-keys"; +- +- pinctrl-0 = <&keyboard_pins>; +- pinctrl-names = "default"; +- +- one { +- linux,code = ; +- label = "SW2-1"; +- wakeup-source; +- debounce-interval = <20>; +- gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; +- }; +- two { +- linux,code = ; +- label = "SW2-2"; +- wakeup-source; +- debounce-interval = <20>; +- gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; +- }; +- three { +- linux,code = ; +- label = "SW2-3"; +- wakeup-source; +- debounce-interval = <20>; +- gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; +- }; +- four { +- linux,code = ; +- label = "SW2-4"; +- wakeup-source; +- debounce-interval = <20>; +- gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- vga-encoder { +- compatible = "adi,adv7123"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7123_in: endpoint { +- remote-endpoint = <&du_out_rgb1>; +- }; +- }; +- port@1 { +- reg = <1>; +- adv7123_out: endpoint { +- remote-endpoint = <&vga_in>; +- }; +- }; +- }; +- }; +- +- vga { +- compatible = "vga-connector"; +- +- port { +- vga_in: endpoint { +- remote-endpoint = <&adv7123_out>; +- }; +- }; +- }; +- +- x2_clk: x2-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <74250000>; +- }; +- +- x13_clk: x13-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <148500000>; +- }; +- +- gpioi2c1: i2c-9 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "i2c-gpio"; +- status = "disabled"; +- scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- }; +- +- gpioi2c4: i2c-10 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "i2c-gpio"; +- status = "disabled"; +- scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <5>; +- }; +- +- /* +- * A fallback to GPIO is provided for I2C1. +- */ +- i2chdmi: i2c-11 { +- compatible = "i2c-demux-pinctrl"; +- i2c-parent = <&i2c1>, <&gpioi2c1>; +- i2c-bus-name = "i2c-hdmi"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- composite-in@20 { +- compatible = "adi,adv7180"; +- reg = <0x20>; +- +- port { +- adv7180: endpoint { +- bus-width = <8>; +- remote-endpoint = <&vin0ep>; +- }; +- }; +- }; +- +- eeprom@50 { +- compatible = "renesas,r1ex24002", "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- }; +- +- /* +- * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA). +- * A fallback to GPIO is provided. +- */ +- i2cexio4: i2c-14 { +- compatible = "i2c-demux-pinctrl"; +- i2c-parent = <&i2c4>, <&gpioi2c4>; +- i2c-bus-name = "i2c-exio4"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +- +-&pci0 { +- status = "okay"; +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +-}; +- +-&pci1 { +- status = "okay"; +- pinctrl-0 = <&usb1_pins>; +- pinctrl-names = "default"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&du { +- pinctrl-0 = <&du_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, +- <&x13_clk>, <&x2_clk>; +- clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; +- +- ports { +- port@1 { +- endpoint { +- remote-endpoint = <&adv7123_in>; +- }; +- }; +- }; +-}; +- +-&extal_clk { +- clock-frequency = <20000000>; +-}; +- +-&pfc { +- pinctrl-0 = <&scif_clk_pins>; +- pinctrl-names = "default"; +- +- du_pins: du { +- groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; +- function = "du1"; +- }; +- +- scif2_pins: scif2 { +- groups = "scif2_data"; +- function = "scif2"; +- }; +- +- scif_clk_pins: scif_clk { +- groups = "scif_clk"; +- function = "scif_clk"; +- }; +- +- ether_pins: ether { +- groups = "eth_link", "eth_mdio", "eth_rmii"; +- function = "eth"; +- }; +- +- phy1_pins: phy1 { +- groups = "intc_irq8"; +- function = "intc"; +- }; +- +- i2c1_pins: i2c1 { +- groups = "i2c1"; +- function = "i2c1"; +- }; +- +- i2c4_pins: i2c4 { +- groups = "i2c4"; +- function = "i2c4"; +- }; +- +- vin0_pins: vin0 { +- groups = "vin0_data8", "vin0_clk"; +- function = "vin0"; +- }; +- +- mmcif0_pins: mmcif0 { +- groups = "mmc_data8", "mmc_ctrl"; +- function = "mmc"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <3300>; +- }; +- +- sdhi0_pins_uhs: sd0_uhs { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <1800>; +- }; +- +- sdhi1_pins: sd1 { +- groups = "sdhi1_data4", "sdhi1_ctrl"; +- function = "sdhi1"; +- power-source = <3300>; +- }; +- +- sdhi1_pins_uhs: sd1_uhs { +- groups = "sdhi1_data4", "sdhi1_ctrl"; +- function = "sdhi1"; +- power-source = <1800>; +- }; +- +- usb0_pins: usb0 { +- groups = "usb0"; +- function = "usb0"; +- }; +- +- usb1_pins: usb1 { +- groups = "usb1"; +- function = "usb1"; +- }; +- +- keyboard_pins: keyboard { +- pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12"; +- bias-pull-up; +- }; +-}; +- +-&cmt0 { +- status = "okay"; +-}; +- +-&pfc { +- qspi_pins: qspi { +- groups = "qspi_ctrl", "qspi_data4"; +- function = "qspi"; +- }; +-}; +- +-ðer { +- pinctrl-0 = <ðer_pins>, <&phy1_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <&phy1>; +- renesas,ether-link-active-low; +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- interrupt-parent = <&irqc0>; +- interrupts = <8 IRQ_TYPE_LEVEL_LOW>; +- micrel,led-mode = <1>; +- reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&mmcif0 { +- pinctrl-0 = <&mmcif0_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <&d3_3v>; +- vqmmc-supply = <&d3_3v>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-1 = <&sdhi0_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <&vcc_sdhi0>; +- vqmmc-supply = <&vccq_sdhi0>; +- cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- status = "okay"; +-}; +- +-&sdhi1 { +- pinctrl-0 = <&sdhi1_pins>; +- pinctrl-1 = <&sdhi1_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <&vcc_sdhi1>; +- vqmmc-supply = <&vccq_sdhi1>; +- cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; +- sd-uhs-sdr50; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-0 = <&i2c1_pins>; +- pinctrl-names = "i2c-hdmi"; +- +- clock-frequency = <400000>; +-}; +- +-&i2c4 { +- pinctrl-0 = <&i2c4_pins>; +- pinctrl-names = "i2c-exio4"; +-}; +- +-&i2c7 { +- status = "okay"; +- clock-frequency = <100000>; +- +- pmic@58 { +- compatible = "dlg,da9063"; +- reg = <0x58>; +- interrupt-parent = <&gpio3>; +- interrupts = <31 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- +- rtc { +- compatible = "dlg,da9063-rtc"; +- }; +- +- wdt { +- compatible = "dlg,da9063-watchdog"; +- }; +- }; +-}; +- +-&vin0 { +- status = "okay"; +- pinctrl-0 = <&vin0_pins>; +- pinctrl-names = "default"; +- +- port { +- vin0ep: endpoint { +- remote-endpoint = <&adv7180>; +- bus-width = <8>; +- }; +- }; +-}; +- +-&scif2 { +- pinctrl-0 = <&scif2_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scif_clk { +- clock-frequency = <14745600>; +-}; +- +-&qspi { +- pinctrl-0 = <&qspi_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- flash@0 { +- compatible = "spansion,s25fl512s", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <30000000>; +- spi-tx-bus-width = <4>; +- spi-rx-bus-width = <4>; +- spi-cpol; +- spi-cpha; +- m25p,fast-read; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "loader"; +- reg = <0x00000000 0x00040000>; +- read-only; +- }; +- partition@40000 { +- label = "system"; +- reg = <0x00040000 0x00040000>; +- read-only; +- }; +- partition@80000 { +- label = "user"; +- reg = <0x00080000 0x03f80000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7794-silk.dts b/scripts/dtc/include-prefixes/arm/r8a7794-silk.dts +deleted file mode 100644 +index cafa3046daa4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7794-silk.dts ++++ /dev/null +@@ -1,576 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the SILK board +- * +- * Copyright (C) 2014 Renesas Electronics Corporation +- * Copyright (C) 2014-2015 Renesas Solutions Corp. +- * Copyright (C) 2014-2015 Cogent Embedded, Inc. +- */ +- +-/* +- * SSI-AK4643 +- * +- * SW1: 2-1: AK4643 +- * 2-3: ADV7511 +- * +- * This command is required before playback/capture: +- * +- * amixer set "LINEOUT Mixer DACL" on +- */ +- +-/dts-v1/; +-#include "r8a7794.dtsi" +-#include +-#include +- +-/ { +- model = "SILK"; +- compatible = "renesas,silk", "renesas,r8a7794"; +- +- aliases { +- serial0 = &scif2; +- i2c9 = &gpioi2c1; +- i2c10 = &i2chdmi; +- mmc0 = &mmcif0; +- mmc1 = &sdhi1; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x40000000>; +- }; +- +- keyboard { +- compatible = "gpio-keys"; +- +- pinctrl-0 = <&keyboard_pins>; +- pinctrl-names = "default"; +- +- key-3 { +- gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW3"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-4 { +- gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW4"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-6 { +- gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW6"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-a { +- gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW12-1"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-b { +- gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW12-2"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-c { +- gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW12-3"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-d { +- gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW12-4"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- }; +- +- d3_3v: regulator-d3-3v { +- compatible = "regulator-fixed"; +- regulator-name = "D3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcc_sdhi1: regulator-vcc-sdhi1 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI1 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhi1: regulator-vccq-sdhi1 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI1 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- vga-encoder { +- compatible = "adi,adv7123"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7123_in: endpoint { +- remote-endpoint = <&du_out_rgb1>; +- }; +- }; +- port@1 { +- reg = <1>; +- adv7123_out: endpoint { +- remote-endpoint = <&vga_in>; +- }; +- }; +- }; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con: endpoint { +- remote-endpoint = <&adv7511_out>; +- }; +- }; +- }; +- +- vga { +- compatible = "vga-connector"; +- +- port { +- vga_in: endpoint { +- remote-endpoint = <&adv7123_out>; +- }; +- }; +- }; +- +- x2_clk: x2-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <148500000>; +- }; +- +- x3_clk: x3-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <74250000>; +- }; +- +- x9_clk: audio_clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <12288000>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- +- simple-audio-card,format = "left_j"; +- simple-audio-card,bitclock-master = <&soundcodec>; +- simple-audio-card,frame-master = <&soundcodec>; +- +- simple-audio-card,cpu { +- sound-dai = <&rcar_sound>; +- }; +- +- soundcodec: simple-audio-card,codec { +- sound-dai = <&ak4643>; +- clocks = <&x9_clk>; +- }; +- }; +- +- gpioi2c1: i2c-9 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "i2c-gpio"; +- status = "disabled"; +- scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <5>; +- }; +- +- /* +- * A fallback to GPIO is provided for I2C1. +- */ +- i2chdmi: i2c-10 { +- compatible = "i2c-demux-pinctrl"; +- i2c-parent = <&i2c1>, <&gpioi2c1>; +- i2c-bus-name = "i2c-hdmi"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ak4643: codec@12 { +- compatible = "asahi-kasei,ak4643"; +- #sound-dai-cells = <0>; +- reg = <0x12>; +- }; +- +- composite-in@20 { +- compatible = "adi,adv7180"; +- reg = <0x20>; +- +- port { +- adv7180: endpoint { +- bus-width = <8>; +- remote-endpoint = <&vin0ep>; +- }; +- }; +- }; +- +- hdmi@39 { +- compatible = "adi,adv7511w"; +- reg = <0x39>; +- interrupt-parent = <&gpio5>; +- interrupts = <23 IRQ_TYPE_LEVEL_LOW>; +- +- adi,input-depth = <8>; +- adi,input-colorspace = "rgb"; +- adi,input-clock = "1x"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7511_in: endpoint { +- remote-endpoint = <&du_out_rgb0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- adv7511_out: endpoint { +- remote-endpoint = <&hdmi_con>; +- }; +- }; +- }; +- }; +- +- eeprom@50 { +- compatible = "renesas,r1ex24002", "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- }; +-}; +- +-&extal_clk { +- clock-frequency = <20000000>; +-}; +- +-&pfc { +- pinctrl-0 = <&scif_clk_pins>; +- pinctrl-names = "default"; +- +- scif2_pins: scif2 { +- groups = "scif2_data"; +- function = "scif2"; +- }; +- +- scif_clk_pins: scif_clk { +- groups = "scif_clk"; +- function = "scif_clk"; +- }; +- +- ether_pins: ether { +- groups = "eth_link", "eth_mdio", "eth_rmii"; +- function = "eth"; +- }; +- +- phy1_pins: phy1 { +- groups = "intc_irq8"; +- function = "intc"; +- }; +- +- i2c1_pins: i2c1 { +- groups = "i2c1"; +- function = "i2c1"; +- }; +- +- mmcif0_pins: mmcif0 { +- groups = "mmc_data8", "mmc_ctrl"; +- function = "mmc"; +- }; +- +- sdhi1_pins: sd1 { +- groups = "sdhi1_data4", "sdhi1_ctrl"; +- function = "sdhi1"; +- }; +- +- qspi_pins: qspi { +- groups = "qspi_ctrl", "qspi_data4"; +- function = "qspi"; +- }; +- +- vin0_pins: vin0 { +- groups = "vin0_data8", "vin0_clk"; +- function = "vin0"; +- }; +- +- usb0_pins: usb0 { +- groups = "usb0"; +- function = "usb0"; +- }; +- +- usb1_pins: usb1 { +- groups = "usb1"; +- function = "usb1"; +- }; +- +- du0_pins: du0 { +- groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out"; +- function = "du0"; +- }; +- +- du1_pins: du1 { +- groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; +- function = "du1"; +- }; +- +- keyboard_pins: keyboard { +- pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12"; +- bias-pull-up; +- }; +- +- ssi_pins: sound { +- groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; +- function = "ssi"; +- }; +- +- audio_clk_pins: audio_clk { +- groups = "audio_clkc"; +- function = "audio_clk"; +- }; +-}; +- +-&scif2 { +- pinctrl-0 = <&scif2_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scif_clk { +- clock-frequency = <14745600>; +-}; +- +-ðer { +- pinctrl-0 = <ðer_pins>, <&phy1_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <&phy1>; +- renesas,ether-link-active-low; +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- interrupt-parent = <&irqc0>; +- interrupts = <8 IRQ_TYPE_LEVEL_LOW>; +- micrel,led-mode = <1>; +- reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&i2c1 { +- pinctrl-0 = <&i2c1_pins>; +- pinctrl-names = "i2c-hdmi"; +- +- clock-frequency = <400000>; +-}; +- +-&i2c7 { +- status = "okay"; +- clock-frequency = <100000>; +- +- pmic@58 { +- compatible = "dlg,da9063"; +- reg = <0x58>; +- interrupt-parent = <&gpio3>; +- interrupts = <31 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- +- onkey { +- compatible = "dlg,da9063-onkey"; +- }; +- +- rtc { +- compatible = "dlg,da9063-rtc"; +- }; +- +- wdt { +- compatible = "dlg,da9063-watchdog"; +- }; +- }; +-}; +- +-&mmcif0 { +- pinctrl-0 = <&mmcif0_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <&d3_3v>; +- vqmmc-supply = <&d3_3v>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&sdhi1 { +- pinctrl-0 = <&sdhi1_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <&vcc_sdhi1>; +- vqmmc-supply = <&vccq_sdhi1>; +- cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&qspi { +- pinctrl-0 = <&qspi_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- flash@0 { +- compatible = "spansion,s25fl512s", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <30000000>; +- spi-tx-bus-width = <4>; +- spi-rx-bus-width = <4>; +- spi-cpol; +- spi-cpha; +- m25p,fast-read; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "loader"; +- reg = <0x00000000 0x00040000>; +- read-only; +- }; +- partition@40000 { +- label = "user"; +- reg = <0x00040000 0x00400000>; +- read-only; +- }; +- partition@440000 { +- label = "flash"; +- reg = <0x00440000 0x03bc0000>; +- }; +- }; +- }; +-}; +- +-/* composite video input */ +-&vin0 { +- status = "okay"; +- pinctrl-0 = <&vin0_pins>; +- pinctrl-names = "default"; +- +- port { +- vin0ep: endpoint { +- remote-endpoint = <&adv7180>; +- bus-width = <8>; +- }; +- }; +-}; +- +-&pci0 { +- status = "okay"; +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +-}; +- +-&pci1 { +- status = "okay"; +- pinctrl-0 = <&usb1_pins>; +- pinctrl-names = "default"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&du { +- pinctrl-0 = <&du0_pins>, <&du1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, +- <&x2_clk>, <&x3_clk>; +- clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; +- +- ports { +- port@0 { +- endpoint { +- remote-endpoint = <&adv7511_in>; +- }; +- }; +- port@1 { +- endpoint { +- remote-endpoint = <&adv7123_in>; +- }; +- }; +- }; +-}; +- +-&rcar_sound { +- pinctrl-0 = <&ssi_pins>, <&audio_clk_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- /* Single DAI */ +- #sound-dai-cells = <0>; +- +- rcar_sound,dai { +- dai0 { +- playback = <&ssi0>; +- capture = <&ssi1>; +- }; +- }; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&ssi1 { +- shared-pin; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a7794.dtsi b/scripts/dtc/include-prefixes/arm/r8a7794.dtsi +deleted file mode 100644 +index eac9ed8df0be..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a7794.dtsi ++++ /dev/null +@@ -1,1436 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Car E2 (R8A77940) SoC +- * +- * Copyright (C) 2014 Renesas Electronics Corporation +- * Copyright (C) 2014 Ulrich Hecht +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r8a7794"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c7; +- spi0 = &qspi; +- vin0 = &vin0; +- vin1 = &vin1; +- }; +- +- /* +- * The external audio clocks are configured as 0 Hz fixed frequency +- * clocks by default. +- * Boards that provide audio clocks should override them. +- */ +- audio_clka: audio_clka { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- audio_clkb: audio_clkb { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- audio_clkc: audio_clkc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* External CAN clock */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0>; +- clock-frequency = <1000000000>; +- clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; +- power-domains = <&sysc R8A7794_PD_CA7_CPU0>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA7>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <1>; +- clock-frequency = <1000000000>; +- clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; +- power-domains = <&sysc R8A7794_PD_CA7_CPU1>; +- enable-method = "renesas,apmu"; +- next-level-cache = <&L2_CA7>; +- }; +- +- L2_CA7: cache-controller-0 { +- compatible = "cache"; +- power-domains = <&sysc R8A7794_PD_CA7_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- }; +- +- /* External root clock */ +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- /* External SCIF clock */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a7794-wdt", +- "renesas,rcar-gen2-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a7794", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a7794", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a7794", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a7794", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a7794", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a7794", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 28>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- gpio6: gpio@e6055400 { +- compatible = "renesas,gpio-r8a7794", +- "renesas,rcar-gen2-gpio"; +- reg = <0 0xe6055400 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 192 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 905>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 905>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a7794"; +- reg = <0 0xe6060000 0 0x11c>; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a7794-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>, <&usb_extal_clk>; +- clock-names = "extal", "usb_extal"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- apmu@e6151000 { +- compatible = "renesas,r8a7794-apmu", "renesas,apmu"; +- reg = <0 0xe6151000 0 0x188>; +- cpus = <&cpu0>, <&cpu1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a7794-rst"; +- reg = <0 0xe6160000 0 0x0100>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a7794-sysc"; +- reg = <0 0xe6180000 0 0x0200>; +- #power-domain-cells = <1>; +- }; +- +- irqc0: interrupt-controller@e61c0000 { +- compatible = "renesas,irqc-r8a7794", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- ipmmu_sy0: iommu@e6280000 { +- compatible = "renesas,ipmmu-r8a7794", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6280000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_sy1: iommu@e6290000 { +- compatible = "renesas,ipmmu-r8a7794", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6290000 0 0x1000>; +- interrupts = ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_ds: iommu@e6740000 { +- compatible = "renesas,ipmmu-r8a7794", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe6740000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_mp: iommu@ec680000 { +- compatible = "renesas,ipmmu-r8a7794", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xec680000 0 0x1000>; +- interrupts = ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_mx: iommu@fe951000 { +- compatible = "renesas,ipmmu-r8a7794", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xfe951000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- ipmmu_gp: iommu@e62a0000 { +- compatible = "renesas,ipmmu-r8a7794", +- "renesas,ipmmu-vmsa"; +- reg = <0 0xe62a0000 0 0x1000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- icram0: sram@e63a0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63a0000 0 0x12000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63a0000 0x12000>; +- }; +- +- icram1: sram@e63c0000 { +- compatible = "mmio-sram"; +- reg = <0 0xe63c0000 0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xe63c0000 0x1000>; +- +- smp-sram@0 { +- compatible = "renesas,smp-sram"; +- reg = <0 0x100>; +- }; +- }; +- +- /* The memory map in the User's Manual maps the cores to +- * bus numbers +- */ +- i2c0: i2c@e6508000 { +- compatible = "renesas,i2c-r8a7794", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6518000 { +- compatible = "renesas,i2c-r8a7794", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6518000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6530000 { +- compatible = "renesas,i2c-r8a7794", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6530000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e6540000 { +- compatible = "renesas,i2c-r8a7794", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6540000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e6520000 { +- compatible = "renesas,i2c-r8a7794", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6520000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 927>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 927>; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c5: i2c@e6528000 { +- compatible = "renesas,i2c-r8a7794", +- "renesas,rcar-gen2-i2c"; +- reg = <0 0xe6528000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 925>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 925>; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c6: i2c@e6500000 { +- compatible = "renesas,iic-r8a7794", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe6500000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 318>; +- dmas = <&dmac0 0x61>, <&dmac0 0x62>, +- <&dmac1 0x61>, <&dmac1 0x62>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 318>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c7: i2c@e6510000 { +- compatible = "renesas,iic-r8a7794", +- "renesas,rcar-gen2-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe6510000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 323>; +- dmas = <&dmac0 0x65>, <&dmac0 0x66>, +- <&dmac1 0x65>, <&dmac1 0x66>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 323>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- hsusb: usb@e6590000 { +- compatible = "renesas,usbhs-r8a7794", +- "renesas,rcar-gen2-usbhs"; +- reg = <0 0xe6590000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 704>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 704>; +- renesas,buswait = <4>; +- phys = <&usb0 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usbphy: usb-phy@e6590100 { +- compatible = "renesas,usb-phy-r8a7794", +- "renesas,rcar-gen2-usb-phy"; +- reg = <0 0xe6590100 0 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cpg CPG_MOD 704>; +- clock-names = "usbhs"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 704>; +- status = "disabled"; +- +- usb0: usb-channel@0 { +- reg = <0>; +- #phy-cells = <1>; +- }; +- usb2: usb-channel@2 { +- reg = <2>; +- #phy-cells = <1>; +- }; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a7794", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- dmac1: dma-controller@e6720000 { +- compatible = "renesas,dmac-r8a7794", +- "renesas,rcar-dmac"; +- reg = <0 0xe6720000 0 0x20000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <15>; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a7794", +- "renesas,etheravb-rcar-gen2"; +- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- qspi: spi@e6b10000 { +- compatible = "renesas,qspi-r8a7794", "renesas,qspi"; +- reg = <0 0xe6b10000 0 0x2c>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 917>; +- dmas = <&dmac0 0x17>, <&dmac0 0x18>, +- <&dmac1 0x17>, <&dmac1 0x18>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 917>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- scifa0: serial@e6c40000 { +- compatible = "renesas,scifa-r8a7794", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c40000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>; +- clock-names = "fck"; +- dmas = <&dmac0 0x21>, <&dmac0 0x22>, +- <&dmac1 0x21>, <&dmac1 0x22>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scifa1: serial@e6c50000 { +- compatible = "renesas,scifa-r8a7794", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c50000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>; +- clock-names = "fck"; +- dmas = <&dmac0 0x25>, <&dmac0 0x26>, +- <&dmac1 0x25>, <&dmac1 0x26>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- scifa2: serial@e6c60000 { +- compatible = "renesas,scifa-r8a7794", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c60000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 202>; +- clock-names = "fck"; +- dmas = <&dmac0 0x27>, <&dmac0 0x28>, +- <&dmac1 0x27>, <&dmac1 0x28>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 202>; +- status = "disabled"; +- }; +- +- scifa3: serial@e6c70000 { +- compatible = "renesas,scifa-r8a7794", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c70000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1106>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, +- <&dmac1 0x1b>, <&dmac1 0x1c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 1106>; +- status = "disabled"; +- }; +- +- scifa4: serial@e6c78000 { +- compatible = "renesas,scifa-r8a7794", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c78000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1107>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1f>, <&dmac0 0x20>, +- <&dmac1 0x1f>, <&dmac1 0x20>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 1107>; +- status = "disabled"; +- }; +- +- scifa5: serial@e6c80000 { +- compatible = "renesas,scifa-r8a7794", +- "renesas,rcar-gen2-scifa", "renesas,scifa"; +- reg = <0 0xe6c80000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1108>; +- clock-names = "fck"; +- dmas = <&dmac0 0x23>, <&dmac0 0x24>, +- <&dmac1 0x23>, <&dmac1 0x24>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 1108>; +- status = "disabled"; +- }; +- +- scifb0: serial@e6c20000 { +- compatible = "renesas,scifb-r8a7794", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6c20000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>; +- clock-names = "fck"; +- dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, +- <&dmac1 0x3d>, <&dmac1 0x3e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scifb1: serial@e6c30000 { +- compatible = "renesas,scifb-r8a7794", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6c30000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>; +- clock-names = "fck"; +- dmas = <&dmac0 0x19>, <&dmac0 0x1a>, +- <&dmac1 0x19>, <&dmac1 0x1a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scifb2: serial@e6ce0000 { +- compatible = "renesas,scifb-r8a7794", +- "renesas,rcar-gen2-scifb", "renesas,scifb"; +- reg = <0 0xe6ce0000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 216>; +- clock-names = "fck"; +- dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, +- <&dmac1 0x1d>, <&dmac1 0x1e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 216>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a7794", +- "renesas,rcar-gen2-scif", +- "renesas,scif"; +- reg = <0 0xe6e60000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x29>, <&dmac0 0x2a>, +- <&dmac1 0x29>, <&dmac1 0x2a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 721>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a7794", +- "renesas,rcar-gen2-scif", +- "renesas,scif"; +- reg = <0 0xe6e68000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, +- <&dmac1 0x2d>, <&dmac1 0x2e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 720>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e58000 { +- compatible = "renesas,scif-r8a7794", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6e58000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, +- <&dmac1 0x2b>, <&dmac1 0x2c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 719>; +- status = "disabled"; +- }; +- +- scif3: serial@e6ea8000 { +- compatible = "renesas,scif-r8a7794", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ea8000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x2f>, <&dmac0 0x30>, +- <&dmac1 0x2f>, <&dmac1 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 718>; +- status = "disabled"; +- }; +- +- scif4: serial@e6ee0000 { +- compatible = "renesas,scif-r8a7794", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ee0000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, +- <&dmac1 0xfb>, <&dmac1 0xfc>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 715>; +- status = "disabled"; +- }; +- +- scif5: serial@e6ee8000 { +- compatible = "renesas,scif-r8a7794", +- "renesas,rcar-gen2-scif", "renesas,scif"; +- reg = <0 0xe6ee8000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, +- <&dmac1 0xfd>, <&dmac1 0xfe>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 714>; +- status = "disabled"; +- }; +- +- hscif0: serial@e62c0000 { +- compatible = "renesas,hscif-r8a7794", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c0000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 717>, +- <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x39>, <&dmac0 0x3a>, +- <&dmac1 0x39>, <&dmac1 0x3a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 717>; +- status = "disabled"; +- }; +- +- hscif1: serial@e62c8000 { +- compatible = "renesas,hscif-r8a7794", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62c8000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>, +- <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, +- <&dmac1 0x4d>, <&dmac1 0x4e>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- }; +- +- hscif2: serial@e62d0000 { +- compatible = "renesas,hscif-r8a7794", +- "renesas,rcar-gen2-hscif", "renesas,hscif"; +- reg = <0 0xe62d0000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, +- <&dmac1 0x3b>, <&dmac1 0x3c>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 713>; +- status = "disabled"; +- }; +- +- can0: can@e6e80000 { +- compatible = "renesas,can-r8a7794", +- "renesas,rcar-gen2-can"; +- reg = <0 0xe6e80000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- status = "disabled"; +- }; +- +- can1: can@e6e88000 { +- compatible = "renesas,can-r8a7794", +- "renesas,rcar-gen2-can"; +- reg = <0 0xe6e88000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- status = "disabled"; +- }; +- +- vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a7794", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef0000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 811>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 811>; +- status = "disabled"; +- }; +- +- vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a7794", +- "renesas,rcar-gen2-vin"; +- reg = <0 0xe6ef1000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 810>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 810>; +- status = "disabled"; +- }; +- +- rcar_sound: sound@ec500000 { +- /* +- * #sound-dai-cells is required +- * +- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; +- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; +- */ +- compatible = "renesas,rcar_sound-r8a7794", +- "renesas,rcar_sound-gen2"; +- reg = <0 0xec500000 0 0x1000>, /* SCU */ +- <0 0xec5a0000 0 0x100>, /* ADG */ +- <0 0xec540000 0 0x1000>, /* SSIU */ +- <0 0xec541000 0 0x280>, /* SSI */ +- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ +- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; +- +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, +- <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, +- <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, +- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, +- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clka>, <&audio_clkb>, <&audio_clkc>, +- <&cpg CPG_CORE R8A7794_CLK_M2>; +- clock-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0", +- "src.6", "src.5", "src.4", "src.3", +- "src.2", "src.1", +- "ctu.0", "ctu.1", +- "mix.0", "mix.1", +- "dvc.0", "dvc.1", +- "clk_a", "clk_b", "clk_c", "clk_i"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 1005>, +- <&cpg 1006>, <&cpg 1007>, +- <&cpg 1008>, <&cpg 1009>, +- <&cpg 1010>, <&cpg 1011>, +- <&cpg 1012>, <&cpg 1013>, +- <&cpg 1014>, <&cpg 1015>; +- reset-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0"; +- +- status = "disabled"; +- +- rcar_sound,dvc { +- dvc0: dvc-0 { +- dmas = <&audma0 0xbc>; +- dma-names = "tx"; +- }; +- dvc1: dvc-1 { +- dmas = <&audma0 0xbe>; +- dma-names = "tx"; +- }; +- }; +- +- rcar_sound,mix { +- mix0: mix-0 { }; +- mix1: mix-1 { }; +- }; +- +- rcar_sound,ctu { +- ctu00: ctu-0 { }; +- ctu01: ctu-1 { }; +- ctu02: ctu-2 { }; +- ctu03: ctu-3 { }; +- ctu10: ctu-4 { }; +- ctu11: ctu-5 { }; +- ctu12: ctu-6 { }; +- ctu13: ctu-7 { }; +- }; +- +- rcar_sound,src { +- src-0 { +- status = "disabled"; +- }; +- src1: src-1 { +- interrupts = ; +- dmas = <&audma0 0x87>, <&audma0 0x9c>; +- dma-names = "rx", "tx"; +- }; +- src2: src-2 { +- interrupts = ; +- dmas = <&audma0 0x89>, <&audma0 0x9e>; +- dma-names = "rx", "tx"; +- }; +- src3: src-3 { +- interrupts = ; +- dmas = <&audma0 0x8b>, <&audma0 0xa0>; +- dma-names = "rx", "tx"; +- }; +- src4: src-4 { +- interrupts = ; +- dmas = <&audma0 0x8d>, <&audma0 0xb0>; +- dma-names = "rx", "tx"; +- }; +- src5: src-5 { +- interrupts = ; +- dmas = <&audma0 0x8f>, <&audma0 0xb2>; +- dma-names = "rx", "tx"; +- }; +- src6: src-6 { +- interrupts = ; +- dmas = <&audma0 0x91>, <&audma0 0xb4>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssi { +- ssi0: ssi-0 { +- interrupts = ; +- dmas = <&audma0 0x01>, <&audma0 0x02>, +- <&audma0 0x15>, <&audma0 0x16>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi1: ssi-1 { +- interrupts = ; +- dmas = <&audma0 0x03>, <&audma0 0x04>, +- <&audma0 0x49>, <&audma0 0x4a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi2: ssi-2 { +- interrupts = ; +- dmas = <&audma0 0x05>, <&audma0 0x06>, +- <&audma0 0x63>, <&audma0 0x64>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi3: ssi-3 { +- interrupts = ; +- dmas = <&audma0 0x07>, <&audma0 0x08>, +- <&audma0 0x6f>, <&audma0 0x70>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi4: ssi-4 { +- interrupts = ; +- dmas = <&audma0 0x09>, <&audma0 0x0a>, +- <&audma0 0x71>, <&audma0 0x72>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi5: ssi-5 { +- interrupts = ; +- dmas = <&audma0 0x0b>, <&audma0 0x0c>, +- <&audma0 0x73>, <&audma0 0x74>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi6: ssi-6 { +- interrupts = ; +- dmas = <&audma0 0x0d>, <&audma0 0x0e>, +- <&audma0 0x75>, <&audma0 0x76>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi7: ssi-7 { +- interrupts = ; +- dmas = <&audma0 0x0f>, <&audma0 0x10>, +- <&audma0 0x79>, <&audma0 0x7a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi8: ssi-8 { +- interrupts = ; +- dmas = <&audma0 0x11>, <&audma0 0x12>, +- <&audma0 0x7b>, <&audma0 0x7c>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi9: ssi-9 { +- interrupts = ; +- dmas = <&audma0 0x13>, <&audma0 0x14>, +- <&audma0 0x7d>, <&audma0 0x7e>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- }; +- }; +- +- audma0: dma-controller@ec700000 { +- compatible = "renesas,dmac-r8a7794", +- "renesas,rcar-dmac"; +- reg = <0 0xec700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", "ch4", +- "ch5", "ch6", "ch7", "ch8", "ch9", +- "ch10", "ch11", +- "ch12"; +- clocks = <&cpg CPG_MOD 502>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 502>; +- #dma-cells = <1>; +- dma-channels = <13>; +- }; +- +- pci0: pci@ee090000 { +- compatible = "renesas,pci-r8a7794", +- "renesas,pci-rcar-gen2"; +- device_type = "pci"; +- reg = <0 0xee090000 0 0xc00>, +- <0 0xee080000 0 0x1100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- status = "disabled"; +- +- bus-range = <0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; +- interrupt-map-mask = <0xf800 0 0 0x7>; +- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, +- <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, +- <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; +- +- usb@1,0 { +- reg = <0x800 0 0 0 0>; +- phys = <&usb0 0>; +- phy-names = "usb"; +- }; +- +- usb@2,0 { +- reg = <0x1000 0 0 0 0>; +- phys = <&usb0 0>; +- phy-names = "usb"; +- }; +- }; +- +- pci1: pci@ee0d0000 { +- compatible = "renesas,pci-r8a7794", +- "renesas,pci-rcar-gen2"; +- device_type = "pci"; +- reg = <0 0xee0d0000 0 0xc00>, +- <0 0xee0c0000 0 0x1100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- status = "disabled"; +- +- bus-range = <1 1>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; +- interrupt-map-mask = <0xf800 0 0 0x7>; +- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, +- <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, +- <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; +- +- usb@1,0 { +- reg = <0x10800 0 0 0 0>; +- phys = <&usb2 0>; +- phy-names = "usb"; +- }; +- +- usb@2,0 { +- reg = <0x11000 0 0 0 0>; +- phys = <&usb2 0>; +- phy-names = "usb"; +- }; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a7794", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee100000 0 0x328>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- dmas = <&dmac0 0xcd>, <&dmac0 0xce>, +- <&dmac1 0xcd>, <&dmac1 0xce>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <195000000>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a7794", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee140000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 312>; +- dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, +- <&dmac1 0xc1>, <&dmac1 0xc2>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <97500000>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 312>; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ee160000 { +- compatible = "renesas,sdhi-r8a7794", +- "renesas,rcar-gen2-sdhi"; +- reg = <0 0xee160000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 311>; +- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, +- <&dmac1 0xd3>, <&dmac1 0xd4>; +- dma-names = "tx", "rx", "tx", "rx"; +- max-frequency = <97500000>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 311>; +- status = "disabled"; +- }; +- +- mmcif0: mmc@ee200000 { +- compatible = "renesas,mmcif-r8a7794", +- "renesas,sh-mmcif"; +- reg = <0 0xee200000 0 0x80>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 315>; +- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, +- <&dmac1 0xd1>, <&dmac1 0xd2>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 315>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- ether: ethernet@ee700000 { +- compatible = "renesas,ether-r8a7794", +- "renesas,rcar-gen2-ether"; +- reg = <0 0xee700000 0 0x400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 813>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 813>; +- phy-mode = "rmii"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1001000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0 0xf1001000 0 0x1000>, +- <0 0xf1002000 0 0x2000>, +- <0 0xf1004000 0 0x2000>, +- <0 0xf1006000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- vsp@fe928000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe928000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 131>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 131>; +- }; +- +- vsp@fe930000 { +- compatible = "renesas,vsp1"; +- reg = <0 0xfe930000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 128>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 128>; +- }; +- +- fdp1@fe940000 { +- compatible = "renesas,fdp1"; +- reg = <0 0xfe940000 0 0x2400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 119>; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 119>; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a7794"; +- reg = <0 0xfeb00000 0 0x40000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; +- clock-names = "du.0", "du.1"; +- resets = <&cpg 724>; +- reset-names = "du.0"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb0: endpoint { +- }; +- }; +- port@1 { +- reg = <1>; +- du_out_rgb1: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@ff000044 { +- compatible = "renesas,prr"; +- reg = <0 0xff000044 0 4>; +- }; +- +- cmt0: timer@ffca0000 { +- compatible = "renesas,r8a7794-cmt0", +- "renesas,rcar-gen2-cmt0"; +- reg = <0 0xffca0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a7794-cmt1", +- "renesas,rcar-gen2-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 329>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; +- resets = <&cpg 329>; +- +- status = "disabled"; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +- }; +- +- /* External USB clock - can be overridden by the board */ +- usb_extal_clk: usb_extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <48000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a77xx-aa104xd12-panel.dtsi b/scripts/dtc/include-prefixes/arm/r8a77xx-aa104xd12-panel.dtsi +deleted file mode 100644 +index 79fce67ebb1c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a77xx-aa104xd12-panel.dtsi ++++ /dev/null +@@ -1,39 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Common file for the AA104XD12 panel connected to Renesas R-Car boards +- * +- * Copyright (C) 2014 Renesas Electronics Corp. +- */ +- +-/ { +- panel { +- compatible = "mitsubishi,aa104xd12", "panel-lvds"; +- +- width-mm = <210>; +- height-mm = <158>; +- data-mapping = "jeida-18"; +- +- panel-timing { +- /* 1024x768 @65Hz */ +- clock-frequency = <65000000>; +- hactive = <1024>; +- vactive = <768>; +- hsync-len = <136>; +- hfront-porch = <20>; +- hback-porch = <160>; +- vfront-porch = <3>; +- vback-porch = <29>; +- vsync-len = <6>; +- }; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds_connector>; +- }; +- }; +- }; +-}; +- +-&lvds_connector { +- remote-endpoint = <&panel_in>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r8a77xx-aa121td01-panel.dtsi b/scripts/dtc/include-prefixes/arm/r8a77xx-aa121td01-panel.dtsi +deleted file mode 100644 +index 6e7589ea7562..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r8a77xx-aa121td01-panel.dtsi ++++ /dev/null +@@ -1,39 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Common file for the AA121TD01 panel connected to Renesas R-Car boards +- * +- * Copyright (C) 2015 Renesas Electronics Corp. +- */ +- +-/ { +- panel { +- compatible = "mitsubishi,aa121td01", "panel-lvds"; +- +- width-mm = <261>; +- height-mm = <163>; +- data-mapping = "jeida-18"; +- +- panel-timing { +- /* 1280x800 @60Hz */ +- clock-frequency = <71000000>; +- hactive = <1280>; +- vactive = <800>; +- hsync-len = <70>; +- hfront-porch = <20>; +- hback-porch = <70>; +- vsync-len = <5>; +- vfront-porch = <3>; +- vback-porch = <15>; +- }; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds_connector>; +- }; +- }; +- }; +-}; +- +-&lvds_connector { +- remote-endpoint = <&panel_in>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r9a06g032-rzn1d400-db.dts b/scripts/dtc/include-prefixes/arm/r9a06g032-rzn1d400-db.dts +deleted file mode 100644 +index 4e57ae2688fc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r9a06g032-rzn1d400-db.dts ++++ /dev/null +@@ -1,28 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the RZN1D-DB Board +- * +- * Copyright (C) 2018 Renesas Electronics Europe Limited +- * +- */ +- +-/dts-v1/; +- +-#include "r9a06g032.dtsi" +- +-/ { +- model = "RZN1D-DB Board"; +- compatible = "renesas,rzn1d400-db", "renesas,r9a06g032"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/r9a06g032.dtsi b/scripts/dtc/include-prefixes/arm/r9a06g032.dtsi +deleted file mode 100644 +index c47896e4ab58..000000000000 +--- a/scripts/dtc/include-prefixes/arm/r9a06g032.dtsi ++++ /dev/null +@@ -1,201 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032) +- * +- * Copyright (C) 2018 Renesas Electronics Europe Limited +- * +- */ +- +-#include +-#include +- +-/ { +- compatible = "renesas,r9a06g032"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0>; +- clocks = <&sysctrl R9A06G032_CLK_A7MP>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <1>; +- clocks = <&sysctrl R9A06G032_CLK_A7MP>; +- enable-method = "renesas,r9a06g032-smp"; +- cpu-release-addr = <0 0x4000c204>; +- }; +- }; +- +- ext_jtag_clk: extjtagclk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- ext_mclk: extmclk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <40000000>; +- }; +- +- ext_rgmii_ref: extrgmiiref { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- ext_rtc_clk: extrtcclk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&gic>; +- ranges; +- +- sysctrl: system-controller@4000c000 { +- compatible = "renesas,r9a06g032-sysctrl"; +- reg = <0x4000c000 0x1000>; +- status = "okay"; +- #clock-cells = <1>; +- +- clocks = <&ext_mclk>, <&ext_rtc_clk>, +- <&ext_jtag_clk>, <&ext_rgmii_ref>; +- clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; +- }; +- +- uart0: serial@40060000 { +- compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; +- reg = <0x40060000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>; +- clock-names = "baudclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- uart1: serial@40061000 { +- compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; +- reg = <0x40061000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>; +- clock-names = "baudclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- uart2: serial@40062000 { +- compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; +- reg = <0x40062000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>; +- clock-names = "baudclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- uart3: serial@50000000 { +- compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; +- reg = <0x50000000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; +- clock-names = "baudclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- uart4: serial@50001000 { +- compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; +- reg = <0x50001000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; +- clock-names = "baudclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- uart5: serial@50002000 { +- compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; +- reg = <0x50002000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; +- clock-names = "baudclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- uart6: serial@50003000 { +- compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; +- reg = <0x50003000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; +- clock-names = "baudclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- uart7: serial@50004000 { +- compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; +- reg = <0x50004000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; +- clock-names = "baudclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- pinctrl: pinctrl@40067000 { +- compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; +- reg = <0x40067000 0x1000>, <0x51000000 0x480>; +- clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; +- clock-names = "bus"; +- status = "okay"; +- }; +- +- gic: interrupt-controller@44101000 { +- compatible = "arm,gic-400", "arm,cortex-a7-gic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x44101000 0x1000>, /* Distributer */ +- <0x44102000 0x2000>, /* CPU interface */ +- <0x44104000 0x2000>, /* Virt interface control */ +- <0x44106000 0x2000>; /* Virt CPU interface */ +- interrupts = +- ; +- }; +- }; +- +- timer { +- compatible = "arm,cortex-a7-timer", +- "arm,armv7-timer"; +- interrupt-parent = <&gic>; +- arm,cpu-registers-not-fw-configured; +- always-on; +- interrupts = +- , +- , +- , +- ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rda8810pl-orangepi-2g-iot.dts b/scripts/dtc/include-prefixes/arm/rda8810pl-orangepi-2g-iot.dts +deleted file mode 100644 +index 98e34248ae80..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rda8810pl-orangepi-2g-iot.dts ++++ /dev/null +@@ -1,50 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Andreas Färber +- * Copyright (c) 2018 Manivannan Sadhasivam +- */ +- +-/dts-v1/; +- +-#include "rda8810pl.dtsi" +- +-/ { +- compatible = "xunlong,orangepi-2g-iot", "rda,8810pl"; +- model = "Orange Pi 2G-IoT"; +- +- aliases { +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial2:921600n8"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; +- }; +- +- uart_clk: uart-clk { +- compatible = "fixed-clock"; +- clock-frequency = <921600>; +- #clock-cells = <0>; +- }; +-}; +- +-&uart1 { +- status = "okay"; +- clocks = <&uart_clk>; +-}; +- +-&uart2 { +- status = "okay"; +- clocks = <&uart_clk>; +-}; +- +-&uart3 { +- status = "okay"; +- clocks = <&uart_clk>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rda8810pl-orangepi-i96.dts b/scripts/dtc/include-prefixes/arm/rda8810pl-orangepi-i96.dts +deleted file mode 100644 +index 728f76931b99..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rda8810pl-orangepi-i96.dts ++++ /dev/null +@@ -1,50 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Andreas Färber +- * Copyright (c) 2018 Manivannan Sadhasivam +- */ +- +-/dts-v1/; +- +-#include "rda8810pl.dtsi" +- +-/ { +- compatible = "xunlong,orangepi-i96", "rda,8810pl"; +- model = "Orange Pi i96"; +- +- aliases { +- serial0 = &uart2; +- serial1 = &uart1; +- serial2 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial2:921600n8"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; +- }; +- +- uart_clk: uart-clk { +- compatible = "fixed-clock"; +- clock-frequency = <921600>; +- #clock-cells = <0>; +- }; +-}; +- +-&uart1 { +- status = "okay"; +- clocks = <&uart_clk>; +-}; +- +-&uart2 { +- status = "okay"; +- clocks = <&uart_clk>; +-}; +- +-&uart3 { +- status = "okay"; +- clocks = <&uart_clk>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rda8810pl.dtsi b/scripts/dtc/include-prefixes/arm/rda8810pl.dtsi +deleted file mode 100644 +index f30d6ece49fb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rda8810pl.dtsi ++++ /dev/null +@@ -1,147 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * RDA8810PL SoC +- * +- * Copyright (c) 2017 Andreas Färber +- * Copyright (c) 2018 Manivannan Sadhasivam +- */ +- +-#include +- +-/ { +- compatible = "rda,8810pl"; +- interrupt-parent = <&intc>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a5"; +- reg = <0x0>; +- }; +- }; +- +- sram@100000 { +- compatible = "mmio-sram"; +- reg = <0x100000 0x10000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- }; +- +- modem@10000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10000000 0xfffffff>; +- +- gpioc@1a08000 { +- compatible = "rda,8810pl-gpio"; +- reg = <0x1a08000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- }; +- }; +- +- apb@20800000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x20800000 0x100000>; +- +- intc: interrupt-controller@0 { +- compatible = "rda,8810pl-intc"; +- reg = <0x0 0x1000>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- apb@20900000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x20900000 0x100000>; +- +- timer@10000 { +- compatible = "rda,8810pl-timer"; +- reg = <0x10000 0x1000>; +- interrupts = <16 IRQ_TYPE_LEVEL_HIGH>, +- <17 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "hwtimer", "ostimer"; +- }; +- +- gpioa@30000 { +- compatible = "rda,8810pl-gpio"; +- reg = <0x30000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- gpiob@31000 { +- compatible = "rda,8810pl-gpio"; +- reg = <0x31000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- gpiod@32000 { +- compatible = "rda,8810pl-gpio"; +- reg = <0x32000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; +- }; +- }; +- +- apb@20a00000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x20a00000 0x100000>; +- +- uart1: serial@0 { +- compatible = "rda,8810pl-uart"; +- reg = <0x0 0x1000>; +- interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +- +- uart2: serial@10000 { +- compatible = "rda,8810pl-uart"; +- reg = <0x10000 0x1000>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +- +- uart3: serial@90000 { +- compatible = "rda,8810pl-uart"; +- reg = <0x90000 0x1000>; +- interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +- }; +- +- l2: cache-controller@21100000 { +- compatible = "arm,pl310-cache"; +- reg = <0x21100000 0x1000>; +- cache-unified; +- cache-level = <2>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3036-evb.dts b/scripts/dtc/include-prefixes/arm/rk3036-evb.dts +deleted file mode 100644 +index 2a7e6624efb9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3036-evb.dts ++++ /dev/null +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-/dts-v1/; +- +-#include "rk3036.dtsi" +- +-/ { +- model = "Rockchip RK3036 Evaluation board"; +- compatible = "rockchip,rk3036-evb", "rockchip,rk3036"; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x40000000>; +- }; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_xfer>, <&emac_mdio>; +- phy = <&phy0>; +- phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ +- phy-reset-duration = <10>; /* millisecond */ +- +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- hym8563: hym8563@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "xin32k"; +- }; +-}; +- +-&uart2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3036-kylin.dts b/scripts/dtc/include-prefixes/arm/rk3036-kylin.dts +deleted file mode 100644 +index e817eba8c622..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3036-kylin.dts ++++ /dev/null +@@ -1,398 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-/dts-v1/; +- +-#include "rk3036.dtsi" +- +-/ { +- model = "Rockchip RK3036 KylinBoard"; +- compatible = "rockchip,rk3036-kylin", "rockchip,rk3036"; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x20000000>; +- }; +- +- leds: gpio-leds { +- compatible = "gpio-leds"; +- +- work_led: led-0 { +- gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; +- label = "kylin:red:led"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_ctl>; +- }; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_wake_h>; +- +- /* +- * On the module itself this is one of these (depending +- * on the actual card populated): +- * - SDIO_RESET_L_WL_REG_ON +- * - SDIO_RESET_L_WL_RST +- * - SDIO_RESET_L_BT_EN +- */ +- reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ +- <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>, /* WL_RST */ +- <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; /* BT_EN */ +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,name = "rockchip,rt5616-codec"; +- simple-audio-card,mclk-fs = <512>; +- simple-audio-card,widgets = +- "Microphone", "Microphone Jack", +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "MIC1", "Microphone Jack", +- "MIC2", "Microphone Jack", +- "Microphone Jack", "micbias1", +- "Headphone Jack", "HPOL", +- "Headphone Jack", "HPOR"; +- +- simple-audio-card,cpu { +- sound-dai = <&i2s>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&rt5616>; +- }; +- }; +- +- vcc_sys: vsys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&acodec { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_xfer>, <&emac_mdio>; +- phy = <&phy0>; +- phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ +- phy-reset-duration = <10>; /* millisecond */ +- +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&emmc { +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- +- status = "okay"; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int &global_pwroff>; +- rockchip,system-power-controller; +- wakeup-source; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc6-supply = <&vcc_sys>; +- vcc7-supply = <&vcc_sys>; +- vcc8-supply = <&vcc_18>; +- vcc9-supply = <&vcc_io>; +- vcc10-supply = <&vcc_io>; +- vcc11-supply = <&vcc_sys>; +- vcc12-supply = <&vcc_io>; +- vddio-supply = <&vccio_pmu>; +- +- regulators { +- vdd_cpu: DCDC_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-name = "vdd_arm"; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: DCDC_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-name = "vdd_gpu"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc_ddr"; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_io: DCDC_REG4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc_io"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vccio_pmu: LDO_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vccio_pmu"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_tp: LDO_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc_tp"; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_10: LDO_REG3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-name = "vdd_10"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc18_lcd: LDO_REG4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc18_lcd"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vccio_sd: LDO_REG5 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vccio_sd"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vout5: LDO_REG6 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2500000>; +- regulator-name = "vout5"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc_18: LDO_REG7 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc_18"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcca_codec: LDO_REG8 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcca_codec"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc_wl: SWITCH_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc_wl"; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_lcd: SWITCH_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc_lcd"; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- +- rt5616: rt5616@1b { +- compatible = "rt5616"; +- reg = <0x1b>; +- clocks = <&cru SCLK_I2S_OUT>; +- clock-names = "mclk"; +- #sound-dai-cells = <0>; +- }; +-}; +- +-&i2s { +- status = "okay"; +-}; +- +-&sdio { +- status = "okay"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- cap-sdio-irq; +- rockchip,default-sample-phase = <90>; +- keep-power-in-suspend; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- card-detect-delay = <200>; +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +- +-&vop { +- status = "okay"; +-}; +- +-&vop_mmu { +- status = "okay"; +-}; +- +-&pinctrl { +- leds { +- led_ctl: led-ctl { +- rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- pmic_int: pmic-int { +- rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_default>; +- }; +- }; +- +- sdio { +- bt_wake_h: bt-wake-h { +- rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_default>; +- }; +- }; +- +- sdmmc { +- sdmmc_pwr: sdmmc-pwr { +- rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- suspend { +- global_pwroff: global-pwroff { +- rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3036.dtsi b/scripts/dtc/include-prefixes/arm/rk3036.dtsi +deleted file mode 100644 +index ffa9bc7ed3d0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3036.dtsi ++++ /dev/null +@@ -1,871 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- compatible = "rockchip,rk3036"; +- +- interrupt-parent = <&gic>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- mshc0 = &emmc; +- mshc1 = &sdmmc; +- mshc2 = &sdio; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- spi = &spi; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "rockchip,rk3036-smp"; +- +- cpu0: cpu@f00 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0xf00>; +- resets = <&cru SRST_CORE0>; +- operating-points = < +- /* KHz uV */ +- 816000 1000000 +- >; +- clock-latency = <40000>; +- clocks = <&cru ARMCLK>; +- }; +- +- cpu1: cpu@f01 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0xf01>; +- resets = <&cru SRST_CORE1>; +- }; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupts = , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- display-subsystem { +- compatible = "rockchip,display-subsystem"; +- ports = <&vop_out>; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- arm,cpu-registers-not-fw-configured; +- interrupts = , +- , +- , +- ; +- clock-frequency = <24000000>; +- }; +- +- xin24m: oscillator { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "xin24m"; +- #clock-cells = <0>; +- }; +- +- bus_intmem: sram@10080000 { +- compatible = "mmio-sram"; +- reg = <0x10080000 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x10080000 0x2000>; +- +- smp-sram@0 { +- compatible = "rockchip,rk3066-smp-sram"; +- reg = <0x00 0x10>; +- }; +- }; +- +- gpu: gpu@10090000 { +- compatible = "rockchip,rk3036-mali", "arm,mali-400"; +- reg = <0x10090000 0x10000>; +- interrupts = , +- , +- , +- ; +- interrupt-names = "gp", +- "gpmmu", +- "pp0", +- "ppmmu0"; +- assigned-clocks = <&cru SCLK_GPU>; +- assigned-clock-rates = <100000000>; +- clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>; +- clock-names = "bus", "core"; +- power-domains = <&power RK3036_PD_GPU>; +- resets = <&cru SRST_GPU>; +- status = "disabled"; +- }; +- +- vpu: video-codec@10108000 { +- compatible = "rockchip,rk3036-vpu"; +- reg = <0x10108000 0x800>; +- interrupts = ; +- interrupt-names = "vdpu"; +- clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; +- clock-names = "aclk", "hclk"; +- iommus = <&vpu_mmu>; +- power-domains = <&power RK3036_PD_VPU>; +- }; +- +- vpu_mmu: iommu@10108800 { +- compatible = "rockchip,iommu"; +- reg = <0x10108800 0x100>; +- interrupts = ; +- clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; +- clock-names = "aclk", "iface"; +- power-domains = <&power RK3036_PD_VPU>; +- #iommu-cells = <0>; +- }; +- +- vop: vop@10118000 { +- compatible = "rockchip,rk3036-vop"; +- reg = <0x10118000 0x19c>; +- interrupts = ; +- clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>; +- clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; +- resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; +- reset-names = "axi", "ahb", "dclk"; +- iommus = <&vop_mmu>; +- power-domains = <&power RK3036_PD_VIO>; +- status = "disabled"; +- +- vop_out: port { +- #address-cells = <1>; +- #size-cells = <0>; +- vop_out_hdmi: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&hdmi_in_vop>; +- }; +- }; +- }; +- +- vop_mmu: iommu@10118300 { +- compatible = "rockchip,iommu"; +- reg = <0x10118300 0x100>; +- interrupts = ; +- clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>; +- clock-names = "aclk", "iface"; +- power-domains = <&power RK3036_PD_VIO>; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- qos_gpu: qos@1012d000 { +- compatible = "rockchip,rk3036-qos", "syscon"; +- reg = <0x1012d000 0x20>; +- }; +- +- qos_vpu: qos@1012e000 { +- compatible = "rockchip,rk3036-qos", "syscon"; +- reg = <0x1012e000 0x20>; +- }; +- +- qos_vio: qos@1012f000 { +- compatible = "rockchip,rk3036-qos", "syscon"; +- reg = <0x1012f000 0x20>; +- }; +- +- gic: interrupt-controller@10139000 { +- compatible = "arm,gic-400"; +- interrupt-controller; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- +- reg = <0x10139000 0x1000>, +- <0x1013a000 0x2000>, +- <0x1013c000 0x2000>, +- <0x1013e000 0x2000>; +- interrupts = ; +- }; +- +- usb_otg: usb@10180000 { +- compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", +- "snps,dwc2"; +- reg = <0x10180000 0x40000>; +- interrupts = ; +- clocks = <&cru HCLK_OTG0>; +- clock-names = "otg"; +- dr_mode = "otg"; +- g-np-tx-fifo-size = <16>; +- g-rx-fifo-size = <275>; +- g-tx-fifo-size = <256 128 128 64 64 32>; +- status = "disabled"; +- }; +- +- usb_host: usb@101c0000 { +- compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", +- "snps,dwc2"; +- reg = <0x101c0000 0x40000>; +- interrupts = ; +- clocks = <&cru HCLK_OTG1>; +- clock-names = "otg"; +- dr_mode = "host"; +- status = "disabled"; +- }; +- +- emac: ethernet@10200000 { +- compatible = "rockchip,rk3036-emac", "snps,arc-emac"; +- reg = <0x10200000 0x4000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- rockchip,grf = <&grf>; +- clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>; +- clock-names = "hclk", "macref", "macclk"; +- /* +- * Fix the emac parent clock is DPLL instead of APLL. +- * since that will cause some unstable things if the cpufreq +- * is working. (e.g: the accurate 50MHz what mac_ref need) +- */ +- assigned-clocks = <&cru SCLK_MACPLL>; +- assigned-clock-parents = <&cru PLL_DPLL>; +- max-speed = <100>; +- phy-mode = "rmii"; +- status = "disabled"; +- }; +- +- sdmmc: mmc@10214000 { +- compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x10214000 0x4000>; +- clock-frequency = <37500000>; +- max-frequency = <37500000>; +- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x100>; +- interrupts = ; +- resets = <&cru SRST_MMC0>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- sdio: mmc@10218000 { +- compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x10218000 0x4000>; +- max-frequency = <37500000>; +- clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, +- <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- interrupts = ; +- resets = <&cru SRST_SDIO>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- emmc: mmc@1021c000 { +- compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x1021c000 0x4000>; +- interrupts = ; +- bus-width = <8>; +- cap-mmc-highspeed; +- clock-frequency = <37500000>; +- max-frequency = <37500000>; +- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, +- <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- rockchip,default-sample-phase = <158>; +- disable-wp; +- dmas = <&pdma 12>; +- dma-names = "rx-tx"; +- fifo-depth = <0x100>; +- mmc-ddr-1_8v; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +- resets = <&cru SRST_EMMC>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- i2s: i2s@10220000 { +- compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s"; +- reg = <0x10220000 0x4000>; +- interrupts = ; +- clock-names = "i2s_clk", "i2s_hclk"; +- clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>; +- dmas = <&pdma 0>, <&pdma 1>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s_bus>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- nfc: nand-controller@10500000 { +- compatible = "rockchip,rk3036-nfc", +- "rockchip,rk2928-nfc"; +- reg = <0x10500000 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; +- clock-names = "ahb", "nfc"; +- assigned-clocks = <&cru SCLK_NANDC>; +- assigned-clock-rates = <150000000>; +- pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 +- &flash_rdn &flash_rdy &flash_wrn>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- cru: clock-controller@20000000 { +- compatible = "rockchip,rk3036-cru"; +- reg = <0x20000000 0x1000>; +- rockchip,grf = <&grf>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- assigned-clocks = <&cru PLL_GPLL>; +- assigned-clock-rates = <594000000>; +- }; +- +- grf: syscon@20008000 { +- compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; +- reg = <0x20008000 0x1000>; +- +- power: power-controller { +- compatible = "rockchip,rk3036-power-controller"; +- #power-domain-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- power-domain@RK3036_PD_VIO { +- reg = ; +- clocks = <&cru ACLK_LCDC>, +- <&cru HCLK_LCDC>, +- <&cru SCLK_LCDC>; +- pm_qos = <&qos_vio>; +- #power-domain-cells = <0>; +- }; +- +- power-domain@RK3036_PD_VPU { +- reg = ; +- clocks = <&cru ACLK_VCODEC>, +- <&cru HCLK_VCODEC>; +- pm_qos = <&qos_vpu>; +- #power-domain-cells = <0>; +- }; +- +- power-domain@RK3036_PD_GPU { +- reg = ; +- clocks = <&cru SCLK_GPU>; +- pm_qos = <&qos_gpu>; +- #power-domain-cells = <0>; +- }; +- }; +- +- reboot-mode { +- compatible = "syscon-reboot-mode"; +- offset = <0x1d8>; +- mode-normal = ; +- mode-recovery = ; +- mode-bootloader = ; +- mode-loader = ; +- }; +- }; +- +- acodec: acodec-ana@20030000 { +- compatible = "rk3036-codec"; +- reg = <0x20030000 0x4000>; +- rockchip,grf = <&grf>; +- clock-names = "acodec_pclk"; +- clocks = <&cru PCLK_ACODEC>; +- status = "disabled"; +- }; +- +- hdmi: hdmi@20034000 { +- compatible = "rockchip,rk3036-inno-hdmi"; +- reg = <0x20034000 0x4000>; +- interrupts = ; +- clocks = <&cru PCLK_HDMI>; +- clock-names = "pclk"; +- rockchip,grf = <&grf>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_ctl>; +- status = "disabled"; +- +- hdmi_in: port { +- #address-cells = <1>; +- #size-cells = <0>; +- hdmi_in_vop: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vop_out_hdmi>; +- }; +- }; +- }; +- +- timer: timer@20044000 { +- compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer"; +- reg = <0x20044000 0x20>; +- interrupts = ; +- clocks = <&xin24m>, <&cru PCLK_TIMER>; +- clock-names = "timer", "pclk"; +- }; +- +- pwm0: pwm@20050000 { +- compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; +- reg = <0x20050000 0x10>; +- #pwm-cells = <3>; +- clocks = <&cru PCLK_PWM>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>; +- status = "disabled"; +- }; +- +- pwm1: pwm@20050010 { +- compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; +- reg = <0x20050010 0x10>; +- #pwm-cells = <3>; +- clocks = <&cru PCLK_PWM>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm1_pin>; +- status = "disabled"; +- }; +- +- pwm2: pwm@20050020 { +- compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; +- reg = <0x20050020 0x10>; +- #pwm-cells = <3>; +- clocks = <&cru PCLK_PWM>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm2_pin>; +- status = "disabled"; +- }; +- +- pwm3: pwm@20050030 { +- compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; +- reg = <0x20050030 0x10>; +- #pwm-cells = <2>; +- clocks = <&cru PCLK_PWM>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm3_pin>; +- status = "disabled"; +- }; +- +- i2c1: i2c@20056000 { +- compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; +- reg = <0x20056000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "i2c"; +- clocks = <&cru PCLK_I2C1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_xfer>; +- status = "disabled"; +- }; +- +- i2c2: i2c@2005a000 { +- compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; +- reg = <0x2005a000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "i2c"; +- clocks = <&cru PCLK_I2C2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_xfer>; +- status = "disabled"; +- }; +- +- uart0: serial@20060000 { +- compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; +- reg = <0x20060000 0x100>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <24000000>; +- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; +- clock-names = "baudclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +- status = "disabled"; +- }; +- +- uart1: serial@20064000 { +- compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; +- reg = <0x20064000 0x100>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <24000000>; +- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; +- clock-names = "baudclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_xfer>; +- status = "disabled"; +- }; +- +- uart2: serial@20068000 { +- compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; +- reg = <0x20068000 0x100>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <24000000>; +- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; +- clock-names = "baudclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_xfer>; +- status = "disabled"; +- }; +- +- i2c0: i2c@20072000 { +- compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; +- reg = <0x20072000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "i2c"; +- clocks = <&cru PCLK_I2C0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_xfer>; +- status = "disabled"; +- }; +- +- spi: spi@20074000 { +- compatible = "rockchip,rockchip-spi"; +- reg = <0x20074000 0x1000>; +- interrupts = ; +- clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>; +- clock-names = "apb-pclk","spi_pclk"; +- dmas = <&pdma 8>, <&pdma 9>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pdma: pdma@20078000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x20078000 0x4000>; +- interrupts = , +- ; +- #dma-cells = <1>; +- arm,pl330-broken-no-flushp; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMAC2>; +- clock-names = "apb_pclk"; +- }; +- +- pinctrl: pinctrl { +- compatible = "rockchip,rk3036-pinctrl"; +- rockchip,grf = <&grf>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gpio0: gpio0@2007c000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x2007c000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio1@20080000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x20080000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO1>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio2@20084000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x20084000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO2>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pcfg_pull_default: pcfg_pull_default { +- bias-pull-pin-default; +- }; +- +- pcfg_pull_none: pcfg-pull-none { +- bias-disable; +- }; +- +- pwm0 { +- pwm0_pin: pwm0-pin { +- rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; +- }; +- }; +- +- pwm1 { +- pwm1_pin: pwm1-pin { +- rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; +- }; +- }; +- +- pwm2 { +- pwm2_pin: pwm2-pin { +- rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; +- }; +- }; +- +- pwm3 { +- pwm3_pin: pwm3-pin { +- rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; +- }; +- }; +- +- sdmmc { +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; +- }; +- +- sdmmc_cd: sdmmc-cd { +- rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; +- }; +- +- sdmmc_bus1: sdmmc-bus1 { +- rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>; +- }; +- +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, +- <1 RK_PC3 1 &pcfg_pull_default>, +- <1 RK_PC4 1 &pcfg_pull_default>, +- <1 RK_PC5 1 &pcfg_pull_default>; +- }; +- }; +- +- sdio { +- sdio_bus1: sdio-bus1 { +- rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>; +- }; +- +- sdio_bus4: sdio-bus4 { +- rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>, +- <0 RK_PB4 1 &pcfg_pull_default>, +- <0 RK_PB5 1 &pcfg_pull_default>, +- <0 RK_PB6 1 &pcfg_pull_default>; +- }; +- +- sdio_cmd: sdio-cmd { +- rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>; +- }; +- +- sdio_clk: sdio-clk { +- rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>; +- }; +- }; +- +- emmc { +- /* +- * We run eMMC at max speed; bump up drive strength. +- * We also have external pulls, so disable the internal ones. +- */ +- emmc_clk: emmc-clk { +- rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; +- }; +- +- emmc_cmd: emmc-cmd { +- rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>; +- }; +- +- emmc_bus8: emmc-bus8 { +- rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, +- <1 RK_PD1 2 &pcfg_pull_default>, +- <1 RK_PD2 2 &pcfg_pull_default>, +- <1 RK_PD3 2 &pcfg_pull_default>, +- <1 RK_PD4 2 &pcfg_pull_default>, +- <1 RK_PD5 2 &pcfg_pull_default>, +- <1 RK_PD6 2 &pcfg_pull_default>, +- <1 RK_PD7 2 &pcfg_pull_default>; +- }; +- }; +- +- nfc { +- flash_ale: flash-ale { +- rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>; +- }; +- +- flash_bus8: flash-bus8 { +- rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>, +- <1 RK_PD1 1 &pcfg_pull_default>, +- <1 RK_PD2 1 &pcfg_pull_default>, +- <1 RK_PD3 1 &pcfg_pull_default>, +- <1 RK_PD4 1 &pcfg_pull_default>, +- <1 RK_PD5 1 &pcfg_pull_default>, +- <1 RK_PD6 1 &pcfg_pull_default>, +- <1 RK_PD7 1 &pcfg_pull_default>; +- }; +- +- flash_cle: flash-cle { +- rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>; +- }; +- +- flash_csn0: flash-csn0 { +- rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>; +- }; +- +- flash_rdn: flash-rdn { +- rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>; +- }; +- +- flash_rdy: flash-rdy { +- rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>; +- }; +- +- flash_wrn: flash-wrn { +- rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>; +- }; +- }; +- +- emac { +- emac_xfer: emac-xfer { +- rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */ +- <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */ +- <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */ +- <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */ +- <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */ +- <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */ +- <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */ +- <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */ +- }; +- +- emac_mdio: emac-mdio { +- rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */ +- <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */ +- }; +- }; +- +- i2c0 { +- i2c0_xfer: i2c0-xfer { +- rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, +- <0 RK_PA1 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c1 { +- i2c1_xfer: i2c1-xfer { +- rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, +- <0 RK_PA3 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c2 { +- i2c2_xfer: i2c2-xfer { +- rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, +- <2 RK_PC5 1 &pcfg_pull_none>; +- }; +- }; +- +- i2s { +- i2s_bus: i2s-bus { +- rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, +- <1 RK_PA1 1 &pcfg_pull_default>, +- <1 RK_PA2 1 &pcfg_pull_default>, +- <1 RK_PA3 1 &pcfg_pull_default>, +- <1 RK_PA4 1 &pcfg_pull_default>, +- <1 RK_PA5 1 &pcfg_pull_default>; +- }; +- }; +- +- hdmi { +- hdmi_ctl: hdmi-ctl { +- rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>, +- <1 RK_PB1 1 &pcfg_pull_none>, +- <1 RK_PB2 1 &pcfg_pull_none>, +- <1 RK_PB3 1 &pcfg_pull_none>; +- }; +- }; +- +- uart0 { +- uart0_xfer: uart0-xfer { +- rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, +- <0 RK_PC1 1 &pcfg_pull_none>; +- }; +- +- uart0_cts: uart0-cts { +- rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>; +- }; +- +- uart0_rts: uart0-rts { +- rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>; +- }; +- }; +- +- uart1 { +- uart1_xfer: uart1-xfer { +- rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>, +- <2 RK_PC7 1 &pcfg_pull_none>; +- }; +- /* no rts / cts for uart1 */ +- }; +- +- uart2 { +- uart2_xfer: uart2-xfer { +- rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, +- <1 RK_PC3 2 &pcfg_pull_none>; +- }; +- /* no rts / cts for uart2 */ +- }; +- +- spi-pins { +- spi_txd:spi-txd { +- rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; +- }; +- +- spi_rxd:spi-rxd { +- rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; +- }; +- +- spi_clk:spi-clk { +- rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; +- }; +- +- spi_cs0:spi-cs0 { +- rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; +- +- }; +- +- spi_cs1:spi-cs1 { +- rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; +- +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3066a-bqcurie2.dts b/scripts/dtc/include-prefixes/arm/rk3066a-bqcurie2.dts +deleted file mode 100644 +index 390aa33cd55a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3066a-bqcurie2.dts ++++ /dev/null +@@ -1,207 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2013 MundoReader S.L. +- * Author: Heiko Stuebner +- */ +- +-/dts-v1/; +-#include +-#include "rk3066a.dtsi" +- +-/ { +- model = "bq Curie 2"; +- compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; +- +- aliases { +- mmc0 = &mmc0; +- mmc1 = &mmc1; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x40000000>; +- }; +- +- vdd_log: vdd-log { +- compatible = "pwm-regulator"; +- pwms = <&pwm3 0 1000>; +- regulator-name = "vdd_log"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- voltage-table = <1000000 100>, +- <1200000 42>; +- status = "okay"; +- }; +- +- vcc_sd0: fixed-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "sdmmc-supply"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; +- startup-delay-us = <100000>; +- vin-supply = <&vcc_io>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- +- power { +- gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */ +- linux,code = ; +- label = "GPIO Key Power"; +- linux,input-type = <1>; +- wakeup-source; +- debounce-interval = <100>; +- }; +- volume-down { +- gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */ +- linux,code = ; +- label = "GPIO Key Vol-"; +- linux,input-type = <1>; +- debounce-interval = <100>; +- }; +- /* VOL+ comes somehow thru the ADC */ +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- tps: tps@2d { +- reg = <0x2d>; +- +- interrupt-parent = <&gpio6>; +- interrupts = ; +- +- vcc5-supply = <&vcc_io>; +- vcc6-supply = <&vcc_io>; +- +- regulators { +- vcc_rtc: regulator@0 { +- regulator-name = "vcc_rtc"; +- regulator-always-on; +- }; +- +- vcc_io: regulator@1 { +- regulator-name = "vcc_io"; +- regulator-always-on; +- }; +- +- vdd_arm: regulator@2 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcc_ddr: regulator@3 { +- regulator-name = "vcc_ddr"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcc18_cif: regulator@5 { +- regulator-name = "vcc18_cif"; +- regulator-always-on; +- }; +- +- vdd_11: regulator@6 { +- regulator-name = "vdd_11"; +- regulator-always-on; +- }; +- +- vcc_25: regulator@7 { +- regulator-name = "vcc_25"; +- regulator-always-on; +- }; +- +- vcc_18: regulator@8 { +- regulator-name = "vcc_18"; +- regulator-always-on; +- }; +- +- vcc25_hdmi: regulator@9 { +- regulator-name = "vcc25_hdmi"; +- regulator-always-on; +- }; +- +- vcca_33: regulator@10 { +- regulator-name = "vcca_33"; +- regulator-always-on; +- }; +- +- vcc_tp: regulator@11 { +- regulator-name = "vcc_tp"; +- regulator-always-on; +- }; +- +- vcc28_cif: regulator@12 { +- regulator-name = "vcc28_cif"; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-/* must be included after &tps gets defined */ +-#include "tps65910.dtsi" +- +-&mmc0 { /* sdmmc */ +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; +- vmmc-supply = <&vcc_sd0>; +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- disable-wp; +-}; +- +-&mmc1 { /* wifi */ +- status = "okay"; +- non-removable; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; +- +- bus-width = <4>; +-}; +- +-&pwm3 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3066a-marsboard.dts b/scripts/dtc/include-prefixes/arm/rk3066a-marsboard.dts +deleted file mode 100644 +index a66d915aa0f6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3066a-marsboard.dts ++++ /dev/null +@@ -1,218 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2014 Romain Perier +- */ +- +-/dts-v1/; +-#include "rk3066a.dtsi" +- +-/ { +- model = "MarsBoard RK3066"; +- compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a"; +- +- aliases { +- mmc0 = &mmc0; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x40000000>; +- }; +- +- vdd_log: vdd-log { +- compatible = "pwm-regulator"; +- pwms = <&pwm3 0 1000>; +- regulator-name = "vdd_log"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- voltage-table = <1000000 100>, +- <1200000 42>; +- status = "okay"; +- }; +- +- vcc_sd0: sdmmc-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "sdmmc-supply"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; +- startup-delay-us = <100000>; +- vin-supply = <&vcc_io>; +- }; +- +- vsys: vsys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vsys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- tps: tps@2d { +- reg = <0x2d>; +- +- interrupt-parent = <&gpio6>; +- interrupts = ; +- +- vcc1-supply = <&vsys>; +- vcc2-supply = <&vsys>; +- vcc3-supply = <&vsys>; +- vcc4-supply = <&vsys>; +- vcc5-supply = <&vcc_io>; +- vcc6-supply = <&vcc_io>; +- vcc7-supply = <&vsys>; +- vccio-supply = <&vsys>; +- +- regulators { +- vcc_rtc: regulator@0 { +- regulator-name = "vcc_rtc"; +- regulator-always-on; +- }; +- +- vcc_io: regulator@1 { +- regulator-name = "vcc_io"; +- regulator-always-on; +- }; +- +- vdd_arm: regulator@2 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcc_ddr: regulator@3 { +- regulator-name = "vcc_ddr"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcc18_cif: regulator@5 { +- regulator-name = "vcc18_cif"; +- regulator-always-on; +- }; +- +- vdd_11: regulator@6 { +- regulator-name = "vdd_11"; +- regulator-always-on; +- }; +- +- vcc_25: regulator@7 { +- regulator-name = "vcc_25"; +- regulator-always-on; +- }; +- +- vcc_18: regulator@8 { +- regulator-name = "vcc_18"; +- regulator-always-on; +- }; +- +- vcc25_hdmi: regulator@9 { +- regulator-name = "vcc25_hdmi"; +- regulator-always-on; +- }; +- +- vcca_33: regulator@10 { +- regulator-name = "vcca_33"; +- regulator-always-on; +- }; +- +- vcc_rmii: regulator@11 { +- regulator-name = "vcc_rmii"; +- }; +- +- vcc28_cif: regulator@12 { +- regulator-name = "vcc28_cif"; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-/* must be included after &tps gets defined */ +-#include "tps65910.dtsi" +- +-&emac { +- status = "okay"; +- +- phy = <&phy0>; +- phy-supply = <&vcc_rmii>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- interrupt-parent = <&gpio1>; +- interrupts = ; +- }; +-}; +- +-&mmc0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; +- vmmc-supply = <&vcc_sd0>; +-}; +- +-&pinctrl { +- lan8720a { +- phy_int: phy-int { +- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm3 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&usb_host { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3066a-mk808.dts b/scripts/dtc/include-prefixes/arm/rk3066a-mk808.dts +deleted file mode 100644 +index 9790bc63b50a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3066a-mk808.dts ++++ /dev/null +@@ -1,189 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Paweł Jarosz +- */ +- +-/dts-v1/; +-#include "rk3066a.dtsi" +- +-/ { +- model = "Rikomagic MK808"; +- compatible = "rikomagic,mk808", "rockchip,rk3066a"; +- +- aliases { +- mmc0 = &mmc0; +- mmc1 = &mmc1; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- memory@60000000 { +- reg = <0x60000000 0x40000000>; +- device_type = "memory"; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- blue_led: led-0 { +- label = "mk808:blue:power"; +- gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "default-on"; +- }; +- }; +- +- hdmi_con { +- compatible = "hdmi-connector"; +- type = "c"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- vcc_io: vcc-io { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vcc_host: usb-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; +- pinctrl-0 = <&host_drv>; +- pinctrl-names = "default"; +- regulator-always-on; +- regulator-name = "host-pwr"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- startup-delay-us = <100000>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_otg: usb-otg-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; +- pinctrl-0 = <&otg_drv>; +- pinctrl-names = "default"; +- regulator-always-on; +- regulator-name = "vcc_otg"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- startup-delay-us = <100000>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_sd: sdmmc-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; +- pinctrl-0 = <&sdmmc_pwr>; +- pinctrl-names = "default"; +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_wifi: sdio-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; +- pinctrl-0 = <&wifi_pwr>; +- pinctrl-names = "default"; +- regulator-name = "vcc_wifi"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- vin-supply = <&vcc_io>; +- }; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_in_vop1 { +- status = "disabled"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&mmc0 { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- vmmc-supply = <&vcc_sd>; +- status = "okay"; +-}; +- +-&mmc1 { +- bus-width = <4>; +- non-removable; +- pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; +- pinctrl-names = "default"; +- vmmc-supply = <&vcc_wifi>; +- status = "okay"; +-}; +- +-&pinctrl { +- usb-host { +- host_drv: host-drv { +- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_default>; +- }; +- }; +- +- usb-otg { +- otg_drv: otg-drv { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_default>; +- }; +- }; +- +- sdmmc { +- sdmmc_pwr: sdmmc-pwr { +- rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_default>; +- }; +- }; +- +- sdio { +- wifi_pwr: wifi-pwr { +- rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&vop0 { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3066a-rayeager.dts b/scripts/dtc/include-prefixes/arm/rk3066a-rayeager.dts +deleted file mode 100644 +index 12b2e59aebc4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3066a-rayeager.dts ++++ /dev/null +@@ -1,457 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2014, 2015 FUKAUMI Naoki +- */ +- +-/dts-v1/; +-#include +-#include "rk3066a.dtsi" +- +-/ { +- model = "Rayeager PX2"; +- compatible = "chipspark,rayeager-px2", "rockchip,rk3066a"; +- +- aliases { +- mmc0 = &mmc0; +- mmc1 = &mmc1; +- mmc2 = &emmc; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x40000000>; +- }; +- +- ir: ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio6 RK_PA1 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ir_int>; +- }; +- +- keys: gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- wakeup-source; +- gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>; +- label = "GPIO Power"; +- linux,code = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_key>; +- }; +- }; +- +- vdd_log: vdd-log { +- compatible = "pwm-regulator"; +- pwms = <&pwm3 0 1000>; +- regulator-name = "vdd_log"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- voltage-table = <1000000 100>, +- <1200000 42>; +- status = "okay"; +- }; +- +- vsys: vsys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vsys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* input for 5V_STDBY is VSYS or DC5V, selectable by jumper J4 */ +- vcc_stdby: stdby-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "5v_stdby"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc_emmc: emmc-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "emmc_vccq"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- vin-supply = <&vsys>; +- }; +- +- vcc_sata: sata-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sata_pwr>; +- regulator-name = "usb_5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- vin-supply = <&vcc_stdby>; +- }; +- +- vcc_sd: sdmmc-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_pwr>; +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_host: usb-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&host_drv>; +- regulator-name = "host-pwr"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- vin-supply = <&vcc_stdby>; +- }; +- +- vcc_otg: usb-otg-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&otg_drv>; +- regulator-name = "vcc_otg"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- vin-supply = <&vcc_stdby>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>; +- phy = <&phy0>; +- phy-supply = <&vcc_rmii>; +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>; +- vmmc-supply = <&vcc_emmc>; +- vqmmc-supply = <&vcc_emmc>; +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- status = "okay"; +- +- ak8963: ak8963@d { +- compatible = "asahi-kasei,ak8975"; +- reg = <0x0d>; +- interrupt-parent = <&gpio4>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&comp_int>; +- }; +- +- mma8452: mma8452@1d { +- compatible = "fsl,mma8452"; +- reg = <0x1d>; +- interrupt-parent = <&gpio4>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&gsensor_int>; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- status = "okay"; +- +- tps: tps@2d { +- reg = <0x2d>; +- interrupt-parent = <&gpio6>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int>, <&pwr_hold>; +- +- vcc1-supply = <&vsys>; +- vcc2-supply = <&vsys>; +- vcc3-supply = <&vsys>; +- vcc4-supply = <&vsys>; +- vcc5-supply = <&vcc_io>; +- vcc6-supply = <&vcc_io>; +- vcc7-supply = <&vsys>; +- vccio-supply = <&vsys>; +- +- regulators { +- vcc_rtc: regulator@0 { +- regulator-name = "vcc_rtc"; +- regulator-always-on; +- }; +- +- vcc_io: regulator@1 { +- regulator-name = "vcc_io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_arm: regulator@2 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc_ddr: regulator@3 { +- regulator-name = "vcc_ddr"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc18: regulator@5 { +- regulator-name = "vcc18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vdd_11: regulator@6 { +- regulator-name = "vdd_11"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- vcc_25: regulator@7 { +- regulator-name = "vcc_25"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- vccio_wl: regulator@8 { +- regulator-name = "vccio_wl"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vcc25_hdmi: regulator@9 { +- regulator-name = "vcc25_hdmi"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- }; +- +- vcca_33: regulator@10 { +- regulator-name = "vcca_33"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vcc_rmii: regulator@11 { +- regulator-name = "vcc_rmii"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vcc28_cif: regulator@12 { +- regulator-name = "vcc28_cif"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- }; +- }; +-}; +- +-#include "tps65910.dtsi" +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&mmc0 { +- bus-width = <4>; +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; +- vmmc-supply = <&vcc_sd>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- status = "okay"; +-}; +- +-&mmc1 { +- bus-width = <4>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>; +- vmmc-supply = <&vccio_wl>; +- status = "okay"; +-}; +- +-&pinctrl { +- pcfg_output_high: pcfg-output-high { +- output-high; +- }; +- +- ak8963 { +- comp_int: comp-int { +- rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_default>; +- }; +- }; +- +- emac { +- rmii_rst: rmii-rst { +- rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- }; +- +- ir { +- ir_int: ir-int { +- rockchip,pins = <6 RK_PA1 RK_FUNC_GPIO &pcfg_pull_default>; +- }; +- }; +- +- keys { +- pwr_key: pwr-key { +- rockchip,pins = <6 RK_PA2 RK_FUNC_GPIO &pcfg_pull_default>; +- }; +- }; +- +- mma8452 { +- gsensor_int: gsensor-int { +- rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_default>; +- }; +- }; +- +- mmc { +- sdmmc_pwr: sdmmc-pwr { +- rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_default>; +- }; +- }; +- +- usb_host { +- host_drv: host-drv { +- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_default>; +- }; +- +- hub_rst: hub-rst { +- rockchip,pins = <1 RK_PD7 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- +- sata_pwr: sata-pwr { +- rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_default>; +- }; +- +- sata_reset: sata-reset { +- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- }; +- +- usb_otg { +- otg_drv: otg-drv { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_default>; +- }; +- }; +- +- tps { +- pmic_int: pmic-int { +- rockchip,pins = <6 RK_PA4 RK_FUNC_GPIO &pcfg_pull_default>; +- }; +- +- pwr_hold: pwr-hold { +- rockchip,pins = <6 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- }; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&pwm3 { +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vcc_25>; +- status = "okay"; +-}; +- +-&spi0 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_xfer>, <&uart3_cts>, <&uart3_rts>; +- status = "okay"; +-}; +- +-&usb_host { +- pinctrl-names = "default"; +- pinctrl-0 = <&hub_rst>, <&sata_reset>; +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3066a.dtsi b/scripts/dtc/include-prefixes/arm/rk3066a.dtsi +deleted file mode 100644 +index ae4055428c5e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3066a.dtsi ++++ /dev/null +@@ -1,881 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2013 MundoReader S.L. +- * Author: Heiko Stuebner +- */ +- +-#include +-#include +-#include +-#include +-#include "rk3xxx.dtsi" +- +-/ { +- compatible = "rockchip,rk3066a"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "rockchip,rk3066-smp"; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- reg = <0x0>; +- operating-points = < +- /* kHz uV */ +- 1416000 1300000 +- 1200000 1175000 +- 1008000 1125000 +- 816000 1125000 +- 600000 1100000 +- 504000 1100000 +- 312000 1075000 +- >; +- clock-latency = <40000>; +- clocks = <&cru ARMCLK>; +- }; +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- reg = <0x1>; +- }; +- }; +- +- display-subsystem { +- compatible = "rockchip,display-subsystem"; +- ports = <&vop0_out>, <&vop1_out>; +- }; +- +- sram: sram@10080000 { +- compatible = "mmio-sram"; +- reg = <0x10080000 0x10000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x10080000 0x10000>; +- +- smp-sram@0 { +- compatible = "rockchip,rk3066-smp-sram"; +- reg = <0x0 0x50>; +- }; +- }; +- +- vop0: vop@1010c000 { +- compatible = "rockchip,rk3066-vop"; +- reg = <0x1010c000 0x19c>; +- interrupts = ; +- clocks = <&cru ACLK_LCDC0>, +- <&cru DCLK_LCDC0>, +- <&cru HCLK_LCDC0>; +- clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; +- power-domains = <&power RK3066_PD_VIO>; +- resets = <&cru SRST_LCDC0_AXI>, +- <&cru SRST_LCDC0_AHB>, +- <&cru SRST_LCDC0_DCLK>; +- reset-names = "axi", "ahb", "dclk"; +- status = "disabled"; +- +- vop0_out: port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- vop0_out_hdmi: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&hdmi_in_vop0>; +- }; +- }; +- }; +- +- vop1: vop@1010e000 { +- compatible = "rockchip,rk3066-vop"; +- reg = <0x1010e000 0x19c>; +- interrupts = ; +- clocks = <&cru ACLK_LCDC1>, +- <&cru DCLK_LCDC1>, +- <&cru HCLK_LCDC1>; +- clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; +- power-domains = <&power RK3066_PD_VIO>; +- resets = <&cru SRST_LCDC1_AXI>, +- <&cru SRST_LCDC1_AHB>, +- <&cru SRST_LCDC1_DCLK>; +- reset-names = "axi", "ahb", "dclk"; +- status = "disabled"; +- +- vop1_out: port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- vop1_out_hdmi: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&hdmi_in_vop1>; +- }; +- }; +- }; +- +- hdmi: hdmi@10116000 { +- compatible = "rockchip,rk3066-hdmi"; +- reg = <0x10116000 0x2000>; +- interrupts = ; +- clocks = <&cru HCLK_HDMI>; +- clock-names = "hclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; +- power-domains = <&power RK3066_PD_VIO>; +- rockchip,grf = <&grf>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- hdmi_in: port@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- hdmi_in_vop0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vop0_out_hdmi>; +- }; +- +- hdmi_in_vop1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vop1_out_hdmi>; +- }; +- }; +- +- hdmi_out: port@1 { +- reg = <1>; +- }; +- }; +- }; +- +- i2s0: i2s@10118000 { +- compatible = "rockchip,rk3066-i2s"; +- reg = <0x10118000 0x2000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s0_bus>; +- clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; +- clock-names = "i2s_clk", "i2s_hclk"; +- dmas = <&dmac1_s 4>, <&dmac1_s 5>; +- dma-names = "tx", "rx"; +- rockchip,playback-channels = <8>; +- rockchip,capture-channels = <2>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- i2s1: i2s@1011a000 { +- compatible = "rockchip,rk3066-i2s"; +- reg = <0x1011a000 0x2000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s1_bus>; +- clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; +- clock-names = "i2s_clk", "i2s_hclk"; +- dmas = <&dmac1_s 6>, <&dmac1_s 7>; +- dma-names = "tx", "rx"; +- rockchip,playback-channels = <2>; +- rockchip,capture-channels = <2>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- i2s2: i2s@1011c000 { +- compatible = "rockchip,rk3066-i2s"; +- reg = <0x1011c000 0x2000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s2_bus>; +- clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; +- clock-names = "i2s_clk", "i2s_hclk"; +- dmas = <&dmac1_s 9>, <&dmac1_s 10>; +- dma-names = "tx", "rx"; +- rockchip,playback-channels = <2>; +- rockchip,capture-channels = <2>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- cru: clock-controller@20000000 { +- compatible = "rockchip,rk3066a-cru"; +- reg = <0x20000000 0x1000>; +- rockchip,grf = <&grf>; +- +- #clock-cells = <1>; +- #reset-cells = <1>; +- assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, +- <&cru ACLK_CPU>, <&cru HCLK_CPU>, +- <&cru PCLK_CPU>, <&cru ACLK_PERI>, +- <&cru HCLK_PERI>, <&cru PCLK_PERI>; +- assigned-clock-rates = <400000000>, <594000000>, +- <300000000>, <150000000>, +- <75000000>, <300000000>, +- <150000000>, <75000000>; +- }; +- +- timer2: timer@2000e000 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2000e000 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; +- clock-names = "timer", "pclk"; +- }; +- +- efuse: efuse@20010000 { +- compatible = "rockchip,rk3066a-efuse"; +- reg = <0x20010000 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&cru PCLK_EFUSE>; +- clock-names = "pclk_efuse"; +- +- cpu_leakage: cpu_leakage@17 { +- reg = <0x17 0x1>; +- }; +- }; +- +- timer0: timer@20038000 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x20038000 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; +- clock-names = "timer", "pclk"; +- }; +- +- timer1: timer@2003a000 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x2003a000 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; +- clock-names = "timer", "pclk"; +- }; +- +- tsadc: tsadc@20060000 { +- compatible = "rockchip,rk3066-tsadc"; +- reg = <0x20060000 0x100>; +- clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; +- clock-names = "saradc", "apb_pclk"; +- interrupts = ; +- #io-channel-cells = <1>; +- resets = <&cru SRST_TSADC>; +- reset-names = "saradc-apb"; +- status = "disabled"; +- }; +- +- pinctrl: pinctrl { +- compatible = "rockchip,rk3066a-pinctrl"; +- rockchip,grf = <&grf>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gpio0: gpio0@20034000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x20034000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio1@2003c000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x2003c000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO1>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio2@2003e000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x2003e000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO2>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio3@20080000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x20080000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO3>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio4: gpio4@20084000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x20084000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO4>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio6: gpio6@2000a000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x2000a000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO6>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pcfg_pull_default: pcfg-pull-default { +- bias-pull-pin-default; +- }; +- +- pcfg_pull_none: pcfg-pull-none { +- bias-disable; +- }; +- +- emac { +- emac_xfer: emac-xfer { +- rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */ +- <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */ +- <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */ +- <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */ +- <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */ +- <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */ +- <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */ +- <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */ +- }; +- +- emac_mdio: emac-mdio { +- rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */ +- <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */ +- }; +- }; +- +- emmc { +- emmc_clk: emmc-clk { +- rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>; +- }; +- +- emmc_cmd: emmc-cmd { +- rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>; +- }; +- +- emmc_rst: emmc-rst { +- rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>; +- }; +- +- /* +- * The data pins are shared between nandc and emmc and +- * not accessible through pinctrl. Also they should've +- * been already set correctly by firmware, as +- * flash/emmc is the boot-device. +- */ +- }; +- +- hdmi { +- hdmi_hpd: hdmi-hpd { +- rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; +- }; +- +- hdmii2c_xfer: hdmii2c-xfer { +- rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, +- <0 RK_PA2 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c0 { +- i2c0_xfer: i2c0-xfer { +- rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>, +- <2 RK_PD5 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c1 { +- i2c1_xfer: i2c1-xfer { +- rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>, +- <2 RK_PD7 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c2 { +- i2c2_xfer: i2c2-xfer { +- rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>, +- <3 RK_PA1 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c3 { +- i2c3_xfer: i2c3-xfer { +- rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>, +- <3 RK_PA3 2 &pcfg_pull_none>; +- }; +- }; +- +- i2c4 { +- i2c4_xfer: i2c4-xfer { +- rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, +- <3 RK_PA5 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm0 { +- pwm0_out: pwm0-out { +- rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm1 { +- pwm1_out: pwm1-out { +- rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm2 { +- pwm2_out: pwm2-out { +- rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm3 { +- pwm3_out: pwm3-out { +- rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; +- }; +- }; +- +- spi0 { +- spi0_clk: spi0-clk { +- rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>; +- }; +- spi0_cs0: spi0-cs0 { +- rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>; +- }; +- spi0_tx: spi0-tx { +- rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>; +- }; +- spi0_rx: spi0-rx { +- rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>; +- }; +- spi0_cs1: spi0-cs1 { +- rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>; +- }; +- }; +- +- spi1 { +- spi1_clk: spi1-clk { +- rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>; +- }; +- spi1_cs0: spi1-cs0 { +- rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>; +- }; +- spi1_rx: spi1-rx { +- rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>; +- }; +- spi1_tx: spi1-tx { +- rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>; +- }; +- spi1_cs1: spi1-cs1 { +- rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>; +- }; +- }; +- +- uart0 { +- uart0_xfer: uart0-xfer { +- rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, +- <1 RK_PA1 1 &pcfg_pull_default>; +- }; +- +- uart0_cts: uart0-cts { +- rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>; +- }; +- +- uart0_rts: uart0-rts { +- rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>; +- }; +- }; +- +- uart1 { +- uart1_xfer: uart1-xfer { +- rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>, +- <1 RK_PA5 1 &pcfg_pull_default>; +- }; +- +- uart1_cts: uart1-cts { +- rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>; +- }; +- +- uart1_rts: uart1-rts { +- rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; +- }; +- }; +- +- uart2 { +- uart2_xfer: uart2-xfer { +- rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, +- <1 RK_PB1 1 &pcfg_pull_default>; +- }; +- /* no rts / cts for uart2 */ +- }; +- +- uart3 { +- uart3_xfer: uart3-xfer { +- rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>, +- <3 RK_PD4 1 &pcfg_pull_default>; +- }; +- +- uart3_cts: uart3-cts { +- rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>; +- }; +- +- uart3_rts: uart3-rts { +- rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>; +- }; +- }; +- +- sd0 { +- sd0_clk: sd0-clk { +- rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>; +- }; +- +- sd0_cmd: sd0-cmd { +- rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>; +- }; +- +- sd0_cd: sd0-cd { +- rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>; +- }; +- +- sd0_wp: sd0-wp { +- rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>; +- }; +- +- sd0_bus1: sd0-bus-width1 { +- rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>; +- }; +- +- sd0_bus4: sd0-bus-width4 { +- rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>, +- <3 RK_PB3 1 &pcfg_pull_default>, +- <3 RK_PB4 1 &pcfg_pull_default>, +- <3 RK_PB5 1 &pcfg_pull_default>; +- }; +- }; +- +- sd1 { +- sd1_clk: sd1-clk { +- rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>; +- }; +- +- sd1_cmd: sd1-cmd { +- rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>; +- }; +- +- sd1_cd: sd1-cd { +- rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>; +- }; +- +- sd1_wp: sd1-wp { +- rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>; +- }; +- +- sd1_bus1: sd1-bus-width1 { +- rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>; +- }; +- +- sd1_bus4: sd1-bus-width4 { +- rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>, +- <3 RK_PC2 1 &pcfg_pull_default>, +- <3 RK_PC3 1 &pcfg_pull_default>, +- <3 RK_PC4 1 &pcfg_pull_default>; +- }; +- }; +- +- i2s0 { +- i2s0_bus: i2s0-bus { +- rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>, +- <0 RK_PB0 1 &pcfg_pull_default>, +- <0 RK_PB1 1 &pcfg_pull_default>, +- <0 RK_PB2 1 &pcfg_pull_default>, +- <0 RK_PB3 1 &pcfg_pull_default>, +- <0 RK_PB4 1 &pcfg_pull_default>, +- <0 RK_PB5 1 &pcfg_pull_default>, +- <0 RK_PB6 1 &pcfg_pull_default>, +- <0 RK_PB7 1 &pcfg_pull_default>; +- }; +- }; +- +- i2s1 { +- i2s1_bus: i2s1-bus { +- rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, +- <0 RK_PC1 1 &pcfg_pull_default>, +- <0 RK_PC2 1 &pcfg_pull_default>, +- <0 RK_PC3 1 &pcfg_pull_default>, +- <0 RK_PC4 1 &pcfg_pull_default>, +- <0 RK_PC5 1 &pcfg_pull_default>; +- }; +- }; +- +- i2s2 { +- i2s2_bus: i2s2-bus { +- rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>, +- <0 RK_PD1 1 &pcfg_pull_default>, +- <0 RK_PD2 1 &pcfg_pull_default>, +- <0 RK_PD3 1 &pcfg_pull_default>, +- <0 RK_PD4 1 &pcfg_pull_default>, +- <0 RK_PD5 1 &pcfg_pull_default>; +- }; +- }; +- }; +-}; +- +-&gpu { +- compatible = "rockchip,rk3066-mali", "arm,mali-400"; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "gp", +- "gpmmu", +- "pp0", +- "ppmmu0", +- "pp1", +- "ppmmu1", +- "pp2", +- "ppmmu2", +- "pp3", +- "ppmmu3"; +- power-domains = <&power RK3066_PD_GPU>; +-}; +- +-&grf { +- compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd"; +- +- usbphy: usbphy { +- compatible = "rockchip,rk3066a-usb-phy", +- "rockchip,rk3288-usb-phy"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- usbphy0: usb-phy@17c { +- reg = <0x17c>; +- clocks = <&cru SCLK_OTGPHY0>; +- clock-names = "phyclk"; +- #clock-cells = <0>; +- #phy-cells = <0>; +- }; +- +- usbphy1: usb-phy@188 { +- reg = <0x188>; +- clocks = <&cru SCLK_OTGPHY1>; +- clock-names = "phyclk"; +- #clock-cells = <0>; +- #phy-cells = <0>; +- }; +- }; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_xfer>; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_xfer>; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_xfer>; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_xfer>; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_xfer>; +-}; +- +-&mmc0 { +- clock-frequency = <50000000>; +- dmas = <&dmac2 1>; +- dma-names = "rx-tx"; +- max-frequency = <50000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; +-}; +- +-&mmc1 { +- dmas = <&dmac2 3>; +- dma-names = "rx-tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; +-}; +- +-&emmc { +- dmas = <&dmac2 4>; +- dma-names = "rx-tx"; +-}; +- +-&pmu { +- power: power-controller { +- compatible = "rockchip,rk3066-power-controller"; +- #power-domain-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- power-domain@RK3066_PD_VIO { +- reg = ; +- clocks = <&cru ACLK_LCDC0>, +- <&cru ACLK_LCDC1>, +- <&cru DCLK_LCDC0>, +- <&cru DCLK_LCDC1>, +- <&cru HCLK_LCDC0>, +- <&cru HCLK_LCDC1>, +- <&cru SCLK_CIF1>, +- <&cru ACLK_CIF1>, +- <&cru HCLK_CIF1>, +- <&cru SCLK_CIF0>, +- <&cru ACLK_CIF0>, +- <&cru HCLK_CIF0>, +- <&cru HCLK_HDMI>, +- <&cru ACLK_IPP>, +- <&cru HCLK_IPP>, +- <&cru ACLK_RGA>, +- <&cru HCLK_RGA>; +- pm_qos = <&qos_lcdc0>, +- <&qos_lcdc1>, +- <&qos_cif0>, +- <&qos_cif1>, +- <&qos_ipp>, +- <&qos_rga>; +- #power-domain-cells = <0>; +- }; +- +- power-domain@RK3066_PD_VIDEO { +- reg = ; +- clocks = <&cru ACLK_VDPU>, +- <&cru ACLK_VEPU>, +- <&cru HCLK_VDPU>, +- <&cru HCLK_VEPU>; +- pm_qos = <&qos_vpu>; +- #power-domain-cells = <0>; +- }; +- +- power-domain@RK3066_PD_GPU { +- reg = ; +- clocks = <&cru ACLK_GPU>; +- pm_qos = <&qos_gpu>; +- #power-domain-cells = <0>; +- }; +- }; +-}; +- +-&pwm0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_out>; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm1_out>; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm2_out>; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm3_out>; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; +-}; +- +-&uart0 { +- compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; +- dmas = <&dmac1_s 0>, <&dmac1_s 1>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer>; +-}; +- +-&uart1 { +- compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; +- dmas = <&dmac1_s 2>, <&dmac1_s 3>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_xfer>; +-}; +- +-&uart2 { +- compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; +- dmas = <&dmac2 6>, <&dmac2 7>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_xfer>; +-}; +- +-&uart3 { +- compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; +- dmas = <&dmac2 8>, <&dmac2 9>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_xfer>; +-}; +- +-&vpu { +- power-domains = <&power RK3066_PD_VIDEO>; +-}; +- +-&wdt { +- compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; +-}; +- +-&emac { +- compatible = "rockchip,rk3066-emac"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3188-bqedison2qc.dts b/scripts/dtc/include-prefixes/arm/rk3188-bqedison2qc.dts +deleted file mode 100644 +index 85d3fce0142f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3188-bqedison2qc.dts ++++ /dev/null +@@ -1,738 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 MundoReader S.L. +- * Author: Heiko Stuebner +- */ +- +-/dts-v1/; +-#include +-#include +-#include "rk3188.dtsi" +- +-/ { +- model = "BQ Edison2 Quad-Core"; +- compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188"; +- +- aliases { +- mmc0 = &mmc0; +- mmc1 = &mmc1; +- mmc2 = &emmc; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x80000000>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- power-supply = <&vsys>; +- pwms = <&pwm1 0 25000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_key &usb_int>; +- +- power { +- gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "GPIO Key Power"; +- linux,input-type = <1>; +- debounce-interval = <100>; +- wakeup-source; +- }; +- +- wake_on_usb: wake-on-usb { +- label = "Wake-on-USB"; +- gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- gpio-poweroff { +- compatible = "gpio-poweroff"; +- gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_hold>; +- /* only drive the pin low until device is off */ +- active-delay-ms = <3000>; +- }; +- +- lvds-encoder { +- compatible = "ti,sn75lvds83", "lvds-encoder"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- lvds_in_vop0: endpoint { +- remote-endpoint = <&vop0_out_lvds>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lvds_out_panel: endpoint { +- remote-endpoint = <&panel_in_lvds>; +- }; +- }; +- }; +- }; +- +- panel { +- compatible = "innolux,ee101ia-01d", "panel-lvds"; +- backlight = <&backlight>; +- +- /* pin LCD_CS, Nshtdn input of lvds-encoder */ +- enable-gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_cs>; +- power-supply = <&vcc_lcd>; +- +- data-mapping = "vesa-24"; +- height-mm = <163>; +- width-mm = <261>; +- +- panel-timing { +- clock-frequency = <72000000>; +- hactive = <1280>; +- vactive = <800>; +- hback-porch = <160>; +- hfront-porch = <16>; +- hsync-len = <10>; +- vback-porch = <23>; +- vfront-porch = <12>; +- vsync-len = <3>; +- }; +- +- port { +- panel_in_lvds: endpoint { +- remote-endpoint = <&lvds_out_panel>; +- }; +- }; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&hym8563>; +- clock-names = "ext_clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_reg_on>; +- reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>; +- }; +- +- avdd_cif: cif-avdd-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "avdd-cif"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cif_avdd_en>; +- startup-delay-us = <100000>; +- vin-supply = <&vcc28_cif>; +- }; +- +- vcc_5v: vcc-5v-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc-5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&v5_drv>; +- vin-supply = <&vsys>; +- }; +- +- vcc_lcd: lcd-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc-lcd"; +- gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_en>; +- startup-delay-us = <50000>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_otg: usb-otg-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc-otg"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&otg_drv>; +- startup-delay-us = <100000>; +- vin-supply = <&vcc_5v>; +- }; +- +- vcc_sd: sdmmc-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc-sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_pwr>; +- startup-delay-us = <100000>; +- vin-supply = <&vcc_io>; +- }; +- +- vccq_emmc: emmc-vccq-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vccq-emmc"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- vin-supply = <&vcc_io>; +- }; +- +- /* supplied from the bq24196 */ +- vsys: vsys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vsys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cru { +- assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, +- <&cru ACLK_CPU>, +- <&cru HCLK_CPU>, <&cru PCLK_CPU>, +- <&cru ACLK_PERI>, <&cru HCLK_PERI>, +- <&cru PCLK_PERI>; +- assigned-clock-rates = <594000000>, <504000000>, +- <300000000>, +- <150000000>, <75000000>, +- <300000000>, <150000000>, +- <75000000>; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd>; +- vmmc-supply = <&vcc_io>; +- vqmmc-supply = <&vccq_emmc>; +- status = "okay"; +-}; +- +-&gpu { +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- status = "okay"; +- +- lis3de: accelerometer@29 { +- compatible = "st,lis3de"; +- reg = <0x29>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&gsensor_int>; +- rotation-matrix = "1", "0", "0", +- "0", "-1", "0", +- "0", "0", "1"; +- vdd-supply = <&vcc_io>; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- status = "okay"; +- +- tmp108@48 { +- compatible = "ti,tmp108"; +- reg = <0x48>; +- interrupt-parent = <&gpio1>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&tmp_alrt>; +- #thermal-sensor-cells = <0>; +- }; +- +- hym8563: rtc@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&rtc_int>; +- #clock-cells = <0>; +- clock-output-names = "xin32k"; +- }; +- +- bat: battery@55 { +- compatible = "ti,bq27541"; +- reg = <0x55>; +- power-supplies = <&bq24196>; +- }; +- +- act8846: pmic@5a { +- compatible = "active-semi,act8846"; +- reg = <0x5a>; +- pinctrl-names = "default"; +- pinctrl-0 = <&dvs0_ctl &pmic_int>; +- +- vp1-supply = <&vsys>; +- vp2-supply = <&vsys>; +- vp3-supply = <&vsys>; +- vp4-supply = <&vsys>; +- inl1-supply = <&vcc_io>; +- inl2-supply = <&vsys>; +- inl3-supply = <&vsys>; +- +- regulators { +- vcc_ddr: REG1 { +- regulator-name = "VCC_DDR"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vdd_log: REG2 { +- regulator-name = "VDD_LOG"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vdd_arm: REG3 { +- regulator-name = "VDD_ARM"; +- regulator-min-microvolt = <875000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- }; +- +- vcc_io: vcc_hdmi: REG4 { +- regulator-name = "VCC_IO"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- +- vdd_10: REG5 { +- regulator-name = "VDD_10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- vdd_12: REG6 { +- regulator-name = "VDD_12"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vcc18_cif: REG7 { +- regulator-name = "VCC18_CIF"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcca_33: REG8 { +- regulator-name = "VCCA_33"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vcc_tp: REG9 { +- regulator-name = "VCC_TP"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vccio_wl: REG10 { +- regulator-name = "VCCIO_WL"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- vcc_18: REG11 { +- regulator-name = "VCC_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcc28_cif: REG12 { +- regulator-name = "VCC28_CIF"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- }; +- }; +- +- bq24196: charger@6b { +- compatible = "ti,bq24196"; +- reg = <0x6b>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&charger_int &chg_ctl &otg_en>; +- ti,system-minimum-microvolt = <3200000>; +- monitored-battery = <&bat>; +- omit-battery-class; +- +- usb_otg_vbus: usb-otg-vbus { }; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- status = "okay"; +- +- ft5606: touchscreen@3e { +- compatible = "edt,edt-ft5506"; +- reg = <0x3e>; +- interrupt-parent = <&gpio1>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&tp_int &tp_rst>; +- reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; +- touchscreen-inverted-y; +- /* hw ts resolution does not match display */ +- touchscreen-size-y = <1024>; +- touchscreen-size-x = <768>; +- touchscreen-swapped-x-y; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +- status = "okay"; +-}; +- +-&i2c4 { +- clock-frequency = <400000>; +- status = "okay"; +- +- rt5616: codec@1b { +- compatible = "realtek,rt5616"; +- reg = <0x1b>; +- clocks = <&cru SCLK_I2S0>; +- clock-names = "mclk"; +- #sound-dai-cells = <0>; +- }; +-}; +- +-&i2s0 { +- status = "okay"; +-}; +- +-&mmc0 { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; +- vmmc-supply = <&vcc_sd>; +- status = "okay"; +-}; +- +-&mmc1 { +- bus-width = <4>; +- cap-sd-highspeed; +- keep-power-in-suspend; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>; +- vqmmc-supply = <&vccio_wl>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&gpio3>; +- interrupts = ; +- interrupt-names = "host-wake"; +- brcm,drive-strength = <5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_host_wake>; +- }; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&pinctrl { +- pcfg_output_high: pcfg-output-high { +- output-high; +- }; +- +- pcfg_output_low: pcfg-output-low { +- output-low; +- }; +- +- act8846 { +- dvs0_ctl: dvs0-ctl { +- rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- +- pmic_int: pmic-int { +- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- bq24196 { +- charger_int: charger-int { +- rockchip,pins = <0 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- /* pin hog to make it select usb profile */ +- chg_ctl: chg-ctl { +- rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- +- /* low: charging, high: complete, fault: blinking */ +- chg_det: chg-det { +- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- /* charging enabled when pin low and register set */ +- chg_en: chg-en { +- rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- +- /* bq29196 powergood (when low) signal */ +- dc_det: dc-det { +- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- /* wire bq24196 otg pin to high, to enable 500mA charging */ +- otg_en: otg-en { +- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- }; +- +- camera { +- cif0_pdn: cif0-pdn { +- rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- cif1_pdn: cif1-pdn { +- rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- cif_avdd_en: cif-avdd-en { +- rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- display { +- lcd_cs: lcd-cs { +- rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- lcd_en: lcd-en { +- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- ft5606 { +- tp_int: tp-int { +- rockchip,pins = <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- tp_rst: tp-rst { +- rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- hdmi { +- hdmi_int: hdmi-int { +- rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- hdmi_rst: hdmi-rst { +- rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- hym8563 { +- rtc_int: rtc-int { +- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- keys { +- pwr_hold: pwr-hold { +- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- pwr_key: pwr-key { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- lis3de { +- gsensor_int: gsensor-int { +- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- mmc { +- sdmmc_pwr: sdmmc-pwr { +- rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- tmp108 { +- tmp_alrt: tmp-alrt { +- rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb { +- v5_drv: v5-drv { +- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- otg_drv: otg-drv { +- rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- usb_int: usb-int { +- rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- rk903 { +- bt_host_wake: bt-host-wake { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- bt_reg_on: bt-reg-on { +- rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- /* pin hog to pull the reset high */ +- bt_rst: bt-rst { +- rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- +- bt_wake: bt-wake { +- rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- wifi_host_wake: wifi-host-wake { +- rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- wifi_reg_on: wifi-reg-on { +- rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&saradc { +- vref-supply = <&vcc_18>; +- status = "okay"; +-}; +- +-&spdif { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- max-speed = <2000000>; +- device-wakeup-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_host_wake &bt_reg_on &bt_rst &bt_wake>; +- }; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>; +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&usb_host { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +- +-&vop0 { +- status = "okay"; +-}; +- +-&vop0_out { +- vop0_out_lvds: endpoint { +- remote-endpoint = <&lvds_in_vop0>; +- }; +-}; +- +-&vop1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcdc1_dclk &lcdc1_den &lcdc1_hsync +- &lcdc1_vsync &lcdc1_rgb24>; +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3188-px3-evb.dts b/scripts/dtc/include-prefixes/arm/rk3188-px3-evb.dts +deleted file mode 100644 +index 39c60426c9c9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3188-px3-evb.dts ++++ /dev/null +@@ -1,305 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Andy Yan +- */ +- +-/dts-v1/; +-#include +-#include "rk3188.dtsi" +- +-/ { +- model = "Rockchip PX3-EVB"; +- compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188"; +- +- aliases { +- mmc0 = &mmc0; +- mmc1 = &emmc; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- memory@60000000 { +- reg = <0x60000000 0x80000000>; +- device_type = "memory"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- +- power { +- gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "GPIO Key Power"; +- linux,input-type = <1>; +- wakeup-source; +- debounce-interval = <100>; +- }; +- }; +- +- vcc_sys: vsys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vsys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- accelerometer@18 { +- compatible = "bosch,bma250"; +- reg = <0x18>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- rk808: pmic@1c { +- compatible = "rockchip,rk818"; +- reg = <0x1c>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- rockchip,system-power-controller; +- wakeup-source; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc6-supply = <&vcc_sys>; +- vcc7-supply = <&vcc_sys>; +- vcc8-supply = <&vcc_io>; +- vcc9-supply = <&vcc_io>; +- +- regulators { +- vdd_cpu: DCDC_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-name = "vdd_arm"; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: DCDC_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-name = "vdd_gpu"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc_ddr"; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_io: DCDC_REG4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc_io"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_cif: LDO_REG1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc_cif"; +- }; +- +- vcc_jetta33: LDO_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc_jetta33"; +- }; +- +- vdd_10: LDO_REG3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-name = "vdd_10"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- lvds_12: LDO_REG4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "lvds_12"; +- }; +- +- lvds_25: LDO_REG5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "lvds_25"; +- }; +- +- cif_18: LDO_REG6 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-name = "cif_18"; +- }; +- +- vcc_sd: LDO_REG7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc_sd"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- wl_18: LDO_REG8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "wl_18"; +- }; +- +- lcd_33: SWITCH_REG1 { +- regulator-name = "lcd_33"; +- }; +- }; +- }; +- +-}; +- +-&i2c2 { +- gsl1680: touchscreen@40 { +- compatible = "silead,gsl1680"; +- reg = <0x40>; +- interrupt-parent = <&gpio1>; +- interrupts = ; +- power-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; +- touchscreen-size-x = <800>; +- touchscreen-size-y = <1280>; +- silead,max-fingers = <5>; +- }; +-}; +- +-&mmc0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; +- vmmc-supply = <&vcc_sd>; +- +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- disable-wp; +-}; +- +-&pinctrl { +- pcfg_output_low: pcfg-output-low { +- output-low; +- }; +- +- usb { +- host_vbus_drv: host-vbus-drv { +- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- otg_vbus_drv: otg-vbus-drv { +- rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&pwm3 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&usb_host { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3188-radxarock.dts b/scripts/dtc/include-prefixes/arm/rk3188-radxarock.dts +deleted file mode 100644 +index 36c0945f43b2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3188-radxarock.dts ++++ /dev/null +@@ -1,386 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2013 Heiko Stuebner +- */ +- +-/dts-v1/; +-#include +-#include "rk3188.dtsi" +- +-/ { +- model = "Radxa Rock"; +- compatible = "radxa,rock", "rockchip,rk3188"; +- +- aliases { +- mmc0 = &mmc0; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x80000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- +- power { +- gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "GPIO Key Power"; +- linux,input-type = <1>; +- wakeup-source; +- debounce-interval = <100>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- green_led: led-0 { +- label = "rock:green:user1"; +- gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- blue_led: led-1 { +- label = "rock:blue:user2"; +- gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- sleep_led: led-2 { +- label = "rock:red:power"; +- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "SPDIF"; +- +- simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ +- cpu { sound-dai = <&spdif>; }; +- codec { sound-dai = <&spdif_out>; }; +- }; +- }; +- +- spdif_out: spdif-out { +- compatible = "linux,spdif-dit"; +- #sound-dai-cells = <0>; +- }; +- +- ir_recv: gpio-ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ir_recv_pin>; +- }; +- +- vcc_otg: usb-otg-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&otg_vbus_drv>; +- regulator-name = "otg-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc_sd0: sdmmc-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "sdmmc-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_pwr>; +- startup-delay-us = <100000>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_host: usb-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&host_vbus_drv>; +- regulator-name = "host-pwr"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vsys: vsys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vsys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- }; +-}; +- +-&emac { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; +- +- phy = <&phy0>; +- phy-supply = <&vcc_rmii>; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- interrupt-parent = <&gpio3>; +- interrupts = ; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&gpu { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- rtc@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&rtc_int>; +- #clock-cells = <0>; +- clock-output-names = "xin32k"; +- }; +- +- act8846: act8846@5a { +- compatible = "active-semi,act8846"; +- reg = <0x5a>; +- status = "okay"; +- system-power-controller; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&act8846_dvs0_ctl>; +- +- vp1-supply = <&vsys>; +- vp2-supply = <&vsys>; +- vp3-supply = <&vsys>; +- vp4-supply = <&vsys>; +- inl1-supply = <&vcc_io>; +- inl2-supply = <&vsys>; +- inl3-supply = <&vsys>; +- +- regulators { +- vcc_ddr: REG1 { +- regulator-name = "VCC_DDR"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vdd_log: REG2 { +- regulator-name = "VDD_LOG"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- vdd_arm: REG3 { +- regulator-name = "VDD_ARM"; +- regulator-min-microvolt = <875000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- }; +- +- vcc_io: REG4 { +- regulator-name = "VCC_IO"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_10: REG5 { +- regulator-name = "VDD_10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- vdd_hdmi: REG6 { +- regulator-name = "VDD_HDMI"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- +- vcc18: REG7 { +- regulator-name = "VCC_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcca_33: REG8 { +- regulator-name = "VCCA_33"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vcc_rmii: REG9 { +- regulator-name = "VCC_RMII"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vccio_wl: REG10 { +- regulator-name = "VCCIO_WL"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vcc_18: REG11 { +- regulator-name = "VCC18_IO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcc28: REG12 { +- regulator-name = "VCC_28"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&mmc0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; +- vmmc-supply = <&vcc_sd0>; +- +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- disable-wp; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&pwm3 { +- status = "okay"; +-}; +- +-&pinctrl { +- pcfg_output_low: pcfg-output-low { +- output-low; +- }; +- +- act8846 { +- act8846_dvs0_ctl: act8846-dvs0-ctl { +- rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- }; +- +- hym8563 { +- rtc_int: rtc-int { +- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- lan8720a { +- phy_int: phy-int { +- rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- ir-receiver { +- ir_recv_pin: ir-recv-pin { +- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sd0 { +- sdmmc_pwr: sdmmc-pwr { +- rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb { +- host_vbus_drv: host-vbus-drv { +- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- otg_vbus_drv: otg-vbus-drv { +- rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&spdif { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&usb_host { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3188.dtsi b/scripts/dtc/include-prefixes/arm/rk3188.dtsi +deleted file mode 100644 +index 2c606494b78c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3188.dtsi ++++ /dev/null +@@ -1,816 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2013 MundoReader S.L. +- * Author: Heiko Stuebner +- */ +- +-#include +-#include +-#include +-#include +-#include "rk3xxx.dtsi" +- +-/ { +- compatible = "rockchip,rk3188"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "rockchip,rk3066-smp"; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- reg = <0x0>; +- clock-latency = <40000>; +- clocks = <&cru ARMCLK>; +- operating-points-v2 = <&cpu0_opp_table>; +- resets = <&cru SRST_CORE0>; +- }; +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- reg = <0x1>; +- operating-points-v2 = <&cpu0_opp_table>; +- resets = <&cru SRST_CORE1>; +- }; +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- reg = <0x2>; +- operating-points-v2 = <&cpu0_opp_table>; +- resets = <&cru SRST_CORE2>; +- }; +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- next-level-cache = <&L2>; +- reg = <0x3>; +- operating-points-v2 = <&cpu0_opp_table>; +- resets = <&cru SRST_CORE3>; +- }; +- }; +- +- cpu0_opp_table: opp_table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-312000000 { +- opp-hz = /bits/ 64 <312000000>; +- opp-microvolt = <875000>; +- clock-latency-ns = <40000>; +- }; +- opp-504000000 { +- opp-hz = /bits/ 64 <504000000>; +- opp-microvolt = <925000>; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <950000>; +- opp-suspend; +- }; +- opp-816000000 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <975000>; +- }; +- opp-1008000000 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <1075000>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <1150000>; +- }; +- opp-1416000000 { +- opp-hz = /bits/ 64 <1416000000>; +- opp-microvolt = <1250000>; +- }; +- opp-1608000000 { +- opp-hz = /bits/ 64 <1608000000>; +- opp-microvolt = <1350000>; +- }; +- }; +- +- display-subsystem { +- compatible = "rockchip,display-subsystem"; +- ports = <&vop0_out>, <&vop1_out>; +- }; +- +- sram: sram@10080000 { +- compatible = "mmio-sram"; +- reg = <0x10080000 0x8000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x10080000 0x8000>; +- +- smp-sram@0 { +- compatible = "rockchip,rk3066-smp-sram"; +- reg = <0x0 0x50>; +- }; +- }; +- +- vop0: vop@1010c000 { +- compatible = "rockchip,rk3188-vop"; +- reg = <0x1010c000 0x1000>; +- interrupts = ; +- clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>; +- clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; +- power-domains = <&power RK3188_PD_VIO>; +- resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; +- reset-names = "axi", "ahb", "dclk"; +- status = "disabled"; +- +- vop0_out: port { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- vop1: vop@1010e000 { +- compatible = "rockchip,rk3188-vop"; +- reg = <0x1010e000 0x1000>; +- interrupts = ; +- clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>; +- clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; +- power-domains = <&power RK3188_PD_VIO>; +- resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; +- reset-names = "axi", "ahb", "dclk"; +- status = "disabled"; +- +- vop1_out: port { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- timer3: timer@2000e000 { +- compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; +- reg = <0x2000e000 0x20>; +- interrupts = ; +- clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>; +- clock-names = "pclk", "timer"; +- }; +- +- timer6: timer@200380a0 { +- compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; +- reg = <0x200380a0 0x20>; +- interrupts = ; +- clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>; +- clock-names = "pclk", "timer"; +- }; +- +- i2s0: i2s@1011a000 { +- compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; +- reg = <0x1011a000 0x2000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s0_bus>; +- clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; +- clock-names = "i2s_clk", "i2s_hclk"; +- dmas = <&dmac1_s 6>, <&dmac1_s 7>; +- dma-names = "tx", "rx"; +- rockchip,playback-channels = <2>; +- rockchip,capture-channels = <2>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- spdif: sound@1011e000 { +- compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; +- reg = <0x1011e000 0x2000>; +- #sound-dai-cells = <0>; +- clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; +- clock-names = "mclk", "hclk"; +- dmas = <&dmac1_s 8>; +- dma-names = "tx"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&spdif_tx>; +- status = "disabled"; +- }; +- +- cru: clock-controller@20000000 { +- compatible = "rockchip,rk3188-cru"; +- reg = <0x20000000 0x1000>; +- rockchip,grf = <&grf>; +- +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- efuse: efuse@20010000 { +- compatible = "rockchip,rk3188-efuse"; +- reg = <0x20010000 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&cru PCLK_EFUSE>; +- clock-names = "pclk_efuse"; +- +- cpu_leakage: cpu_leakage@17 { +- reg = <0x17 0x1>; +- }; +- }; +- +- pinctrl: pinctrl { +- compatible = "rockchip,rk3188-pinctrl"; +- rockchip,grf = <&grf>; +- rockchip,pmu = <&pmu>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gpio0: gpio0@2000a000 { +- compatible = "rockchip,rk3188-gpio-bank0"; +- reg = <0x2000a000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio1@2003c000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x2003c000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO1>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio2@2003e000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x2003e000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO2>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio3@20080000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x20080000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO3>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pcfg_pull_up: pcfg-pull-up { +- bias-pull-up; +- }; +- +- pcfg_pull_down: pcfg-pull-down { +- bias-pull-down; +- }; +- +- pcfg_pull_none: pcfg-pull-none { +- bias-disable; +- }; +- +- emmc { +- emmc_clk: emmc-clk { +- rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; +- }; +- +- emmc_cmd: emmc-cmd { +- rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>; +- }; +- +- emmc_rst: emmc-rst { +- rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>; +- }; +- +- /* +- * The data pins are shared between nandc and emmc and +- * not accessible through pinctrl. Also they should've +- * been already set correctly by firmware, as +- * flash/emmc is the boot-device. +- */ +- }; +- +- emac { +- emac_xfer: emac-xfer { +- rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */ +- <3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */ +- <3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */ +- <3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */ +- <3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */ +- <3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */ +- <3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */ +- <3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */ +- }; +- +- emac_mdio: emac-mdio { +- rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, +- <3 RK_PD1 2 &pcfg_pull_none>; +- }; +- }; +- +- i2c0 { +- i2c0_xfer: i2c0-xfer { +- rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, +- <1 RK_PD1 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c1 { +- i2c1_xfer: i2c1-xfer { +- rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>, +- <1 RK_PD3 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c2 { +- i2c2_xfer: i2c2-xfer { +- rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>, +- <1 RK_PD5 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c3 { +- i2c3_xfer: i2c3-xfer { +- rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>, +- <3 RK_PB7 2 &pcfg_pull_none>; +- }; +- }; +- +- i2c4 { +- i2c4_xfer: i2c4-xfer { +- rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>, +- <1 RK_PD7 1 &pcfg_pull_none>; +- }; +- }; +- +- lcdc1 { +- lcdc1_dclk: lcdc1-dclk { +- rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>; +- }; +- +- lcdc1_den: lcdc1-den { +- rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>; +- }; +- +- lcdc1_hsync: lcdc1-hsync { +- rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; +- }; +- +- lcdc1_vsync: lcdc1-vsync { +- rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; +- }; +- +- lcdc1_rgb24: ldcd1-rgb24 { +- rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, +- <2 RK_PA1 1 &pcfg_pull_none>, +- <2 RK_PA2 1 &pcfg_pull_none>, +- <2 RK_PA3 1 &pcfg_pull_none>, +- <2 RK_PA4 1 &pcfg_pull_none>, +- <2 RK_PA5 1 &pcfg_pull_none>, +- <2 RK_PA6 1 &pcfg_pull_none>, +- <2 RK_PA7 1 &pcfg_pull_none>, +- <2 RK_PB0 1 &pcfg_pull_none>, +- <2 RK_PB1 1 &pcfg_pull_none>, +- <2 RK_PB2 1 &pcfg_pull_none>, +- <2 RK_PB3 1 &pcfg_pull_none>, +- <2 RK_PB4 1 &pcfg_pull_none>, +- <2 RK_PB5 1 &pcfg_pull_none>, +- <2 RK_PB6 1 &pcfg_pull_none>, +- <2 RK_PB7 1 &pcfg_pull_none>, +- <2 RK_PC0 1 &pcfg_pull_none>, +- <2 RK_PC1 1 &pcfg_pull_none>, +- <2 RK_PC2 1 &pcfg_pull_none>, +- <2 RK_PC3 1 &pcfg_pull_none>, +- <2 RK_PC4 1 &pcfg_pull_none>, +- <2 RK_PC5 1 &pcfg_pull_none>, +- <2 RK_PC6 1 &pcfg_pull_none>, +- <2 RK_PC7 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm0 { +- pwm0_out: pwm0-out { +- rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm1 { +- pwm1_out: pwm1-out { +- rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm2 { +- pwm2_out: pwm2-out { +- rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm3 { +- pwm3_out: pwm3-out { +- rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>; +- }; +- }; +- +- spi0 { +- spi0_clk: spi0-clk { +- rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>; +- }; +- spi0_cs0: spi0-cs0 { +- rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>; +- }; +- spi0_tx: spi0-tx { +- rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>; +- }; +- spi0_rx: spi0-rx { +- rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>; +- }; +- spi0_cs1: spi0-cs1 { +- rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>; +- }; +- }; +- +- spi1 { +- spi1_clk: spi1-clk { +- rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>; +- }; +- spi1_cs0: spi1-cs0 { +- rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>; +- }; +- spi1_rx: spi1-rx { +- rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>; +- }; +- spi1_tx: spi1-tx { +- rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>; +- }; +- spi1_cs1: spi1-cs1 { +- rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; +- }; +- }; +- +- uart0 { +- uart0_xfer: uart0-xfer { +- rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>, +- <1 RK_PA1 1 &pcfg_pull_none>; +- }; +- +- uart0_cts: uart0-cts { +- rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>; +- }; +- +- uart0_rts: uart0-rts { +- rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>; +- }; +- }; +- +- uart1 { +- uart1_xfer: uart1-xfer { +- rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>, +- <1 RK_PA5 1 &pcfg_pull_none>; +- }; +- +- uart1_cts: uart1-cts { +- rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; +- }; +- +- uart1_rts: uart1-rts { +- rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>; +- }; +- }; +- +- uart2 { +- uart2_xfer: uart2-xfer { +- rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>, +- <1 RK_PB1 1 &pcfg_pull_none>; +- }; +- /* no rts / cts for uart2 */ +- }; +- +- uart3 { +- uart3_xfer: uart3-xfer { +- rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>, +- <1 RK_PB3 1 &pcfg_pull_none>; +- }; +- +- uart3_cts: uart3-cts { +- rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>; +- }; +- +- uart3_rts: uart3-rts { +- rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>; +- }; +- }; +- +- sd0 { +- sd0_clk: sd0-clk { +- rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>; +- }; +- +- sd0_cmd: sd0-cmd { +- rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; +- }; +- +- sd0_cd: sd0-cd { +- rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>; +- }; +- +- sd0_wp: sd0-wp { +- rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>; +- }; +- +- sd0_pwr: sd0-pwr { +- rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; +- }; +- +- sd0_bus1: sd0-bus-width1 { +- rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; +- }; +- +- sd0_bus4: sd0-bus-width4 { +- rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, +- <3 RK_PA5 1 &pcfg_pull_none>, +- <3 RK_PA6 1 &pcfg_pull_none>, +- <3 RK_PA7 1 &pcfg_pull_none>; +- }; +- }; +- +- sd1 { +- sd1_clk: sd1-clk { +- rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; +- }; +- +- sd1_cmd: sd1-cmd { +- rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>; +- }; +- +- sd1_cd: sd1-cd { +- rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>; +- }; +- +- sd1_wp: sd1-wp { +- rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>; +- }; +- +- sd1_bus1: sd1-bus-width1 { +- rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>; +- }; +- +- sd1_bus4: sd1-bus-width4 { +- rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>, +- <3 RK_PC2 1 &pcfg_pull_none>, +- <3 RK_PC3 1 &pcfg_pull_none>, +- <3 RK_PC4 1 &pcfg_pull_none>; +- }; +- }; +- +- i2s0 { +- i2s0_bus: i2s0-bus { +- rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, +- <1 RK_PC1 1 &pcfg_pull_none>, +- <1 RK_PC2 1 &pcfg_pull_none>, +- <1 RK_PC3 1 &pcfg_pull_none>, +- <1 RK_PC4 1 &pcfg_pull_none>, +- <1 RK_PC5 1 &pcfg_pull_none>; +- }; +- }; +- +- spdif { +- spdif_tx: spdif-tx { +- rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>; +- }; +- }; +- }; +-}; +- +-&emac { +- compatible = "rockchip,rk3188-emac"; +-}; +- +-&global_timer { +- interrupts = ; +- status = "disabled"; +-}; +- +-&local_timer { +- interrupts = ; +-}; +- +-&gpu { +- compatible = "rockchip,rk3188-mali", "arm,mali-400"; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "gp", +- "gpmmu", +- "pp0", +- "ppmmu0", +- "pp1", +- "ppmmu1", +- "pp2", +- "ppmmu2", +- "pp3", +- "ppmmu3"; +- power-domains = <&power RK3188_PD_GPU>; +-}; +- +-&grf { +- compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd"; +- +- io_domains: io-domains { +- compatible = "rockchip,rk3188-io-voltage-domain"; +- status = "disabled"; +- }; +- +- usbphy: usbphy { +- compatible = "rockchip,rk3188-usb-phy", +- "rockchip,rk3288-usb-phy"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- usbphy0: usb-phy@10c { +- reg = <0x10c>; +- clocks = <&cru SCLK_OTGPHY0>; +- clock-names = "phyclk"; +- #clock-cells = <0>; +- #phy-cells = <0>; +- }; +- +- usbphy1: usb-phy@11c { +- reg = <0x11c>; +- clocks = <&cru SCLK_OTGPHY1>; +- clock-names = "phyclk"; +- #clock-cells = <0>; +- #phy-cells = <0>; +- }; +- }; +-}; +- +-&i2c0 { +- compatible = "rockchip,rk3188-i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_xfer>; +-}; +- +-&i2c1 { +- compatible = "rockchip,rk3188-i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_xfer>; +-}; +- +-&i2c2 { +- compatible = "rockchip,rk3188-i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_xfer>; +-}; +- +-&i2c3 { +- compatible = "rockchip,rk3188-i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_xfer>; +-}; +- +-&i2c4 { +- compatible = "rockchip,rk3188-i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_xfer>; +-}; +- +-&pmu { +- power: power-controller { +- compatible = "rockchip,rk3188-power-controller"; +- #power-domain-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- power-domain@RK3188_PD_VIO { +- reg = ; +- clocks = <&cru ACLK_LCDC0>, +- <&cru ACLK_LCDC1>, +- <&cru DCLK_LCDC0>, +- <&cru DCLK_LCDC1>, +- <&cru HCLK_LCDC0>, +- <&cru HCLK_LCDC1>, +- <&cru SCLK_CIF0>, +- <&cru ACLK_CIF0>, +- <&cru HCLK_CIF0>, +- <&cru ACLK_IPP>, +- <&cru HCLK_IPP>, +- <&cru ACLK_RGA>, +- <&cru HCLK_RGA>; +- pm_qos = <&qos_lcdc0>, +- <&qos_lcdc1>, +- <&qos_cif0>, +- <&qos_ipp>, +- <&qos_rga>; +- #power-domain-cells = <0>; +- }; +- +- power-domain@RK3188_PD_VIDEO { +- reg = ; +- clocks = <&cru ACLK_VDPU>, +- <&cru ACLK_VEPU>, +- <&cru HCLK_VDPU>, +- <&cru HCLK_VEPU>; +- pm_qos = <&qos_vpu>; +- #power-domain-cells = <0>; +- }; +- +- power-domain@RK3188_PD_GPU { +- reg = ; +- clocks = <&cru ACLK_GPU>; +- pm_qos = <&qos_gpu>; +- #power-domain-cells = <0>; +- }; +- }; +-}; +- +-&pwm0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_out>; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm1_out>; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm2_out>; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm3_out>; +-}; +- +-&spi0 { +- compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; +-}; +- +-&spi1 { +- compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; +-}; +- +-&uart0 { +- compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer>; +-}; +- +-&uart1 { +- compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_xfer>; +-}; +- +-&uart2 { +- compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_xfer>; +-}; +- +-&uart3 { +- compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_xfer>; +-}; +- +-&vpu { +- compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu"; +- power-domains = <&power RK3188_PD_VIDEO>; +-}; +- +-&wdt { +- compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3228-evb.dts b/scripts/dtc/include-prefixes/arm/rk3228-evb.dts +deleted file mode 100644 +index 69a5e239ed1a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3228-evb.dts ++++ /dev/null +@@ -1,72 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-/dts-v1/; +- +-#include "rk322x.dtsi" +- +-/ { +- model = "Rockchip RK3228 Evaluation board"; +- compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; +- +- aliases { +- mmc0 = &emmc; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x40000000>; +- }; +- +- vcc_phy: vcc-phy-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- regulator-name = "vcc_phy"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&emmc { +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- disable-wp; +- non-removable; +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_MAC_SRC>; +- assigned-clock-rates = <50000000>; +- clock_in_out = "output"; +- phy-supply = <&vcc_phy>; +- phy-mode = "rmii"; +- phy-handle = <&phy>; +- status = "okay"; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy: ethernet-phy@0 { +- compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- clocks = <&cru SCLK_MAC_PHY>; +- resets = <&cru SRST_MACPHY>; +- phy-is-integrated; +- }; +- }; +-}; +- +-&tsadc { +- status = "okay"; +- +- rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ +-}; +- +-&uart2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3229-evb.dts b/scripts/dtc/include-prefixes/arm/rk3229-evb.dts +deleted file mode 100644 +index 797476e8bef1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3229-evb.dts ++++ /dev/null +@@ -1,256 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-/dts-v1/; +- +-#include +-#include "rk3229.dtsi" +- +-/ { +- model = "Rockchip RK3229 Evaluation board"; +- compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; +- +- aliases { +- mmc0 = &emmc; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x40000000>; +- }; +- +- dc_12v: dc-12v-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "dc_12v"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- ext_gmac: ext_gmac { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "ext_gmac"; +- #clock-cells = <0>; +- }; +- +- vcc_host: vcc-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&host_vbus_drv>; +- regulator-name = "vcc_host"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_phy: vcc-phy-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- regulator-name = "vcc_phy"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vccio_1v8>; +- }; +- +- vcc_sys: vcc-sys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&dc_12v>; +- }; +- +- vccio_1v8: vccio-1v8-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vccio_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vccio_3v3: vccio-3v3-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vccio_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vdd_arm: vdd-arm-regulator { +- compatible = "pwm-regulator"; +- pwms = <&pwm1 0 25000 1>; +- pwm-supply = <&vcc_sys>; +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_log: vdd-log-regulator { +- compatible = "pwm-regulator"; +- pwms = <&pwm2 0 25000 1>; +- pwm-supply = <&vcc_sys>; +- regulator-name = "vdd_log"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- autorepeat; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_key>; +- +- power_key: power-key { +- label = "GPIO Key Power"; +- gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <100>; +- wakeup-source; +- }; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&emmc { +- cap-mmc-highspeed; +- non-removable; +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>; +- assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>; +- clock_in_out = "input"; +- phy-supply = <&vcc_phy>; +- phy-mode = "rgmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 1000000>; +- tx_delay = <0x30>; +- rx_delay = <0x10>; +- status = "okay"; +-}; +- +-&io_domains { +- status = "okay"; +- +- vccio1-supply = <&vccio_3v3>; +- vccio2-supply = <&vccio_1v8>; +- vccio4-supply = <&vccio_3v3>; +-}; +- +-&pinctrl { +- keys { +- pwr_key: pwr-key { +- rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- usb { +- host_vbus_drv: host-vbus-drv { +- rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&u2phy0 { +- status = "okay"; +- +- u2phy0_otg: otg-port { +- status = "okay"; +- }; +- +- u2phy0_host: host-port { +- phy-supply = <&vcc_host>; +- status = "okay"; +- }; +-}; +- +-&u2phy1 { +- status = "okay"; +- +- u2phy1_otg: otg-port { +- phy-supply = <&vcc_host>; +- status = "okay"; +- }; +- +- u2phy1_host: host-port { +- phy-supply = <&vcc_host>; +- status = "okay"; +- }; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&usb_host2_ehci { +- status = "okay"; +-}; +- +-&usb_host2_ohci { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3229-xms6.dts b/scripts/dtc/include-prefixes/arm/rk3229-xms6.dts +deleted file mode 100644 +index 7bfbfd11fb55..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3229-xms6.dts ++++ /dev/null +@@ -1,304 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-/dts-v1/; +- +-#include +-#include "rk3229.dtsi" +- +-/ { +- model = "Mecer Xtreme Mini S6"; +- compatible = "mecer,xms6", "rockchip,rk3229"; +- +- aliases { +- mmc0 = &sdmmc; +- mmc1 = &sdio; +- mmc2 = &emmc; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x40000000>; +- }; +- +- dc_12v: dc-12v-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "dc_12v"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- ext_gmac: ext_gmac { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "ext_gmac"; +- #clock-cells = <0>; +- }; +- +- power-led { +- compatible = "gpio-leds"; +- +- blue_led: led-0 { +- gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, +- <&gpio2 29 GPIO_ACTIVE_LOW>; +- }; +- +- vcc_host: vcc-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&host_vbus_drv>; +- regulator-name = "vcc_host"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_phy: vcc-phy-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- regulator-name = "vcc_phy"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vccio_1v8>; +- }; +- +- vcc_sys: vcc-sys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&dc_12v>; +- }; +- +- vccio_1v8: vccio-1v8-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vccio_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vccio_3v3: vccio-3v3-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vccio_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vdd_arm: vdd-arm-regulator { +- compatible = "pwm-regulator"; +- pwms = <&pwm1 0 25000 1>; +- pwm-supply = <&vcc_sys>; +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_log: vdd-log-regulator { +- compatible = "pwm-regulator"; +- pwms = <&pwm2 0 25000 1>; +- pwm-supply = <&vcc_sys>; +- regulator-name = "vdd_log"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&emmc { +- cap-mmc-highspeed; +- non-removable; +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_MAC_SRC>; +- assigned-clock-rates = <50000000>; +- clock_in_out = "output"; +- phy-handle = <&phy>; +- phy-mode = "rmii"; +- phy-supply = <&vcc_phy>; +- status = "okay"; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy: ethernet-phy@0 { +- compatible = "ethernet-phy-id1234.d400", +- "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- clocks = <&cru SCLK_MAC_PHY>; +- phy-is-integrated; +- resets = <&cru SRST_MACPHY>; +- }; +- }; +-}; +- +-&gpu { +- mali-supply = <&vdd_log>; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_phy { +- status = "okay"; +-}; +- +-&iep_mmu { +- status = "okay"; +-}; +- +-&io_domains { +- status = "okay"; +- +- vccio1-supply = <&vccio_3v3>; +- vccio2-supply = <&vccio_1v8>; +- vccio4-supply = <&vccio_3v3>; +-}; +- +-&pinctrl { +- usb { +- host_vbus_drv: host-vbus-drv { +- rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&sdio { +- bus-width = <4>; +- cap-sd-highspeed; +- cap-sdio-irq; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- vqmmc-supply = <&vccio_1v8>; +- status = "okay"; +-}; +- +-&sdmmc { +- cap-mmc-highspeed; +- disable-wp; +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <0>; +- status = "okay"; +-}; +- +-&u2phy0 { +- status = "okay"; +- +- u2phy0_host: host-port { +- phy-supply = <&vcc_host>; +- status = "okay"; +- }; +- +- u2phy0_otg: otg-port { +- phy-supply = <&vcc_host>; +- status = "okay"; +- }; +-}; +- +-&u2phy1 { +- status = "okay"; +- +- u2phy1_host: host-port { +- phy-supply = <&vcc_host>; +- status = "okay"; +- }; +- +- u2phy1_otg: otg-port { +- phy-supply = <&vcc_host>; +- status = "okay"; +- }; +-}; +- +-&uart2 { +- pinctrl-0 = <&uart21_xfer>; +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&usb_host2_ehci { +- status = "okay"; +-}; +- +-&usb_host2_ohci { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +- +-&vop { +- status = "okay"; +-}; +- +-&vop_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3229.dtsi b/scripts/dtc/include-prefixes/arm/rk3229.dtsi +deleted file mode 100644 +index cb7d3fad8e60..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3229.dtsi ++++ /dev/null +@@ -1,52 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd +- */ +- +-#include "rk322x.dtsi" +- +-/ { +- compatible = "rockchip,rk3229"; +- +- /delete-node/ opp-table0; +- +- cpu0_opp_table: opp_table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-408000000 { +- opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <950000>; +- clock-latency-ns = <40000>; +- opp-suspend; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <975000>; +- }; +- opp-816000000 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <1000000>; +- }; +- opp-1008000000 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <1175000>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <1275000>; +- }; +- opp-1296000000 { +- opp-hz = /bits/ 64 <1296000000>; +- opp-microvolt = <1325000>; +- }; +- opp-1392000000 { +- opp-hz = /bits/ 64 <1392000000>; +- opp-microvolt = <1375000>; +- }; +- opp-1464000000 { +- opp-hz = /bits/ 64 <1464000000>; +- opp-microvolt = <1400000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk322x.dtsi b/scripts/dtc/include-prefixes/arm/rk322x.dtsi +deleted file mode 100644 +index f31cf1df892b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk322x.dtsi ++++ /dev/null +@@ -1,1293 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- interrupt-parent = <&gic>; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- spi0 = &spi0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@f00 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0xf00>; +- resets = <&cru SRST_CORE0>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- clock-latency = <40000>; +- clocks = <&cru ARMCLK>; +- enable-method = "psci"; +- }; +- +- cpu1: cpu@f01 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0xf01>; +- resets = <&cru SRST_CORE1>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- enable-method = "psci"; +- }; +- +- cpu2: cpu@f02 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0xf02>; +- resets = <&cru SRST_CORE2>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- enable-method = "psci"; +- }; +- +- cpu3: cpu@f03 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0xf03>; +- resets = <&cru SRST_CORE3>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- enable-method = "psci"; +- }; +- }; +- +- cpu0_opp_table: opp_table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-408000000 { +- opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <950000>; +- clock-latency-ns = <40000>; +- opp-suspend; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <975000>; +- }; +- opp-816000000 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <1000000>; +- }; +- opp-1008000000 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <1175000>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <1275000>; +- }; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- psci { +- compatible = "arm,psci-1.0", "arm,psci-0.2"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- arm,cpu-registers-not-fw-configured; +- interrupts = , +- , +- , +- ; +- clock-frequency = <24000000>; +- }; +- +- xin24m: oscillator { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "xin24m"; +- #clock-cells = <0>; +- }; +- +- display_subsystem: display-subsystem { +- compatible = "rockchip,display-subsystem"; +- ports = <&vop_out>; +- }; +- +- i2s1: i2s1@100b0000 { +- compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; +- reg = <0x100b0000 0x4000>; +- interrupts = ; +- clock-names = "i2s_clk", "i2s_hclk"; +- clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; +- dmas = <&pdma 14>, <&pdma 15>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s1_bus>; +- status = "disabled"; +- }; +- +- i2s0: i2s0@100c0000 { +- compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; +- reg = <0x100c0000 0x4000>; +- interrupts = ; +- clock-names = "i2s_clk", "i2s_hclk"; +- clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; +- dmas = <&pdma 11>, <&pdma 12>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- spdif: spdif@100d0000 { +- compatible = "rockchip,rk3228-spdif"; +- reg = <0x100d0000 0x1000>; +- interrupts = ; +- clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; +- clock-names = "mclk", "hclk"; +- dmas = <&pdma 10>; +- dma-names = "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spdif_tx>; +- status = "disabled"; +- }; +- +- i2s2: i2s2@100e0000 { +- compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; +- reg = <0x100e0000 0x4000>; +- interrupts = ; +- clock-names = "i2s_clk", "i2s_hclk"; +- clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; +- dmas = <&pdma 0>, <&pdma 1>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- grf: syscon@11000000 { +- compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd"; +- reg = <0x11000000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- io_domains: io-domains { +- compatible = "rockchip,rk3228-io-voltage-domain"; +- status = "disabled"; +- }; +- +- power: power-controller { +- compatible = "rockchip,rk3228-power-controller"; +- #power-domain-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- power-domain@RK3228_PD_VIO { +- reg = ; +- clocks = <&cru ACLK_HDCP>, +- <&cru SCLK_HDCP>, +- <&cru ACLK_IEP>, +- <&cru HCLK_IEP>, +- <&cru ACLK_RGA>, +- <&cru HCLK_RGA>, +- <&cru SCLK_RGA>; +- pm_qos = <&qos_hdcp>, +- <&qos_iep>, +- <&qos_rga_r>, +- <&qos_rga_w>; +- #power-domain-cells = <0>; +- }; +- +- power-domain@RK3228_PD_VOP { +- reg = ; +- clocks =<&cru ACLK_VOP>, +- <&cru DCLK_VOP>, +- <&cru HCLK_VOP>; +- pm_qos = <&qos_vop>; +- #power-domain-cells = <0>; +- }; +- +- power-domain@RK3228_PD_VPU { +- reg = ; +- clocks = <&cru ACLK_VPU>, +- <&cru HCLK_VPU>; +- pm_qos = <&qos_vpu>; +- #power-domain-cells = <0>; +- }; +- +- power-domain@RK3228_PD_RKVDEC { +- reg = ; +- clocks = <&cru ACLK_RKVDEC>, +- <&cru HCLK_RKVDEC>, +- <&cru SCLK_VDEC_CABAC>, +- <&cru SCLK_VDEC_CORE>; +- pm_qos = <&qos_rkvdec_r>, +- <&qos_rkvdec_w>; +- #power-domain-cells = <0>; +- }; +- +- power-domain@RK3228_PD_GPU { +- reg = ; +- clocks = <&cru ACLK_GPU>; +- pm_qos = <&qos_gpu>; +- #power-domain-cells = <0>; +- }; +- }; +- +- u2phy0: usb2phy@760 { +- compatible = "rockchip,rk3228-usb2phy"; +- reg = <0x0760 0x0c>; +- clocks = <&cru SCLK_OTGPHY0>; +- clock-names = "phyclk"; +- clock-output-names = "usb480m_phy0"; +- #clock-cells = <0>; +- status = "disabled"; +- +- u2phy0_otg: otg-port { +- interrupts = , +- , +- ; +- interrupt-names = "otg-bvalid", "otg-id", +- "linestate"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- u2phy0_host: host-port { +- interrupts = ; +- interrupt-names = "linestate"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- u2phy1: usb2phy@800 { +- compatible = "rockchip,rk3228-usb2phy"; +- reg = <0x0800 0x0c>; +- clocks = <&cru SCLK_OTGPHY1>; +- clock-names = "phyclk"; +- clock-output-names = "usb480m_phy1"; +- #clock-cells = <0>; +- status = "disabled"; +- +- u2phy1_otg: otg-port { +- interrupts = ; +- interrupt-names = "linestate"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- u2phy1_host: host-port { +- interrupts = ; +- interrupt-names = "linestate"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- }; +- +- uart0: serial@11010000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x11010000 0x100>; +- interrupts = ; +- clock-frequency = <24000000>; +- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; +- clock-names = "baudclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart1: serial@11020000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x11020000 0x100>; +- interrupts = ; +- clock-frequency = <24000000>; +- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; +- clock-names = "baudclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_xfer>; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart2: serial@11030000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x11030000 0x100>; +- interrupts = ; +- clock-frequency = <24000000>; +- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; +- clock-names = "baudclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_xfer>; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- efuse: efuse@11040000 { +- compatible = "rockchip,rk3228-efuse"; +- reg = <0x11040000 0x20>; +- clocks = <&cru PCLK_EFUSE_256>; +- clock-names = "pclk_efuse"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* Data cells */ +- efuse_id: id@7 { +- reg = <0x7 0x10>; +- }; +- cpu_leakage: cpu_leakage@17 { +- reg = <0x17 0x1>; +- }; +- }; +- +- i2c0: i2c@11050000 { +- compatible = "rockchip,rk3228-i2c"; +- reg = <0x11050000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "i2c"; +- clocks = <&cru PCLK_I2C0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_xfer>; +- status = "disabled"; +- }; +- +- i2c1: i2c@11060000 { +- compatible = "rockchip,rk3228-i2c"; +- reg = <0x11060000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "i2c"; +- clocks = <&cru PCLK_I2C1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_xfer>; +- status = "disabled"; +- }; +- +- i2c2: i2c@11070000 { +- compatible = "rockchip,rk3228-i2c"; +- reg = <0x11070000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "i2c"; +- clocks = <&cru PCLK_I2C2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_xfer>; +- status = "disabled"; +- }; +- +- i2c3: i2c@11080000 { +- compatible = "rockchip,rk3228-i2c"; +- reg = <0x11080000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "i2c"; +- clocks = <&cru PCLK_I2C3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_xfer>; +- status = "disabled"; +- }; +- +- spi0: spi@11090000 { +- compatible = "rockchip,rk3228-spi"; +- reg = <0x11090000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; +- clock-names = "spiclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; +- status = "disabled"; +- }; +- +- wdt: watchdog@110a0000 { +- compatible = "rockchip,rk3228-wdt", "snps,dw-wdt"; +- reg = <0x110a0000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_CPU>; +- status = "disabled"; +- }; +- +- pwm0: pwm@110b0000 { +- compatible = "rockchip,rk3288-pwm"; +- reg = <0x110b0000 0x10>; +- #pwm-cells = <3>; +- clocks = <&cru PCLK_PWM>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>; +- status = "disabled"; +- }; +- +- pwm1: pwm@110b0010 { +- compatible = "rockchip,rk3288-pwm"; +- reg = <0x110b0010 0x10>; +- #pwm-cells = <3>; +- clocks = <&cru PCLK_PWM>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm1_pin>; +- status = "disabled"; +- }; +- +- pwm2: pwm@110b0020 { +- compatible = "rockchip,rk3288-pwm"; +- reg = <0x110b0020 0x10>; +- #pwm-cells = <3>; +- clocks = <&cru PCLK_PWM>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm2_pin>; +- status = "disabled"; +- }; +- +- pwm3: pwm@110b0030 { +- compatible = "rockchip,rk3288-pwm"; +- reg = <0x110b0030 0x10>; +- #pwm-cells = <2>; +- clocks = <&cru PCLK_PWM>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm3_pin>; +- status = "disabled"; +- }; +- +- timer: timer@110c0000 { +- compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer"; +- reg = <0x110c0000 0x20>; +- interrupts = ; +- clocks = <&xin24m>, <&cru PCLK_TIMER>; +- clock-names = "timer", "pclk"; +- }; +- +- cru: clock-controller@110e0000 { +- compatible = "rockchip,rk3228-cru"; +- reg = <0x110e0000 0x1000>; +- rockchip,grf = <&grf>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- assigned-clocks = +- <&cru PLL_GPLL>, <&cru ARMCLK>, +- <&cru PLL_CPLL>, <&cru ACLK_PERI>, +- <&cru HCLK_PERI>, <&cru PCLK_PERI>, +- <&cru ACLK_CPU>, <&cru HCLK_CPU>, +- <&cru PCLK_CPU>; +- assigned-clock-rates = +- <594000000>, <816000000>, +- <500000000>, <150000000>, +- <150000000>, <75000000>, +- <150000000>, <150000000>, +- <75000000>; +- }; +- +- pdma: pdma@110f0000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x110f0000 0x4000>; +- interrupts = , +- ; +- #dma-cells = <1>; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMAC>; +- clock-names = "apb_pclk"; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <100>; /* milliseconds */ +- polling-delay = <5000>; /* milliseconds */ +- +- thermal-sensors = <&tsadc 0>; +- +- trips { +- cpu_alert0: cpu_alert0 { +- temperature = <70000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu_alert1: cpu_alert1 { +- temperature = <75000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu_crit: cpu_crit { +- temperature = <90000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- cooling-device = +- <&cpu0 THERMAL_NO_LIMIT 6>, +- <&cpu1 THERMAL_NO_LIMIT 6>, +- <&cpu2 THERMAL_NO_LIMIT 6>, +- <&cpu3 THERMAL_NO_LIMIT 6>; +- }; +- map1 { +- trip = <&cpu_alert1>; +- cooling-device = +- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- tsadc: tsadc@11150000 { +- compatible = "rockchip,rk3228-tsadc"; +- reg = <0x11150000 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; +- clock-names = "tsadc", "apb_pclk"; +- assigned-clocks = <&cru SCLK_TSADC>; +- assigned-clock-rates = <32768>; +- resets = <&cru SRST_TSADC>; +- reset-names = "tsadc-apb"; +- pinctrl-names = "init", "default", "sleep"; +- pinctrl-0 = <&otp_pin>; +- pinctrl-1 = <&otp_out>; +- pinctrl-2 = <&otp_pin>; +- #thermal-sensor-cells = <1>; +- rockchip,hw-tshut-temp = <95000>; +- status = "disabled"; +- }; +- +- hdmi_phy: hdmi-phy@12030000 { +- compatible = "rockchip,rk3228-hdmi-phy"; +- reg = <0x12030000 0x10000>; +- clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>; +- clock-names = "sysclk", "refoclk", "refpclk"; +- #clock-cells = <0>; +- clock-output-names = "hdmiphy_phy"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- gpu: gpu@20000000 { +- compatible = "rockchip,rk3228-mali", "arm,mali-400"; +- reg = <0x20000000 0x10000>; +- interrupts = , +- , +- , +- , +- , +- ; +- interrupt-names = "gp", +- "gpmmu", +- "pp0", +- "ppmmu0", +- "pp1", +- "ppmmu1"; +- clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; +- clock-names = "bus", "core"; +- power-domains = <&power RK3228_PD_GPU>; +- resets = <&cru SRST_GPU_A>; +- status = "disabled"; +- }; +- +- vpu: video-codec@20020000 { +- compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu"; +- reg = <0x20020000 0x800>; +- interrupts = , +- ; +- interrupt-names = "vepu", "vdpu"; +- clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; +- clock-names = "aclk", "hclk"; +- iommus = <&vpu_mmu>; +- power-domains = <&power RK3228_PD_VPU>; +- }; +- +- vpu_mmu: iommu@20020800 { +- compatible = "rockchip,iommu"; +- reg = <0x20020800 0x100>; +- interrupts = ; +- clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; +- clock-names = "aclk", "iface"; +- power-domains = <&power RK3228_PD_VPU>; +- #iommu-cells = <0>; +- }; +- +- vdec: video-codec@20030000 { +- compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec"; +- reg = <0x20030000 0x480>; +- interrupts = ; +- clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, +- <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; +- clock-names = "axi", "ahb", "cabac", "core"; +- assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; +- assigned-clock-rates = <300000000>, <300000000>; +- iommus = <&vdec_mmu>; +- power-domains = <&power RK3228_PD_RKVDEC>; +- }; +- +- vdec_mmu: iommu@20030480 { +- compatible = "rockchip,iommu"; +- reg = <0x20030480 0x40>, <0x200304c0 0x40>; +- interrupts = ; +- clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; +- clock-names = "aclk", "iface"; +- power-domains = <&power RK3228_PD_RKVDEC>; +- #iommu-cells = <0>; +- }; +- +- vop: vop@20050000 { +- compatible = "rockchip,rk3228-vop"; +- reg = <0x20050000 0x1ffc>; +- interrupts = ; +- clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; +- clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; +- resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; +- reset-names = "axi", "ahb", "dclk"; +- iommus = <&vop_mmu>; +- power-domains = <&power RK3228_PD_VOP>; +- status = "disabled"; +- +- vop_out: port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- vop_out_hdmi: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&hdmi_in_vop>; +- }; +- }; +- }; +- +- vop_mmu: iommu@20053f00 { +- compatible = "rockchip,iommu"; +- reg = <0x20053f00 0x100>; +- interrupts = ; +- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; +- clock-names = "aclk", "iface"; +- power-domains = <&power RK3228_PD_VOP>; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- rga: rga@20060000 { +- compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga"; +- reg = <0x20060000 0x1000>; +- interrupts = ; +- clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; +- clock-names = "aclk", "hclk", "sclk"; +- power-domains = <&power RK3228_PD_VIO>; +- resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>; +- reset-names = "core", "axi", "ahb"; +- }; +- +- iep_mmu: iommu@20070800 { +- compatible = "rockchip,iommu"; +- reg = <0x20070800 0x100>; +- interrupts = ; +- clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; +- clock-names = "aclk", "iface"; +- power-domains = <&power RK3228_PD_VIO>; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- hdmi: hdmi@200a0000 { +- compatible = "rockchip,rk3228-dw-hdmi"; +- reg = <0x200a0000 0x20000>; +- reg-io-width = <4>; +- interrupts = ; +- assigned-clocks = <&cru SCLK_HDMI_PHY>; +- assigned-clock-parents = <&hdmi_phy>; +- clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; +- clock-names = "iahb", "isfr", "cec"; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; +- resets = <&cru SRST_HDMI_P>; +- reset-names = "hdmi"; +- phys = <&hdmi_phy>; +- phy-names = "hdmi"; +- rockchip,grf = <&grf>; +- status = "disabled"; +- +- ports { +- hdmi_in: port { +- #address-cells = <1>; +- #size-cells = <0>; +- hdmi_in_vop: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vop_out_hdmi>; +- }; +- }; +- }; +- }; +- +- sdmmc: mmc@30000000 { +- compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x30000000 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, +- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; +- status = "disabled"; +- }; +- +- sdio: mmc@30010000 { +- compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x30010000 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, +- <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; +- status = "disabled"; +- }; +- +- emmc: mmc@30020000 { +- compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x30020000 0x4000>; +- interrupts = ; +- clock-frequency = <37500000>; +- max-frequency = <37500000>; +- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, +- <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- bus-width = <8>; +- rockchip,default-sample-phase = <158>; +- fifo-depth = <0x100>; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +- resets = <&cru SRST_EMMC>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- usb_otg: usb@30040000 { +- compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", +- "snps,dwc2"; +- reg = <0x30040000 0x40000>; +- interrupts = ; +- clocks = <&cru HCLK_OTG>; +- clock-names = "otg"; +- dr_mode = "otg"; +- g-np-tx-fifo-size = <16>; +- g-rx-fifo-size = <280>; +- g-tx-fifo-size = <256 128 128 64 32 16>; +- phys = <&u2phy0_otg>; +- phy-names = "usb2-phy"; +- status = "disabled"; +- }; +- +- usb_host0_ehci: usb@30080000 { +- compatible = "generic-ehci"; +- reg = <0x30080000 0x20000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST0>, <&u2phy0>; +- phys = <&u2phy0_host>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usb_host0_ohci: usb@300a0000 { +- compatible = "generic-ohci"; +- reg = <0x300a0000 0x20000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST0>, <&u2phy0>; +- phys = <&u2phy0_host>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usb_host1_ehci: usb@300c0000 { +- compatible = "generic-ehci"; +- reg = <0x300c0000 0x20000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST1>, <&u2phy1>; +- phys = <&u2phy1_otg>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usb_host1_ohci: usb@300e0000 { +- compatible = "generic-ohci"; +- reg = <0x300e0000 0x20000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST1>, <&u2phy1>; +- phys = <&u2phy1_otg>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usb_host2_ehci: usb@30100000 { +- compatible = "generic-ehci"; +- reg = <0x30100000 0x20000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST2>, <&u2phy1>; +- phys = <&u2phy1_host>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usb_host2_ohci: usb@30120000 { +- compatible = "generic-ohci"; +- reg = <0x30120000 0x20000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST2>, <&u2phy1>; +- phys = <&u2phy1_host>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- gmac: ethernet@30200000 { +- compatible = "rockchip,rk3228-gmac"; +- reg = <0x30200000 0x10000>; +- interrupts = ; +- interrupt-names = "macirq"; +- clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, +- <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, +- <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, +- <&cru PCLK_GMAC>; +- clock-names = "stmmaceth", "mac_clk_rx", +- "mac_clk_tx", "clk_mac_ref", +- "clk_mac_refout", "aclk_mac", +- "pclk_mac"; +- resets = <&cru SRST_GMAC>; +- reset-names = "stmmaceth"; +- rockchip,grf = <&grf>; +- status = "disabled"; +- }; +- +- qos_iep: qos@31030080 { +- compatible = "rockchip,rk3228-qos", "syscon"; +- reg = <0x31030080 0x20>; +- }; +- +- qos_rga_w: qos@31030100 { +- compatible = "rockchip,rk3228-qos", "syscon"; +- reg = <0x31030100 0x20>; +- }; +- +- qos_hdcp: qos@31030180 { +- compatible = "rockchip,rk3228-qos", "syscon"; +- reg = <0x31030180 0x20>; +- }; +- +- qos_rga_r: qos@31030200 { +- compatible = "rockchip,rk3228-qos", "syscon"; +- reg = <0x31030200 0x20>; +- }; +- +- qos_vpu: qos@31040000 { +- compatible = "rockchip,rk3228-qos", "syscon"; +- reg = <0x31040000 0x20>; +- }; +- +- qos_gpu: qos@31050000 { +- compatible = "rockchip,rk3228-qos", "syscon"; +- reg = <0x31050000 0x20>; +- }; +- +- qos_vop: qos@31060000 { +- compatible = "rockchip,rk3228-qos", "syscon"; +- reg = <0x31060000 0x20>; +- }; +- +- qos_rkvdec_r: qos@31070000 { +- compatible = "rockchip,rk3228-qos", "syscon"; +- reg = <0x31070000 0x20>; +- }; +- +- qos_rkvdec_w: qos@31070080 { +- compatible = "rockchip,rk3228-qos", "syscon"; +- reg = <0x31070080 0x20>; +- }; +- +- gic: interrupt-controller@32010000 { +- compatible = "arm,gic-400"; +- interrupt-controller; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- +- reg = <0x32011000 0x1000>, +- <0x32012000 0x2000>, +- <0x32014000 0x2000>, +- <0x32016000 0x2000>; +- interrupts = ; +- }; +- +- pinctrl: pinctrl { +- compatible = "rockchip,rk3228-pinctrl"; +- rockchip,grf = <&grf>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gpio0: gpio0@11110000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x11110000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio1@11120000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x11120000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO1>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio2@11130000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x11130000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO2>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio3@11140000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x11140000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO3>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pcfg_pull_up: pcfg-pull-up { +- bias-pull-up; +- }; +- +- pcfg_pull_down: pcfg-pull-down { +- bias-pull-down; +- }; +- +- pcfg_pull_none: pcfg-pull-none { +- bias-disable; +- }; +- +- pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { +- drive-strength = <12>; +- }; +- +- sdmmc { +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>; +- }; +- +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>, +- <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>, +- <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>, +- <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; +- }; +- }; +- +- sdio { +- sdio_clk: sdio-clk { +- rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>; +- }; +- +- sdio_cmd: sdio-cmd { +- rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>; +- }; +- +- sdio_bus4: sdio-bus4 { +- rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>, +- <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>, +- <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>, +- <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>; +- }; +- }; +- +- emmc { +- emmc_clk: emmc-clk { +- rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; +- }; +- +- emmc_cmd: emmc-cmd { +- rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>; +- }; +- +- emmc_bus8: emmc-bus8 { +- rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, +- <1 RK_PD1 2 &pcfg_pull_none>, +- <1 RK_PD2 2 &pcfg_pull_none>, +- <1 RK_PD3 2 &pcfg_pull_none>, +- <1 RK_PD4 2 &pcfg_pull_none>, +- <1 RK_PD5 2 &pcfg_pull_none>, +- <1 RK_PD6 2 &pcfg_pull_none>, +- <1 RK_PD7 2 &pcfg_pull_none>; +- }; +- }; +- +- gmac { +- rgmii_pins: rgmii-pins { +- rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, +- <2 RK_PB4 1 &pcfg_pull_none>, +- <2 RK_PD1 1 &pcfg_pull_none>, +- <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, +- <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, +- <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>, +- <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>, +- <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>, +- <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, +- <2 RK_PC1 1 &pcfg_pull_none>, +- <2 RK_PC0 1 &pcfg_pull_none>, +- <2 RK_PC5 2 &pcfg_pull_none>, +- <2 RK_PC4 2 &pcfg_pull_none>, +- <2 RK_PB3 1 &pcfg_pull_none>, +- <2 RK_PB0 1 &pcfg_pull_none>; +- }; +- +- rmii_pins: rmii-pins { +- rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, +- <2 RK_PB4 1 &pcfg_pull_none>, +- <2 RK_PD1 1 &pcfg_pull_none>, +- <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, +- <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, +- <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, +- <2 RK_PC1 1 &pcfg_pull_none>, +- <2 RK_PC0 1 &pcfg_pull_none>, +- <2 RK_PB0 1 &pcfg_pull_none>, +- <2 RK_PB7 1 &pcfg_pull_none>; +- }; +- +- phy_pins: phy-pins { +- rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>, +- <2 RK_PB0 2 &pcfg_pull_none>; +- }; +- }; +- +- hdmi { +- hdmi_hpd: hdmi-hpd { +- rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>; +- }; +- +- hdmii2c_xfer: hdmii2c-xfer { +- rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, +- <0 RK_PA7 2 &pcfg_pull_none>; +- }; +- +- hdmi_cec: hdmi-cec { +- rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c0 { +- i2c0_xfer: i2c0-xfer { +- rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, +- <0 RK_PA1 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c1 { +- i2c1_xfer: i2c1-xfer { +- rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, +- <0 RK_PA3 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c2 { +- i2c2_xfer: i2c2-xfer { +- rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, +- <2 RK_PC5 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c3 { +- i2c3_xfer: i2c3-xfer { +- rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, +- <0 RK_PA7 1 &pcfg_pull_none>; +- }; +- }; +- +- spi0 { +- spi0_clk: spi0-clk { +- rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>; +- }; +- spi0_cs0: spi0-cs0 { +- rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>; +- }; +- spi0_tx: spi0-tx { +- rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; +- }; +- spi0_rx: spi0-rx { +- rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; +- }; +- spi0_cs1: spi0-cs1 { +- rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>; +- }; +- }; +- +- spi1 { +- spi1_clk: spi1-clk { +- rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>; +- }; +- spi1_cs0: spi1-cs0 { +- rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>; +- }; +- spi1_rx: spi1-rx { +- rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>; +- }; +- spi1_tx: spi1-tx { +- rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>; +- }; +- spi1_cs1: spi1-cs1 { +- rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>; +- }; +- }; +- +- i2s1 { +- i2s1_bus: i2s1-bus { +- rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, +- <0 RK_PB1 1 &pcfg_pull_none>, +- <0 RK_PB3 1 &pcfg_pull_none>, +- <0 RK_PB4 1 &pcfg_pull_none>, +- <0 RK_PB5 1 &pcfg_pull_none>, +- <0 RK_PB6 1 &pcfg_pull_none>, +- <1 RK_PA2 2 &pcfg_pull_none>, +- <1 RK_PA4 2 &pcfg_pull_none>, +- <1 RK_PA5 2 &pcfg_pull_none>; +- }; +- }; +- +- pwm0 { +- pwm0_pin: pwm0-pin { +- rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm1 { +- pwm1_pin: pwm1-pin { +- rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; +- }; +- }; +- +- pwm2 { +- pwm2_pin: pwm2-pin { +- rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>; +- }; +- }; +- +- pwm3 { +- pwm3_pin: pwm3-pin { +- rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; +- }; +- }; +- +- spdif { +- spdif_tx: spdif-tx { +- rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>; +- }; +- }; +- +- tsadc { +- otp_pin: otp-pin { +- rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- otp_out: otp-out { +- rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; +- }; +- }; +- +- uart0 { +- uart0_xfer: uart0-xfer { +- rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>, +- <2 RK_PD3 1 &pcfg_pull_none>; +- }; +- +- uart0_cts: uart0-cts { +- rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>; +- }; +- +- uart0_rts: uart0-rts { +- rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>; +- }; +- }; +- +- uart1 { +- uart1_xfer: uart1-xfer { +- rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, +- <1 RK_PB2 1 &pcfg_pull_none>; +- }; +- +- uart1_cts: uart1-cts { +- rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>; +- }; +- +- uart1_rts: uart1-rts { +- rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; +- }; +- }; +- +- uart2 { +- uart2_xfer: uart2-xfer { +- rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, +- <1 RK_PC3 2 &pcfg_pull_none>; +- }; +- +- uart21_xfer: uart21-xfer { +- rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>, +- <1 RK_PB1 2 &pcfg_pull_none>; +- }; +- +- uart2_cts: uart2-cts { +- rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; +- }; +- +- uart2_rts: uart2-rts { +- rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-evb-act8846.dts b/scripts/dtc/include-prefixes/arm/rk3288-evb-act8846.dts +deleted file mode 100644 +index be695b8c1f67..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-evb-act8846.dts ++++ /dev/null +@@ -1,188 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-/dts-v1/; +-#include "rk3288-evb.dtsi" +- +-/ { +- model = "Rockchip RK3288 EVB ACT8846"; +- compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288"; +- +- vcc_lcd: vcc-lcd { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio7 RK_PA3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_en>; +- regulator-name = "vcc_lcd"; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_wl: vcc-wl { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio7 RK_PB1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_pwr>; +- regulator-name = "vcc_wl"; +- vin-supply = <&vcc_18>; +- }; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- +- vdd_cpu: syr827@40 { +- compatible = "silergy,syr827"; +- fcs,suspend-voltage-selector = <1>; +- reg = <0x40>; +- regulator-name = "vdd_cpu"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vdd_gpu: syr828@41 { +- compatible = "silergy,syr828"; +- fcs,suspend-voltage-selector = <1>; +- reg = <0x41>; +- regulator-name = "vdd_gpu"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- vin-supply = <&vcc_sys>; +- }; +- +- hym8563@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- +- interrupt-parent = <&gpio0>; +- interrupts = ; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int>; +- +- #clock-cells = <0>; +- clock-output-names = "xin32k"; +- }; +- +- act8846: act8846@5a { +- compatible = "active-semi,act8846"; +- reg = <0x5a>; +- status = "okay"; +- +- vp1-supply = <&vcc_sys>; +- vp2-supply = <&vcc_sys>; +- vp3-supply = <&vcc_sys>; +- vp4-supply = <&vcc_sys>; +- inl1-supply = <&vcc_io>; +- inl2-supply = <&vcc_sys>; +- inl3-supply = <&vcc_20>; +- +- regulators { +- vcc_ddr: REG1 { +- regulator-name = "VCC_DDR"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vcc_io: REG2 { +- regulator-name = "VCC_IO"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_log: REG3 { +- regulator-name = "VDD_LOG"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- +- vcc_20: REG4 { +- regulator-name = "VCC_20"; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- regulator-always-on; +- }; +- +- vccio_sd: REG5 { +- regulator-name = "VCCIO_SD"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd10_lcd: REG6 { +- regulator-name = "VDD10_LCD"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- vcca_codec: REG7 { +- regulator-name = "VCCA_CODEC"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vcc_tp: REG8 { +- regulator-name = "VCCA_TP"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vccio_pmu: REG9 { +- regulator-name = "VCCIO_PMU"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_10: REG10 { +- regulator-name = "VDD_10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- vcc_18: REG11 { +- regulator-name = "VCC_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcc18_lcd: REG12 { +- regulator-name = "VCC18_LCD"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&panel { +- power-supply = <&vcc_lcd>; +-}; +- +-&pinctrl { +- lcd { +- lcd_en: lcd-en { +- rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- wifi { +- wifi_pwr: wifi-pwr { +- rockchip,pins = <7 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-evb-rk808.dts b/scripts/dtc/include-prefixes/arm/rk3288-evb-rk808.dts +deleted file mode 100644 +index 42384ea4ca21..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-evb-rk808.dts ++++ /dev/null +@@ -1,202 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-/dts-v1/; +-#include "rk3288-evb.dtsi" +- +-/ { +- model = "Rockchip RK3288 EVB RK808"; +- compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int &global_pwroff>; +- rockchip,system-power-controller; +- wakeup-source; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc6-supply = <&vcc_sys>; +- vcc7-supply = <&vcc_sys>; +- vcc8-supply = <&vcc_18>; +- vcc9-supply = <&vcc_io>; +- vcc10-supply = <&vcc_io>; +- vcc11-supply = <&vcc_sys>; +- vcc12-supply = <&vcc_io>; +- vddio-supply = <&vccio_pmu>; +- +- regulators { +- vdd_cpu: DCDC_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-name = "vdd_arm"; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: DCDC_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-name = "vdd_gpu"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc_ddr"; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_io: DCDC_REG4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc_io"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vccio_pmu: LDO_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vccio_pmu"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_tp: LDO_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc_tp"; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_10: LDO_REG3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-name = "vdd_10"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc18_lcd: LDO_REG4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc18_lcd"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vccio_sd: LDO_REG5 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vccio_sd"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vdd10_lcd: LDO_REG6 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-name = "vdd10_lcd"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc_18: LDO_REG7 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc_18"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcca_codec: LDO_REG8 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcca_codec"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_wl: SWITCH_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc_wl"; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_lcd: SWITCH_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc_lcd"; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- }; +- }; +-}; +- +-&panel { +- power-supply = <&vcc_lcd>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-evb.dtsi b/scripts/dtc/include-prefixes/arm/rk3288-evb.dtsi +deleted file mode 100644 +index c4ca73b40d4a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-evb.dtsi ++++ /dev/null +@@ -1,403 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-#include +-#include +-#include "rk3288.dtsi" +- +-/ { +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 1>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1800000>; +- +- button-up { +- label = "Volume Up"; +- linux,code = ; +- press-threshold-microvolt = <100000>; +- }; +- +- button-down { +- label = "Volume Down"; +- linux,code = ; +- press-threshold-microvolt = <300000>; +- }; +- +- menu { +- label = "Menu"; +- linux,code = ; +- press-threshold-microvolt = <640000>; +- }; +- +- esc { +- label = "Esc"; +- linux,code = ; +- press-threshold-microvolt = <1000000>; +- }; +- +- home { +- label = "Home"; +- linux,code = ; +- press-threshold-microvolt = <1300000>; +- }; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- brightness-levels = < +- 0 1 2 3 4 5 6 7 +- 8 9 10 11 12 13 14 15 +- 16 17 18 19 20 21 22 23 +- 24 25 26 27 28 29 30 31 +- 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 +- 48 49 50 51 52 53 54 55 +- 56 57 58 59 60 61 62 63 +- 64 65 66 67 68 69 70 71 +- 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 +- 88 89 90 91 92 93 94 95 +- 96 97 98 99 100 101 102 103 +- 104 105 106 107 108 109 110 111 +- 112 113 114 115 116 117 118 119 +- 120 121 122 123 124 125 126 127 +- 128 129 130 131 132 133 134 135 +- 136 137 138 139 140 141 142 143 +- 144 145 146 147 148 149 150 151 +- 152 153 154 155 156 157 158 159 +- 160 161 162 163 164 165 166 167 +- 168 169 170 171 172 173 174 175 +- 176 177 178 179 180 181 182 183 +- 184 185 186 187 188 189 190 191 +- 192 193 194 195 196 197 198 199 +- 200 201 202 203 204 205 206 207 +- 208 209 210 211 212 213 214 215 +- 216 217 218 219 220 221 222 223 +- 224 225 226 227 228 229 230 231 +- 232 233 234 235 236 237 238 239 +- 240 241 242 243 244 245 246 247 +- 248 249 250 251 252 253 254 255>; +- default-brightness-level = <128>; +- enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bl_en>; +- pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>; +- }; +- +- ext_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "ext_gmac"; +- #clock-cells = <0>; +- }; +- +- panel: panel { +- compatible = "lg,lp079qx1-sp0v"; +- backlight = <&backlight>; +- enable-gpios = <&gpio7 RK_PA4 GPIO_ACTIVE_HIGH>; +- pinctrl-0 = <&lcd_cs>; +- +- ports { +- panel_in: port { +- panel_in_edp: endpoint { +- remote-endpoint = <&edp_out_panel>; +- }; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pwrbtn>; +- +- power { +- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "GPIO Key Power"; +- linux,input-type = <1>; +- wakeup-source; +- debounce-interval = <100>; +- }; +- }; +- +- /* This turns on USB vbus for both host0 (ehci) and host1 (dwc2) */ +- vcc_host: vcc-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&host_vbus_drv>; +- regulator-name = "vcc_host"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc_phy: vcc-phy-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <ð_phy_pwr>; +- regulator-name = "vcc_phy"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc_sys: vsys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* +- * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from +- * vcc_io directly. Those boards won't be able to power cycle SD cards +- * but it shouldn't hurt to toggle this pin there anyway. +- */ +- vcc_sd: sdmmc-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_pwr>; +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- vin-supply = <&vcc_io>; +- }; +-}; +- +-&cpu0 { +- cpu0-supply = <&vdd_cpu>; +-}; +- +-&edp { +- force-hpd; +- status = "okay"; +- +- ports { +- edp_out: port@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- edp_out_panel: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_in_edp>; +- }; +- }; +- }; +-}; +- +-&edp_phy { +- status = "okay"; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- disable-wp; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vcc_18>; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- card-detect-delay = <200>; +- disable-wp; /* wp not hooked up */ +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +- status = "okay"; +- vmmc-supply = <&vcc_sd>; +- vqmmc-supply = <&vccio_sd>; +-}; +- +-&gmac { +- phy-supply = <&vcc_phy>; +- phy-mode = "rgmii"; +- clock_in_out = "input"; +- snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 1000000>; +- assigned-clocks = <&cru SCLK_MAC>; +- assigned-clock-parents = <&ext_gmac>; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- tx_delay = <0x30>; +- rx_delay = <0x10>; +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c5>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&uart4 { +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ +- status = "okay"; +-}; +- +-&pinctrl { +- pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { +- drive-strength = <8>; +- }; +- +- pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { +- bias-pull-up; +- drive-strength = <8>; +- }; +- +- backlight { +- bl_en: bl-en { +- rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- buttons { +- pwrbtn: pwrbtn { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- lcd { +- lcd_cs: lcd-cs { +- rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- pmic_int: pmic-int { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- sdmmc { +- /* +- * Default drive strength isn't enough to achieve even +- * high-speed mode on EVB board so bump up to 8ma. +- */ +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, +- <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, +- <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, +- <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; +- }; +- +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; +- }; +- +- sdmmc_pwr: sdmmc-pwr { +- rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb { +- host_vbus_drv: host-vbus-drv { +- rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- eth_phy { +- eth_phy_pwr: eth-phy-pwr { +- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host1 { +- status = "okay"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-firefly-beta.dts b/scripts/dtc/include-prefixes/arm/rk3288-firefly-beta.dts +deleted file mode 100644 +index 135e8832141f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-firefly-beta.dts ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2014, 2015 FUKAUMI Naoki +- */ +- +-/dts-v1/; +-#include "rk3288-firefly.dtsi" +- +-/ { +- model = "Firefly-RK3288 Beta"; +- compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288"; +-}; +- +-&ir { +- gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>; +-}; +- +-&pinctrl { +- act8846 { +- pmic_vsel: pmic-vsel { +- rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- }; +- +- ir { +- ir_int: ir-int { +- rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-firefly-reload-core.dtsi b/scripts/dtc/include-prefixes/arm/rk3288-firefly-reload-core.dtsi +deleted file mode 100644 +index 36efa36b7190..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-firefly-reload-core.dtsi ++++ /dev/null +@@ -1,274 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device tree file for Firefly Rockchip RK3288 Core board +- * Copyright (c) 2016 Randy Li +- */ +- +-#include +-#include "rk3288.dtsi" +- +-/ { +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- ext_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- clock-output-names = "ext_gmac"; +- }; +- +- +- vcc_flash: flash-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_flash"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_io>; +- }; +-}; +- +-&cpu0 { +- cpu0-supply = <&vdd_cpu>; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- disable-wp; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; +- vmmc-supply = <&vcc_io>; +- vqmmc-supply = <&vcc_flash>; +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_MAC>; +- assigned-clock-parents = <&ext_gmac>; +- clock_in_out = "input"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; +- phy-supply = <&vcc_lan>; +- phy-mode = "rgmii"; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 1000000>; +- snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; +- tx_delay = <0x30>; +- rx_delay = <0x10>; +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- status = "okay"; +- +- vdd_cpu: syr827@40 { +- compatible = "silergy,syr827"; +- fcs,suspend-voltage-selector = <1>; +- reg = <0x40>; +- regulator-name = "vdd_cpu"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-enable-ramp-delay = <300>; +- regulator-ramp-delay = <8000>; +- vin-supply = <&vcc_sys>; +- }; +- +- vdd_gpu: syr828@41 { +- compatible = "silergy,syr828"; +- fcs,suspend-voltage-selector = <1>; +- reg = <0x41>; +- regulator-name = "vdd_gpu"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- vin-supply = <&vcc_sys>; +- }; +- +- act8846: act8846@5a { +- compatible = "active-semi,act8846"; +- reg = <0x5a>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; +- system-power-controller; +- +- vp1-supply = <&vcc_sys>; +- vp2-supply = <&vcc_sys>; +- vp3-supply = <&vcc_sys>; +- vp4-supply = <&vcc_sys>; +- inl1-supply = <&vcc_sys>; +- inl2-supply = <&vcc_sys>; +- inl3-supply = <&vcc_20>; +- +- regulators { +- vcc_ddr: REG1 { +- regulator-name = "vcc_ddr"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vcc_io: REG2 { +- regulator-name = "vcc_io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_log: REG3 { +- regulator-name = "vdd_log"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- vcc_20: REG4 { +- regulator-name = "vcc_20"; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- regulator-always-on; +- }; +- +- vccio_sd: REG5 { +- regulator-name = "vccio_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vdd10_lcd: REG6 { +- regulator-name = "vdd10_lcd"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- vcca_18: REG7 { +- regulator-name = "vcca_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcca_33: REG8 { +- regulator-name = "vcca_33"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vcc_lan: REG9 { +- regulator-name = "vcca_lan"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vdd_10: REG10 { +- regulator-name = "vdd_10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- vccio_wl: vcc_18: REG11 { +- regulator-name = "vcc_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vcc18_lcd: REG12 { +- regulator-name = "vcc18_lcd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&io_domains { +- status = "okay"; +- +- audio-supply = <&vccio_wl>; +- bb-supply = <&vcc_io>; +- dvp-supply = <&dovdd_1v8>; +- flash0-supply = <&vcc_flash>; +- flash1-supply = <&vcc_lan>; +- gpio30-supply = <&vcc_io>; +- gpio1830-supply = <&vcc_io>; +- lcdc-supply = <&vcc_io>; +- sdcard-supply = <&vccio_sd>; +- wifi-supply = <&vccio_wl>; +-}; +- +-&pinctrl { +- pcfg_output_high: pcfg-output-high { +- output-high; +- }; +- +- pcfg_output_low: pcfg-output-low { +- output-low; +- }; +- +- pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { +- bias-pull-up; +- drive-strength = <12>; +- }; +- +- act8846 { +- pwr_hold: pwr-hold { +- rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- +- pmic_vsel: pmic-vsel { +- rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- }; +- +- gmac { +- phy_int: phy-int { +- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- phy_pmeb: phy-pmeb { +- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- phy_rst: phy-rst { +- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- }; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <0>; +- rockchip,hw-tshut-polarity = <0>; +- status = "okay"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-firefly-reload.dts b/scripts/dtc/include-prefixes/arm/rk3288-firefly-reload.dts +deleted file mode 100644 +index 9a4a9749c405..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-firefly-reload.dts ++++ /dev/null +@@ -1,392 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device tree file for Firefly Rockchip RK3288 Core board +- * Copyright (c) 2016 Randy Li +- */ +- +-/dts-v1/; +-#include "rk3288-firefly-reload-core.dtsi" +- +-/ { +- model = "Firefly-RK3288-reload"; +- compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288"; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 1>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1800000>; +- +- button-recovery { +- label = "Recovery"; +- linux,code = ; +- press-threshold-microvolt = <0>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- wakeup-source; +- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; +- label = "GPIO Power"; +- linux,code = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_key>; +- }; +- }; +- +- ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- power_led: led-0 { +- gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>; +- label = "firefly:blue:power"; +- pinctrl-names = "default"; +- pinctrl-0 = <&power_led_pin>; +- panic-indicator; +- }; +- +- work_led: led-1 { +- gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>; +- label = "firefly:blue:user"; +- linux,default-trigger = "rc-feedback"; +- pinctrl-names = "default"; +- pinctrl-0 = <&work_led_pin>; +- }; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&hym8563>; +- clock-names = "ext_clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_enable>; +- reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "SPDIF"; +- simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ +- cpu { sound-dai = <&spdif>; }; +- codec { sound-dai = <&spdif_out>; }; +- }; +- }; +- +- spdif_out: spdif-out { +- compatible = "linux,spdif-dit"; +- #sound-dai-cells = <0>; +- }; +- +- vcc_host_5v: usb-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&host_vbus_drv>; +- regulator-name = "vcc_host_5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- vin-supply = <&vcc_5v>; +- }; +- +- vcc_5v: vcc_sys: vsys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc_sd: sdmmc-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_pwr>; +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_otg_5v: usb-otg-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&otg_vbus_drv>; +- regulator-name = "vcc_otg_5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- vin-supply = <&vcc_5v>; +- }; +- +- dovdd_1v8: dovdd-1v8-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&dvp_pwr>; +- regulator-name = "dovdd_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc28_dvp: vcc28-dvp-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&dvp_pwr>; +- regulator-name = "vcc28_dvp"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- vin-supply = <&vcc_io>; +- }; +- +- af_28: af_28-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&dvp_pwr>; +- regulator-name = "af_28"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- vin-supply = <&vcc_io>; +- }; +- +- dvdd_1v2: af_28-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cif_pwr>; +- regulator-name = "dvdd_1v2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- vin-supply = <&vcc_io>; +- }; +- +- vbat_wl: wifi-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vbat_wl"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc_io>; +- }; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_cec_c0>; +- status = "okay"; +-}; +- +-&i2c0 { +- hym8563: hym8563@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "xin32k"; +- interrupt-parent = <&gpio7>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&rtc_int>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- +- codec: es8328@10 { +- compatible = "everest,es8328"; +- DVDD-supply = <&vcca_33>; +- AVDD-supply = <&vcca_33>; +- PVDD-supply = <&vcca_33>; +- HPVDD-supply = <&vcca_33>; +- clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; +- clock-names = "i2s_hclk", "i2s_clk"; +- reg = <0x10>; +- }; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2s { +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vcc_18>; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- card-detect-delay = <200>; +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; +- vmmc-supply = <&vcc_sd>; +- vqmmc-supply = <&vccio_sd>; +- status = "okay"; +-}; +- +-&sdio0 { +- bus-width = <4>; +- cap-sd-highspeed; +- cap-sdio-irq; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-ddr50; +- vmmc-supply = <&vbat_wl>; +- vqmmc-supply = <&vccio_wl>; +- status = "okay"; +-}; +- +-&spdif { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&usb_host1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usbhub_rst>; +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +- +-&pinctrl { +- ir { +- ir_int: ir-int { +- rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- dvp { +- dvp_pwr: dvp-pwr { +- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- cif_pwr: cif-pwr { +- rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- hym8563 { +- rtc_int: rtc-int { +- rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- keys { +- pwr_key: pwr-key { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- leds { +- power_led_pin: power-led-pin { +- rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- work_led_pin: work-led-pin { +- rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdmmc { +- /* +- * Default drive strength isn't enough to achieve even +- * high-speed mode on firefly board so bump up to 12ma. +- */ +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, +- <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, +- <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, +- <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; +- }; +- +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; +- }; +- +- sdmmc_pwr: sdmmc-pwr { +- rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdio { +- wifi_enable: wifi-enable { +- rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb_host { +- host_vbus_drv: host-vbus-drv { +- rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- usbhub_rst: usbhub-rst { +- rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- }; +- +- usb_otg { +- otg_vbus_drv: otg-vbus-drv { +- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-firefly.dts b/scripts/dtc/include-prefixes/arm/rk3288-firefly.dts +deleted file mode 100644 +index 313459dab2e4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-firefly.dts ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2014, 2015 FUKAUMI Naoki +- */ +- +-/dts-v1/; +-#include "rk3288-firefly.dtsi" +- +-/ { +- model = "Firefly-RK3288"; +- compatible = "firefly,firefly-rk3288", "rockchip,rk3288"; +-}; +- +-&ir { +- gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>; +-}; +- +-&pinctrl { +- act8846 { +- pmic_vsel: pmic-vsel { +- rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- }; +- +- ir { +- ir_int: ir-int { +- rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-firefly.dtsi b/scripts/dtc/include-prefixes/arm/rk3288-firefly.dtsi +deleted file mode 100644 +index 7fb582302b32..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-firefly.dtsi ++++ /dev/null +@@ -1,574 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2014, 2015 FUKAUMI Naoki +- */ +- +-#include +-#include "rk3288.dtsi" +- +-/ { +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 1>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1800000>; +- +- button-recovery { +- label = "Recovery"; +- linux,code = ; +- press-threshold-microvolt = <0>; +- }; +- }; +- +- dovdd_1v8: dovdd-1v8-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "dovdd_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc28_dvp>; +- }; +- +- ext_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- clock-output-names = "ext_gmac"; +- }; +- +- ir: ir-receiver { +- compatible = "gpio-ir-receiver"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ir_int>; +- }; +- +- keys: gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- wakeup-source; +- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; +- label = "GPIO Power"; +- linux,code = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_key>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- work_led: led-0 { +- gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>; +- label = "firefly:blue:user"; +- linux,default-trigger = "rc-feedback"; +- pinctrl-names = "default"; +- pinctrl-0 = <&work_led_pin>; +- }; +- +- power_led: led-1 { +- gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>; +- label = "firefly:green:power"; +- linux,default-trigger = "default-on"; +- pinctrl-names = "default"; +- pinctrl-0 = <&power_led_pin>; +- }; +- }; +- +- vbat_wl: vcc_sys: vsys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc_sd: sdmmc-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_pwr>; +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_flash: flash-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_flash"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_5v: usb-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_host_5v: usb-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&host_vbus_drv>; +- regulator-name = "vcc_host_5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- vin-supply = <&vcc_5v>; +- }; +- +- vcc_otg_5v: usb-otg-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&otg_vbus_drv>; +- regulator-name = "vcc_otg_5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- vin-supply = <&vcc_5v>; +- }; +- +- /* +- * A TT8142 creates both dovdd_1v8 and vcc28_dvp, controlled +- * by the dvp_pwr pin. +- */ +- vcc28_dvp: vcc28-dvp-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&dvp_pwr>; +- regulator-name = "vcc28_dvp"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- vin-supply = <&vcc_io>; +- }; +-}; +- +-&cpu0 { +- cpu0-supply = <&vdd_cpu>; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- disable-wp; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; +- vmmc-supply = <&vcc_io>; +- vqmmc-supply = <&vcc_flash>; +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_MAC>; +- assigned-clock-parents = <&ext_gmac>; +- clock_in_out = "input"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; +- phy-supply = <&vcc_lan>; +- phy-mode = "rgmii"; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 1000000>; +- snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; +- tx_delay = <0x30>; +- rx_delay = <0x10>; +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c5>; +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- status = "okay"; +- +- vdd_cpu: syr827@40 { +- compatible = "silergy,syr827"; +- fcs,suspend-voltage-selector = <1>; +- reg = <0x40>; +- regulator-name = "vdd_cpu"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-enable-ramp-delay = <300>; +- regulator-ramp-delay = <8000>; +- vin-supply = <&vcc_sys>; +- }; +- +- vdd_gpu: syr828@41 { +- compatible = "silergy,syr828"; +- fcs,suspend-voltage-selector = <1>; +- reg = <0x41>; +- regulator-name = "vdd_gpu"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- vin-supply = <&vcc_sys>; +- }; +- +- hym8563: hym8563@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "xin32k"; +- interrupt-parent = <&gpio7>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&rtc_int>; +- }; +- +- act8846: act8846@5a { +- compatible = "active-semi,act8846"; +- reg = <0x5a>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; +- system-power-controller; +- +- vp1-supply = <&vcc_sys>; +- vp2-supply = <&vcc_sys>; +- vp3-supply = <&vcc_sys>; +- vp4-supply = <&vcc_sys>; +- inl1-supply = <&vcc_sys>; +- inl2-supply = <&vcc_sys>; +- inl3-supply = <&vcc_20>; +- +- regulators { +- vcc_ddr: REG1 { +- regulator-name = "vcc_ddr"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vcc_io: REG2 { +- regulator-name = "vcc_io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_log: REG3 { +- regulator-name = "vdd_log"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- vcc_20: REG4 { +- regulator-name = "vcc_20"; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- regulator-always-on; +- }; +- +- vccio_sd: REG5 { +- regulator-name = "vccio_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd10_lcd: REG6 { +- regulator-name = "vdd10_lcd"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- vcca_18: REG7 { +- regulator-name = "vcca_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vcca_33: REG8 { +- regulator-name = "vcca_33"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vcc_lan: REG9 { +- regulator-name = "vcc_lan"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vdd_10: REG10 { +- regulator-name = "vdd_10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- vccio_wl: vcc_18: REG11 { +- regulator-name = "vcc_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcc18_lcd: REG12 { +- regulator-name = "vcc18_lcd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&io_domains { +- status = "okay"; +- +- audio-supply = <&vcca_33>; +- bb-supply = <&vcc_io>; +- dvp-supply = <&dovdd_1v8>; +- flash0-supply = <&vcc_flash>; +- flash1-supply = <&vcc_lan>; +- gpio30-supply = <&vcc_io>; +- gpio1830-supply = <&vcc_io>; +- lcdc-supply = <&vcc_io>; +- sdcard-supply = <&vccio_sd>; +- wifi-supply = <&vccio_wl>; +-}; +- +-&pinctrl { +- pcfg_output_high: pcfg-output-high { +- output-high; +- }; +- +- pcfg_output_low: pcfg-output-low { +- output-low; +- }; +- +- pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { +- bias-pull-up; +- drive-strength = <12>; +- }; +- +- act8846 { +- pwr_hold: pwr-hold { +- rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- }; +- +- dvp { +- dvp_pwr: dvp-pwr { +- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- gmac { +- phy_int: phy-int { +- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- phy_pmeb: phy-pmeb { +- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- phy_rst: phy-rst { +- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- }; +- +- hym8563 { +- rtc_int: rtc-int { +- rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- keys { +- pwr_key: pwr-key { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- leds { +- power_led_pin: power-led-pin { +- rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- work_led_pin: work-led-pin { +- rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdmmc { +- /* +- * Default drive strength isn't enough to achieve even +- * high-speed mode on firefly board so bump up to 12ma. +- */ +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, +- <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, +- <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, +- <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; +- }; +- +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; +- }; +- +- sdmmc_pwr: sdmmc-pwr { +- rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb_host { +- host_vbus_drv: host-vbus-drv { +- rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- usbhub_rst: usbhub-rst { +- rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- }; +- +- usb_otg { +- otg_vbus_drv: otg-vbus-drv { +- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&saradc { +- vref-supply = <&vcc_18>; +- status = "okay"; +-}; +- +-&sdio0 { +- bus-width = <4>; +- disable-wp; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>; +- vmmc-supply = <&vbat_wl>; +- vqmmc-supply = <&vccio_wl>; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- card-detect-delay = <200>; +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; +- vmmc-supply = <&vcc_sd>; +- vqmmc-supply = <&vccio_sd>; +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_clk>, <&spi0_cs0>, <&spi0_tx>, <&spi0_rx>, <&spi0_cs1>; +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <0>; +- rockchip,hw-tshut-polarity = <0>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&usb_host1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usbhub_rst>; +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-miqi.dts b/scripts/dtc/include-prefixes/arm/rk3288-miqi.dts +deleted file mode 100644 +index 713f55e143c6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-miqi.dts ++++ /dev/null +@@ -1,441 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Heiko Stuebner +- */ +- +-/dts-v1/; +-#include +-#include "rk3288.dtsi" +- +-/ { +- model = "mqmaker MiQi"; +- compatible = "mqmaker,miqi", "rockchip,rk3288"; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- ext_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- clock-output-names = "ext_gmac"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- work_led: led-0 { +- gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; +- label = "miqi:green:user"; +- linux,default-trigger = "timer"; +- }; +- }; +- +- vcc_flash: flash-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_flash"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_host: usb-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&host_vbus_drv>; +- regulator-name = "vcc_host"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_sd: sdmmc-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_pwr>; +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_sys: vsys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; +- vmmc-supply = <&vcc_io>; +- vqmmc-supply = <&vcc_flash>; +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_MAC>; +- assigned-clock-parents = <&ext_gmac>; +- clock_in_out = "input"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; +- phy-supply = <&vcc_lan>; +- phy-mode = "rgmii"; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 1000000>; +- snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; +- tx_delay = <0x30>; +- rx_delay = <0x10>; +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c5>; +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- status = "okay"; +- +- vdd_cpu: syr827@40 { +- compatible = "silergy,syr827"; +- fcs,suspend-voltage-selector = <1>; +- reg = <0x40>; +- regulator-name = "vdd_cpu"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-enable-ramp-delay = <300>; +- regulator-ramp-delay = <8000>; +- vin-supply = <&vcc_sys>; +- }; +- +- vdd_gpu: syr828@41 { +- compatible = "silergy,syr828"; +- fcs,suspend-voltage-selector = <1>; +- reg = <0x41>; +- regulator-name = "vdd_gpu"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- vin-supply = <&vcc_sys>; +- }; +- +- hym8563: hym8563@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "xin32k"; +- }; +- +- act8846: act8846@5a { +- compatible = "active-semi,act8846"; +- reg = <0x5a>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_vsel>; +- system-power-controller; +- +- vp1-supply = <&vcc_sys>; +- vp2-supply = <&vcc_sys>; +- vp3-supply = <&vcc_sys>; +- vp4-supply = <&vcc_sys>; +- inl1-supply = <&vcc_sys>; +- inl2-supply = <&vcc_sys>; +- inl3-supply = <&vcc_20>; +- +- regulators { +- vcc_ddr: REG1 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- }; +- +- vcc_io: REG2 { +- regulator-name = "vcc_io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_log: REG3 { +- regulator-name = "vdd_log"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- vcc_20: REG4 { +- regulator-name = "vcc_20"; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- regulator-always-on; +- }; +- +- vccio_sd: REG5 { +- regulator-name = "vccio_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd10_lcd: REG6 { +- regulator-name = "vdd10_lcd"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- vcca_18: REG7 { +- regulator-name = "vcca_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vcca_33: REG8 { +- regulator-name = "vcca_33"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vcc_lan: REG9 { +- regulator-name = "vcc_lan"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vdd_10: REG10 { +- regulator-name = "vdd_10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- vcc_18: REG11 { +- regulator-name = "vcc_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcc18_lcd: REG12 { +- regulator-name = "vcc18_lcd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&io_domains { +- status = "okay"; +- +- audio-supply = <&vcca_33>; +- flash0-supply = <&vcc_flash>; +- flash1-supply = <&vcc_lan>; +- gpio30-supply = <&vcc_io>; +- gpio1830-supply = <&vcc_io>; +- lcdc-supply = <&vcc_io>; +- sdcard-supply = <&vccio_sd>; +- wifi-supply = <&vcc_18>; +-}; +- +-&pinctrl { +- pcfg_output_high: pcfg-output-high { +- output-high; +- }; +- +- pcfg_output_low: pcfg-output-low { +- output-low; +- }; +- +- pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { +- bias-pull-up; +- drive-strength = <12>; +- }; +- +- act8846 { +- pmic_int: pmic-int { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- pmic_sleep: pmic-sleep { +- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- +- pmic_vsel: pmic-vsel { +- rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- }; +- +- gmac { +- phy_int: phy-int { +- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- phy_pmeb: phy-pmeb { +- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- phy_rst: phy-rst { +- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- }; +- +- sdmmc { +- /* +- * Default drive strength isn't enough to achieve even +- * high-speed mode on firefly board so bump up to 12ma. +- */ +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, +- <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, +- <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, +- <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; +- }; +- +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; +- }; +- +- sdmmc_pwr: sdmmc-pwr { +- rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb_host { +- host_vbus_drv: host-vbus-drv { +- rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&saradc { +- vref-supply = <&vcc_18>; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- card-detect-delay = <200>; +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; +- vmmc-supply = <&vcc_sd>; +- vqmmc-supply = <&vccio_sd>; +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <0>; +- rockchip,hw-tshut-polarity = <0>; +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&usb_host1 { +- status = "okay"; +-}; +- +-&usb_otg { +- /* +- * The otg controller is the only system power source, +- * so needs to always stay in device mode. +- */ +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-phycore-rdk.dts b/scripts/dtc/include-prefixes/arm/rk3288-phycore-rdk.dts +deleted file mode 100644 +index 1e33859de484..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-phycore-rdk.dts ++++ /dev/null +@@ -1,264 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device tree file for Phytec PCM-947 carrier board +- * Copyright (C) 2017 PHYTEC Messtechnik GmbH +- * Author: Wadim Egorov +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "rk3288-phycore-som.dtsi" +- +-/ { +- model = "Phytec RK3288 PCM-947"; +- compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288"; +- +- user_buttons: user-buttons { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&user_button_pins>; +- +- button@0 { +- label = "home"; +- linux,code = ; +- gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>; +- wakeup-source; +- }; +- +- button@1 { +- label = "menu"; +- linux,code = ; +- gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; +- wakeup-source; +- }; +- }; +- +- vcc_host0_5v: usb-host0-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&host0_vbus_drv>; +- regulator-name = "vcc_host0_5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- vin-supply = <&vdd_in_otg_out>; +- }; +- +- vcc_host1_5v: usb-host1-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&host1_vbus_drv>; +- regulator-name = "vcc_host1_5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- vin-supply = <&vdd_in_otg_out>; +- }; +- +- vcc_otg_5v: usb-otg-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&otg_vbus_drv>; +- regulator-name = "vcc_otg_5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- vin-supply = <&vdd_in_otg_out>; +- }; +-}; +- +-&gmac { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- +- touchscreen@44 { +- compatible = "st,stmpe811"; +- reg = <0x44>; +- }; +- +- adc@64 { +- compatible = "maxim,max1037"; +- reg = <0x64>; +- }; +- +- i2c_rtc: rtc@68 { +- compatible = "rv4162"; +- reg = <0x68>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_rtc_int>; +- interrupt-parent = <&gpio5>; +- interrupts = <10 0>; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +- +- i2c_eeprom_cb: eeprom@51 { +- compatible = "atmel,24c32"; +- reg = <0x51>; +- pagesize = <32>; +- }; +-}; +- +-&i2c4 { +- status = "okay"; +- +- /* PCA9533 - 4-bit LED dimmer */ +- leddim: leddimmer@62 { +- compatible = "nxp,pca9533"; +- reg = <0x62>; +- +- led1 { +- label = "red:user1"; +- linux,default-trigger = "none"; +- type = ; +- }; +- +- led2 { +- label = "green:user2"; +- linux,default-trigger = "none"; +- type = ; +- }; +- +- led3 { +- label = "blue:user3"; +- linux,default-trigger = "none"; +- type = ; +- }; +- +- led4 { +- label = "red:user4"; +- linux,default-trigger = "none"; +- type = ; +- }; +- }; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&pinctrl { +- pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { +- bias-pull-up; +- drive-strength = <12>; +- }; +- +- buttons { +- user_button_pins: user-button-pins { +- /* button 1 */ +- rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, +- /* button 2 */ +- <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- rv4162 { +- i2c_rtc_int: i2c-rtc-int { +- rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- sdmmc { +- /* +- * Default drive strength isn't enough to achieve even +- * high-speed mode on pcm-947 board so bump up to 12 mA. +- */ +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, +- <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, +- <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, +- <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; +- }; +- +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; +- }; +- +- sdmmc_pwr: sdmmc-pwr { +- rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- touchscreen { +- ts_irq_pin: ts-irq-pin { +- rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb_host { +- host0_vbus_drv: host0-vbus-drv { +- rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- host1_vbus_drv: host1-vbus-drv { +- rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb_otg { +- otg_vbus_drv: otg-vbus-drv { +- rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- card-detect-delay = <200>; +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- vmmc-supply = <&vdd_sd>; +- vqmmc-supply = <&vdd_io_sd>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host1 { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-phycore-som.dtsi b/scripts/dtc/include-prefixes/arm/rk3288-phycore-som.dtsi +deleted file mode 100644 +index e43887c9635f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-phycore-som.dtsi ++++ /dev/null +@@ -1,439 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device tree file for Phytec phyCORE-RK3288 SoM +- * Copyright (C) 2017 PHYTEC Messtechnik GmbH +- * Author: Wadim Egorov +- */ +- +-#include +-#include "rk3288.dtsi" +- +-/ { +- model = "Phytec RK3288 phyCORE"; +- compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288"; +- +- /* +- * Set the minimum memory size here and +- * let the bootloader set the real size. +- */ +- memory { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x8000000>; +- }; +- +- aliases { +- rtc0 = &i2c_rtc; +- rtc1 = &rk818; +- }; +- +- ext_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- clock-output-names = "ext_gmac"; +- }; +- +- leds: user-leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&user_led_pin>; +- +- user_led: led-0 { +- label = "green_led"; +- gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "keep"; +- }; +- }; +- +- vdd_emmc_io: vdd-emmc-io { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_emmc_io"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vdd_3v3_io>; +- }; +- +- vdd_in_otg_out: vdd-in-otg-out { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_in_otg_out"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- vdd_misc_1v8: vdd-misc-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_misc_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +-}; +- +-&emmc { +- status = "okay"; +- bus-width = <8>; +- cap-mmc-highspeed; +- disable-wp; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; +- vmmc-supply = <&vdd_3v3_io>; +- vqmmc-supply = <&vdd_emmc_io>; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_MAC>; +- assigned-clock-parents = <&ext_gmac>; +- clock_in_out = "input"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins &phy_rst &phy_int>; +- phy-handle = <&phy0>; +- phy-supply = <&vdd_eth_2v5>; +- phy-mode = "rgmii-id"; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 1000000>; +- snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; +- tx_delay = <0x0>; +- rx_delay = <0x0>; +- +- mdio0 { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- interrupt-parent = <&gpio4>; +- interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +- ti,rx-internal-delay = ; +- ti,tx-internal-delay = ; +- ti,fifo-depth = ; +- enet-phy-lane-no-swap; +- ti,clk-output-sel = ; +- }; +- }; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c5>; +-}; +- +-&io_domains { +- status = "okay"; +- sdcard-supply = <&vdd_io_sd>; +- flash0-supply = <&vdd_emmc_io>; +- flash1-supply = <&vdd_misc_1v8>; +- gpio1830-supply = <&vdd_3v3_io>; +- gpio30-supply = <&vdd_3v3_io>; +- bb-supply = <&vdd_3v3_io>; +- dvp-supply = <&vdd_3v3_io>; +- lcdc-supply = <&vdd_3v3_io>; +- wifi-supply = <&vdd_3v3_io>; +- audio-supply = <&vdd_3v3_io>; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <400000>; +- +- rk818: pmic@1c { +- compatible = "rockchip,rk818"; +- reg = <0x1c>; +- interrupt-parent = <&gpio0>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int>; +- rockchip,system-power-controller; +- wakeup-source; +- #clock-cells = <1>; +- +- vcc1-supply = <&vdd_sys>; +- vcc2-supply = <&vdd_sys>; +- vcc3-supply = <&vdd_sys>; +- vcc4-supply = <&vdd_sys>; +- boost-supply = <&vdd_in_otg_out>; +- vcc6-supply = <&vdd_sys>; +- vcc7-supply = <&vdd_misc_1v8>; +- vcc8-supply = <&vdd_misc_1v8>; +- vcc9-supply = <&vdd_3v3_io>; +- vddio-supply = <&vdd_3v3_io>; +- +- regulators { +- vdd_log: DCDC_REG1 { +- regulator-name = "vdd_log"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: DCDC_REG2 { +- regulator-name = "vdd_gpu"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1250000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vdd_3v3_io: DCDC_REG4 { +- regulator-name = "vdd_3v3_io"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vdd_sys: DCDC_BOOST { +- regulator-name = "vdd_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <5000000>; +- }; +- }; +- +- /* vcc9 */ +- vdd_sd: SWITCH_REG { +- regulator-name = "vdd_sd"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- /* vcc6 */ +- vdd_eth_2v5: LDO_REG2 { +- regulator-name = "vdd_eth_2v5"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <2500000>; +- }; +- }; +- +- /* vcc7 */ +- vdd_1v0: LDO_REG3 { +- regulator-name = "vdd_1v0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- /* vcc8 */ +- vdd_1v8_lcd_ldo: LDO_REG4 { +- regulator-name = "vdd_1v8_lcd_ldo"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- /* vcc8 */ +- vdd_1v0_lcd: LDO_REG6 { +- regulator-name = "vdd_1v0_lcd"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- /* vcc7 */ +- vdd_1v8_ldo: LDO_REG7 { +- regulator-name = "vdd_1v8_ldo"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- /* vcc9 */ +- vdd_io_sd: LDO_REG9 { +- regulator-name = "vdd_io_sd"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +- +- /* M24C32-D */ +- i2c_eeprom: eeprom@50 { +- compatible = "atmel,24c32"; +- reg = <0x50>; +- pagesize = <32>; +- }; +- +- vdd_cpu: regulator@60 { +- compatible = "fcs,fan53555"; +- reg = <0x60>; +- fcs,suspend-voltage-selector = <1>; +- regulator-always-on; +- regulator-boot-on; +- regulator-enable-ramp-delay = <300>; +- regulator-name = "vdd_cpu"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1430000>; +- regulator-ramp-delay = <8000>; +- vin-supply = <&vdd_sys>; +- }; +-}; +- +-&pinctrl { +- pcfg_output_high: pcfg-output-high { +- output-high; +- }; +- +- emmc { +- /* +- * We run eMMC at max speed; bump up drive strength. +- * We also have external pulls, so disable the internal ones. +- */ +- emmc_clk: emmc-clk { +- rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_12ma>; +- }; +- +- emmc_cmd: emmc-cmd { +- rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_12ma>; +- }; +- +- emmc_bus8: emmc-bus8 { +- rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_12ma>, +- <3 RK_PA1 2 &pcfg_pull_none_12ma>, +- <3 RK_PA2 2 &pcfg_pull_none_12ma>, +- <3 RK_PA3 2 &pcfg_pull_none_12ma>, +- <3 RK_PA4 2 &pcfg_pull_none_12ma>, +- <3 RK_PA5 2 &pcfg_pull_none_12ma>, +- <3 RK_PA6 2 &pcfg_pull_none_12ma>, +- <3 RK_PA7 2 &pcfg_pull_none_12ma>; +- }; +- }; +- +- gmac { +- phy_int: phy-int { +- rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- phy_rst: phy-rst { +- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- }; +- +- leds { +- user_led_pin: user-led-pin { +- rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- }; +- +- pmic { +- pmic_int: pmic-int { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- /* Pin for switching state between sleep and non-sleep state */ +- pmic_sleep: pmic-sleep { +- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vdd_1v8_ldo>; +-}; +- +-&spi2 { +- status = "okay"; +- +- serial_flash: flash@0 { +- compatible = "micron,n25q128a13", "jedec,spi-nor"; +- reg = <0x0>; +- spi-max-frequency = <50000000>; +- m25p,fast-read; +- #address-cells = <1>; +- #size-cells = <1>; +- status = "okay"; +- }; +-}; +- +-&tsadc { +- status = "okay"; +- rockchip,hw-tshut-mode = <0>; +- rockchip,hw-tshut-polarity = <0>; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-popmetal.dts b/scripts/dtc/include-prefixes/arm/rk3288-popmetal.dts +deleted file mode 100644 +index 8c7376d64bc4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-popmetal.dts ++++ /dev/null +@@ -1,513 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2014, 2015 Andy Yan +- */ +- +-/dts-v1/; +-#include +-#include "rk3288.dtsi" +- +-/ { +- model = "PopMetal-RK3288"; +- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- ext_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "ext_gmac"; +- #clock-cells = <0>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pwrbtn>; +- +- power { +- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "GPIO Key Power"; +- linux,input-type = <1>; +- wakeup-source; +- debounce-interval = <100>; +- }; +- }; +- +- ir: ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ir_int>; +- }; +- +- vcc_flash: flash-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_flash"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_sd: sdmmc-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_pwr>; +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_sys: vsys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* +- * A PT5128 creates both dovdd_1v8 and vcc28_dvp, controlled +- * by the dvp_pwr pin. +- */ +- vcc18_dvp: vcc18-dvp-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc18-dvp"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc28_dvp>; +- }; +- +- vcc28_dvp: vcc28-dvp-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&dvp_pwr>; +- regulator-name = "vcc28_dvp"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- vin-supply = <&vcc_io>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; +- vmmc-supply = <&vcc_io>; +- vqmmc-supply = <&vcc_flash>; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- card-detect-delay = <200>; +- disable-wp; /* wp not hooked up */ +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- vmmc-supply = <&vcc_sd>; +- vqmmc-supply = <&vccio_sd>; +- status = "okay"; +-}; +- +-&gmac { +- phy-supply = <&vcc_lan>; +- phy-mode = "rgmii"; +- clock_in_out = "input"; +- snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 1000000>; +- assigned-clocks = <&cru SCLK_MAC>; +- assigned-clock-parents = <&ext_gmac>; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- tx_delay = <0x30>; +- rx_delay = <0x10>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c5>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <400000>; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int &global_pwroff>; +- rockchip,system-power-controller; +- wakeup-source; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc6-supply = <&vcc_sys>; +- vcc7-supply = <&vcc_sys>; +- vcc8-supply = <&vcc_18>; +- vcc9-supply = <&vcc_io>; +- vcc10-supply = <&vcc_io>; +- vcc11-supply = <&vcc_sys>; +- vcc12-supply = <&vcc_io>; +- vddio-supply = <&vcc_io>; +- +- regulators { +- vdd_cpu: DCDC_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-name = "vdd_arm"; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: DCDC_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-name = "vdd_gpu"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc_ddr"; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_io: DCDC_REG4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc_io"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_lan: LDO_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc_lan"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vccio_sd: LDO_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vccio_sd"; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_10: LDO_REG3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-name = "vdd_10"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc18_lcd: LDO_REG4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc18_lcd"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- ldo5: LDO_REG5 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "ldo5"; +- }; +- +- vdd10_lcd: LDO_REG6 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-name = "vdd10_lcd"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc_18: LDO_REG7 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc_18"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcca_33: LDO_REG8 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcca_33"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vccio_wl: SWITCH_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vccio_wl"; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_lcd: SWITCH_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc_lcd"; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- ak8963: ak8963@d { +- compatible = "asahi-kasei,ak8975"; +- reg = <0x0d>; +- interrupt-parent = <&gpio8>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&comp_int>; +- vdd-supply = <&vcc_io>; +- vid-supply = <&vcc_io>; +- }; +- +- l3g4200d: l3g4200d@69 { +- compatible = "st,l3g4200d-gyro"; +- st,drdy-int-pin = <2>; +- reg = <0x69>; +- vdd-supply = <&vcc_io>; +- vddio-supply = <&vcc_io>; +- }; +- +- mma8452: mma8452@1d { +- compatible = "fsl,mma8452"; +- reg = <0x1d>; +- interrupt-parent = <&gpio8>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&gsensor_int>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&io_domains { +- status = "okay"; +- +- audio-supply = <&vcca_33>; +- bb-supply = <&vcc_io>; +- dvp-supply = <&vcc18_dvp>; +- flash0-supply = <&vcc_flash>; +- flash1-supply = <&vcc_lan>; +- gpio30-supply = <&vcc_io>; +- gpio1830-supply = <&vcc_io>; +- lcdc-supply = <&vcc_io>; +- sdcard-supply = <&vccio_sd>; +- wifi-supply = <&vccio_wl>; +-}; +- +-&pinctrl { +- ak8963 { +- comp_int: comp-int { +- rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- buttons { +- pwrbtn: pwrbtn { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- dvp { +- dvp_pwr: dvp-pwr { +- rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- ir { +- ir_int: ir-int { +- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- mma8452 { +- gsensor_int: gsensor-int { +- rockchip,pins = <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- pmic { +- pmic_int: pmic-int { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- sdmmc { +- sdmmc_pwr: sdmmc-pwr { +- rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <0>; +- rockchip,hw-tshut-polarity = <0>; +- status = "okay"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&uart4 { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-r89.dts b/scripts/dtc/include-prefixes/arm/rk3288-r89.dts +deleted file mode 100644 +index 55467bc30fa6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-r89.dts ++++ /dev/null +@@ -1,400 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2015 Heiko Stuebner +- */ +- +-/dts-v1/; +-#include +-#include +-#include "rk3288.dtsi" +- +-/ { +- model = "Netxeon R89"; +- compatible = "netxeon,r89", "rockchip,rk3288"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- ext_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "ext_gmac"; +- #clock-cells = <0>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pwrbtn>; +- +- power { +- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "GPIO Key Power"; +- linux,input-type = <1>; +- wakeup-source; +- debounce-interval = <100>; +- }; +- }; +- +- ir: ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ir_int>; +- }; +- +- vcc_host: vcc-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&host_vbus_drv>; +- regulator-name = "vcc_host"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc_otg: vcc-otg-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&otg_vbus_drv>; +- regulator-name = "vcc_otg"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc_sdmmc: sdmmc-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "sdmmc-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; +- startup-delay-us = <100000>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_sys: sys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "sys-supply"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&gmac { +- phy-supply = <&vcc_lan>; +- phy-mode = "rgmii"; +- clock_in_out = "input"; +- snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 1000000>; +- assigned-clocks = <&cru SCLK_MAC>; +- assigned-clock-parents = <&ext_gmac>; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- tx_delay = <0x30>; +- rx_delay = <0x10>; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- vdd_cpu: pmic@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "VDD_CPU"; +- regulator-enable-ramp-delay = <300>; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <8000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vdd_gpu: pmic@41 { +- compatible = "silergy,syr828"; +- reg = <0x41>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "VDD_GPU"; +- regulator-enable-ramp-delay = <300>; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <8000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +- rtc@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- clock-output-names = "xin32k"; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int>; +- }; +- +- act8846: pmic@5a { +- compatible = "active-semi,act8846"; +- reg = <0x5a>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; +- system-power-controller; +- +- regulators { +- vcc_ddr: REG1 { +- regulator-name = "VCC_DDR"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vcc_io: REG2 { +- regulator-name = "VCC_IO"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_log: REG3 { +- regulator-name = "VDD_LOG"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- vcc_20: REG4 { +- regulator-name = "VCC_20"; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- regulator-always-on; +- }; +- +- vccio_sd: REG5 { +- regulator-name = "VCCIO_SD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd10_lcd: REG6 { +- regulator-name = "VDD10_LCD"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- vcc_wl: REG7 { +- regulator-name = "VCC_WL"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vcca_33: REG8 { +- regulator-name = "VCCA_33"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vcc_lan: REG9 { +- regulator-name = "VCC_LAN"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_10: REG10 { +- regulator-name = "VDD_10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- vcc_18: REG11 { +- regulator-name = "VCC_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcc18_lcd: REG12 { +- regulator-name = "VCC18_LCD"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&pinctrl { +- pcfg_output_high: pcfg-output-high { +- output-high; +- }; +- +- pcfg_output_low: pcfg-output-low { +- output-low; +- }; +- +- act8846 { +- pmic_vsel: pmic-vsel { +- rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- +- pwr_hold: pwr-hold { +- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- }; +- +- buttons { +- pwrbtn: pwrbtn { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- ir { +- ir_int: ir-int { +- rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- pmic { +- pmic_int: pmic-int { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- usb { +- host_vbus_drv: host-vbus-drv { +- rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- otg_vbus_drv: otg-vbus-drv { +- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vcc_18>; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- card-detect-delay = <200>; +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +- vmmc-supply = <&vcc_sdmmc>; +- vqmmc-supply = <&vccio_sd>; +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <0>; +- rockchip,hw-tshut-polarity = <0>; +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&uart4 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host1 { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-rock-pi-n8.dts b/scripts/dtc/include-prefixes/arm/rk3288-rock-pi-n8.dts +deleted file mode 100644 +index b19593021713..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-rock-pi-n8.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd +- * Copyright (c) 2019 Vamrs Limited +- * Copyright (c) 2019 Amarula Solutions(India) +- */ +- +-/dts-v1/; +-#include "rk3288.dtsi" +-#include +-#include "rk3288-vmarc-som.dtsi" +- +-/ { +- model = "Radxa ROCK Pi N8"; +- compatible = "radxa,rockpi-n8", "vamrs,rk3288-vmarc-som", +- "rockchip,rk3288"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-rock2-som.dtsi b/scripts/dtc/include-prefixes/arm/rk3288-rock2-som.dtsi +deleted file mode 100644 +index 76363b8afcb9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-rock2-som.dtsi ++++ /dev/null +@@ -1,273 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-#include +-#include "rk3288.dtsi" +- +-/ { +- memory@0 { +- reg = <0x0 0x0 0x0 0x80000000>; +- device_type = "memory"; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- pinctrl-0 = <&emmc_reset>; +- pinctrl-names = "default"; +- reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; +- }; +- +- ext_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- clock-output-names = "ext_gmac"; +- }; +- +- vcc_flash: flash-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_flash"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- startup-delay-us = <150>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_sys: vsys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&cpu0 { +- cpu0-supply = <&vdd_cpu>; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- disable-wp; +- non-removable; +- mmc-pwrseq = <&emmc_pwrseq>; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +- vmmc-supply = <&vcc_io>; +- vqmmc-supply = <&vcc_flash>; +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_MAC>; +- assigned-clock-parents = <&ext_gmac>; +- clock_in_out = "input"; +- phy-mode = "rgmii"; +- phy-supply = <&vccio_pmu>; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins &phy_rst>; +- snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 30000>; +- rx_delay = <0x10>; +- tx_delay = <0x30>; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- act8846: act8846@5a { +- compatible = "active-semi,act8846"; +- reg = <0x5a>; +- system-power-controller; +- inl1-supply = <&vcc_io>; +- inl2-supply = <&vcc_sys>; +- inl3-supply = <&vcc_20>; +- vp1-supply = <&vcc_sys>; +- vp2-supply = <&vcc_sys>; +- vp3-supply = <&vcc_sys>; +- vp4-supply = <&vcc_sys>; +- +- regulators { +- vcc_ddr: REG1 { +- regulator-name = "VCC_DDR"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vcc_io: vccio_codec: REG2 { +- regulator-name = "VCC_IO"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_log: REG3 { +- regulator-name = "VDD_LOG"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- vcc_20: REG4 { +- regulator-name = "VCC_20"; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- regulator-always-on; +- }; +- +- vccio_sd: REG5 { +- regulator-name = "VCCIO_SD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd10_lcd: REG6 { +- regulator-name = "VDD10_LCD"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- vcca_codec: REG7 { +- regulator-name = "VCCA_CODEC"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vcca_tp: REG8 { +- regulator-name = "VCCA_TP"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vccio_pmu: REG9 { +- regulator-name = "VCCIO_PMU"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_10: REG10 { +- regulator-name = "VDD_10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- vcc_18: REG11 { +- regulator-name = "VCC_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcc18_lcd: REG12 { +- regulator-name = "VCC18_LCD"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- }; +- }; +- +- vdd_cpu: syr827@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- fcs,suspend-voltage-selector = <1>; +- regulator-always-on; +- regulator-boot-on; +- regulator-enable-ramp-delay = <300>; +- regulator-name = "vdd_cpu"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <8000>; +- vin-supply = <&vcc_sys>; +- }; +- +- vdd_gpu: syr828@41 { +- compatible = "silergy,syr828"; +- reg = <0x41>; +- fcs,suspend-voltage-selector = <1>; +- regulator-always-on; +- regulator-enable-ramp-delay = <300>; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1350000>; +- regulator-name = "vdd_gpu"; +- regulator-ramp-delay = <8000>; +- vin-supply = <&vcc_sys>; +- }; +-}; +- +-&io_domains { +- status = "okay"; +- +- audio-supply = <&vcc_io>; +- bb-supply = <&vcc_io>; +- dvp-supply = <&vcc_18>; +- flash0-supply = <&vcc_flash>; +- flash1-supply = <&vccio_pmu>; +- gpio30-supply = <&vccio_pmu>; +- gpio1830-supply = <&vcc_io>; +- lcdc-supply = <&vcc_io>; +- sdcard-supply = <&vccio_sd>; +- wifi-supply = <&vcc_18>; +-}; +- +-&pinctrl { +- pcfg_output_high: pcfg-output-high { +- output-high; +- }; +- +- emmc { +- emmc_reset: emmc-reset { +- rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- gmac { +- phy_rst: phy-rst { +- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- }; +-}; +- +-&saradc { +- vref-supply = <&vcc_18>; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ +- status = "okay"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-rock2-square.dts b/scripts/dtc/include-prefixes/arm/rk3288-rock2-square.dts +deleted file mode 100644 +index c4d1d142d8c6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-rock2-square.dts ++++ /dev/null +@@ -1,288 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-/dts-v1/; +-#include +-#include "rk3288-rock2-som.dtsi" +- +-/ { +- model = "Radxa Rock 2 Square"; +- compatible = "radxa,rock2-square", "rockchip,rk3288"; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 1>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1800000>; +- +- button-recovery { +- label = "Recovery"; +- linux,code = ; +- press-threshold-microvolt = <0>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; +- label = "GPIO Power"; +- linux,code = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_key>; +- wakeup-source; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- heartbeat_led: led-0 { +- gpios = <&gpio7 RK_PB7 GPIO_ACTIVE_LOW>; +- label = "rock2:green:state1"; +- linux,default-trigger = "heartbeat"; +- }; +- +- mmc_led: led-1 { +- gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; +- label = "rock2:blue:state2"; +- linux,default-trigger = "mmc0"; +- }; +- }; +- +- ir: ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ir_int>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "SPDIF"; +- simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ +- cpu { sound-dai = <&spdif>; }; +- codec { sound-dai = <&spdif_out>; }; +- }; +- }; +- +- sata_pwr: sata-prw-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sata_pwr_en>; +- /* Always turn on the 5V sata power connector */ +- regulator-always-on; +- regulator-name = "sata_pwr"; +- }; +- +- spdif_out: spdif-out { +- compatible = "linux,spdif-dit"; +- #sound-dai-cells = <0>; +- }; +- +- sound-i2s { +- compatible = "rockchip,rk3288-hdmi-analog"; +- pinctrl-names = "default"; +- pinctrl-0 = <&phone_ctl>, <&hp_det>; +- rockchip,audio-codec = <&es8388>; +- rockchip,hp-det-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; +- rockchip,hp-en-gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>; +- rockchip,i2s-controller = <&i2s>; +- rockchip,model = "I2S"; +- rockchip,routing = "Analog", "LOUT2", +- "Analog", "ROUT2"; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&hym8563>; +- clock-names = "ext_clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_enable>; +- reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; +- }; +- +- vcc_usb_host: vcc-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&host_vbus_drv>; +- regulator-name = "vcc_host"; +- }; +- +- vcc_sd: sdmmc-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_pwr>; +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc_io>; +- }; +-}; +- +-&sdio0 { +- bus-width = <4>; +- cap-sd-highspeed; +- cap-sdio-irq; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk &sdio0_int>; +- vmmc-supply = <&vcc_io>; +- vqmmc-supply = <&vcc_18>; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- card-detect-delay = <200>; +- disable-wp; /* wp not hooked up */ +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +- vmmc-supply = <&vcc_sd>; +- vqmmc-supply = <&vccio_sd>; +- status = "okay"; +-}; +- +-&gmac { +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c5>; +- status = "okay"; +-}; +- +-&i2c0 { +- hym8563: hym8563@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "xin32k"; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int>; +- +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- +- es8388: es8388@10 { +- compatible = "everest,es8388", "everest,es8328"; +- reg = <0x10>; +- AVDD-supply = <&vccio_codec>; +- DVDD-supply = <&vccio_codec>; +- HPVDD-supply = <&vccio_codec>; +- PVDD-supply = <&vccio_codec>; +- clocks = <&cru SCLK_I2S0_OUT>; +- }; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2s { +- status = "okay"; +-}; +- +-&pinctrl { +- ir { +- ir_int: ir-int { +- rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- keys { +- pwr_key: pwr-key { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- pmic { +- pmic_int: pmic-int { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- headphone { +- hp_det: hp-det { +- rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- phone_ctl: phone-ctl { +- rockchip,pins = <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- usb { +- host_vbus_drv: host-vbus-drv { +- rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sata { +- sata_pwr_en: sata-pwr-en { +- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdmmc { +- sdmmc_pwr: sdmmc-pwr { +- rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdio { +- wifi_enable: wifi-enable { +- rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&saradc { +- status = "okay"; +-}; +- +-&spdif { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&usbphy1 { +- vbus-supply = <&vcc_usb_host>; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host1 { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-tinker-s.dts b/scripts/dtc/include-prefixes/arm/rk3288-tinker-s.dts +deleted file mode 100644 +index 970e13859198..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-tinker-s.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. +- */ +- +-/dts-v1/; +- +-#include "rk3288-tinker.dtsi" +- +-/ { +- model = "Rockchip RK3288 Asus Tinker Board S"; +- compatible = "asus,rk3288-tinker-s", "rockchip,rk3288"; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; +- max-frequency = <150000000>; +- mmc-hs200-1_8v; +- mmc-ddr-1_8v; +- status = "okay"; +-}; +- +-&hdmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_cec_c0>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-tinker.dts b/scripts/dtc/include-prefixes/arm/rk3288-tinker.dts +deleted file mode 100644 +index 1e43527aa196..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-tinker.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. +- */ +- +-/dts-v1/; +- +-#include "rk3288-tinker.dtsi" +- +-/ { +- model = "Rockchip RK3288 Asus Tinker Board"; +- compatible = "asus,rk3288-tinker", "rockchip,rk3288"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-tinker.dtsi b/scripts/dtc/include-prefixes/arm/rk3288-tinker.dtsi +deleted file mode 100644 +index 9c1e38c54eae..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-tinker.dtsi ++++ /dev/null +@@ -1,548 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. +- */ +- +-#include "rk3288.dtsi" +-#include +-#include +- +-/ { +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- memory { +- reg = <0x0 0x0 0x0 0x80000000>; +- device_type = "memory"; +- }; +- +- ext_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- clock-output-names = "ext_gmac"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- autorepeat; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pwrbtn>; +- +- button@0 { +- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "GPIO Key Power"; +- linux,input-type = <1>; +- wakeup-source; +- debounce-interval = <100>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- act_led: led-0 { +- gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- }; +- +- heartbeat_led: led-1 { +- gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- pwr_led: led-2 { +- gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; +- }; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&rk808 RK808_CLKOUT1>; +- clock-names = "ext_clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_enable>; +- reset-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>, +- <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,name = "rockchip,tinker-codec"; +- simple-audio-card,mclk-fs = <512>; +- +- simple-audio-card,codec { +- sound-dai = <&hdmi>; +- }; +- +- simple-audio-card,cpu { +- sound-dai = <&i2s>; +- }; +- }; +- +- vcc_sys: vsys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc_sd: sdmmc-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_pwr>; +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- vin-supply = <&vcc_io>; +- }; +-}; +- +-&cpu0 { +- cpu0-supply = <&vdd_cpu>; +-}; +- +-&cpu_opp_table { +- opp-1704000000 { +- opp-hz = /bits/ 64 <1704000000>; +- opp-microvolt = <1350000>; +- }; +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <1400000>; +- }; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_MAC>; +- assigned-clock-parents = <&ext_gmac>; +- clock_in_out = "input"; +- phy-mode = "rgmii"; +- phy-supply = <&vcc33_lan>; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- snps,reset-gpio = <&gpio4 7 0>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 1000000>; +- tx_delay = <0x30>; +- rx_delay = <0x10>; +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c5>; +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- status = "okay"; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio0>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- dvs-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>, +- <&gpio0 12 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int &global_pwroff &dvs_1 &dvs_2>; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc6-supply = <&vcc_sys>; +- vcc7-supply = <&vcc_sys>; +- vcc8-supply = <&vcc_io>; +- vcc9-supply = <&vcc_io>; +- vcc10-supply = <&vcc_io>; +- vcc11-supply = <&vcc_sys>; +- vcc12-supply = <&vcc_io>; +- vddio-supply = <&vcc_io>; +- +- regulators { +- vdd_cpu: DCDC_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd_arm"; +- regulator-ramp-delay = <6000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: DCDC_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-name = "vdd_gpu"; +- regulator-ramp-delay = <6000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc_ddr"; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_io: DCDC_REG4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc_io"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc18_ldo1: LDO_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc18_ldo1"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc33_mipi: LDO_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc33_mipi"; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_10: LDO_REG3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-name = "vdd_10"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc18_codec: LDO_REG4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc18_codec"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vccio_sd: LDO_REG5 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vccio_sd"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vdd10_lcd: LDO_REG6 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-name = "vdd10_lcd"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc_18: LDO_REG7 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc_18"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc18_lcd: LDO_REG8 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc18_lcd"; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc33_sd: SWITCH_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc33_sd"; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc33_lan: SWITCH_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc33_lan"; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&i2s { +- #sound-dai-cells = <0>; +- status = "okay"; +-}; +- +-&io_domains { +- status = "okay"; +- +- sdcard-supply = <&vccio_sd>; +- wifi-supply = <&vcc_18>; +-}; +- +-&pinctrl { +- pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { +- drive-strength = <8>; +- }; +- +- pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { +- bias-pull-up; +- drive-strength = <8>; +- }; +- +- backlight { +- bl_en: bl-en { +- rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- buttons { +- pwrbtn: pwrbtn { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- eth_phy { +- eth_phy_pwr: eth-phy-pwr { +- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- pmic_int: pmic-int { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- dvs_1: dvs-1 { +- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- dvs_2: dvs-2 { +- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- sdmmc { +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, +- <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, +- <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, +- <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; +- }; +- +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; +- }; +- +- sdmmc_pwr: sdmmc-pwr { +- rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb { +- host_vbus_drv: host-vbus-drv { +- rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- pwr_3g: pwr-3g { +- rockchip,pins = <7 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdio { +- wifi_enable: wifi-enable { +- rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, +- <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vcc18_ldo1>; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- broken-cd; +- disable-wp; /* wp not hooked up */ +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +- status = "okay"; +- vmmc-supply = <&vcc33_sd>; +- vqmmc-supply = <&vccio_sd>; +-}; +- +-&sdio0 { +- bus-width = <4>; +- cap-sd-highspeed; +- cap-sdio-irq; +- keep-power-in-suspend; +- max-frequency = <50000000>; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- vmmc-supply = <&vcc_io>; +- vqmmc-supply = <&vcc_18>; +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&uart4 { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host1 { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-veyron-analog-audio.dtsi b/scripts/dtc/include-prefixes/arm/rk3288-veyron-analog-audio.dtsi +deleted file mode 100644 +index 51208d161d65..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-veyron-analog-audio.dtsi ++++ /dev/null +@@ -1,99 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Google Veyron (and derivatives) fragment for the max98090 audio +- * codec and analog headphone jack. +- * +- * Copyright 2016 Google, Inc +- */ +- +-/ { +- sound { +- compatible = "rockchip,rockchip-audio-max98090"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mic_det>, <&hp_det>; +- rockchip,model = "VEYRON-I2S"; +- rockchip,i2s-controller = <&i2s>; +- rockchip,audio-codec = <&max98090>; +- rockchip,hp-det-gpios = <&gpio6 RK_PA5 GPIO_ACTIVE_HIGH>; +- rockchip,mic-det-gpios = <&gpio6 RK_PB3 GPIO_ACTIVE_LOW>; +- rockchip,headset-codec = <&headsetcodec>; +- rockchip,hdmi-codec = <&hdmi>; +- }; +-}; +- +-&i2c2 { +- max98090: max98090@10 { +- compatible = "maxim,max98090"; +- reg = <0x10>; +- interrupt-parent = <&gpio6>; +- interrupts = ; +- clock-names = "mclk"; +- clocks = <&cru SCLK_I2S0_OUT>; +- pinctrl-names = "default"; +- pinctrl-0 = <&int_codec>; +- }; +-}; +- +-&i2c4 { +- headsetcodec: ts3a227e@3b { +- compatible = "ti,ts3a227e"; +- reg = <0x3b>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&ts3a227e_int_l>; +- ti,micbias = <7>; /* MICBIAS = 2.8V */ +- }; +-}; +- +-&i2s { +- status = "okay"; +-}; +- +-&io_domains { +- audio-supply = <&vcc18_codec>; +-}; +- +-&rk808 { +- vcc10-supply = <&vcc33_sys>; +- +- regulators { +- vcc18_codec: LDO_REG6 { +- regulator-name = "vcc18_codec"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +-}; +- +-&pinctrl { +- codec { +- hp_det: hp-det { +- rockchip,pins = <6 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- /* +- * HACK: We're going to _pull down_ this _active low_ interrupt +- * so that it never fires. We don't need this interrupt because +- * we've got a ts3a227e chip but the driver requires it. +- */ +- int_codec: int-codec { +- rockchip,pins = <6 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- mic_det: mic-det { +- rockchip,pins = <6 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- headset { +- ts3a227e_int_l: ts3a227e-int-l { +- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-veyron-brain.dts b/scripts/dtc/include-prefixes/arm/rk3288-veyron-brain.dts +deleted file mode 100644 +index aa33d09184ad..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-veyron-brain.dts ++++ /dev/null +@@ -1,111 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Veyron Brain Rev 0 board device tree source +- * +- * Copyright 2014 Google, Inc +- */ +- +-/dts-v1/; +-#include "rk3288-veyron.dtsi" +-#include "rk3288-veyron-broadcom-bluetooth.dtsi" +- +-/ { +- model = "Google Brain"; +- compatible = "google,veyron-brain-rev0", "google,veyron-brain", +- "google,veyron", "rockchip,rk3288"; +- +- vcc33_sys: vcc33-sys { +- vin-supply = <&vcc_5v>; +- }; +- +- vcc33_io: vcc33_io { +- compatible = "regulator-fixed"; +- regulator-name = "vcc33_io"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc33_sys>; +- /* This is gated by vcc_18 too */ +- }; +- +- /* This turns on vbus for host2 and otg (dwc2) */ +- vcc5_host2: vcc5-host2-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb2_pwr_en>; +- regulator-name = "vcc5_host2"; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = < +- /* Common for sleep and wake, but no owners */ +- &ddr0_retention +- &ddrio_pwroff +- &global_pwroff +- >; +- +- hdmi { +- vcc50_hdmi_en: vcc50-hdmi-en { +- rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- dvs_1: dvs-1 { +- rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- dvs_2: dvs-2 { +- rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- usb-host { +- usb2_pwr_en: usb2-pwr-en { +- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&rk808 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; +- dvs-gpios = <&gpio7 RK_PB3 GPIO_ACTIVE_HIGH>, +- <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; +- +- /delete-property/ vcc6-supply; +- +- regulators { +- /* vcc33_io is sourced directly from vcc33_sys */ +- /delete-node/ LDO_REG1; +- +- /* This is not a pwren anymore, but the real power supply */ +- vdd10_lcd: LDO_REG7 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-name = "vdd10_lcd"; +- regulator-suspend-mem-disabled; +- }; +- +- vcc18_hdmi: SWITCH_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc18_hdmi"; +- regulator-suspend-mem-disabled; +- }; +- }; +-}; +- +-&vcc50_hdmi { +- enable-active-high; +- gpio = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc50_hdmi_en>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-veyron-broadcom-bluetooth.dtsi b/scripts/dtc/include-prefixes/arm/rk3288-veyron-broadcom-bluetooth.dtsi +deleted file mode 100644 +index a10d25ac8f7b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-veyron-broadcom-bluetooth.dtsi ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Veyron (and derivatives) fragment for the Broadcom 43450 bluetooth +- * chip. +- * +- * Copyright 2019 Google, Inc +- */ +- +-&uart0 { +- bluetooth { +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_host_wake_l>, <&bt_enable_l>, +- <&bt_dev_wake>; +- +- compatible = "brcm,bcm43540-bt"; +- host-wakeup-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; +- device-wakeup-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; +- max-speed = <3000000>; +- brcm,bt-pcm-int-params = [01 02 00 01 01]; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-veyron-chromebook.dtsi b/scripts/dtc/include-prefixes/arm/rk3288-veyron-chromebook.dtsi +deleted file mode 100644 +index 05112c25176d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-veyron-chromebook.dtsi ++++ /dev/null +@@ -1,184 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Veyron (and derivatives) board device tree source +- * Chromebook specific parts +- * +- * Copyright 2015 Google, Inc +- */ +- +-#include +-#include +-#include "rk3288-veyron.dtsi" +-#include "rk3288-veyron-analog-audio.dtsi" +-#include "rk3288-veyron-edp.dtsi" +-#include "rk3288-veyron-sdmmc.dtsi" +- +-/ { +- aliases { +- /* Assign 20 so we don't get confused w/ builtin ones */ +- i2c20 = &i2c_tunnel; +- }; +- +- gpio-charger { +- compatible = "gpio-charger"; +- charger-type = "mains"; +- gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ac_present_ap>; +- }; +- +- lid_switch: lid-switch { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ap_lid_int_l>; +- +- lid { +- label = "Lid"; +- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; +- wakeup-source; +- linux,code = ; +- linux,input-type = ; +- debounce-interval = <1>; +- }; +- }; +- +- /* A non-regulated voltage from power supply or battery */ +- vccsys: vccsys { +- compatible = "regulator-fixed"; +- regulator-name = "vccsys"; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcc33_sys: vcc33-sys { +- vin-supply = <&vccsys>; +- }; +- +- vcc_5v: vcc-5v { +- vin-supply = <&vccsys>; +- }; +- +- /* This turns on vbus for host1 (dwc2) */ +- vcc5_host1: vcc5-host1-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&host1_pwr_en>; +- regulator-name = "vcc5_host1"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* This turns on vbus for otg for host mode (dwc2) */ +- vcc5v_otg: vcc5v-otg-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usbotg_pwren_h>; +- regulator-name = "vcc5_host2"; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&rk808 { +- vcc11-supply = <&vcc_5v>; +- +- regulators { +- vcc33_ccd: LDO_REG8 { +- regulator-name = "vcc33_ccd"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- +- cros_ec: ec@0 { +- compatible = "google,cros-ec-spi"; +- reg = <0>; +- google,cros-ec-spi-pre-delay = <30>; +- interrupt-parent = <&gpio7>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&ec_int>; +- spi-max-frequency = <3000000>; +- +- i2c_tunnel: i2c-tunnel { +- compatible = "google,cros-ec-i2c-tunnel"; +- google,remote-bus = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +-}; +- +-&i2c4 { +- trackpad@15 { +- compatible = "elan,ekth3000"; +- reg = <0x15>; +- interrupt-parent = <&gpio7>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&trackpad_int>; +- vcc-supply = <&vcc33_io>; +- wakeup-source; +- }; +-}; +- +-&pinctrl { +- buttons { +- ap_lid_int_l: ap-lid-int-l { +- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- charger { +- ac_present_ap: ac-present-ap { +- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- cros-ec { +- ec_int: ec-int { +- rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- suspend { +- suspend_l_wake: suspend-l-wake { +- rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- +- suspend_l_sleep: suspend-l-sleep { +- rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- }; +- +- trackpad { +- trackpad_int: trackpad-int { +- rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- usb-host { +- host1_pwr_en: host1-pwr-en { +- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- usbotg_pwren_h: usbotg-pwren-h { +- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-#include "cros-ec-keyboard.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-veyron-edp.dtsi b/scripts/dtc/include-prefixes/arm/rk3288-veyron-edp.dtsi +deleted file mode 100644 +index 32c0f10765dd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-veyron-edp.dtsi ++++ /dev/null +@@ -1,141 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Veyron (and derivatives) fragment for the edp displays +- * +- * Copyright 2019 Google LLC +- */ +- +-/ { +- backlight_regulator: backlight-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bl_pwr_en>; +- regulator-name = "backlight_regulator"; +- vin-supply = <&vcc33_sys>; +- startup-delay-us = <15000>; +- }; +- +- panel_regulator: panel-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_enable_h>; +- regulator-name = "panel_regulator"; +- vin-supply = <&vcc33_sys>; +- }; +- +- vcc18_lcd: vcc18-lcd { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&avdd_1v8_disp_en>; +- regulator-name = "vcc18_lcd"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc18_wl>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- brightness-levels = <0 255>; +- num-interpolated-steps = <255>; +- default-brightness-level = <128>; +- enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bl_en>; +- pwms = <&pwm0 0 1000000 0>; +- post-pwm-on-delay-ms = <10>; +- pwm-off-delay-ms = <10>; +- power-supply = <&backlight_regulator>; +- }; +- +- panel: panel { +- compatible = "innolux,n116bge"; +- status = "okay"; +- power-supply = <&panel_regulator>; +- backlight = <&backlight>; +- +- panel-timing { +- clock-frequency = <74250000>; +- hactive = <1366>; +- hfront-porch = <136>; +- hback-porch = <60>; +- hsync-len = <30>; +- hsync-active = <0>; +- vactive = <768>; +- vfront-porch = <8>; +- vback-porch = <12>; +- vsync-len = <12>; +- vsync-active = <0>; +- }; +- +- ports { +- panel_in: port { +- panel_in_edp: endpoint { +- remote-endpoint = <&edp_out_panel>; +- }; +- }; +- }; +- }; +-}; +- +-&edp { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&edp_hpd>; +- +- ports { +- edp_out: port@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- edp_out_panel: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_in_edp>; +- }; +- }; +- }; +-}; +- +-&edp_phy { +- status = "okay"; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +- +-&pinctrl { +- backlight { +- bl_pwr_en: bl_pwr_en { +- rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bl_en: bl-en { +- rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- lcd { +- lcd_enable_h: lcd-en { +- rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- avdd_1v8_disp_en: avdd-1v8-disp-en { +- rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-veyron-fievel.dts b/scripts/dtc/include-prefixes/arm/rk3288-veyron-fievel.dts +deleted file mode 100644 +index 309b122b4d0d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-veyron-fievel.dts ++++ /dev/null +@@ -1,528 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Veyron Fievel Rev 0+ board device tree source +- * +- * Copyright 2016 Google, Inc +- */ +- +-/dts-v1/; +-#include "rk3288-veyron.dtsi" +-#include "rk3288-veyron-analog-audio.dtsi" +- +-/ { +- model = "Google Fievel"; +- compatible = "google,veyron-fievel-rev8", "google,veyron-fievel-rev7", +- "google,veyron-fievel-rev6", "google,veyron-fievel-rev5", +- "google,veyron-fievel-rev4", "google,veyron-fievel-rev3", +- "google,veyron-fievel-rev2", "google,veyron-fievel-rev1", +- "google,veyron-fievel-rev0", "google,veyron-fievel", +- "google,veyron", "rockchip,rk3288"; +- +- vccsys: vccsys { +- compatible = "regulator-fixed"; +- regulator-name = "vccsys"; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* +- * vcc33_pmuio and vcc33_io is sourced directly from vcc33_sys, +- * enabled by vcc_18 +- */ +- vcc33_io: vcc33-io { +- compatible = "regulator-fixed"; +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc33_io"; +- }; +- +- vcc5_host1: vcc5-host1-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio5 RK_PC2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hub_usb1_pwr_en>; +- regulator-name = "vcc5_host1"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc5_host2: vcc5-host2-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio5 RK_PB6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hub_usb2_pwr_en>; +- regulator-name = "vcc5_host2"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc5v_otg: vcc5v-otg-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_otg_pwr_en>; +- regulator-name = "vcc5_otg"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ext_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- clock-output-names = "ext_gmac"; +- }; +-}; +- +-&gmac { +- status = "okay"; +- +- assigned-clocks = <&cru SCLK_MAC>; +- assigned-clock-parents = <&ext_gmac>; +- clock_in_out = "input"; +- phy-handle = <ðphy>; +- phy-mode = "rgmii"; +- phy-supply = <&vcc33_lan>; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; +- rx_delay = <0x10>; +- tx_delay = <0x30>; +- +- /* +- * Reset for the RTL8211 PHY which requires a 10-ms reset pulse (low) +- * with a 30ms settling time. +- */ +- snps,reset-gpio = <&gpio4 RK_PB0 0>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 30000>; +- wakeup-source; +- +- mdio0 { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy@1 { +- reg = <1>; +- }; +- }; +-}; +- +-&rk808 { +- dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, +- <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; +- +- vcc6-supply = <&vcc33_sys>; +- vcc10-supply = <&vcc33_sys>; +- vcc11-supply = <&vcc_5v>; +- vcc12-supply = <&vcc33_sys>; +- +- regulators { +- /delete-node/ LDO_REG1; +- +- /* +- * According to the schematic, vcc18_lcdt is for +- * HDMI_AVDD_1V8 +- */ +- vcc18_lcdt: LDO_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vdd18_lcdt"; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- /* +- * This is not a pwren anymore, but the real power supply, +- * vdd10_lcd for HDMI_AVDD_1V0 +- */ +- vdd10_lcd: LDO_REG7 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-name = "vdd10_lcd"; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- /* for usb camera */ +- vcc33_ccd: LDO_REG8 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc33_ccd"; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc33_lan: SWITCH_REG2 { +- regulator-name = "vcc33_lan"; +- }; +- }; +-}; +- +-&sdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- btmrvl: btmrvl@2 { +- compatible = "marvell,sd8897-bt"; +- reg = <2>; +- interrupt-parent = <&gpio4>; +- interrupts = ; +- marvell,wakeup-pin = /bits/ 16 <13>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_host_wake_l>; +- }; +-}; +- +-&vcc50_hdmi { +- enable-active-high; +- gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc50_hdmi_en>; +-}; +- +-&vcc_5v { +- enable-active-high; +- gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&drv_5v>; +-}; +- +-&gpio0 { +- gpio-line-names = "PMIC_SLEEP_AP", +- "DDRIO_PWROFF", +- "DDRIO_RETEN", +- "TS3A227E_INT_L", +- "PMIC_INT_L", +- "PWR_KEY_L", +- "HUB_USB1_nFALUT", +- "PHY_PMEB", +- +- "PHY_INT", +- /* +- * RECOVERY_SW_L is Chrome OS ABI. Schematics call +- * it REC_MODE_L. +- */ +- "RECOVERY_SW_L", +- "OTP_OUT", +- "", +- "USB_OTG_POWER_EN", +- "AP_WARM_RESET_H", +- "USB_OTG_nFALUT", +- "I2C0_SDA_PMIC", +- +- "I2C0_SCL_PMIC", +- "DEVMODE_L", +- "USB_INT"; +-}; +- +-&gpio2 { +- gpio-line-names = "CONFIG0", +- "CONFIG1", +- "CONFIG2", +- "", +- "", +- "", +- "", +- "CONFIG3", +- +- "", +- "EMMC_RST_L", +- "", +- "", +- "BL_PWR_EN", +- "", +- "TOUCH_INT", +- "TOUCH_RST", +- +- "I2C3_SCL_TP", +- "I2C3_SDA_TP"; +-}; +- +-&gpio3 { +- gpio-line-names = "FLASH0_D0", +- "FLASH0_D1", +- "FLASH0_D2", +- "FLASH0_D3", +- "FLASH0_D4", +- "FLASH0_D5", +- "FLASH0_D6", +- "FLASH0_D7", +- +- "VCC5V_GOOD_H", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "FLASH0_CS2/EMMC_CMD", +- "", +- "FLASH0_DQS/EMMC_CLKO", +- "", +- "", +- "", +- "", +- "", +- +- "PHY_TXD2", +- "PHY_TXD3", +- "MAC_RXD2", +- "MAC_RXD3", +- "PHY_TXD0", +- "PHY_TXD1", +- "MAC_RXD0", +- "MAC_RXD1"; +-}; +- +-&gpio4 { +- gpio-line-names = "MAC_MDC", +- "MAC_RXDV", +- "MAC_RXER", +- "MAC_CLK", +- "PHY_TXEN", +- "MAC_MDIO", +- "MAC_RXCLK", +- "", +- +- "PHY_RST", +- "PHY_TXCLK", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "UART0_RXD", +- "UART0_TXD", +- "UART0_CTS_L", +- "UART0_RTS_L", +- "SDIO0_D0", +- "SDIO0_D1", +- "SDIO0_D2", +- "SDIO0_D3", +- +- "SDIO0_CMD", +- "SDIO0_CLK", +- "BT_DEV_WAKE", +- "", +- "WIFI_ENABLE_H", +- "BT_ENABLE_L", +- "WIFI_HOST_WAKE", +- "BT_HOST_WAKE"; +-}; +- +-&gpio5 { +- gpio-line-names = "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "", +- "", +- "", +- "", +- "USB_OTG_CTL1", +- "HUB_USB2_CTL1", +- "HUB_USB2_PWR_EN", +- "HUB_USB_ILIM_SEL", +- +- "USB_OTG_STATUS_L", +- "HUB_USB1_CTL1", +- "HUB_USB1_PWR_EN", +- "VCC50_HDMI_EN"; +-}; +- +-&gpio6 { +- gpio-line-names = "I2S0_SCLK", +- "I2S0_LRCK_RX", +- "I2S0_LRCK_TX", +- "I2S0_SDI", +- "I2S0_SDO0", +- "HP_DET_H", +- "", +- "INT_CODEC", +- +- "I2S0_CLK", +- "I2C2_SDA", +- "I2C2_SCL", +- "MICDET", +- "", +- "", +- "", +- "", +- +- "HUB_USB2_nFALUT", +- "USB_OTG_ILIM_SEL"; +-}; +- +-&gpio7 { +- gpio-line-names = "LCD_BL_PWM", +- "PWM_LOG", +- "BL_EN", +- "PWR_LED1", +- "TPM_INT_H", +- "SPK_ON", +- /* +- * AP_FLASH_WP_L is Chrome OS ABI. Schematics call +- * it FW_WP_AP. +- */ +- "AP_FLASH_WP_L", +- "", +- +- "CPU_NMI", +- "DVSOK", +- "", +- "EDP_HPD", +- "DVS1", +- "", +- "LCD_EN", +- "DVS2", +- +- "HDMI_CEC", +- "I2C4_SDA", +- "I2C4_SCL", +- "I2C5_SDA_HDMI", +- "I2C5_SCL_HDMI", +- "5V_DRV", +- "UART2_RXD", +- "UART2_TXD"; +-}; +- +-&gpio8 { +- gpio-line-names = "RAM_ID0", +- "RAM_ID1", +- "RAM_ID2", +- "RAM_ID3", +- "I2C1_SDA_TPM", +- "I2C1_SCL_TPM", +- "SPI2_CLK", +- "SPI2_CS0", +- +- "SPI2_RXD", +- "SPI2_TXD"; +-}; +- +-&pinctrl { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = < +- /* Common for sleep and wake, but no owners */ +- &ddr0_retention +- &ddrio_pwroff +- &global_pwroff +- +- /* For usb bc1.2 */ +- &usb_otg_ilim_sel +- &usb_usb_ilim_sel +- +- /* Wake only */ +- &bt_dev_wake_awake +- &pwr_led1_on +- >; +- +- pinctrl-1 = < +- /* Common for sleep and wake, but no owners */ +- &ddr0_retention +- &ddrio_pwroff +- &global_pwroff +- +- /* For usb bc1.2 */ +- &usb_otg_ilim_sel +- &usb_usb_ilim_sel +- +- /* Sleep only */ +- &bt_dev_wake_sleep +- &pwr_led1_blink +- >; +- +- buck-5v { +- drv_5v: drv-5v { +- rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- gmac { +- phy_rst: phy-rst { +- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- +- phy_pmeb: phy-pmeb { +- rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- phy_int: phy-int { +- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- hdmi { +- vcc50_hdmi_en: vcc50-hdmi-en { +- rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- leds { +- pwr_led1_on: pwr-led1-on { +- rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- +- pwr_led1_blink: pwr-led1-blink { +- rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- }; +- +- pmic { +- dvs_1: dvs-1 { +- rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- dvs_2: dvs-2 { +- rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- usb-bc12 { +- usb_otg_ilim_sel: usb-otg-ilim-sel { +- rockchip,pins = <6 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- +- usb_usb_ilim_sel: usb-usb-ilim-sel { +- rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- }; +- +- usb-host { +- hub_usb1_pwr_en: hub_usb1_pwr_en { +- rockchip,pins = <5 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- hub_usb2_pwr_en: hub_usb2_pwr_en { +- rockchip,pins = <5 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- usb_otg_pwr_en: usb_otg_pwr_en { +- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-veyron-jaq.dts b/scripts/dtc/include-prefixes/arm/rk3288-veyron-jaq.dts +deleted file mode 100644 +index 4a148cf1defc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-veyron-jaq.dts ++++ /dev/null +@@ -1,334 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Veyron Jaq Rev 1+ board device tree source +- * +- * Copyright 2015 Google, Inc +- */ +- +-/dts-v1/; +- +-#include "rk3288-veyron-chromebook.dtsi" +-#include "cros-ec-sbs.dtsi" +- +-/ { +- model = "Google Jaq"; +- compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4", +- "google,veyron-jaq-rev3", "google,veyron-jaq-rev2", +- "google,veyron-jaq-rev1", "google,veyron-jaq", +- "google,veyron", "rockchip,rk3288"; +-}; +- +-&backlight { +- /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */ +- brightness-levels = <8 255>; +- num-interpolated-steps = <247>; +-}; +- +-&rk808 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; +- dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, +- <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; +- +- regulators { +- mic_vcc: LDO_REG2 { +- regulator-name = "mic_vcc"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +-}; +- +-&sdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- btmrvl: btmrvl@2 { +- compatible = "marvell,sd8897-bt"; +- reg = <2>; +- interrupt-parent = <&gpio4>; +- interrupts = ; +- marvell,wakeup-pin = /bits/ 16 <13>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_host_wake_l>; +- }; +-}; +- +-&sdmmc { +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin +- &sdmmc_bus4>; +-}; +- +-&vcc_5v { +- enable-active-high; +- gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&drv_5v>; +-}; +- +-&vcc50_hdmi { +- enable-active-high; +- gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc50_hdmi_en>; +-}; +- +-&gpio0 { +- gpio-line-names = "PMIC_SLEEP_AP", +- "DDRIO_PWROFF", +- "DDRIO_RETEN", +- "TS3A227E_INT_L", +- "PMIC_INT_L", +- "PWR_KEY_L", +- "AP_LID_INT_L", +- "EC_IN_RW", +- +- "AC_PRESENT_AP", +- /* +- * RECOVERY_SW_L is Chrome OS ABI. Schematics call +- * it REC_MODE_L. +- */ +- "RECOVERY_SW_L", +- "OTP_OUT", +- "HOST1_PWR_EN", +- "USBOTG_PWREN_H", +- "AP_WARM_RESET_H", +- "nFALUT2", +- "I2C0_SDA_PMIC", +- +- "I2C0_SCL_PMIC", +- "SUSPEND_L", +- "USB_INT"; +-}; +- +-&gpio2 { +- gpio-line-names = "CONFIG0", +- "CONFIG1", +- "CONFIG2", +- "", +- "", +- "", +- "", +- "CONFIG3", +- +- "", +- "EMMC_RST_L", +- "", +- "", +- "BL_PWR_EN", +- "AVDD_1V8_DISP_EN"; +-}; +- +-&gpio3 { +- gpio-line-names = "FLASH0_D0", +- "FLASH0_D1", +- "FLASH0_D2", +- "FLASH0_D3", +- "FLASH0_D4", +- "FLASH0_D5", +- "FLASH0_D6", +- "FLASH0_D7", +- +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "FLASH0_CS2/EMMC_CMD", +- "", +- "FLASH0_DQS/EMMC_CLKO"; +-}; +- +-&gpio4 { +- gpio-line-names = "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "UART0_RXD", +- "UART0_TXD", +- "UART0_CTS", +- "UART0_RTS", +- "SDIO0_D0", +- "SDIO0_D1", +- "SDIO0_D2", +- "SDIO0_D3", +- +- "SDIO0_CMD", +- "SDIO0_CLK", +- "BT_DEV_WAKE", /* Maybe missing from mighty? */ +- "", +- "WIFI_ENABLE_H", +- "BT_ENABLE_L", +- "WIFI_HOST_WAKE", +- "BT_HOST_WAKE"; +-}; +- +-&gpio5 { +- gpio-line-names = "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "", +- "", +- "", +- "", +- "SPI0_CLK", +- "SPI0_CS0", +- "SPI0_TXD", +- "SPI0_RXD", +- +- "", +- "", +- "", +- "VCC50_HDMI_EN"; +-}; +- +-&gpio6 { +- gpio-line-names = "I2S0_SCLK", +- "I2S0_LRCK_RX", +- "I2S0_LRCK_TX", +- "I2S0_SDI", +- "I2S0_SDO0", +- "HP_DET_H", +- "ALS_INT", +- "INT_CODEC", +- +- "I2S0_CLK", +- "I2C2_SDA", +- "I2C2_SCL", +- "MICDET", +- "", +- "", +- "", +- "", +- +- "SDMMC_D0", +- "SDMMC_D1", +- "SDMMC_D2", +- "SDMMC_D3", +- "SDMMC_CLK", +- "SDMMC_CMD"; +-}; +- +-&gpio7 { +- gpio-line-names = "LCDC_BL", +- "PWM_LOG", +- "BL_EN", +- "TRACKPAD_INT", +- "TPM_INT_H", +- "SDMMC_DET_L", +- /* +- * AP_FLASH_WP_L is Chrome OS ABI. Schematics call +- * it FW_WP_AP. +- */ +- "AP_FLASH_WP_L", +- "EC_INT", +- +- "CPU_NMI", +- "DVSOK", +- "SDMMC_WP", /* mighty only */ +- "EDP_HPD", +- "DVS1", +- "nFALUT1", /* nFAULT1 on jaq */ +- "LCD_EN", +- "DVS2", +- +- "VCC5V_GOOD_H", +- "I2C4_SDA_TP", +- "I2C4_SCL_TP", +- "I2C5_SDA_HDMI", +- "I2C5_SCL_HDMI", +- "5V_DRV", +- "UART2_RXD", +- "UART2_TXD"; +-}; +- +-&gpio8 { +- gpio-line-names = "RAM_ID0", +- "RAM_ID1", +- "RAM_ID2", +- "RAM_ID3", +- "I2C1_SDA_TPM", +- "I2C1_SCL_TPM", +- "SPI2_CLK", +- "SPI2_CS0", +- +- "SPI2_RXD", +- "SPI2_TXD"; +-}; +- +-&pinctrl { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = < +- /* Common for sleep and wake, but no owners */ +- &ddr0_retention +- &ddrio_pwroff +- &global_pwroff +- +- /* Wake only */ +- &suspend_l_wake +- &bt_dev_wake_awake +- >; +- pinctrl-1 = < +- /* Common for sleep and wake, but no owners */ +- &ddr0_retention +- &ddrio_pwroff +- &global_pwroff +- +- /* Sleep only */ +- &suspend_l_sleep +- &bt_dev_wake_sleep +- >; +- +- buck-5v { +- drv_5v: drv-5v { +- rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- hdmi { +- vcc50_hdmi_en: vcc50-hdmi-en { +- rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- dvs_1: dvs-1 { +- rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- dvs_2: dvs-2 { +- rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-veyron-jerry.dts b/scripts/dtc/include-prefixes/arm/rk3288-veyron-jerry.dts +deleted file mode 100644 +index 2c916c50dda5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-veyron-jerry.dts ++++ /dev/null +@@ -1,494 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Veyron Jerry Rev 3+ board device tree source +- * +- * Copyright 2015 Google, Inc +- */ +- +-/dts-v1/; +-#include "rk3288-veyron-chromebook.dtsi" +-#include "cros-ec-sbs.dtsi" +- +-/ { +- model = "Google Jerry"; +- compatible = "google,veyron-jerry-rev15", "google,veyron-jerry-rev14", +- "google,veyron-jerry-rev13", "google,veyron-jerry-rev12", +- "google,veyron-jerry-rev11", "google,veyron-jerry-rev10", +- "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", +- "google,veyron-jerry-rev5", "google,veyron-jerry-rev4", +- "google,veyron-jerry-rev3", "google,veyron-jerry", +- "google,veyron", "rockchip,rk3288"; +-}; +- +-&rk808 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; +- dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, +- <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; +- +- regulators { +- mic_vcc: LDO_REG2 { +- regulator-name = "mic_vcc"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +-}; +- +-&sdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mwifiex: wifi@1 { +- compatible = "marvell,sd8897"; +- reg = <1>; +- +- marvell,caldata-txpwrlimit-2g = /bits/ 8 < +-0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01 +-0x24 0x00 0x67 0x09 0x14 0x01 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c +-0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c +-0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x02 0x00 0x0f +-0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 +-0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 +-0x24 0x00 0x67 0x09 0x14 0x03 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c +-0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c +-0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x04 0x00 0x0f +-0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 +-0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 +-0x24 0x00 0x67 0x09 0x14 0x05 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c +-0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c +-0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x06 0x00 0x0f +-0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 +-0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 +-0x24 0x00 0x67 0x09 0x14 0x07 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c +-0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c +-0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x08 0x00 0x0f +-0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 +-0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 +-0x24 0x00 0x67 0x09 0x14 0x09 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c +-0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c +-0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0a 0x00 0x0f +-0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 +-0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 +-0x24 0x00 0x67 0x09 0x14 0x0b 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c +-0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c +-0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0c 0x00 0x0f +-0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 +-0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 +-0x24 0x00 0x67 0x09 0x14 0x0d 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c +-0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c +-0x0d 0x09 0x0e 0x09 0x0f 0x09>; +- +- marvell,caldata-txpwrlimit-5g-sub0 = /bits/ 8 < +-0x01 0x00 0x06 0x00 0xf0 0x01 0x89 0x01 +-0x3a 0x00 0x88 0x13 0x14 0x24 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a +-0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 +-0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 +-0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 +-0x88 0x13 0x14 0x28 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a +-0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 +-0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 +-0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 +-0x14 0x2c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 +-0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 +-0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 +-0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x30 +-0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 +-0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 +-0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 +-0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x34 0x01 0x0c +-0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 +-0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 +-0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 +-0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x38 0x01 0x0c 0x02 0x0c +-0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a +-0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 +-0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 +-0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x3c 0x01 0x0c 0x02 0x0c 0x03 0x0c +-0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a +-0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 +-0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 +-0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x40 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a +-0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a +-0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 +-0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>; +- +- marvell,caldata-txpwrlimit-5g-sub1 = /bits/ 8 < +-0x01 0x00 0x06 0x00 0xaa 0x02 0x89 0x01 +-0x3a 0x00 0x88 0x13 0x14 0x64 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a +-0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 +-0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 +-0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 +-0x88 0x13 0x14 0x68 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a +-0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 +-0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 +-0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 +-0x14 0x6c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 +-0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 +-0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 +-0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x70 +-0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 +-0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 +-0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 +-0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x74 0x01 0x0c +-0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 +-0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 +-0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 +-0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x78 0x01 0x0c 0x02 0x0c +-0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a +-0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 +-0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 +-0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x7c 0x01 0x0c 0x02 0x0c 0x03 0x0c +-0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a +-0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 +-0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 +-0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x80 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a +-0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a +-0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 +-0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 +-0x3a 0x00 0x88 0x13 0x14 0x84 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a +-0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 +-0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 +-0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 +-0x88 0x13 0x14 0x88 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a +-0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 +-0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 +-0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 +-0x14 0x8c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 +-0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 +-0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 +-0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>; +- +- marvell,caldata-txpwrlimit-5g-sub2 = /bits/ 8 < +-0x01 0x00 0x06 0x00 0x36 0x01 0x89 0x01 +-0x3a 0x00 0x88 0x13 0x14 0x95 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a +-0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 +-0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 +-0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 +-0x88 0x13 0x14 0x99 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a +-0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 +-0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 +-0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 +-0x14 0x9d 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 +-0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 +-0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 +-0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa1 +-0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08 +-0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04 +-0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05 +-0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa5 0x01 0x0b +-0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08 +-0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04 +-0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05 +-0x1a 0x05 0x1b 0x05>; +- }; +-}; +- +-&sdmmc { +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin +- &sdmmc_bus4>; +-}; +- +-&vcc_5v { +- enable-active-high; +- gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&drv_5v>; +-}; +- +-&vcc50_hdmi { +- enable-active-high; +- gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc50_hdmi_en>; +-}; +- +-&gpio0 { +- gpio-line-names = "PMIC_SLEEP_AP", +- "DDRIO_PWROFF", +- "DDRIO_RETEN", +- "TS3A227E_INT_L", +- "PMIC_INT_L", +- "PWR_KEY_L", +- "AP_LID_INT_L", +- "EC_IN_RW", +- +- "AC_PRESENT_AP", +- /* +- * RECOVERY_SW_L is Chrome OS ABI. Schematics call +- * it REC_MODE_L. +- */ +- "RECOVERY_SW_L", +- "OTP_OUT", +- "HOST1_PWR_EN", +- "USBOTG_PWREN_H", +- "AP_WARM_RESET_H", +- "nFAULT2", +- "I2C0_SDA_PMIC", +- +- "I2C0_SCL_PMIC", +- "SUSPEND_L", +- "USB_INT"; +-}; +- +-&gpio2 { +- gpio-line-names = "CONFIG0", +- "CONFIG1", +- "CONFIG2", +- "", +- "", +- "", +- "", +- "CONFIG3", +- +- "", +- "EMMC_RST_L", +- "", +- "", +- "BL_PWR_EN", +- "AVDD_1V8_DISP_EN"; +-}; +- +-&gpio3 { +- gpio-line-names = "FLASH0_D0", +- "FLASH0_D1", +- "FLASH0_D2", +- "FLASH0_D3", +- "FLASH0_D4", +- "FLASH0_D5", +- "FLASH0_D6", +- "FLASH0_D7", +- +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "FLASH0_CS2/EMMC_CMD", +- "", +- "FLASH0_DQS/EMMC_CLKO"; +-}; +- +-&gpio4 { +- gpio-line-names = "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "UART0_RXD", +- "UART0_TXD", +- "UART0_CTS", +- "UART0_RTS", +- "SDIO0_D0", +- "SDIO0_D1", +- "SDIO0_D2", +- "SDIO0_D3", +- +- "SDIO0_CMD", +- "SDIO0_CLK", +- "BT_DEV_WAKE", +- "", +- "WIFI_ENABLE_H", +- "BT_ENABLE_L", +- "WIFI_HOST_WAKE", +- "BT_HOST_WAKE"; +-}; +- +-&gpio5 { +- gpio-line-names = "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "", +- "", +- "", +- "", +- "SPI0_CLK", +- "SPI0_CS0", +- "SPI0_TXD", +- "SPI0_RXD", +- +- "", +- "", +- "", +- "VCC50_HDMI_EN"; +-}; +- +-&gpio6 { +- gpio-line-names = "I2S0_SCLK", +- "I2S0_LRCK_RX", +- "I2S0_LRCK_TX", +- "I2S0_SDI", +- "I2S0_SDO0", +- "HP_DET_H", +- "", +- "INT_CODEC", +- +- "I2S0_CLK", +- "I2C2_SDA", +- "I2C2_SCL", +- "MICDET", +- "", +- "", +- "", +- "", +- +- "SDMMC_D0", +- "SDMMC_D1", +- "SDMMC_D2", +- "SDMMC_D3", +- "SDMMC_CLK", +- "SDMMC_CMD"; +-}; +- +-&gpio7 { +- gpio-line-names = "LCDC_BL", +- "PWM_LOG", +- "BL_EN", +- "TRACKPAD_INT", +- "TPM_INT_H", +- "SDMMC_DET_L", +- /* +- * AP_FLASH_WP_L is Chrome OS ABI. Schematics call +- * it FW_WP_AP. +- */ +- "AP_FLASH_WP_L", +- "EC_INT", +- +- "CPU_NMI", +- "DVSOK", +- "", +- "EDP_HPD", +- "DVS1", +- "nFAULT1", +- "LCD_EN", +- "DVS2", +- +- "VCC5V_GOOD_H", +- "I2C4_SDA_TP", +- "I2C4_SCL_TP", +- "I2C5_SDA_HDMI", +- "I2C5_SCL_HDMI", +- "5V_DRV", +- "UART2_RXD", +- "UART2_TXD"; +-}; +- +-&gpio8 { +- gpio-line-names = "RAM_ID0", +- "RAM_ID1", +- "RAM_ID2", +- "RAM_ID3", +- "I2C1_SDA_TPM", +- "I2C1_SCL_TPM", +- "SPI2_CLK", +- "SPI2_CS0", +- +- "SPI2_RXD", +- "SPI2_TXD"; +-}; +- +-&pinctrl { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = < +- /* Common for sleep and wake, but no owners */ +- &ddr0_retention +- &ddrio_pwroff +- &global_pwroff +- +- /* Wake only */ +- &suspend_l_wake +- &bt_dev_wake_awake +- >; +- pinctrl-1 = < +- /* Common for sleep and wake, but no owners */ +- &ddr0_retention +- &ddrio_pwroff +- &global_pwroff +- +- /* Sleep only */ +- &suspend_l_sleep +- &bt_dev_wake_sleep +- >; +- +- buck-5v { +- drv_5v: drv-5v { +- rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- hdmi { +- vcc50_hdmi_en: vcc50-hdmi-en { +- rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- dvs_1: dvs-1 { +- rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- dvs_2: dvs-2 { +- rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +-}; +- +-&i2c4 { +- status = "okay"; +- +- /* +- * Trackpad pin control is shared between Elan and Synaptics devices +- * so we have to pull it up to the bus level. +- */ +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_xfer &trackpad_int>; +- +- trackpad@15 { +- /* +- * Remove the inherited pinctrl settings to avoid clashing +- * with bus-wide ones. +- */ +- /delete-property/pinctrl-names; +- /delete-property/pinctrl-0; +- }; +- +- trackpad@2c { +- compatible = "hid-over-i2c"; +- interrupt-parent = <&gpio7>; +- interrupts = ; +- reg = <0x2c>; +- hid-descr-addr = <0x0020>; +- vcc-supply = <&vcc33_io>; +- wakeup-source; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-veyron-mickey.dts b/scripts/dtc/include-prefixes/arm/rk3288-veyron-mickey.dts +deleted file mode 100644 +index ffd1121d19be..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-veyron-mickey.dts ++++ /dev/null +@@ -1,453 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Veyron Mickey Rev 0 board device tree source +- * +- * Copyright 2015 Google, Inc +- */ +- +-/dts-v1/; +-#include "rk3288-veyron.dtsi" +-#include "rk3288-veyron-broadcom-bluetooth.dtsi" +- +-/ { +- model = "Google Mickey"; +- compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7", +- "google,veyron-mickey-rev6", "google,veyron-mickey-rev5", +- "google,veyron-mickey-rev4", "google,veyron-mickey-rev3", +- "google,veyron-mickey-rev2", "google,veyron-mickey-rev1", +- "google,veyron-mickey-rev0", "google,veyron-mickey", +- "google,veyron", "rockchip,rk3288"; +- +- vcc_5v: vcc-5v { +- vin-supply = <&vcc33_sys>; +- }; +- +- vcc33_io: vcc33_io { +- compatible = "regulator-fixed"; +- regulator-name = "vcc33_io"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc33_sys>; +- }; +- +- sound { +- compatible = "rockchip,rockchip-audio-max98090"; +- rockchip,model = "VEYRON-HDMI"; +- rockchip,hdmi-codec = <&hdmi>; +- rockchip,i2s-controller = <&i2s>; +- }; +-}; +- +-&cpu_thermal { +- /delete-node/ trips; +- /delete-node/ cooling-maps; +- +- trips { +- cpu_alert_almost_warm: cpu_alert_almost_warm { +- temperature = <63000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu_alert_warm: cpu_alert_warm { +- temperature = <65000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu_alert_almost_hot: cpu_alert_almost_hot { +- temperature = <80000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu_alert_hot: cpu_alert_hot { +- temperature = <82000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu_alert_hotter: cpu_alert_hotter { +- temperature = <84000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu_alert_very_hot: cpu_alert_very_hot { +- temperature = <85000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu_crit: cpu_crit { +- temperature = <90000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- /* +- * After 1st level, throttle the CPU down to as low as 1.4 GHz +- * and don't let the GPU go faster than 400 MHz. +- */ +- cpu_warm_limit_cpu { +- trip = <&cpu_alert_warm>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT 4>, +- <&cpu1 THERMAL_NO_LIMIT 4>, +- <&cpu2 THERMAL_NO_LIMIT 4>, +- <&cpu3 THERMAL_NO_LIMIT 4>; +- }; +- cpu_warm_limit_gpu { +- trip = <&cpu_alert_warm>; +- cooling-device = <&gpu 1 1>; +- }; +- +- /* +- * Add some discrete steps to help throttling system deal +- * with the fact that there are two passive cooling devices: +- * the CPU and the GPU. +- * +- * - 1.2 GHz - 1.0 GHz (almost hot) +- * - 800 MHz (hot) +- * - 800 MHz - 696 MHz (hotter) +- * - 696 MHz - min (very hot) +- * +- * Note: +- * - 800 MHz appears to be a "sweet spot" for me. I can run +- * some pretty serious workload here and be happy. +- * - After 696 MHz we stop lowering voltage, so throttling +- * past there is less effective. +- */ +- cpu_almost_hot_limit_cpu { +- trip = <&cpu_alert_almost_hot>; +- cooling-device = <&cpu0 5 6>, <&cpu1 5 6>, <&cpu2 5 6>, +- <&cpu3 5 6>; +- }; +- cpu_hot_limit_cpu { +- trip = <&cpu_alert_hot>; +- cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, <&cpu2 7 7>, +- <&cpu3 7 7>; +- }; +- cpu_hotter_limit_cpu { +- trip = <&cpu_alert_hotter>; +- cooling-device = <&cpu0 7 8>, <&cpu1 7 8>, <&cpu2 7 8>, +- <&cpu3 7 8>; +- }; +- cpu_very_hot_limit_cpu { +- trip = <&cpu_alert_very_hot>; +- cooling-device = <&cpu0 8 THERMAL_NO_LIMIT>, +- <&cpu1 8 THERMAL_NO_LIMIT>, +- <&cpu2 8 THERMAL_NO_LIMIT>, +- <&cpu3 8 THERMAL_NO_LIMIT>; +- }; +- +- /* At very hot, don't let GPU go over 300 MHz */ +- cpu_very_hot_limit_gpu { +- trip = <&cpu_alert_very_hot>; +- cooling-device = <&gpu 2 2>; +- }; +- }; +-}; +- +-&gpu_thermal { +- /delete-node/ trips; +- /delete-node/ cooling-maps; +- +- trips { +- gpu_alert_warmish: gpu_alert_warmish { +- temperature = <60000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- gpu_alert_warm: gpu_alert_warm { +- temperature = <65000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- gpu_alert_hotter: gpu_alert_hotter { +- temperature = <84000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- gpu_alert_very_very_hot: gpu_alert_very_very_hot { +- temperature = <86000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- gpu_crit: gpu_crit { +- temperature = <90000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- /* After 1st level throttle the GPU down to as low as 400 MHz */ +- gpu_warmish_limit_gpu { +- trip = <&gpu_alert_warmish>; +- cooling-device = <&gpu THERMAL_NO_LIMIT 1>; +- }; +- +- /* +- * Slightly after we throttle the GPU, we'll also make sure that +- * the CPU can't go faster than 1.4 GHz. Note that we won't +- * throttle the CPU lower than 1.4 GHz due to GPU heat--we'll +- * let the CPU do the rest itself. +- */ +- gpu_warm_limit_cpu { +- trip = <&gpu_alert_warm>; +- cooling-device = <&cpu0 4 4>, +- <&cpu1 4 4>, +- <&cpu2 4 4>, +- <&cpu3 4 4>; +- }; +- +- /* When hot, GPU goes down to 300 MHz */ +- gpu_hotter_limit_gpu { +- trip = <&gpu_alert_hotter>; +- cooling-device = <&gpu 2 2>; +- }; +- +- /* When really hot, don't let GPU go _above_ 300 MHz */ +- gpu_very_very_hot_limit_gpu { +- trip = <&gpu_alert_very_very_hot>; +- cooling-device = <&gpu 2 THERMAL_NO_LIMIT>; +- }; +- }; +-}; +- +-&i2c2 { +- status = "disabled"; +-}; +- +-&i2c4 { +- status = "disabled"; +-}; +- +-&i2s { +- status = "okay"; +-}; +- +-&rk808 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; +- dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, +- <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; +- +- /delete-property/ vcc6-supply; +- /delete-property/ vcc12-supply; +- +- vcc11-supply = <&vcc33_sys>; +- +- regulators { +- /* vcc33_io is sourced directly from vcc33_sys */ +- /delete-node/ LDO_REG1; +- /delete-node/ LDO_REG7; +- +- /* This is not a pwren anymore, but the real power supply */ +- vdd10_lcd: LDO_REG7 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-name = "vdd10_lcd"; +- regulator-suspend-mem-disabled; +- }; +- +- vcc18_lcd: LDO_REG8 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc18_lcd"; +- regulator-suspend-mem-disabled; +- }; +- }; +-}; +- +-&gpio0 { +- gpio-line-names = "PMIC_SLEEP_AP", +- "", +- "", +- "", +- "PMIC_INT_L", +- "POWER_BUTTON_L", +- "", +- "", +- +- "", +- /* +- * RECOVERY_SW_L is Chrome OS ABI. Schematics call +- * it REC_MODE_L. +- */ +- "RECOVERY_SW_L", +- "OT_RESET", +- "", +- "", +- "AP_WARM_RESET_H", +- "", +- "I2C0_SDA_PMIC", +- +- "I2C0_SCL_PMIC", +- "", +- "nFALUT"; +-}; +- +-&gpio2 { +- gpio-line-names = "CONFIG0", +- "CONFIG1", +- "CONFIG2", +- "", +- "", +- "", +- "", +- "CONFIG3", +- +- "", +- "EMMC_RST_L"; +-}; +- +-&gpio3 { +- gpio-line-names = "FLASH0_D0", +- "FLASH0_D1", +- "FLASH0_D2", +- "FLASH0_D3", +- "FLASH0_D4", +- "FLASH0_D5", +- "FLASH0_D6", +- "FLASH0_D7", +- +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "FLASH0_CS2/EMMC_CMD", +- "", +- "FLASH0_DQS/EMMC_CLKO"; +-}; +- +-&gpio4 { +- gpio-line-names = "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "UART0_RXD", +- "UART0_TXD", +- "UART0_CTS_L", +- "UART0_RTS_L", +- "SDIO0_D0", +- "SDIO0_D1", +- "SDIO0_D2", +- "SDIO0_D3", +- +- "SDIO0_CMD", +- "SDIO0_CLK", +- "BT_DEV_WAKE", +- "", +- "WIFI_ENABLE_H", +- "BT_ENABLE_L", +- "WIFI_HOST_WAKE", +- "BT_HOST_WAKE"; +-}; +- +-&gpio7 { +- gpio-line-names = "", +- "PWM_LOG", +- "", +- "", +- "TPM_INT_H", +- "SDMMC_DET_L", +- /* +- * AP_FLASH_WP_L is Chrome OS ABI. Schematics call +- * it FW_WP_AP. +- */ +- "AP_FLASH_WP_L", +- "", +- +- "CPU_NMI", +- "DVSOK", +- "HDMI_WAKE", +- "POWER_HDMI_ON", +- "DVS1", +- "", +- "", +- "DVS2", +- +- "HDMI_CEC", +- "", +- "", +- "I2C5_SDA_HDMI", +- "I2C5_SCL_HDMI", +- "", +- "UART2_RXD", +- "UART2_TXD"; +-}; +- +-&gpio8 { +- gpio-line-names = "RAM_ID0", +- "RAM_ID1", +- "RAM_ID2", +- "RAM_ID3", +- "I2C1_SDA_TPM", +- "I2C1_SCL_TPM", +- "SPI2_CLK", +- "SPI2_CS0", +- +- "SPI2_RXD", +- "SPI2_TXD"; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = < +- /* Common for sleep and wake, but no owners */ +- &ddr0_retention +- &ddrio_pwroff +- &global_pwroff +- >; +- +- hdmi { +- power_hdmi_on: power-hdmi-on { +- rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- dvs_1: dvs-1 { +- rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- dvs_2: dvs-2 { +- rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +-}; +- +-&usb_host0_ehci { +- status = "disabled"; +-}; +- +-&usb_host1 { +- status = "disabled"; +-}; +- +-&vcc50_hdmi { +- enable-active-high; +- gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&power_hdmi_on>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-veyron-mighty.dts b/scripts/dtc/include-prefixes/arm/rk3288-veyron-mighty.dts +deleted file mode 100644 +index fa695a88f236..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-veyron-mighty.dts ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Veyron Mighty Rev 1+ board device tree source +- * +- * Copyright 2015 Google, Inc +- */ +- +-/dts-v1/; +- +-#include "rk3288-veyron-jaq.dts" +- +-/ { +- model = "Google Mighty"; +- compatible = "google,veyron-mighty-rev5", "google,veyron-mighty-rev4", +- "google,veyron-mighty-rev3", "google,veyron-mighty-rev2", +- "google,veyron-mighty-rev1", "google,veyron-mighty", +- "google,veyron", "rockchip,rk3288"; +-}; +- +-&sdmmc { +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin +- &sdmmc_wp_pin &sdmmc_bus4>; +- wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; +- +- /delete-property/ disable-wp; +-}; +- +-&pinctrl { +- sdmmc { +- sdmmc_wp_pin: sdmmc-wp-pin { +- rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-veyron-minnie.dts b/scripts/dtc/include-prefixes/arm/rk3288-veyron-minnie.dts +deleted file mode 100644 +index 82fc6fba9999..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-veyron-minnie.dts ++++ /dev/null +@@ -1,415 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Veyron Minnie Rev 0+ board device tree source +- * +- * Copyright 2015 Google, Inc +- */ +- +-/dts-v1/; +-#include "rk3288-veyron-chromebook.dtsi" +-#include "rk3288-veyron-broadcom-bluetooth.dtsi" +- +-/ { +- model = "Google Minnie"; +- compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3", +- "google,veyron-minnie-rev2", "google,veyron-minnie-rev1", +- "google,veyron-minnie-rev0", "google,veyron-minnie", +- "google,veyron", "rockchip,rk3288"; +- +- volume_buttons: volume-buttons { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&volum_down_l &volum_up_l>; +- +- volum_down { +- label = "Volum_down"; +- gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <100>; +- }; +- +- volum_up { +- label = "Volum_up"; +- gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <100>; +- }; +- }; +-}; +- +-&backlight { +- /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */ +- brightness-levels = <3 255>; +- num-interpolated-steps = <252>; +-}; +- +-&i2c_tunnel { +- battery: bq27500@55 { +- compatible = "ti,bq27500"; +- reg = <0x55>; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +- +- clock-frequency = <400000>; +- i2c-scl-falling-time-ns = <50>; +- i2c-scl-rising-time-ns = <300>; +- +- touchscreen@10 { +- compatible = "elan,ekth3500"; +- reg = <0x10>; +- interrupt-parent = <&gpio2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&touch_int &touch_rst>; +- reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>; +- vcc33-supply = <&vcc33_touch>; +- vccio-supply = <&vcc33_touch>; +- }; +-}; +- +-&panel { +- compatible = "auo,b101ean01"; +- +- /delete-node/ panel-timing; +- +- panel-timing { +- clock-frequency = <66666667>; +- hactive = <1280>; +- hfront-porch = <18>; +- hback-porch = <21>; +- hsync-len = <32>; +- vactive = <800>; +- vfront-porch = <4>; +- vback-porch = <8>; +- vsync-len = <18>; +- }; +-}; +- +-&rk808 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; +- +- regulators { +- vcc33_touch: LDO_REG2 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc33_touch"; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc5v_touch: SWITCH_REG2 { +- regulator-name = "vcc5v_touch"; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +-}; +- +-&sdmmc { +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin +- &sdmmc_bus4>; +-}; +- +-&vcc_5v { +- enable-active-high; +- gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&drv_5v>; +-}; +- +-&vcc50_hdmi { +- enable-active-high; +- gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc50_hdmi_en>; +-}; +- +-&gpio0 { +- gpio-line-names = "PMIC_SLEEP_AP", +- "DDRIO_PWROFF", +- "DDRIO_RETEN", +- "TS3A227E_INT_L", +- "PMIC_INT_L", +- "PWR_KEY_L", +- "AP_LID_INT_L", +- "EC_IN_RW", +- +- "AC_PRESENT_AP", +- /* +- * RECOVERY_SW_L is Chrome OS ABI. Schematics call +- * it REC_MODE_L. +- */ +- "RECOVERY_SW_L", +- "OTP_OUT", +- "HOST1_PWR_EN", +- "USBOTG_PWREN_H", +- "AP_WARM_RESET_H", +- "nFALUT2", +- "I2C0_SDA_PMIC", +- +- "I2C0_SCL_PMIC", +- "SUSPEND_L", +- "USB_INT"; +-}; +- +-&gpio2 { +- gpio-line-names = "CONFIG0", +- "CONFIG1", +- "CONFIG2", +- "", +- "", +- "", +- "", +- "CONFIG3", +- +- "PROCHOT#", +- "EMMC_RST_L", +- "", +- "", +- "BL_PWR_EN", +- "AVDD_1V8_DISP_EN", +- "TOUCH_INT", +- "TOUCH_RST", +- +- "I2C3_SCL_TP", +- "I2C3_SDA_TP"; +-}; +- +-&gpio3 { +- gpio-line-names = "FLASH0_D0", +- "FLASH0_D1", +- "FLASH0_D2", +- "FLASH0_D3", +- "FLASH0_D4", +- "FLASH0_D5", +- "FLASH0_D6", +- "FLASH0_D7", +- +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "FLASH0_CS2/EMMC_CMD", +- "", +- "FLASH0_DQS/EMMC_CLKO"; +-}; +- +-&gpio4 { +- gpio-line-names = "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "UART0_RXD", +- "UART0_TXD", +- "UART0_CTS", +- "UART0_RTS", +- "SDIO0_D0", +- "SDIO0_D1", +- "SDIO0_D2", +- "SDIO0_D3", +- +- "SDIO0_CMD", +- "SDIO0_CLK", +- "dev_wake", +- "", +- "WIFI_ENABLE_H", +- "BT_ENABLE_L", +- "WIFI_HOST_WAKE", +- "BT_HOST_WAKE"; +-}; +- +-&gpio5 { +- gpio-line-names = "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "", +- "", +- "Volum_Up#", +- "Volum_Down#", +- "SPI0_CLK", +- "SPI0_CS0", +- "SPI0_TXD", +- "SPI0_RXD", +- +- "", +- "", +- "", +- "VCC50_HDMI_EN"; +-}; +- +-&gpio6 { +- gpio-line-names = "I2S0_SCLK", +- "I2S0_LRCK_RX", +- "I2S0_LRCK_TX", +- "I2S0_SDI", +- "I2S0_SDO0", +- "HP_DET_H", +- "", +- "INT_CODEC", +- +- "I2S0_CLK", +- "I2C2_SDA", +- "I2C2_SCL", +- "MICDET", +- "", +- "", +- "", +- "", +- +- "SDMMC_D0", +- "SDMMC_D1", +- "SDMMC_D2", +- "SDMMC_D3", +- "SDMMC_CLK", +- "SDMMC_CMD"; +-}; +- +-&gpio7 { +- gpio-line-names = "LCDC_BL", +- "PWM_LOG", +- "BL_EN", +- "TRACKPAD_INT", +- "TPM_INT_H", +- "SDMMC_DET_L", +- /* +- * AP_FLASH_WP_L is Chrome OS ABI. Schematics call +- * it FW_WP_AP. +- */ +- "AP_FLASH_WP_L", +- "EC_INT", +- +- "CPU_NMI", +- "DVS_OK", +- "SDMMC_WP", +- "EDP_HPD", +- "DVS1", +- "nFALUT1", +- "LCD_EN", +- "DVS2", +- +- "VCC5V_GOOD_H", +- "I2C4_SDA_TP", +- "I2C4_SCL_TP", +- "I2C5_SDA_HDMI", +- "I2C5_SCL_HDMI", +- "5V_DRV", +- "UART2_RXD", +- "UART2_TXD"; +-}; +- +-&gpio8 { +- gpio-line-names = "RAM_ID0", +- "RAM_ID1", +- "RAM_ID2", +- "RAM_ID3", +- "I2C1_SDA_TPM", +- "I2C1_SCL_TPM", +- "SPI2_CLK", +- "SPI2_CS0", +- +- "SPI2_RXD", +- "SPI2_TXD"; +-}; +- +-&pinctrl { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = < +- /* Common for sleep and wake, but no owners */ +- &ddr0_retention +- &ddrio_pwroff +- &global_pwroff +- +- /* Wake only */ +- &suspend_l_wake +- >; +- pinctrl-1 = < +- /* Common for sleep and wake, but no owners */ +- &ddr0_retention +- &ddrio_pwroff +- &global_pwroff +- +- /* Sleep only */ +- &suspend_l_sleep +- >; +- +- buck-5v { +- drv_5v: drv-5v { +- rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- buttons { +- volum_down_l: volum-down-l { +- rockchip,pins = <5 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- volum_up_l: volum-up-l { +- rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- hdmi { +- vcc50_hdmi_en: vcc50-hdmi-en { +- rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- dvs_1: dvs-1 { +- rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- dvs_2: dvs-2 { +- rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- prochot { +- gpio_prochot: gpio-prochot { +- rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- touchscreen { +- touch_int: touch-int { +- rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- touch_rst: touch-rst { +- rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-veyron-pinky.dts b/scripts/dtc/include-prefixes/arm/rk3288-veyron-pinky.dts +deleted file mode 100644 +index 4e9fdb0f722d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-veyron-pinky.dts ++++ /dev/null +@@ -1,137 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Veyron Pinky Rev 2 board device tree source +- * +- * Copyright 2015 Google, Inc +- */ +- +-/dts-v1/; +-#include "rk3288-veyron-chromebook.dtsi" +-#include "cros-ec-sbs.dtsi" +- +-/ { +- model = "Google Pinky"; +- compatible = "google,veyron-pinky-rev2", "google,veyron-pinky", +- "google,veyron", "rockchip,rk3288"; +- +- /delete-node/backlight-regulator; +- /delete-node/panel-regulator; +- /delete-node/emmc-pwrseq; +- /delete-node/vcc18-lcd; +-}; +- +-&backlight { +- /delete-property/power-supply; +-}; +- +-&emmc { +- /* +- * Use a pullup instead of a drive since the output is 3.3V and +- * really should be 1.8V (oops). The external pulldown will help +- * bring the voltage down if we only drive with a pullup here. +- * Therefore disable the powerseq (and actual reset) for pinky. +- */ +- /delete-property/mmc-pwrseq; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_reset>; +-}; +- +-&edp { +- /delete-property/pinctrl-names; +- /delete-property/pinctrl-0; +- +- force-hpd; +-}; +- +-&lid_switch { +- pinctrl-0 = <&pwr_key_h &ap_lid_int_l>; +- +- power { +- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-/* Touchpad connector */ +-&i2c3 { +- status = "okay"; +- +- clock-frequency = <400000>; +- i2c-scl-falling-time-ns = <50>; +- i2c-scl-rising-time-ns = <300>; +-}; +- +-&panel { +- power-supply = <&vcc33_lcd>; +-}; +- +-&pinctrl { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = < +- /* Common for sleep and wake, but no owners */ +- &ddr0_retention +- &ddrio_pwroff +- &global_pwroff +- +- /* Wake only */ +- &suspend_l_wake +- &bt_dev_wake_awake +- >; +- pinctrl-1 = < +- /* Common for sleep and wake, but no owners */ +- &ddr0_retention +- &ddrio_pwroff +- &global_pwroff +- +- /* Sleep only */ +- &suspend_l_sleep +- &bt_dev_wake_sleep +- >; +- +- /delete-node/ lcd; +- +- backlight { +- /delete-node/ bl_pwr_en; +- }; +- +- buttons { +- pwr_key_h: pwr-key-h { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- emmc { +- emmc_reset: emmc-reset { +- rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- sdmmc { +- sdmmc_wp_pin: sdmmc-wp-pin { +- rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +- +-&rk808 { +- regulators { +- vcc18_lcd: SWITCH_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc18_lcd"; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +-}; +- +-&sdmmc { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin +- &sdmmc_wp_pin &sdmmc_bus4>; +- wp-gpios = <&gpio7 RK_PB2 GPIO_ACTIVE_HIGH>; +-}; +- +-&tsadc { +- /* Some connection is flaky making the tsadc hang the system */ +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-veyron-sdmmc.dtsi b/scripts/dtc/include-prefixes/arm/rk3288-veyron-sdmmc.dtsi +deleted file mode 100644 +index 27fb06ce907e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-veyron-sdmmc.dtsi ++++ /dev/null +@@ -1,89 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Veyron (and derivatives) fragment for sdmmc cards +- * +- * Copyright 2015 Google, Inc +- */ +- +-&io_domains { +- sdcard-supply = <&vccio_sd>; +-}; +- +-&pinctrl { +- sdmmc { +- /* +- * We run sdmmc at max speed; bump up drive strength. +- * We also have external pulls, so disable the internal ones. +- */ +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <6 RK_PC0 1 &pcfg_pull_none_drv_8ma>, +- <6 RK_PC1 1 &pcfg_pull_none_drv_8ma>, +- <6 RK_PC2 1 &pcfg_pull_none_drv_8ma>, +- <6 RK_PC3 1 &pcfg_pull_none_drv_8ma>; +- }; +- +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <6 RK_PC5 1 &pcfg_pull_none_drv_8ma>; +- }; +- +- /* +- * Builtin CD line is hooked to ground to prevent JTAG at boot +- * (and also to get the voltage rail correct). +- * Configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't +- * think there's a card inserted +- */ +- sdmmc_cd_disabled: sdmmc-cd-disabled { +- rockchip,pins = <6 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- /* This is where we actually hook up CD */ +- sdmmc_cd_pin: sdmmc-cd-pin { +- rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&rk808 { +- vcc9-supply = <&vcc_5v>; +- +- regulators { +- vccio_sd: LDO_REG4 { +- regulator-name = "vccio_sd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc33_sd: LDO_REG5 { +- regulator-name = "vcc33_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +-}; +- +-&sdmmc { +- status = "okay"; +- +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- card-detect-delay = <200>; +- cd-gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>; +- rockchip,default-sample-phase = <90>; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- vmmc-supply = <&vcc33_sd>; +- vqmmc-supply = <&vccio_sd>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-veyron-speedy.dts b/scripts/dtc/include-prefixes/arm/rk3288-veyron-speedy.dts +deleted file mode 100644 +index 4a3ea934d03e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-veyron-speedy.dts ++++ /dev/null +@@ -1,324 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Veyron Speedy Rev 1+ board device tree source +- * +- * Copyright 2015 Google, Inc +- */ +- +-/dts-v1/; +-#include "rk3288-veyron-chromebook.dtsi" +-#include "rk3288-veyron-broadcom-bluetooth.dtsi" +-#include "cros-ec-sbs.dtsi" +- +-/ { +- model = "Google Speedy"; +- compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", +- "google,veyron-speedy-rev7", "google,veyron-speedy-rev6", +- "google,veyron-speedy-rev5", "google,veyron-speedy-rev4", +- "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", +- "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; +-}; +- +-&cpu_alert0 { +- temperature = <65000>; +-}; +- +-&cpu_alert1 { +- temperature = <70000>; +-}; +- +-&cpu_crit { +- temperature = <90000>; +-}; +- +-&edp { +- /delete-property/pinctrl-names; +- /delete-property/pinctrl-0; +- +- force-hpd; +-}; +- +-&gpu_alert0 { +- temperature = <80000>; +-}; +- +-&gpu_crit { +- temperature = <90000>; +-}; +- +-&rk808 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +-}; +- +-&sdmmc { +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin +- &sdmmc_bus4>; +-}; +- +-&vcc_5v { +- enable-active-high; +- gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&drv_5v>; +-}; +- +-&vcc50_hdmi { +- enable-active-high; +- gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc50_hdmi_en>; +-}; +- +-&gpio0 { +- gpio-line-names = "PMIC_SLEEP_AP", +- "DDRIO_PWROFF", +- "DDRIO_RETEN", +- "TS3A227E_INT_L", +- "PMIC_INT_L", +- "PWR_KEY_L", +- "AP_LID_INT_L", +- "EC_IN_RW", +- +- "AC_PRESENT_AP", +- /* +- * RECOVERY_SW_L is Chrome OS ABI. Schematics call +- * it REC_MODE_L. +- */ +- "RECOVERY_SW_L", +- "OTP_OUT", +- "HOST1_PWR_EN", +- "USBOTG_PWREN_H", +- "AP_WARM_RESET_H", +- "nFALUT2", +- "I2C0_SDA_PMIC", +- +- "I2C0_SCL_PMIC", +- "SUSPEND_L", +- "USB_INT"; +-}; +- +-&gpio2 { +- gpio-line-names = "CONFIG0", +- "CONFIG1", +- "CONFIG2", +- "", +- "", +- "", +- "", +- "CONFIG3", +- +- "PWRLIMIT#_CPU", +- "EMMC_RST_L", +- "", +- "", +- "BL_PWR_EN", +- "AVDD_1V8_DISP_EN"; +-}; +- +-&gpio3 { +- gpio-line-names = "FLASH0_D0", +- "FLASH0_D1", +- "FLASH0_D2", +- "FLASH0_D3", +- "FLASH0_D4", +- "FLASH0_D5", +- "FLASH0_D6", +- "FLASH0_D7", +- +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "FLASH0_CS2/EMMC_CMD", +- "", +- "FLASH0_DQS/EMMC_CLKO"; +-}; +- +-&gpio4 { +- gpio-line-names = "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "UART0_RXD", +- "UART0_TXD", +- "UART0_CTS", +- "UART0_RTS", +- "SDIO0_D0", +- "SDIO0_D1", +- "SDIO0_D2", +- "SDIO0_D3", +- +- "SDIO0_CMD", +- "SDIO0_CLK", +- "BT_DEV_WAKE", +- "", +- "WIFI_ENABLE_H", +- "BT_ENABLE_L", +- "WIFI_HOST_WAKE", +- "BT_HOST_WAKE"; +-}; +- +-&gpio5 { +- gpio-line-names = "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- +- "", +- "", +- "", +- "", +- "SPI0_CLK", +- "SPI0_CS0", +- "SPI0_TXD", +- "SPI0_RXD", +- +- "", +- "", +- "", +- "VCC50_HDMI_EN"; +-}; +- +-&gpio6 { +- gpio-line-names = "I2S0_SCLK", +- "I2S0_LRCK_RX", +- "I2S0_LRCK_TX", +- "I2S0_SDI", +- "I2S0_SDO0", +- "HP_DET_H", +- "ALS_INT", /* not connected */ +- "INT_CODEC", +- +- "I2S0_CLK", +- "I2C2_SDA", +- "I2C2_SCL", +- "MICDET", +- "", +- "", +- "", +- "", +- +- "SDMMC_D0", +- "SDMMC_D1", +- "SDMMC_D2", +- "SDMMC_D3", +- "SDMMC_CLK", +- "SDMMC_CMD"; +-}; +- +-&gpio7 { +- gpio-line-names = "LCDC_BL", +- "PWM_LOG", +- "BL_EN", +- "TRACKPAD_INT", +- "TPM_INT_H", +- "SDMMC_DET_L", +- /* +- * AP_FLASH_WP_L is Chrome OS ABI. Schematics call +- * it FW_WP_AP. +- */ +- "AP_FLASH_WP_L", +- "EC_INT", +- +- "CPU_NMI", +- "DVS_OK", +- "", +- "EDP_HOTPLUG", +- "DVS1", +- "nFALUT1", +- "LCD_EN", +- "DVS2", +- +- "VCC5V_GOOD_H", +- "I2C4_SDA_TP", +- "I2C4_SCL_TP", +- "I2C5_SDA_HDMI", +- "I2C5_SCL_HDMI", +- "5V_DRV", +- "UART2_RXD", +- "UART2_TXD"; +-}; +- +-&gpio8 { +- gpio-line-names = "RAM_ID0", +- "RAM_ID1", +- "RAM_ID2", +- "RAM_ID3", +- "I2C1_SDA_TPM", +- "I2C1_SCL_TPM", +- "SPI2_CLK", +- "SPI2_CS0", +- +- "SPI2_RXD", +- "SPI2_TXD"; +-}; +- +-&pinctrl { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = < +- /* Common for sleep and wake, but no owners */ +- &ddr0_retention +- &ddrio_pwroff +- &global_pwroff +- +- /* Wake only */ +- &suspend_l_wake +- >; +- pinctrl-1 = < +- /* Common for sleep and wake, but no owners */ +- &ddr0_retention +- &ddrio_pwroff +- &global_pwroff +- +- /* Sleep only */ +- &suspend_l_sleep +- >; +- +- buck-5v { +- drv_5v: drv-5v { +- rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- hdmi { +- vcc50_hdmi_en: vcc50-hdmi-en { +- rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- dvs_1: dvs-1 { +- rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- dvs_2: dvs-2 { +- rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-veyron-tiger.dts b/scripts/dtc/include-prefixes/arm/rk3288-veyron-tiger.dts +deleted file mode 100644 +index 52a84cbe7a90..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-veyron-tiger.dts ++++ /dev/null +@@ -1,87 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Veyron Tiger Rev 0+ board device tree source +- * +- * Copyright 2016 Google, Inc +- */ +- +-/dts-v1/; +-#include "rk3288-veyron-fievel.dts" +-#include "rk3288-veyron-edp.dtsi" +- +-/ { +- model = "Google Tiger"; +- compatible = "google,veyron-tiger-rev8", "google,veyron-tiger-rev7", +- "google,veyron-tiger-rev6", "google,veyron-tiger-rev5", +- "google,veyron-tiger-rev4", "google,veyron-tiger-rev3", +- "google,veyron-tiger-rev2", "google,veyron-tiger-rev1", +- "google,veyron-tiger-rev0", "google,veyron-tiger", +- "google,veyron", "rockchip,rk3288"; +- +- /delete-node/ vcc18-lcd; +-}; +- +-&backlight { +- /* Tiger panel PWM must be >= 1%, so start non-zero brightness at 3 */ +- brightness-levels = <3 255>; +- num-interpolated-steps = <252>; +-}; +- +-&backlight_regulator { +- vin-supply = <&vccsys>; +-}; +- +-&i2c3 { +- status = "okay"; +- +- clock-frequency = <400000>; +- i2c-scl-falling-time-ns = <50>; +- i2c-scl-rising-time-ns = <300>; +- +- touchscreen@10 { +- compatible = "elan,ekth3500"; +- reg = <0x10>; +- interrupt-parent = <&gpio2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&touch_int &touch_rst>; +- reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>; +- vcc33-supply = <&vcc33_io>; +- vccio-supply = <&vcc33_io>; +- wakeup-source; +- }; +-}; +- +-&panel { +- compatible = "auo,b101ean01"; +- +- /delete-node/ panel-timing; +- +- panel-timing { +- clock-frequency = <66666667>; +- hactive = <1280>; +- hfront-porch = <18>; +- hback-porch = <21>; +- hsync-len = <32>; +- vactive = <800>; +- vfront-porch = <4>; +- vback-porch = <8>; +- vsync-len = <18>; +- }; +-}; +- +-&pinctrl { +- lcd { +- /delete-node/ avdd-1v8-disp-en; +- }; +- +- touchscreen { +- touch_int: touch-int { +- rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- touch_rst: touch-rst { +- rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-veyron.dtsi b/scripts/dtc/include-prefixes/arm/rk3288-veyron.dtsi +deleted file mode 100644 +index 54a6838d73f5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-veyron.dtsi ++++ /dev/null +@@ -1,593 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Veyron (and derivatives) board device tree source +- * +- * Copyright 2015 Google, Inc +- */ +- +-#include +-#include +-#include "rk3288.dtsi" +- +-/ { +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- /* +- * The default coreboot on veyron devices ignores memory@0 nodes +- * and would instead create another memory node. +- */ +- memory { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- +- power_button: power-button { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_key_l>; +- +- power { +- label = "Power"; +- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <100>; +- wakeup-source; +- }; +- }; +- +- gpio-restart { +- compatible = "gpio-restart"; +- gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ap_warm_reset_h>; +- priority = <200>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- pinctrl-0 = <&emmc_reset>; +- pinctrl-names = "default"; +- reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&rk808 RK808_CLKOUT1>; +- clock-names = "ext_clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_enable_h>; +- +- /* +- * Depending on the actual card populated GPIO4 D4 +- * correspond to one of these signals on the module: +- * +- * D4: +- * - SDIO_RESET_L_WL_REG_ON +- * - PDN (power down when low) +- */ +- reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; +- }; +- +- vcc_5v: vcc-5v { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_5v"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- vcc33_sys: vcc33-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc33_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vcc50_hdmi: vcc50-hdmi { +- compatible = "regulator-fixed"; +- regulator-name = "vcc50_hdmi"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_5v>; +- }; +- +- vdd_logic: vdd-logic { +- compatible = "pwm-regulator"; +- regulator-name = "vdd_logic"; +- +- pwms = <&pwm1 0 1994 0>; +- pwm-supply = <&vcc33_sys>; +- +- pwm-dutycycle-range = <0x7b 0>; +- pwm-dutycycle-unit = <0x94>; +- +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <4000>; +- }; +-}; +- +-&cpu0 { +- cpu0-supply = <&vdd_cpu>; +-}; +- +-&cpu_crit { +- temperature = <100000>; +-}; +- +-/* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */ +-&cpu_opp_table { +- /delete-node/ opp-312000000; +- +- opp-1512000000 { +- opp-microvolt = <1250000>; +- }; +- opp-1608000000 { +- opp-microvolt = <1300000>; +- }; +- opp-1704000000 { +- opp-hz = /bits/ 64 <1704000000>; +- opp-microvolt = <1350000>; +- }; +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <1400000>; +- }; +-}; +- +-&emmc { +- status = "okay"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- rockchip,default-sample-phase = <158>; +- disable-wp; +- mmc-hs200-1_8v; +- mmc-pwrseq = <&emmc_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&gpu_alert0 { +- temperature = <72500>; +-}; +- +-&gpu_crit { +- temperature = <100000>; +-}; +- +-&hdmi { +- pinctrl-names = "default", "unwedge"; +- pinctrl-0 = <&hdmi_ddc>; +- pinctrl-1 = <&hdmi_ddc_unwedge>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- clock-frequency = <400000>; +- i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ +- i2c-scl-rising-time-ns = <100>; /* 45ns measured */ +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- clock-output-names = "xin32k", "wifibt_32kin"; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- #clock-cells = <1>; +- +- vcc1-supply = <&vcc33_sys>; +- vcc2-supply = <&vcc33_sys>; +- vcc3-supply = <&vcc33_sys>; +- vcc4-supply = <&vcc33_sys>; +- vcc6-supply = <&vcc_5v>; +- vcc7-supply = <&vcc33_sys>; +- vcc8-supply = <&vcc33_sys>; +- vcc12-supply = <&vcc_18>; +- vddio-supply = <&vcc33_io>; +- +- regulators { +- vdd_cpu: DCDC_REG1 { +- regulator-name = "vdd_arm"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1450000>; +- regulator-ramp-delay = <6001>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: DCDC_REG2 { +- regulator-name = "vdd_gpu"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1250000>; +- regulator-ramp-delay = <6001>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc135_ddr: DCDC_REG3 { +- regulator-name = "vcc135_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- /* +- * vcc_18 has several aliases. (vcc18_flashio and +- * vcc18_wl). We'll add those aliases here just to +- * make it easier to follow the schematic. The signals +- * are actually hooked together and only separated for +- * power measurement purposes). +- */ +- vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 { +- regulator-name = "vcc_18"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- /* +- * Note that both vcc33_io and vcc33_pmuio are always +- * powered together. To simplify the logic in the dts +- * we just refer to vcc33_io every time something is +- * powered from vcc33_pmuio. In fact, on later boards +- * (such as danger) they're the same net. +- */ +- vcc33_io: LDO_REG1 { +- regulator-name = "vcc33_io"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vdd_10: LDO_REG3 { +- regulator-name = "vdd_10"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vdd10_lcd_pwren_h: LDO_REG7 { +- regulator-name = "vdd10_lcd_pwren_h"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc33_lcd: SWITCH_REG1 { +- regulator-name = "vcc33_lcd"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- clock-frequency = <400000>; +- i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ +- i2c-scl-rising-time-ns = <100>; /* 40ns measured */ +- +- tpm: tpm@20 { +- compatible = "infineon,slb9645tt"; +- reg = <0x20>; +- powered-while-suspended; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- +- /* 100kHz since 4.7k resistors don't rise fast enough */ +- clock-frequency = <100000>; +- i2c-scl-falling-time-ns = <50>; /* 10ns measured */ +- i2c-scl-rising-time-ns = <800>; /* 600ns measured */ +-}; +- +-&i2c4 { +- status = "okay"; +- +- clock-frequency = <400000>; +- i2c-scl-falling-time-ns = <50>; /* 11ns measured */ +- i2c-scl-rising-time-ns = <300>; /* 225ns measured */ +-}; +- +-&io_domains { +- status = "okay"; +- +- bb-supply = <&vcc33_io>; +- dvp-supply = <&vcc_18>; +- flash0-supply = <&vcc18_flashio>; +- gpio1830-supply = <&vcc33_io>; +- gpio30-supply = <&vcc33_io>; +- lcdc-supply = <&vcc33_lcd>; +- wifi-supply = <&vcc18_wl>; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&sdio0 { +- status = "okay"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- cap-sdio-irq; +- keep-power-in-suspend; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- vmmc-supply = <&vcc33_sys>; +- vqmmc-supply = <&vcc18_wl>; +-}; +- +-&spi2 { +- status = "okay"; +- +- rx-sample-delay-ns = <12>; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- reg = <0>; +- }; +-}; +- +-&tsadc { +- status = "okay"; +- +- rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ +- rockchip,hw-tshut-temp = <125000>; +-}; +- +-&uart0 { +- status = "okay"; +- +- /* Pins don't include flow control by default; add that in */ +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +- +- needs-reset-on-resume; +-}; +- +-&usb_host1 { +- status = "okay"; +- snps,need-phy-for-wake; +-}; +- +-&usb_otg { +- status = "okay"; +- +- assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; +- assigned-clock-parents = <&usbphy0>; +- dr_mode = "host"; +- snps,need-phy-for-wake; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +- +-&pinctrl { +- pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { +- bias-disable; +- drive-strength = <8>; +- }; +- +- pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { +- bias-pull-up; +- drive-strength = <8>; +- }; +- +- pcfg_output_high: pcfg-output-high { +- output-high; +- }; +- +- pcfg_output_low: pcfg-output-low { +- output-low; +- }; +- +- buttons { +- pwr_key_l: pwr-key-l { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- emmc { +- emmc_reset: emmc-reset { +- rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- /* +- * We run eMMC at max speed; bump up drive strength. +- * We also have external pulls, so disable the internal ones. +- */ +- emmc_clk: emmc-clk { +- rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_drv_8ma>; +- }; +- +- emmc_cmd: emmc-cmd { +- rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_drv_8ma>; +- }; +- +- emmc_bus8: emmc-bus8 { +- rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_drv_8ma>, +- <3 RK_PA1 2 &pcfg_pull_none_drv_8ma>, +- <3 RK_PA2 2 &pcfg_pull_none_drv_8ma>, +- <3 RK_PA3 2 &pcfg_pull_none_drv_8ma>, +- <3 RK_PA4 2 &pcfg_pull_none_drv_8ma>, +- <3 RK_PA5 2 &pcfg_pull_none_drv_8ma>, +- <3 RK_PA6 2 &pcfg_pull_none_drv_8ma>, +- <3 RK_PA7 2 &pcfg_pull_none_drv_8ma>; +- }; +- }; +- +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- reboot { +- ap_warm_reset_h: ap-warm-reset-h { +- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- recovery-switch { +- rec_mode_l: rec-mode-l { +- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- sdio0 { +- wifi_enable_h: wifienable-h { +- rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- /* NOTE: mislabelled on schematic; should be bt_enable_h */ +- bt_enable_l: bt-enable-l { +- rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_host_wake: bt-host-wake { +- rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- bt_host_wake_l: bt-host-wake-l { +- rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- /* +- * We run sdio0 at max speed; bump up drive strength. +- * We also have external pulls, so disable the internal ones. +- */ +- sdio0_bus4: sdio0-bus4 { +- rockchip,pins = <4 RK_PC4 1 &pcfg_pull_none_drv_8ma>, +- <4 RK_PC5 1 &pcfg_pull_none_drv_8ma>, +- <4 RK_PC6 1 &pcfg_pull_none_drv_8ma>, +- <4 RK_PC7 1 &pcfg_pull_none_drv_8ma>; +- }; +- +- sdio0_cmd: sdio0-cmd { +- rockchip,pins = <4 RK_PD0 1 &pcfg_pull_none_drv_8ma>; +- }; +- +- sdio0_clk: sdio0-clk { +- rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>; +- }; +- +- /* +- * These pins are only present on very new veyron boards; on +- * older boards bt_dev_wake is simply always high. Note that +- * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt +- * to map this pin everywhere +- */ +- bt_dev_wake_sleep: bt-dev-wake-sleep { +- rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- +- bt_dev_wake_awake: bt-dev-wake-awake { +- rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- +- bt_dev_wake: bt-dev-wake { +- rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- tpm { +- tpm_int_h: tpm-int-h { +- rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- write-protect { +- fw_wp_ap: fw-wp-ap { +- rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-vmarc-som.dtsi b/scripts/dtc/include-prefixes/arm/rk3288-vmarc-som.dtsi +deleted file mode 100644 +index 0ae2bd150e37..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-vmarc-som.dtsi ++++ /dev/null +@@ -1,362 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd +- * Copyright (c) 2019 Vamrs Limited +- * Copyright (c) 2019 Amarula Solutions(India) +- */ +- +-#include +-#include +- +-/ { +- compatible = "vamrs,rk3288-vmarc-som", "rockchip,rk3288"; +- +- vccio_flash: vccio-flash-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vccio_flash"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_io>; +- }; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- disable-wp; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; +- vmmc-supply = <&vcc_io>; +- vqmmc-supply = <&vccio_flash>; +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_MAC>; +- phy-supply = <&vcc_io>; +- snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_cec_c0>; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- status = "okay"; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int &global_pwroff>; +- rockchip,system-power-controller; +- wakeup-source; +- #clock-cells = <1>; +- clock-output-names = "rk808-clkout1", "rk808-clkout2"; +- +- vcc1-supply = <&vcc5v0_sys>; +- vcc2-supply = <&vcc5v0_sys>; +- vcc3-supply = <&vcc5v0_sys>; +- vcc4-supply = <&vcc5v0_sys>; +- vcc6-supply = <&vcc5v0_sys>; +- vcc7-supply = <&vcc5v0_sys>; +- vcc8-supply = <&vcc_io>; +- vcc9-supply = <&vcc_io>; +- vcc10-supply = <&vcc5v0_sys>; +- vcc11-supply = <&vcc5v0_sys>; +- vcc12-supply = <&vcc_io>; +- vddio-supply = <&vcc_io>; +- +- regulators { +- vdd_cpu: DCDC_REG1 { +- regulator-name = "vdd_arm"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1400000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: DCDC_REG2 { +- regulator-name = "vdd_gpu"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-ramp-delay = <6000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_io: DCDC_REG4 { +- regulator-name = "vcc_io"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_tp: LDO_REG1 { +- regulator-name = "vcc_tp"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcca_codec: LDO_REG2 { +- regulator-name = "vcca_codec"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vdd_10: LDO_REG3 { +- regulator-name = "vdd_10"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc_wl: LDO_REG4 { +- regulator-name = "vcc_wl"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vccio_sd: LDO_REG5 { +- regulator-name = "vccio_sd"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vdd10_lcd: LDO_REG6 { +- regulator-name = "vdd10_lcd"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_18: LDO_REG7 { +- regulator-name = "vcc_18"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc18_lcd: LDO_REG8 { +- regulator-name = "vcc18_lcd"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_sd: SWITCH_REG1 { +- regulator-name = "vcc_sd"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_lcd: SWITCH_REG2 { +- regulator-name = "vcc_lcd"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- status = "okay"; +- +- hym8563: rtc@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- interrupt-parent = <&gpio5>; +- interrupts = ; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "hym8563"; +- pinctrl-names = "default"; +- pinctrl-0 = <&hym8563_int>; +- }; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&io_domains { +- bb-supply = <&vcc_io>; +- flash0-supply = <&vccio_flash>; +- gpio1830-supply = <&vcc_18>; +- gpio30-supply = <&vcc_io>; +- sdcard-supply = <&vccio_sd>; +- wifi-supply = <&vcc_wl>; +- status = "okay"; +-}; +- +-&pinctrl { +- hym8563 { +- hym8563_int: hym8563-int { +- rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { +- drive-strength = <8>; +- }; +- +- pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { +- bias-pull-up; +- drive-strength = <8>; +- }; +- +- pmic { +- pmic_int: pmic-int { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- sdio-pwrseq { +- wifi_enable_h: wifi-enable-h { +- rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdmmc { +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = +- <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, +- <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, +- <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, +- <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; +- }; +- +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; +- }; +- }; +- +- vbus_host { +- usb1_en_oc: usb1-en-oc { +- rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- vbus_typec { +- usb0_en_oc: usb0-en-oc { +- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +- +-&sdio_pwrseq { +- /* +- * On the module itself this is one of these (depending +- * on the actual card populated): +- * - SDIO_RESET_L_WL_REG_ON +- * - PDN (power down when low) +- */ +- reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; /* WIFI_REG_ON */ +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1 { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +- +-&vbus_host { +- enable-active-high; +- gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; /* USB1_EN_OC# */ +-}; +- +-&vbus_typec { +- enable-active-high; +- gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; /* USB0_EN_OC# */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288-vyasa.dts b/scripts/dtc/include-prefixes/arm/rk3288-vyasa.dts +deleted file mode 100644 +index b156a83eb7d7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288-vyasa.dts ++++ /dev/null +@@ -1,500 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2017 Jagan Teki +- */ +- +-/dts-v1/; +-#include "rk3288.dtsi" +- +-/ { +- model = "Amarula Vyasa-RK3288"; +- compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- memory { +- reg = <0x0 0x0 0x0 0x80000000>; +- device_type = "memory"; +- }; +- +- dc12_vbat: dc12-vbat { +- compatible = "regulator-fixed"; +- regulator-name = "dc12_vbat"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vboot_3v3: vboot-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vboot_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&dc12_vbat>; +- }; +- +- vcc_sys: vsys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&dc12_vbat>; +- }; +- +- vboot_5v: vboot-5v { +- compatible = "regulator-fixed"; +- regulator-name = "vboot_sv"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&dc12_vbat>; +- }; +- +- v3g_3v3: v3g-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "v3g_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&dc12_vbat>; +- }; +- +- vsus_5v: vsus-5v { +- compatible = "regulator-fixed"; +- regulator-name = "vsus_5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_io>; +- }; +- +- vcc50_hdmi: vcc50-hdmi { +- compatible = "regulator-fixed"; +- regulator-name = "vcc50_hdmi"; +- enable-active-high; +- gpio = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>; /* HDMI_EN */ +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc50_hdmi_en>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vsus_5v>; +- }; +- +- vusb1_5v: vusb1-5v { +- compatible = "regulator-fixed"; +- regulator-name = "vusb1_5v"; +- enable-active-high; +- gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; /* OTG_VBUS_DRV */ +- pinctrl-names = "default"; +- pinctrl-0 = <&otg_vbus_drv>; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vsus_5v>; +- }; +- +- vusb2_5v: vusb2-5v { +- compatible = "regulator-fixed"; +- regulator-name = "vusb2_5v"; +- enable-active-high; +- gpio = <&gpio8 RK_PB1 GPIO_ACTIVE_HIGH>; /* USB2_PWR_EN */ +- pinctrl-names = "default"; +- pinctrl-0 = <&usb2_pwr_en>; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vsus_5v>; +- }; +- +- ext_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- clock-output-names = "ext_gmac"; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; +- vmmc-supply = <&vcc_io>; +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_MAC>; +- assigned-clock-parents = <&ext_gmac>; +- clock_in_out = "input"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; +- phy-supply = <&vcc_lan>; +- phy-mode = "rgmii"; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 1000000>; +- snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; +- tx_delay = <0x30>; +- rx_delay = <0x10>; +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c5>; +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- status = "okay"; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int &global_pwroff>; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc6-supply = <&vcc_sys>; +- vcc7-supply = <&vcc_sys>; +- vcc8-supply = <&vcc_io>; +- vcc9-supply = <&vcc_sys>; +- vcc10-supply = <&vcc_sys>; +- vcc11-supply = <&vcc_sys>; +- vcc12-supply = <&vcc_io>; +- +- regulators { +- vdd_cpu: DCDC_REG1 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: DCDC_REG2 { +- regulator-name = "vdd_gpu"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1250000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_io: DCDC_REG4 { +- regulator-name = "vcc_io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcca_tp: LDO_REG1 { +- regulator-name = "vcc_tp"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_codec: LDO_REG2 { +- regulator-name = "vcc_codec"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_10: LDO_REG3 { +- regulator-name = "vdd_10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc_gps: LDO_REG4 { +- regulator-name = "vcc_gps"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vccio_sd: LDO_REG5 { +- regulator-name = "vccio_sd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vdd10_lcd: LDO_REG6 { +- regulator-name = "vdd10_lcd"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc_18: LDO_REG7 { +- regulator-name = "vcc_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc18_lcd: LDO_REG8 { +- regulator-name = "vcc18_lcd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc_sd: SWITCH_REG1 { +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_lan: SWITCH_REG2 { +- regulator-name = "vcc_lan"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- }; +- }; +-}; +- +-&i2c5 { +- status = "okay"; +-}; +- +-&io_domains { +- status = "okay"; +- +- audio-supply = <&vcc_18>; +- bb-supply = <&vcc_io>; +- dvp-supply = <&vcc_io>; +- flash0-supply = <&vcc_18>; +- flash1-supply = <&vcc_lan>; +- gpio30-supply = <&vcc_io>; +- gpio1830-supply = <&vcc_io>; +- lcdc-supply = <&vcc_io>; +- sdcard-supply = <&vccio_sd>; +- wifi-supply = <&vcc_18>; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- card-detect-delay = <200>; +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; +- vmmc-supply = <&vcc_sd>; +- vqmmc-supply = <&vccio_sd>; +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&phy_pwr_en>; +- status = "okay"; +-}; +- +-&usb_otg { +- vbus-supply = <&vusb1_5v>; +- status = "okay"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +- +-&pinctrl { +- pcfg_output_high: pcfg-output-high { +- output-high; +- }; +- +- gmac { +- phy_int: phy-int { +- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- phy_pmeb: phy-pmeb { +- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- phy_rst: phy-rst { +- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- }; +- +- hdmi { +- vcc50_hdmi_en: vcc50-hdmi-en { +- rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- pmic_int: pmic-int { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- usb_host { +- phy_pwr_en: phy-pwr-en { +- rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- +- usb2_pwr_en: usb2-pwr-en { +- rockchip,pins = <8 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb_otg { +- otg_vbus_drv: otg-vbus-drv { +- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; +- +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3288.dtsi b/scripts/dtc/include-prefixes/arm/rk3288.dtsi +deleted file mode 100644 +index 66ff5db53c5a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3288.dtsi ++++ /dev/null +@@ -1,2003 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- +- compatible = "rockchip,rk3288"; +- +- interrupt-parent = <&gic>; +- +- aliases { +- ethernet0 = &gmac; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- mshc0 = &emmc; +- mshc1 = &sdmmc; +- mshc2 = &sdio0; +- mshc3 = &sdio1; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- spi0 = &spi0; +- spi1 = &spi1; +- spi2 = &spi2; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a12-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "rockchip,rk3066-smp"; +- rockchip,pmu = <&pmu>; +- +- cpu0: cpu@500 { +- device_type = "cpu"; +- compatible = "arm,cortex-a12"; +- reg = <0x500>; +- resets = <&cru SRST_CORE0>; +- operating-points-v2 = <&cpu_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- clock-latency = <40000>; +- clocks = <&cru ARMCLK>; +- dynamic-power-coefficient = <370>; +- }; +- cpu1: cpu@501 { +- device_type = "cpu"; +- compatible = "arm,cortex-a12"; +- reg = <0x501>; +- resets = <&cru SRST_CORE1>; +- operating-points-v2 = <&cpu_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- clock-latency = <40000>; +- clocks = <&cru ARMCLK>; +- dynamic-power-coefficient = <370>; +- }; +- cpu2: cpu@502 { +- device_type = "cpu"; +- compatible = "arm,cortex-a12"; +- reg = <0x502>; +- resets = <&cru SRST_CORE2>; +- operating-points-v2 = <&cpu_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- clock-latency = <40000>; +- clocks = <&cru ARMCLK>; +- dynamic-power-coefficient = <370>; +- }; +- cpu3: cpu@503 { +- device_type = "cpu"; +- compatible = "arm,cortex-a12"; +- reg = <0x503>; +- resets = <&cru SRST_CORE3>; +- operating-points-v2 = <&cpu_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- clock-latency = <40000>; +- clocks = <&cru ARMCLK>; +- dynamic-power-coefficient = <370>; +- }; +- }; +- +- cpu_opp_table: cpu-opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-126000000 { +- opp-hz = /bits/ 64 <126000000>; +- opp-microvolt = <900000>; +- }; +- opp-216000000 { +- opp-hz = /bits/ 64 <216000000>; +- opp-microvolt = <900000>; +- }; +- opp-312000000 { +- opp-hz = /bits/ 64 <312000000>; +- opp-microvolt = <900000>; +- }; +- opp-408000000 { +- opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <900000>; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <900000>; +- }; +- opp-696000000 { +- opp-hz = /bits/ 64 <696000000>; +- opp-microvolt = <950000>; +- }; +- opp-816000000 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <1000000>; +- }; +- opp-1008000000 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <1050000>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <1100000>; +- }; +- opp-1416000000 { +- opp-hz = /bits/ 64 <1416000000>; +- opp-microvolt = <1200000>; +- }; +- opp-1512000000 { +- opp-hz = /bits/ 64 <1512000000>; +- opp-microvolt = <1300000>; +- }; +- opp-1608000000 { +- opp-hz = /bits/ 64 <1608000000>; +- opp-microvolt = <1350000>; +- }; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- /* +- * The rk3288 cannot use the memory area above 0xfe000000 +- * for dma operations for some reason. While there is +- * probably a better solution available somewhere, we +- * haven't found it yet and while devices with 2GB of ram +- * are not affected, this issue prevents 4GB from booting. +- * So to make these devices at least bootable, block +- * this area for the time being until the real solution +- * is found. +- */ +- dma-unusable@fe000000 { +- reg = <0x0 0xfe000000 0x0 0x1000000>; +- }; +- }; +- +- xin24m: oscillator { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "xin24m"; +- #clock-cells = <0>; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- arm,cpu-registers-not-fw-configured; +- interrupts = , +- , +- , +- ; +- clock-frequency = <24000000>; +- arm,no-tick-in-suspend; +- }; +- +- timer: timer@ff810000 { +- compatible = "rockchip,rk3288-timer"; +- reg = <0x0 0xff810000 0x0 0x20>; +- interrupts = ; +- clocks = <&cru PCLK_TIMER>, <&xin24m>; +- clock-names = "pclk", "timer"; +- }; +- +- display-subsystem { +- compatible = "rockchip,display-subsystem"; +- ports = <&vopl_out>, <&vopb_out>; +- }; +- +- sdmmc: mmc@ff0c0000 { +- compatible = "rockchip,rk3288-dw-mshc"; +- max-frequency = <150000000>; +- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, +- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- interrupts = ; +- reg = <0x0 0xff0c0000 0x0 0x4000>; +- resets = <&cru SRST_MMC0>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- sdio0: mmc@ff0d0000 { +- compatible = "rockchip,rk3288-dw-mshc"; +- max-frequency = <150000000>; +- clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, +- <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- interrupts = ; +- reg = <0x0 0xff0d0000 0x0 0x4000>; +- resets = <&cru SRST_SDIO0>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- sdio1: mmc@ff0e0000 { +- compatible = "rockchip,rk3288-dw-mshc"; +- max-frequency = <150000000>; +- clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, +- <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- interrupts = ; +- reg = <0x0 0xff0e0000 0x0 0x4000>; +- resets = <&cru SRST_SDIO1>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- emmc: mmc@ff0f0000 { +- compatible = "rockchip,rk3288-dw-mshc"; +- max-frequency = <150000000>; +- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, +- <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- interrupts = ; +- reg = <0x0 0xff0f0000 0x0 0x4000>; +- resets = <&cru SRST_EMMC>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- saradc: saradc@ff100000 { +- compatible = "rockchip,saradc"; +- reg = <0x0 0xff100000 0x0 0x100>; +- interrupts = ; +- #io-channel-cells = <1>; +- clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; +- clock-names = "saradc", "apb_pclk"; +- resets = <&cru SRST_SARADC>; +- reset-names = "saradc-apb"; +- status = "disabled"; +- }; +- +- spi0: spi@ff110000 { +- compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; +- clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; +- clock-names = "spiclk", "apb_pclk"; +- dmas = <&dmac_peri 11>, <&dmac_peri 12>; +- dma-names = "tx", "rx"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; +- reg = <0x0 0xff110000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi1: spi@ff120000 { +- compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; +- clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; +- clock-names = "spiclk", "apb_pclk"; +- dmas = <&dmac_peri 13>, <&dmac_peri 14>; +- dma-names = "tx", "rx"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; +- reg = <0x0 0xff120000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi2: spi@ff130000 { +- compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; +- clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; +- clock-names = "spiclk", "apb_pclk"; +- dmas = <&dmac_peri 15>, <&dmac_peri 16>; +- dma-names = "tx", "rx"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; +- reg = <0x0 0xff130000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@ff140000 { +- compatible = "rockchip,rk3288-i2c"; +- reg = <0x0 0xff140000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "i2c"; +- clocks = <&cru PCLK_I2C1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_xfer>; +- status = "disabled"; +- }; +- +- i2c3: i2c@ff150000 { +- compatible = "rockchip,rk3288-i2c"; +- reg = <0x0 0xff150000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "i2c"; +- clocks = <&cru PCLK_I2C3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_xfer>; +- status = "disabled"; +- }; +- +- i2c4: i2c@ff160000 { +- compatible = "rockchip,rk3288-i2c"; +- reg = <0x0 0xff160000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "i2c"; +- clocks = <&cru PCLK_I2C4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_xfer>; +- status = "disabled"; +- }; +- +- i2c5: i2c@ff170000 { +- compatible = "rockchip,rk3288-i2c"; +- reg = <0x0 0xff170000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "i2c"; +- clocks = <&cru PCLK_I2C5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_xfer>; +- status = "disabled"; +- }; +- +- uart0: serial@ff180000 { +- compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff180000 0x0 0x100>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac_peri 1>, <&dmac_peri 2>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer>; +- status = "disabled"; +- }; +- +- uart1: serial@ff190000 { +- compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff190000 0x0 0x100>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac_peri 3>, <&dmac_peri 4>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_xfer>; +- status = "disabled"; +- }; +- +- uart2: serial@ff690000 { +- compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff690000 0x0 0x100>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; +- clock-names = "baudclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_xfer>; +- status = "disabled"; +- }; +- +- uart3: serial@ff1b0000 { +- compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff1b0000 0x0 0x100>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac_peri 7>, <&dmac_peri 8>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_xfer>; +- status = "disabled"; +- }; +- +- uart4: serial@ff1c0000 { +- compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff1c0000 0x0 0x100>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac_peri 9>, <&dmac_peri 10>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_xfer>; +- status = "disabled"; +- }; +- +- dmac_peri: dma-controller@ff250000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xff250000 0x0 0x4000>; +- interrupts = , +- ; +- #dma-cells = <1>; +- arm,pl330-broken-no-flushp; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMAC2>; +- clock-names = "apb_pclk"; +- }; +- +- thermal-zones { +- reserve_thermal: reserve-thermal { +- polling-delay-passive = <1000>; /* milliseconds */ +- polling-delay = <5000>; /* milliseconds */ +- +- thermal-sensors = <&tsadc 0>; +- }; +- +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <100>; /* milliseconds */ +- polling-delay = <5000>; /* milliseconds */ +- +- thermal-sensors = <&tsadc 1>; +- +- trips { +- cpu_alert0: cpu_alert0 { +- temperature = <70000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu_alert1: cpu_alert1 { +- temperature = <75000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu_crit: cpu_crit { +- temperature = <90000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- cooling-device = +- <&cpu0 THERMAL_NO_LIMIT 6>, +- <&cpu1 THERMAL_NO_LIMIT 6>, +- <&cpu2 THERMAL_NO_LIMIT 6>, +- <&cpu3 THERMAL_NO_LIMIT 6>; +- }; +- map1 { +- trip = <&cpu_alert1>; +- cooling-device = +- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- gpu_thermal: gpu-thermal { +- polling-delay-passive = <100>; /* milliseconds */ +- polling-delay = <5000>; /* milliseconds */ +- +- thermal-sensors = <&tsadc 2>; +- +- trips { +- gpu_alert0: gpu_alert0 { +- temperature = <70000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- gpu_crit: gpu_crit { +- temperature = <90000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&gpu_alert0>; +- cooling-device = +- <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- tsadc: tsadc@ff280000 { +- compatible = "rockchip,rk3288-tsadc"; +- reg = <0x0 0xff280000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; +- clock-names = "tsadc", "apb_pclk"; +- resets = <&cru SRST_TSADC>; +- reset-names = "tsadc-apb"; +- pinctrl-names = "init", "default", "sleep"; +- pinctrl-0 = <&otp_pin>; +- pinctrl-1 = <&otp_out>; +- pinctrl-2 = <&otp_pin>; +- #thermal-sensor-cells = <1>; +- rockchip,grf = <&grf>; +- rockchip,hw-tshut-temp = <95000>; +- status = "disabled"; +- }; +- +- gmac: ethernet@ff290000 { +- compatible = "rockchip,rk3288-gmac"; +- reg = <0x0 0xff290000 0x0 0x10000>; +- interrupts = , +- ; +- interrupt-names = "macirq", "eth_wake_irq"; +- rockchip,grf = <&grf>; +- clocks = <&cru SCLK_MAC>, +- <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, +- <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, +- <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; +- clock-names = "stmmaceth", +- "mac_clk_rx", "mac_clk_tx", +- "clk_mac_ref", "clk_mac_refout", +- "aclk_mac", "pclk_mac"; +- resets = <&cru SRST_MAC>; +- reset-names = "stmmaceth"; +- status = "disabled"; +- }; +- +- usb_host0_ehci: usb@ff500000 { +- compatible = "generic-ehci"; +- reg = <0x0 0xff500000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru HCLK_USBHOST0>; +- phys = <&usbphy1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */ +- usb_host0_ohci: usb@ff520000 { +- compatible = "generic-ohci"; +- reg = <0x0 0xff520000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru HCLK_USBHOST0>; +- phys = <&usbphy1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usb_host1: usb@ff540000 { +- compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", +- "snps,dwc2"; +- reg = <0x0 0xff540000 0x0 0x40000>; +- interrupts = ; +- clocks = <&cru HCLK_USBHOST1>; +- clock-names = "otg"; +- dr_mode = "host"; +- phys = <&usbphy2>; +- phy-names = "usb2-phy"; +- snps,reset-phy-on-wake; +- status = "disabled"; +- }; +- +- usb_otg: usb@ff580000 { +- compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", +- "snps,dwc2"; +- reg = <0x0 0xff580000 0x0 0x40000>; +- interrupts = ; +- clocks = <&cru HCLK_OTG0>; +- clock-names = "otg"; +- dr_mode = "otg"; +- g-np-tx-fifo-size = <16>; +- g-rx-fifo-size = <275>; +- g-tx-fifo-size = <256 128 128 64 64 32>; +- phys = <&usbphy0>; +- phy-names = "usb2-phy"; +- status = "disabled"; +- }; +- +- usb_hsic: usb@ff5c0000 { +- compatible = "generic-ehci"; +- reg = <0x0 0xff5c0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru HCLK_HSIC>; +- status = "disabled"; +- }; +- +- dmac_bus_ns: dma-controller@ff600000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xff600000 0x0 0x4000>; +- interrupts = , +- ; +- #dma-cells = <1>; +- arm,pl330-broken-no-flushp; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMAC1>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- i2c0: i2c@ff650000 { +- compatible = "rockchip,rk3288-i2c"; +- reg = <0x0 0xff650000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "i2c"; +- clocks = <&cru PCLK_I2C0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_xfer>; +- status = "disabled"; +- }; +- +- i2c2: i2c@ff660000 { +- compatible = "rockchip,rk3288-i2c"; +- reg = <0x0 0xff660000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "i2c"; +- clocks = <&cru PCLK_I2C2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_xfer>; +- status = "disabled"; +- }; +- +- pwm0: pwm@ff680000 { +- compatible = "rockchip,rk3288-pwm"; +- reg = <0x0 0xff680000 0x0 0x10>; +- #pwm-cells = <3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>; +- clocks = <&cru PCLK_RKPWM>; +- status = "disabled"; +- }; +- +- pwm1: pwm@ff680010 { +- compatible = "rockchip,rk3288-pwm"; +- reg = <0x0 0xff680010 0x0 0x10>; +- #pwm-cells = <3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm1_pin>; +- clocks = <&cru PCLK_RKPWM>; +- status = "disabled"; +- }; +- +- pwm2: pwm@ff680020 { +- compatible = "rockchip,rk3288-pwm"; +- reg = <0x0 0xff680020 0x0 0x10>; +- #pwm-cells = <3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm2_pin>; +- clocks = <&cru PCLK_RKPWM>; +- status = "disabled"; +- }; +- +- pwm3: pwm@ff680030 { +- compatible = "rockchip,rk3288-pwm"; +- reg = <0x0 0xff680030 0x0 0x10>; +- #pwm-cells = <3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm3_pin>; +- clocks = <&cru PCLK_RKPWM>; +- status = "disabled"; +- }; +- +- bus_intmem: sram@ff700000 { +- compatible = "mmio-sram"; +- reg = <0x0 0xff700000 0x0 0x18000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x0 0xff700000 0x18000>; +- smp-sram@0 { +- compatible = "rockchip,rk3066-smp-sram"; +- reg = <0x00 0x10>; +- }; +- }; +- +- pmu_sram: sram@ff720000 { +- compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; +- reg = <0x0 0xff720000 0x0 0x1000>; +- }; +- +- pmu: power-management@ff730000 { +- compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; +- reg = <0x0 0xff730000 0x0 0x100>; +- +- power: power-controller { +- compatible = "rockchip,rk3288-power-controller"; +- #power-domain-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- assigned-clocks = <&cru SCLK_EDP_24M>; +- assigned-clock-parents = <&xin24m>; +- +- /* +- * Note: Although SCLK_* are the working clocks +- * of device without including on the NOC, needed for +- * synchronous reset. +- * +- * The clocks on the which NOC: +- * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. +- * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. +- * ACLK_RGA is on ACLK_RGA_NIU. +- * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. +- * +- * Which clock are device clocks: +- * clocks devices +- * *_IEP IEP:Image Enhancement Processor +- * *_ISP ISP:Image Signal Processing +- * *_VIP VIP:Video Input Processor +- * *_VOP* VOP:Visual Output Processor +- * *_RGA RGA +- * *_EDP* EDP +- * *_LVDS_* LVDS +- * *_HDMI HDMI +- * *_MIPI_* MIPI +- */ +- power-domain@RK3288_PD_VIO { +- reg = ; +- clocks = <&cru ACLK_IEP>, +- <&cru ACLK_ISP>, +- <&cru ACLK_RGA>, +- <&cru ACLK_VIP>, +- <&cru ACLK_VOP0>, +- <&cru ACLK_VOP1>, +- <&cru DCLK_VOP0>, +- <&cru DCLK_VOP1>, +- <&cru HCLK_IEP>, +- <&cru HCLK_ISP>, +- <&cru HCLK_RGA>, +- <&cru HCLK_VIP>, +- <&cru HCLK_VOP0>, +- <&cru HCLK_VOP1>, +- <&cru PCLK_EDP_CTRL>, +- <&cru PCLK_HDMI_CTRL>, +- <&cru PCLK_LVDS_PHY>, +- <&cru PCLK_MIPI_CSI>, +- <&cru PCLK_MIPI_DSI0>, +- <&cru PCLK_MIPI_DSI1>, +- <&cru SCLK_EDP_24M>, +- <&cru SCLK_EDP>, +- <&cru SCLK_ISP_JPE>, +- <&cru SCLK_ISP>, +- <&cru SCLK_RGA>; +- pm_qos = <&qos_vio0_iep>, +- <&qos_vio1_vop>, +- <&qos_vio1_isp_w0>, +- <&qos_vio1_isp_w1>, +- <&qos_vio0_vop>, +- <&qos_vio0_vip>, +- <&qos_vio2_rga_r>, +- <&qos_vio2_rga_w>, +- <&qos_vio1_isp_r>; +- #power-domain-cells = <0>; +- }; +- +- /* +- * Note: The following 3 are HEVC(H.265) clocks, +- * and on the ACLK_HEVC_NIU (NOC). +- */ +- power-domain@RK3288_PD_HEVC { +- reg = ; +- clocks = <&cru ACLK_HEVC>, +- <&cru SCLK_HEVC_CABAC>, +- <&cru SCLK_HEVC_CORE>; +- pm_qos = <&qos_hevc_r>, +- <&qos_hevc_w>; +- #power-domain-cells = <0>; +- }; +- +- /* +- * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC +- * (video endecoder & decoder) clocks that on the +- * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). +- */ +- power-domain@RK3288_PD_VIDEO { +- reg = ; +- clocks = <&cru ACLK_VCODEC>, +- <&cru HCLK_VCODEC>; +- pm_qos = <&qos_video>; +- #power-domain-cells = <0>; +- }; +- +- /* +- * Note: ACLK_GPU is the GPU clock, +- * and on the ACLK_GPU_NIU (NOC). +- */ +- power-domain@RK3288_PD_GPU { +- reg = ; +- clocks = <&cru ACLK_GPU>; +- pm_qos = <&qos_gpu_r>, +- <&qos_gpu_w>; +- #power-domain-cells = <0>; +- }; +- }; +- +- reboot-mode { +- compatible = "syscon-reboot-mode"; +- offset = <0x94>; +- mode-normal = ; +- mode-recovery = ; +- mode-bootloader = ; +- mode-loader = ; +- }; +- }; +- +- sgrf: syscon@ff740000 { +- compatible = "rockchip,rk3288-sgrf", "syscon"; +- reg = <0x0 0xff740000 0x0 0x1000>; +- }; +- +- cru: clock-controller@ff760000 { +- compatible = "rockchip,rk3288-cru"; +- reg = <0x0 0xff760000 0x0 0x1000>; +- rockchip,grf = <&grf>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, +- <&cru PLL_NPLL>, <&cru ACLK_CPU>, +- <&cru HCLK_CPU>, <&cru PCLK_CPU>, +- <&cru ACLK_PERI>, <&cru HCLK_PERI>, +- <&cru PCLK_PERI>; +- assigned-clock-rates = <594000000>, <400000000>, +- <500000000>, <300000000>, +- <150000000>, <75000000>, +- <300000000>, <150000000>, +- <75000000>; +- }; +- +- grf: syscon@ff770000 { +- compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; +- reg = <0x0 0xff770000 0x0 0x1000>; +- +- edp_phy: edp-phy { +- compatible = "rockchip,rk3288-dp-phy"; +- clocks = <&cru SCLK_EDP_24M>; +- clock-names = "24m"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- io_domains: io-domains { +- compatible = "rockchip,rk3288-io-voltage-domain"; +- status = "disabled"; +- }; +- +- usbphy: usbphy { +- compatible = "rockchip,rk3288-usb-phy"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- usbphy0: usb-phy@320 { +- #phy-cells = <0>; +- reg = <0x320>; +- clocks = <&cru SCLK_OTGPHY0>; +- clock-names = "phyclk"; +- #clock-cells = <0>; +- resets = <&cru SRST_USBOTG_PHY>; +- reset-names = "phy-reset"; +- }; +- +- usbphy1: usb-phy@334 { +- #phy-cells = <0>; +- reg = <0x334>; +- clocks = <&cru SCLK_OTGPHY1>; +- clock-names = "phyclk"; +- #clock-cells = <0>; +- resets = <&cru SRST_USBHOST0_PHY>; +- reset-names = "phy-reset"; +- }; +- +- usbphy2: usb-phy@348 { +- #phy-cells = <0>; +- reg = <0x348>; +- clocks = <&cru SCLK_OTGPHY2>; +- clock-names = "phyclk"; +- #clock-cells = <0>; +- resets = <&cru SRST_USBHOST1_PHY>; +- reset-names = "phy-reset"; +- }; +- }; +- }; +- +- wdt: watchdog@ff800000 { +- compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; +- reg = <0x0 0xff800000 0x0 0x100>; +- clocks = <&cru PCLK_WDT>; +- interrupts = ; +- status = "disabled"; +- }; +- +- spdif: sound@ff88b0000 { +- compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; +- reg = <0x0 0xff8b0000 0x0 0x10000>; +- #sound-dai-cells = <0>; +- clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>; +- clock-names = "mclk", "hclk"; +- dmas = <&dmac_bus_s 3>; +- dma-names = "tx"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&spdif_tx>; +- rockchip,grf = <&grf>; +- status = "disabled"; +- }; +- +- i2s: i2s@ff890000 { +- compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; +- reg = <0x0 0xff890000 0x0 0x10000>; +- #sound-dai-cells = <0>; +- interrupts = ; +- clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; +- clock-names = "i2s_clk", "i2s_hclk"; +- dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s0_bus>; +- rockchip,playback-channels = <8>; +- rockchip,capture-channels = <2>; +- status = "disabled"; +- }; +- +- crypto: crypto@ff8a0000 { +- compatible = "rockchip,rk3288-crypto"; +- reg = <0x0 0xff8a0000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, +- <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; +- clock-names = "aclk", "hclk", "sclk", "apb_pclk"; +- resets = <&cru SRST_CRYPTO>; +- reset-names = "crypto-rst"; +- status = "okay"; +- }; +- +- iep_mmu: iommu@ff900800 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff900800 0x0 0x40>; +- interrupts = ; +- clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- isp_mmu: iommu@ff914000 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- rockchip,disable-mmu-reset; +- status = "disabled"; +- }; +- +- rga: rga@ff920000 { +- compatible = "rockchip,rk3288-rga"; +- reg = <0x0 0xff920000 0x0 0x180>; +- interrupts = ; +- clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; +- clock-names = "aclk", "hclk", "sclk"; +- power-domains = <&power RK3288_PD_VIO>; +- resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; +- reset-names = "core", "axi", "ahb"; +- }; +- +- vopb: vop@ff930000 { +- compatible = "rockchip,rk3288-vop"; +- reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; +- clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; +- power-domains = <&power RK3288_PD_VIO>; +- resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; +- reset-names = "axi", "ahb", "dclk"; +- iommus = <&vopb_mmu>; +- status = "disabled"; +- +- vopb_out: port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- vopb_out_hdmi: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&hdmi_in_vopb>; +- }; +- +- vopb_out_edp: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&edp_in_vopb>; +- }; +- +- vopb_out_mipi: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&mipi_in_vopb>; +- }; +- +- vopb_out_lvds: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&lvds_in_vopb>; +- }; +- }; +- }; +- +- vopb_mmu: iommu@ff930300 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff930300 0x0 0x100>; +- interrupts = ; +- clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; +- clock-names = "aclk", "iface"; +- power-domains = <&power RK3288_PD_VIO>; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- vopl: vop@ff940000 { +- compatible = "rockchip,rk3288-vop"; +- reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; +- clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; +- power-domains = <&power RK3288_PD_VIO>; +- resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; +- reset-names = "axi", "ahb", "dclk"; +- iommus = <&vopl_mmu>; +- status = "disabled"; +- +- vopl_out: port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- vopl_out_hdmi: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&hdmi_in_vopl>; +- }; +- +- vopl_out_edp: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&edp_in_vopl>; +- }; +- +- vopl_out_mipi: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&mipi_in_vopl>; +- }; +- +- vopl_out_lvds: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&lvds_in_vopl>; +- }; +- }; +- }; +- +- vopl_mmu: iommu@ff940300 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff940300 0x0 0x100>; +- interrupts = ; +- clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; +- clock-names = "aclk", "iface"; +- power-domains = <&power RK3288_PD_VIO>; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- mipi_dsi: mipi@ff960000 { +- compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; +- reg = <0x0 0xff960000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; +- clock-names = "ref", "pclk"; +- power-domains = <&power RK3288_PD_VIO>; +- rockchip,grf = <&grf>; +- status = "disabled"; +- +- ports { +- mipi_in: port { +- #address-cells = <1>; +- #size-cells = <0>; +- mipi_in_vopb: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vopb_out_mipi>; +- }; +- mipi_in_vopl: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vopl_out_mipi>; +- }; +- }; +- }; +- }; +- +- lvds: lvds@ff96c000 { +- compatible = "rockchip,rk3288-lvds"; +- reg = <0x0 0xff96c000 0x0 0x4000>; +- clocks = <&cru PCLK_LVDS_PHY>; +- clock-names = "pclk_lvds"; +- pinctrl-names = "lcdc"; +- pinctrl-0 = <&lcdc_ctl>; +- power-domains = <&power RK3288_PD_VIO>; +- rockchip,grf = <&grf>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- lvds_in: port@0 { +- reg = <0>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- lvds_in_vopb: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vopb_out_lvds>; +- }; +- lvds_in_vopl: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vopl_out_lvds>; +- }; +- }; +- }; +- }; +- +- edp: dp@ff970000 { +- compatible = "rockchip,rk3288-dp"; +- reg = <0x0 0xff970000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; +- clock-names = "dp", "pclk"; +- phys = <&edp_phy>; +- phy-names = "dp"; +- resets = <&cru SRST_EDP>; +- reset-names = "dp"; +- rockchip,grf = <&grf>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- edp_in: port@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- edp_in_vopb: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vopb_out_edp>; +- }; +- edp_in_vopl: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vopl_out_edp>; +- }; +- }; +- }; +- }; +- +- hdmi: hdmi@ff980000 { +- compatible = "rockchip,rk3288-dw-hdmi"; +- reg = <0x0 0xff980000 0x0 0x20000>; +- reg-io-width = <4>; +- #sound-dai-cells = <0>; +- rockchip,grf = <&grf>; +- interrupts = ; +- clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; +- clock-names = "iahb", "isfr", "cec"; +- power-domains = <&power RK3288_PD_VIO>; +- status = "disabled"; +- +- ports { +- hdmi_in: port { +- #address-cells = <1>; +- #size-cells = <0>; +- hdmi_in_vopb: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vopb_out_hdmi>; +- }; +- hdmi_in_vopl: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vopl_out_hdmi>; +- }; +- }; +- }; +- }; +- +- vpu: video-codec@ff9a0000 { +- compatible = "rockchip,rk3288-vpu"; +- reg = <0x0 0xff9a0000 0x0 0x800>; +- interrupts = , +- ; +- interrupt-names = "vepu", "vdpu"; +- clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; +- clock-names = "aclk", "hclk"; +- iommus = <&vpu_mmu>; +- power-domains = <&power RK3288_PD_VIDEO>; +- }; +- +- vpu_mmu: iommu@ff9a0800 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff9a0800 0x0 0x100>; +- interrupts = ; +- clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- power-domains = <&power RK3288_PD_VIDEO>; +- }; +- +- hevc_mmu: iommu@ff9c0440 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; +- interrupts = ; +- clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- gpu: gpu@ffa30000 { +- compatible = "rockchip,rk3288-mali", "arm,mali-t760"; +- reg = <0x0 0xffa30000 0x0 0x10000>; +- interrupts = , +- , +- ; +- interrupt-names = "job", "mmu", "gpu"; +- clocks = <&cru ACLK_GPU>; +- operating-points-v2 = <&gpu_opp_table>; +- #cooling-cells = <2>; /* min followed by max */ +- power-domains = <&power RK3288_PD_GPU>; +- status = "disabled"; +- }; +- +- gpu_opp_table: gpu-opp-table { +- compatible = "operating-points-v2"; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- opp-microvolt = <950000>; +- }; +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- opp-microvolt = <950000>; +- }; +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <1000000>; +- }; +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <1100000>; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <1250000>; +- }; +- }; +- +- qos_gpu_r: qos@ffaa0000 { +- compatible = "rockchip,rk3288-qos", "syscon"; +- reg = <0x0 0xffaa0000 0x0 0x20>; +- }; +- +- qos_gpu_w: qos@ffaa0080 { +- compatible = "rockchip,rk3288-qos", "syscon"; +- reg = <0x0 0xffaa0080 0x0 0x20>; +- }; +- +- qos_vio1_vop: qos@ffad0000 { +- compatible = "rockchip,rk3288-qos", "syscon"; +- reg = <0x0 0xffad0000 0x0 0x20>; +- }; +- +- qos_vio1_isp_w0: qos@ffad0100 { +- compatible = "rockchip,rk3288-qos", "syscon"; +- reg = <0x0 0xffad0100 0x0 0x20>; +- }; +- +- qos_vio1_isp_w1: qos@ffad0180 { +- compatible = "rockchip,rk3288-qos", "syscon"; +- reg = <0x0 0xffad0180 0x0 0x20>; +- }; +- +- qos_vio0_vop: qos@ffad0400 { +- compatible = "rockchip,rk3288-qos", "syscon"; +- reg = <0x0 0xffad0400 0x0 0x20>; +- }; +- +- qos_vio0_vip: qos@ffad0480 { +- compatible = "rockchip,rk3288-qos", "syscon"; +- reg = <0x0 0xffad0480 0x0 0x20>; +- }; +- +- qos_vio0_iep: qos@ffad0500 { +- compatible = "rockchip,rk3288-qos", "syscon"; +- reg = <0x0 0xffad0500 0x0 0x20>; +- }; +- +- qos_vio2_rga_r: qos@ffad0800 { +- compatible = "rockchip,rk3288-qos", "syscon"; +- reg = <0x0 0xffad0800 0x0 0x20>; +- }; +- +- qos_vio2_rga_w: qos@ffad0880 { +- compatible = "rockchip,rk3288-qos", "syscon"; +- reg = <0x0 0xffad0880 0x0 0x20>; +- }; +- +- qos_vio1_isp_r: qos@ffad0900 { +- compatible = "rockchip,rk3288-qos", "syscon"; +- reg = <0x0 0xffad0900 0x0 0x20>; +- }; +- +- qos_video: qos@ffae0000 { +- compatible = "rockchip,rk3288-qos", "syscon"; +- reg = <0x0 0xffae0000 0x0 0x20>; +- }; +- +- qos_hevc_r: qos@ffaf0000 { +- compatible = "rockchip,rk3288-qos", "syscon"; +- reg = <0x0 0xffaf0000 0x0 0x20>; +- }; +- +- qos_hevc_w: qos@ffaf0080 { +- compatible = "rockchip,rk3288-qos", "syscon"; +- reg = <0x0 0xffaf0080 0x0 0x20>; +- }; +- +- dmac_bus_s: dma-controller@ffb20000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xffb20000 0x0 0x4000>; +- interrupts = , +- ; +- #dma-cells = <1>; +- arm,pl330-broken-no-flushp; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMAC1>; +- clock-names = "apb_pclk"; +- }; +- +- efuse: efuse@ffb40000 { +- compatible = "rockchip,rk3288-efuse"; +- reg = <0x0 0xffb40000 0x0 0x20>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&cru PCLK_EFUSE256>; +- clock-names = "pclk_efuse"; +- +- cpu_id: cpu-id@7 { +- reg = <0x07 0x10>; +- }; +- cpu_leakage: cpu_leakage@17 { +- reg = <0x17 0x1>; +- }; +- }; +- +- gic: interrupt-controller@ffc01000 { +- compatible = "arm,gic-400"; +- interrupt-controller; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- +- reg = <0x0 0xffc01000 0x0 0x1000>, +- <0x0 0xffc02000 0x0 0x2000>, +- <0x0 0xffc04000 0x0 0x2000>, +- <0x0 0xffc06000 0x0 0x2000>; +- interrupts = ; +- }; +- +- pinctrl: pinctrl { +- compatible = "rockchip,rk3288-pinctrl"; +- rockchip,grf = <&grf>; +- rockchip,pmu = <&pmu>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gpio0: gpio0@ff750000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff750000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio1@ff780000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff780000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO1>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio2@ff790000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff790000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO2>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio3@ff7a0000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff7a0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO3>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio4: gpio4@ff7b0000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff7b0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO4>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio5: gpio5@ff7c0000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff7c0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO5>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio6: gpio6@ff7d0000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff7d0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO6>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio7: gpio7@ff7e0000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff7e0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO7>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio8: gpio8@ff7f0000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff7f0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO8>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- hdmi { +- hdmi_cec_c0: hdmi-cec-c0 { +- rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>; +- }; +- +- hdmi_cec_c7: hdmi-cec-c7 { +- rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>; +- }; +- +- hdmi_ddc: hdmi-ddc { +- rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>, +- <7 RK_PC4 2 &pcfg_pull_none>; +- }; +- +- hdmi_ddc_unwedge: hdmi-ddc-unwedge { +- rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>, +- <7 RK_PC4 2 &pcfg_pull_none>; +- }; +- }; +- +- pcfg_output_low: pcfg-output-low { +- output-low; +- }; +- +- pcfg_pull_up: pcfg-pull-up { +- bias-pull-up; +- }; +- +- pcfg_pull_down: pcfg-pull-down { +- bias-pull-down; +- }; +- +- pcfg_pull_none: pcfg-pull-none { +- bias-disable; +- }; +- +- pcfg_pull_none_12ma: pcfg-pull-none-12ma { +- bias-disable; +- drive-strength = <12>; +- }; +- +- suspend { +- global_pwroff: global-pwroff { +- rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>; +- }; +- +- ddrio_pwroff: ddrio-pwroff { +- rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; +- }; +- +- ddr0_retention: ddr0-retention { +- rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>; +- }; +- +- ddr1_retention: ddr1-retention { +- rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; +- }; +- }; +- +- edp { +- edp_hpd: edp-hpd { +- rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>; +- }; +- }; +- +- i2c0 { +- i2c0_xfer: i2c0-xfer { +- rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>, +- <0 RK_PC0 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c1 { +- i2c1_xfer: i2c1-xfer { +- rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>, +- <8 RK_PA5 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c2 { +- i2c2_xfer: i2c2-xfer { +- rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>, +- <6 RK_PB2 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c3 { +- i2c3_xfer: i2c3-xfer { +- rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>, +- <2 RK_PC1 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c4 { +- i2c4_xfer: i2c4-xfer { +- rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>, +- <7 RK_PC2 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c5 { +- i2c5_xfer: i2c5-xfer { +- rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>, +- <7 RK_PC4 1 &pcfg_pull_none>; +- }; +- }; +- +- i2s0 { +- i2s0_bus: i2s0-bus { +- rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>, +- <6 RK_PA1 1 &pcfg_pull_none>, +- <6 RK_PA2 1 &pcfg_pull_none>, +- <6 RK_PA3 1 &pcfg_pull_none>, +- <6 RK_PA4 1 &pcfg_pull_none>, +- <6 RK_PB0 1 &pcfg_pull_none>; +- }; +- }; +- +- lcdc { +- lcdc_ctl: lcdc-ctl { +- rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, +- <1 RK_PD1 1 &pcfg_pull_none>, +- <1 RK_PD2 1 &pcfg_pull_none>, +- <1 RK_PD3 1 &pcfg_pull_none>; +- }; +- }; +- +- sdmmc { +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>; +- }; +- +- sdmmc_cd: sdmmc-cd { +- rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>; +- }; +- +- sdmmc_bus1: sdmmc-bus1 { +- rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>; +- }; +- +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>, +- <6 RK_PC1 1 &pcfg_pull_up>, +- <6 RK_PC2 1 &pcfg_pull_up>, +- <6 RK_PC3 1 &pcfg_pull_up>; +- }; +- }; +- +- sdio0 { +- sdio0_bus1: sdio0-bus1 { +- rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>; +- }; +- +- sdio0_bus4: sdio0-bus4 { +- rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>, +- <4 RK_PC5 1 &pcfg_pull_up>, +- <4 RK_PC6 1 &pcfg_pull_up>, +- <4 RK_PC7 1 &pcfg_pull_up>; +- }; +- +- sdio0_cmd: sdio0-cmd { +- rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>; +- }; +- +- sdio0_clk: sdio0-clk { +- rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>; +- }; +- +- sdio0_cd: sdio0-cd { +- rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>; +- }; +- +- sdio0_wp: sdio0-wp { +- rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>; +- }; +- +- sdio0_pwr: sdio0-pwr { +- rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>; +- }; +- +- sdio0_bkpwr: sdio0-bkpwr { +- rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>; +- }; +- +- sdio0_int: sdio0-int { +- rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>; +- }; +- }; +- +- sdio1 { +- sdio1_bus1: sdio1-bus1 { +- rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>; +- }; +- +- sdio1_bus4: sdio1-bus4 { +- rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>, +- <3 RK_PD1 4 &pcfg_pull_up>, +- <3 RK_PD2 4 &pcfg_pull_up>, +- <3 RK_PD3 4 &pcfg_pull_up>; +- }; +- +- sdio1_cd: sdio1-cd { +- rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>; +- }; +- +- sdio1_wp: sdio1-wp { +- rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>; +- }; +- +- sdio1_bkpwr: sdio1-bkpwr { +- rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>; +- }; +- +- sdio1_int: sdio1-int { +- rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>; +- }; +- +- sdio1_cmd: sdio1-cmd { +- rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>; +- }; +- +- sdio1_clk: sdio1-clk { +- rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>; +- }; +- +- sdio1_pwr: sdio1-pwr { +- rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>; +- }; +- }; +- +- emmc { +- emmc_clk: emmc-clk { +- rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>; +- }; +- +- emmc_cmd: emmc-cmd { +- rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>; +- }; +- +- emmc_pwr: emmc-pwr { +- rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>; +- }; +- +- emmc_bus1: emmc-bus1 { +- rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>; +- }; +- +- emmc_bus4: emmc-bus4 { +- rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, +- <3 RK_PA1 2 &pcfg_pull_up>, +- <3 RK_PA2 2 &pcfg_pull_up>, +- <3 RK_PA3 2 &pcfg_pull_up>; +- }; +- +- emmc_bus8: emmc-bus8 { +- rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, +- <3 RK_PA1 2 &pcfg_pull_up>, +- <3 RK_PA2 2 &pcfg_pull_up>, +- <3 RK_PA3 2 &pcfg_pull_up>, +- <3 RK_PA4 2 &pcfg_pull_up>, +- <3 RK_PA5 2 &pcfg_pull_up>, +- <3 RK_PA6 2 &pcfg_pull_up>, +- <3 RK_PA7 2 &pcfg_pull_up>; +- }; +- }; +- +- spi0 { +- spi0_clk: spi0-clk { +- rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>; +- }; +- spi0_cs0: spi0-cs0 { +- rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>; +- }; +- spi0_tx: spi0-tx { +- rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>; +- }; +- spi0_rx: spi0-rx { +- rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>; +- }; +- spi0_cs1: spi0-cs1 { +- rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>; +- }; +- }; +- spi1 { +- spi1_clk: spi1-clk { +- rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>; +- }; +- spi1_cs0: spi1-cs0 { +- rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>; +- }; +- spi1_rx: spi1-rx { +- rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>; +- }; +- spi1_tx: spi1-tx { +- rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>; +- }; +- }; +- +- spi2 { +- spi2_cs1: spi2-cs1 { +- rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>; +- }; +- spi2_clk: spi2-clk { +- rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>; +- }; +- spi2_cs0: spi2-cs0 { +- rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>; +- }; +- spi2_rx: spi2-rx { +- rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>; +- }; +- spi2_tx: spi2-tx { +- rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>; +- }; +- }; +- +- uart0 { +- uart0_xfer: uart0-xfer { +- rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>, +- <4 RK_PC1 1 &pcfg_pull_none>; +- }; +- +- uart0_cts: uart0-cts { +- rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>; +- }; +- +- uart0_rts: uart0-rts { +- rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>; +- }; +- }; +- +- uart1 { +- uart1_xfer: uart1-xfer { +- rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>, +- <5 RK_PB1 1 &pcfg_pull_none>; +- }; +- +- uart1_cts: uart1-cts { +- rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>; +- }; +- +- uart1_rts: uart1-rts { +- rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>; +- }; +- }; +- +- uart2 { +- uart2_xfer: uart2-xfer { +- rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>, +- <7 RK_PC7 1 &pcfg_pull_none>; +- }; +- /* no rts / cts for uart2 */ +- }; +- +- uart3 { +- uart3_xfer: uart3-xfer { +- rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>, +- <7 RK_PB0 1 &pcfg_pull_none>; +- }; +- +- uart3_cts: uart3-cts { +- rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>; +- }; +- +- uart3_rts: uart3-rts { +- rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>; +- }; +- }; +- +- uart4 { +- uart4_xfer: uart4-xfer { +- rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>, +- <5 RK_PB6 3 &pcfg_pull_none>; +- }; +- +- uart4_cts: uart4-cts { +- rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>; +- }; +- +- uart4_rts: uart4-rts { +- rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>; +- }; +- }; +- +- tsadc { +- otp_pin: otp-pin { +- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- otp_out: otp-out { +- rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm0 { +- pwm0_pin: pwm0-pin { +- rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm1 { +- pwm1_pin: pwm1-pin { +- rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm2 { +- pwm2_pin: pwm2-pin { +- rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>; +- }; +- }; +- +- pwm3 { +- pwm3_pin: pwm3-pin { +- rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>; +- }; +- }; +- +- gmac { +- rgmii_pins: rgmii-pins { +- rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, +- <3 RK_PD7 3 &pcfg_pull_none>, +- <3 RK_PD2 3 &pcfg_pull_none>, +- <3 RK_PD3 3 &pcfg_pull_none>, +- <3 RK_PD4 3 &pcfg_pull_none_12ma>, +- <3 RK_PD5 3 &pcfg_pull_none_12ma>, +- <3 RK_PD0 3 &pcfg_pull_none_12ma>, +- <3 RK_PD1 3 &pcfg_pull_none_12ma>, +- <4 RK_PA0 3 &pcfg_pull_none>, +- <4 RK_PA5 3 &pcfg_pull_none>, +- <4 RK_PA6 3 &pcfg_pull_none>, +- <4 RK_PB1 3 &pcfg_pull_none_12ma>, +- <4 RK_PA4 3 &pcfg_pull_none_12ma>, +- <4 RK_PA1 3 &pcfg_pull_none>, +- <4 RK_PA3 3 &pcfg_pull_none>; +- }; +- +- rmii_pins: rmii-pins { +- rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, +- <3 RK_PD7 3 &pcfg_pull_none>, +- <3 RK_PD4 3 &pcfg_pull_none>, +- <3 RK_PD5 3 &pcfg_pull_none>, +- <4 RK_PA0 3 &pcfg_pull_none>, +- <4 RK_PA5 3 &pcfg_pull_none>, +- <4 RK_PA4 3 &pcfg_pull_none>, +- <4 RK_PA1 3 &pcfg_pull_none>, +- <4 RK_PA2 3 &pcfg_pull_none>, +- <4 RK_PA3 3 &pcfg_pull_none>; +- }; +- }; +- +- spdif { +- spdif_tx: spdif-tx { +- rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rk3xxx.dtsi b/scripts/dtc/include-prefixes/arm/rk3xxx.dtsi +deleted file mode 100644 +index 616a828e0c6e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rk3xxx.dtsi ++++ /dev/null +@@ -1,483 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2013 MundoReader S.L. +- * Author: Heiko Stuebner +- */ +- +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- interrupt-parent = <&gic>; +- +- aliases { +- ethernet0 = &emac; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- spi0 = &spi0; +- spi1 = &spi1; +- }; +- +- xin24m: oscillator { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- #clock-cells = <0>; +- clock-output-names = "xin24m"; +- }; +- +- gpu: gpu@10090000 { +- compatible = "arm,mali-400"; +- reg = <0x10090000 0x10000>; +- clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; +- clock-names = "bus", "core"; +- assigned-clocks = <&cru ACLK_GPU>; +- assigned-clock-rates = <100000000>; +- resets = <&cru SRST_GPU>; +- status = "disabled"; +- }; +- +- vpu: video-codec@10104000 { +- compatible = "rockchip,rk3066-vpu"; +- reg = <0x10104000 0x800>; +- interrupts = , +- ; +- interrupt-names = "vepu", "vdpu"; +- clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>, +- <&cru ACLK_VEPU>, <&cru HCLK_VEPU>; +- clock-names = "aclk_vdpu", "hclk_vdpu", +- "aclk_vepu", "hclk_vepu"; +- }; +- +- L2: cache-controller@10138000 { +- compatible = "arm,pl310-cache"; +- reg = <0x10138000 0x1000>; +- cache-unified; +- cache-level = <2>; +- }; +- +- scu@1013c000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0x1013c000 0x100>; +- }; +- +- global_timer: global-timer@1013c200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0x1013c200 0x20>; +- interrupts = ; +- clocks = <&cru CORE_PERI>; +- }; +- +- local_timer: local-timer@1013c600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x1013c600 0x20>; +- interrupts = ; +- clocks = <&cru CORE_PERI>; +- }; +- +- gic: interrupt-controller@1013d000 { +- compatible = "arm,cortex-a9-gic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x1013d000 0x1000>, +- <0x1013c100 0x0100>; +- }; +- +- uart0: serial@10124000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x10124000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <1>; +- clock-names = "baudclk", "apb_pclk"; +- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; +- status = "disabled"; +- }; +- +- uart1: serial@10126000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x10126000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <1>; +- clock-names = "baudclk", "apb_pclk"; +- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; +- status = "disabled"; +- }; +- +- qos_gpu: qos@1012d000 { +- compatible = "rockchip,rk3066-qos", "syscon"; +- reg = <0x1012d000 0x20>; +- }; +- +- qos_vpu: qos@1012e000 { +- compatible = "rockchip,rk3066-qos", "syscon"; +- reg = <0x1012e000 0x20>; +- }; +- +- qos_lcdc0: qos@1012f000 { +- compatible = "rockchip,rk3066-qos", "syscon"; +- reg = <0x1012f000 0x20>; +- }; +- +- qos_cif0: qos@1012f080 { +- compatible = "rockchip,rk3066-qos", "syscon"; +- reg = <0x1012f080 0x20>; +- }; +- +- qos_ipp: qos@1012f100 { +- compatible = "rockchip,rk3066-qos", "syscon"; +- reg = <0x1012f100 0x20>; +- }; +- +- qos_lcdc1: qos@1012f180 { +- compatible = "rockchip,rk3066-qos", "syscon"; +- reg = <0x1012f180 0x20>; +- }; +- +- qos_cif1: qos@1012f200 { +- compatible = "rockchip,rk3066-qos", "syscon"; +- reg = <0x1012f200 0x20>; +- }; +- +- qos_rga: qos@1012f280 { +- compatible = "rockchip,rk3066-qos", "syscon"; +- reg = <0x1012f280 0x20>; +- }; +- +- usb_otg: usb@10180000 { +- compatible = "rockchip,rk3066-usb", "snps,dwc2"; +- reg = <0x10180000 0x40000>; +- interrupts = ; +- clocks = <&cru HCLK_OTG0>; +- clock-names = "otg"; +- dr_mode = "otg"; +- g-np-tx-fifo-size = <16>; +- g-rx-fifo-size = <275>; +- g-tx-fifo-size = <256 128 128 64 64 32>; +- phys = <&usbphy0>; +- phy-names = "usb2-phy"; +- status = "disabled"; +- }; +- +- usb_host: usb@101c0000 { +- compatible = "snps,dwc2"; +- reg = <0x101c0000 0x40000>; +- interrupts = ; +- clocks = <&cru HCLK_OTG1>; +- clock-names = "otg"; +- dr_mode = "host"; +- phys = <&usbphy1>; +- phy-names = "usb2-phy"; +- status = "disabled"; +- }; +- +- emac: ethernet@10204000 { +- compatible = "snps,arc-emac"; +- reg = <0x10204000 0x3c>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rockchip,grf = <&grf>; +- +- clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; +- clock-names = "hclk", "macref"; +- max-speed = <100>; +- phy-mode = "rmii"; +- +- status = "disabled"; +- }; +- +- mmc0: mmc@10214000 { +- compatible = "rockchip,rk2928-dw-mshc"; +- reg = <0x10214000 0x1000>; +- interrupts = ; +- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; +- clock-names = "biu", "ciu"; +- dmas = <&dmac2 1>; +- dma-names = "rx-tx"; +- fifo-depth = <256>; +- resets = <&cru SRST_SDMMC>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- mmc1: mmc@10218000 { +- compatible = "rockchip,rk2928-dw-mshc"; +- reg = <0x10218000 0x1000>; +- interrupts = ; +- clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; +- clock-names = "biu", "ciu"; +- dmas = <&dmac2 3>; +- dma-names = "rx-tx"; +- fifo-depth = <256>; +- resets = <&cru SRST_SDIO>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- emmc: mmc@1021c000 { +- compatible = "rockchip,rk2928-dw-mshc"; +- reg = <0x1021c000 0x1000>; +- interrupts = ; +- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; +- clock-names = "biu", "ciu"; +- dmas = <&dmac2 4>; +- dma-names = "rx-tx"; +- fifo-depth = <256>; +- resets = <&cru SRST_EMMC>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- nfc: nand-controller@10500000 { +- compatible = "rockchip,rk2928-nfc"; +- reg = <0x10500000 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_NANDC0>; +- clock-names = "ahb"; +- status = "disabled"; +- }; +- +- pmu: pmu@20004000 { +- compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; +- reg = <0x20004000 0x100>; +- +- reboot-mode { +- compatible = "syscon-reboot-mode"; +- offset = <0x40>; +- mode-normal = ; +- mode-recovery = ; +- mode-bootloader = ; +- mode-loader = ; +- }; +- }; +- +- grf: grf@20008000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x20008000 0x200>; +- }; +- +- dmac1_s: dma-controller@20018000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x20018000 0x4000>; +- interrupts = , +- ; +- #dma-cells = <1>; +- arm,pl330-broken-no-flushp; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMA1>; +- clock-names = "apb_pclk"; +- }; +- +- dmac1_ns: dma-controller@2001c000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x2001c000 0x4000>; +- interrupts = , +- ; +- #dma-cells = <1>; +- arm,pl330-broken-no-flushp; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMA1>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- i2c0: i2c@2002d000 { +- compatible = "rockchip,rk3066-i2c"; +- reg = <0x2002d000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rockchip,grf = <&grf>; +- +- clock-names = "i2c"; +- clocks = <&cru PCLK_I2C0>; +- +- status = "disabled"; +- }; +- +- i2c1: i2c@2002f000 { +- compatible = "rockchip,rk3066-i2c"; +- reg = <0x2002f000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rockchip,grf = <&grf>; +- +- clocks = <&cru PCLK_I2C1>; +- clock-names = "i2c"; +- +- status = "disabled"; +- }; +- +- pwm0: pwm@20030000 { +- compatible = "rockchip,rk2928-pwm"; +- reg = <0x20030000 0x10>; +- #pwm-cells = <2>; +- clocks = <&cru PCLK_PWM01>; +- status = "disabled"; +- }; +- +- pwm1: pwm@20030010 { +- compatible = "rockchip,rk2928-pwm"; +- reg = <0x20030010 0x10>; +- #pwm-cells = <2>; +- clocks = <&cru PCLK_PWM01>; +- status = "disabled"; +- }; +- +- wdt: watchdog@2004c000 { +- compatible = "snps,dw-wdt"; +- reg = <0x2004c000 0x100>; +- clocks = <&cru PCLK_WDT>; +- interrupts = ; +- status = "disabled"; +- }; +- +- pwm2: pwm@20050020 { +- compatible = "rockchip,rk2928-pwm"; +- reg = <0x20050020 0x10>; +- #pwm-cells = <2>; +- clocks = <&cru PCLK_PWM23>; +- status = "disabled"; +- }; +- +- pwm3: pwm@20050030 { +- compatible = "rockchip,rk2928-pwm"; +- reg = <0x20050030 0x10>; +- #pwm-cells = <2>; +- clocks = <&cru PCLK_PWM23>; +- status = "disabled"; +- }; +- +- i2c2: i2c@20056000 { +- compatible = "rockchip,rk3066-i2c"; +- reg = <0x20056000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rockchip,grf = <&grf>; +- +- clocks = <&cru PCLK_I2C2>; +- clock-names = "i2c"; +- +- status = "disabled"; +- }; +- +- i2c3: i2c@2005a000 { +- compatible = "rockchip,rk3066-i2c"; +- reg = <0x2005a000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rockchip,grf = <&grf>; +- +- clocks = <&cru PCLK_I2C3>; +- clock-names = "i2c"; +- +- status = "disabled"; +- }; +- +- i2c4: i2c@2005e000 { +- compatible = "rockchip,rk3066-i2c"; +- reg = <0x2005e000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rockchip,grf = <&grf>; +- +- clocks = <&cru PCLK_I2C4>; +- clock-names = "i2c"; +- +- status = "disabled"; +- }; +- +- uart2: serial@20064000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x20064000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <1>; +- clock-names = "baudclk", "apb_pclk"; +- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; +- status = "disabled"; +- }; +- +- uart3: serial@20068000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x20068000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <1>; +- clock-names = "baudclk", "apb_pclk"; +- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; +- status = "disabled"; +- }; +- +- saradc: saradc@2006c000 { +- compatible = "rockchip,saradc"; +- reg = <0x2006c000 0x100>; +- interrupts = ; +- #io-channel-cells = <1>; +- clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; +- clock-names = "saradc", "apb_pclk"; +- resets = <&cru SRST_SARADC>; +- reset-names = "saradc-apb"; +- status = "disabled"; +- }; +- +- spi0: spi@20070000 { +- compatible = "rockchip,rk3066-spi"; +- clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; +- clock-names = "spiclk", "apb_pclk"; +- interrupts = ; +- reg = <0x20070000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- dmas = <&dmac2 10>, <&dmac2 11>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- spi1: spi@20074000 { +- compatible = "rockchip,rk3066-spi"; +- clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; +- clock-names = "spiclk", "apb_pclk"; +- interrupts = ; +- reg = <0x20074000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- dmas = <&dmac2 12>, <&dmac2 13>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- dmac2: dma-controller@20078000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x20078000 0x4000>; +- interrupts = , +- ; +- #dma-cells = <1>; +- arm,pl330-broken-no-flushp; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMA2>; +- clock-names = "apb_pclk"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rockchip-radxa-dalang-carrier.dtsi b/scripts/dtc/include-prefixes/arm/rockchip-radxa-dalang-carrier.dtsi +deleted file mode 100644 +index da1d548b7330..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rockchip-radxa-dalang-carrier.dtsi ++++ /dev/null +@@ -1,137 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd +- * Copyright (c) 2019 Radxa Limited +- * Copyright (c) 2019 Amarula Solutions(India) +- */ +- +-#include +- +-/ { +- clkin_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "clkin_gmac"; +- #clock-cells = <0>; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&hym8563>; +- clock-names = "ext_clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_enable_h>; +- }; +- +- vcc12v_dcin: vcc12v-dcin-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc12v_dcin"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- vcc5v0_sys: vcc5v0-sys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc12v_dcin>; +- }; +- +- vbus_host: vbus-host { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb1_en_oc>; +- regulator-name = "vbus_host"; /* HOST-5V */ +- regulator-always-on; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vbus_typec: vbus-typec { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb0_en_oc>; +- regulator-name = "vbus_typec"; +- regulator-always-on; +- vin-supply = <&vcc5v0_sys>; +- }; +-}; +- +-&gmac { +- assigned-clock-parents = <&clkin_gmac>; +- clock_in_out = "input"; +- phy-mode = "rgmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 50000>; +- tx_delay = <0x28>; +- rx_delay = <0x11>; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&sdio0 { +- bus-width = <4>; +- cap-sd-highspeed; +- cap-sdio-irq; +- keep-power-in-suspend; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; +- sd-uhs-sdr104; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- disable-wp; +- vqmmc-supply = <&vccio_sd>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts>; +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rtd1195-horseradish.dts b/scripts/dtc/include-prefixes/arm/rtd1195-horseradish.dts +deleted file mode 100644 +index 9d06d3d34c74..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rtd1195-horseradish.dts ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +-/* +- * Copyright (c) 2019 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "rtd1195.dtsi" +- +-/ { +- compatible = "realtek,horseradish", "realtek,rtd1195"; +- model = "Realtek Horseradish EVB"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@a800 { +- device_type = "memory"; +- reg = <0x0000a800 0x17ff5800>, /* boot ROM to r-bus */ +- <0x18070000 0x00090000>, /* r-bus to NOR flash */ +- <0x19100000 0x26f00000>; /* NOR flash to 1 GiB */ +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rtd1195-mele-x1000.dts b/scripts/dtc/include-prefixes/arm/rtd1195-mele-x1000.dts +deleted file mode 100644 +index c7951b9a2c97..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rtd1195-mele-x1000.dts ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +-/* +- * Copyright (c) 2017-2019 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "rtd1195.dtsi" +- +-/ { +- compatible = "mele,x1000", "realtek,rtd1195"; +- model = "MeLE X1000"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@a800 { +- device_type = "memory"; +- reg = <0x0000a800 0x17ff5800>, /* boot ROM to r-bus */ +- <0x18070000 0x00090000>, /* r-bus to NOR flash */ +- <0x19100000 0x26f00000>; /* NOR flash to 1 GiB */ +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rtd1195.dtsi b/scripts/dtc/include-prefixes/arm/rtd1195.dtsi +deleted file mode 100644 +index 21897210d9d0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rtd1195.dtsi ++++ /dev/null +@@ -1,217 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +-/* +- * Copyright (c) 2017-2019 Andreas Färber +- */ +- +-/memreserve/ 0x00000000 0x0000a800; /* boot code */ +-/memreserve/ 0x0000a800 0x000f5800; +-/memreserve/ 0x17fff000 0x00001000; +- +-#include +-#include +- +-/ { +- compatible = "realtek,rtd1195"; +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x0>; +- clock-frequency = <1000000000>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x1>; +- clock-frequency = <1000000000>; +- }; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- rpc_comm: rpc@b000 { +- reg = <0x0000b000 0x1000>; +- }; +- +- audio@1b00000 { +- reg = <0x01b00000 0x400000>; +- }; +- +- rpc_ringbuf: rpc@1ffe000 { +- reg = <0x01ffe000 0x4000>; +- }; +- +- secure@10000000 { +- reg = <0x10000000 0x100000>; +- no-map; +- }; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupts = , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- clock-frequency = <27000000>; +- }; +- +- osc27M: osc { +- compatible = "fixed-clock"; +- clock-frequency = <27000000>; +- #clock-cells = <0>; +- clock-output-names = "osc27M"; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x0000a800>, +- <0x18000000 0x18000000 0x00070000>, +- <0x18100000 0x18100000 0x01000000>, +- <0x80000000 0x80000000 0x80000000>; +- +- rbus: bus@18000000 { +- compatible = "simple-bus"; +- reg = <0x18000000 0x70000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x18000000 0x70000>; +- +- crt: syscon@0 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x0 0x1000>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1000>; +- }; +- +- iso: syscon@7000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x7000 0x1000>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x7000 0x1000>; +- }; +- +- sb2: syscon@1a000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x1a000 0x1000>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1a000 0x1000>; +- }; +- +- misc: syscon@1b000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x1b000 0x1000>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1b000 0x1000>; +- }; +- +- scpu_wrapper: syscon@1d000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x1d000 0x1000>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1d000 0x1000>; +- }; +- }; +- +- gic: interrupt-controller@ff011000 { +- compatible = "arm,cortex-a7-gic"; +- reg = <0xff011000 0x1000>, +- <0xff012000 0x2000>, +- <0xff014000 0x2000>, +- <0xff016000 0x2000>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- }; +-}; +- +-&crt { +- reset1: reset-controller@0 { +- compatible = "snps,dw-low-reset"; +- reg = <0x0 0x4>; +- #reset-cells = <1>; +- }; +- +- reset2: reset-controller@4 { +- compatible = "snps,dw-low-reset"; +- reg = <0x4 0x4>; +- #reset-cells = <1>; +- }; +- +- reset3: reset-controller@8 { +- compatible = "snps,dw-low-reset"; +- reg = <0x8 0x4>; +- #reset-cells = <1>; +- }; +-}; +- +-&iso { +- iso_reset: reset-controller@88 { +- compatible = "snps,dw-low-reset"; +- reg = <0x88 0x4>; +- #reset-cells = <1>; +- }; +- +- wdt: watchdog@680 { +- compatible = "realtek,rtd1295-watchdog"; +- reg = <0x680 0x100>; +- clocks = <&osc27M>; +- }; +- +- uart0: serial@800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x800 0x400>; +- reg-shift = <2>; +- reg-io-width = <4>; +- resets = <&iso_reset RTD1195_ISO_RSTN_UR0>; +- clock-frequency = <27000000>; +- status = "disabled"; +- }; +-}; +- +-&misc { +- uart1: serial@200 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x200 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; +- resets = <&reset2 RTD1195_RSTN_UR1>; +- clock-frequency = <27000000>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rv1108-elgin-r1.dts b/scripts/dtc/include-prefixes/arm/rv1108-elgin-r1.dts +deleted file mode 100644 +index f62c9f7af79d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rv1108-elgin-r1.dts ++++ /dev/null +@@ -1,211 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-/* +- * Copyright (C) 2018 O.S. Systems Software LTDA. +- */ +- +-/dts-v1/; +- +-#include "rv1108.dtsi" +- +-/ { +- model = "Elgin RV1108 R1 board"; +- compatible = "elgin,rv1108-r1", "rockchip,rv1108"; +- +- aliases { +- mmc0 = &emmc; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x08000000>; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- vcc_sys: vsys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vsys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_core>; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- no-sd; +- no-sdio; +- non-removable; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +- status = "okay"; +-}; +- +-&gmac { +- clock_in_out = "output"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rmii_pins>; +- snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- i2c-scl-rising-time-ns = <275>; +- i2c-scl-falling-time-ns = <16>; +- status = "okay"; +- +- rk805: pmic@18 { +- compatible = "rockchip,rk805"; +- reg = <0x18>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- rockchip,system-power-controller; +- +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc5-supply = <&vdd_buck2>; +- vcc6-supply = <&vdd_buck2>; +- +- regulators { +- vdd_core: DCDC_REG1 { +- regulator-name= "vdd_core"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <900000>; +- }; +- }; +- +- vdd_buck2: DCDC_REG2 { +- regulator-name= "vdd_buck2"; +- regulator-min-microvolt = <2200000>; +- regulator-max-microvolt = <2200000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name= "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_io: DCDC_REG4 { +- regulator-name= "vcc_io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vdd_10: LDO_REG1 { +- regulator-name= "vdd_10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_18: LDO_REG2 { +- regulator-name= "vcc_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd10_pmu: LDO_REG3 { +- regulator-name= "vdd10_pmu"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- }; +- }; +-}; +- +-&spi { +- pinctrl-names = "default"; +- pinctrl-0 = <&spim1_clk &spim1_cs0 &spim1_tx &spim1_rx>; +- status = "okay"; +- +- dh2228fv: dac@0 { +- compatible = "rohm,dh2228fv"; +- reg = <0>; +- spi-max-frequency = <24000000>; +- spi-cpha; +- spi-cpol; +- }; +-}; +- +-&u2phy { +- status = "okay"; +- +- u2phy_host: host-port { +- status = "okay"; +- }; +- +- u2phy_otg: otg-port { +- status = "okay"; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer>; +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host_ehci { +- status = "okay"; +-}; +- +-&usb_host_ohci { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rv1108-evb.dts b/scripts/dtc/include-prefixes/arm/rv1108-evb.dts +deleted file mode 100644 +index fe5fc9bf75c9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rv1108-evb.dts ++++ /dev/null +@@ -1,229 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-/dts-v1/; +- +-#include "rv1108.dtsi" +- +-/ { +- model = "Rockchip RV1108 Evaluation board"; +- compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; +- +- aliases { +- mmc0 = &sdmmc; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x08000000>; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- brightness-levels = < +- 0 1 2 3 4 5 6 7 +- 8 9 10 11 12 13 14 15 +- 16 17 18 19 20 21 22 23 +- 24 25 26 27 28 29 30 31 +- 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 +- 48 49 50 51 52 53 54 55 +- 56 57 58 59 60 61 62 63 +- 64 65 66 67 68 69 70 71 +- 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 +- 88 89 90 91 92 93 94 95 +- 96 97 98 99 100 101 102 103 +- 104 105 106 107 108 109 110 111 +- 112 113 114 115 116 117 118 119 +- 120 121 122 123 124 125 126 127 +- 128 129 130 131 132 133 134 135 +- 136 137 138 139 140 141 142 143 +- 144 145 146 147 148 149 150 151 +- 152 153 154 155 156 157 158 159 +- 160 161 162 163 164 165 166 167 +- 168 169 170 171 172 173 174 175 +- 176 177 178 179 180 181 182 183 +- 184 185 186 187 188 189 190 191 +- 192 193 194 195 196 197 198 199 +- 200 201 202 203 204 205 206 207 +- 208 209 210 211 212 213 214 215 +- 216 217 218 219 220 221 222 223 +- 224 225 226 227 228 229 230 231 +- 232 233 234 235 236 237 238 239 +- 240 241 242 243 244 245 246 247 +- 248 249 250 251 252 253 254 255>; +- default-brightness-level = <200>; +- pwms = <&pwm0 0 25000 0>; +- }; +- +- vcc_sys: vsys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vsys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_core>; +-}; +- +-&i2c0 { +- status = "okay"; +- i2c-scl-rising-time-ns = <275>; +- i2c-scl-falling-time-ns = <16>; +- clock-frequency = <400000>; +- +- rk805: pmic@18 { +- compatible = "rockchip,rk805"; +- reg = <0x18>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- rockchip,system-power-controller; +- +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc5-supply = <&vcc_sys>; +- vcc6-supply = <&vcc_sys>; +- +- regulators { +- vdd_core: DCDC_REG1 { +- regulator-name= "vdd_core"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <900000>; +- }; +- }; +- +- vdd_cam: DCDC_REG2 { +- regulator-name= "vdd_cam"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <2000000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name= "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_io: DCDC_REG4 { +- regulator-name= "vcc_io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vdd_10: LDO_REG1 { +- regulator-name= "vdd_10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_18: LDO_REG2 { +- regulator-name= "vcc_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd10_pmu: LDO_REG3 { +- regulator-name= "vdd10_pmu"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- }; +- }; +- +- bma250: accelerometer@19 { +- compatible = "bosch,bma250e"; +- reg = <0x19>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- }; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&sdmmc { +- status = "okay"; +-}; +- +-&tsadc { +- status = "okay"; +-}; +- +-&u2phy { +- status = "okay"; +- +- u2phy_host: host-port { +- status = "okay"; +- }; +- +- u2phy_otg: otg-port { +- status = "okay"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host_ehci { +- status = "okay"; +-}; +- +-&usb_host_ohci { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/rv1108.dtsi b/scripts/dtc/include-prefixes/arm/rv1108.dtsi +deleted file mode 100644 +index 24d56849af46..000000000000 +--- a/scripts/dtc/include-prefixes/arm/rv1108.dtsi ++++ /dev/null +@@ -1,991 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-#include +-#include +-#include +-#include +-#include +-#include +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- compatible = "rockchip,rv1108"; +- +- interrupt-parent = <&gic>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@f00 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0xf00>; +- clock-latency = <40000>; +- clocks = <&cru ARMCLK>; +- #cooling-cells = <2>; /* min followed by max */ +- dynamic-power-coefficient = <75>; +- operating-points-v2 = <&cpu_opp_table>; +- }; +- }; +- +- cpu_opp_table: opp_table { +- compatible = "operating-points-v2"; +- +- opp-408000000 { +- opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <975000>; +- clock-latency-ns = <40000>; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <975000>; +- clock-latency-ns = <40000>; +- }; +- opp-816000000 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <1025000>; +- clock-latency-ns = <40000>; +- }; +- opp-1008000000 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <1150000>; +- clock-latency-ns = <40000>; +- }; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupts = ; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- ; +- arm,cpu-registers-not-fw-configured; +- clock-frequency = <24000000>; +- }; +- +- xin24m: oscillator { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "xin24m"; +- #clock-cells = <0>; +- }; +- +- amba: bus { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- pdma: pdma@102a0000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x102a0000 0x4000>; +- interrupts = ; +- #dma-cells = <1>; +- arm,pl330-broken-no-flushp; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMAC>; +- clock-names = "apb_pclk"; +- }; +- }; +- +- bus_intmem: sram@10080000 { +- compatible = "mmio-sram"; +- reg = <0x10080000 0x2000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x10080000 0x2000>; +- }; +- +- uart2: serial@10210000 { +- compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; +- reg = <0x10210000 0x100>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <24000000>; +- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&pdma 6>, <&pdma 7>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2m0_xfer>; +- status = "disabled"; +- }; +- +- uart1: serial@10220000 { +- compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; +- reg = <0x10220000 0x100>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <24000000>; +- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&pdma 4>, <&pdma 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_xfer>; +- status = "disabled"; +- }; +- +- uart0: serial@10230000 { +- compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; +- reg = <0x10230000 0x100>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <24000000>; +- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&pdma 2>, <&pdma 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +- status = "disabled"; +- }; +- +- i2c1: i2c@10240000 { +- compatible = "rockchip,rv1108-i2c"; +- reg = <0x10240000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; +- clock-names = "i2c", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_xfer>; +- rockchip,grf = <&grf>; +- status = "disabled"; +- }; +- +- i2c2: i2c@10250000 { +- compatible = "rockchip,rv1108-i2c"; +- reg = <0x10250000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; +- clock-names = "i2c", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2m1_xfer>; +- rockchip,grf = <&grf>; +- status = "disabled"; +- }; +- +- i2c3: i2c@10260000 { +- compatible = "rockchip,rv1108-i2c"; +- reg = <0x10260000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; +- clock-names = "i2c", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_xfer>; +- rockchip,grf = <&grf>; +- status = "disabled"; +- }; +- +- spi: spi@10270000 { +- compatible = "rockchip,rv1108-spi"; +- reg = <0x10270000 0x1000>; +- interrupts = ; +- clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; +- clock-names = "spiclk", "apb_pclk"; +- dmas = <&pdma 8>, <&pdma 9>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pwm4: pwm@10280000 { +- compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; +- reg = <0x10280000 0x10>; +- interrupts = ; +- clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm4_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm5: pwm@10280010 { +- compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; +- reg = <0x10280010 0x10>; +- interrupts = ; +- clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm5_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm6: pwm@10280020 { +- compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; +- reg = <0x10280020 0x10>; +- interrupts = ; +- clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm6_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm7: pwm@10280030 { +- compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; +- reg = <0x10280030 0x10>; +- interrupts = ; +- clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm7_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- grf: syscon@10300000 { +- compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd"; +- reg = <0x10300000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- io_domains: io-domains { +- compatible = "rockchip,rv1108-io-voltage-domain"; +- status = "disabled"; +- }; +- +- u2phy: usb2phy@100 { +- compatible = "rockchip,rv1108-usb2phy"; +- reg = <0x100 0x0c>; +- clocks = <&cru SCLK_USBPHY>; +- clock-names = "phyclk"; +- #clock-cells = <0>; +- clock-output-names = "usbphy"; +- rockchip,usbgrf = <&usbgrf>; +- status = "disabled"; +- +- u2phy_otg: otg-port { +- interrupts = ; +- interrupt-names = "otg-mux"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- u2phy_host: host-port { +- interrupts = ; +- interrupt-names = "linestate"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- }; +- +- timer: timer@10350000 { +- compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer"; +- reg = <0x10350000 0x20>; +- interrupts = ; +- clocks = <&xin24m>, <&cru PCLK_TIMER>; +- clock-names = "timer", "pclk"; +- }; +- +- watchdog: watchdog@10360000 { +- compatible = "rockchip,rv1108-wdt", "snps,dw-wdt"; +- reg = <0x10360000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_WDT>; +- status = "disabled"; +- }; +- +- thermal-zones { +- soc_thermal: soc-thermal { +- polling-delay-passive = <20>; +- polling-delay = <1000>; +- sustainable-power = <50>; +- thermal-sensors = <&tsadc 0>; +- +- trips { +- threshold: trip-point0 { +- temperature = <70000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- target: trip-point1 { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- soc_crit: soc-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&target>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- contribution = <4096>; +- }; +- }; +- }; +- }; +- +- tsadc: tsadc@10370000 { +- compatible = "rockchip,rv1108-tsadc"; +- reg = <0x10370000 0x100>; +- interrupts = ; +- assigned-clocks = <&cru SCLK_TSADC>; +- assigned-clock-rates = <750000>; +- clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; +- clock-names = "tsadc", "apb_pclk"; +- pinctrl-names = "init", "default", "sleep"; +- pinctrl-0 = <&otp_pin>; +- pinctrl-1 = <&otp_out>; +- pinctrl-2 = <&otp_pin>; +- resets = <&cru SRST_TSADC>; +- reset-names = "tsadc-apb"; +- rockchip,hw-tshut-temp = <120000>; +- #thermal-sensor-cells = <1>; +- status = "disabled"; +- }; +- +- adc: adc@1038c000 { +- compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; +- reg = <0x1038c000 0x100>; +- interrupts = ; +- #io-channel-cells = <1>; +- clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; +- clock-names = "saradc", "apb_pclk"; +- status = "disabled"; +- }; +- +- i2c0: i2c@20000000 { +- compatible = "rockchip,rv1108-i2c"; +- reg = <0x20000000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>; +- clock-names = "i2c", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_xfer>; +- rockchip,grf = <&grf>; +- status = "disabled"; +- }; +- +- pwm0: pwm@20040000 { +- compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; +- reg = <0x20040000 0x10>; +- interrupts = ; +- clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm1: pwm@20040010 { +- compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; +- reg = <0x20040010 0x10>; +- interrupts = ; +- clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm1_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm2: pwm@20040020 { +- compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; +- reg = <0x20040020 0x10>; +- interrupts = ; +- clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm2_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm3: pwm@20040030 { +- compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; +- reg = <0x20040030 0x10>; +- interrupts = ; +- clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm3_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pmugrf: syscon@20060000 { +- compatible = "rockchip,rv1108-pmugrf", "syscon", "simple-mfd"; +- reg = <0x20060000 0x1000>; +- +- pmu_io_domains: io-domains { +- compatible = "rockchip,rv1108-pmu-io-voltage-domain"; +- status = "disabled"; +- }; +- }; +- +- usbgrf: syscon@202a0000 { +- compatible = "rockchip,rv1108-usbgrf", "syscon"; +- reg = <0x202a0000 0x1000>; +- }; +- +- cru: clock-controller@20200000 { +- compatible = "rockchip,rv1108-cru"; +- reg = <0x20200000 0x1000>; +- rockchip,grf = <&grf>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- nfc: nand-controller@30100000 { +- compatible = "rockchip,rv1108-nfc"; +- reg = <0x30100000 0x1000>; +- interrupts = ; +- clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; +- clock-names = "ahb", "nfc"; +- assigned-clocks = <&cru SCLK_NANDC>; +- assigned-clock-rates = <150000000>; +- status = "disabled"; +- }; +- +- emmc: mmc@30110000 { +- compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x30110000 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, +- <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- max-frequency = <150000000>; +- status = "disabled"; +- }; +- +- sdio: mmc@30120000 { +- compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x30120000 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, +- <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- max-frequency = <150000000>; +- status = "disabled"; +- }; +- +- sdmmc: mmc@30130000 { +- compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x30130000 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, +- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- max-frequency = <100000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +- status = "disabled"; +- }; +- +- usb_host_ehci: usb@30140000 { +- compatible = "generic-ehci"; +- reg = <0x30140000 0x20000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST0>, <&u2phy>; +- phys = <&u2phy_host>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usb_host_ohci: usb@30160000 { +- compatible = "generic-ohci"; +- reg = <0x30160000 0x20000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST0>, <&u2phy>; +- phys = <&u2phy_host>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usb_otg: usb@30180000 { +- compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb", +- "snps,dwc2"; +- reg = <0x30180000 0x40000>; +- interrupts = ; +- clocks = <&cru HCLK_OTG>; +- clock-names = "otg"; +- dr_mode = "otg"; +- g-np-tx-fifo-size = <16>; +- g-rx-fifo-size = <280>; +- g-tx-fifo-size = <256 128 128 64 32 16>; +- phys = <&u2phy_otg>; +- phy-names = "usb2-phy"; +- status = "disabled"; +- }; +- +- sfc: spi@301c0000 { +- compatible = "rockchip,sfc"; +- reg = <0x301c0000 0x4000>; +- interrupts = ; +- clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; +- clock-names = "clk_sfc", "hclk_sfc"; +- pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- gmac: eth@30200000 { +- compatible = "rockchip,rv1108-gmac"; +- reg = <0x30200000 0x10000>; +- interrupts = , +- ; +- interrupt-names = "macirq", "eth_wake_irq"; +- clocks = <&cru SCLK_MAC>, +- <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>, +- <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, +- <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; +- clock-names = "stmmaceth", +- "mac_clk_rx", "mac_clk_tx", +- "clk_mac_ref", "clk_mac_refout", +- "aclk_mac", "pclk_mac"; +- /* rv1108 only supports an rmii interface */ +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rmii_pins>; +- rockchip,grf = <&grf>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@32010000 { +- compatible = "arm,gic-400"; +- interrupt-controller; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- +- reg = <0x32011000 0x1000>, +- <0x32012000 0x2000>, +- <0x32014000 0x2000>, +- <0x32016000 0x2000>; +- interrupts = ; +- }; +- +- pinctrl: pinctrl { +- compatible = "rockchip,rv1108-pinctrl"; +- rockchip,grf = <&grf>; +- rockchip,pmu = <&pmugrf>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gpio0: gpio0@20030000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x20030000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO0_PMU>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio1@10310000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x10310000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO1>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio2@10320000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x10320000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO2>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio3@10330000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x10330000 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO3>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pcfg_pull_up: pcfg-pull-up { +- bias-pull-up; +- }; +- +- pcfg_pull_down: pcfg-pull-down { +- bias-pull-down; +- }; +- +- pcfg_pull_none: pcfg-pull-none { +- bias-disable; +- }; +- +- pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { +- drive-strength = <8>; +- }; +- +- pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { +- drive-strength = <12>; +- }; +- +- pcfg_pull_none_smt: pcfg-pull-none-smt { +- bias-disable; +- input-schmitt-enable; +- }; +- +- pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { +- bias-pull-up; +- drive-strength = <8>; +- }; +- +- pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { +- drive-strength = <4>; +- }; +- +- pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { +- bias-pull-up; +- drive-strength = <4>; +- }; +- +- pcfg_output_high: pcfg-output-high { +- output-high; +- }; +- +- pcfg_output_low: pcfg-output-low { +- output-low; +- }; +- +- pcfg_input_high: pcfg-input-high { +- bias-pull-up; +- input-enable; +- }; +- +- emmc { +- emmc_bus8: emmc-bus8 { +- rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>, +- <2 RK_PA1 2 &pcfg_pull_up_drv_8ma>, +- <2 RK_PA2 2 &pcfg_pull_up_drv_8ma>, +- <2 RK_PA3 2 &pcfg_pull_up_drv_8ma>, +- <2 RK_PA4 2 &pcfg_pull_up_drv_8ma>, +- <2 RK_PA5 2 &pcfg_pull_up_drv_8ma>, +- <2 RK_PA6 2 &pcfg_pull_up_drv_8ma>, +- <2 RK_PA7 2 &pcfg_pull_up_drv_8ma>; +- }; +- +- emmc_clk: emmc-clk { +- rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>; +- }; +- +- emmc_cmd: emmc-cmd { +- rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>; +- }; +- }; +- +- sfc { +- sfc_bus4: sfc-bus4 { +- rockchip,pins = +- <2 RK_PA0 3 &pcfg_pull_none>, +- <2 RK_PA1 3 &pcfg_pull_none>, +- <2 RK_PA2 3 &pcfg_pull_none>, +- <2 RK_PA3 3 &pcfg_pull_none>; +- }; +- +- sfc_bus2: sfc-bus2 { +- rockchip,pins = +- <2 RK_PA0 3 &pcfg_pull_none>, +- <2 RK_PA1 3 &pcfg_pull_none>; +- }; +- +- sfc_cs0: sfc-cs0 { +- rockchip,pins = +- <2 RK_PB4 3 &pcfg_pull_none>; +- }; +- +- sfc_clk: sfc-clk { +- rockchip,pins = +- <2 RK_PB7 2 &pcfg_pull_none>; +- }; +- }; +- +- gmac { +- rmii_pins: rmii-pins { +- rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>, +- <1 RK_PC3 2 &pcfg_pull_none>, +- <1 RK_PC4 2 &pcfg_pull_none>, +- <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>, +- <1 RK_PB3 3 &pcfg_pull_none_drv_12ma>, +- <1 RK_PB4 3 &pcfg_pull_none_drv_12ma>, +- <1 RK_PB5 3 &pcfg_pull_none>, +- <1 RK_PB6 3 &pcfg_pull_none>, +- <1 RK_PB7 3 &pcfg_pull_none>, +- <1 RK_PC2 3 &pcfg_pull_none>; +- }; +- }; +- +- i2c0 { +- i2c0_xfer: i2c0-xfer { +- rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>, +- <0 RK_PB2 1 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c1 { +- i2c1_xfer: i2c1-xfer { +- rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>, +- <2 RK_PD4 1 &pcfg_pull_up>; +- }; +- }; +- +- i2c2m1 { +- i2c2m1_xfer: i2c2m1-xfer { +- rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>, +- <0 RK_PC6 3 &pcfg_pull_none>; +- }; +- +- i2c2m1_pins: i2c2m1-pins { +- rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, +- <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- i2c2m05v { +- i2c2m05v_xfer: i2c2m05v-xfer { +- rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>, +- <1 RK_PD4 2 &pcfg_pull_none>; +- }; +- +- i2c2m05v_pins: i2c2m05v-pins { +- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, +- <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- i2c3 { +- i2c3_xfer: i2c3-xfer { +- rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>, +- <0 RK_PC4 2 &pcfg_pull_none>; +- }; +- }; +- +- pwm0 { +- pwm0_pin: pwm0-pin { +- rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm1 { +- pwm1_pin: pwm1-pin { +- rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm2 { +- pwm2_pin: pwm2-pin { +- rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm3 { +- pwm3_pin: pwm3-pin { +- rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm4 { +- pwm4_pin: pwm4-pin { +- rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>; +- }; +- }; +- +- pwm5 { +- pwm5_pin: pwm5-pin { +- rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>; +- }; +- }; +- +- pwm6 { +- pwm6_pin: pwm6-pin { +- rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; +- }; +- }; +- +- pwm7 { +- pwm7_pin: pwm7-pin { +- rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>; +- }; +- }; +- +- sdmmc { +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>; +- }; +- +- sdmmc_cd: sdmmc-cd { +- rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>; +- }; +- +- sdmmc_bus1: sdmmc-bus1 { +- rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>; +- }; +- +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>, +- <3 RK_PC2 1 &pcfg_pull_up_drv_4ma>, +- <3 RK_PC1 1 &pcfg_pull_up_drv_4ma>, +- <3 RK_PC0 1 &pcfg_pull_up_drv_4ma>; +- }; +- }; +- +- spim0 { +- spim0_clk: spim0-clk { +- rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>; +- }; +- +- spim0_cs0: spim0-cs0 { +- rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>; +- }; +- +- spim0_tx: spim0-tx { +- rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>; +- }; +- +- spim0_rx: spim0-rx { +- rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>; +- }; +- }; +- +- spim1 { +- spim1_clk: spim1-clk { +- rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; +- }; +- +- spim1_cs0: spim1-cs0 { +- rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>; +- }; +- +- spim1_rx: spim1-rx { +- rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>; +- }; +- +- spim1_tx: spim1-tx { +- rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>; +- }; +- }; +- +- tsadc { +- otp_out: otp-out { +- rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; +- }; +- +- otp_pin: otp-pin { +- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- uart0 { +- uart0_xfer: uart0-xfer { +- rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>, +- <3 RK_PA5 1 &pcfg_pull_none>; +- }; +- +- uart0_cts: uart0-cts { +- rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; +- }; +- +- uart0_rts: uart0-rts { +- rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; +- }; +- +- uart0_rts_pin: uart0-rts-pin { +- rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- uart1 { +- uart1_xfer: uart1-xfer { +- rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>, +- <1 RK_PD2 1 &pcfg_pull_none>; +- }; +- +- uart1_cts: uart1-cts { +- rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; +- }; +- +- uart1_rts: uart1-rts { +- rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; +- }; +- }; +- +- uart2m0 { +- uart2m0_xfer: uart2m0-xfer { +- rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>, +- <2 RK_PD1 1 &pcfg_pull_none>; +- }; +- }; +- +- uart2m1 { +- uart2m1_xfer: uart2m1-xfer { +- rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>, +- <3 RK_PC2 2 &pcfg_pull_none>; +- }; +- }; +- +- uart2_5v { +- uart2_5v_cts: uart2_5v-cts { +- rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>; +- }; +- +- uart2_5v_rts: uart2_5v-rts { +- rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/s3c2416-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/s3c2416-pinctrl.dtsi +deleted file mode 100644 +index 92439ee5d7de..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s3c2416-pinctrl.dtsi ++++ /dev/null +@@ -1,172 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung S3C2416 pinctrl settings +- * +- * Copyright (c) 2013 Heiko Stuebner +- */ +- +-#include +- +-&pinctrl_0 { +- /* +- * Pin banks +- */ +- +- gpa: gpa { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpb: gpb { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpc: gpc { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpd: gpd { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpe: gpe { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpf: gpf { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg: gpg { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gph: gph { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpj: gpj { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpk: gpk { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpl: gpl { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpm: gpm { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- /* +- * Pin groups +- */ +- +- uart0_data: uart0-data { +- samsung,pins = "gph-0", "gph-1"; +- samsung,pin-function = ; +- }; +- +- uart0_fctl: uart0-fctl { +- samsung,pins = "gph-8", "gph-9"; +- samsung,pin-function = ; +- }; +- +- uart1_data: uart1-data { +- samsung,pins = "gph-2", "gph-3"; +- samsung,pin-function = ; +- }; +- +- uart1_fctl: uart1-fctl { +- samsung,pins = "gph-10", "gph-11"; +- samsung,pin-function = ; +- }; +- +- uart2_data: uart2-data { +- samsung,pins = "gph-4", "gph-5"; +- samsung,pin-function = ; +- }; +- +- uart2_fctl: uart2-fctl { +- samsung,pins = "gph-6", "gph-7"; +- samsung,pin-function = ; +- }; +- +- uart3_data: uart3-data { +- samsung,pins = "gph-6", "gph-7"; +- samsung,pin-function = ; +- }; +- +- extuart_clk: extuart-clk { +- samsung,pins = "gph-12"; +- samsung,pin-function = ; +- }; +- +- i2c0_bus: i2c0-bus { +- samsung,pins = "gpe-14", "gpe-15"; +- samsung,pin-function = ; +- }; +- +- spi0_bus: spi0-bus { +- samsung,pins = "gpe-11", "gpe-12", "gpe-13"; +- samsung,pin-function = ; +- }; +- +- sd0_clk: sd0-clk { +- samsung,pins = "gpe-5"; +- samsung,pin-function = ; +- }; +- +- sd0_cmd: sd0-cmd { +- samsung,pins = "gpe-6"; +- samsung,pin-function = ; +- }; +- +- sd0_bus1: sd0-bus1 { +- samsung,pins = "gpe-7"; +- samsung,pin-function = ; +- }; +- +- sd0_bus4: sd0-bus4 { +- samsung,pins = "gpe-8", "gpe-9", "gpe-10"; +- samsung,pin-function = ; +- }; +- +- sd1_cmd: sd1-cmd { +- samsung,pins = "gpl-8"; +- samsung,pin-function = ; +- }; +- +- sd1_clk: sd1-clk { +- samsung,pins = "gpl-9"; +- samsung,pin-function = ; +- }; +- +- sd1_bus1: sd1-bus1 { +- samsung,pins = "gpl-0"; +- samsung,pin-function = ; +- }; +- +- sd1_bus4: sd1-bus4 { +- samsung,pins = "gpl-1", "gpl-2", "gpl-3"; +- samsung,pin-function = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/s3c2416-smdk2416.dts b/scripts/dtc/include-prefixes/arm/s3c2416-smdk2416.dts +deleted file mode 100644 +index e7c379a9842e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s3c2416-smdk2416.dts ++++ /dev/null +@@ -1,77 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung SMDK2416 board device tree source +- * +- * Copyright (c) 2013 Heiko Stuebner +- */ +- +-/dts-v1/; +-#include "s3c2416.dtsi" +- +-/ { +- model = "SMDK2416"; +- compatible = "samsung,smdk2416", "samsung,s3c2416"; +- +- memory@30000000 { +- device_type = "memory"; +- reg = <0x30000000 0x4000000>; +- }; +- +- xti: clock-0 { +- compatible = "fixed-clock"; +- clock-frequency = <12000000>; +- clock-output-names = "xti"; +- #clock-cells = <0>; +- }; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&sdhci_0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, +- <&sd1_bus1>, <&sd1_bus4>; +- bus-width = <4>; +- broken-cd; +- status = "okay"; +-}; +- +-&sdhci_1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, +- <&sd0_bus1>, <&sd0_bus4>; +- bus-width = <4>; +- cd-gpios = <&gpf 1 0>; +- cd-inverted; +- status = "okay"; +-}; +- +-&uart_0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_data>, <&uart0_fctl>; +-}; +- +-&uart_1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_data>, <&uart1_fctl>; +-}; +- +-&uart_2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_data>; +-}; +- +-&uart_3 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_data>; +-}; +- +-&watchdog { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/s3c2416.dtsi b/scripts/dtc/include-prefixes/arm/s3c2416.dtsi +deleted file mode 100644 +index 4f084f4fe44f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s3c2416.dtsi ++++ /dev/null +@@ -1,124 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's S3C2416 SoC device tree source +- * +- * Copyright (c) 2013 Heiko Stuebner +- */ +- +-#include +-#include "s3c24xx.dtsi" +-#include "s3c2416-pinctrl.dtsi" +- +-/ { +- model = "Samsung S3C2416 SoC"; +- compatible = "samsung,s3c2416"; +- +- aliases { +- serial3 = &uart_3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,arm926ej-s"; +- reg = <0x0>; +- }; +- }; +- +- clocks: clock-controller@4c000000 { +- compatible = "samsung,s3c2416-clock"; +- reg = <0x4c000000 0x40>; +- #clock-cells = <1>; +- }; +- +- uart_3: serial@5000c000 { +- compatible = "samsung,s3c2440-uart"; +- reg = <0x5000C000 0x4000>; +- interrupts = <1 18 24 4>, <1 18 25 4>; +- clock-names = "uart", "clk_uart_baud2", +- "clk_uart_baud3"; +- clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>, +- <&clocks SCLK_UART>; +- status = "disabled"; +- }; +- +- sdhci_1: sdhci@4ac00000 { +- compatible = "samsung,s3c6410-sdhci"; +- reg = <0x4AC00000 0x100>; +- interrupts = <0 0 21 3>; +- clock-names = "hsmmc", "mmc_busclk.0", +- "mmc_busclk.2"; +- clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>, +- <&clocks MUX_HSMMC0>; +- status = "disabled"; +- }; +- +- sdhci_0: sdhci@4a800000 { +- compatible = "samsung,s3c6410-sdhci"; +- reg = <0x4A800000 0x100>; +- interrupts = <0 0 20 3>; +- clock-names = "hsmmc", "mmc_busclk.0", +- "mmc_busclk.2"; +- clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>, +- <&clocks MUX_HSMMC1>; +- status = "disabled"; +- }; +-}; +- +-&i2c { +- compatible = "samsung,s3c2440-i2c"; +- clocks = <&clocks PCLK_I2C0>; +- clock-names = "i2c"; +-}; +- +-&intc { +- compatible = "samsung,s3c2416-irq"; +-}; +- +-&pinctrl_0 { +- compatible = "samsung,s3c2416-pinctrl"; +-}; +- +-&rtc { +- compatible = "samsung,s3c2416-rtc"; +- clocks = <&clocks PCLK_RTC>; +- clock-names = "rtc"; +-}; +- +-&timer { +- clocks = <&clocks PCLK_PWM>; +- clock-names = "timers"; +-}; +- +-&uart_0 { +- compatible = "samsung,s3c2440-uart"; +- clock-names = "uart", "clk_uart_baud2", +- "clk_uart_baud3"; +- clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, +- <&clocks SCLK_UART>; +-}; +- +-&uart_1 { +- compatible = "samsung,s3c2440-uart"; +- clock-names = "uart", "clk_uart_baud2", +- "clk_uart_baud3"; +- clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, +- <&clocks SCLK_UART>; +-}; +- +-&uart_2 { +- compatible = "samsung,s3c2440-uart"; +- clock-names = "uart", "clk_uart_baud2", +- "clk_uart_baud3"; +- clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, +- <&clocks SCLK_UART>; +-}; +- +-&watchdog { +- interrupts = <1 9 27 3>; +- clocks = <&clocks PCLK_WDT>; +- clock-names = "watchdog"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/s3c24xx.dtsi b/scripts/dtc/include-prefixes/arm/s3c24xx.dtsi +deleted file mode 100644 +index 06f82c7e458e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s3c24xx.dtsi ++++ /dev/null +@@ -1,92 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's S3C24XX family device tree source +- * +- * Copyright (c) 2013 Heiko Stuebner +- */ +- +-/ { +- compatible = "samsung,s3c24xx"; +- interrupt-parent = <&intc>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- pinctrl0 = &pinctrl_0; +- serial0 = &uart_0; +- serial1 = &uart_1; +- serial2 = &uart_2; +- }; +- +- intc: interrupt-controller@4a000000 { +- compatible = "samsung,s3c2410-irq"; +- reg = <0x4a000000 0x100>; +- interrupt-controller; +- #interrupt-cells = <4>; +- }; +- +- pinctrl_0: pinctrl@56000000 { +- reg = <0x56000000 0x1000>; +- +- wakeup-interrupt-controller { +- compatible = "samsung,s3c2410-wakeup-eint"; +- interrupts = <0 0 0 3>, +- <0 0 1 3>, +- <0 0 2 3>, +- <0 0 3 3>, +- <0 0 4 4>, +- <0 0 5 4>; +- }; +- }; +- +- timer: pwm@51000000 { +- compatible = "samsung,s3c2410-pwm"; +- reg = <0x51000000 0x1000>; +- interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>; +- #pwm-cells = <3>; +- }; +- +- uart_0: serial@50000000 { +- compatible = "samsung,s3c2410-uart"; +- reg = <0x50000000 0x4000>; +- interrupts = <1 28 0 4>, <1 28 1 4>; +- status = "disabled"; +- }; +- +- uart_1: serial@50004000 { +- compatible = "samsung,s3c2410-uart"; +- reg = <0x50004000 0x4000>; +- interrupts = <1 23 3 4>, <1 23 4 4>; +- status = "disabled"; +- }; +- +- uart_2: serial@50008000 { +- compatible = "samsung,s3c2410-uart"; +- reg = <0x50008000 0x4000>; +- interrupts = <1 15 6 4>, <1 15 7 4>; +- status = "disabled"; +- }; +- +- watchdog: watchdog@53000000 { +- compatible = "samsung,s3c2410-wdt"; +- reg = <0x53000000 0x100>; +- interrupts = <0 0 9 3>; +- status = "disabled"; +- }; +- +- rtc: rtc@57000000 { +- compatible = "samsung,s3c2410-rtc"; +- reg = <0x57000000 0x100>; +- interrupts = <0 0 30 3>, <0 0 8 3>; +- status = "disabled"; +- }; +- +- i2c: i2c@54000000 { +- compatible = "samsung,s3c2410-i2c"; +- reg = <0x54000000 0x100>; +- interrupts = <0 0 27 3>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/s3c6400.dtsi b/scripts/dtc/include-prefixes/arm/s3c6400.dtsi +deleted file mode 100644 +index 8c28e8a0c824..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s3c6400.dtsi ++++ /dev/null +@@ -1,38 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's S3C6400 SoC device tree source +- * +- * Copyright (c) 2013 Tomasz Figa +- * +- * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400 +- * based board files can include this file and provide values for board specfic +- * bindings. +- * +- * Note: This file does not include device nodes for all the controllers in +- * S3C6400 SoC. As device tree coverage for S3C6400 increases, additional +- * nodes can be added to this file. +- */ +- +-#include "s3c64xx.dtsi" +- +-/ { +- compatible = "samsung,s3c6400"; +-}; +- +-&vic0 { +- valid-mask = <0xfffffe1f>; +- valid-wakeup-mask = <0x00200004>; +-}; +- +-&vic1 { +- valid-mask = <0xffffffff>; +- valid-wakeup-mask = <0x53020000>; +-}; +- +-&soc { +- clocks: clock-controller@7e00f000 { +- compatible = "samsung,s3c6400-clock"; +- reg = <0x7e00f000 0x1000>; +- #clock-cells = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/s3c6410-mini6410.dts b/scripts/dtc/include-prefixes/arm/s3c6410-mini6410.dts +deleted file mode 100644 +index 285555b9ed94..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s3c6410-mini6410.dts ++++ /dev/null +@@ -1,218 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's S3C6410 based Mini6410 board device tree source +- * +- * Copyright (c) 2013 Tomasz Figa +- * +- * Device tree source file for FriendlyARM Mini6410 board which is based on +- * Samsung's S3C6410 SoC. +- */ +- +-/dts-v1/; +- +-#include +-#include +- +-#include "s3c6410.dtsi" +- +-/ { +- model = "FriendlyARM Mini6410 board based on S3C6410"; +- compatible = "friendlyarm,mini6410", "samsung,s3c6410"; +- +- memory@50000000 { +- device_type = "memory"; +- reg = <0x50000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; +- }; +- +- fin_pll: oscillator-0 { +- compatible = "fixed-clock"; +- clock-frequency = <12000000>; +- clock-output-names = "fin_pll"; +- #clock-cells = <0>; +- }; +- +- xusbxti: oscillator-1 { +- compatible = "fixed-clock"; +- clock-output-names = "xusbxti"; +- clock-frequency = <48000000>; +- #clock-cells = <0>; +- }; +- +- srom-cs1-bus@18000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x18000000 0x8000000>; +- ranges; +- +- ethernet@18000000 { +- compatible = "davicom,dm9000"; +- reg = <0x18000000 0x2 0x18000004 0x2>; +- interrupt-parent = <&gpn>; +- interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; +- davicom,no-eeprom; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys>; +- autorepeat; +- +- button-k1 { +- label = "K1"; +- gpios = <&gpn 0 GPIO_ACTIVE_LOW>; +- linux,code = <2>; +- debounce-interval = <20>; +- }; +- +- button-k2 { +- label = "K2"; +- gpios = <&gpn 1 GPIO_ACTIVE_LOW>; +- linux,code = <3>; +- debounce-interval = <20>; +- }; +- +- button-k3 { +- label = "K3"; +- gpios = <&gpn 2 GPIO_ACTIVE_LOW>; +- linux,code = <4>; +- debounce-interval = <20>; +- }; +- +- button-k4 { +- label = "K4"; +- gpios = <&gpn 3 GPIO_ACTIVE_LOW>; +- linux,code = <5>; +- debounce-interval = <20>; +- }; +- +- button-k5 { +- label = "K5"; +- gpios = <&gpn 4 GPIO_ACTIVE_LOW>; +- linux,code = <6>; +- debounce-interval = <20>; +- }; +- +- button-k6 { +- label = "K6"; +- gpios = <&gpn 5 GPIO_ACTIVE_LOW>; +- linux,code = <7>; +- debounce-interval = <20>; +- }; +- +- button-k7 { +- label = "K7"; +- gpios = <&gpl 11 GPIO_ACTIVE_LOW>; +- linux,code = <8>; +- debounce-interval = <20>; +- }; +- +- button-k8 { +- label = "K8"; +- gpios = <&gpl 12 GPIO_ACTIVE_LOW>; +- linux,code = <9>; +- debounce-interval = <20>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_leds>; +- +- led-1 { +- label = "LED1"; +- gpios = <&gpk 4 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-2 { +- label = "LED2"; +- gpios = <&gpk 5 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "mmc0"; +- }; +- +- led-3 { +- label = "LED3"; +- gpios = <&gpk 6 GPIO_ACTIVE_LOW>; +- }; +- +- led-4 { +- label = "LED4"; +- gpios = <&gpk 7 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- buzzer { +- compatible = "pwm-beeper"; +- pwms = <&pwm 0 1000000 0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_out>; +- }; +-}; +- +-&clocks { +- clocks = <&fin_pll>; +-}; +- +-&sdhci0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_data>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_data>, <&uart1_fctl>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_data>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_data>; +- status = "okay"; +-}; +- +-&pinctrl0 { +- gpio_leds: gpio-leds { +- samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7"; +- samsung,pin-pud = ; +- }; +- +- gpio_keys: gpio-keys { +- samsung,pins = "gpn-0", "gpn-1", "gpn-2", "gpn-3", +- "gpn-4", "gpn-5", "gpl-11", "gpl-12"; +- samsung,pin-pud = ; +- }; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_bus>; +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c08"; +- reg = <0x50>; +- pagesize = <16>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/s3c6410-smdk6410.dts b/scripts/dtc/include-prefixes/arm/s3c6410-smdk6410.dts +deleted file mode 100644 +index 581309e7f15e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s3c6410-smdk6410.dts ++++ /dev/null +@@ -1,97 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung S3C6410 based SMDK6410 board device tree source. +- * +- * Copyright (c) 2013 Tomasz Figa +- * +- * Device tree source file for Samsung SMDK6410 board which is based on +- * Samsung's S3C6410 SoC. +- */ +- +-/dts-v1/; +- +-#include +-#include +- +-#include "s3c6410.dtsi" +- +-/ { +- model = "Samsung SMDK6410 board based on S3C6410"; +- compatible = "samsung,smdk6410", "samsung,s3c6410"; +- +- memory@50000000 { +- device_type = "memory"; +- reg = <0x50000000 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; +- }; +- +- fin_pll: oscillator-0 { +- compatible = "fixed-clock"; +- clock-frequency = <12000000>; +- clock-output-names = "fin_pll"; +- #clock-cells = <0>; +- }; +- +- xusbxti: oscillator-1 { +- compatible = "fixed-clock"; +- clock-output-names = "xusbxti"; +- clock-frequency = <48000000>; +- #clock-cells = <0>; +- }; +- +- srom-cs1-bus@18000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x18000000 0x8000000>; +- ranges; +- +- ethernet@18000000 { +- compatible = "smsc,lan9115"; +- reg = <0x18000000 0x10000>; +- interrupt-parent = <&gpn>; +- interrupts = <10 IRQ_TYPE_LEVEL_LOW>; +- phy-mode = "mii"; +- reg-io-width = <4>; +- smsc,force-internal-phy; +- }; +- }; +-}; +- +-&clocks { +- clocks = <&fin_pll>; +-}; +- +-&sdhci0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_data>, <&uart0_fctl>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_data>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_data>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_data>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/s3c6410.dtsi b/scripts/dtc/include-prefixes/arm/s3c6410.dtsi +deleted file mode 100644 +index a766d6de696c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s3c6410.dtsi ++++ /dev/null +@@ -1,54 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's S3C6410 SoC device tree source +- * +- * Copyright (c) 2013 Tomasz Figa +- * +- * Samsung's S3C6410 SoC device nodes are listed in this file. S3C6410 +- * based board files can include this file and provide values for board specfic +- * bindings. +- * +- * Note: This file does not include device nodes for all the controllers in +- * S3C6410 SoC. As device tree coverage for S3C6410 increases, additional +- * nodes can be added to this file. +- */ +- +-#include "s3c64xx.dtsi" +- +-/ { +- compatible = "samsung,s3c6410"; +- +- aliases { +- i2c1 = &i2c1; +- }; +-}; +- +-&vic0 { +- valid-mask = <0xffffff7f>; +- valid-wakeup-mask = <0x00200004>; +-}; +- +-&vic1 { +- valid-mask = <0xffffffff>; +- valid-wakeup-mask = <0x53020000>; +-}; +- +-&soc { +- clocks: clock-controller@7e00f000 { +- compatible = "samsung,s3c6410-clock"; +- reg = <0x7e00f000 0x1000>; +- #clock-cells = <1>; +- }; +- +- i2c1: i2c@7f00f000 { +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x7f00f000 0x1000>; +- interrupt-parent = <&vic0>; +- interrupts = <5>; +- clock-names = "i2c"; +- clocks = <&clocks PCLK_IIC1>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/s3c64xx-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/s3c64xx-pinctrl.dtsi +deleted file mode 100644 +index 8e9594d64b57..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s3c64xx-pinctrl.dtsi ++++ /dev/null +@@ -1,682 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's S3C64xx SoC series common device tree source +- * - pin control-related definitions +- * +- * Copyright (c) 2013 Tomasz Figa +- * +- * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are +- * listed as device tree nodes in this file. +- */ +- +-#include +- +-&pinctrl0 { +- /* +- * Pin banks +- */ +- +- gpa: gpa { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb: gpb { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc: gpc { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd: gpd { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpe: gpe { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpf: gpf { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg: gpg { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gph: gph { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpi: gpi { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpj: gpj { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpk: gpk { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpl: gpl { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpm: gpm { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpn: gpn { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpo: gpo { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpp: gpp { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpq: gpq { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- /* +- * Pin groups +- */ +- +- uart0_data: uart0-data { +- samsung,pins = "gpa-0", "gpa-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- uart0_fctl: uart0-fctl { +- samsung,pins = "gpa-2", "gpa-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- uart1_data: uart1-data { +- samsung,pins = "gpa-4", "gpa-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- uart1_fctl: uart1-fctl { +- samsung,pins = "gpa-6", "gpa-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- uart2_data: uart2-data { +- samsung,pins = "gpb-0", "gpb-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- uart3_data: uart3-data { +- samsung,pins = "gpb-2", "gpb-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- ext_dma_0: ext-dma-0 { +- samsung,pins = "gpb-0", "gpb-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- ext_dma_1: ext-dma-1 { +- samsung,pins = "gpb-2", "gpb-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- irda_data_0: irda-data-0 { +- samsung,pins = "gpb-0", "gpb-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- irda_data_1: irda-data-1 { +- samsung,pins = "gpb-2", "gpb-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- irda_sdbw: irda-sdbw { +- samsung,pins = "gpb-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- i2c0_bus: i2c0-bus { +- samsung,pins = "gpb-5", "gpb-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- i2c1_bus: i2c1-bus { +- /* S3C6410-only */ +- samsung,pins = "gpb-2", "gpb-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- spi0_bus: spi0-bus { +- samsung,pins = "gpc-0", "gpc-1", "gpc-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- spi0_cs: spi0-cs { +- samsung,pins = "gpc-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- spi1_bus: spi1-bus { +- samsung,pins = "gpc-4", "gpc-5", "gpc-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- spi1_cs: spi1-cs { +- samsung,pins = "gpc-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- sd0_cmd: sd0-cmd { +- samsung,pins = "gpg-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- sd0_clk: sd0-clk { +- samsung,pins = "gpg-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- sd0_bus1: sd0-bus1 { +- samsung,pins = "gpg-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- sd0_bus4: sd0-bus4 { +- samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- sd0_cd: sd0-cd { +- samsung,pins = "gpg-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- sd1_cmd: sd1-cmd { +- samsung,pins = "gph-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- sd1_clk: sd1-clk { +- samsung,pins = "gph-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- sd1_bus1: sd1-bus1 { +- samsung,pins = "gph-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- sd1_bus4: sd1-bus4 { +- samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- sd1_bus8: sd1-bus8 { +- samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5", +- "gph-6", "gph-7", "gph-8", "gph-9"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- sd1_cd: sd1-cd { +- samsung,pins = "gpg-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- sd2_cmd: sd2-cmd { +- samsung,pins = "gpc-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- sd2_clk: sd2-clk { +- samsung,pins = "gpc-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- sd2_bus1: sd2-bus1 { +- samsung,pins = "gph-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- sd2_bus4: sd2-bus4 { +- samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- i2s0_bus: i2s0-bus { +- samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- i2s0_cdclk: i2s0-cdclk { +- samsung,pins = "gpd-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- i2s1_bus: i2s1-bus { +- samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- i2s1_cdclk: i2s1-cdclk { +- samsung,pins = "gpe-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- i2s2_bus: i2s2-bus { +- /* S3C6410-only */ +- samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6", +- "gph-8", "gph-9"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- i2s2_cdclk: i2s2-cdclk { +- /* S3C6410-only */ +- samsung,pins = "gph-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- pcm0_bus: pcm0-bus { +- samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- pcm0_extclk: pcm0-extclk { +- samsung,pins = "gpd-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- pcm1_bus: pcm1-bus { +- samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- pcm1_extclk: pcm1-extclk { +- samsung,pins = "gpe-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- ac97_bus_0: ac97-bus-0 { +- samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- ac97_bus_1: ac97-bus-1 { +- samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- cam_port: cam-port { +- samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4", +- "gpf-5", "gpf-6", "gpf-7", "gpf-8", +- "gpf-9", "gpf-10", "gpf-11", "gpf-12"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- cam_rst: cam-rst { +- samsung,pins = "gpf-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- cam_field: cam-field { +- /* S3C6410-only */ +- samsung,pins = "gpb-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- pwm_extclk: pwm-extclk { +- samsung,pins = "gpf-13"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- pwm0_out: pwm0-out { +- samsung,pins = "gpf-14"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- pwm1_out: pwm1-out { +- samsung,pins = "gpf-15"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- clkout0: clkout-0 { +- samsung,pins = "gpf-14"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_col0_0: keypad-col0-0 { +- samsung,pins = "gph-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_col1_0: keypad-col1-0 { +- samsung,pins = "gph-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_col2_0: keypad-col2-0 { +- samsung,pins = "gph-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_col3_0: keypad-col3-0 { +- samsung,pins = "gph-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_col4_0: keypad-col4-0 { +- samsung,pins = "gph-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_col5_0: keypad-col5-0 { +- samsung,pins = "gph-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_col6_0: keypad-col6-0 { +- samsung,pins = "gph-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_col7_0: keypad-col7-0 { +- samsung,pins = "gph-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_col0_1: keypad-col0-1 { +- samsung,pins = "gpl-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_col1_1: keypad-col1-1 { +- samsung,pins = "gpl-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_col2_1: keypad-col2-1 { +- samsung,pins = "gpl-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_col3_1: keypad-col3-1 { +- samsung,pins = "gpl-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_col4_1: keypad-col4-1 { +- samsung,pins = "gpl-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_col5_1: keypad-col5-1 { +- samsung,pins = "gpl-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_col6_1: keypad-col6-1 { +- samsung,pins = "gpl-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_col7_1: keypad-col7-1 { +- samsung,pins = "gpl-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_row0_0: keypad-row0-0 { +- samsung,pins = "gpk-8"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_row1_0: keypad-row1-0 { +- samsung,pins = "gpk-9"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_row2_0: keypad-row2-0 { +- samsung,pins = "gpk-10"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_row3_0: keypad-row3-0 { +- samsung,pins = "gpk-11"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_row4_0: keypad-row4-0 { +- samsung,pins = "gpk-12"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_row5_0: keypad-row5-0 { +- samsung,pins = "gpk-13"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_row6_0: keypad-row6-0 { +- samsung,pins = "gpk-14"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_row7_0: keypad-row7-0 { +- samsung,pins = "gpk-15"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_row0_1: keypad-row0-1 { +- samsung,pins = "gpn-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_row1_1: keypad-row1-1 { +- samsung,pins = "gpn-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_row2_1: keypad-row2-1 { +- samsung,pins = "gpn-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_row3_1: keypad-row3-1 { +- samsung,pins = "gpn-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_row4_1: keypad-row4-1 { +- samsung,pins = "gpn-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_row5_1: keypad-row5-1 { +- samsung,pins = "gpn-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_row6_1: keypad-row6-1 { +- samsung,pins = "gpn-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- keypad_row7_1: keypad-row7-1 { +- samsung,pins = "gpn-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- lcd_ctrl: lcd-ctrl { +- samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- lcd_data16: lcd-data-width16 { +- samsung,pins = "gpi-3", "gpi-4", "gpi-5", "gpi-6", +- "gpi-7", "gpi-10", "gpi-11", "gpi-12", +- "gpi-13", "gpi-14", "gpi-15", "gpj-3", +- "gpj-4", "gpj-5", "gpj-6", "gpj-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- lcd_data18: lcd-data-width18 { +- samsung,pins = "gpi-2", "gpi-3", "gpi-4", "gpi-5", +- "gpi-6", "gpi-7", "gpi-10", "gpi-11", +- "gpi-12", "gpi-13", "gpi-14", "gpi-15", +- "gpj-2", "gpj-3", "gpj-4", "gpj-5", +- "gpj-6", "gpj-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- lcd_data24: lcd-data-width24 { +- samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", +- "gpi-4", "gpi-5", "gpi-6", "gpi-7", +- "gpi-8", "gpi-9", "gpi-10", "gpi-11", +- "gpi-12", "gpi-13", "gpi-14", "gpi-15", +- "gpj-0", "gpj-1", "gpj-2", "gpj-3", +- "gpj-4", "gpj-5", "gpj-6", "gpj-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- hsi_bus: hsi-bus { +- samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3", +- "gpk-4", "gpk-5", "gpk-6", "gpk-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/s3c64xx.dtsi b/scripts/dtc/include-prefixes/arm/s3c64xx.dtsi +deleted file mode 100644 +index cb11a87dbc42..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s3c64xx.dtsi ++++ /dev/null +@@ -1,200 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's S3C64xx SoC series common device tree source +- * +- * Copyright (c) 2013 Tomasz Figa +- * +- * Samsung's S3C64xx SoC series device nodes are listed in this file. +- * Particular SoCs from S3C64xx series can include this file and provide +- * values for SoCs specfic bindings. +- * +- * Note: This file does not include device nodes for all the controllers in +- * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional +- * nodes can be added to this file. +- */ +- +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- i2c0 = &i2c0; +- pinctrl0 = &pinctrl0; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,arm1176jzf-s"; +- reg = <0x0>; +- }; +- }; +- +- soc: soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- vic0: interrupt-controller@71200000 { +- compatible = "arm,pl192-vic"; +- interrupt-controller; +- reg = <0x71200000 0x1000>; +- #interrupt-cells = <1>; +- }; +- +- vic1: interrupt-controller@71300000 { +- compatible = "arm,pl192-vic"; +- interrupt-controller; +- reg = <0x71300000 0x1000>; +- #interrupt-cells = <1>; +- }; +- +- sdhci0: sdhci@7c200000 { +- compatible = "samsung,s3c6410-sdhci"; +- reg = <0x7c200000 0x100>; +- interrupt-parent = <&vic1>; +- interrupts = <24>; +- clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; +- clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>, +- <&clocks SCLK_MMC0>; +- status = "disabled"; +- }; +- +- sdhci1: sdhci@7c300000 { +- compatible = "samsung,s3c6410-sdhci"; +- reg = <0x7c300000 0x100>; +- interrupt-parent = <&vic1>; +- interrupts = <25>; +- clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; +- clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>, +- <&clocks SCLK_MMC1>; +- status = "disabled"; +- }; +- +- sdhci2: sdhci@7c400000 { +- compatible = "samsung,s3c6410-sdhci"; +- reg = <0x7c400000 0x100>; +- interrupt-parent = <&vic1>; +- interrupts = <17>; +- clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; +- clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>, +- <&clocks SCLK_MMC2>; +- status = "disabled"; +- }; +- +- watchdog: watchdog@7e004000 { +- compatible = "samsung,s3c6410-wdt"; +- reg = <0x7e004000 0x1000>; +- interrupt-parent = <&vic0>; +- interrupts = <26>; +- clock-names = "watchdog"; +- clocks = <&clocks PCLK_WDT>; +- }; +- +- i2c0: i2c@7f004000 { +- compatible = "samsung,s3c2440-i2c"; +- reg = <0x7f004000 0x1000>; +- interrupt-parent = <&vic1>; +- interrupts = <18>; +- clock-names = "i2c"; +- clocks = <&clocks PCLK_IIC0>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- uart0: serial@7f005000 { +- compatible = "samsung,s3c6400-uart"; +- reg = <0x7f005000 0x100>; +- interrupt-parent = <&vic1>; +- interrupts = <5>; +- clock-names = "uart", "clk_uart_baud2", +- "clk_uart_baud3"; +- clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, +- <&clocks SCLK_UART>; +- status = "disabled"; +- }; +- +- uart1: serial@7f005400 { +- compatible = "samsung,s3c6400-uart"; +- reg = <0x7f005400 0x100>; +- interrupt-parent = <&vic1>; +- interrupts = <6>; +- clock-names = "uart", "clk_uart_baud2", +- "clk_uart_baud3"; +- clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, +- <&clocks SCLK_UART>; +- status = "disabled"; +- }; +- +- uart2: serial@7f005800 { +- compatible = "samsung,s3c6400-uart"; +- reg = <0x7f005800 0x100>; +- interrupt-parent = <&vic1>; +- interrupts = <7>; +- clock-names = "uart", "clk_uart_baud2", +- "clk_uart_baud3"; +- clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, +- <&clocks SCLK_UART>; +- status = "disabled"; +- }; +- +- uart3: serial@7f005c00 { +- compatible = "samsung,s3c6400-uart"; +- reg = <0x7f005c00 0x100>; +- interrupt-parent = <&vic1>; +- interrupts = <8>; +- clock-names = "uart", "clk_uart_baud2", +- "clk_uart_baud3"; +- clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>, +- <&clocks SCLK_UART>; +- status = "disabled"; +- }; +- +- pwm: pwm@7f006000 { +- compatible = "samsung,s3c6400-pwm"; +- reg = <0x7f006000 0x1000>; +- interrupt-parent = <&vic0>; +- interrupts = <23>, <24>, <25>, <27>, <28>; +- clock-names = "timers"; +- clocks = <&clocks PCLK_PWM>; +- samsung,pwm-outputs = <0>, <1>; +- #pwm-cells = <3>; +- }; +- +- pinctrl0: pinctrl@7f008000 { +- compatible = "samsung,s3c64xx-pinctrl"; +- reg = <0x7f008000 0x1000>; +- interrupt-parent = <&vic1>; +- interrupts = <21>; +- +- pctrl_int_map: pinctrl-interrupt-map { +- interrupt-map = <0 &vic0 0>, +- <1 &vic0 1>, +- <2 &vic1 0>, +- <3 &vic1 1>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <1>; +- }; +- +- wakeup-interrupt-controller { +- compatible = "samsung,s3c64xx-wakeup-eint"; +- interrupts = <0>, <1>, <2>, <3>; +- interrupt-parent = <&pctrl_int_map>; +- }; +- }; +- }; +-}; +- +-#include "s3c64xx-pinctrl.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/s5pv210-aquila.dts b/scripts/dtc/include-prefixes/arm/s5pv210-aquila.dts +deleted file mode 100644 +index 6423348034b6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s5pv210-aquila.dts ++++ /dev/null +@@ -1,399 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's S5PV210 SoC device tree source +- * +- * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. +- * +- * Mateusz Krawczuk +- * Tomasz Figa +- * +- * Board device tree source for Samsung Aquila board. +- */ +- +-/dts-v1/; +-#include +-#include +-#include "s5pv210.dtsi" +- +-/ { +- model = "Samsung Aquila based on S5PC110"; +- compatible = "samsung,aquila", "samsung,s5pv210"; +- +- aliases { +- i2c3 = &i2c_pmic; +- }; +- +- chosen { +- bootargs = "console=ttySAC2,115200n8 root=/dev/mmcblk1p5 rw rootwait ignore_loglevel earlyprintk"; +- }; +- +- memory@30000000 { +- device_type = "memory"; +- reg = <0x30000000 0x05000000 +- 0x40000000 0x18000000>; +- }; +- +- pmic_ap_clk: clock-0 { +- /* Workaround for missing clock on PMIC */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- vtf_reg: regulator-0 { +- compatible = "regulator-fixed"; +- regulator-name = "V_TF_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&mp05 4 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- pda_reg: regulator-1 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_1.8V_PDA"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- bat_reg: regulator-2 { +- compatible = "regulator-fixed"; +- regulator-name = "V_BAT"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- }; +- +- i2c_pmic: i2c-pmic { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpj4 0 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&gpj4 3 GPIO_ACTIVE_HIGH>; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- +- pmic@66 { +- compatible = "national,lp3974"; +- reg = <0x66>; +- +- max8998,pmic-buck1-default-dvs-idx = <0>; +- max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>, +- <&gph0 4 GPIO_ACTIVE_HIGH>; +- max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>, +- <1200000>, <1200000>; +- +- max8998,pmic-buck2-default-dvs-idx = <0>; +- max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; +- max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>; +- +- regulators { +- ldo2_reg: LDO2 { +- regulator-name = "VALIVE_1.1V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "VUSB+MIPI_1.1V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "VADC_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "VTF_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "VCC_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "VCC_3.0V"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "VUSB+VDAC_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "VCC+VCAM_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "VPLL_1.1V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "CAM_IO_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "CAM_ISP_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "CAM_A_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "CAM_CIF_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "CAM_AF_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "VMIPI_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "CAM_8M_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "VARM_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "VINT_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "VCC_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "CAM_CORE_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ap32khz_reg: EN32KHz-AP { +- regulator-name = "32KHz AP"; +- regulator-always-on; +- }; +- +- vichg_reg: ENVICHG { +- regulator-name = "VICHG"; +- }; +- +- safeout1_reg: ESAFEOUT1 { +- regulator-name = "SAFEOUT1"; +- regulator-always-on; +- }; +- +- safeout2_reg: ESAFEOUT2 { +- regulator-name = "SAFEOUT2"; +- regulator-boot-on; +- }; +- }; +- }; +- +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power-key { +- gpios = <&gph2 6 1>; +- linux,code = ; +- label = "power"; +- debounce-interval = <1>; +- wakeup-source; +- }; +- }; +-}; +- +-&xusbxti { +- clock-frequency = <24000000>; +-}; +- +-&keypad { +- linux,input-no-autorepeat; +- wakeup-source; +- samsung,keypad-num-rows = <3>; +- samsung,keypad-num-columns = <3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>, +- <&keypad_col0>, <&keypad_col1>, <&keypad_col2>; +- status = "okay"; +- +- key-1 { +- keypad,row = <0>; +- keypad,column = <1>; +- linux,code = ; +- }; +- +- key-2 { +- keypad,row = <0>; +- keypad,column = <2>; +- linux,code = ; +- }; +- +- key-3 { +- keypad,row = <1>; +- keypad,column = <1>; +- linux,code = ; +- }; +- +- key-4 { +- keypad,row = <1>; +- keypad,column = <2>; +- linux,code = ; +- }; +- +- key-5 { +- keypad,row = <2>; +- keypad,column = <1>; +- linux,code = ; +- }; +- +- key-6 { +- keypad,row = <2>; +- keypad,column = <2>; +- linux,code = ; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&rtc { +- clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&sdhci0 { +- bus-width = <4>; +- non-removable; +- status = "okay"; +- vmmc-supply = <&ldo5_reg>; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>; +- pinctrl-names = "default"; +-}; +- +-&sdhci2 { +- bus-width = <4>; +- cd-gpios = <&gph3 4 1>; +- vmmc-supply = <&vtf_reg>; +- cd-inverted; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &t_flash_detect>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&onenand { +- status = "okay"; +-}; +- +-&hsotg { +- vusb_a-supply = <&ldo3_reg>; +- vusb_d-supply = <&ldo8_reg>; +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&fimd { +- pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; +- pinctrl-names = "default"; +- status = "okay"; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing { +- clock-frequency = <0>; +- hactive = <800>; +- vactive = <480>; +- hfront-porch = <16>; +- hback-porch = <16>; +- hsync-len = <2>; +- vback-porch = <3>; +- vfront-porch = <28>; +- vsync-len = <1>; +- }; +- }; +-}; +- +-&pinctrl0 { +- t_flash_detect: t-flash-detect { +- samsung,pins = "gph3-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/s5pv210-aries.dtsi b/scripts/dtc/include-prefixes/arm/s5pv210-aries.dtsi +deleted file mode 100644 +index 160f8cd9a68d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s5pv210-aries.dtsi ++++ /dev/null +@@ -1,917 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's S5PV210 based Galaxy Aries board device tree source +- */ +- +-/dts-v1/; +-#include +-#include +-#include "s5pv210.dtsi" +- +-/ { +- compatible = "samsung,aries", "samsung,s5pv210"; +- +- aliases: aliases { +- i2c4 = &i2c_sound; +- i2c5 = &i2c_accel; +- i2c6 = &i2c_pmic; +- i2c7 = &i2c_musb; +- i2c9 = &i2c_fuel; +- i2c10 = &i2c_touchkey; +- i2c11 = &i2c_prox; +- i2c12 = &i2c_magnetometer; +- }; +- +- memory@30000000 { +- device_type = "memory"; +- reg = <0x30000000 0x05000000 +- 0x40000000 0x10000000 +- 0x50000000 0x08000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- mfc_left: region@43000000 { +- compatible = "shared-dma-pool"; +- no-map; +- reg = <0x43000000 0x2000000>; +- }; +- +- mfc_right: region@51000000 { +- compatible = "shared-dma-pool"; +- no-map; +- reg = <0x51000000 0x2000000>; +- }; +- }; +- +- pmic_ap_clk: clock-0 { +- /* Workaround for missing clock on PMIC */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- bt_codec: bt-sco { +- compatible = "linux,bt-sco"; +- #sound-dai-cells = <0>; +- }; +- +- vibrator_pwr: regulator-fixed-0 { +- compatible = "regulator-fixed"; +- regulator-name = "vibrator-en"; +- enable-active-high; +- gpio = <&gpj1 1 GPIO_ACTIVE_HIGH>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&vibrator_ena>; +- }; +- +- touchkey_vdd: regulator-fixed-1 { +- compatible = "regulator-fixed"; +- regulator-name = "VTOUCH_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- gpio = <&gpj3 2 GPIO_ACTIVE_HIGH>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&touchkey_vdd_ena>; +- }; +- +- gp2a_vled: regulator-fixed-2 { +- compatible = "regulator-fixed"; +- regulator-name = "VLED"; +- enable-active-high; +- gpio = <&gpj1 4 GPIO_ACTIVE_HIGH>; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gp2a_power>; +- }; +- +- wifi_pwrseq: wifi-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpg1 2 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_gpio_rst>; +- post-power-on-delay-ms = <500>; +- power-off-delay-us = <500>; +- }; +- +- i2c_sound: i2c-gpio-0 { +- compatible = "i2c-gpio"; +- sda-gpios = <&mp05 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&mp05 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sound_i2c_pins>; +- +- wm8994: audio-codec@1a { +- compatible = "wlf,wm8994"; +- reg = <0x1a>; +- +- #sound-dai-cells = <0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- clocks = <&clocks MOUT_CLKOUT>; +- clock-names = "MCLK1"; +- +- AVDD2-supply = <&buck3_reg>; +- DBVDD-supply = <&buck3_reg>; +- CPVDD-supply = <&buck3_reg>; +- SPKVDD1-supply = <&buck3_reg>; +- SPKVDD2-supply = <&buck3_reg>; +- +- wlf,gpio-cfg = <0xa101 0x8100 0x0100 0x0100 0x8100 +- 0xa101 0x0100 0x8100 0x0100 0x0100 +- 0x0100>; +- +- wlf,ldo1ena = <&gpf3 4 GPIO_ACTIVE_HIGH>; +- wlf,ldo2ena = <&gpf3 4 GPIO_ACTIVE_HIGH>; +- +- wlf,lineout1-se; +- wlf,lineout2-se; +- +- assigned-clocks = <&clocks MOUT_CLKOUT>; +- assigned-clock-rates = <0>; +- assigned-clock-parents = <&xusbxti>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&codec_ldo>; +- }; +- }; +- +- i2c_accel: i2c-gpio-1 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpj3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpj3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&accel_i2c_pins>; +- +- accelerometer@38 { +- compatible = "bosch,bma023"; +- reg = <0x38>; +- +- vdd-supply = <&ldo9_reg>; +- vddio-supply = <&ldo9_reg>; +- }; +- }; +- +- i2c_pmic: i2c-gpio-2 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpj4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpj4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_i2c_pins>; +- +- pmic@66 { +- compatible = "maxim,max8998"; +- reg = <0x66>; +- interrupt-parent = <&gph0>; +- interrupts = <7 IRQ_TYPE_EDGE_FALLING>; +- +- max8998,pmic-buck1-default-dvs-idx = <1>; +- max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>, +- <&gph0 4 GPIO_ACTIVE_HIGH>; +- max8998,pmic-buck1-dvs-voltage = <1275000>, <1200000>, +- <1050000>, <950000>; +- +- max8998,pmic-buck2-default-dvs-idx = <0>; +- max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; +- max8998,pmic-buck2-dvs-voltage = <1100000>, <1000000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_dvs_pins &pmic_irq>; +- +- regulators { +- ldo2_reg: LDO2 { +- regulator-name = "VALIVE_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "VUSB_1.1V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "VADC_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "VTF_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "LDO6"; +- regulator-min-microvolt = <1600000>; +- regulator-max-microvolt = <3600000>; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "VLCD_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "VUSB_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "VCC_2.8V_PDA"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "VPLL_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "CAM_AF_3.0V"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "CAM_SENSOR_CORE_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "VGA_VDDIO_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "VGA_DVDD_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "CAM_ISP_HOST_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "VGA_AVDD_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "VCC_3.0V_LCD"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "vddarm"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1500000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <1250000>; +- }; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "vddint"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1500000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <1100000>; +- }; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "VCC_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "CAM_ISP_CORE_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ap32khz_reg: EN32KHz-AP { +- regulator-name = "32KHz AP"; +- regulator-always-on; +- }; +- +- cp32khz_reg: EN32KHz-CP { +- regulator-name = "32KHz CP"; +- }; +- +- vichg_reg: ENVICHG { +- regulator-name = "VICHG"; +- regulator-always-on; +- }; +- +- safe1_sreg: ESAFEOUT1 { +- regulator-name = "SAFEOUT1"; +- }; +- +- safe2_sreg: ESAFEOUT2 { +- regulator-name = "SAFEOUT2"; +- }; +- }; +- }; +- }; +- +- i2c_musb: i2c-gpio-3 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpj3 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpj3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&musb_i2c_pins>; +- +- fsa9480: musb@25 { +- compatible = "fcs,fsa9480"; +- reg = <0x25>; +- interrupt-parent = <&gph2>; +- interrupts = <7 IRQ_TYPE_EDGE_FALLING>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&musb_irq>; +- }; +- }; +- +- i2c_fuel: i2c-gpio-4 { +- compatible = "i2c-gpio"; +- sda-gpios = <&mp05 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&mp05 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&fg_i2c_pins>; +- +- fg: fuelgauge@36 { +- compatible = "maxim,max17040"; +- reg = <0x36>; +- }; +- }; +- +- i2c_touchkey: i2c-gpio-5 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpj3 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpj3 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&touchkey_i2c_pins>; +- +- touchkey@20 { +- compatible = "cypress,aries-touchkey"; +- reg = <0x20>; +- vdd-supply = <&touchkey_vdd>; +- vcc-supply = <&buck3_reg>; +- linux,keycodes = ; +- interrupt-parent = <&gpj4>; +- interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&touchkey_irq>; +- }; +- }; +- +- i2c_prox: i2c-gpio-6 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpg2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpg0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&prox_i2c_pins>; +- +- light-sensor@44 { +- compatible = "sharp,gp2ap002a00f"; +- reg = <0x44>; +- interrupt-parent = <&gph0>; +- interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +- vdd-supply = <&gp2a_vled>; +- vio-supply = <&gp2a_vled>; +- io-channels = <&gp2a_shunt>; +- io-channel-names = "alsout"; +- sharp,proximity-far-hysteresis = /bits/ 8 <0x40>; +- sharp,proximity-close-hysteresis = /bits/ 8 <0x20>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gp2a_irq>; +- }; +- }; +- +- i2c_magnetometer: i2c-gpio-7 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpj0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpj0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&magnetometer_i2c_pins>; +- +- status = "disabled"; +- +- /* Yamaha yas529 magnetometer, no mainline binding */ +- }; +- +- vibrator: pwm-vibrator { +- compatible = "pwm-vibrator"; +- pwms = <&pwm 1 44642 0>; +- pwm-names = "enable"; +- vcc-supply = <&vibrator_pwr>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm1_out>; +- }; +- +- poweroff: syscon-poweroff { +- compatible = "syscon-poweroff"; +- regmap = <&pmu_syscon>; +- offset = <0x681c>; /* PS_HOLD_CONTROL */ +- value = <0x5200>; +- }; +- +- spi_lcd: spi-2 { +- compatible = "spi-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- sck-gpios = <&mp04 1 GPIO_ACTIVE_HIGH>; +- mosi-gpios = <&mp04 3 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&mp01 1 GPIO_ACTIVE_HIGH>; +- num-chipselects = <1>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_spi_pins>; +- +- panel@0 { +- compatible = "samsung,s6e63m0"; +- reg = <0>; +- reset-gpios = <&mp05 5 GPIO_ACTIVE_LOW>; +- vdd3-supply = <&ldo7_reg>; +- vci-supply = <&ldo17_reg>; +- spi-cs-high; +- spi-max-frequency = <1200000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&panel_rst>; +- +- port { +- lcd_ep: endpoint { +- remote-endpoint = <&fimd_ep>; +- }; +- }; +- }; +- }; +-}; +- +-&adc { +- vdd-supply = <&ldo4_reg>; +- +- status = "okay"; +- +- gp2a_shunt: current-sense-shunt { +- compatible = "current-sense-shunt"; +- io-channels = <&adc 9>; +- shunt-resistor-micro-ohms = <47000000>; /* 47 ohms */ +- #io-channel-cells = <0>; +- }; +-}; +- +-&fimd { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_clk &lcd_data24>; +- status = "okay"; +- +- samsung,invert-vden; +- samsung,invert-vclk; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@3 { +- reg = <3>; +- fimd_ep: endpoint { +- remote-endpoint = <&lcd_ep>; +- }; +- }; +-}; +- +-&hsotg { +- vusb_a-supply = <&ldo8_reg>; +- vusb_d-supply = <&ldo3_reg>; +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&i2c2 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <400000>; +- samsung,i2c-slave-addr = <0x10>; +- status = "okay"; +- +- touchscreen@4a { +- compatible = "atmel,maxtouch"; +- reg = <0x4a>; +- interrupt-parent = <&gpj0>; +- interrupts = <5 IRQ_TYPE_EDGE_FALLING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ts_irq>; +- reset-gpios = <&gpj1 3 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&i2s0 { +- dmas = <&pdma0 9>, <&pdma0 10>, <&pdma0 11>; +- status = "okay"; +-}; +- +-&mfc { +- memory-region = <&mfc_left>, <&mfc_right>; +-}; +- +-&pinctrl0 { +- bt_reset: bt-reset { +- samsung,pins = "gpb-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- wlan_bt_en: wlan-bt-en { +- samsung,pins = "gpb-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-val = <1>; +- }; +- +- codec_ldo: codec-ldo { +- samsung,pins = "gpf3-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- prox_i2c_pins: gp2a-i2c-pins { +- samsung,pins = "gpg0-2", "gpg2-2"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- wlan_gpio_rst: wlan-gpio-rst { +- samsung,pins = "gpg1-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- bt_wake: bt-wake { +- samsung,pins = "gpg3-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- gp2a_irq: gp2a-irq { +- samsung,pins = "gph0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pmic_dvs_pins: pmic-dvs-pins { +- samsung,pins = "gph0-3", "gph0-4", "gph0-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- samsung,pin-val = <0>; +- }; +- +- pmic_irq: pmic-irq { +- samsung,pins = "gph0-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- wifi_host_wake: wifi-host-wake { +- samsung,pins = "gph2-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- bt_host_wake: bt-host-wake { +- samsung,pins = "gph2-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- musb_irq: musq-irq { +- samsung,pins = "gph2-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- tf_detect: tf-detect { +- samsung,pins = "gph3-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- wifi_wake: wifi-wake { +- samsung,pins = "gph3-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- magnetometer_i2c_pins: yas529-i2c-pins { +- samsung,pins = "gpj0-0", "gpj0-1"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- ts_irq: ts-irq { +- samsung,pins = "gpj0-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- vibrator_ena: vibrator-ena { +- samsung,pins = "gpj1-1"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- gp2a_power: gp2a-power { +- samsung,pins = "gpj1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- touchkey_i2c_pins: touchkey-i2c-pins { +- samsung,pins = "gpj3-0", "gpj3-1"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- touchkey_vdd_ena: touchkey-vdd-ena { +- samsung,pins = "gpj3-2"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- musb_i2c_pins: musb-i2c-pins { +- samsung,pins = "gpj3-4", "gpj3-5"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- accel_i2c_pins: accel-i2c-pins { +- samsung,pins = "gpj3-6", "gpj3-7"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pmic_i2c_pins: pmic-i2c-pins { +- samsung,pins = "gpj4-0", "gpj4-3"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- touchkey_irq: touchkey-irq { +- samsung,pins = "gpj4-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lcd_spi_pins: spi-lcd-pins { +- samsung,pins = "mp01-1", "mp04-1", "mp04-3"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- fg_i2c_pins: fg-i2c-pins { +- samsung,pins = "mp05-0", "mp05-1"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sound_i2c_pins: sound-i2c-pins { +- samsung,pins = "mp05-2", "mp05-3"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- panel_rst: panel-rst { +- samsung,pins = "mp05-5"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pwm { +- samsung,pwm-outputs = <1>; +-}; +- +-&rtc { +- clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&sdhci1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- bus-width = <4>; +- max-frequency = <38400000>; +- pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4 &wifi_wake &wifi_host_wake &wlan_bt_en>; +- pinctrl-names = "default"; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- keep-power-in-suspend; +- +- mmc-pwrseq = <&wifi_pwrseq>; +- non-removable; +- status = "okay"; +- +- assigned-clocks = <&clocks MOUT_MMC1>, <&clocks SCLK_MMC1>; +- assigned-clock-rates = <0>, <50000000>; +- assigned-clock-parents = <&clocks MOUT_MPLL>; +- +- wlan@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&gph2>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "host-wake"; +- }; +-}; +- +-&sdhci2 { +- bus-width = <4>; +- cd-gpios = <&gph3 4 GPIO_ACTIVE_LOW>; +- vmmc-supply = <&ldo5_reg>; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &tf_detect>; +- pinctrl-names = "default"; +- status = "okay"; +- +- assigned-clocks = <&clocks MOUT_MMC2>, <&clocks SCLK_MMC2>; +- assigned-clock-rates = <0>, <50000000>; +- assigned-clock-parents = <&clocks MOUT_MPLL>; +-}; +- +-&uart0 { +- assigned-clocks = <&clocks MOUT_UART0>, <&clocks SCLK_UART0>; +- assigned-clock-rates = <0>, <111166667>; +- assigned-clock-parents = <&clocks MOUT_MPLL>; +- +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm4329-bt"; +- max-speed = <3000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_data &uart0_fctl &bt_host_wake +- &bt_reset &bt_wake>; +- shutdown-gpios = <&gpb 3 GPIO_ACTIVE_HIGH>; +- device-wakeup-gpios = <&gpg3 4 GPIO_ACTIVE_HIGH>; +- interrupt-parent = <&gph2>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "host-wake"; +- }; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +- vbus-supply = <&safe1_sreg>; +-}; +- +-&xusbxti { +- clock-frequency = <24000000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/s5pv210-fascinate4g.dts b/scripts/dtc/include-prefixes/arm/s5pv210-fascinate4g.dts +deleted file mode 100644 +index b47d8300e536..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s5pv210-fascinate4g.dts ++++ /dev/null +@@ -1,402 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/dts-v1/; +-#include +-#include +-#include "s5pv210-aries.dtsi" +- +-/ { +- model = "Samsung Galaxy S Fascinate 4G (SGH-T959P) based on S5PV210"; +- compatible = "samsung,fascinate4g", "samsung,aries", "samsung,s5pv210"; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "power"; +- gpios = <&gph2 6 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- vol-down { +- label = "volume_down"; +- gpios = <&gph3 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- vol-up { +- label = "volume_up"; +- gpios = <&gph3 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- headset_micbias_reg: regulator-fixed-3 { +- compatible = "regulator-fixed"; +- regulator-name = "Headset_Micbias"; +- gpio = <&gpj2 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&headset_micbias_ena>; +- }; +- +- main_micbias_reg: regulator-fixed-4 { +- compatible = "regulator-fixed"; +- regulator-name = "Main_Micbias"; +- gpio = <&gpj4 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&main_micbias_ena>; +- }; +- +- sound { +- compatible = "samsung,fascinate4g-wm8994"; +- +- model = "Fascinate4G"; +- +- extcon = <&fsa9480>; +- +- main-micbias-supply = <&main_micbias_reg>; +- headset-micbias-supply = <&headset_micbias_reg>; +- +- earpath-sel-gpios = <&gpj2 6 GPIO_ACTIVE_HIGH>; +- +- io-channels = <&adc 3>; +- io-channel-names = "headset-detect"; +- headset-detect-gpios = <&gph0 6 GPIO_ACTIVE_HIGH>; +- headset-key-gpios = <&gph3 6 GPIO_ACTIVE_HIGH>; +- +- samsung,audio-routing = +- "HP", "HPOUT1L", +- "HP", "HPOUT1R", +- +- "SPK", "SPKOUTLN", +- "SPK", "SPKOUTLP", +- +- "RCV", "HPOUT2N", +- "RCV", "HPOUT2P", +- +- "LINE", "LINEOUT2N", +- "LINE", "LINEOUT2P", +- +- "IN1LP", "Main Mic", +- "IN1LN", "Main Mic", +- +- "IN1RP", "Headset Mic", +- "IN1RN", "Headset Mic", +- +- "Modem Out", "Modem TX", +- "Modem RX", "Modem In", +- +- "Bluetooth SPK", "TX", +- "RX", "Bluetooth Mic"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&headset_det &earpath_sel>; +- +- cpu { +- sound-dai = <&i2s0>, <&bt_codec>; +- }; +- +- codec { +- sound-dai = <&wm8994>; +- }; +- }; +-}; +- +-&fg { +- compatible = "maxim,max77836-battery"; +- +- interrupt-parent = <&gph3>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&fg_irq>; +-}; +- +-&pinctrl0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sleep_cfg>; +- +- headset_det: headset-det { +- samsung,pins = "gph0-6", "gph3-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- fg_irq: fg-irq { +- samsung,pins = "gph3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- headset_micbias_ena: headset-micbias-ena { +- samsung,pins = "gpj2-5"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- earpath_sel: earpath-sel { +- samsung,pins = "gpj2-6"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- main_micbias_ena: main-micbias-ena { +- samsung,pins = "gpj4-2"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- /* Based on vendor kernel v2.6.35.7 */ +- sleep_cfg: sleep-cfg { +- PIN_SLP(gpa0-0, PREV, NONE); +- PIN_SLP(gpa0-1, PREV, NONE); +- PIN_SLP(gpa0-2, PREV, NONE); +- PIN_SLP(gpa0-3, OUT1, NONE); +- PIN_SLP(gpa0-4, PREV, NONE); +- PIN_SLP(gpa0-5, PREV, NONE); +- PIN_SLP(gpa0-6, PREV, NONE); +- PIN_SLP(gpa0-7, PREV, NONE); +- +- PIN_SLP(gpa1-0, INPUT, DOWN); +- PIN_SLP(gpa1-1, OUT0, NONE); +- PIN_SLP(gpa1-2, INPUT, DOWN); +- PIN_SLP(gpa1-3, OUT0, NONE); +- +- PIN_SLP(gpb-0, OUT0, NONE); +- PIN_SLP(gpb-1, OUT1, NONE); +- PIN_SLP(gpb-2, OUT0, NONE); +- PIN_SLP(gpb-3, PREV, NONE); +- PIN_SLP(gpb-4, INPUT, NONE); +- PIN_SLP(gpb-5, PREV, NONE); +- PIN_SLP(gpb-6, INPUT, DOWN); +- PIN_SLP(gpb-7, OUT0, NONE); +- +- PIN_SLP(gpc0-0, OUT0, NONE); +- PIN_SLP(gpc0-1, INPUT, DOWN); +- PIN_SLP(gpc0-2, OUT0, NONE); +- PIN_SLP(gpc0-3, INPUT, DOWN); +- PIN_SLP(gpc0-4, OUT0, NONE); +- +- PIN_SLP(gpc1-0, INPUT, DOWN); +- PIN_SLP(gpc1-1, INPUT, DOWN); +- PIN_SLP(gpc1-2, INPUT, DOWN); +- PIN_SLP(gpc1-3, INPUT, DOWN); +- PIN_SLP(gpc1-4, INPUT, DOWN); +- +- PIN_SLP(gpd0-0, INPUT, DOWN); +- PIN_SLP(gpd0-1, OUT0, NONE); +- PIN_SLP(gpd0-2, INPUT, DOWN); +- PIN_SLP(gpd0-3, INPUT, DOWN); +- +- PIN_SLP(gpd1-0, INPUT, NONE); +- PIN_SLP(gpd1-1, INPUT, NONE); +- PIN_SLP(gpd1-2, INPUT, DOWN); +- PIN_SLP(gpd1-3, INPUT, DOWN); +- PIN_SLP(gpd1-4, INPUT, DOWN); +- PIN_SLP(gpd1-5, INPUT, DOWN); +- +- PIN_SLP(gpe0-0, INPUT, DOWN); +- PIN_SLP(gpe0-1, INPUT, DOWN); +- PIN_SLP(gpe0-2, INPUT, DOWN); +- PIN_SLP(gpe0-3, INPUT, DOWN); +- PIN_SLP(gpe0-4, INPUT, DOWN); +- PIN_SLP(gpe0-5, INPUT, DOWN); +- PIN_SLP(gpe0-6, INPUT, DOWN); +- PIN_SLP(gpe0-7, INPUT, DOWN); +- +- PIN_SLP(gpe1-0, INPUT, DOWN); +- PIN_SLP(gpe1-1, INPUT, DOWN); +- PIN_SLP(gpe1-2, INPUT, DOWN); +- PIN_SLP(gpe1-3, OUT0, NONE); +- PIN_SLP(gpe1-4, INPUT, DOWN); +- +- PIN_SLP(gpf0-0, OUT0, NONE); +- PIN_SLP(gpf0-1, OUT0, NONE); +- PIN_SLP(gpf0-2, OUT0, NONE); +- PIN_SLP(gpf0-3, OUT0, NONE); +- PIN_SLP(gpf0-4, OUT0, NONE); +- PIN_SLP(gpf0-5, OUT0, NONE); +- PIN_SLP(gpf0-6, OUT0, NONE); +- PIN_SLP(gpf0-7, OUT0, NONE); +- +- PIN_SLP(gpf1-0, OUT0, NONE); +- PIN_SLP(gpf1-1, OUT0, NONE); +- PIN_SLP(gpf1-2, OUT0, NONE); +- PIN_SLP(gpf1-3, OUT0, NONE); +- PIN_SLP(gpf1-4, OUT0, NONE); +- PIN_SLP(gpf1-5, OUT0, NONE); +- PIN_SLP(gpf1-6, OUT0, NONE); +- PIN_SLP(gpf1-7, OUT0, NONE); +- +- PIN_SLP(gpf2-0, OUT0, NONE); +- PIN_SLP(gpf2-1, OUT0, NONE); +- PIN_SLP(gpf2-2, OUT0, NONE); +- PIN_SLP(gpf2-3, OUT0, NONE); +- PIN_SLP(gpf2-4, OUT0, NONE); +- PIN_SLP(gpf2-5, OUT0, NONE); +- PIN_SLP(gpf2-6, OUT0, NONE); +- PIN_SLP(gpf2-7, OUT0, NONE); +- +- PIN_SLP(gpf3-0, OUT0, NONE); +- PIN_SLP(gpf3-1, OUT0, NONE); +- PIN_SLP(gpf3-2, OUT0, NONE); +- PIN_SLP(gpf3-3, OUT0, NONE); +- PIN_SLP(gpf3-4, PREV, NONE); +- PIN_SLP(gpf3-5, INPUT, DOWN); +- +- PIN_SLP(gpg0-0, INPUT, DOWN); +- PIN_SLP(gpg0-1, INPUT, DOWN); +- PIN_SLP(gpg0-2, INPUT, NONE); +- PIN_SLP(gpg0-3, INPUT, DOWN); +- PIN_SLP(gpg0-4, INPUT, DOWN); +- PIN_SLP(gpg0-5, INPUT, DOWN); +- PIN_SLP(gpg0-6, INPUT, DOWN); +- +- PIN_SLP(gpg1-0, OUT0, NONE); +- PIN_SLP(gpg1-1, OUT1, NONE); +- PIN_SLP(gpg1-2, PREV, NONE); +- PIN_SLP(gpg1-3, OUT1, NONE); +- PIN_SLP(gpg1-4, OUT1, NONE); +- PIN_SLP(gpg1-5, OUT1, NONE); +- PIN_SLP(gpg1-6, OUT1, NONE); +- +- PIN_SLP(gpg2-0, OUT0, NONE); +- PIN_SLP(gpg2-1, OUT0, NONE); +- PIN_SLP(gpg2-2, INPUT, NONE); +- PIN_SLP(gpg2-3, OUT0, NONE); +- PIN_SLP(gpg2-4, OUT0, NONE); +- PIN_SLP(gpg2-5, OUT0, NONE); +- PIN_SLP(gpg2-6, OUT0, NONE); +- +- PIN_SLP(gpg3-0, PREV, UP); +- PIN_SLP(gpg3-1, PREV, UP); +- PIN_SLP(gpg3-2, INPUT, NONE); +- PIN_SLP(gpg3-3, INPUT, DOWN); +- PIN_SLP(gpg3-4, OUT0, NONE); +- PIN_SLP(gpg3-5, OUT0, NONE); +- PIN_SLP(gpg3-6, INPUT, DOWN); +- +- PIN_SLP(gpi-0, PREV, NONE); +- PIN_SLP(gpi-1, INPUT, DOWN); +- PIN_SLP(gpi-2, PREV, NONE); +- PIN_SLP(gpi-3, PREV, NONE); +- PIN_SLP(gpi-4, PREV, NONE); +- PIN_SLP(gpi-5, INPUT, DOWN); +- PIN_SLP(gpi-6, INPUT, DOWN); +- +- PIN_SLP(gpj0-0, INPUT, NONE); +- PIN_SLP(gpj0-1, INPUT, NONE); +- PIN_SLP(gpj0-2, INPUT, NONE); +- PIN_SLP(gpj0-3, INPUT, NONE); +- PIN_SLP(gpj0-4, INPUT, NONE); +- PIN_SLP(gpj0-5, INPUT, DOWN); +- PIN_SLP(gpj0-6, OUT0, NONE); +- PIN_SLP(gpj0-7, INPUT, NONE); +- +- PIN_SLP(gpj1-0, OUT1, NONE); +- PIN_SLP(gpj1-1, OUT0, NONE); +- PIN_SLP(gpj1-2, INPUT, DOWN); +- PIN_SLP(gpj1-3, PREV, NONE); +- PIN_SLP(gpj1-4, PREV, NONE); +- PIN_SLP(gpj1-5, OUT0, NONE); +- +- PIN_SLP(gpj2-0, INPUT, DOWN); +- PIN_SLP(gpj2-1, INPUT, DOWN); +- PIN_SLP(gpj2-2, OUT0, NONE); +- PIN_SLP(gpj2-3, INPUT, DOWN); +- PIN_SLP(gpj2-4, INPUT, DOWN); +- PIN_SLP(gpj2-5, PREV, NONE); +- PIN_SLP(gpj2-6, PREV, NONE); +- PIN_SLP(gpj2-7, INPUT, DOWN); +- +- PIN_SLP(gpj3-0, INPUT, NONE); +- PIN_SLP(gpj3-1, INPUT, NONE); +- PIN_SLP(gpj3-2, OUT0, NONE); +- PIN_SLP(gpj3-3, INPUT, DOWN); +- PIN_SLP(gpj3-4, INPUT, NONE); +- PIN_SLP(gpj3-5, INPUT, NONE); +- PIN_SLP(gpj3-6, INPUT, NONE); +- PIN_SLP(gpj3-7, INPUT, NONE); +- +- PIN_SLP(gpj4-0, INPUT, NONE); +- PIN_SLP(gpj4-1, INPUT, DOWN); +- PIN_SLP(gpj4-2, PREV, NONE); +- PIN_SLP(gpj4-3, INPUT, NONE); +- PIN_SLP(gpj4-4, INPUT, DOWN); +- +- PIN_SLP(mp01-0, OUT1, NONE); +- PIN_SLP(mp01-1, OUT0, NONE); +- PIN_SLP(mp01-2, INPUT, DOWN); +- PIN_SLP(mp01-3, INPUT, DOWN); +- PIN_SLP(mp01-4, OUT1, NONE); +- PIN_SLP(mp01-5, INPUT, DOWN); +- PIN_SLP(mp01-6, INPUT, DOWN); +- PIN_SLP(mp01-7, INPUT, DOWN); +- +- PIN_SLP(mp02-0, INPUT, DOWN); +- PIN_SLP(mp02-1, INPUT, DOWN); +- PIN_SLP(mp02-2, INPUT, NONE); +- PIN_SLP(mp02-3, INPUT, DOWN); +- +- PIN_SLP(mp03-0, INPUT, DOWN); +- PIN_SLP(mp03-1, INPUT, DOWN); +- PIN_SLP(mp03-2, OUT1, NONE); +- PIN_SLP(mp03-3, OUT0, NONE); +- PIN_SLP(mp03-4, INPUT, NONE); +- PIN_SLP(mp03-5, OUT0, NONE); +- PIN_SLP(mp03-6, INPUT, DOWN); +- PIN_SLP(mp03-7, INPUT, DOWN); +- +- PIN_SLP(mp04-0, INPUT, DOWN); +- PIN_SLP(mp04-1, OUT0, NONE); +- PIN_SLP(mp04-2, INPUT, DOWN); +- PIN_SLP(mp04-3, OUT0, NONE); +- PIN_SLP(mp04-4, INPUT, DOWN); +- PIN_SLP(mp04-5, INPUT, DOWN); +- PIN_SLP(mp04-6, OUT0, NONE); +- PIN_SLP(mp04-7, INPUT, DOWN); +- +- PIN_SLP(mp05-0, INPUT, NONE); +- PIN_SLP(mp05-1, INPUT, NONE); +- PIN_SLP(mp05-2, INPUT, NONE); +- PIN_SLP(mp05-3, INPUT, NONE); +- PIN_SLP(mp05-4, INPUT, DOWN); +- PIN_SLP(mp05-5, OUT0, NONE); +- PIN_SLP(mp05-6, INPUT, DOWN); +- PIN_SLP(mp05-7, PREV, NONE); +- +- PIN_SLP(mp06-0, INPUT, DOWN); +- PIN_SLP(mp06-1, INPUT, DOWN); +- PIN_SLP(mp06-2, INPUT, DOWN); +- PIN_SLP(mp06-3, INPUT, DOWN); +- PIN_SLP(mp06-4, INPUT, DOWN); +- PIN_SLP(mp06-5, INPUT, DOWN); +- PIN_SLP(mp06-6, INPUT, DOWN); +- PIN_SLP(mp06-7, INPUT, DOWN); +- +- PIN_SLP(mp07-0, INPUT, DOWN); +- PIN_SLP(mp07-1, INPUT, DOWN); +- PIN_SLP(mp07-2, INPUT, DOWN); +- PIN_SLP(mp07-3, INPUT, DOWN); +- PIN_SLP(mp07-4, INPUT, DOWN); +- PIN_SLP(mp07-5, INPUT, DOWN); +- PIN_SLP(mp07-6, INPUT, DOWN); +- PIN_SLP(mp07-7, INPUT, DOWN); +- }; +-}; +- +-&wm8994 { +- /* GPIO3 (BCLK2) and GPIO4 (LRCLK2) as outputs */ +- wlf,gpio-cfg = <0xa101 0x8100 0x8100 0x8100 0x8100 0xa101 +- 0x0100 0x8100 0x0100 0x0100 0x0100>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/s5pv210-galaxys.dts b/scripts/dtc/include-prefixes/arm/s5pv210-galaxys.dts +deleted file mode 100644 +index 560f830b6f6b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s5pv210-galaxys.dts ++++ /dev/null +@@ -1,447 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/dts-v1/; +-#include +-#include +-#include "s5pv210-aries.dtsi" +- +-/ { +- model = "Samsung Galaxy S1 (GT-I9000) based on S5PV210"; +- compatible = "samsung,galaxys", "samsung,aries", "samsung,s5pv210"; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- nand_pwrseq: nand-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpj2 7 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&massmemory_en>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "power"; +- gpios = <&gph2 6 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- vol-down { +- label = "volume_down"; +- gpios = <&gph3 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- vol-up { +- label = "volume_up"; +- gpios = <&gph3 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- home { +- label = "home"; +- gpios = <&gph3 5 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- i2c_fmradio: i2c-gpio-8 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpd1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpd1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- i2c-gpio,delay-us = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&fm_i2c_pins>; +- +- fmradio@10 { +- compatible = "silabs,si470x"; +- reg = <0x10>; +- interrupt-parent = <&gpj2>; +- interrupts = <4 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&gpj2 5 GPIO_ACTIVE_HIGH>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&fm_irq &fm_rst>; +- }; +- }; +- +- micbias_reg: regulator-fixed-3 { +- compatible = "regulator-fixed"; +- regulator-name = "MICBIAS"; +- gpio = <&gpj4 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&micbias_reg_ena>; +- }; +- +- sound { +- compatible = "samsung,aries-wm8994"; +- +- model = "Aries"; +- +- extcon = <&fsa9480>; +- +- main-micbias-supply = <&micbias_reg>; +- headset-micbias-supply = <&micbias_reg>; +- +- earpath-sel-gpios = <&gpj2 6 GPIO_ACTIVE_HIGH>; +- +- io-channels = <&adc 3>; +- io-channel-names = "headset-detect"; +- headset-detect-gpios = <&gph0 6 GPIO_ACTIVE_LOW>; +- headset-key-gpios = <&gph3 6 GPIO_ACTIVE_HIGH>; +- +- samsung,audio-routing = +- "HP", "HPOUT1L", +- "HP", "HPOUT1R", +- +- "SPK", "SPKOUTLN", +- "SPK", "SPKOUTLP", +- +- "RCV", "HPOUT2N", +- "RCV", "HPOUT2P", +- +- "LINE", "LINEOUT2N", +- "LINE", "LINEOUT2P", +- +- "IN1LP", "Main Mic", +- "IN1LN", "Main Mic", +- +- "IN1RP", "Headset Mic", +- "IN1RN", "Headset Mic", +- +- "IN2LN", "FM In", +- "IN2RN", "FM In", +- +- "Modem Out", "Modem TX", +- "Modem RX", "Modem In", +- +- "Bluetooth SPK", "TX", +- "RX", "Bluetooth Mic"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&headset_det &earpath_sel>; +- +- cpu { +- sound-dai = <&i2s0>, <&bt_codec>; +- }; +- +- codec { +- sound-dai = <&wm8994>; +- }; +- }; +-}; +- +-&aliases { +- i2c8 = &i2c_fmradio; +-}; +- +-&pinctrl0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sleep_cfg>; +- +- fm_i2c_pins: fm-i2c-pins { +- samsung,pins = "gpd1-2", "gpd1-3"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- headset_det: headset-det { +- samsung,pins = "gph0-6", "gph3-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- fm_irq: fm-irq { +- samsung,pins = "gpj2-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- fm_rst: fm-rst { +- samsung,pins = "gpj2-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- earpath_sel: earpath-sel { +- samsung,pins = "gpj2-6"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- massmemory_en: massmemory-en { +- samsung,pins = "gpj2-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- micbias_reg_ena: micbias-reg-ena { +- samsung,pins = "gpj4-2"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- /* Based on CyanogenMod 3.0.101 kernel */ +- sleep_cfg: sleep-cfg { +- PIN_SLP(gpa0-0, PREV, NONE); +- PIN_SLP(gpa0-1, PREV, NONE); +- PIN_SLP(gpa0-2, PREV, NONE); +- PIN_SLP(gpa0-3, OUT1, NONE); +- PIN_SLP(gpa0-4, INPUT, DOWN); +- PIN_SLP(gpa0-5, OUT0, NONE); +- PIN_SLP(gpa0-6, INPUT, DOWN); +- PIN_SLP(gpa0-7, OUT1, NONE); +- +- PIN_SLP(gpa1-0, INPUT, DOWN); +- PIN_SLP(gpa1-1, OUT0, NONE); +- PIN_SLP(gpa1-2, INPUT, NONE); +- PIN_SLP(gpa1-3, OUT0, NONE); +- +- PIN_SLP(gpb-0, OUT0, NONE); +- PIN_SLP(gpb-1, OUT1, NONE); +- PIN_SLP(gpb-2, OUT0, NONE); +- PIN_SLP(gpb-3, PREV, NONE); +- PIN_SLP(gpb-4, INPUT, NONE); +- PIN_SLP(gpb-5, PREV, NONE); +- PIN_SLP(gpb-6, INPUT, DOWN); +- PIN_SLP(gpb-7, OUT0, NONE); +- +- PIN_SLP(gpc0-0, OUT0, NONE); +- PIN_SLP(gpc0-1, INPUT, DOWN); +- PIN_SLP(gpc0-2, OUT0, NONE); +- PIN_SLP(gpc0-3, INPUT, NONE); +- PIN_SLP(gpc0-4, OUT0, NONE); +- +- PIN_SLP(gpc1-0, INPUT, DOWN); +- PIN_SLP(gpc1-1, INPUT, DOWN); +- PIN_SLP(gpc1-2, INPUT, DOWN); +- PIN_SLP(gpc1-3, INPUT, DOWN); +- PIN_SLP(gpc1-4, INPUT, DOWN); +- +- PIN_SLP(gpd0-0, INPUT, DOWN); +- PIN_SLP(gpd0-1, OUT0, NONE); +- PIN_SLP(gpd0-2, INPUT, DOWN); +- PIN_SLP(gpd0-3, INPUT, DOWN); +- +- PIN_SLP(gpd1-0, INPUT, NONE); +- PIN_SLP(gpd1-1, INPUT, NONE); +- PIN_SLP(gpd1-2, INPUT, NONE); +- PIN_SLP(gpd1-3, INPUT, NONE); +- PIN_SLP(gpd1-4, INPUT, DOWN); +- PIN_SLP(gpd1-5, INPUT, DOWN); +- +- PIN_SLP(gpe0-0, INPUT, DOWN); +- PIN_SLP(gpe0-1, INPUT, DOWN); +- PIN_SLP(gpe0-2, INPUT, DOWN); +- PIN_SLP(gpe0-3, INPUT, DOWN); +- PIN_SLP(gpe0-4, INPUT, DOWN); +- PIN_SLP(gpe0-5, INPUT, DOWN); +- PIN_SLP(gpe0-6, INPUT, DOWN); +- PIN_SLP(gpe0-7, INPUT, DOWN); +- +- PIN_SLP(gpe1-0, INPUT, DOWN); +- PIN_SLP(gpe1-1, INPUT, DOWN); +- PIN_SLP(gpe1-2, INPUT, DOWN); +- PIN_SLP(gpe1-3, OUT0, NONE); +- PIN_SLP(gpe1-4, INPUT, DOWN); +- +- PIN_SLP(gpf0-0, OUT0, NONE); +- PIN_SLP(gpf0-1, OUT0, NONE); +- PIN_SLP(gpf0-2, OUT0, NONE); +- PIN_SLP(gpf0-3, OUT0, NONE); +- PIN_SLP(gpf0-4, OUT0, NONE); +- PIN_SLP(gpf0-5, OUT0, NONE); +- PIN_SLP(gpf0-6, OUT0, NONE); +- PIN_SLP(gpf0-7, OUT0, NONE); +- +- PIN_SLP(gpf1-0, OUT0, NONE); +- PIN_SLP(gpf1-1, OUT0, NONE); +- PIN_SLP(gpf1-2, OUT0, NONE); +- PIN_SLP(gpf1-3, OUT0, NONE); +- PIN_SLP(gpf1-4, OUT0, NONE); +- PIN_SLP(gpf1-5, OUT0, NONE); +- PIN_SLP(gpf1-6, OUT0, NONE); +- PIN_SLP(gpf1-7, OUT0, NONE); +- +- PIN_SLP(gpf2-0, OUT0, NONE); +- PIN_SLP(gpf2-1, OUT0, NONE); +- PIN_SLP(gpf2-2, OUT0, NONE); +- PIN_SLP(gpf2-3, OUT0, NONE); +- PIN_SLP(gpf2-4, OUT0, NONE); +- PIN_SLP(gpf2-5, OUT0, NONE); +- PIN_SLP(gpf2-6, OUT0, NONE); +- PIN_SLP(gpf2-7, OUT0, NONE); +- +- PIN_SLP(gpf3-0, OUT0, NONE); +- PIN_SLP(gpf3-1, OUT0, NONE); +- PIN_SLP(gpf3-2, OUT0, NONE); +- PIN_SLP(gpf3-3, OUT0, NONE); +- PIN_SLP(gpf3-4, PREV, NONE); +- PIN_SLP(gpf3-5, INPUT, DOWN); +- +- PIN_SLP(gpg0-0, OUT0, NONE); +- PIN_SLP(gpg0-1, INPUT, NONE); +- PIN_SLP(gpg0-2, INPUT, NONE); +- PIN_SLP(gpg0-3, INPUT, NONE); +- PIN_SLP(gpg0-4, INPUT, NONE); +- PIN_SLP(gpg0-5, INPUT, NONE); +- PIN_SLP(gpg0-6, INPUT, NONE); +- +- PIN_SLP(gpg1-0, OUT0, NONE); +- PIN_SLP(gpg1-1, OUT1, NONE); +- PIN_SLP(gpg1-2, PREV, NONE); +- PIN_SLP(gpg1-3, OUT1, NONE); +- PIN_SLP(gpg1-4, OUT1, NONE); +- PIN_SLP(gpg1-5, OUT1, NONE); +- PIN_SLP(gpg1-6, OUT1, NONE); +- +- PIN_SLP(gpg2-0, OUT0, NONE); +- PIN_SLP(gpg2-1, OUT0, NONE); +- PIN_SLP(gpg2-2, INPUT, NONE); +- PIN_SLP(gpg2-3, OUT0, NONE); +- PIN_SLP(gpg2-4, OUT0, NONE); +- PIN_SLP(gpg2-5, OUT0, NONE); +- PIN_SLP(gpg2-6, OUT0, NONE); +- +- PIN_SLP(gpg3-0, OUT1, NONE); +- PIN_SLP(gpg3-1, OUT0, NONE); +- PIN_SLP(gpg3-2, INPUT, NONE); +- PIN_SLP(gpg3-3, INPUT, DOWN); +- PIN_SLP(gpg3-4, OUT0, NONE); +- PIN_SLP(gpg3-5, OUT0, NONE); +- PIN_SLP(gpg3-6, INPUT, DOWN); +- +- PIN_SLP(gpi-0, PREV, NONE); +- PIN_SLP(gpi-1, INPUT, DOWN); +- PIN_SLP(gpi-2, PREV, NONE); +- PIN_SLP(gpi-3, PREV, NONE); +- PIN_SLP(gpi-4, PREV, NONE); +- PIN_SLP(gpi-5, INPUT, DOWN); +- PIN_SLP(gpi-6, INPUT, DOWN); +- +- PIN_SLP(gpj0-0, INPUT, NONE); +- PIN_SLP(gpj0-1, INPUT, NONE); +- PIN_SLP(gpj0-2, INPUT, NONE); +- PIN_SLP(gpj0-3, INPUT, NONE); +- PIN_SLP(gpj0-4, INPUT, NONE); +- PIN_SLP(gpj0-5, INPUT, DOWN); +- PIN_SLP(gpj0-6, OUT0, NONE); +- PIN_SLP(gpj0-7, INPUT, NONE); +- +- PIN_SLP(gpj1-0, INPUT, DOWN); +- PIN_SLP(gpj1-1, OUT0, NONE); +- PIN_SLP(gpj1-2, INPUT, DOWN); +- PIN_SLP(gpj1-3, PREV, NONE); +- PIN_SLP(gpj1-4, PREV, NONE); +- PIN_SLP(gpj1-5, OUT0, NONE); +- +- PIN_SLP(gpj2-0, INPUT, DOWN); +- PIN_SLP(gpj2-1, INPUT, DOWN); +- PIN_SLP(gpj2-2, OUT0, NONE); +- PIN_SLP(gpj2-3, INPUT, DOWN); +- PIN_SLP(gpj2-4, INPUT, UP); +- PIN_SLP(gpj2-5, PREV, NONE); +- PIN_SLP(gpj2-6, PREV, NONE); +- PIN_SLP(gpj2-7, OUT1, NONE); +- +- PIN_SLP(gpj3-0, INPUT, NONE); +- PIN_SLP(gpj3-1, INPUT, NONE); +- PIN_SLP(gpj3-2, OUT0, NONE); +- PIN_SLP(gpj3-3, INPUT, DOWN); +- PIN_SLP(gpj3-4, INPUT, NONE); +- PIN_SLP(gpj3-5, INPUT, NONE); +- PIN_SLP(gpj3-6, INPUT, NONE); +- PIN_SLP(gpj3-7, INPUT, NONE); +- +- PIN_SLP(gpj4-0, INPUT, NONE); +- PIN_SLP(gpj4-1, INPUT, DOWN); +- PIN_SLP(gpj4-2, PREV, NONE); +- PIN_SLP(gpj4-3, INPUT, NONE); +- PIN_SLP(gpj4-4, INPUT, DOWN); +- +- PIN_SLP(mp01-0, INPUT, DOWN); +- PIN_SLP(mp01-1, OUT0, NONE); +- PIN_SLP(mp01-2, INPUT, DOWN); +- PIN_SLP(mp01-3, INPUT, DOWN); +- PIN_SLP(mp01-4, OUT1, NONE); +- PIN_SLP(mp01-5, INPUT, DOWN); +- PIN_SLP(mp01-6, INPUT, DOWN); +- PIN_SLP(mp01-7, INPUT, DOWN); +- +- PIN_SLP(mp02-0, INPUT, DOWN); +- PIN_SLP(mp02-1, INPUT, DOWN); +- PIN_SLP(mp02-2, INPUT, NONE); +- PIN_SLP(mp02-3, INPUT, DOWN); +- +- PIN_SLP(mp03-0, INPUT, DOWN); +- PIN_SLP(mp03-1, INPUT, DOWN); +- PIN_SLP(mp03-2, OUT1, NONE); +- PIN_SLP(mp03-3, OUT0, NONE); +- PIN_SLP(mp03-4, INPUT, NONE); +- PIN_SLP(mp03-5, OUT1, NONE); +- PIN_SLP(mp03-6, INPUT, DOWN); +- PIN_SLP(mp03-7, INPUT, DOWN); +- +- PIN_SLP(mp04-0, INPUT, DOWN); +- PIN_SLP(mp04-1, OUT0, NONE); +- PIN_SLP(mp04-2, INPUT, DOWN); +- PIN_SLP(mp04-3, OUT0, NONE); +- PIN_SLP(mp04-4, INPUT, DOWN); +- PIN_SLP(mp04-5, INPUT, DOWN); +- PIN_SLP(mp04-6, OUT0, NONE); +- PIN_SLP(mp04-7, INPUT, DOWN); +- +- PIN_SLP(mp05-0, INPUT, NONE); +- PIN_SLP(mp05-1, INPUT, NONE); +- PIN_SLP(mp05-2, INPUT, NONE); +- PIN_SLP(mp05-3, INPUT, NONE); +- PIN_SLP(mp05-4, INPUT, DOWN); +- PIN_SLP(mp05-5, OUT0, NONE); +- PIN_SLP(mp05-6, INPUT, DOWN); +- PIN_SLP(mp05-7, PREV, NONE); +- +- PIN_SLP(mp06-0, INPUT, DOWN); +- PIN_SLP(mp06-1, INPUT, DOWN); +- PIN_SLP(mp06-2, INPUT, DOWN); +- PIN_SLP(mp06-3, INPUT, DOWN); +- PIN_SLP(mp06-4, INPUT, DOWN); +- PIN_SLP(mp06-5, INPUT, DOWN); +- PIN_SLP(mp06-6, INPUT, DOWN); +- PIN_SLP(mp06-7, INPUT, DOWN); +- +- PIN_SLP(mp07-0, INPUT, DOWN); +- PIN_SLP(mp07-1, INPUT, DOWN); +- PIN_SLP(mp07-2, INPUT, DOWN); +- PIN_SLP(mp07-3, INPUT, DOWN); +- PIN_SLP(mp07-4, INPUT, DOWN); +- PIN_SLP(mp07-5, INPUT, DOWN); +- PIN_SLP(mp07-6, INPUT, DOWN); +- PIN_SLP(mp07-7, INPUT, DOWN); +- }; +-}; +- +-&sdhci0 { +- bus-width = <4>; +- non-removable; +- mmc-pwrseq = <&nand_pwrseq>; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>; +- pinctrl-names = "default"; +- status = "okay"; +- +- assigned-clocks = <&clocks MOUT_MMC0>, <&clocks SCLK_MMC0>; +- assigned-clock-rates = <0>, <52000000>; +- assigned-clock-parents = <&clocks MOUT_MPLL>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/s5pv210-goni.dts b/scripts/dtc/include-prefixes/arm/s5pv210-goni.dts +deleted file mode 100644 +index c6f39147cb96..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s5pv210-goni.dts ++++ /dev/null +@@ -1,447 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's S5PV210 SoC device tree source +- * +- * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. +- * +- * Mateusz Krawczuk +- * Tomasz Figa +- * +- * Board device tree source for Samsung Goni board. +- */ +- +-/dts-v1/; +-#include +-#include +-#include +-#include "s5pv210.dtsi" +- +-/ { +- model = "Samsung Goni based on S5PC110"; +- compatible = "samsung,goni", "samsung,s5pv210"; +- +- aliases { +- i2c3 = &i2c_pmic; +- }; +- +- chosen { +- bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p5 rw rootwait ignore_loglevel earlyprintk"; +- }; +- +- memory@30000000 { +- device_type = "memory"; +- reg = <0x30000000 0x05000000 +- 0x40000000 0x10000000 +- 0x50000000 0x08000000>; +- }; +- +- pmic_ap_clk: clock-0 { +- /* Workaround for missing clock on PMIC */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- vtf_reg: regulator-0 { +- compatible = "regulator-fixed"; +- regulator-name = "V_TF_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&mp05 4 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- pda_reg: regulator-1 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_1.8V_PDA"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- bat_reg: regulator-2 { +- compatible = "regulator-fixed"; +- regulator-name = "V_BAT"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- }; +- +- tsp_reg: regulator-3 { +- compatible = "regulator-fixed"; +- regulator-name = "TSP_VDD"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpj1 3 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- i2c_pmic: i2c-pmic { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpj4 0 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&gpj4 3 GPIO_ACTIVE_HIGH>; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- +- pmic@66 { +- compatible = "national,lp3974"; +- reg = <0x66>; +- +- max8998,pmic-buck1-default-dvs-idx = <0>; +- max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>, +- <&gph0 4 GPIO_ACTIVE_HIGH>; +- max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>, +- <1200000>, <1200000>; +- +- max8998,pmic-buck2-default-dvs-idx = <0>; +- max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; +- max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>; +- +- regulators { +- ldo2_reg: LDO2 { +- regulator-name = "VALIVE_1.1V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "VUSB+MIPI_1.1V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "VADC_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "VTF_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "VCC_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "VLCD_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "VUSB+VDAC_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "VCC+VCAM_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "VPLL_1.1V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-boot-on; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "CAM_IO_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "CAM_ISP_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "CAM_A_2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "CAM_CIF_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "CAM_AF_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "VMIPI_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "CAM_8M_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "VARM_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "VINT_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "VCC_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "CAM_CORE_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ap32khz_reg: EN32KHz-AP { +- regulator-name = "32KHz AP"; +- regulator-always-on; +- }; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power-key { +- gpios = <&gph2 6 1>; +- linux,code = ; +- label = "power"; +- debounce-interval = <1>; +- wakeup-source; +- }; +- }; +-}; +- +-&xusbxti { +- clock-frequency = <24000000>; +-}; +- +-&keypad { +- linux,input-no-autorepeat; +- wakeup-source; +- samsung,keypad-num-rows = <3>; +- samsung,keypad-num-columns = <3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>, +- <&keypad_col0>, <&keypad_col1>, <&keypad_col2>; +- status = "okay"; +- +- key-1 { +- keypad,row = <0>; +- keypad,column = <1>; +- linux,code = ; +- }; +- +- key-2 { +- keypad,row = <0>; +- keypad,column = <2>; +- linux,code = ; +- }; +- +- key-3 { +- keypad,row = <1>; +- keypad,column = <1>; +- linux,code = ; +- }; +- +- key-4 { +- keypad,row = <1>; +- keypad,column = <2>; +- linux,code = ; +- }; +- +- key-5 { +- keypad,row = <2>; +- keypad,column = <1>; +- linux,code = ; +- }; +- +- key-6 { +- keypad,row = <2>; +- keypad,column = <2>; +- linux,code = ; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&rtc { +- clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&sdhci0 { +- bus-width = <4>; +- non-removable; +- vmmc-supply = <&ldo5_reg>; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&sdhci2 { +- bus-width = <4>; +- cd-gpios = <&gph3 4 1>; +- vmmc-supply = <&vtf_reg>; +- cd-inverted; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&hsotg { +- vusb_a-supply = <&ldo3_reg>; +- vusb_d-supply = <&ldo8_reg>; +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&i2c2 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <400000>; +- samsung,i2c-slave-addr = <0x10>; +- status = "okay"; +- +- touchscreen@4a { +- compatible = "atmel,maxtouch"; +- reg = <0x4a>; +- interrupt-parent = <&gpj0>; +- interrupts = <5 IRQ_TYPE_EDGE_FALLING>; +- vdd-supply = <&tsp_reg>; +- }; +-}; +- +-&i2c0 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <100000>; +- samsung,i2c-slave-addr = <0x10>; +- status = "okay"; +- +- noon010pc30: sensor@30 { +- compatible = "siliconfile,noon010pc30"; +- reg = <0x30>; +- vddio-supply = <&ldo11_reg>; +- vdda-supply = <&ldo13_reg>; +- vdd_core-supply = <&ldo14_reg>; +- +- clock-frequency = <16000000>; +- clocks = <&camera 0>; +- clock-names = "mclk"; +- nreset-gpios = <&gpb 2 GPIO_ACTIVE_HIGH>; +- nstby-gpios = <&gpb 0 GPIO_ACTIVE_HIGH>; +- +- port { +- noon010pc30_ep: endpoint { +- remote-endpoint = <&fimc0_ep>; +- bus-width = <8>; +- hsync-active = <0>; +- vsync-active = <1>; +- pclk-sample = <1>; +- }; +- }; +- }; +-}; +- +-&camera { +- pinctrl-0 = <&cam_port_a_io &cam_port_a_clk_active>; +- pinctrl-1 = <&cam_port_a_io &cam_port_a_clk_idle>; +- pinctrl-names = "default", "idle"; +- +- parallel-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* camera A input */ +- port@1 { +- reg = <1>; +- fimc0_ep: endpoint { +- remote-endpoint = <&noon010pc30_ep>; +- bus-width = <8>; +- hsync-active = <1>; +- vsync-active = <1>; +- pclk-sample = <0>; +- }; +- }; +- }; +-}; +- +-&fimd { +- pinctrl-0 = <&lcd_clk &lcd_data24>; +- pinctrl-names = "default"; +- status = "okay"; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing { +- /* 480x800@55Hz */ +- clock-frequency = <23439570>; +- hactive = <480>; +- hfront-porch = <16>; +- hback-porch = <16>; +- hsync-len = <2>; +- vactive = <800>; +- vback-porch = <2>; +- vfront-porch = <28>; +- vsync-len = <1>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <0>; +- pixelclk-active = <0>; +- }; +- }; +-}; +- +-&onenand { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/s5pv210-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/s5pv210-pinctrl.dtsi +deleted file mode 100644 +index b8c5172c31dd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s5pv210-pinctrl.dtsi ++++ /dev/null +@@ -1,849 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's S5PV210 SoC device tree source +- * +- * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. +- * +- * Mateusz Krawczuk +- * Tomasz Figa +- * +- * Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210 +- * based board files can include this file and provide values for board specfic +- * bindings. +- * +- * Note: This file does not include device nodes for all the controllers in +- * S5PV210 SoC. As device tree coverage for S5PV210 increases, additional +- * nodes can be added to this file. +- */ +- +-#include +- +-#define PIN_SLP(_pin, _mode, _pull) \ +- _pin { \ +- samsung,pins = #_pin; \ +- samsung,pin-con-pdn = ; \ +- samsung,pin-pud-pdn = ; \ +- } +- +-&pinctrl0 { +- gpa0: gpa0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpa1: gpa1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb: gpb { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc0: gpc0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc1: gpc1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd0: gpd0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd1: gpd1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpe0: gpe0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpe1: gpe1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf0: gpf0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf1: gpf1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf2: gpf2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf3: gpf3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg0: gpg0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg1: gpg1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg2: gpg2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg3: gpg3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpj0: gpj0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpj1: gpj1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpj2: gpj2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpj3: gpj3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpj4: gpj4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpi: gpi { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- mp01: mp01 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- mp02: mp02 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- mp03: mp03 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- mp04: mp04 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- mp05: mp05 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- mp06: mp06 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- mp07: mp07 { +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gph0: gph0 { +- gpio-controller; +- interrupt-controller; +- interrupt-parent = <&vic0>; +- interrupts = <0>, <1>, <2>, <3>, +- <4>, <5>, <6>, <7>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- }; +- +- gph1: gph1 { +- gpio-controller; +- interrupt-controller; +- interrupt-parent = <&vic0>; +- interrupts = <8>, <9>, <10>, <11>, +- <12>, <13>, <14>, <15>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- }; +- +- gph2: gph2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gph3: gph3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- uart0_data: uart0-data { +- samsung,pins = "gpa0-0", "gpa0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart0_fctl: uart0-fctl { +- samsung,pins = "gpa0-2", "gpa0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart1_data: uart1-data { +- samsung,pins = "gpa0-4", "gpa0-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart1_fctl: uart1-fctl { +- samsung,pins = "gpa0-6", "gpa0-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart2_data: uart2-data { +- samsung,pins = "gpa1-0", "gpa1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart2_fctl: uart2-fctl { +- samsung,pins = "gpa1-2", "gpa1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart3_data: uart3-data { +- samsung,pins = "gpa1-2", "gpa1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart_audio: uart-audio { +- samsung,pins = "gpa1-2", "gpa1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi0_bus: spi0-bus { +- samsung,pins = "gpb-0", "gpb-2", "gpb-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi1_bus: spi1-bus { +- samsung,pins = "gpb-4", "gpb-6", "gpb-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2s0_bus: i2s0-bus { +- samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", +- "gpi-4", "gpi-5", "gpi-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2s1_bus: i2s1-bus { +- samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", +- "gpc0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2s2_bus: i2s2-bus { +- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", +- "gpc1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pcm1_bus: pcm1-bus { +- samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", +- "gpc0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- ac97_bus: ac97-bus { +- samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", +- "gpc0-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2s2_bus: i2s2-bus { +- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", +- "gpc1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pcm2_bus: pcm2-bus { +- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", +- "gpc1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spdif_bus: spdif-bus { +- samsung,pins = "gpc1-0", "gpc1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi2_bus: spi2-bus { +- samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c0_bus: i2c0-bus { +- samsung,pins = "gpd1-0", "gpd1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c1_bus: i2c1-bus { +- samsung,pins = "gpd1-2", "gpd1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2c2_bus: i2c2-bus { +- samsung,pins = "gpd1-4", "gpd1-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm0_out: pwm0-out { +- samsung,pins = "gpd0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm1_out: pwm1-out { +- samsung,pins = "gpd0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm2_out: pwm2-out { +- samsung,pins = "gpd0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm3_out: pwm3-out { +- samsung,pins = "gpd0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- keypad_row0: keypad-row-0 { +- samsung,pins = "gph3-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- keypad_row1: keypad-row-1 { +- samsung,pins = "gph3-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- keypad_row2: keypad-row-2 { +- samsung,pins = "gph3-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- keypad_row3: keypad-row-3 { +- samsung,pins = "gph3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- keypad_row4: keypad-row-4 { +- samsung,pins = "gph3-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- keypad_row5: keypad-row-5 { +- samsung,pins = "gph3-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- keypad_row6: keypad-row-6 { +- samsung,pins = "gph3-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- keypad_row7: keypad-row-7 { +- samsung,pins = "gph3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- keypad_col0: keypad-col-0 { +- samsung,pins = "gph2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- keypad_col1: keypad-col-1 { +- samsung,pins = "gph2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- keypad_col2: keypad-col-2 { +- samsung,pins = "gph2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- keypad_col3: keypad-col-3 { +- samsung,pins = "gph2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- keypad_col4: keypad-col-4 { +- samsung,pins = "gph2-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- keypad_col5: keypad-col-5 { +- samsung,pins = "gph2-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- keypad_col6: keypad-col-6 { +- samsung,pins = "gph2-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- keypad_col7: keypad-col-7 { +- samsung,pins = "gph2-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_clk: sd0-clk { +- samsung,pins = "gpg0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_cmd: sd0-cmd { +- samsung,pins = "gpg0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_cd: sd0-cd { +- samsung,pins = "gpg0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus1: sd0-bus-width1 { +- samsung,pins = "gpg0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus4: sd0-bus-width4 { +- samsung,pins = "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus8: sd0-bus-width8 { +- samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_clk: sd1-clk { +- samsung,pins = "gpg1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_cmd: sd1-cmd { +- samsung,pins = "gpg1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_cd: sd1-cd { +- samsung,pins = "gpg1-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus1: sd1-bus-width1 { +- samsung,pins = "gpg1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus4: sd1-bus-width4 { +- samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_clk: sd2-clk { +- samsung,pins = "gpg2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cmd: sd2-cmd { +- samsung,pins = "gpg2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cd: sd2-cd { +- samsung,pins = "gpg2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus1: sd2-bus-width1 { +- samsung,pins = "gpg2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus4: sd2-bus-width4 { +- samsung,pins = "gpg2-3", "gpg2-4", "gpg2-5", "gpg2-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus8: sd2-bus-width8 { +- samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_clk: sd3-clk { +- samsung,pins = "gpg3-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_cmd: sd3-cmd { +- samsung,pins = "gpg3-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_cd: sd3-cd { +- samsung,pins = "gpg3-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_bus1: sd3-bus-width1 { +- samsung,pins = "gpg3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd3_bus4: sd3-bus-width4 { +- samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- eint0: ext-int0 { +- samsung,pins = "gph0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- eint8: ext-int8 { +- samsung,pins = "gph1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- eint15: ext-int15 { +- samsung,pins = "gph1-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- eint16: ext-int16 { +- samsung,pins = "gph2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- eint31: ext-int31 { +- samsung,pins = "gph3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_port_a_io: cam-port-a-io { +- samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", +- "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", +- "gpe1-0", "gpe1-1", "gpe1-2", "gpe1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_port_a_clk_active: cam-port-a-clk-active { +- samsung,pins = "gpe1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_port_a_clk_idle: cam-port-a-clk-idle { +- samsung,pins = "gpe1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_port_b_io: cam-port-b-io { +- samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", +- "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", +- "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_port_b_clk_active: cam-port-b-clk-active { +- samsung,pins = "gpj1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- cam_port_b_clk_idle: cam-port-b-clk-idle { +- samsung,pins = "gpj1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lcd_ctrl: lcd-ctrl { +- samsung,pins = "gpd0-0", "gpd0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lcd_sync: lcd-sync { +- samsung,pins = "gpf0-0", "gpf0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lcd_clk: lcd-clk { +- samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- lcd_data24: lcd-data-width24 { +- samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", +- "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", +- "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", +- "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", +- "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", +- "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/s5pv210-smdkc110.dts b/scripts/dtc/include-prefixes/arm/s5pv210-smdkc110.dts +deleted file mode 100644 +index 0c623b78af72..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s5pv210-smdkc110.dts ++++ /dev/null +@@ -1,84 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's S5PV210 SoC device tree source +- * +- * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. +- * +- * Mateusz Krawczuk +- * Tomasz Figa +- * +- * Board device tree source for YIC System SMDC110 board. +- * +- * NOTE: This file is completely based on original board file for mach-smdkc110 +- * available in Linux 3.15 and intends to provide equivalent level of hardware +- * support. Due to lack of hardware, _no_ testing has been performed. +- */ +- +-/dts-v1/; +-#include +-#include "s5pv210.dtsi" +- +-/ { +- model = "YIC System SMDKC110 based on S5PC110"; +- compatible = "yic,smdkc110", "samsung,s5pv210"; +- +- chosen { +- bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; +- }; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x20000000>; +- }; +- +- pmic_ap_clk: clock-0 { +- /* Workaround for missing PMIC and its clock */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +-}; +- +-&xusbxti { +- clock-frequency = <24000000>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- audio-codec@1b { +- compatible = "wlf,wm8580"; +- reg = <0x1b>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c08"; +- reg = <0x50>; +- }; +-}; +- +-&i2s0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/s5pv210-smdkv210.dts b/scripts/dtc/include-prefixes/arm/s5pv210-smdkv210.dts +deleted file mode 100644 +index fbae768d65e2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s5pv210-smdkv210.dts ++++ /dev/null +@@ -1,246 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's S5PV210 SoC device tree source +- * +- * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. +- * +- * Mateusz Krawczuk +- * Tomasz Figa +- * +- * Board device tree source for YIC System SMDV210 board. +- * +- * NOTE: This file is completely based on original board file for mach-smdkv210 +- * available in Linux 3.15 and intends to provide equivalent level of hardware +- * support. Due to lack of hardware, _no_ testing has been performed. +- */ +- +-/dts-v1/; +-#include +-#include +-#include "s5pv210.dtsi" +- +-/ { +- model = "YIC System SMDKV210 based on S5PV210"; +- compatible = "yic,smdkv210", "samsung,s5pv210"; +- +- chosen { +- bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; +- }; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x40000000>; +- }; +- +- pmic_ap_clk: clock-0 { +- /* Workaround for missing PMIC and its clock */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- ethernet@a8000000 { +- compatible = "davicom,dm9000"; +- reg = <0xA8000000 0x2 0xA8000002 0x2>; +- interrupt-parent = <&gph1>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; +- local-mac-address = [00 00 de ad be ef]; +- davicom,no-eeprom; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 3 5000000 0>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm3_out>; +- }; +-}; +- +-&xusbxti { +- clock-frequency = <24000000>; +-}; +- +-&keypad { +- linux,input-no-autorepeat; +- wakeup-source; +- samsung,keypad-num-rows = <8>; +- samsung,keypad-num-columns = <8>; +- pinctrl-names = "default"; +- pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>, +- <&keypad_row3>, <&keypad_row4>, <&keypad_row5>, +- <&keypad_row6>, <&keypad_row7>, +- <&keypad_col0>, <&keypad_col1>, <&keypad_col2>, +- <&keypad_col3>, <&keypad_col4>, <&keypad_col5>, +- <&keypad_col6>, <&keypad_col7>; +- status = "okay"; +- +- key-1 { +- keypad,row = <0>; +- keypad,column = <3>; +- linux,code = ; +- }; +- +- key-2 { +- keypad,row = <0>; +- keypad,column = <4>; +- linux,code = ; +- }; +- +- key-3 { +- keypad,row = <0>; +- keypad,column = <5>; +- linux,code = ; +- }; +- +- key-4 { +- keypad,row = <0>; +- keypad,column = <6>; +- linux,code = ; +- }; +- +- key-5 { +- keypad,row = <0 +- >; +- keypad,column = <7>; +- linux,code = ; +- }; +- +- key-6 { +- keypad,row = <1>; +- keypad,column = <3>; +- linux,code = ; +- }; +- key-7 { +- keypad,row = <1>; +- keypad,column = <4>; +- linux,code = ; +- }; +- +- key-8 { +- keypad,row = <1>; +- keypad,column = <5>; +- linux,code = ; +- }; +- +- key-9 { +- keypad,row = <1>; +- keypad,column = <6>; +- linux,code = ; +- }; +- +- key-10 { +- keypad,row = <1>; +- keypad,column = <7>; +- linux,code = ; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&sdhci0 { +- bus-width = <4>; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&sdhci1 { +- bus-width = <4>; +- pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus1 &sd1_bus4>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&sdhci2 { +- bus-width = <4>; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&sdhci3 { +- bus-width = <4>; +- pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_cd &sd3_bus1 &sd3_bus4>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&hsotg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&fimd { +- pinctrl-0 = <&lcd_clk &lcd_data24>; +- pinctrl-names = "default"; +- status = "okay"; +- +- display-timings { +- native-mode = <&timing0>; +- +- timing0: timing { +- /* 800x480@60Hz */ +- clock-frequency = <24373920>; +- hactive = <800>; +- vactive = <480>; +- hfront-porch = <8>; +- hback-porch = <13>; +- hsync-len = <3>; +- vback-porch = <7>; +- vfront-porch = <5>; +- vsync-len = <1>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +-}; +- +-&pwm { +- samsung,pwm-outputs = <3>; +-}; +- +-&i2c0 { +- status = "okay"; +- +- audio-codec@1b { +- compatible = "wlf,wm8580"; +- reg = <0x1b>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c08"; +- reg = <0x50>; +- }; +-}; +- +-&i2s0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/s5pv210-torbreck.dts b/scripts/dtc/include-prefixes/arm/s5pv210-torbreck.dts +deleted file mode 100644 +index e18259737684..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s5pv210-torbreck.dts ++++ /dev/null +@@ -1,98 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's S5PV210 SoC device tree source +- * +- * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. +- * +- * Mateusz Krawczuk +- * Tomasz Figa +- * +- * Board device tree source for Torbreck board. +- * +- * NOTE: This file is completely based on original board file for mach-torbreck +- * available in Linux 3.15 and intends to provide equivalent level of hardware +- * support. Due to lack of hardware, _no_ testing has been performed. +- */ +- +-/dts-v1/; +-#include +-#include "s5pv210.dtsi" +- +-/ { +- model = "aESOP Torbreck based on S5PV210"; +- compatible = "aesop,torbreck", "samsung,s5pv210"; +- +- chosen { +- bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; +- }; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x20000000>; +- }; +- +- pmic_ap_clk: clock-0 { +- /* Workaround for missing PMIC and its clock */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +-}; +- +-&xusbxti { +- clock-frequency = <24000000>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&sdhci0 { +- bus-width = <4>; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&sdhci1 { +- bus-width = <4>; +- pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus1 &sd1_bus4>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&sdhci2 { +- bus-width = <4>; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&sdhci3 { +- bus-width = <4>; +- pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_cd &sd3_bus1 &sd3_bus4>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&i2s0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/s5pv210.dtsi b/scripts/dtc/include-prefixes/arm/s5pv210.dtsi +deleted file mode 100644 +index 353ba7b09a0c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/s5pv210.dtsi ++++ /dev/null +@@ -1,650 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's S5PV210 SoC device tree source +- * +- * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. +- * +- * Mateusz Krawczuk +- * Tomasz Figa +- * +- * Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210 +- * based board files can include this file and provide values for board specfic +- * bindings. +- * +- * Note: This file does not include device nodes for all the controllers in +- * S5PV210 SoC. As device tree coverage for S5PV210 increases, additional +- * nodes can be added to this file. +- */ +- +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- csis0 = &csis0; +- dmc0 = &dmc0; +- dmc1 = &dmc1; +- fimc0 = &fimc0; +- fimc1 = &fimc1; +- fimc2 = &fimc2; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2s0 = &i2s0; +- i2s1 = &i2s1; +- i2s2 = &i2s2; +- pinctrl0 = &pinctrl0; +- spi0 = &spi0; +- spi1 = &spi1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a8"; +- reg = <0>; +- }; +- }; +- +- xxti: oscillator-0 { +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- clock-output-names = "xxti"; +- #clock-cells = <0>; +- }; +- +- xusbxti: oscillator-1 { +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- clock-output-names = "xusbxti"; +- #clock-cells = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- onenand: onenand@b0600000 { +- compatible = "samsung,s5pv210-onenand"; +- reg = <0xb0600000 0x2000>, +- <0xb0000000 0x20000>, +- <0xb0040000 0x20000>; +- interrupt-parent = <&vic1>; +- interrupts = <31>; +- clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>; +- clock-names = "bus", "onenand"; +- #address-cells = <1>; +- #size-cells = <1>; +- status = "disabled"; +- }; +- +- chipid@e0000000 { +- compatible = "samsung,s5pv210-chipid"; +- reg = <0xe0000000 0x1000>; +- }; +- +- clocks: clock-controller@e0100000 { +- compatible = "samsung,s5pv210-clock"; +- reg = <0xe0100000 0x10000>; +- clock-names = "xxti", "xusbxti"; +- clocks = <&xxti>, <&xusbxti>; +- #clock-cells = <1>; +- }; +- +- pmu_syscon: syscon@e0108000 { +- compatible = "samsung-s5pv210-pmu", "syscon"; +- reg = <0xe0108000 0x8000>; +- }; +- +- pinctrl0: pinctrl@e0200000 { +- compatible = "samsung,s5pv210-pinctrl"; +- reg = <0xe0200000 0x1000>; +- interrupt-parent = <&vic0>; +- interrupts = <30>; +- +- wakeup-interrupt-controller { +- compatible = "samsung,s5pv210-wakeup-eint"; +- interrupts = <16>; +- interrupt-parent = <&vic0>; +- }; +- }; +- +- pdma0: dma@e0900000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0xe0900000 0x1000>; +- interrupt-parent = <&vic0>; +- interrupts = <19>; +- clocks = <&clocks CLK_PDMA0>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- }; +- +- pdma1: dma@e0a00000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0xe0a00000 0x1000>; +- interrupt-parent = <&vic0>; +- interrupts = <20>; +- clocks = <&clocks CLK_PDMA1>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- }; +- +- adc: adc@e1700000 { +- compatible = "samsung,s5pv210-adc"; +- reg = <0xe1700000 0x1000>; +- interrupt-parent = <&vic2>; +- interrupts = <23>, <24>; +- clocks = <&clocks CLK_TSADC>; +- clock-names = "adc"; +- #io-channel-cells = <1>; +- status = "disabled"; +- }; +- +- spi0: spi@e1300000 { +- compatible = "samsung,s5pv210-spi"; +- reg = <0xe1300000 0x1000>; +- interrupt-parent = <&vic1>; +- interrupts = <15>; +- dmas = <&pdma0 7>, <&pdma0 6>; +- dma-names = "tx", "rx"; +- clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>; +- clock-names = "spi", "spi_busclk0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_bus>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi1: spi@e1400000 { +- compatible = "samsung,s5pv210-spi"; +- reg = <0xe1400000 0x1000>; +- interrupt-parent = <&vic1>; +- interrupts = <16>; +- dmas = <&pdma1 7>, <&pdma1 6>; +- dma-names = "tx", "rx"; +- clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>; +- clock-names = "spi", "spi_busclk0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_bus>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- keypad: keypad@e1600000 { +- compatible = "samsung,s5pv210-keypad"; +- reg = <0xe1600000 0x1000>; +- interrupt-parent = <&vic2>; +- interrupts = <25>; +- clocks = <&clocks CLK_KEYIF>; +- clock-names = "keypad"; +- status = "disabled"; +- }; +- +- i2c0: i2c@e1800000 { +- compatible = "samsung,s3c2440-i2c"; +- reg = <0xe1800000 0x1000>; +- interrupt-parent = <&vic1>; +- interrupts = <14>; +- clocks = <&clocks CLK_I2C0>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_bus>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e1a00000 { +- compatible = "samsung,s3c2440-i2c"; +- reg = <0xe1a00000 0x1000>; +- interrupt-parent = <&vic1>; +- interrupts = <19>; +- clocks = <&clocks CLK_I2C2>; +- clock-names = "i2c"; +- pinctrl-0 = <&i2c2_bus>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- clk_audss: clock-controller@eee10000 { +- compatible = "samsung,s5pv210-audss-clock"; +- reg = <0xeee10000 0x1000>; +- clock-names = "hclk", "xxti", +- "fout_epll", +- "sclk_audio0"; +- clocks = <&clocks DOUT_HCLKP>, <&xxti>, +- <&clocks FOUT_EPLL>, +- <&clocks SCLK_AUDIO0>; +- #clock-cells = <1>; +- }; +- +- i2s0: i2s@eee30000 { +- compatible = "samsung,s5pv210-i2s"; +- reg = <0xeee30000 0x1000>; +- interrupt-parent = <&vic2>; +- interrupts = <16>; +- dma-names = "rx", "tx", "tx-sec"; +- dmas = <&pdma1 9>, <&pdma1 10>, <&pdma1 11>; +- clock-names = "iis", +- "i2s_opclk0", +- "i2s_opclk1"; +- clocks = <&clk_audss CLK_I2S>, +- <&clk_audss CLK_I2S>, +- <&clk_audss CLK_DOUT_AUD_BUS>; +- samsung,idma-addr = <0xc0010000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s0_bus>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- i2s1: i2s@e2100000 { +- compatible = "samsung,s3c6410-i2s"; +- reg = <0xe2100000 0x1000>; +- interrupt-parent = <&vic2>; +- interrupts = <17>; +- dma-names = "rx", "tx"; +- dmas = <&pdma1 12>, <&pdma1 13>; +- clock-names = "iis", "i2s_opclk0"; +- clocks = <&clocks CLK_I2S1>, <&clocks SCLK_AUDIO1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s1_bus>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- i2s2: i2s@e2a00000 { +- compatible = "samsung,s3c6410-i2s"; +- reg = <0xe2a00000 0x1000>; +- interrupt-parent = <&vic2>; +- interrupts = <18>; +- dma-names = "rx", "tx"; +- dmas = <&pdma1 14>, <&pdma1 15>; +- clock-names = "iis", "i2s_opclk0"; +- clocks = <&clocks CLK_I2S2>, <&clocks SCLK_AUDIO2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s2_bus>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- pwm: pwm@e2500000 { +- compatible = "samsung,s5pc100-pwm"; +- reg = <0xe2500000 0x1000>; +- interrupt-parent = <&vic0>; +- interrupts = <21>, <22>, <23>, <24>, <25>; +- clock-names = "timers"; +- clocks = <&clocks CLK_PWM>; +- #pwm-cells = <3>; +- }; +- +- watchdog: watchdog@e2700000 { +- compatible = "samsung,s3c6410-wdt"; +- reg = <0xe2700000 0x1000>; +- interrupt-parent = <&vic0>; +- interrupts = <26>; +- clock-names = "watchdog"; +- clocks = <&clocks CLK_WDT>; +- }; +- +- rtc: rtc@e2800000 { +- compatible = "samsung,s3c6410-rtc"; +- reg = <0xe2800000 0x100>; +- interrupt-parent = <&vic0>; +- interrupts = <28>, <29>; +- clocks = <&clocks CLK_RTC>; +- clock-names = "rtc"; +- status = "disabled"; +- }; +- +- uart0: serial@e2900000 { +- compatible = "samsung,s5pv210-uart"; +- reg = <0xe2900000 0x400>; +- interrupt-parent = <&vic1>; +- interrupts = <10>; +- clock-names = "uart", "clk_uart_baud0", +- "clk_uart_baud1"; +- clocks = <&clocks CLK_UART0>, <&clocks CLK_UART0>, +- <&clocks SCLK_UART0>; +- status = "disabled"; +- }; +- +- uart1: serial@e2900400 { +- compatible = "samsung,s5pv210-uart"; +- reg = <0xe2900400 0x400>; +- interrupt-parent = <&vic1>; +- interrupts = <11>; +- clock-names = "uart", "clk_uart_baud0", +- "clk_uart_baud1"; +- clocks = <&clocks CLK_UART1>, <&clocks CLK_UART1>, +- <&clocks SCLK_UART1>; +- status = "disabled"; +- }; +- +- uart2: serial@e2900800 { +- compatible = "samsung,s5pv210-uart"; +- reg = <0xe2900800 0x400>; +- interrupt-parent = <&vic1>; +- interrupts = <12>; +- clock-names = "uart", "clk_uart_baud0", +- "clk_uart_baud1"; +- clocks = <&clocks CLK_UART2>, <&clocks CLK_UART2>, +- <&clocks SCLK_UART2>; +- status = "disabled"; +- }; +- +- uart3: serial@e2900c00 { +- compatible = "samsung,s5pv210-uart"; +- reg = <0xe2900c00 0x400>; +- interrupt-parent = <&vic1>; +- interrupts = <13>; +- clock-names = "uart", "clk_uart_baud0", +- "clk_uart_baud1"; +- clocks = <&clocks CLK_UART3>, <&clocks CLK_UART3>, +- <&clocks SCLK_UART3>; +- status = "disabled"; +- }; +- +- sdhci0: sdhci@eb000000 { +- compatible = "samsung,s3c6410-sdhci"; +- reg = <0xeb000000 0x100000>; +- interrupt-parent = <&vic1>; +- interrupts = <26>; +- clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; +- clocks = <&clocks CLK_HSMMC0>, <&clocks CLK_HSMMC0>, +- <&clocks SCLK_MMC0>; +- status = "disabled"; +- }; +- +- sdhci1: sdhci@eb100000 { +- compatible = "samsung,s3c6410-sdhci"; +- reg = <0xeb100000 0x100000>; +- interrupt-parent = <&vic1>; +- interrupts = <27>; +- clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; +- clocks = <&clocks CLK_HSMMC1>, <&clocks CLK_HSMMC1>, +- <&clocks SCLK_MMC1>; +- status = "disabled"; +- }; +- +- sdhci2: sdhci@eb200000 { +- compatible = "samsung,s3c6410-sdhci"; +- reg = <0xeb200000 0x100000>; +- interrupt-parent = <&vic1>; +- interrupts = <28>; +- clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; +- clocks = <&clocks CLK_HSMMC2>, <&clocks CLK_HSMMC2>, +- <&clocks SCLK_MMC2>; +- status = "disabled"; +- }; +- +- sdhci3: sdhci@eb300000 { +- compatible = "samsung,s3c6410-sdhci"; +- reg = <0xeb300000 0x100000>; +- interrupt-parent = <&vic3>; +- interrupts = <2>; +- clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.3"; +- clocks = <&clocks CLK_HSMMC3>, <&clocks CLK_HSMMC3>, +- <&clocks SCLK_MMC3>; +- status = "disabled"; +- }; +- +- hsotg: hsotg@ec000000 { +- compatible = "samsung,s3c6400-hsotg"; +- reg = <0xec000000 0x20000>; +- interrupt-parent = <&vic1>; +- interrupts = <24>; +- clocks = <&clocks CLK_USB_OTG>; +- clock-names = "otg"; +- phy-names = "usb2-phy"; +- phys = <&usbphy 0>; +- status = "disabled"; +- }; +- +- usbphy: usbphy@ec100000 { +- compatible = "samsung,s5pv210-usb2-phy"; +- reg = <0xec100000 0x100>; +- samsung,pmureg-phandle = <&pmu_syscon>; +- clocks = <&clocks CLK_USB_OTG>, <&xusbxti>; +- clock-names = "phy", "ref"; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- ehci: ehci@ec200000 { +- compatible = "samsung,exynos4210-ehci"; +- reg = <0xec200000 0x100>; +- interrupts = <23>; +- interrupt-parent = <&vic1>; +- clocks = <&clocks CLK_USB_HOST>; +- clock-names = "usbhost"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- port@0 { +- reg = <0>; +- phys = <&usbphy 1>; +- }; +- }; +- +- ohci: ohci@ec300000 { +- compatible = "samsung,exynos4210-ohci"; +- reg = <0xec300000 0x100>; +- interrupts = <23>; +- interrupt-parent = <&vic1>; +- clocks = <&clocks CLK_USB_HOST>; +- clock-names = "usbhost"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- port@0 { +- reg = <0>; +- phys = <&usbphy 1>; +- }; +- }; +- +- mfc: codec@f1700000 { +- compatible = "samsung,mfc-v5"; +- reg = <0xf1700000 0x10000>; +- interrupt-parent = <&vic2>; +- interrupts = <14>; +- clocks = <&clocks DOUT_MFC>, <&clocks CLK_MFC>; +- clock-names = "sclk_mfc", "mfc"; +- }; +- +- vic0: interrupt-controller@f2000000 { +- compatible = "arm,pl192-vic"; +- interrupt-controller; +- reg = <0xf2000000 0x1000>; +- #interrupt-cells = <1>; +- }; +- +- vic1: interrupt-controller@f2100000 { +- compatible = "arm,pl192-vic"; +- interrupt-controller; +- reg = <0xf2100000 0x1000>; +- #interrupt-cells = <1>; +- }; +- +- vic2: interrupt-controller@f2200000 { +- compatible = "arm,pl192-vic"; +- interrupt-controller; +- reg = <0xf2200000 0x1000>; +- #interrupt-cells = <1>; +- }; +- +- vic3: interrupt-controller@f2300000 { +- compatible = "arm,pl192-vic"; +- interrupt-controller; +- reg = <0xf2300000 0x1000>; +- #interrupt-cells = <1>; +- }; +- +- fimd: fimd@f8000000 { +- compatible = "samsung,s5pv210-fimd"; +- interrupt-parent = <&vic2>; +- reg = <0xf8000000 0x20000>; +- interrupt-names = "fifo", "vsync", "lcd_sys"; +- interrupts = <0>, <1>, <2>; +- clocks = <&clocks SCLK_FIMD>, <&clocks CLK_FIMD>; +- clock-names = "sclk_fimd", "fimd"; +- status = "disabled"; +- }; +- +- dmc0: dmc@f0000000 { +- compatible = "samsung,s5pv210-dmc"; +- reg = <0xf0000000 0x1000>; +- }; +- +- dmc1: dmc@f1400000 { +- compatible = "samsung,s5pv210-dmc"; +- reg = <0xf1400000 0x1000>; +- }; +- +- g2d: g2d@fa000000 { +- compatible = "samsung,s5pv210-g2d"; +- reg = <0xfa000000 0x1000>; +- interrupt-parent = <&vic2>; +- interrupts = <9>; +- clocks = <&clocks DOUT_G2D>, <&clocks CLK_G2D>; +- clock-names = "sclk_fimg2d", "fimg2d"; +- }; +- +- mdma1: mdma@fa200000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0xfa200000 0x1000>; +- interrupt-parent = <&vic0>; +- interrupts = <18>; +- clocks = <&clocks CLK_MDMA>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <1>; +- }; +- +- rotator: rotator@fa300000 { +- compatible = "samsung,s5pv210-rotator"; +- reg = <0xfa300000 0x1000>; +- interrupt-parent = <&vic2>; +- interrupts = <4>; +- clocks = <&clocks CLK_ROTATOR>; +- clock-names = "rotator"; +- }; +- +- i2c1: i2c@fab00000 { +- compatible = "samsung,s3c2440-i2c"; +- reg = <0xfab00000 0x1000>; +- interrupt-parent = <&vic2>; +- interrupts = <13>; +- clocks = <&clocks CLK_I2C1>; +- clock-names = "i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_bus>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- camera: camera { +- compatible = "samsung,fimc", "simple-bus"; +- pinctrl-names = "default"; +- pinctrl-0 = <>; +- clocks = <&clocks SCLK_CAM0>, <&clocks SCLK_CAM1>; +- clock-names = "sclk_cam0", "sclk_cam1"; +- #address-cells = <1>; +- #size-cells = <1>; +- #clock-cells = <1>; +- clock-output-names = "cam_a_clkout", "cam_b_clkout"; +- ranges; +- +- csis0: csis@fa600000 { +- compatible = "samsung,s5pv210-csis"; +- reg = <0xfa600000 0x4000>; +- interrupt-parent = <&vic2>; +- interrupts = <29>; +- clocks = <&clocks CLK_CSIS>, +- <&clocks SCLK_CSIS>; +- clock-names = "clk_csis", +- "sclk_csis"; +- bus-width = <4>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- fimc0: fimc@fb200000 { +- compatible = "samsung,s5pv210-fimc"; +- reg = <0xfb200000 0x1000>; +- interrupts = <5>; +- interrupt-parent = <&vic2>; +- clocks = <&clocks CLK_FIMC0>, +- <&clocks SCLK_FIMC0>; +- clock-names = "fimc", +- "sclk_fimc"; +- samsung,pix-limits = <4224 8192 1920 4224>; +- samsung,min-pix-alignment = <16 8>; +- samsung,cam-if; +- }; +- +- fimc1: fimc@fb300000 { +- compatible = "samsung,s5pv210-fimc"; +- reg = <0xfb300000 0x1000>; +- interrupt-parent = <&vic2>; +- interrupts = <6>; +- clocks = <&clocks CLK_FIMC1>, +- <&clocks SCLK_FIMC1>; +- clock-names = "fimc", +- "sclk_fimc"; +- samsung,pix-limits = <4224 8192 1920 4224>; +- samsung,min-pix-alignment = <1 1>; +- samsung,mainscaler-ext; +- samsung,cam-if; +- samsung,lcd-wb; +- }; +- +- fimc2: fimc@fb400000 { +- compatible = "samsung,s5pv210-fimc"; +- reg = <0xfb400000 0x1000>; +- interrupt-parent = <&vic2>; +- interrupts = <7>; +- clocks = <&clocks CLK_FIMC2>, +- <&clocks SCLK_FIMC2>; +- clock-names = "fimc", +- "sclk_fimc"; +- samsung,pix-limits = <1920 8192 1280 1920>; +- samsung,min-pix-alignment = <16 8>; +- samsung,rotators = <0>; +- samsung,cam-if; +- }; +- }; +- +- jpeg_codec: jpeg-codec@fb600000 { +- compatible = "samsung,s5pv210-jpeg"; +- reg = <0xfb600000 0x1000>; +- interrupt-parent = <&vic2>; +- interrupts = <8>; +- clocks = <&clocks CLK_JPEG>; +- clock-names = "jpeg"; +- }; +- }; +-}; +- +-#include "s5pv210-pinctrl.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/sam9x60.dtsi b/scripts/dtc/include-prefixes/arm/sam9x60.dtsi +deleted file mode 100644 +index ec45ced3cde6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sam9x60.dtsi ++++ /dev/null +@@ -1,733 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC +- * +- * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries +- * +- * Author: Sandeep Sheriker M +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Microchip SAM9X60 SoC"; +- compatible = "microchip,sam9x60"; +- interrupt-parent = <&aic>; +- +- aliases { +- serial0 = &dbgu; +- gpio0 = &pioA; +- gpio1 = &pioB; +- gpio2 = &pioC; +- gpio3 = &pioD; +- tcb0 = &tcb0; +- tcb1 = &tcb1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,arm926ej-s"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x10000000>; +- }; +- +- clocks { +- slow_xtal: slow_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- }; +- +- main_xtal: main_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- }; +- }; +- +- sram: sram@300000 { +- compatible = "mmio-sram"; +- reg = <0x00300000 0x100000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00300000 0x100000>; +- }; +- +- ahb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- usb0: gadget@500000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "microchip,sam9x60-udc"; +- reg = <0x00500000 0x100000 +- 0xf803c000 0x400>; +- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>; +- clock-names = "pclk", "hclk"; +- assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; +- assigned-clock-rates = <480000000>; +- status = "disabled"; +- }; +- +- usb1: ohci@600000 { +- compatible = "atmel,at91rm9200-ohci", "usb-ohci"; +- reg = <0x00600000 0x100000>; +- interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; +- clock-names = "ohci_clk", "hclk", "uhpck"; +- status = "disabled"; +- }; +- +- usb2: ehci@700000 { +- compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; +- reg = <0x00700000 0x100000>; +- interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; +- clock-names = "usb_clk", "ehci_clk"; +- assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; +- assigned-clock-rates = <480000000>; +- status = "disabled"; +- }; +- +- ebi: ebi@10000000 { +- compatible = "microchip,sam9x60-ebi"; +- #address-cells = <2>; +- #size-cells = <1>; +- atmel,smc = <&smc>; +- microchip,sfr = <&sfr>; +- reg = <0x10000000 0x60000000>; +- ranges = <0x0 0x0 0x10000000 0x10000000 +- 0x1 0x0 0x20000000 0x10000000 +- 0x2 0x0 0x30000000 0x10000000 +- 0x3 0x0 0x40000000 0x10000000 +- 0x4 0x0 0x50000000 0x10000000 +- 0x5 0x0 0x60000000 0x10000000>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- status = "disabled"; +- +- nand_controller: nand-controller { +- compatible = "microchip,sam9x60-nand-controller"; +- ecc-engine = <&pmecc>; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- }; +- }; +- +- sdmmc0: sdio-host@80000000 { +- compatible = "microchip,sam9x60-sdhci"; +- reg = <0x80000000 0x300>; +- interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; +- clock-names = "hclock", "multclk"; +- assigned-clocks = <&pmc PMC_TYPE_GCK 12>; +- assigned-clock-rates = <100000000>; +- status = "disabled"; +- }; +- +- sdmmc1: sdio-host@90000000 { +- compatible = "microchip,sam9x60-sdhci"; +- reg = <0x90000000 0x300>; +- interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; +- clock-names = "hclock", "multclk"; +- assigned-clocks = <&pmc PMC_TYPE_GCK 26>; +- assigned-clock-rates = <100000000>; +- status = "disabled"; +- }; +- +- apb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- flx4: flexcom@f0000000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xf0000000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf0000000 0x800>; +- status = "disabled"; +- }; +- +- flx5: flexcom@f0004000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xf0004000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf0004000 0x800>; +- status = "disabled"; +- }; +- +- dma0: dma-controller@f0008000 { +- compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma"; +- reg = <0xf0008000 0x1000>; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; +- #dma-cells = <1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; +- clock-names = "dma_clk"; +- }; +- +- ssc: ssc@f0010000 { +- compatible = "atmel,at91sam9g45-ssc"; +- reg = <0xf0010000 0x4000>; +- interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(38))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(39))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; +- clock-names = "pclk"; +- status = "disabled"; +- }; +- +- qspi: spi@f0014000 { +- compatible = "microchip,sam9x60-qspi"; +- reg = <0xf0014000 0x100>, <0x70000000 0x10000000>; +- reg-names = "qspi_base", "qspi_mmap"; +- interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(26))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(27))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>; +- clock-names = "pclk", "qspick"; +- atmel,pmc = <&pmc>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2s: i2s@f001c000 { +- compatible = "microchip,sam9x60-i2smcc"; +- reg = <0xf001c000 0x100>; +- interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(36))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(37))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; +- clock-names = "pclk", "gclk"; +- status = "disabled"; +- }; +- +- flx11: flexcom@f0020000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xf0020000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf0020000 0x800>; +- status = "disabled"; +- }; +- +- flx12: flexcom@f0024000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xf0024000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf0024000 0x800>; +- status = "disabled"; +- }; +- +- pit64b: timer@f0028000 { +- compatible = "microchip,sam9x60-pit64b"; +- reg = <0xf0028000 0x100>; +- interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; +- clock-names = "pclk", "gclk"; +- }; +- +- sha: sha@f002c000 { +- compatible = "atmel,at91sam9g46-sha"; +- reg = <0xf002c000 0x100>; +- interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(34))>; +- dma-names = "tx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; +- clock-names = "sha_clk"; +- status = "okay"; +- }; +- +- trng: trng@f0030000 { +- compatible = "microchip,sam9x60-trng"; +- reg = <0xf0030000 0x100>; +- interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; +- status = "okay"; +- }; +- +- aes: aes@f0034000 { +- compatible = "atmel,at91sam9g46-aes"; +- reg = <0xf0034000 0x100>; +- interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(32))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(33))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; +- clock-names = "aes_clk"; +- status = "okay"; +- }; +- +- tdes: tdes@f0038000 { +- compatible = "atmel,at91sam9g46-tdes"; +- reg = <0xf0038000 0x100>; +- interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(31))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(30))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; +- clock-names = "tdes_clk"; +- status = "okay"; +- }; +- +- classd: classd@f003c000 { +- compatible = "atmel,sama5d2-classd"; +- reg = <0xf003c000 0x100>; +- interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(35))>; +- dma-names = "tx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; +- clock-names = "pclk", "gclk"; +- status = "disabled"; +- }; +- +- can0: can@f8000000 { +- compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can"; +- reg = <0xf8000000 0x300>; +- interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; +- clock-names = "can_clk"; +- status = "disabled"; +- }; +- +- can1: can@f8004000 { +- compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can"; +- reg = <0xf8004000 0x300>; +- interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; +- clock-names = "can_clk"; +- status = "disabled"; +- }; +- +- tcb0: timer@f8008000 { +- compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xf8008000 0x100>; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>; +- clock-names = "t0_clk", "slow_clk"; +- }; +- +- tcb1: timer@f800c000 { +- compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xf800c000 0x100>; +- interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>; +- clock-names = "t0_clk", "slow_clk"; +- }; +- +- flx6: flexcom@f8010000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xf8010000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf8010000 0x800>; +- status = "disabled"; +- }; +- +- flx7: flexcom@f8014000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xf8014000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf8014000 0x800>; +- status = "disabled"; +- }; +- +- flx8: flexcom@f8018000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xf8018000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf8018000 0x800>; +- status = "disabled"; +- }; +- +- flx0: flexcom@f801c000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xf801c000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf801c000 0x800>; +- status = "disabled"; +- }; +- +- flx1: flexcom@f8020000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xf8020000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf8020000 0x800>; +- status = "disabled"; +- }; +- +- flx2: flexcom@f8024000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xf8024000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf8024000 0x800>; +- status = "disabled"; +- }; +- +- flx3: flexcom@f8028000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xf8028000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf8028000 0x800>; +- status = "disabled"; +- }; +- +- macb0: ethernet@f802c000 { +- compatible = "cdns,sam9x60-macb", "cdns,macb"; +- reg = <0xf802c000 0x1000>; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>; +- clock-names = "hclk", "pclk"; +- status = "disabled"; +- }; +- +- macb1: ethernet@f8030000 { +- compatible = "cdns,sam9x60-macb", "cdns,macb"; +- reg = <0xf8030000 0x1000>; +- interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>; +- clock-names = "hclk", "pclk"; +- status = "disabled"; +- }; +- +- pwm0: pwm@f8034000 { +- compatible = "microchip,sam9x60-pwm"; +- reg = <0xf8034000 0x300>; +- interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; +- #pwm-cells = <3>; +- status="disabled"; +- }; +- +- hlcdc: hlcdc@f8038000 { +- compatible = "microchip,sam9x60-hlcdc"; +- reg = <0xf8038000 0x4000>; +- interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>; +- clock-names = "periph_clk","sys_clk", "slow_clk"; +- assigned-clocks = <&pmc PMC_TYPE_GCK 25>; +- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>; +- status = "disabled"; +- +- hlcdc-display-controller { +- compatible = "atmel,hlcdc-display-controller"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- }; +- +- hlcdc_pwm: hlcdc-pwm { +- compatible = "atmel,hlcdc-pwm"; +- #pwm-cells = <3>; +- }; +- }; +- +- flx9: flexcom@f8040000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xf8040000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf8040000 0x800>; +- status = "disabled"; +- }; +- +- flx10: flexcom@f8044000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xf8044000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf8044000 0x800>; +- status = "disabled"; +- }; +- +- isi: isi@f8048000 { +- compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi"; +- reg = <0xf8048000 0x100>; +- interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; +- clock-names = "isi_clk"; +- status = "disabled"; +- port { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- adc: adc@f804c000 { +- compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc"; +- reg = <0xf804c000 0x100>; +- interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; +- clock-names = "adc_clk"; +- dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>; +- dma-names = "rx"; +- atmel,min-sample-rate-hz = <200000>; +- atmel,max-sample-rate-hz = <20000000>; +- atmel,startup-time-ms = <4>; +- atmel,trigger-edge-type = ; +- #io-channel-cells = <1>; +- status = "disabled"; +- }; +- +- sfr: sfr@f8050000 { +- compatible = "microchip,sam9x60-sfr", "syscon"; +- reg = <0xf8050000 0x100>; +- }; +- +- matrix: matrix@ffffde00 { +- compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon"; +- reg = <0xffffde00 0x200>; +- }; +- +- pmecc: ecc-engine@ffffe000 { +- compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc"; +- reg = <0xffffe000 0x300>, +- <0xffffe600 0x100>; +- }; +- +- mpddrc: mpddrc@ffffe800 { +- compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc"; +- reg = <0xffffe800 0x200>; +- clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>; +- clock-names = "ddrck", "mpddr"; +- }; +- +- smc: smc@ffffea00 { +- compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon"; +- reg = <0xffffea00 0x100>; +- }; +- +- aic: interrupt-controller@fffff100 { +- compatible = "microchip,sam9x60-aic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0xfffff100 0x100>; +- atmel,external-irqs = <31>; +- }; +- +- dbgu: serial@fffff200 { +- compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; +- reg = <0xfffff200 0x200>; +- interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(28))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(29))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- pinctrl: pinctrl@fffff400 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; +- ranges = <0xfffff400 0xfffff400 0x800>; +- +- /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */ +- atmel,mux-mask = < +- /* A B C */ +- 0xffffffff 0xffe03fff 0xef00019d /* pioA */ +- 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */ +- 0xffffffff 0xffffffff 0xf83fffff /* pioC */ +- 0x003fffff 0x003f8000 0x00000000 /* pioD */ +- >; +- +- pioA: gpio@fffff400 { +- compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfffff400 0x200>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; +- }; +- +- pioB: gpio@fffff600 { +- compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfffff600 0x200>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- #gpio-lines = <26>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; +- }; +- +- pioC: gpio@fffff800 { +- compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfffff800 0x200>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; +- }; +- +- pioD: gpio@fffffa00 { +- compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfffffa00 0x200>; +- interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- #gpio-lines = <22>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; +- }; +- }; +- +- pmc: pmc@fffffc00 { +- compatible = "microchip,sam9x60-pmc", "syscon"; +- reg = <0xfffffc00 0x200>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- #clock-cells = <2>; +- clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; +- clock-names = "td_slck", "md_slck", "main_xtal"; +- }; +- +- reset_controller: rstc@fffffe00 { +- compatible = "microchip,sam9x60-rstc"; +- reg = <0xfffffe00 0x10>; +- clocks = <&clk32k 0>; +- }; +- +- shutdown_controller: shdwc@fffffe10 { +- compatible = "microchip,sam9x60-shdwc"; +- reg = <0xfffffe10 0x10>; +- clocks = <&clk32k 0>; +- #address-cells = <1>; +- #size-cells = <0>; +- atmel,wakeup-rtc-timer; +- atmel,wakeup-rtt-timer; +- status = "disabled"; +- }; +- +- rtt: rtt@fffffe20 { +- compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; +- reg = <0xfffffe20 0x20>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&clk32k 0>; +- }; +- +- pit: timer@fffffe40 { +- compatible = "atmel,at91sam9260-pit"; +- reg = <0xfffffe40 0x10>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- }; +- +- clk32k: sckc@fffffe50 { +- compatible = "microchip,sam9x60-sckc"; +- reg = <0xfffffe50 0x4>; +- clocks = <&slow_xtal>; +- #clock-cells = <1>; +- }; +- +- gpbr: syscon@fffffe60 { +- compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon"; +- reg = <0xfffffe60 0x10>; +- }; +- +- rtc: rtc@fffffea8 { +- compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc"; +- reg = <0xfffffea8 0x100>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&clk32k 0>; +- }; +- +- watchdog: watchdog@ffffff80 { +- compatible = "microchip,sam9x60-wdt"; +- reg = <0xffffff80 0x24>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&clk32k 0>; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d2-pinfunc.h b/scripts/dtc/include-prefixes/arm/sama5d2-pinfunc.h +deleted file mode 100644 +index 28a2e45752fe..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d2-pinfunc.h ++++ /dev/null +@@ -1,881 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#define PINMUX_PIN(no, func, ioset) \ +-(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20)) +- +-#define PIN_PA0 0 +-#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0) +-#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1) +-#define PIN_PA0__QSPI0_SCK PINMUX_PIN(PIN_PA0, 2, 1) +-#define PIN_PA0__D0 PINMUX_PIN(PIN_PA0, 6, 2) +-#define PIN_PA1 1 +-#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0) +-#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1) +-#define PIN_PA1__QSPI0_CS PINMUX_PIN(PIN_PA1, 2, 1) +-#define PIN_PA1__D1 PINMUX_PIN(PIN_PA1, 6, 2) +-#define PIN_PA2 2 +-#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0) +-#define PIN_PA2__SDMMC0_DAT0 PINMUX_PIN(PIN_PA2, 1, 1) +-#define PIN_PA2__QSPI0_IO0 PINMUX_PIN(PIN_PA2, 2, 1) +-#define PIN_PA2__D2 PINMUX_PIN(PIN_PA2, 6, 2) +-#define PIN_PA3 3 +-#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0) +-#define PIN_PA3__SDMMC0_DAT1 PINMUX_PIN(PIN_PA3, 1, 1) +-#define PIN_PA3__QSPI0_IO1 PINMUX_PIN(PIN_PA3, 2, 1) +-#define PIN_PA3__D3 PINMUX_PIN(PIN_PA3, 6, 2) +-#define PIN_PA4 4 +-#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0) +-#define PIN_PA4__SDMMC0_DAT2 PINMUX_PIN(PIN_PA4, 1, 1) +-#define PIN_PA4__QSPI0_IO2 PINMUX_PIN(PIN_PA4, 2, 1) +-#define PIN_PA4__D4 PINMUX_PIN(PIN_PA4, 6, 2) +-#define PIN_PA5 5 +-#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0) +-#define PIN_PA5__SDMMC0_DAT3 PINMUX_PIN(PIN_PA5, 1, 1) +-#define PIN_PA5__QSPI0_IO3 PINMUX_PIN(PIN_PA5, 2, 1) +-#define PIN_PA5__D5 PINMUX_PIN(PIN_PA5, 6, 2) +-#define PIN_PA6 6 +-#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0) +-#define PIN_PA6__SDMMC0_DAT4 PINMUX_PIN(PIN_PA6, 1, 1) +-#define PIN_PA6__QSPI1_SCK PINMUX_PIN(PIN_PA6, 2, 1) +-#define PIN_PA6__TIOA5 PINMUX_PIN(PIN_PA6, 4, 1) +-#define PIN_PA6__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA6, 5, 1) +-#define PIN_PA6__D6 PINMUX_PIN(PIN_PA6, 6, 2) +-#define PIN_PA7 7 +-#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0) +-#define PIN_PA7__SDMMC0_DAT5 PINMUX_PIN(PIN_PA7, 1, 1) +-#define PIN_PA7__QSPI1_IO0 PINMUX_PIN(PIN_PA7, 2, 1) +-#define PIN_PA7__TIOB5 PINMUX_PIN(PIN_PA7, 4, 1) +-#define PIN_PA7__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA7, 5, 1) +-#define PIN_PA7__D7 PINMUX_PIN(PIN_PA7, 6, 2) +-#define PIN_PA8 8 +-#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0) +-#define PIN_PA8__SDMMC0_DAT6 PINMUX_PIN(PIN_PA8, 1, 1) +-#define PIN_PA8__QSPI1_IO1 PINMUX_PIN(PIN_PA8, 2, 1) +-#define PIN_PA8__TCLK5 PINMUX_PIN(PIN_PA8, 4, 1) +-#define PIN_PA8__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA8, 5, 1) +-#define PIN_PA8__NWE_NANDWE PINMUX_PIN(PIN_PA8, 6, 2) +-#define PIN_PA9 9 +-#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0) +-#define PIN_PA9__SDMMC0_DAT7 PINMUX_PIN(PIN_PA9, 1, 1) +-#define PIN_PA9__QSPI1_IO2 PINMUX_PIN(PIN_PA9, 2, 1) +-#define PIN_PA9__TIOA4 PINMUX_PIN(PIN_PA9, 4, 1) +-#define PIN_PA9__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA9, 5, 1) +-#define PIN_PA9__NCS3 PINMUX_PIN(PIN_PA9, 6, 2) +-#define PIN_PA10 10 +-#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0) +-#define PIN_PA10__SDMMC0_RSTN PINMUX_PIN(PIN_PA10, 1, 1) +-#define PIN_PA10__QSPI1_IO3 PINMUX_PIN(PIN_PA10, 2, 1) +-#define PIN_PA10__TIOB4 PINMUX_PIN(PIN_PA10, 4, 1) +-#define PIN_PA10__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA10, 5, 1) +-#define PIN_PA10__A21_NANDALE PINMUX_PIN(PIN_PA10, 6, 2) +-#define PIN_PA11 11 +-#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0) +-#define PIN_PA11__SDMMC0_VDDSEL PINMUX_PIN(PIN_PA11, 1, 1) +-#define PIN_PA11__QSPI1_CS PINMUX_PIN(PIN_PA11, 2, 1) +-#define PIN_PA11__TCLK4 PINMUX_PIN(PIN_PA11, 4, 1) +-#define PIN_PA11__A22_NANDCLE PINMUX_PIN(PIN_PA11, 6, 2) +-#define PIN_PA12 12 +-#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0) +-#define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1) +-#define PIN_PA12__IRQ PINMUX_PIN(PIN_PA12, 2, 1) +-#define PIN_PA12__NRD_NANDOE PINMUX_PIN(PIN_PA12, 6, 2) +-#define PIN_PA13 13 +-#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0) +-#define PIN_PA13__SDMMC0_CD PINMUX_PIN(PIN_PA13, 1, 1) +-#define PIN_PA13__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA13, 5, 1) +-#define PIN_PA13__D8 PINMUX_PIN(PIN_PA13, 6, 2) +-#define PIN_PA14 14 +-#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0) +-#define PIN_PA14__SPI0_SPCK PINMUX_PIN(PIN_PA14, 1, 1) +-#define PIN_PA14__TK1 PINMUX_PIN(PIN_PA14, 2, 1) +-#define PIN_PA14__QSPI0_SCK PINMUX_PIN(PIN_PA14, 3, 2) +-#define PIN_PA14__I2SC1_MCK PINMUX_PIN(PIN_PA14, 4, 2) +-#define PIN_PA14__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA14, 5, 1) +-#define PIN_PA14__D9 PINMUX_PIN(PIN_PA14, 6, 2) +-#define PIN_PA15 15 +-#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) +-#define PIN_PA15__SPI0_MOSI PINMUX_PIN(PIN_PA15, 1, 1) +-#define PIN_PA15__TF1 PINMUX_PIN(PIN_PA15, 2, 1) +-#define PIN_PA15__QSPI0_CS PINMUX_PIN(PIN_PA15, 3, 2) +-#define PIN_PA15__I2SC1_CK PINMUX_PIN(PIN_PA15, 4, 2) +-#define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 5, 1) +-#define PIN_PA15__D10 PINMUX_PIN(PIN_PA15, 6, 2) +-#define PIN_PA16 16 +-#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0) +-#define PIN_PA16__SPI0_MISO PINMUX_PIN(PIN_PA16, 1, 1) +-#define PIN_PA16__TD1 PINMUX_PIN(PIN_PA16, 2, 1) +-#define PIN_PA16__QSPI0_IO0 PINMUX_PIN(PIN_PA16, 3, 2) +-#define PIN_PA16__I2SC1_WS PINMUX_PIN(PIN_PA16, 4, 2) +-#define PIN_PA16__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA16, 5, 1) +-#define PIN_PA16__D11 PINMUX_PIN(PIN_PA16, 6, 2) +-#define PIN_PA17 17 +-#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0) +-#define PIN_PA17__SPI0_NPCS0 PINMUX_PIN(PIN_PA17, 1, 1) +-#define PIN_PA17__RD1 PINMUX_PIN(PIN_PA17, 2, 1) +-#define PIN_PA17__QSPI0_IO1 PINMUX_PIN(PIN_PA17, 3, 2) +-#define PIN_PA17__I2SC1_DI0 PINMUX_PIN(PIN_PA17, 4, 2) +-#define PIN_PA17__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA17, 5, 1) +-#define PIN_PA17__D12 PINMUX_PIN(PIN_PA17, 6, 2) +-#define PIN_PA18 18 +-#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0) +-#define PIN_PA18__SPI0_NPCS1 PINMUX_PIN(PIN_PA18, 1, 1) +-#define PIN_PA18__RK1 PINMUX_PIN(PIN_PA18, 2, 1) +-#define PIN_PA18__QSPI0_IO2 PINMUX_PIN(PIN_PA18, 3, 2) +-#define PIN_PA18__I2SC1_DO0 PINMUX_PIN(PIN_PA18, 4, 2) +-#define PIN_PA18__SDMMC1_DAT0 PINMUX_PIN(PIN_PA18, 5, 1) +-#define PIN_PA18__D13 PINMUX_PIN(PIN_PA18, 6, 2) +-#define PIN_PA19 19 +-#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0) +-#define PIN_PA19__SPI0_NPCS2 PINMUX_PIN(PIN_PA19, 1, 1) +-#define PIN_PA19__RF1 PINMUX_PIN(PIN_PA19, 2, 1) +-#define PIN_PA19__QSPI0_IO3 PINMUX_PIN(PIN_PA19, 3, 2) +-#define PIN_PA19__TIOA0 PINMUX_PIN(PIN_PA19, 4, 1) +-#define PIN_PA19__SDMMC1_DAT1 PINMUX_PIN(PIN_PA19, 5, 1) +-#define PIN_PA19__D14 PINMUX_PIN(PIN_PA19, 6, 2) +-#define PIN_PA20 20 +-#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0) +-#define PIN_PA20__SPI0_NPCS3 PINMUX_PIN(PIN_PA20, 1, 1) +-#define PIN_PA20__TIOB0 PINMUX_PIN(PIN_PA20, 4, 1) +-#define PIN_PA20__SDMMC1_DAT2 PINMUX_PIN(PIN_PA20, 5, 1) +-#define PIN_PA20__D15 PINMUX_PIN(PIN_PA20, 6, 2) +-#define PIN_PA21 21 +-#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0) +-#define PIN_PA21__IRQ PINMUX_PIN(PIN_PA21, 1, 2) +-#define PIN_PA21__PCK2 PINMUX_PIN(PIN_PA21, 2, 3) +-#define PIN_PA21__TCLK0 PINMUX_PIN(PIN_PA21, 4, 1) +-#define PIN_PA21__SDMMC1_DAT3 PINMUX_PIN(PIN_PA21, 5, 1) +-#define PIN_PA21__NANDRDY PINMUX_PIN(PIN_PA21, 6, 2) +-#define PIN_PA22 22 +-#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0) +-#define PIN_PA22__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA22, 1, 1) +-#define PIN_PA22__D0 PINMUX_PIN(PIN_PA22, 2, 1) +-#define PIN_PA22__TCK PINMUX_PIN(PIN_PA22, 3, 4) +-#define PIN_PA22__SPI1_SPCK PINMUX_PIN(PIN_PA22, 4, 2) +-#define PIN_PA22__SDMMC1_CK PINMUX_PIN(PIN_PA22, 5, 1) +-#define PIN_PA22__QSPI0_SCK PINMUX_PIN(PIN_PA22, 6, 3) +-#define PIN_PA23 23 +-#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0) +-#define PIN_PA23__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA23, 1, 1) +-#define PIN_PA23__D1 PINMUX_PIN(PIN_PA23, 2, 1) +-#define PIN_PA23__TDI PINMUX_PIN(PIN_PA23, 3, 4) +-#define PIN_PA23__SPI1_MOSI PINMUX_PIN(PIN_PA23, 4, 2) +-#define PIN_PA23__QSPI0_CS PINMUX_PIN(PIN_PA23, 6, 3) +-#define PIN_PA24 24 +-#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0) +-#define PIN_PA24__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA24, 1, 1) +-#define PIN_PA24__D2 PINMUX_PIN(PIN_PA24, 2, 1) +-#define PIN_PA24__TDO PINMUX_PIN(PIN_PA24, 3, 4) +-#define PIN_PA24__SPI1_MISO PINMUX_PIN(PIN_PA24, 4, 2) +-#define PIN_PA24__QSPI0_IO0 PINMUX_PIN(PIN_PA24, 6, 3) +-#define PIN_PA25 25 +-#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0) +-#define PIN_PA25__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA25, 1, 1) +-#define PIN_PA25__D3 PINMUX_PIN(PIN_PA25, 2, 1) +-#define PIN_PA25__TMS PINMUX_PIN(PIN_PA25, 3, 4) +-#define PIN_PA25__SPI1_NPCS0 PINMUX_PIN(PIN_PA25, 4, 2) +-#define PIN_PA25__QSPI0_IO1 PINMUX_PIN(PIN_PA25, 6, 3) +-#define PIN_PA26 26 +-#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0) +-#define PIN_PA26__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA26, 1, 1) +-#define PIN_PA26__D4 PINMUX_PIN(PIN_PA26, 2, 1) +-#define PIN_PA26__NTRST PINMUX_PIN(PIN_PA26, 3, 4) +-#define PIN_PA26__SPI1_NPCS1 PINMUX_PIN(PIN_PA26, 4, 2) +-#define PIN_PA26__QSPI0_IO2 PINMUX_PIN(PIN_PA26, 6, 3) +-#define PIN_PA27 27 +-#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0) +-#define PIN_PA27__TIOA1 PINMUX_PIN(PIN_PA27, 1, 2) +-#define PIN_PA27__D5 PINMUX_PIN(PIN_PA27, 2, 1) +-#define PIN_PA27__SPI0_NPCS2 PINMUX_PIN(PIN_PA27, 3, 2) +-#define PIN_PA27__SPI1_NPCS2 PINMUX_PIN(PIN_PA27, 4, 2) +-#define PIN_PA27__SDMMC1_RSTN PINMUX_PIN(PIN_PA27, 5, 1) +-#define PIN_PA27__QSPI0_IO3 PINMUX_PIN(PIN_PA27, 6, 3) +-#define PIN_PA28 28 +-#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0) +-#define PIN_PA28__TIOB1 PINMUX_PIN(PIN_PA28, 1, 2) +-#define PIN_PA28__D6 PINMUX_PIN(PIN_PA28, 2, 1) +-#define PIN_PA28__SPI0_NPCS3 PINMUX_PIN(PIN_PA28, 3, 2) +-#define PIN_PA28__SPI1_NPCS3 PINMUX_PIN(PIN_PA28, 4, 2) +-#define PIN_PA28__SDMMC1_CMD PINMUX_PIN(PIN_PA28, 5, 1) +-#define PIN_PA28__CLASSD_L0 PINMUX_PIN(PIN_PA28, 6, 1) +-#define PIN_PA29 29 +-#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0) +-#define PIN_PA29__TCLK1 PINMUX_PIN(PIN_PA29, 1, 2) +-#define PIN_PA29__D7 PINMUX_PIN(PIN_PA29, 2, 1) +-#define PIN_PA29__SPI0_NPCS1 PINMUX_PIN(PIN_PA29, 3, 2) +-#define PIN_PA29__SDMMC1_WP PINMUX_PIN(PIN_PA29, 5, 1) +-#define PIN_PA29__CLASSD_L1 PINMUX_PIN(PIN_PA29, 6, 1) +-#define PIN_PA30 30 +-#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0) +-#define PIN_PA30__NWE_NANDWE PINMUX_PIN(PIN_PA30, 2, 1) +-#define PIN_PA30__SPI0_NPCS0 PINMUX_PIN(PIN_PA30, 3, 2) +-#define PIN_PA30__PWMH0 PINMUX_PIN(PIN_PA30, 4, 1) +-#define PIN_PA30__SDMMC1_CD PINMUX_PIN(PIN_PA30, 5, 1) +-#define PIN_PA30__CLASSD_L2 PINMUX_PIN(PIN_PA30, 6, 1) +-#define PIN_PA31 31 +-#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0) +-#define PIN_PA31__NCS3 PINMUX_PIN(PIN_PA31, 2, 1) +-#define PIN_PA31__SPI0_MISO PINMUX_PIN(PIN_PA31, 3, 2) +-#define PIN_PA31__PWML0 PINMUX_PIN(PIN_PA31, 4, 1) +-#define PIN_PA31__CLASSD_L3 PINMUX_PIN(PIN_PA31, 6, 1) +-#define PIN_PB0 32 +-#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0) +-#define PIN_PB0__A21_NANDALE PINMUX_PIN(PIN_PB0, 2, 1) +-#define PIN_PB0__SPI0_MOSI PINMUX_PIN(PIN_PB0, 3, 2) +-#define PIN_PB0__PWMH1 PINMUX_PIN(PIN_PB0, 4, 1) +-#define PIN_PB1 33 +-#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0) +-#define PIN_PB1__A22_NANDCLE PINMUX_PIN(PIN_PB1, 2, 1) +-#define PIN_PB1__SPI0_SPCK PINMUX_PIN(PIN_PB1, 3, 2) +-#define PIN_PB1__PWML1 PINMUX_PIN(PIN_PB1, 4, 1) +-#define PIN_PB1__CLASSD_R0 PINMUX_PIN(PIN_PB1, 6, 1) +-#define PIN_PB2 34 +-#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0) +-#define PIN_PB2__NRD_NANDOE PINMUX_PIN(PIN_PB2, 2, 1) +-#define PIN_PB2__PWMFI0 PINMUX_PIN(PIN_PB2, 4, 1) +-#define PIN_PB2__CLASSD_R1 PINMUX_PIN(PIN_PB2, 6, 1) +-#define PIN_PB3 35 +-#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) +-#define PIN_PB3__URXD4 PINMUX_PIN(PIN_PB3, 1, 1) +-#define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 2, 1) +-#define PIN_PB3__IRQ PINMUX_PIN(PIN_PB3, 3, 3) +-#define PIN_PB3__PWMEXTRG0 PINMUX_PIN(PIN_PB3, 4, 1) +-#define PIN_PB3__CLASSD_R2 PINMUX_PIN(PIN_PB3, 6, 1) +-#define PIN_PB4 36 +-#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0) +-#define PIN_PB4__UTXD4 PINMUX_PIN(PIN_PB4, 1, 1) +-#define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 2, 1) +-#define PIN_PB4__FIQ PINMUX_PIN(PIN_PB4, 3, 4) +-#define PIN_PB4__CLASSD_R3 PINMUX_PIN(PIN_PB4, 6, 1) +-#define PIN_PB5 37 +-#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0) +-#define PIN_PB5__TCLK2 PINMUX_PIN(PIN_PB5, 1, 1) +-#define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 2, 1) +-#define PIN_PB5__PWMH2 PINMUX_PIN(PIN_PB5, 3, 1) +-#define PIN_PB5__QSPI1_SCK PINMUX_PIN(PIN_PB5, 4, 2) +-#define PIN_PB5__GTSUCOMP PINMUX_PIN(PIN_PB5, 6, 3) +-#define PIN_PB6 38 +-#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0) +-#define PIN_PB6__TIOA2 PINMUX_PIN(PIN_PB6, 1, 1) +-#define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 2, 1) +-#define PIN_PB6__PWML2 PINMUX_PIN(PIN_PB6, 3, 1) +-#define PIN_PB6__QSPI1_CS PINMUX_PIN(PIN_PB6, 4, 2) +-#define PIN_PB6__GTXER PINMUX_PIN(PIN_PB6, 6, 3) +-#define PIN_PB7 39 +-#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0) +-#define PIN_PB7__TIOB2 PINMUX_PIN(PIN_PB7, 1, 1) +-#define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 2, 1) +-#define PIN_PB7__PWMH3 PINMUX_PIN(PIN_PB7, 3, 1) +-#define PIN_PB7__QSPI1_IO0 PINMUX_PIN(PIN_PB7, 4, 2) +-#define PIN_PB7__GRXCK PINMUX_PIN(PIN_PB7, 6, 3) +-#define PIN_PB8 40 +-#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0) +-#define PIN_PB8__TCLK3 PINMUX_PIN(PIN_PB8, 1, 1) +-#define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 2, 1) +-#define PIN_PB8__PWML3 PINMUX_PIN(PIN_PB8, 3, 1) +-#define PIN_PB8__QSPI1_IO1 PINMUX_PIN(PIN_PB8, 4, 2) +-#define PIN_PB8__GCRS PINMUX_PIN(PIN_PB8, 6, 3) +-#define PIN_PB9 41 +-#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0) +-#define PIN_PB9__TIOA3 PINMUX_PIN(PIN_PB9, 1, 1) +-#define PIN_PB9__D14 PINMUX_PIN(PIN_PB9, 2, 1) +-#define PIN_PB9__PWMFI1 PINMUX_PIN(PIN_PB9, 3, 1) +-#define PIN_PB9__QSPI1_IO2 PINMUX_PIN(PIN_PB9, 4, 2) +-#define PIN_PB9__GCOL PINMUX_PIN(PIN_PB9, 6, 3) +-#define PIN_PB10 42 +-#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0) +-#define PIN_PB10__TIOB3 PINMUX_PIN(PIN_PB10, 1, 1) +-#define PIN_PB10__D15 PINMUX_PIN(PIN_PB10, 2, 1) +-#define PIN_PB10__PWMEXTRG1 PINMUX_PIN(PIN_PB10, 3, 1) +-#define PIN_PB10__QSPI1_IO3 PINMUX_PIN(PIN_PB10, 4, 2) +-#define PIN_PB10__GRX2 PINMUX_PIN(PIN_PB10, 6, 3) +-#define PIN_PB11 43 +-#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0) +-#define PIN_PB11__LCDDAT0 PINMUX_PIN(PIN_PB11, 1, 1) +-#define PIN_PB11__A0_NBS0 PINMUX_PIN(PIN_PB11, 2, 1) +-#define PIN_PB11__URXD3 PINMUX_PIN(PIN_PB11, 3, 3) +-#define PIN_PB11__PDMIC_DAT PINMUX_PIN(PIN_PB11, 4, 2) +-#define PIN_PB11__GRX3 PINMUX_PIN(PIN_PB11, 6, 3) +-#define PIN_PB12 44 +-#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0) +-#define PIN_PB12__LCDDAT1 PINMUX_PIN(PIN_PB12, 1, 1) +-#define PIN_PB12__A1 PINMUX_PIN(PIN_PB12, 2, 1) +-#define PIN_PB12__UTXD3 PINMUX_PIN(PIN_PB12, 3, 3) +-#define PIN_PB12__PDMIC_CLK PINMUX_PIN(PIN_PB12, 4, 2) +-#define PIN_PB12__GTX2 PINMUX_PIN(PIN_PB12, 6, 3) +-#define PIN_PB13 45 +-#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0) +-#define PIN_PB13__LCDDAT2 PINMUX_PIN(PIN_PB13, 1, 1) +-#define PIN_PB13__A2 PINMUX_PIN(PIN_PB13, 2, 1) +-#define PIN_PB13__PCK1 PINMUX_PIN(PIN_PB13, 3, 3) +-#define PIN_PB13__GTX3 PINMUX_PIN(PIN_PB13, 6, 3) +-#define PIN_PB14 46 +-#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0) +-#define PIN_PB14__LCDDAT3 PINMUX_PIN(PIN_PB14, 1, 1) +-#define PIN_PB14__A3 PINMUX_PIN(PIN_PB14, 2, 1) +-#define PIN_PB14__TK1 PINMUX_PIN(PIN_PB14, 3, 2) +-#define PIN_PB14__I2SC1_MCK PINMUX_PIN(PIN_PB14, 4, 1) +-#define PIN_PB14__QSPI1_SCK PINMUX_PIN(PIN_PB14, 5, 3) +-#define PIN_PB14__GTXCK PINMUX_PIN(PIN_PB14, 6, 3) +-#define PIN_PB15 47 +-#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0) +-#define PIN_PB15__LCDDAT4 PINMUX_PIN(PIN_PB15, 1, 1) +-#define PIN_PB15__A4 PINMUX_PIN(PIN_PB15, 2, 1) +-#define PIN_PB15__TF1 PINMUX_PIN(PIN_PB15, 3, 2) +-#define PIN_PB15__I2SC1_CK PINMUX_PIN(PIN_PB15, 4, 1) +-#define PIN_PB15__QSPI1_CS PINMUX_PIN(PIN_PB15, 5, 3) +-#define PIN_PB15__GTXEN PINMUX_PIN(PIN_PB15, 6, 3) +-#define PIN_PB16 48 +-#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0) +-#define PIN_PB16__LCDDAT5 PINMUX_PIN(PIN_PB16, 1, 1) +-#define PIN_PB16__A5 PINMUX_PIN(PIN_PB16, 2, 1) +-#define PIN_PB16__TD1 PINMUX_PIN(PIN_PB16, 3, 2) +-#define PIN_PB16__I2SC1_WS PINMUX_PIN(PIN_PB16, 4, 1) +-#define PIN_PB16__QSPI1_IO0 PINMUX_PIN(PIN_PB16, 5, 3) +-#define PIN_PB16__GRXDV PINMUX_PIN(PIN_PB16, 6, 3) +-#define PIN_PB17 49 +-#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0) +-#define PIN_PB17__LCDDAT6 PINMUX_PIN(PIN_PB17, 1, 1) +-#define PIN_PB17__A6 PINMUX_PIN(PIN_PB17, 2, 1) +-#define PIN_PB17__RD1 PINMUX_PIN(PIN_PB17, 3, 2) +-#define PIN_PB17__I2SC1_DI0 PINMUX_PIN(PIN_PB17, 4, 1) +-#define PIN_PB17__QSPI1_IO1 PINMUX_PIN(PIN_PB17, 5, 3) +-#define PIN_PB17__GRXER PINMUX_PIN(PIN_PB17, 6, 3) +-#define PIN_PB18 50 +-#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0) +-#define PIN_PB18__LCDDAT7 PINMUX_PIN(PIN_PB18, 1, 1) +-#define PIN_PB18__A7 PINMUX_PIN(PIN_PB18, 2, 1) +-#define PIN_PB18__RK1 PINMUX_PIN(PIN_PB18, 3, 2) +-#define PIN_PB18__I2SC1_DO0 PINMUX_PIN(PIN_PB18, 4, 1) +-#define PIN_PB18__QSPI1_IO2 PINMUX_PIN(PIN_PB18, 5, 3) +-#define PIN_PB18__GRX0 PINMUX_PIN(PIN_PB18, 6, 3) +-#define PIN_PB19 51 +-#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0) +-#define PIN_PB19__LCDDAT8 PINMUX_PIN(PIN_PB19, 1, 1) +-#define PIN_PB19__A8 PINMUX_PIN(PIN_PB19, 2, 1) +-#define PIN_PB19__RF1 PINMUX_PIN(PIN_PB19, 3, 2) +-#define PIN_PB19__TIOA3 PINMUX_PIN(PIN_PB19, 4, 2) +-#define PIN_PB19__QSPI1_IO3 PINMUX_PIN(PIN_PB19, 5, 3) +-#define PIN_PB19__GRX1 PINMUX_PIN(PIN_PB19, 6, 3) +-#define PIN_PB20 52 +-#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0) +-#define PIN_PB20__LCDDAT9 PINMUX_PIN(PIN_PB20, 1, 1) +-#define PIN_PB20__A9 PINMUX_PIN(PIN_PB20, 2, 1) +-#define PIN_PB20__TK0 PINMUX_PIN(PIN_PB20, 3, 1) +-#define PIN_PB20__TIOB3 PINMUX_PIN(PIN_PB20, 4, 2) +-#define PIN_PB20__PCK1 PINMUX_PIN(PIN_PB20, 5, 4) +-#define PIN_PB20__GTX0 PINMUX_PIN(PIN_PB20, 6, 3) +-#define PIN_PB21 53 +-#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0) +-#define PIN_PB21__LCDDAT10 PINMUX_PIN(PIN_PB21, 1, 1) +-#define PIN_PB21__A10 PINMUX_PIN(PIN_PB21, 2, 1) +-#define PIN_PB21__TF0 PINMUX_PIN(PIN_PB21, 3, 1) +-#define PIN_PB21__TCLK3 PINMUX_PIN(PIN_PB21, 4, 2) +-#define PIN_PB21__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB21, 5, 3) +-#define PIN_PB21__GTX1 PINMUX_PIN(PIN_PB21, 6, 3) +-#define PIN_PB22 54 +-#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) +-#define PIN_PB22__LCDDAT11 PINMUX_PIN(PIN_PB22, 1, 1) +-#define PIN_PB22__A11 PINMUX_PIN(PIN_PB22, 2, 1) +-#define PIN_PB22__TD0 PINMUX_PIN(PIN_PB22, 3, 1) +-#define PIN_PB22__TIOA2 PINMUX_PIN(PIN_PB22, 4, 2) +-#define PIN_PB22__FLEXCOM3_IO1 PINMUX_PIN(PIN_PB22, 5, 3) +-#define PIN_PB22__GMDC PINMUX_PIN(PIN_PB22, 6, 3) +-#define PIN_PB23 55 +-#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0) +-#define PIN_PB23__LCDDAT12 PINMUX_PIN(PIN_PB23, 1, 1) +-#define PIN_PB23__A12 PINMUX_PIN(PIN_PB23, 2, 1) +-#define PIN_PB23__RD0 PINMUX_PIN(PIN_PB23, 3, 1) +-#define PIN_PB23__TIOB2 PINMUX_PIN(PIN_PB23, 4, 2) +-#define PIN_PB23__FLEXCOM3_IO0 PINMUX_PIN(PIN_PB23, 5, 3) +-#define PIN_PB23__GMDIO PINMUX_PIN(PIN_PB23, 6, 3) +-#define PIN_PB24 56 +-#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0) +-#define PIN_PB24__LCDDAT13 PINMUX_PIN(PIN_PB24, 1, 1) +-#define PIN_PB24__A13 PINMUX_PIN(PIN_PB24, 2, 1) +-#define PIN_PB24__RK0 PINMUX_PIN(PIN_PB24, 3, 1) +-#define PIN_PB24__TCLK2 PINMUX_PIN(PIN_PB24, 4, 2) +-#define PIN_PB24__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB24, 5, 3) +-#define PIN_PB24__ISC_D10 PINMUX_PIN(PIN_PB24, 6, 3) +-#define PIN_PB25 57 +-#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0) +-#define PIN_PB25__LCDDAT14 PINMUX_PIN(PIN_PB25, 1, 1) +-#define PIN_PB25__A14 PINMUX_PIN(PIN_PB25, 2, 1) +-#define PIN_PB25__RF0 PINMUX_PIN(PIN_PB25, 3, 1) +-#define PIN_PB25__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB25, 5, 3) +-#define PIN_PB25__ISC_D11 PINMUX_PIN(PIN_PB25, 6, 3) +-#define PIN_PB26 58 +-#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0) +-#define PIN_PB26__LCDDAT15 PINMUX_PIN(PIN_PB26, 1, 1) +-#define PIN_PB26__A15 PINMUX_PIN(PIN_PB26, 2, 1) +-#define PIN_PB26__URXD0 PINMUX_PIN(PIN_PB26, 3, 1) +-#define PIN_PB26__PDMIC_DAT PINMUX_PIN(PIN_PB26, 4, 1) +-#define PIN_PB26__ISC_D0 PINMUX_PIN(PIN_PB26, 6, 3) +-#define PIN_PB27 59 +-#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0) +-#define PIN_PB27__LCDDAT16 PINMUX_PIN(PIN_PB27, 1, 1) +-#define PIN_PB27__A16 PINMUX_PIN(PIN_PB27, 2, 1) +-#define PIN_PB27__UTXD0 PINMUX_PIN(PIN_PB27, 3, 1) +-#define PIN_PB27__PDMIC_CLK PINMUX_PIN(PIN_PB27, 4, 1) +-#define PIN_PB27__ISC_D1 PINMUX_PIN(PIN_PB27, 6, 3) +-#define PIN_PB28 60 +-#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0) +-#define PIN_PB28__LCDDAT17 PINMUX_PIN(PIN_PB28, 1, 1) +-#define PIN_PB28__A17 PINMUX_PIN(PIN_PB28, 2, 1) +-#define PIN_PB28__FLEXCOM0_IO0 PINMUX_PIN(PIN_PB28, 3, 1) +-#define PIN_PB28__TIOA5 PINMUX_PIN(PIN_PB28, 4, 2) +-#define PIN_PB28__ISC_D2 PINMUX_PIN(PIN_PB28, 6, 3) +-#define PIN_PB29 61 +-#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0) +-#define PIN_PB29__LCDDAT18 PINMUX_PIN(PIN_PB29, 1, 1) +-#define PIN_PB29__A18 PINMUX_PIN(PIN_PB29, 2, 1) +-#define PIN_PB29__FLEXCOM0_IO1 PINMUX_PIN(PIN_PB29, 3, 1) +-#define PIN_PB29__TIOB5 PINMUX_PIN(PIN_PB29, 4, 2) +-#define PIN_PB29__ISC_D3 PINMUX_PIN(PIN_PB29, 7, 3) +-#define PIN_PB30 62 +-#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0) +-#define PIN_PB30__LCDDAT19 PINMUX_PIN(PIN_PB30, 1, 1) +-#define PIN_PB30__A19 PINMUX_PIN(PIN_PB30, 2, 1) +-#define PIN_PB30__FLEXCOM0_IO2 PINMUX_PIN(PIN_PB30, 3, 1) +-#define PIN_PB30__TCLK5 PINMUX_PIN(PIN_PB30, 4, 2) +-#define PIN_PB30__ISC_D4 PINMUX_PIN(PIN_PB30, 6, 3) +-#define PIN_PB31 63 +-#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0) +-#define PIN_PB31__LCDDAT20 PINMUX_PIN(PIN_PB31, 1, 1) +-#define PIN_PB31__A20 PINMUX_PIN(PIN_PB31, 2, 1) +-#define PIN_PB31__FLEXCOM0_IO3 PINMUX_PIN(PIN_PB31, 3, 1) +-#define PIN_PB31__TWD0 PINMUX_PIN(PIN_PB31, 4, 1) +-#define PIN_PB31__ISC_D5 PINMUX_PIN(PIN_PB31, 6, 3) +-#define PIN_PC0 64 +-#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0) +-#define PIN_PC0__LCDDAT21 PINMUX_PIN(PIN_PC0, 1, 1) +-#define PIN_PC0__A23 PINMUX_PIN(PIN_PC0, 2, 1) +-#define PIN_PC0__FLEXCOM0_IO4 PINMUX_PIN(PIN_PC0, 3, 1) +-#define PIN_PC0__TWCK0 PINMUX_PIN(PIN_PC0, 4, 1) +-#define PIN_PC0__ISC_D6 PINMUX_PIN(PIN_PC0, 6, 3) +-#define PIN_PC1 65 +-#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0) +-#define PIN_PC1__LCDDAT22 PINMUX_PIN(PIN_PC1, 1, 1) +-#define PIN_PC1__A24 PINMUX_PIN(PIN_PC1, 2, 1) +-#define PIN_PC1__CANTX0 PINMUX_PIN(PIN_PC1, 3, 1) +-#define PIN_PC1__SPI1_SPCK PINMUX_PIN(PIN_PC1, 4, 1) +-#define PIN_PC1__I2SC0_CK PINMUX_PIN(PIN_PC1, 5, 1) +-#define PIN_PC1__ISC_D7 PINMUX_PIN(PIN_PC1, 6, 3) +-#define PIN_PC2 66 +-#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0) +-#define PIN_PC2__LCDDAT23 PINMUX_PIN(PIN_PC2, 1, 1) +-#define PIN_PC2__A25 PINMUX_PIN(PIN_PC2, 2, 1) +-#define PIN_PC2__CANRX0 PINMUX_PIN(PIN_PC2, 3, 1) +-#define PIN_PC2__SPI1_MOSI PINMUX_PIN(PIN_PC2, 4, 1) +-#define PIN_PC2__I2SC0_MCK PINMUX_PIN(PIN_PC2, 5, 1) +-#define PIN_PC2__ISC_D8 PINMUX_PIN(PIN_PC2, 6, 3) +-#define PIN_PC3 67 +-#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0) +-#define PIN_PC3__LCDPWM PINMUX_PIN(PIN_PC3, 1, 1) +-#define PIN_PC3__NWAIT PINMUX_PIN(PIN_PC3, 2, 1) +-#define PIN_PC3__TIOA1 PINMUX_PIN(PIN_PC3, 3, 1) +-#define PIN_PC3__SPI1_MISO PINMUX_PIN(PIN_PC3, 4, 1) +-#define PIN_PC3__I2SC0_WS PINMUX_PIN(PIN_PC3, 5, 1) +-#define PIN_PC3__ISC_D9 PINMUX_PIN(PIN_PC3, 6, 3) +-#define PIN_PC4 68 +-#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0) +-#define PIN_PC4__LCDDISP PINMUX_PIN(PIN_PC4, 1, 1) +-#define PIN_PC4__NWR1_NBS1 PINMUX_PIN(PIN_PC4, 2, 1) +-#define PIN_PC4__TIOB1 PINMUX_PIN(PIN_PC4, 3, 1) +-#define PIN_PC4__SPI1_NPCS0 PINMUX_PIN(PIN_PC4, 4, 1) +-#define PIN_PC4__I2SC0_DI0 PINMUX_PIN(PIN_PC4, 5, 1) +-#define PIN_PC4__ISC_PCK PINMUX_PIN(PIN_PC4, 6, 3) +-#define PIN_PC5 69 +-#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0) +-#define PIN_PC5__LCDVSYNC PINMUX_PIN(PIN_PC5, 1, 1) +-#define PIN_PC5__NCS0 PINMUX_PIN(PIN_PC5, 2, 1) +-#define PIN_PC5__TCLK1 PINMUX_PIN(PIN_PC5, 3, 1) +-#define PIN_PC5__SPI1_NPCS1 PINMUX_PIN(PIN_PC5, 4, 1) +-#define PIN_PC5__I2SC0_DO0 PINMUX_PIN(PIN_PC5, 5, 1) +-#define PIN_PC5__ISC_VSYNC PINMUX_PIN(PIN_PC5, 6, 3) +-#define PIN_PC6 70 +-#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0) +-#define PIN_PC6__LCDHSYNC PINMUX_PIN(PIN_PC6, 1, 1) +-#define PIN_PC6__NCS1 PINMUX_PIN(PIN_PC6, 2, 1) +-#define PIN_PC6__TWD1 PINMUX_PIN(PIN_PC6, 3, 1) +-#define PIN_PC6__SPI1_NPCS2 PINMUX_PIN(PIN_PC6, 4, 1) +-#define PIN_PC6__ISC_HSYNC PINMUX_PIN(PIN_PC6, 6, 3) +-#define PIN_PC7 71 +-#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0) +-#define PIN_PC7__LCDPCK PINMUX_PIN(PIN_PC7, 1, 1) +-#define PIN_PC7__NCS2 PINMUX_PIN(PIN_PC7, 2, 1) +-#define PIN_PC7__TWCK1 PINMUX_PIN(PIN_PC7, 3, 1) +-#define PIN_PC7__SPI1_NPCS3 PINMUX_PIN(PIN_PC7, 4, 1) +-#define PIN_PC7__URXD1 PINMUX_PIN(PIN_PC7, 5, 2) +-#define PIN_PC7__ISC_MCK PINMUX_PIN(PIN_PC7, 6, 3) +-#define PIN_PC8 72 +-#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0) +-#define PIN_PC8__LCDDEN PINMUX_PIN(PIN_PC8, 1, 1) +-#define PIN_PC8__NANDRDY PINMUX_PIN(PIN_PC8, 2, 1) +-#define PIN_PC8__FIQ PINMUX_PIN(PIN_PC8, 3, 1) +-#define PIN_PC8__PCK0 PINMUX_PIN(PIN_PC8, 4, 3) +-#define PIN_PC8__UTXD1 PINMUX_PIN(PIN_PC8, 5, 2) +-#define PIN_PC8__ISC_FIELD PINMUX_PIN(PIN_PC8, 6, 3) +-#define PIN_PC9 73 +-#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) +-#define PIN_PC9__FIQ PINMUX_PIN(PIN_PC9, 1, 3) +-#define PIN_PC9__GTSUCOMP PINMUX_PIN(PIN_PC9, 2, 1) +-#define PIN_PC9__ISC_D0 PINMUX_PIN(PIN_PC9, 3, 1) +-#define PIN_PC9__TIOA4 PINMUX_PIN(PIN_PC9, 4, 2) +-#define PIN_PC10 74 +-#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0) +-#define PIN_PC10__LCDDAT2 PINMUX_PIN(PIN_PC10, 1, 2) +-#define PIN_PC10__GTXCK PINMUX_PIN(PIN_PC10, 2, 1) +-#define PIN_PC10__ISC_D1 PINMUX_PIN(PIN_PC10, 3, 1) +-#define PIN_PC10__TIOB4 PINMUX_PIN(PIN_PC10, 4, 2) +-#define PIN_PC10__CANTX0 PINMUX_PIN(PIN_PC10, 5, 2) +-#define PIN_PC11 75 +-#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0) +-#define PIN_PC11__LCDDAT3 PINMUX_PIN(PIN_PC11, 1, 2) +-#define PIN_PC11__GTXEN PINMUX_PIN(PIN_PC11, 2, 1) +-#define PIN_PC11__ISC_D2 PINMUX_PIN(PIN_PC11, 3, 1) +-#define PIN_PC11__TCLK4 PINMUX_PIN(PIN_PC11, 4, 2) +-#define PIN_PC11__CANRX0 PINMUX_PIN(PIN_PC11, 5, 2) +-#define PIN_PC11__A0_NBS0 PINMUX_PIN(PIN_PC11, 6, 2) +-#define PIN_PC12 76 +-#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0) +-#define PIN_PC12__LCDDAT4 PINMUX_PIN(PIN_PC12, 1, 2) +-#define PIN_PC12__GRXDV PINMUX_PIN(PIN_PC12, 2, 1) +-#define PIN_PC12__ISC_D3 PINMUX_PIN(PIN_PC12, 3, 1) +-#define PIN_PC12__URXD3 PINMUX_PIN(PIN_PC12, 4, 1) +-#define PIN_PC12__TK0 PINMUX_PIN(PIN_PC12, 5, 2) +-#define PIN_PC12__A1 PINMUX_PIN(PIN_PC12, 6, 2) +-#define PIN_PC13 77 +-#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0) +-#define PIN_PC13__LCDDAT5 PINMUX_PIN(PIN_PC13, 1, 2) +-#define PIN_PC13__GRXER PINMUX_PIN(PIN_PC13, 2, 1) +-#define PIN_PC13__ISC_D4 PINMUX_PIN(PIN_PC13, 3, 1) +-#define PIN_PC13__UTXD3 PINMUX_PIN(PIN_PC13, 4, 1) +-#define PIN_PC13__TF0 PINMUX_PIN(PIN_PC13, 5, 2) +-#define PIN_PC13__A2 PINMUX_PIN(PIN_PC13, 6, 2) +-#define PIN_PC14 78 +-#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0) +-#define PIN_PC14__LCDDAT6 PINMUX_PIN(PIN_PC14, 1, 2) +-#define PIN_PC14__GRX0 PINMUX_PIN(PIN_PC14, 2, 1) +-#define PIN_PC14__ISC_D5 PINMUX_PIN(PIN_PC14, 3, 1) +-#define PIN_PC14__TD0 PINMUX_PIN(PIN_PC14, 5, 2) +-#define PIN_PC14__A3 PINMUX_PIN(PIN_PC14, 6, 2) +-#define PIN_PC15 79 +-#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) +-#define PIN_PC15__LCDDAT7 PINMUX_PIN(PIN_PC15, 1, 2) +-#define PIN_PC15__GRX1 PINMUX_PIN(PIN_PC15, 2, 1) +-#define PIN_PC15__ISC_D6 PINMUX_PIN(PIN_PC15, 3, 1) +-#define PIN_PC15__RD0 PINMUX_PIN(PIN_PC15, 5, 2) +-#define PIN_PC15__A4 PINMUX_PIN(PIN_PC15, 6, 2) +-#define PIN_PC16 80 +-#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0) +-#define PIN_PC16__LCDDAT10 PINMUX_PIN(PIN_PC16, 1, 2) +-#define PIN_PC16__GTX0 PINMUX_PIN(PIN_PC16, 2, 1) +-#define PIN_PC16__ISC_D7 PINMUX_PIN(PIN_PC16, 3, 1) +-#define PIN_PC16__RK0 PINMUX_PIN(PIN_PC16, 5, 2) +-#define PIN_PC16__A5 PINMUX_PIN(PIN_PC16, 6, 2) +-#define PIN_PC17 81 +-#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0) +-#define PIN_PC17__LCDDAT11 PINMUX_PIN(PIN_PC17, 1, 2) +-#define PIN_PC17__GTX1 PINMUX_PIN(PIN_PC17, 2, 1) +-#define PIN_PC17__ISC_D8 PINMUX_PIN(PIN_PC17, 3, 1) +-#define PIN_PC17__RF0 PINMUX_PIN(PIN_PC17, 5, 2) +-#define PIN_PC17__A6 PINMUX_PIN(PIN_PC17, 6, 2) +-#define PIN_PC18 82 +-#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0) +-#define PIN_PC18__LCDDAT12 PINMUX_PIN(PIN_PC18, 1, 2) +-#define PIN_PC18__GMDC PINMUX_PIN(PIN_PC18, 2, 1) +-#define PIN_PC18__ISC_D9 PINMUX_PIN(PIN_PC18, 3, 1) +-#define PIN_PC18__FLEXCOM3_IO2 PINMUX_PIN(PIN_PC18, 5, 2) +-#define PIN_PC18__A7 PINMUX_PIN(PIN_PC18, 6, 2) +-#define PIN_PC19 83 +-#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0) +-#define PIN_PC19__LCDDAT13 PINMUX_PIN(PIN_PC19, 1, 2) +-#define PIN_PC19__GMDIO PINMUX_PIN(PIN_PC19, 2, 1) +-#define PIN_PC19__ISC_D10 PINMUX_PIN(PIN_PC19, 3, 1) +-#define PIN_PC19__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC19, 5, 2) +-#define PIN_PC19__A8 PINMUX_PIN(PIN_PC19, 6, 2) +-#define PIN_PC20 84 +-#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0) +-#define PIN_PC20__LCDDAT14 PINMUX_PIN(PIN_PC20, 1, 2) +-#define PIN_PC20__GRXCK PINMUX_PIN(PIN_PC20, 2, 1) +-#define PIN_PC20__ISC_D11 PINMUX_PIN(PIN_PC20, 3, 1) +-#define PIN_PC20__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC20, 5, 2) +-#define PIN_PC20__A9 PINMUX_PIN(PIN_PC20, 6, 2) +-#define PIN_PC21 85 +-#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0) +-#define PIN_PC21__LCDDAT15 PINMUX_PIN(PIN_PC21, 1, 2) +-#define PIN_PC21__GTXER PINMUX_PIN(PIN_PC21, 2, 1) +-#define PIN_PC21__ISC_PCK PINMUX_PIN(PIN_PC21, 3, 1) +-#define PIN_PC21__FLEXCOM3_IO3 PINMUX_PIN(PIN_PC21, 5, 2) +-#define PIN_PC21__A10 PINMUX_PIN(PIN_PC21, 6, 2) +-#define PIN_PC22 86 +-#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0) +-#define PIN_PC22__LCDDAT18 PINMUX_PIN(PIN_PC22, 1, 2) +-#define PIN_PC22__GCRS PINMUX_PIN(PIN_PC22, 2, 1) +-#define PIN_PC22__ISC_VSYNC PINMUX_PIN(PIN_PC22, 3, 1) +-#define PIN_PC22__FLEXCOM3_IO4 PINMUX_PIN(PIN_PC22, 5, 2) +-#define PIN_PC22__A11 PINMUX_PIN(PIN_PC22, 6, 2) +-#define PIN_PC23 87 +-#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0) +-#define PIN_PC23__LCDDAT19 PINMUX_PIN(PIN_PC23, 1, 2) +-#define PIN_PC23__GCOL PINMUX_PIN(PIN_PC23, 2, 1) +-#define PIN_PC23__ISC_HSYNC PINMUX_PIN(PIN_PC23, 3, 1) +-#define PIN_PC23__A12 PINMUX_PIN(PIN_PC23, 6, 2) +-#define PIN_PC24 88 +-#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0) +-#define PIN_PC24__LCDDAT20 PINMUX_PIN(PIN_PC24, 1, 2) +-#define PIN_PC24__GRX2 PINMUX_PIN(PIN_PC24, 2, 1) +-#define PIN_PC24__ISC_MCK PINMUX_PIN(PIN_PC24, 3, 1) +-#define PIN_PC24__A13 PINMUX_PIN(PIN_PC24, 6, 2) +-#define PIN_PC25 89 +-#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0) +-#define PIN_PC25__LCDDAT21 PINMUX_PIN(PIN_PC25, 1, 2) +-#define PIN_PC25__GRX3 PINMUX_PIN(PIN_PC25, 2, 1) +-#define PIN_PC25__ISC_FIELD PINMUX_PIN(PIN_PC25, 3, 1) +-#define PIN_PC25__A14 PINMUX_PIN(PIN_PC25, 6, 2) +-#define PIN_PC26 90 +-#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0) +-#define PIN_PC26__LCDDAT22 PINMUX_PIN(PIN_PC26, 1, 2) +-#define PIN_PC26__GTX2 PINMUX_PIN(PIN_PC26, 2, 1) +-#define PIN_PC26__CANTX1 PINMUX_PIN(PIN_PC26, 4, 1) +-#define PIN_PC26__A15 PINMUX_PIN(PIN_PC26, 6, 2) +-#define PIN_PC27 91 +-#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0) +-#define PIN_PC27__LCDDAT23 PINMUX_PIN(PIN_PC27, 1, 2) +-#define PIN_PC27__GTX3 PINMUX_PIN(PIN_PC27, 2, 1) +-#define PIN_PC27__PCK1 PINMUX_PIN(PIN_PC27, 3, 2) +-#define PIN_PC27__CANRX1 PINMUX_PIN(PIN_PC27, 4, 1) +-#define PIN_PC27__TWD0 PINMUX_PIN(PIN_PC27, 5, 2) +-#define PIN_PC27__A16 PINMUX_PIN(PIN_PC27, 6, 2) +-#define PIN_PC28 92 +-#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0) +-#define PIN_PC28__LCDPWM PINMUX_PIN(PIN_PC28, 1, 2) +-#define PIN_PC28__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC28, 2, 1) +-#define PIN_PC28__PCK2 PINMUX_PIN(PIN_PC28, 3, 2) +-#define PIN_PC28__TWCK0 PINMUX_PIN(PIN_PC28, 5, 2) +-#define PIN_PC28__A17 PINMUX_PIN(PIN_PC28, 6, 2) +-#define PIN_PC29 93 +-#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0) +-#define PIN_PC29__LCDDISP PINMUX_PIN(PIN_PC29, 1, 2) +-#define PIN_PC29__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC29, 2, 1) +-#define PIN_PC29__A18 PINMUX_PIN(PIN_PC29, 6, 2) +-#define PIN_PC30 94 +-#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0) +-#define PIN_PC30__LCDVSYNC PINMUX_PIN(PIN_PC30, 1, 2) +-#define PIN_PC30__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC30, 2, 1) +-#define PIN_PC30__A19 PINMUX_PIN(PIN_PC30, 6, 2) +-#define PIN_PC31 95 +-#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0) +-#define PIN_PC31__LCDHSYNC PINMUX_PIN(PIN_PC31, 1, 2) +-#define PIN_PC31__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC31, 2, 1) +-#define PIN_PC31__URXD3 PINMUX_PIN(PIN_PC31, 3, 2) +-#define PIN_PC31__A20 PINMUX_PIN(PIN_PC31, 6, 2) +-#define PIN_PD0 96 +-#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0) +-#define PIN_PD0__LCDPCK PINMUX_PIN(PIN_PD0, 1, 2) +-#define PIN_PD0__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD0, 2, 1) +-#define PIN_PD0__UTXD3 PINMUX_PIN(PIN_PD0, 3, 2) +-#define PIN_PD0__GTSUCOMP PINMUX_PIN(PIN_PD0, 4, 2) +-#define PIN_PD0__A23 PINMUX_PIN(PIN_PD0, 6, 2) +-#define PIN_PD1 97 +-#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0) +-#define PIN_PD1__LCDDEN PINMUX_PIN(PIN_PD1, 1, 2) +-#define PIN_PD1__GRXCK PINMUX_PIN(PIN_PD1, 4, 2) +-#define PIN_PD1__A24 PINMUX_PIN(PIN_PD1, 6, 2) +-#define PIN_PD2 98 +-#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0) +-#define PIN_PD2__URXD1 PINMUX_PIN(PIN_PD2, 1, 1) +-#define PIN_PD2__GTXER PINMUX_PIN(PIN_PD2, 4, 2) +-#define PIN_PD2__ISC_MCK PINMUX_PIN(PIN_PD2, 5, 2) +-#define PIN_PD2__A25 PINMUX_PIN(PIN_PD2, 6, 2) +-#define PIN_PD3 99 +-#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0) +-#define PIN_PD3__UTXD1 PINMUX_PIN(PIN_PD3, 1, 1) +-#define PIN_PD3__FIQ PINMUX_PIN(PIN_PD3, 2, 2) +-#define PIN_PD3__GCRS PINMUX_PIN(PIN_PD3, 4, 2) +-#define PIN_PD3__ISC_D11 PINMUX_PIN(PIN_PD3, 5, 2) +-#define PIN_PD3__NWAIT PINMUX_PIN(PIN_PD3, 6, 2) +-#define PIN_PD4 100 +-#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0) +-#define PIN_PD4__TWD1 PINMUX_PIN(PIN_PD4, 1, 2) +-#define PIN_PD4__URXD2 PINMUX_PIN(PIN_PD4, 2, 1) +-#define PIN_PD4__GCOL PINMUX_PIN(PIN_PD4, 4, 2) +-#define PIN_PD4__ISC_D10 PINMUX_PIN(PIN_PD4, 5, 2) +-#define PIN_PD4__NCS0 PINMUX_PIN(PIN_PD4, 6, 2) +-#define PIN_PD5 101 +-#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0) +-#define PIN_PD5__TWCK1 PINMUX_PIN(PIN_PD5, 1, 2) +-#define PIN_PD5__UTXD2 PINMUX_PIN(PIN_PD5, 2, 1) +-#define PIN_PD5__GRX2 PINMUX_PIN(PIN_PD5, 4, 2) +-#define PIN_PD5__ISC_D9 PINMUX_PIN(PIN_PD5, 5, 2) +-#define PIN_PD5__NCS1 PINMUX_PIN(PIN_PD5, 6, 2) +-#define PIN_PD6 102 +-#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0) +-#define PIN_PD6__TCK PINMUX_PIN(PIN_PD6, 1, 2) +-#define PIN_PD6__PCK1 PINMUX_PIN(PIN_PD6, 2, 1) +-#define PIN_PD6__GRX3 PINMUX_PIN(PIN_PD6, 4, 2) +-#define PIN_PD6__ISC_D8 PINMUX_PIN(PIN_PD6, 5, 2) +-#define PIN_PD6__NCS2 PINMUX_PIN(PIN_PD6, 6, 2) +-#define PIN_PD7 103 +-#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0) +-#define PIN_PD7__TDI PINMUX_PIN(PIN_PD7, 1, 2) +-#define PIN_PD7__UTMI_RXVAL PINMUX_PIN(PIN_PD7, 3, 1) +-#define PIN_PD7__GTX2 PINMUX_PIN(PIN_PD7, 4, 2) +-#define PIN_PD7__ISC_D0 PINMUX_PIN(PIN_PD7, 5, 2) +-#define PIN_PD7__NWR1_NBS1 PINMUX_PIN(PIN_PD7, 6, 2) +-#define PIN_PD8 104 +-#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) +-#define PIN_PD8__TDO PINMUX_PIN(PIN_PD8, 1, 2) +-#define PIN_PD8__UTMI_RXERR PINMUX_PIN(PIN_PD8, 3, 1) +-#define PIN_PD8__GTX3 PINMUX_PIN(PIN_PD8, 4, 2) +-#define PIN_PD8__ISC_D1 PINMUX_PIN(PIN_PD8, 5, 2) +-#define PIN_PD8__NANDRDY PINMUX_PIN(PIN_PD8, 6, 2) +-#define PIN_PD9 105 +-#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0) +-#define PIN_PD9__TMS PINMUX_PIN(PIN_PD9, 1, 2) +-#define PIN_PD9__UTMI_RXACT PINMUX_PIN(PIN_PD9, 3, 1) +-#define PIN_PD9__GTXCK PINMUX_PIN(PIN_PD9, 4, 2) +-#define PIN_PD9__ISC_D2 PINMUX_PIN(PIN_PD9, 5, 2) +-#define PIN_PD10 106 +-#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0) +-#define PIN_PD10__NTRST PINMUX_PIN(PIN_PD10, 1, 2) +-#define PIN_PD10__UTMI_HDIS PINMUX_PIN(PIN_PD10, 3, 1) +-#define PIN_PD10__GTXEN PINMUX_PIN(PIN_PD10, 4, 2) +-#define PIN_PD10__ISC_D3 PINMUX_PIN(PIN_PD10, 5, 2) +-#define PIN_PD11 107 +-#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0) +-#define PIN_PD11__TIOA1 PINMUX_PIN(PIN_PD11, 1, 3) +-#define PIN_PD11__PCK2 PINMUX_PIN(PIN_PD11, 2, 2) +-#define PIN_PD11__UTMI_LS0 PINMUX_PIN(PIN_PD11, 3, 1) +-#define PIN_PD11__GRXDV PINMUX_PIN(PIN_PD11, 4, 2) +-#define PIN_PD11__ISC_D4 PINMUX_PIN(PIN_PD11, 5, 2) +-#define PIN_PD11__ISC_MCK PINMUX_PIN(PIN_PD11, 7, 4) +-#define PIN_PD12 108 +-#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0) +-#define PIN_PD12__TIOB1 PINMUX_PIN(PIN_PD12, 1, 3) +-#define PIN_PD12__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD12, 2, 2) +-#define PIN_PD12__UTMI_LS1 PINMUX_PIN(PIN_PD12, 3, 1) +-#define PIN_PD12__GRXER PINMUX_PIN(PIN_PD12, 4, 2) +-#define PIN_PD12__ISC_D5 PINMUX_PIN(PIN_PD12, 5, 2) +-#define PIN_PD12__ISC_D4 PINMUX_PIN(PIN_PD12, 6, 4) +-#define PIN_PD13 109 +-#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0) +-#define PIN_PD13__TCLK1 PINMUX_PIN(PIN_PD13, 1, 3) +-#define PIN_PD13__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD13, 2, 2) +-#define PIN_PD13__UTMI_CDRPCSEL0 PINMUX_PIN(PIN_PD13, 3, 1) +-#define PIN_PD13__GRX0 PINMUX_PIN(PIN_PD13, 4, 2) +-#define PIN_PD13__ISC_D6 PINMUX_PIN(PIN_PD13, 5, 2) +-#define PIN_PD13__ISC_D5 PINMUX_PIN(PIN_PD13, 6, 4) +-#define PIN_PD14 110 +-#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0) +-#define PIN_PD14__TCK PINMUX_PIN(PIN_PD14, 1, 1) +-#define PIN_PD14__FLEXCOM4_IO2 PINMUX_PIN(PIN_PD14, 2, 2) +-#define PIN_PD14__UTMI_CDRPCSEL1 PINMUX_PIN(PIN_PD14, 3, 1) +-#define PIN_PD14__GRX1 PINMUX_PIN(PIN_PD14, 4, 2) +-#define PIN_PD14__ISC_D7 PINMUX_PIN(PIN_PD14, 5, 2) +-#define PIN_PD14__ISC_D6 PINMUX_PIN(PIN_PD14, 6, 4) +-#define PIN_PD15 111 +-#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0) +-#define PIN_PD15__TDI PINMUX_PIN(PIN_PD15, 1, 1) +-#define PIN_PD15__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD15, 2, 2) +-#define PIN_PD15__UTMI_CDRCPDIVEN PINMUX_PIN(PIN_PD15, 3, 1) +-#define PIN_PD15__GTX0 PINMUX_PIN(PIN_PD15, 4, 2) +-#define PIN_PD15__ISC_PCK PINMUX_PIN(PIN_PD15, 5, 2) +-#define PIN_PD15__ISC_D7 PINMUX_PIN(PIN_PD15, 6, 4) +-#define PIN_PD16 112 +-#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0) +-#define PIN_PD16__TDO PINMUX_PIN(PIN_PD16, 1, 1) +-#define PIN_PD16__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD16, 2, 2) +-#define PIN_PD16__UTMI_CDRBISTEN PINMUX_PIN(PIN_PD16, 3, 1) +-#define PIN_PD16__GTX1 PINMUX_PIN(PIN_PD16, 4, 2) +-#define PIN_PD16__ISC_VSYNC PINMUX_PIN(PIN_PD16, 5, 2) +-#define PIN_PD16__ISC_D8 PINMUX_PIN(PIN_PD16, 6, 4) +-#define PIN_PD17 113 +-#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0) +-#define PIN_PD17__TMS PINMUX_PIN(PIN_PD17, 1, 1) +-#define PIN_PD17__UTMI_CDRCPSELDIV PINMUX_PIN(PIN_PD17, 3, 1) +-#define PIN_PD17__GMDC PINMUX_PIN(PIN_PD17, 4, 2) +-#define PIN_PD17__ISC_HSYNC PINMUX_PIN(PIN_PD17, 5, 2) +-#define PIN_PD17__ISC_D9 PINMUX_PIN(PIN_PD17, 6, 4) +-#define PIN_PD18 114 +-#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0) +-#define PIN_PD18__NTRST PINMUX_PIN(PIN_PD18, 1, 1) +-#define PIN_PD18__GMDIO PINMUX_PIN(PIN_PD18, 4, 2) +-#define PIN_PD18__ISC_FIELD PINMUX_PIN(PIN_PD18, 5, 2) +-#define PIN_PD18__ISC_D10 PINMUX_PIN(PIN_PD18, 6, 4) +-#define PIN_PD19 115 +-#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0) +-#define PIN_PD19__PCK0 PINMUX_PIN(PIN_PD19, 1, 1) +-#define PIN_PD19__TWD1 PINMUX_PIN(PIN_PD19, 2, 3) +-#define PIN_PD19__URXD2 PINMUX_PIN(PIN_PD19, 3, 3) +-#define PIN_PD19__I2SC0_CK PINMUX_PIN(PIN_PD19, 5, 2) +-#define PIN_PD19__ISC_D11 PINMUX_PIN(PIN_PD19, 6, 4) +-#define PIN_PD20 116 +-#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0) +-#define PIN_PD20__TIOA2 PINMUX_PIN(PIN_PD20, 1, 3) +-#define PIN_PD20__TWCK1 PINMUX_PIN(PIN_PD20, 2, 3) +-#define PIN_PD20__UTXD2 PINMUX_PIN(PIN_PD20, 3, 3) +-#define PIN_PD20__I2SC0_MCK PINMUX_PIN(PIN_PD20, 5, 2) +-#define PIN_PD20__ISC_PCK PINMUX_PIN(PIN_PD20, 6, 4) +-#define PIN_PD21 117 +-#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) +-#define PIN_PD21__TIOB2 PINMUX_PIN(PIN_PD21, 1, 3) +-#define PIN_PD21__TWD0 PINMUX_PIN(PIN_PD21, 2, 4) +-#define PIN_PD21__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD21, 3, 3) +-#define PIN_PD21__I2SC0_WS PINMUX_PIN(PIN_PD21, 5, 2) +-#define PIN_PD21__ISC_VSYNC PINMUX_PIN(PIN_PD21, 6, 4) +-#define PIN_PD22 118 +-#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0) +-#define PIN_PD22__TCLK2 PINMUX_PIN(PIN_PD22, 1, 3) +-#define PIN_PD22__TWCK0 PINMUX_PIN(PIN_PD22, 2, 4) +-#define PIN_PD22__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD22, 3, 3) +-#define PIN_PD22__I2SC0_DI0 PINMUX_PIN(PIN_PD22, 5, 2) +-#define PIN_PD22__ISC_HSYNC PINMUX_PIN(PIN_PD22, 6, 4) +-#define PIN_PD23 119 +-#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0) +-#define PIN_PD23__URXD2 PINMUX_PIN(PIN_PD23, 1, 2) +-#define PIN_PD23__FLEXCOM4_IO2 PINMUX_PIN(PIN_PD23, 3, 3) +-#define PIN_PD23__I2SC0_DO0 PINMUX_PIN(PIN_PD23, 5, 2) +-#define PIN_PD23__ISC_FIELD PINMUX_PIN(PIN_PD23, 6, 4) +-#define PIN_PD24 120 +-#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) +-#define PIN_PD24__UTXD2 PINMUX_PIN(PIN_PD24, 1, 2) +-#define PIN_PD24__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD24, 3, 3) +-#define PIN_PD25 121 +-#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) +-#define PIN_PD25__SPI1_SPCK PINMUX_PIN(PIN_PD25, 1, 3) +-#define PIN_PD25__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD25, 3, 3) +-#define PIN_PD26 122 +-#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0) +-#define PIN_PD26__SPI1_MOSI PINMUX_PIN(PIN_PD26, 1, 3) +-#define PIN_PD26__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD26, 3, 2) +-#define PIN_PD27 123 +-#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0) +-#define PIN_PD27__SPI1_MISO PINMUX_PIN(PIN_PD27, 1, 3) +-#define PIN_PD27__TCK PINMUX_PIN(PIN_PD27, 2, 3) +-#define PIN_PD27__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD27, 3, 2) +-#define PIN_PD28 124 +-#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0) +-#define PIN_PD28__SPI1_NPCS0 PINMUX_PIN(PIN_PD28, 1, 3) +-#define PIN_PD28__TCI PINMUX_PIN(PIN_PD28, 2, 3) +-#define PIN_PD28__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD28, 3, 2) +-#define PIN_PD29 125 +-#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0) +-#define PIN_PD29__SPI1_NPCS1 PINMUX_PIN(PIN_PD29, 1, 3) +-#define PIN_PD29__TDO PINMUX_PIN(PIN_PD29, 2, 3) +-#define PIN_PD29__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD29, 3, 2) +-#define PIN_PD29__TIOA3 PINMUX_PIN(PIN_PD29, 4, 3) +-#define PIN_PD29__TWD0 PINMUX_PIN(PIN_PD29, 5, 3) +-#define PIN_PD30 126 +-#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0) +-#define PIN_PD30__SPI1_NPCS2 PINMUX_PIN(PIN_PD30, 1, 3) +-#define PIN_PD30__TMS PINMUX_PIN(PIN_PD30, 2, 3) +-#define PIN_PD30__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD30, 3, 2) +-#define PIN_PD30__TIOB3 PINMUX_PIN(PIN_PD30, 4, 3) +-#define PIN_PD30__TWCK0 PINMUX_PIN(PIN_PD30, 5, 3) +-#define PIN_PD31 127 +-#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0) +-#define PIN_PD31__ADTRG PINMUX_PIN(PIN_PD31, 1, 1) +-#define PIN_PD31__NTRST PINMUX_PIN(PIN_PD31, 2, 3) +-#define PIN_PD31__IRQ PINMUX_PIN(PIN_PD31, 3, 4) +-#define PIN_PD31__TCLK3 PINMUX_PIN(PIN_PD31, 4, 3) +-#define PIN_PD31__PCK0 PINMUX_PIN(PIN_PD31, 5, 2) +diff --git a/scripts/dtc/include-prefixes/arm/sama5d2.dtsi b/scripts/dtc/include-prefixes/arm/sama5d2.dtsi +deleted file mode 100644 +index 801969c113d6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d2.dtsi ++++ /dev/null +@@ -1,1159 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC +- * +- * Copyright (C) 2015 Atmel, +- * 2015 Ludovic Desroches +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Atmel SAMA5D2 family SoC"; +- compatible = "atmel,sama5d2"; +- interrupt-parent = <&aic>; +- +- aliases { +- serial0 = &uart1; +- serial1 = &uart3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a5"; +- reg = <0>; +- next-level-cache = <&L2>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a5-pmu"; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; +- }; +- +- etb@740000 { +- compatible = "arm,coresight-etb10", "arm,primecell"; +- reg = <0x740000 0x1000>; +- +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- clock-names = "apb_pclk"; +- +- in-ports { +- port { +- etb_in: endpoint { +- remote-endpoint = <&etm_out>; +- }; +- }; +- }; +- }; +- +- etm@73c000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0x73c000 0x1000>; +- +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etm_out: endpoint { +- remote-endpoint = <&etb_in>; +- }; +- }; +- }; +- }; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x20000000>; +- }; +- +- clocks { +- slow_xtal: slow_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- main_xtal: main_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- }; +- +- ns_sram: sram@200000 { +- compatible = "mmio-sram"; +- reg = <0x00200000 0x20000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00200000 0x20000>; +- }; +- +- ahb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- nfc_sram: sram@100000 { +- compatible = "mmio-sram"; +- no-memory-wc; +- reg = <0x00100000 0x2400>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00100000 0x2400>; +- +- }; +- +- usb0: gadget@300000 { +- compatible = "atmel,sama5d3-udc"; +- reg = <0x00300000 0x100000 +- 0xfc02c000 0x400>; +- interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; +- clock-names = "pclk", "hclk"; +- status = "disabled"; +- }; +- +- usb1: ohci@400000 { +- compatible = "atmel,at91rm9200-ohci", "usb-ohci"; +- reg = <0x00400000 0x100000>; +- interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>; +- clock-names = "ohci_clk", "hclk", "uhpck"; +- status = "disabled"; +- }; +- +- usb2: ehci@500000 { +- compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; +- reg = <0x00500000 0x100000>; +- interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>; +- clock-names = "usb_clk", "ehci_clk"; +- status = "disabled"; +- }; +- +- L2: cache-controller@a00000 { +- compatible = "arm,pl310-cache"; +- reg = <0x00a00000 0x1000>; +- interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; +- cache-unified; +- cache-level = <2>; +- }; +- +- ebi: ebi@10000000 { +- compatible = "atmel,sama5d3-ebi"; +- #address-cells = <2>; +- #size-cells = <1>; +- atmel,smc = <&hsmc>; +- reg = <0x10000000 0x10000000 +- 0x60000000 0x30000000>; +- ranges = <0x0 0x0 0x10000000 0x10000000 +- 0x1 0x0 0x60000000 0x10000000 +- 0x2 0x0 0x70000000 0x10000000 +- 0x3 0x0 0x80000000 0x10000000>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; +- status = "disabled"; +- +- nand_controller: nand-controller { +- compatible = "atmel,sama5d3-nand-controller"; +- atmel,nfc-sram = <&nfc_sram>; +- atmel,nfc-io = <&nfc_io>; +- ecc-engine = <&pmecc>; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- }; +- }; +- +- sdmmc0: sdio-host@a0000000 { +- compatible = "atmel,sama5d2-sdhci"; +- reg = <0xa0000000 0x300>; +- interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>; +- clock-names = "hclock", "multclk", "baseclk"; +- assigned-clocks = <&pmc PMC_TYPE_GCK 31>; +- assigned-clock-rates = <480000000>; +- status = "disabled"; +- }; +- +- sdmmc1: sdio-host@b0000000 { +- compatible = "atmel,sama5d2-sdhci"; +- reg = <0xb0000000 0x300>; +- interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>; +- clock-names = "hclock", "multclk", "baseclk"; +- assigned-clocks = <&pmc PMC_TYPE_GCK 32>; +- assigned-clock-rates = <480000000>; +- status = "disabled"; +- }; +- +- nfc_io: nfc-io@c0000000 { +- compatible = "atmel,sama5d3-nfc-io", "syscon"; +- reg = <0xc0000000 0x8000000>; +- }; +- +- apb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- hlcdc: hlcdc@f0000000 { +- compatible = "atmel,sama5d2-hlcdc"; +- reg = <0xf0000000 0x2000>; +- interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; +- clock-names = "periph_clk","sys_clk", "slow_clk"; +- status = "disabled"; +- +- hlcdc-display-controller { +- compatible = "atmel,hlcdc-display-controller"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- }; +- +- hlcdc_pwm: hlcdc-pwm { +- compatible = "atmel,hlcdc-pwm"; +- #pwm-cells = <3>; +- }; +- }; +- +- isc: isc@f0008000 { +- compatible = "atmel,sama5d2-isc"; +- reg = <0xf0008000 0x4000>; +- interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>; +- clock-names = "hclock", "iscck", "gck"; +- #clock-cells = <0>; +- clock-output-names = "isc-mck"; +- status = "disabled"; +- }; +- +- ramc0: ramc@f000c000 { +- compatible = "atmel,sama5d3-ddramc"; +- reg = <0xf000c000 0x200>; +- clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>; +- clock-names = "ddrck", "mpddr"; +- }; +- +- dma0: dma-controller@f0010000 { +- compatible = "atmel,sama5d4-dma"; +- reg = <0xf0010000 0x1000>; +- interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; +- #dma-cells = <1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; +- clock-names = "dma_clk"; +- }; +- +- /* Place dma1 here despite its address */ +- dma1: dma-controller@f0004000 { +- compatible = "atmel,sama5d4-dma"; +- reg = <0xf0004000 0x1000>; +- interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>; +- #dma-cells = <1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; +- clock-names = "dma_clk"; +- }; +- +- pmc: pmc@f0014000 { +- compatible = "atmel,sama5d2-pmc", "syscon"; +- reg = <0xf0014000 0x160>; +- interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; +- #clock-cells = <2>; +- clocks = <&clk32k>, <&main_xtal>; +- clock-names = "slow_clk", "main_xtal"; +- }; +- +- qspi0: spi@f0020000 { +- compatible = "atmel,sama5d2-qspi"; +- reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; +- reg-names = "qspi_base", "qspi_mmap"; +- interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- qspi1: spi@f0024000 { +- compatible = "atmel,sama5d2-qspi"; +- reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; +- reg-names = "qspi_base", "qspi_mmap"; +- interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- sha@f0028000 { +- compatible = "atmel,at91sam9g46-sha"; +- reg = <0xf0028000 0x100>; +- interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(30))>; +- dma-names = "tx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; +- clock-names = "sha_clk"; +- status = "okay"; +- }; +- +- aes@f002c000 { +- compatible = "atmel,at91sam9g46-aes"; +- reg = <0xf002c000 0x100>; +- interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(26))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(27))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; +- clock-names = "aes_clk"; +- status = "okay"; +- }; +- +- spi0: spi@f8000000 { +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xf8000000 0x100>; +- interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(6))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(7))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; +- clock-names = "spi_clk"; +- atmel,fifo-size = <16>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- ssc0: ssc@f8004000 { +- compatible = "atmel,at91sam9g45-ssc"; +- reg = <0xf8004000 0x4000>; +- interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(21))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(22))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; +- clock-names = "pclk"; +- status = "disabled"; +- }; +- +- macb0: ethernet@f8008000 { +- compatible = "atmel,sama5d2-gem"; +- reg = <0xf8008000 0x1000>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ +- 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ +- 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; +- clock-names = "hclk", "pclk"; +- status = "disabled"; +- }; +- +- tcb0: timer@f800c000 { +- compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xf800c000 0x100>; +- interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>; +- clock-names = "t0_clk", "gclk", "slow_clk"; +- }; +- +- tcb1: timer@f8010000 { +- compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xf8010000 0x100>; +- interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>; +- clock-names = "t0_clk", "gclk", "slow_clk"; +- }; +- +- hsmc: hsmc@f8014000 { +- compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; +- reg = <0xf8014000 0x1000>; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- pmecc: ecc-engine@f8014070 { +- compatible = "atmel,sama5d2-pmecc"; +- reg = <0xf8014070 0x490>, +- <0xf8014500 0x100>; +- }; +- }; +- +- pdmic: pdmic@f8018000 { +- compatible = "atmel,sama5d2-pdmic"; +- reg = <0xf8018000 0x124>; +- interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(50))>; +- dma-names = "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>; +- clock-names = "pclk", "gclk"; +- status = "disabled"; +- }; +- +- uart0: serial@f801c000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf801c000 0x100>; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(35))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(36))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- uart1: serial@f8020000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf8020000 0x100>; +- interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(37))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(38))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- uart2: serial@f8024000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf8024000 0x100>; +- interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(39))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(40))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- i2c0: i2c@f8028000 { +- compatible = "atmel,sama5d2-i2c"; +- reg = <0xf8028000 0x100>; +- interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(0))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(1))>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; +- atmel,fifo-size = <16>; +- status = "disabled"; +- }; +- +- pwm0: pwm@f802c000 { +- compatible = "atmel,sama5d2-pwm"; +- reg = <0xf802c000 0x4000>; +- interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>; +- #pwm-cells = <3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; +- status = "disabled"; +- }; +- +- sfr: sfr@f8030000 { +- compatible = "atmel,sama5d2-sfr", "syscon"; +- reg = <0xf8030000 0x98>; +- }; +- +- flx0: flexcom@f8034000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xf8034000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf8034000 0x800>; +- status = "disabled"; +- +- uart5: serial@200 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0x200 0x200>; +- interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; +- clock-names = "usart"; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(11))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(12))>; +- dma-names = "tx", "rx"; +- atmel,fifo-size = <32>; +- status = "disabled"; +- }; +- +- spi2: spi@400 { +- compatible = "atmel,at91rm9200-spi"; +- reg = <0x400 0x200>; +- interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; +- clock-names = "spi_clk"; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(11))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(12))>; +- dma-names = "tx", "rx"; +- atmel,fifo-size = <16>; +- status = "disabled"; +- }; +- +- i2c2: i2c@600 { +- compatible = "atmel,sama5d2-i2c"; +- reg = <0x600 0x200>; +- interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(11))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(12))>; +- dma-names = "tx", "rx"; +- atmel,fifo-size = <16>; +- status = "disabled"; +- }; +- }; +- +- flx1: flexcom@f8038000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xf8038000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xf8038000 0x800>; +- status = "disabled"; +- +- uart6: serial@200 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0x200 0x200>; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; +- clock-names = "usart"; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(13))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(14))>; +- dma-names = "tx", "rx"; +- atmel,fifo-size = <32>; +- status = "disabled"; +- }; +- +- spi3: spi@400 { +- compatible = "atmel,at91rm9200-spi"; +- reg = <0x400 0x200>; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; +- clock-names = "spi_clk"; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(13))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(14))>; +- dma-names = "tx", "rx"; +- atmel,fifo-size = <16>; +- status = "disabled"; +- }; +- +- i2c3: i2c@600 { +- compatible = "atmel,sama5d2-i2c"; +- reg = <0x600 0x200>; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(13))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(14))>; +- dma-names = "tx", "rx"; +- atmel,fifo-size = <16>; +- status = "disabled"; +- }; +- }; +- +- securam: sram@f8044000 { +- compatible = "atmel,sama5d2-securam", "mmio-sram"; +- reg = <0xf8044000 0x1420>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; +- #address-cells = <1>; +- #size-cells = <1>; +- no-memory-wc; +- ranges = <0 0xf8044000 0x1420>; +- }; +- +- reset_controller: rstc@f8048000 { +- compatible = "atmel,sama5d3-rstc"; +- reg = <0xf8048000 0x10>; +- clocks = <&clk32k>; +- }; +- +- shutdown_controller: shdwc@f8048010 { +- compatible = "atmel,sama5d2-shdwc"; +- reg = <0xf8048010 0x10>; +- clocks = <&clk32k>; +- #address-cells = <1>; +- #size-cells = <0>; +- atmel,wakeup-rtc-timer; +- }; +- +- pit: timer@f8048030 { +- compatible = "atmel,at91sam9260-pit"; +- reg = <0xf8048030 0x10>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; +- }; +- +- watchdog: watchdog@f8048040 { +- compatible = "atmel,sama5d4-wdt"; +- reg = <0xf8048040 0x10>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&clk32k>; +- status = "disabled"; +- }; +- +- clk32k: sckc@f8048050 { +- compatible = "atmel,sama5d4-sckc"; +- reg = <0xf8048050 0x4>; +- +- clocks = <&slow_xtal>; +- #clock-cells = <0>; +- }; +- +- rtc: rtc@f80480b0 { +- compatible = "atmel,sama5d2-rtc"; +- reg = <0xf80480b0 0x30>; +- interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&clk32k>; +- }; +- +- i2s0: i2s@f8050000 { +- compatible = "atmel,sama5d2-i2s"; +- reg = <0xf8050000 0x100>; +- interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(31))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(32))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>; +- clock-names = "pclk", "gclk"; +- assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>; +- assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>; +- status = "disabled"; +- }; +- +- can0: can@f8054000 { +- compatible = "bosch,m_can"; +- reg = <0xf8054000 0x4000>, <0x210000 0x1c00>; +- reg-names = "m_can", "message_ram"; +- interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, +- <64 IRQ_TYPE_LEVEL_HIGH 7>; +- interrupt-names = "int0", "int1"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>; +- clock-names = "hclk", "cclk"; +- assigned-clocks = <&pmc PMC_TYPE_GCK 56>; +- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; +- assigned-clock-rates = <40000000>; +- bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; +- status = "disabled"; +- }; +- +- spi1: spi@fc000000 { +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xfc000000 0x100>; +- interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(8))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(9))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; +- clock-names = "spi_clk"; +- atmel,fifo-size = <16>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- uart3: serial@fc008000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfc008000 0x100>; +- interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; +- dmas = <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(41))>, +- <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(42))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- uart4: serial@fc00c000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfc00c000 0x100>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(43))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(44))>; +- dma-names = "tx", "rx"; +- interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- flx2: flexcom@fc010000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xfc010000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xfc010000 0x800>; +- status = "disabled"; +- +- uart7: serial@200 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0x200 0x200>; +- interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; +- clock-names = "usart"; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(15))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(16))>; +- dma-names = "tx", "rx"; +- atmel,fifo-size = <32>; +- status = "disabled"; +- }; +- +- spi4: spi@400 { +- compatible = "atmel,at91rm9200-spi"; +- reg = <0x400 0x200>; +- interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; +- clock-names = "spi_clk"; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(15))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(16))>; +- dma-names = "tx", "rx"; +- atmel,fifo-size = <16>; +- status = "disabled"; +- }; +- +- i2c4: i2c@600 { +- compatible = "atmel,sama5d2-i2c"; +- reg = <0x600 0x200>; +- interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(15))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(16))>; +- dma-names = "tx", "rx"; +- atmel,fifo-size = <16>; +- status = "disabled"; +- }; +- }; +- +- flx3: flexcom@fc014000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xfc014000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xfc014000 0x800>; +- status = "disabled"; +- +- uart8: serial@200 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0x200 0x200>; +- interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; +- clock-names = "usart"; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(17))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(18))>; +- dma-names = "tx", "rx"; +- atmel,fifo-size = <32>; +- status = "disabled"; +- }; +- +- spi5: spi@400 { +- compatible = "atmel,at91rm9200-spi"; +- reg = <0x400 0x200>; +- interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; +- clock-names = "spi_clk"; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(17))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(18))>; +- dma-names = "tx", "rx"; +- atmel,fifo-size = <16>; +- status = "disabled"; +- }; +- +- i2c5: i2c@600 { +- compatible = "atmel,sama5d2-i2c"; +- reg = <0x600 0x200>; +- interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(17))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(18))>; +- dma-names = "tx", "rx"; +- atmel,fifo-size = <16>; +- status = "disabled"; +- }; +- +- }; +- +- flx4: flexcom@fc018000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xfc018000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xfc018000 0x800>; +- status = "disabled"; +- +- uart9: serial@200 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0x200 0x200>; +- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; +- clock-names = "usart"; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(19))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(20))>; +- dma-names = "tx", "rx"; +- atmel,fifo-size = <32>; +- status = "disabled"; +- }; +- +- spi6: spi@400 { +- compatible = "atmel,at91rm9200-spi"; +- reg = <0x400 0x200>; +- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; +- clock-names = "spi_clk"; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(19))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(20))>; +- dma-names = "tx", "rx"; +- atmel,fifo-size = <16>; +- status = "disabled"; +- }; +- +- i2c6: i2c@600 { +- compatible = "atmel,sama5d2-i2c"; +- reg = <0x600 0x200>; +- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(19))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | +- AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(20))>; +- dma-names = "tx", "rx"; +- atmel,fifo-size = <16>; +- status = "disabled"; +- }; +- }; +- +- trng@fc01c000 { +- compatible = "atmel,at91sam9g45-trng"; +- reg = <0xfc01c000 0x100>; +- interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; +- }; +- +- aic: interrupt-controller@fc020000 { +- #interrupt-cells = <3>; +- compatible = "atmel,sama5d2-aic"; +- interrupt-controller; +- reg = <0xfc020000 0x200>; +- atmel,external-irqs = <49>; +- }; +- +- i2c1: i2c@fc028000 { +- compatible = "atmel,sama5d2-i2c"; +- reg = <0xfc028000 0x100>; +- interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(2))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(3))>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; +- atmel,fifo-size = <16>; +- status = "disabled"; +- }; +- +- adc: adc@fc030000 { +- compatible = "atmel,sama5d2-adc"; +- reg = <0xfc030000 0x100>; +- interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; +- clock-names = "adc_clk"; +- dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; +- dma-names = "rx"; +- atmel,min-sample-rate-hz = <200000>; +- atmel,max-sample-rate-hz = <20000000>; +- atmel,startup-time-ms = <4>; +- atmel,trigger-edge-type = ; +- #io-channel-cells = <1>; +- status = "disabled"; +- }; +- +- resistive_touch: resistive-touch { +- compatible = "resistive-adc-touch"; +- io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, +- <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, +- <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; +- io-channel-names = "x", "y", "pressure"; +- touchscreen-min-pressure = <50000>; +- status = "disabled"; +- }; +- +- pioA: pinctrl@fc038000 { +- compatible = "atmel,sama5d2-pinctrl"; +- reg = <0xfc038000 0x600>; +- interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, +- <68 IRQ_TYPE_LEVEL_HIGH 7>, +- <69 IRQ_TYPE_LEVEL_HIGH 7>, +- <70 IRQ_TYPE_LEVEL_HIGH 7>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; +- }; +- +- pioBU: secumod@fc040000 { +- compatible = "atmel,sama5d2-secumod", "syscon"; +- reg = <0xfc040000 0x100>; +- +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- tdes@fc044000 { +- compatible = "atmel,at91sam9g46-tdes"; +- reg = <0xfc044000 0x100>; +- interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(28))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(29))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; +- clock-names = "tdes_clk"; +- status = "okay"; +- }; +- +- classd: classd@fc048000 { +- compatible = "atmel,sama5d2-classd"; +- reg = <0xfc048000 0x100>; +- interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(47))>; +- dma-names = "tx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; +- clock-names = "pclk", "gclk"; +- status = "disabled"; +- }; +- +- i2s1: i2s@fc04c000 { +- compatible = "atmel,sama5d2-i2s"; +- reg = <0xfc04c000 0x100>; +- interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(33))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | +- AT91_XDMAC_DT_PERID(34))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; +- clock-names = "pclk", "gclk"; +- assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; +- assigned-parrents = <&pmc PMC_TYPE_GCK 55>; +- status = "disabled"; +- }; +- +- can1: can@fc050000 { +- compatible = "bosch,m_can"; +- reg = <0xfc050000 0x4000>, <0x210000 0x3800>; +- reg-names = "m_can", "message_ram"; +- interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, +- <65 IRQ_TYPE_LEVEL_HIGH 7>; +- interrupt-names = "int0", "int1"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; +- clock-names = "hclk", "cclk"; +- assigned-clocks = <&pmc PMC_TYPE_GCK 57>; +- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; +- assigned-clock-rates = <40000000>; +- bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>; +- status = "disabled"; +- }; +- +- sfrbu: sfr@fc05c000 { +- compatible = "atmel,sama5d2-sfrbu", "syscon"; +- reg = <0xfc05c000 0x20>; +- }; +- +- chipid@fc069000 { +- compatible = "atmel,sama5d2-chipid"; +- reg = <0xfc069000 0x8>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d3.dtsi b/scripts/dtc/include-prefixes/arm/sama5d3.dtsi +deleted file mode 100644 +index d1841bffe3c5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d3.dtsi ++++ /dev/null +@@ -1,1119 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC +- * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC +- * +- * Copyright (C) 2013 Atmel, +- * 2013 Ludovic Desroches +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Atmel SAMA5D3 family SoC"; +- compatible = "atmel,sama5d3", "atmel,sama5"; +- interrupt-parent = <&aic>; +- +- aliases { +- serial0 = &dbgu; +- serial1 = &usart0; +- serial2 = &usart1; +- serial3 = &usart2; +- serial4 = &usart3; +- serial5 = &uart0; +- gpio0 = &pioA; +- gpio1 = &pioB; +- gpio2 = &pioC; +- gpio3 = &pioD; +- gpio4 = &pioE; +- tcb0 = &tcb0; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- ssc0 = &ssc0; +- ssc1 = &ssc1; +- pwm0 = &pwm0; +- }; +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a5"; +- reg = <0x0>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a5-pmu"; +- interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>; +- }; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x8000000>; +- }; +- +- clocks { +- slow_xtal: slow_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- main_xtal: main_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- adc_op_clk: adc_op_clk{ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <1000000>; +- }; +- }; +- +- sram: sram@300000 { +- compatible = "mmio-sram"; +- reg = <0x00300000 0x20000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00300000 0x20000>; +- }; +- +- ahb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- apb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- mmc0: mmc@f0000000 { +- compatible = "atmel,hsmci"; +- reg = <0xf0000000 0x600>; +- interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>; +- dma-names = "rxtx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; +- clock-names = "mci_clk"; +- }; +- +- spi0: spi@f0004000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xf0004000 0x100>; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; +- dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>, +- <&dma0 2 AT91_DMA_CFG_PER_ID(2)>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; +- clock-names = "spi_clk"; +- status = "disabled"; +- }; +- +- ssc0: ssc@f0008000 { +- compatible = "atmel,at91sam9g45-ssc"; +- reg = <0xf0008000 0x4000>; +- interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; +- dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>, +- <&dma0 2 AT91_DMA_CFG_PER_ID(14)>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; +- clock-names = "pclk"; +- status = "disabled"; +- }; +- +- tcb0: timer@f0010000 { +- compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xf0010000 0x100>; +- interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&clk32k>; +- clock-names = "t0_clk", "slow_clk"; +- }; +- +- i2c0: i2c@f0014000 { +- compatible = "atmel,at91sam9x5-i2c"; +- reg = <0xf0014000 0x4000>; +- interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>; +- dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>, +- <&dma0 2 AT91_DMA_CFG_PER_ID(8)>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c0>; +- pinctrl-1 = <&pinctrl_i2c0_gpio>; +- sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; +- status = "disabled"; +- }; +- +- i2c1: i2c@f0018000 { +- compatible = "atmel,at91sam9x5-i2c"; +- reg = <0xf0018000 0x4000>; +- interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>; +- dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>, +- <&dma0 2 AT91_DMA_CFG_PER_ID(10)>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c1>; +- pinctrl-1 = <&pinctrl_i2c1_gpio>; +- sda-gpios = <&pioC 26 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&pioC 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; +- status = "disabled"; +- }; +- +- usart0: serial@f001c000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf001c000 0x100>; +- interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; +- dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, +- <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart1: serial@f0020000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf0020000 0x100>; +- interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; +- dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>, +- <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- uart0: serial@f0024000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf0024000 0x100>; +- interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- pwm0: pwm@f002c000 { +- compatible = "atmel,sama5d3-pwm"; +- reg = <0xf002c000 0x300>; +- interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>; +- #pwm-cells = <3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; +- status = "disabled"; +- }; +- +- isi: isi@f0034000 { +- compatible = "atmel,at91sam9g45-isi"; +- reg = <0xf0034000 0x4000>; +- interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_isi_data_0_7>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; +- clock-names = "isi_clk"; +- status = "disabled"; +- port { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- sfr: sfr@f0038000 { +- compatible = "atmel,sama5d3-sfr", "syscon"; +- reg = <0xf0038000 0x60>; +- }; +- +- mmc1: mmc@f8000000 { +- compatible = "atmel,hsmci"; +- reg = <0xf8000000 0x600>; +- interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>; +- dma-names = "rxtx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; +- clock-names = "mci_clk"; +- }; +- +- spi1: spi@f8008000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xf8008000 0x100>; +- interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; +- dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>, +- <&dma1 2 AT91_DMA_CFG_PER_ID(16)>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; +- clock-names = "spi_clk"; +- status = "disabled"; +- }; +- +- ssc1: ssc@f800c000 { +- compatible = "atmel,at91sam9g45-ssc"; +- reg = <0xf800c000 0x4000>; +- interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; +- dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>, +- <&dma1 2 AT91_DMA_CFG_PER_ID(4)>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; +- clock-names = "pclk"; +- status = "disabled"; +- }; +- +- adc0: adc@f8018000 { +- compatible = "atmel,sama5d3-adc"; +- reg = <0xf8018000 0x100>; +- interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = < +- &pinctrl_adc0_adtrg +- &pinctrl_adc0_ad0 +- &pinctrl_adc0_ad1 +- &pinctrl_adc0_ad2 +- &pinctrl_adc0_ad3 +- &pinctrl_adc0_ad4 +- &pinctrl_adc0_ad5 +- &pinctrl_adc0_ad6 +- &pinctrl_adc0_ad7 +- &pinctrl_adc0_ad8 +- &pinctrl_adc0_ad9 +- &pinctrl_adc0_ad10 +- &pinctrl_adc0_ad11 +- >; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, +- <&adc_op_clk>; +- clock-names = "adc_clk", "adc_op_clk"; +- atmel,adc-channels-used = <0xfff>; +- atmel,adc-startup-time = <40>; +- atmel,adc-use-external-triggers; +- atmel,adc-vref = <3000>; +- atmel,adc-sample-hold-time = <11>; +- status = "disabled"; +- }; +- +- i2c2: i2c@f801c000 { +- compatible = "atmel,at91sam9x5-i2c"; +- reg = <0xf801c000 0x4000>; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>; +- dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, +- <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c2>; +- pinctrl-1 = <&pinctrl_i2c2_gpio>; +- sda-gpios = <&pioA 18 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&pioA 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; +- status = "disabled"; +- }; +- +- usart2: serial@f8020000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf8020000 0x100>; +- interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; +- dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>, +- <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart3: serial@f8024000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf8024000 0x100>; +- interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; +- dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>, +- <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- sha@f8034000 { +- compatible = "atmel,at91sam9g46-sha"; +- reg = <0xf8034000 0x100>; +- interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; +- dma-names = "tx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; +- clock-names = "sha_clk"; +- }; +- +- aes@f8038000 { +- compatible = "atmel,at91sam9g46-aes"; +- reg = <0xf8038000 0x100>; +- interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, +- <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; +- clock-names = "aes_clk"; +- }; +- +- tdes@f803c000 { +- compatible = "atmel,at91sam9g46-tdes"; +- reg = <0xf803c000 0x100>; +- interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, +- <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; +- clock-names = "tdes_clk"; +- }; +- +- trng@f8040000 { +- compatible = "atmel,at91sam9g45-trng"; +- reg = <0xf8040000 0x100>; +- interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; +- }; +- +- hsmc: hsmc@ffffc000 { +- compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; +- reg = <0xffffc000 0x1000>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- pmecc: ecc-engine@ffffc070 { +- compatible = "atmel,at91sam9g45-pmecc"; +- reg = <0xffffc070 0x490>, +- <0xffffc500 0x100>; +- }; +- }; +- +- dma0: dma-controller@ffffe600 { +- compatible = "atmel,at91sam9g45-dma"; +- reg = <0xffffe600 0x200>; +- interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; +- #dma-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; +- clock-names = "dma_clk"; +- }; +- +- dma1: dma-controller@ffffe800 { +- compatible = "atmel,at91sam9g45-dma"; +- reg = <0xffffe800 0x200>; +- interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; +- #dma-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 31>; +- clock-names = "dma_clk"; +- }; +- +- ramc0: ramc@ffffea00 { +- compatible = "atmel,sama5d3-ddramc"; +- reg = <0xffffea00 0x200>; +- clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>; +- clock-names = "ddrck", "mpddr"; +- }; +- +- dbgu: serial@ffffee00 { +- compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; +- reg = <0xffffee00 0x200>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; +- dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>, +- <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dbgu>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- aic: interrupt-controller@fffff000 { +- #interrupt-cells = <3>; +- compatible = "atmel,sama5d3-aic"; +- interrupt-controller; +- reg = <0xfffff000 0x200>; +- atmel,external-irqs = <47>; +- }; +- +- pinctrl: pinctrl@fffff200 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; +- ranges = <0xfffff200 0xfffff200 0xa00>; +- atmel,mux-mask = < +- /* A B C */ +- 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ +- 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ +- 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ +- 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ +- 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ +- >; +- +- /* shared pinctrl settings */ +- adc0 { +- pinctrl_adc0_adtrg: adc0_adtrg { +- atmel,pins = +- ; /* PD19 periph A ADTRG */ +- }; +- pinctrl_adc0_ad0: adc0_ad0 { +- atmel,pins = +- ; /* PD20 periph A AD0 */ +- }; +- pinctrl_adc0_ad1: adc0_ad1 { +- atmel,pins = +- ; /* PD21 periph A AD1 */ +- }; +- pinctrl_adc0_ad2: adc0_ad2 { +- atmel,pins = +- ; /* PD22 periph A AD2 */ +- }; +- pinctrl_adc0_ad3: adc0_ad3 { +- atmel,pins = +- ; /* PD23 periph A AD3 */ +- }; +- pinctrl_adc0_ad4: adc0_ad4 { +- atmel,pins = +- ; /* PD24 periph A AD4 */ +- }; +- pinctrl_adc0_ad5: adc0_ad5 { +- atmel,pins = +- ; /* PD25 periph A AD5 */ +- }; +- pinctrl_adc0_ad6: adc0_ad6 { +- atmel,pins = +- ; /* PD26 periph A AD6 */ +- }; +- pinctrl_adc0_ad7: adc0_ad7 { +- atmel,pins = +- ; /* PD27 periph A AD7 */ +- }; +- pinctrl_adc0_ad8: adc0_ad8 { +- atmel,pins = +- ; /* PD28 periph A AD8 */ +- }; +- pinctrl_adc0_ad9: adc0_ad9 { +- atmel,pins = +- ; /* PD29 periph A AD9 */ +- }; +- pinctrl_adc0_ad10: adc0_ad10 { +- atmel,pins = +- ; /* PD30 periph A AD10, conflicts with PCK0 */ +- }; +- pinctrl_adc0_ad11: adc0_ad11 { +- atmel,pins = +- ; /* PD31 periph A AD11, conflicts with PCK1 */ +- }; +- }; +- +- dbgu { +- pinctrl_dbgu: dbgu-0 { +- atmel,pins = +- ; +- }; +- }; +- +- ebi { +- pinctrl_ebi_addr: ebi-addr-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_nand_addr: ebi-addr-1 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_cs0: ebi-cs0-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_cs1: ebi-cs1-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_cs2: ebi-cs2-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_nwait: ebi-nwait-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 { +- atmel,pins = +- ; +- }; +- }; +- +- i2c0 { +- pinctrl_i2c0: i2c0-0 { +- atmel,pins = +- ; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ +- }; +- +- pinctrl_i2c0_gpio: i2c0-gpio { +- atmel,pins = +- ; +- }; +- }; +- +- i2c1 { +- pinctrl_i2c1: i2c1-0 { +- atmel,pins = +- ; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ +- }; +- +- pinctrl_i2c1_gpio: i2c1-gpio { +- atmel,pins = +- ; +- }; +- }; +- +- i2c2 { +- pinctrl_i2c2: i2c2-0 { +- atmel,pins = +- ; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */ +- }; +- +- pinctrl_i2c2_gpio: i2c2-gpio { +- atmel,pins = +- ; +- }; +- }; +- +- isi { +- pinctrl_isi_data_0_7: isi-0-data-0-7 { +- atmel,pins = +- ; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ +- }; +- +- pinctrl_isi_data_8_9: isi-0-data-8-9 { +- atmel,pins = +- ; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ +- }; +- +- pinctrl_isi_data_10_11: isi-0-data-10-11 { +- atmel,pins = +- ; /* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */ +- }; +- }; +- +- mmc0 { +- pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { +- atmel,pins = +- ; /* PD1 periph A MCI0_DA0 with pullup */ +- }; +- pinctrl_mmc0_dat1_3: mmc0_dat1_3 { +- atmel,pins = +- ; /* PD4 periph A MCI0_DA3 with pullup */ +- }; +- pinctrl_mmc0_dat4_7: mmc0_dat4_7 { +- atmel,pins = +- ; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ +- }; +- }; +- +- mmc1 { +- pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { +- atmel,pins = +- ; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ +- }; +- pinctrl_mmc1_dat1_3: mmc1_dat1_3 { +- atmel,pins = +- ; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ +- }; +- }; +- +- nand0 { +- pinctrl_nand0_ale_cle: nand0_ale_cle-0 { +- atmel,pins = +- ; /* PE22 periph A with pullup */ +- }; +- }; +- +- pwm0 { +- pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 { +- atmel,pins = +- ; /* conflicts with ISI_D4 and LCDDAT20 */ +- }; +- pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 { +- atmel,pins = +- ; /* conflicts with GTX0 */ +- }; +- pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 { +- atmel,pins = +- ; /* conflicts with ISI_D5 and LCDDAT21 */ +- }; +- pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 { +- atmel,pins = +- ; /* conflicts with GTX1 */ +- }; +- +- pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 { +- atmel,pins = +- ; /* conflicts with ISI_D6 and LCDDAT22 */ +- }; +- pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 { +- atmel,pins = +- ; /* conflicts with GRX0 */ +- }; +- pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 { +- atmel,pins = +- ; /* conflicts with G125CKO and RTS1 */ +- }; +- pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 { +- atmel,pins = +- ; /* conflicts with ISI_D7 and LCDDAT23 */ +- }; +- pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 { +- atmel,pins = +- ; /* conflicts with GRX1 */ +- }; +- pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 { +- atmel,pins = +- ; /* conflicts with IRQ */ +- }; +- +- pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 { +- atmel,pins = +- ; /* conflicts with GTXCK */ +- }; +- pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 { +- atmel,pins = +- ; /* conflicts with MCI0_DA4 and TIOA0 */ +- }; +- pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 { +- atmel,pins = +- ; /* conflicts with GTXEN */ +- }; +- pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 { +- atmel,pins = +- ; /* conflicts with MCI0_DA5 and TIOB0 */ +- }; +- +- pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 { +- atmel,pins = +- ; /* conflicts with GRXDV */ +- }; +- pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 { +- atmel,pins = +- ; /* conflicts with MCI0_DA6 and TCLK0 */ +- }; +- pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 { +- atmel,pins = +- ; /* conflicts with GRXER */ +- }; +- pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 { +- atmel,pins = +- ; /* conflicts with MCI0_DA7 */ +- }; +- }; +- +- spi0 { +- pinctrl_spi0: spi0-0 { +- atmel,pins = +- ; /* PD12 periph A SPI0_SPCK pin */ +- }; +- }; +- +- spi1 { +- pinctrl_spi1: spi1-0 { +- atmel,pins = +- ; /* PC24 periph A SPI1_SPCK pin */ +- }; +- }; +- +- ssc0 { +- pinctrl_ssc0_tx: ssc0_tx { +- atmel,pins = +- ; /* PC18 periph A TD0 */ +- }; +- +- pinctrl_ssc0_rx: ssc0_rx { +- atmel,pins = +- ; /* PC21 periph A RD0 */ +- }; +- }; +- +- ssc1 { +- pinctrl_ssc1_tx: ssc1_tx { +- atmel,pins = +- ; /* PB6 periph B TD1, conflicts with TD1 */ +- }; +- +- pinctrl_ssc1_rx: ssc1_rx { +- atmel,pins = +- ; /* PB11 periph B RD1, conflicts with GRXCK */ +- }; +- }; +- +- uart0 { +- pinctrl_uart0: uart0-0 { +- atmel,pins = +- ; /* conflicts with ISI_PCK */ +- }; +- }; +- +- uart1 { +- pinctrl_uart1: uart1-0 { +- atmel,pins = +- ; /* conflicts with TWCK0, ISI_HSYNC */ +- }; +- }; +- +- usart0 { +- pinctrl_usart0: usart0-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart0_rts_cts: usart0_rts_cts-0 { +- atmel,pins = +- ; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ +- }; +- }; +- +- usart1 { +- pinctrl_usart1: usart1-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usart1_rts_cts: usart1_rts_cts-0 { +- atmel,pins = +- ; /* PB27 periph A, conflicts with G125CKO */ +- }; +- }; +- +- usart2 { +- pinctrl_usart2: usart2-0 { +- atmel,pins = +- ; /* conflicts NCS0 */ +- }; +- +- pinctrl_usart2_rts_cts: usart2_rts_cts-0 { +- atmel,pins = +- ; /* PE24 periph B, conflicts with A24 */ +- }; +- }; +- +- usart3 { +- pinctrl_usart3: usart3-0 { +- atmel,pins = +- ; /* conflicts with A19 */ +- }; +- +- pinctrl_usart3_rts_cts: usart3_rts_cts-0 { +- atmel,pins = +- ; /* PE17 periph B, conflicts with A17 */ +- }; +- }; +- +- +- pioA: gpio@fffff200 { +- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfffff200 0x100>; +- interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; +- }; +- +- pioB: gpio@fffff400 { +- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfffff400 0x100>; +- interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; +- }; +- +- pioC: gpio@fffff600 { +- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfffff600 0x100>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; +- }; +- +- pioD: gpio@fffff800 { +- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfffff800 0x100>; +- interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; +- }; +- +- pioE: gpio@fffffa00 { +- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfffffa00 0x100>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; +- }; +- }; +- +- pmc: pmc@fffffc00 { +- compatible = "atmel,sama5d3-pmc", "syscon"; +- reg = <0xfffffc00 0x120>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- #clock-cells = <2>; +- clocks = <&clk32k>, <&main_xtal>; +- clock-names = "slow_clk", "main_xtal"; +- }; +- +- reset_controller: rstc@fffffe00 { +- compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; +- reg = <0xfffffe00 0x10>; +- clocks = <&clk32k>; +- }; +- +- shutdown_controller: shutdown-controller@fffffe10 { +- compatible = "atmel,at91sam9x5-shdwc"; +- reg = <0xfffffe10 0x10>; +- clocks = <&clk32k>; +- }; +- +- pit: timer@fffffe30 { +- compatible = "atmel,at91sam9260-pit"; +- reg = <0xfffffe30 0xf>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- }; +- +- watchdog: watchdog@fffffe40 { +- compatible = "atmel,at91sam9260-wdt"; +- reg = <0xfffffe40 0x10>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&clk32k>; +- atmel,watchdog-type = "hardware"; +- atmel,reset-type = "all"; +- atmel,dbg-halt; +- status = "disabled"; +- }; +- +- clk32k: sckc@fffffe50 { +- compatible = "atmel,sama5d3-sckc"; +- reg = <0xfffffe50 0x4>; +- clocks = <&slow_xtal>; +- #clock-cells = <0>; +- }; +- +- rtc@fffffeb0 { +- compatible = "atmel,at91rm9200-rtc"; +- reg = <0xfffffeb0 0x30>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&clk32k>; +- }; +- }; +- +- nfc_sram: sram@200000 { +- compatible = "mmio-sram"; +- no-memory-wc; +- reg = <0x200000 0x2400>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x200000 0x2400>; +- }; +- +- usb0: gadget@500000 { +- compatible = "atmel,sama5d3-udc"; +- reg = <0x00500000 0x100000 +- 0xf8030000 0x4000>; +- interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 33>, <&pmc PMC_TYPE_CORE PMC_UTMI>; +- clock-names = "pclk", "hclk"; +- status = "disabled"; +- }; +- +- usb1: ohci@600000 { +- compatible = "atmel,at91rm9200-ohci", "usb-ohci"; +- reg = <0x00600000 0x100000>; +- interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_SYSTEM 6>; +- clock-names = "ohci_clk", "hclk", "uhpck"; +- status = "disabled"; +- }; +- +- usb2: ehci@700000 { +- compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; +- reg = <0x00700000 0x100000>; +- interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 32>; +- clock-names = "usb_clk", "ehci_clk"; +- status = "disabled"; +- }; +- +- ebi: ebi@10000000 { +- compatible = "atmel,sama5d3-ebi"; +- #address-cells = <2>; +- #size-cells = <1>; +- atmel,smc = <&hsmc>; +- reg = <0x10000000 0x10000000 +- 0x40000000 0x30000000>; +- ranges = <0x0 0x0 0x10000000 0x10000000 +- 0x1 0x0 0x40000000 0x10000000 +- 0x2 0x0 0x50000000 0x10000000 +- 0x3 0x0 0x60000000 0x10000000>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- status = "disabled"; +- +- nand_controller: nand-controller { +- compatible = "atmel,sama5d3-nand-controller"; +- atmel,nfc-sram = <&nfc_sram>; +- atmel,nfc-io = <&nfc_io>; +- ecc-engine = <&pmecc>; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- }; +- }; +- +- nfc_io: nfc-io@70000000 { +- compatible = "atmel,sama5d3-nfc-io", "syscon"; +- reg = <0x70000000 0x8000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d31.dtsi b/scripts/dtc/include-prefixes/arm/sama5d31.dtsi +deleted file mode 100644 +index cbe8f275ecc4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d31.dtsi ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * sama5d31.dtsi - Device Tree Include file for SAMA5D31 SoC +- * +- * Copyright (C) 2013 Boris BREZILLON +- */ +-#include "sama5d3.dtsi" +-#include "sama5d3_lcd.dtsi" +-#include "sama5d3_emac.dtsi" +-#include "sama5d3_mci2.dtsi" +-#include "sama5d3_uart.dtsi" +- +-/ { +- compatible = "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d31ek.dts b/scripts/dtc/include-prefixes/arm/sama5d31ek.dts +deleted file mode 100644 +index 10fc80d6d30d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d31ek.dts ++++ /dev/null +@@ -1,52 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * sama5d31ek.dts - Device Tree file for SAMA5D31-EK board +- * +- * Copyright (C) 2013 Atmel, +- * 2013 Ludovic Desroches +- */ +-/dts-v1/; +-#include "sama5d31.dtsi" +-#include "sama5d3xmb.dtsi" +-#include "sama5d3xmb_emac.dtsi" +-#include "sama5d3xdm.dtsi" +- +-/ { +- model = "Atmel SAMA5D31-EK"; +- compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; +- +- ahb { +- apb { +- spi0: spi@f0004000 { +- status = "okay"; +- }; +- +- ssc0: ssc@f0008000 { +- status = "okay"; +- }; +- +- i2c0: i2c@f0014000 { +- status = "okay"; +- }; +- +- i2c1: i2c@f0018000 { +- status = "okay"; +- }; +- +- macb1: ethernet@f802c000 { +- status = "okay"; +- }; +- }; +- }; +- +- leds { +- d3 { +- label = "d3"; +- gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- sound { +- status = "okay"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d33.dtsi b/scripts/dtc/include-prefixes/arm/sama5d33.dtsi +deleted file mode 100644 +index 146fd59acea5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d33.dtsi ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * sama5d33.dtsi - Device Tree Include file for SAMA5D33 SoC +- * +- * Copyright (C) 2013 Boris BREZILLON +- */ +-#include "sama5d3.dtsi" +-#include "sama5d3_lcd.dtsi" +-#include "sama5d3_gmac.dtsi" +- +-/ { +- compatible = "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d33ek.dts b/scripts/dtc/include-prefixes/arm/sama5d33ek.dts +deleted file mode 100644 +index 7d4ae1682933..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d33ek.dts ++++ /dev/null +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * sama5d33ek.dts - Device Tree file for SAMA5D33-EK board +- * +- * Copyright (C) 2013 Atmel, +- * 2013 Ludovic Desroches +- */ +-/dts-v1/; +-#include "sama5d33.dtsi" +-#include "sama5d3xmb.dtsi" +-#include "sama5d3xmb_gmac.dtsi" +-#include "sama5d3xdm.dtsi" +- +-/ { +- model = "Atmel SAMA5D33-EK"; +- compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5"; +- +- ahb { +- apb { +- spi0: spi@f0004000 { +- status = "okay"; +- }; +- +- ssc0: ssc@f0008000 { +- status = "okay"; +- }; +- +- i2c0: i2c@f0014000 { +- status = "okay"; +- }; +- +- i2c1: i2c@f0018000 { +- status = "okay"; +- }; +- +- macb0: ethernet@f0028000 { +- status = "okay"; +- }; +- }; +- }; +- +- sound { +- status = "okay"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d34.dtsi b/scripts/dtc/include-prefixes/arm/sama5d34.dtsi +deleted file mode 100644 +index 132918c889a0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d34.dtsi ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * sama5d34.dtsi - Device Tree Include file for SAMA5D34 SoC +- * +- * Copyright (C) 2013 Boris BREZILLON +- */ +-#include "sama5d3.dtsi" +-#include "sama5d3_lcd.dtsi" +-#include "sama5d3_gmac.dtsi" +-#include "sama5d3_can.dtsi" +-#include "sama5d3_mci2.dtsi" +- +-/ { +- compatible = "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d34ek.dts b/scripts/dtc/include-prefixes/arm/sama5d34ek.dts +deleted file mode 100644 +index 2335bf906f69..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d34ek.dts ++++ /dev/null +@@ -1,62 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * sama5d34ek.dts - Device Tree file for SAMA5D34-EK board +- * +- * Copyright (C) 2013 Atmel, +- * 2013 Ludovic Desroches +- */ +-/dts-v1/; +-#include "sama5d34.dtsi" +-#include "sama5d3xmb.dtsi" +-#include "sama5d3xmb_gmac.dtsi" +-#include "sama5d3xdm.dtsi" +- +-/ { +- model = "Atmel SAMA5D34-EK"; +- compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5"; +- +- ahb { +- apb { +- spi0: spi@f0004000 { +- status = "okay"; +- }; +- +- ssc0: ssc@f0008000 { +- status = "okay"; +- }; +- +- can0: can@f000c000 { +- status = "okay"; +- }; +- +- i2c0: i2c@f0014000 { +- status = "okay"; +- }; +- +- i2c1: i2c@f0018000 { +- status = "okay"; +- +- 24c256@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- pagesize = <64>; +- }; +- }; +- +- macb0: ethernet@f0028000 { +- status = "okay"; +- }; +- }; +- }; +- +- leds { +- d3 { +- label = "d3"; +- gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- sound { +- status = "okay"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d35.dtsi b/scripts/dtc/include-prefixes/arm/sama5d35.dtsi +deleted file mode 100644 +index b2ccfa77c4be..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d35.dtsi ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * sama5d35.dtsi - Device Tree Include file for SAMA5D35 SoC +- * +- * Copyright (C) 2013 Boris BREZILLON +- */ +-#include "sama5d3.dtsi" +-#include "sama5d3_gmac.dtsi" +-#include "sama5d3_emac.dtsi" +-#include "sama5d3_can.dtsi" +-#include "sama5d3_mci2.dtsi" +-#include "sama5d3_uart.dtsi" +-#include "sama5d3_tcb1.dtsi" +- +-/ { +- compatible = "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d35ek.dts b/scripts/dtc/include-prefixes/arm/sama5d35ek.dts +deleted file mode 100644 +index 8edfcebb1df0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d35ek.dts ++++ /dev/null +@@ -1,56 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * sama5d35ek.dts - Device Tree file for SAMA5D35-EK board +- * +- * Copyright (C) 2013 Atmel, +- * 2013 Ludovic Desroches +- */ +-/dts-v1/; +-#include "sama5d35.dtsi" +-#include "sama5d3xmb.dtsi" +-#include "sama5d3xmb_emac.dtsi" +-#include "sama5d3xmb_gmac.dtsi" +- +-/ { +- model = "Atmel SAMA5D35-EK"; +- compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5"; +- +- ahb { +- apb { +- spi0: spi@f0004000 { +- status = "okay"; +- }; +- +- can0: can@f000c000 { +- status = "okay"; +- }; +- +- i2c1: i2c@f0018000 { +- status = "okay"; +- }; +- +- macb0: ethernet@f0028000 { +- status = "okay"; +- }; +- +- isi: isi@f0034000 { +- status = "okay"; +- }; +- +- macb1: ethernet@f802c000 { +- status = "okay"; +- }; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- pb_user1 { +- label = "pb_user1"; +- gpios = <&pioE 27 GPIO_ACTIVE_HIGH>; +- linux,code = <0x100>; +- wakeup-source; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d36.dtsi b/scripts/dtc/include-prefixes/arm/sama5d36.dtsi +deleted file mode 100644 +index 5d88f9967138..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d36.dtsi ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * sama5d36.dtsi - Device Tree Include file for SAMA5D36 SoC +- * +- * Copyright (C) 2013 Atmel, +- * 2013 Josh Wu +- */ +-#include "sama5d3.dtsi" +-#include "sama5d3_can.dtsi" +-#include "sama5d3_gmac.dtsi" +-#include "sama5d3_emac.dtsi" +-#include "sama5d3_lcd.dtsi" +-#include "sama5d3_mci2.dtsi" +-#include "sama5d3_tcb1.dtsi" +-#include "sama5d3_uart.dtsi" +- +-/ { +- compatible = "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d36ek.dts b/scripts/dtc/include-prefixes/arm/sama5d36ek.dts +deleted file mode 100644 +index 26950f9284c2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d36ek.dts ++++ /dev/null +@@ -1,54 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * sama5d36ek.dts - Device Tree file for SAMA5D36-EK board +- * +- * Copyright (C) 2013 Atmel, +- * 2013 Josh Wu +- */ +-/dts-v1/; +-#include "sama5d36.dtsi" +-#include "sama5d3xmb.dtsi" +-#include "sama5d3xdm.dtsi" +-#include "sama5d3xmb_emac.dtsi" +-#include "sama5d3xmb_gmac.dtsi" +- +-/ { +- model = "Atmel SAMA5D36-EK"; +- compatible = "atmel,sama5d36ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; +- +- ahb { +- apb { +- spi0: spi@f0004000 { +- status = "okay"; +- }; +- +- ssc0: ssc@f0008000 { +- status = "okay"; +- }; +- +- can0: can@f000c000 { +- status = "okay"; +- }; +- +- i2c0: i2c@f0014000 { +- status = "okay"; +- }; +- +- i2c1: i2c@f0018000 { +- status = "okay"; +- }; +- +- macb0: ethernet@f0028000 { +- status = "okay"; +- }; +- +- macb1: ethernet@f802c000 { +- status = "okay"; +- }; +- }; +- }; +- +- sound { +- status = "okay"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d36ek_cmp.dts b/scripts/dtc/include-prefixes/arm/sama5d36ek_cmp.dts +deleted file mode 100644 +index 66695b9a3e77..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d36ek_cmp.dts ++++ /dev/null +@@ -1,50 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * sama5d36ek_cmp.dts - Device Tree file for SAMA5D36-EK CMP board +- * +- * Copyright (C) 2016 Atmel, +- */ +-/dts-v1/; +-#include "sama5d36.dtsi" +-#include "sama5d3xmb_cmp.dtsi" +- +-/ { +- model = "Atmel SAMA5D36EK-CMP"; +- compatible = "atmel,sama5d36ek-cmp", "atmel,sama5d3xmb-cmp", "atmel,sama5d3xcm-cmp", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; +- +- ahb { +- apb { +- spi0: spi@f0004000 { +- status = "okay"; +- }; +- +- ssc0: ssc@f0008000 { +- status = "okay"; +- }; +- +- can0: can@f000c000 { +- status = "okay"; +- }; +- +- i2c0: i2c@f0014000 { +- status = "okay"; +- }; +- +- i2c1: i2c@f0018000 { +- status = "okay"; +- }; +- +- macb0: ethernet@f0028000 { +- status = "okay"; +- }; +- +- macb1: ethernet@f802c000 { +- status = "okay"; +- }; +- }; +- }; +- +- sound { +- status = "okay"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d3_can.dtsi b/scripts/dtc/include-prefixes/arm/sama5d3_can.dtsi +deleted file mode 100644 +index 9ac29bf3f933..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d3_can.dtsi ++++ /dev/null +@@ -1,57 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with +- * CAN support +- * +- * Copyright (C) 2013 Boris BREZILLON +- */ +- +-#include +-#include +- +-/ { +- ahb { +- apb { +- pinctrl@fffff200 { +- can0 { +- pinctrl_can0_rx_tx: can0_rx_tx { +- atmel,pins = +- ; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ +- }; +- }; +- +- can1 { +- pinctrl_can1_rx_tx: can1_rx_tx { +- atmel,pins = +- ; /* PB15 periph B TX, conflicts with GCOL */ +- }; +- }; +- +- }; +- +- can0: can@f000c000 { +- compatible = "atmel,at91sam9x5-can"; +- reg = <0xf000c000 0x300>; +- interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can0_rx_tx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; +- clock-names = "can_clk"; +- status = "disabled"; +- }; +- +- can1: can@f8010000 { +- compatible = "atmel,at91sam9x5-can"; +- reg = <0xf8010000 0x300>; +- interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1_rx_tx>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; +- clock-names = "can_clk"; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d3_emac.dtsi b/scripts/dtc/include-prefixes/arm/sama5d3_emac.dtsi +deleted file mode 100644 +index 45226108850d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d3_emac.dtsi ++++ /dev/null +@@ -1,48 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * sama5d3_emac.dtsi - Device Tree Include file for SAMA5D3 SoC with +- * Ethernet. +- * +- * Copyright (C) 2013 Boris BREZILLON +- */ +- +-#include +-#include +- +-/ { +- ahb { +- apb { +- pinctrl@fffff200 { +- macb1 { +- pinctrl_macb1_rmii: macb1_rmii-0 { +- atmel,pins = +- ; /* PC9 periph A EMDIO */ +- }; +- }; +- }; +- +- pmc: pmc@fffffc00 { +- }; +- +- macb1: ethernet@f802c000 { +- compatible = "atmel,sama5d3-macb", "cdns,at91sam9260-macb", "cdns,macb"; +- reg = <0xf802c000 0x100>; +- interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_macb1_rmii>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_PERIPHERAL 35>; +- clock-names = "hclk", "pclk"; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d3_gmac.dtsi b/scripts/dtc/include-prefixes/arm/sama5d3_gmac.dtsi +deleted file mode 100644 +index 884df7a54dbb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d3_gmac.dtsi ++++ /dev/null +@@ -1,78 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * sama5d3_gmac.dtsi - Device Tree Include file for SAMA5D3 SoC with +- * Gigabit Ethernet. +- * +- * Copyright (C) 2013 Boris BREZILLON +- */ +- +-#include +-#include +- +-/ { +- ahb { +- apb { +- pinctrl@fffff200 { +- macb0 { +- pinctrl_macb0_data_rgmii: macb0_data_rgmii { +- atmel,pins = +- ; /* PB7 periph A GRX3, conflicts with RK1 */ +- }; +- pinctrl_macb0_data_gmii: macb0_data_gmii { +- atmel,pins = +- ; /* PB26 periph B GRX7, conflicts with CTS1 */ +- }; +- pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { +- atmel,pins = +- ; /* PB18 periph A G125CK */ +- }; +- pinctrl_macb0_signal_gmii: macb0_signal_gmii { +- atmel,pins = +- ; /* PB27 periph B G125CKO */ +- }; +- +- }; +- }; +- +- macb0: ethernet@f0028000 { +- compatible = "atmel,sama5d3-gem"; +- reg = <0xf0028000 0x100>; +- interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_PERIPHERAL 34>; +- clock-names = "hclk", "pclk"; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d3_lcd.dtsi b/scripts/dtc/include-prefixes/arm/sama5d3_lcd.dtsi +deleted file mode 100644 +index 308d2fc276d6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d3_lcd.dtsi ++++ /dev/null +@@ -1,197 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with +- * LCD support +- * +- * Copyright (C) 2013 Boris BREZILLON +- */ +- +-#include +-#include +- +-/ { +- ahb { +- apb { +- hlcdc: hlcdc@f0030000 { +- compatible = "atmel,sama5d3-hlcdc"; +- reg = <0xf0030000 0x2000>; +- interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; +- clock-names = "periph_clk","sys_clk", "slow_clk"; +- status = "disabled"; +- +- hlcdc-display-controller { +- compatible = "atmel,hlcdc-display-controller"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- }; +- +- hlcdc_pwm: hlcdc-pwm { +- compatible = "atmel,hlcdc-pwm"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd_pwm>; +- #pwm-cells = <3>; +- }; +- }; +- +- pinctrl@fffff200 { +- lcd { +- pinctrl_lcd_base: lcd-base-0 { +- atmel,pins = +- ; /* LCDPCK */ +- }; +- +- pinctrl_lcd_pwm: lcd-pwm-0 { +- atmel,pins = ; /* LCDPWM */ +- }; +- +- pinctrl_lcd_rgb444: lcd-rgb-0 { +- atmel,pins = +- ; /* LCDD11 pin */ +- }; +- +- pinctrl_lcd_rgb565: lcd-rgb-1 { +- atmel,pins = +- ; /* LCDD15 pin */ +- }; +- +- pinctrl_lcd_rgb666: lcd-rgb-2 { +- atmel,pins = +- ; /* LCDD17 pin */ +- }; +- +- pinctrl_lcd_rgb666_alt: lcd-rgb-2-alt { +- atmel,pins = +- ; /* LCDD17 pin */ +- }; +- +- pinctrl_lcd_rgb888: lcd-rgb-3 { +- atmel,pins = +- ; /* LCDD23 pin */ +- }; +- +- pinctrl_lcd_rgb888_alt: lcd-rgb-3-alt { +- atmel,pins = +- ; /* LCDD23 pin */ +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d3_mci2.dtsi b/scripts/dtc/include-prefixes/arm/sama5d3_mci2.dtsi +deleted file mode 100644 +index 7141ee97ec3e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d3_mci2.dtsi ++++ /dev/null +@@ -1,49 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * sama5d3_mci2.dtsi - Device Tree Include file for SAMA5D3 SoC with +- * 3 MMC ports +- * +- * Copyright (C) 2013 Boris BREZILLON +- */ +- +-#include +-#include +-#include +- +-/ { +- ahb { +- apb { +- pinctrl@fffff200 { +- mmc2 { +- pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { +- atmel,pins = +- ; /* PC11 periph A MCI2_DA0 with pullup */ +- }; +- pinctrl_mmc2_dat1_3: mmc2_dat1_3 { +- atmel,pins = +- ; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ +- }; +- }; +- }; +- +- mmc2: mmc@f8004000 { +- compatible = "atmel,hsmci"; +- reg = <0xf8004000 0x600>; +- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>; +- dma-names = "rxtx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; +- clock-names = "mci_clk"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d3_tcb1.dtsi b/scripts/dtc/include-prefixes/arm/sama5d3_tcb1.dtsi +deleted file mode 100644 +index 2b18c5c2cc03..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d3_tcb1.dtsi ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * sama5d3_tcb1.dtsi - Device Tree Include file for SAMA5D3 SoC with +- * 2 TC blocks. +- * +- * Copyright (C) 2013 Boris BREZILLON +- */ +- +-#include +-#include +-#include +- +-/ { +- aliases { +- tcb1 = &tcb1; +- }; +- +- ahb { +- apb { +- tcb1: timer@f8014000 { +- compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xf8014000 0x100>; +- interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&clk32k>; +- clock-names = "t0_clk", "slow_clk"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d3_uart.dtsi b/scripts/dtc/include-prefixes/arm/sama5d3_uart.dtsi +deleted file mode 100644 +index a3eaba995cf4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d3_uart.dtsi ++++ /dev/null +@@ -1,62 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with +- * UART support +- * +- * Copyright (C) 2013 Boris BREZILLON +- */ +- +-#include +-#include +-#include +- +-/ { +- aliases { +- serial5 = &uart0; +- serial6 = &uart1; +- }; +- +- ahb { +- apb { +- pinctrl@fffff200 { +- uart0 { +- pinctrl_uart0: uart0-0 { +- atmel,pins = +- ; /* conflicts with ISI_PCK */ +- }; +- }; +- +- uart1 { +- pinctrl_uart1: uart1-0 { +- atmel,pins = +- ; /* conflicts with TWCK0, ISI_HSYNC */ +- }; +- }; +- }; +- +- uart0: serial@f0024000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf0024000 0x100>; +- interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- uart1: serial@f8028000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf8028000 0x100>; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d3xcm.dtsi b/scripts/dtc/include-prefixes/arm/sama5d3xcm.dtsi +deleted file mode 100644 +index 384335635792..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d3xcm.dtsi ++++ /dev/null +@@ -1,139 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module +- * +- * Copyright (C) 2013 Atmel, +- * 2013 Ludovic Desroches +- */ +- +-/ { +- compatible = "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; +- +- chosen { +- bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x20000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- ahb { +- apb { +- spi0: spi@f0004000 { +- cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; +- }; +- +- tcb0: timer@f0010000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>; +- }; +- +- timer@1 { +- compatible = "atmel,tcb-timer"; +- reg = <1>; +- }; +- }; +- }; +- +- ebi@10000000 { +- pinctrl-0 = <&pinctrl_ebi_addr &pinctrl_ebi_cs0>; +- pinctr-name = "default"; +- status = "okay"; +- +- nor: flash@0,0 { +- compatible = "cfi-flash"; +- linux,mtd-name = "physmap-flash.0"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x0 0x0 0x1000000>; +- bank-width = <2>; +- atmel,smc-read-mode = "nrd"; +- atmel,smc-write-mode = "nwe"; +- atmel,smc-bus-width = <16>; +- atmel,smc-ncs-rd-setup-ns = <0>; +- atmel,smc-ncs-wr-setup-ns = <0>; +- atmel,smc-nwe-setup-ns = <8>; +- atmel,smc-nrd-setup-ns = <16>; +- atmel,smc-ncs-rd-pulse-ns = <84>; +- atmel,smc-ncs-wr-pulse-ns = <84>; +- atmel,smc-nrd-pulse-ns = <76>; +- atmel,smc-nwe-pulse-ns = <76>; +- atmel,smc-nrd-cycle-ns = <107>; +- atmel,smc-nwe-cycle-ns = <84>; +- atmel,smc-tdf-ns = <16>; +- }; +- +- nand_controller: nand-controller { +- status = "okay"; +- +- nand@3 { +- reg = <0x3 0x0 0x2>; +- atmel,rb = <0>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x40000>; +- }; +- +- bootloader@40000 { +- label = "bootloader"; +- reg = <0x40000 0x80000>; +- }; +- +- bootloaderenv@c0000 { +- label = "bootloader env"; +- reg = <0xc0000 0xc0000>; +- }; +- +- dtb@180000 { +- label = "device tree"; +- reg = <0x180000 0x80000>; +- }; +- +- kernel@200000 { +- label = "kernel"; +- reg = <0x200000 0x600000>; +- }; +- +- rootfs@800000 { +- label = "rootfs"; +- reg = <0x800000 0x0f800000>; +- }; +- }; +- }; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- d2 { +- label = "d2"; +- gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */ +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d3xcm_cmp.dtsi b/scripts/dtc/include-prefixes/arm/sama5d3xcm_cmp.dtsi +deleted file mode 100644 +index 5579c955f141..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d3xcm_cmp.dtsi ++++ /dev/null +@@ -1,193 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * sama5d3xcm_cmp.dtsi - Device Tree Include file for SAMA5D36 CMP CPU Module +- * +- * Copyright (C) 2016 Atmel, +- */ +- +-/ { +- compatible = "atmel,sama5d3xcm-cmp", "atmel,sama5d3", "atmel,sama5"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x20000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- ahb { +- apb { +- spi0: spi@f0004000 { +- cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; +- }; +- +- tcb0: timer@f0010000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>; +- }; +- +- timer@1 { +- compatible = "atmel,tcb-timer"; +- reg = <1>; +- }; +- }; +- +- macb0: ethernet@f0028000 { +- phy-mode = "rgmii"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethernet-phy@1 { +- reg = <0x1>; +- interrupt-parent = <&pioB>; +- interrupts = <25 IRQ_TYPE_EDGE_FALLING>; +- txen-skew-ps = <800>; +- txc-skew-ps = <3000>; +- rxdv-skew-ps = <400>; +- rxc-skew-ps = <3000>; +- rxd0-skew-ps = <400>; +- rxd1-skew-ps = <400>; +- rxd2-skew-ps = <400>; +- rxd3-skew-ps = <400>; +- }; +- +- ethernet-phy@7 { +- reg = <0x7>; +- interrupt-parent = <&pioB>; +- interrupts = <25 IRQ_TYPE_EDGE_FALLING>; +- txen-skew-ps = <800>; +- txc-skew-ps = <3000>; +- rxdv-skew-ps = <400>; +- rxc-skew-ps = <3000>; +- rxd0-skew-ps = <400>; +- rxd1-skew-ps = <400>; +- rxd2-skew-ps = <400>; +- rxd3-skew-ps = <400>; +- }; +- }; +- +- i2c1: i2c@f0018000 { +- pmic: act8865@5b { +- compatible = "active-semi,act8865"; +- reg = <0x5b>; +- status = "disabled"; +- +- regulators { +- vcc_1v8_reg: DCDC_REG1 { +- regulator-name = "VCC_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcc_1v2_reg: DCDC_REG2 { +- regulator-name = "VCC_1V2"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- }; +- +- vcc_3v3_reg: DCDC_REG3 { +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vddana_reg: LDO_REG1 { +- regulator-name = "VDDANA"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vddfuse_reg: LDO_REG2 { +- regulator-name = "FUSE_2V5"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- }; +- }; +- }; +- }; +- }; +- +- ebi: ebi@10000000 { +- pinctrl-0 = <&pinctrl_ebi_nand_addr>; +- pinctrl-names = "default"; +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- +- nand@3 { +- reg = <0x3 0x0 0x2>; +- atmel,rb = <0>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x40000>; +- }; +- +- bootloader@40000 { +- label = "bootloader"; +- reg = <0x40000 0x80000>; +- }; +- +- bootloaderenv@c0000 { +- label = "bootloader env"; +- reg = <0xc0000 0xc0000>; +- }; +- +- dtb@180000 { +- label = "device tree"; +- reg = <0x180000 0x80000>; +- }; +- +- kernel@200000 { +- label = "kernel"; +- reg = <0x200000 0x600000>; +- }; +- +- rootfs@800000 { +- label = "rootfs"; +- reg = <0x800000 0x0f800000>; +- }; +- }; +- }; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- d2 { +- label = "d2"; +- gpios = <&pioE 25 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d3xdm.dtsi b/scripts/dtc/include-prefixes/arm/sama5d3xdm.dtsi +deleted file mode 100644 +index 3c1c4d62fbf9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d3xdm.dtsi ++++ /dev/null +@@ -1,40 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * sama5d3dm.dtsi - Device Tree file for SAMA5 display module +- * +- * Copyright (C) 2013 Atmel, +- * 2013 Ludovic Desroches +- */ +- +-/ { +- ahb { +- apb { +- i2c1: i2c@f0018000 { +- qt1070: keyboard@1b { +- compatible = "qt1070"; +- reg = <0x1b>; +- interrupt-parent = <&pioE>; +- interrupts = <31 0x0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_qt1070_irq>; +- wakeup-source; +- }; +- }; +- +- adc0: adc@f8018000 { +- atmel,adc-ts-wires = <4>; +- atmel,adc-ts-pressure-threshold = <10000>; +- status = "okay"; +- }; +- +- pinctrl@fffff200 { +- board { +- pinctrl_qt1070_irq: qt1070_irq { +- atmel,pins = +- ; /* PE31 GPIO with pull up deglith */ +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d3xmb.dtsi b/scripts/dtc/include-prefixes/arm/sama5d3xmb.dtsi +deleted file mode 100644 +index a499de8a7a64..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d3xmb.dtsi ++++ /dev/null +@@ -1,208 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board +- * +- * Copyright (C) 2013 Atmel, +- * 2013 Ludovic Desroches +- */ +-#include "sama5d3xcm.dtsi" +- +-/ { +- compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; +- +- ahb { +- apb { +- mmc0: mmc@f0000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; +- status = "okay"; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- spi0: spi@f0004000 { +- dmas = <0>, <0>; /* Do not use DMA for spi0 */ +- +- m25p80@0 { +- compatible = "atmel,at25df321a"; +- spi-max-frequency = <50000000>; +- reg = <0>; +- }; +- }; +- +- ssc0: ssc@f0008000 { +- atmel,clk-from-rk-pin; +- }; +- +- /* +- * i2c0 conflicts with ISI: +- * disable it to allow the use of ISI +- * can not enable audio when i2c0 disabled +- */ +- i2c0: i2c@f0014000 { +- wm8904: wm8904@1a { +- compatible = "wlf,wm8904"; +- reg = <0x1a>; +- clocks = <&pmc PMC_TYPE_SYSTEM 8>; +- clock-names = "mclk"; +- }; +- }; +- +- i2c1: i2c@f0018000 { +- ov2640: camera@30 { +- compatible = "ovti,ov2640"; +- reg = <0x30>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; +- resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; +- pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; +- /* use pck1 for the master clock of ov2640 */ +- clocks = <&pmc PMC_TYPE_SYSTEM 9>; +- clock-names = "xvclk"; +- assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; +- assigned-clock-rates = <25000000>; +- +- port { +- ov2640_0: endpoint { +- remote-endpoint = <&isi_0>; +- bus-width = <8>; +- }; +- }; +- }; +- }; +- +- usart1: serial@f0020000 { +- dmas = <0>, <0>; /* Do not use DMA for usart1 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; +- status = "okay"; +- }; +- +- isi: isi@f0034000 { +- port { +- isi_0: endpoint { +- remote-endpoint = <&ov2640_0>; +- bus-width = <8>; +- vsync-active = <1>; +- hsync-active = <1>; +- }; +- }; +- }; +- +- mmc1: mmc@f8000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; +- status = "okay"; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- adc0: adc@f8018000 { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &pinctrl_adc0_adtrg +- &pinctrl_adc0_ad0 +- &pinctrl_adc0_ad1 +- &pinctrl_adc0_ad2 +- &pinctrl_adc0_ad3 +- &pinctrl_adc0_ad4 +- >; +- status = "okay"; +- }; +- +- pinctrl@fffff200 { +- board { +- pinctrl_mmc0_cd: mmc0_cd { +- atmel,pins = +- ; /* PD17 GPIO with pullup deglitch */ +- }; +- +- pinctrl_mmc1_cd: mmc1_cd { +- atmel,pins = +- ; /* PD18 GPIO with pullup deglitch */ +- }; +- +- pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { +- atmel,pins = +- ; /* PD30 periph B */ +- }; +- +- pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { +- atmel,pins = +- ; /* PD31 periph B ISI_MCK */ +- }; +- +- pinctrl_sensor_reset: sensor_reset-0 { +- atmel,pins = +- ; /* PE24 gpio */ +- }; +- +- pinctrl_sensor_power: sensor_power-0 { +- atmel,pins = +- ; /* PE29 gpio */ +- }; +- +- pinctrl_usba_vbus: usba_vbus { +- atmel,pins = +- ; /* PD29 GPIO with deglitch */ +- }; +- }; +- }; +- +- dbgu: serial@ffffee00 { +- dmas = <0>, <0>; /* Do not use DMA for dbgu */ +- status = "okay"; +- }; +- +- watchdog@fffffe40 { +- status = "okay"; +- }; +- }; +- +- usb0: gadget@500000 { +- atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usba_vbus>; +- status = "okay"; +- }; +- +- usb1: ohci@600000 { +- num-ports = <3>; +- atmel,vbus-gpio = <&pioD 25 GPIO_ACTIVE_HIGH +- &pioD 26 GPIO_ACTIVE_LOW +- &pioD 27 GPIO_ACTIVE_LOW +- >; +- status = "okay"; +- }; +- +- usb2: ehci@700000 { +- status = "okay"; +- }; +- }; +- +- sound { +- compatible = "atmel,asoc-wm8904"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; +- +- atmel,model = "wm8904 @ SAMA5D3EK"; +- atmel,audio-routing = +- "Headphone Jack", "HPOUTL", +- "Headphone Jack", "HPOUTR", +- "IN2L", "Line In Jack", +- "IN2R", "Line In Jack", +- "Mic", "MICBIAS", +- "IN1L", "Mic"; +- +- atmel,ssc-controller = <&ssc0>; +- atmel,audio-codec = <&wm8904>; +- +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d3xmb_cmp.dtsi b/scripts/dtc/include-prefixes/arm/sama5d3xmb_cmp.dtsi +deleted file mode 100644 +index fa9e5e2a745d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d3xmb_cmp.dtsi ++++ /dev/null +@@ -1,264 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * sama5d3xmb_cmp.dts - Device Tree file for SAMA5D3x CMP mother board +- * +- * Copyright (C) 2016 Atmel, +- */ +-#include "sama5d3xcm_cmp.dtsi" +- +-/ { +- compatible = "atmel,sama5d3xmb-cmp", "atmel,sama5d3xcm-cmp", "atmel,sama5d3", "atmel,sama5"; +- +- ahb { +- apb { +- mmc0: mmc@f0000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; +- status = "okay"; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- spi0: spi@f0004000 { +- dmas = <0>, <0>; /* Do not use DMA for spi0 */ +- +- m25p80@0 { +- compatible = "atmel,at25df321a"; +- spi-max-frequency = <50000000>; +- reg = <0>; +- }; +- }; +- +- ssc0: ssc@f0008000 { +- atmel,clk-from-rk-pin; +- }; +- +- /* +- * i2c0 conflicts with ISI: +- * disable it to allow the use of ISI +- * can not enable audio when i2c0 disabled +- */ +- i2c0: i2c@f0014000 { +- wm8904: wm8904@1a { +- compatible = "wlf,wm8904"; +- reg = <0x1a>; +- clocks = <&pmc PMC_TYPE_SYSTEM 8>; +- clock-names = "mclk"; +- }; +- }; +- +- i2c1: i2c@f0018000 { +- ov2640: camera@30 { +- compatible = "ovti,ov2640"; +- reg = <0x30>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; +- resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; +- pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; +- /* use pck1 for the master clock of ov2640 */ +- clocks = <&pmc PMC_TYPE_SYSTEM 9>; +- clock-names = "xvclk"; +- assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; +- assigned-clock-rates = <25000000>; +- +- port { +- ov2640_0: endpoint { +- remote-endpoint = <&isi_0>; +- bus-width = <8>; +- }; +- }; +- }; +- }; +- +- usart1: serial@f0020000 { +- dmas = <0>, <0>; /* Do not use DMA for usart1 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; +- status = "okay"; +- }; +- +- isi: isi@f0034000 { +- port { +- isi_0: endpoint { +- remote-endpoint = <&ov2640_0>; +- bus-width = <8>; +- vsync-active = <1>; +- hsync-active = <1>; +- }; +- }; +- }; +- +- mmc1: mmc@f8000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; +- status = "okay"; +- slot@0 { +- reg = <0>; +- bus-width = <4>; +- cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- adc0: adc@f8018000 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = < +- &pinctrl_adc0_adtrg +- &pinctrl_adc0_ad0 +- &pinctrl_adc0_ad1 +- &pinctrl_adc0_ad2 +- &pinctrl_adc0_ad3 +- &pinctrl_adc0_ad4 +- >; +- pinctrl-1 = < +- &pinctrl_adc0_adtrg_sleep +- &pinctrl_adc0_ad0_sleep +- &pinctrl_adc0_ad1_sleep +- &pinctrl_adc0_ad2_sleep +- &pinctrl_adc0_ad3_sleep +- &pinctrl_adc0_ad4_sleep +- >; +- status = "okay"; +- }; +- +- macb1: ethernet@f802c000 { +- phy-mode = "rmii"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- phy0: ethernet-phy@1 { +- /*interrupt-parent = <&pioE>;*/ +- /*interrupts = <30 IRQ_TYPE_EDGE_FALLING>;*/ +- reg = <1>; +- }; +- }; +- +- pinctrl@fffff200 { +- adc0 { +- pinctrl_adc0_adtrg_sleep: adc0_adtrg_1 { +- atmel,pins = +- ; +- }; +- pinctrl_adc0_ad0_sleep: adc0_ad0_1 { +- atmel,pins = +- ; +- }; +- pinctrl_adc0_ad1_sleep: adc0_ad1_1 { +- atmel,pins = +- ; +- }; +- pinctrl_adc0_ad2_sleep: adc0_ad2_1 { +- atmel,pins = +- ; +- }; +- pinctrl_adc0_ad3_sleep: adc0_ad3_1 { +- atmel,pins = +- ; +- }; +- pinctrl_adc0_ad4_sleep: adc0_ad4_1 { +- atmel,pins = +- ; +- }; +- }; +- +- board { +- pinctrl_gpio_keys: gpio_keys { +- atmel,pins = +- ; +- }; +- +- pinctrl_mmc0_cd: mmc0_cd { +- atmel,pins = +- ; +- }; +- +- pinctrl_mmc1_cd: mmc1_cd { +- atmel,pins = +- ; +- }; +- +- pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { +- atmel,pins = +- ; +- }; +- +- pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_sensor_reset: sensor_reset-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_sensor_power: sensor_power-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_usba_vbus: usba_vbus { +- atmel,pins = +- ; +- }; +- }; +- }; +- +- dbgu: serial@ffffee00 { +- dmas = <0>, <0>; /* Do not use DMA for dbgu */ +- status = "okay"; +- }; +- +- watchdog@fffffe40 { +- status = "okay"; +- }; +- }; +- +- usb0: gadget@500000 { +- atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usba_vbus>; +- status = "okay"; +- }; +- }; +- +- sound { +- compatible = "atmel,asoc-wm8904"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; +- +- atmel,model = "wm8904 @ SAMA5D3EK"; +- atmel,audio-routing = +- "Headphone Jack", "HPOUTL", +- "Headphone Jack", "HPOUTR", +- "IN2L", "Line In Jack", +- "IN2R", "Line In Jack", +- "Mic", "MICBIAS", +- "IN1L", "Mic"; +- +- atmel,ssc-controller = <&ssc0>; +- atmel,audio-codec = <&wm8904>; +- +- status = "disabled"; +- }; +- +- /* Conflict with LCD pins */ +- gpio_keys { +- compatible = "gpio-keys"; +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- pb_user1 { +- label = "pb_user1"; +- gpios = <&pioE 27 GPIO_ACTIVE_HIGH>; +- linux,code = <0x100>; +- wakeup-source; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d3xmb_emac.dtsi b/scripts/dtc/include-prefixes/arm/sama5d3xmb_emac.dtsi +deleted file mode 100644 +index a5dd41cd9522..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d3xmb_emac.dtsi ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * sama5d3xmb_emac.dts - Device Tree Include file for SAMA5D3x mother board +- * Ethernet +- * +- * Copyright (C) 2016 Atmel, +- */ +- +-/ { +- ahb { +- apb { +- macb1: ethernet@f802c000 { +- phy-mode = "rmii"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- phy0: ethernet-phy@1 { +- interrupt-parent = <&pioE>; +- interrupts = <30 IRQ_TYPE_EDGE_FALLING>; +- reg = <1>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d3xmb_gmac.dtsi b/scripts/dtc/include-prefixes/arm/sama5d3xmb_gmac.dtsi +deleted file mode 100644 +index d750da38ff3c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d3xmb_gmac.dtsi ++++ /dev/null +@@ -1,47 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * sama5d3xmb_gmac.dtsi - Device Tree Include file for SAMA5D3x motherboard +- * Gigabit Ethernet +- * +- * Copyright (C) 2016 Atmel, +- */ +- +-/ { +- ahb { +- apb { +- macb0: ethernet@f0028000 { +- phy-mode = "rgmii"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethernet-phy@1 { +- reg = <0x1>; +- interrupt-parent = <&pioB>; +- interrupts = <25 IRQ_TYPE_EDGE_FALLING>; +- txen-skew-ps = <800>; +- txc-skew-ps = <3000>; +- rxdv-skew-ps = <400>; +- rxc-skew-ps = <3000>; +- rxd0-skew-ps = <400>; +- rxd1-skew-ps = <400>; +- rxd2-skew-ps = <400>; +- rxd3-skew-ps = <400>; +- }; +- +- ethernet-phy@7 { +- reg = <0x7>; +- interrupt-parent = <&pioB>; +- interrupts = <25 IRQ_TYPE_EDGE_FALLING>; +- txen-skew-ps = <800>; +- txc-skew-ps = <3000>; +- rxdv-skew-ps = <400>; +- rxc-skew-ps = <3000>; +- rxd0-skew-ps = <400>; +- rxd1-skew-ps = <400>; +- rxd2-skew-ps = <400>; +- rxd3-skew-ps = <400>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama5d4.dtsi b/scripts/dtc/include-prefixes/arm/sama5d4.dtsi +deleted file mode 100644 +index f6e3e6f57252..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama5d4.dtsi ++++ /dev/null +@@ -1,1447 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC +- * +- * Copyright (C) 2014 Atmel, +- * 2014 Nicolas Ferre +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "Atmel SAMA5D4 family SoC"; +- compatible = "atmel,sama5d4"; +- interrupt-parent = <&aic>; +- +- aliases { +- serial0 = &usart3; +- serial1 = &usart4; +- serial2 = &usart2; +- serial3 = &usart0; +- serial4 = &usart1; +- serial5 = &uart0; +- serial6 = &uart1; +- gpio0 = &pioA; +- gpio1 = &pioB; +- gpio2 = &pioC; +- gpio3 = &pioD; +- gpio4 = &pioE; +- pwm0 = &pwm0; +- ssc0 = &ssc0; +- ssc1 = &ssc1; +- tcb0 = &tcb0; +- tcb1 = &tcb1; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- }; +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a5"; +- reg = <0>; +- next-level-cache = <&L2>; +- }; +- }; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x20000000 0x20000000>; +- }; +- +- clocks { +- slow_xtal: slow_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- main_xtal: main_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- adc_op_clk: adc_op_clk{ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <1000000>; +- }; +- }; +- +- ns_sram: sram@210000 { +- compatible = "mmio-sram"; +- reg = <0x00210000 0x10000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00210000 0x10000>; +- }; +- +- ahb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- nfc_sram: sram@100000 { +- compatible = "mmio-sram"; +- no-memory-wc; +- reg = <0x100000 0x2400>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x100000 0x2400>; +- }; +- +- vdec0: vdec@300000 { +- compatible = "microchip,sama5d4-vdec"; +- reg = <0x00300000 0x100000>; +- interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; +- }; +- +- usb0: gadget@400000 { +- compatible = "atmel,sama5d3-udc"; +- reg = <0x00400000 0x100000 +- 0xfc02c000 0x4000>; +- interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>; +- clock-names = "pclk", "hclk"; +- status = "disabled"; +- }; +- +- usb1: ohci@500000 { +- compatible = "atmel,at91rm9200-ohci", "usb-ohci"; +- reg = <0x00500000 0x100000>; +- interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 6>; +- clock-names = "ohci_clk", "hclk", "uhpck"; +- status = "disabled"; +- }; +- +- usb2: ehci@600000 { +- compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; +- reg = <0x00600000 0x100000>; +- interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; +- clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 46>; +- clock-names = "usb_clk", "ehci_clk"; +- status = "disabled"; +- }; +- +- L2: cache-controller@a00000 { +- compatible = "arm,pl310-cache"; +- reg = <0x00a00000 0x1000>; +- interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>; +- cache-unified; +- cache-level = <2>; +- }; +- +- ebi: ebi@10000000 { +- compatible = "atmel,sama5d3-ebi"; +- #address-cells = <2>; +- #size-cells = <1>; +- atmel,smc = <&hsmc>; +- reg = <0x10000000 0x10000000 +- 0x60000000 0x28000000>; +- ranges = <0x0 0x0 0x10000000 0x10000000 +- 0x1 0x0 0x60000000 0x10000000 +- 0x2 0x0 0x70000000 0x10000000 +- 0x3 0x0 0x80000000 0x8000000>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; +- status = "disabled"; +- +- nand_controller: nand-controller { +- compatible = "atmel,sama5d3-nand-controller"; +- atmel,nfc-sram = <&nfc_sram>; +- atmel,nfc-io = <&nfc_io>; +- ecc-engine = <&pmecc>; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- }; +- }; +- +- nfc_io: nfc-io@90000000 { +- compatible = "atmel,sama5d3-nfc-io", "syscon"; +- reg = <0x90000000 0x8000000>; +- }; +- +- apb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- hlcdc: hlcdc@f0000000 { +- compatible = "atmel,sama5d4-hlcdc"; +- reg = <0xf0000000 0x4000>; +- interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; +- clock-names = "periph_clk","sys_clk", "slow_clk"; +- status = "disabled"; +- +- hlcdc-display-controller { +- compatible = "atmel,hlcdc-display-controller"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- }; +- +- hlcdc_pwm: hlcdc-pwm { +- compatible = "atmel,hlcdc-pwm"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcd_pwm>; +- #pwm-cells = <3>; +- }; +- }; +- +- dma1: dma-controller@f0004000 { +- compatible = "atmel,sama5d4-dma"; +- reg = <0xf0004000 0x200>; +- interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>; +- #dma-cells = <1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 50>; +- clock-names = "dma_clk"; +- }; +- +- isi: isi@f0008000 { +- compatible = "atmel,at91sam9g45-isi"; +- reg = <0xf0008000 0x4000>; +- interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_isi_data_0_7>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; +- clock-names = "isi_clk"; +- status = "disabled"; +- port { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- ramc0: ramc@f0010000 { +- compatible = "atmel,sama5d3-ddramc"; +- reg = <0xf0010000 0x200>; +- clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 16>; +- clock-names = "ddrck", "mpddr"; +- }; +- +- dma0: dma-controller@f0014000 { +- compatible = "atmel,sama5d4-dma"; +- reg = <0xf0014000 0x200>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>; +- #dma-cells = <1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; +- clock-names = "dma_clk"; +- }; +- +- pmc: pmc@f0018000 { +- compatible = "atmel,sama5d4-pmc", "syscon"; +- reg = <0xf0018000 0x120>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- #clock-cells = <2>; +- clocks = <&clk32k>, <&main_xtal>; +- clock-names = "slow_clk", "main_xtal"; +- }; +- +- mmc0: mmc@f8000000 { +- compatible = "atmel,hsmci"; +- reg = <0xf8000000 0x600>; +- interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(0))>; +- dma-names = "rxtx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; +- clock-names = "mci_clk"; +- }; +- +- uart0: serial@f8004000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf8004000 0x100>; +- interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(22))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(23))>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- ssc0: ssc@f8008000 { +- compatible = "atmel,at91sam9g45-ssc"; +- reg = <0xf8008000 0x4000>; +- interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; +- dmas = <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(26))>, +- <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(27))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; +- clock-names = "pclk"; +- status = "disabled"; +- }; +- +- pwm0: pwm@f800c000 { +- compatible = "atmel,sama5d3-pwm"; +- reg = <0xf800c000 0x300>; +- interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; +- #pwm-cells = <3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; +- status = "disabled"; +- }; +- +- spi0: spi@f8010000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xf8010000 0x100>; +- interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>; +- dmas = <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(10))>, +- <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(11))>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; +- clock-names = "spi_clk"; +- status = "disabled"; +- }; +- +- i2c0: i2c@f8014000 { +- compatible = "atmel,sama5d4-i2c"; +- reg = <0xf8014000 0x4000>; +- interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>; +- dmas = <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(2))>, +- <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(3))>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c0>; +- pinctrl-1 = <&pinctrl_i2c0_gpio>; +- sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; +- status = "disabled"; +- }; +- +- i2c1: i2c@f8018000 { +- compatible = "atmel,sama5d4-i2c"; +- reg = <0xf8018000 0x4000>; +- interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(4))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(5))>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c1>; +- pinctrl-1 = <&pinctrl_i2c1_gpio>; +- sda-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&pioE 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; +- status = "disabled"; +- }; +- +- tcb0: timer@f801c000 { +- compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xf801c000 0x100>; +- interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 40>, <&clk32k>; +- clock-names = "t0_clk", "slow_clk"; +- }; +- +- macb0: ethernet@f8020000 { +- compatible = "atmel,sama5d4-gem"; +- reg = <0xf8020000 0x100>; +- interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_macb0_rmii>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_PERIPHERAL 54>; +- clock-names = "hclk", "pclk"; +- status = "disabled"; +- }; +- +- i2c2: i2c@f8024000 { +- compatible = "atmel,sama5d4-i2c"; +- reg = <0xf8024000 0x4000>; +- interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>; +- dmas = <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(6))>, +- <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(7))>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c2>; +- pinctrl-1 = <&pinctrl_i2c2_gpio>; +- sda-gpios = <&pioB 29 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&pioB 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; +- status = "disabled"; +- }; +- +- sfr: sfr@f8028000 { +- compatible = "atmel,sama5d4-sfr", "syscon"; +- reg = <0xf8028000 0x60>; +- }; +- +- usart0: serial@f802c000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf802c000 0x100>; +- interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(36))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(37))>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart1: serial@f8030000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xf8030000 0x100>; +- interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(38))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(39))>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- mmc1: mmc@fc000000 { +- compatible = "atmel,hsmci"; +- reg = <0xfc000000 0x600>; +- interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(1))>; +- dma-names = "rxtx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; +- clock-names = "mci_clk"; +- }; +- +- uart1: serial@fc004000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfc004000 0x100>; +- interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(24))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(25))>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart2: serial@fc008000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfc008000 0x100>; +- interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; +- dmas = <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(16))>, +- <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(17))>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart3: serial@fc00c000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfc00c000 0x100>; +- interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>; +- dmas = <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(18))>, +- <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(19))>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- usart4: serial@fc010000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfc010000 0x100>; +- interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>; +- dmas = <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(20))>, +- <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(21))>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usart4>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 31>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- ssc1: ssc@fc014000 { +- compatible = "atmel,at91sam9g45-ssc"; +- reg = <0xfc014000 0x4000>; +- interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; +- dmas = <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(28))>, +- <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(29))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; +- clock-names = "pclk"; +- status = "disabled"; +- }; +- +- spi1: spi@fc018000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xfc018000 0x100>; +- interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>; +- dmas = <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(12))>, +- <&dma1 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(13))>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; +- clock-names = "spi_clk"; +- status = "disabled"; +- }; +- +- spi2: spi@fc01c000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "atmel,at91rm9200-spi"; +- reg = <0xfc01c000 0x100>; +- interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>; +- dmas = <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(14))>, +- <&dma0 +- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(15))>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; +- clock-names = "spi_clk"; +- status = "disabled"; +- }; +- +- tcb1: timer@fc020000 { +- compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xfc020000 0x100>; +- interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&clk32k>; +- clock-names = "t0_clk", "slow_clk"; +- }; +- +- tcb2: timer@fc024000 { +- compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xfc024000 0x100>; +- interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&clk32k>; +- clock-names = "t0_clk", "slow_clk"; +- }; +- +- macb1: ethernet@fc028000 { +- compatible = "atmel,sama5d4-gem"; +- reg = <0xfc028000 0x100>; +- interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_macb1_rmii>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_PERIPHERAL 55>; +- clock-names = "hclk", "pclk"; +- status = "disabled"; +- }; +- +- trng@fc030000 { +- compatible = "atmel,at91sam9g45-trng"; +- reg = <0xfc030000 0x100>; +- interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; +- }; +- +- adc0: adc@fc034000 { +- compatible = "atmel,at91sam9x5-adc"; +- reg = <0xfc034000 0x100>; +- interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 44>, +- <&adc_op_clk>; +- clock-names = "adc_clk", "adc_op_clk"; +- atmel,adc-channels-used = <0x01f>; +- atmel,adc-startup-time = <40>; +- atmel,adc-use-external-triggers; +- atmel,adc-vref = <3000>; +- atmel,adc-sample-hold-time = <11>; +- atmel,adc-ts-pressure-threshold = <10000>; +- status = "disabled"; +- }; +- +- aes@fc044000 { +- compatible = "atmel,at91sam9g46-aes"; +- reg = <0xfc044000 0x100>; +- interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(41))>, +- <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(40))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; +- clock-names = "aes_clk"; +- status = "okay"; +- }; +- +- tdes@fc04c000 { +- compatible = "atmel,at91sam9g46-tdes"; +- reg = <0xfc04c000 0x100>; +- interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(42))>, +- <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(43))>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; +- clock-names = "tdes_clk"; +- status = "okay"; +- }; +- +- sha@fc050000 { +- compatible = "atmel,at91sam9g46-sha"; +- reg = <0xfc050000 0x100>; +- interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>; +- dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) +- | AT91_XDMAC_DT_PERID(44))>; +- dma-names = "tx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; +- clock-names = "sha_clk"; +- status = "okay"; +- }; +- +- hsmc: smc@fc05c000 { +- compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; +- reg = <0xfc05c000 0x1000>; +- interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- pmecc: ecc-engine@ffffc070 { +- compatible = "atmel,sama5d4-pmecc"; +- reg = <0xfc05c070 0x490>, +- <0xfc05c500 0x100>; +- }; +- }; +- +- reset_controller: rstc@fc068600 { +- compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; +- reg = <0xfc068600 0x10>; +- clocks = <&clk32k>; +- }; +- +- shutdown_controller: shdwc@fc068610 { +- compatible = "atmel,at91sam9x5-shdwc"; +- reg = <0xfc068610 0x10>; +- clocks = <&clk32k>; +- }; +- +- pit: timer@fc068630 { +- compatible = "atmel,at91sam9260-pit"; +- reg = <0xfc068630 0x10>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; +- clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; +- }; +- +- watchdog: watchdog@fc068640 { +- compatible = "atmel,sama5d4-wdt"; +- reg = <0xfc068640 0x10>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&clk32k>; +- status = "disabled"; +- }; +- +- clk32k: sckc@fc068650 { +- compatible = "atmel,sama5d4-sckc"; +- reg = <0xfc068650 0x4>; +- #clock-cells = <0>; +- clocks = <&slow_xtal>; +- }; +- +- rtc@fc0686b0 { +- compatible = "atmel,sama5d4-rtc"; +- reg = <0xfc0686b0 0x30>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; +- clocks = <&clk32k>; +- }; +- +- dbgu: serial@fc069000 { +- compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; +- reg = <0xfc069000 0x200>; +- interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dbgu>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; +- clock-names = "usart"; +- status = "disabled"; +- }; +- +- +- pinctrl: pinctrl@fc06a000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; +- ranges = <0xfc068000 0xfc068000 0x100 +- 0xfc06a000 0xfc06a000 0x4000>; +- /* WARNING: revisit as pin spec has changed */ +- atmel,mux-mask = < +- /* A B C */ +- 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */ +- 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */ +- 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */ +- 0xb003ff00 0x8002a800 0x00000000 /* pioD */ +- 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ +- >; +- +- pioA: gpio@fc06a000 { +- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfc06a000 0x100>; +- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; +- }; +- +- pioB: gpio@fc06b000 { +- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfc06b000 0x100>; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; +- }; +- +- pioC: gpio@fc06c000 { +- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfc06c000 0x100>; +- interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; +- }; +- +- pioD: gpio@fc068000 { +- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfc068000 0x100>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; +- }; +- +- pioE: gpio@fc06d000 { +- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; +- reg = <0xfc06d000 0x100>; +- interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; +- }; +- +- /* pinctrl pin settings */ +- adc0 { +- pinctrl_adc0_adtrg: adc0_adtrg { +- atmel,pins = +- ; /* conflicts with USBA_VBUS */ +- }; +- pinctrl_adc0_ad0: adc0_ad0 { +- atmel,pins = +- ; +- }; +- pinctrl_adc0_ad1: adc0_ad1 { +- atmel,pins = +- ; +- }; +- pinctrl_adc0_ad2: adc0_ad2 { +- atmel,pins = +- ; +- }; +- pinctrl_adc0_ad3: adc0_ad3 { +- atmel,pins = +- ; +- }; +- pinctrl_adc0_ad4: adc0_ad4 { +- atmel,pins = +- ; +- }; +- }; +- +- dbgu { +- pinctrl_dbgu: dbgu-0 { +- atmel,pins = +- ; /* conflicts with D15 and TDO */ +- }; +- }; +- +- ebi { +- pinctrl_ebi_addr: ebi-addr-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_nand_addr: ebi-addr-1 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_cs0: ebi-cs0-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_cs1: ebi-cs1-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_cs2: ebi-cs2-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_cs3: ebi-cs3-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_data_0_7: ebi-data-lsb-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_data_8_15: ebi-data-msb-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_nandrdy: ebi-nandrdy-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_nrd_nandoe: ebi-nrd-nandoe-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_nwait: ebi-nwait-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_nwe_nandwe: ebi-nwe-nandwe-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 { +- atmel,pins = +- ; +- }; +- }; +- +- i2c0 { +- pinctrl_i2c0: i2c0-0 { +- atmel,pins = +- ; +- }; +- +- pinctrl_i2c0_gpio: i2c0-gpio { +- atmel,pins = +- ; +- }; +- }; +- +- i2c1 { +- pinctrl_i2c1: i2c1-0 { +- atmel,pins = +- ; /* TWCK1, conflicts with UART0 TX and DIBN */ +- }; +- +- pinctrl_i2c1_gpio: i2c1-gpio { +- atmel,pins = +- ; +- }; +- }; +- +- i2c2 { +- pinctrl_i2c2: i2c2-0 { +- atmel,pins = +- ; /* TWCK2, conflicts with RF0 */ +- }; +- +- pinctrl_i2c2_gpio: i2c2-gpio { +- atmel,pins = +- ; +- }; +- }; +- +- isi { +- pinctrl_isi_data_0_7: isi-0-data-0-7 { +- atmel,pins = +- ; /* ISI_HSYNC */ +- }; +- pinctrl_isi_data_8_9: isi-0-data-8-9 { +- atmel,pins = +- ; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */ +- }; +- pinctrl_isi_data_10_11: isi-0-data-10-11 { +- atmel,pins = +- ; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */ +- }; +- }; +- +- lcd { +- pinctrl_lcd_base: lcd-base-0 { +- atmel,pins = +- ; /* LCDPCK */ +- }; +- pinctrl_lcd_pwm: lcd-pwm-0 { +- atmel,pins = ; /* LCDPWM */ +- }; +- pinctrl_lcd_rgb444: lcd-rgb-0 { +- atmel,pins = +- ; /* LCDD11 pin */ +- }; +- pinctrl_lcd_rgb565: lcd-rgb-1 { +- atmel,pins = +- ; /* LCDD15 pin */ +- }; +- pinctrl_lcd_rgb666: lcd-rgb-2 { +- atmel,pins = +- ; /* LCDD23 pin */ +- }; +- pinctrl_lcd_rgb777: lcd-rgb-3 { +- atmel,pins = +- /* LCDDAT0 conflicts with TMS */ +- ; /* LCDD23 pin */ +- }; +- pinctrl_lcd_rgb888: lcd-rgb-4 { +- atmel,pins = +- ; /* LCDD23 pin */ +- }; +- }; +- +- macb0 { +- pinctrl_macb0_rmii: macb0_rmii-0 { +- atmel,pins = +- ; +- }; +- }; +- +- macb1 { +- pinctrl_macb1_rmii: macb1_rmii-0 { +- atmel,pins = +- ; +- }; +- }; +- +- mmc0 { +- pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { +- atmel,pins = +- ; +- }; +- pinctrl_mmc0_dat1_3: mmc0_dat1_3 { +- atmel,pins = +- ; +- }; +- pinctrl_mmc0_dat4_7: mmc0_dat4_7 { +- atmel,pins = +- ; +- }; +- }; +- +- mmc1 { +- pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { +- atmel,pins = +- ; +- }; +- pinctrl_mmc1_dat1_3: mmc1_dat1_3 { +- atmel,pins = +- ; +- }; +- }; +- +- nand0 { +- pinctrl_nand: nand-0 { +- atmel,pins = +- ; /* PC12 periph A Data bit 7 */ +- }; +- }; +- +- spi0 { +- pinctrl_spi0: spi0-0 { +- atmel,pins = +- ; +- }; +- }; +- +- ssc0 { +- pinctrl_ssc0_tx: ssc0_tx { +- atmel,pins = +- ; /* TD0 */ +- }; +- +- pinctrl_ssc0_rx: ssc0_rx { +- atmel,pins = +- ; /* RD0 */ +- }; +- }; +- +- ssc1 { +- pinctrl_ssc1_tx: ssc1_tx { +- atmel,pins = +- ; /* TD1 */ +- }; +- +- pinctrl_ssc1_rx: ssc1_rx { +- atmel,pins = +- ; /* RD1 */ +- }; +- }; +- +- spi1 { +- pinctrl_spi1: spi1-0 { +- atmel,pins = +- ; +- }; +- }; +- +- spi2 { +- pinctrl_spi2: spi2-0 { +- atmel,pins = +- ; +- }; +- }; +- +- uart0 { +- pinctrl_uart0: uart0-0 { +- atmel,pins = +- ; +- }; +- }; +- +- uart1 { +- pinctrl_uart1: uart1-0 { +- atmel,pins = +- ; +- }; +- }; +- +- usart0 { +- pinctrl_usart0: usart0-0 { +- atmel,pins = +- ; +- }; +- pinctrl_usart0_rts: usart0_rts-0 { +- atmel,pins = ; +- }; +- pinctrl_usart0_cts: usart0_cts-0 { +- atmel,pins = ; +- }; +- }; +- +- usart1 { +- pinctrl_usart1: usart1-0 { +- atmel,pins = +- ; +- }; +- pinctrl_usart1_rts: usart1_rts-0 { +- atmel,pins = ; +- }; +- pinctrl_usart1_cts: usart1_cts-0 { +- atmel,pins = ; +- }; +- }; +- +- usart2 { +- pinctrl_usart2: usart2-0 { +- atmel,pins = +- ; +- }; +- pinctrl_usart2_rts: usart2_rts-0 { +- atmel,pins = ; /* conflicts with G0_RX3, PWMH1 */ +- }; +- pinctrl_usart2_cts: usart2_cts-0 { +- atmel,pins = ; /* conflicts with G0_TXER, ISI_VSYNC */ +- }; +- }; +- +- usart3 { +- pinctrl_usart3: usart3-0 { +- atmel,pins = +- ; +- }; +- }; +- +- usart4 { +- pinctrl_usart4: usart4-0 { +- atmel,pins = +- ; +- }; +- pinctrl_usart4_rts: usart4_rts-0 { +- atmel,pins = ; /* conflicts with NWAIT, A19 */ +- }; +- pinctrl_usart4_cts: usart4_cts-0 { +- atmel,pins = ; /* conflicts with A0/NBS0, MCI0_CDB */ +- }; +- }; +- }; +- +- aic: interrupt-controller@fc06e000 { +- #interrupt-cells = <3>; +- compatible = "atmel,sama5d4-aic"; +- interrupt-controller; +- reg = <0xfc06e000 0x200>; +- atmel,external-irqs = <56>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sama7g5-pinfunc.h b/scripts/dtc/include-prefixes/arm/sama7g5-pinfunc.h +deleted file mode 100644 +index 4eb30445d205..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama7g5-pinfunc.h ++++ /dev/null +@@ -1,923 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +-#define PINMUX_PIN(no, func, ioset) \ +-(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20)) +- +-#define PIN_PA0 0 +-#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0) +-#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1) +-#define PIN_PA0__FLEXCOM0_IO0 PINMUX_PIN(PIN_PA0, 2, 1) +-#define PIN_PA0__CANTX3 PINMUX_PIN(PIN_PA0, 3, 1) +-#define PIN_PA0__PWML0 PINMUX_PIN(PIN_PA0, 5, 2) +-#define PIN_PA1 1 +-#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0) +-#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1) +-#define PIN_PA1__FLEXCOM0_IO1 PINMUX_PIN(PIN_PA1, 2, 1) +-#define PIN_PA1__CANRX3 PINMUX_PIN(PIN_PA1, 3, 1) +-#define PIN_PA1__D14 PINMUX_PIN(PIN_PA1, 4, 1) +-#define PIN_PA1__PWMH0 PINMUX_PIN(PIN_PA1, 5, 3) +-#define PIN_PA2 2 +-#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0) +-#define PIN_PA2__SDMMC0_RSTN PINMUX_PIN(PIN_PA2, 1, 1) +-#define PIN_PA2__FLEXCOM0_IO2 PINMUX_PIN(PIN_PA2, 2, 1) +-#define PIN_PA2__PDMC1_CLK PINMUX_PIN(PIN_PA2, 3, 1) +-#define PIN_PA2__D15 PINMUX_PIN(PIN_PA2, 4, 1) +-#define PIN_PA2__PWMH1 PINMUX_PIN(PIN_PA2, 5, 3) +-#define PIN_PA2__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA2, 6, 3) +-#define PIN_PA3 3 +-#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0) +-#define PIN_PA3__SDMMC0_DAT0 PINMUX_PIN(PIN_PA3, 1, 1) +-#define PIN_PA3__FLEXCOM0_IO3 PINMUX_PIN(PIN_PA3, 2, 1) +-#define PIN_PA3__PDMC1_DS0 PINMUX_PIN(PIN_PA3, 3, 1) +-#define PIN_PA3__NWR1_NBS1 PINMUX_PIN(PIN_PA3, 4, 1) +-#define PIN_PA3__PWML3 PINMUX_PIN(PIN_PA3, 5, 3) +-#define PIN_PA3__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA3, 6, 3) +-#define PIN_PA4 4 +-#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0) +-#define PIN_PA4__SDMMC0_DAT1 PINMUX_PIN(PIN_PA4, 1, 1) +-#define PIN_PA4__FLEXCOM0_IO4 PINMUX_PIN(PIN_PA4, 2, 1) +-#define PIN_PA4__PDMC1_DS1 PINMUX_PIN(PIN_PA4, 3, 1) +-#define PIN_PA4__NCS2 PINMUX_PIN(PIN_PA4, 4, 1) +-#define PIN_PA4__PWMH3 PINMUX_PIN(PIN_PA4, 5, 3) +-#define PIN_PA4__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA4, 6, 3) +-#define PIN_PA5 5 +-#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0) +-#define PIN_PA5__SDMMC0_DAT2 PINMUX_PIN(PIN_PA5, 1, 1) +-#define PIN_PA5__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA5, 2, 1) +-#define PIN_PA5__CANTX2 PINMUX_PIN(PIN_PA5, 3, 1) +-#define PIN_PA5__A23 PINMUX_PIN(PIN_PA5, 4, 1) +-#define PIN_PA5__PWMEXTRG0 PINMUX_PIN(PIN_PA5, 5, 3) +-#define PIN_PA5__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA5, 6, 3) +-#define PIN_PA6 6 +-#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0) +-#define PIN_PA6__SDMMC0_DAT3 PINMUX_PIN(PIN_PA6, 1, 1) +-#define PIN_PA6__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA6, 2, 1) +-#define PIN_PA6__CANRX2 PINMUX_PIN(PIN_PA6, 3, 1) +-#define PIN_PA6__A24 PINMUX_PIN(PIN_PA6, 4, 1) +-#define PIN_PA6__PWMEXTRG1 PINMUX_PIN(PIN_PA6, 5, 3) +-#define PIN_PA6__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA6, 6, 3) +-#define PIN_PA7 7 +-#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0) +-#define PIN_PA7__SDMMC0_DAT4 PINMUX_PIN(PIN_PA7, 1, 1) +-#define PIN_PA7__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA7, 2, 1) +-#define PIN_PA7__CANTX1 PINMUX_PIN(PIN_PA7, 3, 1) +-#define PIN_PA7__NWAIT PINMUX_PIN(PIN_PA7, 4, 1) +-#define PIN_PA7__PWMFI0 PINMUX_PIN(PIN_PA7, 5, 3) +-#define PIN_PA7__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA7, 6, 3) +-#define PIN_PA8 8 +-#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0) +-#define PIN_PA8__SDMMC0_DAT5 PINMUX_PIN(PIN_PA8, 1, 1) +-#define PIN_PA8__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA8, 2, 1) +-#define PIN_PA8__CANRX1 PINMUX_PIN(PIN_PA8, 3, 1) +-#define PIN_PA8__NCS0 PINMUX_PIN(PIN_PA8, 4, 1) +-#define PIN_PA8__PWMIF1 PINMUX_PIN(PIN_PA8, 5, 3) +-#define PIN_PA8__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA8, 6, 3) +-#define PIN_PA9 9 +-#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0) +-#define PIN_PA9__SDMMC0_DAT6 PINMUX_PIN(PIN_PA9, 1, 1) +-#define PIN_PA9__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA9, 2, 1) +-#define PIN_PA9__CANTX0 PINMUX_PIN(PIN_PA9, 3, 1) +-#define PIN_PA9__SMCK PINMUX_PIN(PIN_PA9, 4, 1) +-#define PIN_PA9__SPDIF_RX PINMUX_PIN(PIN_PA9, 5, 1) +-#define PIN_PA9__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA9, 6, 3) +-#define PIN_PA10 10 +-#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0) +-#define PIN_PA10__SDMMC0_DAT7 PINMUX_PIN(PIN_PA10, 1, 1) +-#define PIN_PA10__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA10, 2, 1) +-#define PIN_PA10__CANRX0 PINMUX_PIN(PIN_PA10, 3, 1) +-#define PIN_PA10__NCS1 PINMUX_PIN(PIN_PA10, 4, 1) +-#define PIN_PA10__SPDIF_TX PINMUX_PIN(PIN_PA10, 5, 1) +-#define PIN_PA10__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA10, 6, 3) +-#define PIN_PA11 11 +-#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0) +-#define PIN_PA11__SDMMC0_DS PINMUX_PIN(PIN_PA11, 1, 1) +-#define PIN_PA11__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA11, 2, 1) +-#define PIN_PA11__A0_NBS0 PINMUX_PIN(PIN_PA11, 4, 1) +-#define PIN_PA11__TIOA0 PINMUX_PIN(PIN_PA11, 5, 1) +-#define PIN_PA11__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA11, 6, 3) +-#define PIN_PA12 12 +-#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0) +-#define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1) +-#define PIN_PA12__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA12, 2, 1) +-#define PIN_PA12__FLEXCOM3_IO5 PINMUX_PIN(PIN_PA12, 4, 1) +-#define PIN_PA12__PWML2 PINMUX_PIN(PIN_PA12, 5, 3) +-#define PIN_PA12__FLEXCOM6_IO0 PINMUX_PIN(PIN_PA12, 6, 3) +-#define PIN_PA13 13 +-#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0) +-#define PIN_PA13__SDMMC0_1V8SEL PINMUX_PIN(PIN_PA13, 1, 1) +-#define PIN_PA13__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA13, 2, 1) +-#define PIN_PA13__FLEXCOM3_IO6 PINMUX_PIN(PIN_PA13, 4, 1) +-#define PIN_PA13__PWMH2 PINMUX_PIN(PIN_PA13, 5, 3) +-#define PIN_PA13__FLEXCOM6_IO1 PINMUX_PIN(PIN_PA13, 6, 3) +-#define PIN_PA14 14 +-#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0) +-#define PIN_PA14__SDMMC0_CD PINMUX_PIN(PIN_PA14, 1, 1) +-#define PIN_PA14__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA14, 2, 1) +-#define PIN_PA14__A25 PINMUX_PIN(PIN_PA14, 4, 1) +-#define PIN_PA14__PWML1 PINMUX_PIN(PIN_PA14, 5, 3) +-#define PIN_PA15 15 +-#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) +-#define PIN_PA15__G0_TXEN PINMUX_PIN(PIN_PA15, 1, 1) +-#define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 2, 1) +-#define PIN_PA15__ISC_MCK PINMUX_PIN(PIN_PA15, 3, 1) +-#define PIN_PA15__A1 PINMUX_PIN(PIN_PA15, 4, 1) +-#define PIN_PA15__TIOB0 PINMUX_PIN(PIN_PA15, 5, 1) +-#define PIN_PA16 16 +-#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0) +-#define PIN_PA16__G0_TX0 PINMUX_PIN(PIN_PA16, 1, 1) +-#define PIN_PA16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA16, 2, 1) +-#define PIN_PA16__ISC_D0 PINMUX_PIN(PIN_PA16, 3, 1) +-#define PIN_PA16__A2 PINMUX_PIN(PIN_PA16, 4, 1) +-#define PIN_PA16__TCLK0 PINMUX_PIN(PIN_PA16, 5, 1) +-#define PIN_PA17 17 +-#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0) +-#define PIN_PA17__G0_TX1 PINMUX_PIN(PIN_PA17, 1, 1) +-#define PIN_PA17__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA17, 2, 1) +-#define PIN_PA17__ISC_D1 PINMUX_PIN(PIN_PA17, 3, 1) +-#define PIN_PA17__A3 PINMUX_PIN(PIN_PA17, 4, 1) +-#define PIN_PA17__TIOA1 PINMUX_PIN(PIN_PA17, 5, 1) +-#define PIN_PA18 18 +-#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0) +-#define PIN_PA18__G0_RXDV PINMUX_PIN(PIN_PA18, 1, 1) +-#define PIN_PA18__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA18, 2, 1) +-#define PIN_PA18__ISC_D2 PINMUX_PIN(PIN_PA18, 3, 1) +-#define PIN_PA18__A4 PINMUX_PIN(PIN_PA18, 4, 1) +-#define PIN_PA18__TIOB1 PINMUX_PIN(PIN_PA18, 5, 1) +-#define PIN_PA19 19 +-#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0) +-#define PIN_PA19__G0_RX0 PINMUX_PIN(PIN_PA19, 1, 1) +-#define PIN_PA19__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA19, 2, 1) +-#define PIN_PA19__ISC_D3 PINMUX_PIN(PIN_PA19, 3, 1) +-#define PIN_PA19__A5 PINMUX_PIN(PIN_PA19, 4, 1) +-#define PIN_PA19__TCLK1 PINMUX_PIN(PIN_PA19, 5, 1) +-#define PIN_PA20 20 +-#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0) +-#define PIN_PA20__G0_RX1 PINMUX_PIN(PIN_PA20, 1, 1) +-#define PIN_PA20__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA20, 2, 1) +-#define PIN_PA20__ISC_D4 PINMUX_PIN(PIN_PA20, 3, 1) +-#define PIN_PA20__A6 PINMUX_PIN(PIN_PA20, 4, 1) +-#define PIN_PA20__TIOA2 PINMUX_PIN(PIN_PA20, 5, 1) +-#define PIN_PA21 21 +-#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0) +-#define PIN_PA21__G0_RXER PINMUX_PIN(PIN_PA21, 1, 1) +-#define PIN_PA21__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA21, 2, 1) +-#define PIN_PA21__ISC_D5 PINMUX_PIN(PIN_PA21, 3, 1) +-#define PIN_PA21__A7 PINMUX_PIN(PIN_PA21, 4, 1) +-#define PIN_PA21__TIOB2 PINMUX_PIN(PIN_PA21, 5, 1) +-#define PIN_PA22 22 +-#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0) +-#define PIN_PA22__G0_MDC PINMUX_PIN(PIN_PA22, 1, 1) +-#define PIN_PA22__FLEXCOM4_IO2 PINMUX_PIN(PIN_PA22, 2, 1) +-#define PIN_PA22__ISC_D6 PINMUX_PIN(PIN_PA22, 3, 1) +-#define PIN_PA22__A8 PINMUX_PIN(PIN_PA22, 4, 1) +-#define PIN_PA22__TCLK2 PINMUX_PIN(PIN_PA22, 5, 1) +-#define PIN_PA23 23 +-#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0) +-#define PIN_PA23__G0_MDIO PINMUX_PIN(PIN_PA23, 1, 1) +-#define PIN_PA23__FLEXCOM4_IO3 PINMUX_PIN(PIN_PA23, 2, 1) +-#define PIN_PA23__ISC_D7 PINMUX_PIN(PIN_PA23, 3, 1) +-#define PIN_PA23__A9 PINMUX_PIN(PIN_PA23, 4, 1) +-#define PIN_PA24 24 +-#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0) +-#define PIN_PA24__G0_TXCK PINMUX_PIN(PIN_PA24, 1, 1) +-#define PIN_PA24__FLEXCOM4_IO4 PINMUX_PIN(PIN_PA24, 2, 1) +-#define PIN_PA24__ISC_HSYNC PINMUX_PIN(PIN_PA24, 3, 1) +-#define PIN_PA24__A10 PINMUX_PIN(PIN_PA24, 4, 1) +-#define PIN_PA24__FLEXCOM0_IO5 PINMUX_PIN(PIN_PA24, 5, 1) +-#define PIN_PA25 25 +-#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0) +-#define PIN_PA25__G0_125CK PINMUX_PIN(PIN_PA25, 1, 1) +-#define PIN_PA25__FLEXCOM5_IO4 PINMUX_PIN(PIN_PA25, 2, 1) +-#define PIN_PA25__ISC_VSYNC PINMUX_PIN(PIN_PA25, 3, 1) +-#define PIN_PA25__A11 PINMUX_PIN(PIN_PA25, 4, 1) +-#define PIN_PA25__FLEXCOM0_IO6 PINMUX_PIN(PIN_PA25, 5, 1) +-#define PIN_PA25__FLEXCOM7_IO0 PINMUX_PIN(PIN_PA25, 6, 3) +-#define PIN_PA26 26 +-#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0) +-#define PIN_PA26__G0_TX2 PINMUX_PIN(PIN_PA26, 1, 1) +-#define PIN_PA26__FLEXCOM5_IO2 PINMUX_PIN(PIN_PA26, 2, 1) +-#define PIN_PA26__ISC_FIELD PINMUX_PIN(PIN_PA26, 3, 1) +-#define PIN_PA26__A12 PINMUX_PIN(PIN_PA26, 4, 1) +-#define PIN_PA26__TF0 PINMUX_PIN(PIN_PA26, 5, 1) +-#define PIN_PA26__FLEXCOM7_IO1 PINMUX_PIN(PIN_PA26, 6, 3) +-#define PIN_PA27 27 +-#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0) +-#define PIN_PA27__G0_TX3 PINMUX_PIN(PIN_PA27, 1, 1) +-#define PIN_PA27__FLEXCOM5_IO3 PINMUX_PIN(PIN_PA27, 2, 1) +-#define PIN_PA27__ISC_PCK PINMUX_PIN(PIN_PA27, 3, 1) +-#define PIN_PA27__A13 PINMUX_PIN(PIN_PA27, 4, 1) +-#define PIN_PA27__TK0 PINMUX_PIN(PIN_PA27, 5, 1) +-#define PIN_PA27__FLEXCOM8_IO0 PINMUX_PIN(PIN_PA27, 6, 3) +-#define PIN_PA28 28 +-#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0) +-#define PIN_PA28__G0_RX2 PINMUX_PIN(PIN_PA28, 1, 1) +-#define PIN_PA28__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA28, 2, 1) +-#define PIN_PA28__ISC_D8 PINMUX_PIN(PIN_PA28, 3, 1) +-#define PIN_PA28__A14 PINMUX_PIN(PIN_PA28, 4, 1) +-#define PIN_PA28__RD0 PINMUX_PIN(PIN_PA28, 5, 1) +-#define PIN_PA28__FLEXCOM8_IO1 PINMUX_PIN(PIN_PA28, 6, 3) +-#define PIN_PA29 29 +-#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0) +-#define PIN_PA29__G0_RX3 PINMUX_PIN(PIN_PA29, 1, 1) +-#define PIN_PA29__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA29, 2, 1) +-#define PIN_PA29__ISC_D9 PINMUX_PIN(PIN_PA29, 3, 1) +-#define PIN_PA29__A15 PINMUX_PIN(PIN_PA29, 4, 1) +-#define PIN_PA29__RF0 PINMUX_PIN(PIN_PA29, 5, 1) +-#define PIN_PA29__FLEXCOM9_IO0 PINMUX_PIN(PIN_PA29, 6, 3) +-#define PIN_PA30 30 +-#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0) +-#define PIN_PA30__G0_RXCK PINMUX_PIN(PIN_PA30, 1, 1) +-#define PIN_PA30__FLEXCOM6_IO4 PINMUX_PIN(PIN_PA30, 2, 1) +-#define PIN_PA30__ISC_D10 PINMUX_PIN(PIN_PA30, 3, 1) +-#define PIN_PA30__A16 PINMUX_PIN(PIN_PA30, 4, 1) +-#define PIN_PA30__RK0 PINMUX_PIN(PIN_PA30, 5, 1) +-#define PIN_PA30__FLEXCOM9_IO1 PINMUX_PIN(PIN_PA30, 6, 3) +-#define PIN_PA31 31 +-#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0) +-#define PIN_PA31__G0_TXER PINMUX_PIN(PIN_PA31, 1, 1) +-#define PIN_PA31__FLEXCOM6_IO2 PINMUX_PIN(PIN_PA31, 2, 1) +-#define PIN_PA31__ISC_D11 PINMUX_PIN(PIN_PA31, 3, 1) +-#define PIN_PA31__A17 PINMUX_PIN(PIN_PA31, 4, 1) +-#define PIN_PA31__TD0 PINMUX_PIN(PIN_PA31, 5, 1) +-#define PIN_PA31__FLEXCOM10_IO0 PINMUX_PIN(PIN_PA31, 6, 3) +-#define PIN_PB0 32 +-#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0) +-#define PIN_PB0__G0_COL PINMUX_PIN(PIN_PB0, 1, 1) +-#define PIN_PB0__FLEXCOM6_IO3 PINMUX_PIN(PIN_PB0, 2, 2) +-#define PIN_PB0__EXT_IRQ0 PINMUX_PIN(PIN_PB0, 3, 1) +-#define PIN_PB0__A18 PINMUX_PIN(PIN_PB0, 4, 1) +-#define PIN_PB0__SPDIF_RX PINMUX_PIN(PIN_PB0, 5, 2) +-#define PIN_PB0__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB0, 6, 3) +-#define PIN_PB1 33 +-#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0) +-#define PIN_PB1__G0_CRS PINMUX_PIN(PIN_PB1, 1, 1) +-#define PIN_PB1__FLEXCOM6_IO1 PINMUX_PIN(PIN_PB1, 2, 2) +-#define PIN_PB1__EXT_IRQ1 PINMUX_PIN(PIN_PB1, 3, 1) +-#define PIN_PB1__A19 PINMUX_PIN(PIN_PB1, 4, 1) +-#define PIN_PB1__SPDIF_TX PINMUX_PIN(PIN_PB1, 5, 2) +-#define PIN_PB1__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB1, 6, 3) +-#define PIN_PB2 34 +-#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0) +-#define PIN_PB2__G0_TSUCOMP PINMUX_PIN(PIN_PB2, 1, 1) +-#define PIN_PB2__FLEXCOM6_IO0 PINMUX_PIN(PIN_PB2, 2, 1) +-#define PIN_PB2__ADTRG PINMUX_PIN(PIN_PB2, 3, 1) +-#define PIN_PB2__A20 PINMUX_PIN(PIN_PB2, 4, 1) +-#define PIN_PB2__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB2, 6, 3) +-#define PIN_PB3 35 +-#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) +-#define PIN_PB3__RF1 PINMUX_PIN(PIN_PB3, 1, 1) +-#define PIN_PB3__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB3, 2, 1) +-#define PIN_PB3__PCK2 PINMUX_PIN(PIN_PB3, 3, 2) +-#define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 4, 1) +-#define PIN_PB4 36 +-#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0) +-#define PIN_PB4__TF1 PINMUX_PIN(PIN_PB4, 1, 1) +-#define PIN_PB4__FLEXCOM11_IO1 PINMUX_PIN(PIN_PB4, 2, 1) +-#define PIN_PB4__PCK3 PINMUX_PIN(PIN_PB4, 3, 2) +-#define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 4, 1) +-#define PIN_PB5 37 +-#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0) +-#define PIN_PB5__TK1 PINMUX_PIN(PIN_PB5, 1, 1) +-#define PIN_PB5__FLEXCOM11_IO2 PINMUX_PIN(PIN_PB5, 2, 1) +-#define PIN_PB5__PCK4 PINMUX_PIN(PIN_PB5, 3, 2) +-#define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 4, 1) +-#define PIN_PB6 38 +-#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0) +-#define PIN_PB6__RK1 PINMUX_PIN(PIN_PB6, 1, 1) +-#define PIN_PB6__FLEXCOM11_IO3 PINMUX_PIN(PIN_PB6, 2, 1) +-#define PIN_PB6__PCK5 PINMUX_PIN(PIN_PB6, 3, 2) +-#define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 4, 1) +-#define PIN_PB7 39 +-#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0) +-#define PIN_PB7__TD1 PINMUX_PIN(PIN_PB7, 1, 1) +-#define PIN_PB7__FLEXCOM11_IO4 PINMUX_PIN(PIN_PB7, 2, 1) +-#define PIN_PB7__FLEXCOM3_IO5 PINMUX_PIN(PIN_PB7, 3, 2) +-#define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 4, 1) +-#define PIN_PB8 40 +-#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0) +-#define PIN_PB8__RD1 PINMUX_PIN(PIN_PB8, 1, 1) +-#define PIN_PB8__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB8, 2, 1) +-#define PIN_PB8__FLEXCOM3_IO6 PINMUX_PIN(PIN_PB8, 3, 2) +-#define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 4, 1) +-#define PIN_PB9 41 +-#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0) +-#define PIN_PB9__QSPI0_IO3 PINMUX_PIN(PIN_PB9, 1, 1) +-#define PIN_PB9__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB9, 2, 1) +-#define PIN_PB9__PDMC0_CLK PINMUX_PIN(PIN_PB9, 3, 1) +-#define PIN_PB9__NCS3_NANDCS PINMUX_PIN(PIN_PB9, 4, 1) +-#define PIN_PB9__PWML0 PINMUX_PIN(PIN_PB9, 5, 2) +-#define PIN_PB10 42 +-#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0) +-#define PIN_PB10__QSPI0_IO2 PINMUX_PIN(PIN_PB10, 1, 1) +-#define PIN_PB10__FLEXCOM8_IO2 PINMUX_PIN(PIN_PB10, 2, 1) +-#define PIN_PB10__PDMC0_DS0 PINMUX_PIN(PIN_PB10, 3, 1) +-#define PIN_PB10__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PB10, 4, 1) +-#define PIN_PB10__PWMH0 PINMUX_PIN(PIN_PB10, 5, 2) +-#define PIN_PB11 43 +-#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0) +-#define PIN_PB11__QSPI0_IO1 PINMUX_PIN(PIN_PB11, 1, 1) +-#define PIN_PB11__FLEXCOM8_IO3 PINMUX_PIN(PIN_PB11, 2, 1) +-#define PIN_PB11__PDMC0_DS1 PINMUX_PIN(PIN_PB11, 3, 1) +-#define PIN_PB11__NRD_NANDOE PINMUX_PIN(PIN_PB11, 4, 1) +-#define PIN_PB11__PWML1 PINMUX_PIN(PIN_PB11, 5, 2) +-#define PIN_PB12 44 +-#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0) +-#define PIN_PB12__QSPI0_IO0 PINMUX_PIN(PIN_PB12, 1, 1) +-#define PIN_PB12__FLEXCOM8_IO4 PINMUX_PIN(PIN_PB12, 2, 1) +-#define PIN_PB12__FLEXCOM6_IO5 PINMUX_PIN(PIN_PB12, 3, 1) +-#define PIN_PB12__A21_NANDALE PINMUX_PIN(PIN_PB12, 4, 1) +-#define PIN_PB12__PWMH1 PINMUX_PIN(PIN_PB12, 5, 2) +-#define PIN_PB13 45 +-#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0) +-#define PIN_PB13__QSPI0_CS PINMUX_PIN(PIN_PB13, 1, 1) +-#define PIN_PB13__FLEXCOM9_IO0 PINMUX_PIN(PIN_PB13, 2, 1) +-#define PIN_PB13__FLEXCOM6_IO6 PINMUX_PIN(PIN_PB13, 3, 1) +-#define PIN_PB13__A22_NANDCLE PINMUX_PIN(PIN_PB13, 4, 1) +-#define PIN_PB13__PWML2 PINMUX_PIN(PIN_PB13, 5, 2) +-#define PIN_PB14 46 +-#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0) +-#define PIN_PB14__QSPI0_SCK PINMUX_PIN(PIN_PB14, 1, 1) +-#define PIN_PB14__FLEXCOM9_IO1 PINMUX_PIN(PIN_PB14, 2, 1) +-#define PIN_PB14__D0 PINMUX_PIN(PIN_PB14, 4, 1) +-#define PIN_PB14__PWMH2 PINMUX_PIN(PIN_PB14, 5, 2) +-#define PIN_PB15 47 +-#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0) +-#define PIN_PB15__QSPI0_SCKN PINMUX_PIN(PIN_PB15, 1, 1) +-#define PIN_PB15__FLEXCOM9_IO2 PINMUX_PIN(PIN_PB15, 2, 1) +-#define PIN_PB15__D1 PINMUX_PIN(PIN_PB15, 4, 1) +-#define PIN_PB15__PWML3 PINMUX_PIN(PIN_PB15, 5, 2) +-#define PIN_PB16 48 +-#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0) +-#define PIN_PB16__QSPI0_IO4 PINMUX_PIN(PIN_PB16, 1, 1) +-#define PIN_PB16__FLEXCOM9_IO3 PINMUX_PIN(PIN_PB16, 2, 1) +-#define PIN_PB16__PCK0 PINMUX_PIN(PIN_PB16, 3, 1) +-#define PIN_PB16__D2 PINMUX_PIN(PIN_PB16, 4, 1) +-#define PIN_PB16__PWMH3 PINMUX_PIN(PIN_PB16, 5, 2) +-#define PIN_PB16__EXT_IRQ0 PINMUX_PIN(PIN_PB16, 6, 2) +-#define PIN_PB17 49 +-#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0) +-#define PIN_PB17__QSPI0_IO5 PINMUX_PIN(PIN_PB17, 1, 1) +-#define PIN_PB17__FLEXCOM9_IO4 PINMUX_PIN(PIN_PB17, 2, 1) +-#define PIN_PB17__PCK1 PINMUX_PIN(PIN_PB17, 3, 1) +-#define PIN_PB17__D3 PINMUX_PIN(PIN_PB17, 4, 1) +-#define PIN_PB17__PWMEXTRG0 PINMUX_PIN(PIN_PB17, 5, 2) +-#define PIN_PB17__EXT_IRQ1 PINMUX_PIN(PIN_PB17, 6, 2) +-#define PIN_PB18 50 +-#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0) +-#define PIN_PB18__QSPI0_IO6 PINMUX_PIN(PIN_PB18, 1, 1) +-#define PIN_PB18__FLEXCOM10_IO0 PINMUX_PIN(PIN_PB18, 2, 1) +-#define PIN_PB18__PCK2 PINMUX_PIN(PIN_PB18, 3, 1) +-#define PIN_PB18__D4 PINMUX_PIN(PIN_PB18, 4, 1) +-#define PIN_PB18__PWMEXTRG1 PINMUX_PIN(PIN_PB18, 5, 2) +-#define PIN_PB19 51 +-#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0) +-#define PIN_PB19__QSPI0_IO7 PINMUX_PIN(PIN_PB19, 1, 1) +-#define PIN_PB19__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB19, 2, 1) +-#define PIN_PB19__PCK3 PINMUX_PIN(PIN_PB19, 3, 1) +-#define PIN_PB19__D5 PINMUX_PIN(PIN_PB19, 4, 1) +-#define PIN_PB19__PWMFI0 PINMUX_PIN(PIN_PB19, 5, 2) +-#define PIN_PB20 52 +-#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0) +-#define PIN_PB20__QSPI0_DQS PINMUX_PIN(PIN_PB20, 1, 1) +-#define PIN_PB20__FLEXCOM10_IO2 PINMUX_PIN(PIN_PB20, 2, 1) +-#define PIN_PB20__D6 PINMUX_PIN(PIN_PB20, 4, 1) +-#define PIN_PB20__PWMFI1 PINMUX_PIN(PIN_PB20, 5, 2) +-#define PIN_PB21 53 +-#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0) +-#define PIN_PB21__QSPI0_INT PINMUX_PIN(PIN_PB21, 1, 1) +-#define PIN_PB21__FLEXCOM10_IO3 PINMUX_PIN(PIN_PB21, 2, 1) +-#define PIN_PB21__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB21, 3, 1) +-#define PIN_PB21__D7 PINMUX_PIN(PIN_PB21, 4, 1) +-#define PIN_PB22 54 +-#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) +-#define PIN_PB22__QSPI1_IO3 PINMUX_PIN(PIN_PB22, 1, 1) +-#define PIN_PB22__FLEXCOM10_IO4 PINMUX_PIN(PIN_PB22, 2, 1) +-#define PIN_PB22__FLEXCOM9_IO6 PINMUX_PIN(PIN_PB22, 3, 1) +-#define PIN_PB22__NANDRDY PINMUX_PIN(PIN_PB22, 4, 1) +-#define PIN_PB23 55 +-#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0) +-#define PIN_PB23__QSPI1_IO2 PINMUX_PIN(PIN_PB23, 1, 1) +-#define PIN_PB23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB23, 2, 1) +-#define PIN_PB23__I2SMCC0_CK PINMUX_PIN(PIN_PB23, 3, 1) +-#define PIN_PB23__PCK4 PINMUX_PIN(PIN_PB23, 6, 1) +-#define PIN_PB24 56 +-#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0) +-#define PIN_PB24__QSPI1_IO1 PINMUX_PIN(PIN_PB24, 1, 1) +-#define PIN_PB24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB24, 2, 1) +-#define PIN_PB24__I2SMCC0_WS PINMUX_PIN(PIN_PB24, 3, 1) +-#define PIN_PB24__PCK5 PINMUX_PIN(PIN_PB24, 6, 1) +-#define PIN_PB25 57 +-#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0) +-#define PIN_PB25__QSPI1_IO0 PINMUX_PIN(PIN_PB25, 1, 1) +-#define PIN_PB25__FLEXCOM7_IO2 PINMUX_PIN(PIN_PB25, 2, 1) +-#define PIN_PB25__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PB25, 3, 1) +-#define PIN_PB25__PCK6 PINMUX_PIN(PIN_PB25, 6, 1) +-#define PIN_PB26 58 +-#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0) +-#define PIN_PB26__QSPI1_CS PINMUX_PIN(PIN_PB26, 1, 1) +-#define PIN_PB26__FLEXCOM7_IO3 PINMUX_PIN(PIN_PB26, 2, 1) +-#define PIN_PB26__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PB26, 3, 1) +-#define PIN_PB26__PWMEXTRG0 PINMUX_PIN(PIN_PB26, 5, 1) +-#define PIN_PB26__PCK7 PINMUX_PIN(PIN_PB26, 6, 1) +-#define PIN_PB27 59 +-#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0) +-#define PIN_PB27__QSPI1_SCK PINMUX_PIN(PIN_PB27, 1, 1) +-#define PIN_PB27__FLEXCOM7_IO4 PINMUX_PIN(PIN_PB27, 2, 1) +-#define PIN_PB27__I2SMCC0_MCK PINMUX_PIN(PIN_PB27, 3, 1) +-#define PIN_PB27__PWMEXTRG1 PINMUX_PIN(PIN_PB27, 5, 1) +-#define PIN_PB28 60 +-#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0) +-#define PIN_PB28__SDMMC1_RSTN PINMUX_PIN(PIN_PB28, 1, 1) +-#define PIN_PB28__ADTRG PINMUX_PIN(PIN_PB28, 2, 2) +-#define PIN_PB28__PWMFI0 PINMUX_PIN(PIN_PB28, 5, 1) +-#define PIN_PB28__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB28, 6, 4) +-#define PIN_PB29 61 +-#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0) +-#define PIN_PB29__SDMMC1_CMD PINMUX_PIN(PIN_PB29, 1, 1) +-#define PIN_PB29__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB29, 2, 2) +-#define PIN_PB29__FLEXCOM0_IO5 PINMUX_PIN(PIN_PB29, 3, 2) +-#define PIN_PB29__TIOA3 PINMUX_PIN(PIN_PB29, 4, 2) +-#define PIN_PB29__PWMFI1 PINMUX_PIN(PIN_PB29, 5, 1) +-#define PIN_PB29__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB29, 6, 4) +-#define PIN_PB30 62 +-#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0) +-#define PIN_PB30__SDMMC1_CK PINMUX_PIN(PIN_PB30, 1, 1) +-#define PIN_PB30__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB30, 2, 2) +-#define PIN_PB30__FLEXCOM0_IO6 PINMUX_PIN(PIN_PB30, 3, 2) +-#define PIN_PB30__TIOB3 PINMUX_PIN(PIN_PB30, 4, 1) +-#define PIN_PB30__PWMH0 PINMUX_PIN(PIN_PB30, 5, 1) +-#define PIN_PB30__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB30, 6, 4) +-#define PIN_PB31 63 +-#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0) +-#define PIN_PB31__SDMMC1_DAT0 PINMUX_PIN(PIN_PB31, 1, 1) +-#define PIN_PB31__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB31, 2, 2) +-#define PIN_PB31__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB31, 3, 2) +-#define PIN_PB31__TCLK3 PINMUX_PIN(PIN_PB31, 4, 1) +-#define PIN_PB31__PWML0 PINMUX_PIN(PIN_PB31, 5, 1) +-#define PIN_PB31__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB31, 6, 4) +-#define PIN_PC0 64 +-#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0) +-#define PIN_PC0__SDMMC1_DAT1 PINMUX_PIN(PIN_PC0, 1, 1) +-#define PIN_PC0__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC0, 2, 2) +-#define PIN_PC0__TIOA4 PINMUX_PIN(PIN_PC0, 4, 1) +-#define PIN_PC0__PWML1 PINMUX_PIN(PIN_PC0, 5, 1) +-#define PIN_PC0__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC0, 6, 4) +-#define PIN_PC1 65 +-#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0) +-#define PIN_PC1__SDMMC1_DAT2 PINMUX_PIN(PIN_PC1, 1, 1) +-#define PIN_PC1__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC1, 2, 2) +-#define PIN_PC1__TIOB4 PINMUX_PIN(PIN_PC1, 4, 1) +-#define PIN_PC1__PWMH1 PINMUX_PIN(PIN_PC1, 5, 1) +-#define PIN_PC1__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC1, 6, 4) +-#define PIN_PC2 66 +-#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0) +-#define PIN_PC2__SDMMC1_DAT3 PINMUX_PIN(PIN_PC2, 1, 1) +-#define PIN_PC2__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC2, 2, 2) +-#define PIN_PC2__TCLK4 PINMUX_PIN(PIN_PC2, 4, 1) +-#define PIN_PC2__PWML2 PINMUX_PIN(PIN_PC2, 5, 1) +-#define PIN_PC2__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC2, 6, 4) +-#define PIN_PC3 67 +-#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0) +-#define PIN_PC3__SDMMC1_WP PINMUX_PIN(PIN_PC3, 1, 1) +-#define PIN_PC3__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC3, 2, 2) +-#define PIN_PC3__TIOA5 PINMUX_PIN(PIN_PC3, 4, 1) +-#define PIN_PC3__PWMH2 PINMUX_PIN(PIN_PC3, 5, 1) +-#define PIN_PC3__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC3, 6, 4) +-#define PIN_PC4 68 +-#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0) +-#define PIN_PC4__SDMMC1_CD PINMUX_PIN(PIN_PC4, 1, 1) +-#define PIN_PC4__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC4, 2, 2) +-#define PIN_PC4__FLEXCOM9_IO6 PINMUX_PIN(PIN_PC4, 3, 2) +-#define PIN_PC4__TIOB5 PINMUX_PIN(PIN_PC4, 4, 1) +-#define PIN_PC4__PWML3 PINMUX_PIN(PIN_PC4, 5, 1) +-#define PIN_PC4__FLEXCOM11_IO0 PINMUX_PIN(PIN_PC4, 6, 4) +-#define PIN_PC5 69 +-#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0) +-#define PIN_PC5__SDMMC1_1V8SEL PINMUX_PIN(PIN_PC5, 1, 1) +-#define PIN_PC5__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC5, 2, 2) +-#define PIN_PC5__FLEXCOM6_IO5 PINMUX_PIN(PIN_PC5, 3, 2) +-#define PIN_PC5__TCLK5 PINMUX_PIN(PIN_PC5, 4, 1) +-#define PIN_PC5__PWMH3 PINMUX_PIN(PIN_PC5, 5, 1) +-#define PIN_PC5__FLEXCOM11_IO1 PINMUX_PIN(PIN_PC5, 6, 4) +-#define PIN_PC6 70 +-#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0) +-#define PIN_PC6__FLEXCOM4_IO4 PINMUX_PIN(PIN_PC6, 2, 2) +-#define PIN_PC6__FLEXCOM6_IO6 PINMUX_PIN(PIN_PC6, 3, 2) +-#define PIN_PC7 71 +-#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0) +-#define PIN_PC7__I2SMCC0_DIN0 PINMUX_PIN(PIN_PC7, 1, 1) +-#define PIN_PC7__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC7, 2, 2) +-#define PIN_PC8 72 +-#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0) +-#define PIN_PC8__I2SMCC0_DIN1 PINMUX_PIN(PIN_PC8, 1, 1) +-#define PIN_PC8__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC8, 2, 2) +-#define PIN_PC9 73 +-#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) +-#define PIN_PC9__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PC9, 1, 1) +-#define PIN_PC9__FLEXCOM7_IO2 PINMUX_PIN(PIN_PC9, 2, 2) +-#define PIN_PC9__FLEXCOM1_IO0 PINMUX_PIN(PIN_PC9, 6, 4) +-#define PIN_PC10 74 +-#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0) +-#define PIN_PC10__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PC10, 1, 1) +-#define PIN_PC10__FLEXCOM7_IO3 PINMUX_PIN(PIN_PC10, 2, 2) +-#define PIN_PC10__FLEXCOM1_IO1 PINMUX_PIN(PIN_PC10, 6, 4) +-#define PIN_PC11 75 +-#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0) +-#define PIN_PC11__I2SMCC1_CK PINMUX_PIN(PIN_PC11, 1, 1) +-#define PIN_PC11__FLEXCOM7_IO4 PINMUX_PIN(PIN_PC11, 2, 2) +-#define PIN_PC11__FLEXCOM2_IO0 PINMUX_PIN(PIN_PC11, 6, 4) +-#define PIN_PC12 76 +-#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0) +-#define PIN_PC12__I2SMCC1_WS PINMUX_PIN(PIN_PC12, 1, 1) +-#define PIN_PC12__FLEXCOM8_IO2 PINMUX_PIN(PIN_PC12, 2, 2) +-#define PIN_PC12__FLEXCOM2_IO1 PINMUX_PIN(PIN_PC12, 6, 4) +-#define PIN_PC13 77 +-#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0) +-#define PIN_PC13__I2SMCC1_MCK PINMUX_PIN(PIN_PC13, 1, 1) +-#define PIN_PC13__FLEXCOM8_IO1 PINMUX_PIN(PIN_PC13, 2, 2) +-#define PIN_PC13__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC13, 6, 4) +-#define PIN_PC14 78 +-#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0) +-#define PIN_PC14__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PC14, 1, 1) +-#define PIN_PC14__FLEXCOM8_IO0 PINMUX_PIN(PIN_PC14, 2, 2) +-#define PIN_PC14__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC14, 6, 4) +-#define PIN_PC15 79 +-#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) +-#define PIN_PC15__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PC15, 1, 1) +-#define PIN_PC15__FLEXCOM8_IO3 PINMUX_PIN(PIN_PC15, 2, 2) +-#define PIN_PC15__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC15, 6, 4) +-#define PIN_PC16 80 +-#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0) +-#define PIN_PC16__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PC16, 1, 1) +-#define PIN_PC16__FLEXCOM8_IO4 PINMUX_PIN(PIN_PC16, 2, 2) +-#define PIN_PC16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC16, 6, 4) +-#define PIN_PC17 81 +-#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0) +-#define PIN_PC17__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PC17, 1, 1) +-#define PIN_PC17__EXT_IRQ0 PINMUX_PIN(PIN_PC17, 2, 3) +-#define PIN_PC17__FLEXCOM5_IO0 PINMUX_PIN(PIN_PC17, 6, 4) +-#define PIN_PC18 82 +-#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0) +-#define PIN_PC18__I2SMCC1_DIN0 PINMUX_PIN(PIN_PC18, 1, 1) +-#define PIN_PC18__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC18, 2, 2) +-#define PIN_PC18__FLEXCOM5_IO1 PINMUX_PIN(PIN_PC18, 6, 4) +-#define PIN_PC19 83 +-#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0) +-#define PIN_PC19__I2SMCC1_DIN1 PINMUX_PIN(PIN_PC19, 1, 1) +-#define PIN_PC19__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC19, 2, 2) +-#define PIN_PC19__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC19, 6, 4) +-#define PIN_PC20 84 +-#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0) +-#define PIN_PC20__I2SMCC1_DIN2 PINMUX_PIN(PIN_PC20, 1, 1) +-#define PIN_PC20__FLEXCOM9_IO4 PINMUX_PIN(PIN_PC20, 2, 2) +-#define PIN_PC20__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC20, 6, 4) +-#define PIN_PC21 85 +-#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0) +-#define PIN_PC21__I2SMCC1_DIN3 PINMUX_PIN(PIN_PC21, 1, 1) +-#define PIN_PC21__FLEXCOM9_IO2 PINMUX_PIN(PIN_PC21, 2, 2) +-#define PIN_PC21__D3 PINMUX_PIN(PIN_PC21, 4, 2) +-#define PIN_PC21__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC21, 6, 5) +-#define PIN_PC22 86 +-#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0) +-#define PIN_PC22__I2SMCC0_DIN2 PINMUX_PIN(PIN_PC22, 1, 1) +-#define PIN_PC22__FLEXCOM9_IO3 PINMUX_PIN(PIN_PC22, 2, 2) +-#define PIN_PC22__D4 PINMUX_PIN(PIN_PC22, 4, 2) +-#define PIN_PC22__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC22, 6, 5) +-#define PIN_PC23 87 +-#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0) +-#define PIN_PC23__I2SMCC0_DIN3 PINMUX_PIN(PIN_PC23, 1, 1) +-#define PIN_PC23__FLEXCOM0_IO5 PINMUX_PIN(PIN_PC23, 2, 3) +-#define PIN_PC23__D5 PINMUX_PIN(PIN_PC23, 4, 2) +-#define PIN_PC23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC23, 6, 5) +-#define PIN_PC24 88 +-#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0) +-#define PIN_PC24__FLEXCOM0_IO6 PINMUX_PIN(PIN_PC24, 2, 3) +-#define PIN_PC24__EXT_IRQ1 PINMUX_PIN(PIN_PC24, 3, 3) +-#define PIN_PC24__D6 PINMUX_PIN(PIN_PC24, 4, 2) +-#define PIN_PC24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC24, 6, 5) +-#define PIN_PC25 89 +-#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0) +-#define PIN_PC25__NTRST PINMUX_PIN(PIN_PC25, 1, 1) +-#define PIN_PC26 90 +-#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0) +-#define PIN_PC26__TCK_SWCLK PINMUX_PIN(PIN_PC26, 1, 1) +-#define PIN_PC27 91 +-#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0) +-#define PIN_PC27__TMS_SWDIO PINMUX_PIN(PIN_PC27, 1, 1) +-#define PIN_PC28 92 +-#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0) +-#define PIN_PC28__TDI PINMUX_PIN(PIN_PC28, 1, 1) +-#define PIN_PC29 93 +-#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0) +-#define PIN_PC29__TDO PINMUX_PIN(PIN_PC29, 1, 1) +-#define PIN_PC30 94 +-#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0) +-#define PIN_PC30__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC30, 2, 2) +-#define PIN_PC31 95 +-#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0) +-#define PIN_PC31__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC31, 2, 2) +-#define PIN_PD0 96 +-#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0) +-#define PIN_PD0__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD0, 2, 2) +-#define PIN_PD1 97 +-#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0) +-#define PIN_PD1__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD1, 2, 2) +-#define PIN_PD2 98 +-#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0) +-#define PIN_PD2__SDMMC2_RSTN PINMUX_PIN(PIN_PD2, 1, 1) +-#define PIN_PD2__PCK0 PINMUX_PIN(PIN_PD2, 2, 2) +-#define PIN_PD2__CANTX4 PINMUX_PIN(PIN_PD2, 3, 1) +-#define PIN_PD2__D7 PINMUX_PIN(PIN_PD2, 4, 2) +-#define PIN_PD2__TIOA0 PINMUX_PIN(PIN_PD2, 5, 2) +-#define PIN_PD2__FLEXCOM8_IO0 PINMUX_PIN(PIN_PD2, 6, 5) +-#define PIN_PD3 99 +-#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0) +-#define PIN_PD3__SDMMC2_CMD PINMUX_PIN(PIN_PD3, 1, 1) +-#define PIN_PD3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD3, 2, 2) +-#define PIN_PD3__CANRX4 PINMUX_PIN(PIN_PD3, 3, 1) +-#define PIN_PD3__NANDRDY PINMUX_PIN(PIN_PD3, 4, 2) +-#define PIN_PD3__TIOB0 PINMUX_PIN(PIN_PD3, 5, 2) +-#define PIN_PD3__FLEXCOM8_IO1 PINMUX_PIN(PIN_PD3, 6, 5) +-#define PIN_PD4 100 +-#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0) +-#define PIN_PD4__SDMMC2_CK PINMUX_PIN(PIN_PD4, 1, 1) +-#define PIN_PD4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD4, 2, 2) +-#define PIN_PD4__CANTX5 PINMUX_PIN(PIN_PD4, 3, 1) +-#define PIN_PD4__NCS3_NANDCS PINMUX_PIN(PIN_PD4, 4, 2) +-#define PIN_PD4__TCLK0 PINMUX_PIN(PIN_PD4, 5, 2) +-#define PIN_PD4__FLEXCOM9_IO0 PINMUX_PIN(PIN_PD4, 6, 5) +-#define PIN_PD5 101 +-#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0) +-#define PIN_PD5__SDMMC2_DAT0 PINMUX_PIN(PIN_PD5, 1, 1) +-#define PIN_PD5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PD5, 2, 2) +-#define PIN_PD5__CANRX5 PINMUX_PIN(PIN_PD5, 3, 1) +-#define PIN_PD5__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PD5, 4, 2) +-#define PIN_PD5__TIOA1 PINMUX_PIN(PIN_PD5, 5, 2) +-#define PIN_PD5__FLEXCOM9_IO1 PINMUX_PIN(PIN_PD5, 6, 5) +-#define PIN_PD6 102 +-#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0) +-#define PIN_PD6__SDMMC2_DAT1 PINMUX_PIN(PIN_PD6, 1, 1) +-#define PIN_PD6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PD6, 2, 2) +-#define PIN_PD6__SPDIF_RX PINMUX_PIN(PIN_PD6, 3, 3) +-#define PIN_PD6__NRD_NANDOE PINMUX_PIN(PIN_PD6, 4, 2) +-#define PIN_PD6__TIOB1 PINMUX_PIN(PIN_PD6, 5, 2) +-#define PIN_PD6__FLEXCOM10_IO0 PINMUX_PIN(PIN_PD6, 6, 5) +-#define PIN_PD7 103 +-#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0) +-#define PIN_PD7__SDMMC2_DAT2 PINMUX_PIN(PIN_PD7, 1, 1) +-#define PIN_PD7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PD7, 2, 2) +-#define PIN_PD7__SPDIF_TX PINMUX_PIN(PIN_PD7, 2, 2) +-#define PIN_PD7__A21_NANDALE PINMUX_PIN(PIN_PD7, 4, 2) +-#define PIN_PD7__TCLK1 PINMUX_PIN(PIN_PD7, 5, 2) +-#define PIN_PD7__FLEXCOM10_IO1 PINMUX_PIN(PIN_PD7, 6, 5) +-#define PIN_PD8 104 +-#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) +-#define PIN_PD8__SDMMC2_DAT3 PINMUX_PIN(PIN_PD8, 1, 1) +-#define PIN_PD8__I2SMCC0_DIN0 PINMUX_PIN(PIN_PD8, 3, 1) +-#define PIN_PD8__A11_NANDCLE PINMUX_PIN(PIN_PD8, 4, 2) +-#define PIN_PD8__TIOA2 PINMUX_PIN(PIN_PD8, 5, 2) +-#define PIN_PD8__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD8, 6, 5) +-#define PIN_PD9 105 +-#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0) +-#define PIN_PD9__SDMMC2_WP PINMUX_PIN(PIN_PD9, 1, 1) +-#define PIN_PD9__I2SMCC0_DIN1 PINMUX_PIN(PIN_PD9, 3, 2) +-#define PIN_PD9__D0 PINMUX_PIN(PIN_PD9, 4, 2) +-#define PIN_PD9__TIOB2 PINMUX_PIN(PIN_PD9, 5, 2) +-#define PIN_PD9__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD9, 6, 5) +-#define PIN_PD10 106 +-#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0) +-#define PIN_PD10__SDMMC2_CD PINMUX_PIN(PIN_PD10, 1, 1) +-#define PIN_PD10__PCK6 PINMUX_PIN(PIN_PD10, 2, 2) +-#define PIN_PD10__I2SMCC0_DIN2 PINMUX_PIN(PIN_PD10, 3, 2) +-#define PIN_PD10__D1 PINMUX_PIN(PIN_PD10, 4, 2) +-#define PIN_PD10__TCLK2 PINMUX_PIN(PIN_PD10, 5, 2) +-#define PIN_PD10__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD10, 6, 3) +-#define PIN_PD11 107 +-#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0) +-#define PIN_PD11__SDMMC2_1V8SEL PINMUX_PIN(PIN_PD11, 1, 1) +-#define PIN_PD11__PCK7 PINMUX_PIN(PIN_PD11, 2, 2) +-#define PIN_PD11__I2SMCC0_DIN3 PINMUX_PIN(PIN_PD11, 3, 2) +-#define PIN_PD11__D2 PINMUX_PIN(PIN_PD11, 4, 2) +-#define PIN_PD11__TIOA3 PINMUX_PIN(PIN_PD11, 5, 2) +-#define PIN_PD11__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD11, 6, 3) +-#define PIN_PD12 108 +-#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0) +-#define PIN_PD12__PCK1 PINMUX_PIN(PIN_PD12, 1, 2) +-#define PIN_PD12__FLEXCOM1_IO0 PINMUX_PIN(PIN_PD12, 2, 2) +-#define PIN_PD12__CANTX0 PINMUX_PIN(PIN_PD12, 4, 2) +-#define PIN_PD12__TIOB3 PINMUX_PIN(PIN_PD12, 5, 2) +-#define PIN_PD13 109 +-#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0) +-#define PIN_PD13__I2SMCC0_CK PINMUX_PIN(PIN_PD13, 1, 2) +-#define PIN_PD13__FLEXCOM1_IO1 PINMUX_PIN(PIN_PD13, 2, 2) +-#define PIN_PD13__PWML0 PINMUX_PIN(PIN_PD13, 3, 4) +-#define PIN_PD13__CANRX0 PINMUX_PIN(PIN_PD13, 4, 2) +-#define PIN_PD13__TCLK3 PINMUX_PIN(PIN_PD13, 5, 2) +-#define PIN_PD14 110 +-#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0) +-#define PIN_PD14__I2SMCC0_MCK PINMUX_PIN(PIN_PD14, 1, 2) +-#define PIN_PD14__FLEXCOM1_IO2 PINMUX_PIN(PIN_PD14, 2, 2) +-#define PIN_PD14__PWMH0 PINMUX_PIN(PIN_PD14, 3, 4) +-#define PIN_PD14__CANTX1 PINMUX_PIN(PIN_PD14, 4, 2) +-#define PIN_PD14__TIOA4 PINMUX_PIN(PIN_PD14, 5, 2) +-#define PIN_PD14__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD14, 6, 5) +-#define PIN_PD15 111 +-#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0) +-#define PIN_PD15__I2SMCC0_WS PINMUX_PIN(PIN_PD15, 1, 2) +-#define PIN_PD15__FLEXCOM1_IO3 PINMUX_PIN(PIN_PD15, 2, 2) +-#define PIN_PD15__PWML1 PINMUX_PIN(PIN_PD15, 3, 4) +-#define PIN_PD15__CANRX1 PINMUX_PIN(PIN_PD15, 4, 2) +-#define PIN_PD15__TIOB4 PINMUX_PIN(PIN_PD15, 5, 2) +-#define PIN_PD15__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD15, 6, 5) +-#define PIN_PD16 112 +-#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0) +-#define PIN_PD16__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PD16, 1, 2) +-#define PIN_PD16__FLEXCOM1_IO4 PINMUX_PIN(PIN_PD16, 2, 2) +-#define PIN_PD16__PWMH1 PINMUX_PIN(PIN_PD16, 3, 4) +-#define PIN_PD16__CANTX2 PINMUX_PIN(PIN_PD16, 4, 2) +-#define PIN_PD16__TCLK4 PINMUX_PIN(PIN_PD16, 5, 2) +-#define PIN_PD16__FLEXCOM3_IO0 PINMUX_PIN(PIN_PD16, 6, 5) +-#define PIN_PD17 113 +-#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0) +-#define PIN_PD17__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PD17, 1, 2) +-#define PIN_PD17__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD17, 2, 2) +-#define PIN_PD17__PWML2 PINMUX_PIN(PIN_PD17, 3, 4) +-#define PIN_PD17__CANRX2 PINMUX_PIN(PIN_PD17, 4, 2) +-#define PIN_PD17__TIOA5 PINMUX_PIN(PIN_PD17, 5, 2) +-#define PIN_PD17__FLEXCOM3_IO1 PINMUX_PIN(PIN_PD17, 6, 5) +-#define PIN_PD18 114 +-#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0) +-#define PIN_PD18__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PD18, 1, 2) +-#define PIN_PD18__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD18, 2, 2) +-#define PIN_PD18__PWMH2 PINMUX_PIN(PIN_PD18, 3, 4) +-#define PIN_PD18__CANTX3 PINMUX_PIN(PIN_PD18, 4, 2) +-#define PIN_PD18__TIOB5 PINMUX_PIN(PIN_PD18, 5, 2) +-#define PIN_PD18__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD18, 6, 5) +-#define PIN_PD19 115 +-#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0) +-#define PIN_PD19__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PD19, 1, 2) +-#define PIN_PD19__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD19, 2, 2) +-#define PIN_PD19__PWML3 PINMUX_PIN(PIN_PD19, 3, 4) +-#define PIN_PD19__CANRX3 PINMUX_PIN(PIN_PD19, 4, 2) +-#define PIN_PD19__TCLK5 PINMUX_PIN(PIN_PD19, 5, 2) +-#define PIN_PD19__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD19, 6, 5) +-#define PIN_PD20 116 +-#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0) +-#define PIN_PD20__PCK0 PINMUX_PIN(PIN_PD20, 1, 3) +-#define PIN_PD20__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD20, 2, 2) +-#define PIN_PD20__PWMH3 PINMUX_PIN(PIN_PD20, 3, 4) +-#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 4, 2) +-#define PIN_PD20__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD20, 6, 5) +-#define PIN_PD21 117 +-#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) +-#define PIN_PD21__PCK1 PINMUX_PIN(PIN_PD21, 1, 3) +-#define PIN_PD21__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD21, 2, 2) +-#define PIN_PD21__CANRX4 PINMUX_PIN(PIN_PD21, 4, 2) +-#define PIN_PD21__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD21, 6, 5) +-#define PIN_PD21__G1_TXEN PINMUX_PIN(PIN_PD21, 7, 1) +-#define PIN_PD22 118 +-#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0) +-#define PIN_PD22__PDMC0_CLK PINMUX_PIN(PIN_PD22, 1, 2) +-#define PIN_PD22__PWMEXTRG0 PINMUX_PIN(PIN_PD22, 3, 4) +-#define PIN_PD22__RD1 PINMUX_PIN(PIN_PD22, 4, 2) +-#define PIN_PD22__CANTX5 PINMUX_PIN(PIN_PD22, 6, 2) +-#define PIN_PD22__G1_TX0 PINMUX_PIN(PIN_PD22, 7, 1) +-#define PIN_PD23 119 +-#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0) +-#define PIN_PD23__PDMC0_DS0 PINMUX_PIN(PIN_PD23, 1, 2) +-#define PIN_PD23__PWMEXTRG1 PINMUX_PIN(PIN_PD23, 3, 4) +-#define PIN_PD23__RF1 PINMUX_PIN(PIN_PD23, 4, 2) +-#define PIN_PD23__ISC_MCK PINMUX_PIN(PIN_PD23, 5, 2) +-#define PIN_PD23__CANRX5 PINMUX_PIN(PIN_PD23, 6, 2) +-#define PIN_PD23__G1_TX1 PINMUX_PIN(PIN_PD23, 7, 1) +-#define PIN_PD24 120 +-#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) +-#define PIN_PD24__PDMC0_DS1 PINMUX_PIN(PIN_PD24, 1, 2) +-#define PIN_PD24__PWMFI0 PINMUX_PIN(PIN_PD24, 3, 4) +-#define PIN_PD24__RK1 PINMUX_PIN(PIN_PD24, 4, 2) +-#define PIN_PD24__ISC_D0 PINMUX_PIN(PIN_PD24, 5, 2) +-#define PIN_PD24__G1_RXDV PINMUX_PIN(PIN_PD24, 7, 1) +-#define PIN_PD25 121 +-#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) +-#define PIN_PD25__PDMC1_CLK PINMUX_PIN(PIN_PD25, 1, 2) +-#define PIN_PD25__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD25, 2, 2) +-#define PIN_PD25__PWMFI1 PINMUX_PIN(PIN_PD25, 3, 4) +-#define PIN_PD25__TD1 PINMUX_PIN(PIN_PD25, 4, 2) +-#define PIN_PD25__ISC_D1 PINMUX_PIN(PIN_PD25, 5, 2) +-#define PIN_PD25__G1_RX0 PINMUX_PIN(PIN_PD25, 7, 1) +-#define PIN_PD26 122 +-#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0) +-#define PIN_PD26__PDMC1_DS0 PINMUX_PIN(PIN_PD26, 1, 2) +-#define PIN_PD26__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD26, 2, 2) +-#define PIN_PD26__ADTRG PINMUX_PIN(PIN_PD26, 3, 3) +-#define PIN_PD26__TF1 PINMUX_PIN(PIN_PD26, 4, 2) +-#define PIN_PD26__ISC_D2 PINMUX_PIN(PIN_PD26, 5, 2) +-#define PIN_PD26__G1_RX1 PINMUX_PIN(PIN_PD26, 7, 1) +-#define PIN_PD27 123 +-#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0) +-#define PIN_PD27__PDMC1_DS1 PINMUX_PIN(PIN_PD27, 1, 2) +-#define PIN_PD27__FLEXCOM5_IO2 PINMUX_PIN(PIN_PD27, 2, 2) +-#define PIN_PD27__TIOA0 PINMUX_PIN(PIN_PD27, 3, 3) +-#define PIN_PD27__TK1 PINMUX_PIN(PIN_PD27, 4, 2) +-#define PIN_PD27__ISC_D3 PINMUX_PIN(PIN_PD27, 5, 2) +-#define PIN_PD27__G1_RXER PINMUX_PIN(PIN_PD27, 7, 1) +-#define PIN_PD28 124 +-#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0) +-#define PIN_PD28__RD0 PINMUX_PIN(PIN_PD28, 1, 2) +-#define PIN_PD28__FLEXCOM5_IO3 PINMUX_PIN(PIN_PD28, 2, 2) +-#define PIN_PD28__TIOB0 PINMUX_PIN(PIN_PD28, 3, 3) +-#define PIN_PD28__I2SMCC1_CK PINMUX_PIN(PIN_PD28, 4, 2) +-#define PIN_PD28__ISC_D4 PINMUX_PIN(PIN_PD28, 5, 2) +-#define PIN_PD28__PWML3 PINMUX_PIN(PIN_PD28, 6, 5) +-#define PIN_PD28__G1_MDC PINMUX_PIN(PIN_PD28, 7, 1) +-#define PIN_PD29 125 +-#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0) +-#define PIN_PD29__RF0 PINMUX_PIN(PIN_PD29, 1, 2) +-#define PIN_PD29__FLEXCOM5_IO4 PINMUX_PIN(PIN_PD29, 2, 2) +-#define PIN_PD29__TCLK0 PINMUX_PIN(PIN_PD29, 3, 3) +-#define PIN_PD29__I2SMCC1_WS PINMUX_PIN(PIN_PD29, 4, 2) +-#define PIN_PD29__ISC_D5 PINMUX_PIN(PIN_PD29, 5, 2) +-#define PIN_PD29__PWMH3 PINMUX_PIN(PIN_PD29, 6, 5) +-#define PIN_PD29__G1_MDIO PINMUX_PIN(PIN_PD29, 7, 1) +-#define PIN_PD30 126 +-#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0) +-#define PIN_PD30__RK0 PINMUX_PIN(PIN_PD30, 1, 2) +-#define PIN_PD30__FLEXCOM6_IO0 PINMUX_PIN(PIN_PD30, 2, 2) +-#define PIN_PD30__TIOA1 PINMUX_PIN(PIN_PD30, 3, 3) +-#define PIN_PD30__I2SMCC1_MCK PINMUX_PIN(PIN_PD30, 4, 2) +-#define PIN_PD30__ISC_D6 PINMUX_PIN(PIN_PD30, 5, 2) +-#define PIN_PD30__PWMEXTRG0 PINMUX_PIN(PIN_PD30, 6, 5) +-#define PIN_PD30__G1_TXCK PINMUX_PIN(PIN_PD30, 7, 1) +-#define PIN_PD31 127 +-#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0) +-#define PIN_PD31__TD0 PINMUX_PIN(PIN_PD31, 1, 2) +-#define PIN_PD31__FLEXCOM6_IO1 PINMUX_PIN(PIN_PD31, 2, 2) +-#define PIN_PD31__TIOB1 PINMUX_PIN(PIN_PD31, 3, 3) +-#define PIN_PD31__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PD31, 4, 2) +-#define PIN_PD31__ISC_D7 PINMUX_PIN(PIN_PD31, 5, 2) +-#define PIN_PD31__PWM_EXTRG1 PINMUX_PIN(PIN_PD31, 6, 5) +-#define PIN_PD31__G1_TX2 PINMUX_PIN(PIN_PD31, 7, 1) +-#define PIN_PE0 128 +-#define PIN_PE0__GPIO PINMUX_PIN(PIN_PE0, 0, 0) +-#define PIN_PE0__TF0 PINMUX_PIN(PIN_PE0, 1, 2) +-#define PIN_PE0__FLEXCOM6_IO2 PINMUX_PIN(PIN_PE0, 2, 2) +-#define PIN_PE0__TCLK1 PINMUX_PIN(PIN_PE0, 3, 3) +-#define PIN_PE0__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PE0, 4, 2) +-#define PIN_PE0__ISC_HSYNC PINMUX_PIN(PIN_PE0, 5, 2) +-#define PIN_PE0__PWMFI0 PINMUX_PIN(PIN_PE0, 6, 5) +-#define PIN_PE0__G1_TX3 PINMUX_PIN(PIN_PE0, 7, 1) +-#define PIN_PE1 129 +-#define PIN_PE1__GPIO PINMUX_PIN(PIN_PE1, 0, 0) +-#define PIN_PE1__TK0 PINMUX_PIN(PIN_PE1, 1, 2) +-#define PIN_PE1__FLEXCOM6_IO3 PINMUX_PIN(PIN_PE1, 2, 2) +-#define PIN_PE1__TIOA2 PINMUX_PIN(PIN_PE1, 3, 3) +-#define PIN_PE1__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PE1, 4, 2) +-#define PIN_PE1__ISC_VSYNC PINMUX_PIN(PIN_PE1, 5, 2) +-#define PIN_PE1__PWMFI1 PINMUX_PIN(PIN_PE1, 6, 5) +-#define PIN_PE1__G1_RX2 PINMUX_PIN(PIN_PE1, 7, 1) +-#define PIN_PE2 130 +-#define PIN_PE2__GPIO PINMUX_PIN(PIN_PE2, 0, 0) +-#define PIN_PE2__PWML0 PINMUX_PIN(PIN_PE2, 1, 5) +-#define PIN_PE2__FLEXCOM6_IO4 PINMUX_PIN(PIN_PE2, 2, 2) +-#define PIN_PE2__TIOB2 PINMUX_PIN(PIN_PE2, 3, 3) +-#define PIN_PE2__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PE2, 4, 2) +-#define PIN_PE2__ISC_FIELD PINMUX_PIN(PIN_PE2, 5, 2) +-#define PIN_PE2__G1_RX3 PINMUX_PIN(PIN_PE2, 7, 1) +-#define PIN_PE3 131 +-#define PIN_PE3__GPIO PINMUX_PIN(PIN_PE3, 0, 0) +-#define PIN_PE3__PWMH0 PINMUX_PIN(PIN_PE3, 1, 5) +-#define PIN_PE3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PE3, 2, 4) +-#define PIN_PE3__TCLK2 PINMUX_PIN(PIN_PE3, 3, 3) +-#define PIN_PE3__I2SMCC1_DIN0 PINMUX_PIN(PIN_PE3, 4, 2) +-#define PIN_PE3__ISC_PCK PINMUX_PIN(PIN_PE3, 5, 2) +-#define PIN_PE3__G1_RXCK PINMUX_PIN(PIN_PE3, 7, 1) +-#define PIN_PE4 132 +-#define PIN_PE4__GPIO PINMUX_PIN(PIN_PE4, 0, 0) +-#define PIN_PE4__PWML1 PINMUX_PIN(PIN_PE4, 1, 5) +-#define PIN_PE4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PE4, 2, 4) +-#define PIN_PE4__TIOA3 PINMUX_PIN(PIN_PE4, 3, 3) +-#define PIN_PE4__I2SMCC1_DIN1 PINMUX_PIN(PIN_PE4, 4, 2) +-#define PIN_PE4__ISC_D8 PINMUX_PIN(PIN_PE4, 5, 2) +-#define PIN_PE4__G1_TXER PINMUX_PIN(PIN_PE4, 7, 1) +-#define PIN_PE5 133 +-#define PIN_PE5__GPIO PINMUX_PIN(PIN_PE5, 0, 0) +-#define PIN_PE5__PWMH1 PINMUX_PIN(PIN_PE5, 1, 5) +-#define PIN_PE5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PE5, 2, 4) +-#define PIN_PE5__TIOB3 PINMUX_PIN(PIN_PE5, 3, 3) +-#define PIN_PE5__I2SMCC1_DIN2 PINMUX_PIN(PIN_PE5, 4, 2) +-#define PIN_PE5__ISC_D9 PINMUX_PIN(PIN_PE5, 5, 2) +-#define PIN_PE5__G1_COL PINMUX_PIN(PIN_PE5, 7, 1) +-#define PIN_PE6 134 +-#define PIN_PE6__GPIO PINMUX_PIN(PIN_PE6, 0, 0) +-#define PIN_PE6__PWML2 PINMUX_PIN(PIN_PE6, 1, 5) +-#define PIN_PE6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PE6, 2, 4) +-#define PIN_PE6__TCLK3 PINMUX_PIN(PIN_PE6, 3, 3) +-#define PIN_PE6__I2SMCC1_DIN3 PINMUX_PIN(PIN_PE6, 4, 2) +-#define PIN_PE6__ISC_D10 PINMUX_PIN(PIN_PE6, 5, 2) +-#define PIN_PE6__G1_CRS PINMUX_PIN(PIN_PE6, 7, 1) +-#define PIN_PE7 135 +-#define PIN_PE7__GPIO PINMUX_PIN(PIN_PE7, 0, 0) +-#define PIN_PE7__PWMH2 PINMUX_PIN(PIN_PE7, 1, 5) +-#define PIN_PE7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PE7, 2, 4) +-#define PIN_PE7__TIOA4 PINMUX_PIN(PIN_PE7, 3, 3) +-#define PIN_PE7__ISC_D11 PINMUX_PIN(PIN_PE7, 5, 2) +-#define PIN_PE7__G1_TSUCOMP PINMUX_PIN(PIN_PE7, 7, 1) +diff --git a/scripts/dtc/include-prefixes/arm/sama7g5.dtsi b/scripts/dtc/include-prefixes/arm/sama7g5.dtsi +deleted file mode 100644 +index 6c58c151c6d9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sama7g5.dtsi ++++ /dev/null +@@ -1,567 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC +- * +- * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries +- * +- * Author: Eugen Hristev +- * Author: Claudiu Beznea +- * +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- model = "Microchip SAMA7G5 family SoC"; +- compatible = "microchip,sama7g5"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&gic>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x0>; +- }; +- }; +- +- clocks { +- slow_xtal: slow_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- }; +- +- main_xtal: main_xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- }; +- +- usb_clk: usb_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <48000000>; +- }; +- }; +- +- vddout25: fixed-regulator-vddout25 { +- compatible = "regulator-fixed"; +- +- regulator-name = "VDDOUT25"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-boot-on; +- status = "disabled"; +- }; +- +- ns_sram: sram@100000 { +- compatible = "mmio-sram"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x100000 0x20000>; +- ranges; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- securam: securam@e0000000 { +- compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram"; +- reg = <0xe0000000 0x4000>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xe0000000 0x4000>; +- no-memory-wc; +- status = "okay"; +- }; +- +- secumod: secumod@e0004000 { +- compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon"; +- reg = <0xe0004000 0x4000>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- sfrbu: sfr@e0008000 { +- compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; +- reg = <0xe0008000 0x20>; +- }; +- +- pioA: pinctrl@e0014000 { +- compatible = "microchip,sama7g5-pinctrl"; +- reg = <0xe0014000 0x800>; +- interrupts = , +- , +- , +- , +- ; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; +- }; +- +- pmc: pmc@e0018000 { +- compatible = "microchip,sama7g5-pmc", "syscon"; +- reg = <0xe0018000 0x200>; +- interrupts = ; +- #clock-cells = <2>; +- clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; +- clock-names = "td_slck", "md_slck", "main_xtal"; +- }; +- +- shdwc: shdwc@e001d010 { +- compatible = "microchip,sama7g5-shdwc", "syscon"; +- reg = <0xe001d010 0x10>; +- clocks = <&clk32k 0>; +- #address-cells = <1>; +- #size-cells = <0>; +- atmel,wakeup-rtc-timer; +- atmel,wakeup-rtt-timer; +- status = "disabled"; +- }; +- +- rtt: rtt@e001d020 { +- compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; +- reg = <0xe001d020 0x30>; +- interrupts = ; +- clocks = <&clk32k 0>; +- }; +- +- clk32k: clock-controller@e001d050 { +- compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc"; +- reg = <0xe001d050 0x4>; +- clocks = <&slow_xtal>; +- #clock-cells = <1>; +- }; +- +- gpbr: gpbr@e001d060 { +- compatible = "microchip,sama7g5-gpbr", "syscon"; +- reg = <0xe001d060 0x48>; +- }; +- +- ps_wdt: watchdog@e001d180 { +- compatible = "microchip,sama7g5-wdt"; +- reg = <0xe001d180 0x24>; +- interrupts = ; +- clocks = <&clk32k 0>; +- }; +- +- chipid@e0020000 { +- compatible = "microchip,sama7g5-chipid"; +- reg = <0xe0020000 0x8>; +- }; +- +- sdmmc0: mmc@e1204000 { +- compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; +- reg = <0xe1204000 0x4000>; +- interrupts = ; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>; +- clock-names = "hclock", "multclk"; +- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; +- assigned-clocks = <&pmc PMC_TYPE_GCK 80>; +- assigned-clock-rates = <200000000>; +- microchip,sdcal-inverted; +- status = "disabled"; +- }; +- +- sdmmc1: mmc@e1208000 { +- compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; +- reg = <0xe1208000 0x4000>; +- interrupts = ; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>; +- clock-names = "hclock", "multclk"; +- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; +- assigned-clocks = <&pmc PMC_TYPE_GCK 81>; +- assigned-clock-rates = <200000000>; +- microchip,sdcal-inverted; +- status = "disabled"; +- }; +- +- sdmmc2: mmc@e120c000 { +- compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; +- reg = <0xe120c000 0x4000>; +- interrupts = ; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>; +- clock-names = "hclock", "multclk"; +- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; +- assigned-clocks = <&pmc PMC_TYPE_GCK 82>; +- assigned-clock-rates = <200000000>; +- microchip,sdcal-inverted; +- status = "disabled"; +- }; +- +- pwm: pwm@e1604000 { +- compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; +- reg = <0xe1604000 0x4000>; +- interrupts = ; +- #pwm-cells = <3>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 77>; +- status = "disabled"; +- }; +- +- spdifrx: spdifrx@e1614000 { +- #sound-dai-cells = <0>; +- compatible = "microchip,sama7g5-spdifrx"; +- reg = <0xe1614000 0x4000>; +- interrupts = ; +- dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>; +- dma-names = "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>; +- clock-names = "pclk", "gclk"; +- status = "disabled"; +- }; +- +- spdiftx: spdiftx@e1618000 { +- #sound-dai-cells = <0>; +- compatible = "microchip,sama7g5-spdiftx"; +- reg = <0xe1618000 0x4000>; +- interrupts = ; +- dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>; +- dma-names = "tx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>; +- clock-names = "pclk", "gclk"; +- }; +- +- i2s0: i2s@e161c000 { +- compatible = "microchip,sama7g5-i2smcc"; +- #sound-dai-cells = <0>; +- reg = <0xe161c000 0x4000>; +- interrupts = ; +- dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; +- clock-names = "pclk", "gclk"; +- status = "disabled"; +- }; +- +- i2s1: i2s@e1620000 { +- compatible = "microchip,sama7g5-i2smcc"; +- #sound-dai-cells = <0>; +- reg = <0xe1620000 0x4000>; +- interrupts = ; +- dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>; +- dma-names = "tx", "rx"; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; +- clock-names = "pclk", "gclk"; +- status = "disabled"; +- }; +- +- pit64b0: timer@e1800000 { +- compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; +- reg = <0xe1800000 0x4000>; +- interrupts = ; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>; +- clock-names = "pclk", "gclk"; +- }; +- +- pit64b1: timer@e1804000 { +- compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; +- reg = <0xe1804000 0x4000>; +- interrupts = ; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>; +- clock-names = "pclk", "gclk"; +- }; +- +- flx0: flexcom@e1818000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xe1818000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xe1818000 0x800>; +- status = "disabled"; +- +- uart0: serial@200 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0x200 0x200>; +- interrupts = ; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; +- clock-names = "usart"; +- dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, +- <&dma1 AT91_XDMAC_DT_PERID(5)>; +- dma-names = "tx", "rx"; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +- }; +- }; +- +- flx1: flexcom@e181c000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xe181c000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xe181c000 0x800>; +- status = "disabled"; +- +- i2c1: i2c@600 { +- compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; +- reg = <0x600 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; +- atmel,fifo-size = <32>; +- dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, +- <&dma0 AT91_XDMAC_DT_PERID(8)>; +- dma-names = "rx", "tx"; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +- }; +- }; +- +- flx3: flexcom@e1824000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xe1824000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xe1824000 0x800>; +- status = "disabled"; +- +- uart3: serial@200 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0x200 0x200>; +- interrupts = ; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; +- clock-names = "usart"; +- dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>, +- <&dma1 AT91_XDMAC_DT_PERID(11)>; +- dma-names = "tx", "rx"; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +- }; +- }; +- +- trng: rng@e2010000 { +- compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng"; +- reg = <0xe2010000 0x100>; +- interrupts = ; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 97>; +- status = "disabled"; +- }; +- +- flx4: flexcom@e2018000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xe2018000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xe2018000 0x800>; +- status = "disabled"; +- +- uart4: serial@200 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0x200 0x200>; +- interrupts = ; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; +- clock-names = "usart"; +- dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, +- <&dma1 AT91_XDMAC_DT_PERID(13)>; +- dma-names = "tx", "rx"; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- atmel,fifo-size = <16>; +- status = "disabled"; +- }; +- }; +- +- flx7: flexcom@e2024000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xe2024000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xe2024000 0x800>; +- status = "disabled"; +- +- uart7: serial@200 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0x200 0x200>; +- interrupts = ; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; +- clock-names = "usart"; +- dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, +- <&dma1 AT91_XDMAC_DT_PERID(19)>; +- dma-names = "tx", "rx"; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- atmel,fifo-size = <16>; +- status = "disabled"; +- }; +- }; +- +- gmac0: ethernet@e2800000 { +- compatible = "microchip,sama7g5-gem"; +- reg = <0xe2800000 0x1000>; +- interrupts = ; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>; +- clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; +- assigned-clocks = <&pmc PMC_TYPE_GCK 51>; +- assigned-clock-rates = <125000000>; +- status = "disabled"; +- }; +- +- gmac1: ethernet@e2804000 { +- compatible = "microchip,sama7g5-emac"; +- reg = <0xe2804000 0x1000>; +- interrupts = ; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>; +- clock-names = "pclk", "hclk"; +- status = "disabled"; +- }; +- +- dma0: dma-controller@e2808000 { +- compatible = "microchip,sama7g5-dma"; +- reg = <0xe2808000 0x1000>; +- interrupts = ; +- #dma-cells = <1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; +- clock-names = "dma_clk"; +- status = "disabled"; +- }; +- +- dma1: dma-controller@e280c000 { +- compatible = "microchip,sama7g5-dma"; +- reg = <0xe280c000 0x1000>; +- interrupts = ; +- #dma-cells = <1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; +- clock-names = "dma_clk"; +- status = "disabled"; +- }; +- +- /* Place dma2 here despite it's address */ +- dma2: dma-controller@e1200000 { +- compatible = "microchip,sama7g5-dma"; +- reg = <0xe1200000 0x1000>; +- interrupts = ; +- #dma-cells = <1>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; +- clock-names = "dma_clk"; +- dma-requests = <0>; +- status = "disabled"; +- }; +- +- flx8: flexcom@e2818000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xe2818000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xe2818000 0x800>; +- status = "disabled"; +- +- i2c8: i2c@600 { +- compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; +- reg = <0x600 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; +- atmel,fifo-size = <32>; +- dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>, +- <&dma0 AT91_XDMAC_DT_PERID(22)>; +- dma-names = "rx", "tx"; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +- }; +- }; +- +- flx9: flexcom@e281c000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xe281c000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xe281c000 0x800>; +- status = "disabled"; +- +- i2c9: i2c@600 { +- compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; +- reg = <0x600 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; +- atmel,fifo-size = <32>; +- dmas = <&dma0 AT91_XDMAC_DT_PERID(23)>, +- <&dma0 AT91_XDMAC_DT_PERID(24)>; +- dma-names = "rx", "tx"; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +- }; +- }; +- +- flx11: flexcom@e2824000 { +- compatible = "atmel,sama5d2-flexcom"; +- reg = <0xe2824000 0x200>; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0xe2824000 0x800>; +- status = "disabled"; +- +- spi11: spi@400 { +- compatible = "atmel,at91rm9200-spi"; +- reg = <0x400 0x200>; +- interrupts = ; +- clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; +- clock-names = "spi_clk"; +- #address-cells = <1>; +- #size-cells = <0>; +- atmel,fifo-size = <32>; +- dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>, +- <&dma0 AT91_XDMAC_DT_PERID(28)>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- }; +- +- uddrc: uddrc@e3800000 { +- compatible = "microchip,sama7g5-uddrc"; +- reg = <0xe3800000 0x4000>; +- status = "okay"; +- }; +- +- ddr3phy: ddr3phy@e3804000 { +- compatible = "microchip,sama7g5-ddr3phy"; +- reg = <0xe3804000 0x1000>; +- status = "okay"; +- }; +- +- gic: interrupt-controller@e8c11000 { +- compatible = "arm,cortex-a7-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- interrupt-parent; +- reg = <0xe8c11000 0x1000>, +- <0xe8c12000 0x2000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sd5203.dts b/scripts/dtc/include-prefixes/arm/sd5203.dts +deleted file mode 100644 +index a61a078ea042..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sd5203.dts ++++ /dev/null +@@ -1,96 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2020 HiSilicon Limited. +- * +- * DTS file for Hisilicon SD5203 Board +- */ +- +-/dts-v1/; +- +-/ { +- model = "Hisilicon SD5203"; +- compatible = "H836ASDJ", "hisilicon,sd5203"; +- interrupt-parent = <&vic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- chosen { +- bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0 { +- device_type = "cpu"; +- compatible = "arm,arm926ej-s"; +- reg = <0x0>; +- }; +- }; +- +- memory@30000000 { +- device_type = "memory"; +- reg = <0x30000000 0x8000000>; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges; +- +- vic: interrupt-controller@10130000 { +- compatible = "snps,dw-apb-ictl"; +- reg = <0x10130000 0x1000>; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- refclk125mhz: refclk125mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- }; +- +- timer0: timer@16002000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x16002000 0x1000>; +- interrupts = <4>; +- clocks = <&refclk125mhz>; +- clock-names = "apb_pclk"; +- }; +- +- timer1: timer@16003000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x16003000 0x1000>; +- interrupts = <5>; +- clocks = <&refclk125mhz>; +- clock-names = "apb_pclk"; +- }; +- +- uart0: serial@1600d000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x1600d000 0x1000>; +- bus_id = "uart0"; +- clocks = <&refclk125mhz>; +- clock-names = "baudclk", "apb_pclk"; +- reg-shift = <2>; +- interrupts = <17>; +- }; +- +- uart1: serial@1600c000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x1600c000 0x1000>; +- clocks = <&refclk125mhz>; +- clock-names = "baudclk", "apb_pclk"; +- reg-shift = <2>; +- interrupts = <16>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sh73a0-kzm9g.dts b/scripts/dtc/include-prefixes/arm/sh73a0-kzm9g.dts +deleted file mode 100644 +index 5a8d92a061df..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sh73a0-kzm9g.dts ++++ /dev/null +@@ -1,403 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the KZM-A9-GT board +- * +- * Copyright (C) 2012 Horms Solutions Ltd. +- * +- * Based on sh73a0-kzm9g.dts +- * Copyright (C) 2012 Renesas Solutions Corp. +- */ +- +-/dts-v1/; +-#include "sh73a0.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "KZM-A9-GT"; +- compatible = "renesas,kzm9g", "renesas,sh73a0"; +- +- aliases { +- serial0 = &scifa4; +- }; +- +- cpus { +- cpu@0 { +- cpu0-supply = <&vdd_dvfs>; +- operating-points = <1196000 1315000>, /* kHz uV */ +- < 598000 1175000>, +- < 398667 1065000>; +- voltage-tolerance = <1>; /* 1% */ +- }; +- }; +- +- chosen { +- bootargs = "root=/dev/nfs ip=on ignore_loglevel rw"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x20000000>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vmmc_sdhi0: regulator-vmmc-sdhi0 { +- compatible = "regulator-fixed"; +- regulator-name = "SDHI0 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&pfc 15 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vmmc_sdhi2: regulator-vmmc-sdhi2 { +- compatible = "regulator-fixed"; +- regulator-name = "SDHI2 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&pfc 14 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led1 { +- gpios = <&pfc 20 GPIO_ACTIVE_LOW>; +- label = "LED1"; +- }; +- led2 { +- gpios = <&pfc 21 GPIO_ACTIVE_LOW>; +- label = "LED2"; +- }; +- led3 { +- gpios = <&pfc 22 GPIO_ACTIVE_LOW>; +- label = "LED3"; +- }; +- led4 { +- gpios = <&pfc 23 GPIO_ACTIVE_LOW>; +- label = "LED4"; +- }; +- }; +- +- keyboard { +- compatible = "gpio-keys"; +- +- back-key { +- gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW3"; +- }; +- +- right-key { +- gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW2-R"; +- }; +- +- left-key { +- gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW2-L"; +- }; +- +- enter-key { +- gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW2-P"; +- }; +- +- up-key { +- gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW2-U"; +- }; +- +- down-key { +- gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW2-D"; +- }; +- +- home-key { +- gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW1"; +- wakeup-source; +- }; +- +- wakeup-key { +- gpios = <&pfc 159 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "NMI"; +- wakeup-source; +- }; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "left_j"; +- simple-audio-card,cpu { +- sound-dai = <&sh_fsi2 0>; +- }; +- simple-audio-card,codec { +- sound-dai = <&ak4648>; +- bitclock-master; +- frame-master; +- system-clock-frequency = <11289600>; +- }; +- }; +-}; +- +-&bsc { +- ethernet@10000000 { +- compatible = "smsc,lan9220", "smsc,lan9115"; +- reg = <0x10000000 0x100>; +- phy-mode = "mii"; +- interrupt-parent = <&irqpin0>; +- interrupts = <3 IRQ_TYPE_EDGE_FALLING>; +- reg-io-width = <4>; +- smsc,irq-push-pull; +- smsc,save-mac-address; +- vddvario-supply = <®_1p8v>; +- vdd33a-supply = <®_3p3v>; +- }; +-}; +- +-&cmt1 { +- status = "okay"; +-}; +- +-&extal2_clk { +- clock-frequency = <48000000>; +-}; +- +-&i2c0 { +- status = "okay"; +- +- compass@c { +- compatible = "asahi-kasei,ak8975"; +- reg = <0x0c>; +- interrupt-parent = <&irqpin3>; +- interrupts = <4 IRQ_TYPE_EDGE_FALLING>; +- }; +- +- ak4648: codec@12 { +- compatible = "asahi-kasei,ak4648"; +- reg = <0x12>; +- #sound-dai-cells = <0>; +- }; +- +- accelerometer@1d { +- compatible = "adi,adxl345"; +- reg = <0x1d>; +- interrupt-parent = <&irqpin3>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, +- <3 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- rtc@32 { +- compatible = "ricoh,r2025sd"; +- reg = <0x32>; +- }; +- +- as3711@40 { +- compatible = "ams,as3711"; +- reg = <0x40>; +- +- regulators { +- vdd_dvfs: sd1 { +- regulator-name = "1.315V CPU"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- sd2 { +- regulator-name = "1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- sd4 { +- regulator-name = "1.215V"; +- regulator-min-microvolt = <1215000>; +- regulator-max-microvolt = <1235000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- ldo2 { +- regulator-name = "2.8V CPU"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- ldo3 { +- regulator-name = "3.0V CPU"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- ldo4 { +- regulator-name = "2.8V"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- ldo5 { +- regulator-name = "2.8V #2"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- ldo7 { +- regulator-name = "1.15V CPU"; +- regulator-min-microvolt = <1150000>; +- regulator-max-microvolt = <1150000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- ldo8 { +- regulator-name = "1.15V CPU #2"; +- regulator-min-microvolt = <1150000>; +- regulator-max-microvolt = <1150000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- touchscreen@55 { +- compatible = "sitronix,st1232"; +- reg = <0x55>; +- interrupt-parent = <&irqpin1>; +- interrupts = <0 IRQ_TYPE_EDGE_FALLING>; +- }; +-}; +- +-&i2c3 { +- pinctrl-0 = <&i2c3_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- pcf8575: gpio@20 { +- compatible = "nxp,pcf8575"; +- reg = <0x20>; +- interrupt-parent = <&irqpin2>; +- interrupts = <3 IRQ_TYPE_EDGE_FALLING>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +-}; +- +-&mmcif { +- pinctrl-0 = <&mmcif_pins>; +- pinctrl-names = "default"; +- +- bus-width = <8>; +- vmmc-supply = <®_1p8v>; +- status = "okay"; +-}; +- +-&pfc { +- i2c3_pins: i2c3 { +- groups = "i2c3_1"; +- function = "i2c3"; +- }; +- +- mmcif_pins: mmc { +- mux { +- groups = "mmc0_data8_0", "mmc0_ctrl_0"; +- function = "mmc0"; +- }; +- cfg { +- groups = "mmc0_data8_0"; +- pins = "PORT279"; +- bias-pull-up; +- }; +- }; +- +- scifa4_pins: scifa4 { +- groups = "scifa4_data", "scifa4_ctrl"; +- function = "scifa4"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; +- function = "sdhi0"; +- }; +- +- sdhi2_pins: sd2 { +- groups = "sdhi2_data4", "sdhi2_ctrl"; +- function = "sdhi2"; +- }; +- +- fsia_pins: sounda { +- groups = "fsia_mclk_in", "fsia_sclk_in", +- "fsia_data_in", "fsia_data_out"; +- function = "fsia"; +- }; +-}; +- +-&scifa4 { +- pinctrl-0 = <&scifa4_pins>; +- pinctrl-names = "default"; +- +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <&vmmc_sdhi0>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&sdhi2 { +- pinctrl-0 = <&sdhi2_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <&vmmc_sdhi2>; +- bus-width = <4>; +- broken-cd; +- status = "okay"; +-}; +- +-&sh_fsi2 { +- pinctrl-0 = <&fsia_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sh73a0.dtsi b/scripts/dtc/include-prefixes/arm/sh73a0.dtsi +deleted file mode 100644 +index 30c67acc4e35..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sh73a0.dtsi ++++ /dev/null +@@ -1,949 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC +- * +- * Copyright (C) 2012 Renesas Solutions Corp. +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,sh73a0"; +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- clock-frequency = <1196000000>; +- clocks = <&cpg_clocks SH73A0_CLK_Z>; +- power-domains = <&pd_a2sl>; +- next-level-cache = <&L2>; +- }; +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <1>; +- clock-frequency = <1196000000>; +- clocks = <&cpg_clocks SH73A0_CLK_Z>; +- power-domains = <&pd_a2sl>; +- next-level-cache = <&L2>; +- }; +- }; +- +- timer@f0000200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0xf0000200 0x100>; +- interrupts = ; +- clocks = <&periph_clk>; +- }; +- +- timer@f0000600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0xf0000600 0x20>; +- interrupts = ; +- clocks = <&periph_clk>; +- }; +- +- gic: interrupt-controller@f0001000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0xf0001000 0x1000>, +- <0xf0000100 0x100>; +- }; +- +- L2: cache-controller@f0100000 { +- compatible = "arm,pl310-cache"; +- reg = <0xf0100000 0x1000>; +- interrupts = ; +- power-domains = <&pd_a3sm>; +- arm,data-latency = <3 3 3>; +- arm,tag-latency = <2 2 2>; +- arm,shared-override; +- cache-unified; +- cache-level = <2>; +- }; +- +- sbsc2: memory-controller@fb400000 { +- compatible = "renesas,sbsc-sh73a0"; +- reg = <0xfb400000 0x400>; +- interrupts = , +- ; +- interrupt-names = "sec", "temp"; +- power-domains = <&pd_a4bc1>; +- }; +- +- sbsc1: memory-controller@fe400000 { +- compatible = "renesas,sbsc-sh73a0"; +- reg = <0xfe400000 0x400>; +- interrupts = , +- ; +- interrupt-names = "sec", "temp"; +- power-domains = <&pd_a4bc0>; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- cmt1: timer@e6138000 { +- compatible = "renesas,sh73a0-cmt1"; +- reg = <0xe6138000 0x200>; +- interrupts = ; +- clocks = <&mstp3_clks SH73A0_CLK_CMT1>; +- clock-names = "fck"; +- power-domains = <&pd_c5>; +- status = "disabled"; +- }; +- +- irqpin0: interrupt-controller@e6900000 { +- compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0xe6900000 4>, +- <0xe6900010 4>, +- <0xe6900020 1>, +- <0xe6900040 1>, +- <0xe6900060 1>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; +- power-domains = <&pd_a4s>; +- control-parent; +- }; +- +- irqpin1: interrupt-controller@e6900004 { +- compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0xe6900004 4>, +- <0xe6900014 4>, +- <0xe6900024 1>, +- <0xe6900044 1>, +- <0xe6900064 1>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; +- power-domains = <&pd_a4s>; +- control-parent; +- }; +- +- irqpin2: interrupt-controller@e6900008 { +- compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0xe6900008 4>, +- <0xe6900018 4>, +- <0xe6900028 1>, +- <0xe6900048 1>, +- <0xe6900068 1>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; +- power-domains = <&pd_a4s>; +- control-parent; +- }; +- +- irqpin3: interrupt-controller@e690000c { +- compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0xe690000c 4>, +- <0xe690001c 4>, +- <0xe690002c 1>, +- <0xe690004c 1>, +- <0xe690006c 1>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; +- power-domains = <&pd_a4s>; +- control-parent; +- }; +- +- i2c0: i2c@e6820000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; +- reg = <0xe6820000 0x425>; +- interrupts = , +- , +- , +- ; +- clocks = <&mstp1_clks SH73A0_CLK_IIC0>; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6822000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; +- reg = <0xe6822000 0x425>; +- interrupts = , +- , +- , +- ; +- clocks = <&mstp3_clks SH73A0_CLK_IIC1>; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6824000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; +- reg = <0xe6824000 0x425>; +- interrupts = , +- , +- , +- ; +- clocks = <&mstp0_clks SH73A0_CLK_IIC2>; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e6826000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; +- reg = <0xe6826000 0x425>; +- interrupts = , +- , +- , +- ; +- clocks = <&mstp4_clks SH73A0_CLK_IIC3>; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e6828000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; +- reg = <0xe6828000 0x425>; +- interrupts = , +- , +- , +- ; +- clocks = <&mstp4_clks SH73A0_CLK_IIC4>; +- power-domains = <&pd_c5>; +- status = "disabled"; +- }; +- +- mmcif: mmc@e6bd0000 { +- compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif"; +- reg = <0xe6bd0000 0x100>; +- interrupts = , +- ; +- clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>; +- power-domains = <&pd_a3sp>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e20000 { +- compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; +- reg = <0xe6e20000 0x0064>; +- interrupts = ; +- clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>; +- power-domains = <&pd_a3sp>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6e10000 { +- compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; +- reg = <0xe6e10000 0x0064>; +- interrupts = ; +- clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>; +- power-domains = <&pd_a3sp>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6e00000 { +- compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; +- reg = <0xe6e00000 0x0064>; +- interrupts = ; +- clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>; +- power-domains = <&pd_a3sp>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof3: spi@e6c90000 { +- compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; +- reg = <0xe6c90000 0x0064>; +- interrupts = ; +- clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>; +- power-domains = <&pd_a3sp>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-sh73a0"; +- reg = <0xee100000 0x100>; +- interrupts = , +- , +- ; +- clocks = <&mstp3_clks SH73A0_CLK_SDHI0>; +- power-domains = <&pd_a3sp>; +- cap-sd-highspeed; +- status = "disabled"; +- }; +- +- /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ +- sdhi1: mmc@ee120000 { +- compatible = "renesas,sdhi-sh73a0"; +- reg = <0xee120000 0x100>; +- interrupts = , +- ; +- clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; +- power-domains = <&pd_a3sp>; +- disable-wp; +- cap-sd-highspeed; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ee140000 { +- compatible = "renesas,sdhi-sh73a0"; +- reg = <0xee140000 0x100>; +- interrupts = , +- ; +- clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; +- power-domains = <&pd_a3sp>; +- disable-wp; +- cap-sd-highspeed; +- status = "disabled"; +- }; +- +- scifa0: serial@e6c40000 { +- compatible = "renesas,scifa-sh73a0", "renesas,scifa"; +- reg = <0xe6c40000 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifa1: serial@e6c50000 { +- compatible = "renesas,scifa-sh73a0", "renesas,scifa"; +- reg = <0xe6c50000 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifa2: serial@e6c60000 { +- compatible = "renesas,scifa-sh73a0", "renesas,scifa"; +- reg = <0xe6c60000 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifa3: serial@e6c70000 { +- compatible = "renesas,scifa-sh73a0", "renesas,scifa"; +- reg = <0xe6c70000 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifa4: serial@e6c80000 { +- compatible = "renesas,scifa-sh73a0", "renesas,scifa"; +- reg = <0xe6c80000 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifa5: serial@e6cb0000 { +- compatible = "renesas,scifa-sh73a0", "renesas,scifa"; +- reg = <0xe6cb0000 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifa6: serial@e6cc0000 { +- compatible = "renesas,scifa-sh73a0", "renesas,scifa"; +- reg = <0xe6cc0000 0x100>; +- interrupts = ; +- clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifa7: serial@e6cd0000 { +- compatible = "renesas,scifa-sh73a0", "renesas,scifa"; +- reg = <0xe6cd0000 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- scifb: serial@e6c30000 { +- compatible = "renesas,scifb-sh73a0", "renesas,scifb"; +- reg = <0xe6c30000 0x100>; +- interrupts = ; +- clocks = <&mstp2_clks SH73A0_CLK_SCIFB>; +- clock-names = "fck"; +- power-domains = <&pd_a3sp>; +- status = "disabled"; +- }; +- +- pfc: pinctrl@e6050000 { +- compatible = "renesas,pfc-sh73a0"; +- reg = <0xe6050000 0x8000>, +- <0xe605801c 0x1c>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = +- <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>, +- <&pfc 288 288 22>; +- interrupts-extended = +- <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, +- <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, +- <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, +- <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, +- <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, +- <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, +- <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, +- <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; +- power-domains = <&pd_c5>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile"; +- reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; +- +- pm-domains { +- pd_c5: c5 { +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- pd_c4: c4@0 { +- reg = <0>; +- #power-domain-cells = <0>; +- }; +- +- pd_d4: d4@1 { +- reg = <1>; +- #power-domain-cells = <0>; +- }; +- +- pd_a4bc0: a4bc0@4 { +- reg = <4>; +- #power-domain-cells = <0>; +- }; +- +- pd_a4bc1: a4bc1@5 { +- reg = <5>; +- #power-domain-cells = <0>; +- }; +- +- pd_a4lc0: a4lc0@6 { +- reg = <6>; +- #power-domain-cells = <0>; +- }; +- +- pd_a4lc1: a4lc1@7 { +- reg = <7>; +- #power-domain-cells = <0>; +- }; +- +- pd_a4mp: a4mp@8 { +- reg = <8>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- pd_a3mp: a3mp@9 { +- reg = <9>; +- #power-domain-cells = <0>; +- }; +- +- pd_a3vc: a3vc@10 { +- reg = <10>; +- #power-domain-cells = <0>; +- }; +- }; +- +- pd_a4rm: a4rm@12 { +- reg = <12>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- pd_a3r: a3r@13 { +- reg = <13>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- pd_a2rv: a2rv@14 { +- reg = <14>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- }; +- }; +- }; +- +- pd_a4s: a4s@16 { +- reg = <16>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- pd_a3sp: a3sp@17 { +- reg = <17>; +- #power-domain-cells = <0>; +- }; +- +- pd_a3sg: a3sg@18 { +- reg = <18>; +- #power-domain-cells = <0>; +- }; +- +- pd_a3sm: a3sm@19 { +- reg = <19>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- pd_a2sl: a2sl@20 { +- reg = <20>; +- #power-domain-cells = <0>; +- }; +- }; +- }; +- }; +- }; +- }; +- +- sh_fsi2: sound@ec230000 { +- #sound-dai-cells = <1>; +- compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2"; +- reg = <0xec230000 0x400>; +- interrupts = ; +- clocks = <&mstp3_clks SH73A0_CLK_FSI>; +- power-domains = <&pd_a4mp>; +- status = "disabled"; +- }; +- +- bsc: bus@fec10000 { +- compatible = "renesas,bsc-sh73a0", "renesas,bsc", +- "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x20000000>; +- reg = <0xfec10000 0x400>; +- interrupts = ; +- clocks = <&zb_clk>; +- power-domains = <&pd_a4s>; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* External root clocks */ +- extalr_clk: extalr { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- extal1_clk: extal1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +- extal2_clk: extal2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board. */ +- clock-frequency = <0>; +- }; +- extcki_clk: extcki { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value can be overridden by the board. */ +- clock-frequency = <0>; +- }; +- fsiack_clk: fsiack { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value can be overridden by the board. */ +- clock-frequency = <0>; +- }; +- fsibck_clk: fsibck { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value can be overridden by the board. */ +- clock-frequency = <0>; +- }; +- +- /* Special CPG clocks */ +- cpg_clocks: cpg_clocks@e6150000 { +- compatible = "renesas,sh73a0-cpg-clocks"; +- reg = <0xe6150000 0x10000>; +- clocks = <&extal1_clk>, <&extal2_clk>; +- #clock-cells = <1>; +- clock-output-names = "main", "pll0", "pll1", "pll2", +- "pll3", "dsi0phy", "dsi1phy", +- "zg", "m3", "b", "m1", "m2", +- "z", "zx", "hp"; +- }; +- +- /* Variable factor clocks (DIV6) */ +- vclk1_clk: vclk1@e6150008 { +- compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150008 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, +- <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, +- <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, +- <0>; +- #clock-cells = <0>; +- }; +- vclk2_clk: vclk2@e615000c { +- compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe615000c 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, +- <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, +- <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, +- <0>; +- #clock-cells = <0>; +- }; +- vclk3_clk: vclk3@e615001c { +- compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe615001c 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, +- <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, +- <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, +- <0>; +- #clock-cells = <0>; +- }; +- zb_clk: zb_clk@e6150010 { +- compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150010 4>; +- clocks = <&pll1_div2_clk>, <0>, +- <&cpg_clocks SH73A0_CLK_PLL2>, <0>; +- #clock-cells = <0>; +- clock-output-names = "zb"; +- }; +- flctl_clk: flctlck@e6150014 { +- compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150014 4>; +- clocks = <&pll1_div2_clk>, <0>, +- <&cpg_clocks SH73A0_CLK_PLL2>, <0>; +- #clock-cells = <0>; +- }; +- sdhi0_clk: sdhi0ck@e6150074 { +- compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150074 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, +- <&pll1_div13_clk>, <0>; +- #clock-cells = <0>; +- }; +- sdhi1_clk: sdhi1ck@e6150078 { +- compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150078 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, +- <&pll1_div13_clk>, <0>; +- #clock-cells = <0>; +- }; +- sdhi2_clk: sdhi2ck@e615007c { +- compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe615007c 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, +- <&pll1_div13_clk>, <0>; +- #clock-cells = <0>; +- }; +- fsia_clk: fsia@e6150018 { +- compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150018 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, +- <&fsiack_clk>, <&fsiack_clk>; +- #clock-cells = <0>; +- }; +- fsib_clk: fsib@e6150090 { +- compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150090 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, +- <&fsibck_clk>, <&fsibck_clk>; +- #clock-cells = <0>; +- }; +- sub_clk: sub@e6150080 { +- compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150080 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, +- <&extal2_clk>, <&extal2_clk>; +- #clock-cells = <0>; +- }; +- spua_clk: spua@e6150084 { +- compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150084 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, +- <&extal2_clk>, <&extal2_clk>; +- #clock-cells = <0>; +- }; +- spuv_clk: spuv@e6150094 { +- compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150094 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, +- <&extal2_clk>, <&extal2_clk>; +- #clock-cells = <0>; +- }; +- msu_clk: msu@e6150088 { +- compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150088 4>; +- clocks = <&pll1_div2_clk>, <0>, +- <&cpg_clocks SH73A0_CLK_PLL2>, <0>; +- #clock-cells = <0>; +- }; +- hsi_clk: hsi@e615008c { +- compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe615008c 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, +- <&pll1_div7_clk>, <0>; +- #clock-cells = <0>; +- }; +- mfg1_clk: mfg1@e6150098 { +- compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150098 4>; +- clocks = <&pll1_div2_clk>, <0>, +- <&cpg_clocks SH73A0_CLK_PLL2>, <0>; +- #clock-cells = <0>; +- }; +- mfg2_clk: mfg2@e615009c { +- compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe615009c 4>; +- clocks = <&pll1_div2_clk>, <0>, +- <&cpg_clocks SH73A0_CLK_PLL2>, <0>; +- #clock-cells = <0>; +- }; +- dsit_clk: dsit@e6150060 { +- compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150060 4>; +- clocks = <&pll1_div2_clk>, <0>, +- <&cpg_clocks SH73A0_CLK_PLL2>, <0>; +- #clock-cells = <0>; +- }; +- dsi0p_clk: dsi0pck@e6150064 { +- compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; +- reg = <0xe6150064 4>; +- clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, +- <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>, +- <&extcki_clk>, <0>, <0>, <0>; +- #clock-cells = <0>; +- }; +- +- /* Fixed factor clocks */ +- main_div2_clk: main_div2 { +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks SH73A0_CLK_MAIN>; +- #clock-cells = <0>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- pll1_div2_clk: pll1_div2 { +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks SH73A0_CLK_PLL1>; +- #clock-cells = <0>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- pll1_div7_clk: pll1_div7 { +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks SH73A0_CLK_PLL1>; +- #clock-cells = <0>; +- clock-div = <7>; +- clock-mult = <1>; +- }; +- pll1_div13_clk: pll1_div13 { +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks SH73A0_CLK_PLL1>; +- #clock-cells = <0>; +- clock-div = <13>; +- clock-mult = <1>; +- }; +- periph_clk: periph { +- compatible = "fixed-factor-clock"; +- clocks = <&cpg_clocks SH73A0_CLK_Z>; +- #clock-cells = <0>; +- clock-div = <4>; +- clock-mult = <1>; +- }; +- +- /* Gate clocks */ +- mstp0_clks: mstp0_clks@e6150130 { +- compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xe6150130 4>, <0xe6150030 4>; +- clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>; +- #clock-cells = <1>; +- clock-indices = < +- SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0 +- >; +- clock-output-names = +- "iic2", "msiof0"; +- }; +- mstp1_clks: mstp1_clks@e6150134 { +- compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xe6150134 4>, <0xe6150038 4>; +- clocks = <&cpg_clocks SH73A0_CLK_B>, +- <&cpg_clocks SH73A0_CLK_B>, +- <&cpg_clocks SH73A0_CLK_B>, +- <&cpg_clocks SH73A0_CLK_B>, +- <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>, +- <&cpg_clocks SH73A0_CLK_HP>, +- <&cpg_clocks SH73A0_CLK_ZG>, +- <&cpg_clocks SH73A0_CLK_B>; +- #clock-cells = <1>; +- clock-indices = < +- SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1 +- SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0 +- SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0 +- SH73A0_CLK_IIC0 SH73A0_CLK_SGX +- SH73A0_CLK_LCDC0 +- >; +- clock-output-names = +- "ceu1", "csi2_rx1", "ceu0", "csi2_rx0", +- "tmu0", "dsitx0", "iic0", "sgx", "lcdc0"; +- }; +- mstp2_clks: mstp2_clks@e6150138 { +- compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xe6150138 4>, <0xe6150040 4>; +- clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>, +- <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, +- <&sub_clk>, <&sub_clk>, <&sub_clk>, +- <&sub_clk>, <&sub_clk>, <&sub_clk>, +- <&sub_clk>, <&sub_clk>, <&sub_clk>; +- #clock-cells = <1>; +- clock-indices = < +- SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC +- SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3 +- SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5 +- SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2 +- SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1 +- SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3 +- SH73A0_CLK_SCIFA4 +- >; +- clock-output-names = +- "scifa7", "sy_dmac", "mp_dmac", "msiof3", +- "msiof1", "scifa5", "scifb", "msiof2", +- "scifa0", "scifa1", "scifa2", "scifa3", +- "scifa4"; +- }; +- mstp3_clks: mstp3_clks@e615013c { +- compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xe615013c 4>, <0xe6150048 4>; +- clocks = <&sub_clk>, <&extalr_clk>, +- <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, +- <&cpg_clocks SH73A0_CLK_HP>, +- <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>, +- <&sdhi0_clk>, <&sdhi1_clk>, +- <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>, +- <&main_div2_clk>, <&main_div2_clk>, +- <&main_div2_clk>, <&main_div2_clk>, +- <&main_div2_clk>; +- #clock-cells = <1>; +- clock-indices = < +- SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1 +- SH73A0_CLK_FSI SH73A0_CLK_IRDA +- SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL +- SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1 +- SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2 +- SH73A0_CLK_TPU0 SH73A0_CLK_TPU1 +- SH73A0_CLK_TPU2 SH73A0_CLK_TPU3 +- SH73A0_CLK_TPU4 +- >; +- clock-output-names = +- "scifa6", "cmt1", "fsi", "irda", "iic1", +- "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2", +- "tpu0", "tpu1", "tpu2", "tpu3", "tpu4"; +- }; +- mstp4_clks: mstp4_clks@e6150140 { +- compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xe6150140 4>, <0xe615004c 4>; +- clocks = <&cpg_clocks SH73A0_CLK_HP>, +- <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>; +- #clock-cells = <1>; +- clock-indices = < +- SH73A0_CLK_IIC3 SH73A0_CLK_IIC4 +- SH73A0_CLK_KEYSC +- >; +- clock-output-names = +- "iic3", "iic4", "keysc"; +- }; +- mstp5_clks: mstp5_clks@e6150144 { +- compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; +- reg = <0xe6150144 4>, <0xe615003c 4>; +- clocks = <&cpg_clocks SH73A0_CLK_HP>; +- #clock-cells = <1>; +- clock-indices = < +- SH73A0_CLK_INTCA0 +- >; +- clock-output-names = +- "intca0"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/socfpga.dtsi b/scripts/dtc/include-prefixes/arm/socfpga.dtsi +deleted file mode 100644 +index 0b021eef0b53..000000000000 +--- a/scripts/dtc/include-prefixes/arm/socfpga.dtsi ++++ /dev/null +@@ -1,978 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2012 Altera +- */ +- +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- timer0 = &timer0; +- timer1 = &timer1; +- timer2 = &timer2; +- timer3 = &timer3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "altr,socfpga-smp"; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <0>; +- next-level-cache = <&L2>; +- }; +- cpu1: cpu@1 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <1>; +- next-level-cache = <&L2>; +- }; +- }; +- +- pmu: pmu@ff111000 { +- compatible = "arm,cortex-a9-pmu"; +- interrupt-parent = <&intc>; +- interrupts = <0 176 4>, <0 177 4>; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- reg = <0xff111000 0x1000>, +- <0xff113000 0x1000>; +- }; +- +- intc: intc@fffed000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0xfffed000 0x1000>, +- <0xfffec100 0x100>; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- device_type = "soc"; +- interrupt-parent = <&intc>; +- ranges; +- +- amba { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- pdma: pdma@ffe01000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0xffe01000 0x1000>; +- interrupts = <0 104 4>, +- <0 105 4>, +- <0 106 4>, +- <0 107 4>, +- <0 108 4>, +- <0 109 4>, +- <0 110 4>, +- <0 111 4>; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- clocks = <&l4_main_clk>; +- clock-names = "apb_pclk"; +- resets = <&rst DMA_RESET>; +- reset-names = "dma"; +- }; +- }; +- +- base_fpga_region { +- compatible = "fpga-region"; +- fpga-mgr = <&fpgamgr0>; +- +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- }; +- +- can0: can@ffc00000 { +- compatible = "bosch,d_can"; +- reg = <0xffc00000 0x1000>; +- interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; +- clocks = <&can0_clk>; +- resets = <&rst CAN0_RESET>; +- status = "disabled"; +- }; +- +- can1: can@ffc01000 { +- compatible = "bosch,d_can"; +- reg = <0xffc01000 0x1000>; +- interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; +- clocks = <&can1_clk>; +- resets = <&rst CAN1_RESET>; +- status = "disabled"; +- }; +- +- clkmgr@ffd04000 { +- compatible = "altr,clk-mgr"; +- reg = <0xffd04000 0x1000>; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- osc1: osc1 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- }; +- +- osc2: osc2 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- }; +- +- f2s_periph_ref_clk: f2s_periph_ref_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- }; +- +- f2s_sdram_ref_clk: f2s_sdram_ref_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- }; +- +- main_pll: main_pll@40 { +- #address-cells = <1>; +- #size-cells = <0>; +- #clock-cells = <0>; +- compatible = "altr,socfpga-pll-clock"; +- clocks = <&osc1>; +- reg = <0x40>; +- +- mpuclk: mpuclk@48 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-perip-clk"; +- clocks = <&main_pll>; +- div-reg = <0xe0 0 9>; +- reg = <0x48>; +- }; +- +- mainclk: mainclk@4c { +- #clock-cells = <0>; +- compatible = "altr,socfpga-perip-clk"; +- clocks = <&main_pll>; +- div-reg = <0xe4 0 9>; +- reg = <0x4C>; +- }; +- +- dbg_base_clk: dbg_base_clk@50 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-perip-clk"; +- clocks = <&main_pll>, <&osc1>; +- div-reg = <0xe8 0 9>; +- reg = <0x50>; +- }; +- +- main_qspi_clk: main_qspi_clk@54 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-perip-clk"; +- clocks = <&main_pll>; +- reg = <0x54>; +- }; +- +- main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-perip-clk"; +- clocks = <&main_pll>; +- reg = <0x58>; +- }; +- +- cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c { +- #clock-cells = <0>; +- compatible = "altr,socfpga-perip-clk"; +- clocks = <&main_pll>; +- reg = <0x5C>; +- }; +- }; +- +- periph_pll: periph_pll@80 { +- #address-cells = <1>; +- #size-cells = <0>; +- #clock-cells = <0>; +- compatible = "altr,socfpga-pll-clock"; +- clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; +- reg = <0x80>; +- +- emac0_clk: emac0_clk@88 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-perip-clk"; +- clocks = <&periph_pll>; +- reg = <0x88>; +- }; +- +- emac1_clk: emac1_clk@8c { +- #clock-cells = <0>; +- compatible = "altr,socfpga-perip-clk"; +- clocks = <&periph_pll>; +- reg = <0x8C>; +- }; +- +- per_qspi_clk: per_qsi_clk@90 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-perip-clk"; +- clocks = <&periph_pll>; +- reg = <0x90>; +- }; +- +- per_nand_mmc_clk: per_nand_mmc_clk@94 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-perip-clk"; +- clocks = <&periph_pll>; +- reg = <0x94>; +- }; +- +- per_base_clk: per_base_clk@98 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-perip-clk"; +- clocks = <&periph_pll>; +- reg = <0x98>; +- }; +- +- h2f_usr1_clk: h2f_usr1_clk@9c { +- #clock-cells = <0>; +- compatible = "altr,socfpga-perip-clk"; +- clocks = <&periph_pll>; +- reg = <0x9C>; +- }; +- }; +- +- sdram_pll: sdram_pll@c0 { +- #address-cells = <1>; +- #size-cells = <0>; +- #clock-cells = <0>; +- compatible = "altr,socfpga-pll-clock"; +- clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; +- reg = <0xC0>; +- +- ddr_dqs_clk: ddr_dqs_clk@c8 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-perip-clk"; +- clocks = <&sdram_pll>; +- reg = <0xC8>; +- }; +- +- ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc { +- #clock-cells = <0>; +- compatible = "altr,socfpga-perip-clk"; +- clocks = <&sdram_pll>; +- reg = <0xCC>; +- }; +- +- ddr_dq_clk: ddr_dq_clk@d0 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-perip-clk"; +- clocks = <&sdram_pll>; +- reg = <0xD0>; +- }; +- +- h2f_usr2_clk: h2f_usr2_clk@d4 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-perip-clk"; +- clocks = <&sdram_pll>; +- reg = <0xD4>; +- }; +- }; +- +- mpu_periph_clk: mpu_periph_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-perip-clk"; +- clocks = <&mpuclk>; +- fixed-divider = <4>; +- }; +- +- mpu_l2_ram_clk: mpu_l2_ram_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-perip-clk"; +- clocks = <&mpuclk>; +- fixed-divider = <2>; +- }; +- +- l4_main_clk: l4_main_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&mainclk>; +- clk-gate = <0x60 0>; +- }; +- +- l3_main_clk: l3_main_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-perip-clk"; +- clocks = <&mainclk>; +- fixed-divider = <1>; +- }; +- +- l3_mp_clk: l3_mp_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&mainclk>; +- div-reg = <0x64 0 2>; +- clk-gate = <0x60 1>; +- }; +- +- l3_sp_clk: l3_sp_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&l3_mp_clk>; +- div-reg = <0x64 2 2>; +- }; +- +- l4_mp_clk: l4_mp_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&mainclk>, <&per_base_clk>; +- div-reg = <0x64 4 3>; +- clk-gate = <0x60 2>; +- }; +- +- l4_sp_clk: l4_sp_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&mainclk>, <&per_base_clk>; +- div-reg = <0x64 7 3>; +- clk-gate = <0x60 3>; +- }; +- +- dbg_at_clk: dbg_at_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&dbg_base_clk>; +- div-reg = <0x68 0 2>; +- clk-gate = <0x60 4>; +- }; +- +- dbg_clk: dbg_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&dbg_at_clk>; +- div-reg = <0x68 2 2>; +- clk-gate = <0x60 5>; +- }; +- +- dbg_trace_clk: dbg_trace_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&dbg_base_clk>; +- div-reg = <0x6C 0 3>; +- clk-gate = <0x60 6>; +- }; +- +- dbg_timer_clk: dbg_timer_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&dbg_base_clk>; +- clk-gate = <0x60 7>; +- }; +- +- cfg_clk: cfg_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&cfg_h2f_usr0_clk>; +- clk-gate = <0x60 8>; +- }; +- +- h2f_user0_clk: h2f_user0_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&cfg_h2f_usr0_clk>; +- clk-gate = <0x60 9>; +- }; +- +- emac_0_clk: emac_0_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&emac0_clk>; +- clk-gate = <0xa0 0>; +- }; +- +- emac_1_clk: emac_1_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&emac1_clk>; +- clk-gate = <0xa0 1>; +- }; +- +- usb_mp_clk: usb_mp_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&per_base_clk>; +- clk-gate = <0xa0 2>; +- div-reg = <0xa4 0 3>; +- }; +- +- spi_m_clk: spi_m_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&per_base_clk>; +- clk-gate = <0xa0 3>; +- div-reg = <0xa4 3 3>; +- }; +- +- can0_clk: can0_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&per_base_clk>; +- clk-gate = <0xa0 4>; +- div-reg = <0xa4 6 3>; +- }; +- +- can1_clk: can1_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&per_base_clk>; +- clk-gate = <0xa0 5>; +- div-reg = <0xa4 9 3>; +- }; +- +- gpio_db_clk: gpio_db_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&per_base_clk>; +- clk-gate = <0xa0 6>; +- div-reg = <0xa8 0 24>; +- }; +- +- h2f_user1_clk: h2f_user1_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&h2f_usr1_clk>; +- clk-gate = <0xa0 7>; +- }; +- +- sdmmc_clk: sdmmc_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; +- clk-gate = <0xa0 8>; +- clk-phase = <0 135>; +- }; +- +- sdmmc_clk_divided: sdmmc_clk_divided { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&sdmmc_clk>; +- clk-gate = <0xa0 8>; +- fixed-divider = <4>; +- }; +- +- nand_x_clk: nand_x_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; +- clk-gate = <0xa0 9>; +- }; +- +- nand_ecc_clk: nand_ecc_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&nand_x_clk>; +- clk-gate = <0xa0 9>; +- }; +- +- nand_clk: nand_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&nand_x_clk>; +- clk-gate = <0xa0 10>; +- fixed-divider = <4>; +- }; +- +- qspi_clk: qspi_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; +- clk-gate = <0xa0 11>; +- }; +- +- ddr_dqs_clk_gate: ddr_dqs_clk_gate { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&ddr_dqs_clk>; +- clk-gate = <0xd8 0>; +- }; +- +- ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&ddr_2x_dqs_clk>; +- clk-gate = <0xd8 1>; +- }; +- +- ddr_dq_clk_gate: ddr_dq_clk_gate { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&ddr_dq_clk>; +- clk-gate = <0xd8 2>; +- }; +- +- h2f_user2_clk: h2f_user2_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-gate-clk"; +- clocks = <&h2f_usr2_clk>; +- clk-gate = <0xd8 3>; +- }; +- +- }; +- }; +- +- fpga_bridge0: fpga_bridge@ff400000 { +- compatible = "altr,socfpga-lwhps2fpga-bridge"; +- reg = <0xff400000 0x100000>; +- resets = <&rst LWHPS2FPGA_RESET>; +- clocks = <&l4_main_clk>; +- status = "disabled"; +- }; +- +- fpga_bridge1: fpga_bridge@ff500000 { +- compatible = "altr,socfpga-hps2fpga-bridge"; +- reg = <0xff500000 0x10000>; +- resets = <&rst HPS2FPGA_RESET>; +- clocks = <&l4_main_clk>; +- status = "disabled"; +- }; +- +- fpga_bridge2: fpga-bridge@ff600000 { +- compatible = "altr,socfpga-fpga2hps-bridge"; +- reg = <0xff600000 0x100000>; +- resets = <&rst FPGA2HPS_RESET>; +- clocks = <&l4_main_clk>; +- status = "disabled"; +- }; +- +- fpga_bridge3: fpga-bridge@ffc25080 { +- compatible = "altr,socfpga-fpga2sdram-bridge"; +- reg = <0xffc25080 0x4>; +- status = "disabled"; +- }; +- +- fpgamgr0: fpgamgr@ff706000 { +- compatible = "altr,socfpga-fpga-mgr"; +- reg = <0xff706000 0x1000 +- 0xffb90000 0x4>; +- interrupts = <0 175 4>; +- }; +- +- gmac0: ethernet@ff700000 { +- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; +- altr,sysmgr-syscon = <&sysmgr 0x60 0>; +- reg = <0xff700000 0x2000>; +- interrupts = <0 115 4>; +- interrupt-names = "macirq"; +- mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ +- clocks = <&emac_0_clk>; +- clock-names = "stmmaceth"; +- resets = <&rst EMAC0_RESET>; +- reset-names = "stmmaceth"; +- snps,multicast-filter-bins = <256>; +- snps,perfect-filter-entries = <128>; +- tx-fifo-depth = <4096>; +- rx-fifo-depth = <4096>; +- status = "disabled"; +- }; +- +- gmac1: ethernet@ff702000 { +- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; +- altr,sysmgr-syscon = <&sysmgr 0x60 2>; +- reg = <0xff702000 0x2000>; +- interrupts = <0 120 4>; +- interrupt-names = "macirq"; +- mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ +- clocks = <&emac_1_clk>; +- clock-names = "stmmaceth"; +- resets = <&rst EMAC1_RESET>; +- reset-names = "stmmaceth"; +- snps,multicast-filter-bins = <256>; +- snps,perfect-filter-entries = <128>; +- tx-fifo-depth = <4096>; +- rx-fifo-depth = <4096>; +- status = "disabled"; +- }; +- +- gpio0: gpio@ff708000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dw-apb-gpio"; +- reg = <0xff708000 0x1000>; +- clocks = <&l4_mp_clk>; +- resets = <&rst GPIO0_RESET>; +- status = "disabled"; +- +- porta: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <29>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <0 164 4>; +- }; +- }; +- +- gpio1: gpio@ff709000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dw-apb-gpio"; +- reg = <0xff709000 0x1000>; +- clocks = <&l4_mp_clk>; +- resets = <&rst GPIO1_RESET>; +- status = "disabled"; +- +- portb: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <29>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <0 165 4>; +- }; +- }; +- +- gpio2: gpio@ff70a000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dw-apb-gpio"; +- reg = <0xff70a000 0x1000>; +- clocks = <&l4_mp_clk>; +- resets = <&rst GPIO2_RESET>; +- status = "disabled"; +- +- portc: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <27>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <0 166 4>; +- }; +- }; +- +- i2c0: i2c@ffc04000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xffc04000 0x1000>; +- resets = <&rst I2C0_RESET>; +- clocks = <&l4_sp_clk>; +- interrupts = <0 158 0x4>; +- status = "disabled"; +- }; +- +- i2c1: i2c@ffc05000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xffc05000 0x1000>; +- resets = <&rst I2C1_RESET>; +- clocks = <&l4_sp_clk>; +- interrupts = <0 159 0x4>; +- status = "disabled"; +- }; +- +- i2c2: i2c@ffc06000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xffc06000 0x1000>; +- resets = <&rst I2C2_RESET>; +- clocks = <&l4_sp_clk>; +- interrupts = <0 160 0x4>; +- status = "disabled"; +- }; +- +- i2c3: i2c@ffc07000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xffc07000 0x1000>; +- resets = <&rst I2C3_RESET>; +- clocks = <&l4_sp_clk>; +- interrupts = <0 161 0x4>; +- status = "disabled"; +- }; +- +- eccmgr: eccmgr { +- compatible = "altr,socfpga-ecc-manager"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- l2-ecc@ffd08140 { +- compatible = "altr,socfpga-l2-ecc"; +- reg = <0xffd08140 0x4>; +- interrupts = <0 36 1>, <0 37 1>; +- }; +- +- ocram-ecc@ffd08144 { +- compatible = "altr,socfpga-ocram-ecc"; +- reg = <0xffd08144 0x4>; +- iram = <&ocram>; +- interrupts = <0 178 1>, <0 179 1>; +- }; +- }; +- +- L2: cache-controller@fffef000 { +- compatible = "arm,pl310-cache"; +- reg = <0xfffef000 0x1000>; +- interrupts = <0 38 0x04>; +- cache-unified; +- cache-level = <2>; +- arm,tag-latency = <1 1 1>; +- arm,data-latency = <2 1 1>; +- prefetch-data = <1>; +- prefetch-instr = <1>; +- arm,shared-override; +- arm,double-linefill = <1>; +- arm,double-linefill-incr = <0>; +- arm,double-linefill-wrap = <1>; +- arm,prefetch-drop = <0>; +- arm,prefetch-offset = <7>; +- }; +- +- l3regs@0xff800000 { +- compatible = "altr,l3regs", "syscon"; +- reg = <0xff800000 0x1000>; +- }; +- +- mmc: dwmmc0@ff704000 { +- compatible = "altr,socfpga-dw-mshc"; +- reg = <0xff704000 0x1000>; +- interrupts = <0 139 4>; +- fifo-depth = <0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; +- clock-names = "biu", "ciu"; +- resets = <&rst SDMMC_RESET>; +- status = "disabled"; +- }; +- +- nand0: nand@ff900000 { +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- compatible = "altr,socfpga-denali-nand"; +- reg = <0xff900000 0x100000>, +- <0xffb80000 0x10000>; +- reg-names = "nand_data", "denali_reg"; +- interrupts = <0x0 0x90 0x4>; +- clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; +- clock-names = "nand", "nand_x", "ecc"; +- resets = <&rst NAND_RESET>; +- status = "disabled"; +- }; +- +- ocram: sram@ffff0000 { +- compatible = "mmio-sram"; +- reg = <0xffff0000 0x10000>; +- }; +- +- qspi: spi@ff705000 { +- compatible = "cdns,qspi-nor"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xff705000 0x1000>, +- <0xffa00000 0x1000>; +- interrupts = <0 151 4>; +- cdns,fifo-depth = <128>; +- cdns,fifo-width = <4>; +- cdns,trigger-address = <0x00000000>; +- clocks = <&qspi_clk>; +- resets = <&rst QSPI_RESET>; +- status = "disabled"; +- }; +- +- rst: rstmgr@ffd05000 { +- #reset-cells = <1>; +- compatible = "altr,rst-mgr"; +- reg = <0xffd05000 0x1000>; +- altr,modrst-offset = <0x10>; +- }; +- +- scu: snoop-control-unit@fffec000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0xfffec000 0x100>; +- }; +- +- sdr: sdr@ffc25000 { +- compatible = "altr,sdr-ctl", "syscon"; +- reg = <0xffc25000 0x1000>; +- resets = <&rst SDR_RESET>; +- }; +- +- sdramedac { +- compatible = "altr,sdram-edac"; +- altr,sdr-syscon = <&sdr>; +- interrupts = <0 39 4>; +- }; +- +- spi0: spi@fff00000 { +- compatible = "snps,dw-apb-ssi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xfff00000 0x1000>; +- interrupts = <0 154 4>; +- num-cs = <4>; +- clocks = <&spi_m_clk>; +- resets = <&rst SPIM0_RESET>; +- reset-names = "spi"; +- status = "disabled"; +- }; +- +- spi1: spi@fff01000 { +- compatible = "snps,dw-apb-ssi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xfff01000 0x1000>; +- interrupts = <0 155 4>; +- num-cs = <4>; +- clocks = <&spi_m_clk>; +- resets = <&rst SPIM1_RESET>; +- reset-names = "spi"; +- status = "disabled"; +- }; +- +- sysmgr: sysmgr@ffd08000 { +- compatible = "altr,sys-mgr", "syscon"; +- reg = <0xffd08000 0x4000>; +- }; +- +- /* Local timer */ +- timer@fffec600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0xfffec600 0x100>; +- interrupts = <1 13 0xf01>; +- clocks = <&mpu_periph_clk>; +- }; +- +- timer0: timer0@ffc08000 { +- compatible = "snps,dw-apb-timer"; +- interrupts = <0 167 4>; +- reg = <0xffc08000 0x1000>; +- clocks = <&l4_sp_clk>; +- clock-names = "timer"; +- resets = <&rst SPTIMER0_RESET>; +- reset-names = "timer"; +- }; +- +- timer1: timer1@ffc09000 { +- compatible = "snps,dw-apb-timer"; +- interrupts = <0 168 4>; +- reg = <0xffc09000 0x1000>; +- clocks = <&l4_sp_clk>; +- clock-names = "timer"; +- resets = <&rst SPTIMER1_RESET>; +- reset-names = "timer"; +- }; +- +- timer2: timer2@ffd00000 { +- compatible = "snps,dw-apb-timer"; +- interrupts = <0 169 4>; +- reg = <0xffd00000 0x1000>; +- clocks = <&osc1>; +- clock-names = "timer"; +- resets = <&rst OSC1TIMER0_RESET>; +- reset-names = "timer"; +- }; +- +- timer3: timer3@ffd01000 { +- compatible = "snps,dw-apb-timer"; +- interrupts = <0 170 4>; +- reg = <0xffd01000 0x1000>; +- clocks = <&osc1>; +- clock-names = "timer"; +- resets = <&rst OSC1TIMER1_RESET>; +- reset-names = "timer"; +- }; +- +- uart0: serial0@ffc02000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0xffc02000 0x1000>; +- interrupts = <0 162 4>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&l4_sp_clk>; +- dmas = <&pdma 28>, +- <&pdma 29>; +- dma-names = "tx", "rx"; +- resets = <&rst UART0_RESET>; +- }; +- +- uart1: serial1@ffc03000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0xffc03000 0x1000>; +- interrupts = <0 163 4>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&l4_sp_clk>; +- dmas = <&pdma 30>, +- <&pdma 31>; +- dma-names = "tx", "rx"; +- resets = <&rst UART1_RESET>; +- }; +- +- usbphy0: usbphy { +- #phy-cells = <0>; +- compatible = "usb-nop-xceiv"; +- status = "okay"; +- }; +- +- usb0: usb@ffb00000 { +- compatible = "snps,dwc2"; +- reg = <0xffb00000 0xffff>; +- interrupts = <0 125 4>; +- clocks = <&usb_mp_clk>; +- clock-names = "otg"; +- resets = <&rst USB0_RESET>; +- reset-names = "dwc2"; +- phys = <&usbphy0>; +- phy-names = "usb2-phy"; +- status = "disabled"; +- }; +- +- usb1: usb@ffb40000 { +- compatible = "snps,dwc2"; +- reg = <0xffb40000 0xffff>; +- interrupts = <0 128 4>; +- clocks = <&usb_mp_clk>; +- clock-names = "otg"; +- resets = <&rst USB1_RESET>; +- reset-names = "dwc2"; +- phys = <&usbphy0>; +- phy-names = "usb2-phy"; +- status = "disabled"; +- }; +- +- watchdog0: watchdog@ffd02000 { +- compatible = "snps,dw-wdt"; +- reg = <0xffd02000 0x1000>; +- interrupts = <0 171 4>; +- clocks = <&osc1>; +- resets = <&rst L4WD0_RESET>; +- status = "disabled"; +- }; +- +- watchdog1: watchdog@ffd03000 { +- compatible = "snps,dw-wdt"; +- reg = <0xffd03000 0x1000>; +- interrupts = <0 172 4>; +- clocks = <&osc1>; +- resets = <&rst L4WD1_RESET>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/socfpga_arria10.dtsi b/scripts/dtc/include-prefixes/arm/socfpga_arria10.dtsi +deleted file mode 100644 +index a574ea91d9d3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/socfpga_arria10.dtsi ++++ /dev/null +@@ -1,912 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright Altera Corporation (C) 2014. All rights reserved. +- */ +- +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "altr,socfpga-a10-smp"; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <0>; +- next-level-cache = <&L2>; +- }; +- cpu1: cpu@1 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <1>; +- next-level-cache = <&L2>; +- }; +- }; +- +- pmu: pmu@ff111000 { +- compatible = "arm,cortex-a9-pmu"; +- interrupt-parent = <&intc>; +- interrupts = <0 124 4>, <0 125 4>; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- reg = <0xff111000 0x1000>, +- <0xff113000 0x1000>; +- }; +- +- intc: intc@ffffd000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0xffffd000 0x1000>, +- <0xffffc100 0x100>; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- device_type = "soc"; +- interrupt-parent = <&intc>; +- ranges; +- +- amba { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- pdma: pdma@ffda1000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0xffda1000 0x1000>; +- interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>, +- <0 84 IRQ_TYPE_LEVEL_HIGH>, +- <0 85 IRQ_TYPE_LEVEL_HIGH>, +- <0 86 IRQ_TYPE_LEVEL_HIGH>, +- <0 87 IRQ_TYPE_LEVEL_HIGH>, +- <0 88 IRQ_TYPE_LEVEL_HIGH>, +- <0 89 IRQ_TYPE_LEVEL_HIGH>, +- <0 90 IRQ_TYPE_LEVEL_HIGH>, +- <0 91 IRQ_TYPE_LEVEL_HIGH>; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- clocks = <&l4_main_clk>; +- clock-names = "apb_pclk"; +- resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; +- reset-names = "dma", "dma-ocp"; +- }; +- }; +- +- base_fpga_region { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- +- compatible = "fpga-region"; +- fpga-mgr = <&fpga_mgr>; +- }; +- +- clkmgr@ffd04000 { +- compatible = "altr,clk-mgr"; +- reg = <0xffd04000 0x1000>; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- }; +- +- cb_intosc_ls_clk: cb_intosc_ls_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- }; +- +- f2s_free_clk: f2s_free_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- }; +- +- osc1: osc1 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- }; +- +- main_pll: main_pll@40 { +- #address-cells = <1>; +- #size-cells = <0>; +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-pll-clock"; +- clocks = <&osc1>, <&cb_intosc_ls_clk>, +- <&f2s_free_clk>; +- reg = <0x40>; +- +- main_mpu_base_clk: main_mpu_base_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&main_pll>; +- div-reg = <0x140 0 11>; +- }; +- +- main_noc_base_clk: main_noc_base_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&main_pll>; +- div-reg = <0x144 0 11>; +- }; +- +- main_emaca_clk: main_emaca_clk@68 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&main_pll>; +- reg = <0x68>; +- }; +- +- main_emacb_clk: main_emacb_clk@6c { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&main_pll>; +- reg = <0x6C>; +- }; +- +- main_emac_ptp_clk: main_emac_ptp_clk@70 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&main_pll>; +- reg = <0x70>; +- }; +- +- main_gpio_db_clk: main_gpio_db_clk@74 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&main_pll>; +- reg = <0x74>; +- }; +- +- main_sdmmc_clk: main_sdmmc_clk@78 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk" +-; +- clocks = <&main_pll>; +- reg = <0x78>; +- }; +- +- main_s2f_usr0_clk: main_s2f_usr0_clk@7c { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&main_pll>; +- reg = <0x7C>; +- }; +- +- main_s2f_usr1_clk: main_s2f_usr1_clk@80 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&main_pll>; +- reg = <0x80>; +- }; +- +- main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&main_pll>; +- reg = <0x84>; +- }; +- +- main_periph_ref_clk: main_periph_ref_clk@9c { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&main_pll>; +- reg = <0x9C>; +- }; +- }; +- +- periph_pll: periph_pll@c0 { +- #address-cells = <1>; +- #size-cells = <0>; +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-pll-clock"; +- clocks = <&osc1>, <&cb_intosc_ls_clk>, +- <&f2s_free_clk>, <&main_periph_ref_clk>; +- reg = <0xC0>; +- +- peri_mpu_base_clk: peri_mpu_base_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&periph_pll>; +- div-reg = <0x140 16 11>; +- }; +- +- peri_noc_base_clk: peri_noc_base_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&periph_pll>; +- div-reg = <0x144 16 11>; +- }; +- +- peri_emaca_clk: peri_emaca_clk@e8 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&periph_pll>; +- reg = <0xE8>; +- }; +- +- peri_emacb_clk: peri_emacb_clk@ec { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&periph_pll>; +- reg = <0xEC>; +- }; +- +- peri_emac_ptp_clk: peri_emac_ptp_clk@f0 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&periph_pll>; +- reg = <0xF0>; +- }; +- +- peri_gpio_db_clk: peri_gpio_db_clk@f4 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&periph_pll>; +- reg = <0xF4>; +- }; +- +- peri_sdmmc_clk: peri_sdmmc_clk@f8 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&periph_pll>; +- reg = <0xF8>; +- }; +- +- peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&periph_pll>; +- reg = <0xFC>; +- }; +- +- peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&periph_pll>; +- reg = <0x100>; +- }; +- +- peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&periph_pll>; +- reg = <0x104>; +- }; +- }; +- +- mpu_free_clk: mpu_free_clk@60 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>, +- <&osc1>, <&cb_intosc_hs_div2_clk>, +- <&f2s_free_clk>; +- reg = <0x60>; +- }; +- +- noc_free_clk: noc_free_clk@64 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>, +- <&osc1>, <&cb_intosc_hs_div2_clk>, +- <&f2s_free_clk>; +- reg = <0x64>; +- }; +- +- s2f_user1_free_clk: s2f_user1_free_clk@104 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>, +- <&osc1>, <&cb_intosc_hs_div2_clk>, +- <&f2s_free_clk>; +- reg = <0x104>; +- }; +- +- sdmmc_free_clk: sdmmc_free_clk@f8 { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>, +- <&osc1>, <&cb_intosc_hs_div2_clk>, +- <&f2s_free_clk>; +- fixed-divider = <4>; +- reg = <0xF8>; +- }; +- +- l4_sys_free_clk: l4_sys_free_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-perip-clk"; +- clocks = <&noc_free_clk>; +- fixed-divider = <4>; +- }; +- +- l4_main_clk: l4_main_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-gate-clk"; +- clocks = <&noc_free_clk>; +- div-reg = <0xA8 0 2>; +- clk-gate = <0x48 1>; +- }; +- +- l4_mp_clk: l4_mp_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-gate-clk"; +- clocks = <&noc_free_clk>; +- div-reg = <0xA8 8 2>; +- clk-gate = <0x48 2>; +- }; +- +- l4_sp_clk: l4_sp_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-gate-clk"; +- clocks = <&noc_free_clk>; +- div-reg = <0xA8 16 2>; +- clk-gate = <0x48 3>; +- }; +- +- mpu_periph_clk: mpu_periph_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-gate-clk"; +- clocks = <&mpu_free_clk>; +- fixed-divider = <4>; +- clk-gate = <0x48 0>; +- }; +- +- sdmmc_clk: sdmmc_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-gate-clk"; +- clocks = <&sdmmc_free_clk>; +- clk-gate = <0xC8 5>; +- clk-phase = <0 135>; +- }; +- +- qspi_clk: qspi_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-gate-clk"; +- clocks = <&l4_main_clk>; +- clk-gate = <0xC8 11>; +- }; +- +- nand_x_clk: nand_x_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-gate-clk"; +- clocks = <&l4_mp_clk>; +- clk-gate = <0xC8 10>; +- }; +- +- nand_ecc_clk: nand_ecc_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-gate-clk"; +- clocks = <&nand_x_clk>; +- clk-gate = <0xC8 10>; +- }; +- +- nand_clk: nand_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-gate-clk"; +- clocks = <&nand_x_clk>; +- fixed-divider = <4>; +- clk-gate = <0xC8 10>; +- }; +- +- spi_m_clk: spi_m_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-gate-clk"; +- clocks = <&l4_main_clk>; +- clk-gate = <0xC8 9>; +- }; +- +- usb_clk: usb_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-gate-clk"; +- clocks = <&l4_mp_clk>; +- clk-gate = <0xC8 8>; +- }; +- +- s2f_usr1_clk: s2f_usr1_clk { +- #clock-cells = <0>; +- compatible = "altr,socfpga-a10-gate-clk"; +- clocks = <&peri_s2f_usr1_clk>; +- clk-gate = <0xC8 6>; +- }; +- }; +- }; +- +- socfpga_axi_setup: stmmac-axi-config { +- snps,wr_osr_lmt = <0xf>; +- snps,rd_osr_lmt = <0xf>; +- snps,blen = <0 0 0 0 16 0 0>; +- }; +- +- gmac0: ethernet@ff800000 { +- compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; +- altr,sysmgr-syscon = <&sysmgr 0x44 0>; +- reg = <0xff800000 0x2000>; +- interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "macirq"; +- /* Filled in by bootloader */ +- mac-address = [00 00 00 00 00 00]; +- snps,multicast-filter-bins = <256>; +- snps,perfect-filter-entries = <128>; +- tx-fifo-depth = <4096>; +- rx-fifo-depth = <16384>; +- clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; +- clock-names = "stmmaceth", "ptp_ref"; +- resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; +- reset-names = "stmmaceth", "stmmaceth-ocp"; +- snps,axi-config = <&socfpga_axi_setup>; +- status = "disabled"; +- }; +- +- gmac1: ethernet@ff802000 { +- compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; +- altr,sysmgr-syscon = <&sysmgr 0x48 8>; +- reg = <0xff802000 0x2000>; +- interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "macirq"; +- /* Filled in by bootloader */ +- mac-address = [00 00 00 00 00 00]; +- snps,multicast-filter-bins = <256>; +- snps,perfect-filter-entries = <128>; +- tx-fifo-depth = <4096>; +- rx-fifo-depth = <16384>; +- clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; +- clock-names = "stmmaceth", "ptp_ref"; +- resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; +- reset-names = "stmmaceth", "stmmaceth-ocp"; +- snps,axi-config = <&socfpga_axi_setup>; +- status = "disabled"; +- }; +- +- gmac2: ethernet@ff804000 { +- compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; +- altr,sysmgr-syscon = <&sysmgr 0x4C 16>; +- reg = <0xff804000 0x2000>; +- interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "macirq"; +- /* Filled in by bootloader */ +- mac-address = [00 00 00 00 00 00]; +- snps,multicast-filter-bins = <256>; +- snps,perfect-filter-entries = <128>; +- tx-fifo-depth = <4096>; +- rx-fifo-depth = <16384>; +- clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; +- clock-names = "stmmaceth", "ptp_ref"; +- resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; +- reset-names = "stmmaceth", "stmmaceth-ocp"; +- snps,axi-config = <&socfpga_axi_setup>; +- status = "disabled"; +- }; +- +- gpio0: gpio@ffc02900 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dw-apb-gpio"; +- reg = <0xffc02900 0x100>; +- resets = <&rst GPIO0_RESET>; +- status = "disabled"; +- +- porta: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <29>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; +- }; +- }; +- +- gpio1: gpio@ffc02a00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dw-apb-gpio"; +- reg = <0xffc02a00 0x100>; +- resets = <&rst GPIO1_RESET>; +- status = "disabled"; +- +- portb: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <29>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; +- }; +- }; +- +- gpio2: gpio@ffc02b00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dw-apb-gpio"; +- reg = <0xffc02b00 0x100>; +- resets = <&rst GPIO2_RESET>; +- status = "disabled"; +- +- portc: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <27>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; +- }; +- }; +- +- fpga_mgr: fpga-mgr@ffd03000 { +- compatible = "altr,socfpga-a10-fpga-mgr"; +- reg = <0xffd03000 0x100 +- 0xffcfe400 0x20>; +- clocks = <&l4_mp_clk>; +- resets = <&rst FPGAMGR_RESET>; +- reset-names = "fpgamgr"; +- }; +- +- i2c0: i2c@ffc02200 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xffc02200 0x100>; +- interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&l4_sp_clk>; +- resets = <&rst I2C0_RESET>; +- status = "disabled"; +- }; +- +- i2c1: i2c@ffc02300 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xffc02300 0x100>; +- interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&l4_sp_clk>; +- resets = <&rst I2C1_RESET>; +- status = "disabled"; +- }; +- +- i2c2: i2c@ffc02400 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xffc02400 0x100>; +- interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&l4_sp_clk>; +- resets = <&rst I2C2_RESET>; +- status = "disabled"; +- }; +- +- i2c3: i2c@ffc02500 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xffc02500 0x100>; +- interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&l4_sp_clk>; +- resets = <&rst I2C3_RESET>; +- status = "disabled"; +- }; +- +- i2c4: i2c@ffc02600 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xffc02600 0x100>; +- interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&l4_sp_clk>; +- resets = <&rst I2C4_RESET>; +- status = "disabled"; +- }; +- +- spi0: spi@ffda4000 { +- compatible = "snps,dw-apb-ssi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xffda4000 0x100>; +- interrupts = <0 101 4>; +- num-cs = <4>; +- /*32bit_access;*/ +- clocks = <&spi_m_clk>; +- resets = <&rst SPIM0_RESET>; +- reset-names = "spi"; +- status = "disabled"; +- }; +- +- spi1: spi@ffda5000 { +- compatible = "snps,dw-apb-ssi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xffda5000 0x100>; +- interrupts = <0 102 4>; +- num-cs = <4>; +- /*32bit_access;*/ +- tx-dma-channel = <&pdma 16>; +- rx-dma-channel = <&pdma 17>; +- clocks = <&spi_m_clk>; +- resets = <&rst SPIM1_RESET>; +- reset-names = "spi"; +- status = "disabled"; +- }; +- +- sdr: sdr@ffcfb100 { +- compatible = "altr,sdr-ctl", "syscon"; +- reg = <0xffcfb100 0x80>; +- }; +- +- L2: cache-controller@fffff000 { +- compatible = "arm,pl310-cache"; +- reg = <0xfffff000 0x1000>; +- interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; +- cache-unified; +- cache-level = <2>; +- prefetch-data = <1>; +- prefetch-instr = <1>; +- arm,shared-override; +- }; +- +- mmc: dwmmc0@ff808000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "altr,socfpga-dw-mshc"; +- reg = <0xff808000 0x1000>; +- interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; +- fifo-depth = <0x400>; +- clocks = <&l4_mp_clk>, <&sdmmc_clk>; +- clock-names = "biu", "ciu"; +- resets = <&rst SDMMC_RESET>; +- status = "disabled"; +- }; +- +- nand: nand@ffb90000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "altr,socfpga-denali-nand"; +- reg = <0xffb90000 0x72000>, +- <0xffb80000 0x10000>; +- reg-names = "nand_data", "denali_reg"; +- interrupts = <0 99 4>; +- clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; +- clock-names = "nand", "nand_x", "ecc"; +- resets = <&rst NAND_RESET>; +- status = "disabled"; +- }; +- +- ocram: sram@ffe00000 { +- compatible = "mmio-sram"; +- reg = <0xffe00000 0x40000>; +- }; +- +- eccmgr: eccmgr { +- compatible = "altr,socfpga-a10-ecc-manager"; +- altr,sysmgr-syscon = <&sysmgr>; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ranges; +- +- sdramedac { +- compatible = "altr,sdram-edac-a10"; +- altr,sdr-syscon = <&sdr>; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, +- <49 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- l2-ecc@ffd06010 { +- compatible = "altr,socfpga-a10-l2-ecc"; +- reg = <0xffd06010 0x4>; +- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, +- <32 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- ocram-ecc@ff8c3000 { +- compatible = "altr,socfpga-a10-ocram-ecc"; +- reg = <0xff8c3000 0x400>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, +- <33 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- emac0-rx-ecc@ff8c0800 { +- compatible = "altr,socfpga-eth-mac-ecc"; +- reg = <0xff8c0800 0x400>; +- altr,ecc-parent = <&gmac0>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, +- <36 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- emac0-tx-ecc@ff8c0c00 { +- compatible = "altr,socfpga-eth-mac-ecc"; +- reg = <0xff8c0c00 0x400>; +- altr,ecc-parent = <&gmac0>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, +- <37 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- dma-ecc@ff8c8000 { +- compatible = "altr,socfpga-dma-ecc"; +- reg = <0xff8c8000 0x400>; +- altr,ecc-parent = <&pdma>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, +- <42 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- usb0-ecc@ff8c8800 { +- compatible = "altr,socfpga-usb-ecc"; +- reg = <0xff8c8800 0x400>; +- altr,ecc-parent = <&usb0>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, +- <34 IRQ_TYPE_LEVEL_HIGH>; +- }; +- }; +- +- qspi: spi@ff809000 { +- compatible = "cdns,qspi-nor"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xff809000 0x100>, +- <0xffa00000 0x100000>; +- interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; +- cdns,fifo-depth = <128>; +- cdns,fifo-width = <4>; +- cdns,trigger-address = <0x00000000>; +- clocks = <&qspi_clk>; +- resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>; +- reset-names = "qspi", "qspi-ocp"; +- status = "disabled"; +- }; +- +- rst: rstmgr@ffd05000 { +- #reset-cells = <1>; +- compatible = "altr,rst-mgr"; +- reg = <0xffd05000 0x100>; +- altr,modrst-offset = <0x20>; +- }; +- +- scu: snoop-control-unit@ffffc000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0xffffc000 0x100>; +- }; +- +- sysmgr: sysmgr@ffd06000 { +- compatible = "altr,sys-mgr", "syscon"; +- reg = <0xffd06000 0x300>; +- cpu1-start-addr = <0xffd06230>; +- }; +- +- /* Local timer */ +- timer@ffffc600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0xffffc600 0x100>; +- interrupts = <1 13 0xf01>; +- clocks = <&mpu_periph_clk>; +- }; +- +- timer0: timer0@ffc02700 { +- compatible = "snps,dw-apb-timer"; +- interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; +- reg = <0xffc02700 0x100>; +- clocks = <&l4_sp_clk>; +- clock-names = "timer"; +- resets = <&rst SPTIMER0_RESET>; +- reset-names = "timer"; +- }; +- +- timer1: timer1@ffc02800 { +- compatible = "snps,dw-apb-timer"; +- interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>; +- reg = <0xffc02800 0x100>; +- clocks = <&l4_sp_clk>; +- clock-names = "timer"; +- resets = <&rst SPTIMER1_RESET>; +- reset-names = "timer"; +- }; +- +- timer2: timer2@ffd00000 { +- compatible = "snps,dw-apb-timer"; +- interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>; +- reg = <0xffd00000 0x100>; +- clocks = <&l4_sys_free_clk>; +- clock-names = "timer"; +- resets = <&rst L4SYSTIMER0_RESET>; +- reset-names = "timer"; +- }; +- +- timer3: timer3@ffd00100 { +- compatible = "snps,dw-apb-timer"; +- interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; +- reg = <0xffd00100 0x100>; +- clocks = <&l4_sys_free_clk>; +- clock-names = "timer"; +- resets = <&rst L4SYSTIMER1_RESET>; +- reset-names = "timer"; +- }; +- +- uart0: serial0@ffc02000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0xffc02000 0x100>; +- interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&l4_sp_clk>; +- resets = <&rst UART0_RESET>; +- status = "disabled"; +- }; +- +- uart1: serial1@ffc02100 { +- compatible = "snps,dw-apb-uart"; +- reg = <0xffc02100 0x100>; +- interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&l4_sp_clk>; +- resets = <&rst UART1_RESET>; +- status = "disabled"; +- }; +- +- usbphy0: usbphy { +- #phy-cells = <0>; +- compatible = "usb-nop-xceiv"; +- status = "okay"; +- }; +- +- usb0: usb@ffb00000 { +- compatible = "snps,dwc2"; +- reg = <0xffb00000 0xffff>; +- interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&usb_clk>; +- clock-names = "otg"; +- resets = <&rst USB0_RESET>; +- reset-names = "dwc2"; +- phys = <&usbphy0>; +- phy-names = "usb2-phy"; +- status = "disabled"; +- }; +- +- usb1: usb@ffb40000 { +- compatible = "snps,dwc2"; +- reg = <0xffb40000 0xffff>; +- interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&usb_clk>; +- clock-names = "otg"; +- resets = <&rst USB1_RESET>; +- reset-names = "dwc2"; +- phys = <&usbphy0>; +- phy-names = "usb2-phy"; +- status = "disabled"; +- }; +- +- watchdog0: watchdog@ffd00200 { +- compatible = "snps,dw-wdt"; +- reg = <0xffd00200 0x100>; +- interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&l4_sys_free_clk>; +- resets = <&rst L4WD0_RESET>; +- status = "disabled"; +- }; +- +- watchdog1: watchdog@ffd00300 { +- compatible = "snps,dw-wdt"; +- reg = <0xffd00300 0x100>; +- interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&l4_sys_free_clk>; +- resets = <&rst L4WD1_RESET>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/socfpga_arria10_socdk.dtsi b/scripts/dtc/include-prefixes/arm/socfpga_arria10_socdk.dtsi +deleted file mode 100644 +index 7edebe20e859..000000000000 +--- a/scripts/dtc/include-prefixes/arm/socfpga_arria10_socdk.dtsi ++++ /dev/null +@@ -1,183 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2015 Altera Corporation +- */ +-#include "socfpga_arria10.dtsi" +- +-/ { +- model = "Altera SOCFPGA Arria 10"; +- compatible = "altr,socfpga-arria10", "altr,socfpga"; +- +- aliases { +- ethernet0 = &gmac0; +- serial0 = &uart1; +- }; +- +- chosen { +- bootargs = "earlyprintk"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- name = "memory"; +- device_type = "memory"; +- reg = <0x0 0x40000000>; /* 1GB */ +- }; +- +- a10leds { +- compatible = "gpio-leds"; +- +- a10sr_led0 { +- label = "a10sr-led0"; +- gpios = <&a10sr_gpio 0 1>; +- }; +- +- a10sr_led1 { +- label = "a10sr-led1"; +- gpios = <&a10sr_gpio 1 1>; +- }; +- +- a10sr_led2 { +- label = "a10sr-led2"; +- gpios = <&a10sr_gpio 2 1>; +- }; +- +- a10sr_led3 { +- label = "a10sr-led3"; +- gpios = <&a10sr_gpio 3 1>; +- }; +- }; +- +- ref_033v: 033-v-ref { +- compatible = "regulator-fixed"; +- regulator-name = "0.33V"; +- regulator-min-microvolt = <330000>; +- regulator-max-microvolt = <330000>; +- }; +- +- soc { +- clkmgr@ffd04000 { +- clocks { +- osc1 { +- clock-frequency = <25000000>; +- }; +- }; +- }; +- }; +-}; +- +-&gmac0 { +- phy-mode = "rgmii"; +- phy-addr = <0xffffffff>; /* probe for phy addr */ +- +- /* +- * These skews assume the user's FPGA design is adding 600ps of delay +- * for TX_CLK on Arria 10. +- * +- * All skews are offset since hardware skew values for the ksz9031 +- * range from a negative skew to a positive skew. +- * See the micrel-ksz90x1.txt Documentation file for details. +- */ +- txd0-skew-ps = <0>; /* -420ps */ +- txd1-skew-ps = <0>; /* -420ps */ +- txd2-skew-ps = <0>; /* -420ps */ +- txd3-skew-ps = <0>; /* -420ps */ +- rxd0-skew-ps = <420>; /* 0ps */ +- rxd1-skew-ps = <420>; /* 0ps */ +- rxd2-skew-ps = <420>; /* 0ps */ +- rxd3-skew-ps = <420>; /* 0ps */ +- txen-skew-ps = <0>; /* -420ps */ +- txc-skew-ps = <1860>; /* 960ps */ +- rxdv-skew-ps = <420>; /* 0ps */ +- rxc-skew-ps = <1680>; /* 780ps */ +- max-frame-size = <3800>; +- status = "okay"; +-}; +- +-&gpio1 { +- status = "okay"; +-}; +- +-&spi1 { +- status = "okay"; +- +- resource-manager@0 { +- compatible = "altr,a10sr"; +- reg = <0>; +- spi-max-frequency = <100000>; +- /* low-level active IRQ at GPIO1_5 */ +- interrupt-parent = <&portb>; +- interrupts = <5 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- a10sr_gpio: gpio-controller { +- compatible = "altr,a10sr-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- a10sr_rst: reset-controller { +- compatible = "altr,a10sr-reset"; +- #reset-cells = <1>; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- /* +- * adjust the falling times to decrease the i2c frequency to 50Khz +- * because the LCD module does not work at the standard 100Khz +- */ +- clock-frequency = <100000>; +- i2c-sda-falling-time-ns = <6000>; +- i2c-scl-falling-time-ns = <6000>; +- +- adc@14 { +- compatible = "lltc,ltc2497"; +- reg = <0x14>; +- vref-supply = <&ref_033v>; +- }; +- +- adc@16 { +- compatible = "lltc,ltc2497"; +- reg = <0x16>; +- vref-supply = <&ref_033v>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c32"; +- reg = <0x51>; +- pagesize = <32>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +- +- ltc@5c { +- compatible = "ltc2977"; +- reg = <0x5c>; +- }; +- +- temp@4c { +- compatible = "maxim,max1619"; +- reg = <0x4c>; +- }; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- disable-over-current; +-}; +- +-&watchdog1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/socfpga_arria10_socdk_nand.dts b/scripts/dtc/include-prefixes/arm/socfpga_arria10_socdk_nand.dts +deleted file mode 100644 +index 9aa897b79544..000000000000 +--- a/scripts/dtc/include-prefixes/arm/socfpga_arria10_socdk_nand.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2015 Altera Corporation. All rights reserved. +- */ +- +-/dts-v1/; +-#include "socfpga_arria10_socdk.dtsi" +- +-&nand { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "Boot and fpga data"; +- reg = <0x0 0x02000000>; +- }; +- partition@1c00000 { +- label = "Root Filesystem - JFFS2"; +- reg = <0x02000000 0x06000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/socfpga_arria10_socdk_qspi.dts b/scripts/dtc/include-prefixes/arm/socfpga_arria10_socdk_qspi.dts +deleted file mode 100644 +index 2a745522404d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/socfpga_arria10_socdk_qspi.dts ++++ /dev/null +@@ -1,38 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2016 Intel. All rights reserved. +- */ +- +-/dts-v1/; +-#include "socfpga_arria10_socdk.dtsi" +- +-&qspi { +- status = "okay"; +- +- flash0: n25q00@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,mt25qu02g", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <100000000>; +- +- m25p,fast-read; +- cdns,page-size = <256>; +- cdns,block-size = <16>; +- cdns,read-delay = <3>; +- cdns,tshsl-ns = <50>; +- cdns,tsd2d-ns = <50>; +- cdns,tchsh-ns = <4>; +- cdns,tslch-ns = <4>; +- +- partition@qspi-boot { +- label = "Boot and fpga data"; +- reg = <0x0 0x2720000>; +- }; +- +- partition@qspi-rootfs { +- label = "Root Filesystem - JFFS2"; +- reg = <0x2720000 0x58E0000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/socfpga_arria10_socdk_sdmmc.dts b/scripts/dtc/include-prefixes/arm/socfpga_arria10_socdk_sdmmc.dts +deleted file mode 100644 +index 64dc0799f3d7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/socfpga_arria10_socdk_sdmmc.dts ++++ /dev/null +@@ -1,27 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2014-2015 Altera Corporation +- */ +- +-/dts-v1/; +-#include "socfpga_arria10_socdk.dtsi" +- +-&mmc { +- status = "okay"; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- broken-cd; +- bus-width = <4>; +-}; +- +-&eccmgr { +- sdmmca-ecc@ff8c2c00 { +- compatible = "altr,socfpga-sdmmc-ecc"; +- reg = <0xff8c2c00 0x400>; +- altr,ecc-parent = <&mmc>; +- interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, +- <47 IRQ_TYPE_LEVEL_HIGH>, +- <16 IRQ_TYPE_LEVEL_HIGH>, +- <48 IRQ_TYPE_LEVEL_HIGH>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/socfpga_arria5.dtsi b/scripts/dtc/include-prefixes/arm/socfpga_arria5.dtsi +deleted file mode 100644 +index 22dbf07afcff..000000000000 +--- a/scripts/dtc/include-prefixes/arm/socfpga_arria5.dtsi ++++ /dev/null +@@ -1,36 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2013 Altera Corporation +- */ +- +-/dts-v1/; +-/* First 4KB has trampoline code for secondary cores. */ +-/memreserve/ 0x00000000 0x0001000; +-#include "socfpga.dtsi" +- +-/ { +- soc { +- clkmgr@ffd04000 { +- clocks { +- osc1 { +- clock-frequency = <25000000>; +- }; +- }; +- }; +- +- mmc0: dwmmc0@ff704000 { +- broken-cd; +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- }; +- +- sysmgr@ffd08000 { +- cpu1-start-addr = <0xffd080c4>; +- }; +- }; +-}; +- +-&watchdog0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/socfpga_arria5_socdk.dts b/scripts/dtc/include-prefixes/arm/socfpga_arria5_socdk.dts +deleted file mode 100644 +index 1b02d46496a8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/socfpga_arria5_socdk.dts ++++ /dev/null +@@ -1,151 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2013 Altera Corporation +- */ +- +-#include "socfpga_arria5.dtsi" +- +-/ { +- model = "Altera SOCFPGA Arria V SoC Development Kit"; +- compatible = "altr,socfpga-arria5", "altr,socfpga"; +- +- chosen { +- bootargs = "earlyprintk"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- name = "memory"; +- device_type = "memory"; +- reg = <0x0 0x40000000>; /* 1GB */ +- }; +- +- aliases { +- /* this allow the ethaddr uboot environmnet variable contents +- * to be added to the gmac1 device tree blob. +- */ +- ethernet0 = &gmac1; +- }; +- +- leds { +- compatible = "gpio-leds"; +- hps0 { +- label = "hps_led0"; +- gpios = <&porta 0 1>; +- }; +- +- hps1 { +- label = "hps_led1"; +- gpios = <&portb 11 1>; +- }; +- +- hps2 { +- label = "hps_led2"; +- gpios = <&porta 17 1>; +- }; +- +- hps3 { +- label = "hps_led3"; +- gpios = <&porta 18 1>; +- }; +- }; +- +- regulator_3_3v: 3-3-v-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&gmac1 { +- status = "okay"; +- phy-mode = "rgmii"; +- +- rxd0-skew-ps = <0>; +- rxd1-skew-ps = <0>; +- rxd2-skew-ps = <0>; +- rxd3-skew-ps = <0>; +- txen-skew-ps = <0>; +- txc-skew-ps = <2600>; +- rxdv-skew-ps = <0>; +- rxc-skew-ps = <2000>; +-}; +- +-&gpio0 { +- status = "okay"; +-}; +- +-&gpio1 { +- status = "okay"; +-}; +- +-&gpio2 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <100000>; +- +- /* +- * adjust the falling times to decrease the i2c frequency to 50Khz +- * because the LCD module does not work at the standard 100Khz +- */ +- i2c-sda-falling-time-ns = <5000>; +- i2c-scl-falling-time-ns = <5000>; +- +- eeprom@51 { +- compatible = "atmel,24c32"; +- reg = <0x51>; +- pagesize = <32>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®ulator_3_3v>; +- vqmmc-supply = <®ulator_3_3v>; +- status = "okay"; +-}; +- +-&qspi { +- status = "okay"; +- +- flash: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q256a", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <100000000>; +- +- m25p,fast-read; +- cdns,page-size = <256>; +- cdns,block-size = <16>; +- cdns,read-delay = <4>; +- cdns,tshsl-ns = <50>; +- cdns,tsd2d-ns = <50>; +- cdns,tchsh-ns = <4>; +- cdns,tslch-ns = <4>; +- +- partition@qspi-boot { +- /* 8MB for raw data. */ +- label = "Flash 0 Raw Data"; +- reg = <0x0 0x800000>; +- }; +- +- partition@qspi-rootfs { +- /* 120MB for jffs2 data. */ +- label = "Flash 0 jffs2 Filesystem"; +- reg = <0x800000 0x7800000>; +- }; +- }; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5.dtsi b/scripts/dtc/include-prefixes/arm/socfpga_cyclone5.dtsi +deleted file mode 100644 +index 319a71e41ea4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5.dtsi ++++ /dev/null +@@ -1,36 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2012 Altera Corporation +- */ +- +-/dts-v1/; +-/* First 4KB has trampoline code for secondary cores. */ +-/memreserve/ 0x00000000 0x0001000; +-#include "socfpga.dtsi" +- +-/ { +- soc { +- clkmgr@ffd04000 { +- clocks { +- osc1 { +- clock-frequency = <25000000>; +- }; +- }; +- }; +- +- mmc0: dwmmc0@ff704000 { +- broken-cd; +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- }; +- +- sysmgr@ffd08000 { +- cpu1-start-addr = <0xffd080c4>; +- }; +- }; +-}; +- +-&watchdog0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_chameleon96.dts b/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_chameleon96.dts +deleted file mode 100644 +index f6561766d83f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_chameleon96.dts ++++ /dev/null +@@ -1,130 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Device Tree file for the Chameleon96 +- * +- * Copyright (c) 2018 Manivannan Sadhasivam +- */ +- +-#include +- +-#include "socfpga_cyclone5.dtsi" +- +-/ { +- model = "Novetech Chameleon96"; +- compatible = "novtech,chameleon96", "altr,socfpga-cyclone5", "altr,socfpga"; +- +- chosen { +- bootargs = "earlyprintk"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- name = "memory"; +- device_type = "memory"; +- reg = <0x0 0x20000000>; /* 512MB */ +- }; +- +- regulator_3_3v: 3-3-v-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- user_led1 { +- label = "green:user1"; +- gpios = <&porta 14 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- +- user_led2 { +- label = "green:user2"; +- gpios = <&porta 22 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "mmc0"; +- }; +- +- user_led3 { +- label = "green:user3"; +- gpios = <&porta 25 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "none"; +- }; +- +- user_led4 { +- label = "green:user4"; +- gpios = <&portb 3 GPIO_ACTIVE_LOW>; +- panic-indicator; +- linux,default-trigger = "none"; +- }; +- }; +-}; +- +-&gpio0 { +- status = "okay"; +-}; +- +-&gpio1 { +- status = "okay"; +-}; +- +-&i2c0 { +- /* On Low speed expansion */ +- label = "LS-I2C0"; +- status = "okay"; +-}; +- +-&i2c1 { +- /* On Low speed expansion */ +- label = "LS-I2C1"; +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- /* On High speed expansion */ +- label = "HS-I2C2"; +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®ulator_3_3v>; +- vqmmc-supply = <®ulator_3_3v>; +- status = "okay"; +-}; +- +-&spi0 { +- /* On High speed expansion */ +- label = "HS-SPI1"; +- status = "okay"; +-}; +- +-&spi1 { +- /* On Low speed expansion */ +- label = "LS-SPI0"; +- status = "okay"; +-}; +- +-&uart0 { +- /* On Low speed expansion */ +- label = "LS-UART1"; +- status = "okay"; +-}; +- +-&uart1 { +- /* On Low speed expansion */ +- label = "LS-UART0"; +- status = "okay"; +-}; +- +-&usbphy0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_de0_nano_soc.dts b/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_de0_nano_soc.dts +deleted file mode 100644 +index 67076e1b1c7f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_de0_nano_soc.dts ++++ /dev/null +@@ -1,101 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright Altera Corporation (C) 2015. All rights reserved. +- */ +- +-#include "socfpga_cyclone5.dtsi" +- +-/ { +- model = "Terasic DE-0(Atlas)"; +- compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga"; +- +- chosen { +- bootargs = "earlyprintk"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- name = "memory"; +- device_type = "memory"; +- reg = <0x0 0x40000000>; /* 1GB */ +- }; +- +- aliases { +- ethernet0 = &gmac1; +- }; +- +- regulator_3_3v: 3-3-v-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- hps0 { +- label = "hps_led0"; +- gpios = <&portb 24 0>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-&gmac1 { +- status = "okay"; +- phy-mode = "rgmii"; +- +- txd0-skew-ps = <0>; /* -420ps */ +- txd1-skew-ps = <0>; /* -420ps */ +- txd2-skew-ps = <0>; /* -420ps */ +- txd3-skew-ps = <0>; /* -420ps */ +- rxd0-skew-ps = <420>; /* 0ps */ +- rxd1-skew-ps = <420>; /* 0ps */ +- rxd2-skew-ps = <420>; /* 0ps */ +- rxd3-skew-ps = <420>; /* 0ps */ +- txen-skew-ps = <0>; /* -420ps */ +- txc-skew-ps = <1860>; /* 960ps */ +- rxdv-skew-ps = <420>; /* 0ps */ +- rxc-skew-ps = <1680>; /* 780ps */ +- +- max-frame-size = <3800>; +-}; +- +-&gpio0 { +- status = "okay"; +-}; +- +-&gpio1 { +- status = "okay"; +-}; +- +-&gpio2 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <100000>; +- +- adxl345: adxl345@53 { +- compatible = "adi,adxl345"; +- reg = <0x53>; +- +- interrupt-parent = <&portc>; +- interrupts = <3 2>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®ulator_3_3v>; +- vqmmc-supply = <®ulator_3_3v>; +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_mcv.dtsi b/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_mcv.dtsi +deleted file mode 100644 +index bd92806ffc12..000000000000 +--- a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_mcv.dtsi ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2015 Marek Vasut +- */ +- +-#include "socfpga_cyclone5.dtsi" +- +-/ { +- model = "Aries/DENX MCV"; +- compatible = "altr,socfpga-cyclone5", "altr,socfpga"; +- +- memory@0 { +- name = "memory"; +- device_type = "memory"; +- reg = <0x0 0x40000000>; /* 1 GiB */ +- }; +-}; +- +-&mmc0 { /* On-SoM eMMC */ +- bus-width = <8>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_mcvevk.dts b/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_mcvevk.dts +deleted file mode 100644 +index ceaec29770c6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_mcvevk.dts ++++ /dev/null +@@ -1,81 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2015 Marek Vasut +- */ +- +-#include "socfpga_cyclone5_mcv.dtsi" +- +-/ { +- model = "Aries/DENX MCV EVK"; +- compatible = "denx,mcvevk", "altr,socfpga-cyclone5", "altr,socfpga"; +- +- aliases { +- ethernet0 = &gmac0; +- stmpe-i2c0 = &stmpe1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&can0 { +- status = "okay"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&gmac0 { +- phy-mode = "rgmii"; +- status = "okay"; +-}; +- +-&gpio0 { /* GPIO 0 ... 28 */ +- status = "okay"; +-}; +- +-&gpio1 { /* GPIO 29 ... 57 */ +- status = "okay"; +-}; +- +-&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <100000>; +- +- stmpe1: stmpe811@41 { +- compatible = "st,stmpe811"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x41>; +- id = <0>; +- blocks = <0x5>; +- irq-gpio = <&portb 28 0x4>; /* GPIO 57, trig. level HI */ +- +- stmpe_touchscreen { +- compatible = "st,stmpe-ts"; +- ts,sample-time = <4>; +- ts,mod-12b = <1>; +- ts,ref-sel = <0>; +- ts,adc-freq = <1>; +- ts,ave-ctrl = <1>; +- ts,touch-det-delay = <3>; +- ts,settling = <4>; +- ts,fraction-z = <7>; +- ts,i-drive = <1>; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_socdk.dts b/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_socdk.dts +deleted file mode 100644 +index 51bb436784e2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_socdk.dts ++++ /dev/null +@@ -1,166 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2012 Altera Corporation +- */ +- +-#include "socfpga_cyclone5.dtsi" +- +-/ { +- model = "Altera SOCFPGA Cyclone V SoC Development Kit"; +- compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga"; +- +- chosen { +- bootargs = "earlyprintk"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- name = "memory"; +- device_type = "memory"; +- reg = <0x0 0x40000000>; /* 1GB */ +- }; +- +- aliases { +- /* this allow the ethaddr uboot environmnet variable contents +- * to be added to the gmac1 device tree blob. +- */ +- ethernet0 = &gmac1; +- }; +- +- leds { +- compatible = "gpio-leds"; +- hps0 { +- label = "hps_led0"; +- gpios = <&portb 15 1>; +- }; +- +- hps1 { +- label = "hps_led1"; +- gpios = <&portb 14 1>; +- }; +- +- hps2 { +- label = "hps_led2"; +- gpios = <&portb 13 1>; +- }; +- +- hps3 { +- label = "hps_led3"; +- gpios = <&portb 12 1>; +- }; +- }; +- +- regulator_3_3v: 3-3-v-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&can0 { +- status = "okay"; +-}; +- +-&gmac1 { +- status = "okay"; +- phy-mode = "rgmii"; +- +- rxd0-skew-ps = <0>; +- rxd1-skew-ps = <0>; +- rxd2-skew-ps = <0>; +- rxd3-skew-ps = <0>; +- txen-skew-ps = <0>; +- txc-skew-ps = <2600>; +- rxdv-skew-ps = <0>; +- rxc-skew-ps = <2000>; +-}; +- +-&gpio0 { +- status = "okay"; +-}; +- +-&gpio1 { +- status = "okay"; +-}; +- +-&gpio2 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <100000>; +- +- /* +- * adjust the falling times to decrease the i2c frequency to 50Khz +- * because the LCD module does not work at the standard 100Khz +- */ +- i2c-sda-falling-time-ns = <5000>; +- i2c-scl-falling-time-ns = <5000>; +- +- eeprom@51 { +- compatible = "atmel,24c32"; +- reg = <0x51>; +- pagesize = <32>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +-}; +- +-&mmc0 { +- cd-gpios = <&portb 18 0>; +- vmmc-supply = <®ulator_3_3v>; +- vqmmc-supply = <®ulator_3_3v>; +- status = "okay"; +-}; +- +-&qspi { +- status = "okay"; +- +- flash0: n25q00@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,mt25qu02g", "jedec,spi-nor"; +- reg = <0>; /* chip select */ +- spi-max-frequency = <100000000>; +- +- m25p,fast-read; +- cdns,page-size = <256>; +- cdns,block-size = <16>; +- cdns,read-delay = <4>; +- cdns,tshsl-ns = <50>; +- cdns,tsd2d-ns = <50>; +- cdns,tchsh-ns = <4>; +- cdns,tslch-ns = <4>; +- +- partition@qspi-boot { +- /* 8MB for raw data. */ +- label = "Flash 0 Raw Data"; +- reg = <0x0 0x800000>; +- }; +- +- partition@qspi-rootfs { +- /* 120MB for jffs2 data. */ +- label = "Flash 0 jffs2 Filesystem"; +- reg = <0x800000 0x7800000>; +- }; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- +- spidev@0 { +- compatible = "rohm,dh2228fv"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_sockit.dts b/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_sockit.dts +deleted file mode 100644 +index cae9ddd5ed38..000000000000 +--- a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_sockit.dts ++++ /dev/null +@@ -1,189 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2013 Steffen Trumtrar +- */ +- +-#include "socfpga_cyclone5.dtsi" +- +-/ { +- model = "Terasic SoCkit"; +- compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga"; +- +- chosen { +- bootargs = "earlyprintk"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- name = "memory"; +- device_type = "memory"; +- reg = <0x0 0x40000000>; /* 1GB */ +- }; +- +- aliases { +- /* this allow the ethaddr uboot environmnet variable contents +- * to be added to the gmac1 device tree blob. +- */ +- ethernet0 = &gmac1; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- hps_led0 { +- label = "hps:blue:led0"; +- gpios = <&portb 24 0>; /* HPS_GPIO53 */ +- linux,default-trigger = "heartbeat"; +- }; +- +- hps_led1 { +- label = "hps:blue:led1"; +- gpios = <&portb 25 0>; /* HPS_GPIO54 */ +- linux,default-trigger = "heartbeat"; +- }; +- +- hps_led2 { +- label = "hps:blue:led2"; +- gpios = <&portb 26 0>; /* HPS_GPIO55 */ +- linux,default-trigger = "heartbeat"; +- }; +- +- hps_led3 { +- label = "hps:blue:led3"; +- gpios = <&portb 27 0>; /* HPS_GPIO56 */ +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- hps_sw0 { +- label = "hps_sw0"; +- gpios = <&portc 20 0>; /* HPS_GPI7 */ +- linux,input-type = <5>; /* EV_SW */ +- linux,code = <0x0>; /* SW_LID */ +- }; +- +- hps_sw1 { +- label = "hps_sw1"; +- gpios = <&portc 19 0>; /* HPS_GPI6 */ +- linux,input-type = <5>; /* EV_SW */ +- linux,code = <0x5>; /* SW_DOCK */ +- }; +- +- hps_sw2 { +- label = "hps_sw2"; +- gpios = <&portc 18 0>; /* HPS_GPI5 */ +- linux,input-type = <5>; /* EV_SW */ +- linux,code = <0xa>; /* SW_KEYPAD_SLIDE */ +- }; +- +- hps_sw3 { +- label = "hps_sw3"; +- gpios = <&portc 17 0>; /* HPS_GPI4 */ +- linux,input-type = <5>; /* EV_SW */ +- linux,code = <0xc>; /* SW_ROTATE_LOCK */ +- }; +- +- hps_hkey0 { +- label = "hps_hkey0"; +- gpios = <&portc 21 1>; /* HPS_GPI8 */ +- linux,code = <187>; /* KEY_F17 */ +- }; +- +- hps_hkey1 { +- label = "hps_hkey1"; +- gpios = <&portc 22 1>; /* HPS_GPI9 */ +- linux,code = <188>; /* KEY_F18 */ +- }; +- +- hps_hkey2 { +- label = "hps_hkey2"; +- gpios = <&portc 23 1>; /* HPS_GPI10 */ +- linux,code = <189>; /* KEY_F19 */ +- }; +- +- hps_hkey3 { +- label = "hps_hkey3"; +- gpios = <&portc 24 1>; /* HPS_GPI11 */ +- linux,code = <190>; /* KEY_F20 */ +- }; +- }; +- +- regulator_3_3v: vcc3p3-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "VCC3P3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&gmac1 { +- status = "okay"; +- phy-mode = "rgmii"; +- +- rxd0-skew-ps = <0>; +- rxd1-skew-ps = <0>; +- rxd2-skew-ps = <0>; +- rxd3-skew-ps = <0>; +- txen-skew-ps = <0>; +- txc-skew-ps = <2600>; +- rxdv-skew-ps = <0>; +- rxc-skew-ps = <2000>; +-}; +- +-&gpio0 { /* GPIO 0..29 */ +- status = "okay"; +-}; +- +-&gpio1 { /* GPIO 30..57 */ +- status = "okay"; +-}; +- +-&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- +- accel1: accelerometer@53 { +- compatible = "adi,adxl345"; +- reg = <0x53>; +- +- interrupt-parent = <&portc>; +- interrupts = <3 2>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®ulator_3_3v>; +- vqmmc-supply = <®ulator_3_3v>; +- status = "okay"; +-}; +- +-&qspi { +- status = "okay"; +- +- flash: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,mt25qu02g", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <100000000>; +- +- m25p,fast-read; +- cdns,page-size = <256>; +- cdns,block-size = <16>; +- cdns,read-delay = <4>; +- cdns,tshsl-ns = <50>; +- cdns,tsd2d-ns = <50>; +- cdns,tchsh-ns = <4>; +- cdns,tslch-ns = <4>; +- }; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_socrates.dts b/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_socrates.dts +deleted file mode 100644 +index ca18b959e655..000000000000 +--- a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_socrates.dts ++++ /dev/null +@@ -1,94 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2014 Steffen Trumtrar +- */ +- +-#include "socfpga_cyclone5.dtsi" +- +-/ { +- model = "EBV SOCrates"; +- compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga"; +- +- aliases { +- ethernet0 = &gmac1; +- }; +- +- chosen { +- bootargs = "earlyprintk"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- name = "memory"; +- device_type = "memory"; +- reg = <0x0 0x40000000>; /* 1GB */ +- }; +- +- leds: gpio-leds { +- }; +-}; +- +-&gmac1 { +- phy-mode = "rgmii"; +- status = "okay"; +-}; +- +-&gpio0 { +- status = "okay"; +-}; +- +-&gpio1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- rtc: rtc@68 { +- compatible = "st,m41t82"; +- reg = <0x68>; +- }; +-}; +- +-&leds { +- compatible = "gpio-leds"; +- +- led0 { +- label = "led:green:heartbeat"; +- gpios = <&porta 28 1>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led1 { +- label = "led:green:D7"; +- gpios = <&portb 19 1>; +- }; +- +- led2 { +- label = "led:green:D8"; +- gpios = <&portb 25 1>; +- }; +-}; +- +-&mmc { +- status = "okay"; +-}; +- +-&qspi { +- status = "okay"; +- +- flash: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q256a", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <100000000>; +- m25p,fast-read; +- cdns,read-delay = <4>; +- cdns,tshsl-ns = <50>; +- cdns,tsd2d-ns = <50>; +- cdns,tchsh-ns = <4>; +- cdns,tslch-ns = <4>; +- status = "okay"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_sodia.dts b/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_sodia.dts +deleted file mode 100644 +index 3f7aa7bf0863..000000000000 +--- a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_sodia.dts ++++ /dev/null +@@ -1,132 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2016 Nobuhiro Iwamatsu +- */ +- +-#include "socfpga_cyclone5.dtsi" +-#include +-#include +- +-/ { +- model = "Altera SOCFPGA Cyclone V SoC Macnica Sodia board"; +- compatible = "macnica,sodia", "altr,socfpga-cyclone5", "altr,socfpga"; +- +- chosen { +- bootargs = "earlyprintk"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- name = "memory"; +- device_type = "memory"; +- reg = <0x0 0x40000000>; +- }; +- +- aliases { +- ethernet0 = &gmac1; +- }; +- +- regulator_3_3v: 3-3-v-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- leds: gpio-leds { +- compatible = "gpio-leds"; +- +- hps_led0 { +- label = "hps:green:led0"; +- gpios = <&portb 12 GPIO_ACTIVE_LOW>; +- }; +- +- hps_led1 { +- label = "hps:green:led1"; +- gpios = <&portb 13 GPIO_ACTIVE_LOW>; +- }; +- +- hps_led2 { +- label = "hps:green:led2"; +- gpios = <&portb 14 GPIO_ACTIVE_LOW>; +- }; +- +- hps_led3 { +- label = "hps:green:led3"; +- gpios = <&portb 15 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&gmac1 { +- status = "okay"; +- phy-mode = "rgmii"; +- phy = <&phy0>; +- +- mdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- phy0: ethernet-phy@0 { +- reg = <0>; +- rxd0-skew-ps = <0>; +- rxd1-skew-ps = <0>; +- rxd2-skew-ps = <0>; +- rxd3-skew-ps = <0>; +- rxdv-skew-ps = <0>; +- rxc-skew-ps = <3000>; +- txen-skew-ps = <0>; +- txc-skew-ps = <3000>; +- }; +- }; +-}; +- +-&gpio1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- eeprom@51 { +- compatible = "atmel,24c32"; +- reg = <0x51>; +- pagesize = <32>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +-}; +- +-&mmc0 { +- cd-gpios = <&portb 18 0>; +- vmmc-supply = <®ulator_3_3v>; +- vqmmc-supply = <®ulator_3_3v>; +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&qspi { +- status = "okay"; +- +- flash0: n25q512a@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q512a", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <100000000>; +- +- m25p,fast-read; +- cdns,page-size = <256>; +- cdns,block-size = <16>; +- cdns,read-delay = <4>; +- cdns,tshsl-ns = <50>; +- cdns,tsd2d-ns = <50>; +- cdns,tchsh-ns = <4>; +- cdns,tslch-ns = <4>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_vining_fpga.dts b/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_vining_fpga.dts +deleted file mode 100644 +index 25874e1b9c82..000000000000 +--- a/scripts/dtc/include-prefixes/arm/socfpga_cyclone5_vining_fpga.dts ++++ /dev/null +@@ -1,267 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR X11) +-/* +- * Copyright (C) 2015 Marek Vasut +- */ +- +-#include "socfpga_cyclone5.dtsi" +-#include +-#include +- +-/ { +- model = "samtec VIN|ING FPGA"; +- compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga"; +- +- chosen { +- bootargs = "earlyprintk"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- name = "memory"; +- device_type = "memory"; +- reg = <0x0 0x40000000>; /* 1GB */ +- }; +- +- aliases { +- /* +- * This allow the ethaddr uboot environment variable contents +- * to be added to the gmac1 device tree blob. +- */ +- ethernet0 = &gmac1; +- ethernet1 = &gmac0; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- hps_temp0 { +- label = "BTN_0"; /* TEMP_OS */ +- gpios = <&portc 18 GPIO_ACTIVE_LOW>; /* HPS_GPI5 */ +- linux,code = ; +- }; +- +- hps_hkey0 { +- label = "GP_SWITCH"; /* GP_SWITCH */ +- gpios = <&portc 19 GPIO_ACTIVE_LOW>; /* HPS_GPI6 */ +- linux,code = ; +- }; +- +- hps_hkey1 { +- label = "RESET_SWITCH"; /* RESET_SWITCH */ +- gpios = <&portc 20 GPIO_ACTIVE_LOW>; /* HPS_GPI7 */ +- linux,code = ; +- }; +- +- hps_hkey2 { +- label = "POWER_DOWN"; /* POWER_DOWN */ +- gpios = <&portc 4 GPIO_ACTIVE_LOW>; /* HPS_GPIO62 */ +- linux,code = ; +- }; +- +- hps_hkey3 { +- label = "SENSE"; /* SENSE */ +- gpios = <&porta 9 GPIO_ACTIVE_LOW>; /* HPS_GPIO9 */ +- linux,code = ; +- }; +- }; +- +- regulator-usb-nrst { +- compatible = "regulator-fixed"; +- regulator-name = "usb_nrst"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&portb 5 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <70000>; +- enable-active-high; +- regulator-always-on; +- }; +-}; +- +-&gmac1 { +- status = "okay"; +- phy-mode = "rgmii"; +- phy-handle = <&phy1>; +- +- snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- snps,reset-delays-us = <10000 10000 10000>; +- +- mdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy1: ethernet-phy@1 { +- reg = <1>; +- rxd0-skew-ps = <0>; +- rxd1-skew-ps = <0>; +- rxd2-skew-ps = <0>; +- rxd3-skew-ps = <0>; +- txd0-skew-ps = <0>; +- txd1-skew-ps = <0>; +- txd2-skew-ps = <0>; +- txd3-skew-ps = <0>; +- txen-skew-ps = <0>; +- txc-skew-ps = <1860>; +- rxdv-skew-ps = <0>; +- rxc-skew-ps = <1860>; +- }; +- }; +-}; +- +-&gpio0 { /* GPIO 0..29 */ +- status = "okay"; +-}; +- +-&gpio1 { /* GPIO 30..57 */ +- status = "okay"; +-}; +- +-&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- gpio: pca9557@1f { +- compatible = "nxp,pca9557"; +- reg = <0x1f>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- temp: lm75@48 { +- compatible = "lm75"; +- reg = <0x48>; +- }; +- +- at24@50 { +- compatible = "atmel,24c01"; +- pagesize = <8>; +- reg = <0x50>; +- }; +- +- i2cswitch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- i2c@6 { /* Backplane EEPROM */ +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- eeprom@51 { +- compatible = "atmel,24c01"; +- pagesize = <8>; +- reg = <0x51>; +- }; +- }; +- +- i2c@7 { /* Power board EEPROM */ +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- eeprom@51 { +- compatible = "atmel,24c01"; +- pagesize = <8>; +- reg = <0x51>; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <100000>; +- +- at24@50 { +- compatible = "atmel,24c02"; +- pagesize = <8>; +- reg = <0x50>; +- }; +-}; +- +-&qspi { +- status = "okay"; +- +- n25q128@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q128", "jedec,spi-nor"; +- reg = <0>; /* chip select */ +- spi-max-frequency = <100000000>; +- m25p,fast-read; +- +- cdns,page-size = <256>; +- cdns,block-size = <16>; +- cdns,read-delay = <4>; +- cdns,tshsl-ns = <50>; +- cdns,tsd2d-ns = <50>; +- cdns,tchsh-ns = <4>; +- cdns,tslch-ns = <4>; +- }; +- +- n25q00@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,mt25qu02g", "jedec,spi-nor"; +- reg = <1>; /* chip select */ +- spi-max-frequency = <100000000>; +- m25p,fast-read; +- +- cdns,page-size = <256>; +- cdns,block-size = <16>; +- cdns,read-delay = <4>; +- cdns,tshsl-ns = <50>; +- cdns,tsd2d-ns = <50>; +- cdns,tchsh-ns = <4>; +- cdns,tslch-ns = <4>; +- }; +-}; +- +-&usb0 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb1 { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/socfpga_vt.dts b/scripts/dtc/include-prefixes/arm/socfpga_vt.dts +deleted file mode 100644 +index a77846f73b34..000000000000 +--- a/scripts/dtc/include-prefixes/arm/socfpga_vt.dts ++++ /dev/null +@@ -1,77 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2013 Altera Corporation +- */ +- +-/dts-v1/; +-#include "socfpga.dtsi" +- +-/ { +- model = "Altera SOCFPGA VT"; +- compatible = "altr,socfpga-vt", "altr,socfpga"; +- +- chosen { +- bootargs = "console=ttyS0,57600"; +- }; +- +- memory@0 { +- name = "memory"; +- device_type = "memory"; +- reg = <0x0 0x40000000>; /* 1 GB */ +- }; +- +- soc { +- clkmgr@ffd04000 { +- clocks { +- osc1 { +- clock-frequency = <10000000>; +- }; +- }; +- }; +- +- dwmmc0@ff704000 { +- broken-cd; +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- }; +- +- ethernet@ff700000 { +- phy-mode = "gmii"; +- status = "okay"; +- }; +- +- timer0@ffc08000 { +- clock-frequency = <7000000>; +- }; +- +- timer1@ffc09000 { +- clock-frequency = <7000000>; +- }; +- +- timer2@ffd00000 { +- clock-frequency = <7000000>; +- }; +- +- timer3@ffd01000 { +- clock-frequency = <7000000>; +- }; +- +- serial0@ffc02000 { +- clock-frequency = <7372800>; +- }; +- +- serial1@ffc03000 { +- clock-frequency = <7372800>; +- }; +- +- sysmgr@ffd08000 { +- cpu1-start-addr = <0xffd08010>; +- }; +- }; +-}; +- +-&gmac0 { +- status = "okay"; +- phy-mode = "gmii"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/spear1310-evb.dts b/scripts/dtc/include-prefixes/arm/spear1310-evb.dts +deleted file mode 100644 +index 8fcb6be6e7c7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/spear1310-evb.dts ++++ /dev/null +@@ -1,421 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * DTS file for SPEAr1310 Evaluation Baord +- * +- * Copyright 2012 Viresh Kumar +- */ +- +-/dts-v1/; +-/include/ "spear1310.dtsi" +- +-/ { +- model = "ST SPEAr1310 Evaluation Board"; +- compatible = "st,spear1310-evb", "st,spear1310"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory { +- reg = <0 0x40000000>; +- }; +- +- ahb { +- pinmux@e0700000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- i2c0 { +- st,pins = "i2c0_grp"; +- st,function = "i2c0"; +- }; +- i2s0 { +- st,pins = "i2s0_grp"; +- st,function = "i2s0"; +- }; +- i2s1 { +- st,pins = "i2s1_grp"; +- st,function = "i2s1"; +- }; +- gpio { +- st,pins = "arm_gpio_grp"; +- st,function = "arm_gpio"; +- }; +- clcd { +- st,pins = "clcd_grp" , "clcd_high_res"; +- st,function = "clcd"; +- }; +- eth { +- st,pins = "gmii_grp"; +- st,function = "gmii"; +- }; +- ssp0 { +- st,pins = "ssp0_grp"; +- st,function = "ssp0"; +- }; +- kbd { +- st,pins = "keyboard_6x6_grp"; +- st,function = "keyboard"; +- }; +- sdhci { +- st,pins = "sdhci_grp"; +- st,function = "sdhci"; +- }; +- smi-pmx { +- st,pins = "smi_2_chips_grp"; +- st,function = "smi"; +- }; +- uart0 { +- st,pins = "uart0_grp"; +- st,function = "uart0"; +- }; +- rs485 { +- st,pins = "rs485_0_1_tdm_0_1_grp"; +- st,function = "rs485_0_1_tdm_0_1"; +- }; +- i2c1_2 { +- st,pins = "i2c_1_2_grp"; +- st,function = "i2c_1_2"; +- }; +- smii { +- st,pins = "smii_0_1_2_grp"; +- st,function = "smii_0_1_2"; +- }; +- nand { +- st,pins = "nand_8bit_grp", +- "nand_16bit_grp"; +- st,function = "nand"; +- }; +- sata { +- st,pins = "sata0_grp"; +- st,function = "sata"; +- }; +- pcie { +- st,pins = "pcie1_grp", "pcie2_grp"; +- st,function = "pci_express"; +- }; +- }; +- }; +- +- ahci@b1000000 { +- status = "okay"; +- }; +- +- miphy@eb800000 { +- status = "okay"; +- }; +- +- cf@b2800000 { +- status = "okay"; +- }; +- +- dma@ea800000 { +- status = "okay"; +- }; +- +- dma@eb000000 { +- status = "okay"; +- }; +- +- fsmc: flash@b0000000 { +- status = "okay"; +- +- partition@0 { +- label = "xloader"; +- reg = <0x0 0x80000>; +- }; +- partition@80000 { +- label = "u-boot"; +- reg = <0x80000 0x140000>; +- }; +- partition@1C0000 { +- label = "environment"; +- reg = <0x1C0000 0x40000>; +- }; +- partition@200000 { +- label = "dtb"; +- reg = <0x200000 0x40000>; +- }; +- partition@240000 { +- label = "linux"; +- reg = <0x240000 0xC00000>; +- }; +- partition@E40000 { +- label = "rootfs"; +- reg = <0xE40000 0x0>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- button@1 { +- label = "wakeup"; +- linux,code = <0x100>; +- gpios = <&gpio0 7 0x4>; +- debounce-interval = <20>; +- wakeup-source; +- }; +- }; +- +- gmac0: eth@e2000000 { +- phy-mode = "gmii"; +- status = "okay"; +- }; +- +- sdhci@b3000000 { +- status = "okay"; +- }; +- +- smi: flash@ea000000 { +- status = "okay"; +- clock-rate=<50000000>; +- +- flash@e6000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xe6000000 0x800000>; +- st,smi-fast-mode; +- +- partition@0 { +- label = "xloader"; +- reg = <0x0 0x10000>; +- }; +- partition@10000 { +- label = "u-boot"; +- reg = <0x10000 0x50000>; +- }; +- partition@60000 { +- label = "environment"; +- reg = <0x60000 0x10000>; +- }; +- partition@70000 { +- label = "dtb"; +- reg = <0x70000 0x10000>; +- }; +- partition@80000 { +- label = "linux"; +- reg = <0x80000 0x310000>; +- }; +- partition@390000 { +- label = "rootfs"; +- reg = <0x390000 0x0>; +- }; +- }; +- }; +- +- ehci@e4800000 { +- status = "okay"; +- }; +- +- ehci@e5800000 { +- status = "okay"; +- }; +- +- ohci@e4000000 { +- status = "okay"; +- }; +- +- ohci@e5000000 { +- status = "okay"; +- }; +- +- apb { +- adc@e0080000 { +- status = "okay"; +- }; +- +- gpio0: gpio@e0600000 { +- status = "okay"; +- }; +- +- gpio1: gpio@e0680000 { +- status = "okay"; +- }; +- +- gpio@d8400000 { +- status = "okay"; +- }; +- +- i2c0: i2c@e0280000 { +- status = "okay"; +- }; +- +- kbd@e0300000 { +- linux,keymap = < 0x00000001 +- 0x00010002 +- 0x00020003 +- 0x00030004 +- 0x00040005 +- 0x00050006 +- 0x00060007 +- 0x00070008 +- 0x00080009 +- 0x0100000a +- 0x0101000c +- 0x0102000d +- 0x0103000e +- 0x0104000f +- 0x01050010 +- 0x01060011 +- 0x01070012 +- 0x01080013 +- 0x02000014 +- 0x02010015 +- 0x02020016 +- 0x02030017 +- 0x02040018 +- 0x02050019 +- 0x0206001a +- 0x0207001b +- 0x0208001c +- 0x0300001d +- 0x0301001e +- 0x0302001f +- 0x03030020 +- 0x03040021 +- 0x03050022 +- 0x03060023 +- 0x03070024 +- 0x03080025 +- 0x04000026 +- 0x04010027 +- 0x04020028 +- 0x04030029 +- 0x0404002a +- 0x0405002b +- 0x0406002c +- 0x0407002d +- 0x0408002e +- 0x0500002f +- 0x05010030 +- 0x05020031 +- 0x05030032 +- 0x05040033 +- 0x05050034 +- 0x05060035 +- 0x05070036 +- 0x05080037 +- 0x06000038 +- 0x06010039 +- 0x0602003a +- 0x0603003b +- 0x0604003c +- 0x0605003d +- 0x0606003e +- 0x0607003f +- 0x06080040 +- 0x07000041 +- 0x07010042 +- 0x07020043 +- 0x07030044 +- 0x07040045 +- 0x07050046 +- 0x07060047 +- 0x07070048 +- 0x07080049 +- 0x0800004a +- 0x0801004b +- 0x0802004c +- 0x0803004d +- 0x0804004e +- 0x0805004f +- 0x08060050 +- 0x08070051 +- 0x08080052 >; +- autorepeat; +- st,mode = <0>; +- suspended_rate = <2000000>; +- status = "okay"; +- }; +- +- rtc@e0580000 { +- status = "okay"; +- }; +- +- serial@e0000000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <>; +- }; +- +- spi0: spi@e0100000 { +- status = "okay"; +- num-cs = <3>; +- cs-gpios = <&gpio1 7 0>, <&spics 0 0>, <&spics 1 0>; +- +- stmpe610@0 { +- compatible = "st,stmpe610"; +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- spi-max-frequency = <1000000>; +- spi-cpha; +- pl022,hierarchy = <0>; +- pl022,interface = <0>; +- pl022,slave-tx-disable; +- pl022,com-mode = <0>; +- pl022,rx-level-trig = <0>; +- pl022,tx-level-trig = <0>; +- pl022,ctrl-len = <0x7>; +- pl022,wait-state = <0>; +- pl022,duplex = <0>; +- interrupts = <6 0x4>; +- interrupt-parent = <&gpio1>; +- irq-trigger = <0x2>; +- +- stmpe_touchscreen { +- compatible = "st,stmpe-ts"; +- ts,sample-time = <4>; +- ts,mod-12b = <1>; +- ts,ref-sel = <0>; +- ts,adc-freq = <1>; +- ts,ave-ctrl = <1>; +- ts,touch-det-delay = <2>; +- ts,settling = <2>; +- ts,fraction-z = <7>; +- ts,i-drive = <1>; +- }; +- }; +- +- m25p80@1 { +- compatible = "st,m25p80"; +- reg = <1>; +- spi-max-frequency = <12000000>; +- spi-cpol; +- spi-cpha; +- pl022,hierarchy = <0>; +- pl022,interface = <0>; +- pl022,slave-tx-disable; +- pl022,com-mode = <0x2>; +- pl022,rx-level-trig = <0>; +- pl022,tx-level-trig = <0>; +- pl022,ctrl-len = <0x11>; +- pl022,wait-state = <0>; +- pl022,duplex = <0>; +- }; +- +- spidev@2 { +- compatible = "spidev"; +- reg = <2>; +- spi-max-frequency = <25000000>; +- spi-cpha; +- pl022,hierarchy = <0>; +- pl022,interface = <0>; +- pl022,slave-tx-disable; +- pl022,com-mode = <0x2>; +- pl022,rx-level-trig = <0>; +- pl022,tx-level-trig = <0>; +- pl022,ctrl-len = <0x11>; +- pl022,wait-state = <0>; +- pl022,duplex = <0>; +- }; +- }; +- +- wdt@ec800620 { +- status = "okay"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/spear1310.dtsi b/scripts/dtc/include-prefixes/arm/spear1310.dtsi +deleted file mode 100644 +index c4b49baf9804..000000000000 +--- a/scripts/dtc/include-prefixes/arm/spear1310.dtsi ++++ /dev/null +@@ -1,313 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * DTS file for all SPEAr1310 SoCs +- * +- * Copyright 2012 Viresh Kumar +- */ +- +-/include/ "spear13xx.dtsi" +- +-/ { +- compatible = "st,spear1310"; +- +- ahb { +- spics: spics@e0700000{ +- compatible = "st,spear-spics-gpio"; +- reg = <0xe0700000 0x1000>; +- st-spics,peripcfg-reg = <0x3b0>; +- st-spics,sw-enable-bit = <12>; +- st-spics,cs-value-bit = <11>; +- st-spics,cs-enable-mask = <3>; +- st-spics,cs-enable-shift = <8>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- miphy0: miphy@eb800000 { +- compatible = "st,spear1310-miphy"; +- reg = <0xeb800000 0x4000>; +- misc = <&misc>; +- phy-id = <0>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- miphy1: miphy@eb804000 { +- compatible = "st,spear1310-miphy"; +- reg = <0xeb804000 0x4000>; +- misc = <&misc>; +- phy-id = <1>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- miphy2: miphy@eb808000 { +- compatible = "st,spear1310-miphy"; +- reg = <0xeb808000 0x4000>; +- misc = <&misc>; +- phy-id = <2>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- ahci0: ahci@b1000000 { +- compatible = "snps,spear-ahci"; +- reg = <0xb1000000 0x10000>; +- interrupts = <0 68 0x4>; +- phys = <&miphy0 0>; +- phy-names = "sata-phy"; +- status = "disabled"; +- }; +- +- ahci1: ahci@b1800000 { +- compatible = "snps,spear-ahci"; +- reg = <0xb1800000 0x10000>; +- interrupts = <0 69 0x4>; +- phys = <&miphy1 0>; +- phy-names = "sata-phy"; +- status = "disabled"; +- }; +- +- ahci2: ahci@b4000000 { +- compatible = "snps,spear-ahci"; +- reg = <0xb4000000 0x10000>; +- interrupts = <0 70 0x4>; +- phys = <&miphy2 0>; +- phy-names = "sata-phy"; +- status = "disabled"; +- }; +- +- pcie0: pcie@b1000000 { +- compatible = "st,spear1340-pcie", "snps,dw-pcie"; +- reg = <0xb1000000 0x4000>, <0x80000000 0x20000>; +- reg-names = "dbi", "config"; +- interrupts = <0 68 0x4>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0x0 0 &gic 0 68 0x4>; +- num-lanes = <1>; +- phys = <&miphy0 1>; +- phy-names = "pcie-phy"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ +- 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ +- bus-range = <0x00 0xff>; +- status = "disabled"; +- }; +- +- pcie1: pcie@b1800000 { +- compatible = "st,spear1340-pcie", "snps,dw-pcie"; +- reg = <0xb1800000 0x4000>, <0x90000000 0x20000>; +- reg-names = "dbi", "config"; +- interrupts = <0 69 0x4>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0x0 0 &gic 0 69 0x4>; +- num-lanes = <1>; +- phys = <&miphy1 1>; +- phy-names = "pcie-phy"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */ +- 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */ +- bus-range = <0x00 0xff>; +- status = "disabled"; +- }; +- +- pcie2: pcie@b4000000 { +- compatible = "st,spear1340-pcie", "snps,dw-pcie"; +- reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>; +- reg-names = "dbi", "config"; +- interrupts = <0 70 0x4>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0x0 0 &gic 0 70 0x4>; +- num-lanes = <1>; +- phys = <&miphy2 1>; +- phy-names = "pcie-phy"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */ +- 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ +- bus-range = <0x00 0xff>; +- status = "disabled"; +- }; +- +- gmac1: eth@5c400000 { +- compatible = "st,spear600-gmac"; +- reg = <0x5c400000 0x8000>; +- interrupts = <0 95 0x4>; +- interrupt-names = "macirq"; +- phy-mode = "mii"; +- status = "disabled"; +- }; +- +- gmac2: eth@5c500000 { +- compatible = "st,spear600-gmac"; +- reg = <0x5c500000 0x8000>; +- interrupts = <0 96 0x4>; +- interrupt-names = "macirq"; +- phy-mode = "mii"; +- status = "disabled"; +- }; +- +- gmac3: eth@5c600000 { +- compatible = "st,spear600-gmac"; +- reg = <0x5c600000 0x8000>; +- interrupts = <0 97 0x4>; +- interrupt-names = "macirq"; +- phy-mode = "rmii"; +- status = "disabled"; +- }; +- +- gmac4: eth@5c700000 { +- compatible = "st,spear600-gmac"; +- reg = <0x5c700000 0x8000>; +- interrupts = <0 98 0x4>; +- interrupt-names = "macirq"; +- phy-mode = "rgmii"; +- status = "disabled"; +- }; +- +- pinmux: pinmux@e0700000 { +- compatible = "st,spear1310-pinmux"; +- reg = <0xe0700000 0x1000>; +- #gpio-range-cells = <3>; +- }; +- +- apb { +- i2c1: i2c@5cd00000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0x5cd00000 0x1000>; +- interrupts = <0 87 0x4>; +- status = "disabled"; +- }; +- +- i2c2: i2c@5ce00000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0x5ce00000 0x1000>; +- interrupts = <0 88 0x4>; +- status = "disabled"; +- }; +- +- i2c3: i2c@5cf00000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0x5cf00000 0x1000>; +- interrupts = <0 89 0x4>; +- status = "disabled"; +- }; +- +- i2c4: i2c@5d000000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0x5d000000 0x1000>; +- interrupts = <0 90 0x4>; +- status = "disabled"; +- }; +- +- i2c5: i2c@5d100000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0x5d100000 0x1000>; +- interrupts = <0 91 0x4>; +- status = "disabled"; +- }; +- +- i2c6: i2c@5d200000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0x5d200000 0x1000>; +- interrupts = <0 92 0x4>; +- status = "disabled"; +- }; +- +- i2c7: i2c@5d300000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0x5d300000 0x1000>; +- interrupts = <0 93 0x4>; +- status = "disabled"; +- }; +- +- spi1: spi@5d400000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x5d400000 0x1000>; +- interrupts = <0 99 0x4>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- serial@5c800000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x5c800000 0x1000>; +- interrupts = <0 82 0x4>; +- status = "disabled"; +- }; +- +- serial@5c900000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x5c900000 0x1000>; +- interrupts = <0 83 0x4>; +- status = "disabled"; +- }; +- +- serial@5ca00000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x5ca00000 0x1000>; +- interrupts = <0 84 0x4>; +- status = "disabled"; +- }; +- +- serial@5cb00000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x5cb00000 0x1000>; +- interrupts = <0 85 0x4>; +- status = "disabled"; +- }; +- +- serial@5cc00000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x5cc00000 0x1000>; +- interrupts = <0 86 0x4>; +- status = "disabled"; +- }; +- +- thermal@e07008c4 { +- st,thermal-flags = <0x7000>; +- }; +- +- gpiopinctrl: gpio@d8400000 { +- compatible = "st,spear-plgpio"; +- reg = <0xd8400000 0x1000>; +- interrupts = <0 100 0x4>; +- #interrupt-cells = <1>; +- interrupt-controller; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinmux 0 0 246>; +- status = "disabled"; +- +- st-plgpio,ngpio = <246>; +- st-plgpio,enb-reg = <0xd0>; +- st-plgpio,wdata-reg = <0x90>; +- st-plgpio,dir-reg = <0xb0>; +- st-plgpio,ie-reg = <0x30>; +- st-plgpio,rdata-reg = <0x70>; +- st-plgpio,mis-reg = <0x10>; +- st-plgpio,eit-reg = <0x50>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/spear1340-evb.dts b/scripts/dtc/include-prefixes/arm/spear1340-evb.dts +deleted file mode 100644 +index f70ff56d4542..000000000000 +--- a/scripts/dtc/include-prefixes/arm/spear1340-evb.dts ++++ /dev/null +@@ -1,519 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * DTS file for SPEAr1340 Evaluation Baord +- * +- * Copyright 2012 Viresh Kumar +- */ +- +-/dts-v1/; +-/include/ "spear1340.dtsi" +- +-/ { +- model = "ST SPEAr1340 Evaluation Board"; +- compatible = "st,spear1340-evb", "st,spear1340"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory { +- reg = <0 0x40000000>; +- }; +- +- ahb { +- pinmux@e0700000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- pads_as_gpio { +- st,pins = "pads_as_gpio_grp"; +- st,function = "pads_as_gpio"; +- }; +- fsmc { +- st,pins = "fsmc_8bit_grp"; +- st,function = "fsmc"; +- }; +- uart0 { +- st,pins = "uart0_grp"; +- st,function = "uart0"; +- }; +- i2c0 { +- st,pins = "i2c0_grp"; +- st,function = "i2c0"; +- }; +- i2c1 { +- st,pins = "i2c1_grp"; +- st,function = "i2c1"; +- }; +- spdif-in { +- st,pins = "spdif_in_grp"; +- st,function = "spdif_in"; +- }; +- spdif-out { +- st,pins = "spdif_out_grp"; +- st,function = "spdif_out"; +- }; +- ssp0 { +- st,pins = "ssp0_grp", "ssp0_cs1_grp", "ssp0_cs2_grp", "ssp0_cs3_grp"; +- st,function = "ssp0"; +- }; +- smi-pmx { +- st,pins = "smi_grp"; +- st,function = "smi"; +- }; +- i2s { +- st,pins = "i2s_in_grp", "i2s_out_grp"; +- st,function = "i2s"; +- }; +- gmac { +- st,pins = "gmii_grp", "rgmii_grp"; +- st,function = "gmac"; +- }; +- cam0 { +- st,pins = "cam0_grp"; +- st,function = "cam0"; +- }; +- cam1 { +- st,pins = "cam1_grp"; +- st,function = "cam1"; +- }; +- cam2 { +- st,pins = "cam2_grp"; +- st,function = "cam2"; +- }; +- cam3 { +- st,pins = "cam3_grp"; +- st,function = "cam3"; +- }; +- cec0 { +- st,pins = "cec0_grp"; +- st,function = "cec0"; +- }; +- cec1 { +- st,pins = "cec1_grp"; +- st,function = "cec1"; +- }; +- sdhci { +- st,pins = "sdhci_grp"; +- st,function = "sdhci"; +- }; +- clcd { +- st,pins = "clcd_grp"; +- st,function = "clcd"; +- }; +- sata { +- st,pins = "sata_grp"; +- st,function = "sata"; +- }; +- pcie { +- st,pins = "pcie_grp"; +- st,function = "pcie"; +- }; +- +- }; +- }; +- +- ahci@b1000000 { +- status = "okay"; +- }; +- +- miphy@eb800000 { +- status = "okay"; +- }; +- +- dma@ea800000 { +- status = "okay"; +- }; +- +- dma@eb000000 { +- status = "okay"; +- }; +- +- fsmc: flash@b0000000 { +- status = "okay"; +- +- partition@0 { +- label = "xloader"; +- reg = <0x0 0x200000>; +- }; +- partition@200000 { +- label = "u-boot"; +- reg = <0x200000 0x200000>; +- }; +- partition@400000 { +- label = "environment"; +- reg = <0x400000 0x100000>; +- }; +- partition@500000 { +- label = "dtb"; +- reg = <0x500000 0x100000>; +- }; +- partition@600000 { +- label = "linux"; +- reg = <0x600000 0xC00000>; +- }; +- partition@1200000 { +- label = "rootfs"; +- reg = <0x1200000 0x0>; +- }; +- }; +- +- gmac0: eth@e2000000 { +- phy-mode = "rgmii"; +- status = "okay"; +- }; +- +- sdhci@b3000000 { +- status = "okay"; +- }; +- +- smi: flash@ea000000 { +- status = "okay"; +- clock-rate=<50000000>; +- +- flash@e6000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xe6000000 0x800000>; +- st,smi-fast-mode; +- +- partition@0 { +- label = "xloader"; +- reg = <0x0 0x10000>; +- }; +- partition@10000 { +- label = "u-boot"; +- reg = <0x10000 0x50000>; +- }; +- partition@60000 { +- label = "environment"; +- reg = <0x60000 0x10000>; +- }; +- partition@70000 { +- label = "dtb"; +- reg = <0x70000 0x10000>; +- }; +- partition@80000 { +- label = "linux"; +- reg = <0x80000 0x310000>; +- }; +- partition@390000 { +- label = "rootfs"; +- reg = <0x390000 0x0>; +- }; +- }; +- }; +- +- ehci@e4800000 { +- status = "okay"; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- button@1 { +- label = "wakeup"; +- linux,code = <0x100>; +- gpios = <&gpio1 1 0x4>; +- debounce-interval = <20>; +- wakeup-source; +- }; +- }; +- +- ehci@e5800000 { +- status = "okay"; +- }; +- +- i2s0: i2s-play@b2400000 { +- status = "okay"; +- }; +- +- i2s1: i2s-rec@b2000000 { +- status = "okay"; +- }; +- +- incodec: dir-hifi { +- compatible = "dummy,dir-hifi"; +- status = "okay"; +- }; +- +- ohci@e4000000 { +- status = "okay"; +- }; +- +- ohci@e5000000 { +- status = "okay"; +- }; +- +- outcodec: dit-hifi { +- compatible = "dummy,dit-hifi"; +- status = "okay"; +- }; +- +- sound { +- compatible = "spear,spear-evb"; +- audio-controllers = <&spdif0 &spdif1 &i2s0 &i2s1>; +- audio-codecs = <&incodec &outcodec &sta529 &sta529>; +- codec_dai_name = "dir-hifi", "dit-hifi", "sta529-audio", "sta529-audio"; +- stream_name = "spdif-cap", "spdif-play", "i2s-play", "i2s-cap"; +- dai_name = "spdifin-pcm", "spdifout-pcm", "i2s0-pcm", "i2s1-pcm"; +- nr_controllers = <4>; +- status = "okay"; +- }; +- +- spdif0: spdif-in@d0100000 { +- status = "okay"; +- }; +- +- spdif1: spdif-out@d0000000 { +- status = "okay"; +- }; +- +- apb { +- adc@e0080000 { +- status = "okay"; +- }; +- +- i2s-play@b2400000 { +- status = "okay"; +- }; +- +- i2s-rec@b2000000 { +- status = "okay"; +- }; +- +- gpio0: gpio@e0600000 { +- status = "okay"; +- }; +- +- gpio1: gpio@e0680000 { +- status = "okay"; +- }; +- +- gpio@e2800000 { +- status = "okay"; +- }; +- +- i2c0: i2c@e0280000 { +- status = "okay"; +- +- sta529: sta529@1a { +- compatible = "st,sta529"; +- reg = <0x1a>; +- }; +- }; +- +- i2c1: i2c@b4000000 { +- status = "okay"; +- +- eeprom0@56 { +- compatible = "st,eeprom"; +- reg = <0x56>; +- }; +- +- stmpe801@41 { +- compatible = "st,stmpe801"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x41>; +- interrupts = <4 0x4>; +- interrupt-parent = <&gpio0>; +- irq-trigger = <0x2>; +- +- stmpegpio: stmpe_gpio { +- compatible = "st,stmpe-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +- }; +- +- kbd@e0300000 { +- linux,keymap = < 0x00000001 +- 0x00010002 +- 0x00020003 +- 0x00030004 +- 0x00040005 +- 0x00050006 +- 0x00060007 +- 0x00070008 +- 0x00080009 +- 0x0100000a +- 0x0101000c +- 0x0102000d +- 0x0103000e +- 0x0104000f +- 0x01050010 +- 0x01060011 +- 0x01070012 +- 0x01080013 +- 0x02000014 +- 0x02010015 +- 0x02020016 +- 0x02030017 +- 0x02040018 +- 0x02050019 +- 0x0206001a +- 0x0207001b +- 0x0208001c +- 0x0300001d +- 0x0301001e +- 0x0302001f +- 0x03030020 +- 0x03040021 +- 0x03050022 +- 0x03060023 +- 0x03070024 +- 0x03080025 +- 0x04000026 +- 0x04010027 +- 0x04020028 +- 0x04030029 +- 0x0404002a +- 0x0405002b +- 0x0406002c +- 0x0407002d +- 0x0408002e +- 0x0500002f +- 0x05010030 +- 0x05020031 +- 0x05030032 +- 0x05040033 +- 0x05050034 +- 0x05060035 +- 0x05070036 +- 0x05080037 +- 0x06000038 +- 0x06010039 +- 0x0602003a +- 0x0603003b +- 0x0604003c +- 0x0605003d +- 0x0606003e +- 0x0607003f +- 0x06080040 +- 0x07000041 +- 0x07010042 +- 0x07020043 +- 0x07030044 +- 0x07040045 +- 0x07050046 +- 0x07060047 +- 0x07070048 +- 0x07080049 +- 0x0800004a +- 0x0801004b +- 0x0802004c +- 0x0803004d +- 0x0804004e +- 0x0805004f +- 0x08060050 +- 0x08070051 +- 0x08080052 >; +- autorepeat; +- st,mode = <0>; +- suspended_rate = <2000000>; +- status = "okay"; +- }; +- +- rtc@e0580000 { +- status = "okay"; +- }; +- +- serial@e0000000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <>; +- }; +- +- serial@b4100000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <>; +- }; +- +- spi0: spi@e0100000 { +- status = "okay"; +- num-cs = <3>; +- cs-gpios = <&gpiopinctrl 80 0>, <&gpiopinctrl 24 0>, +- <&gpiopinctrl 85 0>; +- +- m25p80@0 { +- compatible = "m25p80"; +- reg = <0>; +- spi-max-frequency = <12000000>; +- spi-cpol; +- spi-cpha; +- pl022,hierarchy = <0>; +- pl022,interface = <0>; +- pl022,slave-tx-disable; +- pl022,com-mode = <0x2>; +- pl022,rx-level-trig = <0>; +- pl022,tx-level-trig = <0>; +- pl022,ctrl-len = <0x11>; +- pl022,wait-state = <0>; +- pl022,duplex = <0>; +- }; +- +- stmpe610@1 { +- compatible = "st,stmpe610"; +- spi-max-frequency = <1000000>; +- spi-cpha; +- reg = <1>; +- pl022,hierarchy = <0>; +- pl022,interface = <0>; +- pl022,slave-tx-disable; +- pl022,com-mode = <0>; +- pl022,rx-level-trig = <0>; +- pl022,tx-level-trig = <0>; +- pl022,ctrl-len = <0x7>; +- pl022,wait-state = <0>; +- pl022,duplex = <0>; +- interrupts = <100 0>; +- interrupt-parent = <&gpiopinctrl>; +- irq-trigger = <0x2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- stmpe_touchscreen { +- compatible = "st,stmpe-ts"; +- ts,sample-time = <4>; +- ts,mod-12b = <1>; +- ts,ref-sel = <0>; +- ts,adc-freq = <1>; +- ts,ave-ctrl = <1>; +- ts,touch-det-delay = <2>; +- ts,settling = <2>; +- ts,fraction-z = <7>; +- ts,i-drive = <1>; +- }; +- }; +- +- spidev@2 { +- compatible = "spidev"; +- reg = <2>; +- spi-max-frequency = <25000000>; +- spi-cpha; +- pl022,hierarchy = <0>; +- pl022,interface = <0>; +- pl022,slave-tx-disable; +- pl022,com-mode = <0x2>; +- pl022,rx-level-trig = <0>; +- pl022,tx-level-trig = <0>; +- pl022,ctrl-len = <0x11>; +- pl022,wait-state = <0>; +- pl022,duplex = <0>; +- }; +- }; +- +- timer@ec800600 { +- status = "okay"; +- }; +- +- wdt@ec800620 { +- status = "okay"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/spear1340.dtsi b/scripts/dtc/include-prefixes/arm/spear1340.dtsi +deleted file mode 100644 +index 1a8f5e8b10e3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/spear1340.dtsi ++++ /dev/null +@@ -1,169 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * DTS file for all SPEAr1340 SoCs +- * +- * Copyright 2012 Viresh Kumar +- */ +- +-/include/ "spear13xx.dtsi" +- +-/ { +- compatible = "st,spear1340"; +- +- ahb { +- +- spics: spics@e0700000{ +- compatible = "st,spear-spics-gpio"; +- reg = <0xe0700000 0x1000>; +- st-spics,peripcfg-reg = <0x42c>; +- st-spics,sw-enable-bit = <21>; +- st-spics,cs-value-bit = <20>; +- st-spics,cs-enable-mask = <3>; +- st-spics,cs-enable-shift = <18>; +- gpio-controller; +- #gpio-cells = <2>; +- status = "disabled"; +- }; +- +- miphy0: miphy@eb800000 { +- compatible = "st,spear1340-miphy"; +- reg = <0xeb800000 0x4000>; +- misc = <&misc>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- ahci0: ahci@b1000000 { +- compatible = "snps,spear-ahci"; +- reg = <0xb1000000 0x10000>; +- interrupts = <0 72 0x4>; +- phys = <&miphy0 0>; +- phy-names = "sata-phy"; +- status = "disabled"; +- }; +- +- pcie0: pcie@b1000000 { +- compatible = "st,spear1340-pcie", "snps,dw-pcie"; +- reg = <0xb1000000 0x4000>, <0x80000000 0x20000>; +- reg-names = "dbi", "config"; +- interrupts = <0 68 0x4>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0x0 0 &gic 0 68 0x4>; +- num-lanes = <1>; +- phys = <&miphy0 1>; +- phy-names = "pcie-phy"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ +- 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ +- bus-range = <0x00 0xff>; +- status = "disabled"; +- }; +- +- i2s-play@b2400000 { +- compatible = "snps,designware-i2s"; +- reg = <0xb2400000 0x10000>; +- interrupt-names = "play_irq"; +- interrupts = <0 98 0x4 +- 0 99 0x4>; +- play; +- channel = <8>; +- status = "disabled"; +- }; +- +- i2s-rec@b2000000 { +- compatible = "snps,designware-i2s"; +- reg = <0xb2000000 0x10000>; +- interrupt-names = "record_irq"; +- interrupts = <0 100 0x4 +- 0 101 0x4>; +- record; +- channel = <8>; +- status = "disabled"; +- }; +- +- pinmux: pinmux@e0700000 { +- compatible = "st,spear1340-pinmux"; +- reg = <0xe0700000 0x1000>; +- #gpio-range-cells = <3>; +- }; +- +- pwm: pwm@e0180000 { +- compatible ="st,spear13xx-pwm"; +- reg = <0xe0180000 0x1000>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- spdif-in@d0100000 { +- compatible = "st,spdif-in"; +- reg = < 0xd0100000 0x20000 +- 0xd0110000 0x10000 >; +- interrupts = <0 84 0x4>; +- status = "disabled"; +- }; +- +- spdif-out@d0000000 { +- compatible = "st,spdif-out"; +- reg = <0xd0000000 0x20000>; +- interrupts = <0 85 0x4>; +- status = "disabled"; +- }; +- +- spi1: spi@5d400000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x5d400000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 99 0x4>; +- status = "disabled"; +- }; +- +- apb { +- i2c1: i2c@b4000000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xb4000000 0x1000>; +- interrupts = <0 104 0x4>; +- write-16bit; +- status = "disabled"; +- }; +- +- serial@b4100000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xb4100000 0x1000>; +- interrupts = <0 105 0x4>; +- status = "disabled"; +- dmas = <&dwdma0 12 0 1>, +- <&dwdma0 13 1 0>; +- dma-names = "tx", "rx"; +- }; +- +- thermal@e07008c4 { +- st,thermal-flags = <0x2a00>; +- }; +- +- gpiopinctrl: gpio@e2800000 { +- compatible = "st,spear-plgpio"; +- reg = <0xe2800000 0x1000>; +- interrupts = <0 107 0x4>; +- #interrupt-cells = <1>; +- interrupt-controller; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinmux 0 0 252>; +- status = "disabled"; +- +- st-plgpio,ngpio = <250>; +- st-plgpio,wdata-reg = <0x40>; +- st-plgpio,dir-reg = <0x00>; +- st-plgpio,ie-reg = <0x80>; +- st-plgpio,rdata-reg = <0x20>; +- st-plgpio,mis-reg = <0xa0>; +- st-plgpio,eit-reg = <0x60>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/spear13xx.dtsi b/scripts/dtc/include-prefixes/arm/spear13xx.dtsi +deleted file mode 100644 +index c87b881b2c8b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/spear13xx.dtsi ++++ /dev/null +@@ -1,339 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * DTS file for all SPEAr13xx SoCs +- * +- * Copyright 2012 Viresh Kumar +- */ +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&gic>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <0>; +- next-level-cache = <&L2>; +- }; +- +- cpu@1 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <1>; +- next-level-cache = <&L2>; +- }; +- }; +- +- gic: interrupt-controller@ec801000 { +- compatible = "arm,cortex-a9-gic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = < 0xec801000 0x1000 >, +- < 0xec800100 0x0100 >; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = <0 6 0x04 +- 0 7 0x04>; +- }; +- +- L2: cache-controller { +- compatible = "arm,pl310-cache"; +- reg = <0xed000000 0x1000>; +- cache-unified; +- cache-level = <2>; +- }; +- +- memory { +- name = "memory"; +- device_type = "memory"; +- reg = <0 0x40000000>; +- }; +- +- chosen { +- bootargs = "console=ttyAMA0,115200"; +- }; +- +- cpufreq { +- compatible = "st,cpufreq-spear"; +- cpufreq_tbl = < 166000 +- 200000 +- 250000 +- 300000 +- 400000 +- 500000 +- 600000 >; +- status = "disabled"; +- }; +- +- ahb { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0x50000000 0x50000000 0x10000000 +- 0x80000000 0x80000000 0x20000000 +- 0xb0000000 0xb0000000 0x22000000 +- 0xd8000000 0xd8000000 0x01000000 +- 0xe0000000 0xe0000000 0x10000000>; +- +- sdhci@b3000000 { +- compatible = "st,sdhci-spear"; +- reg = <0xb3000000 0x100>; +- interrupts = <0 28 0x4>; +- status = "disabled"; +- }; +- +- cf@b2800000 { +- compatible = "arasan,cf-spear1340"; +- reg = <0xb2800000 0x1000>; +- interrupts = <0 29 0x4>; +- status = "disabled"; +- dmas = <&dwdma0 0 0 0>; +- dma-names = "data"; +- }; +- +- dwdma0: dma@ea800000 { +- compatible = "snps,dma-spear1340"; +- reg = <0xea800000 0x1000>; +- interrupts = <0 19 0x4>; +- status = "disabled"; +- +- dma-channels = <8>; +- #dma-cells = <3>; +- dma-requests = <32>; +- chan_allocation_order = <1>; +- chan_priority = <1>; +- block_size = <0xfff>; +- dma-masters = <2>; +- data-width = <8 8>; +- multi-block = <1 1 1 1 1 1 1 1>; +- }; +- +- dma@eb000000 { +- compatible = "snps,dma-spear1340"; +- reg = <0xeb000000 0x1000>; +- interrupts = <0 59 0x4>; +- status = "disabled"; +- +- dma-requests = <32>; +- dma-channels = <8>; +- dma-masters = <2>; +- #dma-cells = <3>; +- chan_allocation_order = <1>; +- chan_priority = <1>; +- block_size = <0xfff>; +- data-width = <8 8>; +- multi-block = <1 1 1 1 1 1 1 1>; +- }; +- +- fsmc: flash@b0000000 { +- compatible = "st,spear600-fsmc-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xb0000000 0x1000 /* FSMC Register*/ +- 0xb0800000 0x0010 /* NAND Base DATA */ +- 0xb0820000 0x0010 /* NAND Base ADDR */ +- 0xb0810000 0x0010>; /* NAND Base CMD */ +- reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; +- interrupts = <0 20 0x4 +- 0 21 0x4 +- 0 22 0x4 +- 0 23 0x4>; +- st,mode = <2>; +- status = "disabled"; +- }; +- +- gmac0: eth@e2000000 { +- compatible = "st,spear600-gmac"; +- reg = <0xe2000000 0x8000>; +- interrupts = <0 33 0x4 +- 0 34 0x4>; +- interrupt-names = "macirq", "eth_wake_irq"; +- status = "disabled"; +- }; +- +- pcm { +- compatible = "st,pcm-audio"; +- #address-cells = <0>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- smi: flash@ea000000 { +- compatible = "st,spear600-smi"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xea000000 0x1000>; +- interrupts = <0 30 0x4>; +- status = "disabled"; +- }; +- +- ehci@e4800000 { +- compatible = "st,spear600-ehci", "usb-ehci"; +- reg = <0xe4800000 0x1000>; +- interrupts = <0 64 0x4>; +- usbh0_id = <0>; +- status = "disabled"; +- }; +- +- ehci@e5800000 { +- compatible = "st,spear600-ehci", "usb-ehci"; +- reg = <0xe5800000 0x1000>; +- interrupts = <0 66 0x4>; +- usbh1_id = <1>; +- status = "disabled"; +- }; +- +- ohci@e4000000 { +- compatible = "st,spear600-ohci", "usb-ohci"; +- reg = <0xe4000000 0x1000>; +- interrupts = <0 65 0x4>; +- usbh0_id = <0>; +- status = "disabled"; +- }; +- +- ohci@e5000000 { +- compatible = "st,spear600-ohci", "usb-ohci"; +- reg = <0xe5000000 0x1000>; +- interrupts = <0 67 0x4>; +- usbh1_id = <1>; +- status = "disabled"; +- }; +- +- apb { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0x50000000 0x50000000 0x10000000 +- 0xb0000000 0xb0000000 0x10000000 +- 0xd0000000 0xd0000000 0x02000000 +- 0xd8000000 0xd8000000 0x01000000 +- 0xe0000000 0xe0000000 0x10000000>; +- +- misc: syscon@e0700000 { +- compatible = "st,spear1340-misc", "syscon"; +- reg = <0xe0700000 0x1000>; +- }; +- +- gpio0: gpio@e0600000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xe0600000 0x1000>; +- interrupts = <0 24 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- gpio1: gpio@e0680000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xe0680000 0x1000>; +- interrupts = <0 25 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- kbd@e0300000 { +- compatible = "st,spear300-kbd"; +- reg = <0xe0300000 0x1000>; +- interrupts = <0 52 0x4>; +- status = "disabled"; +- }; +- +- i2c0: i2c@e0280000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xe0280000 0x1000>; +- interrupts = <0 41 0x4>; +- status = "disabled"; +- }; +- +- i2s@e0180000 { +- compatible = "st,designware-i2s"; +- reg = <0xe0180000 0x1000>; +- interrupt-names = "play_irq", "record_irq"; +- interrupts = <0 10 0x4 +- 0 11 0x4 >; +- status = "disabled"; +- }; +- +- i2s@e0200000 { +- compatible = "st,designware-i2s"; +- reg = <0xe0200000 0x1000>; +- interrupt-names = "play_irq", "record_irq"; +- interrupts = <0 26 0x4 +- 0 53 0x4>; +- status = "disabled"; +- }; +- +- spi0: spi@e0100000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0xe0100000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 31 0x4>; +- status = "disabled"; +- dmas = <&dwdma0 4 0 0>, +- <&dwdma0 5 0 0>; +- dma-names = "tx", "rx"; +- }; +- +- rtc@e0580000 { +- compatible = "st,spear600-rtc"; +- reg = <0xe0580000 0x1000>; +- interrupts = <0 36 0x4>; +- status = "disabled"; +- }; +- +- serial@e0000000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xe0000000 0x1000>; +- interrupts = <0 35 0x4>; +- status = "disabled"; +- }; +- +- adc@e0080000 { +- compatible = "st,spear600-adc"; +- reg = <0xe0080000 0x1000>; +- interrupts = <0 12 0x4>; +- status = "disabled"; +- }; +- +- timer@e0380000 { +- compatible = "st,spear-timer"; +- reg = <0xe0380000 0x400>; +- interrupts = <0 37 0x4>; +- }; +- +- timer@ec800600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0xec800600 0x20>; +- interrupts = <1 13 0x4>; +- status = "disabled"; +- }; +- +- wdt@ec800620 { +- compatible = "arm,cortex-a9-twd-wdt"; +- reg = <0xec800620 0x20>; +- status = "disabled"; +- }; +- +- thermal@e07008c4 { +- compatible = "st,thermal-spear1340"; +- reg = <0xe07008c4 0x4>; +- thermal_flags = <0x7000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/spear300-evb.dts b/scripts/dtc/include-prefixes/arm/spear300-evb.dts +deleted file mode 100644 +index 2beb30ca2cba..000000000000 +--- a/scripts/dtc/include-prefixes/arm/spear300-evb.dts ++++ /dev/null +@@ -1,249 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * DTS file for SPEAr300 Evaluation Baord +- * +- * Copyright 2012 Viresh Kumar +- */ +- +-/dts-v1/; +-/include/ "spear300.dtsi" +- +-/ { +- model = "ST SPEAr300 Evaluation Board"; +- compatible = "st,spear300-evb", "st,spear300"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory { +- reg = <0 0x40000000>; +- }; +- +- ahb { +- pinmux@99000000 { +- st,pinmux-mode = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- i2c0 { +- st,pins = "i2c0_grp"; +- st,function = "i2c0"; +- }; +- ssp0 { +- st,pins = "ssp0_grp"; +- st,function = "ssp0"; +- }; +- mii0 { +- st,pins = "mii0_grp"; +- st,function = "mii0"; +- }; +- uart0 { +- st,pins = "uart0_grp"; +- st,function = "uart0"; +- }; +- clcd { +- st,pins = "clcd_pfmode_grp"; +- st,function = "clcd"; +- }; +- sdhci { +- st,pins = "sdhci_4bit_grp"; +- st,function = "sdhci"; +- }; +- gpio1 { +- st,pins = "gpio1_4_to_7_grp", +- "gpio1_0_to_3_grp"; +- st,function = "gpio1"; +- }; +- }; +- }; +- +- clcd@60000000 { +- status = "okay"; +- }; +- +- dma@fc400000 { +- status = "okay"; +- }; +- +- fsmc: flash@94000000 { +- status = "okay"; +- }; +- +- gmac: eth@e0800000 { +- status = "okay"; +- }; +- +- sdhci@70000000 { +- cd-gpios = <&gpio1 0 0>; +- status = "okay"; +- }; +- +- smi: flash@fc000000 { +- status = "okay"; +- clock-rate=<50000000>; +- +- flash@f8000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xf8000000 0x800000>; +- st,smi-fast-mode; +- +- partition@0 { +- label = "xloader"; +- reg = <0x0 0x10000>; +- }; +- partition@10000 { +- label = "u-boot"; +- reg = <0x10000 0x50000>; +- }; +- partition@60000 { +- label = "environment"; +- reg = <0x60000 0x10000>; +- }; +- partition@70000 { +- label = "dtb"; +- reg = <0x70000 0x10000>; +- }; +- partition@80000 { +- label = "linux"; +- reg = <0x80000 0x310000>; +- }; +- partition@390000 { +- label = "rootfs"; +- reg = <0x390000 0x0>; +- }; +- }; +- }; +- +- spi0: spi@d0100000 { +- status = "okay"; +- }; +- +- ehci@e1800000 { +- status = "okay"; +- }; +- +- ohci@e1900000 { +- status = "okay"; +- }; +- +- ohci@e2100000 { +- status = "okay"; +- }; +- +- apb { +- gpio0: gpio@fc980000 { +- status = "okay"; +- }; +- +- gpio1: gpio@a9000000 { +- status = "okay"; +- }; +- +- i2c0: i2c@d0180000 { +- status = "okay"; +- }; +- +- kbd@a0000000 { +- linux,keymap = < 0x00000001 +- 0x00010002 +- 0x00020003 +- 0x00030004 +- 0x00040005 +- 0x00050006 +- 0x00060007 +- 0x00070008 +- 0x00080009 +- 0x0100000a +- 0x0101000c +- 0x0102000d +- 0x0103000e +- 0x0104000f +- 0x01050010 +- 0x01060011 +- 0x01070012 +- 0x01080013 +- 0x02000014 +- 0x02010015 +- 0x02020016 +- 0x02030017 +- 0x02040018 +- 0x02050019 +- 0x0206001a +- 0x0207001b +- 0x0208001c +- 0x0300001d +- 0x0301001e +- 0x0302001f +- 0x03030020 +- 0x03040021 +- 0x03050022 +- 0x03060023 +- 0x03070024 +- 0x03080025 +- 0x04000026 +- 0x04010027 +- 0x04020028 +- 0x04030029 +- 0x0404002a +- 0x0405002b +- 0x0406002c +- 0x0407002d +- 0x0408002e +- 0x0500002f +- 0x05010030 +- 0x05020031 +- 0x05030032 +- 0x05040033 +- 0x05050034 +- 0x05060035 +- 0x05070036 +- 0x05080037 +- 0x06000038 +- 0x06010039 +- 0x0602003a +- 0x0603003b +- 0x0604003c +- 0x0605003d +- 0x0606003e +- 0x0607003f +- 0x06080040 +- 0x07000041 +- 0x07010042 +- 0x07020043 +- 0x07030044 +- 0x07040045 +- 0x07050046 +- 0x07060047 +- 0x07070048 +- 0x07080049 +- 0x0800004a +- 0x0801004b +- 0x0802004c +- 0x0803004d +- 0x0804004e +- 0x0805004f +- 0x08060050 +- 0x08070051 +- 0x08080052 >; +- autorepeat; +- st,mode = <0>; +- status = "okay"; +- }; +- +- rtc@fc900000 { +- status = "okay"; +- }; +- +- serial@d0000000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <>; +- }; +- +- wdt@fc880000 { +- status = "okay"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/spear300.dtsi b/scripts/dtc/include-prefixes/arm/spear300.dtsi +deleted file mode 100644 +index b39bd5a22627..000000000000 +--- a/scripts/dtc/include-prefixes/arm/spear300.dtsi ++++ /dev/null +@@ -1,83 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * DTS file for SPEAr300 SoC +- * +- * Copyright 2012 Viresh Kumar +- */ +- +-/include/ "spear3xx.dtsi" +- +-/ { +- ahb { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0x60000000 0x60000000 0x50000000 +- 0xd0000000 0xd0000000 0x30000000>; +- +- pinmux@99000000 { +- compatible = "st,spear300-pinmux"; +- reg = <0x99000000 0x1000>; +- }; +- +- clcd@60000000 { +- compatible = "arm,pl110", "arm,primecell"; +- reg = <0x60000000 0x1000>; +- interrupts = <30>; +- status = "disabled"; +- }; +- +- fsmc: flash@94000000 { +- compatible = "st,spear600-fsmc-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x94000000 0x1000 /* FSMC Register */ +- 0x80000000 0x0010 /* NAND Base DATA */ +- 0x80020000 0x0010 /* NAND Base ADDR */ +- 0x80010000 0x0010>; /* NAND Base CMD */ +- reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; +- status = "disabled"; +- }; +- +- sdhci@70000000 { +- compatible = "st,sdhci-spear"; +- reg = <0x70000000 0x100>; +- interrupts = <1>; +- status = "disabled"; +- }; +- +- shirq: interrupt-controller@0x50000000 { +- compatible = "st,spear300-shirq"; +- reg = <0x50000000 0x1000>; +- interrupts = <28>; +- #interrupt-cells = <1>; +- interrupt-controller; +- }; +- +- apb { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0xa0000000 0xa0000000 0x10000000 +- 0xd0000000 0xd0000000 0x30000000>; +- +- gpio1: gpio@a9000000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0xa9000000 0x1000>; +- interrupts = <8>; +- interrupt-parent = <&shirq>; +- status = "disabled"; +- }; +- +- kbd@a0000000 { +- compatible = "st,spear300-kbd"; +- reg = <0xa0000000 0x1000>; +- interrupts = <7>; +- interrupt-parent = <&shirq>; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/spear310-evb.dts b/scripts/dtc/include-prefixes/arm/spear310-evb.dts +deleted file mode 100644 +index 1c41e4a40334..000000000000 +--- a/scripts/dtc/include-prefixes/arm/spear310-evb.dts ++++ /dev/null +@@ -1,202 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * DTS file for SPEAr310 Evaluation Baord +- * +- * Copyright 2012 Viresh Kumar +- */ +- +-/dts-v1/; +-/include/ "spear310.dtsi" +- +-/ { +- model = "ST SPEAr310 Evaluation Board"; +- compatible = "st,spear310-evb", "st,spear310"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory { +- reg = <0 0x40000000>; +- }; +- +- ahb { +- pinmux@b4000000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- gpio0 { +- st,pins = "gpio0_pin0_grp", +- "gpio0_pin1_grp", +- "gpio0_pin2_grp", +- "gpio0_pin3_grp", +- "gpio0_pin4_grp", +- "gpio0_pin5_grp"; +- st,function = "gpio0"; +- }; +- i2c0 { +- st,pins = "i2c0_grp"; +- st,function = "i2c0"; +- }; +- mii0 { +- st,pins = "mii0_grp"; +- st,function = "mii0"; +- }; +- ssp0 { +- st,pins = "ssp0_grp"; +- st,function = "ssp0"; +- }; +- uart0 { +- st,pins = "uart0_grp"; +- st,function = "uart0"; +- }; +- emi { +- st,pins = "emi_cs_0_to_5_grp"; +- st,function = "emi"; +- }; +- fsmc { +- st,pins = "fsmc_grp"; +- st,function = "fsmc"; +- }; +- uart1 { +- st,pins = "uart1_grp"; +- st,function = "uart1"; +- }; +- uart2 { +- st,pins = "uart2_grp"; +- st,function = "uart2"; +- }; +- uart3 { +- st,pins = "uart3_grp"; +- st,function = "uart3"; +- }; +- uart4 { +- st,pins = "uart4_grp"; +- st,function = "uart4"; +- }; +- uart5 { +- st,pins = "uart5_grp"; +- st,function = "uart5"; +- }; +- }; +- }; +- +- dma@fc400000 { +- status = "okay"; +- }; +- +- fsmc: flash@44000000 { +- status = "okay"; +- }; +- +- gmac: eth@e0800000 { +- status = "okay"; +- }; +- +- smi: flash@fc000000 { +- status = "okay"; +- clock-rate=<50000000>; +- +- flash@f8000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xf8000000 0x800000>; +- st,smi-fast-mode; +- +- partition@0 { +- label = "xloader"; +- reg = <0x0 0x10000>; +- }; +- partition@10000 { +- label = "u-boot"; +- reg = <0x10000 0x50000>; +- }; +- partition@60000 { +- label = "environment"; +- reg = <0x60000 0x10000>; +- }; +- partition@70000 { +- label = "dtb"; +- reg = <0x70000 0x10000>; +- }; +- partition@80000 { +- label = "linux"; +- reg = <0x80000 0x310000>; +- }; +- partition@390000 { +- label = "rootfs"; +- reg = <0x390000 0x0>; +- }; +- }; +- }; +- +- spi0: spi@d0100000 { +- status = "okay"; +- }; +- +- ehci@e1800000 { +- status = "okay"; +- }; +- +- ohci@e1900000 { +- status = "okay"; +- }; +- +- ohci@e2100000 { +- status = "okay"; +- }; +- +- apb { +- gpio0: gpio@fc980000 { +- status = "okay"; +- }; +- +- i2c0: i2c@d0180000 { +- status = "okay"; +- }; +- +- rtc@fc900000 { +- status = "okay"; +- }; +- +- serial@d0000000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <>; +- }; +- +- serial@b2000000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <>; +- }; +- +- serial@b2080000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <>; +- }; +- +- serial@b2100000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <>; +- }; +- +- serial@b2180000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <>; +- }; +- +- serial@b2200000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <>; +- }; +- +- wdt@fc880000 { +- status = "okay"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/spear310.dtsi b/scripts/dtc/include-prefixes/arm/spear310.dtsi +deleted file mode 100644 +index 8ce751a1376d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/spear310.dtsi ++++ /dev/null +@@ -1,112 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * DTS file for SPEAr310 SoC +- * +- * Copyright 2012 Viresh Kumar +- */ +- +-/include/ "spear3xx.dtsi" +- +-/ { +- ahb { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0x40000000 0x40000000 0x10000000 +- 0xb0000000 0xb0000000 0x10000000 +- 0xd0000000 0xd0000000 0x30000000>; +- +- pinmux: pinmux@b4000000 { +- compatible = "st,spear310-pinmux"; +- reg = <0xb4000000 0x1000>; +- #gpio-range-cells = <3>; +- }; +- +- fsmc: flash@44000000 { +- compatible = "st,spear600-fsmc-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x44000000 0x1000 /* FSMC Register */ +- 0x40000000 0x0010 /* NAND Base DATA */ +- 0x40020000 0x0010 /* NAND Base ADDR */ +- 0x40010000 0x0010>; /* NAND Base CMD */ +- reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; +- status = "disabled"; +- }; +- +- shirq: interrupt-controller@0xb4000000 { +- compatible = "st,spear310-shirq"; +- reg = <0xb4000000 0x1000>; +- interrupts = <28 29 30 1>; +- #interrupt-cells = <1>; +- interrupt-controller; +- }; +- +- apb { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0xb0000000 0xb0000000 0x10000000 +- 0xd0000000 0xd0000000 0x30000000>; +- +- serial@b2000000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xb2000000 0x1000>; +- interrupts = <8>; +- interrupt-parent = <&shirq>; +- status = "disabled"; +- }; +- +- serial@b2080000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xb2080000 0x1000>; +- interrupts = <9>; +- interrupt-parent = <&shirq>; +- status = "disabled"; +- }; +- +- serial@b2100000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xb2100000 0x1000>; +- interrupts = <10>; +- interrupt-parent = <&shirq>; +- status = "disabled"; +- }; +- +- serial@b2180000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xb2180000 0x1000>; +- interrupts = <11>; +- interrupt-parent = <&shirq>; +- status = "disabled"; +- }; +- +- serial@b2200000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xb2200000 0x1000>; +- interrupts = <12>; +- interrupt-parent = <&shirq>; +- status = "disabled"; +- }; +- +- gpiopinctrl: gpio@b4000000 { +- compatible = "st,spear-plgpio"; +- reg = <0xb4000000 0x1000>; +- #interrupt-cells = <1>; +- interrupt-controller; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinmux 0 0 102>; +- status = "disabled"; +- +- st-plgpio,ngpio = <102>; +- st-plgpio,enb-reg = <0x10>; +- st-plgpio,wdata-reg = <0x20>; +- st-plgpio,dir-reg = <0x30>; +- st-plgpio,ie-reg = <0x50>; +- st-plgpio,rdata-reg = <0x40>; +- st-plgpio,mis-reg = <0x60>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/spear320-evb.dts b/scripts/dtc/include-prefixes/arm/spear320-evb.dts +deleted file mode 100644 +index c322407a0ade..000000000000 +--- a/scripts/dtc/include-prefixes/arm/spear320-evb.dts ++++ /dev/null +@@ -1,201 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * DTS file for SPEAr320 Evaluation Baord +- * +- * Copyright 2012 Viresh Kumar +- */ +- +-/dts-v1/; +-/include/ "spear320.dtsi" +- +-/ { +- model = "ST SPEAr320 Evaluation Board"; +- compatible = "st,spear320-evb", "st,spear320"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory { +- reg = <0 0x40000000>; +- }; +- +- ahb { +- pinmux@b3000000 { +- st,pinmux-mode = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- i2c0 { +- st,pins = "i2c0_grp"; +- st,function = "i2c0"; +- }; +- mii0 { +- st,pins = "mii0_grp"; +- st,function = "mii0"; +- }; +- ssp0 { +- st,pins = "ssp0_grp"; +- st,function = "ssp0"; +- }; +- uart0 { +- st,pins = "uart0_grp"; +- st,function = "uart0"; +- }; +- sdhci { +- st,pins = "sdhci_cd_51_grp"; +- st,function = "sdhci"; +- }; +- i2s { +- st,pins = "i2s_grp"; +- st,function = "i2s"; +- }; +- uart1 { +- st,pins = "uart1_grp"; +- st,function = "uart1"; +- }; +- uart2 { +- st,pins = "uart2_grp"; +- st,function = "uart2"; +- }; +- can0 { +- st,pins = "can0_grp"; +- st,function = "can0"; +- }; +- can1 { +- st,pins = "can1_grp"; +- st,function = "can1"; +- }; +- mii2 { +- st,pins = "mii2_grp"; +- st,function = "mii2"; +- }; +- pwm0_1 { +- st,pins = "pwm0_1_pin_37_38_grp"; +- st,function = "pwm0_1"; +- }; +- }; +- }; +- +- dma@fc400000 { +- status = "okay"; +- }; +- +- fsmc: flash@4c000000 { +- status = "okay"; +- }; +- +- gmac: eth@e0800000 { +- status = "okay"; +- }; +- +- sdhci@70000000 { +- power-gpio = <&gpiopinctrl 61 1>; +- status = "okay"; +- }; +- +- smi: flash@fc000000 { +- status = "okay"; +- clock-rate=<50000000>; +- +- flash@f8000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xf8000000 0x800000>; +- st,smi-fast-mode; +- +- partition@0 { +- label = "xloader"; +- reg = <0x0 0x10000>; +- }; +- partition@10000 { +- label = "u-boot"; +- reg = <0x10000 0x50000>; +- }; +- partition@60000 { +- label = "environment"; +- reg = <0x60000 0x10000>; +- }; +- partition@70000 { +- label = "dtb"; +- reg = <0x70000 0x10000>; +- }; +- partition@80000 { +- label = "linux"; +- reg = <0x80000 0x310000>; +- }; +- partition@390000 { +- label = "rootfs"; +- reg = <0x390000 0x0>; +- }; +- }; +- }; +- +- spi0: spi@d0100000 { +- status = "okay"; +- }; +- +- spi1: spi@a5000000 { +- status = "okay"; +- }; +- +- spi2: spi@a6000000 { +- status = "okay"; +- }; +- +- ehci@e1800000 { +- status = "okay"; +- }; +- +- ohci@e1900000 { +- status = "okay"; +- }; +- +- ohci@e2100000 { +- status = "okay"; +- }; +- +- apb { +- gpio0: gpio@fc980000 { +- status = "okay"; +- }; +- +- gpio@b3000000 { +- status = "okay"; +- }; +- +- i2c0: i2c@d0180000 { +- status = "okay"; +- }; +- +- i2c1: i2c@a7000000 { +- status = "okay"; +- }; +- +- rtc@fc900000 { +- status = "okay"; +- }; +- +- serial@d0000000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <>; +- }; +- +- serial@a3000000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <>; +- }; +- +- serial@a4000000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <>; +- }; +- +- wdt@fc880000 { +- status = "okay"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/spear320-hmi.dts b/scripts/dtc/include-prefixes/arm/spear320-hmi.dts +deleted file mode 100644 +index 367ba48aac3e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/spear320-hmi.dts ++++ /dev/null +@@ -1,299 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * DTS file for SPEAr320 Evaluation Baord +- * +- * Copyright 2012 Shiraz Hashim +- */ +- +-/dts-v1/; +-/include/ "spear320.dtsi" +- +-/ { +- model = "ST SPEAr320 HMI Board"; +- compatible = "st,spear320-hmi", "st,spear320"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory { +- reg = <0 0x40000000>; +- }; +- +- ahb { +- pinmux@b3000000 { +- st,pinmux-mode = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- i2c0 { +- st,pins = "i2c0_grp"; +- st,function = "i2c0"; +- }; +- ssp0 { +- st,pins = "ssp0_grp"; +- st,function = "ssp0"; +- }; +- uart0 { +- st,pins = "uart0_grp"; +- st,function = "uart0"; +- }; +- clcd { +- st,pins = "clcd_grp"; +- st,function = "clcd"; +- }; +- fsmc { +- st,pins = "fsmc_8bit_grp"; +- st,function = "fsmc"; +- }; +- sdhci { +- st,pins = "sdhci_cd_12_grp"; +- st,function = "sdhci"; +- }; +- i2s { +- st,pins = "i2s_grp"; +- st,function = "i2s"; +- }; +- uart1 { +- st,pins = "uart1_grp"; +- st,function = "uart1"; +- }; +- uart2 { +- st,pins = "uart2_grp"; +- st,function = "uart2"; +- }; +- can0 { +- st,pins = "can0_grp"; +- st,function = "can0"; +- }; +- can1 { +- st,pins = "can1_grp"; +- st,function = "can1"; +- }; +- mii0_1 { +- st,pins = "rmii0_1_grp"; +- st,function = "mii0_1"; +- }; +- pwm0_1 { +- st,pins = "pwm0_1_pin_37_38_grp"; +- st,function = "pwm0_1"; +- }; +- pwm2 { +- st,pins = "pwm2_pin_34_grp"; +- st,function = "pwm2"; +- }; +- }; +- }; +- +- clcd@90000000 { +- status = "okay"; +- }; +- +- dma@fc400000 { +- status = "okay"; +- }; +- +- ehci@e1800000 { +- status = "okay"; +- }; +- +- fsmc: flash@4c000000 { +- status = "okay"; +- +- partition@0 { +- label = "xloader"; +- reg = <0x0 0x80000>; +- }; +- partition@80000 { +- label = "u-boot"; +- reg = <0x80000 0x140000>; +- }; +- partition@1C0000 { +- label = "environment"; +- reg = <0x1C0000 0x40000>; +- }; +- partition@200000 { +- label = "dtb"; +- reg = <0x200000 0x40000>; +- }; +- partition@240000 { +- label = "linux"; +- reg = <0x240000 0xC00000>; +- }; +- partition@E40000 { +- label = "rootfs"; +- reg = <0xE40000 0x0>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- button@1 { +- label = "user button 1"; +- linux,code = <0x100>; +- gpios = <&stmpegpio 3 0x4>; +- debounce-interval = <20>; +- wakeup-source; +- }; +- +- button@2 { +- label = "user button 2"; +- linux,code = <0x200>; +- gpios = <&stmpegpio 2 0x4>; +- debounce-interval = <20>; +- wakeup-source; +- }; +- }; +- +- ohci@e1900000 { +- status = "okay"; +- }; +- +- ohci@e2100000 { +- status = "okay"; +- }; +- +- pwm: pwm@a8000000 { +- status = "okay"; +- }; +- +- sdhci@70000000 { +- power-gpio = <&gpiopinctrl 50 1>; +- power_always_enb; +- status = "okay"; +- }; +- +- smi: flash@fc000000 { +- status = "okay"; +- clock-rate=<50000000>; +- +- flash@f8000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xf8000000 0x800000>; +- st,smi-fast-mode; +- +- partition@0 { +- label = "xloader"; +- reg = <0x0 0x10000>; +- }; +- partition@10000 { +- label = "u-boot"; +- reg = <0x10000 0x50000>; +- }; +- partition@60000 { +- label = "environment"; +- reg = <0x60000 0x10000>; +- }; +- partition@70000 { +- label = "dtb"; +- reg = <0x70000 0x10000>; +- }; +- partition@80000 { +- label = "linux"; +- reg = <0x80000 0x310000>; +- }; +- partition@390000 { +- label = "rootfs"; +- reg = <0x390000 0x0>; +- }; +- }; +- }; +- +- spi0: spi@d0100000 { +- status = "okay"; +- }; +- +- spi1: spi@a5000000 { +- status = "okay"; +- }; +- +- spi2: spi@a6000000 { +- status = "okay"; +- }; +- +- usbd@e1100000 { +- status = "okay"; +- }; +- +- apb { +- gpio0: gpio@fc980000 { +- status = "okay"; +- }; +- +- gpio@b3000000 { +- status = "okay"; +- }; +- +- i2c0: i2c@d0180000 { +- status = "okay"; +- +- stmpe811@41 { +- compatible = "st,stmpe811"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x41>; +- irq-over-gpio; +- irq-gpios = <&gpiopinctrl 29 0x4>; +- id = <0>; +- blocks = <0x5>; +- irq-trigger = <0x1>; +- +- stmpegpio: stmpe-gpio { +- compatible = "stmpe,gpio"; +- reg = <0>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio,norequest-mask = <0xF3>; +- }; +- +- stmpe610-ts { +- compatible = "stmpe,ts"; +- reg = <0>; +- ts,sample-time = <4>; +- ts,mod-12b = <1>; +- ts,ref-sel = <0>; +- ts,adc-freq = <1>; +- ts,ave-ctrl = <1>; +- ts,touch-det-delay = <3>; +- ts,settling = <4>; +- ts,fraction-z = <7>; +- ts,i-drive = <1>; +- }; +- }; +- }; +- +- i2c1: i2c@a7000000 { +- status = "okay"; +- }; +- +- rtc@fc900000 { +- status = "okay"; +- }; +- +- serial@d0000000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <>; +- }; +- +- serial@a3000000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <>; +- }; +- +- serial@a4000000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <>; +- }; +- +- wdt@fc880000 { +- status = "okay"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/spear320.dtsi b/scripts/dtc/include-prefixes/arm/spear320.dtsi +deleted file mode 100644 +index 3bc1e93a0a55..000000000000 +--- a/scripts/dtc/include-prefixes/arm/spear320.dtsi ++++ /dev/null +@@ -1,141 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * DTS file for SPEAr320 SoC +- * +- * Copyright 2012 Viresh Kumar +- */ +- +-/include/ "spear3xx.dtsi" +- +-/ { +- ahb { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0x40000000 0x40000000 0x80000000 +- 0xd0000000 0xd0000000 0x30000000>; +- +- pinmux: pinmux@b3000000 { +- compatible = "st,spear320-pinmux"; +- reg = <0xb3000000 0x1000>; +- #gpio-range-cells = <3>; +- }; +- +- clcd@90000000 { +- compatible = "arm,pl110", "arm,primecell"; +- reg = <0x90000000 0x1000>; +- interrupts = <8>; +- interrupt-parent = <&shirq>; +- status = "disabled"; +- }; +- +- fsmc: flash@4c000000 { +- compatible = "st,spear600-fsmc-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x4c000000 0x1000 /* FSMC Register */ +- 0x50000000 0x0010 /* NAND Base DATA */ +- 0x50020000 0x0010 /* NAND Base ADDR */ +- 0x50010000 0x0010>; /* NAND Base CMD */ +- reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; +- status = "disabled"; +- }; +- +- sdhci@70000000 { +- compatible = "st,sdhci-spear"; +- reg = <0x70000000 0x100>; +- interrupts = <10>; +- interrupt-parent = <&shirq>; +- status = "disabled"; +- }; +- +- shirq: interrupt-controller@0xb3000000 { +- compatible = "st,spear320-shirq"; +- reg = <0xb3000000 0x1000>; +- interrupts = <30 28 29 1>; +- #interrupt-cells = <1>; +- interrupt-controller; +- }; +- +- spi1: spi@a5000000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0xa5000000 0x1000>; +- interrupts = <15>; +- interrupt-parent = <&shirq>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi2: spi@a6000000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0xa6000000 0x1000>; +- interrupts = <16>; +- interrupt-parent = <&shirq>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pwm: pwm@a8000000 { +- compatible ="st,spear-pwm"; +- reg = <0xa8000000 0x1000>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- apb { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0xa0000000 0xa0000000 0x20000000 +- 0xd0000000 0xd0000000 0x30000000>; +- +- i2c1: i2c@a7000000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xa7000000 0x1000>; +- interrupts = <21>; +- interrupt-parent = <&shirq>; +- status = "disabled"; +- }; +- +- serial@a3000000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xa3000000 0x1000>; +- interrupts = <13>; +- interrupt-parent = <&shirq>; +- status = "disabled"; +- }; +- +- serial@a4000000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xa4000000 0x1000>; +- interrupts = <14>; +- interrupt-parent = <&shirq>; +- status = "disabled"; +- }; +- +- gpiopinctrl: gpio@b3000000 { +- compatible = "st,spear-plgpio"; +- reg = <0xb3000000 0x1000>; +- #interrupt-cells = <1>; +- interrupt-controller; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinmux 0 0 102>; +- status = "disabled"; +- +- st-plgpio,ngpio = <102>; +- st-plgpio,enb-reg = <0x24>; +- st-plgpio,wdata-reg = <0x34>; +- st-plgpio,dir-reg = <0x44>; +- st-plgpio,ie-reg = <0x64>; +- st-plgpio,rdata-reg = <0x54>; +- st-plgpio,mis-reg = <0x84>; +- st-plgpio,eit-reg = <0x94>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/spear3xx.dtsi b/scripts/dtc/include-prefixes/arm/spear3xx.dtsi +deleted file mode 100644 +index cc88ebe7a60c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/spear3xx.dtsi ++++ /dev/null +@@ -1,151 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * DTS file for all SPEAr3xx SoCs +- * +- * Copyright 2012 Viresh Kumar +- */ +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&vic>; +- +- cpus { +- #address-cells = <0>; +- #size-cells = <0>; +- +- cpu { +- compatible = "arm,arm926ej-s"; +- device_type = "cpu"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0 0x40000000>; +- }; +- +- ahb { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0xd0000000 0xd0000000 0x30000000>; +- +- vic: interrupt-controller@f1100000 { +- compatible = "arm,pl190-vic"; +- interrupt-controller; +- reg = <0xf1100000 0x1000>; +- #interrupt-cells = <1>; +- }; +- +- dma@fc400000 { +- compatible = "arm,pl080", "arm,primecell"; +- reg = <0xfc400000 0x1000>; +- interrupt-parent = <&vic>; +- interrupts = <8>; +- status = "disabled"; +- }; +- +- gmac: eth@e0800000 { +- compatible = "snps,dwmac-3.40a"; +- reg = <0xe0800000 0x8000>; +- interrupts = <23 22>; +- interrupt-names = "macirq", "eth_wake_irq"; +- phy-mode = "mii"; +- status = "disabled"; +- }; +- +- smi: flash@fc000000 { +- compatible = "st,spear600-smi"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xfc000000 0x1000>; +- interrupts = <9>; +- status = "disabled"; +- }; +- +- spi0: spi@d0100000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0xd0100000 0x1000>; +- interrupts = <20>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- ehci@e1800000 { +- compatible = "st,spear600-ehci", "usb-ehci"; +- reg = <0xe1800000 0x1000>; +- interrupts = <26>; +- status = "disabled"; +- }; +- +- ohci@e1900000 { +- compatible = "st,spear600-ohci", "usb-ohci"; +- reg = <0xe1900000 0x1000>; +- interrupts = <25>; +- status = "disabled"; +- }; +- +- ohci@e2100000 { +- compatible = "st,spear600-ohci", "usb-ohci"; +- reg = <0xe2100000 0x1000>; +- interrupts = <27>; +- status = "disabled"; +- }; +- +- apb { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0xd0000000 0xd0000000 0x30000000>; +- +- gpio0: gpio@fc980000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0xfc980000 0x1000>; +- interrupts = <11>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "disabled"; +- }; +- +- i2c0: i2c@d0180000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xd0180000 0x1000>; +- interrupts = <21>; +- status = "disabled"; +- }; +- +- rtc@fc900000 { +- compatible = "st,spear600-rtc"; +- reg = <0xfc900000 0x1000>; +- interrupts = <10>; +- status = "disabled"; +- }; +- +- serial@d0000000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xd0000000 0x1000>; +- interrupts = <19>; +- status = "disabled"; +- }; +- +- wdt@fc880000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0xfc880000 0x1000>; +- interrupts = <12>; +- status = "disabled"; +- }; +- +- timer@f0000000 { +- compatible = "st,spear-timer"; +- reg = <0xf0000000 0x400>; +- interrupts = <2>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/spear600-evb.dts b/scripts/dtc/include-prefixes/arm/spear600-evb.dts +deleted file mode 100644 +index a25b86d149ad..000000000000 +--- a/scripts/dtc/include-prefixes/arm/spear600-evb.dts ++++ /dev/null +@@ -1,106 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Stefan Roese +- */ +- +-/dts-v1/; +-/include/ "spear600.dtsi" +- +-/ { +- model = "ST SPEAr600 Evaluation Board"; +- compatible = "st,spear600-evb", "st,spear600"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory { +- device_type = "memory"; +- reg = <0 0x10000000>; +- }; +-}; +- +-&clcd { +- status = "okay"; +-}; +- +-&dmac { +- status = "okay"; +-}; +- +-&ehci_usb0 { +- status = "okay"; +-}; +- +-&ehci_usb1 { +- status = "okay"; +-}; +- +-&gmac { +- phy-mode = "gmii"; +- status = "okay"; +-}; +- +-&ohci_usb0 { +- status = "okay"; +-}; +- +-&ohci_usb1 { +- status = "okay"; +-}; +- +-&smi { +- status = "okay"; +- clock-rate = <50000000>; +- +- flash@f8000000 { +- reg = <0xf8000000 0x800000>; +- st,smi-fast-mode; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "xloader"; +- reg = <0x0 0x10000>; +- }; +- partition@10000 { +- label = "u-boot"; +- reg = <0x10000 0x50000>; +- }; +- partition@60000 { +- label = "environment"; +- reg = <0x60000 0x10000>; +- }; +- partition@70000 { +- label = "dtb"; +- reg = <0x70000 0x10000>; +- }; +- partition@80000 { +- label = "linux"; +- reg = <0x80000 0x310000>; +- }; +- partition@390000 { +- label = "rootfs"; +- reg = <0x390000 0x0>; +- }; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&i2c { +- clock-frequency = <400000>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/spear600.dtsi b/scripts/dtc/include-prefixes/arm/spear600.dtsi +deleted file mode 100644 +index fd41243a0b2c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/spear600.dtsi ++++ /dev/null +@@ -1,212 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Stefan Roese +- */ +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,spear600"; +- +- cpus { +- #address-cells = <0>; +- #size-cells = <0>; +- +- cpu { +- compatible = "arm,arm926ej-s"; +- device_type = "cpu"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0 0x40000000>; +- }; +- +- ahb { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0xd0000000 0xd0000000 0x30000000>; +- +- vic0: interrupt-controller@f1100000 { +- compatible = "arm,pl190-vic"; +- interrupt-controller; +- reg = <0xf1100000 0x1000>; +- #interrupt-cells = <1>; +- }; +- +- vic1: interrupt-controller@f1000000 { +- compatible = "arm,pl190-vic"; +- interrupt-controller; +- reg = <0xf1000000 0x1000>; +- #interrupt-cells = <1>; +- }; +- +- clcd: clcd@fc200000 { +- compatible = "arm,pl110", "arm,primecell"; +- reg = <0xfc200000 0x1000>; +- interrupt-parent = <&vic1>; +- interrupts = <12>; +- status = "disabled"; +- }; +- +- dmac: dma@fc400000 { +- compatible = "arm,pl080", "arm,primecell"; +- reg = <0xfc400000 0x1000>; +- interrupt-parent = <&vic1>; +- interrupts = <10>; +- status = "disabled"; +- }; +- +- gmac: ethernet@e0800000 { +- compatible = "st,spear600-gmac"; +- reg = <0xe0800000 0x8000>; +- interrupt-parent = <&vic1>; +- interrupts = <24 23>; +- interrupt-names = "macirq", "eth_wake_irq"; +- phy-mode = "gmii"; +- status = "disabled"; +- }; +- +- fsmc: flash@d1800000 { +- compatible = "st,spear600-fsmc-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xd1800000 0x1000 /* FSMC Register */ +- 0xd2000000 0x0010 /* NAND Base DATA */ +- 0xd2020000 0x0010 /* NAND Base ADDR */ +- 0xd2010000 0x0010>; /* NAND Base CMD */ +- reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; +- status = "disabled"; +- }; +- +- smi: flash@fc000000 { +- compatible = "st,spear600-smi"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xfc000000 0x1000>; +- interrupt-parent = <&vic1>; +- interrupts = <12>; +- status = "disabled"; +- }; +- +- ehci_usb0: ehci@e1800000 { +- compatible = "st,spear600-ehci", "usb-ehci"; +- reg = <0xe1800000 0x1000>; +- interrupt-parent = <&vic1>; +- interrupts = <27>; +- status = "disabled"; +- }; +- +- ehci_usb1: ehci@e2000000 { +- compatible = "st,spear600-ehci", "usb-ehci"; +- reg = <0xe2000000 0x1000>; +- interrupt-parent = <&vic1>; +- interrupts = <29>; +- status = "disabled"; +- }; +- +- ohci_usb0: ohci@e1900000 { +- compatible = "st,spear600-ohci", "usb-ohci"; +- reg = <0xe1900000 0x1000>; +- interrupt-parent = <&vic1>; +- interrupts = <26>; +- status = "disabled"; +- }; +- +- ohci_usb1: ohci@e2100000 { +- compatible = "st,spear600-ohci", "usb-ohci"; +- reg = <0xe2100000 0x1000>; +- interrupt-parent = <&vic1>; +- interrupts = <28>; +- status = "disabled"; +- }; +- +- apb { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0xd0000000 0xd0000000 0x30000000>; +- +- uart0: serial@d0000000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xd0000000 0x1000>; +- interrupt-parent = <&vic0>; +- interrupts = <24>; +- status = "disabled"; +- }; +- +- uart1: serial@d0080000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0xd0080000 0x1000>; +- interrupt-parent = <&vic0>; +- interrupts = <25>; +- status = "disabled"; +- }; +- +- /* local/cpu GPIO */ +- gpio0: gpio@f0100000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0xf0100000 0x1000>; +- interrupt-parent = <&vic0>; +- interrupts = <18>; +- }; +- +- /* basic GPIO */ +- gpio1: gpio@fc980000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0xfc980000 0x1000>; +- interrupt-parent = <&vic1>; +- interrupts = <19>; +- }; +- +- /* appl GPIO */ +- gpio2: gpio@d8100000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0xd8100000 0x1000>; +- interrupt-parent = <&vic1>; +- interrupts = <4>; +- }; +- +- i2c: i2c@d0200000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xd0200000 0x1000>; +- interrupt-parent = <&vic0>; +- interrupts = <28>; +- status = "disabled"; +- }; +- +- rtc: rtc@fc900000 { +- compatible = "st,spear600-rtc"; +- reg = <0xfc900000 0x1000>; +- interrupt-parent = <&vic0>; +- interrupts = <10>; +- status = "disabled"; +- }; +- +- timer@f0000000 { +- compatible = "st,spear-timer"; +- reg = <0xf0000000 0x400>; +- interrupt-parent = <&vic0>; +- interrupts = <16>; +- }; +- +- adc: adc@d820b000 { +- compatible = "st,spear600-adc"; +- reg = <0xd820b000 0x1000>; +- interrupt-parent = <&vic1>; +- interrupts = <6>; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/st-pincfg.h b/scripts/dtc/include-prefixes/arm/st-pincfg.h +deleted file mode 100644 +index d80551202292..000000000000 +--- a/scripts/dtc/include-prefixes/arm/st-pincfg.h ++++ /dev/null +@@ -1,72 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef _ST_PINCFG_H_ +-#define _ST_PINCFG_H_ +- +-/* Alternate functions */ +-#define ALT1 1 +-#define ALT2 2 +-#define ALT3 3 +-#define ALT4 4 +-#define ALT5 5 +-#define ALT6 6 +-#define ALT7 7 +- +-/* Output enable */ +-#define OE (1 << 27) +-/* Pull Up */ +-#define PU (1 << 26) +-/* Open Drain */ +-#define OD (1 << 25) +-#define RT (1 << 23) +-#define INVERTCLK (1 << 22) +-#define CLKNOTDATA (1 << 21) +-#define DOUBLE_EDGE (1 << 20) +-#define CLK_A (0 << 18) +-#define CLK_B (1 << 18) +-#define CLK_C (2 << 18) +-#define CLK_D (3 << 18) +- +-/* User-frendly defines for Pin Direction */ +- /* oe = 0, pu = 0, od = 0 */ +-#define IN (0) +- /* oe = 0, pu = 1, od = 0 */ +-#define IN_PU (PU) +- /* oe = 1, pu = 0, od = 0 */ +-#define OUT (OE) +- /* oe = 1, pu = 0, od = 1 */ +-#define BIDIR (OE | OD) +- /* oe = 1, pu = 1, od = 1 */ +-#define BIDIR_PU (OE | PU | OD) +- +-/* RETIME_TYPE */ +-/* +- * B Mode +- * Bypass retime with optional delay parameter +- */ +-#define BYPASS (0) +-/* +- * R0, R1, R0D, R1D modes +- * single-edge data non inverted clock, retime data with clk +- */ +-#define SE_NICLK_IO (RT) +-/* +- * RIV0, RIV1, RIV0D, RIV1D modes +- * single-edge data inverted clock, retime data with clk +- */ +-#define SE_ICLK_IO (RT | INVERTCLK) +-/* +- * R0E, R1E, R0ED, R1ED modes +- * double-edge data, retime data with clk +- */ +-#define DE_IO (RT | DOUBLE_EDGE) +-/* +- * CIV0, CIV1 modes with inverted clock +- * Retiming the clk pins will park clock & reduce the noise within the core. +- */ +-#define ICLK (RT | CLKNOTDATA | INVERTCLK) +-/* +- * CLK0, CLK1 modes with non-inverted clock +- * Retiming the clk pins will park clock & reduce the noise within the core. +- */ +-#define NICLK (RT | CLKNOTDATA) +-#endif /* _ST_PINCFG_H_ */ +diff --git a/scripts/dtc/include-prefixes/arm/ste-ab8500.dtsi b/scripts/dtc/include-prefixes/arm/ste-ab8500.dtsi +deleted file mode 100644 +index 9baf927f9b95..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-ab8500.dtsi ++++ /dev/null +@@ -1,396 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Linaro Ltd +- */ +- +-#include +- +-/ { +- /* Essential housekeeping hardware monitors */ +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&gpadc 0x02>, /* Battery temperature */ +- <&gpadc 0x03>, /* Main charger voltage */ +- <&gpadc 0x08>, /* Main battery voltage */ +- <&gpadc 0x09>, /* VBUS */ +- <&gpadc 0x0a>, /* Main charger current */ +- <&gpadc 0x0b>, /* USB charger current */ +- <&gpadc 0x0c>, /* Backup battery voltage */ +- <&gpadc 0x0d>, /* Die temperature */ +- <&gpadc 0x12>; /* Crystal temperature */ +- }; +- +- soc { +- prcmu@80157000 { +- ab8500 { +- compatible = "stericsson,ab8500"; +- interrupt-parent = <&intc>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- ab8500_clock: clock-controller { +- compatible = "stericsson,ab8500-clk"; +- #clock-cells = <1>; +- }; +- +- ab8500_gpio: ab8500-gpiocontroller { +- compatible = "stericsson,ab8500-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- ab8500-rtc { +- compatible = "stericsson,ab8500-rtc"; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, +- <18 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "60S", "ALARM"; +- }; +- +- gpadc: ab8500-gpadc { +- compatible = "stericsson,ab8500-gpadc"; +- interrupts = <32 IRQ_TYPE_LEVEL_HIGH>, +- <39 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "HW_CONV_END", "SW_CONV_END"; +- vddadc-supply = <&ab8500_ldo_tvout_reg>; +- #address-cells = <1>; +- #size-cells = <0>; +- #io-channel-cells = <1>; +- +- /* GPADC channels */ +- bat_ctrl: channel@1 { +- reg = <0x01>; +- }; +- btemp_ball: channel@2 { +- reg = <0x02>; +- }; +- main_charger_v: channel@3 { +- reg = <0x03>; +- }; +- acc_detect1: channel@4 { +- reg = <0x04>; +- }; +- acc_detect2: channel@5 { +- reg = <0x05>; +- }; +- adc_aux1: channel@6 { +- reg = <0x06>; +- }; +- adc_aux2: channel@7 { +- reg = <0x07>; +- }; +- main_batt_v: channel@8 { +- reg = <0x08>; +- }; +- vbus_v: channel@9 { +- reg = <0x09>; +- }; +- main_charger_c: channel@a { +- reg = <0x0a>; +- }; +- usb_charger_c: channel@b { +- reg = <0x0b>; +- }; +- bk_bat_v: channel@c { +- reg = <0x0c>; +- }; +- die_temp: channel@d { +- reg = <0x0d>; +- }; +- usb_id: channel@e { +- reg = <0x0e>; +- }; +- xtal_temp: channel@12 { +- reg = <0x12>; +- }; +- vbat_true_meas: channel@13 { +- reg = <0x13>; +- }; +- bat_ctrl_and_ibat: channel@1c { +- reg = <0x1c>; +- }; +- vbat_meas_and_ibat: channel@1d { +- reg = <0x1d>; +- }; +- vbat_true_meas_and_ibat: channel@1e { +- reg = <0x1e>; +- }; +- bat_temp_and_ibat: channel@1f { +- reg = <0x1f>; +- }; +- }; +- +- ab8500_temp { +- compatible = "stericsson,abx500-temp"; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "ABX500_TEMP_WARM"; +- io-channels = <&gpadc 0x06>, +- <&gpadc 0x07>; +- io-channel-names = "aux1", "aux2"; +- }; +- +- ab8500_battery: ab8500_battery { +- stericsson,battery-type = "LIPO"; +- thermistor-on-batctrl; +- }; +- +- ab8500_fg { +- compatible = "stericsson,ab8500-fg"; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, +- <8 IRQ_TYPE_LEVEL_HIGH>, +- <28 IRQ_TYPE_LEVEL_HIGH>, +- <27 IRQ_TYPE_LEVEL_HIGH>, +- <26 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "NCONV_ACCU", +- "BATT_OVV", +- "LOW_BAT_F", +- "CC_INT_CALIB", +- "CCEOC"; +- battery = <&ab8500_battery>; +- io-channels = <&gpadc 0x08>; +- io-channel-names = "main_bat_v"; +- }; +- +- ab8500_btemp { +- compatible = "stericsson,ab8500-btemp"; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH>, +- <80 IRQ_TYPE_LEVEL_HIGH>, +- <83 IRQ_TYPE_LEVEL_HIGH>, +- <81 IRQ_TYPE_LEVEL_HIGH>, +- <82 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "BAT_CTRL_INDB", +- "BTEMP_LOW", +- "BTEMP_HIGH", +- "BTEMP_LOW_MEDIUM", +- "BTEMP_MEDIUM_HIGH"; +- battery = <&ab8500_battery>; +- io-channels = <&gpadc 0x02>, +- <&gpadc 0x01>; +- io-channel-names = "btemp_ball", +- "bat_ctrl"; +- }; +- +- ab8500_charger { +- compatible = "stericsson,ab8500-charger"; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, +- <11 IRQ_TYPE_LEVEL_HIGH>, +- <0 IRQ_TYPE_LEVEL_HIGH>, +- <107 IRQ_TYPE_LEVEL_HIGH>, +- <106 IRQ_TYPE_LEVEL_HIGH>, +- <14 IRQ_TYPE_LEVEL_HIGH>, +- <15 IRQ_TYPE_LEVEL_HIGH>, +- <79 IRQ_TYPE_LEVEL_HIGH>, +- <105 IRQ_TYPE_LEVEL_HIGH>, +- <104 IRQ_TYPE_LEVEL_HIGH>, +- <89 IRQ_TYPE_LEVEL_HIGH>, +- <22 IRQ_TYPE_LEVEL_HIGH>, +- <21 IRQ_TYPE_LEVEL_HIGH>, +- <16 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "MAIN_CH_UNPLUG_DET", +- "MAIN_CHARGE_PLUG_DET", +- "MAIN_EXT_CH_NOT_OK", +- "MAIN_CH_TH_PROT_R", +- "MAIN_CH_TH_PROT_F", +- "VBUS_DET_F", +- "VBUS_DET_R", +- "USB_LINK_STATUS", +- "USB_CH_TH_PROT_R", +- "USB_CH_TH_PROT_F", +- "USB_CHARGER_NOT_OKR", +- "VBUS_OVV", +- "CH_WD_EXP", +- "VBUS_CH_DROP_END"; +- battery = <&ab8500_battery>; +- vddadc-supply = <&ab8500_ldo_tvout_reg>; +- io-channels = <&gpadc 0x03>, +- <&gpadc 0x0a>, +- <&gpadc 0x09>, +- <&gpadc 0x0b>; +- io-channel-names = "main_charger_v", +- "main_charger_c", +- "vbus_v", +- "usb_charger_c"; +- }; +- +- ab8500_chargalg { +- compatible = "stericsson,ab8500-chargalg"; +- battery = <&ab8500_battery>; +- }; +- +- ab8500_usb: ab8500_usb { +- compatible = "stericsson,ab8500-usb"; +- interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, +- <96 IRQ_TYPE_LEVEL_HIGH>, +- <14 IRQ_TYPE_LEVEL_HIGH>, +- <15 IRQ_TYPE_LEVEL_HIGH>, +- <79 IRQ_TYPE_LEVEL_HIGH>, +- <74 IRQ_TYPE_LEVEL_HIGH>, +- <75 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "ID_WAKEUP_R", +- "ID_WAKEUP_F", +- "VBUS_DET_F", +- "VBUS_DET_R", +- "USB_LINK_STATUS", +- "USB_ADP_PROBE_PLUG", +- "USB_ADP_PROBE_UNPLUG"; +- vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; +- v-ape-supply = <&db8500_vape_reg>; +- musb_1v8-supply = <&db8500_vsmps2_reg>; +- clocks = <&prcmu_clk PRCMU_SYSCLK>; +- clock-names = "sysclk"; +- #phy-cells = <0>; +- }; +- +- ab8500-ponkey { +- compatible = "stericsson,ab8500-poweron-key"; +- interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, +- <7 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; +- }; +- +- ab8500-sysctrl { +- compatible = "stericsson,ab8500-sysctrl"; +- }; +- +- ab8500-pwm-1 { +- compatible = "stericsson,ab8500-pwm"; +- clocks = <&ab8500_clock AB8500_SYSCLK_INT>; +- clock-names = "intclk"; +- }; +- +- ab8500-pwm-2 { +- compatible = "stericsson,ab8500-pwm"; +- clocks = <&ab8500_clock AB8500_SYSCLK_INT>; +- clock-names = "intclk"; +- }; +- +- ab8500-pwm-3 { +- compatible = "stericsson,ab8500-pwm"; +- clocks = <&ab8500_clock AB8500_SYSCLK_INT>; +- clock-names = "intclk"; +- }; +- +- ab8500-debugfs { +- compatible = "stericsson,ab8500-debug"; +- }; +- +- codec: ab8500-codec { +- compatible = "stericsson,ab8500-codec"; +- +- V-AUD-supply = <&ab8500_ldo_audio_reg>; +- V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>; +- V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>; +- V-DMIC-supply = <&ab8500_ldo_dmic_reg>; +- +- clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>; +- clock-names = "audioclk"; +- +- stericsson,earpeice-cmv = <950>; /* Units in mV. */ +- }; +- +- ext_regulators: ab8500-ext-regulators { +- compatible = "stericsson,ab8500-ext-regulator"; +- +- ab8500_ext1_reg: ab8500_ext1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ab8500_ext2_reg: ab8500_ext2 { +- regulator-min-microvolt = <1360000>; +- regulator-max-microvolt = <1360000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ab8500_ext3_reg: ab8500_ext3 { +- regulator-min-microvolt = <3400000>; +- regulator-max-microvolt = <3400000>; +- regulator-boot-on; +- }; +- }; +- +- ab8500-regulators { +- compatible = "stericsson,ab8500-regulator"; +- vin-supply = <&ab8500_ext3_reg>; +- +- // supplies to the display/camera +- ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- /* BUG: If turned off MMC will be affected. */ +- regulator-always-on; +- }; +- +- // supplies to the on-board eMMC +- ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- // supply for VAUX3; SDcard slots +- ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- // supply for v-intcore12; VINTCORE12 LDO +- ab8500_ldo_intcore_reg: ab8500_ldo_intcore { +- }; +- +- // supply for tvout; gpadc; TVOUT LDO +- ab8500_ldo_tvout_reg: ab8500_ldo_tvout { +- }; +- +- // supply for ab8500-vaudio; VAUDIO LDO +- ab8500_ldo_audio_reg: ab8500_ldo_audio { +- }; +- +- // supply for v-anamic1 VAMIC1 LDO +- ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { +- }; +- +- // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 +- ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { +- }; +- +- // supply for v-dmic; VDMIC LDO +- ab8500_ldo_dmic_reg: ab8500_ldo_dmic { +- }; +- +- // supply for U8500 CSI/DSI; VANA LDO +- ab8500_ldo_ana_reg: ab8500_ldo_ana { +- }; +- }; +- }; +- }; +- +- sound { +- stericsson,audio-codec = <&codec>; +- clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>; +- clock-names = "sysclk", "ulpclk", "intclk"; +- }; +- +- mcde@a0350000 { +- vana-supply = <&ab8500_ldo_ana_reg>; +- +- dsi@a0351000 { +- vana-supply = <&ab8500_ldo_ana_reg>; +- }; +- dsi@a0352000 { +- vana-supply = <&ab8500_ldo_ana_reg>; +- }; +- dsi@a0353000 { +- vana-supply = <&ab8500_ldo_ana_reg>; +- }; +- }; +- +- usb_per5@a03e0000 { +- phys = <&ab8500_usb>; +- phy-names = "usb"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-ab8505.dtsi b/scripts/dtc/include-prefixes/arm/ste-ab8505.dtsi +deleted file mode 100644 +index 8d018701a680..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-ab8505.dtsi ++++ /dev/null +@@ -1,332 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Linaro Ltd +- */ +- +-#include +- +-/ { +- /* Essential housekeeping hardware monitors */ +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&gpadc 0x02>, /* Battery temperature */ +- <&gpadc 0x08>, /* Main battery voltage */ +- <&gpadc 0x09>, /* VBUS */ +- <&gpadc 0x0b>, /* Charger current */ +- <&gpadc 0x0c>, /* Backup battery voltage */ +- <&gpadc 0x0d>; /* Die temperature */ +- }; +- +- soc { +- prcmu@80157000 { +- ab8505 { +- compatible = "stericsson,ab8505"; +- interrupt-parent = <&intc>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- ab8500_clock: clock-controller { +- compatible = "stericsson,ab8500-clk"; +- #clock-cells = <1>; +- }; +- +- ab8505_gpio: ab8505-gpiocontroller { +- compatible = "stericsson,ab8505-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- ab8500-rtc { +- compatible = "stericsson,ab8500-rtc"; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, +- <18 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "60S", "ALARM"; +- }; +- +- gpadc: ab8500-gpadc { +- compatible = "stericsson,ab8500-gpadc"; +- interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "SW_CONV_END"; +- vddadc-supply = <&ab8500_ldo_adc_reg>; +- #address-cells = <1>; +- #size-cells = <0>; +- #io-channel-cells = <1>; +- +- /* GPADC channels */ +- bat_ctrl: channel@1 { +- reg = <0x01>; +- }; +- btemp_ball: channel@2 { +- reg = <0x02>; +- }; +- acc_detect1: channel@4 { +- reg = <0x04>; +- }; +- acc_detect2: channel@5 { +- reg = <0x05>; +- }; +- adc_aux1: channel@6 { +- reg = <0x06>; +- }; +- adc_aux2: channel@7 { +- reg = <0x07>; +- }; +- main_batt_v: channel@8 { +- reg = <0x08>; +- }; +- vbus_v: channel@9 { +- reg = <0x09>; +- }; +- charger_c: channel@b { +- reg = <0x0b>; +- }; +- bk_bat_v: channel@c { +- reg = <0x0c>; +- }; +- die_temp: channel@d { +- reg = <0x0d>; +- }; +- usb_id: channel@e { +- reg = <0x0e>; +- }; +- }; +- +- ab8500_battery: ab8500_battery { +- stericsson,battery-type = "LIPO"; +- thermistor-on-batctrl; +- }; +- +- ab8500_fg { +- status = "disabled"; +- compatible = "stericsson,ab8500-fg"; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, +- <8 IRQ_TYPE_LEVEL_HIGH>, +- <28 IRQ_TYPE_LEVEL_HIGH>, +- <27 IRQ_TYPE_LEVEL_HIGH>, +- <26 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "NCONV_ACCU", +- "BATT_OVV", +- "LOW_BAT_F", +- "CC_INT_CALIB", +- "CCEOC"; +- battery = <&ab8500_battery>; +- io-channels = <&gpadc 0x08>; +- io-channel-names = "main_bat_v"; +- }; +- +- ab8500_btemp { +- status = "disabled"; +- compatible = "stericsson,ab8500-btemp"; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH>, +- <80 IRQ_TYPE_LEVEL_HIGH>, +- <83 IRQ_TYPE_LEVEL_HIGH>, +- <81 IRQ_TYPE_LEVEL_HIGH>, +- <82 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "BAT_CTRL_INDB", +- "BTEMP_LOW", +- "BTEMP_HIGH", +- "BTEMP_LOW_MEDIUM", +- "BTEMP_MEDIUM_HIGH"; +- battery = <&ab8500_battery>; +- io-channels = <&gpadc 0x02>, +- <&gpadc 0x01>; +- io-channel-names = "btemp_ball", +- "bat_ctrl"; +- }; +- +- ab8500_charger { +- status = "disabled"; +- compatible = "stericsson,ab8500-charger"; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, +- <11 IRQ_TYPE_LEVEL_HIGH>, +- <0 IRQ_TYPE_LEVEL_HIGH>, +- <107 IRQ_TYPE_LEVEL_HIGH>, +- <106 IRQ_TYPE_LEVEL_HIGH>, +- <14 IRQ_TYPE_LEVEL_HIGH>, +- <15 IRQ_TYPE_LEVEL_HIGH>, +- <79 IRQ_TYPE_LEVEL_HIGH>, +- <105 IRQ_TYPE_LEVEL_HIGH>, +- <104 IRQ_TYPE_LEVEL_HIGH>, +- <89 IRQ_TYPE_LEVEL_HIGH>, +- <22 IRQ_TYPE_LEVEL_HIGH>, +- <21 IRQ_TYPE_LEVEL_HIGH>, +- <16 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "MAIN_CH_UNPLUG_DET", +- "MAIN_CHARGE_PLUG_DET", +- "MAIN_EXT_CH_NOT_OK", +- "MAIN_CH_TH_PROT_R", +- "MAIN_CH_TH_PROT_F", +- "VBUS_DET_F", +- "VBUS_DET_R", +- "USB_LINK_STATUS", +- "USB_CH_TH_PROT_R", +- "USB_CH_TH_PROT_F", +- "USB_CHARGER_NOT_OKR", +- "VBUS_OVV", +- "CH_WD_EXP", +- "VBUS_CH_DROP_END"; +- battery = <&ab8500_battery>; +- vddadc-supply = <&ab8500_ldo_adc_reg>; +- io-channels = <&gpadc 0x09>, +- <&gpadc 0x0b>; +- io-channel-names = "vbus_v", +- "usb_charger_c"; +- }; +- +- ab8500_chargalg { +- status = "disabled"; +- compatible = "stericsson,ab8500-chargalg"; +- battery = <&ab8500_battery>; +- }; +- +- ab8500_usb: ab8500_usb { +- compatible = "stericsson,ab8500-usb"; +- interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, +- <96 IRQ_TYPE_LEVEL_HIGH>, +- <14 IRQ_TYPE_LEVEL_HIGH>, +- <15 IRQ_TYPE_LEVEL_HIGH>, +- <79 IRQ_TYPE_LEVEL_HIGH>, +- <74 IRQ_TYPE_LEVEL_HIGH>, +- <75 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "ID_WAKEUP_R", +- "ID_WAKEUP_F", +- "VBUS_DET_F", +- "VBUS_DET_R", +- "USB_LINK_STATUS", +- "USB_ADP_PROBE_PLUG", +- "USB_ADP_PROBE_UNPLUG"; +- vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; +- v-ape-supply = <&db8500_vape_reg>; +- musb_1v8-supply = <&db8500_vsmps2_reg>; +- clocks = <&prcmu_clk PRCMU_SYSCLK>; +- clock-names = "sysclk"; +- #phy-cells = <0>; +- }; +- +- ab8500-ponkey { +- compatible = "stericsson,ab8500-poweron-key"; +- interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, +- <7 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; +- }; +- +- ab8500-sysctrl { +- compatible = "stericsson,ab8500-sysctrl"; +- }; +- +- ab8500-pwm { +- compatible = "stericsson,ab8500-pwm"; +- clocks = <&ab8500_clock AB8500_SYSCLK_INT>; +- clock-names = "intclk"; +- }; +- +- ab8500-debugfs { +- compatible = "stericsson,ab8500-debug"; +- }; +- +- codec: ab8500-codec { +- compatible = "stericsson,ab8500-codec"; +- +- V-AUD-supply = <&ab8500_ldo_audio_reg>; +- V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>; +- V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>; +- +- clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>; +- clock-names = "audioclk"; +- +- stericsson,earpeice-cmv = <950>; /* Units in mV. */ +- }; +- +- ab8505-regulators { +- compatible = "stericsson,ab8505-regulator"; +- +- ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ab8500_ldo_aux4_reg: ab8500_ldo_aux4 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ab8500_ldo_aux5_reg: ab8500_ldo_aux5 { +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <2790000>; +- }; +- +- ab8500_ldo_aux6_reg: ab8500_ldo_aux6 { +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <2790000>; +- }; +- +- // supply for v-intcore12; VINTCORE12 LDO +- ab8500_ldo_intcore_reg: ab8500_ldo_intcore { +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1350000>; +- }; +- +- // supply for gpadc; ADC LDO +- ab8500_ldo_adc_reg: ab8500_ldo_adc { +- }; +- +- // supply for ab8500-vaudio; VAUDIO LDO +- ab8500_ldo_audio_reg: ab8500_ldo_audio { +- }; +- +- // supply for v-anamic1 VAMIC1 LDO +- ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { +- }; +- +- // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 +- ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { +- }; +- +- // supply for v-aux8; VAUX8 LDO +- ab8500_ldo_aux8_reg: ab8500_ldo_aux8 { +- }; +- +- // supply for U8500 CSI/DSI; VANA LDO +- ab8500_ldo_ana_reg: ab8500_ldo_ana { +- }; +- }; +- }; +- }; +- +- sound { +- stericsson,audio-codec = <&codec>; +- clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>; +- clock-names = "sysclk", "ulpclk", "intclk"; +- }; +- +- mcde@a0350000 { +- vana-supply = <&ab8500_ldo_ana_reg>; +- +- dsi@a0351000 { +- vana-supply = <&ab8500_ldo_ana_reg>; +- }; +- dsi@a0352000 { +- vana-supply = <&ab8500_ldo_ana_reg>; +- }; +- dsi@a0353000 { +- vana-supply = <&ab8500_ldo_ana_reg>; +- }; +- }; +- +- usb_per5@a03e0000 { +- phys = <&ab8500_usb>; +- phy-names = "usb"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-db8500.dtsi b/scripts/dtc/include-prefixes/arm/ste-db8500.dtsi +deleted file mode 100644 +index f1ff3f4835d7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-db8500.dtsi ++++ /dev/null +@@ -1,52 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +- +-#include "ste-dbx5x0.dtsi" +- +-/ { +- cpus { +- cpu@300 { +- operating-points = <998400 0 +- 798720 0 +- 399360 0 +- 199680 0>; +- }; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* Modem trace memory */ +- ram@6000000 { +- reg = <0x06000000 0x00f00000>; +- no-map; +- }; +- +- /* Modem shared memory */ +- ram@6f00000 { +- reg = <0x06f00000 0x00100000>; +- no-map; +- }; +- +- /* Modem private memory */ +- ram@7000000 { +- reg = <0x07000000 0x01000000>; +- no-map; +- }; +- +- /* +- * Initial Secure Software ISSW memory +- * +- * This is probably only used if the kernel tries +- * to actually call into trustzone to run secure +- * applications, which the mainline kernel probably +- * will not do on this old chipset. But you can never +- * be too careful, so reserve this memory anyway. +- */ +- ram@17f00000 { +- reg = <0x17f00000 0x00100000>; +- no-map; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-db8520.dtsi b/scripts/dtc/include-prefixes/arm/ste-db8520.dtsi +deleted file mode 100644 +index e4e8d5fc1f8a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-db8520.dtsi ++++ /dev/null +@@ -1,52 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +- +-#include "ste-dbx5x0.dtsi" +- +-/ { +- cpus { +- cpu@300 { +- operating-points = <1152000 0 +- 798720 0 +- 399360 0 +- 199680 0>; +- }; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* Modem trace memory */ +- ram@6000000 { +- reg = <0x06000000 0x00f00000>; +- no-map; +- }; +- +- /* Modem shared memory */ +- ram@6f00000 { +- reg = <0x06f00000 0x00100000>; +- no-map; +- }; +- +- /* Modem private memory */ +- ram@7000000 { +- reg = <0x07000000 0x01000000>; +- no-map; +- }; +- +- /* +- * Initial Secure Software ISSW memory +- * +- * This is probably only used if the kernel tries +- * to actually call into trustzone to run secure +- * applications, which the mainline kernel probably +- * will not do on this old chipset. But you can never +- * be too careful, so reserve this memory anyway. +- */ +- ram@17f00000 { +- reg = <0x17f00000 0x00100000>; +- no-map; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-db9500.dtsi b/scripts/dtc/include-prefixes/arm/ste-db9500.dtsi +deleted file mode 100644 +index 4273d36e881d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-db9500.dtsi ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +- +-#include "ste-dbx5x0.dtsi" +- +-/ { +- cpus { +- cpu@300 { +- operating-points = <998400 0 +- 798720 0 +- 399360 0 +- 199680 0>; +- }; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* +- * Initial Secure Software ISSW memory +- * +- * This is probably only used if the kernel tries +- * to actually call into trustzone to run secure +- * applications, which the mainline kernel probably +- * will not do on this old chipset. But you can never +- * be too careful, so reserve this memory anyway. +- */ +- ram@17f00000 { +- reg = <0x17f00000 0x00100000>; +- no-map; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-dbx5x0-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/ste-dbx5x0-pinctrl.dtsi +deleted file mode 100644 +index 31a86606beda..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-dbx5x0-pinctrl.dtsi ++++ /dev/null +@@ -1,650 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Linaro Ltd. +- */ +- +-#include "ste-nomadik-pinctrl.dtsi" +- +-&pinctrl { +- /* Settings for all UART default and sleep states */ +- uart0 { +- u0_a_1_default: u0_a_1_default { +- default_mux { +- function = "u0"; +- groups = "u0_a_1"; +- }; +- default_cfg1 { +- pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ +- ste,config = <&in_pu>; +- }; +- default_cfg2 { +- pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ +- ste,config = <&out_hi>; +- }; +- }; +- +- u0_a_1_sleep: u0_a_1_sleep { +- sleep_cfg1 { +- pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ +- ste,config = <&slpm_in_wkup_pdis>; +- }; +- sleep_cfg2 { +- pins = "GPIO1_AJ3"; /* RTS */ +- ste,config = <&slpm_out_hi_wkup_pdis>; +- }; +- sleep_cfg3 { +- pins = "GPIO3_AH3"; /* TXD */ +- ste,config = <&slpm_out_wkup_pdis>; +- }; +- }; +- }; +- +- uart1 { +- u1rxtx_a_1_default: u1rxtx_a_1_default { +- default_mux { +- function = "u1"; +- groups = "u1rxtx_a_1"; +- }; +- default_cfg1 { +- pins = "GPIO4_AH6"; /* RXD */ +- ste,config = <&in_pu>; +- }; +- default_cfg2 { +- pins = "GPIO5_AG6"; /* TXD */ +- ste,config = <&out_hi>; +- }; +- }; +- +- u1rxtx_a_1_sleep: u1rxtx_a_1_sleep { +- sleep_cfg1 { +- pins = "GPIO4_AH6"; /* RXD */ +- ste,config = <&slpm_in_wkup_pdis>; +- }; +- sleep_cfg2 { +- pins = "GPIO5_AG6"; /* TXD */ +- ste,config = <&slpm_out_wkup_pdis>; +- }; +- }; +- +- u1ctsrts_a_1_default: u1ctsrts_a_1_default { +- default_mux { +- function = "u1"; +- groups = "u1ctsrts_a_1"; +- }; +- default_cfg1 { +- pins = "GPIO6_AF6"; /* CTS */ +- ste,config = <&in_pu>; +- }; +- default_cfg2 { +- pins = "GPIO7_AG5"; /* RTS */ +- ste,config = <&out_hi>; +- }; +- }; +- +- u1ctsrts_a_1_sleep: u1ctsrts_a_1_sleep { +- sleep_cfg1 { +- pins = "GPIO6_AF6"; /* CTS */ +- ste,config = <&slpm_in_wkup_pdis>; +- }; +- sleep_cfg2 { +- pins = "GPIO7_AG5"; /* RTS */ +- ste,config = <&slpm_out_hi_wkup_pdis>; +- }; +- }; +- }; +- +- uart2 { +- u2rxtx_c_1_default: u2rxtx_c_1_default { +- default_mux { +- function = "u2"; +- groups = "u2rxtx_c_1"; +- }; +- default_cfg1 { +- pins = "GPIO29_W2"; /* RXD */ +- ste,config = <&in_pu>; +- }; +- default_cfg2 { +- pins = "GPIO30_W3"; /* TXD */ +- ste,config = <&out_hi>; +- }; +- }; +- +- u2rxtx_c_1_sleep: u2rxtx_c_1_sleep { +- sleep_cfg1 { +- pins = "GPIO29_W2"; /* RXD */ +- ste,config = <&in_wkup_pdis>; +- }; +- sleep_cfg2 { +- pins = "GPIO30_W3"; /* TXD */ +- ste,config = <&out_wkup_pdis>; +- }; +- }; +- }; +- +- /* Settings for all I2C default and sleep states */ +- i2c0 { +- i2c0_a_1_default: i2c0_a_1_default { +- default_mux { +- function = "i2c0"; +- groups = "i2c0_a_1"; +- }; +- default_cfg1 { +- pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ +- ste,config = <&in_nopull>; +- }; +- }; +- +- i2c0_a_1_sleep: i2c0_a_1_sleep { +- sleep_cfg1 { +- pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ +- ste,config = <&slpm_in_wkup_pdis>; +- }; +- }; +- }; +- +- i2c1 { +- i2c1_b_2_default: i2c1_b_2_default { +- default_mux { +- function = "i2c1"; +- groups = "i2c1_b_2"; +- }; +- default_cfg1 { +- pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ +- ste,config = <&in_nopull>; +- }; +- }; +- +- i2c1_b_2_sleep: i2c1_b_2_sleep { +- sleep_cfg1 { +- pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ +- ste,config = <&slpm_in_wkup_pdis>; +- }; +- }; +- }; +- +- i2c2 { +- i2c2_b_1_default: i2c2_b_1_default { +- default_mux { +- function = "i2c2"; +- groups = "i2c2_b_1"; +- }; +- default_cfg1 { +- pins = "GPIO8_AD5", "GPIO9_AE4"; /* SDA/SCL */ +- ste,config = <&in_nopull>; +- }; +- }; +- +- i2c2_b_1_sleep: i2c2_b_1_sleep { +- sleep_cfg1 { +- pins = "GPIO8_AD5", "GPIO9_AE4"; /* SDA/SCL */ +- ste,config = <&slpm_in_wkup_pdis>; +- }; +- }; +- +- i2c2_b_2_default: i2c2_b_2_default { +- default_mux { +- function = "i2c2"; +- groups = "i2c2_b_2"; +- }; +- default_cfg1 { +- pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ +- ste,config = <&in_nopull>; +- }; +- }; +- +- i2c2_b_2_sleep: i2c2_b_2_sleep { +- sleep_cfg1 { +- pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ +- ste,config = <&slpm_in_wkup_pdis>; +- }; +- }; +- }; +- +- i2c3 { +- i2c3_c_2_default: i2c3_c_2_default { +- default_mux { +- function = "i2c3"; +- groups = "i2c3_c_2"; +- }; +- default_cfg1 { +- pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ +- ste,config = <&in_nopull>; +- }; +- }; +- +- i2c3_c_2_sleep: i2c3_c_2_sleep { +- sleep_cfg1 { +- pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ +- ste,config = <&slpm_in_wkup_pdis>; +- }; +- }; +- }; +- +- /* +- * Activating I2C4 will conflict with UART1 about the same pins so do not +- * enable I2C4 and UART1 at the same time. +- */ +- i2c4 { +- i2c4_b_1_default: i2c4_b_1_default { +- default_mux { +- function = "i2c4"; +- groups = "i2c4_b_1"; +- }; +- default_cfg1 { +- pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ +- ste,config = <&in_nopull>; +- }; +- }; +- +- i2c4_b_1_sleep: i2c4_b_1_sleep { +- sleep_cfg1 { +- pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ +- ste,config = <&slpm_in_wkup_pdis>; +- }; +- }; +- }; +- +- /* Settings for all MMC/SD/SDIO default and sleep states */ +- sdi0 { +- /* This is the external SD card slot, 4 bits wide */ +- mc0_a_1_default: mc0_a_1_default { +- default_mux { +- function = "mc0"; +- groups = "mc0_a_1"; +- }; +- default_cfg1 { +- pins = +- "GPIO18_AC2", /* CMDDIR */ +- "GPIO19_AC1", /* DAT0DIR */ +- "GPIO20_AB4"; /* DAT2DIR */ +- ste,config = <&out_hi>; +- }; +- default_cfg2 { +- pins = "GPIO22_AA3"; /* FBCLK */ +- ste,config = <&in_nopull>; +- }; +- default_cfg3 { +- pins = "GPIO23_AA4"; /* CLK */ +- ste,config = <&out_lo>; +- }; +- default_cfg4 { +- pins = +- "GPIO24_AB2", /* CMD */ +- "GPIO25_Y4", /* DAT0 */ +- "GPIO26_Y2", /* DAT1 */ +- "GPIO27_AA2", /* DAT2 */ +- "GPIO28_AA1"; /* DAT3 */ +- ste,config = <&in_pu>; +- }; +- }; +- +- mc0_a_1_sleep: mc0_a_1_sleep { +- sleep_cfg1 { +- pins = +- "GPIO18_AC2", /* CMDDIR */ +- "GPIO19_AC1", /* DAT0DIR */ +- "GPIO20_AB4"; /* DAT2DIR */ +- ste,config = <&slpm_out_hi_wkup_pdis>; +- }; +- sleep_cfg2 { +- pins = +- "GPIO22_AA3", /* FBCLK */ +- "GPIO24_AB2", /* CMD */ +- "GPIO25_Y4", /* DAT0 */ +- "GPIO26_Y2", /* DAT1 */ +- "GPIO27_AA2", /* DAT2 */ +- "GPIO28_AA1"; /* DAT3 */ +- ste,config = <&slpm_in_wkup_pdis>; +- }; +- sleep_cfg3 { +- pins = "GPIO23_AA4"; /* CLK */ +- ste,config = <&slpm_out_lo_wkup_pdis>; +- }; +- }; +- +- mc0_a_2_default: mc0_a_2_default { +- default_mux { +- function = "mc0"; +- groups = "mc0_a_2"; +- }; +- default_cfg1 { +- pins = "GPIO22_AA3"; /* FBCLK */ +- ste,config = <&in_nopull>; +- }; +- default_cfg2 { +- pins = "GPIO23_AA4"; /* CLK */ +- ste,config = <&out_lo>; +- }; +- default_cfg3 { +- pins = +- "GPIO24_AB2", /* CMD */ +- "GPIO25_Y4", /* DAT0 */ +- "GPIO26_Y2", /* DAT1 */ +- "GPIO27_AA2", /* DAT2 */ +- "GPIO28_AA1"; /* DAT3 */ +- ste,config = <&in_pu>; +- }; +- }; +- +- mc0_a_2_sleep: mc0_a_2_sleep { +- sleep_cfg1 { +- pins = +- "GPIO22_AA3", /* FBCLK */ +- "GPIO24_AB2", /* CMD */ +- "GPIO25_Y4", /* DAT0 */ +- "GPIO26_Y2", /* DAT1 */ +- "GPIO27_AA2", /* DAT2 */ +- "GPIO28_AA1"; /* DAT3 */ +- ste,config = <&slpm_in_wkup_pdis>; +- }; +- sleep_cfg2 { +- pins = "GPIO23_AA4"; /* CLK */ +- ste,config = <&slpm_out_lo_wkup_pdis>; +- }; +- }; +- }; +- +- sdi1 { +- /* This is the WLAN SDIO 4 bits wide */ +- mc1_a_1_default: mc1_a_1_default { +- default_mux { +- function = "mc1"; +- groups = "mc1_a_1"; +- }; +- default_cfg1 { +- pins = "GPIO208_AH16"; /* CLK */ +- ste,config = <&out_lo>; +- }; +- default_cfg2 { +- pins = "GPIO209_AG15"; /* FBCLK */ +- ste,config = <&in_nopull>; +- }; +- default_cfg3 { +- pins = +- "GPIO210_AJ15", /* CMD */ +- "GPIO211_AG14", /* DAT0 */ +- "GPIO212_AF13", /* DAT1 */ +- "GPIO213_AG13", /* DAT2 */ +- "GPIO214_AH15"; /* DAT3 */ +- ste,config = <&in_pu>; +- }; +- }; +- +- mc1_a_1_sleep: mc1_a_1_sleep { +- sleep_cfg1 { +- pins = "GPIO208_AH16"; /* CLK */ +- ste,config = <&slpm_out_lo_wkup_pdis>; +- }; +- sleep_cfg2 { +- pins = +- "GPIO209_AG15", /* FBCLK */ +- "GPIO210_AJ15", /* CMD */ +- "GPIO211_AG14", /* DAT0 */ +- "GPIO212_AF13", /* DAT1 */ +- "GPIO213_AG13", /* DAT2 */ +- "GPIO214_AH15"; /* DAT3 */ +- ste,config = <&slpm_in_wkup_pdis>; +- }; +- }; +- +- mc1_a_2_default: mc1_a_2_default { +- default_mux { +- function = "mc1"; +- groups = "mc1_a_2"; +- }; +- default_cfg1 { +- pins = "GPIO208_AH16"; /* CLK */ +- ste,config = <&out_lo>; +- }; +- default_cfg2 { +- pins = +- "GPIO210_AJ15", /* CMD */ +- "GPIO211_AG14", /* DAT0 */ +- "GPIO212_AF13", /* DAT1 */ +- "GPIO213_AG13", /* DAT2 */ +- "GPIO214_AH15"; /* DAT3 */ +- ste,config = <&in_pu>; +- }; +- }; +- +- mc1_a_2_sleep: mc1_a_2_sleep { +- sleep_cfg1 { +- pins = "GPIO208_AH16"; /* CLK */ +- ste,config = <&slpm_out_lo_wkup_pdis>; +- }; +- sleep_cfg2 { +- pins = +- "GPIO210_AJ15", /* CMD */ +- "GPIO211_AG14", /* DAT0 */ +- "GPIO212_AF13", /* DAT1 */ +- "GPIO213_AG13", /* DAT2 */ +- "GPIO214_AH15"; /* DAT3 */ +- ste,config = <&slpm_in_wkup_pdis>; +- }; +- }; +- }; +- +- sdi2 { +- /* This is the eMMC 8 bits wide, usually PoP eMMC */ +- mc2_a_1_default: mc2_a_1_default { +- default_mux { +- function = "mc2"; +- groups = "mc2_a_1"; +- }; +- default_cfg1 { +- pins = "GPIO128_A5"; /* CLK */ +- ste,config = <&out_lo>; +- }; +- default_cfg2 { +- pins = "GPIO130_C8"; /* FBCLK */ +- ste,config = <&in_nopull>; +- }; +- default_cfg3 { +- pins = +- "GPIO129_B4", /* CMD */ +- "GPIO131_A12", /* DAT0 */ +- "GPIO132_C10", /* DAT1 */ +- "GPIO133_B10", /* DAT2 */ +- "GPIO134_B9", /* DAT3 */ +- "GPIO135_A9", /* DAT4 */ +- "GPIO136_C7", /* DAT5 */ +- "GPIO137_A7", /* DAT6 */ +- "GPIO138_C5"; /* DAT7 */ +- ste,config = <&in_pu>; +- }; +- }; +- +- mc2_a_1_sleep: mc2_a_1_sleep { +- sleep_cfg1 { +- pins = "GPIO128_A5"; /* CLK */ +- ste,config = <&out_lo_wkup_pdis>; +- }; +- sleep_cfg2 { +- pins = +- "GPIO130_C8", /* FBCLK */ +- "GPIO129_B4"; /* CMD */ +- ste,config = <&in_wkup_pdis_en>; +- }; +- sleep_cfg3 { +- pins = +- "GPIO131_A12", /* DAT0 */ +- "GPIO132_C10", /* DAT1 */ +- "GPIO133_B10", /* DAT2 */ +- "GPIO134_B9", /* DAT3 */ +- "GPIO135_A9", /* DAT4 */ +- "GPIO136_C7", /* DAT5 */ +- "GPIO137_A7", /* DAT6 */ +- "GPIO138_C5"; /* DAT7 */ +- ste,config = <&in_wkup_pdis>; +- }; +- }; +- }; +- +- sdi4 { +- /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */ +- mc4_a_1_default: mc4_a_1_default { +- default_mux { +- function = "mc4"; +- groups = "mc4_a_1"; +- }; +- default_cfg1 { +- pins = "GPIO203_AE23"; /* CLK */ +- ste,config = <&out_lo>; +- }; +- default_cfg2 { +- pins = "GPIO202_AF25"; /* FBCLK */ +- ste,config = <&in_nopull>; +- }; +- default_cfg3 { +- pins = +- "GPIO201_AF24", /* CMD */ +- "GPIO200_AH26", /* DAT0 */ +- "GPIO199_AH23", /* DAT1 */ +- "GPIO198_AG25", /* DAT2 */ +- "GPIO197_AH24", /* DAT3 */ +- "GPIO207_AJ23", /* DAT4 */ +- "GPIO206_AG24", /* DAT5 */ +- "GPIO205_AG23", /* DAT6 */ +- "GPIO204_AF23"; /* DAT7 */ +- ste,config = <&in_pu>; +- }; +- }; +- +- mc4_a_1_sleep: mc4_a_1_sleep { +- sleep_cfg1 { +- pins = "GPIO203_AE23"; /* CLK */ +- ste,config = <&out_lo_wkup_pdis>; +- }; +- sleep_cfg2 { +- pins = +- "GPIO202_AF25", /* FBCLK */ +- "GPIO201_AF24", /* CMD */ +- "GPIO200_AH26", /* DAT0 */ +- "GPIO199_AH23", /* DAT1 */ +- "GPIO198_AG25", /* DAT2 */ +- "GPIO197_AH24", /* DAT3 */ +- "GPIO207_AJ23", /* DAT4 */ +- "GPIO206_AG24", /* DAT5 */ +- "GPIO205_AG23", /* DAT6 */ +- "GPIO204_AF23"; /* DAT7 */ +- ste,config = <&slpm_in_wkup_pdis>; +- }; +- }; +- }; +- +- /* +- * Multi-rate serial ports (MSPs) - MSP3 output is internal and +- * cannot be muxed onto any pins. +- */ +- msp0 { +- msp0txrxtfstck_a_1_default: msp0txrxtfstck_a_1_default { +- default_msp0_mux { +- function = "msp0"; +- groups = "msp0txrx_a_1", "msp0tfstck_a_1"; +- }; +- default_msp0_cfg { +- pins = +- "GPIO12_AC4", /* TXD */ +- "GPIO15_AC3", /* RXD */ +- "GPIO13_AF3", /* TFS */ +- "GPIO14_AE3"; /* TCK */ +- ste,config = <&in_nopull>; +- }; +- }; +- }; +- +- msp1 { +- msp1txrx_a_1_default: msp1txrx_a_1_default { +- default_mux { +- function = "msp1"; +- groups = "msp1txrx_a_1", "msp1_a_1"; +- }; +- default_cfg1 { +- pins = "GPIO33_AF2"; +- ste,config = <&out_lo>; +- }; +- default_cfg2 { +- pins = +- "GPIO34_AE1", +- "GPIO35_AE2", +- "GPIO36_AG2"; +- ste,config = <&in_nopull>; +- }; +- }; +- }; +- +- msp2 { +- msp2_a_1_default: msp2_a_1_default { +- /* MSP2 usually used for HDMI audio */ +- default_mux { +- function = "msp2"; +- groups = "msp2_a_1"; +- }; +- default_cfg1 { +- pins = +- "GPIO193_AH27", /* TXD */ +- "GPIO194_AF27", /* TCK */ +- "GPIO195_AG28"; /* TFS */ +- ste,config = <&in_pd>; +- }; +- default_cfg2 { +- pins = "GPIO196_AG26"; /* RXD */ +- ste,config = <&out_lo>; +- }; +- }; +- }; +- +- musb { +- usb_a_1_default: usb_a_1_default { +- default_mux { +- function = "usb"; +- groups = "usb_a_1"; +- }; +- default_cfg1 { +- pins = +- "GPIO256_AF28", /* NXT */ +- "GPIO258_AD29", /* XCLK */ +- "GPIO259_AC29", /* DIR */ +- "GPIO260_AD28", /* DAT7 */ +- "GPIO261_AD26", /* DAT6 */ +- "GPIO262_AE26", /* DAT5 */ +- "GPIO263_AG29", /* DAT4 */ +- "GPIO264_AE27", /* DAT3 */ +- "GPIO265_AD27", /* DAT2 */ +- "GPIO266_AC28", /* DAT1 */ +- "GPIO267_AC27"; /* DAT0 */ +- ste,config = <&in_nopull>; +- }; +- default_cfg2 { +- pins = "GPIO257_AE29"; /* STP */ +- ste,config = <&out_hi>; +- }; +- }; +- +- usb_a_1_sleep: usb_a_1_sleep { +- sleep_cfg1 { +- pins = +- "GPIO256_AF28", /* NXT */ +- "GPIO258_AD29", /* XCLK */ +- "GPIO259_AC29"; /* DIR */ +- ste,config = <&slpm_wkup_pdis_en>; +- }; +- sleep_cfg2 { +- pins = "GPIO257_AE29"; /* STP */ +- ste,config = <&slpm_out_hi_wkup_pdis>; +- }; +- sleep_cfg3 { +- pins = +- "GPIO260_AD28", /* DAT7 */ +- "GPIO261_AD26", /* DAT6 */ +- "GPIO262_AE26", /* DAT5 */ +- "GPIO263_AG29", /* DAT4 */ +- "GPIO264_AE27", /* DAT3 */ +- "GPIO265_AD27", /* DAT2 */ +- "GPIO266_AC28", /* DAT1 */ +- "GPIO267_AC27"; /* DAT0 */ +- ste,config = <&slpm_in_wkup_pdis_en>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-dbx5x0.dtsi b/scripts/dtc/include-prefixes/arm/ste-dbx5x0.dtsi +deleted file mode 100644 +index 68607e4ad80c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-dbx5x0.dtsi ++++ /dev/null +@@ -1,1144 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 Linaro Ltd +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* This stablilizes the device enumeration */ +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- spi0 = &spi0; +- spi1 = &spi1; +- spi2 = &spi2; +- spi3 = &spi3; +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- }; +- +- chosen { +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- enable-method = "ste,dbx500-smp"; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&CPU0>; +- }; +- core1 { +- cpu = <&CPU1>; +- }; +- }; +- }; +- CPU0: cpu@300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0x300>; +- clocks = <&prcmu_clk PRCMU_ARMSS>; +- clock-names = "cpu"; +- clock-latency = <20000>; +- #cooling-cells = <2>; +- }; +- CPU1: cpu@301 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0x301>; +- }; +- }; +- +- thermal-zones { +- /* +- * Thermal zone for the SoC, using the thermal sensor in the +- * PRCMU for temperature and the cpufreq driver for passive +- * cooling. +- */ +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <250>; +- /* +- * This sensor fires interrupts to update the thermal +- * zone, so no polling is needed. +- */ +- polling-delay = <0>; +- +- thermal-sensors = <&thermal>; +- +- trips { +- cpu_alert: cpu-alert { +- temperature = <70000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu-crit { +- temperature = <85000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- trip = <&cpu_alert>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- contribution = <100>; +- }; +- }; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "stericsson,db8500", "simple-bus"; +- interrupt-parent = <&intc>; +- ranges; +- +- ptm@801ae000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0x801ae000 0x1000>; +- +- clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; +- clock-names = "apb_pclk", "atclk"; +- cpu = <&CPU0>; +- out-ports { +- port { +- ptm0_out_port: endpoint { +- remote-endpoint = <&funnel_in_port0>; +- }; +- }; +- }; +- }; +- +- ptm@801af000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0x801af000 0x1000>; +- +- clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; +- clock-names = "apb_pclk", "atclk"; +- cpu = <&CPU1>; +- out-ports { +- port { +- ptm1_out_port: endpoint { +- remote-endpoint = <&funnel_in_port1>; +- }; +- }; +- }; +- }; +- +- funnel@801a6000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0x801a6000 0x1000>; +- +- clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; +- clock-names = "apb_pclk", "atclk"; +- out-ports { +- port { +- funnel_out_port: endpoint { +- remote-endpoint = +- <&replicator_in_port0>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- funnel_in_port0: endpoint { +- remote-endpoint = <&ptm0_out_port>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- funnel_in_port1: endpoint { +- remote-endpoint = <&ptm1_out_port>; +- }; +- }; +- }; +- }; +- +- replicator { +- compatible = "arm,coresight-static-replicator"; +- clocks = <&prcmu_clk PRCMU_APEATCLK>; +- clock-names = "atclk"; +- +- out-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- replicator_out_port0: endpoint { +- remote-endpoint = <&tpiu_in_port>; +- }; +- }; +- port@1 { +- reg = <1>; +- replicator_out_port1: endpoint { +- remote-endpoint = <&etb_in_port>; +- }; +- }; +- }; +- +- in-ports { +- port { +- replicator_in_port0: endpoint { +- remote-endpoint = <&funnel_out_port>; +- }; +- }; +- }; +- }; +- +- tpiu@80190000 { +- compatible = "arm,coresight-tpiu", "arm,primecell"; +- reg = <0x80190000 0x1000>; +- +- clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; +- clock-names = "apb_pclk", "atclk"; +- in-ports { +- port { +- tpiu_in_port: endpoint { +- remote-endpoint = <&replicator_out_port0>; +- }; +- }; +- }; +- }; +- +- etb@801a4000 { +- compatible = "arm,coresight-etb10", "arm,primecell"; +- reg = <0x801a4000 0x1000>; +- +- clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; +- clock-names = "apb_pclk", "atclk"; +- in-ports { +- port { +- etb_in_port: endpoint { +- remote-endpoint = <&replicator_out_port1>; +- }; +- }; +- }; +- }; +- +- intc: interrupt-controller@a0411000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #address-cells = <1>; +- interrupt-controller; +- reg = <0xa0411000 0x1000>, +- <0xa0410100 0x100>; +- }; +- +- scu@a0410000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0xa0410000 0x100>; +- }; +- +- /* +- * The backup RAM is used for retention during sleep +- * and various things like spin tables +- */ +- backupram@80150000 { +- compatible = "ste,dbx500-backupram"; +- reg = <0x80150000 0x2000>; +- }; +- +- L2: cache-controller { +- compatible = "arm,pl310-cache"; +- reg = <0xa0412000 0x1000>; +- interrupts = ; +- cache-unified; +- cache-level = <2>; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = ; +- }; +- +- pm_domains: pm_domains0 { +- compatible = "stericsson,ux500-pm-domains"; +- #power-domain-cells = <1>; +- }; +- +- clocks { +- compatible = "stericsson,u8500-clks"; +- /* +- * Registers for the CLKRST block on peripheral +- * groups 1, 2, 3, 5, 6, +- */ +- reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, +- <0x8000f000 0x1000>, <0xa03ff000 0x1000>, +- <0xa03cf000 0x1000>; +- +- prcmu_clk: prcmu-clock { +- #clock-cells = <1>; +- }; +- +- prcc_pclk: prcc-periph-clock { +- #clock-cells = <2>; +- }; +- +- prcc_kclk: prcc-kernel-clock { +- #clock-cells = <2>; +- }; +- +- rtc_clk: rtc32k-clock { +- #clock-cells = <0>; +- }; +- +- smp_twd_clk: smp-twd-clock { +- #clock-cells = <0>; +- }; +- }; +- +- mtu@a03c6000 { +- /* Nomadik System Timer */ +- compatible = "st,nomadik-mtu"; +- reg = <0xa03c6000 0x1000>; +- interrupts = ; +- +- clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>; +- clock-names = "timclk", "apb_pclk"; +- }; +- +- timer@a0410600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0xa0410600 0x20>; +- interrupts = ; +- +- clocks = <&smp_twd_clk>; +- }; +- +- watchdog@a0410620 { +- compatible = "arm,cortex-a9-twd-wdt"; +- reg = <0xa0410620 0x20>; +- interrupts = ; +- clocks = <&smp_twd_clk>; +- }; +- +- rtc@80154000 { +- compatible = "arm,pl031", "arm,primecell"; +- reg = <0x80154000 0x1000>; +- interrupts = ; +- +- clocks = <&rtc_clk>; +- clock-names = "apb_pclk"; +- }; +- +- gpio0: gpio@8012e000 { +- compatible = "stericsson,db8500-gpio", +- "st,nomadik-gpio"; +- reg = <0x8012e000 0x80>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <2>; +- st,supports-sleepmode; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-bank = <0>; +- gpio-ranges = <&pinctrl 0 0 32>; +- clocks = <&prcc_pclk 1 9>; +- }; +- +- gpio1: gpio@8012e080 { +- compatible = "stericsson,db8500-gpio", +- "st,nomadik-gpio"; +- reg = <0x8012e080 0x80>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <2>; +- st,supports-sleepmode; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-bank = <1>; +- gpio-ranges = <&pinctrl 0 32 5>; +- clocks = <&prcc_pclk 1 9>; +- }; +- +- gpio2: gpio@8000e000 { +- compatible = "stericsson,db8500-gpio", +- "st,nomadik-gpio"; +- reg = <0x8000e000 0x80>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <2>; +- st,supports-sleepmode; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-bank = <2>; +- gpio-ranges = <&pinctrl 0 64 32>; +- clocks = <&prcc_pclk 3 8>; +- }; +- +- gpio3: gpio@8000e080 { +- compatible = "stericsson,db8500-gpio", +- "st,nomadik-gpio"; +- reg = <0x8000e080 0x80>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <2>; +- st,supports-sleepmode; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-bank = <3>; +- gpio-ranges = <&pinctrl 0 96 2>; +- clocks = <&prcc_pclk 3 8>; +- }; +- +- gpio4: gpio@8000e100 { +- compatible = "stericsson,db8500-gpio", +- "st,nomadik-gpio"; +- reg = <0x8000e100 0x80>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <2>; +- st,supports-sleepmode; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-bank = <4>; +- gpio-ranges = <&pinctrl 0 128 32>; +- clocks = <&prcc_pclk 3 8>; +- }; +- +- gpio5: gpio@8000e180 { +- compatible = "stericsson,db8500-gpio", +- "st,nomadik-gpio"; +- reg = <0x8000e180 0x80>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <2>; +- st,supports-sleepmode; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-bank = <5>; +- gpio-ranges = <&pinctrl 0 160 12>; +- clocks = <&prcc_pclk 3 8>; +- }; +- +- gpio6: gpio@8011e000 { +- compatible = "stericsson,db8500-gpio", +- "st,nomadik-gpio"; +- reg = <0x8011e000 0x80>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <2>; +- st,supports-sleepmode; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-bank = <6>; +- gpio-ranges = <&pinctrl 0 192 32>; +- clocks = <&prcc_pclk 2 11>; +- }; +- +- gpio7: gpio@8011e080 { +- compatible = "stericsson,db8500-gpio", +- "st,nomadik-gpio"; +- reg = <0x8011e080 0x80>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <2>; +- st,supports-sleepmode; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-bank = <7>; +- gpio-ranges = <&pinctrl 0 224 7>; +- clocks = <&prcc_pclk 2 11>; +- }; +- +- gpio8: gpio@a03fe000 { +- compatible = "stericsson,db8500-gpio", +- "st,nomadik-gpio"; +- reg = <0xa03fe000 0x80>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <2>; +- st,supports-sleepmode; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-bank = <8>; +- gpio-ranges = <&pinctrl 0 256 12>; +- clocks = <&prcc_pclk 5 1>; +- }; +- +- pinctrl: pinctrl { +- compatible = "stericsson,db8500-pinctrl"; +- nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>, +- <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>, +- <&gpio8>; +- prcm = <&prcmu>; +- }; +- +- usb_per5@a03e0000 { +- compatible = "stericsson,db8500-musb"; +- reg = <0xa03e0000 0x10000>; +- interrupts = ; +- interrupt-names = "mc"; +- +- dr_mode = "otg"; +- +- dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */ +- <&dma 38 0 0x0>, /* Logical - MemToDev */ +- <&dma 37 0 0x2>, /* Logical - DevToMem */ +- <&dma 37 0 0x0>, /* Logical - MemToDev */ +- <&dma 36 0 0x2>, /* Logical - DevToMem */ +- <&dma 36 0 0x0>, /* Logical - MemToDev */ +- <&dma 19 0 0x2>, /* Logical - DevToMem */ +- <&dma 19 0 0x0>, /* Logical - MemToDev */ +- <&dma 18 0 0x2>, /* Logical - DevToMem */ +- <&dma 18 0 0x0>, /* Logical - MemToDev */ +- <&dma 17 0 0x2>, /* Logical - DevToMem */ +- <&dma 17 0 0x0>, /* Logical - MemToDev */ +- <&dma 16 0 0x2>, /* Logical - DevToMem */ +- <&dma 16 0 0x0>, /* Logical - MemToDev */ +- <&dma 39 0 0x2>, /* Logical - DevToMem */ +- <&dma 39 0 0x0>; /* Logical - MemToDev */ +- +- dma-names = "iep_1_9", "oep_1_9", +- "iep_2_10", "oep_2_10", +- "iep_3_11", "oep_3_11", +- "iep_4_12", "oep_4_12", +- "iep_5_13", "oep_5_13", +- "iep_6_14", "oep_6_14", +- "iep_7_15", "oep_7_15", +- "iep_8", "oep_8"; +- +- clocks = <&prcc_pclk 5 0>; +- }; +- +- dma: dma-controller@801C0000 { +- compatible = "stericsson,db8500-dma40", "stericsson,dma40"; +- reg = <0x801C0000 0x1000 0x40010000 0x800>; +- reg-names = "base", "lcpa"; +- interrupts = ; +- +- #dma-cells = <3>; +- memcpy-channels = <56 57 58 59 60>; +- +- clocks = <&prcmu_clk PRCMU_DMACLK>; +- }; +- +- prcmu: prcmu@80157000 { +- compatible = "stericsson,db8500-prcmu", "syscon"; +- reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; +- reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ranges; +- +- prcmu-timer-4@80157450 { +- compatible = "stericsson,db8500-prcmu-timer-4"; +- reg = <0x80157450 0xC>; +- }; +- +- thermal: thermal@801573c0 { +- compatible = "stericsson,db8500-thermal"; +- reg = <0x801573c0 0x40>; +- interrupt-parent = <&prcmu>; +- interrupts = <21 IRQ_TYPE_LEVEL_HIGH>, +- <22 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; +- #thermal-sensor-cells = <0>; +- }; +- +- db8500-prcmu-regulators { +- compatible = "stericsson,db8500-prcmu-regulator"; +- +- // DB8500_REGULATOR_VAPE +- db8500_vape_reg: db8500_vape { +- regulator-always-on; +- }; +- +- // DB8500_REGULATOR_VARM +- db8500_varm_reg: db8500_varm { +- }; +- +- // DB8500_REGULATOR_VMODEM +- db8500_vmodem_reg: db8500_vmodem { +- }; +- +- // DB8500_REGULATOR_VPLL +- db8500_vpll_reg: db8500_vpll { +- }; +- +- // DB8500_REGULATOR_VSMPS1 +- db8500_vsmps1_reg: db8500_vsmps1 { +- }; +- +- // DB8500_REGULATOR_VSMPS2 +- db8500_vsmps2_reg: db8500_vsmps2 { +- }; +- +- // DB8500_REGULATOR_VSMPS3 +- db8500_vsmps3_reg: db8500_vsmps3 { +- }; +- +- // DB8500_REGULATOR_VRF1 +- db8500_vrf1_reg: db8500_vrf1 { +- }; +- +- // DB8500_REGULATOR_SWITCH_SVAMMDSP +- db8500_sva_mmdsp_reg: db8500_sva_mmdsp { +- }; +- +- // DB8500_REGULATOR_SWITCH_SVAMMDSPRET +- db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { +- }; +- +- // DB8500_REGULATOR_SWITCH_SVAPIPE +- db8500_sva_pipe_reg: db8500_sva_pipe { +- }; +- +- // DB8500_REGULATOR_SWITCH_SIAMMDSP +- db8500_sia_mmdsp_reg: db8500_sia_mmdsp { +- }; +- +- // DB8500_REGULATOR_SWITCH_SIAMMDSPRET +- db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { +- }; +- +- // DB8500_REGULATOR_SWITCH_SIAPIPE +- db8500_sia_pipe_reg: db8500_sia_pipe { +- }; +- +- // DB8500_REGULATOR_SWITCH_SGA +- db8500_sga_reg: db8500_sga { +- vin-supply = <&db8500_vape_reg>; +- }; +- +- // DB8500_REGULATOR_SWITCH_B2R2_MCDE +- db8500_b2r2_mcde_reg: db8500_b2r2_mcde { +- vin-supply = <&db8500_vape_reg>; +- }; +- +- // DB8500_REGULATOR_SWITCH_ESRAM12 +- db8500_esram12_reg: db8500_esram12 { +- }; +- +- // DB8500_REGULATOR_SWITCH_ESRAM12RET +- db8500_esram12_ret_reg: db8500_esram12_ret { +- }; +- +- // DB8500_REGULATOR_SWITCH_ESRAM34 +- db8500_esram34_reg: db8500_esram34 { +- }; +- +- // DB8500_REGULATOR_SWITCH_ESRAM34RET +- db8500_esram34_ret_reg: db8500_esram34_ret { +- }; +- }; +- }; +- +- i2c0: i2c@80004000 { +- compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; +- reg = <0x80004000 0x1000>; +- interrupts = ; +- +- #address-cells = <1>; +- #size-cells = <0>; +- v-i2c-supply = <&db8500_vape_reg>; +- +- clock-frequency = <400000>; +- clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; +- clock-names = "i2cclk", "apb_pclk"; +- power-domains = <&pm_domains DOMAIN_VAPE>; +- +- status = "disabled"; +- }; +- +- i2c1: i2c@80122000 { +- compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; +- reg = <0x80122000 0x1000>; +- interrupts = ; +- +- #address-cells = <1>; +- #size-cells = <0>; +- v-i2c-supply = <&db8500_vape_reg>; +- +- clock-frequency = <400000>; +- +- clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; +- clock-names = "i2cclk", "apb_pclk"; +- power-domains = <&pm_domains DOMAIN_VAPE>; +- +- status = "disabled"; +- }; +- +- i2c2: i2c@80128000 { +- compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; +- reg = <0x80128000 0x1000>; +- interrupts = ; +- +- #address-cells = <1>; +- #size-cells = <0>; +- v-i2c-supply = <&db8500_vape_reg>; +- +- clock-frequency = <400000>; +- +- clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; +- clock-names = "i2cclk", "apb_pclk"; +- power-domains = <&pm_domains DOMAIN_VAPE>; +- +- status = "disabled"; +- }; +- +- i2c3: i2c@80110000 { +- compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; +- reg = <0x80110000 0x1000>; +- interrupts = ; +- +- #address-cells = <1>; +- #size-cells = <0>; +- v-i2c-supply = <&db8500_vape_reg>; +- +- clock-frequency = <400000>; +- +- clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; +- clock-names = "i2cclk", "apb_pclk"; +- power-domains = <&pm_domains DOMAIN_VAPE>; +- +- status = "disabled"; +- }; +- +- i2c4: i2c@8012a000 { +- compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; +- reg = <0x8012a000 0x1000>; +- interrupts = ; +- +- #address-cells = <1>; +- #size-cells = <0>; +- v-i2c-supply = <&db8500_vape_reg>; +- +- clock-frequency = <400000>; +- +- clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; +- clock-names = "i2cclk", "apb_pclk"; +- power-domains = <&pm_domains DOMAIN_VAPE>; +- +- status = "disabled"; +- }; +- +- ssp0: spi@80002000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x80002000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; +- clock-names = "SSPCLK", "apb_pclk"; +- dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ +- <&dma 8 0 0x0>; /* Logical - MemToDev */ +- dma-names = "rx", "tx"; +- power-domains = <&pm_domains DOMAIN_VAPE>; +- +- status = "disabled"; +- }; +- +- ssp1: spi@80003000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x80003000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; +- clock-names = "SSPCLK", "apb_pclk"; +- dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ +- <&dma 9 0 0x0>; /* Logical - MemToDev */ +- dma-names = "rx", "tx"; +- power-domains = <&pm_domains DOMAIN_VAPE>; +- +- status = "disabled"; +- }; +- +- spi0: spi@8011a000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x8011a000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- /* Same clock wired to kernel and pclk */ +- clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; +- clock-names = "SSPCLK", "apb_pclk"; +- dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ +- <&dma 0 0 0x0>; /* Logical - MemToDev */ +- dma-names = "rx", "tx"; +- power-domains = <&pm_domains DOMAIN_VAPE>; +- +- status = "disabled"; +- }; +- +- spi1: spi@80112000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x80112000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- /* Same clock wired to kernel and pclk */ +- clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; +- clock-names = "SSPCLK", "apb_pclk"; +- dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ +- <&dma 35 0 0x0>; /* Logical - MemToDev */ +- dma-names = "rx", "tx"; +- power-domains = <&pm_domains DOMAIN_VAPE>; +- +- status = "disabled"; +- }; +- +- spi2: spi@80111000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x80111000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- /* Same clock wired to kernel and pclk */ +- clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; +- clock-names = "SSPCLK", "apb_pclk"; +- dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ +- <&dma 33 0 0x0>; /* Logical - MemToDev */ +- dma-names = "rx", "tx"; +- power-domains = <&pm_domains DOMAIN_VAPE>; +- +- status = "disabled"; +- }; +- +- spi3: spi@80129000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x80129000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- /* Same clock wired to kernel and pclk */ +- clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; +- clock-names = "SSPCLK", "apb_pclk"; +- dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ +- <&dma 40 0 0x0>; /* Logical - MemToDev */ +- dma-names = "rx", "tx"; +- power-domains = <&pm_domains DOMAIN_VAPE>; +- +- status = "disabled"; +- }; +- +- serial0: uart@80120000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x80120000 0x1000>; +- interrupts = ; +- +- dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ +- <&dma 13 0 0x0>; /* Logical - MemToDev */ +- dma-names = "rx", "tx"; +- +- clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>; +- clock-names = "uart", "apb_pclk"; +- +- status = "disabled"; +- }; +- +- serial1: uart@80121000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x80121000 0x1000>; +- interrupts = ; +- +- dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */ +- <&dma 12 0 0x0>; /* Logical - MemToDev */ +- dma-names = "rx", "tx"; +- +- clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>; +- clock-names = "uart", "apb_pclk"; +- +- status = "disabled"; +- }; +- +- serial2: uart@80007000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x80007000 0x1000>; +- interrupts = ; +- +- dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */ +- <&dma 11 0 0x0>; /* Logical - MemToDev */ +- dma-names = "rx", "tx"; +- +- clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>; +- clock-names = "uart", "apb_pclk"; +- +- status = "disabled"; +- }; +- +- mmc@80126000 { +- compatible = "arm,pl18x", "arm,primecell"; +- reg = <0x80126000 0x1000>; +- interrupts = ; +- +- dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */ +- <&dma 29 0 0x0>; /* Logical - MemToDev */ +- dma-names = "rx", "tx"; +- +- clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; +- clock-names = "sdi", "apb_pclk"; +- power-domains = <&pm_domains DOMAIN_VAPE>; +- +- status = "disabled"; +- }; +- +- mmc@80118000 { +- compatible = "arm,pl18x", "arm,primecell"; +- reg = <0x80118000 0x1000>; +- interrupts = ; +- +- dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */ +- <&dma 32 0 0x0>; /* Logical - MemToDev */ +- dma-names = "rx", "tx"; +- +- clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; +- clock-names = "sdi", "apb_pclk"; +- power-domains = <&pm_domains DOMAIN_VAPE>; +- +- status = "disabled"; +- }; +- +- mmc@80005000 { +- compatible = "arm,pl18x", "arm,primecell"; +- reg = <0x80005000 0x1000>; +- interrupts = ; +- +- dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */ +- <&dma 28 0 0x0>; /* Logical - MemToDev */ +- dma-names = "rx", "tx"; +- +- clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; +- clock-names = "sdi", "apb_pclk"; +- power-domains = <&pm_domains DOMAIN_VAPE>; +- +- status = "disabled"; +- }; +- +- mmc@80119000 { +- compatible = "arm,pl18x", "arm,primecell"; +- reg = <0x80119000 0x1000>; +- interrupts = ; +- +- dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */ +- <&dma 41 0 0x0>; /* Logical - MemToDev */ +- dma-names = "rx", "tx"; +- +- clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; +- clock-names = "sdi", "apb_pclk"; +- power-domains = <&pm_domains DOMAIN_VAPE>; +- +- status = "disabled"; +- }; +- +- mmc@80114000 { +- compatible = "arm,pl18x", "arm,primecell"; +- reg = <0x80114000 0x1000>; +- interrupts = ; +- +- dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */ +- <&dma 42 0 0x0>; /* Logical - MemToDev */ +- dma-names = "rx", "tx"; +- +- clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; +- clock-names = "sdi", "apb_pclk"; +- power-domains = <&pm_domains DOMAIN_VAPE>; +- +- status = "disabled"; +- }; +- +- mmc@80008000 { +- compatible = "arm,pl18x", "arm,primecell"; +- reg = <0x80008000 0x1000>; +- interrupts = ; +- +- dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */ +- <&dma 43 0 0x0>; /* Logical - MemToDev */ +- dma-names = "rx", "tx"; +- +- clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; +- clock-names = "sdi", "apb_pclk"; +- power-domains = <&pm_domains DOMAIN_VAPE>; +- +- status = "disabled"; +- }; +- +- sound { +- compatible = "stericsson,snd-soc-mop500"; +- stericsson,cpu-dai = <&msp1 &msp3>; +- }; +- +- msp0: msp@80123000 { +- compatible = "stericsson,ux500-msp-i2s"; +- reg = <0x80123000 0x1000>; +- interrupts = ; +- v-ape-supply = <&db8500_vape_reg>; +- +- dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */ +- <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */ +- dma-names = "rx", "tx"; +- +- clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; +- clock-names = "msp", "apb_pclk"; +- +- status = "disabled"; +- }; +- +- msp1: msp@80124000 { +- compatible = "stericsson,ux500-msp-i2s"; +- reg = <0x80124000 0x1000>; +- interrupts = ; +- v-ape-supply = <&db8500_vape_reg>; +- +- /* This DMA channel only exist on DB8500 v1 */ +- dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */ +- dma-names = "tx"; +- +- clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; +- clock-names = "msp", "apb_pclk"; +- +- status = "disabled"; +- }; +- +- // HDMI sound +- msp2: msp@80117000 { +- compatible = "stericsson,ux500-msp-i2s"; +- reg = <0x80117000 0x1000>; +- interrupts = ; +- v-ape-supply = <&db8500_vape_reg>; +- +- dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */ +- <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev +- HighPrio - Fixed */ +- dma-names = "rx", "tx"; +- +- clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; +- clock-names = "msp", "apb_pclk"; +- +- status = "disabled"; +- }; +- +- msp3: msp@80125000 { +- compatible = "stericsson,ux500-msp-i2s"; +- reg = <0x80125000 0x1000>; +- interrupts = ; +- v-ape-supply = <&db8500_vape_reg>; +- +- /* This DMA channel only exist on DB8500 v2 */ +- dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */ +- dma-names = "rx"; +- +- clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; +- clock-names = "msp", "apb_pclk"; +- +- status = "disabled"; +- }; +- +- external-bus@50000000 { +- compatible = "simple-bus"; +- reg = <0x50000000 0x4000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x50000000 0x4000000>; +- status = "disabled"; +- }; +- +- gpu@a0300000 { +- /* +- * This block is referred to as "Smart Graphics Adapter SGA500" +- * in documentation but is in practice a pretty straight-forward +- * MALI-400 GPU block. +- */ +- compatible = "stericsson,db8500-mali", "arm,mali-400"; +- reg = <0xa0300000 0x10000>; +- interrupts = , +- , +- , +- , +- ; +- interrupt-names = "gp", +- "gpmmu", +- "pp0", +- "ppmmu0", +- "combined"; +- clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>; +- clock-names = "bus", "core"; +- mali-supply = <&db8500_sga_reg>; +- power-domains = <&pm_domains DOMAIN_VAPE>; +- }; +- +- mcde@a0350000 { +- compatible = "ste,mcde"; +- reg = <0xa0350000 0x1000>; +- interrupts = ; +- epod-supply = <&db8500_b2r2_mcde_reg>; +- clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */ +- <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */ +- <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */ +- clock-names = "mcde", "lcd", "hdmi"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- +- dsi0: dsi@a0351000 { +- compatible = "ste,mcde-dsi"; +- reg = <0xa0351000 0x1000>; +- clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>; +- clock-names = "hs", "lp"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- dsi1: dsi@a0352000 { +- compatible = "ste,mcde-dsi"; +- reg = <0xa0352000 0x1000>; +- clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>; +- clock-names = "hs", "lp"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- dsi2: dsi@a0353000 { +- compatible = "ste,mcde-dsi"; +- reg = <0xa0353000 0x1000>; +- /* This DSI port only has the Low Power / Energy Save clock */ +- clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>; +- clock-names = "lp"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- cryp@a03cb000 { +- compatible = "stericsson,ux500-cryp"; +- reg = <0xa03cb000 0x1000>; +- interrupts = ; +- +- v-ape-supply = <&db8500_vape_reg>; +- clocks = <&prcc_pclk 6 1>; +- }; +- +- hash@a03c2000 { +- compatible = "stericsson,ux500-hash"; +- reg = <0xa03c2000 0x1000>; +- +- v-ape-supply = <&db8500_vape_reg>; +- clocks = <&prcc_pclk 6 2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-href-ab8500.dtsi b/scripts/dtc/include-prefixes/arm/ste-href-ab8500.dtsi +deleted file mode 100644 +index 3ccb7b5c7162..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-href-ab8500.dtsi ++++ /dev/null +@@ -1,424 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2014 Linaro Ltd. +- */ +- +-#include "ste-ab8500.dtsi" +- +-/ { +- soc { +- prcmu@80157000 { +- ab8500 { +- ab8500-gpiocontroller { +- /* Hog a few default settings */ +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio2_default_mode>, +- <&gpio4_default_mode>, +- <&gpio10_default_mode>, +- <&gpio11_default_mode>, +- <&gpio12_default_mode>, +- <&gpio13_default_mode>, +- <&gpio16_default_mode>, +- <&gpio24_default_mode>, +- <&gpio25_default_mode>, +- <&gpio36_default_mode>, +- <&gpio37_default_mode>, +- <&gpio38_default_mode>, +- <&gpio39_default_mode>, +- <&gpio42_default_mode>, +- <&gpio26_default_mode>, +- <&gpio35_default_mode>, +- <&ycbcr_default_mode>, +- <&pwm_default_mode>, +- <&adi1_default_mode>, +- <&usbuicc_default_mode>, +- <&dmic_default_mode>, +- <&extcpena_default_mode>, +- <&modsclsda_default_mode>; +- +- /* +- * Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42 +- * are muxed in as GPIO, and configured as INPUT PULL DOWN +- */ +- gpio2 { +- gpio2_default_mode: gpio2_default { +- default_mux { +- function = "gpio"; +- groups = "gpio2_a_1"; +- }; +- default_cfg { +- pins = "GPIO2_T9"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- gpio4 { +- gpio4_default_mode: gpio4_default { +- default_mux { +- function = "gpio"; +- groups = "gpio4_a_1"; +- }; +- default_cfg { +- pins = "GPIO4_W2"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- gpio10 { +- gpio10_default_mode: gpio10_default { +- default_mux { +- function = "gpio"; +- groups = "gpio10_d_1"; +- }; +- default_cfg { +- pins = "GPIO10_U17"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- gpio11 { +- gpio11_default_mode: gpio11_default { +- default_mux { +- function = "gpio"; +- groups = "gpio11_d_1"; +- }; +- default_cfg { +- pins = "GPIO11_AA18"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- gpio12 { +- gpio12_default_mode: gpio12_default { +- default_mux { +- function = "gpio"; +- groups = "gpio12_d_1"; +- }; +- default_cfg { +- pins = "GPIO12_U16"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- gpio13 { +- gpio13_default_mode: gpio13_default { +- default_mux { +- function = "gpio"; +- groups = "gpio13_d_1"; +- }; +- default_cfg { +- pins = "GPIO13_W17"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- gpio16 { +- gpio16_default_mode: gpio16_default { +- default_mux { +- function = "gpio"; +- groups = "gpio16_a_1"; +- }; +- default_cfg { +- pins = "GPIO16_F15"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- gpio24 { +- gpio24_default_mode: gpio24_default { +- default_mux { +- function = "gpio"; +- groups = "gpio24_a_1"; +- }; +- default_cfg { +- pins = "GPIO24_T14"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- gpio25 { +- gpio25_default_mode: gpio25_default { +- default_mux { +- function = "gpio"; +- groups = "gpio25_a_1"; +- }; +- default_cfg { +- pins = "GPIO25_R16"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- gpio36 { +- gpio36_default_mode: gpio36_default { +- default_mux { +- function = "gpio"; +- groups = "gpio36_a_1"; +- }; +- default_cfg { +- pins = "GPIO36_A17"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- gpio37 { +- gpio37_default_mode: gpio37_default { +- default_mux { +- function = "gpio"; +- groups = "gpio37_a_1"; +- }; +- default_cfg { +- pins = "GPIO37_E15"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- gpio38 { +- gpio38_default_mode: gpio38_default { +- default_mux { +- function = "gpio"; +- groups = "gpio38_a_1"; +- }; +- default_cfg { +- pins = "GPIO38_C17"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- gpio39 { +- gpio39_default_mode: gpio39_default { +- default_mux { +- function = "gpio"; +- groups = "gpio39_a_1"; +- }; +- default_cfg { +- pins = "GPIO39_E16"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- gpio42 { +- gpio42_default_mode: gpio42_default { +- default_mux { +- function = "gpio"; +- groups = "gpio42_a_1"; +- }; +- default_cfg { +- pins = "GPIO42_U2"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- /* +- * Pins 26 and 35 muxed in as GPIO, and configured as OUTPUT LOW +- */ +- gpio26 { +- gpio26_default_mode: gpio26_default { +- default_mux { +- function = "gpio"; +- groups = "gpio26_d_1"; +- }; +- default_cfg { +- pins = "GPIO26_M16"; +- output-low; +- }; +- }; +- }; +- gpio35 { +- gpio35_default_mode: gpio35_default { +- default_mux { +- function = "gpio"; +- groups = "gpio35_d_1"; +- }; +- default_cfg { +- pins = "GPIO35_W15"; +- output-low; +- }; +- }; +- }; +- /* +- * This sets up the YCBCR connector pins, i.e. analog video out. +- * Set as input with no bias. +- */ +- ycbcr { +- ycbcr_default_mode: ycbcr_default { +- default_mux { +- function = "ycbcr"; +- groups = "ycbcr0123_d_1"; +- }; +- default_cfg { +- pins = "GPIO6_Y18", +- "GPIO7_AA20", +- "GPIO8_W18", +- "GPIO9_AA19"; +- input-enable; +- bias-disable; +- }; +- }; +- }; +- /* This sets up the PWM pins 14 and 15 */ +- pwm { +- pwm_default_mode: pwm_default { +- default_mux { +- function = "pwmout"; +- groups = "pwmout1_d_1", "pwmout2_d_1"; +- }; +- default_cfg { +- pins = "GPIO14_F14", +- "GPIO15_B17"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- /* This sets up audio interface 1 */ +- adi1 { +- adi1_default_mode: adi1_default { +- default_mux { +- function = "adi1"; +- groups = "adi1_d_1"; +- }; +- default_cfg { +- pins = "GPIO17_P5", +- "GPIO18_R5", +- "GPIO19_U5", +- "GPIO20_T5"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- /* This sets up the USB UICC pins */ +- usbuicc { +- usbuicc_default_mode: usbuicc_default { +- default_mux { +- function = "usbuicc"; +- groups = "usbuicc_d_1"; +- }; +- default_cfg { +- pins = "GPIO21_H19", +- "GPIO22_G20", +- "GPIO23_G19"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- /* This sets up the microphone pins */ +- dmic { +- dmic_default_mode: dmic_default { +- default_mux { +- function = "dmic"; +- groups = "dmic12_d_1", +- "dmic34_d_1", +- "dmic56_d_1"; +- }; +- default_cfg { +- pins = "GPIO27_J6", +- "GPIO28_K6", +- "GPIO29_G6", +- "GPIO30_H6", +- "GPIO31_F5", +- "GPIO32_G5"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- extcpena { +- extcpena_default_mode: extcpena_default { +- default_mux { +- function = "extcpena"; +- groups = "extcpena_d_1"; +- }; +- default_cfg { +- pins = "GPIO34_R17"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- /* Modem I2C setup (SCL and SDA pins) */ +- modsclsda { +- modsclsda_default_mode: modsclsda_default { +- default_mux { +- function = "modsclsda"; +- groups = "modsclsda_d_1"; +- }; +- default_cfg { +- pins = "GPIO40_T19", +- "GPIO41_U19"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- /* +- * Clock output pins associated with regulators. +- */ +- sysclkreq2 { +- sysclkreq2_default_mode: sysclkreq2_default { +- default_mux { +- function = "sysclkreq"; +- groups = "sysclkreq2_d_1"; +- }; +- default_cfg { +- pins = "GPIO1_T10"; +- input-enable; +- bias-disable; +- }; +- }; +- sysclkreq2_sleep_mode: sysclkreq2_sleep { +- default_mux { +- function = "gpio"; +- groups = "gpio1_a_1"; +- }; +- default_cfg { +- pins = "GPIO1_T10"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- sysclkreq4 { +- sysclkreq4_default_mode: sysclkreq4_default { +- default_mux { +- function = "sysclkreq"; +- groups = "sysclkreq4_d_1"; +- }; +- default_cfg { +- pins = "GPIO3_U9"; +- input-enable; +- bias-disable; +- }; +- }; +- sysclkreq4_sleep_mode: sysclkreq4_sleep { +- default_mux { +- function = "gpio"; +- groups = "gpio3_a_1"; +- }; +- default_cfg { +- pins = "GPIO3_U9"; +- input-enable; +- bias-pull-down; +- }; +- }; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-href-family-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/ste-href-family-pinctrl.dtsi +deleted file mode 100644 +index 434fa6baf71f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-href-family-pinctrl.dtsi ++++ /dev/null +@@ -1,212 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Linaro Ltd. +- */ +- +-#include "ste-dbx5x0-pinctrl.dtsi" +- +-/ { +- soc { +- pinctrl { +- /* Settings for all SPI default and sleep states */ +- spi2 { +- spi2_default_mode: spi_default { +- default_mux { +- function = "spi2"; +- groups = "spi2_oc1_2"; +- }; +- default_cfg1 { +- pins = "GPIO216_AG12"; /* FRM */ +- ste,config = <&gpio_out_hi>; +- }; +- default_cfg2 { +- pins = "GPIO218_AH11"; /* RXD */ +- ste,config = <&in_pd>; +- }; +- default_cfg3 { +- pins = +- "GPIO215_AH13", /* TXD */ +- "GPIO217_AH12"; /* CLK */ +- ste,config = <&out_lo>; +- }; +- }; +- +- spi2_idle_mode: spi_idle { +- /* +- * The idle mode is basically sleep mode sans wakeups. Also +- * note that we have muxes the pins off the function here +- * as we do not state any muxing. +- */ +- idle_cfg1 { +- pins = "GPIO218_AH11"; /* RXD */ +- ste,config = <&slpm_in_pdis>; +- }; +- idle_cfg2 { +- pins = "GPIO215_AH13"; /* TXD */ +- ste,config = <&slpm_out_lo_pdis>; +- }; +- idle_cfg3 { +- pins = "GPIO217_AH12"; /* CLK */ +- ste,config = <&slpm_pdis>; +- }; +- }; +- +- spi2_sleep_mode: spi_sleep { +- sleep_cfg1 { +- pins = +- "GPIO216_AG12", /* FRM */ +- "GPIO218_AH11"; /* RXD */ +- ste,config = <&slpm_in_wkup_pdis>; +- }; +- sleep_cfg2 { +- pins = "GPIO215_AH13"; /* TXD */ +- ste,config = <&slpm_out_lo_wkup_pdis>; +- }; +- sleep_cfg3 { +- pins = "GPIO217_AH12"; /* CLK */ +- ste,config = <&slpm_wkup_pdis>; +- }; +- }; +- }; +- +- mcde { +- lcd_default_mode: lcd_default { +- default_mux1 { +- /* Mux in VSI0 and all the data lines */ +- function = "lcd"; +- groups = +- "lcdvsi0_a_1", /* VSI0 for LCD */ +- "lcd_d0_d7_a_1", /* Data lines */ +- "lcdvsi1_a_1"; /* VSI1 for HDMI */ +- }; +- default_mux2 { +- function = "lcda"; +- groups = +- "lcdaclk_b_1"; /* Clock line for TV-out */ +- }; +- default_cfg1 { +- pins = +- "GPIO68_E1", /* VSI0 */ +- "GPIO69_E2"; /* VSI1 */ +- ste,config = <&in_pu>; +- }; +- }; +- lcd_sleep_mode: lcd_sleep { +- sleep_cfg1 { +- pins = "GPIO69_E2"; /* VSI1 */ +- ste,config = <&slpm_in_wkup_pdis>; +- }; +- }; +- }; +- +- ske { +- /* SKE keys on position 2 in an 8x8 matrix */ +- ske_kpa2_default_mode: ske_kpa2_default { +- default_mux { +- function = "kp"; +- groups = "kp_a_2"; +- }; +- default_cfg1 { +- pins = +- "GPIO153_B17", /* I7 */ +- "GPIO154_C16", /* I6 */ +- "GPIO155_C19", /* I5 */ +- "GPIO156_C17", /* I4 */ +- "GPIO161_D21", /* I3 */ +- "GPIO162_D20", /* I2 */ +- "GPIO163_C20", /* I1 */ +- "GPIO164_B21"; /* I0 */ +- ste,config = <&in_pd>; +- }; +- default_cfg2 { +- pins = +- "GPIO157_A18", /* O7 */ +- "GPIO158_C18", /* O6 */ +- "GPIO159_B19", /* O5 */ +- "GPIO160_B20", /* O4 */ +- "GPIO165_C21", /* O3 */ +- "GPIO166_A22", /* O2 */ +- "GPIO167_B24", /* O1 */ +- "GPIO168_C22"; /* O0 */ +- ste,config = <&out_lo>; +- }; +- }; +- ske_kpa2_sleep_mode: ske_kpa2_sleep { +- sleep_cfg1 { +- pins = +- "GPIO153_B17", /* I7 */ +- "GPIO154_C16", /* I6 */ +- "GPIO155_C19", /* I5 */ +- "GPIO156_C17", /* I4 */ +- "GPIO161_D21", /* I3 */ +- "GPIO162_D20", /* I2 */ +- "GPIO163_C20", /* I1 */ +- "GPIO164_B21"; /* I0 */ +- ste,config = <&slpm_in_pu_wkup_pdis_en>; +- }; +- sleep_cfg2 { +- pins = +- "GPIO157_A18", /* O7 */ +- "GPIO158_C18", /* O6 */ +- "GPIO159_B19", /* O5 */ +- "GPIO160_B20", /* O4 */ +- "GPIO165_C21", /* O3 */ +- "GPIO166_A22", /* O2 */ +- "GPIO167_B24", /* O1 */ +- "GPIO168_C22"; /* O0 */ +- ste,config = <&slpm_out_lo_pdis>; +- }; +- }; +- /* +- * SKE keys on position 1 and "other C1" combi giving +- * six rows of six keys. +- */ +- ske_kpaoc1_default_mode: ske_kpaoc1_default { +- default_mux { +- function = "kp"; +- groups = "kp_a_1", "kp_oc1_1"; +- }; +- default_cfg1 { +- pins = +- "GPIO91_B6", /* KP_O0 */ +- "GPIO90_A3", /* KP_O1 */ +- "GPIO87_B3", /* KP_O2 */ +- "GPIO86_C6", /* KP_O3 */ +- "GPIO96_D8", /* KP_O6 */ +- "GPIO94_D7"; /* KP_O7 */ +- ste,config = <&out_lo>; +- }; +- default_cfg2 { +- pins = +- "GPIO93_B7", /* KP_I0 */ +- "GPIO92_D6", /* KP_I1 */ +- "GPIO89_E6", /* KP_I2 */ +- "GPIO88_C4", /* KP_I3 */ +- "GPIO97_D9", /* KP_I6 */ +- "GPIO95_E8"; /* KP_I7 */ +- ste,config = <&in_pu>; +- }; +- }; +- }; +- +- wlan { +- wlan_default_mode: wlan_default { +- /* +- * Activate this mode with the WLAN chip. +- * These are plain GPIO pins used by WLAN +- */ +- default_cfg1 { +- pins = +- "GPIO226_AF8", /* WLAN_PMU_EN */ +- "GPIO85_D5"; /* WLAN_ENA */ +- ste,config = <&gpio_out_lo>; +- }; +- default_cfg2 { +- pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */ +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-href-stuib.dtsi b/scripts/dtc/include-prefixes/arm/ste-href-stuib.dtsi +deleted file mode 100644 +index e32d0c36feb8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-href-stuib.dtsi ++++ /dev/null +@@ -1,212 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 ST-Ericsson AB +- */ +- +-#include +- +-/ { +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&prox_stuib_mode>, <&hall_stuib_mode>; +- +- button@139 { +- /* Proximity sensor */ +- gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>; +- linux,code = <11>; /* SW_FRONT_PROXIMITY */ +- label = "SFH7741 Proximity Sensor"; +- }; +- button@145 { +- /* Hall sensor */ +- gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; +- linux,code = <0>; /* SW_LID */ +- label = "HED54XXU11 Hall Effect Sensor"; +- }; +- }; +- +- soc { +- i2c@80004000 { +- stmpe1601: stmpe1601@40 { +- compatible = "st,stmpe1601"; +- reg = <0x40>; +- interrupts = <26 IRQ_TYPE_EDGE_FALLING>; +- interrupt-parent = <&gpio6>; +- interrupt-controller; +- vcc-supply = <&db8500_vsmps2_reg>; +- vio-supply = <&db8500_vsmps2_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&stmpe_stuib_mode>; +- +- wakeup-source; +- st,autosleep-timeout = <1024>; +- +- stmpe_keypad { +- compatible = "st,stmpe-keypad"; +- +- debounce-interval = <64>; +- st,scan-count = <8>; +- st,no-autorepeat; +- +- linux,keymap = <0x205006b +- 0x4010074 +- 0x3050072 +- 0x1030004 +- 0x502006a +- 0x500000a +- 0x5008b +- 0x706001c +- 0x405000b +- 0x6070003 +- 0x3040067 +- 0x303006c +- 0x60400e7 +- 0x602009e +- 0x4020073 +- 0x5050002 +- 0x4030069 +- 0x3020008>; +- }; +- }; +- }; +- +- /* Sensors mounted on this board variant */ +- i2c@80128000 { +- lis331dl@1c { +- /* Accelerometer */ +- compatible = "st,lis331dl-accel"; +- st,drdy-int-pin = <1>; +- reg = <0x1c>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vddio-supply = <&db8500_vsmps2_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&accel_stuib_mode>; +- interrupt-parent = <&gpio2>; +- interrupts = <18 IRQ_TYPE_EDGE_RISING>, +- <19 IRQ_TYPE_EDGE_RISING>; +- }; +- ak8974@f { +- /* Magnetometer */ +- compatible = "asahi-kasei,ak8974"; +- reg = <0x0f>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vddio-supply = <&db8500_vsmps2_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&magneto_stuib_mode>; +- interrupt-parent = <&gpio1>; +- interrupts = <0 IRQ_TYPE_EDGE_RISING>; +- }; +- }; +- +- i2c@80110000 { +- bu21013_tp@5c { +- compatible = "rohm,bu21013_tp"; +- reg = <0x5c>; +- avdd-supply = <&ab8500_ldo_aux1_reg>; +- +- rohm,touch-max-x = <384>; +- rohm,touch-max-y = <704>; +- rohm,flip-y; +- pinctrl-names = "default"; +- pinctrl-0 = <&touch_rohm_mode>; +- }; +- +- bu21013_tp@5d { +- compatible = "rohm,bu21013_tp"; +- reg = <0x5d>; +- avdd-supply = <&ab8500_ldo_aux1_reg>; +- +- rohm,touch-max-x = <384>; +- rohm,touch-max-y = <704>; +- rohm,flip-y; +- pinctrl-names = "default"; +- pinctrl-0 = <&touch_rohm_mode>; +- }; +- }; +- +- pinctrl { +- /* Pull up this GPIO pin */ +- stmpe { +- stmpe_stuib_mode: stmpe_stuib { +- stuib_cfg { +- ste,pins = "GPIO218_AH11"; +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- prox { +- prox_stuib_mode: prox_stuib { +- stuib_cfg { +- pins = "GPIO217_AH12"; +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- hall { +- hall_stuib_mode: stuib_tvk { +- stuib_cfg { +- pins = "GPIO145_C13"; +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- accelerometer { +- accel_stuib_mode: accel_stuib { +- /* Accelerometer interrupt lines 1 & 2 */ +- stuib_cfg { +- pins = "GPIO82_C1", "GPIO83_D3"; +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- magnetometer { +- magneto_stuib_mode: magneto_stuib { +- /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */ +- stuib_cfg1 { +- pins = "GPIO31_V3"; +- ste,config = <&gpio_in_pu>; +- }; +- stuib_cfg2 { +- pins = "GPIO32_V2"; +- ste,config = <&gpio_in_pd>; +- }; +- }; +- }; +- touch { +- touch_rohm_mode: touch_rohm { +- /* +- * ROHM touch screen uses GPIO 143 for +- * RST1, GPIO 146 for RST2 and +- * GPIO 67 for interrupts. Pull-up +- * the IRQ line and drive both +- * reset signals low. +- */ +- stuib_cfg1 { +- pins = "GPIO143_D12", "GPIO146_D13"; +- ste,config = <&gpio_out_lo>; +- }; +- stuib_cfg2 { +- pins = "GPIO67_G2"; +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- }; +- +- mcde@a0350000 { +- status = "okay"; +- +- dsi@a0351000 { +- panel { +- compatible = "samsung,s6d16d0"; +- reg = <0>; +- vdd1-supply = <&ab8500_ldo_aux1_reg>; +- reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-href-tvk1281618-r2.dtsi b/scripts/dtc/include-prefixes/arm/ste-href-tvk1281618-r2.dtsi +deleted file mode 100644 +index 37e59403c01f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-href-tvk1281618-r2.dtsi ++++ /dev/null +@@ -1,289 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Device Tree for the TVK1281618 R2 user interface board (UIB) +- */ +- +-#include +-#include +- +-/ { +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&prox_tvk_mode>, <&hall_tvk_mode>; +- +- button@139 { +- /* Proximity sensor */ +- gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>; +- linux,code = <11>; /* SW_FRONT_PROXIMITY */ +- label = "SFH7741 Proximity Sensor"; +- }; +- button@145 { +- /* Hall sensor */ +- gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; +- linux,code = <0>; /* SW_LID */ +- label = "HED54XXU11 Hall Effect Sensor"; +- }; +- }; +- +- soc { +- i2c@80004000 { +- tc35893@44 { +- compatible = "toshiba,tc35893"; +- reg = <0x44>; +- interrupt-parent = <&gpio6>; +- interrupts = <26 IRQ_TYPE_EDGE_RISING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tc35893_tvk_mode>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- status = "disabled"; +- +- tc3589x_gpio { +- compatible = "toshiba,tc3589x-gpio"; +- interrupts = <0>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- tc3589x_keypad { +- compatible = "toshiba,tc3589x-keypad"; +- interrupts = <6>; +- debounce-delay-ms = <4>; +- keypad,num-columns = <8>; +- keypad,num-rows = <8>; +- linux,no-autorepeat; +- wakeup-source; +- linux,keymap = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- }; +- }; +- }; +- +- i2c@80128000 { +- accelerometer@18 { +- /* Accelerometer */ +- compatible = "st,lsm303dlh-accel"; +- st,drdy-int-pin = <1>; +- drive-open-drain; +- reg = <0x18>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vddio-supply = <&db8500_vsmps2_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&accel_tvk_mode>; +- /* +- * These interrupts cannot be used: the other component +- * ST-Micro L3D4200D gyro that is connected to the same lines +- * cannot set its DRDY line to open drain, so it cannot be +- * shared with other peripherals. The should be defined for +- * the falling edge if they could be wired together. +- * +- * interrupts-extended = +- * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, +- * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>; +- */ +- mount-matrix = "0", "1", "0", +- "1", "0", "0", +- "0", "0", "-1"; +- }; +- magnetometer@1e { +- /* Magnetometer */ +- compatible = "st,lsm303dlh-magn"; +- reg = <0x1e>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vddio-supply = <&db8500_vsmps2_reg>; +- /* +- * These interrupts cannot be used: the other component +- * ST-Micro L3D4200D gyro that is connected to the same lines +- * cannot set its DRDY line to open drain, so it cannot be +- * shared with other peripherals. The should be defined for +- * the falling edge if they could be wired together. +- * +- * interrupts-extended = +- * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, +- * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>; +- */ +- }; +- accelerometer@1c { +- /* Accelerometer */ +- compatible = "st,lis331dl-accel"; +- st,drdy-int-pin = <1>; +- reg = <0x1c>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vddio-supply = <&db8500_vsmps2_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&accel_tvk_mode>; +- interrupt-parent = <&gpio2>; +- /* INT2 would need to be open drain */ +- interrupts = <18 IRQ_TYPE_EDGE_RISING>, +- <19 IRQ_TYPE_EDGE_RISING>; +- mount-matrix = "0", "-1", "0", +- "-1", "0", "0", +- "0", "0", "-1"; +- }; +- magnetometer@f { +- /* Magnetometer */ +- compatible = "asahi-kasei,ak8974"; +- reg = <0x0f>; +- avdd-supply = <&ab8500_ldo_aux1_reg>; +- dvdd-supply = <&db8500_vsmps2_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gyro_magn_tvk_mode>; +- /* +- * These interrupts cannot be used: the other component +- * ST-Micro L3D4200D gyro that is connected to the same lines +- * cannot set its DRDY line to open drain, so it cannot be +- * shared with other peripherals. The should be defined for +- * the falling edge if they could be wired together. +- * +- * interrupts-extended = +- * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, +- * <&gpio0 31 IRQ_TYPE_EDGE_FALLING>; +- */ +- }; +- gyroscope@68 { +- /* Gyroscope */ +- compatible = "st,l3g4200d-gyro"; +- st,drdy-int-pin = <2>; +- reg = <0x68>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vddio-supply = <&db8500_vsmps2_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gyro_magn_tvk_mode>; +- interrupts-extended = +- <&gpio1 0 IRQ_TYPE_EDGE_RISING>, +- <&gpio0 31 IRQ_TYPE_EDGE_RISING>; +- }; +- pressure@5c { +- /* Barometer/pressure sensor */ +- compatible = "st,lps001wp-press"; +- reg = <0x5c>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vddio-supply = <&db8500_vsmps2_reg>; +- }; +- }; +- i2c@80110000 { +- synaptics@4b { +- /* Synaptics RMI4 TM1217 touchscreen */ +- compatible = "syna,rmi4-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x4b>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vddio-supply = <&db8500_vsmps2_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&synaptics_tvk_mode>; +- interrupt-parent = <&gpio2>; +- interrupts = <20 IRQ_TYPE_EDGE_FALLING>; +- +- rmi4-f01@1 { +- reg = <0x1>; +- syna,nosleep = <1>; +- }; +- rmi4-f11@11 { +- reg = <0x11>; +- syna,sensor-type = <1>; +- /* This is a landscape display */ +- touchscreen-swapped-x-y; +- }; +- }; +- }; +- mcde@a0350000 { +- status = "okay"; +- +- dsi@a0351000 { +- panel { +- compatible = "samsung,s6d16d0"; +- reg = <0>; +- vdd1-supply = <&ab8500_ldo_aux1_reg>; +- reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +- }; +- }; +- }; +- pinctrl { +- prox { +- prox_tvk_mode: prox_tvk { +- tvk_cfg { +- pins = "GPIO217_AH12"; +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- hall { +- hall_tvk_mode: hall_tvk { +- tvk_cfg { +- pins = "GPIO145_C13"; +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- tc35893 { +- /* IRQ from the TC35893 */ +- tc35893_tvk_mode: tc35893_tvk { +- tvk_cfg { +- pins = "GPIO218_AH11"; +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- accelerometer { +- accel_tvk_mode: accel_tvk { +- /* Accelerometer interrupt lines 1 & 2 */ +- tvk_cfg { +- pins = "GPIO82_C1", "GPIO83_D3"; +- ste,config = <&gpio_in_pd>; +- }; +- }; +- }; +- gyroscope { +- /* +- * These lines are shared between Gyroscope l3g400dh +- * and AK8974 magnetometer. +- */ +- gyro_magn_tvk_mode: gyro_magn_tvk { +- /* GPIO 31 used for INT pull down the line */ +- tvk_cfg1 { +- pins = "GPIO31_V3"; +- ste,config = <&gpio_in_pd>; +- }; +- /* GPIO 32 used for DRDY, pull this down */ +- tvk_cfg2 { +- pins = "GPIO32_V2"; +- ste,config = <&gpio_in_pd>; +- }; +- }; +- }; +- synaptics { +- synaptics_tvk_mode: synaptics_tvk { +- /* Touchscreen uses GPIO 84 */ +- tvk_cfg1 { +- pins = "GPIO84_C2"; +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-href-tvk1281618-r3.dtsi b/scripts/dtc/include-prefixes/arm/ste-href-tvk1281618-r3.dtsi +deleted file mode 100644 +index 00ce9d79f540..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-href-tvk1281618-r3.dtsi ++++ /dev/null +@@ -1,220 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Device Tree for the TVK1281618 R3 user interface board (UIB) +- * also known as the "CYTTSP board" +- */ +- +-#include +-#include +- +-/ { +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hall_tvk_mode>; +- +- button@145 { +- /* Hall sensor */ +- gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; +- linux,code = <0>; /* SW_LID */ +- label = "HED54XXU11 Hall Effect Sensor"; +- }; +- }; +- +- soc { +- i2c@80004000 { +- tc35893@44 { +- compatible = "toshiba,tc35893"; +- reg = <0x44>; +- interrupt-parent = <&gpio2>; +- interrupts = <0 IRQ_TYPE_EDGE_RISING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tc35893_tvk_mode>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- status = "disabled"; +- +- tc3589x_gpio { +- compatible = "toshiba,tc3589x-gpio"; +- interrupts = <0>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- tc3589x_keypad { +- compatible = "toshiba,tc3589x-keypad"; +- interrupts = <6>; +- debounce-delay-ms = <4>; +- keypad,num-columns = <8>; +- keypad,num-rows = <8>; +- linux,no-autorepeat; +- wakeup-source; +- linux,keymap = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- }; +- }; +- }; +- +- i2c@80128000 { +- accelerometer@19 { +- compatible = "st,lsm303dlhc-accel"; +- st,drdy-int-pin = <1>; +- reg = <0x19>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vddio-supply = <&db8500_vsmps2_reg>; +- interrupt-parent = <&gpio2>; +- interrupts = <18 IRQ_TYPE_EDGE_RISING>, +- <19 IRQ_TYPE_EDGE_RISING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&accel_tvk_mode>; +- mount-matrix = "0", "-1", "0", +- "-1", "0", "0", +- "0", "0", "-1"; +- }; +- magnetometer@1e { +- compatible = "st,lsm303dlm-magn"; +- reg = <0x1e>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vddio-supply = <&db8500_vsmps2_reg>; +- // This interrupt is not properly working with the driver +- // interrupt-parent = <&gpio1>; +- // interrupts = <0 IRQ_TYPE_EDGE_RISING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&magn_tvk_mode>; +- }; +- gyroscope@68 { +- /* Gyroscope */ +- compatible = "st,l3g4200d-gyro"; +- reg = <0x68>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vddio-supply = <&db8500_vsmps2_reg>; +- }; +- pressure@5c { +- /* Barometer/pressure sensor */ +- compatible = "st,lps001wp-press"; +- reg = <0x5c>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vddio-supply = <&db8500_vsmps2_reg>; +- }; +- }; +- +- spi@80111000 { +- num-cs = <1>; +- cs-gpios = <&gpio6 24 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_default_mode>; +- status = "okay"; +- +- touchscreen@0 { +- compatible = "cypress,cy8ctma340"; +- /* +- * Actually the max frequency is 6 MHz, but over 2 MHz the +- * data rate needs to be restricted to max 2Mbps which the +- * SPI framework cannot handle. +- */ +- spi-max-frequency = <2000000>; +- reg = <0>; +- interrupt-parent = <&gpio2>; +- interrupts = <20 IRQ_TYPE_EDGE_FALLING>; +- vcpin-supply = <&ab8500_ldo_aux1_reg>; +- vdd-supply = <&db8500_vsmps2_reg>; +- reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; +- touchscreen-size-x = <480>; +- touchscreen-size-y = <854>; +- active-interval-ms = <0>; +- touch-timeout-ms = <255>; +- lowpower-interval-ms = <10>; +- bootloader-key = /bits/ 8 <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cyttsp_tvk_mode>; +- }; +- }; +- +- mcde@a0350000 { +- status = "okay"; +- +- dsi@a0351000 { +- panel { +- compatible = "sony,acx424akp"; +- reg = <0>; +- vddi-supply = <&ab8500_ldo_aux1_reg>; +- reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +- }; +- }; +- }; +- +- pinctrl { +- hall { +- hall_tvk_mode: hall_tvk { +- tvk_cfg { +- pins = "GPIO145_C13"; +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- tc35893 { +- /* IRQ from the TC35893 */ +- tc35893_tvk_mode: tc35893_tvk { +- tvk_cfg { +- pins = "GPIO64_F3"; +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- accelerometer { +- accel_tvk_mode: accel_tvk { +- /* Accelerometer interrupt lines 1 & 2 */ +- tvk_cfg { +- pins = "GPIO82_C1", "GPIO83_D3"; +- ste,config = <&gpio_in_pd>; +- }; +- }; +- }; +- magnetometer { +- magn_tvk_mode: magn_tvk { +- /* GPIO 32 used for DRDY, pull this down */ +- tvk_cfg { +- pins = "GPIO32_V2"; +- ste,config = <&gpio_in_pd>; +- }; +- }; +- }; +- cyttsp { +- cyttsp_tvk_mode: cyttsp_tvk { +- /* Touchscreen uses GPIO84 for IRQ */ +- tvk_cfg1 { +- pins = "GPIO84_C2"; +- ste,config = <&gpio_in_pu>; +- }; +- /* GPIO143 is reset */ +- tvk_cfg2 { +- pins = "GPIO143_D12"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-href.dtsi b/scripts/dtc/include-prefixes/arm/ste-href.dtsi +deleted file mode 100644 +index 961f2c7274ce..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-href.dtsi ++++ /dev/null +@@ -1,283 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 ST-Ericsson AB +- */ +- +-#include +-#include +-#include "ste-href-family-pinctrl.dtsi" +- +-/ { +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; +- }; +- +- soc { +- uart@80120000 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u0_a_1_default>; +- pinctrl-1 = <&u0_a_1_sleep>; +- status = "okay"; +- }; +- +- /* This UART is unused and thus left disabled */ +- uart@80121000 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u1rxtx_a_1_default>; +- pinctrl-1 = <&u1rxtx_a_1_sleep>; +- }; +- +- uart@80007000 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u2rxtx_c_1_default>; +- pinctrl-1 = <&u2rxtx_c_1_sleep>; +- status = "okay"; +- }; +- +- i2c@80004000 { +- pinctrl-names = "default","sleep"; +- pinctrl-0 = <&i2c0_a_1_default>; +- pinctrl-1 = <&i2c0_a_1_sleep>; +- status = "okay"; +- }; +- +- i2c@80122000 { +- pinctrl-names = "default","sleep"; +- pinctrl-0 = <&i2c1_b_2_default>; +- pinctrl-1 = <&i2c1_b_2_sleep>; +- status = "okay"; +- }; +- +- i2c@80128000 { +- pinctrl-names = "default","sleep"; +- pinctrl-0 = <&i2c2_b_2_default>; +- pinctrl-1 = <&i2c2_b_2_sleep>; +- status = "okay"; +- lp5521@33 { +- compatible = "national,lp5521"; +- reg = <0x33>; +- label = "lp5521_pri"; +- clock-mode = /bits/ 8 <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- chan@0 { +- reg = <0>; +- led-cur = /bits/ 8 <0x2f>; +- max-cur = /bits/ 8 <0x5f>; +- color = ; +- linux,default-trigger = "heartbeat"; +- }; +- chan@1 { +- reg = <1>; +- led-cur = /bits/ 8 <0x2f>; +- max-cur = /bits/ 8 <0x5f>; +- color = ; +- }; +- chan@2 { +- reg = <2>; +- led-cur = /bits/ 8 <0x2f>; +- max-cur = /bits/ 8 <0x5f>; +- color = ; +- }; +- }; +- lp5521@34 { +- compatible = "national,lp5521"; +- reg = <0x34>; +- label = "lp5521_sec"; +- clock-mode = /bits/ 8 <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- chan@0 { +- reg = <0>; +- led-cur = /bits/ 8 <0x2f>; +- max-cur = /bits/ 8 <0x5f>; +- color = ; +- }; +- chan@1 { +- reg = <1>; +- led-cur = /bits/ 8 <0x2f>; +- max-cur = /bits/ 8 <0x5f>; +- color = ; +- }; +- chan@2 { +- reg = <2>; +- led-cur = /bits/ 8 <0x2f>; +- max-cur = /bits/ 8 <0x5f>; +- color = ; +- }; +- }; +- bh1780@29 { +- compatible = "rohm,bh1780gli"; +- reg = <0x29>; +- }; +- }; +- +- i2c@80110000 { +- pinctrl-names = "default","sleep"; +- pinctrl-0 = <&i2c3_c_2_default>; +- pinctrl-1 = <&i2c3_c_2_sleep>; +- status = "okay"; +- }; +- +- // External Micro SD slot +- mmc@80126000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <100000000>; +- bus-width = <4>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- full-pwr-cycle; +- st,sig-dir-dat0; +- st,sig-dir-dat2; +- st,sig-dir-cmd; +- st,sig-pin-fbclk; +- vmmc-supply = <&ab8500_ldo_aux3_reg>; +- vqmmc-supply = <&vmmci>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc0_a_1_default &sdi0_default_mode>; +- pinctrl-1 = <&mc0_a_1_sleep>; +- +- status = "okay"; +- }; +- +- // WLAN SDIO channel +- mmc@80118000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <100000000>; +- bus-width = <4>; +- non-removable; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc1_a_1_default>; +- pinctrl-1 = <&mc1_a_1_sleep>; +- +- status = "okay"; +- }; +- +- // PoP:ed eMMC +- mmc@80005000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <100000000>; +- bus-width = <8>; +- cap-mmc-highspeed; +- non-removable; +- no-sdio; +- no-sd; +- vmmc-supply = <&db8500_vsmps2_reg>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc2_a_1_default>; +- pinctrl-1 = <&mc2_a_1_sleep>; +- +- status = "okay"; +- }; +- +- // On-board eMMC +- mmc@80114000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <100000000>; +- bus-width = <8>; +- cap-mmc-highspeed; +- non-removable; +- no-sdio; +- no-sd; +- vmmc-supply = <&ab8500_ldo_aux2_reg>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc4_a_1_default>; +- pinctrl-1 = <&mc4_a_1_sleep>; +- +- status = "okay"; +- }; +- +- msp0: msp@80123000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&msp0txrxtfstck_a_1_default>; +- status = "okay"; +- }; +- +- msp1: msp@80124000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&msp1txrx_a_1_default>; +- status = "okay"; +- }; +- +- msp2: msp@80117000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&msp2_a_1_default>; +- }; +- +- msp3: msp@80125000 { +- status = "okay"; +- }; +- +- prcmu@80157000 { +- ab8500 { +- ab8500-gpiocontroller { +- }; +- +- ab8500_usb { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&usb_a_1_default>; +- pinctrl-1 = <&usb_a_1_sleep>; +- }; +- +- ab8500-regulators { +- ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { +- regulator-name = "V-DISPLAY"; +- }; +- +- ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { +- regulator-name = "V-eMMC1"; +- }; +- +- ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { +- regulator-name = "V-MMC-SD"; +- }; +- +- ab8500_ldo_intcore_reg: ab8500_ldo_intcore { +- regulator-name = "V-INTCORE"; +- }; +- +- ab8500_ldo_tvout_reg: ab8500_ldo_tvout { +- regulator-name = "V-TVOUT"; +- }; +- +- ab8500_ldo_audio_reg: ab8500_ldo_audio { +- regulator-name = "V-AUD"; +- }; +- +- ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { +- regulator-name = "V-AMIC1"; +- }; +- +- ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { +- regulator-name = "V-AMIC2"; +- }; +- +- ab8500_ldo_dmic_reg: ab8500_ldo_dmic { +- regulator-name = "V-DMIC"; +- }; +- +- ab8500_ldo_ana_reg: ab8500_ldo_ana { +- regulator-name = "V-CSI/DSI"; +- }; +- }; +- }; +- }; +- +- pinctrl { +- sdi0 { +- sdi0_default_mode: sdi0_default { +- /* Some boards set additional settings here */ +- }; +- }; +- }; +- +- mcde@a0350000 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&lcd_default_mode>; +- pinctrl-1 = <&lcd_sleep_mode>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-href520-tvk.dts b/scripts/dtc/include-prefixes/arm/ste-href520-tvk.dts +deleted file mode 100644 +index 4201547c5988..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-href520-tvk.dts ++++ /dev/null +@@ -1,54 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Device Tree for the HREF520 version with the TVK1281618 R3 UIB +- */ +- +-/dts-v1/; +-#include "ste-db8520.dtsi" +-#include "ste-hrefv60plus.dtsi" +-#include "ste-href-tvk1281618-r3.dtsi" +- +-/ { +- model = "ST-Ericsson HREF520 and TVK1281618 R3 UIB"; +- compatible = "st-ericsson,href520", "st-ericsson,u8500"; +- +- +- /* ST6G3244ME level translator for 1.8/2.9 V */ +- vmmci: regulator-gpio { +- compatible = "regulator-gpio"; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2900000>; +- regulator-name = "mmci-reg"; +- regulator-type = "voltage"; +- +- startup-delay-us = <100>; +- +- states = <1800000 0x1 +- 2900000 0x0>; +- +- gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; +- enable-gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&vmmci_default_mode>; +- }; +-}; +- +-&pinctrl { +- vmmci { +- vmmci_default_mode: vmmc_default { +- /* VMMCI level-shifter enable */ +- default_href520_cfg1 { +- pins = "GPIO78_F4"; +- ste,config = <&gpio_out_hi>; +- }; +- /* VMMCI level-shifter voltage select */ +- default_href520_cfg2 { +- pins = "GPIO5_AG6"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-hrefprev60-stuib.dts b/scripts/dtc/include-prefixes/arm/ste-hrefprev60-stuib.dts +deleted file mode 100644 +index dfc933214c1a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-hrefprev60-stuib.dts ++++ /dev/null +@@ -1,52 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 ST-Ericsson AB +- */ +- +-/dts-v1/; +-#include "ste-db8500.dtsi" +-#include "ste-hrefprev60.dtsi" +-#include "ste-href-stuib.dtsi" +- +-/ { +- model = "ST-Ericsson HREF (pre-v60) and ST UIB"; +- compatible = "st-ericsson,mop500", "st-ericsson,u8500"; +- +- /* ST6G3244ME level translator for 1.8/2.9 V */ +- vmmci: regulator-gpio { +- compatible = "regulator-gpio"; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2900000>; +- regulator-name = "mmci-reg"; +- regulator-type = "voltage"; +- +- startup-delay-us = <100>; +- +- states = <1800000 0x1 +- 2900000 0x0>; +- +- gpios = <&tc3589x_gpio 18 GPIO_ACTIVE_HIGH>; +- enable-gpio = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- soc { +- /* Reset line for the BU21013 touchscreen */ +- i2c@80110000 { +- /* Only one of these will be used */ +- bu21013_tp@5c { +- interrupt-parent = <&gpio2>; +- interrupts = <12 IRQ_TYPE_LEVEL_LOW>; +- touch-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- reset-gpios = <&tc3589x_gpio 13 GPIO_LINE_OPEN_DRAIN>; +- }; +- bu21013_tp@5d { +- interrupt-parent = <&gpio2>; +- interrupts = <12 IRQ_TYPE_LEVEL_LOW>; +- touch-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- reset-gpios = <&tc3589x_gpio 13 GPIO_LINE_OPEN_DRAIN>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-hrefprev60-tvk.dts b/scripts/dtc/include-prefixes/arm/ste-hrefprev60-tvk.dts +deleted file mode 100644 +index 75506339a93c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-hrefprev60-tvk.dts ++++ /dev/null +@@ -1,33 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 ST-Ericsson AB +- */ +- +-/dts-v1/; +-#include "ste-db8500.dtsi" +-#include "ste-hrefprev60.dtsi" +-#include "ste-href-tvk1281618-r2.dtsi" +- +-/ { +- model = "ST-Ericsson HREF (pre-v60) and TVK1281618 R2 UIB"; +- compatible = "st-ericsson,mop500", "st-ericsson,u8500"; +- +- /* ST6G3244ME level translator for 1.8/2.9 V */ +- vmmci: regulator-gpio { +- compatible = "regulator-gpio"; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2900000>; +- regulator-name = "mmci-reg"; +- regulator-type = "voltage"; +- +- startup-delay-us = <100>; +- +- states = <1800000 0x1 +- 2900000 0x0>; +- +- gpios = <&tc3589x_gpio 18 GPIO_ACTIVE_HIGH>; +- enable-gpio = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-hrefprev60.dtsi b/scripts/dtc/include-prefixes/arm/ste-hrefprev60.dtsi +deleted file mode 100644 +index 29b67abfc461..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-hrefprev60.dtsi ++++ /dev/null +@@ -1,122 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 ST-Ericsson AB +- * +- * Device Tree for the HREF+ prior to the v60 variant. +- */ +- +-#include "ste-href-ab8500.dtsi" +-#include "ste-href.dtsi" +- +-/ { +- gpio_keys { +- button@1 { +- gpios = <&tc3589x_gpio 7 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- soc { +- /* Enable UART1 on this board */ +- uart@80121000 { +- status = "okay"; +- }; +- +- i2c@80004000 { +- tps61052@33 { +- compatible = "ti,tps61052"; +- reg = <0x33>; +- }; +- +- tc35892@42 { +- compatible = "toshiba,tc35892"; +- reg = <0x42>; +- interrupt-parent = <&gpio6>; +- interrupts = <25 IRQ_TYPE_EDGE_RISING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tc35892_hrefprev60_mode>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- tc3589x_gpio: tc3589x_gpio { +- compatible = "tc3589x-gpio"; +- interrupts = <0>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +- }; +- +- spi@80002000 { +- /* +- * On the first generation boards, this SSP/SPI port was connected +- * to the AB8500. +- */ +- pinctrl-names = "default"; +- pinctrl-0 = <&ssp0_hrefprev60_mode>; +- status = "okay"; +- }; +- +- // External Micro SD slot +- mmc@80126000 { +- cd-gpios = <&tc3589x_gpio 3 GPIO_ACTIVE_HIGH>; +- }; +- +- pinctrl { +- /* Set this up using hogs */ +- pinctrl-names = "default"; +- pinctrl-0 = <&ipgpio_hrefprev60_mode>; +- +- ssp0 { +- ssp0_hrefprev60_mode: ssp0_hrefprev60_default { +- hrefprev60_mux { +- function = "ssp0"; +- groups = "ssp0_a_1"; +- }; +- hrefprev60_cfg1 { +- pins = "GPIO145_C13"; /* RXD */ +- ste,config = <&in_pd>; +- }; +- +- }; +- }; +- sdi0 { +- /* This additional pin needed on early MOP500 and HREFs previous to v60 */ +- sdi0_default_mode: sdi0_default { +- hrefprev60_mux { +- function = "mc0"; +- groups = "mc0dat31dir_a_1"; +- }; +- hrefprev60_cfg1 { +- pins = "GPIO21_AB3"; /* DAT31DIR */ +- ste,config = <&out_hi>; +- }; +- +- }; +- }; +- tc35892 { +- tc35892_hrefprev60_mode: tc35892_hrefprev60 { +- hrefprev60_cfg { +- pins = "GPIO217_AH12"; +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- ipgpio { +- ipgpio_hrefprev60_mode: ipgpio_hrefprev60 { +- hrefprev60_mux { +- function = "ipgpio"; +- groups = "ipgpio0_c_1", "ipgpio1_c_1"; +- }; +- hrefprev60_cfg1 { +- pins = "GPIO6_AF6", "GPIO7_AG5"; +- ste,config = <&in_pu>; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-hrefv60plus-stuib.dts b/scripts/dtc/include-prefixes/arm/ste-hrefv60plus-stuib.dts +deleted file mode 100644 +index 52c56ed17ae6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-hrefv60plus-stuib.dts ++++ /dev/null +@@ -1,74 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 ST-Ericsson AB +- * +- * Device Tree for the HREF version 60 or later with the ST UIB +- */ +- +-/dts-v1/; +-#include "ste-db8500.dtsi" +-#include "ste-hrefv60plus.dtsi" +-#include "ste-href-stuib.dtsi" +- +-/ { +- model = "ST-Ericsson HREF (v60+) and ST UIB"; +- compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; +- +- /* ST6G3244ME level translator for 1.8/2.9 V */ +- vmmci: regulator-gpio { +- compatible = "regulator-gpio"; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2900000>; +- regulator-name = "mmci-reg"; +- regulator-type = "voltage"; +- +- startup-delay-us = <100>; +- +- states = <1800000 0x1 +- 2900000 0x0>; +- +- gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; +- enable-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&vmmci_default_mode>; +- }; +- +- soc { +- /* Reset line for the BU21013 touchscreen */ +- i2c@80110000 { +- /* Only one of these will be used */ +- bu21013_tp@5c { +- interrupt-parent = <&gpio2>; +- interrupts = <20 IRQ_TYPE_LEVEL_LOW>; +- touch-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; +- reset-gpios = <&gpio4 17 GPIO_LINE_OPEN_DRAIN>; +- }; +- bu21013_tp@5d { +- interrupt-parent = <&gpio2>; +- interrupts = <20 IRQ_TYPE_LEVEL_LOW>; +- touch-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; +- reset-gpios = <&gpio4 17 GPIO_LINE_OPEN_DRAIN>; +- }; +- }; +- }; +-}; +- +-&pinctrl { +- vmmci { +- vmmci_default_mode: vmmc_default { +- /* VMMCI level-shifter enable */ +- default_hrefv60_cfg2 { +- pins = "GPIO169_D22"; +- ste,config = <&gpio_out_hi>; +- }; +- /* VMMCI level-shifter voltage select */ +- default_hrefv60_cfg3 { +- pins = "GPIO5_AG6"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-hrefv60plus-tvk.dts b/scripts/dtc/include-prefixes/arm/ste-hrefv60plus-tvk.dts +deleted file mode 100644 +index 2db2f8be8b03..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-hrefv60plus-tvk.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 ST-Ericsson AB +- * +- * Device Tree for the HREF version 60 or later with the TVK1281618 R2 UIB +- */ +- +-/dts-v1/; +-#include "ste-db8500.dtsi" +-#include "ste-hrefv60plus.dtsi" +-#include "ste-href-tvk1281618-r2.dtsi" +- +-/ { +- model = "ST-Ericsson HREF (v60+) and TVK1281618 R2 UIB"; +- compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; +- +- /* ST6G3244ME level translator for 1.8/2.9 V */ +- vmmci: regulator-gpio { +- compatible = "regulator-gpio"; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2900000>; +- regulator-name = "mmci-reg"; +- regulator-type = "voltage"; +- +- startup-delay-us = <100>; +- +- states = <1800000 0x1 +- 2900000 0x0>; +- +- gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; +- enable-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&vmmci_default_mode>; +- }; +-}; +- +-&pinctrl { +- vmmci { +- vmmci_default_mode: vmmc_default { +- /* VMMCI level-shifter enable */ +- default_hrefv60_cfg2 { +- pins = "GPIO169_D22"; +- ste,config = <&gpio_out_hi>; +- }; +- /* VMMCI level-shifter voltage select */ +- default_hrefv60_cfg3 { +- pins = "GPIO5_AG6"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-hrefv60plus.dtsi b/scripts/dtc/include-prefixes/arm/ste-hrefv60plus.dtsi +deleted file mode 100644 +index 8f504edefd3f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-hrefv60plus.dtsi ++++ /dev/null +@@ -1,377 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 ST-Ericsson AB +- */ +- +-#include "ste-href-ab8500.dtsi" +-#include "ste-href.dtsi" +- +-/ { +- model = "ST-Ericsson HREF (v60+) platform with Device Tree"; +- compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; +- +- thermal-zones { +- chassis-thermal { +- /* Poll every 20 seconds */ +- polling-delay = <20000>; +- /* Poll every 2nd second when cooling */ +- polling-delay-passive = <2000>; +- +- thermal-sensors = <&therm1>, <&therm2>; +- +- /* Tripping points made from rough guess about operating conditions */ +- trips { +- chassis_alert: chassis-alert { +- /* At 50 degrees take down the CPU frequency */ +- temperature = <50000>; +- hysteresis = <3000>; +- type = "active"; +- }; +- chassis_crit: chassis-crit { +- /* Just shut down at 70 degrees */ +- temperature = <70000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- /* Push down the operating frequency of the SoC when it gets hot */ +- cooling-maps { +- map0 { +- trip = <&chassis_alert>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- contribution = <100>; +- }; +- }; +- }; +- }; +- +- /* +- * Thermistors on the board, formally to monitor battery temperatures +- * but what they measure is the board temperature. +- */ +- therm1: thermistor@0 { +- compatible = "murata,ncp18wb473"; +- io-channels = <&gpadc 0x06>; /* AUX1 */ +- pullup-uv = <1800000>; +- pullup-ohm = <220000>; +- pulldown-ohm = <0>; +- #thermal-sensor-cells = <0>; +- }; +- +- therm2: thermistor@1 { +- compatible = "murata,ncp18wb473"; +- io-channels = <&gpadc 0x07>; /* AUX2 */ +- pullup-uv = <1800000>; +- pullup-ohm = <220000>; +- pulldown-ohm = <0>; +- #thermal-sensor-cells = <0>; +- }; +- +- soc { +- /* Name the GPIO muxed rails on the HREF boards */ +- gpio@8012e000 { +- /* GPIOs 0 - 31 */ +- gpio-line-names = +- /* GPIO0,1 used for UART0 BT RX/TX */ +- "", "", +- "UART_WAKE", +- "BT_WAKE", +- "", +- "SDMMC_1V8_3V_SEL", +- "FLASH_LED_SYNC (FLASH_CTRL_0)", +- "XENON_READY (FLASH_CTRL_1)", +- "", "", "", "", "", "", "", "", +- "", "", "", "", +- "", +- "FLASH_LED_EN (FLASH_CTRL_3)", +- "", "", +- "", "", "", "", "", +- /* Used by UART2 (console) */ +- "", "", +- "MAGNETOMETER_INT"; +- }; +- +- gpio@8012e080 { +- /* GPIOs 32 - 63 */ +- gpio-line-names = +- "MAGNETOMETER_DRDY", +- "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +- }; +- +- gpio@8000e000 { +- /* GPIOs 64 - 95 */ +- gpio-line-names = "XENON_EN2 (FLASH_CTRL_4)", +- "DISP1_RST", +- "DISP2_RST", +- "TOUCH_INT2", +- "LCD_VSI0_A", +- "LCD_VSI1_A", +- /* GPIO 70-77 used for ETM */ +- "", "", "", "", "", "", "", "", +- /* GPIO 78-81 used for YCBCR */ +- "", "", "", "", +- "ACCELEROMETER_INT1_RDY", +- "ACCELEROMETER_INT2", +- "TOUCH_INT", +- "WLAN_ENA", +- "", "", "", "", "", +- "FORCE_SENSING_INT", +- "FORCE_SENSING_RESET", +- "", "", +- "SDMMC_CD"; +- }; +- +- gpio@8000e080 { +- /* GPIOs 96 - 127 */ +- gpio-line-names = "", +- "FORCE_SENSING_WU", +- "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +- }; +- +- gpio@8000e100 { +- /* GPIOs 128 - 159 */ +- gpio-line-names = "", "", "", "", "", "", "", "", +- "", "", "", +- "DIPRO_INT", /* GPIO139 */ +- "XSHUTDOWN_SECONDARY_SENSOR", +- "XSHUTDOWN_PRIMARY_SENSOR", +- "NFC_RST (NFC_CTRL_", +- "TOUCH_RST", +- "NFC_IRQ (NFC_CTRL_1)", +- "HAL_SW", +- "TOUCH_RST2", +- "", "", +- "VAUDIO_HF_EN", /* GPIO149 */ +- "", "", "", "", "", "", "", "", "", ""; +- }; +- +- gpio@8000e180 { +- /* GPIOs 160 - 191 */ +- gpio-line-names = "", "", "", "", "", "", "", "", +- "", +- "SDMMC_EN", +- "XENON_CHARGE (FLASH_CONTROL_5)", +- "GBF_ENA_RESET", +- "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +- }; +- +- gpio@8011e000 { +- /* GPIOs 192 - 223 */ +- gpio-line-names = "HDTV_INTN", +- "", "", "", +- "HDTV_RSTN", +- "", "", "", +- "", /* GPIO200 */ +- "", "", "", "", "", "", "", +- /* GPIO208-216 used for WGBF_MC1 */ +- "", "", "", "", "", "", "", "", "", +- "SW_FRONT_PROXIMITY", /* GPIO217 */ +- "KPD_CTRL_INT", /* Keypad controller */ +- "", "", "", "", ""; +- }; +- +- gpio@8011e080 { +- /* GPIOs 224 - 255 */ +- gpio-line-names = "", "", +- "HSIT_ACWAKE0", +- "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +- }; +- +- // External Micro SD slot +- mmc@80126000 { +- cd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; // 95 +- }; +- +- pinctrl { +- /* +- * Set this up using hogs, as time goes by and as seems fit, these +- * can be moved over to being controlled by respective device. +- */ +- pinctrl-names = "default"; +- pinctrl-0 = <&ipgpio_hrefv60_mode>, +- <&etm_hrefv60_mode>, +- <&nahj_hrefv60_mode>, +- <&nfc_hrefv60_mode>, +- <&force_hrefv60_mode>, +- <&dipro_hrefv60_mode>, +- <&vaudio_hf_hrefv60_mode>, +- <&gbf_hrefv60_mode>, +- <&hdtv_hrefv60_mode>, +- <&gpios_hrefv60_mode>; +- +- sdi0 { +- sdi0_default_mode: sdi0_default { +- /* SD card detect GPIO pin, extend default state */ +- default_hrefv60_cfg1 { +- pins = "GPIO95_E8"; +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- ipgpio { +- /* +- * XENON Flashgun on image processor GPIO (controlled from image +- * processor firmware), mux in these image processor GPIO lines 0 +- * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant +- * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias +- * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output. +- */ +- ipgpio_hrefv60_mode: ipgpio_hrefv60 { +- hrefv60_mux { +- function = "ipgpio"; +- groups = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1"; +- }; +- hrefv60_cfg1 { +- pins = "GPIO6_AF6", "GPIO7_AG5"; +- ste,config = <&in_pu>; +- }; +- hrefv60_cfg2 { +- pins = "GPIO21_AB3"; +- ste,config = <&gpio_out_lo>; +- }; +- hrefv60_cfg3 { +- pins = "GPIO64_F3"; +- ste,config = <&out_lo>; +- }; +- }; +- }; +- etm { +- /* +- * Drive D19-D23 for the ETM PTM trace interface low, +- * (presumably pins are unconnected therefore grounded here, +- * the "other alt C1" setting enables these pins) +- */ +- etm_hrefv60_mode: etm_hrefv60 { +- hrefv60_cfg1 { +- pins = +- "GPIO70_G5", +- "GPIO71_G4", +- "GPIO72_H4", +- "GPIO73_H3", +- "GPIO74_J3"; +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- nahj { +- nahj_hrefv60_mode: nahj_hrefv60 { +- /* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */ +- hrefv60_cfg1 { +- pins = "GPIO76_J2"; +- ste,config = <&gpio_out_lo>; +- }; +- hrefv60_cfg2 { +- pins = "GPIO216_AG12"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- nfc { +- nfc_hrefv60_mode: nfc_hrefv60 { +- /* NFC ENA and RESET to low, pulldown IRQ line */ +- hrefv60_cfg1 { +- pins = +- "GPIO77_H1", /* NFC_ENA */ +- "GPIO142_C11"; /* NFC_RESET */ +- ste,config = <&gpio_out_lo>; +- }; +- hrefv60_cfg2 { +- pins = "GPIO144_B13"; /* NFC_IRQ */ +- ste,config = <&gpio_in_pd>; +- }; +- }; +- }; +- force { +- force_hrefv60_mode: force_hrefv60 { +- hrefv60_cfg1 { +- pins = "GPIO91_B6"; /* FORCE_SENSING_INT */ +- ste,config = <&gpio_in_pu>; +- }; +- hrefv60_cfg2 { +- pins = +- "GPIO92_D6", /* FORCE_SENSING_RST */ +- "GPIO97_D9"; /* FORCE_SENSING_WU */ +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- dipro { +- dipro_hrefv60_mode: dipro_hrefv60 { +- hrefv60_cfg1 { +- pins = "GPIO139_C9"; /* DIPRO_INT */ +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- vaudio_hf { +- vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 { +- /* Audio Amplifier HF enable GPIO */ +- hrefv60_cfg1 { +- pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */ +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- gbf { +- gbf_hrefv60_mode: gbf_hrefv60 { +- /* +- * GBF (GPS, Bluetooth, FM-radio) interface, +- * pull low to reset state +- */ +- hrefv60_cfg1 { +- pins = "GPIO171_D23"; /* GBF_ENA_RESET */ +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- hdtv { +- hdtv_hrefv60_mode: hdtv_hrefv60 { +- /* MSP : HDTV INTERFACE GPIO line */ +- hrefv60_cfg1 { +- pins = "GPIO192_AJ27"; +- ste,config = <&gpio_in_pd>; +- }; +- }; +- }; +- mcde { +- lcd_hrefv60_mode: lcd_hrefv60 { +- /* +- * Display Interface 1 uses GPIO 65 for RST (reset). +- * Display Interface 2 uses GPIO 66 for RST (reset). +- * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset) +- */ +- hrefv60_cfg1 { +- pins ="GPIO65_F1"; +- ste,config = <&gpio_out_hi>; +- }; +- hrefv60_cfg2 { +- pins ="GPIO66_G3"; +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- gpios { +- /* Dangling GPIO pins */ +- gpios_hrefv60_mode: gpios_hrefv60 { +- default_cfg1 { +- /* Normally UART1 RXD, now dangling */ +- pins = "GPIO4_AH6"; +- ste,config = <&in_pu>; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-nomadik-nhk15.dts b/scripts/dtc/include-prefixes/arm/ste-nomadik-nhk15.dts +deleted file mode 100644 +index 8142c017882c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-nomadik-nhk15.dts ++++ /dev/null +@@ -1,266 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree for the ST Microelectronics Nomadik NHK8815 board +- */ +- +-/dts-v1/; +-#include +-#include +-#include "ste-nomadik-stn8815.dtsi" +- +-/ { +- model = "Nomadik STN8815NHK"; +- compatible = "st,nomadik-nhk-15"; +- +- chosen { +- bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk"; +- }; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- stmpe-i2c0 = &stmpe0; +- stmpe-i2c1 = &stmpe1; +- }; +- +- pinctrl { +- uart0 { +- uart0_nhk_mode: uart0_mux { +- u0_default_mux { +- function = "u0"; +- groups = "u0txrx_a_1", "u0ctsrts_a_1"; +- }; +- }; +- }; +- +- stmpe2401_1 { +- stmpe2401_1_nhk_mode: stmpe2401_1_nhk { +- nhk_cfg1 { +- pins = "GPIO76_B20"; // IRQ line +- ste,input = <0>; +- }; +- nhk_cfg2 { +- pins = "GPIO77_B8"; // reset line +- ste,output = <1>; +- }; +- }; +- }; +- stmpe2401_2 { +- stmpe2401_2_nhk_mode: stmpe2401_2_nhk { +- nhk_cfg1 { +- pins = "GPIO78_A8"; // IRQ line +- ste,input = <0>; +- }; +- nhk_cfg2 { +- pins = "GPIO79_C9"; // reset line +- ste,output = <1>; +- }; +- }; +- }; +- lis3lv02dl { +- lis3lv02dl_nhk_mode: lis3lv02dl_nhk { +- nhk_cfg1 { +- pins = "GPIO82_C10"; // IRQ line +- ste,input = <0>; +- }; +- }; +- }; +- }; +- src@101e0000 { +- /* These chrystal outputs are not used on this board */ +- disable-sxtalo; +- disable-mxtalo; +- }; +- +- /* This is where the interrupt is routed on the NHK-15 debug board */ +- external-bus@34000000 { +- compatible = "simple-bus"; +- reg = <0x34000000 0x1000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x34000000 0x1000000>; +- ethernet@300 { +- compatible = "smsc,lan91c111"; +- reg = <0x300 0x0fd00>; +- reg-io-width = <2>; +- reset-gpios = <&stmpe_gpio44 10 GPIO_ACTIVE_HIGH>; +- interrupt-parent = <&stmpe_gpio44>; +- interrupts = <11 IRQ_TYPE_EDGE_RISING>; +- }; +- }; +- +- i2c0 { +- lis3lv02dl@1d { +- /* Accelerometer */ +- compatible = "st,lis3lv02dl-accel"; +- interrupt-parent = <&gpio2>; +- interrupts = <18 IRQ_TYPE_EDGE_RISING>; // GPIO 82 +- pinctrl-0 = <&lis3lv02dl_nhk_mode>; +- pinctrl-names = "default"; +- reg = <0x1d>; +- }; +- stmpe0: stmpe2401@43 { +- compatible = "st,stmpe2401"; +- reg = <0x43>; +- reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; // GPIO77 +- interrupts = <12 IRQ_TYPE_EDGE_FALLING>; // GPIO76 +- interrupt-parent = <&gpio2>; +- interrupt-controller; +- wakeup-source; +- pinctrl-names = "default"; +- pinctrl-0 = <&stmpe2401_1_nhk_mode>; +- stmpe_gpio43: stmpe_gpio { +- compatible = "st,stmpe-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- /* Some pins in alternate functions */ +- st,norequest-mask = <0xf0f002>; +- }; +- stmpe_keypad { +- compatible = "st,stmpe-keypad"; +- debounce-interval = <64>; +- st,scan-count = <8>; +- st,no-autorepeat; +- keypad,num-rows = <8>; +- keypad,num-columns = <8>; +- linux,keymap = <0x00020072 // Vol down +- 0x00030073 // Vol up +- 0x0100009e // Back +- 0x010100e3 // TV out +- 0x01020098 // Lock +- 0x0103013b // Start +- 0x020000a3 // Next +- 0x020100a4 // Play +- 0x020200a5 // Prev +- 0x02030160 // OK +- 0x03000069 // Left +- 0x0301006a // Right +- 0x03020067 // Up +- 0x0303006c>; // Down +- }; +- stmpe0_pwm: stmpe_pwm { +- compatible = "st,stmpe-pwm"; +- #pwm-cells = <2>; +- }; +- }; +- stmpe1: stmpe2401@44 { +- compatible = "st,stmpe2401"; +- reg = <0x44>; +- reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; // GPIO79 +- interrupts = <14 IRQ_TYPE_EDGE_FALLING>; // GPIO78 +- interrupt-parent = <&gpio2>; +- interrupt-controller; +- wakeup-source; +- pinctrl-names = "default"; +- pinctrl-0 = <&stmpe2401_2_nhk_mode>; +- stmpe_gpio44: stmpe_gpio { +- compatible = "st,stmpe-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- /* +- * This will turn off SATA so that MMC/SD +- * can thrive +- */ +- mmcsd-gpio { +- gpio-hog; +- gpios = <2 0x0>; +- output-low; +- line-name = "SATA EN"; +- }; +- }; +- }; +- }; +- +- amba { +- clcd@10120000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&clcd_24bit_mux>; +- port { +- nomadik_clcd: endpoint { +- remote-endpoint = <&nomadik_clcd_panel>; +- arm,pl11x,tft-r0g0b0-pads = <16 8 0>; +- }; +- }; +- +- }; +- +- /* Activate RX/TX and CTS/RTS on UART 0 */ +- uart0: uart@101fd000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_nhk_mode>; +- status = "okay"; +- }; +- mmcsd: mmc@101f6000 { +- cd-gpios = <&stmpe_gpio44 7 GPIO_ACTIVE_LOW>; +- wp-gpios = <&stmpe_gpio44 18 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- spi { +- compatible = "spi-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* +- * As we're dealing with 3wire SPI, we only define SCK +- * and MOSI (in the spec MOSI is called "SDA"). +- */ +- gpio-sck = <&gpio0 5 GPIO_ACTIVE_HIGH>; +- gpio-mosi = <&gpio0 4 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +- num-chipselects = <1>; +- +- /* +- * WVGA connector 21 +- * WVGA (800x480): 4.3" TPG110 TDO43MTEA2 24-bit RGB +- * with TPO touch screen. +- */ +- panel: display@0 { +- /* +- * The TPO display driver is connected to a +- * 5.7" OSD OSD057VA01CT TFT display. +- */ +- compatible = "tpo,tpg110"; +- reg = <0>; +- spi-3wire; +- /* 320 ns min period ~= 3 MHz */ +- spi-max-frequency = <3000000>; +- /* Width and height from the OSD data sheet */ +- width-mm = <116>; +- height-mm = <87>; +- grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>; +- backlight = <&bl>; +- +- port { +- nomadik_clcd_panel: endpoint { +- remote-endpoint = <&nomadik_clcd>; +- }; +- }; +- }; +- }; +- +- bl: backlight { +- compatible = "pwm-backlight"; +- pwms = <&stmpe0_pwm 0 500000>; +- pwm-names = "backlight"; +- brightness-levels = < +- 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100 +- >; +- default-brightness-level = <100>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-nomadik-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/ste-nomadik-pinctrl.dtsi +deleted file mode 100644 +index bfdb5d9a014f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-nomadik-pinctrl.dtsi ++++ /dev/null +@@ -1,174 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2012 ST-Ericsson +- */ +-#include +- +-/ { +- in_nopull: in_nopull { +- ste,input = ; +- }; +- +- in_pu: input_pull_up { +- ste,input = ; +- }; +- +- in_pd: input_pull_down { +- ste,input = ; +- }; +- +- out_hi: output_high { +- ste,output = ; +- }; +- +- out_lo: output_low { +- ste,output = ; +- }; +- +- gpio_in_nopull: gpio_input_nopull { +- ste,gpio = ; +- ste,input = ; +- }; +- +- gpio_in_pu: gpio_input_pull_up { +- ste,gpio = ; +- ste,input = ; +- }; +- +- gpio_in_pd: gpio_input_pull_down { +- ste,gpio = ; +- ste,input = ; +- }; +- +- gpio_out_lo: gpio_output_low { +- ste,gpio = ; +- ste,output = ; +- }; +- +- gpio_out_hi: gpio_output_high { +- ste,gpio = ; +- ste,output = ; +- }; +- +- slpm_pdis: slpm_pdis { +- ste,sleep = ; +- ste,sleep-wakeup = ; +- ste,sleep-pull-disable = ; +- }; +- +- slpm_wkup_pdis: slpm_wkup_pdis { +- ste,sleep = ; +- ste,sleep-wakeup = ; +- ste,sleep-pull-disable = ; +- }; +- +- slpm_wkup_pdis_en: slpm_wkup_pdis_en { +- ste,sleep = ; +- ste,sleep-wakeup = ; +- ste,sleep-pull-disable = ; +- }; +- +- slpm_in_pu: slpm_in_pu { +- ste,sleep = ; +- ste,sleep-input = ; +- ste,sleep-wakeup = ; +- }; +- +- slpm_in_pdis: slpm_in_pdis { +- ste,sleep = ; +- ste,sleep-input = ; +- ste,sleep-wakeup = ; +- ste,sleep-pull-disable = ; +- }; +- +- slpm_in_wkup_pdis: slpm_in_wkup_pdis { +- ste,sleep = ; +- ste,sleep-input = ; +- ste,sleep-wakeup = ; +- ste,sleep-pull-disable = ; +- }; +- +- slpm_in_wkup_pdis_en: slpm_in_wkup_pdis_en { +- ste,sleep = ; +- ste,sleep-input = ; +- ste,sleep-wakeup = ; +- ste,sleep-pull-disable = ; +- }; +- +- slpm_in_pu_wkup_pdis_en: slpm_in_wkup_pdis_en { +- ste,sleep = ; +- ste,sleep-input = ; +- ste,sleep-wakeup = ; +- ste,sleep-pull-disable = ; +- }; +- +- slpm_out_lo: slpm_out_lo { +- ste,sleep = ; +- ste,sleep-output = ; +- ste,sleep-wakeup = ; +- }; +- +- slpm_out_hi: slpm_out_hi { +- ste,sleep = ; +- ste,sleep-output = ; +- ste,sleep-wakeup = ; +- }; +- +- slpm_out_hi_wkup_pdis: slpm_out_hi_wkup_pdis { +- ste,sleep = ; +- ste,sleep-output = ; +- ste,sleep-wakeup = ; +- ste,sleep-pull-disable = ; +- }; +- +- slpm_out_lo_pdis: slpm_out_lo_pdis { +- ste,sleep = ; +- ste,sleep-output = ; +- ste,sleep-wakeup = ; +- ste,sleep-pull-disable = ; +- }; +- +- slpm_out_lo_wkup_pdis: slpm_out_lo_wkup_pdis { +- ste,sleep = ; +- ste,sleep-output = ; +- ste,sleep-wakeup = ; +- ste,sleep-pull-disable = ; +- }; +- +- slpm_out_wkup_pdis: slpm_out_wkup_pdis { +- ste,sleep = ; +- ste,sleep-output = ; +- ste,sleep-wakeup = ; +- ste,sleep-pull-disable = ; +- }; +- +- in_wkup_pdis: in_wkup_pdis { +- ste,sleep-input = ; +- ste,sleep-wakeup = ; +- ste,sleep-pull-disable = ; +- }; +- +- in_wkup_pdis_en: in_wkup_pdis_en { +- ste,sleep-input = ; +- ste,sleep-wakeup = ; +- ste,sleep-pull-disable = ; +- }; +- +- out_lo_wkup_pdis: out_lo_wkup_pdis { +- ste,sleep-output = ; +- ste,sleep-wakeup = ; +- ste,sleep-pull-disable = ; +- }; +- +- out_hi_wkup_pdis: out_hi_wkup_pdis { +- ste,sleep-output = ; +- ste,sleep-wakeup = ; +- ste,sleep-pull-disable = ; +- }; +- +- out_wkup_pdis: out_wkup_pdis { +- ste,sleep-output = ; +- ste,sleep-wakeup = ; +- ste,sleep-pull-disable = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-nomadik-s8815.dts b/scripts/dtc/include-prefixes/arm/ste-nomadik-s8815.dts +deleted file mode 100644 +index f16314ffbf4b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-nomadik-s8815.dts ++++ /dev/null +@@ -1,172 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree for the ST-Ericsson Nomadik S8815 board +- * Produced by Calao Systems +- */ +- +-/dts-v1/; +-#include +-#include "ste-nomadik-stn8815.dtsi" +- +-/ { +- model = "Calao Systems USB-S8815"; +- compatible = "calaosystems,usb-s8815"; +- +- chosen { +- bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk"; +- }; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- gpio3: gpio@101e7000 { +- /* This hog will bias the MMC/SD card detect line */ +- mmcsd-gpio { +- gpio-hog; +- gpios = <16 0x0>; +- output-low; +- line-name = "card detect bias"; +- }; +- }; +- +- src@101e0000 { +- /* These chrystal drivers are not used on this board */ +- disable-sxtalo; +- disable-mxtalo; +- }; +- +- pinctrl { +- /* Hog CD pins */ +- pinctrl-names = "default"; +- pinctrl-0 = <&cd_default_mode>; +- +- uart0 { +- /* Only use RX/TX pins */ +- uart0_s8815_mode: uart0_mux { +- u0_default_mux { +- function = "u0"; +- groups = "u0txrx_a_1"; +- }; +- }; +- }; +- mmcsd-cd { +- cd_default_mode: cd_default { +- cd_default_cfg1 { +- /* CD input GPIO */ +- pins = "GPIO111_H21"; +- ste,input = <0>; +- }; +- cd_default_cfg2 { +- /* CD GPIO biasing */ +- pins = "GPIO112_J21"; +- ste,output = <0>; +- }; +- }; +- }; +- gpioi2c { +- gpioi2c_default_mode: gpioi2c_default { +- gpioi2c_default_cfg { +- pins = "GPIO73_C21", "GPIO74_C20"; +- ste,input = <0>; +- }; +- }; +- }; +- user-led { +- user_led_default_mode: user_led_default { +- user_led_default_cfg { +- pins = "GPIO2_C5"; +- ste,output = <1>; +- }; +- }; +- }; +- user-button { +- user_button_default_mode: user_button_default { +- user_button_default_cfg { +- pins = "GPIO3_A4"; +- ste,input = <0>; +- }; +- }; +- }; +- }; +- +- /* Ethernet */ +- external-bus@34000000 { +- compatible = "simple-bus"; +- reg = <0x34000000 0x1000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x34000000 0x1000000>; +- ethernet@300 { +- compatible = "smsc,lan91c111"; +- reg = <0x300 0x0fd00>; +- interrupt-parent = <&gpio3>; +- interrupts = <8 IRQ_TYPE_EDGE_RISING>; +- }; +- }; +- +- i2c1 { +- lis3lv02dl@1d { +- /* Accelerometer */ +- compatible = "st,lis3lv02dl-accel"; +- reg = <0x1d>; +- }; +- }; +- +- /* GPIO I2C connected to the USB portions of the STw4811 only */ +- gpio-i2c { +- compatible = "i2c-gpio"; +- gpios = <&gpio2 10 0>, /* sda */ +- <&gpio2 9 0>; /* scl */ +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpioi2c_default_mode>; +- +- stw4811@2d { +- compatible = "st,stw4811-usb"; +- reg = <0x2d>; +- }; +- }; +- +- +- amba { +- /* Activate RXTX on UART 0 */ +- uart0: uart@101fd000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_s8815_mode>; +- status = "okay"; +- }; +- /* Configure card detect for the uSD slot */ +- mmc@101f6000 { +- cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- /* The user LED on the board is set up to be used for heartbeat */ +- leds { +- compatible = "gpio-leds"; +- user-led { +- label = "user_led"; +- gpios = <&gpio0 2 0x1>; +- default-state = "off"; +- linux,default-trigger = "heartbeat"; +- pinctrl-names = "default"; +- pinctrl-0 = <&user_led_default_mode>; +- }; +- }; +- +- /* User key mapped in as "escape" */ +- gpio-keys { +- compatible = "gpio-keys"; +- user-button { +- label = "user_button"; +- gpios = <&gpio0 3 0x1>; +- linux,code = <1>; /* KEY_ESC */ +- wakeup-source; +- pinctrl-names = "default"; +- pinctrl-0 = <&user_button_default_mode>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-nomadik-stn8815.dtsi b/scripts/dtc/include-prefixes/arm/ste-nomadik-stn8815.dtsi +deleted file mode 100644 +index 1815361fe73c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-nomadik-stn8815.dtsi ++++ /dev/null +@@ -1,884 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC +- */ +- +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x04000000>, +- <0x08000000 0x04000000>; +- }; +- +- L2: cache-controller { +- compatible = "arm,l210-cache"; +- reg = <0x10210000 0x1000>; +- interrupt-parent = <&vica>; +- interrupts = <30>; +- cache-unified; +- cache-level = <2>; +- cache-size = <131072>; +- cache-sets = <512>; +- cache-line-size = <32>; +- /* At full speed latency must be >=2 */ +- arm,tag-latency = <8>; +- arm,data-latency = <8 8>; +- arm,dirty-latency = <8>; +- }; +- +- mtu0: mtu@101e2000 { +- /* Nomadik system timer */ +- compatible = "st,nomadik-mtu"; +- reg = <0x101e2000 0x1000>; +- interrupt-parent = <&vica>; +- interrupts = <4>; +- clocks = <&timclk>, <&pclk>; +- clock-names = "timclk", "apb_pclk"; +- }; +- +- mtu1: mtu@101e3000 { +- /* Secondary timer */ +- reg = <0x101e3000 0x1000>; +- interrupt-parent = <&vica>; +- interrupts = <5>; +- clocks = <&timclk>, <&pclk>; +- clock-names = "timclk", "apb_pclk"; +- }; +- +- gpio0: gpio@101e4000 { +- compatible = "st,nomadik-gpio"; +- reg = <0x101e4000 0x80>; +- interrupt-parent = <&vica>; +- interrupts = <6>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-bank = <0>; +- gpio-ranges = <&pinctrl 0 0 32>; +- clocks = <&pclk>; +- }; +- +- gpio1: gpio@101e5000 { +- compatible = "st,nomadik-gpio"; +- reg = <0x101e5000 0x80>; +- interrupt-parent = <&vica>; +- interrupts = <7>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-bank = <1>; +- gpio-ranges = <&pinctrl 0 32 32>; +- clocks = <&pclk>; +- }; +- +- gpio2: gpio@101e6000 { +- compatible = "st,nomadik-gpio"; +- reg = <0x101e6000 0x80>; +- interrupt-parent = <&vica>; +- interrupts = <8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-bank = <2>; +- gpio-ranges = <&pinctrl 0 64 32>; +- clocks = <&pclk>; +- }; +- +- gpio3: gpio@101e7000 { +- compatible = "st,nomadik-gpio"; +- reg = <0x101e7000 0x80>; +- ngpio = <28>; +- interrupt-parent = <&vica>; +- interrupts = <9>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-bank = <3>; +- gpio-ranges = <&pinctrl 0 96 28>; +- clocks = <&pclk>; +- }; +- +- pinctrl: pinctrl { +- compatible = "stericsson,stn8815-pinctrl"; +- nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>; +- /* Pin configurations */ +- uart1 { +- uart1_default_mux: uart1_mux { +- u1_default_mux { +- function = "u1"; +- groups = "u1_a_1"; +- }; +- }; +- }; +- mmcsd { +- mmcsd_default_mux: mmcsd_mux { +- mmcsd_default_mux { +- function = "mmcsd"; +- groups = "mmcsd_a_1", "mmcsd_b_1"; +- }; +- }; +- mmcsd_default_mode: mmcsd_default { +- mmcsd_default_cfg1 { +- /* +- * MCCLK, MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 +- * MCCMD, MCDAT3-0, MCMSFBCLK +- */ +- pins = "GPIO8_B10", "GPIO9_A10", "GPIO10_C11", "GPIO11_B11", +- "GPIO12_A11", "GPIO13_C12", "GPIO14_B12", "GPIO15_A12", +- "GPIO16_C13", "GPIO23_D15", "GPIO24_C15"; +- ste,output = <2>; +- }; +- }; +- }; +- i2c0 { +- i2c0_default_mux: i2c0_mux { +- i2c0_default_mux { +- function = "i2c0"; +- groups = "i2c0_a_1"; +- }; +- }; +- i2c0_default_mode: i2c0_default { +- i2c0_default_cfg { +- pins = "GPIO62_D3", "GPIO63_D2"; +- ste,input = <0>; +- }; +- }; +- }; +- i2c1 { +- i2c1_default_mux: i2c1_mux { +- i2c1_default_mux { +- function = "i2c1"; +- groups = "i2c1_a_1"; +- }; +- }; +- i2c1_default_mode: i2c1_default { +- i2c1_default_cfg { +- pins = "GPIO53_L4", "GPIO54_L3"; +- ste,input = <0>; +- }; +- }; +- }; +- clcd { +- /* +- * This should be activated to use the additional +- * 8 lines for bits 16 thru 23 from the CLCD block. +- */ +- clcd_24bit_mux: clcd_mux { +- clcd_24bit_mux { +- function = "clcd"; +- groups = "clcd_16_23_b_1"; +- }; +- }; +- }; +- }; +- +- /* Power Management Unit */ +- pmu: pmu@101e9000 { +- compatible = "stericsson,nomadik-pmu", "syscon"; +- reg = <0x101e0000 0x1000>; +- }; +- +- src: src@101e0000 { +- compatible = "stericsson,nomadik-src"; +- reg = <0x101e0000 0x1000>; +- +- /* +- * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz +- * that is parent of TIMCLK, PLL1 and PLL2 +- */ +- mxtal: mxtal@19.2M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <19200000>; +- }; +- +- /* +- * The 2.4 MHz TIMCLK reference clock is active at +- * boot time, this is actually the MXTALCLK @19.2 MHz +- * divided by 8. This clock is used by the timers and +- * watchdog. See page 105 ff. +- */ +- timclk: timclk@2.4M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <8>; +- clock-mult = <1>; +- clocks = <&mxtal>; +- }; +- +- /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */ +- pll1: pll1@0 { +- #clock-cells = <0>; +- compatible = "st,nomadik-pll-clock"; +- pll-id = <1>; +- clocks = <&mxtal>; +- }; +- +- /* HCLK divides the PLL1 with 1,2,3 or 4 */ +- hclk: hclk@0 { +- #clock-cells = <0>; +- compatible = "st,nomadik-hclk-clock"; +- clocks = <&pll1>; +- }; +- /* The PCLK domain uses HCLK right off */ +- pclk: pclk@0 { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&hclk>; +- }; +- +- /* PLL2 is usually 864 MHz and divided into a few fixed rates */ +- pll2: pll2@0 { +- #clock-cells = <0>; +- compatible = "st,nomadik-pll-clock"; +- pll-id = <2>; +- clocks = <&mxtal>; +- }; +- clk216: clk216@216M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <4>; +- clock-mult = <1>; +- clocks = <&pll2>; +- }; +- clk108: clk108@108M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <2>; +- clock-mult = <1>; +- clocks = <&clk216>; +- }; +- clk72: clk72@72M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- /* The data sheet does not say how this is derived */ +- clock-div = <12>; +- clock-mult = <1>; +- clocks = <&pll2>; +- }; +- clk48: clk48@48M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- /* The data sheet does not say how this is derived */ +- clock-div = <18>; +- clock-mult = <1>; +- clocks = <&pll2>; +- }; +- clk27: clk27@27M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <4>; +- clock-mult = <1>; +- clocks = <&clk108>; +- }; +- +- /* This apparently exists as well */ +- ulpiclk: ulpiclk@60M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <60000000>; +- }; +- +- /* +- * IP AMBA bus clocks, driving the bus side of the +- * peripheral clocking, clock gates. +- */ +- +- hclkdma0: hclkdma0@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <0>; +- clocks = <&hclk>; +- }; +- hclksmc: hclksmc@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <1>; +- clocks = <&hclk>; +- }; +- hclksdram: hclksdram@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <2>; +- clocks = <&hclk>; +- }; +- hclkdma1: hclkdma1@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <3>; +- clocks = <&hclk>; +- }; +- hclkclcd: hclkclcd@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <4>; +- clocks = <&hclk>; +- }; +- pclkirda: pclkirda@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <5>; +- clocks = <&pclk>; +- }; +- pclkssp: pclkssp@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <6>; +- clocks = <&pclk>; +- }; +- pclkuart0: pclkuart0@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <7>; +- clocks = <&pclk>; +- }; +- pclksdi: pclksdi@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <8>; +- clocks = <&pclk>; +- }; +- pclki2c0: pclki2c0@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <9>; +- clocks = <&pclk>; +- }; +- pclki2c1: pclki2c1@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <10>; +- clocks = <&pclk>; +- }; +- pclkuart1: pclkuart1@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <11>; +- clocks = <&pclk>; +- }; +- pclkmsp0: pclkmsp0@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <12>; +- clocks = <&pclk>; +- }; +- hclkusb: hclkusb@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <13>; +- clocks = <&hclk>; +- }; +- hclkdif: hclkdif@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <14>; +- clocks = <&hclk>; +- }; +- hclksaa: hclksaa@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <15>; +- clocks = <&hclk>; +- }; +- hclksva: hclksva@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <16>; +- clocks = <&hclk>; +- }; +- pclkhsi: pclkhsi@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <17>; +- clocks = <&pclk>; +- }; +- pclkxti: pclkxti@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <18>; +- clocks = <&pclk>; +- }; +- pclkuart2: pclkuart2@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <19>; +- clocks = <&pclk>; +- }; +- pclkmsp1: pclkmsp1@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <20>; +- clocks = <&pclk>; +- }; +- pclkmsp2: pclkmsp2@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <21>; +- clocks = <&pclk>; +- }; +- pclkowm: pclkowm@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <22>; +- clocks = <&pclk>; +- }; +- hclkhpi: hclkhpi@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <23>; +- clocks = <&hclk>; +- }; +- pclkske: pclkske@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <24>; +- clocks = <&pclk>; +- }; +- pclkhsem: pclkhsem@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <25>; +- clocks = <&pclk>; +- }; +- hclk3d: hclk3d@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <26>; +- clocks = <&hclk>; +- }; +- hclkhash: hclkhash@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <27>; +- clocks = <&hclk>; +- }; +- hclkcryp: hclkcryp@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <28>; +- clocks = <&hclk>; +- }; +- pclkmshc: pclkmshc@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <29>; +- clocks = <&pclk>; +- }; +- hclkusbm: hclkusbm@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <30>; +- clocks = <&hclk>; +- }; +- hclkrng: hclkrng@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <31>; +- clocks = <&hclk>; +- }; +- +- /* IP kernel clocks */ +- clcdclk: clcdclk@0 { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <36>; +- clocks = <&clk72 &clk48>; +- }; +- irdaclk: irdaclk@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <37>; +- clocks = <&clk48>; +- }; +- sspiclk: sspiclk@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <38>; +- clocks = <&clk48>; +- }; +- uart0clk: uart0clk@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <39>; +- clocks = <&clk48>; +- }; +- sdiclk: sdiclk@48M { +- /* Also called MCCLK in some documents */ +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <40>; +- clocks = <&clk48>; +- }; +- i2c0clk: i2c0clk@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <41>; +- clocks = <&clk48>; +- }; +- i2c1clk: i2c1clk@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <42>; +- clocks = <&clk48>; +- }; +- uart1clk: uart1clk@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <43>; +- clocks = <&clk48>; +- }; +- mspclk0: mspclk0@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <44>; +- clocks = <&clk48>; +- }; +- usbclk: usbclk@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <45>; +- clocks = <&clk48>; /* 48 MHz not ULPI */ +- }; +- difclk: difclk@72M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <46>; +- clocks = <&clk72>; +- }; +- ipi2cclk: ipi2cclk@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <47>; +- clocks = <&clk48>; /* Guess */ +- }; +- ipbmcclk: ipbmcclk@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <48>; +- clocks = <&clk48>; /* Guess */ +- }; +- hsiclkrx: hsiclkrx@216M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <49>; +- clocks = <&clk216>; +- }; +- hsiclktx: hsiclktx@108M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <50>; +- clocks = <&clk108>; +- }; +- uart2clk: uart2clk@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <51>; +- clocks = <&clk48>; +- }; +- mspclk1: mspclk1@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <52>; +- clocks = <&clk48>; +- }; +- mspclk2: mspclk2@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <53>; +- clocks = <&clk48>; +- }; +- owmclk: owmclk@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <54>; +- clocks = <&clk48>; /* Guess */ +- }; +- skeclk: skeclk@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <56>; +- clocks = <&clk48>; /* Guess */ +- }; +- x3dclk: x3dclk@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <58>; +- clocks = <&clk48>; /* Guess */ +- }; +- pclkmsp3: pclkmsp3@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <59>; +- clocks = <&pclk>; +- }; +- mspclk3: mspclk3@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <60>; +- clocks = <&clk48>; +- }; +- mshcclk: mshcclk@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <61>; +- clocks = <&clk48>; /* Guess */ +- }; +- usbmclk: usbmclk@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <62>; +- /* Stated as "48 MHz not ULPI clock" */ +- clocks = <&clk48>; +- }; +- rngcclk: rngcclk@48M { +- #clock-cells = <0>; +- compatible = "st,nomadik-src-clock"; +- clock-id = <63>; +- clocks = <&clk48>; /* Guess */ +- }; +- }; +- +- /* A NAND flash of 128 MiB */ +- fsmc: flash@40000000 { +- compatible = "stericsson,fsmc-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x10100000 0x1000>, /* FSMC Register*/ +- <0x40000000 0x2000>, /* NAND Base DATA */ +- <0x41000000 0x2000>, /* NAND Base ADDR */ +- <0x40800000 0x2000>; /* NAND Base CMD */ +- reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; +- clocks = <&hclksmc>; +- status = "okay"; +- +- partition@0 { +- label = "X-Loader(NAND)"; +- reg = <0x0 0x40000>; +- }; +- partition@40000 { +- label = "MemInit(NAND)"; +- reg = <0x40000 0x40000>; +- }; +- partition@80000 { +- label = "BootLoader(NAND)"; +- reg = <0x80000 0x200000>; +- }; +- partition@280000 { +- label = "Kernel zImage(NAND)"; +- reg = <0x280000 0x300000>; +- }; +- partition@580000 { +- label = "Root Filesystem(NAND)"; +- reg = <0x580000 0x1600000>; +- }; +- partition@1b80000 { +- label = "User Filesystem(NAND)"; +- reg = <0x1b80000 0x6480000>; +- }; +- }; +- +- /* I2C0 connected to the STw4811 power management chip */ +- i2c0 { +- compatible = "st,nomadik-i2c", "arm,primecell"; +- reg = <0x101f8000 0x1000>; +- interrupt-parent = <&vica>; +- interrupts = <20>; +- clock-frequency = <100000>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&i2c0clk>, <&pclki2c0>; +- clock-names = "mclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>; +- +- stw4811@2d { +- compatible = "st,stw4811"; +- reg = <0x2d>; +- vmmc_regulator: vmmc { +- compatible = "st,stw481x-vmmc"; +- regulator-name = "VMMC"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +- }; +- +- /* I2C1 connected to various sensors */ +- i2c1 { +- compatible = "st,nomadik-i2c", "arm,primecell"; +- reg = <0x101f7000 0x1000>; +- interrupt-parent = <&vica>; +- interrupts = <21>; +- clock-frequency = <100000>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&i2c1clk>, <&pclki2c1>; +- clock-names = "mclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>; +- +- camera@2d { +- compatible = "st,camera"; +- reg = <0x10>; +- }; +- stw5095@1a { +- compatible = "st,stw5095"; +- reg = <0x1a>; +- }; +- }; +- +- amba { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clcd@10120000 { +- compatible = "arm,pl110", "arm,primecell"; +- reg = <0x10120000 0x1000>; +- interrupt-names = "combined"; +- interrupts = <14>; +- interrupt-parent = <&vica>; +- clocks = <&clcdclk>, <&hclkclcd>; +- clock-names = "clcdclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- vica: interrupt-controller@10140000 { +- compatible = "arm,versatile-vic"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x10140000 0x20>; +- }; +- +- vicb: interrupt-controller@10140020 { +- compatible = "arm,versatile-vic"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x10140020 0x20>; +- }; +- +- uart0: uart@101fd000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x101fd000 0x1000>; +- interrupt-parent = <&vica>; +- interrupts = <12>; +- clocks = <&uart0clk>, <&pclkuart0>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disabled"; +- dmas = <&dmac0 14 1>, +- <&dmac0 15 1>; +- dma-names = "rx", "tx"; +- }; +- +- uart1: uart@101fb000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x101fb000 0x1000>; +- interrupt-parent = <&vica>; +- interrupts = <17>; +- clocks = <&uart1clk>, <&pclkuart1>; +- clock-names = "uartclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_default_mux>; +- dmas = <&dmac1 22 1>, +- <&dmac1 23 1>; +- dma-names = "rx", "tx"; +- }; +- +- uart2: uart@101f2000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x101f2000 0x1000>; +- interrupt-parent = <&vica>; +- interrupts = <28>; +- clocks = <&uart2clk>, <&pclkuart2>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disabled"; +- dmas = <&dmac1 30 1>, +- <&dmac1 31 1>; +- dma-names = "rx", "tx"; +- }; +- +- rng: rng@101b0000 { +- compatible = "arm,primecell"; +- reg = <0x101b0000 0x1000>; +- clocks = <&rngcclk>, <&hclkrng>; +- clock-names = "rng", "apb_pclk"; +- }; +- +- rtc: rtc@101e8000 { +- compatible = "arm,pl031", "arm,primecell"; +- reg = <0x101e8000 0x1000>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- interrupt-parent = <&vica>; +- interrupts = <10>; +- }; +- +- mmcsd: mmc@101f6000 { +- compatible = "arm,pl18x", "arm,primecell"; +- reg = <0x101f6000 0x1000>; +- clocks = <&sdiclk>, <&pclksdi>; +- clock-names = "mclk", "apb_pclk"; +- interrupt-parent = <&vica>; +- interrupts = <22>; +- max-frequency = <400000>; +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- full-pwr-cycle; +- /* +- * The STw4811 circuit used with the Nomadik strictly +- * requires that all of these signal direction pins be +- * routed and used for its 4-bit levelshifter. +- */ +- st,sig-dir-dat0; +- st,sig-dir-dat2; +- st,sig-dir-dat31; +- st,sig-dir-cmd; +- st,sig-pin-fbclk; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; +- vmmc-supply = <&vmmc_regulator>; +- }; +- +- dmac0: dma-controller@10130000 { +- compatible = "arm,pl080", "arm,primecell"; +- reg = <0x10130000 0x1000>; +- interrupt-parent = <&vica>; +- interrupts = <15>; +- clocks = <&hclkdma0>; +- clock-names = "apb_pclk"; +- lli-bus-interface-ahb1; +- lli-bus-interface-ahb2; +- mem-bus-interface-ahb2; +- memcpy-burst-size = <256>; +- memcpy-bus-width = <32>; +- #dma-cells = <2>; +- }; +- dmac1: dma-controller@10150000 { +- compatible = "arm,pl080", "arm,primecell"; +- reg = <0x10150000 0x1000>; +- interrupt-parent = <&vica>; +- interrupts = <13>; +- clocks = <&hclkdma1>; +- clock-names = "apb_pclk"; +- lli-bus-interface-ahb1; +- lli-bus-interface-ahb2; +- mem-bus-interface-ahb2; +- memcpy-burst-size = <256>; +- memcpy-bus-width = <32>; +- #dma-cells = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-snowball.dts b/scripts/dtc/include-prefixes/arm/ste-snowball.dts +deleted file mode 100644 +index 934fc788fe1d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-snowball.dts ++++ /dev/null +@@ -1,626 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2011 ST-Ericsson AB +- */ +- +-/dts-v1/; +-#include "ste-db9500.dtsi" +-#include "ste-href-ab8500.dtsi" +-#include "ste-href-family-pinctrl.dtsi" +- +-/ { +- model = "Calao Systems Snowball platform with device tree"; +- compatible = "calaosystems,snowball-a9500", "st-ericsson,u9500"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; +- }; +- +- en_3v3_reg: en_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "en-3v3-fixed-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- /* AB8500 GPIOs start from 1 - offset 25 is GPIO26. */ +- gpio = <&ab8500_gpio 25 0x4>; +- startup-delay-us = <5000>; +- enable-active-high; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- button@1 { +- debounce-interval = <50>; +- wakeup-source; +- linux,code = <2>; +- label = "userpb"; +- gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; +- }; +- button@2 { +- debounce-interval = <50>; +- wakeup-source; +- linux,code = <3>; +- label = "extkb1"; +- gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; +- }; +- button@3 { +- debounce-interval = <50>; +- wakeup-source; +- linux,code = <4>; +- label = "extkb2"; +- gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; +- }; +- button@4 { +- debounce-interval = <50>; +- wakeup-source; +- linux,code = <5>; +- label = "extkb3"; +- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; +- }; +- button@5 { +- debounce-interval = <50>; +- wakeup-source; +- linux,code = <6>; +- label = "extkb4"; +- gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpioled_snowball_mode>; +- used-led { +- label = "user_led"; +- gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- soc { +- /* Name the GPIO muxed rails on the Snowball board */ +- gpio@8012e000 { +- /* GPIOs 0 - 31 */ +- gpio-line-names = "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", +- "AP_GPIO31"; +- }; +- +- gpio@8012e080 { +- /* GPIOs 32 - 63 */ +- gpio-line-names = "USR PB", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +- }; +- +- gpio@8000e000 { +- /* GPIOs 64 - 95 */ +- gpio-line-names = "", "", "", "", "AP_GPIO68", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +- }; +- +- gpio@8000e100 { +- /* GPIOs 128 - 159 */ +- gpio-line-names = "", "", "", "", "", "", "", "", +- "", "", "", "", "IRQ_LAN", "RSTn_LAN", +- "USR_LED", "", "", "", "", "", "", +- "", "", "AP_GPIO151", "AP_GPIO152", +- "", "", "", "", "", "", ""; +- }; +- +- gpio@8000e180 { +- /* GPIOs 160 - 191 */ +- gpio-line-names = "", "AP_GPIO161", "AP_GPIO162", +- "ACCELEROMETER_INT1_RDY", +- "ACCELEROMETER_INT2", "MAG_DRDY", +- "GYRO_DRDY", "RSTn_MLC", "RSTn_SLC", +- "GYRO_INT", "UART_WAKE", "GBF_RESET", +- "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +- }; +- +- gpio@8011e000 { +- /* GPIOs 192 - 223 */ +- gpio-line-names = "HDTV_INTn", "", "", "", "HDTV_RST", +- "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", +- "WLAN_RESETN", "WLAN_IRQ", "MMC_EN", +- "MMC_CD", "", "", "", "", ""; +- }; +- +- gpio@8011e080 { +- /* GPIOs 224 - 255 */ +- gpio-line-names = "", "", "", "", "SD_SEL", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +- }; +- +- msp0: msp@80123000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&msp0txrxtfstck_a_1_default>; +- status = "okay"; +- }; +- +- msp1: msp@80124000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&msp1txrx_a_1_default>; +- status = "okay"; +- }; +- +- msp2: msp@80117000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&msp2_a_1_default>; +- }; +- +- msp3: msp@80125000 { +- status = "okay"; +- }; +- +- external-bus@50000000 { +- status = "okay"; +- +- ethernet@0 { +- compatible = "smsc,lan9115"; +- reg = <0 0x10000>; +- interrupts = <12 IRQ_TYPE_EDGE_RISING>; +- interrupt-parent = <&gpio4>; +- vdd33a-supply = <&en_3v3_reg>; +- vddvario-supply = <&db8500_vape_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <ð_snowball_mode>; +- +- reg-shift = <1>; +- reg-io-width = <2>; +- smsc,force-internal-phy; +- smsc,irq-active-high; +- smsc,irq-push-pull; +- +- clocks = <&prcc_pclk 3 0>; +- }; +- }; +- +- /* ST6G3244ME level translator for 1.8/2.9 V */ +- vmmci: regulator-gpio { +- compatible = "regulator-gpio"; +- +- /* GPIO228 SD_SEL */ +- gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; +- /* GPIO217 MMC_EN */ +- enable-gpio = <&gpio6 25 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2900000>; +- regulator-name = "mmci-reg"; +- regulator-type = "voltage"; +- +- startup-delay-us = <100>; +- +- states = <1800000 0x1 +- 2900000 0x0>; +- }; +- +- // External Micro SD slot +- mmc@80126000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <100000000>; +- bus-width = <4>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- /* All direction control is used */ +- st,sig-dir-cmd; +- st,sig-dir-dat0; +- st,sig-dir-dat2; +- st,sig-dir-dat31; +- st,sig-pin-fbclk; +- full-pwr-cycle; +- vmmc-supply = <&ab8500_ldo_aux3_reg>; +- vqmmc-supply = <&vmmci>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc0_a_1_default &sdi0_default_mode>; +- pinctrl-1 = <&mc0_a_1_sleep>; +- +- /* GPIO218 MMC_CD */ +- cd-gpios = <&gpio6 26 GPIO_ACTIVE_LOW>; +- +- status = "okay"; +- }; +- +- // WLAN SDIO channel +- mmc@80118000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <100000000>; +- bus-width = <4>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc1_a_1_default>; +- pinctrl-1 = <&mc1_a_1_sleep>; +- +- status = "okay"; +- }; +- +- // Unused PoP eMMC - register and put it to sleep by default */ +- mmc@80005000 { +- arm,primecell-periphid = <0x10480180>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mc2_a_1_sleep>; +- +- status = "okay"; +- }; +- +- // On-board eMMC +- mmc@80114000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <100000000>; +- bus-width = <8>; +- cap-mmc-highspeed; +- no-sdio; +- no-sd; +- vmmc-supply = <&ab8500_ldo_aux2_reg>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc4_a_1_default>; +- pinctrl-1 = <&mc4_a_1_sleep>; +- +- status = "okay"; +- }; +- +- uart@80120000 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u0_a_1_default>; +- pinctrl-1 = <&u0_a_1_sleep>; +- status = "okay"; +- }; +- +- /* This UART is unused and thus left disabled */ +- uart@80121000 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u1rxtx_a_1_default>; +- pinctrl-1 = <&u1rxtx_a_1_sleep>; +- }; +- +- uart@80007000 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u2rxtx_c_1_default>; +- pinctrl-1 = <&u2rxtx_c_1_sleep>; +- status = "okay"; +- }; +- +- i2c@80004000 { +- pinctrl-names = "default","sleep"; +- pinctrl-0 = <&i2c0_a_1_default>; +- pinctrl-1 = <&i2c0_a_1_sleep>; +- status = "okay"; +- }; +- +- i2c@80122000 { +- pinctrl-names = "default","sleep"; +- pinctrl-0 = <&i2c1_b_2_default>; +- pinctrl-1 = <&i2c1_b_2_sleep>; +- status = "okay"; +- }; +- +- i2c@80128000 { +- pinctrl-names = "default","sleep"; +- pinctrl-0 = <&i2c2_b_2_default>; +- pinctrl-1 = <&i2c2_b_2_sleep>; +- status = "okay"; +- lsm303dlh@18 { +- /* Accelerometer */ +- compatible = "st,lsm303dlh-accel"; +- st,drdy-int-pin = <1>; +- reg = <0x18>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vddio-supply = <&db8500_vsmps2_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&accel_snowball_mode>; +- interrupt-parent = <&gpio5>; +- interrupts = <3 IRQ_TYPE_EDGE_RISING>, /* INT1 */ +- <4 IRQ_TYPE_EDGE_RISING>; /* INT2 */ +- }; +- lsm303dlh@1e { +- /* Magnetometer */ +- compatible = "st,lsm303dlh-magn"; +- reg = <0x1e>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vddio-supply = <&db8500_vsmps2_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&magneto_snowball_mode>; +- interrupt-parent = <&gpio5>; +- interrupts = <5 IRQ_TYPE_EDGE_RISING>; /* DRDY line */ +- }; +- l3g4200d@68 { +- /* Gyroscope */ +- compatible = "st,l3g4200d-gyro"; +- st,drdy-int-pin = <2>; +- reg = <0x68>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vddio-supply = <&db8500_vsmps2_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gyro_snowball_mode>; +- interrupt-parent = <&gpio5>; +- interrupts = <6 IRQ_TYPE_EDGE_RISING>, /* DRDY line */ +- <9 IRQ_TYPE_EDGE_RISING>; /* INT1 */ +- }; +- lsp001wm@5c { +- /* Barometer/pressure sensor */ +- compatible = "st,lps001wp-press"; +- reg = <0x5c>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vddio-supply = <&db8500_vsmps2_reg>; +- }; +- }; +- +- i2c@80110000 { +- pinctrl-names = "default","sleep"; +- pinctrl-0 = <&i2c3_c_2_default>; +- pinctrl-1 = <&i2c3_c_2_sleep>; +- status = "okay"; +- }; +- +- spi@80002000 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ssp0_snowball_mode>; +- status = "okay"; +- }; +- +- prcmu@80157000 { +- ab8500 { +- ab8500-gpiocontroller { +- /* +- * AB8500 GPIOs are numbered starting from 1, so the first +- * index 0 is what in the datasheet is called "GPIO1", and +- * the second is "GPIO2" and so forth. Confusingly, the +- * Snowball schematic then names the "GPIO2" line "PM_GPIO1". +- * while later naming "GPIO4" as "PM_GPIO4". +- */ +- gpio-line-names = "", /* AB8500 GPIO1 */ +- "PM_GPIO1", /* AB8500 GPIO2 */ +- "WLAN_CLK_REQ", /* AB8500 GPIO3 */ +- "PM_GPIO4", /* AB8500 GPIO4 */ +- "", "", "", "", "", "", "", "", "", "", "", +- "EN_3V6", /* AB8500 GPIO16 */ +- "", "", "", "" ,"", "", "", "", "", +- "EN_3V3", /* AB8500 GPIO26 */ +- "", "", "", "", "", "", "", "", "", "", "", "", "", +- "PM_GPIO40", /* AB8500 GPIO40 */ +- "PM_GPIO41", /* AB8500 GPIO41 */ +- "PM_GPIO42"; /* AB8500 GPIO42 */ +- }; +- +- ab8500_usb { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&usb_a_1_default>; +- pinctrl-1 = <&usb_a_1_sleep>; +- }; +- +- ext_regulators: ab8500-ext-regulators { +- ab8500_ext1_reg: ab8500_ext1 { +- regulator-name = "ab8500-ext-supply1"; +- }; +- +- ab8500_ext2_reg_reg: ab8500_ext2 { +- regulator-name = "ab8500-ext-supply2"; +- }; +- +- ab8500_ext3_reg_reg: ab8500_ext3 { +- regulator-name = "ab8500-ext-supply3"; +- }; +- }; +- +- ab8500-regulators { +- ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { +- regulator-name = "V-DISPLAY"; +- }; +- +- ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { +- regulator-name = "V-eMMC1"; +- }; +- +- ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { +- regulator-name = "V-MMC-SD"; +- }; +- +- ab8500_ldo_intcore_reg: ab8500_ldo_intcore { +- regulator-name = "V-INTCORE"; +- }; +- +- ab8500_ldo_tvout_reg: ab8500_ldo_tvout { +- regulator-name = "V-TVOUT"; +- }; +- +- ab8500_ldo_audio_reg: ab8500_ldo_audio { +- regulator-name = "V-AUD"; +- }; +- +- ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { +- regulator-name = "V-AMIC1"; +- }; +- +- ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { +- regulator-name = "V-AMIC2"; +- }; +- +- ab8500_ldo_dmic_reg: ab8500_ldo_dmic { +- regulator-name = "V-DMIC"; +- }; +- +- ab8500_ldo_ana_reg: ab8500_ldo_ana { +- regulator-name = "V-CSI/DSI"; +- }; +- }; +- }; +- }; +- +- pinctrl { +- /* +- * Set this up using hogs, as time goes by and as seems fit, these +- * can be moved over to being controlled by respective device. +- */ +- pinctrl-names = "default"; +- pinctrl-0 = <&gbf_snowball_mode>, +- <&wlan_snowball_mode>; +- +- ethernet { +- /* +- * Mux in "SM" which is used for the +- * SMSC911x Ethernet adapter +- */ +- eth_snowball_mode: eth_snowball { +- snowball_mux { +- function = "sm"; +- groups = "sm_b_1"; +- }; +- /* LAN IRQ pin */ +- snowball_cfg1 { +- pins = "GPIO140_B11"; +- ste,config = <&in_nopull>; +- }; +- /* LAN reset pin */ +- snowball_cfg2 { +- pins = "GPIO141_C12"; +- ste,config = <&gpio_out_hi>; +- }; +- +- }; +- }; +- sdi0 { +- sdi0_default_mode: sdi0_default { +- snowball_mux { +- function = "mc0"; +- /* Add the DAT31 pin even if it is not really used */ +- groups = "mc0dat31dir_a_1"; +- }; +- snowball_cfg1 { +- pins = "GPIO21_AB3"; /* DAT31DIR */ +- ste,config = <&out_hi>; +- }; +- /* SD card detect GPIO pin, extend default state */ +- snowball_cfg2 { +- pins = "GPIO218_AH11"; +- ste,config = <&gpio_in_pu>; +- }; +- /* VMMCI level-shifter enable */ +- snowball_cfg3 { +- pins = "GPIO217_AH12"; +- ste,config = <&gpio_out_hi>; +- }; +- /* VMMCI level-shifter voltage select */ +- snowball_cfg4 { +- pins = "GPIO228_AJ6"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- ssp0 { +- ssp0_snowball_mode: ssp0_snowball_default { +- snowball_mux { +- function = "ssp0"; +- groups = "ssp0_a_1"; +- }; +- snowball_cfg1 { +- pins = "GPIO144_B13"; /* FRM */ +- ste,config = <&gpio_out_hi>; +- }; +- snowball_cfg2 { +- pins = "GPIO145_C13"; /* RXD */ +- ste,config = <&in_pd>; +- }; +- snowball_cfg3 { +- pins = +- "GPIO146_D13", /* TXD */ +- "GPIO143_D12"; /* CLK */ +- ste,config = <&out_lo>; +- }; +- +- }; +- }; +- gpio_led { +- gpioled_snowball_mode: gpioled_default { +- snowball_cfg1 { +- pins = "GPIO142_C11"; +- ste,config = <&gpio_out_hi>; +- }; +- +- }; +- }; +- accelerometer { +- accel_snowball_mode: accel_snowball { +- /* Accelerometer lines */ +- snowball_cfg1 { +- pins = +- "GPIO163_C20", /* ACCEL_IRQ1 */ +- "GPIO164_B21"; /* ACCEL_IRQ2 */ +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- gyro { +- gyro_snowball_mode: gyro_snowball { +- snowball_cfg1 { +- pins = +- "GPIO166_A22", /* DRDY */ +- "GPIO169_D22"; /* INT */ +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- magnetometer { +- magneto_snowball_mode: magneto_snowball { +- snowball_cfg1 { +- pins = "GPIO165_C21"; /* MAG_DRDY */ +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- gbf { +- gbf_snowball_mode: gbf_snowball { +- /* +- * GBF (GPS, Bluetooth, FM-radio) interface, +- * pull low to reset state +- */ +- snowball_cfg1 { +- pins = "GPIO171_D23"; /* GBF_ENA_RESET */ +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- wlan { +- wlan_snowball_mode: wlan_snowball { +- /* +- * Activate this mode with the WLAN chip. +- * These are plain GPIO pins used by WLAN +- */ +- snowball_cfg1 { +- pins = +- "GPIO161_D21", /* WLAN_PMU_EN */ +- "GPIO215_AH13"; /* WLAN_ENA */ +- ste,config = <&gpio_out_lo>; +- }; +- snowball_cfg2 { +- pins = "GPIO216_AG12"; /* WLAN_IRQ */ +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- }; +- +- mcde@a0350000 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&lcd_default_mode>; +- pinctrl-1 = <&lcd_sleep_mode>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-ux500-samsung-codina.dts b/scripts/dtc/include-prefixes/arm/ste-ux500-samsung-codina.dts +deleted file mode 100644 +index 952606e607ed..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-ux500-samsung-codina.dts ++++ /dev/null +@@ -1,863 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Devicetree for the Samsung Galaxy Ace 2 GT-I8160 also known as Codina. +- * +- * NOTE: this is the most common variant according to the vendor tree, known +- * as "R0.0". There appears to be a "R0.4" variant with backlight on GPIO69, +- * AB8505 and other changes. There is also talk about some variants having a +- * Samsung S6D27A1 display, indicated by passing a different command line from +- * the boot loader. +- * +- * The Samsung tree further talks about GT-I8160P and GT-I8160chn (China). +- * The GT-I8160 plain is knonw as the "europe" variant. +- * The GT-I8160P appears to not use the ST Microelectronics accelerometer. +- * The GT-I8160chn appears to be the same as the europe variant. +- */ +- +-/dts-v1/; +-#include "ste-db8500.dtsi" +-#include "ste-ab8500.dtsi" +-#include "ste-dbx5x0-pinctrl.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "Samsung Galaxy Ace 2 (GT-I8160)"; +- compatible = "samsung,codina", "st-ericsson,u8500"; +- +- cpus { +- cpu@300 { +- /* +- * This has a frequency cap at ~800 MHz in the firmware. +- * (Changing this number here will not overclock it.) +- */ +- operating-points = <798720 0 +- 399360 0 +- 199680 0>; +- }; +- }; +- +- chosen { +- stdout-path = &serial2; +- }; +- +- /* TI TXS0206 level translator for 2.9 V */ +- sd_level_translator: regulator-gpio { +- compatible = "regulator-fixed"; +- +- /* GPIO87 EN */ +- gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- regulator-name = "sd-level-translator"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- regulator-type = "voltage"; +- +- startup-delay-us = <200>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sd_level_translator_default>; +- }; +- +- /* External LDO MIC5366-3.3YMT for eMMC */ +- ldo_3v3_reg: regulator-gpio-ldo-3v3 { +- compatible = "regulator-fixed"; +- /* Supplied in turn by VBAT */ +- regulator-name = "VMEM_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <5000>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_ldo_en_default_mode>; +- }; +- +- /* +- * External Ricoh "TSP" regulator for the touchscreen. +- * One GPIO line controls two voltages of 3.3V and 1.8V +- * this line is known as "TSP_LDO_ON1" in the schematics. +- */ +- ldo_tsp_3v3_reg: regulator-gpio-tsp-ldo-3v3 { +- compatible = "regulator-fixed"; +- /* Supplied in turn by VBAT */ +- regulator-name = "LDO_TSP_A3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- /* GPIO94 controls this regulator */ +- gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; +- /* 70 ms power-on delay */ +- startup-delay-us = <70000>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsp_ldo_en_default_mode>; +- }; +- ldo_tsp_1v8_reg: regulator-gpio-tsp-ldo-1v8 { +- compatible = "regulator-fixed"; +- /* Supplied in turn by VBAT */ +- regulator-name = "VREG_TSP_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- /* GPIO94 controls this regulator */ +- gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; +- /* 70 ms power-on delay */ +- startup-delay-us = <70000>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsp_ldo_en_default_mode>; +- }; +- +- /* +- * External Ricoh RP152L010B-TR LCD LDO regulator for the display. +- * LCD_PWR_EN controls both a 3.0V and 1.8V output. +- */ +- lcd_3v0_reg: regulator-gpio-lcd-3v0 { +- compatible = "regulator-fixed"; +- /* Supplied in turn by VBAT */ +- regulator-name = "VREG_LCD_3.0V"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- /* GPIO219 controls this regulator */ +- gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_pwr_en_default_mode>; +- }; +- lcd_1v8_reg: regulator-gpio-lcd-1v8 { +- compatible = "regulator-fixed"; +- /* Supplied in turn by VBAT */ +- regulator-name = "VREG_LCD_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- /* GPIO219 controls this regulator too */ +- gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_pwr_en_default_mode>; +- }; +- +- /* +- * This regulator is a GPIO line that drives the Broadcom WLAN +- * line WL_REG_ON high and enables the internal regulators +- * inside the chip. Unfortunatley it is erroneously named +- * WLAN_RST_N on the schematic but it is not a reset line. +- * +- * The voltage specified here is only used to determine the OCR mask, +- * the for the SDIO connector, the chip is actually connected +- * directly to VBAT. +- */ +- wl_reg: regulator-gpio-wlan { +- compatible = "regulator-fixed"; +- regulator-name = "WL_REG_ON"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- startup-delay-us = <100000>; +- /* GPIO215 (WLAN_RST_N to WL_REG_ON) */ +- gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_ldo_en_default>; +- }; +- +- vibrator { +- compatible = "gpio-vibrator"; +- /* GPIO195 "MOT_EN" */ +- enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vibrator_default>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_default_mode>; +- +- button-home { +- linux,code = ; +- label = "HOME"; +- /* GPIO91 */ +- gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; +- }; +- button-volup { +- linux,code = ; +- label = "VOL+"; +- /* GPIO67 */ +- gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; +- }; +- button-voldown { +- linux,code = ; +- label = "VOL-"; +- /* GPIO92 */ +- gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_leds_default_mode>; +- touchkey-led { +- label = "touchkeys"; +- /* +- * GPIO194 on R0.0, R0.4 does not use this at all, it +- * will instead turn LDO AUX4 on/off for key led backlighy. +- * (Line is pulled down on R0.4) +- */ +- gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- ktd253: backlight { +- compatible = "kinetic,ktd253"; +- /* +- * GPIO68 is for R0.0, the board file talks about a TMO variant +- * (R0.4) using GPIO69. +- */ +- enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; +- /* Default to 13/32 brightness */ +- default-brightness = <13>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ktd253_backlight_default_mode>; +- }; +- +- /* Richtek RT8515GQW Flash LED Driver IC */ +- flash { +- compatible = "richtek,rt8515"; +- /* GPIO 140 */ +- enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; +- /* GPIO 141 */ +- ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; +- /* +- * RFS is 16 kOhm and RTS is 100 kOhm giving +- * the flash max current 343mA and torch max +- * current 55 mA. +- */ +- richtek,rfs-ohms = <16000>; +- richtek,rts-ohms = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_flash_default_mode>; +- +- led { +- function = LED_FUNCTION_FLASH; +- color = ; +- flash-max-timeout-us = <250000>; +- flash-max-microamp = <343750>; +- led-max-microamp = <55000>; +- }; +- }; +- +- /* Bit-banged I2C on GPIO143 and GPIO144 also called "SUBPMU I2C" */ +- i2c-gpio-0 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_gpio_0_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- magnetometer@c { +- compatible = "alps,hscdtd008a"; +- reg = <0x0c>; +- clock-frequency = <400000>; +- +- avdd-supply = <&ab8500_ldo_aux1_reg>; // 3V +- dvdd-supply = <&ab8500_ldo_aux2_reg>; // 1.8V +- }; +- /* TODO: this should also be used by the SM5103 Camera power management unit */ +- }; +- +- /* Bit-banged I2C on GPIO151 and GPIO152 also called "NFC I2C" */ +- i2c-gpio-1 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_gpio_1_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* TODO: add the NFC chip here */ +- }; +- +- spi-gpio-0 { +- compatible = "spi-gpio"; +- /* Clock on GPIO220, pin SCL */ +- sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; +- /* MOSI on GPIO224, pin SDI "slave data in" */ +- mosi-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; +- /* MISO on GPIO225, pin SDO "slave data out" */ +- miso-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; +- /* Chip select on GPIO201 */ +- cs-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; +- num-chipselects = <1>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_gpio_0_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* +- * Some Codinas (90%) have a WideChips WS2401-based LMS380KF01 +- * display mounted and some 10% has a Samsung S6D27A1 instead. +- * The boot loader needs to modify this compatible to +- * correspond to whatever is passed from the early Samsung boot. +- */ +- panel@0 { +- compatible = "samsung,lms380kf01"; +- spi-max-frequency = <1200000>; +- /* TYPE 3: inverse clock polarity and phase */ +- spi-cpha; +- spi-cpol; +- +- reg = <0>; +- vci-supply = <&lcd_3v0_reg>; +- vccio-supply = <&lcd_1v8_reg>; +- +- /* Reset on GPIO139 */ +- reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; +- /* LCD_VGH/LCD_DETECT, ESD IRQ on GPIO93 */ +- interrupt-parent = <&gpio2>; +- interrupts = <29 IRQ_TYPE_EDGE_RISING>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&panel_default_mode>; +- backlight = <&ktd253>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +- }; +- +- soc { +- /* External Micro SD slot */ +- mmc@80126000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <100000000>; +- bus-width = <4>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- st,sig-pin-fbclk; +- full-pwr-cycle; +- /* MMC is powered by AUX3 1.2V .. 2.91V */ +- vmmc-supply = <&ab8500_ldo_aux3_reg>; +- /* 2.9 V level translator is using AUX3 at 2.9 V as well */ +- vqmmc-supply = <&sd_level_translator>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc0_a_2_default>; +- pinctrl-1 = <&mc0_a_2_sleep>; +- cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217 +- status = "okay"; +- }; +- +- /* WLAN SDIO channel */ +- mmc@80118000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <50000000>; +- bus-width = <4>; +- non-removable; +- cap-sd-highspeed; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc1_a_2_default>; +- pinctrl-1 = <&mc1_a_2_sleep>; +- /* +- * GPIO-controlled voltage enablement: this drives +- * the WL_REG_ON line high when we use this device. +- * Represented as regulator to fill OCR mask. +- */ +- vmmc-supply = <&wl_reg>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- wifi@1 { +- /* Actually BRCM4330 */ +- compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; +- reg = <1>; +- /* GPIO216 WL_HOST_WAKE */ +- interrupt-parent = <&gpio6>; +- interrupts = <24 IRQ_TYPE_EDGE_FALLING>; +- interrupt-names = "host-wake"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_default_mode>; +- }; +- }; +- +- /* eMMC */ +- mmc@80005000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <100000000>; +- bus-width = <8>; +- non-removable; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- no-sdio; +- no-sd; +- vmmc-supply = <&ldo_3v3_reg>; +- pinctrl-names = "default", "sleep"; +- /* +- * GPIO130 will be set to input no pull-up resulting in a resistor +- * pulling the reset high and taking the memory out of reset. +- */ +- pinctrl-0 = <&mc2_a_1_default>; +- pinctrl-1 = <&mc2_a_1_sleep>; +- status = "okay"; +- }; +- +- /* GBF (Bluetooth) UART */ +- uart@80120000 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u0_a_1_default>; +- pinctrl-1 = <&u0_a_1_sleep>; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm4330-bt"; +- /* GPIO222 rail BT_VREG_EN to BT_REG_ON */ +- shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; +- /* BT_WAKE on GPIO199 */ +- device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; +- /* BT_HOST_WAKE on GPIO97 */ +- /* FIXME: convert to interrupt */ +- host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; +- /* BT_RST_N on GPIO209 */ +- reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bluetooth_default_mode>; +- }; +- }; +- +- /* GPS UART */ +- uart@80121000 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- /* CTS/RTS is not used, CTS is repurposed as GPIO */ +- pinctrl-0 = <&u1rxtx_a_1_default>; +- pinctrl-1 = <&u1rxtx_a_1_sleep>; +- /* FIXME: add a device for the GPS here */ +- }; +- +- /* Debugging console UART connected to TSU6111RSVR (FSA880) */ +- uart@80007000 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u2rxtx_c_1_default>; +- pinctrl-1 = <&u2rxtx_c_1_sleep>; +- }; +- +- prcmu@80157000 { +- ab8500 { +- ab8500_usb { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&usb_a_1_default>; +- pinctrl-1 = <&usb_a_1_sleep>; +- }; +- +- ab8500-regulators { +- ab8500_ldo_aux1 { +- /* Used for VDD for sensors */ +- regulator-name = "V-SENSORS-VDD"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- ab8500_ldo_aux2 { +- /* Used for VIO for sensors */ +- regulator-name = "V-SENSORS-VIO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ab8500_ldo_aux3 { +- /* Used for voltage for external MMC/SD card */ +- regulator-name = "V-MMC-SD"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <2910000>; +- }; +- }; +- }; +- }; +- +- /* I2C0 also known as "AGC I2C" */ +- i2c@80004000 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c0_a_1_default>; +- pinctrl-1 = <&i2c0_a_1_sleep>; +- +- /* TODO: write bindings and driver for this proximity sensor */ +- proximity@39 { +- /* Codina has the Mouser TMD2672 */ +- compatible = "mouser,tmd2672"; +- clock-frequency = <400000>; +- reg = <0x39>; +- +- /* IRQ on GPIO146 "PS_INT" */ +- interrupt-parent = <&gpio4>; +- interrupts = <18 IRQ_TYPE_EDGE_FALLING>; +- /* FIXME: needs a VDDIO supply that is connected to a pull-up resistor */ +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tms2672_codina_default>; +- }; +- }; +- +- /* I2C1 on GPIO16 and GPIO17 also called "MUS I2C" */ +- i2c@80122000 { +- status = "okay"; +- pinctrl-names = "default","sleep"; +- /* FIXME: If it doesn't work try what we use on Gavini */ +- pinctrl-0 = <&i2c1_b_2_default>; +- pinctrl-1 = <&i2c1_b_2_sleep>; +- +- /* Texas Instruments TSU6111 micro USB switch */ +- usb-switch@25 { +- compatible = "ti,tsu6111"; +- reg = <0x25>; +- /* Interrupt JACK_INT_N on GPIO95 */ +- interrupt-parent = <&gpio2>; +- interrupts = <31 IRQ_TYPE_EDGE_FALLING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsu6111_codina_default>; +- }; +- }; +- +- /* I2C2 on GPIO10 and GPIO11 also called "SENSORS I2C" */ +- i2c@80128000 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c2_b_2_default>; +- pinctrl-1 = <&i2c2_b_2_sleep>; +- +- lisd3dh@19 { +- /* ST Microelectronics Accelerometer */ +- compatible = "st,lis3dh-accel"; +- st,drdy-int-pin = <1>; +- reg = <0x19>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V +- vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V +- mount-matrix = "0", "-1", "0", +- "1", "0", "0", +- "0", "0", "1"; +- }; +- }; +- +- /* I2C3 */ +- i2c@80110000 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c3_c_2_default>; +- pinctrl-1 = <&i2c3_c_2_sleep>; +- +- /* TODO: write bindings and driver for this touchscreen */ +- +- /* Zinitix BT404 ISP part */ +- isp@50 { +- compatible = "zinitix,bt404-isp"; +- reg = <0x50>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsp_default>; +- }; +- +- /* Zinitix BT404 touchscreen, also has the touchkeys for menu and back */ +- touchscreen@20 { +- compatible = "zinitix,bt404"; +- reg = <0x20>; +- /* GPIO218 (TSP_INT_1V8) */ +- interrupt-parent = <&gpio6>; +- interrupts = <26 IRQ_TYPE_EDGE_FALLING>; +- vcca-supply = <&ldo_tsp_3v3_reg>; +- vdd-supply = <&ldo_tsp_1v8_reg>; +- zinitix,mode = <2>; +- touchscreen-size-x = <480>; +- touchscreen-size-y = <800>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsp_default>; +- }; +- }; +- +- mcde@a0350000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dpi_default_mode>; +- +- port { +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +- }; +-}; +- +-&pinctrl { +- /* +- * This extends the MC0_A_2 default config to include +- * the card detect GPIO217 line. +- */ +- sdi0 { +- mc0_a_2_default { +- default_cfg4 { +- pins = "GPIO217_AH12"; /* card detect */ +- ste,config = <&gpio_in_pd>; +- }; +- }; +- }; +- sdi2 { +- /* +- * This will make the resistor mounted in R0.0 pull up +- * the reset line and take the eMMC out of reset. On +- * R0.4 variants, GPIO130 should be set in GPIO mode and +- * pulled down. (Not connected.) +- */ +- mc2_a_1_default { +- default_cfg2 { +- pins = "GPIO130_C8"; /* FBCLK */ +- ste,config = <&in_nopull>; +- }; +- }; +- }; +- /* GPIO that enables the 2.9V SD card level translator */ +- sd-level-translator { +- sd_level_translator_default: sd_level_translator_default { +- /* level shifter on GPIO87 */ +- codina_cfg1 { +- pins = "GPIO87_B3"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* GPIO that enables the LDO regulator for the eMMC */ +- emmc-ldo { +- emmc_ldo_en_default_mode: emmc_ldo_default { +- /* LDO enable on GPIO223 */ +- codina_cfg1 { +- pins = "GPIO223_AH9"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* GPIOs for panel control */ +- panel { +- panel_default_mode: panel_default { +- codina_cfg1 { +- /* Reset line */ +- pins = "GPIO139_C9"; +- ste,config = <&gpio_out_lo>; +- }; +- codina_cfg2 { +- /* ESD IRQ line "LCD detect" */ +- pins = "GPIO93_B7"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* GPIO that enables the LDO regulator for the touchscreen */ +- tsp-ldo { +- tsp_ldo_en_default_mode: tsp_ldo_default { +- /* LDO enable on GPIO94 */ +- gavini_cfg1 { +- pins = "GPIO94_D7"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* GPIO that enables the LDO regulator for the LCD display */ +- lcd-ldo { +- lcd_pwr_en_default_mode: lcd_pwr_en_default { +- /* LCD_PWR_EN on GPIO219 */ +- codina_cfg1 { +- pins = "GPIO219_AG10"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* GPIO that enables the LDO regulator for the key LED */ +- key-led { +- gpio_leds_default_mode: en_led_ldo_default { +- /* EN_LED_LDO on GPIO194 */ +- codina_cfg1 { +- pins = "GPIO194_AF27"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* GPIO that enables the WLAN internal LDO regulators */ +- wlan-ldo { +- wlan_ldo_en_default: wlan_ldo_default { +- /* GPIO215 named WLAN_RST_N */ +- codina_cfg1 { +- pins = "GPIO215_AH13"; +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- /* Backlight GPIO */ +- backlight { +- ktd253_backlight_default_mode: backlight_default { +- skomer_cfg1 { +- pins = "GPIO68_E1"; /* LCD_BL_CTRL */ +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- /* Flash and torch */ +- flash { +- gpio_flash_default_mode: flash_default { +- codina_cfg1 { +- pins = "GPIO140_B11", "GPIO141_C12"; +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- /* GPIO keys */ +- gpio-keys { +- gpio_keys_default_mode: gpio_keys_default { +- skomer_cfg1 { +- pins = "GPIO67_G2", /* VOL UP */ +- "GPIO91_B6", /* HOME */ +- "GPIO92_D6"; /* VOL DOWN */ +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- /* Interrupt line for the Zinitix BT404 touchscreen */ +- tsp { +- tsp_default: tsp_default { +- codina_cfg1 { +- pins = "GPIO218_AH11"; /* TSP_INT_1V8 */ +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* Interrupt line for light/proximity sensor TMS2672 */ +- tms2672 { +- tms2672_codina_default: tms2672_codina { +- codina_cfg1 { +- pins = "GPIO146_D13"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* GPIO-based I2C bus for subpmu */ +- i2c-gpio-0 { +- i2c_gpio_0_default: i2c_gpio_0 { +- codina_cfg1 { +- pins = "GPIO143_D12", "GPIO144_B13"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* GPIO-based I2C bus for the NFC */ +- i2c-gpio-1 { +- i2c_gpio_1_default: i2c_gpio_1 { +- codina_cfg1 { +- pins = "GPIO151_D17", "GPIO152_D16"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* GPIO-based SPI bus for the display */ +- spi-gpio-0 { +- spi_gpio_0_default: spi_gpio_0_d { +- codina_cfg1 { +- pins = "GPIO220_AH10", "GPIO201_AF24", "GPIO224_AG9"; +- ste,config = <&gpio_out_hi>; +- }; +- codina_cfg2 { +- pins = "GPIO225_AG8"; +- /* Needs pull down, no pull down resistor on board */ +- ste,config = <&gpio_in_pd>; +- }; +- }; +- spi_gpio_0_sleep: spi_gpio_0_s { +- codina_cfg1 { +- pins = "GPIO220_AH10", "GPIO201_AF24", +- "GPIO224_AG9", "GPIO225_AG8"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- wlan { +- wlan_default_mode: wlan_default { +- /* GPIO216 for WL_HOST_WAKE */ +- codina_cfg2 { +- pins = "GPIO216_AG12"; +- ste,config = <&gpio_in_pd>; +- }; +- }; +- }; +- bluetooth { +- bluetooth_default_mode: bluetooth_default { +- /* GPIO199 BT_WAKE and GPIO222 BT_VREG_ON */ +- codina_cfg1 { +- pins = "GPIO199_AH23", "GPIO222_AJ9"; +- ste,config = <&gpio_out_lo>; +- }; +- /* GPIO97 BT_HOST_WAKE */ +- codina_cfg2 { +- pins = "GPIO97_D9"; +- ste,config = <&gpio_in_nopull>; +- }; +- /* GPIO209 BT_RST_N */ +- codina_cfg3 { +- pins = "GPIO209_AG15"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* Interrupt line for TI TSU6111 Micro USB switch */ +- tsu6111 { +- tsu6111_codina_default: tsu6111_codina { +- codina_cfg1 { +- /* GPIO95 used for IRQ */ +- pins = "GPIO95_E8"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- vibrator { +- vibrator_default: vibrator_default { +- codina_cfg1 { +- pins = "GPIO195_AG28"; /* MOT_EN */ +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- mcde { +- dpi_default_mode: dpi_default { +- default_mux1 { +- /* Mux in all the data lines */ +- function = "lcd"; +- groups = +- /* Data lines D0-D7 GPIO70..GPIO77 */ +- "lcd_d0_d7_a_1", +- /* Data lines D8-D11 GPIO78..GPIO81 */ +- "lcd_d8_d11_a_1", +- /* Data lines D12-D15 GPIO82..GPIO85 */ +- "lcd_d12_d15_a_1", +- /* Data lines D16-D23 GPIO161..GPIO168 */ +- "lcd_d16_d23_b_1"; +- }; +- default_mux2 { +- function = "lcda"; +- /* Clock line on GPIO150, DE, VSO, HSO on GPIO169..GPIO171 */ +- groups = "lcdaclk_b_1", "lcda_b_1"; +- }; +- /* Input, no pull-up is the default state for pins used for an alt function */ +- default_cfg1 { +- pins = "GPIO150_C14", "GPIO169_D22", "GPIO170_C23", "GPIO171_D23"; +- ste,config = <&in_nopull>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-ux500-samsung-gavini.dts b/scripts/dtc/include-prefixes/arm/ste-ux500-samsung-gavini.dts +deleted file mode 100644 +index fabc390ccb0c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-ux500-samsung-gavini.dts ++++ /dev/null +@@ -1,854 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Devicetree for the Samsung Galaxy Beam GT-I8530 also known as Gavini. +- */ +- +-/dts-v1/; +-#include "ste-db8500.dtsi" +-#include "ste-ab8500.dtsi" +-#include "ste-dbx5x0-pinctrl.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "Samsung Galaxy Beam (GT-I8530)"; +- compatible = "samsung,gavini", "st-ericsson,u8500"; +- +- chosen { +- stdout-path = &serial2; +- }; +- +- /* TI TXS0206 level translator for 2.9 V */ +- sd_level_translator: regulator-gpio { +- compatible = "regulator-fixed"; +- +- /* GPIO193 EN */ +- gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- regulator-name = "sd-level-translator"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- regulator-type = "voltage"; +- +- startup-delay-us = <200>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sd_level_translator_default>; +- }; +- +- /* External LDO for eMMC LDO VMEM_3V3 controlled by GPIO6 */ +- ldo_3v3_reg: regulator-gpio-ldo-3v3 { +- compatible = "regulator-fixed"; +- /* Supplied in turn by VBAT */ +- regulator-name = "VMEM_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <5000>; // FIXME +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_ldo_en_default_mode>; +- }; +- +- /* +- * External Ricoh "TSP" regulator for the touchscreen. +- * One GPIO line controls two voltages of 3.3V and 1.8V +- * this line is known as "TSP_LDO_ON1" in the schematics. +- */ +- ldo_tsp_3v3_reg: regulator-gpio-tsp-ldo-3v3 { +- compatible = "regulator-fixed"; +- /* Supplied in turn by VBAT */ +- regulator-name = "LDO_TSP_A3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- /* GPIO94 controls this regulator */ +- gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; +- /* 70 ms power-on delay */ +- startup-delay-us = <70000>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsp_ldo_en_default_mode>; +- }; +- ldo_tsp_1v8_reg: regulator-gpio-tsp-ldo-1v8 { +- compatible = "regulator-fixed"; +- /* Supplied in turn by VBAT */ +- regulator-name = "VREG_TSP_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- /* GPIO94 controls this regulator */ +- gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; +- /* 70 ms power-on delay */ +- startup-delay-us = <70000>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsp_ldo_en_default_mode>; +- }; +- +- /* +- * External Ricoh RP152L010B-TR LCD LDO regulator for the display. +- * LCD_PWR_EN controls both a 3.0V and 1.8V output. +- */ +- lcd_3v0_reg: regulator-gpio-lcd-3v0 { +- compatible = "regulator-fixed"; +- /* Supplied in turn by VBAT */ +- regulator-name = "VREG_LCD_3V0"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- /* GPIO219 controls this regulator */ +- gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_pwr_en_default_mode>; +- }; +- lcd_1v8_reg: regulator-gpio-lcd-1v8 { +- compatible = "regulator-fixed"; +- /* Supplied in turn by VBAT */ +- regulator-name = "VREG_LCD_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- /* GPIO219 controls this regulator too */ +- gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_pwr_en_default_mode>; +- }; +- +- /* +- * This regulator is a GPIO line that drives the Broadcom WLAN +- * line WL_REG_ON high and enables the internal regulators +- * inside the chip. Unfortunatley it is erroneously named +- * WLAN_RST_N on the schematic but it is not a reset line. +- * +- * The voltage specified here is only used to determine the OCR mask, +- * the for the SDIO connector, the chip is actually connected +- * directly to VBAT. +- */ +- wl_reg: regulator-gpio-wlan { +- compatible = "regulator-fixed"; +- regulator-name = "WL_REG_ON"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- startup-delay-us = <100000>; +- /* GPIO215 (WLAN_RST_N to WL_REG_ON) */ +- gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_ldo_en_default>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_default_mode>; +- +- button-projector { +- linux,code = ; +- label = "Projector"; +- /* GPIO32 "Projector On HotKey" */ +- gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; +- }; +- button-home { +- linux,code = ; +- label = "HOME"; +- /* GPIO91 */ +- gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; +- }; +- button-volup { +- linux,code = ; +- label = "VOL+"; +- /* GPIO67 */ +- gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; +- }; +- button-voldown { +- linux,code = ; +- label = "VOL-"; +- /* GPIO92 */ +- gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- /* Richtek RT8515GQW Flash LED Driver IC */ +- flash { +- compatible = "richtek,rt8515"; +- /* GPIO 140 */ +- enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; +- /* GPIO 141 */ +- ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; +- /* +- * RFS is 16 kOhm and RTS is 100 kOhm giving +- * the flash max current 343mA and torch max +- * current 55 mA. +- */ +- richtek,rfs-ohms = <16000>; +- richtek,rts-ohms = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_flash_default_mode>; +- +- led { +- function = LED_FUNCTION_FLASH; +- color = ; +- flash-max-timeout-us = <250000>; +- flash-max-microamp = <343750>; +- led-max-microamp = <55000>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_leds_default_mode>; +- used-led { +- label = "touchkeys"; +- /* GPIO68 */ +- gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- ktd259: backlight { +- compatible = "kinetic,ktd259"; +- /* GPIO20 */ +- enable-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; +- /* Default to 13/32 brightness */ +- default-brightness = <13>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ktd259_backlight_default_mode>; +- }; +- +- /* Bit-banged I2C on GPIO143 and GPIO144 also called "SUBPMU I2C" */ +- i2c-gpio-0 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_gpio_0_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* TODO: Memsic MMC328 magnetometer */ +- magnetometer@30 { +- compatible = "memsic,mmc328"; +- reg = <0x30>; +- /* TODO: if you have the schematic, check if both voltages come from AUX2 */ +- /* VDA 1.8 V */ +- vda-supply = <&ab8500_ldo_aux2_reg>; +- /* VDD 1.8V */ +- vdd-supply = <&ab8500_ldo_aux2_reg>; +- /* GPIO204 */ +- reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc328_default>; +- }; +- /* TODO: this should also be used by the NCP6914 Camera power management unit */ +- }; +- +- /* +- * TODO: See if we can use the PL023 for this instead. +- */ +- spi-gpio-0 { +- compatible = "spi-gpio"; +- /* Clock on GPIO220, pin SCL */ +- sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; +- /* MOSI on GPIO224, pin SDI "slave data in" */ +- mosi-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; +- /* MISO on GPIO225, pin SDO "slave data out" */ +- miso-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; +- /* Chip select on GPIO223 */ +- cs-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>; +- num-chipselects = <1>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_gpio_0_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- panel@0 { +- compatible = "samsung,lms397kf04"; +- /* 300 ns at read cycle -> 3 MHz max speed */ +- //spi-max-frequency = <3000000>; +- spi-max-frequency = <1200000>; +- /* TYPE 3: inverse clock polarity and phase */ +- spi-cpha; +- spi-cpol; +- +- reg = <0>; +- vci-supply = <&lcd_3v0_reg>; +- vccio-supply = <&lcd_1v8_reg>; +- /* Reset on GPIO139 */ +- reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&panel_default_mode>; +- backlight = <&ktd259>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +- }; +- +- /* Bit-banged I2C on GPIO201 and GPIO202 also called "MOT_I2C" */ +- i2c-gpio-2 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio6 10 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio6 9 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_gpio_2_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- /* TODO: add the Immersion ISA1200 I2C device here */ +- }; +- +- /* Bit-banged I2C on GPIO196 and GPIO197 also called "MPR_I2C" */ +- i2c-gpio-3 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio6 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio6 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_gpio_3_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- /* TODO: add the DPP2601 projector I2C device 0x1b here */ +- }; +- +- soc { +- /* External Micro SD slot */ +- mmc@80126000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <50000000>; +- bus-width = <4>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- st,sig-pin-fbclk; +- full-pwr-cycle; +- /* MMC is powered by AUX3 1.2V .. 2.91V */ +- vmmc-supply = <&ab8500_ldo_aux3_reg>; +- /* 2.9 V level translator */ +- vqmmc-supply = <&sd_level_translator>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc0_a_2_default>; +- pinctrl-1 = <&mc0_a_2_sleep>; +- /* "flash detect" actually card detect */ +- cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; +- status = "okay"; +- }; +- +- /* WLAN SDIO channel */ +- mmc@80118000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <50000000>; +- bus-width = <4>; +- non-removable; +- cap-sd-highspeed; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc1_a_2_default>; +- pinctrl-1 = <&mc1_a_2_sleep>; +- /* +- * GPIO-controlled voltage enablement: this drives +- * the WL_REG_ON line high when we use this device. +- * Represented as regulator to fill OCR mask. +- */ +- vmmc-supply = <&wl_reg>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- wifi@1 { +- compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; +- reg = <1>; +- /* GPIO216 WL_HOST_WAKE */ +- interrupt-parent = <&gpio6>; +- interrupts = <24 IRQ_TYPE_EDGE_FALLING>; +- interrupt-names = "host-wake"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_default_mode>; +- }; +- }; +- +- /* eMMC */ +- mmc@80005000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <50000000>; +- bus-width = <8>; +- non-removable; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- no-sdio; +- no-sd; +- vmmc-supply = <&ldo_3v3_reg>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc2_a_1_default>; +- pinctrl-1 = <&mc2_a_1_sleep>; +- status = "okay"; +- }; +- +- /* GBF (Bluetooth) UART */ +- uart@80120000 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u0_a_1_default>; +- pinctrl-1 = <&u0_a_1_sleep>; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm4330-bt"; +- /* GPIO222 rail BT_VREG_EN to BT_REG_ON */ +- shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; +- /* BT_WAKE on GPIO199 */ +- device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; +- /* BT_HOST_WAKE on GPIO97 */ +- host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; +- /* BT_RST_N on GPIO209 */ +- reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bluetooth_default_mode>; +- }; +- }; +- +- /* GPS UART */ +- uart@80121000 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- /* CTS/RTS is not used, CTS is repurposed as GPIO */ +- pinctrl-0 = <&u1rxtx_a_1_default>; +- pinctrl-1 = <&u1rxtx_a_1_sleep>; +- /* FIXME: add a device for the GPS here */ +- }; +- +- /* Debugging console UART connected to TSU6111RSVR (FSA880) */ +- uart@80007000 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u2rxtx_c_1_default>; +- pinctrl-1 = <&u2rxtx_c_1_sleep>; +- }; +- +- prcmu@80157000 { +- ab8500 { +- ab8500_usb { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&usb_a_1_default>; +- pinctrl-1 = <&usb_a_1_sleep>; +- }; +- +- ab8500-regulators { +- ab8500_ldo_aux1 { +- /* Used for VDD for sensors */ +- regulator-name = "V-SENSORS-VDD"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- ab8500_ldo_aux2 { +- /* Used for VIO for sensors */ +- regulator-name = "V-SENSORS-VIO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ab8500_ldo_aux3 { +- /* Used for voltage for external MMC/SD card */ +- regulator-name = "V-MMC-SD"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <2910000>; +- }; +- }; +- }; +- }; +- +- /* I2C0 */ +- i2c@80004000 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c0_a_1_default>; +- pinctrl-1 = <&i2c0_a_1_sleep>; +- +- /* FIXME: fix the proximity sensor bindings and driver */ +- proximity@39 { +- /* Gavini has the GP2A030S00F proximity sensor */ +- compatible = "sharp,gp2a030s00f"; +- clock-frequency = <400000>; +- reg = <0x39>; +- /* FIXME: GPIO146 provides power on, IR LED? */ +- }; +- +- gyroscope@68 { +- compatible = "invensense,mpu3050"; +- reg = <0x68>; +- /* GPIO226 interrupt */ +- interrupt-parent = <&gpio7>; +- interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +- mount-matrix = "0", "1", "0", +- "1", "0", "0", +- "0", "0", "1"; +- vlogic-supply = <&ab8500_ldo_aux2_reg>; // 1.8V +- vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V +- pinctrl-names = "default"; +- pinctrl-0 = <&mpu3050_default>; +- +- /* +- * The MPU-3050 acts as a hub for the +- * accelerometer. +- */ +- i2c-gate { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Bosch BMA222E accelerometer */ +- accelerometer@18 { +- compatible = "bosch,bma222e"; +- reg = <0x18>; +- mount-matrix = "0", "1", "0", +- "-1", "0", "0", +- "0", "0", "1"; +- vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V +- vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V +- }; +- }; +- }; +- }; +- +- /* I2C2 "AGC I2C" */ +- i2c@80128000 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c2_b_1_default>; +- pinctrl-1 = <&i2c2_b_1_sleep>; +- +- /* Texas Instruments TSU6111 micro USB switch */ +- usb-switch@25 { +- compatible = "ti,tsu6111"; +- reg = <0x25>; +- /* Interrupt JACK_INT_N on GPIO95 */ +- interrupt-parent = <&gpio2>; +- interrupts = <31 IRQ_TYPE_EDGE_FALLING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsu6111_default>; +- }; +- }; +- +- /* I2C3 */ +- i2c@80110000 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c3_c_2_default>; +- pinctrl-1 = <&i2c3_c_2_sleep>; +- +- /* Melfas MMS136 touchscreen */ +- touchscreen@48 { +- compatible = "melfas,mms136"; +- reg = <0x48>; +- /* GPIO218 (TSP_INT_1V8) */ +- interrupt-parent = <&gpio6>; +- interrupts = <26 IRQ_TYPE_EDGE_FALLING>; +- /* AVDD is "analog supply", 2.57-3.47 V */ +- avdd-supply = <&ldo_tsp_3v3_reg>; +- /* VDD is "digital supply" 1.71-3.47V */ +- vdd-supply = <&ldo_tsp_1v8_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsp_default>; +- touchscreen-size-x = <480>; +- touchscreen-size-y = <800>; +- }; +- }; +- +- mcde@a0350000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dpi_default_mode>; +- +- port { +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +- }; +-}; +- +-&pinctrl { +- /* +- * This extends the MC0_A_2 default config to include +- * the card detect GPIO217 line. +- */ +- sdi0 { +- mc0_a_2_default { +- default_cfg4 { +- pins = "GPIO217_AH12"; /* card detect */ +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- mcde { +- dpi_default_mode: dpi_default { +- default_mux1 { +- /* Mux in all the data lines */ +- function = "lcd"; +- groups = +- /* Data lines D0-D7 GPIO70..GPIO77 */ +- "lcd_d0_d7_a_1", +- /* Data lines D8-D11 GPIO78..GPIO81 */ +- "lcd_d8_d11_a_1", +- /* Data lines D12-D15 GPIO82..GPIO85 */ +- "lcd_d12_d15_a_1", +- /* Data lines D16-D23 GPIO161..GPIO168 */ +- "lcd_d16_d23_b_1"; +- }; +- default_mux2 { +- function = "lcda"; +- /* Clock line on GPIO150, DE, VSO, HSO on GPIO169..GPIO171 */ +- groups = "lcdaclk_b_1", "lcda_b_1"; +- }; +- /* Input, no pull-up is the default state for pins used for an alt function */ +- default_cfg1 { +- pins = "GPIO150_C14", "GPIO169_D22", "GPIO170_C23", "GPIO171_D23"; +- ste,config = <&in_nopull>; +- }; +- }; +- }; +- /* GPIO for panel reset control */ +- panel { +- panel_default_mode: panel_default { +- gavini_cfg1 { +- /* Reset line */ +- pins = "GPIO139_C9"; +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- /* GPIO that enables the LDO regulator for the eMMC */ +- emmc-ldo { +- emmc_ldo_en_default_mode: emmc_ldo_default { +- /* LDO enable on GPIO6 */ +- gavini_cfg1 { +- pins = "GPIO6_AF6"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* GPIO that enables the LDO regulator for the touchscreen */ +- tsp-ldo { +- tsp_ldo_en_default_mode: tsp_ldo_default { +- /* LDO enable on GPIO94 */ +- gavini_cfg1 { +- pins = "GPIO94_D7"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* Flash and torch */ +- flash { +- gpio_flash_default_mode: flash_default { +- janice_cfg1 { +- pins = "GPIO140_B11", "GPIO141_C12"; +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- /* GPIO that enables the LDO regulator for the key LED */ +- gpio-leds { +- gpio_leds_default_mode: gpio_leds_default { +- /* EN_LED_LDO on GPIO68 */ +- gavini_cfg1 { +- pins = "GPIO68_E1"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- backlight { +- ktd259_backlight_default_mode: backlight_default { +- skomer_cfg1 { +- pins = "GPIO20_AB4"; /* LCD_BL_EN */ +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- /* GPIO that enables the LDO regulator for the touchkeys */ +- touchkey-ldo { +- tsp_ldo_on2_default_mode: tsp_ldo_on2_default { +- /* TSP_LDO_ON2 on GPIO89 */ +- gavini_cfg1 { +- pins = "GPIO89_E6"; +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- touchkey { +- touchkey_default_mode: touchkey_default { +- gavini_cfg1 { +- /* Interrupt */ +- pins = "GPIO198_AG25"; +- ste,config = <&gpio_in_nopull>; +- }; +- gavini_cfg2 { +- /* Reset, actually completely unused (not routed) */ +- pins = "GPIO205_AG23"; +- ste,config = <&gpio_in_pd>; +- }; +- }; +- }; +- /* GPIO that enables the LDO regulator for the LCD display */ +- lcd-ldo { +- lcd_pwr_en_default_mode: lcd_pwr_en_default { +- /* LCD_PWR_EN on GPIO219 */ +- gavini_cfg1 { +- pins = "GPIO219_AG10"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* GPIO that enables the WLAN internal LDO regulators */ +- wlan-ldo { +- wlan_ldo_en_default: wlan_ldo_default { +- /* GPIO215 named WLAN_RST_N */ +- gavini_cfg1 { +- pins = "GPIO215_AH13"; +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- /* GPIO that enables the 2.9V SD card level translator */ +- sd-level-translator { +- sd_level_translator_default: sd_level_translator_default { +- /* level shifter on GPIO193 */ +- skomer_cfg1 { +- pins = "GPIO193_AH27"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* GPIO keys */ +- gpio-keys { +- gpio_keys_default_mode: gpio_keys_default { +- skomer_cfg1 { +- pins = "GPIO32_V2", /* Projector On HotKey */ +- "GPIO67_G2", /* VOL UP */ +- "GPIO91_B6", /* HOME */ +- "GPIO92_D6"; /* VOL DOWN */ +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- /* Interrupt line for the Atmel MXT228 touchscreen */ +- tsp { +- tsp_default: tsp_default { +- gavini_cfg1 { +- pins = "GPIO218_AH11"; /* TSP_INT_1V8 */ +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* Reset line for the Memsic MMC328 magnetometer */ +- mmc328 { +- mmc328_default: mmc328_gavini { +- gavini_cfg1 { +- pins = "GPIO204_AF23"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* Interrupt line for Invensense MPU3050 gyroscope */ +- mpu3050 { +- mpu3050_default: mpu3050 { +- gavini_cfg1 { +- /* GPIO226 used for IRQ */ +- pins = "GPIO226_AF8"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* GPIO-based I2C bus for magnetometer and NCP6914 */ +- i2c-gpio-0 { +- i2c_gpio_0_default: i2c_gpio_0 { +- gavini_cfg1 { +- pins = "GPIO143_D12", "GPIO144_B13"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* GPIO-based I2C bus for the Immersion ISA1200 */ +- i2c-gpio-2 { +- i2c_gpio_2_default: i2c_gpio_2 { +- gavini_cfg1 { +- pins = "GPIO201_AF24", "GPIO202_AF25"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* GPIO-based I2C bus for the TI DPP2601 */ +- i2c-gpio-3 { +- i2c_gpio_3_default: i2c_gpio_3 { +- gavini_cfg1 { +- pins = "GPIO196_AG26", "GPIO197_AH24"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* GPIO-based SPI bus for the display */ +- spi-gpio-0 { +- spi_gpio_0_default: spi_gpio_0_d { +- gavini_cfg1 { +- pins = "GPIO220_AH10", "GPIO223_AH9", "GPIO224_AG9"; +- ste,config = <&gpio_out_hi>; +- }; +- gavini_cfg2 { +- pins = "GPIO225_AG8"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- spi_gpio_0_sleep: spi_gpio_0_s { +- gavini_cfg1 { +- pins = "GPIO220_AH10", "GPIO223_AH9", +- "GPIO224_AG9", "GPIO225_AG8"; +- ste,config = <&gpio_out_hi>; +- }; +- gavini_cfg2 { +- pins = "GPIO225_AG8"; +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- wlan { +- wlan_default_mode: wlan_default { +- /* GPIO216 for WL_HOST_WAKE */ +- gavini_cfg2 { +- pins = "GPIO216_AG12"; +- ste,config = <&gpio_in_pd>; +- }; +- }; +- }; +- bluetooth { +- bluetooth_default_mode: bluetooth_default { +- /* GPIO199 BT_WAKE and GPIO222 BT_VREG_ON */ +- gavini_cfg1 { +- pins = "GPIO199_AH23", "GPIO222_AJ9"; +- ste,config = <&gpio_out_lo>; +- }; +- /* GPIO97 BT_HOST_WAKE */ +- gavini_cfg2 { +- pins = "GPIO97_D9"; +- ste,config = <&gpio_in_nopull>; +- }; +- /* GPIO209 BT_RST_N */ +- gavini_cfg3 { +- pins = "GPIO209_AG15"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* Interrupt line for TI TSU6111 Micro USB switch */ +- tsu6111 { +- tsu6111_default: tsu6111 { +- gavini_cfg1 { +- /* GPIO95 used for IRQ */ +- pins = "GPIO95_E8"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-ux500-samsung-golden.dts b/scripts/dtc/include-prefixes/arm/ste-ux500-samsung-golden.dts +deleted file mode 100644 +index ee6379ab688c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-ux500-samsung-golden.dts ++++ /dev/null +@@ -1,699 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/dts-v1/; +- +-#include "ste-db8500.dtsi" +-#include "ste-ab8505.dtsi" +-#include "ste-dbx5x0-pinctrl.dtsi" +-#include +-#include +-#include +-#include +- +-/* +- * Note: This device tree cannot be booted directly with the Samsung bootloader. +- * You need an intermediate, device-tree compatible bootloader +- * that locks the L2 cache. Otherwise the kernel will crash after decompression. +- * +- * There is a port of (mainline) U-Boot, see +- * https://wiki.postmarketos.org/wiki/ST-Ericsson_NovaThor_U8500#U-Boot +- */ +-/ { +- model = "Samsung Galaxy S III mini (GT-I8190)"; +- compatible = "samsung,golden", "st-ericsson,u8500"; +- +- chosen { +- stdout-path = &serial2; +- }; +- +- i2c-gpio-0 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio2 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio2 13 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_gpio_0_default>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- touchkey@20 { +- compatible = "coreriver,tc360-touchkey"; +- reg = <0x20>; +- vdd-supply = <&ab8500_ldo_aux4_reg>; +- vcc-supply = <&ab8500_ldo_aux6_reg>; +- +- interrupt-parent = <&gpio2>; +- interrupts = <15 IRQ_TYPE_EDGE_FALLING>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&touchkey_default>; +- linux,keycodes = ; +- }; +- }; +- +- i2c-gpio-1 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_gpio_1_default>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- magnetometer@c { +- compatible = "alps,hscdtd008a"; +- reg = <0x0c>; +- +- avdd-supply = <&ab8500_ldo_aux1_reg>; +- dvdd-supply = <&ab8500_ldo_aux8_reg>; +- }; +- }; +- +- soc { +- /* External Micro SD card slot */ +- mmc@80126000 { +- status = "okay"; +- +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <100000000>; +- bus-width = <4>; +- +- non-removable; +- /* +- * Unfortunately, there is no way to enable the UHS +- * modes due to a limitation of the SD level translator: +- * It will either translate to 2.9V or disconnect the +- * DATA lines, so switching to 1.8V signal voltage fails. +- */ +- cap-sd-highspeed; +- cap-mmc-highspeed; +- st,sig-pin-fbclk; +- full-pwr-cycle; +- +- vmmc-supply = <&ab8500_ldo_aux3_reg>; +- vqmmc-supply = <&sd_level_translator>; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc0_a_2_default>; +- pinctrl-1 = <&mc0_a_2_sleep>; +- }; +- +- /* WLAN SDIO */ +- mmc@80118000 { +- status = "okay"; +- +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <50000000>; +- bus-width = <4>; +- +- non-removable; +- cap-sd-highspeed; +- +- vmmc-supply = <&wl_reg_on>; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc1_a_2_default>; +- pinctrl-1 = <&mc1_a_2_sleep>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- wifi@1 { +- compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; +- reg = <1>; +- +- /* GPIO216 (WLAN_HOST_WAKE) */ +- interrupt-parent = <&gpio6>; +- interrupts = <24 IRQ_TYPE_EDGE_FALLING>; +- interrupt-names = "host-wake"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_default>; +- }; +- }; +- +- /* eMMC */ +- mmc@80005000 { +- status = "okay"; +- +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <100000000>; +- bus-width = <8>; +- +- non-removable; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- no-sdio; +- no-sd; +- +- vmmc-supply = <&vmem_3v3>; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc2_a_1_default>; +- pinctrl-1 = <&mc2_a_1_sleep>; +- }; +- +- /* BT UART */ +- uart@80120000 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u0_a_1_default>; +- pinctrl-1 = <&u0_a_1_sleep>; +- +- bluetooth { +- /* BCM4334B0 actually */ +- compatible = "brcm,bcm4330-bt"; +- /* GPIO222 (BT_VREG_ON) */ +- shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; +- /* GPIO199 (BT_WAKE) */ +- device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; +- /* GPIO97 (BT_HOST_WAKE) */ +- host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&bluetooth_default>; +- }; +- }; +- +- /* GPF UART */ +- uart@80121000 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; +- pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; +- }; +- +- /* Debugging console UART */ +- uart@80007000 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u2rxtx_c_1_default>; +- pinctrl-1 = <&u2rxtx_c_1_sleep>; +- }; +- +- i2c@80004000 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c0_a_1_default>; +- pinctrl-1 = <&i2c0_a_1_sleep>; +- +- proximity@44 { +- compatible = "sharp,gp2ap002s00f"; +- reg = <0x44>; +- +- /* GPIO146 (PS_INT) */ +- interrupt-parent = <&gpio4>; +- interrupts = <18 IRQ_TYPE_EDGE_FALLING>; +- +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vio-supply = <&ab8500_ldo_aux8_reg>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&proximity_default>; +- +- sharp,proximity-far-hysteresis = <0x40>; +- sharp,proximity-close-hysteresis = <0x0f>; +- }; +- }; +- +- i2c@80128000 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c2_b_2_default>; +- pinctrl-1 = <&i2c2_b_2_sleep>; +- +- imu@68 { +- compatible = "invensense,mpu6050"; +- reg = <0x68>; +- +- /* GPIO206 (ACC_INT) */ +- interrupt-parent = <&gpio6>; +- interrupts = <14 IRQ_TYPE_EDGE_RISING>; +- +- mount-matrix = "0", "1", "0", +- "-1", "0", "0", +- "0", "0", "1"; +- +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vddio-supply = <&ab8500_ldo_aux8_reg>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&imu_default>; +- }; +- }; +- +- i2c@80110000 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c3_c_2_default>; +- pinctrl-1 = <&i2c3_c_2_sleep>; +- +- touchscreen@4a { +- compatible = "atmel,maxtouch"; +- reg = <0x4a>; +- +- /* GPIO218 (TSP_INT_1V8) */ +- interrupt-parent = <&gpio6>; +- interrupts = <26 IRQ_TYPE_EDGE_FALLING>; +- +- /* VDDA is "analog supply", 2.57-3.47 V */ +- vdda-supply = <&ab8500_ldo_aux2_reg>; +- /* VDD is "digital supply" 1.71-3.47V */ +- vdd-supply = <&ab8500_ldo_aux5_reg>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&tsp_default>; +- }; +- }; +- +- prcmu@80157000 { +- ab8505 { +- ab8500_usb { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&usb_a_1_default>; +- pinctrl-1 = <&usb_a_1_sleep>; +- }; +- +- ab8505-regulators { +- ab8500_ldo_aux1 { +- regulator-name = "sensor_3v"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- ab8500_ldo_aux2 { +- regulator-name = "vreg_tsp_a3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ab8500_ldo_aux3 { +- regulator-name = "vdd_tf_2v91"; +- }; +- +- ab8500_ldo_aux4 { +- regulator-name = "key_led_3.3v"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ab8500_ldo_aux5 { +- regulator-name = "vreg_tsp_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ab8500_ldo_aux6 { +- regulator-name = "touch_key_2.2v"; +- regulator-min-microvolt = <2200000>; +- regulator-max-microvolt = <2200000>; +- }; +- +- ab8500_ldo_aux8 { +- regulator-name = "sensor_1v8"; +- }; +- }; +- }; +- }; +- +- mcde@a0350000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dsi_default_mode>; +- +- dsi@a0351000 { +- panel@0 { +- compatible = "samsung,s6e63m0"; +- reg = <0>; +- max-brightness = <15>; +- vdd3-supply = <&panel_reg_3v0>; +- vci-supply = <&panel_reg_1v8>; +- reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; +- /* ESD (electrostatic discharge) detection interrupt */ +- interrupt-parent = <&gpio2>; +- interrupts = <18 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "esd"; +- pinctrl-names = "default"; +- pinctrl-0 = <&display_default_mode>; +- }; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_default>; +- +- label = "GPIO Buttons"; +- +- volume-up { +- label = "Volume Up"; +- /* GPIO67 (VOL_UP) */ +- gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- volume-down { +- label = "Volume Down"; +- /* GPIO92 (VOL_DOWN) */ +- gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- home { +- label = "Home"; +- /* GPIO91 (HOME_KEY) */ +- gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- /* Richtek RT8515GQW Flash LED Driver IC */ +- flash { +- compatible = "richtek,rt8515"; +- /* GPIO 140 */ +- enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; +- /* GPIO 141 */ +- ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; +- /* +- * RFS is 16 kOhm and RTS is 100 kOhm giving +- * the flash max current 343mA and torch max +- * current 55 mA. +- */ +- richtek,rfs-ohms = <16000>; +- richtek,rts-ohms = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_flash_default_mode>; +- +- led { +- function = LED_FUNCTION_FLASH; +- color = ; +- flash-max-timeout-us = <250000>; +- flash-max-microamp = <343750>; +- led-max-microamp = <55000>; +- }; +- }; +- +- vibrator { +- compatible = "gpio-vibrator"; +- /* GPIO195 (MOT_EN) */ +- enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&vibrator_default>; +- }; +- +- /* External LDO for eMMC */ +- vmem_3v3: regulator-vmem { +- compatible = "regulator-fixed"; +- +- regulator-name = "vmem_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- +- startup-delay-us = <200>; +- +- /* GPIO223 (MEM_LDO_EN) */ +- gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&mem_ldo_default>; +- }; +- +- /* TI TXS0206-29 level translator for 2.9 V */ +- sd_level_translator: regulator-sd-level-translator { +- compatible = "regulator-fixed"; +- +- regulator-name = "sd-level-translator"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- +- startup-delay-us = <200>; +- +- /* GPIO87 (TXS0206-29_EN) */ +- gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sd_level_translator_default>; +- }; +- +- /* +- * WL_REG_ON takes WLAN out of reset and enables the internal regulators. +- * The voltage specified here is only used to determine the OCR mask, +- * the BCM chip is actually connected directly to VBAT. +- */ +- wl_reg_on: regulator-wl-reg-on { +- compatible = "regulator-fixed"; +- +- regulator-name = "wl-reg-on"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- +- startup-delay-us = <100000>; +- +- /* GPIO215 (WLAN_EN) */ +- gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_en_default>; +- }; +- +- /* MIC5366 GPIO-controlled regulator */ +- panel_reg_1v8: regulator-panel-1v8 { +- compatible = "regulator-fixed"; +- +- regulator-name = "panel-fixed-supply"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- /* GPIO219 */ +- gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; +- +- startup-delay-us = <200>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&panel_reg_default_mode>; +- }; +- +- /* MIC5366 GPIO-controlled regulator */ +- panel_reg_3v0: regulator-panel-3v0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "panel-fixed-supply"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- /* GPIO219 */ +- gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; +- +- startup-delay-us = <200>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&panel_reg_default_mode>; +- }; +-}; +- +-&pinctrl { +- gpio-keys { +- gpio_keys_default: gpio_keys_default { +- golden_cfg1 { +- pins = "GPIO67", /* VOL_UP */ +- "GPIO91", /* HOME_KEY */ +- "GPIO92"; /* VOL_DOWN */ +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- +- i2c-gpio-0 { +- i2c_gpio_0_default: i2c_gpio_0 { +- golden_cfg1 { +- pins = "GPIO77", /* TOUCHKEY_SCL */ +- "GPIO78"; /* TOUCHKEY_SDA */ +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- +- flash { +- gpio_flash_default_mode: flash_default { +- golden_cfg1 { +- pins = "GPIO140_B11", "GPIO141_C12"; +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- +- i2c-gpio-1 { +- i2c_gpio_1_default: i2c_gpio_1 { +- golden_cfg1 { +- pins = "GPIO151", /* COMP_SCL */ +- "GPIO152"; /* COMP_SDA */ +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- +- touchkey { +- touchkey_default: touchkey_default { +- golden_cfg1 { +- pins = "GPIO79"; /* TOUCHKEY_INT */ +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- +- sdi0 { +- sd_level_translator_default: sd_level_translator_default { +- golden_cfg1 { +- pins = "GPIO87_B3"; /* TXS0206-29_EN */ +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- +- sdi2 { +- mem_ldo_default: mem_ldo_default { +- golden_cfg1 { +- pins = "GPIO223_AH9"; /* MEM_LDO_EN */ +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- +- mcde { +- dsi_default_mode: dsi_default { +- default_mux1 { +- /* Mux in VSI0 used for DSI TE */ +- function = "lcd"; +- groups = +- "lcdvsi0_a_1"; /* VSI0 for LCD */ +- }; +- default_cfg1 { +- pins = +- "GPIO68_E1"; /* VSI0 */ +- ste,config = <&in_nopull>; +- }; +- }; +- }; +- +- display { +- display_default_mode: display_default { +- golden_cfg1 { +- pins = "GPIO139_C9"; /* MIPI_DSI0_RESET_N */ +- ste,config = <&gpio_out_lo>; +- }; +- golden_cfg2 { +- pins = "GPIO82_C1"; /* LDI_ESD_DET */ +- ste,config = <&gpio_in_pu>; +- }; +- }; +- panel_reg_default_mode: panel_reg_default { +- golden_cfg1 { +- pins = "GPIO219_AG10"; /* LCD_PWR_EN */ +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- +- proximity { +- proximity_default: proximity_default { +- golden_cfg1 { +- pins = "GPIO146_D13"; /* PS_INT */ +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- +- imu { +- imu_default: imu_default { +- golden_cfg1 { +- pins = "GPIO206_AG24"; /* ACC_INT */ +- ste,config = <&gpio_in_pd>; +- }; +- }; +- }; +- +- tsp { +- tsp_default: tsp_default { +- golden_cfg1 { +- pins = "GPIO218_AH11"; /* TSP_INT_1V8 */ +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- +- wlan { +- wlan_default: wlan_default { +- golden_cfg1 { +- pins = "GPIO216_AG12"; /* WLAN_HOST_WAKE */ +- ste,config = <&gpio_in_pd>; +- }; +- }; +- +- wlan_en_default: wlan_en_default { +- golden_cfg1 { +- pins = "GPIO215_AH13"; /* WLAN_EN */ +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- +- bluetooth { +- bluetooth_default: bluetooth_default { +- golden_cfg1 { +- pins = "GPIO199_AH23", /* BT_WAKE */ +- "GPIO222_AJ9"; /* BT_VREG_ON */ +- ste,config = <&gpio_out_lo>; +- }; +- golden_cfg2 { +- pins = "GPIO97_D9"; /* BT_HOST_WAKE */ +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- +- vibrator { +- vibrator_default: vibrator_default { +- golden_cfg1 { +- pins = "GPIO195_AG28"; /* MOT_EN */ +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +-}; +- +-&ab8505_gpio { +- /* Hog a few default settings */ +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_default>; +- +- gpio { +- gpio_default: gpio_default { +- golden_mux { +- /* Change unused pins to GPIO mode */ +- function = "gpio"; +- groups = "gpio3_a_1", /* default: SysClkReq4 */ +- "gpio14_a_1"; /* default: PWMOut1 */ +- }; +- golden_cfg1 { +- pins = "GPIO11_B17", "GPIO13_D17", "GPIO50_L4"; +- bias-disable; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-ux500-samsung-janice.dts b/scripts/dtc/include-prefixes/arm/ste-ux500-samsung-janice.dts +deleted file mode 100644 +index f14cf316a70a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-ux500-samsung-janice.dts ++++ /dev/null +@@ -1,919 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Devicetree for the Samsung Galaxy S Advance GT-I9070 also known as Janice. +- */ +- +-/dts-v1/; +-#include "ste-db8500.dtsi" +-#include "ste-ab8500.dtsi" +-#include "ste-dbx5x0-pinctrl.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "Samsung Galaxy S Advance (GT-I9070)"; +- compatible = "samsung,janice", "st-ericsson,u8500"; +- +- chosen { +- stdout-path = &serial2; +- }; +- +- /* External LDO for eMMC LDO VMEM_3V3 controlled by GPIO6 */ +- ldo_3v3_reg: regulator-gpio-ldo-3v3 { +- compatible = "regulator-fixed"; +- /* Supplied in turn by VBAT */ +- regulator-name = "VMEM_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <5000>; // FIXME +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_ldo_en_default_mode>; +- }; +- +- /* +- * External Ricoh "TSP" regulator for the touchscreen. +- * One GPIO line controls two voltages of 3.3V and 1.8V +- * this line is known as "TSP_LDO_ON1" in the schematics. +- */ +- ldo_tsp_3v3_reg: regulator-gpio-tsp-ldo-3v3 { +- compatible = "regulator-fixed"; +- /* Supplied in turn by VBAT */ +- regulator-name = "LDO_TSP_A3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- /* GPIO94 controls this regulator */ +- gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; +- /* 70 ms power-on delay */ +- startup-delay-us = <70000>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsp_ldo_en_default_mode>; +- }; +- ldo_tsp_1v8_reg: regulator-gpio-tsp-ldo-1v8 { +- compatible = "regulator-fixed"; +- /* Supplied in turn by VBAT */ +- regulator-name = "VREG_TSP_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- /* GPIO94 controls this regulator */ +- gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; +- /* 70 ms power-on delay */ +- startup-delay-us = <70000>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsp_ldo_en_default_mode>; +- }; +- +- /* +- * External Ricoh "TSP" regulator for the touchkeys. +- * Two GPIO lines controls two voltages of 3.3V and 1.8V +- * TSP_LDO_ON2 controls VREG_TOUCHKEY_1V8 +- * EN_LED_LDO controls VREG_KLED_3V3 (key LED) +- */ +- ldo_kled_3v3_reg: regulator-gpio-vreg-kled-3v3 { +- compatible = "regulator-fixed"; +- /* Supplied in turn by VBAT */ +- regulator-name = "VREG_KLED_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- /* GPIO68 controls this regulator */ +- gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>; +- /* 70 ms power-on delay */ +- startup-delay-us = <70000>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&en_led_ldo_default_mode>; +- }; +- ldo_touchkey_1v8_reg: regulator-gpio-vreg-touchkey-1v8 { +- compatible = "regulator-fixed"; +- /* Supplied in turn by VBAT */ +- regulator-name = "VREG_TOUCHKEY_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- /* GPIO89 controls this regulator */ +- gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; +- /* 70 ms power-on delay */ +- startup-delay-us = <70000>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsp_ldo_on2_default_mode>; +- }; +- +- +- /* +- * External Ricoh RP152L010B-TR LCD LDO regulator for the display. +- * LCD_PWR_EN controls a 3.0V and 1.8V output. +- */ +- lcd_3v0_reg: regulator-gpio-lcd-3v0 { +- compatible = "regulator-fixed"; +- /* Supplied in turn by VBAT */ +- regulator-name = "VREG_LCD_3V0"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- /* GPIO219 controls this regulator */ +- gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_pwr_en_default_mode>; +- }; +- lcd_1v8_reg: regulator-gpio-lcd-1v8 { +- compatible = "regulator-fixed"; +- /* Supplied in turn by VBAT */ +- regulator-name = "VREG_LCD_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- /* GPIO219 controls this regulator */ +- gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_pwr_en_default_mode>; +- }; +- +- /* +- * This regulator is a GPIO line that drives the Broadcom WLAN +- * line WL_REG_ON high and enables the internal regulators +- * inside the chip. Unfortunatley it is erroneously named +- * WLAN_RST_N on the schematic but it is not a reset line. +- * +- * The voltage specified here is only used to determine the OCR mask, +- * the for the SDIO connector, the chip is actually connected +- * directly to VBAT. +- */ +- wl_reg: regulator-gpio-wlan { +- compatible = "regulator-fixed"; +- regulator-name = "WL_REG_ON"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- startup-delay-us = <100000>; +- /* GPIO215 (WLAN_RST_N to WL_REG_ON) */ +- gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_ldo_en_default>; +- }; +- +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_default_mode>; +- +- button-home { +- linux,code = ; +- label = "HOME"; +- /* GPIO91 */ +- gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; +- }; +- button-volup { +- linux,code = ; +- label = "VOL+"; +- /* GPIO67 */ +- gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; +- }; +- button-voldown { +- linux,code = ; +- label = "VOL-"; +- /* GPIO92 */ +- gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- /* Richtek RT8515GQW Flash LED Driver IC */ +- flash { +- compatible = "richtek,rt8515"; +- /* GPIO 140 */ +- enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; +- /* GPIO 141 */ +- ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; +- /* +- * RFS is 16 kOhm and RTS is 100 kOhm giving +- * the flash max current 343mA and torch max +- * current 55 mA. +- */ +- richtek,rfs-ohms = <16000>; +- richtek,rts-ohms = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_flash_default_mode>; +- +- led { +- function = LED_FUNCTION_FLASH; +- color = ; +- flash-max-timeout-us = <250000>; +- flash-max-microamp = <343750>; +- led-max-microamp = <55000>; +- }; +- }; +- +- /* Bit-banged I2C on GPIO143 and GPIO144 also called "SUBPMU I2C" */ +- i2c-gpio-0 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_gpio_0_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Yamaha YAS530 magnetometer */ +- magnetometer@2e { +- compatible = "yamaha,yas530"; +- reg = <0x2e>; +- /* VDD 3V */ +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- /* IOVDD 1.8V */ +- iovdd-supply = <&ab8500_ldo_aux2_reg>; +- /* GPIO204 COMPASS_RST_N */ +- reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&yas529_default>; +- }; +- /* TODO: this should also be used by the NCP6914 Camera power management unit */ +- }; +- +- /* +- * These pins do have an spi controller, however the controller on +- * these pins is not the fully featured PL022 SSP/SPI block but the +- * ST Micro diet "PL023" version. One of the lacking features in +- * this derivative is 3wire support, so it cannot be used to drive +- * this panel interface. We have to use GPIO bit-banging instead. +- */ +- spi-gpio-0 { +- compatible = "spi-gpio"; +- /* Clock on GPIO220 */ +- sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; +- /* MISO/MOSI on GPIO224 (no separate MISO pin) */ +- mosi-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; +- /* Chip select on GPIO223 */ +- cs-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>; +- num-chipselects = <1>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_gpio_0_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- panel@0 { +- compatible = "samsung,s6e63m0"; +- reg = <0>; +- vdd3-supply = <&lcd_3v0_reg>; +- vci-supply = <&lcd_1v8_reg>; +- /* Reset on GPIO139 */ +- reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&panel_default_mode>; +- spi-3wire; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&display_out>; +- }; +- }; +- }; +- }; +- +- /* +- * Current sense amplifier on the light sensor to convert current to +- * voltage. We do not know if this is the actual configuration. The +- * sense resistor value was found by calibrating in a room ambient +- * light with a second mobile phone light sensor as reference. If you +- * pry a Janice phone apart and inspect it you may figure this out. +- */ +- gp2a_shunt: current-sense-shunt { +- compatible = "current-sense-shunt"; +- io-channels = <&gpadc 0x07>; +- shunt-resistor-micro-ohms = <15000000>; /* 15 ohms c:a */ +- #io-channel-cells = <0>; +- io-channel-ranges; +- }; +- +- /* Bit-banged I2C on GPIO196 and GPIO197 also called "TOUCHKEY_I2C" */ +- i2c-gpio-1 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio6 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio6 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_gpio_1_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- touchkey@20 { +- compatible = "coreriver,tc360-touchkey"; +- reg = <0x20>; +- vdd-supply = <&ldo_kled_3v3_reg>; +- vcc-supply = <&ldo_touchkey_1v8_reg>; +- vddio-supply = <&ldo_touchkey_1v8_reg>; +- +- /* Interrupt on GPIO 198 */ +- interrupt-parent = <&gpio6>; +- interrupts = <6 IRQ_TYPE_EDGE_RISING>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&touchkey_default_mode>; +- linux,keycodes = ; +- }; +- }; +- +- /* Bit-banged I2C on GPIO201 and GPIO202 also called "MOT_I2C" */ +- i2c-gpio-2 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio6 10 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio6 9 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_gpio_2_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- /* TODO: add the Immersion ISA1200 I2C device here */ +- }; +- +- /* Bit-banged I2C on GPIO151 and GPIO152 also called "NFC_I2C" */ +- i2c-gpio-3 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_gpio_3_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- nfc@30 { +- compatible = "nxp,pn547", "nxp,nxp-nci-i2c"; +- reg = <0x30>; +- /* NFC IRQ on GPIO32 */ +- interrupt-parent = <&gpio1>; +- interrupts = <0 IRQ_TYPE_EDGE_FALLING>; +- /* GPIO 31 */ +- firmware-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; +- /* GPIO88 */ +- enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pn547_janice_default>; +- }; +- }; +- +- soc { +- /* External Micro SD slot */ +- mmc@80126000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <50000000>; +- bus-width = <4>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- st,sig-dir-cmd; +- st,sig-dir-dat0; +- st,sig-dir-dat2; +- st,sig-pin-fbclk; +- full-pwr-cycle; +- /* MMC is powered by AUX3 1.2V .. 2.91V */ +- vmmc-supply = <&ab8500_ldo_aux3_reg>; +- /* 2.9 V level translator is using AUX3 at 2.9 V as well */ +- vqmmc-supply = <&ab8500_ldo_aux3_reg>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc0_a_2_default>; +- pinctrl-1 = <&mc0_a_2_sleep>; +- cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217 +- status = "okay"; +- }; +- +- /* WLAN SDIO channel */ +- mmc@80118000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <50000000>; +- bus-width = <4>; +- non-removable; +- cap-sd-highspeed; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc1_a_2_default>; +- pinctrl-1 = <&mc1_a_2_sleep>; +- /* +- * GPIO-controlled voltage enablement: this drives +- * the WL_REG_ON line high when we use this device. +- * Represented as regulator to fill OCR mask. +- */ +- vmmc-supply = <&wl_reg>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- wifi@1 { +- compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; +- reg = <1>; +- /* GPIO216 WL_HOST_WAKE */ +- interrupt-parent = <&gpio6>; +- interrupts = <24 IRQ_TYPE_EDGE_FALLING>; +- interrupt-names = "host-wake"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_default_mode>; +- }; +- }; +- +- /* eMMC */ +- mmc@80005000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <50000000>; +- bus-width = <8>; +- non-removable; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- no-sdio; +- no-sd; +- vmmc-supply = <&ldo_3v3_reg>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc2_a_1_default>; +- pinctrl-1 = <&mc2_a_1_sleep>; +- status = "okay"; +- }; +- +- /* GBF (Bluetooth) UART */ +- uart@80120000 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u0_a_1_default>; +- pinctrl-1 = <&u0_a_1_sleep>; +- status = "okay"; +- +- bluetooth { +- /* BCM4330B1 actually */ +- compatible = "brcm,bcm4330-bt"; +- /* GPIO222 rail BT_VREG_EN to BT_REG_ON */ +- shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; +- /* BT_WAKE on GPIO199 */ +- device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; +- /* BT_HOST_WAKE on GPIO97 */ +- /* FIXME: convert to interrupt */ +- host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; +- /* BT_RST_N on GPIO209 */ +- reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bluetooth_default_mode>; +- }; +- }; +- +- /* GPS UART */ +- uart@80121000 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- /* CTS/RTS is not used, CTS is repurposed as GPIO */ +- pinctrl-0 = <&u1rxtx_a_1_default>; +- pinctrl-1 = <&u1rxtx_a_1_sleep>; +- /* FIXME: add a device for the GPS here */ +- }; +- +- /* Debugging console UART connected to TSU6111RSVR (FSA880) */ +- uart@80007000 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u2rxtx_c_1_default>; +- pinctrl-1 = <&u2rxtx_c_1_sleep>; +- }; +- +- prcmu@80157000 { +- ab8500 { +- ab8500_usb { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&usb_a_1_default>; +- pinctrl-1 = <&usb_a_1_sleep>; +- }; +- +- ab8500-regulators { +- ab8500_ldo_aux1 { +- /* Used for VDD for sensors */ +- regulator-name = "V-SENSORS-VDD"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- ab8500_ldo_aux2 { +- /* Used for VIO for sensors */ +- regulator-name = "V-SENSORS-VIO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ab8500_ldo_aux3 { +- /* Used for voltage for external MMC/SD card */ +- regulator-name = "V-MMC-SD"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <2910000>; +- }; +- }; +- }; +- }; +- +- /* I2C0 */ +- i2c@80004000 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c0_a_1_default>; +- pinctrl-1 = <&i2c0_a_1_sleep>; +- +- proximity@44 { +- /* Janice has the GP2AP002A00F with light sensor */ +- compatible = "sharp,gp2ap002a00f"; +- clock-frequency = <400000>; +- reg = <0x44>; +- +- interrupt-parent = <&gpio4>; +- interrupts = <18 IRQ_TYPE_EDGE_FALLING>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vio-supply = <&ab8500_ldo_aux2_reg>; +- /* ADC channel AUX2 to read ALSOUT ambient light sensor out */ +- io-channels = <&gp2a_shunt>; +- io-channel-names = "alsout"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gp2ap002_janice_default>; +- /* B1 mode (arch/arm/mach-ux500/include/mach/gp2a.h) */ +- sharp,proximity-far-hysteresis = /bits/ 8 <0x40>; +- sharp,proximity-close-hysteresis = /bits/ 8 <0x0f>; +- }; +- }; +- +- /* I2C1 on GPIO16 and GPIO17 also called "MUS I2C" */ +- i2c@80122000 { +- status = "okay"; +- pinctrl-names = "default","sleep"; +- pinctrl-0 = <&i2c1_b_2_default>; +- pinctrl-1 = <&i2c1_b_2_sleep>; +- +- /* Texas Instruments TSU6111 micro USB switch */ +- usb-switch@25 { +- compatible = "ti,tsu6111"; +- reg = <0x25>; +- /* Interrupt JACK_INT_N on GPIO95 */ +- interrupt-parent = <&gpio2>; +- interrupts = <31 IRQ_TYPE_EDGE_FALLING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsu6111_janice_default>; +- }; +- }; +- +- /* I2C2 on GPIO10 and GPIO11 also called "SENSORS I2C" */ +- i2c@80128000 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c2_b_2_default>; +- pinctrl-1 = <&i2c2_b_2_sleep>; +- +- gyroscope@68 { +- compatible = "invensense,mpu3050"; +- reg = <0x68>; +- /* GPIO226 interrupt */ +- interrupt-parent = <&gpio7>; +- interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +- /* FIXME: no idea about this */ +- mount-matrix = "1", "0", "0", +- "0", "1", "0", +- "0", "0", "1"; +- vlogic-supply = <&ab8500_ldo_aux2_reg>; // 1.8V +- vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V +- pinctrl-names = "default"; +- pinctrl-0 = <&mpu3050_janice_default>; +- +- /* +- * The MPU-3050 acts as a hub for the +- * accelerometer. +- */ +- i2c-gate { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Bosch BMA222 accelerometer */ +- accelerometer@8 { +- compatible = "bosch,bma222"; +- reg = <0x08>; +- mount-matrix = "0", "1", "0", +- "-1", "0", "0", +- "0", "0", "-1"; +- vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V +- vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V +- }; +- }; +- }; +- }; +- +- /* I2C3 */ +- i2c@80110000 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c3_c_2_default>; +- pinctrl-1 = <&i2c3_c_2_sleep>; +- +- /* Atmel mXT224E touchscreen */ +- touchscreen@4a { +- compatible = "atmel,maxtouch"; +- reg = <0x4a>; +- /* GPIO218 (TSP_INT_1V8) */ +- interrupt-parent = <&gpio6>; +- interrupts = <26 IRQ_TYPE_EDGE_FALLING>; +- /* VDDA is "analog supply", 2.57-3.47 V */ +- vdda-supply = <&ldo_tsp_3v3_reg>; +- /* VDD is "digital supply" 1.71-3.47V */ +- vdd-supply = <&ldo_tsp_1v8_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tsp_default>; +- }; +- }; +- +- mcde@a0350000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dpi_default_mode>; +- +- port { +- display_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +- }; +-}; +- +-&pinctrl { +- /* +- * This extends the MC0_A_2 default config to include +- * the card detect GPIO217 line. +- */ +- sdi0 { +- mc0_a_2_default { +- default_cfg4 { +- pins = "GPIO217_AH12"; /* card detect */ +- ste,config = <&gpio_in_pd>; +- }; +- }; +- }; +- mcde { +- dpi_default_mode: dpi_default { +- default_mux1 { +- /* Mux in all the data lines */ +- function = "lcd"; +- groups = +- /* Data lines D0-D7 GPIO70..GPIO77 */ +- "lcd_d0_d7_a_1", +- /* Data lines D8-D11 GPIO78..GPIO81 */ +- "lcd_d8_d11_a_1", +- /* Data lines D12-D15 GPIO82..GPIO85 */ +- "lcd_d12_d15_a_1", +- /* Data lines D16-D23 GPIO161..GPIO168 */ +- "lcd_d16_d23_b_1"; +- }; +- default_mux2 { +- function = "lcda"; +- /* Clock line on GPIO150, DE, VSO, HSO on GPIO169..GPIO171 */ +- groups = "lcdaclk_b_1", "lcda_b_1"; +- }; +- /* Input, no pull-up is the default state for pins used for an alt function */ +- default_cfg1 { +- pins = "GPIO150_C14", "GPIO169_D22", "GPIO170_C23", "GPIO171_D23"; +- ste,config = <&in_nopull>; +- }; +- }; +- }; +- /* GPIO for panel reset control */ +- panel { +- panel_default_mode: panel_default { +- janice_cfg1 { +- /* Reset line */ +- pins = "GPIO139_C9"; +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- /* GPIO that enables the LDO regulator for the eMMC */ +- emmc-ldo { +- emmc_ldo_en_default_mode: emmc_ldo_default { +- /* LDO enable on GPIO6 */ +- janice_cfg1 { +- pins = "GPIO6_AF6"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* GPIO that enables the LDO regulator for the touchscreen */ +- tsp-ldo { +- tsp_ldo_en_default_mode: tsp_ldo_default { +- /* LDO enable on GPIO94 */ +- janice_cfg1 { +- pins = "GPIO94_D7"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* GPIO that enables the LDO regulator for the key LED */ +- key-led { +- en_led_ldo_default_mode: en_led_ldo_default { +- /* EN_LED_LDO on GPIO68 */ +- janice_cfg1 { +- pins = "GPIO68_E1"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* GPIO that enables the LDO regulator for the touchkeys */ +- touchkey-ldo { +- tsp_ldo_on2_default_mode: tsp_ldo_on2_default { +- /* TSP_LDO_ON2 on GPIO89 */ +- janice_cfg1 { +- pins = "GPIO89_E6"; +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- touchkey { +- touchkey_default_mode: touchkey_default { +- janice_cfg1 { +- /* Interrupt */ +- pins = "GPIO198_AG25"; +- ste,config = <&gpio_in_nopull>; +- }; +- janice_cfg2 { +- /* Reset, actually completely unused (not routed) */ +- pins = "GPIO205_AG23"; +- ste,config = <&gpio_in_pd>; +- }; +- }; +- }; +- /* GPIO that enabled the LDO regulator for the LCD display */ +- lcd-ldo { +- lcd_pwr_en_default_mode: lcd_pwr_en_default { +- /* LCD_PWR_EN on GPIO219 */ +- janice_cfg1 { +- pins = "GPIO219_AG10"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* GPIO that enables the WLAN internal LDO regulators */ +- wlan-ldo { +- wlan_ldo_en_default: wlan_ldo_default { +- /* GPIO215 named WLAN_RST_N */ +- janice_cfg1 { +- pins = "GPIO215_AH13"; +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- /* Flash and torch */ +- flash { +- gpio_flash_default_mode: flash_default { +- janice_cfg1 { +- pins = "GPIO140_B11", "GPIO141_C12"; +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- /* GPIO keys */ +- gpio-keys { +- gpio_keys_default_mode: gpio_keys_default { +- skomer_cfg1 { +- pins = "GPIO67_G2", /* VOL UP */ +- "GPIO91_B6", /* HOME */ +- "GPIO92_D6"; /* VOL DOWN */ +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- /* Interrupt line for the Atmel MXT228 touchscreen */ +- tsp { +- tsp_default: tsp_default { +- janice_cfg1 { +- pins = "GPIO218_AH11"; /* TSP_INT_1V8 */ +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* Reset line for the Yamaha YAS529 magnetometer */ +- yas529 { +- yas529_default: yas529_janice { +- janice_cfg1 { +- pins = "GPIO204_AF23"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* Interrupt line for light/proximity sensor GP2AP002 */ +- gp2ap002 { +- gp2ap002_janice_default: gp2ap002_janice { +- janice_cfg1 { +- pins = "GPIO146_D13"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* Interrupt line for Invensense MPU3050 gyroscope */ +- mpu3050 { +- mpu3050_janice_default: mpu3050_janice { +- janice_cfg1 { +- /* GPIO226 used for IRQ */ +- pins = "GPIO226_AF8"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* GPIO-based I2C bus for magnetometer and NCP6914 */ +- i2c-gpio-0 { +- i2c_gpio_0_default: i2c_gpio_0 { +- janice_cfg1 { +- pins = "GPIO143_D12", "GPIO144_B13"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* GPIO-based I2C bus for the Cypress touchkeys */ +- i2c-gpio-1 { +- i2c_gpio_1_default: i2c_gpio_1 { +- janice_cfg1 { +- pins = "GPIO196_AG26", "GPIO197_AH24"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* GPIO-based I2C bus for the Immersion ISA1200 */ +- i2c-gpio-2 { +- i2c_gpio_2_default: i2c_gpio_2 { +- janice_cfg1 { +- pins = "GPIO201_AF24", "GPIO202_AF25"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* GPIO-based I2C bus for the NFC */ +- i2c-gpio-3 { +- i2c_gpio_3_default: i2c_gpio_3 { +- janice_cfg1 { +- pins = "GPIO151_D17", "GPIO152_D16"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* GPIO-based SPI bus for the display */ +- spi-gpio-0 { +- spi_gpio_0_default: spi_gpio_0 { +- janice_cfg1 { +- pins = "GPIO220_AH10", "GPIO223_AH9", "GPIO224_AG9"; +- ste,config = <&gpio_out_hi>; +- }; +- /* This pin is unused but belongs with this SPI block */ +- janice_cfg2 { +- pins = "GPIO225_AG8"; +- ste,config = <&in_pd>; +- }; +- }; +- }; +- wlan { +- wlan_default_mode: wlan_default { +- /* GPIO216 for WL_HOST_WAKE */ +- janice_cfg2 { +- pins = "GPIO216_AG12"; +- ste,config = <&gpio_in_pd>; +- }; +- }; +- }; +- bluetooth { +- bluetooth_default_mode: bluetooth_default { +- /* GPIO199 BT_WAKE and GPIO222 BT_VREG_ON */ +- janice_cfg1 { +- pins = "GPIO199_AH23", "GPIO222_AJ9"; +- ste,config = <&gpio_out_lo>; +- }; +- /* GPIO97 BT_HOST_WAKE */ +- janice_cfg2 { +- pins = "GPIO97_D9"; +- ste,config = <&gpio_in_nopull>; +- }; +- /* GPIO209 BT_RST_N */ +- janice_cfg3 { +- pins = "GPIO209_AG15"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* Interrupt line for TI TSU6111 Micro USB switch */ +- tsu6111 { +- tsu6111_janice_default: tsu6111_janice { +- janice_cfg1 { +- /* GPIO95 used for IRQ */ +- pins = "GPIO95_E8"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- nfc { +- pn547_janice_default: pn547_janice { +- /* Interrupt line */ +- janice_cfg1 { +- pins = "GPIO32_V2"; +- ste,config = <&gpio_in_nopull>; +- }; +- /* Enable and firmware GPIOs */ +- janice_cfg2 { +- pins = "GPIO31_V3", "GPIO88_C4"; +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-ux500-samsung-kyle.dts b/scripts/dtc/include-prefixes/arm/ste-ux500-samsung-kyle.dts +deleted file mode 100644 +index 3b825666d302..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-ux500-samsung-kyle.dts ++++ /dev/null +@@ -1,664 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Devicetree for the Samsung Galaxy Amp SGH-I407 also known as Kyle. +- * +- * The code also refers to "Kyle AT&T" reflecting that this mobile phone +- * was customized for the AT&T subsidiary Aio Wireless (All In One) and +- * offered by the company in 2013. +- */ +- +-/dts-v1/; +-#include "ste-db8500.dtsi" +-#include "ste-ab8505.dtsi" +-#include "ste-dbx5x0-pinctrl.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "Samsung Galaxy Amp (SGH-I407)"; +- compatible = "samsung,kyle", "st-ericsson,u8500"; +- +- chosen { +- stdout-path = &serial2; +- }; +- +- /* TI TXS0206 level translator for 2.9 V */ +- sd_level_translator: regulator-gpio { +- compatible = "regulator-fixed"; +- +- /* GPIO87 EN */ +- gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- regulator-name = "sd-level-translator"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- regulator-type = "voltage"; +- +- startup-delay-us = <200>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sd_level_translator_default>; +- }; +- +- /* External LDO MIC5366-3.3YMT for eMMC */ +- ldo_3v3_reg: regulator-gpio-ldo-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "en-3v3-fixed-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <5000>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_ldo_en_default_mode>; +- }; +- +- /* +- * External Ricoh RP152L010B-TR LCD LDO regulator for the display. +- * LCD_PWR_EN controls both a 3.0V and 1.8V output. +- */ +- lcd_3v0_reg: regulator-gpio-lcd-3v0 { +- compatible = "regulator-fixed"; +- /* Supplied in turn by VBAT */ +- regulator-name = "VREG_LCD_3V0"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- /* GPIO219 controls this regulator */ +- gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_pwr_en_default_mode>; +- }; +- lcd_1v8_reg: regulator-gpio-lcd-1v8 { +- compatible = "regulator-fixed"; +- /* Supplied in turn by VBAT */ +- regulator-name = "VREG_LCD_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- /* GPIO219 controls this regulator too */ +- gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_pwr_en_default_mode>; +- }; +- +- wlan_en: regulator-gpio-wlan-en { +- compatible = "regulator-fixed"; +- regulator-name = "wl-reg-on"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- startup-delay-us = <200000>; +- /* GPIO215 WLAN_EN */ +- gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_en_default_mode>; +- }; +- +- vibrator { +- compatible = "gpio-vibrator"; +- enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vibrator_default>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_default_mode>; +- +- button-home { +- linux,code = ; +- label = "HOME"; +- /* GPIO91 */ +- gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; +- }; +- button-volup { +- linux,code = ; +- label = "VOL+"; +- /* GPIO67 */ +- gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; +- }; +- button-voldown { +- linux,code = ; +- label = "VOL-"; +- /* GPIO92 */ +- gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- ktd253: backlight { +- compatible = "kinetic,ktd253"; +- /* GPIO 69 */ +- enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; +- /* Default to 13/32 brightness */ +- default-brightness = <13>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_backlight_default_mode>; +- }; +- +- /* Richtek RT8515GQW Flash LED Driver IC */ +- flash { +- compatible = "richtek,rt8515"; +- /* GPIO 140 */ +- enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; +- /* GPIO 141 */ +- ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; +- /* +- * RFS is 16 kOhm and RTS is 100 kOhm giving +- * the flash max current 343mA and torch max +- * current 55 mA. +- */ +- richtek,rfs-ohms = <16000>; +- richtek,rts-ohms = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_flash_default_mode>; +- +- led { +- function = LED_FUNCTION_FLASH; +- color = ; +- flash-max-timeout-us = <250000>; +- flash-max-microamp = <343750>; +- led-max-microamp = <55000>; +- }; +- }; +- +- i2c-gpio-0 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_gpio_0_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- /* TODO: this should be used by the NCP6914 Camera power management unit */ +- }; +- +- i2c-gpio-1 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_gpio_1_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- magnetometer@c { +- compatible = "alps,hscdtd008a"; +- reg = <0x0c>; +- avdd-supply = <&ab8500_ldo_aux1_reg>; +- dvdd-supply = <&ab8500_ldo_aux6_reg>; +- }; +- }; +- +- soc { +- // External Micro SD slot +- mmc@80126000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <100000000>; +- bus-width = <4>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- st,sig-pin-fbclk; +- full-pwr-cycle; +- vmmc-supply = <&ab8500_ldo_aux3_reg>; +- vqmmc-supply = <&sd_level_translator>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc0_a_1_default>; +- pinctrl-1 = <&mc0_a_1_sleep>; +- cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217 +- status = "okay"; +- }; +- +- // WLAN SDIO channel +- mmc@80118000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <50000000>; +- bus-width = <4>; +- non-removable; +- cap-sd-highspeed; +- vmmc-supply = <&wlan_en>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc1_a_2_default>; +- pinctrl-1 = <&mc1_a_2_sleep>; +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- wifi@1 { +- compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; +- reg = <1>; +- /* GPIO216 WL_HOST_WAKE */ +- interrupt-parent = <&gpio6>; +- interrupts = <24 IRQ_TYPE_EDGE_FALLING>; +- interrupt-names = "host-wake"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_default_mode>; +- }; +- }; +- +- /* +- * eMMC seems to be mostly Samsung KLM4G1YE4C "4YMD1R" +- */ +- mmc@80005000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <100000000>; +- bus-width = <8>; +- non-removable; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- no-sdio; +- no-sd; +- /* From datasheet page 26 figure 9: 300 ms set-up time for 4GB */ +- post-power-on-delay-ms = <300>; +- vmmc-supply = <&ldo_3v3_reg>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc2_a_1_default>; +- pinctrl-1 = <&mc2_a_1_sleep>; +- +- status = "okay"; +- }; +- +- /* GBF (Bluetooth) UART */ +- uart@80120000 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u0_a_1_default>; +- pinctrl-1 = <&u0_a_1_sleep>; +- status = "okay"; +- +- bluetooth { +- /* BCM4334B0 actually */ +- compatible = "brcm,bcm4330-bt"; +- shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; +- device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bluetooth_default_mode>; +- }; +- }; +- +- /* GPF UART */ +- uart@80121000 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; +- pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; +- }; +- +- /* Debugging console UART connected to AB8505 USB */ +- uart@80007000 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u2rxtx_c_1_default>; +- pinctrl-1 = <&u2rxtx_c_1_sleep>; +- }; +- +- prcmu@80157000 { +- ab8505 { +- ab8500_usb { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&usb_a_1_default>; +- pinctrl-1 = <&usb_a_1_sleep>; +- }; +- +- ab8505-regulators { +- ab8500_ldo_aux1 { +- /* Used for VDD for sensors */ +- regulator-name = "AUX1"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ab8500_ldo_aux2 { +- /* Supplies the MMS touchscreen only with 3.3V */ +- regulator-name = "AUX2"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ab8500_ldo_aux3 { +- /* Used for voltage for external MMC/SD card */ +- regulator-name = "AUX3"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ab8500_ldo_aux4 { +- regulator-name = "AUX4"; +- /* Hammer to 3.3V for the touchscreen */ +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ab8500_ldo_aux5 { +- regulator-name = "AUX5"; +- /* 1.8V for the touchscreen */ +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ab8500_ldo_aux6 { +- regulator-name = "AUX6"; +- /* Used by sensors for 1.8 V in R0.1+ */ +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ab8500_ldo_aux8 { +- /* Unused */ +- regulator-name = "AUX8"; +- }; +- }; +- }; +- }; +- +- /* I2C0 */ +- i2c@80004000 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c0_a_1_default>; +- pinctrl-1 = <&i2c0_a_1_sleep>; +- +- proximity@44 { +- compatible = "sharp,gp2ap002s00f"; +- clock-frequency = <400000>; +- reg = <0x44>; +- +- interrupt-parent = <&gpio4>; +- interrupts = <18 IRQ_TYPE_EDGE_FALLING>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vio-supply = <&ab8500_ldo_aux6_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gp2ap002_kyle_default>; +- sharp,proximity-far-hysteresis = /bits/ 8 <0x2f>; +- sharp,proximity-close-hysteresis = /bits/ 8 <0x0f>; +- }; +- }; +- +- /* I2C2 */ +- i2c@80128000 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c2_b_2_default>; +- pinctrl-1 = <&i2c2_b_2_sleep>; +- +- accel@18 { +- compatible = "bosch,bma254"; +- clock-frequency = <400000>; +- reg = <0x18>; +- +- mount-matrix = "-1", "0", "0", +- "0", "-1", "0", +- "0", "0", "-1"; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vddio-supply = <&ab8500_ldo_aux6_reg>; +- }; +- }; +- +- /* I2C3 */ +- i2c@80110000 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c3_c_2_default>; +- pinctrl-1 = <&i2c3_c_2_sleep>; +- +- /* Melfas MMS134S touchscreen */ +- touchscreen@48 { +- compatible = "melfas,mms134s"; +- reg = <0x48>; +- /* GPIO218 for IRQ */ +- interrupt-parent = <&gpio6>; +- interrupts = <26 IRQ_TYPE_EDGE_FALLING>; +- /* AVDD is "analog supply", 2.57-3.47 V */ +- avdd-supply = <&ab8500_ldo_aux2_reg>; +- /* VDD is "digital supply" 1.71-3.47V */ +- vdd-supply = <&ab8500_ldo_aux5_reg>; +- +- touchscreen-size-x = <480>; +- touchscreen-size-y = <800>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&mms134s_kyle_default>; +- }; +- }; +- +- mcde@a0350000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dsi_default_mode>; +- +- dsi@a0351000 { +- panel { +- /* +- * NT35510-based Hydis HVA40WV1 +- * Apparently some Kyle models can have a NT35512 fitted +- * here instead. In that case the boot loader needs to +- * modify this compatible. +- */ +- compatible = "hydis,hva40wv1", "novatek,nt35510"; +- reg = <0>; +- /* v_lcd_3v0 2.3-4.8V */ +- vdd-supply = <&lcd_3v0_reg>; +- /* v_lcd_1v8 1.65-3.3V */ +- vddi-supply = <&lcd_1v8_reg>; +- /* GPIO 139 */ +- reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&display_default_mode>; +- backlight = <&ktd253>; +- }; +- }; +- }; +- }; +-}; +- +-&pinctrl { +- /* +- * This extends the MC0_A_1 default config to include +- * the card detect GPIO217 line. +- */ +- sdi0 { +- mc0_a_1_default { +- default_cfg1 { +- /* GPIO18, 19 & 20 unused so pull down */ +- ste,config = <&gpio_in_pd>; +- }; +- default_cfg4 { +- pins = "GPIO217_AH12"; /* card detect */ +- ste,config = <&gpio_in_pd>; +- }; +- }; +- }; +- +- mcde { +- dsi_default_mode: dsi_default { +- default_mux1 { +- /* Mux in VSI0 used for DSI TE */ +- function = "lcd"; +- groups = "lcdvsi0_a_1"; /* VSI0 for LCD */ +- }; +- default_cfg1 { +- pins = "GPIO68_E1"; /* VSI0 */ +- ste,config = <&in_nopull>; +- }; +- }; +- }; +- +- /* Two GPIO lines used by the display */ +- display { +- display_default_mode: display_default { +- kyle_cfg1 { +- /* +- * OLED DETECT or check_pba, this appears to be high +- * on "PBA" which I guess is "prototype board A". +- */ +- pins = "GPIO93_B7"; +- ste,config = <&gpio_in_nopull>; +- }; +- kyle_cfg2 { +- pins = "GPIO139_C9"; +- /* +- * MIPI_DSI0_RESET_N resets the display, leave high +- * (de-asserted) so we only assert reset explicitly +- * from the display driver. +- */ +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- +- /* GPIO that enables the LDO regulator for the LCD display */ +- lcd-ldo { +- lcd_pwr_en_default_mode: lcd_pwr_en_default { +- /* LCD_PWR_EN on GPIO219 */ +- kyle_cfg1 { +- pins = "GPIO219_AG10"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- +- backlight { +- gpio_backlight_default_mode: backlight_default { +- kyle_cfg1 { +- pins = "GPIO69_E2"; /* LCD_BL_CTRL */ +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- flash { +- gpio_flash_default_mode: flash_default { +- kyle_cfg1 { +- pins = "GPIO140_B11", "GPIO141_C12"; +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- /* GPIO that enables the 2.9V SD card level translator */ +- sd-level-translator { +- sd_level_translator_default: sd_level_translator_default { +- /* level shifter on GPIO87 */ +- kyle_cfg1 { +- pins = "GPIO87_B3"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* GPIO that enables the LDO regulator for the eMMC */ +- emmc-ldo { +- emmc_ldo_en_default_mode: emmc_ldo_default { +- /* LDO enable on GPIO223 */ +- kyle_cfg1 { +- pins = "GPIO223_AH9"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* GPIO keys */ +- gpio-keys { +- gpio_keys_default_mode: gpio_keys_default { +- kyle_cfg1 { +- pins = "GPIO67_G2", /* VOL UP */ +- "GPIO91_B6", /* HOME */ +- "GPIO92_D6"; /* VOL DOWN */ +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- /* Interrupt line for light/proximity sensor GP2AP002 */ +- gp2ap002 { +- gp2ap002_kyle_default: gp2ap002_kyle { +- kyle_cfg1 { +- pins = "GPIO146_D13"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* GPIO-based I2C bus for NCP6914 */ +- i2c-gpio-0 { +- i2c_gpio_0_default: i2c_gpio_0 { +- kyle_cfg1 { +- pins = "GPIO143_D12", "GPIO144_B13"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* GPIO-based I2C bus for ALPS HSCD compass */ +- i2c-gpio-1 { +- i2c_gpio_1_default: i2c_gpio_1 { +- kyle_cfg1 { +- pins = "GPIO151_B17", "GPIO152_D16"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- wlan { +- wlan_default_mode: wlan_default { +- kyle_cfg1 { +- pins = "GPIO216_AG12"; +- ste,config = <&gpio_in_pd>; +- }; +- }; +- wlan_en_default_mode: wlan_en_default { +- kyle_cfg2 { +- pins = "GPIO215_AH13"; +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- bluetooth { +- bluetooth_default_mode: bluetooth_default { +- kyle_cfg1 { +- pins = "GPIO199_AH23", "GPIO222_AJ9"; +- ste,config = <&gpio_out_lo>; +- }; +- kyle_cfg2 { +- pins = "GPIO97_D9"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- vibrator { +- vibrator_default: vibrator_default { +- kyle_cfg1 { +- pins = "GPIO195_AG28"; /* MOT_EN */ +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- /* Interrupt line for the Melfas MMS134S touchscreen */ +- touchscreen { +- mms134s_kyle_default: mms134s_kyle { +- kyle_cfg1 { +- pins = "GPIO218_AH11"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +-}; +- +-&ab8505_gpio { +- /* Hog a few default settings */ +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_default>; +- +- gpio { +- gpio_default: gpio_default { +- kyle_mux { +- /* Change unused pins to GPIO mode */ +- function = "gpio"; +- groups = "gpio3_a_1", /* default: SysClkReq4 */ +- "gpio14_a_1"; /* default: PWMOut1 */ +- }; +- kyle_cfg1 { +- pins = "GPIO11_B17", "GPIO13_D17", "GPIO50_L4"; +- bias-disable; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/ste-ux500-samsung-skomer.dts b/scripts/dtc/include-prefixes/arm/ste-ux500-samsung-skomer.dts +deleted file mode 100644 +index 7fab746e0570..000000000000 +--- a/scripts/dtc/include-prefixes/arm/ste-ux500-samsung-skomer.dts ++++ /dev/null +@@ -1,657 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Devicetree for the Samsung XCover 2 GT-S7710 also known as Skomer. +- */ +- +-/dts-v1/; +-#include "ste-db8500.dtsi" +-#include "ste-ab8505.dtsi" +-#include "ste-dbx5x0-pinctrl.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "Samsung XCover 2 (GT-S7710)"; +- compatible = "samsung,skomer", "st-ericsson,u8500"; +- +- chosen { +- stdout-path = &serial2; +- }; +- +- /* TI TXS0206 level translator for 2.9 V */ +- sd_level_translator: regulator-gpio { +- compatible = "regulator-fixed"; +- +- /* GPIO87 EN */ +- gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- regulator-name = "sd-level-translator"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- regulator-type = "voltage"; +- +- startup-delay-us = <200>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sd_level_translator_default>; +- }; +- +- /* External LDO MIC5366-3.3YMT for eMMC */ +- ldo_3v3_reg: regulator-gpio-ldo-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "en-3v3-fixed-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <5000>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_ldo_en_default_mode>; +- }; +- +- wlan_en: regulator-gpio-wlan-en { +- compatible = "regulator-fixed"; +- regulator-name = "wl-reg-on"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- startup-delay-us = <200000>; +- /* GPIO215 WLAN_EN */ +- gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_en_default_mode>; +- }; +- +- vibrator { +- compatible = "gpio-vibrator"; +- enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vibrator_default>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_default_mode>; +- +- button-home { +- linux,code = ; +- label = "HOME"; +- /* GPIO91 */ +- gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; +- }; +- button-volup { +- linux,code = ; +- label = "VOL+"; +- /* GPIO67 */ +- gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; +- }; +- button-voldown { +- linux,code = ; +- label = "VOL-"; +- /* GPIO92 */ +- gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; +- }; +- button-menu { +- linux,code = ; +- label = "MENU"; +- /* GPIO204 */ +- gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; +- }; +- button-back { +- linux,code = ; +- label = "BACK"; +- /* GPIO205 */ +- gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- ktd253: backlight { +- compatible = "kinetic,ktd253"; +- /* GPIO 69 */ +- enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; +- /* Default to 13/32 brightness */ +- default-brightness = <13>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_backlight_default_mode>; +- }; +- +- /* Richtek RT8515GQW Flash LED Driver IC */ +- flash { +- compatible = "richtek,rt8515"; +- /* GPIO 140 */ +- enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; +- /* GPIO 141 */ +- ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; +- /* +- * RFS is 16 kOhm and RTS is 100 kOhm giving +- * the flash max current 343mA and torch max +- * current 55 mA. +- */ +- richtek,rfs-ohms = <16000>; +- richtek,rts-ohms = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_flash_default_mode>; +- +- led { +- function = LED_FUNCTION_FLASH; +- color = ; +- flash-max-timeout-us = <250000>; +- flash-max-microamp = <343750>; +- led-max-microamp = <55000>; +- }; +- }; +- +- i2c-gpio-0 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_gpio_0_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- /* TODO: this should be used by the NCP6914 Camera power management unit */ +- }; +- +- i2c-gpio-1 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_gpio_1_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- magnetometer@c { +- compatible = "alps,hscdtd008a"; +- reg = <0x0c>; +- avdd-supply = <&ab8500_ldo_aux1_reg>; +- dvdd-supply = <&ab8500_ldo_aux8_reg>; +- }; +- }; +- +- soc { +- // External Micro SD slot +- mmc@80126000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <100000000>; +- bus-width = <4>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- /* All direction control is used */ +- st,sig-pin-fbclk; +- full-pwr-cycle; +- vmmc-supply = <&ab8500_ldo_aux3_reg>; +- vqmmc-supply = <&sd_level_translator>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc0_a_1_default>; +- pinctrl-1 = <&mc0_a_1_sleep>; +- status = "okay"; +- }; +- +- // WLAN SDIO channel +- mmc@80118000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <50000000>; +- bus-width = <4>; +- non-removable; +- cap-sd-highspeed; +- vmmc-supply = <&wlan_en>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc1_a_2_default>; +- pinctrl-1 = <&mc1_a_2_sleep>; +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- wifi@1 { +- compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; +- reg = <1>; +- /* GPIO216 WL_HOST_WAKE */ +- interrupt-parent = <&gpio6>; +- interrupts = <24 IRQ_TYPE_EDGE_FALLING>; +- interrupt-names = "host-wake"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_default_mode>; +- }; +- }; +- +- // eMMC +- mmc@80005000 { +- arm,primecell-periphid = <0x10480180>; +- max-frequency = <100000000>; +- bus-width = <8>; +- non-removable; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- no-sdio; +- no-sd; +- vmmc-supply = <&ldo_3v3_reg>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mc2_a_1_default>; +- pinctrl-1 = <&mc2_a_1_sleep>; +- +- status = "okay"; +- }; +- +- /* GBF (Bluetooth) UART */ +- uart@80120000 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u0_a_1_default>; +- pinctrl-1 = <&u0_a_1_sleep>; +- status = "okay"; +- +- /* FIXME: not quite working yet, probably needs regulators */ +- bluetooth { +- /* BCM4334B0 actually */ +- compatible = "brcm,bcm4330-bt"; +- shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; +- device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bluetooth_default_mode>; +- }; +- }; +- +- /* GPF UART */ +- uart@80121000 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; +- pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; +- }; +- +- /* Debugging console UART connected to AB8505 USB */ +- uart@80007000 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&u2rxtx_c_1_default>; +- pinctrl-1 = <&u2rxtx_c_1_sleep>; +- }; +- +- prcmu@80157000 { +- ab8505 { +- ab8500_usb { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&usb_a_1_default>; +- pinctrl-1 = <&usb_a_1_sleep>; +- }; +- +- ab8505-regulators { +- ab8500_ldo_aux1 { +- /* Used for VDD for sensors */ +- regulator-name = "AUX1"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ab8500_ldo_aux2 { +- /* Supplies the Cypress TMA140 touchscreen only with 3.0V */ +- regulator-name = "AUX2"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- ab8500_ldo_aux3 { +- /* Used for voltage for external MMC/SD card */ +- regulator-name = "AUX3"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ab8500_ldo_aux4 { +- regulator-name = "AUX4"; +- /* Hammer to 3.0V for the display */ +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- ab8500_ldo_aux5 { +- regulator-name = "AUX5"; +- /* Intended for 1V8 for touchscreen but actually left unused */ +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <2790000>; +- }; +- +- ab8500_ldo_aux6 { +- regulator-name = "AUX6"; +- /* Hammer to 1.8V for the display */ +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ab8500_ldo_aux8 { +- /* Mostly VIO for sensors */ +- regulator-name = "AUX8"; +- }; +- }; +- }; +- }; +- +- /* I2C0 */ +- i2c@80004000 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c0_a_1_default>; +- pinctrl-1 = <&i2c0_a_1_sleep>; +- +- proximity@44 { +- compatible = "sharp,gp2ap002s00f"; +- clock-frequency = <400000>; +- reg = <0x44>; +- +- interrupt-parent = <&gpio4>; +- interrupts = <18 IRQ_TYPE_EDGE_FALLING>; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vio-supply = <&ab8500_ldo_aux8_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gp2ap002_skomer_default>; +- sharp,proximity-far-hysteresis = /bits/ 8 <0x2f>; +- sharp,proximity-close-hysteresis = /bits/ 8 <0x0f>; +- }; +- }; +- +- +- /* I2C2 */ +- i2c@80128000 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c2_b_2_default>; +- pinctrl-1 = <&i2c2_b_2_sleep>; +- +- accel@18 { +- compatible = "bosch,bma254"; +- clock-frequency = <400000>; +- reg = <0x18>; +- +- /* GPIO224 used as "smart alert" interrupt */ +- interrupt-parent = <&gpio7>; +- interrupts = <0 IRQ_TYPE_EDGE_RISING>; +- +- mount-matrix = "0", "-1", "0", +- "1", "0", "0", +- "0", "0", "1"; +- vdd-supply = <&ab8500_ldo_aux1_reg>; +- vddio-supply = <&ab8500_ldo_aux8_reg>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bma254_skomer_default>; +- }; +- }; +- +- /* I2C3 */ +- i2c@80110000 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c3_c_2_default>; +- pinctrl-1 = <&i2c3_c_2_sleep>; +- +- /* Cypress CY8CTMA140 touchscreen */ +- touchscreen@20 { +- compatible = "cypress,cy8ctma140"; +- clock-frequency = <400000>; +- reg = <0x20>; +- +- touchscreen-size-x = <480>; +- touchscreen-size-y = <800>; +- touchscreen-max-pressure = <255>; +- +- /* GPIO218 for IRQ */ +- interrupt-parent = <&gpio6>; +- interrupts = <26 IRQ_TYPE_EDGE_FALLING>; +- +- /* VDD is "digital supply" nominally 1.71-3.6V */ +- vdd-supply = <&ab8500_ldo_aux2_reg>; +- /* VCPIN is "analog supply", 2.7-3.6 V */ +- vcpin-supply = <&ab8500_ldo_aux2_reg>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&tma140_skomer_default>; +- }; +- }; +- +- mcde@a0350000 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dsi_default_mode>; +- +- dsi@a0351000 { +- panel { +- /* NT35510-based Hydis HVA40WV1 */ +- compatible = "hydis,hva40wv1", "novatek,nt35510"; +- reg = <0>; +- /* v_lcd_3v0 2.3-4.8V */ +- vdd-supply = <&ab8500_ldo_aux4_reg>; +- /* v_lcd_1v8 1.65-3.3V */ +- vddi-supply = <&ab8500_ldo_aux6_reg>; +- /* GPIO 139 */ +- reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&display_default_mode>; +- backlight = <&ktd253>; +- }; +- }; +- }; +- }; +-}; +- +-&pinctrl { +- /* +- * This extends the MC0 default config to include DAT32DIR +- * which is used by this machine. If we don't do this the +- * SD card does not work. +- */ +- sdi0 { +- mc0_a_1_default { +- default_mux { +- function = "mc0"; +- /* This machine uses the DAT31 pin */ +- groups = "mc0_a_1", "mc0dat31dir_a_1"; +- }; +- default_cfg5 { +- pins = "GPIO21_AB3"; /* DAT31DIR */ +- ste,config = <&out_hi>; +- }; +- }; +- }; +- +- /* The unused FBCLK needs to be pulled down on this machine */ +- sdi2 { +- mc2_a_1_default { +- default_cfg2 { +- pins = "GPIO130_C8"; /* FBCLK */ +- ste,config = <&in_pd>; +- }; +- }; +- }; +- +- mcde { +- dsi_default_mode: dsi_default { +- default_mux1 { +- /* Mux in VSI0 used for DSI TE */ +- function = "lcd"; +- groups = "lcdvsi0_a_1"; /* VSI0 for LCD */ +- }; +- default_cfg1 { +- pins = "GPIO68_E1"; /* VSI0 */ +- ste,config = <&in_nopull>; +- }; +- }; +- }; +- +- /* Two GPIO lines used by the display */ +- display { +- display_default_mode: display_default { +- skomer_cfg1 { +- /* +- * OLED DETECT or check_pba, this appears to be high +- * on "PBA" which I guess is "prototype board A". +- */ +- pins = "GPIO93_B7"; +- ste,config = <&gpio_in_nopull>; +- }; +- skomer_cfg2 { +- pins = "GPIO139_C9"; +- /* +- * MIPI_DSI0_RESET_N resets the display, leave high +- * (de-asserted) so we only assert reset explicitly +- * from the display driver. +- */ +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- backlight { +- gpio_backlight_default_mode: backlight_default { +- skomer_cfg1 { +- pins = "GPIO69_E2"; /* LCD_BL_CTRL */ +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- flash { +- gpio_flash_default_mode: flash_default { +- skomer_cfg1 { +- pins = "GPIO140_B11", "GPIO141_C12"; +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- /* GPIO that enables the 2.9V SD card level translator */ +- sd-level-translator { +- sd_level_translator_default: sd_level_translator_default { +- /* level shifter on GPIO87 */ +- skomer_cfg1 { +- pins = "GPIO87_B3"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* GPIO that enables the LDO regulator for the eMMC */ +- emmc-ldo { +- emmc_ldo_en_default_mode: emmc_ldo_default { +- /* LDO enable on GPIO223 */ +- skomer_cfg1 { +- pins = "GPIO223_AH9"; +- ste,config = <&gpio_out_hi>; +- }; +- }; +- }; +- /* GPIO keys */ +- gpio-keys { +- gpio_keys_default_mode: gpio_keys_default { +- skomer_cfg1 { +- pins = "GPIO67_G2", /* VOL UP */ +- "GPIO91_B6", /* HOME */ +- "GPIO92_D6", /* VOL DOWN */ +- "GPIO204_AF23", /* MENU */ +- "GPIO205_AG23"; /* BACK */ +- ste,config = <&gpio_in_pu>; +- }; +- }; +- }; +- /* Interrupt line for BMA254 */ +- bma254 { +- bma254_skomer_default: bma254_skomer { +- skomer_cfg1 { +- pins = "GPIO224_AG9"; +- ste,config = <&gpio_in_pd>; +- }; +- }; +- }; +- /* Interrupt line for light/proximity sensor GP2AP002 */ +- gp2ap002 { +- gp2ap002_skomer_default: gp2ap002_skomer { +- skomer_cfg1 { +- pins = "GPIO146_D13"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* GPIO-based I2C bus for NCP6914 */ +- i2c-gpio-0 { +- i2c_gpio_0_default: i2c_gpio_0 { +- skomer_cfg1 { +- pins = "GPIO143_D12", "GPIO144_B13"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- /* GPIO-based I2C bus for ALPS HSCD compass */ +- i2c-gpio-1 { +- i2c_gpio_1_default: i2c_gpio_1 { +- skomer_cfg1 { +- pins = "GPIO151_B17", "GPIO152_D16"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- wlan { +- wlan_default_mode: wlan_default { +- skomer_cfg1 { +- pins = "GPIO216_AG12"; +- ste,config = <&gpio_in_pd>; +- }; +- }; +- wlan_en_default_mode: wlan_en_default { +- skomer_cfg2 { +- pins = "GPIO215_AH13"; +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- bluetooth { +- bluetooth_default_mode: bluetooth_default { +- skomer_cfg1 { +- pins = "GPIO199_AH23", "GPIO222_AJ9"; +- ste,config = <&gpio_out_lo>; +- }; +- skomer_cfg2 { +- pins = "GPIO97_D9"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +- vibrator { +- vibrator_default: vibrator_default { +- skomer_cfg1 { +- pins = "GPIO195_AG28"; /* MOT_EN */ +- ste,config = <&gpio_out_lo>; +- }; +- }; +- }; +- /* Interrupt line for the Cypress TMA140 touchscreen */ +- touchscreen { +- tma140_skomer_default: tma140_skomer { +- skomer_cfg1 { +- pins = "GPIO218_AH11"; +- ste,config = <&gpio_in_nopull>; +- }; +- }; +- }; +-}; +- +-&ab8505_gpio { +- /* Hog a few default settings */ +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_default>; +- +- gpio { +- gpio_default: gpio_default { +- skomer_mux { +- /* Change unused pins to GPIO mode */ +- function = "gpio"; +- groups = "gpio3_a_1", /* default: SysClkReq4 */ +- "gpio14_a_1"; /* default: PWMOut1 */ +- }; +- skomer_cfg1 { +- pins = "GPIO11_B17", "GPIO13_D17", "GPIO50_L4"; +- bias-disable; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stih407-b2120.dts b/scripts/dtc/include-prefixes/arm/stih407-b2120.dts +deleted file mode 100644 +index 9c79982ee7ba..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stih407-b2120.dts ++++ /dev/null +@@ -1,27 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 STMicroelectronics (R&D) Limited. +- * Author: Giuseppe Cavallaro +- */ +-/dts-v1/; +-#include "stih407.dtsi" +-#include "stihxxx-b2120.dtsi" +-/ { +- model = "STiH407 B2120"; +- compatible = "st,stih407-b2120", "st,stih407"; +- +- chosen { +- stdout-path = &sbc_serial0; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x80000000>; +- }; +- +- aliases { +- serial0 = &sbc_serial0; +- ethernet0 = ðernet0; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stih407-clock.dtsi b/scripts/dtc/include-prefixes/arm/stih407-clock.dtsi +deleted file mode 100644 +index 9cce9541e26b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stih407-clock.dtsi ++++ /dev/null +@@ -1,219 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 STMicroelectronics R&D Limited +- */ +-#include +-/ { +- /* +- * Fixed 30MHz oscillator inputs to SoC +- */ +- clk_sysin: clk-sysin { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <30000000>; +- }; +- +- clk_tmdsout_hdmi: clk-tmdsout-hdmi { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* +- * A9 PLL. +- */ +- clockgen-a9@92b0000 { +- compatible = "st,clkgen-c32"; +- reg = <0x92b0000 0xffff>; +- +- clockgen_a9_pll: clockgen-a9-pll { +- #clock-cells = <1>; +- compatible = "st,stih407-clkgen-plla9"; +- +- clocks = <&clk_sysin>; +- }; +- }; +- +- /* +- * ARM CPU related clocks. +- */ +- clk_m_a9: clk-m-a9@92b0000 { +- #clock-cells = <0>; +- compatible = "st,stih407-clkgen-a9-mux"; +- reg = <0x92b0000 0x10000>; +- +- clocks = <&clockgen_a9_pll 0>, +- <&clockgen_a9_pll 0>, +- <&clk_s_c0_flexgen 13>, +- <&clk_m_a9_ext2f_div2>; +- +- +- /* +- * ARM Peripheral clock for timers +- */ +- arm_periph_clk: clk-m-a9-periphs { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- +- clocks = <&clk_m_a9>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- }; +- +- clockgen-a@90ff000 { +- compatible = "st,clkgen-c32"; +- reg = <0x90ff000 0x1000>; +- +- clk_s_a0_pll: clk-s-a0-pll { +- #clock-cells = <1>; +- compatible = "st,clkgen-pll0-a0"; +- +- clocks = <&clk_sysin>; +- }; +- +- clk_s_a0_flexgen: clk-s-a0-flexgen { +- compatible = "st,flexgen", "st,flexgen-stih407-a0"; +- +- #clock-cells = <1>; +- +- clocks = <&clk_s_a0_pll 0>, +- <&clk_sysin>; +- }; +- }; +- +- clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { +- #clock-cells = <1>; +- compatible = "st,quadfs-pll"; +- reg = <0x9103000 0x1000>; +- +- clocks = <&clk_sysin>; +- }; +- +- clk_s_c0: clockgen-c@9103000 { +- compatible = "st,clkgen-c32"; +- reg = <0x9103000 0x1000>; +- +- clk_s_c0_pll0: clk-s-c0-pll0 { +- #clock-cells = <1>; +- compatible = "st,clkgen-pll0-c0"; +- +- clocks = <&clk_sysin>; +- }; +- +- clk_s_c0_pll1: clk-s-c0-pll1 { +- #clock-cells = <1>; +- compatible = "st,clkgen-pll1-c0"; +- +- clocks = <&clk_sysin>; +- }; +- +- clk_s_c0_flexgen: clk-s-c0-flexgen { +- #clock-cells = <1>; +- compatible = "st,flexgen", "st,flexgen-stih407-c0"; +- +- clocks = <&clk_s_c0_pll0 0>, +- <&clk_s_c0_pll1 0>, +- <&clk_s_c0_quadfs 0>, +- <&clk_s_c0_quadfs 1>, +- <&clk_s_c0_quadfs 2>, +- <&clk_s_c0_quadfs 3>, +- <&clk_sysin>; +- +- /* +- * ARM Peripheral clock for timers +- */ +- clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- +- clocks = <&clk_s_c0_flexgen 13>; +- +- clock-output-names = "clk-m-a9-ext2f-div2"; +- +- clock-div = <2>; +- clock-mult = <1>; +- }; +- }; +- }; +- +- clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { +- #clock-cells = <1>; +- compatible = "st,quadfs-d0"; +- reg = <0x9104000 0x1000>; +- +- clocks = <&clk_sysin>; +- }; +- +- clockgen-d0@9104000 { +- compatible = "st,clkgen-c32"; +- reg = <0x9104000 0x1000>; +- +- clk_s_d0_flexgen: clk-s-d0-flexgen { +- #clock-cells = <1>; +- compatible = "st,flexgen", "st,flexgen-stih407-d0"; +- +- clocks = <&clk_s_d0_quadfs 0>, +- <&clk_s_d0_quadfs 1>, +- <&clk_s_d0_quadfs 2>, +- <&clk_s_d0_quadfs 3>, +- <&clk_sysin>; +- }; +- }; +- +- clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { +- #clock-cells = <1>; +- compatible = "st,quadfs-d2"; +- reg = <0x9106000 0x1000>; +- +- clocks = <&clk_sysin>; +- }; +- +- clockgen-d2@9106000 { +- compatible = "st,clkgen-c32"; +- reg = <0x9106000 0x1000>; +- +- clk_s_d2_flexgen: clk-s-d2-flexgen { +- #clock-cells = <1>; +- compatible = "st,flexgen", "st,flexgen-stih407-d2"; +- +- clocks = <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 1>, +- <&clk_s_d2_quadfs 2>, +- <&clk_s_d2_quadfs 3>, +- <&clk_sysin>, +- <&clk_sysin>, +- <&clk_tmdsout_hdmi>; +- }; +- }; +- +- clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { +- #clock-cells = <1>; +- compatible = "st,quadfs-d3"; +- reg = <0x9107000 0x1000>; +- +- clocks = <&clk_sysin>; +- }; +- +- clockgen-d3@9107000 { +- compatible = "st,clkgen-c32"; +- reg = <0x9107000 0x1000>; +- +- clk_s_d3_flexgen: clk-s-d3-flexgen { +- #clock-cells = <1>; +- compatible = "st,flexgen", "st,flexgen-stih407-d3"; +- +- clocks = <&clk_s_d3_quadfs 0>, +- <&clk_s_d3_quadfs 1>, +- <&clk_s_d3_quadfs 2>, +- <&clk_s_d3_quadfs 3>, +- <&clk_sysin>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stih407-family.dtsi b/scripts/dtc/include-prefixes/arm/stih407-family.dtsi +deleted file mode 100644 +index 21f3347a91d6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stih407-family.dtsi ++++ /dev/null +@@ -1,1001 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 STMicroelectronics Limited. +- * Author: Giuseppe Cavallaro +- */ +-#include "stih407-pinctrl.dtsi" +-#include +-#include +-#include +-#include +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gp0_reserved: rproc@45000000 { +- compatible = "shared-dma-pool"; +- reg = <0x45000000 0x00400000>; +- no-map; +- }; +- +- delta_reserved: rproc@44000000 { +- compatible = "shared-dma-pool"; +- reg = <0x44000000 0x01000000>; +- no-map; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- +- /* u-boot puts hpen in SBC dmem at 0xa4 offset */ +- cpu-release-addr = <0x94100A4>; +- +- /* kHz uV */ +- operating-points = <1500000 0 +- 1200000 0 +- 800000 0 +- 500000 0>; +- +- clocks = <&clk_m_a9>; +- clock-names = "cpu"; +- clock-latency = <100000>; +- cpu0-supply = <&pwm_regulator>; +- st,syscfg = <&syscfg_core 0x8e0>; +- }; +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <1>; +- +- /* u-boot puts hpen in SBC dmem at 0xa4 offset */ +- cpu-release-addr = <0x94100A4>; +- +- /* kHz uV */ +- operating-points = <1500000 0 +- 1200000 0 +- 800000 0 +- 500000 0>; +- }; +- }; +- +- intc: interrupt-controller@8761000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x08761000 0x1000>, <0x08760100 0x100>; +- }; +- +- scu@8760000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0x08760000 0x1000>; +- }; +- +- timer@8760200 { +- interrupt-parent = <&intc>; +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0x08760200 0x100>; +- interrupts = ; +- clocks = <&arm_periph_clk>; +- }; +- +- l2: cache-controller@8762000 { +- compatible = "arm,pl310-cache"; +- reg = <0x08762000 0x1000>; +- arm,data-latency = <3 3 3>; +- arm,tag-latency = <2 2 2>; +- cache-unified; +- cache-level = <2>; +- }; +- +- arm-pmu { +- interrupt-parent = <&intc>; +- compatible = "arm,cortex-a9-pmu"; +- interrupts = ; +- }; +- +- pwm_regulator: pwm-regulator { +- compatible = "pwm-regulator"; +- pwms = <&pwm1 3 8448>; +- regulator-name = "CPU_1V0_AVS"; +- regulator-min-microvolt = <784000>; +- regulator-max-microvolt = <1299000>; +- regulator-always-on; +- max-duty-cycle = <255>; +- status = "okay"; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&intc>; +- ranges; +- compatible = "simple-bus"; +- +- restart: restart-controller@0 { +- compatible = "st,stih407-restart"; +- reg = <0 0>; +- st,syscfg = <&syscfg_sbc_reg>; +- status = "okay"; +- }; +- +- powerdown: powerdown-controller@0 { +- compatible = "st,stih407-powerdown"; +- reg = <0 0>; +- #reset-cells = <1>; +- }; +- +- softreset: softreset-controller@0 { +- compatible = "st,stih407-softreset"; +- reg = <0 0>; +- #reset-cells = <1>; +- }; +- +- picophyreset: picophyreset-controller@0 { +- compatible = "st,stih407-picophyreset"; +- reg = <0 0>; +- #reset-cells = <1>; +- }; +- +- syscfg_sbc: sbc-syscfg@9620000 { +- compatible = "st,stih407-sbc-syscfg", "syscon"; +- reg = <0x9620000 0x1000>; +- }; +- +- syscfg_front: front-syscfg@9280000 { +- compatible = "st,stih407-front-syscfg", "syscon"; +- reg = <0x9280000 0x1000>; +- }; +- +- syscfg_rear: rear-syscfg@9290000 { +- compatible = "st,stih407-rear-syscfg", "syscon"; +- reg = <0x9290000 0x1000>; +- }; +- +- syscfg_flash: flash-syscfg@92a0000 { +- compatible = "st,stih407-flash-syscfg", "syscon"; +- reg = <0x92a0000 0x1000>; +- }; +- +- syscfg_sbc_reg: fvdp-lite-syscfg@9600000 { +- compatible = "st,stih407-sbc-reg-syscfg", "syscon"; +- reg = <0x9600000 0x1000>; +- }; +- +- syscfg_core: core-syscfg@92b0000 { +- compatible = "st,stih407-core-syscfg", "syscon"; +- reg = <0x92b0000 0x1000>; +- +- sti_sasg_codec: sti-sasg-codec { +- compatible = "st,stih407-sas-codec"; +- #sound-dai-cells = <1>; +- status = "disabled"; +- st,syscfg = <&syscfg_core>; +- }; +- }; +- +- syscfg_lpm: lpm-syscfg@94b5100 { +- compatible = "st,stih407-lpm-syscfg", "syscon"; +- reg = <0x94b5100 0x1000>; +- }; +- +- irq-syscfg@0 { +- compatible = "st,stih407-irq-syscfg"; +- reg = <0 0>; +- st,syscfg = <&syscfg_core>; +- st,irq-device = , +- ; +- st,fiq-device = , +- ; +- }; +- +- /* Display */ +- vtg_main: sti-vtg-main@8d02800 { +- compatible = "st,vtg"; +- reg = <0x8d02800 0x200>; +- interrupts = ; +- }; +- +- vtg_aux: sti-vtg-aux@8d00200 { +- compatible = "st,vtg"; +- reg = <0x8d00200 0x100>; +- interrupts = ; +- }; +- +- serial@9830000 { +- compatible = "st,asc"; +- reg = <0x9830000 0x2c>; +- interrupts = ; +- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; +- /* Pinctrl moved out to a per-board configuration */ +- +- status = "disabled"; +- }; +- +- serial@9831000 { +- compatible = "st,asc"; +- reg = <0x9831000 0x2c>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_serial1>; +- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; +- +- status = "disabled"; +- }; +- +- serial@9832000 { +- compatible = "st,asc"; +- reg = <0x9832000 0x2c>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_serial2>; +- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; +- +- status = "disabled"; +- }; +- +- /* SBC_ASC0 - UART10 */ +- sbc_serial0: serial@9530000 { +- compatible = "st,asc"; +- reg = <0x9530000 0x2c>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sbc_serial0>; +- clocks = <&clk_sysin>; +- +- status = "disabled"; +- }; +- +- serial@9531000 { +- compatible = "st,asc"; +- reg = <0x9531000 0x2c>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sbc_serial1>; +- clocks = <&clk_sysin>; +- +- status = "disabled"; +- }; +- +- i2c@9840000 { +- compatible = "st,comms-ssc4-i2c"; +- interrupts = ; +- reg = <0x9840000 0x110>; +- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; +- clock-names = "ssc"; +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- +- i2c@9841000 { +- compatible = "st,comms-ssc4-i2c"; +- reg = <0x9841000 0x110>; +- interrupts = ; +- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; +- clock-names = "ssc"; +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- +- i2c@9842000 { +- compatible = "st,comms-ssc4-i2c"; +- reg = <0x9842000 0x110>; +- interrupts = ; +- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; +- clock-names = "ssc"; +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- +- i2c@9843000 { +- compatible = "st,comms-ssc4-i2c"; +- reg = <0x9843000 0x110>; +- interrupts = ; +- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; +- clock-names = "ssc"; +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- +- i2c@9844000 { +- compatible = "st,comms-ssc4-i2c"; +- reg = <0x9844000 0x110>; +- interrupts = ; +- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; +- clock-names = "ssc"; +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- +- i2c@9845000 { +- compatible = "st,comms-ssc4-i2c"; +- reg = <0x9845000 0x110>; +- interrupts = ; +- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; +- clock-names = "ssc"; +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c5_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- +- +- /* SSCs on SBC */ +- i2c@9540000 { +- compatible = "st,comms-ssc4-i2c"; +- reg = <0x9540000 0x110>; +- interrupts = ; +- clocks = <&clk_sysin>; +- clock-names = "ssc"; +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c10_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- +- i2c@9541000 { +- compatible = "st,comms-ssc4-i2c"; +- reg = <0x9541000 0x110>; +- interrupts = ; +- clocks = <&clk_sysin>; +- clock-names = "ssc"; +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c11_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- +- usb2_picophy0: phy1@0 { +- compatible = "st,stih407-usb2-phy"; +- reg = <0 0>; +- #phy-cells = <0>; +- st,syscfg = <&syscfg_core 0x100 0xf4>; +- resets = <&softreset STIH407_PICOPHY_SOFTRESET>, +- <&picophyreset STIH407_PICOPHY2_RESET>; +- reset-names = "global", "port"; +- }; +- +- miphy28lp_phy: miphy28lp@0 { +- compatible = "st,miphy28lp-phy"; +- st,syscfg = <&syscfg_core>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- reg = <0 0>; +- +- phy_port0: port@9b22000 { +- reg = <0x9b22000 0xff>, +- <0x9b09000 0xff>, +- <0x9b04000 0xff>; +- reg-names = "sata-up", +- "pcie-up", +- "pipew"; +- +- st,syscfg = <0x114 0x818 0xe0 0xec>; +- #phy-cells = <1>; +- +- reset-names = "miphy-sw-rst"; +- resets = <&softreset STIH407_MIPHY0_SOFTRESET>; +- }; +- +- phy_port1: port@9b2a000 { +- reg = <0x9b2a000 0xff>, +- <0x9b19000 0xff>, +- <0x9b14000 0xff>; +- reg-names = "sata-up", +- "pcie-up", +- "pipew"; +- +- st,syscfg = <0x118 0x81c 0xe4 0xf0>; +- +- #phy-cells = <1>; +- +- reset-names = "miphy-sw-rst"; +- resets = <&softreset STIH407_MIPHY1_SOFTRESET>; +- }; +- +- phy_port2: port@8f95000 { +- reg = <0x8f95000 0xff>, +- <0x8f90000 0xff>; +- reg-names = "pipew", +- "usb3-up"; +- +- st,syscfg = <0x11c 0x820>; +- +- #phy-cells = <1>; +- +- reset-names = "miphy-sw-rst"; +- resets = <&softreset STIH407_MIPHY2_SOFTRESET>; +- }; +- }; +- +- spi@9840000 { +- compatible = "st,comms-ssc4-spi"; +- reg = <0x9840000 0x110>; +- interrupts = ; +- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; +- clock-names = "ssc"; +- pinctrl-0 = <&pinctrl_spi0_default>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- +- spi@9841000 { +- compatible = "st,comms-ssc4-spi"; +- reg = <0x9841000 0x110>; +- interrupts = ; +- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; +- clock-names = "ssc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- +- spi@9842000 { +- compatible = "st,comms-ssc4-spi"; +- reg = <0x9842000 0x110>; +- interrupts = ; +- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; +- clock-names = "ssc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi2_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- +- spi@9843000 { +- compatible = "st,comms-ssc4-spi"; +- reg = <0x9843000 0x110>; +- interrupts = ; +- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; +- clock-names = "ssc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi3_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- +- spi@9844000 { +- compatible = "st,comms-ssc4-spi"; +- reg = <0x9844000 0x110>; +- interrupts = ; +- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; +- clock-names = "ssc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi4_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- +- /* SBC SSC */ +- spi@9540000 { +- compatible = "st,comms-ssc4-spi"; +- reg = <0x9540000 0x110>; +- interrupts = ; +- clocks = <&clk_sysin>; +- clock-names = "ssc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi10_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- +- spi@9541000 { +- compatible = "st,comms-ssc4-spi"; +- reg = <0x9541000 0x110>; +- interrupts = ; +- clocks = <&clk_sysin>; +- clock-names = "ssc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi11_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- +- spi@9542000 { +- compatible = "st,comms-ssc4-spi"; +- reg = <0x9542000 0x110>; +- interrupts = ; +- clocks = <&clk_sysin>; +- clock-names = "ssc"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi12_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- +- mmc0: sdhci@9060000 { +- compatible = "st,sdhci-stih407", "st,sdhci"; +- status = "disabled"; +- reg = <0x09060000 0x7ff>, <0x9061008 0x20>; +- reg-names = "mmc", "top-mmc-delay"; +- interrupts = ; +- interrupt-names = "mmcirq"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mmc0>; +- clock-names = "mmc", "icn"; +- clocks = <&clk_s_c0_flexgen CLK_MMC_0>, +- <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; +- bus-width = <8>; +- }; +- +- mmc1: sdhci@9080000 { +- compatible = "st,sdhci-stih407", "st,sdhci"; +- status = "disabled"; +- reg = <0x09080000 0x7ff>; +- reg-names = "mmc"; +- interrupts = ; +- interrupt-names = "mmcirq"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sd1>; +- clock-names = "mmc", "icn"; +- clocks = <&clk_s_c0_flexgen CLK_MMC_1>, +- <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; +- resets = <&softreset STIH407_MMC1_SOFTRESET>; +- bus-width = <4>; +- }; +- +- /* Watchdog and Real-Time Clock */ +- lpc@8787000 { +- compatible = "st,stih407-lpc"; +- reg = <0x8787000 0x1000>; +- interrupts = ; +- clocks = <&clk_s_d3_flexgen CLK_LPC_0>; +- timeout-sec = <120>; +- st,syscfg = <&syscfg_core>; +- st,lpc-mode = ; +- }; +- +- lpc@8788000 { +- compatible = "st,stih407-lpc"; +- reg = <0x8788000 0x1000>; +- interrupts = ; +- clocks = <&clk_s_d3_flexgen CLK_LPC_1>; +- st,lpc-mode = ; +- }; +- +- spifsm: spifsm@9022000{ +- compatible = "st,spi-fsm"; +- reg = <0x9022000 0x1000>; +- reg-names = "spi-fsm"; +- clocks = <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; +- clock-names = "emi_clk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fsm>; +- st,syscfg = <&syscfg_core>; +- st,boot-device-reg = <0x8c4>; +- st,boot-device-spi = <0x68>; +- +- status = "disabled"; +- }; +- +- sata0: sata@9b20000 { +- compatible = "st,ahci"; +- reg = <0x9b20000 0x1000>; +- +- interrupts = ; +- interrupt-names = "hostc"; +- +- phys = <&phy_port0 PHY_TYPE_SATA>; +- phy-names = "ahci_phy"; +- +- resets = <&powerdown STIH407_SATA0_POWERDOWN>, +- <&softreset STIH407_SATA0_SOFTRESET>, +- <&softreset STIH407_SATA0_PWR_SOFTRESET>; +- reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; +- +- clock-names = "ahci_clk"; +- clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; +- +- ports-implemented = <0x1>; +- +- status = "disabled"; +- }; +- +- sata1: sata@9b28000 { +- compatible = "st,ahci"; +- reg = <0x9b28000 0x1000>; +- +- interrupts = ; +- interrupt-names = "hostc"; +- +- phys = <&phy_port1 PHY_TYPE_SATA>; +- phy-names = "ahci_phy"; +- +- resets = <&powerdown STIH407_SATA1_POWERDOWN>, +- <&softreset STIH407_SATA1_SOFTRESET>, +- <&softreset STIH407_SATA1_PWR_SOFTRESET>; +- reset-names = "pwr-dwn", +- "sw-rst", +- "pwr-rst"; +- +- clock-names = "ahci_clk"; +- clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; +- +- ports-implemented = <0x1>; +- +- status = "disabled"; +- }; +- +- +- st_dwc3: dwc3@8f94000 { +- compatible = "st,stih407-dwc3"; +- reg = <0x08f94000 0x1000>, <0x110 0x4>; +- reg-names = "reg-glue", "syscfg-reg"; +- st,syscfg = <&syscfg_core>; +- resets = <&powerdown STIH407_USB3_POWERDOWN>, +- <&softreset STIH407_MIPHY2_SOFTRESET>; +- reset-names = "powerdown", "softreset"; +- #address-cells = <1>; +- #size-cells = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb3>; +- ranges; +- +- status = "disabled"; +- +- dwc3: dwc3@9900000 { +- compatible = "snps,dwc3"; +- reg = <0x09900000 0x100000>; +- interrupts = ; +- dr_mode = "host"; +- phy-names = "usb2-phy", "usb3-phy"; +- phys = <&usb2_picophy0>, +- <&phy_port2 PHY_TYPE_USB3>; +- snps,dis_u3_susphy_quirk; +- }; +- }; +- +- /* COMMS PWM Module */ +- pwm0: pwm@9810000 { +- compatible = "st,sti-pwm"; +- #pwm-cells = <2>; +- reg = <0x9810000 0x68>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0_chan0_default>; +- clock-names = "pwm"; +- clocks = <&clk_sysin>; +- st,pwm-num-chan = <1>; +- +- status = "disabled"; +- }; +- +- /* SBC PWM Module */ +- pwm1: pwm@9510000 { +- compatible = "st,sti-pwm"; +- #pwm-cells = <2>; +- reg = <0x9510000 0x68>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1_chan0_default +- &pinctrl_pwm1_chan1_default +- &pinctrl_pwm1_chan2_default +- &pinctrl_pwm1_chan3_default>; +- clock-names = "pwm"; +- clocks = <&clk_sysin>; +- st,pwm-num-chan = <4>; +- +- status = "disabled"; +- }; +- +- rng10: rng@8a89000 { +- compatible = "st,rng"; +- reg = <0x08a89000 0x1000>; +- clocks = <&clk_sysin>; +- status = "okay"; +- }; +- +- rng11: rng@8a8a000 { +- compatible = "st,rng"; +- reg = <0x08a8a000 0x1000>; +- clocks = <&clk_sysin>; +- status = "okay"; +- }; +- +- ethernet0: dwmac@9630000 { +- device_type = "network"; +- status = "disabled"; +- compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; +- reg = <0x9630000 0x8000>, <0x80 0x4>; +- reg-names = "stmmaceth", "sti-ethconf"; +- +- st,syscon = <&syscfg_sbc_reg 0x80>; +- st,gmac_en; +- resets = <&softreset STIH407_ETH1_SOFTRESET>; +- reset-names = "stmmaceth"; +- +- interrupts = , +- ; +- interrupt-names = "macirq", "eth_wake_irq"; +- +- /* DMA Bus Mode */ +- snps,pbl = <8>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rgmii1>; +- +- clock-names = "stmmaceth", "sti-ethclk"; +- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>, +- <&clk_s_c0_flexgen CLK_ETH_PHY>; +- }; +- +- mailbox0: mailbox@8f00000 { +- compatible = "st,stih407-mailbox"; +- reg = <0x8f00000 0x1000>; +- interrupts = ; +- #mbox-cells = <2>; +- mbox-name = "a9"; +- status = "okay"; +- }; +- +- mailbox1: mailbox@8f01000 { +- compatible = "st,stih407-mailbox"; +- reg = <0x8f01000 0x1000>; +- #mbox-cells = <2>; +- mbox-name = "st231_gp_1"; +- status = "okay"; +- }; +- +- mailbox2: mailbox@8f02000 { +- compatible = "st,stih407-mailbox"; +- reg = <0x8f02000 0x1000>; +- #mbox-cells = <2>; +- mbox-name = "st231_gp_0"; +- status = "okay"; +- }; +- +- mailbox3: mailbox@8f03000 { +- compatible = "st,stih407-mailbox"; +- reg = <0x8f03000 0x1000>; +- #mbox-cells = <2>; +- mbox-name = "st231_audio_video"; +- status = "okay"; +- }; +- +- st231_gp0: st231-gp0@0 { +- compatible = "st,st231-rproc"; +- reg = <0 0>; +- memory-region = <&gp0_reserved>; +- resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; +- reset-names = "sw_reset"; +- clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; +- clock-frequency = <600000000>; +- st,syscfg = <&syscfg_core 0x22c>; +- #mbox-cells = <1>; +- mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; +- mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>; +- }; +- +- st231_delta: st231-delta@0 { +- compatible = "st,st231-rproc"; +- reg = <0 0>; +- memory-region = <&delta_reserved>; +- resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; +- reset-names = "sw_reset"; +- clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; +- clock-frequency = <600000000>; +- st,syscfg = <&syscfg_core 0x224>; +- #mbox-cells = <1>; +- mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; +- mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>; +- }; +- +- /* fdma audio */ +- fdma0: dma-controller@8e20000 { +- compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc"; +- reg = <0x8e20000 0x8000>, +- <0x8e30000 0x3000>, +- <0x8e37000 0x1000>, +- <0x8e38000 0x8000>; +- reg-names = "slimcore", "dmem", "peripherals", "imem"; +- clocks = <&clk_s_c0_flexgen CLK_FDMA>, +- <&clk_s_c0_flexgen CLK_EXT2F_A9>, +- <&clk_s_c0_flexgen CLK_EXT2F_A9>, +- <&clk_s_c0_flexgen CLK_EXT2F_A9>; +- interrupts = ; +- dma-channels = <16>; +- #dma-cells = <3>; +- }; +- +- /* fdma app */ +- fdma1: dma-controller@8e40000 { +- compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc"; +- reg = <0x8e40000 0x8000>, +- <0x8e50000 0x3000>, +- <0x8e57000 0x1000>, +- <0x8e58000 0x8000>; +- reg-names = "slimcore", "dmem", "peripherals", "imem"; +- clocks = <&clk_s_c0_flexgen CLK_FDMA>, +- <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, +- <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, +- <&clk_s_c0_flexgen CLK_EXT2F_A9>; +- +- interrupts = ; +- dma-channels = <16>; +- #dma-cells = <3>; +- +- status = "disabled"; +- }; +- +- /* fdma free running */ +- fdma2: dma-controller@8e60000 { +- compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc"; +- reg = <0x8e60000 0x8000>, +- <0x8e70000 0x3000>, +- <0x8e77000 0x1000>, +- <0x8e78000 0x8000>; +- reg-names = "slimcore", "dmem", "peripherals", "imem"; +- interrupts = ; +- dma-channels = <16>; +- #dma-cells = <3>; +- clocks = <&clk_s_c0_flexgen CLK_FDMA>, +- <&clk_s_c0_flexgen CLK_EXT2F_A9>, +- <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, +- <&clk_s_c0_flexgen CLK_EXT2F_A9>; +- +- status = "disabled"; +- }; +- +- sti_uni_player0: sti-uni-player@8d80000 { +- compatible = "st,stih407-uni-player-hdmi"; +- #sound-dai-cells = <0>; +- st,syscfg = <&syscfg_core>; +- clocks = <&clk_s_d0_flexgen CLK_PCM_0>; +- assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>; +- assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>; +- assigned-clock-rates = <50000000>; +- reg = <0x8d80000 0x158>; +- interrupts = ; +- dmas = <&fdma0 2 0 1>; +- dma-names = "tx"; +- +- status = "disabled"; +- }; +- +- sti_uni_player1: sti-uni-player@8d81000 { +- compatible = "st,stih407-uni-player-pcm-out"; +- #sound-dai-cells = <0>; +- st,syscfg = <&syscfg_core>; +- clocks = <&clk_s_d0_flexgen CLK_PCM_1>; +- assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>; +- assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>; +- assigned-clock-rates = <50000000>; +- reg = <0x8d81000 0x158>; +- interrupts = ; +- dmas = <&fdma0 3 0 1>; +- dma-names = "tx"; +- +- status = "disabled"; +- }; +- +- sti_uni_player2: sti-uni-player@8d82000 { +- compatible = "st,stih407-uni-player-dac"; +- #sound-dai-cells = <0>; +- st,syscfg = <&syscfg_core>; +- clocks = <&clk_s_d0_flexgen CLK_PCM_2>; +- assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>; +- assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>; +- assigned-clock-rates = <50000000>; +- reg = <0x8d82000 0x158>; +- interrupts = ; +- dmas = <&fdma0 4 0 1>; +- dma-names = "tx"; +- +- status = "disabled"; +- }; +- +- sti_uni_player3: sti-uni-player@8d85000 { +- compatible = "st,stih407-uni-player-spdif"; +- #sound-dai-cells = <0>; +- st,syscfg = <&syscfg_core>; +- clocks = <&clk_s_d0_flexgen CLK_SPDIFF>; +- assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>; +- assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>; +- assigned-clock-rates = <50000000>; +- reg = <0x8d85000 0x158>; +- interrupts = ; +- dmas = <&fdma0 7 0 1>; +- dma-names = "tx"; +- +- status = "disabled"; +- }; +- +- sti_uni_reader0: sti-uni-reader@8d83000 { +- compatible = "st,stih407-uni-reader-pcm_in"; +- #sound-dai-cells = <0>; +- st,syscfg = <&syscfg_core>; +- reg = <0x8d83000 0x158>; +- interrupts = ; +- dmas = <&fdma0 5 0 1>; +- dma-names = "rx"; +- +- status = "disabled"; +- }; +- +- sti_uni_reader1: sti-uni-reader@8d84000 { +- compatible = "st,stih407-uni-reader-hdmi"; +- #sound-dai-cells = <0>; +- st,syscfg = <&syscfg_core>; +- reg = <0x8d84000 0x158>; +- interrupts = ; +- dmas = <&fdma0 6 0 1>; +- dma-names = "rx"; +- +- status = "disabled"; +- }; +- +- delta0@0 { +- compatible = "st,st-delta"; +- reg = <0 0>; +- clock-names = "delta", +- "delta-st231", +- "delta-flash-promip"; +- clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, +- <&clk_s_c0_flexgen CLK_ST231_DMU>, +- <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stih407-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/stih407-pinctrl.dtsi +deleted file mode 100644 +index 2cf335714ca2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stih407-pinctrl.dtsi ++++ /dev/null +@@ -1,1262 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 STMicroelectronics Limited. +- * Author: Giuseppe Cavallaro +- */ +-#include "st-pincfg.h" +-#include +-/ { +- +- aliases { +- /* 0-5: PIO_SBC */ +- gpio0 = &pio0; +- gpio1 = &pio1; +- gpio2 = &pio2; +- gpio3 = &pio3; +- gpio4 = &pio4; +- gpio5 = &pio5; +- /* 10-19: PIO_FRONT0 */ +- gpio6 = &pio10; +- gpio7 = &pio11; +- gpio8 = &pio12; +- gpio9 = &pio13; +- gpio10 = &pio14; +- gpio11 = &pio15; +- gpio12 = &pio16; +- gpio13 = &pio17; +- gpio14 = &pio18; +- gpio15 = &pio19; +- /* 20: PIO_FRONT1 */ +- gpio16 = &pio20; +- /* 30-35: PIO_REAR */ +- gpio17 = &pio30; +- gpio18 = &pio31; +- gpio19 = &pio32; +- gpio20 = &pio33; +- gpio21 = &pio34; +- gpio22 = &pio35; +- /* 40-42: PIO_FLASH */ +- gpio23 = &pio40; +- gpio24 = &pio41; +- gpio25 = &pio42; +- }; +- +- soc { +- pin-controller-sbc@961f080 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,stih407-sbc-pinctrl"; +- st,syscfg = <&syscfg_sbc>; +- reg = <0x0961f080 0x4>; +- reg-names = "irqmux"; +- interrupts = ; +- interrupt-names = "irqmux"; +- ranges = <0 0x09610000 0x6000>; +- +- pio0: gpio@9610000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x0 0x100>; +- st,bank-name = "PIO0"; +- }; +- pio1: gpio@9611000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x1000 0x100>; +- st,bank-name = "PIO1"; +- }; +- pio2: gpio@9612000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x2000 0x100>; +- st,bank-name = "PIO2"; +- }; +- pio3: gpio@9613000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x3000 0x100>; +- st,bank-name = "PIO3"; +- }; +- pio4: gpio@9614000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x4000 0x100>; +- st,bank-name = "PIO4"; +- }; +- +- pio5: gpio@9615000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x5000 0x100>; +- st,bank-name = "PIO5"; +- st,retime-pin-mask = <0x3f>; +- }; +- +- cec0 { +- pinctrl_cec0_default: cec0-default { +- st,pins { +- hdmi_cec = <&pio2 4 ALT1 BIDIR>; +- }; +- }; +- }; +- +- rc { +- pinctrl_ir: ir0 { +- st,pins { +- ir = <&pio4 0 ALT2 IN>; +- }; +- }; +- +- pinctrl_uhf: uhf0 { +- st,pins { +- ir = <&pio4 1 ALT2 IN>; +- }; +- }; +- +- pinctrl_tx: tx0 { +- st,pins { +- tx = <&pio4 2 ALT2 OUT>; +- }; +- }; +- +- pinctrl_tx_od: tx_od0 { +- st,pins { +- tx_od = <&pio4 3 ALT2 OUT>; +- }; +- }; +- }; +- +- /* SBC_ASC0 - UART10 */ +- sbc_serial0 { +- pinctrl_sbc_serial0: sbc_serial0-0 { +- st,pins { +- tx = <&pio3 4 ALT1 OUT>; +- rx = <&pio3 5 ALT1 IN>; +- }; +- }; +- }; +- /* SBC_ASC1 - UART11 */ +- sbc_serial1 { +- pinctrl_sbc_serial1: sbc_serial1-0 { +- st,pins { +- tx = <&pio2 6 ALT3 OUT>; +- rx = <&pio2 7 ALT3 IN>; +- }; +- }; +- }; +- +- i2c10 { +- pinctrl_i2c10_default: i2c10-default { +- st,pins { +- sda = <&pio4 6 ALT1 BIDIR>; +- scl = <&pio4 5 ALT1 BIDIR>; +- }; +- }; +- }; +- +- i2c11 { +- pinctrl_i2c11_default: i2c11-default { +- st,pins { +- sda = <&pio5 1 ALT1 BIDIR>; +- scl = <&pio5 0 ALT1 BIDIR>; +- }; +- }; +- }; +- +- keyscan { +- pinctrl_keyscan: keyscan { +- st,pins { +- keyin0 = <&pio4 0 ALT6 IN>; +- keyin1 = <&pio4 5 ALT4 IN>; +- keyin2 = <&pio0 4 ALT2 IN>; +- keyin3 = <&pio2 6 ALT2 IN>; +- +- keyout0 = <&pio4 6 ALT4 OUT>; +- keyout1 = <&pio1 7 ALT2 OUT>; +- keyout2 = <&pio0 6 ALT2 OUT>; +- keyout3 = <&pio2 7 ALT2 OUT>; +- }; +- }; +- }; +- +- gmac1 { +- /* +- * Almost all the boards based on STiH407 SoC have an embedded +- * switch where the mdio/mdc have been used for managing the SMI +- * iface via I2C. For this reason these lines can be allocated +- * by using dedicated configuration (in case of there will be a +- * standard PHY transceiver on-board). +- */ +- pinctrl_rgmii1: rgmii1-0 { +- st,pins { +- +- txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>; +- txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>; +- txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>; +- txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>; +- txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; +- txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; +- rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>; +- rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>; +- rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; +- rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; +- rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>; +- rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; +- clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>; +- phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>; +- }; +- }; +- +- pinctrl_rgmii1_mdio: rgmii1-mdio { +- st,pins { +- mdio = <&pio1 0 ALT1 OUT BYPASS 0>; +- mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; +- mdint = <&pio1 3 ALT1 IN BYPASS 0>; +- }; +- }; +- +- pinctrl_rgmii1_mdio_1: rgmii1-mdio-1 { +- st,pins { +- mdio = <&pio1 0 ALT1 OUT BYPASS 0>; +- mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; +- }; +- }; +- +- pinctrl_mii1: mii1 { +- st,pins { +- txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; +- txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; +- txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; +- txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; +- txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; +- txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; +- txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; +- col = <&pio0 7 ALT1 IN BYPASS 1000>; +- +- mdio = <&pio1 0 ALT1 OUT BYPASS 1500>; +- mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; +- crs = <&pio1 2 ALT1 IN BYPASS 1000>; +- mdint = <&pio1 3 ALT1 IN BYPASS 0>; +- rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- +- rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; +- phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; +- }; +- }; +- +- pinctrl_rmii1: rmii1-0 { +- st,pins { +- txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; +- txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; +- txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; +- mdio = <&pio1 0 ALT1 OUT BYPASS 0>; +- mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; +- mdint = <&pio1 3 ALT1 IN BYPASS 0>; +- rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>; +- rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>; +- rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>; +- rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- }; +- }; +- +- pinctrl_rmii1_phyclk: rmii1_phyclk { +- st,pins { +- phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; +- }; +- }; +- +- pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext { +- st,pins { +- phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>; +- }; +- }; +- }; +- +- pwm1 { +- pinctrl_pwm1_chan0_default: pwm1-0-default { +- st,pins { +- pwm-out = <&pio3 0 ALT1 OUT>; +- pwm-capturein = <&pio3 2 ALT1 IN>; +- }; +- }; +- pinctrl_pwm1_chan1_default: pwm1-1-default { +- st,pins { +- pwm-capturein = <&pio4 3 ALT1 IN>; +- pwm-out = <&pio4 4 ALT1 OUT>; +- }; +- }; +- pinctrl_pwm1_chan2_default: pwm1-2-default { +- st,pins { +- pwm-out = <&pio4 6 ALT3 OUT>; +- }; +- }; +- pinctrl_pwm1_chan3_default: pwm1-3-default { +- st,pins { +- pwm-out = <&pio4 7 ALT3 OUT>; +- }; +- }; +- }; +- +- spi10 { +- pinctrl_spi10_default: spi10-4w-alt1-0 { +- st,pins { +- mtsr = <&pio4 6 ALT1 OUT>; +- mrst = <&pio4 7 ALT1 IN>; +- scl = <&pio4 5 ALT1 OUT>; +- }; +- }; +- +- pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 { +- st,pins { +- mtsr = <&pio4 6 ALT1 BIDIR_PU>; +- scl = <&pio4 5 ALT1 OUT>; +- }; +- }; +- }; +- +- spi11 { +- pinctrl_spi11_default: spi11-4w-alt2-0 { +- st,pins { +- mtsr = <&pio3 1 ALT2 OUT>; +- mrst = <&pio3 0 ALT2 IN>; +- scl = <&pio3 2 ALT2 OUT>; +- }; +- }; +- +- pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 { +- st,pins { +- mtsr = <&pio3 1 ALT2 BIDIR_PU>; +- scl = <&pio3 2 ALT2 OUT>; +- }; +- }; +- }; +- +- spi12 { +- pinctrl_spi12_default: spi12-4w-alt2-0 { +- st,pins { +- mtsr = <&pio3 6 ALT2 OUT>; +- mrst = <&pio3 4 ALT2 IN>; +- scl = <&pio3 7 ALT2 OUT>; +- }; +- }; +- +- pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 { +- st,pins { +- mtsr = <&pio3 6 ALT2 BIDIR_PU>; +- scl = <&pio3 7 ALT2 OUT>; +- }; +- }; +- }; +- }; +- +- pin-controller-front0@920f080 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,stih407-front-pinctrl"; +- st,syscfg = <&syscfg_front>; +- reg = <0x0920f080 0x4>; +- reg-names = "irqmux"; +- interrupts = ; +- interrupt-names = "irqmux"; +- ranges = <0 0x09200000 0x10000>; +- +- pio10: pio@9200000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x0 0x100>; +- st,bank-name = "PIO10"; +- }; +- pio11: pio@9201000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x1000 0x100>; +- st,bank-name = "PIO11"; +- }; +- pio12: pio@9202000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x2000 0x100>; +- st,bank-name = "PIO12"; +- }; +- pio13: pio@9203000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x3000 0x100>; +- st,bank-name = "PIO13"; +- }; +- pio14: pio@9204000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x4000 0x100>; +- st,bank-name = "PIO14"; +- }; +- pio15: pio@9205000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x5000 0x100>; +- st,bank-name = "PIO15"; +- }; +- pio16: pio@9206000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x6000 0x100>; +- st,bank-name = "PIO16"; +- }; +- pio17: pio@9207000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x7000 0x100>; +- st,bank-name = "PIO17"; +- }; +- pio18: pio@9208000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x8000 0x100>; +- st,bank-name = "PIO18"; +- }; +- pio19: pio@9209000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x9000 0x100>; +- st,bank-name = "PIO19"; +- }; +- +- /* Comms */ +- serial0 { +- pinctrl_serial0: serial0-0 { +- st,pins { +- tx = <&pio17 0 ALT1 OUT>; +- rx = <&pio17 1 ALT1 IN>; +- }; +- }; +- pinctrl_serial0_hw_flowctrl: serial0-0_hw_flowctrl { +- st,pins { +- tx = <&pio17 0 ALT1 OUT>; +- rx = <&pio17 1 ALT1 IN>; +- cts = <&pio17 2 ALT1 IN>; +- rts = <&pio17 3 ALT1 OUT>; +- }; +- }; +- }; +- +- serial1 { +- pinctrl_serial1: serial1-0 { +- st,pins { +- tx = <&pio16 0 ALT1 OUT>; +- rx = <&pio16 1 ALT1 IN>; +- }; +- }; +- }; +- +- serial2 { +- pinctrl_serial2: serial2-0 { +- st,pins { +- tx = <&pio15 0 ALT1 OUT>; +- rx = <&pio15 1 ALT1 IN>; +- }; +- }; +- }; +- +- mmc1 { +- pinctrl_sd1: sd1-0 { +- st,pins { +- sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>; +- sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>; +- sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>; +- sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>; +- sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>; +- sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>; +- sd_led = <&pio16 6 ALT6 OUT>; +- sd_pwren = <&pio16 7 ALT6 OUT>; +- sd_cd = <&pio19 0 ALT6 IN>; +- sd_wp = <&pio19 1 ALT6 IN>; +- }; +- }; +- }; +- +- +- i2c0 { +- pinctrl_i2c0_default: i2c0-default { +- st,pins { +- sda = <&pio10 6 ALT2 BIDIR>; +- scl = <&pio10 5 ALT2 BIDIR>; +- }; +- }; +- }; +- +- i2c1 { +- pinctrl_i2c1_default: i2c1-default { +- st,pins { +- sda = <&pio11 1 ALT2 BIDIR>; +- scl = <&pio11 0 ALT2 BIDIR>; +- }; +- }; +- }; +- +- i2c2 { +- pinctrl_i2c2_default: i2c2-default { +- st,pins { +- sda = <&pio15 6 ALT2 BIDIR>; +- scl = <&pio15 5 ALT2 BIDIR>; +- }; +- }; +- +- pinctrl_i2c2_alt2_1: i2c2-alt2-1 { +- st,pins { +- sda = <&pio12 6 ALT2 BIDIR>; +- scl = <&pio12 5 ALT2 BIDIR>; +- }; +- }; +- }; +- +- i2c3 { +- pinctrl_i2c3_default: i2c3-alt1-0 { +- st,pins { +- sda = <&pio18 6 ALT1 BIDIR>; +- scl = <&pio18 5 ALT1 BIDIR>; +- }; +- }; +- pinctrl_i2c3_alt1_1: i2c3-alt1-1 { +- st,pins { +- sda = <&pio17 7 ALT1 BIDIR>; +- scl = <&pio17 6 ALT1 BIDIR>; +- }; +- }; +- pinctrl_i2c3_alt3_0: i2c3-alt3-0 { +- st,pins { +- sda = <&pio13 6 ALT3 BIDIR>; +- scl = <&pio13 5 ALT3 BIDIR>; +- }; +- }; +- }; +- +- spi0 { +- pinctrl_spi0_default: spi0-4w-alt2-0 { +- st,pins { +- mtsr = <&pio10 6 ALT2 OUT>; +- mrst = <&pio10 7 ALT2 IN>; +- scl = <&pio10 5 ALT2 OUT>; +- }; +- }; +- +- pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 { +- st,pins { +- mtsr = <&pio10 6 ALT2 BIDIR_PU>; +- scl = <&pio10 5 ALT2 OUT>; +- }; +- }; +- +- pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 { +- st,pins { +- mtsr = <&pio19 7 ALT1 OUT>; +- mrst = <&pio19 5 ALT1 IN>; +- scl = <&pio19 6 ALT1 OUT>; +- }; +- }; +- +- pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 { +- st,pins { +- mtsr = <&pio19 7 ALT1 BIDIR_PU>; +- scl = <&pio19 6 ALT1 OUT>; +- }; +- }; +- }; +- +- spi1 { +- pinctrl_spi1_default: spi1-4w-alt2-0 { +- st,pins { +- mtsr = <&pio11 1 ALT2 OUT>; +- mrst = <&pio11 2 ALT2 IN>; +- scl = <&pio11 0 ALT2 OUT>; +- }; +- }; +- +- pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 { +- st,pins { +- mtsr = <&pio11 1 ALT2 BIDIR_PU>; +- scl = <&pio11 0 ALT2 OUT>; +- }; +- }; +- +- pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 { +- st,pins { +- mtsr = <&pio14 3 ALT1 OUT>; +- mrst = <&pio14 4 ALT1 IN>; +- scl = <&pio14 2 ALT1 OUT>; +- }; +- }; +- +- pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 { +- st,pins { +- mtsr = <&pio14 3 ALT1 BIDIR_PU>; +- scl = <&pio14 2 ALT1 OUT>; +- }; +- }; +- }; +- +- spi2 { +- pinctrl_spi2_default: spi2-4w-alt2-0 { +- st,pins { +- mtsr = <&pio12 6 ALT2 OUT>; +- mrst = <&pio12 7 ALT2 IN>; +- scl = <&pio12 5 ALT2 OUT>; +- }; +- }; +- +- pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 { +- st,pins { +- mtsr = <&pio12 6 ALT2 BIDIR_PU>; +- scl = <&pio12 5 ALT2 OUT>; +- }; +- }; +- +- pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 { +- st,pins { +- mtsr = <&pio14 6 ALT1 OUT>; +- mrst = <&pio14 7 ALT1 IN>; +- scl = <&pio14 5 ALT1 OUT>; +- }; +- }; +- +- pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 { +- st,pins { +- mtsr = <&pio14 6 ALT1 BIDIR_PU>; +- scl = <&pio14 5 ALT1 OUT>; +- }; +- }; +- +- pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 { +- st,pins { +- mtsr = <&pio15 6 ALT2 OUT>; +- mrst = <&pio15 7 ALT2 IN>; +- scl = <&pio15 5 ALT2 OUT>; +- }; +- }; +- +- pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 { +- st,pins { +- mtsr = <&pio15 6 ALT2 BIDIR_PU>; +- scl = <&pio15 5 ALT2 OUT>; +- }; +- }; +- }; +- +- spi3 { +- pinctrl_spi3_default: spi3-4w-alt3-0 { +- st,pins { +- mtsr = <&pio13 6 ALT3 OUT>; +- mrst = <&pio13 7 ALT3 IN>; +- scl = <&pio13 5 ALT3 OUT>; +- }; +- }; +- +- pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 { +- st,pins { +- mtsr = <&pio13 6 ALT3 BIDIR_PU>; +- scl = <&pio13 5 ALT3 OUT>; +- }; +- }; +- +- pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 { +- st,pins { +- mtsr = <&pio17 7 ALT1 OUT>; +- mrst = <&pio17 5 ALT1 IN>; +- scl = <&pio17 6 ALT1 OUT>; +- }; +- }; +- +- pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 { +- st,pins { +- mtsr = <&pio17 7 ALT1 BIDIR_PU>; +- scl = <&pio17 6 ALT1 OUT>; +- }; +- }; +- +- pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 { +- st,pins { +- mtsr = <&pio18 6 ALT1 OUT>; +- mrst = <&pio18 7 ALT1 IN>; +- scl = <&pio18 5 ALT1 OUT>; +- }; +- }; +- +- pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 { +- st,pins { +- mtsr = <&pio18 6 ALT1 BIDIR_PU>; +- scl = <&pio18 5 ALT1 OUT>; +- }; +- }; +- }; +- +- tsin0 { +- pinctrl_tsin0_parallel: tsin0_parallel { +- st,pins { +- DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>; +- VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- }; +- }; +- pinctrl_tsin0_serial: tsin0_serial { +- st,pins { +- DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>; +- VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- }; +- }; +- }; +- +- tsin1 { +- pinctrl_tsin1_parallel: tsin1_parallel { +- st,pins { +- DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>; +- VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- }; +- }; +- pinctrl_tsin1_serial: tsin1_serial { +- st,pins { +- DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>; +- VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- }; +- }; +- }; +- +- tsin2 { +- pinctrl_tsin2_parallel: tsin2_parallel { +- st,pins { +- DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>; +- DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>; +- DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>; +- DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; +- DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>; +- DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; +- DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; +- CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; +- VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- }; +- }; +- pinctrl_tsin2_serial: tsin2_serial { +- st,pins { +- DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; +- VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- }; +- }; +- }; +- +- tsin3 { +- pinctrl_tsin3_serial: tsin3_serial { +- st,pins { +- DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>; +- VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- }; +- }; +- }; +- +- tsin4 { +- pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 { +- st,pins { +- DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; +- CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>; +- VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>; +- ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>; +- PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; +- }; +- }; +- }; +- +- tsin5 { +- pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 { +- st,pins { +- DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>; +- VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- }; +- }; +- pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 { +- st,pins { +- DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>; +- CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>; +- VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; +- ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; +- PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; +- }; +- }; +- }; +- +- tsout0 { +- pinctrl_tsout0_parallel: tsout0_parallel { +- st,pins { +- DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>; +- DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>; +- DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>; +- DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>; +- DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; +- DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; +- DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; +- DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>; +- CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>; +- VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; +- ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; +- PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; +- }; +- }; +- pinctrl_tsout0_serial: tsout0_serial { +- st,pins { +- DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>; +- CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>; +- VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; +- ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; +- PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; +- }; +- }; +- }; +- +- tsout1 { +- pinctrl_tsout1_serial: tsout1_serial { +- st,pins { +- DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; +- CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>; +- VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; +- ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; +- PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; +- }; +- }; +- }; +- +- mtsin0 { +- pinctrl_mtsin0_parallel: mtsin0_parallel { +- st,pins { +- DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; +- DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>; +- DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; +- DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>; +- DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; +- DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; +- DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; +- DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>; +- CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>; +- VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; +- ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; +- PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; +- }; +- }; +- }; +- +- systrace { +- pinctrl_systrace_default: systrace-default { +- st,pins { +- trc_data0 = <&pio11 3 ALT5 OUT>; +- trc_data1 = <&pio11 4 ALT5 OUT>; +- trc_data2 = <&pio11 5 ALT5 OUT>; +- trc_data3 = <&pio11 6 ALT5 OUT>; +- trc_clk = <&pio11 7 ALT5 OUT>; +- }; +- }; +- }; +- }; +- +- pin-controller-front1@921f080 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,stih407-front-pinctrl"; +- st,syscfg = <&syscfg_front>; +- reg = <0x0921f080 0x4>; +- reg-names = "irqmux"; +- interrupts = ; +- interrupt-names = "irqmux"; +- ranges = <0 0x09210000 0x10000>; +- +- pio20: pio@9210000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x0 0x100>; +- st,bank-name = "PIO20"; +- }; +- +- tsin4 { +- pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 { +- st,pins { +- DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>; +- VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; +- }; +- }; +- }; +- }; +- +- pin-controller-rear@922f080 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,stih407-rear-pinctrl"; +- st,syscfg = <&syscfg_rear>; +- reg = <0x0922f080 0x4>; +- reg-names = "irqmux"; +- interrupts = ; +- interrupt-names = "irqmux"; +- ranges = <0 0x09220000 0x6000>; +- +- pio30: gpio@9220000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x0 0x100>; +- st,bank-name = "PIO30"; +- }; +- pio31: gpio@9221000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x1000 0x100>; +- st,bank-name = "PIO31"; +- }; +- pio32: gpio@9222000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x2000 0x100>; +- st,bank-name = "PIO32"; +- }; +- pio33: gpio@9223000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x3000 0x100>; +- st,bank-name = "PIO33"; +- }; +- pio34: gpio@9224000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x4000 0x100>; +- st,bank-name = "PIO34"; +- }; +- pio35: gpio@9225000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x5000 0x100>; +- st,bank-name = "PIO35"; +- st,retime-pin-mask = <0x7f>; +- }; +- +- i2c4 { +- pinctrl_i2c4_default: i2c4-default { +- st,pins { +- sda = <&pio30 1 ALT1 BIDIR>; +- scl = <&pio30 0 ALT1 BIDIR>; +- }; +- }; +- }; +- +- i2c5 { +- pinctrl_i2c5_default: i2c5-default { +- st,pins { +- sda = <&pio34 4 ALT1 BIDIR>; +- scl = <&pio34 3 ALT1 BIDIR>; +- }; +- }; +- }; +- +- usb3 { +- pinctrl_usb3: usb3-2 { +- st,pins { +- usb-oc-detect = <&pio35 4 ALT1 IN>; +- usb-pwr-enable = <&pio35 5 ALT1 OUT>; +- usb-vbus-valid = <&pio35 6 ALT1 IN>; +- }; +- }; +- }; +- +- pwm0 { +- pinctrl_pwm0_chan0_default: pwm0-0-default { +- st,pins { +- pwm-capturein = <&pio31 0 ALT1 IN>; +- pwm-out = <&pio31 1 ALT1 OUT>; +- }; +- }; +- }; +- +- spi4 { +- pinctrl_spi4_default: spi4-4w-alt1-0 { +- st,pins { +- mtsr = <&pio30 1 ALT1 OUT>; +- mrst = <&pio30 2 ALT1 IN>; +- scl = <&pio30 0 ALT1 OUT>; +- }; +- }; +- +- pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 { +- st,pins { +- mtsr = <&pio30 1 ALT1 BIDIR_PU>; +- scl = <&pio30 0 ALT1 OUT>; +- }; +- }; +- +- pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 { +- st,pins { +- mtsr = <&pio34 1 ALT3 OUT>; +- mrst = <&pio34 2 ALT3 IN>; +- scl = <&pio34 0 ALT3 OUT>; +- }; +- }; +- +- pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 { +- st,pins { +- mtsr = <&pio34 1 ALT3 BIDIR_PU>; +- scl = <&pio34 0 ALT3 OUT>; +- }; +- }; +- }; +- +- i2s_out { +- pinctrl_i2s_8ch_out: i2s_8ch_out{ +- st,pins { +- mclk = <&pio33 5 ALT1 OUT>; +- lrclk = <&pio33 7 ALT1 OUT>; +- sclk = <&pio33 6 ALT1 OUT>; +- data0 = <&pio33 4 ALT1 OUT>; +- data1 = <&pio34 0 ALT1 OUT>; +- data2 = <&pio34 1 ALT1 OUT>; +- data3 = <&pio34 2 ALT1 OUT>; +- }; +- }; +- +- pinctrl_i2s_2ch_out: i2s_2ch_out{ +- st,pins { +- mclk = <&pio33 5 ALT1 OUT>; +- lrclk = <&pio33 7 ALT1 OUT>; +- sclk = <&pio33 6 ALT1 OUT>; +- data0 = <&pio33 4 ALT1 OUT>; +- }; +- }; +- }; +- +- i2s_in { +- pinctrl_i2s_8ch_in: i2s_8ch_in{ +- st,pins { +- mclk = <&pio32 5 ALT1 IN>; +- lrclk = <&pio32 7 ALT1 IN>; +- sclk = <&pio32 6 ALT1 IN>; +- data0 = <&pio32 4 ALT1 IN>; +- data1 = <&pio33 0 ALT1 IN>; +- data2 = <&pio33 1 ALT1 IN>; +- data3 = <&pio33 2 ALT1 IN>; +- data4 = <&pio33 3 ALT1 IN>; +- }; +- }; +- +- pinctrl_i2s_2ch_in: i2s_2ch_in{ +- st,pins { +- mclk = <&pio32 5 ALT1 IN>; +- lrclk = <&pio32 7 ALT1 IN>; +- sclk = <&pio32 6 ALT1 IN>; +- data0 = <&pio32 4 ALT1 IN>; +- }; +- }; +- }; +- +- spdif_out { +- pinctrl_spdif_out: spdif_out{ +- st,pins { +- spdif_out = <&pio34 7 ALT1 OUT>; +- }; +- }; +- }; +- +- serial3 { +- pinctrl_serial3: serial3-0 { +- st,pins { +- tx = <&pio31 3 ALT1 OUT>; +- rx = <&pio31 4 ALT1 IN>; +- }; +- }; +- }; +- }; +- +- pin-controller-flash@923f080 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,stih407-flash-pinctrl"; +- st,syscfg = <&syscfg_flash>; +- reg = <0x0923f080 0x4>; +- reg-names = "irqmux"; +- interrupts = ; +- interrupt-names = "irqmux"; +- ranges = <0 0x09230000 0x3000>; +- +- pio40: gpio@9230000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0 0x100>; +- st,bank-name = "PIO40"; +- }; +- pio41: gpio@9231000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x1000 0x100>; +- st,bank-name = "PIO41"; +- }; +- pio42: gpio@9232000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x2000 0x100>; +- st,bank-name = "PIO42"; +- }; +- +- mmc0 { +- pinctrl_mmc0: mmc0-0 { +- st,pins { +- emmc_clk = <&pio40 6 ALT1 BIDIR>; +- emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>; +- emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>; +- emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>; +- emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>; +- emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>; +- emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>; +- emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>; +- emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>; +- emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>; +- }; +- }; +- pinctrl_sd0: sd0-0 { +- st,pins { +- sd_clk = <&pio40 6 ALT1 BIDIR>; +- sd_cmd = <&pio40 7 ALT1 BIDIR_PU>; +- sd_dat0 = <&pio41 0 ALT1 BIDIR_PU>; +- sd_dat1 = <&pio41 1 ALT1 BIDIR_PU>; +- sd_dat2 = <&pio41 2 ALT1 BIDIR_PU>; +- sd_dat3 = <&pio41 3 ALT1 BIDIR_PU>; +- sd_led = <&pio42 0 ALT2 OUT>; +- sd_pwren = <&pio42 2 ALT2 OUT>; +- sd_vsel = <&pio42 3 ALT2 OUT>; +- sd_cd = <&pio42 4 ALT2 IN>; +- sd_wp = <&pio42 5 ALT2 IN>; +- }; +- }; +- }; +- +- fsm { +- pinctrl_fsm: fsm { +- st,pins { +- spi-fsm-clk = <&pio40 1 ALT1 OUT>; +- spi-fsm-cs = <&pio40 0 ALT1 OUT>; +- spi-fsm-mosi = <&pio40 2 ALT1 OUT>; +- spi-fsm-miso = <&pio40 3 ALT1 IN>; +- spi-fsm-hol = <&pio40 5 ALT1 OUT>; +- spi-fsm-wp = <&pio40 4 ALT1 OUT>; +- }; +- }; +- }; +- +- nand { +- pinctrl_nand: nand { +- st,pins { +- nand_cs1 = <&pio40 6 ALT3 OUT>; +- nand_cs0 = <&pio40 7 ALT3 OUT>; +- nand_d0 = <&pio41 0 ALT3 BIDIR>; +- nand_d1 = <&pio41 1 ALT3 BIDIR>; +- nand_d2 = <&pio41 2 ALT3 BIDIR>; +- nand_d3 = <&pio41 3 ALT3 BIDIR>; +- nand_d4 = <&pio41 4 ALT3 BIDIR>; +- nand_d5 = <&pio41 5 ALT3 BIDIR>; +- nand_d6 = <&pio41 6 ALT3 BIDIR>; +- nand_d7 = <&pio41 7 ALT3 BIDIR>; +- nand_we = <&pio42 0 ALT3 OUT>; +- nand_dqs = <&pio42 1 ALT3 OUT>; +- nand_ale = <&pio42 2 ALT3 OUT>; +- nand_cle = <&pio42 3 ALT3 OUT>; +- nand_rnb = <&pio42 4 ALT3 IN>; +- nand_oe = <&pio42 5 ALT3 OUT>; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stih407.dtsi b/scripts/dtc/include-prefixes/arm/stih407.dtsi +deleted file mode 100644 +index 9e212b0af89d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stih407.dtsi ++++ /dev/null +@@ -1,145 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 STMicroelectronics Limited. +- * Author: Gabriel Fernandez +- */ +-#include "stih407-clock.dtsi" +-#include "stih407-family.dtsi" +-#include +-/ { +- soc { +- sti-display-subsystem@0 { +- compatible = "st,sti-display-subsystem"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0 0>; +- assigned-clocks = <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 1>, +- <&clk_s_c0_pll1 0>, +- <&clk_s_c0_flexgen CLK_COMPO_DVP>, +- <&clk_s_c0_flexgen CLK_MAIN_DISP>, +- <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, +- <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, +- <&clk_s_d2_flexgen CLK_PIX_GDP1>, +- <&clk_s_d2_flexgen CLK_PIX_GDP2>, +- <&clk_s_d2_flexgen CLK_PIX_GDP3>, +- <&clk_s_d2_flexgen CLK_PIX_GDP4>; +- +- assigned-clock-parents = <0>, +- <0>, +- <0>, +- <&clk_s_c0_pll1 0>, +- <&clk_s_c0_pll1 0>, +- <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 1>, +- <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 0>; +- +- assigned-clock-rates = <297000000>, +- <108000000>, +- <0>, +- <400000000>, +- <400000000>; +- +- ranges; +- +- sti-compositor@9d11000 { +- compatible = "st,stih407-compositor"; +- reg = <0x9d11000 0x1000>; +- +- clock-names = "compo_main", +- "compo_aux", +- "pix_main", +- "pix_aux", +- "pix_gdp1", +- "pix_gdp2", +- "pix_gdp3", +- "pix_gdp4", +- "main_parent", +- "aux_parent"; +- +- clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, +- <&clk_s_c0_flexgen CLK_COMPO_DVP>, +- <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, +- <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, +- <&clk_s_d2_flexgen CLK_PIX_GDP1>, +- <&clk_s_d2_flexgen CLK_PIX_GDP2>, +- <&clk_s_d2_flexgen CLK_PIX_GDP3>, +- <&clk_s_d2_flexgen CLK_PIX_GDP4>, +- <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 1>; +- +- reset-names = "compo-main", "compo-aux"; +- resets = <&softreset STIH407_COMPO_SOFTRESET>, +- <&softreset STIH407_COMPO_SOFTRESET>; +- st,vtg = <&vtg_main>, <&vtg_aux>; +- }; +- +- sti-tvout@8d08000 { +- compatible = "st,stih407-tvout"; +- reg = <0x8d08000 0x1000>; +- reg-names = "tvout-reg"; +- reset-names = "tvout"; +- resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; +- #address-cells = <1>; +- #size-cells = <1>; +- assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, +- <&clk_s_d2_flexgen CLK_TMDS_HDMI>, +- <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, +- <&clk_s_d0_flexgen CLK_PCM_0>, +- <&clk_s_d2_flexgen CLK_PIX_HDDAC>, +- <&clk_s_d2_flexgen CLK_HDDAC>; +- +- assigned-clock-parents = <&clk_s_d2_quadfs 0>, +- <&clk_tmdsout_hdmi>, +- <&clk_s_d2_quadfs 0>, +- <&clk_s_d0_quadfs 0>, +- <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 0>; +- }; +- +- sti_hdmi: sti-hdmi@8d04000 { +- compatible = "st,stih407-hdmi"; +- reg = <0x8d04000 0x1000>; +- reg-names = "hdmi-reg"; +- #sound-dai-cells = <0>; +- interrupts = ; +- interrupt-names = "irq"; +- clock-names = "pix", +- "tmds", +- "phy", +- "audio", +- "main_parent", +- "aux_parent"; +- +- clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, +- <&clk_s_d2_flexgen CLK_TMDS_HDMI>, +- <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, +- <&clk_s_d0_flexgen CLK_PCM_0>, +- <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 1>; +- +- hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; +- reset-names = "hdmi"; +- resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; +- ddc = <&hdmiddc>; +- }; +- +- sti-hda@8d02000 { +- compatible = "st,stih407-hda"; +- reg = <0x8d02000 0x400>, <0x92b0120 0x4>; +- reg-names = "hda-reg", "video-dacs-ctrl"; +- clock-names = "pix", +- "hddac", +- "main_parent", +- "aux_parent"; +- clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, +- <&clk_s_d2_flexgen CLK_HDDAC>, +- <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 1>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stih410-b2120.dts b/scripts/dtc/include-prefixes/arm/stih410-b2120.dts +deleted file mode 100644 +index 9d3b118f5f0f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stih410-b2120.dts ++++ /dev/null +@@ -1,66 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 STMicroelectronics (R&D) Limited. +- * Author: Peter Griffin +- */ +-/dts-v1/; +-#include "stih410.dtsi" +-#include "stihxxx-b2120.dtsi" +-/ { +- model = "STiH410 B2120"; +- compatible = "st,stih410-b2120", "st,stih410"; +- +- chosen { +- stdout-path = &sbc_serial0; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x80000000>; +- }; +- +- aliases { +- serial0 = &sbc_serial0; +- ethernet0 = ðernet0; +- }; +- +- soc { +- +- mmc0: sdhci@9060000 { +- max-frequency = <200000000>; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- sd-uhs-ddr50; +- }; +- +- usb2_picophy1: phy2@0 { +- status = "okay"; +- }; +- +- usb2_picophy2: phy3@0 { +- status = "okay"; +- }; +- +- ohci0: usb@9a03c00 { +- status = "okay"; +- }; +- +- ehci0: usb@9a03e00 { +- status = "okay"; +- }; +- +- ohci1: usb@9a83c00 { +- status = "okay"; +- }; +- +- ehci1: usb@9a83e00 { +- status = "okay"; +- }; +- +- sti-display-subsystem@0 { +- sti-hda@8d02000 { +- status = "okay"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stih410-b2260.dts b/scripts/dtc/include-prefixes/arm/stih410-b2260.dts +deleted file mode 100644 +index 9d579c16c295..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stih410-b2260.dts ++++ /dev/null +@@ -1,210 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2016 STMicroelectronics (R&D) Limited. +- * Author: Patrice Chotard +- */ +-/dts-v1/; +-#include "stih410.dtsi" +-#include +- +-/ { +- model = "STiH410 B2260"; +- compatible = "st,stih410-b2260", "st,stih410"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0x40000000>; +- }; +- +- aliases { +- serial1 = &uart1; +- ethernet0 = ðernet0; +- }; +- +- leds { +- compatible = "gpio-leds"; +- user_green_1 { +- label = "User_green_1"; +- gpios = <&pio1 3 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- +- user_green_2 { +- label = "User_green_2"; +- gpios = <&pio4 1 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- user_green_3 { +- label = "User_green_3"; +- gpios = <&pio2 1 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- user_green_4 { +- label = "User_green_4"; +- gpios = <&pio2 5 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- sound: sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "STI-B2260"; +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- simple-audio-card,dai-link@0 { +- reg = <0>; +- /* DAC */ +- format = "i2s"; +- mclk-fs = <128>; +- cpu { +- sound-dai = <&sti_uni_player0>; +- }; +- +- codec { +- sound-dai = <&sti_hdmi>; +- }; +- }; +- }; +- +- soc { +- /* Low speed expansion connector */ +- uart0: serial@9830000 { +- label = "LS-UART0"; +- pinctrl-names = "default", "no-hw-flowctrl"; +- pinctrl-0 = <&pinctrl_serial0_hw_flowctrl>; +- pinctrl-1 = <&pinctrl_serial0>; +- rts-gpios = <&pio17 3 GPIO_ACTIVE_LOW>; +- uart-has-rtscts; +- status = "okay"; +- }; +- +- /* Low speed expansion connector */ +- uart1: serial@9831000 { +- label = "LS-UART1"; +- status = "okay"; +- }; +- +- /* Low speed expansion connector */ +- spi0: spi@9844000 { +- label = "LS-SPI0"; +- cs-gpios = <&pio30 3 0>; +- status = "okay"; +- }; +- +- /* Low speed expansion connector */ +- i2c0: i2c@9840000 { +- label = "LS-I2C0"; +- status = "okay"; +- }; +- +- /* Low speed expansion connector */ +- i2c1: i2c@9841000 { +- label = "LS-I2C1"; +- status = "okay"; +- }; +- +- /* high speed expansion connector */ +- i2c2: i2c@9842000 { +- label = "HS-I2C2"; +- pinctrl-0 = <&pinctrl_i2c2_alt2_1>; +- status = "okay"; +- }; +- +- /* high speed expansion connector */ +- i2c3: i2c@9843000 { +- label = "HS-I2C3"; +- pinctrl-0 = <&pinctrl_i2c3_alt3_0>; +- status = "okay"; +- }; +- +- mmc0: sdhci@9060000 { +- pinctrl-0 = <&pinctrl_sd0>; +- bus-width = <4>; +- status = "okay"; +- }; +- +- /* high speed expansion connector */ +- mmc1: sdhci@9080000 { +- status = "okay"; +- }; +- +- pwm0: pwm@9810000 { +- status = "okay"; +- }; +- +- pwm1: pwm@9510000 { +- status = "okay"; +- }; +- +- usb2_picophy1: phy2@0 { +- status = "okay"; +- }; +- +- usb2_picophy2: phy3@0 { +- status = "okay"; +- }; +- +- ohci0: usb@9a03c00 { +- status = "okay"; +- }; +- +- ehci0: usb@9a03e00 { +- status = "okay"; +- }; +- +- ohci1: usb@9a83c00 { +- status = "okay"; +- }; +- +- ehci1: usb@9a83e00 { +- status = "okay"; +- }; +- +- st_dwc3: dwc3@8f94000 { +- status = "okay"; +- }; +- +- ethernet0: dwmac@9630000 { +- phy-mode = "rgmii"; +- pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>; +- +- snps,reset-gpio = <&pio0 7 0>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 1000000>; +- +- status = "okay"; +- }; +- +- sti_uni_player0: sti-uni-player@8d80000 { +- status = "okay"; +- }; +- /* SSC11 to HDMI */ +- hdmiddc: i2c@9541000 { +- /* HDMI V1.3a supports Standard mode only */ +- clock-frequency = <100000>; +- st,i2c-min-scl-pulse-width-us = <0>; +- st,i2c-min-sda-pulse-width-us = <5>; +- status = "okay"; +- }; +- +- miphy28lp_phy: miphy28lp@0 { +- +- phy_port1: port@9b2a000 { +- st,osc-force-ext; +- }; +- }; +- +- sata1: sata@9b28000 { +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stih410-clock.dtsi b/scripts/dtc/include-prefixes/arm/stih410-clock.dtsi +deleted file mode 100644 +index 6b0e6d4477a3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stih410-clock.dtsi ++++ /dev/null +@@ -1,219 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 STMicroelectronics R&D Limited +- */ +-#include +-/ { +- /* +- * Fixed 30MHz oscillator inputs to SoC +- */ +- clk_sysin: clk-sysin { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <30000000>; +- clock-output-names = "CLK_SYSIN"; +- }; +- +- clk_tmdsout_hdmi: clk-tmdsout-hdmi { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- compatible = "st,stih410-clk", "simple-bus"; +- +- /* +- * A9 PLL. +- */ +- clockgen-a9@92b0000 { +- compatible = "st,clkgen-c32"; +- reg = <0x92b0000 0xffff>; +- +- clockgen_a9_pll: clockgen-a9-pll { +- #clock-cells = <1>; +- compatible = "st,stih407-clkgen-plla9"; +- +- clocks = <&clk_sysin>; +- }; +- }; +- +- /* +- * ARM CPU related clocks. +- */ +- clk_m_a9: clk-m-a9@92b0000 { +- #clock-cells = <0>; +- compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; +- reg = <0x92b0000 0x10000>; +- +- clocks = <&clockgen_a9_pll 0>, +- <&clockgen_a9_pll 0>, +- <&clk_s_c0_flexgen 13>, +- <&clk_m_a9_ext2f_div2>; +- /* +- * ARM Peripheral clock for timers +- */ +- arm_periph_clk: clk-m-a9-periphs { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&clk_m_a9>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- }; +- +- clockgen-a@90ff000 { +- compatible = "st,clkgen-c32"; +- reg = <0x90ff000 0x1000>; +- +- clk_s_a0_pll: clk-s-a0-pll { +- #clock-cells = <1>; +- compatible = "st,clkgen-pll0-a0"; +- +- clocks = <&clk_sysin>; +- }; +- +- clk_s_a0_flexgen: clk-s-a0-flexgen { +- compatible = "st,flexgen", "st,flexgen-stih410-a0"; +- +- #clock-cells = <1>; +- +- clocks = <&clk_s_a0_pll 0>, +- <&clk_sysin>; +- }; +- }; +- +- clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { +- #clock-cells = <1>; +- compatible = "st,quadfs-pll"; +- reg = <0x9103000 0x1000>; +- +- clocks = <&clk_sysin>; +- }; +- +- clk_s_c0: clockgen-c@9103000 { +- compatible = "st,clkgen-c32"; +- reg = <0x9103000 0x1000>; +- +- clk_s_c0_pll0: clk-s-c0-pll0 { +- #clock-cells = <1>; +- compatible = "st,clkgen-pll0-c0"; +- +- clocks = <&clk_sysin>; +- }; +- +- clk_s_c0_pll1: clk-s-c0-pll1 { +- #clock-cells = <1>; +- compatible = "st,clkgen-pll1-c0"; +- +- clocks = <&clk_sysin>; +- }; +- +- clk_s_c0_flexgen: clk-s-c0-flexgen { +- #clock-cells = <1>; +- compatible = "st,flexgen", "st,flexgen-stih410-c0"; +- +- clocks = <&clk_s_c0_pll0 0>, +- <&clk_s_c0_pll1 0>, +- <&clk_s_c0_quadfs 0>, +- <&clk_s_c0_quadfs 1>, +- <&clk_s_c0_quadfs 2>, +- <&clk_s_c0_quadfs 3>, +- <&clk_sysin>; +- +- /* +- * ARM Peripheral clock for timers +- */ +- clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- +- clocks = <&clk_s_c0_flexgen 13>; +- +- clock-output-names = "clk-m-a9-ext2f-div2"; +- +- clock-div = <2>; +- clock-mult = <1>; +- }; +- }; +- }; +- +- clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { +- #clock-cells = <1>; +- compatible = "st,quadfs-d0"; +- reg = <0x9104000 0x1000>; +- +- clocks = <&clk_sysin>; +- }; +- +- clockgen-d0@9104000 { +- compatible = "st,clkgen-c32"; +- reg = <0x9104000 0x1000>; +- +- clk_s_d0_flexgen: clk-s-d0-flexgen { +- #clock-cells = <1>; +- compatible = "st,flexgen", "st,flexgen-stih410-d0"; +- +- clocks = <&clk_s_d0_quadfs 0>, +- <&clk_s_d0_quadfs 1>, +- <&clk_s_d0_quadfs 2>, +- <&clk_s_d0_quadfs 3>, +- <&clk_sysin>; +- }; +- }; +- +- clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { +- #clock-cells = <1>; +- compatible = "st,quadfs-d2"; +- reg = <0x9106000 0x1000>; +- +- clocks = <&clk_sysin>; +- }; +- +- clockgen-d2@9106000 { +- compatible = "st,clkgen-c32"; +- reg = <0x9106000 0x1000>; +- +- clk_s_d2_flexgen: clk-s-d2-flexgen { +- #clock-cells = <1>; +- compatible = "st,flexgen", "st,flexgen-stih407-d2"; +- +- clocks = <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 1>, +- <&clk_s_d2_quadfs 2>, +- <&clk_s_d2_quadfs 3>, +- <&clk_sysin>, +- <&clk_sysin>, +- <&clk_tmdsout_hdmi>; +- }; +- }; +- +- clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { +- #clock-cells = <1>; +- compatible = "st,quadfs-d3"; +- reg = <0x9107000 0x1000>; +- +- clocks = <&clk_sysin>; +- }; +- +- clockgen-d3@9107000 { +- compatible = "st,clkgen-c32"; +- reg = <0x9107000 0x1000>; +- +- clk_s_d3_flexgen: clk-s-d3-flexgen { +- #clock-cells = <1>; +- compatible = "st,flexgen", "st,flexgen-stih407-d3"; +- +- clocks = <&clk_s_d3_quadfs 0>, +- <&clk_s_d3_quadfs 1>, +- <&clk_s_d3_quadfs 2>, +- <&clk_s_d3_quadfs 3>, +- <&clk_sysin>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stih410-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/stih410-pinctrl.dtsi +deleted file mode 100644 +index e6eadd124416..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stih410-pinctrl.dtsi ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 STMicroelectronics Limited. +- * Author: Peter Griffin +- */ +-#include "st-pincfg.h" +-/ { +- +- soc { +- pin-controller-rear@922f080 { +- +- usb0 { +- pinctrl_usb0: usb2-0 { +- st,pins { +- usb-oc-detect = <&pio35 0 ALT1 IN>; +- usb-pwr-enable = <&pio35 1 ALT1 OUT>; +- }; +- }; +- }; +- +- usb1 { +- pinctrl_usb1: usb2-1 { +- st,pins { +- usb-oc-detect = <&pio35 2 ALT1 IN>; +- usb-pwr-enable = <&pio35 3 ALT1 OUT>; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stih410.dtsi b/scripts/dtc/include-prefixes/arm/stih410.dtsi +deleted file mode 100644 +index 6d847019c554..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stih410.dtsi ++++ /dev/null +@@ -1,300 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 STMicroelectronics Limited. +- * Author: Peter Griffin +- */ +-#include "stih410-clock.dtsi" +-#include "stih407-family.dtsi" +-#include "stih410-pinctrl.dtsi" +-#include +-/ { +- aliases { +- bdisp0 = &bdisp0; +- }; +- +- soc { +- usb2_picophy1: phy2@0 { +- compatible = "st,stih407-usb2-phy"; +- reg = <0 0>; +- #phy-cells = <0>; +- st,syscfg = <&syscfg_core 0xf8 0xf4>; +- resets = <&softreset STIH407_PICOPHY_SOFTRESET>, +- <&picophyreset STIH407_PICOPHY0_RESET>; +- reset-names = "global", "port"; +- +- status = "disabled"; +- }; +- +- usb2_picophy2: phy3@0 { +- compatible = "st,stih407-usb2-phy"; +- reg = <0 0>; +- #phy-cells = <0>; +- st,syscfg = <&syscfg_core 0xfc 0xf4>; +- resets = <&softreset STIH407_PICOPHY_SOFTRESET>, +- <&picophyreset STIH407_PICOPHY1_RESET>; +- reset-names = "global", "port"; +- +- status = "disabled"; +- }; +- +- ohci0: usb@9a03c00 { +- compatible = "st,st-ohci-300x"; +- reg = <0x9a03c00 0x100>; +- interrupts = ; +- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, +- <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; +- resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, +- <&softreset STIH407_USB2_PORT0_SOFTRESET>; +- reset-names = "power", "softreset"; +- phys = <&usb2_picophy1>; +- phy-names = "usb"; +- +- status = "disabled"; +- }; +- +- ehci0: usb@9a03e00 { +- compatible = "st,st-ehci-300x"; +- reg = <0x9a03e00 0x100>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb0>; +- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, +- <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; +- resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, +- <&softreset STIH407_USB2_PORT0_SOFTRESET>; +- reset-names = "power", "softreset"; +- phys = <&usb2_picophy1>; +- phy-names = "usb"; +- +- status = "disabled"; +- }; +- +- ohci1: usb@9a83c00 { +- compatible = "st,st-ohci-300x"; +- reg = <0x9a83c00 0x100>; +- interrupts = ; +- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, +- <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; +- resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, +- <&softreset STIH407_USB2_PORT1_SOFTRESET>; +- reset-names = "power", "softreset"; +- phys = <&usb2_picophy2>; +- phy-names = "usb"; +- +- status = "disabled"; +- }; +- +- ehci1: usb@9a83e00 { +- compatible = "st,st-ehci-300x"; +- reg = <0x9a83e00 0x100>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb1>; +- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, +- <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; +- resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, +- <&softreset STIH407_USB2_PORT1_SOFTRESET>; +- reset-names = "power", "softreset"; +- phys = <&usb2_picophy2>; +- phy-names = "usb"; +- +- status = "disabled"; +- }; +- +- sti-display-subsystem@0 { +- compatible = "st,sti-display-subsystem"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- reg = <0 0>; +- assigned-clocks = <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 1>, +- <&clk_s_c0_pll1 0>, +- <&clk_s_c0_flexgen CLK_COMPO_DVP>, +- <&clk_s_c0_flexgen CLK_MAIN_DISP>, +- <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, +- <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, +- <&clk_s_d2_flexgen CLK_PIX_GDP1>, +- <&clk_s_d2_flexgen CLK_PIX_GDP2>, +- <&clk_s_d2_flexgen CLK_PIX_GDP3>, +- <&clk_s_d2_flexgen CLK_PIX_GDP4>; +- +- assigned-clock-parents = <0>, +- <0>, +- <0>, +- <&clk_s_c0_pll1 0>, +- <&clk_s_c0_pll1 0>, +- <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 1>, +- <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 0>; +- +- assigned-clock-rates = <297000000>, +- <297000000>, +- <0>, +- <400000000>, +- <400000000>; +- +- ranges; +- +- sti-compositor@9d11000 { +- compatible = "st,stih407-compositor"; +- reg = <0x9d11000 0x1000>; +- +- clock-names = "compo_main", +- "compo_aux", +- "pix_main", +- "pix_aux", +- "pix_gdp1", +- "pix_gdp2", +- "pix_gdp3", +- "pix_gdp4", +- "main_parent", +- "aux_parent"; +- +- clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, +- <&clk_s_c0_flexgen CLK_COMPO_DVP>, +- <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, +- <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, +- <&clk_s_d2_flexgen CLK_PIX_GDP1>, +- <&clk_s_d2_flexgen CLK_PIX_GDP2>, +- <&clk_s_d2_flexgen CLK_PIX_GDP3>, +- <&clk_s_d2_flexgen CLK_PIX_GDP4>, +- <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 1>; +- +- reset-names = "compo-main", "compo-aux"; +- resets = <&softreset STIH407_COMPO_SOFTRESET>, +- <&softreset STIH407_COMPO_SOFTRESET>; +- st,vtg = <&vtg_main>, <&vtg_aux>; +- }; +- +- sti-tvout@8d08000 { +- compatible = "st,stih407-tvout"; +- reg = <0x8d08000 0x1000>; +- reg-names = "tvout-reg"; +- reset-names = "tvout"; +- resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; +- #address-cells = <1>; +- #size-cells = <1>; +- assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, +- <&clk_s_d2_flexgen CLK_TMDS_HDMI>, +- <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, +- <&clk_s_d0_flexgen CLK_PCM_0>, +- <&clk_s_d2_flexgen CLK_PIX_HDDAC>, +- <&clk_s_d2_flexgen CLK_HDDAC>; +- +- assigned-clock-parents = <&clk_s_d2_quadfs 0>, +- <&clk_tmdsout_hdmi>, +- <&clk_s_d2_quadfs 0>, +- <&clk_s_d0_quadfs 0>, +- <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 0>; +- }; +- +- sti_hdmi: sti-hdmi@8d04000 { +- compatible = "st,stih407-hdmi"; +- reg = <0x8d04000 0x1000>; +- reg-names = "hdmi-reg"; +- #sound-dai-cells = <0>; +- interrupts = ; +- interrupt-names = "irq"; +- clock-names = "pix", +- "tmds", +- "phy", +- "audio", +- "main_parent", +- "aux_parent"; +- +- clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, +- <&clk_s_d2_flexgen CLK_TMDS_HDMI>, +- <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, +- <&clk_s_d0_flexgen CLK_PCM_0>, +- <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 1>; +- +- hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; +- reset-names = "hdmi"; +- resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; +- ddc = <&hdmiddc>; +- }; +- +- sti-hda@8d02000 { +- compatible = "st,stih407-hda"; +- status = "disabled"; +- reg = <0x8d02000 0x400>, <0x92b0120 0x4>; +- reg-names = "hda-reg", "video-dacs-ctrl"; +- clock-names = "pix", +- "hddac", +- "main_parent", +- "aux_parent"; +- clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, +- <&clk_s_d2_flexgen CLK_HDDAC>, +- <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 1>; +- }; +- +- sti-hqvdp@9c00000 { +- compatible = "st,stih407-hqvdp"; +- reg = <0x9C00000 0x100000>; +- clock-names = "hqvdp", "pix_main"; +- clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, +- <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>; +- reset-names = "hqvdp"; +- resets = <&softreset STIH407_HDQVDP_SOFTRESET>; +- st,vtg = <&vtg_main>; +- }; +- }; +- +- bdisp0:bdisp@9f10000 { +- compatible = "st,stih407-bdisp"; +- reg = <0x9f10000 0x1000>; +- interrupts = ; +- clock-names = "bdisp"; +- clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>; +- }; +- +- hva@8c85000 { +- compatible = "st,st-hva"; +- reg = <0x8c85000 0x400>, <0x6000000 0x40000>; +- reg-names = "hva_registers", "hva_esram"; +- interrupts = , +- ; +- clock-names = "clk_hva"; +- clocks = <&clk_s_c0_flexgen CLK_HVA>; +- }; +- +- thermal@91a0000 { +- compatible = "st,stih407-thermal"; +- reg = <0x91a0000 0x28>; +- clock-names = "thermal"; +- clocks = <&clk_sysin>; +- interrupts = ; +- }; +- +- delta0@0 { +- compatible = "st,st-delta"; +- clock-names = "delta", +- "delta-st231", +- "delta-flash-promip"; +- clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, +- <&clk_s_c0_flexgen CLK_ST231_DMU>, +- <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; +- }; +- +- sti-cec@94a087c { +- compatible = "st,stih-cec"; +- reg = <0x94a087c 0x64>; +- clocks = <&clk_sysin>; +- clock-names = "cec-clk"; +- interrupts = ; +- interrupt-names = "cec-irq"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_cec0_default>; +- resets = <&softreset STIH407_LPM_SOFTRESET>; +- hdmi-phandle = <&sti_hdmi>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stih418-b2199.dts b/scripts/dtc/include-prefixes/arm/stih418-b2199.dts +deleted file mode 100644 +index b66e2b29edea..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stih418-b2199.dts ++++ /dev/null +@@ -1,109 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 STMicroelectronics (R&D) Limited. +- * Author: Maxime Coquelin +- */ +-/dts-v1/; +-#include "stih418.dtsi" +-#include +-/ { +- model = "STiH418 B2199"; +- compatible = "st,stih418-b2199", "st,stih418"; +- +- chosen { +- stdout-path = &sbc_serial0; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0xc0000000>; +- }; +- +- aliases { +- serial0 = &sbc_serial0; +- ethernet0 = ðernet0; +- }; +- +- leds { +- compatible = "gpio-leds"; +- red { +- label = "Front Panel LED"; +- gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- green { +- gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- soc { +- sbc_serial0: serial@9530000 { +- status = "okay"; +- }; +- +- i2c@9842000 { +- status = "okay"; +- }; +- +- i2c@9843000 { +- status = "okay"; +- }; +- +- i2c@9844000 { +- status = "okay"; +- }; +- +- i2c@9845000 { +- status = "okay"; +- }; +- +- i2c@9540000 { +- status = "okay"; +- }; +- +- /* SSC11 to HDMI */ +- i2c@9541000 { +- status = "okay"; +- /* HDMI V1.3a supports Standard mode only */ +- clock-frequency = <100000>; +- st,i2c-min-scl-pulse-width-us = <0>; +- st,i2c-min-sda-pulse-width-us = <5>; +- }; +- +- mmc1: sdhci@9080000 { +- status = "okay"; +- }; +- +- mmc0: sdhci@9060000 { +- status = "okay"; +- max-frequency = <200000000>; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- sd-uhs-ddr50; +- non-removable; +- }; +- +- miphy28lp_phy: miphy28lp@0 { +- +- phy_port0: port@9b22000 { +- st,osc-rdy; +- }; +- +- phy_port1: port@9b2a000 { +- st,osc-force-ext; +- }; +- }; +- +- st_dwc3: dwc3@8f94000 { +- status = "okay"; +- }; +- +- ethernet0: dwmac@9630000 { +- st,tx-retime-src = "clkgen"; +- status = "okay"; +- phy-mode = "rgmii"; +- fixed-link = <0 1 1000 0 0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stih418-b2264.dts b/scripts/dtc/include-prefixes/arm/stih418-b2264.dts +deleted file mode 100644 +index a99604bebf8c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stih418-b2264.dts ++++ /dev/null +@@ -1,151 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2021 STMicroelectronics +- * Author: Alain Volmat +- */ +-/dts-v1/; +-#include "stih418.dtsi" +-#include +-/ { +- model = "STiH418 B2264"; +- compatible = "st,stih418-b2264", "st,stih418"; +- +- chosen { +- stdout-path = &sbc_serial0; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x40000000 0xc0000000>; +- }; +- +- cpus { +- cpu@0 { +- operating-points-v2 = <&cpu_opp_table>; +- /* u-boot puts hpen in SBC dmem at 0xb8 offset */ +- cpu-release-addr = <0x94100b8>; +- }; +- cpu@1 { +- operating-points-v2 = <&cpu_opp_table>; +- /* u-boot puts hpen in SBC dmem at 0xb8 offset */ +- cpu-release-addr = <0x94100b8>; +- }; +- cpu@2 { +- operating-points-v2 = <&cpu_opp_table>; +- /* u-boot puts hpen in SBC dmem at 0xb8 offset */ +- cpu-release-addr = <0x94100b8>; +- }; +- cpu@3 { +- operating-points-v2 = <&cpu_opp_table>; +- /* u-boot puts hpen in SBC dmem at 0xb8 offset */ +- cpu-release-addr = <0x94100b8>; +- }; +- }; +- +- cpu_opp_table: opp_table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp00 { +- opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <784000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <784000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <784000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <784000>; +- }; +- opp04 { +- opp-hz = /bits/ 64 <1500000000>; +- opp-microvolt = <784000>; +- }; +- }; +- +- aliases { +- ttyAS0 = &sbc_serial0; +- ethernet0 = ðernet0; +- }; +- +- soc { +- leds { +- compatible = "gpio-leds"; +- green { +- gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- pin-controller-sbc@961f080 { +- gmac1 { +- rgmii1-0 { +- st,pins { +- rxd0 = <&pio1 4 ALT1 IN DE_IO 300 CLK_A>; +- rxd1 = <&pio1 5 ALT1 IN DE_IO 300 CLK_A>; +- rxd2 = <&pio1 6 ALT1 IN DE_IO 300 CLK_A>; +- rxd3 = <&pio1 7 ALT1 IN DE_IO 300 CLK_A>; +- rxdv = <&pio2 0 ALT1 IN DE_IO 300 CLK_A>; +- }; +- }; +- }; +- }; +- +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-ðernet0 { +- phy-mode = "rgmii"; +- pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>; +- st,tx-retime-src = "clkgen"; +- +- snps,reset-gpio = <&pio0 7 0>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 1000000>; +- +- status = "okay"; +-}; +- +-&miphy28lp_phy { +- phy_port0: port@9b22000 { +- st,sata-gen = <2>; /* SATA GEN3 */ +- st,osc-rdy; +- }; +-}; +- +-&mmc0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&sata0 { +- status = "okay"; +-}; +- +-&sbc_serial0 { +- status = "okay"; +-}; +- +-&spifsm { +- status = "okay"; +-}; +- +-&st_dwc3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stih418-clock.dtsi b/scripts/dtc/include-prefixes/arm/stih418-clock.dtsi +deleted file mode 100644 +index e84c476b83ed..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stih418-clock.dtsi ++++ /dev/null +@@ -1,220 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 STMicroelectronics R&D Limited +- */ +-#include +-/ { +- /* +- * Fixed 30MHz oscillator inputs to SoC +- */ +- clk_sysin: clk-sysin { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <30000000>; +- clock-output-names = "CLK_SYSIN"; +- }; +- +- clk_tmdsout_hdmi: clk-tmdsout-hdmi { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- compatible = "st,stih418-clk", "simple-bus"; +- +- /* +- * A9 PLL. +- */ +- clockgen-a9@92b0000 { +- compatible = "st,clkgen-c32"; +- reg = <0x92b0000 0xffff>; +- +- clockgen_a9_pll: clockgen-a9-pll { +- #clock-cells = <1>; +- compatible = "st,stih418-clkgen-plla9"; +- +- clocks = <&clk_sysin>; +- }; +- }; +- +- /* +- * ARM CPU related clocks. +- */ +- clk_m_a9: clk-m-a9@92b0000 { +- #clock-cells = <0>; +- compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; +- reg = <0x92b0000 0x10000>; +- +- clocks = <&clockgen_a9_pll 0>, +- <&clockgen_a9_pll 0>, +- <&clk_s_c0_flexgen 13>, +- <&clk_m_a9_ext2f_div2>; +- +- /* +- * ARM Peripheral clock for timers +- */ +- arm_periph_clk: clk-m-a9-periphs { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&clk_m_a9>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- }; +- +- clockgen-a@90ff000 { +- compatible = "st,clkgen-c32"; +- reg = <0x90ff000 0x1000>; +- +- clk_s_a0_pll: clk-s-a0-pll { +- #clock-cells = <1>; +- compatible = "st,clkgen-pll0-a0"; +- +- clocks = <&clk_sysin>; +- }; +- +- clk_s_a0_flexgen: clk-s-a0-flexgen { +- compatible = "st,flexgen", "st,flexgen-stih410-a0"; +- +- #clock-cells = <1>; +- +- clocks = <&clk_s_a0_pll 0>, +- <&clk_sysin>; +- }; +- }; +- +- clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { +- #clock-cells = <1>; +- compatible = "st,quadfs-pll"; +- reg = <0x9103000 0x1000>; +- +- clocks = <&clk_sysin>; +- }; +- +- clk_s_c0: clockgen-c@9103000 { +- compatible = "st,clkgen-c32"; +- reg = <0x9103000 0x1000>; +- +- clk_s_c0_pll0: clk-s-c0-pll0 { +- #clock-cells = <1>; +- compatible = "st,clkgen-pll0-c0"; +- +- clocks = <&clk_sysin>; +- }; +- +- clk_s_c0_pll1: clk-s-c0-pll1 { +- #clock-cells = <1>; +- compatible = "st,clkgen-pll1-c0"; +- +- clocks = <&clk_sysin>; +- }; +- +- clk_s_c0_flexgen: clk-s-c0-flexgen { +- #clock-cells = <1>; +- compatible = "st,flexgen", "st,flexgen-stih418-c0"; +- +- clocks = <&clk_s_c0_pll0 0>, +- <&clk_s_c0_pll1 0>, +- <&clk_s_c0_quadfs 0>, +- <&clk_s_c0_quadfs 1>, +- <&clk_s_c0_quadfs 2>, +- <&clk_s_c0_quadfs 3>, +- <&clk_sysin>; +- +- /* +- * ARM Peripheral clock for timers +- */ +- clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- +- clocks = <&clk_s_c0_flexgen 13>; +- +- clock-output-names = "clk-m-a9-ext2f-div2"; +- +- clock-div = <2>; +- clock-mult = <1>; +- }; +- }; +- }; +- +- clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { +- #clock-cells = <1>; +- compatible = "st,quadfs-d0"; +- reg = <0x9104000 0x1000>; +- +- clocks = <&clk_sysin>; +- }; +- +- clockgen-d0@9104000 { +- compatible = "st,clkgen-c32"; +- reg = <0x9104000 0x1000>; +- +- clk_s_d0_flexgen: clk-s-d0-flexgen { +- #clock-cells = <1>; +- compatible = "st,flexgen", "st,flexgen-stih410-d0"; +- +- clocks = <&clk_s_d0_quadfs 0>, +- <&clk_s_d0_quadfs 1>, +- <&clk_s_d0_quadfs 2>, +- <&clk_s_d0_quadfs 3>, +- <&clk_sysin>; +- }; +- }; +- +- clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { +- #clock-cells = <1>; +- compatible = "st,quadfs-d2"; +- reg = <0x9106000 0x1000>; +- +- clocks = <&clk_sysin>; +- }; +- +- clockgen-d2@9106000 { +- compatible = "st,clkgen-c32"; +- reg = <0x9106000 0x1000>; +- +- clk_s_d2_flexgen: clk-s-d2-flexgen { +- #clock-cells = <1>; +- compatible = "st,flexgen", "st,flexgen-stih418-d2"; +- +- clocks = <&clk_s_d2_quadfs 0>, +- <&clk_s_d2_quadfs 1>, +- <&clk_s_d2_quadfs 2>, +- <&clk_s_d2_quadfs 3>, +- <&clk_sysin>, +- <&clk_sysin>, +- <&clk_tmdsout_hdmi>; +- }; +- }; +- +- clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { +- #clock-cells = <1>; +- compatible = "st,quadfs-d3"; +- reg = <0x9107000 0x1000>; +- +- clocks = <&clk_sysin>; +- }; +- +- clockgen-d3@9107000 { +- compatible = "st,clkgen-c32"; +- reg = <0x9107000 0x1000>; +- +- clk_s_d3_flexgen: clk-s-d3-flexgen { +- #clock-cells = <1>; +- compatible = "st,flexgen", "st,flexgen-stih407-d3"; +- +- clocks = <&clk_s_d3_quadfs 0>, +- <&clk_s_d3_quadfs 1>, +- <&clk_s_d3_quadfs 2>, +- <&clk_s_d3_quadfs 3>, +- <&clk_sysin>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stih418.dtsi b/scripts/dtc/include-prefixes/arm/stih418.dtsi +deleted file mode 100644 +index 97eda4392fbe..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stih418.dtsi ++++ /dev/null +@@ -1,120 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 STMicroelectronics Limited. +- * Author: Peter Griffin +- */ +-#include "stih418-clock.dtsi" +-#include "stih407-family.dtsi" +-#include "stih410-pinctrl.dtsi" +-/ { +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <2>; +- /* u-boot puts hpen in SBC dmem at 0xa4 offset */ +- cpu-release-addr = <0x94100A4>; +- }; +- cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <3>; +- /* u-boot puts hpen in SBC dmem at 0xa4 offset */ +- cpu-release-addr = <0x94100A4>; +- }; +- }; +- +- soc { +- rng11: rng@8a8a000 { +- status = "disabled"; +- }; +- +- usb2_picophy1: phy2@0 { +- compatible = "st,stih407-usb2-phy"; +- reg = <0 0>; +- #phy-cells = <0>; +- st,syscfg = <&syscfg_core 0xf8 0xf4>; +- resets = <&softreset STIH407_PICOPHY_SOFTRESET>, +- <&picophyreset STIH407_PICOPHY0_RESET>; +- reset-names = "global", "port"; +- }; +- +- usb2_picophy2: phy3@0 { +- compatible = "st,stih407-usb2-phy"; +- reg = <0 0>; +- #phy-cells = <0>; +- st,syscfg = <&syscfg_core 0xfc 0xf4>; +- resets = <&softreset STIH407_PICOPHY_SOFTRESET>, +- <&picophyreset STIH407_PICOPHY1_RESET>; +- reset-names = "global", "port"; +- }; +- +- ohci0: usb@9a03c00 { +- compatible = "st,st-ohci-300x"; +- reg = <0x9a03c00 0x100>; +- interrupts = ; +- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; +- resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, +- <&softreset STIH407_USB2_PORT0_SOFTRESET>; +- reset-names = "power", "softreset"; +- phys = <&usb2_picophy1>; +- phy-names = "usb"; +- }; +- +- ehci0: usb@9a03e00 { +- compatible = "st,st-ehci-300x"; +- reg = <0x9a03e00 0x100>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb0>; +- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; +- resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, +- <&softreset STIH407_USB2_PORT0_SOFTRESET>; +- reset-names = "power", "softreset"; +- phys = <&usb2_picophy1>; +- phy-names = "usb"; +- }; +- +- ohci1: usb@9a83c00 { +- compatible = "st,st-ohci-300x"; +- reg = <0x9a83c00 0x100>; +- interrupts = ; +- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; +- resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, +- <&softreset STIH407_USB2_PORT1_SOFTRESET>; +- reset-names = "power", "softreset"; +- phys = <&usb2_picophy2>; +- phy-names = "usb"; +- }; +- +- ehci1: usb@9a83e00 { +- compatible = "st,st-ehci-300x"; +- reg = <0x9a83e00 0x100>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb1>; +- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; +- resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, +- <&softreset STIH407_USB2_PORT1_SOFTRESET>; +- reset-names = "power", "softreset"; +- phys = <&usb2_picophy2>; +- phy-names = "usb"; +- }; +- +- mmc0: sdhci@9060000 { +- assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>; +- assigned-clock-parents = <&clk_s_c0_pll1 0>; +- assigned-clock-rates = <200000000>; +- }; +- +- thermal@91a0000 { +- compatible = "st,stih407-thermal"; +- reg = <0x91a0000 0x28>; +- clock-names = "thermal"; +- clocks = <&clk_sysin>; +- interrupts = ; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stihxxx-b2120.dtsi b/scripts/dtc/include-prefixes/arm/stihxxx-b2120.dtsi +deleted file mode 100644 +index d051f080e52e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stihxxx-b2120.dtsi ++++ /dev/null +@@ -1,206 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2014 STMicroelectronics (R&D) Limited. +- * Author: Giuseppe Cavallaro +- */ +-#include +-#include +-#include +-/ { +- leds { +- compatible = "gpio-leds"; +- red { +- label = "Front Panel LED"; +- gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- green { +- gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- sound: sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "STI-B2120"; +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- simple-audio-card,dai-link@0 { +- reg = <0>; +- /* HDMI */ +- format = "i2s"; +- mclk-fs = <128>; +- cpu { +- sound-dai = <&sti_uni_player0>; +- }; +- +- codec { +- sound-dai = <&sti_hdmi>; +- }; +- }; +- +- simple-audio-card,dai-link@1 { +- reg = <1>; +- /* DAC */ +- format = "i2s"; +- mclk-fs = <256>; +- frame-inversion; +- cpu { +- sound-dai = <&sti_uni_player2>; +- }; +- +- codec { +- sound-dai = <&sti_sasg_codec 1>; +- }; +- }; +- +- simple-audio-card,dai-link@2 { +- reg = <2>; +- /* SPDIF */ +- format = "left_j"; +- mclk-fs = <128>; +- cpu { +- sound-dai = <&sti_uni_player3>; +- }; +- +- codec { +- sound-dai = <&sti_sasg_codec 0>; +- }; +- }; +- }; +- +- soc { +- sbc_serial0: serial@9530000 { +- status = "okay"; +- }; +- +- pwm0: pwm@9810000 { +- status = "okay"; +- }; +- +- pwm1: pwm@9510000 { +- status = "okay"; +- }; +- +- ssc2: i2c@9842000 { +- status = "okay"; +- clock-frequency = <100000>; +- st,i2c-min-scl-pulse-width-us = <0>; +- st,i2c-min-sda-pulse-width-us = <5>; +- }; +- +- ssc3: i2c@9843000 { +- status = "okay"; +- clock-frequency = <100000>; +- st,i2c-min-scl-pulse-width-us = <0>; +- st,i2c-min-sda-pulse-width-us = <5>; +- }; +- +- i2c@9844000 { +- status = "okay"; +- }; +- +- i2c@9845000 { +- status = "okay"; +- }; +- +- i2c@9540000 { +- status = "okay"; +- }; +- +- mmc0: sdhci@9060000 { +- non-removable; +- status = "okay"; +- }; +- +- mmc1: sdhci@9080000 { +- status = "okay"; +- }; +- +- /* SSC11 to HDMI */ +- hdmiddc: i2c@9541000 { +- status = "okay"; +- /* HDMI V1.3a supports Standard mode only */ +- clock-frequency = <100000>; +- st,i2c-min-scl-pulse-width-us = <0>; +- st,i2c-min-sda-pulse-width-us = <5>; +- }; +- +- miphy28lp_phy: miphy28lp@0 { +- +- phy_port0: port@9b22000 { +- st,osc-rdy; +- }; +- +- phy_port1: port@9b2a000 { +- st,osc-force-ext; +- }; +- }; +- +- st_dwc3: dwc3@8f94000 { +- status = "okay"; +- }; +- +- ethernet0: dwmac@9630000 { +- st,tx-retime-src = "clkgen"; +- status = "okay"; +- phy-mode = "rgmii"; +- fixed-link = <0 1 1000 0 0>; +- }; +- +- demux@8a20000 { +- compatible = "st,stih407-c8sectpfe"; +- status = "okay"; +- reg = <0x08a20000 0x10000>, +- <0x08a00000 0x4000>; +- reg-names = "c8sectpfe", "c8sectpfe-ram"; +- interrupts = , +- ; +- interrupt-names = "c8sectpfe-error-irq", +- "c8sectpfe-idle-irq"; +- pinctrl-0 = <&pinctrl_tsin0_serial>; +- pinctrl-1 = <&pinctrl_tsin0_parallel>; +- pinctrl-2 = <&pinctrl_tsin3_serial>; +- pinctrl-3 = <&pinctrl_tsin4_serial_alt3>; +- pinctrl-4 = <&pinctrl_tsin5_serial_alt1>; +- pinctrl-names = "tsin0-serial", +- "tsin0-parallel", +- "tsin3-serial", +- "tsin4-serial", +- "tsin5-serial"; +- clocks = <&clk_s_c0_flexgen CLK_PROC_STFE>; +- clock-names = "c8sectpfe"; +- +- /* tsin0 is TSA on NIMA */ +- tsin0: port { +- tsin-num = <0>; +- serial-not-parallel; +- i2c-bus = <&ssc2>; +- reset-gpios = <&pio15 4 GPIO_ACTIVE_HIGH>; +- dvb-card = ; +- }; +- }; +- +- sti_uni_player0: sti-uni-player@8d80000 { +- status = "okay"; +- }; +- +- sti_uni_player2: sti-uni-player@8d82000 { +- status = "okay"; +- }; +- +- sti_uni_player3: sti-uni-player@8d85000 { +- status = "okay"; +- }; +- +- syscfg_core: core-syscfg@92b0000 { +- sti_sasg_codec: sti-sasg-codec { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spdif_out>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32429i-eval.dts b/scripts/dtc/include-prefixes/arm/stm32429i-eval.dts +deleted file mode 100644 +index cb46326a8c75..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32429i-eval.dts ++++ /dev/null +@@ -1,324 +0,0 @@ +-/* +- * Copyright 2015 - Maxime Coquelin +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "stm32f429.dtsi" +-#include "stm32f429-pinctrl.dtsi" +-#include +-#include +- +-/ { +- model = "STMicroelectronics STM32429i-EVAL board"; +- compatible = "st,stm32429i-eval", "st,stm32f429"; +- +- chosen { +- bootargs = "root=/dev/ram"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x2000000>; +- }; +- +- aliases { +- serial0 = &usart1; +- }; +- +- clocks { +- clk_ext_camera: clk-ext-camera { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- }; +- +- soc { +- dma-ranges = <0xc0000000 0x0 0x10000000>; +- }; +- +- vdda: regulator-vdda { +- compatible = "regulator-fixed"; +- regulator-name = "vdda"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vref: regulator-vref { +- compatible = "regulator-fixed"; +- regulator-name = "vref"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vdd_panel: vdd-panel { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_panel"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-green { +- gpios = <&gpiog 6 1>; +- linux,default-trigger = "heartbeat"; +- }; +- led-orange { +- gpios = <&gpiog 7 1>; +- }; +- led-red { +- gpios = <&gpiog 10 1>; +- }; +- led-blue { +- gpios = <&gpiog 12 1>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- button-0 { +- label = "Wake up"; +- linux,code = ; +- gpios = <&gpioa 0 0>; +- }; +- button-1 { +- label = "Tamper"; +- linux,code = ; +- gpios = <&gpioc 13 0>; +- }; +- }; +- +- usbotg_hs_phy: usbphy { +- #phy-cells = <0>; +- compatible = "usb-nop-xceiv"; +- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>; +- clock-names = "main_clk"; +- }; +- +- panel_rgb: panel-rgb { +- compatible = "ampire,am-480272h3tmqw-t01h"; +- power-supply = <&vdd_panel>; +- status = "okay"; +- port { +- panel_in_rgb: endpoint { +- remote-endpoint = <<dc_out_rgb>; +- }; +- }; +- }; +- +- mmc_vcard: mmc_vcard { +- compatible = "regulator-fixed"; +- regulator-name = "mmc_vcard"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&adc { +- pinctrl-names = "default"; +- pinctrl-0 = <&adc3_in8_pin>; +- vdda-supply = <&vdda>; +- vref-supply = <&vref>; +- status = "okay"; +- adc3: adc@200 { +- st,adc-channels = <8>; +- status = "okay"; +- }; +-}; +- +-&clk_hse { +- clock-frequency = <25000000>; +-}; +- +-&crc { +- status = "okay"; +-}; +- +-&dcmi { +- status = "okay"; +- +- port { +- dcmi_0: endpoint { +- remote-endpoint = <&ov2640_0>; +- bus-type = <5>; +- bus-width = <8>; +- hsync-active = <0>; +- vsync-active = <0>; +- pclk-sample = <1>; +- }; +- }; +-}; +- +-&i2c1 { +- pinctrl-0 = <&i2c1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- ov2640: camera@30 { +- compatible = "ovti,ov2640"; +- reg = <0x30>; +- resetb-gpios = <&stmpegpio 2 GPIO_ACTIVE_HIGH>; +- pwdn-gpios = <&stmpegpio 0 GPIO_ACTIVE_LOW>; +- clocks = <&clk_ext_camera>; +- clock-names = "xvclk"; +- status = "okay"; +- +- port { +- ov2640_0: endpoint { +- remote-endpoint = <&dcmi_0>; +- }; +- }; +- }; +- +- stmpe1600: stmpe1600@42 { +- compatible = "st,stmpe1600"; +- reg = <0x42>; +- interrupts = <8 3>; +- interrupt-parent = <&gpioi>; +- interrupt-controller; +- wakeup-source; +- +- stmpegpio: stmpe_gpio { +- compatible = "st,stmpe-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +-}; +- +-&iwdg { +- status = "okay"; +- timeout-sec = <32>; +-}; +- +-<dc { +- status = "okay"; +- pinctrl-0 = <<dc_pins_a>; +- pinctrl-names = "default"; +- +- port { +- ltdc_out_rgb: endpoint { +- remote-endpoint = <&panel_in_rgb>; +- }; +- }; +-}; +- +-&mac { +- status = "okay"; +- pinctrl-0 = <ðernet_mii>; +- pinctrl-names = "default"; +- phy-mode = "mii"; +- phy-handle = <&phy1>; +- mdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +- }; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&sdio { +- status = "okay"; +- vmmc-supply = <&mmc_vcard>; +- cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default", "opendrain"; +- pinctrl-0 = <&sdio_pins>; +- pinctrl-1 = <&sdio_pins_od>; +- bus-width = <4>; +- max-frequency = <12500000>; +-}; +- +-&timers1 { +- status = "okay"; +- +- pwm { +- pinctrl-0 = <&pwm1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- +- timer@0 { +- status = "okay"; +- }; +-}; +- +-&timers3 { +- status = "okay"; +- +- pwm { +- pinctrl-0 = <&pwm3_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- +- timer@2 { +- status = "okay"; +- }; +-}; +- +-&usart1 { +- pinctrl-0 = <&usart1_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&usbotg_hs { +- dr_mode = "host"; +- phys = <&usbotg_hs_phy>; +- phy-names = "usb2-phy"; +- pinctrl-0 = <&usbotg_hs_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32746g-eval.dts b/scripts/dtc/include-prefixes/arm/stm32746g-eval.dts +deleted file mode 100644 +index 327613fd9666..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32746g-eval.dts ++++ /dev/null +@@ -1,210 +0,0 @@ +-/* +- * Copyright 2015 - Maxime Coquelin +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "stm32f746.dtsi" +-#include "stm32f746-pinctrl.dtsi" +-#include +-#include +- +-/ { +- model = "STMicroelectronics STM32746g-EVAL board"; +- compatible = "st,stm32746g-eval", "st,stm32f746"; +- +- chosen { +- bootargs = "root=/dev/ram"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@c0000000 { +- device_type = "memory"; +- reg = <0xc0000000 0x2000000>; +- }; +- +- aliases { +- serial0 = &usart1; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-green { +- gpios = <&gpiof 10 1>; +- linux,default-trigger = "heartbeat"; +- }; +- led-orange { +- gpios = <&stmfx_pinctrl 17 1>; +- }; +- led-red { +- gpios = <&gpiob 7 1>; +- }; +- led-blue { +- gpios = <&stmfx_pinctrl 19 1>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- button-0 { +- label = "Wake up"; +- linux,code = ; +- gpios = <&gpioc 13 0>; +- }; +- }; +- +- joystick { +- compatible = "gpio-keys"; +- pinctrl-0 = <&joystick_pins>; +- pinctrl-names = "default"; +- button-0 { +- label = "JoySel"; +- linux,code = ; +- interrupt-parent = <&stmfx_pinctrl>; +- interrupts = <0 IRQ_TYPE_EDGE_FALLING>; +- }; +- button-1 { +- label = "JoyDown"; +- linux,code = ; +- interrupt-parent = <&stmfx_pinctrl>; +- interrupts = <1 IRQ_TYPE_EDGE_FALLING>; +- }; +- button-2 { +- label = "JoyLeft"; +- linux,code = ; +- interrupt-parent = <&stmfx_pinctrl>; +- interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +- }; +- button-3 { +- label = "JoyRight"; +- linux,code = ; +- interrupt-parent = <&stmfx_pinctrl>; +- interrupts = <3 IRQ_TYPE_EDGE_FALLING>; +- }; +- button-4 { +- label = "JoyUp"; +- linux,code = ; +- interrupt-parent = <&stmfx_pinctrl>; +- interrupts = <4 IRQ_TYPE_EDGE_FALLING>; +- }; +- }; +- +- usbotg_hs_phy: usb-phy { +- #phy-cells = <0>; +- compatible = "usb-nop-xceiv"; +- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; +- clock-names = "main_clk"; +- }; +- +- mmc_vcard: mmc_vcard { +- compatible = "regulator-fixed"; +- regulator-name = "mmc_vcard"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&clk_hse { +- clock-frequency = <25000000>; +-}; +- +-&crc { +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-0 = <&i2c1_pins_b>; +- pinctrl-names = "default"; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- +- stmfx: stmfx@42 { +- compatible = "st,stmfx-0300"; +- reg = <0x42>; +- interrupts = <8 IRQ_TYPE_EDGE_RISING>; +- interrupt-parent = <&gpioi>; +- +- stmfx_pinctrl: pinctrl { +- compatible = "st,stmfx-0300-pinctrl"; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&stmfx_pinctrl 0 0 24>; +- +- joystick_pins: joystick { +- pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; +- drive-push-pull; +- bias-pull-up; +- }; +- }; +- }; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&sdio1 { +- status = "okay"; +- vmmc-supply = <&mmc_vcard>; +- broken-cd; +- pinctrl-names = "default", "opendrain"; +- pinctrl-0 = <&sdio_pins_a>; +- pinctrl-1 = <&sdio_pins_od_a>; +- bus-width = <4>; +-}; +- +-&usart1 { +- pinctrl-0 = <&usart1_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&usbotg_hs { +- dr_mode = "otg"; +- phys = <&usbotg_hs_phy>; +- phy-names = "usb2-phy"; +- pinctrl-0 = <&usbotg_hs_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32f4-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/stm32f4-pinctrl.dtsi +deleted file mode 100644 +index 155d9ffacc83..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32f4-pinctrl.dtsi ++++ /dev/null +@@ -1,453 +0,0 @@ +-/* +- * Copyright 2017 - Alexandre Torgue +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +- +-/ { +- soc { +- pinctrl: pin-controller@40020000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x40020000 0x3000>; +- interrupt-parent = <&exti>; +- st,syscfg = <&syscfg 0x8>; +- pins-are-numbered; +- +- gpioa: gpio@40020000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x0 0x400>; +- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>; +- st,bank-name = "GPIOA"; +- }; +- +- gpiob: gpio@40020400 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x400 0x400>; +- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>; +- st,bank-name = "GPIOB"; +- }; +- +- gpioc: gpio@40020800 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x800 0x400>; +- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>; +- st,bank-name = "GPIOC"; +- }; +- +- gpiod: gpio@40020c00 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0xc00 0x400>; +- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>; +- st,bank-name = "GPIOD"; +- }; +- +- gpioe: gpio@40021000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x1000 0x400>; +- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>; +- st,bank-name = "GPIOE"; +- }; +- +- gpiof: gpio@40021400 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x1400 0x400>; +- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>; +- st,bank-name = "GPIOF"; +- }; +- +- gpiog: gpio@40021800 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x1800 0x400>; +- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>; +- st,bank-name = "GPIOG"; +- }; +- +- gpioh: gpio@40021c00 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x1c00 0x400>; +- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>; +- st,bank-name = "GPIOH"; +- }; +- +- gpioi: gpio@40022000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x2000 0x400>; +- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>; +- st,bank-name = "GPIOI"; +- }; +- +- gpioj: gpio@40022400 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x2400 0x400>; +- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>; +- st,bank-name = "GPIOJ"; +- }; +- +- gpiok: gpio@40022800 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x2800 0x400>; +- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>; +- st,bank-name = "GPIOK"; +- }; +- +- usart1_pins_a: usart1-0 { +- pins1 { +- pinmux = ; /* USART1_TX */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = ; /* USART1_RX */ +- bias-disable; +- }; +- }; +- +- usart3_pins_a: usart3-0 { +- pins1 { +- pinmux = ; /* USART3_TX */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = ; /* USART3_RX */ +- bias-disable; +- }; +- }; +- +- usbotg_fs_pins_a: usbotg-fs-0 { +- pins { +- pinmux = , /* OTG_FS_ID */ +- , /* OTG_FS_DM */ +- ; /* OTG_FS_DP */ +- bias-disable; +- drive-push-pull; +- slew-rate = <2>; +- }; +- }; +- +- usbotg_fs_pins_b: usbotg-fs-1 { +- pins { +- pinmux = , /* OTG_HS_ID */ +- , /* OTG_HS_DM */ +- ; /* OTG_HS_DP */ +- bias-disable; +- drive-push-pull; +- slew-rate = <2>; +- }; +- }; +- +- usbotg_hs_pins_a: usbotg-hs-0 { +- pins { +- pinmux = , /* OTG_HS_ULPI_NXT*/ +- , /* OTG_HS_ULPI_DIR */ +- , /* OTG_HS_ULPI_STP */ +- , /* OTG_HS_ULPI_CK */ +- , /* OTG_HS_ULPI_D0 */ +- , /* OTG_HS_ULPI_D1 */ +- , /* OTG_HS_ULPI_D2 */ +- , /* OTG_HS_ULPI_D3 */ +- , /* OTG_HS_ULPI_D4 */ +- , /* OTG_HS_ULPI_D5 */ +- , /* OTG_HS_ULPI_D6 */ +- ; /* OTG_HS_ULPI_D7 */ +- bias-disable; +- drive-push-pull; +- slew-rate = <2>; +- }; +- }; +- +- ethernet_mii: mii-0 { +- pins { +- pinmux = , /* ETH_MII_TXD0_ETH_RMII_TXD0 */ +- , /* ETH_MII_TXD1_ETH_RMII_TXD1 */ +- , /* ETH_MII_TXD2 */ +- , /* ETH_MII_TXD3 */ +- , /* ETH_MII_TX_CLK */ +- , /* ETH_MII_TX_EN_ETH_RMII_TX_EN */ +- , /* ETH_MDIO */ +- , /* ETH_MDC */ +- , /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */ +- , /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */ +- , /* ETH_MII_RXD0_ETH_RMII_RXD0 */ +- , /* ETH_MII_RXD1_ETH_RMII_RXD1 */ +- , /* ETH_MII_RXD2 */ +- ; /* ETH_MII_RXD3 */ +- slew-rate = <2>; +- }; +- }; +- +- adc3_in8_pin: adc-200 { +- pins { +- pinmux = ; +- }; +- }; +- +- pwm1_pins: pwm1-0 { +- pins { +- pinmux = , /* TIM1_CH1 */ +- , /* TIM1_CH1N */ +- ; /* TIM1_BKIN */ +- }; +- }; +- +- pwm3_pins: pwm3-0 { +- pins { +- pinmux = , /* TIM3_CH1 */ +- ; /* TIM3_CH2 */ +- }; +- }; +- +- i2c1_pins: i2c1-0 { +- pins { +- pinmux = , /* I2C1_SDA */ +- ; /* I2C1_SCL */ +- bias-disable; +- drive-open-drain; +- slew-rate = <3>; +- }; +- }; +- +- ltdc_pins_a: ltdc-0 { +- pins { +- pinmux = , /* LCD_HSYNC */ +- , /* LCD_VSYNC */ +- , /* LCD_CLK */ +- , /* LCD_R0 */ +- , /* LCD_R1 */ +- , /* LCD_R2 */ +- , /* LCD_R3 */ +- , /* LCD_R4 */ +- , /* LCD_R5 */ +- , /* LCD_R6*/ +- , /* LCD_R7 */ +- , /* LCD_G0 */ +- , /* LCD_G1 */ +- , /* LCD_G2 */ +- , /* LCD_G3 */ +- , /* LCD_G4 */ +- , /* LCD_B0 */ +- , /* LCD_B1 */ +- , /* LCD_B2 */ +- , /* LCD_B3*/ +- , /* LCD_G5 */ +- , /* LCD_G6 */ +- , /* LCD_G7 */ +- , /* LCD_B4 */ +- , /* LCD_B5 */ +- , /* LCD_B6 */ +- , /* LCD_B7 */ +- ; /* LCD_DE */ +- slew-rate = <2>; +- }; +- }; +- +- ltdc_pins_b: ltdc-1 { +- pins { +- pinmux = , +- /* LCD_HSYNC */ +- , +- /* LCD_VSYNC */ +- , +- /* LCD_CLK */ +- , +- /* LCD_R2 */ +- , +- /* LCD_R3 */ +- , +- /* LCD_R4 */ +- , +- /* LCD_R5 */ +- , +- /* LCD_R6*/ +- , +- /* LCD_R7 */ +- , +- /* LCD_G2 */ +- , +- /* LCD_G3 */ +- , +- /* LCD_G4 */ +- , +- /* LCD_B2 */ +- , +- /* LCD_B3*/ +- , +- /* LCD_G5 */ +- , +- /* LCD_G6 */ +- , +- /* LCD_G7 */ +- , +- /* LCD_B4 */ +- , +- /* LCD_B5 */ +- , +- /* LCD_B6 */ +- , +- /* LCD_B7 */ +- ; +- /* LCD_DE */ +- slew-rate = <2>; +- }; +- }; +- +- spi5_pins: spi5-0 { +- pins1 { +- pinmux = , +- /* SPI5_CLK */ +- ; +- /* SPI5_MOSI */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = ; +- /* SPI5_MISO */ +- bias-disable; +- }; +- }; +- +- i2c3_pins: i2c3-0 { +- pins { +- pinmux = , +- /* I2C3_SDA */ +- ; +- /* I2C3_SCL */ +- bias-disable; +- drive-open-drain; +- slew-rate = <3>; +- }; +- }; +- +- dcmi_pins: dcmi-0 { +- pins { +- pinmux = , /* DCMI_HSYNC */ +- , /* DCMI_VSYNC */ +- , /* DCMI_PIXCLK */ +- , /* DCMI_D0 */ +- , /* DCMI_D1 */ +- , /* DCMI_D2 */ +- , /* DCMI_D3 */ +- , /*DCMI_D4 */ +- , /* DCMI_D5 */ +- , /* DCMI_D6 */ +- , /* DCMI_D7 */ +- , /* DCMI_D8 */ +- , /* DCMI_D9 */ +- , /* DCMI_D10 */ +- ; /* DCMI_D11 */ +- bias-disable; +- drive-push-pull; +- slew-rate = <3>; +- }; +- }; +- +- sdio_pins: sdio-pins-0 { +- pins { +- pinmux = , /* SDIO_D0 */ +- , /* SDIO_D1 */ +- , /* SDIO_D2 */ +- , /* SDIO_D3 */ +- , /* SDIO_CK */ +- ; /* SDIO_CMD */ +- drive-push-pull; +- slew-rate = <2>; +- }; +- }; +- +- sdio_pins_od: sdio-pins-od-0 { +- pins1 { +- pinmux = , /* SDIO_D0 */ +- , /* SDIO_D1 */ +- , /* SDIO_D2 */ +- , /* SDIO_D3 */ +- ; /* SDIO_CK */ +- drive-push-pull; +- slew-rate = <2>; +- }; +- +- pins2 { +- pinmux = ; /* SDIO_CMD */ +- drive-open-drain; +- slew-rate = <2>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32f429-disco.dts b/scripts/dtc/include-prefixes/arm/stm32f429-disco.dts +deleted file mode 100644 +index 6435e099c632..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32f429-disco.dts ++++ /dev/null +@@ -1,220 +0,0 @@ +-/* +- * Copyright 2015 - Maxime Coquelin +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "stm32f429.dtsi" +-#include "stm32f429-pinctrl.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "STMicroelectronics STM32F429i-DISCO board"; +- compatible = "st,stm32f429i-disco", "st,stm32f429"; +- +- chosen { +- bootargs = "root=/dev/ram"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@90000000 { +- device_type = "memory"; +- reg = <0x90000000 0x800000>; +- }; +- +- aliases { +- serial0 = &usart1; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-red { +- gpios = <&gpiog 14 0>; +- }; +- led-green { +- gpios = <&gpiog 13 0>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- button-0 { +- label = "User"; +- linux,code = ; +- gpios = <&gpioa 0 0>; +- }; +- }; +- +- /* This turns on vbus for otg for host mode (dwc2) */ +- vcc5v_otg: vcc5v-otg-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpioc 4 0>; +- regulator-name = "vcc5_host1"; +- regulator-always-on; +- }; +-}; +- +-&clk_hse { +- clock-frequency = <8000000>; +-}; +- +-&crc { +- status = "okay"; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- clock-frequency = <100000>; +- status = "okay"; +- +- stmpe811@41 { +- compatible = "st,stmpe811"; +- reg = <0x41>; +- interrupts = <15 IRQ_TYPE_EDGE_FALLING>; +- interrupt-parent = <&gpioa>; +- /* 3.25 MHz ADC clock speed */ +- st,adc-freq = <1>; +- /* 12-bit ADC */ +- st,mod-12b = <1>; +- /* internal ADC reference */ +- st,ref-sel = <0>; +- /* ADC converstion time: 80 clocks */ +- st,sample-time = <4>; +- +- stmpe_touchscreen { +- compatible = "st,stmpe-ts"; +- /* 8 sample average control */ +- st,ave-ctrl = <3>; +- /* 7 length fractional part in z */ +- st,fraction-z = <7>; +- /* +- * 50 mA typical 80 mA max touchscreen drivers +- * current limit value +- */ +- st,i-drive = <1>; +- /* 1 ms panel driver settling time */ +- st,settling = <3>; +- /* 5 ms touch detect interrupt delay */ +- st,touch-det-delay = <5>; +- }; +- +- stmpe_adc { +- compatible = "st,stmpe-adc"; +- /* forbid to use ADC channels 3-0 (touch) */ +- st,norequest-mask = <0x0F>; +- }; +- }; +-}; +- +-<dc { +- status = "okay"; +- pinctrl-0 = <<dc_pins_b>; +- pinctrl-names = "default"; +- +- port { +- ltdc_out_rgb: endpoint { +- remote-endpoint = <&panel_in_rgb>; +- }; +- }; +-}; +- +-&rtc { +- assigned-clocks = <&rcc 1 CLK_RTC>; +- assigned-clock-parents = <&rcc 1 CLK_LSI>; +- status = "okay"; +-}; +- +-&spi5 { +- status = "okay"; +- pinctrl-0 = <&spi5_pins>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- cs-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>, <&gpioc 2 GPIO_ACTIVE_LOW>; +- +- l3gd20: l3gd20@0 { +- compatible = "st,l3gd20-gyro"; +- spi-max-frequency = <10000000>; +- st,drdy-int-pin = <2>; +- interrupt-parent = <&gpioa>; +- interrupts = <1 IRQ_TYPE_EDGE_RISING>, +- <2 IRQ_TYPE_EDGE_RISING>; +- reg = <0>; +- status = "okay"; +- }; +- +- display: display@1{ +- /* Connect panel-ilitek-9341 to ltdc */ +- compatible = "st,sf-tc240t-9370-t", "ilitek,ili9341"; +- reg = <1>; +- spi-3wire; +- spi-max-frequency = <10000000>; +- dc-gpios = <&gpiod 13 0>; +- port { +- panel_in_rgb: endpoint { +- remote-endpoint = <<dc_out_rgb>; +- }; +- }; +- }; +-}; +- +-&usart1 { +- pinctrl-0 = <&usart1_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&usbotg_hs { +- compatible = "st,stm32f4x9-fsotg"; +- dr_mode = "host"; +- pinctrl-0 = <&usbotg_fs_pins_b>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32f429-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/stm32f429-pinctrl.dtsi +deleted file mode 100644 +index e10d7a1f3207..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32f429-pinctrl.dtsi ++++ /dev/null +@@ -1,91 +0,0 @@ +-/* +- * Copyright 2017 - Alexandre Torgue +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "stm32f4-pinctrl.dtsi" +- +-&pinctrl { +- compatible = "st,stm32f429-pinctrl"; +- +- gpioa: gpio@40020000 { +- gpio-ranges = <&pinctrl 0 0 16>; +- }; +- +- gpiob: gpio@40020400 { +- gpio-ranges = <&pinctrl 0 16 16>; +- }; +- +- gpioc: gpio@40020800 { +- gpio-ranges = <&pinctrl 0 32 16>; +- }; +- +- gpiod: gpio@40020c00 { +- gpio-ranges = <&pinctrl 0 48 16>; +- }; +- +- gpioe: gpio@40021000 { +- gpio-ranges = <&pinctrl 0 64 16>; +- }; +- +- gpiof: gpio@40021400 { +- gpio-ranges = <&pinctrl 0 80 16>; +- }; +- +- gpiog: gpio@40021800 { +- gpio-ranges = <&pinctrl 0 96 16>; +- }; +- +- gpioh: gpio@40021c00 { +- gpio-ranges = <&pinctrl 0 112 16>; +- }; +- +- gpioi: gpio@40022000 { +- gpio-ranges = <&pinctrl 0 128 16>; +- }; +- +- gpioj: gpio@40022400 { +- gpio-ranges = <&pinctrl 0 144 16>; +- }; +- +- gpiok: gpio@40022800 { +- gpio-ranges = <&pinctrl 0 160 8>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32f429.dtsi b/scripts/dtc/include-prefixes/arm/stm32f429.dtsi +deleted file mode 100644 +index 8748d5850298..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32f429.dtsi ++++ /dev/null +@@ -1,806 +0,0 @@ +-/* +- * Copyright 2015 - Maxime Coquelin +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "armv7-m.dtsi" +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- clocks { +- clk_hse: clk-hse { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- clk_lse: clk-lse { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- clk_lsi: clk-lsi { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32000>; +- }; +- +- clk_i2s_ckin: i2s-ckin { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- }; +- +- soc { +- romem: efuse@1fff7800 { +- compatible = "st,stm32f4-otp"; +- reg = <0x1fff7800 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- ts_cal1: calib@22c { +- reg = <0x22c 0x2>; +- }; +- ts_cal2: calib@22e { +- reg = <0x22e 0x2>; +- }; +- }; +- +- timer2: timer@40000000 { +- compatible = "st,stm32-timer"; +- reg = <0x40000000 0x400>; +- interrupts = <28>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; +- status = "disabled"; +- }; +- +- timers2: timers@40000000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40000000 0x400>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@1 { +- compatible = "st,stm32-timer-trigger"; +- reg = <1>; +- status = "disabled"; +- }; +- }; +- +- timer3: timer@40000400 { +- compatible = "st,stm32-timer"; +- reg = <0x40000400 0x400>; +- interrupts = <29>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; +- status = "disabled"; +- }; +- +- timers3: timers@40000400 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40000400 0x400>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@2 { +- compatible = "st,stm32-timer-trigger"; +- reg = <2>; +- status = "disabled"; +- }; +- }; +- +- timer4: timer@40000800 { +- compatible = "st,stm32-timer"; +- reg = <0x40000800 0x400>; +- interrupts = <30>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; +- status = "disabled"; +- }; +- +- timers4: timers@40000800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40000800 0x400>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@3 { +- compatible = "st,stm32-timer-trigger"; +- reg = <3>; +- status = "disabled"; +- }; +- }; +- +- timer5: timer@40000c00 { +- compatible = "st,stm32-timer"; +- reg = <0x40000c00 0x400>; +- interrupts = <50>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; +- }; +- +- timers5: timers@40000c00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40000C00 0x400>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@4 { +- compatible = "st,stm32-timer-trigger"; +- reg = <4>; +- status = "disabled"; +- }; +- }; +- +- timer6: timer@40001000 { +- compatible = "st,stm32-timer"; +- reg = <0x40001000 0x400>; +- interrupts = <54>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; +- status = "disabled"; +- }; +- +- timers6: timers@40001000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40001000 0x400>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; +- clock-names = "int"; +- status = "disabled"; +- +- timer@5 { +- compatible = "st,stm32-timer-trigger"; +- reg = <5>; +- status = "disabled"; +- }; +- }; +- +- timer7: timer@40001400 { +- compatible = "st,stm32-timer"; +- reg = <0x40001400 0x400>; +- interrupts = <55>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; +- status = "disabled"; +- }; +- +- timers7: timers@40001400 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40001400 0x400>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; +- clock-names = "int"; +- status = "disabled"; +- +- timer@6 { +- compatible = "st,stm32-timer-trigger"; +- reg = <6>; +- status = "disabled"; +- }; +- }; +- +- timers12: timers@40001800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40001800 0x400>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@11 { +- compatible = "st,stm32-timer-trigger"; +- reg = <11>; +- status = "disabled"; +- }; +- }; +- +- timers13: timers@40001c00 { +- compatible = "st,stm32-timers"; +- reg = <0x40001C00 0x400>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- }; +- +- timers14: timers@40002000 { +- compatible = "st,stm32-timers"; +- reg = <0x40002000 0x400>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- }; +- +- rtc: rtc@40002800 { +- compatible = "st,stm32-rtc"; +- reg = <0x40002800 0x400>; +- clocks = <&rcc 1 CLK_RTC>; +- assigned-clocks = <&rcc 1 CLK_RTC>; +- assigned-clock-parents = <&rcc 1 CLK_LSE>; +- interrupt-parent = <&exti>; +- interrupts = <17 1>; +- st,syscfg = <&pwrcfg 0x00 0x100>; +- status = "disabled"; +- }; +- +- iwdg: watchdog@40003000 { +- compatible = "st,stm32-iwdg"; +- reg = <0x40003000 0x400>; +- clocks = <&clk_lsi>; +- clock-names = "lsi"; +- status = "disabled"; +- }; +- +- spi2: spi@40003800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32f4-spi"; +- reg = <0x40003800 0x400>; +- interrupts = <36>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>; +- status = "disabled"; +- }; +- +- spi3: spi@40003c00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32f4-spi"; +- reg = <0x40003c00 0x400>; +- interrupts = <51>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>; +- status = "disabled"; +- }; +- +- usart2: serial@40004400 { +- compatible = "st,stm32-uart"; +- reg = <0x40004400 0x400>; +- interrupts = <38>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>; +- status = "disabled"; +- }; +- +- usart3: serial@40004800 { +- compatible = "st,stm32-uart"; +- reg = <0x40004800 0x400>; +- interrupts = <39>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>; +- status = "disabled"; +- dmas = <&dma1 1 4 0x400 0x0>, +- <&dma1 3 4 0x400 0x0>; +- dma-names = "rx", "tx"; +- }; +- +- usart4: serial@40004c00 { +- compatible = "st,stm32-uart"; +- reg = <0x40004c00 0x400>; +- interrupts = <52>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>; +- status = "disabled"; +- }; +- +- usart5: serial@40005000 { +- compatible = "st,stm32-uart"; +- reg = <0x40005000 0x400>; +- interrupts = <53>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>; +- status = "disabled"; +- }; +- +- i2c1: i2c@40005400 { +- compatible = "st,stm32f4-i2c"; +- reg = <0x40005400 0x400>; +- interrupts = <31>, +- <32>; +- resets = <&rcc STM32F4_APB1_RESET(I2C1)>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@40005c00 { +- compatible = "st,stm32f4-i2c"; +- reg = <0x40005c00 0x400>; +- interrupts = <72>, +- <73>; +- resets = <&rcc STM32F4_APB1_RESET(I2C3)>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- dac: dac@40007400 { +- compatible = "st,stm32f4-dac-core"; +- reg = <0x40007400 0x400>; +- resets = <&rcc STM32F4_APB1_RESET(DAC)>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>; +- clock-names = "pclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- dac1: dac@1 { +- compatible = "st,stm32-dac"; +- #io-channel-cells = <1>; +- reg = <1>; +- status = "disabled"; +- }; +- +- dac2: dac@2 { +- compatible = "st,stm32-dac"; +- #io-channel-cells = <1>; +- reg = <2>; +- status = "disabled"; +- }; +- }; +- +- usart7: serial@40007800 { +- compatible = "st,stm32-uart"; +- reg = <0x40007800 0x400>; +- interrupts = <82>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>; +- status = "disabled"; +- }; +- +- usart8: serial@40007c00 { +- compatible = "st,stm32-uart"; +- reg = <0x40007c00 0x400>; +- interrupts = <83>; +- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>; +- status = "disabled"; +- }; +- +- timers1: timers@40010000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40010000 0x400>; +- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@0 { +- compatible = "st,stm32-timer-trigger"; +- reg = <0>; +- status = "disabled"; +- }; +- }; +- +- timers8: timers@40010400 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40010400 0x400>; +- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@7 { +- compatible = "st,stm32-timer-trigger"; +- reg = <7>; +- status = "disabled"; +- }; +- }; +- +- usart1: serial@40011000 { +- compatible = "st,stm32-uart"; +- reg = <0x40011000 0x400>; +- interrupts = <37>; +- clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>; +- status = "disabled"; +- dmas = <&dma2 2 4 0x400 0x0>, +- <&dma2 7 4 0x400 0x0>; +- dma-names = "rx", "tx"; +- }; +- +- usart6: serial@40011400 { +- compatible = "st,stm32-uart"; +- reg = <0x40011400 0x400>; +- interrupts = <71>; +- clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>; +- status = "disabled"; +- }; +- +- adc: adc@40012000 { +- compatible = "st,stm32f4-adc-core"; +- reg = <0x40012000 0x400>; +- interrupts = <18>; +- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; +- clock-names = "adc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- adc1: adc@0 { +- compatible = "st,stm32f4-adc"; +- #io-channel-cells = <1>; +- reg = <0x0>; +- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; +- interrupt-parent = <&adc>; +- interrupts = <0>; +- dmas = <&dma2 0 0 0x400 0x0>; +- dma-names = "rx"; +- status = "disabled"; +- }; +- +- adc2: adc@100 { +- compatible = "st,stm32f4-adc"; +- #io-channel-cells = <1>; +- reg = <0x100>; +- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>; +- interrupt-parent = <&adc>; +- interrupts = <1>; +- dmas = <&dma2 3 1 0x400 0x0>; +- dma-names = "rx"; +- status = "disabled"; +- }; +- +- adc3: adc@200 { +- compatible = "st,stm32f4-adc"; +- #io-channel-cells = <1>; +- reg = <0x200>; +- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>; +- interrupt-parent = <&adc>; +- interrupts = <2>; +- dmas = <&dma2 1 2 0x400 0x0>; +- dma-names = "rx"; +- status = "disabled"; +- }; +- }; +- +- sdio: mmc@40012c00 { +- compatible = "arm,pl180", "arm,primecell"; +- arm,primecell-periphid = <0x00880180>; +- reg = <0x40012c00 0x400>; +- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>; +- clock-names = "apb_pclk"; +- interrupts = <49>; +- max-frequency = <48000000>; +- status = "disabled"; +- }; +- +- spi1: spi@40013000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32f4-spi"; +- reg = <0x40013000 0x400>; +- interrupts = <35>; +- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>; +- status = "disabled"; +- }; +- +- spi4: spi@40013400 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32f4-spi"; +- reg = <0x40013400 0x400>; +- interrupts = <84>; +- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>; +- status = "disabled"; +- }; +- +- syscfg: syscon@40013800 { +- compatible = "st,stm32-syscfg", "syscon"; +- reg = <0x40013800 0x400>; +- }; +- +- exti: interrupt-controller@40013c00 { +- compatible = "st,stm32-exti"; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x40013C00 0x400>; +- interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; +- }; +- +- timers9: timers@40014000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40014000 0x400>; +- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@8 { +- compatible = "st,stm32-timer-trigger"; +- reg = <8>; +- status = "disabled"; +- }; +- }; +- +- timers10: timers@40014400 { +- compatible = "st,stm32-timers"; +- reg = <0x40014400 0x400>; +- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- }; +- +- timers11: timers@40014800 { +- compatible = "st,stm32-timers"; +- reg = <0x40014800 0x400>; +- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- }; +- +- spi5: spi@40015000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32f4-spi"; +- reg = <0x40015000 0x400>; +- interrupts = <85>; +- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>; +- dmas = <&dma2 3 2 0x400 0x0>, +- <&dma2 4 2 0x400 0x0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi6: spi@40015400 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32f4-spi"; +- reg = <0x40015400 0x400>; +- interrupts = <86>; +- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>; +- status = "disabled"; +- }; +- +- pwrcfg: power-config@40007000 { +- compatible = "st,stm32-power-config", "syscon"; +- reg = <0x40007000 0x400>; +- }; +- +- ltdc: display-controller@40016800 { +- compatible = "st,stm32-ltdc"; +- reg = <0x40016800 0x200>; +- interrupts = <88>, <89>; +- resets = <&rcc STM32F4_APB2_RESET(LTDC)>; +- clocks = <&rcc 1 CLK_LCD>; +- clock-names = "lcd"; +- status = "disabled"; +- }; +- +- crc: crc@40023000 { +- compatible = "st,stm32f4-crc"; +- reg = <0x40023000 0x400>; +- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>; +- status = "disabled"; +- }; +- +- rcc: rcc@40023800 { +- #reset-cells = <1>; +- #clock-cells = <2>; +- compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; +- reg = <0x40023800 0x400>; +- clocks = <&clk_hse>, <&clk_i2s_ckin>; +- st,syscfg = <&pwrcfg>; +- assigned-clocks = <&rcc 1 CLK_HSE_RTC>; +- assigned-clock-rates = <1000000>; +- }; +- +- dma1: dma-controller@40026000 { +- compatible = "st,stm32-dma"; +- reg = <0x40026000 0x400>; +- interrupts = <11>, +- <12>, +- <13>, +- <14>, +- <15>, +- <16>, +- <17>, +- <47>; +- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>; +- #dma-cells = <4>; +- }; +- +- dma2: dma-controller@40026400 { +- compatible = "st,stm32-dma"; +- reg = <0x40026400 0x400>; +- interrupts = <56>, +- <57>, +- <58>, +- <59>, +- <60>, +- <68>, +- <69>, +- <70>; +- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>; +- #dma-cells = <4>; +- st,mem2mem; +- }; +- +- mac: ethernet@40028000 { +- compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; +- reg = <0x40028000 0x8000>; +- reg-names = "stmmaceth"; +- interrupts = <61>; +- interrupt-names = "macirq"; +- clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; +- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>, +- <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>, +- <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>; +- st,syscon = <&syscfg 0x4>; +- snps,pbl = <8>; +- snps,mixed-burst; +- status = "disabled"; +- }; +- +- usbotg_hs: usb@40040000 { +- compatible = "snps,dwc2"; +- reg = <0x40040000 0x40000>; +- interrupts = <77>; +- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>; +- clock-names = "otg"; +- status = "disabled"; +- }; +- +- usbotg_fs: usb@50000000 { +- compatible = "st,stm32f4x9-fsotg"; +- reg = <0x50000000 0x40000>; +- interrupts = <67>; +- clocks = <&rcc 0 39>; +- clock-names = "otg"; +- status = "disabled"; +- }; +- +- dcmi: dcmi@50050000 { +- compatible = "st,stm32-dcmi"; +- reg = <0x50050000 0x400>; +- interrupts = <78>; +- resets = <&rcc STM32F4_AHB2_RESET(DCMI)>; +- clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>; +- clock-names = "mclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dcmi_pins>; +- dmas = <&dma2 1 1 0x414 0x3>; +- dma-names = "tx"; +- status = "disabled"; +- }; +- +- rng: rng@50060800 { +- compatible = "st,stm32-rng"; +- reg = <0x50060800 0x400>; +- clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>; +- +- }; +- }; +-}; +- +-&systick { +- clocks = <&rcc 1 SYSTICK>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32f469-disco.dts b/scripts/dtc/include-prefixes/arm/stm32f469-disco.dts +deleted file mode 100644 +index 30905ce672a0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32f469-disco.dts ++++ /dev/null +@@ -1,238 +0,0 @@ +-/* +- * Copyright 2016 - Lee Jones +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "stm32f469.dtsi" +-#include "stm32f469-pinctrl.dtsi" +-#include +-#include +- +-/ { +- model = "STMicroelectronics STM32F469i-DISCO board"; +- compatible = "st,stm32f469i-disco", "st,stm32f469"; +- +- chosen { +- bootargs = "root=/dev/ram"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x1000000>; +- }; +- +- aliases { +- serial0 = &usart3; +- }; +- +- mmc_vcard: mmc_vcard { +- compatible = "regulator-fixed"; +- regulator-name = "mmc_vcard"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vdd_dsi: vdd-dsi { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_dsi"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- soc { +- dma-ranges = <0xc0000000 0x0 0x10000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-green { +- gpios = <&gpiog 6 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- led-orange { +- gpios = <&gpiod 4 GPIO_ACTIVE_LOW>; +- }; +- led-red { +- gpios = <&gpiod 5 GPIO_ACTIVE_LOW>; +- }; +- led-blue { +- gpios = <&gpiok 3 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- button-0 { +- label = "User"; +- linux,code = ; +- gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- /* This turns on vbus for otg for host mode (dwc2) */ +- vcc5v_otg: vcc5v-otg-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpiob 2 GPIO_ACTIVE_HIGH>; +- regulator-name = "vcc5_host1"; +- regulator-always-on; +- }; +-}; +- +-&rcc { +- compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc"; +-}; +- +-&clk_hse { +- clock-frequency = <8000000>; +-}; +- +-&dsi { +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dsi_in: endpoint { +- remote-endpoint = <<dc_out_dsi>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- dsi_out: endpoint { +- remote-endpoint = <&dsi_panel_in>; +- }; +- }; +- }; +- +- panel-dsi@0 { +- compatible = "orisetech,otm8009a"; +- reg = <0>; /* dsi virtual channel (0..3) */ +- reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>; +- power-supply = <&vdd_dsi>; +- status = "okay"; +- +- port { +- dsi_panel_in: endpoint { +- remote-endpoint = <&dsi_out>; +- }; +- }; +- }; +-}; +- +-<dc { +- status = "okay"; +- +- port { +- ltdc_out_dsi: endpoint@0 { +- remote-endpoint = <&dsi_in>; +- }; +- }; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&timers1 { +- status = "okay"; +- +- pwm { +- pinctrl-0 = <&pwm1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- +- timer@0 { +- status = "okay"; +- }; +-}; +- +-&timers3 { +- status = "okay"; +- +- pwm { +- pinctrl-0 = <&pwm3_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- +- timer@2 { +- status = "okay"; +- }; +-}; +- +-&sdio { +- status = "okay"; +- vmmc-supply = <&mmc_vcard>; +- cd-gpios = <&gpiog 2 GPIO_ACTIVE_LOW>; +- broken-cd; +- pinctrl-names = "default", "opendrain"; +- pinctrl-0 = <&sdio_pins>; +- pinctrl-1 = <&sdio_pins_od>; +- bus-width = <4>; +-}; +- +-&usart3 { +- pinctrl-0 = <&usart3_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&usbotg_fs { +- dr_mode = "host"; +- pinctrl-0 = <&usbotg_fs_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32f469-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/stm32f469-pinctrl.dtsi +deleted file mode 100644 +index 6bf60263dff8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32f469-pinctrl.dtsi ++++ /dev/null +@@ -1,92 +0,0 @@ +-/* +- * Copyright 2017 - Alexandre Torgue +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "stm32f4-pinctrl.dtsi" +- +-&pinctrl { +- compatible = "st,stm32f469-pinctrl"; +- +- gpioa: gpio@40020000 { +- gpio-ranges = <&pinctrl 0 0 16>; +- }; +- +- gpiob: gpio@40020400 { +- gpio-ranges = <&pinctrl 0 16 16>; +- }; +- +- gpioc: gpio@40020800 { +- gpio-ranges = <&pinctrl 0 32 16>; +- }; +- +- gpiod: gpio@40020c00 { +- gpio-ranges = <&pinctrl 0 48 16>; +- }; +- +- gpioe: gpio@40021000 { +- gpio-ranges = <&pinctrl 0 64 16>; +- }; +- +- gpiof: gpio@40021400 { +- gpio-ranges = <&pinctrl 0 80 16>; +- }; +- +- gpiog: gpio@40021800 { +- gpio-ranges = <&pinctrl 0 96 16>; +- }; +- +- gpioh: gpio@40021c00 { +- gpio-ranges = <&pinctrl 0 112 16>; +- }; +- +- gpioi: gpio@40022000 { +- gpio-ranges = <&pinctrl 0 128 16>; +- }; +- +- gpioj: gpio@40022400 { +- gpio-ranges = <&pinctrl 0 144 6>, +- <&pinctrl 12 156 4>; +- }; +- +- gpiok: gpio@40022800 { +- gpio-ranges = <&pinctrl 3 163 5>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32f469.dtsi b/scripts/dtc/include-prefixes/arm/stm32f469.dtsi +deleted file mode 100644 +index be002e8a78ac..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32f469.dtsi ++++ /dev/null +@@ -1,18 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +-/* Copyright (C) STMicroelectronics 2017 - All Rights Reserved */ +- +-#include "stm32f429.dtsi" +- +-/ { +- soc { +- dsi: dsi@40016c00 { +- compatible = "st,stm32-dsi"; +- reg = <0x40016c00 0x800>; +- resets = <&rcc STM32F4_APB2_RESET(DSI)>; +- reset-names = "apb"; +- clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>; +- clock-names = "pclk", "ref"; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32f7-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/stm32f7-pinctrl.dtsi +deleted file mode 100644 +index 1cf8a23c2644..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32f7-pinctrl.dtsi ++++ /dev/null +@@ -1,289 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved +- * Author: Alexandre Torgue for STMicroelectronics. +- */ +- +-#include +-#include +- +-/ { +- soc { +- pinctrl: pin-controller@40020000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x40020000 0x3000>; +- interrupt-parent = <&exti>; +- st,syscfg = <&syscfg 0x8>; +- pins-are-numbered; +- +- gpioa: gpio@40020000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x0 0x400>; +- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; +- st,bank-name = "GPIOA"; +- }; +- +- gpiob: gpio@40020400 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x400 0x400>; +- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; +- st,bank-name = "GPIOB"; +- }; +- +- gpioc: gpio@40020800 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x800 0x400>; +- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; +- st,bank-name = "GPIOC"; +- }; +- +- gpiod: gpio@40020c00 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0xc00 0x400>; +- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; +- st,bank-name = "GPIOD"; +- }; +- +- gpioe: gpio@40021000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x1000 0x400>; +- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; +- st,bank-name = "GPIOE"; +- }; +- +- gpiof: gpio@40021400 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x1400 0x400>; +- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; +- st,bank-name = "GPIOF"; +- }; +- +- gpiog: gpio@40021800 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x1800 0x400>; +- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; +- st,bank-name = "GPIOG"; +- }; +- +- gpioh: gpio@40021c00 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x1c00 0x400>; +- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; +- st,bank-name = "GPIOH"; +- }; +- +- gpioi: gpio@40022000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x2000 0x400>; +- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; +- st,bank-name = "GPIOI"; +- }; +- +- gpioj: gpio@40022400 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x2400 0x400>; +- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; +- st,bank-name = "GPIOJ"; +- }; +- +- gpiok: gpio@40022800 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x2800 0x400>; +- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; +- st,bank-name = "GPIOK"; +- }; +- +- cec_pins_a: cec-0 { +- pins { +- pinmux = ; /* HDMI CEC */ +- slew-rate = <0>; +- drive-open-drain; +- bias-disable; +- }; +- }; +- +- usart1_pins_a: usart1-0 { +- pins1 { +- pinmux = ; /* USART1_TX */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = ; /* USART1_RX */ +- bias-disable; +- }; +- }; +- +- usart1_pins_b: usart1-1 { +- pins1 { +- pinmux = ; /* USART1_TX */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = ; /* USART1_RX */ +- bias-disable; +- }; +- }; +- +- i2c1_pins_b: i2c1-0 { +- pins { +- pinmux = , /* I2C1 SDA */ +- ; /* I2C1 SCL */ +- bias-disable; +- drive-open-drain; +- slew-rate = <0>; +- }; +- }; +- +- usbotg_hs_pins_a: usbotg-hs-0 { +- pins { +- pinmux = , /* OTG_HS_ULPI_NXT */ +- , /* OTG_HS_ULPI_DIR */ +- , /* OTG_HS_ULPI_STP */ +- , /* OTG_HS_ULPI_CK */ +- , /* OTG_HS_ULPI_D0 */ +- , /* OTG_HS_ULPI_D1 */ +- , /* OTG_HS_ULPI_D2 */ +- , /* OTG_HS_ULPI_D3 */ +- , /* OTG_HS_ULPI_D4 */ +- , /* OTG_HS_ULPI_D5 */ +- , /* OTG_HS_ULPI_D6 */ +- ; /* OTG_HS_ULPI_D7 */ +- bias-disable; +- drive-push-pull; +- slew-rate = <2>; +- }; +- }; +- +- usbotg_hs_pins_b: usbotg-hs-1 { +- pins { +- pinmux = , /* OTG_HS_ULPI_NXT */ +- , /* OTG_HS_ULPI_DIR */ +- , /* OTG_HS_ULPI_STP */ +- , /* OTG_HS_ULPI_CK */ +- , /* OTG_HS_ULPI_D0 */ +- , /* OTG_HS_ULPI_D1 */ +- , /* OTG_HS_ULPI_D2 */ +- , /* OTG_HS_ULPI_D3 */ +- , /* OTG_HS_ULPI_D4 */ +- , /* OTG_HS_ULPI_D5 */ +- , /* OTG_HS_ULPI_D6 */ +- ; /* OTG_HS_ULPI_D7 */ +- bias-disable; +- drive-push-pull; +- slew-rate = <2>; +- }; +- }; +- +- usbotg_fs_pins_a: usbotg-fs-0 { +- pins { +- pinmux = , /* OTG_FS_ID */ +- , /* OTG_FS_DM */ +- ; /* OTG_FS_DP */ +- bias-disable; +- drive-push-pull; +- slew-rate = <2>; +- }; +- }; +- +- sdio_pins_a: sdio-pins-a-0 { +- pins { +- pinmux = , /* SDMMC1 D0 */ +- , /* SDMMC1 D1 */ +- , /* SDMMC1 D2 */ +- , /* SDMMC1 D3 */ +- , /* SDMMC1 CLK */ +- ; /* SDMMC1 CMD */ +- drive-push-pull; +- slew-rate = <2>; +- }; +- }; +- +- sdio_pins_od_a: sdio-pins-od-a-0 { +- pins1 { +- pinmux = , /* SDMMC1 D0 */ +- , /* SDMMC1 D1 */ +- , /* SDMMC1 D2 */ +- , /* SDMMC1 D3 */ +- ; /* SDMMC1 CLK */ +- drive-push-pull; +- slew-rate = <2>; +- }; +- +- pins2 { +- pinmux = ; /* SDMMC1 CMD */ +- drive-open-drain; +- slew-rate = <2>; +- }; +- }; +- +- sdio_pins_b: sdio-pins-b-0 { +- pins { +- pinmux = , /* SDMMC2 D0 */ +- , /* SDMMC2 D1 */ +- , /* SDMMC2 D2 */ +- , /* SDMMC2 D3 */ +- , /* SDMMC2 CLK */ +- ; /* SDMMC2 CMD */ +- drive-push-pull; +- slew-rate = <2>; +- }; +- }; +- +- sdio_pins_od_b: sdio-pins-od-b-0 { +- pins1 { +- pinmux = , /* SDMMC2 D0 */ +- , /* SDMMC2 D1 */ +- , /* SDMMC2 D2 */ +- , /* SDMMC2 D3 */ +- ; /* SDMMC2 CLK */ +- drive-push-pull; +- slew-rate = <2>; +- }; +- +- pins2 { +- pinmux = ; /* SDMMC2 CMD */ +- drive-open-drain; +- slew-rate = <2>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32f746-disco.dts b/scripts/dtc/include-prefixes/arm/stm32f746-disco.dts +deleted file mode 100644 +index 569d23cc61e5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32f746-disco.dts ++++ /dev/null +@@ -1,132 +0,0 @@ +-/* +- * Copyright 2017 - Vikas MANOCHA +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "stm32f746.dtsi" +-#include "stm32f746-pinctrl.dtsi" +-#include +-#include +- +-/ { +- model = "STMicroelectronics STM32F746-DISCO board"; +- compatible = "st,stm32f746-disco", "st,stm32f746"; +- +- chosen { +- bootargs = "root=/dev/ram"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@c0000000 { +- device_type = "memory"; +- reg = <0xC0000000 0x800000>; +- }; +- +- aliases { +- serial0 = &usart1; +- }; +- +- usbotg_hs_phy: usb-phy { +- #phy-cells = <0>; +- compatible = "usb-nop-xceiv"; +- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; +- clock-names = "main_clk"; +- }; +- +- /* This turns on vbus for otg fs for host mode (dwc2) */ +- vcc5v_otg_fs: vcc5v-otg-fs-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpiod 5 0>; +- regulator-name = "vcc5_host1"; +- regulator-always-on; +- }; +- +- mmc_vcard: mmc_vcard { +- compatible = "regulator-fixed"; +- regulator-name = "mmc_vcard"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&clk_hse { +- clock-frequency = <25000000>; +-}; +- +-&i2c1 { +- pinctrl-0 = <&i2c1_pins_b>; +- pinctrl-names = "default"; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +-}; +- +-&sdio1 { +- status = "okay"; +- vmmc-supply = <&mmc_vcard>; +- cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default", "opendrain"; +- pinctrl-0 = <&sdio_pins_a>; +- pinctrl-1 = <&sdio_pins_od_a>; +- bus-width = <4>; +-}; +- +-&usart1 { +- pinctrl-0 = <&usart1_pins_b>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&usbotg_fs { +- dr_mode = "host"; +- pinctrl-0 = <&usbotg_fs_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&usbotg_hs { +- dr_mode = "host"; +- phys = <&usbotg_hs_phy>; +- phy-names = "usb2-phy"; +- pinctrl-0 = <&usbotg_hs_pins_b>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32f746-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/stm32f746-pinctrl.dtsi +deleted file mode 100644 +index fcfd2ac7239b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32f746-pinctrl.dtsi ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved +- * Author: Alexandre Torgue for STMicroelectronics. +- */ +- +-#include "stm32f7-pinctrl.dtsi" +- +-&pinctrl{ +- compatible = "st,stm32f746-pinctrl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32f746.dtsi b/scripts/dtc/include-prefixes/arm/stm32f746.dtsi +deleted file mode 100644 +index 014b416f57e6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32f746.dtsi ++++ /dev/null +@@ -1,639 +0,0 @@ +-/* +- * Copyright 2015 - Maxime Coquelin +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "armv7-m.dtsi" +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- clocks { +- clk_hse: clk-hse { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- clk-lse { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- clk-lsi { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32000>; +- }; +- +- clk_i2s_ckin: clk-i2s-ckin { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <48000000>; +- }; +- }; +- +- soc { +- timer2: timer@40000000 { +- compatible = "st,stm32-timer"; +- reg = <0x40000000 0x400>; +- interrupts = <28>; +- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; +- status = "disabled"; +- }; +- +- timers2: timers@40000000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40000000 0x400>; +- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@1 { +- compatible = "st,stm32-timer-trigger"; +- reg = <1>; +- status = "disabled"; +- }; +- }; +- +- timer3: timer@40000400 { +- compatible = "st,stm32-timer"; +- reg = <0x40000400 0x400>; +- interrupts = <29>; +- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; +- status = "disabled"; +- }; +- +- timers3: timers@40000400 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40000400 0x400>; +- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@2 { +- compatible = "st,stm32-timer-trigger"; +- reg = <2>; +- status = "disabled"; +- }; +- }; +- +- timer4: timer@40000800 { +- compatible = "st,stm32-timer"; +- reg = <0x40000800 0x400>; +- interrupts = <30>; +- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; +- status = "disabled"; +- }; +- +- timers4: timers@40000800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40000800 0x400>; +- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@3 { +- compatible = "st,stm32-timer-trigger"; +- reg = <3>; +- status = "disabled"; +- }; +- }; +- +- timer5: timer@40000c00 { +- compatible = "st,stm32-timer"; +- reg = <0x40000c00 0x400>; +- interrupts = <50>; +- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; +- }; +- +- timers5: timers@40000c00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40000C00 0x400>; +- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@4 { +- compatible = "st,stm32-timer-trigger"; +- reg = <4>; +- status = "disabled"; +- }; +- }; +- +- timer6: timer@40001000 { +- compatible = "st,stm32-timer"; +- reg = <0x40001000 0x400>; +- interrupts = <54>; +- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; +- status = "disabled"; +- }; +- +- timers6: timers@40001000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40001000 0x400>; +- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; +- clock-names = "int"; +- status = "disabled"; +- +- timer@5 { +- compatible = "st,stm32-timer-trigger"; +- reg = <5>; +- status = "disabled"; +- }; +- }; +- +- timer7: timer@40001400 { +- compatible = "st,stm32-timer"; +- reg = <0x40001400 0x400>; +- interrupts = <55>; +- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; +- status = "disabled"; +- }; +- +- timers7: timers@40001400 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40001400 0x400>; +- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; +- clock-names = "int"; +- status = "disabled"; +- +- timer@6 { +- compatible = "st,stm32-timer-trigger"; +- reg = <6>; +- status = "disabled"; +- }; +- }; +- +- timers12: timers@40001800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40001800 0x400>; +- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@11 { +- compatible = "st,stm32-timer-trigger"; +- reg = <11>; +- status = "disabled"; +- }; +- }; +- +- timers13: timers@40001c00 { +- compatible = "st,stm32-timers"; +- reg = <0x40001C00 0x400>; +- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- }; +- +- timers14: timers@40002000 { +- compatible = "st,stm32-timers"; +- reg = <0x40002000 0x400>; +- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- }; +- +- rtc: rtc@40002800 { +- compatible = "st,stm32-rtc"; +- reg = <0x40002800 0x400>; +- clocks = <&rcc 1 CLK_RTC>; +- assigned-clocks = <&rcc 1 CLK_RTC>; +- assigned-clock-parents = <&rcc 1 CLK_LSE>; +- interrupt-parent = <&exti>; +- interrupts = <17 1>; +- st,syscfg = <&pwrcfg 0x00 0x100>; +- status = "disabled"; +- }; +- +- usart2: serial@40004400 { +- compatible = "st,stm32f7-uart"; +- reg = <0x40004400 0x400>; +- interrupts = <38>; +- clocks = <&rcc 1 CLK_USART2>; +- status = "disabled"; +- }; +- +- usart3: serial@40004800 { +- compatible = "st,stm32f7-uart"; +- reg = <0x40004800 0x400>; +- interrupts = <39>; +- clocks = <&rcc 1 CLK_USART3>; +- status = "disabled"; +- }; +- +- usart4: serial@40004c00 { +- compatible = "st,stm32f7-uart"; +- reg = <0x40004c00 0x400>; +- interrupts = <52>; +- clocks = <&rcc 1 CLK_UART4>; +- status = "disabled"; +- }; +- +- usart5: serial@40005000 { +- compatible = "st,stm32f7-uart"; +- reg = <0x40005000 0x400>; +- interrupts = <53>; +- clocks = <&rcc 1 CLK_UART5>; +- status = "disabled"; +- }; +- +- i2c1: i2c@40005400 { +- compatible = "st,stm32f7-i2c"; +- reg = <0x40005400 0x400>; +- interrupts = <31>, +- <32>; +- resets = <&rcc STM32F7_APB1_RESET(I2C1)>; +- clocks = <&rcc 1 CLK_I2C1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@40005800 { +- compatible = "st,stm32f7-i2c"; +- reg = <0x40005800 0x400>; +- interrupts = <33>, +- <34>; +- resets = <&rcc STM32F7_APB1_RESET(I2C2)>; +- clocks = <&rcc 1 CLK_I2C2>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@40005c00 { +- compatible = "st,stm32f7-i2c"; +- reg = <0x40005c00 0x400>; +- interrupts = <72>, +- <73>; +- resets = <&rcc STM32F7_APB1_RESET(I2C3)>; +- clocks = <&rcc 1 CLK_I2C3>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@40006000 { +- compatible = "st,stm32f7-i2c"; +- reg = <0x40006000 0x400>; +- interrupts = <95>, +- <96>; +- resets = <&rcc STM32F7_APB1_RESET(I2C4)>; +- clocks = <&rcc 1 CLK_I2C4>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- cec: cec@40006c00 { +- compatible = "st,stm32-cec"; +- reg = <0x40006C00 0x400>; +- interrupts = <94>; +- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; +- clock-names = "cec", "hdmi-cec"; +- status = "disabled"; +- }; +- +- usart7: serial@40007800 { +- compatible = "st,stm32f7-uart"; +- reg = <0x40007800 0x400>; +- interrupts = <82>; +- clocks = <&rcc 1 CLK_UART7>; +- status = "disabled"; +- }; +- +- usart8: serial@40007c00 { +- compatible = "st,stm32f7-uart"; +- reg = <0x40007c00 0x400>; +- interrupts = <83>; +- clocks = <&rcc 1 CLK_UART8>; +- status = "disabled"; +- }; +- +- timers1: timers@40010000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40010000 0x400>; +- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@0 { +- compatible = "st,stm32-timer-trigger"; +- reg = <0>; +- status = "disabled"; +- }; +- }; +- +- timers8: timers@40010400 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40010400 0x400>; +- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@7 { +- compatible = "st,stm32-timer-trigger"; +- reg = <7>; +- status = "disabled"; +- }; +- }; +- +- usart1: serial@40011000 { +- compatible = "st,stm32f7-uart"; +- reg = <0x40011000 0x400>; +- interrupts = <37>; +- clocks = <&rcc 1 CLK_USART1>; +- status = "disabled"; +- }; +- +- usart6: serial@40011400 { +- compatible = "st,stm32f7-uart"; +- reg = <0x40011400 0x400>; +- interrupts = <71>; +- clocks = <&rcc 1 CLK_USART6>; +- status = "disabled"; +- }; +- +- sdio2: mmc@40011c00 { +- compatible = "arm,pl180", "arm,primecell"; +- arm,primecell-periphid = <0x00880180>; +- reg = <0x40011c00 0x400>; +- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>; +- clock-names = "apb_pclk"; +- interrupts = <103>; +- max-frequency = <48000000>; +- status = "disabled"; +- }; +- +- sdio1: mmc@40012c00 { +- compatible = "arm,pl180", "arm,primecell"; +- arm,primecell-periphid = <0x00880180>; +- reg = <0x40012c00 0x400>; +- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>; +- clock-names = "apb_pclk"; +- interrupts = <49>; +- max-frequency = <48000000>; +- status = "disabled"; +- }; +- +- syscfg: syscon@40013800 { +- compatible = "st,stm32-syscfg", "syscon"; +- reg = <0x40013800 0x400>; +- }; +- +- exti: interrupt-controller@40013c00 { +- compatible = "st,stm32-exti"; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x40013C00 0x400>; +- interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; +- }; +- +- timers9: timers@40014000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40014000 0x400>; +- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@8 { +- compatible = "st,stm32-timer-trigger"; +- reg = <8>; +- status = "disabled"; +- }; +- }; +- +- timers10: timers@40014400 { +- compatible = "st,stm32-timers"; +- reg = <0x40014400 0x400>; +- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- }; +- +- timers11: timers@40014800 { +- compatible = "st,stm32-timers"; +- reg = <0x40014800 0x400>; +- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- }; +- +- pwrcfg: power-config@40007000 { +- compatible = "st,stm32-power-config", "syscon"; +- reg = <0x40007000 0x400>; +- }; +- +- crc: crc@40023000 { +- compatible = "st,stm32f7-crc"; +- reg = <0x40023000 0x400>; +- clocks = <&rcc 0 12>; +- status = "disabled"; +- }; +- +- rcc: rcc@40023800 { +- #reset-cells = <1>; +- #clock-cells = <2>; +- compatible = "st,stm32f746-rcc", "st,stm32-rcc"; +- reg = <0x40023800 0x400>; +- clocks = <&clk_hse>, <&clk_i2s_ckin>; +- st,syscfg = <&pwrcfg>; +- assigned-clocks = <&rcc 1 CLK_HSE_RTC>; +- assigned-clock-rates = <1000000>; +- }; +- +- dma1: dma-controller@40026000 { +- compatible = "st,stm32-dma"; +- reg = <0x40026000 0x400>; +- interrupts = <11>, +- <12>, +- <13>, +- <14>, +- <15>, +- <16>, +- <17>, +- <47>; +- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>; +- #dma-cells = <4>; +- status = "disabled"; +- }; +- +- dma2: dma-controller@40026400 { +- compatible = "st,stm32-dma"; +- reg = <0x40026400 0x400>; +- interrupts = <56>, +- <57>, +- <58>, +- <59>, +- <60>, +- <68>, +- <69>, +- <70>; +- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>; +- #dma-cells = <4>; +- st,mem2mem; +- status = "disabled"; +- }; +- +- usbotg_hs: usb@40040000 { +- compatible = "st,stm32f7-hsotg"; +- reg = <0x40040000 0x40000>; +- interrupts = <77>; +- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>; +- clock-names = "otg"; +- g-rx-fifo-size = <256>; +- g-np-tx-fifo-size = <32>; +- g-tx-fifo-size = <128 128 64 64 64 64 32 32>; +- status = "disabled"; +- }; +- +- usbotg_fs: usb@50000000 { +- compatible = "st,stm32f4x9-fsotg"; +- reg = <0x50000000 0x40000>; +- interrupts = <67>; +- clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>; +- clock-names = "otg"; +- status = "disabled"; +- }; +- }; +-}; +- +-&systick { +- clocks = <&rcc 1 0>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32f769-disco.dts b/scripts/dtc/include-prefixes/arm/stm32f769-disco.dts +deleted file mode 100644 +index be943b701980..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32f769-disco.dts ++++ /dev/null +@@ -1,153 +0,0 @@ +-/* +- * Copyright 2017 - Vikas MANOCHA +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "stm32f746.dtsi" +-#include "stm32f769-pinctrl.dtsi" +-#include +-#include +- +-/ { +- model = "STMicroelectronics STM32F769-DISCO board"; +- compatible = "st,stm32f769-disco", "st,stm32f769"; +- +- chosen { +- bootargs = "root=/dev/ram"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@c0000000 { +- device_type = "memory"; +- reg = <0xC0000000 0x1000000>; +- }; +- +- aliases { +- serial0 = &usart1; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-green { +- gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- led-red { +- gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- button-0 { +- label = "User"; +- linux,code = ; +- gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- usbotg_hs_phy: usb-phy { +- #phy-cells = <0>; +- compatible = "usb-nop-xceiv"; +- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; +- clock-names = "main_clk"; +- }; +- +- mmc_vcard: mmc_vcard { +- compatible = "regulator-fixed"; +- regulator-name = "mmc_vcard"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&rcc { +- compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc"; +-}; +- +-&cec { +- pinctrl-0 = <&cec_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&clk_hse { +- clock-frequency = <25000000>; +-}; +- +-&i2c1 { +- pinctrl-0 = <&i2c1_pins_b>; +- pinctrl-names = "default"; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&sdio2 { +- status = "okay"; +- vmmc-supply = <&mmc_vcard>; +- cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; +- broken-cd; +- pinctrl-names = "default", "opendrain"; +- pinctrl-0 = <&sdio_pins_b>; +- pinctrl-1 = <&sdio_pins_od_b>; +- bus-width = <4>; +-}; +- +-&usart1 { +- pinctrl-0 = <&usart1_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&usbotg_hs { +- dr_mode = "otg"; +- phys = <&usbotg_hs_phy>; +- phy-names = "usb2-phy"; +- pinctrl-0 = <&usbotg_hs_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32f769-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/stm32f769-pinctrl.dtsi +deleted file mode 100644 +index 31005dd9929c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32f769-pinctrl.dtsi ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved +- * Author: Alexandre Torgue for STMicroelectronics. +- */ +- +-#include "stm32f7-pinctrl.dtsi" +- +-&pinctrl{ +- compatible = "st,stm32f769-pinctrl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32h7-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/stm32h7-pinctrl.dtsi +deleted file mode 100644 +index aa1bc3e10a49..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32h7-pinctrl.dtsi ++++ /dev/null +@@ -1,275 +0,0 @@ +-/* +- * Copyright 2017 - Alexandre Torgue +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +- +-&pinctrl { +- +- i2c1_pins_a: i2c1-0 { +- pins { +- pinmux = , /* I2C1_SCL */ +- ; /* I2C1_SDA */ +- bias-disable; +- drive-open-drain; +- slew-rate = <0>; +- }; +- }; +- +- ethernet_rmii: rmii-0 { +- pins { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- ; +- slew-rate = <2>; +- }; +- }; +- +- sdmmc1_b4_pins_a: sdmmc1-b4-0 { +- pins { +- pinmux = , /* SDMMC1_D0 */ +- , /* SDMMC1_D1 */ +- , /* SDMMC1_D2 */ +- , /* SDMMC1_D3 */ +- , /* SDMMC1_CK */ +- ; /* SDMMC1_CMD */ +- slew-rate = <3>; +- drive-push-pull; +- bias-disable; +- }; +- }; +- +- sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { +- pins1 { +- pinmux = , /* SDMMC1_D0 */ +- , /* SDMMC1_D1 */ +- , /* SDMMC1_D2 */ +- , /* SDMMC1_D3 */ +- ; /* SDMMC1_CK */ +- slew-rate = <3>; +- drive-push-pull; +- bias-disable; +- }; +- pins2{ +- pinmux = ; /* SDMMC1_CMD */ +- slew-rate = <3>; +- drive-open-drain; +- bias-disable; +- }; +- }; +- +- sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { +- pins { +- pinmux = , /* SDMMC1_D0 */ +- , /* SDMMC1_D1 */ +- , /* SDMMC1_D2 */ +- , /* SDMMC1_D3 */ +- , /* SDMMC1_CK */ +- ; /* SDMMC1_CMD */ +- }; +- }; +- +- sdmmc1_dir_pins_a: sdmmc1-dir-0 { +- pins1 { +- pinmux = , /* SDMMC1_D0DIR */ +- , /* SDMMC1_D123DIR */ +- ; /* SDMMC1_CDIR */ +- slew-rate = <3>; +- drive-push-pull; +- bias-pull-up; +- }; +- pins2{ +- pinmux = ; /* SDMMC1_CKIN */ +- bias-pull-up; +- }; +- }; +- +- sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { +- pins { +- pinmux = , /* SDMMC1_D0DIR */ +- , /* SDMMC1_D123DIR */ +- , /* SDMMC1_CDIR */ +- ; /* SDMMC1_CKIN */ +- }; +- }; +- +- sdmmc2_b4_pins_a: sdmmc2-b4-0 { +- pins { +- pinmux = , /* SDMMC1_D0 */ +- , /* SDMMC1_D1 */ +- , /* SDMMC1_D2 */ +- , /* SDMMC1_D3 */ +- , /* SDMMC1_CK */ +- ; /* SDMMC1_CMD */ +- slew-rate = <3>; +- drive-push-pull; +- bias-disable; +- }; +- }; +- +- sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { +- pins1 { +- pinmux = , /* SDMMC2_D0 */ +- , /* SDMMC1_D1 */ +- , /* SDMMC1_D2 */ +- , /* SDMMC1_D3 */ +- ; /* SDMMC1_CK */ +- slew-rate = <3>; +- drive-push-pull; +- bias-disable; +- }; +- pins2{ +- pinmux = ; /* SDMMC1_CMD */ +- slew-rate = <3>; +- drive-open-drain; +- bias-disable; +- }; +- }; +- +- sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { +- pins { +- pinmux = , /* SDMMC1_D0 */ +- , /* SDMMC1_D1 */ +- , /* SDMMC1_D2 */ +- , /* SDMMC1_D3 */ +- , /* SDMMC1_CK */ +- ; /* SDMMC1_CMD */ +- }; +- }; +- +- spi1_pins: spi1-0 { +- pins1 { +- pinmux = , +- /* SPI1_CLK */ +- ; +- /* SPI1_MOSI */ +- bias-disable; +- drive-push-pull; +- slew-rate = <2>; +- }; +- pins2 { +- pinmux = ; +- /* SPI1_MISO */ +- bias-disable; +- }; +- }; +- +- uart4_pins: uart4-0 { +- pins1 { +- pinmux = ; /* UART4_TX */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = ; /* UART4_RX */ +- bias-disable; +- }; +- }; +- +- usart1_pins: usart1-0 { +- pins1 { +- pinmux = ; /* USART1_TX */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = ; /* USART1_RX */ +- bias-disable; +- }; +- }; +- +- usart2_pins: usart2-0 { +- pins1 { +- pinmux = ; /* USART2_TX */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = ; /* USART2_RX */ +- bias-disable; +- }; +- }; +- +- usart3_pins: usart3-0 { +- pins1 { +- pinmux = , /* USART3_TX */ +- ; /* USART3_RTS_DE */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = , /* USART3_RX */ +- ; /* USART3_CTS_NSS */ +- bias-disable; +- }; +- }; +- +- usbotg_hs_pins_a: usbotg-hs-0 { +- pins { +- pinmux = , /* ULPI_NXT */ +- , /* ULPI_DIR> */ +- , /* ULPI_STP> */ +- , /* ULPI_CK> */ +- , /* ULPI_D0> */ +- , /* ULPI_D1> */ +- , /* ULPI_D2> */ +- , /* ULPI_D3> */ +- , /* ULPI_D4> */ +- , /* ULPI_D5> */ +- , /* ULPI_D6> */ +- ; /* ULPI_D7> */ +- bias-disable; +- drive-push-pull; +- slew-rate = <2>; +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/stm32h743.dtsi b/scripts/dtc/include-prefixes/arm/stm32h743.dtsi +deleted file mode 100644 +index 6e42ca2dada2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32h743.dtsi ++++ /dev/null +@@ -1,733 +0,0 @@ +-/* +- * Copyright 2017 - Alexandre Torgue +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "armv7-m.dtsi" +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- clocks { +- clk_hse: clk-hse { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- clk_lse: clk-lse { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- clk_i2s: i2s_ckin { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- }; +- +- soc { +- timer5: timer@40000c00 { +- compatible = "st,stm32-timer"; +- reg = <0x40000c00 0x400>; +- interrupts = <50>; +- clocks = <&rcc TIM5_CK>; +- }; +- +- lptimer1: timer@40002400 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-lptimer"; +- reg = <0x40002400 0x400>; +- clocks = <&rcc LPTIM1_CK>; +- clock-names = "mux"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- trigger@0 { +- compatible = "st,stm32-lptimer-trigger"; +- reg = <0>; +- status = "disabled"; +- }; +- +- counter { +- compatible = "st,stm32-lptimer-counter"; +- status = "disabled"; +- }; +- }; +- +- spi2: spi@40003800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x40003800 0x400>; +- interrupts = <36>; +- resets = <&rcc STM32H7_APB1L_RESET(SPI2)>; +- clocks = <&rcc SPI2_CK>; +- status = "disabled"; +- +- }; +- +- spi3: spi@40003c00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x40003c00 0x400>; +- interrupts = <51>; +- resets = <&rcc STM32H7_APB1L_RESET(SPI3)>; +- clocks = <&rcc SPI3_CK>; +- status = "disabled"; +- }; +- +- usart2: serial@40004400 { +- compatible = "st,stm32h7-uart"; +- reg = <0x40004400 0x400>; +- interrupts = <38>; +- status = "disabled"; +- clocks = <&rcc USART2_CK>; +- }; +- +- usart3: serial@40004800 { +- compatible = "st,stm32h7-uart"; +- reg = <0x40004800 0x400>; +- interrupts = <39>; +- status = "disabled"; +- clocks = <&rcc USART3_CK>; +- }; +- +- uart4: serial@40004c00 { +- compatible = "st,stm32h7-uart"; +- reg = <0x40004c00 0x400>; +- interrupts = <52>; +- status = "disabled"; +- clocks = <&rcc UART4_CK>; +- }; +- +- i2c1: i2c@40005400 { +- compatible = "st,stm32f7-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x40005400 0x400>; +- interrupts = <31>, +- <32>; +- resets = <&rcc STM32H7_APB1L_RESET(I2C1)>; +- clocks = <&rcc I2C1_CK>; +- status = "disabled"; +- }; +- +- i2c2: i2c@40005800 { +- compatible = "st,stm32f7-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x40005800 0x400>; +- interrupts = <33>, +- <34>; +- resets = <&rcc STM32H7_APB1L_RESET(I2C2)>; +- clocks = <&rcc I2C2_CK>; +- status = "disabled"; +- }; +- +- i2c3: i2c@40005c00 { +- compatible = "st,stm32f7-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x40005C00 0x400>; +- interrupts = <72>, +- <73>; +- resets = <&rcc STM32H7_APB1L_RESET(I2C3)>; +- clocks = <&rcc I2C3_CK>; +- status = "disabled"; +- }; +- +- dac: dac@40007400 { +- compatible = "st,stm32h7-dac-core"; +- reg = <0x40007400 0x400>; +- clocks = <&rcc DAC12_CK>; +- clock-names = "pclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- dac1: dac@1 { +- compatible = "st,stm32-dac"; +- #io-channel-cells = <1>; +- reg = <1>; +- status = "disabled"; +- }; +- +- dac2: dac@2 { +- compatible = "st,stm32-dac"; +- #io-channel-cells = <1>; +- reg = <2>; +- status = "disabled"; +- }; +- }; +- +- usart1: serial@40011000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x40011000 0x400>; +- interrupts = <37>; +- status = "disabled"; +- clocks = <&rcc USART1_CK>; +- }; +- +- spi1: spi@40013000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x40013000 0x400>; +- interrupts = <35>; +- resets = <&rcc STM32H7_APB2_RESET(SPI1)>; +- clocks = <&rcc SPI1_CK>; +- status = "disabled"; +- }; +- +- spi4: spi@40013400 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x40013400 0x400>; +- interrupts = <84>; +- resets = <&rcc STM32H7_APB2_RESET(SPI4)>; +- clocks = <&rcc SPI4_CK>; +- status = "disabled"; +- }; +- +- spi5: spi@40015000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x40015000 0x400>; +- interrupts = <85>; +- resets = <&rcc STM32H7_APB2_RESET(SPI5)>; +- clocks = <&rcc SPI5_CK>; +- status = "disabled"; +- }; +- +- dma1: dma-controller@40020000 { +- compatible = "st,stm32-dma"; +- reg = <0x40020000 0x400>; +- interrupts = <11>, +- <12>, +- <13>, +- <14>, +- <15>, +- <16>, +- <17>, +- <47>; +- clocks = <&rcc DMA1_CK>; +- #dma-cells = <4>; +- st,mem2mem; +- dma-requests = <8>; +- status = "disabled"; +- }; +- +- dma2: dma-controller@40020400 { +- compatible = "st,stm32-dma"; +- reg = <0x40020400 0x400>; +- interrupts = <56>, +- <57>, +- <58>, +- <59>, +- <60>, +- <68>, +- <69>, +- <70>; +- clocks = <&rcc DMA2_CK>; +- #dma-cells = <4>; +- st,mem2mem; +- dma-requests = <8>; +- status = "disabled"; +- }; +- +- dmamux1: dma-router@40020800 { +- compatible = "st,stm32h7-dmamux"; +- reg = <0x40020800 0x40>; +- #dma-cells = <3>; +- dma-channels = <16>; +- dma-requests = <128>; +- dma-masters = <&dma1 &dma2>; +- clocks = <&rcc DMA1_CK>; +- }; +- +- adc_12: adc@40022000 { +- compatible = "st,stm32h7-adc-core"; +- reg = <0x40022000 0x400>; +- interrupts = <18>; +- clocks = <&rcc ADC12_CK>; +- clock-names = "bus"; +- interrupt-controller; +- #interrupt-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- adc1: adc@0 { +- compatible = "st,stm32h7-adc"; +- #io-channel-cells = <1>; +- reg = <0x0>; +- interrupt-parent = <&adc_12>; +- interrupts = <0>; +- status = "disabled"; +- }; +- +- adc2: adc@100 { +- compatible = "st,stm32h7-adc"; +- #io-channel-cells = <1>; +- reg = <0x100>; +- interrupt-parent = <&adc_12>; +- interrupts = <1>; +- status = "disabled"; +- }; +- }; +- +- usbotg_hs: usb@40040000 { +- compatible = "st,stm32f7-hsotg"; +- reg = <0x40040000 0x40000>; +- interrupts = <77>; +- clocks = <&rcc USB1OTG_CK>; +- clock-names = "otg"; +- g-rx-fifo-size = <256>; +- g-np-tx-fifo-size = <32>; +- g-tx-fifo-size = <128 128 64 64 64 64 32 32>; +- status = "disabled"; +- }; +- +- usbotg_fs: usb@40080000 { +- compatible = "st,stm32f4x9-fsotg"; +- reg = <0x40080000 0x40000>; +- interrupts = <101>; +- clocks = <&rcc USB2OTG_CK>; +- clock-names = "otg"; +- status = "disabled"; +- }; +- +- ltdc: display-controller@50001000 { +- compatible = "st,stm32-ltdc"; +- reg = <0x50001000 0x200>; +- interrupts = <88>, <89>; +- resets = <&rcc STM32H7_APB3_RESET(LTDC)>; +- clocks = <&rcc LTDC_CK>; +- clock-names = "lcd"; +- status = "disabled"; +- }; +- +- mdma1: dma-controller@52000000 { +- compatible = "st,stm32h7-mdma"; +- reg = <0x52000000 0x1000>; +- interrupts = <122>; +- clocks = <&rcc MDMA_CK>; +- #dma-cells = <5>; +- dma-channels = <16>; +- dma-requests = <32>; +- }; +- +- sdmmc1: mmc@52007000 { +- compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x10153180>; +- reg = <0x52007000 0x1000>; +- interrupts = <49>; +- interrupt-names = "cmd_irq"; +- clocks = <&rcc SDMMC1_CK>; +- clock-names = "apb_pclk"; +- resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <120000000>; +- }; +- +- sdmmc2: mmc@48022400 { +- compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x10153180>; +- reg = <0x48022400 0x400>; +- interrupts = <124>; +- interrupt-names = "cmd_irq"; +- clocks = <&rcc SDMMC2_CK>; +- clock-names = "apb_pclk"; +- resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <120000000>; +- status = "disabled"; +- }; +- +- exti: interrupt-controller@58000000 { +- compatible = "st,stm32h7-exti"; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x58000000 0x400>; +- interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>; +- }; +- +- syscfg: syscon@58000400 { +- compatible = "st,stm32-syscfg", "syscon"; +- reg = <0x58000400 0x400>; +- }; +- +- spi6: spi@58001400 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x58001400 0x400>; +- interrupts = <86>; +- resets = <&rcc STM32H7_APB4_RESET(SPI6)>; +- clocks = <&rcc SPI6_CK>; +- status = "disabled"; +- }; +- +- i2c4: i2c@58001c00 { +- compatible = "st,stm32f7-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x58001C00 0x400>; +- interrupts = <95>, +- <96>; +- resets = <&rcc STM32H7_APB4_RESET(I2C4)>; +- clocks = <&rcc I2C4_CK>; +- status = "disabled"; +- }; +- +- lptimer2: timer@58002400 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-lptimer"; +- reg = <0x58002400 0x400>; +- clocks = <&rcc LPTIM2_CK>; +- clock-names = "mux"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- trigger@1 { +- compatible = "st,stm32-lptimer-trigger"; +- reg = <1>; +- status = "disabled"; +- }; +- +- counter { +- compatible = "st,stm32-lptimer-counter"; +- status = "disabled"; +- }; +- }; +- +- lptimer3: timer@58002800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-lptimer"; +- reg = <0x58002800 0x400>; +- clocks = <&rcc LPTIM3_CK>; +- clock-names = "mux"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- trigger@2 { +- compatible = "st,stm32-lptimer-trigger"; +- reg = <2>; +- status = "disabled"; +- }; +- }; +- +- lptimer4: timer@58002c00 { +- compatible = "st,stm32-lptimer"; +- reg = <0x58002c00 0x400>; +- clocks = <&rcc LPTIM4_CK>; +- clock-names = "mux"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- }; +- +- lptimer5: timer@58003000 { +- compatible = "st,stm32-lptimer"; +- reg = <0x58003000 0x400>; +- clocks = <&rcc LPTIM5_CK>; +- clock-names = "mux"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- }; +- +- vrefbuf: regulator@58003c00 { +- compatible = "st,stm32-vrefbuf"; +- reg = <0x58003C00 0x8>; +- clocks = <&rcc VREF_CK>; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <2500000>; +- status = "disabled"; +- }; +- +- rtc: rtc@58004000 { +- compatible = "st,stm32h7-rtc"; +- reg = <0x58004000 0x400>; +- clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>; +- clock-names = "pclk", "rtc_ck"; +- assigned-clocks = <&rcc RTC_CK>; +- assigned-clock-parents = <&rcc LSE_CK>; +- interrupt-parent = <&exti>; +- interrupts = <17 IRQ_TYPE_EDGE_RISING>; +- st,syscfg = <&pwrcfg 0x00 0x100>; +- status = "disabled"; +- }; +- +- rcc: reset-clock-controller@58024400 { +- compatible = "st,stm32h743-rcc", "st,stm32-rcc"; +- reg = <0x58024400 0x400>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>; +- st,syscfg = <&pwrcfg>; +- }; +- +- pwrcfg: power-config@58024800 { +- compatible = "st,stm32-power-config", "syscon"; +- reg = <0x58024800 0x400>; +- }; +- +- adc_3: adc@58026000 { +- compatible = "st,stm32h7-adc-core"; +- reg = <0x58026000 0x400>; +- interrupts = <127>; +- clocks = <&rcc ADC3_CK>; +- clock-names = "bus"; +- interrupt-controller; +- #interrupt-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- adc3: adc@0 { +- compatible = "st,stm32h7-adc"; +- #io-channel-cells = <1>; +- reg = <0x0>; +- interrupt-parent = <&adc_3>; +- interrupts = <0>; +- status = "disabled"; +- }; +- }; +- +- mac: ethernet@40028000 { +- compatible = "st,stm32-dwmac", "snps,dwmac-4.10a"; +- reg = <0x40028000 0x8000>; +- reg-names = "stmmaceth"; +- interrupts = <61>; +- interrupt-names = "macirq"; +- clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; +- clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>; +- st,syscon = <&syscfg 0x4>; +- snps,pbl = <8>; +- status = "disabled"; +- }; +- +- pinctrl: pin-controller@58020000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,stm32h743-pinctrl"; +- ranges = <0 0x58020000 0x3000>; +- interrupt-parent = <&exti>; +- st,syscfg = <&syscfg 0x8>; +- pins-are-numbered; +- +- gpioa: gpio@58020000 { +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x0 0x400>; +- clocks = <&rcc GPIOA_CK>; +- st,bank-name = "GPIOA"; +- interrupt-controller; +- #interrupt-cells = <2>; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 0 16>; +- }; +- +- gpiob: gpio@58020400 { +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x400 0x400>; +- clocks = <&rcc GPIOB_CK>; +- st,bank-name = "GPIOB"; +- interrupt-controller; +- #interrupt-cells = <2>; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 16 16>; +- }; +- +- gpioc: gpio@58020800 { +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x800 0x400>; +- clocks = <&rcc GPIOC_CK>; +- st,bank-name = "GPIOC"; +- interrupt-controller; +- #interrupt-cells = <2>; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 32 16>; +- }; +- +- gpiod: gpio@58020c00 { +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0xc00 0x400>; +- clocks = <&rcc GPIOD_CK>; +- st,bank-name = "GPIOD"; +- interrupt-controller; +- #interrupt-cells = <2>; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 48 16>; +- }; +- +- gpioe: gpio@58021000 { +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x1000 0x400>; +- clocks = <&rcc GPIOE_CK>; +- st,bank-name = "GPIOE"; +- interrupt-controller; +- #interrupt-cells = <2>; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 64 16>; +- }; +- +- gpiof: gpio@58021400 { +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x1400 0x400>; +- clocks = <&rcc GPIOF_CK>; +- st,bank-name = "GPIOF"; +- interrupt-controller; +- #interrupt-cells = <2>; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 80 16>; +- }; +- +- gpiog: gpio@58021800 { +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x1800 0x400>; +- clocks = <&rcc GPIOG_CK>; +- st,bank-name = "GPIOG"; +- interrupt-controller; +- #interrupt-cells = <2>; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 96 16>; +- }; +- +- gpioh: gpio@58021c00 { +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x1c00 0x400>; +- clocks = <&rcc GPIOH_CK>; +- st,bank-name = "GPIOH"; +- interrupt-controller; +- #interrupt-cells = <2>; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 112 16>; +- }; +- +- gpioi: gpio@58022000 { +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x2000 0x400>; +- clocks = <&rcc GPIOI_CK>; +- st,bank-name = "GPIOI"; +- interrupt-controller; +- #interrupt-cells = <2>; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 128 16>; +- }; +- +- gpioj: gpio@58022400 { +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x2400 0x400>; +- clocks = <&rcc GPIOJ_CK>; +- st,bank-name = "GPIOJ"; +- interrupt-controller; +- #interrupt-cells = <2>; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 144 16>; +- }; +- +- gpiok: gpio@58022800 { +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x2800 0x400>; +- clocks = <&rcc GPIOK_CK>; +- st,bank-name = "GPIOK"; +- interrupt-controller; +- #interrupt-cells = <2>; +- ngpios = <8>; +- gpio-ranges = <&pinctrl 0 160 8>; +- }; +- }; +- }; +-}; +- +-&systick { +- clock-frequency = <250000000>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32h743i-disco.dts b/scripts/dtc/include-prefixes/arm/stm32h743i-disco.dts +deleted file mode 100644 +index 59e01ce10318..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32h743i-disco.dts ++++ /dev/null +@@ -1,111 +0,0 @@ +-/* +- * Copyright 2017 - Patrice Chotard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "stm32h743.dtsi" +-#include "stm32h7-pinctrl.dtsi" +- +-/ { +- model = "STMicroelectronics STM32H743i-Discovery board"; +- compatible = "st,stm32h743i-disco", "st,stm32h743"; +- +- chosen { +- bootargs = "root=/dev/ram"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@d0000000 { +- device_type = "memory"; +- reg = <0xd0000000 0x2000000>; +- }; +- +- aliases { +- serial0 = &usart2; +- }; +- +- v3v3: regulator-v3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "v3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +-}; +- +-&clk_hse { +- clock-frequency = <25000000>; +-}; +- +-&mac { +- status = "disabled"; +- pinctrl-0 = <ðernet_rmii>; +- pinctrl-names = "default"; +- phy-mode = "rmii"; +- phy-handle = <&phy0>; +- +- mdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +-}; +- +-&sdmmc1 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc1_b4_pins_a>; +- pinctrl-1 = <&sdmmc1_b4_od_pins_a>; +- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; +- broken-cd; +- st,neg-edge; +- bus-width = <4>; +- vmmc-supply = <&v3v3>; +- status = "okay"; +-}; +- +-&usart2 { +- pinctrl-0 = <&usart2_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32h743i-eval.dts b/scripts/dtc/include-prefixes/arm/stm32h743i-eval.dts +deleted file mode 100644 +index 38cc7faf6884..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32h743i-eval.dts ++++ /dev/null +@@ -1,160 +0,0 @@ +-/* +- * Copyright 2017 - Alexandre Torgue +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "stm32h743.dtsi" +-#include "stm32h7-pinctrl.dtsi" +- +-/ { +- model = "STMicroelectronics STM32H743i-EVAL board"; +- compatible = "st,stm32h743i-eval", "st,stm32h743"; +- +- chosen { +- bootargs = "root=/dev/ram"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@d0000000 { +- device_type = "memory"; +- reg = <0xd0000000 0x2000000>; +- }; +- +- aliases { +- serial0 = &usart1; +- }; +- +- vdda: regulator-vdda { +- compatible = "regulator-fixed"; +- regulator-name = "vdda"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- v2v9_sd: regulator-v2v9_sd { +- compatible = "regulator-fixed"; +- regulator-name = "v2v9_sd"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- regulator-always-on; +- }; +- +- usbotg_hs_phy: usb-phy { +- #phy-cells = <0>; +- compatible = "usb-nop-xceiv"; +- clocks = <&rcc USB1ULPI_CK>; +- clock-names = "main_clk"; +- }; +-}; +- +-&adc_12 { +- vdda-supply = <&vdda>; +- vref-supply = <&vdda>; +- status = "okay"; +- adc1: adc@0 { +- /* potentiometer */ +- st,adc-channels = <0>; +- status = "okay"; +- }; +-}; +- +-&clk_hse { +- clock-frequency = <25000000>; +-}; +- +-&i2c1 { +- pinctrl-0 = <&i2c1_pins_a>; +- pinctrl-names = "default"; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&mac { +- status = "disabled"; +- pinctrl-0 = <ðernet_rmii>; +- pinctrl-names = "default"; +- phy-mode = "rmii"; +- phy-handle = <&phy0>; +- +- mdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +-}; +- +-&sdmmc1 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; +- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; +- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; +- broken-cd; +- st,sig-dir; +- st,neg-edge; +- st,use-ckin; +- bus-width = <4>; +- vmmc-supply = <&v2v9_sd>; +- status = "okay"; +-}; +- +-&usart1 { +- pinctrl-0 = <&usart1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&usbotg_hs { +- pinctrl-0 = <&usbotg_hs_pins_a>; +- pinctrl-names = "default"; +- phys = <&usbotg_hs_phy>; +- phy-names = "usb2-phy"; +- dr_mode = "otg"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32h750.dtsi b/scripts/dtc/include-prefixes/arm/stm32h750.dtsi +deleted file mode 100644 +index 41e3b1e3a874..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32h750.dtsi ++++ /dev/null +@@ -1,6 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +-/* Copyright (C) STMicroelectronics 2021 - All Rights Reserved */ +- +-#include "stm32h743.dtsi" +- +- +diff --git a/scripts/dtc/include-prefixes/arm/stm32h750i-art-pi.dts b/scripts/dtc/include-prefixes/arm/stm32h750i-art-pi.dts +deleted file mode 100644 +index 9bb73bb61901..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32h750i-art-pi.dts ++++ /dev/null +@@ -1,229 +0,0 @@ +-/* +- * Copyright 2021 - Dillon Min +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * For art-pi board resources, you can refer to link: +- * https://art-pi.gitee.io/website/ +- */ +- +-/dts-v1/; +-#include "stm32h750.dtsi" +-#include "stm32h7-pinctrl.dtsi" +-#include +-#include +- +-/ { +- model = "RT-Thread STM32H750i-ART-PI board"; +- compatible = "st,stm32h750i-art-pi", "st,stm32h750"; +- +- chosen { +- bootargs = "root=/dev/ram"; +- stdout-path = "serial0:2000000n8"; +- }; +- +- memory@c0000000 { +- device_type = "memory"; +- reg = <0xc0000000 0x2000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- linux,cma { +- compatible = "shared-dma-pool"; +- no-map; +- size = <0x100000>; +- linux,dma-default; +- }; +- }; +- +- aliases { +- serial0 = &uart4; +- serial1 = &usart3; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-red { +- gpios = <&gpioi 8 0>; +- }; +- led-green { +- gpios = <&gpioc 15 0>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- v3v3: regulator-v3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "v3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- wlan_pwr: regulator-wlan { +- compatible = "regulator-fixed"; +- +- regulator-name = "wl-reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&clk_hse { +- clock-frequency = <25000000>; +-}; +- +-&dma1 { +- status = "okay"; +-}; +- +-&dma2 { +- status = "okay"; +-}; +- +-&mac { +- status = "disabled"; +- pinctrl-0 = <ðernet_rmii>; +- pinctrl-names = "default"; +- phy-mode = "rmii"; +- phy-handle = <&phy0>; +- +- mdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +-}; +- +-&sdmmc1 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc1_b4_pins_a>; +- pinctrl-1 = <&sdmmc1_b4_od_pins_a>; +- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; +- broken-cd; +- st,neg-edge; +- bus-width = <4>; +- vmmc-supply = <&v3v3>; +- status = "okay"; +-}; +- +-&sdmmc2 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc2_b4_pins_a>; +- pinctrl-1 = <&sdmmc2_b4_od_pins_a>; +- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; +- broken-cd; +- non-removable; +- st,neg-edge; +- bus-width = <4>; +- vmmc-supply = <&wlan_pwr>; +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- brcmf: bcrmf@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-&spi1 { +- status = "okay"; +- pinctrl-0 = <&spi1_pins>; +- pinctrl-names = "default"; +- cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; +- dmas = <&dmamux1 37 0x400 0x05>, +- <&dmamux1 38 0x400 0x05>; +- dma-names = "rx", "tx"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "winbond,w25q128", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <80000000>; +- +- partition@0 { +- label = "root filesystem"; +- reg = <0 0x1000000>; +- }; +- }; +-}; +- +-&usart2 { +- pinctrl-0 = <&usart2_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +-}; +- +-&usart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usart3_pins>; +- dmas = <&dmamux1 45 0x400 0x05>, +- <&dmamux1 46 0x400 0x05>; +- dma-names = "rx", "tx"; +- st,hw-flow-ctrl; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- host-wakeup-gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>; +- device-wakeup-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>; +- max-speed = <115200>; +- }; +-}; +- +-&uart4 { +- pinctrl-0 = <&uart4_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +- +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp15-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp15-pinctrl.dtsi +deleted file mode 100644 +index 2ebafe27a865..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp15-pinctrl.dtsi ++++ /dev/null +@@ -1,2123 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved +- * Author: Ludovic Barre for STMicroelectronics. +- */ +-#include +- +-&pinctrl { +- adc1_in6_pins_a: adc1-in6-0 { +- pins { +- pinmux = ; +- }; +- }; +- +- adc12_ain_pins_a: adc12-ain-0 { +- pins { +- pinmux = , /* ADC1 in13 */ +- , /* ADC1 in6 */ +- , /* ADC2 in2 */ +- ; /* ADC2 in6 */ +- }; +- }; +- +- adc12_ain_pins_b: adc12-ain-1 { +- pins { +- pinmux = , /* ADC1 in6 */ +- ; /* ADC2 in2 */ +- }; +- }; +- +- adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { +- pins { +- pinmux = , /* ADC12 in18 */ +- ; /* ADC12 in19 */ +- }; +- }; +- +- cec_pins_a: cec-0 { +- pins { +- pinmux = ; +- bias-disable; +- drive-open-drain; +- slew-rate = <0>; +- }; +- }; +- +- cec_sleep_pins_a: cec-sleep-0 { +- pins { +- pinmux = ; /* HDMI_CEC */ +- }; +- }; +- +- cec_pins_b: cec-1 { +- pins { +- pinmux = ; +- bias-disable; +- drive-open-drain; +- slew-rate = <0>; +- }; +- }; +- +- cec_sleep_pins_b: cec-sleep-1 { +- pins { +- pinmux = ; /* HDMI_CEC */ +- }; +- }; +- +- dac_ch1_pins_a: dac-ch1-0 { +- pins { +- pinmux = ; +- }; +- }; +- +- dac_ch2_pins_a: dac-ch2-0 { +- pins { +- pinmux = ; +- }; +- }; +- +- dcmi_pins_a: dcmi-0 { +- pins { +- pinmux = ,/* DCMI_HSYNC */ +- ,/* DCMI_VSYNC */ +- ,/* DCMI_PIXCLK */ +- ,/* DCMI_D0 */ +- ,/* DCMI_D1 */ +- ,/* DCMI_D2 */ +- ,/* DCMI_D3 */ +- ,/* DCMI_D4 */ +- ,/* DCMI_D5 */ +- ,/* DCMI_D6 */ +- ,/* DCMI_D7 */ +- ,/* DCMI_D8 */ +- ,/* DCMI_D9 */ +- ,/* DCMI_D10 */ +- ;/* DCMI_D11 */ +- bias-disable; +- }; +- }; +- +- dcmi_sleep_pins_a: dcmi-sleep-0 { +- pins { +- pinmux = ,/* DCMI_HSYNC */ +- ,/* DCMI_VSYNC */ +- ,/* DCMI_PIXCLK */ +- ,/* DCMI_D0 */ +- ,/* DCMI_D1 */ +- ,/* DCMI_D2 */ +- ,/* DCMI_D3 */ +- ,/* DCMI_D4 */ +- ,/* DCMI_D5 */ +- ,/* DCMI_D6 */ +- ,/* DCMI_D7 */ +- ,/* DCMI_D8 */ +- ,/* DCMI_D9 */ +- ,/* DCMI_D10 */ +- ;/* DCMI_D11 */ +- }; +- }; +- +- dcmi_pins_b: dcmi-1 { +- pins { +- pinmux = ,/* DCMI_HSYNC */ +- ,/* DCMI_VSYNC */ +- ,/* DCMI_PIXCLK */ +- ,/* DCMI_D0 */ +- ,/* DCMI_D1 */ +- ,/* DCMI_D2 */ +- ,/* DCMI_D3 */ +- ,/* DCMI_D4 */ +- ,/* DCMI_D5 */ +- ,/* DCMI_D6 */ +- ;/* DCMI_D7 */ +- bias-disable; +- }; +- }; +- +- dcmi_sleep_pins_b: dcmi-sleep-1 { +- pins { +- pinmux = ,/* DCMI_HSYNC */ +- ,/* DCMI_VSYNC */ +- ,/* DCMI_PIXCLK */ +- ,/* DCMI_D0 */ +- ,/* DCMI_D1 */ +- ,/* DCMI_D2 */ +- ,/* DCMI_D3 */ +- ,/* DCMI_D4 */ +- ,/* DCMI_D5 */ +- ,/* DCMI_D6 */ +- ;/* DCMI_D7 */ +- }; +- }; +- +- ethernet0_rgmii_pins_a: rgmii-0 { +- pins1 { +- pinmux = , /* ETH_RGMII_CLK125 */ +- , /* ETH_RGMII_GTX_CLK */ +- , /* ETH_RGMII_TXD0 */ +- , /* ETH_RGMII_TXD1 */ +- , /* ETH_RGMII_TXD2 */ +- , /* ETH_RGMII_TXD3 */ +- , /* ETH_RGMII_TX_CTL */ +- ; /* ETH_MDC */ +- bias-disable; +- drive-push-pull; +- slew-rate = <2>; +- }; +- pins2 { +- pinmux = ; /* ETH_MDIO */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins3 { +- pinmux = , /* ETH_RGMII_RXD0 */ +- , /* ETH_RGMII_RXD1 */ +- , /* ETH_RGMII_RXD2 */ +- , /* ETH_RGMII_RXD3 */ +- , /* ETH_RGMII_RX_CLK */ +- ; /* ETH_RGMII_RX_CTL */ +- bias-disable; +- }; +- }; +- +- ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 { +- pins1 { +- pinmux = , /* ETH_RGMII_CLK125 */ +- , /* ETH_RGMII_GTX_CLK */ +- , /* ETH_RGMII_TXD0 */ +- , /* ETH_RGMII_TXD1 */ +- , /* ETH_RGMII_TXD2 */ +- , /* ETH_RGMII_TXD3 */ +- , /* ETH_RGMII_TX_CTL */ +- , /* ETH_MDIO */ +- , /* ETH_MDC */ +- , /* ETH_RGMII_RXD0 */ +- , /* ETH_RGMII_RXD1 */ +- , /* ETH_RGMII_RXD2 */ +- , /* ETH_RGMII_RXD3 */ +- , /* ETH_RGMII_RX_CLK */ +- ; /* ETH_RGMII_RX_CTL */ +- }; +- }; +- +- ethernet0_rgmii_pins_b: rgmii-1 { +- pins1 { +- pinmux = , /* ETH_RGMII_CLK125 */ +- , /* ETH_RGMII_GTX_CLK */ +- , /* ETH_RGMII_TXD0 */ +- , /* ETH_RGMII_TXD1 */ +- , /* ETH_RGMII_TXD2 */ +- , /* ETH_RGMII_TXD3 */ +- , /* ETH_RGMII_TX_CTL */ +- ; /* ETH_MDC */ +- bias-disable; +- drive-push-pull; +- slew-rate = <2>; +- }; +- pins2 { +- pinmux = ; /* ETH_MDIO */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins3 { +- pinmux = , /* ETH_RGMII_RXD0 */ +- , /* ETH_RGMII_RXD1 */ +- , /* ETH_RGMII_RXD2 */ +- , /* ETH_RGMII_RXD3 */ +- , /* ETH_RGMII_RX_CLK */ +- ; /* ETH_RGMII_RX_CTL */ +- bias-disable; +- }; +- }; +- +- ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 { +- pins1 { +- pinmux = , /* ETH_RGMII_CLK125 */ +- , /* ETH_RGMII_GTX_CLK */ +- , /* ETH_RGMII_TXD0 */ +- , /* ETH_RGMII_TXD1 */ +- , /* ETH_RGMII_TXD2 */ +- , /* ETH_RGMII_TXD3 */ +- , /* ETH_RGMII_TX_CTL */ +- , /* ETH_MDC */ +- , /* ETH_MDIO */ +- , /* ETH_RGMII_RXD0 */ +- , /* ETH_RGMII_RXD1 */ +- , /* ETH_RGMII_RXD2 */ +- , /* ETH_RGMII_RXD3 */ +- , /* ETH_RGMII_RX_CLK */ +- ; /* ETH_RGMII_RX_CTL */ +- }; +- }; +- +- ethernet0_rgmii_pins_c: rgmii-2 { +- pins1 { +- pinmux = , /* ETH_RGMII_CLK125 */ +- , /* ETH_RGMII_GTX_CLK */ +- , /* ETH_RGMII_TXD0 */ +- , /* ETH_RGMII_TXD1 */ +- , /* ETH_RGMII_TXD2 */ +- , /* ETH_RGMII_TXD3 */ +- , /* ETH_RGMII_TX_CTL */ +- ; /* ETH_MDC */ +- bias-disable; +- drive-push-pull; +- slew-rate = <2>; +- }; +- pins2 { +- pinmux = ; /* ETH_MDIO */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins3 { +- pinmux = , /* ETH_RGMII_RXD0 */ +- , /* ETH_RGMII_RXD1 */ +- , /* ETH_RGMII_RXD2 */ +- , /* ETH_RGMII_RXD3 */ +- , /* ETH_RGMII_RX_CLK */ +- ; /* ETH_RGMII_RX_CTL */ +- bias-disable; +- }; +- }; +- +- ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 { +- pins1 { +- pinmux = , /* ETH_RGMII_CLK125 */ +- , /* ETH_RGMII_GTX_CLK */ +- , /* ETH_RGMII_TXD0 */ +- , /* ETH_RGMII_TXD1 */ +- , /* ETH_RGMII_TXD2 */ +- , /* ETH_RGMII_TXD3 */ +- , /* ETH_RGMII_TX_CTL */ +- , /* ETH_MDIO */ +- , /* ETH_MDC */ +- , /* ETH_RGMII_RXD0 */ +- , /* ETH_RGMII_RXD1 */ +- , /* ETH_RGMII_RXD2 */ +- , /* ETH_RGMII_RXD3 */ +- , /* ETH_RGMII_RX_CLK */ +- ; /* ETH_RGMII_RX_CTL */ +- }; +- }; +- +- ethernet0_rmii_pins_a: rmii-0 { +- pins1 { +- pinmux = , /* ETH1_RMII_TXD0 */ +- , /* ETH1_RMII_TXD1 */ +- , /* ETH1_RMII_TX_EN */ +- , /* ETH1_RMII_REF_CLK */ +- , /* ETH1_MDIO */ +- ; /* ETH1_MDC */ +- bias-disable; +- drive-push-pull; +- slew-rate = <2>; +- }; +- pins2 { +- pinmux = , /* ETH1_RMII_RXD0 */ +- , /* ETH1_RMII_RXD1 */ +- ; /* ETH1_RMII_CRS_DV */ +- bias-disable; +- }; +- }; +- +- ethernet0_rmii_sleep_pins_a: rmii-sleep-0 { +- pins1 { +- pinmux = , /* ETH1_RMII_TXD0 */ +- , /* ETH1_RMII_TXD1 */ +- , /* ETH1_RMII_TX_EN */ +- , /* ETH1_MDIO */ +- , /* ETH1_MDC */ +- , /* ETH1_RMII_RXD0 */ +- , /* ETH1_RMII_RXD1 */ +- , /* ETH1_RMII_REF_CLK */ +- ; /* ETH1_RMII_CRS_DV */ +- }; +- }; +- +- fmc_pins_a: fmc-0 { +- pins1 { +- pinmux = , /* FMC_NOE */ +- , /* FMC_NWE */ +- , /* FMC_A16_FMC_CLE */ +- , /* FMC_A17_FMC_ALE */ +- , /* FMC_D0 */ +- , /* FMC_D1 */ +- , /* FMC_D2 */ +- , /* FMC_D3 */ +- , /* FMC_D4 */ +- , /* FMC_D5 */ +- , /* FMC_D6 */ +- , /* FMC_D7 */ +- ; /* FMC_NE2_FMC_NCE */ +- bias-disable; +- drive-push-pull; +- slew-rate = <1>; +- }; +- pins2 { +- pinmux = ; /* FMC_NWAIT */ +- bias-pull-up; +- }; +- }; +- +- fmc_sleep_pins_a: fmc-sleep-0 { +- pins { +- pinmux = , /* FMC_NOE */ +- , /* FMC_NWE */ +- , /* FMC_A16_FMC_CLE */ +- , /* FMC_A17_FMC_ALE */ +- , /* FMC_D0 */ +- , /* FMC_D1 */ +- , /* FMC_D2 */ +- , /* FMC_D3 */ +- , /* FMC_D4 */ +- , /* FMC_D5 */ +- , /* FMC_D6 */ +- , /* FMC_D7 */ +- , /* FMC_NWAIT */ +- ; /* FMC_NE2_FMC_NCE */ +- }; +- }; +- +- fmc_pins_b: fmc-1 { +- pins { +- pinmux = , /* FMC_NOE */ +- , /* FMC_NWE */ +- , /* FMC_NL */ +- , /* FMC_D0 */ +- , /* FMC_D1 */ +- , /* FMC_D2 */ +- , /* FMC_D3 */ +- , /* FMC_D4 */ +- , /* FMC_D5 */ +- , /* FMC_D6 */ +- , /* FMC_D7 */ +- , /* FMC_D8 */ +- , /* FMC_D9 */ +- , /* FMC_D10 */ +- , /* FMC_D11 */ +- , /* FMC_D12 */ +- , /* FMC_D13 */ +- , /* FMC_D14 */ +- , /* FMC_D15 */ +- , /* FMC_NE2_FMC_NCE */ +- ; /* FMC_NE4 */ +- bias-disable; +- drive-push-pull; +- slew-rate = <3>; +- }; +- }; +- +- fmc_sleep_pins_b: fmc-sleep-1 { +- pins { +- pinmux = , /* FMC_NOE */ +- , /* FMC_NWE */ +- , /* FMC_NL */ +- , /* FMC_D0 */ +- , /* FMC_D1 */ +- , /* FMC_D2 */ +- , /* FMC_D3 */ +- , /* FMC_D4 */ +- , /* FMC_D5 */ +- , /* FMC_D6 */ +- , /* FMC_D7 */ +- , /* FMC_D8 */ +- , /* FMC_D9 */ +- , /* FMC_D10 */ +- , /* FMC_D11 */ +- , /* FMC_D12 */ +- , /* FMC_D13 */ +- , /* FMC_D14 */ +- , /* FMC_D15 */ +- , /* FMC_NE2_FMC_NCE */ +- ; /* FMC_NE4 */ +- }; +- }; +- +- i2c1_pins_a: i2c1-0 { +- pins { +- pinmux = , /* I2C1_SCL */ +- ; /* I2C1_SDA */ +- bias-disable; +- drive-open-drain; +- slew-rate = <0>; +- }; +- }; +- +- i2c1_sleep_pins_a: i2c1-sleep-0 { +- pins { +- pinmux = , /* I2C1_SCL */ +- ; /* I2C1_SDA */ +- }; +- }; +- +- i2c1_pins_b: i2c1-1 { +- pins { +- pinmux = , /* I2C1_SCL */ +- ; /* I2C1_SDA */ +- bias-disable; +- drive-open-drain; +- slew-rate = <0>; +- }; +- }; +- +- i2c1_sleep_pins_b: i2c1-sleep-1 { +- pins { +- pinmux = , /* I2C1_SCL */ +- ; /* I2C1_SDA */ +- }; +- }; +- +- i2c2_pins_a: i2c2-0 { +- pins { +- pinmux = , /* I2C2_SCL */ +- ; /* I2C2_SDA */ +- bias-disable; +- drive-open-drain; +- slew-rate = <0>; +- }; +- }; +- +- i2c2_sleep_pins_a: i2c2-sleep-0 { +- pins { +- pinmux = , /* I2C2_SCL */ +- ; /* I2C2_SDA */ +- }; +- }; +- +- i2c2_pins_b1: i2c2-1 { +- pins { +- pinmux = ; /* I2C2_SDA */ +- bias-disable; +- drive-open-drain; +- slew-rate = <0>; +- }; +- }; +- +- i2c2_sleep_pins_b1: i2c2-sleep-1 { +- pins { +- pinmux = ; /* I2C2_SDA */ +- }; +- }; +- +- i2c2_pins_c: i2c2-2 { +- pins { +- pinmux = , /* I2C2_SCL */ +- ; /* I2C2_SDA */ +- bias-disable; +- drive-open-drain; +- slew-rate = <0>; +- }; +- }; +- +- i2c2_pins_sleep_c: i2c2-sleep-2 { +- pins { +- pinmux = , /* I2C2_SCL */ +- ; /* I2C2_SDA */ +- }; +- }; +- +- i2c5_pins_a: i2c5-0 { +- pins { +- pinmux = , /* I2C5_SCL */ +- ; /* I2C5_SDA */ +- bias-disable; +- drive-open-drain; +- slew-rate = <0>; +- }; +- }; +- +- i2c5_sleep_pins_a: i2c5-sleep-0 { +- pins { +- pinmux = , /* I2C5_SCL */ +- ; /* I2C5_SDA */ +- +- }; +- }; +- +- i2c5_pins_b: i2c5-1 { +- pins { +- pinmux = , /* I2C5_SCL */ +- ; /* I2C5_SDA */ +- bias-disable; +- drive-open-drain; +- slew-rate = <0>; +- }; +- }; +- +- i2c5_sleep_pins_b: i2c5-sleep-1 { +- pins { +- pinmux = , /* I2C5_SCL */ +- ; /* I2C5_SDA */ +- }; +- }; +- +- i2s2_pins_a: i2s2-0 { +- pins { +- pinmux = , /* I2S2_SDO */ +- , /* I2S2_WS */ +- ; /* I2S2_CK */ +- slew-rate = <1>; +- drive-push-pull; +- bias-disable; +- }; +- }; +- +- i2s2_sleep_pins_a: i2s2-sleep-0 { +- pins { +- pinmux = , /* I2S2_SDO */ +- , /* I2S2_WS */ +- ; /* I2S2_CK */ +- }; +- }; +- +- ltdc_pins_a: ltdc-0 { +- pins { +- pinmux = , /* LCD_CLK */ +- , /* LCD_HSYNC */ +- , /* LCD_VSYNC */ +- , /* LCD_DE */ +- , /* LCD_R0 */ +- , /* LCD_R1 */ +- , /* LCD_R2 */ +- , /* LCD_R3 */ +- , /* LCD_R4 */ +- , /* LCD_R5 */ +- , /* LCD_R6 */ +- , /* LCD_R7 */ +- , /* LCD_G0 */ +- , /* LCD_G1 */ +- , /* LCD_G2 */ +- , /* LCD_G3 */ +- , /* LCD_G4 */ +- , /* LCD_G5 */ +- , /* LCD_G6 */ +- , /* LCD_G7 */ +- , /* LCD_B0 */ +- , /* LCD_B1 */ +- , /* LCD_B2 */ +- , /* LCD_B3 */ +- , /* LCD_B4 */ +- , /* LCD_B5 */ +- , /* LCD_B6 */ +- ; /* LCD_B7 */ +- bias-disable; +- drive-push-pull; +- slew-rate = <1>; +- }; +- }; +- +- ltdc_sleep_pins_a: ltdc-sleep-0 { +- pins { +- pinmux = , /* LCD_CLK */ +- , /* LCD_HSYNC */ +- , /* LCD_VSYNC */ +- , /* LCD_DE */ +- , /* LCD_R0 */ +- , /* LCD_R1 */ +- , /* LCD_R2 */ +- , /* LCD_R3 */ +- , /* LCD_R4 */ +- , /* LCD_R5 */ +- , /* LCD_R6 */ +- , /* LCD_R7 */ +- , /* LCD_G0 */ +- , /* LCD_G1 */ +- , /* LCD_G2 */ +- , /* LCD_G3 */ +- , /* LCD_G4 */ +- , /* LCD_G5 */ +- , /* LCD_G6 */ +- , /* LCD_G7 */ +- , /* LCD_B0 */ +- , /* LCD_B1 */ +- , /* LCD_B2 */ +- , /* LCD_B3 */ +- , /* LCD_B4 */ +- , /* LCD_B5 */ +- , /* LCD_B6 */ +- ; /* LCD_B7 */ +- }; +- }; +- +- ltdc_pins_b: ltdc-1 { +- pins { +- pinmux = , /* LCD_CLK */ +- , /* LCD_HSYNC */ +- , /* LCD_VSYNC */ +- , /* LCD_DE */ +- , /* LCD_R0 */ +- , /* LCD_R1 */ +- , /* LCD_R2 */ +- , /* LCD_R3 */ +- , /* LCD_R4 */ +- , /* LCD_R5 */ +- , /* LCD_R6 */ +- , /* LCD_R7 */ +- , /* LCD_G0 */ +- , /* LCD_G1 */ +- , /* LCD_G2 */ +- , /* LCD_G3 */ +- , /* LCD_G4 */ +- , /* LCD_G5 */ +- , /* LCD_G6 */ +- , /* LCD_G7 */ +- , /* LCD_B0 */ +- , /* LCD_B1 */ +- , /* LCD_B2 */ +- , /* LCD_B3 */ +- , /* LCD_B4 */ +- , /* LCD_B5 */ +- , /* LCD_B6 */ +- ; /* LCD_B7 */ +- bias-disable; +- drive-push-pull; +- slew-rate = <1>; +- }; +- }; +- +- ltdc_sleep_pins_b: ltdc-sleep-1 { +- pins { +- pinmux = , /* LCD_CLK */ +- , /* LCD_HSYNC */ +- , /* LCD_VSYNC */ +- , /* LCD_DE */ +- , /* LCD_R0 */ +- , /* LCD_R1 */ +- , /* LCD_R2 */ +- , /* LCD_R3 */ +- , /* LCD_R4 */ +- , /* LCD_R5 */ +- , /* LCD_R6 */ +- , /* LCD_R7 */ +- , /* LCD_G0 */ +- , /* LCD_G1 */ +- , /* LCD_G2 */ +- , /* LCD_G3 */ +- , /* LCD_G4 */ +- , /* LCD_G5 */ +- , /* LCD_G6 */ +- , /* LCD_G7 */ +- , /* LCD_B0 */ +- , /* LCD_B1 */ +- , /* LCD_B2 */ +- , /* LCD_B3 */ +- , /* LCD_B4 */ +- , /* LCD_B5 */ +- , /* LCD_B6 */ +- ; /* LCD_B7 */ +- }; +- }; +- +- ltdc_pins_c: ltdc-2 { +- pins1 { +- pinmux = , /* LTDC_R6 */ +- , /* LTDC_B7 */ +- , /* LTDC_R5 */ +- , /* LTDC_G7 */ +- , /* LTDC_B2 */ +- , /* LTDC_B3 */ +- , /* LTDC_G3 */ +- , /* LTDC_B4 */ +- , /* LTDC_DE */ +- , /* LTDC_R7 */ +- , /* LTDC_G5 */ +- , /* LTDC_R2 */ +- , /* LTDC_R3 */ +- , /* LTDC_R4 */ +- , /* LTDC_G2 */ +- , /* LTDC_G4 */ +- , /* LTDC_G6 */ +- , /* LTDC_B5 */ +- , /* LTDC_B6 */ +- , /* LTDC_VSYNC */ +- ; /* LTDC_HSYNC */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = ; /* LTDC_CLK */ +- bias-disable; +- drive-push-pull; +- slew-rate = <1>; +- }; +- }; +- +- ltdc_sleep_pins_c: ltdc-sleep-2 { +- pins1 { +- pinmux = , /* LTDC_R6 */ +- , /* LTDC_B7 */ +- , /* LTDC_R5 */ +- , /* LTDC_G7 */ +- , /* LTDC_B2 */ +- , /* LTDC_B3 */ +- , /* LTDC_G3 */ +- , /* LTDC_B4 */ +- , /* LTDC_DE */ +- , /* LTDC_R7 */ +- , /* LTDC_G5 */ +- , /* LTDC_R2 */ +- , /* LTDC_R3 */ +- , /* LTDC_R4 */ +- , /* LTDC_G2 */ +- , /* LTDC_G4 */ +- , /* LTDC_G6 */ +- , /* LTDC_B5 */ +- , /* LTDC_B6 */ +- , /* LTDC_VSYNC */ +- , /* LTDC_HSYNC */ +- ; /* LTDC_CLK */ +- }; +- }; +- +- ltdc_pins_d: ltdc-3 { +- pins1 { +- pinmux = ; /* LCD_CLK */ +- bias-disable; +- drive-push-pull; +- slew-rate = <3>; +- }; +- pins2 { +- pinmux = , /* LCD_HSYNC */ +- , /* LCD_VSYNC */ +- , /* LCD_DE */ +- , /* LCD_R0 */ +- , /* LCD_R1 */ +- , /* LCD_R2 */ +- , /* LCD_R3 */ +- , /* LCD_R4 */ +- , /* LCD_R5 */ +- , /* LCD_R6 */ +- , /* LCD_R7 */ +- , /* LCD_G0 */ +- , /* LCD_G1 */ +- , /* LCD_G2 */ +- , /* LCD_G3 */ +- , /* LCD_G4 */ +- , /* LCD_G5 */ +- , /* LCD_G6 */ +- , /* LCD_G7 */ +- , /* LCD_B0 */ +- , /* LCD_B1 */ +- , /* LCD_B2 */ +- , /* LCD_B3 */ +- , /* LCD_B4 */ +- , /* LCD_B5 */ +- , /* LCD_B6 */ +- ; /* LCD_B7 */ +- bias-disable; +- drive-push-pull; +- slew-rate = <2>; +- }; +- }; +- +- ltdc_sleep_pins_d: ltdc-sleep-3 { +- pins { +- pinmux = , /* LCD_CLK */ +- , /* LCD_HSYNC */ +- , /* LCD_VSYNC */ +- , /* LCD_DE */ +- , /* LCD_R0 */ +- , /* LCD_R1 */ +- , /* LCD_R2 */ +- , /* LCD_R3 */ +- , /* LCD_R4 */ +- , /* LCD_R5 */ +- , /* LCD_R6 */ +- , /* LCD_R7 */ +- , /* LCD_G0 */ +- , /* LCD_G1 */ +- , /* LCD_G2 */ +- , /* LCD_G3 */ +- , /* LCD_G4 */ +- , /* LCD_G5 */ +- , /* LCD_G6 */ +- , /* LCD_G7 */ +- , /* LCD_B0 */ +- , /* LCD_B1 */ +- , /* LCD_B2 */ +- , /* LCD_B3 */ +- , /* LCD_B4 */ +- , /* LCD_B5 */ +- , /* LCD_B6 */ +- ; /* LCD_B7 */ +- }; +- }; +- +- m_can1_pins_a: m-can1-0 { +- pins1 { +- pinmux = ; /* CAN1_TX */ +- slew-rate = <1>; +- drive-push-pull; +- bias-disable; +- }; +- pins2 { +- pinmux = ; /* CAN1_RX */ +- bias-disable; +- }; +- }; +- +- m_can1_sleep_pins_a: m_can1-sleep-0 { +- pins { +- pinmux = , /* CAN1_TX */ +- ; /* CAN1_RX */ +- }; +- }; +- +- m_can1_pins_b: m-can1-1 { +- pins1 { +- pinmux = ; /* CAN1_TX */ +- slew-rate = <1>; +- drive-push-pull; +- bias-disable; +- }; +- pins2 { +- pinmux = ; /* CAN1_RX */ +- bias-disable; +- }; +- }; +- +- m_can1_sleep_pins_b: m_can1-sleep-1 { +- pins { +- pinmux = , /* CAN1_TX */ +- ; /* CAN1_RX */ +- }; +- }; +- +- m_can2_pins_a: m-can2-0 { +- pins1 { +- pinmux = ; /* CAN2_TX */ +- slew-rate = <1>; +- drive-push-pull; +- bias-disable; +- }; +- pins2 { +- pinmux = ; /* CAN2_RX */ +- bias-disable; +- }; +- }; +- +- m_can2_sleep_pins_a: m_can2-sleep-0 { +- pins { +- pinmux = , /* CAN2_TX */ +- ; /* CAN2_RX */ +- }; +- }; +- +- pwm1_pins_a: pwm1-0 { +- pins { +- pinmux = , /* TIM1_CH1 */ +- , /* TIM1_CH2 */ +- ; /* TIM1_CH4 */ +- bias-pull-down; +- drive-push-pull; +- slew-rate = <0>; +- }; +- }; +- +- pwm1_sleep_pins_a: pwm1-sleep-0 { +- pins { +- pinmux = , /* TIM1_CH1 */ +- , /* TIM1_CH2 */ +- ; /* TIM1_CH4 */ +- }; +- }; +- +- pwm2_pins_a: pwm2-0 { +- pins { +- pinmux = ; /* TIM2_CH4 */ +- bias-pull-down; +- drive-push-pull; +- slew-rate = <0>; +- }; +- }; +- +- pwm2_sleep_pins_a: pwm2-sleep-0 { +- pins { +- pinmux = ; /* TIM2_CH4 */ +- }; +- }; +- +- pwm3_pins_a: pwm3-0 { +- pins { +- pinmux = ; /* TIM3_CH2 */ +- bias-pull-down; +- drive-push-pull; +- slew-rate = <0>; +- }; +- }; +- +- pwm3_sleep_pins_a: pwm3-sleep-0 { +- pins { +- pinmux = ; /* TIM3_CH2 */ +- }; +- }; +- +- pwm3_pins_b: pwm3-1 { +- pins { +- pinmux = ; /* TIM3_CH2 */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- }; +- +- pwm3_sleep_pins_b: pwm3-sleep-1 { +- pins { +- pinmux = ; /* TIM3_CH2 */ +- }; +- }; +- +- pwm4_pins_a: pwm4-0 { +- pins { +- pinmux = , /* TIM4_CH3 */ +- ; /* TIM4_CH4 */ +- bias-pull-down; +- drive-push-pull; +- slew-rate = <0>; +- }; +- }; +- +- pwm4_sleep_pins_a: pwm4-sleep-0 { +- pins { +- pinmux = , /* TIM4_CH3 */ +- ; /* TIM4_CH4 */ +- }; +- }; +- +- pwm4_pins_b: pwm4-1 { +- pins { +- pinmux = ; /* TIM4_CH2 */ +- bias-pull-down; +- drive-push-pull; +- slew-rate = <0>; +- }; +- }; +- +- pwm4_sleep_pins_b: pwm4-sleep-1 { +- pins { +- pinmux = ; /* TIM4_CH2 */ +- }; +- }; +- +- pwm5_pins_a: pwm5-0 { +- pins { +- pinmux = ; /* TIM5_CH2 */ +- bias-pull-down; +- drive-push-pull; +- slew-rate = <0>; +- }; +- }; +- +- pwm5_sleep_pins_a: pwm5-sleep-0 { +- pins { +- pinmux = ; /* TIM5_CH2 */ +- }; +- }; +- +- pwm5_pins_b: pwm5-1 { +- pins { +- pinmux = , /* TIM5_CH2 */ +- , /* TIM5_CH3 */ +- ; /* TIM5_CH4 */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- }; +- +- pwm5_sleep_pins_b: pwm5-sleep-1 { +- pins { +- pinmux = , /* TIM5_CH2 */ +- , /* TIM5_CH3 */ +- ; /* TIM5_CH4 */ +- }; +- }; +- +- pwm8_pins_a: pwm8-0 { +- pins { +- pinmux = ; /* TIM8_CH4 */ +- bias-pull-down; +- drive-push-pull; +- slew-rate = <0>; +- }; +- }; +- +- pwm8_sleep_pins_a: pwm8-sleep-0 { +- pins { +- pinmux = ; /* TIM8_CH4 */ +- }; +- }; +- +- pwm12_pins_a: pwm12-0 { +- pins { +- pinmux = ; /* TIM12_CH1 */ +- bias-pull-down; +- drive-push-pull; +- slew-rate = <0>; +- }; +- }; +- +- pwm12_sleep_pins_a: pwm12-sleep-0 { +- pins { +- pinmux = ; /* TIM12_CH1 */ +- }; +- }; +- +- qspi_clk_pins_a: qspi-clk-0 { +- pins { +- pinmux = ; /* QSPI_CLK */ +- bias-disable; +- drive-push-pull; +- slew-rate = <3>; +- }; +- }; +- +- qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { +- pins { +- pinmux = ; /* QSPI_CLK */ +- }; +- }; +- +- qspi_bk1_pins_a: qspi-bk1-0 { +- pins1 { +- pinmux = , /* QSPI_BK1_IO0 */ +- , /* QSPI_BK1_IO1 */ +- , /* QSPI_BK1_IO2 */ +- ; /* QSPI_BK1_IO3 */ +- bias-disable; +- drive-push-pull; +- slew-rate = <1>; +- }; +- pins2 { +- pinmux = ; /* QSPI_BK1_NCS */ +- bias-pull-up; +- drive-push-pull; +- slew-rate = <1>; +- }; +- }; +- +- qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { +- pins { +- pinmux = , /* QSPI_BK1_IO0 */ +- , /* QSPI_BK1_IO1 */ +- , /* QSPI_BK1_IO2 */ +- , /* QSPI_BK1_IO3 */ +- ; /* QSPI_BK1_NCS */ +- }; +- }; +- +- qspi_bk2_pins_a: qspi-bk2-0 { +- pins1 { +- pinmux = , /* QSPI_BK2_IO0 */ +- , /* QSPI_BK2_IO1 */ +- , /* QSPI_BK2_IO2 */ +- ; /* QSPI_BK2_IO3 */ +- bias-disable; +- drive-push-pull; +- slew-rate = <1>; +- }; +- pins2 { +- pinmux = ; /* QSPI_BK2_NCS */ +- bias-pull-up; +- drive-push-pull; +- slew-rate = <1>; +- }; +- }; +- +- qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { +- pins { +- pinmux = , /* QSPI_BK2_IO0 */ +- , /* QSPI_BK2_IO1 */ +- , /* QSPI_BK2_IO2 */ +- , /* QSPI_BK2_IO3 */ +- ; /* QSPI_BK2_NCS */ +- }; +- }; +- +- sai2a_pins_a: sai2a-0 { +- pins { +- pinmux = , /* SAI2_SCK_A */ +- , /* SAI2_SD_A */ +- , /* SAI2_FS_A */ +- ; /* SAI2_MCLK_A */ +- slew-rate = <0>; +- drive-push-pull; +- bias-disable; +- }; +- }; +- +- sai2a_sleep_pins_a: sai2a-sleep-0 { +- pins { +- pinmux = , /* SAI2_SCK_A */ +- , /* SAI2_SD_A */ +- , /* SAI2_FS_A */ +- ; /* SAI2_MCLK_A */ +- }; +- }; +- +- sai2a_pins_b: sai2a-1 { +- pins1 { +- pinmux = , /* SAI2_SD_A */ +- , /* SAI2_FS_A */ +- ; /* SAI2_SCK_A */ +- slew-rate = <0>; +- drive-push-pull; +- bias-disable; +- }; +- }; +- +- sai2a_sleep_pins_b: sai2a-sleep-1 { +- pins { +- pinmux = , /* SAI2_SD_A */ +- , /* SAI2_FS_A */ +- ; /* SAI2_SCK_A */ +- }; +- }; +- +- sai2a_pins_c: sai2a-2 { +- pins { +- pinmux = , /* SAI2_SCK_A */ +- , /* SAI2_SD_A */ +- ; /* SAI2_FS_A */ +- slew-rate = <0>; +- drive-push-pull; +- bias-disable; +- }; +- }; +- +- sai2a_sleep_pins_c: sai2a-2 { +- pins { +- pinmux = , /* SAI2_SCK_A */ +- , /* SAI2_SD_A */ +- ; /* SAI2_FS_A */ +- }; +- }; +- +- sai2b_pins_a: sai2b-0 { +- pins1 { +- pinmux = , /* SAI2_SCK_B */ +- , /* SAI2_FS_B */ +- ; /* SAI2_MCLK_B */ +- slew-rate = <0>; +- drive-push-pull; +- bias-disable; +- }; +- pins2 { +- pinmux = ; /* SAI2_SD_B */ +- bias-disable; +- }; +- }; +- +- sai2b_sleep_pins_a: sai2b-sleep-0 { +- pins { +- pinmux = , /* SAI2_SD_B */ +- , /* SAI2_SCK_B */ +- , /* SAI2_FS_B */ +- ; /* SAI2_MCLK_B */ +- }; +- }; +- +- sai2b_pins_b: sai2b-1 { +- pins { +- pinmux = ; /* SAI2_SD_B */ +- bias-disable; +- }; +- }; +- +- sai2b_sleep_pins_b: sai2b-sleep-1 { +- pins { +- pinmux = ; /* SAI2_SD_B */ +- }; +- }; +- +- sai2b_pins_c: sai2b-2 { +- pins1 { +- pinmux = ; /* SAI2_SD_B */ +- bias-disable; +- }; +- }; +- +- sai2b_sleep_pins_c: sai2b-sleep-2 { +- pins { +- pinmux = ; /* SAI2_SD_B */ +- }; +- }; +- +- sai4a_pins_a: sai4a-0 { +- pins { +- pinmux = ; /* SAI4_SD_A */ +- slew-rate = <0>; +- drive-push-pull; +- bias-disable; +- }; +- }; +- +- sai4a_sleep_pins_a: sai4a-sleep-0 { +- pins { +- pinmux = ; /* SAI4_SD_A */ +- }; +- }; +- +- sdmmc1_b4_pins_a: sdmmc1-b4-0 { +- pins1 { +- pinmux = , /* SDMMC1_D0 */ +- , /* SDMMC1_D1 */ +- , /* SDMMC1_D2 */ +- , /* SDMMC1_D3 */ +- ; /* SDMMC1_CMD */ +- slew-rate = <1>; +- drive-push-pull; +- bias-disable; +- }; +- pins2 { +- pinmux = ; /* SDMMC1_CK */ +- slew-rate = <2>; +- drive-push-pull; +- bias-disable; +- }; +- }; +- +- sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { +- pins1 { +- pinmux = , /* SDMMC1_D0 */ +- , /* SDMMC1_D1 */ +- , /* SDMMC1_D2 */ +- ; /* SDMMC1_D3 */ +- slew-rate = <1>; +- drive-push-pull; +- bias-disable; +- }; +- pins2 { +- pinmux = ; /* SDMMC1_CK */ +- slew-rate = <2>; +- drive-push-pull; +- bias-disable; +- }; +- pins3 { +- pinmux = ; /* SDMMC1_CMD */ +- slew-rate = <1>; +- drive-open-drain; +- bias-disable; +- }; +- }; +- +- sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 { +- pins1 { +- pinmux = , /* SDMMC1_D0 */ +- , /* SDMMC1_D1 */ +- , /* SDMMC1_D2 */ +- ; /* SDMMC1_D3 */ +- slew-rate = <1>; +- drive-push-pull; +- bias-disable; +- }; +- }; +- +- sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { +- pins { +- pinmux = , /* SDMMC1_D0 */ +- , /* SDMMC1_D1 */ +- , /* SDMMC1_D2 */ +- , /* SDMMC1_D3 */ +- , /* SDMMC1_CK */ +- ; /* SDMMC1_CMD */ +- }; +- }; +- +- sdmmc1_dir_pins_a: sdmmc1-dir-0 { +- pins1 { +- pinmux = , /* SDMMC1_D0DIR */ +- , /* SDMMC1_D123DIR */ +- ; /* SDMMC1_CDIR */ +- slew-rate = <1>; +- drive-push-pull; +- bias-pull-up; +- }; +- pins2{ +- pinmux = ; /* SDMMC1_CKIN */ +- bias-pull-up; +- }; +- }; +- +- sdmmc1_dir_init_pins_a: sdmmc1-dir-init-0 { +- pins1 { +- pinmux = , /* SDMMC1_D0DIR */ +- , /* SDMMC1_D123DIR */ +- ; /* SDMMC1_CDIR */ +- slew-rate = <1>; +- drive-push-pull; +- bias-pull-up; +- }; +- }; +- +- sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { +- pins { +- pinmux = , /* SDMMC1_D0DIR */ +- , /* SDMMC1_D123DIR */ +- , /* SDMMC1_CDIR */ +- ; /* SDMMC1_CKIN */ +- }; +- }; +- +- sdmmc1_dir_pins_b: sdmmc1-dir-1 { +- pins1 { +- pinmux = , /* SDMMC1_D0DIR */ +- , /* SDMMC1_D123DIR */ +- ; /* SDMMC1_CDIR */ +- slew-rate = <1>; +- drive-push-pull; +- bias-pull-up; +- }; +- pins2{ +- pinmux = ; /* SDMMC1_CKIN */ +- bias-pull-up; +- }; +- }; +- +- sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 { +- pins { +- pinmux = , /* SDMMC1_D0DIR */ +- , /* SDMMC1_D123DIR */ +- , /* SDMMC1_CDIR */ +- ; /* SDMMC1_CKIN */ +- }; +- }; +- +- sdmmc2_b4_pins_a: sdmmc2-b4-0 { +- pins1 { +- pinmux = , /* SDMMC2_D0 */ +- , /* SDMMC2_D1 */ +- , /* SDMMC2_D2 */ +- , /* SDMMC2_D3 */ +- ; /* SDMMC2_CMD */ +- slew-rate = <1>; +- drive-push-pull; +- bias-pull-up; +- }; +- pins2 { +- pinmux = ; /* SDMMC2_CK */ +- slew-rate = <2>; +- drive-push-pull; +- bias-pull-up; +- }; +- }; +- +- sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { +- pins1 { +- pinmux = , /* SDMMC2_D0 */ +- , /* SDMMC2_D1 */ +- , /* SDMMC2_D2 */ +- ; /* SDMMC2_D3 */ +- slew-rate = <1>; +- drive-push-pull; +- bias-pull-up; +- }; +- pins2 { +- pinmux = ; /* SDMMC2_CK */ +- slew-rate = <2>; +- drive-push-pull; +- bias-pull-up; +- }; +- pins3 { +- pinmux = ; /* SDMMC2_CMD */ +- slew-rate = <1>; +- drive-open-drain; +- bias-pull-up; +- }; +- }; +- +- sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { +- pins { +- pinmux = , /* SDMMC2_D0 */ +- , /* SDMMC2_D1 */ +- , /* SDMMC2_D2 */ +- , /* SDMMC2_D3 */ +- , /* SDMMC2_CK */ +- ; /* SDMMC2_CMD */ +- }; +- }; +- +- sdmmc2_b4_pins_b: sdmmc2-b4-1 { +- pins1 { +- pinmux = , /* SDMMC2_D0 */ +- , /* SDMMC2_D1 */ +- , /* SDMMC2_D2 */ +- , /* SDMMC2_D3 */ +- ; /* SDMMC2_CMD */ +- slew-rate = <1>; +- drive-push-pull; +- bias-disable; +- }; +- pins2 { +- pinmux = ; /* SDMMC2_CK */ +- slew-rate = <2>; +- drive-push-pull; +- bias-disable; +- }; +- }; +- +- sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 { +- pins1 { +- pinmux = , /* SDMMC2_D0 */ +- , /* SDMMC2_D1 */ +- , /* SDMMC2_D2 */ +- ; /* SDMMC2_D3 */ +- slew-rate = <1>; +- drive-push-pull; +- bias-disable; +- }; +- pins2 { +- pinmux = ; /* SDMMC2_CK */ +- slew-rate = <2>; +- drive-push-pull; +- bias-disable; +- }; +- pins3 { +- pinmux = ; /* SDMMC2_CMD */ +- slew-rate = <1>; +- drive-open-drain; +- bias-disable; +- }; +- }; +- +- sdmmc2_d47_pins_a: sdmmc2-d47-0 { +- pins { +- pinmux = , /* SDMMC2_D4 */ +- , /* SDMMC2_D5 */ +- , /* SDMMC2_D6 */ +- ; /* SDMMC2_D7 */ +- slew-rate = <1>; +- drive-push-pull; +- bias-pull-up; +- }; +- }; +- +- sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { +- pins { +- pinmux = , /* SDMMC2_D4 */ +- , /* SDMMC2_D5 */ +- , /* SDMMC2_D6 */ +- ; /* SDMMC2_D7 */ +- }; +- }; +- +- sdmmc2_d47_pins_b: sdmmc2-d47-1 { +- pins { +- pinmux = , /* SDMMC2_D4 */ +- , /* SDMMC2_D5 */ +- , /* SDMMC2_D6 */ +- ; /* SDMMC2_D7 */ +- slew-rate = <1>; +- drive-push-pull; +- bias-disable; +- }; +- }; +- +- sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { +- pins { +- pinmux = , /* SDMMC2_D4 */ +- , /* SDMMC2_D5 */ +- , /* SDMMC2_D6 */ +- ; /* SDMMC2_D7 */ +- }; +- }; +- +- sdmmc2_d47_pins_c: sdmmc2-d47-2 { +- pins { +- pinmux = , /* SDMMC2_D4 */ +- , /* SDMMC2_D5 */ +- , /* SDMMC2_D6 */ +- ; /* SDMMC2_D7 */ +- slew-rate = <1>; +- drive-push-pull; +- bias-pull-up; +- }; +- }; +- +- sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 { +- pins { +- pinmux = , /* SDMMC2_D4 */ +- , /* SDMMC2_D5 */ +- , /* SDMMC2_D6 */ +- ; /* SDMMC2_D7 */ +- }; +- }; +- +- sdmmc2_d47_pins_d: sdmmc2-d47-3 { +- pins { +- pinmux = , /* SDMMC2_D4 */ +- , /* SDMMC2_D5 */ +- , /* SDMMC2_D6 */ +- ; /* SDMMC2_D7 */ +- }; +- }; +- +- sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 { +- pins { +- pinmux = , /* SDMMC2_D4 */ +- , /* SDMMC2_D5 */ +- , /* SDMMC2_D6 */ +- ; /* SDMMC2_D7 */ +- }; +- }; +- +- sdmmc3_b4_pins_a: sdmmc3-b4-0 { +- pins1 { +- pinmux = , /* SDMMC3_D0 */ +- , /* SDMMC3_D1 */ +- , /* SDMMC3_D2 */ +- , /* SDMMC3_D3 */ +- ; /* SDMMC3_CMD */ +- slew-rate = <1>; +- drive-push-pull; +- bias-pull-up; +- }; +- pins2 { +- pinmux = ; /* SDMMC3_CK */ +- slew-rate = <2>; +- drive-push-pull; +- bias-pull-up; +- }; +- }; +- +- sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 { +- pins1 { +- pinmux = , /* SDMMC3_D0 */ +- , /* SDMMC3_D1 */ +- , /* SDMMC3_D2 */ +- ; /* SDMMC3_D3 */ +- slew-rate = <1>; +- drive-push-pull; +- bias-pull-up; +- }; +- pins2 { +- pinmux = ; /* SDMMC3_CK */ +- slew-rate = <2>; +- drive-push-pull; +- bias-pull-up; +- }; +- pins3 { +- pinmux = ; /* SDMMC2_CMD */ +- slew-rate = <1>; +- drive-open-drain; +- bias-pull-up; +- }; +- }; +- +- sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 { +- pins { +- pinmux = , /* SDMMC3_D0 */ +- , /* SDMMC3_D1 */ +- , /* SDMMC3_D2 */ +- , /* SDMMC3_D3 */ +- , /* SDMMC3_CK */ +- ; /* SDMMC3_CMD */ +- }; +- }; +- +- sdmmc3_b4_pins_b: sdmmc3-b4-1 { +- pins1 { +- pinmux = , /* SDMMC3_D0 */ +- , /* SDMMC3_D1 */ +- , /* SDMMC3_D2 */ +- , /* SDMMC3_D3 */ +- ; /* SDMMC3_CMD */ +- slew-rate = <1>; +- drive-push-pull; +- bias-pull-up; +- }; +- pins2 { +- pinmux = ; /* SDMMC3_CK */ +- slew-rate = <2>; +- drive-push-pull; +- bias-pull-up; +- }; +- }; +- +- sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 { +- pins1 { +- pinmux = , /* SDMMC3_D0 */ +- , /* SDMMC3_D1 */ +- , /* SDMMC3_D2 */ +- ; /* SDMMC3_D3 */ +- slew-rate = <1>; +- drive-push-pull; +- bias-pull-up; +- }; +- pins2 { +- pinmux = ; /* SDMMC3_CK */ +- slew-rate = <2>; +- drive-push-pull; +- bias-pull-up; +- }; +- pins3 { +- pinmux = ; /* SDMMC2_CMD */ +- slew-rate = <1>; +- drive-open-drain; +- bias-pull-up; +- }; +- }; +- +- sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 { +- pins { +- pinmux = , /* SDMMC3_D0 */ +- , /* SDMMC3_D1 */ +- , /* SDMMC3_D2 */ +- , /* SDMMC3_D3 */ +- , /* SDMMC3_CK */ +- ; /* SDMMC3_CMD */ +- }; +- }; +- +- spdifrx_pins_a: spdifrx-0 { +- pins { +- pinmux = ; /* SPDIF_IN1 */ +- bias-disable; +- }; +- }; +- +- spdifrx_sleep_pins_a: spdifrx-sleep-0 { +- pins { +- pinmux = ; /* SPDIF_IN1 */ +- }; +- }; +- +- spi2_pins_a: spi2-0 { +- pins1 { +- pinmux = , /* SPI1_SCK */ +- ; /* SPI1_MOSI */ +- bias-disable; +- drive-push-pull; +- slew-rate = <1>; +- }; +- +- pins2 { +- pinmux = ; /* SPI1_MISO */ +- bias-disable; +- }; +- }; +- +- spi4_pins_a: spi4-0 { +- pins { +- pinmux = , /* SPI4_SCK */ +- ; /* SPI4_MOSI */ +- bias-disable; +- drive-push-pull; +- slew-rate = <1>; +- }; +- pins2 { +- pinmux = ; /* SPI4_MISO */ +- bias-disable; +- }; +- }; +- +- stusb1600_pins_a: stusb1600-0 { +- pins { +- pinmux = ; +- bias-pull-up; +- }; +- }; +- +- uart4_pins_a: uart4-0 { +- pins1 { +- pinmux = ; /* UART4_TX */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = ; /* UART4_RX */ +- bias-disable; +- }; +- }; +- +- uart4_idle_pins_a: uart4-idle-0 { +- pins1 { +- pinmux = ; /* UART4_TX */ +- }; +- pins2 { +- pinmux = ; /* UART4_RX */ +- bias-disable; +- }; +- }; +- +- uart4_sleep_pins_a: uart4-sleep-0 { +- pins { +- pinmux = , /* UART4_TX */ +- ; /* UART4_RX */ +- }; +- }; +- +- uart4_pins_b: uart4-1 { +- pins1 { +- pinmux = ; /* UART4_TX */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = ; /* UART4_RX */ +- bias-disable; +- }; +- }; +- +- uart4_pins_c: uart4-2 { +- pins1 { +- pinmux = ; /* UART4_TX */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = ; /* UART4_RX */ +- bias-disable; +- }; +- }; +- +- uart7_pins_a: uart7-0 { +- pins1 { +- pinmux = ; /* UART7_TX */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = , /* UART7_RX */ +- , /* UART7_CTS */ +- ; /* UART7_RTS */ +- bias-disable; +- }; +- }; +- +- uart7_pins_b: uart7-1 { +- pins1 { +- pinmux = ; /* UART7_TX */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = ; /* UART7_RX */ +- bias-disable; +- }; +- }; +- +- uart7_pins_c: uart7-2 { +- pins1 { +- pinmux = ; /* UART7_TX */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = ; /* UART7_RX */ +- bias-disable; +- }; +- }; +- +- uart7_idle_pins_c: uart7-idle-2 { +- pins1 { +- pinmux = ; /* UART7_TX */ +- }; +- pins2 { +- pinmux = ; /* UART7_RX */ +- bias-disable; +- }; +- }; +- +- uart7_sleep_pins_c: uart7-sleep-2 { +- pins { +- pinmux = , /* UART7_TX */ +- ; /* UART7_RX */ +- }; +- }; +- +- uart8_pins_a: uart8-0 { +- pins1 { +- pinmux = ; /* UART8_TX */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = ; /* UART8_RX */ +- bias-disable; +- }; +- }; +- +- uart8_rtscts_pins_a: uart8rtscts-0 { +- pins { +- pinmux = , /* UART8_RTS */ +- ; /* UART8_CTS */ +- bias-disable; +- }; +- }; +- +- usart2_pins_a: usart2-0 { +- pins1 { +- pinmux = , /* USART2_TX */ +- ; /* USART2_RTS */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = , /* USART2_RX */ +- ; /* USART2_CTS_NSS */ +- bias-disable; +- }; +- }; +- +- usart2_sleep_pins_a: usart2-sleep-0 { +- pins { +- pinmux = , /* USART2_TX */ +- , /* USART2_RTS */ +- , /* USART2_RX */ +- ; /* USART2_CTS_NSS */ +- }; +- }; +- +- usart2_pins_b: usart2-1 { +- pins1 { +- pinmux = , /* USART2_TX */ +- ; /* USART2_RTS */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = , /* USART2_RX */ +- ; /* USART2_CTS_NSS */ +- bias-disable; +- }; +- }; +- +- usart2_sleep_pins_b: usart2-sleep-1 { +- pins { +- pinmux = , /* USART2_TX */ +- , /* USART2_RTS */ +- , /* USART2_RX */ +- ; /* USART2_CTS_NSS */ +- }; +- }; +- +- usart2_pins_c: usart2-2 { +- pins1 { +- pinmux = , /* USART2_TX */ +- ; /* USART2_RTS */ +- bias-disable; +- drive-push-pull; +- slew-rate = <3>; +- }; +- pins2 { +- pinmux = , /* USART2_RX */ +- ; /* USART2_CTS_NSS */ +- bias-disable; +- }; +- }; +- +- usart2_idle_pins_c: usart2-idle-2 { +- pins1 { +- pinmux = , /* USART2_TX */ +- ; /* USART2_CTS_NSS */ +- }; +- pins2 { +- pinmux = ; /* USART2_RTS */ +- bias-disable; +- drive-push-pull; +- slew-rate = <3>; +- }; +- pins3 { +- pinmux = ; /* USART2_RX */ +- bias-disable; +- }; +- }; +- +- usart2_sleep_pins_c: usart2-sleep-2 { +- pins { +- pinmux = , /* USART2_TX */ +- , /* USART2_RTS */ +- , /* USART2_RX */ +- ; /* USART2_CTS_NSS */ +- }; +- }; +- +- usart3_pins_a: usart3-0 { +- pins1 { +- pinmux = ; /* USART3_TX */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = ; /* USART3_RX */ +- bias-disable; +- }; +- }; +- +- usart3_pins_b: usart3-1 { +- pins1 { +- pinmux = , /* USART3_TX */ +- ; /* USART3_RTS */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = , /* USART3_RX */ +- ; /* USART3_CTS_NSS */ +- bias-disable; +- }; +- }; +- +- usart3_idle_pins_b: usart3-idle-1 { +- pins1 { +- pinmux = , /* USART3_TX */ +- ; /* USART3_CTS_NSS */ +- }; +- pins2 { +- pinmux = ; /* USART3_RTS */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins3 { +- pinmux = ; /* USART3_RX */ +- bias-disable; +- }; +- }; +- +- usart3_sleep_pins_b: usart3-sleep-1 { +- pins { +- pinmux = , /* USART3_TX */ +- , /* USART3_RTS */ +- , /* USART3_CTS_NSS */ +- ; /* USART3_RX */ +- }; +- }; +- +- usart3_pins_c: usart3-2 { +- pins1 { +- pinmux = , /* USART3_TX */ +- ; /* USART3_RTS */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins2 { +- pinmux = , /* USART3_RX */ +- ; /* USART3_CTS_NSS */ +- bias-disable; +- }; +- }; +- +- usart3_idle_pins_c: usart3-idle-2 { +- pins1 { +- pinmux = , /* USART3_TX */ +- ; /* USART3_CTS_NSS */ +- }; +- pins2 { +- pinmux = ; /* USART3_RTS */ +- bias-disable; +- drive-push-pull; +- slew-rate = <0>; +- }; +- pins3 { +- pinmux = ; /* USART3_RX */ +- bias-disable; +- }; +- }; +- +- usart3_sleep_pins_c: usart3-sleep-2 { +- pins { +- pinmux = , /* USART3_TX */ +- , /* USART3_RTS */ +- , /* USART3_CTS_NSS */ +- ; /* USART3_RX */ +- }; +- }; +- +- usbotg_hs_pins_a: usbotg-hs-0 { +- pins { +- pinmux = ; /* OTG_ID */ +- }; +- }; +- +- usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 { +- pins { +- pinmux = , /* OTG_FS_DM */ +- ; /* OTG_FS_DP */ +- }; +- }; +-}; +- +-&pinctrl_z { +- i2c2_pins_b2: i2c2-0 { +- pins { +- pinmux = ; /* I2C2_SCL */ +- bias-disable; +- drive-open-drain; +- slew-rate = <0>; +- }; +- }; +- +- i2c2_sleep_pins_b2: i2c2-sleep-0 { +- pins { +- pinmux = ; /* I2C2_SCL */ +- }; +- }; +- +- i2c4_pins_a: i2c4-0 { +- pins { +- pinmux = , /* I2C4_SCL */ +- ; /* I2C4_SDA */ +- bias-disable; +- drive-open-drain; +- slew-rate = <0>; +- }; +- }; +- +- i2c4_sleep_pins_a: i2c4-sleep-0 { +- pins { +- pinmux = , /* I2C4_SCL */ +- ; /* I2C4_SDA */ +- }; +- }; +- +- i2c6_pins_a: i2c6-0 { +- pins { +- pinmux = , /* I2C6_SCL */ +- ; /* I2C6_SDA */ +- bias-disable; +- drive-open-drain; +- slew-rate = <0>; +- }; +- }; +- +- i2c6_sleep_pins_a: i2c6-sleep-0 { +- pins { +- pinmux = , /* I2C6_SCL */ +- ; /* I2C6_SDA */ +- }; +- }; +- +- spi1_pins_a: spi1-0 { +- pins1 { +- pinmux = , /* SPI1_SCK */ +- ; /* SPI1_MOSI */ +- bias-disable; +- drive-push-pull; +- slew-rate = <1>; +- }; +- +- pins2 { +- pinmux = ; /* SPI1_MISO */ +- bias-disable; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp151.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp151.dtsi +deleted file mode 100644 +index 6992a4b0ba79..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp151.dtsi ++++ /dev/null +@@ -1,1781 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved +- * Author: Ludovic Barre for STMicroelectronics. +- */ +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a7"; +- clock-frequency = <650000000>; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupts = ; +- interrupt-affinity = <&cpu0>; +- interrupt-parent = <&intc>; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- intc: interrupt-controller@a0021000 { +- compatible = "arm,cortex-a7-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0xa0021000 0x1000>, +- <0xa0022000 0x2000>; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- interrupt-parent = <&intc>; +- }; +- +- clocks { +- clk_hse: clk-hse { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- clk_hsi: clk-hsi { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <64000000>; +- }; +- +- clk_lse: clk-lse { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- clk_lsi: clk-lsi { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32000>; +- }; +- +- clk_csi: clk-csi { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <4000000>; +- }; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&dts>; +- +- trips { +- cpu_alert1: cpu-alert1 { +- temperature = <85000>; +- hysteresis = <0>; +- type = "passive"; +- }; +- +- cpu-crit { +- temperature = <120000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- }; +- }; +- }; +- +- booster: regulator-booster { +- compatible = "st,stm32mp1-booster"; +- st,syscfg = <&syscfg>; +- status = "disabled"; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&intc>; +- ranges; +- +- timers2: timer@40000000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40000000 0x400>; +- clocks = <&rcc TIM2_K>; +- clock-names = "int"; +- dmas = <&dmamux1 18 0x400 0x1>, +- <&dmamux1 19 0x400 0x1>, +- <&dmamux1 20 0x400 0x1>, +- <&dmamux1 21 0x400 0x1>, +- <&dmamux1 22 0x400 0x1>; +- dma-names = "ch1", "ch2", "ch3", "ch4", "up"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@1 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <1>; +- status = "disabled"; +- }; +- +- counter { +- compatible = "st,stm32-timer-counter"; +- status = "disabled"; +- }; +- }; +- +- timers3: timer@40001000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40001000 0x400>; +- clocks = <&rcc TIM3_K>; +- clock-names = "int"; +- dmas = <&dmamux1 23 0x400 0x1>, +- <&dmamux1 24 0x400 0x1>, +- <&dmamux1 25 0x400 0x1>, +- <&dmamux1 26 0x400 0x1>, +- <&dmamux1 27 0x400 0x1>, +- <&dmamux1 28 0x400 0x1>; +- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@2 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <2>; +- status = "disabled"; +- }; +- +- counter { +- compatible = "st,stm32-timer-counter"; +- status = "disabled"; +- }; +- }; +- +- timers4: timer@40002000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40002000 0x400>; +- clocks = <&rcc TIM4_K>; +- clock-names = "int"; +- dmas = <&dmamux1 29 0x400 0x1>, +- <&dmamux1 30 0x400 0x1>, +- <&dmamux1 31 0x400 0x1>, +- <&dmamux1 32 0x400 0x1>; +- dma-names = "ch1", "ch2", "ch3", "ch4"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@3 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <3>; +- status = "disabled"; +- }; +- +- counter { +- compatible = "st,stm32-timer-counter"; +- status = "disabled"; +- }; +- }; +- +- timers5: timer@40003000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40003000 0x400>; +- clocks = <&rcc TIM5_K>; +- clock-names = "int"; +- dmas = <&dmamux1 55 0x400 0x1>, +- <&dmamux1 56 0x400 0x1>, +- <&dmamux1 57 0x400 0x1>, +- <&dmamux1 58 0x400 0x1>, +- <&dmamux1 59 0x400 0x1>, +- <&dmamux1 60 0x400 0x1>; +- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@4 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <4>; +- status = "disabled"; +- }; +- +- counter { +- compatible = "st,stm32-timer-counter"; +- status = "disabled"; +- }; +- }; +- +- timers6: timer@40004000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40004000 0x400>; +- clocks = <&rcc TIM6_K>; +- clock-names = "int"; +- dmas = <&dmamux1 69 0x400 0x1>; +- dma-names = "up"; +- status = "disabled"; +- +- timer@5 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <5>; +- status = "disabled"; +- }; +- }; +- +- timers7: timer@40005000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40005000 0x400>; +- clocks = <&rcc TIM7_K>; +- clock-names = "int"; +- dmas = <&dmamux1 70 0x400 0x1>; +- dma-names = "up"; +- status = "disabled"; +- +- timer@6 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <6>; +- status = "disabled"; +- }; +- }; +- +- timers12: timer@40006000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40006000 0x400>; +- clocks = <&rcc TIM12_K>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@11 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <11>; +- status = "disabled"; +- }; +- }; +- +- timers13: timer@40007000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40007000 0x400>; +- clocks = <&rcc TIM13_K>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@12 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <12>; +- status = "disabled"; +- }; +- }; +- +- timers14: timer@40008000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40008000 0x400>; +- clocks = <&rcc TIM14_K>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@13 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <13>; +- status = "disabled"; +- }; +- }; +- +- lptimer1: timer@40009000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-lptimer"; +- reg = <0x40009000 0x400>; +- interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc LPTIM1_K>; +- clock-names = "mux"; +- wakeup-source; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- trigger@0 { +- compatible = "st,stm32-lptimer-trigger"; +- reg = <0>; +- status = "disabled"; +- }; +- +- counter { +- compatible = "st,stm32-lptimer-counter"; +- status = "disabled"; +- }; +- }; +- +- spi2: spi@4000b000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x4000b000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI2_K>; +- resets = <&rcc SPI2_R>; +- dmas = <&dmamux1 39 0x400 0x05>, +- <&dmamux1 40 0x400 0x05>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2s2: audio-controller@4000b000 { +- compatible = "st,stm32h7-i2s"; +- #sound-dai-cells = <0>; +- reg = <0x4000b000 0x400>; +- interrupts = ; +- dmas = <&dmamux1 39 0x400 0x01>, +- <&dmamux1 40 0x400 0x01>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi3: spi@4000c000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x4000c000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI3_K>; +- resets = <&rcc SPI3_R>; +- dmas = <&dmamux1 61 0x400 0x05>, +- <&dmamux1 62 0x400 0x05>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2s3: audio-controller@4000c000 { +- compatible = "st,stm32h7-i2s"; +- #sound-dai-cells = <0>; +- reg = <0x4000c000 0x400>; +- interrupts = ; +- dmas = <&dmamux1 61 0x400 0x01>, +- <&dmamux1 62 0x400 0x01>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spdifrx: audio-controller@4000d000 { +- compatible = "st,stm32h7-spdifrx"; +- #sound-dai-cells = <0>; +- reg = <0x4000d000 0x400>; +- clocks = <&rcc SPDIF_K>; +- clock-names = "kclk"; +- interrupts = ; +- dmas = <&dmamux1 93 0x400 0x01>, +- <&dmamux1 94 0x400 0x01>; +- dma-names = "rx", "rx-ctrl"; +- status = "disabled"; +- }; +- +- usart2: serial@4000e000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x4000e000 0x400>; +- interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc USART2_K>; +- wakeup-source; +- status = "disabled"; +- }; +- +- usart3: serial@4000f000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x4000f000 0x400>; +- interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc USART3_K>; +- wakeup-source; +- status = "disabled"; +- }; +- +- uart4: serial@40010000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x40010000 0x400>; +- interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc UART4_K>; +- wakeup-source; +- status = "disabled"; +- }; +- +- uart5: serial@40011000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x40011000 0x400>; +- interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc UART5_K>; +- wakeup-source; +- status = "disabled"; +- }; +- +- i2c1: i2c@40012000 { +- compatible = "st,stm32mp15-i2c"; +- reg = <0x40012000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C1_K>; +- resets = <&rcc I2C1_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- st,syscfg-fmp = <&syscfg 0x4 0x1>; +- wakeup-source; +- i2c-analog-filter; +- status = "disabled"; +- }; +- +- i2c2: i2c@40013000 { +- compatible = "st,stm32mp15-i2c"; +- reg = <0x40013000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C2_K>; +- resets = <&rcc I2C2_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- st,syscfg-fmp = <&syscfg 0x4 0x2>; +- wakeup-source; +- i2c-analog-filter; +- status = "disabled"; +- }; +- +- i2c3: i2c@40014000 { +- compatible = "st,stm32mp15-i2c"; +- reg = <0x40014000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C3_K>; +- resets = <&rcc I2C3_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- st,syscfg-fmp = <&syscfg 0x4 0x4>; +- wakeup-source; +- i2c-analog-filter; +- status = "disabled"; +- }; +- +- i2c5: i2c@40015000 { +- compatible = "st,stm32mp15-i2c"; +- reg = <0x40015000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C5_K>; +- resets = <&rcc I2C5_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- st,syscfg-fmp = <&syscfg 0x4 0x10>; +- wakeup-source; +- i2c-analog-filter; +- status = "disabled"; +- }; +- +- cec: cec@40016000 { +- compatible = "st,stm32-cec"; +- reg = <0x40016000 0x400>; +- interrupts = ; +- clocks = <&rcc CEC_K>, <&clk_lse>; +- clock-names = "cec", "hdmi-cec"; +- status = "disabled"; +- }; +- +- dac: dac@40017000 { +- compatible = "st,stm32h7-dac-core"; +- reg = <0x40017000 0x400>; +- clocks = <&rcc DAC12>; +- clock-names = "pclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- dac1: dac@1 { +- compatible = "st,stm32-dac"; +- #io-channel-cells = <1>; +- reg = <1>; +- status = "disabled"; +- }; +- +- dac2: dac@2 { +- compatible = "st,stm32-dac"; +- #io-channel-cells = <1>; +- reg = <2>; +- status = "disabled"; +- }; +- }; +- +- uart7: serial@40018000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x40018000 0x400>; +- interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc UART7_K>; +- wakeup-source; +- status = "disabled"; +- }; +- +- uart8: serial@40019000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x40019000 0x400>; +- interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc UART8_K>; +- wakeup-source; +- status = "disabled"; +- }; +- +- timers1: timer@44000000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x44000000 0x400>; +- clocks = <&rcc TIM1_K>; +- clock-names = "int"; +- dmas = <&dmamux1 11 0x400 0x1>, +- <&dmamux1 12 0x400 0x1>, +- <&dmamux1 13 0x400 0x1>, +- <&dmamux1 14 0x400 0x1>, +- <&dmamux1 15 0x400 0x1>, +- <&dmamux1 16 0x400 0x1>, +- <&dmamux1 17 0x400 0x1>; +- dma-names = "ch1", "ch2", "ch3", "ch4", +- "up", "trig", "com"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@0 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <0>; +- status = "disabled"; +- }; +- +- counter { +- compatible = "st,stm32-timer-counter"; +- status = "disabled"; +- }; +- }; +- +- timers8: timer@44001000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x44001000 0x400>; +- clocks = <&rcc TIM8_K>; +- clock-names = "int"; +- dmas = <&dmamux1 47 0x400 0x1>, +- <&dmamux1 48 0x400 0x1>, +- <&dmamux1 49 0x400 0x1>, +- <&dmamux1 50 0x400 0x1>, +- <&dmamux1 51 0x400 0x1>, +- <&dmamux1 52 0x400 0x1>, +- <&dmamux1 53 0x400 0x1>; +- dma-names = "ch1", "ch2", "ch3", "ch4", +- "up", "trig", "com"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@7 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <7>; +- status = "disabled"; +- }; +- +- counter { +- compatible = "st,stm32-timer-counter"; +- status = "disabled"; +- }; +- }; +- +- usart6: serial@44003000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x44003000 0x400>; +- interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc USART6_K>; +- wakeup-source; +- status = "disabled"; +- }; +- +- spi1: spi@44004000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x44004000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI1_K>; +- resets = <&rcc SPI1_R>; +- dmas = <&dmamux1 37 0x400 0x05>, +- <&dmamux1 38 0x400 0x05>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2s1: audio-controller@44004000 { +- compatible = "st,stm32h7-i2s"; +- #sound-dai-cells = <0>; +- reg = <0x44004000 0x400>; +- interrupts = ; +- dmas = <&dmamux1 37 0x400 0x01>, +- <&dmamux1 38 0x400 0x01>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi4: spi@44005000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x44005000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI4_K>; +- resets = <&rcc SPI4_R>; +- dmas = <&dmamux1 83 0x400 0x05>, +- <&dmamux1 84 0x400 0x05>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- timers15: timer@44006000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x44006000 0x400>; +- clocks = <&rcc TIM15_K>; +- clock-names = "int"; +- dmas = <&dmamux1 105 0x400 0x1>, +- <&dmamux1 106 0x400 0x1>, +- <&dmamux1 107 0x400 0x1>, +- <&dmamux1 108 0x400 0x1>; +- dma-names = "ch1", "up", "trig", "com"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@14 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <14>; +- status = "disabled"; +- }; +- }; +- +- timers16: timer@44007000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x44007000 0x400>; +- clocks = <&rcc TIM16_K>; +- clock-names = "int"; +- dmas = <&dmamux1 109 0x400 0x1>, +- <&dmamux1 110 0x400 0x1>; +- dma-names = "ch1", "up"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- timer@15 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <15>; +- status = "disabled"; +- }; +- }; +- +- timers17: timer@44008000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x44008000 0x400>; +- clocks = <&rcc TIM17_K>; +- clock-names = "int"; +- dmas = <&dmamux1 111 0x400 0x1>, +- <&dmamux1 112 0x400 0x1>; +- dma-names = "ch1", "up"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@16 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <16>; +- status = "disabled"; +- }; +- }; +- +- spi5: spi@44009000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x44009000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI5_K>; +- resets = <&rcc SPI5_R>; +- dmas = <&dmamux1 85 0x400 0x05>, +- <&dmamux1 86 0x400 0x05>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sai1: sai@4400a000 { +- compatible = "st,stm32h7-sai"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x4400a000 0x400>; +- reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; +- interrupts = ; +- resets = <&rcc SAI1_R>; +- status = "disabled"; +- +- sai1a: audio-controller@4400a004 { +- #sound-dai-cells = <0>; +- +- compatible = "st,stm32-sai-sub-a"; +- reg = <0x4 0x20>; +- clocks = <&rcc SAI1_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 87 0x400 0x01>; +- status = "disabled"; +- }; +- +- sai1b: audio-controller@4400a024 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-b"; +- reg = <0x24 0x20>; +- clocks = <&rcc SAI1_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 88 0x400 0x01>; +- status = "disabled"; +- }; +- }; +- +- sai2: sai@4400b000 { +- compatible = "st,stm32h7-sai"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x4400b000 0x400>; +- reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; +- interrupts = ; +- resets = <&rcc SAI2_R>; +- status = "disabled"; +- +- sai2a: audio-controller@4400b004 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-a"; +- reg = <0x4 0x20>; +- clocks = <&rcc SAI2_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 89 0x400 0x01>; +- status = "disabled"; +- }; +- +- sai2b: audio-controller@4400b024 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-b"; +- reg = <0x24 0x20>; +- clocks = <&rcc SAI2_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 90 0x400 0x01>; +- status = "disabled"; +- }; +- }; +- +- sai3: sai@4400c000 { +- compatible = "st,stm32h7-sai"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x4400c000 0x400>; +- reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; +- interrupts = ; +- resets = <&rcc SAI3_R>; +- status = "disabled"; +- +- sai3a: audio-controller@4400c004 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-a"; +- reg = <0x04 0x20>; +- clocks = <&rcc SAI3_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 113 0x400 0x01>; +- status = "disabled"; +- }; +- +- sai3b: audio-controller@4400c024 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-b"; +- reg = <0x24 0x20>; +- clocks = <&rcc SAI3_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 114 0x400 0x01>; +- status = "disabled"; +- }; +- }; +- +- dfsdm: dfsdm@4400d000 { +- compatible = "st,stm32mp1-dfsdm"; +- reg = <0x4400d000 0x800>; +- clocks = <&rcc DFSDM_K>; +- clock-names = "dfsdm"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- dfsdm0: filter@0 { +- compatible = "st,stm32-dfsdm-adc"; +- #io-channel-cells = <1>; +- reg = <0>; +- interrupts = ; +- dmas = <&dmamux1 101 0x400 0x01>; +- dma-names = "rx"; +- status = "disabled"; +- }; +- +- dfsdm1: filter@1 { +- compatible = "st,stm32-dfsdm-adc"; +- #io-channel-cells = <1>; +- reg = <1>; +- interrupts = ; +- dmas = <&dmamux1 102 0x400 0x01>; +- dma-names = "rx"; +- status = "disabled"; +- }; +- +- dfsdm2: filter@2 { +- compatible = "st,stm32-dfsdm-adc"; +- #io-channel-cells = <1>; +- reg = <2>; +- interrupts = ; +- dmas = <&dmamux1 103 0x400 0x01>; +- dma-names = "rx"; +- status = "disabled"; +- }; +- +- dfsdm3: filter@3 { +- compatible = "st,stm32-dfsdm-adc"; +- #io-channel-cells = <1>; +- reg = <3>; +- interrupts = ; +- dmas = <&dmamux1 104 0x400 0x01>; +- dma-names = "rx"; +- status = "disabled"; +- }; +- +- dfsdm4: filter@4 { +- compatible = "st,stm32-dfsdm-adc"; +- #io-channel-cells = <1>; +- reg = <4>; +- interrupts = ; +- dmas = <&dmamux1 91 0x400 0x01>; +- dma-names = "rx"; +- status = "disabled"; +- }; +- +- dfsdm5: filter@5 { +- compatible = "st,stm32-dfsdm-adc"; +- #io-channel-cells = <1>; +- reg = <5>; +- interrupts = ; +- dmas = <&dmamux1 92 0x400 0x01>; +- dma-names = "rx"; +- status = "disabled"; +- }; +- }; +- +- dma1: dma-controller@48000000 { +- compatible = "st,stm32-dma"; +- reg = <0x48000000 0x400>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&rcc DMA1>; +- resets = <&rcc DMA1_R>; +- #dma-cells = <4>; +- st,mem2mem; +- dma-requests = <8>; +- }; +- +- dma2: dma-controller@48001000 { +- compatible = "st,stm32-dma"; +- reg = <0x48001000 0x400>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&rcc DMA2>; +- resets = <&rcc DMA2_R>; +- #dma-cells = <4>; +- st,mem2mem; +- dma-requests = <8>; +- }; +- +- dmamux1: dma-router@48002000 { +- compatible = "st,stm32h7-dmamux"; +- reg = <0x48002000 0x40>; +- #dma-cells = <3>; +- dma-requests = <128>; +- dma-masters = <&dma1 &dma2>; +- dma-channels = <16>; +- clocks = <&rcc DMAMUX>; +- resets = <&rcc DMAMUX_R>; +- }; +- +- adc: adc@48003000 { +- compatible = "st,stm32mp1-adc-core"; +- reg = <0x48003000 0x400>; +- interrupts = , +- ; +- clocks = <&rcc ADC12>, <&rcc ADC12_K>; +- clock-names = "bus", "adc"; +- interrupt-controller; +- st,syscfg = <&syscfg>; +- #interrupt-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- adc1: adc@0 { +- compatible = "st,stm32mp1-adc"; +- #io-channel-cells = <1>; +- reg = <0x0>; +- interrupt-parent = <&adc>; +- interrupts = <0>; +- dmas = <&dmamux1 9 0x400 0x01>; +- dma-names = "rx"; +- status = "disabled"; +- }; +- +- adc2: adc@100 { +- compatible = "st,stm32mp1-adc"; +- #io-channel-cells = <1>; +- reg = <0x100>; +- interrupt-parent = <&adc>; +- interrupts = <1>; +- dmas = <&dmamux1 10 0x400 0x01>; +- dma-names = "rx"; +- status = "disabled"; +- }; +- }; +- +- sdmmc3: mmc@48004000 { +- compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00253180>; +- reg = <0x48004000 0x400>; +- interrupts = ; +- interrupt-names = "cmd_irq"; +- clocks = <&rcc SDMMC3_K>; +- clock-names = "apb_pclk"; +- resets = <&rcc SDMMC3_R>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <120000000>; +- status = "disabled"; +- }; +- +- usbotg_hs: usb-otg@49000000 { +- compatible = "st,stm32mp15-hsotg", "snps,dwc2"; +- reg = <0x49000000 0x10000>; +- clocks = <&rcc USBO_K>; +- clock-names = "otg"; +- resets = <&rcc USBO_R>; +- reset-names = "dwc2"; +- interrupts = ; +- g-rx-fifo-size = <512>; +- g-np-tx-fifo-size = <32>; +- g-tx-fifo-size = <256 16 16 16 16 16 16 16>; +- dr_mode = "otg"; +- usb33d-supply = <&usb33>; +- status = "disabled"; +- }; +- +- ipcc: mailbox@4c001000 { +- compatible = "st,stm32mp1-ipcc"; +- #mbox-cells = <1>; +- reg = <0x4c001000 0x400>; +- st,proc-id = <0>; +- interrupts-extended = +- <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, +- <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, +- <&exti 61 1>; +- interrupt-names = "rx", "tx", "wakeup"; +- clocks = <&rcc IPCC>; +- wakeup-source; +- status = "disabled"; +- }; +- +- dcmi: dcmi@4c006000 { +- compatible = "st,stm32-dcmi"; +- reg = <0x4c006000 0x400>; +- interrupts = ; +- resets = <&rcc CAMITF_R>; +- clocks = <&rcc DCMI>; +- clock-names = "mclk"; +- dmas = <&dmamux1 75 0x400 0x01>; +- dma-names = "tx"; +- status = "disabled"; +- }; +- +- rcc: rcc@50000000 { +- compatible = "st,stm32mp1-rcc", "syscon"; +- reg = <0x50000000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pwr_regulators: pwr@50001000 { +- compatible = "st,stm32mp1,pwr-reg"; +- reg = <0x50001000 0x10>; +- +- reg11: reg11 { +- regulator-name = "reg11"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- reg18: reg18 { +- regulator-name = "reg18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- usb33: usb33 { +- regulator-name = "usb33"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +- +- pwr_mcu: pwr_mcu@50001014 { +- compatible = "st,stm32mp151-pwr-mcu", "syscon"; +- reg = <0x50001014 0x4>; +- }; +- +- exti: interrupt-controller@5000d000 { +- compatible = "st,stm32mp1-exti", "syscon"; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x5000d000 0x400>; +- }; +- +- syscfg: syscon@50020000 { +- compatible = "st,stm32mp157-syscfg", "syscon"; +- reg = <0x50020000 0x400>; +- clocks = <&rcc SYSCFG>; +- }; +- +- lptimer2: timer@50021000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-lptimer"; +- reg = <0x50021000 0x400>; +- interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc LPTIM2_K>; +- clock-names = "mux"; +- wakeup-source; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- trigger@1 { +- compatible = "st,stm32-lptimer-trigger"; +- reg = <1>; +- status = "disabled"; +- }; +- +- counter { +- compatible = "st,stm32-lptimer-counter"; +- status = "disabled"; +- }; +- }; +- +- lptimer3: timer@50022000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-lptimer"; +- reg = <0x50022000 0x400>; +- interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc LPTIM3_K>; +- clock-names = "mux"; +- wakeup-source; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- trigger@2 { +- compatible = "st,stm32-lptimer-trigger"; +- reg = <2>; +- status = "disabled"; +- }; +- }; +- +- lptimer4: timer@50023000 { +- compatible = "st,stm32-lptimer"; +- reg = <0x50023000 0x400>; +- interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc LPTIM4_K>; +- clock-names = "mux"; +- wakeup-source; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- }; +- +- lptimer5: timer@50024000 { +- compatible = "st,stm32-lptimer"; +- reg = <0x50024000 0x400>; +- interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc LPTIM5_K>; +- clock-names = "mux"; +- wakeup-source; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- }; +- +- vrefbuf: vrefbuf@50025000 { +- compatible = "st,stm32-vrefbuf"; +- reg = <0x50025000 0x8>; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <2500000>; +- clocks = <&rcc VREF>; +- status = "disabled"; +- }; +- +- sai4: sai@50027000 { +- compatible = "st,stm32h7-sai"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x50027000 0x400>; +- reg = <0x50027000 0x4>, <0x500273f0 0x10>; +- interrupts = ; +- resets = <&rcc SAI4_R>; +- status = "disabled"; +- +- sai4a: audio-controller@50027004 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-a"; +- reg = <0x04 0x20>; +- clocks = <&rcc SAI4_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 99 0x400 0x01>; +- status = "disabled"; +- }; +- +- sai4b: audio-controller@50027024 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-b"; +- reg = <0x24 0x20>; +- clocks = <&rcc SAI4_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 100 0x400 0x01>; +- status = "disabled"; +- }; +- }; +- +- dts: thermal@50028000 { +- compatible = "st,stm32-thermal"; +- reg = <0x50028000 0x100>; +- interrupts = ; +- clocks = <&rcc TMPSENS>; +- clock-names = "pclk"; +- #thermal-sensor-cells = <0>; +- status = "disabled"; +- }; +- +- hash1: hash@54002000 { +- compatible = "st,stm32f756-hash"; +- reg = <0x54002000 0x400>; +- interrupts = ; +- clocks = <&rcc HASH1>; +- resets = <&rcc HASH1_R>; +- dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; +- dma-names = "in"; +- dma-maxburst = <2>; +- status = "disabled"; +- }; +- +- rng1: rng@54003000 { +- compatible = "st,stm32-rng"; +- reg = <0x54003000 0x400>; +- clocks = <&rcc RNG1_K>; +- resets = <&rcc RNG1_R>; +- status = "disabled"; +- }; +- +- mdma1: dma-controller@58000000 { +- compatible = "st,stm32h7-mdma"; +- reg = <0x58000000 0x1000>; +- interrupts = ; +- clocks = <&rcc MDMA>; +- resets = <&rcc MDMA_R>; +- #dma-cells = <5>; +- dma-channels = <32>; +- dma-requests = <48>; +- }; +- +- fmc: memory-controller@58002000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "st,stm32mp1-fmc2-ebi"; +- reg = <0x58002000 0x1000>; +- clocks = <&rcc FMC_K>; +- resets = <&rcc FMC_R>; +- status = "disabled"; +- +- ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ +- <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ +- <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ +- <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ +- <4 0 0x80000000 0x10000000>; /* NAND */ +- +- nand-controller@4,0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32mp1-fmc2-nfc"; +- reg = <4 0x00000000 0x1000>, +- <4 0x08010000 0x1000>, +- <4 0x08020000 0x1000>, +- <4 0x01000000 0x1000>, +- <4 0x09010000 0x1000>, +- <4 0x09020000 0x1000>; +- interrupts = ; +- dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, +- <&mdma1 20 0x2 0x12000a08 0x0 0x0>, +- <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; +- dma-names = "tx", "rx", "ecc"; +- status = "disabled"; +- }; +- }; +- +- qspi: spi@58003000 { +- compatible = "st,stm32f469-qspi"; +- reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; +- reg-names = "qspi", "qspi_mm"; +- interrupts = ; +- dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, +- <&mdma1 22 0x2 0x10100008 0x0 0x0>; +- dma-names = "tx", "rx"; +- clocks = <&rcc QSPI_K>; +- resets = <&rcc QSPI_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- sdmmc1: mmc@58005000 { +- compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00253180>; +- reg = <0x58005000 0x1000>; +- interrupts = ; +- interrupt-names = "cmd_irq"; +- clocks = <&rcc SDMMC1_K>; +- clock-names = "apb_pclk"; +- resets = <&rcc SDMMC1_R>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <120000000>; +- status = "disabled"; +- }; +- +- sdmmc2: mmc@58007000 { +- compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00253180>; +- reg = <0x58007000 0x1000>; +- interrupts = ; +- interrupt-names = "cmd_irq"; +- clocks = <&rcc SDMMC2_K>; +- clock-names = "apb_pclk"; +- resets = <&rcc SDMMC2_R>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <120000000>; +- status = "disabled"; +- }; +- +- crc1: crc@58009000 { +- compatible = "st,stm32f7-crc"; +- reg = <0x58009000 0x400>; +- clocks = <&rcc CRC1>; +- status = "disabled"; +- }; +- +- ethernet0: ethernet@5800a000 { +- compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; +- reg = <0x5800a000 0x2000>; +- reg-names = "stmmaceth"; +- interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "macirq"; +- clock-names = "stmmaceth", +- "mac-clk-tx", +- "mac-clk-rx", +- "eth-ck", +- "ptp_ref", +- "ethstp"; +- clocks = <&rcc ETHMAC>, +- <&rcc ETHTX>, +- <&rcc ETHRX>, +- <&rcc ETHCK_K>, +- <&rcc ETHPTP_K>, +- <&rcc ETHSTP>; +- st,syscon = <&syscfg 0x4>; +- snps,mixed-burst; +- snps,pbl = <2>; +- snps,en-tx-lpi-clockgating; +- snps,axi-config = <&stmmac_axi_config_0>; +- snps,tso; +- status = "disabled"; +- +- stmmac_axi_config_0: stmmac-axi-config { +- snps,wr_osr_lmt = <0x7>; +- snps,rd_osr_lmt = <0x7>; +- snps,blen = <0 0 0 0 16 8 4>; +- }; +- }; +- +- usbh_ohci: usb@5800c000 { +- compatible = "generic-ohci"; +- reg = <0x5800c000 0x1000>; +- clocks = <&rcc USBH>; +- resets = <&rcc USBH_R>; +- interrupts = ; +- status = "disabled"; +- }; +- +- usbh_ehci: usb@5800d000 { +- compatible = "generic-ehci"; +- reg = <0x5800d000 0x1000>; +- clocks = <&rcc USBH>; +- resets = <&rcc USBH_R>; +- interrupts = ; +- companion = <&usbh_ohci>; +- status = "disabled"; +- }; +- +- ltdc: display-controller@5a001000 { +- compatible = "st,stm32-ltdc"; +- reg = <0x5a001000 0x400>; +- interrupts = , +- ; +- clocks = <&rcc LTDC_PX>; +- clock-names = "lcd"; +- resets = <&rcc LTDC_R>; +- status = "disabled"; +- +- port { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- iwdg2: watchdog@5a002000 { +- compatible = "st,stm32mp1-iwdg"; +- reg = <0x5a002000 0x400>; +- clocks = <&rcc IWDG2>, <&rcc CK_LSI>; +- clock-names = "pclk", "lsi"; +- status = "disabled"; +- }; +- +- usbphyc: usbphyc@5a006000 { +- #address-cells = <1>; +- #size-cells = <0>; +- #clock-cells = <0>; +- compatible = "st,stm32mp1-usbphyc"; +- reg = <0x5a006000 0x1000>; +- clocks = <&rcc USBPHY_K>; +- resets = <&rcc USBPHY_R>; +- vdda1v1-supply = <®11>; +- vdda1v8-supply = <®18>; +- status = "disabled"; +- +- usbphyc_port0: usb-phy@0 { +- #phy-cells = <0>; +- reg = <0>; +- }; +- +- usbphyc_port1: usb-phy@1 { +- #phy-cells = <1>; +- reg = <1>; +- }; +- }; +- +- usart1: serial@5c000000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x5c000000 0x400>; +- interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc USART1_K>; +- wakeup-source; +- status = "disabled"; +- }; +- +- spi6: spi@5c001000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x5c001000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI6_K>; +- resets = <&rcc SPI6_R>; +- dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, +- <&mdma1 35 0x0 0x40002 0x0 0x0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c4: i2c@5c002000 { +- compatible = "st,stm32mp15-i2c"; +- reg = <0x5c002000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C4_K>; +- resets = <&rcc I2C4_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- st,syscfg-fmp = <&syscfg 0x4 0x8>; +- wakeup-source; +- i2c-analog-filter; +- status = "disabled"; +- }; +- +- rtc: rtc@5c004000 { +- compatible = "st,stm32mp1-rtc"; +- reg = <0x5c004000 0x400>; +- clocks = <&rcc RTCAPB>, <&rcc RTC>; +- clock-names = "pclk", "rtc_ck"; +- interrupts = ; +- status = "disabled"; +- }; +- +- bsec: efuse@5c005000 { +- compatible = "st,stm32mp15-bsec"; +- reg = <0x5c005000 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- ts_cal1: calib@5c { +- reg = <0x5c 0x2>; +- }; +- ts_cal2: calib@5e { +- reg = <0x5e 0x2>; +- }; +- }; +- +- i2c6: i2c@5c009000 { +- compatible = "st,stm32mp15-i2c"; +- reg = <0x5c009000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C6_K>; +- resets = <&rcc I2C6_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- st,syscfg-fmp = <&syscfg 0x4 0x20>; +- wakeup-source; +- i2c-analog-filter; +- status = "disabled"; +- }; +- +- tamp: tamp@5c00a000 { +- compatible = "st,stm32-tamp", "syscon", "simple-mfd"; +- reg = <0x5c00a000 0x400>; +- }; +- +- /* +- * Break node order to solve dependency probe issue between +- * pinctrl and exti. +- */ +- pinctrl: pin-controller@50002000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,stm32mp157-pinctrl"; +- ranges = <0 0x50002000 0xa400>; +- interrupt-parent = <&exti>; +- st,syscfg = <&exti 0x60 0xff>; +- pins-are-numbered; +- +- gpioa: gpio@50002000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x0 0x400>; +- clocks = <&rcc GPIOA>; +- st,bank-name = "GPIOA"; +- status = "disabled"; +- }; +- +- gpiob: gpio@50003000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x1000 0x400>; +- clocks = <&rcc GPIOB>; +- st,bank-name = "GPIOB"; +- status = "disabled"; +- }; +- +- gpioc: gpio@50004000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x2000 0x400>; +- clocks = <&rcc GPIOC>; +- st,bank-name = "GPIOC"; +- status = "disabled"; +- }; +- +- gpiod: gpio@50005000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x3000 0x400>; +- clocks = <&rcc GPIOD>; +- st,bank-name = "GPIOD"; +- status = "disabled"; +- }; +- +- gpioe: gpio@50006000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x4000 0x400>; +- clocks = <&rcc GPIOE>; +- st,bank-name = "GPIOE"; +- status = "disabled"; +- }; +- +- gpiof: gpio@50007000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x5000 0x400>; +- clocks = <&rcc GPIOF>; +- st,bank-name = "GPIOF"; +- status = "disabled"; +- }; +- +- gpiog: gpio@50008000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x6000 0x400>; +- clocks = <&rcc GPIOG>; +- st,bank-name = "GPIOG"; +- status = "disabled"; +- }; +- +- gpioh: gpio@50009000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x7000 0x400>; +- clocks = <&rcc GPIOH>; +- st,bank-name = "GPIOH"; +- status = "disabled"; +- }; +- +- gpioi: gpio@5000a000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x8000 0x400>; +- clocks = <&rcc GPIOI>; +- st,bank-name = "GPIOI"; +- status = "disabled"; +- }; +- +- gpioj: gpio@5000b000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x9000 0x400>; +- clocks = <&rcc GPIOJ>; +- st,bank-name = "GPIOJ"; +- status = "disabled"; +- }; +- +- gpiok: gpio@5000c000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0xa000 0x400>; +- clocks = <&rcc GPIOK>; +- st,bank-name = "GPIOK"; +- status = "disabled"; +- }; +- }; +- +- pinctrl_z: pin-controller-z@54004000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,stm32mp157-z-pinctrl"; +- ranges = <0 0x54004000 0x400>; +- pins-are-numbered; +- interrupt-parent = <&exti>; +- st,syscfg = <&exti 0x60 0xff>; +- +- gpioz: gpio@54004000 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0 0x400>; +- clocks = <&rcc GPIOZ>; +- st,bank-name = "GPIOZ"; +- st,bank-ioport = <11>; +- status = "disabled"; +- }; +- }; +- }; +- +- mlahb: ahb { +- compatible = "st,mlahb", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- dma-ranges = <0x00000000 0x38000000 0x10000>, +- <0x10000000 0x10000000 0x60000>, +- <0x30000000 0x30000000 0x60000>; +- +- m4_rproc: m4@10000000 { +- compatible = "st,stm32mp1-m4"; +- reg = <0x10000000 0x40000>, +- <0x30000000 0x40000>, +- <0x38000000 0x10000>; +- resets = <&rcc MCU_R>; +- st,syscfg-holdboot = <&rcc 0x10C 0x1>; +- st,syscfg-tz = <&rcc 0x000 0x1>; +- st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; +- st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; +- st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp153.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp153.dtsi +deleted file mode 100644 +index 1c1889b194cf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp153.dtsi ++++ /dev/null +@@ -1,52 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved +- * Author: Alexandre Torgue for STMicroelectronics. +- */ +- +-#include "stm32mp151.dtsi" +- +-/ { +- cpus { +- cpu1: cpu@1 { +- compatible = "arm,cortex-a7"; +- clock-frequency = <650000000>; +- device_type = "cpu"; +- reg = <1>; +- }; +- }; +- +- arm-pmu { +- interrupts = , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- soc { +- m_can1: can@4400e000 { +- compatible = "bosch,m_can"; +- reg = <0x4400e000 0x400>, <0x44011000 0x1400>; +- reg-names = "m_can", "message_ram"; +- interrupts = , +- ; +- interrupt-names = "int0", "int1"; +- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; +- clock-names = "hclk", "cclk"; +- bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; +- status = "disabled"; +- }; +- +- m_can2: can@4400f000 { +- compatible = "bosch,m_can"; +- reg = <0x4400f000 0x400>, <0x44011000 0x2800>; +- reg-names = "m_can", "message_ram"; +- interrupts = , +- ; +- interrupt-names = "int0", "int1"; +- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; +- clock-names = "hclk", "cclk"; +- bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp153c-dhcom-drc02.dts b/scripts/dtc/include-prefixes/arm/stm32mp153c-dhcom-drc02.dts +deleted file mode 100644 +index b4e504f026ce..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp153c-dhcom-drc02.dts ++++ /dev/null +@@ -1,39 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +-/* +- * Copyright (C) 2020 Marek Vasut +- * +- * DHCOM STM32MP1 variant: +- * DHCM-STM32MP153C-C065-R102-F0819-SPI-E2-CAN2-RTC-I-01D2 +- * DHCOM PCB number: 587-200 or newer +- * DRC02 PCB number: 568-100 or newer +- */ +-/dts-v1/; +- +-#include "stm32mp153.dtsi" +-#include "stm32mp15xc.dtsi" +-#include "stm32mp15xx-dhcom-som.dtsi" +-#include "stm32mp15xx-dhcom-drc02.dtsi" +- +-/ { +- model = "DH electronics STM32MP153C DHCOM DRC02"; +- compatible = "dh,stm32mp153c-dhcom-drc02", "dh,stm32mp153c-dhcom-som", +- "st,stm32mp153"; +-}; +- +-&cryp1 { +- status = "okay"; +-}; +- +-&m_can1 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&m_can1_pins_a>; +- pinctrl-1 = <&m_can1_sleep_pins_a>; +- status = "okay"; +-}; +- +-&m_can2 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&m_can2_pins_a>; +- pinctrl-1 = <&m_can2_sleep_pins_a>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp157.dtsi +deleted file mode 100644 +index 54e73ccea446..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157.dtsi ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved +- * Author: Alexandre Torgue for STMicroelectronics. +- */ +- +-#include "stm32mp153.dtsi" +- +-/ { +- soc { +- gpu: gpu@59000000 { +- compatible = "vivante,gc"; +- reg = <0x59000000 0x800>; +- interrupts = ; +- clocks = <&rcc GPU>, <&rcc GPU_K>; +- clock-names = "bus" ,"core"; +- resets = <&rcc GPU_R>; +- }; +- +- dsi: dsi@5a000000 { +- compatible = "st,stm32-dsi"; +- reg = <0x5a000000 0x800>; +- clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; +- clock-names = "pclk", "ref", "px_clk"; +- resets = <&rcc DSI_R>; +- reset-names = "apb"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157a-avenger96.dts b/scripts/dtc/include-prefixes/arm/stm32mp157a-avenger96.dts +deleted file mode 100644 +index 8a6eaca994d1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157a-avenger96.dts ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +-/* +- * Copyright (C) Linaro Ltd 2019 - All Rights Reserved +- * Author: Manivannan Sadhasivam +- * Copyright (C) 2020 Marek Vasut +- */ +- +-/dts-v1/; +- +-/* This DT is here only for backward compatibility */ +-#include "stm32mp157a-dhcor-avenger96.dts" +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157a-dhcor-avenger96.dts b/scripts/dtc/include-prefixes/arm/stm32mp157a-dhcor-avenger96.dts +deleted file mode 100644 +index 2e3c9fbb4eb3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157a-dhcor-avenger96.dts ++++ /dev/null +@@ -1,38 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +-/* +- * Copyright (C) Linaro Ltd 2019 - All Rights Reserved +- * Author: Manivannan Sadhasivam +- * Copyright (C) 2020 Marek Vasut +- * +- * DHCOR STM32MP1 variant: +- * DHCR-STM32MP157A-C065-R102-V18-SPI-C-01LG +- * DHCOR PCB number: 586-100 or newer +- * Avenger96 PCB number: 588-200 or newer +- */ +- +-/dts-v1/; +- +-#include "stm32mp157.dtsi" +-#include "stm32mp15xc.dtsi" +-#include "stm32mp15xx-dhcor-som.dtsi" +-#include "stm32mp15xx-dhcor-avenger96.dtsi" +- +-/ { +- model = "Arrow Electronics STM32MP157A Avenger96 board"; +- compatible = "arrow,stm32mp157a-avenger96", "dh,stm32mp157a-dhcor-som", +- "st,stm32mp157"; +-}; +- +-&m_can1 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&m_can1_pins_b>; +- pinctrl-1 = <&m_can1_sleep_pins_b>; +- status = "disabled"; +-}; +- +-&m_can2 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&m_can2_pins_a>; +- pinctrl-1 = <&m_can2_sleep_pins_a>; +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157a-dk1.dts b/scripts/dtc/include-prefixes/arm/stm32mp157a-dk1.dts +deleted file mode 100644 +index 4c8be9c8eb20..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157a-dk1.dts ++++ /dev/null +@@ -1,28 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved +- * Author: Alexandre Torgue for STMicroelectronics. +- */ +- +-/dts-v1/; +- +-#include "stm32mp157.dtsi" +-#include "stm32mp15-pinctrl.dtsi" +-#include "stm32mp15xxac-pinctrl.dtsi" +-#include "stm32mp15xx-dkx.dtsi" +- +-/ { +- model = "STMicroelectronics STM32MP157A-DK1 Discovery Board"; +- compatible = "st,stm32mp157a-dk1", "st,stm32mp157"; +- +- aliases { +- ethernet0 = ðernet0; +- serial0 = &uart4; +- serial1 = &usart3; +- serial2 = &uart7; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157a-icore-stm32mp1-ctouch2.dts b/scripts/dtc/include-prefixes/arm/stm32mp157a-icore-stm32mp1-ctouch2.dts +deleted file mode 100644 +index d3058a036c74..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157a-icore-stm32mp1-ctouch2.dts ++++ /dev/null +@@ -1,47 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (c) STMicroelectronics 2019 - All Rights Reserved +- * Copyright (c) 2020 Engicam srl +- * Copyright (c) 2020 Amarula Solutons(India) +- */ +- +-/dts-v1/; +-#include "stm32mp157.dtsi" +-#include "stm32mp157a-icore-stm32mp1.dtsi" +-#include "stm32mp15-pinctrl.dtsi" +-#include "stm32mp15xxaa-pinctrl.dtsi" +-#include +- +-/ { +- model = "Engicam i.Core STM32MP1 C.TOUCH 2.0"; +- compatible = "engicam,icore-stm32mp1-ctouch2", +- "engicam,icore-stm32mp1", "st,stm32mp157"; +- +- aliases { +- serial0 = &uart4; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&sdmmc1 { +- bus-width = <4>; +- disable-wp; +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc1_b4_pins_a>; +- pinctrl-1 = <&sdmmc1_b4_od_pins_a>; +- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; +- st,neg-edge; +- vmmc-supply = <&v3v3>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default", "sleep", "idle"; +- pinctrl-0 = <&uart4_pins_a>; +- pinctrl-1 = <&uart4_sleep_pins_a>; +- pinctrl-2 = <&uart4_idle_pins_a>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/scripts/dtc/include-prefixes/arm/stm32mp157a-icore-stm32mp1-edimm2.2.dts +deleted file mode 100644 +index ec9f1d1cd50f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157a-icore-stm32mp1-edimm2.2.dts ++++ /dev/null +@@ -1,47 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (c) STMicroelectronics 2019 - All Rights Reserved +- * Copyright (c) 2020 Engicam srl +- * Copyright (c) 2020 Amarula Solutons(India) +- */ +- +-/dts-v1/; +-#include "stm32mp157.dtsi" +-#include "stm32mp157a-icore-stm32mp1.dtsi" +-#include "stm32mp15-pinctrl.dtsi" +-#include "stm32mp15xxaa-pinctrl.dtsi" +-#include +- +-/ { +- model = "Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit"; +- compatible = "engicam,icore-stm32mp1-edimm2.2", +- "engicam,icore-stm32mp1", "st,stm32mp157"; +- +- aliases { +- serial0 = &uart4; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&sdmmc1 { +- bus-width = <4>; +- disable-wp; +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc1_b4_pins_a>; +- pinctrl-1 = <&sdmmc1_b4_od_pins_a>; +- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; +- st,neg-edge; +- vmmc-supply = <&v3v3>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default", "sleep", "idle"; +- pinctrl-0 = <&uart4_pins_a>; +- pinctrl-1 = <&uart4_sleep_pins_a>; +- pinctrl-2 = <&uart4_idle_pins_a>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157a-icore-stm32mp1.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp157a-icore-stm32mp1.dtsi +deleted file mode 100644 +index 01166ccacf2b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157a-icore-stm32mp1.dtsi ++++ /dev/null +@@ -1,196 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (c) STMicroelectronics 2019 - All Rights Reserved +- * Copyright (c) 2020 Engicam srl +- * Copyright (c) 2020 Amarula Solutons(India) +- */ +- +-/ { +- compatible = "engicam,icore-stm32mp1", "st,stm32mp157"; +- +- memory@c0000000 { +- device_type = "memory"; +- reg = <0xc0000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- mcuram2: mcuram2@10000000 { +- compatible = "shared-dma-pool"; +- reg = <0x10000000 0x40000>; +- no-map; +- }; +- +- vdev0vring0: vdev0vring0@10040000 { +- compatible = "shared-dma-pool"; +- reg = <0x10040000 0x1000>; +- no-map; +- }; +- +- vdev0vring1: vdev0vring1@10041000 { +- compatible = "shared-dma-pool"; +- reg = <0x10041000 0x1000>; +- no-map; +- }; +- +- vdev0buffer: vdev0buffer@10042000 { +- compatible = "shared-dma-pool"; +- reg = <0x10042000 0x4000>; +- no-map; +- }; +- +- mcuram: mcuram@30000000 { +- compatible = "shared-dma-pool"; +- reg = <0x30000000 0x40000>; +- no-map; +- }; +- +- retram: retram@38000000 { +- compatible = "shared-dma-pool"; +- reg = <0x38000000 0x10000>; +- no-map; +- }; +- }; +- +- vddcore: regulator-vddcore { +- compatible = "regulator-fixed"; +- regulator-name = "vddcore"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vdd: regulator-vdd { +- compatible = "regulator-fixed"; +- regulator-name = "vdd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_usb: regulator-vdd-usb { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_usb"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdda: regulator-vdda { +- compatible = "regulator-fixed"; +- regulator-name = "vdda"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_ddr: regulator-vdd-ddr { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_ddr"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- }; +- +- vtt_ddr: regulator-vtt-ddr { +- compatible = "regulator-fixed"; +- regulator-name = "vtt_ddr"; +- regulator-min-microvolt = <675000>; +- regulator-max-microvolt = <675000>; +- regulator-always-on; +- vin-supply = <&vdd>; +- }; +- +- vref_ddr: regulator-vref-ddr { +- compatible = "regulator-fixed"; +- regulator-name = "vref_ddr"; +- regulator-min-microvolt = <675000>; +- regulator-max-microvolt = <675000>; +- regulator-always-on; +- vin-supply = <&vdd>; +- }; +- +- vdd_sd: regulator-vdd-sd { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- v3v3: regulator-v3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "v3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- v2v8: regulator-v2v8 { +- compatible = "regulator-fixed"; +- regulator-name = "v2v8"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- vin-supply = <&v3v3>; +- }; +- +- v1v8: regulator-v1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "v1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- vin-supply = <&v3v3>; +- }; +-}; +- +-&dts { +- status = "okay"; +-}; +- +-&i2c2 { +- i2c-scl-falling-time-ns = <20>; +- i2c-scl-rising-time-ns = <185>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c2_pins_a>; +- pinctrl-1 = <&i2c2_sleep_pins_a>; +- status = "okay"; +-}; +- +-&ipcc { +- status = "okay"; +-}; +- +-&iwdg2{ +- timeout-sec = <32>; +- status = "okay"; +-}; +- +-&m4_rproc{ +- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, +- <&vdev0vring1>, <&vdev0buffer>; +- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; +- mbox-names = "vq0", "vq1", "shutdown"; +- interrupt-parent = <&exti>; +- interrupts = <68 1>; +- status = "okay"; +-}; +- +-&rng1 { +- status = "okay"; +-}; +- +-&rtc{ +- status = "okay"; +-}; +- +-&vrefbuf { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- vdda-supply = <&vdd>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157a-iot-box.dts b/scripts/dtc/include-prefixes/arm/stm32mp157a-iot-box.dts +deleted file mode 100644 +index 70f394b4d3c0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157a-iot-box.dts ++++ /dev/null +@@ -1,68 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2020 Manivannan Sadhasivam +- */ +- +-/dts-v1/; +-#include "stm32mp157a-stinger96.dtsi" +- +-/ { +- model = "Shiratech STM32MP157A IoT Box"; +- compatible = "shiratech,stm32mp157a-iot-box", "st,stm32mp157"; +- +- wlan_pwr: regulator-wlan { +- compatible = "regulator-fixed"; +- +- regulator-name = "wl-reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&i2c2 { +- ccs811@5b { +- compatible = "ams,ccs811"; +- reg = <0x5b>; +- wakeup-gpios = <&gpioa 12 GPIO_ACTIVE_LOW>; +- reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-/* WiFi */ +-&sdmmc2 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc2_b4_pins_a>; +- pinctrl-1 = <&sdmmc2_b4_od_pins_b>; +- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; +- broken-cd; +- non-removable; +- st,neg-edge; +- bus-width = <1>; +- vmmc-supply = <&wlan_pwr>; +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- brcmf: bcrmf@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* Bluetooth */ +-&uart4 { +- /* Note: HW flow control is broken, hence using custom CTS/RTS gpios */ +- /delete-property/st,hw-flow-ctrl; +- cts-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; +- rts-gpios = <&gpiob 0 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- bluetooth { +- shutdown-gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>; +- compatible = "brcm,bcm43438-bt"; +- max-speed = <115200>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/scripts/dtc/include-prefixes/arm/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts +deleted file mode 100644 +index 5670b23812a2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts ++++ /dev/null +@@ -1,154 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (c) STMicroelectronics 2019 - All Rights Reserved +- * Copyright (c) 2020 Engicam srl +- * Copyright (c) 2020 Amarula Solutons(India) +- */ +- +-/dts-v1/; +-#include "stm32mp157.dtsi" +-#include "stm32mp157a-microgea-stm32mp1.dtsi" +-#include "stm32mp15-pinctrl.dtsi" +-#include "stm32mp15xxaa-pinctrl.dtsi" +-#include +- +-/ { +- model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 7\" Open Frame"; +- compatible = "engicam,microgea-stm32mp1-microdev2.0-of7", +- "engicam,microgea-stm32mp1", "st,stm32mp157"; +- +- aliases { +- serial0 = &uart4; +- serial1 = &uart8; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- backlight: backlight { +- compatible = "gpio-backlight"; +- gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; +- default-on; +- }; +- +- lcd_3v3: regulator-lcd-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "lcd_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpiof 10 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- power-supply = <&panel_pwr>; +- }; +- +- panel_pwr: regulator-panel-pwr { +- compatible = "regulator-fixed"; +- regulator-name = "panel_pwr"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpiob 10 GPIO_ACTIVE_HIGH>; +- regulator-always-on; +- }; +- +- panel { +- compatible = "auo,b101aw03"; +- backlight = <&backlight>; +- enable-gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>; +- power-supply = <&lcd_3v3>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <<dc_ep0_out>; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- i2c-scl-falling-time-ns = <20>; +- i2c-scl-rising-time-ns = <185>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c2_pins_a>; +- pinctrl-1 = <&i2c2_sleep_pins_a>; +- status = "okay"; +-}; +- +-<dc { +- pinctrl-names = "default"; +- pinctrl-0 = <<dc_pins>; +- status = "okay"; +- +- port { +- ltdc_ep0_out: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_in>; +- }; +- }; +-}; +- +-&pinctrl { +- ltdc_pins: ltdc-0 { +- pins { +- pinmux = , /* LTDC_B2 */ +- , /* LTDC_R6 */ +- , /* LTDC_R5 */ +- , /* LTDC_B3 */ +- , /* LTDC_B0 */ +- , /* LTDC_G0 */ +- , /* LTDC_G1 */ +- , /* LTDC_DE */ +- , /* LTDC_R7 */ +- , /* LTDC_CLK */ +- , /* LTDC_B1 */ +- , /* LTDC_R0 */ +- , /* LTDC_R1 */ +- , /* LTDC_R2 */ +- , /* LTDC_R3 */ +- , /* LTDC_R4 */ +- , /* LTDC_G2 */ +- , /* LTDC_G3 */ +- , /* LTDC_G4 */ +- , /* LTDC_G5 */ +- , /* LTDC_G6 */ +- , /* LTDC_G7 */ +- , /* LTDC_B4 */ +- , /* LTDC_B5 */ +- , /* LTDC_B6 */ +- , /* LTDC_B7 */ +- , /* LTDC_VSYNC */ +- ; /* LTDC_HSYNC */ +- bias-disable; +- drive-push-pull; +- slew-rate = <3>; +- }; +- }; +-}; +- +-&sdmmc1 { +- bus-width = <4>; +- disable-wp; +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc1_b4_pins_a>; +- pinctrl-1 = <&sdmmc1_b4_od_pins_a>; +- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; +- st,neg-edge; +- vmmc-supply = <&vdd>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default", "sleep", "idle"; +- pinctrl-0 = <&uart4_pins_a>; +- pinctrl-1 = <&uart4_sleep_pins_a>; +- pinctrl-2 = <&uart4_idle_pins_a>; +- status = "okay"; +-}; +- +-/* J31: RS323 */ +-&uart8 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart8_pins_a>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/scripts/dtc/include-prefixes/arm/stm32mp157a-microgea-stm32mp1-microdev2.0.dts +deleted file mode 100644 +index 7a75868164dc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157a-microgea-stm32mp1-microdev2.0.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (c) STMicroelectronics 2019 - All Rights Reserved +- * Copyright (c) 2020 Engicam srl +- * Copyright (c) 2020 Amarula Solutons(India) +- */ +- +-/dts-v1/; +-#include "stm32mp157.dtsi" +-#include "stm32mp157a-microgea-stm32mp1.dtsi" +-#include "stm32mp15-pinctrl.dtsi" +-#include "stm32mp15xxaa-pinctrl.dtsi" +-#include +- +-/ { +- model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 Carrier Board"; +- compatible = "engicam,microgea-stm32mp1-microdev2.0", +- "engicam,microgea-stm32mp1", "st,stm32mp157"; +- +- aliases { +- serial0 = &uart4; +- serial1 = &uart8; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&sdmmc1 { +- bus-width = <4>; +- disable-wp; +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc1_b4_pins_a>; +- pinctrl-1 = <&sdmmc1_b4_od_pins_a>; +- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; +- st,neg-edge; +- vmmc-supply = <&vdd>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default", "sleep", "idle"; +- pinctrl-0 = <&uart4_pins_a>; +- pinctrl-1 = <&uart4_sleep_pins_a>; +- pinctrl-2 = <&uart4_idle_pins_a>; +- status = "okay"; +-}; +- +-/* J31: RS323 */ +-&uart8 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart8_pins_a>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157a-microgea-stm32mp1.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp157a-microgea-stm32mp1.dtsi +deleted file mode 100644 +index 0b85175f151e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157a-microgea-stm32mp1.dtsi ++++ /dev/null +@@ -1,148 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (c) STMicroelectronics 2019 - All Rights Reserved +- * Copyright (c) 2020 Engicam srl +- * Copyright (c) 2020 Amarula Solutons(India) +- */ +- +-/ { +- compatible = "engicam,microgea-stm32mp1", "st,stm32mp157"; +- +- memory@c0000000 { +- device_type = "memory"; +- reg = <0xc0000000 0x10000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- mcuram2: mcuram2@10000000 { +- compatible = "shared-dma-pool"; +- reg = <0x10000000 0x40000>; +- no-map; +- }; +- +- vdev0vring0: vdev0vring0@10040000 { +- compatible = "shared-dma-pool"; +- reg = <0x10040000 0x1000>; +- no-map; +- }; +- +- vdev0vring1: vdev0vring1@10041000 { +- compatible = "shared-dma-pool"; +- reg = <0x10041000 0x1000>; +- no-map; +- }; +- +- vdev0buffer: vdev0buffer@10042000 { +- compatible = "shared-dma-pool"; +- reg = <0x10042000 0x4000>; +- no-map; +- }; +- +- mcuram: mcuram@30000000 { +- compatible = "shared-dma-pool"; +- reg = <0x30000000 0x40000>; +- no-map; +- }; +- +- retram: retram@38000000 { +- compatible = "shared-dma-pool"; +- reg = <0x38000000 0x10000>; +- no-map; +- }; +- }; +- +- vin: regulator-vin { +- compatible = "regulator-fixed"; +- regulator-name = "vin"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- vddcore: regulator-vddcore { +- compatible = "regulator-fixed"; +- regulator-name = "vddcore"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- vin-supply = <&vin>; +- }; +- +- vdd: regulator-vdd { +- compatible = "regulator-fixed"; +- regulator-name = "vdd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- vin-supply = <&vin>; +- }; +- +- vddq_ddr: regulator-vddq-ddr { +- compatible = "regulator-fixed"; +- regulator-name = "vddq_ddr"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- vin-supply = <&vin>; +- }; +-}; +- +-&dts { +- status = "okay"; +-}; +- +-&fmc { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&fmc_pins_a>; +- pinctrl-1 = <&fmc_sleep_pins_a>; +- status = "okay"; +- +- nand-controller@4,0 { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- nand-on-flash-bbt; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- }; +-}; +- +-&ipcc { +- status = "okay"; +-}; +- +-&iwdg2{ +- timeout-sec = <32>; +- status = "okay"; +-}; +- +-&m4_rproc{ +- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, +- <&vdev0vring1>, <&vdev0buffer>; +- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; +- mbox-names = "vq0", "vq1", "shutdown"; +- interrupt-parent = <&exti>; +- interrupts = <68 1>; +- status = "okay"; +-}; +- +-&rng1 { +- status = "okay"; +-}; +- +-&rtc{ +- status = "okay"; +-}; +- +-&vrefbuf { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- vdda-supply = <&vdd>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157a-stinger96.dts b/scripts/dtc/include-prefixes/arm/stm32mp157a-stinger96.dts +deleted file mode 100644 +index 249a53877512..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157a-stinger96.dts ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2020 Manivannan Sadhasivam +- */ +- +-/dts-v1/; +-#include "stm32mp157a-stinger96.dtsi" +- +-/ { +- model = "Shiratech STM32MP157A Stinger96 board"; +- compatible = "shiratech,stm32mp157a-stinger96", "st,stm32mp157"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157a-stinger96.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp157a-stinger96.dtsi +deleted file mode 100644 +index a4b14ef3caee..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157a-stinger96.dtsi ++++ /dev/null +@@ -1,335 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2020 Manivannan Sadhasivam +- */ +- +-/dts-v1/; +- +-#include "stm32mp157.dtsi" +-#include "stm32mp15-pinctrl.dtsi" +-#include "stm32mp15xxac-pinctrl.dtsi" +-#include +-#include +- +-/ { +- aliases { +- mmc0 = &sdmmc1; +- serial0 = &uart4; +- serial1 = &uart7; +- serial2 = &usart2; +- spi0 = &spi4; +- }; +- +- chosen { +- stdout-path = "serial1:115200n8"; +- }; +- +- memory@c0000000 { +- device_type = "memory"; +- reg = <0xc0000000 0x10000000>; +- }; +- +- led { +- compatible = "gpio-leds"; +- +- led1 { +- label = "green:user1"; +- gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- +- led2 { +- label = "green:user2"; +- gpios = <&gpioh 3 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- +- led3 { +- label = "green:user3"; +- gpios = <&gpioh 2 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc1"; +- default-state = "off"; +- }; +- +- led4 { +- label = "green:user4"; +- gpios = <&gpiof 12 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "none"; +- default-state = "off"; +- panic-indicator; +- }; +- }; +- +- sd_switch: regulator-sd_switch { +- compatible = "regulator-gpio"; +- regulator-name = "sd_switch"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2900000>; +- regulator-type = "voltage"; +- regulator-always-on; +- +- gpios = <&gpioa 8 GPIO_ACTIVE_HIGH>; +- gpios-states = <0>; +- states = <1800000 0x1>, +- <2900000 0x0>; +- }; +-}; +- +-/* Only headless mode is supported */ +-&gpu { +- status = "disabled"; +-}; +- +-/* LS-I2C0 */ +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins_a>; +- i2c-scl-rising-time-ns = <1000>; +- i2c-scl-falling-time-ns = <300>; +- status = "okay"; +- /delete-property/dmas; +- /delete-property/dma-names; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- /delete-property/dmas; +- /delete-property/dma-names; +- +- pmic: stpmic@33 { +- compatible = "st,stpmic1"; +- reg = <0x33>; +- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "okay"; +- +- regulators { +- compatible = "st,stpmic1-regulators"; +- +- ldo1-supply = <&v3v3>; +- ldo2-supply = <&v3v3>; +- ldo3-supply = <&vdd_ddr>; +- ldo5-supply = <&v3v3>; +- ldo6-supply = <&v3v3>; +- pwr_sw1-supply = <&bst_out>; +- pwr_sw2-supply = <&bst_out>; +- +- vddcore: buck1 { +- regulator-name = "vddcore"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- vdd_ddr: buck2 { +- regulator-name = "vdd_ddr"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- vdd: buck3 { +- regulator-name = "vdd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- st,mask-reset; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- v3v3: buck4 { +- regulator-name = "v3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-over-current-protection; +- regulator-initial-mode = <0>; +- }; +- +- vdda: ldo1 { +- regulator-name = "vdda"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- interrupts = ; +- }; +- +- v2v9: ldo2 { +- regulator-name = "v2v9"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- regulator-always-on; +- interrupts = ; +- }; +- +- vtt_ddr: ldo3 { +- regulator-name = "vtt_ddr"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <750000>; +- regulator-always-on; +- regulator-over-current-protection; +- }; +- +- vdd_usb: ldo4 { +- regulator-name = "vdd_usb"; +- interrupts = ; +- }; +- +- vdd_sd: ldo5 { +- regulator-name = "vdd_sd"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- interrupts = ; +- regulator-boot-on; +- }; +- +- v1v8: ldo6 { +- regulator-name = "v1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- interrupts = ; +- }; +- +- vref_ddr: vref_ddr { +- regulator-name = "vref_ddr"; +- regulator-always-on; +- }; +- +- bst_out: boost { +- regulator-name = "bst_out"; +- interrupts = ; +- }; +- +- vbus_otg: pwr_sw1 { +- regulator-name = "vbus_otg"; +- interrupts = ; +- regulator-active-discharge = <1>; +- }; +- +- vbus_sw: pwr_sw2 { +- regulator-name = "vbus_sw"; +- interrupts = ; +- regulator-active-discharge = <1>; +- }; +- }; +- +- onkey { +- compatible = "st,stpmic1-onkey"; +- interrupts = , ; +- interrupt-names = "onkey-falling", "onkey-rising"; +- status = "okay"; +- }; +- +- watchdog { +- compatible = "st,stpmic1-wdt"; +- status = "disabled"; +- }; +- }; +-}; +- +-&iwdg2 { +- timeout-sec = <32>; +- status = "okay"; +-}; +- +-&pwr_regulators { +- vdd-supply = <&vdd>; +- vdd_3v3_usbfs-supply = <&vdd_usb>; +-}; +- +-&rng1 { +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&sdmmc1 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; +- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; +- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; +- broken-cd; +- disable-wp; +- st,sig-dir; +- st,neg-edge; +- st,use-ckin; +- bus-width = <4>; +- vmmc-supply = <&vdd_sd>; +- vqmmc-supply = <&sd_switch>; +- status = "okay"; +-}; +- +-/* LS-SPI0 */ +-&spi4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi4_pins_a>; +- cs-gpios = <&gpioe 11 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-/* BG96 */ +-&usart2 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&usart2_pins_b>; +- pinctrl-1 = <&usart2_sleep_pins_b>; +- st,hw-flow-ctrl; +- status = "okay"; +-}; +- +-/* LS-UART0 */ +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pins_c>; +- st,hw-flow-ctrl; +- status = "okay"; +-}; +- +-/* Debug console */ +-&uart7 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart7_pins_b>; +- status = "okay"; +-}; +- +-&usbh_ehci { +- phys = <&usbphyc_port0>; +- phy-names = "usb"; +- status = "okay"; +-}; +- +-&usbotg_hs { +- dr_mode = "peripheral"; +- pinctrl-0 = <&usbotg_hs_pins_a>; +- pinctrl-names = "default"; +- phy-names = "usb2-phy"; +- phys = <&usbphyc_port1 0>; +- vbus-supply = <&vbus_otg>; +- status = "okay"; +-}; +- +-&usbphyc { +- status = "okay"; +-}; +- +-&usbphyc_port0 { +- phy-supply = <&vdd_usb>; +-}; +- +-&usbphyc_port1 { +- phy-supply = <&vdd_usb>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157c-dhcom-pdk2.dts b/scripts/dtc/include-prefixes/arm/stm32mp157c-dhcom-pdk2.dts +deleted file mode 100644 +index 6dd8216c235e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157c-dhcom-pdk2.dts ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +-/* +- * Copyright (C) 2019-2020 Marek Vasut +- * +- * DHCOM STM32MP1 variant: +- * DHCM-STM32MP157C-C065-R102-F0819-SPI-E2-CAN2-SDR104-RTC-WBT-T-DSI-I-01D2 +- * DHCOM PCB number: 587-200 or newer +- * PDK2 PCB number: 516-400 or newer +- */ +-/dts-v1/; +- +-#include "stm32mp157.dtsi" +-#include "stm32mp15xc.dtsi" +-#include "stm32mp15xx-dhcom-som.dtsi" +-#include "stm32mp15xx-dhcom-pdk2.dtsi" +- +-/ { +- model = "DH electronics STM32MP157C DHCOM Premium Developer Kit (2)"; +- compatible = "dh,stm32mp157c-dhcom-pdk2", "dh,stm32mp157c-dhcom-som", +- "st,stm32mp157"; +-}; +- +-&cryp1 { +- status = "okay"; +-}; +- +-&m_can1 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&m_can1_pins_a>; +- pinctrl-1 = <&m_can1_sleep_pins_a>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157c-dhcom-picoitx.dts b/scripts/dtc/include-prefixes/arm/stm32mp157c-dhcom-picoitx.dts +deleted file mode 100644 +index 7067a860aaff..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157c-dhcom-picoitx.dts ++++ /dev/null +@@ -1,39 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +-/* +- * Copyright (C) 2020 Marek Vasut +- * +- * DHCOM STM32MP1 variant: +- * DHCM-STM32MP157C-C065-R102-F0819-SPI-E-CAN2-SD-RTC-T-DSI-I-01D2 +- * DHCOM PCB number: 587-200 or newer +- * PicoITX PCB number: 487-600 or newer +- */ +-/dts-v1/; +- +-#include "stm32mp157.dtsi" +-#include "stm32mp15xc.dtsi" +-#include "stm32mp15xx-dhcom-som.dtsi" +-#include "stm32mp15xx-dhcom-picoitx.dtsi" +- +-/ { +- model = "DH electronics STM32MP157C DHCOM PicoITX"; +- compatible = "dh,stm32mp157c-dhcom-picoitx", "dh,stm32mp157c-dhcom-som", +- "st,stm32mp157"; +-}; +- +-&cryp1 { +- status = "okay"; +-}; +- +-&m_can1 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&m_can1_pins_a>; +- pinctrl-1 = <&m_can1_sleep_pins_a>; +- status = "okay"; +-}; +- +-&m_can2 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&m_can2_pins_a>; +- pinctrl-1 = <&m_can2_sleep_pins_a>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157c-dk2.dts b/scripts/dtc/include-prefixes/arm/stm32mp157c-dk2.dts +deleted file mode 100644 +index 2bc92ef3aeb9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157c-dk2.dts ++++ /dev/null +@@ -1,101 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved +- * Author: Alexandre Torgue for STMicroelectronics. +- */ +- +-/dts-v1/; +- +-#include "stm32mp157.dtsi" +-#include "stm32mp15xc.dtsi" +-#include "stm32mp15-pinctrl.dtsi" +-#include "stm32mp15xxac-pinctrl.dtsi" +-#include "stm32mp15xx-dkx.dtsi" +- +-/ { +- model = "STMicroelectronics STM32MP157C-DK2 Discovery Board"; +- compatible = "st,stm32mp157c-dk2", "st,stm32mp157"; +- +- aliases { +- ethernet0 = ðernet0; +- serial0 = &uart4; +- serial1 = &usart3; +- serial2 = &uart7; +- serial3 = &usart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&cryp1 { +- status = "okay"; +-}; +- +-&dsi { +- status = "okay"; +- phy-dsi-supply = <®18>; +- +- ports { +- port@0 { +- reg = <0>; +- dsi_in: endpoint { +- remote-endpoint = <<dc_ep1_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- dsi_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +- +- panel@0 { +- compatible = "orisetech,otm8009a"; +- reg = <0>; +- reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; +- power-supply = <&v3v3>; +- status = "okay"; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&dsi_out>; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- touchscreen@38 { +- compatible = "focaltech,ft6236"; +- reg = <0x38>; +- interrupts = <2 2>; +- interrupt-parent = <&gpiof>; +- interrupt-controller; +- touchscreen-size-x = <480>; +- touchscreen-size-y = <800>; +- status = "okay"; +- }; +-}; +- +-<dc { +- status = "okay"; +- +- port { +- ltdc_ep1_out: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&dsi_in>; +- }; +- }; +-}; +- +-&usart2 { +- pinctrl-names = "default", "sleep", "idle"; +- pinctrl-0 = <&usart2_pins_c>; +- pinctrl-1 = <&usart2_sleep_pins_c>; +- pinctrl-2 = <&usart2_idle_pins_c>; +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157c-ed1.dts b/scripts/dtc/include-prefixes/arm/stm32mp157c-ed1.dts +deleted file mode 100644 +index 46b471d09c50..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157c-ed1.dts ++++ /dev/null +@@ -1,400 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved +- * Author: Ludovic Barre for STMicroelectronics. +- */ +-/dts-v1/; +- +-#include "stm32mp157.dtsi" +-#include "stm32mp15xc.dtsi" +-#include "stm32mp15-pinctrl.dtsi" +-#include "stm32mp15xxaa-pinctrl.dtsi" +-#include +-#include +- +-/ { +- model = "STMicroelectronics STM32MP157C eval daughter"; +- compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@c0000000 { +- device_type = "memory"; +- reg = <0xC0000000 0x40000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- mcuram2: mcuram2@10000000 { +- compatible = "shared-dma-pool"; +- reg = <0x10000000 0x40000>; +- no-map; +- }; +- +- vdev0vring0: vdev0vring0@10040000 { +- compatible = "shared-dma-pool"; +- reg = <0x10040000 0x1000>; +- no-map; +- }; +- +- vdev0vring1: vdev0vring1@10041000 { +- compatible = "shared-dma-pool"; +- reg = <0x10041000 0x1000>; +- no-map; +- }; +- +- vdev0buffer: vdev0buffer@10042000 { +- compatible = "shared-dma-pool"; +- reg = <0x10042000 0x4000>; +- no-map; +- }; +- +- mcuram: mcuram@30000000 { +- compatible = "shared-dma-pool"; +- reg = <0x30000000 0x40000>; +- no-map; +- }; +- +- retram: retram@38000000 { +- compatible = "shared-dma-pool"; +- reg = <0x38000000 0x10000>; +- no-map; +- }; +- +- gpu_reserved: gpu@e8000000 { +- reg = <0xe8000000 0x8000000>; +- no-map; +- }; +- }; +- +- aliases { +- serial0 = &uart4; +- }; +- +- sd_switch: regulator-sd_switch { +- compatible = "regulator-gpio"; +- regulator-name = "sd_switch"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2900000>; +- regulator-type = "voltage"; +- regulator-always-on; +- +- gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>; +- gpios-states = <0>; +- states = <1800000 0x1>, +- <2900000 0x0>; +- }; +- +- vin: vin { +- compatible = "regulator-fixed"; +- regulator-name = "vin"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +-}; +- +-&adc { +- /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */ +- pinctrl-0 = <&adc1_in6_pins_a>; +- pinctrl-names = "default"; +- vdd-supply = <&vdd>; +- vdda-supply = <&vdda>; +- vref-supply = <&vdda>; +- status = "disabled"; +- adc1: adc@0 { +- st,adc-channels = <0 1 6>; +- /* 16.5 ck_cycles sampling time */ +- st,min-sample-time-nsecs = <400>; +- status = "okay"; +- }; +-}; +- +-&crc1 { +- status = "okay"; +-}; +- +-&cryp1 { +- status = "okay"; +-}; +- +-&dac { +- pinctrl-names = "default"; +- pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; +- vref-supply = <&vdda>; +- status = "disabled"; +- dac1: dac@1 { +- status = "okay"; +- }; +- dac2: dac@2 { +- status = "okay"; +- }; +-}; +- +-&dts { +- status = "okay"; +-}; +- +-&gpu { +- contiguous-area = <&gpu_reserved>; +-}; +- +-&hash1 { +- status = "okay"; +-}; +- +-&i2c4 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c4_pins_a>; +- pinctrl-1 = <&i2c4_sleep_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- clock-frequency = <400000>; +- status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +- +- pmic: stpmic@33 { +- compatible = "st,stpmic1"; +- reg = <0x33>; +- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "okay"; +- +- regulators { +- compatible = "st,stpmic1-regulators"; +- buck1-supply = <&vin>; +- buck2-supply = <&vin>; +- buck3-supply = <&vin>; +- buck4-supply = <&vin>; +- ldo1-supply = <&v3v3>; +- ldo2-supply = <&v3v3>; +- ldo3-supply = <&vdd_ddr>; +- ldo4-supply = <&vin>; +- ldo5-supply = <&v3v3>; +- ldo6-supply = <&v3v3>; +- vref_ddr-supply = <&vin>; +- boost-supply = <&vin>; +- pwr_sw1-supply = <&bst_out>; +- pwr_sw2-supply = <&bst_out>; +- +- vddcore: buck1 { +- regulator-name = "vddcore"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- vdd_ddr: buck2 { +- regulator-name = "vdd_ddr"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- vdd: buck3 { +- regulator-name = "vdd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- st,mask-reset; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- v3v3: buck4 { +- regulator-name = "v3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-over-current-protection; +- regulator-initial-mode = <0>; +- }; +- +- vdda: ldo1 { +- regulator-name = "vdda"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- interrupts = ; +- }; +- +- v2v8: ldo2 { +- regulator-name = "v2v8"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- interrupts = ; +- }; +- +- vtt_ddr: ldo3 { +- regulator-name = "vtt_ddr"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <750000>; +- regulator-always-on; +- regulator-over-current-protection; +- }; +- +- vdd_usb: ldo4 { +- regulator-name = "vdd_usb"; +- interrupts = ; +- }; +- +- vdd_sd: ldo5 { +- regulator-name = "vdd_sd"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- interrupts = ; +- regulator-boot-on; +- }; +- +- v1v8: ldo6 { +- regulator-name = "v1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- interrupts = ; +- }; +- +- vref_ddr: vref_ddr { +- regulator-name = "vref_ddr"; +- regulator-always-on; +- }; +- +- bst_out: boost { +- regulator-name = "bst_out"; +- interrupts = ; +- }; +- +- vbus_otg: pwr_sw1 { +- regulator-name = "vbus_otg"; +- interrupts = ; +- }; +- +- vbus_sw: pwr_sw2 { +- regulator-name = "vbus_sw"; +- interrupts = ; +- regulator-active-discharge = <1>; +- }; +- }; +- +- onkey { +- compatible = "st,stpmic1-onkey"; +- interrupts = , ; +- interrupt-names = "onkey-falling", "onkey-rising"; +- power-off-time-sec = <10>; +- status = "okay"; +- }; +- +- watchdog { +- compatible = "st,stpmic1-wdt"; +- status = "disabled"; +- }; +- }; +-}; +- +-&ipcc { +- status = "okay"; +-}; +- +-&iwdg2 { +- timeout-sec = <32>; +- status = "okay"; +-}; +- +-&m4_rproc { +- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, +- <&vdev0vring1>, <&vdev0buffer>; +- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; +- mbox-names = "vq0", "vq1", "shutdown", "detach"; +- interrupt-parent = <&exti>; +- interrupts = <68 1>; +- status = "okay"; +-}; +- +-&pwr_regulators { +- vdd-supply = <&vdd>; +- vdd_3v3_usbfs-supply = <&vdd_usb>; +-}; +- +-&rng1 { +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&sdmmc1 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; +- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; +- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; +- cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; +- disable-wp; +- st,sig-dir; +- st,neg-edge; +- st,use-ckin; +- bus-width = <4>; +- vmmc-supply = <&vdd_sd>; +- vqmmc-supply = <&sd_switch>; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-ddr50; +- status = "okay"; +-}; +- +-&sdmmc2 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; +- pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; +- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; +- non-removable; +- no-sd; +- no-sdio; +- st,neg-edge; +- bus-width = <8>; +- vmmc-supply = <&v3v3>; +- vqmmc-supply = <&vdd>; +- mmc-ddr-3_3v; +- status = "okay"; +-}; +- +-&timers6 { +- status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +- timer@5 { +- status = "okay"; +- }; +-}; +- +-&uart4 { +- pinctrl-names = "default", "sleep", "idle"; +- pinctrl-0 = <&uart4_pins_a>; +- pinctrl-1 = <&uart4_sleep_pins_a>; +- pinctrl-2 = <&uart4_idle_pins_a>; +- status = "okay"; +-}; +- +-&usbotg_hs { +- vbus-supply = <&vbus_otg>; +-}; +- +-&usbphyc_port0 { +- phy-supply = <&vdd_usb>; +-}; +- +-&usbphyc_port1 { +- phy-supply = <&vdd_usb>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157c-ev1.dts b/scripts/dtc/include-prefixes/arm/stm32mp157c-ev1.dts +deleted file mode 100644 +index 5c5b1ddf7bfd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157c-ev1.dts ++++ /dev/null +@@ -1,377 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved +- * Author: Ludovic Barre for STMicroelectronics. +- */ +-/dts-v1/; +- +-#include "stm32mp157c-ed1.dts" +-#include +-#include +- +-/ { +- model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; +- compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- serial0 = &uart4; +- serial1 = &usart3; +- ethernet0 = ðernet0; +- }; +- +- clocks { +- clk_ext_camera: clk-ext-camera { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- }; +- +- joystick { +- compatible = "gpio-keys"; +- pinctrl-0 = <&joystick_pins>; +- pinctrl-names = "default"; +- button-0 { +- label = "JoySel"; +- linux,code = ; +- interrupt-parent = <&stmfx_pinctrl>; +- interrupts = <0 IRQ_TYPE_EDGE_RISING>; +- }; +- button-1 { +- label = "JoyDown"; +- linux,code = ; +- interrupt-parent = <&stmfx_pinctrl>; +- interrupts = <1 IRQ_TYPE_EDGE_RISING>; +- }; +- button-2 { +- label = "JoyLeft"; +- linux,code = ; +- interrupt-parent = <&stmfx_pinctrl>; +- interrupts = <2 IRQ_TYPE_EDGE_RISING>; +- }; +- button-3 { +- label = "JoyRight"; +- linux,code = ; +- interrupt-parent = <&stmfx_pinctrl>; +- interrupts = <3 IRQ_TYPE_EDGE_RISING>; +- }; +- button-4 { +- label = "JoyUp"; +- linux,code = ; +- interrupt-parent = <&stmfx_pinctrl>; +- interrupts = <4 IRQ_TYPE_EDGE_RISING>; +- }; +- }; +- +- panel_backlight: panel-backlight { +- compatible = "gpio-backlight"; +- gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; +- default-on; +- status = "okay"; +- }; +-}; +- +-&cec { +- pinctrl-names = "default"; +- pinctrl-0 = <&cec_pins_a>; +- status = "okay"; +-}; +- +-&dcmi { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&dcmi_pins_a>; +- pinctrl-1 = <&dcmi_sleep_pins_a>; +- +- port { +- dcmi_0: endpoint { +- remote-endpoint = <&ov5640_0>; +- bus-type = <5>; +- bus-width = <8>; +- hsync-active = <0>; +- vsync-active = <0>; +- pclk-sample = <1>; +- }; +- }; +-}; +- +-&dsi { +- phy-dsi-supply = <®18>; +- status = "okay"; +- +- ports { +- port@0 { +- reg = <0>; +- dsi_in: endpoint { +- remote-endpoint = <<dc_ep0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- dsi_out: endpoint { +- remote-endpoint = <&dsi_panel_in>; +- }; +- }; +- }; +- +- panel-dsi@0 { +- compatible = "raydium,rm68200"; +- reg = <0>; +- reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; +- backlight = <&panel_backlight>; +- power-supply = <&v3v3>; +- status = "okay"; +- +- port { +- dsi_panel_in: endpoint { +- remote-endpoint = <&dsi_out>; +- }; +- }; +- }; +-}; +- +-ðernet0 { +- status = "okay"; +- pinctrl-0 = <ðernet0_rgmii_pins_a>; +- pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- phy-mode = "rgmii-id"; +- max-speed = <1000>; +- phy-handle = <&phy0>; +- +- mdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +-}; +- +-&fmc { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&fmc_pins_a>; +- pinctrl-1 = <&fmc_sleep_pins_a>; +- status = "okay"; +- +- nand-controller@4,0 { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- nand-on-flash-bbt; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c2_pins_a>; +- pinctrl-1 = <&i2c2_sleep_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- +- ov5640: camera@3c { +- compatible = "ovti,ov5640"; +- reg = <0x3c>; +- clocks = <&clk_ext_camera>; +- clock-names = "xclk"; +- DOVDD-supply = <&v2v8>; +- powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; +- reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; +- rotation = <180>; +- status = "okay"; +- +- port { +- ov5640_0: endpoint { +- remote-endpoint = <&dcmi_0>; +- bus-width = <8>; +- data-shift = <2>; /* lines 9:2 are used */ +- hsync-active = <0>; +- vsync-active = <0>; +- pclk-sample = <1>; +- }; +- }; +- }; +- +- stmfx: stmfx@42 { +- compatible = "st,stmfx-0300"; +- reg = <0x42>; +- interrupts = <8 IRQ_TYPE_EDGE_RISING>; +- interrupt-parent = <&gpioi>; +- vdd-supply = <&v3v3>; +- +- stmfx_pinctrl: pinctrl { +- compatible = "st,stmfx-0300-pinctrl"; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&stmfx_pinctrl 0 0 24>; +- +- joystick_pins: joystick-pins { +- pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; +- bias-pull-down; +- }; +- }; +- }; +-}; +- +-&i2c5 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c5_pins_a>; +- pinctrl-1 = <&i2c5_sleep_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +-}; +- +-<dc { +- status = "okay"; +- +- port { +- ltdc_ep0_out: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&dsi_in>; +- }; +- }; +-}; +- +-&m_can1 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&m_can1_pins_a>; +- pinctrl-1 = <&m_can1_sleep_pins_a>; +- status = "okay"; +-}; +- +-&qspi { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; +- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; +- reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- flash0: mx66l51235l@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-rx-bus-width = <4>; +- spi-max-frequency = <108000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- flash1: mx66l51235l@1 { +- compatible = "jedec,spi-nor"; +- reg = <1>; +- spi-rx-bus-width = <4>; +- spi-max-frequency = <108000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&sdmmc3 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc3_b4_pins_a>; +- pinctrl-1 = <&sdmmc3_b4_od_pins_a>; +- pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; +- broken-cd; +- st,neg-edge; +- bus-width = <4>; +- vmmc-supply = <&v3v3>; +- status = "disabled"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins_a>; +- status = "disabled"; +-}; +- +-&timers2 { +- /* spare dmas for other usage (un-delete to enable pwm capture) */ +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +- pwm { +- pinctrl-0 = <&pwm2_pins_a>; +- pinctrl-1 = <&pwm2_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- status = "okay"; +- }; +- timer@1 { +- status = "okay"; +- }; +-}; +- +-&timers8 { +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +- pwm { +- pinctrl-0 = <&pwm8_pins_a>; +- pinctrl-1 = <&pwm8_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- status = "okay"; +- }; +- timer@7 { +- status = "okay"; +- }; +-}; +- +-&timers12 { +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +- pwm { +- pinctrl-0 = <&pwm12_pins_a>; +- pinctrl-1 = <&pwm12_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- status = "okay"; +- }; +- timer@11 { +- status = "okay"; +- }; +-}; +- +-&usart3 { +- pinctrl-names = "default", "sleep", "idle"; +- pinctrl-0 = <&usart3_pins_b>; +- pinctrl-1 = <&usart3_sleep_pins_b>; +- pinctrl-2 = <&usart3_idle_pins_b>; +- /* +- * HW flow control USART3_RTS is optional, and isn't default wired to +- * the connector. SB23 needs to be soldered in order to use it, and R77 +- * (ETH_CLK) should be removed. +- */ +- uart-has-rtscts; +- status = "disabled"; +-}; +- +-&usbh_ehci { +- phys = <&usbphyc_port0>; +- status = "okay"; +-}; +- +-&usbotg_hs { +- pinctrl-0 = <&usbotg_hs_pins_a>; +- pinctrl-names = "default"; +- phys = <&usbphyc_port1 0>; +- phy-names = "usb2-phy"; +- status = "okay"; +-}; +- +-&usbphyc { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157c-lxa-mc1.dts b/scripts/dtc/include-prefixes/arm/stm32mp157c-lxa-mc1.dts +deleted file mode 100644 +index 1e9bf7eea0f1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157c-lxa-mc1.dts ++++ /dev/null +@@ -1,252 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */ +-/* +- * Copyright (C) 2020 STMicroelectronics - All Rights Reserved +- * Copyright (C) 2020 Ahmad Fatoum, Pengutronix +- */ +- +-/dts-v1/; +- +-#include "stm32mp157.dtsi" +-#include "stm32mp15xx-osd32.dtsi" +-#include "stm32mp15xxac-pinctrl.dtsi" +- +-#include +-#include +- +-/ { +- model = "Linux Automation MC-1 board"; +- compatible = "lxa,stm32mp157c-mc1", "oct,stm32mp15xx-osd32", "st,stm32mp157"; +- +- aliases { +- ethernet0 = ðernet0; +- mmc0 = &sdmmc1; +- mmc1 = &sdmmc2; +- serial0 = &uart4; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&backlight_pwm 1 100000 PWM_POLARITY_INVERTED>; +- brightness-levels = <0 31 63 95 127 159 191 223 255>; +- default-brightness-level = <7>; +- power-supply = <®_5v2>; /* 3V3_BACKLIGHT */ +- }; +- +- chosen { +- stdout-path = &uart4; +- }; +- +- led-controller-0 { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "mc1:green:act"; +- gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- led-controller-1 { +- compatible = "pwm-leds"; +- +- /* led-1 to led-3 are part of a single RGB led */ +- led-1 { +- label = "mc1:red:rgb"; +- pwms = <&leds_pwm 1 1000000 0>; +- max-brightness = <255>; +- active-low; +- }; +- +- led-2 { +- label = "mc1:green:rgb"; +- pwms = <&leds_pwm 2 1000000 0>; +- max-brightness = <255>; +- active-low; +- }; +- +- led-3 { +- label = "mc1:blue:rgb"; +- pwms = <&leds_pwm 3 1000000 0>; +- max-brightness = <255>; +- active-low; +- }; +- }; +- +- panel: panel { +- compatible = "edt,etm0700g0edh6", "simple-panel"; +- backlight = <&backlight>; +- enable-gpios = <&gpiod 4 GPIO_ACTIVE_HIGH>; +- power-supply = <®_3v3>; +- +- port { +- panel_input: endpoint { +- remote-endpoint = <<dc_ep0_out>; +- }; +- }; +- }; +- +- reg_3v3: regulator_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- vin-supply = <&v3v3>; +- }; +- +- /* supplied by either debug board or PoE */ +- reg_5v2: regulator_5v2 { +- compatible = "regulator-fixed"; +- regulator-name = "5V2"; +- regulator-min-microvolt = <5200000>; +- regulator-max-microvolt = <5200000>; +- regulator-always-on; +- }; +-}; +- +-ðernet0 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <ðernet0_rgmii_pins_b>; +- pinctrl-1 = <ðernet0_rgmii_sleep_pins_b>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy>; +- status = "okay"; +- +- mdio0 { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy@3 { /* KSZ9031RN */ +- reg = <3>; +- reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */ +- interrupt-parent = <&gpioa>; +- interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* ETH_MDINT# */ +- reset-assert-us = <10000>; +- reset-deassert-us = <300>; +- micrel,force-master; +- }; +- }; +-}; +- +-&gpioz { +- gpio-line-names = "HWID0", "HWID1", "HWID2", "HWID3", "", "", +- "HWID4", "HWID5"; +-}; +- +-&i2c5 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c5_pins_b>; +- pinctrl-1 = <&i2c5_sleep_pins_b>; +- clock-frequency = <400000>; +- status = "okay"; +- +- touchscreen@38 { +- compatible = "edt,edt-ft5x06"; +- interrupt-parent = <&gpiod>; +- interrupts = <11 IRQ_TYPE_EDGE_FALLING>; /* TOUCH_INT# */ +- vcc-supply = <®_3v3>; +- reg = <0x38>; +- reset-gpios = <&gpiof 8 GPIO_ACTIVE_LOW>; /* TOUCH_RESET# */ +- touchscreen-size-x = <1792>; +- touchscreen-size-y = <1024>; +- wakeup-source; +- }; +-}; +- +-<dc { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <<dc_pins_c>; +- pinctrl-1 = <<dc_sleep_pins_c>; +- status = "okay"; +- +- port { +- ltdc_ep0_out: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_input>; +- }; +- }; +-}; +- +-&pmic { +- regulators { +- buck4-supply = <®_5v2>; /* VIN */ +- ldo2-supply = <®_5v2>; /* PMIC_LDO25IN */ +- ldo5-supply = <®_5v2>; /* PMIC_LDO25IN */ +- boost-supply = <®_5v2>; /* PMIC_BSTIN */ +- pwr_sw2-supply = <&bst_out>; /* PMIC_SWIN */ +- }; +-}; +- +-&sdmmc1 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc1_b4_pins_a>; +- pinctrl-1 = <&sdmmc1_b4_od_pins_a>; +- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; +- bus-width = <4>; +- cd-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; +- disable-wp; +- no-1-8-v; +- st,neg-edge; +- vmmc-supply = <®_3v3>; +- status = "okay"; +-}; +- +-&sdmmc1_b4_pins_a { +- /* +- * board lacks external pull-ups on SDMMC lines. Class 10 SD refuses to +- * work, thus enable internal pull-ups. +- */ +- pins1 { +- /delete-property/ bias-disable; +- bias-pull-up; +- }; +- pins2 { +- /delete-property/ bias-disable; +- bias-pull-up; +- }; +-}; +- +-&sdmmc2 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; +- pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; +- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; +- bus-width = <8>; +- mmc-ddr-3_3v; +- no-1-8-v; +- no-sd; +- no-sdio; +- non-removable; +- st,neg-edge; +- vmmc-supply = <®_3v3>; +- status = "okay"; +-}; +- +-&timers3 { +- status = "okay"; +- +- backlight_pwm: pwm { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&pwm3_pins_b>; +- pinctrl-1 = <&pwm3_sleep_pins_b>; +- status = "okay"; +- }; +-}; +- +-&timers5 { +- status = "okay"; +- +- leds_pwm: pwm { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&pwm5_pins_b>; +- pinctrl-1 = <&pwm5_sleep_pins_b>; +- status = "okay"; +- }; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pins_a>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157c-odyssey-som.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp157c-odyssey-som.dtsi +deleted file mode 100644 +index 2d9461006810..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157c-odyssey-som.dtsi ++++ /dev/null +@@ -1,273 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) 2020 Marcin Sloniewski . +- */ +- +-/dts-v1/; +- +-#include "stm32mp157.dtsi" +-#include "stm32mp15xc.dtsi" +-#include "stm32mp15-pinctrl.dtsi" +-#include "stm32mp15xxac-pinctrl.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "Seeed Studio Odyssey-STM32MP157C SOM"; +- compatible = "seeed,stm32mp157c-odyssey-som", "st,stm32mp157"; +- +- memory@c0000000 { +- device_type = "memory"; +- reg = <0xc0000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- mcuram2: mcuram2@10000000 { +- compatible = "shared-dma-pool"; +- reg = <0x10000000 0x40000>; +- no-map; +- }; +- +- vdev0vring0: vdev0vring0@10040000 { +- compatible = "shared-dma-pool"; +- reg = <0x10040000 0x1000>; +- no-map; +- }; +- +- vdev0vring1: vdev0vring1@10041000 { +- compatible = "shared-dma-pool"; +- reg = <0x10041000 0x1000>; +- no-map; +- }; +- +- vdev0buffer: vdev0buffer@10042000 { +- compatible = "shared-dma-pool"; +- reg = <0x10042000 0x4000>; +- no-map; +- }; +- +- mcuram: mcuram@30000000 { +- compatible = "shared-dma-pool"; +- reg = <0x30000000 0x40000>; +- no-map; +- }; +- +- retram: retram@38000000 { +- compatible = "shared-dma-pool"; +- reg = <0x38000000 0x10000>; +- no-map; +- }; +- +- gpu_reserved: gpu@d4000000 { +- reg = <0xd4000000 0x4000000>; +- no-map; +- }; +- }; +- +- led { +- compatible = "gpio-leds"; +- led-blue { +- color = ; +- function = LED_FUNCTION_HEARTBEAT; +- gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-&gpu { +- contiguous-area = <&gpu_reserved>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +- +- pmic: stpmic@33 { +- compatible = "st,stpmic1"; +- reg = <0x33>; +- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- regulators { +- compatible = "st,stpmic1-regulators"; +- ldo1-supply = <&v3v3>; +- ldo3-supply = <&vdd_ddr>; +- ldo6-supply = <&v3v3>; +- pwr_sw1-supply = <&bst_out>; +- pwr_sw2-supply = <&bst_out>; +- +- vddcore: buck1 { +- regulator-name = "vddcore"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- vdd_ddr: buck2 { +- regulator-name = "vdd_ddr"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- vdd: buck3 { +- regulator-name = "vdd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- st,mask-reset; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- v3v3: buck4 { +- regulator-name = "v3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-over-current-protection; +- regulator-initial-mode = <0>; +- }; +- +- v1v8_audio: ldo1 { +- regulator-name = "v1v8_audio"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- interrupts = ; +- }; +- +- v3v3_hdmi: ldo2 { +- regulator-name = "v3v3_hdmi"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- interrupts = ; +- }; +- +- vtt_ddr: ldo3 { +- regulator-name = "vtt_ddr"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <750000>; +- regulator-always-on; +- regulator-over-current-protection; +- }; +- +- vdd_usb: ldo4 { +- regulator-name = "vdd_usb"; +- interrupts = ; +- }; +- +- vdda: ldo5 { +- regulator-name = "vdda"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- interrupts = ; +- regulator-boot-on; +- }; +- +- v1v2_hdmi: ldo6 { +- regulator-name = "v1v2_hdmi"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- interrupts = ; +- }; +- +- vref_ddr: vref_ddr { +- regulator-name = "vref_ddr"; +- regulator-always-on; +- }; +- +- bst_out: boost { +- regulator-name = "bst_out"; +- interrupts = ; +- }; +- +- vbus_otg: pwr_sw1 { +- regulator-name = "vbus_otg"; +- interrupts = ; +- }; +- +- vbus_sw: pwr_sw2 { +- regulator-name = "vbus_sw"; +- interrupts = ; +- regulator-active-discharge = <1>; +- }; +- }; +- +- onkey { +- compatible = "st,stpmic1-onkey"; +- interrupts = , ; +- interrupt-names = "onkey-falling", "onkey-rising"; +- power-off-time-sec = <10>; +- }; +- +- watchdog { +- compatible = "st,stpmic1-wdt"; +- status = "disabled"; +- }; +- }; +-}; +- +-&ipcc { +- status = "okay"; +-}; +- +-&iwdg2 { +- timeout-sec = <32>; +- status = "okay"; +-}; +- +-&m4_rproc { +- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, +- <&vdev0vring1>, <&vdev0buffer>; +- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; +- mbox-names = "vq0", "vq1", "shutdown"; +- interrupt-parent = <&exti>; +- interrupts = <68 1>; +- status = "okay"; +-}; +- +-&rng1 { +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&sdmmc2 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>; +- pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_d>; +- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_d>; +- non-removable; +- no-sd; +- no-sdio; +- st,neg-edge; +- bus-width = <8>; +- vmmc-supply = <&v3v3>; +- vqmmc-supply = <&vdd>; +- mmc-ddr-3_3v; +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp157c-odyssey.dts b/scripts/dtc/include-prefixes/arm/stm32mp157c-odyssey.dts +deleted file mode 100644 +index be1dd5e9e744..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp157c-odyssey.dts ++++ /dev/null +@@ -1,80 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) 2020 Marcin Sloniewski . +- */ +- +-/dts-v1/; +- +-#include "stm32mp157c-odyssey-som.dtsi" +- +-/ { +- model = "Seeed Studio Odyssey-STM32MP157C Board"; +- compatible = "seeed,stm32mp157c-odyssey", +- "seeed,stm32mp157c-odyssey-som", "st,stm32mp157"; +- +- aliases { +- ethernet0 = ðernet0; +- serial0 = &uart4; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-ðernet0 { +- status = "okay"; +- pinctrl-0 = <ðernet0_rgmii_pins_a>; +- pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- phy-mode = "rgmii-id"; +- max-speed = <1000>; +- phy-handle = <&phy0>; +- assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>; +- assigned-clock-parents = <&rcc PLL4_P>; +- assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */ +- st,eth-clk-sel; +- +- mdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy0: ethernet-phy@7 { /* KSZ9031RN */ +- reg = <7>; +- reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */ +- reset-assert-us = <10000>; +- reset-deassert-us = <300>; +- }; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c1_pins_a>; +- pinctrl-1 = <&i2c1_sleep_pins_a>; +- i2c-scl-rising-time-ns = <100>; +- i2c-scl-falling-time-ns = <7>; +- status = "okay"; +- /delete-property/dmas; +- /delete-property/dma-names; +-}; +- +-&sdmmc1 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc1_b4_pins_a>; +- pinctrl-1 = <&sdmmc1_b4_od_pins_a>; +- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; +- cd-gpios = <&gpioi 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; +- disable-wp; +- st,neg-edge; +- bus-width = <4>; +- vmmc-supply = <&v3v3>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pins_a>; +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp15xc.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp15xc.dtsi +deleted file mode 100644 +index b06a55a2fa18..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp15xc.dtsi ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved +- * Author: Alexandre Torgue for STMicroelectronics. +- */ +- +-/ { +- soc { +- cryp1: cryp@54001000 { +- compatible = "st,stm32mp1-cryp"; +- reg = <0x54001000 0x400>; +- interrupts = ; +- clocks = <&rcc CRYP1>; +- resets = <&rcc CRYP1_R>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcom-drc02.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcom-drc02.dtsi +deleted file mode 100644 +index 4b10b013ffd5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcom-drc02.dtsi ++++ /dev/null +@@ -1,165 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +-/* +- * Copyright (C) 2020 Marek Vasut +- */ +- +-#include +-#include +- +-/ { +- aliases { +- serial0 = &uart4; +- serial1 = &usart3; +- serial2 = &uart8; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&adc { +- status = "disabled"; +-}; +- +-&dac { +- status = "disabled"; +-}; +- +-&gpiob { +- /* +- * NOTE: On DRC02, the RS485_RX_En is controlled by a separate +- * GPIO line, however the STM32 UART driver assumes RX happens +- * during TX anyway and that it only controls drive enable DE +- * line. Hence, the RX is always enabled here. +- */ +- rs485-rx-en-hog { +- gpio-hog; +- gpios = <8 0>; +- output-low; +- line-name = "rs485-rx-en"; +- }; +-}; +- +-&gpiod { +- gpio-line-names = "", "", "", "", +- "", "", "DHCOM-B", "", +- "", "", "", "DRC02-Out1", +- "DRC02-Out2", "", "", ""; +-}; +- +-&gpioi { +- gpio-line-names = "DRC02-In1", "DHCOM-O", "DHCOM-H", "DHCOM-I", +- "DHCOM-R", "DHCOM-M", "", "", +- "DRC02-In2", "", "", "", +- "", "", "", ""; +- +- /* +- * NOTE: The USB Hub on the DRC02 needs a reset signal to be +- * pulled high in order to be detected by the USB Controller. +- * This signal should be handled by USB power sequencing in +- * order to reset the Hub when USB bus is powered down, but +- * so far there is no such functionality. +- */ +- usb-hub-hog { +- gpio-hog; +- gpios = <2 0>; +- output-high; +- line-name = "usb-hub-reset"; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c04"; +- reg = <0x50>; +- pagesize = <16>; +- }; +-}; +- +-&i2c4 { +- touchscreen@49 { +- status = "disabled"; +- }; +-}; +- +-&i2c5 { /* TP7/TP8 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +-}; +- +-&sdmmc3 { +- /* +- * On DRC02, the SoM does not have SDIO WiFi. The pins +- * are used for on-board microSD slot instead. +- */ +- /delete-property/broken-cd; +- cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; +- disable-wp; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins_a>; +- cs-gpios = <&gpioz 3 0>; +- /* Use PIO for the display */ +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; /* Enable once there is display driver */ +- /* +- * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are +- * also connected to the display board connector. +- */ +-}; +- +-&usart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usart3_pins_a>; +- status = "okay"; +-}; +- +-/* +- * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1), +- * however the STM32MP1 pinmux cannot map them to UART4 . +- */ +- +-&uart8 { /* RS485 */ +- linux,rs485-enabled-at-boot-time; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart8_pins_a>; +- rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&usbh_ehci { +- phys = <&usbphyc_port0>; +- status = "okay"; +-}; +- +-&usbphyc { +- status = "okay"; +-}; +- +-&usbphyc_port0 { +- phy-supply = <&vdd_usb>; +-}; +- +-&usbphyc_port1 { +- phy-supply = <&vdd_usb>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcom-pdk2.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcom-pdk2.dtsi +deleted file mode 100644 +index fbf3826933e4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcom-pdk2.dtsi ++++ /dev/null +@@ -1,325 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +-/* +- * Copyright (C) 2019-2020 Marek Vasut +- */ +- +-#include +-#include +- +-/ { +- aliases { +- serial0 = &uart4; +- serial1 = &usart3; +- serial2 = &uart8; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- clk_ext_audio_codec: clock-codec { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- }; +- +- display_bl: display-bl { +- compatible = "pwm-backlight"; +- pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>; +- brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; +- default-brightness-level = <8>; +- enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; +- power-supply = <®_panel_bl>; +- status = "okay"; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- poll-interval = <20>; +- +- /* +- * The EXTi IRQ line 3 is shared with ethernet, +- * so mark this as polled GPIO key. +- */ +- button-0 { +- label = "TA1-GPIO-A"; +- linux,code = ; +- gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; +- }; +- +- /* +- * The EXTi IRQ line 6 is shared with touchscreen, +- * so mark this as polled GPIO key. +- */ +- button-1 { +- label = "TA2-GPIO-B"; +- linux,code = ; +- gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; +- }; +- +- /* +- * The EXTi IRQ line 0 is shared with PMIC, +- * so mark this as polled GPIO key. +- */ +- button-2 { +- label = "TA3-GPIO-C"; +- linux,code = ; +- gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- button-3 { +- label = "TA4-GPIO-D"; +- linux,code = ; +- gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; +- wakeup-source; +- }; +- }; +- +- led { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "green:led5"; +- gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- status = "disabled"; +- }; +- +- led-1 { +- label = "green:led6"; +- gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-2 { +- label = "green:led7"; +- gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-3 { +- label = "green:led8"; +- gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- panel { +- compatible = "edt,etm0700g0edh6"; +- backlight = <&display_bl>; +- power-supply = <®_panel_bl>; +- +- port { +- lcd_panel_in: endpoint { +- remote-endpoint = <&lcd_display_out>; +- }; +- }; +- }; +- +- reg_panel_bl: regulator-panel-bl { +- compatible = "regulator-fixed"; +- regulator-name = "panel_backlight"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <®_panel_supply>; +- }; +- +- reg_panel_supply: regulator-panel-supply { +- compatible = "regulator-fixed"; +- regulator-name = "panel_supply"; +- regulator-min-microvolt = <24000000>; +- regulator-max-microvolt = <24000000>; +- }; +- +- sound { +- compatible = "audio-graph-card"; +- routing = +- "MIC_IN", "Capture", +- "Capture", "Mic Bias", +- "Playback", "HP_OUT"; +- dais = <&sai2a_port &sai2b_port>; +- status = "okay"; +- }; +-}; +- +-&cec { +- pinctrl-names = "default"; +- pinctrl-0 = <&cec_pins_a>; +- status = "okay"; +-}; +- +-&i2c2 { /* Header X22 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "okay"; +-}; +- +-&i2c5 { /* Header X21 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- clocks = <&clk_ext_audio_codec>; +- VDDA-supply = <&v3v3>; +- VDDIO-supply = <&vdd>; +- +- sgtl5000_port: port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- sgtl5000_tx_endpoint: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&sai2a_endpoint>; +- frame-master = <&sgtl5000_tx_endpoint>; +- bitclock-master = <&sgtl5000_tx_endpoint>; +- }; +- +- sgtl5000_rx_endpoint: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&sai2b_endpoint>; +- frame-master = <&sgtl5000_rx_endpoint>; +- bitclock-master = <&sgtl5000_rx_endpoint>; +- }; +- }; +- +- }; +- +- touchscreen@38 { +- compatible = "edt,edt-ft5406"; +- reg = <0x38>; +- interrupt-parent = <&gpioc>; +- interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ +- }; +-}; +- +-<dc { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <<dc_pins_b>; +- pinctrl-1 = <<dc_sleep_pins_b>; +- status = "okay"; +- +- port { +- lcd_display_out: endpoint { +- remote-endpoint = <&lcd_panel_in>; +- }; +- }; +-}; +- +-&sai2 { +- clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; +- clock-names = "pclk", "x8k", "x11k"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sai2a_pins_b &sai2b_pins_b>; +- pinctrl-1 = <&sai2a_sleep_pins_b &sai2b_sleep_pins_b>; +- status = "okay"; +- +- sai2a: audio-controller@4400b004 { +- #clock-cells = <0>; +- dma-names = "tx"; +- clocks = <&rcc SAI2_K>; +- clock-names = "sai_ck"; +- status = "okay"; +- +- sai2a_port: port { +- sai2a_endpoint: endpoint { +- remote-endpoint = <&sgtl5000_tx_endpoint>; +- format = "i2s"; +- mclk-fs = <512>; +- dai-tdm-slot-num = <2>; +- dai-tdm-slot-width = <16>; +- }; +- }; +- }; +- +- sai2b: audio-controller@4400b024 { +- dma-names = "rx"; +- st,sync = <&sai2a 2>; +- clocks = <&rcc SAI2_K>, <&sai2a>; +- clock-names = "sai_ck", "MCLK"; +- status = "okay"; +- +- sai2b_port: port { +- sai2b_endpoint: endpoint { +- remote-endpoint = <&sgtl5000_rx_endpoint>; +- format = "i2s"; +- mclk-fs = <512>; +- dai-tdm-slot-num = <2>; +- dai-tdm-slot-width = <16>; +- }; +- }; +- }; +-}; +- +-&timers2 { +- /* spare dmas for other usage (un-delete to enable pwm capture) */ +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "okay"; +- pwm2: pwm { +- pinctrl-0 = <&pwm2_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- timer@1 { +- status = "okay"; +- }; +-}; +- +-&usart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usart3_pins_a>; +- status = "okay"; +-}; +- +-&uart8 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbh_ehci { +- phys = <&usbphyc_port0>; +- status = "okay"; +-}; +- +-&usbotg_hs { +- dr_mode = "otg"; +- pinctrl-0 = <&usbotg_hs_pins_a>; +- pinctrl-names = "default"; +- phy-names = "usb2-phy"; +- phys = <&usbphyc_port1 0>; +- vbus-supply = <&vbus_otg>; +- status = "okay"; +-}; +- +-&usbphyc { +- status = "okay"; +-}; +- +-&usbphyc_port0 { +- phy-supply = <&vdd_usb>; +-}; +- +-&usbphyc_port1 { +- phy-supply = <&vdd_usb>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcom-picoitx.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcom-picoitx.dtsi +deleted file mode 100644 +index ba816ef8b9b2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcom-picoitx.dtsi ++++ /dev/null +@@ -1,147 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +-/* +- * Copyright (C) 2020 Marek Vasut +- */ +- +-#include +-#include +- +-/ { +- aliases { +- serial0 = &uart4; +- serial1 = &usart3; +- serial2 = &uart8; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- led { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "yellow:led"; +- gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +-}; +- +-&adc { +- status = "disabled"; +-}; +- +-&dac { +- status = "disabled"; +-}; +- +-&fmc { +- status = "disabled"; +-}; +- +-&gpioa { +- /* +- * NOTE: The USB Port on the PicoITX needs a PWR_EN signal to enable +- * port power. This signal should be handled by USB power sequencing +- * in order to turn on port power when USB bus is powered up, but so +- * far there is no such functionality. +- */ +- usb-port-power-hog { +- gpio-hog; +- gpios = <13 0>; +- output-low; +- line-name = "usb-port-power"; +- }; +-}; +- +-&gpioc { +- gpio-line-names = "", "", "", "", +- "", "", "PicoITX-In1", "", +- "", "", "", "", +- "", "", "", ""; +-}; +- +-&gpiod { +- gpio-line-names = "", "", "", "", +- "", "", "DHCOM-B", "", +- "", "", "", "PicoITX-Out1", +- "PicoITX-Out2", "", "", ""; +-}; +- +-&gpiog { +- gpio-line-names = "PicoITX-In2", "", "", "", +- "", "", "", "", +- "DHCOM-L", "", "", "", +- "", "", "", ""; +-}; +- +-&i2c2 { /* On board-to-board connector (optional) */ +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +-}; +- +-&i2c5 { /* On board-to-board connector */ +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +-}; +- +-&ksz8851 { +- status = "disabled"; +-}; +- +-&usart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usart3_pins_a>; +- status = "okay"; +-}; +- +-&uart8 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; +- status = "okay"; +-}; +- +-&usbh_ehci { +- phys = <&usbphyc_port0>; +- status = "okay"; +-}; +- +-&usbh_ohci { +- phys = <&usbphyc_port0>; +- status = "okay"; +-}; +- +-&usbotg_hs { +- dr_mode = "otg"; +- pinctrl-0 = <&usbotg_hs_pins_a>; +- pinctrl-names = "default"; +- phy-names = "usb2-phy"; +- phys = <&usbphyc_port1 0>; +- vbus-supply = <&vbus_otg>; +- status = "okay"; +-}; +- +-&usbphyc { +- status = "okay"; +-}; +- +-&usbphyc_port0 { +- phy-supply = <&vdd_usb>; +-}; +- +-&usbphyc_port1 { +- phy-supply = <&vdd_usb>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcom-som.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcom-som.dtsi +deleted file mode 100644 +index 8c41f819f776..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcom-som.dtsi ++++ /dev/null +@@ -1,525 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) 2019-2020 Marek Vasut +- */ +- +-#include "stm32mp15-pinctrl.dtsi" +-#include "stm32mp15xxaa-pinctrl.dtsi" +-#include +-#include +- +-/ { +- aliases { +- ethernet0 = ðernet0; +- ethernet1 = &ksz8851; +- rtc0 = &hwrtc; +- rtc1 = &rtc; +- }; +- +- memory@c0000000 { +- device_type = "memory"; +- reg = <0xC0000000 0x40000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- mcuram2: mcuram2@10000000 { +- compatible = "shared-dma-pool"; +- reg = <0x10000000 0x40000>; +- no-map; +- }; +- +- vdev0vring0: vdev0vring0@10040000 { +- compatible = "shared-dma-pool"; +- reg = <0x10040000 0x1000>; +- no-map; +- }; +- +- vdev0vring1: vdev0vring1@10041000 { +- compatible = "shared-dma-pool"; +- reg = <0x10041000 0x1000>; +- no-map; +- }; +- +- vdev0buffer: vdev0buffer@10042000 { +- compatible = "shared-dma-pool"; +- reg = <0x10042000 0x4000>; +- no-map; +- }; +- +- mcuram: mcuram@30000000 { +- compatible = "shared-dma-pool"; +- reg = <0x30000000 0x40000>; +- no-map; +- }; +- +- retram: retram@38000000 { +- compatible = "shared-dma-pool"; +- reg = <0x38000000 0x10000>; +- no-map; +- }; +- }; +- +- ethernet_vio: vioregulator { +- compatible = "regulator-fixed"; +- regulator-name = "vio"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd>; +- }; +-}; +- +-&adc { +- vdd-supply = <&vdd>; +- vdda-supply = <&vdda>; +- vref-supply = <&vdda>; +- status = "okay"; +- +- adc1: adc@0 { +- st,min-sample-time-nsecs = <5000>; +- st,adc-channels = <0>; +- status = "okay"; +- }; +- +- adc2: adc@100 { +- st,adc-channels = <1>; +- st,min-sample-time-nsecs = <5000>; +- status = "okay"; +- }; +-}; +- +-&crc1 { +- status = "okay"; +-}; +- +-&dac { +- pinctrl-names = "default"; +- pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; +- vref-supply = <&vdda>; +- status = "okay"; +- +- dac1: dac@1 { +- status = "okay"; +- }; +- dac2: dac@2 { +- status = "okay"; +- }; +-}; +- +-&dts { +- status = "okay"; +-}; +- +-ðernet0 { +- status = "okay"; +- pinctrl-0 = <ðernet0_rmii_pins_a>; +- pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- phy-mode = "rmii"; +- max-speed = <100>; +- phy-handle = <&phy0>; +- st,eth-ref-clk-sel; +- +- mdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- +- phy0: ethernet-phy@1 { +- reg = <1>; +- /* LAN8710Ai */ +- compatible = "ethernet-phy-id0007.c0f0", +- "ethernet-phy-ieee802.3-c22"; +- clocks = <&rcc ETHCK_K>; +- reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; +- reset-assert-us = <500>; +- reset-deassert-us = <500>; +- smsc,disable-energy-detect; +- interrupt-parent = <&gpioi>; +- interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +-}; +- +-&fmc { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&fmc_pins_b>; +- pinctrl-1 = <&fmc_sleep_pins_b>; +- status = "okay"; +- +- ksz8851: ethernet@1,0 { +- compatible = "micrel,ks8851-mll"; +- reg = <1 0x0 0x2>, <1 0x2 0x20000>; +- interrupt-parent = <&gpioc>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- bank-width = <2>; +- +- /* Timing values are in nS */ +- st,fmc2-ebi-cs-mux-enable; +- st,fmc2-ebi-cs-transaction-type = <4>; +- st,fmc2-ebi-cs-buswidth = <16>; +- st,fmc2-ebi-cs-address-setup-ns = <5>; +- st,fmc2-ebi-cs-address-hold-ns = <5>; +- st,fmc2-ebi-cs-bus-turnaround-ns = <5>; +- st,fmc2-ebi-cs-data-setup-ns = <45>; +- st,fmc2-ebi-cs-data-hold-ns = <1>; +- st,fmc2-ebi-cs-write-address-setup-ns = <5>; +- st,fmc2-ebi-cs-write-address-hold-ns = <5>; +- st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>; +- st,fmc2-ebi-cs-write-data-setup-ns = <45>; +- st,fmc2-ebi-cs-write-data-hold-ns = <1>; +- }; +-}; +- +-&gpioa { +- gpio-line-names = "", "", "", "", +- "", "", "DHCOM-K", "", +- "", "", "", "", +- "", "", "", ""; +-}; +- +-&gpiob { +- gpio-line-names = "", "", "", "", +- "", "", "", "", +- "DHCOM-Q", "", "", "", +- "", "", "", ""; +-}; +- +-&gpioc { +- gpio-line-names = "", "", "", "", +- "", "", "DHCOM-E", "", +- "", "", "", "", +- "", "", "", ""; +- status = "okay"; +-}; +- +-&gpiod { +- gpio-line-names = "", "", "", "", +- "", "", "DHCOM-B", "", +- "", "", "", "DHCOM-F", +- "DHCOM-D", "", "", ""; +-}; +- +-&gpioe { +- gpio-line-names = "", "", "", "", +- "", "", "DHCOM-P", "", +- "", "", "", "", +- "", "", "", ""; +-}; +- +-&gpiof { +- gpio-line-names = "", "", "", "DHCOM-A", +- "", "", "", "", +- "", "", "", "", +- "", "", "", ""; +-}; +- +-&gpiog { +- gpio-line-names = "DHCOM-C", "", "", "", +- "", "", "", "", +- "DHCOM-L", "", "", "", +- "", "", "", ""; +-}; +- +-&gpioh { +- gpio-line-names = "", "", "", "", +- "", "", "", "DHCOM-N", +- "DHCOM-J", "DHCOM-W", "DHCOM-V", "DHCOM-U", +- "DHCOM-T", "", "DHCOM-S", ""; +-}; +- +-&gpioi { +- gpio-line-names = "DHCOM-G", "DHCOM-O", "DHCOM-H", "DHCOM-I", +- "DHCOM-R", "DHCOM-M", "", "", +- "", "", "", "", +- "", "", "", ""; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +- +- hwrtc: rtc@32 { +- compatible = "microcrystal,rv8803"; +- reg = <0x32>; +- }; +- +- pmic: stpmic@33 { +- compatible = "st,stpmic1"; +- reg = <0x33>; +- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "okay"; +- +- regulators { +- compatible = "st,stpmic1-regulators"; +- ldo1-supply = <&v3v3>; +- ldo2-supply = <&v3v3>; +- ldo3-supply = <&vdd_ddr>; +- ldo5-supply = <&v3v3>; +- ldo6-supply = <&v3v3>; +- pwr_sw1-supply = <&bst_out>; +- pwr_sw2-supply = <&bst_out>; +- +- vddcore: buck1 { +- regulator-name = "vddcore"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- vdd_ddr: buck2 { +- regulator-name = "vdd_ddr"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- vdd: buck3 { +- regulator-name = "vdd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- st,mask-reset; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- v3v3: buck4 { +- regulator-name = "v3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-over-current-protection; +- regulator-initial-mode = <0>; +- }; +- +- vdda: ldo1 { +- regulator-name = "vdda"; +- regulator-always-on; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- interrupts = ; +- }; +- +- v2v8: ldo2 { +- regulator-name = "v2v8"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- interrupts = ; +- }; +- +- vtt_ddr: ldo3 { +- regulator-name = "vtt_ddr"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <750000>; +- regulator-always-on; +- regulator-over-current-protection; +- }; +- +- vdd_usb: ldo4 { +- regulator-name = "vdd_usb"; +- interrupts = ; +- }; +- +- vdd_sd: ldo5 { +- regulator-name = "vdd_sd"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- interrupts = ; +- regulator-boot-on; +- }; +- +- v1v8: ldo6 { +- regulator-name = "v1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- interrupts = ; +- }; +- +- vref_ddr: vref_ddr { +- regulator-name = "vref_ddr"; +- regulator-always-on; +- }; +- +- bst_out: boost { +- regulator-name = "bst_out"; +- interrupts = ; +- }; +- +- vbus_otg: pwr_sw1 { +- regulator-name = "vbus_otg"; +- interrupts = ; +- }; +- +- vbus_sw: pwr_sw2 { +- regulator-name = "vbus_sw"; +- interrupts = ; +- regulator-active-discharge = <1>; +- }; +- }; +- +- onkey { +- compatible = "st,stpmic1-onkey"; +- interrupts = , ; +- interrupt-names = "onkey-falling", "onkey-rising"; +- power-off-time-sec = <10>; +- status = "okay"; +- }; +- +- watchdog { +- compatible = "st,stpmic1-wdt"; +- status = "disabled"; +- }; +- }; +- +- touchscreen@49 { +- compatible = "ti,tsc2004"; +- reg = <0x49>; +- vio-supply = <&v3v3>; +- interrupts-extended = <&gpioh 15 IRQ_TYPE_EDGE_FALLING>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +-}; +- +-&ipcc { +- status = "okay"; +-}; +- +-&iwdg2 { +- timeout-sec = <32>; +- status = "okay"; +-}; +- +-&m4_rproc { +- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, +- <&vdev0vring1>, <&vdev0buffer>; +- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; +- mbox-names = "vq0", "vq1", "shutdown"; +- interrupt-parent = <&exti>; +- interrupts = <68 1>; +- status = "okay"; +-}; +- +-&pwr_regulators { +- vdd-supply = <&vdd>; +- vdd_3v3_usbfs-supply = <&vdd_usb>; +-}; +- +-&qspi { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; +- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; +- reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- flash0: flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-rx-bus-width = <4>; +- spi-max-frequency = <108000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&rng1 { +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&sdmmc1 { +- pinctrl-names = "default", "opendrain", "sleep", "init"; +- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; +- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; +- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; +- pinctrl-3 = <&sdmmc1_b4_init_pins_a &sdmmc1_dir_init_pins_a>; +- cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; +- disable-wp; +- st,sig-dir; +- st,neg-edge; +- st,use-ckin; +- st,cmd-gpios = <&gpiod 2 0>; +- st,ck-gpios = <&gpioc 12 0>; +- st,ckin-gpios = <&gpioe 4 0>; +- bus-width = <4>; +- vmmc-supply = <&vdd_sd>; +- status = "okay"; +-}; +- +-&sdmmc1_b4_pins_a { +- /* +- * SD bus pull-up resistors: +- * - optional on SoMs with SD voltage translator +- * - mandatory on SoMs without SD voltage translator +- */ +- pins1 { +- bias-pull-up; +- }; +- pins2 { +- bias-pull-up; +- }; +-}; +- +-&sdmmc2 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; +- pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; +- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; +- non-removable; +- no-sd; +- no-sdio; +- st,neg-edge; +- bus-width = <8>; +- vmmc-supply = <&v3v3>; +- vqmmc-supply = <&v3v3>; +- mmc-ddr-3_3v; +- status = "okay"; +-}; +- +-&sdmmc3 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc3_b4_pins_a>; +- pinctrl-1 = <&sdmmc3_b4_od_pins_a>; +- pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; +- broken-cd; +- st,neg-edge; +- bus-width = <4>; +- vmmc-supply = <&v3v3>; +- vqmmc-supply = <&v3v3>; +- mmc-ddr-3_3v; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pins_a>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcor-avenger96.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcor-avenger96.dtsi +deleted file mode 100644 +index 6885948f3024..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcor-avenger96.dtsi ++++ /dev/null +@@ -1,431 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +-/* +- * Copyright (C) Linaro Ltd 2019 - All Rights Reserved +- * Author: Manivannan Sadhasivam +- * Copyright (C) 2020 Marek Vasut +- */ +- +-/* Avenger96 uses DHCOR SoM configured for 1V8 IO operation */ +-#include "stm32mp15xx-dhcor-io1v8.dtsi" +- +-/ { +- aliases { +- ethernet0 = ðernet0; +- mmc0 = &sdmmc1; +- serial0 = &uart4; +- serial1 = &uart7; +- serial2 = &usart2; +- spi0 = &qspi; +- }; +- +- /* XTal Q1 */ +- cec_clock: clk-cec-fixed { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con: endpoint { +- remote-endpoint = <&adv7513_out>; +- }; +- }; +- }; +- +- led { +- compatible = "gpio-leds"; +- led1 { +- label = "green:user0"; +- gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- +- led2 { +- label = "green:user1"; +- gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- +- led3 { +- label = "green:user2"; +- gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc1"; +- default-state = "off"; +- }; +- +- led4 { +- label = "green:user3"; +- gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "none"; +- default-state = "off"; +- panic-indicator; +- }; +- }; +- +- sd_switch: regulator-sd_switch { +- compatible = "regulator-gpio"; +- regulator-name = "sd_switch"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2900000>; +- regulator-type = "voltage"; +- regulator-always-on; +- +- gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; +- gpios-states = <0>; +- states = <1800000 0x1>, +- <2900000 0x0>; +- }; +- +- sound { +- compatible = "audio-graph-card"; +- label = "STM32MP1-AV96-HDMI"; +- dais = <&sai2a_port>; +- status = "okay"; +- }; +- +- wlan_pwr: regulator-wlan { +- compatible = "regulator-fixed"; +- +- regulator-name = "wl-reg"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&adc { +- pinctrl-names = "default"; +- pinctrl-0 = <&adc12_ain_pins_b>; +- vdd-supply = <&vdd>; +- vdda-supply = <&vdda>; +- vref-supply = <&vdda>; +- status = "okay"; +- +- adc1: adc@0 { +- st,adc-channels = <0 1 6>; +- st,min-sample-time-nsecs = <5000>; +- status = "okay"; +- }; +- +- adc2: adc@100 { +- st,adc-channels = <0 1 2>; +- st,min-sample-time-nsecs = <5000>; +- status = "okay"; +- }; +-}; +- +-ðernet0 { +- status = "okay"; +- pinctrl-0 = <ðernet0_rgmii_pins_c>; +- pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; +- pinctrl-names = "default", "sleep"; +- phy-mode = "rgmii"; +- max-speed = <1000>; +- phy-handle = <&phy0>; +- +- mdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; +- reset-delay-us = <1000>; +- +- phy0: ethernet-phy@7 { +- reg = <7>; +- +- rxc-skew-ps = <1500>; +- rxdv-skew-ps = <540>; +- rxd0-skew-ps = <420>; +- rxd1-skew-ps = <420>; +- rxd2-skew-ps = <420>; +- rxd3-skew-ps = <420>; +- +- txc-skew-ps = <1440>; +- txen-skew-ps = <540>; +- txd0-skew-ps = <420>; +- txd1-skew-ps = <420>; +- txd2-skew-ps = <420>; +- txd3-skew-ps = <420>; +- }; +- }; +-}; +- +-&gpioa { +- gpio-line-names = "", "", "", "", +- "", "", "", "", +- "", "", "", "AV96-K", +- "AV96-I", "", "AV96-A", ""; +-}; +- +-&gpiob { +- gpio-line-names = "", "", "", "", +- "", "AV96-J", "", "", +- "", "", "", "AV96-B", +- "", "AV96-L", "", ""; +-}; +- +-&gpioc { +- gpio-line-names = "", "", "", "AV96-C", +- "", "", "", "", +- "", "", "", "", +- "", "", "", ""; +-}; +- +-&gpiod { +- gpio-line-names = "", "", "", "", +- "", "", "", "", +- "AV96-D", "", "", "", +- "", "", "AV96-E", "AV96-F"; +-}; +- +-&gpiof { +- gpio-line-names = "", "", "", "", +- "", "", "", "", +- "", "", "", "", +- "AV96-G", "AV96-H", "", ""; +-}; +- +-&i2c1 { /* X6 I2C1 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins_b>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- /delete-property/dmas; +- /delete-property/dma-names; +-}; +- +-&i2c2 { /* X6 I2C2 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins_c>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- /delete-property/dmas; +- /delete-property/dma-names; +-}; +- +-&i2c4 { +- hdmi-transmitter@3d { +- compatible = "adi,adv7513"; +- reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>; +- reg-names = "main", "edid", "cec", "packet"; +- clocks = <&cec_clock>; +- clock-names = "cec"; +- +- avdd-supply = <&v3v3>; +- dvdd-supply = <&v3v3>; +- pvdd-supply = <&v3v3>; +- dvdd-3v-supply = <&v3v3>; +- bgvdd-supply = <&v3v3>; +- +- interrupts = <9 IRQ_TYPE_EDGE_FALLING>; +- interrupt-parent = <&gpiog>; +- +- status = "okay"; +- +- adi,input-depth = <8>; +- adi,input-colorspace = "rgb"; +- adi,input-clock = "1x"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7513_in: endpoint { +- remote-endpoint = <<dc_ep0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- adv7513_out: endpoint { +- remote-endpoint = <&hdmi_con>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- adv7513_i2s0: endpoint { +- remote-endpoint = <&sai2a_endpoint>; +- }; +- }; +- }; +- }; +-}; +- +-<dc { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <<dc_pins_d>; +- pinctrl-1 = <<dc_sleep_pins_d>; +- status = "okay"; +- +- port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ltdc_ep0_out: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&adv7513_in>; +- }; +- }; +-}; +- +-&sai2 { +- clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sai2a_pins_c>; +- pinctrl-1 = <&sai2a_sleep_pins_c>; +- clock-names = "pclk", "x8k", "x11k"; +- status = "okay"; +- +- sai2a: audio-controller@4400b004 { +- #clock-cells = <0>; +- dma-names = "tx"; +- clocks = <&rcc SAI2_K>; +- clock-names = "sai_ck"; +- status = "okay"; +- +- sai2a_port: port { +- sai2a_endpoint: endpoint { +- remote-endpoint = <&adv7513_i2s0>; +- format = "i2s"; +- mclk-fs = <256>; +- }; +- }; +- }; +-}; +- +-&sdmmc1 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; +- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; +- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; +- cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; +- disable-wp; +- st,sig-dir; +- st,neg-edge; +- st,use-ckin; +- bus-width = <4>; +- vmmc-supply = <&vdd_sd>; +- vqmmc-supply = <&sd_switch>; +- status = "okay"; +-}; +- +-&sdmmc2 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; +- pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; +- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; +- bus-width = <8>; +- mmc-ddr-1_8v; +- no-sd; +- no-sdio; +- non-removable; +- st,neg-edge; +- vmmc-supply = <&v3v3>; +- vqmmc-supply = <&vdd_io>; +- status = "okay"; +-}; +- +-&sdmmc3 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc3_b4_pins_b>; +- pinctrl-1 = <&sdmmc3_b4_od_pins_b>; +- pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>; +- broken-cd; +- non-removable; +- st,neg-edge; +- bus-width = <4>; +- vmmc-supply = <&wlan_pwr>; +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- brcmf: bcrmf@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-&spi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pins_a>; +- cs-gpios = <&gpioi 0 0>; +- status = "disabled"; +- /delete-property/dmas; +- /delete-property/dma-names; +-}; +- +-&uart4 { +- /* On Low speed expansion header */ +- label = "LS-UART1"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pins_b>; +- status = "okay"; +-}; +- +-&uart7 { +- /* On Low speed expansion header */ +- label = "LS-UART0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart7_pins_a>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-/* Bluetooth */ +-&usart2 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&usart2_pins_a>; +- pinctrl-1 = <&usart2_sleep_pins_a>; +- st,hw-flow-ctrl; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- max-speed = <3000000>; +- shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&usbh_ehci { +- phys = <&usbphyc_port0>; +- phy-names = "usb"; +- status = "okay"; +-}; +- +-&usbotg_hs { +- pinctrl-0 = <&usbotg_hs_pins_a>; +- pinctrl-names = "default"; +- phy-names = "usb2-phy"; +- phys = <&usbphyc_port1 0>; +- status = "okay"; +- vbus-supply = <&vbus_otg>; +-}; +- +-&usbphyc { +- status = "okay"; +-}; +- +-&usbphyc_port0 { +- phy-supply = <&vdd_usb>; +-}; +- +-&usbphyc_port1 { +- phy-supply = <&vdd_usb>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcor-io1v8.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcor-io1v8.dtsi +deleted file mode 100644 +index 75172314d7af..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcor-io1v8.dtsi ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +-/* +- * Copyright (C) Linaro Ltd 2019 - All Rights Reserved +- * Author: Manivannan Sadhasivam +- * Copyright (C) 2020 Marek Vasut +- */ +- +-/ { +- /* Enpirion EP3A8LQI U2 on the DHCOR */ +- vdd_io: regulator-buck-io { +- compatible = "regulator-fixed"; +- regulator-name = "buck-io"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd>; +- }; +-}; +- +-&pwr_regulators { +- vdd-supply = <&vdd_io>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcor-som.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcor-som.dtsi +deleted file mode 100644 +index 44ecc4708587..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp15xx-dhcor-som.dtsi ++++ /dev/null +@@ -1,217 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +-/* +- * Copyright (C) Linaro Ltd 2019 - All Rights Reserved +- * Author: Manivannan Sadhasivam +- * Copyright (C) 2020 Marek Vasut +- */ +- +-#include "stm32mp15-pinctrl.dtsi" +-#include "stm32mp15xxac-pinctrl.dtsi" +-#include +-#include +- +-/ { +- aliases { +- spi0 = &qspi; +- }; +- +- memory@c0000000 { +- device_type = "memory"; +- reg = <0xc0000000 0x40000000>; +- }; +-}; +- +-&crc1 { +- status = "okay"; +-}; +- +-&dts { +- status = "okay"; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- /delete-property/dmas; +- /delete-property/dma-names; +- +- pmic: stpmic@33 { +- compatible = "st,stpmic1"; +- reg = <0x33>; +- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "okay"; +- +- regulators { +- compatible = "st,stpmic1-regulators"; +- +- ldo1-supply = <&v3v3>; +- ldo2-supply = <&v3v3>; +- ldo3-supply = <&vdd_ddr>; +- ldo5-supply = <&v3v3>; +- ldo6-supply = <&v3v3>; +- pwr_sw1-supply = <&bst_out>; +- pwr_sw2-supply = <&bst_out>; +- +- vddcore: buck1 { +- regulator-name = "vddcore"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- vdd_ddr: buck2 { +- regulator-name = "vdd_ddr"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- vdd: buck3 { +- regulator-name = "vdd"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- regulator-always-on; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- v3v3: buck4 { +- regulator-name = "v3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-over-current-protection; +- regulator-initial-mode = <0>; +- }; +- +- vdda: ldo1 { +- regulator-name = "vdda"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- interrupts = ; +- }; +- +- v2v8: ldo2 { +- regulator-name = "v2v8"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- interrupts = ; +- }; +- +- vtt_ddr: ldo3 { +- regulator-name = "vtt_ddr"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <750000>; +- regulator-always-on; +- regulator-over-current-protection; +- }; +- +- vdd_usb: ldo4 { +- regulator-name = "vdd_usb"; +- interrupts = ; +- }; +- +- vdd_sd: ldo5 { +- regulator-name = "vdd_sd"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- interrupts = ; +- regulator-boot-on; +- }; +- +- v1v8: ldo6 { +- regulator-name = "v1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- interrupts = ; +- regulator-enable-ramp-delay = <300000>; +- }; +- +- vref_ddr: vref_ddr { +- regulator-name = "vref_ddr"; +- regulator-always-on; +- }; +- +- bst_out: boost { +- regulator-name = "bst_out"; +- interrupts = ; +- }; +- +- vbus_otg: pwr_sw1 { +- regulator-name = "vbus_otg"; +- interrupts = ; +- regulator-active-discharge = <1>; +- }; +- +- vbus_sw: pwr_sw2 { +- regulator-name = "vbus_sw"; +- interrupts = ; +- regulator-active-discharge = <1>; +- }; +- }; +- +- onkey { +- compatible = "st,stpmic1-onkey"; +- interrupts = , ; +- interrupt-names = "onkey-falling", "onkey-rising"; +- status = "okay"; +- }; +- +- watchdog { +- compatible = "st,stpmic1-wdt"; +- status = "disabled"; +- }; +- }; +- +- eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +-}; +- +-&iwdg2 { +- timeout-sec = <32>; +- status = "okay"; +-}; +- +-&pwr_regulators { +- vdd-supply = <&vdd>; +- vdd_3v3_usbfs-supply = <&vdd_usb>; +-}; +- +-&qspi { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; +- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; +- reg = <0x58003000 0x1000>, <0x70000000 0x200000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- flash0: flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-rx-bus-width = <4>; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&rng1 { +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp15xx-dkx.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp15xx-dkx.dtsi +deleted file mode 100644 +index 48beed0f1f30..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp15xx-dkx.dtsi ++++ /dev/null +@@ -1,708 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved +- * Author: Alexandre Torgue for STMicroelectronics. +- */ +- +-#include +-#include +- +-/ { +- memory@c0000000 { +- device_type = "memory"; +- reg = <0xc0000000 0x20000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- mcuram2: mcuram2@10000000 { +- compatible = "shared-dma-pool"; +- reg = <0x10000000 0x40000>; +- no-map; +- }; +- +- vdev0vring0: vdev0vring0@10040000 { +- compatible = "shared-dma-pool"; +- reg = <0x10040000 0x1000>; +- no-map; +- }; +- +- vdev0vring1: vdev0vring1@10041000 { +- compatible = "shared-dma-pool"; +- reg = <0x10041000 0x1000>; +- no-map; +- }; +- +- vdev0buffer: vdev0buffer@10042000 { +- compatible = "shared-dma-pool"; +- reg = <0x10042000 0x4000>; +- no-map; +- }; +- +- mcuram: mcuram@30000000 { +- compatible = "shared-dma-pool"; +- reg = <0x30000000 0x40000>; +- no-map; +- }; +- +- retram: retram@38000000 { +- compatible = "shared-dma-pool"; +- reg = <0x38000000 0x10000>; +- no-map; +- }; +- +- gpu_reserved: gpu@d4000000 { +- reg = <0xd4000000 0x4000000>; +- no-map; +- }; +- }; +- +- led { +- compatible = "gpio-leds"; +- led-blue { +- label = "heartbeat"; +- gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- }; +- +- sound { +- compatible = "audio-graph-card"; +- label = "STM32MP1-DK"; +- routing = +- "Playback" , "MCLK", +- "Capture" , "MCLK", +- "MICL" , "Mic Bias"; +- dais = <&sai2a_port &sai2b_port &i2s2_port>; +- status = "okay"; +- }; +- +- vin: vin { +- compatible = "regulator-fixed"; +- regulator-name = "vin"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +-}; +- +-&adc { +- pinctrl-names = "default"; +- pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>; +- vdd-supply = <&vdd>; +- vdda-supply = <&vdd>; +- vref-supply = <&vrefbuf>; +- status = "disabled"; +- adc1: adc@0 { +- /* +- * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19. +- * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: +- * 5 * (56 + 47kOhms) * 5pF => 2.5us. +- * Use arbitrary margin here (e.g. 5us). +- */ +- st,min-sample-time-nsecs = <5000>; +- /* AIN connector, USB Type-C CC1 & CC2 */ +- st,adc-channels = <0 1 6 13 18 19>; +- status = "okay"; +- }; +- adc2: adc@100 { +- /* AIN connector, USB Type-C CC1 & CC2 */ +- st,adc-channels = <0 1 2 6 18 19>; +- st,min-sample-time-nsecs = <5000>; +- status = "okay"; +- }; +-}; +- +-&cec { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&cec_pins_b>; +- pinctrl-1 = <&cec_sleep_pins_b>; +- status = "okay"; +-}; +- +-&crc1 { +- status = "okay"; +-}; +- +-&dts { +- status = "okay"; +-}; +- +-ðernet0 { +- status = "okay"; +- pinctrl-0 = <ðernet0_rgmii_pins_a>; +- pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- phy-mode = "rgmii-id"; +- max-speed = <1000>; +- phy-handle = <&phy0>; +- +- mdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +-}; +- +-&gpu { +- contiguous-area = <&gpu_reserved>; +-}; +- +-&hash1 { +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c1_pins_a>; +- pinctrl-1 = <&i2c1_sleep_pins_a>; +- i2c-scl-rising-time-ns = <100>; +- i2c-scl-falling-time-ns = <7>; +- status = "okay"; +- /delete-property/dmas; +- /delete-property/dma-names; +- +- hdmi-transmitter@39 { +- compatible = "sil,sii9022"; +- reg = <0x39>; +- iovcc-supply = <&v3v3_hdmi>; +- cvcc12-supply = <&v1v2_hdmi>; +- reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>; +- interrupts = <1 IRQ_TYPE_EDGE_FALLING>; +- interrupt-parent = <&gpiog>; +- #sound-dai-cells = <0>; +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- sii9022_in: endpoint { +- remote-endpoint = <<dc_ep0_out>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- sii9022_tx_endpoint: endpoint { +- remote-endpoint = <&i2s2_endpoint>; +- }; +- }; +- }; +- }; +- +- cs42l51: cs42l51@4a { +- compatible = "cirrus,cs42l51"; +- reg = <0x4a>; +- #sound-dai-cells = <0>; +- VL-supply = <&v3v3>; +- VD-supply = <&v1v8_audio>; +- VA-supply = <&v1v8_audio>; +- VAHP-supply = <&v1v8_audio>; +- reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>; +- clocks = <&sai2a>; +- clock-names = "MCLK"; +- status = "okay"; +- +- cs42l51_port: port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cs42l51_tx_endpoint: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&sai2a_endpoint>; +- frame-master = <&cs42l51_tx_endpoint>; +- bitclock-master = <&cs42l51_tx_endpoint>; +- }; +- +- cs42l51_rx_endpoint: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&sai2b_endpoint>; +- frame-master = <&cs42l51_rx_endpoint>; +- bitclock-master = <&cs42l51_rx_endpoint>; +- }; +- }; +- }; +-}; +- +-&i2c4 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c4_pins_a>; +- pinctrl-1 = <&i2c4_sleep_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- clock-frequency = <400000>; +- status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +- +- stusb1600@28 { +- compatible = "st,stusb1600"; +- reg = <0x28>; +- interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +- interrupt-parent = <&gpioi>; +- pinctrl-names = "default"; +- pinctrl-0 = <&stusb1600_pins_a>; +- status = "okay"; +- vdd-supply = <&vin>; +- +- connector { +- compatible = "usb-c-connector"; +- label = "USB-C"; +- power-role = "dual"; +- typec-power-opmode = "default"; +- +- port { +- con_usbotg_hs_ep: endpoint { +- remote-endpoint = <&usbotg_hs_ep>; +- }; +- }; +- }; +- }; +- +- pmic: stpmic@33 { +- compatible = "st,stpmic1"; +- reg = <0x33>; +- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "okay"; +- +- regulators { +- compatible = "st,stpmic1-regulators"; +- buck1-supply = <&vin>; +- buck2-supply = <&vin>; +- buck3-supply = <&vin>; +- buck4-supply = <&vin>; +- ldo1-supply = <&v3v3>; +- ldo2-supply = <&vin>; +- ldo3-supply = <&vdd_ddr>; +- ldo4-supply = <&vin>; +- ldo5-supply = <&vin>; +- ldo6-supply = <&v3v3>; +- vref_ddr-supply = <&vin>; +- boost-supply = <&vin>; +- pwr_sw1-supply = <&bst_out>; +- pwr_sw2-supply = <&bst_out>; +- +- vddcore: buck1 { +- regulator-name = "vddcore"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- vdd_ddr: buck2 { +- regulator-name = "vdd_ddr"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- vdd: buck3 { +- regulator-name = "vdd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- st,mask-reset; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- v3v3: buck4 { +- regulator-name = "v3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-over-current-protection; +- regulator-initial-mode = <0>; +- }; +- +- v1v8_audio: ldo1 { +- regulator-name = "v1v8_audio"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- interrupts = ; +- }; +- +- v3v3_hdmi: ldo2 { +- regulator-name = "v3v3_hdmi"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- interrupts = ; +- }; +- +- vtt_ddr: ldo3 { +- regulator-name = "vtt_ddr"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <750000>; +- regulator-always-on; +- regulator-over-current-protection; +- }; +- +- vdd_usb: ldo4 { +- regulator-name = "vdd_usb"; +- interrupts = ; +- }; +- +- vdda: ldo5 { +- regulator-name = "vdda"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- interrupts = ; +- regulator-boot-on; +- }; +- +- v1v2_hdmi: ldo6 { +- regulator-name = "v1v2_hdmi"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- interrupts = ; +- }; +- +- vref_ddr: vref_ddr { +- regulator-name = "vref_ddr"; +- regulator-always-on; +- }; +- +- bst_out: boost { +- regulator-name = "bst_out"; +- interrupts = ; +- }; +- +- vbus_otg: pwr_sw1 { +- regulator-name = "vbus_otg"; +- interrupts = ; +- }; +- +- vbus_sw: pwr_sw2 { +- regulator-name = "vbus_sw"; +- interrupts = ; +- regulator-active-discharge = <1>; +- }; +- }; +- +- onkey { +- compatible = "st,stpmic1-onkey"; +- interrupts = , ; +- interrupt-names = "onkey-falling", "onkey-rising"; +- power-off-time-sec = <10>; +- status = "okay"; +- }; +- +- watchdog { +- compatible = "st,stpmic1-wdt"; +- status = "disabled"; +- }; +- }; +-}; +- +-&i2c5 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c5_pins_a>; +- pinctrl-1 = <&i2c5_sleep_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- clock-frequency = <400000>; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +-}; +- +-&i2s2 { +- clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; +- clock-names = "pclk", "i2sclk", "x8k", "x11k"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2s2_pins_a>; +- pinctrl-1 = <&i2s2_sleep_pins_a>; +- status = "okay"; +- +- i2s2_port: port { +- i2s2_endpoint: endpoint { +- remote-endpoint = <&sii9022_tx_endpoint>; +- format = "i2s"; +- mclk-fs = <256>; +- }; +- }; +-}; +- +-&ipcc { +- status = "okay"; +-}; +- +-&iwdg2 { +- timeout-sec = <32>; +- status = "okay"; +-}; +- +-<dc { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <<dc_pins_a>; +- pinctrl-1 = <<dc_sleep_pins_a>; +- status = "okay"; +- +- port { +- ltdc_ep0_out: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&sii9022_in>; +- }; +- }; +-}; +- +-&m4_rproc { +- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, +- <&vdev0vring1>, <&vdev0buffer>; +- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; +- mbox-names = "vq0", "vq1", "shutdown", "detach"; +- interrupt-parent = <&exti>; +- interrupts = <68 1>; +- status = "okay"; +-}; +- +-&pwr_regulators { +- vdd-supply = <&vdd>; +- vdd_3v3_usbfs-supply = <&vdd_usb>; +-}; +- +-&rng1 { +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&sai2 { +- clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; +- clock-names = "pclk", "x8k", "x11k"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>; +- pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>; +- status = "okay"; +- +- sai2a: audio-controller@4400b004 { +- #clock-cells = <0>; +- dma-names = "tx"; +- clocks = <&rcc SAI2_K>; +- clock-names = "sai_ck"; +- status = "okay"; +- +- sai2a_port: port { +- sai2a_endpoint: endpoint { +- remote-endpoint = <&cs42l51_tx_endpoint>; +- format = "i2s"; +- mclk-fs = <256>; +- dai-tdm-slot-num = <2>; +- dai-tdm-slot-width = <32>; +- }; +- }; +- }; +- +- sai2b: audio-controller@4400b024 { +- dma-names = "rx"; +- st,sync = <&sai2a 2>; +- clocks = <&rcc SAI2_K>, <&sai2a>; +- clock-names = "sai_ck", "MCLK"; +- status = "okay"; +- +- sai2b_port: port { +- sai2b_endpoint: endpoint { +- remote-endpoint = <&cs42l51_rx_endpoint>; +- format = "i2s"; +- mclk-fs = <256>; +- dai-tdm-slot-num = <2>; +- dai-tdm-slot-width = <32>; +- }; +- }; +- }; +-}; +- +-&sdmmc1 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc1_b4_pins_a>; +- pinctrl-1 = <&sdmmc1_b4_od_pins_a>; +- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; +- cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; +- disable-wp; +- st,neg-edge; +- bus-width = <4>; +- vmmc-supply = <&v3v3>; +- status = "okay"; +-}; +- +-&sdmmc3 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc3_b4_pins_a>; +- pinctrl-1 = <&sdmmc3_b4_od_pins_a>; +- pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; +- broken-cd; +- st,neg-edge; +- bus-width = <4>; +- vmmc-supply = <&v3v3>; +- status = "disabled"; +-}; +- +-&timers1 { +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +- pwm { +- pinctrl-0 = <&pwm1_pins_a>; +- pinctrl-1 = <&pwm1_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- status = "okay"; +- }; +- timer@0 { +- status = "okay"; +- }; +-}; +- +-&timers3 { +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +- pwm { +- pinctrl-0 = <&pwm3_pins_a>; +- pinctrl-1 = <&pwm3_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- status = "okay"; +- }; +- timer@2 { +- status = "okay"; +- }; +-}; +- +-&timers4 { +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +- pwm { +- pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>; +- pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>; +- pinctrl-names = "default", "sleep"; +- status = "okay"; +- }; +- timer@3 { +- status = "okay"; +- }; +-}; +- +-&timers5 { +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +- pwm { +- pinctrl-0 = <&pwm5_pins_a>; +- pinctrl-1 = <&pwm5_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- status = "okay"; +- }; +- timer@4 { +- status = "okay"; +- }; +-}; +- +-&timers6 { +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +- timer@5 { +- status = "okay"; +- }; +-}; +- +-&timers12 { +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +- pwm { +- pinctrl-0 = <&pwm12_pins_a>; +- pinctrl-1 = <&pwm12_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- status = "okay"; +- }; +- timer@11 { +- status = "okay"; +- }; +-}; +- +-&uart4 { +- pinctrl-names = "default", "sleep", "idle"; +- pinctrl-0 = <&uart4_pins_a>; +- pinctrl-1 = <&uart4_sleep_pins_a>; +- pinctrl-2 = <&uart4_idle_pins_a>; +- status = "okay"; +-}; +- +-&uart7 { +- pinctrl-names = "default", "sleep", "idle"; +- pinctrl-0 = <&uart7_pins_c>; +- pinctrl-1 = <&uart7_sleep_pins_c>; +- pinctrl-2 = <&uart7_idle_pins_c>; +- status = "disabled"; +-}; +- +-&usart3 { +- pinctrl-names = "default", "sleep", "idle"; +- pinctrl-0 = <&usart3_pins_c>; +- pinctrl-1 = <&usart3_sleep_pins_c>; +- pinctrl-2 = <&usart3_idle_pins_c>; +- uart-has-rtscts; +- status = "disabled"; +-}; +- +-&usbh_ehci { +- phys = <&usbphyc_port0>; +- status = "okay"; +-}; +- +-&usbotg_hs { +- phys = <&usbphyc_port1 0>; +- phy-names = "usb2-phy"; +- usb-role-switch; +- status = "okay"; +- +- port { +- usbotg_hs_ep: endpoint { +- remote-endpoint = <&con_usbotg_hs_ep>; +- }; +- }; +-}; +- +-&usbphyc { +- status = "okay"; +-}; +- +-&usbphyc_port0 { +- phy-supply = <&vdd_usb>; +-}; +- +-&usbphyc_port1 { +- phy-supply = <&vdd_usb>; +-}; +- +-&vrefbuf { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- vdda-supply = <&vdd>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp15xx-osd32.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp15xx-osd32.dtsi +deleted file mode 100644 +index 6706d8311a66..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp15xx-osd32.dtsi ++++ /dev/null +@@ -1,227 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */ +-/* +- * Copyright (C) 2020 STMicroelectronics - All Rights Reserved +- * Copyright (C) 2020 Ahmad Fatoum, Pengutronix +- */ +- +-#include "stm32mp15-pinctrl.dtsi" +- +-#include +- +-/ { +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- mcuram2: mcuram2@10000000 { +- compatible = "shared-dma-pool"; +- reg = <0x10000000 0x40000>; +- no-map; +- }; +- +- vdev0vring0: vdev0vring0@10040000 { +- compatible = "shared-dma-pool"; +- reg = <0x10040000 0x1000>; +- no-map; +- }; +- +- vdev0vring1: vdev0vring1@10041000 { +- compatible = "shared-dma-pool"; +- reg = <0x10041000 0x1000>; +- no-map; +- }; +- +- vdev0buffer: vdev0buffer@10042000 { +- compatible = "shared-dma-pool"; +- reg = <0x10042000 0x4000>; +- no-map; +- }; +- +- mcuram: mcuram@30000000 { +- compatible = "shared-dma-pool"; +- reg = <0x30000000 0x40000>; +- no-map; +- }; +- +- retram: retram@38000000 { +- compatible = "shared-dma-pool"; +- reg = <0x38000000 0x10000>; +- no-map; +- }; +- }; +- +- reg_sip_eeprom: regulator_eeprom { +- compatible = "regulator-fixed"; +- regulator-name = "sip_eeprom"; +- regulator-always-on; +- }; +-}; +- +-&i2c4 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c4_pins_a>; +- pinctrl-1 = <&i2c4_sleep_pins_a>; +- clock-frequency = <400000>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- +- pmic: stpmic@33 { +- compatible = "st,stpmic1"; +- reg = <0x33>; +- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- regulators { +- compatible = "st,stpmic1-regulators"; +- +- ldo1-supply = <&v3v3>; +- ldo6-supply = <&v3v3>; +- pwr_sw1-supply = <&bst_out>; +- +- vddcore: buck1 { +- regulator-name = "vddcore"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- vdd_ddr: buck2 { +- regulator-name = "vdd_ddr"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- vdd: buck3 { +- regulator-name = "vdd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- st,mask-reset; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- v3v3: buck4 { +- regulator-name = "v3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-over-current-protection; +- regulator-initial-mode = <0>; +- }; +- +- v1v8_audio: ldo1 { +- regulator-name = "v1v8_audio"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- interrupts = ; +- +- }; +- +- v3v3_hdmi: ldo2 { +- regulator-name = "v3v3_hdmi"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- interrupts = ; +- +- }; +- +- vtt_ddr: ldo3 { +- regulator-name = "vtt_ddr"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <750000>; +- regulator-always-on; +- regulator-over-current-protection; +- }; +- +- vdd_usb: ldo4 { +- regulator-name = "vdd_usb"; +- interrupts = ; +- }; +- +- vdda: ldo5 { +- regulator-name = "vdda"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- interrupts = ; +- regulator-boot-on; +- }; +- +- v1v2_hdmi: ldo6 { +- regulator-name = "v1v2_hdmi"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- interrupts = ; +- +- }; +- +- vref_ddr: vref_ddr { +- regulator-name = "vref_ddr"; +- regulator-always-on; +- }; +- +- bst_out: boost { +- regulator-name = "bst_out"; +- interrupts = ; +- }; +- +- vbus_otg: pwr_sw1 { +- regulator-name = "vbus_otg"; +- interrupts = ; +- regulator-active-discharge = <1>; +- }; +- +- vbus_sw: pwr_sw2 { +- regulator-name = "vbus_sw"; +- interrupts = ; +- regulator-active-discharge = <1>; +- }; +- }; +- +- onkey { +- compatible = "st,stpmic1-onkey"; +- interrupts = , ; +- interrupt-names = "onkey-falling", "onkey-rising"; +- }; +- +- pmic_watchdog: watchdog { +- compatible = "st,stpmic1-wdt"; +- status = "disabled"; +- }; +- }; +- +- sip_eeprom: eeprom@50 { +- compatible = "atmel,24c32"; +- vcc-supply = <®_sip_eeprom>; +- reg = <0x50>; +- }; +-}; +- +-&ipcc { +- status = "okay"; +-}; +- +-&m4_rproc { +- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, +- <&vdev0vring1>, <&vdev0buffer>; +- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; +- mbox-names = "vq0", "vq1", "shutdown"; +- interrupt-parent = <&exti>; +- interrupts = <68 1>; +- status = "okay"; +-}; +- +-&rng1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp15xxaa-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp15xxaa-pinctrl.dtsi +deleted file mode 100644 +index 04f7a43ad66f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp15xxaa-pinctrl.dtsi ++++ /dev/null +@@ -1,85 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved +- * Author: Alexandre Torgue for STMicroelectronics. +- */ +- +-&pinctrl { +- st,package = ; +- +- gpioa: gpio@50002000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 0 16>; +- }; +- +- gpiob: gpio@50003000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 16 16>; +- }; +- +- gpioc: gpio@50004000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 32 16>; +- }; +- +- gpiod: gpio@50005000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 48 16>; +- }; +- +- gpioe: gpio@50006000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 64 16>; +- }; +- +- gpiof: gpio@50007000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 80 16>; +- }; +- +- gpiog: gpio@50008000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 96 16>; +- }; +- +- gpioh: gpio@50009000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 112 16>; +- }; +- +- gpioi: gpio@5000a000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 128 16>; +- }; +- +- gpioj: gpio@5000b000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 144 16>; +- }; +- +- gpiok: gpio@5000c000 { +- status = "okay"; +- ngpios = <8>; +- gpio-ranges = <&pinctrl 0 160 8>; +- }; +-}; +- +-&pinctrl_z { +- st,package = ; +- +- gpioz: gpio@54004000 { +- status = "okay"; +- ngpios = <8>; +- gpio-ranges = <&pinctrl_z 0 400 8>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp15xxab-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp15xxab-pinctrl.dtsi +deleted file mode 100644 +index 328dad140e9b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp15xxab-pinctrl.dtsi ++++ /dev/null +@@ -1,57 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved +- * Author: Alexandre Torgue for STMicroelectronics. +- */ +- +-&pinctrl { +- st,package = ; +- +- gpioa: gpio@50002000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 0 16>; +- }; +- +- gpiob: gpio@50003000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 16 16>; +- }; +- +- gpioc: gpio@50004000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 32 16>; +- }; +- +- gpiod: gpio@50005000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 48 16>; +- }; +- +- gpioe: gpio@50006000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 64 16>; +- }; +- +- gpiof: gpio@50007000 { +- status = "okay"; +- ngpios = <6>; +- gpio-ranges = <&pinctrl 6 86 6>; +- }; +- +- gpiog: gpio@50008000 { +- status = "okay"; +- ngpios = <10>; +- gpio-ranges = <&pinctrl 6 102 10>; +- }; +- +- gpioh: gpio@50009000 { +- status = "okay"; +- ngpios = <2>; +- gpio-ranges = <&pinctrl 0 112 2>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp15xxac-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp15xxac-pinctrl.dtsi +deleted file mode 100644 +index 7eaa245f44db..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp15xxac-pinctrl.dtsi ++++ /dev/null +@@ -1,73 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved +- * Author: Alexandre Torgue for STMicroelectronics. +- */ +- +-&pinctrl { +- st,package = ; +- +- gpioa: gpio@50002000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 0 16>; +- }; +- +- gpiob: gpio@50003000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 16 16>; +- }; +- +- gpioc: gpio@50004000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 32 16>; +- }; +- +- gpiod: gpio@50005000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 48 16>; +- }; +- +- gpioe: gpio@50006000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 64 16>; +- }; +- +- gpiof: gpio@50007000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 80 16>; +- }; +- +- gpiog: gpio@50008000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 96 16>; +- }; +- +- gpioh: gpio@50009000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 112 16>; +- }; +- +- gpioi: gpio@5000a000 { +- status = "okay"; +- ngpios = <12>; +- gpio-ranges = <&pinctrl 0 128 12>; +- }; +-}; +- +-&pinctrl_z { +- st,package = ; +- +- gpioz: gpio@54004000 { +- status = "okay"; +- ngpios = <8>; +- gpio-ranges = <&pinctrl_z 0 400 8>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/stm32mp15xxad-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/stm32mp15xxad-pinctrl.dtsi +deleted file mode 100644 +index b63e207de216..000000000000 +--- a/scripts/dtc/include-prefixes/arm/stm32mp15xxad-pinctrl.dtsi ++++ /dev/null +@@ -1,57 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved +- * Author: Alexandre Torgue for STMicroelectronics. +- */ +- +-&pinctrl { +- st,package = ; +- +- gpioa: gpio@50002000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 0 16>; +- }; +- +- gpiob: gpio@50003000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 16 16>; +- }; +- +- gpioc: gpio@50004000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 32 16>; +- }; +- +- gpiod: gpio@50005000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 48 16>; +- }; +- +- gpioe: gpio@50006000 { +- status = "okay"; +- ngpios = <16>; +- gpio-ranges = <&pinctrl 0 64 16>; +- }; +- +- gpiof: gpio@50007000 { +- status = "okay"; +- ngpios = <6>; +- gpio-ranges = <&pinctrl 6 86 6>; +- }; +- +- gpiog: gpio@50008000 { +- status = "okay"; +- ngpios = <10>; +- gpio-ranges = <&pinctrl 6 102 10>; +- }; +- +- gpioh: gpio@50009000 { +- status = "okay"; +- ngpios = <2>; +- gpio-ranges = <&pinctrl 0 112 2>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-a1000.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-a1000.dts +deleted file mode 100644 +index 20f9ed244851..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-a1000.dts ++++ /dev/null +@@ -1,255 +0,0 @@ +-/* +- * Copyright 2013 Emilio López +- * +- * Emilio López +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- model = "Mele A1000"; +- compatible = "mele,a1000", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "a1000:red:usr"; +- gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; +- }; +- +- led-1 { +- label = "a1000:blue:pwr"; +- gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- reg_emac_3v3: emac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "emac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <20000>; +- enable-active-high; +- gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "On-board SPDIF"; +- +- simple-audio-card,cpu { +- sound-dai = <&spdif>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&spdif_out>; +- }; +- }; +- +- spdif_out: spdif-out { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- }; +-}; +- +-&ahci { +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&phy1>; +- status = "okay"; +-}; +- +-&emac_sram { +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- compatible = "x-powers,axp209"; +- reg = <0x34>; +- interrupts = <0>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pins>; +- status = "okay"; +-}; +- +-&mdio { +- phy-supply = <®_emac_3v3>; +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-#include "axp209.dtsi" +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1250000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&spdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&spdif_tx_pin>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-ba10-tvbox.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-ba10-tvbox.dts +deleted file mode 100644 +index 816d534ac093..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-ba10-tvbox.dts ++++ /dev/null +@@ -1,151 +0,0 @@ +-/* +- * Copyright 2014 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- model = "BA10 tvbox"; +- compatible = "allwinner,ba10-tvbox", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&phy1>; +- status = "okay"; +-}; +- +-&emac_sram { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- compatible = "x-powers,axp209"; +- reg = <0x34>; +- interrupts = <0>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pins>; +- status = "okay"; +-}; +- +-&mdio { +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_usb0_vbus { +- regulator-boot-on; +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-chuwi-v7-cw0825.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-chuwi-v7-cw0825.dts +deleted file mode 100644 +index 74262988881c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-chuwi-v7-cw0825.dts ++++ /dev/null +@@ -1,159 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "Chuwi V7 CW0825"; +- compatible = "chuwi,v7-cw0825", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- compatible = "x-powers,axp209"; +- reg = <0x34>; +- interrupts = <0>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +- +- ft5306de4: touchscreen@38 { +- compatible = "edt,edt-ft5406"; +- reg = <0x38>; +- interrupt-parent = <&pio>; +- interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; +- touchscreen-size-x = <1024>; +- touchscreen-size-y = <768>; +- }; +-}; +- +-&lradc { +- vref-supply = <®_vcc3v0>; +- status = "okay"; +- +- button-800 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <800000>; +- }; +- +- button-1000 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <1000000>; +- }; +- +- button-1200 { +- label = "Back"; +- linux,code = ; +- channel = <0>; +- voltage = <1200000>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-cubieboard.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-cubieboard.dts +deleted file mode 100644 +index 0645d6064235..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-cubieboard.dts ++++ /dev/null +@@ -1,255 +0,0 @@ +-/* +- * Copyright 2012 Stefan Roese +- * Stefan Roese +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- model = "Cubietech Cubieboard"; +- compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins_cubieboard>; +- +- led-0 { +- label = "cubieboard:blue:usr"; +- gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* LED1 */ +- }; +- +- led-1 { +- label = "cubieboard:green:usr"; +- gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* LED2 */ +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-&ahci { +- target-supply = <®_ahci_5v>; +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&phy1>; +- status = "okay"; +-}; +- +-&emac_sram { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupts = <0>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pins>; +- status = "okay"; +-}; +- +-&mdio { +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pio { +- led_pins_cubieboard: led-pins { +- pins = "PH20", "PH21"; +- function = "gpio_out"; +- drive-strength = <20>; +- }; +-}; +- +-®_ahci_5v { +- status = "okay"; +-}; +- +-#include "axp209.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1450000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pi_pins>, +- <&spi0_cs0_pi_pin>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-dserve-dsrv9703c.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-dserve-dsrv9703c.dts +deleted file mode 100644 +index 63e77c05bfda..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-dserve-dsrv9703c.dts ++++ /dev/null +@@ -1,218 +0,0 @@ +-/* +- * Copyright 2016 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "Dserve DSRV9703C"; +- compatible = "dserve,dsrv9703c", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; +- brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; +- default-brightness-level = <8>; +- enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ +- power-supply = <®_vcc3v3>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- haptics { +- compatible = "regulator-haptic"; +- haptic-supply = <®_motor>; +- min-microvolt = <3000000>; +- max-microvolt = <3000000>; +- }; +- +- reg_motor: reg-motor { +- compatible = "regulator-fixed"; +- regulator-name = "vcc-motor"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- enable-active-high; +- gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ +- }; +-}; +- +-&codec { +- allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupts = <0>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&i2c1 { +- /* pull-ups and devices require AXP209 LDO3 */ +- status = "failed"; +-}; +- +-&i2c2 { +- status = "okay"; +- +- ft5406ee8: touchscreen@38 { +- compatible = "edt,edt-ft5406"; +- reg = <0x38>; +- interrupt-parent = <&pio>; +- interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>; +- touchscreen-size-x = <1024>; +- touchscreen-size-y = <768>; +- }; +-}; +- +-&lradc { +- vref-supply = <®_ldo2>; +- status = "okay"; +- +- button-400 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <400000>; +- }; +- +- button-800 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <800000>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>; +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-gemei-g9.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-gemei-g9.dts +deleted file mode 100644 +index ea7a59dcf8f9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-gemei-g9.dts ++++ /dev/null +@@ -1,192 +0,0 @@ +-/* +- * Copyright 2015 Priit Laes +- * +- * Priit Laes +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "Gemei G9 Tablet"; +- compatible = "gemei,g9", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-/* +- * TODO: +- * 2x cameras via CSI +- * AXP battery management +- * NAND +- * OTG +- * Touchscreen - gt801_2plus1 @ i2c adapter 2 @ 0x48 +- */ +-&codec { +- /* PH15 controls power to external amplifier (ft2012q) */ +- allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupts = <0>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&i2c1 { +- status = "okay"; +- +- /* Accelerometer */ +- bma250@18 { +- compatible = "bosch,bma250"; +- reg = <0x18>; +- interrupt-parent = <&pio>; +- interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH00 / EINT0 */ +- }; +-}; +- +-&lradc { +- vref-supply = <®_ldo2>; +- +- status = "okay"; +- +- button-158 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <158730>; +- }; +- +- button-349 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <349206>; +- }; +- +- button-1142 { +- label = "Esc"; +- linux,code = ; +- channel = <0>; +- voltage = <1142856>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */ +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-hackberry.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-hackberry.dts +deleted file mode 100644 +index 47dea0922501..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-hackberry.dts ++++ /dev/null +@@ -1,140 +0,0 @@ +-/* +- * Copyright 2012 Maxime Ripard +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- model = "Miniand Hackberry"; +- compatible = "miniand,hackberry", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- reg_emac_3v3: emac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "emac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <20000>; +- enable-active-high; +- gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&phy0>; +- status = "okay"; +-}; +- +-&emac_sram { +- status = "okay"; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pins>; +- status = "okay"; +-}; +- +-&mdio { +- phy-supply = <®_emac_3v3>; +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-hyundai-a7hd.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-hyundai-a7hd.dts +deleted file mode 100644 +index bf2044bac42f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-hyundai-a7hd.dts ++++ /dev/null +@@ -1,115 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +-#include +- +-/ { +- model = "Hyundai A7HD"; +- compatible = "hyundai,a7hd", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- compatible = "x-powers,axp209"; +- reg = <0x34>; +- interrupts = <0>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-inet1.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-inet1.dts +deleted file mode 100644 +index 60e432a0ef1c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-inet1.dts ++++ /dev/null +@@ -1,229 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "iNet-1"; +- compatible = "inet-tek,inet1", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; +- brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; +- default-brightness-level = <8>; +- enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ +- power-supply = <®_vcc3v3>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupts = <0>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&i2c1 { +- status = "okay"; +- +- /* Accelerometer */ +- bma250@18 { +- compatible = "bosch,bma250"; +- reg = <0x18>; +- interrupt-parent = <&pio>; +- interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH0 / EINT0 */ +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- +- ft5x: touchscreen@38 { +- compatible = "edt,edt-ft5406"; +- reg = <0x38>; +- interrupt-parent = <&pio>; +- interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; +- wake-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* PB13 */ +- touchscreen-size-x = <600>; +- touchscreen-size-y = <1024>; +- touchscreen-swapped-x-y; +- }; +-}; +- +-&lradc { +- vref-supply = <®_ldo2>; +- status = "okay"; +- +- button-200 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <200000>; +- }; +- +- button-1000 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <1000000>; +- }; +- +- button-1200 { +- label = "Home"; +- linux,code = ; +- channel = <0>; +- voltage = <1200000>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>; +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-inet97fv2.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-inet97fv2.dts +deleted file mode 100644 +index 76016f2ca29d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-inet97fv2.dts ++++ /dev/null +@@ -1,203 +0,0 @@ +-/* +- * Copyright 2014 Open Source Support GmbH +- * +- * David Lanzendörfer +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +-#include +- +-/ { +- model = "INet-97F Rev 02"; +- compatible = "primux,inet97fv2", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupts = <0>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +- +- ft5406ee8: touchscreen@38 { +- compatible = "edt,edt-ft5406"; +- reg = <0x38>; +- interrupt-parent = <&pio>; +- interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; +- touchscreen-size-x = <800>; +- touchscreen-size-y = <480>; +- }; +-}; +- +-&lradc { +- vref-supply = <®_ldo2>; +- status = "okay"; +- +- button-200 { +- label = "Menu"; +- linux,code = ; +- channel = <0>; +- voltage = <200000>; +- }; +- +- button-600 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <600000>; +- }; +- +- button-800 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <800000>; +- }; +- +- button-1000 { +- label = "Home"; +- linux,code = ; +- channel = <0>; +- voltage = <1000000>; +- }; +- +- button-1200 { +- label = "Esc"; +- linux,code = ; +- channel = <0>; +- voltage = <1200000>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-inet9f-rev03.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-inet9f-rev03.dts +deleted file mode 100644 +index 0a562b2cc5bc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-inet9f-rev03.dts ++++ /dev/null +@@ -1,357 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "iNet-9F Rev 03"; +- compatible = "inet-tek,inet9f-rev03", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys-polled"; +- poll-interval = <20>; +- +- left-joystick-left { +- label = "Left Joystick Left"; +- linux,code = ; +- linux,input-type = ; +- linux,input-value = <0xffffffff>; /* -1 */ +- gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */ +- }; +- +- left-joystick-right { +- label = "Left Joystick Right"; +- linux,code = ; +- linux,input-type = ; +- linux,input-value = <1>; +- gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */ +- }; +- +- left-joystick-up { +- label = "Left Joystick Up"; +- linux,code = ; +- linux,input-type = ; +- linux,input-value = <0xffffffff>; /* -1 */ +- gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */ +- }; +- +- left-joystick-down { +- label = "Left Joystick Down"; +- linux,code = ; +- linux,input-type = ; +- linux,input-value = <1>; +- gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */ +- }; +- +- right-joystick-left { +- label = "Right Joystick Left"; +- linux,code = ; +- linux,input-type = ; +- linux,input-value = <0xffffffff>; /* -1 */ +- gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */ +- }; +- +- right-joystick-right { +- label = "Right Joystick Right"; +- linux,code = ; +- linux,input-type = ; +- linux,input-value = <1>; +- gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */ +- }; +- +- right-joystick-up { +- label = "Right Joystick Up"; +- linux,code = ; +- linux,input-type = ; +- linux,input-value = <0xffffffff>; /* -1 */ +- gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */ +- }; +- +- right-joystick-down { +- label = "Right Joystick Down"; +- linux,code = ; +- linux,input-type = ; +- linux,input-value = <1>; +- gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */ +- }; +- +- dpad-left { +- label = "DPad Left"; +- linux,code = ; +- linux,input-type = ; +- linux,input-value = <0xffffffff>; /* -1 */ +- gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */ +- }; +- +- dpad-right { +- label = "DPad Right"; +- linux,code = ; +- linux,input-type = ; +- linux,input-value = <1>; +- gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */ +- }; +- +- dpad-up { +- label = "DPad Up"; +- linux,code = ; +- linux,input-type = ; +- linux,input-value = <0xffffffff>; /* -1 */ +- gpios = <&pio 7 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH25 */ +- }; +- +- dpad-down { +- label = "DPad Down"; +- linux,code = ; +- linux,input-type = ; +- linux,input-value = <1>; +- gpios = <&pio 7 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH26 */ +- }; +- +- x { +- label = "Button X"; +- linux,code = ; +- gpios = <&pio 0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA16 */ +- }; +- +- y { +- label = "Button Y"; +- linux,code = ; +- gpios = <&pio 0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA14 */ +- }; +- +- a { +- label = "Button A"; +- linux,code = ; +- gpios = <&pio 0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA17 */ +- }; +- +- b { +- label = "Button B"; +- linux,code = ; +- gpios = <&pio 0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA15 */ +- }; +- +- select { +- label = "Select Button"; +- linux,code = ; +- gpios = <&pio 0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA11 */ +- }; +- +- start { +- label = "Start Button"; +- linux,code = ; +- gpios = <&pio 0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA12 */ +- }; +- +- top-left { +- label = "Top Left Button"; +- linux,code = ; +- gpios = <&pio 7 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH22 */ +- }; +- +- top-right { +- label = "Top Right Button"; +- linux,code = ; +- gpios = <&pio 0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA13 */ +- }; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupts = <0>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&i2c1 { +- status = "okay"; +- +- /* Accelerometer */ +- bma250@18 { +- compatible = "bosch,bma250"; +- reg = <0x18>; +- interrupt-parent = <&pio>; +- interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH0 / EINT0 */ +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- +- ft5406ee8: touchscreen@38 { +- compatible = "edt,edt-ft5406"; +- reg = <0x38>; +- interrupt-parent = <&pio>; +- interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; +- touchscreen-size-x = <800>; +- touchscreen-size-y = <480>; +- }; +-}; +- +-&lradc { +- vref-supply = <®_ldo2>; +- status = "okay"; +- +- button-200 { +- label = "Menu"; +- linux,code = ; +- channel = <0>; +- voltage = <200000>; +- }; +- +- button-600 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <600000>; +- }; +- +- button-800 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <800000>; +- }; +- +- button-1000 { +- label = "Home"; +- linux,code = ; +- channel = <0>; +- voltage = <1000000>; +- }; +- +- button-1200 { +- label = "Esc"; +- linux,code = ; +- channel = <0>; +- voltage = <1200000>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-itead-iteaduino-plus.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-itead-iteaduino-plus.dts +deleted file mode 100644 +index d4e319d16aae..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-itead-iteaduino-plus.dts ++++ /dev/null +@@ -1,126 +0,0 @@ +-/* +- * Copyright 2015 Josef Gajdusek +- * Copyright 2015 - Marcus Cooper +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-itead-core-common.dtsi" +- +-/ { +- model = "Iteaduino Plus A10"; +- compatible = "itead,iteaduino-plus-a10", "allwinner,sun4i-a10"; +-}; +- +-&ahci { +- target-supply = <®_ahci_5v>; +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_pins>; +- phy-handle = <&phy1>; +- status = "okay"; +-}; +- +-&emac_sram { +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- +- axp209: pmic@34 { +- interrupts = <0>; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "okay"; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pins>; +- status = "okay"; +-}; +- +-&mdio { +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-®_ahci_5v { +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pi_pins>, +- <&spi0_cs0_pi_pin>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-0 = <&uart0_pb_pins>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-jesurun-q5.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-jesurun-q5.dts +deleted file mode 100644 +index 1aeb0bd5519e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-jesurun-q5.dts ++++ /dev/null +@@ -1,181 +0,0 @@ +-/* +- * Copyright 2015 Gábor Nyers +- * +- * Gábor Nyers +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- model = "Jesurun Q5"; +- compatible = "jesurun,q5", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led { +- label = "q5:green:usr"; +- gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* PH20 */ +- }; +- +- }; +- +- reg_emac_3v3: emac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "emac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <20000>; +- enable-active-high; +- gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ +- }; +-}; +- +-&ahci { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&phy1>; +- status = "okay"; +-}; +- +-&emac_sram { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- compatible = "x-powers,axp209"; +- reg = <0x34>; +- interrupts = <0>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pins>; +- status = "okay"; +-}; +- +-&mdio { +- phy-supply = <®_emac_3v3>; +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_usb0_vbus { +- regulator-boot-on; +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-marsboard.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-marsboard.dts +deleted file mode 100644 +index 81fdb217d339..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-marsboard.dts ++++ /dev/null +@@ -1,182 +0,0 @@ +-/* +- * Copyright 2015 Aleksei Mamlin +- * Aleksei Mamlin +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- model = "HAOYU Electronics Marsboard A10"; +- compatible = "haoyu,a10-marsboard", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "marsboard:red1:usr"; +- gpios = <&pio 1 5 GPIO_ACTIVE_HIGH>; +- }; +- +- led-1 { +- label = "marsboard:red2:usr"; +- gpios = <&pio 1 6 GPIO_ACTIVE_HIGH>; +- }; +- +- led-2 { +- label = "marsboard:red3:usr"; +- gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; +- }; +- +- led-3 { +- label = "marsboard:red4:usr"; +- gpios = <&pio 1 8 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&ahci { +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emac_sram { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&phy1>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&mdio { +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pi_pins>, +- <&spi0_cs0_pi_pin>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-mini-xplus.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-mini-xplus.dts +deleted file mode 100644 +index f9d74e21031d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-mini-xplus.dts ++++ /dev/null +@@ -1,144 +0,0 @@ +-/* +- * Copyright 2012 Maxime Ripard +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- model = "PineRiver Mini X-Plus"; +- compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- compatible = "x-powers,axp209"; +- reg = <0x34>; +- interrupts = <0>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pins>; +- status = "okay"; +-}; +- +-&ir0_rx_pins { +- /* The ir receiver is not always populated */ +- bias-pull-up; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_usb0_vbus { +- regulator-boot-on; +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-mk802.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-mk802.dts +deleted file mode 100644 +index 059fe9c5d024..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-mk802.dts ++++ /dev/null +@@ -1,144 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +-#include +- +-/ { +- model = "MK802"; +- compatible = "allwinner,mk802", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ +- usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-mk802ii.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-mk802ii.dts +deleted file mode 100644 +index 17dcdf031118..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-mk802ii.dts ++++ /dev/null +@@ -1,111 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +-#include +- +-/ { +- model = "MK802ii"; +- compatible = "allwinner,mk802ii", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- compatible = "x-powers,axp209"; +- reg = <0x34>; +- interrupts = <0>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-olinuxino-lime.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-olinuxino-lime.dts +deleted file mode 100644 +index ad0e25af45be..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-olinuxino-lime.dts ++++ /dev/null +@@ -1,226 +0,0 @@ +-/* +- * Copyright 2014 - Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- model = "Olimex A10-OLinuXino-LIME"; +- compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins_olinuxinolime>; +- +- led { +- label = "a10-olinuxino-lime:green:usr"; +- gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +-}; +- +-&ahci { +- target-supply = <®_ahci_5v>; +- status = "okay"; +-}; +- +-&cpu0 { +- /* +- * The A10-Lime is known to be unstable when running at 1008 MHz +- */ +- operating-points = < +- /* kHz uV */ +- 912000 1350000 +- 864000 1300000 +- 624000 1250000 +- >; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&phy1>; +- status = "okay"; +-}; +- +-&emac_sram { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- compatible = "x-powers,axp209"; +- reg = <0x34>; +- interrupts = <0>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c16"; +- reg = <0x50>; +- pagesize = <16>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pio { +- led_pins_olinuxinolime: led-pin { +- pins = "PH2"; +- function = "gpio_out"; +- drive-strength = <20>; +- }; +-}; +- +-®_ahci_5v { +- gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH5 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-pcduino.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-pcduino.dts +deleted file mode 100644 +index 1ac82376baef..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-pcduino.dts ++++ /dev/null +@@ -1,200 +0,0 @@ +-/* +- * Copyright 2014 Zoltan HERPAI +- * Zoltan HERPAI +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "LinkSprite pcDuino"; +- compatible = "linksprite,a10-pcduino", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "pcduino:green:tx"; +- gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; +- }; +- +- led-1 { +- label = "pcduino:green:rx"; +- gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- back { +- label = "Key Back"; +- linux,code = ; +- gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; +- }; +- +- home { +- label = "Key Home"; +- linux,code = ; +- gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; +- }; +- +- menu { +- label = "Key Menu"; +- linux,code = ; +- gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&phy1>; +- status = "okay"; +-}; +- +-&emac_sram { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupts = <0>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-#include "axp209.dtsi" +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ +- usb2_vbus-supply = <®_vcc5v0>; /* USB2 VBUS is always on */ +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-pcduino2.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-pcduino2.dts +deleted file mode 100644 +index bc4f128965ed..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-pcduino2.dts ++++ /dev/null +@@ -1,67 +0,0 @@ +-/* +- * Copyright 2015 Siarhei Siamashka +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/* +- * The LinkSprite pcDuino2 board is almost identical to the older +- * LinkSprite pcDuino1 board. The only software visible difference +- * is that the pcDuino2 board got a USB VBUS voltage regulator, which +- * is controlled by the PD2 pin (pulled-up by default). Also one of +- * the USB host ports has been replaced with a USB WIFI chip. +- */ +- +-#include "sun4i-a10-pcduino.dts" +- +-/ { +- model = "LinkSprite pcDuino2"; +- compatible = "linksprite,a10-pcduino2", "allwinner,sun4i-a10"; +-}; +- +-®_usb2_vbus { +- gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_vcc3v3>; /* USB WIFI is always on */ +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-pov-protab2-ips9.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-pov-protab2-ips9.dts +deleted file mode 100644 +index c32596947647..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-pov-protab2-ips9.dts ++++ /dev/null +@@ -1,206 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "Point of View Protab2-IPS9"; +- compatible = "pov,protab2-ips9", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; +- brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; +- default-brightness-level = <8>; +- enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ +- power-supply = <®_vcc3v3>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&codec { +- allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupts = <0>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&i2c1 { +- /* pull-ups and devices require AXP209 LDO3 */ +- status = "failed"; +-}; +- +-&i2c2 { +- status = "okay"; +- +- touchscreen@5c { +- compatible = "pixcir,pixcir_tangoc"; +- reg = <0x5c>; +- interrupt-parent = <&pio>; +- interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; /* EINT21 (PH21) */ +- attb-gpio = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* PH21 */ +- enable-gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; +- wake-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>; +- touchscreen-size-x = <1024>; +- touchscreen-size-y = <768>; +- touchscreen-inverted-x; +- touchscreen-inverted-y; +- }; +-}; +- +-&lradc { +- vref-supply = <®_ldo2>; +- status = "okay"; +- +- button-400 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <400000>; +- }; +- +- button-800 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <800000>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>; +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10-topwise-a721.dts b/scripts/dtc/include-prefixes/arm/sun4i-a10-topwise-a721.dts +deleted file mode 100644 +index 3628f12d2521..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10-topwise-a721.dts ++++ /dev/null +@@ -1,242 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2020 Pascal Roeleven +- */ +- +-/dts-v1/; +-#include "sun4i-a10.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +-#include +-#include +- +-/ { +- model = "Topwise A721"; +- compatible = "topwise,a721", "allwinner,sun4i-a10"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 100000 PWM_POLARITY_INVERTED>; +- power-supply = <®_vbat>; +- enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ +- brightness-levels = <0 30 40 50 60 70 80 90 100>; +- default-brightness-level = <8>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- panel { +- compatible = "starry,kr070pe2t"; +- backlight = <&backlight>; +- power-supply = <®_lcd_power>; +- +- port { +- panel_input: endpoint { +- remote-endpoint = <&tcon0_out_panel>; +- }; +- }; +- }; +- +- reg_lcd_power: reg-lcd-power { +- compatible = "regulator-fixed"; +- regulator-name = "reg-lcd-power"; +- gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ +- enable-active-high; +- }; +- +- reg_vbat: reg-vbat { +- compatible = "regulator-fixed"; +- regulator-name = "vbat"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- }; +- +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupts = <0>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- +- accelerometer@4c { +- compatible = "fsl,mma7660"; +- reg = <0x4c>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- +- touchscreen@38 { +- compatible = "edt,edt-ft5406"; +- reg = <0x38>; +- interrupt-parent = <&pio>; +- interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; +- touchscreen-size-x = <800>; +- touchscreen-size-y = <480>; +- vcc-supply = <®_vcc3v3>; +- }; +-}; +- +-&lradc { +- vref-supply = <®_ldo2>; +- status = "okay"; +- +- button-571 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <571428>; +- }; +- +- button-761 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <761904>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pio { +- vcc-pb-supply = <®_vcc3v3>; +- vcc-pf-supply = <®_vcc3v3>; +- vcc-ph-supply = <®_vcc3v3>; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>; +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&tcon0_out { +- tcon0_out_panel: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_input>; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ +- usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun4i-a10.dtsi b/scripts/dtc/include-prefixes/arm/sun4i-a10.dtsi +deleted file mode 100644 +index 1c5a666c54b5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun4i-a10.dtsi ++++ /dev/null +@@ -1,1272 +0,0 @@ +-/* +- * Copyright 2012 Stefan Roese +- * Stefan Roese +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This library is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This library is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&intc>; +- +- aliases { +- ethernet0 = &emac; +- }; +- +- chosen { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- framebuffer-lcd0-hdmi { +- compatible = "allwinner,simple-framebuffer", +- "simple-framebuffer"; +- allwinner,pipeline = "de_be0-lcd0-hdmi"; +- clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, +- <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, +- <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>; +- status = "disabled"; +- }; +- +- framebuffer-fe0-lcd0-hdmi { +- compatible = "allwinner,simple-framebuffer", +- "simple-framebuffer"; +- allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; +- clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, +- <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, +- <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, +- <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>, +- <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; +- status = "disabled"; +- }; +- +- framebuffer-fe0-lcd0 { +- compatible = "allwinner,simple-framebuffer", +- "simple-framebuffer"; +- allwinner,pipeline = "de_fe0-de_be0-lcd0"; +- clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, +- <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>, +- <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>, +- <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; +- status = "disabled"; +- }; +- +- framebuffer-fe0-lcd0-tve0 { +- compatible = "allwinner,simple-framebuffer", +- "simple-framebuffer"; +- allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; +- clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, +- <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, +- <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, +- <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>, +- <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; +- status = "disabled"; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a8"; +- reg = <0x0>; +- clocks = <&ccu CLK_CPU>; +- clock-latency = <244144>; /* 8 32k periods */ +- operating-points = < +- /* kHz uV */ +- 1008000 1400000 +- 912000 1350000 +- 864000 1300000 +- 624000 1250000 +- >; +- #cooling-cells = <2>; +- }; +- }; +- +- thermal-zones { +- cpu-thermal { +- /* milliseconds */ +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&rtp>; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- +- trips { +- cpu_alert0: cpu-alert0 { +- /* milliCelsius */ +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_crit: cpu-crit { +- /* milliCelsius */ +- temperature = <100000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- osc24M: clk-24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "osc24M"; +- }; +- +- osc32k: clk-32k { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-output-names = "osc32k"; +- }; +- }; +- +- de: display-engine { +- compatible = "allwinner,sun4i-a10-display-engine"; +- allwinner,pipelines = <&fe0>, <&fe1>; +- status = "disabled"; +- }; +- +- pmu { +- compatible = "arm,cortex-a8-pmu"; +- interrupts = <3>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ +- default-pool { +- compatible = "shared-dma-pool"; +- size = <0x6000000>; +- alloc-ranges = <0x40000000 0x10000000>; +- reusable; +- linux,cma-default; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- system-control@1c00000 { +- compatible = "allwinner,sun4i-a10-system-control"; +- reg = <0x01c00000 0x30>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- sram_a: sram@0 { +- compatible = "mmio-sram"; +- reg = <0x00000000 0xc000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00000000 0xc000>; +- +- emac_sram: sram-section@8000 { +- compatible = "allwinner,sun4i-a10-sram-a3-a4"; +- reg = <0x8000 0x4000>; +- status = "disabled"; +- }; +- }; +- +- sram_d: sram@10000 { +- compatible = "mmio-sram"; +- reg = <0x00010000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00010000 0x1000>; +- +- otg_sram: sram-section@0 { +- compatible = "allwinner,sun4i-a10-sram-d"; +- reg = <0x0000 0x1000>; +- status = "disabled"; +- }; +- }; +- +- sram_c: sram@1d00000 { +- compatible = "mmio-sram"; +- reg = <0x01d00000 0xd0000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x01d00000 0xd0000>; +- +- ve_sram: sram-section@0 { +- compatible = "allwinner,sun4i-a10-sram-c1"; +- reg = <0x000000 0x80000>; +- }; +- }; +- }; +- +- dma: dma-controller@1c02000 { +- compatible = "allwinner,sun4i-a10-dma"; +- reg = <0x01c02000 0x1000>; +- interrupts = <27>; +- clocks = <&ccu CLK_AHB_DMA>; +- #dma-cells = <2>; +- }; +- +- nfc: nand-controller@1c03000 { +- compatible = "allwinner,sun4i-a10-nand"; +- reg = <0x01c03000 0x1000>; +- interrupts = <37>; +- clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; +- clock-names = "ahb", "mod"; +- dmas = <&dma SUN4I_DMA_DEDICATED 3>; +- dma-names = "rxtx"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spi0: spi@1c05000 { +- compatible = "allwinner,sun4i-a10-spi"; +- reg = <0x01c05000 0x1000>; +- interrupts = <10>; +- clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; +- clock-names = "ahb", "mod"; +- dmas = <&dma SUN4I_DMA_DEDICATED 27>, +- <&dma SUN4I_DMA_DEDICATED 26>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spi1: spi@1c06000 { +- compatible = "allwinner,sun4i-a10-spi"; +- reg = <0x01c06000 0x1000>; +- interrupts = <11>; +- clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; +- clock-names = "ahb", "mod"; +- dmas = <&dma SUN4I_DMA_DEDICATED 9>, +- <&dma SUN4I_DMA_DEDICATED 8>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- emac: ethernet@1c0b000 { +- compatible = "allwinner,sun4i-a10-emac"; +- reg = <0x01c0b000 0x1000>; +- interrupts = <55>; +- clocks = <&ccu CLK_AHB_EMAC>; +- allwinner,sram = <&emac_sram 1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_pins>; +- status = "disabled"; +- }; +- +- mdio: mdio@1c0b080 { +- compatible = "allwinner,sun4i-a10-mdio"; +- reg = <0x01c0b080 0x14>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- tcon0: lcd-controller@1c0c000 { +- compatible = "allwinner,sun4i-a10-tcon"; +- reg = <0x01c0c000 0x1000>; +- interrupts = <44>; +- resets = <&ccu RST_TCON0>; +- reset-names = "lcd"; +- clocks = <&ccu CLK_AHB_LCD0>, +- <&ccu CLK_TCON0_CH0>, +- <&ccu CLK_TCON0_CH1>; +- clock-names = "ahb", +- "tcon-ch0", +- "tcon-ch1"; +- clock-output-names = "tcon0-pixel-clock"; +- #clock-cells = <0>; +- dmas = <&dma SUN4I_DMA_DEDICATED 14>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon0_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- tcon0_in_be0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&be0_out_tcon0>; +- }; +- +- tcon0_in_be1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&be1_out_tcon0>; +- }; +- }; +- +- tcon0_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tcon0_out_hdmi: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&hdmi_in_tcon0>; +- allwinner,tcon-channel = <1>; +- }; +- }; +- }; +- }; +- +- tcon1: lcd-controller@1c0d000 { +- compatible = "allwinner,sun4i-a10-tcon"; +- reg = <0x01c0d000 0x1000>; +- interrupts = <45>; +- resets = <&ccu RST_TCON1>; +- reset-names = "lcd"; +- clocks = <&ccu CLK_AHB_LCD1>, +- <&ccu CLK_TCON1_CH0>, +- <&ccu CLK_TCON1_CH1>; +- clock-names = "ahb", +- "tcon-ch0", +- "tcon-ch1"; +- clock-output-names = "tcon1-pixel-clock"; +- #clock-cells = <0>; +- dmas = <&dma SUN4I_DMA_DEDICATED 15>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon1_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- tcon1_in_be0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&be0_out_tcon1>; +- }; +- +- tcon1_in_be1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&be1_out_tcon1>; +- }; +- }; +- +- tcon1_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tcon1_out_hdmi: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&hdmi_in_tcon1>; +- allwinner,tcon-channel = <1>; +- }; +- }; +- }; +- }; +- +- video-codec@1c0e000 { +- compatible = "allwinner,sun4i-a10-video-engine"; +- reg = <0x01c0e000 0x1000>; +- clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, +- <&ccu CLK_DRAM_VE>; +- clock-names = "ahb", "mod", "ram"; +- resets = <&ccu RST_VE>; +- interrupts = <53>; +- allwinner,sram = <&ve_sram 1>; +- }; +- +- mmc0: mmc@1c0f000 { +- compatible = "allwinner,sun4i-a10-mmc"; +- reg = <0x01c0f000 0x1000>; +- clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; +- clock-names = "ahb", "mmc"; +- interrupts = <32>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc1: mmc@1c10000 { +- compatible = "allwinner,sun4i-a10-mmc"; +- reg = <0x01c10000 0x1000>; +- clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; +- clock-names = "ahb", "mmc"; +- interrupts = <33>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc2: mmc@1c11000 { +- compatible = "allwinner,sun4i-a10-mmc"; +- reg = <0x01c11000 0x1000>; +- clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; +- clock-names = "ahb", "mmc"; +- interrupts = <34>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc3: mmc@1c12000 { +- compatible = "allwinner,sun4i-a10-mmc"; +- reg = <0x01c12000 0x1000>; +- clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>; +- clock-names = "ahb", "mmc"; +- interrupts = <35>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- usb_otg: usb@1c13000 { +- compatible = "allwinner,sun4i-a10-musb"; +- reg = <0x01c13000 0x0400>; +- clocks = <&ccu CLK_AHB_OTG>; +- interrupts = <38>; +- interrupt-names = "mc"; +- phys = <&usbphy 0>; +- phy-names = "usb"; +- extcon = <&usbphy 0>; +- allwinner,sram = <&otg_sram 1>; +- dr_mode = "otg"; +- status = "disabled"; +- }; +- +- usbphy: phy@1c13400 { +- #phy-cells = <1>; +- compatible = "allwinner,sun4i-a10-usb-phy"; +- reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>; +- reg-names = "phy_ctrl", "pmu1", "pmu2"; +- clocks = <&ccu CLK_USB_PHY>; +- clock-names = "usb_phy"; +- resets = <&ccu RST_USB_PHY0>, +- <&ccu RST_USB_PHY1>, +- <&ccu RST_USB_PHY2>; +- reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; +- status = "disabled"; +- }; +- +- ehci0: usb@1c14000 { +- compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; +- reg = <0x01c14000 0x100>; +- interrupts = <39>; +- clocks = <&ccu CLK_AHB_EHCI0>; +- phys = <&usbphy 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci0: usb@1c14400 { +- compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; +- reg = <0x01c14400 0x100>; +- interrupts = <64>; +- clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; +- phys = <&usbphy 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- crypto: crypto-engine@1c15000 { +- compatible = "allwinner,sun4i-a10-crypto"; +- reg = <0x01c15000 0x1000>; +- interrupts = <86>; +- clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; +- clock-names = "ahb", "mod"; +- }; +- +- hdmi: hdmi@1c16000 { +- compatible = "allwinner,sun4i-a10-hdmi"; +- reg = <0x01c16000 0x1000>; +- interrupts = <58>; +- clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, +- <&ccu CLK_PLL_VIDEO0_2X>, +- <&ccu CLK_PLL_VIDEO1_2X>; +- clock-names = "ahb", "mod", "pll-0", "pll-1"; +- dmas = <&dma SUN4I_DMA_NORMAL 16>, +- <&dma SUN4I_DMA_NORMAL 16>, +- <&dma SUN4I_DMA_DEDICATED 24>; +- dma-names = "ddc-tx", "ddc-rx", "audio-tx"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- hdmi_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- hdmi_in_tcon0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&tcon0_out_hdmi>; +- }; +- +- hdmi_in_tcon1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tcon1_out_hdmi>; +- }; +- }; +- +- hdmi_out: port@1 { +- reg = <1>; +- }; +- }; +- }; +- +- spi2: spi@1c17000 { +- compatible = "allwinner,sun4i-a10-spi"; +- reg = <0x01c17000 0x1000>; +- interrupts = <12>; +- clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; +- clock-names = "ahb", "mod"; +- dmas = <&dma SUN4I_DMA_DEDICATED 29>, +- <&dma SUN4I_DMA_DEDICATED 28>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- ahci: sata@1c18000 { +- compatible = "allwinner,sun4i-a10-ahci"; +- reg = <0x01c18000 0x1000>; +- interrupts = <56>; +- clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; +- status = "disabled"; +- }; +- +- ehci1: usb@1c1c000 { +- compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; +- reg = <0x01c1c000 0x100>; +- interrupts = <40>; +- clocks = <&ccu CLK_AHB_EHCI1>; +- phys = <&usbphy 2>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci1: usb@1c1c400 { +- compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; +- reg = <0x01c1c400 0x100>; +- interrupts = <65>; +- clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; +- phys = <&usbphy 2>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- csi1: csi@1c1d000 { +- compatible = "allwinner,sun4i-a10-csi1"; +- reg = <0x01c1d000 0x1000>; +- interrupts = <43>; +- clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>; +- clock-names = "bus", "ram"; +- resets = <&ccu RST_CSI1>; +- status = "disabled"; +- }; +- +- spi3: spi@1c1f000 { +- compatible = "allwinner,sun4i-a10-spi"; +- reg = <0x01c1f000 0x1000>; +- interrupts = <50>; +- clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; +- clock-names = "ahb", "mod"; +- dmas = <&dma SUN4I_DMA_DEDICATED 31>, +- <&dma SUN4I_DMA_DEDICATED 30>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- ccu: clock@1c20000 { +- compatible = "allwinner,sun4i-a10-ccu"; +- reg = <0x01c20000 0x400>; +- clocks = <&osc24M>, <&osc32k>; +- clock-names = "hosc", "losc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- intc: interrupt-controller@1c20400 { +- compatible = "allwinner,sun4i-a10-ic"; +- reg = <0x01c20400 0x400>; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- pio: pinctrl@1c20800 { +- compatible = "allwinner,sun4i-a10-pinctrl"; +- reg = <0x01c20800 0x400>; +- interrupts = <28>; +- clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; +- clock-names = "apb", "hosc", "losc"; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <3>; +- #gpio-cells = <3>; +- +- can0_ph_pins: can0-ph-pins { +- pins = "PH20", "PH21"; +- function = "can"; +- }; +- +- /omit-if-no-ref/ +- csi1_8bits_pg_pins: csi1-8bits-pg-pins { +- pins = "PG0", "PG2", "PG3", "PG4", "PG5", +- "PG6", "PG7", "PG8", "PG9", "PG10", +- "PG11"; +- function = "csi1"; +- }; +- +- /omit-if-no-ref/ +- csi1_24bits_ph_pins: csi1-24bits-ph-pins { +- pins = "PH0", "PH1", "PH2", "PH3", "PH4", +- "PH5", "PH6", "PH7", "PH8", "PH9", +- "PH10", "PH11", "PH12", "PH13", "PH14", +- "PH15", "PH16", "PH17", "PH18", "PH19", +- "PH20", "PH21", "PH22", "PH23", "PH24", +- "PH25", "PH26", "PH27"; +- function = "csi1"; +- }; +- +- /omit-if-no-ref/ +- csi1_clk_pg_pin: csi1-clk-pg-pin { +- pins = "PG1"; +- function = "csi1"; +- }; +- +- emac_pins: emac0-pins { +- pins = "PA0", "PA1", "PA2", +- "PA3", "PA4", "PA5", "PA6", +- "PA7", "PA8", "PA9", "PA10", +- "PA11", "PA12", "PA13", "PA14", +- "PA15", "PA16"; +- function = "emac"; +- }; +- +- i2c0_pins: i2c0-pins { +- pins = "PB0", "PB1"; +- function = "i2c0"; +- }; +- +- i2c1_pins: i2c1-pins { +- pins = "PB18", "PB19"; +- function = "i2c1"; +- }; +- +- i2c2_pins: i2c2-pins { +- pins = "PB20", "PB21"; +- function = "i2c2"; +- }; +- +- ir0_rx_pins: ir0-rx-pin { +- pins = "PB4"; +- function = "ir0"; +- }; +- +- ir0_tx_pins: ir0-tx-pin { +- pins = "PB3"; +- function = "ir0"; +- }; +- +- ir1_rx_pins: ir1-rx-pin { +- pins = "PB23"; +- function = "ir1"; +- }; +- +- ir1_tx_pins: ir1-tx-pin { +- pins = "PB22"; +- function = "ir1"; +- }; +- +- mmc0_pins: mmc0-pins { +- pins = "PF0", "PF1", "PF2", +- "PF3", "PF4", "PF5"; +- function = "mmc0"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- ps2_ch0_pins: ps2-ch0-pins { +- pins = "PI20", "PI21"; +- function = "ps2"; +- }; +- +- ps2_ch1_ph_pins: ps2-ch1-ph-pins { +- pins = "PH12", "PH13"; +- function = "ps2"; +- }; +- +- pwm0_pin: pwm0-pin { +- pins = "PB2"; +- function = "pwm"; +- }; +- +- pwm1_pin: pwm1-pin { +- pins = "PI3"; +- function = "pwm"; +- }; +- +- spdif_tx_pin: spdif-tx-pin { +- pins = "PB13"; +- function = "spdif"; +- bias-pull-up; +- }; +- +- spi0_pi_pins: spi0-pi-pins { +- pins = "PI11", "PI12", "PI13"; +- function = "spi0"; +- }; +- +- spi0_cs0_pi_pin: spi0-cs0-pi-pin { +- pins = "PI10"; +- function = "spi0"; +- }; +- +- spi1_pins: spi1-pins { +- pins = "PI17", "PI18", "PI19"; +- function = "spi1"; +- }; +- +- spi1_cs0_pin: spi1-cs0-pin { +- pins = "PI16"; +- function = "spi1"; +- }; +- +- spi2_pb_pins: spi2-pb-pins { +- pins = "PB15", "PB16", "PB17"; +- function = "spi2"; +- }; +- +- spi2_pc_pins: spi2-pc-pins { +- pins = "PC20", "PC21", "PC22"; +- function = "spi2"; +- }; +- +- spi2_cs0_pb_pin: spi2-cs0-pb-pin { +- pins = "PB14"; +- function = "spi2"; +- }; +- +- spi2_cs0_pc_pins: spi2-cs0-pc-pin { +- pins = "PC19"; +- function = "spi2"; +- }; +- +- uart0_pb_pins: uart0-pb-pins { +- pins = "PB22", "PB23"; +- function = "uart0"; +- }; +- +- uart0_pf_pins: uart0-pf-pins { +- pins = "PF2", "PF4"; +- function = "uart0"; +- }; +- +- uart1_pins: uart1-pins { +- pins = "PA10", "PA11"; +- function = "uart1"; +- }; +- }; +- +- timer@1c20c00 { +- compatible = "allwinner,sun4i-a10-timer"; +- reg = <0x01c20c00 0x90>; +- interrupts = <22>, +- <23>, +- <24>, +- <25>, +- <67>, +- <68>; +- clocks = <&osc24M>; +- }; +- +- wdt: watchdog@1c20c90 { +- compatible = "allwinner,sun4i-a10-wdt"; +- reg = <0x01c20c90 0x10>; +- interrupts = <24>; +- clocks = <&osc24M>; +- }; +- +- rtc: rtc@1c20d00 { +- compatible = "allwinner,sun4i-a10-rtc"; +- reg = <0x01c20d00 0x20>; +- interrupts = <24>; +- }; +- +- pwm: pwm@1c20e00 { +- compatible = "allwinner,sun4i-a10-pwm"; +- reg = <0x01c20e00 0xc>; +- clocks = <&osc24M>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- spdif: spdif@1c21000 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun4i-a10-spdif"; +- reg = <0x01c21000 0x400>; +- interrupts = <13>; +- clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; +- clock-names = "apb", "spdif"; +- dmas = <&dma SUN4I_DMA_NORMAL 2>, +- <&dma SUN4I_DMA_NORMAL 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ir0: ir@1c21800 { +- compatible = "allwinner,sun4i-a10-ir"; +- clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; +- clock-names = "apb", "ir"; +- interrupts = <5>; +- reg = <0x01c21800 0x40>; +- status = "disabled"; +- }; +- +- ir1: ir@1c21c00 { +- compatible = "allwinner,sun4i-a10-ir"; +- clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; +- clock-names = "apb", "ir"; +- interrupts = <6>; +- reg = <0x01c21c00 0x40>; +- status = "disabled"; +- }; +- +- i2s0: i2s@1c22400 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun4i-a10-i2s"; +- reg = <0x01c22400 0x400>; +- interrupts = <16>; +- clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; +- clock-names = "apb", "mod"; +- dmas = <&dma SUN4I_DMA_NORMAL 3>, +- <&dma SUN4I_DMA_NORMAL 3>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- lradc: lradc@1c22800 { +- compatible = "allwinner,sun4i-a10-lradc-keys"; +- reg = <0x01c22800 0x100>; +- interrupts = <31>; +- status = "disabled"; +- }; +- +- codec: codec@1c22c00 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun4i-a10-codec"; +- reg = <0x01c22c00 0x40>; +- interrupts = <30>; +- clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; +- clock-names = "apb", "codec"; +- dmas = <&dma SUN4I_DMA_NORMAL 19>, +- <&dma SUN4I_DMA_NORMAL 19>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sid: eeprom@1c23800 { +- compatible = "allwinner,sun4i-a10-sid"; +- reg = <0x01c23800 0x10>; +- }; +- +- rtp: rtp@1c25000 { +- compatible = "allwinner,sun4i-a10-ts"; +- reg = <0x01c25000 0x100>; +- interrupts = <29>; +- #thermal-sensor-cells = <0>; +- }; +- +- uart0: serial@1c28000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28000 0x400>; +- interrupts = <1>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART0>; +- status = "disabled"; +- }; +- +- uart1: serial@1c28400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28400 0x400>; +- interrupts = <2>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART1>; +- status = "disabled"; +- }; +- +- uart2: serial@1c28800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28800 0x400>; +- interrupts = <3>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART2>; +- status = "disabled"; +- }; +- +- uart3: serial@1c28c00 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28c00 0x400>; +- interrupts = <4>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART3>; +- status = "disabled"; +- }; +- +- uart4: serial@1c29000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c29000 0x400>; +- interrupts = <17>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART4>; +- status = "disabled"; +- }; +- +- uart5: serial@1c29400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c29400 0x400>; +- interrupts = <18>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART5>; +- status = "disabled"; +- }; +- +- uart6: serial@1c29800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c29800 0x400>; +- interrupts = <19>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART6>; +- status = "disabled"; +- }; +- +- uart7: serial@1c29c00 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c29c00 0x400>; +- interrupts = <20>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART7>; +- status = "disabled"; +- }; +- +- ps20: ps2@1c2a000 { +- compatible = "allwinner,sun4i-a10-ps2"; +- reg = <0x01c2a000 0x400>; +- interrupts = <62>; +- clocks = <&ccu CLK_APB1_PS20>; +- status = "disabled"; +- }; +- +- ps21: ps2@1c2a400 { +- compatible = "allwinner,sun4i-a10-ps2"; +- reg = <0x01c2a400 0x400>; +- interrupts = <63>; +- clocks = <&ccu CLK_APB1_PS21>; +- status = "disabled"; +- }; +- +- i2c0: i2c@1c2ac00 { +- compatible = "allwinner,sun4i-a10-i2c"; +- reg = <0x01c2ac00 0x400>; +- interrupts = <7>; +- clocks = <&ccu CLK_APB1_I2C0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c1: i2c@1c2b000 { +- compatible = "allwinner,sun4i-a10-i2c"; +- reg = <0x01c2b000 0x400>; +- interrupts = <8>; +- clocks = <&ccu CLK_APB1_I2C1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c2: i2c@1c2b400 { +- compatible = "allwinner,sun4i-a10-i2c"; +- reg = <0x01c2b400 0x400>; +- interrupts = <9>; +- clocks = <&ccu CLK_APB1_I2C2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- can0: can@1c2bc00 { +- compatible = "allwinner,sun4i-a10-can"; +- reg = <0x01c2bc00 0x400>; +- interrupts = <26>; +- clocks = <&ccu CLK_APB1_CAN>; +- status = "disabled"; +- }; +- +- mali: gpu@1c40000 { +- compatible = "allwinner,sun4i-a10-mali", "arm,mali-400"; +- reg = <0x01c40000 0x10000>; +- interrupts = <69>, +- <70>, +- <71>, +- <72>, +- <73>; +- interrupt-names = "gp", +- "gpmmu", +- "pp0", +- "ppmmu0", +- "pmu"; +- clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; +- clock-names = "bus", "core"; +- resets = <&ccu RST_GPU>; +- +- assigned-clocks = <&ccu CLK_GPU>; +- assigned-clock-rates = <384000000>; +- }; +- +- fe0: display-frontend@1e00000 { +- compatible = "allwinner,sun4i-a10-display-frontend"; +- reg = <0x01e00000 0x20000>; +- interrupts = <47>; +- clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, +- <&ccu CLK_DRAM_DE_FE0>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&ccu RST_DE_FE0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- fe0_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- fe0_out_be0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&be0_in_fe0>; +- }; +- +- fe0_out_be1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&be1_in_fe0>; +- }; +- }; +- }; +- }; +- +- fe1: display-frontend@1e20000 { +- compatible = "allwinner,sun4i-a10-display-frontend"; +- reg = <0x01e20000 0x20000>; +- interrupts = <48>; +- clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, +- <&ccu CLK_DRAM_DE_FE1>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&ccu RST_DE_FE1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- fe1_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- fe1_out_be0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&be0_in_fe1>; +- }; +- +- fe1_out_be1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&be1_in_fe1>; +- }; +- }; +- }; +- }; +- +- be1: display-backend@1e40000 { +- compatible = "allwinner,sun4i-a10-display-backend"; +- reg = <0x01e40000 0x10000>; +- interrupts = <48>; +- clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, +- <&ccu CLK_DRAM_DE_BE1>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&ccu RST_DE_BE1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- be1_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- be1_in_fe0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&fe0_out_be1>; +- }; +- +- be1_in_fe1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&fe1_out_be1>; +- }; +- }; +- +- be1_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- be1_out_tcon0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&tcon0_in_be1>; +- }; +- +- be1_out_tcon1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tcon1_in_be1>; +- }; +- }; +- }; +- }; +- +- be0: display-backend@1e60000 { +- compatible = "allwinner,sun4i-a10-display-backend"; +- reg = <0x01e60000 0x10000>; +- interrupts = <47>; +- clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, +- <&ccu CLK_DRAM_DE_BE0>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&ccu RST_DE_BE0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- be0_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- be0_in_fe0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&fe0_out_be0>; +- }; +- +- be0_in_fe1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&fe1_out_be0>; +- }; +- }; +- +- be0_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- be0_out_tcon0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&tcon0_in_be0>; +- }; +- +- be0_out_tcon1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tcon1_in_be0>; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-a10s-auxtek-t003.dts b/scripts/dtc/include-prefixes/arm/sun5i-a10s-auxtek-t003.dts +deleted file mode 100644 +index 04b0e6d28769..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-a10s-auxtek-t003.dts ++++ /dev/null +@@ -1,137 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun5i-a10s.dtsi" +-#include "sunxi-common-regulators.dtsi" +-#include +- +-/ { +- model = "Auxtek t003 A10s hdmi tv-stick"; +- compatible = "allwinner,auxtek-t003", "allwinner,sun5i-a10s"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins_t003>; +- +- led { +- label = "t003-tv-dongle:red:usr"; +- gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ +- default-state = "on"; +- }; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp152: pmic@30 { +- compatible = "x-powers,axp152"; +- reg = <0x30>; +- interrupts = <0>; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pio { +- led_pins_t003: led-pin { +- pins = "PB2"; +- function = "gpio_out"; +- drive-strength = <20>; +- }; +-}; +- +-®_usb0_vbus { +- gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ +- status = "okay"; +-}; +- +-®_usb1_vbus { +- gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-a10s-auxtek-t004.dts b/scripts/dtc/include-prefixes/arm/sun5i-a10s-auxtek-t004.dts +deleted file mode 100644 +index 667bc2dc1ea9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-a10s-auxtek-t004.dts ++++ /dev/null +@@ -1,149 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun5i-a10s.dtsi" +-#include "sunxi-common-regulators.dtsi" +-#include +- +-/ { +- model = "Auxtek t004 A10s hdmi tv-stick"; +- compatible = "allwinner,auxtek-t004", "allwinner,sun5i-a10s"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins_t004>; +- +- led { +- label = "t004-tv-dongle:red:usr"; +- gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ +- default-state = "on"; +- }; +- }; +- +- reg_vmmc1: vmmc1 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmc1"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- gpio = <&pio 1 18 GPIO_ACTIVE_HIGH>; /* PB18 */ +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp152: pmic@30 { +- compatible = "x-powers,axp152"; +- reg = <0x30>; +- interrupts = <0>; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vmmc1>; +- bus-width = <4>; +- non-removable; +- cap-sdio-irq; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pio { +- led_pins_t004: led-pin { +- pins = "PB2"; +- function = "gpio_out"; +- drive-strength = <20>; +- }; +-}; +- +-®_usb1_vbus { +- gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */ +- usb1_vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-a10s-mk802.dts b/scripts/dtc/include-prefixes/arm/sun5i-a10s-mk802.dts +deleted file mode 100644 +index d0219404c231..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-a10s-mk802.dts ++++ /dev/null +@@ -1,127 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun5i-a10s.dtsi" +-#include "sunxi-common-regulators.dtsi" +-#include +- +-/ { +- model = "MK802-A10s"; +- compatible = "allwinner,a10s-mk802", "allwinner,sun5i-a10s"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led { +- label = "mk802:red:usr"; +- gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ +- }; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp152: pmic@30 { +- compatible = "x-powers,axp152"; +- reg = <0x30>; +- interrupts = <0>; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-a10s-olinuxino-micro.dts b/scripts/dtc/include-prefixes/arm/sun5i-a10s-olinuxino-micro.dts +deleted file mode 100644 +index 5832bb31fc51..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-a10s-olinuxino-micro.dts ++++ /dev/null +@@ -1,272 +0,0 @@ +-/* +- * Copyright 2013 Maxime Ripard +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun5i-a10s.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Olimex A10s-Olinuxino Micro"; +- compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart2; +- serial2 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins_olinuxino>; +- +- led { +- label = "a10s-olinuxino-micro:green:usr"; +- gpios = <&pio 4 3 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +-}; +- +-&be0 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_pa_pins>; +- phy-handle = <&phy1>; +- status = "okay"; +-}; +- +-&emac_sram { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp152: pmic@30 { +- reg = <0x30>; +- interrupts = <0>; +- }; +-}; +- +-#include "axp152.dtsi" +- +-&i2c1 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c16"; +- pagesize = <16>; +- reg = <0x50>; +- read-only; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&lradc { +- vref-supply = <®_vcc3v0>; +- status = "okay"; +- +- button-191 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <191274>; +- }; +- +- button-392 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <392644>; +- }; +- +- button-601 { +- label = "Menu"; +- linux,code = ; +- channel = <0>; +- voltage = <601151>; +- }; +- +- button-795 { +- label = "Enter"; +- linux,code = ; +- channel = <0>; +- voltage = <795090>; +- }; +- +- button-987 { +- label = "Home"; +- linux,code = ; +- channel = <0>; +- voltage = <987387>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pio { +- led_pins_olinuxino: led-pin { +- pins = "PE3"; +- function = "gpio_out"; +- drive-strength = <20>; +- }; +-}; +- +-®_usb0_vbus { +- gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ +- status = "okay"; +-}; +- +-®_usb1_vbus { +- gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&spi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pb_pins>, +- <&spi2_cs0_pb_pin>; +- status = "okay"; +-}; +- +-&tcon0 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pc_pins>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pg_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-a10s-r7-tv-dongle.dts b/scripts/dtc/include-prefixes/arm/sun5i-a10s-r7-tv-dongle.dts +deleted file mode 100644 +index 964360f0610a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-a10s-r7-tv-dongle.dts ++++ /dev/null +@@ -1,118 +0,0 @@ +-/* +- * Copyright 2014 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun5i-a10s.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- model = "R7 A10s hdmi tv-stick"; +- compatible = "allwinner,r7-tv-dongle", "allwinner,sun5i-a10s"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins_r7>; +- +- led { +- label = "r7-tv-dongle:green:usr"; +- gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&pio { +- led_pins_r7: led-pin { +- pins = "PB2"; +- function = "gpio_out"; +- drive-strength = <20>; +- }; +-}; +- +-®_usb1_vbus { +- gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-a10s-wobo-i5.dts b/scripts/dtc/include-prefixes/arm/sun5i-a10s-wobo-i5.dts +deleted file mode 100644 +index ef8baa992687..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-a10s-wobo-i5.dts ++++ /dev/null +@@ -1,195 +0,0 @@ +-/* +- * Copyright 2015 Jelle van der Waa +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun5i-a10s.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "A10s-Wobo i5"; +- compatible = "wobo,a10s-wobo-i5", "allwinner,sun5i-a10s"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led { +- label = "a10s-wobo-i5:blue:usr"; +- gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- reg_emac_3v3: emac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "emac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <20000>; +- enable-active-high; +- gpio = <&pio 0 2 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_pd_pins>; +- phy-handle = <&phy1>; +- status = "okay"; +-}; +- +-&emac_sram { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupts = <0>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&mdio { +- phy-supply = <®_emac_3v3>; +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_ldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi1"; +-}; +- +-®_ldo4 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi2"; +-}; +- +-®_usb1_vbus { +- gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-a10s.dtsi b/scripts/dtc/include-prefixes/arm/sun5i-a10s.dtsi +deleted file mode 100644 +index 09c486b608b2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-a10s.dtsi ++++ /dev/null +@@ -1,173 +0,0 @@ +-/* +- * Copyright 2013 Maxime Ripard +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This library is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This library is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "sun5i.dtsi" +- +-#include +- +-/ { +- aliases { +- ethernet0 = &emac; +- }; +- +- chosen { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- framebuffer-lcd0-hdmi { +- compatible = "allwinner,simple-framebuffer", +- "simple-framebuffer"; +- allwinner,pipeline = "de_be0-lcd0-hdmi"; +- clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_HDMI>, +- <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DRAM_DE_BE>, +- <&ccu CLK_DE_BE>, <&ccu CLK_HDMI>; +- status = "disabled"; +- }; +- }; +- +- display-engine { +- compatible = "allwinner,sun5i-a10s-display-engine"; +- allwinner,pipelines = <&fe0>; +- }; +- +- soc { +- hdmi: hdmi@1c16000 { +- compatible = "allwinner,sun5i-a10s-hdmi"; +- reg = <0x01c16000 0x1000>; +- interrupts = <58>; +- clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>, +- <&ccu CLK_PLL_VIDEO0_2X>, +- <&ccu CLK_PLL_VIDEO1_2X>; +- clock-names = "ahb", "mod", "pll-0", "pll-1"; +- dmas = <&dma SUN4I_DMA_NORMAL 16>, +- <&dma SUN4I_DMA_NORMAL 16>, +- <&dma SUN4I_DMA_DEDICATED 24>; +- dma-names = "ddc-tx", "ddc-rx", "audio-tx"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- hdmi_in: port@0 { +- reg = <0>; +- +- hdmi_in_tcon0: endpoint { +- remote-endpoint = <&tcon0_out_hdmi>; +- }; +- }; +- +- hdmi_out: port@1 { +- reg = <1>; +- }; +- }; +- }; +- +- pwm: pwm@1c20e00 { +- compatible = "allwinner,sun5i-a10s-pwm"; +- reg = <0x01c20e00 0xc>; +- clocks = <&ccu CLK_HOSC>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- }; +-}; +- +-&ccu { +- compatible = "allwinner,sun5i-a10s-ccu"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +-}; +- +-&pio { +- compatible = "allwinner,sun5i-a10s-pinctrl"; +- +- uart0_pb_pins: uart0-pb-pins { +- pins = "PB19", "PB20"; +- function = "uart0"; +- }; +- +- uart2_pc_pins: uart2-pc-pins { +- pins = "PC18", "PC19"; +- function = "uart2"; +- }; +- +- emac_pa_pins: emac-pa-pins { +- pins = "PA0", "PA1", "PA2", +- "PA3", "PA4", "PA5", "PA6", +- "PA7", "PA8", "PA9", "PA10", +- "PA11", "PA12", "PA13", "PA14", +- "PA15", "PA16"; +- function = "emac"; +- }; +- +- mmc1_pins: mmc1-pins { +- pins = "PG3", "PG4", "PG5", +- "PG6", "PG7", "PG8"; +- function = "mmc1"; +- drive-strength = <30>; +- }; +- +- spi2_pb_pins: spi2-pb-pins { +- pins = "PB12", "PB13", "PB14"; +- function = "spi2"; +- }; +- +- spi2_cs0_pb_pin: spi2-cs0-pb-pin { +- pins = "PB11"; +- function = "spi2"; +- }; +-}; +- +-&tcon0_out { +- tcon0_out_hdmi: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&hdmi_in_tcon0>; +- allwinner,tcon-channel = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-a13-difrnce-dit4350.dts b/scripts/dtc/include-prefixes/arm/sun5i-a13-difrnce-dit4350.dts +deleted file mode 100644 +index 894c4c4f9a1f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-a13-difrnce-dit4350.dts ++++ /dev/null +@@ -1,50 +0,0 @@ +-/* +- * Copyright 2016 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun5i-a13.dtsi" +-#include "sun5i-reference-design-tablet.dtsi" +- +-/ { +- model = "Difrnce DIT4350"; +- compatible = "difrnce,dit4350", "allwinner,sun5i-a13"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-a13-empire-electronix-d709.dts b/scripts/dtc/include-prefixes/arm/sun5i-a13-empire-electronix-d709.dts +deleted file mode 100644 +index d059388d7252..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-a13-empire-electronix-d709.dts ++++ /dev/null +@@ -1,190 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun5i-a13.dtsi" +-#include "sunxi-common-regulators.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "Empire Electronix D709 tablet"; +- compatible = "empire-electronix,d709", "allwinner,sun5i-a13"; +- +- aliases { +- serial0 = &uart1; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; +- brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; +- default-brightness-level = <8>; +- power-supply = <®_vcc3v3>; +- /* TODO: backlight uses axp gpio1 as enable pin */ +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupts = <0>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&i2c1 { +- status = "okay"; +- +- pcf8563: rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +-}; +- +-&lradc { +- vref-supply = <®_ldo2>; +- status = "okay"; +- +- button-200 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <200000>; +- }; +- +- button-400 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <400000>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>; +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- regulator-name = "vdd-int-pll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_ldo3 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-®_usb0_vbus { +- gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pg_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ +- usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_ldo3>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-a13-empire-electronix-m712.dts b/scripts/dtc/include-prefixes/arm/sun5i-a13-empire-electronix-m712.dts +deleted file mode 100644 +index b1e2afd9de52..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-a13-empire-electronix-m712.dts ++++ /dev/null +@@ -1,51 +0,0 @@ +-/* +- * Copyright 2016 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun5i-a13.dtsi" +-#include "sun5i-reference-design-tablet.dtsi" +-#include +- +-/ { +- model = "Empire Electronix M712 tablet"; +- compatible = "empire-electronix,m712", "allwinner,sun5i-a13"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-a13-hsg-h702.dts b/scripts/dtc/include-prefixes/arm/sun5i-a13-hsg-h702.dts +deleted file mode 100644 +index 9b9f2a574851..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-a13-hsg-h702.dts ++++ /dev/null +@@ -1,182 +0,0 @@ +-/* +- * Copyright 2014 Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun5i-a13.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "HSG H702"; +- compatible = "hsg,h702", "allwinner,sun5i-a13"; +- +- aliases { +- serial0 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupts = <0>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- pcf8563: rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&lradc { +- vref-supply = <®_ldo2>; +- status = "okay"; +- +- button-200 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <200000>; +- }; +- +- button-400 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <400000>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-#include "axp209.dtsi" +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_ldo3 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-®_usb0_vbus { +- gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pg_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ +- usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_ldo3>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-a13-inet-98v-rev2.dts b/scripts/dtc/include-prefixes/arm/sun5i-a13-inet-98v-rev2.dts +deleted file mode 100644 +index 439ae3b537df..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-a13-inet-98v-rev2.dts ++++ /dev/null +@@ -1,50 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun5i-a13.dtsi" +-#include "sun5i-reference-design-tablet.dtsi" +- +-/ { +- model = "INet-98V Rev 02"; +- compatible = "primux,inet98v-rev2", "allwinner,sun5i-a13"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-a13-licheepi-one.dts b/scripts/dtc/include-prefixes/arm/sun5i-a13-licheepi-one.dts +deleted file mode 100644 +index 2ce361f8fede..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-a13-licheepi-one.dts ++++ /dev/null +@@ -1,214 +0,0 @@ +-/* +- * Copyright 2016 Icenowy Zheng +- * +- * Based on sun5i-a13-olinuxino.dts, which is +- * Copyright 2012 Maxime Ripard +- * Copyright 2013 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun5i-a13.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Lichee Pi One"; +- compatible = "licheepi,licheepi-one", "allwinner,sun5i-a13"; +- +- aliases { +- serial0 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label ="licheepi:red:usr"; +- gpios = <&pio 2 5 GPIO_ACTIVE_LOW>; +- }; +- +- led-1 { +- label ="licheepi:green:usr"; +- gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- +- led-2 { +- label ="licheepi:blue:usr"; +- gpios = <&pio 2 4 GPIO_ACTIVE_LOW>; +- }; +- +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- compatible = "x-powers,axp209"; +- reg = <0x34>; +- interrupts = <0>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +-}; +- +-&i2c1 { +- status = "disabled"; +-}; +- +-&i2c2 { +- status = "disabled"; +-}; +- +-&lradc { +- vref-supply = <®_ldo2>; +- status = "okay"; +- +- button-984 { +- label = "Home"; +- linux,code = ; +- channel = <0>; +- voltage = <984126>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- broken-cd; +- status = "okay"; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_4bit_pc_pins>; +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- broken-cd; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-#include "axp209.dtsi" +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_ldo3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "csi-1.8v"; +-}; +- +-®_ldo4 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "csi-2.8v"; +-}; +- +-®_usb0_vbus { +- gpio = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pg_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ +- usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_vcc5v0>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-a13-olinuxino-micro.dts b/scripts/dtc/include-prefixes/arm/sun5i-a13-olinuxino-micro.dts +deleted file mode 100644 +index bfe1075e62cc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-a13-olinuxino-micro.dts ++++ /dev/null +@@ -1,141 +0,0 @@ +-/* +- * Copyright 2012 Maxime Ripard +- * Copyright 2013 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun5i-a13.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- model = "Olimex A13-Olinuxino Micro"; +- compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13"; +- +- aliases { +- serial0 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins_olinuxinom>; +- +- led { +- label = "a13-olinuxino-micro:green:power"; +- gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pio { +- led_pins_olinuxinom: led-pin { +- pins = "PG9"; +- function = "gpio_out"; +- drive-strength = <20>; +- }; +-}; +- +-®_usb0_vbus { +- gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-®_usb1_vbus { +- gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pg_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ +- usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-a13-olinuxino.dts b/scripts/dtc/include-prefixes/arm/sun5i-a13-olinuxino.dts +deleted file mode 100644 +index fadeae3cd8bb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-a13-olinuxino.dts ++++ /dev/null +@@ -1,247 +0,0 @@ +-/* +- * Copyright 2012 Maxime Ripard +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun5i-a13.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Olimex A13-Olinuxino"; +- compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13"; +- +- aliases { +- serial0 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins_olinuxino>; +- +- led { +- gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- bridge { +- compatible = "dumb-vga-dac"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- vga_bridge_in: endpoint { +- remote-endpoint = <&tcon0_out_vga>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- vga_bridge_out: endpoint { +- remote-endpoint = <&vga_con_in>; +- }; +- }; +- }; +- }; +- +- vga { +- compatible = "vga-connector"; +- +- port { +- vga_con_in: endpoint { +- remote-endpoint = <&vga_bridge_out>; +- }; +- }; +- }; +-}; +- +-&be0 { +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- compatible = "x-powers,axp209"; +- reg = <0x34>; +- interrupts = <0>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&lradc { +- vref-supply = <®_vcc3v0>; +- status = "okay"; +- +- button-191 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <191274>; +- }; +- +- button-392 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <392644>; +- }; +- +- button-601 { +- label = "Menu"; +- linux,code = ; +- channel = <0>; +- voltage = <601151>; +- }; +- +- button-795 { +- label = "Enter"; +- linux,code = ; +- channel = <0>; +- voltage = <795090>; +- }; +- +- button-987 { +- label = "Home"; +- linux,code = ; +- channel = <0>; +- voltage = <987387>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pio { +- led_pins_olinuxino: led-pin { +- pins = "PG9"; +- function = "gpio_out"; +- drive-strength = <20>; +- }; +-}; +- +-®_usb0_vbus { +- status = "okay"; +- gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +-}; +- +-®_usb1_vbus { +- gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&tcon0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_rgb666_pins>; +- status = "okay"; +-}; +- +-&tcon0_out { +- tcon0_out_vga: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vga_bridge_in>; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pg_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ +- usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-a13-pocketbook-touch-lux-3.dts b/scripts/dtc/include-prefixes/arm/sun5i-a13-pocketbook-touch-lux-3.dts +deleted file mode 100644 +index d60407772e5d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-a13-pocketbook-touch-lux-3.dts ++++ /dev/null +@@ -1,258 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-/* +- * Copyright 2019 Ondrej Jirman +- */ +- +-/dts-v1/; +-#include "sun5i-a13.dtsi" +-#include "sunxi-common-regulators.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "PocketBook Touch Lux 3"; +- compatible = "pocketbook,touch-lux-3", "allwinner,sun5i-a13"; +- +- aliases { +- serial0 = &uart1; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; +- enable-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ +- brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; +- default-brightness-level = <8>; +- power-supply = <®_vcc3v3>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led { +- gpios = <&pio 4 8 GPIO_ACTIVE_LOW>; /* PE8 */ +- default-state = "on"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- label = "GPIO Keys"; +- +- key-right { +- label = "Right"; +- linux,code = ; +- gpios = <&pio 6 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG9 */ +- }; +- +- key-left { +- label = "Left"; +- linux,code = ; +- gpios = <&pio 6 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG10 */ +- }; +- }; +- +- reg_1v8: regulator-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-1v8-nor-ctp"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&pio 2 15 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_1v8_nor: regulator-nor { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-nor"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&pio 2 14 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_1v8>; +- regulator-always-on; +- }; +- +- reg_1v8_ctp: regulator-ctp { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-ctp"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&pio 2 13 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_1v8>; +- }; +- +- reg_3v3_mmc0: regulator-mmc0 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-mmc0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&pio 4 4 GPIO_ACTIVE_LOW>; /* PE4 */ +- vin-supply = <®_vcc3v3>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupts = <0>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&i2c1 { +- status = "okay"; +- +- pcf8563: rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- +- /* Touchpanel is connected here. */ +-}; +- +-&lradc { +- vref-supply = <®_ldo2>; +- status = "okay"; +- +- button-200 { +- label = "Home"; +- linux,code = ; +- channel = <0>; +- voltage = <200000>; +- }; +- +- button-400 { +- label = "Menu"; +- linux,code = ; +- channel = <0>; +- voltage = <400000>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_3v3_mmc0>; +- bus-width = <4>; +- cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ +- status = "okay"; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_4bit_pc_pins>; +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>; +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vdd-int-pll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_ldo3 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +- /* We need this otherwise the LDO3 would overload */ +- regulator-soft-start; +- regulator-ramp-delay = <1600>; +-}; +- +-&spi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pe_pins>, <&spi2_cs0_pe_pin>; +- status = "okay"; +- +- epd_flash: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "macronix,mx25u4033", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <4000000>; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pg_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_ldo3>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-a13-q8-tablet.dts b/scripts/dtc/include-prefixes/arm/sun5i-a13-q8-tablet.dts +deleted file mode 100644 +index f9fc1c8b60b8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-a13-q8-tablet.dts ++++ /dev/null +@@ -1,80 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun5i-a13.dtsi" +-#include "sun5i-reference-design-tablet.dtsi" +- +-/ { +- model = "Q8 A13 Tablet"; +- compatible = "allwinner,q8-a13", "allwinner,sun5i-a13"; +- +- panel: panel { +- compatible = "bananapi,s070wv20-ct16"; +- power-supply = <®_vcc3v3>; +- enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */ +- backlight = <&backlight>; +- +- port { +- panel_input: endpoint { +- remote-endpoint = <&tcon0_out_lcd>; +- }; +- }; +- }; +-}; +- +-&be0 { +- status = "okay"; +-}; +- +-&tcon0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_rgb666_pins>; +- status = "okay"; +-}; +- +-&tcon0_out { +- tcon0_out_lcd: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_input>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-a13-utoo-p66.dts b/scripts/dtc/include-prefixes/arm/sun5i-a13-utoo-p66.dts +deleted file mode 100644 +index be486d28d04f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-a13-utoo-p66.dts ++++ /dev/null +@@ -1,116 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun5i-a13.dtsi" +-#include "sun5i-reference-design-tablet.dtsi" +-#include +- +-/ { +- model = "Utoo P66"; +- compatible = "utoo,p66", "allwinner,sun5i-a13"; +- +- /* The P66 uses the uart pins as gpios */ +- aliases { +- /delete-property/serial0; +- }; +- +- chosen { +- /delete-property/stdout-path; +- }; +- +- i2c_lcd: i2c { +- /* The lcd panel i2c interface is hooked up via gpios */ +- compatible = "i2c-gpio"; +- sda-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */ +- scl-gpios = <&pio 6 10 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG10 */ +- i2c-gpio,delay-us = <5>; +- }; +-}; +- +-&backlight { +- /* Note levels of 10 / 20% result in backlight off */ +- brightness-levels = <0 30 40 50 60 70 80 90 100>; +- default-brightness-level = <6>; +-}; +- +-&codec { +- allwinner,pa-gpios = <&pio 6 3 GPIO_ACTIVE_HIGH>; /* PG3 */ +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_pins>; +- vmmc-supply = <®_vcc3v3>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +- +- mmccard: mmccard@0 { +- reg = <0>; +- compatible = "mmc-card"; +- broken-hpi; +- }; +-}; +- +-®_usb0_vbus { +- gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ +-}; +- +-&touchscreen { +- compatible = "chipone,icn8318"; +- reg = <0x40>; +- /* The P66 uses a different EINT then the reference design */ +- interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ +- /* The icn8318 binding expects wake-gpios instead of power-gpios */ +- wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ +- touchscreen-size-x = <800>; +- touchscreen-size-y = <480>; +- touchscreen-inverted-x; +- touchscreen-swapped-x-y; +- status = "okay"; +-}; +- +-&uart1 { +- /* The P66 uses the uart pins as gpios */ +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-a13.dtsi b/scripts/dtc/include-prefixes/arm/sun5i-a13.dtsi +deleted file mode 100644 +index 7075e10911d5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-a13.dtsi ++++ /dev/null +@@ -1,119 +0,0 @@ +-/* +- * Copyright 2012 Maxime Ripard +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This library is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This library is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "sun5i.dtsi" +- +-#include +- +-/ { +- thermal-zones { +- cpu-thermal { +- /* milliseconds */ +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&rtp>; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- +- trips { +- cpu_alert0: cpu_alert0 { +- /* milliCelsius */ +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_crit: cpu_crit { +- /* milliCelsius */ +- temperature = <100000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- display-engine { +- compatible = "allwinner,sun5i-a13-display-engine"; +- allwinner,pipelines = <&fe0>; +- }; +- +- soc { +- pwm: pwm@1c20e00 { +- compatible = "allwinner,sun5i-a13-pwm"; +- reg = <0x01c20e00 0xc>; +- clocks = <&ccu CLK_HOSC>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- }; +-}; +- +-&ccu { +- compatible = "allwinner,sun5i-a13-ccu"; +-}; +- +-&cpu0 { +- clock-latency = <244144>; /* 8 32k periods */ +- operating-points = < +- /* kHz uV */ +- 1008000 1400000 +- 912000 1350000 +- 864000 1300000 +- 624000 1200000 +- 576000 1200000 +- 432000 1200000 +- >; +- #cooling-cells = <2>; +-}; +- +-&pio { +- compatible = "allwinner,sun5i-a13-pinctrl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-gr8-chip-pro.dts b/scripts/dtc/include-prefixes/arm/sun5i-gr8-chip-pro.dts +deleted file mode 100644 +index a32cde3e32eb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-gr8-chip-pro.dts ++++ /dev/null +@@ -1,238 +0,0 @@ +-/* +- * Copyright 2016 Free Electrons +- * Copyright 2016 NextThing Co +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun5i-gr8.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +-#include +- +-/ { +- model = "NextThing C.H.I.P. Pro"; +- compatible = "nextthing,chip-pro", "nextthing,gr8"; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- status { +- label = "chip-pro:white:status"; +- gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- mmc0_pwrseq: mmc0_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ +- }; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- +- /* +- * The interrupt is routed through the "External Fast +- * Interrupt Request" pin (ball G13 of the module) +- * directly to the main interrupt controller, without +- * any other controller interfering. +- */ +- interrupts = <0>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&i2c1 { +- status = "disabled"; +-}; +- +-&i2s0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s0_mclk_pin>, <&i2s0_data_pins>; +- status = "disabled"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&mmc0_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&nfc { +- pinctrl-names = "default"; +- pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- allwinner,rb = <0>; +- nand-ecc-mode = "hw"; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>, <&pwm1_pins>; +- status = "disabled"; +-}; +- +-®_dcdc2 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +- regulator-always-on; +-}; +- +-®_dcdc3 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-sys"; +- regulator-always-on; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "avcc"; +- regulator-always-on; +-}; +- +-/* +- * Both LDO3 and LDO4 are used in parallel to power up the +- * WiFi/BT chip. +- */ +-®_ldo3 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-1"; +- regulator-always-on; +-}; +- +-®_ldo4 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-2"; +- regulator-always-on; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pins>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pd_pins>, <&uart2_cts_rts_pd_pins>; +- status = "disabled"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pg_pins>, <&uart3_cts_rts_pg_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- /* +- * The CHIP Pro doesn't have a controllable VBUS, nor does it +- * have any 5v rail on the board itself. +- * +- * If one wants to use it as a true OTG port, it should be +- * done in the baseboard, and its DT / overlay will add it. +- */ +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb1_vbus-supply = <®_vcc5v0>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-gr8-evb.dts b/scripts/dtc/include-prefixes/arm/sun5i-gr8-evb.dts +deleted file mode 100644 +index f4fe258ef06d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-gr8-evb.dts ++++ /dev/null +@@ -1,333 +0,0 @@ +-/* +- * Copyright 2016 Free Electrons +- * Copyright 2016 NextThing Co +- * +- * Mylène Josserand +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun5i-gr8.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +-#include +- +-/ { +- model = "NextThing GR8-EVB"; +- compatible = "nextthing,gr8-evb", "nextthing,gr8"; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- serial0 = &uart1; +- serial1 = &uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 10000 0>; +- enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; +- power-supply = <®_vcc3v3>; +- brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; +- default-brightness-level = <8>; +- }; +- +- sound-analog { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "gr8-evb-wm8978"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,mclk-fs = <512>; +- +- simple-audio-card,cpu { +- sound-dai = <&i2s0>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&wm8978>; +- }; +- }; +- +- sound-spdif { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "On-board SPDIF"; +- +- simple-audio-card,cpu { +- sound-dai = <&spdif>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&spdif_out>; +- }; +- }; +- +- spdif_out: spdif-out { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- }; +-}; +- +-&be0 { +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- +- /* +- * The interrupt is routed through the "External Fast +- * Interrupt Request" pin (ball G13 of the module) +- * directly to the main interrupt controller, without +- * any other controller interfering. +- */ +- interrupts = <0>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&i2c1 { +- status = "okay"; +- +- wm8978: codec@1a { +- #sound-dai-cells = <0>; +- compatible = "wlf,wm8978"; +- reg = <0x1a>; +- }; +- +- pcf8563: rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2s0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s0_mclk_pin>, <&i2s0_data_pins>; +- status = "okay"; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pin>; +- status = "okay"; +-}; +- +-&lradc { +- vref-supply = <®_ldo2>; +- status = "okay"; +- +- button-190 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <190000>; +- }; +- +- button-390 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <390000>; +- }; +- +- button-600 { +- label = "Menu"; +- linux,code = ; +- channel = <0>; +- voltage = <600000>; +- }; +- +- button-800 { +- label = "Search"; +- linux,code = ; +- channel = <0>; +- voltage = <800000>; +- }; +- +- button-980 { +- label = "Home"; +- linux,code = ; +- channel = <0>; +- voltage = <980000>; +- }; +- +- button-1180 { +- label = "Esc"; +- linux,code = ; +- channel = <0>; +- voltage = <1180000>; +- }; +- +- button-1400 { +- label = "Enter"; +- linux,code = ; +- channel = <0>; +- voltage = <1400000>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ +- status = "okay"; +-}; +- +-&nfc { +- pinctrl-names = "default"; +- pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; +- +- /* MLC Support sucks for now */ +- status = "disabled"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>; +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +- regulator-always-on; +-}; +- +-®_dcdc3 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-sys"; +- regulator-always-on; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "avcc"; +- regulator-always-on; +-}; +- +-®_usb1_vbus { +- gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&rtp { +- allwinner,ts-attached; +-}; +- +-&spdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&spdif_tx_pin>; +- status = "okay"; +-}; +- +-&tve0 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- /* +- * The GR8-EVB has a somewhat interesting design. There's a +- * pin supposed to control VBUS, an ID pin, a VBUS detect pin, +- * so everything should work just fine. +- * +- * Except that the pin supposed to control VBUS is not +- * connected to any controllable output, neither to the SoC +- * through a GPIO or to the PMIC, and it is pulled down, +- * meaning that we will never be able to enable VBUS on this +- * board. +- */ +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ +- usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb1_vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-gr8.dtsi b/scripts/dtc/include-prefixes/arm/sun5i-gr8.dtsi +deleted file mode 100644 +index 98a8fd5e89e8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-gr8.dtsi ++++ /dev/null +@@ -1,126 +0,0 @@ +-/* +- * Copyright 2016 Mylène Josserand +- * +- * Mylène Josserand +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This library is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This library is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "sun5i.dtsi" +- +-#include +-#include +-#include +- +-/ { +- display-engine { +- compatible = "allwinner,sun5i-a13-display-engine"; +- allwinner,pipelines = <&fe0>; +- }; +- +- soc { +- pwm: pwm@1c20e00 { +- compatible = "allwinner,sun5i-a10s-pwm"; +- reg = <0x01c20e00 0xc>; +- clocks = <&ccu CLK_HOSC>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- spdif: spdif@1c21000 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun4i-a10-spdif"; +- reg = <0x01c21000 0x400>; +- interrupts = <13>; +- clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; +- clock-names = "apb", "spdif"; +- dmas = <&dma SUN4I_DMA_NORMAL 2>, +- <&dma SUN4I_DMA_NORMAL 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2s0: i2s@1c22400 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun4i-a10-i2s"; +- reg = <0x01c22400 0x400>; +- interrupts = <16>; +- clocks = <&ccu CLK_APB0_I2S>, <&ccu CLK_I2S>; +- clock-names = "apb", "mod"; +- dmas = <&dma SUN4I_DMA_NORMAL 3>, +- <&dma SUN4I_DMA_NORMAL 3>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- }; +-}; +- +-&ccu { +- compatible = "nextthing,gr8-ccu"; +-}; +- +-&pio { +- compatible = "nextthing,gr8-pinctrl"; +- +- i2s0_data_pins: i2s0-data-pins { +- pins = "PB6", "PB7", "PB8", "PB9"; +- function = "i2s0"; +- }; +- +- i2s0_mclk_pin: i2s0-mclk-pin { +- pins = "PB5"; +- function = "i2s0"; +- }; +- +- pwm1_pins: pwm1-pin { +- pins = "PG13"; +- function = "pwm1"; +- }; +- +- spdif_tx_pin: spdif-tx-pin { +- pins = "PB10"; +- function = "spdif"; +- bias-pull-up; +- }; +- +- uart1_cts_rts_pins: uart1-cts-rts-pins { +- pins = "PG5", "PG6"; +- function = "uart1"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-r8-chip.dts b/scripts/dtc/include-prefixes/arm/sun5i-r8-chip.dts +deleted file mode 100644 +index 4bf4943d4eb7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-r8-chip.dts ++++ /dev/null +@@ -1,276 +0,0 @@ +-/* +- * Copyright 2015 Free Electrons +- * Copyright 2015 NextThing Co +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun5i-r8.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "NextThing C.H.I.P."; +- compatible = "nextthing,chip", "allwinner,sun5i-r8", "allwinner,sun5i-a13"; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- serial0 = &uart1; +- serial1 = &uart3; +- spi0 = &spi2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- status { +- label = "chip:white:status"; +- gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- mmc0_pwrseq: mmc0_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */ +- }; +- +- onewire { +- compatible = "w1-gpio"; +- gpios = <&pio 3 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PD2 */ +- }; +-}; +- +-&be0 { +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- +- /* +- * The interrupt is routed through the "External Fast +- * Interrupt Request" pin (ball G13 of the module) +- * directly to the main interrupt controller, without +- * any other controller interfering. +- */ +- interrupts = <0>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "disabled"; +-}; +- +-&i2c2 { +- status = "okay"; +- +- xio: gpio@38 { +- compatible = "nxp,pcf8574a"; +- reg = <0x38>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-parent = <&pio>; +- interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +-}; +- +-&mmc0_pins { +- bias-pull-up; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&mmc0_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "cpuvdd"; +- regulator-always-on; +-}; +- +-®_dcdc3 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "corevdd"; +- regulator-always-on; +-}; +- +-®_ldo1 { +- regulator-name = "rtcvdd"; +-}; +- +-®_ldo2 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "avcc"; +- regulator-always-on; +-}; +- +-/* +- * Both LDO3 and LDO4 are used in parallel to power up the WiFi/BT +- * Chip. +- * +- * If those are not enabled, the SDIO part will not enumerate, and +- * since there's no way currently to pass DT infos to an SDIO device, +- * we cannot really do better than this ugly hack for now. +- */ +-®_ldo3 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-1"; +- regulator-always-on; +-}; +- +-®_ldo4 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-2"; +- regulator-always-on; +-}; +- +-®_ldo5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-1v8"; +-}; +- +-®_usb0_vbus { +- vin-supply = <®_vcc5v0>; +- gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ +- status = "okay"; +-}; +- +-&spi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pe_pins>; +- status = "disabled"; +-}; +- +-&tcon0 { +- status = "okay"; +-}; +- +-&tve0 { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pg_pins>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pg_pins>, +- <&uart3_cts_rts_pg_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +- +- usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_vcc5v0>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-r8.dtsi b/scripts/dtc/include-prefixes/arm/sun5i-r8.dtsi +deleted file mode 100644 +index de35dbcd1191..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-r8.dtsi ++++ /dev/null +@@ -1,47 +0,0 @@ +-/* +- * Copyright 2015 Free Electrons +- * Copyright 2015 NextThing Co +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "sun5i-a13.dtsi" +- +diff --git a/scripts/dtc/include-prefixes/arm/sun5i-reference-design-tablet.dtsi b/scripts/dtc/include-prefixes/arm/sun5i-reference-design-tablet.dtsi +deleted file mode 100644 +index 6847f66699ac..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i-reference-design-tablet.dtsi ++++ /dev/null +@@ -1,194 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-#include "sunxi-reference-design-tablet.dtsi" +- +-#include +-#include +- +-/ { +- aliases { +- serial0 = &uart1; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; +- brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; +- default-brightness-level = <8>; +- enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; /* AXP GPIO1 */ +- power-supply = <®_vcc3v0>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&codec { +- allwinner,pa-gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */ +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&i2c0 { +- axp209: pmic@34 { +- reg = <0x34>; +- interrupts = <0>; +- }; +-}; +- +-&i2c1 { +- /* +- * The gsl1680 is rated at 400KHz and it will not work reliable at +- * 100KHz, this has been confirmed on multiple different q8 tablets. +- * All other devices on this bus are also rated for 400KHz. +- */ +- clock-frequency = <400000>; +- +- touchscreen: touchscreen@40 { +- reg = <0x40>; +- interrupt-parent = <&pio>; +- interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* EINT11 (PG11) */ +- power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ +- /* Tablet dts must provide reg and compatible */ +- status = "disabled"; +- }; +- +- pcf8563: rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-&lradc { +- vref-supply = <®_ldo2>; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_vcc3v0>; +- bus-width = <4>; +- cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-pll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_ldo3 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-®_usb0_vbus { +- gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pg_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ +- usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_ldo3>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun5i.dtsi b/scripts/dtc/include-prefixes/arm/sun5i.dtsi +deleted file mode 100644 +index 250d6b87ab4d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun5i.dtsi ++++ /dev/null +@@ -1,810 +0,0 @@ +-/* +- * Copyright 2012-2015 Maxime Ripard +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This library is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This library is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&intc>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a8"; +- reg = <0x0>; +- clocks = <&ccu CLK_CPU>; +- }; +- }; +- +- chosen { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- framebuffer-lcd0 { +- compatible = "allwinner,simple-framebuffer", +- "simple-framebuffer"; +- allwinner,pipeline = "de_be0-lcd0"; +- clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, +- <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>; +- status = "disabled"; +- }; +- +- framebuffer-lcd0-tve0 { +- compatible = "allwinner,simple-framebuffer", +- "simple-framebuffer"; +- allwinner,pipeline = "de_be0-lcd0-tve0"; +- clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>, +- <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, +- <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>; +- status = "disabled"; +- }; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- osc24M: clk-24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "osc24M"; +- }; +- +- osc32k: clk-32k { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-output-names = "osc32k"; +- }; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ +- default-pool { +- compatible = "shared-dma-pool"; +- size = <0x6000000>; +- alloc-ranges = <0x40000000 0x10000000>; +- reusable; +- linux,cma-default; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- dma-ranges; +- ranges; +- +- system-control@1c00000 { +- compatible = "allwinner,sun5i-a13-system-control"; +- reg = <0x01c00000 0x30>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- sram_a: sram@0 { +- compatible = "mmio-sram"; +- reg = <0x00000000 0xc000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00000000 0xc000>; +- +- emac_sram: sram-section@8000 { +- compatible = "allwinner,sun5i-a13-sram-a3-a4", +- "allwinner,sun4i-a10-sram-a3-a4"; +- reg = <0x8000 0x4000>; +- status = "disabled"; +- }; +- }; +- +- sram_d: sram@10000 { +- compatible = "mmio-sram"; +- reg = <0x00010000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00010000 0x1000>; +- +- otg_sram: sram-section@0 { +- compatible = "allwinner,sun5i-a13-sram-d", +- "allwinner,sun4i-a10-sram-d"; +- reg = <0x0000 0x1000>; +- status = "disabled"; +- }; +- }; +- +- sram_c: sram@1d00000 { +- compatible = "mmio-sram"; +- reg = <0x01d00000 0xd0000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x01d00000 0xd0000>; +- +- ve_sram: sram-section@0 { +- compatible = "allwinner,sun5i-a13-sram-c1", +- "allwinner,sun4i-a10-sram-c1"; +- reg = <0x000000 0x80000>; +- }; +- }; +- }; +- +- mbus: dram-controller@1c01000 { +- compatible = "allwinner,sun5i-a13-mbus"; +- reg = <0x01c01000 0x1000>; +- clocks = <&ccu CLK_MBUS>; +- #address-cells = <1>; +- #size-cells = <1>; +- dma-ranges = <0x00000000 0x40000000 0x20000000>; +- #interconnect-cells = <1>; +- }; +- +- dma: dma-controller@1c02000 { +- compatible = "allwinner,sun4i-a10-dma"; +- reg = <0x01c02000 0x1000>; +- interrupts = <27>; +- clocks = <&ccu CLK_AHB_DMA>; +- #dma-cells = <2>; +- }; +- +- nfc: nand-controller@1c03000 { +- compatible = "allwinner,sun4i-a10-nand"; +- reg = <0x01c03000 0x1000>; +- interrupts = <37>; +- clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; +- clock-names = "ahb", "mod"; +- dmas = <&dma SUN4I_DMA_DEDICATED 3>; +- dma-names = "rxtx"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spi0: spi@1c05000 { +- compatible = "allwinner,sun4i-a10-spi"; +- reg = <0x01c05000 0x1000>; +- interrupts = <10>; +- clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; +- clock-names = "ahb", "mod"; +- dmas = <&dma SUN4I_DMA_DEDICATED 27>, +- <&dma SUN4I_DMA_DEDICATED 26>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spi1: spi@1c06000 { +- compatible = "allwinner,sun4i-a10-spi"; +- reg = <0x01c06000 0x1000>; +- interrupts = <11>; +- clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; +- clock-names = "ahb", "mod"; +- dmas = <&dma SUN4I_DMA_DEDICATED 9>, +- <&dma SUN4I_DMA_DEDICATED 8>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- tve0: tv-encoder@1c0a000 { +- compatible = "allwinner,sun4i-a10-tv-encoder"; +- reg = <0x01c0a000 0x1000>; +- clocks = <&ccu CLK_AHB_TVE>; +- resets = <&ccu RST_TVE>; +- status = "disabled"; +- +- port { +- +- tve0_in_tcon0: endpoint { +- remote-endpoint = <&tcon0_out_tve0>; +- }; +- }; +- }; +- +- emac: ethernet@1c0b000 { +- compatible = "allwinner,sun4i-a10-emac"; +- reg = <0x01c0b000 0x1000>; +- interrupts = <55>; +- clocks = <&ccu CLK_AHB_EMAC>; +- allwinner,sram = <&emac_sram 1>; +- status = "disabled"; +- }; +- +- mdio: mdio@1c0b080 { +- compatible = "allwinner,sun4i-a10-mdio"; +- reg = <0x01c0b080 0x14>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- tcon0: lcd-controller@1c0c000 { +- compatible = "allwinner,sun5i-a13-tcon"; +- reg = <0x01c0c000 0x1000>; +- interrupts = <44>; +- dmas = <&dma SUN4I_DMA_DEDICATED 14>; +- resets = <&ccu RST_LCD>; +- reset-names = "lcd"; +- clocks = <&ccu CLK_AHB_LCD>, +- <&ccu CLK_TCON_CH0>, +- <&ccu CLK_TCON_CH1>; +- clock-names = "ahb", +- "tcon-ch0", +- "tcon-ch1"; +- clock-output-names = "tcon-pixel-clock"; +- #clock-cells = <0>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon0_in: port@0 { +- reg = <0>; +- +- tcon0_in_be0: endpoint { +- remote-endpoint = <&be0_out_tcon0>; +- }; +- }; +- +- tcon0_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tcon0_out_tve0: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tve0_in_tcon0>; +- allwinner,tcon-channel = <1>; +- }; +- }; +- }; +- }; +- +- video-codec@1c0e000 { +- compatible = "allwinner,sun5i-a13-video-engine"; +- reg = <0x01c0e000 0x1000>; +- clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, +- <&ccu CLK_DRAM_VE>; +- clock-names = "ahb", "mod", "ram"; +- resets = <&ccu RST_VE>; +- interrupts = <53>; +- allwinner,sram = <&ve_sram 1>; +- }; +- +- mmc0: mmc@1c0f000 { +- compatible = "allwinner,sun5i-a13-mmc"; +- reg = <0x01c0f000 0x1000>; +- clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; +- clock-names = "ahb", "mmc"; +- interrupts = <32>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc1: mmc@1c10000 { +- compatible = "allwinner,sun5i-a13-mmc"; +- reg = <0x01c10000 0x1000>; +- clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; +- clock-names = "ahb", "mmc"; +- interrupts = <33>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc2: mmc@1c11000 { +- compatible = "allwinner,sun5i-a13-mmc"; +- reg = <0x01c11000 0x1000>; +- clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; +- clock-names = "ahb", "mmc"; +- interrupts = <34>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- usb_otg: usb@1c13000 { +- compatible = "allwinner,sun4i-a10-musb"; +- reg = <0x01c13000 0x0400>; +- clocks = <&ccu CLK_AHB_OTG>; +- interrupts = <38>; +- interrupt-names = "mc"; +- phys = <&usbphy 0>; +- phy-names = "usb"; +- extcon = <&usbphy 0>; +- allwinner,sram = <&otg_sram 1>; +- dr_mode = "otg"; +- status = "disabled"; +- }; +- +- usbphy: phy@1c13400 { +- #phy-cells = <1>; +- compatible = "allwinner,sun5i-a13-usb-phy"; +- reg = <0x01c13400 0x10>, <0x01c14800 0x4>; +- reg-names = "phy_ctrl", "pmu1"; +- clocks = <&ccu CLK_USB_PHY0>; +- clock-names = "usb_phy"; +- resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>; +- reset-names = "usb0_reset", "usb1_reset"; +- status = "disabled"; +- }; +- +- ehci0: usb@1c14000 { +- compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; +- reg = <0x01c14000 0x100>; +- interrupts = <39>; +- clocks = <&ccu CLK_AHB_EHCI>; +- phys = <&usbphy 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci0: usb@1c14400 { +- compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; +- reg = <0x01c14400 0x100>; +- interrupts = <40>; +- clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>; +- phys = <&usbphy 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- crypto: crypto-engine@1c15000 { +- compatible = "allwinner,sun5i-a13-crypto", +- "allwinner,sun4i-a10-crypto"; +- reg = <0x01c15000 0x1000>; +- interrupts = <54>; +- clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; +- clock-names = "ahb", "mod"; +- }; +- +- spi2: spi@1c17000 { +- compatible = "allwinner,sun4i-a10-spi"; +- reg = <0x01c17000 0x1000>; +- interrupts = <12>; +- clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; +- clock-names = "ahb", "mod"; +- dmas = <&dma SUN4I_DMA_DEDICATED 29>, +- <&dma SUN4I_DMA_DEDICATED 28>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- ccu: clock@1c20000 { +- reg = <0x01c20000 0x400>; +- clocks = <&osc24M>, <&osc32k>; +- clock-names = "hosc", "losc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- intc: interrupt-controller@1c20400 { +- compatible = "allwinner,sun4i-a10-ic"; +- reg = <0x01c20400 0x400>; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- pio: pinctrl@1c20800 { +- reg = <0x01c20800 0x400>; +- interrupts = <28>; +- clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; +- clock-names = "apb", "hosc", "losc"; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <3>; +- #gpio-cells = <3>; +- +- emac_pd_pins: emac-pd-pins { +- pins = "PD6", "PD7", "PD10", +- "PD11", "PD12", "PD13", "PD14", +- "PD15", "PD18", "PD19", "PD20", +- "PD21", "PD22", "PD23", "PD24", +- "PD25", "PD26", "PD27"; +- function = "emac"; +- }; +- +- i2c0_pins: i2c0-pins { +- pins = "PB0", "PB1"; +- function = "i2c0"; +- }; +- +- i2c1_pins: i2c1-pins { +- pins = "PB15", "PB16"; +- function = "i2c1"; +- }; +- +- i2c2_pins: i2c2-pins { +- pins = "PB17", "PB18"; +- function = "i2c2"; +- }; +- +- ir0_rx_pin: ir0-rx-pin { +- pins = "PB4"; +- function = "ir0"; +- }; +- +- lcd_rgb565_pins: lcd-rgb565-pins { +- pins = "PD3", "PD4", "PD5", "PD6", "PD7", +- "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", +- "PD19", "PD20", "PD21", "PD22", "PD23", +- "PD24", "PD25", "PD26", "PD27"; +- function = "lcd0"; +- }; +- +- lcd_rgb666_pins: lcd-rgb666-pins { +- pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", +- "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", +- "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", +- "PD24", "PD25", "PD26", "PD27"; +- function = "lcd0"; +- }; +- +- mmc0_pins: mmc0-pins { +- pins = "PF0", "PF1", "PF2", "PF3", +- "PF4", "PF5"; +- function = "mmc0"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc2_4bit_pc_pins: mmc2-4bit-pc-pins { +- pins = "PC6", "PC7", "PC8", "PC9", +- "PC10", "PC11"; +- function = "mmc2"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc2_8bit_pins: mmc2-8bit-pins { +- pins = "PC6", "PC7", "PC8", "PC9", +- "PC10", "PC11", "PC12", "PC13", +- "PC14", "PC15"; +- function = "mmc2"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- nand_pins: nand-pins { +- pins = "PC0", "PC1", "PC2", +- "PC5", "PC8", "PC9", "PC10", +- "PC11", "PC12", "PC13", "PC14", +- "PC15"; +- function = "nand0"; +- }; +- +- nand_cs0_pin: nand-cs0-pin { +- pins = "PC4"; +- function = "nand0"; +- }; +- +- nand_rb0_pin: nand-rb0-pin { +- pins = "PC6"; +- function = "nand0"; +- }; +- +- pwm0_pin: pwm0-pin { +- pins = "PB2"; +- function = "pwm"; +- }; +- +- spi2_pe_pins: spi2-pe-pins { +- pins = "PE1", "PE2", "PE3"; +- function = "spi2"; +- }; +- +- spi2_cs0_pe_pin: spi2-cs0-pe-pin { +- pins = "PE0"; +- function = "spi2"; +- }; +- +- uart1_pe_pins: uart1-pe-pins { +- pins = "PE10", "PE11"; +- function = "uart1"; +- }; +- +- uart1_pg_pins: uart1-pg-pins { +- pins = "PG3", "PG4"; +- function = "uart1"; +- }; +- +- uart2_pd_pins: uart2-pd-pins { +- pins = "PD2", "PD3"; +- function = "uart2"; +- }; +- +- uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins { +- pins = "PD4", "PD5"; +- function = "uart2"; +- }; +- +- uart3_pg_pins: uart3-pg-pins { +- pins = "PG9", "PG10"; +- function = "uart3"; +- }; +- +- uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins { +- pins = "PG11", "PG12"; +- function = "uart3"; +- }; +- }; +- +- timer@1c20c00 { +- compatible = "allwinner,sun4i-a10-timer"; +- reg = <0x01c20c00 0x90>; +- interrupts = <22>, +- <23>, +- <24>, +- <25>, +- <67>, +- <68>; +- clocks = <&ccu CLK_HOSC>; +- }; +- +- wdt: watchdog@1c20c90 { +- compatible = "allwinner,sun4i-a10-wdt"; +- reg = <0x01c20c90 0x10>; +- interrupts = <24>; +- clocks = <&osc24M>; +- }; +- +- ir0: ir@1c21800 { +- compatible = "allwinner,sun4i-a10-ir"; +- clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>; +- clock-names = "apb", "ir"; +- interrupts = <5>; +- reg = <0x01c21800 0x40>; +- status = "disabled"; +- }; +- +- lradc: lradc@1c22800 { +- compatible = "allwinner,sun4i-a10-lradc-keys"; +- reg = <0x01c22800 0x100>; +- interrupts = <31>; +- status = "disabled"; +- }; +- +- codec: codec@1c22c00 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun4i-a10-codec"; +- reg = <0x01c22c00 0x40>; +- interrupts = <30>; +- clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; +- clock-names = "apb", "codec"; +- dmas = <&dma SUN4I_DMA_NORMAL 19>, +- <&dma SUN4I_DMA_NORMAL 19>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sid: eeprom@1c23800 { +- compatible = "allwinner,sun4i-a10-sid"; +- reg = <0x01c23800 0x10>; +- }; +- +- rtp: rtp@1c25000 { +- compatible = "allwinner,sun5i-a13-ts"; +- reg = <0x01c25000 0x100>; +- interrupts = <29>; +- #thermal-sensor-cells = <0>; +- }; +- +- uart0: serial@1c28000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28000 0x400>; +- interrupts = <1>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART0>; +- status = "disabled"; +- }; +- +- uart1: serial@1c28400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28400 0x400>; +- interrupts = <2>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART1>; +- status = "disabled"; +- }; +- +- uart2: serial@1c28800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28800 0x400>; +- interrupts = <3>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART2>; +- status = "disabled"; +- }; +- +- uart3: serial@1c28c00 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28c00 0x400>; +- interrupts = <4>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART3>; +- status = "disabled"; +- }; +- +- i2c0: i2c@1c2ac00 { +- compatible = "allwinner,sun4i-a10-i2c"; +- reg = <0x01c2ac00 0x400>; +- interrupts = <7>; +- clocks = <&ccu CLK_APB1_I2C0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c1: i2c@1c2b000 { +- compatible = "allwinner,sun4i-a10-i2c"; +- reg = <0x01c2b000 0x400>; +- interrupts = <8>; +- clocks = <&ccu CLK_APB1_I2C1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c2: i2c@1c2b400 { +- compatible = "allwinner,sun4i-a10-i2c"; +- reg = <0x01c2b400 0x400>; +- interrupts = <9>; +- clocks = <&ccu CLK_APB1_I2C2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mali: gpu@1c40000 { +- compatible = "allwinner,sun4i-a10-mali", "arm,mali-400"; +- reg = <0x01c40000 0x10000>; +- interrupts = <69>, <70>, <71>, <72>, <73>; +- interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pmu"; +- clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; +- clock-names = "bus", "core"; +- resets = <&ccu RST_GPU>; +- assigned-clocks = <&ccu CLK_GPU>; +- assigned-clock-rates = <320000000>; +- }; +- +- timer@1c60000 { +- compatible = "allwinner,sun5i-a13-hstimer"; +- reg = <0x01c60000 0x1000>; +- interrupts = <82>, <83>; +- clocks = <&ccu CLK_AHB_HSTIMER>; +- }; +- +- fe0: display-frontend@1e00000 { +- compatible = "allwinner,sun5i-a13-display-frontend"; +- reg = <0x01e00000 0x20000>; +- interrupts = <47>; +- clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>, +- <&ccu CLK_DRAM_DE_FE>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&ccu RST_DE_FE>; +- interconnects = <&mbus 19>; +- interconnect-names = "dma-mem"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- fe0_out: port@1 { +- reg = <1>; +- +- fe0_out_be0: endpoint { +- remote-endpoint = <&be0_in_fe0>; +- }; +- }; +- }; +- }; +- +- be0: display-backend@1e60000 { +- compatible = "allwinner,sun5i-a13-display-backend"; +- reg = <0x01e60000 0x10000>; +- interrupts = <47>; +- clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, +- <&ccu CLK_DRAM_DE_BE>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&ccu RST_DE_BE>; +- interconnects = <&mbus 18>; +- interconnect-names = "dma-mem"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- be0_in: port@0 { +- reg = <0>; +- +- be0_in_fe0: endpoint { +- remote-endpoint = <&fe0_out_be0>; +- }; +- }; +- +- be0_out: port@1 { +- reg = <1>; +- +- be0_out_tcon0: endpoint { +- remote-endpoint = <&tcon0_in_be0>; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun6i-a31-app4-evb1.dts b/scripts/dtc/include-prefixes/arm/sun6i-a31-app4-evb1.dts +deleted file mode 100644 +index 32d22025ac99..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun6i-a31-app4-evb1.dts ++++ /dev/null +@@ -1,82 +0,0 @@ +-/* +- * Copyright 2014 Boris Brezillon +- * +- * Boris Brezillon +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun6i-a31.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- model = "Allwinner A31 APP4 EVB1 Evaluation Board"; +- compatible = "allwinner,app4-evb1", "allwinner,sun6i-a31"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- gpio = <&pio 7 27 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ph_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun6i-a31-colombus.dts b/scripts/dtc/include-prefixes/arm/sun6i-a31-colombus.dts +deleted file mode 100644 +index 93a15eaaa8cb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun6i-a31-colombus.dts ++++ /dev/null +@@ -1,130 +0,0 @@ +-/* +- * Copyright 2013 Maxime Ripard +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun6i-a31.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- model = "WITS A31 Colombus Evaluation Board"; +- compatible = "wits,colombus", "allwinner,sun6i-a31"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- i2c_lcd: i2c { +- /* The lcd panel i2c interface is hooked up via gpios */ +- compatible = "i2c-gpio"; +- sda-gpios = <&pio 0 23 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA23 */ +- scl-gpios = <&pio 0 24 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA24 */ +- i2c-gpio,delay-us = <5>; +- }; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii"; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "fail"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +- +- mma8452: mma8452@1d { +- compatible = "fsl,mma8452"; +- reg = <0x1d>; +- interrupt-parent = <&pio>; +- interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PA9 */ +- }; +-}; +- +-&mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v0>; +- bus-width = <4>; +- cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ +- status = "okay"; +-}; +- +-®_usb2_vbus { +- gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ph_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun6i-a31-hummingbird.dts b/scripts/dtc/include-prefixes/arm/sun6i-a31-hummingbird.dts +deleted file mode 100644 +index 236ebfc06192..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun6i-a31-hummingbird.dts ++++ /dev/null +@@ -1,338 +0,0 @@ +-/* +- * Copyright 2014 Maxime Ripard +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun6i-a31.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- model = "Merrii A31 Hummingbird"; +- compatible = "merrii,a31-hummingbird", "allwinner,sun6i-a31"; +- +- aliases { +- rtc0 = &pcf8563; +- rtc1 = &rtc; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- vga-connector { +- compatible = "vga-connector"; +- +- port { +- vga_con_in: endpoint { +- remote-endpoint = <&vga_dac_out>; +- }; +- }; +- }; +- +- vga-dac { +- compatible = "dumb-vga-dac"; +- vdd-supply = <®_vga_3v3>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- vga_dac_in: endpoint { +- remote-endpoint = <&tcon0_out_vga>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- vga_dac_out: endpoint { +- remote-endpoint = <&vga_con_in>; +- }; +- }; +- }; +- }; +- +- reg_vga_3v3: vga_3v3_regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vga-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- enable-active-high; +- gpio = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */ +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */ +- }; +-}; +- +-&codec { +- allwinner,audio-routing = +- "Headphone", "HP", +- "Speaker", "LINEOUT", +- "LINEIN", "Line In", +- "MIC1", "Mic", +- "MIC2", "Headset Mic", +- "Mic", "MBIAS", +- "Headset Mic", "HBIAS"; +- allwinner,pa-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc3>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- /* pull-ups and devices require AXP221 DLDO3 */ +- status = "failed"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +- +- pcf8563: rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +-}; +- +-&ir { +- pinctrl-names = "default"; +- pinctrl-0 = <&s_ir_rx_pin>; +- status = "okay"; +-}; +- +-&mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- reset-gpios = <&pio 0 21 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- reset-deassert-us = <30000>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_aldo1>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&p2wi { +- status = "okay"; +- +- axp22x: pmic@68 { +- compatible = "x-powers,axp221"; +- reg = <0x68>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- x-powers,drive-vbus-en; +- }; +-}; +- +-#include "axp22x.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-®_aldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "avcc"; +-}; +- +-®_dc5ldo { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-3v0"; +-}; +- +-®_dcdc2 { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-gpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc4 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-sys-dll"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_drivevbus { +- regulator-name = "usb0-vbus"; +- status = "okay"; +-}; +- +-®_usb1_vbus { +- gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ +- status = "okay"; +-}; +- +-&tcon0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd0_rgb888_pins>; +-}; +- +-&tcon0_out { +- tcon0_out_vga: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vga_dac_in>; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ph_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ +- usb0_vbus_det-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_drivevbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun6i-a31-i7.dts b/scripts/dtc/include-prefixes/arm/sun6i-a31-i7.dts +deleted file mode 100644 +index 744723d956f0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun6i-a31-i7.dts ++++ /dev/null +@@ -1,178 +0,0 @@ +-/* +- * Copyright 2015 Marcus Cooper +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun6i-a31.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- model = "Mele I7 Quad top set box"; +- compatible = "mele,i7", "allwinner,sun6i-a31"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led { +- label = "i7:blue:usr"; +- gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "On-board SPDIF"; +- simple-audio-card,cpu { +- sound-dai = <&spdif>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&spdif_out>; +- }; +- }; +- +- spdif_out: spdif-out { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- }; +-}; +- +-&codec { +- allwinner,audio-routing = +- "Headphone", "HP"; +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_mii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "mii"; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&ir { +- pinctrl-names = "default"; +- pinctrl-0 = <&s_ir_rx_pin>; +- status = "okay"; +-}; +- +-&mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ +- status = "okay"; +-}; +- +-®_usb1_vbus { +- gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&spdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&spdif_tx_pin>; +- status = "okay"; +-}; +- +-&tcon0 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ph_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun6i-a31-m9.dts b/scripts/dtc/include-prefixes/arm/sun6i-a31-m9.dts +deleted file mode 100644 +index 7d2eaaf5c33e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun6i-a31-m9.dts ++++ /dev/null +@@ -1,212 +0,0 @@ +-/* +- * Copyright 2014 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun6i-a31.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- model = "Mele M9 top set box"; +- compatible = "mele,m9", "allwinner,sun6i-a31"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led { +- label = "m9:blue:pwr"; +- gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc3>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_mii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "mii"; +- phy-supply = <®_dldo1>; +- status = "okay"; +-}; +- +-&ir { +- pinctrl-names = "default"; +- pinctrl-0 = <&s_ir_rx_pin>; +- status = "okay"; +-}; +- +-&mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ +- status = "okay"; +-}; +- +-&p2wi { +- status = "okay"; +- +- axp22x: pmic@68 { +- compatible = "x-powers,axp221"; +- reg = <0x68>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- }; +-}; +- +-#include "axp22x.dtsi" +- +-®_aldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "avcc"; +-}; +- +-®_dc5ldo { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-cpus"; /* This is an educated guess */ +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_dcdc2 { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-gpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc4 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-sys-dll"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-ethernet-phy"; +-}; +- +-/* +- * Both reg_usb1_vbus and reg_dldo4 need to be on for the hub attached +- * to usb1 to work, and we can list only one usb1_vbus-supply, so dldo4 is +- * marked as regulator-always-on. +- */ +-®_dldo4 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-usb-hub"; +-}; +- +-®_usb1_vbus { +- gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ph_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_aldo1>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun6i-a31-mele-a1000g-quad.dts b/scripts/dtc/include-prefixes/arm/sun6i-a31-mele-a1000g-quad.dts +deleted file mode 100644 +index 83611434270c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun6i-a31-mele-a1000g-quad.dts ++++ /dev/null +@@ -1,217 +0,0 @@ +-/* +- * Copyright 2014 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun6i-a31.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- model = "Mele A1000G Quad top set box"; +- compatible = "mele,a1000g-quad", "allwinner,sun6i-a31"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led { +- label = "a1000g:blue:pwr"; +- gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc3>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_mii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "mii"; +- phy-supply = <®_dldo1>; +- status = "okay"; +-}; +- +-&ir { +- pinctrl-names = "default"; +- pinctrl-0 = <&s_ir_rx_pin>; +- status = "okay"; +-}; +- +-&mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ +- status = "okay"; +-}; +- +-&p2wi { +- status = "okay"; +- +- axp22x: pmic@68 { +- compatible = "x-powers,axp221"; +- reg = <0x68>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- }; +-}; +- +-#include "axp22x.dtsi" +- +-®_aldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "avcc"; +-}; +- +-®_dc5ldo { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-cpus"; /* This is an educated guess */ +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_dcdc2 { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-gpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc4 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-sys-dll"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-ethernet-phy"; +-}; +- +-/* +- * Both reg_usb1_vbus and reg_dldo4 need to be on for the hub attached +- * to usb1 to work, and we can list only one usb1_vbus-supply, so dldo4 is +- * marked as regulator-always-on. +- */ +-®_dldo4 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-usb-hub"; +-}; +- +-®_usb1_vbus { +- gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ph_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_aldo1>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun6i-a31.dtsi b/scripts/dtc/include-prefixes/arm/sun6i-a31.dtsi +deleted file mode 100644 +index a31f9072bf79..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun6i-a31.dtsi ++++ /dev/null +@@ -1,1425 +0,0 @@ +-/* +- * Copyright 2013 Maxime Ripard +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +- +-#include +-#include +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &gmac; +- }; +- +- chosen { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- simplefb_hdmi: framebuffer-lcd0-hdmi { +- compatible = "allwinner,simple-framebuffer", +- "simple-framebuffer"; +- allwinner,pipeline = "de_be0-lcd0-hdmi"; +- clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, +- <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>, +- <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>, +- <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>; +- status = "disabled"; +- }; +- +- simplefb_lcd: framebuffer-lcd0 { +- compatible = "allwinner,simple-framebuffer", +- "simple-framebuffer"; +- allwinner,pipeline = "de_be0-lcd0"; +- clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, +- <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>, +- <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>; +- status = "disabled"; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- clock-frequency = <24000000>; +- arm,cpu-registers-not-fw-configured; +- }; +- +- cpus { +- enable-method = "allwinner,sun6i-a31"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <0>; +- clocks = <&ccu CLK_CPU>; +- clock-latency = <244144>; /* 8 32k periods */ +- operating-points = < +- /* kHz uV */ +- 1008000 1200000 +- 864000 1200000 +- 720000 1100000 +- 480000 1000000 +- >; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <1>; +- clocks = <&ccu CLK_CPU>; +- clock-latency = <244144>; /* 8 32k periods */ +- operating-points = < +- /* kHz uV */ +- 1008000 1200000 +- 864000 1200000 +- 720000 1100000 +- 480000 1000000 +- >; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <2>; +- clocks = <&ccu CLK_CPU>; +- clock-latency = <244144>; /* 8 32k periods */ +- operating-points = < +- /* kHz uV */ +- 1008000 1200000 +- 864000 1200000 +- 720000 1100000 +- 480000 1000000 +- >; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <3>; +- clocks = <&ccu CLK_CPU>; +- clock-latency = <244144>; /* 8 32k periods */ +- operating-points = < +- /* kHz uV */ +- 1008000 1200000 +- 864000 1200000 +- 720000 1100000 +- 480000 1000000 +- >; +- #cooling-cells = <2>; +- }; +- }; +- +- thermal-zones { +- cpu-thermal { +- /* milliseconds */ +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&rtp>; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- +- trips { +- cpu_alert0: cpu_alert0 { +- /* milliCelsius */ +- temperature = <70000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_crit: cpu_crit { +- /* milliCelsius */ +- temperature = <100000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupts = , +- , +- , +- ; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- osc24M: clk-24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-accuracy = <50000>; +- clock-output-names = "osc24M"; +- }; +- +- osc32k: clk-32k { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-accuracy = <50000>; +- clock-output-names = "ext_osc32k"; +- }; +- +- /* +- * The following two are dummy clocks, placeholders +- * used in the gmac_tx clock. The gmac driver will +- * choose one parent depending on the PHY interface +- * mode, using clk_set_rate auto-reparenting. +- * +- * The actual TX clock rate is not controlled by the +- * gmac_tx clock. +- */ +- mii_phy_tx_clk: clk-mii-phy-tx { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25000000>; +- clock-output-names = "mii_phy_tx"; +- }; +- +- gmac_int_tx_clk: clk-gmac-int-tx { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "gmac_int_tx"; +- }; +- +- gmac_tx_clk: clk@1c200d0 { +- #clock-cells = <0>; +- compatible = "allwinner,sun7i-a20-gmac-clk"; +- reg = <0x01c200d0 0x4>; +- clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; +- clock-output-names = "gmac_tx"; +- }; +- }; +- +- de: display-engine { +- compatible = "allwinner,sun6i-a31-display-engine"; +- allwinner,pipelines = <&fe0>, <&fe1>; +- status = "disabled"; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- dma: dma-controller@1c02000 { +- compatible = "allwinner,sun6i-a31-dma"; +- reg = <0x01c02000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB1_DMA>; +- resets = <&ccu RST_AHB1_DMA>; +- #dma-cells = <1>; +- }; +- +- tcon0: lcd-controller@1c0c000 { +- compatible = "allwinner,sun6i-a31-tcon"; +- reg = <0x01c0c000 0x1000>; +- interrupts = ; +- dmas = <&dma 11>; +- resets = <&ccu RST_AHB1_LCD0>, +- <&ccu RST_AHB1_LVDS>; +- reset-names = "lcd", +- "lvds"; +- clocks = <&ccu CLK_AHB1_LCD0>, +- <&ccu CLK_LCD0_CH0>, +- <&ccu CLK_LCD0_CH1>, +- <&ccu 15>; +- clock-names = "ahb", +- "tcon-ch0", +- "tcon-ch1", +- "lvds-alt"; +- clock-output-names = "tcon0-pixel-clock"; +- #clock-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon0_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- tcon0_in_drc0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&drc0_out_tcon0>; +- }; +- +- tcon0_in_drc1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&drc1_out_tcon0>; +- }; +- }; +- +- tcon0_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tcon0_out_hdmi: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&hdmi_in_tcon0>; +- allwinner,tcon-channel = <1>; +- }; +- }; +- }; +- }; +- +- tcon1: lcd-controller@1c0d000 { +- compatible = "allwinner,sun6i-a31-tcon"; +- reg = <0x01c0d000 0x1000>; +- interrupts = ; +- dmas = <&dma 12>; +- resets = <&ccu RST_AHB1_LCD1>, +- <&ccu RST_AHB1_LVDS>; +- reset-names = "lcd", "lvds"; +- clocks = <&ccu CLK_AHB1_LCD1>, +- <&ccu CLK_LCD1_CH0>, +- <&ccu CLK_LCD1_CH1>, +- <&ccu 15>; +- clock-names = "ahb", +- "tcon-ch0", +- "tcon-ch1", +- "lvds-alt"; +- clock-output-names = "tcon1-pixel-clock"; +- #clock-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon1_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- tcon1_in_drc0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&drc0_out_tcon1>; +- }; +- +- tcon1_in_drc1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&drc1_out_tcon1>; +- }; +- }; +- +- tcon1_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tcon1_out_hdmi: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&hdmi_in_tcon1>; +- allwinner,tcon-channel = <1>; +- }; +- }; +- }; +- }; +- +- mmc0: mmc@1c0f000 { +- compatible = "allwinner,sun7i-a20-mmc"; +- reg = <0x01c0f000 0x1000>; +- clocks = <&ccu CLK_AHB1_MMC0>, +- <&ccu CLK_MMC0>, +- <&ccu CLK_MMC0_OUTPUT>, +- <&ccu CLK_MMC0_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- resets = <&ccu RST_AHB1_MMC0>; +- reset-names = "ahb"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc1: mmc@1c10000 { +- compatible = "allwinner,sun7i-a20-mmc"; +- reg = <0x01c10000 0x1000>; +- clocks = <&ccu CLK_AHB1_MMC1>, +- <&ccu CLK_MMC1>, +- <&ccu CLK_MMC1_OUTPUT>, +- <&ccu CLK_MMC1_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- resets = <&ccu RST_AHB1_MMC1>; +- reset-names = "ahb"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc2: mmc@1c11000 { +- compatible = "allwinner,sun7i-a20-mmc"; +- reg = <0x01c11000 0x1000>; +- clocks = <&ccu CLK_AHB1_MMC2>, +- <&ccu CLK_MMC2>, +- <&ccu CLK_MMC2_OUTPUT>, +- <&ccu CLK_MMC2_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- resets = <&ccu RST_AHB1_MMC2>; +- reset-names = "ahb"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc3: mmc@1c12000 { +- compatible = "allwinner,sun7i-a20-mmc"; +- reg = <0x01c12000 0x1000>; +- clocks = <&ccu CLK_AHB1_MMC3>, +- <&ccu CLK_MMC3>, +- <&ccu CLK_MMC3_OUTPUT>, +- <&ccu CLK_MMC3_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- resets = <&ccu RST_AHB1_MMC3>; +- reset-names = "ahb"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- hdmi: hdmi@1c16000 { +- compatible = "allwinner,sun6i-a31-hdmi"; +- reg = <0x01c16000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>, +- <&ccu CLK_HDMI_DDC>, +- <&ccu CLK_PLL_VIDEO0_2X>, +- <&ccu CLK_PLL_VIDEO1_2X>; +- clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1"; +- resets = <&ccu RST_AHB1_HDMI>; +- dma-names = "ddc-tx", "ddc-rx", "audio-tx"; +- dmas = <&dma 13>, <&dma 13>, <&dma 14>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- hdmi_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- hdmi_in_tcon0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&tcon0_out_hdmi>; +- }; +- +- hdmi_in_tcon1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tcon1_out_hdmi>; +- }; +- }; +- +- hdmi_out: port@1 { +- reg = <1>; +- }; +- }; +- }; +- +- usb_otg: usb@1c19000 { +- compatible = "allwinner,sun6i-a31-musb"; +- reg = <0x01c19000 0x0400>; +- clocks = <&ccu CLK_AHB1_OTG>; +- resets = <&ccu RST_AHB1_OTG>; +- interrupts = ; +- interrupt-names = "mc"; +- phys = <&usbphy 0>; +- phy-names = "usb"; +- extcon = <&usbphy 0>; +- dr_mode = "otg"; +- status = "disabled"; +- }; +- +- usbphy: phy@1c19400 { +- compatible = "allwinner,sun6i-a31-usb-phy"; +- reg = <0x01c19400 0x10>, +- <0x01c1a800 0x4>, +- <0x01c1b800 0x4>; +- reg-names = "phy_ctrl", +- "pmu1", +- "pmu2"; +- clocks = <&ccu CLK_USB_PHY0>, +- <&ccu CLK_USB_PHY1>, +- <&ccu CLK_USB_PHY2>; +- clock-names = "usb0_phy", +- "usb1_phy", +- "usb2_phy"; +- resets = <&ccu RST_USB_PHY0>, +- <&ccu RST_USB_PHY1>, +- <&ccu RST_USB_PHY2>; +- reset-names = "usb0_reset", +- "usb1_reset", +- "usb2_reset"; +- status = "disabled"; +- #phy-cells = <1>; +- }; +- +- ehci0: usb@1c1a000 { +- compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; +- reg = <0x01c1a000 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_AHB1_EHCI0>; +- resets = <&ccu RST_AHB1_EHCI0>; +- phys = <&usbphy 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci0: usb@1c1a400 { +- compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; +- reg = <0x01c1a400 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>; +- resets = <&ccu RST_AHB1_OHCI0>; +- phys = <&usbphy 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ehci1: usb@1c1b000 { +- compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; +- reg = <0x01c1b000 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_AHB1_EHCI1>; +- resets = <&ccu RST_AHB1_EHCI1>; +- phys = <&usbphy 2>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci1: usb@1c1b400 { +- compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; +- reg = <0x01c1b400 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>; +- resets = <&ccu RST_AHB1_OHCI1>; +- phys = <&usbphy 2>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci2: usb@1c1c400 { +- compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; +- reg = <0x01c1c400 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>; +- resets = <&ccu RST_AHB1_OHCI2>; +- status = "disabled"; +- }; +- +- ccu: clock@1c20000 { +- compatible = "allwinner,sun6i-a31-ccu"; +- reg = <0x01c20000 0x400>; +- clocks = <&osc24M>, <&rtc 0>; +- clock-names = "hosc", "losc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pio: pinctrl@1c20800 { +- compatible = "allwinner,sun6i-a31-pinctrl"; +- reg = <0x01c20800 0x400>; +- interrupt-parent = <&r_intc>; +- interrupts = , +- , +- , +- ; +- clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>; +- clock-names = "apb", "hosc", "losc"; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <3>; +- #gpio-cells = <3>; +- +- gmac_gmii_pins: gmac-gmii-pins { +- pins = "PA0", "PA1", "PA2", "PA3", +- "PA4", "PA5", "PA6", "PA7", +- "PA8", "PA9", "PA10", "PA11", +- "PA12", "PA13", "PA14", "PA15", +- "PA16", "PA17", "PA18", "PA19", +- "PA20", "PA21", "PA22", "PA23", +- "PA24", "PA25", "PA26", "PA27"; +- function = "gmac"; +- /* +- * data lines in GMII mode run at 125MHz and +- * might need a higher signal drive strength +- */ +- drive-strength = <30>; +- }; +- +- gmac_mii_pins: gmac-mii-pins { +- pins = "PA0", "PA1", "PA2", "PA3", +- "PA8", "PA9", "PA11", +- "PA12", "PA13", "PA14", "PA19", +- "PA20", "PA21", "PA22", "PA23", +- "PA24", "PA26", "PA27"; +- function = "gmac"; +- }; +- +- gmac_rgmii_pins: gmac-rgmii-pins { +- pins = "PA0", "PA1", "PA2", "PA3", +- "PA9", "PA10", "PA11", +- "PA12", "PA13", "PA14", "PA19", +- "PA20", "PA25", "PA26", "PA27"; +- function = "gmac"; +- /* +- * data lines in RGMII mode use DDR mode +- * and need a higher signal drive strength +- */ +- drive-strength = <40>; +- }; +- +- i2c0_pins: i2c0-pins { +- pins = "PH14", "PH15"; +- function = "i2c0"; +- }; +- +- i2c1_pins: i2c1-pins { +- pins = "PH16", "PH17"; +- function = "i2c1"; +- }; +- +- i2c2_pins: i2c2-pins { +- pins = "PH18", "PH19"; +- function = "i2c2"; +- }; +- +- lcd0_rgb888_pins: lcd0-rgb888-pins { +- pins = "PD0", "PD1", "PD2", "PD3", +- "PD4", "PD5", "PD6", "PD7", +- "PD8", "PD9", "PD10", "PD11", +- "PD12", "PD13", "PD14", "PD15", +- "PD16", "PD17", "PD18", "PD19", +- "PD20", "PD21", "PD22", "PD23", +- "PD24", "PD25", "PD26", "PD27"; +- function = "lcd0"; +- }; +- +- mmc0_pins: mmc0-pins { +- pins = "PF0", "PF1", "PF2", +- "PF3", "PF4", "PF5"; +- function = "mmc0"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc1_pins: mmc1-pins { +- pins = "PG0", "PG1", "PG2", "PG3", +- "PG4", "PG5"; +- function = "mmc1"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc2_4bit_pins: mmc2-4bit-pins { +- pins = "PC6", "PC7", "PC8", "PC9", +- "PC10", "PC11"; +- function = "mmc2"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { +- pins = "PC6", "PC7", "PC8", "PC9", +- "PC10", "PC11", "PC12", +- "PC13", "PC14", "PC15", +- "PC24"; +- function = "mmc2"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins { +- pins = "PC6", "PC7", "PC8", "PC9", +- "PC10", "PC11", "PC12", +- "PC13", "PC14", "PC15", +- "PC24"; +- function = "mmc3"; +- drive-strength = <40>; +- bias-pull-up; +- }; +- +- spdif_tx_pin: spdif-tx-pin { +- pins = "PH28"; +- function = "spdif"; +- }; +- +- uart0_ph_pins: uart0-ph-pins { +- pins = "PH20", "PH21"; +- function = "uart0"; +- }; +- }; +- +- timer@1c20c00 { +- compatible = "allwinner,sun4i-a10-timer"; +- reg = <0x01c20c00 0xa0>; +- interrupts = , +- , +- , +- , +- , +- ; +- clocks = <&osc24M>; +- }; +- +- wdt1: watchdog@1c20ca0 { +- compatible = "allwinner,sun6i-a31-wdt"; +- reg = <0x01c20ca0 0x20>; +- interrupts = ; +- clocks = <&osc24M>; +- }; +- +- spdif: spdif@1c21000 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun6i-a31-spdif"; +- reg = <0x01c21000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>; +- resets = <&ccu RST_APB1_SPDIF>; +- clock-names = "apb", "spdif"; +- dmas = <&dma 2>, <&dma 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2s0: i2s@1c22000 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun6i-a31-i2s"; +- reg = <0x01c22000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>; +- resets = <&ccu RST_APB1_DAUDIO0>; +- clock-names = "apb", "mod"; +- dmas = <&dma 3>, <&dma 3>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2s1: i2s@1c22400 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun6i-a31-i2s"; +- reg = <0x01c22400 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>; +- resets = <&ccu RST_APB1_DAUDIO1>; +- clock-names = "apb", "mod"; +- dmas = <&dma 4>, <&dma 4>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- lradc: lradc@1c22800 { +- compatible = "allwinner,sun4i-a10-lradc-keys"; +- reg = <0x01c22800 0x100>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- status = "disabled"; +- }; +- +- rtp: rtp@1c25000 { +- compatible = "allwinner,sun6i-a31-ts"; +- reg = <0x01c25000 0x100>; +- interrupts = ; +- #thermal-sensor-cells = <0>; +- }; +- +- uart0: serial@1c28000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB2_UART0>; +- resets = <&ccu RST_APB2_UART0>; +- dmas = <&dma 6>, <&dma 6>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart1: serial@1c28400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28400 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB2_UART1>; +- resets = <&ccu RST_APB2_UART1>; +- dmas = <&dma 7>, <&dma 7>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart2: serial@1c28800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28800 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB2_UART2>; +- resets = <&ccu RST_APB2_UART2>; +- dmas = <&dma 8>, <&dma 8>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart3: serial@1c28c00 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28c00 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB2_UART3>; +- resets = <&ccu RST_APB2_UART3>; +- dmas = <&dma 9>, <&dma 9>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart4: serial@1c29000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c29000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB2_UART4>; +- resets = <&ccu RST_APB2_UART4>; +- dmas = <&dma 10>, <&dma 10>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart5: serial@1c29400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c29400 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB2_UART5>; +- resets = <&ccu RST_APB2_UART5>; +- dmas = <&dma 22>, <&dma 22>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c0: i2c@1c2ac00 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2ac00 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB2_I2C0>; +- resets = <&ccu RST_APB2_I2C0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c1: i2c@1c2b000 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2b000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB2_I2C1>; +- resets = <&ccu RST_APB2_I2C1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c2: i2c@1c2b400 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2b400 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB2_I2C2>; +- resets = <&ccu RST_APB2_I2C2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c3: i2c@1c2b800 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2b800 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB2_I2C3>; +- resets = <&ccu RST_APB2_I2C3>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- gmac: ethernet@1c30000 { +- compatible = "allwinner,sun7i-a20-gmac"; +- reg = <0x01c30000 0x1054>; +- interrupts = ; +- interrupt-names = "macirq"; +- clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>; +- clock-names = "stmmaceth", "allwinner_gmac_tx"; +- resets = <&ccu RST_AHB1_EMAC>; +- reset-names = "stmmaceth"; +- snps,pbl = <2>; +- snps,fixed-burst; +- snps,force_sf_dma_mode; +- status = "disabled"; +- +- mdio: mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- crypto: crypto-engine@1c15000 { +- compatible = "allwinner,sun6i-a31-crypto", +- "allwinner,sun4i-a10-crypto"; +- reg = <0x01c15000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>; +- clock-names = "ahb", "mod"; +- resets = <&ccu RST_AHB1_SS>; +- reset-names = "ahb"; +- }; +- +- codec: codec@1c22c00 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun6i-a31-codec"; +- reg = <0x01c22c00 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>; +- clock-names = "apb", "codec"; +- resets = <&ccu RST_APB1_CODEC>; +- dmas = <&dma 15>, <&dma 15>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- timer@1c60000 { +- compatible = "allwinner,sun6i-a31-hstimer", +- "allwinner,sun7i-a20-hstimer"; +- reg = <0x01c60000 0x1000>; +- interrupts = , +- , +- , +- ; +- clocks = <&ccu CLK_AHB1_HSTIMER>; +- resets = <&ccu RST_AHB1_HSTIMER>; +- }; +- +- spi0: spi@1c68000 { +- compatible = "allwinner,sun6i-a31-spi"; +- reg = <0x01c68000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>; +- clock-names = "ahb", "mod"; +- dmas = <&dma 23>, <&dma 23>; +- dma-names = "rx", "tx"; +- resets = <&ccu RST_AHB1_SPI0>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spi1: spi@1c69000 { +- compatible = "allwinner,sun6i-a31-spi"; +- reg = <0x01c69000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>; +- clock-names = "ahb", "mod"; +- dmas = <&dma 24>, <&dma 24>; +- dma-names = "rx", "tx"; +- resets = <&ccu RST_AHB1_SPI1>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spi2: spi@1c6a000 { +- compatible = "allwinner,sun6i-a31-spi"; +- reg = <0x01c6a000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>; +- clock-names = "ahb", "mod"; +- dmas = <&dma 25>, <&dma 25>; +- dma-names = "rx", "tx"; +- resets = <&ccu RST_AHB1_SPI2>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spi3: spi@1c6b000 { +- compatible = "allwinner,sun6i-a31-spi"; +- reg = <0x01c6b000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>; +- clock-names = "ahb", "mod"; +- dmas = <&dma 26>, <&dma 26>; +- dma-names = "rx", "tx"; +- resets = <&ccu RST_AHB1_SPI3>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- gic: interrupt-controller@1c81000 { +- compatible = "arm,gic-400"; +- reg = <0x01c81000 0x1000>, +- <0x01c82000 0x2000>, +- <0x01c84000 0x2000>, +- <0x01c86000 0x2000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = ; +- }; +- +- fe0: display-frontend@1e00000 { +- compatible = "allwinner,sun6i-a31-display-frontend"; +- reg = <0x01e00000 0x20000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>, +- <&ccu CLK_DRAM_FE0>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&ccu RST_AHB1_FE0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- fe0_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- fe0_out_be0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&be0_in_fe0>; +- }; +- +- fe0_out_be1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&be1_in_fe0>; +- }; +- }; +- }; +- }; +- +- fe1: display-frontend@1e20000 { +- compatible = "allwinner,sun6i-a31-display-frontend"; +- reg = <0x01e20000 0x20000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>, +- <&ccu CLK_DRAM_FE1>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&ccu RST_AHB1_FE1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- fe1_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- fe1_out_be0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&be0_in_fe1>; +- }; +- +- fe1_out_be1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&be1_in_fe1>; +- }; +- }; +- }; +- }; +- +- be1: display-backend@1e40000 { +- compatible = "allwinner,sun6i-a31-display-backend"; +- reg = <0x01e40000 0x10000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>, +- <&ccu CLK_DRAM_BE1>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&ccu RST_AHB1_BE1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- be1_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- be1_in_fe0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&fe0_out_be1>; +- }; +- +- be1_in_fe1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&fe1_out_be1>; +- }; +- }; +- +- be1_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- be1_out_drc1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&drc1_in_be1>; +- }; +- }; +- }; +- }; +- +- drc1: drc@1e50000 { +- compatible = "allwinner,sun6i-a31-drc"; +- reg = <0x01e50000 0x10000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>, +- <&ccu CLK_DRAM_DRC1>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&ccu RST_AHB1_DRC1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- drc1_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- drc1_in_be1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&be1_out_drc1>; +- }; +- }; +- +- drc1_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- drc1_out_tcon0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&tcon0_in_drc1>; +- }; +- +- drc1_out_tcon1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tcon1_in_drc1>; +- }; +- }; +- }; +- }; +- +- be0: display-backend@1e60000 { +- compatible = "allwinner,sun6i-a31-display-backend"; +- reg = <0x01e60000 0x10000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>, +- <&ccu CLK_DRAM_BE0>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&ccu RST_AHB1_BE0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- be0_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- be0_in_fe0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&fe0_out_be0>; +- }; +- +- be0_in_fe1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&fe1_out_be0>; +- }; +- }; +- +- be0_out: port@1 { +- reg = <1>; +- +- be0_out_drc0: endpoint { +- remote-endpoint = <&drc0_in_be0>; +- }; +- }; +- }; +- }; +- +- drc0: drc@1e70000 { +- compatible = "allwinner,sun6i-a31-drc"; +- reg = <0x01e70000 0x10000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>, +- <&ccu CLK_DRAM_DRC0>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&ccu RST_AHB1_DRC0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- drc0_in: port@0 { +- reg = <0>; +- +- drc0_in_be0: endpoint { +- remote-endpoint = <&be0_out_drc0>; +- }; +- }; +- +- drc0_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- drc0_out_tcon0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&tcon0_in_drc0>; +- }; +- +- drc0_out_tcon1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tcon1_in_drc0>; +- }; +- }; +- }; +- }; +- +- rtc: rtc@1f00000 { +- #clock-cells = <1>; +- compatible = "allwinner,sun6i-a31-rtc"; +- reg = <0x01f00000 0x54>; +- interrupt-parent = <&r_intc>; +- interrupts = , +- ; +- clocks = <&osc32k>; +- clock-output-names = "osc32k"; +- }; +- +- r_intc: interrupt-controller@1f00c00 { +- compatible = "allwinner,sun6i-a31-r-intc"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x01f00c00 0x400>; +- interrupts = ; +- }; +- +- prcm@1f01400 { +- compatible = "allwinner,sun6i-a31-prcm"; +- reg = <0x01f01400 0x200>; +- +- ar100: ar100_clk { +- compatible = "allwinner,sun6i-a31-ar100-clk"; +- #clock-cells = <0>; +- clocks = <&rtc 0>, <&osc24M>, +- <&ccu CLK_PLL_PERIPH>, +- <&ccu CLK_PLL_PERIPH>; +- clock-output-names = "ar100"; +- }; +- +- ahb0: ahb0_clk { +- compatible = "fixed-factor-clock"; +- #clock-cells = <0>; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&ar100>; +- clock-output-names = "ahb0"; +- }; +- +- apb0: apb0_clk { +- compatible = "allwinner,sun6i-a31-apb0-clk"; +- #clock-cells = <0>; +- clocks = <&ahb0>; +- clock-output-names = "apb0"; +- }; +- +- apb0_gates: apb0_gates_clk { +- compatible = "allwinner,sun6i-a31-apb0-gates-clk"; +- #clock-cells = <1>; +- clocks = <&apb0>; +- clock-output-names = "apb0_pio", "apb0_ir", +- "apb0_timer", "apb0_p2wi", +- "apb0_uart", "apb0_1wire", +- "apb0_i2c"; +- }; +- +- ir_clk: ir_clk { +- #clock-cells = <0>; +- compatible = "allwinner,sun4i-a10-mod0-clk"; +- clocks = <&rtc 0>, <&osc24M>; +- clock-output-names = "ir"; +- }; +- +- apb0_rst: apb0_rst { +- compatible = "allwinner,sun6i-a31-clock-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- cpucfg@1f01c00 { +- compatible = "allwinner,sun6i-a31-cpuconfig"; +- reg = <0x01f01c00 0x300>; +- }; +- +- ir: ir@1f02000 { +- compatible = "allwinner,sun6i-a31-ir"; +- clocks = <&apb0_gates 1>, <&ir_clk>; +- clock-names = "apb", "ir"; +- resets = <&apb0_rst 1>; +- interrupts = ; +- reg = <0x01f02000 0x40>; +- status = "disabled"; +- }; +- +- r_pio: pinctrl@1f02c00 { +- compatible = "allwinner,sun6i-a31-r-pinctrl"; +- reg = <0x01f02c00 0x400>; +- interrupt-parent = <&r_intc>; +- interrupts = , +- ; +- clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; +- clock-names = "apb", "hosc", "losc"; +- resets = <&apb0_rst 0>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <3>; +- #gpio-cells = <3>; +- +- s_ir_rx_pin: s-ir-rx-pin { +- pins = "PL4"; +- function = "s_ir"; +- }; +- +- s_p2wi_pins: s-p2wi-pins { +- pins = "PL0", "PL1"; +- function = "s_p2wi"; +- }; +- }; +- +- p2wi: i2c@1f03400 { +- compatible = "allwinner,sun6i-a31-p2wi"; +- reg = <0x01f03400 0x400>; +- interrupts = ; +- clocks = <&apb0_gates 3>; +- clock-frequency = <100000>; +- resets = <&apb0_rst 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&s_p2wi_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun6i-a31s-colorfly-e708-q1.dts b/scripts/dtc/include-prefixes/arm/sun6i-a31s-colorfly-e708-q1.dts +deleted file mode 100644 +index a2ef7846e2c8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun6i-a31s-colorfly-e708-q1.dts ++++ /dev/null +@@ -1,72 +0,0 @@ +-/* +- * Copyright 2016 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun6i-a31s.dtsi" +-#include "sun6i-reference-design-tablet.dtsi" +- +-/ { +- model = "Colorfly E708 Q1 tablet"; +- compatible = "colorfly,e708-q1", "allwinner,sun6i-a31s"; +-}; +- +-&lradc { +- vref-supply = <®_aldo3>; +- status = "okay"; +- +- button-1000 { +- label = "Home"; +- linux,code = ; +- channel = <0>; +- voltage = <1000000>; +- }; +-}; +- +-®_dldo2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-pg"; +-}; +- +-&simplefb_lcd { +- vcc-pg-supply = <®_dldo2>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun6i-a31s-cs908.dts b/scripts/dtc/include-prefixes/arm/sun6i-a31s-cs908.dts +deleted file mode 100644 +index 1d15e15011c6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun6i-a31s-cs908.dts ++++ /dev/null +@@ -1,104 +0,0 @@ +-/* +- * Copyright 2014 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This library is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This library is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun6i-a31s.dtsi" +- +-/ { +- model = "CSQ CS908 top set box"; +- compatible = "csq,cs908", "allwinner,sun6i-a31s"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_mii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "mii"; +- status = "okay"; +-}; +- +-&ir { +- pinctrl-names = "default"; +- pinctrl-0 = <&s_ir_rx_pin>; +- status = "okay"; +-}; +- +-&mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ph_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun6i-a31s-inet-q972.dts b/scripts/dtc/include-prefixes/arm/sun6i-a31s-inet-q972.dts +deleted file mode 100644 +index c5e2c55cdc63..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun6i-a31s-inet-q972.dts ++++ /dev/null +@@ -1,98 +0,0 @@ +-/* +- * Copyright 2016 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun6i-a31s.dtsi" +-#include "sun6i-reference-design-tablet.dtsi" +- +-/ { +- model = "iNet Q972 tablet"; +- compatible = "inet-tek,inet-q972", "allwinner,sun6i-a31s"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- +- ft5406ee8: touchscreen@38 { +- compatible = "edt,edt-ft5406"; +- reg = <0x38>; +- interrupt-parent = <&pio>; +- interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; /* PA3 */ +- touchscreen-size-x = <768>; +- touchscreen-size-y = <1024>; +- touchscreen-swapped-x-y; +- }; +-}; +- +-&lradc { +- vref-supply = <®_aldo3>; +- status = "okay"; +- +- button-200 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <200000>; +- }; +- +- button-900 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <900000>; +- }; +- +- button-1200 { +- label = "Back"; +- linux,code = ; +- channel = <0>; +- voltage = <1200000>; +- }; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun6i-a31s-primo81.dts b/scripts/dtc/include-prefixes/arm/sun6i-a31s-primo81.dts +deleted file mode 100644 +index b32b70ada7fd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun6i-a31s-primo81.dts ++++ /dev/null +@@ -1,267 +0,0 @@ +-/* +- * Copyright 2014 Siarhei Siamashka +- * Copyright 2015 Karsten Merker +- * Copyright 2015 Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun6i-a31s.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "MSI Primo81 tablet"; +- compatible = "msi,primo81", "allwinner,sun6i-a31s"; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "c"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc3>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- /* rtl8188etv wifi is connected here */ +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- /* pull-ups and device VDDIO use AXP221 DLDO3 */ +- status = "failed"; +-}; +- +-&i2c1 { +- status = "okay"; +- +- ctp@5d { +- compatible = "goodix,gt911"; +- reg = <0x5d>; +- interrupt-parent = <&pio>; +- interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; /* PA3 */ +- touchscreen-swapped-x-y; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- +- accelerometer@1c { +- pinctrl-names = "default"; +- pinctrl-0 = <&mma8452_int_primo81>; +- compatible = "fsl,mma8452"; +- reg = <0x1c>; +- interrupt-parent = <&pio>; +- interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; /* PA9 */ +- }; +-}; +- +-&lradc { +- vref-supply = <®_aldo3>; +- status = "okay"; +- +- button-158 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <158730>; +- }; +- +- button-349 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <349206>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ +- status = "okay"; +-}; +- +-&pio { +- mma8452_int_primo81: mma8452-int-pin { +- pins = "PA9"; +- function = "gpio_in"; +- bias-pull-up; +- }; +-}; +- +-&p2wi { +- status = "okay"; +- +- axp22x: pmic@68 { +- compatible = "x-powers,axp221"; +- reg = <0x68>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- x-powers,drive-vbus-en; +- }; +-}; +- +-#include "axp22x.dtsi" +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "avcc"; +-}; +- +-®_dc1sw { +- regulator-name = "vcc-lcd"; +-}; +- +-®_dc5ldo { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-cpus"; /* This is an educated guess */ +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-3v0"; +-}; +- +-®_dcdc2 { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-gpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc4 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-sys-dll"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-®_dldo3 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "vddio-csi"; +-}; +- +-®_drivevbus { +- regulator-name = "usb0-vbus"; +- status = "okay"; +-}; +- +-®_eldo3 { +- regulator-min-microvolt = <1080000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-mipi-bridge"; +-}; +- +-&simplefb_lcd { +- vcc-lcd-supply = <®_dc1sw>; +- vdd-mipi-bridge-supply = <®_eldo3>; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_drivevbus>; +- usb1_vbus-supply = <®_dldo1>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun6i-a31s-sina31s-core.dtsi b/scripts/dtc/include-prefixes/arm/sun6i-a31s-sina31s-core.dtsi +deleted file mode 100644 +index 227ad489731c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun6i-a31s-sina31s-core.dtsi ++++ /dev/null +@@ -1,141 +0,0 @@ +-/* +- * Copyright 2015 Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun6i-a31s.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- model = "Sinlinx SinA31s Core Board"; +- compatible = "sinlinx,sina31s", "allwinner,sun6i-a31s"; +- +- aliases { +- serial0 = &uart0; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc3>; +-}; +- +-/* eMMC on core board */ +-&mmc3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc3_8bit_emmc_pins>; +- vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_dcdc1>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-/* AXP221s PMIC on core board */ +-&p2wi { +- status = "okay"; +- +- axp22x: pmic@68 { +- compatible = "x-powers,axp221"; +- reg = <0x68>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- }; +-}; +- +-#include "axp22x.dtsi" +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "avcc"; +-}; +- +-®_dc5ldo { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-3v0"; +-}; +- +-®_dcdc2 { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-gpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc4 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-sys-dll"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-/* UART0 pads available on core board */ +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ph_pins>; +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/sun6i-a31s-sina31s.dts b/scripts/dtc/include-prefixes/arm/sun6i-a31s-sina31s.dts +deleted file mode 100644 +index 0af48e143b66..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun6i-a31s-sina31s.dts ++++ /dev/null +@@ -1,195 +0,0 @@ +-/* +- * Copyright 2015 Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/* The SinA31s development board has the SinA31s core board soldered on */ +-#include "sun6i-a31s-sina31s-core.dtsi" +- +-#include +- +-/ { +- model = "Sinlinx SinA31s Development Board"; +- compatible = "sinlinx,sina31s-sdk", "allwinner,sun6i-a31s"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- status { +- label = "sina31s:status:usr"; +- gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */ +- }; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "On-board SPDIF"; +- simple-audio-card,cpu { +- sound-dai = <&spdif>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&spdif_out>; +- }; +- }; +- +- spdif_out: spdif-out { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- }; +-}; +- +-&codec { +- allwinner,audio-routing = +- "Line Out", "LINEOUT", +- "MIC1", "Mic", +- "Mic", "MBIAS"; +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- /* USB 2.0 4 port hub IC */ +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_mii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "mii"; +- phy-supply = <®_dldo1>; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&ir { +- pinctrl-names = "default"; +- pinctrl-0 = <&s_ir_rx_pin>; +- status = "okay"; +-}; +- +-&lradc { +- vref-supply = <®_aldo3>; +- status = "okay"; +- +- button-158 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <158730>; +- }; +- +- button-349 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <349206>; +- }; +-}; +- +-&mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-gmac-phy"; +-}; +- +-&spdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&spdif_tx_pin>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun6i-a31s-sinovoip-bpi-m2.dts b/scripts/dtc/include-prefixes/arm/sun6i-a31s-sinovoip-bpi-m2.dts +deleted file mode 100644 +index 96554ab4f6d3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun6i-a31s-sinovoip-bpi-m2.dts ++++ /dev/null +@@ -1,334 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This library is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This library is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun6i-a31s.dtsi" +-#include +- +-/ { +- model = "Sinovoip BPI-M2"; +- compatible = "sinovoip,bpi-m2", "allwinner,sun6i-a31s"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "bpi-m2:blue:usr"; +- gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ +- }; +- +- led-1 { +- label = "bpi-m2:green:usr"; +- gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */ +- }; +- +- led-2 { +- label = "bpi-m2:red:usr"; +- gpios = <&pio 6 5 GPIO_ACTIVE_HIGH>; /* PG5 */ +- }; +- }; +- +- mmc2_pwrseq: mmc2_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 WIFI_EN */ +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc3>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii"; +- phy-supply = <®_dldo1>; +- status = "okay"; +-}; +- +-&ir { +- pinctrl-names = "default"; +- pinctrl-0 = <&s_ir_rx_pin>; +- status = "okay"; +-}; +- +-&mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- reset-gpios = <&pio 0 21 GPIO_ACTIVE_LOW>; /* PA21 */ +- reset-assert-us = <10000>; +- reset-deassert-us = <30000>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ +- status = "okay"; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_4bit_pins>; +- vmmc-supply = <®_aldo1>; +- mmc-pwrseq = <&mmc2_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&r_pio>; +- interrupts = <0 5 IRQ_TYPE_LEVEL_LOW>; /* PL5 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&p2wi { +- status = "okay"; +- +- axp22x: pmic@68 { +- compatible = "x-powers,axp221"; +- reg = <0x68>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- eldoin-supply = <®_dcdc1>; +- x-powers,drive-vbus-en; +- }; +-}; +- +-#include "axp22x.dtsi" +- +-®_aldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-name = "vcc-gmac"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_dc5ldo { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vdd-3v0"; +-}; +- +-®_dcdc2 { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-gpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc4 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-sys-dll"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-mac"; +-}; +- +-®_dldo2 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "avdd-csi"; +-}; +- +-®_dldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pb"; +-}; +- +-®_eldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vdd-csi"; +- status = "okay"; +-}; +- +-®_ldo_io1 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-pm-cpus"; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ph_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +- +-&pio { +- gpio-line-names = +- /* PA */ +- "ETXD0", "ETXD1", "ETXD2", "ETXD3", "SDC0-DET", "", "", +- "", "ETXCLK", "ETXEN", "EGTXCLK", "ERXD0", "ERXD1", +- "ERXD2", "ERXD3", "", "", "", "", "ERXDV", "ERXCK", +- "ETXERR", "ERXERR", "ECOL", "ECRS", "ECLKIN", "EMDC", +- "EMDIO", "", "", "", "", +- +- /* PB */ +- "CN7-P29", "CN7-P31", "CN7-P33", "CN7-P35", "CN7-P37", +- "CN7-P28", "CN7-P27", "CN7-P32", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", "", "", "", "", "", +- "", "", "", "", +- +- /* PC */ +- "", "", "", "", "", "", "WL-SDIO-CMD", "WL-SDIO-CLK", +- "WL-SDIO-D0", "WL-SDIO-D2", "WL-SDIO-D2", "WL-SDIO-D3", +- "", "", "", "", "", "", "", "", "", "", "", "", "", "", +- "", "USB-DRV", "", "", "", "", +- +- /* PD */ +- "CN9-P09", "CN9-P11", "CN9-P13", "CN9-P15", "CN9-P17", +- "CN9-P19", "CN9-P21", "CN9-P23", "CN9-P25", "CN9-P27", +- "CN9-P29", "CN9-P31", "CN9-P33", "CN9-P35", "CN9-P37", +- "CN9-P39", "CN9-P40", "CN9-P38", "CN9-P36", "CN9-P34", +- "CN9-P32", "CN9-P30", "CN9-P28", "CN9-P26", "CN9-P22", +- "CN9-P14", "CN9-P18", "CN9-P16", "", "", "", "", +- +- /* PE */ +- "CN6-P20", "CN6-P24", "CN6-P30", "CN6-P28", "CN7-P08", +- "CN7-P10", "CN7-P36", "CN7-P38", "CN6-P17", "CN6-P19", +- "CN6-P21", "CN6-P23", "CN6-P25", "CN6-P27", "CN6-P29", +- "CN6-P31", "", "", "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", +- +- /* PF */ +- "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3", +- "SDC0-D2", "", "", "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", "", "", "", "", "", +- "", +- +- /* PG */ +- "CN9-P06", "CN9-P08", "CN9-P20", "CN9-P12", "CN9-P07", +- "LED-PWR", "CN7-P13", "CN7-P11", "CN7-P22", "CN7-P15", +- "LED-G", "LED-B", "CN7-P26", "CN7-P24", "CN7-P23", +- "CN7-P19", "CN7-P21", "HCEC", "CN6-P22", "", "", "", "", +- "", "", "", "", "", "", "", "", "", +- +- /* PH */ +- "", "", "", "", "", "", "", "", "", "CN7-P07", +- "CN7-P12", "CN7-P16", "CN7-P18", "CN9-P10", "CN6-P16", +- "CN6-P14", "CN9-P04", "CN9-P02", "CN7-P05", "CN7-P03", +- "CN8-P03", "CN8-P02", "", "", "CN6-P34", "CN6-P32", +- "CN6-P26", "CN6-P18", "", "", "", ""; +-}; +- +-&r_pio { +- gpio-line-names = +- /* PL */ +- "PMU-SCK", "PMU-SDA", "VBAT-EN", "", "IR-RX", +- "WL-WAKE-HOST", "BT-WAKE_HOST", "BT-ENABLE", +- "WL-PMU-EN", "", "", "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", "", "", "", +- +- /* PM */ +- "CN6-P12", "CN6-P35", "CN7-P40", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", ""; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun6i-a31s-yones-toptech-bs1078-v2.dts b/scripts/dtc/include-prefixes/arm/sun6i-a31s-yones-toptech-bs1078-v2.dts +deleted file mode 100644 +index 0b61f5368d44..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun6i-a31s-yones-toptech-bs1078-v2.dts ++++ /dev/null +@@ -1,182 +0,0 @@ +-/* +- * Copyright 2015 Lawrence Yu +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun6i-a31s.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- model = "Yones TopTech BS1078 v2 Tablet"; +- compatible = "yones-toptech,bs1078-v2", "allwinner,sun6i-a31s"; +- +- aliases { +- serial0 = &uart0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v0>; +- bus-width = <4>; +- cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ +- status = "okay"; +-}; +- +-&p2wi { +- status = "okay"; +- +- axp22x: pmic@68 { +- compatible = "x-powers,axp221"; +- reg = <0x68>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- }; +-}; +- +-#include "axp22x.dtsi" +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "avcc"; +-}; +- +-®_dc1sw { +- regulator-name = "vcc-lcd-usb2"; +-}; +- +-®_dc5ldo { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-3v0"; +-}; +- +-®_dcdc2 { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-gpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc4 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-sys-dll"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-/* Voltage source for I2C pullup resistors for I2C Bus 0 */ +-®_dldo3 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "vddio-csi"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ph_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_dldo1>; +- usb2_vbus-supply = <®_dc1sw>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun6i-a31s.dtsi b/scripts/dtc/include-prefixes/arm/sun6i-a31s.dtsi +deleted file mode 100644 +index 97e2c51d0aea..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun6i-a31s.dtsi ++++ /dev/null +@@ -1,61 +0,0 @@ +-/* +- * Copyright 2014 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This library is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This library is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/* +- * The A31s is the same die as the A31 in a different package, this is +- * reflected by it having different pinctrl compatible everything else is +- * identical. +- */ +- +-#include "sun6i-a31.dtsi" +- +-&de { +- compatible = "allwinner,sun6i-a31s-display-engine"; +-}; +- +-&pio { +- compatible = "allwinner,sun6i-a31s-pinctrl"; +-}; +- +-&tcon0 { +- compatible = "allwinner,sun6i-a31s-tcon"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun6i-reference-design-tablet.dtsi b/scripts/dtc/include-prefixes/arm/sun6i-reference-design-tablet.dtsi +deleted file mode 100644 +index f38d19c6be8c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun6i-reference-design-tablet.dtsi ++++ /dev/null +@@ -1,173 +0,0 @@ +-/* +- * Copyright 2016 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc3>; +-}; +- +-&ehci0 { +- /* Wifi is connected here */ +- status = "okay"; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ +- status = "okay"; +-}; +- +-&p2wi { +- status = "okay"; +- +- axp22x: pmic@68 { +- compatible = "x-powers,axp221"; +- reg = <0x68>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- drivevbus-supply = <®_vcc5v0>; +- x-powers,drive-vbus-en; +- }; +-}; +- +-#include "axp22x.dtsi" +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "avcc"; +-}; +- +-®_dc1sw { +- regulator-name = "vcc-lcd"; +-}; +- +-®_dc5ldo { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-cpus"; /* This is an educated guess */ +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-3v0"; +-}; +- +-®_dcdc2 { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-gpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc4 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd-sys-dll"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-®_drivevbus { +- regulator-name = "usb0-vbus"; +- status = "okay"; +-}; +- +-&simplefb_lcd { +- vcc-lcd-supply = <®_dc1sw>; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 0 15 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA15 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_drivevbus>; +- usb1_vbus-supply = <®_dldo1>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-bananapi-m1-plus.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-bananapi-m1-plus.dts +deleted file mode 100644 +index caa935ca4f19..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-bananapi-m1-plus.dts ++++ /dev/null +@@ -1,264 +0,0 @@ +-/* +- * Copyright 2016 Luo Yi +- * +- * Thanks to the original work by Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +-#include +-#include +- +-/ { +- model = "Banana Pi BPI-M1-Plus"; +- compatible = "sinovoip,bpi-m1-plus", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "bananapi-m1-plus:green:usr"; +- gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; +- }; +- +- led-1 { +- label = "bananapi-m1-plus:pwr:usr"; +- gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- mmc3_pwrseq: mmc3_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */ +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- enable-active-high; +- gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&ahci { +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii-id"; +- phy-supply = <®_gmac_3v3>; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pin>; +- status = "okay"; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ +- status = "okay"; +-}; +- +-&mmc3 { +- #address-cells = <1>; +- #size-cells = <0>; +- vmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&mmc3_pwrseq>; +- bus-width = <4>; +- non-removable; +- wakeup-source; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&pio>; +- interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>; +- interrupt-names = "host-wake"; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_usb0_vbus>; +- /* VBUS on usb host ports are tied to DC5V and therefore always on */ +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-bananapi.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-bananapi.dts +deleted file mode 100644 +index 9d792d7a0f92..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-bananapi.dts ++++ /dev/null +@@ -1,334 +0,0 @@ +-/* +- * Copyright 2014 Hans de Goede +- * +- * Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "LeMaker Banana Pi"; +- compatible = "lemaker,bananapi", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart3; +- serial2 = &uart7; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led { +- label = "bananapi:green:usr"; +- gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- enable-active-high; +- gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&ahci { +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +- operating-points = < +- /* kHz uV */ +- 960000 1400000 +- 912000 1400000 +- 864000 1350000 +- 720000 1250000 +- 528000 1150000 +- 312000 1100000 +- 144000 1050000 +- >; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii-id"; +- phy-supply = <®_gmac_3v3>; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pin>; +- status = "okay"; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pio { +- vcc-pa-supply = <®_vcc3v3>; +- vcc-pc-supply = <®_vcc3v3>; +- vcc-pe-supply = <®_vcc3v3>; +- vcc-pf-supply = <®_vcc3v3>; +- vcc-pg-supply = <®_vcc3v3>; +- gpio-line-names = +- /* PA */ +- "ERXD3", "ERXD2", "ERXD1", "ERXD0", "ETXD3", +- "ETXD2", "ETXD1", "ETXD0", +- "ERXCK", "ERXERR", "ERXDV", "EMDC", "EMDIO", +- "ETXEN", "ETXCK", "ECRS", +- "ECOL", "ETXERR", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- /* PB */ +- "PMU-SCK", "PMU-SDA", "", "", "", "", "", "", +- "", "USB0-DRV", "", "", "", "", "", "", +- "", "", "", "", "SCL", "SDA", "", "", +- "", "", "", "", "", "", "", "", +- /* PC */ +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- /* PD */ +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- /* PE */ +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- /* PF */ +- "SD0-D1", "SD0-D0", "SD0-CLK", "SD0-CMD", "SD0-D3", +- "SD0-D2", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- /* PG */ +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- /* PH */ +- "TXD0", "RXD0", "IO-1", "PH3", "USB0-IDDET", "PH5", "", "", +- "", "", "SD0-DET", "", "", "", "", "", +- "", "", "", "", "IO-4", "IO-5", "", "EMAC-PWR-EN", +- "LED1", "", "", "", "", "", "", "", +- /* PI */ +- "", "", "", "IO-GCLK", "", "", "", "", +- "", "", "SPI-CE0", "SPI-CLK", "SPI-MOSI", +- "SPI-MISO", "SPI-CE1", "", +- "IO-6", "IO-3", "IO-2", "IO-0", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-#include "axp209.dtsi" +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pi_pins>, +- <&spi0_cs0_pi_pin>, +- <&spi0_cs1_pi_pin>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_ph_pins>; +- status = "okay"; +-}; +- +-&uart7 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart7_pi_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-bananapro.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-bananapro.dts +deleted file mode 100644 +index e22f0e8bb17a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-bananapro.dts ++++ /dev/null +@@ -1,219 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +-#include +-#include +- +-/ { +- model = "LeMaker Banana Pro"; +- compatible = "lemaker,bananapro", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart4; +- serial2 = &uart7; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "bananapro:blue:usr"; +- gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; +- }; +- +- led-1 { +- label = "bananapro:green:usr"; +- gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- wifi_pwrseq: wifi-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- enable-active-high; +- gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&ahci { +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii-id"; +- phy-supply = <®_gmac_3v3>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- compatible = "x-powers,axp209"; +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pin>; +- status = "okay"; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ +- status = "okay"; +-}; +- +-&mmc3 { +- vmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&pio>; +- interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>; +- interrupt-names = "host-wake"; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- gpio = <&pio 7 0 GPIO_ACTIVE_HIGH>; /* PH0 */ +- status = "okay"; +-}; +- +-®_usb2_vbus { +- gpio = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pi_pins>, +- <&spi0_cs0_pi_pin>, +- <&spi0_cs1_pi_pin>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_ph_pins>; +- status = "okay"; +-}; +- +-&uart7 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart7_pi_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-cubieboard2.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-cubieboard2.dts +deleted file mode 100644 +index e35e6990c4b2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-cubieboard2.dts ++++ /dev/null +@@ -1,237 +0,0 @@ +-/* +- * Copyright 2013 Maxime Ripard +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Cubietech Cubieboard2"; +- compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "cubieboard2:blue:usr"; +- gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; +- }; +- +- led-1 { +- label = "cubieboard2:green:usr"; +- gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&ahci { +- target-supply = <®_ahci_5v>; +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_mii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "mii"; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pin>; +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_ahci_5v { +- status = "okay"; +-}; +- +-#include "axp209.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1450000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-cubietruck.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-cubietruck.dts +deleted file mode 100644 +index 52160e368304..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-cubietruck.dts ++++ /dev/null +@@ -1,345 +0,0 @@ +-/* +- * Copyright 2013 Oliver Schinagl +- * +- * Oliver Schinagl +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Cubietech Cubietruck"; +- compatible = "cubietech,cubietruck", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "cubietruck:blue:usr"; +- gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; +- }; +- +- led-1 { +- label = "cubietruck:orange:usr"; +- gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; +- }; +- +- led-2 { +- label = "cubietruck:white:usr"; +- gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; +- }; +- +- led-3 { +- label = "cubietruck:green:usr"; +- gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- mmc3_pwrseq: mmc3_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ +- clocks = <&ccu CLK_OUT_A>; +- clock-names = "ext_clock"; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "On-board SPDIF"; +- +- simple-audio-card,cpu { +- sound-dai = <&spdif>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&spdif_out>; +- }; +- }; +- +- spdif_out: spdif-out { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- }; +-}; +- +-&ahci { +- target-supply = <®_ahci_5v>; +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pin>; +- status = "okay"; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&mmc3 { +- vmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&mmc3_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&pio>; +- interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pio { +- /* Pin outputs low power clock for WiFi and BT */ +- pinctrl-0 = <&clk_out_a_pin>; +- pinctrl-names = "default"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>, <&pwm1_pin>; +- status = "okay"; +-}; +- +-®_ahci_5v { +- gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-#include "axp209.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1450000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb0_vbus { +- gpio = <&pio 7 17 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&spdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&spdif_tx_pin>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm20702a1"; +- clocks = <&ccu CLK_OUT_A>; +- clock-names = "lpo"; +- device-wakeup-gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */ +- host-wakeup-gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */ +- shutdown-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH18 */ +- max-speed = <1500000>; +- }; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ +- usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-hummingbird.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-hummingbird.dts +deleted file mode 100644 +index 3def2a330598..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-hummingbird.dts ++++ /dev/null +@@ -1,233 +0,0 @@ +-/* +- * Copyright 2013 Wills Wang +- * +- * Wills Wang +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Merrii A20 Hummingbird"; +- compatible = "merrii,a20-hummingbird", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- serial4 = &uart5; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- reg_mmc3_vdd: mmc3_vdd { +- compatible = "regulator-fixed"; +- regulator-name = "mmc3_vdd"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- enable-active-high; +- gpio = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ +- }; +- +- reg_gmac_vdd: gmac_vdd { +- compatible = "regulator-fixed"; +- regulator-name = "gmac_vdd"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- enable-active-high; +- gpio = <&pio 7 16 GPIO_ACTIVE_HIGH>; /* PH16 */ +- }; +-}; +- +-&ahci { +- target-supply = <®_ahci_5v>; +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii"; +- phy-supply = <®_gmac_vdd>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- compatible = "x-powers,axp209"; +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pin>; +- status = "okay"; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- reset-gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */ +- reset-assert-us = <10000>; +- /* wait 1s after reset, otherwise fail to read phy id */ +- reset-deassert-us = <1000000>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v0>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&mmc3 { +- vmmc-supply = <®_mmc3_vdd>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>; +- status = "okay"; +-}; +- +-®_ahci_5v { +- gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ +- status = "okay"; +-}; +- +-®_usb1_vbus { +- gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&spi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pb_pins>, +- <&spi2_cs0_pb_pin>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pg_pins>, <&uart3_cts_rts_pg_pins>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pg_pins>; +- status = "okay"; +-}; +- +-&uart5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart5_pi_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-i12-tvbox.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-i12-tvbox.dts +deleted file mode 100644 +index b21ddd0ec1c2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-i12-tvbox.dts ++++ /dev/null +@@ -1,198 +0,0 @@ +-/* +- * Copyright 2014 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "I12 / Q5 / QT840A A20 tvbox"; +- compatible = "allwinner,i12-tvbox", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "i12_tvbox:red:usr"; +- gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; +- }; +- +- led-1 { +- label = "i12_tvbox:blue:usr"; +- gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- reg_vmmc3: vmmc3 { +- compatible = "regulator-fixed"; +- regulator-name = "vmmc3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_vmmc3_io: vmmc3-io { +- compatible = "regulator-fixed"; +- regulator-name = "vmmc3-io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- /* This controls VCC-PI, must be always on! */ +- regulator-always-on; +- enable-active-high; +- gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <50000>; +- enable-active-high; +- gpio = <&pio 7 21 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_mii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "mii"; +- phy-supply = <®_gmac_3v3>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- compatible = "x-powers,axp209"; +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pin>; +- status = "okay"; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&mmc3 { +- vmmc-supply = <®_vmmc3>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&pio>; +- interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-icnova-swac.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-icnova-swac.dts +deleted file mode 100644 +index 413505f45a81..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-icnova-swac.dts ++++ /dev/null +@@ -1,164 +0,0 @@ +-/* +- * Copyright 2015 Stefan Roese +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "ICnova-A20 SWAC"; +- compatible = "incircuit,icnova-a20-swac", "incircuit,icnova-a20", +- "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_mii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "mii"; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 8 5 GPIO_ACTIVE_LOW>; /* PI5 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-#include "axp209.dtsi" +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-itead-ibox.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-itead-ibox.dts +deleted file mode 100644 +index 8ff83016ff5a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-itead-ibox.dts ++++ /dev/null +@@ -1,147 +0,0 @@ +-/* +- * Copyright 2015 - Marcus Cooper +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-itead-core-common.dtsi" +- +-/ { +- model = "Itead Ibox A20"; +- compatible = "itead,itead-ibox-a20", "allwinner,sun7i-a20"; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins_itead_core>; +- +- led-0 { +- label = "itead_core:green:usr"; +- gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- led-1 { +- label = "itead_core:blue:usr"; +- gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "On-board SPDIF"; +- +- simple-audio-card,cpu { +- sound-dai = <&spdif>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&spdif_out>; +- }; +- }; +- +- spdif_out: spdif-out { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- }; +-}; +- +-&ahci { +- target-supply = <®_ahci_5v>; +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_mii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "mii"; +- status = "okay"; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&i2c0 { +- axp209: pmic@34 { +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pin>; +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&pio { +- led_pins_itead_core: led-pins { +- pins = "PH20","PH21"; +- function = "gpio_out"; +- drive-strength = <20>; +- }; +-}; +- +-®_ahci_5v { +- status = "okay"; +-}; +- +-&spdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&spdif_tx_pin>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-lamobo-r1.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-lamobo-r1.dts +deleted file mode 100644 +index 97518afe4658..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-lamobo-r1.dts ++++ /dev/null +@@ -1,320 +0,0 @@ +-/* +- * Copyright 2015 Jelle de Jong +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Lamobo R1"; +- compatible = "lamobo,lamobo-r1", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart3; +- serial2 = &uart7; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led { +- label = "lamobo_r1:green:usr"; +- gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- enable-active-high; +- gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ +- }; +-}; +- +-&ahci { +- target-supply = <®_ahci_5v>; +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-mode = "rgmii"; +- phy-supply = <®_gmac_3v3>; +- status = "okay"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch: ethernet-switch@1e { +- compatible = "brcm,bcm53125"; +- reg = <30>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port0: port@0 { +- reg = <0>; +- label = "lan2"; +- }; +- +- port1: port@1 { +- reg = <1>; +- label = "lan3"; +- }; +- +- port2: port@2 { +- reg = <2>; +- label = "lan4"; +- }; +- +- port3: port@3 { +- reg = <3>; +- label = "wan"; +- }; +- +- port4: port@4 { +- reg = <4>; +- label = "lan1"; +- }; +- +- port8: port@8 { +- reg = <8>; +- label = "cpu"; +- ethernet = <&gmac>; +- phy-mode = "rgmii-txid"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pin>; +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-#include "axp209.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_ahci_5v { +- gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pi_pins>, +- <&spi0_cs0_pi_pin>, +- <&spi0_cs1_pi_pin>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_ph_pins>; +- status = "okay"; +-}; +- +-&uart7 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart7_pi_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_usb0_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-linutronix-testbox-v2.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-linutronix-testbox-v2.dts +deleted file mode 100644 +index da5a2eea4ce3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-linutronix-testbox-v2.dts ++++ /dev/null +@@ -1,47 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2020 Linutronix GmbH +- * Author: Benedikt Spranger +- */ +- +-/dts-v1/; +-#include "sun7i-a20-lamobo-r1.dts" +- +-/ { +- model = "Lamobo R1"; +- compatible = "linutronix,testbox-v2", "lamobo,lamobo-r1", "allwinner,sun7i-a20"; +- +- leds { +- led-opto1 { +- label = "lamobo_r1:opto:powerswitch"; +- gpios = <&pio 7 3 GPIO_ACTIVE_HIGH>; +- }; +- +- led-opto2 { +- label = "lamobo_r1:opto:relay"; +- gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- status = "okay"; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c08"; +- reg = <0x50>; +- status = "okay"; +- }; +- +- atecc508a@60 { +- compatible = "atmel,atecc508a"; +- reg = <0x60>; +- }; +-}; +- +-&can0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&can_ph_pins>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-m3.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-m3.dts +deleted file mode 100644 +index f161d5238860..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-m3.dts ++++ /dev/null +@@ -1,156 +0,0 @@ +-/* +- * Copyright 2014 Hans de Goede +- * +- * Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Mele M3"; +- compatible = "mele,m3", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led { +- label = "m3:blue:usr"; +- gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_mii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "mii"; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- compatible = "x-powers,axp209"; +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pin>; +- status = "okay"; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&mmc2 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-mk808c.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-mk808c.dts +deleted file mode 100644 +index 1491c603f661..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-mk808c.dts ++++ /dev/null +@@ -1,184 +0,0 @@ +-/* +- * Copyright 2015 Marcus Cooper +- * +- * Marcus Cooper +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "mk808c"; +- compatible = "allwinner,mk808c", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- compatible = "x-powers,axp209"; +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v0>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ +- usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-olimex-som-evb-emmc.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-olimex-som-evb-emmc.dts +deleted file mode 100644 +index 20bf09b2226c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-olimex-som-evb-emmc.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Source for A20-Olimex-SOM-EVB-eMMC Board +- * +- * Copyright (C) 2018 Olimex Ltd. +- * Author: Stefan Mavrodiev +- */ +- +-/dts-v1/; +-#include "sun7i-a20-olimex-som-evb.dts" +- +-/ { +- +- model = "Olimex A20-Olimex-SOM-EVB-eMMC"; +- compatible = "olimex,a20-olimex-som-evb-emmc", "allwinner,sun7i-a20"; +- +- mmc2_pwrseq: mmc2_pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&pio 2 18 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&mmc2 { +- vmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&mmc2_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- emmc: emmc@0 { +- reg = <0>; +- compatible = "mmc-card"; +- broken-hpi; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-olimex-som-evb.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-olimex-som-evb.dts +deleted file mode 100644 +index f05ee32bc9cb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-olimex-som-evb.dts ++++ /dev/null +@@ -1,329 +0,0 @@ +-/* +- * Copyright 2015 - Marcus Cooper +- * Copyright 2015 - Karsten Merker +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +-#include +- +-/ { +- model = "Olimex A20-Olimex-SOM-EVB"; +- compatible = "olimex,a20-olimex-som-evb", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led { +- label = "a20-olimex-som-evb:green:usr"; +- gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +-}; +- +-&ahci { +- target-supply = <®_ahci_5v>; +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii"; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&lradc { +- vref-supply = <®_vcc3v0>; +- status = "okay"; +- +- button-190 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <190000>; +- }; +- +- button-390 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <390000>; +- }; +- +- button-600 { +- label = "Menu"; +- linux,code = ; +- channel = <0>; +- voltage = <600000>; +- }; +- +- button-800 { +- label = "Search"; +- linux,code = ; +- channel = <0>; +- voltage = <800000>; +- }; +- +- button-980 { +- label = "Home"; +- linux,code = ; +- channel = <0>; +- voltage = <980000>; +- }; +- +- button-1180 { +- label = "Esc"; +- linux,code = ; +- channel = <0>; +- voltage = <1180000>; +- }; +- +- button-1400 { +- label = "Enter"; +- linux,code = ; +- channel = <0>; +- voltage = <1400000>; +- }; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&mmc3 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 0 GPIO_ACTIVE_LOW>; /* PH0 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pio { +- led_pins_olimex_som_evb: led-pins { +- pins = "PH2"; +- function = "gpio_out"; +- drive-strength = <20>; +- }; +-}; +- +-®_ahci_5v { +- gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-#include "axp209.dtsi" +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pi_pins>, +- <&spi1_cs0_pi_pin>; +- status = "okay"; +-}; +- +-&spi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pc_pins>, +- <&spi2_cs0_pc_pin>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&uart6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart6_pi_pins>; +- status = "okay"; +-}; +- +-&uart7 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart7_pi_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH04 */ +- usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH05 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-olimex-som204-evb-emmc.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-olimex-som204-evb-emmc.dts +deleted file mode 100644 +index a59755a2e7a9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-olimex-som204-evb-emmc.dts ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Source for A20-SOM204-EVB-eMMC Board +- * +- * Copyright (C) 2018 Olimex Ltd. +- * Author: Stefan Mavrodiev +- */ +- +-/dts-v1/; +-#include "sun7i-a20-olimex-som204-evb.dts" +- +-/ { +- model = "Olimex A20-SOM204-EVB-eMMC"; +- compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20"; +- +- mmc2_pwrseq: mmc2_pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&mmc2 { +- vmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&mmc2_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- emmc: emmc@0 { +- reg = <0>; +- compatible = "mmc-card"; +- broken-hpi; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-olimex-som204-evb.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-olimex-som204-evb.dts +deleted file mode 100644 +index 54af6c18075b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-olimex-som204-evb.dts ++++ /dev/null +@@ -1,326 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Source for A20-SOM204-EVB Board +- * +- * Copyright (C) 2018 Olimex Ltd. +- * Author: Stefan Mavrodiev +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +- +-#include +-#include +-#include +- +-/ { +- model = "Olimex A20-SOM204-EVB"; +- compatible = "olimex,a20-olimex-som204-evb", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart4; +- serial2 = &uart7; +- spi0 = &spi1; +- spi1 = &spi2; +- ethernet1 = &rtl8723bs; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "a20-som204-evb:green:stat"; +- gpios = <&pio 8 0 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- led-1 { +- label = "a20-som204-evb:green:led1"; +- gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- led-2 { +- label = "a20-som204-evb:yellow:led2"; +- gpios = <&pio 8 11 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- rtl_pwrseq: rtl_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&ahci { +- target-supply = <®_ahci_5v>; +- status = "okay"; +-}; +- +-&can0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&can_ph_pins>; +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy3>; +- phy-mode = "rgmii"; +- phy-supply = <®_vcc3v3>; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-/* Exposed to UEXT1 */ +-&i2c1 { +- status = "okay"; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c16"; +- reg = <0x50>; +- pagesize = <16>; +- }; +-}; +- +-/* Exposed to UEXT2 */ +-&i2c2 { +- status = "okay"; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pin>; +- status = "okay"; +-}; +- +-&gmac_mdio { +- phy3: ethernet-phy@3 { +- reg = <3>; +- reset-gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */ +- reset-assert-us = <10000>; +- /* wait 1s after reset, otherwise fail to read phy id */ +- reset-deassert-us = <1000000>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&mmc3 { +- vmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&rtl_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- rtl8723bs: sdio_wifi@1 { +- reg = <1>; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pio { +- uart3_rts_pin: uart3-rts-pin { +- pins = "PG8"; +- function = "uart3"; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_ahci_5v { +- gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-always-on; +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_ldo4 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pg"; +-}; +- +-®_usb0_vbus { +- gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-/* Exposed to UEXT1 */ +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pi_pins>, +- <&spi1_cs0_pi_pin>; +- status = "okay"; +-}; +- +-/* Exposed to UEXT2 */ +-&spi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pc_pins>, +- <&spi2_cs0_pc_pin>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-/* Used for RTL8723BS bluetooth */ +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_pin>; +- status = "okay"; +-}; +- +-/* Exposed to UEXT1 */ +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pg_pins>; +- status = "okay"; +-}; +- +-/* Exposed to UEXT2 */ +-&uart7 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart7_pi_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ +- usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-olinuxino-lime-emmc.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-olinuxino-lime-emmc.dts +deleted file mode 100644 +index 033cab3443f8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-olinuxino-lime-emmc.dts ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2020 Olimex Ltd. +- * Author: Stefan Mavrodiev +- */ +- +-#include "sun7i-a20-olinuxino-lime.dts" +- +-/ { +- model = "Olimex A20-OLinuXino-LIME-eMMC"; +- compatible = "olimex,a20-olinuxino-lime-emmc", "allwinner,sun7i-a20"; +- +- mmc2_pwrseq: pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&mmc2 { +- vmmc-supply = <®_vcc3v3>; +- vqmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- non-removable; +- mmc-pwrseq = <&mmc2_pwrseq>; +- status = "okay"; +- +- emmc: emmc@0 { +- reg = <0>; +- compatible = "mmc-card"; +- broken-hpi; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-olinuxino-lime.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-olinuxino-lime.dts +deleted file mode 100644 +index 92938d022295..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-olinuxino-lime.dts ++++ /dev/null +@@ -1,216 +0,0 @@ +-/* +- * This is based on sun4i-a10-olinuxino-lime.dts +- * +- * Copyright 2014 - Hans de Goede +- * Copyright (c) 2014 FUKAUMI Naoki +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Olimex A20-OLinuXino-LIME"; +- compatible = "olimex,a20-olinuxino-lime", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins_olinuxinolime>; +- +- led { +- label = "a20-olinuxino-lime:green:usr"; +- gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +-}; +- +-&ahci { +- target-supply = <®_ahci_5v>; +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_mii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "mii"; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- compatible = "x-powers,axp209"; +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c16"; +- reg = <0x50>; +- pagesize = <16>; +- }; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pio { +- led_pins_olinuxinolime: led-pins { +- pins = "PH2"; +- function = "gpio_out"; +- drive-strength = <20>; +- }; +-}; +- +-®_ahci_5v { +- gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-olinuxino-lime2-emmc.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-olinuxino-lime2-emmc.dts +deleted file mode 100644 +index decb014a382b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-olinuxino-lime2-emmc.dts ++++ /dev/null +@@ -1,69 +0,0 @@ +- /* +- * Copyright 2015 - Ultimaker B.V. +- * Author Olliver Schinagl +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "sun7i-a20-olinuxino-lime2.dts" +- +-/ { +- model = "Olimex A20-OLinuXino-LIME2-eMMC"; +- compatible = "olimex,a20-olinuxino-lime2-emmc", "allwinner,sun7i-a20"; +- +- mmc2_pwrseq: pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&mmc2 { +- vmmc-supply = <®_vcc3v3>; +- vqmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- non-removable; +- mmc-pwrseq = <&mmc2_pwrseq>; +- status = "okay"; +- +- emmc: emmc@0 { +- reg = <0>; +- compatible = "mmc-card"; +- broken-hpi; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-olinuxino-lime2.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-olinuxino-lime2.dts +deleted file mode 100644 +index ecb91fb899ff..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-olinuxino-lime2.dts ++++ /dev/null +@@ -1,280 +0,0 @@ +-/* +- * Copyright 2014 - Iain Paton +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Olimex A20-OLinuXino-LIME2"; +- compatible = "olimex,a20-olinuxino-lime2", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins_olinuxinolime>; +- +- led { +- label = "a20-olinuxino-lime2:green:usr"; +- gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- reg_axp_ipsout: axp_ipsout { +- compatible = "regulator-fixed"; +- regulator-name = "axp-ipsout"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +-}; +- +-&ahci { +- target-supply = <®_ahci_5v>; +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c16"; +- reg = <0x50>; +- pagesize = <16>; +- }; +-}; +- +-&lradc { +- vref-supply = <®_vcc3v0>; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pio { +- vcc-pa-supply = <®_vcc3v3>; +- vcc-pc-supply = <®_vcc3v3>; +- vcc-pe-supply = <®_ldo3>; +- vcc-pf-supply = <®_vcc3v3>; +- vcc-pg-supply = <®_ldo4>; +- +- led_pins_olinuxinolime: led-pins { +- pins = "PH2"; +- function = "gpio_out"; +- drive-strength = <20>; +- }; +-}; +- +-®_ahci_5v { +- gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-#include "axp209.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-always-on; +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_ldo3 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "vddio-csi0"; +- regulator-soft-start; +- regulator-ramp-delay = <1600>; +-}; +- +-®_ldo4 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "vddio-csi1"; +-}; +- +-®_usb0_vbus { +- gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-olinuxino-micro-emmc.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-olinuxino-micro-emmc.dts +deleted file mode 100644 +index 2337b44a88aa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-olinuxino-micro-emmc.dts ++++ /dev/null +@@ -1,68 +0,0 @@ +- /* +- * Copyright 2017 Olimex Ltd. +- * Stefan Mavrodiev +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "sun7i-a20-olinuxino-micro.dts" +- +-/ { +- model = "Olimex A20-OLinuXino-MICRO-eMMC"; +- compatible = "olimex,a20-olinuxino-micro-emmc", "allwinner,sun7i-a20"; +- +- mmc2_pwrseq: pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&mmc2 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- non-removable; +- mmc-pwrseq = <&mmc2_pwrseq>; +- status = "okay"; +- +- emmc: emmc@0 { +- reg = <0>; +- compatible = "mmc-card"; +- broken-hpi; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-olinuxino-micro.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-olinuxino-micro.dts +deleted file mode 100644 +index a1b89b2a2999..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-olinuxino-micro.dts ++++ /dev/null +@@ -1,354 +0,0 @@ +-/* +- * Copyright 2013 Maxime Ripard +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +-#include +- +-/ { +- model = "Olimex A20-Olinuxino Micro"; +- compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart6; +- serial2 = &uart7; +- spi0 = &spi1; +- spi1 = &spi2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pins_olinuxino>; +- +- led { +- label = "a20-olinuxino-micro:green:usr"; +- gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +-}; +- +-&ahci { +- target-supply = <®_ahci_5v>; +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_mii_pins>, <&gmac_txerr>; +- phy-handle = <&phy1>; +- phy-mode = "mii"; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c16"; +- reg = <0x50>; +- pagesize = <16>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&lradc { +- vref-supply = <®_vcc3v0>; +- status = "okay"; +- +- button-191 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <191274>; +- }; +- +- button-392 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <392644>; +- }; +- +- button-601 { +- label = "Menu"; +- linux,code = ; +- channel = <0>; +- voltage = <601151>; +- }; +- +- button-795 { +- label = "Search"; +- linux,code = ; +- channel = <0>; +- voltage = <795090>; +- }; +- +- button-987 { +- label = "Home"; +- linux,code = ; +- channel = <0>; +- voltage = <987387>; +- }; +- +- button-1184 { +- label = "Esc"; +- linux,code = ; +- channel = <0>; +- voltage = <1184678>; +- }; +- +- button-1398 { +- label = "Enter"; +- linux,code = ; +- channel = <0>; +- voltage = <1398804>; +- }; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&mmc3 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pio { +- gmac_txerr: gmac-txerr-pin { +- pins = "PA17"; +- function = "gmac"; +- }; +- +- led_pins_olinuxino: led-pins { +- pins = "PH2"; +- function = "gpio_out"; +- drive-strength = <20>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_ahci_5v { +- status = "okay"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pi_pins>, +- <&spi1_cs0_pi_pin>; +- status = "okay"; +-}; +- +-&spi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pc_pins>, +- <&spi2_cs0_pc_pin>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&uart6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart6_pi_pins>; +- status = "okay"; +-}; +- +-&uart7 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart7_pi_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-orangepi-mini.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-orangepi-mini.dts +deleted file mode 100644 +index 84efa01e7cba..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-orangepi-mini.dts ++++ /dev/null +@@ -1,242 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Orange Pi Mini"; +- compatible = "xunlong,orangepi-mini", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "orangepi:green:usr"; +- gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ +- }; +- +- led-1 { +- label = "orangepi:blue:usr"; +- gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */ +- }; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- enable-active-high; +- gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ +- }; +-}; +- +-&ahci { +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii"; +- phy-supply = <®_gmac_3v3>; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pin>; +- status = "okay"; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ +- status = "okay"; +-}; +- +-&mmc3 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-pll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */ +- status = "okay"; +-}; +- +-®_usb2_vbus { +- gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-orangepi.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-orangepi.dts +deleted file mode 100644 +index 5d77f1d9818f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-orangepi.dts ++++ /dev/null +@@ -1,201 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Orange Pi"; +- compatible = "xunlong,orangepi", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led { +- label = "orangepi:green:usr"; +- gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ +- }; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- enable-active-high; +- gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ +- }; +-}; +- +-&ahci { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii"; +- phy-supply = <®_gmac_3v3>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pin>; +- status = "okay"; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-pll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */ +- status = "okay"; +-}; +- +-®_usb2_vbus { +- gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-pcduino3-nano.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-pcduino3-nano.dts +deleted file mode 100644 +index e40ecb48d726..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-pcduino3-nano.dts ++++ /dev/null +@@ -1,225 +0,0 @@ +-/* +- * Copyright 2015-2020 Adam Sampson +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +-#include +-#include +- +-/ { +- model = "LinkSprite pcDuino3 Nano"; +- compatible = "linksprite,pcduino3-nano", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-3 { +- label = "pcduino3-nano:green:usr1"; +- gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; /* PH16 */ +- }; +- +- led-4 { +- label = "pcduino3-nano:green:usr2"; +- gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; /* PH15 */ +- }; +- }; +-}; +- +-&ahci { +- target-supply = <®_ahci_5v>; +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pin>; +- status = "okay"; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_ahci_5v { +- gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ +- status = "okay"; +-}; +- +-#include "axp209.dtsi" +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-pll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-/* A single regulator (U24) powers both USB host ports. */ +-®_usb1_vbus { +- gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */ +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-pcduino3.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-pcduino3.dts +deleted file mode 100644 +index 4f8d55d3ba79..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-pcduino3.dts ++++ /dev/null +@@ -1,227 +0,0 @@ +-/* +- * Copyright 2014 Zoltan HERPAI +- * Zoltan HERPAI +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +-#include +- +-/ { +- model = "LinkSprite pcDuino3"; +- compatible = "linksprite,pcduino3", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "pcduino3:green:tx"; +- gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; +- }; +- +- led-1 { +- label = "pcduino3:green:rx"; +- gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- back { +- label = "Key Back"; +- linux,code = ; +- gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; +- }; +- +- home { +- label = "Key Home"; +- linux,code = ; +- gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; +- }; +- +- menu { +- label = "Key Menu"; +- linux,code = ; +- gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&ahci { +- target-supply = <®_ahci_5v>; +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_mii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "mii"; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&ir0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir0_rx_pin>; +- status = "okay"; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_ahci_5v { +- gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-pll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-wexler-tab7200.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-wexler-tab7200.dts +deleted file mode 100644 +index fef02fcbbdf8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-wexler-tab7200.dts ++++ /dev/null +@@ -1,225 +0,0 @@ +-/* +- * Copyright 2015 Aleksei Mamlin +- * Aleksei Mamlin +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +-#include +-#include +- +-/ { +- model = "Wexler TAB7200"; +- compatible = "wexler,tab7200", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; +- brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; +- default-brightness-level = <8>; +- enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ +- power-supply = <®_vcc3v3>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&codec { +- allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-#include "axp209.dtsi" +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +- +- gt911: touchscreen@5d { +- compatible = "goodix,gt911"; +- reg = <0x5d>; +- interrupt-parent = <&pio>; +- interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; /* EINT21 (PH21) */ +- irq-gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* INT (PH21) */ +- reset-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* RST (PB13) */ +- touchscreen-swapped-x-y; +- }; +-}; +- +-&lradc { +- vref-supply = <®_vcc3v0>; +- status = "okay"; +- +- button-571 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <571428>; +- }; +- +- button-761 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <761904>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>; +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1450000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20-wits-pro-a20-dkt.dts b/scripts/dtc/include-prefixes/arm/sun7i-a20-wits-pro-a20-dkt.dts +deleted file mode 100644 +index 3bfae98f3cc3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20-wits-pro-a20-dkt.dts ++++ /dev/null +@@ -1,209 +0,0 @@ +-/* +- * Copyright 2015 Jelle de Jong +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun7i-a20.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +-#include +- +-/ { +- model = "Wits Pro A20 DKT"; +- compatible = "wits,pro-a20-dkt", "allwinner,sun7i-a20"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- mmc3_pwrseq: mmc3_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii"; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-#include "axp209.dtsi" +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ +- status = "okay"; +-}; +- +-&mmc3 { +- vmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&mmc3_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&pio>; +- interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&otg_sram { +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1450000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb0_vbus { +- status = "okay"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun7i-a20.dtsi b/scripts/dtc/include-prefixes/arm/sun7i-a20.dtsi +deleted file mode 100644 +index 5a40e0280665..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun7i-a20.dtsi ++++ /dev/null +@@ -1,1712 +0,0 @@ +-/* +- * Copyright 2013 Maxime Ripard +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &gmac; +- }; +- +- chosen { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- framebuffer-lcd0-hdmi { +- compatible = "allwinner,simple-framebuffer", +- "simple-framebuffer"; +- allwinner,pipeline = "de_be0-lcd0-hdmi"; +- clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, +- <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, +- <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>, +- <&ccu CLK_HDMI>; +- status = "disabled"; +- }; +- +- framebuffer-lcd0 { +- compatible = "allwinner,simple-framebuffer", +- "simple-framebuffer"; +- allwinner,pipeline = "de_be0-lcd0"; +- clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, +- <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>, +- <&ccu CLK_DRAM_DE_BE0>; +- status = "disabled"; +- }; +- +- framebuffer-lcd0-tve0 { +- compatible = "allwinner,simple-framebuffer", +- "simple-framebuffer"; +- allwinner,pipeline = "de_be0-lcd0-tve0"; +- clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, +- <&ccu CLK_AHB_DE_BE0>, +- <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>, +- <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>; +- status = "disabled"; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <0>; +- clocks = <&ccu CLK_CPU>; +- clock-latency = <244144>; /* 8 32k periods */ +- operating-points = < +- /* kHz uV */ +- 960000 1400000 +- 912000 1400000 +- 864000 1300000 +- 720000 1200000 +- 528000 1100000 +- 312000 1000000 +- 144000 1000000 +- >; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <1>; +- clocks = <&ccu CLK_CPU>; +- clock-latency = <244144>; /* 8 32k periods */ +- operating-points = < +- /* kHz uV */ +- 960000 1400000 +- 912000 1400000 +- 864000 1300000 +- 720000 1200000 +- 528000 1100000 +- 312000 1000000 +- 144000 1000000 +- >; +- #cooling-cells = <2>; +- }; +- }; +- +- thermal-zones { +- cpu-thermal { +- /* milliseconds */ +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&rtp>; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- +- trips { +- cpu_alert0: cpu_alert0 { +- /* milliCelsius */ +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_crit: cpu_crit { +- /* milliCelsius */ +- temperature = <100000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ +- default-pool { +- compatible = "shared-dma-pool"; +- size = <0x6000000>; +- alloc-ranges = <0x40000000 0x10000000>; +- reusable; +- linux,cma-default; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupts = , +- ; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- osc24M: clk-24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "osc24M"; +- }; +- +- osc32k: clk-32k { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-output-names = "osc32k"; +- }; +- +- /* +- * The following two are dummy clocks, placeholders +- * used in the gmac_tx clock. The gmac driver will +- * choose one parent depending on the PHY interface +- * mode, using clk_set_rate auto-reparenting. +- * +- * The actual TX clock rate is not controlled by the +- * gmac_tx clock. +- */ +- mii_phy_tx_clk: clk-mii-phy-tx { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25000000>; +- clock-output-names = "mii_phy_tx"; +- }; +- +- gmac_int_tx_clk: clk-gmac-int-tx { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "gmac_int_tx"; +- }; +- +- gmac_tx_clk: clk@1c20164 { +- #clock-cells = <0>; +- compatible = "allwinner,sun7i-a20-gmac-clk"; +- reg = <0x01c20164 0x4>; +- clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; +- clock-output-names = "gmac_tx"; +- }; +- }; +- +- +- de: display-engine { +- compatible = "allwinner,sun7i-a20-display-engine"; +- allwinner,pipelines = <&fe0>, <&fe1>; +- status = "disabled"; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- system-control@1c00000 { +- compatible = "allwinner,sun7i-a20-system-control", +- "allwinner,sun4i-a10-system-control"; +- reg = <0x01c00000 0x30>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- sram_a: sram@0 { +- compatible = "mmio-sram"; +- reg = <0x00000000 0xc000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00000000 0xc000>; +- +- emac_sram: sram-section@8000 { +- compatible = "allwinner,sun7i-a20-sram-a3-a4", +- "allwinner,sun4i-a10-sram-a3-a4"; +- reg = <0x8000 0x4000>; +- status = "disabled"; +- }; +- }; +- +- sram_d: sram@10000 { +- compatible = "mmio-sram"; +- reg = <0x00010000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00010000 0x1000>; +- +- otg_sram: sram-section@0 { +- compatible = "allwinner,sun7i-a20-sram-d", +- "allwinner,sun4i-a10-sram-d"; +- reg = <0x0000 0x1000>; +- status = "disabled"; +- }; +- }; +- +- sram_c: sram@1d00000 { +- compatible = "mmio-sram"; +- reg = <0x01d00000 0xd0000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x01d00000 0xd0000>; +- +- ve_sram: sram-section@0 { +- compatible = "allwinner,sun7i-a20-sram-c1", +- "allwinner,sun4i-a10-sram-c1"; +- reg = <0x000000 0x80000>; +- }; +- }; +- }; +- +- nmi_intc: interrupt-controller@1c00030 { +- compatible = "allwinner,sun7i-a20-sc-nmi"; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x01c00030 0x0c>; +- interrupts = ; +- }; +- +- dma: dma-controller@1c02000 { +- compatible = "allwinner,sun4i-a10-dma"; +- reg = <0x01c02000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB_DMA>; +- #dma-cells = <2>; +- }; +- +- nfc: nand-controller@1c03000 { +- compatible = "allwinner,sun4i-a10-nand"; +- reg = <0x01c03000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; +- clock-names = "ahb", "mod"; +- dmas = <&dma SUN4I_DMA_DEDICATED 3>; +- dma-names = "rxtx"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spi0: spi@1c05000 { +- compatible = "allwinner,sun4i-a10-spi"; +- reg = <0x01c05000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; +- clock-names = "ahb", "mod"; +- dmas = <&dma SUN4I_DMA_DEDICATED 27>, +- <&dma SUN4I_DMA_DEDICATED 26>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- num-cs = <4>; +- }; +- +- spi1: spi@1c06000 { +- compatible = "allwinner,sun4i-a10-spi"; +- reg = <0x01c06000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; +- clock-names = "ahb", "mod"; +- dmas = <&dma SUN4I_DMA_DEDICATED 9>, +- <&dma SUN4I_DMA_DEDICATED 8>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- num-cs = <1>; +- }; +- +- csi0: csi@1c09000 { +- compatible = "allwinner,sun7i-a20-csi0"; +- reg = <0x01c09000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>; +- clock-names = "bus", "isp", "ram"; +- resets = <&ccu RST_CSI0>; +- status = "disabled"; +- }; +- +- emac: ethernet@1c0b000 { +- compatible = "allwinner,sun4i-a10-emac"; +- reg = <0x01c0b000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB_EMAC>; +- allwinner,sram = <&emac_sram 1>; +- status = "disabled"; +- }; +- +- mdio: mdio@1c0b080 { +- compatible = "allwinner,sun4i-a10-mdio"; +- reg = <0x01c0b080 0x14>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- tcon0: lcd-controller@1c0c000 { +- compatible = "allwinner,sun7i-a20-tcon0", +- "allwinner,sun7i-a20-tcon"; +- reg = <0x01c0c000 0x1000>; +- interrupts = ; +- resets = <&ccu RST_TCON0>, <&ccu RST_LVDS>; +- reset-names = "lcd", "lvds"; +- clocks = <&ccu CLK_AHB_LCD0>, +- <&ccu CLK_TCON0_CH0>, +- <&ccu CLK_TCON0_CH1>; +- clock-names = "ahb", +- "tcon-ch0", +- "tcon-ch1"; +- clock-output-names = "tcon0-pixel-clock"; +- #clock-cells = <0>; +- dmas = <&dma SUN4I_DMA_DEDICATED 14>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon0_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- tcon0_in_be0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&be0_out_tcon0>; +- }; +- +- tcon0_in_be1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&be1_out_tcon0>; +- }; +- }; +- +- tcon0_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tcon0_out_hdmi: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&hdmi_in_tcon0>; +- allwinner,tcon-channel = <1>; +- }; +- }; +- }; +- }; +- +- tcon1: lcd-controller@1c0d000 { +- compatible = "allwinner,sun7i-a20-tcon1", +- "allwinner,sun7i-a20-tcon"; +- reg = <0x01c0d000 0x1000>; +- interrupts = ; +- resets = <&ccu RST_TCON1>; +- reset-names = "lcd"; +- clocks = <&ccu CLK_AHB_LCD1>, +- <&ccu CLK_TCON1_CH0>, +- <&ccu CLK_TCON1_CH1>; +- clock-names = "ahb", +- "tcon-ch0", +- "tcon-ch1"; +- clock-output-names = "tcon1-pixel-clock"; +- #clock-cells = <0>; +- dmas = <&dma SUN4I_DMA_DEDICATED 15>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon1_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- tcon1_in_be0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&be0_out_tcon1>; +- }; +- +- tcon1_in_be1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&be1_out_tcon1>; +- }; +- }; +- +- tcon1_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tcon1_out_hdmi: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&hdmi_in_tcon1>; +- allwinner,tcon-channel = <1>; +- }; +- }; +- }; +- }; +- +- video-codec@1c0e000 { +- compatible = "allwinner,sun7i-a20-video-engine"; +- reg = <0x01c0e000 0x1000>; +- clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, +- <&ccu CLK_DRAM_VE>; +- clock-names = "ahb", "mod", "ram"; +- resets = <&ccu RST_VE>; +- interrupts = ; +- allwinner,sram = <&ve_sram 1>; +- }; +- +- mmc0: mmc@1c0f000 { +- compatible = "allwinner,sun7i-a20-mmc"; +- reg = <0x01c0f000 0x1000>; +- clocks = <&ccu CLK_AHB_MMC0>, +- <&ccu CLK_MMC0>, +- <&ccu CLK_MMC0_OUTPUT>, +- <&ccu CLK_MMC0_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc1: mmc@1c10000 { +- compatible = "allwinner,sun7i-a20-mmc"; +- reg = <0x01c10000 0x1000>; +- clocks = <&ccu CLK_AHB_MMC1>, +- <&ccu CLK_MMC1>, +- <&ccu CLK_MMC1_OUTPUT>, +- <&ccu CLK_MMC1_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc2: mmc@1c11000 { +- compatible = "allwinner,sun7i-a20-mmc"; +- reg = <0x01c11000 0x1000>; +- clocks = <&ccu CLK_AHB_MMC2>, +- <&ccu CLK_MMC2>, +- <&ccu CLK_MMC2_OUTPUT>, +- <&ccu CLK_MMC2_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc3: mmc@1c12000 { +- compatible = "allwinner,sun7i-a20-mmc"; +- reg = <0x01c12000 0x1000>; +- clocks = <&ccu CLK_AHB_MMC3>, +- <&ccu CLK_MMC3>, +- <&ccu CLK_MMC3_OUTPUT>, +- <&ccu CLK_MMC3_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc3_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- usb_otg: usb@1c13000 { +- compatible = "allwinner,sun4i-a10-musb"; +- reg = <0x01c13000 0x0400>; +- clocks = <&ccu CLK_AHB_OTG>; +- interrupts = ; +- interrupt-names = "mc"; +- phys = <&usbphy 0>; +- phy-names = "usb"; +- extcon = <&usbphy 0>; +- allwinner,sram = <&otg_sram 1>; +- dr_mode = "otg"; +- status = "disabled"; +- }; +- +- usbphy: phy@1c13400 { +- #phy-cells = <1>; +- compatible = "allwinner,sun7i-a20-usb-phy"; +- reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>; +- reg-names = "phy_ctrl", "pmu1", "pmu2"; +- clocks = <&ccu CLK_USB_PHY>; +- clock-names = "usb_phy"; +- resets = <&ccu RST_USB_PHY0>, +- <&ccu RST_USB_PHY1>, +- <&ccu RST_USB_PHY2>; +- reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; +- status = "disabled"; +- }; +- +- ehci0: usb@1c14000 { +- compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; +- reg = <0x01c14000 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_AHB_EHCI0>; +- phys = <&usbphy 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci0: usb@1c14400 { +- compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; +- reg = <0x01c14400 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; +- phys = <&usbphy 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- crypto: crypto-engine@1c15000 { +- compatible = "allwinner,sun7i-a20-crypto", +- "allwinner,sun4i-a10-crypto"; +- reg = <0x01c15000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; +- clock-names = "ahb", "mod"; +- }; +- +- hdmi: hdmi@1c16000 { +- compatible = "allwinner,sun7i-a20-hdmi", +- "allwinner,sun5i-a10s-hdmi"; +- reg = <0x01c16000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, +- <&ccu CLK_PLL_VIDEO0_2X>, +- <&ccu CLK_PLL_VIDEO1_2X>; +- clock-names = "ahb", "mod", "pll-0", "pll-1"; +- dmas = <&dma SUN4I_DMA_NORMAL 16>, +- <&dma SUN4I_DMA_NORMAL 16>, +- <&dma SUN4I_DMA_DEDICATED 24>; +- dma-names = "ddc-tx", "ddc-rx", "audio-tx"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- hdmi_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- hdmi_in_tcon0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&tcon0_out_hdmi>; +- }; +- +- hdmi_in_tcon1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tcon1_out_hdmi>; +- }; +- }; +- +- hdmi_out: port@1 { +- reg = <1>; +- }; +- }; +- }; +- +- spi2: spi@1c17000 { +- compatible = "allwinner,sun4i-a10-spi"; +- reg = <0x01c17000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; +- clock-names = "ahb", "mod"; +- dmas = <&dma SUN4I_DMA_DEDICATED 29>, +- <&dma SUN4I_DMA_DEDICATED 28>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- num-cs = <1>; +- }; +- +- ahci: sata@1c18000 { +- compatible = "allwinner,sun4i-a10-ahci"; +- reg = <0x01c18000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; +- status = "disabled"; +- }; +- +- ehci1: usb@1c1c000 { +- compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; +- reg = <0x01c1c000 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_AHB_EHCI1>; +- phys = <&usbphy 2>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci1: usb@1c1c400 { +- compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; +- reg = <0x01c1c400 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; +- phys = <&usbphy 2>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- csi1: csi@1c1d000 { +- compatible = "allwinner,sun7i-a20-csi1", +- "allwinner,sun4i-a10-csi1"; +- reg = <0x01c1d000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>; +- clock-names = "bus", "ram"; +- resets = <&ccu RST_CSI1>; +- status = "disabled"; +- }; +- +- spi3: spi@1c1f000 { +- compatible = "allwinner,sun4i-a10-spi"; +- reg = <0x01c1f000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; +- clock-names = "ahb", "mod"; +- dmas = <&dma SUN4I_DMA_DEDICATED 31>, +- <&dma SUN4I_DMA_DEDICATED 30>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- num-cs = <1>; +- }; +- +- ccu: clock@1c20000 { +- compatible = "allwinner,sun7i-a20-ccu"; +- reg = <0x01c20000 0x400>; +- clocks = <&osc24M>, <&osc32k>; +- clock-names = "hosc", "losc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pio: pinctrl@1c20800 { +- compatible = "allwinner,sun7i-a20-pinctrl"; +- reg = <0x01c20800 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; +- clock-names = "apb", "hosc", "losc"; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <3>; +- #gpio-cells = <3>; +- +- /omit-if-no-ref/ +- can_pa_pins: can-pa-pins { +- pins = "PA16", "PA17"; +- function = "can"; +- }; +- +- /omit-if-no-ref/ +- can_ph_pins: can-ph-pins { +- pins = "PH20", "PH21"; +- function = "can"; +- }; +- +- /omit-if-no-ref/ +- clk_out_a_pin: clk-out-a-pin { +- pins = "PI12"; +- function = "clk_out_a"; +- }; +- +- /omit-if-no-ref/ +- clk_out_b_pin: clk-out-b-pin { +- pins = "PI13"; +- function = "clk_out_b"; +- }; +- +- /omit-if-no-ref/ +- csi0_8bits_pins: csi-8bits-pins { +- pins = "PE0", "PE2", "PE3", "PE4", "PE5", +- "PE6", "PE7", "PE8", "PE9", "PE10", +- "PE11"; +- function = "csi0"; +- }; +- +- /omit-if-no-ref/ +- csi0_clk_pin: csi-clk-pin { +- pins = "PE1"; +- function = "csi0"; +- }; +- +- /omit-if-no-ref/ +- csi1_8bits_pg_pins: csi1-8bits-pg-pins { +- pins = "PG0", "PG2", "PG3", "PG4", "PG5", +- "PG6", "PG7", "PG8", "PG9", "PG10", +- "PG11"; +- function = "csi1"; +- }; +- +- /omit-if-no-ref/ +- csi1_24bits_ph_pins: csi1-24bits-ph-pins { +- pins = "PH0", "PH1", "PH2", "PH3", "PH4", +- "PH5", "PH6", "PH7", "PH8", "PH9", +- "PH10", "PH11", "PH12", "PH13", "PH14", +- "PH15", "PH16", "PH17", "PH18", "PH19", +- "PH20", "PH21", "PH22", "PH23", "PH24", +- "PH25", "PH26", "PH27"; +- function = "csi1"; +- }; +- +- /omit-if-no-ref/ +- csi1_clk_pg_pin: csi1-clk-pg-pin { +- pins = "PG1"; +- function = "csi1"; +- }; +- +- /omit-if-no-ref/ +- emac_pa_pins: emac-pa-pins { +- pins = "PA0", "PA1", "PA2", +- "PA3", "PA4", "PA5", "PA6", +- "PA7", "PA8", "PA9", "PA10", +- "PA11", "PA12", "PA13", "PA14", +- "PA15", "PA16"; +- function = "emac"; +- }; +- +- /omit-if-no-ref/ +- emac_ph_pins: emac-ph-pins { +- pins = "PH8", "PH9", "PH10", "PH11", +- "PH14", "PH15", "PH16", "PH17", +- "PH18", "PH19", "PH20", "PH21", +- "PH22", "PH23", "PH24", "PH25", +- "PH26"; +- function = "emac"; +- }; +- +- /omit-if-no-ref/ +- gmac_mii_pins: gmac-mii-pins { +- pins = "PA0", "PA1", "PA2", +- "PA3", "PA4", "PA5", "PA6", +- "PA7", "PA8", "PA9", "PA10", +- "PA11", "PA12", "PA13", "PA14", +- "PA15", "PA16"; +- function = "gmac"; +- }; +- +- /omit-if-no-ref/ +- gmac_rgmii_pins: gmac-rgmii-pins { +- pins = "PA0", "PA1", "PA2", +- "PA3", "PA4", "PA5", "PA6", +- "PA7", "PA8", "PA10", +- "PA11", "PA12", "PA13", +- "PA15", "PA16"; +- function = "gmac"; +- /* +- * data lines in RGMII mode use DDR mode +- * and need a higher signal drive strength +- */ +- drive-strength = <40>; +- }; +- +- /omit-if-no-ref/ +- i2c0_pins: i2c0-pins { +- pins = "PB0", "PB1"; +- function = "i2c0"; +- }; +- +- /omit-if-no-ref/ +- i2c1_pins: i2c1-pins { +- pins = "PB18", "PB19"; +- function = "i2c1"; +- }; +- +- /omit-if-no-ref/ +- i2c2_pins: i2c2-pins { +- pins = "PB20", "PB21"; +- function = "i2c2"; +- }; +- +- /omit-if-no-ref/ +- i2c3_pins: i2c3-pins { +- pins = "PI0", "PI1"; +- function = "i2c3"; +- }; +- +- /omit-if-no-ref/ +- ir0_rx_pin: ir0-rx-pin { +- pins = "PB4"; +- function = "ir0"; +- }; +- +- /omit-if-no-ref/ +- ir0_tx_pin: ir0-tx-pin { +- pins = "PB3"; +- function = "ir0"; +- }; +- +- /omit-if-no-ref/ +- ir1_rx_pin: ir1-rx-pin { +- pins = "PB23"; +- function = "ir1"; +- }; +- +- /omit-if-no-ref/ +- ir1_tx_pin: ir1-tx-pin { +- pins = "PB22"; +- function = "ir1"; +- }; +- +- /omit-if-no-ref/ +- lcd_lvds0_pins: lcd-lvds0-pins { +- pins = "PD0", "PD1", "PD2", "PD3", "PD4", +- "PD5", "PD6", "PD7", "PD8", "PD9"; +- function = "lvds0"; +- }; +- +- /omit-if-no-ref/ +- lcd_lvds1_pins: lcd-lvds1-pins { +- pins = "PD10", "PD11", "PD12", "PD13", "PD14", +- "PD15", "PD16", "PD17", "PD18", "PD19"; +- function = "lvds1"; +- }; +- +- /omit-if-no-ref/ +- mmc0_pins: mmc0-pins { +- pins = "PF0", "PF1", "PF2", +- "PF3", "PF4", "PF5"; +- function = "mmc0"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- /omit-if-no-ref/ +- mmc2_pins: mmc2-pins { +- pins = "PC6", "PC7", "PC8", +- "PC9", "PC10", "PC11"; +- function = "mmc2"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- /omit-if-no-ref/ +- mmc3_pins: mmc3-pins { +- pins = "PI4", "PI5", "PI6", +- "PI7", "PI8", "PI9"; +- function = "mmc3"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- /omit-if-no-ref/ +- ps2_0_pins: ps2-0-pins { +- pins = "PI20", "PI21"; +- function = "ps2"; +- }; +- +- /omit-if-no-ref/ +- ps2_1_ph_pins: ps2-1-ph-pins { +- pins = "PH12", "PH13"; +- function = "ps2"; +- }; +- +- /omit-if-no-ref/ +- pwm0_pin: pwm0-pin { +- pins = "PB2"; +- function = "pwm"; +- }; +- +- /omit-if-no-ref/ +- pwm1_pin: pwm1-pin { +- pins = "PI3"; +- function = "pwm"; +- }; +- +- /omit-if-no-ref/ +- spdif_tx_pin: spdif-tx-pin { +- pins = "PB13"; +- function = "spdif"; +- bias-pull-up; +- }; +- +- /omit-if-no-ref/ +- spi0_pi_pins: spi0-pi-pins { +- pins = "PI11", "PI12", "PI13"; +- function = "spi0"; +- }; +- +- /omit-if-no-ref/ +- spi0_cs0_pi_pin: spi0-cs0-pi-pin { +- pins = "PI10"; +- function = "spi0"; +- }; +- +- /omit-if-no-ref/ +- spi0_cs1_pi_pin: spi0-cs1-pi-pin { +- pins = "PI14"; +- function = "spi0"; +- }; +- +- /omit-if-no-ref/ +- spi1_pi_pins: spi1-pi-pins { +- pins = "PI17", "PI18", "PI19"; +- function = "spi1"; +- }; +- +- /omit-if-no-ref/ +- spi1_cs0_pi_pin: spi1-cs0-pi-pin { +- pins = "PI16"; +- function = "spi1"; +- }; +- +- /omit-if-no-ref/ +- spi2_pb_pins: spi2-pb-pins { +- pins = "PB15", "PB16", "PB17"; +- function = "spi2"; +- }; +- +- /omit-if-no-ref/ +- spi2_cs0_pb_pin: spi2-cs0-pb-pin { +- pins = "PB14"; +- function = "spi2"; +- }; +- +- /omit-if-no-ref/ +- spi2_pc_pins: spi2-pc-pins { +- pins = "PC20", "PC21", "PC22"; +- function = "spi2"; +- }; +- +- /omit-if-no-ref/ +- spi2_cs0_pc_pin: spi2-cs0-pc-pin { +- pins = "PC19"; +- function = "spi2"; +- }; +- +- /omit-if-no-ref/ +- uart0_pb_pins: uart0-pb-pins { +- pins = "PB22", "PB23"; +- function = "uart0"; +- }; +- +- /omit-if-no-ref/ +- uart0_pf_pins: uart0-pf-pins { +- pins = "PF2", "PF4"; +- function = "uart0"; +- }; +- +- /omit-if-no-ref/ +- uart1_pa_pins: uart1-pa-pins { +- pins = "PA10", "PA11"; +- function = "uart1"; +- }; +- +- /omit-if-no-ref/ +- uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins { +- pins = "PA12", "PA13"; +- function = "uart1"; +- }; +- +- /omit-if-no-ref/ +- uart2_pa_pins: uart2-pa-pins { +- pins = "PA2", "PA3"; +- function = "uart2"; +- }; +- +- /omit-if-no-ref/ +- uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins { +- pins = "PA0", "PA1"; +- function = "uart2"; +- }; +- +- /omit-if-no-ref/ +- uart2_pi_pins: uart2-pi-pins { +- pins = "PI18", "PI19"; +- function = "uart2"; +- }; +- +- /omit-if-no-ref/ +- uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins { +- pins = "PI16", "PI17"; +- function = "uart2"; +- }; +- +- /omit-if-no-ref/ +- uart3_pg_pins: uart3-pg-pins { +- pins = "PG6", "PG7"; +- function = "uart3"; +- }; +- +- /omit-if-no-ref/ +- uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins { +- pins = "PG8", "PG9"; +- function = "uart3"; +- }; +- +- /omit-if-no-ref/ +- uart3_ph_pins: uart3-ph-pins { +- pins = "PH0", "PH1"; +- function = "uart3"; +- }; +- +- /omit-if-no-ref/ +- uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins { +- pins = "PH2", "PH3"; +- function = "uart3"; +- }; +- +- /omit-if-no-ref/ +- uart4_pg_pins: uart4-pg-pins { +- pins = "PG10", "PG11"; +- function = "uart4"; +- }; +- +- /omit-if-no-ref/ +- uart4_ph_pins: uart4-ph-pins { +- pins = "PH4", "PH5"; +- function = "uart4"; +- }; +- +- /omit-if-no-ref/ +- uart5_ph_pins: uart5-ph-pins { +- pins = "PH6", "PH7"; +- function = "uart5"; +- }; +- +- /omit-if-no-ref/ +- uart5_pi_pins: uart5-pi-pins { +- pins = "PI10", "PI11"; +- function = "uart5"; +- }; +- +- /omit-if-no-ref/ +- uart6_pa_pins: uart6-pa-pins { +- pins = "PA12", "PA13"; +- function = "uart6"; +- }; +- +- /omit-if-no-ref/ +- uart6_pi_pins: uart6-pi-pins { +- pins = "PI12", "PI13"; +- function = "uart6"; +- }; +- +- /omit-if-no-ref/ +- uart7_pa_pins: uart7-pa-pins { +- pins = "PA14", "PA15"; +- function = "uart7"; +- }; +- +- /omit-if-no-ref/ +- uart7_pi_pins: uart7-pi-pins { +- pins = "PI20", "PI21"; +- function = "uart7"; +- }; +- }; +- +- timer@1c20c00 { +- compatible = "allwinner,sun4i-a10-timer"; +- reg = <0x01c20c00 0x90>; +- interrupts = , +- , +- , +- , +- , +- ; +- clocks = <&osc24M>; +- }; +- +- wdt: watchdog@1c20c90 { +- compatible = "allwinner,sun4i-a10-wdt"; +- reg = <0x01c20c90 0x10>; +- interrupts = ; +- clocks = <&osc24M>; +- }; +- +- rtc: rtc@1c20d00 { +- compatible = "allwinner,sun7i-a20-rtc"; +- reg = <0x01c20d00 0x20>; +- interrupts = ; +- }; +- +- pwm: pwm@1c20e00 { +- compatible = "allwinner,sun7i-a20-pwm"; +- reg = <0x01c20e00 0xc>; +- clocks = <&osc24M>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- spdif: spdif@1c21000 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun4i-a10-spdif"; +- reg = <0x01c21000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; +- clock-names = "apb", "spdif"; +- dmas = <&dma SUN4I_DMA_NORMAL 2>, +- <&dma SUN4I_DMA_NORMAL 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ir0: ir@1c21800 { +- compatible = "allwinner,sun4i-a10-ir"; +- clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; +- clock-names = "apb", "ir"; +- interrupts = ; +- reg = <0x01c21800 0x40>; +- status = "disabled"; +- }; +- +- ir1: ir@1c21c00 { +- compatible = "allwinner,sun4i-a10-ir"; +- clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; +- clock-names = "apb", "ir"; +- interrupts = ; +- reg = <0x01c21c00 0x40>; +- status = "disabled"; +- }; +- +- i2s1: i2s@1c22000 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun4i-a10-i2s"; +- reg = <0x01c22000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>; +- clock-names = "apb", "mod"; +- dmas = <&dma SUN4I_DMA_NORMAL 4>, +- <&dma SUN4I_DMA_NORMAL 4>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2s0: i2s@1c22400 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun4i-a10-i2s"; +- reg = <0x01c22400 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; +- clock-names = "apb", "mod"; +- dmas = <&dma SUN4I_DMA_NORMAL 3>, +- <&dma SUN4I_DMA_NORMAL 3>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- lradc: lradc@1c22800 { +- compatible = "allwinner,sun4i-a10-lradc-keys"; +- reg = <0x01c22800 0x100>; +- interrupts = ; +- status = "disabled"; +- }; +- +- codec: codec@1c22c00 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun7i-a20-codec"; +- reg = <0x01c22c00 0x40>; +- interrupts = ; +- clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; +- clock-names = "apb", "codec"; +- dmas = <&dma SUN4I_DMA_NORMAL 19>, +- <&dma SUN4I_DMA_NORMAL 19>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sid: eeprom@1c23800 { +- compatible = "allwinner,sun7i-a20-sid"; +- reg = <0x01c23800 0x200>; +- }; +- +- i2s2: i2s@1c24400 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun4i-a10-i2s"; +- reg = <0x01c24400 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>; +- clock-names = "apb", "mod"; +- dmas = <&dma SUN4I_DMA_NORMAL 6>, +- <&dma SUN4I_DMA_NORMAL 6>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- rtp: rtp@1c25000 { +- compatible = "allwinner,sun5i-a13-ts"; +- reg = <0x01c25000 0x100>; +- interrupts = ; +- #thermal-sensor-cells = <0>; +- }; +- +- uart0: serial@1c28000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART0>; +- status = "disabled"; +- }; +- +- uart1: serial@1c28400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28400 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART1>; +- status = "disabled"; +- }; +- +- uart2: serial@1c28800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28800 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART2>; +- status = "disabled"; +- }; +- +- uart3: serial@1c28c00 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28c00 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART3>; +- status = "disabled"; +- }; +- +- uart4: serial@1c29000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c29000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART4>; +- status = "disabled"; +- }; +- +- uart5: serial@1c29400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c29400 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART5>; +- status = "disabled"; +- }; +- +- uart6: serial@1c29800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c29800 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART6>; +- status = "disabled"; +- }; +- +- uart7: serial@1c29c00 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c29c00 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_APB1_UART7>; +- status = "disabled"; +- }; +- +- ps20: ps2@1c2a000 { +- compatible = "allwinner,sun4i-a10-ps2"; +- reg = <0x01c2a000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB1_PS20>; +- status = "disabled"; +- }; +- +- ps21: ps2@1c2a400 { +- compatible = "allwinner,sun4i-a10-ps2"; +- reg = <0x01c2a400 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB1_PS21>; +- status = "disabled"; +- }; +- +- i2c0: i2c@1c2ac00 { +- compatible = "allwinner,sun7i-a20-i2c", +- "allwinner,sun4i-a10-i2c"; +- reg = <0x01c2ac00 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB1_I2C0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c1: i2c@1c2b000 { +- compatible = "allwinner,sun7i-a20-i2c", +- "allwinner,sun4i-a10-i2c"; +- reg = <0x01c2b000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB1_I2C1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c2: i2c@1c2b400 { +- compatible = "allwinner,sun7i-a20-i2c", +- "allwinner,sun4i-a10-i2c"; +- reg = <0x01c2b400 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB1_I2C2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c3: i2c@1c2b800 { +- compatible = "allwinner,sun7i-a20-i2c", +- "allwinner,sun4i-a10-i2c"; +- reg = <0x01c2b800 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB1_I2C3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- can0: can@1c2bc00 { +- compatible = "allwinner,sun7i-a20-can", +- "allwinner,sun4i-a10-can"; +- reg = <0x01c2bc00 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB1_CAN>; +- status = "disabled"; +- }; +- +- i2c4: i2c@1c2c000 { +- compatible = "allwinner,sun7i-a20-i2c", +- "allwinner,sun4i-a10-i2c"; +- reg = <0x01c2c000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_APB1_I2C4>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mali: gpu@1c40000 { +- compatible = "allwinner,sun7i-a20-mali", "arm,mali-400"; +- reg = <0x01c40000 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "gp", +- "gpmmu", +- "pp0", +- "ppmmu0", +- "pp1", +- "ppmmu1", +- "pmu"; +- clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; +- clock-names = "bus", "core"; +- resets = <&ccu RST_GPU>; +- +- assigned-clocks = <&ccu CLK_GPU>; +- assigned-clock-rates = <384000000>; +- }; +- +- gmac: ethernet@1c50000 { +- compatible = "allwinner,sun7i-a20-gmac"; +- reg = <0x01c50000 0x10000>; +- interrupts = ; +- interrupt-names = "macirq"; +- clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>; +- clock-names = "stmmaceth", "allwinner_gmac_tx"; +- snps,pbl = <2>; +- snps,fixed-burst; +- snps,force_sf_dma_mode; +- status = "disabled"; +- +- gmac_mdio: mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- hstimer@1c60000 { +- compatible = "allwinner,sun7i-a20-hstimer"; +- reg = <0x01c60000 0x1000>; +- interrupts = , +- , +- , +- ; +- clocks = <&ccu CLK_AHB_HSTIMER>; +- }; +- +- gic: interrupt-controller@1c81000 { +- compatible = "arm,gic-400"; +- reg = <0x01c81000 0x1000>, +- <0x01c82000 0x2000>, +- <0x01c84000 0x2000>, +- <0x01c86000 0x2000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = ; +- }; +- +- fe0: display-frontend@1e00000 { +- compatible = "allwinner,sun7i-a20-display-frontend"; +- reg = <0x01e00000 0x20000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, +- <&ccu CLK_DRAM_DE_FE0>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&ccu RST_DE_FE0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- fe0_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- fe0_out_be0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&be0_in_fe0>; +- }; +- +- fe0_out_be1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&be1_in_fe0>; +- }; +- }; +- }; +- }; +- +- fe1: display-frontend@1e20000 { +- compatible = "allwinner,sun7i-a20-display-frontend"; +- reg = <0x01e20000 0x20000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, +- <&ccu CLK_DRAM_DE_FE1>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&ccu RST_DE_FE1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- fe1_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- fe1_out_be0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&be0_in_fe1>; +- }; +- +- fe1_out_be1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&be1_in_fe1>; +- }; +- }; +- }; +- }; +- +- be1: display-backend@1e40000 { +- compatible = "allwinner,sun7i-a20-display-backend"; +- reg = <0x01e40000 0x10000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, +- <&ccu CLK_DRAM_DE_BE1>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&ccu RST_DE_BE1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- be1_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- be1_in_fe0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&fe0_out_be1>; +- }; +- +- be1_in_fe1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&fe1_out_be1>; +- }; +- }; +- +- be1_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- be1_out_tcon0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&tcon0_in_be1>; +- }; +- +- be1_out_tcon1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tcon1_in_be1>; +- }; +- }; +- }; +- }; +- +- be0: display-backend@1e60000 { +- compatible = "allwinner,sun7i-a20-display-backend"; +- reg = <0x01e60000 0x10000>; +- interrupts = ; +- clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, +- <&ccu CLK_DRAM_DE_BE0>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&ccu RST_DE_BE0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- be0_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- be0_in_fe0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&fe0_out_be0>; +- }; +- +- be0_in_fe1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&fe1_out_be0>; +- }; +- }; +- +- be0_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- be0_out_tcon0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&tcon0_in_be0>; +- }; +- +- be0_out_tcon1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tcon1_in_be0>; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a23-a33.dtsi b/scripts/dtc/include-prefixes/arm/sun8i-a23-a33.dtsi +deleted file mode 100644 +index 4461d5098b20..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a23-a33.dtsi ++++ /dev/null +@@ -1,854 +0,0 @@ +-/* +- * Copyright 2014 Chen-Yu Tsai +- * +- * Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +- +-#include +-#include +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- chosen { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- simplefb_lcd: framebuffer-lcd0 { +- compatible = "allwinner,simple-framebuffer", +- "simple-framebuffer"; +- allwinner,pipeline = "de_be0-lcd0"; +- clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>, +- <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>, +- <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>; +- status = "disabled"; +- }; +- }; +- +- de: display-engine { +- /* compatible gets set in SoC specific dtsi file */ +- allwinner,pipelines = <&fe0>; +- status = "disabled"; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- clock-frequency = <24000000>; +- arm,cpu-registers-not-fw-configured; +- }; +- +- cpus { +- enable-method = "allwinner,sun8i-a23"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <0>; +- }; +- +- cpu@1 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <1>; +- }; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- osc24M: osc24M_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-accuracy = <50000>; +- clock-output-names = "osc24M"; +- }; +- +- ext_osc32k: ext_osc32k_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-accuracy = <50000>; +- clock-output-names = "ext-osc32k"; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- system-control@1c00000 { +- compatible = "allwinner,sun8i-a23-system-control"; +- reg = <0x01c00000 0x30>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- sram_c: sram@1d00000 { +- compatible = "mmio-sram"; +- reg = <0x01d00000 0x80000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x01d00000 0x80000>; +- +- ve_sram: sram-section@0 { +- compatible = "allwinner,sun8i-a23-sram-c1", +- "allwinner,sun4i-a10-sram-c1"; +- reg = <0x000000 0x80000>; +- }; +- }; +- }; +- +- dma: dma-controller@1c02000 { +- compatible = "allwinner,sun8i-a23-dma"; +- reg = <0x01c02000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_DMA>; +- resets = <&ccu RST_BUS_DMA>; +- #dma-cells = <1>; +- }; +- +- nfc: nand-controller@1c03000 { +- compatible = "allwinner,sun8i-a23-nand-controller"; +- reg = <0x01c03000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; +- clock-names = "ahb", "mod"; +- resets = <&ccu RST_BUS_NAND>; +- reset-names = "ahb"; +- dmas = <&dma 5>; +- dma-names = "rxtx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- tcon0: lcd-controller@1c0c000 { +- /* compatible gets set in SoC specific dtsi file */ +- reg = <0x01c0c000 0x1000>; +- interrupts = ; +- dmas = <&dma 12>; +- clocks = <&ccu CLK_BUS_LCD>, +- <&ccu CLK_LCD_CH0>, +- <&ccu 13>; +- clock-names = "ahb", +- "tcon-ch0", +- "lvds-alt"; +- clock-output-names = "tcon-pixel-clock"; +- #clock-cells = <0>; +- resets = <&ccu RST_BUS_LCD>, +- <&ccu RST_BUS_LVDS>; +- reset-names = "lcd", +- "lvds"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon0_in: port@0 { +- reg = <0>; +- +- tcon0_in_drc0: endpoint { +- remote-endpoint = <&drc0_out_tcon0>; +- }; +- }; +- +- tcon0_out: port@1 { +- reg = <1>; +- }; +- }; +- }; +- +- mmc0: mmc@1c0f000 { +- compatible = "allwinner,sun7i-a20-mmc"; +- reg = <0x01c0f000 0x1000>; +- clocks = <&ccu CLK_BUS_MMC0>, +- <&ccu CLK_MMC0>, +- <&ccu CLK_MMC0_OUTPUT>, +- <&ccu CLK_MMC0_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- resets = <&ccu RST_BUS_MMC0>; +- reset-names = "ahb"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc1: mmc@1c10000 { +- compatible = "allwinner,sun7i-a20-mmc"; +- reg = <0x01c10000 0x1000>; +- clocks = <&ccu CLK_BUS_MMC1>, +- <&ccu CLK_MMC1>, +- <&ccu CLK_MMC1_OUTPUT>, +- <&ccu CLK_MMC1_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- resets = <&ccu RST_BUS_MMC1>; +- reset-names = "ahb"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc2: mmc@1c11000 { +- compatible = "allwinner,sun7i-a20-mmc"; +- reg = <0x01c11000 0x1000>; +- clocks = <&ccu CLK_BUS_MMC2>, +- <&ccu CLK_MMC2>, +- <&ccu CLK_MMC2_OUTPUT>, +- <&ccu CLK_MMC2_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- resets = <&ccu RST_BUS_MMC2>; +- reset-names = "ahb"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- usb_otg: usb@1c19000 { +- /* compatible gets set in SoC specific dtsi file */ +- reg = <0x01c19000 0x0400>; +- clocks = <&ccu CLK_BUS_OTG>; +- resets = <&ccu RST_BUS_OTG>; +- interrupts = ; +- interrupt-names = "mc"; +- phys = <&usbphy 0>; +- phy-names = "usb"; +- extcon = <&usbphy 0>; +- dr_mode = "otg"; +- status = "disabled"; +- }; +- +- usbphy: phy@1c19400 { +- /* +- * compatible and address regions get set in +- * SoC specific dtsi file +- */ +- clocks = <&ccu CLK_USB_PHY0>, +- <&ccu CLK_USB_PHY1>; +- clock-names = "usb0_phy", +- "usb1_phy"; +- resets = <&ccu RST_USB_PHY0>, +- <&ccu RST_USB_PHY1>; +- reset-names = "usb0_reset", +- "usb1_reset"; +- status = "disabled"; +- #phy-cells = <1>; +- }; +- +- ehci0: usb@1c1a000 { +- compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; +- reg = <0x01c1a000 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_EHCI>; +- resets = <&ccu RST_BUS_EHCI>; +- phys = <&usbphy 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci0: usb@1c1a400 { +- compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; +- reg = <0x01c1a400 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>; +- resets = <&ccu RST_BUS_OHCI>; +- phys = <&usbphy 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ccu: clock@1c20000 { +- reg = <0x01c20000 0x400>; +- clocks = <&osc24M>, <&rtc 0>; +- clock-names = "hosc", "losc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pio: pinctrl@1c20800 { +- /* compatible gets set in SoC specific dtsi file */ +- reg = <0x01c20800 0x400>; +- interrupt-parent = <&r_intc>; +- /* interrupts get set in SoC specific dtsi file */ +- clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; +- clock-names = "apb", "hosc", "losc"; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <3>; +- #gpio-cells = <3>; +- +- i2c0_pins: i2c0-pins { +- pins = "PH2", "PH3"; +- function = "i2c0"; +- }; +- +- i2c1_pins: i2c1-pins { +- pins = "PH4", "PH5"; +- function = "i2c1"; +- }; +- +- i2c2_pins: i2c2-pins { +- pins = "PE12", "PE13"; +- function = "i2c2"; +- }; +- +- lcd_rgb666_pins: lcd-rgb666-pins { +- pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", +- "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", +- "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", +- "PD24", "PD25", "PD26", "PD27"; +- function = "lcd0"; +- }; +- +- mmc0_pins: mmc0-pins { +- pins = "PF0", "PF1", "PF2", +- "PF3", "PF4", "PF5"; +- function = "mmc0"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc1_pg_pins: mmc1-pg-pins { +- pins = "PG0", "PG1", "PG2", +- "PG3", "PG4", "PG5"; +- function = "mmc1"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc2_8bit_pins: mmc2-8bit-pins { +- pins = "PC5", "PC6", "PC8", +- "PC9", "PC10", "PC11", +- "PC12", "PC13", "PC14", +- "PC15", "PC16"; +- function = "mmc2"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- nand_pins: nand-pins { +- pins = "PC0", "PC1", "PC2", "PC5", +- "PC8", "PC9", "PC10", "PC11", +- "PC12", "PC13", "PC14", "PC15"; +- function = "nand0"; +- }; +- +- nand_cs0_pin: nand-cs0-pin { +- pins = "PC4"; +- function = "nand0"; +- bias-pull-up; +- }; +- +- nand_cs1_pin: nand-cs1-pin { +- pins = "PC3"; +- function = "nand0"; +- bias-pull-up; +- }; +- +- nand_rb0_pin: nand-rb0-pin { +- pins = "PC6"; +- function = "nand0"; +- bias-pull-up; +- }; +- +- nand_rb1_pin: nand-rb1-pin { +- pins = "PC7"; +- function = "nand0"; +- bias-pull-up; +- }; +- +- pwm0_pin: pwm0-pin { +- pins = "PH0"; +- function = "pwm0"; +- }; +- +- uart0_pf_pins: uart0-pf-pins { +- pins = "PF2", "PF4"; +- function = "uart0"; +- }; +- +- uart1_pg_pins: uart1-pg-pins { +- pins = "PG6", "PG7"; +- function = "uart1"; +- }; +- +- uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins { +- pins = "PG8", "PG9"; +- function = "uart1"; +- }; +- }; +- +- timer@1c20c00 { +- compatible = "allwinner,sun8i-a23-timer"; +- reg = <0x01c20c00 0xa0>; +- interrupts = , +- ; +- clocks = <&osc24M>; +- }; +- +- wdt0: watchdog@1c20ca0 { +- compatible = "allwinner,sun6i-a31-wdt"; +- reg = <0x01c20ca0 0x20>; +- interrupts = ; +- clocks = <&osc24M>; +- }; +- +- pwm: pwm@1c21400 { +- compatible = "allwinner,sun7i-a20-pwm"; +- reg = <0x01c21400 0xc>; +- clocks = <&osc24M>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- lradc: lradc@1c22800 { +- compatible = "allwinner,sun4i-a10-lradc-keys"; +- reg = <0x01c22800 0x100>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart0: serial@1c28000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART0>; +- resets = <&ccu RST_BUS_UART0>; +- dmas = <&dma 6>, <&dma 6>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart1: serial@1c28400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28400 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART1>; +- resets = <&ccu RST_BUS_UART1>; +- dmas = <&dma 7>, <&dma 7>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart2: serial@1c28800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28800 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART2>; +- resets = <&ccu RST_BUS_UART2>; +- dmas = <&dma 8>, <&dma 8>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart3: serial@1c28c00 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28c00 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART3>; +- resets = <&ccu RST_BUS_UART3>; +- dmas = <&dma 9>, <&dma 9>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart4: serial@1c29000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c29000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART4>; +- resets = <&ccu RST_BUS_UART4>; +- dmas = <&dma 10>, <&dma 10>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c0: i2c@1c2ac00 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2ac00 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C0>; +- resets = <&ccu RST_BUS_I2C0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c1: i2c@1c2b000 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2b000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C1>; +- resets = <&ccu RST_BUS_I2C1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c2: i2c@1c2b400 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2b400 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C2>; +- resets = <&ccu RST_BUS_I2C2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mali: gpu@1c40000 { +- compatible = "allwinner,sun8i-a23-mali", +- "allwinner,sun7i-a20-mali", "arm,mali-400"; +- reg = <0x01c40000 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "gp", +- "gpmmu", +- "pp0", +- "ppmmu0", +- "pp1", +- "ppmmu1", +- "pmu"; +- clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; +- clock-names = "bus", "core"; +- resets = <&ccu RST_BUS_GPU>; +- #cooling-cells = <2>; +- +- assigned-clocks = <&ccu CLK_GPU>; +- assigned-clock-rates = <384000000>; +- }; +- +- gic: interrupt-controller@1c81000 { +- compatible = "arm,gic-400"; +- reg = <0x01c81000 0x1000>, +- <0x01c82000 0x2000>, +- <0x01c84000 0x2000>, +- <0x01c86000 0x2000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = ; +- }; +- +- fe0: display-frontend@1e00000 { +- /* compatible gets set in SoC specific dtsi file */ +- reg = <0x01e00000 0x20000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>, +- <&ccu CLK_DRAM_DE_FE>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&ccu RST_BUS_DE_FE>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- fe0_out: port@1 { +- reg = <1>; +- +- fe0_out_be0: endpoint { +- remote-endpoint = <&be0_in_fe0>; +- }; +- }; +- }; +- }; +- +- be0: display-backend@1e60000 { +- /* compatible gets set in SoC specific dtsi file */ +- reg = <0x01e60000 0x10000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, +- <&ccu CLK_DRAM_DE_BE>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&ccu RST_BUS_DE_BE>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- be0_in: port@0 { +- reg = <0>; +- +- be0_in_fe0: endpoint { +- remote-endpoint = <&fe0_out_be0>; +- }; +- }; +- +- be0_out: port@1 { +- reg = <1>; +- +- be0_out_drc0: endpoint { +- remote-endpoint = <&drc0_in_be0>; +- }; +- }; +- }; +- }; +- +- drc0: drc@1e70000 { +- /* compatible gets set in SoC specific dtsi file */ +- reg = <0x01e70000 0x10000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>, +- <&ccu CLK_DRAM_DRC>; +- clock-names = "ahb", "mod", "ram"; +- resets = <&ccu RST_BUS_DRC>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- drc0_in: port@0 { +- reg = <0>; +- +- drc0_in_be0: endpoint { +- remote-endpoint = <&be0_out_drc0>; +- }; +- }; +- +- drc0_out: port@1 { +- reg = <1>; +- +- drc0_out_tcon0: endpoint { +- remote-endpoint = <&tcon0_in_drc0>; +- }; +- }; +- }; +- }; +- +- rtc: rtc@1f00000 { +- compatible = "allwinner,sun8i-a23-rtc"; +- reg = <0x01f00000 0x400>; +- interrupt-parent = <&r_intc>; +- interrupts = , +- ; +- clock-output-names = "osc32k", "osc32k-out"; +- clocks = <&ext_osc32k>; +- #clock-cells = <1>; +- }; +- +- r_intc: interrupt-controller@1f00c00 { +- compatible = "allwinner,sun6i-a31-r-intc"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x01f00c00 0x400>; +- interrupts = ; +- }; +- +- prcm@1f01400 { +- compatible = "allwinner,sun8i-a23-prcm"; +- reg = <0x01f01400 0x200>; +- +- ar100: ar100_clk { +- compatible = "fixed-factor-clock"; +- #clock-cells = <0>; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&osc24M>; +- clock-output-names = "ar100"; +- }; +- +- ahb0: ahb0_clk { +- compatible = "fixed-factor-clock"; +- #clock-cells = <0>; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&ar100>; +- clock-output-names = "ahb0"; +- }; +- +- apb0: apb0_clk { +- compatible = "allwinner,sun8i-a23-apb0-clk"; +- #clock-cells = <0>; +- clocks = <&ahb0>; +- clock-output-names = "apb0"; +- }; +- +- apb0_gates: apb0_gates_clk { +- compatible = "allwinner,sun8i-a23-apb0-gates-clk"; +- #clock-cells = <1>; +- clocks = <&apb0>; +- clock-output-names = "apb0_pio", "apb0_timer", +- "apb0_rsb", "apb0_uart", +- "apb0_i2c"; +- }; +- +- apb0_rst: apb0_rst { +- compatible = "allwinner,sun6i-a31-clock-reset"; +- #reset-cells = <1>; +- }; +- +- codec_analog: codec-analog { +- compatible = "allwinner,sun8i-a23-codec-analog"; +- }; +- }; +- +- cpucfg@1f01c00 { +- compatible = "allwinner,sun8i-a23-cpuconfig"; +- reg = <0x01f01c00 0x300>; +- }; +- +- r_uart: serial@1f02800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01f02800 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&apb0_gates 4>; +- resets = <&apb0_rst 4>; +- status = "disabled"; +- }; +- +- r_i2c: i2c@1f02400 { +- compatible = "allwinner,sun8i-a23-i2c", +- "allwinner,sun6i-a31-i2c"; +- reg = <0x01f02400 0x400>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&r_i2c_pins>; +- clocks = <&apb0_gates 6>; +- resets = <&apb0_rst 6>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- r_pio: pinctrl@1f02c00 { +- compatible = "allwinner,sun8i-a23-r-pinctrl"; +- reg = <0x01f02c00 0x400>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; +- clock-names = "apb", "hosc", "losc"; +- resets = <&apb0_rst 0>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <3>; +- #gpio-cells = <3>; +- +- r_i2c_pins: r-i2c-pins { +- pins = "PL0", "PL1"; +- function = "s_i2c"; +- bias-pull-up; +- }; +- +- r_rsb_pins: r-rsb-pins { +- pins = "PL0", "PL1"; +- function = "s_rsb"; +- drive-strength = <20>; +- bias-pull-up; +- }; +- +- r_uart_pins_a: r-uart-pins { +- pins = "PL2", "PL3"; +- function = "s_uart"; +- }; +- }; +- +- r_rsb: rsb@1f03400 { +- compatible = "allwinner,sun8i-a23-rsb"; +- reg = <0x01f03400 0x400>; +- interrupts = ; +- clocks = <&apb0_gates 3>; +- clock-frequency = <3000000>; +- resets = <&apb0_rst 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&r_rsb_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a23-evb.dts b/scripts/dtc/include-prefixes/arm/sun8i-a23-evb.dts +deleted file mode 100644 +index 53fb1be0401a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a23-evb.dts ++++ /dev/null +@@ -1,117 +0,0 @@ +-/* +- * Copyright 2015 Maxime Ripard +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a23.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Allwinner A23 Evaluation Board"; +- compatible = "allwinner,sun8i-a23-evb", "allwinner,sun8i-a23"; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- serial0 = &r_uart; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&lradc { +- vref-supply = <®_vcc3v0>; +- status = "okay"; +- +- button-190 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <190000>; +- }; +- +- button-390 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <390000>; +- }; +- +- button-600 { +- label = "Home"; +- linux,code = ; +- channel = <0>; +- voltage = <600000>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v0>; +- bus-width = <4>; +- cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ +- status = "okay"; +-}; +- +-/* +- * The RX line has a non-populated resistance. In order to use it, you +- * need to solder R207 on the back of the board in order to close the +- * line and get a working UART. +- */ +-&r_uart { +- pinctrl-names = "default"; +- pinctrl-0 = <&r_uart_pins_a>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a23-gt90h-v4.dts b/scripts/dtc/include-prefixes/arm/sun8i-a23-gt90h-v4.dts +deleted file mode 100644 +index bcbc9b0758f9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a23-gt90h-v4.dts ++++ /dev/null +@@ -1,76 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a23.dtsi" +-#include "sun8i-reference-design-tablet.dtsi" +- +-/ { +- model = "Allwinner GT90H Dual Core Tablet (v4)"; +- compatible = "allwinner,gt90h-v4", "allwinner,sun8i-a23"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&touchscreen { +- reg = <0x40>; +- compatible = "silead,gsl3675"; +- firmware-name = "gsl3675-gt90h.fw"; +- touchscreen-size-x = <1792>; +- touchscreen-size-y = <1024>; +- status = "okay"; +-}; +- +-&lradc { +- button-600 { +- label = "Back"; +- linux,code = ; +- channel = <0>; +- voltage = <600000>; +- }; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_dldo1>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a23-inet86dz.dts b/scripts/dtc/include-prefixes/arm/sun8i-a23-inet86dz.dts +deleted file mode 100644 +index d4405752a414..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a23-inet86dz.dts ++++ /dev/null +@@ -1,67 +0,0 @@ +-/* +- * Copyright 2016 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a23.dtsi" +-#include "sun8i-reference-design-tablet.dtsi" +- +-/ { +- model = "INet-86DZ Rev 01"; +- compatible = "primux,inet86dz", "allwinner,sun8i-a23"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&touchscreen { +- reg = <0x40>; +- compatible = "silead,gsl1680"; +- firmware-name = "gsl1680-inet86dz.fw"; +- touchscreen-size-x = <960>; +- touchscreen-size-y = <640>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_dldo1>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a23-ippo-q8h-v1.2.dts b/scripts/dtc/include-prefixes/arm/sun8i-a23-ippo-q8h-v1.2.dts +deleted file mode 100644 +index 51097c77a152..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a23-ippo-q8h-v1.2.dts ++++ /dev/null +@@ -1,73 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a23.dtsi" +-#include "sun8i-q8-common.dtsi" +- +-/ { +- model = "Q8 A23 Tablet"; +- compatible = "allwinner,q8-a23", "allwinner,sun8i-a23"; +-}; +- +-&codec { +- allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ +- allwinner,audio-routing = +- "Headphone", "HP", +- "Headphone", "HPCOM", +- "Speaker", "HP", +- "MIC1", "Mic", +- "MIC2", "Headset Mic", +- "Mic", "MBIAS", +- "Headset Mic", "HBIAS"; +- status = "okay"; +-}; +- +-&panel { +- compatible = "bananapi,s070wv20-ct16"; +-}; +- +-&tcon0_out { +- tcon0_out_lcd: endpoint { +- remote-endpoint = <&panel_input>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a23-ippo-q8h-v5.dts b/scripts/dtc/include-prefixes/arm/sun8i-a23-ippo-q8h-v5.dts +deleted file mode 100644 +index 51097c77a152..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a23-ippo-q8h-v5.dts ++++ /dev/null +@@ -1,73 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a23.dtsi" +-#include "sun8i-q8-common.dtsi" +- +-/ { +- model = "Q8 A23 Tablet"; +- compatible = "allwinner,q8-a23", "allwinner,sun8i-a23"; +-}; +- +-&codec { +- allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ +- allwinner,audio-routing = +- "Headphone", "HP", +- "Headphone", "HPCOM", +- "Speaker", "HP", +- "MIC1", "Mic", +- "MIC2", "Headset Mic", +- "Mic", "MBIAS", +- "Headset Mic", "HBIAS"; +- status = "okay"; +-}; +- +-&panel { +- compatible = "bananapi,s070wv20-ct16"; +-}; +- +-&tcon0_out { +- tcon0_out_lcd: endpoint { +- remote-endpoint = <&panel_input>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a23-polaroid-mid2407pxe03.dts b/scripts/dtc/include-prefixes/arm/sun8i-a23-polaroid-mid2407pxe03.dts +deleted file mode 100644 +index d5f6aebd7216..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a23-polaroid-mid2407pxe03.dts ++++ /dev/null +@@ -1,96 +0,0 @@ +-/* +- * Copyright 2016 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a23.dtsi" +-#include "sun8i-reference-design-tablet.dtsi" +- +-/ { +- model = "Polaroid MID2407PXE03 tablet"; +- compatible = "polaroid,mid2407pxe03", "allwinner,sun8i-a23"; +- +- aliases { +- ethernet0 = &esp8089; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ +- /* The esp8089 needs 200 ms after driving wifi-en high */ +- post-power-on-delay-ms = <200>; +- }; +-}; +- +-&i2c1 { +- mma7660: accelerometer@4c { +- reg = <0x4c>; +- compatible = "fsl,mma7660"; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pg_pins>; +- vmmc-supply = <®_dldo1>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- esp8089: sdio_wifi@1 { +- compatible = "esp,esp8089"; +- reg = <1>; +- esp,crystal-26M-en = <2>; +- }; +-}; +- +-&touchscreen { +- reg = <0x40>; +- compatible = "silead,gsl1680"; +- firmware-name = "gsl1680-polaroid-mid2407pxe03.fw"; +- touchscreen-size-x = <960>; +- touchscreen-size-y = <640>; +- touchscreen-inverted-x; +- touchscreen-inverted-y; +- vddio-supply = <®_ldo_io1>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a23-polaroid-mid2809pxe04.dts b/scripts/dtc/include-prefixes/arm/sun8i-a23-polaroid-mid2809pxe04.dts +deleted file mode 100644 +index 9f9232a2fefb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a23-polaroid-mid2809pxe04.dts ++++ /dev/null +@@ -1,86 +0,0 @@ +-/* +- * Copyright 2016 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a23.dtsi" +-#include "sun8i-reference-design-tablet.dtsi" +- +-/ { +- model = "Polaroid MID2809PXE04 tablet"; +- compatible = "polaroid,mid2809pxe04", "allwinner,sun8i-a23"; +- +- aliases { +- ethernet0 = &esp8089; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ +- /* The esp8089 needs 200 ms after driving wifi-en high */ +- post-power-on-delay-ms = <200>; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pg_pins>; +- vmmc-supply = <®_dldo1>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- esp8089: sdio_wifi@1 { +- compatible = "esp,esp8089"; +- reg = <1>; +- esp,crystal-26M-en = <2>; +- }; +-}; +- +-&touchscreen { +- reg = <0x40>; +- compatible = "silead,gsl3670"; +- firmware-name = "gsl3670-polaroid-mid2809pxe04.fw"; +- touchscreen-size-x = <1660>; +- touchscreen-size-y = <890>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a23-q8-tablet.dts b/scripts/dtc/include-prefixes/arm/sun8i-a23-q8-tablet.dts +deleted file mode 100644 +index 51097c77a152..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a23-q8-tablet.dts ++++ /dev/null +@@ -1,73 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a23.dtsi" +-#include "sun8i-q8-common.dtsi" +- +-/ { +- model = "Q8 A23 Tablet"; +- compatible = "allwinner,q8-a23", "allwinner,sun8i-a23"; +-}; +- +-&codec { +- allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ +- allwinner,audio-routing = +- "Headphone", "HP", +- "Headphone", "HPCOM", +- "Speaker", "HP", +- "MIC1", "Mic", +- "MIC2", "Headset Mic", +- "Mic", "MBIAS", +- "Headset Mic", "HBIAS"; +- status = "okay"; +-}; +- +-&panel { +- compatible = "bananapi,s070wv20-ct16"; +-}; +- +-&tcon0_out { +- tcon0_out_lcd: endpoint { +- remote-endpoint = <&panel_input>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a23.dtsi b/scripts/dtc/include-prefixes/arm/sun8i-a23.dtsi +deleted file mode 100644 +index a5e884a8b2ae..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a23.dtsi ++++ /dev/null +@@ -1,104 +0,0 @@ +-/* +- * Copyright 2014 Chen-Yu Tsai +- * +- * Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "sun8i-a23-a33.dtsi" +- +-/ { +- soc { +- codec: codec@1c22c00 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun8i-a23-codec"; +- reg = <0x01c22c00 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; +- clock-names = "apb", "codec"; +- resets = <&ccu RST_BUS_CODEC>; +- dmas = <&dma 15>, <&dma 15>; +- dma-names = "rx", "tx"; +- allwinner,codec-analog-controls = <&codec_analog>; +- status = "disabled"; +- }; +- }; +-}; +- +-&be0 { +- compatible = "allwinner,sun8i-a23-display-backend"; +-}; +- +-&ccu { +- compatible = "allwinner,sun8i-a23-ccu"; +-}; +- +-&de { +- compatible = "allwinner,sun8i-a23-display-engine"; +-}; +- +-&drc0 { +- compatible = "allwinner,sun8i-a23-drc"; +-}; +- +-&fe0 { +- compatible = "allwinner,sun8i-a23-display-frontend"; +-}; +- +-&pio { +- compatible = "allwinner,sun8i-a23-pinctrl"; +- interrupts = , +- , +- ; +-}; +- +-&tcon0 { +- compatible = "allwinner,sun8i-a23-tcon"; +-}; +- +-&usb_otg { +- compatible = "allwinner,sun6i-a31-musb"; +-}; +- +-&usbphy { +- compatible = "allwinner,sun8i-a23-usb-phy"; +- reg = <0x01c19400 0x10>, <0x01c1a800 0x4>; +- reg-names = "phy_ctrl", "pmu1"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a33-et-q8-v1.6.dts b/scripts/dtc/include-prefixes/arm/sun8i-a33-et-q8-v1.6.dts +deleted file mode 100644 +index 9c5750c25613..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a33-et-q8-v1.6.dts ++++ /dev/null +@@ -1,57 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a33.dtsi" +-#include "sun8i-q8-common.dtsi" +- +-/ { +- model = "Q8 A33 Tablet"; +- compatible = "allwinner,q8-a33", "allwinner,sun8i-a33"; +-}; +- +-&tcon0_out { +- tcon0_out_lcd: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_input>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a33-ga10h-v1.1.dts b/scripts/dtc/include-prefixes/arm/sun8i-a33-ga10h-v1.1.dts +deleted file mode 100644 +index 2dfdd0a3151e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a33-ga10h-v1.1.dts ++++ /dev/null +@@ -1,95 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a33.dtsi" +-#include "sun8i-reference-design-tablet.dtsi" +- +-/ { +- model = "Allwinner GA10H Quad Core Tablet (v1.1)"; +- compatible = "allwinner,ga10h-v1.1", "allwinner,sun8i-a33"; +- +- aliases { +- /* Make u-boot set mac-address for rtl8703as (no eeprom) */ +- ethernet0 = &rtl8703as; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&touchscreen { +- reg = <0x40>; +- compatible = "silead,gsl3675"; +- firmware-name = "gsl3675-ga10h.fw"; +- touchscreen-size-x = <1630>; +- touchscreen-size-y = <990>; +- touchscreen-inverted-y; +- status = "okay"; +-}; +- +-&lradc { +- button-600 { +- label = "Back"; +- linux,code = ; +- channel = <0>; +- voltage = <600000>; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pg_pins>; +- vmmc-supply = <®_dldo1>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- rtl8703as: sdio_wifi@1 { +- reg = <1>; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a33-inet-d978-rev2.dts b/scripts/dtc/include-prefixes/arm/sun8i-a33-inet-d978-rev2.dts +deleted file mode 100644 +index 065cb620aa99..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a33-inet-d978-rev2.dts ++++ /dev/null +@@ -1,103 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * Copyright 2016 Icenowy Zheng +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a33.dtsi" +-#include "sun8i-reference-design-tablet.dtsi" +- +-/ { +- model = "INet-D978 Rev 02"; +- compatible = "primux,inet-d978-rev2", "allwinner,sun8i-a33"; +- +- aliases { +- serial0 = &uart1; +- }; +- +- chosen { +- /* Delete debug UART as serial0 is the UART for bluetooth */ +- /delete-property/stdout-path; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_pin_d978>; +- +- led { +- label = "d978:blue:home"; +- gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ +- }; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pg_pins>; +- vmmc-supply = <®_dldo1>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- rtl8723bs: sdio_wifi@1 { +- reg = <1>; +- }; +-}; +- +-&r_pio { +- led_pin_d978: led-pin { +- pins = "PL5"; +- function = "gpio_out"; +- drive-strength = <20>; +- }; +-}; +- +-&r_uart { +- status = "disabled"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pg_pins>, +- <&uart1_cts_rts_pg_pins>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a33-ippo-q8h-v1.2.dts b/scripts/dtc/include-prefixes/arm/sun8i-a33-ippo-q8h-v1.2.dts +deleted file mode 100644 +index 9c5750c25613..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a33-ippo-q8h-v1.2.dts ++++ /dev/null +@@ -1,57 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a33.dtsi" +-#include "sun8i-q8-common.dtsi" +- +-/ { +- model = "Q8 A33 Tablet"; +- compatible = "allwinner,q8-a33", "allwinner,sun8i-a33"; +-}; +- +-&tcon0_out { +- tcon0_out_lcd: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_input>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a33-olinuxino.dts b/scripts/dtc/include-prefixes/arm/sun8i-a33-olinuxino.dts +deleted file mode 100644 +index 6fee8f133508..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a33-olinuxino.dts ++++ /dev/null +@@ -1,226 +0,0 @@ +-/* +- * Copyright 2016 - Stefan Mavrodiev +- * Olimex LTD. +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a33.dtsi" +- +-#include +-#include +- +-/ { +- model = "Olimex A33-OLinuXino"; +- compatible = "olimex,a33-olinuxino","allwinner,sun8i-a33"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led { +- label = "a33-olinuxino:green:usr"; +- gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&dai { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp22x: pmic@3a3 { +- compatible = "x-powers,axp223"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- eldoin-supply = <®_dcdc1>; +- x-powers,drive-vbus-en; +- }; +-}; +- +-#include "axp223.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_aldo1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-io"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <2350000>; +- regulator-max-microvolt = <2650000>; +- regulator-name = "vdd-dll"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-avcc"; +-}; +- +-®_dc1sw { +- regulator-name = "vcc-lcd"; +-}; +- +-®_dc5ldo { +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_drivevbus { +- regulator-name = "usb0-vbus"; +- status = "okay"; +-}; +- +-®_rtc_ldo { +- regulator-name = "vcc-rtc"; +-}; +- +-&simplefb_lcd { +- vcc-lcd-supply = <®_dc1sw>; +-}; +- +-&sound { +- /* Board level jack widgets */ +- simple-audio-card,widgets = "Microphone", "Microphone Jack", +- "Headphone", "Headphone Jack"; +- /* Board level routing. First 2 routes copied from SoC level */ +- simple-audio-card,routing = +- "Left DAC", "DACL", +- "Right DAC", "DACR", +- "HP", "HPCOM", +- "Headphone Jack", "HP", +- "MIC1", "Microphone Jack", +- "Microphone Jack", "MBIAS"; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_drivevbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a33-q8-tablet.dts b/scripts/dtc/include-prefixes/arm/sun8i-a33-q8-tablet.dts +deleted file mode 100644 +index 9c5750c25613..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a33-q8-tablet.dts ++++ /dev/null +@@ -1,57 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a33.dtsi" +-#include "sun8i-q8-common.dtsi" +- +-/ { +- model = "Q8 A33 Tablet"; +- compatible = "allwinner,q8-a33", "allwinner,sun8i-a33"; +-}; +- +-&tcon0_out { +- tcon0_out_lcd: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_input>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a33-sinlinx-sina33.dts b/scripts/dtc/include-prefixes/arm/sun8i-a33-sinlinx-sina33.dts +deleted file mode 100644 +index 0c82ff3c7cb4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a33-sinlinx-sina33.dts ++++ /dev/null +@@ -1,275 +0,0 @@ +-/* +- * Copyright 2015 Chen-Yu Tsai +- * +- * Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a33.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Sinlinx SinA33"; +- compatible = "sinlinx,sina33", "allwinner,sun8i-a33"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- panel { +- compatible = "netron-dy,e231732"; +- power-supply = <®_vcc3v3>; +- +- port { +- panel_input: endpoint { +- remote-endpoint = <&tcon0_out_panel>; +- }; +- }; +- }; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc3>; +-}; +- +-&cpu0_opp_table { +- opp-1104000000 { +- opp-hz = /bits/ 64 <1104000000>; +- opp-microvolt = <1320000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <1320000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&dai { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&lradc { +- vref-supply = <®_dcdc1>; +- status = "okay"; +- +- button-200 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <191011>; +- }; +- +- button-400 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <391304>; +- }; +- +- button-600 { +- label = "Home"; +- linux,code = ; +- channel = <0>; +- voltage = <600000>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ +- status = "okay"; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_pins>; +- vmmc-supply = <®_dcdc1>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&mmc2_8bit_pins { +- /* Increase drive strength for DDR modes */ +- drive-strength = <40>; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp22x: pmic@3a3 { +- compatible = "x-powers,axp223"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- eldoin-supply = <®_dcdc1>; +- }; +-}; +- +-#include "axp223.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_aldo1 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-io"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <2350000>; +- regulator-max-microvolt = <2650000>; +- regulator-name = "vdd-dll"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pll-avcc"; +-}; +- +-®_dc5ldo { +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-3v0"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_rtc_ldo { +- regulator-name = "vcc-rtc"; +-}; +- +-&sound { +- status = "okay"; +-}; +- +-&tcon0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_rgb666_pins>; +- status = "okay"; +-}; +- +-&tcon0_out { +- tcon0_out_panel: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_input>; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +- usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a33.dtsi b/scripts/dtc/include-prefixes/arm/sun8i-a33.dtsi +deleted file mode 100644 +index b3d1bdfb5118..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a33.dtsi ++++ /dev/null +@@ -1,431 +0,0 @@ +-/* +- * Copyright 2014 Chen-Yu Tsai +- * +- * Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "sun8i-a23-a33.dtsi" +-#include +- +-/ { +- cpu0_opp_table: opp-table-cpu { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-120000000 { +- opp-hz = /bits/ 64 <120000000>; +- opp-microvolt = <1040000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-240000000 { +- opp-hz = /bits/ 64 <240000000>; +- opp-microvolt = <1040000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-312000000 { +- opp-hz = /bits/ 64 <312000000>; +- opp-microvolt = <1040000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-408000000 { +- opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <1040000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-480000000 { +- opp-hz = /bits/ 64 <480000000>; +- opp-microvolt = <1040000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-504000000 { +- opp-hz = /bits/ 64 <504000000>; +- opp-microvolt = <1040000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <1040000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-648000000 { +- opp-hz = /bits/ 64 <648000000>; +- opp-microvolt = <1040000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-720000000 { +- opp-hz = /bits/ 64 <720000000>; +- opp-microvolt = <1100000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-816000000 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <1100000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-912000000 { +- opp-hz = /bits/ 64 <912000000>; +- opp-microvolt = <1200000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-1008000000 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <1200000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- }; +- +- cpus { +- cpu@0 { +- clocks = <&ccu CLK_CPUX>; +- clock-names = "cpu"; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- clocks = <&ccu CLK_CPUX>; +- clock-names = "cpu"; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <2>; +- clocks = <&ccu CLK_CPUX>; +- clock-names = "cpu"; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <3>; +- clocks = <&ccu CLK_CPUX>; +- clock-names = "cpu"; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- }; +- +- iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&ths>; +- }; +- +- mali_opp_table: opp-table-gpu { +- compatible = "operating-points-v2"; +- +- opp-144000000 { +- opp-hz = /bits/ 64 <144000000>; +- }; +- +- opp-240000000 { +- opp-hz = /bits/ 64 <240000000>; +- }; +- +- opp-384000000 { +- opp-hz = /bits/ 64 <384000000>; +- }; +- }; +- +- sound: sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "sun8i-a33-audio"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,frame-master = <&link_codec>; +- simple-audio-card,bitclock-master = <&link_codec>; +- simple-audio-card,mclk-fs = <128>; +- simple-audio-card,aux-devs = <&codec_analog>; +- simple-audio-card,routing = +- "Left DAC", "DACL", +- "Right DAC", "DACR"; +- status = "disabled"; +- +- simple-audio-card,cpu { +- sound-dai = <&dai>; +- }; +- +- link_codec: simple-audio-card,codec { +- sound-dai = <&codec 0>; +- }; +- }; +- +- soc { +- video-codec@1c0e000 { +- compatible = "allwinner,sun8i-a33-video-engine"; +- reg = <0x01c0e000 0x1000>; +- clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, +- <&ccu CLK_DRAM_VE>; +- clock-names = "ahb", "mod", "ram"; +- resets = <&ccu RST_BUS_VE>; +- interrupts = ; +- allwinner,sram = <&ve_sram 1>; +- }; +- +- crypto: crypto-engine@1c15000 { +- compatible = "allwinner,sun8i-a33-crypto"; +- reg = <0x01c15000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; +- clock-names = "ahb", "mod"; +- resets = <&ccu RST_BUS_SS>; +- reset-names = "ahb"; +- }; +- +- dai: dai@1c22c00 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun6i-a31-i2s"; +- reg = <0x01c22c00 0x200>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; +- clock-names = "apb", "mod"; +- resets = <&ccu RST_BUS_CODEC>; +- dmas = <&dma 15>, <&dma 15>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- codec: codec@1c22e00 { +- #sound-dai-cells = <1>; +- compatible = "allwinner,sun8i-a33-codec"; +- reg = <0x01c22e00 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; +- clock-names = "bus", "mod"; +- status = "disabled"; +- }; +- +- ths: ths@1c25000 { +- compatible = "allwinner,sun8i-a33-ths"; +- reg = <0x01c25000 0x100>; +- #thermal-sensor-cells = <0>; +- #io-channel-cells = <0>; +- }; +- +- dsi: dsi@1ca0000 { +- compatible = "allwinner,sun6i-a31-mipi-dsi"; +- reg = <0x01ca0000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_MIPI_DSI>, +- <&ccu CLK_DSI_SCLK>; +- clock-names = "bus", "mod"; +- resets = <&ccu RST_BUS_MIPI_DSI>; +- phys = <&dphy>; +- phy-names = "dphy"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- port { +- dsi_in_tcon0: endpoint { +- remote-endpoint = <&tcon0_out_dsi>; +- }; +- }; +- }; +- +- dphy: d-phy@1ca1000 { +- compatible = "allwinner,sun6i-a31-mipi-dphy"; +- reg = <0x01ca1000 0x1000>; +- clocks = <&ccu CLK_BUS_MIPI_DSI>, +- <&ccu CLK_DSI_DPHY>; +- clock-names = "bus", "mod"; +- resets = <&ccu RST_BUS_MIPI_DSI>; +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- +- thermal-zones { +- cpu-thermal { +- /* milliseconds */ +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&ths>; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu_alert1>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- +- map2 { +- trip = <&gpu_alert0>; +- cooling-device = <&mali 1 THERMAL_NO_LIMIT>; +- }; +- +- map3 { +- trip = <&gpu_alert1>; +- cooling-device = <&mali 2 THERMAL_NO_LIMIT>; +- }; +- }; +- +- trips { +- cpu_alert0: cpu_alert0 { +- /* milliCelsius */ +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- gpu_alert0: gpu_alert0 { +- /* milliCelsius */ +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_alert1: cpu_alert1 { +- /* milliCelsius */ +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- gpu_alert1: gpu_alert1 { +- /* milliCelsius */ +- temperature = <95000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- cpu_crit: cpu_crit { +- /* milliCelsius */ +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +- +-&be0 { +- compatible = "allwinner,sun8i-a33-display-backend"; +- /* A33 has an extra "SAT" module packed inside the display backend */ +- reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; +- reg-names = "be", "sat"; +- clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, +- <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>; +- clock-names = "ahb", "mod", +- "ram", "sat"; +- resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>; +- reset-names = "be", "sat"; +-}; +- +-&ccu { +- compatible = "allwinner,sun8i-a33-ccu"; +-}; +- +-&de { +- compatible = "allwinner,sun8i-a33-display-engine"; +-}; +- +-&drc0 { +- compatible = "allwinner,sun8i-a33-drc"; +-}; +- +-&fe0 { +- compatible = "allwinner,sun8i-a33-display-frontend"; +-}; +- +-&mali { +- operating-points-v2 = <&mali_opp_table>; +-}; +- +-&pio { +- compatible = "allwinner,sun8i-a33-pinctrl"; +- interrupts = , +- ; +- +- uart0_pb_pins: uart0-pb-pins { +- pins = "PB0", "PB1"; +- function = "uart0"; +- }; +- +-}; +- +-&tcon0 { +- compatible = "allwinner,sun8i-a33-tcon"; +-}; +- +-&tcon0_out { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon0_out_dsi: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&dsi_in_tcon0>; +- }; +-}; +- +-&usb_otg { +- compatible = "allwinner,sun8i-a33-musb"; +-}; +- +-&usbphy { +- compatible = "allwinner,sun8i-a33-usb-phy"; +- reg = <0x01c19400 0x14>, <0x01c1a800 0x4>; +- reg-names = "phy_ctrl", "pmu1"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a83t-allwinner-h8homlet-v2.dts b/scripts/dtc/include-prefixes/arm/sun8i-a83t-allwinner-h8homlet-v2.dts +deleted file mode 100644 +index c31c97d16024..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a83t-allwinner-h8homlet-v2.dts ++++ /dev/null +@@ -1,281 +0,0 @@ +-/* +- * Copyright 2015 Vishnu Patekar +- * Vishnu Patekar +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a83t.dtsi" +- +-#include +- +-/ { +- model = "Allwinner A83T H8Homlet Proto Dev Board v2.0"; +- compatible = "allwinner,h8homlet-v2", "allwinner,sun8i-a83t"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- reg_usb0_vbus: reg-usb0-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb0-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- enable-active-high; +- gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ +- }; +- +- reg_usb1_vbus: reg-usb1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb1-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- enable-active-high; +- gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu100 { +- cpu-supply = <®_dcdc3>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_dcdc1>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- bus-width = <4>; +- status = "okay"; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_emmc_pins>; +- vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_dcdc1>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp81x: pmic@3a3 { +- compatible = "x-powers,axp818", "x-powers,axp813"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- eldoin-supply = <®_dcdc1>; +- swin-supply = <®_dcdc1>; +- }; +- +- ac100: codec@e89 { +- compatible = "x-powers,ac100"; +- reg = <0xe89>; +- +- ac100_codec: codec { +- compatible = "x-powers,ac100-codec"; +- interrupt-parent = <&r_pio>; +- interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ +- #clock-cells = <0>; +- clock-output-names = "4M_adda"; +- }; +- +- ac100_rtc: rtc { +- compatible = "x-powers,ac100-rtc"; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- clocks = <&ac100_codec>; +- #clock-cells = <1>; +- clock-output-names = "cko1_rtc", +- "cko2_rtc", +- "cko3_rtc"; +- }; +- }; +-}; +- +-#include "axp81x.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-®_aldo1 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-1v8"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "dram-pll"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpua"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpub"; +-}; +- +-®_dcdc4 { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-gpu"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dcdc6 { +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dldo2 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-mipi"; +-}; +- +-®_dldo4 { +- /* +- * The PHY requires 20ms after all voltages are applied until core +- * logic is ready and 30ms after the reset pin is de-asserted. +- * Set a 100ms delay to account for PMIC ramp time and board traces. +- */ +- regulator-enable-ramp-delay = <100000>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-ephy"; +-}; +- +-®_fldo1 { +- regulator-min-microvolt = <1080000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd12-hsic"; +-}; +- +-®_fldo2 { +- /* +- * Despite the embedded CPUs core not being used in any way, +- * this must remain on or the system will hang. +- */ +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_rtc_ldo { +- regulator-name = "vcc-rtc"; +-}; +- +-®_sw { +- regulator-name = "vcc-wifi"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_vbus-supply = <®_usb0_vbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a83t-bananapi-m3.dts b/scripts/dtc/include-prefixes/arm/sun8i-a83t-bananapi-m3.dts +deleted file mode 100644 +index 5a7e1bd5f825..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a83t-bananapi-m3.dts ++++ /dev/null +@@ -1,407 +0,0 @@ +-/* +- * Copyright 2017 Chen-Yu Tsai +- * +- * Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a83t.dtsi" +- +-#include +- +-/ { +- model = "Banana Pi BPI-M3"; +- compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t"; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "bananapi-m3:blue:usr"; +- gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; +- }; +- +- led-1 { +- label = "bananapi-m3:green:usr"; +- gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- reg_usb1_vbus: reg-usb1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb1-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- enable-active-high; +- gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&ac100_rtc 1>; +- clock-names = "ext_clock"; +- /* The WiFi low power clock must be 32768 Hz */ +- assigned-clocks = <&ac100_rtc 1>; +- assigned-clock-rates = <32768>; +- /* enables internal regulator and de-asserts reset */ +- reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu100 { +- cpu-supply = <®_dcdc3>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */ +- status = "okay"; +- +- /* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */ +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_rgmii_pins>; +- phy-supply = <®_sw>; +- phy-handle = <&rgmii_phy>; +- phy-mode = "rgmii-id"; +- allwinner,rx-delay-ps = <700>; +- allwinner,tx-delay-ps = <700>; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&mdio { +- rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_dldo1>; +- vqmmc-supply = <®_dldo1>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&r_pio>; +- interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; +- interrupt-names = "host-wake"; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_emmc_pins>; +- vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_dcdc1>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&r_cir { +- clock-frequency = <3000000>; +- status = "okay"; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp81x: pmic@3a3 { +- compatible = "x-powers,axp813"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- eldoin-supply = <®_dcdc1>; +- fldoin-supply = <®_dcdc5>; +- swin-supply = <®_dcdc1>; +- x-powers,drive-vbus-en; +- }; +- +- ac100: codec@e89 { +- compatible = "x-powers,ac100"; +- reg = <0xe89>; +- +- ac100_codec: codec { +- compatible = "x-powers,ac100-codec"; +- interrupt-parent = <&r_pio>; +- interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ +- #clock-cells = <0>; +- clock-output-names = "4M_adda"; +- }; +- +- ac100_rtc: rtc { +- compatible = "x-powers,ac100-rtc"; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- clocks = <&ac100_codec>; +- #clock-cells = <1>; +- clock-output-names = "cko1_rtc", +- "cko2_rtc", +- "cko3_rtc"; +- }; +- }; +-}; +- +-#include "axp81x.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_aldo1 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-1v8"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "dram-pll"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_dcdc1 { +- /* schematics says 3.1V but FEX file says 3.3V */ +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpua"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpub"; +-}; +- +-®_dcdc4 { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-gpu"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dcdc6 { +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dldo1 { +- /* +- * This powers both the WiFi/BT module's main power, I/O supply, +- * and external pull-ups on all the data lines. It should be set +- * to the same voltage as the I/O supply (DCDC1 in this case) to +- * avoid any leakage or mismatch. +- */ +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-®_dldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pd"; +-}; +- +-®_drivevbus { +- regulator-name = "usb0-vbus"; +- status = "okay"; +-}; +- +-®_fldo1 { +- regulator-min-microvolt = <1080000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd12-hsic"; +-}; +- +-®_fldo2 { +- /* +- * Despite the embedded CPUs core not being used in any way, +- * this must remain on or the system will hang. +- */ +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_rtc_ldo { +- regulator-name = "vcc-rtc"; +-}; +- +-®_sw { +- /* +- * The PHY requires 20ms after all voltages +- * are applied until core logic is ready and +- * 30ms after the reset pin is de-asserted. +- * Set a 100ms delay to account for PMIC +- * ramp time and board traces. +- */ +- regulator-enable-ramp-delay = <100000>; +- regulator-name = "vcc-ephy"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&ac100_rtc 1>; +- clock-names = "lpo"; +- vbat-supply = <®_dldo1>; +- vddio-supply = <®_dldo1>; +- device-wakeup-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ +- host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ +- shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ +- }; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_drivevbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a83t-cubietruck-plus.dts b/scripts/dtc/include-prefixes/arm/sun8i-a83t-cubietruck-plus.dts +deleted file mode 100644 +index 870993393fc2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a83t-cubietruck-plus.dts ++++ /dev/null +@@ -1,464 +0,0 @@ +-/* +- * Copyright 2015 Chen-Yu Tsai +- * +- * Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a83t.dtsi" +- +-#include +- +-/ { +- model = "Cubietech Cubietruck Plus"; +- compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t"; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "cubietruck-plus:blue:usr"; +- gpios = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */ +- }; +- +- led-1 { +- label = "cubietruck-plus:orange:usr"; +- gpios = <&pio 3 26 GPIO_ACTIVE_HIGH>; /* PD26 */ +- }; +- +- led-2 { +- label = "cubietruck-plus:white:usr"; +- gpios = <&pio 3 27 GPIO_ACTIVE_HIGH>; /* PD27 */ +- }; +- +- led-3 { +- label = "cubietruck-plus:green:usr"; +- gpios = <&pio 4 4 GPIO_ACTIVE_HIGH>; /* PE4 */ +- }; +- }; +- +- usb-hub { +- /* I2C is not connected */ +- compatible = "smsc,usb3503"; +- initial-mode = <1>; /* initialize in HUB mode */ +- disabled-ports = <1>; +- intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ +- reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */ +- connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ +- refclk-frequency = <19200000>; +- }; +- +- reg_usb1_vbus: reg-usb1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb1-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- enable-active-high; +- gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */ +- }; +- +- reg_usb2_vbus: reg-usb2-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb2-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- enable-active-high; +- gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "On-board SPDIF"; +- +- simple-audio-card,cpu { +- sound-dai = <&spdif>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&spdif_out>; +- }; +- }; +- +- spdif_out: spdif-out { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&ac100_rtc 1>; +- clock-names = "ext_clock"; +- /* The WiFi low power clock must be 32768 Hz */ +- assigned-clocks = <&ac100_rtc 1>; +- assigned-clock-rates = <32768>; +- /* enables internal regulator and de-asserts reset */ +- reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu100 { +- cpu-supply = <®_dcdc3>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- /* GL830 USB-to-SATA bridge here */ +- status = "okay"; +-}; +- +-&ehci1 { +- /* USB3503 HSIC USB 2.0 hub here */ +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_rgmii_pins>; +- phy-supply = <®_dldo4>; +- phy-handle = <&rgmii_phy>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&mdio { +- rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_sw>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_emmc_pins>; +- vmmc-supply = <®_dcdc1>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp81x: pmic@3a3 { +- compatible = "x-powers,axp818", "x-powers,axp813"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- eldoin-supply = <®_dcdc1>; +- swin-supply = <®_dcdc1>; +- x-powers,drive-vbus-en; +- }; +- +- ac100: codec@e89 { +- compatible = "x-powers,ac100"; +- reg = <0xe89>; +- +- ac100_codec: codec { +- compatible = "x-powers,ac100-codec"; +- interrupt-parent = <&r_pio>; +- interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ +- #clock-cells = <0>; +- clock-output-names = "4M_adda"; +- }; +- +- ac100_rtc: rtc { +- compatible = "x-powers,ac100-rtc"; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- clocks = <&ac100_codec>; +- #clock-cells = <1>; +- clock-output-names = "cko1_rtc", +- "cko2_rtc", +- "cko3_rtc"; +- }; +- }; +-}; +- +-#include "axp81x.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_aldo1 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-1v8"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "dram-pll"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_dcdc1 { +- /* +- * The schematics say this should be 3.3V, but the FEX file says +- * it should be 3V. The latter makes sense, as the WiFi module's +- * I/O is indirectly powered from DCDC1, through SW. It is rated +- * at 2.98V maximum. +- */ +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-3v"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpua"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpub"; +-}; +- +-®_dcdc4 { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-gpu"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dcdc6 { +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dldo2 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "dp-pwr"; +-}; +- +-®_dldo3 { +- regulator-always-on; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-name = "ephy-io"; +-}; +- +-®_dldo4 { +- /* +- * The PHY requires 20ms after all voltages are applied until core +- * logic is ready and 30ms after the reset pin is de-asserted. +- * Set a 100ms delay to account for PMIC ramp time and board traces. +- */ +- regulator-enable-ramp-delay = <100000>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "ephy"; +-}; +- +-®_drivevbus { +- regulator-name = "usb0-vbus"; +- status = "okay"; +-}; +- +-®_eldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "dp-bridge-1"; +-}; +- +-®_eldo2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "dp-bridge-2"; +-}; +- +-®_fldo1 { +- /* TODO should be handled by USB PHY */ +- regulator-always-on; +- regulator-min-microvolt = <1080000>; +- regulator-max-microvolt = <1320000>; +- regulator-name = "vdd12-hsic"; +-}; +- +-®_fldo2 { +- /* +- * Despite the embedded CPUs core not being used in any way, +- * this must remain on or the system will hang. +- */ +- regulator-always-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_rtc_ldo { +- regulator-name = "vcc-rtc"; +-}; +- +-®_sw { +- regulator-name = "vcc-wifi-io"; +-}; +- +-&spdif { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm4330-bt"; +- clocks = <&ac100_rtc 1>; +- clock-names = "lpo"; +- vbat-supply = <®_dcdc1>; +- vddio-supply = <®_sw>; +- device-wakeup-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ +- host-wakeup-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ +- shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ +- }; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_drivevbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a83t-tbs-a711.dts b/scripts/dtc/include-prefixes/arm/sun8i-a83t-tbs-a711.dts +deleted file mode 100644 +index 7fe2a584ddf9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a83t-tbs-a711.dts ++++ /dev/null +@@ -1,506 +0,0 @@ +-/* +- * Copyright (C) 2017 Touchless Biometric Systems AG +- * Tomas Novotny +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a83t.dtsi" +- +-#include +-#include +-#include +- +-/ { +- model = "TBS A711 Tablet"; +- compatible = "tbs-biometrics,a711", "allwinner,sun8i-a83t"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; +- enable-gpios = <&pio 3 29 GPIO_ACTIVE_HIGH>; +- power-supply = <®_sw>; +- brightness-levels = <0 1 2 4 8 16 32 64 128 255>; +- default-brightness-level = <9>; +- }; +- +- panel { +- compatible = "tbs,a711-panel", "panel-lvds"; +- backlight = <&backlight>; +- power-supply = <®_sw>; +- +- width-mm = <153>; +- height-mm = <90>; +- data-mapping = "vesa-24"; +- +- panel-timing { +- /* 1024x600 @60Hz */ +- clock-frequency = <52000000>; +- hactive = <1024>; +- vactive = <600>; +- hsync-len = <20>; +- hfront-porch = <180>; +- hback-porch = <160>; +- vfront-porch = <12>; +- vback-porch = <23>; +- vsync-len = <5>; +- }; +- +- port { +- panel_input: endpoint { +- remote-endpoint = <&tcon0_out_lcd>; +- }; +- }; +- }; +- +- reg_gps: reg-gps { +- compatible = "regulator-fixed"; +- regulator-name = "gps"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- reg_vbat: reg-vbat { +- compatible = "regulator-fixed"; +- regulator-name = "vbat"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- }; +- +- reg_vmain: reg-vmain { +- compatible = "regulator-fixed"; +- regulator-name = "vmain"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_vbat>; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ +- +- /* +- * This is actually Bluetooth's clock, but we have to +- * hook it up somewheere +- */ +- clocks = <&ac100_rtc 1>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu100 { +- cpu-supply = <®_dcdc3>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-/* +- * An USB-2 hub is connected here, which also means we don't need to +- * enable the OHCI controller. +- */ +-&ehci0 { +- status = "okay"; +-}; +- +-/* +- * There's a modem connected here that needs to be initialised before +- * being able to be enumerated. +- */ +-&ehci1 { +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- status = "okay"; +- +- touchscreen@38 { +- compatible = "edt,edt-ft5x06"; +- reg = <0x38>; +- interrupt-parent = <&r_pio>; +- interrupts = <0 7 IRQ_TYPE_EDGE_FALLING>; /* PL7 */ +- reset-gpios = <&pio 3 5 GPIO_ACTIVE_LOW>; /* PD5 */ +- vcc-supply = <®_ldo_io0>; +- touchscreen-size-x = <1024>; +- touchscreen-size-y = <600>; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- status = "okay"; +- +- accelerometer@18 { +- compatible = "bosch,bma250"; +- reg = <0x18>; +- interrupt-parent = <&pio>; +- interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */ +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_dcdc1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&mmc1 { +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- vmmc-supply = <®_dldo1>; +- vqmmc-supply = <®_dldo1>; +- non-removable; +- wakeup-source; +- keep-power-in-suspend; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&r_pio>; +- interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 WL_WAKE_UP */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&mmc2 { +- pinctrl-0 = <&mmc2_8bit_emmc_pins>; +- pinctrl-names = "default"; +- vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_dcdc1>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm_pin>; +- status = "okay"; +-}; +- +-&r_lradc { +- vref-supply = <®_aldo2>; +- status = "okay"; +- +- button-210 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <210000>; +- }; +- +- button-410 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <410000>; +- }; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp81x: pmic@3a3 { +- compatible = "x-powers,axp813"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- swin-supply = <®_dcdc1>; +- x-powers,drive-vbus-en; +- }; +- +- ac100: codec@e89 { +- compatible = "x-powers,ac100"; +- reg = <0xe89>; +- +- ac100_codec: codec { +- compatible = "x-powers,ac100-codec"; +- interrupt-parent = <&r_pio>; +- interrupts = <0 12 IRQ_TYPE_LEVEL_LOW>; /* PL12 */ +- #clock-cells = <0>; +- clock-output-names = "4M_adda"; +- }; +- +- ac100_rtc: rtc { +- compatible = "x-powers,ac100-rtc"; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- clocks = <&ac100_codec>; +- #clock-cells = <1>; +- clock-output-names = "cko1_rtc", +- "cko2_rtc", +- "cko3_rtc"; +- }; +- }; +- +-}; +- +-#include "axp81x.dtsi" +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_aldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-1.8"; +-}; +- +-®_aldo2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-name = "vdd-drampll"; +-}; +- +-®_aldo3 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-name = "avcc"; +-}; +- +-®_dcdc1 { +- regulator-min-microvolt = <3100000>; +- regulator-max-microvolt = <3100000>; +- regulator-always-on; +- regulator-name = "vcc-io"; +-}; +- +-®_dcdc2 { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-name = "vdd-cpu-A"; +-}; +- +-®_dcdc3 { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-name = "vdd-cpu-B"; +-}; +- +-®_dcdc4 { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-gpu"; +-}; +- +-®_dcdc5 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-name = "vcc-dram"; +-}; +- +-®_dcdc6 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-always-on; +- regulator-name = "vdd-sys"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <3100000>; +- regulator-max-microvolt = <3100000>; +- regulator-name = "vcc-wifi-io"; +-}; +- +-®_dldo2 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <4200000>; +- regulator-name = "vcc-mipi"; +-}; +- +-®_dldo3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vdd-csi"; +-}; +- +-®_dldo4 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "avdd-csi"; +-}; +- +-®_drivevbus { +- regulator-name = "usb0-vbus"; +- status = "okay"; +-}; +- +-®_eldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "dvdd-csi-r"; +-}; +- +-®_eldo2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-dsi"; +-}; +- +-®_eldo3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "dvdd-csi-f"; +-}; +- +-®_fldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-hsic"; +-}; +- +-®_fldo2 { +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-name = "vdd-cpus"; +-}; +- +-®_ldo_io0 { +- regulator-min-microvolt = <3100000>; +- regulator-max-microvolt = <3100000>; +- regulator-name = "vcc-ctp"; +- status = "okay"; +-}; +- +-®_ldo_io1 { +- regulator-min-microvolt = <3100000>; +- regulator-max-microvolt = <3100000>; +- regulator-name = "vcc-vb"; +- status = "okay"; +-}; +- +-®_sw { +- regulator-min-microvolt = <3100000>; +- regulator-max-microvolt = <3100000>; +- regulator-name = "vcc-lcd"; +-}; +- +-&tcon0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_lvds_pins>; +-}; +- +-&tcon0_out { +- tcon0_out_lcd: endpoint { +- remote-endpoint = <&panel_input>; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-/* There's the BT part of the AP6210 connected to that UART */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm20702a1"; +- clocks = <&ac100_rtc 1>; +- clock-names = "lpo"; +- vbat-supply = <®_vbat>; +- vddio-supply = <®_dldo1>; +- device-wakeup-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ +- host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ +- shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ +- max-speed = <1500000>; +- }; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pb_pins>; +- status = "okay"; +- +- gnss { +- compatible = "u-blox,neo-6m"; +- +- v-bckp-supply = <®_rtc_ldo>; +- vcc-supply = <®_gps>; +- current-speed = <9600>; +- }; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 11 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH11 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_drivevbus>; +- usb1_vbus-supply = <®_vmain>; +- usb2_vbus-supply = <®_vmain>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-a83t.dtsi b/scripts/dtc/include-prefixes/arm/sun8i-a83t.dtsi +deleted file mode 100644 +index 82fdb04122ca..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-a83t.dtsi ++++ /dev/null +@@ -1,1274 +0,0 @@ +-/* +- * Copyright 2015 Vishnu Patekar +- * +- * Vishnu Patekar +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- clocks = <&ccu CLK_C0CPUX>; +- operating-points-v2 = <&cpu0_opp_table>; +- cci-control-port = <&cci_control0>; +- enable-method = "allwinner,sun8i-a83t-smp"; +- reg = <0>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- clocks = <&ccu CLK_C0CPUX>; +- operating-points-v2 = <&cpu0_opp_table>; +- cci-control-port = <&cci_control0>; +- enable-method = "allwinner,sun8i-a83t-smp"; +- reg = <1>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- clocks = <&ccu CLK_C0CPUX>; +- operating-points-v2 = <&cpu0_opp_table>; +- cci-control-port = <&cci_control0>; +- enable-method = "allwinner,sun8i-a83t-smp"; +- reg = <2>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- clocks = <&ccu CLK_C0CPUX>; +- operating-points-v2 = <&cpu0_opp_table>; +- cci-control-port = <&cci_control0>; +- enable-method = "allwinner,sun8i-a83t-smp"; +- reg = <3>; +- #cooling-cells = <2>; +- }; +- +- cpu100: cpu@100 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- clocks = <&ccu CLK_C1CPUX>; +- operating-points-v2 = <&cpu1_opp_table>; +- cci-control-port = <&cci_control1>; +- enable-method = "allwinner,sun8i-a83t-smp"; +- reg = <0x100>; +- #cooling-cells = <2>; +- }; +- +- cpu101: cpu@101 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- clocks = <&ccu CLK_C1CPUX>; +- operating-points-v2 = <&cpu1_opp_table>; +- cci-control-port = <&cci_control1>; +- enable-method = "allwinner,sun8i-a83t-smp"; +- reg = <0x101>; +- #cooling-cells = <2>; +- }; +- +- cpu102: cpu@102 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- clocks = <&ccu CLK_C1CPUX>; +- operating-points-v2 = <&cpu1_opp_table>; +- cci-control-port = <&cci_control1>; +- enable-method = "allwinner,sun8i-a83t-smp"; +- reg = <0x102>; +- #cooling-cells = <2>; +- }; +- +- cpu103: cpu@103 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- clocks = <&ccu CLK_C1CPUX>; +- operating-points-v2 = <&cpu1_opp_table>; +- cci-control-port = <&cci_control1>; +- enable-method = "allwinner,sun8i-a83t-smp"; +- reg = <0x103>; +- #cooling-cells = <2>; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* TODO: PRCM block has a mux for this. */ +- osc24M: osc24M_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-accuracy = <50000>; +- clock-output-names = "osc24M"; +- }; +- +- /* +- * This is called "internal OSC" in some places. +- * It is an internal RC-based oscillator. +- * TODO: Its controls are in the PRCM block. +- */ +- osc16M: osc16M_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <16000000>; +- clock-output-names = "osc16M"; +- }; +- +- osc16Md512: osc16Md512_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <512>; +- clock-mult = <1>; +- clocks = <&osc16M>; +- clock-output-names = "osc16M-d512"; +- }; +- }; +- +- de: display-engine { +- compatible = "allwinner,sun8i-a83t-display-engine"; +- allwinner,pipelines = <&mixer0>, <&mixer1>; +- status = "disabled"; +- }; +- +- cpu0_opp_table: opp-table-cluster0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-480000000 { +- opp-hz = /bits/ 64 <480000000>; +- opp-microvolt = <840000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <840000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-720000000 { +- opp-hz = /bits/ 64 <720000000>; +- opp-microvolt = <840000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-864000000 { +- opp-hz = /bits/ 64 <864000000>; +- opp-microvolt = <840000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-912000000 { +- opp-hz = /bits/ 64 <912000000>; +- opp-microvolt = <840000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-1008000000 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <840000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-1128000000 { +- opp-hz = /bits/ 64 <1128000000>; +- opp-microvolt = <840000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <840000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- }; +- +- cpu1_opp_table: opp-table-cluster1 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-480000000 { +- opp-hz = /bits/ 64 <480000000>; +- opp-microvolt = <840000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <840000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-720000000 { +- opp-hz = /bits/ 64 <720000000>; +- opp-microvolt = <840000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-864000000 { +- opp-hz = /bits/ 64 <864000000>; +- opp-microvolt = <840000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-912000000 { +- opp-hz = /bits/ 64 <912000000>; +- opp-microvolt = <840000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-1008000000 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <840000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-1128000000 { +- opp-hz = /bits/ 64 <1128000000>; +- opp-microvolt = <840000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <840000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- display_clocks: clock@1000000 { +- compatible = "allwinner,sun8i-a83t-de2-clk"; +- reg = <0x01000000 0x10000>; +- clocks = <&ccu CLK_BUS_DE>, +- <&ccu CLK_PLL_DE>; +- clock-names = "bus", +- "mod"; +- resets = <&ccu RST_BUS_DE>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- rotate: rotate@1020000 { +- compatible = "allwinner,sun8i-a83t-de2-rotate"; +- reg = <0x1020000 0x10000>; +- interrupts = ; +- clocks = <&display_clocks CLK_BUS_ROT>, +- <&display_clocks CLK_ROT>; +- clock-names = "bus", +- "mod"; +- resets = <&display_clocks RST_ROT>; +- }; +- +- mixer0: mixer@1100000 { +- compatible = "allwinner,sun8i-a83t-de2-mixer-0"; +- reg = <0x01100000 0x100000>; +- clocks = <&display_clocks CLK_BUS_MIXER0>, +- <&display_clocks CLK_MIXER0>; +- clock-names = "bus", +- "mod"; +- resets = <&display_clocks RST_MIXER0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mixer0_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- mixer0_out_tcon0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&tcon0_in_mixer0>; +- }; +- +- mixer0_out_tcon1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tcon1_in_mixer0>; +- }; +- }; +- }; +- }; +- +- mixer1: mixer@1200000 { +- compatible = "allwinner,sun8i-a83t-de2-mixer-1"; +- reg = <0x01200000 0x100000>; +- clocks = <&display_clocks CLK_BUS_MIXER1>, +- <&display_clocks CLK_MIXER1>; +- clock-names = "bus", +- "mod"; +- resets = <&display_clocks RST_WB>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mixer1_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- mixer1_out_tcon0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&tcon0_in_mixer1>; +- }; +- +- mixer1_out_tcon1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tcon1_in_mixer1>; +- }; +- }; +- }; +- }; +- +- cpucfg@1700000 { +- compatible = "allwinner,sun8i-a83t-cpucfg"; +- reg = <0x01700000 0x400>; +- }; +- +- cci@1790000 { +- compatible = "arm,cci-400"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x01790000 0x10000>; +- ranges = <0x0 0x01790000 0x10000>; +- +- cci_control0: slave-if@4000 { +- compatible = "arm,cci-400-ctrl-if"; +- interface-type = "ace"; +- reg = <0x4000 0x1000>; +- }; +- +- cci_control1: slave-if@5000 { +- compatible = "arm,cci-400-ctrl-if"; +- interface-type = "ace"; +- reg = <0x5000 0x1000>; +- }; +- +- pmu@9000 { +- compatible = "arm,cci-400-pmu,r1"; +- reg = <0x9000 0x5000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- }; +- }; +- +- syscon: syscon@1c00000 { +- compatible = "allwinner,sun8i-a83t-system-controller", +- "syscon"; +- reg = <0x01c00000 0x1000>; +- }; +- +- dma: dma-controller@1c02000 { +- compatible = "allwinner,sun8i-a83t-dma"; +- reg = <0x01c02000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_DMA>; +- resets = <&ccu RST_BUS_DMA>; +- #dma-cells = <1>; +- }; +- +- tcon0: lcd-controller@1c0c000 { +- compatible = "allwinner,sun8i-a83t-tcon-lcd"; +- reg = <0x01c0c000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; +- clock-names = "ahb", "tcon-ch0"; +- clock-output-names = "tcon-pixel-clock"; +- #clock-cells = <0>; +- resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; +- reset-names = "lcd", "lvds"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon0_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- tcon0_in_mixer0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&mixer0_out_tcon0>; +- }; +- +- tcon0_in_mixer1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&mixer1_out_tcon0>; +- }; +- }; +- +- tcon0_out: port@1 { +- reg = <1>; +- }; +- }; +- }; +- +- tcon1: lcd-controller@1c0d000 { +- compatible = "allwinner,sun8i-a83t-tcon-tv"; +- reg = <0x01c0d000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; +- clock-names = "ahb", "tcon-ch1"; +- resets = <&ccu RST_BUS_TCON1>; +- reset-names = "lcd"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon1_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- tcon1_in_mixer0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&mixer0_out_tcon1>; +- }; +- +- tcon1_in_mixer1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&mixer1_out_tcon1>; +- }; +- }; +- +- tcon1_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tcon1_out_hdmi: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&hdmi_in_tcon1>; +- }; +- }; +- }; +- }; +- +- mmc0: mmc@1c0f000 { +- compatible = "allwinner,sun8i-a83t-mmc", +- "allwinner,sun7i-a20-mmc"; +- reg = <0x01c0f000 0x1000>; +- clocks = <&ccu CLK_BUS_MMC0>, +- <&ccu CLK_MMC0>, +- <&ccu CLK_MMC0_OUTPUT>, +- <&ccu CLK_MMC0_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- resets = <&ccu RST_BUS_MMC0>; +- reset-names = "ahb"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc1: mmc@1c10000 { +- compatible = "allwinner,sun8i-a83t-mmc", +- "allwinner,sun7i-a20-mmc"; +- reg = <0x01c10000 0x1000>; +- clocks = <&ccu CLK_BUS_MMC1>, +- <&ccu CLK_MMC1>, +- <&ccu CLK_MMC1_OUTPUT>, +- <&ccu CLK_MMC1_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- resets = <&ccu RST_BUS_MMC1>; +- reset-names = "ahb"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc2: mmc@1c11000 { +- compatible = "allwinner,sun8i-a83t-emmc"; +- reg = <0x01c11000 0x1000>; +- clocks = <&ccu CLK_BUS_MMC2>, +- <&ccu CLK_MMC2>, +- <&ccu CLK_MMC2_OUTPUT>, +- <&ccu CLK_MMC2_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- resets = <&ccu RST_BUS_MMC2>; +- reset-names = "ahb"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- sid: eeprom@1c14000 { +- compatible = "allwinner,sun8i-a83t-sid"; +- reg = <0x1c14000 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ths_calibration: thermal-sensor-calibration@34 { +- reg = <0x34 8>; +- }; +- }; +- +- crypto: crypto@1c15000 { +- compatible = "allwinner,sun8i-a83t-crypto"; +- reg = <0x01c15000 0x1000>; +- interrupts = ; +- resets = <&ccu RST_BUS_SS>; +- clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; +- clock-names = "bus", "mod"; +- }; +- +- msgbox: mailbox@1c17000 { +- compatible = "allwinner,sun8i-a83t-msgbox", +- "allwinner,sun6i-a31-msgbox"; +- reg = <0x01c17000 0x1000>; +- clocks = <&ccu CLK_BUS_MSGBOX>; +- resets = <&ccu RST_BUS_MSGBOX>; +- interrupts = ; +- #mbox-cells = <1>; +- }; +- +- usb_otg: usb@1c19000 { +- compatible = "allwinner,sun8i-a83t-musb", +- "allwinner,sun8i-a33-musb"; +- reg = <0x01c19000 0x0400>; +- clocks = <&ccu CLK_BUS_OTG>; +- resets = <&ccu RST_BUS_OTG>; +- interrupts = ; +- interrupt-names = "mc"; +- phys = <&usbphy 0>; +- phy-names = "usb"; +- extcon = <&usbphy 0>; +- dr_mode = "otg"; +- status = "disabled"; +- }; +- +- usbphy: phy@1c19400 { +- compatible = "allwinner,sun8i-a83t-usb-phy"; +- reg = <0x01c19400 0x10>, +- <0x01c1a800 0x14>, +- <0x01c1b800 0x14>; +- reg-names = "phy_ctrl", +- "pmu1", +- "pmu2"; +- clocks = <&ccu CLK_USB_PHY0>, +- <&ccu CLK_USB_PHY1>, +- <&ccu CLK_USB_HSIC>, +- <&ccu CLK_USB_HSIC_12M>; +- clock-names = "usb0_phy", +- "usb1_phy", +- "usb2_phy", +- "usb2_hsic_12M"; +- resets = <&ccu RST_USB_PHY0>, +- <&ccu RST_USB_PHY1>, +- <&ccu RST_USB_HSIC>; +- reset-names = "usb0_reset", +- "usb1_reset", +- "usb2_reset"; +- status = "disabled"; +- #phy-cells = <1>; +- }; +- +- ehci0: usb@1c1a000 { +- compatible = "allwinner,sun8i-a83t-ehci", +- "generic-ehci"; +- reg = <0x01c1a000 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_EHCI0>; +- resets = <&ccu RST_BUS_EHCI0>; +- phys = <&usbphy 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci0: usb@1c1a400 { +- compatible = "allwinner,sun8i-a83t-ohci", +- "generic-ohci"; +- reg = <0x01c1a400 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; +- resets = <&ccu RST_BUS_OHCI0>; +- phys = <&usbphy 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ehci1: usb@1c1b000 { +- compatible = "allwinner,sun8i-a83t-ehci", +- "generic-ehci"; +- reg = <0x01c1b000 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_EHCI1>; +- resets = <&ccu RST_BUS_EHCI1>; +- phys = <&usbphy 2>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ccu: clock@1c20000 { +- compatible = "allwinner,sun8i-a83t-ccu"; +- reg = <0x01c20000 0x400>; +- clocks = <&osc24M>, <&osc16Md512>; +- clock-names = "hosc", "losc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pio: pinctrl@1c20800 { +- compatible = "allwinner,sun8i-a83t-pinctrl"; +- interrupt-parent = <&r_intc>; +- interrupts = , +- , +- ; +- reg = <0x01c20800 0x400>; +- clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>; +- clock-names = "apb", "hosc", "losc"; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <3>; +- #gpio-cells = <3>; +- +- /omit-if-no-ref/ +- csi_8bit_parallel_pins: csi-8bit-parallel-pins { +- pins = "PE0", "PE2", "PE3", "PE6", "PE7", +- "PE8", "PE9", "PE10", "PE11", +- "PE12", "PE13"; +- function = "csi"; +- }; +- +- /omit-if-no-ref/ +- csi_mclk_pin: csi-mclk-pin { +- pins = "PE1"; +- function = "csi"; +- }; +- +- emac_rgmii_pins: emac-rgmii-pins { +- pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", +- "PD11", "PD12", "PD13", "PD14", "PD18", +- "PD19", "PD21", "PD22", "PD23"; +- function = "gmac"; +- /* +- * data lines in RGMII mode use DDR mode +- * and need a higher signal drive strength +- */ +- drive-strength = <40>; +- }; +- +- hdmi_pins: hdmi-pins { +- pins = "PH6", "PH7", "PH8"; +- function = "hdmi"; +- }; +- +- i2c0_pins: i2c0-pins { +- pins = "PH0", "PH1"; +- function = "i2c0"; +- }; +- +- i2c1_pins: i2c1-pins { +- pins = "PH2", "PH3"; +- function = "i2c1"; +- }; +- +- /omit-if-no-ref/ +- i2c2_pe_pins: i2c2-pe-pins { +- pins = "PE14", "PE15"; +- function = "i2c2"; +- }; +- +- i2c2_ph_pins: i2c2-ph-pins { +- pins = "PH4", "PH5"; +- function = "i2c2"; +- }; +- +- i2s1_pins: i2s1-pins { +- /* I2S1 does not have external MCLK pin */ +- pins = "PG10", "PG11", "PG12", "PG13"; +- function = "i2s1"; +- }; +- +- lcd_lvds_pins: lcd-lvds-pins { +- pins = "PD18", "PD19", "PD20", "PD21", "PD22", +- "PD23", "PD24", "PD25", "PD26", "PD27"; +- function = "lvds0"; +- }; +- +- mmc0_pins: mmc0-pins { +- pins = "PF0", "PF1", "PF2", +- "PF3", "PF4", "PF5"; +- function = "mmc0"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc1_pins: mmc1-pins { +- pins = "PG0", "PG1", "PG2", +- "PG3", "PG4", "PG5"; +- function = "mmc1"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { +- pins = "PC5", "PC6", "PC8", "PC9", +- "PC10", "PC11", "PC12", "PC13", +- "PC14", "PC15", "PC16"; +- function = "mmc2"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- pwm_pin: pwm-pin { +- pins = "PD28"; +- function = "pwm"; +- }; +- +- spdif_tx_pin: spdif-tx-pin { +- pins = "PE18"; +- function = "spdif"; +- }; +- +- uart0_pb_pins: uart0-pb-pins { +- pins = "PB9", "PB10"; +- function = "uart0"; +- }; +- +- uart0_pf_pins: uart0-pf-pins { +- pins = "PF2", "PF4"; +- function = "uart0"; +- }; +- +- uart1_pins: uart1-pins { +- pins = "PG6", "PG7"; +- function = "uart1"; +- }; +- +- uart1_rts_cts_pins: uart1-rts-cts-pins { +- pins = "PG8", "PG9"; +- function = "uart1"; +- }; +- +- /omit-if-no-ref/ +- uart2_pb_pins: uart2-pb-pins { +- pins = "PB0", "PB1"; +- function = "uart2"; +- }; +- }; +- +- timer@1c20c00 { +- compatible = "allwinner,sun8i-a23-timer"; +- reg = <0x01c20c00 0xa0>; +- interrupts = , +- ; +- clocks = <&osc24M>; +- }; +- +- watchdog@1c20ca0 { +- compatible = "allwinner,sun6i-a31-wdt"; +- reg = <0x01c20ca0 0x20>; +- interrupts = ; +- clocks = <&osc24M>; +- }; +- +- spdif: spdif@1c21000 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun8i-a83t-spdif", +- "allwinner,sun8i-h3-spdif"; +- reg = <0x01c21000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; +- resets = <&ccu RST_BUS_SPDIF>; +- clock-names = "apb", "spdif"; +- dmas = <&dma 2>; +- dma-names = "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spdif_tx_pin>; +- status = "disabled"; +- }; +- +- i2s0: i2s@1c22000 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun8i-a83t-i2s"; +- reg = <0x01c22000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; +- clock-names = "apb", "mod"; +- dmas = <&dma 3>, <&dma 3>; +- resets = <&ccu RST_BUS_I2S0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2s1: i2s@1c22400 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun8i-a83t-i2s"; +- reg = <0x01c22400 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; +- clock-names = "apb", "mod"; +- dmas = <&dma 4>, <&dma 4>; +- resets = <&ccu RST_BUS_I2S1>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s1_pins>; +- status = "disabled"; +- }; +- +- i2s2: i2s@1c22800 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun8i-a83t-i2s"; +- reg = <0x01c22800 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; +- clock-names = "apb", "mod"; +- dmas = <&dma 27>; +- resets = <&ccu RST_BUS_I2S2>; +- dma-names = "tx"; +- status = "disabled"; +- }; +- +- pwm: pwm@1c21400 { +- compatible = "allwinner,sun8i-a83t-pwm", +- "allwinner,sun8i-h3-pwm"; +- reg = <0x01c21400 0x400>; +- clocks = <&osc24M>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- uart0: serial@1c28000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART0>; +- resets = <&ccu RST_BUS_UART0>; +- status = "disabled"; +- }; +- +- uart1: serial@1c28400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28400 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART1>; +- resets = <&ccu RST_BUS_UART1>; +- status = "disabled"; +- }; +- +- uart2: serial@1c28800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28800 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART2>; +- resets = <&ccu RST_BUS_UART2>; +- status = "disabled"; +- }; +- +- uart3: serial@1c28c00 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28c00 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART3>; +- resets = <&ccu RST_BUS_UART3>; +- status = "disabled"; +- }; +- +- uart4: serial@1c29000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c29000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART4>; +- resets = <&ccu RST_BUS_UART4>; +- status = "disabled"; +- }; +- +- i2c0: i2c@1c2ac00 { +- compatible = "allwinner,sun8i-a83t-i2c", +- "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2ac00 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C0>; +- resets = <&ccu RST_BUS_I2C0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c1: i2c@1c2b000 { +- compatible = "allwinner,sun8i-a83t-i2c", +- "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2b000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C1>; +- resets = <&ccu RST_BUS_I2C1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c2: i2c@1c2b400 { +- compatible = "allwinner,sun8i-a83t-i2c", +- "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2b400 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C2>; +- resets = <&ccu RST_BUS_I2C2>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- emac: ethernet@1c30000 { +- compatible = "allwinner,sun8i-a83t-emac"; +- syscon = <&syscon>; +- reg = <0x01c30000 0x104>; +- interrupts = ; +- interrupt-names = "macirq"; +- clocks = <&ccu CLK_BUS_EMAC>; +- clock-names = "stmmaceth"; +- resets = <&ccu RST_BUS_EMAC>; +- reset-names = "stmmaceth"; +- status = "disabled"; +- +- mdio: mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- gic: interrupt-controller@1c81000 { +- compatible = "arm,gic-400"; +- reg = <0x01c81000 0x1000>, +- <0x01c82000 0x2000>, +- <0x01c84000 0x2000>, +- <0x01c86000 0x2000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = ; +- }; +- +- csi: camera@1cb0000 { +- compatible = "allwinner,sun8i-a83t-csi"; +- reg = <0x01cb0000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_CSI>, +- <&ccu CLK_CSI_SCLK>, +- <&ccu CLK_DRAM_CSI>; +- clock-names = "bus", "mod", "ram"; +- resets = <&ccu RST_BUS_CSI>; +- status = "disabled"; +- }; +- +- hdmi: hdmi@1ee0000 { +- compatible = "allwinner,sun8i-a83t-dw-hdmi"; +- reg = <0x01ee0000 0x10000>; +- reg-io-width = <1>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, +- <&ccu CLK_HDMI>; +- clock-names = "iahb", "isfr", "tmds"; +- resets = <&ccu RST_BUS_HDMI1>; +- reset-names = "ctrl"; +- phys = <&hdmi_phy>; +- phy-names = "phy"; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_pins>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- hdmi_in: port@0 { +- reg = <0>; +- +- hdmi_in_tcon1: endpoint { +- remote-endpoint = <&tcon1_out_hdmi>; +- }; +- }; +- +- hdmi_out: port@1 { +- reg = <1>; +- }; +- }; +- }; +- +- hdmi_phy: hdmi-phy@1ef0000 { +- compatible = "allwinner,sun8i-a83t-hdmi-phy"; +- reg = <0x01ef0000 0x10000>; +- clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; +- clock-names = "bus", "mod"; +- resets = <&ccu RST_BUS_HDMI0>; +- reset-names = "phy"; +- #phy-cells = <0>; +- }; +- +- r_intc: interrupt-controller@1f00c00 { +- compatible = "allwinner,sun8i-a83t-r-intc", +- "allwinner,sun6i-a31-r-intc"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x01f00c00 0x400>; +- interrupts = ; +- }; +- +- r_ccu: clock@1f01400 { +- compatible = "allwinner,sun8i-a83t-r-ccu"; +- reg = <0x01f01400 0x400>; +- clocks = <&osc24M>, <&osc16Md512>, <&osc16M>, +- <&ccu CLK_PLL_PERIPH>; +- clock-names = "hosc", "losc", "iosc", "pll-periph"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- r_cpucfg@1f01c00 { +- compatible = "allwinner,sun8i-a83t-r-cpucfg"; +- reg = <0x1f01c00 0x400>; +- }; +- +- r_cir: ir@1f02000 { +- compatible = "allwinner,sun8i-a83t-ir", +- "allwinner,sun6i-a31-ir"; +- clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; +- clock-names = "apb", "ir"; +- resets = <&r_ccu RST_APB0_IR>; +- interrupts = ; +- reg = <0x01f02000 0x400>; +- pinctrl-names = "default"; +- pinctrl-0 = <&r_cir_pin>; +- status = "disabled"; +- }; +- +- r_lradc: lradc@1f03c00 { +- compatible = "allwinner,sun8i-a83t-r-lradc"; +- reg = <0x01f03c00 0x100>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- status = "disabled"; +- }; +- +- r_pio: pinctrl@1f02c00 { +- compatible = "allwinner,sun8i-a83t-r-pinctrl"; +- reg = <0x01f02c00 0x400>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, +- <&osc16Md512>; +- clock-names = "apb", "hosc", "losc"; +- gpio-controller; +- #gpio-cells = <3>; +- interrupt-controller; +- #interrupt-cells = <3>; +- +- r_cir_pin: r-cir-pin { +- pins = "PL12"; +- function = "s_cir_rx"; +- }; +- +- r_rsb_pins: r-rsb-pins { +- pins = "PL0", "PL1"; +- function = "s_rsb"; +- drive-strength = <20>; +- bias-pull-up; +- }; +- }; +- +- r_rsb: rsb@1f03400 { +- compatible = "allwinner,sun8i-a83t-rsb", +- "allwinner,sun8i-a23-rsb"; +- reg = <0x01f03400 0x400>; +- interrupts = ; +- clocks = <&r_ccu CLK_APB0_RSB>; +- clock-frequency = <3000000>; +- resets = <&r_ccu RST_APB0_RSB>; +- pinctrl-names = "default"; +- pinctrl-0 = <&r_rsb_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- ths: thermal-sensor@1f04000 { +- compatible = "allwinner,sun8i-a83t-ths"; +- reg = <0x01f04000 0x100>; +- interrupts = ; +- nvmem-cells = <&ths_calibration>; +- nvmem-cell-names = "calibration"; +- #thermal-sensor-cells = <1>; +- }; +- }; +- +- thermal-zones { +- cpu0_thermal: cpu0-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&ths 0>; +- +- trips { +- cpu0_hot: cpu-hot { +- temperature = <80000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu0_very_hot: cpu-very-hot { +- temperature = <100000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- cpu-hot-limit { +- trip = <&cpu0_hot>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu1_thermal: cpu1-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&ths 1>; +- +- trips { +- cpu1_hot: cpu-hot { +- temperature = <80000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu1_very_hot: cpu-very-hot { +- temperature = <100000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- cpu-hot-limit { +- trip = <&cpu1_hot>; +- cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- gpu_thermal: gpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&ths 2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h2-plus-bananapi-m2-zero.dts b/scripts/dtc/include-prefixes/arm/sun8i-h2-plus-bananapi-m2-zero.dts +deleted file mode 100644 +index 8e8634ff2f9d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h2-plus-bananapi-m2-zero.dts ++++ /dev/null +@@ -1,272 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2017 Icenowy Zheng +- * +- * Based on sun8i-h3-bananapi-m2-plus.dts, which is: +- * Copyright (C) 2016 Chen-Yu Tsai +- */ +- +-/dts-v1/; +-#include "sun8i-h3.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Banana Pi BPI-M2-Zero"; +- compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "c"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pwr_led { +- label = "bananapi-m2-zero:red:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */ +- default-state = "on"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- sw4 { +- label = "power"; +- linux,code = ; +- gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- reg_vdd_cpux: vdd-cpux-regulator { +- compatible = "regulator-gpio"; +- regulator-name = "vdd-cpux"; +- regulator-type = "voltage"; +- regulator-boot-on; +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1300000>; +- regulator-ramp-delay = <50>; /* 4ms */ +- +- gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */ +- enable-active-high; +- gpios-states = <0x1>; +- states = <1100000 0>, <1300000 1>; +- }; +- +- reg_vcc_dram: vcc-dram { +- compatible = "regulator-fixed"; +- regulator-name = "vcc-dram"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ +- vin-supply = <®_vcc5v0>; +- }; +- +- reg_vcc1v2: vcc1v2 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc1v2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ +- vin-supply = <®_vcc5v0>; +- }; +- +- poweroff { +- compatible = "regulator-poweroff"; +- cpu-supply = <®_vcc1v2>; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ +- clocks = <&rtc 1>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_vdd_cpux>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- /* +- * On the production batch of this board the card detect GPIO is +- * high active (card inserted), although on the early samples it's +- * low active. +- */ +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- vqmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&pio>; +- interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- max-speed = <1500000>; +- clocks = <&rtc 1>; +- clock-names = "lpo"; +- vbat-supply = <®_vcc3v3>; +- vddio-supply = <®_vcc3v3>; +- device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ +- host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ +- shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +- }; +- +-}; +- +-&pio { +- gpio-line-names = +- /* PA */ +- "CON2-P13", "CON2-P11", "CON2-P22", "CON2-P15", +- "CON3-P03", "CON3-P02", "CON2-P07", "CON2-P29", +- "CON2-P31", "CON2-P33", "CON2-P35", "CON2-P05", +- "CON2-P03", "CON2-P08", "CON2-P10", "CON2-P16", +- "CON2-P12", "CON2-P37", "CON2-P28", "CON2-P27", +- "CON2-P40", "CON2-P38", "", "", +- "", "", "", "", "", "", "", "", +- +- /* PB */ +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- +- /* PC */ +- "CON2-P19", "CON2-P21", "CON2-P23", "CON2-P24", +- "CON2-P18", "", "", "CON2-P26", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- +- /* PD */ +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "CSI-PWR-EN", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- +- /* PE */ +- "CN3-P17", "CN3-P13", "CN3-P09", "CN3-P07", +- "CN3-P19", "CN3-P21", "CN3-P22", "CN3-P20", +- "CN3-P18", "CN3-P16", "CN3-P14", "CN3-P12", +- "CN3-P05", "CN3-P03", "CN3-P06", "CN3-P08", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- +- /* PF */ +- "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3", +- "SDC0-D2", "SDC0-DET", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- +- /* PG */ +- "WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1", +- "WL-SDIO-D2", "WL-SDIO-D3", "BT-UART-TX", "BT-UART-RX", +- "BT-UART-RTS", "BT-UART-CTS", "WL-WAKE-AP", "BT-WAKE-AP", +- "BT-RST-N", "AP-WAKE-BT", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&r_pio { +- gpio-line-names = +- /* PL */ +- "", "CPUX-SET", "CON2-P32", "POWER-KEY", "CON2-P36", +- "VCC-IO-EN", "USB0-ID", "WL-PWR-EN", +- "PWR-STB", "PWR-DRAM", "PWR-LED", "IR-RX", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ +- /* +- * There're two micro-USB connectors, one is power-only and another is +- * OTG. The Vbus of these two connectors are connected together, so +- * the external USB device will be powered just by the power input +- * from the power-only USB port. +- */ +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h2-plus-libretech-all-h3-cc.dts b/scripts/dtc/include-prefixes/arm/sun8i-h2-plus-libretech-all-h3-cc.dts +deleted file mode 100644 +index 4db0d4bb65eb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h2-plus-libretech-all-h3-cc.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2018 Chen-Yu Tsai +- */ +- +-/dts-v1/; +-#include "sun8i-h3.dtsi" +-#include "sunxi-libretech-all-h3-cc.dtsi" +- +-/ { +- model = "Libre Computer Board ALL-H3-CC H2+"; +- compatible = "libretech,all-h3-cc-h2-plus", "allwinner,sun8i-h2-plus"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h2-plus-orangepi-r1.dts b/scripts/dtc/include-prefixes/arm/sun8i-h2-plus-orangepi-r1.dts +deleted file mode 100644 +index 3356f4210d45..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h2-plus-orangepi-r1.dts ++++ /dev/null +@@ -1,99 +0,0 @@ +-/* +- * Copyright (C) 2017 Icenowy Zheng +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/* Orange Pi R1 is based on Orange Pi Zero design */ +-#include "sun8i-h2-plus-orangepi-zero.dts" +- +-/ { +- model = "Xunlong Orange Pi R1"; +- compatible = "xunlong,orangepi-r1", "allwinner,sun8i-h2-plus"; +- +- /delete-node/ reg_vcc_wifi; +- +- /* +- * Ths pin of this regulator is the same with the Wi-Fi extra +- * regulator on the original Zero. However it's used for USB +- * Ethernet rather than the Wi-Fi now. +- */ +- reg_vcc_usb_eth: reg-vcc-usb-ethernet { +- compatible = "regulator-fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-usb-ethernet"; +- enable-active-high; +- gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>; +- }; +- +- aliases { +- ethernet1 = &rtl8189etv; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- +- flash@0 { +- compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; +- }; +-}; +- +-&ohci1 { +- /* +- * RTL8152B USB-Ethernet adapter is connected to USB1, +- * and it's a USB 2.0 device. So the OHCI1 controller +- * can be left disabled. +- */ +- status = "disabled"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- vqmmc-supply = <®_vcc3v3>; +- +- rtl8189etv: sdio_wifi@1 { +- reg = <1>; +- }; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_vcc_usb_eth>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h2-plus-orangepi-zero.dts b/scripts/dtc/include-prefixes/arm/sun8i-h2-plus-orangepi-zero.dts +deleted file mode 100644 +index f19ed981da9d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h2-plus-orangepi-zero.dts ++++ /dev/null +@@ -1,209 +0,0 @@ +-/* +- * Copyright (C) 2016 Icenowy Zheng +- * +- * Based on sun8i-h3-orangepi-one.dts, which is: +- * Copyright (C) 2016 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-h3.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Xunlong Orange Pi Zero"; +- compatible = "xunlong,orangepi-zero", "allwinner,sun8i-h2-plus"; +- +- aliases { +- serial0 = &uart0; +- /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ +- ethernet0 = &emac; +- ethernet1 = &xr819; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pwr_led { +- label = "orangepi:green:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- status_led { +- label = "orangepi:red:status"; +- gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- reg_vcc_wifi: reg_vcc_wifi { +- compatible = "regulator-fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +- enable-active-high; +- gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_vdd_cpux: vdd-cpux-regulator { +- compatible = "regulator-gpio"; +- regulator-name = "vdd-cpux"; +- regulator-type = "voltage"; +- regulator-boot-on; +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1300000>; +- regulator-ramp-delay = <50>; /* 4ms */ +- +- gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ +- enable-active-high; +- gpios-states = <1>; +- states = <1100000 0>, <1300000 1>; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; +- post-power-on-delay-ms = <200>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_vdd_cpux>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&int_mii_phy>; +- phy-mode = "mii"; +- allwinner,leds-active-low; +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc_wifi>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- /* +- * Explicitly define the sdio device, so that we can add an ethernet +- * alias for it (which e.g. makes u-boot set a mac-address). +- */ +- xr819: sdio_wifi@1 { +- reg = <1>; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&spi0 { +- /* Disable SPI NOR by default: it optional on Orange Pi Zero boards */ +- status = "disabled"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mxicy,mx25l1606e", "winbond,w25q128"; +- reg = <0>; +- spi-max-frequency = <40000000>; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- status = "disabled"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "disabled"; +-}; +- +-&usb_otg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usbphy { +- /* +- * USB Type-A port VBUS is always on. However, MicroUSB VBUS can only +- * power up the board; when it's used as OTG port, this VBUS is +- * always off even if the board is powered via GPIO pins. +- */ +- status = "okay"; +- usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-bananapi-m2-plus-v1.2.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-bananapi-m2-plus-v1.2.dts +deleted file mode 100644 +index fc4a8c3d084d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-bananapi-m2-plus-v1.2.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2018 Chen-Yu Tsai +- */ +- +-/dts-v1/; +-#include "sun8i-h3.dtsi" +-#include "sunxi-bananapi-m2-plus-v1.2.dtsi" +- +-/ { +- model = "Banana Pi BPI-M2-Plus v1.2 H3"; +- compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun8i-h3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-bananapi-m2-plus.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-bananapi-m2-plus.dts +deleted file mode 100644 +index 195a75da13f1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-bananapi-m2-plus.dts ++++ /dev/null +@@ -1,50 +0,0 @@ +-/* +- * Copyright (C) 2016 Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-h3.dtsi" +-#include "sunxi-bananapi-m2-plus.dtsi" +- +-/ { +- model = "Banana Pi BPI-M2-Plus H3"; +- compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-beelink-x2.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-beelink-x2.dts +deleted file mode 100644 +index f0e591e1c771..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-beelink-x2.dts ++++ /dev/null +@@ -1,232 +0,0 @@ +-/* +- * Copyright (C) 2017 Marcus Cooper +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-h3.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Beelink X2"; +- compatible = "roofull,beelink-x2", "allwinner,sun8i-h3"; +- +- aliases { +- serial0 = &uart0; +- ethernet0 = &emac; +- ethernet1 = &sdiowifi; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "beelink-x2:blue:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ +- default-state = "on"; +- }; +- +- led-1 { +- label = "beelink-x2:red:standby"; +- gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ +- }; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ +- clocks = <&rtc 1>; +- clock-names = "ext_clock"; +- }; +- +- sound_spdif { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "On-board SPDIF"; +- +- simple-audio-card,cpu { +- sound-dai = <&spdif>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&spdif_out>; +- }; +- }; +- +- spdif_out: spdif-out { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- }; +- +- r-gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "power"; +- linux,code = ; +- gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; +- wakeup-source; +- }; +- }; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&int_mii_phy>; +- phy-mode = "mii"; +- allwinner,leds-active-low; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&ir { +- linux,rc-map-name = "rc-tanix-tx3mini"; +- pinctrl-names = "default"; +- pinctrl-0 = <&r_ir_rx_pin>; +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- vqmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- /* +- * Explicitly define the sdio device, so that we can add an ethernet +- * alias for it (which e.g. makes u-boot set a mac-address). +- */ +- sdiowifi: sdio_wifi@1 { +- reg = <1>; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_pins>; +- vmmc-supply = <®_vcc3v3>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-®_usb0_vbus { +- gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ +- status = "okay"; +-}; +- +-&spdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&spdif_tx_pin>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- /* USB VBUS is always on except for the OTG port */ +- status = "okay"; +- usb0_id_det-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA07 */ +- usb0_vbus-supply = <®_usb0_vbus>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-emlid-neutis-n5h3-devboard.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-emlid-neutis-n5h3-devboard.dts +deleted file mode 100644 +index 02fbe00cde97..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-emlid-neutis-n5h3-devboard.dts ++++ /dev/null +@@ -1,72 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * DTS for Emlid Neutis N5 Dev board. +- * +- * Copyright (C) 2019 Georgii Staroselskii +- */ +- +-/dts-v1/; +- +-#include "sun8i-h3-emlid-neutis-n5h3.dtsi" +- +-/ { +- model = "Emlid Neutis N5H3 Developer board"; +- compatible = "emlid,neutis-n5h3-devboard", +- "emlid,neutis-n5h3", +- "allwinner,sun8i-h3"; +- +- vdd_cpux: gpio-regulator { +- compatible = "regulator-gpio"; +- regulator-name = "vdd-cpux"; +- regulator-type = "voltage"; +- regulator-boot-on; +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1300000>; +- regulator-ramp-delay = <50>; /* 4ms */ +- gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ +- gpios-states = <0x1>; +- states = <1100000 0x0>, <1300000 0x1>; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_cpux>; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&int_mii_phy>; +- phy-mode = "mii"; +- allwinner,leds-active-low; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-emlid-neutis-n5h3.dtsi b/scripts/dtc/include-prefixes/arm/sun8i-h3-emlid-neutis-n5h3.dtsi +deleted file mode 100644 +index eedd5da5dc2f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-emlid-neutis-n5h3.dtsi ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * DTSI for Emlid Neutis N5 SoM. +- * +- * Copyright (C) 2019 Georgii Staroselskii +- */ +- +-/dts-v1/; +- +-#include "sun8i-h3.dtsi" +-#include +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-libretech-all-h3-cc.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-libretech-all-h3-cc.dts +deleted file mode 100644 +index a8b2f0f1c11d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-libretech-all-h3-cc.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-/* +- * Copyright (C) 2017 Chen-Yu Tsai +- * +- * SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- */ +- +-/dts-v1/; +-#include "sun8i-h3.dtsi" +-#include "sunxi-libretech-all-h3-cc.dtsi" +- +-/ { +- model = "Libre Computer Board ALL-H3-CC H3"; +- compatible = "libretech,all-h3-cc-h3", "allwinner,sun8i-h3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-mapleboard-mp130.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-mapleboard-mp130.dts +deleted file mode 100644 +index ff0a7a952e0c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-mapleboard-mp130.dts ++++ /dev/null +@@ -1,152 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2017 Centrum Embedded Systems, Jia-Bin Huang +- * Copyright (C) 2018 Jonathan McDowell +- */ +- +-/dts-v1/; +-#include "sun8i-h3.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "MapleBoard MP130"; +- compatible = "mapleboard,mp130", "allwinner,sun8i-h3"; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pwr_led { +- label = "mp130:orange:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- status_led { +- label = "mp130:orange:status"; +- gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- r_gpio_keys { +- compatible = "gpio-keys"; +- +- power { +- label = "power"; +- linux,code = ; +- gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ +- }; +- +- user { +- label = "user"; +- linux,code = ; +- gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&codec { +- allwinner,audio-routing = +- "Line Out", "LINEOUT", +- "LINEIN", "Line In"; +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&ehci3 { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&int_mii_phy>; +- phy-mode = "mii"; +- allwinner,leds-active-low; +- status = "okay"; +-}; +- +-&ir { +- pinctrl-names = "default"; +- pinctrl-0 = <&r_ir_rx_pin>; +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_pins>; +- vmmc-supply = <®_vcc3v3>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-&ohci3 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- status = "disabled"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "disabled"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- status = "disabled"; +-}; +- +-&usb_otg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usbphy { +- /* USB VBUS is always on */ +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi-duo2.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi-duo2.dts +deleted file mode 100644 +index 8e7dfcffe1fb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi-duo2.dts ++++ /dev/null +@@ -1,173 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 Karl Palsson +- */ +- +-/dts-v1/; +-#include "sun8i-h3.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "FriendlyARM NanoPi Duo2"; +- compatible = "friendlyarm,nanopi-duo2", "allwinner,sun8i-h3"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "nanopi:red:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ +- default-state = "on"; +- }; +- +- led-1 { +- label = "nanopi:green:status"; +- gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ +- }; +- }; +- +- r_gpio_keys { +- compatible = "gpio-keys"; +- +- k1 { +- label = "k1"; +- linux,code = ; +- gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ +- }; +- }; +- +- reg_vdd_cpux: vdd-cpux-regulator { +- compatible = "regulator-gpio"; +- regulator-name = "vdd-cpux"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-ramp-delay = <50>; /* 4ms */ +- +- enable-active-high; +- enable-gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ +- gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ +- gpios-states = <0x1>; +- states = <1100000 0>, <1300000 1>; +- }; +- +- reg_vcc_dram: vcc-dram { +- compatible = "regulator-fixed"; +- regulator-name = "vcc-dram"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ +- vin-supply = <®_vcc5v0>; +- }; +- +- reg_vdd_sys: vdd-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-sys"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ +- vin-supply = <®_vcc5v0>; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ +- clocks = <&rtc 1>; +- clock-names = "ext_clock"; +- }; +- +-}; +- +-&cpu0 { +- cpu-supply = <®_vdd_cpux>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&mmc0 { +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +- vmmc-supply = <®_vcc3v3>; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- vqmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- sdio_wifi: sdio_wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&pio>; +- interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-®_usb0_vbus { +- gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&rtc 1>; +- clock-names = "lpo"; +- vbat-supply = <®_vcc3v3>; +- vddio-supply = <®_vcc3v3>; +- device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ +- host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ +- shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ +- }; +-}; +- +-&usb_otg { +- status = "okay"; +- dr_mode = "otg"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi-m1-plus.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi-m1-plus.dts +deleted file mode 100644 +index 4ba533b0340f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi-m1-plus.dts ++++ /dev/null +@@ -1,166 +0,0 @@ +-/* +- * Copyright (C) 2017 Jagan Teki +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "sun8i-h3-nanopi.dtsi" +- +-/ { +- model = "FriendlyArm NanoPi M1 Plus"; +- compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3"; +- +- aliases { +- serial1 = &uart3; +- ethernet0 = &emac; +- ethernet1 = &sdio_wifi; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- enable-active-high; +- gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_rgmii_pins>; +- phy-supply = <®_gmac_3v3>; +- phy-handle = <&ext_rgmii_phy>; +- phy-mode = "rgmii"; +- +- status = "okay"; +-}; +- +-&external_mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <7>; +- }; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&ir { +- pinctrl-names = "default"; +- pinctrl-0 = <&r_ir_rx_pin>; +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- vqmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- sdio_wifi: sdio_wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&pio>; +- interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_pins>; +- vmmc-supply = <®_vcc3v3>; +- vqmmc-supply = <®_vcc3v3>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi-m1.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi-m1.dts +deleted file mode 100644 +index 69243dcb30a6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi-m1.dts ++++ /dev/null +@@ -1,106 +0,0 @@ +-/* +- * Copyright (C) 2016 Milo Kim +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "sun8i-h3-nanopi.dtsi" +- +-/ { +- model = "FriendlyArm NanoPi M1"; +- compatible = "friendlyarm,nanopi-m1", "allwinner,sun8i-h3"; +- +- aliases { +- ethernet0 = &emac; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&int_mii_phy>; +- phy-mode = "mii"; +- allwinner,leds-active-low; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&ir { +- pinctrl-names = "default"; +- pinctrl-0 = <&r_ir_rx_pin>; +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi-neo-air.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi-neo-air.dts +deleted file mode 100644 +index be49eabbff94..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi-neo-air.dts ++++ /dev/null +@@ -1,115 +0,0 @@ +-/* +- * Copyright (C) 2017 Jelle van der Waa +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-h3.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- model = "FriendlyARM NanoPi NEO Air"; +- compatible = "friendlyarm,nanopi-neo-air", "allwinner,sun8i-h3"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "nanopi:green:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ +- default-state = "on"; +- }; +- +- led-1 { +- label = "nanopi:blue:status"; +- gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ +- }; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- vqmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- brcmf: bcrmf@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&pio>; +- interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- /* USB VBUS is always on */ +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi-neo.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi-neo.dts +deleted file mode 100644 +index 9f33f6fae595..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi-neo.dts ++++ /dev/null +@@ -1,72 +0,0 @@ +-/* +- * Copyright (C) 2016 James Pettigrew +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "sun8i-h3-nanopi.dtsi" +- +-/ { +- model = "FriendlyARM NanoPi NEO"; +- compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&int_mii_phy>; +- phy-mode = "mii"; +- allwinner,leds-active-low; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +- dr_mode = "peripheral"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi-r1.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi-r1.dts +deleted file mode 100644 +index 26e2e6172e0d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi-r1.dts ++++ /dev/null +@@ -1,169 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 Igor Pecovnik +- * Copyright (C) 2020 Jayantajit Gogoi +- * Copyright (C) 2020 Yu-Tung Chang +-*/ +- +-#include "sun8i-h3-nanopi.dtsi" +-#include +- +-/ { +- model = "FriendlyARM NanoPi R1"; +- compatible = "friendlyarm,nanopi-r1", "allwinner,sun8i-h3"; +- +- aliases { +- serial1 = &uart1; +- ethernet0 = &emac; +- ethernet1 = &wifi; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- enable-active-high; +- gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ +- }; +- +- reg_vdd_cpux: gpio-regulator { +- compatible = "regulator-gpio"; +- regulator-name = "vdd-cpux"; +- regulator-type = "voltage"; +- regulator-boot-on; +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1300000>; +- regulator-ramp-delay = <50>; +- gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ +- gpios-states = <0x1>; +- states = <1100000 0x0>, +- <1300000 0x1>; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ +- clocks = <&rtc 1>; +- clock-names = "ext_clock"; +- }; +- +- leds { +- led-2 { +- function = LED_FUNCTION_WAN; +- color = ; +- gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ +- }; +- +- led-3 { +- function = LED_FUNCTION_LAN; +- color = ; +- gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; /* PA9 */ +- }; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_vdd_cpux>; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_rgmii_pins>; +- phy-supply = <®_gmac_3v3>; +- phy-handle = <&ext_rgmii_phy>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&external_mdio { +- ext_rgmii_phy: ethernet-phy@7 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <7>; +- }; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- vqmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- wifi: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&pio>; +- interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_pins>; +- vmmc-supply = <®_vcc3v3>; +- vqmmc-supply = <®_vcc3v3>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-®_usb0_vbus { +- gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&rtc 1>; +- clock-names = "lpo"; +- vbat-supply = <®_vcc3v3>; +- vddio-supply = <®_vcc3v3>; +- device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ +- host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ +- shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ +- }; +-}; +- +-&usb_otg { +- status = "okay"; +- dr_mode = "otg"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi.dtsi b/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi.dtsi +deleted file mode 100644 +index c7c3e7d8b3c8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-nanopi.dtsi ++++ /dev/null +@@ -1,111 +0,0 @@ +-/* +- * Copyright (C) 2016 James Pettigrew +- * Copyright (C) 2016 Milo Kim +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-h3.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "nanopi:blue:status"; +- gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-1 { +- label = "nanopi:green:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- r_gpio_keys { +- compatible = "gpio-keys"; +- input-name = "k1"; +- +- k1 { +- label = "k1"; +- linux,code = ; +- gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&ehci3 { +- status = "okay"; +-}; +- +-&mmc0 { +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; +- status = "okay"; +- vmmc-supply = <®_vcc3v3>; +-}; +- +-&ohci3 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-2.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-2.dts +deleted file mode 100644 +index 597c425d08ec..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-2.dts ++++ /dev/null +@@ -1,208 +0,0 @@ +-/* +- * Copyright (C) 2016 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-h3.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Xunlong Orange Pi 2"; +- compatible = "xunlong,orangepi-2", "allwinner,sun8i-h3"; +- +- aliases { +- serial0 = &uart0; +- /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ +- ethernet0 = &emac; +- ethernet1 = &rtl8189; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- status_led { +- label = "orangepi:red:status"; +- gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; +- }; +- +- pwr_led { +- label = "orangepi:green:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- r_gpio_keys { +- compatible = "gpio-keys"; +- +- sw2 { +- label = "sw2"; +- linux,code = ; +- gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; +- }; +- +- sw4 { +- label = "sw4"; +- linux,code = ; +- gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */ +- }; +-}; +- +-&codec { +- allwinner,pa-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */ +- allwinner,audio-routing = +- "Speaker", "LINEOUT", +- "MIC1", "Mic", +- "Mic", "MBIAS"; +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&int_mii_phy>; +- phy-mode = "mii"; +- allwinner,leds-active-low; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&ir { +- pinctrl-names = "default"; +- pinctrl-0 = <&r_ir_rx_pin>; +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- /* +- * Explicitly define the sdio device, so that we can add an ethernet +- * alias for it (which e.g. makes u-boot set a mac-address). +- */ +- rtl8189: sdio_wifi@1 { +- reg = <1>; +- }; +-}; +- +-®_usb1_vbus { +- gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- status = "disabled"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "disabled"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- status = "disabled"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-lite.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-lite.dts +deleted file mode 100644 +index 6f9c97add54e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-lite.dts ++++ /dev/null +@@ -1,168 +0,0 @@ +-/* +- * Copyright (C) 2016 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-h3.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Xunlong Orange Pi Lite"; +- compatible = "xunlong,orangepi-lite", "allwinner,sun8i-h3"; +- +- aliases { +- /* The H3 emac is not used so the wifi is ethernet0 */ +- ethernet0 = &rtl8189ftv; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pwr_led { +- label = "orangepi:green:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- status_led { +- label = "orangepi:red:status"; +- gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- r_gpio_keys { +- compatible = "gpio-keys"; +- +- sw4 { +- label = "sw4"; +- linux,code = ; +- gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&ir { +- pinctrl-names = "default"; +- pinctrl-0 = <&r_ir_rx_pin>; +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- /* +- * Explicitly define the sdio device, so that we can add an ethernet +- * alias for it (which e.g. makes u-boot set a mac-address). +- */ +- rtl8189ftv: sdio_wifi@1 { +- reg = <1>; +- }; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- /* USB VBUS is always on */ +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-one.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-one.dts +deleted file mode 100644 +index 4759ba3f2986..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-one.dts ++++ /dev/null +@@ -1,203 +0,0 @@ +-/* +- * Copyright (C) 2016 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-h3.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Xunlong Orange Pi One"; +- compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pwr_led { +- label = "orangepi:green:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- status_led { +- label = "orangepi:red:status"; +- gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- r_gpio_keys { +- compatible = "gpio-keys"; +- +- sw4 { +- label = "sw4"; +- linux,code = ; +- gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- reg_vdd_cpux: vdd-cpux-regulator { +- compatible = "regulator-gpio"; +- regulator-name = "vdd-cpux"; +- regulator-type = "voltage"; +- regulator-boot-on; +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1300000>; +- regulator-ramp-delay = <50>; /* 4ms */ +- +- gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ +- enable-active-high; +- gpios-states = <0x1>; +- states = <1100000 0>, <1300000 1>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_vdd_cpux>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&int_mii_phy>; +- phy-mode = "mii"; +- allwinner,leds-active-low; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-®_usb0_vbus { +- gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- status = "disabled"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "disabled"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- status = "disabled"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- /* USB Type-A port's VBUS is always on */ +- usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-pc-plus.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-pc-plus.dts +deleted file mode 100644 +index babf4cf1b2f6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-pc-plus.dts ++++ /dev/null +@@ -1,86 +0,0 @@ +-/* +- * Copyright (C) 2016 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/* The Orange Pi PC Plus is an extended version of the regular PC */ +-#include "sun8i-h3-orangepi-pc.dts" +- +-/ { +- model = "Xunlong Orange Pi PC Plus"; +- compatible = "xunlong,orangepi-pc-plus", "allwinner,sun8i-h3"; +- +- aliases { +- /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ +- ethernet1 = &rtl8189ftv; +- }; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- /* +- * Explicitly define the sdio device, so that we can add an ethernet +- * alias for it (which e.g. makes u-boot set a mac-address). +- */ +- rtl8189ftv: sdio_wifi@1 { +- reg = <1>; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_pins>; +- vmmc-supply = <®_vcc3v3>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&mmc2_8bit_pins { +- /* Increase drive strength for DDR modes */ +- drive-strength = <40>; +- /* eMMC is missing pull-ups */ +- bias-pull-up; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-pc.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-pc.dts +deleted file mode 100644 +index 5aff8ecc66cb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-pc.dts ++++ /dev/null +@@ -1,241 +0,0 @@ +-/* +- * Copyright (C) 2015 Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-h3.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Xunlong Orange Pi PC"; +- compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pwr_led { +- label = "orangepi:green:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- status_led { +- label = "orangepi:red:status"; +- gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- r_gpio_keys { +- compatible = "gpio-keys"; +- +- sw4 { +- label = "sw4"; +- linux,code = ; +- gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&codec { +- allwinner,audio-routing = +- "Line Out", "LINEOUT", +- "MIC1", "Mic", +- "Mic", "MBIAS"; +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_vdd_cpux>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&ehci3 { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&int_mii_phy>; +- phy-mode = "mii"; +- allwinner,leds-active-low; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&ir { +- pinctrl-names = "default"; +- pinctrl-0 = <&r_ir_rx_pin>; +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-&ohci3 { +- status = "okay"; +-}; +- +-&r_i2c { +- status = "okay"; +- +- reg_vdd_cpux: regulator@65 { +- compatible = "silergy,sy8106a"; +- reg = <0x65>; +- regulator-name = "vdd-cpux"; +- silergy,fixed-microvolt = <1200000>; +- /* +- * The datasheet uses 1.1V as the minimum value of VDD-CPUX, +- * however both the Armbian DVFS table and the official one +- * have operating points with voltage under 1.1V, and both +- * DVFS table are known to work properly at the lowest +- * operating point. +- * +- * Use 1.0V as the minimum voltage instead. +- */ +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-®_usb0_vbus { +- gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- status = "disabled"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "disabled"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- status = "disabled"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- /* VBUS on USB host ports are always on */ +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-plus.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-plus.dts +deleted file mode 100644 +index d05fa679dcd3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-plus.dts ++++ /dev/null +@@ -1,135 +0,0 @@ +-/* +- * Copyright (C) 2015 Jens Kuske +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/* The Orange Pi Plus is an extended version of the Orange Pi 2 */ +-#include "sun8i-h3-orangepi-2.dts" +- +-/ { +- model = "Xunlong Orange Pi Plus / Plus 2"; +- compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; +- +- aliases { +- ethernet0 = &emac; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- enable-active-high; +- gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_usb3_vbus: usb3-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb3-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- enable-active-high; +- gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_vdd_cpux>; +-}; +- +-&ehci3 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_rgmii_pins>; +- phy-supply = <®_gmac_3v3>; +- phy-handle = <&ext_rgmii_phy>; +- phy-mode = "rgmii-id"; +- +- status = "okay"; +-}; +- +-&external_mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_pins>; +- vmmc-supply = <®_vcc3v3>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&mmc2_8bit_pins { +- /* Increase drive strength for DDR modes */ +- drive-strength = <40>; +- /* eMMC is missing pull-ups */ +- bias-pull-up; +-}; +- +-&r_i2c { +- status = "okay"; +- +- reg_vdd_cpux: regulator@65 { +- compatible = "silergy,sy8106a"; +- reg = <0x65>; +- regulator-name = "vdd-cpux"; +- silergy,fixed-microvolt = <1200000>; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-ramp-delay = <200>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&usbphy { +- usb3_vbus-supply = <®_usb3_vbus>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-plus2e.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-plus2e.dts +deleted file mode 100644 +index b6ca45d18e51..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-plus2e.dts ++++ /dev/null +@@ -1,79 +0,0 @@ +-/* +- * Copyright (C) 2016 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/* +- * The Orange Pi Plus 2E is an extended version of the Orange Pi PC Plus, +- * with 2G RAM and an external gbit ethernet phy. +- */ +- +-#include "sun8i-h3-orangepi-pc-plus.dts" +- +-/ { +- model = "Xunlong Orange Pi Plus 2E"; +- compatible = "xunlong,orangepi-plus2e", "allwinner,sun8i-h3"; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- enable-active-high; +- gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ +- }; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_rgmii_pins>; +- phy-supply = <®_gmac_3v3>; +- phy-handle = <&ext_rgmii_phy>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&external_mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-zero-plus2.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-zero-plus2.dts +deleted file mode 100644 +index 561ea1d2f861..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-orangepi-zero-plus2.dts ++++ /dev/null +@@ -1,177 +0,0 @@ +-/* +- * Copyright (C) 2017 Jagan Teki +- * Copyright (C) 2018 Diego Rondini +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include "sun8i-h3.dtsi" +- +-#include +- +-/ { +- model = "OrangePi Zero Plus2 H3"; +- compatible = "xunlong,orangepi-zero-plus2-h3", "allwinner,sun8i-h3"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "orangepi:green:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- led-1 { +- label = "orangepi:red:status"; +- gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- reg_vcc3v3: vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ +- post-power-on-delay-ms = <200>; +- }; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- vqmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&r_pio>; +- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_pins>; +- vmmc-supply = <®_vcc3v3>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- /* +- * According to schematics CN1 MicroUSB port can be used to take +- * external 5V to power up the board VBUS. On the contrary CN1 MicroUSB +- * port cannot provide power externally even if the board is powered +- * via GPIO pins. It thus makes sense to force peripheral mode. +- */ +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-rervision-dvk.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-rervision-dvk.dts +deleted file mode 100644 +index 4738f3a9efe4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-rervision-dvk.dts ++++ /dev/null +@@ -1,114 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 Bootlin +- * Author: Paul Kocialkowski +- */ +- +-/dts-v1/; +-#include "sun8i-h3.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "RerVision H3-DVK"; +- compatible = "rervision,h3-dvk", "allwinner,sun8i-h3"; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&ehci3 { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&int_mii_phy>; +- phy-mode = "mii"; +- allwinner,leds-active-low; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&mmc0 { +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +- vmmc-supply = <®_vcc3v3>; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_pins>; +- vmmc-supply = <®_vcc3v3>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-&ohci3 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +- dr_mode = "peripheral"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3-zeropi.dts b/scripts/dtc/include-prefixes/arm/sun8i-h3-zeropi.dts +deleted file mode 100644 +index 7d3e7323b661..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3-zeropi.dts ++++ /dev/null +@@ -1,85 +0,0 @@ +-/* +- * Copyright (C) 2020 Yu-Tung Chang +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "sun8i-h3-nanopi.dtsi" +- +-/ { +- model = "FriendlyARM ZeroPi"; +- compatible = "friendlyarm,zeropi", "allwinner,sun8i-h3"; +- +- aliases { +- ethernet0 = &emac; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- enable-active-high; +- gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ +- }; +-}; +- +-&external_mdio { +- ext_rgmii_phy: ethernet-phy@7 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <7>; +- }; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_rgmii_pins>; +- phy-supply = <®_gmac_3v3>; +- phy-handle = <&ext_rgmii_phy>; +- phy-mode = "rgmii-id"; +- +- allwinner,leds-active-low; +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-h3.dtsi b/scripts/dtc/include-prefixes/arm/sun8i-h3.dtsi +deleted file mode 100644 +index ae4f933abb89..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-h3.dtsi ++++ /dev/null +@@ -1,331 +0,0 @@ +-/* +- * Copyright (C) 2015 Jens Kuske +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "sunxi-h3-h5.dtsi" +-#include +- +-/ { +- cpu0_opp_table: opp-table-cpu { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-648000000 { +- opp-hz = /bits/ 64 <648000000>; +- opp-microvolt = <1040000 1040000 1300000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-816000000 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <1100000 1100000 1300000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-1008000000 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <1200000 1200000 1300000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <0>; +- clocks = <&ccu CLK_CPUX>; +- clock-names = "cpu"; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <1>; +- clocks = <&ccu CLK_CPUX>; +- clock-names = "cpu"; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <2>; +- clocks = <&ccu CLK_CPUX>; +- clock-names = "cpu"; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <3>; +- clocks = <&ccu CLK_CPUX>; +- clock-names = "cpu"; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- }; +- +- gpu_opp_table: opp-table-gpu { +- compatible = "operating-points-v2"; +- +- opp-120000000 { +- opp-hz = /bits/ 64 <120000000>; +- }; +- +- opp-312000000 { +- opp-hz = /bits/ 64 <312000000>; +- }; +- +- opp-432000000 { +- opp-hz = /bits/ 64 <432000000>; +- }; +- +- opp-576000000 { +- opp-hz = /bits/ 64 <576000000>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- soc { +- deinterlace: deinterlace@1400000 { +- compatible = "allwinner,sun8i-h3-deinterlace"; +- reg = <0x01400000 0x20000>; +- clocks = <&ccu CLK_BUS_DEINTERLACE>, +- <&ccu CLK_DEINTERLACE>, +- <&ccu CLK_DRAM_DEINTERLACE>; +- clock-names = "bus", "mod", "ram"; +- resets = <&ccu RST_BUS_DEINTERLACE>; +- interrupts = ; +- interconnects = <&mbus 9>; +- interconnect-names = "dma-mem"; +- }; +- +- syscon: system-control@1c00000 { +- compatible = "allwinner,sun8i-h3-system-control"; +- reg = <0x01c00000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- sram_c: sram@1d00000 { +- compatible = "mmio-sram"; +- reg = <0x01d00000 0x80000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x01d00000 0x80000>; +- +- ve_sram: sram-section@0 { +- compatible = "allwinner,sun8i-h3-sram-c1", +- "allwinner,sun4i-a10-sram-c1"; +- reg = <0x000000 0x80000>; +- }; +- }; +- }; +- +- video-codec@1c0e000 { +- compatible = "allwinner,sun8i-h3-video-engine"; +- reg = <0x01c0e000 0x1000>; +- clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, +- <&ccu CLK_DRAM_VE>; +- clock-names = "ahb", "mod", "ram"; +- resets = <&ccu RST_BUS_VE>; +- interrupts = ; +- allwinner,sram = <&ve_sram 1>; +- }; +- +- crypto: crypto@1c15000 { +- compatible = "allwinner,sun8i-h3-crypto"; +- reg = <0x01c15000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; +- clock-names = "bus", "mod"; +- resets = <&ccu RST_BUS_CE>; +- }; +- +- mali: gpu@1c40000 { +- compatible = "allwinner,sun8i-h3-mali", "arm,mali-400"; +- reg = <0x01c40000 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "gp", +- "gpmmu", +- "pp0", +- "ppmmu0", +- "pp1", +- "ppmmu1", +- "pmu"; +- clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; +- clock-names = "bus", "core"; +- resets = <&ccu RST_BUS_GPU>; +- operating-points-v2 = <&gpu_opp_table>; +- }; +- +- ths: thermal-sensor@1c25000 { +- compatible = "allwinner,sun8i-h3-ths"; +- reg = <0x01c25000 0x400>; +- interrupts = ; +- resets = <&ccu RST_BUS_THS>; +- clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; +- clock-names = "bus", "mod"; +- nvmem-cells = <&ths_calibration>; +- nvmem-cell-names = "calibration"; +- #thermal-sensor-cells = <0>; +- }; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&ths 0>; +- +- trips { +- cpu_hot_trip: cpu-hot { +- temperature = <80000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_very_hot_trip: cpu-very-hot { +- temperature = <100000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- cpu-hot-limit { +- trip = <&cpu_hot_trip>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +-}; +- +-&ccu { +- compatible = "allwinner,sun8i-h3-ccu"; +-}; +- +-&display_clocks { +- compatible = "allwinner,sun8i-h3-de2-clk"; +-}; +- +-&mmc0 { +- compatible = "allwinner,sun7i-a20-mmc"; +- clocks = <&ccu CLK_BUS_MMC0>, +- <&ccu CLK_MMC0>, +- <&ccu CLK_MMC0_OUTPUT>, +- <&ccu CLK_MMC0_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +-}; +- +-&mmc1 { +- compatible = "allwinner,sun7i-a20-mmc"; +- clocks = <&ccu CLK_BUS_MMC1>, +- <&ccu CLK_MMC1>, +- <&ccu CLK_MMC1_OUTPUT>, +- <&ccu CLK_MMC1_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +-}; +- +-&mmc2 { +- compatible = "allwinner,sun7i-a20-mmc"; +- clocks = <&ccu CLK_BUS_MMC2>, +- <&ccu CLK_MMC2>, +- <&ccu CLK_MMC2_OUTPUT>, +- <&ccu CLK_MMC2_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +-}; +- +-&pio { +- compatible = "allwinner,sun8i-h3-pinctrl"; +-}; +- +-&rtc { +- compatible = "allwinner,sun8i-h3-rtc"; +-}; +- +-&sid { +- compatible = "allwinner,sun8i-h3-sid"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-q8-common.dtsi b/scripts/dtc/include-prefixes/arm/sun8i-q8-common.dtsi +deleted file mode 100644 +index 3d9a1524e17e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-q8-common.dtsi ++++ /dev/null +@@ -1,118 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-#include "sunxi-reference-design-tablet.dtsi" +-#include "sun8i-reference-design-tablet.dtsi" +- +-/ { +- aliases { +- serial0 = &r_uart; +- /* Make u-boot set mac-address for wifi without an eeprom */ +- ethernet0 = &sdio_wifi; +- }; +- +- panel: panel { +- /* Tablet dts should provide panel compatible */ +- backlight = <&backlight>; +- enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ +- power-supply = <®_dc1sw>; +- +- port { +- panel_input: endpoint { +- remote-endpoint = <&tcon0_out_lcd>; +- }; +- }; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- /* +- * Q8 boards use various PL# pins as wifi-en. On other boards +- * these may be connected to a wifi module output pin. To avoid +- * short-circuits we configure these as inputs with pull-ups via +- * pinctrl, instead of listing them as active-low reset-gpios. +- */ +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_pwrseq_pin_q8>; +- /* The esp8089 needs 200 ms after driving wifi-en high */ +- post-power-on-delay-ms = <200>; +- }; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pg_pins>; +- vmmc-supply = <®_dldo1>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- sdio_wifi: sdio_wifi@1 { +- reg = <1>; +- }; +-}; +- +-&r_pio { +- wifi_pwrseq_pin_q8: wifi-pwrseq-pins { +- pins = "PL6", "PL7", "PL11"; +- function = "gpio_in"; +- bias-pull-up; +- }; +-}; +- +-&tcon0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_rgb666_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_dldo1>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-r16-bananapi-m2m.dts b/scripts/dtc/include-prefixes/arm/sun8i-r16-bananapi-m2m.dts +deleted file mode 100644 +index bf5b5e2f6168..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-r16-bananapi-m2m.dts ++++ /dev/null +@@ -1,311 +0,0 @@ +-/* +- * Copyright (c) 2017 Free Electrons +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a33.dtsi" +- +-#include +- +-/ { +- model = "BananaPi M2 Magic"; +- compatible = "sinovoip,bananapi-m2m", "allwinner,sun8i-a33"; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "bpi-m2m:blue:usr"; +- gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; +- }; +- +- led-1 { +- label = "bpi-m2m:green:usr"; +- gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; +- }; +- +- led-2 { +- label = "bpi-m2m:red:power"; +- gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- }; +- +- reg_vcc5v0: vcc5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ +- clocks = <&rtc 1>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc3>; +-}; +- +-&cpu0_opp_table { +- opp-1104000000 { +- opp-hz = /bits/ 64 <1104000000>; +- opp-microvolt = <1320000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <1320000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +-}; +- +-&dai { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pg_pins>; +- vmmc-supply = <®_aldo1>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_pins>; +- vmmc-supply = <®_dcdc1>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp22x: pmic@3a3 { +- compatible = "x-powers,axp223"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- eldoin-supply = <®_dcdc1>; +- x-powers,drive-vbus-en; +- }; +-}; +- +-#include "axp223.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-®_aldo1 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-io"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-name = "vdd-dll"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_dc1sw { +- regulator-name = "vcc-lcd"; +-}; +- +-®_dc5ldo { +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-3v0"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-/* +- * Our WiFi chip needs both DLDO1 and DLDO2 to be powered at the same +- * time, with the two being in sync. Since this is not really +- * supported right now, just use the two as always on, and we will fix +- * it later. +- */ +-®_dldo1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi0"; +-}; +- +-®_dldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi1"; +-}; +- +-®_drivevbus { +- regulator-name = "usb0-vbus"; +- status = "okay"; +-}; +- +-®_rtc_ldo { +- regulator-name = "vcc-rtc"; +-}; +- +-&sound { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pg_pins>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&rtc 1>; +- clock-names = "lpo"; +- vbat-supply = <®_dldo1>; +- vddio-supply = <®_aldo3>; +- device-wakeup-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ +- host-wakeup-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ +- shutdown-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ +- }; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_drivevbus>; +- usb1_vbus-supply = <®_vcc5v0>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-r16-nintendo-nes-classic.dts b/scripts/dtc/include-prefixes/arm/sun8i-r16-nintendo-nes-classic.dts +deleted file mode 100644 +index 246dec5846a4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-r16-nintendo-nes-classic.dts ++++ /dev/null +@@ -1,54 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* Copyright (c) 2016 FUKAUMI Naoki */ +- +-/dts-v1/; +-#include "sun8i-a33.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-/ { +- model = "Nintendo NES Classic Edition"; +- compatible = "nintendo,nes-classic", "allwinner,sun8i-r16", +- "allwinner,sun8i-a33"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&uart0 { +- /* +- * UART0 is available on two ports: PB and PF, both are accessible. +- * PF can also be used for the SD card so PB is preferred. +- */ +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pf_pins>; +- status = "okay"; +-}; +- +-&nfc { +- status = "okay"; +- +- /* 2Gb Macronix MX30LF2G18AC (3V) */ +- nand@0 { +- reg = <0>; +- allwinner,rb = <0>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <16>; +- nand-ecc-step-size = <1024>; +- }; +-}; +- +-&usb_otg { +- status = "okay"; +- dr_mode = "otg"; +-}; +- +-&usbphy { +- /* VBUS is always on because it is wired to the power supply */ +- usb1_vbus-supply = <®_vcc5v0>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-r16-nintendo-super-nes-classic.dts b/scripts/dtc/include-prefixes/arm/sun8i-r16-nintendo-super-nes-classic.dts +deleted file mode 100644 +index 80761d7904ec..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-r16-nintendo-super-nes-classic.dts ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* Copyright (c) 2018 Miquèl RAYNAL */ +- +-/dts-v1/; +-#include "sun8i-r16-nintendo-nes-classic.dts" +- +-/ { +- model = "Nintendo SuperNES Classic Edition"; +- compatible = "nintendo,super-nes-classic", "nintendo,nes-classic", +- "allwinner,sun8i-r16", "allwinner,sun8i-a33"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-r16-parrot.dts b/scripts/dtc/include-prefixes/arm/sun8i-r16-parrot.dts +deleted file mode 100644 +index 95543a9c2118..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-r16-parrot.dts ++++ /dev/null +@@ -1,313 +0,0 @@ +-/* +- * Copyright 2016 Quentin Schulz +- * +- * Quentin Schulz +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-a33.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- model = "Allwinner R16 EVB (Parrot)"; +- compatible = "allwinner,parrot", "allwinner,sun8i-a33"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-1 { +- label = "parrot:led1:usr"; +- gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ +- }; +- +- led-2 { +- label = "parrot:led2:usr"; +- gpios = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */ +- }; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ +- }; +- +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&dai { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- +- /* +- * FIXME: An as-yet-unknown accelerometer is connected to this +- * i2c bus. +- */ +-}; +- +-&lradc { +- vref-supply = <®_aldo3>; +- status = "okay"; +- +- button-190 { +- label = "V+"; +- linux,code = ; +- channel = <0>; +- voltage = <190000>; +- }; +- +- button-390 { +- label = "V-"; +- linux,code = ; +- channel = <0>; +- voltage = <390000>; +- }; +- +-}; +- +-&mmc0 { +- vmmc-supply = <®_dcdc1>; +- cd-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ +- bus-width = <4>; +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pg_pins>; +- vmmc-supply = <®_aldo1>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_pins>; +- vmmc-supply = <®_dcdc1>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&mmc2_8bit_pins { +- drive-strength = <40>; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp22x: pmic@3a3 { +- compatible = "x-powers,axp223"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- drivevbus-supply = <®_vcc5v0>; +- x-powers,drive-vbus-en; +- }; +-}; +- +-#include "axp223.dtsi" +- +-®_aldo1 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-io"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <2350000>; +- regulator-max-microvolt = <2650000>; +- regulator-name = "vdd-dll"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pll-avcc"; +-}; +- +-®_dc5ldo { +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-3v0"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dldo1 { +- /* +- * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered. +- * Remove next line once it is possible to sync two regulators. +- */ +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi0"; +-}; +- +-®_dldo2 { +- /* +- * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered. +- * Remove next line once it is possible to sync two regulators. +- */ +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi1"; +-}; +- +-®_dldo3 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-3v0-csi"; +-}; +- +-®_drivevbus { +- regulator-name = "usb0-vbus"; +- status = "okay"; +-}; +- +-®_eldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-1v2-hsic"; +-}; +- +-®_eldo2 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-dsp"; +-}; +- +-®_eldo3 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "eldo3"; +-}; +- +-®_usb1_vbus { +- gpio = <&pio 3 12 GPIO_ACTIVE_HIGH>; /* PD12 */ +- status = "okay"; +-}; +- +-&sound { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +- usb0_vbus-supply = <®_drivevbus>; +- usb0_id_det-gpios = <&pio 3 10 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PD10 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb1_vbus-supply = <®_usb1_vbus>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-r40-bananapi-m2-ultra.dts b/scripts/dtc/include-prefixes/arm/sun8i-r40-bananapi-m2-ultra.dts +deleted file mode 100644 +index a6a1087a0c9b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-r40-bananapi-m2-ultra.dts ++++ /dev/null +@@ -1,335 +0,0 @@ +-/* +- * Copyright (C) 2017 Chen-Yu Tsai +- * Copyright (C) 2017 Icenowy Zheng +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-r40.dtsi" +- +-#include +- +-/ { +- model = "Banana Pi BPI-M2-Ultra"; +- compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40"; +- +- aliases { +- ethernet0 = &gmac; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pwr-led { +- label = "bananapi:red:pwr"; +- gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- user-led-green { +- label = "bananapi:green:user"; +- gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; +- }; +- +- user-led-blue { +- label = "bananapi:blue:user"; +- gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- reg_vcc5v0: vcc5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ +- enable-active-high; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ +- clocks = <&ccu CLK_OUTA>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&ahci { +- ahci-supply = <®_dldo4>; +- phy-supply = <®_eldo3>; +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii-id"; +- phy-supply = <®_dc1sw>; +- status = "okay"; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp22x: pmic@34 { +- compatible = "x-powers,axp221"; +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-#include "axp22x.dtsi" +- +-&ir0 { +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */ +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pg_pins>; +- vmmc-supply = <®_dldo2>; +- vqmmc-supply = <®_dldo1>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&mmc2 { +- vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_dcdc1>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-&pio { +- pinctrl-names = "default"; +- pinctrl-0 = <&clk_out_a_pin>; +- vcc-pa-supply = <®_aldo2>; +- vcc-pc-supply = <®_dcdc1>; +- vcc-pd-supply = <®_dcdc1>; +- vcc-pe-supply = <®_eldo1>; +- vcc-pf-supply = <®_dcdc1>; +- vcc-pg-supply = <®_dldo1>; +-}; +- +-®_aldo2 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-name = "vcc-pa"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "avcc"; +-}; +- +-®_dc1sw { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-gmac-phy"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-io"; +-}; +- +-/* +- * Our WiFi chip needs both DLDO2 and DLDO3 to be powered at the same +- * time, with the two being in sync, to be able to meet maximum power +- * consumption during transmits. Since this is not really supported +- * right now, just use the two as always on, and we will fix it later. +- */ +- +-®_dldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-®_dldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-2"; +-}; +- +-®_dldo4 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-name = "vdd2v5-sata"; +-}; +- +-®_eldo3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vdd1v2-sata"; +-}; +- +-&tcon_tv0 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&ccu CLK_OUTA>; +- clock-names = "lpo"; +- vbat-supply = <®_dldo2>; +- vddio-supply = <®_dldo1>; +- device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ +- /* TODO host wake line connected to PMIC GPIO pins */ +- shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ +- max-speed = <1500000>; +- }; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_vcc5v0>; +- usb2_vbus-supply = <®_vcc5v0>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-r40-feta40i.dtsi b/scripts/dtc/include-prefixes/arm/sun8i-r40-feta40i.dtsi +deleted file mode 100644 +index 265e0fa57a32..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-r40-feta40i.dtsi ++++ /dev/null +@@ -1,106 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// Copyright (C) 2021 Ivan Uvarov +-// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is: +-// Copyright (C) 2017 Chen-Yu Tsai +-// Copyright (C) 2017 Icenowy Zheng +- +-#include "sun8i-r40.dtsi" +- +-&i2c0 { +- status = "okay"; +- +- axp22x: pmic@34 { +- compatible = "x-powers,axp221"; +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-#include "axp22x.dtsi" +- +-&mmc2 { +- vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_aldo2>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&pio { +- pinctrl-names = "default"; +- pinctrl-0 = <&clk_out_a_pin>; +- vcc-pa-supply = <®_dcdc1>; +- vcc-pc-supply = <®_aldo2>; +- vcc-pd-supply = <®_dcdc1>; +- vcc-pf-supply = <®_dldo4>; +- vcc-pg-supply = <®_dldo1>; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-pa"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dldo1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-io"; +-}; +- +-®_dldo4 { +- regulator-always-on; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-name = "vdd2v5-sata"; +-}; +- +-®_eldo2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vdd1v2-sata"; +-}; +- +-®_eldo3 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "vcc-pe"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-r40-oka40i-c.dts b/scripts/dtc/include-prefixes/arm/sun8i-r40-oka40i-c.dts +deleted file mode 100644 +index 0bd1336206b8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-r40-oka40i-c.dts ++++ /dev/null +@@ -1,203 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// Copyright (C) 2021 Ivan Uvarov +-// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is: +-// Copyright (C) 2017 Chen-Yu Tsai +-// Copyright (C) 2017 Icenowy Zheng +- +-/dts-v1/; +-#include "sun8i-r40-feta40i.dtsi" +- +-#include +-#include +- +-/ { +- model = "Forlinx OKA40i-C"; +- compatible = "forlinx,oka40i-c", "forlinx,feta40i-c", "allwinner,sun8i-r40"; +- +- aliases { +- ethernet0 = &gmac; +- serial0 = &uart0; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- serial5 = &uart5; /* RS485 */ +- serial7 = &uart7; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-5 { /* this is how the leds are labeled on the board */ +- gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */ +- color = ; +- function = LED_FUNCTION_STATUS; +- }; +- +- led-6 { +- gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */ +- color = ; +- function = LED_FUNCTION_STATUS; +- }; +- }; +- +- reg_vcc5v0: vcc5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; // PB10 WIFI_EN +- clocks = <&ccu CLK_OUTA>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&ahci { +- ahci-supply = <®_dldo4>; +- phy-supply = <®_eldo2>; +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii-id"; +- phy-supply = <®_dcdc1>; +- status = "okay"; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 8 11 GPIO_ACTIVE_LOW>; // PI11 +- status = "okay"; +-}; +- +-&mmc3 { +- vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 8 10 GPIO_ACTIVE_LOW>; // PI10 +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-®_dc1sw { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-lcd"; +-}; +- +-®_dldo2 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-&tcon_tv0 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pi_pins>, <&uart2_rts_cts_pi_pins>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pg_pins>; +- status = "okay"; +-}; +- +-&uart5 { /* RS485 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&uart5_ph_pins>; +- status = "okay"; +-}; +- +-&uart7 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart7_pi_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_vcc5v0>; +- usb2_vbus-supply = <®_vcc5v0>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-r40.dtsi b/scripts/dtc/include-prefixes/arm/sun8i-r40.dtsi +deleted file mode 100644 +index 291f4784e86c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-r40.dtsi ++++ /dev/null +@@ -1,1230 +0,0 @@ +-/* +- * Copyright 2017 Chen-Yu Tsai +- * Copyright 2017 Icenowy Zheng +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&gic>; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- osc24M: osc24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-accuracy = <50000>; +- clock-output-names = "osc24M"; +- }; +- +- osc32k: osc32k { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-accuracy = <20000>; +- clock-output-names = "ext-osc32k"; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <0>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <1>; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <2>; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <3>; +- }; +- }; +- +- de: display-engine { +- compatible = "allwinner,sun8i-r40-display-engine"; +- allwinner,pipelines = <&mixer0>, <&mixer1>; +- status = "disabled"; +- }; +- +- thermal-zones { +- cpu_thermal: cpu0-thermal { +- /* milliseconds */ +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&ths 0>; +- }; +- +- gpu_thermal: gpu-thermal { +- /* milliseconds */ +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&ths 1>; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- display_clocks: clock@1000000 { +- compatible = "allwinner,sun8i-r40-de2-clk", +- "allwinner,sun8i-h3-de2-clk"; +- reg = <0x01000000 0x10000>; +- clocks = <&ccu CLK_BUS_DE>, +- <&ccu CLK_DE>; +- clock-names = "bus", +- "mod"; +- resets = <&ccu RST_BUS_DE>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- mixer0: mixer@1100000 { +- compatible = "allwinner,sun8i-r40-de2-mixer-0"; +- reg = <0x01100000 0x100000>; +- clocks = <&display_clocks CLK_BUS_MIXER0>, +- <&display_clocks CLK_MIXER0>; +- clock-names = "bus", +- "mod"; +- resets = <&display_clocks RST_MIXER0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mixer0_out: port@1 { +- reg = <1>; +- mixer0_out_tcon_top: endpoint { +- remote-endpoint = <&tcon_top_mixer0_in_mixer0>; +- }; +- }; +- }; +- }; +- +- mixer1: mixer@1200000 { +- compatible = "allwinner,sun8i-r40-de2-mixer-1"; +- reg = <0x01200000 0x100000>; +- clocks = <&display_clocks CLK_BUS_MIXER1>, +- <&display_clocks CLK_MIXER1>; +- clock-names = "bus", +- "mod"; +- resets = <&display_clocks RST_WB>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mixer1_out: port@1 { +- reg = <1>; +- mixer1_out_tcon_top: endpoint { +- remote-endpoint = <&tcon_top_mixer1_in_mixer1>; +- }; +- }; +- }; +- }; +- +- deinterlace: deinterlace@1400000 { +- compatible = "allwinner,sun8i-r40-deinterlace", +- "allwinner,sun8i-h3-deinterlace"; +- reg = <0x01400000 0x20000>; +- clocks = <&ccu CLK_BUS_DEINTERLACE>, +- <&ccu CLK_DEINTERLACE>, +- /* +- * NOTE: Contrary to what datasheet claims, +- * DRAM deinterlace gate doesn't exist and +- * it's shared with CSI1. +- */ +- <&ccu CLK_DRAM_CSI1>; +- clock-names = "bus", "mod", "ram"; +- resets = <&ccu RST_BUS_DEINTERLACE>; +- interrupts = ; +- interconnects = <&mbus 9>; +- interconnect-names = "dma-mem"; +- }; +- +- syscon: system-control@1c00000 { +- compatible = "allwinner,sun8i-r40-system-control", +- "allwinner,sun4i-a10-system-control"; +- reg = <0x01c00000 0x30>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- sram_c: sram@1d00000 { +- compatible = "mmio-sram"; +- reg = <0x01d00000 0xd0000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x01d00000 0xd0000>; +- +- ve_sram: sram-section@0 { +- compatible = "allwinner,sun8i-r40-sram-c1", +- "allwinner,sun4i-a10-sram-c1"; +- reg = <0x000000 0x80000>; +- }; +- }; +- }; +- +- nmi_intc: interrupt-controller@1c00030 { +- compatible = "allwinner,sun7i-a20-sc-nmi"; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x01c00030 0x0c>; +- interrupts = ; +- }; +- +- dma: dma-controller@1c02000 { +- compatible = "allwinner,sun8i-r40-dma", +- "allwinner,sun50i-a64-dma"; +- reg = <0x01c02000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_DMA>; +- dma-channels = <16>; +- dma-requests = <31>; +- resets = <&ccu RST_BUS_DMA>; +- #dma-cells = <1>; +- }; +- +- spi0: spi@1c05000 { +- compatible = "allwinner,sun8i-r40-spi", +- "allwinner,sun8i-h3-spi"; +- reg = <0x01c05000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; +- clock-names = "ahb", "mod"; +- resets = <&ccu RST_BUS_SPI0>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spi1: spi@1c06000 { +- compatible = "allwinner,sun8i-r40-spi", +- "allwinner,sun8i-h3-spi"; +- reg = <0x01c06000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; +- clock-names = "ahb", "mod"; +- resets = <&ccu RST_BUS_SPI1>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- csi0: csi@1c09000 { +- compatible = "allwinner,sun8i-r40-csi0", +- "allwinner,sun7i-a20-csi0"; +- reg = <0x01c09000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>, +- <&ccu CLK_DRAM_CSI0>; +- clock-names = "bus", "isp", "ram"; +- resets = <&ccu RST_BUS_CSI0>; +- interconnects = <&mbus 5>; +- interconnect-names = "dma-mem"; +- status = "disabled"; +- }; +- +- video-codec@1c0e000 { +- compatible = "allwinner,sun8i-r40-video-engine"; +- reg = <0x01c0e000 0x1000>; +- clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, +- <&ccu CLK_DRAM_VE>; +- clock-names = "ahb", "mod", "ram"; +- resets = <&ccu RST_BUS_VE>; +- interrupts = ; +- allwinner,sram = <&ve_sram 1>; +- }; +- +- mmc0: mmc@1c0f000 { +- compatible = "allwinner,sun8i-r40-mmc", +- "allwinner,sun50i-a64-mmc"; +- reg = <0x01c0f000 0x1000>; +- clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; +- clock-names = "ahb", "mmc"; +- resets = <&ccu RST_BUS_MMC0>; +- reset-names = "ahb"; +- pinctrl-0 = <&mmc0_pins>; +- pinctrl-names = "default"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc1: mmc@1c10000 { +- compatible = "allwinner,sun8i-r40-mmc", +- "allwinner,sun50i-a64-mmc"; +- reg = <0x01c10000 0x1000>; +- clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; +- clock-names = "ahb", "mmc"; +- resets = <&ccu RST_BUS_MMC1>; +- reset-names = "ahb"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc2: mmc@1c11000 { +- compatible = "allwinner,sun8i-r40-emmc", +- "allwinner,sun50i-a64-emmc"; +- reg = <0x01c11000 0x1000>; +- clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; +- clock-names = "ahb", "mmc"; +- resets = <&ccu RST_BUS_MMC2>; +- reset-names = "ahb"; +- pinctrl-0 = <&mmc2_pins>; +- pinctrl-names = "default"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc3: mmc@1c12000 { +- compatible = "allwinner,sun8i-r40-mmc", +- "allwinner,sun50i-a64-mmc"; +- reg = <0x01c12000 0x1000>; +- clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>; +- clock-names = "ahb", "mmc"; +- resets = <&ccu RST_BUS_MMC3>; +- reset-names = "ahb"; +- pinctrl-0 = <&mmc3_pins>; +- pinctrl-names = "default"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- usbphy: phy@1c13400 { +- compatible = "allwinner,sun8i-r40-usb-phy"; +- reg = <0x01c13400 0x14>, +- <0x01c14800 0x4>, +- <0x01c19800 0x4>, +- <0x01c1c800 0x4>; +- reg-names = "phy_ctrl", +- "pmu0", +- "pmu1", +- "pmu2"; +- clocks = <&ccu CLK_USB_PHY0>, +- <&ccu CLK_USB_PHY1>, +- <&ccu CLK_USB_PHY2>; +- clock-names = "usb0_phy", +- "usb1_phy", +- "usb2_phy"; +- resets = <&ccu RST_USB_PHY0>, +- <&ccu RST_USB_PHY1>, +- <&ccu RST_USB_PHY2>; +- reset-names = "usb0_reset", +- "usb1_reset", +- "usb2_reset"; +- status = "disabled"; +- #phy-cells = <1>; +- }; +- +- crypto: crypto@1c15000 { +- compatible = "allwinner,sun8i-r40-crypto"; +- reg = <0x01c15000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; +- clock-names = "bus", "mod"; +- resets = <&ccu RST_BUS_CE>; +- }; +- +- spi2: spi@1c17000 { +- compatible = "allwinner,sun8i-r40-spi", +- "allwinner,sun8i-h3-spi"; +- reg = <0x01c17000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; +- clock-names = "ahb", "mod"; +- resets = <&ccu RST_BUS_SPI2>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- ahci: sata@1c18000 { +- compatible = "allwinner,sun8i-r40-ahci"; +- reg = <0x01c18000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; +- resets = <&ccu RST_BUS_SATA>; +- reset-names = "ahci"; +- status = "disabled"; +- }; +- +- ehci1: usb@1c19000 { +- compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; +- reg = <0x01c19000 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_EHCI1>; +- resets = <&ccu RST_BUS_EHCI1>; +- phys = <&usbphy 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci1: usb@1c19400 { +- compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; +- reg = <0x01c19400 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_OHCI1>, +- <&ccu CLK_USB_OHCI1>; +- resets = <&ccu RST_BUS_OHCI1>; +- phys = <&usbphy 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ehci2: usb@1c1c000 { +- compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; +- reg = <0x01c1c000 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_EHCI2>; +- resets = <&ccu RST_BUS_EHCI2>; +- phys = <&usbphy 2>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci2: usb@1c1c400 { +- compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; +- reg = <0x01c1c400 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_OHCI2>, +- <&ccu CLK_USB_OHCI2>; +- resets = <&ccu RST_BUS_OHCI2>; +- phys = <&usbphy 2>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- spi3: spi@1c1f000 { +- compatible = "allwinner,sun8i-r40-spi", +- "allwinner,sun8i-h3-spi"; +- reg = <0x01c1f000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; +- clock-names = "ahb", "mod"; +- resets = <&ccu RST_BUS_SPI3>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- ccu: clock@1c20000 { +- compatible = "allwinner,sun8i-r40-ccu"; +- reg = <0x01c20000 0x400>; +- clocks = <&osc24M>, <&rtc 0>; +- clock-names = "hosc", "losc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- rtc: rtc@1c20400 { +- compatible = "allwinner,sun8i-r40-rtc"; +- reg = <0x01c20400 0x400>; +- interrupts = ; +- clock-output-names = "osc32k", "osc32k-out"; +- clocks = <&osc32k>; +- #clock-cells = <1>; +- }; +- +- pio: pinctrl@1c20800 { +- compatible = "allwinner,sun8i-r40-pinctrl"; +- reg = <0x01c20800 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; +- clock-names = "apb", "hosc", "losc"; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <3>; +- #gpio-cells = <3>; +- +- clk_out_a_pin: clk-out-a-pin { +- pins = "PI12"; +- function = "clk_out_a"; +- }; +- +- /omit-if-no-ref/ +- csi0_8bits_pins: csi0-8bits-pins { +- pins = "PE0", "PE2", "PE3", "PE4", "PE5", +- "PE6", "PE7", "PE8", "PE9", "PE10", +- "PE11"; +- function = "csi0"; +- }; +- +- /omit-if-no-ref/ +- csi0_mclk_pin: csi0-mclk-pin { +- pins = "PE1"; +- function = "csi0"; +- }; +- +- gmac_rgmii_pins: gmac-rgmii-pins { +- pins = "PA0", "PA1", "PA2", "PA3", +- "PA4", "PA5", "PA6", "PA7", +- "PA8", "PA10", "PA11", "PA12", +- "PA13", "PA15", "PA16"; +- function = "gmac"; +- /* +- * data lines in RGMII mode use DDR mode +- * and need a higher signal drive strength +- */ +- drive-strength = <40>; +- }; +- +- i2c0_pins: i2c0-pins { +- pins = "PB0", "PB1"; +- function = "i2c0"; +- }; +- +- i2c1_pins: i2c1-pins { +- pins = "PB18", "PB19"; +- function = "i2c1"; +- }; +- +- i2c2_pins: i2c2-pins { +- pins = "PB20", "PB21"; +- function = "i2c2"; +- }; +- +- i2c3_pins: i2c3-pins { +- pins = "PI0", "PI1"; +- function = "i2c3"; +- }; +- +- i2c4_pins: i2c4-pins { +- pins = "PI2", "PI3"; +- function = "i2c4"; +- }; +- +- ir0_pins: ir0-pins { +- pins = "PB4"; +- function = "ir0"; +- }; +- +- ir1_pins: ir1-pins { +- pins = "PB23"; +- function = "ir1"; +- }; +- +- mmc0_pins: mmc0-pins { +- pins = "PF0", "PF1", "PF2", +- "PF3", "PF4", "PF5"; +- function = "mmc0"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc1_pg_pins: mmc1-pg-pins { +- pins = "PG0", "PG1", "PG2", +- "PG3", "PG4", "PG5"; +- function = "mmc1"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc2_pins: mmc2-pins { +- pins = "PC5", "PC6", "PC7", "PC8", "PC9", +- "PC10", "PC11", "PC12", "PC13", "PC14", +- "PC15", "PC24"; +- function = "mmc2"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- /omit-if-no-ref/ +- mmc3_pins: mmc3-pins { +- pins = "PI4", "PI5", "PI6", +- "PI7", "PI8", "PI9"; +- function = "mmc3"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- /omit-if-no-ref/ +- spi0_pc_pins: spi0-pc-pins { +- pins = "PC0", "PC1", "PC2"; +- function = "spi0"; +- }; +- +- /omit-if-no-ref/ +- spi0_cs0_pc_pin: spi0-cs0-pc-pin { +- pins = "PC23"; +- function = "spi0"; +- }; +- +- /omit-if-no-ref/ +- spi1_pi_pins: spi1-pi-pins { +- pins = "PI17", "PI18", "PI19"; +- function = "spi1"; +- }; +- +- /omit-if-no-ref/ +- spi1_cs0_pi_pin: spi1-cs0-pi-pin { +- pins = "PI16"; +- function = "spi1"; +- }; +- +- /omit-if-no-ref/ +- spi1_cs1_pi_pin: spi1-cs1-pi-pin { +- pins = "PI15"; +- function = "spi1"; +- }; +- +- /omit-if-no-ref/ +- uart0_pb_pins: uart0-pb-pins { +- pins = "PB22", "PB23"; +- function = "uart0"; +- }; +- +- /omit-if-no-ref/ +- uart2_pi_pins: uart2-pi-pins { +- pins = "PI18", "PI19"; +- function = "uart2"; +- }; +- +- /omit-if-no-ref/ +- uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{ +- pins = "PI16", "PI17"; +- function = "uart2"; +- }; +- +- /omit-if-no-ref/ +- uart3_pg_pins: uart3-pg-pins { +- pins = "PG6", "PG7"; +- function = "uart3"; +- }; +- +- /omit-if-no-ref/ +- uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins { +- pins = "PG8", "PG9"; +- function = "uart3"; +- }; +- +- /omit-if-no-ref/ +- uart4_pg_pins: uart4-pg-pins { +- pins = "PG10", "PG11"; +- function = "uart4"; +- }; +- +- /omit-if-no-ref/ +- uart5_ph_pins: uart5-ph-pins { +- pins = "PH6", "PH7"; +- function = "uart5"; +- }; +- +- /omit-if-no-ref/ +- uart7_pi_pins: uart7-pi-pins { +- pins = "PI20", "PI21"; +- function = "uart7"; +- }; +- }; +- +- timer@1c20c00 { +- compatible = "allwinner,sun4i-a10-timer"; +- reg = <0x01c20c00 0x90>; +- interrupts = , +- , +- , +- , +- , +- ; +- clocks = <&osc24M>; +- }; +- +- wdt: watchdog@1c20c90 { +- compatible = "allwinner,sun4i-a10-wdt"; +- reg = <0x01c20c90 0x10>; +- interrupts = ; +- clocks = <&osc24M>; +- }; +- +- ir0: ir@1c21800 { +- compatible = "allwinner,sun8i-r40-ir", +- "allwinner,sun6i-a31-ir"; +- reg = <0x01c21800 0x400>; +- pinctrl-0 = <&ir0_pins>; +- pinctrl-names = "default"; +- clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>; +- clock-names = "apb", "ir"; +- interrupts = ; +- resets = <&ccu RST_BUS_IR0>; +- status = "disabled"; +- }; +- +- ir1: ir@1c21c00 { +- compatible = "allwinner,sun8i-r40-ir", +- "allwinner,sun6i-a31-ir"; +- reg = <0x01c21c00 0x400>; +- pinctrl-0 = <&ir1_pins>; +- pinctrl-names = "default"; +- clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>; +- clock-names = "apb", "ir"; +- interrupts = ; +- resets = <&ccu RST_BUS_IR1>; +- status = "disabled"; +- }; +- +- ths: thermal-sensor@1c24c00 { +- compatible = "allwinner,sun8i-r40-ths"; +- reg = <0x01c24c00 0x100>; +- clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; +- clock-names = "bus", "mod"; +- interrupts = ; +- resets = <&ccu RST_BUS_THS>; +- /* TODO: add nvmem-cells for calibration */ +- #thermal-sensor-cells = <1>; +- }; +- +- uart0: serial@1c28000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART0>; +- resets = <&ccu RST_BUS_UART0>; +- status = "disabled"; +- }; +- +- uart1: serial@1c28400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28400 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART1>; +- resets = <&ccu RST_BUS_UART1>; +- status = "disabled"; +- }; +- +- uart2: serial@1c28800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28800 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART2>; +- resets = <&ccu RST_BUS_UART2>; +- status = "disabled"; +- }; +- +- uart3: serial@1c28c00 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28c00 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART3>; +- resets = <&ccu RST_BUS_UART3>; +- status = "disabled"; +- }; +- +- uart4: serial@1c29000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c29000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART4>; +- resets = <&ccu RST_BUS_UART4>; +- status = "disabled"; +- }; +- +- uart5: serial@1c29400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c29400 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART5>; +- resets = <&ccu RST_BUS_UART5>; +- status = "disabled"; +- }; +- +- uart6: serial@1c29800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c29800 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART6>; +- resets = <&ccu RST_BUS_UART6>; +- status = "disabled"; +- }; +- +- uart7: serial@1c29c00 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c29c00 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART7>; +- resets = <&ccu RST_BUS_UART7>; +- status = "disabled"; +- }; +- +- i2c0: i2c@1c2ac00 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2ac00 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C0>; +- resets = <&ccu RST_BUS_I2C0>; +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c1: i2c@1c2b000 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2b000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C1>; +- resets = <&ccu RST_BUS_I2C1>; +- pinctrl-0 = <&i2c1_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c2: i2c@1c2b400 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2b400 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C2>; +- resets = <&ccu RST_BUS_I2C2>; +- pinctrl-0 = <&i2c2_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c3: i2c@1c2b800 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2b800 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C3>; +- resets = <&ccu RST_BUS_I2C3>; +- pinctrl-0 = <&i2c3_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c4: i2c@1c2c000 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2c000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C4>; +- resets = <&ccu RST_BUS_I2C4>; +- pinctrl-0 = <&i2c4_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mali: gpu@1c40000 { +- compatible = "allwinner,sun8i-r40-mali", "arm,mali-400"; +- reg = <0x01c40000 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "gp", +- "gpmmu", +- "pp0", +- "ppmmu0", +- "pp1", +- "ppmmu1", +- "pmu"; +- clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; +- clock-names = "bus", "core"; +- resets = <&ccu RST_BUS_GPU>; +- }; +- +- gmac: ethernet@1c50000 { +- compatible = "allwinner,sun8i-r40-gmac"; +- syscon = <&ccu>; +- reg = <0x01c50000 0x10000>; +- interrupts = ; +- interrupt-names = "macirq"; +- resets = <&ccu RST_BUS_GMAC>; +- reset-names = "stmmaceth"; +- clocks = <&ccu CLK_BUS_GMAC>; +- clock-names = "stmmaceth"; +- status = "disabled"; +- +- gmac_mdio: mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- mbus: dram-controller@1c62000 { +- compatible = "allwinner,sun8i-r40-mbus"; +- reg = <0x01c62000 0x1000>; +- clocks = <&ccu 155>; +- #address-cells = <1>; +- #size-cells = <1>; +- dma-ranges = <0x00000000 0x40000000 0x80000000>; +- #interconnect-cells = <1>; +- }; +- +- tcon_top: tcon-top@1c70000 { +- compatible = "allwinner,sun8i-r40-tcon-top"; +- reg = <0x01c70000 0x1000>; +- clocks = <&ccu CLK_BUS_TCON_TOP>, +- <&ccu CLK_TCON_TV0>, +- <&ccu CLK_TVE0>, +- <&ccu CLK_TCON_TV1>, +- <&ccu CLK_TVE1>, +- <&ccu CLK_DSI_DPHY>; +- clock-names = "bus", +- "tcon-tv0", +- "tve0", +- "tcon-tv1", +- "tve1", +- "dsi"; +- clock-output-names = "tcon-top-tv0", +- "tcon-top-tv1", +- "tcon-top-dsi"; +- resets = <&ccu RST_BUS_TCON_TOP>; +- #clock-cells = <1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon_top_mixer0_in: port@0 { +- reg = <0>; +- +- tcon_top_mixer0_in_mixer0: endpoint { +- remote-endpoint = <&mixer0_out_tcon_top>; +- }; +- }; +- +- tcon_top_mixer0_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { +- reg = <0>; +- }; +- +- tcon_top_mixer0_out_tcon_lcd1: endpoint@1 { +- reg = <1>; +- }; +- +- tcon_top_mixer0_out_tcon_tv0: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; +- }; +- +- tcon_top_mixer0_out_tcon_tv1: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>; +- }; +- }; +- +- tcon_top_mixer1_in: port@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- tcon_top_mixer1_in_mixer1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&mixer1_out_tcon_top>; +- }; +- }; +- +- tcon_top_mixer1_out: port@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { +- reg = <0>; +- }; +- +- tcon_top_mixer1_out_tcon_lcd1: endpoint@1 { +- reg = <1>; +- }; +- +- tcon_top_mixer1_out_tcon_tv0: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; +- }; +- +- tcon_top_mixer1_out_tcon_tv1: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>; +- }; +- }; +- +- tcon_top_hdmi_in: port@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- +- tcon_top_hdmi_in_tcon_tv0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&tcon_tv0_out_tcon_top>; +- }; +- +- tcon_top_hdmi_in_tcon_tv1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tcon_tv1_out_tcon_top>; +- }; +- }; +- +- tcon_top_hdmi_out: port@5 { +- reg = <5>; +- +- tcon_top_hdmi_out_hdmi: endpoint { +- remote-endpoint = <&hdmi_in_tcon_top>; +- }; +- }; +- }; +- }; +- +- tcon_tv0: lcd-controller@1c73000 { +- compatible = "allwinner,sun8i-r40-tcon-tv"; +- reg = <0x01c73000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>; +- clock-names = "ahb", "tcon-ch1"; +- resets = <&ccu RST_BUS_TCON_TV0>; +- reset-names = "lcd"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon_tv0_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- tcon_tv0_in_tcon_top_mixer0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; +- }; +- +- tcon_tv0_in_tcon_top_mixer1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; +- }; +- }; +- +- tcon_tv0_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tcon_tv0_out_tcon_top: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; +- }; +- }; +- }; +- }; +- +- tcon_tv1: lcd-controller@1c74000 { +- compatible = "allwinner,sun8i-r40-tcon-tv"; +- reg = <0x01c74000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>; +- clock-names = "ahb", "tcon-ch1"; +- resets = <&ccu RST_BUS_TCON_TV1>; +- reset-names = "lcd"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon_tv1_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- tcon_tv1_in_tcon_top_mixer0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>; +- }; +- +- tcon_tv1_in_tcon_top_mixer1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>; +- }; +- }; +- +- tcon_tv1_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tcon_tv1_out_tcon_top: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>; +- }; +- }; +- }; +- }; +- +- gic: interrupt-controller@1c81000 { +- compatible = "arm,gic-400"; +- reg = <0x01c81000 0x1000>, +- <0x01c82000 0x2000>, +- <0x01c84000 0x2000>, +- <0x01c86000 0x2000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = ; +- }; +- +- hdmi: hdmi@1ee0000 { +- compatible = "allwinner,sun8i-r40-dw-hdmi", +- "allwinner,sun8i-a83t-dw-hdmi"; +- reg = <0x01ee0000 0x10000>; +- reg-io-width = <1>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, +- <&ccu CLK_HDMI>; +- clock-names = "iahb", "isfr", "tmds"; +- resets = <&ccu RST_BUS_HDMI1>; +- reset-names = "ctrl"; +- phys = <&hdmi_phy>; +- phy-names = "phy"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- hdmi_in: port@0 { +- reg = <0>; +- +- hdmi_in_tcon_top: endpoint { +- remote-endpoint = <&tcon_top_hdmi_out_hdmi>; +- }; +- }; +- +- hdmi_out: port@1 { +- reg = <1>; +- }; +- }; +- }; +- +- hdmi_phy: hdmi-phy@1ef0000 { +- compatible = "allwinner,sun8i-r40-hdmi-phy"; +- reg = <0x01ef0000 0x10000>; +- clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>, +- <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>; +- clock-names = "bus", "mod", "pll-0", "pll-1"; +- resets = <&ccu RST_BUS_HDMI0>; +- reset-names = "phy"; +- #phy-cells = <0>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a7-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-reference-design-tablet.dtsi b/scripts/dtc/include-prefixes/arm/sun8i-reference-design-tablet.dtsi +deleted file mode 100644 +index 872d56caa9ce..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-reference-design-tablet.dtsi ++++ /dev/null +@@ -1,224 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-#include "sunxi-reference-design-tablet.dtsi" +- +-#include +- +-/ { +- aliases { +- serial0 = &r_uart; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; +- brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; +- default-brightness-level = <8>; +- enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ +- power-supply = <®_dc1sw>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&i2c0 { +- /* +- * The gsl1680 is rated at 400KHz and it will not work reliable at +- * 100KHz, this has been confirmed on multiple different q8 tablets. +- * The gsl1680 is the only device on this bus. +- */ +- clock-frequency = <400000>; +- +- touchscreen: touchscreen@40 { +- reg = <0x40>; +- interrupt-parent = <&pio>; +- interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5 */ +- power-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ +- /* Tablet dts must provide reg and compatible */ +- status = "disabled"; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ +- status = "okay"; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp22x: pmic@3a3 { +- compatible = "x-powers,axp223"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- eldoin-supply = <®_dcdc1>; +- drivevbus-supply = <®_vcc5v0>; +- x-powers,drive-vbus-en; +- }; +-}; +- +-#include "axp223.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_aldo1 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-io"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <2350000>; +- regulator-max-microvolt = <2650000>; +- regulator-name = "vdd-dll"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pll-avcc"; +-}; +- +-®_dc1sw { +- regulator-name = "vcc-lcd"; +-}; +- +-®_dc5ldo { +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-3v0"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-®_drivevbus { +- regulator-name = "usb0-vbus"; +- status = "okay"; +-}; +- +-®_ldo_io1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-touchscreen"; +- status = "okay"; +-}; +- +-®_rtc_ldo { +- regulator-name = "vcc-rtc"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&r_uart { +- pinctrl-names = "default"; +- pinctrl-0 = <&r_uart_pins_a>; +- status = "okay"; +-}; +- +-&simplefb_lcd { +- vcc-lcd-supply = <®_dc1sw>; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH8 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_drivevbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-s3-elimo-impetus.dtsi b/scripts/dtc/include-prefixes/arm/sun8i-s3-elimo-impetus.dtsi +deleted file mode 100644 +index 052b010a5607..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-s3-elimo-impetus.dtsi ++++ /dev/null +@@ -1,44 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2020 Matteo Scordino +- */ +- +-/dts-v1/; +-#include "sun8i-v3.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-/ { +- model = "Elimo Impetus SoM"; +- compatible = "elimo,impetus", "sochip,s3", "allwinner,sun8i-v3"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&mmc0 { +- broken-cd; +- bus-width = <4>; +- vmmc-supply = <®_vcc3v3>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-0 = <&uart0_pb_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-s3-elimo-initium.dts b/scripts/dtc/include-prefixes/arm/sun8i-s3-elimo-initium.dts +deleted file mode 100644 +index 039677c2cc65..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-s3-elimo-initium.dts ++++ /dev/null +@@ -1,29 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2020 Matteo Scordino +- */ +- +-/dts-v1/; +-#include "sun8i-s3-elimo-impetus.dtsi" +- +-/ { +- model = "Elimo Initium"; +- compatible = "elimo,initium", "elimo,impetus", "sochip,s3", +- "allwinner,sun8i-v3"; +- +- aliases { +- serial1 = &uart1; +- }; +-}; +- +-&uart1 { +- pinctrl-0 = <&uart1_pg_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&int_mii_phy>; +- phy-mode = "mii"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-s3-lichee-zero-plus.dts b/scripts/dtc/include-prefixes/arm/sun8i-s3-lichee-zero-plus.dts +deleted file mode 100644 +index d18192d51d1b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-s3-lichee-zero-plus.dts ++++ /dev/null +@@ -1,53 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 Icenowy Zheng +- */ +- +-/dts-v1/; +-#include "sun8i-v3.dtsi" +- +-#include +- +-/ { +- model = "Sipeed Lichee Zero Plus"; +- compatible = "sipeed,lichee-zero-plus", "sochip,s3", +- "allwinner,sun8i-v3"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- reg_vcc3v3: vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&mmc0 { +- broken-cd; +- bus-width = <4>; +- vmmc-supply = <®_vcc3v3>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-0 = <&uart0_pb_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-s3-pinecube.dts b/scripts/dtc/include-prefixes/arm/sun8i-s3-pinecube.dts +deleted file mode 100644 +index 20966e954eda..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-s3-pinecube.dts ++++ /dev/null +@@ -1,228 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR X11) +-/* +- * Copyright 2019 Icenowy Zheng +- */ +- +-/dts-v1/; +-#include "sun8i-v3.dtsi" +-#include +-#include +- +-/ { +- model = "PineCube IP Camera"; +- compatible = "pine64,pinecube", "sochip,s3", "allwinner,sun8i-v3"; +- +- aliases { +- serial0 = &uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led1 { +- label = "pine64:ir:led1"; +- gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ +- }; +- +- led2 { +- label = "pine64:ir:led2"; +- gpios = <&pio 1 12 GPIO_ACTIVE_LOW>; /* PB12 */ +- }; +- }; +- +- reg_vcc5v0: vcc5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_vcc_wifi: vcc-wifi { +- compatible = "regulator-fixed"; +- regulator-name = "vcc-wifi"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&pio 1 2 GPIO_ACTIVE_LOW>; /* PB2 WIFI-EN */ +- vin-supply = <®_dcdc3>; +- startup-delay-us = <200000>; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 WIFI-RST */ +- post-power-on-delay-ms = <200>; +- }; +-}; +- +-&csi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&csi1_8bit_pins>; +- status = "okay"; +- +- port { +- csi1_ep: endpoint { +- remote-endpoint = <&ov5640_ep>; +- bus-width = <8>; +- hsync-active = <1>; /* Active high */ +- vsync-active = <0>; /* Active low */ +- data-active = <1>; /* Active high */ +- pclk-sample = <1>; /* Rising */ +- }; +- }; +-}; +- +-&emac { +- phy-handle = <&int_mii_phy>; +- phy-mode = "mii"; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pe_pins>; +- status = "okay"; +- +- ov5640: camera@3c { +- compatible = "ovti,ov5640"; +- reg = <0x3c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&csi1_mclk_pin>; +- clocks = <&ccu CLK_CSI1_MCLK>; +- clock-names = "xclk"; +- +- AVDD-supply = <®_ldo3>; +- DOVDD-supply = <®_ldo3>; +- DVDD-supply = <®_ldo4>; +- reset-gpios = <&pio 4 23 GPIO_ACTIVE_LOW>; /* PE23 */ +- powerdown-gpios = <&pio 4 24 GPIO_ACTIVE_HIGH>; /* PE24 */ +- +- port { +- ov5640_ep: endpoint { +- remote-endpoint = <&csi1_ep>; +- bus-width = <8>; +- hsync-active = <1>; /* Active high */ +- vsync-active = <0>; /* Active low */ +- data-active = <1>; /* Active high */ +- pclk-sample = <1>; /* Rising */ +- }; +- }; +- }; +-}; +- +-&lradc { +- vref-supply = <®_ldo2>; +- status = "okay"; +- +- button-200 { +- label = "Setup"; +- linux,code = ; +- channel = <0>; +- voltage = <190000>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_dcdc3>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc_wifi>; +- vqmmc-supply = <®_dcdc3>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&pio { +- vcc-pd-supply = <®_dcdc3>; +- vcc-pe-supply = <®_ldo3>; +-}; +- +-#include "axp209.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- regulator-name = "vdd-sys-cpu-ephy"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_ldo3 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "avdd-dovdd-2v8-csi"; +- regulator-soft-start; +- regulator-ramp-delay = <1600>; +-}; +- +-®_ldo4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "dvdd-1v8-csi"; +-}; +- +-&spi0 { +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "winbond,w25q128", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; +- }; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_vbus-supply = <®_vcc5v0>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-t3-cqa3t-bv3.dts b/scripts/dtc/include-prefixes/arm/sun8i-t3-cqa3t-bv3.dts +deleted file mode 100644 +index 6931aaab2382..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-t3-cqa3t-bv3.dts ++++ /dev/null +@@ -1,226 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2017 Chen-Yu Tsai +- * Copyright (C) 2017 Icenowy Zheng +- * Copyright (C) 2018 Hao Zhang +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-r40.dtsi" +- +-#include +- +-/ { +- model = "t3-cqa3t-bv3"; +- compatible = "qihua,t3-cqa3t-bv3", "allwinner,sun8i-t3", +- "allwinner,sun8i-r40"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- reg_vcc5v0: vcc5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ +- enable-active-high; +- }; +-}; +- +-&ahci { +- ahci-supply = <®_dldo4>; +- phy-supply = <®_eldo3>; +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp22x: pmic@34 { +- compatible = "x-powers,axp221"; +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-#include "axp22x.dtsi" +- +-&mmc0 { +- vmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; /* PH15 */ +- status = "okay"; +-}; +- +-&mmc2 { +- vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_dcdc1>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-name = "vcc-pa"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "avcc"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-3v0"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dldo1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pg"; +-}; +- +-®_dldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-dldo3"; +-}; +- +-®_eldo3 { +- regulator-always-on; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "vcc-pe"; +-}; +- +-&tcon_tv0 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_vcc5v0>; +- usb2_vbus-supply = <®_vcc5v0>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-v3-sl631-imx179.dts b/scripts/dtc/include-prefixes/arm/sun8i-v3-sl631-imx179.dts +deleted file mode 100644 +index 117aeece4e55..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-v3-sl631-imx179.dts ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR X11) +-/* +- * Copyright 2020 Paul Kocialkowski +- */ +- +-#include "sun8i-v3-sl631.dtsi" +- +-/ { +- model = "SL631 Action Camera with IMX179"; +- compatible = "allwinner,sl631-imx179", "allwinner,sl631", +- "allwinner,sun8i-v3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-v3-sl631.dtsi b/scripts/dtc/include-prefixes/arm/sun8i-v3-sl631.dtsi +deleted file mode 100644 +index e0d2a31efc7f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-v3-sl631.dtsi ++++ /dev/null +@@ -1,138 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR X11) +-/* +- * Copyright 2020 Paul Kocialkowski +- */ +- +-/dts-v1/; +- +-#include "sun8i-v3.dtsi" +- +-#include +-#include +- +-/ { +- model = "SL631 Action Camera"; +- compatible = "allwinner,sl631", "allwinner,sun8i-v3"; +- +- aliases { +- serial0 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pb_pins>; +- status = "okay"; +-}; +- +-&lradc { +- vref-supply = <®_ldo2>; +- status = "okay"; +- +- button-174 { +- label = "Down"; +- linux,code = ; +- channel = <0>; +- voltage = <174603>; +- }; +- +- button-384 { +- label = "Up"; +- linux,code = ; +- channel = <0>; +- voltage = <384126>; +- }; +- +- button-593 { +- label = "OK"; +- linux,code = ; +- channel = <0>; +- voltage = <593650>; +- }; +-}; +- +-&mmc0 { +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- bus-width = <4>; +- vmmc-supply = <®_dcdc3>; +- status = "okay"; +-}; +- +-&pio { +- vcc-pd-supply = <®_dcdc3>; +- vcc-pe-supply = <®_dcdc3>; +-}; +- +-#include "axp209.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- regulator-name = "vdd-sys-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vdd-3v3"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- reg = <0>; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- }; +-}; +- +-&uart1 { +- pinctrl-0 = <&uart1_pg_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-v3.dtsi b/scripts/dtc/include-prefixes/arm/sun8i-v3.dtsi +deleted file mode 100644 +index 186c30cbe6ee..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-v3.dtsi ++++ /dev/null +@@ -1,63 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 Icenowy Zheng +- * Copyright (C) 2021 Tobias Schramm +- */ +- +-#include "sun8i-v3s.dtsi" +- +-/ { +- soc { +- i2s0: i2s@1c22000 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun8i-v3-i2s", +- "allwinner,sun8i-h3-i2s"; +- reg = <0x01c22000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; +- clock-names = "apb", "mod"; +- dmas = <&dma 3>, <&dma 3>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s0_pins>; +- resets = <&ccu RST_BUS_I2S0>; +- status = "disabled"; +- }; +- }; +-}; +- +-&ccu { +- compatible = "allwinner,sun8i-v3-ccu"; +-}; +- +-&codec_analog { +- compatible = "allwinner,sun8i-v3-codec-analog", +- "allwinner,sun8i-h3-codec-analog"; +-}; +- +-&emac { +- /delete-property/ phy-handle; +- /delete-property/ phy-mode; +-}; +- +-&mdio_mux { +- external_mdio: mdio@2 { +- reg = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +- +-&pio { +- compatible = "allwinner,sun8i-v3-pinctrl"; +- +- i2s0_pins: i2s0-pins { +- pins = "PG10", "PG11", "PG12", "PG13"; +- function = "i2s"; +- }; +- +- uart1_pg_pins: uart1-pg-pins { +- pins = "PG6", "PG7"; +- function = "uart1"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-v3s-licheepi-zero-dock.dts b/scripts/dtc/include-prefixes/arm/sun8i-v3s-licheepi-zero-dock.dts +deleted file mode 100644 +index 752ad05c8f83..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-v3s-licheepi-zero-dock.dts ++++ /dev/null +@@ -1,105 +0,0 @@ +-/* +- * Copyright (C) 2016 Icenowy Zheng +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "sun8i-v3s-licheepi-zero.dts" +- +-#include +- +-/ { +- model = "Lichee Pi Zero with Dock"; +- compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero", +- "allwinner,sun8i-v3s"; +- +- aliases { +- ethernet0 = &emac; +- }; +- +- leds { +- /* The LEDs use PG0~2 pins, which conflict with MMC1 */ +- status = "disabled"; +- }; +-}; +- +-&emac { +- allwinner,leds-active-low; +- status = "okay"; +-}; +- +-&lradc { +- vref-supply = <®_vcc3v0>; +- status = "okay"; +- +- button-200 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <200000>; +- }; +- +- button-400 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <400000>; +- }; +- +- button-600 { +- label = "Select"; +- linux,code = ; +- channel = <0>; +- voltage = <600000>; +- }; +- +- button-800 { +- label = "Start"; +- linux,code = ; +- channel = <0>; +- voltage = <800000>; +- }; +-}; +- +-&mmc1 { +- broken-cd; +- bus-width = <4>; +- vmmc-supply = <®_vcc3v3>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-v3s-licheepi-zero.dts b/scripts/dtc/include-prefixes/arm/sun8i-v3s-licheepi-zero.dts +deleted file mode 100644 +index 2e4587d26ce5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-v3s-licheepi-zero.dts ++++ /dev/null +@@ -1,101 +0,0 @@ +-/* +- * Copyright (C) 2016 Icenowy Zheng +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-v3s.dtsi" +-#include "sunxi-common-regulators.dtsi" +- +-/ { +- model = "Lichee Pi Zero"; +- compatible = "licheepi,licheepi-zero", "allwinner,sun8i-v3s"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- blue_led { +- label = "licheepi:blue:usr"; +- gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ +- }; +- +- green_led { +- label = "licheepi:green:usr"; +- gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ +- default-state = "on"; +- }; +- +- red_led { +- label = "licheepi:red:usr"; +- gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */ +- }; +- }; +-}; +- +-&mmc0 { +- broken-cd; +- bus-width = <4>; +- vmmc-supply = <®_vcc3v3>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-0 = <&uart0_pb_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-v3s.dtsi b/scripts/dtc/include-prefixes/arm/sun8i-v3s.dtsi +deleted file mode 100644 +index b30bc1a25ebb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-v3s.dtsi ++++ /dev/null +@@ -1,619 +0,0 @@ +-/* +- * Copyright (C) 2016 Icenowy Zheng +- * Copyright (C) 2021 Tobias Schramm +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&gic>; +- +- chosen { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- framebuffer-lcd { +- compatible = "allwinner,simple-framebuffer", +- "simple-framebuffer"; +- allwinner,pipeline = "mixer0-lcd0"; +- clocks = <&display_clocks CLK_MIXER0>, +- <&ccu CLK_TCON0>; +- status = "disabled"; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- reg = <0>; +- clocks = <&ccu CLK_CPU>; +- }; +- }; +- +- de: display-engine { +- compatible = "allwinner,sun8i-v3s-display-engine"; +- allwinner,pipelines = <&mixer0>; +- status = "disabled"; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- osc24M: osc24M_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-accuracy = <50000>; +- clock-output-names = "osc24M"; +- }; +- +- osc32k: osc32k_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-accuracy = <50000>; +- clock-output-names = "ext-osc32k"; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- display_clocks: clock@1000000 { +- compatible = "allwinner,sun8i-v3s-de2-clk"; +- reg = <0x01000000 0x10000>; +- clocks = <&ccu CLK_BUS_DE>, +- <&ccu CLK_DE>; +- clock-names = "bus", +- "mod"; +- resets = <&ccu RST_BUS_DE>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- mixer0: mixer@1100000 { +- compatible = "allwinner,sun8i-v3s-de2-mixer"; +- reg = <0x01100000 0x100000>; +- clocks = <&display_clocks 0>, +- <&display_clocks 6>; +- clock-names = "bus", +- "mod"; +- resets = <&display_clocks 0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mixer0_out: port@1 { +- reg = <1>; +- +- mixer0_out_tcon0: endpoint { +- remote-endpoint = <&tcon0_in_mixer0>; +- }; +- }; +- }; +- }; +- +- syscon: system-control@1c00000 { +- compatible = "allwinner,sun8i-v3s-system-control", +- "allwinner,sun8i-h3-system-control"; +- reg = <0x01c00000 0xd0>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- }; +- +- nmi_intc: interrupt-controller@1c000d0 { +- compatible = "allwinner,sun8i-v3s-nmi", +- "allwinner,sun9i-a80-nmi"; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x01c000d0 0x0c>; +- interrupts = ; +- }; +- +- dma: dma-controller@1c02000 { +- compatible = "allwinner,sun8i-v3s-dma"; +- reg = <0x01c02000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_DMA>; +- resets = <&ccu RST_BUS_DMA>; +- #dma-cells = <1>; +- }; +- +- tcon0: lcd-controller@1c0c000 { +- compatible = "allwinner,sun8i-v3s-tcon"; +- reg = <0x01c0c000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_TCON0>, +- <&ccu CLK_TCON0>; +- clock-names = "ahb", +- "tcon-ch0"; +- clock-output-names = "tcon-pixel-clock"; +- #clock-cells = <0>; +- resets = <&ccu RST_BUS_TCON0>; +- reset-names = "lcd"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon0_in: port@0 { +- reg = <0>; +- +- tcon0_in_mixer0: endpoint { +- remote-endpoint = <&mixer0_out_tcon0>; +- }; +- }; +- +- tcon0_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- }; +- }; +- +- +- mmc0: mmc@1c0f000 { +- compatible = "allwinner,sun7i-a20-mmc"; +- reg = <0x01c0f000 0x1000>; +- clocks = <&ccu CLK_BUS_MMC0>, +- <&ccu CLK_MMC0>, +- <&ccu CLK_MMC0_OUTPUT>, +- <&ccu CLK_MMC0_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- resets = <&ccu RST_BUS_MMC0>; +- reset-names = "ahb"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc1: mmc@1c10000 { +- compatible = "allwinner,sun7i-a20-mmc"; +- reg = <0x01c10000 0x1000>; +- clocks = <&ccu CLK_BUS_MMC1>, +- <&ccu CLK_MMC1>, +- <&ccu CLK_MMC1_OUTPUT>, +- <&ccu CLK_MMC1_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- resets = <&ccu RST_BUS_MMC1>; +- reset-names = "ahb"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc2: mmc@1c11000 { +- compatible = "allwinner,sun7i-a20-mmc"; +- reg = <0x01c11000 0x1000>; +- clocks = <&ccu CLK_BUS_MMC2>, +- <&ccu CLK_MMC2>, +- <&ccu CLK_MMC2_OUTPUT>, +- <&ccu CLK_MMC2_SAMPLE>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- resets = <&ccu RST_BUS_MMC2>; +- reset-names = "ahb"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- crypto@1c15000 { +- compatible = "allwinner,sun8i-v3s-crypto", +- "allwinner,sun8i-a33-crypto"; +- reg = <0x01c15000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; +- clock-names = "ahb", "mod"; +- dmas = <&dma 16>, <&dma 16>; +- dma-names = "rx", "tx"; +- resets = <&ccu RST_BUS_CE>; +- reset-names = "ahb"; +- }; +- +- usb_otg: usb@1c19000 { +- compatible = "allwinner,sun8i-h3-musb"; +- reg = <0x01c19000 0x0400>; +- clocks = <&ccu CLK_BUS_OTG>; +- resets = <&ccu RST_BUS_OTG>; +- interrupts = ; +- interrupt-names = "mc"; +- phys = <&usbphy 0>; +- phy-names = "usb"; +- extcon = <&usbphy 0>; +- status = "disabled"; +- }; +- +- usbphy: phy@1c19400 { +- compatible = "allwinner,sun8i-v3s-usb-phy"; +- reg = <0x01c19400 0x2c>, +- <0x01c1a800 0x4>; +- reg-names = "phy_ctrl", +- "pmu0"; +- clocks = <&ccu CLK_USB_PHY0>; +- clock-names = "usb0_phy"; +- resets = <&ccu RST_USB_PHY0>; +- reset-names = "usb0_reset"; +- status = "disabled"; +- #phy-cells = <1>; +- }; +- +- ccu: clock@1c20000 { +- compatible = "allwinner,sun8i-v3s-ccu"; +- reg = <0x01c20000 0x400>; +- clocks = <&osc24M>, <&rtc 0>; +- clock-names = "hosc", "losc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- rtc: rtc@1c20400 { +- #clock-cells = <1>; +- compatible = "allwinner,sun8i-v3-rtc"; +- reg = <0x01c20400 0x54>; +- interrupts = , +- ; +- clocks = <&osc32k>; +- clock-output-names = "osc32k", "osc32k-out"; +- }; +- +- pio: pinctrl@1c20800 { +- compatible = "allwinner,sun8i-v3s-pinctrl"; +- reg = <0x01c20800 0x400>; +- interrupts = , +- ; +- clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; +- clock-names = "apb", "hosc", "losc"; +- gpio-controller; +- #gpio-cells = <3>; +- interrupt-controller; +- #interrupt-cells = <3>; +- +- /omit-if-no-ref/ +- csi0_mclk_pin: csi0-mclk-pin { +- pins = "PE20"; +- function = "csi_mipi"; +- }; +- +- /omit-if-no-ref/ +- csi1_8bit_pins: csi1-8bit-pins { +- pins = "PE0", "PE2", "PE3", "PE8", "PE9", +- "PE10", "PE11", "PE12", "PE13", "PE14", +- "PE15"; +- function = "csi"; +- }; +- +- /omit-if-no-ref/ +- csi1_mclk_pin: csi1-mclk-pin { +- pins = "PE1"; +- function = "csi"; +- }; +- +- i2c0_pins: i2c0-pins { +- pins = "PB6", "PB7"; +- function = "i2c0"; +- }; +- +- /omit-if-no-ref/ +- i2c1_pb_pins: i2c1-pb-pins { +- pins = "PB8", "PB9"; +- function = "i2c1"; +- }; +- +- /omit-if-no-ref/ +- i2c1_pe_pins: i2c1-pe-pins { +- pins = "PE21", "PE22"; +- function = "i2c1"; +- }; +- +- uart0_pb_pins: uart0-pb-pins { +- pins = "PB8", "PB9"; +- function = "uart0"; +- }; +- +- uart2_pins: uart2-pins { +- pins = "PB0", "PB1"; +- function = "uart2"; +- }; +- +- mmc0_pins: mmc0-pins { +- pins = "PF0", "PF1", "PF2", "PF3", +- "PF4", "PF5"; +- function = "mmc0"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc1_pins: mmc1-pins { +- pins = "PG0", "PG1", "PG2", "PG3", +- "PG4", "PG5"; +- function = "mmc1"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- spi0_pins: spi0-pins { +- pins = "PC0", "PC1", "PC2", "PC3"; +- function = "spi0"; +- }; +- }; +- +- timer@1c20c00 { +- compatible = "allwinner,sun8i-v3s-timer"; +- reg = <0x01c20c00 0xa0>; +- interrupts = , +- , +- ; +- clocks = <&osc24M>; +- }; +- +- wdt0: watchdog@1c20ca0 { +- compatible = "allwinner,sun6i-a31-wdt"; +- reg = <0x01c20ca0 0x20>; +- interrupts = ; +- clocks = <&osc24M>; +- }; +- +- pwm: pwm@1c21400 { +- compatible = "allwinner,sun8i-v3s-pwm", +- "allwinner,sun7i-a20-pwm"; +- reg = <0x01c21400 0xc>; +- clocks = <&osc24M>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- lradc: lradc@1c22800 { +- compatible = "allwinner,sun4i-a10-lradc-keys"; +- reg = <0x01c22800 0x400>; +- interrupts = ; +- status = "disabled"; +- }; +- +- codec: codec@1c22c00 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun8i-v3s-codec"; +- reg = <0x01c22c00 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; +- clock-names = "apb", "codec"; +- resets = <&ccu RST_BUS_CODEC>; +- dmas = <&dma 15>, <&dma 15>; +- dma-names = "rx", "tx"; +- allwinner,codec-analog-controls = <&codec_analog>; +- status = "disabled"; +- }; +- +- codec_analog: codec-analog@1c23000 { +- compatible = "allwinner,sun8i-v3s-codec-analog"; +- reg = <0x01c23000 0x4>; +- }; +- +- uart0: serial@1c28000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART0>; +- dmas = <&dma 6>, <&dma 6>; +- dma-names = "rx", "tx"; +- resets = <&ccu RST_BUS_UART0>; +- status = "disabled"; +- }; +- +- uart1: serial@1c28400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28400 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART1>; +- dmas = <&dma 7>, <&dma 7>; +- dma-names = "rx", "tx"; +- resets = <&ccu RST_BUS_UART1>; +- status = "disabled"; +- }; +- +- uart2: serial@1c28800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28800 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART2>; +- dmas = <&dma 8>, <&dma 8>; +- dma-names = "rx", "tx"; +- resets = <&ccu RST_BUS_UART2>; +- pinctrl-0 = <&uart2_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- i2c0: i2c@1c2ac00 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2ac00 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C0>; +- resets = <&ccu RST_BUS_I2C0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c1: i2c@1c2b000 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2b000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C1>; +- resets = <&ccu RST_BUS_I2C1>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- emac: ethernet@1c30000 { +- compatible = "allwinner,sun8i-v3s-emac"; +- syscon = <&syscon>; +- reg = <0x01c30000 0x10000>; +- interrupts = ; +- interrupt-names = "macirq"; +- resets = <&ccu RST_BUS_EMAC>; +- reset-names = "stmmaceth"; +- clocks = <&ccu CLK_BUS_EMAC>; +- clock-names = "stmmaceth"; +- phy-handle = <&int_mii_phy>; +- phy-mode = "mii"; +- status = "disabled"; +- +- mdio: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- }; +- +- mdio_mux: mdio-mux { +- compatible = "allwinner,sun8i-h3-mdio-mux"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- mdio-parent-bus = <&mdio>; +- /* Only one MDIO is usable at the time */ +- internal_mdio: mdio@1 { +- compatible = "allwinner,sun8i-h3-mdio-internal"; +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- int_mii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- clocks = <&ccu CLK_BUS_EPHY>; +- resets = <&ccu RST_BUS_EPHY>; +- }; +- }; +- }; +- }; +- +- spi0: spi@1c68000 { +- compatible = "allwinner,sun8i-h3-spi"; +- reg = <0x01c68000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; +- clock-names = "ahb", "mod"; +- dmas = <&dma 23>, <&dma 23>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins>; +- resets = <&ccu RST_BUS_SPI0>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- csi1: camera@1cb4000 { +- compatible = "allwinner,sun8i-v3s-csi"; +- reg = <0x01cb4000 0x3000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_CSI>, +- <&ccu CLK_CSI1_SCLK>, +- <&ccu CLK_DRAM_CSI>; +- clock-names = "bus", "mod", "ram"; +- resets = <&ccu RST_BUS_CSI>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@1c81000 { +- compatible = "arm,gic-400"; +- reg = <0x01c81000 0x1000>, +- <0x01c82000 0x2000>, +- <0x01c84000 0x2000>, +- <0x01c86000 0x2000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = ; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun8i-v40-bananapi-m2-berry.dts b/scripts/dtc/include-prefixes/arm/sun8i-v40-bananapi-m2-berry.dts +deleted file mode 100644 +index 47954551f573..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun8i-v40-bananapi-m2-berry.dts ++++ /dev/null +@@ -1,305 +0,0 @@ +-/* +- * Copyright (C) 2017 Icenowy Zheng +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun8i-r40.dtsi" +- +-#include +- +-/ { +- model = "Banana Pi M2 Berry"; +- compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40"; +- +- aliases { +- ethernet0 = &gmac; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pwr-led { +- label = "bananapi:red:pwr"; +- gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- user-led { +- label = "bananapi:green:user"; +- gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- reg_vcc5v0: vcc5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ +- enable-active-high; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ +- clocks = <&ccu CLK_OUTA>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&ahci { +- ahci-supply = <®_dldo4>; +- phy-supply = <®_eldo3>; +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci1 { +- /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */ +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii-id"; +- phy-supply = <®_dc1sw>; +- status = "okay"; +-}; +- +-&gmac_mdio { +- phy1: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp22x: pmic@34 { +- compatible = "x-powers,axp221"; +- reg = <0x34>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-#include "axp22x.dtsi" +- +-&mmc0 { +- vmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */ +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pg_pins>; +- vmmc-supply = <®_dldo2>; +- vqmmc-supply = <®_dldo1>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&pio { +- pinctrl-names = "default"; +- pinctrl-0 = <&clk_out_a_pin>; +- vcc-pa-supply = <®_aldo2>; +- vcc-pc-supply = <®_dcdc1>; +- vcc-pd-supply = <®_dcdc1>; +- vcc-pe-supply = <®_eldo1>; +- vcc-pf-supply = <®_dcdc1>; +- vcc-pg-supply = <®_dldo1>; +-}; +- +-®_aldo2 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-name = "vcc-pa"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "avcc"; +-}; +- +-®_dc1sw { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-gmac-phy"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-io"; +-}; +- +-/* +- * Our WiFi chip needs both DLDO2 and DLDO3 to be powered at the same +- * time, with the two being in sync, to be able to meet maximum power +- * consumption during transmits. Since this is not really supported +- * right now, just use the two as always on, and we will fix it later. +- */ +- +-®_dldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-®_dldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-2"; +-}; +- +-®_dldo4 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-name = "vdd2v5-sata"; +-}; +- +-®_eldo3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vdd1v2-sata"; +-}; +- +-&tcon_tv0 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&ccu CLK_OUTA>; +- clock-names = "lpo"; +- vbat-supply = <®_dldo2>; +- vddio-supply = <®_dldo1>; +- device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ +- /* TODO host wake line connected to PMIC GPIO pins */ +- shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ +- max-speed = <1500000>; +- }; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_vcc5v0>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun9i-a80-cubieboard4.dts b/scripts/dtc/include-prefixes/arm/sun9i-a80-cubieboard4.dts +deleted file mode 100644 +index 1fe251ea94bc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun9i-a80-cubieboard4.dts ++++ /dev/null +@@ -1,508 +0,0 @@ +-/* +- * Copyright 2015 Tyler Baker +- * +- * Tyler Baker +- * Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun9i-a80.dtsi" +- +-#include +- +-/ { +- model = "Cubietech Cubieboard4"; +- compatible = "cubietech,a80-cubieboard4", "allwinner,sun9i-a80"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "cubieboard4:green:usr"; +- gpios = <&pio 7 17 GPIO_ACTIVE_HIGH>; /* PH17 */ +- }; +- +- led-1 { +- label = "cubieboard4:red:usr"; +- gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ +- }; +- }; +- +- vga-connector { +- compatible = "vga-connector"; +- label = "vga"; +- ddc-i2c-bus = <&i2c3>; +- +- port { +- vga_con_in: endpoint { +- remote-endpoint = <&vga_dac_out>; +- }; +- }; +- }; +- +- vga-dac { +- compatible = "corpro,gm7123", "adi,adv7123", "dumb-vga-dac"; +- vdd-supply = <®_dcdc1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- vga_dac_in: endpoint { +- remote-endpoint = <&tcon0_out_vga>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- vga_dac_out: endpoint { +- remote-endpoint = <&vga_con_in>; +- }; +- }; +- }; +- }; +- +- wifi_pwrseq: wifi-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&ac100_rtc 1>; +- clock-names = "ext_clock"; +- /* enables internal regulator and de-asserts reset */ +- reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ +- }; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii-id"; +- phy-supply = <®_cldo1>; +- status = "okay"; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- status = "okay"; +-}; +- +-&mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; /* PH18 */ +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <®_dldo1>; +- vqmmc-supply = <®_cldo3>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&mmc1_pins { +- bias-pull-up; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_pins>; +- vmmc-supply = <®_dcdc1>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&mmc2_8bit_pins { +- /* Increase drive strength for DDR modes */ +- drive-strength = <40>; +-}; +- +-&osc32k { +- /* osc32k input is from AC100 */ +- clocks = <&ac100_rtc 0>; +-}; +- +-&pio { +- vcc-pa-supply = <®_ldo_io1>; +- vcc-pb-supply = <®_aldo2>; +- vcc-pc-supply = <®_dcdc1>; +- vcc-pd-supply = <®_dc1sw>; +- vcc-pe-supply = <®_eldo2>; +- vcc-pf-supply = <®_dcdc1>; +- vcc-pg-supply = <®_ldo_io0>; +- vcc-ph-supply = <®_dcdc1>; +-}; +- +-&r_ir { +- status = "okay"; +-}; +- +-&r_pio { +- vcc-pl-supply = <®_dldo2>; +- vcc-pm-supply = <®_eldo3>; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp809: pmic@3a3 { +- reg = <0x3a3>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- +- regulators { +- reg_aldo1: aldo1 { +- /* +- * TODO: This should be handled by the +- * USB PHY driver. +- */ +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc33-usbh"; +- }; +- +- reg_aldo2: aldo2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-pb-io-cam"; +- }; +- +- aldo3 { +- /* unused */ +- }; +- +- reg_dc1sw: dc1sw { +- regulator-name = "vcc-pd"; +- }; +- +- reg_dc5ldo: dc5ldo { +- regulator-always-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpus-09-usbh"; +- }; +- +- reg_dcdc1: dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-3v"; +- }; +- +- reg_dcdc2: dcdc2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-gpu"; +- }; +- +- reg_dcdc3: dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpua"; +- }; +- +- reg_dcdc4: dcdc4 { +- regulator-always-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-sys-usb0-hdmi"; +- }; +- +- reg_dcdc5: dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1425000>; +- regulator-max-microvolt = <1575000>; +- regulator-name = "vcc-dram"; +- }; +- +- reg_dldo1: dldo1 { +- /* +- * The WiFi chip supports a wide range +- * (3.0 ~ 4.8V) of voltages, and so does +- * this regulator (3.0 ~ 4.2V), but +- * Allwinner SDK always sets it to 3.3V. +- */ +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +- }; +- +- reg_dldo2: dldo2 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-pl"; +- }; +- +- reg_eldo1: eldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-dvdd-cam"; +- }; +- +- reg_eldo2: eldo2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-pe"; +- }; +- +- reg_eldo3: eldo3 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-pm-codec-io1"; +- }; +- +- reg_ldo_io0: ldo_io0 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-pg"; +- }; +- +- reg_ldo_io1: ldo_io1 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-name = "vcc-pa-gmac-2v5"; +- }; +- +- reg_rtc_ldo: rtc_ldo { +- regulator-name = "vcc-rtc-vdd1v8-io"; +- }; +- +- sw { +- /* unused */ +- }; +- }; +- }; +- +- axp806: pmic@745 { +- compatible = "x-powers,axp806"; +- reg = <0x745>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <1>; +- bldoin-supply = <®_dcdce>; +- +- regulators { +- reg_s_aldo1: aldo1 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +- }; +- +- aldo2 { +- /* +- * unused, but use a different name to +- * avoid name clash with axp809's aldo's +- */ +- regulator-name = "s_aldo2"; +- }; +- +- aldo3 { +- /* +- * unused, but use a different name to +- * avoid name clash with axp809's aldo's +- */ +- regulator-name = "s_aldo3"; +- }; +- +- reg_bldo1: bldo1 { +- regulator-always-on; +- regulator-min-microvolt = <1700000>; +- regulator-max-microvolt = <1900000>; +- regulator-name = "vcc18-efuse-adc-display-csi"; +- }; +- +- reg_bldo2: bldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1700000>; +- regulator-max-microvolt = <1900000>; +- regulator-name = +- "vdd18-drampll-vcc18-pll-cpvdd"; +- }; +- +- bldo3 { +- /* unused */ +- }; +- +- reg_bldo4: bldo4 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vcc12-hsic"; +- }; +- +- reg_cldo1: cldo1 { +- /* +- * This was 3V in the original design, but +- * 3.3V is the recommended supply voltage +- * for the Ethernet PHY. +- */ +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- /* +- * The PHY requires 20ms after all voltages +- * are applied until core logic is ready and +- * 30ms after the reset pin is de-asserted. +- * Set a 100ms delay to account for PMIC +- * ramp time and board traces. +- */ +- regulator-enable-ramp-delay = <100000>; +- regulator-name = "vcc-gmac-phy"; +- }; +- +- reg_cldo2: cldo2 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "afvcc-cam"; +- }; +- +- reg_cldo3: cldo3 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-io-wifi-codec-io2"; +- }; +- +- reg_dcdca: dcdca { +- regulator-always-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpub"; +- }; +- +- reg_dcdcd: dcdcd { +- regulator-always-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-vpu"; +- }; +- +- reg_dcdce: dcdce { +- regulator-always-on; +- regulator-min-microvolt = <2100000>; +- regulator-max-microvolt = <2100000>; +- regulator-name = "vcc-bldo-codec-ldoin"; +- }; +- +- sw { +- /* +- * unused, but use a different name to +- * avoid name clash with axp809's sw +- */ +- regulator-name = "s_sw"; +- }; +- }; +- }; +- +- ac100: codec@e89 { +- compatible = "x-powers,ac100"; +- reg = <0xe89>; +- +- ac100_codec: codec { +- compatible = "x-powers,ac100-codec"; +- interrupt-parent = <&r_pio>; +- interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ +- #clock-cells = <0>; +- clock-output-names = "4M_adda"; +- }; +- +- ac100_rtc: rtc { +- compatible = "x-powers,ac100-rtc"; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- clocks = <&ac100_codec>; +- #clock-cells = <1>; +- clock-output-names = "cko1_rtc", +- "cko2_rtc", +- "cko3_rtc"; +- }; +- }; +-}; +- +-#include "axp809.dtsi" +- +-&tcon0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd0_rgb888_pins>; +-}; +- +-&tcon0_out { +- tcon0_out_vga: endpoint { +- remote-endpoint = <&vga_dac_in>; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ph_pins>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun9i-a80-optimus.dts b/scripts/dtc/include-prefixes/arm/sun9i-a80-optimus.dts +deleted file mode 100644 +index 5c3580d712e4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun9i-a80-optimus.dts ++++ /dev/null +@@ -1,510 +0,0 @@ +-/* +- * Copyright 2014 Chen-Yu Tsai +- * +- * Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "sun9i-a80.dtsi" +- +-#include +- +-/ { +- model = "Merrii A80 Optimus Board"; +- compatible = "merrii,a80-optimus", "allwinner,sun9i-a80"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart4; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- /* The LED names match those found on the board */ +- led2 { +- label = "optimus:led2:usr"; +- gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; +- }; +- +- led3 { +- label = "optimus:led3:usr"; +- gpios = <&r_pio 1 15 GPIO_ACTIVE_HIGH>; /* PM15 */ +- }; +- +- led4 { +- label = "optimus:led4:usr"; +- gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- reg_usb1_vbus: usb1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb1-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ +- }; +- +- reg_usb3_vbus: usb3-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb3-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ +- }; +- +- wifi_pwrseq: wifi-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&ac100_rtc 1>; +- clock-names = "ext_clock"; +- /* enables internal regulator and de-asserts reset */ +- reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- /* Enable if HSIC peripheral is connected */ +- status = "disabled"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&gmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&gmac_rgmii_pins>; +- phy-handle = <&phy1>; +- phy-mode = "rgmii-id"; +- phy-supply = <®_cldo1>; +- status = "okay"; +-}; +- +-&mdio { +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_dcdc1>; +- bus-width = <4>; +- cd-gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; /* PH8 */ +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <®_dldo1>; +- vqmmc-supply = <®_cldo3>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&mmc1_pins { +- bias-pull-up; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_pins>; +- vmmc-supply = <®_dcdc1>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&mmc2_8bit_pins { +- /* Increase drive strength for DDR modes */ +- drive-strength = <40>; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-&osc32k { +- /* osc32k input is from AC100 */ +- clocks = <&ac100_rtc 0>; +-}; +- +-&pio { +- vcc-pa-supply = <®_ldo_io1>; +- vcc-pb-supply = <®_aldo2>; +- vcc-pc-supply = <®_dcdc1>; +- vcc-pd-supply = <®_dcdc1>; +- vcc-pe-supply = <®_eldo2>; +- vcc-pf-supply = <®_dcdc1>; +- vcc-pg-supply = <®_ldo_io0>; +- vcc-ph-supply = <®_dcdc1>; +-}; +- +-&r_ir { +- status = "okay"; +-}; +- +-&r_pio { +- vcc-pl-supply = <®_dldo2>; +- vcc-pm-supply = <®_eldo3>; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp809: pmic@3a3 { +- reg = <0x3a3>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- +- regulators { +- reg_aldo1: aldo1 { +- /* +- * TODO: This should be handled by the +- * USB PHY driver. +- */ +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc33-usbh"; +- }; +- +- reg_aldo2: aldo2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-pb-io-cam"; +- }; +- +- aldo3 { +- /* unused */ +- }; +- +- reg_dc5ldo: dc5ldo { +- regulator-always-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpus-09-usbh"; +- }; +- +- dc1sw { +- /* unused */ +- }; +- +- reg_dcdc1: dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-3v"; +- }; +- +- reg_dcdc2: dcdc2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-gpu"; +- }; +- +- reg_dcdc3: dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpua"; +- }; +- +- reg_dcdc4: dcdc4 { +- regulator-always-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-sys-usb0-hdmi"; +- }; +- +- reg_dcdc5: dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1425000>; +- regulator-max-microvolt = <1575000>; +- regulator-name = "vcc-dram"; +- }; +- +- reg_dldo1: dldo1 { +- /* +- * The WiFi chip supports a wide range +- * (3.0 ~ 4.8V) of voltages, and so does +- * this regulator (3.0 ~ 4.2V), but +- * Allwinner SDK always sets it to 3.3V. +- */ +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +- }; +- +- reg_dldo2: dldo2 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-pl"; +- }; +- +- reg_eldo1: eldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-dvdd-cam"; +- }; +- +- reg_eldo2: eldo2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-pe"; +- }; +- +- reg_eldo3: eldo3 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-pm-codec-io1"; +- }; +- +- reg_ldo_io0: ldo_io0 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-pg"; +- }; +- +- reg_ldo_io1: ldo_io1 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-name = "vcc-pa-gmac-2v5"; +- }; +- +- reg_rtc_ldo: rtc_ldo { +- regulator-name = "vcc-rtc-vdd1v8-io"; +- }; +- +- sw { +- /* unused */ +- }; +- }; +- }; +- +- axp806: pmic@745 { +- compatible = "x-powers,axp806"; +- reg = <0x745>; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <1>; +- bldoin-supply = <®_dcdce>; +- +- regulators { +- reg_s_aldo1: aldo1 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +- }; +- +- aldo2 { +- /* +- * unused, but use a different name to +- * avoid name clash with axp809's aldo's +- */ +- regulator-name = "s_aldo2"; +- }; +- +- aldo3 { +- /* +- * unused, but use a different name to +- * avoid name clash with axp809's aldo's +- */ +- regulator-name = "s_aldo3"; +- }; +- +- reg_bldo1: bldo1 { +- regulator-always-on; +- regulator-min-microvolt = <1700000>; +- regulator-max-microvolt = <1900000>; +- regulator-name = "vcc18-efuse-adc-display-csi"; +- }; +- +- reg_bldo2: bldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1700000>; +- regulator-max-microvolt = <1900000>; +- regulator-name = +- "vdd18-drampll-vcc18-pll-cpvdd"; +- }; +- +- bldo3 { +- /* unused */ +- }; +- +- reg_bldo4: bldo4 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vcc12-hsic"; +- }; +- +- reg_cldo1: cldo1 { +- /* +- * This was 3V in the original design, but +- * 3.3V is the recommended supply voltage +- * for the Ethernet PHY. +- */ +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- /* +- * The PHY requires 20ms after all voltages +- * are applied until core logic is ready and +- * 30ms after the reset pin is de-asserted. +- * Set a 100ms delay to account for PMIC +- * ramp time and board traces. +- */ +- regulator-enable-ramp-delay = <100000>; +- regulator-name = "vcc-gmac-phy"; +- }; +- +- reg_cldo2: cldo2 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "afvcc-cam"; +- }; +- +- reg_cldo3: cldo3 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-io-wifi-codec-io2"; +- }; +- +- reg_dcdca: dcdca { +- regulator-always-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpub"; +- }; +- +- reg_dcdcd: dcdcd { +- regulator-always-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-vpu"; +- }; +- +- reg_dcdce: dcdce { +- regulator-always-on; +- regulator-min-microvolt = <2100000>; +- regulator-max-microvolt = <2100000>; +- regulator-name = "vcc-bldo-codec-ldoin"; +- }; +- +- sw { +- /* +- * unused, but use a different name to +- * avoid name clash with axp809's sw +- */ +- regulator-name = "s_sw"; +- }; +- }; +- }; +- +- ac100: codec@e89 { +- compatible = "x-powers,ac100"; +- reg = <0xe89>; +- +- ac100_codec: codec { +- compatible = "x-powers,ac100-codec"; +- interrupt-parent = <&r_pio>; +- interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ +- #clock-cells = <0>; +- clock-output-names = "4M_adda"; +- }; +- +- ac100_rtc: rtc { +- compatible = "x-powers,ac100-rtc"; +- interrupt-parent = <&nmi_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- clocks = <&ac100_codec>; +- #clock-cells = <1>; +- clock-output-names = "cko1_rtc", +- "cko2_rtc", +- "cko3_rtc"; +- }; +- }; +-}; +- +-#include "axp809.dtsi" +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ph_pins>; +- status = "okay"; +-}; +- +-&usbphy1 { +- phy-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +- +-&usbphy2 { +- phy-supply = <®_bldo4>; +- /* Enable if HSIC peripheral is connected */ +- status = "disabled"; +-}; +- +-&usbphy3 { +- phy-supply = <®_usb3_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sun9i-a80.dtsi b/scripts/dtc/include-prefixes/arm/sun9i-a80.dtsi +deleted file mode 100644 +index ce4fa6706d06..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sun9i-a80.dtsi ++++ /dev/null +@@ -1,1254 +0,0 @@ +-/* +- * Copyright 2014 Chen-Yu Tsai +- * +- * Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&gic>; +- +- aliases { +- ethernet0 = &gmac; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- cci-control-port = <&cci_control0>; +- clock-frequency = <12000000>; +- enable-method = "allwinner,sun9i-a80-smp"; +- reg = <0x0>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- cci-control-port = <&cci_control0>; +- clock-frequency = <12000000>; +- enable-method = "allwinner,sun9i-a80-smp"; +- reg = <0x1>; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- cci-control-port = <&cci_control0>; +- clock-frequency = <12000000>; +- enable-method = "allwinner,sun9i-a80-smp"; +- reg = <0x2>; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a7"; +- device_type = "cpu"; +- cci-control-port = <&cci_control0>; +- clock-frequency = <12000000>; +- enable-method = "allwinner,sun9i-a80-smp"; +- reg = <0x3>; +- }; +- +- cpu4: cpu@100 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- cci-control-port = <&cci_control1>; +- clock-frequency = <18000000>; +- enable-method = "allwinner,sun9i-a80-smp"; +- reg = <0x100>; +- }; +- +- cpu5: cpu@101 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- cci-control-port = <&cci_control1>; +- clock-frequency = <18000000>; +- enable-method = "allwinner,sun9i-a80-smp"; +- reg = <0x101>; +- }; +- +- cpu6: cpu@102 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- cci-control-port = <&cci_control1>; +- clock-frequency = <18000000>; +- enable-method = "allwinner,sun9i-a80-smp"; +- reg = <0x102>; +- }; +- +- cpu7: cpu@103 { +- compatible = "arm,cortex-a15"; +- device_type = "cpu"; +- cci-control-port = <&cci_control1>; +- clock-frequency = <18000000>; +- enable-method = "allwinner,sun9i-a80-smp"; +- reg = <0x103>; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- clock-frequency = <24000000>; +- arm,cpu-registers-not-fw-configured; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * map 64 bit address range down to 32 bits, +- * as the peripherals are all under 512MB. +- */ +- ranges = <0 0 0 0x20000000>; +- +- /* +- * This clock is actually configurable from the PRCM address +- * space. The external 24M oscillator can be turned off, and +- * the clock switched to an internal 16M RC oscillator. Under +- * normal operation there's no reason to do this, and the +- * default is to use the external good one, so just model this +- * as a fixed clock. Also it is not entirely clear if the +- * osc24M mux in the PRCM affects the entire clock tree, which +- * would also throw all the PLL clock rates off, or just the +- * downstream clocks in the PRCM. +- */ +- osc24M: clk-24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "osc24M"; +- }; +- +- /* +- * The 32k clock is from an external source, normally the +- * AC100 codec/RTC chip. This serves as a placeholder for +- * board dts files to specify the source. +- */ +- osc32k: clk-32k { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clock-output-names = "osc32k"; +- }; +- +- /* +- * The following two are dummy clocks, placeholders +- * used in the gmac_tx clock. The gmac driver will +- * choose one parent depending on the PHY interface +- * mode, using clk_set_rate auto-reparenting. +- * +- * The actual TX clock rate is not controlled by the +- * gmac_tx clock. +- */ +- mii_phy_tx_clk: mii_phy_tx_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25000000>; +- clock-output-names = "mii_phy_tx"; +- }; +- +- gmac_int_tx_clk: gmac_int_tx_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "gmac_int_tx"; +- }; +- +- gmac_tx_clk: clk@800030 { +- #clock-cells = <0>; +- compatible = "allwinner,sun7i-a20-gmac-clk"; +- reg = <0x00800030 0x4>; +- clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; +- clock-output-names = "gmac_tx"; +- }; +- +- cpus_clk: clk@8001410 { +- compatible = "allwinner,sun9i-a80-cpus-clk"; +- reg = <0x08001410 0x4>; +- #clock-cells = <0>; +- clocks = <&osc32k>, <&osc24M>, +- <&ccu CLK_PLL_PERIPH0>, +- <&ccu CLK_PLL_AUDIO>; +- clock-output-names = "cpus"; +- }; +- +- ahbs: clk-ahbs { +- compatible = "fixed-factor-clock"; +- #clock-cells = <0>; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&cpus_clk>; +- clock-output-names = "ahbs"; +- }; +- +- apbs: clk@800141c { +- compatible = "allwinner,sun8i-a23-apb0-clk"; +- reg = <0x0800141c 0x4>; +- #clock-cells = <0>; +- clocks = <&ahbs>; +- clock-output-names = "apbs"; +- }; +- +- apbs_gates: clk@8001428 { +- compatible = "allwinner,sun9i-a80-apbs-gates-clk"; +- reg = <0x08001428 0x4>; +- #clock-cells = <1>; +- clocks = <&apbs>; +- clock-indices = <0>, <1>, +- <2>, <3>, +- <4>, <5>, +- <6>, <7>, +- <12>, <13>, +- <16>, <17>, +- <18>, <20>; +- clock-output-names = "apbs_pio", "apbs_ir", +- "apbs_timer", "apbs_rsb", +- "apbs_uart", "apbs_1wire", +- "apbs_i2c0", "apbs_i2c1", +- "apbs_ps2_0", "apbs_ps2_1", +- "apbs_dma", "apbs_i2s0", +- "apbs_i2s1", "apbs_twd"; +- }; +- +- r_1wire_clk: clk@8001450 { +- reg = <0x08001450 0x4>; +- #clock-cells = <0>; +- compatible = "allwinner,sun4i-a10-mod0-clk"; +- clocks = <&osc32k>, <&osc24M>; +- clock-output-names = "r_1wire"; +- }; +- +- r_ir_clk: clk@8001454 { +- reg = <0x08001454 0x4>; +- #clock-cells = <0>; +- compatible = "allwinner,sun4i-a10-mod0-clk"; +- clocks = <&osc32k>, <&osc24M>; +- clock-output-names = "r_ir"; +- }; +- }; +- +- de: display-engine { +- compatible = "allwinner,sun9i-a80-display-engine"; +- allwinner,pipelines = <&fe0>, <&fe1>; +- status = "disabled"; +- }; +- +- soc@20000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * map 64 bit address range down to 32 bits, +- * as the peripherals are all under 512MB. +- */ +- ranges = <0 0 0 0x20000000>; +- +- sram_b: sram@20000 { +- /* 256 KiB secure SRAM at 0x20000 */ +- compatible = "mmio-sram"; +- reg = <0x00020000 0x40000>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00020000 0x40000>; +- +- smp-sram@1000 { +- /* +- * This is checked by BROM to determine if +- * cpu0 should jump to SMP entry vector +- */ +- compatible = "allwinner,sun9i-a80-smp-sram"; +- reg = <0x1000 0x8>; +- }; +- }; +- +- gmac: ethernet@830000 { +- compatible = "allwinner,sun7i-a20-gmac"; +- reg = <0x00830000 0x1054>; +- interrupts = ; +- interrupt-names = "macirq"; +- clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>; +- clock-names = "stmmaceth", "allwinner_gmac_tx"; +- resets = <&ccu RST_BUS_GMAC>; +- reset-names = "stmmaceth"; +- snps,pbl = <2>; +- snps,fixed-burst; +- snps,force_sf_dma_mode; +- status = "disabled"; +- +- mdio: mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- ehci0: usb@a00000 { +- compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; +- reg = <0x00a00000 0x100>; +- interrupts = ; +- clocks = <&usb_clocks CLK_BUS_HCI0>; +- resets = <&usb_clocks RST_USB0_HCI>; +- phys = <&usbphy1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci0: usb@a00400 { +- compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; +- reg = <0x00a00400 0x100>; +- interrupts = ; +- clocks = <&usb_clocks CLK_BUS_HCI0>, +- <&usb_clocks CLK_USB_OHCI0>; +- resets = <&usb_clocks RST_USB0_HCI>; +- phys = <&usbphy1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usbphy1: phy@a00800 { +- compatible = "allwinner,sun9i-a80-usb-phy"; +- reg = <0x00a00800 0x4>; +- clocks = <&usb_clocks CLK_USB0_PHY>; +- clock-names = "phy"; +- resets = <&usb_clocks RST_USB0_PHY>; +- reset-names = "phy"; +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- ehci1: usb@a01000 { +- compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; +- reg = <0x00a01000 0x100>; +- interrupts = ; +- clocks = <&usb_clocks CLK_BUS_HCI1>; +- resets = <&usb_clocks RST_USB1_HCI>; +- phys = <&usbphy2>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usbphy2: phy@a01800 { +- compatible = "allwinner,sun9i-a80-usb-phy"; +- reg = <0x00a01800 0x4>; +- clocks = <&usb_clocks CLK_USB1_PHY>, +- <&usb_clocks CLK_USB_HSIC>, +- <&usb_clocks CLK_USB1_HSIC>; +- clock-names = "phy", +- "hsic_12M", +- "hsic_480M"; +- resets = <&usb_clocks RST_USB1_PHY>, +- <&usb_clocks RST_USB1_HSIC>; +- reset-names = "phy", +- "hsic"; +- status = "disabled"; +- #phy-cells = <0>; +- /* usb1 is always used with HSIC */ +- phy_type = "hsic"; +- }; +- +- ehci2: usb@a02000 { +- compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; +- reg = <0x00a02000 0x100>; +- interrupts = ; +- clocks = <&usb_clocks CLK_BUS_HCI2>; +- resets = <&usb_clocks RST_USB2_HCI>; +- phys = <&usbphy3>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci2: usb@a02400 { +- compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; +- reg = <0x00a02400 0x100>; +- interrupts = ; +- clocks = <&usb_clocks CLK_BUS_HCI2>, +- <&usb_clocks CLK_USB_OHCI2>; +- resets = <&usb_clocks RST_USB2_HCI>; +- phys = <&usbphy3>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usbphy3: phy@a02800 { +- compatible = "allwinner,sun9i-a80-usb-phy"; +- reg = <0x00a02800 0x4>; +- clocks = <&usb_clocks CLK_USB2_PHY>, +- <&usb_clocks CLK_USB_HSIC>, +- <&usb_clocks CLK_USB2_HSIC>; +- clock-names = "phy", +- "hsic_12M", +- "hsic_480M"; +- resets = <&usb_clocks RST_USB2_PHY>, +- <&usb_clocks RST_USB2_HSIC>; +- reset-names = "phy", +- "hsic"; +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- usb_clocks: clock@a08000 { +- compatible = "allwinner,sun9i-a80-usb-clks"; +- reg = <0x00a08000 0x8>; +- clocks = <&ccu CLK_BUS_USB>, <&osc24M>; +- clock-names = "bus", "hosc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- cpucfg@1700000 { +- compatible = "allwinner,sun9i-a80-cpucfg"; +- reg = <0x01700000 0x100>; +- }; +- +- crypto: crypto@1c02000 { +- compatible = "allwinner,sun9i-a80-crypto"; +- reg = <0x01c02000 0x1000>; +- interrupts = ; +- resets = <&ccu RST_BUS_SS>; +- clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; +- clock-names = "bus", "mod"; +- }; +- +- mmc0: mmc@1c0f000 { +- compatible = "allwinner,sun9i-a80-mmc"; +- reg = <0x01c0f000 0x1000>; +- clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>, +- <&ccu CLK_MMC0_OUTPUT>, +- <&ccu CLK_MMC0_SAMPLE>; +- clock-names = "ahb", "mmc", "output", "sample"; +- resets = <&mmc_config_clk 0>; +- reset-names = "ahb"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc1: mmc@1c10000 { +- compatible = "allwinner,sun9i-a80-mmc"; +- reg = <0x01c10000 0x1000>; +- clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>, +- <&ccu CLK_MMC1_OUTPUT>, +- <&ccu CLK_MMC1_SAMPLE>; +- clock-names = "ahb", "mmc", "output", "sample"; +- resets = <&mmc_config_clk 1>; +- reset-names = "ahb"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc2: mmc@1c11000 { +- compatible = "allwinner,sun9i-a80-mmc"; +- reg = <0x01c11000 0x1000>; +- clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>, +- <&ccu CLK_MMC2_OUTPUT>, +- <&ccu CLK_MMC2_SAMPLE>; +- clock-names = "ahb", "mmc", "output", "sample"; +- resets = <&mmc_config_clk 2>; +- reset-names = "ahb"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc3: mmc@1c12000 { +- compatible = "allwinner,sun9i-a80-mmc"; +- reg = <0x01c12000 0x1000>; +- clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>, +- <&ccu CLK_MMC3_OUTPUT>, +- <&ccu CLK_MMC3_SAMPLE>; +- clock-names = "ahb", "mmc", "output", "sample"; +- resets = <&mmc_config_clk 3>; +- reset-names = "ahb"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc_config_clk: clk@1c13000 { +- compatible = "allwinner,sun9i-a80-mmc-config-clk"; +- reg = <0x01c13000 0x10>; +- clocks = <&ccu CLK_BUS_MMC>; +- resets = <&ccu RST_BUS_MMC>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- clock-output-names = "mmc0_config", "mmc1_config", +- "mmc2_config", "mmc3_config"; +- }; +- +- gic: interrupt-controller@1c41000 { +- compatible = "arm,gic-400"; +- reg = <0x01c41000 0x1000>, +- <0x01c42000 0x2000>, +- <0x01c44000 0x2000>, +- <0x01c46000 0x2000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = ; +- }; +- +- cci: cci@1c90000 { +- compatible = "arm,cci-400"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x01c90000 0x1000>; +- ranges = <0x0 0x01c90000 0x10000>; +- +- cci_control0: slave-if@4000 { +- compatible = "arm,cci-400-ctrl-if"; +- interface-type = "ace"; +- reg = <0x4000 0x1000>; +- }; +- +- cci_control1: slave-if@5000 { +- compatible = "arm,cci-400-ctrl-if"; +- interface-type = "ace"; +- reg = <0x5000 0x1000>; +- }; +- +- pmu@9000 { +- compatible = "arm,cci-400-pmu,r1"; +- reg = <0x9000 0x5000>; +- interrupts = , +- , +- , +- , +- ; +- }; +- }; +- +- de_clocks: clock@3000000 { +- compatible = "allwinner,sun9i-a80-de-clks"; +- reg = <0x03000000 0x30>; +- clocks = <&ccu CLK_DE>, +- <&ccu CLK_SDRAM>, +- <&ccu CLK_BUS_DE>; +- clock-names = "mod", +- "dram", +- "bus"; +- resets = <&ccu RST_BUS_DE>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- fe0: display-frontend@3100000 { +- compatible = "allwinner,sun9i-a80-display-frontend"; +- reg = <0x03100000 0x40000>; +- interrupts = ; +- clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>, +- <&de_clocks CLK_DRAM_FE0>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&de_clocks RST_FE0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- fe0_out: port@1 { +- reg = <1>; +- +- fe0_out_deu0: endpoint { +- remote-endpoint = <&deu0_in_fe0>; +- }; +- }; +- }; +- }; +- +- fe1: display-frontend@3140000 { +- compatible = "allwinner,sun9i-a80-display-frontend"; +- reg = <0x03140000 0x40000>; +- interrupts = ; +- clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>, +- <&de_clocks CLK_DRAM_FE1>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&de_clocks RST_FE0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- fe1_out: port@1 { +- reg = <1>; +- +- fe1_out_deu1: endpoint { +- remote-endpoint = <&deu1_in_fe1>; +- }; +- }; +- }; +- }; +- +- be0: display-backend@3200000 { +- compatible = "allwinner,sun9i-a80-display-backend"; +- reg = <0x03200000 0x40000>; +- interrupts = ; +- clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>, +- <&de_clocks CLK_DRAM_BE0>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&de_clocks RST_BE0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- be0_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- be0_in_deu0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&deu0_out_be0>; +- }; +- +- be0_in_deu1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&deu1_out_be0>; +- }; +- }; +- +- be0_out: port@1 { +- reg = <1>; +- +- be0_out_drc0: endpoint { +- remote-endpoint = <&drc0_in_be0>; +- }; +- }; +- }; +- }; +- +- be1: display-backend@3240000 { +- compatible = "allwinner,sun9i-a80-display-backend"; +- reg = <0x03240000 0x40000>; +- interrupts = ; +- clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>, +- <&de_clocks CLK_DRAM_BE1>; +- clock-names = "ahb", "mod", +- "ram"; +- resets = <&de_clocks RST_BE1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- be1_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- be1_in_deu0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&deu0_out_be1>; +- }; +- +- be1_in_deu1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&deu1_out_be1>; +- }; +- }; +- +- be1_out: port@1 { +- reg = <1>; +- +- be1_out_drc1: endpoint { +- remote-endpoint = <&drc1_in_be1>; +- }; +- }; +- }; +- }; +- +- deu0: deu@3300000 { +- compatible = "allwinner,sun9i-a80-deu"; +- reg = <0x03300000 0x40000>; +- interrupts = ; +- clocks = <&de_clocks CLK_BUS_DEU0>, +- <&de_clocks CLK_IEP_DEU0>, +- <&de_clocks CLK_DRAM_DEU0>; +- clock-names = "ahb", +- "mod", +- "ram"; +- resets = <&de_clocks RST_DEU0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- deu0_in: port@0 { +- reg = <0>; +- +- deu0_in_fe0: endpoint { +- remote-endpoint = <&fe0_out_deu0>; +- }; +- }; +- +- deu0_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- deu0_out_be0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&be0_in_deu0>; +- }; +- +- deu0_out_be1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&be1_in_deu0>; +- }; +- }; +- }; +- }; +- +- deu1: deu@3340000 { +- compatible = "allwinner,sun9i-a80-deu"; +- reg = <0x03340000 0x40000>; +- interrupts = ; +- clocks = <&de_clocks CLK_BUS_DEU1>, +- <&de_clocks CLK_IEP_DEU1>, +- <&de_clocks CLK_DRAM_DEU1>; +- clock-names = "ahb", +- "mod", +- "ram"; +- resets = <&de_clocks RST_DEU1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- deu1_in: port@0 { +- reg = <0>; +- +- deu1_in_fe1: endpoint { +- remote-endpoint = <&fe1_out_deu1>; +- }; +- }; +- +- deu1_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- deu1_out_be0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&be0_in_deu1>; +- }; +- +- deu1_out_be1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&be1_in_deu1>; +- }; +- }; +- }; +- }; +- +- drc0: drc@3400000 { +- compatible = "allwinner,sun9i-a80-drc"; +- reg = <0x03400000 0x40000>; +- interrupts = ; +- clocks = <&de_clocks CLK_BUS_DRC0>, +- <&de_clocks CLK_IEP_DRC0>, +- <&de_clocks CLK_DRAM_DRC0>; +- clock-names = "ahb", +- "mod", +- "ram"; +- resets = <&de_clocks RST_DRC0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- drc0_in: port@0 { +- reg = <0>; +- +- drc0_in_be0: endpoint { +- remote-endpoint = <&be0_out_drc0>; +- }; +- }; +- +- drc0_out: port@1 { +- reg = <1>; +- +- drc0_out_tcon0: endpoint { +- remote-endpoint = <&tcon0_in_drc0>; +- }; +- }; +- }; +- }; +- +- drc1: drc@3440000 { +- compatible = "allwinner,sun9i-a80-drc"; +- reg = <0x03440000 0x40000>; +- interrupts = ; +- clocks = <&de_clocks CLK_BUS_DRC1>, +- <&de_clocks CLK_IEP_DRC1>, +- <&de_clocks CLK_DRAM_DRC1>; +- clock-names = "ahb", +- "mod", +- "ram"; +- resets = <&de_clocks RST_DRC1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- drc1_in: port@0 { +- reg = <0>; +- +- drc1_in_be1: endpoint { +- remote-endpoint = <&be1_out_drc1>; +- }; +- }; +- +- drc1_out: port@1 { +- reg = <1>; +- +- drc1_out_tcon1: endpoint { +- remote-endpoint = <&tcon1_in_drc1>; +- }; +- }; +- }; +- }; +- +- tcon0: lcd-controller@3c00000 { +- compatible = "allwinner,sun9i-a80-tcon-lcd"; +- reg = <0x03c00000 0x10000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>; +- clock-names = "ahb", "tcon-ch0"; +- resets = <&ccu RST_BUS_LCD0>, +- <&ccu RST_BUS_EDP>, +- <&ccu RST_BUS_LVDS>; +- reset-names = "lcd", +- "edp", +- "lvds"; +- clock-output-names = "tcon0-pixel-clock"; +- #clock-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon0_in: port@0 { +- reg = <0>; +- +- tcon0_in_drc0: endpoint { +- remote-endpoint = <&drc0_out_tcon0>; +- }; +- }; +- +- tcon0_out: port@1 { +- reg = <1>; +- }; +- }; +- }; +- +- tcon1: lcd-controller@3c10000 { +- compatible = "allwinner,sun9i-a80-tcon-tv"; +- reg = <0x03c10000 0x10000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>; +- clock-names = "ahb", "tcon-ch1"; +- resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>; +- reset-names = "lcd", "edp"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon1_in: port@0 { +- reg = <0>; +- +- tcon1_in_drc1: endpoint { +- remote-endpoint = <&drc1_out_tcon1>; +- }; +- }; +- +- tcon1_out: port@1 { +- reg = <1>; +- }; +- }; +- }; +- +- ccu: clock@6000000 { +- compatible = "allwinner,sun9i-a80-ccu"; +- reg = <0x06000000 0x800>; +- clocks = <&osc24M>, <&osc32k>; +- clock-names = "hosc", "losc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- timer@6000c00 { +- compatible = "allwinner,sun4i-a10-timer"; +- reg = <0x06000c00 0xa0>; +- interrupts = , +- , +- , +- , +- , +- ; +- +- clocks = <&osc24M>; +- }; +- +- wdt: watchdog@6000ca0 { +- compatible = "allwinner,sun6i-a31-wdt"; +- reg = <0x06000ca0 0x20>; +- interrupts = ; +- clocks = <&osc24M>; +- }; +- +- pio: pinctrl@6000800 { +- compatible = "allwinner,sun9i-a80-pinctrl"; +- reg = <0x06000800 0x400>; +- interrupts = , +- , +- , +- , +- ; +- clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; +- clock-names = "apb", "hosc", "losc"; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <3>; +- #gpio-cells = <3>; +- +- gmac_rgmii_pins: gmac-rgmii-pins { +- pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", +- "PA7", "PA8", "PA9", "PA10", "PA12", +- "PA13", "PA15", "PA16", "PA17"; +- function = "gmac"; +- /* +- * data lines in RGMII mode use DDR mode +- * and need a higher signal drive strength +- */ +- drive-strength = <40>; +- }; +- +- i2c3_pins: i2c3-pins { +- pins = "PG10", "PG11"; +- function = "i2c3"; +- }; +- +- lcd0_rgb888_pins: lcd0-rgb888-pins { +- pins = "PD0", "PD1", "PD2", "PD3", +- "PD4", "PD5", "PD6", "PD7", +- "PD8", "PD9", "PD10", "PD11", +- "PD12", "PD13", "PD14", "PD15", +- "PD16", "PD17", "PD18", "PD19", +- "PD20", "PD21", "PD22", "PD23", +- "PD24", "PD25", "PD26", "PD27"; +- function = "lcd0"; +- }; +- +- mmc0_pins: mmc0-pins { +- pins = "PF0", "PF1" ,"PF2", "PF3", +- "PF4", "PF5"; +- function = "mmc0"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc1_pins: mmc1-pins { +- pins = "PG0", "PG1" ,"PG2", "PG3", +- "PG4", "PG5"; +- function = "mmc1"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc2_8bit_pins: mmc2-8bit-pins { +- pins = "PC6", "PC7", "PC8", "PC9", +- "PC10", "PC11", "PC12", +- "PC13", "PC14", "PC15", +- "PC16"; +- function = "mmc2"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- uart0_ph_pins: uart0-ph-pins { +- pins = "PH12", "PH13"; +- function = "uart0"; +- }; +- +- uart4_pins: uart4-pins { +- pins = "PG12", "PG13", "PG14", "PG15"; +- function = "uart4"; +- }; +- }; +- +- uart0: serial@7000000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x07000000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART0>; +- resets = <&ccu RST_BUS_UART0>; +- status = "disabled"; +- }; +- +- uart1: serial@7000400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x07000400 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART1>; +- resets = <&ccu RST_BUS_UART1>; +- status = "disabled"; +- }; +- +- uart2: serial@7000800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x07000800 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART2>; +- resets = <&ccu RST_BUS_UART2>; +- status = "disabled"; +- }; +- +- uart3: serial@7000c00 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x07000c00 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART3>; +- resets = <&ccu RST_BUS_UART3>; +- status = "disabled"; +- }; +- +- uart4: serial@7001000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x07001000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART4>; +- resets = <&ccu RST_BUS_UART4>; +- status = "disabled"; +- }; +- +- uart5: serial@7001400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x07001400 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART5>; +- resets = <&ccu RST_BUS_UART5>; +- status = "disabled"; +- }; +- +- i2c0: i2c@7002800 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x07002800 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C0>; +- resets = <&ccu RST_BUS_I2C0>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c1: i2c@7002c00 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x07002c00 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C1>; +- resets = <&ccu RST_BUS_I2C1>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c2: i2c@7003000 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x07003000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C2>; +- resets = <&ccu RST_BUS_I2C2>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c3: i2c@7003400 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x07003400 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C3>; +- resets = <&ccu RST_BUS_I2C3>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c4: i2c@7003800 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x07003800 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C4>; +- resets = <&ccu RST_BUS_I2C4>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- r_wdt: watchdog@8001000 { +- compatible = "allwinner,sun6i-a31-wdt"; +- reg = <0x08001000 0x20>; +- interrupts = ; +- clocks = <&osc24M>; +- }; +- +- prcm@8001400 { +- compatible = "allwinner,sun9i-a80-prcm"; +- reg = <0x08001400 0x200>; +- }; +- +- apbs_rst: reset@80014b0 { +- reg = <0x080014b0 0x4>; +- compatible = "allwinner,sun6i-a31-clock-reset"; +- #reset-cells = <1>; +- }; +- +- nmi_intc: interrupt-controller@80015a0 { +- compatible = "allwinner,sun9i-a80-nmi"; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x080015a0 0xc>; +- interrupts = ; +- }; +- +- r_ir: ir@8002000 { +- compatible = "allwinner,sun6i-a31-ir"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&r_ir_pins>; +- clocks = <&apbs_gates 1>, <&r_ir_clk>; +- clock-names = "apb", "ir"; +- resets = <&apbs_rst 1>; +- reg = <0x08002000 0x40>; +- status = "disabled"; +- }; +- +- r_uart: serial@8002800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x08002800 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&apbs_gates 4>; +- resets = <&apbs_rst 4>; +- status = "disabled"; +- }; +- +- r_pio: pinctrl@8002c00 { +- compatible = "allwinner,sun9i-a80-r-pinctrl"; +- reg = <0x08002c00 0x400>; +- interrupts = , +- ; +- clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>; +- clock-names = "apb", "hosc", "losc"; +- resets = <&apbs_rst 0>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <3>; +- #gpio-cells = <3>; +- +- r_ir_pins: r-ir-pins { +- pins = "PL6"; +- function = "s_cir_rx"; +- }; +- +- r_rsb_pins: r-rsb-pins { +- pins = "PN0", "PN1"; +- function = "s_rsb"; +- drive-strength = <20>; +- bias-pull-up; +- }; +- }; +- +- r_rsb: rsb@8003400 { +- compatible = "allwinner,sun8i-a23-rsb"; +- reg = <0x08003400 0x400>; +- interrupts = ; +- clocks = <&apbs_gates 3>; +- clock-frequency = <3000000>; +- resets = <&apbs_rst 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&r_rsb_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/suniv-f1c100s-licheepi-nano.dts b/scripts/dtc/include-prefixes/arm/suniv-f1c100s-licheepi-nano.dts +deleted file mode 100644 +index a1154e6c7cb5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/suniv-f1c100s-licheepi-nano.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR X11) +-/* +- * Copyright 2018 Icenowy Zheng +- */ +- +-/dts-v1/; +-#include "suniv-f1c100s.dtsi" +- +-/ { +- model = "Lichee Pi Nano"; +- compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pe_pins>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/suniv-f1c100s.dtsi b/scripts/dtc/include-prefixes/arm/suniv-f1c100s.dtsi +deleted file mode 100644 +index 6100d3b75f61..000000000000 +--- a/scripts/dtc/include-prefixes/arm/suniv-f1c100s.dtsi ++++ /dev/null +@@ -1,144 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR X11) +-/* +- * Copyright 2018 Icenowy Zheng +- * Copyright 2018 Mesih Kilinc +- */ +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&intc>; +- +- clocks { +- osc24M: clk-24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "osc24M"; +- }; +- +- osc32k: clk-32k { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-output-names = "osc32k"; +- }; +- }; +- +- cpus { +- cpu { +- compatible = "arm,arm926ej-s"; +- device_type = "cpu"; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- sram-controller@1c00000 { +- compatible = "allwinner,suniv-f1c100s-system-control", +- "allwinner,sun4i-a10-system-control"; +- reg = <0x01c00000 0x30>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- sram_d: sram@10000 { +- compatible = "mmio-sram"; +- reg = <0x00010000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00010000 0x1000>; +- +- otg_sram: sram-section@0 { +- compatible = "allwinner,suniv-f1c100s-sram-d", +- "allwinner,sun4i-a10-sram-d"; +- reg = <0x0000 0x1000>; +- status = "disabled"; +- }; +- }; +- }; +- +- ccu: clock@1c20000 { +- compatible = "allwinner,suniv-f1c100s-ccu"; +- reg = <0x01c20000 0x400>; +- clocks = <&osc24M>, <&osc32k>; +- clock-names = "hosc", "losc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- intc: interrupt-controller@1c20400 { +- compatible = "allwinner,suniv-f1c100s-ic"; +- reg = <0x01c20400 0x400>; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- pio: pinctrl@1c20800 { +- compatible = "allwinner,suniv-f1c100s-pinctrl"; +- reg = <0x01c20800 0x400>; +- interrupts = <38>, <39>, <40>; +- clocks = <&ccu 37>, <&osc24M>, <&osc32k>; +- clock-names = "apb", "hosc", "losc"; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <3>; +- #gpio-cells = <3>; +- +- uart0_pe_pins: uart0-pe-pins { +- pins = "PE0", "PE1"; +- function = "uart0"; +- }; +- }; +- +- timer@1c20c00 { +- compatible = "allwinner,suniv-f1c100s-timer"; +- reg = <0x01c20c00 0x90>; +- interrupts = <13>; +- clocks = <&osc24M>; +- }; +- +- wdt: watchdog@1c20ca0 { +- compatible = "allwinner,suniv-f1c100s-wdt", +- "allwinner,sun4i-a10-wdt"; +- reg = <0x01c20ca0 0x20>; +- }; +- +- uart0: serial@1c25000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c25000 0x400>; +- interrupts = <1>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu 38>; +- resets = <&ccu 24>; +- status = "disabled"; +- }; +- +- uart1: serial@1c25400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c25400 0x400>; +- interrupts = <2>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu 39>; +- resets = <&ccu 25>; +- status = "disabled"; +- }; +- +- uart2: serial@1c25800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c25800 0x400>; +- interrupts = <3>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu 40>; +- resets = <&ccu 26>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sunxi-bananapi-m2-plus-v1.2.dtsi b/scripts/dtc/include-prefixes/arm/sunxi-bananapi-m2-plus-v1.2.dtsi +deleted file mode 100644 +index 235994a4a2eb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sunxi-bananapi-m2-plus-v1.2.dtsi ++++ /dev/null +@@ -1,42 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2018 Chen-Yu Tsai +- */ +- +-#include "sunxi-bananapi-m2-plus.dtsi" +- +-/ { +- /* +- * Bananapi M2+ v1.2 uses a GPIO line to change the effective +- * resistance on the CPU regulator's feedback pin. +- */ +- reg_vdd_cpux: vdd-cpux { +- compatible = "regulator-gpio"; +- regulator-name = "vdd-cpux"; +- regulator-type = "voltage"; +- regulator-boot-on; +- regulator-always-on; +- regulator-min-microvolt = <1108475>; +- regulator-max-microvolt = <1308475>; +- regulator-ramp-delay = <50>; /* 4ms */ +- gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */ +- gpios-states = <0x1>; +- states = <1108475 0>, <1308475 1>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_vdd_cpux>; +-}; +- +-&cpu1 { +- cpu-supply = <®_vdd_cpux>; +-}; +- +-&cpu2 { +- cpu-supply = <®_vdd_cpux>; +-}; +- +-&cpu3 { +- cpu-supply = <®_vdd_cpux>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sunxi-bananapi-m2-plus.dtsi b/scripts/dtc/include-prefixes/arm/sunxi-bananapi-m2-plus.dtsi +deleted file mode 100644 +index 7a6af54dd342..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sunxi-bananapi-m2-plus.dtsi ++++ /dev/null +@@ -1,243 +0,0 @@ +-/* +- * Copyright (C) 2016 Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "sunxi-common-regulators.dtsi" +- +-#include +-#include +- +-/ { +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pwr_led { +- label = "bananapi-m2-plus:red:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ +- default-state = "on"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- sw4 { +- label = "power"; +- linux,code = ; +- gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- enable-active-high; +- gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ +- clocks = <&rtc 1>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_rgmii_pins>; +- phy-supply = <®_gmac_3v3>; +- phy-handle = <&ext_rgmii_phy>; +- phy-mode = "rgmii-id"; +- +- status = "okay"; +-}; +- +-&external_mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&ir { +- pinctrl-names = "default"; +- pinctrl-0 = <&r_ir_rx_pin>; +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- vqmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&pio>; +- interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_pins>; +- vmmc-supply = <®_vcc3v3>; +- vqmmc-supply = <®_vcc3v3>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-®_usb0_vbus { +- gpio = <&pio 3 11 GPIO_ACTIVE_HIGH>; /* PD11 */ +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- max-speed = <1500000>; +- clocks = <&rtc 1>; +- clock-names = "lpo"; +- vbat-supply = <®_vcc3v3>; +- vddio-supply = <®_vcc3v3>; +- device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ +- host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ +- shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +- }; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- /* USB host VBUS is on as long as VCC-IO is on */ +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sunxi-common-regulators.dtsi b/scripts/dtc/include-prefixes/arm/sunxi-common-regulators.dtsi +deleted file mode 100644 +index d8e5826fb3de..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sunxi-common-regulators.dtsi ++++ /dev/null +@@ -1,111 +0,0 @@ +-/* +- * sunxi boards common regulator (ahci target power supply, usb-vbus) code +- * +- * Copyright 2014 - Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +- +-/ { +- reg_ahci_5v: ahci-5v { +- compatible = "regulator-fixed"; +- regulator-name = "ahci-5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- enable-active-high; +- gpio = <&pio 1 8 GPIO_ACTIVE_HIGH>; +- status = "disabled"; +- }; +- +- reg_usb0_vbus: usb0-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb0-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&pio 1 9 GPIO_ACTIVE_HIGH>; +- status = "disabled"; +- }; +- +- reg_usb1_vbus: usb1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb1-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- enable-active-high; +- gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; +- status = "disabled"; +- }; +- +- reg_usb2_vbus: usb2-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb2-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- enable-active-high; +- gpio = <&pio 7 3 GPIO_ACTIVE_HIGH>; +- status = "disabled"; +- }; +- +- reg_vcc3v0: vcc3v0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v0"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- reg_vcc3v3: vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_vcc5v0: vcc5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sunxi-h3-h5-emlid-neutis.dtsi b/scripts/dtc/include-prefixes/arm/sunxi-h3-h5-emlid-neutis.dtsi +deleted file mode 100644 +index fc67e30fe212..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sunxi-h3-h5-emlid-neutis.dtsi ++++ /dev/null +@@ -1,170 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-/* +- * DTSI for Emlid Neutis SoMs. +- * +- * Copyright (C) 2019 Georgii Staroselskii +- */ +- +-#include "sunxi-common-regulators.dtsi" +- +-#include +- +-/ { +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */ +- post-power-on-delay-ms = <200>; +- clocks = <&rtc 1>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_cpux>; +-}; +- +-®_usb0_vbus { +- gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ +- status = "okay"; +-}; +- +- +-&de { +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-&ohci3 { +- status = "okay"; +-}; +- +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&ehci3 { +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- vqmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&r_pio>; +- interrupts = <0 5 IRQ_TYPE_LEVEL_LOW>; /* PL5 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_pins>; +- vmmc-supply = <®_vcc3v3>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&rtc 1>; +- clock-names = "lpo"; +- vbat-supply = <®_vcc3v3>; +- vddio-supply = <®_vcc3v3>; +- shutdown-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */ +- device-wakeup-gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ +- }; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&codec { +- allwinner,audio-routing = +- "Line Out", "LINEOUT", +- "LINEIN", "Line In", +- "MIC1", "Mic", +- "MIC2", "Mic", +- "Mic", "MBIAS"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sunxi-h3-h5.dtsi b/scripts/dtc/include-prefixes/arm/sunxi-h3-h5.dtsi +deleted file mode 100644 +index c7428df9469e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sunxi-h3-h5.dtsi ++++ /dev/null +@@ -1,949 +0,0 @@ +-/* +- * Copyright (C) 2015 Jens Kuske +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- chosen { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- framebuffer-hdmi { +- compatible = "allwinner,simple-framebuffer", +- "simple-framebuffer"; +- allwinner,pipeline = "mixer0-lcd0-hdmi"; +- clocks = <&display_clocks CLK_MIXER0>, +- <&ccu CLK_TCON0>, <&ccu CLK_HDMI>; +- status = "disabled"; +- }; +- +- framebuffer-tve { +- compatible = "allwinner,simple-framebuffer", +- "simple-framebuffer"; +- allwinner,pipeline = "mixer1-lcd1-tve"; +- clocks = <&display_clocks CLK_MIXER1>, +- <&ccu CLK_TVE>; +- status = "disabled"; +- }; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- osc24M: osc24M_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-accuracy = <50000>; +- clock-output-names = "osc24M"; +- }; +- +- osc32k: osc32k_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-accuracy = <50000>; +- clock-output-names = "ext_osc32k"; +- }; +- }; +- +- de: display-engine { +- compatible = "allwinner,sun8i-h3-display-engine"; +- allwinner,pipelines = <&mixer0>; +- status = "disabled"; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- dma-ranges; +- ranges; +- +- display_clocks: clock@1000000 { +- /* compatible is in per SoC .dtsi file */ +- reg = <0x01000000 0x10000>; +- clocks = <&ccu CLK_BUS_DE>, +- <&ccu CLK_DE>; +- clock-names = "bus", +- "mod"; +- resets = <&ccu RST_BUS_DE>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- mixer0: mixer@1100000 { +- compatible = "allwinner,sun8i-h3-de2-mixer-0"; +- reg = <0x01100000 0x100000>; +- clocks = <&display_clocks CLK_BUS_MIXER0>, +- <&display_clocks CLK_MIXER0>; +- clock-names = "bus", +- "mod"; +- resets = <&display_clocks RST_MIXER0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mixer0_out: port@1 { +- reg = <1>; +- +- mixer0_out_tcon0: endpoint { +- remote-endpoint = <&tcon0_in_mixer0>; +- }; +- }; +- }; +- }; +- +- dma: dma-controller@1c02000 { +- compatible = "allwinner,sun8i-h3-dma"; +- reg = <0x01c02000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_DMA>; +- resets = <&ccu RST_BUS_DMA>; +- #dma-cells = <1>; +- }; +- +- tcon0: lcd-controller@1c0c000 { +- compatible = "allwinner,sun8i-h3-tcon-tv", +- "allwinner,sun8i-a83t-tcon-tv"; +- reg = <0x01c0c000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; +- clock-names = "ahb", "tcon-ch1"; +- resets = <&ccu RST_BUS_TCON0>; +- reset-names = "lcd"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon0_in: port@0 { +- reg = <0>; +- +- tcon0_in_mixer0: endpoint { +- remote-endpoint = <&mixer0_out_tcon0>; +- }; +- }; +- +- tcon0_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tcon0_out_hdmi: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&hdmi_in_tcon0>; +- }; +- }; +- }; +- }; +- +- mmc0: mmc@1c0f000 { +- /* compatible and clocks are in per SoC .dtsi file */ +- reg = <0x01c0f000 0x1000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- resets = <&ccu RST_BUS_MMC0>; +- reset-names = "ahb"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc1: mmc@1c10000 { +- /* compatible and clocks are in per SoC .dtsi file */ +- reg = <0x01c10000 0x1000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- resets = <&ccu RST_BUS_MMC1>; +- reset-names = "ahb"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc2: mmc@1c11000 { +- /* compatible and clocks are in per SoC .dtsi file */ +- reg = <0x01c11000 0x1000>; +- resets = <&ccu RST_BUS_MMC2>; +- reset-names = "ahb"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- sid: eeprom@1c14000 { +- /* compatible is in per SoC .dtsi file */ +- reg = <0x1c14000 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ths_calibration: thermal-sensor-calibration@34 { +- reg = <0x34 4>; +- }; +- }; +- +- msgbox: mailbox@1c17000 { +- compatible = "allwinner,sun8i-h3-msgbox", +- "allwinner,sun6i-a31-msgbox"; +- reg = <0x01c17000 0x1000>; +- clocks = <&ccu CLK_BUS_MSGBOX>; +- resets = <&ccu RST_BUS_MSGBOX>; +- interrupts = ; +- #mbox-cells = <1>; +- }; +- +- usb_otg: usb@1c19000 { +- compatible = "allwinner,sun8i-h3-musb"; +- reg = <0x01c19000 0x400>; +- clocks = <&ccu CLK_BUS_OTG>; +- resets = <&ccu RST_BUS_OTG>; +- interrupts = ; +- interrupt-names = "mc"; +- phys = <&usbphy 0>; +- phy-names = "usb"; +- extcon = <&usbphy 0>; +- dr_mode = "otg"; +- status = "disabled"; +- }; +- +- usbphy: phy@1c19400 { +- compatible = "allwinner,sun8i-h3-usb-phy"; +- reg = <0x01c19400 0x2c>, +- <0x01c1a800 0x4>, +- <0x01c1b800 0x4>, +- <0x01c1c800 0x4>, +- <0x01c1d800 0x4>; +- reg-names = "phy_ctrl", +- "pmu0", +- "pmu1", +- "pmu2", +- "pmu3"; +- clocks = <&ccu CLK_USB_PHY0>, +- <&ccu CLK_USB_PHY1>, +- <&ccu CLK_USB_PHY2>, +- <&ccu CLK_USB_PHY3>; +- clock-names = "usb0_phy", +- "usb1_phy", +- "usb2_phy", +- "usb3_phy"; +- resets = <&ccu RST_USB_PHY0>, +- <&ccu RST_USB_PHY1>, +- <&ccu RST_USB_PHY2>, +- <&ccu RST_USB_PHY3>; +- reset-names = "usb0_reset", +- "usb1_reset", +- "usb2_reset", +- "usb3_reset"; +- status = "disabled"; +- #phy-cells = <1>; +- }; +- +- ehci0: usb@1c1a000 { +- compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; +- reg = <0x01c1a000 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; +- resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; +- status = "disabled"; +- }; +- +- ohci0: usb@1c1a400 { +- compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; +- reg = <0x01c1a400 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, +- <&ccu CLK_USB_OHCI0>; +- resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; +- status = "disabled"; +- }; +- +- ehci1: usb@1c1b000 { +- compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; +- reg = <0x01c1b000 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>; +- resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; +- phys = <&usbphy 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci1: usb@1c1b400 { +- compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; +- reg = <0x01c1b400 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>, +- <&ccu CLK_USB_OHCI1>; +- resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; +- phys = <&usbphy 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ehci2: usb@1c1c000 { +- compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; +- reg = <0x01c1c000 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>; +- resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; +- phys = <&usbphy 2>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci2: usb@1c1c400 { +- compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; +- reg = <0x01c1c400 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>, +- <&ccu CLK_USB_OHCI2>; +- resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; +- phys = <&usbphy 2>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ehci3: usb@1c1d000 { +- compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; +- reg = <0x01c1d000 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>; +- resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; +- phys = <&usbphy 3>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci3: usb@1c1d400 { +- compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; +- reg = <0x01c1d400 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>, +- <&ccu CLK_USB_OHCI3>; +- resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; +- phys = <&usbphy 3>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ccu: clock@1c20000 { +- /* compatible is in per SoC .dtsi file */ +- reg = <0x01c20000 0x400>; +- clocks = <&osc24M>, <&rtc 0>; +- clock-names = "hosc", "losc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pio: pinctrl@1c20800 { +- /* compatible is in per SoC .dtsi file */ +- reg = <0x01c20800 0x400>; +- interrupt-parent = <&r_intc>; +- interrupts = , +- ; +- clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; +- clock-names = "apb", "hosc", "losc"; +- gpio-controller; +- #gpio-cells = <3>; +- interrupt-controller; +- #interrupt-cells = <3>; +- +- csi_pins: csi-pins { +- pins = "PE0", "PE2", "PE3", "PE4", "PE5", +- "PE6", "PE7", "PE8", "PE9", "PE10", +- "PE11"; +- function = "csi"; +- }; +- +- emac_rgmii_pins: emac-rgmii-pins { +- pins = "PD0", "PD1", "PD2", "PD3", "PD4", +- "PD5", "PD7", "PD8", "PD9", "PD10", +- "PD12", "PD13", "PD15", "PD16", "PD17"; +- function = "emac"; +- drive-strength = <40>; +- }; +- +- i2c0_pins: i2c0-pins { +- pins = "PA11", "PA12"; +- function = "i2c0"; +- }; +- +- i2c1_pins: i2c1-pins { +- pins = "PA18", "PA19"; +- function = "i2c1"; +- }; +- +- i2c2_pins: i2c2-pins { +- pins = "PE12", "PE13"; +- function = "i2c2"; +- }; +- +- mmc0_pins: mmc0-pins { +- pins = "PF0", "PF1", "PF2", "PF3", +- "PF4", "PF5"; +- function = "mmc0"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc1_pins: mmc1-pins { +- pins = "PG0", "PG1", "PG2", "PG3", +- "PG4", "PG5"; +- function = "mmc1"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc2_8bit_pins: mmc2-8bit-pins { +- pins = "PC5", "PC6", "PC8", +- "PC9", "PC10", "PC11", +- "PC12", "PC13", "PC14", +- "PC15", "PC16"; +- function = "mmc2"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- spdif_tx_pin: spdif-tx-pin { +- pins = "PA17"; +- function = "spdif"; +- }; +- +- spi0_pins: spi0-pins { +- pins = "PC0", "PC1", "PC2", "PC3"; +- function = "spi0"; +- }; +- +- spi1_pins: spi1-pins { +- pins = "PA15", "PA16", "PA14", "PA13"; +- function = "spi1"; +- }; +- +- uart0_pa_pins: uart0-pa-pins { +- pins = "PA4", "PA5"; +- function = "uart0"; +- }; +- +- uart1_pins: uart1-pins { +- pins = "PG6", "PG7"; +- function = "uart1"; +- }; +- +- uart1_rts_cts_pins: uart1-rts-cts-pins { +- pins = "PG8", "PG9"; +- function = "uart1"; +- }; +- +- uart2_pins: uart2-pins { +- pins = "PA0", "PA1"; +- function = "uart2"; +- }; +- +- uart2_rts_cts_pins: uart2-rts-cts-pins { +- pins = "PA2", "PA3"; +- function = "uart2"; +- }; +- +- uart3_pins: uart3-pins { +- pins = "PA13", "PA14"; +- function = "uart3"; +- }; +- +- uart3_rts_cts_pins: uart3-rts-cts-pins { +- pins = "PA15", "PA16"; +- function = "uart3"; +- }; +- }; +- +- timer@1c20c00 { +- compatible = "allwinner,sun8i-a23-timer"; +- reg = <0x01c20c00 0xa0>; +- interrupts = , +- ; +- clocks = <&osc24M>; +- }; +- +- emac: ethernet@1c30000 { +- compatible = "allwinner,sun8i-h3-emac"; +- syscon = <&syscon>; +- reg = <0x01c30000 0x10000>; +- interrupts = ; +- interrupt-names = "macirq"; +- resets = <&ccu RST_BUS_EMAC>; +- reset-names = "stmmaceth"; +- clocks = <&ccu CLK_BUS_EMAC>; +- clock-names = "stmmaceth"; +- status = "disabled"; +- +- mdio: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- }; +- +- mdio-mux { +- compatible = "allwinner,sun8i-h3-mdio-mux"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- mdio-parent-bus = <&mdio>; +- /* Only one MDIO is usable at the time */ +- internal_mdio: mdio@1 { +- compatible = "allwinner,sun8i-h3-mdio-internal"; +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- int_mii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- clocks = <&ccu CLK_BUS_EPHY>; +- resets = <&ccu RST_BUS_EPHY>; +- }; +- }; +- +- external_mdio: mdio@2 { +- reg = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- }; +- +- mbus: dram-controller@1c62000 { +- compatible = "allwinner,sun8i-h3-mbus"; +- reg = <0x01c62000 0x1000>; +- clocks = <&ccu CLK_MBUS>; +- #address-cells = <1>; +- #size-cells = <1>; +- dma-ranges = <0x00000000 0x40000000 0xc0000000>; +- #interconnect-cells = <1>; +- }; +- +- spi0: spi@1c68000 { +- compatible = "allwinner,sun8i-h3-spi"; +- reg = <0x01c68000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; +- clock-names = "ahb", "mod"; +- dmas = <&dma 23>, <&dma 23>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins>; +- resets = <&ccu RST_BUS_SPI0>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spi1: spi@1c69000 { +- compatible = "allwinner,sun8i-h3-spi"; +- reg = <0x01c69000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; +- clock-names = "ahb", "mod"; +- dmas = <&dma 24>, <&dma 24>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins>; +- resets = <&ccu RST_BUS_SPI1>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- wdt0: watchdog@1c20ca0 { +- compatible = "allwinner,sun6i-a31-wdt"; +- reg = <0x01c20ca0 0x20>; +- interrupts = ; +- clocks = <&osc24M>; +- }; +- +- spdif: spdif@1c21000 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun8i-h3-spdif"; +- reg = <0x01c21000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; +- resets = <&ccu RST_BUS_SPDIF>; +- clock-names = "apb", "spdif"; +- dmas = <&dma 2>; +- dma-names = "tx"; +- status = "disabled"; +- }; +- +- pwm: pwm@1c21400 { +- compatible = "allwinner,sun8i-h3-pwm"; +- reg = <0x01c21400 0x8>; +- clocks = <&osc24M>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- i2s0: i2s@1c22000 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun8i-h3-i2s"; +- reg = <0x01c22000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; +- clock-names = "apb", "mod"; +- dmas = <&dma 3>, <&dma 3>; +- resets = <&ccu RST_BUS_I2S0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2s1: i2s@1c22400 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun8i-h3-i2s"; +- reg = <0x01c22400 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; +- clock-names = "apb", "mod"; +- dmas = <&dma 4>, <&dma 4>; +- resets = <&ccu RST_BUS_I2S1>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2s2: i2s@1c22800 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun8i-h3-i2s"; +- reg = <0x01c22800 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; +- clock-names = "apb", "mod"; +- dmas = <&dma 27>; +- resets = <&ccu RST_BUS_I2S2>; +- dma-names = "tx"; +- status = "disabled"; +- }; +- +- codec: codec@1c22c00 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun8i-h3-codec"; +- reg = <0x01c22c00 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; +- clock-names = "apb", "codec"; +- resets = <&ccu RST_BUS_CODEC>; +- dmas = <&dma 15>, <&dma 15>; +- dma-names = "rx", "tx"; +- allwinner,codec-analog-controls = <&codec_analog>; +- status = "disabled"; +- }; +- +- uart0: serial@1c28000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART0>; +- resets = <&ccu RST_BUS_UART0>; +- dmas = <&dma 6>, <&dma 6>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart1: serial@1c28400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28400 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART1>; +- resets = <&ccu RST_BUS_UART1>; +- dmas = <&dma 7>, <&dma 7>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart2: serial@1c28800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28800 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART2>; +- resets = <&ccu RST_BUS_UART2>; +- dmas = <&dma 8>, <&dma 8>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart3: serial@1c28c00 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28c00 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART3>; +- resets = <&ccu RST_BUS_UART3>; +- dmas = <&dma 9>, <&dma 9>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c0: i2c@1c2ac00 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2ac00 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C0>; +- resets = <&ccu RST_BUS_I2C0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c1: i2c@1c2b000 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2b000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C1>; +- resets = <&ccu RST_BUS_I2C1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c2: i2c@1c2b400 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2b400 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C2>; +- resets = <&ccu RST_BUS_I2C2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- gic: interrupt-controller@1c81000 { +- compatible = "arm,gic-400"; +- reg = <0x01c81000 0x1000>, +- <0x01c82000 0x2000>, +- <0x01c84000 0x2000>, +- <0x01c86000 0x2000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = ; +- }; +- +- csi: camera@1cb0000 { +- compatible = "allwinner,sun8i-h3-csi"; +- reg = <0x01cb0000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_CSI>, +- <&ccu CLK_CSI_SCLK>, +- <&ccu CLK_DRAM_CSI>; +- clock-names = "bus", "mod", "ram"; +- resets = <&ccu RST_BUS_CSI>; +- pinctrl-names = "default"; +- pinctrl-0 = <&csi_pins>; +- status = "disabled"; +- }; +- +- hdmi: hdmi@1ee0000 { +- compatible = "allwinner,sun8i-h3-dw-hdmi", +- "allwinner,sun8i-a83t-dw-hdmi"; +- reg = <0x01ee0000 0x10000>; +- reg-io-width = <1>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, +- <&ccu CLK_HDMI>; +- clock-names = "iahb", "isfr", "tmds"; +- resets = <&ccu RST_BUS_HDMI1>; +- reset-names = "ctrl"; +- phys = <&hdmi_phy>; +- phy-names = "phy"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- hdmi_in: port@0 { +- reg = <0>; +- +- hdmi_in_tcon0: endpoint { +- remote-endpoint = <&tcon0_out_hdmi>; +- }; +- }; +- +- hdmi_out: port@1 { +- reg = <1>; +- }; +- }; +- }; +- +- hdmi_phy: hdmi-phy@1ef0000 { +- compatible = "allwinner,sun8i-h3-hdmi-phy"; +- reg = <0x01ef0000 0x10000>; +- clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, +- <&ccu CLK_PLL_VIDEO>; +- clock-names = "bus", "mod", "pll-0"; +- resets = <&ccu RST_BUS_HDMI0>; +- reset-names = "phy"; +- #phy-cells = <0>; +- }; +- +- rtc: rtc@1f00000 { +- /* compatible is in per SoC .dtsi file */ +- reg = <0x01f00000 0x400>; +- interrupt-parent = <&r_intc>; +- interrupts = , +- ; +- clock-output-names = "osc32k", "osc32k-out", "iosc"; +- clocks = <&osc32k>; +- #clock-cells = <1>; +- }; +- +- r_intc: interrupt-controller@1f00c00 { +- compatible = "allwinner,sun8i-h3-r-intc", +- "allwinner,sun6i-a31-r-intc"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x01f00c00 0x400>; +- interrupts = ; +- }; +- +- r_ccu: clock@1f01400 { +- compatible = "allwinner,sun8i-h3-r-ccu"; +- reg = <0x01f01400 0x100>; +- clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, +- <&ccu CLK_PLL_PERIPH0>; +- clock-names = "hosc", "losc", "iosc", "pll-periph"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- codec_analog: codec-analog@1f015c0 { +- compatible = "allwinner,sun8i-h3-codec-analog"; +- reg = <0x01f015c0 0x4>; +- }; +- +- ir: ir@1f02000 { +- compatible = "allwinner,sun6i-a31-ir"; +- clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; +- clock-names = "apb", "ir"; +- resets = <&r_ccu RST_APB0_IR>; +- interrupts = ; +- reg = <0x01f02000 0x400>; +- status = "disabled"; +- }; +- +- r_i2c: i2c@1f02400 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01f02400 0x400>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&r_i2c_pins>; +- clocks = <&r_ccu CLK_APB0_I2C>; +- resets = <&r_ccu RST_APB0_I2C>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- r_pio: pinctrl@1f02c00 { +- compatible = "allwinner,sun8i-h3-r-pinctrl"; +- reg = <0x01f02c00 0x400>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>; +- clock-names = "apb", "hosc", "losc"; +- gpio-controller; +- #gpio-cells = <3>; +- interrupt-controller; +- #interrupt-cells = <3>; +- +- r_ir_rx_pin: r-ir-rx-pin { +- pins = "PL11"; +- function = "s_cir_rx"; +- }; +- +- r_i2c_pins: r-i2c-pins { +- pins = "PL0", "PL1"; +- function = "s_i2c"; +- }; +- +- r_pwm_pin: r-pwm-pin { +- pins = "PL10"; +- function = "s_pwm"; +- }; +- }; +- +- r_pwm: pwm@1f03800 { +- compatible = "allwinner,sun8i-h3-pwm"; +- reg = <0x01f03800 0x8>; +- pinctrl-names = "default"; +- pinctrl-0 = <&r_pwm_pin>; +- clocks = <&osc24M>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sunxi-itead-core-common.dtsi b/scripts/dtc/include-prefixes/arm/sunxi-itead-core-common.dtsi +deleted file mode 100644 +index 0d002f83a259..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sunxi-itead-core-common.dtsi ++++ /dev/null +@@ -1,132 +0,0 @@ +-/* +- * Copyright 2015 - Marcus Cooper +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "sunxi-common-regulators.dtsi" +- +-/ { +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- axp209: pmic@34 { +- reg = <0x34>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-#include "axp209.dtsi" +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-cpu"; +-}; +- +-®_dcdc3 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-name = "vdd-int-dll"; +-}; +- +-®_ldo1 { +- regulator-name = "vdd-rtc"; +-}; +- +-®_ldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "avcc"; +-}; +- +-®_usb1_vbus { +- status = "okay"; +-}; +- +-®_usb2_vbus { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_usb1_vbus>; +- usb2_vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sunxi-libretech-all-h3-cc.dtsi b/scripts/dtc/include-prefixes/arm/sunxi-libretech-all-h3-cc.dtsi +deleted file mode 100644 +index c44fd726945a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sunxi-libretech-all-h3-cc.dtsi ++++ /dev/null +@@ -1,236 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2017 Chen-Yu Tsai +- */ +- +-#include +-#include +- +-/ { +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pwr_led { +- label = "librecomputer:green:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ +- default-state = "on"; +- }; +- +- status_led { +- label = "librecomputer:blue:status"; +- gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- power { +- label = "power"; +- linux,code = ; +- gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ +- }; +- }; +- +- reg_vcc1v2: vcc1v2 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc1v2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <®_vcc5v0>; +- gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ +- enable-active-high; +- }; +- +- reg_vcc3v3: vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <®_vcc5v0>; +- }; +- +- /* This represents the board's 5V input */ +- reg_vcc5v0: vcc5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_vcc_dram: vcc-dram { +- compatible = "regulator-fixed"; +- regulator-name = "vcc-dram"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <®_vcc5v0>; +- gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ +- enable-active-high; +- }; +- +- reg_vcc_io: vcc-io { +- compatible = "regulator-fixed"; +- regulator-name = "vcc-io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <®_vcc3v3>; +- gpio = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */ +- }; +- +- reg_vdd_cpux: vdd-cpux { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-cpux"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <®_vcc5v0>; +- gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ +- enable-active-high; +- }; +-}; +- +-&codec { +- allwinner,audio-routing = +- "Line Out", "LINEOUT", +- "MIC1", "Mic", +- "Mic", "MBIAS"; +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_vdd_cpux>; +-}; +- +-&cpu1 { +- cpu-supply = <®_vdd_cpux>; +-}; +- +-&cpu2 { +- cpu-supply = <®_vdd_cpux>; +-}; +- +-&cpu3 { +- cpu-supply = <®_vdd_cpux>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&ehci3 { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&int_mii_phy>; +- phy-mode = "mii"; +- allwinner,leds-active-low; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&ir { +- pinctrl-names = "default"; +- pinctrl-0 = <&r_ir_rx_pin>; +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc_io>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_pins>; +- vmmc-supply = <®_vcc_io>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-&ohci3 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbphy { +- /* VBUS on USB ports are always on */ +- usb0_vbus-supply = <®_vcc5v0>; +- usb1_vbus-supply = <®_vcc5v0>; +- usb2_vbus-supply = <®_vcc5v0>; +- usb3_vbus-supply = <®_vcc5v0>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sunxi-libretech-all-h3-it.dtsi b/scripts/dtc/include-prefixes/arm/sunxi-libretech-all-h3-it.dtsi +deleted file mode 100644 +index 204fba3614f9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sunxi-libretech-all-h3-it.dtsi ++++ /dev/null +@@ -1,180 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2019 Chen-Yu Tsai +- +-#include +-#include +- +-/ { +- aliases { +- serial0 = &uart0; +- spi0 = &spi0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "d"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- status_led { +- label = "librecomputer:blue:status"; +- gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ +- }; +- }; +- +- reg_vcc3v3: vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <®_vcc5v0>; +- }; +- +- /* This represents the board's 5V input */ +- reg_vcc5v0: vcc5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_vcc_dram: vcc-dram { +- compatible = "regulator-fixed"; +- regulator-name = "vcc-dram"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <®_vcc5v0>; +- gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ +- enable-active-high; +- }; +- +- reg_vcc_io: vcc-io { +- compatible = "regulator-fixed"; +- regulator-name = "vcc-io"; +- /* This is simply a MOSFET switch */ +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <®_vcc3v3>; +- gpio = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */ +- }; +- +- reg_vcc_usbwifi: vcc-usbwifi { +- compatible = "regulator-fixed"; +- regulator-name = "vcc-usbwifi"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <®_vcc5v0>; +- gpio = <&pio 6 4 GPIO_ACTIVE_HIGH>; /* PG4 */ +- enable-active-high; +- }; +- +- reg_vdd_cpux: vdd-cpux { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-cpux"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <®_vcc5v0>; +- gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ +- enable-active-high; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_vdd_cpux>; +-}; +- +-&cpu1 { +- cpu-supply = <®_vdd_cpux>; +-}; +- +-&cpu2 { +- cpu-supply = <®_vdd_cpux>; +-}; +- +-&cpu3 { +- cpu-supply = <®_vdd_cpux>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc_io>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +-&pio { +- vcc-pa-supply = <®_vcc_io>; +- vcc-pc-supply = <®_vcc_io>; +- vcc-pd-supply = <®_vcc_io>; +- vcc-pe-supply = <®_vcc_io>; +- vcc-pf-supply = <®_vcc_io>; +- vcc-pg-supply = <®_vcc_io>; +-}; +- +-&r_pio { +- vcc-pl-supply = <®_vcc3v3>; +-}; +- +-&spi0 { +- status = "okay"; +- +- spiflash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_vcc_usbwifi>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/sunxi-reference-design-tablet.dtsi b/scripts/dtc/include-prefixes/arm/sunxi-reference-design-tablet.dtsi +deleted file mode 100644 +index 117198c52e1f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/sunxi-reference-design-tablet.dtsi ++++ /dev/null +@@ -1,82 +0,0 @@ +-/* +- * Copyright 2015 Hans de Goede +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include "sunxi-common-regulators.dtsi" +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "okay"; +-}; +- +-&lradc { +- vref-supply = <®_vcc3v0>; +- status = "okay"; +- +- button-200 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <200000>; +- }; +- +- button-400 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <400000>; +- }; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra114-dalmore.dts b/scripts/dtc/include-prefixes/arm/tegra114-dalmore.dts +deleted file mode 100644 +index 7fd901f8d39a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra114-dalmore.dts ++++ /dev/null +@@ -1,1286 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * This dts file supports Dalmore A04. +- * Other board revisions are not supported +- */ +- +-/dts-v1/; +- +-#include +-#include "tegra114.dtsi" +- +-/ { +- model = "NVIDIA Tegra114 Dalmore evaluation board"; +- compatible = "nvidia,dalmore", "nvidia,tegra114"; +- +- aliases { +- rtc0 = "/i2c@7000d000/tps65913@58"; +- rtc1 = "/rtc@7000e000"; +- serial0 = &uartd; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x40000000>; +- }; +- +- host1x@50000000 { +- hdmi@54280000 { +- status = "okay"; +- +- hdmi-supply = <&vdd_5v0_hdmi>; +- vdd-supply = <&vdd_hdmi_reg>; +- pll-supply = <&palmas_smps3_reg>; +- +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = +- <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; +- }; +- +- dsi@54300000 { +- status = "okay"; +- +- avdd-dsi-csi-supply = <&avdd_1v2_reg>; +- +- panel@0 { +- compatible = "panasonic,vvx10f004b00"; +- reg = <0>; +- +- power-supply = <&avdd_lcd_reg>; +- backlight = <&backlight>; +- }; +- }; +- }; +- +- pinmux@70000868 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- clk1_out_pw4 { +- nvidia,pins = "clk1_out_pw4"; +- nvidia,function = "extperiph1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_din_pn1 { +- nvidia,pins = "dap1_din_pn1"; +- nvidia,function = "i2s0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_dout_pn2 { +- nvidia,pins = "dap1_dout_pn2", +- "dap1_fs_pn0", +- "dap1_sclk_pn3"; +- nvidia,function = "i2s0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_din_pa4 { +- nvidia,pins = "dap2_din_pa4"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_dout_pa5 { +- nvidia,pins = "dap2_dout_pa5", +- "dap2_fs_pa2", +- "dap2_sclk_pa3"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_din_pp5 { +- nvidia,pins = "dap4_din_pp5", +- "dap4_dout_pp6", +- "dap4_fs_pp4", +- "dap4_sclk_pp7"; +- nvidia,function = "i2s3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dvfs_pwm_px0 { +- nvidia,pins = "dvfs_pwm_px0", +- "dvfs_clk_px2"; +- nvidia,function = "cldvfs"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_clk_py0 { +- nvidia,pins = "ulpi_clk_py0", +- "ulpi_data0_po1", +- "ulpi_data1_po2", +- "ulpi_data2_po3", +- "ulpi_data3_po4", +- "ulpi_data4_po5", +- "ulpi_data5_po6", +- "ulpi_data6_po7", +- "ulpi_data7_po0"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_dir_py1 { +- nvidia,pins = "ulpi_dir_py1", +- "ulpi_nxt_py2"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_stp_py3 { +- nvidia,pins = "ulpi_stp_py3"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cam_i2c_scl_pbb1 { +- nvidia,pins = "cam_i2c_scl_pbb1", +- "cam_i2c_sda_pbb2"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- cam_mclk_pcc0 { +- nvidia,pins = "cam_mclk_pcc0", +- "pbb0"; +- nvidia,function = "vi_alt3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- }; +- gen2_i2c_scl_pt5 { +- nvidia,pins = "gen2_i2c_scl_pt5", +- "gen2_i2c_sda_pt6"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- gmi_a16_pj7 { +- nvidia,pins = "gmi_a16_pj7"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_a17_pb0 { +- nvidia,pins = "gmi_a17_pb0", +- "gmi_a18_pb1"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_a19_pk7 { +- nvidia,pins = "gmi_a19_pk7"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad5_pg5 { +- nvidia,pins = "gmi_ad5_pg5", +- "gmi_cs6_n_pi3", +- "gmi_wr_n_pi0"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad6_pg6 { +- nvidia,pins = "gmi_ad6_pg6", +- "gmi_ad7_pg7"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad12_ph4 { +- nvidia,pins = "gmi_ad12_ph4"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad9_ph1 { +- nvidia,pins = "gmi_ad9_ph1"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_cs1_n_pj2 { +- nvidia,pins = "gmi_cs1_n_pj2", +- "gmi_oe_n_pi1"; +- nvidia,function = "soc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2_out_pw5 { +- nvidia,pins = "clk2_out_pw5"; +- nvidia,function = "extperiph2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_clk_pz0 { +- nvidia,pins = "sdmmc1_clk_pz0"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_cmd_pz1 { +- nvidia,pins = "sdmmc1_cmd_pz1", +- "sdmmc1_dat0_py7", +- "sdmmc1_dat1_py6", +- "sdmmc1_dat2_py5", +- "sdmmc1_dat3_py4"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_wp_n_pv3 { +- nvidia,pins = "sdmmc1_wp_n_pv3"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_clk_pa6 { +- nvidia,pins = "sdmmc3_clk_pa6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_cmd_pa7 { +- nvidia,pins = "sdmmc3_cmd_pa7", +- "sdmmc3_dat0_pb7", +- "sdmmc3_dat1_pb6", +- "sdmmc3_dat2_pb5", +- "sdmmc3_dat3_pb4", +- "kb_col4_pq4", +- "sdmmc3_clk_lb_out_pee4", +- "sdmmc3_clk_lb_in_pee5"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_clk_pcc4 { +- nvidia,pins = "sdmmc4_clk_pcc4"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_cmd_pt7 { +- nvidia,pins = "sdmmc4_cmd_pt7", +- "sdmmc4_dat0_paa0", +- "sdmmc4_dat1_paa1", +- "sdmmc4_dat2_paa2", +- "sdmmc4_dat3_paa3", +- "sdmmc4_dat4_paa4", +- "sdmmc4_dat5_paa5", +- "sdmmc4_dat6_paa6", +- "sdmmc4_dat7_paa7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk_32k_out_pa0 { +- nvidia,pins = "clk_32k_out_pa0"; +- nvidia,function = "blink"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col0_pq0 { +- nvidia,pins = "kb_col0_pq0", +- "kb_col1_pq1", +- "kb_col2_pq2", +- "kb_row0_pr0", +- "kb_row1_pr1", +- "kb_row2_pr2"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_din_pp1 { +- nvidia,pins = "dap3_din_pp1", +- "dap3_sclk_pp3"; +- nvidia,function = "displayb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv0 { +- nvidia,pins = "pv0"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row7_pr7 { +- nvidia,pins = "kb_row7_pr7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row10_ps2 { +- nvidia,pins = "kb_row10_ps2"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row9_ps1 { +- nvidia,pins = "kb_row9_ps1"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pwr_i2c_scl_pz6 { +- nvidia,pins = "pwr_i2c_scl_pz6", +- "pwr_i2c_sda_pz7"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- sys_clk_req_pz5 { +- nvidia,pins = "sys_clk_req_pz5"; +- nvidia,function = "sysclk"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- core_pwr_req { +- nvidia,pins = "core_pwr_req"; +- nvidia,function = "pwron"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cpu_pwr_req { +- nvidia,pins = "cpu_pwr_req"; +- nvidia,function = "cpu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pwr_int_n { +- nvidia,pins = "pwr_int_n"; +- nvidia,function = "pmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- reset_out_n { +- nvidia,pins = "reset_out_n"; +- nvidia,function = "reset_out_n"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3_out_pee0 { +- nvidia,pins = "clk3_out_pee0"; +- nvidia,function = "extperiph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gen1_i2c_scl_pc4 { +- nvidia,pins = "gen1_i2c_scl_pc4", +- "gen1_i2c_sda_pc5"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- uart2_cts_n_pj5 { +- nvidia,pins = "uart2_cts_n_pj5"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_rts_n_pj6 { +- nvidia,pins = "uart2_rts_n_pj6"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_rxd_pc3 { +- nvidia,pins = "uart2_rxd_pc3"; +- nvidia,function = "irda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_txd_pc2 { +- nvidia,pins = "uart2_txd_pc2"; +- nvidia,function = "irda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_cts_n_pa1 { +- nvidia,pins = "uart3_cts_n_pa1", +- "uart3_rxd_pw7"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_rts_n_pc0 { +- nvidia,pins = "uart3_rts_n_pc0", +- "uart3_txd_pw6"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- owr { +- nvidia,pins = "owr"; +- nvidia,function = "owr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- hdmi_cec_pee3 { +- nvidia,pins = "hdmi_cec_pee3"; +- nvidia,function = "cec"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- ddc_scl_pv4 { +- nvidia,pins = "ddc_scl_pv4", +- "ddc_sda_pv5"; +- nvidia,function = "i2c4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,rcv-sel = ; +- }; +- spdif_in_pk6 { +- nvidia,pins = "spdif_in_pk6"; +- nvidia,function = "usb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- }; +- usb_vbus_en0_pn4 { +- nvidia,pins = "usb_vbus_en0_pn4"; +- nvidia,function = "usb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- gpio_x6_aud_px6 { +- nvidia,pins = "gpio_x6_aud_px6"; +- nvidia,function = "spi6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x4_aud_px4 { +- nvidia,pins = "gpio_x4_aud_px4", +- "gpio_x7_aud_px7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x5_aud_px5 { +- nvidia,pins = "gpio_x5_aud_px5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_w2_aud_pw2 { +- nvidia,pins = "gpio_w2_aud_pw2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_w3_aud_pw3 { +- nvidia,pins = "gpio_w3_aud_pw3"; +- nvidia,function = "spi6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x1_aud_px1 { +- nvidia,pins = "gpio_x1_aud_px1"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x3_aud_px3 { +- nvidia,pins = "gpio_x3_aud_px3"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_fs_pp0 { +- nvidia,pins = "dap3_fs_pp0"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_dout_pp2 { +- nvidia,pins = "dap3_dout_pp2"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv1 { +- nvidia,pins = "pv1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb3 { +- nvidia,pins = "pbb3", +- "pbb5", +- "pbb6", +- "pbb7"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pcc1 { +- nvidia,pins = "pcc1", +- "pcc2"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad0_pg0 { +- nvidia,pins = "gmi_ad0_pg0", +- "gmi_ad1_pg1"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad10_ph2 { +- nvidia,pins = "gmi_ad10_ph2", +- "gmi_ad11_ph3", +- "gmi_ad13_ph5", +- "gmi_ad8_ph0", +- "gmi_clk_pk1"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad2_pg2 { +- nvidia,pins = "gmi_ad2_pg2", +- "gmi_ad3_pg3"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_adv_n_pk0 { +- nvidia,pins = "gmi_adv_n_pk0", +- "gmi_cs0_n_pj0", +- "gmi_cs2_n_pk3", +- "gmi_cs4_n_pk2", +- "gmi_cs7_n_pi6", +- "gmi_dqs_p_pj3", +- "gmi_iordy_pi5", +- "gmi_wp_n_pc7"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_cs3_n_pk4 { +- nvidia,pins = "gmi_cs3_n_pk4"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2_req_pcc5 { +- nvidia,pins = "clk2_req_pcc5"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col3_pq3 { +- nvidia,pins = "kb_col3_pq3", +- "kb_col6_pq6", +- "kb_col7_pq7"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col5_pq5 { +- nvidia,pins = "kb_col5_pq5"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row3_pr3 { +- nvidia,pins = "kb_row3_pr3", +- "kb_row4_pr4", +- "kb_row6_pr6", +- "kb_row8_ps0"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3_req_pee1 { +- nvidia,pins = "clk3_req_pee1"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu4 { +- nvidia,pins = "pu4"; +- nvidia,function = "displayb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu5 { +- nvidia,pins = "pu5", +- "pu6"; +- nvidia,function = "displayb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- hdmi_int_pn7 { +- nvidia,pins = "hdmi_int_pn7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk1_req_pee2 { +- nvidia,pins = "clk1_req_pee2", +- "usb_vbus_en1_pn5"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- drive_sdio1 { +- nvidia,pins = "drive_sdio1"; +- nvidia,high-speed-mode = ; +- nvidia,schmitt = ; +- nvidia,pull-down-strength = <36>; +- nvidia,pull-up-strength = <20>; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- }; +- drive_sdio3 { +- nvidia,pins = "drive_sdio3"; +- nvidia,high-speed-mode = ; +- nvidia,schmitt = ; +- nvidia,pull-down-strength = <22>; +- nvidia,pull-up-strength = <36>; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- }; +- drive_gma { +- nvidia,pins = "drive_gma"; +- nvidia,high-speed-mode = ; +- nvidia,schmitt = ; +- nvidia,pull-down-strength = <2>; +- nvidia,pull-up-strength = <1>; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- }; +- }; +- }; +- +- serial@70006300 { +- status = "okay"; +- }; +- +- pwm@7000a000 { +- status = "okay"; +- }; +- +- i2c@7000c000 { +- status = "okay"; +- clock-frequency = <100000>; +- +- battery: smart-battery@b { +- compatible = "ti,bq20z45", "sbs,sbs-battery"; +- reg = <0xb>; +- sbs,i2c-retry-count = <2>; +- sbs,poll-retry-count = <100>; +- power-supplies = <&charger>; +- }; +- +- rt5640: rt5640@1c { +- compatible = "realtek,rt5640"; +- reg = <0x1c>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- realtek,ldo1-en-gpios = +- <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; +- }; +- +- temperature-sensor@4c { +- compatible = "onnn,nct1008"; +- reg = <0x4c>; +- vcc-supply = <&palmas_ldo6_reg>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- }; +- }; +- +- hdmi_ddc: i2c@7000c700 { +- status = "okay"; +- }; +- +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- tps51632@43 { +- compatible = "ti,tps51632"; +- reg = <0x43>; +- regulator-name = "vdd-cpu"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1520000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- tps65090@48 { +- compatible = "ti,tps65090"; +- reg = <0x48>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- vsys1-supply = <&vdd_ac_bat_reg>; +- vsys2-supply = <&vdd_ac_bat_reg>; +- vsys3-supply = <&vdd_ac_bat_reg>; +- infet1-supply = <&vdd_ac_bat_reg>; +- infet2-supply = <&vdd_ac_bat_reg>; +- infet3-supply = <&tps65090_dcdc2_reg>; +- infet4-supply = <&tps65090_dcdc2_reg>; +- infet5-supply = <&tps65090_dcdc2_reg>; +- infet6-supply = <&tps65090_dcdc2_reg>; +- infet7-supply = <&tps65090_dcdc2_reg>; +- vsys-l1-supply = <&vdd_ac_bat_reg>; +- vsys-l2-supply = <&vdd_ac_bat_reg>; +- +- charger: charger { +- compatible = "ti,tps65090-charger"; +- ti,enable-low-current-chrg; +- }; +- +- regulators { +- tps65090_dcdc1_reg: dcdc1 { +- regulator-name = "vdd-sys-5v0"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- tps65090_dcdc2_reg: dcdc2 { +- regulator-name = "vdd-sys-3v3"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- tps65090_dcdc3_reg: dcdc3 { +- regulator-name = "vdd-ao"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_bl_reg: fet1 { +- regulator-name = "vdd-lcd-bl"; +- }; +- +- fet3 { +- regulator-name = "vdd-modem-3v3"; +- }; +- +- avdd_lcd_reg: fet4 { +- regulator-name = "avdd-lcd"; +- }; +- +- fet5 { +- regulator-name = "vdd-lvds"; +- }; +- +- fet6 { +- regulator-name = "vdd-sd-slot"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- fet7 { +- regulator-name = "vdd-com-3v3"; +- }; +- +- ldo1 { +- regulator-name = "vdd-sby-5v0"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo2 { +- regulator-name = "vdd-sby-3v3"; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +- +- palmas: tps65913@58 { +- compatible = "ti,palmas"; +- reg = <0x58>; +- interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; +- +- #interrupt-cells = <2>; +- interrupt-controller; +- +- ti,system-power-controller; +- +- palmas_gpio: gpio { +- compatible = "ti,palmas-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- pmic { +- compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; +- smps1-in-supply = <&tps65090_dcdc3_reg>; +- smps3-in-supply = <&tps65090_dcdc3_reg>; +- smps4-in-supply = <&tps65090_dcdc2_reg>; +- smps7-in-supply = <&tps65090_dcdc2_reg>; +- smps8-in-supply = <&tps65090_dcdc2_reg>; +- smps9-in-supply = <&tps65090_dcdc2_reg>; +- ldo1-in-supply = <&tps65090_dcdc2_reg>; +- ldo2-in-supply = <&tps65090_dcdc2_reg>; +- ldo3-in-supply = <&palmas_smps3_reg>; +- ldo4-in-supply = <&tps65090_dcdc2_reg>; +- ldo5-in-supply = <&vdd_ac_bat_reg>; +- ldo6-in-supply = <&tps65090_dcdc2_reg>; +- ldo7-in-supply = <&tps65090_dcdc2_reg>; +- ldo8-in-supply = <&tps65090_dcdc3_reg>; +- ldo9-in-supply = <&palmas_smps9_reg>; +- ldoln-in-supply = <&tps65090_dcdc1_reg>; +- ldousb-in-supply = <&tps65090_dcdc1_reg>; +- +- regulators { +- smps12 { +- regulator-name = "vddio-ddr"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- palmas_smps3_reg: smps3 { +- regulator-name = "vddio-1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps45 { +- regulator-name = "vdd-core"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps457 { +- regulator-name = "vdd-core"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps8 { +- regulator-name = "avdd-pll"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- palmas_smps9_reg: smps9 { +- regulator-name = "sdhci-vdd-sd-slot"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- ldo1 { +- regulator-name = "avdd-cam1"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo2 { +- regulator-name = "avdd-cam2"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- avdd_1v2_reg: ldo3 { +- regulator-name = "avdd-dsi-csi"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo4 { +- regulator-name = "vpp-fuse"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- palmas_ldo6_reg: ldo6 { +- regulator-name = "vdd-sensor-2v85"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- ldo7 { +- regulator-name = "vdd-af-cam1"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo8 { +- regulator-name = "vdd-rtc"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-always-on; +- regulator-boot-on; +- ti,enable-ldo8-tracking; +- }; +- +- ldo9 { +- regulator-name = "vddio-sdmmc-2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldoln { +- regulator-name = "hvdd-usb"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldousb { +- regulator-name = "avdd-usb"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- regen1 { +- regulator-name = "rail-3v3"; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- regen2 { +- regulator-name = "rail-5v0"; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +- +- rtc { +- compatible = "ti,palmas-rtc"; +- interrupt-parent = <&palmas>; +- interrupts = <8 0>; +- }; +- +- pinmux { +- compatible = "ti,tps65913-pinctrl"; +- pinctrl-names = "default"; +- pinctrl-0 = <&palmas_default>; +- +- palmas_default: pinmux { +- pin_gpio6 { +- pins = "gpio6"; +- function = "gpio"; +- }; +- }; +- }; +- }; +- }; +- +- spi@7000da00 { +- status = "okay"; +- spi-max-frequency = <25000000>; +- spi-flash@0 { +- compatible = "winbond,w25q32dw", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- }; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <500>; +- nvidia,cpu-pwr-off-time = <300>; +- nvidia,core-pwr-good-time = <641 3845>; +- nvidia,core-pwr-off-time = <61036>; +- nvidia,core-power-req-active-high; +- nvidia,sys-clock-req-active-high; +- }; +- +- ahub@70080000 { +- i2s@70080400 { +- status = "okay"; +- }; +- }; +- +- mmc@78000400 { +- cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; +- bus-width = <4>; +- status = "okay"; +- }; +- +- mmc@78000600 { +- bus-width = <8>; +- status = "okay"; +- non-removable; +- }; +- +- usb@7d000000 { +- compatible = "nvidia,tegra114-udc"; +- status = "okay"; +- dr_mode = "peripheral"; +- }; +- +- usb-phy@7d000000 { +- status = "okay"; +- }; +- +- usb@7d008000 { +- status = "okay"; +- }; +- +- usb-phy@7d008000 { +- status = "okay"; +- vbus-supply = <&usb3_vbus_reg>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- +- enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; +- power-supply = <&vdd_bl_reg>; +- pwms = <&pwm 1 1000000>; +- +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- home { +- label = "Home"; +- gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- power { +- label = "Power"; +- gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- volume_down { +- label = "Volume Down"; +- gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- volume_up { +- label = "Volume Up"; +- gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- vdd_ac_bat_reg: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_ac_bat"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- dvdd_ts_reg: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "dvdd_ts"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; +- }; +- +- usb1_vbus_reg: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "usb1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; +- gpio-open-drain; +- vin-supply = <&tps65090_dcdc1_reg>; +- }; +- +- usb3_vbus_reg: regulator@4 { +- compatible = "regulator-fixed"; +- regulator-name = "usb2_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; +- gpio-open-drain; +- vin-supply = <&tps65090_dcdc1_reg>; +- }; +- +- vdd_hdmi_reg: regulator@5 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_hdmi_5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&tps65090_dcdc1_reg>; +- }; +- +- vdd_cam_1v8_reg: regulator@6 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_cam_1v8_reg"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- enable-active-high; +- gpio = <&palmas_gpio 6 0>; +- }; +- +- vdd_5v0_hdmi: regulator@7 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_5V0_HDMI_CON"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&tps65090_dcdc1_reg>; +- }; +- +- sound { +- compatible = "nvidia,tegra-audio-rt5640-dalmore", +- "nvidia,tegra-audio-rt5640"; +- nvidia,model = "NVIDIA Tegra Dalmore"; +- +- nvidia,audio-routing = +- "Headphones", "HPOR", +- "Headphones", "HPOL", +- "Speakers", "SPORP", +- "Speakers", "SPORN", +- "Speakers", "SPOLP", +- "Speakers", "SPOLN", +- "Mic Jack", "MICBIAS1", +- "IN2P", "Mic Jack"; +- +- nvidia,i2s-controller = <&tegra_i2s1>; +- nvidia,audio-codec = <&rt5640>; +- +- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; +- +- clocks = <&tegra_car TEGRA114_CLK_PLL_A>, +- <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- +- assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- +- assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA114_CLK_EXTERN1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra114-roth.dts b/scripts/dtc/include-prefixes/arm/tegra114-roth.dts +deleted file mode 100644 +index 07960171fabe..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra114-roth.dts ++++ /dev/null +@@ -1,1108 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include "tegra114.dtsi" +- +-/ { +- model = "NVIDIA SHIELD"; +- compatible = "nvidia,roth", "nvidia,tegra114"; +- +- chosen { +- /* SHIELD's bootloader's arguments need to be overridden */ +- bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:1"; +- /* SHIELD's bootloader will place initrd at this address */ +- linux,initrd-start = <0x82000000>; +- linux,initrd-end = <0x82800000>; +- }; +- +- aliases { +- serial0 = &uartd; +- }; +- +- firmware { +- trusted-foundations { +- compatible = "tlm,trusted-foundations"; +- tlm,version-major = <2>; +- tlm,version-minor = <8>; +- }; +- }; +- +- memory@80000000 { +- /* memory >= 0x79600000 is reserved for firmware usage */ +- reg = <0x80000000 0x79600000>; +- }; +- +- host1x@50000000 { +- dsi@54300000 { +- status = "okay"; +- +- avdd-dsi-csi-supply = <&vdd_1v2_ap>; +- +- panel@0 { +- compatible = "lg,lh500wx1-sd03"; +- reg = <0>; +- +- power-supply = <&vdd_lcd>; +- backlight = <&backlight>; +- }; +- }; +- }; +- +- pinmux@70000868 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- clk1_out_pw4 { +- nvidia,pins = "clk1_out_pw4"; +- nvidia,function = "extperiph1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_din_pn1 { +- nvidia,pins = "dap1_din_pn1"; +- nvidia,function = "i2s0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_dout_pn2 { +- nvidia,pins = "dap1_dout_pn2", +- "dap1_fs_pn0", +- "dap1_sclk_pn3"; +- nvidia,function = "i2s0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_din_pa4 { +- nvidia,pins = "dap2_din_pa4"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_dout_pa5 { +- nvidia,pins = "dap2_dout_pa5", +- "dap2_fs_pa2", +- "dap2_sclk_pa3"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_din_pp5 { +- nvidia,pins = "dap4_din_pp5", +- "dap4_dout_pp6", +- "dap4_fs_pp4", +- "dap4_sclk_pp7"; +- nvidia,function = "i2s3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dvfs_pwm_px0 { +- nvidia,pins = "dvfs_pwm_px0", +- "dvfs_clk_px2"; +- nvidia,function = "cldvfs"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_clk_py0 { +- nvidia,pins = "ulpi_clk_py0", +- "ulpi_data0_po1", +- "ulpi_data1_po2", +- "ulpi_data2_po3", +- "ulpi_data3_po4", +- "ulpi_data4_po5", +- "ulpi_data5_po6", +- "ulpi_data6_po7", +- "ulpi_data7_po0"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_dir_py1 { +- nvidia,pins = "ulpi_dir_py1", +- "ulpi_nxt_py2"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_stp_py3 { +- nvidia,pins = "ulpi_stp_py3"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cam_i2c_scl_pbb1 { +- nvidia,pins = "cam_i2c_scl_pbb1", +- "cam_i2c_sda_pbb2"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- cam_mclk_pcc0 { +- nvidia,pins = "cam_mclk_pcc0", +- "pbb0"; +- nvidia,function = "vi_alt3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- }; +- pbb4 { +- nvidia,pins = "pbb4"; +- nvidia,function = "vgp4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- }; +- gen2_i2c_scl_pt5 { +- nvidia,pins = "gen2_i2c_scl_pt5", +- "gen2_i2c_sda_pt6"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- gmi_a16_pj7 { +- nvidia,pins = "gmi_a16_pj7", +- "gmi_a19_pk7"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_a17_pb0 { +- nvidia,pins = "gmi_a17_pb0", +- "gmi_a18_pb1"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad5_pg5 { +- nvidia,pins = "gmi_ad5_pg5", +- "gmi_wr_n_pi0"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad6_pg6 { +- nvidia,pins = "gmi_ad6_pg6", +- "gmi_ad7_pg7"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad12_ph4 { +- nvidia,pins = "gmi_ad12_ph4"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_cs6_n_pi13 { +- nvidia,pins = "gmi_cs6_n_pi3"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad9_ph1 { +- nvidia,pins = "gmi_ad9_ph1"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_cs1_n_pj2 { +- nvidia,pins = "gmi_cs1_n_pj2", +- "gmi_oe_n_pi1"; +- nvidia,function = "soc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_rst_n_pi4 { +- nvidia,pins = "gmi_rst_n_pi4"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_iordy_pi5 { +- nvidia,pins = "gmi_iordy_pi5"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2_out_pw5 { +- nvidia,pins = "clk2_out_pw5"; +- nvidia,function = "extperiph2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_clk_pz0 { +- nvidia,pins = "sdmmc1_clk_pz0"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_cmd_pz1 { +- nvidia,pins = "sdmmc1_cmd_pz1", +- "sdmmc1_dat0_py7", +- "sdmmc1_dat1_py6", +- "sdmmc1_dat2_py5", +- "sdmmc1_dat3_py4"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_clk_pa6 { +- nvidia,pins = "sdmmc3_clk_pa6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_cmd_pa7 { +- nvidia,pins = "sdmmc3_cmd_pa7", +- "sdmmc3_dat0_pb7", +- "sdmmc3_dat1_pb6", +- "sdmmc3_dat2_pb5", +- "sdmmc3_dat3_pb4", +- "sdmmc3_cd_n_pv2", +- "sdmmc3_clk_lb_out_pee4", +- "sdmmc3_clk_lb_in_pee5"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col4_pq4 { +- nvidia,pins = "kb_col4_pq4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_clk_pcc4 { +- nvidia,pins = "sdmmc4_clk_pcc4"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_cmd_pt7 { +- nvidia,pins = "sdmmc4_cmd_pt7", +- "sdmmc4_dat0_paa0", +- "sdmmc4_dat1_paa1", +- "sdmmc4_dat2_paa2", +- "sdmmc4_dat3_paa3", +- "sdmmc4_dat4_paa4", +- "sdmmc4_dat5_paa5", +- "sdmmc4_dat6_paa6", +- "sdmmc4_dat7_paa7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk_32k_out_pa0 { +- nvidia,pins = "clk_32k_out_pa0"; +- nvidia,function = "blink"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col0_pq0 { +- nvidia,pins = "kb_col0_pq0", +- "kb_col1_pq1", +- "kb_col2_pq2", +- "kb_row0_pr0", +- "kb_row1_pr1", +- "kb_row2_pr2", +- "kb_row8_ps0"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row7_pr7 { +- nvidia,pins = "kb_row7_pr7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row10_ps2 { +- nvidia,pins = "kb_row10_ps2"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row9_ps1 { +- nvidia,pins = "kb_row9_ps1"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pwr_i2c_scl_pz6 { +- nvidia,pins = "pwr_i2c_scl_pz6", +- "pwr_i2c_sda_pz7"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- sys_clk_req_pz5 { +- nvidia,pins = "sys_clk_req_pz5"; +- nvidia,function = "sysclk"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- core_pwr_req { +- nvidia,pins = "core_pwr_req"; +- nvidia,function = "pwron"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cpu_pwr_req { +- nvidia,pins = "cpu_pwr_req"; +- nvidia,function = "cpu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pwr_int_n { +- nvidia,pins = "pwr_int_n"; +- nvidia,function = "pmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- reset_out_n { +- nvidia,pins = "reset_out_n"; +- nvidia,function = "reset_out_n"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3_out_pee0 { +- nvidia,pins = "clk3_out_pee0"; +- nvidia,function = "extperiph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gen1_i2c_scl_pc4 { +- nvidia,pins = "gen1_i2c_scl_pc4", +- "gen1_i2c_sda_pc5"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- uart2_cts_n_pj5 { +- nvidia,pins = "uart2_cts_n_pj5"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_rts_n_pj6 { +- nvidia,pins = "uart2_rts_n_pj6"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_rxd_pc3 { +- nvidia,pins = "uart2_rxd_pc3"; +- nvidia,function = "irda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_txd_pc2 { +- nvidia,pins = "uart2_txd_pc2"; +- nvidia,function = "irda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_cts_n_pa1 { +- nvidia,pins = "uart3_cts_n_pa1", +- "uart3_rxd_pw7"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_rts_n_pc0 { +- nvidia,pins = "uart3_rts_n_pc0", +- "uart3_txd_pw6"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- owr { +- nvidia,pins = "owr"; +- nvidia,function = "owr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- hdmi_cec_pee3 { +- nvidia,pins = "hdmi_cec_pee3"; +- nvidia,function = "cec"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- ddc_scl_pv4 { +- nvidia,pins = "ddc_scl_pv4", +- "ddc_sda_pv5"; +- nvidia,function = "i2c4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,rcv-sel = ; +- }; +- spdif_in_pk6 { +- nvidia,pins = "spdif_in_pk6"; +- nvidia,function = "usb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- }; +- usb_vbus_en0_pn4 { +- nvidia,pins = "usb_vbus_en0_pn4"; +- nvidia,function = "usb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- gpio_x6_aud_px6 { +- nvidia,pins = "gpio_x6_aud_px6"; +- nvidia,function = "spi6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x1_aud_px1 { +- nvidia,pins = "gpio_x1_aud_px1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x7_aud_px7 { +- nvidia,pins = "gpio_x7_aud_px7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_adv_n_pk0 { +- nvidia,pins = "gmi_adv_n_pk0"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_cs0_n_pj0 { +- nvidia,pins = "gmi_cs0_n_pj0"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu3 { +- nvidia,pins = "pu3"; +- nvidia,function = "pwm0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x4_aud_px4 { +- nvidia,pins = "gpio_x4_aud_px4", +- "gpio_x5_aud_px5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x3_aud_px3 { +- nvidia,pins = "gpio_x3_aud_px3"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_w2_aud_pw2 { +- nvidia,pins = "gpio_w2_aud_pw2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_w3_aud_pw3 { +- nvidia,pins = "gpio_w3_aud_pw3"; +- nvidia,function = "spi6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_fs_pp0 { +- nvidia,pins = "dap3_fs_pp0", +- "dap3_din_pp1", +- "dap3_dout_pp2", +- "dap3_sclk_pp3"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv0 { +- nvidia,pins = "pv0"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv1 { +- nvidia,pins = "pv1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb3 { +- nvidia,pins = "pbb3", +- "pbb5", +- "pbb6", +- "pbb7"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pcc1 { +- nvidia,pins = "pcc1", +- "pcc2"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad0_pg0 { +- nvidia,pins = "gmi_ad0_pg0", +- "gmi_ad1_pg1"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad10_ph2 { +- nvidia,pins = "gmi_ad10_ph2", +- "gmi_ad12_ph4", +- "gmi_ad15_ph7", +- "gmi_cs3_n_pk4"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad11_ph3 { +- nvidia,pins = "gmi_ad11_ph3", +- "gmi_ad13_ph5", +- "gmi_ad8_ph0", +- "gmi_clk_pk1", +- "gmi_cs2_n_pk3"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad14_ph6 { +- nvidia,pins = "gmi_ad14_ph6", +- "gmi_cs0_n_pj0", +- "gmi_cs4_n_pk2", +- "gmi_cs7_n_pi6", +- "gmi_dqs_p_pj3", +- "gmi_wp_n_pc7"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad2_pg2 { +- nvidia,pins = "gmi_ad2_pg2", +- "gmi_ad3_pg3"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_wp_n_pv3 { +- nvidia,pins = "sdmmc1_wp_n_pv3"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2_req_pcc5 { +- nvidia,pins = "clk2_req_pcc5"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col3_pq3 { +- nvidia,pins = "kb_col3_pq3"; +- nvidia,function = "pwm2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col5_pq5 { +- nvidia,pins = "kb_col5_pq5"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col6_pq6 { +- nvidia,pins = "kb_col6_pq6", +- "kb_col7_pq7"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row3_pr3 { +- nvidia,pins = "kb_row3_pr3", +- "kb_row4_pr4", +- "kb_row6_pr6"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3_req_pee1 { +- nvidia,pins = "clk3_req_pee1"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu2 { +- nvidia,pins = "pu2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- hdmi_int_pn7 { +- nvidia,pins = "hdmi_int_pn7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- drive_sdio1 { +- nvidia,pins = "drive_sdio1"; +- nvidia,high-speed-mode = ; +- nvidia,schmitt = ; +- nvidia,pull-down-strength = <36>; +- nvidia,pull-up-strength = <20>; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- }; +- drive_sdio3 { +- nvidia,pins = "drive_sdio3"; +- nvidia,high-speed-mode = ; +- nvidia,schmitt = ; +- nvidia,pull-down-strength = <36>; +- nvidia,pull-up-strength = <20>; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- }; +- drive_gma { +- nvidia,pins = "drive_gma"; +- nvidia,high-speed-mode = ; +- nvidia,schmitt = ; +- nvidia,pull-down-strength = <2>; +- nvidia,pull-up-strength = <2>; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- }; +- }; +- }; +- +- /* Usable on reworked devices only */ +- serial@70006300 { +- status = "okay"; +- }; +- +- pwm@7000a000 { +- status = "okay"; +- }; +- +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- regulator@43 { +- compatible = "ti,tps51632"; +- reg = <0x43>; +- regulator-name = "vdd-cpu"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1520000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- palmas: pmic@58 { +- compatible = "ti,palmas"; +- reg = <0x58>; +- interrupts = ; +- +- #interrupt-cells = <2>; +- interrupt-controller; +- +- ti,system-power-controller; +- +- palmas_gpio: gpio { +- compatible = "ti,palmas-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- pmic { +- compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; +- +- regulators { +- smps12 { +- regulator-name = "vdd-ddr"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v8: smps3 { +- regulator-name = "vdd-1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- }; +- +- smps457 { +- regulator-name = "vdd-soc"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps8 { +- regulator-name = "avdd-pll-1v05"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps9 { +- regulator-name = "vdd-2v85-emmc"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- smps10_out1 { +- regulator-name = "vdd-fan"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps10_out2 { +- regulator-name = "vdd-5v0-sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo2 { +- regulator-name = "vdd-2v8-display"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v2_ap: ldo3 { +- regulator-name = "avdd-1v2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo4 { +- regulator-name = "vpp-fuse"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo5 { +- regulator-name = "avdd-hdmi-pll"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo6 { +- regulator-name = "vdd-sensor-2v8"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- ldo8 { +- regulator-name = "vdd-rtc"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- ti,enable-ldo8-tracking; +- }; +- +- vddio_sdmmc3: ldo9 { +- regulator-name = "vddio-sdmmc3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldousb { +- regulator-name = "avdd-usb-hdmi"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_3v3_sys: regen1 { +- regulator-name = "rail-3v3"; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- regen2 { +- regulator-name = "rail-5v0"; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- }; +- }; +- +- rtc { +- compatible = "ti,palmas-rtc"; +- interrupt-parent = <&palmas>; +- interrupts = <8 0>; +- }; +- +- }; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- }; +- +- /* SD card */ +- mmc@78000400 { +- status = "okay"; +- bus-width = <4>; +- vqmmc-supply = <&vddio_sdmmc3>; +- cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; +- power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; +- }; +- +- /* eMMC */ +- mmc@78000600 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- }; +- +- /* External USB port (must be powered) */ +- usb@7d000000 { +- status = "okay"; +- }; +- +- usb-phy@7d000000 { +- status = "okay"; +- nvidia,xcvr-setup = <7>; +- nvidia,xcvr-lsfslew = <2>; +- nvidia,xcvr-lsrslew = <2>; +- interrupts = ; +- /* Should be changed to "otg" once we have vbus_supply */ +- /* As of now, USB devices need to be powered externally */ +- dr_mode = "host"; +- }; +- +- /* SHIELD controller */ +- usb@7d008000 { +- status = "okay"; +- }; +- +- usb-phy@7d008000 { +- status = "okay"; +- nvidia,xcvr-setup = <7>; +- nvidia,xcvr-lsfslew = <2>; +- nvidia,xcvr-lsrslew = <2>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 1 40000>; +- +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- +- power-supply = <&lcd_bl_en>; +- enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- back { +- label = "Back"; +- gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- home { +- label = "Home"; +- gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- power { +- label = "Power"; +- gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- lcd_bl_en: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "lcd_bl_en"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- }; +- +- vdd_lcd: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_lcd_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vdd_1v8>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; +- regulator-boot-on; +- }; +- +- regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_1v8_ts"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>; +- regulator-boot-on; +- }; +- +- regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_3v3_ts"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; +- regulator-boot-on; +- }; +- +- regulator@4 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_1v8_com"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vdd_1v8>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; +- regulator-boot-on; +- }; +- +- regulator@5 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_3v3_com"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vdd_3v3_sys>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra114-tn7.dts b/scripts/dtc/include-prefixes/arm/tegra114-tn7.dts +deleted file mode 100644 +index 745d234b105b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra114-tn7.dts ++++ /dev/null +@@ -1,336 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include "tegra114.dtsi" +- +-/ { +- model = "Tegra Note 7"; +- compatible = "nvidia,tn7", "nvidia,tegra114"; +- +- chosen { +- /* TN7's bootloader's arguments need to be overridden */ +- bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:2"; +- /* TN7's bootloader will place initrd at this address */ +- linux,initrd-start = <0x82000000>; +- linux,initrd-end = <0x82800000>; +- }; +- +- aliases { +- serial0 = &uartd; +- }; +- +- firmware { +- trusted-foundations { +- compatible = "tlm,trusted-foundations"; +- tlm,version-major = <2>; +- tlm,version-minor = <8>; +- }; +- }; +- +- memory@80000000 { +- /* memory >= 0x37e00000 is reserved for firmware usage */ +- reg = <0x80000000 0x37e00000>; +- }; +- +- host1x@50000000 { +- dsi@54300000 { +- status = "okay"; +- +- avdd-dsi-csi-supply = <&vdd_1v2_ap>; +- +- panel@0 { +- compatible = "lg,ld070wx3-sl01"; +- reg = <0>; +- +- power-supply = <&vdd_lcd>; +- backlight = <&backlight>; +- }; +- }; +- }; +- +- serial@70006300 { +- status = "okay"; +- }; +- +- pwm@7000a000 { +- status = "okay"; +- }; +- +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- palmas: pmic@58 { +- compatible = "ti,palmas"; +- reg = <0x58>; +- interrupts = ; +- +- #interrupt-cells = <2>; +- interrupt-controller; +- +- ti,system-power-controller; +- +- palmas_gpio: gpio { +- compatible = "ti,palmas-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- pmic { +- compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; +- +- ldoln-in-supply = <&vdd_smps10_out2>; +- +- regulators { +- smps123 { +- regulator-name = "vd-cpu"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps45 { +- regulator-name = "vd-soc"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps6 { +- regulator-name = "va-lcd-hv"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- smps7 { +- regulator-name = "vd-ddr"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v8: smps8 { +- regulator-name = "vs-pmu-1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_2v9_sys: smps9 { +- regulator-name = "vs-sys-2v9"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_smps10_out1: smps10_out1 { +- regulator-name = "vd-smps10-out1"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_smps10_out2: smps10_out2 { +- regulator-name = "vd-smps10-out2"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo1 { +- regulator-name = "va-pllx"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v2_ap: ldo2 { +- regulator-name = "va-ap-1v2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo3 { +- regulator-name = "vd-fuse"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo4 { +- regulator-name = "vd-ts-hv"; +- regulator-min-microvolt = <3200000>; +- regulator-max-microvolt = <3200000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo5 { +- regulator-name = "va-cam2-hv"; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- ldo6 { +- regulator-name = "va-sns-hv"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- ldo7 { +- regulator-name = "va-cam1-hv"; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- ldo8 { +- regulator-name = "va-ap-rtc"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- ti,enable-ldo8-tracking; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo9 { +- regulator-name = "vi-sdcard"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- }; +- +- ldousb { +- regulator-name = "avdd-usb"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldoln { +- regulator-name = "va-hdmi"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +- }; +- +- rtc { +- compatible = "ti,palmas-rtc"; +- interrupt-parent = <&palmas>; +- interrupts = <8 0>; +- }; +- +- }; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- }; +- +- /* eMMC */ +- mmc@78000600 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- }; +- +- usb@7d000000 { +- status = "okay"; +- }; +- +- usb-phy@7d000000 { +- status = "okay"; +- nvidia,xcvr-setup = <7>; +- nvidia,xcvr-lsfslew = <2>; +- nvidia,xcvr-lsrslew = <2>; +- interrupts = ; +- /* Should be changed to "otg" once we have vbus_supply */ +- /* As of now, USB devices need to be powered externally */ +- dr_mode = "host"; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 1 40000>; +- +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- +- power-supply = <&lcd_bl_en>; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "Power"; +- gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- volume_down { +- label = "Volume Down"; +- gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- volume_up { +- label = "Volume Up"; +- gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- /* FIXME: output of BQ24192 */ +- vs_sys: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "VS_SYS"; +- regulator-min-microvolt = <4200000>; +- regulator-max-microvolt = <4200000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- lcd_bl_en: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_LCD_BL"; +- regulator-min-microvolt = <16500000>; +- regulator-max-microvolt = <16500000>; +- gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vs_sys>; +- regulator-boot-on; +- }; +- +- vdd_lcd: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "VD_LCD_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_1v8>; +- regulator-boot-on; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra114.dtsi b/scripts/dtc/include-prefixes/arm/tegra114.dtsi +deleted file mode 100644 +index fb99b3e971c3..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra114.dtsi ++++ /dev/null +@@ -1,810 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "nvidia,tegra114"; +- interrupt-parent = <&lic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x0>; +- }; +- +- host1x@50000000 { +- compatible = "nvidia,tegra114-host1x"; +- reg = <0x50000000 0x00028000>; +- interrupts = , /* syncpt */ +- ; /* general */ +- interrupt-names = "syncpt", "host1x"; +- clocks = <&tegra_car TEGRA114_CLK_HOST1X>; +- clock-names = "host1x"; +- resets = <&tegra_car 28>; +- reset-names = "host1x"; +- iommus = <&mc TEGRA_SWGROUP_HC>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0x54000000 0x54000000 0x01000000>; +- +- gr2d@54140000 { +- compatible = "nvidia,tegra114-gr2d"; +- reg = <0x54140000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA114_CLK_GR2D>; +- resets = <&tegra_car 21>; +- reset-names = "2d"; +- +- iommus = <&mc TEGRA_SWGROUP_G2>; +- }; +- +- gr3d@54180000 { +- compatible = "nvidia,tegra114-gr3d"; +- reg = <0x54180000 0x00040000>; +- clocks = <&tegra_car TEGRA114_CLK_GR3D>; +- resets = <&tegra_car 24>; +- reset-names = "3d"; +- +- iommus = <&mc TEGRA_SWGROUP_NV>; +- }; +- +- dc@54200000 { +- compatible = "nvidia,tegra114-dc"; +- reg = <0x54200000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA114_CLK_DISP1>, +- <&tegra_car TEGRA114_CLK_PLL_P>; +- clock-names = "dc", "parent"; +- resets = <&tegra_car 27>; +- reset-names = "dc"; +- +- iommus = <&mc TEGRA_SWGROUP_DC>; +- +- nvidia,head = <0>; +- +- rgb { +- status = "disabled"; +- }; +- }; +- +- dc@54240000 { +- compatible = "nvidia,tegra114-dc"; +- reg = <0x54240000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA114_CLK_DISP2>, +- <&tegra_car TEGRA114_CLK_PLL_P>; +- clock-names = "dc", "parent"; +- resets = <&tegra_car 26>; +- reset-names = "dc"; +- +- iommus = <&mc TEGRA_SWGROUP_DCB>; +- +- nvidia,head = <1>; +- +- rgb { +- status = "disabled"; +- }; +- }; +- +- hdmi@54280000 { +- compatible = "nvidia,tegra114-hdmi"; +- reg = <0x54280000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA114_CLK_HDMI>, +- <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; +- clock-names = "hdmi", "parent"; +- resets = <&tegra_car 51>; +- reset-names = "hdmi"; +- status = "disabled"; +- }; +- +- dsi@54300000 { +- compatible = "nvidia,tegra114-dsi"; +- reg = <0x54300000 0x00040000>; +- clocks = <&tegra_car TEGRA114_CLK_DSIA>, +- <&tegra_car TEGRA114_CLK_DSIALP>, +- <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; +- clock-names = "dsi", "lp", "parent"; +- resets = <&tegra_car 48>; +- reset-names = "dsi"; +- nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ +- status = "disabled"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- dsi@54400000 { +- compatible = "nvidia,tegra114-dsi"; +- reg = <0x54400000 0x00040000>; +- clocks = <&tegra_car TEGRA114_CLK_DSIB>, +- <&tegra_car TEGRA114_CLK_DSIBLP>, +- <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; +- clock-names = "dsi", "lp", "parent"; +- resets = <&tegra_car 82>; +- reset-names = "dsi"; +- nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ +- status = "disabled"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- gic: interrupt-controller@50041000 { +- compatible = "arm,cortex-a15-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x50041000 0x1000>, +- <0x50042000 0x1000>, +- <0x50044000 0x2000>, +- <0x50046000 0x2000>; +- interrupts = ; +- interrupt-parent = <&gic>; +- }; +- +- lic: interrupt-controller@60004000 { +- compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr"; +- reg = <0x60004000 0x100>, +- <0x60004100 0x50>, +- <0x60004200 0x50>, +- <0x60004300 0x50>, +- <0x60004400 0x50>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- }; +- +- timer@60005000 { +- compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; +- reg = <0x60005000 0x400>; +- interrupts = , +- , +- , +- , +- , +- ; +- clocks = <&tegra_car TEGRA114_CLK_TIMER>; +- }; +- +- tegra_car: clock@60006000 { +- compatible = "nvidia,tegra114-car"; +- reg = <0x60006000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- flow-controller@60007000 { +- compatible = "nvidia,tegra114-flowctrl"; +- reg = <0x60007000 0x1000>; +- }; +- +- apbdma: dma@6000a000 { +- compatible = "nvidia,tegra114-apbdma"; +- reg = <0x6000a000 0x1400>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&tegra_car TEGRA114_CLK_APBDMA>; +- resets = <&tegra_car 34>; +- reset-names = "dma"; +- #dma-cells = <1>; +- }; +- +- ahb: ahb@6000c000 { +- compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; +- reg = <0x6000c000 0x150>; +- }; +- +- gpio: gpio@6000d000 { +- compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; +- reg = <0x6000d000 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- #gpio-cells = <2>; +- gpio-controller; +- #interrupt-cells = <2>; +- interrupt-controller; +- /* +- gpio-ranges = <&pinmux 0 0 246>; +- */ +- }; +- +- apbmisc@70000800 { +- compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; +- reg = <0x70000800 0x64>, /* Chip revision */ +- <0x70000008 0x04>; /* Strapping options */ +- }; +- +- pinmux: pinmux@70000868 { +- compatible = "nvidia,tegra114-pinmux"; +- reg = <0x70000868 0x148>, /* Pad control registers */ +- <0x70003000 0x40c>; /* Mux registers */ +- }; +- +- /* +- * There are two serial driver i.e. 8250 based simple serial +- * driver and APB DMA based serial driver for higher baudrate +- * and performace. To enable the 8250 based driver, the compatible +- * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable +- * the APB DMA based serial driver, the compatible is +- * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". +- */ +- uarta: serial@70006000 { +- compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; +- reg = <0x70006000 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA114_CLK_UARTA>; +- resets = <&tegra_car 6>; +- reset-names = "serial"; +- dmas = <&apbdma 8>, <&apbdma 8>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uartb: serial@70006040 { +- compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; +- reg = <0x70006040 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA114_CLK_UARTB>; +- resets = <&tegra_car 7>; +- reset-names = "serial"; +- dmas = <&apbdma 9>, <&apbdma 9>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uartc: serial@70006200 { +- compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; +- reg = <0x70006200 0x100>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA114_CLK_UARTC>; +- resets = <&tegra_car 55>; +- reset-names = "serial"; +- dmas = <&apbdma 10>, <&apbdma 10>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uartd: serial@70006300 { +- compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; +- reg = <0x70006300 0x100>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA114_CLK_UARTD>; +- resets = <&tegra_car 65>; +- reset-names = "serial"; +- dmas = <&apbdma 19>, <&apbdma 19>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- pwm: pwm@7000a000 { +- compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; +- reg = <0x7000a000 0x100>; +- #pwm-cells = <2>; +- clocks = <&tegra_car TEGRA114_CLK_PWM>; +- resets = <&tegra_car 17>; +- reset-names = "pwm"; +- status = "disabled"; +- }; +- +- i2c@7000c000 { +- compatible = "nvidia,tegra114-i2c"; +- reg = <0x7000c000 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA114_CLK_I2C1>; +- clock-names = "div-clk"; +- resets = <&tegra_car 12>; +- reset-names = "i2c"; +- dmas = <&apbdma 21>, <&apbdma 21>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000c400 { +- compatible = "nvidia,tegra114-i2c"; +- reg = <0x7000c400 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA114_CLK_I2C2>; +- clock-names = "div-clk"; +- resets = <&tegra_car 54>; +- reset-names = "i2c"; +- dmas = <&apbdma 22>, <&apbdma 22>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000c500 { +- compatible = "nvidia,tegra114-i2c"; +- reg = <0x7000c500 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA114_CLK_I2C3>; +- clock-names = "div-clk"; +- resets = <&tegra_car 67>; +- reset-names = "i2c"; +- dmas = <&apbdma 23>, <&apbdma 23>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000c700 { +- compatible = "nvidia,tegra114-i2c"; +- reg = <0x7000c700 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA114_CLK_I2C4>; +- clock-names = "div-clk"; +- resets = <&tegra_car 103>; +- reset-names = "i2c"; +- dmas = <&apbdma 26>, <&apbdma 26>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000d000 { +- compatible = "nvidia,tegra114-i2c"; +- reg = <0x7000d000 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA114_CLK_I2C5>; +- clock-names = "div-clk"; +- resets = <&tegra_car 47>; +- reset-names = "i2c"; +- dmas = <&apbdma 24>, <&apbdma 24>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000d400 { +- compatible = "nvidia,tegra114-spi"; +- reg = <0x7000d400 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA114_CLK_SBC1>; +- clock-names = "spi"; +- resets = <&tegra_car 41>; +- reset-names = "spi"; +- dmas = <&apbdma 15>, <&apbdma 15>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000d600 { +- compatible = "nvidia,tegra114-spi"; +- reg = <0x7000d600 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA114_CLK_SBC2>; +- clock-names = "spi"; +- resets = <&tegra_car 44>; +- reset-names = "spi"; +- dmas = <&apbdma 16>, <&apbdma 16>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000d800 { +- compatible = "nvidia,tegra114-spi"; +- reg = <0x7000d800 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA114_CLK_SBC3>; +- clock-names = "spi"; +- resets = <&tegra_car 46>; +- reset-names = "spi"; +- dmas = <&apbdma 17>, <&apbdma 17>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000da00 { +- compatible = "nvidia,tegra114-spi"; +- reg = <0x7000da00 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA114_CLK_SBC4>; +- clock-names = "spi"; +- resets = <&tegra_car 68>; +- reset-names = "spi"; +- dmas = <&apbdma 18>, <&apbdma 18>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000dc00 { +- compatible = "nvidia,tegra114-spi"; +- reg = <0x7000dc00 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA114_CLK_SBC5>; +- clock-names = "spi"; +- resets = <&tegra_car 104>; +- reset-names = "spi"; +- dmas = <&apbdma 27>, <&apbdma 27>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000de00 { +- compatible = "nvidia,tegra114-spi"; +- reg = <0x7000de00 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA114_CLK_SBC6>; +- clock-names = "spi"; +- resets = <&tegra_car 105>; +- reset-names = "spi"; +- dmas = <&apbdma 28>, <&apbdma 28>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- rtc@7000e000 { +- compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; +- reg = <0x7000e000 0x100>; +- interrupts = ; +- clocks = <&tegra_car TEGRA114_CLK_RTC>; +- }; +- +- kbc@7000e200 { +- compatible = "nvidia,tegra114-kbc"; +- reg = <0x7000e200 0x100>; +- interrupts = ; +- clocks = <&tegra_car TEGRA114_CLK_KBC>; +- resets = <&tegra_car 36>; +- reset-names = "kbc"; +- status = "disabled"; +- }; +- +- tegra_pmc: pmc@7000e400 { +- compatible = "nvidia,tegra114-pmc"; +- reg = <0x7000e400 0x400>; +- clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; +- clock-names = "pclk", "clk32k_in"; +- #clock-cells = <1>; +- }; +- +- fuse@7000f800 { +- compatible = "nvidia,tegra114-efuse"; +- reg = <0x7000f800 0x400>; +- clocks = <&tegra_car TEGRA114_CLK_FUSE>; +- clock-names = "fuse"; +- resets = <&tegra_car 39>; +- reset-names = "fuse"; +- }; +- +- mc: memory-controller@70019000 { +- compatible = "nvidia,tegra114-mc"; +- reg = <0x70019000 0x1000>; +- clocks = <&tegra_car TEGRA114_CLK_MC>; +- clock-names = "mc"; +- +- interrupts = ; +- +- #iommu-cells = <1>; +- }; +- +- ahub@70080000 { +- compatible = "nvidia,tegra114-ahub"; +- reg = <0x70080000 0x200>, +- <0x70080200 0x100>, +- <0x70081000 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, +- <&tegra_car TEGRA114_CLK_APBIF>; +- clock-names = "d_audio", "apbif"; +- resets = <&tegra_car 106>, /* d_audio */ +- <&tegra_car 107>, /* apbif */ +- <&tegra_car 30>, /* i2s0 */ +- <&tegra_car 11>, /* i2s1 */ +- <&tegra_car 18>, /* i2s2 */ +- <&tegra_car 101>, /* i2s3 */ +- <&tegra_car 102>, /* i2s4 */ +- <&tegra_car 108>, /* dam0 */ +- <&tegra_car 109>, /* dam1 */ +- <&tegra_car 110>, /* dam2 */ +- <&tegra_car 10>, /* spdif */ +- <&tegra_car 153>, /* amx */ +- <&tegra_car 154>; /* adx */ +- reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", +- "i2s3", "i2s4", "dam0", "dam1", "dam2", +- "spdif", "amx", "adx"; +- dmas = <&apbdma 1>, <&apbdma 1>, +- <&apbdma 2>, <&apbdma 2>, +- <&apbdma 3>, <&apbdma 3>, +- <&apbdma 4>, <&apbdma 4>, +- <&apbdma 6>, <&apbdma 6>, +- <&apbdma 7>, <&apbdma 7>, +- <&apbdma 12>, <&apbdma 12>, +- <&apbdma 13>, <&apbdma 13>, +- <&apbdma 14>, <&apbdma 14>, +- <&apbdma 29>, <&apbdma 29>; +- dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", +- "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", +- "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", +- "rx9", "tx9"; +- ranges; +- #address-cells = <1>; +- #size-cells = <1>; +- +- tegra_i2s0: i2s@70080300 { +- compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; +- reg = <0x70080300 0x100>; +- nvidia,ahub-cif-ids = <4 4>; +- clocks = <&tegra_car TEGRA114_CLK_I2S0>; +- resets = <&tegra_car 30>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- +- tegra_i2s1: i2s@70080400 { +- compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; +- reg = <0x70080400 0x100>; +- nvidia,ahub-cif-ids = <5 5>; +- clocks = <&tegra_car TEGRA114_CLK_I2S1>; +- resets = <&tegra_car 11>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- +- tegra_i2s2: i2s@70080500 { +- compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; +- reg = <0x70080500 0x100>; +- nvidia,ahub-cif-ids = <6 6>; +- clocks = <&tegra_car TEGRA114_CLK_I2S2>; +- resets = <&tegra_car 18>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- +- tegra_i2s3: i2s@70080600 { +- compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; +- reg = <0x70080600 0x100>; +- nvidia,ahub-cif-ids = <7 7>; +- clocks = <&tegra_car TEGRA114_CLK_I2S3>; +- resets = <&tegra_car 101>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- +- tegra_i2s4: i2s@70080700 { +- compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; +- reg = <0x70080700 0x100>; +- nvidia,ahub-cif-ids = <8 8>; +- clocks = <&tegra_car TEGRA114_CLK_I2S4>; +- resets = <&tegra_car 102>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- }; +- +- mipi: mipi@700e3000 { +- compatible = "nvidia,tegra114-mipi"; +- reg = <0x700e3000 0x100>; +- clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; +- #nvidia,mipi-calibrate-cells = <1>; +- }; +- +- mmc@78000000 { +- compatible = "nvidia,tegra114-sdhci"; +- reg = <0x78000000 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; +- clock-names = "sdhci"; +- resets = <&tegra_car 14>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- mmc@78000200 { +- compatible = "nvidia,tegra114-sdhci"; +- reg = <0x78000200 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; +- clock-names = "sdhci"; +- resets = <&tegra_car 9>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- mmc@78000400 { +- compatible = "nvidia,tegra114-sdhci"; +- reg = <0x78000400 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; +- clock-names = "sdhci"; +- resets = <&tegra_car 69>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- mmc@78000600 { +- compatible = "nvidia,tegra114-sdhci"; +- reg = <0x78000600 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; +- clock-names = "sdhci"; +- resets = <&tegra_car 15>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- usb@7d000000 { +- compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci"; +- reg = <0x7d000000 0x4000>; +- interrupts = ; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA114_CLK_USBD>; +- resets = <&tegra_car 22>; +- reset-names = "usb"; +- nvidia,phy = <&phy1>; +- status = "disabled"; +- }; +- +- phy1: usb-phy@7d000000 { +- compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; +- reg = <0x7d000000 0x4000>, +- <0x7d000000 0x4000>; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA114_CLK_USBD>, +- <&tegra_car TEGRA114_CLK_PLL_U>, +- <&tegra_car TEGRA114_CLK_USBD>; +- clock-names = "reg", "pll_u", "utmi-pads"; +- resets = <&tegra_car 22>, <&tegra_car 22>; +- reset-names = "usb", "utmi-pads"; +- #phy-cells = <0>; +- nvidia,hssync-start-delay = <0>; +- nvidia,idle-wait-delay = <17>; +- nvidia,elastic-limit = <16>; +- nvidia,term-range-adj = <6>; +- nvidia,xcvr-setup = <9>; +- nvidia,xcvr-lsfslew = <0>; +- nvidia,xcvr-lsrslew = <3>; +- nvidia,hssquelch-level = <2>; +- nvidia,hsdiscon-level = <5>; +- nvidia,xcvr-hsslew = <12>; +- nvidia,has-utmi-pad-registers; +- status = "disabled"; +- }; +- +- usb@7d008000 { +- compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci"; +- reg = <0x7d008000 0x4000>; +- interrupts = ; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA114_CLK_USB3>; +- resets = <&tegra_car 59>; +- reset-names = "usb"; +- nvidia,phy = <&phy3>; +- status = "disabled"; +- }; +- +- phy3: usb-phy@7d008000 { +- compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; +- reg = <0x7d008000 0x4000>, +- <0x7d000000 0x4000>; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA114_CLK_USB3>, +- <&tegra_car TEGRA114_CLK_PLL_U>, +- <&tegra_car TEGRA114_CLK_USBD>; +- clock-names = "reg", "pll_u", "utmi-pads"; +- resets = <&tegra_car 59>, <&tegra_car 22>; +- reset-names = "usb", "utmi-pads"; +- #phy-cells = <0>; +- nvidia,hssync-start-delay = <0>; +- nvidia,idle-wait-delay = <17>; +- nvidia,elastic-limit = <16>; +- nvidia,term-range-adj = <6>; +- nvidia,xcvr-setup = <9>; +- nvidia,xcvr-lsfslew = <0>; +- nvidia,xcvr-lsrslew = <3>; +- nvidia,hssquelch-level = <2>; +- nvidia,hsdiscon-level = <5>; +- nvidia,xcvr-hsslew = <12>; +- status = "disabled"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <1>; +- }; +- +- cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <2>; +- }; +- +- cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <3>; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = +- , +- , +- , +- ; +- interrupt-parent = <&gic>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra124-apalis-emc.dtsi b/scripts/dtc/include-prefixes/arm/tegra124-apalis-emc.dtsi +deleted file mode 100644 +index a7ac805eeed5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra124-apalis-emc.dtsi ++++ /dev/null +@@ -1,1475 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright 2016-2019 Toradex AG +- * +- */ +- +-/ { +- clock@60006000 { +- emc-timings-1 { +- nvidia,ram-code = <1>; +- +- timing-12750000 { +- clock-frequency = <12750000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-20400000 { +- clock-frequency = <20400000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-40800000 { +- clock-frequency = <40800000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-68000000 { +- clock-frequency = <68000000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-102000000 { +- clock-frequency = <102000000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-204000000 { +- clock-frequency = <204000000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-300000000 { +- clock-frequency = <300000000>; +- nvidia,parent-clock-frequency = <600000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_C>; +- clock-names = "emc-parent"; +- }; +- timing-396000000 { +- clock-frequency = <396000000>; +- nvidia,parent-clock-frequency = <792000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_M>; +- clock-names = "emc-parent"; +- }; +- timing-528000000 { +- clock-frequency = <528000000>; +- nvidia,parent-clock-frequency = <528000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; +- clock-names = "emc-parent"; +- }; +- timing-600000000 { +- clock-frequency = <600000000>; +- nvidia,parent-clock-frequency = <600000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; +- clock-names = "emc-parent"; +- }; +- timing-792000000 { +- clock-frequency = <792000000>; +- nvidia,parent-clock-frequency = <792000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; +- clock-names = "emc-parent"; +- }; +- timing-924000000 { +- clock-frequency = <924000000>; +- nvidia,parent-clock-frequency = <924000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; +- clock-names = "emc-parent"; +- }; +- }; +- }; +- +- external-memory-controller@7001b000 { +- emc-timings-1 { +- nvidia,ram-code = <1>; +- +- timing-12750000 { +- clock-frequency = <12750000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000e000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000000 0x00000003 +- 0x00000000 0x00000000 +- 0x00000000 0x00000004 +- 0x0000000a 0x00000005 +- 0x0000000b 0x00000000 +- 0x00000000 0x00000003 +- 0x00000003 0x00000000 +- 0x00000006 0x00000006 +- 0x00000006 0x00000002 +- 0x00000000 0x00000005 +- 0x00000005 0x00010000 +- 0x00000003 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000004 +- 0x0000000c 0x0000000d +- 0x0000000f 0x00000060 +- 0x00000000 0x00000018 +- 0x00000002 0x00000002 +- 0x00000001 0x00000000 +- 0x00000007 0x0000000f +- 0x00000005 0x00000005 +- 0x00000004 0x00000005 +- 0x00000004 0x00000000 +- 0x00000000 0x00000005 +- 0x00000005 0x00000064 +- 0x00000000 0x00000000 +- 0x00000000 0x106aa298 +- 0x002c00a0 0x00008000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x000fc000 0x000fc000 +- 0x000fc000 0x000fc000 +- 0x0000fc00 0x0000fc00 +- 0x0000fc00 0x0000fc00 +- 0x10000280 0x00000000 +- 0x00111111 0x00000000 +- 0x00000000 0x77ffc081 +- 0x00000e0e 0x81f1f108 +- 0x07070004 0x0000003f +- 0x016eeeee 0x51451400 +- 0x00514514 0x00514514 +- 0x51451400 0x0000003f +- 0x00000007 0x00000000 +- 0x00000042 0x000e000e +- 0x00000000 0x00000003 +- 0x0000f2f3 0x800001c5 +- 0x0000000a +- >; +- }; +- +- timing-20400000 { +- clock-frequency = <20400000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000e000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000000 0x00000005 +- 0x00000000 0x00000000 +- 0x00000000 0x00000004 +- 0x0000000a 0x00000005 +- 0x0000000b 0x00000000 +- 0x00000000 0x00000003 +- 0x00000003 0x00000000 +- 0x00000006 0x00000006 +- 0x00000006 0x00000002 +- 0x00000000 0x00000005 +- 0x00000005 0x00010000 +- 0x00000003 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000004 +- 0x0000000c 0x0000000d +- 0x0000000f 0x0000009a +- 0x00000000 0x00000026 +- 0x00000002 0x00000002 +- 0x00000001 0x00000000 +- 0x00000007 0x0000000f +- 0x00000006 0x00000006 +- 0x00000004 0x00000005 +- 0x00000004 0x00000000 +- 0x00000000 0x00000005 +- 0x00000005 0x000000a0 +- 0x00000000 0x00000000 +- 0x00000000 0x106aa298 +- 0x002c00a0 0x00008000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x000fc000 0x000fc000 +- 0x000fc000 0x000fc000 +- 0x0000fc00 0x0000fc00 +- 0x0000fc00 0x0000fc00 +- 0x10000280 0x00000000 +- 0x00111111 0x00000000 +- 0x00000000 0x77ffc081 +- 0x00000e0e 0x81f1f108 +- 0x07070004 0x0000003f +- 0x016eeeee 0x51451400 +- 0x00514514 0x00514514 +- 0x51451400 0x0000003f +- 0x0000000b 0x00000000 +- 0x00000042 0x000e000e +- 0x00000000 0x00000003 +- 0x0000f2f3 0x8000023a +- 0x0000000a +- >; +- }; +- +- timing-40800000 { +- clock-frequency = <40800000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000e000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000001 0x0000000a +- 0x00000000 0x00000001 +- 0x00000000 0x00000004 +- 0x0000000a 0x00000005 +- 0x0000000b 0x00000000 +- 0x00000000 0x00000003 +- 0x00000003 0x00000000 +- 0x00000006 0x00000006 +- 0x00000006 0x00000002 +- 0x00000000 0x00000005 +- 0x00000005 0x00010000 +- 0x00000003 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000004 +- 0x0000000c 0x0000000d +- 0x0000000f 0x00000134 +- 0x00000000 0x0000004d +- 0x00000002 0x00000002 +- 0x00000001 0x00000000 +- 0x00000008 0x0000000f +- 0x0000000c 0x0000000c +- 0x00000004 0x00000005 +- 0x00000004 0x00000000 +- 0x00000000 0x00000005 +- 0x00000005 0x0000013f +- 0x00000000 0x00000000 +- 0x00000000 0x106aa298 +- 0x002c00a0 0x00008000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x000fc000 0x000fc000 +- 0x000fc000 0x000fc000 +- 0x0000fc00 0x0000fc00 +- 0x0000fc00 0x0000fc00 +- 0x10000280 0x00000000 +- 0x00111111 0x00000000 +- 0x00000000 0x77ffc081 +- 0x00000e0e 0x81f1f108 +- 0x07070004 0x0000003f +- 0x016eeeee 0x51451400 +- 0x00514514 0x00514514 +- 0x51451400 0x0000003f +- 0x00000015 0x00000000 +- 0x00000042 0x000e000e +- 0x00000000 0x00000003 +- 0x0000f2f3 0x80000370 +- 0x0000000a +- >; +- }; +- +- timing-68000000 { +- clock-frequency = <68000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000e000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000003 0x00000011 +- 0x00000000 0x00000002 +- 0x00000000 0x00000004 +- 0x0000000a 0x00000005 +- 0x0000000b 0x00000000 +- 0x00000000 0x00000003 +- 0x00000003 0x00000000 +- 0x00000006 0x00000006 +- 0x00000006 0x00000002 +- 0x00000000 0x00000005 +- 0x00000005 0x00010000 +- 0x00000003 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000004 +- 0x0000000c 0x0000000d +- 0x0000000f 0x00000202 +- 0x00000000 0x00000080 +- 0x00000002 0x00000002 +- 0x00000001 0x00000000 +- 0x0000000f 0x0000000f +- 0x00000013 0x00000013 +- 0x00000004 0x00000005 +- 0x00000004 0x00000001 +- 0x00000000 0x00000005 +- 0x00000005 0x00000213 +- 0x00000000 0x00000000 +- 0x00000000 0x106aa298 +- 0x002c00a0 0x00008000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x000fc000 0x000fc000 +- 0x000fc000 0x000fc000 +- 0x0000fc00 0x0000fc00 +- 0x0000fc00 0x0000fc00 +- 0x10000280 0x00000000 +- 0x00111111 0x00000000 +- 0x00000000 0x77ffc081 +- 0x00000e0e 0x81f1f108 +- 0x07070004 0x0000003f +- 0x016eeeee 0x51451400 +- 0x00514514 0x00514514 +- 0x51451400 0x0000003f +- 0x00000022 0x00000000 +- 0x00000042 0x000e000e +- 0x00000000 0x00000003 +- 0x0000f2f3 0x8000050e +- 0x0000000a +- >; +- }; +- +- timing-102000000 { +- clock-frequency = <102000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000e000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000004 0x0000001a +- 0x00000000 0x00000003 +- 0x00000001 0x00000004 +- 0x0000000a 0x00000005 +- 0x0000000b 0x00000001 +- 0x00000001 0x00000003 +- 0x00000003 0x00000000 +- 0x00000006 0x00000006 +- 0x00000006 0x00000002 +- 0x00000000 0x00000005 +- 0x00000005 0x00010000 +- 0x00000003 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000004 +- 0x0000000c 0x0000000d +- 0x0000000f 0x00000304 +- 0x00000000 0x000000c1 +- 0x00000002 0x00000002 +- 0x00000001 0x00000000 +- 0x00000018 0x0000000f +- 0x0000001c 0x0000001c +- 0x00000004 0x00000005 +- 0x00000004 0x00000002 +- 0x00000000 0x00000005 +- 0x00000005 0x0000031c +- 0x00000000 0x00000000 +- 0x00000000 0x106aa298 +- 0x002c00a0 0x00008000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x000fc000 0x000fc000 +- 0x000fc000 0x000fc000 +- 0x0000fc00 0x0000fc00 +- 0x0000fc00 0x0000fc00 +- 0x10000280 0x00000000 +- 0x00111111 0x00000000 +- 0x00000000 0x77ffc081 +- 0x00000e0e 0x81f1f108 +- 0x07070004 0x0000003f +- 0x016eeeee 0x51451400 +- 0x00514514 0x00514514 +- 0x51451400 0x0000003f +- 0x00000033 0x00000000 +- 0x00000042 0x000e000e +- 0x00000000 0x00000003 +- 0x0000f2f3 0x80000713 +- 0x0000000a +- >; +- }; +- +- timing-204000000 { +- clock-frequency = <204000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008cd>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000e000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000009 0x00000035 +- 0x00000000 0x00000006 +- 0x00000002 0x00000005 +- 0x0000000a 0x00000005 +- 0x0000000b 0x00000002 +- 0x00000002 0x00000003 +- 0x00000003 0x00000000 +- 0x00000005 0x00000005 +- 0x00000006 0x00000002 +- 0x00000000 0x00000004 +- 0x00000006 0x00010000 +- 0x00000003 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000003 +- 0x0000000d 0x0000000f +- 0x00000011 0x00000607 +- 0x00000000 0x00000181 +- 0x00000002 0x00000002 +- 0x00000001 0x00000000 +- 0x00000032 0x0000000f +- 0x00000038 0x00000038 +- 0x00000004 0x00000005 +- 0x00000004 0x00000006 +- 0x00000000 0x00000005 +- 0x00000005 0x00000638 +- 0x00000000 0x00000000 +- 0x00000000 0x106aa298 +- 0x002c00a0 0x00008000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00080000 0x00080000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00008000 0x00000000 +- 0x00000000 0x00008000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00090000 0x00090000 +- 0x00090000 0x00090000 +- 0x00009000 0x00009000 +- 0x00009000 0x00009000 +- 0x10000280 0x00000000 +- 0x00111111 0x00000000 +- 0x00000000 0x77ffc081 +- 0x00000707 0x81f1f108 +- 0x07070004 0x0000003f +- 0x016eeeee 0x51451400 +- 0x00514514 0x00514514 +- 0x51451400 0x0000003f +- 0x00000066 0x00000000 +- 0x00000100 0x000e000e +- 0x00000000 0x00000003 +- 0x0000d2b3 0x80000d22 +- 0x0000000a +- >; +- }; +- +- timing-300000000 { +- clock-frequency = <300000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73340000>; +- nvidia,emc-cfg-2 = <0x000008d5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200000>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000321>; +- nvidia,emc-mrs-wait-cnt = <0x0173000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x01231339>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x0000000d 0x0000004d +- 0x00000000 0x00000009 +- 0x00000003 0x00000004 +- 0x00000008 0x00000002 +- 0x00000009 0x00000003 +- 0x00000003 0x00000002 +- 0x00000002 0x00000000 +- 0x00000003 0x00000003 +- 0x00000005 0x00000002 +- 0x00000000 0x00000002 +- 0x00000007 0x00020000 +- 0x00000003 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000001 +- 0x0000000e 0x00000010 +- 0x00000012 0x000008e4 +- 0x00000000 0x00000239 +- 0x00000001 0x00000008 +- 0x00000001 0x00000000 +- 0x0000004b 0x0000000e +- 0x00000052 0x00000200 +- 0x00000004 0x00000005 +- 0x00000004 0x00000008 +- 0x00000000 0x00000005 +- 0x00000005 0x00000924 +- 0x00000000 0x00000000 +- 0x00000000 0x104ab098 +- 0x002c00a0 0x00008000 +- 0x00030000 0x00030000 +- 0x00030000 0x00030000 +- 0x00030000 0x00030000 +- 0x00030000 0x00030000 +- 0x00030000 0x00030000 +- 0x00030000 0x00030000 +- 0x00030000 0x00030000 +- 0x00030000 0x00030000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00098000 0x00098000 +- 0x00000000 0x00098000 +- 0x00098000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00050000 0x00050000 +- 0x00050000 0x00050000 +- 0x00005000 0x00005000 +- 0x00005000 0x00005000 +- 0x10000280 0x00000000 +- 0x00111111 0x00000000 +- 0x00000000 0x77ffc081 +- 0x00000505 0x81f1f108 +- 0x07070004 0x00000000 +- 0x016eeeee 0x51451420 +- 0x00514514 0x00514514 +- 0x51451400 0x0000003f +- 0x00000096 0x00000000 +- 0x00000100 0x0173000e +- 0x00000000 0x00000003 +- 0x000052a3 0x800012d7 +- 0x00000009 +- >; +- }; +- +- timing-396000000 { +- clock-frequency = <396000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73340000>; +- nvidia,emc-cfg-2 = <0x00000895>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200000>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000521>; +- nvidia,emc-mrs-wait-cnt = <0x015b000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x01231339>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000011 0x00000066 +- 0x00000000 0x0000000c +- 0x00000004 0x00000004 +- 0x00000008 0x00000002 +- 0x0000000a 0x00000004 +- 0x00000004 0x00000002 +- 0x00000002 0x00000000 +- 0x00000003 0x00000003 +- 0x00000005 0x00000002 +- 0x00000000 0x00000001 +- 0x00000008 0x00020000 +- 0x00000003 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x0000000f 0x00000010 +- 0x00000012 0x00000bd1 +- 0x00000000 0x000002f4 +- 0x00000001 0x00000008 +- 0x00000001 0x00000000 +- 0x00000063 0x0000000f +- 0x0000006c 0x00000200 +- 0x00000004 0x00000005 +- 0x00000004 0x0000000b +- 0x00000000 0x00000005 +- 0x00000005 0x00000c11 +- 0x00000000 0x00000000 +- 0x00000000 0x104ab098 +- 0x002c00a0 0x00008000 +- 0x00030000 0x00030000 +- 0x00030000 0x00030000 +- 0x00030000 0x00030000 +- 0x00030000 0x00030000 +- 0x00030000 0x00030000 +- 0x00030000 0x00030000 +- 0x00030000 0x00030000 +- 0x00030000 0x00030000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00070000 0x00070000 +- 0x00000000 0x00070000 +- 0x00070000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00038000 0x00038000 +- 0x00038000 0x00038000 +- 0x00003800 0x00003800 +- 0x00003800 0x00003800 +- 0x10000280 0x00000000 +- 0x00111111 0x00000000 +- 0x00000000 0x77ffc081 +- 0x00000505 0x81f1f108 +- 0x07070004 0x00000000 +- 0x016eeeee 0x51451420 +- 0x00514514 0x00514514 +- 0x51451400 0x0000003f +- 0x000000c6 0x00000000 +- 0x00000100 0x015b000e +- 0x00000000 0x00000003 +- 0x000052a3 0x8000188b +- 0x00000009 +- >; +- }; +- +- timing-528000000 { +- clock-frequency = <528000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73300000>; +- nvidia,emc-cfg-2 = <0x0000089d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000941>; +- nvidia,emc-mrs-wait-cnt = <0x0139000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000018 0x00000088 +- 0x00000000 0x00000010 +- 0x00000006 0x00000006 +- 0x00000009 0x00000002 +- 0x0000000d 0x00000006 +- 0x00000006 0x00000002 +- 0x00000002 0x00000000 +- 0x00000003 0x00000003 +- 0x00000006 0x00000002 +- 0x00000000 0x00000001 +- 0x00000009 0x00030000 +- 0x00000003 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000010 0x00000012 +- 0x00000014 0x00000fd6 +- 0x00000000 0x000003f5 +- 0x00000002 0x0000000b +- 0x00000001 0x00000000 +- 0x00000085 0x00000012 +- 0x00000090 0x00000200 +- 0x00000004 0x00000005 +- 0x00000004 0x00000010 +- 0x00000000 0x00000006 +- 0x00000006 0x00001017 +- 0x00000000 0x00000000 +- 0x00000000 0x104ab098 +- 0xe01200b1 0x00008000 +- 0x0000000a 0x0000000a +- 0x0000000a 0x0000000a +- 0x0000000a 0x0000000a +- 0x0000000a 0x0000000a +- 0x0000000a 0x0000000a +- 0x0000000a 0x0000000a +- 0x0000000a 0x0000000a +- 0x0000000a 0x0000000a +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00054000 0x00054000 +- 0x00000000 0x00054000 +- 0x00054000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x0000000c 0x0000000c +- 0x0000000c 0x0000000c +- 0x0000000c 0x0000000c +- 0x0000000c 0x0000000c +- 0x100002a0 0x00000000 +- 0x00111111 0x00000000 +- 0x00000000 0x77ffc085 +- 0x00000505 0x81f1f108 +- 0x07070004 0x00000000 +- 0x016eeeee 0x51451420 +- 0x00514514 0x00514514 +- 0x51451400 0x0606003f +- 0x00000000 0x00000000 +- 0x00000100 0x0139000e +- 0x00000000 0x00000003 +- 0x000042a0 0x80002062 +- 0x0000000a +- >; +- }; +- +- timing-600000000 { +- clock-frequency = <600000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73300000>; +- nvidia,emc-cfg-2 = <0x0000089d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200010>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000b61>; +- nvidia,emc-mrs-wait-cnt = <0x0127000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x0000001b 0x0000009b +- 0x00000000 0x00000013 +- 0x00000007 0x00000007 +- 0x0000000b 0x00000003 +- 0x00000010 0x00000007 +- 0x00000007 0x00000002 +- 0x00000002 0x00000000 +- 0x00000005 0x00000005 +- 0x0000000a 0x00000002 +- 0x00000000 0x00000003 +- 0x0000000b 0x00070000 +- 0x00000003 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000002 +- 0x00000012 0x00000016 +- 0x00000018 0x00001208 +- 0x00000000 0x00000482 +- 0x00000002 0x0000000d +- 0x00000001 0x00000000 +- 0x00000097 0x00000015 +- 0x000000a3 0x00000200 +- 0x00000004 0x00000005 +- 0x00000004 0x00000013 +- 0x00000000 0x00000006 +- 0x00000006 0x00001248 +- 0x00000000 0x00000000 +- 0x00000000 0x104ab098 +- 0xe00e00b1 0x00008000 +- 0x0000000a 0x0000000a +- 0x0000000a 0x0000000a +- 0x0000000a 0x0000000a +- 0x0000000a 0x0000000a +- 0x0000000a 0x0000000a +- 0x0000000a 0x0000000a +- 0x0000000a 0x0000000a +- 0x0000000a 0x0000000a +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00048000 0x00048000 +- 0x00000000 0x00048000 +- 0x00048000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x0000000d 0x0000000d +- 0x0000000d 0x0000000d +- 0x0000000d 0x0000000d +- 0x0000000d 0x0000000d +- 0x100002a0 0x00000000 +- 0x00111111 0x00000000 +- 0x00000000 0x77ffc085 +- 0x00000505 0x81f1f108 +- 0x07070004 0x00000000 +- 0x016eeeee 0x51451420 +- 0x00514514 0x00514514 +- 0x51451400 0x0606003f +- 0x00000000 0x00000000 +- 0x00000100 0x0127000e +- 0x00000000 0x00000003 +- 0x000040a0 0x800024aa +- 0x0000000e +- >; +- }; +- +- timing-792000000 { +- clock-frequency = <792000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73300000>; +- nvidia,emc-cfg-2 = <0x0000089d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200018>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000d71>; +- nvidia,emc-mrs-wait-cnt = <0x00f7000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040000>; +- nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000024 0x000000cd +- 0x00000000 0x00000019 +- 0x0000000a 0x00000008 +- 0x0000000d 0x00000004 +- 0x00000013 0x0000000a +- 0x0000000a 0x00000004 +- 0x00000002 0x00000000 +- 0x00000006 0x00000006 +- 0x0000000b 0x00000002 +- 0x00000000 0x00000002 +- 0x0000000d 0x00080000 +- 0x00000004 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000001 +- 0x00000014 0x00000018 +- 0x0000001a 0x000017e2 +- 0x00000000 0x000005f8 +- 0x00000003 0x00000011 +- 0x00000001 0x00000000 +- 0x000000c7 0x00000018 +- 0x000000d7 0x00000200 +- 0x00000005 0x00000006 +- 0x00000005 0x00000019 +- 0x00000000 0x00000008 +- 0x00000008 0x00001822 +- 0x00000000 0x00000000 +- 0x00000000 0x104ab098 +- 0xe00700b1 0x00008000 +- 0x007fc008 0x007fc008 +- 0x007fc008 0x007fc008 +- 0x007fc008 0x007fc008 +- 0x007fc008 0x007fc008 +- 0x007fc008 0x007fc008 +- 0x007fc008 0x007fc008 +- 0x007fc008 0x007fc008 +- 0x007fc008 0x007fc008 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00034000 0x00034000 +- 0x00000000 0x00034000 +- 0x00034000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000005 0x00000005 +- 0x00000005 0x00000005 +- 0x00000005 0x00000005 +- 0x00000005 0x00000005 +- 0x00000005 0x00000005 +- 0x00000005 0x00000005 +- 0x00000005 0x00000005 +- 0x00000005 0x00000005 +- 0x0000000a 0x0000000a +- 0x0000000a 0x0000000a +- 0x0000000a 0x0000000a +- 0x0000000a 0x0000000a +- 0x100002a0 0x00000000 +- 0x00111111 0x00000000 +- 0x00000000 0x77ffc085 +- 0x00000000 0x81f1f108 +- 0x07070004 0x00000000 +- 0x016eeeee 0x61861820 +- 0x00514514 0x00514514 +- 0x61861800 0x0606003f +- 0x00000000 0x00000000 +- 0x00000100 0x00f7000e +- 0x00000000 0x00000004 +- 0x00004080 0x80003012 +- 0x0000000f +- >; +- }; +- +- timing-924000000 { +- clock-frequency = <924000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430303>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73300000>; +- nvidia,emc-cfg-2 = <0x0000089d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200020>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000f15>; +- nvidia,emc-mrs-wait-cnt = <0x00cd000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040000>; +- nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; +- nvidia,emc-zcal-cnt-long = <0x0000004c>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x0000002b 0x000000f0 +- 0x00000000 0x0000001e +- 0x0000000b 0x00000009 +- 0x0000000f 0x00000005 +- 0x00000016 0x0000000b +- 0x0000000b 0x00000004 +- 0x00000002 0x00000000 +- 0x00000007 0x00000007 +- 0x0000000d 0x00000002 +- 0x00000000 0x00000002 +- 0x0000000f 0x000a0000 +- 0x00000004 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000001 +- 0x00000016 0x0000001a +- 0x0000001c 0x00001be7 +- 0x00000000 0x000006f9 +- 0x00000004 0x00000015 +- 0x00000001 0x00000000 +- 0x000000e7 0x0000001b +- 0x000000fb 0x00000200 +- 0x00000006 0x00000007 +- 0x00000006 0x0000001e +- 0x00000000 0x0000000a +- 0x0000000a 0x00001c28 +- 0x00000000 0x00000000 +- 0x00000000 0x104ab898 +- 0xe00400b1 0x00008000 +- 0x007f800a 0x007f800a +- 0x007f800a 0x007f800a +- 0x007f800a 0x007f800a +- 0x007f800a 0x007f800a +- 0x007f800a 0x007f800a +- 0x007f800a 0x007f800a +- 0x007f800a 0x007f800a +- 0x007f800a 0x007f800a +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x0002c000 0x0002c000 +- 0x00000000 0x0002c000 +- 0x0002c000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000000 0x00000000 +- 0x00000004 0x00000004 +- 0x00000004 0x00000004 +- 0x00000004 0x00000004 +- 0x00000004 0x00000004 +- 0x00000004 0x00000004 +- 0x00000004 0x00000004 +- 0x00000004 0x00000004 +- 0x00000004 0x00000004 +- 0x00000008 0x00000008 +- 0x00000008 0x00000008 +- 0x00000008 0x00000008 +- 0x00000008 0x00000008 +- 0x100002a0 0x00000000 +- 0x00111111 0x00000000 +- 0x00000000 0x77ffc085 +- 0x00000000 0x81f1f108 +- 0x07070004 0x00000000 +- 0x016eeeee 0x5d75d720 +- 0x00514514 0x00514514 +- 0x5d75d700 0x0606003f +- 0x00000000 0x00000000 +- 0x00000128 0x00cd000e +- 0x00000000 0x00000004 +- 0x00004080 0x800037ea +- 0x00000011 +- >; +- }; +- +- }; +- }; +- +- memory-controller@70019000 { +- emc-timings-1 { +- nvidia,ram-code = <1>; +- +- timing-12750000 { +- clock-frequency = <12750000>; +- +- nvidia,emem-configuration = < +- 0x40040001 0x8000000a +- 0x00000001 0x00000001 +- 0x00000002 0x00000000 +- 0x00000002 0x00000001 +- 0x00000003 0x00000008 +- 0x00000003 0x00000002 +- 0x00000003 0x00000006 +- 0x06030203 0x000a0502 +- 0x77e30303 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-20400000 { +- clock-frequency = <20400000>; +- +- nvidia,emem-configuration = < +- 0x40020001 0x80000012 +- 0x00000001 0x00000001 +- 0x00000002 0x00000000 +- 0x00000002 0x00000001 +- 0x00000003 0x00000008 +- 0x00000003 0x00000002 +- 0x00000003 0x00000006 +- 0x06030203 0x000a0502 +- 0x76230303 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-40800000 { +- clock-frequency = <40800000>; +- +- nvidia,emem-configuration = < +- 0xa0000001 0x80000017 +- 0x00000001 0x00000001 +- 0x00000002 0x00000000 +- 0x00000002 0x00000001 +- 0x00000003 0x00000008 +- 0x00000003 0x00000002 +- 0x00000003 0x00000006 +- 0x06030203 0x000a0502 +- 0x74a30303 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-68000000 { +- clock-frequency = <68000000>; +- +- nvidia,emem-configuration = < +- 0x00000001 0x8000001e +- 0x00000001 0x00000001 +- 0x00000002 0x00000000 +- 0x00000002 0x00000001 +- 0x00000003 0x00000008 +- 0x00000003 0x00000002 +- 0x00000003 0x00000006 +- 0x06030203 0x000a0502 +- 0x74230403 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-102000000 { +- clock-frequency = <102000000>; +- +- nvidia,emem-configuration = < +- 0x08000001 0x80000026 +- 0x00000001 0x00000001 +- 0x00000003 0x00000000 +- 0x00000002 0x00000001 +- 0x00000003 0x00000008 +- 0x00000003 0x00000002 +- 0x00000003 0x00000006 +- 0x06030203 0x000a0503 +- 0x73c30504 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-204000000 { +- clock-frequency = <204000000>; +- +- nvidia,emem-configuration = < +- 0x01000003 0x80000040 +- 0x00000001 0x00000001 +- 0x00000004 0x00000002 +- 0x00000003 0x00000001 +- 0x00000003 0x00000008 +- 0x00000003 0x00000002 +- 0x00000004 0x00000006 +- 0x06040203 0x000a0504 +- 0x73840a05 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-300000000 { +- clock-frequency = <300000000>; +- +- nvidia,emem-configuration = < +- 0x08000004 0x80000040 +- 0x00000001 0x00000002 +- 0x00000007 0x00000004 +- 0x00000004 0x00000001 +- 0x00000002 0x00000007 +- 0x00000002 0x00000002 +- 0x00000004 0x00000006 +- 0x06040202 0x000b0607 +- 0x77450e08 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-396000000 { +- clock-frequency = <396000000>; +- +- nvidia,emem-configuration = < +- 0x0f000005 0x80000040 +- 0x00000001 0x00000002 +- 0x00000009 0x00000005 +- 0x00000006 0x00000001 +- 0x00000002 0x00000008 +- 0x00000002 0x00000002 +- 0x00000004 0x00000006 +- 0x06040202 0x000d0709 +- 0x7586120a 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-528000000 { +- clock-frequency = <528000000>; +- +- nvidia,emem-configuration = < +- 0x0f000007 0x80000040 +- 0x00000002 0x00000003 +- 0x0000000c 0x00000007 +- 0x00000008 0x00000001 +- 0x00000002 0x00000009 +- 0x00000002 0x00000002 +- 0x00000005 0x00000006 +- 0x06050202 0x0010090c +- 0x7428180d 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-600000000 { +- clock-frequency = <600000000>; +- +- nvidia,emem-configuration = < +- 0x00000009 0x80000040 +- 0x00000003 0x00000004 +- 0x0000000e 0x00000009 +- 0x0000000a 0x00000001 +- 0x00000003 0x0000000b +- 0x00000002 0x00000002 +- 0x00000005 0x00000007 +- 0x07050202 0x00130b0e +- 0x73a91b0f 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-792000000 { +- clock-frequency = <792000000>; +- +- nvidia,emem-configuration = < +- 0x0e00000b 0x80000040 +- 0x00000004 0x00000005 +- 0x00000013 0x0000000c +- 0x0000000d 0x00000002 +- 0x00000003 0x0000000c +- 0x00000002 0x00000002 +- 0x00000006 0x00000008 +- 0x08060202 0x00170e13 +- 0x736c2414 0x70000f02 +- 0x001f0000 +- >; +- }; +- +- timing-924000000 { +- clock-frequency = <924000000>; +- +- nvidia,emem-configuration = < +- 0x0e00000d 0x80000040 +- 0x00000005 0x00000006 +- 0x00000016 0x0000000e +- 0x0000000f 0x00000002 +- 0x00000004 0x0000000e +- 0x00000002 0x00000002 +- 0x00000006 0x00000009 +- 0x09060202 0x001a1016 +- 0x734e2a17 0x70000f02 +- 0x001f0000 +- >; +- }; +- }; +- }; +-}; +- +-&emc_icc_dvfs_opp_table { +- /delete-node/ opp@1200000000,1100; +-}; +- +-&emc_bw_dfs_opp_table { +- /delete-node/ opp@1200000000; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra124-apalis-eval.dts b/scripts/dtc/include-prefixes/arm/tegra124-apalis-eval.dts +deleted file mode 100644 +index 28c29b6813a7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra124-apalis-eval.dts ++++ /dev/null +@@ -1,255 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright 2016-2019 Toradex AG +- */ +- +-/dts-v1/; +- +-#include +-#include "tegra124-apalis.dtsi" +- +-/ { +- model = "Toradex Apalis TK1 on Apalis Evaluation Board"; +- compatible = "toradex,apalis-tk1-eval", "toradex,apalis-tk1", +- "nvidia,tegra124"; +- +- aliases { +- rtc0 = "/i2c@7000c000/rtc@68"; +- rtc1 = "/i2c@7000d000/pmic@40"; +- rtc2 = "/rtc@7000e000"; +- serial0 = &uarta; +- serial1 = &uartb; +- serial2 = &uartc; +- serial3 = &uartd; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- pcie@1003000 { +- pci@1,0 { +- status = "okay"; +- }; +- }; +- +- host1x@50000000 { +- hdmi@54280000 { +- status = "okay"; +- hdmi-supply = <®_5v0>; +- }; +- }; +- +- /* Apalis UART1 */ +- serial@70006000 { +- status = "okay"; +- }; +- +- /* Apalis UART2 */ +- serial@70006040 { +- status = "okay"; +- }; +- +- /* Apalis UART3 */ +- serial@70006200 { +- status = "okay"; +- }; +- +- /* Apalis UART4 */ +- serial@70006300 { +- status = "okay"; +- }; +- +- pwm@7000a000 { +- status = "okay"; +- }; +- +- /* +- * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier +- * board) +- */ +- i2c@7000c000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- pcie-switch@58 { +- compatible = "plx,pex8605"; +- reg = <0x58>; +- }; +- +- /* M41T0M6 real time clock on carrier board */ +- rtc@68 { +- compatible = "st,m41t0"; +- reg = <0x68>; +- }; +- }; +- +- /* +- * GEN2_I2C: I2C2_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID) +- */ +- i2c@7000c400 { +- status = "okay"; +- }; +- +- /* +- * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor +- * on carrier board) +- */ +- i2c@7000c500 { +- status = "okay"; +- clock-frequency = <400000>; +- }; +- +- /* I2C4 (DDC): unused */ +- +- /* SPI1: Apalis SPI1 */ +- spi@7000d400 { +- status = "okay"; +- spi-max-frequency = <50000000>; +- }; +- +- /* SPI4: Apalis SPI2 */ +- spi@7000da00 { +- status = "okay"; +- spi-max-frequency = <50000000>; +- }; +- +- /* Apalis Serial ATA */ +- sata@70020000 { +- status = "okay"; +- target-5v-supply = <®_5v0>; +- target-12v-supply = <®_12v0>; +- }; +- +- hda@70030000 { +- status = "okay"; +- }; +- +- usb@70090000 { +- status = "okay"; +- }; +- +- /* Apalis MMC1 */ +- mmc@700b0000 { +- status = "okay"; +- bus-width = <4>; +- /* MMC1_CD# */ +- cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; +- vqmmc-supply = <&vddio_sdmmc1>; +- }; +- +- /* Apalis SD1 */ +- mmc@700b0400 { +- status = "okay"; +- bus-width = <4>; +- /* SD1_CD# */ +- cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; +- vqmmc-supply = <&vddio_sdmmc3>; +- }; +- +- /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ +- usb@7d000000 { +- status = "okay"; +- dr_mode = "otg"; +- }; +- +- usb-phy@7d000000 { +- status = "okay"; +- vbus-supply = <®_usbo1_vbus>; +- }; +- +- /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ +- usb@7d004000 { +- status = "okay"; +- }; +- +- usb-phy@7d004000 { +- status = "okay"; +- vbus-supply = <®_usbh_vbus>; +- }; +- +- /* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */ +- usb@7d008000 { +- status = "okay"; +- }; +- +- usb-phy@7d008000 { +- status = "okay"; +- vbus-supply = <®_usbh_vbus>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- brightness-levels = <255 231 223 207 191 159 127 0>; +- default-brightness-level = <6>; +- /* BKL1_ON */ +- enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; +- power-supply = <®_3v3>; +- pwms = <&pwm 3 5000000>; /* BKL1_PWM */ +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- wakeup { +- label = "WAKE1_MICO"; +- gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3.3V_SW"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_5v0: regulator-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "5V_SW"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_12v0: regulator-12v0 { +- compatible = "regulator-fixed"; +- regulator-name = "12V_SW"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- /* USBO1_EN */ +- reg_usbo1_vbus: regulator-usbo1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_USBO1"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_5v0>; +- }; +- +- /* USBH_EN */ +- reg_usbh_vbus: regulator-usbh-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_5v0>; +- }; +-}; +- +-&gpio { +- /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ +- pex-perst-n { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "PEX_PERST_N"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra124-apalis-v1.2-eval.dts b/scripts/dtc/include-prefixes/arm/tegra124-apalis-v1.2-eval.dts +deleted file mode 100644 +index f3afde410615..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra124-apalis-v1.2-eval.dts ++++ /dev/null +@@ -1,257 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-/* +- * Copyright 2016-2018 Toradex AG +- */ +- +-/dts-v1/; +- +-#include +-#include "tegra124-apalis-v1.2.dtsi" +- +-/ { +- model = "Toradex Apalis TK1 on Apalis Evaluation Board"; +- compatible = "toradex,apalis-tk1-v1.2-eval", "toradex,apalis-tk1-eval", +- "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1", +- "nvidia,tegra124"; +- +- aliases { +- rtc0 = "/i2c@7000c000/rtc@68"; +- rtc1 = "/i2c@7000d000/pmic@40"; +- rtc2 = "/rtc@7000e000"; +- serial0 = &uarta; +- serial1 = &uartb; +- serial2 = &uartc; +- serial3 = &uartd; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- pcie@1003000 { +- pci@1,0 { +- status = "okay"; +- }; +- }; +- +- host1x@50000000 { +- hdmi@54280000 { +- status = "okay"; +- hdmi-supply = <®_5v0>; +- }; +- }; +- +- /* Apalis UART1 */ +- serial@70006000 { +- status = "okay"; +- }; +- +- /* Apalis UART2 */ +- serial@70006040 { +- status = "okay"; +- }; +- +- /* Apalis UART3 */ +- serial@70006200 { +- status = "okay"; +- }; +- +- /* Apalis UART4 */ +- serial@70006300 { +- status = "okay"; +- }; +- +- pwm@7000a000 { +- status = "okay"; +- }; +- +- /* +- * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier +- * board) +- */ +- i2c@7000c000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- pcie-switch@58 { +- compatible = "plx,pex8605"; +- reg = <0x58>; +- }; +- +- /* M41T0M6 real time clock on carrier board */ +- rtc@68 { +- compatible = "st,m41t0"; +- reg = <0x68>; +- }; +- }; +- +- /* GEN2_I2C: unused */ +- +- /* +- * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor +- * on carrier board) +- */ +- i2c@7000c500 { +- status = "okay"; +- clock-frequency = <400000>; +- }; +- +- /* +- * I2C4 (DDC): I2C4_SDA/SCL (DDC) on MXM3 pin 205/207 +- * (e.g. display EDID) +- */ +- i2c@7000c700 { +- status = "okay"; +- }; +- +- /* SPI1: Apalis SPI1 */ +- spi@7000d400 { +- status = "okay"; +- spi-max-frequency = <50000000>; +- }; +- +- /* SPI4: Apalis SPI2 */ +- spi@7000da00 { +- status = "okay"; +- spi-max-frequency = <50000000>; +- }; +- +- /* Apalis Serial ATA */ +- sata@70020000 { +- status = "okay"; +- target-5v-supply = <®_5v0>; +- target-12v-supply = <®_12v0>; +- }; +- +- hda@70030000 { +- status = "okay"; +- }; +- +- usb@70090000 { +- status = "okay"; +- }; +- +- /* Apalis MMC1 */ +- mmc@700b0000 { +- status = "okay"; +- bus-width = <4>; +- /* MMC1_CD# */ +- cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; +- vqmmc-supply = <&vddio_sdmmc1>; +- }; +- +- /* Apalis SD1 */ +- mmc@700b0400 { +- status = "okay"; +- bus-width = <4>; +- /* SD1_CD# */ +- cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; +- vqmmc-supply = <&vddio_sdmmc3>; +- }; +- +- /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ +- usb@7d000000 { +- status = "okay"; +- dr_mode = "otg"; +- }; +- +- usb-phy@7d000000 { +- status = "okay"; +- vbus-supply = <®_usbo1_vbus>; +- }; +- +- /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ +- usb@7d004000 { +- status = "okay"; +- }; +- +- usb-phy@7d004000 { +- status = "okay"; +- vbus-supply = <®_usbh_vbus>; +- }; +- +- /* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */ +- usb@7d008000 { +- status = "okay"; +- }; +- +- usb-phy@7d008000 { +- status = "okay"; +- vbus-supply = <®_usbh_vbus>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- brightness-levels = <255 231 223 207 191 159 127 0>; +- default-brightness-level = <6>; +- /* BKL1_ON */ +- enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; +- power-supply = <®_3v3>; +- pwms = <&pwm 3 5000000>; /* BKL1_PWM */ +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- wakeup { +- label = "WAKE1_MICO"; +- gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3.3V_SW"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_5v0: regulator-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "5V_SW"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_12v0: regulator-12v0 { +- compatible = "regulator-fixed"; +- regulator-name = "12V_SW"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- /* USBO1_EN */ +- reg_usbo1_vbus: regulator-usbo1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_USBO1"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_5v0>; +- }; +- +- /* USBH_EN */ +- reg_usbh_vbus: regulator-usbh-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_5v0>; +- }; +-}; +- +-&gpio { +- /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ +- pex-perst-n { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "PEX_PERST_N"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra124-apalis-v1.2.dtsi b/scripts/dtc/include-prefixes/arm/tegra124-apalis-v1.2.dtsi +deleted file mode 100644 +index cde9ae8fa04b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra124-apalis-v1.2.dtsi ++++ /dev/null +@@ -1,2072 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-/* +- * Copyright 2016-2018 Toradex AG +- */ +- +-#include "tegra124.dtsi" +-#include "tegra124-apalis-emc.dtsi" +- +-/* +- * Toradex Apalis TK1 Module Device Tree +- * Compatible for Revisions 2GB: V1.2A +- */ +-/ { +- memory@80000000 { +- reg = <0x0 0x80000000 0x0 0x80000000>; +- }; +- +- pcie@1003000 { +- status = "okay"; +- +- avddio-pex-supply = <®_1v05_vdd>; +- avdd-pex-pll-supply = <®_1v05_vdd>; +- avdd-pll-erefe-supply = <®_1v05_avdd>; +- dvddio-pex-supply = <®_1v05_vdd>; +- hvdd-pex-pll-e-supply = <®_module_3v3>; +- hvdd-pex-supply = <®_module_3v3>; +- vddio-pex-ctl-supply = <®_module_3v3>; +- +- /* Apalis PCIe (additional lane Apalis type specific) */ +- pci@1,0 { +- /* PCIE1_RX/TX and TS_DIFF1/2 */ +- phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>, +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; +- phy-names = "pcie-0", "pcie-1"; +- }; +- +- /* I210 Gigabit Ethernet Controller (On-module) */ +- pci@2,0 { +- phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; +- phy-names = "pcie-0"; +- status = "okay"; +- +- ethernet@0,0 { +- reg = <0 0 0 0 0>; +- local-mac-address = [00 00 00 00 00 00]; +- }; +- }; +- }; +- +- host1x@50000000 { +- hdmi@54280000 { +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = +- <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; +- pll-supply = <®_1v05_avdd_hdmi_pll>; +- vdd-supply = <®_3v3_avdd_hdmi>; +- }; +- }; +- +- gpu@0,57000000 { +- /* +- * Node left disabled on purpose - the bootloader will enable +- * it after having set the VPR up +- */ +- vdd-supply = <®_vdd_gpu>; +- }; +- +- pinmux@70000868 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- /* Analogue Audio (On-module) */ +- dap3-fs-pp0 { +- nvidia,pins = "dap3_fs_pp0"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3-din-pp1 { +- nvidia,pins = "dap3_din_pp1"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3-dout-pp2 { +- nvidia,pins = "dap3_dout_pp2"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3-sclk-pp3 { +- nvidia,pins = "dap3_sclk_pp3"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap-mclk1-pw4 { +- nvidia,pins = "dap_mclk1_pw4"; +- nvidia,function = "extperiph1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis BKL1_ON */ +- pbb5 { +- nvidia,pins = "pbb5"; +- nvidia,function = "vgp5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis BKL1_PWM */ +- pu6 { +- nvidia,pins = "pu6"; +- nvidia,function = "pwm3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis CAM1_MCLK */ +- cam-mclk-pcc0 { +- nvidia,pins = "cam_mclk_pcc0"; +- nvidia,function = "vi_alt3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis Digital Audio */ +- dap2-fs-pa2 { +- nvidia,pins = "dap2_fs_pa2"; +- nvidia,function = "hda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2-sclk-pa3 { +- nvidia,pins = "dap2_sclk_pa3"; +- nvidia,function = "hda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2-din-pa4 { +- nvidia,pins = "dap2_din_pa4"; +- nvidia,function = "hda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2-dout-pa5 { +- nvidia,pins = "dap2_dout_pa5"; +- nvidia,function = "hda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb3 { /* DAP1_RESET */ +- nvidia,pins = "pbb3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3-out-pee0 { +- nvidia,pins = "clk3_out_pee0"; +- nvidia,function = "extperiph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis GPIO */ +- usb-vbus-en0-pn4 { +- nvidia,pins = "usb_vbus_en0_pn4"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- usb-vbus-en1-pn5 { +- nvidia,pins = "usb_vbus_en1_pn5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pex-l0-rst-n-pdd1 { +- nvidia,pins = "pex_l0_rst_n_pdd1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex-l0-clkreq-n-pdd2 { +- nvidia,pins = "pex_l0_clkreq_n_pdd2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex-l1-rst-n-pdd5 { +- nvidia,pins = "pex_l1_rst_n_pdd5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex-l1-clkreq-n-pdd6 { +- nvidia,pins = "pex_l1_clkreq_n_pdd6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dp-hpd-pff0 { +- nvidia,pins = "dp_hpd_pff0"; +- nvidia,function = "dp"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pff2 { +- nvidia,pins = "pff2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */ +- nvidia,pins = "owr"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,rcv-sel = ; +- }; +- +- /* Apalis HDMI1_CEC */ +- hdmi-cec-pee3 { +- nvidia,pins = "hdmi_cec_pee3"; +- nvidia,function = "cec"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* Apalis HDMI1_HPD */ +- hdmi-int-pn7 { +- nvidia,pins = "hdmi_int_pn7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,rcv-sel = ; +- }; +- +- /* Apalis I2C1 */ +- gen1-i2c-scl-pc4 { +- nvidia,pins = "gen1_i2c_scl_pc4"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen1-i2c-sda-pc5 { +- nvidia,pins = "gen1_i2c_sda_pc5"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* Apalis I2C3 (CAM) */ +- cam-i2c-scl-pbb1 { +- nvidia,pins = "cam_i2c_scl_pbb1"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam-i2c-sda-pbb2 { +- nvidia,pins = "cam_i2c_sda_pbb2"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* Apalis I2C4 (DDC) */ +- ddc-scl-pv4 { +- nvidia,pins = "ddc_scl_pv4"; +- nvidia,function = "i2c4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,rcv-sel = ; +- }; +- ddc-sda-pv5 { +- nvidia,pins = "ddc_sda_pv5"; +- nvidia,function = "i2c4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,rcv-sel = ; +- }; +- +- /* Apalis MMC1 */ +- sdmmc1-cd-n-pv3 { /* CD# GPIO */ +- nvidia,pins = "sdmmc1_wp_n_pv3"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2-out-pw5 { /* D5 GPIO */ +- nvidia,pins = "clk2_out_pw5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1-dat3-py4 { +- nvidia,pins = "sdmmc1_dat3_py4"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1-dat2-py5 { +- nvidia,pins = "sdmmc1_dat2_py5"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1-dat1-py6 { +- nvidia,pins = "sdmmc1_dat1_py6"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1-dat0-py7 { +- nvidia,pins = "sdmmc1_dat0_py7"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1-clk-pz0 { +- nvidia,pins = "sdmmc1_clk_pz0"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1-cmd-pz1 { +- nvidia,pins = "sdmmc1_cmd_pz1"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2-req-pcc5 { /* D4 GPIO */ +- nvidia,pins = "clk2_req_pcc5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */ +- nvidia,pins = "sdmmc3_clk_lb_in_pee5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- usb-vbus-en2-pff1 { /* D7 GPIO */ +- nvidia,pins = "usb_vbus_en2_pff1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis PWM */ +- ph0 { +- nvidia,pins = "ph0"; +- nvidia,function = "pwm0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph1 { +- nvidia,pins = "ph1"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph2 { +- nvidia,pins = "ph2"; +- nvidia,function = "pwm2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ +- ph3 { +- nvidia,pins = "ph3"; +- nvidia,function = "pwm3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis SATA1_ACT# */ +- dap1-dout-pn2 { +- nvidia,pins = "dap1_dout_pn2"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis SD1 */ +- sdmmc3-clk-pa6 { +- nvidia,pins = "sdmmc3_clk_pa6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3-cmd-pa7 { +- nvidia,pins = "sdmmc3_cmd_pa7"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3-dat3-pb4 { +- nvidia,pins = "sdmmc3_dat3_pb4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3-dat2-pb5 { +- nvidia,pins = "sdmmc3_dat2_pb5"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3-dat1-pb6 { +- nvidia,pins = "sdmmc3_dat1_pb6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3-dat0-pb7 { +- nvidia,pins = "sdmmc3_dat0_pb7"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3-cd-n-pv2 { /* CD# GPIO */ +- nvidia,pins = "sdmmc3_cd_n_pv2"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis SPDIF */ +- spdif-out-pk5 { +- nvidia,pins = "spdif_out_pk5"; +- nvidia,function = "spdif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spdif-in-pk6 { +- nvidia,pins = "spdif_in_pk6"; +- nvidia,function = "spdif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis SPI1 */ +- ulpi-clk-py0 { +- nvidia,pins = "ulpi_clk_py0"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi-dir-py1 { +- nvidia,pins = "ulpi_dir_py1"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi-nxt-py2 { +- nvidia,pins = "ulpi_nxt_py2"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi-stp-py3 { +- nvidia,pins = "ulpi_stp_py3"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis SPI2 */ +- pg5 { +- nvidia,pins = "pg5"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg6 { +- nvidia,pins = "pg6"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg7 { +- nvidia,pins = "pg7"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi3 { +- nvidia,pins = "pi3"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis UART1 */ +- pb1 { /* DCD GPIO */ +- nvidia,pins = "pb1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk7 { /* RI GPIO */ +- nvidia,pins = "pk7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart1-txd-pu0 { +- nvidia,pins = "pu0"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart1-rxd-pu1 { +- nvidia,pins = "pu1"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart1-cts-n-pu2 { +- nvidia,pins = "pu2"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart1-rts-n-pu3 { +- nvidia,pins = "pu3"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3-cts-n-pa1 { /* DSR GPIO */ +- nvidia,pins = "uart3_cts_n_pa1"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3-rts-n-pc0 { /* DTR GPIO */ +- nvidia,pins = "uart3_rts_n_pc0"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis UART2 */ +- uart2-txd-pc2 { +- nvidia,pins = "uart2_txd_pc2"; +- nvidia,function = "irda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2-rxd-pc3 { +- nvidia,pins = "uart2_rxd_pc3"; +- nvidia,function = "irda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2-cts-n-pj5 { +- nvidia,pins = "uart2_cts_n_pj5"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2-rts-n-pj6 { +- nvidia,pins = "uart2_rts_n_pj6"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis UART3 */ +- uart3-txd-pw6 { +- nvidia,pins = "uart3_txd_pw6"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3-rxd-pw7 { +- nvidia,pins = "uart3_rxd_pw7"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis UART4 */ +- uart4-rxd-pb0 { +- nvidia,pins = "pb0"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart4-txd-pj7 { +- nvidia,pins = "pj7"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis USBH_EN */ +- gen2-i2c-sda-pt6 { +- nvidia,pins = "gen2_i2c_sda_pt6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* Apalis USBH_OC# */ +- pbb0 { +- nvidia,pins = "pbb0"; +- nvidia,function = "vgp6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis USBO1_EN */ +- gen2-i2c-scl-pt5 { +- nvidia,pins = "gen2_i2c_scl_pt5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* Apalis USBO1_OC# */ +- pbb4 { +- nvidia,pins = "pbb4"; +- nvidia,function = "vgp4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis WAKE1_MICO */ +- pex-wake-n-pdd3 { +- nvidia,pins = "pex_wake_n_pdd3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* CORE_PWR_REQ */ +- core-pwr-req { +- nvidia,pins = "core_pwr_req"; +- nvidia,function = "pwron"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* CPU_PWR_REQ */ +- cpu-pwr-req { +- nvidia,pins = "cpu_pwr_req"; +- nvidia,function = "cpu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* DVFS */ +- dvfs-pwm-px0 { +- nvidia,pins = "dvfs_pwm_px0"; +- nvidia,function = "cldvfs"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dvfs-clk-px2 { +- nvidia,pins = "dvfs_clk_px2"; +- nvidia,function = "cldvfs"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* eMMC */ +- sdmmc4-dat0-paa0 { +- nvidia,pins = "sdmmc4_dat0_paa0"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-dat1-paa1 { +- nvidia,pins = "sdmmc4_dat1_paa1"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-dat2-paa2 { +- nvidia,pins = "sdmmc4_dat2_paa2"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-dat3-paa3 { +- nvidia,pins = "sdmmc4_dat3_paa3"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-dat4-paa4 { +- nvidia,pins = "sdmmc4_dat4_paa4"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-dat5-paa5 { +- nvidia,pins = "sdmmc4_dat5_paa5"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-dat6-paa6 { +- nvidia,pins = "sdmmc4_dat6_paa6"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-dat7-paa7 { +- nvidia,pins = "sdmmc4_dat7_paa7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-clk-pcc4 { +- nvidia,pins = "sdmmc4_clk_pcc4"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-cmd-pt7 { +- nvidia,pins = "sdmmc4_cmd_pt7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* JTAG_RTCK */ +- jtag-rtck { +- nvidia,pins = "jtag_rtck"; +- nvidia,function = "rtck"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* LAN_DEV_OFF# */ +- ulpi-data5-po6 { +- nvidia,pins = "ulpi_data5_po6"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* LAN_RESET# */ +- kb-row10-ps2 { +- nvidia,pins = "kb_row10_ps2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* LAN_WAKE# */ +- ulpi-data4-po5 { +- nvidia,pins = "ulpi_data4_po5"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* MCU_INT1# */ +- pk2 { +- nvidia,pins = "pk2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* MCU_INT2# */ +- pj2 { +- nvidia,pins = "pj2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* MCU_INT3# */ +- pi5 { +- nvidia,pins = "pi5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* MCU_INT4# */ +- pj0 { +- nvidia,pins = "pj0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* MCU_RESET */ +- pbb6 { +- nvidia,pins = "pbb6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* MCU SPI */ +- gpio-x4-aud-px4 { +- nvidia,pins = "gpio_x4_aud_px4"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio-x5-aud-px5 { +- nvidia,pins = "gpio_x5_aud_px5"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio-x6-aud-px6 { /* MCU_CS */ +- nvidia,pins = "gpio_x6_aud_px6"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio-x7-aud-px7 { +- nvidia,pins = "gpio_x7_aud_px7"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio-w2-aud-pw2 { /* MCU_CSEZP */ +- nvidia,pins = "gpio_w2_aud_pw2"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* PMIC_CLK_32K */ +- clk-32k-in { +- nvidia,pins = "clk_32k_in"; +- nvidia,function = "clk"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* PMIC_CPU_OC_INT */ +- clk-32k-out-pa0 { +- nvidia,pins = "clk_32k_out_pa0"; +- nvidia,function = "soc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* PWR_I2C */ +- pwr-i2c-scl-pz6 { +- nvidia,pins = "pwr_i2c_scl_pz6"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pwr-i2c-sda-pz7 { +- nvidia,pins = "pwr_i2c_sda_pz7"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* PWR_INT_N */ +- pwr-int-n { +- nvidia,pins = "pwr_int_n"; +- nvidia,function = "pmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* RESET_MOCI_CTRL */ +- pu4 { +- nvidia,pins = "pu4"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* RESET_OUT_N */ +- reset-out-n { +- nvidia,pins = "reset_out_n"; +- nvidia,function = "reset_out_n"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* SHIFT_CTRL_DIR_IN */ +- kb-row0-pr0 { +- nvidia,pins = "kb_row0_pr0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row1-pr1 { +- nvidia,pins = "kb_row1_pr1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Configure level-shifter as output for HDA */ +- kb-row11-ps3 { +- nvidia,pins = "kb_row11_ps3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* SHIFT_CTRL_DIR_OUT */ +- kb-col5-pq5 { +- nvidia,pins = "kb_col5_pq5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-col6-pq6 { +- nvidia,pins = "kb_col6_pq6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-col7-pq7 { +- nvidia,pins = "kb_col7_pq7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* SHIFT_CTRL_OE */ +- kb-col0-pq0 { +- nvidia,pins = "kb_col0_pq0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-col1-pq1 { +- nvidia,pins = "kb_col1_pq1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-col2-pq2 { +- nvidia,pins = "kb_col2_pq2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-col4-pq4 { +- nvidia,pins = "kb_col4_pq4"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row2-pr2 { +- nvidia,pins = "kb_row2_pr2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */ +- pi6 { +- nvidia,pins = "pi6"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* TOUCH_INT */ +- gpio-w3-aud-pw3 { +- nvidia,pins = "gpio_w3_aud_pw3"; +- nvidia,function = "spi6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- pc7 { /* NC */ +- nvidia,pins = "pc7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg0 { /* NC */ +- nvidia,pins = "pg0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg1 { /* NC */ +- nvidia,pins = "pg1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg2 { /* NC */ +- nvidia,pins = "pg2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg3 { /* NC */ +- nvidia,pins = "pg3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg4 { /* NC */ +- nvidia,pins = "pg4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph4 { /* NC */ +- nvidia,pins = "ph4"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph5 { /* NC */ +- nvidia,pins = "ph5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph6 { /* NC */ +- nvidia,pins = "ph6"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph7 { /* NC */ +- nvidia,pins = "ph7"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi0 { /* NC */ +- nvidia,pins = "pi0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi1 { /* NC */ +- nvidia,pins = "pi1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi2 { /* NC */ +- nvidia,pins = "pi2"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi4 { /* NC */ +- nvidia,pins = "pi4"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi7 { /* NC */ +- nvidia,pins = "pi7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk0 { /* NC */ +- nvidia,pins = "pk0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk1 { /* NC */ +- nvidia,pins = "pk1"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk3 { /* NC */ +- nvidia,pins = "pk3"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk4 { /* NC */ +- nvidia,pins = "pk4"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1-fs-pn0 { /* NC */ +- nvidia,pins = "dap1_fs_pn0"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1-din-pn1 { /* NC */ +- nvidia,pins = "dap1_din_pn1"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1-sclk-pn3 { /* NC */ +- nvidia,pins = "dap1_sclk_pn3"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi-data7-po0 { /* NC */ +- nvidia,pins = "ulpi_data7_po0"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi-data0-po1 { /* NC */ +- nvidia,pins = "ulpi_data0_po1"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi-data1-po2 { /* NC */ +- nvidia,pins = "ulpi_data1_po2"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi-data2-po3 { /* NC */ +- nvidia,pins = "ulpi_data2_po3"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi-data3-po4 { /* NC */ +- nvidia,pins = "ulpi_data3_po4"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi-data6-po7 { /* NC */ +- nvidia,pins = "ulpi_data6_po7"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4-fs-pp4 { /* NC */ +- nvidia,pins = "dap4_fs_pp4"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4-din-pp5 { /* NC */ +- nvidia,pins = "dap4_din_pp5"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4-dout-pp6 { /* NC */ +- nvidia,pins = "dap4_dout_pp6"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4-sclk-pp7 { /* NC */ +- nvidia,pins = "dap4_sclk_pp7"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-col3-pq3 { /* NC */ +- nvidia,pins = "kb_col3_pq3"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row3-pr3 { /* NC */ +- nvidia,pins = "kb_row3_pr3"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row4-pr4 { /* NC */ +- nvidia,pins = "kb_row4_pr4"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row5-pr5 { /* NC */ +- nvidia,pins = "kb_row5_pr5"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row6-pr6 { /* NC */ +- nvidia,pins = "kb_row6_pr6"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row7-pr7 { /* NC */ +- nvidia,pins = "kb_row7_pr7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row8-ps0 { /* NC */ +- nvidia,pins = "kb_row8_ps0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row9-ps1 { /* NC */ +- nvidia,pins = "kb_row9_ps1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row12-ps4 { /* NC */ +- nvidia,pins = "kb_row12_ps4"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row13-ps5 { /* NC */ +- nvidia,pins = "kb_row13_ps5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row14-ps6 { /* NC */ +- nvidia,pins = "kb_row14_ps6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row15-ps7 { /* NC */ +- nvidia,pins = "kb_row15_ps7"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row16-pt0 { /* NC */ +- nvidia,pins = "kb_row16_pt0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row17-pt1 { /* NC */ +- nvidia,pins = "kb_row17_pt1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu5 { /* NC */ +- nvidia,pins = "pu5"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* +- * PCB Version Indication: V1.2 and later have GPIO_PV0 +- * wired to GND, was NC before +- */ +- pv0 { +- nvidia,pins = "pv0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv1 { /* NC */ +- nvidia,pins = "pv1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio-x1-aud-px1 { /* NC */ +- nvidia,pins = "gpio_x1_aud_px1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio-x3-aud-px3 { /* NC */ +- nvidia,pins = "gpio_x3_aud_px3"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb7 { /* NC */ +- nvidia,pins = "pbb7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pcc1 { /* NC */ +- nvidia,pins = "pcc1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pcc2 { /* NC */ +- nvidia,pins = "pcc2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3-req-pee1 { /* NC */ +- nvidia,pins = "clk3_req_pee1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap-mclk1-req-pee2 { /* NC */ +- nvidia,pins = "dap_mclk1_req_pee2"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* +- * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output +- * driver enabled aka not tristated and input driver +- * enabled as well as it features some magic properties +- * even though the external loopback is disabled and the +- * internal loopback used as per +- * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 +- * bits being set to 0xfffd according to the TRM! +- */ +- sdmmc3-clk-lb-out-pee4 { /* NC */ +- nvidia,pins = "sdmmc3_clk_lb_out_pee4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- }; +- }; +- +- serial@70006040 { +- compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; +- }; +- +- serial@70006200 { +- compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; +- }; +- +- serial@70006300 { +- compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; +- }; +- +- hdmi_ddc: i2c@7000c700 { +- clock-frequency = <10000>; +- }; +- +- /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- /* SGTL5000 audio codec */ +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- VDDA-supply = <®_module_3v3_audio>; +- VDDD-supply = <®_1v8_vddio>; +- VDDIO-supply = <®_1v8_vddio>; +- clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; +- }; +- +- pmic: pmic@40 { +- compatible = "ams,as3722"; +- reg = <0x40>; +- interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; +- ams,system-power-controller; +- #interrupt-cells = <2>; +- interrupt-controller; +- gpio-controller; +- #gpio-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&as3722_default>; +- +- as3722_default: pinmux { +- gpio2-7 { +- pins = "gpio2", /* PWR_EN_+V3.3 */ +- "gpio7"; /* +V1.6_LPO */ +- function = "gpio"; +- bias-pull-up; +- }; +- +- gpio0-1-3-4-5-6 { +- pins = "gpio0", "gpio1", "gpio3", +- "gpio4", "gpio5", "gpio6"; +- bias-high-impedance; +- }; +- }; +- +- regulators { +- vsup-sd2-supply = <®_module_3v3>; +- vsup-sd3-supply = <®_module_3v3>; +- vsup-sd4-supply = <®_module_3v3>; +- vsup-sd5-supply = <®_module_3v3>; +- vin-ldo0-supply = <®_1v35_vddio_ddr>; +- vin-ldo1-6-supply = <®_module_3v3>; +- vin-ldo2-5-7-supply = <®_1v8_vddio>; +- vin-ldo3-4-supply = <®_module_3v3>; +- vin-ldo9-10-supply = <®_module_3v3>; +- vin-ldo11-supply = <®_module_3v3>; +- +- reg_vdd_cpu: sd0 { +- regulator-name = "+VDD_CPU_AP"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1400000>; +- regulator-min-microamp = <3500000>; +- regulator-max-microamp = <3500000>; +- regulator-always-on; +- regulator-boot-on; +- ams,ext-control = <2>; +- }; +- +- sd1 { +- regulator-name = "+VDD_CORE"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-min-microamp = <2500000>; +- regulator-max-microamp = <4000000>; +- regulator-always-on; +- regulator-boot-on; +- ams,ext-control = <1>; +- }; +- +- reg_1v35_vddio_ddr: sd2 { +- regulator-name = +- "+V1.35_VDDIO_DDR(sd2)"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- sd3 { +- regulator-name = +- "+V1.35_VDDIO_DDR(sd3)"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_1v05_vdd: sd4 { +- regulator-name = "+V1.05"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- reg_1v8_vddio: sd5 { +- regulator-name = "+V1.8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_vdd_gpu: sd6 { +- regulator-name = "+VDD_GPU_AP"; +- regulator-min-microvolt = <650000>; +- regulator-max-microvolt = <1200000>; +- regulator-min-microamp = <3500000>; +- regulator-max-microamp = <3500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_1v05_avdd: ldo0 { +- regulator-name = "+V1.05_AVDD"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-boot-on; +- regulator-always-on; +- ams,ext-control = <1>; +- }; +- +- vddio_sdmmc1: ldo1 { +- regulator-name = "VDDIO_SDMMC1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo2 { +- regulator-name = "+V1.2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo3 { +- regulator-name = "+V1.05_RTC"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-boot-on; +- regulator-always-on; +- ams,enable-tracking; +- }; +- +- /* 1.8V for LVDS, 3.3V for eDP */ +- ldo4 { +- regulator-name = "AVDD_LVDS0_PLL"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- /* LDO5 not used */ +- +- vddio_sdmmc3: ldo6 { +- regulator-name = "VDDIO_SDMMC3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- /* LDO7 not used */ +- +- ldo9 { +- regulator-name = "+V3.3_ETH(ldo9)"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo10 { +- regulator-name = "+V3.3_ETH(ldo10)"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo11 { +- regulator-name = "+V1.8_VPP_FUSE"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- }; +- }; +- +- /* +- * TMP451 temperature sensor +- * Note: THERM_N directly connected to AS3722 PMIC THERM +- */ +- temp-sensor@4c { +- compatible = "ti,tmp451"; +- reg = <0x4c>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- #thermal-sensor-cells = <1>; +- vcc-supply = <®_module_3v3>; +- }; +- }; +- +- /* SPI2: MCU SPI */ +- spi@7000d600 { +- status = "okay"; +- spi-max-frequency = <25000000>; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <500>; +- nvidia,cpu-pwr-off-time = <300>; +- nvidia,core-pwr-good-time = <641 3845>; +- nvidia,core-pwr-off-time = <61036>; +- nvidia,core-power-req-active-high; +- nvidia,sys-clock-req-active-high; +- +- /* Set power_off bit in ResetControl register of AS3722 PMIC */ +- i2c-thermtrip { +- nvidia,i2c-controller-id = <4>; +- nvidia,bus-addr = <0x40>; +- nvidia,reg-addr = <0x36>; +- nvidia,reg-data = <0x2>; +- }; +- }; +- +- sata@70020000 { +- phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; +- phy-names = "sata-0"; +- avdd-supply = <®_1v05_vdd>; +- hvdd-supply = <®_module_3v3>; +- vddio-supply = <®_1v05_vdd>; +- }; +- +- usb@70090000 { +- /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */ +- phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, +- <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, +- <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; +- phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; +- +- avddio-pex-supply = <®_1v05_vdd>; +- avdd-pll-erefe-supply = <®_1v05_avdd>; +- avdd-pll-utmip-supply = <®_1v8_vddio>; +- avdd-usb-ss-pll-supply = <®_1v05_vdd>; +- avdd-usb-supply = <®_module_3v3>; +- dvddio-pex-supply = <®_1v05_vdd>; +- hvdd-usb-ss-pll-e-supply = <®_module_3v3>; +- hvdd-usb-ss-supply = <®_module_3v3>; +- }; +- +- padctl@7009f000 { +- avdd-pll-utmip-supply = <®_1v8_vddio>; +- avdd-pll-erefe-supply = <®_1v05_avdd>; +- avdd-pex-pll-supply = <®_1v05_vdd>; +- hvdd-pex-pll-e-supply = <®_module_3v3>; +- +- pads { +- usb2 { +- status = "okay"; +- +- lanes { +- usb2-0 { +- status = "okay"; +- nvidia,function = "xusb"; +- }; +- +- usb2-1 { +- status = "okay"; +- nvidia,function = "xusb"; +- }; +- +- usb2-2 { +- status = "okay"; +- nvidia,function = "xusb"; +- }; +- }; +- }; +- +- pcie { +- status = "okay"; +- +- lanes { +- pcie-0 { +- status = "okay"; +- nvidia,function = "usb3-ss"; +- }; +- +- pcie-1 { +- status = "okay"; +- nvidia,function = "usb3-ss"; +- }; +- +- pcie-2 { +- status = "okay"; +- nvidia,function = "pcie"; +- }; +- +- pcie-3 { +- status = "okay"; +- nvidia,function = "pcie"; +- }; +- +- pcie-4 { +- status = "okay"; +- nvidia,function = "pcie"; +- }; +- }; +- }; +- +- sata { +- status = "okay"; +- +- lanes { +- sata-0 { +- status = "okay"; +- nvidia,function = "sata"; +- }; +- }; +- }; +- }; +- +- ports { +- /* USBO1 */ +- usb2-0 { +- status = "okay"; +- mode = "otg"; +- vbus-supply = <®_usbo1_vbus>; +- }; +- +- /* USBH2 */ +- usb2-1 { +- status = "okay"; +- mode = "host"; +- vbus-supply = <®_usbh_vbus>; +- }; +- +- /* USBH4 */ +- usb2-2 { +- status = "okay"; +- mode = "host"; +- vbus-supply = <®_usbh_vbus>; +- }; +- +- usb3-0 { +- status = "okay"; +- nvidia,usb2-companion = <2>; +- vbus-supply = <®_usbh_vbus>; +- }; +- +- usb3-1 { +- status = "okay"; +- nvidia,usb2-companion = <0>; +- vbus-supply = <®_usbo1_vbus>; +- }; +- }; +- }; +- +- /* eMMC */ +- mmc@700b0600 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- vmmc-supply = <®_module_3v3>; /* VCC */ +- vqmmc-supply = <®_1v8_vddio>; /* VCCQ */ +- mmc-ddr-1_8v; +- }; +- +- /* CPU DFLL clock */ +- clock@70110000 { +- status = "okay"; +- nvidia,i2c-fs-rate = <400000>; +- vdd-cpu-supply = <®_vdd_cpu>; +- }; +- +- ahub@70300000 { +- i2s@70301200 { +- status = "okay"; +- }; +- }; +- +- clk32k_in: osc3 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- cpus { +- cpu@0 { +- vdd-cpu-supply = <®_vdd_cpu>; +- }; +- }; +- +- reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { +- compatible = "regulator-fixed"; +- regulator-name = "+V1.05_AVDD_HDMI_PLL"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; +- vin-supply = <®_1v05_vdd>; +- }; +- +- reg_3v3_mxm: regulator-3v3-mxm { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3_MXM"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3_AVDD_HDMI"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <®_1v05_vdd>; +- }; +- +- reg_module_3v3: regulator-module-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- /* PWR_EN_+V3.3 */ +- gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_3v3_mxm>; +- }; +- +- reg_module_3v3_audio: regulator-module-3v3-audio { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3_AUDIO_AVDD_S"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- sound { +- compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", +- "nvidia,tegra-audio-sgtl5000"; +- nvidia,model = "Toradex Apalis TK1"; +- nvidia,audio-routing = +- "Headphone Jack", "HP_OUT", +- "LINE_IN", "Line In Jack", +- "MIC_IN", "Mic Jack"; +- nvidia,i2s-controller = <&tegra_i2s2>; +- nvidia,audio-codec = <&sgtl5000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_A>, +- <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- +- assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- +- assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA124_CLK_EXTERN1>; +- }; +- +- thermal-zones { +- cpu { +- trips { +- cpu-shutdown-trip { +- temperature = <101000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- mem { +- trips { +- mem-shutdown-trip { +- temperature = <101000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- gpu { +- trips { +- gpu-shutdown-trip { +- temperature = <101000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +- +-&gpio { +- /* I210 Gigabit Ethernet Controller Reset */ +- lan-reset-n { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "LAN_RESET_N"; +- }; +- +- /* Control MXM3 pin 26 Reset Module Output Carrier Input */ +- reset-moci-ctrl { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "RESET_MOCI_CTRL"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra124-apalis.dtsi b/scripts/dtc/include-prefixes/arm/tegra124-apalis.dtsi +deleted file mode 100644 +index a46d9ba9bb7a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra124-apalis.dtsi ++++ /dev/null +@@ -1,2064 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR X11 +-/* +- * Copyright 2016-2019 Toradex AG +- */ +- +-#include "tegra124.dtsi" +-#include "tegra124-apalis-emc.dtsi" +- +-/* +- * Toradex Apalis TK1 Module Device Tree +- * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A +- */ +-/ { +- memory@80000000 { +- reg = <0x0 0x80000000 0x0 0x80000000>; +- }; +- +- pcie@1003000 { +- status = "okay"; +- avddio-pex-supply = <®_1v05_vdd>; +- avdd-pex-pll-supply = <®_1v05_vdd>; +- avdd-pll-erefe-supply = <®_1v05_avdd>; +- dvddio-pex-supply = <®_1v05_vdd>; +- hvdd-pex-pll-e-supply = <®_module_3v3>; +- hvdd-pex-supply = <®_module_3v3>; +- vddio-pex-ctl-supply = <®_module_3v3>; +- +- /* Apalis PCIe (additional lane Apalis type specific) */ +- pci@1,0 { +- /* PCIE1_RX/TX and TS_DIFF1/2 */ +- phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>, +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; +- phy-names = "pcie-0", "pcie-1"; +- }; +- +- /* I210 Gigabit Ethernet Controller (On-module) */ +- pci@2,0 { +- phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; +- phy-names = "pcie-0"; +- status = "okay"; +- +- ethernet@0,0 { +- reg = <0 0 0 0 0>; +- local-mac-address = [00 00 00 00 00 00]; +- }; +- }; +- }; +- +- host1x@50000000 { +- hdmi@54280000 { +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = +- <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; +- pll-supply = <®_1v05_avdd_hdmi_pll>; +- vdd-supply = <®_3v3_avdd_hdmi>; +- }; +- }; +- +- gpu@0,57000000 { +- /* +- * Node left disabled on purpose - the bootloader will enable +- * it after having set the VPR up +- */ +- vdd-supply = <®_vdd_gpu>; +- }; +- +- pinmux@70000868 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- /* Analogue Audio (On-module) */ +- dap3-fs-pp0 { +- nvidia,pins = "dap3_fs_pp0"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3-din-pp1 { +- nvidia,pins = "dap3_din_pp1"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3-dout-pp2 { +- nvidia,pins = "dap3_dout_pp2"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3-sclk-pp3 { +- nvidia,pins = "dap3_sclk_pp3"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap-mclk1-pw4 { +- nvidia,pins = "dap_mclk1_pw4"; +- nvidia,function = "extperiph1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis BKL1_ON */ +- pbb5 { +- nvidia,pins = "pbb5"; +- nvidia,function = "vgp5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis BKL1_PWM */ +- pu6 { +- nvidia,pins = "pu6"; +- nvidia,function = "pwm3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis CAM1_MCLK */ +- cam-mclk-pcc0 { +- nvidia,pins = "cam_mclk_pcc0"; +- nvidia,function = "vi_alt3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis Digital Audio */ +- dap2-fs-pa2 { +- nvidia,pins = "dap2_fs_pa2"; +- nvidia,function = "hda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2-sclk-pa3 { +- nvidia,pins = "dap2_sclk_pa3"; +- nvidia,function = "hda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2-din-pa4 { +- nvidia,pins = "dap2_din_pa4"; +- nvidia,function = "hda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2-dout-pa5 { +- nvidia,pins = "dap2_dout_pa5"; +- nvidia,function = "hda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb3 { /* DAP1_RESET */ +- nvidia,pins = "pbb3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3-out-pee0 { +- nvidia,pins = "clk3_out_pee0"; +- nvidia,function = "extperiph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis GPIO */ +- ddc-scl-pv4 { +- nvidia,pins = "ddc_scl_pv4"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ddc-sda-pv5 { +- nvidia,pins = "ddc_sda_pv5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex-l0-rst-n-pdd1 { +- nvidia,pins = "pex_l0_rst_n_pdd1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex-l0-clkreq-n-pdd2 { +- nvidia,pins = "pex_l0_clkreq_n_pdd2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex-l1-rst-n-pdd5 { +- nvidia,pins = "pex_l1_rst_n_pdd5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex-l1-clkreq-n-pdd6 { +- nvidia,pins = "pex_l1_clkreq_n_pdd6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dp-hpd-pff0 { +- nvidia,pins = "dp_hpd_pff0"; +- nvidia,function = "dp"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pff2 { +- nvidia,pins = "pff2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */ +- nvidia,pins = "owr"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,rcv-sel = ; +- }; +- +- /* Apalis HDMI1_CEC */ +- hdmi-cec-pee3 { +- nvidia,pins = "hdmi_cec_pee3"; +- nvidia,function = "cec"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* Apalis HDMI1_HPD */ +- hdmi-int-pn7 { +- nvidia,pins = "hdmi_int_pn7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,rcv-sel = ; +- }; +- +- /* Apalis I2C1 */ +- gen1-i2c-scl-pc4 { +- nvidia,pins = "gen1_i2c_scl_pc4"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen1-i2c-sda-pc5 { +- nvidia,pins = "gen1_i2c_sda_pc5"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* Apalis I2C2 (DDC) */ +- gen2-i2c-scl-pt5 { +- nvidia,pins = "gen2_i2c_scl_pt5"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen2-i2c-sda-pt6 { +- nvidia,pins = "gen2_i2c_sda_pt6"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* Apalis I2C3 (CAM) */ +- cam-i2c-scl-pbb1 { +- nvidia,pins = "cam_i2c_scl_pbb1"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam-i2c-sda-pbb2 { +- nvidia,pins = "cam_i2c_sda_pbb2"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* Apalis MMC1 */ +- sdmmc1-cd-n-pv3 { /* CD# GPIO */ +- nvidia,pins = "sdmmc1_wp_n_pv3"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2-out-pw5 { /* D5 GPIO */ +- nvidia,pins = "clk2_out_pw5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1-dat3-py4 { +- nvidia,pins = "sdmmc1_dat3_py4"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1-dat2-py5 { +- nvidia,pins = "sdmmc1_dat2_py5"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1-dat1-py6 { +- nvidia,pins = "sdmmc1_dat1_py6"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1-dat0-py7 { +- nvidia,pins = "sdmmc1_dat0_py7"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1-clk-pz0 { +- nvidia,pins = "sdmmc1_clk_pz0"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1-cmd-pz1 { +- nvidia,pins = "sdmmc1_cmd_pz1"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2-req-pcc5 { /* D4 GPIO */ +- nvidia,pins = "clk2_req_pcc5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */ +- nvidia,pins = "sdmmc3_clk_lb_in_pee5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- usb-vbus-en2-pff1 { /* D7 GPIO */ +- nvidia,pins = "usb_vbus_en2_pff1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis PWM */ +- ph0 { +- nvidia,pins = "ph0"; +- nvidia,function = "pwm0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph1 { +- nvidia,pins = "ph1"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph2 { +- nvidia,pins = "ph2"; +- nvidia,function = "pwm2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ +- ph3 { +- nvidia,pins = "ph3"; +- nvidia,function = "pwm3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis SATA1_ACT# */ +- dap1-dout-pn2 { +- nvidia,pins = "dap1_dout_pn2"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis SD1 */ +- sdmmc3-clk-pa6 { +- nvidia,pins = "sdmmc3_clk_pa6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3-cmd-pa7 { +- nvidia,pins = "sdmmc3_cmd_pa7"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3-dat3-pb4 { +- nvidia,pins = "sdmmc3_dat3_pb4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3-dat2-pb5 { +- nvidia,pins = "sdmmc3_dat2_pb5"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3-dat1-pb6 { +- nvidia,pins = "sdmmc3_dat1_pb6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3-dat0-pb7 { +- nvidia,pins = "sdmmc3_dat0_pb7"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3-cd-n-pv2 { /* CD# GPIO */ +- nvidia,pins = "sdmmc3_cd_n_pv2"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis SPDIF */ +- spdif-out-pk5 { +- nvidia,pins = "spdif_out_pk5"; +- nvidia,function = "spdif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spdif-in-pk6 { +- nvidia,pins = "spdif_in_pk6"; +- nvidia,function = "spdif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis SPI1 */ +- ulpi-clk-py0 { +- nvidia,pins = "ulpi_clk_py0"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi-dir-py1 { +- nvidia,pins = "ulpi_dir_py1"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi-nxt-py2 { +- nvidia,pins = "ulpi_nxt_py2"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi-stp-py3 { +- nvidia,pins = "ulpi_stp_py3"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis SPI2 */ +- pg5 { +- nvidia,pins = "pg5"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg6 { +- nvidia,pins = "pg6"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg7 { +- nvidia,pins = "pg7"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi3 { +- nvidia,pins = "pi3"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis UART1 */ +- pb1 { /* DCD GPIO */ +- nvidia,pins = "pb1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk7 { /* RI GPIO */ +- nvidia,pins = "pk7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart1-txd-pu0 { +- nvidia,pins = "pu0"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart1-rxd-pu1 { +- nvidia,pins = "pu1"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart1-cts-n-pu2 { +- nvidia,pins = "pu2"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart1-rts-n-pu3 { +- nvidia,pins = "pu3"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3-cts-n-pa1 { /* DSR GPIO */ +- nvidia,pins = "uart3_cts_n_pa1"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3-rts-n-pc0 { /* DTR GPIO */ +- nvidia,pins = "uart3_rts_n_pc0"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis UART2 */ +- uart2-txd-pc2 { +- nvidia,pins = "uart2_txd_pc2"; +- nvidia,function = "irda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2-rxd-pc3 { +- nvidia,pins = "uart2_rxd_pc3"; +- nvidia,function = "irda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2-cts-n-pj5 { +- nvidia,pins = "uart2_cts_n_pj5"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2-rts-n-pj6 { +- nvidia,pins = "uart2_rts_n_pj6"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis UART3 */ +- uart3-txd-pw6 { +- nvidia,pins = "uart3_txd_pw6"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3-rxd-pw7 { +- nvidia,pins = "uart3_rxd_pw7"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis UART4 */ +- uart4-rxd-pb0 { +- nvidia,pins = "pb0"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart4-txd-pj7 { +- nvidia,pins = "pj7"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis USBH_EN */ +- usb-vbus-en1-pn5 { +- nvidia,pins = "usb_vbus_en1_pn5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* Apalis USBH_OC# */ +- pbb0 { +- nvidia,pins = "pbb0"; +- nvidia,function = "vgp6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis USBO1_EN */ +- usb-vbus-en0-pn4 { +- nvidia,pins = "usb_vbus_en0_pn4"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* Apalis USBO1_OC# */ +- pbb4 { +- nvidia,pins = "pbb4"; +- nvidia,function = "vgp4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis WAKE1_MICO */ +- pex-wake-n-pdd3 { +- nvidia,pins = "pex_wake_n_pdd3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* CORE_PWR_REQ */ +- core-pwr-req { +- nvidia,pins = "core_pwr_req"; +- nvidia,function = "pwron"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* CPU_PWR_REQ */ +- cpu-pwr-req { +- nvidia,pins = "cpu_pwr_req"; +- nvidia,function = "cpu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* DVFS */ +- dvfs-pwm-px0 { +- nvidia,pins = "dvfs_pwm_px0"; +- nvidia,function = "cldvfs"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dvfs-clk-px2 { +- nvidia,pins = "dvfs_clk_px2"; +- nvidia,function = "cldvfs"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* eMMC */ +- sdmmc4-dat0-paa0 { +- nvidia,pins = "sdmmc4_dat0_paa0"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-dat1-paa1 { +- nvidia,pins = "sdmmc4_dat1_paa1"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-dat2-paa2 { +- nvidia,pins = "sdmmc4_dat2_paa2"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-dat3-paa3 { +- nvidia,pins = "sdmmc4_dat3_paa3"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-dat4-paa4 { +- nvidia,pins = "sdmmc4_dat4_paa4"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-dat5-paa5 { +- nvidia,pins = "sdmmc4_dat5_paa5"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-dat6-paa6 { +- nvidia,pins = "sdmmc4_dat6_paa6"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-dat7-paa7 { +- nvidia,pins = "sdmmc4_dat7_paa7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-clk-pcc4 { +- nvidia,pins = "sdmmc4_clk_pcc4"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-cmd-pt7 { +- nvidia,pins = "sdmmc4_cmd_pt7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* JTAG_RTCK */ +- jtag-rtck { +- nvidia,pins = "jtag_rtck"; +- nvidia,function = "rtck"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* LAN_DEV_OFF# */ +- ulpi-data5-po6 { +- nvidia,pins = "ulpi_data5_po6"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* LAN_RESET# */ +- kb-row10-ps2 { +- nvidia,pins = "kb_row10_ps2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* LAN_WAKE# */ +- ulpi-data4-po5 { +- nvidia,pins = "ulpi_data4_po5"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* MCU_INT1# */ +- pk2 { +- nvidia,pins = "pk2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* MCU_INT2# */ +- pj2 { +- nvidia,pins = "pj2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* MCU_INT3# */ +- pi5 { +- nvidia,pins = "pi5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* MCU_INT4# */ +- pj0 { +- nvidia,pins = "pj0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* MCU_RESET */ +- pbb6 { +- nvidia,pins = "pbb6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* MCU SPI */ +- gpio-x4-aud-px4 { +- nvidia,pins = "gpio_x4_aud_px4"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio-x5-aud-px5 { +- nvidia,pins = "gpio_x5_aud_px5"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio-x6-aud-px6 { /* MCU_CS */ +- nvidia,pins = "gpio_x6_aud_px6"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio-x7-aud-px7 { +- nvidia,pins = "gpio_x7_aud_px7"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio-w2-aud-pw2 { /* MCU_CSEZP */ +- nvidia,pins = "gpio_w2_aud_pw2"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* PMIC_CLK_32K */ +- clk-32k-in { +- nvidia,pins = "clk_32k_in"; +- nvidia,function = "clk"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* PMIC_CPU_OC_INT */ +- clk-32k-out-pa0 { +- nvidia,pins = "clk_32k_out_pa0"; +- nvidia,function = "soc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* PWR_I2C */ +- pwr-i2c-scl-pz6 { +- nvidia,pins = "pwr_i2c_scl_pz6"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pwr-i2c-sda-pz7 { +- nvidia,pins = "pwr_i2c_sda_pz7"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* PWR_INT_N */ +- pwr-int-n { +- nvidia,pins = "pwr_int_n"; +- nvidia,function = "pmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* RESET_MOCI_CTRL */ +- pu4 { +- nvidia,pins = "pu4"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* RESET_OUT_N */ +- reset-out-n { +- nvidia,pins = "reset_out_n"; +- nvidia,function = "reset_out_n"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* SHIFT_CTRL_DIR_IN */ +- kb-row0-pr0 { +- nvidia,pins = "kb_row0_pr0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row1-pr1 { +- nvidia,pins = "kb_row1_pr1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Configure level-shifter as output for HDA */ +- kb-row11-ps3 { +- nvidia,pins = "kb_row11_ps3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* SHIFT_CTRL_DIR_OUT */ +- kb-col5-pq5 { +- nvidia,pins = "kb_col5_pq5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-col6-pq6 { +- nvidia,pins = "kb_col6_pq6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-col7-pq7 { +- nvidia,pins = "kb_col7_pq7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* SHIFT_CTRL_OE */ +- kb-col0-pq0 { +- nvidia,pins = "kb_col0_pq0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-col1-pq1 { +- nvidia,pins = "kb_col1_pq1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-col2-pq2 { +- nvidia,pins = "kb_col2_pq2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-col4-pq4 { +- nvidia,pins = "kb_col4_pq4"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row2-pr2 { +- nvidia,pins = "kb_row2_pr2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */ +- pi6 { +- nvidia,pins = "pi6"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* TOUCH_INT */ +- gpio-w3-aud-pw3 { +- nvidia,pins = "gpio_w3_aud_pw3"; +- nvidia,function = "spi6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- pc7 { /* NC */ +- nvidia,pins = "pc7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg0 { /* NC */ +- nvidia,pins = "pg0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg1 { /* NC */ +- nvidia,pins = "pg1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg2 { /* NC */ +- nvidia,pins = "pg2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg3 { /* NC */ +- nvidia,pins = "pg3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg4 { /* NC */ +- nvidia,pins = "pg4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph4 { /* NC */ +- nvidia,pins = "ph4"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph5 { /* NC */ +- nvidia,pins = "ph5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph6 { /* NC */ +- nvidia,pins = "ph6"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph7 { /* NC */ +- nvidia,pins = "ph7"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi0 { /* NC */ +- nvidia,pins = "pi0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi1 { /* NC */ +- nvidia,pins = "pi1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi2 { /* NC */ +- nvidia,pins = "pi2"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi4 { /* NC */ +- nvidia,pins = "pi4"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi7 { /* NC */ +- nvidia,pins = "pi7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk0 { /* NC */ +- nvidia,pins = "pk0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk1 { /* NC */ +- nvidia,pins = "pk1"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk3 { /* NC */ +- nvidia,pins = "pk3"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk4 { /* NC */ +- nvidia,pins = "pk4"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1-fs-pn0 { /* NC */ +- nvidia,pins = "dap1_fs_pn0"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1-din-pn1 { /* NC */ +- nvidia,pins = "dap1_din_pn1"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1-sclk-pn3 { /* NC */ +- nvidia,pins = "dap1_sclk_pn3"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi-data7-po0 { /* NC */ +- nvidia,pins = "ulpi_data7_po0"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi-data0-po1 { /* NC */ +- nvidia,pins = "ulpi_data0_po1"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi-data1-po2 { /* NC */ +- nvidia,pins = "ulpi_data1_po2"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi-data2-po3 { /* NC */ +- nvidia,pins = "ulpi_data2_po3"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi-data3-po4 { /* NC */ +- nvidia,pins = "ulpi_data3_po4"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi-data6-po7 { /* NC */ +- nvidia,pins = "ulpi_data6_po7"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4-fs-pp4 { /* NC */ +- nvidia,pins = "dap4_fs_pp4"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4-din-pp5 { /* NC */ +- nvidia,pins = "dap4_din_pp5"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4-dout-pp6 { /* NC */ +- nvidia,pins = "dap4_dout_pp6"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4-sclk-pp7 { /* NC */ +- nvidia,pins = "dap4_sclk_pp7"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-col3-pq3 { /* NC */ +- nvidia,pins = "kb_col3_pq3"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row3-pr3 { /* NC */ +- nvidia,pins = "kb_row3_pr3"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row4-pr4 { /* NC */ +- nvidia,pins = "kb_row4_pr4"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row5-pr5 { /* NC */ +- nvidia,pins = "kb_row5_pr5"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row6-pr6 { /* NC */ +- nvidia,pins = "kb_row6_pr6"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row7-pr7 { /* NC */ +- nvidia,pins = "kb_row7_pr7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row8-ps0 { /* NC */ +- nvidia,pins = "kb_row8_ps0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row9-ps1 { /* NC */ +- nvidia,pins = "kb_row9_ps1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row12-ps4 { /* NC */ +- nvidia,pins = "kb_row12_ps4"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row13-ps5 { /* NC */ +- nvidia,pins = "kb_row13_ps5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row14-ps6 { /* NC */ +- nvidia,pins = "kb_row14_ps6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row15-ps7 { /* NC */ +- nvidia,pins = "kb_row15_ps7"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row16-pt0 { /* NC */ +- nvidia,pins = "kb_row16_pt0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row17-pt1 { /* NC */ +- nvidia,pins = "kb_row17_pt1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu5 { /* NC */ +- nvidia,pins = "pu5"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv0 { /* NC */ +- nvidia,pins = "pv0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv1 { /* NC */ +- nvidia,pins = "pv1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio-x1-aud-px1 { /* NC */ +- nvidia,pins = "gpio_x1_aud_px1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio-x3-aud-px3 { /* NC */ +- nvidia,pins = "gpio_x3_aud_px3"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb7 { /* NC */ +- nvidia,pins = "pbb7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pcc1 { /* NC */ +- nvidia,pins = "pcc1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pcc2 { /* NC */ +- nvidia,pins = "pcc2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3-req-pee1 { /* NC */ +- nvidia,pins = "clk3_req_pee1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap-mclk1-req-pee2 { /* NC */ +- nvidia,pins = "dap_mclk1_req_pee2"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* +- * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output +- * driver enabled aka not tristated and input driver +- * enabled as well as it features some magic properties +- * even though the external loopback is disabled and the +- * internal loopback used as per +- * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 +- * bits being set to 0xfffd according to the TRM! +- */ +- sdmmc3-clk-lb-out-pee4 { /* NC */ +- nvidia,pins = "sdmmc3_clk_lb_out_pee4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- }; +- }; +- +- serial@70006040 { +- compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; +- }; +- +- serial@70006200 { +- compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; +- }; +- +- serial@70006300 { +- compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; +- }; +- +- hdmi_ddc: i2c@7000c400 { +- clock-frequency = <10000>; +- }; +- +- /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- /* SGTL5000 audio codec */ +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- VDDA-supply = <®_module_3v3_audio>; +- VDDD-supply = <®_1v8_vddio>; +- VDDIO-supply = <®_1v8_vddio>; +- clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; +- }; +- +- pmic: pmic@40 { +- compatible = "ams,as3722"; +- reg = <0x40>; +- interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; +- ams,system-power-controller; +- #interrupt-cells = <2>; +- interrupt-controller; +- gpio-controller; +- #gpio-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&as3722_default>; +- +- as3722_default: pinmux { +- gpio2-7 { +- pins = "gpio2", /* PWR_EN_+V3.3 */ +- "gpio7"; /* +V1.6_LPO */ +- function = "gpio"; +- bias-pull-up; +- }; +- +- gpio0-1-3-4-5-6 { +- pins = "gpio0", "gpio1", "gpio3", +- "gpio4", "gpio5", "gpio6"; +- bias-high-impedance; +- }; +- }; +- +- regulators { +- vsup-sd2-supply = <®_module_3v3>; +- vsup-sd3-supply = <®_module_3v3>; +- vsup-sd4-supply = <®_module_3v3>; +- vsup-sd5-supply = <®_module_3v3>; +- vin-ldo0-supply = <®_1v35_vddio_ddr>; +- vin-ldo1-6-supply = <®_module_3v3>; +- vin-ldo2-5-7-supply = <®_1v8_vddio>; +- vin-ldo3-4-supply = <®_module_3v3>; +- vin-ldo9-10-supply = <®_module_3v3>; +- vin-ldo11-supply = <®_module_3v3>; +- +- reg_vdd_cpu: sd0 { +- regulator-name = "+VDD_CPU_AP"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1400000>; +- regulator-min-microamp = <3500000>; +- regulator-max-microamp = <3500000>; +- regulator-always-on; +- regulator-boot-on; +- ams,ext-control = <2>; +- }; +- +- sd1 { +- regulator-name = "+VDD_CORE"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-min-microamp = <2500000>; +- regulator-max-microamp = <4000000>; +- regulator-always-on; +- regulator-boot-on; +- ams,ext-control = <1>; +- }; +- +- reg_1v35_vddio_ddr: sd2 { +- regulator-name = +- "+V1.35_VDDIO_DDR(sd2)"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- sd3 { +- regulator-name = +- "+V1.35_VDDIO_DDR(sd3)"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_1v05_vdd: sd4 { +- regulator-name = "+V1.05"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- reg_1v8_vddio: sd5 { +- regulator-name = "+V1.8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_vdd_gpu: sd6 { +- regulator-name = "+VDD_GPU_AP"; +- regulator-min-microvolt = <650000>; +- regulator-max-microvolt = <1200000>; +- regulator-min-microamp = <3500000>; +- regulator-max-microamp = <3500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_1v05_avdd: ldo0 { +- regulator-name = "+V1.05_AVDD"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-boot-on; +- regulator-always-on; +- ams,ext-control = <1>; +- }; +- +- vddio_sdmmc1: ldo1 { +- regulator-name = "VDDIO_SDMMC1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo2 { +- regulator-name = "+V1.2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo3 { +- regulator-name = "+V1.05_RTC"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-boot-on; +- regulator-always-on; +- ams,enable-tracking; +- }; +- +- /* 1.8V for LVDS, 3.3V for eDP */ +- ldo4 { +- regulator-name = "AVDD_LVDS0_PLL"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- /* LDO5 not used */ +- +- vddio_sdmmc3: ldo6 { +- regulator-name = "VDDIO_SDMMC3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- /* LDO7 not used */ +- +- ldo9 { +- regulator-name = "+V3.3_ETH(ldo9)"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo10 { +- regulator-name = "+V3.3_ETH(ldo10)"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo11 { +- regulator-name = "+V1.8_VPP_FUSE"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- }; +- }; +- +- /* +- * TMP451 temperature sensor +- * Note: THERM_N directly connected to AS3722 PMIC THERM +- */ +- temp-sensor@4c { +- compatible = "ti,tmp451"; +- reg = <0x4c>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- #thermal-sensor-cells = <1>; +- vcc-supply = <®_module_3v3>; +- }; +- }; +- +- /* SPI2: MCU SPI */ +- spi@7000d600 { +- status = "okay"; +- spi-max-frequency = <25000000>; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <500>; +- nvidia,cpu-pwr-off-time = <300>; +- nvidia,core-pwr-good-time = <641 3845>; +- nvidia,core-pwr-off-time = <61036>; +- nvidia,core-power-req-active-high; +- nvidia,sys-clock-req-active-high; +- +- /* Set power_off bit in ResetControl register of AS3722 PMIC */ +- i2c-thermtrip { +- nvidia,i2c-controller-id = <4>; +- nvidia,bus-addr = <0x40>; +- nvidia,reg-addr = <0x36>; +- nvidia,reg-data = <0x2>; +- }; +- }; +- +- sata@70020000 { +- phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; +- phy-names = "sata-0"; +- avdd-supply = <®_1v05_vdd>; +- hvdd-supply = <®_module_3v3>; +- vddio-supply = <®_1v05_vdd>; +- }; +- +- usb@70090000 { +- /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */ +- phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, +- <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, +- <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; +- phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; +- avddio-pex-supply = <®_1v05_vdd>; +- avdd-pll-erefe-supply = <®_1v05_avdd>; +- avdd-pll-utmip-supply = <®_1v8_vddio>; +- avdd-usb-ss-pll-supply = <®_1v05_vdd>; +- avdd-usb-supply = <®_module_3v3>; +- dvddio-pex-supply = <®_1v05_vdd>; +- hvdd-usb-ss-pll-e-supply = <®_module_3v3>; +- hvdd-usb-ss-supply = <®_module_3v3>; +- }; +- +- padctl@7009f000 { +- avdd-pll-utmip-supply = <®_1v8_vddio>; +- avdd-pll-erefe-supply = <®_1v05_avdd>; +- avdd-pex-pll-supply = <®_1v05_vdd>; +- hvdd-pex-pll-e-supply = <®_module_3v3>; +- +- pads { +- usb2 { +- status = "okay"; +- +- lanes { +- usb2-0 { +- status = "okay"; +- nvidia,function = "xusb"; +- }; +- +- usb2-1 { +- status = "okay"; +- nvidia,function = "xusb"; +- }; +- +- usb2-2 { +- status = "okay"; +- nvidia,function = "xusb"; +- }; +- }; +- }; +- +- pcie { +- status = "okay"; +- +- lanes { +- pcie-0 { +- status = "okay"; +- nvidia,function = "usb3-ss"; +- }; +- +- pcie-1 { +- status = "okay"; +- nvidia,function = "usb3-ss"; +- }; +- +- pcie-2 { +- status = "okay"; +- nvidia,function = "pcie"; +- }; +- +- pcie-3 { +- status = "okay"; +- nvidia,function = "pcie"; +- }; +- +- pcie-4 { +- status = "okay"; +- nvidia,function = "pcie"; +- }; +- }; +- }; +- +- sata { +- status = "okay"; +- +- lanes { +- sata-0 { +- status = "okay"; +- nvidia,function = "sata"; +- }; +- }; +- }; +- }; +- +- ports { +- /* USBO1 */ +- usb2-0 { +- status = "okay"; +- mode = "otg"; +- vbus-supply = <®_usbo1_vbus>; +- }; +- +- /* USBH2 */ +- usb2-1 { +- status = "okay"; +- mode = "host"; +- vbus-supply = <®_usbh_vbus>; +- }; +- +- /* USBH4 */ +- usb2-2 { +- status = "okay"; +- mode = "host"; +- vbus-supply = <®_usbh_vbus>; +- }; +- +- usb3-0 { +- status = "okay"; +- nvidia,usb2-companion = <2>; +- vbus-supply = <®_usbh_vbus>; +- }; +- +- usb3-1 { +- status = "okay"; +- nvidia,usb2-companion = <0>; +- vbus-supply = <®_usbo1_vbus>; +- }; +- }; +- }; +- +- /* eMMC */ +- mmc@700b0600 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- vmmc-supply = <®_module_3v3>; /* VCC */ +- vqmmc-supply = <®_1v8_vddio>; /* VCCQ */ +- mmc-ddr-1_8v; +- }; +- +- /* CPU DFLL clock */ +- clock@70110000 { +- status = "okay"; +- nvidia,i2c-fs-rate = <400000>; +- vdd-cpu-supply = <®_vdd_cpu>; +- }; +- +- ahub@70300000 { +- i2s@70301200 { +- status = "okay"; +- }; +- }; +- +- clk32k_in: osc3 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- cpus { +- cpu@0 { +- vdd-cpu-supply = <®_vdd_cpu>; +- }; +- }; +- +- reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { +- compatible = "regulator-fixed"; +- regulator-name = "+V1.05_AVDD_HDMI_PLL"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; +- vin-supply = <®_1v05_vdd>; +- }; +- +- reg_3v3_mxm: regulator-3v3-mxm { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3_MXM"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3_AVDD_HDMI"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <®_1v05_vdd>; +- }; +- +- reg_module_3v3: regulator-module-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- /* PWR_EN_+V3.3 */ +- gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_3v3_mxm>; +- }; +- +- reg_module_3v3_audio: regulator-module-3v3-audio { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3_AUDIO_AVDD_S"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- sound { +- compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", +- "nvidia,tegra-audio-sgtl5000"; +- nvidia,model = "Toradex Apalis TK1"; +- nvidia,audio-routing = +- "Headphone Jack", "HP_OUT", +- "LINE_IN", "Line In Jack", +- "MIC_IN", "Mic Jack"; +- nvidia,i2s-controller = <&tegra_i2s2>; +- nvidia,audio-codec = <&sgtl5000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_A>, +- <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- +- assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- +- assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA124_CLK_EXTERN1>; +- }; +- +- thermal-zones { +- cpu { +- trips { +- cpu-shutdown-trip { +- temperature = <101000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- mem { +- trips { +- mem-shutdown-trip { +- temperature = <101000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- gpu { +- trips { +- gpu-shutdown-trip { +- temperature = <101000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +- +-&gpio { +- /* I210 Gigabit Ethernet Controller Reset */ +- lan-reset-n { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "LAN_RESET_N"; +- }; +- +- /* Control MXM3 pin 26 Reset Module Output Carrier Input */ +- reset-moci-ctrl { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "RESET_MOCI_CTRL"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra124-jetson-tk1-emc.dtsi b/scripts/dtc/include-prefixes/arm/tegra124-jetson-tk1-emc.dtsi +deleted file mode 100644 +index df4e463afbd1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra124-jetson-tk1-emc.dtsi ++++ /dev/null +@@ -1,2430 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- clock@60006000 { +- emc-timings-3 { +- nvidia,ram-code = <3>; +- +- timing-12750000 { +- clock-frequency = <12750000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-20400000 { +- clock-frequency = <20400000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-40800000 { +- clock-frequency = <40800000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-68000000 { +- clock-frequency = <68000000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-102000000 { +- clock-frequency = <102000000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-204000000 { +- clock-frequency = <204000000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-300000000 { +- clock-frequency = <300000000>; +- nvidia,parent-clock-frequency = <600000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_C>; +- clock-names = "emc-parent"; +- }; +- timing-396000000 { +- clock-frequency = <396000000>; +- nvidia,parent-clock-frequency = <792000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_M>; +- clock-names = "emc-parent"; +- }; +- timing-528000000 { +- clock-frequency = <528000000>; +- nvidia,parent-clock-frequency = <528000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; +- clock-names = "emc-parent"; +- }; +- timing-600000000 { +- clock-frequency = <600000000>; +- nvidia,parent-clock-frequency = <600000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; +- clock-names = "emc-parent"; +- }; +- timing-792000000 { +- clock-frequency = <792000000>; +- nvidia,parent-clock-frequency = <792000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; +- clock-names = "emc-parent"; +- }; +- timing-924000000 { +- clock-frequency = <924000000>; +- nvidia,parent-clock-frequency = <924000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; +- clock-names = "emc-parent"; +- }; +- }; +- }; +- +- external-memory-controller@7001b000 { +- emc-timings-3 { +- nvidia,ram-code = <3>; +- +- timing-12750000 { +- clock-frequency = <12750000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000e000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000004 +- 0x0000000a +- 0x00000005 +- 0x0000000b +- 0x00000000 +- 0x00000000 +- 0x00000003 +- 0x00000003 +- 0x00000000 +- 0x00000006 +- 0x00000006 +- 0x00000006 +- 0x00000002 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00010000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000004 +- 0x0000000c +- 0x0000000d +- 0x0000000f +- 0x00000060 +- 0x00000000 +- 0x00000018 +- 0x00000002 +- 0x00000002 +- 0x00000001 +- 0x00000000 +- 0x00000007 +- 0x0000000f +- 0x00000005 +- 0x00000005 +- 0x00000004 +- 0x00000005 +- 0x00000004 +- 0x00000000 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00000064 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x106aa298 +- 0x002c00a0 +- 0x00008000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x10000280 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc081 +- 0x00000e0e +- 0x81f1f108 +- 0x07070004 +- 0x0000003f +- 0x016eeeee +- 0x51451400 +- 0x00514514 +- 0x00514514 +- 0x51451400 +- 0x0000003f +- 0x00000007 +- 0x00000000 +- 0x00000042 +- 0x000e000e +- 0x00000000 +- 0x00000003 +- 0x0000f2f3 +- 0x800001c5 +- 0x0000000a +- >; +- }; +- +- timing-20400000 { +- clock-frequency = <20400000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000e000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000000 +- 0x00000005 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000004 +- 0x0000000a +- 0x00000005 +- 0x0000000b +- 0x00000000 +- 0x00000000 +- 0x00000003 +- 0x00000003 +- 0x00000000 +- 0x00000006 +- 0x00000006 +- 0x00000006 +- 0x00000002 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00010000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000004 +- 0x0000000c +- 0x0000000d +- 0x0000000f +- 0x0000009a +- 0x00000000 +- 0x00000026 +- 0x00000002 +- 0x00000002 +- 0x00000001 +- 0x00000000 +- 0x00000007 +- 0x0000000f +- 0x00000006 +- 0x00000006 +- 0x00000004 +- 0x00000005 +- 0x00000004 +- 0x00000000 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x000000a0 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x106aa298 +- 0x002c00a0 +- 0x00008000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x10000280 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc081 +- 0x00000e0e +- 0x81f1f108 +- 0x07070004 +- 0x0000003f +- 0x016eeeee +- 0x51451400 +- 0x00514514 +- 0x00514514 +- 0x51451400 +- 0x0000003f +- 0x0000000b +- 0x00000000 +- 0x00000042 +- 0x000e000e +- 0x00000000 +- 0x00000003 +- 0x0000f2f3 +- 0x8000023a +- 0x0000000a +- >; +- }; +- +- timing-40800000 { +- clock-frequency = <40800000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000e000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000001 +- 0x0000000a +- 0x00000000 +- 0x00000001 +- 0x00000000 +- 0x00000004 +- 0x0000000a +- 0x00000005 +- 0x0000000b +- 0x00000000 +- 0x00000000 +- 0x00000003 +- 0x00000003 +- 0x00000000 +- 0x00000006 +- 0x00000006 +- 0x00000006 +- 0x00000002 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00010000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000004 +- 0x0000000c +- 0x0000000d +- 0x0000000f +- 0x00000134 +- 0x00000000 +- 0x0000004d +- 0x00000002 +- 0x00000002 +- 0x00000001 +- 0x00000000 +- 0x00000008 +- 0x0000000f +- 0x0000000c +- 0x0000000c +- 0x00000004 +- 0x00000005 +- 0x00000004 +- 0x00000000 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x0000013f +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x106aa298 +- 0x002c00a0 +- 0x00008000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x10000280 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc081 +- 0x00000e0e +- 0x81f1f108 +- 0x07070004 +- 0x0000003f +- 0x016eeeee +- 0x51451400 +- 0x00514514 +- 0x00514514 +- 0x51451400 +- 0x0000003f +- 0x00000015 +- 0x00000000 +- 0x00000042 +- 0x000e000e +- 0x00000000 +- 0x00000003 +- 0x0000f2f3 +- 0x80000370 +- 0x0000000a +- >; +- }; +- +- timing-68000000 { +- clock-frequency = <68000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000e000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000003 +- 0x00000011 +- 0x00000000 +- 0x00000002 +- 0x00000000 +- 0x00000004 +- 0x0000000a +- 0x00000005 +- 0x0000000b +- 0x00000000 +- 0x00000000 +- 0x00000003 +- 0x00000003 +- 0x00000000 +- 0x00000006 +- 0x00000006 +- 0x00000006 +- 0x00000002 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00010000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000004 +- 0x0000000c +- 0x0000000d +- 0x0000000f +- 0x00000202 +- 0x00000000 +- 0x00000080 +- 0x00000002 +- 0x00000002 +- 0x00000001 +- 0x00000000 +- 0x0000000f +- 0x0000000f +- 0x00000013 +- 0x00000013 +- 0x00000004 +- 0x00000005 +- 0x00000004 +- 0x00000001 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00000213 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x106aa298 +- 0x002c00a0 +- 0x00008000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x10000280 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc081 +- 0x00000e0e +- 0x81f1f108 +- 0x07070004 +- 0x0000003f +- 0x016eeeee +- 0x51451400 +- 0x00514514 +- 0x00514514 +- 0x51451400 +- 0x0000003f +- 0x00000022 +- 0x00000000 +- 0x00000042 +- 0x000e000e +- 0x00000000 +- 0x00000003 +- 0x0000f2f3 +- 0x8000050e +- 0x0000000a +- >; +- }; +- +- timing-102000000 { +- clock-frequency = <102000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000e000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000004 +- 0x0000001a +- 0x00000000 +- 0x00000003 +- 0x00000001 +- 0x00000004 +- 0x0000000a +- 0x00000005 +- 0x0000000b +- 0x00000001 +- 0x00000001 +- 0x00000003 +- 0x00000003 +- 0x00000000 +- 0x00000006 +- 0x00000006 +- 0x00000006 +- 0x00000002 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00010000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000004 +- 0x0000000c +- 0x0000000d +- 0x0000000f +- 0x00000304 +- 0x00000000 +- 0x000000c1 +- 0x00000002 +- 0x00000002 +- 0x00000001 +- 0x00000000 +- 0x00000018 +- 0x0000000f +- 0x0000001c +- 0x0000001c +- 0x00000004 +- 0x00000005 +- 0x00000004 +- 0x00000002 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x0000031c +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x106aa298 +- 0x002c00a0 +- 0x00008000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x10000280 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc081 +- 0x00000e0e +- 0x81f1f108 +- 0x07070004 +- 0x0000003f +- 0x016eeeee +- 0x51451400 +- 0x00514514 +- 0x00514514 +- 0x51451400 +- 0x0000003f +- 0x00000033 +- 0x00000000 +- 0x00000042 +- 0x000e000e +- 0x00000000 +- 0x00000003 +- 0x0000f2f3 +- 0x80000713 +- 0x0000000a +- >; +- }; +- +- timing-204000000 { +- clock-frequency = <204000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008cd>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000e000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000009 +- 0x00000035 +- 0x00000000 +- 0x00000006 +- 0x00000002 +- 0x00000005 +- 0x0000000a +- 0x00000005 +- 0x0000000b +- 0x00000002 +- 0x00000002 +- 0x00000003 +- 0x00000003 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00000006 +- 0x00000002 +- 0x00000000 +- 0x00000004 +- 0x00000006 +- 0x00010000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000003 +- 0x0000000d +- 0x0000000f +- 0x00000011 +- 0x00000607 +- 0x00000000 +- 0x00000181 +- 0x00000002 +- 0x00000002 +- 0x00000001 +- 0x00000000 +- 0x00000032 +- 0x0000000f +- 0x00000038 +- 0x00000038 +- 0x00000004 +- 0x00000005 +- 0x00000004 +- 0x00000006 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00000638 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x106aa298 +- 0x002c00a0 +- 0x00008000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00080000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00008000 +- 0x00000000 +- 0x00000000 +- 0x00008000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00090000 +- 0x00090000 +- 0x00090000 +- 0x00090000 +- 0x00009000 +- 0x00009000 +- 0x00009000 +- 0x00009000 +- 0x10000280 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc081 +- 0x00000707 +- 0x81f1f108 +- 0x07070004 +- 0x0000003f +- 0x016eeeee +- 0x51451400 +- 0x00514514 +- 0x00514514 +- 0x51451400 +- 0x0000003f +- 0x00000066 +- 0x00000000 +- 0x00000100 +- 0x000e000e +- 0x00000000 +- 0x00000003 +- 0x0000d2b3 +- 0x80000d22 +- 0x0000000a +- >; +- }; +- +- timing-300000000 { +- clock-frequency = <300000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73340000>; +- nvidia,emc-cfg-2 = <0x000008d5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200000>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000321>; +- nvidia,emc-mrs-wait-cnt = <0x0173000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x01231339>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x0000000d +- 0x0000004d +- 0x00000000 +- 0x00000009 +- 0x00000003 +- 0x00000004 +- 0x00000008 +- 0x00000002 +- 0x00000009 +- 0x00000003 +- 0x00000003 +- 0x00000002 +- 0x00000002 +- 0x00000000 +- 0x00000003 +- 0x00000003 +- 0x00000005 +- 0x00000002 +- 0x00000000 +- 0x00000002 +- 0x00000007 +- 0x00020000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000001 +- 0x0000000e +- 0x00000010 +- 0x00000012 +- 0x000008e4 +- 0x00000000 +- 0x00000239 +- 0x00000001 +- 0x00000008 +- 0x00000001 +- 0x00000000 +- 0x0000004b +- 0x0000000e +- 0x00000052 +- 0x00000200 +- 0x00000004 +- 0x00000005 +- 0x00000004 +- 0x00000008 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00000924 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x104ab098 +- 0x002c00a0 +- 0x00008000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00098000 +- 0x00098000 +- 0x00000000 +- 0x00098000 +- 0x00098000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00050000 +- 0x00050000 +- 0x00050000 +- 0x00050000 +- 0x00005000 +- 0x00005000 +- 0x00005000 +- 0x00005000 +- 0x10000280 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc081 +- 0x00000505 +- 0x81f1f108 +- 0x07070004 +- 0x00000000 +- 0x016eeeee +- 0x51451420 +- 0x00514514 +- 0x00514514 +- 0x51451400 +- 0x0000003f +- 0x00000096 +- 0x00000000 +- 0x00000100 +- 0x0173000e +- 0x00000000 +- 0x00000003 +- 0x000052a3 +- 0x800012d7 +- 0x00000009 +- >; +- }; +- +- timing-396000000 { +- clock-frequency = <396000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73340000>; +- nvidia,emc-cfg-2 = <0x00000895>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200000>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000521>; +- nvidia,emc-mrs-wait-cnt = <0x015b000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x01231339>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000011 +- 0x00000066 +- 0x00000000 +- 0x0000000c +- 0x00000004 +- 0x00000004 +- 0x00000008 +- 0x00000002 +- 0x0000000a +- 0x00000004 +- 0x00000004 +- 0x00000002 +- 0x00000002 +- 0x00000000 +- 0x00000003 +- 0x00000003 +- 0x00000005 +- 0x00000002 +- 0x00000000 +- 0x00000001 +- 0x00000008 +- 0x00020000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x0000000f +- 0x00000010 +- 0x00000012 +- 0x00000bd1 +- 0x00000000 +- 0x000002f4 +- 0x00000001 +- 0x00000008 +- 0x00000001 +- 0x00000000 +- 0x00000063 +- 0x0000000f +- 0x0000006c +- 0x00000200 +- 0x00000004 +- 0x00000005 +- 0x00000004 +- 0x0000000b +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00000c11 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x104ab098 +- 0x002c00a0 +- 0x00008000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00070000 +- 0x00070000 +- 0x00000000 +- 0x00070000 +- 0x00070000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00038000 +- 0x00038000 +- 0x00038000 +- 0x00038000 +- 0x00003800 +- 0x00003800 +- 0x00003800 +- 0x00003800 +- 0x10000280 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc081 +- 0x00000505 +- 0x81f1f108 +- 0x07070004 +- 0x00000000 +- 0x016eeeee +- 0x51451420 +- 0x00514514 +- 0x00514514 +- 0x51451400 +- 0x0000003f +- 0x000000c6 +- 0x00000000 +- 0x00000100 +- 0x015b000e +- 0x00000000 +- 0x00000003 +- 0x000052a3 +- 0x8000188b +- 0x00000009 +- >; +- }; +- +- timing-528000000 { +- clock-frequency = <528000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73300000>; +- nvidia,emc-cfg-2 = <0x0000089d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000941>; +- nvidia,emc-mrs-wait-cnt = <0x0139000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000018 +- 0x00000088 +- 0x00000000 +- 0x00000010 +- 0x00000006 +- 0x00000006 +- 0x00000009 +- 0x00000002 +- 0x0000000d +- 0x00000006 +- 0x00000006 +- 0x00000002 +- 0x00000002 +- 0x00000000 +- 0x00000003 +- 0x00000003 +- 0x00000006 +- 0x00000002 +- 0x00000000 +- 0x00000001 +- 0x00000009 +- 0x00030000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000010 +- 0x00000012 +- 0x00000014 +- 0x00000fd6 +- 0x00000000 +- 0x000003f5 +- 0x00000002 +- 0x0000000b +- 0x00000001 +- 0x00000000 +- 0x00000085 +- 0x00000012 +- 0x00000090 +- 0x00000200 +- 0x00000004 +- 0x00000005 +- 0x00000004 +- 0x00000010 +- 0x00000000 +- 0x00000006 +- 0x00000006 +- 0x00001017 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x104ab098 +- 0xe01200b1 +- 0x00008000 +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00054000 +- 0x00054000 +- 0x00000000 +- 0x00054000 +- 0x00054000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x0000000c +- 0x0000000c +- 0x0000000c +- 0x0000000c +- 0x0000000c +- 0x0000000c +- 0x0000000c +- 0x0000000c +- 0x100002a0 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc085 +- 0x00000505 +- 0x81f1f108 +- 0x07070004 +- 0x00000000 +- 0x016eeeee +- 0x51451420 +- 0x00514514 +- 0x00514514 +- 0x51451400 +- 0x0606003f +- 0x00000000 +- 0x00000000 +- 0x00000100 +- 0x0139000e +- 0x00000000 +- 0x00000003 +- 0x000042a0 +- 0x80002062 +- 0x0000000a +- >; +- }; +- +- timing-600000000 { +- clock-frequency = <600000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73300000>; +- nvidia,emc-cfg-2 = <0x0000089d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200010>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000b61>; +- nvidia,emc-mrs-wait-cnt = <0x0127000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x0000001b +- 0x0000009b +- 0x00000000 +- 0x00000013 +- 0x00000007 +- 0x00000007 +- 0x0000000b +- 0x00000003 +- 0x00000010 +- 0x00000007 +- 0x00000007 +- 0x00000002 +- 0x00000002 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x0000000a +- 0x00000002 +- 0x00000000 +- 0x00000003 +- 0x0000000b +- 0x00070000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000002 +- 0x00000012 +- 0x00000016 +- 0x00000018 +- 0x00001208 +- 0x00000000 +- 0x00000482 +- 0x00000002 +- 0x0000000d +- 0x00000001 +- 0x00000000 +- 0x00000097 +- 0x00000015 +- 0x000000a3 +- 0x00000200 +- 0x00000004 +- 0x00000005 +- 0x00000004 +- 0x00000013 +- 0x00000000 +- 0x00000006 +- 0x00000006 +- 0x00001248 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x104ab098 +- 0xe00e00b1 +- 0x00008000 +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00048000 +- 0x00048000 +- 0x00000000 +- 0x00048000 +- 0x00048000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x0000000d +- 0x0000000d +- 0x0000000d +- 0x0000000d +- 0x0000000d +- 0x0000000d +- 0x0000000d +- 0x0000000d +- 0x100002a0 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc085 +- 0x00000505 +- 0x81f1f108 +- 0x07070004 +- 0x00000000 +- 0x016eeeee +- 0x51451420 +- 0x00514514 +- 0x00514514 +- 0x51451400 +- 0x0606003f +- 0x00000000 +- 0x00000000 +- 0x00000100 +- 0x0127000e +- 0x00000000 +- 0x00000003 +- 0x000040a0 +- 0x800024aa +- 0x0000000e +- >; +- }; +- +- timing-792000000 { +- clock-frequency = <792000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73300000>; +- nvidia,emc-cfg-2 = <0x0000089d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200018>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000d71>; +- nvidia,emc-mrs-wait-cnt = <0x00f7000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040000>; +- nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000024 +- 0x000000cd +- 0x00000000 +- 0x00000019 +- 0x0000000a +- 0x00000008 +- 0x0000000d +- 0x00000004 +- 0x00000013 +- 0x0000000a +- 0x0000000a +- 0x00000004 +- 0x00000002 +- 0x00000000 +- 0x00000006 +- 0x00000006 +- 0x0000000b +- 0x00000002 +- 0x00000000 +- 0x00000002 +- 0x0000000d +- 0x00080000 +- 0x00000004 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000001 +- 0x00000014 +- 0x00000018 +- 0x0000001a +- 0x000017e2 +- 0x00000000 +- 0x000005f8 +- 0x00000003 +- 0x00000011 +- 0x00000001 +- 0x00000000 +- 0x000000c7 +- 0x00000018 +- 0x000000d7 +- 0x00000200 +- 0x00000005 +- 0x00000006 +- 0x00000005 +- 0x00000019 +- 0x00000000 +- 0x00000008 +- 0x00000008 +- 0x00001822 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x104ab098 +- 0xe00700b1 +- 0x00008000 +- 0x007fc008 +- 0x007fc008 +- 0x007fc008 +- 0x007fc008 +- 0x007fc008 +- 0x007fc008 +- 0x007fc008 +- 0x007fc008 +- 0x007fc008 +- 0x007fc008 +- 0x007fc008 +- 0x007fc008 +- 0x007fc008 +- 0x007fc008 +- 0x007fc008 +- 0x007fc008 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00034000 +- 0x00034000 +- 0x00000000 +- 0x00034000 +- 0x00034000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00000005 +- 0x00000005 +- 0x00000005 +- 0x00000005 +- 0x00000005 +- 0x00000005 +- 0x00000005 +- 0x00000005 +- 0x00000005 +- 0x00000005 +- 0x00000005 +- 0x00000005 +- 0x00000005 +- 0x00000005 +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x100002a0 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc085 +- 0x00000000 +- 0x81f1f108 +- 0x07070004 +- 0x00000000 +- 0x016eeeee +- 0x61861820 +- 0x00514514 +- 0x00514514 +- 0x61861800 +- 0x0606003f +- 0x00000000 +- 0x00000000 +- 0x00000100 +- 0x00f7000e +- 0x00000000 +- 0x00000004 +- 0x00004080 +- 0x80003012 +- 0x0000000f +- >; +- }; +- +- timing-924000000 { +- clock-frequency = <924000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430303>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73300000>; +- nvidia,emc-cfg-2 = <0x0000089d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200020>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000f15>; +- nvidia,emc-mrs-wait-cnt = <0x00cd000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040000>; +- nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; +- nvidia,emc-zcal-cnt-long = <0x0000004c>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x0000002b +- 0x000000f0 +- 0x00000000 +- 0x0000001e +- 0x0000000b +- 0x00000009 +- 0x0000000f +- 0x00000005 +- 0x00000016 +- 0x0000000b +- 0x0000000b +- 0x00000004 +- 0x00000002 +- 0x00000000 +- 0x00000007 +- 0x00000007 +- 0x0000000d +- 0x00000002 +- 0x00000000 +- 0x00000002 +- 0x0000000f +- 0x000a0000 +- 0x00000004 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000001 +- 0x00000016 +- 0x0000001a +- 0x0000001c +- 0x00001be7 +- 0x00000000 +- 0x000006f9 +- 0x00000004 +- 0x00000015 +- 0x00000001 +- 0x00000000 +- 0x000000e7 +- 0x0000001b +- 0x000000fb +- 0x00000200 +- 0x00000006 +- 0x00000007 +- 0x00000006 +- 0x0000001e +- 0x00000000 +- 0x0000000a +- 0x0000000a +- 0x00001c28 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x104ab898 +- 0xe00400b1 +- 0x00008000 +- 0x007f800a +- 0x007f800a +- 0x007f800a +- 0x007f800a +- 0x007f800a +- 0x007f800a +- 0x007f800a +- 0x007f800a +- 0x007f800a +- 0x007f800a +- 0x007f800a +- 0x007f800a +- 0x007f800a +- 0x007f800a +- 0x007f800a +- 0x007f800a +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x0002c000 +- 0x0002c000 +- 0x00000000 +- 0x0002c000 +- 0x0002c000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000004 +- 0x00000004 +- 0x00000004 +- 0x00000004 +- 0x00000004 +- 0x00000004 +- 0x00000004 +- 0x00000004 +- 0x00000004 +- 0x00000004 +- 0x00000004 +- 0x00000004 +- 0x00000004 +- 0x00000004 +- 0x00000004 +- 0x00000004 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x100002a0 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc085 +- 0x00000000 +- 0x81f1f108 +- 0x07070004 +- 0x00000000 +- 0x016eeeee +- 0x5d75d720 +- 0x00514514 +- 0x00514514 +- 0x5d75d700 +- 0x0606003f +- 0x00000000 +- 0x00000000 +- 0x00000128 +- 0x00cd000e +- 0x00000000 +- 0x00000004 +- 0x00004080 +- 0x800037ea +- 0x00000011 +- >; +- }; +- +- }; +- }; +- +- memory-controller@70019000 { +- emc-timings-3 { +- nvidia,ram-code = <3>; +- +- timing-12750000 { +- clock-frequency = <12750000>; +- +- nvidia,emem-configuration = < +- 0x40040001 +- 0x8000000a +- 0x00000001 +- 0x00000001 +- 0x00000002 +- 0x00000000 +- 0x00000002 +- 0x00000001 +- 0x00000003 +- 0x00000008 +- 0x00000003 +- 0x00000002 +- 0x00000003 +- 0x00000006 +- 0x06030203 +- 0x000a0502 +- 0x77e30303 +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-20400000 { +- clock-frequency = <20400000>; +- +- nvidia,emem-configuration = < +- 0x40020001 +- 0x80000012 +- 0x00000001 +- 0x00000001 +- 0x00000002 +- 0x00000000 +- 0x00000002 +- 0x00000001 +- 0x00000003 +- 0x00000008 +- 0x00000003 +- 0x00000002 +- 0x00000003 +- 0x00000006 +- 0x06030203 +- 0x000a0502 +- 0x76230303 +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-40800000 { +- clock-frequency = <40800000>; +- +- nvidia,emem-configuration = < +- 0xa0000001 +- 0x80000017 +- 0x00000001 +- 0x00000001 +- 0x00000002 +- 0x00000000 +- 0x00000002 +- 0x00000001 +- 0x00000003 +- 0x00000008 +- 0x00000003 +- 0x00000002 +- 0x00000003 +- 0x00000006 +- 0x06030203 +- 0x000a0502 +- 0x74a30303 +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-68000000 { +- clock-frequency = <68000000>; +- +- nvidia,emem-configuration = < +- 0x00000001 +- 0x8000001e +- 0x00000001 +- 0x00000001 +- 0x00000002 +- 0x00000000 +- 0x00000002 +- 0x00000001 +- 0x00000003 +- 0x00000008 +- 0x00000003 +- 0x00000002 +- 0x00000003 +- 0x00000006 +- 0x06030203 +- 0x000a0502 +- 0x74230403 +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-102000000 { +- clock-frequency = <102000000>; +- +- nvidia,emem-configuration = < +- 0x08000001 +- 0x80000026 +- 0x00000001 +- 0x00000001 +- 0x00000003 +- 0x00000000 +- 0x00000002 +- 0x00000001 +- 0x00000003 +- 0x00000008 +- 0x00000003 +- 0x00000002 +- 0x00000003 +- 0x00000006 +- 0x06030203 +- 0x000a0503 +- 0x73c30504 +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-204000000 { +- clock-frequency = <204000000>; +- +- nvidia,emem-configuration = < +- 0x01000003 +- 0x80000040 +- 0x00000001 +- 0x00000001 +- 0x00000004 +- 0x00000002 +- 0x00000003 +- 0x00000001 +- 0x00000003 +- 0x00000008 +- 0x00000003 +- 0x00000002 +- 0x00000004 +- 0x00000006 +- 0x06040203 +- 0x000a0504 +- 0x73840a05 +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-300000000 { +- clock-frequency = <300000000>; +- +- nvidia,emem-configuration = < +- 0x08000004 +- 0x80000040 +- 0x00000001 +- 0x00000002 +- 0x00000007 +- 0x00000004 +- 0x00000004 +- 0x00000001 +- 0x00000002 +- 0x00000007 +- 0x00000002 +- 0x00000002 +- 0x00000004 +- 0x00000006 +- 0x06040202 +- 0x000b0607 +- 0x77450e08 +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-396000000 { +- clock-frequency = <396000000>; +- +- nvidia,emem-configuration = < +- 0x0f000005 +- 0x80000040 +- 0x00000001 +- 0x00000002 +- 0x00000009 +- 0x00000005 +- 0x00000006 +- 0x00000001 +- 0x00000002 +- 0x00000008 +- 0x00000002 +- 0x00000002 +- 0x00000004 +- 0x00000006 +- 0x06040202 +- 0x000d0709 +- 0x7586120a +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-528000000 { +- clock-frequency = <528000000>; +- +- nvidia,emem-configuration = < +- 0x0f000007 +- 0x80000040 +- 0x00000002 +- 0x00000003 +- 0x0000000c +- 0x00000007 +- 0x00000008 +- 0x00000001 +- 0x00000002 +- 0x00000009 +- 0x00000002 +- 0x00000002 +- 0x00000005 +- 0x00000006 +- 0x06050202 +- 0x0010090c +- 0x7428180d +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-600000000 { +- clock-frequency = <600000000>; +- +- nvidia,emem-configuration = < +- 0x00000009 +- 0x80000040 +- 0x00000003 +- 0x00000004 +- 0x0000000e +- 0x00000009 +- 0x0000000a +- 0x00000001 +- 0x00000003 +- 0x0000000b +- 0x00000002 +- 0x00000002 +- 0x00000005 +- 0x00000007 +- 0x07050202 +- 0x00130b0e +- 0x73a91b0f +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-792000000 { +- clock-frequency = <792000000>; +- +- nvidia,emem-configuration = < +- 0x0e00000b +- 0x80000040 +- 0x00000004 +- 0x00000005 +- 0x00000013 +- 0x0000000c +- 0x0000000d +- 0x00000002 +- 0x00000003 +- 0x0000000c +- 0x00000002 +- 0x00000002 +- 0x00000006 +- 0x00000008 +- 0x08060202 +- 0x00170e13 +- 0x736c2414 +- 0x70000f02 +- 0x001f0000 +- >; +- }; +- +- timing-924000000 { +- clock-frequency = <924000000>; +- +- nvidia,emem-configuration = < +- 0x0e00000d +- 0x80000040 +- 0x00000005 +- 0x00000006 +- 0x00000016 +- 0x0000000e +- 0x0000000f +- 0x00000002 +- 0x00000004 +- 0x0000000e +- 0x00000002 +- 0x00000002 +- 0x00000006 +- 0x00000009 +- 0x09060202 +- 0x001a1016 +- 0x734e2a17 +- 0x70000f02 +- 0x001f0000 +- >; +- }; +- }; +- }; +-}; +- +-&emc_icc_dvfs_opp_table { +- /delete-node/ opp@1200000000,1100; +-}; +- +-&emc_bw_dfs_opp_table { +- /delete-node/ opp@1200000000; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra124-jetson-tk1.dts b/scripts/dtc/include-prefixes/arm/tegra124-jetson-tk1.dts +deleted file mode 100644 +index 35ab296408e1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra124-jetson-tk1.dts ++++ /dev/null +@@ -1,2077 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include "tegra124.dtsi" +- +-#include "tegra124-jetson-tk1-emc.dtsi" +- +-/ { +- model = "NVIDIA Tegra124 Jetson TK1"; +- compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; +- +- aliases { +- rtc0 = "/i2c@7000d000/pmic@40"; +- rtc1 = "/rtc@7000e000"; +- +- /* This order keeps the mapping DB9 connector <-> ttyS0 */ +- serial0 = &uartd; +- serial1 = &uarta; +- serial2 = &uartb; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@80000000 { +- reg = <0x0 0x80000000 0x0 0x80000000>; +- }; +- +- pcie@1003000 { +- status = "okay"; +- +- avddio-pex-supply = <&vdd_1v05_run>; +- dvddio-pex-supply = <&vdd_1v05_run>; +- avdd-pex-pll-supply = <&vdd_1v05_run>; +- hvdd-pex-supply = <&vdd_3v3_lp0>; +- hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; +- vddio-pex-ctl-supply = <&vdd_3v3_lp0>; +- avdd-pll-erefe-supply = <&avdd_1v05_run>; +- +- /* Mini PCIe */ +- pci@1,0 { +- phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; +- phy-names = "pcie-0"; +- status = "okay"; +- }; +- +- /* Gigabit Ethernet */ +- pci@2,0 { +- phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; +- phy-names = "pcie-0"; +- status = "okay"; +- }; +- }; +- +- host1x@50000000 { +- hdmi@54280000 { +- status = "okay"; +- +- hdmi-supply = <&vdd_5v0_hdmi>; +- pll-supply = <&vdd_hdmi_pll>; +- vdd-supply = <&vdd_3v3_hdmi>; +- +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = +- <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- cec@70015000 { +- status = "okay"; +- }; +- +- gpu@0,57000000 { +- /* +- * Node left disabled on purpose - the bootloader will enable +- * it after having set the VPR up +- */ +- vdd-supply = <&vdd_gpu>; +- }; +- +- pinmux: pinmux@70000868 { +- pinctrl-names = "boot"; +- pinctrl-0 = <&state_boot>; +- +- state_boot: pinmux { +- clk_32k_out_pa0 { +- nvidia,pins = "clk_32k_out_pa0"; +- nvidia,function = "soc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_cts_n_pa1 { +- nvidia,pins = "uart3_cts_n_pa1"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_fs_pa2 { +- nvidia,pins = "dap2_fs_pa2"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_sclk_pa3 { +- nvidia,pins = "dap2_sclk_pa3"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_din_pa4 { +- nvidia,pins = "dap2_din_pa4"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_dout_pa5 { +- nvidia,pins = "dap2_dout_pa5"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_clk_pa6 { +- nvidia,pins = "sdmmc3_clk_pa6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_cmd_pa7 { +- nvidia,pins = "sdmmc3_cmd_pa7"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pb0 { +- nvidia,pins = "pb0"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pb1 { +- nvidia,pins = "pb1"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat3_pb4 { +- nvidia,pins = "sdmmc3_dat3_pb4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat2_pb5 { +- nvidia,pins = "sdmmc3_dat2_pb5"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat1_pb6 { +- nvidia,pins = "sdmmc3_dat1_pb6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat0_pb7 { +- nvidia,pins = "sdmmc3_dat0_pb7"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_rts_n_pc0 { +- nvidia,pins = "uart3_rts_n_pc0"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_txd_pc2 { +- nvidia,pins = "uart2_txd_pc2"; +- nvidia,function = "irda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_rxd_pc3 { +- nvidia,pins = "uart2_rxd_pc3"; +- nvidia,function = "irda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gen1_i2c_scl_pc4 { +- nvidia,pins = "gen1_i2c_scl_pc4"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen1_i2c_sda_pc5 { +- nvidia,pins = "gen1_i2c_sda_pc5"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pc7 { +- nvidia,pins = "pc7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg0 { +- nvidia,pins = "pg0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg1 { +- nvidia,pins = "pg1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg2 { +- nvidia,pins = "pg2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg3 { +- nvidia,pins = "pg3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg4 { +- nvidia,pins = "pg4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg5 { +- nvidia,pins = "pg5"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg6 { +- nvidia,pins = "pg6"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg7 { +- nvidia,pins = "pg7"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph0 { +- nvidia,pins = "ph0"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph1 { +- nvidia,pins = "ph1"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph2 { +- nvidia,pins = "ph2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph3 { +- nvidia,pins = "ph3"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph4 { +- nvidia,pins = "ph4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph5 { +- nvidia,pins = "ph5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph6 { +- nvidia,pins = "ph6"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph7 { +- nvidia,pins = "ph7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi0 { +- nvidia,pins = "pi0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi1 { +- nvidia,pins = "pi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi2 { +- nvidia,pins = "pi2"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi3 { +- nvidia,pins = "pi3"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi4 { +- nvidia,pins = "pi4"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi5 { +- nvidia,pins = "pi5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi6 { +- nvidia,pins = "pi6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi7 { +- nvidia,pins = "pi7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pj0 { +- nvidia,pins = "pj0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pj2 { +- nvidia,pins = "pj2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_cts_n_pj5 { +- nvidia,pins = "uart2_cts_n_pj5"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_rts_n_pj6 { +- nvidia,pins = "uart2_rts_n_pj6"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pj7 { +- nvidia,pins = "pj7"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk0 { +- nvidia,pins = "pk0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk1 { +- nvidia,pins = "pk1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk2 { +- nvidia,pins = "pk2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk3 { +- nvidia,pins = "pk3"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk4 { +- nvidia,pins = "pk4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spdif_out_pk5 { +- nvidia,pins = "spdif_out_pk5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spdif_in_pk6 { +- nvidia,pins = "spdif_in_pk6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk7 { +- nvidia,pins = "pk7"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_fs_pn0 { +- nvidia,pins = "dap1_fs_pn0"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_din_pn1 { +- nvidia,pins = "dap1_din_pn1"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_dout_pn2 { +- nvidia,pins = "dap1_dout_pn2"; +- nvidia,function = "sata"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_sclk_pn3 { +- nvidia,pins = "dap1_sclk_pn3"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- usb_vbus_en0_pn4 { +- nvidia,pins = "usb_vbus_en0_pn4"; +- nvidia,function = "usb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- usb_vbus_en1_pn5 { +- nvidia,pins = "usb_vbus_en1_pn5"; +- nvidia,function = "usb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- hdmi_int_pn7 { +- nvidia,pins = "hdmi_int_pn7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,rcv-sel = ; +- }; +- ulpi_data7_po0 { +- nvidia,pins = "ulpi_data7_po0"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data0_po1 { +- nvidia,pins = "ulpi_data0_po1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data1_po2 { +- nvidia,pins = "ulpi_data1_po2"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data2_po3 { +- nvidia,pins = "ulpi_data2_po3"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data3_po4 { +- nvidia,pins = "ulpi_data3_po4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data4_po5 { +- nvidia,pins = "ulpi_data4_po5"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data5_po6 { +- nvidia,pins = "ulpi_data5_po6"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data6_po7 { +- nvidia,pins = "ulpi_data6_po7"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_fs_pp0 { +- nvidia,pins = "dap3_fs_pp0"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_din_pp1 { +- nvidia,pins = "dap3_din_pp1"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_dout_pp2 { +- nvidia,pins = "dap3_dout_pp2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_sclk_pp3 { +- nvidia,pins = "dap3_sclk_pp3"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_fs_pp4 { +- nvidia,pins = "dap4_fs_pp4"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_din_pp5 { +- nvidia,pins = "dap4_din_pp5"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_dout_pp6 { +- nvidia,pins = "dap4_dout_pp6"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_sclk_pp7 { +- nvidia,pins = "dap4_sclk_pp7"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col0_pq0 { +- nvidia,pins = "kb_col0_pq0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col1_pq1 { +- nvidia,pins = "kb_col1_pq1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col2_pq2 { +- nvidia,pins = "kb_col2_pq2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col3_pq3 { +- nvidia,pins = "kb_col3_pq3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col4_pq4 { +- nvidia,pins = "kb_col4_pq4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col5_pq5 { +- nvidia,pins = "kb_col5_pq5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col6_pq6 { +- nvidia,pins = "kb_col6_pq6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col7_pq7 { +- nvidia,pins = "kb_col7_pq7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row0_pr0 { +- nvidia,pins = "kb_row0_pr0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row1_pr1 { +- nvidia,pins = "kb_row1_pr1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row2_pr2 { +- nvidia,pins = "kb_row2_pr2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row3_pr3 { +- nvidia,pins = "kb_row3_pr3"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row4_pr4 { +- nvidia,pins = "kb_row4_pr4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row5_pr5 { +- nvidia,pins = "kb_row5_pr5"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row6_pr6 { +- nvidia,pins = "kb_row6_pr6"; +- nvidia,function = "displaya_alt"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row7_pr7 { +- nvidia,pins = "kb_row7_pr7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row8_ps0 { +- nvidia,pins = "kb_row8_ps0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row9_ps1 { +- nvidia,pins = "kb_row9_ps1"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row10_ps2 { +- nvidia,pins = "kb_row10_ps2"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row11_ps3 { +- nvidia,pins = "kb_row11_ps3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row12_ps4 { +- nvidia,pins = "kb_row12_ps4"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row13_ps5 { +- nvidia,pins = "kb_row13_ps5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row14_ps6 { +- nvidia,pins = "kb_row14_ps6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row15_ps7 { +- nvidia,pins = "kb_row15_ps7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row16_pt0 { +- nvidia,pins = "kb_row16_pt0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row17_pt1 { +- nvidia,pins = "kb_row17_pt1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gen2_i2c_scl_pt5 { +- nvidia,pins = "gen2_i2c_scl_pt5"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen2_i2c_sda_pt6 { +- nvidia,pins = "gen2_i2c_sda_pt6"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc4_cmd_pt7 { +- nvidia,pins = "sdmmc4_cmd_pt7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu0 { +- nvidia,pins = "pu0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu1 { +- nvidia,pins = "pu1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu2 { +- nvidia,pins = "pu2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu3 { +- nvidia,pins = "pu3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu4 { +- nvidia,pins = "pu4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu5 { +- nvidia,pins = "pu5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu6 { +- nvidia,pins = "pu6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv0 { +- nvidia,pins = "pv0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv1 { +- nvidia,pins = "pv1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_cd_n_pv2 { +- nvidia,pins = "sdmmc3_cd_n_pv2"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_wp_n_pv3 { +- nvidia,pins = "sdmmc1_wp_n_pv3"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ddc_scl_pv4 { +- nvidia,pins = "ddc_scl_pv4"; +- nvidia,function = "i2c4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,rcv-sel = ; +- }; +- ddc_sda_pv5 { +- nvidia,pins = "ddc_sda_pv5"; +- nvidia,function = "i2c4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,rcv-sel = ; +- }; +- gpio_w2_aud_pw2 { +- nvidia,pins = "gpio_w2_aud_pw2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_w3_aud_pw3 { +- nvidia,pins = "gpio_w3_aud_pw3"; +- nvidia,function = "spi6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap_mclk1_pw4 { +- nvidia,pins = "dap_mclk1_pw4"; +- nvidia,function = "extperiph1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2_out_pw5 { +- nvidia,pins = "clk2_out_pw5"; +- nvidia,function = "extperiph2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_txd_pw6 { +- nvidia,pins = "uart3_txd_pw6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_rxd_pw7 { +- nvidia,pins = "uart3_rxd_pw7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dvfs_pwm_px0 { +- nvidia,pins = "dvfs_pwm_px0"; +- nvidia,function = "cldvfs"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x1_aud_px1 { +- nvidia,pins = "gpio_x1_aud_px1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dvfs_clk_px2 { +- nvidia,pins = "dvfs_clk_px2"; +- nvidia,function = "cldvfs"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x3_aud_px3 { +- nvidia,pins = "gpio_x3_aud_px3"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x4_aud_px4 { +- nvidia,pins = "gpio_x4_aud_px4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x5_aud_px5 { +- nvidia,pins = "gpio_x5_aud_px5"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x6_aud_px6 { +- nvidia,pins = "gpio_x6_aud_px6"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x7_aud_px7 { +- nvidia,pins = "gpio_x7_aud_px7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_clk_py0 { +- nvidia,pins = "ulpi_clk_py0"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_dir_py1 { +- nvidia,pins = "ulpi_dir_py1"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_nxt_py2 { +- nvidia,pins = "ulpi_nxt_py2"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_stp_py3 { +- nvidia,pins = "ulpi_stp_py3"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat3_py4 { +- nvidia,pins = "sdmmc1_dat3_py4"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat2_py5 { +- nvidia,pins = "sdmmc1_dat2_py5"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat1_py6 { +- nvidia,pins = "sdmmc1_dat1_py6"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat0_py7 { +- nvidia,pins = "sdmmc1_dat0_py7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_clk_pz0 { +- nvidia,pins = "sdmmc1_clk_pz0"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_cmd_pz1 { +- nvidia,pins = "sdmmc1_cmd_pz1"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pwr_i2c_scl_pz6 { +- nvidia,pins = "pwr_i2c_scl_pz6"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pwr_i2c_sda_pz7 { +- nvidia,pins = "pwr_i2c_sda_pz7"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc4_dat0_paa0 { +- nvidia,pins = "sdmmc4_dat0_paa0"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat1_paa1 { +- nvidia,pins = "sdmmc4_dat1_paa1"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat2_paa2 { +- nvidia,pins = "sdmmc4_dat2_paa2"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat3_paa3 { +- nvidia,pins = "sdmmc4_dat3_paa3"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat4_paa4 { +- nvidia,pins = "sdmmc4_dat4_paa4"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat5_paa5 { +- nvidia,pins = "sdmmc4_dat5_paa5"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat6_paa6 { +- nvidia,pins = "sdmmc4_dat6_paa6"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat7_paa7 { +- nvidia,pins = "sdmmc4_dat7_paa7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb0 { +- nvidia,pins = "pbb0"; +- nvidia,function = "vimclk2_alt"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cam_i2c_scl_pbb1 { +- nvidia,pins = "cam_i2c_scl_pbb1"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_i2c_sda_pbb2 { +- nvidia,pins = "cam_i2c_sda_pbb2"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pbb3 { +- nvidia,pins = "pbb3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb4 { +- nvidia,pins = "pbb4"; +- nvidia,function = "vgp4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb5 { +- nvidia,pins = "pbb5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb6 { +- nvidia,pins = "pbb6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb7 { +- nvidia,pins = "pbb7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cam_mclk_pcc0 { +- nvidia,pins = "cam_mclk_pcc0"; +- nvidia,function = "vi_alt3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pcc1 { +- nvidia,pins = "pcc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pcc2 { +- nvidia,pins = "pcc2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_clk_pcc4 { +- nvidia,pins = "sdmmc4_clk_pcc4"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2_req_pcc5 { +- nvidia,pins = "clk2_req_pcc5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l0_rst_n_pdd1 { +- nvidia,pins = "pex_l0_rst_n_pdd1"; +- nvidia,function = "pe0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l0_clkreq_n_pdd2 { +- nvidia,pins = "pex_l0_clkreq_n_pdd2"; +- nvidia,function = "pe0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_wake_n_pdd3 { +- nvidia,pins = "pex_wake_n_pdd3"; +- nvidia,function = "pe"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l1_rst_n_pdd5 { +- nvidia,pins = "pex_l1_rst_n_pdd5"; +- nvidia,function = "pe1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l1_clkreq_n_pdd6 { +- nvidia,pins = "pex_l1_clkreq_n_pdd6"; +- nvidia,function = "pe1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3_out_pee0 { +- nvidia,pins = "clk3_out_pee0"; +- nvidia,function = "extperiph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3_req_pee1 { +- nvidia,pins = "clk3_req_pee1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap_mclk1_req_pee2 { +- nvidia,pins = "dap_mclk1_req_pee2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- hdmi_cec_pee3 { +- nvidia,pins = "hdmi_cec_pee3"; +- nvidia,function = "cec"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_clk_lb_out_pee4 { +- nvidia,pins = "sdmmc3_clk_lb_out_pee4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_clk_lb_in_pee5 { +- nvidia,pins = "sdmmc3_clk_lb_in_pee5"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dp_hpd_pff0 { +- nvidia,pins = "dp_hpd_pff0"; +- nvidia,function = "dp"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- usb_vbus_en2_pff1 { +- nvidia,pins = "usb_vbus_en2_pff1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pff2 { +- nvidia,pins = "pff2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- core_pwr_req { +- nvidia,pins = "core_pwr_req"; +- nvidia,function = "pwron"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cpu_pwr_req { +- nvidia,pins = "cpu_pwr_req"; +- nvidia,function = "cpu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pwr_int_n { +- nvidia,pins = "pwr_int_n"; +- nvidia,function = "pmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- reset_out_n { +- nvidia,pins = "reset_out_n"; +- nvidia,function = "reset_out_n"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk_32k_in { +- nvidia,pins = "clk_32k_in"; +- nvidia,function = "clk"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- jtag_rtck { +- nvidia,pins = "jtag_rtck"; +- nvidia,function = "rtck"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dsi_b { +- nvidia,pins = "mipi_pad_ctrl_dsi_b"; +- nvidia,function = "dsi_b"; +- }; +- }; +- }; +- +- /* +- * First high speed UART, exposed on the expansion connector J3A2 +- * Pin 41: BR_UART1_TXD +- * Pin 44: BR_UART1_RXD +- */ +- serial@70006000 { +- compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; +- status = "okay"; +- }; +- +- /* +- * Second high speed UART, exposed on the expansion connector J3A2 +- * Pin 65: UART2_RXD +- * Pin 68: UART2_TXD +- * Pin 71: UART2_CTS_L +- * Pin 74: UART2_RTS_L +- */ +- serial@70006040 { +- compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; +- status = "okay"; +- }; +- +- /* DB9 serial port */ +- serial@70006300 { +- status = "okay"; +- }; +- +- /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */ +- i2c@7000c000 { +- status = "okay"; +- clock-frequency = <100000>; +- +- rt5639: audio-codec@1c { +- compatible = "realtek,rt5639"; +- reg = <0x1c>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- realtek,ldo1-en-gpios = +- <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; +- }; +- +- temperature-sensor@4c { +- compatible = "ti,tmp451"; +- reg = <0x4c>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- }; +- +- eeprom@56 { +- compatible = "atmel,24c02"; +- reg = <0x56>; +- pagesize = <8>; +- }; +- }; +- +- /* Expansion GEN2_I2C_* */ +- i2c@7000c400 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- /* Expansion CAM_I2C_* */ +- i2c@7000c500 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- /* HDMI DDC */ +- hdmi_ddc: i2c@7000c700 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- /* Expansion PWR_I2C_*, on-board components */ +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- pmic: pmic@40 { +- compatible = "ams,as3722"; +- reg = <0x40>; +- interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; +- +- ams,system-power-controller; +- +- #interrupt-cells = <2>; +- interrupt-controller; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&as3722_default>; +- +- as3722_default: pinmux { +- gpio0 { +- pins = "gpio0"; +- function = "gpio"; +- bias-pull-down; +- }; +- +- gpio1_2_4_7 { +- pins = "gpio1", "gpio2", "gpio4", "gpio7"; +- function = "gpio"; +- bias-pull-up; +- }; +- +- gpio3_5_6 { +- pins = "gpio3", "gpio5", "gpio6"; +- bias-high-impedance; +- }; +- }; +- +- regulators { +- vsup-sd2-supply = <&vdd_5v0_sys>; +- vsup-sd3-supply = <&vdd_5v0_sys>; +- vsup-sd4-supply = <&vdd_5v0_sys>; +- vsup-sd5-supply = <&vdd_5v0_sys>; +- vin-ldo0-supply = <&vdd_1v35_lp0>; +- vin-ldo1-6-supply = <&vdd_3v3_run>; +- vin-ldo2-5-7-supply = <&vddio_1v8>; +- vin-ldo3-4-supply = <&vdd_3v3_sys>; +- vin-ldo9-10-supply = <&vdd_5v0_sys>; +- vin-ldo11-supply = <&vdd_3v3_run>; +- +- vdd_cpu: sd0 { +- regulator-name = "+VDD_CPU_AP"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1400000>; +- regulator-min-microamp = <3500000>; +- regulator-max-microamp = <3500000>; +- regulator-always-on; +- regulator-boot-on; +- ams,ext-control = <2>; +- }; +- +- sd1 { +- regulator-name = "+VDD_CORE"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-min-microamp = <2500000>; +- regulator-max-microamp = <2500000>; +- regulator-always-on; +- regulator-boot-on; +- ams,ext-control = <1>; +- }; +- +- vdd_1v35_lp0: sd2 { +- regulator-name = "+1.35V_LP0(sd2)"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- sd3 { +- regulator-name = "+1.35V_LP0(sd3)"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v05_run: sd4 { +- regulator-name = "+1.05V_RUN"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- vddio_1v8: sd5 { +- regulator-name = "+1.8V_VDDIO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd_gpu: sd6 { +- regulator-name = "+VDD_GPU_AP"; +- regulator-min-microvolt = <650000>; +- regulator-max-microvolt = <1200000>; +- regulator-min-microamp = <3500000>; +- regulator-max-microamp = <3500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- avdd_1v05_run: ldo0 { +- regulator-name = "+1.05V_RUN_AVDD"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-boot-on; +- regulator-always-on; +- ams,ext-control = <1>; +- }; +- +- ldo1 { +- regulator-name = "+1.8V_RUN_CAM"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo2 { +- regulator-name = "+1.2V_GEN_AVDD"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo3 { +- regulator-name = "+1.05V_LP0_VDD_RTC"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-boot-on; +- regulator-always-on; +- ams,enable-tracking; +- }; +- +- ldo4 { +- regulator-name = "+2.8V_RUN_CAM"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo5 { +- regulator-name = "+1.2V_RUN_CAM_FRONT"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- vddio_sdmmc3: ldo6 { +- regulator-name = "+VDDIO_SDMMC3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo7 { +- regulator-name = "+1.05V_RUN_CAM_REAR"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- ldo9 { +- regulator-name = "+3.3V_RUN_TOUCH"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo10 { +- regulator-name = "+2.8V_RUN_CAM_AF"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo11 { +- regulator-name = "+1.8V_RUN_VPP_FUSE"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- }; +- }; +- }; +- +- /* Expansion TS_SPI_* */ +- spi@7000d400 { +- status = "okay"; +- }; +- +- /* Internal SPI */ +- spi@7000da00 { +- status = "okay"; +- spi-max-frequency = <25000000>; +- spi-flash@0 { +- compatible = "winbond,w25q32dw", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- }; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <500>; +- nvidia,cpu-pwr-off-time = <300>; +- nvidia,core-pwr-good-time = <641 3845>; +- nvidia,core-pwr-off-time = <61036>; +- nvidia,core-power-req-active-high; +- nvidia,sys-clock-req-active-high; +- +- i2c-thermtrip { +- nvidia,i2c-controller-id = <4>; +- nvidia,bus-addr = <0x40>; +- nvidia,reg-addr = <0x36>; +- nvidia,reg-data = <0x2>; +- }; +- }; +- +- /* Serial ATA */ +- sata@70020000 { +- status = "okay"; +- +- phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; +- phy-names = "sata-0"; +- +- hvdd-supply = <&vdd_3v3_lp0>; +- vddio-supply = <&vdd_1v05_run>; +- avdd-supply = <&vdd_1v05_run>; +- +- target-5v-supply = <&vdd_5v0_sata>; +- target-12v-supply = <&vdd_12v0_sata>; +- }; +- +- hda@70030000 { +- status = "okay"; +- }; +- +- usb@70090000 { +- phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */ +- <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */ +- <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */ +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */ +- phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; +- +- avddio-pex-supply = <&vdd_1v05_run>; +- dvddio-pex-supply = <&vdd_1v05_run>; +- avdd-usb-supply = <&vdd_3v3_lp0>; +- avdd-pll-utmip-supply = <&vddio_1v8>; +- avdd-pll-erefe-supply = <&avdd_1v05_run>; +- avdd-usb-ss-pll-supply = <&vdd_1v05_run>; +- hvdd-usb-ss-supply = <&vdd_3v3_lp0>; +- hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; +- +- status = "okay"; +- }; +- +- padctl@7009f000 { +- status = "okay"; +- +- avdd-pll-utmip-supply = <&vddio_1v8>; +- avdd-pll-erefe-supply = <&avdd_1v05_run>; +- avdd-pex-pll-supply = <&vdd_1v05_run>; +- hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; +- +- pads { +- usb2 { +- status = "okay"; +- +- lanes { +- usb2-0 { +- nvidia,function = "snps"; +- status = "okay"; +- }; +- +- usb2-1 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- +- usb2-2 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- }; +- }; +- +- pcie { +- status = "okay"; +- +- lanes { +- pcie-0 { +- nvidia,function = "usb3-ss"; +- status = "okay"; +- }; +- +- pcie-2 { +- nvidia,function = "pcie"; +- status = "okay"; +- }; +- +- pcie-4 { +- nvidia,function = "pcie"; +- status = "okay"; +- }; +- }; +- }; +- +- sata { +- status = "okay"; +- +- lanes { +- sata-0 { +- nvidia,function = "sata"; +- status = "okay"; +- }; +- }; +- }; +- }; +- +- ports { +- /* Micro A/B */ +- usb2-0 { +- status = "okay"; +- mode = "host"; +- }; +- +- /* Mini PCIe */ +- usb2-1 { +- status = "okay"; +- mode = "host"; +- }; +- +- /* USB3 */ +- usb2-2 { +- status = "okay"; +- mode = "host"; +- +- vbus-supply = <&vdd_usb3_vbus>; +- }; +- +- usb3-0 { +- nvidia,usb2-companion = <2>; +- status = "okay"; +- }; +- }; +- }; +- +- /* SD card */ +- mmc@700b0400 { +- status = "okay"; +- cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; +- power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; +- wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; +- bus-width = <4>; +- vqmmc-supply = <&vddio_sdmmc3>; +- }; +- +- /* eMMC */ +- mmc@700b0600 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- }; +- +- /* CPU DFLL clock */ +- clock@70110000 { +- status = "okay"; +- vdd-cpu-supply = <&vdd_cpu>; +- nvidia,i2c-fs-rate = <400000>; +- }; +- +- ahub@70300000 { +- i2s@70301100 { +- status = "okay"; +- }; +- }; +- +- usb@7d000000 { +- compatible = "nvidia,tegra124-udc"; +- status = "okay"; +- dr_mode = "peripheral"; +- }; +- +- usb-phy@7d000000 { +- status = "okay"; +- }; +- +- /* mini-PCIe USB */ +- usb@7d004000 { +- status = "okay"; +- }; +- +- usb-phy@7d004000 { +- status = "okay"; +- }; +- +- /* USB A connector */ +- usb@7d008000 { +- status = "okay"; +- }; +- +- usb-phy@7d008000 { +- status = "okay"; +- vbus-supply = <&vdd_usb3_vbus>; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- cpus { +- cpu@0 { +- vdd-cpu-supply = <&vdd_cpu>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "Power"; +- gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- vdd_mux: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "+VDD_MUX"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_5v0_sys: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "+5V_SYS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_mux>; +- }; +- +- vdd_3v3_sys: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "+3.3V_SYS"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_mux>; +- }; +- +- vdd_3v3_run: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "+3.3V_RUN"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_3v3_sys>; +- }; +- +- vdd_3v3_hdmi: regulator@4 { +- compatible = "regulator-fixed"; +- regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vdd_3v3_run>; +- }; +- +- vdd_usb1_vbus: regulator@5 { +- compatible = "regulator-fixed"; +- regulator-name = "+USB0_VBUS_SW"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- gpio-open-drain; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_usb3_vbus: regulator@6 { +- compatible = "regulator-fixed"; +- regulator-name = "+5V_USB_HS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- gpio-open-drain; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_3v3_lp0: regulator@7 { +- compatible = "regulator-fixed"; +- regulator-name = "+3.3V_LP0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_3v3_sys>; +- }; +- +- vdd_hdmi_pll: regulator@8 { +- compatible = "regulator-fixed"; +- regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; +- vin-supply = <&vdd_1v05_run>; +- }; +- +- vdd_5v0_hdmi: regulator@9 { +- compatible = "regulator-fixed"; +- regulator-name = "+5V_HDMI_CON"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- /* Molex power connector */ +- vdd_5v0_sata: regulator@10 { +- compatible = "regulator-fixed"; +- regulator-name = "+5V_SATA"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_12v0_sata: regulator@11 { +- compatible = "regulator-fixed"; +- regulator-name = "+12V_SATA"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_mux>; +- }; +- +- sound { +- compatible = "nvidia,tegra-audio-rt5640-jetson-tk1", +- "nvidia,tegra-audio-rt5640"; +- nvidia,model = "NVIDIA Tegra Jetson TK1"; +- +- nvidia,audio-routing = +- "Headphones", "HPOR", +- "Headphones", "HPOL", +- "Mic Jack", "MICBIAS1", +- "IN2P", "Mic Jack"; +- +- nvidia,i2s-controller = <&tegra_i2s1>; +- nvidia,audio-codec = <&rt5639>; +- +- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; +- +- clocks = <&tegra_car TEGRA124_CLK_PLL_A>, +- <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- +- assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- +- assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA124_CLK_EXTERN1>; +- }; +- +- thermal-zones { +- cpu { +- trips { +- cpu-shutdown-trip { +- temperature = <101000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- mem { +- trips { +- mem-shutdown-trip { +- temperature = <101000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- gpu { +- trips { +- gpu-shutdown-trip { +- temperature = <101000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra124-nyan-big-emc.dtsi b/scripts/dtc/include-prefixes/arm/tegra124-nyan-big-emc.dtsi +deleted file mode 100644 +index a0f56cc9da5c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra124-nyan-big-emc.dtsi ++++ /dev/null +@@ -1,6661 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- apbmisc@70000800 { +- nvidia,long-ram-code; +- }; +- +- clock@60006000 { +- emc-timings-1 { +- nvidia,ram-code = <1>; +- +- timing-12750000 { +- clock-frequency = <12750000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-20400000 { +- clock-frequency = <20400000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-40800000 { +- clock-frequency = <40800000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-68000000 { +- clock-frequency = <68000000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-102000000 { +- clock-frequency = <102000000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-204000000 { +- clock-frequency = <204000000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-300000000 { +- clock-frequency = <300000000>; +- nvidia,parent-clock-frequency = <600000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_C>; +- clock-names = "emc-parent"; +- }; +- timing-396000000 { +- clock-frequency = <396000000>; +- nvidia,parent-clock-frequency = <792000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_M>; +- clock-names = "emc-parent"; +- }; +- timing-528000000 { +- clock-frequency = <528000000>; +- nvidia,parent-clock-frequency = <528000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; +- clock-names = "emc-parent"; +- }; +- timing-600000000 { +- clock-frequency = <600000000>; +- nvidia,parent-clock-frequency = <600000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; +- clock-names = "emc-parent"; +- }; +- timing-792000000 { +- clock-frequency = <792000000>; +- nvidia,parent-clock-frequency = <792000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; +- clock-names = "emc-parent"; +- }; +- }; +- +- emc-timings-4 { +- nvidia,ram-code = <4>; +- +- timing-12750000 { +- clock-frequency = <12750000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-20400000 { +- clock-frequency = <20400000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-40800000 { +- clock-frequency = <40800000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-68000000 { +- clock-frequency = <68000000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-102000000 { +- clock-frequency = <102000000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-204000000 { +- clock-frequency = <204000000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-300000000 { +- clock-frequency = <300000000>; +- nvidia,parent-clock-frequency = <600000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_C>; +- clock-names = "emc-parent"; +- }; +- timing-396000000 { +- clock-frequency = <396000000>; +- nvidia,parent-clock-frequency = <792000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_M>; +- clock-names = "emc-parent"; +- }; +- timing-528000000 { +- clock-frequency = <528000000>; +- nvidia,parent-clock-frequency = <528000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; +- clock-names = "emc-parent"; +- }; +- timing-600000000 { +- clock-frequency = <600000000>; +- nvidia,parent-clock-frequency = <600000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; +- clock-names = "emc-parent"; +- }; +- timing-792000000 { +- clock-frequency = <792000000>; +- nvidia,parent-clock-frequency = <792000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; +- clock-names = "emc-parent"; +- }; +- }; +- +- emc-timings-6 { +- nvidia,ram-code = <6>; +- +- timing-12750000 { +- clock-frequency = <12750000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-20400000 { +- clock-frequency = <20400000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-40800000 { +- clock-frequency = <40800000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-68000000 { +- clock-frequency = <68000000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-102000000 { +- clock-frequency = <102000000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-204000000 { +- clock-frequency = <204000000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-300000000 { +- clock-frequency = <300000000>; +- nvidia,parent-clock-frequency = <600000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_C>; +- clock-names = "emc-parent"; +- }; +- timing-396000000 { +- clock-frequency = <396000000>; +- nvidia,parent-clock-frequency = <792000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_M>; +- clock-names = "emc-parent"; +- }; +- timing-528000000 { +- clock-frequency = <528000000>; +- nvidia,parent-clock-frequency = <528000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; +- clock-names = "emc-parent"; +- }; +- timing-600000000 { +- clock-frequency = <600000000>; +- nvidia,parent-clock-frequency = <600000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; +- clock-names = "emc-parent"; +- }; +- timing-792000000 { +- clock-frequency = <792000000>; +- nvidia,parent-clock-frequency = <792000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; +- clock-names = "emc-parent"; +- }; +- }; +- }; +- +- external-memory-controller@7001b000 { +- emc-timings-1 { +- nvidia,ram-code = <1>; +- +- timing-12750000 { +- clock-frequency = <12750000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000c000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000000 /* EMC_RC */ +- 0x00000003 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000000 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000004 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000003 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000003 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000006 /* EMC_WDV */ +- 0x00000006 /* EMC_WDV_MASK */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000005 /* EMC_EINPUT */ +- 0x00000005 /* EMC_EINPUT_DURATION */ +- 0x00010000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000c /* EMC_QSAFE */ +- 0x0000000d /* EMC_RDV */ +- 0x0000000f /* EMC_RDV_MASK */ +- 0x00000060 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000005 /* EMC_TXSR */ +- 0x00000005 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000000 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000064 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x106aa298 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00064000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000303 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000007 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000042 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x0000f2f3 /* EMC_CFG_PIPE */ +- 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000a /* EMC_QPOP */ +- >; +- }; +- +- timing-20400000 { +- clock-frequency = <20400000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000c000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000000 /* EMC_RC */ +- 0x00000005 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000000 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000004 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000003 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000003 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000006 /* EMC_WDV */ +- 0x00000006 /* EMC_WDV_MASK */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000005 /* EMC_EINPUT */ +- 0x00000005 /* EMC_EINPUT_DURATION */ +- 0x00010000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000c /* EMC_QSAFE */ +- 0x0000000d /* EMC_RDV */ +- 0x0000000f /* EMC_RDV_MASK */ +- 0x0000009a /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000006 /* EMC_TXSR */ +- 0x00000006 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000000 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x000000a0 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x106aa298 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00064000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000303 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x0000000b /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000042 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x0000f2f3 /* EMC_CFG_PIPE */ +- 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000a /* EMC_QPOP */ +- >; +- }; +- +- timing-40800000 { +- clock-frequency = <40800000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000c000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000001 /* EMC_RC */ +- 0x0000000a /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000001 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000004 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000003 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000003 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000006 /* EMC_WDV */ +- 0x00000006 /* EMC_WDV_MASK */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000005 /* EMC_EINPUT */ +- 0x00000005 /* EMC_EINPUT_DURATION */ +- 0x00010000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000c /* EMC_QSAFE */ +- 0x0000000d /* EMC_RDV */ +- 0x0000000f /* EMC_RDV_MASK */ +- 0x00000134 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000008 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x0000000c /* EMC_TXSR */ +- 0x0000000c /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000000 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x0000013f /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x106aa298 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00064000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000303 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000015 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000042 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x0000f2f3 /* EMC_CFG_PIPE */ +- 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000a /* EMC_QPOP */ +- >; +- }; +- +- timing-68000000 { +- clock-frequency = <68000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000c000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000003 /* EMC_RC */ +- 0x00000011 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000002 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000004 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000003 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000003 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000006 /* EMC_WDV */ +- 0x00000006 /* EMC_WDV_MASK */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000005 /* EMC_EINPUT */ +- 0x00000005 /* EMC_EINPUT_DURATION */ +- 0x00010000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000c /* EMC_QSAFE */ +- 0x0000000d /* EMC_RDV */ +- 0x0000000f /* EMC_RDV_MASK */ +- 0x00000202 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x0000000f /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000013 /* EMC_TXSR */ +- 0x00000013 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000001 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000213 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x106aa298 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00064000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000303 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000022 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000042 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x0000f2f3 /* EMC_CFG_PIPE */ +- 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000a /* EMC_QPOP */ +- >; +- }; +- +- timing-102000000 { +- clock-frequency = <102000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000c000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000004 /* EMC_RC */ +- 0x0000001a /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000003 /* EMC_RAS */ +- 0x00000001 /* EMC_RP */ +- 0x00000004 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000003 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000001 /* EMC_RD_RCD */ +- 0x00000001 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000003 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000006 /* EMC_WDV */ +- 0x00000006 /* EMC_WDV_MASK */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000005 /* EMC_EINPUT */ +- 0x00000005 /* EMC_EINPUT_DURATION */ +- 0x00010000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000c /* EMC_QSAFE */ +- 0x0000000d /* EMC_RDV */ +- 0x0000000f /* EMC_RDV_MASK */ +- 0x00000304 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000018 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x0000001c /* EMC_TXSR */ +- 0x0000001c /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000003 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x0000031c /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x106aa298 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00064000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000303 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000033 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000042 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x0000f2f3 /* EMC_CFG_PIPE */ +- 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000a /* EMC_QPOP */ +- >; +- }; +- +- timing-204000000 { +- clock-frequency = <204000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x0000088d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000c000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000009 /* EMC_RC */ +- 0x00000035 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000007 /* EMC_RAS */ +- 0x00000002 /* EMC_RP */ +- 0x00000005 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000003 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000002 /* EMC_RD_RCD */ +- 0x00000002 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000003 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_WDV_MASK */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000004 /* EMC_EINPUT */ +- 0x00000006 /* EMC_EINPUT_DURATION */ +- 0x00010000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000003 /* EMC_QRST */ +- 0x0000000d /* EMC_QSAFE */ +- 0x0000000f /* EMC_RDV */ +- 0x00000011 /* EMC_RDV_MASK */ +- 0x00000607 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000032 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000038 /* EMC_TXSR */ +- 0x00000038 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000007 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000638 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x106aa298 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00064000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x00090000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00090000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00094000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00094000 /* EMC_DLL_XFORM_DQ3 */ +- 0x00009400 /* EMC_DLL_XFORM_DQ4 */ +- 0x00009000 /* EMC_DLL_XFORM_DQ5 */ +- 0x00009000 /* EMC_DLL_XFORM_DQ6 */ +- 0x00009000 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000303 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000066 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x0000d2b3 /* EMC_CFG_PIPE */ +- 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000a /* EMC_QPOP */ +- >; +- }; +- +- timing-300000000 { +- clock-frequency = <300000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73340000>; +- nvidia,emc-cfg-2 = <0x000008d5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200000>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000321>; +- nvidia,emc-mrs-wait-cnt = <0x0174000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x01231339>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x0000000d /* EMC_RC */ +- 0x0000004c /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000009 /* EMC_RAS */ +- 0x00000003 /* EMC_RP */ +- 0x00000004 /* EMC_R2W */ +- 0x00000008 /* EMC_W2R */ +- 0x00000002 /* EMC_R2P */ +- 0x00000009 /* EMC_W2P */ +- 0x00000003 /* EMC_RD_RCD */ +- 0x00000003 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000002 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000003 /* EMC_WDV */ +- 0x00000003 /* EMC_WDV_MASK */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000002 /* EMC_EINPUT */ +- 0x00000007 /* EMC_EINPUT_DURATION */ +- 0x00020000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000001 /* EMC_QRST */ +- 0x0000000e /* EMC_QSAFE */ +- 0x00000010 /* EMC_RDV */ +- 0x00000012 /* EMC_RDV_MASK */ +- 0x000008e4 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000001 /* EMC_PDEX2WR */ +- 0x00000008 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x0000004a /* EMC_AR2PDEN */ +- 0x0000000e /* EMC_RW2PDEN */ +- 0x00000051 /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000009 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000924 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x104ab098 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00030000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x00060000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00060000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00060000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00060000 /* EMC_DLL_XFORM_DQ3 */ +- 0x00006000 /* EMC_DLL_XFORM_DQ4 */ +- 0x00006000 /* EMC_DLL_XFORM_DQ5 */ +- 0x00006000 /* EMC_DLL_XFORM_DQ6 */ +- 0x00006000 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000101 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451420 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000096 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x0174000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x000052a3 /* EMC_CFG_PIPE */ +- 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x00000009 /* EMC_QPOP */ +- >; +- }; +- +- timing-396000000 { +- clock-frequency = <396000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73340000>; +- nvidia,emc-cfg-2 = <0x00000895>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200000>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000521>; +- nvidia,emc-mrs-wait-cnt = <0x015b000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x01231339>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000012 /* EMC_RC */ +- 0x00000065 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x0000000c /* EMC_RAS */ +- 0x00000004 /* EMC_RP */ +- 0x00000005 /* EMC_R2W */ +- 0x00000008 /* EMC_W2R */ +- 0x00000002 /* EMC_R2P */ +- 0x0000000a /* EMC_W2P */ +- 0x00000004 /* EMC_RD_RCD */ +- 0x00000004 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000002 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000003 /* EMC_WDV */ +- 0x00000003 /* EMC_WDV_MASK */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000001 /* EMC_EINPUT */ +- 0x00000008 /* EMC_EINPUT_DURATION */ +- 0x00020000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000000 /* EMC_QRST */ +- 0x0000000f /* EMC_QSAFE */ +- 0x00000010 /* EMC_RDV */ +- 0x00000012 /* EMC_RDV_MASK */ +- 0x00000bd1 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000001 /* EMC_PDEX2WR */ +- 0x00000008 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000063 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x0000006b /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x0000000d /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000c11 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x104ab098 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00030000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ3 */ +- 0x00004800 /* EMC_DLL_XFORM_DQ4 */ +- 0x00004800 /* EMC_DLL_XFORM_DQ5 */ +- 0x00004800 /* EMC_DLL_XFORM_DQ6 */ +- 0x00004800 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000101 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451420 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x000000c6 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x015b000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x000052a3 /* EMC_CFG_PIPE */ +- 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ +- 0x00000009 /* EMC_QPOP */ +- >; +- }; +- +- timing-528000000 { +- clock-frequency = <528000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73300000>; +- nvidia,emc-cfg-2 = <0x0000089d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000941>; +- nvidia,emc-mrs-wait-cnt = <0x013a000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000018 /* EMC_RC */ +- 0x00000088 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000011 /* EMC_RAS */ +- 0x00000006 /* EMC_RP */ +- 0x00000006 /* EMC_R2W */ +- 0x00000009 /* EMC_W2R */ +- 0x00000002 /* EMC_R2P */ +- 0x0000000d /* EMC_W2P */ +- 0x00000006 /* EMC_RD_RCD */ +- 0x00000006 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000002 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000003 /* EMC_WDV */ +- 0x00000003 /* EMC_WDV_MASK */ +- 0x00000007 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000002 /* EMC_EINPUT */ +- 0x00000009 /* EMC_EINPUT_DURATION */ +- 0x00040000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000001 /* EMC_QRST */ +- 0x00000010 /* EMC_QSAFE */ +- 0x00000013 /* EMC_RDV */ +- 0x00000015 /* EMC_RDV_MASK */ +- 0x00000fd6 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x0000000b /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000084 /* EMC_AR2PDEN */ +- 0x00000012 /* EMC_RW2PDEN */ +- 0x0000008f /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000013 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000006 /* EMC_TCLKSTABLE */ +- 0x00000006 /* EMC_TCLKSTOP */ +- 0x00001017 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x104ab098 /* EMC_FBIO_CFG5 */ +- 0xe01200b1 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x0000000a /* EMC_DLL_XFORM_DQS0 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS1 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS2 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS3 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS4 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS5 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS6 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS7 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS8 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS9 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS10 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS11 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS12 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS13 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS14 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ0 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ1 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ2 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ3 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ4 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ5 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ6 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ7 */ +- 0x100002a0 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc085 /* EMC_XM2CLKPADCTRL */ +- 0x00000101 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451420 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0606003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000000 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x013a000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x000042a0 /* EMC_CFG_PIPE */ +- 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000b /* EMC_QPOP */ +- >; +- }; +- +- timing-600000000 { +- clock-frequency = <600000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73300000>; +- nvidia,emc-cfg-2 = <0x0000089d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200010>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000b61>; +- nvidia,emc-mrs-wait-cnt = <0x0128000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x0000001c /* EMC_RC */ +- 0x0000009a /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000013 /* EMC_RAS */ +- 0x00000007 /* EMC_RP */ +- 0x00000007 /* EMC_R2W */ +- 0x0000000b /* EMC_W2R */ +- 0x00000003 /* EMC_R2P */ +- 0x00000010 /* EMC_W2P */ +- 0x00000007 /* EMC_RD_RCD */ +- 0x00000007 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000002 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_WDV_MASK */ +- 0x0000000a /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000003 /* EMC_EINPUT */ +- 0x0000000b /* EMC_EINPUT_DURATION */ +- 0x00070000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000002 /* EMC_QRST */ +- 0x00000012 /* EMC_QSAFE */ +- 0x00000016 /* EMC_RDV */ +- 0x00000018 /* EMC_RDV_MASK */ +- 0x00001208 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x0000000d /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000096 /* EMC_AR2PDEN */ +- 0x00000015 /* EMC_RW2PDEN */ +- 0x000000a2 /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000015 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000006 /* EMC_TCLKSTABLE */ +- 0x00000006 /* EMC_TCLKSTOP */ +- 0x00001249 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x104ab098 /* EMC_FBIO_CFG5 */ +- 0xe00e00b1 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x0000000a /* EMC_DLL_XFORM_DQS0 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS1 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS2 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS3 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS4 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS5 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS6 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS7 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS8 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS9 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS10 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS11 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS12 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS13 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS14 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ0 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ1 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ2 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ3 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ4 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ5 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ6 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ7 */ +- 0x100002a0 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc085 /* EMC_XM2CLKPADCTRL */ +- 0x00000101 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451420 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0606003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000000 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x0128000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x000040a0 /* EMC_CFG_PIPE */ +- 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000e /* EMC_QPOP */ +- >; +- }; +- +- timing-792000000 { +- clock-frequency = <792000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73300000>; +- nvidia,emc-cfg-2 = <0x0080089d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200418>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000d71>; +- nvidia,emc-mrs-wait-cnt = <0x00f8000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040000>; +- nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000025 /* EMC_RC */ +- 0x000000cc /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x0000001a /* EMC_RAS */ +- 0x00000009 /* EMC_RP */ +- 0x00000008 /* EMC_R2W */ +- 0x0000000d /* EMC_W2R */ +- 0x00000004 /* EMC_R2P */ +- 0x00000013 /* EMC_W2P */ +- 0x00000009 /* EMC_RD_RCD */ +- 0x00000009 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000002 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000006 /* EMC_WDV */ +- 0x00000006 /* EMC_WDV_MASK */ +- 0x0000000b /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000002 /* EMC_EINPUT */ +- 0x0000000d /* EMC_EINPUT_DURATION */ +- 0x00080000 /* EMC_PUTERM_EXTRA */ +- 0x00000004 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000001 /* EMC_QRST */ +- 0x00000014 /* EMC_QSAFE */ +- 0x00000018 /* EMC_RDV */ +- 0x0000001a /* EMC_RDV_MASK */ +- 0x000017e2 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000003 /* EMC_PDEX2WR */ +- 0x00000011 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x000000c6 /* EMC_AR2PDEN */ +- 0x00000018 /* EMC_RW2PDEN */ +- 0x000000d6 /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000005 /* EMC_TCKE */ +- 0x00000006 /* EMC_TCKESR */ +- 0x00000005 /* EMC_TPD */ +- 0x0000001d /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000008 /* EMC_TCLKSTABLE */ +- 0x00000008 /* EMC_TCLKSTOP */ +- 0x00001822 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x80000005 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x104ab198 /* EMC_FBIO_CFG5 */ +- 0xe00700b1 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00000005 /* EMC_DLL_XFORM_DQS0 */ +- 0x00000005 /* EMC_DLL_XFORM_DQS1 */ +- 0x00000005 /* EMC_DLL_XFORM_DQS2 */ +- 0x00000005 /* EMC_DLL_XFORM_DQS3 */ +- 0x00000005 /* EMC_DLL_XFORM_DQS4 */ +- 0x00000005 /* EMC_DLL_XFORM_DQS5 */ +- 0x00000005 /* EMC_DLL_XFORM_DQS6 */ +- 0x00000005 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000005 /* EMC_DLL_XFORM_DQS8 */ +- 0x00000005 /* EMC_DLL_XFORM_DQS9 */ +- 0x00000005 /* EMC_DLL_XFORM_DQS10 */ +- 0x00000005 /* EMC_DLL_XFORM_DQS11 */ +- 0x00000005 /* EMC_DLL_XFORM_DQS12 */ +- 0x00000005 /* EMC_DLL_XFORM_DQS13 */ +- 0x00000005 /* EMC_DLL_XFORM_DQS14 */ +- 0x00000005 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00034000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00034000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00034000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00034000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ0 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ1 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ2 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ3 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ4 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ5 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ6 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ7 */ +- 0x100002a0 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc085 /* EMC_XM2CLKPADCTRL */ +- 0x00000101 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x61861820 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x61861800 /* EMC_XM2DQSPADCTRL6 */ +- 0x0606003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000000 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x00f8000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000007 /* EMC_CTT */ +- 0x00000004 /* EMC_CTT_DURATION */ +- 0x00004080 /* EMC_CFG_PIPE */ +- 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000f /* EMC_QPOP */ +- >; +- }; +- }; +- +- emc-timings-4 { +- nvidia,ram-code = <4>; +- +- timing-12750000 { +- clock-frequency = <12750000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x00100003>; +- nvidia,emc-mode-2 = <0x00200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x00001221>; +- nvidia,emc-mrs-wait-cnt = <0x000e000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000000 /* EMC_RC */ +- 0x00000004 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000000 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000004 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000003 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000006 /* EMC_WDV */ +- 0x00000006 /* EMC_WDV_MASK */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000005 /* EMC_EINPUT */ +- 0x00000005 /* EMC_EINPUT_DURATION */ +- 0x00010000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000c /* EMC_QSAFE */ +- 0x0000000d /* EMC_RDV */ +- 0x0000000f /* EMC_RDV_MASK */ +- 0x00000060 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000005 /* EMC_TXSR */ +- 0x00000005 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000000 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000064 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x106aa298 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00064000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ3 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ4 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ5 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ6 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000303 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000007 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000042 /* EMC_ZCAL_WAIT_CNT */ +- 0x000e000e /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x0000f2f3 /* EMC_CFG_PIPE */ +- 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000a /* EMC_QPOP */ +- >; +- }; +- +- timing-20400000 { +- clock-frequency = <20400000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x00100003>; +- nvidia,emc-mode-2 = <0x00200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x00001221>; +- nvidia,emc-mrs-wait-cnt = <0x000e000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000000 /* EMC_RC */ +- 0x00000007 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000000 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000004 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000003 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000006 /* EMC_WDV */ +- 0x00000006 /* EMC_WDV_MASK */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000005 /* EMC_EINPUT */ +- 0x00000005 /* EMC_EINPUT_DURATION */ +- 0x00010000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000c /* EMC_QSAFE */ +- 0x0000000d /* EMC_RDV */ +- 0x0000000f /* EMC_RDV_MASK */ +- 0x0000009a /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000008 /* EMC_TXSR */ +- 0x00000008 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000000 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x000000a0 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x106aa298 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00064000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ3 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ4 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ5 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ6 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000303 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x0000000b /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000042 /* EMC_ZCAL_WAIT_CNT */ +- 0x000e000e /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x0000f2f3 /* EMC_CFG_PIPE */ +- 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000a /* EMC_QPOP */ +- >; +- }; +- +- timing-40800000 { +- clock-frequency = <40800000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x00100003>; +- nvidia,emc-mode-2 = <0x00200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x00001221>; +- nvidia,emc-mrs-wait-cnt = <0x000e000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000001 /* EMC_RC */ +- 0x0000000e /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000001 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000004 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000003 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000006 /* EMC_WDV */ +- 0x00000006 /* EMC_WDV_MASK */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000005 /* EMC_EINPUT */ +- 0x00000005 /* EMC_EINPUT_DURATION */ +- 0x00010000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000c /* EMC_QSAFE */ +- 0x0000000d /* EMC_RDV */ +- 0x0000000f /* EMC_RDV_MASK */ +- 0x00000134 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x0000000c /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x0000000f /* EMC_TXSR */ +- 0x0000000f /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000000 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x0000013f /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x106aa298 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00064000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ3 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ4 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ5 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ6 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000303 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000015 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000042 /* EMC_ZCAL_WAIT_CNT */ +- 0x000e000e /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x0000f2f3 /* EMC_CFG_PIPE */ +- 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000a /* EMC_QPOP */ +- >; +- }; +- +- timing-68000000 { +- clock-frequency = <68000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x00100003>; +- nvidia,emc-mode-2 = <0x00200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x00001221>; +- nvidia,emc-mrs-wait-cnt = <0x000e000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000003 /* EMC_RC */ +- 0x00000017 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000002 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000004 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000003 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000006 /* EMC_WDV */ +- 0x00000006 /* EMC_WDV_MASK */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000005 /* EMC_EINPUT */ +- 0x00000005 /* EMC_EINPUT_DURATION */ +- 0x00010000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000c /* EMC_QSAFE */ +- 0x0000000d /* EMC_RDV */ +- 0x0000000f /* EMC_RDV_MASK */ +- 0x00000202 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000015 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000019 /* EMC_TXSR */ +- 0x00000019 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000001 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000213 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x106aa298 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00064000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ3 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ4 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ5 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ6 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000303 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000022 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000042 /* EMC_ZCAL_WAIT_CNT */ +- 0x000e000e /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x0000f2f3 /* EMC_CFG_PIPE */ +- 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000a /* EMC_QPOP */ +- >; +- }; +- +- timing-102000000 { +- clock-frequency = <102000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x00100003>; +- nvidia,emc-mode-2 = <0x00200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x00001221>; +- nvidia,emc-mrs-wait-cnt = <0x000e000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000004 /* EMC_RC */ +- 0x00000023 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000003 /* EMC_RAS */ +- 0x00000001 /* EMC_RP */ +- 0x00000004 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000001 /* EMC_RD_RCD */ +- 0x00000001 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000003 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000006 /* EMC_WDV */ +- 0x00000006 /* EMC_WDV_MASK */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000005 /* EMC_EINPUT */ +- 0x00000005 /* EMC_EINPUT_DURATION */ +- 0x00010000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000c /* EMC_QSAFE */ +- 0x0000000d /* EMC_RDV */ +- 0x0000000f /* EMC_RDV_MASK */ +- 0x00000304 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000021 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000025 /* EMC_TXSR */ +- 0x00000025 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000003 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x0000031c /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x106aa298 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00064000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ3 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ4 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ5 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ6 */ +- 0x00008000 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000303 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000033 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000042 /* EMC_ZCAL_WAIT_CNT */ +- 0x000e000e /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x0000f2f3 /* EMC_CFG_PIPE */ +- 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000a /* EMC_QPOP */ +- >; +- }; +- +- timing-204000000 { +- clock-frequency = <204000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x0000088d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x00100003>; +- nvidia,emc-mode-2 = <0x00200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x00001221>; +- nvidia,emc-mrs-wait-cnt = <0x000e000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000009 /* EMC_RC */ +- 0x00000047 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000006 /* EMC_RAS */ +- 0x00000002 /* EMC_RP */ +- 0x00000005 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000002 /* EMC_RD_RCD */ +- 0x00000002 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000003 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_WDV_MASK */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000004 /* EMC_EINPUT */ +- 0x00000006 /* EMC_EINPUT_DURATION */ +- 0x00010000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000003 /* EMC_QRST */ +- 0x0000000d /* EMC_QSAFE */ +- 0x0000000f /* EMC_RDV */ +- 0x00000011 /* EMC_RDV_MASK */ +- 0x00000607 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000044 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x0000004a /* EMC_TXSR */ +- 0x0000004a /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000007 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000638 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x106aa298 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00064000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x00090000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00090000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00094000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00094000 /* EMC_DLL_XFORM_DQ3 */ +- 0x00009400 /* EMC_DLL_XFORM_DQ4 */ +- 0x00009000 /* EMC_DLL_XFORM_DQ5 */ +- 0x00009000 /* EMC_DLL_XFORM_DQ6 */ +- 0x00009000 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000303 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000066 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x000e000e /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x0000d2b3 /* EMC_CFG_PIPE */ +- 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000a /* EMC_QPOP */ +- >; +- }; +- +- timing-300000000 { +- clock-frequency = <300000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73340000>; +- nvidia,emc-cfg-2 = <0x000008d5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x00100002>; +- nvidia,emc-mode-2 = <0x00200000>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x00000321>; +- nvidia,emc-mrs-wait-cnt = <0x0117000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x01231339>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x0000000d /* EMC_RC */ +- 0x00000067 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000009 /* EMC_RAS */ +- 0x00000003 /* EMC_RP */ +- 0x00000004 /* EMC_R2W */ +- 0x00000008 /* EMC_W2R */ +- 0x00000002 /* EMC_R2P */ +- 0x00000009 /* EMC_W2P */ +- 0x00000003 /* EMC_RD_RCD */ +- 0x00000003 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000002 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000003 /* EMC_WDV */ +- 0x00000003 /* EMC_WDV_MASK */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000002 /* EMC_EINPUT */ +- 0x00000007 /* EMC_EINPUT_DURATION */ +- 0x00020000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000001 /* EMC_QRST */ +- 0x0000000e /* EMC_QSAFE */ +- 0x00000010 /* EMC_RDV */ +- 0x00000012 /* EMC_RDV_MASK */ +- 0x000008e4 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000001 /* EMC_PDEX2WR */ +- 0x00000008 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000065 /* EMC_AR2PDEN */ +- 0x0000000e /* EMC_RW2PDEN */ +- 0x0000006c /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000009 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000924 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x104ab098 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00030000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x00060000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00060000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00060000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00060000 /* EMC_DLL_XFORM_DQ3 */ +- 0x00006000 /* EMC_DLL_XFORM_DQ4 */ +- 0x00006000 /* EMC_DLL_XFORM_DQ5 */ +- 0x00006000 /* EMC_DLL_XFORM_DQ6 */ +- 0x00006000 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000101 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451420 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000096 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x0117000e /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x000052a3 /* EMC_CFG_PIPE */ +- 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x00000009 /* EMC_QPOP */ +- >; +- }; +- +- timing-396000000 { +- clock-frequency = <396000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73340000>; +- nvidia,emc-cfg-2 = <0x00000895>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x00100002>; +- nvidia,emc-mode-2 = <0x00200000>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x00000521>; +- nvidia,emc-mrs-wait-cnt = <0x00f5000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x01231339>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000011 /* EMC_RC */ +- 0x00000089 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x0000000c /* EMC_RAS */ +- 0x00000004 /* EMC_RP */ +- 0x00000005 /* EMC_R2W */ +- 0x00000008 /* EMC_W2R */ +- 0x00000002 /* EMC_R2P */ +- 0x0000000a /* EMC_W2P */ +- 0x00000004 /* EMC_RD_RCD */ +- 0x00000004 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000002 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000003 /* EMC_WDV */ +- 0x00000003 /* EMC_WDV_MASK */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000001 /* EMC_EINPUT */ +- 0x00000008 /* EMC_EINPUT_DURATION */ +- 0x00020000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000000 /* EMC_QRST */ +- 0x0000000f /* EMC_QSAFE */ +- 0x00000010 /* EMC_RDV */ +- 0x00000012 /* EMC_RDV_MASK */ +- 0x00000bd1 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000001 /* EMC_PDEX2WR */ +- 0x00000008 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000087 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x0000008f /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x0000000d /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000c11 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x104ab098 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00030000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ3 */ +- 0x00004800 /* EMC_DLL_XFORM_DQ4 */ +- 0x00004800 /* EMC_DLL_XFORM_DQ5 */ +- 0x00004800 /* EMC_DLL_XFORM_DQ6 */ +- 0x00004800 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000101 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451420 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x000000c6 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x00f5000e /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x000052a3 /* EMC_CFG_PIPE */ +- 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ +- 0x00000009 /* EMC_QPOP */ +- >; +- }; +- +- timing-528000000 { +- clock-frequency = <528000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73300000>; +- nvidia,emc-cfg-2 = <0x0000089d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x00100002>; +- nvidia,emc-mode-2 = <0x00200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x00000941>; +- nvidia,emc-mrs-wait-cnt = <0x00c8000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000018 /* EMC_RC */ +- 0x000000b7 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000010 /* EMC_RAS */ +- 0x00000006 /* EMC_RP */ +- 0x00000006 /* EMC_R2W */ +- 0x00000009 /* EMC_W2R */ +- 0x00000002 /* EMC_R2P */ +- 0x0000000d /* EMC_W2P */ +- 0x00000006 /* EMC_RD_RCD */ +- 0x00000006 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000002 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000003 /* EMC_WDV */ +- 0x00000003 /* EMC_WDV_MASK */ +- 0x00000007 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000002 /* EMC_EINPUT */ +- 0x00000009 /* EMC_EINPUT_DURATION */ +- 0x00040000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000001 /* EMC_QRST */ +- 0x00000010 /* EMC_QSAFE */ +- 0x00000013 /* EMC_RDV */ +- 0x00000015 /* EMC_RDV_MASK */ +- 0x00000fd6 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x0000000b /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x000000b4 /* EMC_AR2PDEN */ +- 0x00000012 /* EMC_RW2PDEN */ +- 0x000000bf /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000013 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000006 /* EMC_TCLKSTABLE */ +- 0x00000006 /* EMC_TCLKSTOP */ +- 0x00001017 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x104ab098 /* EMC_FBIO_CFG5 */ +- 0xe01200b1 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x0000000a /* EMC_DLL_XFORM_DQS0 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS1 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS2 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS3 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS4 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS5 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS6 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS7 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS8 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS9 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS10 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS11 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS12 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS13 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS14 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ0 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ1 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ2 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ3 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ4 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ5 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ6 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ7 */ +- 0x100002a0 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc085 /* EMC_XM2CLKPADCTRL */ +- 0x00000101 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451420 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0606003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000000 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x00c8000e /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x000042a0 /* EMC_CFG_PIPE */ +- 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000b /* EMC_QPOP */ +- >; +- }; +- +- timing-600000000 { +- clock-frequency = <600000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73300000>; +- nvidia,emc-cfg-2 = <0x0000089d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x00100002>; +- nvidia,emc-mode-2 = <0x00200010>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x00000b61>; +- nvidia,emc-mrs-wait-cnt = <0x00b0000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x0000001b /* EMC_RC */ +- 0x000000d0 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000013 /* EMC_RAS */ +- 0x00000007 /* EMC_RP */ +- 0x00000007 /* EMC_R2W */ +- 0x0000000b /* EMC_W2R */ +- 0x00000003 /* EMC_R2P */ +- 0x00000010 /* EMC_W2P */ +- 0x00000007 /* EMC_RD_RCD */ +- 0x00000007 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000002 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_WDV_MASK */ +- 0x0000000a /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000003 /* EMC_EINPUT */ +- 0x0000000b /* EMC_EINPUT_DURATION */ +- 0x00070000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000002 /* EMC_QRST */ +- 0x00000012 /* EMC_QSAFE */ +- 0x00000016 /* EMC_RDV */ +- 0x00000018 /* EMC_RDV_MASK */ +- 0x00001208 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x0000000d /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x000000cc /* EMC_AR2PDEN */ +- 0x00000015 /* EMC_RW2PDEN */ +- 0x000000d8 /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000015 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000006 /* EMC_TCLKSTABLE */ +- 0x00000006 /* EMC_TCLKSTOP */ +- 0x00001249 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x104ab098 /* EMC_FBIO_CFG5 */ +- 0xe00e00b1 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x0000000a /* EMC_DLL_XFORM_DQS0 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS1 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS2 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS3 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS4 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS5 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS6 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS7 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS8 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS9 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS10 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS11 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS12 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS13 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS14 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ0 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ1 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ2 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ3 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ4 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ5 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ6 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ7 */ +- 0x100002a0 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc085 /* EMC_XM2CLKPADCTRL */ +- 0x00000101 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451420 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0606003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000000 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x00b0000e /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x000040a0 /* EMC_CFG_PIPE */ +- 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000e /* EMC_QPOP */ +- >; +- }; +- +- timing-792000000 { +- clock-frequency = <792000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73300000>; +- nvidia,emc-cfg-2 = <0x0080089d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x00100002>; +- nvidia,emc-mode-2 = <0x00200418>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x00000d71>; +- nvidia,emc-mrs-wait-cnt = <0x006f000e>; +- nvidia,emc-sel-dpd-ctrl = <0x00040000>; +- nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000024 /* EMC_RC */ +- 0x00000114 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000019 /* EMC_RAS */ +- 0x0000000a /* EMC_RP */ +- 0x00000008 /* EMC_R2W */ +- 0x0000000d /* EMC_W2R */ +- 0x00000004 /* EMC_R2P */ +- 0x00000013 /* EMC_W2P */ +- 0x0000000a /* EMC_RD_RCD */ +- 0x0000000a /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000002 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000006 /* EMC_WDV */ +- 0x00000006 /* EMC_WDV_MASK */ +- 0x0000000b /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000002 /* EMC_EINPUT */ +- 0x0000000d /* EMC_EINPUT_DURATION */ +- 0x00080000 /* EMC_PUTERM_EXTRA */ +- 0x00000004 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000001 /* EMC_QRST */ +- 0x00000014 /* EMC_QSAFE */ +- 0x00000018 /* EMC_RDV */ +- 0x0000001a /* EMC_RDV_MASK */ +- 0x000017e2 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000003 /* EMC_PDEX2WR */ +- 0x00000011 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x0000010d /* EMC_AR2PDEN */ +- 0x00000018 /* EMC_RW2PDEN */ +- 0x0000011e /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000005 /* EMC_TCKE */ +- 0x00000006 /* EMC_TCKESR */ +- 0x00000005 /* EMC_TPD */ +- 0x0000001d /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000008 /* EMC_TCLKSTABLE */ +- 0x00000008 /* EMC_TCLKSTOP */ +- 0x00001822 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x80000005 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x104ab198 /* EMC_FBIO_CFG5 */ +- 0xe00700b1 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x007fc007 /* EMC_DLL_XFORM_DQS0 */ +- 0x007fc008 /* EMC_DLL_XFORM_DQS1 */ +- 0x007f400c /* EMC_DLL_XFORM_DQS2 */ +- 0x007fc007 /* EMC_DLL_XFORM_DQS3 */ +- 0x007f4006 /* EMC_DLL_XFORM_DQS4 */ +- 0x007f8004 /* EMC_DLL_XFORM_DQS5 */ +- 0x007f8005 /* EMC_DLL_XFORM_DQS6 */ +- 0x007f8004 /* EMC_DLL_XFORM_DQS7 */ +- 0x007fc007 /* EMC_DLL_XFORM_DQS8 */ +- 0x007fc008 /* EMC_DLL_XFORM_DQS9 */ +- 0x007f400c /* EMC_DLL_XFORM_DQS10 */ +- 0x007fc007 /* EMC_DLL_XFORM_DQS11 */ +- 0x007f4006 /* EMC_DLL_XFORM_DQS12 */ +- 0x007f8004 /* EMC_DLL_XFORM_DQS13 */ +- 0x007f8005 /* EMC_DLL_XFORM_DQS14 */ +- 0x007f8004 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00034000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00034000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00034000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00034000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000006 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000006 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ0 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ1 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ2 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ3 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ4 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ5 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ6 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ7 */ +- 0x100002a0 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc085 /* EMC_XM2CLKPADCTRL */ +- 0x00000101 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x61861820 /* EMC_XM2DQSPADCTRL3 */ +- 0x00492492 /* EMC_XM2DQSPADCTRL4 */ +- 0x00492492 /* EMC_XM2DQSPADCTRL5 */ +- 0x61861800 /* EMC_XM2DQSPADCTRL6 */ +- 0x0606003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000000 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x006f000e /* EMC_MRS_WAIT_CNT2 */ +- 0x00000007 /* EMC_CTT */ +- 0x00000004 /* EMC_CTT_DURATION */ +- 0x00004080 /* EMC_CFG_PIPE */ +- 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000f /* EMC_QPOP */ +- >; +- }; +- }; +- +- emc-timings-6 { +- nvidia,ram-code = <6>; +- +- timing-12750000 { +- clock-frequency = <12750000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000c000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000000 /* EMC_RC */ +- 0x00000003 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000000 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000004 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000003 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000003 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000006 /* EMC_WDV */ +- 0x00000006 /* EMC_WDV_MASK */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000005 /* EMC_EINPUT */ +- 0x00000005 /* EMC_EINPUT_DURATION */ +- 0x00010000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000c /* EMC_QSAFE */ +- 0x0000000d /* EMC_RDV */ +- 0x0000000f /* EMC_RDV_MASK */ +- 0x00000060 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000005 /* EMC_TXSR */ +- 0x00000005 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000000 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000064 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x106aa298 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00064000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000303 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000007 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000042 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x0000f2f3 /* EMC_CFG_PIPE */ +- 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000a /* EMC_QPOP */ +- >; +- }; +- +- timing-20400000 { +- clock-frequency = <20400000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000c000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000000 /* EMC_RC */ +- 0x00000005 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000000 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000004 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000003 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000003 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000006 /* EMC_WDV */ +- 0x00000006 /* EMC_WDV_MASK */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000005 /* EMC_EINPUT */ +- 0x00000005 /* EMC_EINPUT_DURATION */ +- 0x00010000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000c /* EMC_QSAFE */ +- 0x0000000d /* EMC_RDV */ +- 0x0000000f /* EMC_RDV_MASK */ +- 0x0000009a /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000006 /* EMC_TXSR */ +- 0x00000006 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000000 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x000000a0 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x106aa298 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00064000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000303 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x0000000b /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000042 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x0000f2f3 /* EMC_CFG_PIPE */ +- 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000a /* EMC_QPOP */ +- >; +- }; +- +- timing-40800000 { +- clock-frequency = <40800000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000c000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000001 /* EMC_RC */ +- 0x0000000a /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000001 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000004 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000003 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000003 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000006 /* EMC_WDV */ +- 0x00000006 /* EMC_WDV_MASK */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000005 /* EMC_EINPUT */ +- 0x00000005 /* EMC_EINPUT_DURATION */ +- 0x00010000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000c /* EMC_QSAFE */ +- 0x0000000d /* EMC_RDV */ +- 0x0000000f /* EMC_RDV_MASK */ +- 0x00000134 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000008 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x0000000c /* EMC_TXSR */ +- 0x0000000c /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000000 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x0000013f /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x106aa298 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00064000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000303 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000015 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000042 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x0000f2f3 /* EMC_CFG_PIPE */ +- 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000a /* EMC_QPOP */ +- >; +- }; +- +- timing-68000000 { +- clock-frequency = <68000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000c000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000003 /* EMC_RC */ +- 0x00000011 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000002 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000004 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000003 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000003 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000006 /* EMC_WDV */ +- 0x00000006 /* EMC_WDV_MASK */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000005 /* EMC_EINPUT */ +- 0x00000005 /* EMC_EINPUT_DURATION */ +- 0x00010000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000c /* EMC_QSAFE */ +- 0x0000000d /* EMC_RDV */ +- 0x0000000f /* EMC_RDV_MASK */ +- 0x00000202 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x0000000f /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000013 /* EMC_TXSR */ +- 0x00000013 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000001 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000213 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x106aa298 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00064000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000303 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000022 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000042 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x0000f2f3 /* EMC_CFG_PIPE */ +- 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000a /* EMC_QPOP */ +- >; +- }; +- +- timing-102000000 { +- clock-frequency = <102000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000c000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000004 /* EMC_RC */ +- 0x0000001a /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000003 /* EMC_RAS */ +- 0x00000001 /* EMC_RP */ +- 0x00000004 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000003 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000001 /* EMC_RD_RCD */ +- 0x00000001 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000003 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000006 /* EMC_WDV */ +- 0x00000006 /* EMC_WDV_MASK */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000005 /* EMC_EINPUT */ +- 0x00000005 /* EMC_EINPUT_DURATION */ +- 0x00010000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000c /* EMC_QSAFE */ +- 0x0000000d /* EMC_RDV */ +- 0x0000000f /* EMC_RDV_MASK */ +- 0x00000304 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000018 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x0000001c /* EMC_TXSR */ +- 0x0000001c /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000003 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x0000031c /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x106aa298 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00064000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ +- 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000303 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000033 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000042 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x0000f2f3 /* EMC_CFG_PIPE */ +- 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000a /* EMC_QPOP */ +- >; +- }; +- +- timing-204000000 { +- clock-frequency = <204000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x0000088d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000c000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000009 /* EMC_RC */ +- 0x00000035 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000007 /* EMC_RAS */ +- 0x00000002 /* EMC_RP */ +- 0x00000005 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000003 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000002 /* EMC_RD_RCD */ +- 0x00000002 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000003 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_WDV_MASK */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000004 /* EMC_EINPUT */ +- 0x00000006 /* EMC_EINPUT_DURATION */ +- 0x00010000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000003 /* EMC_QRST */ +- 0x0000000d /* EMC_QSAFE */ +- 0x0000000f /* EMC_RDV */ +- 0x00000011 /* EMC_RDV_MASK */ +- 0x00000607 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000032 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000038 /* EMC_TXSR */ +- 0x00000038 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000007 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000638 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x106aa298 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00064000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00064000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x00090000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00090000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00094000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00094000 /* EMC_DLL_XFORM_DQ3 */ +- 0x00009400 /* EMC_DLL_XFORM_DQ4 */ +- 0x00009000 /* EMC_DLL_XFORM_DQ5 */ +- 0x00009000 /* EMC_DLL_XFORM_DQ6 */ +- 0x00009000 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000303 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000066 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x0000d2b3 /* EMC_CFG_PIPE */ +- 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000a /* EMC_QPOP */ +- >; +- }; +- +- timing-300000000 { +- clock-frequency = <300000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73340000>; +- nvidia,emc-cfg-2 = <0x000008d5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200000>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000321>; +- nvidia,emc-mrs-wait-cnt = <0x0174000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x01231339>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x0000000d /* EMC_RC */ +- 0x0000004c /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000009 /* EMC_RAS */ +- 0x00000003 /* EMC_RP */ +- 0x00000004 /* EMC_R2W */ +- 0x00000008 /* EMC_W2R */ +- 0x00000002 /* EMC_R2P */ +- 0x00000009 /* EMC_W2P */ +- 0x00000003 /* EMC_RD_RCD */ +- 0x00000003 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000002 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000003 /* EMC_WDV */ +- 0x00000003 /* EMC_WDV_MASK */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000002 /* EMC_EINPUT */ +- 0x00000007 /* EMC_EINPUT_DURATION */ +- 0x00020000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000001 /* EMC_QRST */ +- 0x0000000e /* EMC_QSAFE */ +- 0x00000010 /* EMC_RDV */ +- 0x00000012 /* EMC_RDV_MASK */ +- 0x000008e4 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000001 /* EMC_PDEX2WR */ +- 0x00000008 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x0000004a /* EMC_AR2PDEN */ +- 0x0000000e /* EMC_RW2PDEN */ +- 0x00000051 /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000009 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000924 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x104ab098 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00030000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x00060000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00060000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00060000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00060000 /* EMC_DLL_XFORM_DQ3 */ +- 0x00006000 /* EMC_DLL_XFORM_DQ4 */ +- 0x00006000 /* EMC_DLL_XFORM_DQ5 */ +- 0x00006000 /* EMC_DLL_XFORM_DQ6 */ +- 0x00006000 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000101 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451420 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000096 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x0174000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x000052a3 /* EMC_CFG_PIPE */ +- 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x00000009 /* EMC_QPOP */ +- >; +- }; +- +- timing-396000000 { +- clock-frequency = <396000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73340000>; +- nvidia,emc-cfg-2 = <0x00000895>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200000>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000521>; +- nvidia,emc-mrs-wait-cnt = <0x015b000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x01231339>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000012 /* EMC_RC */ +- 0x00000065 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x0000000c /* EMC_RAS */ +- 0x00000004 /* EMC_RP */ +- 0x00000005 /* EMC_R2W */ +- 0x00000008 /* EMC_W2R */ +- 0x00000002 /* EMC_R2P */ +- 0x0000000a /* EMC_W2P */ +- 0x00000004 /* EMC_RD_RCD */ +- 0x00000004 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000002 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000003 /* EMC_WDV */ +- 0x00000003 /* EMC_WDV_MASK */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000001 /* EMC_EINPUT */ +- 0x00000008 /* EMC_EINPUT_DURATION */ +- 0x00020000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000000 /* EMC_QRST */ +- 0x0000000f /* EMC_QSAFE */ +- 0x00000010 /* EMC_RDV */ +- 0x00000012 /* EMC_RDV_MASK */ +- 0x00000bd1 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000001 /* EMC_PDEX2WR */ +- 0x00000008 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000063 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x0000006b /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x0000000d /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000005 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000c11 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x104ab098 /* EMC_FBIO_CFG5 */ +- 0x002c00a0 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00030000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS8 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS9 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS10 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS11 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS12 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS13 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS14 */ +- 0x00030000 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ3 */ +- 0x00004800 /* EMC_DLL_XFORM_DQ4 */ +- 0x00004800 /* EMC_DLL_XFORM_DQ5 */ +- 0x00004800 /* EMC_DLL_XFORM_DQ6 */ +- 0x00004800 /* EMC_DLL_XFORM_DQ7 */ +- 0x10000280 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc081 /* EMC_XM2CLKPADCTRL */ +- 0x00000101 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451420 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0000003f /* EMC_DSR_VTTGEN_DRV */ +- 0x000000c6 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x015b000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x000052a3 /* EMC_CFG_PIPE */ +- 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ +- 0x00000009 /* EMC_QPOP */ +- >; +- }; +- +- timing-528000000 { +- clock-frequency = <528000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73300000>; +- nvidia,emc-cfg-2 = <0x0000089d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000941>; +- nvidia,emc-mrs-wait-cnt = <0x013a000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000018 /* EMC_RC */ +- 0x00000088 /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000011 /* EMC_RAS */ +- 0x00000006 /* EMC_RP */ +- 0x00000006 /* EMC_R2W */ +- 0x00000009 /* EMC_W2R */ +- 0x00000002 /* EMC_R2P */ +- 0x0000000d /* EMC_W2P */ +- 0x00000006 /* EMC_RD_RCD */ +- 0x00000006 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000002 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000003 /* EMC_WDV */ +- 0x00000003 /* EMC_WDV_MASK */ +- 0x00000007 /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000002 /* EMC_EINPUT */ +- 0x00000009 /* EMC_EINPUT_DURATION */ +- 0x00040000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000001 /* EMC_QRST */ +- 0x00000010 /* EMC_QSAFE */ +- 0x00000013 /* EMC_RDV */ +- 0x00000015 /* EMC_RDV_MASK */ +- 0x00000fd6 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x0000000b /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000084 /* EMC_AR2PDEN */ +- 0x00000012 /* EMC_RW2PDEN */ +- 0x0000008f /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000013 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000006 /* EMC_TCLKSTABLE */ +- 0x00000006 /* EMC_TCLKSTOP */ +- 0x00001017 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x104ab098 /* EMC_FBIO_CFG5 */ +- 0xe01200b1 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x0000000a /* EMC_DLL_XFORM_DQS0 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS1 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS2 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS3 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS4 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS5 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS6 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS7 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS8 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS9 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS10 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS11 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS12 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS13 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS14 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ0 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ1 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ2 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ3 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ4 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ5 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ6 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ7 */ +- 0x100002a0 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc085 /* EMC_XM2CLKPADCTRL */ +- 0x00000101 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451420 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0606003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000000 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x013a000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x000042a0 /* EMC_CFG_PIPE */ +- 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000b /* EMC_QPOP */ +- >; +- }; +- +- timing-600000000 { +- clock-frequency = <600000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73300000>; +- nvidia,emc-cfg-2 = <0x0000089d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200010>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000b61>; +- nvidia,emc-mrs-wait-cnt = <0x0128000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x0000001c /* EMC_RC */ +- 0x0000009a /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x00000013 /* EMC_RAS */ +- 0x00000007 /* EMC_RP */ +- 0x00000007 /* EMC_R2W */ +- 0x0000000b /* EMC_W2R */ +- 0x00000003 /* EMC_R2P */ +- 0x00000010 /* EMC_W2P */ +- 0x00000007 /* EMC_RD_RCD */ +- 0x00000007 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000002 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_WDV_MASK */ +- 0x0000000a /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000003 /* EMC_EINPUT */ +- 0x0000000b /* EMC_EINPUT_DURATION */ +- 0x00070000 /* EMC_PUTERM_EXTRA */ +- 0x00000003 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000002 /* EMC_QRST */ +- 0x00000012 /* EMC_QSAFE */ +- 0x00000016 /* EMC_RDV */ +- 0x00000018 /* EMC_RDV_MASK */ +- 0x00001208 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x0000000d /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000096 /* EMC_AR2PDEN */ +- 0x00000015 /* EMC_RW2PDEN */ +- 0x000000a2 /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TCKESR */ +- 0x00000004 /* EMC_TPD */ +- 0x00000015 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000006 /* EMC_TCLKSTABLE */ +- 0x00000006 /* EMC_TCLKSTOP */ +- 0x00001249 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x104ab098 /* EMC_FBIO_CFG5 */ +- 0xe00e00b1 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x0000000a /* EMC_DLL_XFORM_DQS0 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS1 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS2 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS3 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS4 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS5 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS6 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS7 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS8 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS9 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS10 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS11 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS12 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS13 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS14 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ0 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ1 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ2 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ3 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ4 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ5 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ6 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ7 */ +- 0x100002a0 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc085 /* EMC_XM2CLKPADCTRL */ +- 0x00000101 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x51451420 /* EMC_XM2DQSPADCTRL3 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL4 */ +- 0x00514514 /* EMC_XM2DQSPADCTRL5 */ +- 0x51451400 /* EMC_XM2DQSPADCTRL6 */ +- 0x0606003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000000 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x0128000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000000 /* EMC_CTT */ +- 0x00000003 /* EMC_CTT_DURATION */ +- 0x000040a0 /* EMC_CFG_PIPE */ +- 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000e /* EMC_QPOP */ +- >; +- }; +- +- timing-792000000 { +- clock-frequency = <792000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73300000>; +- nvidia,emc-cfg-2 = <0x0080089d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200418>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000d71>; +- nvidia,emc-mrs-wait-cnt = <0x00f8000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040000>; +- nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000025 /* EMC_RC */ +- 0x000000cc /* EMC_RFC */ +- 0x00000000 /* EMC_RFC_SLR */ +- 0x0000001a /* EMC_RAS */ +- 0x00000009 /* EMC_RP */ +- 0x00000008 /* EMC_R2W */ +- 0x0000000d /* EMC_W2R */ +- 0x00000004 /* EMC_R2P */ +- 0x00000013 /* EMC_W2P */ +- 0x00000009 /* EMC_RD_RCD */ +- 0x00000009 /* EMC_WR_RCD */ +- 0x00000004 /* EMC_RRD */ +- 0x00000002 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000006 /* EMC_WDV */ +- 0x00000006 /* EMC_WDV_MASK */ +- 0x0000000b /* EMC_QUSE */ +- 0x00000002 /* EMC_QUSE_WIDTH */ +- 0x00000000 /* EMC_IBDLY */ +- 0x00000002 /* EMC_EINPUT */ +- 0x0000000d /* EMC_EINPUT_DURATION */ +- 0x00080000 /* EMC_PUTERM_EXTRA */ +- 0x00000004 /* EMC_PUTERM_WIDTH */ +- 0x00000000 /* EMC_PUTERM_ADJ */ +- 0x00000000 /* EMC_CDB_CNTL_1 */ +- 0x00000000 /* EMC_CDB_CNTL_2 */ +- 0x00000000 /* EMC_CDB_CNTL_3 */ +- 0x00000001 /* EMC_QRST */ +- 0x00000014 /* EMC_QSAFE */ +- 0x00000018 /* EMC_RDV */ +- 0x0000001a /* EMC_RDV_MASK */ +- 0x000017e2 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000003 /* EMC_PDEX2WR */ +- 0x00000011 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x000000c6 /* EMC_AR2PDEN */ +- 0x00000018 /* EMC_RW2PDEN */ +- 0x000000d6 /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000005 /* EMC_TCKE */ +- 0x00000006 /* EMC_TCKESR */ +- 0x00000005 /* EMC_TPD */ +- 0x0000001d /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000008 /* EMC_TCLKSTABLE */ +- 0x00000008 /* EMC_TCLKSTOP */ +- 0x00001822 /* EMC_TREFBW */ +- 0x00000000 /* EMC_FBIO_CFG6 */ +- 0x80000005 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x104ab198 /* EMC_FBIO_CFG5 */ +- 0xe00700b1 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00000009 /* EMC_DLL_XFORM_DQS0 */ +- 0x00000009 /* EMC_DLL_XFORM_DQS1 */ +- 0x00000009 /* EMC_DLL_XFORM_DQS2 */ +- 0x00000007 /* EMC_DLL_XFORM_DQS3 */ +- 0x00000006 /* EMC_DLL_XFORM_DQS4 */ +- 0x00000006 /* EMC_DLL_XFORM_DQS5 */ +- 0x007fc009 /* EMC_DLL_XFORM_DQS6 */ +- 0x00000006 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000009 /* EMC_DLL_XFORM_DQS8 */ +- 0x00000009 /* EMC_DLL_XFORM_DQS9 */ +- 0x00000009 /* EMC_DLL_XFORM_DQS10 */ +- 0x00000007 /* EMC_DLL_XFORM_DQS11 */ +- 0x00000006 /* EMC_DLL_XFORM_DQS12 */ +- 0x00000007 /* EMC_DLL_XFORM_DQS13 */ +- 0x00000009 /* EMC_DLL_XFORM_DQS14 */ +- 0x00000007 /* EMC_DLL_XFORM_DQS15 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00034002 /* EMC_DLL_XFORM_ADDR0 */ +- 0x00034002 /* EMC_DLL_XFORM_ADDR1 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ +- 0x00034002 /* EMC_DLL_XFORM_ADDR3 */ +- 0x00034002 /* EMC_DLL_XFORM_ADDR4 */ +- 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ +- 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ +- 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ +- 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ +- 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ +- 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */ +- 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ +- 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */ +- 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ0 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ1 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ2 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ3 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ4 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ5 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ6 */ +- 0x0000000e /* EMC_DLL_XFORM_DQ7 */ +- 0x100002a0 /* EMC_XM2CMDPADCTRL */ +- 0x00000000 /* EMC_XM2CMDPADCTRL4 */ +- 0x00111111 /* EMC_XM2CMDPADCTRL5 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL3 */ +- 0x77ffc085 /* EMC_XM2CLKPADCTRL */ +- 0x00000101 /* EMC_XM2CLKPADCTRL2 */ +- 0x81f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x07070004 /* EMC_XM2VTTGENPADCTRL */ +- 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ +- 0x61861820 /* EMC_XM2DQSPADCTRL3 */ +- 0x004d34d3 /* EMC_XM2DQSPADCTRL4 */ +- 0x004d34d3 /* EMC_XM2DQSPADCTRL5 */ +- 0x61861800 /* EMC_XM2DQSPADCTRL6 */ +- 0x0606003f /* EMC_DSR_VTTGEN_DRV */ +- 0x00000000 /* EMC_TXDSRVTTGEN */ +- 0x00000000 /* EMC_FBIO_SPARE */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x00f8000c /* EMC_MRS_WAIT_CNT2 */ +- 0x00000007 /* EMC_CTT */ +- 0x00000004 /* EMC_CTT_DURATION */ +- 0x00004080 /* EMC_CFG_PIPE */ +- 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ +- 0x0000000f /* EMC_QPOP */ +- >; +- }; +- }; +- }; +- +- memory-controller@70019000 { +- emc-timings-1 { +- nvidia,ram-code = <1>; +- +- timing-12750000 { +- clock-frequency = <12750000>; +- +- nvidia,emem-configuration = < +- 0x40040001 /* MC_EMEM_ARB_CFG */ +- 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ +- 0x77e30303 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-20400000 { +- clock-frequency = <20400000>; +- +- nvidia,emem-configuration = < +- 0x40020001 /* MC_EMEM_ARB_CFG */ +- 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ +- 0x76230303 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-40800000 { +- clock-frequency = <40800000>; +- +- nvidia,emem-configuration = < +- 0xa0000001 /* MC_EMEM_ARB_CFG */ +- 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ +- 0x74a30303 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-68000000 { +- clock-frequency = <68000000>; +- +- nvidia,emem-configuration = < +- 0x00000001 /* MC_EMEM_ARB_CFG */ +- 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ +- 0x74230403 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-102000000 { +- clock-frequency = <102000000>; +- +- nvidia,emem-configuration = < +- 0x08000001 /* MC_EMEM_ARB_CFG */ +- 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ +- 0x73c30504 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-204000000 { +- clock-frequency = <204000000>; +- +- nvidia,emem-configuration = < +- 0x01000003 /* MC_EMEM_ARB_CFG */ +- 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ +- 0x73840a06 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-300000000 { +- clock-frequency = <300000000>; +- +- nvidia,emem-configuration = < +- 0x08000004 /* MC_EMEM_ARB_CFG */ +- 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ +- 0x77450e08 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-396000000 { +- clock-frequency = <396000000>; +- +- nvidia,emem-configuration = < +- 0x0f000005 /* MC_EMEM_ARB_CFG */ +- 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ +- 0x7586120a /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-528000000 { +- clock-frequency = <528000000>; +- +- nvidia,emem-configuration = < +- 0x0f000007 /* MC_EMEM_ARB_CFG */ +- 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ +- 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ +- 0x7428180e /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-600000000 { +- clock-frequency = <600000000>; +- +- nvidia,emem-configuration = < +- 0x00000009 /* MC_EMEM_ARB_CFG */ +- 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ +- 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ +- 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-792000000 { +- clock-frequency = <792000000>; +- +- nvidia,emem-configuration = < +- 0x0e00000b /* MC_EMEM_ARB_CFG */ +- 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ +- 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ +- 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ +- 0x734c2414 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f02 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- }; +- +- emc-timings-4 { +- nvidia,ram-code = <4>; +- +- timing-12750000 { +- clock-frequency = <12750000>; +- +- nvidia,emem-configuration = < +- 0x40040001 /* MC_EMEM_ARB_CFG */ +- 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ +- 0x77e30303 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-20400000 { +- clock-frequency = <20400000>; +- +- nvidia,emem-configuration = < +- 0x40020001 /* MC_EMEM_ARB_CFG */ +- 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ +- 0x77430303 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-40800000 { +- clock-frequency = <40800000>; +- +- nvidia,emem-configuration = < +- 0xa0000001 /* MC_EMEM_ARB_CFG */ +- 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ +- 0x75e30303 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-68000000 { +- clock-frequency = <68000000>; +- +- nvidia,emem-configuration = < +- 0x00000001 /* MC_EMEM_ARB_CFG */ +- 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ +- 0x75430403 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-102000000 { +- clock-frequency = <102000000>; +- +- nvidia,emem-configuration = < +- 0x08000001 /* MC_EMEM_ARB_CFG */ +- 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ +- 0x74e30504 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-204000000 { +- clock-frequency = <204000000>; +- +- nvidia,emem-configuration = < +- 0x01000003 /* MC_EMEM_ARB_CFG */ +- 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0504 /* MC_EMEM_ARB_DA_COVERS */ +- 0x74a40a05 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-300000000 { +- clock-frequency = <300000000>; +- +- nvidia,emem-configuration = < +- 0x08000004 /* MC_EMEM_ARB_CFG */ +- 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ +- 0x77450e08 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-396000000 { +- clock-frequency = <396000000>; +- +- nvidia,emem-configuration = < +- 0x0f000005 /* MC_EMEM_ARB_CFG */ +- 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ +- 0x7586120a /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-528000000 { +- clock-frequency = <528000000>; +- +- nvidia,emem-configuration = < +- 0x0f000007 /* MC_EMEM_ARB_CFG */ +- 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ +- 0x0000000c /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000007 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x0010090c /* MC_EMEM_ARB_DA_COVERS */ +- 0x7488180d /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-600000000 { +- clock-frequency = <600000000>; +- +- nvidia,emem-configuration = < +- 0x00000009 /* MC_EMEM_ARB_CFG */ +- 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ +- 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ +- 0x74691b0f /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-792000000 { +- clock-frequency = <792000000>; +- +- nvidia,emem-configuration = < +- 0x0e00000b /* MC_EMEM_ARB_CFG */ +- 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ +- 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ +- 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x00170e13 /* MC_EMEM_ARB_DA_COVERS */ +- 0x746c2414 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f02 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- }; +- +- emc-timings-6 { +- nvidia,ram-code = <6>; +- +- timing-12750000 { +- clock-frequency = <12750000>; +- +- nvidia,emem-configuration = < +- 0x40040001 /* MC_EMEM_ARB_CFG */ +- 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ +- 0x77e30303 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-20400000 { +- clock-frequency = <20400000>; +- +- nvidia,emem-configuration = < +- 0x40020001 /* MC_EMEM_ARB_CFG */ +- 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ +- 0x76230303 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-40800000 { +- clock-frequency = <40800000>; +- +- nvidia,emem-configuration = < +- 0xa0000001 /* MC_EMEM_ARB_CFG */ +- 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ +- 0x74a30303 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-68000000 { +- clock-frequency = <68000000>; +- +- nvidia,emem-configuration = < +- 0x00000001 /* MC_EMEM_ARB_CFG */ +- 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ +- 0x74230403 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-102000000 { +- clock-frequency = <102000000>; +- +- nvidia,emem-configuration = < +- 0x08000001 /* MC_EMEM_ARB_CFG */ +- 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ +- 0x73c30504 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-204000000 { +- clock-frequency = <204000000>; +- +- nvidia,emem-configuration = < +- 0x01000003 /* MC_EMEM_ARB_CFG */ +- 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ +- 0x73840a06 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-300000000 { +- clock-frequency = <300000000>; +- +- nvidia,emem-configuration = < +- 0x08000004 /* MC_EMEM_ARB_CFG */ +- 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ +- 0x77450e08 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-396000000 { +- clock-frequency = <396000000>; +- +- nvidia,emem-configuration = < +- 0x0f000005 /* MC_EMEM_ARB_CFG */ +- 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ +- 0x7586120a /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-528000000 { +- clock-frequency = <528000000>; +- +- nvidia,emem-configuration = < +- 0x0f000007 /* MC_EMEM_ARB_CFG */ +- 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ +- 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ +- 0x7428180e /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-600000000 { +- clock-frequency = <600000000>; +- +- nvidia,emem-configuration = < +- 0x00000009 /* MC_EMEM_ARB_CFG */ +- 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ +- 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ +- 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ +- 0x70000f03 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-792000000 { +- clock-frequency = <792000000>; +- +- nvidia,emem-configuration = < +- 0x0e00000b /* MC_EMEM_ARB_CFG */ +- 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ +- 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ +- 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ +- 0x734c2414 /* MC_EMEM_ARB_MISC0 */ +- 0x70000f02 /* MC_EMEM_ARB_MISC1 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- }; +- }; +-}; +- +-&emc_icc_dvfs_opp_table { +- /delete-node/ opp@924000000,1100; +- /delete-node/ opp@1200000000,1100; +-}; +- +-&emc_bw_dfs_opp_table { +- /delete-node/ opp@924000000; +- /delete-node/ opp@1200000000; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra124-nyan-big.dts b/scripts/dtc/include-prefixes/arm/tegra124-nyan-big.dts +deleted file mode 100644 +index fdc1d64dfff9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra124-nyan-big.dts ++++ /dev/null +@@ -1,1347 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "tegra124-nyan.dtsi" +- +-#include "tegra124-nyan-big-emc.dtsi" +- +-/ { +- model = "Acer Chromebook 13 CB5-311"; +- compatible = "google,nyan-big-rev7", "google,nyan-big-rev6", +- "google,nyan-big-rev5", "google,nyan-big-rev4", +- "google,nyan-big-rev3", "google,nyan-big-rev2", +- "google,nyan-big-rev1", "google,nyan-big-rev0", +- "google,nyan-big", "google,nyan", "nvidia,tegra124"; +- +- host1x@50000000 { +- dpaux@545c0000 { +- aux-bus { +- panel: panel { +- compatible = "auo,b133xtn01"; +- backlight = <&backlight>; +- }; +- }; +- }; +- }; +- +- mmc@700b0400 { /* SD Card on this bus */ +- wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; +- }; +- +- sound { +- compatible = "nvidia,tegra-audio-max98090-nyan-big", +- "nvidia,tegra-audio-max98090-nyan", +- "nvidia,tegra-audio-max98090"; +- nvidia,model = "GoogleNyanBig"; +- }; +- +- pinmux@70000868 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinmux_default>; +- +- pinmux_default: common { +- clk_32k_out_pa0 { +- nvidia,pins = "clk_32k_out_pa0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_cts_n_pa1 { +- nvidia,pins = "uart3_cts_n_pa1"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_fs_pa2 { +- nvidia,pins = "dap2_fs_pa2"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_sclk_pa3 { +- nvidia,pins = "dap2_sclk_pa3"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_din_pa4 { +- nvidia,pins = "dap2_din_pa4"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_dout_pa5 { +- nvidia,pins = "dap2_dout_pa5"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_clk_pa6 { +- nvidia,pins = "sdmmc3_clk_pa6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_cmd_pa7 { +- nvidia,pins = "sdmmc3_cmd_pa7"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pb0 { +- nvidia,pins = "pb0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pb1 { +- nvidia,pins = "pb1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat3_pb4 { +- nvidia,pins = "sdmmc3_dat3_pb4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat2_pb5 { +- nvidia,pins = "sdmmc3_dat2_pb5"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat1_pb6 { +- nvidia,pins = "sdmmc3_dat1_pb6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat0_pb7 { +- nvidia,pins = "sdmmc3_dat0_pb7"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_rts_n_pc0 { +- nvidia,pins = "uart3_rts_n_pc0"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_txd_pc2 { +- nvidia,pins = "uart2_txd_pc2"; +- nvidia,function = "irda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_rxd_pc3 { +- nvidia,pins = "uart2_rxd_pc3"; +- nvidia,function = "irda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gen1_i2c_scl_pc4 { +- nvidia,pins = "gen1_i2c_scl_pc4"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen1_i2c_sda_pc5 { +- nvidia,pins = "gen1_i2c_sda_pc5"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pc7 { +- nvidia,pins = "pc7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg0 { +- nvidia,pins = "pg0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg1 { +- nvidia,pins = "pg1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg2 { +- nvidia,pins = "pg2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg3 { +- nvidia,pins = "pg3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg4 { +- nvidia,pins = "pg4"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg5 { +- nvidia,pins = "pg5"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg6 { +- nvidia,pins = "pg6"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg7 { +- nvidia,pins = "pg7"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph0 { +- nvidia,pins = "ph0"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph1 { +- nvidia,pins = "ph1"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph2 { +- nvidia,pins = "ph2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph3 { +- nvidia,pins = "ph3"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph4 { +- nvidia,pins = "ph4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph5 { +- nvidia,pins = "ph5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph6 { +- nvidia,pins = "ph6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph7 { +- nvidia,pins = "ph7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi0 { +- nvidia,pins = "pi0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi1 { +- nvidia,pins = "pi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi2 { +- nvidia,pins = "pi2"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi3 { +- nvidia,pins = "pi3"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi4 { +- nvidia,pins = "pi4"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi5 { +- nvidia,pins = "pi5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi6 { +- nvidia,pins = "pi6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi7 { +- nvidia,pins = "pi7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pj0 { +- nvidia,pins = "pj0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pj2 { +- nvidia,pins = "pj2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_cts_n_pj5 { +- nvidia,pins = "uart2_cts_n_pj5"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_rts_n_pj6 { +- nvidia,pins = "uart2_rts_n_pj6"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pj7 { +- nvidia,pins = "pj7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk0 { +- nvidia,pins = "pk0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk1 { +- nvidia,pins = "pk1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk2 { +- nvidia,pins = "pk2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk3 { +- nvidia,pins = "pk3"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk4 { +- nvidia,pins = "pk4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spdif_out_pk5 { +- nvidia,pins = "spdif_out_pk5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spdif_in_pk6 { +- nvidia,pins = "spdif_in_pk6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk7 { +- nvidia,pins = "pk7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_fs_pn0 { +- nvidia,pins = "dap1_fs_pn0"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_din_pn1 { +- nvidia,pins = "dap1_din_pn1"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_dout_pn2 { +- nvidia,pins = "dap1_dout_pn2"; +- nvidia,function = "i2s0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_sclk_pn3 { +- nvidia,pins = "dap1_sclk_pn3"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- usb_vbus_en0_pn4 { +- nvidia,pins = "usb_vbus_en0_pn4"; +- nvidia,function = "usb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- usb_vbus_en1_pn5 { +- nvidia,pins = "usb_vbus_en1_pn5"; +- nvidia,function = "usb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- hdmi_int_pn7 { +- nvidia,pins = "hdmi_int_pn7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,rcv-sel = ; +- }; +- ulpi_data7_po0 { +- nvidia,pins = "ulpi_data7_po0"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data0_po1 { +- nvidia,pins = "ulpi_data0_po1"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data1_po2 { +- nvidia,pins = "ulpi_data1_po2"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data2_po3 { +- nvidia,pins = "ulpi_data2_po3"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data3_po4 { +- nvidia,pins = "ulpi_data3_po4"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data4_po5 { +- nvidia,pins = "ulpi_data4_po5"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data5_po6 { +- nvidia,pins = "ulpi_data5_po6"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data6_po7 { +- nvidia,pins = "ulpi_data6_po7"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_fs_pp0 { +- nvidia,pins = "dap3_fs_pp0"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_din_pp1 { +- nvidia,pins = "dap3_din_pp1"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_dout_pp2 { +- nvidia,pins = "dap3_dout_pp2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_sclk_pp3 { +- nvidia,pins = "dap3_sclk_pp3"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_fs_pp4 { +- nvidia,pins = "dap4_fs_pp4"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_din_pp5 { +- nvidia,pins = "dap4_din_pp5"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_dout_pp6 { +- nvidia,pins = "dap4_dout_pp6"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_sclk_pp7 { +- nvidia,pins = "dap4_sclk_pp7"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col0_pq0 { +- nvidia,pins = "kb_col0_pq0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col1_pq1 { +- nvidia,pins = "kb_col1_pq1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col2_pq2 { +- nvidia,pins = "kb_col2_pq2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col3_pq3 { +- nvidia,pins = "kb_col3_pq3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col4_pq4 { +- nvidia,pins = "kb_col4_pq4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col5_pq5 { +- nvidia,pins = "kb_col5_pq5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col6_pq6 { +- nvidia,pins = "kb_col6_pq6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col7_pq7 { +- nvidia,pins = "kb_col7_pq7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row0_pr0 { +- nvidia,pins = "kb_row0_pr0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row1_pr1 { +- nvidia,pins = "kb_row1_pr1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row2_pr2 { +- nvidia,pins = "kb_row2_pr2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row3_pr3 { +- nvidia,pins = "kb_row3_pr3"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row4_pr4 { +- nvidia,pins = "kb_row4_pr4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row5_pr5 { +- nvidia,pins = "kb_row5_pr5"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row6_pr6 { +- nvidia,pins = "kb_row6_pr6"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row7_pr7 { +- nvidia,pins = "kb_row7_pr7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row8_ps0 { +- nvidia,pins = "kb_row8_ps0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row9_ps1 { +- nvidia,pins = "kb_row9_ps1"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row10_ps2 { +- nvidia,pins = "kb_row10_ps2"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row11_ps3 { +- nvidia,pins = "kb_row11_ps3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row12_ps4 { +- nvidia,pins = "kb_row12_ps4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row13_ps5 { +- nvidia,pins = "kb_row13_ps5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row14_ps6 { +- nvidia,pins = "kb_row14_ps6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row15_ps7 { +- nvidia,pins = "kb_row15_ps7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row16_pt0 { +- nvidia,pins = "kb_row16_pt0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row17_pt1 { +- nvidia,pins = "kb_row17_pt1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gen2_i2c_scl_pt5 { +- nvidia,pins = "gen2_i2c_scl_pt5"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen2_i2c_sda_pt6 { +- nvidia,pins = "gen2_i2c_sda_pt6"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc4_cmd_pt7 { +- nvidia,pins = "sdmmc4_cmd_pt7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu0 { +- nvidia,pins = "pu0"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu1 { +- nvidia,pins = "pu1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu2 { +- nvidia,pins = "pu2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu3 { +- nvidia,pins = "pu3"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu4 { +- nvidia,pins = "pu4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu5 { +- nvidia,pins = "pu5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu6 { +- nvidia,pins = "pu6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv0 { +- nvidia,pins = "pv0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv1 { +- nvidia,pins = "pv1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_cd_n_pv2 { +- nvidia,pins = "sdmmc3_cd_n_pv2"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_wp_n_pv3 { +- nvidia,pins = "sdmmc1_wp_n_pv3"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ddc_scl_pv4 { +- nvidia,pins = "ddc_scl_pv4"; +- nvidia,function = "i2c4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,rcv-sel = ; +- }; +- ddc_sda_pv5 { +- nvidia,pins = "ddc_sda_pv5"; +- nvidia,function = "i2c4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,rcv-sel = ; +- }; +- gpio_w2_aud_pw2 { +- nvidia,pins = "gpio_w2_aud_pw2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_w3_aud_pw3 { +- nvidia,pins = "gpio_w3_aud_pw3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap_mclk1_pw4 { +- nvidia,pins = "dap_mclk1_pw4"; +- nvidia,function = "extperiph1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2_out_pw5 { +- nvidia,pins = "clk2_out_pw5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_txd_pw6 { +- nvidia,pins = "uart3_txd_pw6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_rxd_pw7 { +- nvidia,pins = "uart3_rxd_pw7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dvfs_pwm_px0 { +- nvidia,pins = "dvfs_pwm_px0"; +- nvidia,function = "cldvfs"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x1_aud_px1 { +- nvidia,pins = "gpio_x1_aud_px1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dvfs_clk_px2 { +- nvidia,pins = "dvfs_clk_px2"; +- nvidia,function = "cldvfs"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x3_aud_px3 { +- nvidia,pins = "gpio_x3_aud_px3"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x4_aud_px4 { +- nvidia,pins = "gpio_x4_aud_px4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x5_aud_px5 { +- nvidia,pins = "gpio_x5_aud_px5"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x6_aud_px6 { +- nvidia,pins = "gpio_x6_aud_px6"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x7_aud_px7 { +- nvidia,pins = "gpio_x7_aud_px7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_clk_py0 { +- nvidia,pins = "ulpi_clk_py0"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_dir_py1 { +- nvidia,pins = "ulpi_dir_py1"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_nxt_py2 { +- nvidia,pins = "ulpi_nxt_py2"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_stp_py3 { +- nvidia,pins = "ulpi_stp_py3"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat3_py4 { +- nvidia,pins = "sdmmc1_dat3_py4"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat2_py5 { +- nvidia,pins = "sdmmc1_dat2_py5"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat1_py6 { +- nvidia,pins = "sdmmc1_dat1_py6"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat0_py7 { +- nvidia,pins = "sdmmc1_dat0_py7"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_clk_pz0 { +- nvidia,pins = "sdmmc1_clk_pz0"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_cmd_pz1 { +- nvidia,pins = "sdmmc1_cmd_pz1"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pwr_i2c_scl_pz6 { +- nvidia,pins = "pwr_i2c_scl_pz6"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pwr_i2c_sda_pz7 { +- nvidia,pins = "pwr_i2c_sda_pz7"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc4_dat0_paa0 { +- nvidia,pins = "sdmmc4_dat0_paa0"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat1_paa1 { +- nvidia,pins = "sdmmc4_dat1_paa1"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat2_paa2 { +- nvidia,pins = "sdmmc4_dat2_paa2"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat3_paa3 { +- nvidia,pins = "sdmmc4_dat3_paa3"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat4_paa4 { +- nvidia,pins = "sdmmc4_dat4_paa4"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat5_paa5 { +- nvidia,pins = "sdmmc4_dat5_paa5"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat6_paa6 { +- nvidia,pins = "sdmmc4_dat6_paa6"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat7_paa7 { +- nvidia,pins = "sdmmc4_dat7_paa7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb0 { +- nvidia,pins = "pbb0"; +- nvidia,function = "vgp6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cam_i2c_scl_pbb1 { +- nvidia,pins = "cam_i2c_scl_pbb1"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_i2c_sda_pbb2 { +- nvidia,pins = "cam_i2c_sda_pbb2"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pbb3 { +- nvidia,pins = "pbb3"; +- nvidia,function = "vgp3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb4 { +- nvidia,pins = "pbb4"; +- nvidia,function = "vgp4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb5 { +- nvidia,pins = "pbb5"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb6 { +- nvidia,pins = "pbb6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb7 { +- nvidia,pins = "pbb7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cam_mclk_pcc0 { +- nvidia,pins = "cam_mclk_pcc0"; +- nvidia,function = "vi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pcc1 { +- nvidia,pins = "pcc1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pcc2 { +- nvidia,pins = "pcc2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_clk_pcc4 { +- nvidia,pins = "sdmmc4_clk_pcc4"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2_req_pcc5 { +- nvidia,pins = "clk2_req_pcc5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l0_rst_n_pdd1 { +- nvidia,pins = "pex_l0_rst_n_pdd1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l0_clkreq_n_pdd2 { +- nvidia,pins = "pex_l0_clkreq_n_pdd2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_wake_n_pdd3 { +- nvidia,pins = "pex_wake_n_pdd3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l1_rst_n_pdd5 { +- nvidia,pins = "pex_l1_rst_n_pdd5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l1_clkreq_n_pdd6 { +- nvidia,pins = "pex_l1_clkreq_n_pdd6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3_out_pee0 { +- nvidia,pins = "clk3_out_pee0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3_req_pee1 { +- nvidia,pins = "clk3_req_pee1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap_mclk1_req_pee2 { +- nvidia,pins = "dap_mclk1_req_pee2"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- hdmi_cec_pee3 { +- nvidia,pins = "hdmi_cec_pee3"; +- nvidia,function = "cec"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_clk_lb_out_pee4 { +- nvidia,pins = "sdmmc3_clk_lb_out_pee4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_clk_lb_in_pee5 { +- nvidia,pins = "sdmmc3_clk_lb_in_pee5"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dp_hpd_pff0 { +- nvidia,pins = "dp_hpd_pff0"; +- nvidia,function = "dp"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- usb_vbus_en2_pff1 { +- nvidia,pins = "usb_vbus_en2_pff1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pff2 { +- nvidia,pins = "pff2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- core_pwr_req { +- nvidia,pins = "core_pwr_req"; +- nvidia,function = "pwron"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cpu_pwr_req { +- nvidia,pins = "cpu_pwr_req"; +- nvidia,function = "cpu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pwr_int_n { +- nvidia,pins = "pwr_int_n"; +- nvidia,function = "pmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- reset_out_n { +- nvidia,pins = "reset_out_n"; +- nvidia,function = "reset_out_n"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- owr { +- nvidia,pins = "owr"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,rcv-sel = ; +- }; +- clk_32k_in { +- nvidia,pins = "clk_32k_in"; +- nvidia,function = "clk"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- jtag_rtck { +- nvidia,pins = "jtag_rtck"; +- nvidia,function = "rtck"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra124-nyan-blaze-emc.dtsi b/scripts/dtc/include-prefixes/arm/tegra124-nyan-blaze-emc.dtsi +deleted file mode 100644 +index 35c98734d35f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra124-nyan-blaze-emc.dtsi ++++ /dev/null +@@ -1,2060 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- clock@60006000 { +- emc-timings-1 { +- nvidia,ram-code = <1>; +- +- timing-12750000 { +- clock-frequency = <12750000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-20400000 { +- clock-frequency = <20400000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-40800000 { +- clock-frequency = <40800000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-68000000 { +- clock-frequency = <68000000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-102000000 { +- clock-frequency = <102000000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-204000000 { +- clock-frequency = <204000000>; +- nvidia,parent-clock-frequency = <408000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_P>; +- clock-names = "emc-parent"; +- }; +- timing-300000000 { +- clock-frequency = <300000000>; +- nvidia,parent-clock-frequency = <600000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_C>; +- clock-names = "emc-parent"; +- }; +- timing-396000000 { +- clock-frequency = <396000000>; +- nvidia,parent-clock-frequency = <792000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_M>; +- clock-names = "emc-parent"; +- }; +- /* TODO: Add 528MHz frequency */ +- timing-600000000 { +- clock-frequency = <600000000>; +- nvidia,parent-clock-frequency = <600000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; +- clock-names = "emc-parent"; +- }; +- timing-792000000 { +- clock-frequency = <792000000>; +- nvidia,parent-clock-frequency = <792000000>; +- clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; +- clock-names = "emc-parent"; +- }; +- }; +- }; +- +- external-memory-controller@7001b000 { +- emc-timings-1 { +- nvidia,ram-code = <1>; +- +- timing-12750000 { +- clock-frequency = <12750000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000c000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000004 +- 0x0000000a +- 0x00000003 +- 0x0000000b +- 0x00000000 +- 0x00000000 +- 0x00000003 +- 0x00000003 +- 0x00000000 +- 0x00000006 +- 0x00000006 +- 0x00000006 +- 0x00000002 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00010000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000004 +- 0x0000000c +- 0x0000000d +- 0x0000000f +- 0x00000060 +- 0x00000000 +- 0x00000018 +- 0x00000002 +- 0x00000002 +- 0x00000001 +- 0x00000000 +- 0x00000007 +- 0x0000000f +- 0x00000005 +- 0x00000005 +- 0x00000004 +- 0x00000005 +- 0x00000004 +- 0x00000000 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00000064 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x106aa298 +- 0x002c00a0 +- 0x00008000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x0000c000 +- 0x00000000 +- 0x00000000 +- 0x0000c000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x10000280 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc081 +- 0x00000505 +- 0x81f1f108 +- 0x07070004 +- 0x0000003f +- 0x016eeeee +- 0x51451400 +- 0x00514514 +- 0x00514514 +- 0x51451400 +- 0x0000003f +- 0x00000007 +- 0x00000000 +- 0x00000042 +- 0x000c000c +- 0x00000000 +- 0x00000003 +- 0x0000f2f3 +- 0x800001c5 +- 0x0000000a +- >; +- }; +- +- timing-20400000 { +- clock-frequency = <20400000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000c000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000000 +- 0x00000005 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000004 +- 0x0000000a +- 0x00000003 +- 0x0000000b +- 0x00000000 +- 0x00000000 +- 0x00000003 +- 0x00000003 +- 0x00000000 +- 0x00000006 +- 0x00000006 +- 0x00000006 +- 0x00000002 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00010000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000004 +- 0x0000000c +- 0x0000000d +- 0x0000000f +- 0x0000009a +- 0x00000000 +- 0x00000026 +- 0x00000002 +- 0x00000002 +- 0x00000001 +- 0x00000000 +- 0x00000007 +- 0x0000000f +- 0x00000006 +- 0x00000006 +- 0x00000004 +- 0x00000005 +- 0x00000004 +- 0x00000000 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x000000a0 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x106aa298 +- 0x002c00a0 +- 0x00008000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x0000c000 +- 0x00000000 +- 0x00000000 +- 0x0000c000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x10000280 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc081 +- 0x00000505 +- 0x81f1f108 +- 0x07070004 +- 0x0000003f +- 0x016eeeee +- 0x51451400 +- 0x00514514 +- 0x00514514 +- 0x51451400 +- 0x0000003f +- 0x0000000b +- 0x00000000 +- 0x00000042 +- 0x000c000c +- 0x00000000 +- 0x00000003 +- 0x0000f2f3 +- 0x8000023a +- 0x0000000a +- >; +- }; +- +- timing-40800000 { +- clock-frequency = <40800000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000c000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000001 +- 0x0000000a +- 0x00000000 +- 0x00000001 +- 0x00000000 +- 0x00000004 +- 0x0000000a +- 0x00000003 +- 0x0000000b +- 0x00000000 +- 0x00000000 +- 0x00000003 +- 0x00000003 +- 0x00000000 +- 0x00000006 +- 0x00000006 +- 0x00000006 +- 0x00000002 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00010000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000004 +- 0x0000000c +- 0x0000000d +- 0x0000000f +- 0x00000134 +- 0x00000000 +- 0x0000004d +- 0x00000002 +- 0x00000002 +- 0x00000001 +- 0x00000000 +- 0x00000008 +- 0x0000000f +- 0x0000000c +- 0x0000000c +- 0x00000004 +- 0x00000005 +- 0x00000004 +- 0x00000000 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x0000013f +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x106aa298 +- 0x002c00a0 +- 0x00008000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x0000c000 +- 0x00000000 +- 0x00000000 +- 0x0000c000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x10000280 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc081 +- 0x00000505 +- 0x81f1f108 +- 0x07070004 +- 0x0000003f +- 0x016eeeee +- 0x51451400 +- 0x00514514 +- 0x00514514 +- 0x51451400 +- 0x0000003f +- 0x00000015 +- 0x00000000 +- 0x00000042 +- 0x000c000c +- 0x00000000 +- 0x00000003 +- 0x0000f2f3 +- 0x80000370 +- 0x0000000a +- >; +- }; +- +- timing-68000000 { +- clock-frequency = <68000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000c000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000003 +- 0x00000011 +- 0x00000000 +- 0x00000002 +- 0x00000000 +- 0x00000004 +- 0x0000000a +- 0x00000003 +- 0x0000000b +- 0x00000000 +- 0x00000000 +- 0x00000003 +- 0x00000003 +- 0x00000000 +- 0x00000006 +- 0x00000006 +- 0x00000006 +- 0x00000002 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00010000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000004 +- 0x0000000c +- 0x0000000d +- 0x0000000f +- 0x00000202 +- 0x00000000 +- 0x00000080 +- 0x00000002 +- 0x00000002 +- 0x00000001 +- 0x00000000 +- 0x0000000f +- 0x0000000f +- 0x00000013 +- 0x00000013 +- 0x00000004 +- 0x00000005 +- 0x00000004 +- 0x00000001 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00000213 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x106aa298 +- 0x002c00a0 +- 0x00008000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x0000c000 +- 0x00000000 +- 0x00000000 +- 0x0000c000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x10000280 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc081 +- 0x00000505 +- 0x81f1f108 +- 0x07070004 +- 0x0000003f +- 0x016eeeee +- 0x51451400 +- 0x00514514 +- 0x00514514 +- 0x51451400 +- 0x0000003f +- 0x00000022 +- 0x00000000 +- 0x00000042 +- 0x000c000c +- 0x00000000 +- 0x00000003 +- 0x0000f2f3 +- 0x8000050e +- 0x0000000a +- >; +- }; +- +- timing-102000000 { +- clock-frequency = <102000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x000008c5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000c000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00000000>; +- +- nvidia,emc-configuration = < +- 0x00000004 +- 0x0000001a +- 0x00000000 +- 0x00000003 +- 0x00000001 +- 0x00000004 +- 0x0000000a +- 0x00000003 +- 0x0000000b +- 0x00000001 +- 0x00000001 +- 0x00000003 +- 0x00000003 +- 0x00000000 +- 0x00000006 +- 0x00000006 +- 0x00000006 +- 0x00000002 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00010000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000004 +- 0x0000000c +- 0x0000000d +- 0x0000000f +- 0x00000304 +- 0x00000000 +- 0x000000c1 +- 0x00000002 +- 0x00000002 +- 0x00000001 +- 0x00000000 +- 0x00000018 +- 0x0000000f +- 0x0000001c +- 0x0000001c +- 0x00000004 +- 0x00000005 +- 0x00000004 +- 0x00000003 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x0000031c +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x106aa298 +- 0x002c00a0 +- 0x00008000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x0000c000 +- 0x00000000 +- 0x00000000 +- 0x0000c000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x000fc000 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x0000fc00 +- 0x10000280 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc081 +- 0x00000505 +- 0x81f1f108 +- 0x07070004 +- 0x0000003f +- 0x016eeeee +- 0x51451400 +- 0x00514514 +- 0x00514514 +- 0x51451400 +- 0x0000003f +- 0x00000033 +- 0x00000000 +- 0x00000042 +- 0x000c000c +- 0x00000000 +- 0x00000003 +- 0x0000f2f3 +- 0x80000713 +- 0x0000000a +- >; +- }; +- +- timing-204000000 { +- clock-frequency = <204000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000008>; +- nvidia,emc-cfg = <0x73240000>; +- nvidia,emc-cfg-2 = <0x0000088d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-mrs-wait-cnt = <0x000c000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000009 +- 0x00000035 +- 0x00000000 +- 0x00000007 +- 0x00000002 +- 0x00000005 +- 0x0000000a +- 0x00000003 +- 0x0000000b +- 0x00000002 +- 0x00000002 +- 0x00000003 +- 0x00000003 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00000006 +- 0x00000002 +- 0x00000000 +- 0x00000004 +- 0x00000006 +- 0x00010000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000003 +- 0x0000000d +- 0x0000000f +- 0x00000011 +- 0x00000607 +- 0x00000000 +- 0x00000181 +- 0x00000002 +- 0x00000002 +- 0x00000001 +- 0x00000000 +- 0x00000032 +- 0x0000000f +- 0x00000038 +- 0x00000038 +- 0x00000004 +- 0x00000005 +- 0x00000004 +- 0x00000007 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00000638 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x106aa298 +- 0x002c00a0 +- 0x00008000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00064000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x0000c000 +- 0x00000000 +- 0x00000000 +- 0x0000c000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00090000 +- 0x00090000 +- 0x00090000 +- 0x00090000 +- 0x00009000 +- 0x00009000 +- 0x00009000 +- 0x00009000 +- 0x10000280 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc081 +- 0x00000505 +- 0x81f1f108 +- 0x07070004 +- 0x0000003f +- 0x016eeeee +- 0x51451400 +- 0x00514514 +- 0x00514514 +- 0x51451400 +- 0x0000003f +- 0x00000066 +- 0x00000000 +- 0x00000100 +- 0x000c000c +- 0x00000000 +- 0x00000003 +- 0x0000d2b3 +- 0x80000d22 +- 0x0000000a +- >; +- }; +- +- timing-300000000 { +- clock-frequency = <300000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73340000>; +- nvidia,emc-cfg-2 = <0x000008d5>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200000>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000321>; +- nvidia,emc-mrs-wait-cnt = <0x0174000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040128>; +- nvidia,emc-xm2dqspadctrl2 = <0x01231339>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x0000000d +- 0x0000004c +- 0x00000000 +- 0x00000009 +- 0x00000003 +- 0x00000004 +- 0x00000008 +- 0x00000002 +- 0x00000009 +- 0x00000003 +- 0x00000003 +- 0x00000002 +- 0x00000002 +- 0x00000000 +- 0x00000003 +- 0x00000003 +- 0x00000005 +- 0x00000002 +- 0x00000000 +- 0x00000002 +- 0x00000007 +- 0x00020000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000001 +- 0x0000000e +- 0x00000010 +- 0x00000012 +- 0x000008e4 +- 0x00000000 +- 0x00000239 +- 0x00000001 +- 0x00000008 +- 0x00000001 +- 0x00000000 +- 0x0000004a +- 0x0000000e +- 0x00000051 +- 0x00000200 +- 0x00000004 +- 0x00000005 +- 0x00000004 +- 0x00000009 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00000924 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x104ab098 +- 0x002c00a0 +- 0x00008000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00090000 +- 0x00090000 +- 0x00000000 +- 0x00090000 +- 0x00090000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00060000 +- 0x00060000 +- 0x00060000 +- 0x00060000 +- 0x00006000 +- 0x00006000 +- 0x00006000 +- 0x00006000 +- 0x10000280 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc081 +- 0x00000202 +- 0x81f1f108 +- 0x07070004 +- 0x00000000 +- 0x016eeeee +- 0x51451420 +- 0x00514514 +- 0x00514514 +- 0x51451400 +- 0x0000003f +- 0x00000096 +- 0x00000000 +- 0x00000100 +- 0x0174000c +- 0x00000000 +- 0x00000003 +- 0x000052a3 +- 0x800012d7 +- 0x00000009 +- >; +- }; +- +- timing-396000000 { +- clock-frequency = <396000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73340000>; +- nvidia,emc-cfg-2 = <0x00000895>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200000>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000521>; +- nvidia,emc-mrs-wait-cnt = <0x015b000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x01231339>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000012 +- 0x00000065 +- 0x00000000 +- 0x0000000c +- 0x00000004 +- 0x00000005 +- 0x00000008 +- 0x00000002 +- 0x0000000a +- 0x00000004 +- 0x00000004 +- 0x00000002 +- 0x00000002 +- 0x00000000 +- 0x00000003 +- 0x00000003 +- 0x00000005 +- 0x00000002 +- 0x00000000 +- 0x00000001 +- 0x00000008 +- 0x00020000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x0000000f +- 0x00000010 +- 0x00000012 +- 0x00000bd1 +- 0x00000000 +- 0x000002f4 +- 0x00000001 +- 0x00000008 +- 0x00000001 +- 0x00000000 +- 0x00000063 +- 0x0000000f +- 0x0000006b +- 0x00000200 +- 0x00000004 +- 0x00000005 +- 0x00000004 +- 0x0000000d +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x00000c11 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x104ab098 +- 0x002c00a0 +- 0x00008000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00030000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00068000 +- 0x00068000 +- 0x00000000 +- 0x00068000 +- 0x00068000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00058000 +- 0x00058000 +- 0x00058000 +- 0x00058000 +- 0x00005800 +- 0x00005800 +- 0x00005800 +- 0x00005800 +- 0x10000280 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc081 +- 0x00000202 +- 0x81f1f108 +- 0x07070004 +- 0x00000000 +- 0x016eeeee +- 0x51451420 +- 0x00514514 +- 0x00514514 +- 0x51451400 +- 0x0000003f +- 0x000000c6 +- 0x00000000 +- 0x00000100 +- 0x015b000c +- 0x00000000 +- 0x00000003 +- 0x000052a3 +- 0x8000188b +- 0x00000009 +- >; +- }; +- +- timing-600000000 { +- clock-frequency = <600000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73300000>; +- nvidia,emc-cfg-2 = <0x0000089d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200010>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000b61>; +- nvidia,emc-mrs-wait-cnt = <0x0128000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040008>; +- nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x0000001c +- 0x0000009a +- 0x00000000 +- 0x00000013 +- 0x00000007 +- 0x00000007 +- 0x0000000b +- 0x00000003 +- 0x00000010 +- 0x00000007 +- 0x00000007 +- 0x00000002 +- 0x00000002 +- 0x00000000 +- 0x00000005 +- 0x00000005 +- 0x0000000a +- 0x00000002 +- 0x00000000 +- 0x00000003 +- 0x0000000b +- 0x00070000 +- 0x00000003 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000002 +- 0x00000012 +- 0x00000016 +- 0x00000018 +- 0x00001208 +- 0x00000000 +- 0x00000482 +- 0x00000002 +- 0x0000000d +- 0x00000001 +- 0x00000000 +- 0x00000096 +- 0x00000015 +- 0x000000a2 +- 0x00000200 +- 0x00000004 +- 0x00000005 +- 0x00000004 +- 0x00000015 +- 0x00000000 +- 0x00000006 +- 0x00000006 +- 0x00001248 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x104ab098 +- 0xe00e00b1 +- 0x00008000 +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x0000000a +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00040000 +- 0x00040000 +- 0x00000000 +- 0x00040000 +- 0x00040000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000004 +- 0x00000004 +- 0x00000001 +- 0x00000005 +- 0x00000007 +- 0x00000004 +- 0x00000006 +- 0x00000007 +- 0x00000004 +- 0x00000004 +- 0x00000001 +- 0x00000005 +- 0x00000007 +- 0x00000004 +- 0x00000006 +- 0x00000007 +- 0x0000000e +- 0x0000000e +- 0x0000000e +- 0x0000000e +- 0x0000000e +- 0x0000000e +- 0x0000000e +- 0x0000000e +- 0x100002a0 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc085 +- 0x00000202 +- 0x81f1f108 +- 0x07070004 +- 0x00000000 +- 0x016eeeee +- 0x51451420 +- 0x00514514 +- 0x00514514 +- 0x51451400 +- 0x0606003f +- 0x00000000 +- 0x00000000 +- 0x00000100 +- 0x0128000c +- 0x00000000 +- 0x00000003 +- 0x000040a0 +- 0x800024a9 +- 0x0000000e +- >; +- }; +- +- timing-792000000 { +- clock-frequency = <792000000>; +- +- nvidia,emc-auto-cal-config = <0xa1430000>; +- nvidia,emc-auto-cal-config2 = <0x00000000>; +- nvidia,emc-auto-cal-config3 = <0x00000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-bgbias-ctl0 = <0x00000000>; +- nvidia,emc-cfg = <0x73300000>; +- nvidia,emc-cfg-2 = <0x0000089d>; +- nvidia,emc-ctt-term-ctrl = <0x00000802>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200018>; +- nvidia,emc-mode-4 = <0x00000000>; +- nvidia,emc-mode-reset = <0x80000d71>; +- nvidia,emc-mrs-wait-cnt = <0x00f8000c>; +- nvidia,emc-sel-dpd-ctrl = <0x00040000>; +- nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; +- nvidia,emc-zcal-cnt-long = <0x00000042>; +- nvidia,emc-zcal-interval = <0x00020000>; +- +- nvidia,emc-configuration = < +- 0x00000025 +- 0x000000cc +- 0x00000000 +- 0x0000001a +- 0x00000009 +- 0x00000008 +- 0x0000000d +- 0x00000004 +- 0x00000013 +- 0x00000009 +- 0x00000009 +- 0x00000003 +- 0x00000002 +- 0x00000000 +- 0x00000006 +- 0x00000006 +- 0x0000000b +- 0x00000002 +- 0x00000000 +- 0x00000002 +- 0x0000000d +- 0x00080000 +- 0x00000004 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000001 +- 0x00000014 +- 0x00000018 +- 0x0000001a +- 0x000017e2 +- 0x00000000 +- 0x000005f8 +- 0x00000003 +- 0x00000011 +- 0x00000001 +- 0x00000000 +- 0x000000c6 +- 0x00000018 +- 0x000000d6 +- 0x00000200 +- 0x00000005 +- 0x00000006 +- 0x00000005 +- 0x0000001d +- 0x00000000 +- 0x00000008 +- 0x00000008 +- 0x00001822 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x104ab098 +- 0xe00700b1 +- 0x00008000 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x00000008 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x0002c000 +- 0x0002c000 +- 0x00000000 +- 0x0002c000 +- 0x0002c000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000000 +- 0x00000008 +- 0x00000008 +- 0x00000005 +- 0x00000008 +- 0x0000000a +- 0x00000008 +- 0x0000000a +- 0x0000000a +- 0x00000008 +- 0x00000008 +- 0x00000005 +- 0x00000008 +- 0x0000000a +- 0x00000008 +- 0x0000000a +- 0x0000000a +- 0x0000000e +- 0x0000000e +- 0x0000000e +- 0x0000000e +- 0x0000000e +- 0x0000000e +- 0x0000000e +- 0x0000000e +- 0x100002a0 +- 0x00000000 +- 0x00111111 +- 0x00000000 +- 0x00000000 +- 0x77ffc085 +- 0x00000202 +- 0x81f1f108 +- 0x07070004 +- 0x00000000 +- 0x016eeeee +- 0x61861820 +- 0x00492492 +- 0x00492492 +- 0x61861800 +- 0x0606003f +- 0x00000000 +- 0x00000000 +- 0x00000100 +- 0x00f8000c +- 0x00000000 +- 0x00000004 +- 0x00004080 +- 0x80003012 +- 0x0000000f +- >; +- }; +- +- }; +- }; +- +- memory-controller@70019000 { +- emc-timings-1 { +- nvidia,ram-code = <1>; +- +- +- timing-12750000 { +- clock-frequency = <12750000>; +- +- nvidia,emem-configuration = < +- 0x40040001 +- 0x8000000a +- 0x00000001 +- 0x00000001 +- 0x00000002 +- 0x00000000 +- 0x00000002 +- 0x00000001 +- 0x00000002 +- 0x00000008 +- 0x00000003 +- 0x00000002 +- 0x00000003 +- 0x00000006 +- 0x06030203 +- 0x000a0402 +- 0x77e30303 +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-20400000 { +- clock-frequency = <20400000>; +- +- nvidia,emem-configuration = < +- 0x40020001 +- 0x80000012 +- 0x00000001 +- 0x00000001 +- 0x00000002 +- 0x00000000 +- 0x00000002 +- 0x00000001 +- 0x00000002 +- 0x00000008 +- 0x00000003 +- 0x00000002 +- 0x00000003 +- 0x00000006 +- 0x06030203 +- 0x000a0402 +- 0x76230303 +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-40800000 { +- clock-frequency = <40800000>; +- +- nvidia,emem-configuration = < +- 0xa0000001 +- 0x80000017 +- 0x00000001 +- 0x00000001 +- 0x00000002 +- 0x00000000 +- 0x00000002 +- 0x00000001 +- 0x00000002 +- 0x00000008 +- 0x00000003 +- 0x00000002 +- 0x00000003 +- 0x00000006 +- 0x06030203 +- 0x000a0402 +- 0x74a30303 +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-68000000 { +- clock-frequency = <68000000>; +- +- nvidia,emem-configuration = < +- 0x00000001 +- 0x8000001e +- 0x00000001 +- 0x00000001 +- 0x00000002 +- 0x00000000 +- 0x00000002 +- 0x00000001 +- 0x00000002 +- 0x00000008 +- 0x00000003 +- 0x00000002 +- 0x00000003 +- 0x00000006 +- 0x06030203 +- 0x000a0402 +- 0x74230403 +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-102000000 { +- clock-frequency = <102000000>; +- +- nvidia,emem-configuration = < +- 0x08000001 +- 0x80000026 +- 0x00000001 +- 0x00000001 +- 0x00000003 +- 0x00000000 +- 0x00000002 +- 0x00000001 +- 0x00000002 +- 0x00000008 +- 0x00000003 +- 0x00000002 +- 0x00000003 +- 0x00000006 +- 0x06030203 +- 0x000a0403 +- 0x73c30504 +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-204000000 { +- clock-frequency = <204000000>; +- +- nvidia,emem-configuration = < +- 0x01000003 +- 0x80000040 +- 0x00000001 +- 0x00000001 +- 0x00000005 +- 0x00000002 +- 0x00000004 +- 0x00000001 +- 0x00000002 +- 0x00000008 +- 0x00000003 +- 0x00000002 +- 0x00000004 +- 0x00000006 +- 0x06040203 +- 0x000a0405 +- 0x73840a06 +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-300000000 { +- clock-frequency = <300000000>; +- +- nvidia,emem-configuration = < +- 0x08000004 +- 0x80000040 +- 0x00000001 +- 0x00000002 +- 0x00000007 +- 0x00000004 +- 0x00000005 +- 0x00000001 +- 0x00000002 +- 0x00000007 +- 0x00000002 +- 0x00000002 +- 0x00000004 +- 0x00000006 +- 0x06040202 +- 0x000b0607 +- 0x77450e08 +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-396000000 { +- clock-frequency = <396000000>; +- +- nvidia,emem-configuration = < +- 0x0f000005 +- 0x80000040 +- 0x00000001 +- 0x00000002 +- 0x00000009 +- 0x00000005 +- 0x00000007 +- 0x00000001 +- 0x00000002 +- 0x00000008 +- 0x00000002 +- 0x00000002 +- 0x00000004 +- 0x00000006 +- 0x06040202 +- 0x000d0709 +- 0x7586120a +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-528000000 { +- clock-frequency = <528000000>; +- +- nvidia,emem-configuration = < +- 0x0f000007 +- 0x80000040 +- 0x00000002 +- 0x00000003 +- 0x0000000d +- 0x00000008 +- 0x0000000a +- 0x00000001 +- 0x00000002 +- 0x00000009 +- 0x00000002 +- 0x00000002 +- 0x00000005 +- 0x00000006 +- 0x06050202 +- 0x0010090d +- 0x7428180e +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-600000000 { +- clock-frequency = <600000000>; +- +- nvidia,emem-configuration = < +- 0x00000009 +- 0x80000040 +- 0x00000003 +- 0x00000004 +- 0x0000000e +- 0x00000009 +- 0x0000000b +- 0x00000001 +- 0x00000003 +- 0x0000000b +- 0x00000002 +- 0x00000002 +- 0x00000005 +- 0x00000007 +- 0x07050202 +- 0x00130b0e +- 0x73a91b0f +- 0x70000f03 +- 0x001f0000 +- >; +- }; +- +- timing-792000000 { +- clock-frequency = <792000000>; +- +- nvidia,emem-configuration = < +- 0x0e00000b +- 0x80000040 +- 0x00000004 +- 0x00000005 +- 0x00000013 +- 0x0000000c +- 0x0000000f +- 0x00000002 +- 0x00000003 +- 0x0000000c +- 0x00000002 +- 0x00000002 +- 0x00000006 +- 0x00000008 +- 0x08060202 +- 0x00160d13 +- 0x734c2414 +- 0x70000f02 +- 0x001f0000 +- >; +- }; +- }; +- }; +-}; +- +-&emc_icc_dvfs_opp_table { +- /delete-node/ opp@924000000,1100; +- /delete-node/ opp@1200000000,1100; +-}; +- +-&emc_bw_dfs_opp_table { +- /delete-node/ opp@924000000; +- /delete-node/ opp@1200000000; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra124-nyan-blaze.dts b/scripts/dtc/include-prefixes/arm/tegra124-nyan-blaze.dts +deleted file mode 100644 +index abdf4456826f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra124-nyan-blaze.dts ++++ /dev/null +@@ -1,1345 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "tegra124-nyan.dtsi" +- +-#include "tegra124-nyan-blaze-emc.dtsi" +- +-/ { +- model = "HP Chromebook 14"; +- compatible = "google,nyan-blaze-rev10", "google,nyan-blaze-rev9", +- "google,nyan-blaze-rev8", "google,nyan-blaze-rev7", +- "google,nyan-blaze-rev6", "google,nyan-blaze-rev5", +- "google,nyan-blaze-rev4", "google,nyan-blaze-rev3", +- "google,nyan-blaze-rev2", "google,nyan-blaze-rev1", +- "google,nyan-blaze-rev0", "google,nyan-blaze", +- "google,nyan", "nvidia,tegra124"; +- +- host1x@50000000 { +- dpaux@545c0000 { +- aux-bus { +- panel: panel { +- compatible = "samsung,ltn140at29-301"; +- backlight = <&backlight>; +- }; +- }; +- }; +- }; +- +- sound { +- compatible = "nvidia,tegra-audio-max98090-nyan-blaze", +- "nvidia,tegra-audio-max98090-nyan", +- "nvidia,tegra-audio-max98090"; +- nvidia,model = "GoogleNyanBlaze"; +- }; +- +- pinmux@70000868 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinmux_default>; +- +- pinmux_default: common { +- clk_32k_out_pa0 { +- nvidia,pins = "clk_32k_out_pa0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_cts_n_pa1 { +- nvidia,pins = "uart3_cts_n_pa1"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_fs_pa2 { +- nvidia,pins = "dap2_fs_pa2"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_sclk_pa3 { +- nvidia,pins = "dap2_sclk_pa3"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_din_pa4 { +- nvidia,pins = "dap2_din_pa4"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_dout_pa5 { +- nvidia,pins = "dap2_dout_pa5"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_clk_pa6 { +- nvidia,pins = "sdmmc3_clk_pa6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_cmd_pa7 { +- nvidia,pins = "sdmmc3_cmd_pa7"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pb0 { +- nvidia,pins = "pb0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pb1 { +- nvidia,pins = "pb1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat3_pb4 { +- nvidia,pins = "sdmmc3_dat3_pb4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat2_pb5 { +- nvidia,pins = "sdmmc3_dat2_pb5"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat1_pb6 { +- nvidia,pins = "sdmmc3_dat1_pb6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat0_pb7 { +- nvidia,pins = "sdmmc3_dat0_pb7"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_rts_n_pc0 { +- nvidia,pins = "uart3_rts_n_pc0"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_txd_pc2 { +- nvidia,pins = "uart2_txd_pc2"; +- nvidia,function = "irda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_rxd_pc3 { +- nvidia,pins = "uart2_rxd_pc3"; +- nvidia,function = "irda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gen1_i2c_scl_pc4 { +- nvidia,pins = "gen1_i2c_scl_pc4"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen1_i2c_sda_pc5 { +- nvidia,pins = "gen1_i2c_sda_pc5"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pc7 { +- nvidia,pins = "pc7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg0 { +- nvidia,pins = "pg0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg1 { +- nvidia,pins = "pg1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg2 { +- nvidia,pins = "pg2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg3 { +- nvidia,pins = "pg3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg4 { +- nvidia,pins = "pg4"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg5 { +- nvidia,pins = "pg5"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg6 { +- nvidia,pins = "pg6"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg7 { +- nvidia,pins = "pg7"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph0 { +- nvidia,pins = "ph0"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph1 { +- nvidia,pins = "ph1"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph2 { +- nvidia,pins = "ph2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph3 { +- nvidia,pins = "ph3"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph4 { +- nvidia,pins = "ph4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph5 { +- nvidia,pins = "ph5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph6 { +- nvidia,pins = "ph6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph7 { +- nvidia,pins = "ph7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi0 { +- nvidia,pins = "pi0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi1 { +- nvidia,pins = "pi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi2 { +- nvidia,pins = "pi2"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi3 { +- nvidia,pins = "pi3"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi4 { +- nvidia,pins = "pi4"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi5 { +- nvidia,pins = "pi5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi6 { +- nvidia,pins = "pi6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pi7 { +- nvidia,pins = "pi7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pj0 { +- nvidia,pins = "pj0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pj2 { +- nvidia,pins = "pj2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_cts_n_pj5 { +- nvidia,pins = "uart2_cts_n_pj5"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_rts_n_pj6 { +- nvidia,pins = "uart2_rts_n_pj6"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pj7 { +- nvidia,pins = "pj7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk0 { +- nvidia,pins = "pk0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk1 { +- nvidia,pins = "pk1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk2 { +- nvidia,pins = "pk2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk3 { +- nvidia,pins = "pk3"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk4 { +- nvidia,pins = "pk4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spdif_out_pk5 { +- nvidia,pins = "spdif_out_pk5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spdif_in_pk6 { +- nvidia,pins = "spdif_in_pk6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk7 { +- nvidia,pins = "pk7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_fs_pn0 { +- nvidia,pins = "dap1_fs_pn0"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_din_pn1 { +- nvidia,pins = "dap1_din_pn1"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_dout_pn2 { +- nvidia,pins = "dap1_dout_pn2"; +- nvidia,function = "i2s0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_sclk_pn3 { +- nvidia,pins = "dap1_sclk_pn3"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- usb_vbus_en0_pn4 { +- nvidia,pins = "usb_vbus_en0_pn4"; +- nvidia,function = "usb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- usb_vbus_en1_pn5 { +- nvidia,pins = "usb_vbus_en1_pn5"; +- nvidia,function = "usb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- hdmi_int_pn7 { +- nvidia,pins = "hdmi_int_pn7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,rcv-sel = ; +- }; +- ulpi_data7_po0 { +- nvidia,pins = "ulpi_data7_po0"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data0_po1 { +- nvidia,pins = "ulpi_data0_po1"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data1_po2 { +- nvidia,pins = "ulpi_data1_po2"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data2_po3 { +- nvidia,pins = "ulpi_data2_po3"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data3_po4 { +- nvidia,pins = "ulpi_data3_po4"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data4_po5 { +- nvidia,pins = "ulpi_data4_po5"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data5_po6 { +- nvidia,pins = "ulpi_data5_po6"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data6_po7 { +- nvidia,pins = "ulpi_data6_po7"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_fs_pp0 { +- nvidia,pins = "dap3_fs_pp0"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_din_pp1 { +- nvidia,pins = "dap3_din_pp1"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_dout_pp2 { +- nvidia,pins = "dap3_dout_pp2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_sclk_pp3 { +- nvidia,pins = "dap3_sclk_pp3"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_fs_pp4 { +- nvidia,pins = "dap4_fs_pp4"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_din_pp5 { +- nvidia,pins = "dap4_din_pp5"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_dout_pp6 { +- nvidia,pins = "dap4_dout_pp6"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_sclk_pp7 { +- nvidia,pins = "dap4_sclk_pp7"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col0_pq0 { +- nvidia,pins = "kb_col0_pq0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col1_pq1 { +- nvidia,pins = "kb_col1_pq1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col2_pq2 { +- nvidia,pins = "kb_col2_pq2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col3_pq3 { +- nvidia,pins = "kb_col3_pq3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col4_pq4 { +- nvidia,pins = "kb_col4_pq4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col5_pq5 { +- nvidia,pins = "kb_col5_pq5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col6_pq6 { +- nvidia,pins = "kb_col6_pq6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col7_pq7 { +- nvidia,pins = "kb_col7_pq7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row0_pr0 { +- nvidia,pins = "kb_row0_pr0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row1_pr1 { +- nvidia,pins = "kb_row1_pr1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row2_pr2 { +- nvidia,pins = "kb_row2_pr2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row3_pr3 { +- nvidia,pins = "kb_row3_pr3"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row4_pr4 { +- nvidia,pins = "kb_row4_pr4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row5_pr5 { +- nvidia,pins = "kb_row5_pr5"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row6_pr6 { +- nvidia,pins = "kb_row6_pr6"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row7_pr7 { +- nvidia,pins = "kb_row7_pr7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row8_ps0 { +- nvidia,pins = "kb_row8_ps0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row9_ps1 { +- nvidia,pins = "kb_row9_ps1"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row10_ps2 { +- nvidia,pins = "kb_row10_ps2"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row11_ps3 { +- nvidia,pins = "kb_row11_ps3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row12_ps4 { +- nvidia,pins = "kb_row12_ps4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row13_ps5 { +- nvidia,pins = "kb_row13_ps5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row14_ps6 { +- nvidia,pins = "kb_row14_ps6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row15_ps7 { +- nvidia,pins = "kb_row15_ps7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row16_pt0 { +- nvidia,pins = "kb_row16_pt0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row17_pt1 { +- nvidia,pins = "kb_row17_pt1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gen2_i2c_scl_pt5 { +- nvidia,pins = "gen2_i2c_scl_pt5"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen2_i2c_sda_pt6 { +- nvidia,pins = "gen2_i2c_sda_pt6"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc4_cmd_pt7 { +- nvidia,pins = "sdmmc4_cmd_pt7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu0 { +- nvidia,pins = "pu0"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu1 { +- nvidia,pins = "pu1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu2 { +- nvidia,pins = "pu2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu3 { +- nvidia,pins = "pu3"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu4 { +- nvidia,pins = "pu4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu5 { +- nvidia,pins = "pu5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu6 { +- nvidia,pins = "pu6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv0 { +- nvidia,pins = "pv0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv1 { +- nvidia,pins = "pv1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_cd_n_pv2 { +- nvidia,pins = "sdmmc3_cd_n_pv2"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_wp_n_pv3 { +- nvidia,pins = "sdmmc1_wp_n_pv3"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ddc_scl_pv4 { +- nvidia,pins = "ddc_scl_pv4"; +- nvidia,function = "i2c4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,rcv-sel = ; +- }; +- ddc_sda_pv5 { +- nvidia,pins = "ddc_sda_pv5"; +- nvidia,function = "i2c4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,rcv-sel = ; +- }; +- gpio_w2_aud_pw2 { +- nvidia,pins = "gpio_w2_aud_pw2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_w3_aud_pw3 { +- nvidia,pins = "gpio_w3_aud_pw3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap_mclk1_pw4 { +- nvidia,pins = "dap_mclk1_pw4"; +- nvidia,function = "extperiph1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2_out_pw5 { +- nvidia,pins = "clk2_out_pw5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_txd_pw6 { +- nvidia,pins = "uart3_txd_pw6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_rxd_pw7 { +- nvidia,pins = "uart3_rxd_pw7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dvfs_pwm_px0 { +- nvidia,pins = "dvfs_pwm_px0"; +- nvidia,function = "cldvfs"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x1_aud_px1 { +- nvidia,pins = "gpio_x1_aud_px1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dvfs_clk_px2 { +- nvidia,pins = "dvfs_clk_px2"; +- nvidia,function = "cldvfs"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x3_aud_px3 { +- nvidia,pins = "gpio_x3_aud_px3"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x4_aud_px4 { +- nvidia,pins = "gpio_x4_aud_px4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x5_aud_px5 { +- nvidia,pins = "gpio_x5_aud_px5"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x6_aud_px6 { +- nvidia,pins = "gpio_x6_aud_px6"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gpio_x7_aud_px7 { +- nvidia,pins = "gpio_x7_aud_px7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_clk_py0 { +- nvidia,pins = "ulpi_clk_py0"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_dir_py1 { +- nvidia,pins = "ulpi_dir_py1"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_nxt_py2 { +- nvidia,pins = "ulpi_nxt_py2"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_stp_py3 { +- nvidia,pins = "ulpi_stp_py3"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat3_py4 { +- nvidia,pins = "sdmmc1_dat3_py4"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat2_py5 { +- nvidia,pins = "sdmmc1_dat2_py5"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat1_py6 { +- nvidia,pins = "sdmmc1_dat1_py6"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat0_py7 { +- nvidia,pins = "sdmmc1_dat0_py7"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_clk_pz0 { +- nvidia,pins = "sdmmc1_clk_pz0"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_cmd_pz1 { +- nvidia,pins = "sdmmc1_cmd_pz1"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pwr_i2c_scl_pz6 { +- nvidia,pins = "pwr_i2c_scl_pz6"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pwr_i2c_sda_pz7 { +- nvidia,pins = "pwr_i2c_sda_pz7"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc4_dat0_paa0 { +- nvidia,pins = "sdmmc4_dat0_paa0"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat1_paa1 { +- nvidia,pins = "sdmmc4_dat1_paa1"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat2_paa2 { +- nvidia,pins = "sdmmc4_dat2_paa2"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat3_paa3 { +- nvidia,pins = "sdmmc4_dat3_paa3"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat4_paa4 { +- nvidia,pins = "sdmmc4_dat4_paa4"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat5_paa5 { +- nvidia,pins = "sdmmc4_dat5_paa5"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat6_paa6 { +- nvidia,pins = "sdmmc4_dat6_paa6"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat7_paa7 { +- nvidia,pins = "sdmmc4_dat7_paa7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb0 { +- nvidia,pins = "pbb0"; +- nvidia,function = "vgp6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cam_i2c_scl_pbb1 { +- nvidia,pins = "cam_i2c_scl_pbb1"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_i2c_sda_pbb2 { +- nvidia,pins = "cam_i2c_sda_pbb2"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pbb3 { +- nvidia,pins = "pbb3"; +- nvidia,function = "vgp3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb4 { +- nvidia,pins = "pbb4"; +- nvidia,function = "vgp4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb5 { +- nvidia,pins = "pbb5"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb6 { +- nvidia,pins = "pbb6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb7 { +- nvidia,pins = "pbb7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cam_mclk_pcc0 { +- nvidia,pins = "cam_mclk_pcc0"; +- nvidia,function = "vi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pcc1 { +- nvidia,pins = "pcc1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pcc2 { +- nvidia,pins = "pcc2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_clk_pcc4 { +- nvidia,pins = "sdmmc4_clk_pcc4"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2_req_pcc5 { +- nvidia,pins = "clk2_req_pcc5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l0_rst_n_pdd1 { +- nvidia,pins = "pex_l0_rst_n_pdd1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l0_clkreq_n_pdd2 { +- nvidia,pins = "pex_l0_clkreq_n_pdd2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_wake_n_pdd3 { +- nvidia,pins = "pex_wake_n_pdd3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l1_rst_n_pdd5 { +- nvidia,pins = "pex_l1_rst_n_pdd5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l1_clkreq_n_pdd6 { +- nvidia,pins = "pex_l1_clkreq_n_pdd6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3_out_pee0 { +- nvidia,pins = "clk3_out_pee0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3_req_pee1 { +- nvidia,pins = "clk3_req_pee1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap_mclk1_req_pee2 { +- nvidia,pins = "dap_mclk1_req_pee2"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- hdmi_cec_pee3 { +- nvidia,pins = "hdmi_cec_pee3"; +- nvidia,function = "cec"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_clk_lb_out_pee4 { +- nvidia,pins = "sdmmc3_clk_lb_out_pee4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_clk_lb_in_pee5 { +- nvidia,pins = "sdmmc3_clk_lb_in_pee5"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dp_hpd_pff0 { +- nvidia,pins = "dp_hpd_pff0"; +- nvidia,function = "dp"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- usb_vbus_en2_pff1 { +- nvidia,pins = "usb_vbus_en2_pff1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pff2 { +- nvidia,pins = "pff2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- core_pwr_req { +- nvidia,pins = "core_pwr_req"; +- nvidia,function = "pwron"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cpu_pwr_req { +- nvidia,pins = "cpu_pwr_req"; +- nvidia,function = "cpu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pwr_int_n { +- nvidia,pins = "pwr_int_n"; +- nvidia,function = "pmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- reset_out_n { +- nvidia,pins = "reset_out_n"; +- nvidia,function = "reset_out_n"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- owr { +- nvidia,pins = "owr"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,rcv-sel = ; +- }; +- clk_32k_in { +- nvidia,pins = "clk_32k_in"; +- nvidia,function = "clk"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- jtag_rtck { +- nvidia,pins = "jtag_rtck"; +- nvidia,function = "rtck"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra124-nyan.dtsi b/scripts/dtc/include-prefixes/arm/tegra124-nyan.dtsi +deleted file mode 100644 +index 63a81270300a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra124-nyan.dtsi ++++ /dev/null +@@ -1,789 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include "tegra124.dtsi" +- +-/ { +- aliases { +- rtc0 = "/i2c@7000d000/pmic@40"; +- rtc1 = "/rtc@7000e000"; +- serial0 = &uarta; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- /* +- * Note that recent version of the device tree compiler (starting with +- * version 1.4.2) warn about this node containing a reg property, but +- * missing a unit-address. However, the bootloader on these Chromebook +- * devices relies on the full name of this node to be exactly /memory. +- * Adding the unit-address causes the bootloader to create a /memory +- * node and write the memory bank configuration to that node, which in +- * turn leads the kernel to believe that the device has 2 GiB of +- * memory instead of the amount detected by the bootloader. +- * +- * The name of this node is effectively ABI and must not be changed. +- */ +- memory { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0x80000000>; +- }; +- +- /delete-node/ memory@80000000; +- +- host1x@50000000 { +- hdmi@54280000 { +- status = "okay"; +- +- vdd-supply = <&vdd_3v3_hdmi>; +- pll-supply = <&vdd_hdmi_pll>; +- hdmi-supply = <&vdd_5v0_hdmi>; +- +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = +- <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; +- }; +- +- sor@54540000 { +- status = "okay"; +- +- avdd-io-hdmi-dp-supply = <&vdd_3v3_hdmi>; +- vdd-hdmi-dp-pll-supply = <&vdd_hdmi_pll>; +- +- nvidia,dpaux = <&dpaux>; +- nvidia,panel = <&panel>; +- }; +- +- dpaux@545c0000 { +- vdd-supply = <&vdd_3v3_panel>; +- status = "okay"; +- }; +- }; +- +- gpu@0,57000000 { +- status = "okay"; +- +- vdd-supply = <&vdd_gpu>; +- }; +- +- serial@70006000 { +- /* Debug connector on the bottom of the board near SD card. */ +- status = "okay"; +- }; +- +- pwm@7000a000 { +- status = "okay"; +- }; +- +- i2c@7000c000 { +- status = "okay"; +- clock-frequency = <100000>; +- +- acodec: audio-codec@10 { +- compatible = "maxim,max98090"; +- reg = <0x10>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- }; +- +- temperature-sensor@4c { +- compatible = "ti,tmp451"; +- reg = <0x4c>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- #thermal-sensor-cells = <1>; +- }; +- }; +- +- i2c@7000c400 { +- status = "okay"; +- clock-frequency = <100000>; +- +- trackpad@15 { +- compatible = "elan,ekth3000"; +- reg = <0x15>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- wakeup-source; +- }; +- }; +- +- i2c@7000c500 { +- status = "okay"; +- clock-frequency = <400000>; +- +- tpm@20 { +- compatible = "infineon,slb9645tt"; +- reg = <0x20>; +- }; +- }; +- +- hdmi_ddc: i2c@7000c700 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- pmic: pmic@40 { +- compatible = "ams,as3722"; +- reg = <0x40>; +- interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; +- +- ams,system-power-controller; +- +- #interrupt-cells = <2>; +- interrupt-controller; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&as3722_default>; +- +- as3722_default: pinmux { +- gpio0 { +- pins = "gpio0"; +- function = "gpio"; +- bias-pull-down; +- }; +- +- gpio1 { +- pins = "gpio1"; +- function = "gpio"; +- bias-pull-up; +- }; +- +- gpio2_4_7 { +- pins = "gpio2", "gpio4", "gpio7"; +- function = "gpio"; +- bias-pull-up; +- }; +- +- gpio3_6 { +- pins = "gpio3", "gpio6"; +- bias-high-impedance; +- }; +- +- gpio5 { +- pins = "gpio5"; +- function = "clk32k-out"; +- bias-pull-down; +- }; +- }; +- +- regulators { +- vsup-sd2-supply = <&vdd_5v0_sys>; +- vsup-sd3-supply = <&vdd_5v0_sys>; +- vsup-sd4-supply = <&vdd_5v0_sys>; +- vsup-sd5-supply = <&vdd_5v0_sys>; +- vin-ldo0-supply = <&vdd_1v35_lp0>; +- vin-ldo1-6-supply = <&vdd_3v3_run>; +- vin-ldo2-5-7-supply = <&vddio_1v8>; +- vin-ldo3-4-supply = <&vdd_3v3_sys>; +- vin-ldo9-10-supply = <&vdd_5v0_sys>; +- vin-ldo11-supply = <&vdd_3v3_run>; +- +- vdd_cpu: sd0 { +- regulator-name = "+VDD_CPU_AP"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-min-microamp = <3500000>; +- regulator-max-microamp = <3500000>; +- regulator-always-on; +- regulator-boot-on; +- ams,ext-control = <2>; +- }; +- +- sd1 { +- regulator-name = "+VDD_CORE"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-min-microamp = <2500000>; +- regulator-max-microamp = <4000000>; +- regulator-always-on; +- regulator-boot-on; +- ams,ext-control = <1>; +- }; +- +- vdd_1v35_lp0: sd2 { +- regulator-name = "+1.35V_LP0(sd2)"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- sd3 { +- regulator-name = "+1.35V_LP0(sd3)"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v05_run: sd4 { +- regulator-name = "+1.05V_RUN"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- vddio_1v8: sd5 { +- regulator-name = "+1.8V_VDDIO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vdd_gpu: sd6 { +- regulator-name = "+VDD_GPU_AP"; +- regulator-min-microvolt = <650000>; +- regulator-max-microvolt = <1200000>; +- regulator-min-microamp = <3500000>; +- regulator-max-microamp = <3500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- avdd_1v05_run: ldo0 { +- regulator-name = "+1.05V_RUN_AVDD"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-boot-on; +- regulator-always-on; +- ams,ext-control = <1>; +- }; +- +- ldo1 { +- regulator-name = "+1.8V_RUN_CAM"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo2 { +- regulator-name = "+1.2V_GEN_AVDD"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo3 { +- regulator-name = "+1.00V_LP0_VDD_RTC"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-boot-on; +- regulator-always-on; +- ams,enable-tracking; +- }; +- +- vdd_run_cam: ldo4 { +- regulator-name = "+3.3V_RUN_CAM"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo5 { +- regulator-name = "+1.2V_RUN_CAM_FRONT"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- vddio_sdmmc3: ldo6 { +- regulator-name = "+VDDIO_SDMMC3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo7 { +- regulator-name = "+1.05V_RUN_CAM_REAR"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- ldo9 { +- regulator-name = "+2.8V_RUN_TOUCH"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo10 { +- regulator-name = "+2.8V_RUN_CAM_AF"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo11 { +- regulator-name = "+1.8V_RUN_VPP_FUSE"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- }; +- }; +- }; +- +- spi@7000d400 { +- status = "okay"; +- +- cros_ec: cros-ec@0 { +- compatible = "google,cros-ec-spi"; +- spi-max-frequency = <3000000>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- reg = <0>; +- +- google,cros-ec-spi-msg-delay = <2000>; +- +- i2c-tunnel { +- compatible = "google,cros-ec-i2c-tunnel"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- google,remote-bus = <0>; +- +- charger: bq24735@9 { +- compatible = "ti,bq24735"; +- reg = <0x9>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- ti,ac-detect-gpios = <&gpio +- TEGRA_GPIO(J, 0) +- GPIO_ACTIVE_HIGH>; +- ti,external-control; +- }; +- +- battery: sbs-battery@b { +- compatible = "sbs,sbs-battery"; +- reg = <0xb>; +- sbs,i2c-retry-count = <2>; +- sbs,poll-retry-count = <10>; +- power-supplies = <&charger>; +- }; +- }; +- }; +- }; +- +- spi@7000da00 { +- status = "okay"; +- spi-max-frequency = <25000000>; +- +- flash@0 { +- compatible = "winbond,w25q32dw", "jedec,spi-nor"; +- spi-max-frequency = <25000000>; +- reg = <0>; +- }; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <0>; +- nvidia,cpu-pwr-good-time = <500>; +- nvidia,cpu-pwr-off-time = <300>; +- nvidia,core-pwr-good-time = <641 3845>; +- nvidia,core-pwr-off-time = <61036>; +- nvidia,core-power-req-active-high; +- nvidia,sys-clock-req-active-high; +- }; +- +- hda@70030000 { +- status = "okay"; +- }; +- +- usb@70090000 { +- phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ +- <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ +- <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ +- phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; +- +- avddio-pex-supply = <&vdd_1v05_run>; +- dvddio-pex-supply = <&vdd_1v05_run>; +- avdd-usb-supply = <&vdd_3v3_lp0>; +- avdd-pll-utmip-supply = <&vddio_1v8>; +- avdd-pll-erefe-supply = <&avdd_1v05_run>; +- avdd-usb-ss-pll-supply = <&vdd_1v05_run>; +- hvdd-usb-ss-supply = <&vdd_3v3_lp0>; +- hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; +- +- status = "okay"; +- }; +- +- padctl@7009f000 { +- status = "okay"; +- +- avdd-pll-utmip-supply = <&vddio_1v8>; +- avdd-pll-erefe-supply = <&avdd_1v05_run>; +- avdd-pex-pll-supply = <&vdd_1v05_run>; +- hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; +- +- pads { +- usb2 { +- status = "okay"; +- +- lanes { +- usb2-0 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- +- usb2-1 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- +- usb2-2 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- }; +- }; +- +- pcie { +- status = "okay"; +- +- lanes { +- pcie-0 { +- nvidia,function = "usb3-ss"; +- status = "okay"; +- }; +- +- pcie-1 { +- nvidia,function = "usb3-ss"; +- status = "okay"; +- }; +- }; +- }; +- }; +- +- ports { +- usb2-0 { +- vbus-supply = <&vdd_usb1_vbus>; +- status = "okay"; +- mode = "otg"; +- }; +- +- usb2-1 { +- vbus-supply = <&vdd_run_cam>; +- status = "okay"; +- mode = "host"; +- }; +- +- usb2-2 { +- vbus-supply = <&vdd_usb3_vbus>; +- status = "okay"; +- mode = "host"; +- }; +- +- usb3-0 { +- nvidia,usb2-companion = <0>; +- status = "okay"; +- }; +- +- usb3-1 { +- nvidia,usb2-companion = <1>; +- status = "okay"; +- }; +- }; +- }; +- +- sdhci0_pwrseq: sdhci0_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- +- reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; +- }; +- +- mmc@700b0000 { /* WiFi/BT on this bus */ +- status = "okay"; +- bus-width = <4>; +- no-1-8-v; +- non-removable; +- mmc-pwrseq = <&sdhci0_pwrseq>; +- vmmc-supply = <&vdd_3v3_lp0>; +- vqmmc-supply = <&vddio_1v8>; +- keep-power-in-suspend; +- }; +- +- mmc@700b0400 { /* SD Card on this bus */ +- status = "okay"; +- cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; +- power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; +- bus-width = <4>; +- no-1-8-v; +- vqmmc-supply = <&vddio_sdmmc3>; +- }; +- +- mmc@700b0600 { /* eMMC on this bus */ +- status = "okay"; +- bus-width = <8>; +- no-1-8-v; +- non-removable; +- }; +- +- /* CPU DFLL clock */ +- clock@70110000 { +- status = "disabled"; +- vdd-cpu-supply = <&vdd_cpu>; +- nvidia,i2c-fs-rate = <400000>; +- }; +- +- ahub@70300000 { +- i2s@70301100 { +- status = "okay"; +- }; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- +- enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; +- power-supply = <&vdd_led>; +- pwms = <&pwm 1 1000000>; +- +- default-brightness-level = <224>; +- brightness-levels = +- < 0 1 2 3 4 5 6 7 +- 8 9 10 11 12 13 14 15 +- 16 17 18 19 20 21 22 23 +- 24 25 26 27 28 29 30 31 +- 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 +- 48 49 50 51 52 53 54 55 +- 56 57 58 59 60 61 62 63 +- 64 65 66 67 68 69 70 71 +- 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 +- 88 89 90 91 92 93 94 95 +- 96 97 98 99 100 101 102 103 +- 104 105 106 107 108 109 110 111 +- 112 113 114 115 116 117 118 119 +- 120 121 122 123 124 125 126 127 +- 128 129 130 131 132 133 134 135 +- 136 137 138 139 140 141 142 143 +- 144 145 146 147 148 149 150 151 +- 152 153 154 155 156 157 158 159 +- 160 161 162 163 164 165 166 167 +- 168 169 170 171 172 173 174 175 +- 176 177 178 179 180 181 182 183 +- 184 185 186 187 188 189 190 191 +- 192 193 194 195 196 197 198 199 +- 200 201 202 203 204 205 206 207 +- 208 209 210 211 212 213 214 215 +- 216 217 218 219 220 221 222 223 +- 224 225 226 227 228 229 230 231 +- 232 233 234 235 236 237 238 239 +- 240 241 242 243 244 245 246 247 +- 248 249 250 251 252 253 254 255 +- 256>; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- cpus { +- cpu@0 { +- vdd-cpu-supply = <&vdd_cpu>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- lid { +- label = "Lid"; +- gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; +- linux,input-type = <5>; +- linux,code = ; +- debounce-interval = <1>; +- wakeup-source; +- }; +- +- power { +- label = "Power"; +- gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <30>; +- wakeup-source; +- }; +- }; +- +- vdd_mux: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "+VDD_MUX"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_5v0_sys: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "+5V_SYS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_mux>; +- }; +- +- vdd_3v3_sys: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "+3.3V_SYS"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_mux>; +- }; +- +- vdd_3v3_run: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "+3.3V_RUN"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_3v3_sys>; +- }; +- +- vdd_3v3_hdmi: regulator@4 { +- compatible = "regulator-fixed"; +- regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vdd_3v3_run>; +- }; +- +- vdd_led: regulator@5 { +- compatible = "regulator-fixed"; +- regulator-name = "+VDD_LED"; +- gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_mux>; +- }; +- +- vdd_5v0_ts: regulator@6 { +- compatible = "regulator-fixed"; +- regulator-name = "+5V_VDD_TS_SW"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_usb1_vbus: regulator@7 { +- compatible = "regulator-fixed"; +- regulator-name = "+5V_USB_HS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- gpio-open-drain; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_usb3_vbus: regulator@8 { +- compatible = "regulator-fixed"; +- regulator-name = "+5V_USB_SS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- gpio-open-drain; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_3v3_panel: regulator@9 { +- compatible = "regulator-fixed"; +- regulator-name = "+3.3V_PANEL"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_3v3_run>; +- }; +- +- vdd_3v3_lp0: regulator@10 { +- compatible = "regulator-fixed"; +- regulator-name = "+3.3V_LP0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- /* +- * TODO: find a way to wire this up with the USB EHCI +- * controllers so that it can be enabled on demand. +- */ +- regulator-always-on; +- gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_3v3_sys>; +- }; +- +- vdd_hdmi_pll: regulator@11 { +- compatible = "regulator-fixed"; +- regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; +- vin-supply = <&vdd_1v05_run>; +- }; +- +- vdd_5v0_hdmi: regulator@12 { +- compatible = "regulator-fixed"; +- regulator-name = "+5V_HDMI_CON"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- sound { +- nvidia,audio-routing = +- "Headphones", "HPR", +- "Headphones", "HPL", +- "Speakers", "SPKR", +- "Speakers", "SPKL", +- "Mic Jack", "MICBIAS", +- "DMICL", "Int Mic", +- "DMICR", "Int Mic", +- "IN34", "Mic Jack"; +- +- nvidia,i2s-controller = <&tegra_i2s1>; +- nvidia,audio-codec = <&acodec>; +- +- clocks = <&tegra_car TEGRA124_CLK_PLL_A>, +- <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- +- assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- +- assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA124_CLK_EXTERN1>; +- +- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; +- nvidia,mic-det-gpios = +- <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; +- }; +- +- gpio-restart { +- compatible = "gpio-restart"; +- gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; +- priority = <200>; +- }; +-}; +- +-#include "cros-ec-keyboard.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/tegra124-peripherals-opp.dtsi b/scripts/dtc/include-prefixes/arm/tegra124-peripherals-opp.dtsi +deleted file mode 100644 +index 781ac8601030..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra124-peripherals-opp.dtsi ++++ /dev/null +@@ -1,424 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/ { +- emc_icc_dvfs_opp_table: emc-dvfs-opp-table { +- compatible = "operating-points-v2"; +- +- opp@12750000,800 { +- opp-microvolt = <800000 800000 1150000>; +- opp-hz = /bits/ 64 <12750000>; +- opp-supported-hw = <0x0003>; +- }; +- +- opp@12750000,950 { +- opp-microvolt = <950000 950000 1150000>; +- opp-hz = /bits/ 64 <12750000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@12750000,1050 { +- opp-microvolt = <1050000 1050000 1150000>; +- opp-hz = /bits/ 64 <12750000>; +- opp-supported-hw = <0x0010>; +- }; +- +- opp@12750000,1110 { +- opp-microvolt = <1110000 1110000 1150000>; +- opp-hz = /bits/ 64 <12750000>; +- opp-supported-hw = <0x0004>; +- }; +- +- opp@20400000,800 { +- opp-microvolt = <800000 800000 1150000>; +- opp-hz = /bits/ 64 <20400000>; +- opp-supported-hw = <0x0003>; +- }; +- +- opp@20400000,950 { +- opp-microvolt = <950000 950000 1150000>; +- opp-hz = /bits/ 64 <20400000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@20400000,1050 { +- opp-microvolt = <1050000 1050000 1150000>; +- opp-hz = /bits/ 64 <20400000>; +- opp-supported-hw = <0x0010>; +- }; +- +- opp@20400000,1110 { +- opp-microvolt = <1110000 1110000 1150000>; +- opp-hz = /bits/ 64 <20400000>; +- opp-supported-hw = <0x0004>; +- }; +- +- opp@40800000,800 { +- opp-microvolt = <800000 800000 1150000>; +- opp-hz = /bits/ 64 <40800000>; +- opp-supported-hw = <0x0003>; +- }; +- +- opp@40800000,950 { +- opp-microvolt = <950000 950000 1150000>; +- opp-hz = /bits/ 64 <40800000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@40800000,1050 { +- opp-microvolt = <1050000 1050000 1150000>; +- opp-hz = /bits/ 64 <40800000>; +- opp-supported-hw = <0x0010>; +- }; +- +- opp@40800000,1110 { +- opp-microvolt = <1110000 1110000 1150000>; +- opp-hz = /bits/ 64 <40800000>; +- opp-supported-hw = <0x0004>; +- }; +- +- opp@68000000,800 { +- opp-microvolt = <800000 800000 1150000>; +- opp-hz = /bits/ 64 <68000000>; +- opp-supported-hw = <0x0003>; +- }; +- +- opp@68000000,950 { +- opp-microvolt = <950000 950000 1150000>; +- opp-hz = /bits/ 64 <68000000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@68000000,1050 { +- opp-microvolt = <1050000 1050000 1150000>; +- opp-hz = /bits/ 64 <68000000>; +- opp-supported-hw = <0x0010>; +- }; +- +- opp@68000000,1110 { +- opp-microvolt = <1110000 1110000 1150000>; +- opp-hz = /bits/ 64 <68000000>; +- opp-supported-hw = <0x0004>; +- }; +- +- opp@102000000,800 { +- opp-microvolt = <800000 800000 1150000>; +- opp-hz = /bits/ 64 <102000000>; +- opp-supported-hw = <0x0003>; +- }; +- +- opp@102000000,950 { +- opp-microvolt = <950000 950000 1150000>; +- opp-hz = /bits/ 64 <102000000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@102000000,1050 { +- opp-microvolt = <1050000 1050000 1150000>; +- opp-hz = /bits/ 64 <102000000>; +- opp-supported-hw = <0x0010>; +- }; +- +- opp@102000000,1110 { +- opp-microvolt = <1110000 1110000 1150000>; +- opp-hz = /bits/ 64 <102000000>; +- opp-supported-hw = <0x0004>; +- }; +- +- opp@204000000,800 { +- opp-microvolt = <800000 800000 1150000>; +- opp-hz = /bits/ 64 <204000000>; +- opp-supported-hw = <0x0003>; +- opp-suspend; +- }; +- +- opp@204000000,950 { +- opp-microvolt = <950000 950000 1150000>; +- opp-hz = /bits/ 64 <204000000>; +- opp-supported-hw = <0x0008>; +- opp-suspend; +- }; +- +- opp@204000000,1050 { +- opp-microvolt = <1050000 1050000 1150000>; +- opp-hz = /bits/ 64 <204000000>; +- opp-supported-hw = <0x0010>; +- opp-suspend; +- }; +- +- opp@204000000,1110 { +- opp-microvolt = <1110000 1110000 1150000>; +- opp-hz = /bits/ 64 <204000000>; +- opp-supported-hw = <0x0004>; +- opp-suspend; +- }; +- +- opp@264000000,800 { +- opp-microvolt = <800000 800000 1150000>; +- opp-hz = /bits/ 64 <264000000>; +- opp-supported-hw = <0x0003>; +- }; +- +- opp@264000000,950 { +- opp-microvolt = <950000 950000 1150000>; +- opp-hz = /bits/ 64 <264000000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@264000000,1050 { +- opp-microvolt = <1050000 1050000 1150000>; +- opp-hz = /bits/ 64 <264000000>; +- opp-supported-hw = <0x0010>; +- }; +- +- opp@264000000,1110 { +- opp-microvolt = <1110000 1110000 1150000>; +- opp-hz = /bits/ 64 <264000000>; +- opp-supported-hw = <0x0004>; +- }; +- +- opp@300000000,850 { +- opp-microvolt = <850000 850000 1150000>; +- opp-hz = /bits/ 64 <300000000>; +- opp-supported-hw = <0x0003>; +- }; +- +- opp@300000000,950 { +- opp-microvolt = <950000 950000 1150000>; +- opp-hz = /bits/ 64 <300000000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@300000000,1050 { +- opp-microvolt = <1050000 1050000 1150000>; +- opp-hz = /bits/ 64 <300000000>; +- opp-supported-hw = <0x0010>; +- }; +- +- opp@300000000,1110 { +- opp-microvolt = <1110000 1110000 1150000>; +- opp-hz = /bits/ 64 <300000000>; +- opp-supported-hw = <0x0004>; +- }; +- +- opp@348000000,850 { +- opp-microvolt = <850000 850000 1150000>; +- opp-hz = /bits/ 64 <348000000>; +- opp-supported-hw = <0x0003>; +- }; +- +- opp@348000000,950 { +- opp-microvolt = <950000 950000 1150000>; +- opp-hz = /bits/ 64 <348000000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@348000000,1050 { +- opp-microvolt = <1050000 1050000 1150000>; +- opp-hz = /bits/ 64 <348000000>; +- opp-supported-hw = <0x0010>; +- }; +- +- opp@348000000,1110 { +- opp-microvolt = <1110000 1110000 1150000>; +- opp-hz = /bits/ 64 <348000000>; +- opp-supported-hw = <0x0004>; +- }; +- +- opp@396000000,950 { +- opp-microvolt = <950000 950000 1150000>; +- opp-hz = /bits/ 64 <396000000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@396000000,1000 { +- opp-microvolt = <1000000 1000000 1150000>; +- opp-hz = /bits/ 64 <396000000>; +- opp-supported-hw = <0x0003>; +- }; +- +- opp@396000000,1050 { +- opp-microvolt = <1050000 1050000 1150000>; +- opp-hz = /bits/ 64 <396000000>; +- opp-supported-hw = <0x0010>; +- }; +- +- opp@396000000,1110 { +- opp-microvolt = <1110000 1110000 1150000>; +- opp-hz = /bits/ 64 <396000000>; +- opp-supported-hw = <0x0004>; +- }; +- +- opp@528000000,950 { +- opp-microvolt = <950000 950000 1150000>; +- opp-hz = /bits/ 64 <528000000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@528000000,1000 { +- opp-microvolt = <1000000 1000000 1150000>; +- opp-hz = /bits/ 64 <528000000>; +- opp-supported-hw = <0x0003>; +- }; +- +- opp@528000000,1050 { +- opp-microvolt = <1050000 1050000 1150000>; +- opp-hz = /bits/ 64 <528000000>; +- opp-supported-hw = <0x0010>; +- }; +- +- opp@528000000,1110 { +- opp-microvolt = <1110000 1110000 1150000>; +- opp-hz = /bits/ 64 <528000000>; +- opp-supported-hw = <0x0004>; +- }; +- +- opp@600000000,950 { +- opp-microvolt = <950000 950000 1150000>; +- opp-hz = /bits/ 64 <600000000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@600000000,1000 { +- opp-microvolt = <1000000 1000000 1150000>; +- opp-hz = /bits/ 64 <600000000>; +- opp-supported-hw = <0x0003>; +- }; +- +- opp@600000000,1050 { +- opp-microvolt = <1050000 1050000 1150000>; +- opp-hz = /bits/ 64 <600000000>; +- opp-supported-hw = <0x0010>; +- }; +- +- opp@600000000,1110 { +- opp-microvolt = <1110000 1110000 1150000>; +- opp-hz = /bits/ 64 <600000000>; +- opp-supported-hw = <0x0004>; +- }; +- +- opp@792000000,1000 { +- opp-microvolt = <1000000 1000000 1150000>; +- opp-hz = /bits/ 64 <792000000>; +- opp-supported-hw = <0x000B>; +- }; +- +- opp@792000000,1050 { +- opp-microvolt = <1050000 1050000 1150000>; +- opp-hz = /bits/ 64 <792000000>; +- opp-supported-hw = <0x0010>; +- }; +- +- opp@792000000,1110 { +- opp-microvolt = <1110000 1110000 1150000>; +- opp-hz = /bits/ 64 <792000000>; +- opp-supported-hw = <0x0004>; +- }; +- +- opp@924000000,1100 { +- opp-microvolt = <1100000 1100000 1150000>; +- opp-hz = /bits/ 64 <924000000>; +- opp-supported-hw = <0x0013>; +- }; +- +- opp@1200000000,1100 { +- opp-microvolt = <1100000 1100000 1150000>; +- opp-hz = /bits/ 64 <1200000000>; +- opp-supported-hw = <0x0003>; +- }; +- }; +- +- emc_bw_dfs_opp_table: emc-bandwidth-opp-table { +- compatible = "operating-points-v2"; +- +- opp@12750000 { +- opp-hz = /bits/ 64 <12750000>; +- opp-supported-hw = <0x001F>; +- opp-peak-kBps = <204000>; +- }; +- +- opp@20400000 { +- opp-hz = /bits/ 64 <20400000>; +- opp-supported-hw = <0x001F>; +- opp-peak-kBps = <326400>; +- }; +- +- opp@40800000 { +- opp-hz = /bits/ 64 <40800000>; +- opp-supported-hw = <0x001F>; +- opp-peak-kBps = <652800>; +- }; +- +- opp@68000000 { +- opp-hz = /bits/ 64 <68000000>; +- opp-supported-hw = <0x001F>; +- opp-peak-kBps = <1088000>; +- }; +- +- opp@102000000 { +- opp-hz = /bits/ 64 <102000000>; +- opp-supported-hw = <0x001F>; +- opp-peak-kBps = <1632000>; +- }; +- +- opp@204000000 { +- opp-hz = /bits/ 64 <204000000>; +- opp-supported-hw = <0x001F>; +- opp-peak-kBps = <3264000>; +- opp-suspend; +- }; +- +- opp@264000000 { +- opp-hz = /bits/ 64 <264000000>; +- opp-supported-hw = <0x001F>; +- opp-peak-kBps = <4224000>; +- }; +- +- opp@300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-supported-hw = <0x001F>; +- opp-peak-kBps = <4800000>; +- }; +- +- opp@348000000 { +- opp-hz = /bits/ 64 <348000000>; +- opp-supported-hw = <0x001F>; +- opp-peak-kBps = <5568000>; +- }; +- +- opp@396000000 { +- opp-hz = /bits/ 64 <396000000>; +- opp-supported-hw = <0x001F>; +- opp-peak-kBps = <6336000>; +- }; +- +- opp@528000000 { +- opp-hz = /bits/ 64 <528000000>; +- opp-supported-hw = <0x001F>; +- opp-peak-kBps = <8448000>; +- }; +- +- opp@600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-supported-hw = <0x001F>; +- opp-peak-kBps = <9600000>; +- }; +- +- opp@792000000 { +- opp-hz = /bits/ 64 <792000000>; +- opp-supported-hw = <0x001F>; +- opp-peak-kBps = <12672000>; +- }; +- +- opp@924000000 { +- opp-hz = /bits/ 64 <924000000>; +- opp-supported-hw = <0x0013>; +- opp-peak-kBps = <14784000>; +- }; +- +- opp@1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-supported-hw = <0x0003>; +- opp-peak-kBps = <19200000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra124-venice2.dts b/scripts/dtc/include-prefixes/arm/tegra124-venice2.dts +deleted file mode 100644 +index 84e2d24065e9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra124-venice2.dts ++++ /dev/null +@@ -1,1254 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include "tegra124.dtsi" +- +-/ { +- model = "NVIDIA Tegra124 Venice2"; +- compatible = "nvidia,venice2", "nvidia,tegra124"; +- +- aliases { +- rtc0 = "/i2c@7000d000/pmic@40"; +- rtc1 = "/rtc@7000e000"; +- serial0 = &uarta; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@80000000 { +- reg = <0x0 0x80000000 0x0 0x80000000>; +- }; +- +- host1x@50000000 { +- hdmi@54280000 { +- status = "okay"; +- +- vdd-supply = <&vdd_3v3_hdmi>; +- pll-supply = <&vdd_hdmi_pll>; +- hdmi-supply = <&vdd_5v0_hdmi>; +- +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = +- <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; +- }; +- +- sor@54540000 { +- status = "okay"; +- +- avdd-io-hdmi-dp-supply = <&vdd_1v05_run>; +- vdd-hdmi-dp-pll-supply = <&vdd_3v3_run>; +- +- nvidia,dpaux = <&dpaux>; +- nvidia,panel = <&panel>; +- }; +- +- dpaux@545c0000 { +- vdd-supply = <&vdd_3v3_panel>; +- status = "okay"; +- +- aux-bus { +- panel: panel { +- compatible = "lg,lp129qe"; +- backlight = <&backlight>; +- }; +- }; +- }; +- }; +- +- gpu@0,57000000 { +- /* +- * Node left disabled on purpose - the bootloader will enable +- * it after having set the VPR up +- */ +- vdd-supply = <&vdd_gpu>; +- }; +- +- pinmux: pinmux@70000868 { +- pinctrl-names = "boot"; +- pinctrl-0 = <&pinmux_boot>; +- +- pinmux_boot: common { +- dap_mclk1_pw4 { +- nvidia,pins = "dap_mclk1_pw4"; +- nvidia,function = "extperiph1"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- dap1_din_pn1 { +- nvidia,pins = "dap1_din_pn1"; +- nvidia,function = "i2s0"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- dap1_dout_pn2 { +- nvidia,pins = "dap1_dout_pn2", +- "dap1_fs_pn0", +- "dap1_sclk_pn3"; +- nvidia,function = "i2s0"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- dap2_din_pa4 { +- nvidia,pins = "dap2_din_pa4"; +- nvidia,function = "i2s1"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- dap2_dout_pa5 { +- nvidia,pins = "dap2_dout_pa5", +- "dap2_fs_pa2", +- "dap2_sclk_pa3"; +- nvidia,function = "i2s1"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- dvfs_pwm_px0 { +- nvidia,pins = "dvfs_pwm_px0", +- "dvfs_clk_px2"; +- nvidia,function = "cldvfs"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- ulpi_clk_py0 { +- nvidia,pins = "ulpi_clk_py0", +- "ulpi_nxt_py2", +- "ulpi_stp_py3"; +- nvidia,function = "spi1"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- ulpi_dir_py1 { +- nvidia,pins = "ulpi_dir_py1"; +- nvidia,function = "spi1"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- cam_i2c_scl_pbb1 { +- nvidia,pins = "cam_i2c_scl_pbb1", +- "cam_i2c_sda_pbb2"; +- nvidia,function = "i2c3"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- gen2_i2c_scl_pt5 { +- nvidia,pins = "gen2_i2c_scl_pt5", +- "gen2_i2c_sda_pt6"; +- nvidia,function = "i2c2"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- pg4 { +- nvidia,pins = "pg4", +- "pg5", +- "pg6", +- "pi3"; +- nvidia,function = "spi4"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- pg7 { +- nvidia,pins = "pg7"; +- nvidia,function = "spi4"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- ph1 { +- nvidia,pins = "ph1"; +- nvidia,function = "pwm1"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- pk0 { +- nvidia,pins = "pk0", +- "kb_row15_ps7", +- "clk_32k_out_pa0"; +- nvidia,function = "soc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_clk_pz0 { +- nvidia,pins = "sdmmc1_clk_pz0"; +- nvidia,function = "sdmmc1"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- sdmmc1_cmd_pz1 { +- nvidia,pins = "sdmmc1_cmd_pz1", +- "sdmmc1_dat0_py7", +- "sdmmc1_dat1_py6", +- "sdmmc1_dat2_py5", +- "sdmmc1_dat3_py4"; +- nvidia,function = "sdmmc1"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- sdmmc3_clk_pa6 { +- nvidia,pins = "sdmmc3_clk_pa6"; +- nvidia,function = "sdmmc3"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- sdmmc3_cmd_pa7 { +- nvidia,pins = "sdmmc3_cmd_pa7", +- "sdmmc3_dat0_pb7", +- "sdmmc3_dat1_pb6", +- "sdmmc3_dat2_pb5", +- "sdmmc3_dat3_pb4", +- "sdmmc3_clk_lb_out_pee4", +- "sdmmc3_clk_lb_in_pee5"; +- nvidia,function = "sdmmc3"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- sdmmc4_clk_pcc4 { +- nvidia,pins = "sdmmc4_clk_pcc4"; +- nvidia,function = "sdmmc4"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- sdmmc4_cmd_pt7 { +- nvidia,pins = "sdmmc4_cmd_pt7", +- "sdmmc4_dat0_paa0", +- "sdmmc4_dat1_paa1", +- "sdmmc4_dat2_paa2", +- "sdmmc4_dat3_paa3", +- "sdmmc4_dat4_paa4", +- "sdmmc4_dat5_paa5", +- "sdmmc4_dat6_paa6", +- "sdmmc4_dat7_paa7"; +- nvidia,function = "sdmmc4"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- pwr_i2c_scl_pz6 { +- nvidia,pins = "pwr_i2c_scl_pz6", +- "pwr_i2c_sda_pz7"; +- nvidia,function = "i2cpwr"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- jtag_rtck { +- nvidia,pins = "jtag_rtck"; +- nvidia,function = "rtck"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- clk_32k_in { +- nvidia,pins = "clk_32k_in"; +- nvidia,function = "clk"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- core_pwr_req { +- nvidia,pins = "core_pwr_req"; +- nvidia,function = "pwron"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- cpu_pwr_req { +- nvidia,pins = "cpu_pwr_req"; +- nvidia,function = "cpu"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- pwr_int_n { +- nvidia,pins = "pwr_int_n"; +- nvidia,function = "pmi"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- reset_out_n { +- nvidia,pins = "reset_out_n"; +- nvidia,function = "reset_out_n"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- clk3_out_pee0 { +- nvidia,pins = "clk3_out_pee0"; +- nvidia,function = "extperiph3"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- dap4_din_pp5 { +- nvidia,pins = "dap4_din_pp5"; +- nvidia,function = "i2s3"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- dap4_dout_pp6 { +- nvidia,pins = "dap4_dout_pp6", +- "dap4_fs_pp4", +- "dap4_sclk_pp7"; +- nvidia,function = "i2s3"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- gen1_i2c_sda_pc5 { +- nvidia,pins = "gen1_i2c_sda_pc5", +- "gen1_i2c_scl_pc4"; +- nvidia,function = "i2c1"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- uart2_cts_n_pj5 { +- nvidia,pins = "uart2_cts_n_pj5"; +- nvidia,function = "uartb"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- uart2_rts_n_pj6 { +- nvidia,pins = "uart2_rts_n_pj6"; +- nvidia,function = "uartb"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- uart2_rxd_pc3 { +- nvidia,pins = "uart2_rxd_pc3"; +- nvidia,function = "irda"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- uart2_txd_pc2 { +- nvidia,pins = "uart2_txd_pc2"; +- nvidia,function = "irda"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- uart3_cts_n_pa1 { +- nvidia,pins = "uart3_cts_n_pa1", +- "uart3_rxd_pw7"; +- nvidia,function = "uartc"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- uart3_rts_n_pc0 { +- nvidia,pins = "uart3_rts_n_pc0", +- "uart3_txd_pw6"; +- nvidia,function = "uartc"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- hdmi_cec_pee3 { +- nvidia,pins = "hdmi_cec_pee3"; +- nvidia,function = "cec"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- hdmi_int_pn7 { +- nvidia,pins = "hdmi_int_pn7"; +- nvidia,function = "rsvd1"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- ddc_scl_pv4 { +- nvidia,pins = "ddc_scl_pv4", +- "ddc_sda_pv5"; +- nvidia,function = "i2c4"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,lock = ; +- nvidia,rcv-sel = ; +- }; +- pj7 { +- nvidia,pins = "pj7", +- "pk7"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pb0 { +- nvidia,pins = "pb0", +- "pb1"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph0 { +- nvidia,pins = "ph0"; +- nvidia,function = "pwm0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row10_ps2 { +- nvidia,pins = "kb_row10_ps2"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row9_ps1 { +- nvidia,pins = "kb_row9_ps1"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row6_pr6 { +- nvidia,pins = "kb_row6_pr6"; +- nvidia,function = "displaya_alt"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- usb_vbus_en0_pn4 { +- nvidia,pins = "usb_vbus_en0_pn4", +- "usb_vbus_en1_pn5"; +- nvidia,function = "usb"; +- nvidia,enable-input = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- drive_sdio1 { +- nvidia,pins = "drive_sdio1"; +- nvidia,high-speed-mode = ; +- nvidia,schmitt = ; +- nvidia,pull-down-strength = <32>; +- nvidia,pull-up-strength = <42>; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- }; +- drive_sdio3 { +- nvidia,pins = "drive_sdio3"; +- nvidia,high-speed-mode = ; +- nvidia,schmitt = ; +- nvidia,pull-down-strength = <20>; +- nvidia,pull-up-strength = <36>; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- }; +- drive_gma { +- nvidia,pins = "drive_gma"; +- nvidia,high-speed-mode = ; +- nvidia,schmitt = ; +- nvidia,low-power-mode = ; +- nvidia,pull-down-strength = <1>; +- nvidia,pull-up-strength = <2>; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- nvidia,drive-type = <1>; +- }; +- als_irq_l { +- nvidia,pins = "gpio_x3_aud_px3"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- codec_irq_l { +- nvidia,pins = "ph4"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_bl_en { +- nvidia,pins = "ph2"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- touch_irq_l { +- nvidia,pins = "gpio_w3_aud_pw3"; +- nvidia,function = "spi6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- tpm_davint_l { +- nvidia,pins = "ph6"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ts_irq_l { +- nvidia,pins = "pk2"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ts_reset_l { +- nvidia,pins = "pk4"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ts_shdn_l { +- nvidia,pins = "pk1"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph7 { +- nvidia,pins = "ph7"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col0_ap { +- nvidia,pins = "kb_col0_pq0"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lid_open { +- nvidia,pins = "kb_row4_pr4"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- en_vdd_sd { +- nvidia,pins = "kb_row0_pr0"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ac_ok { +- nvidia,pins = "pj0"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sensor_irq_l { +- nvidia,pins = "pi6"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- wifi_en { +- nvidia,pins = "gpio_x7_aud_px7"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- wifi_rst_l { +- nvidia,pins = "clk2_req_pcc5"; +- nvidia,function = "dap"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- hp_det_l { +- nvidia,pins = "ulpi_data1_po2"; +- nvidia,function = "spi3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- }; +- }; +- +- serial@70006000 { +- status = "okay"; +- }; +- +- pwm@7000a000 { +- status = "okay"; +- }; +- +- i2c@7000c000 { +- status = "okay"; +- clock-frequency = <100000>; +- +- acodec: audio-codec@10 { +- compatible = "maxim,max98090"; +- reg = <0x10>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- }; +- }; +- +- i2c@7000c400 { +- status = "okay"; +- clock-frequency = <100000>; +- +- trackpad@4b { +- compatible = "atmel,maxtouch"; +- reg = <0x4b>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- linux,gpio-keymap = <0 0 0 BTN_LEFT>; +- }; +- }; +- +- i2c@7000c500 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- hdmi_ddc: i2c@7000c700 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- pmic: pmic@40 { +- compatible = "ams,as3722"; +- reg = <0x40>; +- interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; +- +- ams,system-power-controller; +- +- #interrupt-cells = <2>; +- interrupt-controller; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&as3722_default>; +- +- as3722_default: pinmux { +- gpio0 { +- pins = "gpio0"; +- function = "gpio"; +- bias-pull-down; +- }; +- +- gpio1_2_4_7 { +- pins = "gpio1", "gpio2", "gpio4", "gpio7"; +- function = "gpio"; +- bias-pull-up; +- }; +- +- gpio3_6 { +- pins = "gpio3", "gpio6"; +- bias-high-impedance; +- }; +- +- gpio5 { +- pins = "gpio5"; +- function = "clk32k-out"; +- }; +- }; +- +- regulators { +- vsup-sd2-supply = <&vdd_5v0_sys>; +- vsup-sd3-supply = <&vdd_5v0_sys>; +- vsup-sd4-supply = <&vdd_5v0_sys>; +- vsup-sd5-supply = <&vdd_5v0_sys>; +- vin-ldo0-supply = <&vdd_1v35_lp0>; +- vin-ldo1-6-supply = <&vdd_3v3_run>; +- vin-ldo2-5-7-supply = <&vddio_1v8>; +- vin-ldo3-4-supply = <&vdd_3v3_sys>; +- vin-ldo9-10-supply = <&vdd_5v0_sys>; +- vin-ldo11-supply = <&vdd_3v3_run>; +- +- sd0 { +- regulator-name = "+VDD_CPU_AP"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1400000>; +- regulator-min-microamp = <3500000>; +- regulator-max-microamp = <3500000>; +- regulator-always-on; +- regulator-boot-on; +- ams,ext-control = <2>; +- }; +- +- sd1 { +- regulator-name = "+VDD_CORE"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-min-microamp = <2500000>; +- regulator-max-microamp = <2500000>; +- regulator-always-on; +- regulator-boot-on; +- ams,ext-control = <1>; +- }; +- +- vdd_1v35_lp0: sd2 { +- regulator-name = "+1.35V_LP0(sd2)"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- sd3 { +- regulator-name = "+1.35V_LP0(sd3)"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v05_run: sd4 { +- regulator-name = "+1.05V_RUN"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- vddio_1v8: sd5 { +- regulator-name = "+1.8V_VDDIO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vdd_gpu: sd6 { +- regulator-name = "+VDD_GPU_AP"; +- regulator-min-microvolt = <650000>; +- regulator-max-microvolt = <1200000>; +- regulator-min-microamp = <3500000>; +- regulator-max-microamp = <3500000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- avdd_1v05_run: ldo0 { +- regulator-name = "+1.05V_RUN_AVDD"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-boot-on; +- regulator-always-on; +- ams,ext-control = <1>; +- }; +- +- ldo1 { +- regulator-name = "+1.8V_RUN_CAM"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo2 { +- regulator-name = "+1.2V_GEN_AVDD"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo3 { +- regulator-name = "+1.00V_LP0_VDD_RTC"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-boot-on; +- regulator-always-on; +- ams,enable-tracking; +- }; +- +- vdd_run_cam: ldo4 { +- regulator-name = "+3.3V_RUN_CAM"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo5 { +- regulator-name = "+1.2V_RUN_CAM_FRONT"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- vddio_sdmmc3: ldo6 { +- regulator-name = "+VDDIO_SDMMC3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo7 { +- regulator-name = "+1.05V_RUN_CAM_REAR"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- ldo9 { +- regulator-name = "+2.8V_RUN_TOUCH"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo10 { +- regulator-name = "+2.8V_RUN_CAM_AF"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo11 { +- regulator-name = "+1.8V_RUN_VPP_FUSE"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- }; +- }; +- }; +- +- spi@7000d400 { +- status = "okay"; +- +- cros_ec: cros-ec@0 { +- compatible = "google,cros-ec-spi"; +- spi-max-frequency = <4000000>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- reg = <0>; +- +- google,cros-ec-spi-msg-delay = <2000>; +- +- i2c-tunnel { +- compatible = "google,cros-ec-i2c-tunnel"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- google,remote-bus = <0>; +- +- charger: bq24735@9 { +- compatible = "ti,bq24735"; +- reg = <0x9>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- ti,ac-detect-gpios = <&gpio +- TEGRA_GPIO(J, 0) +- GPIO_ACTIVE_HIGH>; +- }; +- +- battery: sbs-battery@b { +- compatible = "sbs,sbs-battery"; +- reg = <0xb>; +- sbs,i2c-retry-count = <2>; +- sbs,poll-retry-count = <1>; +- }; +- }; +- }; +- }; +- +- spi@7000da00 { +- status = "okay"; +- spi-max-frequency = <25000000>; +- spi-flash@0 { +- compatible = "winbond,w25q32dw", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- }; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <500>; +- nvidia,cpu-pwr-off-time = <300>; +- nvidia,core-pwr-good-time = <641 3845>; +- nvidia,core-pwr-off-time = <61036>; +- nvidia,core-power-req-active-high; +- nvidia,sys-clock-req-active-high; +- }; +- +- hda@70030000 { +- status = "okay"; +- }; +- +- usb@70090000 { +- phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ +- <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ +- <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ +- phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; +- +- avddio-pex-supply = <&vdd_1v05_run>; +- dvddio-pex-supply = <&vdd_1v05_run>; +- avdd-usb-supply = <&vdd_3v3_lp0>; +- avdd-pll-utmip-supply = <&vddio_1v8>; +- avdd-pll-erefe-supply = <&avdd_1v05_run>; +- avdd-usb-ss-pll-supply = <&vdd_1v05_run>; +- hvdd-usb-ss-supply = <&vdd_3v3_lp0>; +- hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; +- +- status = "okay"; +- }; +- +- padctl@7009f000 { +- avdd-pll-utmip-supply = <&vddio_1v8>; +- avdd-pll-erefe-supply = <&avdd_1v05_run>; +- avdd-pex-pll-supply = <&vdd_1v05_run>; +- hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; +- +- pads { +- usb2 { +- status = "okay"; +- +- lanes { +- usb2-0 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- +- usb2-1 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- +- usb2-2 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- }; +- }; +- +- pcie { +- status = "okay"; +- +- lanes { +- pcie-0 { +- nvidia,function = "usb3-ss"; +- status = "okay"; +- }; +- +- pcie-1 { +- nvidia,function = "usb3-ss"; +- status = "okay"; +- }; +- }; +- }; +- }; +- +- ports { +- usb2-0 { +- status = "okay"; +- mode = "otg"; +- +- vbus-supply = <&vdd_usb1_vbus>; +- }; +- +- usb2-1 { +- status = "okay"; +- mode = "host"; +- +- vbus-supply = <&vdd_run_cam>; +- }; +- +- usb2-2 { +- status = "okay"; +- mode = "host"; +- +- vbus-supply = <&vdd_usb3_vbus>; +- }; +- +- usb3-0 { +- nvidia,usb2-companion = <0>; +- status = "okay"; +- }; +- +- usb3-1 { +- nvidia,usb2-companion = <2>; +- status = "okay"; +- }; +- }; +- }; +- +- mmc@700b0400 { +- cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; +- power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; +- wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; +- status = "okay"; +- bus-width = <4>; +- vqmmc-supply = <&vddio_sdmmc3>; +- }; +- +- mmc@700b0600 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- }; +- +- ahub@70300000 { +- i2s@70301100 { +- status = "okay"; +- }; +- }; +- +- usb@7d000000 { +- status = "okay"; +- }; +- +- usb-phy@7d000000 { +- status = "okay"; +- vbus-supply = <&vdd_usb1_vbus>; +- }; +- +- usb@7d004000 { +- status = "okay"; +- }; +- +- usb-phy@7d004000 { +- status = "okay"; +- vbus-supply = <&vdd_run_cam>; +- }; +- +- usb@7d008000 { +- status = "okay"; +- }; +- +- usb-phy@7d008000 { +- status = "okay"; +- vbus-supply = <&vdd_usb3_vbus>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- +- enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; +- power-supply = <&vdd_led>; +- pwms = <&pwm 1 1000000>; +- +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "Power"; +- gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- vdd_mux: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "+VDD_MUX"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_5v0_sys: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "+5V_SYS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_mux>; +- }; +- +- vdd_3v3_sys: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "+3.3V_SYS"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_mux>; +- }; +- +- vdd_3v3_run: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "+3.3V_RUN"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_3v3_sys>; +- }; +- +- vdd_3v3_hdmi: regulator@4 { +- compatible = "regulator-fixed"; +- regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vdd_3v3_run>; +- }; +- +- vdd_led: regulator@5 { +- compatible = "regulator-fixed"; +- regulator-name = "+VDD_LED"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_mux>; +- }; +- +- vdd_5v0_ts: regulator@6 { +- compatible = "regulator-fixed"; +- regulator-name = "+5V_VDD_TS_SW"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_usb1_vbus: regulator@7 { +- compatible = "regulator-fixed"; +- regulator-name = "+5V_USB_HS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- gpio-open-drain; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_usb3_vbus: regulator@8 { +- compatible = "regulator-fixed"; +- regulator-name = "+5V_USB_SS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- gpio-open-drain; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_3v3_panel: regulator@9 { +- compatible = "regulator-fixed"; +- regulator-name = "+3.3V_PANEL"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_3v3_run>; +- }; +- +- vdd_3v3_lp0: regulator@10 { +- compatible = "regulator-fixed"; +- regulator-name = "+3.3V_LP0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- /* +- * TODO: find a way to wire this up with the USB EHCI +- * controllers so that it can be enabled on demand. +- */ +- regulator-always-on; +- gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_3v3_sys>; +- }; +- +- vdd_hdmi_pll: regulator@11 { +- compatible = "regulator-fixed"; +- regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; +- vin-supply = <&vdd_1v05_run>; +- }; +- +- vdd_5v0_hdmi: regulator@12 { +- compatible = "regulator-fixed"; +- regulator-name = "+5V_HDMI_CON"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- sound { +- compatible = "nvidia,tegra-audio-max98090-venice2", +- "nvidia,tegra-audio-max98090"; +- nvidia,model = "NVIDIA Tegra Venice2"; +- +- nvidia,audio-routing = +- "Headphones", "HPR", +- "Headphones", "HPL", +- "Speakers", "SPKR", +- "Speakers", "SPKL", +- "Mic Jack", "MICBIAS", +- "IN34", "Mic Jack"; +- +- nvidia,i2s-controller = <&tegra_i2s1>; +- nvidia,audio-codec = <&acodec>; +- +- clocks = <&tegra_car TEGRA124_CLK_PLL_A>, +- <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- +- assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- +- assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA124_CLK_EXTERN1>; +- }; +-}; +- +-#include "cros-ec-keyboard.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/tegra124.dtsi b/scripts/dtc/include-prefixes/arm/tegra124.dtsi +deleted file mode 100644 +index 8b38f123f554..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra124.dtsi ++++ /dev/null +@@ -1,1369 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include "tegra124-peripherals-opp.dtsi" +- +-/ { +- compatible = "nvidia,tegra124"; +- interrupt-parent = <&lic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0x0>; +- }; +- +- pcie@1003000 { +- compatible = "nvidia,tegra124-pcie"; +- device_type = "pci"; +- reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ +- <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ +- <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ +- reg-names = "pads", "afi", "cs"; +- interrupts = , /* controller interrupt */ +- ; /* MSI interrupt */ +- interrupt-names = "intr", "msi"; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; +- +- bus-range = <0x00 0xff>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ +- <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ +- <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ +- <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ +- <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ +- +- clocks = <&tegra_car TEGRA124_CLK_PCIE>, +- <&tegra_car TEGRA124_CLK_AFI>, +- <&tegra_car TEGRA124_CLK_PLL_E>, +- <&tegra_car TEGRA124_CLK_CML0>; +- clock-names = "pex", "afi", "pll_e", "cml"; +- resets = <&tegra_car 70>, +- <&tegra_car 72>, +- <&tegra_car 74>; +- reset-names = "pex", "afi", "pcie_x"; +- status = "disabled"; +- +- pci@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; +- reg = <0x000800 0 0 0 0>; +- bus-range = <0x00 0xff>; +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- ranges; +- +- nvidia,num-lanes = <2>; +- }; +- +- pci@2,0 { +- device_type = "pci"; +- assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; +- reg = <0x001000 0 0 0 0>; +- bus-range = <0x00 0xff>; +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- ranges; +- +- nvidia,num-lanes = <1>; +- }; +- }; +- +- host1x@50000000 { +- compatible = "nvidia,tegra124-host1x"; +- reg = <0x0 0x50000000 0x0 0x00034000>; +- interrupts = , /* syncpt */ +- ; /* general */ +- interrupt-names = "syncpt", "host1x"; +- clocks = <&tegra_car TEGRA124_CLK_HOST1X>; +- clock-names = "host1x"; +- resets = <&tegra_car 28>; +- reset-names = "host1x"; +- iommus = <&mc TEGRA_SWGROUP_HC>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; +- +- dc@54200000 { +- compatible = "nvidia,tegra124-dc"; +- reg = <0x0 0x54200000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_DISP1>; +- clock-names = "dc"; +- resets = <&tegra_car 27>; +- reset-names = "dc"; +- +- iommus = <&mc TEGRA_SWGROUP_DC>; +- +- nvidia,head = <0>; +- +- interconnects = <&mc TEGRA124_MC_DISPLAY0A &emc>, +- <&mc TEGRA124_MC_DISPLAY0B &emc>, +- <&mc TEGRA124_MC_DISPLAY0C &emc>, +- <&mc TEGRA124_MC_DISPLAYHC &emc>, +- <&mc TEGRA124_MC_DISPLAYD &emc>, +- <&mc TEGRA124_MC_DISPLAYT &emc>; +- interconnect-names = "wina", +- "winb", +- "winc", +- "cursor", +- "wind", +- "wint"; +- }; +- +- dc@54240000 { +- compatible = "nvidia,tegra124-dc"; +- reg = <0x0 0x54240000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_DISP2>; +- clock-names = "dc"; +- resets = <&tegra_car 26>; +- reset-names = "dc"; +- +- iommus = <&mc TEGRA_SWGROUP_DCB>; +- +- nvidia,head = <1>; +- +- interconnects = <&mc TEGRA124_MC_DISPLAY0AB &emc>, +- <&mc TEGRA124_MC_DISPLAY0BB &emc>, +- <&mc TEGRA124_MC_DISPLAY0CB &emc>, +- <&mc TEGRA124_MC_DISPLAYHCB &emc>; +- interconnect-names = "wina", +- "winb", +- "winc", +- "cursor"; +- }; +- +- hdmi: hdmi@54280000 { +- compatible = "nvidia,tegra124-hdmi"; +- reg = <0x0 0x54280000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_HDMI>, +- <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; +- clock-names = "hdmi", "parent"; +- resets = <&tegra_car 51>; +- reset-names = "hdmi"; +- status = "disabled"; +- }; +- +- vic@54340000 { +- compatible = "nvidia,tegra124-vic"; +- reg = <0x0 0x54340000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_VIC03>; +- clock-names = "vic"; +- resets = <&tegra_car 178>; +- reset-names = "vic"; +- +- iommus = <&mc TEGRA_SWGROUP_VIC>; +- }; +- +- sor@54540000 { +- compatible = "nvidia,tegra124-sor"; +- reg = <0x0 0x54540000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_SOR0>, +- <&tegra_car TEGRA124_CLK_SOR0_OUT>, +- <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, +- <&tegra_car TEGRA124_CLK_PLL_DP>, +- <&tegra_car TEGRA124_CLK_CLK_M>; +- clock-names = "sor", "out", "parent", "dp", "safe"; +- resets = <&tegra_car 182>; +- reset-names = "sor"; +- status = "disabled"; +- }; +- +- dpaux: dpaux@545c0000 { +- compatible = "nvidia,tegra124-dpaux"; +- reg = <0x0 0x545c0000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_DPAUX>, +- <&tegra_car TEGRA124_CLK_PLL_DP>; +- clock-names = "dpaux", "parent"; +- resets = <&tegra_car 181>; +- reset-names = "dpaux"; +- status = "disabled"; +- +- i2c-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- }; +- +- gic: interrupt-controller@50041000 { +- compatible = "arm,cortex-a15-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x0 0x50041000 0x0 0x1000>, +- <0x0 0x50042000 0x0 0x1000>, +- <0x0 0x50044000 0x0 0x2000>, +- <0x0 0x50046000 0x0 0x2000>; +- interrupts = ; +- interrupt-parent = <&gic>; +- }; +- +- /* +- * Please keep the following 0, notation in place as a former mainline +- * U-Boot version was looking for that particular notation in order to +- * perform required fix-ups on that GPU node. +- */ +- gpu@0,57000000 { +- compatible = "nvidia,gk20a"; +- reg = <0x0 0x57000000 0x0 0x01000000>, +- <0x0 0x58000000 0x0 0x01000000>; +- interrupts = , +- ; +- interrupt-names = "stall", "nonstall"; +- clocks = <&tegra_car TEGRA124_CLK_GPU>, +- <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; +- clock-names = "gpu", "pwr"; +- resets = <&tegra_car 184>; +- reset-names = "gpu"; +- +- iommus = <&mc TEGRA_SWGROUP_GPU>; +- +- status = "disabled"; +- }; +- +- lic: interrupt-controller@60004000 { +- compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; +- reg = <0x0 0x60004000 0x0 0x100>, +- <0x0 0x60004100 0x0 0x100>, +- <0x0 0x60004200 0x0 0x100>, +- <0x0 0x60004300 0x0 0x100>, +- <0x0 0x60004400 0x0 0x100>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- }; +- +- timer@60005000 { +- compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; +- reg = <0x0 0x60005000 0x0 0x400>; +- interrupts = , +- , +- , +- , +- , +- ; +- clocks = <&tegra_car TEGRA124_CLK_TIMER>; +- }; +- +- tegra_car: clock@60006000 { +- compatible = "nvidia,tegra124-car"; +- reg = <0x0 0x60006000 0x0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- nvidia,external-memory-controller = <&emc>; +- }; +- +- flow-controller@60007000 { +- compatible = "nvidia,tegra124-flowctrl"; +- reg = <0x0 0x60007000 0x0 0x1000>; +- }; +- +- actmon: actmon@6000c800 { +- compatible = "nvidia,tegra124-actmon"; +- reg = <0x0 0x6000c800 0x0 0x400>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_ACTMON>, +- <&tegra_car TEGRA124_CLK_EMC>; +- clock-names = "actmon", "emc"; +- resets = <&tegra_car 119>; +- reset-names = "actmon"; +- operating-points-v2 = <&emc_bw_dfs_opp_table>; +- interconnects = <&mc TEGRA124_MC_MPCORER &emc>; +- interconnect-names = "cpu-read"; +- #cooling-cells = <2>; +- }; +- +- gpio: gpio@6000d000 { +- compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; +- reg = <0x0 0x6000d000 0x0 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- #gpio-cells = <2>; +- gpio-controller; +- #interrupt-cells = <2>; +- interrupt-controller; +- /* +- gpio-ranges = <&pinmux 0 0 251>; +- */ +- }; +- +- apbdma: dma@60020000 { +- compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; +- reg = <0x0 0x60020000 0x0 0x1400>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&tegra_car TEGRA124_CLK_APBDMA>; +- resets = <&tegra_car 34>; +- reset-names = "dma"; +- #dma-cells = <1>; +- }; +- +- apbmisc@70000800 { +- compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; +- reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ +- <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ +- }; +- +- pinmux: pinmux@70000868 { +- compatible = "nvidia,tegra124-pinmux"; +- reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ +- <0x0 0x70003000 0x0 0x434>, /* Mux registers */ +- <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ +- }; +- +- /* +- * There are two serial driver i.e. 8250 based simple serial +- * driver and APB DMA based serial driver for higher baudrate +- * and performace. To enable the 8250 based driver, the compatible +- * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable +- * the APB DMA based serial driver, the compatible is +- * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". +- */ +- uarta: serial@70006000 { +- compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; +- reg = <0x0 0x70006000 0x0 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_UARTA>; +- resets = <&tegra_car 6>; +- reset-names = "serial"; +- dmas = <&apbdma 8>, <&apbdma 8>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uartb: serial@70006040 { +- compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; +- reg = <0x0 0x70006040 0x0 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_UARTB>; +- resets = <&tegra_car 7>; +- reset-names = "serial"; +- dmas = <&apbdma 9>, <&apbdma 9>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uartc: serial@70006200 { +- compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; +- reg = <0x0 0x70006200 0x0 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_UARTC>; +- resets = <&tegra_car 55>; +- reset-names = "serial"; +- dmas = <&apbdma 10>, <&apbdma 10>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uartd: serial@70006300 { +- compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; +- reg = <0x0 0x70006300 0x0 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_UARTD>; +- resets = <&tegra_car 65>; +- reset-names = "serial"; +- dmas = <&apbdma 19>, <&apbdma 19>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- pwm: pwm@7000a000 { +- compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; +- reg = <0x0 0x7000a000 0x0 0x100>; +- #pwm-cells = <2>; +- clocks = <&tegra_car TEGRA124_CLK_PWM>; +- resets = <&tegra_car 17>; +- reset-names = "pwm"; +- status = "disabled"; +- }; +- +- i2c@7000c000 { +- compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; +- reg = <0x0 0x7000c000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_I2C1>; +- clock-names = "div-clk"; +- resets = <&tegra_car 12>; +- reset-names = "i2c"; +- dmas = <&apbdma 21>, <&apbdma 21>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000c400 { +- compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; +- reg = <0x0 0x7000c400 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_I2C2>; +- clock-names = "div-clk"; +- resets = <&tegra_car 54>; +- reset-names = "i2c"; +- dmas = <&apbdma 22>, <&apbdma 22>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000c500 { +- compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; +- reg = <0x0 0x7000c500 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_I2C3>; +- clock-names = "div-clk"; +- resets = <&tegra_car 67>; +- reset-names = "i2c"; +- dmas = <&apbdma 23>, <&apbdma 23>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000c700 { +- compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; +- reg = <0x0 0x7000c700 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_I2C4>; +- clock-names = "div-clk"; +- resets = <&tegra_car 103>; +- reset-names = "i2c"; +- dmas = <&apbdma 26>, <&apbdma 26>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000d000 { +- compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; +- reg = <0x0 0x7000d000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_I2C5>; +- clock-names = "div-clk"; +- resets = <&tegra_car 47>; +- reset-names = "i2c"; +- dmas = <&apbdma 24>, <&apbdma 24>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000d100 { +- compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; +- reg = <0x0 0x7000d100 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_I2C6>; +- clock-names = "div-clk"; +- resets = <&tegra_car 166>; +- reset-names = "i2c"; +- dmas = <&apbdma 30>, <&apbdma 30>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000d400 { +- compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; +- reg = <0x0 0x7000d400 0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_SBC1>; +- clock-names = "spi"; +- resets = <&tegra_car 41>; +- reset-names = "spi"; +- dmas = <&apbdma 15>, <&apbdma 15>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000d600 { +- compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; +- reg = <0x0 0x7000d600 0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_SBC2>; +- clock-names = "spi"; +- resets = <&tegra_car 44>; +- reset-names = "spi"; +- dmas = <&apbdma 16>, <&apbdma 16>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000d800 { +- compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; +- reg = <0x0 0x7000d800 0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_SBC3>; +- clock-names = "spi"; +- resets = <&tegra_car 46>; +- reset-names = "spi"; +- dmas = <&apbdma 17>, <&apbdma 17>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000da00 { +- compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; +- reg = <0x0 0x7000da00 0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_SBC4>; +- clock-names = "spi"; +- resets = <&tegra_car 68>; +- reset-names = "spi"; +- dmas = <&apbdma 18>, <&apbdma 18>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000dc00 { +- compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; +- reg = <0x0 0x7000dc00 0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_SBC5>; +- clock-names = "spi"; +- resets = <&tegra_car 104>; +- reset-names = "spi"; +- dmas = <&apbdma 27>, <&apbdma 27>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000de00 { +- compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; +- reg = <0x0 0x7000de00 0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_SBC6>; +- clock-names = "spi"; +- resets = <&tegra_car 105>; +- reset-names = "spi"; +- dmas = <&apbdma 28>, <&apbdma 28>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- rtc@7000e000 { +- compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; +- reg = <0x0 0x7000e000 0x0 0x100>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_RTC>; +- }; +- +- tegra_pmc: pmc@7000e400 { +- compatible = "nvidia,tegra124-pmc"; +- reg = <0x0 0x7000e400 0x0 0x400>; +- clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; +- clock-names = "pclk", "clk32k_in"; +- #clock-cells = <1>; +- }; +- +- fuse@7000f800 { +- compatible = "nvidia,tegra124-efuse"; +- reg = <0x0 0x7000f800 0x0 0x400>; +- clocks = <&tegra_car TEGRA124_CLK_FUSE>; +- clock-names = "fuse"; +- resets = <&tegra_car 39>; +- reset-names = "fuse"; +- }; +- +- mc: memory-controller@70019000 { +- compatible = "nvidia,tegra124-mc"; +- reg = <0x0 0x70019000 0x0 0x1000>; +- clocks = <&tegra_car TEGRA124_CLK_MC>; +- clock-names = "mc"; +- +- interrupts = ; +- +- #iommu-cells = <1>; +- #reset-cells = <1>; +- #interconnect-cells = <1>; +- }; +- +- emc: external-memory-controller@7001b000 { +- compatible = "nvidia,tegra124-emc"; +- reg = <0x0 0x7001b000 0x0 0x1000>; +- clocks = <&tegra_car TEGRA124_CLK_EMC>; +- clock-names = "emc"; +- +- nvidia,memory-controller = <&mc>; +- operating-points-v2 = <&emc_icc_dvfs_opp_table>; +- +- #interconnect-cells = <0>; +- }; +- +- sata@70020000 { +- compatible = "nvidia,tegra124-ahci"; +- reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ +- <0x0 0x70020000 0x0 0x7000>; /* SATA */ +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_SATA>, +- <&tegra_car TEGRA124_CLK_SATA_OOB>, +- <&tegra_car TEGRA124_CLK_CML1>, +- <&tegra_car TEGRA124_CLK_PLL_E>; +- clock-names = "sata", "sata-oob", "cml1", "pll_e"; +- resets = <&tegra_car 124>, +- <&tegra_car 129>, +- <&tegra_car 123>; +- reset-names = "sata", "sata-cold", "sata-oob"; +- status = "disabled"; +- }; +- +- hda@70030000 { +- compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; +- reg = <0x0 0x70030000 0x0 0x10000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_HDA>, +- <&tegra_car TEGRA124_CLK_HDA2HDMI>, +- <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; +- clock-names = "hda", "hda2hdmi", "hda2codec_2x"; +- resets = <&tegra_car 125>, /* hda */ +- <&tegra_car 128>, /* hda2hdmi */ +- <&tegra_car 111>; /* hda2codec_2x */ +- reset-names = "hda", "hda2hdmi", "hda2codec_2x"; +- status = "disabled"; +- }; +- +- usb@70090000 { +- compatible = "nvidia,tegra124-xusb"; +- reg = <0x0 0x70090000 0x0 0x8000>, +- <0x0 0x70098000 0x0 0x1000>, +- <0x0 0x70099000 0x0 0x1000>; +- reg-names = "hcd", "fpci", "ipfs"; +- +- interrupts = , +- ; +- +- clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, +- <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, +- <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, +- <&tegra_car TEGRA124_CLK_XUSB_SS>, +- <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, +- <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, +- <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, +- <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, +- <&tegra_car TEGRA124_CLK_PLL_U_480M>, +- <&tegra_car TEGRA124_CLK_CLK_M>, +- <&tegra_car TEGRA124_CLK_PLL_E>; +- clock-names = "xusb_host", "xusb_host_src", +- "xusb_falcon_src", "xusb_ss", +- "xusb_ss_src", "xusb_ss_div2", +- "xusb_hs_src", "xusb_fs_src", +- "pll_u_480m", "clk_m", "pll_e"; +- resets = <&tegra_car 89>, <&tegra_car 156>, +- <&tegra_car 143>; +- reset-names = "xusb_host", "xusb_ss", "xusb_src"; +- +- nvidia,xusb-padctl = <&padctl>; +- +- status = "disabled"; +- }; +- +- padctl: padctl@7009f000 { +- compatible = "nvidia,tegra124-xusb-padctl"; +- reg = <0x0 0x7009f000 0x0 0x1000>; +- resets = <&tegra_car 142>; +- reset-names = "padctl"; +- +- pads { +- usb2 { +- status = "disabled"; +- +- lanes { +- usb2-0 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- usb2-1 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- usb2-2 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- ulpi { +- status = "disabled"; +- +- lanes { +- ulpi-0 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- hsic { +- status = "disabled"; +- +- lanes { +- hsic-0 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- hsic-1 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- pcie { +- status = "disabled"; +- +- lanes { +- pcie-0 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- pcie-1 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- pcie-2 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- pcie-3 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- pcie-4 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- sata { +- status = "disabled"; +- +- lanes { +- sata-0 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- }; +- }; +- +- ports { +- usb2-0 { +- status = "disabled"; +- }; +- +- usb2-1 { +- status = "disabled"; +- }; +- +- usb2-2 { +- status = "disabled"; +- }; +- +- ulpi-0 { +- status = "disabled"; +- }; +- +- hsic-0 { +- status = "disabled"; +- }; +- +- hsic-1 { +- status = "disabled"; +- }; +- +- usb3-0 { +- status = "disabled"; +- }; +- +- usb3-1 { +- status = "disabled"; +- }; +- }; +- }; +- +- mmc@700b0000 { +- compatible = "nvidia,tegra124-sdhci"; +- reg = <0x0 0x700b0000 0x0 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; +- clock-names = "sdhci"; +- resets = <&tegra_car 14>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- mmc@700b0200 { +- compatible = "nvidia,tegra124-sdhci"; +- reg = <0x0 0x700b0200 0x0 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; +- clock-names = "sdhci"; +- resets = <&tegra_car 9>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- mmc@700b0400 { +- compatible = "nvidia,tegra124-sdhci"; +- reg = <0x0 0x700b0400 0x0 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; +- clock-names = "sdhci"; +- resets = <&tegra_car 69>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- mmc@700b0600 { +- compatible = "nvidia,tegra124-sdhci"; +- reg = <0x0 0x700b0600 0x0 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; +- clock-names = "sdhci"; +- resets = <&tegra_car 15>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- cec@70015000 { +- compatible = "nvidia,tegra124-cec"; +- reg = <0x0 0x70015000 0x0 0x00001000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_CEC>; +- clock-names = "cec"; +- status = "disabled"; +- hdmi-phandle = <&hdmi>; +- }; +- +- soctherm: thermal-sensor@700e2000 { +- compatible = "nvidia,tegra124-soctherm"; +- reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ +- <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ +- reg-names = "soctherm-reg", "car-reg"; +- interrupts = , +- ; +- interrupt-names = "thermal", "edp"; +- clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, +- <&tegra_car TEGRA124_CLK_SOC_THERM>; +- clock-names = "tsensor", "soctherm"; +- resets = <&tegra_car 78>; +- reset-names = "soctherm"; +- #thermal-sensor-cells = <1>; +- +- throttle-cfgs { +- throttle_heavy: heavy { +- nvidia,priority = <100>; +- nvidia,cpu-throt-percent = <85>; +- nvidia,gpu-throt-level = ; +- +- #cooling-cells = <2>; +- }; +- }; +- }; +- +- dfll: clock@70110000 { +- compatible = "nvidia,tegra124-dfll"; +- reg = <0 0x70110000 0 0x100>, /* DFLL control */ +- <0 0x70110000 0 0x100>, /* I2C output control */ +- <0 0x70110100 0 0x100>, /* Integrated I2C controller */ +- <0 0x70110200 0 0x100>; /* Look-up table RAM */ +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, +- <&tegra_car TEGRA124_CLK_DFLL_REF>, +- <&tegra_car TEGRA124_CLK_I2C5>; +- clock-names = "soc", "ref", "i2c"; +- resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; +- reset-names = "dvco"; +- #clock-cells = <0>; +- clock-output-names = "dfllCPU_out"; +- nvidia,sample-rate = <12500>; +- nvidia,droop-ctrl = <0x00000f00>; +- nvidia,force-mode = <1>; +- nvidia,cf = <10>; +- nvidia,ci = <0>; +- nvidia,cg = <2>; +- status = "disabled"; +- }; +- +- ahub@70300000 { +- compatible = "nvidia,tegra124-ahub"; +- reg = <0x0 0x70300000 0x0 0x200>, +- <0x0 0x70300800 0x0 0x800>, +- <0x0 0x70300200 0x0 0x600>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, +- <&tegra_car TEGRA124_CLK_APBIF>; +- clock-names = "d_audio", "apbif"; +- resets = <&tegra_car 106>, /* d_audio */ +- <&tegra_car 107>, /* apbif */ +- <&tegra_car 30>, /* i2s0 */ +- <&tegra_car 11>, /* i2s1 */ +- <&tegra_car 18>, /* i2s2 */ +- <&tegra_car 101>, /* i2s3 */ +- <&tegra_car 102>, /* i2s4 */ +- <&tegra_car 108>, /* dam0 */ +- <&tegra_car 109>, /* dam1 */ +- <&tegra_car 110>, /* dam2 */ +- <&tegra_car 10>, /* spdif */ +- <&tegra_car 153>, /* amx */ +- <&tegra_car 185>, /* amx1 */ +- <&tegra_car 154>, /* adx */ +- <&tegra_car 180>, /* adx1 */ +- <&tegra_car 186>, /* afc0 */ +- <&tegra_car 187>, /* afc1 */ +- <&tegra_car 188>, /* afc2 */ +- <&tegra_car 189>, /* afc3 */ +- <&tegra_car 190>, /* afc4 */ +- <&tegra_car 191>; /* afc5 */ +- reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", +- "i2s3", "i2s4", "dam0", "dam1", "dam2", +- "spdif", "amx", "amx1", "adx", "adx1", +- "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; +- dmas = <&apbdma 1>, <&apbdma 1>, +- <&apbdma 2>, <&apbdma 2>, +- <&apbdma 3>, <&apbdma 3>, +- <&apbdma 4>, <&apbdma 4>, +- <&apbdma 6>, <&apbdma 6>, +- <&apbdma 7>, <&apbdma 7>, +- <&apbdma 12>, <&apbdma 12>, +- <&apbdma 13>, <&apbdma 13>, +- <&apbdma 14>, <&apbdma 14>, +- <&apbdma 29>, <&apbdma 29>; +- dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", +- "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", +- "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", +- "rx9", "tx9"; +- ranges; +- #address-cells = <2>; +- #size-cells = <2>; +- +- tegra_i2s0: i2s@70301000 { +- compatible = "nvidia,tegra124-i2s"; +- reg = <0x0 0x70301000 0x0 0x100>; +- nvidia,ahub-cif-ids = <4 4>; +- clocks = <&tegra_car TEGRA124_CLK_I2S0>; +- resets = <&tegra_car 30>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- +- tegra_i2s1: i2s@70301100 { +- compatible = "nvidia,tegra124-i2s"; +- reg = <0x0 0x70301100 0x0 0x100>; +- nvidia,ahub-cif-ids = <5 5>; +- clocks = <&tegra_car TEGRA124_CLK_I2S1>; +- resets = <&tegra_car 11>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- +- tegra_i2s2: i2s@70301200 { +- compatible = "nvidia,tegra124-i2s"; +- reg = <0x0 0x70301200 0x0 0x100>; +- nvidia,ahub-cif-ids = <6 6>; +- clocks = <&tegra_car TEGRA124_CLK_I2S2>; +- resets = <&tegra_car 18>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- +- tegra_i2s3: i2s@70301300 { +- compatible = "nvidia,tegra124-i2s"; +- reg = <0x0 0x70301300 0x0 0x100>; +- nvidia,ahub-cif-ids = <7 7>; +- clocks = <&tegra_car TEGRA124_CLK_I2S3>; +- resets = <&tegra_car 101>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- +- tegra_i2s4: i2s@70301400 { +- compatible = "nvidia,tegra124-i2s"; +- reg = <0x0 0x70301400 0x0 0x100>; +- nvidia,ahub-cif-ids = <8 8>; +- clocks = <&tegra_car TEGRA124_CLK_I2S4>; +- resets = <&tegra_car 102>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- }; +- +- usb@7d000000 { +- compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; +- reg = <0x0 0x7d000000 0x0 0x4000>; +- interrupts = ; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA124_CLK_USBD>; +- resets = <&tegra_car 22>; +- reset-names = "usb"; +- nvidia,phy = <&phy1>; +- status = "disabled"; +- }; +- +- phy1: usb-phy@7d000000 { +- compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; +- reg = <0x0 0x7d000000 0x0 0x4000>, +- <0x0 0x7d000000 0x0 0x4000>; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA124_CLK_USBD>, +- <&tegra_car TEGRA124_CLK_PLL_U>, +- <&tegra_car TEGRA124_CLK_USBD>; +- clock-names = "reg", "pll_u", "utmi-pads"; +- resets = <&tegra_car 22>, <&tegra_car 22>; +- reset-names = "usb", "utmi-pads"; +- #phy-cells = <0>; +- nvidia,hssync-start-delay = <0>; +- nvidia,idle-wait-delay = <17>; +- nvidia,elastic-limit = <16>; +- nvidia,term-range-adj = <6>; +- nvidia,xcvr-setup = <9>; +- nvidia,xcvr-lsfslew = <0>; +- nvidia,xcvr-lsrslew = <3>; +- nvidia,hssquelch-level = <2>; +- nvidia,hsdiscon-level = <5>; +- nvidia,xcvr-hsslew = <12>; +- nvidia,has-utmi-pad-registers; +- status = "disabled"; +- }; +- +- usb@7d004000 { +- compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; +- reg = <0x0 0x7d004000 0x0 0x4000>; +- interrupts = ; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA124_CLK_USB2>; +- resets = <&tegra_car 58>; +- reset-names = "usb"; +- nvidia,phy = <&phy2>; +- status = "disabled"; +- }; +- +- phy2: usb-phy@7d004000 { +- compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; +- reg = <0x0 0x7d004000 0x0 0x4000>, +- <0x0 0x7d000000 0x0 0x4000>; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA124_CLK_USB2>, +- <&tegra_car TEGRA124_CLK_PLL_U>, +- <&tegra_car TEGRA124_CLK_USBD>; +- clock-names = "reg", "pll_u", "utmi-pads"; +- resets = <&tegra_car 58>, <&tegra_car 22>; +- reset-names = "usb", "utmi-pads"; +- #phy-cells = <0>; +- nvidia,hssync-start-delay = <0>; +- nvidia,idle-wait-delay = <17>; +- nvidia,elastic-limit = <16>; +- nvidia,term-range-adj = <6>; +- nvidia,xcvr-setup = <9>; +- nvidia,xcvr-lsfslew = <0>; +- nvidia,xcvr-lsrslew = <3>; +- nvidia,hssquelch-level = <2>; +- nvidia,hsdiscon-level = <5>; +- nvidia,xcvr-hsslew = <12>; +- status = "disabled"; +- }; +- +- usb@7d008000 { +- compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; +- reg = <0x0 0x7d008000 0x0 0x4000>; +- interrupts = ; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA124_CLK_USB3>; +- resets = <&tegra_car 59>; +- reset-names = "usb"; +- nvidia,phy = <&phy3>; +- status = "disabled"; +- }; +- +- phy3: usb-phy@7d008000 { +- compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; +- reg = <0x0 0x7d008000 0x0 0x4000>, +- <0x0 0x7d000000 0x0 0x4000>; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA124_CLK_USB3>, +- <&tegra_car TEGRA124_CLK_PLL_U>, +- <&tegra_car TEGRA124_CLK_USBD>; +- clock-names = "reg", "pll_u", "utmi-pads"; +- resets = <&tegra_car 59>, <&tegra_car 22>; +- reset-names = "usb", "utmi-pads"; +- #phy-cells = <0>; +- nvidia,hssync-start-delay = <0>; +- nvidia,idle-wait-delay = <17>; +- nvidia,elastic-limit = <16>; +- nvidia,term-range-adj = <6>; +- nvidia,xcvr-setup = <9>; +- nvidia,xcvr-lsfslew = <0>; +- nvidia,xcvr-lsrslew = <3>; +- nvidia,hssquelch-level = <2>; +- nvidia,hsdiscon-level = <5>; +- nvidia,xcvr-hsslew = <12>; +- status = "disabled"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0>; +- +- clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, +- <&tegra_car TEGRA124_CLK_CCLK_LP>, +- <&tegra_car TEGRA124_CLK_PLL_X>, +- <&tegra_car TEGRA124_CLK_PLL_P>, +- <&dfll>; +- clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; +- /* FIXME: what's the actual transition time? */ +- clock-latency = <300000>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <1>; +- }; +- +- cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <2>; +- }; +- +- cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <3>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a15-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&{/cpus/cpu@0}>, +- <&{/cpus/cpu@1}>, +- <&{/cpus/cpu@2}>, +- <&{/cpus/cpu@3}>; +- }; +- +- thermal-zones { +- cpu { +- polling-delay-passive = <1000>; +- polling-delay = <1000>; +- +- thermal-sensors = +- <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; +- +- trips { +- cpu-shutdown-trip { +- temperature = <103000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- cpu_throttle_trip: throttle-trip { +- temperature = <100000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_throttle_trip>; +- cooling-device = <&throttle_heavy 1 1>; +- }; +- }; +- }; +- +- mem { +- polling-delay-passive = <1000>; +- polling-delay = <1000>; +- +- thermal-sensors = +- <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; +- +- trips { +- mem-shutdown-trip { +- temperature = <103000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- mem-throttle-trip { +- temperature = <99000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- +- cooling-maps { +- /* +- * There are currently no cooling maps, +- * because there are no cooling devices. +- */ +- }; +- }; +- +- gpu { +- polling-delay-passive = <1000>; +- polling-delay = <1000>; +- +- thermal-sensors = +- <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; +- +- trips { +- gpu-shutdown-trip { +- temperature = <101000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- gpu_throttle_trip: throttle-trip { +- temperature = <99000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&gpu_throttle_trip>; +- cooling-device = <&throttle_heavy 1 1>; +- }; +- }; +- }; +- +- pllx { +- polling-delay-passive = <1000>; +- polling-delay = <1000>; +- +- thermal-sensors = +- <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; +- +- trips { +- pllx-shutdown-trip { +- temperature = <103000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- pllx-throttle-trip { +- temperature = <99000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- +- cooling-maps { +- /* +- * There are currently no cooling maps, +- * because there are no cooling devices. +- */ +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- interrupt-parent = <&gic>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra20-acer-a500-picasso.dts b/scripts/dtc/include-prefixes/arm/tegra20-acer-a500-picasso.dts +deleted file mode 100644 +index 2280d75b66ab..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra20-acer-a500-picasso.dts ++++ /dev/null +@@ -1,1508 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +-#include +-#include +- +-#include "tegra20.dtsi" +-#include "tegra20-cpu-opp.dtsi" +-#include "tegra20-cpu-opp-microvolt.dtsi" +- +-/ { +- model = "Acer Iconia Tab A500"; +- compatible = "acer,picasso", "nvidia,tegra20"; +- +- aliases { +- mmc0 = &sdmmc4; /* eMMC */ +- mmc1 = &sdmmc3; /* MicroSD */ +- mmc2 = &sdmmc1; /* WiFi */ +- +- rtc0 = &pmic; +- rtc1 = "/rtc@7000e000"; +- +- serial0 = &uartd; /* Docking station */ +- serial1 = &uartc; /* Bluetooth */ +- serial2 = &uartb; /* GPS */ +- }; +- +- /* +- * The decompressor and also some bootloaders rely on a +- * pre-existing /chosen node to be available to insert the +- * command line and merge other ATAGS info. +- */ +- chosen {}; +- +- memory@0 { +- reg = <0x00000000 0x40000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- ramoops@2ffe0000 { +- compatible = "ramoops"; +- reg = <0x2ffe0000 0x10000>; /* 64kB */ +- console-size = <0x8000>; /* 32kB */ +- record-size = <0x400>; /* 1kB */ +- ecc-size = <16>; +- }; +- +- linux,cma@30000000 { +- compatible = "shared-dma-pool"; +- alloc-ranges = <0x30000000 0x10000000>; +- size = <0x10000000>; /* 256MiB */ +- linux,cma-default; +- reusable; +- }; +- }; +- +- host1x@50000000 { +- dc@54200000 { +- rgb { +- status = "okay"; +- +- port@0 { +- lcd_output: endpoint { +- remote-endpoint = <&lvds_encoder_input>; +- bus-width = <18>; +- }; +- }; +- }; +- }; +- +- hdmi@54280000 { +- status = "okay"; +- +- vdd-supply = <&hdmi_vdd_reg>; +- pll-supply = <&hdmi_pll_reg>; +- hdmi-supply = <&vdd_5v0_sys>; +- +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) +- GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- pinmux@70000014 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- ata { +- nvidia,pins = "ata"; +- nvidia,function = "ide"; +- }; +- atb { +- nvidia,pins = "atb", "gma", "gme"; +- nvidia,function = "sdio4"; +- }; +- atc { +- nvidia,pins = "atc"; +- nvidia,function = "nand"; +- }; +- atd { +- nvidia,pins = "atd", "ate", "gmb", "spia", +- "spib", "spic"; +- nvidia,function = "gmi"; +- }; +- cdev1 { +- nvidia,pins = "cdev1"; +- nvidia,function = "plla_out"; +- }; +- cdev2 { +- nvidia,pins = "cdev2"; +- nvidia,function = "pllp_out4"; +- }; +- crtp { +- nvidia,pins = "crtp", "lm1"; +- nvidia,function = "crt"; +- }; +- csus { +- nvidia,pins = "csus"; +- nvidia,function = "vi_sensor_clk"; +- }; +- dap1 { +- nvidia,pins = "dap1"; +- nvidia,function = "dap1"; +- }; +- dap2 { +- nvidia,pins = "dap2"; +- nvidia,function = "dap2"; +- }; +- dap3 { +- nvidia,pins = "dap3"; +- nvidia,function = "dap3"; +- }; +- dap4 { +- nvidia,pins = "dap4"; +- nvidia,function = "dap4"; +- }; +- dta { +- nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; +- nvidia,function = "vi"; +- }; +- dtf { +- nvidia,pins = "dtf"; +- nvidia,function = "i2c3"; +- }; +- gmc { +- nvidia,pins = "gmc"; +- nvidia,function = "uartd"; +- }; +- gmd { +- nvidia,pins = "gmd"; +- nvidia,function = "sflash"; +- }; +- gpu { +- nvidia,pins = "gpu"; +- nvidia,function = "pwm"; +- }; +- gpu7 { +- nvidia,pins = "gpu7"; +- nvidia,function = "rtck"; +- }; +- gpv { +- nvidia,pins = "gpv", "slxa"; +- nvidia,function = "pcie"; +- }; +- hdint { +- nvidia,pins = "hdint"; +- nvidia,function = "hdmi"; +- }; +- i2cp { +- nvidia,pins = "i2cp"; +- nvidia,function = "i2cp"; +- }; +- irrx { +- nvidia,pins = "irrx", "irtx"; +- nvidia,function = "uartb"; +- }; +- kbca { +- nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", +- "kbce", "kbcf"; +- nvidia,function = "kbc"; +- }; +- lcsn { +- nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", +- "lsdi", "lvp0"; +- nvidia,function = "rsvd4"; +- }; +- ld0 { +- nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", +- "ld5", "ld6", "ld7", "ld8", "ld9", +- "ld10", "ld11", "ld12", "ld13", "ld14", +- "ld15", "ld16", "ld17", "ldi", "lhp0", +- "lhp1", "lhp2", "lhs", "lpp", "lsc0", +- "lsc1", "lsck", "lsda", "lspi", "lvp1", +- "lvs"; +- nvidia,function = "displaya"; +- }; +- owc { +- nvidia,pins = "owc", "spdi", "spdo", "uac"; +- nvidia,function = "rsvd2"; +- }; +- pmc { +- nvidia,pins = "pmc"; +- nvidia,function = "pwr_on"; +- }; +- rm { +- nvidia,pins = "rm"; +- nvidia,function = "i2c1"; +- }; +- sdb { +- nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk"; +- nvidia,function = "sdio3"; +- }; +- sdio1 { +- nvidia,pins = "sdio1"; +- nvidia,function = "sdio1"; +- }; +- slxd { +- nvidia,pins = "slxd"; +- nvidia,function = "spdif"; +- }; +- spid { +- nvidia,pins = "spid", "spie", "spif"; +- nvidia,function = "spi1"; +- }; +- spig { +- nvidia,pins = "spig", "spih"; +- nvidia,function = "spi2_alt"; +- }; +- uaa { +- nvidia,pins = "uaa", "uab", "uda"; +- nvidia,function = "ulpi"; +- }; +- uad { +- nvidia,pins = "uad"; +- nvidia,function = "irda"; +- }; +- uca { +- nvidia,pins = "uca", "ucb"; +- nvidia,function = "uartc"; +- }; +- conf_ata { +- nvidia,pins = "ata", "atb", "atc", "atd", +- "cdev1", "cdev2", "csus", "dap1", +- "dap4", "dte", "dtf", "gma", "gmc", +- "gme", "gpu", "gpu7", "gpv", "i2cp", +- "irrx", "irtx", "pta", "rm", +- "sdc", "sdd", "slxc", "slxd", "slxk", +- "spdi", "spdo", "uac", "uad", "uda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_ate { +- nvidia,pins = "ate", "dap2", "dap3", +- "gmd", "owc", "spia", "spib", "spic", +- "spid", "spie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_ck32 { +- nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", +- "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; +- nvidia,pull = ; +- }; +- conf_crtp { +- nvidia,pins = "crtp", "gmb", "slxa", "spig", +- "spih"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_dta { +- nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_dte { +- nvidia,pins = "spif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_hdint { +- nvidia,pins = "hdint", "lcsn", "ldc", "lm1", +- "lpw1", "lsck", "lsda", "lsdi", +- "lvp0"; +- nvidia,tristate = ; +- }; +- conf_kbca { +- nvidia,pins = "kbca", "kbcc", "kbcd", +- "kbce", "kbcf", "sdio1", "uaa", +- "uab", "uca", "ucb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_lc { +- nvidia,pins = "lc", "ls"; +- nvidia,pull = ; +- }; +- conf_ld0 { +- nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", +- "ld5", "ld6", "ld7", "ld8", "ld9", +- "ld10", "ld11", "ld12", "ld13", "ld14", +- "ld15", "ld16", "ld17", "ldi", "lhp0", +- "lhp1", "lhp2", "lhs", "lm0", "lpp", +- "lpw0", "lpw2", "lsc0", "lsc1", "lspi", +- "lvp1", "lvs", "pmc", "sdb"; +- nvidia,tristate = ; +- }; +- conf_ld17_0 { +- nvidia,pins = "ld17_0"; +- nvidia,pull = ; +- }; +- drive_ddc { +- nvidia,pins = "drive_ddc", +- "drive_vi1", +- "drive_sdio1"; +- nvidia,pull-up-strength = <31>; +- nvidia,pull-down-strength = <31>; +- nvidia,schmitt = ; +- nvidia,high-speed-mode = ; +- nvidia,low-power-mode = ; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- }; +- drive_dbg { +- nvidia,pins = "drive_dbg", +- "drive_vi2", +- "drive_at1", +- "drive_ao1"; +- nvidia,pull-up-strength = <31>; +- nvidia,pull-down-strength = <31>; +- nvidia,schmitt = ; +- nvidia,high-speed-mode = ; +- nvidia,low-power-mode = ; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- }; +- }; +- +- state_i2cmux_ddc: pinmux_i2cmux_ddc { +- ddc { +- nvidia,pins = "ddc"; +- nvidia,function = "i2c2"; +- }; +- pta { +- nvidia,pins = "pta"; +- nvidia,function = "rsvd4"; +- }; +- }; +- +- state_i2cmux_pta: pinmux_i2cmux_pta { +- ddc { +- nvidia,pins = "ddc"; +- nvidia,function = "rsvd4"; +- }; +- pta { +- nvidia,pins = "pta"; +- nvidia,function = "i2c2"; +- }; +- }; +- +- state_i2cmux_idle: pinmux_i2cmux_idle { +- ddc { +- nvidia,pins = "ddc"; +- nvidia,function = "rsvd4"; +- }; +- pta { +- nvidia,pins = "pta"; +- nvidia,function = "rsvd4"; +- }; +- }; +- }; +- +- tegra_i2s1: i2s@70002800 { +- status = "okay"; +- }; +- +- uartb: serial@70006040 { +- compatible = "nvidia,tegra20-hsuart"; +- /* GPS BCM4751 */ +- }; +- +- uartc: serial@70006200 { +- compatible = "nvidia,tegra20-hsuart"; +- status = "okay"; +- +- /* Azurewave AW-NH665 BCM4329B1 */ +- bluetooth { +- compatible = "brcm,bcm4329-bt"; +- +- /* PLLP 216MHz / 16 / 4 */ +- max-speed = <3375000>; +- +- clocks = <&rtc_32k_wifi>; +- clock-names = "txco"; +- +- vbat-supply = <&vdd_3v3_sys>; +- vddio-supply = <&vdd_1v8_sys>; +- +- device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- uartd: serial@70006300 { +- /* Docking station */ +- }; +- +- i2c@7000c000 { +- clock-frequency = <400000>; +- status = "okay"; +- +- wm8903: audio-codec@1a { +- compatible = "wlf,wm8903"; +- reg = <0x1a>; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- micdet-cfg = <0>; +- micdet-delay = <100>; +- +- gpio-cfg = < +- 0x0000 /* MIC_LR_OUT# GPIO, output, low */ +- 0x0000 /* FM2018-enable GPIO, output, low */ +- 0x0000 /* Speaker-enable GPIO, output, low */ +- 0x0200 /* Interrupt, output */ +- 0x01a0 /* BCLK, input, active high */ +- >; +- +- AVDD-supply = <&vdd_1v8_sys>; +- CPVDD-supply = <&vdd_1v8_sys>; +- DBVDD-supply = <&vdd_1v8_sys>; +- DCVDD-supply = <&vdd_1v8_sys>; +- }; +- +- touchscreen@4c { +- compatible = "atmel,maxtouch"; +- reg = <0x4c>; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>; +- +- vdda-supply = <&vdd_3v3_sys>; +- vdd-supply = <&vdd_3v3_sys>; +- +- atmel,wakeup-method = ; +- }; +- +- gyroscope@68 { +- compatible = "invensense,mpu3050"; +- reg = <0x68>; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- vdd-supply = <&vdd_3v3_sys>; +- vlogic-supply = <&vdd_1v8_sys>; +- +- mount-matrix = "0", "1", "0", +- "1", "0", "0", +- "0", "0", "-1"; +- +- i2c-gate { +- #address-cells = <1>; +- #size-cells = <0>; +- +- accelerometer@f { +- compatible = "kionix,kxtf9"; +- reg = <0x0f>; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- vdd-supply = <&vdd_1v8_sys>; +- vddio-supply = <&vdd_1v8_sys>; +- +- mount-matrix = "0", "1", "0", +- "1", "0", "0", +- "0", "0", "-1"; +- }; +- }; +- }; +- }; +- +- i2c@7000c400 { +- clock-frequency = <10000>; +- status = "okay"; +- }; +- +- i2cmux { +- compatible = "i2c-mux-pinctrl"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c-parent = <&{/i2c@7000c400}>; +- +- pinctrl-names = "ddc", "pta", "idle"; +- pinctrl-0 = <&state_i2cmux_ddc>; +- pinctrl-1 = <&state_i2cmux_pta>; +- pinctrl-2 = <&state_i2cmux_idle>; +- +- hdmi_ddc: i2c@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- panel_ddc: i2c@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- embedded-controller@58 { +- compatible = "acer,a500-iconia-ec", "ene,kb930"; +- reg = <0x58>; +- +- system-power-controller; +- +- monitored-battery = <&bat1010>; +- power-supplies = <&mains>; +- }; +- }; +- }; +- +- pwm: pwm@7000a000 { +- status = "okay"; +- }; +- +- i2c@7000d000 { +- clock-frequency = <100000>; +- status = "okay"; +- +- magnetometer@c { +- compatible = "ak,ak8975"; +- reg = <0x0c>; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- vdd-supply = <&vdd_3v3_sys>; +- vid-supply = <&vdd_1v8_sys>; +- +- mount-matrix = "1", "0", "0", +- "0", "-1", "0", +- "0", "0", "-1"; +- }; +- +- pmic: pmic@34 { +- compatible = "ti,tps6586x"; +- reg = <0x34>; +- +- interrupts = ; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- sys-supply = <&vdd_5v0_sys>; +- vin-sm0-supply = <&sys_reg>; +- vin-sm1-supply = <&sys_reg>; +- vin-sm2-supply = <&sys_reg>; +- vinldo01-supply = <&sm2_reg>; +- vinldo23-supply = <&sm2_reg>; +- vinldo4-supply = <&sm2_reg>; +- vinldo678-supply = <&sm2_reg>; +- vinldo9-supply = <&sm2_reg>; +- +- regulators { +- sys_reg: sys { +- regulator-name = "vdd_sys"; +- regulator-always-on; +- }; +- +- vdd_core: sm0 { +- regulator-name = "vdd_sm0,vdd_core"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1300000>; +- regulator-coupled-with = <&rtc_vdd &vdd_cpu>; +- regulator-coupled-max-spread = <170000 550000>; +- regulator-always-on; +- regulator-boot-on; +- +- nvidia,tegra-core-regulator; +- }; +- +- vdd_cpu: sm1 { +- regulator-name = "vdd_sm1,vdd_cpu"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1125000>; +- regulator-coupled-with = <&vdd_core &rtc_vdd>; +- regulator-coupled-max-spread = <550000 550000>; +- regulator-always-on; +- regulator-boot-on; +- +- nvidia,tegra-cpu-regulator; +- }; +- +- sm2_reg: sm2 { +- regulator-name = "vdd_sm2,vin_ldo*"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- regulator-always-on; +- }; +- +- /* LDO0 is not connected to anything */ +- +- ldo1 { +- regulator-name = "vdd_ldo1,avdd_pll*"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- rtc_vdd: ldo2 { +- regulator-name = "vdd_ldo2,vdd_rtc"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1300000>; +- regulator-coupled-with = <&vdd_core &vdd_cpu>; +- regulator-coupled-max-spread = <170000 550000>; +- regulator-always-on; +- regulator-boot-on; +- +- nvidia,tegra-rtc-regulator; +- }; +- +- ldo3 { +- regulator-name = "vdd_ldo3,avdd_usb*"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo4 { +- regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcore_emmc: ldo5 { +- regulator-name = "vdd_ldo5,vcore_mmc"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- }; +- +- avdd_vdac_reg: ldo6 { +- regulator-name = "vdd_ldo6,avdd_vdac"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- hdmi_vdd_reg: ldo7 { +- regulator-name = "vdd_ldo7,avdd_hdmi"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- hdmi_pll_reg: ldo8 { +- regulator-name = "vdd_ldo8,avdd_hdmi_pll"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo9 { +- regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo_rtc { +- regulator-name = "vdd_rtc_out,vdd_cell"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +- +- nct1008: temperature-sensor@4c { +- compatible = "onnn,nct1008"; +- reg = <0x4c>; +- vcc-supply = <&vdd_3v3_sys>; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- #thermal-sensor-cells = <1>; +- }; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <2000>; +- nvidia,cpu-pwr-off-time = <100>; +- nvidia,core-pwr-good-time = <3845 3845>; +- nvidia,core-pwr-off-time = <458>; +- nvidia,sys-clock-req-active-high; +- }; +- +- usb@c5000000 { +- compatible = "nvidia,tegra20-udc"; +- status = "okay"; +- dr_mode = "peripheral"; +- }; +- +- usb-phy@c5000000 { +- status = "okay"; +- dr_mode = "peripheral"; +- nvidia,xcvr-setup-use-fuses; +- nvidia,xcvr-lsfslew = <2>; +- nvidia,xcvr-lsrslew = <2>; +- }; +- +- usb@c5008000 { +- status = "okay"; +- }; +- +- usb-phy@c5008000 { +- status = "okay"; +- nvidia,xcvr-setup-use-fuses; +- nvidia,xcvr-lsfslew = <2>; +- nvidia,xcvr-lsrslew = <2>; +- vbus-supply = <&vdd_5v0_sys>; +- }; +- +- brcm_wifi_pwrseq: wifi-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- +- clocks = <&rtc_32k_wifi>; +- clock-names = "ext_clock"; +- +- reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; +- post-power-on-delay-ms = <300>; +- power-off-delay-us = <300>; +- }; +- +- sdmmc1: mmc@c8000000 { +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; +- assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; +- assigned-clock-rates = <50000000>; +- +- max-frequency = <50000000>; +- keep-power-in-suspend; +- bus-width = <4>; +- non-removable; +- +- mmc-pwrseq = <&brcm_wifi_pwrseq>; +- vmmc-supply = <&vdd_3v3_sys>; +- vqmmc-supply = <&vdd_1v8_sys>; +- +- /* Azurewave AW-NH611 BCM4329 */ +- wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&gpio>; +- interrupts = ; +- interrupt-names = "host-wake"; +- }; +- }; +- +- sdmmc3: mmc@c8000400 { +- status = "okay"; +- bus-width = <4>; +- cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; +- power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; +- vmmc-supply = <&vdd_3v3_sys>; +- vqmmc-supply = <&vdd_3v3_sys>; +- }; +- +- sdmmc4: mmc@c8000600 { +- status = "okay"; +- bus-width = <8>; +- vmmc-supply = <&vcore_emmc>; +- vqmmc-supply = <&vdd_3v3_sys>; +- non-removable; +- }; +- +- mains: ac-adapter-detect { +- compatible = "gpio-charger"; +- charger-type = "mains"; +- gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- +- enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; +- power-supply = <&vdd_3v3_sys>; +- pwms = <&pwm 2 41667>; +- +- brightness-levels = <7 255>; +- num-interpolated-steps = <248>; +- default-brightness-level = <20>; +- }; +- +- bat1010: battery-2s1p { +- compatible = "simple-battery"; +- charge-full-design-microamp-hours = <3260000>; +- energy-full-design-microwatt-hours = <24000000>; +- operating-range-celsius = <0 40>; +- }; +- +- /* PMIC has a built-in 32KHz oscillator which is used by PMC */ +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "tps658621-out32k"; +- }; +- +- /* +- * This standalone onboard fixed-clock always-ON 32KHz +- * oscillator is used as a reference clock-source by the +- * Azurewave WiFi/BT module. +- */ +- rtc_32k_wifi: clock@1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "kk3270032"; +- }; +- +- cpus { +- cpu0: cpu@0 { +- cpu-supply = <&vdd_cpu>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- cpu-supply = <&vdd_cpu>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- }; +- +- display-panel { +- compatible = "auo,b101ew05", "panel-lvds"; +- +- ddc-i2c-bus = <&panel_ddc>; +- power-supply = <&vdd_pnl>; +- backlight = <&backlight>; +- +- width-mm = <218>; +- height-mm = <135>; +- +- data-mapping = "jeida-18"; +- +- panel-timing { +- clock-frequency = <71200000>; +- hactive = <1280>; +- vactive = <800>; +- hfront-porch = <8>; +- hback-porch = <18>; +- hsync-len = <184>; +- vsync-len = <3>; +- vfront-porch = <4>; +- vback-porch = <8>; +- }; +- +- port { +- panel_input: endpoint { +- remote-endpoint = <&lvds_encoder_output>; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "Power"; +- gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-event-action = ; +- wakeup-source; +- }; +- +- rotation-lock { +- label = "Rotate-lock"; +- gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>; +- linux,code = ; +- linux,input-type = ; +- debounce-interval = <10>; +- }; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-event-action = ; +- wakeup-source; +- }; +- +- volume-down { +- label = "Volume Down"; +- gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-event-action = ; +- wakeup-source; +- }; +- }; +- +- haptic-feedback { +- compatible = "gpio-vibrator"; +- enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; +- vcc-supply = <&vdd_3v3_sys>; +- }; +- +- lvds-encoder { +- compatible = "ti,sn75lvds83", "lvds-encoder"; +- +- powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; +- power-supply = <&vdd_3v3_sys>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- lvds_encoder_input: endpoint { +- remote-endpoint = <&lcd_output>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lvds_encoder_output: endpoint { +- remote-endpoint = <&panel_input>; +- }; +- }; +- }; +- }; +- +- vdd_5v0_sys: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- vdd_3v3_sys: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_3v3_vs"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_1v8_sys: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_1v8_vs"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_pnl: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_panel"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <300000>; +- gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- sound { +- compatible = "nvidia,tegra-audio-wm8903-picasso", +- "nvidia,tegra-audio-wm8903"; +- nvidia,model = "Acer Iconia Tab A500 WM8903"; +- +- nvidia,audio-routing = +- "Headphone Jack", "HPOUTR", +- "Headphone Jack", "HPOUTL", +- "Int Spk", "LINEOUTL", +- "Int Spk", "LINEOUTR", +- "Mic Jack", "MICBIAS", +- "IN2L", "Mic Jack", +- "IN2R", "Mic Jack", +- "IN1L", "Int Mic", +- "IN1R", "Int Mic"; +- +- nvidia,i2s-controller = <&tegra_i2s1>; +- nvidia,audio-codec = <&wm8903>; +- +- nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; +- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; +- nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>; +- nvidia,headset; +- +- clocks = <&tegra_car TEGRA20_CLK_PLL_A>, +- <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA20_CLK_CDEV1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- }; +- +- thermal-zones { +- /* +- * NCT1008 has two sensors: +- * +- * 0: internal that monitors ambient/skin temperature +- * 1: external that is connected to the CPU's diode +- * +- * Ideally we should use userspace thermal governor, +- * but it's a much more complex solution. The "skin" +- * zone is a simpler solution which prevents A500 from +- * getting too hot from a user's tactile perspective. +- * The CPU zone is intended to protect silicon from damage. +- */ +- +- skin-thermal { +- polling-delay-passive = <1000>; /* milliseconds */ +- polling-delay = <5000>; /* milliseconds */ +- +- thermal-sensors = <&nct1008 0>; +- +- trips { +- trip0: skin-alert { +- /* start throttling at 60C */ +- temperature = <60000>; +- hysteresis = <200>; +- type = "passive"; +- }; +- +- trip1: skin-crit { +- /* shut down at 70C */ +- temperature = <70000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&trip0>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu-thermal { +- polling-delay-passive = <1000>; /* milliseconds */ +- polling-delay = <5000>; /* milliseconds */ +- +- thermal-sensors = <&nct1008 1>; +- +- trips { +- trip2: cpu-alert { +- /* throttle at 85C until temperature drops to 84.8C */ +- temperature = <85000>; +- hysteresis = <200>; +- type = "passive"; +- }; +- +- trip3: cpu-crit { +- /* shut down at 90C */ +- temperature = <90000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map1 { +- trip = <&trip2>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- memory-controller@7000f400 { +- nvidia,use-ram-code; +- +- emc-tables@0 { +- nvidia,ram-code = <0>; /* elpida-8gb */ +- reg = <0>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- emc-table@25000 { +- reg = <25000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <25000>; +- nvidia,emc-registers = <0x00000002 0x00000006 +- 0x00000003 0x00000003 0x00000006 0x00000004 +- 0x00000002 0x00000009 0x00000003 0x00000003 +- 0x00000002 0x00000002 0x00000002 0x00000004 +- 0x00000003 0x00000008 0x0000000b 0x0000004d +- 0x00000000 0x00000003 0x00000003 0x00000003 +- 0x00000008 0x00000001 0x0000000a 0x00000004 +- 0x00000003 0x00000008 0x00000004 0x00000006 +- 0x00000002 0x00000068 0x00000000 0x00000003 +- 0x00000000 0x00000000 0x00000282 0xa0ae04ae +- 0x00070000 0x00000000 0x00000000 0x00000003 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- +- emc-table@50000 { +- reg = <50000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <50000>; +- nvidia,emc-registers = <0x00000003 0x00000007 +- 0x00000003 0x00000003 0x00000006 0x00000004 +- 0x00000002 0x00000009 0x00000003 0x00000003 +- 0x00000002 0x00000002 0x00000002 0x00000005 +- 0x00000003 0x00000008 0x0000000b 0x0000009f +- 0x00000000 0x00000003 0x00000003 0x00000003 +- 0x00000008 0x00000001 0x0000000a 0x00000007 +- 0x00000003 0x00000008 0x00000004 0x00000006 +- 0x00000002 0x000000d0 0x00000000 0x00000000 +- 0x00000000 0x00000000 0x00000282 0xa0ae04ae +- 0x00070000 0x00000000 0x00000000 0x00000005 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- +- emc-table@75000 { +- reg = <75000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <75000>; +- nvidia,emc-registers = <0x00000005 0x0000000a +- 0x00000004 0x00000003 0x00000006 0x00000004 +- 0x00000002 0x00000009 0x00000003 0x00000003 +- 0x00000002 0x00000002 0x00000002 0x00000005 +- 0x00000003 0x00000008 0x0000000b 0x000000ff +- 0x00000000 0x00000003 0x00000003 0x00000003 +- 0x00000008 0x00000001 0x0000000a 0x0000000b +- 0x00000003 0x00000008 0x00000004 0x00000006 +- 0x00000002 0x00000138 0x00000000 0x00000000 +- 0x00000000 0x00000000 0x00000282 0xa0ae04ae +- 0x00070000 0x00000000 0x00000000 0x00000007 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- +- emc-table@150000 { +- reg = <150000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <150000>; +- nvidia,emc-registers = <0x00000009 0x00000014 +- 0x00000007 0x00000003 0x00000006 0x00000004 +- 0x00000002 0x00000009 0x00000003 0x00000003 +- 0x00000002 0x00000002 0x00000002 0x00000005 +- 0x00000003 0x00000008 0x0000000b 0x0000021f +- 0x00000000 0x00000003 0x00000003 0x00000003 +- 0x00000008 0x00000001 0x0000000a 0x00000015 +- 0x00000003 0x00000008 0x00000004 0x00000006 +- 0x00000002 0x00000270 0x00000000 0x00000001 +- 0x00000000 0x00000000 0x00000282 0xa07c04ae +- 0x007dd510 0x00000000 0x00000000 0x0000000e +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- +- emc-table@300000 { +- reg = <300000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <300000>; +- nvidia,emc-registers = <0x00000012 0x00000027 +- 0x0000000d 0x00000006 0x00000007 0x00000005 +- 0x00000003 0x00000009 0x00000006 0x00000006 +- 0x00000003 0x00000003 0x00000002 0x00000006 +- 0x00000003 0x00000009 0x0000000c 0x0000045f +- 0x00000000 0x00000004 0x00000004 0x00000006 +- 0x00000008 0x00000001 0x0000000e 0x0000002a +- 0x00000003 0x0000000f 0x00000007 0x00000005 +- 0x00000002 0x000004e1 0x00000005 0x00000002 +- 0x00000000 0x00000000 0x00000282 0xe059048b +- 0x007e1510 0x00000000 0x00000000 0x0000001b +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- }; +- +- emc-tables@1 { +- nvidia,ram-code = <1>; /* elpida-4gb */ +- reg = <1>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- emc-table@25000 { +- reg = <25000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <25000>; +- nvidia,emc-registers = <0x00000002 0x00000006 +- 0x00000003 0x00000003 0x00000006 0x00000004 +- 0x00000002 0x00000009 0x00000003 0x00000003 +- 0x00000002 0x00000002 0x00000002 0x00000004 +- 0x00000003 0x00000008 0x0000000b 0x0000004d +- 0x00000000 0x00000003 0x00000003 0x00000003 +- 0x00000008 0x00000001 0x0000000a 0x00000004 +- 0x00000003 0x00000008 0x00000004 0x00000006 +- 0x00000002 0x00000068 0x00000000 0x00000003 +- 0x00000000 0x00000000 0x00000282 0xa0ae04ae +- 0x0007c000 0x00000000 0x00000000 0x00000003 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- +- emc-table@50000 { +- reg = <50000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <50000>; +- nvidia,emc-registers = <0x00000003 0x00000007 +- 0x00000003 0x00000003 0x00000006 0x00000004 +- 0x00000002 0x00000009 0x00000003 0x00000003 +- 0x00000002 0x00000002 0x00000002 0x00000005 +- 0x00000003 0x00000008 0x0000000b 0x0000009f +- 0x00000000 0x00000003 0x00000003 0x00000003 +- 0x00000008 0x00000001 0x0000000a 0x00000007 +- 0x00000003 0x00000008 0x00000004 0x00000006 +- 0x00000002 0x000000d0 0x00000000 0x00000000 +- 0x00000000 0x00000000 0x00000282 0xa0ae04ae +- 0x0007c000 0x00000000 0x00000000 0x00000005 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- +- emc-table@75000 { +- reg = <75000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <75000>; +- nvidia,emc-registers = <0x00000005 0x0000000a +- 0x00000004 0x00000003 0x00000006 0x00000004 +- 0x00000002 0x00000009 0x00000003 0x00000003 +- 0x00000002 0x00000002 0x00000002 0x00000005 +- 0x00000003 0x00000008 0x0000000b 0x000000ff +- 0x00000000 0x00000003 0x00000003 0x00000003 +- 0x00000008 0x00000001 0x0000000a 0x0000000b +- 0x00000003 0x00000008 0x00000004 0x00000006 +- 0x00000002 0x00000138 0x00000000 0x00000000 +- 0x00000000 0x00000000 0x00000282 0xa0ae04ae +- 0x0007c000 0x00000000 0x00000000 0x00000007 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- +- emc-table@150000 { +- reg = <150000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <150000>; +- nvidia,emc-registers = <0x00000009 0x00000014 +- 0x00000007 0x00000003 0x00000006 0x00000004 +- 0x00000002 0x00000009 0x00000003 0x00000003 +- 0x00000002 0x00000002 0x00000002 0x00000005 +- 0x00000003 0x00000008 0x0000000b 0x0000021f +- 0x00000000 0x00000003 0x00000003 0x00000003 +- 0x00000008 0x00000001 0x0000000a 0x00000015 +- 0x00000003 0x00000008 0x00000004 0x00000006 +- 0x00000002 0x00000270 0x00000000 0x00000001 +- 0x00000000 0x00000000 0x00000282 0xa07c04ae +- 0x007e4010 0x00000000 0x00000000 0x0000000e +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- +- emc-table@300000 { +- reg = <300000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <300000>; +- nvidia,emc-registers = <0x00000012 0x00000027 +- 0x0000000d 0x00000006 0x00000007 0x00000005 +- 0x00000003 0x00000009 0x00000006 0x00000006 +- 0x00000003 0x00000003 0x00000002 0x00000006 +- 0x00000003 0x00000009 0x0000000c 0x0000045f +- 0x00000000 0x00000004 0x00000004 0x00000006 +- 0x00000008 0x00000001 0x0000000e 0x0000002a +- 0x00000003 0x0000000f 0x00000007 0x00000005 +- 0x00000002 0x000004e1 0x00000005 0x00000002 +- 0x00000000 0x00000000 0x00000282 0xe059048b +- 0x007e0010 0x00000000 0x00000000 0x0000001b +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- }; +- +- emc-tables@2 { +- nvidia,ram-code = <2>; /* hynix-8gb */ +- reg = <2>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- emc-table@25000 { +- reg = <25000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <25000>; +- nvidia,emc-registers = <0x00000002 0x00000006 +- 0x00000003 0x00000003 0x00000006 0x00000004 +- 0x00000002 0x00000009 0x00000003 0x00000003 +- 0x00000002 0x00000002 0x00000002 0x00000004 +- 0x00000003 0x00000008 0x0000000b 0x0000004d +- 0x00000000 0x00000003 0x00000003 0x00000003 +- 0x00000008 0x00000001 0x0000000a 0x00000004 +- 0x00000003 0x00000008 0x00000004 0x00000006 +- 0x00000002 0x00000068 0x00000000 0x00000003 +- 0x00000000 0x00000000 0x00000282 0xa0ae04ae +- 0x00070000 0x00000000 0x00000000 0x00000003 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- +- emc-table@50000 { +- reg = <50000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <50000>; +- nvidia,emc-registers = <0x00000003 0x00000007 +- 0x00000003 0x00000003 0x00000006 0x00000004 +- 0x00000002 0x00000009 0x00000003 0x00000003 +- 0x00000002 0x00000002 0x00000002 0x00000005 +- 0x00000003 0x00000008 0x0000000b 0x0000009f +- 0x00000000 0x00000003 0x00000003 0x00000003 +- 0x00000008 0x00000001 0x0000000a 0x00000007 +- 0x00000003 0x00000008 0x00000004 0x00000006 +- 0x00000002 0x000000d0 0x00000000 0x00000000 +- 0x00000000 0x00000000 0x00000282 0xa0ae04ae +- 0x00070000 0x00000000 0x00000000 0x00000005 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- +- emc-table@75000 { +- reg = <75000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <75000>; +- nvidia,emc-registers = <0x00000005 0x0000000a +- 0x00000004 0x00000003 0x00000006 0x00000004 +- 0x00000002 0x00000009 0x00000003 0x00000003 +- 0x00000002 0x00000002 0x00000002 0x00000005 +- 0x00000003 0x00000008 0x0000000b 0x000000ff +- 0x00000000 0x00000003 0x00000003 0x00000003 +- 0x00000008 0x00000001 0x0000000a 0x0000000b +- 0x00000003 0x00000008 0x00000004 0x00000006 +- 0x00000002 0x00000138 0x00000000 0x00000000 +- 0x00000000 0x00000000 0x00000282 0xa0ae04ae +- 0x00070000 0x00000000 0x00000000 0x00000007 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- +- emc-table@150000 { +- reg = <150000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <150000>; +- nvidia,emc-registers = <0x00000009 0x00000014 +- 0x00000007 0x00000003 0x00000006 0x00000004 +- 0x00000002 0x00000009 0x00000003 0x00000003 +- 0x00000002 0x00000002 0x00000002 0x00000005 +- 0x00000003 0x00000008 0x0000000b 0x0000021f +- 0x00000000 0x00000003 0x00000003 0x00000003 +- 0x00000008 0x00000001 0x0000000a 0x00000015 +- 0x00000003 0x00000008 0x00000004 0x00000006 +- 0x00000002 0x00000270 0x00000000 0x00000001 +- 0x00000000 0x00000000 0x00000282 0xa07c04ae +- 0x007dd010 0x00000000 0x00000000 0x0000000e +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- +- emc-table@300000 { +- reg = <300000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <300000>; +- nvidia,emc-registers = <0x00000012 0x00000027 +- 0x0000000d 0x00000006 0x00000007 0x00000005 +- 0x00000003 0x00000009 0x00000006 0x00000006 +- 0x00000003 0x00000003 0x00000002 0x00000006 +- 0x00000003 0x00000009 0x0000000c 0x0000045f +- 0x00000000 0x00000004 0x00000004 0x00000006 +- 0x00000008 0x00000001 0x0000000e 0x0000002a +- 0x00000003 0x0000000f 0x00000007 0x00000005 +- 0x00000002 0x000004e1 0x00000005 0x00000002 +- 0x00000000 0x00000000 0x00000282 0xe059048b +- 0x007e2010 0x00000000 0x00000000 0x0000001b +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- }; +- +- emc-tables@3 { +- nvidia,ram-code = <3>; /* hynix-4gb */ +- reg = <3>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- emc-table@25000 { +- reg = <25000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <25000>; +- nvidia,emc-registers = <0x00000002 0x00000006 +- 0x00000003 0x00000003 0x00000006 0x00000004 +- 0x00000002 0x00000009 0x00000003 0x00000003 +- 0x00000002 0x00000002 0x00000002 0x00000004 +- 0x00000003 0x00000008 0x0000000b 0x0000004d +- 0x00000000 0x00000003 0x00000003 0x00000003 +- 0x00000008 0x00000001 0x0000000a 0x00000004 +- 0x00000003 0x00000008 0x00000004 0x00000006 +- 0x00000002 0x00000068 0x00000000 0x00000003 +- 0x00000000 0x00000000 0x00000282 0xa0ae04ae +- 0x0007c000 0x00000000 0x00000000 0x00000003 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- +- emc-table@50000 { +- reg = <50000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <50000>; +- nvidia,emc-registers = <0x00000003 0x00000007 +- 0x00000003 0x00000003 0x00000006 0x00000004 +- 0x00000002 0x00000009 0x00000003 0x00000003 +- 0x00000002 0x00000002 0x00000002 0x00000005 +- 0x00000003 0x00000008 0x0000000b 0x0000009f +- 0x00000000 0x00000003 0x00000003 0x00000003 +- 0x00000008 0x00000001 0x0000000a 0x00000007 +- 0x00000003 0x00000008 0x00000004 0x00000006 +- 0x00000002 0x000000d0 0x00000000 0x00000000 +- 0x00000000 0x00000000 0x00000282 0xa0ae04ae +- 0x0007c000 0x00078000 0x00000000 0x00000005 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- +- emc-table@75000 { +- reg = <75000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <75000>; +- nvidia,emc-registers = <0x00000005 0x0000000a +- 0x00000004 0x00000003 0x00000006 0x00000004 +- 0x00000002 0x00000009 0x00000003 0x00000003 +- 0x00000002 0x00000002 0x00000002 0x00000005 +- 0x00000003 0x00000008 0x0000000b 0x000000ff +- 0x00000000 0x00000003 0x00000003 0x00000003 +- 0x00000008 0x00000001 0x0000000a 0x0000000b +- 0x00000003 0x00000008 0x00000004 0x00000006 +- 0x00000002 0x00000138 0x00000000 0x00000000 +- 0x00000000 0x00000000 0x00000282 0xa0ae04ae +- 0x0007c000 0x00000000 0x00000000 0x00000007 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- +- emc-table@150000 { +- reg = <150000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <150000>; +- nvidia,emc-registers = <0x00000009 0x00000014 +- 0x00000007 0x00000003 0x00000006 0x00000004 +- 0x00000002 0x00000009 0x00000003 0x00000003 +- 0x00000002 0x00000002 0x00000002 0x00000005 +- 0x00000003 0x00000008 0x0000000b 0x0000021f +- 0x00000000 0x00000003 0x00000003 0x00000003 +- 0x00000008 0x00000001 0x0000000a 0x00000015 +- 0x00000003 0x00000008 0x00000004 0x00000006 +- 0x00000002 0x00000270 0x00000000 0x00000001 +- 0x00000000 0x00000000 0x00000282 0xa07c04ae +- 0x007e4010 0x00000000 0x00000000 0x0000000e +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- +- emc-table@300000 { +- reg = <300000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <300000>; +- nvidia,emc-registers = <0x00000012 0x00000027 +- 0x0000000d 0x00000006 0x00000007 0x00000005 +- 0x00000003 0x00000009 0x00000006 0x00000006 +- 0x00000003 0x00000003 0x00000002 0x00000006 +- 0x00000003 0x00000009 0x0000000c 0x0000045f +- 0x00000000 0x00000004 0x00000004 0x00000006 +- 0x00000008 0x00000001 0x0000000e 0x0000002a +- 0x00000003 0x0000000f 0x00000007 0x00000005 +- 0x00000002 0x000004e1 0x00000005 0x00000002 +- 0x00000000 0x00000000 0x00000282 0xe059048b +- 0x007e0010 0x00000000 0x00000000 0x0000001b +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- }; +- }; +-}; +- +-&emc_icc_dvfs_opp_table { +- /delete-node/ opp@666000000; +- /delete-node/ opp@760000000; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra20-colibri-eval-v3.dts b/scripts/dtc/include-prefixes/arm/tegra20-colibri-eval-v3.dts +deleted file mode 100644 +index a05fb3853da8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra20-colibri-eval-v3.dts ++++ /dev/null +@@ -1,262 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-/dts-v1/; +- +-#include +-#include "tegra20-colibri.dtsi" +- +-/ { +- model = "Toradex Colibri T20 on Colibri Evaluation Board"; +- compatible = "toradex,colibri_t20-eval-v3", "toradex,colibri_t20", +- "nvidia,tegra20"; +- +- aliases { +- rtc0 = "/i2c@7000c000/rtc@68"; +- rtc1 = "/i2c@7000d000/pmic@34"; +- rtc2 = "/rtc@7000e000"; +- serial0 = &uarta; +- serial1 = &uartd; +- serial2 = &uartb; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- host1x@50000000 { +- dc@54200000 { +- rgb { +- status = "okay"; +- nvidia,panel = <&panel>; +- }; +- }; +- +- hdmi@54280000 { +- status = "okay"; +- hdmi-supply = <®_5v0>; +- }; +- }; +- +- pinmux@70000014 { +- state_default: pinmux { +- bl-on { +- nvidia,tristate = ; +- }; +- +- ddc { +- nvidia,tristate = ; +- }; +- +- hotplug-detect { +- nvidia,tristate = ; +- }; +- +- i2c { +- nvidia,tristate = ; +- }; +- +- lcd { +- nvidia,tristate = ; +- }; +- +- lm1 { +- nvidia,tristate = ; +- }; +- +- mmc { +- nvidia,tristate = ; +- }; +- +- mmccd { +- nvidia,tristate = ; +- }; +- +- pwm-a-b { +- nvidia,tristate = ; +- }; +- +- pwm-c-d { +- nvidia,tristate = ; +- }; +- +- ssp { +- nvidia,tristate = ; +- }; +- +- uart-a { +- nvidia,tristate = ; +- }; +- +- uart-b { +- nvidia,tristate = ; +- }; +- +- uart-c { +- nvidia,tristate = ; +- }; +- +- usbh-pen { +- nvidia,tristate = ; +- }; +- }; +- }; +- +- /* Colibri UART-A */ +- serial@70006000 { +- status = "okay"; +- }; +- +- /* Colibri UART-C */ +- serial@70006040 { +- status = "okay"; +- }; +- +- /* Colibri UART-B */ +- serial@70006300 { +- status = "okay"; +- }; +- +- pwm@7000a000 { +- status = "okay"; +- }; +- +- /* +- * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier +- * board) +- */ +- i2c@7000c000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- /* M41T0M6 real time clock on carrier board */ +- rtc@68 { +- compatible = "st,m41t0"; +- reg = <0x68>; +- }; +- }; +- +- /* GEN2_I2C: unused */ +- +- /* CAM_I2C (I2C3): unused */ +- +- /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ +- i2c@7000c400 { +- status = "okay"; +- }; +- +- /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ +- usb@c5000000 { +- status = "okay"; +- dr_mode = "otg"; +- }; +- +- usb-phy@c5000000 { +- status = "okay"; +- vbus-supply = <®_usbc_vbus>; +- }; +- +- /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ +- usb@c5008000 { +- status = "okay"; +- }; +- +- usb-phy@c5008000 { +- status = "okay"; +- vbus-supply = <®_usbh_vbus>; +- }; +- +- /* SPI4: Colibri SSP */ +- spi@7000da00 { +- status = "okay"; +- spi-max-frequency = <25000000>; +- +- can@0 { +- compatible = "microchip,mcp2515"; +- reg = <0>; +- clocks = <&clk16m>; +- interrupt-parent = <&gpio>; +- /* CAN_INT */ +- interrupts = ; +- spi-max-frequency = <10000000>; +- vdd-supply = <®_3v3>; +- xceiver-supply = <®_5v0>; +- }; +- }; +- +- /* SD/MMC */ +- mmc@c8000600 { +- status = "okay"; +- bus-width = <4>; +- cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ +- no-1-8-v; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- brightness-levels = <255 128 64 32 16 8 4 0>; +- default-brightness-level = <6>; +- /* BL_ON */ +- enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>; +- power-supply = <®_3v3>; +- pwms = <&pwm 0 5000000>; /* PWM */ +- }; +- +- clk16m: osc3 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <16000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- wakeup { +- label = "SODIMM pin 45 wakeup"; +- gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- panel: panel { +- /* +- * edt,et057090dhu: EDT 5.7" LCD TFT +- * edt,et070080dh6: EDT 7.0" LCD TFT +- */ +- compatible = "edt,et057090dhu"; +- backlight = <&backlight>; +- power-supply = <®_3v3>; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3.3V_SW"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_5v0: regulator-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "5V_SW"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usbc_vbus: regulator-usbc-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_USB5"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <®_5v0>; +- }; +- +- /* USBH_PEN resp. USB_P_EN */ +- reg_usbh_vbus: regulator-usbh-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_USB[1-4]"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; +- vin-supply = <®_5v0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra20-colibri-iris.dts b/scripts/dtc/include-prefixes/arm/tegra20-colibri-iris.dts +deleted file mode 100644 +index 425494b9ed54..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra20-colibri-iris.dts ++++ /dev/null +@@ -1,244 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include "tegra20-colibri.dtsi" +- +-/ { +- model = "Toradex Colibri T20 on Iris"; +- compatible = "toradex,colibri_t20-iris", "toradex,colibri_t20", +- "nvidia,tegra20"; +- +- aliases { +- rtc0 = "/i2c@7000c000/rtc@68"; +- rtc1 = "/i2c@7000d000/pmic@34"; +- rtc2 = "/rtc@7000e000"; +- serial0 = &uarta; +- serial1 = &uartd; +- serial2 = &uartb; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- host1x@50000000 { +- dc@54200000 { +- rgb { +- status = "okay"; +- nvidia,panel = <&panel>; +- }; +- }; +- +- hdmi@54280000 { +- status = "okay"; +- hdmi-supply = <®_5v0>; +- }; +- }; +- +- pinmux@70000014 { +- state_default: pinmux { +- bl-on { +- nvidia,tristate = ; +- }; +- +- ddc { +- nvidia,tristate = ; +- }; +- +- hotplug-detect { +- nvidia,tristate = ; +- }; +- +- i2c { +- nvidia,tristate = ; +- }; +- +- lcd { +- nvidia,tristate = ; +- }; +- +- lm1 { +- nvidia,tristate = ; +- }; +- +- mmc { +- nvidia,tristate = ; +- }; +- +- mmccd { +- nvidia,tristate = ; +- }; +- +- pwm-a-b { +- nvidia,tristate = ; +- }; +- +- pwm-c-d { +- nvidia,tristate = ; +- }; +- +- ssp { +- nvidia,tristate = ; +- }; +- +- uart-a { +- nvidia,tristate = ; +- }; +- +- uart-b { +- nvidia,tristate = ; +- }; +- +- uart-c { +- nvidia,tristate = ; +- }; +- +- usbh-pen { +- nvidia,tristate = ; +- }; +- }; +- }; +- +- /* Colibri UART-A */ +- serial@70006000 { +- status = "okay"; +- }; +- +- /* Colibri UART-C */ +- serial@70006040 { +- status = "okay"; +- }; +- +- /* Colibri UART-B */ +- serial@70006300 { +- status = "okay"; +- }; +- +- pwm@7000a000 { +- status = "okay"; +- }; +- +- /* +- * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier +- * board) +- */ +- i2c@7000c000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- /* M41T0M6 real time clock on carrier board */ +- rtc@68 { +- compatible = "st,m41t0"; +- reg = <0x68>; +- }; +- }; +- +- /* GEN2_I2C: unused */ +- +- /* CAM_I2C (I2C3): unused */ +- +- /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ +- i2c@7000c400 { +- status = "okay"; +- }; +- +- /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ +- usb@c5000000 { +- status = "okay"; +- dr_mode = "otg"; +- }; +- +- usb-phy@c5000000 { +- status = "okay"; +- vbus-supply = <®_usbc_vbus>; +- }; +- +- /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ +- usb@c5008000 { +- status = "okay"; +- }; +- +- usb-phy@c5008000 { +- status = "okay"; +- vbus-supply = <®_usbh_vbus>; +- }; +- +- /* SPI4: Colibri SSP */ +- spi@7000da00 { +- status = "okay"; +- spi-max-frequency = <25000000>; +- }; +- +- /* SD/MMC */ +- mmc@c8000600 { +- status = "okay"; +- bus-width = <4>; +- cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ +- no-1-8-v; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- brightness-levels = <255 128 64 32 16 8 4 0>; +- default-brightness-level = <6>; +- /* BL_ON */ +- enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>; +- power-supply = <®_3v3>; +- pwms = <&pwm 0 5000000>; /* PWM */ +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- wakeup { +- label = "SODIMM pin 45 wakeup"; +- gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- panel: panel { +- /* +- * edt,et057090dhu: EDT 5.7" LCD TFT +- * edt,et070080dh6: EDT 7.0" LCD TFT +- */ +- compatible = "edt,et057090dhu"; +- backlight = <&backlight>; +- power-supply = <®_3v3>; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_5v0: regulator-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usbc_vbus: regulator-usbc-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_USB2"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <®_5v0>; +- }; +- +- /* USBH_PEN resp. USB_P_EN */ +- reg_usbh_vbus: regulator-usbh-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_USB1"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; +- vin-supply = <®_5v0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra20-colibri.dtsi b/scripts/dtc/include-prefixes/arm/tegra20-colibri.dtsi +deleted file mode 100644 +index 585a5b441cf6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra20-colibri.dtsi ++++ /dev/null +@@ -1,772 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "tegra20.dtsi" +- +-/* +- * Toradex Colibri T20 Module Device Tree +- * Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A; +- * Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A; +- * Colibri T20 512MB IT V1.2A +- */ +-/ { +- memory@0 { +- /* +- * Set memory to 256 MB to be safe as this could be used on +- * 256 or 512 MB module. It is expected from bootloader +- * to fix this up for 512 MB version. +- */ +- reg = <0x00000000 0x10000000>; +- }; +- +- host1x@50000000 { +- hdmi@54280000 { +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = +- <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; +- pll-supply = <®_1v8_avdd_hdmi_pll>; +- vdd-supply = <®_3v3_avdd_hdmi>; +- }; +- }; +- +- pinmux@70000014 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- /* Analogue Audio AC97 to WM9712 (On-module) */ +- audio-refclk { +- nvidia,pins = "cdev1"; +- nvidia,function = "plla_out"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- dap3 { +- nvidia,pins = "dap3"; +- nvidia,function = "dap3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* +- * AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ +- * (All on-module), SODIMM Pin 45 Wakeup +- */ +- gpio-uac { +- nvidia,pins = "uac"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* +- * Buffer Enables for nPWE and RDnWR (On-module, +- * see GPIO hogging further down below) +- */ +- gpio-pta { +- nvidia,pins = "pta"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* +- * CLK_32K_OUT, CORE_PWR_REQ, CPU_PWR_REQ, PWR_INT_N, +- * SYS_CLK_REQ (All on-module) +- */ +- pmc { +- nvidia,pins = "pmc"; +- nvidia,function = "pwr_on"; +- nvidia,tristate = ; +- }; +- +- /* +- * Colibri Address/Data Bus (GMI) +- * Note: spid and spie optionally used for SPI1 +- */ +- gmi { +- nvidia,pins = "atc", "atd", "ate", "dap1", +- "dap2", "dap4", "gmd", "gpu", +- "irrx", "irtx", "spia", "spib", +- "spic", "spid", "spie", "uca", +- "ucb"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- /* Further pins may be used as GPIOs */ +- gmi-gpio1 { +- nvidia,pins = "lpw0", "lsc1", "lsck", "lsda"; +- nvidia,function = "hdmi"; +- nvidia,tristate = ; +- }; +- gmi-gpio2 { +- nvidia,pins = "lcsn", "ldc", "lm0", "lsdi"; +- nvidia,function = "rsvd4"; +- nvidia,tristate = ; +- }; +- +- /* Colibri BL_ON */ +- bl-on { +- nvidia,pins = "dta"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri Backlight PWM, PWM */ +- pwm-a-b { +- nvidia,pins = "sdc"; +- nvidia,function = "pwm"; +- nvidia,tristate = ; +- }; +- +- /* Colibri DDC */ +- ddc { +- nvidia,pins = "ddc"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* +- * Colibri EXT_IO* +- * Note: dtf optionally used for I2C3 +- */ +- ext-io { +- nvidia,pins = "dtf", "spdi"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* +- * Colibri Ethernet (On-module) +- * ULPI EHCI instance 1 USB2_DP/N -> AX88772B +- */ +- ulpi { +- nvidia,pins = "uaa", "uab", "uda"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- ulpi-refclk { +- nvidia,pins = "cdev2"; +- nvidia,function = "pllp_out4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri HOTPLUG_DETECT (HDMI) */ +- hotplug-detect { +- nvidia,pins = "hdint"; +- nvidia,function = "hdmi"; +- nvidia,tristate = ; +- }; +- +- /* Colibri I2C */ +- i2c { +- nvidia,pins = "rm"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* +- * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE +- * today's display need DE, disable LCD_M1 +- */ +- lm1 { +- nvidia,pins = "lm1"; +- nvidia,function = "rsvd3"; +- nvidia,tristate = ; +- }; +- +- /* Colibri LCD (L_* resp. LDD<*>) */ +- lcd { +- nvidia,pins = "ld0", "ld1", "ld2", "ld3", +- "ld4", "ld5", "ld6", "ld7", +- "ld8", "ld9", "ld10", "ld11", +- "ld12", "ld13", "ld14", "ld15", +- "ld16", "ld17", "lhs", "lsc0", +- "lspi", "lvs"; +- nvidia,function = "displaya"; +- nvidia,tristate = ; +- }; +- /* Colibri LCD (Optional 24 BPP Support) */ +- lcd-24 { +- nvidia,pins = "ldi", "lhp0", "lhp1", "lhp2", +- "lpp", "lvp1"; +- nvidia,function = "displaya"; +- nvidia,tristate = ; +- }; +- +- /* Colibri MMC */ +- mmc { +- nvidia,pins = "atb", "gma"; +- nvidia,function = "sdio4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri MMCCD */ +- mmccd { +- nvidia,pins = "gmb"; +- nvidia,function = "gmi_int"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri MMC (Optional 8-bit) */ +- mmc-8bit { +- nvidia,pins = "gme"; +- nvidia,function = "sdio4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* +- * Colibri Parallel Camera (Optional) +- * pins multiplexed with others and therefore disabled +- * Note: dta used for BL_ON by default +- */ +- cif-mclk { +- nvidia,pins = "csus"; +- nvidia,function = "vi_sensor_clk"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- cif { +- nvidia,pins = "dtb", "dtc", "dtd"; +- nvidia,function = "vi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri PWM, PWM */ +- pwm-c-d { +- nvidia,pins = "sdb", "sdd"; +- nvidia,function = "pwm"; +- nvidia,tristate = ; +- }; +- +- /* Colibri SSP */ +- ssp { +- nvidia,pins = "slxa", "slxc", "slxd", "slxk"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri UART-A */ +- uart-a { +- nvidia,pins = "sdio1"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- uart-a-dsr { +- nvidia,pins = "lpw1"; +- nvidia,function = "rsvd3"; +- nvidia,tristate = ; +- }; +- uart-a-dcd { +- nvidia,pins = "lpw2"; +- nvidia,function = "hdmi"; +- nvidia,tristate = ; +- }; +- +- /* Colibri UART-B */ +- uart-b { +- nvidia,pins = "gmc"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri UART-C */ +- uart-c { +- nvidia,pins = "uad"; +- nvidia,function = "irda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri USB_CDET */ +- usb-cdet { +- nvidia,pins = "spdo"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri USBH_OC */ +- usbh-oc { +- nvidia,pins = "spih"; +- nvidia,function = "spi2_alt"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri USBH_PEN */ +- usbh-pen { +- nvidia,pins = "spig"; +- nvidia,function = "spi2_alt"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri VGA not supported */ +- vga { +- nvidia,pins = "crtp"; +- nvidia,function = "crt"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* I2C3 (Optional) */ +- i2c3 { +- nvidia,pins = "dtf"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* JTAG_RTCK */ +- jtag-rtck { +- nvidia,pins = "gpu7"; +- nvidia,function = "rtck"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* +- * LAN_RESET, LAN_EXT_WAKEUP and LAN_PME +- * (All On-module) +- */ +- gpio-gpv { +- nvidia,pins = "gpv"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* +- * LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN +- * (All On-module); Colibri CAN_INT +- */ +- gpio-dte { +- nvidia,pins = "dte"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* NAND (On-module) */ +- nand { +- nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", +- "kbce", "kbcf"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Onewire (Optional) */ +- owr { +- nvidia,pins = "owc"; +- nvidia,function = "owr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Power I2C (On-module) */ +- i2cp { +- nvidia,pins = "i2cp"; +- nvidia,function = "i2cp"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* RESET_OUT */ +- reset-out { +- nvidia,pins = "ata"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* +- * SPI1 (Optional) +- * Note: spid and spie used for Colibri Address/Data +- * Bus (GMI) +- */ +- spi1 { +- nvidia,pins = "spid", "spie", "spif"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* +- * THERMD_ALERT# (On-module), unlatched I2C address pin +- * of LM95245 temperature sensor therefore requires +- * disabling for now +- */ +- lvp0 { +- nvidia,pins = "lvp0"; +- nvidia,function = "rsvd3"; +- nvidia,tristate = ; +- }; +- }; +- }; +- +- tegra_ac97: ac97@70002000 { +- status = "okay"; +- nvidia,codec-reset-gpio = +- <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>; +- nvidia,codec-sync-gpio = +- <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>; +- }; +- +- serial@70006040 { +- compatible = "nvidia,tegra20-hsuart"; +- }; +- +- serial@70006300 { +- compatible = "nvidia,tegra20-hsuart"; +- }; +- +- nand-controller@70008000 { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- nand-bus-width = <8>; +- nand-on-flash-bbt; +- nand-ecc-algo = "bch"; +- nand-is-boot-medium; +- nand-ecc-maximize; +- wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; +- }; +- }; +- +- /* +- * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier +- * board) +- */ +- i2c@7000c000 { +- clock-frequency = <400000>; +- }; +- +- /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */ +- hdmi_ddc: i2c@7000c400 { +- clock-frequency = <10000>; +- }; +- +- /* GEN2_I2C: unused */ +- +- /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */ +- +- /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */ +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <100000>; +- +- pmic@34 { +- compatible = "ti,tps6586x"; +- reg = <0x34>; +- interrupts = ; +- ti,system-power-controller; +- #gpio-cells = <2>; +- gpio-controller; +- sys-supply = <®_module_3v3>; +- vin-sm0-supply = <®_3v3_vsys>; +- vin-sm1-supply = <®_3v3_vsys>; +- vin-sm2-supply = <®_3v3_vsys>; +- vinldo01-supply = <®_1v8_vdd_ddr2>; +- vinldo23-supply = <®_module_3v3>; +- vinldo4-supply = <®_module_3v3>; +- vinldo678-supply = <®_module_3v3>; +- vinldo9-supply = <®_module_3v3>; +- +- regulators { +- reg_3v3_vsys: sys { +- regulator-name = "VSYS_3.3V"; +- regulator-always-on; +- }; +- +- sm0 { +- regulator-name = "VDD_CORE_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- sm1 { +- regulator-name = "VDD_CPU_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- reg_1v8_vdd_ddr2: sm2 { +- regulator-name = "VDD_DDR2_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- /* LDO0 is not connected to anything */ +- +- /* +- * +3.3V_ENABLE_N switching via FET: +- * AVDD_AUDIO_S and +3.3V +- * see also +3.3V fixed supply +- */ +- ldo1 { +- regulator-name = "AVDD_PLL_1.1V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- ldo2 { +- regulator-name = "VDD_RTC_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- /* LDO3 is not connected to anything */ +- +- ldo4 { +- regulator-name = "VDDIO_SYS_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- /* Switched via FET from regular +3.3V */ +- ldo5 { +- regulator-name = "+3.3V_USB"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo6 { +- regulator-name = "AVDD_VDAC_2.85V"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- reg_3v3_avdd_hdmi: ldo7 { +- regulator-name = "AVDD_HDMI_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_1v8_avdd_hdmi_pll: ldo8 { +- regulator-name = "AVDD_HDMI_PLL_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo9 { +- regulator-name = "VDDIO_RX_DDR_2.85V"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- }; +- +- ldo_rtc { +- regulator-name = "VCC_BATT"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +- +- /* LM95245 temperature sensor */ +- temp-sensor@4c { +- compatible = "national,lm95245"; +- reg = <0x4c>; +- }; +- }; +- +- pmc@7000e400 { +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <5000>; +- nvidia,cpu-pwr-off-time = <5000>; +- nvidia,core-pwr-good-time = <3845 3845>; +- nvidia,core-pwr-off-time = <3875>; +- nvidia,sys-clock-req-active-high; +- +- /* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */ +- i2c-thermtrip { +- nvidia,i2c-controller-id = <3>; +- nvidia,bus-addr = <0x34>; +- nvidia,reg-addr = <0x14>; +- nvidia,reg-data = <0x8>; +- }; +- }; +- +- memory-controller@7000f400 { +- emc-table@83250 { +- reg = <83250>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <83250>; +- nvidia,emc-registers = <0x00000005 0x00000011 +- 0x00000004 0x00000002 0x00000004 0x00000004 +- 0x00000001 0x0000000a 0x00000002 0x00000002 +- 0x00000001 0x00000001 0x00000003 0x00000004 +- 0x00000003 0x00000009 0x0000000c 0x0000025f +- 0x00000000 0x00000003 0x00000003 0x00000002 +- 0x00000002 0x00000001 0x00000008 0x000000c8 +- 0x00000003 0x00000005 0x00000003 0x0000000c +- 0x00000002 0x00000000 0x00000000 0x00000002 +- 0x00000000 0x00000000 0x00000083 0x00520006 +- 0x00000010 0x00000008 0x00000000 0x00000000 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- emc-table@133200 { +- reg = <133200>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <133200>; +- nvidia,emc-registers = <0x00000008 0x00000019 +- 0x00000006 0x00000002 0x00000004 0x00000004 +- 0x00000001 0x0000000a 0x00000002 0x00000002 +- 0x00000002 0x00000001 0x00000003 0x00000004 +- 0x00000003 0x00000009 0x0000000c 0x0000039f +- 0x00000000 0x00000003 0x00000003 0x00000002 +- 0x00000002 0x00000001 0x00000008 0x000000c8 +- 0x00000003 0x00000007 0x00000003 0x0000000c +- 0x00000002 0x00000000 0x00000000 0x00000002 +- 0x00000000 0x00000000 0x00000083 0x00510006 +- 0x00000010 0x00000008 0x00000000 0x00000000 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- emc-table@166500 { +- reg = <166500>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <166500>; +- nvidia,emc-registers = <0x0000000a 0x00000021 +- 0x00000008 0x00000003 0x00000004 0x00000004 +- 0x00000002 0x0000000a 0x00000003 0x00000003 +- 0x00000002 0x00000001 0x00000003 0x00000004 +- 0x00000003 0x00000009 0x0000000c 0x000004df +- 0x00000000 0x00000003 0x00000003 0x00000003 +- 0x00000003 0x00000001 0x00000009 0x000000c8 +- 0x00000003 0x00000009 0x00000004 0x0000000c +- 0x00000002 0x00000000 0x00000000 0x00000002 +- 0x00000000 0x00000000 0x00000083 0x004f0006 +- 0x00000010 0x00000008 0x00000000 0x00000000 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- emc-table@333000 { +- reg = <333000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <333000>; +- nvidia,emc-registers = <0x00000014 0x00000041 +- 0x0000000f 0x00000005 0x00000004 0x00000005 +- 0x00000003 0x0000000a 0x00000005 0x00000005 +- 0x00000004 0x00000001 0x00000003 0x00000004 +- 0x00000003 0x00000009 0x0000000c 0x000009ff +- 0x00000000 0x00000003 0x00000003 0x00000005 +- 0x00000005 0x00000001 0x0000000e 0x000000c8 +- 0x00000003 0x00000011 0x00000006 0x0000000c +- 0x00000002 0x00000000 0x00000000 0x00000002 +- 0x00000000 0x00000000 0x00000083 0x00380006 +- 0x00000010 0x00000008 0x00000000 0x00000000 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- }; +- +- /* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */ +- usb@c5004000 { +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- asix@1 { +- reg = <1>; +- local-mac-address = [00 00 00 00 00 00]; +- }; +- }; +- +- usb-phy@c5004000 { +- status = "okay"; +- nvidia,phy-reset-gpio = +- <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; +- vbus-supply = <®_lan_v_bus>; +- }; +- +- clk32k_in: xtal3 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- reg_lan_v_bus: regulator-lan-v-bus { +- compatible = "regulator-fixed"; +- regulator-name = "LAN_V_BUS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; +- }; +- +- reg_module_3v3: regulator-module-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- sound { +- compatible = "nvidia,tegra-audio-wm9712-colibri_t20", +- "nvidia,tegra-audio-wm9712"; +- nvidia,model = "Toradex Colibri T20"; +- nvidia,audio-routing = +- "Headphone", "HPOUTL", +- "Headphone", "HPOUTR", +- "LineIn", "LINEINL", +- "LineIn", "LINEINR", +- "Mic", "MIC1"; +- nvidia,ac97-controller = <&tegra_ac97>; +- clocks = <&tegra_car TEGRA20_CLK_PLL_A>, +- <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA20_CLK_CDEV1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- }; +-}; +- +-&emc_icc_dvfs_opp_table { +- /delete-node/ opp@760000000; +-}; +- +-&gpio { +- lan-reset-n { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "LAN_RESET#"; +- }; +- +- /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ +- npwe { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "Tri-state nPWE"; +- }; +- +- /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */ +- rdnwr { +- gpio-hog; +- gpios = ; +- output-low; +- line-name = "Not tri-state RDnWR"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra20-cpu-opp-microvolt.dtsi b/scripts/dtc/include-prefixes/arm/tegra20-cpu-opp-microvolt.dtsi +deleted file mode 100644 +index 6f3e8c5fc5f0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra20-cpu-opp-microvolt.dtsi ++++ /dev/null +@@ -1,165 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/ { +- cpu0_opp_table: cpu_opp_table0 { +- opp@216000000,750 { +- opp-microvolt = <750000 750000 1125000>; +- }; +- +- opp@216000000,800 { +- opp-microvolt = <800000 800000 1125000>; +- }; +- +- opp@312000000,750 { +- opp-microvolt = <750000 750000 1125000>; +- }; +- +- opp@312000000,800 { +- opp-microvolt = <800000 800000 1125000>; +- }; +- +- opp@456000000,750 { +- opp-microvolt = <750000 750000 1125000>; +- }; +- +- opp@456000000,800 { +- opp-microvolt = <800000 800000 1125000>; +- }; +- +- opp@456000000,825 { +- opp-microvolt = <825000 825000 1125000>; +- }; +- +- opp@608000000,750 { +- opp-microvolt = <750000 750000 1125000>; +- }; +- +- opp@608000000,800 { +- opp-microvolt = <800000 800000 1125000>; +- }; +- +- opp@608000000,825 { +- opp-microvolt = <825000 825000 1125000>; +- }; +- +- opp@608000000,850 { +- opp-microvolt = <850000 850000 1125000>; +- }; +- +- opp@608000000,900 { +- opp-microvolt = <900000 900000 1125000>; +- }; +- +- opp@760000000,775 { +- opp-microvolt = <775000 775000 1125000>; +- }; +- +- opp@760000000,800 { +- opp-microvolt = <800000 800000 1125000>; +- }; +- +- opp@760000000,850 { +- opp-microvolt = <850000 850000 1125000>; +- }; +- +- opp@760000000,875 { +- opp-microvolt = <875000 875000 1125000>; +- }; +- +- opp@760000000,900 { +- opp-microvolt = <900000 900000 1125000>; +- }; +- +- opp@760000000,975 { +- opp-microvolt = <975000 975000 1125000>; +- }; +- +- opp@816000000,800 { +- opp-microvolt = <800000 800000 1125000>; +- }; +- +- opp@816000000,850 { +- opp-microvolt = <850000 850000 1125000>; +- }; +- +- opp@816000000,875 { +- opp-microvolt = <875000 875000 1125000>; +- }; +- +- opp@816000000,950 { +- opp-microvolt = <950000 950000 1125000>; +- }; +- +- opp@816000000,1000 { +- opp-microvolt = <1000000 1000000 1125000>; +- }; +- +- opp@912000000,850 { +- opp-microvolt = <850000 850000 1125000>; +- }; +- +- opp@912000000,900 { +- opp-microvolt = <900000 900000 1125000>; +- }; +- +- opp@912000000,925 { +- opp-microvolt = <925000 925000 1125000>; +- }; +- +- opp@912000000,950 { +- opp-microvolt = <950000 950000 1125000>; +- }; +- +- opp@912000000,1000 { +- opp-microvolt = <1000000 1000000 1125000>; +- }; +- +- opp@912000000,1050 { +- opp-microvolt = <1050000 1050000 1125000>; +- }; +- +- opp@1000000000,875 { +- opp-microvolt = <875000 875000 1125000>; +- }; +- +- opp@1000000000,900 { +- opp-microvolt = <900000 900000 1125000>; +- }; +- +- opp@1000000000,950 { +- opp-microvolt = <950000 950000 1125000>; +- }; +- +- opp@1000000000,975 { +- opp-microvolt = <975000 975000 1125000>; +- }; +- +- opp@1000000000,1000 { +- opp-microvolt = <1000000 1000000 1125000>; +- }; +- +- opp@1000000000,1025 { +- opp-microvolt = <1025000 1025000 1125000>; +- }; +- +- opp@1000000000,1100 { +- opp-microvolt = <1100000 1100000 1125000>; +- }; +- +- opp@1200000000,1000 { +- opp-microvolt = <1000000 1000000 1125000>; +- }; +- +- opp@1200000000,1050 { +- opp-microvolt = <1050000 1050000 1125000>; +- }; +- +- opp@1200000000,1100 { +- opp-microvolt = <1100000 1100000 1125000>; +- }; +- +- opp@1200000000,1125 { +- opp-microvolt = <1125000 1125000 1125000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra20-cpu-opp.dtsi b/scripts/dtc/include-prefixes/arm/tegra20-cpu-opp.dtsi +deleted file mode 100644 +index 135de316383b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra20-cpu-opp.dtsi ++++ /dev/null +@@ -1,253 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/ { +- cpu0_opp_table: cpu_opp_table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp@216000000,750 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x0F 0x0003>; +- opp-hz = /bits/ 64 <216000000>; +- opp-suspend; +- }; +- +- opp@216000000,800 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x0F 0x0004>; +- opp-hz = /bits/ 64 <216000000>; +- opp-suspend; +- }; +- +- opp@312000000,750 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x0F 0x0003>; +- opp-hz = /bits/ 64 <312000000>; +- }; +- +- opp@312000000,800 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x0F 0x0004>; +- opp-hz = /bits/ 64 <312000000>; +- }; +- +- opp@456000000,750 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x0C 0x0003>; +- opp-hz = /bits/ 64 <456000000>; +- }; +- +- opp@456000000,800 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x03 0x0006>, <0x04 0x0004>, +- <0x08 0x0004>; +- opp-hz = /bits/ 64 <456000000>; +- }; +- +- opp@456000000,825 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x03 0x0001>; +- opp-hz = /bits/ 64 <456000000>; +- }; +- +- opp@608000000,750 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x08 0x0003>; +- opp-hz = /bits/ 64 <608000000>; +- }; +- +- opp@608000000,800 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x04 0x0006>, <0x08 0x0004>; +- opp-hz = /bits/ 64 <608000000>; +- }; +- +- opp@608000000,825 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x04 0x0001>; +- opp-hz = /bits/ 64 <608000000>; +- }; +- +- opp@608000000,850 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x03 0x0006>; +- opp-hz = /bits/ 64 <608000000>; +- }; +- +- opp@608000000,900 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x03 0x0001>; +- opp-hz = /bits/ 64 <608000000>; +- }; +- +- opp@760000000,775 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x08 0x0003>; +- opp-hz = /bits/ 64 <760000000>; +- }; +- +- opp@760000000,800 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x08 0x0004>; +- opp-hz = /bits/ 64 <760000000>; +- }; +- +- opp@760000000,850 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x04 0x0006>; +- opp-hz = /bits/ 64 <760000000>; +- }; +- +- opp@760000000,875 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x04 0x0001>, <0x02 0x0002>, +- <0x01 0x0004>, <0x02 0x0004>; +- opp-hz = /bits/ 64 <760000000>; +- }; +- +- opp@760000000,900 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x01 0x0002>; +- opp-hz = /bits/ 64 <760000000>; +- }; +- +- opp@760000000,975 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x03 0x0001>; +- opp-hz = /bits/ 64 <760000000>; +- }; +- +- opp@816000000,800 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x08 0x0007>; +- opp-hz = /bits/ 64 <816000000>; +- }; +- +- opp@816000000,850 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x04 0x0002>; +- opp-hz = /bits/ 64 <816000000>; +- }; +- +- opp@816000000,875 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x04 0x0005>; +- opp-hz = /bits/ 64 <816000000>; +- }; +- +- opp@816000000,950 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x03 0x0006>; +- opp-hz = /bits/ 64 <816000000>; +- }; +- +- opp@816000000,1000 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x03 0x0001>; +- opp-hz = /bits/ 64 <816000000>; +- }; +- +- opp@912000000,850 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x08 0x0007>; +- opp-hz = /bits/ 64 <912000000>; +- }; +- +- opp@912000000,900 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x04 0x0002>; +- opp-hz = /bits/ 64 <912000000>; +- }; +- +- opp@912000000,925 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x04 0x0001>; +- opp-hz = /bits/ 64 <912000000>; +- }; +- +- opp@912000000,950 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x02 0x0006>, <0x01 0x0004>, +- <0x04 0x0004>; +- opp-hz = /bits/ 64 <912000000>; +- }; +- +- opp@912000000,1000 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x01 0x0002>; +- opp-hz = /bits/ 64 <912000000>; +- }; +- +- opp@912000000,1050 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x03 0x0001>; +- opp-hz = /bits/ 64 <912000000>; +- }; +- +- opp@1000000000,875 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x08 0x0007>; +- opp-hz = /bits/ 64 <1000000000>; +- }; +- +- opp@1000000000,900 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x04 0x0002>; +- opp-hz = /bits/ 64 <1000000000>; +- }; +- +- opp@1000000000,950 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x04 0x0004>; +- opp-hz = /bits/ 64 <1000000000>; +- }; +- +- opp@1000000000,975 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x04 0x0001>; +- opp-hz = /bits/ 64 <1000000000>; +- }; +- +- opp@1000000000,1000 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x02 0x0006>, <0x01 0x0004>; +- opp-hz = /bits/ 64 <1000000000>; +- }; +- +- opp@1000000000,1025 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x01 0x0002>; +- opp-hz = /bits/ 64 <1000000000>; +- }; +- +- opp@1000000000,1100 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x03 0x0001>; +- opp-hz = /bits/ 64 <1000000000>; +- }; +- +- opp@1200000000,1000 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x08 0x0004>; +- opp-hz = /bits/ 64 <1200000000>; +- }; +- +- opp@1200000000,1050 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x04 0x0004>; +- opp-hz = /bits/ 64 <1200000000>; +- }; +- +- opp@1200000000,1100 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x02 0x0004>; +- opp-hz = /bits/ 64 <1200000000>; +- }; +- +- opp@1200000000,1125 { +- clock-latency-ns = <400000>; +- opp-supported-hw = <0x01 0x0004>; +- opp-hz = /bits/ 64 <1200000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra20-harmony.dts b/scripts/dtc/include-prefixes/arm/tegra20-harmony.dts +deleted file mode 100644 +index ae4312eedcbd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra20-harmony.dts ++++ /dev/null +@@ -1,762 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include "tegra20.dtsi" +- +-/ { +- model = "NVIDIA Tegra20 Harmony evaluation board"; +- compatible = "nvidia,harmony", "nvidia,tegra20"; +- +- aliases { +- rtc0 = "/i2c@7000d000/tps6586x@34"; +- rtc1 = "/rtc@7000e000"; +- serial0 = &uartd; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- reg = <0x00000000 0x40000000>; +- }; +- +- host1x@50000000 { +- dc@54200000 { +- rgb { +- status = "okay"; +- +- nvidia,panel = <&panel>; +- }; +- }; +- +- hdmi@54280000 { +- status = "okay"; +- +- hdmi-supply = <&vdd_5v0_hdmi>; +- vdd-supply = <&hdmi_vdd_reg>; +- pll-supply = <&hdmi_pll_reg>; +- +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) +- GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- pinmux@70000014 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- ata { +- nvidia,pins = "ata"; +- nvidia,function = "ide"; +- }; +- atb { +- nvidia,pins = "atb", "gma", "gme"; +- nvidia,function = "sdio4"; +- }; +- atc { +- nvidia,pins = "atc"; +- nvidia,function = "nand"; +- }; +- atd { +- nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", +- "spia", "spib", "spic"; +- nvidia,function = "gmi"; +- }; +- cdev1 { +- nvidia,pins = "cdev1"; +- nvidia,function = "plla_out"; +- }; +- cdev2 { +- nvidia,pins = "cdev2"; +- nvidia,function = "pllp_out4"; +- }; +- crtp { +- nvidia,pins = "crtp"; +- nvidia,function = "crt"; +- }; +- csus { +- nvidia,pins = "csus"; +- nvidia,function = "vi_sensor_clk"; +- }; +- dap1 { +- nvidia,pins = "dap1"; +- nvidia,function = "dap1"; +- }; +- dap2 { +- nvidia,pins = "dap2"; +- nvidia,function = "dap2"; +- }; +- dap3 { +- nvidia,pins = "dap3"; +- nvidia,function = "dap3"; +- }; +- dap4 { +- nvidia,pins = "dap4"; +- nvidia,function = "dap4"; +- }; +- ddc { +- nvidia,pins = "ddc"; +- nvidia,function = "i2c2"; +- }; +- dta { +- nvidia,pins = "dta", "dtd"; +- nvidia,function = "sdio2"; +- }; +- dtb { +- nvidia,pins = "dtb", "dtc", "dte"; +- nvidia,function = "rsvd1"; +- }; +- dtf { +- nvidia,pins = "dtf"; +- nvidia,function = "i2c3"; +- }; +- gmc { +- nvidia,pins = "gmc"; +- nvidia,function = "uartd"; +- }; +- gpu7 { +- nvidia,pins = "gpu7"; +- nvidia,function = "rtck"; +- }; +- gpv { +- nvidia,pins = "gpv", "slxa", "slxk"; +- nvidia,function = "pcie"; +- }; +- hdint { +- nvidia,pins = "hdint", "pta"; +- nvidia,function = "hdmi"; +- }; +- i2cp { +- nvidia,pins = "i2cp"; +- nvidia,function = "i2cp"; +- }; +- irrx { +- nvidia,pins = "irrx", "irtx"; +- nvidia,function = "uarta"; +- }; +- kbca { +- nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", +- "kbce", "kbcf"; +- nvidia,function = "kbc"; +- }; +- lcsn { +- nvidia,pins = "lcsn", "ld0", "ld1", "ld2", +- "ld3", "ld4", "ld5", "ld6", "ld7", +- "ld8", "ld9", "ld10", "ld11", "ld12", +- "ld13", "ld14", "ld15", "ld16", "ld17", +- "ldc", "ldi", "lhp0", "lhp1", "lhp2", +- "lhs", "lm0", "lm1", "lpp", "lpw0", +- "lpw1", "lpw2", "lsc0", "lsc1", "lsck", +- "lsda", "lsdi", "lspi", "lvp0", "lvp1", +- "lvs"; +- nvidia,function = "displaya"; +- }; +- owc { +- nvidia,pins = "owc", "spdi", "spdo", "uac"; +- nvidia,function = "rsvd2"; +- }; +- pmc { +- nvidia,pins = "pmc"; +- nvidia,function = "pwr_on"; +- }; +- rm { +- nvidia,pins = "rm"; +- nvidia,function = "i2c1"; +- }; +- sdb { +- nvidia,pins = "sdb", "sdc", "sdd"; +- nvidia,function = "pwm"; +- }; +- sdio1 { +- nvidia,pins = "sdio1"; +- nvidia,function = "sdio1"; +- }; +- slxc { +- nvidia,pins = "slxc", "slxd"; +- nvidia,function = "spdif"; +- }; +- spid { +- nvidia,pins = "spid", "spie", "spif"; +- nvidia,function = "spi1"; +- }; +- spig { +- nvidia,pins = "spig", "spih"; +- nvidia,function = "spi2_alt"; +- }; +- uaa { +- nvidia,pins = "uaa", "uab", "uda"; +- nvidia,function = "ulpi"; +- }; +- uad { +- nvidia,pins = "uad"; +- nvidia,function = "irda"; +- }; +- uca { +- nvidia,pins = "uca", "ucb"; +- nvidia,function = "uartc"; +- }; +- conf_ata { +- nvidia,pins = "ata", "atb", "atc", "atd", "ate", +- "cdev1", "cdev2", "dap1", "dtb", "gma", +- "gmb", "gmc", "gmd", "gme", "gpu7", +- "gpv", "i2cp", "pta", "rm", "slxa", +- "slxk", "spia", "spib", "uac"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_ck32 { +- nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", +- "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; +- nvidia,pull = ; +- }; +- conf_csus { +- nvidia,pins = "csus", "spid", "spif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_crtp { +- nvidia,pins = "crtp", "dap2", "dap3", "dap4", +- "dtc", "dte", "dtf", "gpu", "sdio1", +- "slxc", "slxd", "spdi", "spdo", "spig", +- "uda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_ddc { +- nvidia,pins = "ddc", "dta", "dtd", "kbca", +- "kbcb", "kbcc", "kbcd", "kbce", "kbcf", +- "sdc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_hdint { +- nvidia,pins = "hdint", "lcsn", "ldc", "lm1", +- "lpw1", "lsc1", "lsck", "lsda", "lsdi", +- "lvp0", "owc", "sdb"; +- nvidia,tristate = ; +- }; +- conf_irrx { +- nvidia,pins = "irrx", "irtx", "sdd", "spic", +- "spie", "spih", "uaa", "uab", "uad", +- "uca", "ucb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_lc { +- nvidia,pins = "lc", "ls"; +- nvidia,pull = ; +- }; +- conf_ld0 { +- nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", +- "ld5", "ld6", "ld7", "ld8", "ld9", +- "ld10", "ld11", "ld12", "ld13", "ld14", +- "ld15", "ld16", "ld17", "ldi", "lhp0", +- "lhp1", "lhp2", "lhs", "lm0", "lpp", +- "lpw0", "lpw2", "lsc0", "lspi", "lvp1", +- "lvs", "pmc"; +- nvidia,tristate = ; +- }; +- conf_ld17_0 { +- nvidia,pins = "ld17_0", "ld19_18", "ld21_20", +- "ld23_22"; +- nvidia,pull = ; +- }; +- }; +- }; +- +- i2s@70002800 { +- status = "okay"; +- }; +- +- serial@70006300 { +- status = "okay"; +- }; +- +- pwm: pwm@7000a000 { +- status = "okay"; +- }; +- +- i2c@7000c000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- wm8903: wm8903@1a { +- compatible = "wlf,wm8903"; +- reg = <0x1a>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- micdet-cfg = <0>; +- micdet-delay = <100>; +- gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; +- }; +- }; +- +- hdmi_ddc: i2c@7000c400 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- i2c@7000c500 { +- status = "okay"; +- clock-frequency = <400000>; +- }; +- +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- pmic: tps6586x@34 { +- compatible = "ti,tps6586x"; +- reg = <0x34>; +- interrupts = ; +- +- ti,system-power-controller; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- sys-supply = <&vdd_5v0_reg>; +- vin-sm0-supply = <&sys_reg>; +- vin-sm1-supply = <&sys_reg>; +- vin-sm2-supply = <&sys_reg>; +- vinldo01-supply = <&sm2_reg>; +- vinldo23-supply = <&sm2_reg>; +- vinldo4-supply = <&sm2_reg>; +- vinldo678-supply = <&sm2_reg>; +- vinldo9-supply = <&sm2_reg>; +- +- regulators { +- sys_reg: sys { +- regulator-name = "vdd_sys"; +- regulator-always-on; +- }; +- +- sm0 { +- regulator-name = "vdd_sm0,vdd_core"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- sm1 { +- regulator-name = "vdd_sm1,vdd_cpu"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- sm2_reg: sm2 { +- regulator-name = "vdd_sm2,vin_ldo*"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- regulator-always-on; +- }; +- +- pci_clk_reg: ldo0 { +- regulator-name = "vdd_ldo0,vddio_pex_clk"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo1 { +- regulator-name = "vdd_ldo1,avdd_pll*"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- ldo2 { +- regulator-name = "vdd_ldo2,vdd_rtc"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo3 { +- regulator-name = "vdd_ldo3,avdd_usb*"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo4 { +- regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo5 { +- regulator-name = "vdd_ldo5,vcore_mmc"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- }; +- +- ldo6 { +- regulator-name = "vdd_ldo6,avdd_vdac"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- hdmi_vdd_reg: ldo7 { +- regulator-name = "vdd_ldo7,avdd_hdmi"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- hdmi_pll_reg: ldo8 { +- regulator-name = "vdd_ldo8,avdd_hdmi_pll"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo9 { +- regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- }; +- +- ldo_rtc { +- regulator-name = "vdd_rtc_out,vdd_cell"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +- +- temperature-sensor@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- }; +- +- kbc@7000e200 { +- status = "okay"; +- nvidia,debounce-delay-ms = <2>; +- nvidia,repeat-delay-ms = <160>; +- nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; +- nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; +- linux,keymap = ; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <5000>; +- nvidia,cpu-pwr-off-time = <5000>; +- nvidia,core-pwr-good-time = <3845 3845>; +- nvidia,core-pwr-off-time = <3875>; +- nvidia,sys-clock-req-active-high; +- }; +- +- pcie@80003000 { +- status = "okay"; +- +- avdd-pex-supply = <&pci_vdd_reg>; +- vdd-pex-supply = <&pci_vdd_reg>; +- avdd-pex-pll-supply = <&pci_vdd_reg>; +- avdd-plle-supply = <&pci_vdd_reg>; +- vddio-pex-clk-supply = <&pci_clk_reg>; +- +- pci@1,0 { +- status = "okay"; +- }; +- +- pci@2,0 { +- status = "okay"; +- }; +- }; +- +- usb@c5000000 { +- status = "okay"; +- }; +- +- usb-phy@c5000000 { +- status = "okay"; +- }; +- +- usb@c5004000 { +- status = "okay"; +- nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) +- GPIO_ACTIVE_LOW>; +- }; +- +- usb-phy@c5004000 { +- status = "okay"; +- nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) +- GPIO_ACTIVE_LOW>; +- }; +- +- usb@c5008000 { +- status = "okay"; +- }; +- +- usb-phy@c5008000 { +- status = "okay"; +- }; +- +- mmc@c8000200 { +- status = "okay"; +- cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; +- power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; +- bus-width = <4>; +- }; +- +- mmc@c8000600 { +- status = "okay"; +- cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; +- power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; +- bus-width = <8>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- +- enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>; +- power-supply = <&vdd_bl_reg>; +- pwms = <&pwm 0 5000000>; +- +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "Power"; +- gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- panel: panel { +- compatible = "auo,b101aw03"; +- +- power-supply = <&vdd_pnl_reg>; +- enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; +- +- backlight = <&backlight>; +- }; +- +- vdd_5v0_reg: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_1v5"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; +- }; +- +- regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_1v2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- pci_vdd_reg: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_1v05"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vdd_pnl_reg: regulator@4 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_pnl"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vdd_bl_reg: regulator@5 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_bl"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vdd_5v0_hdmi: regulator@6 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_HDMI"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_5v0_reg>; +- }; +- +- sound { +- compatible = "nvidia,tegra-audio-wm8903-harmony", +- "nvidia,tegra-audio-wm8903"; +- nvidia,model = "NVIDIA Tegra Harmony"; +- +- nvidia,audio-routing = +- "Headphone Jack", "HPOUTR", +- "Headphone Jack", "HPOUTL", +- "Int Spk", "ROP", +- "Int Spk", "RON", +- "Int Spk", "LOP", +- "Int Spk", "LON", +- "Mic Jack", "MICBIAS", +- "IN1L", "Mic Jack"; +- +- nvidia,i2s-controller = <&tegra_i2s1>; +- nvidia,audio-codec = <&wm8903>; +- +- nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; +- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) +- GPIO_ACTIVE_LOW>; +- nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) +- GPIO_ACTIVE_HIGH>; +- nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) +- GPIO_ACTIVE_HIGH>; +- +- clocks = <&tegra_car TEGRA20_CLK_PLL_A>, +- <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA20_CLK_CDEV1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra20-medcom-wide.dts b/scripts/dtc/include-prefixes/arm/tegra20-medcom-wide.dts +deleted file mode 100644 +index b31c9bca16e6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra20-medcom-wide.dts ++++ /dev/null +@@ -1,129 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "tegra20-tamonten.dtsi" +- +-/ { +- model = "Avionic Design Medcom-Wide board"; +- compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; +- +- aliases { +- serial0 = &uartd; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- pwm@7000a000 { +- status = "okay"; +- }; +- +- host1x@50000000 { +- dc@54200000 { +- rgb { +- status = "okay"; +- nvidia,panel = <&panel>; +- }; +- }; +- }; +- +- i2c@7000c000 { +- wm8903: wm8903@1a { +- compatible = "wlf,wm8903"; +- reg = <0x1a>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- micdet-cfg = <0>; +- micdet-delay = <100>; +- gpio-cfg = <0xffffffff +- 0xffffffff +- 0 +- 0xffffffff +- 0xffffffff>; +- }; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 5000000>; +- +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +- +- panel: panel { +- compatible = "innolux,n156bge-l21"; +- +- power-supply = <&vdd_1v8_reg>; // <&vdd_3v3_reg>; +- enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; +- +- backlight = <&backlight>; +- }; +- +- sound { +- compatible = "ad,tegra-audio-wm8903-medcom-wide", +- "nvidia,tegra-audio-wm8903"; +- nvidia,model = "Avionic Design Medcom-Wide"; +- +- nvidia,audio-routing = +- "Headphone Jack", "HPOUTR", +- "Headphone Jack", "HPOUTL", +- "Int Spk", "ROP", +- "Int Spk", "RON", +- "Int Spk", "LOP", +- "Int Spk", "LON", +- "Mic Jack", "MICBIAS", +- "IN1L", "Mic Jack"; +- +- nvidia,i2s-controller = <&tegra_i2s1>; +- nvidia,audio-codec = <&wm8903>; +- +- nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; +- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; +- +- clocks = <&tegra_car TEGRA20_CLK_PLL_A>, +- <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA20_CLK_CDEV1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- }; +- +- vcc_24v_reg: regulator@100 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_24v"; +- regulator-min-microvolt = <24000000>; +- regulator-max-microvolt = <24000000>; +- regulator-always-on; +- }; +- +- vdd_5v0_reg: regulator@101 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_5v0"; +- vin-supply = <&vcc_24v_reg>; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- vdd_3v3_reg: regulator@102 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_3v3"; +- vin-supply = <&vcc_24v_reg>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_1v8_reg: regulator@103 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_1v8"; +- vin-supply = <&vdd_3v3_reg>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra20-paz00.dts b/scripts/dtc/include-prefixes/arm/tegra20-paz00.dts +deleted file mode 100644 +index acc816bfd233..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra20-paz00.dts ++++ /dev/null +@@ -1,711 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +- +-#include "tegra20.dtsi" +-#include "tegra20-cpu-opp.dtsi" +-#include "tegra20-cpu-opp-microvolt.dtsi" +- +-/ { +- model = "Toshiba AC100 / Dynabook AZ"; +- compatible = "compal,paz00", "nvidia,tegra20"; +- +- aliases { +- rtc0 = "/i2c@7000d000/tps6586x@34"; +- rtc1 = "/rtc@7000e000"; +- serial0 = &uarta; +- serial1 = &uartc; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- reg = <0x00000000 0x20000000>; +- }; +- +- host1x@50000000 { +- dc@54200000 { +- rgb { +- status = "okay"; +- +- nvidia,panel = <&panel>; +- }; +- }; +- +- hdmi@54280000 { +- status = "okay"; +- +- vdd-supply = <&hdmi_vdd_reg>; +- pll-supply = <&hdmi_pll_reg>; +- +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) +- GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- pinmux@70000014 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- ata { +- nvidia,pins = "ata", "atc", "atd", "ate", +- "dap2", "gmb", "gmc", "gmd", "spia", +- "spib", "spic", "spid", "spie"; +- nvidia,function = "gmi"; +- }; +- atb { +- nvidia,pins = "atb", "gma", "gme"; +- nvidia,function = "sdio4"; +- }; +- cdev1 { +- nvidia,pins = "cdev1"; +- nvidia,function = "plla_out"; +- }; +- cdev2 { +- nvidia,pins = "cdev2"; +- nvidia,function = "pllp_out4"; +- }; +- crtp { +- nvidia,pins = "crtp"; +- nvidia,function = "crt"; +- }; +- csus { +- nvidia,pins = "csus"; +- nvidia,function = "pllc_out1"; +- }; +- dap1 { +- nvidia,pins = "dap1"; +- nvidia,function = "dap1"; +- }; +- dap3 { +- nvidia,pins = "dap3"; +- nvidia,function = "dap3"; +- }; +- dap4 { +- nvidia,pins = "dap4"; +- nvidia,function = "dap4"; +- }; +- ddc { +- nvidia,pins = "ddc"; +- nvidia,function = "i2c2"; +- }; +- dta { +- nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; +- nvidia,function = "rsvd1"; +- }; +- dtf { +- nvidia,pins = "dtf"; +- nvidia,function = "i2c3"; +- }; +- gpu { +- nvidia,pins = "gpu", "sdb", "sdd"; +- nvidia,function = "pwm"; +- }; +- gpu7 { +- nvidia,pins = "gpu7"; +- nvidia,function = "rtck"; +- }; +- gpv { +- nvidia,pins = "gpv", "slxa", "slxk"; +- nvidia,function = "pcie"; +- }; +- hdint { +- nvidia,pins = "hdint", "pta"; +- nvidia,function = "hdmi"; +- }; +- i2cp { +- nvidia,pins = "i2cp"; +- nvidia,function = "i2cp"; +- }; +- irrx { +- nvidia,pins = "irrx", "irtx"; +- nvidia,function = "uarta"; +- }; +- kbca { +- nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; +- nvidia,function = "kbc"; +- }; +- kbcb { +- nvidia,pins = "kbcb", "kbcd"; +- nvidia,function = "sdio2"; +- }; +- lcsn { +- nvidia,pins = "lcsn", "ld0", "ld1", "ld2", +- "ld3", "ld4", "ld5", "ld6", "ld7", +- "ld8", "ld9", "ld10", "ld11", "ld12", +- "ld13", "ld14", "ld15", "ld16", "ld17", +- "ldc", "ldi", "lhp0", "lhp1", "lhp2", +- "lhs", "lm0", "lm1", "lpp", "lpw0", +- "lpw1", "lpw2", "lsc0", "lsc1", "lsck", +- "lsda", "lsdi", "lspi", "lvp0", "lvp1", +- "lvs"; +- nvidia,function = "displaya"; +- }; +- owc { +- nvidia,pins = "owc"; +- nvidia,function = "owr"; +- }; +- pmc { +- nvidia,pins = "pmc"; +- nvidia,function = "pwr_on"; +- }; +- rm { +- nvidia,pins = "rm"; +- nvidia,function = "i2c1"; +- }; +- sdc { +- nvidia,pins = "sdc"; +- nvidia,function = "twc"; +- }; +- sdio1 { +- nvidia,pins = "sdio1"; +- nvidia,function = "sdio1"; +- }; +- slxc { +- nvidia,pins = "slxc", "slxd"; +- nvidia,function = "spi4"; +- }; +- spdi { +- nvidia,pins = "spdi", "spdo"; +- nvidia,function = "rsvd2"; +- }; +- spif { +- nvidia,pins = "spif", "uac"; +- nvidia,function = "rsvd4"; +- }; +- spig { +- nvidia,pins = "spig", "spih"; +- nvidia,function = "spi2_alt"; +- }; +- uaa { +- nvidia,pins = "uaa", "uab", "uda"; +- nvidia,function = "ulpi"; +- }; +- uad { +- nvidia,pins = "uad"; +- nvidia,function = "spdif"; +- }; +- uca { +- nvidia,pins = "uca", "ucb"; +- nvidia,function = "uartc"; +- }; +- conf_ata { +- nvidia,pins = "ata", "atb", "atc", "atd", "ate", +- "cdev1", "cdev2", "dap1", "dap2", "dtf", +- "gma", "gmb", "gmc", "gmd", "gme", +- "gpu", "gpu7", "gpv", "i2cp", "pta", +- "rm", "sdio1", "slxk", "spdo", "uac", +- "uda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_ck32 { +- nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", +- "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; +- nvidia,pull = ; +- }; +- conf_crtp { +- nvidia,pins = "crtp", "dap3", "dap4", "dtb", +- "dtc", "dte", "slxa", "slxc", "slxd", +- "spdi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_csus { +- nvidia,pins = "csus", "spia", "spib", "spid", +- "spif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_ddc { +- nvidia,pins = "ddc", "irrx", "irtx", "kbca", +- "kbcb", "kbcc", "kbcd", "kbce", "kbcf", +- "spic", "spig", "uaa", "uab"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_dta { +- nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd", +- "spie", "spih", "uad", "uca", "ucb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_hdint { +- nvidia,pins = "hdint", "ld0", "ld1", "ld2", +- "ld3", "ld4", "ld5", "ld6", "ld7", +- "ld8", "ld9", "ld10", "ld11", "ld12", +- "ld13", "ld14", "ld15", "ld16", "ld17", +- "ldc", "ldi", "lhs", "lsc0", "lspi", +- "lvs", "pmc"; +- nvidia,tristate = ; +- }; +- conf_lc { +- nvidia,pins = "lc", "ls"; +- nvidia,pull = ; +- }; +- conf_lcsn { +- nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2", +- "lm0", "lm1", "lpp", "lpw0", "lpw1", +- "lpw2", "lsc1", "lsck", "lsda", "lsdi", +- "lvp0", "lvp1", "sdb"; +- nvidia,tristate = ; +- }; +- conf_ld17_0 { +- nvidia,pins = "ld17_0", "ld19_18", "ld21_20", +- "ld23_22"; +- nvidia,pull = ; +- }; +- }; +- }; +- +- i2s@70002800 { +- status = "okay"; +- }; +- +- serial@70006000 { +- status = "okay"; +- }; +- +- serial@70006200 { +- status = "okay"; +- }; +- +- pwm: pwm@7000a000 { +- status = "okay"; +- }; +- +- lvds_ddc: i2c@7000c000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- alc5632: alc5632@1e { +- compatible = "realtek,alc5632"; +- reg = <0x1e>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +- +- hdmi_ddc: i2c@7000c400 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- nvec@7000c500 { +- compatible = "nvidia,nvec"; +- reg = <0x7000c500 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <80000>; +- request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; +- slave-addr = <138>; +- clocks = <&tegra_car TEGRA20_CLK_I2C3>, +- <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; +- clock-names = "div-clk", "fast-clk"; +- resets = <&tegra_car 67>; +- reset-names = "i2c"; +- }; +- +- memory-controller@7000f400 { +- nvidia,use-ram-code; +- +- emc-tables@0 { +- nvidia,ram-code = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- emc-table@166500 { +- reg = <166500>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <166500>; +- nvidia,emc-registers = <0x0000000a 0x00000016 +- 0x00000008 0x00000003 0x00000004 0x00000004 +- 0x00000002 0x0000000c 0x00000003 0x00000003 +- 0x00000002 0x00000001 0x00000004 0x00000005 +- 0x00000004 0x00000009 0x0000000d 0x000004df +- 0x00000000 0x00000003 0x00000003 0x00000003 +- 0x00000003 0x00000001 0x0000000a 0x000000c8 +- 0x00000003 0x00000006 0x00000004 0x00000008 +- 0x00000002 0x00000000 0x00000000 0x00000002 +- 0x00000000 0x00000000 0x00000083 0xe03b0323 +- 0x007fe010 0x00001414 0x00000000 0x00000000 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- +- emc-table@333000 { +- reg = <333000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <333000>; +- nvidia,emc-registers = <0x00000018 0x00000033 +- 0x00000012 0x00000004 0x00000004 0x00000005 +- 0x00000003 0x0000000c 0x00000006 0x00000006 +- 0x00000003 0x00000001 0x00000004 0x00000005 +- 0x00000004 0x00000009 0x0000000d 0x00000bff +- 0x00000000 0x00000003 0x00000003 0x00000006 +- 0x00000006 0x00000001 0x00000011 0x000000c8 +- 0x00000003 0x0000000e 0x00000007 0x00000008 +- 0x00000002 0x00000000 0x00000000 0x00000002 +- 0x00000000 0x00000000 0x00000083 0xf0440303 +- 0x007fe010 0x00001414 0x00000000 0x00000000 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- }; +- }; +- +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- pmic: tps6586x@34 { +- compatible = "ti,tps6586x"; +- reg = <0x34>; +- interrupts = ; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- sys-supply = <&p5valw_reg>; +- vin-sm0-supply = <&sys_reg>; +- vin-sm1-supply = <&sys_reg>; +- vin-sm2-supply = <&sys_reg>; +- vinldo01-supply = <&sm2_reg>; +- vinldo23-supply = <&sm2_reg>; +- vinldo4-supply = <&sm2_reg>; +- vinldo678-supply = <&sm2_reg>; +- vinldo9-supply = <&sm2_reg>; +- +- regulators { +- sys_reg: sys { +- regulator-name = "vdd_sys"; +- regulator-always-on; +- }; +- +- core_vdd_reg: sm0 { +- regulator-name = "+1.2vs_sm0,vdd_core"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1300000>; +- regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>; +- regulator-coupled-max-spread = <170000 550000>; +- regulator-always-on; +- +- nvidia,tegra-core-regulator; +- }; +- +- cpu_vdd_reg: sm1 { +- regulator-name = "+1.0vs_sm1,vdd_cpu"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1100000>; +- regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>; +- regulator-coupled-max-spread = <550000 550000>; +- regulator-always-on; +- +- nvidia,tegra-cpu-regulator; +- }; +- +- sm2_reg: sm2 { +- regulator-name = "+3.7vs_sm2,vin_ldo*"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- regulator-always-on; +- }; +- +- /* LDO0 is not connected to anything */ +- +- ldo1 { +- regulator-name = "+1.1vs_ldo1,avdd_pll*"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- rtc_vdd_reg: ldo2 { +- regulator-name = "+1.2vs_ldo2,vdd_rtc"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1300000>; +- regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>; +- regulator-coupled-max-spread = <170000 550000>; +- regulator-always-on; +- +- nvidia,tegra-rtc-regulator; +- }; +- +- ldo3 { +- regulator-name = "+3.3vs_ldo3,avdd_usb*"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo4 { +- regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo5 { +- regulator-name = "+2.85vs_ldo5,vcore_mmc"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- }; +- +- ldo6 { +- /* +- * Research indicates this should be +- * 1.8v; other boards that use this +- * rail for the same purpose need it +- * set to 1.8v. The schematic signal +- * name is incorrect; perhaps copied +- * from an incorrect NVIDIA reference. +- */ +- regulator-name = "+2.85vs_ldo6,avdd_vdac"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- hdmi_vdd_reg: ldo7 { +- regulator-name = "+3.3vs_ldo7,avdd_hdmi"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- hdmi_pll_reg: ldo8 { +- regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo9 { +- regulator-name = "+2.85vs_ldo9,vdd_ddr_rx"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- }; +- +- ldo_rtc { +- regulator-name = "+3.3vs_rtc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +- +- adt7461: temperature-sensor@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- #thermal-sensor-cells = <1>; +- }; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <2000>; +- nvidia,cpu-pwr-off-time = <0>; +- nvidia,core-pwr-good-time = <3845 3845>; +- nvidia,core-pwr-off-time = <0>; +- nvidia,sys-clock-req-active-high; +- }; +- +- usb@c5000000 { +- compatible = "nvidia,tegra20-udc"; +- status = "okay"; +- dr_mode = "peripheral"; +- }; +- +- usb-phy@c5000000 { +- status = "okay"; +- }; +- +- usb@c5004000 { +- status = "okay"; +- nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) +- GPIO_ACTIVE_LOW>; +- }; +- +- usb-phy@c5004000 { +- status = "okay"; +- nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) +- GPIO_ACTIVE_LOW>; +- }; +- +- usb@c5008000 { +- status = "okay"; +- }; +- +- usb-phy@c5008000 { +- status = "okay"; +- }; +- +- mmc@c8000000 { +- status = "okay"; +- cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; +- power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; +- bus-width = <4>; +- }; +- +- mmc@c8000600 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- +- enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; +- pwms = <&pwm 0 5000000>; +- +- brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>; +- default-brightness-level = <10>; +- +- backlight-boot-off; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- wakeup { +- label = "Wakeup"; +- gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "wifi-led"; +- gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "rfkill0"; +- }; +- }; +- +- panel: panel { +- compatible = "samsung,ltn101nt05"; +- +- ddc-i2c-bus = <&lvds_ddc>; +- power-supply = <&vdd_pnl_reg>; +- enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>; +- +- backlight = <&backlight>; +- }; +- +- p5valw_reg: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "+5valw"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- vdd_pnl_reg: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "+3VS,vdd_pnl"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sound { +- compatible = "nvidia,tegra-audio-alc5632-paz00", +- "nvidia,tegra-audio-alc5632"; +- +- nvidia,model = "Compal PAZ00"; +- +- nvidia,audio-routing = +- "Int Spk", "SPKOUT", +- "Int Spk", "SPKOUTN", +- "Headset Mic", "MICBIAS1", +- "MIC1", "Headset Mic", +- "Headset Stereophone", "HPR", +- "Headset Stereophone", "HPL", +- "DMICDAT", "Digital Mic"; +- +- nvidia,audio-codec = <&alc5632>; +- nvidia,i2s-controller = <&tegra_i2s1>; +- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) +- GPIO_ACTIVE_HIGH>; +- +- clocks = <&tegra_car TEGRA20_CLK_PLL_A>, +- <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA20_CLK_CDEV1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- }; +- +- cpus { +- cpu0: cpu@0 { +- cpu-supply = <&cpu_vdd_reg>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- cpu-supply = <&cpu_vdd_reg>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- }; +- +- thermal-zones { +- cpu-thermal { +- polling-delay-passive = <500>; /* milliseconds */ +- polling-delay = <1500>; /* milliseconds */ +- +- thermal-sensors = <&adt7461 1>; +- +- trips { +- trip0: cpu-alert0 { +- /* start throttling at 80C */ +- temperature = <80000>; +- hysteresis = <200>; +- type = "passive"; +- }; +- +- trip1: cpu-crit { +- /* shut down at 85C */ +- temperature = <85000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&trip0>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +-}; +- +-&emc_icc_dvfs_opp_table { +- /delete-node/ opp@760000000; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra20-peripherals-opp.dtsi b/scripts/dtc/include-prefixes/arm/tegra20-peripherals-opp.dtsi +deleted file mode 100644 +index ef3ad2e5f270..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra20-peripherals-opp.dtsi ++++ /dev/null +@@ -1,110 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/ { +- emc_icc_dvfs_opp_table: emc-dvfs-opp-table { +- compatible = "operating-points-v2"; +- +- opp@36000000 { +- opp-microvolt = <950000 950000 1300000>; +- opp-hz = /bits/ 64 <36000000>; +- opp-supported-hw = <0x000F>; +- }; +- +- opp@47500000 { +- opp-microvolt = <950000 950000 1300000>; +- opp-hz = /bits/ 64 <47500000>; +- opp-supported-hw = <0x000F>; +- }; +- +- opp@50000000 { +- opp-microvolt = <950000 950000 1300000>; +- opp-hz = /bits/ 64 <50000000>; +- opp-supported-hw = <0x000F>; +- }; +- +- opp@54000000 { +- opp-microvolt = <950000 950000 1300000>; +- opp-hz = /bits/ 64 <54000000>; +- opp-supported-hw = <0x000F>; +- }; +- +- opp@57000000 { +- opp-microvolt = <950000 950000 1300000>; +- opp-hz = /bits/ 64 <57000000>; +- opp-supported-hw = <0x000F>; +- }; +- +- opp@100000000 { +- opp-microvolt = <1000000 1000000 1300000>; +- opp-hz = /bits/ 64 <100000000>; +- opp-supported-hw = <0x000F>; +- }; +- +- opp@108000000 { +- opp-microvolt = <1000000 1000000 1300000>; +- opp-hz = /bits/ 64 <108000000>; +- opp-supported-hw = <0x000F>; +- }; +- +- opp@126666000 { +- opp-microvolt = <1000000 1000000 1300000>; +- opp-hz = /bits/ 64 <126666000>; +- opp-supported-hw = <0x000F>; +- }; +- +- opp@150000000 { +- opp-microvolt = <1000000 1000000 1300000>; +- opp-hz = /bits/ 64 <150000000>; +- opp-supported-hw = <0x000F>; +- }; +- +- opp@190000000 { +- opp-microvolt = <1000000 1000000 1300000>; +- opp-hz = /bits/ 64 <190000000>; +- opp-supported-hw = <0x000F>; +- }; +- +- opp@216000000 { +- opp-microvolt = <1000000 1000000 1300000>; +- opp-hz = /bits/ 64 <216000000>; +- opp-supported-hw = <0x000F>; +- opp-suspend; +- }; +- +- opp@300000000 { +- opp-microvolt = <1000000 1000000 1300000>; +- opp-hz = /bits/ 64 <300000000>; +- opp-supported-hw = <0x000F>; +- }; +- +- opp@333000000 { +- opp-microvolt = <1000000 1000000 1300000>; +- opp-hz = /bits/ 64 <333000000>; +- opp-supported-hw = <0x000F>; +- }; +- +- opp@380000000 { +- opp-microvolt = <1100000 1100000 1300000>; +- opp-hz = /bits/ 64 <380000000>; +- opp-supported-hw = <0x000F>; +- }; +- +- opp@600000000 { +- opp-microvolt = <1200000 1200000 1300000>; +- opp-hz = /bits/ 64 <600000000>; +- opp-supported-hw = <0x000F>; +- }; +- +- opp@666000000 { +- opp-microvolt = <1200000 1200000 1300000>; +- opp-hz = /bits/ 64 <666000000>; +- opp-supported-hw = <0x000F>; +- }; +- +- opp@760000000 { +- opp-microvolt = <1300000 1300000 1300000>; +- opp-hz = /bits/ 64 <760000000>; +- opp-supported-hw = <0x000F>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra20-plutux.dts b/scripts/dtc/include-prefixes/arm/tegra20-plutux.dts +deleted file mode 100644 +index 5811b7006a9b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra20-plutux.dts ++++ /dev/null +@@ -1,97 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "tegra20-tamonten.dtsi" +- +-/ { +- model = "Avionic Design Plutux board"; +- compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; +- +- host1x@50000000 { +- hdmi@54280000 { +- status = "okay"; +- }; +- }; +- +- i2c@7000c000 { +- wm8903: wm8903@1a { +- compatible = "wlf,wm8903"; +- reg = <0x1a>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- micdet-cfg = <0>; +- micdet-delay = <100>; +- gpio-cfg = <0xffffffff +- 0xffffffff +- 0 +- 0xffffffff +- 0xffffffff>; +- }; +- }; +- +- sound { +- compatible = "ad,tegra-audio-plutux", +- "nvidia,tegra-audio-wm8903"; +- nvidia,model = "Avionic Design Plutux"; +- +- nvidia,audio-routing = +- "Headphone Jack", "HPOUTR", +- "Headphone Jack", "HPOUTL", +- "Int Spk", "ROP", +- "Int Spk", "RON", +- "Int Spk", "LOP", +- "Int Spk", "LON", +- "Mic Jack", "MICBIAS", +- "IN1L", "Mic Jack"; +- +- nvidia,i2s-controller = <&tegra_i2s1>; +- nvidia,audio-codec = <&wm8903>; +- +- nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; +- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; +- +- clocks = <&tegra_car TEGRA20_CLK_PLL_A>, +- <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA20_CLK_CDEV1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- }; +- +- vcc_24v_reg: regulator@100 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_24v"; +- regulator-min-microvolt = <24000000>; +- regulator-max-microvolt = <24000000>; +- regulator-always-on; +- }; +- +- vdd_5v0_reg: regulator@101 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_5v0"; +- vin-supply = <&vcc_24v_reg>; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- vdd_3v3_reg: regulator@102 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_3v3"; +- vin-supply = <&vcc_24v_reg>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_1v8_reg: regulator@103 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_1v8"; +- vin-supply = <&vdd_3v3_reg>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra20-seaboard.dts b/scripts/dtc/include-prefixes/arm/tegra20-seaboard.dts +deleted file mode 100644 +index 92d494b8c3d2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra20-seaboard.dts ++++ /dev/null +@@ -1,921 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include "tegra20.dtsi" +- +-/ { +- model = "NVIDIA Seaboard"; +- compatible = "nvidia,seaboard", "nvidia,tegra20"; +- +- aliases { +- rtc0 = "/i2c@7000d000/tps6586x@34"; +- rtc1 = "/rtc@7000e000"; +- serial0 = &uartd; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- reg = <0x00000000 0x40000000>; +- }; +- +- host1x@50000000 { +- dc@54200000 { +- rgb { +- status = "okay"; +- +- nvidia,panel = <&panel>; +- }; +- }; +- +- hdmi@54280000 { +- status = "okay"; +- +- vdd-supply = <&hdmi_vdd_reg>; +- pll-supply = <&hdmi_pll_reg>; +- hdmi-supply = <&vdd_hdmi>; +- +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) +- GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- pinmux@70000014 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- ata { +- nvidia,pins = "ata"; +- nvidia,function = "ide"; +- }; +- atb { +- nvidia,pins = "atb", "gma", "gme"; +- nvidia,function = "sdio4"; +- }; +- atc { +- nvidia,pins = "atc"; +- nvidia,function = "nand"; +- }; +- atd { +- nvidia,pins = "atd", "ate", "gmb", "spia", +- "spib", "spic"; +- nvidia,function = "gmi"; +- }; +- cdev1 { +- nvidia,pins = "cdev1"; +- nvidia,function = "plla_out"; +- }; +- cdev2 { +- nvidia,pins = "cdev2"; +- nvidia,function = "pllp_out4"; +- }; +- crtp { +- nvidia,pins = "crtp", "lm1"; +- nvidia,function = "crt"; +- }; +- csus { +- nvidia,pins = "csus"; +- nvidia,function = "vi_sensor_clk"; +- }; +- dap1 { +- nvidia,pins = "dap1"; +- nvidia,function = "dap1"; +- }; +- dap2 { +- nvidia,pins = "dap2"; +- nvidia,function = "dap2"; +- }; +- dap3 { +- nvidia,pins = "dap3"; +- nvidia,function = "dap3"; +- }; +- dap4 { +- nvidia,pins = "dap4"; +- nvidia,function = "dap4"; +- }; +- dta { +- nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; +- nvidia,function = "vi"; +- }; +- dtf { +- nvidia,pins = "dtf"; +- nvidia,function = "i2c3"; +- }; +- gmc { +- nvidia,pins = "gmc"; +- nvidia,function = "uartd"; +- }; +- gmd { +- nvidia,pins = "gmd"; +- nvidia,function = "sflash"; +- }; +- gpu { +- nvidia,pins = "gpu"; +- nvidia,function = "pwm"; +- }; +- gpu7 { +- nvidia,pins = "gpu7"; +- nvidia,function = "rtck"; +- }; +- gpv { +- nvidia,pins = "gpv", "slxa", "slxk"; +- nvidia,function = "pcie"; +- }; +- hdint { +- nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1", +- "lsck", "lsda"; +- nvidia,function = "hdmi"; +- }; +- i2cp { +- nvidia,pins = "i2cp"; +- nvidia,function = "i2cp"; +- }; +- irrx { +- nvidia,pins = "irrx", "irtx"; +- nvidia,function = "uartb"; +- }; +- kbca { +- nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", +- "kbce", "kbcf"; +- nvidia,function = "kbc"; +- }; +- lcsn { +- nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", +- "lsdi", "lvp0"; +- nvidia,function = "rsvd4"; +- }; +- ld0 { +- nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", +- "ld5", "ld6", "ld7", "ld8", "ld9", +- "ld10", "ld11", "ld12", "ld13", "ld14", +- "ld15", "ld16", "ld17", "ldi", "lhp0", +- "lhp1", "lhp2", "lhs", "lpp", "lsc0", +- "lspi", "lvp1", "lvs"; +- nvidia,function = "displaya"; +- }; +- owc { +- nvidia,pins = "owc", "spdi", "spdo", "uac"; +- nvidia,function = "rsvd2"; +- }; +- pmc { +- nvidia,pins = "pmc"; +- nvidia,function = "pwr_on"; +- }; +- rm { +- nvidia,pins = "rm"; +- nvidia,function = "i2c1"; +- }; +- sdb { +- nvidia,pins = "sdb", "sdc", "sdd"; +- nvidia,function = "sdio3"; +- }; +- sdio1 { +- nvidia,pins = "sdio1"; +- nvidia,function = "sdio1"; +- }; +- slxc { +- nvidia,pins = "slxc", "slxd"; +- nvidia,function = "spdif"; +- }; +- spid { +- nvidia,pins = "spid", "spie", "spif"; +- nvidia,function = "spi1"; +- }; +- spig { +- nvidia,pins = "spig", "spih"; +- nvidia,function = "spi2_alt"; +- }; +- uaa { +- nvidia,pins = "uaa", "uab", "uda"; +- nvidia,function = "ulpi"; +- }; +- uad { +- nvidia,pins = "uad"; +- nvidia,function = "irda"; +- }; +- uca { +- nvidia,pins = "uca", "ucb"; +- nvidia,function = "uartc"; +- }; +- conf_ata { +- nvidia,pins = "ata", "atb", "atc", "atd", +- "cdev1", "cdev2", "dap1", "dap2", +- "dap4", "ddc", "dtf", "gma", "gmc", "gmd", +- "gme", "gpu", "gpu7", "i2cp", "irrx", +- "irtx", "pta", "rm", "sdc", "sdd", +- "slxd", "slxk", "spdi", "spdo", "uac", +- "uad", "uca", "ucb", "uda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_ate { +- nvidia,pins = "ate", "csus", "dap3", +- "gpv", "owc", "slxc", "spib", "spid", +- "spie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_ck32 { +- nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", +- "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; +- nvidia,pull = ; +- }; +- conf_crtp { +- nvidia,pins = "crtp", "gmb", "slxa", "spia", +- "spig", "spih"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_dta { +- nvidia,pins = "dta", "dtb", "dtc", "dtd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_dte { +- nvidia,pins = "dte", "spif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_hdint { +- nvidia,pins = "hdint", "lcsn", "ldc", "lm1", +- "lpw1", "lsc1", "lsck", "lsda", "lsdi", +- "lvp0"; +- nvidia,tristate = ; +- }; +- conf_kbca { +- nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", +- "kbce", "kbcf", "sdio1", "spic", "uaa", +- "uab"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_lc { +- nvidia,pins = "lc", "ls"; +- nvidia,pull = ; +- }; +- conf_ld0 { +- nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", +- "ld5", "ld6", "ld7", "ld8", "ld9", +- "ld10", "ld11", "ld12", "ld13", "ld14", +- "ld15", "ld16", "ld17", "ldi", "lhp0", +- "lhp1", "lhp2", "lhs", "lm0", "lpp", +- "lpw0", "lpw2", "lsc0", "lspi", "lvp1", +- "lvs", "pmc", "sdb"; +- nvidia,tristate = ; +- }; +- conf_ld17_0 { +- nvidia,pins = "ld17_0", "ld19_18", "ld21_20", +- "ld23_22"; +- nvidia,pull = ; +- }; +- drive_sdio1 { +- nvidia,pins = "drive_sdio1"; +- nvidia,high-speed-mode = ; +- nvidia,schmitt = ; +- nvidia,low-power-mode = ; +- nvidia,pull-down-strength = <31>; +- nvidia,pull-up-strength = <31>; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- }; +- }; +- +- state_i2cmux_ddc: pinmux_i2cmux_ddc { +- ddc { +- nvidia,pins = "ddc"; +- nvidia,function = "i2c2"; +- }; +- pta { +- nvidia,pins = "pta"; +- nvidia,function = "rsvd4"; +- }; +- }; +- +- state_i2cmux_pta: pinmux_i2cmux_pta { +- ddc { +- nvidia,pins = "ddc"; +- nvidia,function = "rsvd4"; +- }; +- pta { +- nvidia,pins = "pta"; +- nvidia,function = "i2c2"; +- }; +- }; +- +- state_i2cmux_idle: pinmux_i2cmux_idle { +- ddc { +- nvidia,pins = "ddc"; +- nvidia,function = "rsvd4"; +- }; +- pta { +- nvidia,pins = "pta"; +- nvidia,function = "rsvd4"; +- }; +- }; +- }; +- +- i2s@70002800 { +- status = "okay"; +- }; +- +- serial@70006300 { +- status = "okay"; +- }; +- +- pwm: pwm@7000a000 { +- status = "okay"; +- }; +- +- i2c@7000c000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- wm8903: wm8903@1a { +- compatible = "wlf,wm8903"; +- reg = <0x1a>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- micdet-cfg = <0>; +- micdet-delay = <100>; +- gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; +- }; +- +- /* ALS and proximity sensor */ +- isl29018@44 { +- compatible = "isil,isl29018"; +- reg = <0x44>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- }; +- +- gyrometer@68 { +- compatible = "invn,mpu3050"; +- reg = <0x68>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- }; +- }; +- +- i2c@7000c400 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- i2cmux { +- compatible = "i2c-mux-pinctrl"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c-parent = <&{/i2c@7000c400}>; +- +- pinctrl-names = "ddc", "pta", "idle"; +- pinctrl-0 = <&state_i2cmux_ddc>; +- pinctrl-1 = <&state_i2cmux_pta>; +- pinctrl-2 = <&state_i2cmux_idle>; +- +- hdmi_ddc: i2c@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- lvds_ddc: i2c@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- smart-battery@b { +- compatible = "ti,bq20z75", "sbs,sbs-battery"; +- reg = <0xb>; +- sbs,i2c-retry-count = <2>; +- sbs,poll-retry-count = <10>; +- }; +- }; +- }; +- +- i2c@7000c500 { +- status = "okay"; +- clock-frequency = <400000>; +- }; +- +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- magnetometer@c { +- compatible = "asahi-kasei,ak8975"; +- reg = <0xc>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- }; +- +- pmic: tps6586x@34 { +- compatible = "ti,tps6586x"; +- reg = <0x34>; +- interrupts = ; +- +- ti,system-power-controller; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- sys-supply = <&vdd_5v0_reg>; +- vin-sm0-supply = <&sys_reg>; +- vin-sm1-supply = <&sys_reg>; +- vin-sm2-supply = <&sys_reg>; +- vinldo01-supply = <&sm2_reg>; +- vinldo23-supply = <&sm2_reg>; +- vinldo4-supply = <&sm2_reg>; +- vinldo678-supply = <&sm2_reg>; +- vinldo9-supply = <&sm2_reg>; +- +- regulators { +- sys_reg: sys { +- regulator-name = "vdd_sys"; +- regulator-always-on; +- }; +- +- sm0 { +- regulator-name = "vdd_sm0,vdd_core"; +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- }; +- +- sm1 { +- regulator-name = "vdd_sm1,vdd_cpu"; +- regulator-min-microvolt = <1125000>; +- regulator-max-microvolt = <1125000>; +- regulator-always-on; +- }; +- +- sm2_reg: sm2 { +- regulator-name = "vdd_sm2,vin_ldo*"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- regulator-always-on; +- }; +- +- /* LDO0 is not connected to anything */ +- +- ldo1 { +- regulator-name = "vdd_ldo1,avdd_pll*"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- ldo2 { +- regulator-name = "vdd_ldo2,vdd_rtc"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo3 { +- regulator-name = "vdd_ldo3,avdd_usb*"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo4 { +- regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo5 { +- regulator-name = "vdd_ldo5,vcore_mmc"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- }; +- +- ldo6 { +- regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- hdmi_vdd_reg: ldo7 { +- regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- hdmi_pll_reg: ldo8 { +- regulator-name = "vdd_ldo8,avdd_hdmi_pll"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo9 { +- regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- }; +- +- ldo_rtc { +- regulator-name = "vdd_rtc_out,vdd_cell"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +- +- temperature-sensor@4c { +- compatible = "onnn,nct1008"; +- reg = <0x4c>; +- }; +- }; +- +- kbc@7000e200 { +- status = "okay"; +- nvidia,debounce-delay-ms = <32>; +- nvidia,repeat-delay-ms = <160>; +- nvidia,ghost-filter; +- nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; +- nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; +- linux,keymap = ; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <5000>; +- nvidia,cpu-pwr-off-time = <5000>; +- nvidia,core-pwr-good-time = <3845 3845>; +- nvidia,core-pwr-off-time = <3875>; +- nvidia,sys-clock-req-active-high; +- }; +- +- memory-controller@7000f400 { +- emc-table@190000 { +- reg = <190000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <190000>; +- nvidia,emc-registers = <0x0000000c 0x00000026 +- 0x00000009 0x00000003 0x00000004 0x00000004 +- 0x00000002 0x0000000c 0x00000003 0x00000003 +- 0x00000002 0x00000001 0x00000004 0x00000005 +- 0x00000004 0x00000009 0x0000000d 0x0000059f +- 0x00000000 0x00000003 0x00000003 0x00000003 +- 0x00000003 0x00000001 0x0000000b 0x000000c8 +- 0x00000003 0x00000007 0x00000004 0x0000000f +- 0x00000002 0x00000000 0x00000000 0x00000002 +- 0x00000000 0x00000000 0x00000083 0xa06204ae +- 0x007dc010 0x00000000 0x00000000 0x00000000 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- +- emc-table@380000 { +- reg = <380000>; +- compatible = "nvidia,tegra20-emc-table"; +- clock-frequency = <380000>; +- nvidia,emc-registers = <0x00000017 0x0000004b +- 0x00000012 0x00000006 0x00000004 0x00000005 +- 0x00000003 0x0000000c 0x00000006 0x00000006 +- 0x00000003 0x00000001 0x00000004 0x00000005 +- 0x00000004 0x00000009 0x0000000d 0x00000b5f +- 0x00000000 0x00000003 0x00000003 0x00000006 +- 0x00000006 0x00000001 0x00000011 0x000000c8 +- 0x00000003 0x0000000e 0x00000007 0x0000000f +- 0x00000002 0x00000000 0x00000000 0x00000002 +- 0x00000000 0x00000000 0x00000083 0xe044048b +- 0x007d8010 0x00000000 0x00000000 0x00000000 +- 0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- }; +- +- usb@c5000000 { +- status = "okay"; +- dr_mode = "otg"; +- }; +- +- usb-phy@c5000000 { +- status = "okay"; +- vbus-supply = <&vbus_reg>; +- dr_mode = "otg"; +- }; +- +- usb@c5004000 { +- status = "okay"; +- nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) +- GPIO_ACTIVE_LOW>; +- }; +- +- usb-phy@c5004000 { +- status = "okay"; +- nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) +- GPIO_ACTIVE_LOW>; +- }; +- +- usb@c5008000 { +- status = "okay"; +- }; +- +- usb-phy@c5008000 { +- status = "okay"; +- }; +- +- mmc@c8000000 { +- status = "okay"; +- power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; +- bus-width = <4>; +- keep-power-in-suspend; +- }; +- +- mmc@c8000400 { +- status = "okay"; +- cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; +- power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; +- bus-width = <4>; +- }; +- +- mmc@c8000600 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- +- enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; +- power-supply = <&vdd_bl_reg>; +- pwms = <&pwm 2 5000000>; +- +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "Power"; +- gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- lid { +- label = "Lid"; +- gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; +- linux,input-type = <5>; /* EV_SW */ +- linux,code = <0>; /* SW_LID */ +- debounce-interval = <1>; +- wakeup-source; +- }; +- }; +- +- panel: panel { +- compatible = "chunghwa,claa101wa01a"; +- +- power-supply = <&vdd_pnl_reg>; +- enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; +- +- backlight = <&backlight>; +- ddc-i2c-bus = <&lvds_ddc>; +- }; +- +- vdd_5v0_reg: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_1v5"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; +- }; +- +- regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_1v2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vbus_reg: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_vbus_wup1"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(D, 0) 0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_pnl_reg: regulator@4 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_pnl"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vdd_bl_reg: regulator@5 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_bl"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vdd_hdmi: regulator@6 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_HDMI"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_5v0_reg>; +- }; +- +- sound { +- compatible = "nvidia,tegra-audio-wm8903-seaboard", +- "nvidia,tegra-audio-wm8903"; +- nvidia,model = "NVIDIA Tegra Seaboard"; +- +- nvidia,audio-routing = +- "Headphone Jack", "HPOUTR", +- "Headphone Jack", "HPOUTL", +- "Int Spk", "ROP", +- "Int Spk", "RON", +- "Int Spk", "LOP", +- "Int Spk", "LON", +- "Mic Jack", "MICBIAS", +- "IN1R", "Mic Jack"; +- +- nvidia,i2s-controller = <&tegra_i2s1>; +- nvidia,audio-codec = <&wm8903>; +- +- nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; +- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_LOW>; +- +- clocks = <&tegra_car TEGRA20_CLK_PLL_A>, +- <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA20_CLK_CDEV1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra20-tamonten.dtsi b/scripts/dtc/include-prefixes/arm/tegra20-tamonten.dtsi +deleted file mode 100644 +index dd4d506683de..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra20-tamonten.dtsi ++++ /dev/null +@@ -1,519 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "tegra20.dtsi" +- +-/ { +- model = "Avionic Design Tamonten SOM"; +- compatible = "ad,tamonten", "nvidia,tegra20"; +- +- aliases { +- rtc0 = "/i2c@7000d000/tps6586x@34"; +- rtc1 = "/rtc@7000e000"; +- serial0 = &uartd; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- reg = <0x00000000 0x20000000>; +- }; +- +- host1x@50000000 { +- hdmi@54280000 { +- vdd-supply = <&hdmi_vdd_reg>; +- pll-supply = <&hdmi_pll_reg>; +- +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) +- GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- pinmux@70000014 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- ata { +- nvidia,pins = "ata"; +- nvidia,function = "ide"; +- }; +- atb { +- nvidia,pins = "atb", "gma", "gme"; +- nvidia,function = "sdio4"; +- }; +- atc { +- nvidia,pins = "atc"; +- nvidia,function = "nand"; +- }; +- atd { +- nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", +- "spia", "spib", "spic"; +- nvidia,function = "gmi"; +- }; +- cdev1 { +- nvidia,pins = "cdev1"; +- nvidia,function = "plla_out"; +- }; +- cdev2 { +- nvidia,pins = "cdev2"; +- nvidia,function = "pllp_out4"; +- }; +- crtp { +- nvidia,pins = "crtp"; +- nvidia,function = "crt"; +- }; +- csus { +- nvidia,pins = "csus"; +- nvidia,function = "vi_sensor_clk"; +- }; +- dap1 { +- nvidia,pins = "dap1"; +- nvidia,function = "dap1"; +- }; +- dap2 { +- nvidia,pins = "dap2"; +- nvidia,function = "dap2"; +- }; +- dap3 { +- nvidia,pins = "dap3"; +- nvidia,function = "dap3"; +- }; +- dap4 { +- nvidia,pins = "dap4"; +- nvidia,function = "dap4"; +- }; +- dta { +- nvidia,pins = "dta", "dtd"; +- nvidia,function = "sdio2"; +- }; +- dtb { +- nvidia,pins = "dtb", "dtc", "dte"; +- nvidia,function = "rsvd1"; +- }; +- dtf { +- nvidia,pins = "dtf"; +- nvidia,function = "i2c3"; +- }; +- gmc { +- nvidia,pins = "gmc"; +- nvidia,function = "uartd"; +- }; +- gpu7 { +- nvidia,pins = "gpu7"; +- nvidia,function = "rtck"; +- }; +- gpv { +- nvidia,pins = "gpv", "slxa", "slxk"; +- nvidia,function = "pcie"; +- }; +- hdint { +- nvidia,pins = "hdint"; +- nvidia,function = "hdmi"; +- }; +- i2cp { +- nvidia,pins = "i2cp"; +- nvidia,function = "i2cp"; +- }; +- irrx { +- nvidia,pins = "irrx", "irtx"; +- nvidia,function = "uarta"; +- }; +- kbca { +- nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", +- "kbce", "kbcf"; +- nvidia,function = "kbc"; +- }; +- lcsn { +- nvidia,pins = "lcsn", "ld0", "ld1", "ld2", +- "ld3", "ld4", "ld5", "ld6", "ld7", +- "ld8", "ld9", "ld10", "ld11", "ld12", +- "ld13", "ld14", "ld15", "ld16", "ld17", +- "ldc", "ldi", "lhp0", "lhp1", "lhp2", +- "lhs", "lm0", "lm1", "lpp", "lpw0", +- "lpw1", "lpw2", "lsc0", "lsc1", "lsck", +- "lsda", "lsdi", "lspi", "lvp0", "lvp1", +- "lvs"; +- nvidia,function = "displaya"; +- }; +- owc { +- nvidia,pins = "owc", "spdi", "spdo", "uac"; +- nvidia,function = "rsvd2"; +- }; +- pmc { +- nvidia,pins = "pmc"; +- nvidia,function = "pwr_on"; +- }; +- rm { +- nvidia,pins = "rm"; +- nvidia,function = "i2c1"; +- }; +- sdb { +- nvidia,pins = "sdb", "sdc", "sdd"; +- nvidia,function = "pwm"; +- }; +- sdio1 { +- nvidia,pins = "sdio1"; +- nvidia,function = "sdio1"; +- }; +- slxc { +- nvidia,pins = "slxc", "slxd"; +- nvidia,function = "spdif"; +- }; +- spid { +- nvidia,pins = "spid", "spie", "spif"; +- nvidia,function = "spi1"; +- }; +- spig { +- nvidia,pins = "spig", "spih"; +- nvidia,function = "spi2_alt"; +- }; +- uaa { +- nvidia,pins = "uaa", "uab", "uda"; +- nvidia,function = "ulpi"; +- }; +- uad { +- nvidia,pins = "uad"; +- nvidia,function = "irda"; +- }; +- uca { +- nvidia,pins = "uca", "ucb"; +- nvidia,function = "uartc"; +- }; +- conf_ata { +- nvidia,pins = "ata", "atb", "atc", "atd", "ate", +- "cdev1", "cdev2", "dap1", "dtb", "gma", +- "gmb", "gmc", "gmd", "gme", "gpu7", +- "gpv", "i2cp", "irrx", "irtx", "pta", +- "rm", "slxa", "slxk", "spia", "spib", +- "uac"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_ck32 { +- nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", +- "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; +- nvidia,pull = ; +- }; +- conf_csus { +- nvidia,pins = "csus", "spid", "spif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_crtp { +- nvidia,pins = "crtp", "dap2", "dap3", "dap4", +- "dtc", "dte", "dtf", "gpu", "sdio1", +- "slxc", "slxd", "spdi", "spdo", "spig", +- "uda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_ddc { +- nvidia,pins = "ddc", "dta", "dtd", "kbca", +- "kbcb", "kbcc", "kbcd", "kbce", "kbcf", +- "sdc", "uad", "uca"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_hdint { +- nvidia,pins = "hdint", "lcsn", "ldc", "lm1", +- "lpw1", "lsc1", "lsck", "lsda", "lsdi", +- "lvp0", "owc", "sdb"; +- nvidia,tristate = ; +- }; +- conf_sdd { +- nvidia,pins = "sdd", "spic", "spie", "spih", +- "uaa", "uab", "ucb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_lc { +- nvidia,pins = "lc", "ls"; +- nvidia,pull = ; +- }; +- conf_ld0 { +- nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", +- "ld5", "ld6", "ld7", "ld8", "ld9", +- "ld10", "ld11", "ld12", "ld13", "ld14", +- "ld15", "ld16", "ld17", "ldi", "lhp0", +- "lhp1", "lhp2", "lhs", "lm0", "lpp", +- "lpw0", "lpw2", "lsc0", "lspi", "lvp1", +- "lvs", "pmc"; +- nvidia,tristate = ; +- }; +- conf_ld17_0 { +- nvidia,pins = "ld17_0", "ld19_18", "ld21_20", +- "ld23_22"; +- nvidia,pull = ; +- }; +- }; +- +- state_i2cmux_ddc: pinmux_i2cmux_ddc { +- ddc { +- nvidia,pins = "ddc"; +- nvidia,function = "i2c2"; +- }; +- pta { +- nvidia,pins = "pta"; +- nvidia,function = "rsvd4"; +- }; +- }; +- +- state_i2cmux_pta: pinmux_i2cmux_pta { +- ddc { +- nvidia,pins = "ddc"; +- nvidia,function = "rsvd4"; +- }; +- pta { +- nvidia,pins = "pta"; +- nvidia,function = "i2c2"; +- }; +- }; +- +- state_i2cmux_idle: pinmux_i2cmux_idle { +- ddc { +- nvidia,pins = "ddc"; +- nvidia,function = "rsvd4"; +- }; +- pta { +- nvidia,pins = "pta"; +- nvidia,function = "rsvd4"; +- }; +- }; +- }; +- +- i2s@70002800 { +- status = "okay"; +- }; +- +- serial@70006300 { +- status = "okay"; +- }; +- +- i2c@7000c000 { +- clock-frequency = <400000>; +- status = "okay"; +- }; +- +- i2c@7000c400 { +- clock-frequency = <100000>; +- status = "okay"; +- }; +- +- i2cmux { +- compatible = "i2c-mux-pinctrl"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c-parent = <&{/i2c@7000c400}>; +- +- pinctrl-names = "ddc", "pta", "idle"; +- pinctrl-0 = <&state_i2cmux_ddc>; +- pinctrl-1 = <&state_i2cmux_pta>; +- pinctrl-2 = <&state_i2cmux_idle>; +- +- hdmi_ddc: i2c@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- i2c@7000d000 { +- clock-frequency = <400000>; +- status = "okay"; +- +- pmic: tps6586x@34 { +- compatible = "ti,tps6586x"; +- reg = <0x34>; +- interrupts = ; +- +- ti,system-power-controller; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- /* vdd_5v0_reg must be provided by the base board */ +- sys-supply = <&vdd_5v0_reg>; +- vin-sm0-supply = <&sys_reg>; +- vin-sm1-supply = <&sys_reg>; +- vin-sm2-supply = <&sys_reg>; +- vinldo01-supply = <&sm2_reg>; +- vinldo23-supply = <&sm2_reg>; +- vinldo4-supply = <&sm2_reg>; +- vinldo678-supply = <&sm2_reg>; +- vinldo9-supply = <&sm2_reg>; +- +- regulators { +- sys_reg: sys { +- regulator-name = "vdd_sys"; +- regulator-always-on; +- }; +- +- sm0 { +- regulator-name = "vdd_sys_sm0,vdd_core"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- sm1 { +- regulator-name = "vdd_sys_sm1,vdd_cpu"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- sm2_reg: sm2 { +- regulator-name = "vdd_sys_sm2,vin_ldo*"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- regulator-always-on; +- }; +- +- pci_clk_reg: ldo0 { +- regulator-name = "vdd_ldo0,vddio_pex_clk"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo1 { +- regulator-name = "vdd_ldo1,avdd_pll*"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- ldo2 { +- regulator-name = "vdd_ldo2,vdd_rtc"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo3 { +- regulator-name = "vdd_ldo3,avdd_usb*"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo4 { +- regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo5 { +- regulator-name = "vdd_ldo5,vcore_mmc"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- ldo6 { +- regulator-name = "vdd_ldo6,avdd_vdac"; +- /* +- * According to the Tegra 2 Automotive +- * DataSheet, a typical value for this +- * would be 2.8V, but the PMIC only +- * supports 2.85V. +- */ +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- hdmi_vdd_reg: ldo7 { +- regulator-name = "vdd_ldo7,avdd_hdmi"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- hdmi_pll_reg: ldo8 { +- regulator-name = "vdd_ldo8,avdd_hdmi_pll"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo9 { +- regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam"; +- /* +- * According to the Tegra 2 Automotive +- * DataSheet, a typical value for this +- * would be 2.8V, but the PMIC only +- * supports 2.85V. +- */ +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- }; +- +- ldo_rtc { +- regulator-name = "vdd_rtc_out"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +- +- temperature-sensor@4c { +- compatible = "onnn,nct1008"; +- reg = <0x4c>; +- }; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <5000>; +- nvidia,cpu-pwr-off-time = <5000>; +- nvidia,core-pwr-good-time = <3845 3845>; +- nvidia,core-pwr-off-time = <3875>; +- nvidia,sys-clock-req-active-high; +- }; +- +- pcie@80003000 { +- avdd-pex-supply = <&pci_vdd_reg>; +- vdd-pex-supply = <&pci_vdd_reg>; +- avdd-pex-pll-supply = <&pci_vdd_reg>; +- avdd-plle-supply = <&pci_vdd_reg>; +- vddio-pex-clk-supply = <&pci_clk_reg>; +- }; +- +- usb@c5008000 { +- status = "okay"; +- }; +- +- usb-phy@c5008000 { +- status = "okay"; +- }; +- +- mmc@c8000600 { +- cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; +- bus-width = <4>; +- status = "okay"; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- pci_vdd_reg: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_1v05"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- gpio = <&pmic 2 0>; +- enable-active-high; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra20-tec.dts b/scripts/dtc/include-prefixes/arm/tegra20-tec.dts +deleted file mode 100644 +index 10ff09d86efa..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra20-tec.dts ++++ /dev/null +@@ -1,106 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "tegra20-tamonten.dtsi" +- +-/ { +- model = "Avionic Design Tamonten Evaluation Carrier"; +- compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; +- +- host1x@50000000 { +- hdmi@54280000 { +- status = "okay"; +- }; +- }; +- +- i2c@7000c000 { +- wm8903: wm8903@1a { +- compatible = "wlf,wm8903"; +- reg = <0x1a>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- micdet-cfg = <0>; +- micdet-delay = <100>; +- gpio-cfg = <0xffffffff +- 0xffffffff +- 0 +- 0xffffffff +- 0xffffffff>; +- }; +- }; +- +- pcie@80003000 { +- status = "okay"; +- +- pci@1,0 { +- status = "okay"; +- }; +- }; +- +- sound { +- compatible = "ad,tegra-audio-wm8903-tec", +- "nvidia,tegra-audio-wm8903"; +- nvidia,model = "Avionic Design TEC"; +- +- nvidia,audio-routing = +- "Headphone Jack", "HPOUTR", +- "Headphone Jack", "HPOUTL", +- "Int Spk", "ROP", +- "Int Spk", "RON", +- "Int Spk", "LOP", +- "Int Spk", "LON", +- "Mic Jack", "MICBIAS", +- "IN1L", "Mic Jack"; +- +- nvidia,i2s-controller = <&tegra_i2s1>; +- nvidia,audio-codec = <&wm8903>; +- +- nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; +- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) +- GPIO_ACTIVE_LOW>; +- +- clocks = <&tegra_car TEGRA20_CLK_PLL_A>, +- <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA20_CLK_CDEV1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- }; +- +- vcc_24v_reg: regulator@100 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_24v"; +- regulator-min-microvolt = <24000000>; +- regulator-max-microvolt = <24000000>; +- regulator-always-on; +- }; +- +- vdd_5v0_reg: regulator@101 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_5v0"; +- vin-supply = <&vcc_24v_reg>; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- vdd_3v3_reg: regulator@102 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_3v3"; +- vin-supply = <&vcc_24v_reg>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_1v8_reg: regulator@103 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_1v8"; +- vin-supply = <&vdd_3v3_reg>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra20-trimslice.dts b/scripts/dtc/include-prefixes/arm/tegra20-trimslice.dts +deleted file mode 100644 +index 4bc87bc0c2a4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra20-trimslice.dts ++++ /dev/null +@@ -1,467 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include "tegra20.dtsi" +-#include "tegra20-cpu-opp.dtsi" +- +-/ { +- model = "Compulab TrimSlice board"; +- compatible = "compulab,trimslice", "nvidia,tegra20"; +- +- aliases { +- rtc0 = "/i2c@7000c500/rtc@56"; +- rtc1 = "/rtc@7000e000"; +- serial0 = &uarta; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- reg = <0x00000000 0x40000000>; +- }; +- +- host1x@50000000 { +- hdmi@54280000 { +- status = "okay"; +- +- vdd-supply = <&hdmi_vdd_reg>; +- pll-supply = <&hdmi_pll_reg>; +- +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) +- GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- pinmux@70000014 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- ata { +- nvidia,pins = "ata"; +- nvidia,function = "ide"; +- }; +- atb { +- nvidia,pins = "atb", "gma"; +- nvidia,function = "sdio4"; +- }; +- atc { +- nvidia,pins = "atc", "gmb"; +- nvidia,function = "nand"; +- }; +- atd { +- nvidia,pins = "atd", "ate", "gme", "pta"; +- nvidia,function = "gmi"; +- }; +- cdev1 { +- nvidia,pins = "cdev1"; +- nvidia,function = "plla_out"; +- }; +- cdev2 { +- nvidia,pins = "cdev2"; +- nvidia,function = "pllp_out4"; +- }; +- crtp { +- nvidia,pins = "crtp"; +- nvidia,function = "crt"; +- }; +- csus { +- nvidia,pins = "csus"; +- nvidia,function = "vi_sensor_clk"; +- }; +- dap1 { +- nvidia,pins = "dap1"; +- nvidia,function = "dap1"; +- }; +- dap2 { +- nvidia,pins = "dap2"; +- nvidia,function = "dap2"; +- }; +- dap3 { +- nvidia,pins = "dap3"; +- nvidia,function = "dap3"; +- }; +- dap4 { +- nvidia,pins = "dap4"; +- nvidia,function = "dap4"; +- }; +- ddc { +- nvidia,pins = "ddc"; +- nvidia,function = "i2c2"; +- }; +- dta { +- nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; +- nvidia,function = "vi"; +- }; +- dtf { +- nvidia,pins = "dtf"; +- nvidia,function = "i2c3"; +- }; +- gmc { +- nvidia,pins = "gmc", "gmd"; +- nvidia,function = "sflash"; +- }; +- gpu { +- nvidia,pins = "gpu"; +- nvidia,function = "uarta"; +- }; +- gpu7 { +- nvidia,pins = "gpu7"; +- nvidia,function = "rtck"; +- }; +- gpv { +- nvidia,pins = "gpv", "slxa", "slxk"; +- nvidia,function = "pcie"; +- }; +- hdint { +- nvidia,pins = "hdint"; +- nvidia,function = "hdmi"; +- }; +- i2cp { +- nvidia,pins = "i2cp"; +- nvidia,function = "i2cp"; +- }; +- irrx { +- nvidia,pins = "irrx", "irtx"; +- nvidia,function = "uartb"; +- }; +- kbca { +- nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", +- "kbce", "kbcf"; +- nvidia,function = "kbc"; +- }; +- lcsn { +- nvidia,pins = "lcsn", "ld0", "ld1", "ld2", +- "ld3", "ld4", "ld5", "ld6", "ld7", +- "ld8", "ld9", "ld10", "ld11", "ld12", +- "ld13", "ld14", "ld15", "ld16", "ld17", +- "ldc", "ldi", "lhp0", "lhp1", "lhp2", +- "lhs", "lm0", "lm1", "lpp", "lpw0", +- "lpw1", "lpw2", "lsc0", "lsc1", "lsck", +- "lsda", "lsdi", "lspi", "lvp0", "lvp1", +- "lvs"; +- nvidia,function = "displaya"; +- }; +- owc { +- nvidia,pins = "owc", "uac"; +- nvidia,function = "rsvd2"; +- }; +- pmc { +- nvidia,pins = "pmc"; +- nvidia,function = "pwr_on"; +- }; +- rm { +- nvidia,pins = "rm"; +- nvidia,function = "i2c1"; +- }; +- sdb { +- nvidia,pins = "sdb", "sdc", "sdd"; +- nvidia,function = "pwm"; +- }; +- sdio1 { +- nvidia,pins = "sdio1"; +- nvidia,function = "sdio1"; +- }; +- slxc { +- nvidia,pins = "slxc", "slxd"; +- nvidia,function = "sdio3"; +- }; +- spdi { +- nvidia,pins = "spdi", "spdo"; +- nvidia,function = "spdif"; +- }; +- spia { +- nvidia,pins = "spia", "spib", "spic"; +- nvidia,function = "spi2"; +- }; +- spid { +- nvidia,pins = "spid", "spie", "spif"; +- nvidia,function = "spi1"; +- }; +- spig { +- nvidia,pins = "spig", "spih"; +- nvidia,function = "spi2_alt"; +- }; +- uaa { +- nvidia,pins = "uaa", "uab", "uda"; +- nvidia,function = "ulpi"; +- }; +- uad { +- nvidia,pins = "uad"; +- nvidia,function = "irda"; +- }; +- uca { +- nvidia,pins = "uca", "ucb"; +- nvidia,function = "uartc"; +- }; +- conf_ata { +- nvidia,pins = "ata", "atc", "atd", "ate", +- "crtp", "dap2", "dap3", "dap4", "dta", +- "dtb", "dtc", "dtd", "dte", "gmb", +- "gme", "i2cp", "pta", "slxc", "slxd", +- "spdi", "spdo", "uda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_atb { +- nvidia,pins = "atb", "cdev1", "cdev2", "dap1", +- "gma", "gmc", "gmd", "gpu", "gpu7", +- "gpv", "sdio1", "slxa", "slxk", "uac"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_ck32 { +- nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", +- "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; +- nvidia,pull = ; +- }; +- conf_csus { +- nvidia,pins = "csus", "spia", "spib", +- "spid", "spif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_ddc { +- nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_hdint { +- nvidia,pins = "hdint", "lcsn", "ldc", "lm1", +- "lpw1", "lsc1", "lsck", "lsda", "lsdi", +- "lvp0", "pmc"; +- nvidia,tristate = ; +- }; +- conf_irrx { +- nvidia,pins = "irrx", "irtx", "kbca", "kbcb", +- "kbcc", "kbcd", "kbce", "kbcf", "owc", +- "spic", "spie", "spig", "spih", "uaa", +- "uab", "uad", "uca", "ucb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_lc { +- nvidia,pins = "lc", "ls"; +- nvidia,pull = ; +- }; +- conf_ld0 { +- nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", +- "ld5", "ld6", "ld7", "ld8", "ld9", +- "ld10", "ld11", "ld12", "ld13", "ld14", +- "ld15", "ld16", "ld17", "ldi", "lhp0", +- "lhp1", "lhp2", "lhs", "lm0", "lpp", +- "lpw0", "lpw2", "lsc0", "lspi", "lvp1", +- "lvs", "sdb"; +- nvidia,tristate = ; +- }; +- conf_ld17_0 { +- nvidia,pins = "ld17_0", "ld19_18", "ld21_20", +- "ld23_22"; +- nvidia,pull = ; +- }; +- conf_spif { +- nvidia,pins = "spif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- }; +- }; +- +- i2s@70002800 { +- status = "okay"; +- }; +- +- serial@70006000 { +- status = "okay"; +- }; +- +- dvi_ddc: i2c@7000c000 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- spi@7000c380 { +- status = "okay"; +- spi-max-frequency = <48000000>; +- spi-flash@0 { +- compatible = "winbond,w25q80bl", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <48000000>; +- }; +- }; +- +- hdmi_ddc: i2c@7000c400 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- i2c@7000c500 { +- status = "okay"; +- clock-frequency = <400000>; +- +- codec: codec@1a { +- compatible = "ti,tlv320aic23"; +- reg = <0x1a>; +- }; +- +- rtc@56 { +- compatible = "emmicro,em3027"; +- reg = <0x56>; +- }; +- }; +- +- pmc@7000e400 { +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <5000>; +- nvidia,cpu-pwr-off-time = <5000>; +- nvidia,core-pwr-good-time = <3845 3845>; +- nvidia,core-pwr-off-time = <3875>; +- nvidia,sys-clock-req-active-high; +- }; +- +- pcie@80003000 { +- status = "okay"; +- +- avdd-pex-supply = <&pci_vdd_reg>; +- vdd-pex-supply = <&pci_vdd_reg>; +- avdd-pex-pll-supply = <&pci_vdd_reg>; +- avdd-plle-supply = <&pci_vdd_reg>; +- vddio-pex-clk-supply = <&pci_clk_reg>; +- +- pci@1,0 { +- status = "okay"; +- }; +- }; +- +- usb@c5000000 { +- status = "okay"; +- }; +- +- usb-phy@c5000000 { +- status = "okay"; +- vbus-supply = <&vbus_reg>; +- }; +- +- usb@c5004000 { +- status = "okay"; +- nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) +- GPIO_ACTIVE_LOW>; +- }; +- +- usb-phy@c5004000 { +- status = "okay"; +- nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) +- GPIO_ACTIVE_LOW>; +- }; +- +- usb@c5008000 { +- status = "okay"; +- }; +- +- usb-phy@c5008000 { +- status = "okay"; +- }; +- +- mmc@c8000000 { +- status = "okay"; +- broken-cd; +- bus-width = <4>; +- }; +- +- mmc@c8000600 { +- status = "okay"; +- cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; +- bus-width = <4>; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "Power"; +- gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- poweroff { +- compatible = "gpio-poweroff"; +- gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; +- }; +- +- hdmi_vdd_reg: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "avdd_hdmi"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- hdmi_pll_reg: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "avdd_hdmi_pll"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vbus_reg: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "usb1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(V, 2) 0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- pci_clk_reg: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "pci_clk"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- pci_vdd_reg: regulator@4 { +- compatible = "regulator-fixed"; +- regulator-name = "pci_vdd"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-always-on; +- }; +- +- sound { +- compatible = "nvidia,tegra-audio-trimslice"; +- nvidia,i2s-controller = <&tegra_i2s1>; +- nvidia,audio-codec = <&codec>; +- +- clocks = <&tegra_car TEGRA20_CLK_PLL_A>, +- <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA20_CLK_CDEV1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- }; +- +- cpus { +- cpu0: cpu@0 { +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- cpu@1 { +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra20-ventana.dts b/scripts/dtc/include-prefixes/arm/tegra20-ventana.dts +deleted file mode 100644 +index 5a2578b3707f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra20-ventana.dts ++++ /dev/null +@@ -1,756 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +-#include "tegra20.dtsi" +-#include "tegra20-cpu-opp.dtsi" +-#include "tegra20-cpu-opp-microvolt.dtsi" +- +-/ { +- model = "NVIDIA Tegra20 Ventana evaluation board"; +- compatible = "nvidia,ventana", "nvidia,tegra20"; +- +- aliases { +- rtc0 = "/i2c@7000d000/tps6586x@34"; +- rtc1 = "/rtc@7000e000"; +- serial0 = &uartd; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- reg = <0x00000000 0x40000000>; +- }; +- +- host1x@50000000 { +- dc@54200000 { +- rgb { +- status = "okay"; +- +- nvidia,panel = <&panel>; +- }; +- }; +- +- hdmi@54280000 { +- status = "okay"; +- +- vdd-supply = <&hdmi_vdd_reg>; +- pll-supply = <&hdmi_pll_reg>; +- +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) +- GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- pinmux@70000014 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- ata { +- nvidia,pins = "ata"; +- nvidia,function = "ide"; +- }; +- atb { +- nvidia,pins = "atb", "gma", "gme"; +- nvidia,function = "sdio4"; +- }; +- atc { +- nvidia,pins = "atc"; +- nvidia,function = "nand"; +- }; +- atd { +- nvidia,pins = "atd", "ate", "gmb", "spia", +- "spib", "spic"; +- nvidia,function = "gmi"; +- }; +- cdev1 { +- nvidia,pins = "cdev1"; +- nvidia,function = "plla_out"; +- }; +- cdev2 { +- nvidia,pins = "cdev2"; +- nvidia,function = "pllp_out4"; +- }; +- crtp { +- nvidia,pins = "crtp", "lm1"; +- nvidia,function = "crt"; +- }; +- csus { +- nvidia,pins = "csus"; +- nvidia,function = "vi_sensor_clk"; +- }; +- dap1 { +- nvidia,pins = "dap1"; +- nvidia,function = "dap1"; +- }; +- dap2 { +- nvidia,pins = "dap2"; +- nvidia,function = "dap2"; +- }; +- dap3 { +- nvidia,pins = "dap3"; +- nvidia,function = "dap3"; +- }; +- dap4 { +- nvidia,pins = "dap4"; +- nvidia,function = "dap4"; +- }; +- dta { +- nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; +- nvidia,function = "vi"; +- }; +- dtf { +- nvidia,pins = "dtf"; +- nvidia,function = "i2c3"; +- }; +- gmc { +- nvidia,pins = "gmc"; +- nvidia,function = "uartd"; +- }; +- gmd { +- nvidia,pins = "gmd"; +- nvidia,function = "sflash"; +- }; +- gpu { +- nvidia,pins = "gpu"; +- nvidia,function = "pwm"; +- }; +- gpu7 { +- nvidia,pins = "gpu7"; +- nvidia,function = "rtck"; +- }; +- gpv { +- nvidia,pins = "gpv", "slxa", "slxk"; +- nvidia,function = "pcie"; +- }; +- hdint { +- nvidia,pins = "hdint"; +- nvidia,function = "hdmi"; +- }; +- i2cp { +- nvidia,pins = "i2cp"; +- nvidia,function = "i2cp"; +- }; +- irrx { +- nvidia,pins = "irrx", "irtx"; +- nvidia,function = "uartb"; +- }; +- kbca { +- nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", +- "kbce", "kbcf"; +- nvidia,function = "kbc"; +- }; +- lcsn { +- nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", +- "lsdi", "lvp0"; +- nvidia,function = "rsvd4"; +- }; +- ld0 { +- nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", +- "ld5", "ld6", "ld7", "ld8", "ld9", +- "ld10", "ld11", "ld12", "ld13", "ld14", +- "ld15", "ld16", "ld17", "ldi", "lhp0", +- "lhp1", "lhp2", "lhs", "lpp", "lpw0", +- "lpw2", "lsc0", "lsc1", "lsck", "lsda", +- "lspi", "lvp1", "lvs"; +- nvidia,function = "displaya"; +- }; +- owc { +- nvidia,pins = "owc", "spdi", "spdo", "uac"; +- nvidia,function = "rsvd2"; +- }; +- pmc { +- nvidia,pins = "pmc"; +- nvidia,function = "pwr_on"; +- }; +- rm { +- nvidia,pins = "rm"; +- nvidia,function = "i2c1"; +- }; +- sdb { +- nvidia,pins = "sdb", "sdc", "sdd", "slxc"; +- nvidia,function = "sdio3"; +- }; +- sdio1 { +- nvidia,pins = "sdio1"; +- nvidia,function = "sdio1"; +- }; +- slxd { +- nvidia,pins = "slxd"; +- nvidia,function = "spdif"; +- }; +- spid { +- nvidia,pins = "spid", "spie", "spif"; +- nvidia,function = "spi1"; +- }; +- spig { +- nvidia,pins = "spig", "spih"; +- nvidia,function = "spi2_alt"; +- }; +- uaa { +- nvidia,pins = "uaa", "uab", "uda"; +- nvidia,function = "ulpi"; +- }; +- uad { +- nvidia,pins = "uad"; +- nvidia,function = "irda"; +- }; +- uca { +- nvidia,pins = "uca", "ucb"; +- nvidia,function = "uartc"; +- }; +- conf_ata { +- nvidia,pins = "ata", "atb", "atc", "atd", +- "cdev1", "cdev2", "dap1", "dap2", +- "dap4", "ddc", "dtf", "gma", "gmc", +- "gme", "gpu", "gpu7", "i2cp", "irrx", +- "irtx", "pta", "rm", "sdc", "sdd", +- "slxc", "slxd", "slxk", "spdi", "spdo", +- "uac", "uad", "uca", "ucb", "uda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_ate { +- nvidia,pins = "ate", "csus", "dap3", "gmd", +- "gpv", "owc", "spia", "spib", "spic", +- "spid", "spie", "spig"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_ck32 { +- nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", +- "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; +- nvidia,pull = ; +- }; +- conf_crtp { +- nvidia,pins = "crtp", "gmb", "slxa", "spih"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_dta { +- nvidia,pins = "dta", "dtb", "dtc", "dtd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_dte { +- nvidia,pins = "dte", "spif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_hdint { +- nvidia,pins = "hdint", "lcsn", "ldc", "lm1", +- "lpw1", "lsck", "lsda", "lsdi", "lvp0"; +- nvidia,tristate = ; +- }; +- conf_kbca { +- nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", +- "kbce", "kbcf", "sdio1", "uaa", "uab"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- conf_lc { +- nvidia,pins = "lc", "ls"; +- nvidia,pull = ; +- }; +- conf_ld0 { +- nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", +- "ld5", "ld6", "ld7", "ld8", "ld9", +- "ld10", "ld11", "ld12", "ld13", "ld14", +- "ld15", "ld16", "ld17", "ldi", "lhp0", +- "lhp1", "lhp2", "lhs", "lm0", "lpp", +- "lpw0", "lpw2", "lsc0", "lsc1", "lspi", +- "lvp1", "lvs", "pmc", "sdb"; +- nvidia,tristate = ; +- }; +- conf_ld17_0 { +- nvidia,pins = "ld17_0", "ld19_18", "ld21_20", +- "ld23_22"; +- nvidia,pull = ; +- }; +- drive_sdio1 { +- nvidia,pins = "drive_sdio1"; +- nvidia,high-speed-mode = ; +- nvidia,schmitt = ; +- nvidia,low-power-mode = ; +- nvidia,pull-down-strength = <31>; +- nvidia,pull-up-strength = <31>; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- }; +- }; +- +- state_i2cmux_ddc: pinmux_i2cmux_ddc { +- ddc { +- nvidia,pins = "ddc"; +- nvidia,function = "i2c2"; +- }; +- pta { +- nvidia,pins = "pta"; +- nvidia,function = "rsvd4"; +- }; +- }; +- +- state_i2cmux_pta: pinmux_i2cmux_pta { +- ddc { +- nvidia,pins = "ddc"; +- nvidia,function = "rsvd4"; +- }; +- pta { +- nvidia,pins = "pta"; +- nvidia,function = "i2c2"; +- }; +- }; +- +- state_i2cmux_idle: pinmux_i2cmux_idle { +- ddc { +- nvidia,pins = "ddc"; +- nvidia,function = "rsvd4"; +- }; +- pta { +- nvidia,pins = "pta"; +- nvidia,function = "rsvd4"; +- }; +- }; +- }; +- +- i2s@70002800 { +- status = "okay"; +- }; +- +- serial@70006300 { +- status = "okay"; +- }; +- +- pwm: pwm@7000a000 { +- status = "okay"; +- }; +- +- i2c@7000c000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- wm8903: wm8903@1a { +- compatible = "wlf,wm8903"; +- reg = <0x1a>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- micdet-cfg = <0>; +- micdet-delay = <100>; +- gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; +- }; +- +- /* ALS and proximity sensor */ +- isl29018@44 { +- compatible = "isil,isl29018"; +- reg = <0x44>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- }; +- }; +- +- i2c@7000c400 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- i2cmux { +- compatible = "i2c-mux-pinctrl"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c-parent = <&{/i2c@7000c400}>; +- +- pinctrl-names = "ddc", "pta", "idle"; +- pinctrl-0 = <&state_i2cmux_ddc>; +- pinctrl-1 = <&state_i2cmux_pta>; +- pinctrl-2 = <&state_i2cmux_idle>; +- +- hdmi_ddc: i2c@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- lvds_ddc: i2c@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- i2c@7000c500 { +- status = "okay"; +- clock-frequency = <400000>; +- }; +- +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- pmic: tps6586x@34 { +- compatible = "ti,tps6586x"; +- reg = <0x34>; +- interrupts = ; +- +- ti,system-power-controller; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- sys-supply = <&vdd_5v0_reg>; +- vin-sm0-supply = <&sys_reg>; +- vin-sm1-supply = <&sys_reg>; +- vin-sm2-supply = <&sys_reg>; +- vinldo01-supply = <&sm2_reg>; +- vinldo23-supply = <&sm2_reg>; +- vinldo4-supply = <&sm2_reg>; +- vinldo678-supply = <&sm2_reg>; +- vinldo9-supply = <&sm2_reg>; +- +- regulators { +- sys_reg: sys { +- regulator-name = "vdd_sys"; +- regulator-always-on; +- }; +- +- vdd_core: sm0 { +- regulator-name = "vdd_sm0,vdd_core"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1300000>; +- regulator-coupled-with = <&rtc_vdd &vdd_cpu>; +- regulator-coupled-max-spread = <170000 550000>; +- regulator-always-on; +- regulator-boot-on; +- +- nvidia,tegra-core-regulator; +- }; +- +- vdd_cpu: sm1 { +- regulator-name = "vdd_sm1,vdd_cpu"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1125000>; +- regulator-coupled-with = <&vdd_core &rtc_vdd>; +- regulator-coupled-max-spread = <550000 550000>; +- regulator-always-on; +- regulator-boot-on; +- +- nvidia,tegra-cpu-regulator; +- }; +- +- sm2_reg: sm2 { +- regulator-name = "vdd_sm2,vin_ldo*"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- regulator-always-on; +- }; +- +- /* LDO0 is not connected to anything */ +- +- ldo1 { +- regulator-name = "vdd_ldo1,avdd_pll*"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- rtc_vdd: ldo2 { +- regulator-name = "vdd_ldo2,vdd_rtc"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1300000>; +- regulator-coupled-with = <&vdd_core &vdd_cpu>; +- regulator-coupled-max-spread = <170000 550000>; +- regulator-always-on; +- regulator-boot-on; +- +- nvidia,tegra-rtc-regulator; +- }; +- +- ldo3 { +- regulator-name = "vdd_ldo3,avdd_usb*"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo4 { +- regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo5 { +- regulator-name = "vdd_ldo5,vcore_mmc"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- }; +- +- ldo6 { +- regulator-name = "vdd_ldo6,avdd_vdac"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- hdmi_vdd_reg: ldo7 { +- regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- hdmi_pll_reg: ldo8 { +- regulator-name = "vdd_ldo8,avdd_hdmi_pll"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo9 { +- regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- }; +- +- ldo_rtc { +- regulator-name = "vdd_rtc_out,vdd_cell"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +- +- nct1008: temperature-sensor@4c { +- compatible = "onnn,nct1008"; +- reg = <0x4c>; +- #thermal-sensor-cells = <1>; +- }; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <2000>; +- nvidia,cpu-pwr-off-time = <100>; +- nvidia,core-pwr-good-time = <3845 3845>; +- nvidia,core-pwr-off-time = <458>; +- nvidia,sys-clock-req-active-high; +- }; +- +- usb@c5000000 { +- status = "okay"; +- }; +- +- usb-phy@c5000000 { +- status = "okay"; +- }; +- +- usb@c5004000 { +- status = "okay"; +- nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) +- GPIO_ACTIVE_LOW>; +- }; +- +- usb-phy@c5004000 { +- status = "okay"; +- nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) +- GPIO_ACTIVE_LOW>; +- }; +- +- usb@c5008000 { +- status = "okay"; +- }; +- +- usb-phy@c5008000 { +- status = "okay"; +- }; +- +- mmc@c8000000 { +- status = "okay"; +- power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; +- bus-width = <4>; +- keep-power-in-suspend; +- }; +- +- mmc@c8000400 { +- status = "okay"; +- cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; +- power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; +- bus-width = <4>; +- }; +- +- mmc@c8000600 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- +- enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; +- power-supply = <&vdd_bl_reg>; +- pwms = <&pwm 2 5000000>; +- +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- cpus { +- cpu0: cpu@0 { +- cpu-supply = <&vdd_cpu>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- cpu-supply = <&vdd_cpu>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "Power"; +- gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- panel: panel { +- compatible = "chunghwa,claa101wa01a"; +- +- power-supply = <&vdd_pnl_reg>; +- enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; +- +- backlight = <&backlight>; +- ddc-i2c-bus = <&lvds_ddc>; +- }; +- +- vdd_5v0_reg: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_1v5"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; +- }; +- +- regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_1v2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vdd_pnl_reg: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_pnl"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vdd_bl_reg: regulator@4 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_bl"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sound { +- compatible = "nvidia,tegra-audio-wm8903-ventana", +- "nvidia,tegra-audio-wm8903"; +- nvidia,model = "NVIDIA Tegra Ventana"; +- +- nvidia,audio-routing = +- "Headphone Jack", "HPOUTR", +- "Headphone Jack", "HPOUTL", +- "Int Spk", "ROP", +- "Int Spk", "RON", +- "Int Spk", "LOP", +- "Int Spk", "LON", +- "Mic Jack", "MICBIAS", +- "IN1L", "Mic Jack"; +- +- nvidia,i2s-controller = <&tegra_i2s1>; +- nvidia,audio-codec = <&wm8903>; +- +- nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; +- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; +- nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) +- GPIO_ACTIVE_HIGH>; +- nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) +- GPIO_ACTIVE_HIGH>; +- +- clocks = <&tegra_car TEGRA20_CLK_PLL_A>, +- <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA20_CLK_CDEV1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- }; +- +- thermal-zones { +- cpu-thermal { +- polling-delay-passive = <1000>; /* milliseconds */ +- polling-delay = <5000>; /* milliseconds */ +- +- thermal-sensors = <&nct1008 1>; +- +- trips { +- trip0: cpu-alert0 { +- /* start throttling at 50C */ +- temperature = <50000>; +- hysteresis = <200>; +- type = "passive"; +- }; +- +- trip1: cpu-crit { +- /* shut down at 60C */ +- temperature = <60000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&trip0>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra20.dtsi b/scripts/dtc/include-prefixes/arm/tegra20.dtsi +deleted file mode 100644 +index 6ce498178105..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra20.dtsi ++++ /dev/null +@@ -1,916 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include "tegra20-peripherals-opp.dtsi" +- +-/ { +- compatible = "nvidia,tegra20"; +- interrupt-parent = <&lic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@0 { +- device_type = "memory"; +- reg = <0 0>; +- }; +- +- sram@40000000 { +- compatible = "mmio-sram"; +- reg = <0x40000000 0x40000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x40000000 0x40000>; +- +- vde_pool: sram@400 { +- reg = <0x400 0x3fc00>; +- pool; +- }; +- }; +- +- host1x@50000000 { +- compatible = "nvidia,tegra20-host1x"; +- reg = <0x50000000 0x00024000>; +- interrupts = , /* syncpt */ +- ; /* general */ +- interrupt-names = "syncpt", "host1x"; +- clocks = <&tegra_car TEGRA20_CLK_HOST1X>; +- clock-names = "host1x"; +- resets = <&tegra_car 28>; +- reset-names = "host1x"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0x54000000 0x54000000 0x04000000>; +- +- mpe@54040000 { +- compatible = "nvidia,tegra20-mpe"; +- reg = <0x54040000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_MPE>; +- resets = <&tegra_car 60>; +- reset-names = "mpe"; +- }; +- +- vi@54080000 { +- compatible = "nvidia,tegra20-vi"; +- reg = <0x54080000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_VI>; +- resets = <&tegra_car 20>; +- reset-names = "vi"; +- }; +- +- epp@540c0000 { +- compatible = "nvidia,tegra20-epp"; +- reg = <0x540c0000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_EPP>; +- resets = <&tegra_car 19>; +- reset-names = "epp"; +- }; +- +- isp@54100000 { +- compatible = "nvidia,tegra20-isp"; +- reg = <0x54100000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_ISP>; +- resets = <&tegra_car 23>; +- reset-names = "isp"; +- }; +- +- gr2d@54140000 { +- compatible = "nvidia,tegra20-gr2d"; +- reg = <0x54140000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_GR2D>; +- resets = <&tegra_car 21>; +- reset-names = "2d"; +- }; +- +- gr3d@54180000 { +- compatible = "nvidia,tegra20-gr3d"; +- reg = <0x54180000 0x00040000>; +- clocks = <&tegra_car TEGRA20_CLK_GR3D>; +- resets = <&tegra_car 24>; +- reset-names = "3d"; +- }; +- +- dc@54200000 { +- compatible = "nvidia,tegra20-dc"; +- reg = <0x54200000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_DISP1>, +- <&tegra_car TEGRA20_CLK_PLL_P>; +- clock-names = "dc", "parent"; +- resets = <&tegra_car 27>; +- reset-names = "dc"; +- +- nvidia,head = <0>; +- +- interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, +- <&mc TEGRA20_MC_DISPLAY0B &emc>, +- <&mc TEGRA20_MC_DISPLAY1B &emc>, +- <&mc TEGRA20_MC_DISPLAY0C &emc>, +- <&mc TEGRA20_MC_DISPLAYHC &emc>; +- interconnect-names = "wina", +- "winb", +- "winb-vfilter", +- "winc", +- "cursor"; +- +- rgb { +- status = "disabled"; +- }; +- }; +- +- dc@54240000 { +- compatible = "nvidia,tegra20-dc"; +- reg = <0x54240000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_DISP2>, +- <&tegra_car TEGRA20_CLK_PLL_P>; +- clock-names = "dc", "parent"; +- resets = <&tegra_car 26>; +- reset-names = "dc"; +- +- nvidia,head = <1>; +- +- interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, +- <&mc TEGRA20_MC_DISPLAY0BB &emc>, +- <&mc TEGRA20_MC_DISPLAY1BB &emc>, +- <&mc TEGRA20_MC_DISPLAY0CB &emc>, +- <&mc TEGRA20_MC_DISPLAYHCB &emc>; +- interconnect-names = "wina", +- "winb", +- "winb-vfilter", +- "winc", +- "cursor"; +- +- rgb { +- status = "disabled"; +- }; +- }; +- +- hdmi@54280000 { +- compatible = "nvidia,tegra20-hdmi"; +- reg = <0x54280000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_HDMI>, +- <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; +- clock-names = "hdmi", "parent"; +- resets = <&tegra_car 51>; +- reset-names = "hdmi"; +- status = "disabled"; +- }; +- +- tvo@542c0000 { +- compatible = "nvidia,tegra20-tvo"; +- reg = <0x542c0000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_TVO>; +- status = "disabled"; +- }; +- +- dsi@54300000 { +- compatible = "nvidia,tegra20-dsi"; +- reg = <0x54300000 0x00040000>; +- clocks = <&tegra_car TEGRA20_CLK_DSI>, +- <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; +- clock-names = "dsi", "parent"; +- resets = <&tegra_car 48>; +- reset-names = "dsi"; +- status = "disabled"; +- }; +- }; +- +- timer@50040600 { +- compatible = "arm,cortex-a9-twd-timer"; +- interrupt-parent = <&intc>; +- reg = <0x50040600 0x20>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_TWD>; +- }; +- +- intc: interrupt-controller@50041000 { +- compatible = "arm,cortex-a9-gic"; +- reg = <0x50041000 0x1000>, +- <0x50040100 0x0100>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&intc>; +- }; +- +- cache-controller@50043000 { +- compatible = "arm,pl310-cache"; +- reg = <0x50043000 0x1000>; +- arm,data-latency = <5 5 2>; +- arm,tag-latency = <4 4 2>; +- cache-unified; +- cache-level = <2>; +- }; +- +- lic: interrupt-controller@60004000 { +- compatible = "nvidia,tegra20-ictlr"; +- reg = <0x60004000 0x100>, +- <0x60004100 0x50>, +- <0x60004200 0x50>, +- <0x60004300 0x50>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&intc>; +- }; +- +- timer@60005000 { +- compatible = "nvidia,tegra20-timer"; +- reg = <0x60005000 0x60>; +- interrupts = , +- , +- , +- ; +- clocks = <&tegra_car TEGRA20_CLK_TIMER>; +- }; +- +- tegra_car: clock@60006000 { +- compatible = "nvidia,tegra20-car"; +- reg = <0x60006000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- flow-controller@60007000 { +- compatible = "nvidia,tegra20-flowctrl"; +- reg = <0x60007000 0x1000>; +- }; +- +- apbdma: dma@6000a000 { +- compatible = "nvidia,tegra20-apbdma"; +- reg = <0x6000a000 0x1200>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&tegra_car TEGRA20_CLK_APBDMA>; +- resets = <&tegra_car 34>; +- reset-names = "dma"; +- #dma-cells = <1>; +- }; +- +- ahb@6000c000 { +- compatible = "nvidia,tegra20-ahb"; +- reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */ +- }; +- +- gpio: gpio@6000d000 { +- compatible = "nvidia,tegra20-gpio"; +- reg = <0x6000d000 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- ; +- #gpio-cells = <2>; +- gpio-controller; +- #interrupt-cells = <2>; +- interrupt-controller; +- /* +- gpio-ranges = <&pinmux 0 0 224>; +- */ +- }; +- +- vde@6001a000 { +- compatible = "nvidia,tegra20-vde"; +- reg = <0x6001a000 0x1000>, /* Syntax Engine */ +- <0x6001b000 0x1000>, /* Video Bitstream Engine */ +- <0x6001c000 0x100>, /* Macroblock Engine */ +- <0x6001c200 0x100>, /* Post-processing Engine */ +- <0x6001c400 0x100>, /* Motion Compensation Engine */ +- <0x6001c600 0x100>, /* Transform Engine */ +- <0x6001c800 0x100>, /* Pixel prediction block */ +- <0x6001ca00 0x100>, /* Video DMA */ +- <0x6001d800 0x300>; /* Video frame controls */ +- reg-names = "sxe", "bsev", "mbe", "ppe", "mce", +- "tfe", "ppb", "vdma", "frameid"; +- iram = <&vde_pool>; /* IRAM region */ +- interrupts = , /* Sync token interrupt */ +- , /* BSE-V interrupt */ +- ; /* SXE interrupt */ +- interrupt-names = "sync-token", "bsev", "sxe"; +- clocks = <&tegra_car TEGRA20_CLK_VDE>; +- reset-names = "vde", "mc"; +- resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; +- }; +- +- apbmisc@70000800 { +- compatible = "nvidia,tegra20-apbmisc"; +- reg = <0x70000800 0x64>, /* Chip revision */ +- <0x70000008 0x04>; /* Strapping options */ +- }; +- +- pinmux: pinmux@70000014 { +- compatible = "nvidia,tegra20-pinmux"; +- reg = <0x70000014 0x10>, /* Tri-state registers */ +- <0x70000080 0x20>, /* Mux registers */ +- <0x700000a0 0x14>, /* Pull-up/down registers */ +- <0x70000868 0xa8>; /* Pad control registers */ +- }; +- +- das@70000c00 { +- compatible = "nvidia,tegra20-das"; +- reg = <0x70000c00 0x80>; +- }; +- +- tegra_ac97: ac97@70002000 { +- compatible = "nvidia,tegra20-ac97"; +- reg = <0x70002000 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_AC97>; +- resets = <&tegra_car 3>; +- reset-names = "ac97"; +- dmas = <&apbdma 12>, <&apbdma 12>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- tegra_i2s1: i2s@70002800 { +- compatible = "nvidia,tegra20-i2s"; +- reg = <0x70002800 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_I2S1>; +- resets = <&tegra_car 11>; +- reset-names = "i2s"; +- dmas = <&apbdma 2>, <&apbdma 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- tegra_i2s2: i2s@70002a00 { +- compatible = "nvidia,tegra20-i2s"; +- reg = <0x70002a00 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_I2S2>; +- resets = <&tegra_car 18>; +- reset-names = "i2s"; +- dmas = <&apbdma 1>, <&apbdma 1>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- /* +- * There are two serial driver i.e. 8250 based simple serial +- * driver and APB DMA based serial driver for higher baudrate +- * and performace. To enable the 8250 based driver, the compatible +- * is "nvidia,tegra20-uart" and to enable the APB DMA based serial +- * driver, the compatible is "nvidia,tegra20-hsuart". +- */ +- uarta: serial@70006000 { +- compatible = "nvidia,tegra20-uart"; +- reg = <0x70006000 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_UARTA>; +- resets = <&tegra_car 6>; +- reset-names = "serial"; +- dmas = <&apbdma 8>, <&apbdma 8>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uartb: serial@70006040 { +- compatible = "nvidia,tegra20-uart"; +- reg = <0x70006040 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_UARTB>; +- resets = <&tegra_car 7>; +- reset-names = "serial"; +- dmas = <&apbdma 9>, <&apbdma 9>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uartc: serial@70006200 { +- compatible = "nvidia,tegra20-uart"; +- reg = <0x70006200 0x100>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_UARTC>; +- resets = <&tegra_car 55>; +- reset-names = "serial"; +- dmas = <&apbdma 10>, <&apbdma 10>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uartd: serial@70006300 { +- compatible = "nvidia,tegra20-uart"; +- reg = <0x70006300 0x100>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_UARTD>; +- resets = <&tegra_car 65>; +- reset-names = "serial"; +- dmas = <&apbdma 19>, <&apbdma 19>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uarte: serial@70006400 { +- compatible = "nvidia,tegra20-uart"; +- reg = <0x70006400 0x100>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_UARTE>; +- resets = <&tegra_car 66>; +- reset-names = "serial"; +- dmas = <&apbdma 20>, <&apbdma 20>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- nand-controller@70008000 { +- compatible = "nvidia,tegra20-nand"; +- reg = <0x70008000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; +- clock-names = "nand"; +- resets = <&tegra_car 13>; +- reset-names = "nand"; +- assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; +- assigned-clock-rates = <150000000>; +- status = "disabled"; +- }; +- +- gmi@70009000 { +- compatible = "nvidia,tegra20-gmi"; +- reg = <0x70009000 0x1000>; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0 0xd0000000 0xfffffff>; +- clocks = <&tegra_car TEGRA20_CLK_NOR>; +- clock-names = "gmi"; +- resets = <&tegra_car 42>; +- reset-names = "gmi"; +- status = "disabled"; +- }; +- +- pwm: pwm@7000a000 { +- compatible = "nvidia,tegra20-pwm"; +- reg = <0x7000a000 0x100>; +- #pwm-cells = <2>; +- clocks = <&tegra_car TEGRA20_CLK_PWM>; +- resets = <&tegra_car 17>; +- reset-names = "pwm"; +- status = "disabled"; +- }; +- +- rtc@7000e000 { +- compatible = "nvidia,tegra20-rtc"; +- reg = <0x7000e000 0x100>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_RTC>; +- }; +- +- i2c@7000c000 { +- compatible = "nvidia,tegra20-i2c"; +- reg = <0x7000c000 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA20_CLK_I2C1>, +- <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; +- clock-names = "div-clk", "fast-clk"; +- resets = <&tegra_car 12>; +- reset-names = "i2c"; +- dmas = <&apbdma 21>, <&apbdma 21>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000c380 { +- compatible = "nvidia,tegra20-sflash"; +- reg = <0x7000c380 0x80>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA20_CLK_SPI>; +- resets = <&tegra_car 43>; +- reset-names = "spi"; +- dmas = <&apbdma 11>, <&apbdma 11>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000c400 { +- compatible = "nvidia,tegra20-i2c"; +- reg = <0x7000c400 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA20_CLK_I2C2>, +- <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; +- clock-names = "div-clk", "fast-clk"; +- resets = <&tegra_car 54>; +- reset-names = "i2c"; +- dmas = <&apbdma 22>, <&apbdma 22>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000c500 { +- compatible = "nvidia,tegra20-i2c"; +- reg = <0x7000c500 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA20_CLK_I2C3>, +- <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; +- clock-names = "div-clk", "fast-clk"; +- resets = <&tegra_car 67>; +- reset-names = "i2c"; +- dmas = <&apbdma 23>, <&apbdma 23>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000d000 { +- compatible = "nvidia,tegra20-i2c-dvc"; +- reg = <0x7000d000 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA20_CLK_DVC>, +- <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; +- clock-names = "div-clk", "fast-clk"; +- resets = <&tegra_car 47>; +- reset-names = "i2c"; +- dmas = <&apbdma 24>, <&apbdma 24>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000d400 { +- compatible = "nvidia,tegra20-slink"; +- reg = <0x7000d400 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA20_CLK_SBC1>; +- resets = <&tegra_car 41>; +- reset-names = "spi"; +- dmas = <&apbdma 15>, <&apbdma 15>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000d600 { +- compatible = "nvidia,tegra20-slink"; +- reg = <0x7000d600 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA20_CLK_SBC2>; +- resets = <&tegra_car 44>; +- reset-names = "spi"; +- dmas = <&apbdma 16>, <&apbdma 16>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000d800 { +- compatible = "nvidia,tegra20-slink"; +- reg = <0x7000d800 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA20_CLK_SBC3>; +- resets = <&tegra_car 46>; +- reset-names = "spi"; +- dmas = <&apbdma 17>, <&apbdma 17>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000da00 { +- compatible = "nvidia,tegra20-slink"; +- reg = <0x7000da00 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA20_CLK_SBC4>; +- resets = <&tegra_car 68>; +- reset-names = "spi"; +- dmas = <&apbdma 18>, <&apbdma 18>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- kbc@7000e200 { +- compatible = "nvidia,tegra20-kbc"; +- reg = <0x7000e200 0x100>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_KBC>; +- resets = <&tegra_car 36>; +- reset-names = "kbc"; +- status = "disabled"; +- }; +- +- tegra_pmc: pmc@7000e400 { +- compatible = "nvidia,tegra20-pmc"; +- reg = <0x7000e400 0x400>; +- clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; +- clock-names = "pclk", "clk32k_in"; +- #clock-cells = <1>; +- }; +- +- mc: memory-controller@7000f000 { +- compatible = "nvidia,tegra20-mc-gart"; +- reg = <0x7000f000 0x00000400>, /* controller registers */ +- <0x58000000 0x02000000>; /* GART aperture */ +- clocks = <&tegra_car TEGRA20_CLK_MC>; +- clock-names = "mc"; +- interrupts = ; +- #reset-cells = <1>; +- #iommu-cells = <0>; +- #interconnect-cells = <1>; +- }; +- +- emc: memory-controller@7000f400 { +- compatible = "nvidia,tegra20-emc"; +- reg = <0x7000f400 0x400>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_EMC>; +- #address-cells = <1>; +- #size-cells = <0>; +- #interconnect-cells = <0>; +- +- operating-points-v2 = <&emc_icc_dvfs_opp_table>; +- nvidia,memory-controller = <&mc>; +- }; +- +- fuse@7000f800 { +- compatible = "nvidia,tegra20-efuse"; +- reg = <0x7000f800 0x400>; +- clocks = <&tegra_car TEGRA20_CLK_FUSE>; +- clock-names = "fuse"; +- resets = <&tegra_car 39>; +- reset-names = "fuse"; +- }; +- +- pcie@80003000 { +- compatible = "nvidia,tegra20-pcie"; +- device_type = "pci"; +- reg = <0x80003000 0x00000800>, /* PADS registers */ +- <0x80003800 0x00000200>, /* AFI registers */ +- <0x90000000 0x10000000>; /* configuration space */ +- reg-names = "pads", "afi", "cs"; +- interrupts = , /* controller interrupt */ +- ; /* MSI interrupt */ +- interrupt-names = "intr", "msi"; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; +- +- bus-range = <0x00 0xff>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */ +- <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */ +- <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */ +- <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */ +- <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ +- +- clocks = <&tegra_car TEGRA20_CLK_PEX>, +- <&tegra_car TEGRA20_CLK_AFI>, +- <&tegra_car TEGRA20_CLK_PLL_E>; +- clock-names = "pex", "afi", "pll_e"; +- resets = <&tegra_car 70>, +- <&tegra_car 72>, +- <&tegra_car 74>; +- reset-names = "pex", "afi", "pcie_x"; +- status = "disabled"; +- +- pci@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; +- reg = <0x000800 0 0 0 0>; +- bus-range = <0x00 0xff>; +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- ranges; +- +- nvidia,num-lanes = <2>; +- }; +- +- pci@2,0 { +- device_type = "pci"; +- assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; +- reg = <0x001000 0 0 0 0>; +- bus-range = <0x00 0xff>; +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- ranges; +- +- nvidia,num-lanes = <2>; +- }; +- }; +- +- usb@c5000000 { +- compatible = "nvidia,tegra20-ehci", "usb-ehci"; +- reg = <0xc5000000 0x4000>; +- interrupts = ; +- phy_type = "utmi"; +- nvidia,has-legacy-mode; +- clocks = <&tegra_car TEGRA20_CLK_USBD>; +- resets = <&tegra_car 22>; +- reset-names = "usb"; +- nvidia,needs-double-reset; +- nvidia,phy = <&phy1>; +- status = "disabled"; +- }; +- +- phy1: usb-phy@c5000000 { +- compatible = "nvidia,tegra20-usb-phy"; +- reg = <0xc5000000 0x4000>, +- <0xc5000000 0x4000>; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA20_CLK_USBD>, +- <&tegra_car TEGRA20_CLK_PLL_U>, +- <&tegra_car TEGRA20_CLK_CLK_M>, +- <&tegra_car TEGRA20_CLK_USBD>; +- clock-names = "reg", "pll_u", "timer", "utmi-pads"; +- resets = <&tegra_car 22>, <&tegra_car 22>; +- reset-names = "usb", "utmi-pads"; +- #phy-cells = <0>; +- nvidia,has-legacy-mode; +- nvidia,hssync-start-delay = <9>; +- nvidia,idle-wait-delay = <17>; +- nvidia,elastic-limit = <16>; +- nvidia,term-range-adj = <6>; +- nvidia,xcvr-setup = <9>; +- nvidia,xcvr-lsfslew = <1>; +- nvidia,xcvr-lsrslew = <1>; +- nvidia,has-utmi-pad-registers; +- status = "disabled"; +- }; +- +- usb@c5004000 { +- compatible = "nvidia,tegra20-ehci", "usb-ehci"; +- reg = <0xc5004000 0x4000>; +- interrupts = ; +- phy_type = "ulpi"; +- clocks = <&tegra_car TEGRA20_CLK_USB2>; +- resets = <&tegra_car 58>; +- reset-names = "usb"; +- nvidia,phy = <&phy2>; +- status = "disabled"; +- }; +- +- phy2: usb-phy@c5004000 { +- compatible = "nvidia,tegra20-usb-phy"; +- reg = <0xc5004000 0x4000>; +- phy_type = "ulpi"; +- clocks = <&tegra_car TEGRA20_CLK_USB2>, +- <&tegra_car TEGRA20_CLK_PLL_U>, +- <&tegra_car TEGRA20_CLK_CDEV2>; +- clock-names = "reg", "pll_u", "ulpi-link"; +- resets = <&tegra_car 58>, <&tegra_car 22>; +- reset-names = "usb", "utmi-pads"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- usb@c5008000 { +- compatible = "nvidia,tegra20-ehci", "usb-ehci"; +- reg = <0xc5008000 0x4000>; +- interrupts = ; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA20_CLK_USB3>; +- resets = <&tegra_car 59>; +- reset-names = "usb"; +- nvidia,phy = <&phy3>; +- status = "disabled"; +- }; +- +- phy3: usb-phy@c5008000 { +- compatible = "nvidia,tegra20-usb-phy"; +- reg = <0xc5008000 0x4000>, +- <0xc5000000 0x4000>; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA20_CLK_USB3>, +- <&tegra_car TEGRA20_CLK_PLL_U>, +- <&tegra_car TEGRA20_CLK_CLK_M>, +- <&tegra_car TEGRA20_CLK_USBD>; +- clock-names = "reg", "pll_u", "timer", "utmi-pads"; +- resets = <&tegra_car 59>, <&tegra_car 22>; +- reset-names = "usb", "utmi-pads"; +- #phy-cells = <0>; +- nvidia,hssync-start-delay = <9>; +- nvidia,idle-wait-delay = <17>; +- nvidia,elastic-limit = <16>; +- nvidia,term-range-adj = <6>; +- nvidia,xcvr-setup = <9>; +- nvidia,xcvr-lsfslew = <2>; +- nvidia,xcvr-lsrslew = <2>; +- status = "disabled"; +- }; +- +- mmc@c8000000 { +- compatible = "nvidia,tegra20-sdhci"; +- reg = <0xc8000000 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; +- clock-names = "sdhci"; +- resets = <&tegra_car 14>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- mmc@c8000200 { +- compatible = "nvidia,tegra20-sdhci"; +- reg = <0xc8000200 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; +- clock-names = "sdhci"; +- resets = <&tegra_car 9>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- mmc@c8000400 { +- compatible = "nvidia,tegra20-sdhci"; +- reg = <0xc8000400 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; +- clock-names = "sdhci"; +- resets = <&tegra_car 69>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- mmc@c8000600 { +- compatible = "nvidia,tegra20-sdhci"; +- reg = <0xc8000600 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; +- clock-names = "sdhci"; +- resets = <&tegra_car 15>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- clocks = <&tegra_car TEGRA20_CLK_CCLK>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <1>; +- clocks = <&tegra_car TEGRA20_CLK_CCLK>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = , +- ; +- interrupt-affinity = <&{/cpus/cpu@0}>, +- <&{/cpus/cpu@1}>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-apalis-eval.dts b/scripts/dtc/include-prefixes/arm/tegra30-apalis-eval.dts +deleted file mode 100644 +index 9f653ef41da4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-apalis-eval.dts ++++ /dev/null +@@ -1,248 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include "tegra30-apalis.dtsi" +- +-/ { +- model = "Toradex Apalis T30 on Apalis Evaluation Board"; +- compatible = "toradex,apalis_t30-eval", "toradex,apalis_t30", +- "nvidia,tegra30"; +- +- aliases { +- rtc0 = "/i2c@7000c000/rtc@68"; +- rtc1 = "/i2c@7000d000/pmic@2d"; +- rtc2 = "/rtc@7000e000"; +- serial0 = &uarta; +- serial1 = &uartb; +- serial2 = &uartc; +- serial3 = &uartd; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- pcie@3000 { +- pci@1,0 { +- status = "okay"; +- }; +- +- pci@2,0 { +- status = "okay"; +- }; +- }; +- +- host1x@50000000 { +- dc@54200000 { +- rgb { +- status = "okay"; +- nvidia,panel = <&panel>; +- }; +- }; +- +- hdmi@54280000 { +- status = "okay"; +- hdmi-supply = <®_5v0>; +- }; +- }; +- +- /* Apalis UART1 */ +- serial@70006000 { +- status = "okay"; +- }; +- +- /* Apalis UART2 */ +- serial@70006040 { +- status = "okay"; +- }; +- +- /* Apalis UART3 */ +- serial@70006200 { +- status = "okay"; +- }; +- +- /* Apalis UART4 */ +- serial@70006300 { +- status = "okay"; +- }; +- +- pwm@7000a000 { +- status = "okay"; +- }; +- +- /* +- * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier +- * board) +- */ +- i2c@7000c000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- pcie-switch@58 { +- compatible = "plx,pex8605"; +- reg = <0x58>; +- }; +- +- /* M41T0M6 real time clock on carrier board */ +- rtc@68 { +- compatible = "st,m41t0"; +- reg = <0x68>; +- }; +- }; +- +- /* GEN2_I2C: unused */ +- +- /* +- * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on +- * carrier board) +- */ +- i2c@7000c500 { +- status = "okay"; +- clock-frequency = <400000>; +- }; +- +- /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ +- i2c@7000c700 { +- status = "okay"; +- }; +- +- /* SPI1: Apalis SPI1 */ +- spi@7000d400 { +- status = "okay"; +- spi-max-frequency = <25000000>; +- }; +- +- /* SPI5: Apalis SPI2 */ +- spi@7000dc00 { +- status = "okay"; +- spi-max-frequency = <25000000>; +- }; +- +- /* Apalis SD1 */ +- mmc@78000000 { +- status = "okay"; +- bus-width = <4>; +- /* SD1_CD# */ +- cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>; +- no-1-8-v; +- }; +- +- /* Apalis MMC1 */ +- mmc@78000400 { +- status = "okay"; +- bus-width = <8>; +- /* MMC1_CD# */ +- cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; +- no-1-8-v; +- }; +- +- /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ +- usb@7d000000 { +- status = "okay"; +- dr_mode = "otg"; +- }; +- +- usb-phy@7d000000 { +- status = "okay"; +- vbus-supply = <®_usbo1_vbus>; +- }; +- +- /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ +- usb@7d004000 { +- status = "okay"; +- }; +- +- usb-phy@7d004000 { +- status = "okay"; +- vbus-supply = <®_usbh_vbus>; +- }; +- +- /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ +- usb@7d008000 { +- status = "okay"; +- }; +- +- usb-phy@7d008000 { +- status = "okay"; +- vbus-supply = <®_usbh_vbus>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- brightness-levels = <255 231 223 207 191 159 127 0>; +- default-brightness-level = <6>; +- /* BKL1_ON */ +- enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; +- power-supply = <®_3v3>; +- pwms = <&pwm 0 5000000>; /* BKL1_PWM */ +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- wakeup { +- label = "WAKE1_MICO"; +- gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- panel: panel { +- /* +- * edt,et057090dhu: EDT 5.7" LCD TFT +- * edt,et070080dh6: EDT 7.0" LCD TFT +- */ +- compatible = "edt,et057090dhu"; +- backlight = <&backlight>; +- power-supply = <®_3v3>; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3.3V_SW"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_5v0: regulator-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "5V_SW"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- /* USBO1_EN */ +- reg_usbo1_vbus: regulator-usbo1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_USBO1"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_5v0>; +- }; +- +- /* USBH_EN */ +- reg_usbh_vbus: regulator-usbh-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_5v0>; +- }; +-}; +- +-&gpio { +- /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ +- pex-perst-n { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "PEX_PERST_N"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-apalis-v1.1-eval.dts b/scripts/dtc/include-prefixes/arm/tegra30-apalis-v1.1-eval.dts +deleted file mode 100644 +index 86e138e8c7f0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-apalis-v1.1-eval.dts ++++ /dev/null +@@ -1,266 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-/dts-v1/; +- +-#include +-#include "tegra30-apalis-v1.1.dtsi" +- +-/ { +- model = "Toradex Apalis T30 on Apalis Evaluation Board"; +- compatible = "toradex,apalis_t30-v1.1-eval", "toradex,apalis_t30-eval", +- "toradex,apalis_t30-v1.1", "toradex,apalis_t30", +- "nvidia,tegra30"; +- +- aliases { +- rtc0 = "/i2c@7000c000/rtc@68"; +- rtc1 = "/i2c@7000d000/pmic@2d"; +- rtc2 = "/rtc@7000e000"; +- serial0 = &uarta; +- serial1 = &uartb; +- serial2 = &uartc; +- serial3 = &uartd; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- pcie@3000 { +- pci@1,0 { +- status = "okay"; +- }; +- +- pci@2,0 { +- status = "okay"; +- }; +- }; +- +- host1x@50000000 { +- dc@54200000 { +- rgb { +- status = "okay"; +- nvidia,panel = <&panel>; +- }; +- }; +- +- hdmi@54280000 { +- status = "okay"; +- hdmi-supply = <®_5v0>; +- }; +- }; +- +- /* Apalis UART1 */ +- serial@70006000 { +- status = "okay"; +- }; +- +- /* Apalis UART2 */ +- serial@70006040 { +- status = "okay"; +- }; +- +- /* Apalis UART3 */ +- serial@70006200 { +- status = "okay"; +- }; +- +- /* Apalis UART4 */ +- serial@70006300 { +- status = "okay"; +- }; +- +- pwm@7000a000 { +- status = "okay"; +- }; +- +- /* +- * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier +- * board) +- */ +- i2c@7000c000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- pcie-switch@58 { +- compatible = "plx,pex8605"; +- reg = <0x58>; +- }; +- +- /* M41T0M6 real time clock on carrier board */ +- rtc@68 { +- compatible = "st,m41t0"; +- reg = <0x68>; +- }; +- }; +- +- /* GEN2_I2C: unused */ +- +- /* +- * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on +- * carrier board) +- */ +- i2c@7000c500 { +- status = "okay"; +- clock-frequency = <400000>; +- }; +- +- /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ +- i2c@7000c700 { +- status = "okay"; +- }; +- +- /* SPI1: Apalis SPI1 */ +- spi@7000d400 { +- status = "okay"; +- spi-max-frequency = <25000000>; +- }; +- +- /* SPI5: Apalis SPI2 */ +- spi@7000dc00 { +- status = "okay"; +- spi-max-frequency = <25000000>; +- }; +- +- /* Apalis SD1 */ +- mmc@78000000 { +- status = "okay"; +- bus-width = <4>; +- /* SD1_CD# */ +- cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>; +- no-1-8-v; +- }; +- +- /* Apalis MMC1 */ +- mmc@78000400 { +- status = "okay"; +- bus-width = <8>; +- /* MMC1_CD# */ +- cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; +- vqmmc-supply = <®_vddio_sdmmc3>; +- }; +- +- /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ +- usb@7d000000 { +- status = "okay"; +- dr_mode = "otg"; +- }; +- +- usb-phy@7d000000 { +- status = "okay"; +- vbus-supply = <®_usbo1_vbus>; +- }; +- +- /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ +- usb@7d004000 { +- status = "okay"; +- }; +- +- usb-phy@7d004000 { +- status = "okay"; +- vbus-supply = <®_usbh_vbus>; +- }; +- +- /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ +- usb@7d008000 { +- status = "okay"; +- }; +- +- usb-phy@7d008000 { +- status = "okay"; +- vbus-supply = <®_usbh_vbus>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- brightness-levels = <255 231 223 207 191 159 127 0>; +- default-brightness-level = <6>; +- /* BKL1_ON */ +- enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; +- power-supply = <®_3v3>; +- pwms = <&pwm 0 5000000>; /* BKL1_PWM */ +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- wakeup { +- label = "WAKE1_MICO"; +- gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- panel: panel { +- /* +- * edt,et057090dhu: EDT 5.7" LCD TFT +- * edt,et070080dh6: EDT 7.0" LCD TFT +- */ +- compatible = "edt,et057090dhu"; +- backlight = <&backlight>; +- power-supply = <®_3v3>; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3.3V_SW"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_5v0: regulator-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "5V_SW"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- /* USBO1_EN */ +- reg_usbo1_vbus: regulator-usbo1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_USBO1"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_5v0>; +- }; +- +- /* USBH_EN */ +- reg_usbh_vbus: regulator-usbh-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_5v0>; +- }; +- +- /* +- * 1.8 volt resp. 3.3 volt VDDIO_SDMMC3 depending on +- * EN_+3.3_SDMMC3 GPIO +- */ +- reg_vddio_sdmmc3: regulator-vddio-sdmmc3 { +- compatible = "regulator-gpio"; +- regulator-name = "VDDIO_SDMMC3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-type = "voltage"; +- gpios = <&gpio TEGRA_GPIO(J, 5) GPIO_ACTIVE_HIGH>; +- states = <1800000 0x0>, +- <3300000 0x1>; +- startup-delay-us = <100000>; +- vin-supply = <&vddio_sdmmc_1v8_reg>; +- }; +-}; +- +-&gpio { +- /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ +- pex-perst-n { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "PEX_PERST_N"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-apalis-v1.1.dtsi b/scripts/dtc/include-prefixes/arm/tegra30-apalis-v1.1.dtsi +deleted file mode 100644 +index 6a3a72f81c44..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-apalis-v1.1.dtsi ++++ /dev/null +@@ -1,1202 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-#include "tegra30.dtsi" +- +-/* +- * Toradex Apalis T30 Module Device Tree +- * Compatible for Revisions 1GB: V1.1A, V1.1B; 1GB IT: V1.1A, V1.1B; +- * 2GB: V1.1A, V1.1B +- */ +-/ { +- memory@80000000 { +- reg = <0x80000000 0x40000000>; +- }; +- +- pcie@3000 { +- status = "okay"; +- avdd-pexa-supply = <&vdd2_reg>; +- avdd-pexb-supply = <&vdd2_reg>; +- avdd-pex-pll-supply = <&vdd2_reg>; +- avdd-plle-supply = <&ldo6_reg>; +- hvdd-pex-supply = <®_module_3v3>; +- vddio-pex-ctl-supply = <®_module_3v3>; +- vdd-pexa-supply = <&vdd2_reg>; +- vdd-pexb-supply = <&vdd2_reg>; +- +- /* Apalis type specific */ +- pci@1,0 { +- nvidia,num-lanes = <4>; +- }; +- +- /* Apalis PCIe */ +- pci@2,0 { +- nvidia,num-lanes = <1>; +- }; +- +- /* I210/I211 Gigabit Ethernet Controller (on-module) */ +- pci@3,0 { +- status = "okay"; +- nvidia,num-lanes = <1>; +- +- ethernet@0,0 { +- reg = <0 0 0 0 0>; +- local-mac-address = [00 00 00 00 00 00]; +- }; +- }; +- }; +- +- host1x@50000000 { +- hdmi@54280000 { +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = +- <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; +- pll-supply = <®_1v8_avdd_hdmi_pll>; +- vdd-supply = <®_3v3_avdd_hdmi>; +- }; +- }; +- +- pinmux@70000868 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- /* Analogue Audio (On-module) */ +- clk1-out-pw4 { +- nvidia,pins = "clk1_out_pw4"; +- nvidia,function = "extperiph1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3-fs-pp0 { +- nvidia,pins = "dap3_fs_pp0", +- "dap3_sclk_pp3", +- "dap3_din_pp1", +- "dap3_dout_pp2"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis BKL1_ON */ +- pv2 { +- nvidia,pins = "pv2"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis BKL1_PWM */ +- uart3-rts-n-pc0 { +- nvidia,pins = "uart3_rts_n_pc0"; +- nvidia,function = "pwm0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ +- uart3-cts-n-pa1 { +- nvidia,pins = "uart3_cts_n_pa1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis CAN1 on SPI6 */ +- spi2-cs0-n-px3 { +- nvidia,pins = "spi2_cs0_n_px3", +- "spi2_miso_px1", +- "spi2_mosi_px0", +- "spi2_sck_px2"; +- nvidia,function = "spi6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- /* CAN_INT1 */ +- spi2-cs1-n-pw2 { +- nvidia,pins = "spi2_cs1_n_pw2"; +- nvidia,function = "spi3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis CAN2 on SPI4 */ +- gmi-a16-pj7 { +- nvidia,pins = "gmi_a16_pj7", +- "gmi_a17_pb0", +- "gmi_a18_pb1", +- "gmi_a19_pk7"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* CAN_INT2 */ +- spi2-cs2-n-pw3 { +- nvidia,pins = "spi2_cs2_n_pw3"; +- nvidia,function = "spi3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis Digital Audio */ +- clk1-req-pee2 { +- nvidia,pins = "clk1_req_pee2"; +- nvidia,function = "hda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- clk2-out-pw5 { +- nvidia,pins = "clk2_out_pw5"; +- nvidia,function = "extperiph2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1-fs-pn0 { +- nvidia,pins = "dap1_fs_pn0", +- "dap1_din_pn1", +- "dap1_dout_pn2", +- "dap1_sclk_pn3"; +- nvidia,function = "hda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis GPIO */ +- kb-col0-pq0 { +- nvidia,pins = "kb_col0_pq0", +- "kb_col1_pq1", +- "kb_row10_ps2", +- "kb_row11_ps3", +- "kb_row12_ps4", +- "kb_row13_ps5", +- "kb_row14_ps6", +- "kb_row15_ps7"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* Multiplexed and therefore disabled */ +- owr { +- nvidia,pins = "owr"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis HDMI1 */ +- hdmi-cec-pee3 { +- nvidia,pins = "hdmi_cec_pee3"; +- nvidia,function = "cec"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- hdmi-int-pn7 { +- nvidia,pins = "hdmi_int_pn7"; +- nvidia,function = "hdmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis I2C1 */ +- gen1-i2c-scl-pc4 { +- nvidia,pins = "gen1_i2c_scl_pc4", +- "gen1_i2c_sda_pc5"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* Apalis I2C2 (DDC) */ +- ddc-scl-pv4 { +- nvidia,pins = "ddc_scl_pv4", +- "ddc_sda_pv5"; +- nvidia,function = "i2c4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis I2C3 (CAM) */ +- cam-i2c-scl-pbb1 { +- nvidia,pins = "cam_i2c_scl_pbb1", +- "cam_i2c_sda_pbb2"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* Apalis LCD1 */ +- lcd-d0-pe0 { +- nvidia,pins = "lcd_d0_pe0", +- "lcd_d1_pe1", +- "lcd_d2_pe2", +- "lcd_d3_pe3", +- "lcd_d4_pe4", +- "lcd_d5_pe5", +- "lcd_d6_pe6", +- "lcd_d7_pe7", +- "lcd_d8_pf0", +- "lcd_d9_pf1", +- "lcd_d10_pf2", +- "lcd_d11_pf3", +- "lcd_d12_pf4", +- "lcd_d13_pf5", +- "lcd_d14_pf6", +- "lcd_d15_pf7", +- "lcd_d16_pm0", +- "lcd_d17_pm1", +- "lcd_d18_pm2", +- "lcd_d19_pm3", +- "lcd_d20_pm4", +- "lcd_d21_pm5", +- "lcd_d22_pm6", +- "lcd_d23_pm7", +- "lcd_de_pj1", +- "lcd_hsync_pj3", +- "lcd_pclk_pb3", +- "lcd_vsync_pj4"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis MMC1 */ +- sdmmc3-clk-pa6 { +- nvidia,pins = "sdmmc3_clk_pa6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- sdmmc3-dat0-pb7 { +- nvidia,pins = "sdmmc3_cmd_pa7", +- "sdmmc3_dat0_pb7", +- "sdmmc3_dat1_pb6", +- "sdmmc3_dat2_pb5", +- "sdmmc3_dat3_pb4", +- "sdmmc3_dat4_pd1", +- "sdmmc3_dat5_pd0", +- "sdmmc3_dat6_pd3", +- "sdmmc3_dat7_pd4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- /* Apalis MMC1_CD# */ +- pv3 { +- nvidia,pins = "pv3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis Parallel Camera */ +- cam-mclk-pcc0 { +- nvidia,pins = "cam_mclk_pcc0"; +- nvidia,function = "vi_alt3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi-vsync-pd6 { +- nvidia,pins = "vi_d0_pt4", +- "vi_d1_pd5", +- "vi_d2_pl0", +- "vi_d3_pl1", +- "vi_d4_pl2", +- "vi_d5_pl3", +- "vi_d6_pl4", +- "vi_d7_pl5", +- "vi_d8_pl6", +- "vi_d9_pl7", +- "vi_d10_pt2", +- "vi_d11_pt3", +- "vi_hsync_pd7", +- "vi_pclk_pt0", +- "vi_vsync_pd6"; +- nvidia,function = "vi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* Multiplexed and therefore disabled */ +- kb-col2-pq2 { +- nvidia,pins = "kb_col2_pq2", +- "kb_col3_pq3", +- "kb_col4_pq4", +- "kb_row4_pr4"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row0-pr0 { +- nvidia,pins = "kb_row0_pr0", +- "kb_row1_pr1", +- "kb_row2_pr2", +- "kb_row3_pr3"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row5-pr5 { +- nvidia,pins = "kb_row5_pr5", +- "kb_row6_pr6", +- "kb_row7_pr7"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* +- * VI level-shifter direction +- * (pull-down => default direction input) +- */ +- vi-mclk-pt1 { +- nvidia,pins = "vi_mclk_pt1"; +- nvidia,function = "vi_alt3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis PWM1 */ +- pu6 { +- nvidia,pins = "pu6"; +- nvidia,function = "pwm3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis PWM2 */ +- pu5 { +- nvidia,pins = "pu5"; +- nvidia,function = "pwm2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis PWM3 */ +- pu4 { +- nvidia,pins = "pu4"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis PWM4 */ +- pu3 { +- nvidia,pins = "pu3"; +- nvidia,function = "pwm0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis RESET_MOCI# */ +- gmi-rst-n-pi4 { +- nvidia,pins = "gmi_rst_n_pi4"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis SATA1_ACT# */ +- pex-l0-prsnt-n-pdd0 { +- nvidia,pins = "pex_l0_prsnt_n_pdd0"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis SD1 */ +- sdmmc1-clk-pz0 { +- nvidia,pins = "sdmmc1_clk_pz0"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- sdmmc1-cmd-pz1 { +- nvidia,pins = "sdmmc1_cmd_pz1", +- "sdmmc1_dat0_py7", +- "sdmmc1_dat1_py6", +- "sdmmc1_dat2_py5", +- "sdmmc1_dat3_py4"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- /* Apalis SD1_CD# */ +- clk2-req-pcc5 { +- nvidia,pins = "clk2_req_pcc5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis SPDIF1 */ +- spdif-out-pk5 { +- nvidia,pins = "spdif_out_pk5", +- "spdif_in_pk6"; +- nvidia,function = "spdif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis SPI1 */ +- spi1-sck-px5 { +- nvidia,pins = "spi1_sck_px5", +- "spi1_mosi_px4", +- "spi1_miso_px7", +- "spi1_cs0_n_px6"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis SPI2 */ +- lcd-sck-pz4 { +- nvidia,pins = "lcd_sck_pz4", +- "lcd_sdout_pn5", +- "lcd_sdin_pz2", +- "lcd_cs0_n_pn4"; +- nvidia,function = "spi5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* +- * Apalis TS (Low-speed type specific) +- * pins may be used as GPIOs +- */ +- kb-col5-pq5 { +- nvidia,pins = "kb_col5_pq5"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-col6-pq6 { +- nvidia,pins = "kb_col6_pq6", +- "kb_col7_pq7", +- "kb_row8_ps0", +- "kb_row9_ps1"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis UART1 */ +- ulpi-data0 { +- nvidia,pins = "ulpi_data0_po1", +- "ulpi_data1_po2", +- "ulpi_data2_po3", +- "ulpi_data3_po4", +- "ulpi_data4_po5", +- "ulpi_data5_po6", +- "ulpi_data6_po7", +- "ulpi_data7_po0"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis UART2 */ +- ulpi-clk-py0 { +- nvidia,pins = "ulpi_clk_py0", +- "ulpi_dir_py1", +- "ulpi_nxt_py2", +- "ulpi_stp_py3"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis UART3 */ +- uart2-rxd-pc3 { +- nvidia,pins = "uart2_rxd_pc3", +- "uart2_txd_pc2"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis UART4 */ +- uart3-rxd-pw7 { +- nvidia,pins = "uart3_rxd_pw7", +- "uart3_txd_pw6"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis USBH_EN */ +- pex-l0-rst-n-pdd1 { +- nvidia,pins = "pex_l0_rst_n_pdd1"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis USBH_OC# */ +- pex-l0-clkreq-n-pdd2 { +- nvidia,pins = "pex_l0_clkreq_n_pdd2"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis USBO1_EN */ +- gen2-i2c-scl-pt5 { +- nvidia,pins = "gen2_i2c_scl_pt5"; +- nvidia,function = "rsvd4"; +- nvidia,open-drain = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis USBO1_OC# */ +- gen2-i2c-sda-pt6 { +- nvidia,pins = "gen2_i2c_sda_pt6"; +- nvidia,function = "rsvd4"; +- nvidia,open-drain = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis VGA1 not supported and therefore disabled */ +- crt-hsync-pv6 { +- nvidia,pins = "crt_hsync_pv6", +- "crt_vsync_pv7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis WAKE1_MICO */ +- pv1 { +- nvidia,pins = "pv1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* eMMC (On-module) */ +- sdmmc4-clk-pcc4 { +- nvidia,pins = "sdmmc4_clk_pcc4", +- "sdmmc4_cmd_pt7", +- "sdmmc4_rst_n_pcc3"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-dat0-paa0 { +- nvidia,pins = "sdmmc4_dat0_paa0", +- "sdmmc4_dat1_paa1", +- "sdmmc4_dat2_paa2", +- "sdmmc4_dat3_paa3", +- "sdmmc4_dat4_paa4", +- "sdmmc4_dat5_paa5", +- "sdmmc4_dat6_paa6", +- "sdmmc4_dat7_paa7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* EN_+3.3_SDMMC3 */ +- uart2-cts-n-pj5 { +- nvidia,pins = "uart2_cts_n_pj5"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */ +- pex-l2-prsnt-n-pdd7 { +- nvidia,pins = "pex_l2_prsnt_n_pdd7", +- "pex_l2_rst_n_pcc6"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */ +- pex-wake-n-pdd3 { +- nvidia,pins = "pex_wake_n_pdd3", +- "pex_l2_clkreq_n_pcc7"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* LAN i210/i211 SMB_ALERT_N (On-module) */ +- sys-clk-req-pz5 { +- nvidia,pins = "sys_clk_req_pz5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* LVDS Transceiver Configuration */ +- pbb0 { +- nvidia,pins = "pbb0", +- "pbb7", +- "pcc1", +- "pcc2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb3 { +- nvidia,pins = "pbb3", +- "pbb4", +- "pbb5", +- "pbb6"; +- nvidia,function = "displayb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Not connected and therefore disabled */ +- clk-32k-out-pa0 { +- nvidia,pins = "clk3_out_pee0", +- "clk3_req_pee1", +- "clk_32k_out_pa0", +- "dap4_din_pp5", +- "dap4_dout_pp6", +- "dap4_fs_pp4", +- "dap4_sclk_pp7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2-fs-pa2 { +- nvidia,pins = "dap2_fs_pa2", +- "dap2_sclk_pa3", +- "dap2_din_pa4", +- "dap2_dout_pa5", +- "lcd_dc0_pn6", +- "lcd_m1_pw1", +- "lcd_pwr1_pc1", +- "pex_l1_clkreq_n_pdd6", +- "pex_l1_prsnt_n_pdd4", +- "pex_l1_rst_n_pdd5"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi-ad0-pg0 { +- nvidia,pins = "gmi_ad0_pg0", +- "gmi_ad2_pg2", +- "gmi_ad3_pg3", +- "gmi_ad4_pg4", +- "gmi_ad5_pg5", +- "gmi_ad6_pg6", +- "gmi_ad7_pg7", +- "gmi_ad8_ph0", +- "gmi_ad9_ph1", +- "gmi_ad10_ph2", +- "gmi_ad11_ph3", +- "gmi_ad12_ph4", +- "gmi_ad13_ph5", +- "gmi_ad14_ph6", +- "gmi_ad15_ph7", +- "gmi_adv_n_pk0", +- "gmi_clk_pk1", +- "gmi_cs4_n_pk2", +- "gmi_cs2_n_pk3", +- "gmi_dqs_pi2", +- "gmi_iordy_pi5", +- "gmi_oe_n_pi1", +- "gmi_wait_pi7", +- "gmi_wr_n_pi0", +- "lcd_cs1_n_pw0", +- "pu0", +- "pu1", +- "pu2"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi-cs0-n-pj0 { +- nvidia,pins = "gmi_cs0_n_pj0", +- "gmi_cs1_n_pj2", +- "gmi_cs3_n_pk4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi-cs6-n-pi3 { +- nvidia,pins = "gmi_cs6_n_pi3"; +- nvidia,function = "sata"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi-cs7-n-pi6 { +- nvidia,pins = "gmi_cs7_n_pi6"; +- nvidia,function = "gmi_alt"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd-pwr0-pb2 { +- nvidia,pins = "lcd_pwr0_pb2", +- "lcd_pwr2_pc6", +- "lcd_wr_n_pz3"; +- nvidia,function = "hdcp"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2-rts-n-pj6 { +- nvidia,pins = "uart2_rts_n_pj6"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Power I2C (On-module) */ +- pwr-i2c-scl-pz6 { +- nvidia,pins = "pwr_i2c_scl_pz6", +- "pwr_i2c_sda_pz7"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* +- * THERMD_ALERT#, unlatched I2C address pin of LM95245 +- * temperature sensor therefore requires disabling for +- * now +- */ +- lcd-dc1-pd2 { +- nvidia,pins = "lcd_dc1_pd2"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* TOUCH_PEN_INT# (On-module) */ +- pv0 { +- nvidia,pins = "pv0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- }; +- }; +- +- serial@70006040 { +- compatible = "nvidia,tegra30-hsuart"; +- }; +- +- serial@70006200 { +- compatible = "nvidia,tegra30-hsuart"; +- }; +- +- serial@70006300 { +- compatible = "nvidia,tegra30-hsuart"; +- }; +- +- hdmi_ddc: i2c@7000c700 { +- clock-frequency = <10000>; +- }; +- +- /* +- * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and +- * touch screen controller +- */ +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <100000>; +- +- /* SGTL5000 audio codec */ +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- VDDA-supply = <®_module_3v3_audio>; +- VDDD-supply = <®_1v8_vio>; +- VDDIO-supply = <®_module_3v3>; +- clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; +- }; +- +- pmic: pmic@2d { +- compatible = "ti,tps65911"; +- reg = <0x2d>; +- +- interrupts = ; +- #interrupt-cells = <2>; +- interrupt-controller; +- +- ti,system-power-controller; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- vcc1-supply = <®_module_3v3>; +- vcc2-supply = <®_module_3v3>; +- vcc3-supply = <®_1v8_vio>; +- vcc4-supply = <®_module_3v3>; +- vcc5-supply = <®_module_3v3>; +- vcc6-supply = <®_1v8_vio>; +- vcc7-supply = <®_5v0_charge_pump>; +- vccio-supply = <®_module_3v3>; +- +- regulators { +- vdd1_reg: vdd1 { +- regulator-name = "+V1.35_VDDIO_DDR"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- }; +- +- vdd2_reg: vdd2 { +- regulator-name = "+V1.05"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- vddctrl_reg: vddctrl { +- regulator-name = "+V1.0_VDD_CPU"; +- regulator-min-microvolt = <1150000>; +- regulator-max-microvolt = <1150000>; +- regulator-always-on; +- }; +- +- reg_1v8_vio: vio { +- regulator-name = "+V1.8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- /* +- * 1.8 volt +VDDIO_SDMMC3 in case EN_+3.3_SDMMC3 +- * is off +- */ +- vddio_sdmmc_1v8_reg: ldo1 { +- regulator-name = "+VDDIO_SDMMC3_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- /* +- * EN_+V3.3 switching via FET: +- * +V3.3_AUDIO_AVDD_S, +V3.3 +- * see also +V3.3 fixed supply +- */ +- ldo2_reg: ldo2 { +- regulator-name = "EN_+V3.3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo3_reg: ldo3 { +- regulator-name = "+V1.2_CSI"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo4_reg: ldo4 { +- regulator-name = "+V1.2_VDD_RTC"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- /* +- * +V2.8_AVDD_VDAC: +- * only required for (unsupported) analog RGB +- */ +- ldo5_reg: ldo5 { +- regulator-name = "+V2.8_AVDD_VDAC"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- /* +- * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V +- * but LDO6 can't set voltage in 50mV +- * granularity +- */ +- ldo6_reg: ldo6 { +- regulator-name = "+V1.05_AVDD_PLLE"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- ldo7_reg: ldo7 { +- regulator-name = "+V1.2_AVDD_PLL"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo8_reg: ldo8 { +- regulator-name = "+V1.0_VDD_DDR_HS"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- }; +- }; +- +- /* STMPE811 touch screen controller */ +- touchscreen@41 { +- compatible = "st,stmpe811"; +- reg = <0x41>; +- irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- id = <0>; +- blocks = <0x5>; +- irq-trigger = <0x1>; +- /* 3.25 MHz ADC clock speed */ +- st,adc-freq = <1>; +- /* 12-bit ADC */ +- st,mod-12b = <1>; +- /* internal ADC reference */ +- st,ref-sel = <0>; +- /* ADC converstion time: 80 clocks */ +- st,sample-time = <4>; +- +- stmpe_touchscreen { +- compatible = "st,stmpe-ts"; +- /* 8 sample average control */ +- st,ave-ctrl = <3>; +- /* 7 length fractional part in z */ +- st,fraction-z = <7>; +- /* +- * 50 mA typical 80 mA max touchscreen drivers +- * current limit value +- */ +- st,i-drive = <1>; +- /* 1 ms panel driver settling time */ +- st,settling = <3>; +- /* 5 ms touch detect interrupt delay */ +- st,touch-det-delay = <5>; +- }; +- +- stmpe_adc { +- compatible = "st,stmpe-adc"; +- /* forbid to use ADC channels 3-0 (touch) */ +- st,norequest-mask = <0x0F>; +- }; +- }; +- +- /* +- * LM95245 temperature sensor +- * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN +- */ +- temp-sensor@4c { +- compatible = "national,lm95245"; +- reg = <0x4c>; +- }; +- +- /* SW: +V1.2_VDD_CORE */ +- regulator@60 { +- compatible = "ti,tps62362"; +- reg = <0x60>; +- +- regulator-name = "tps62362-vout"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- regulator-always-on; +- ti,vsel0-state-low; +- /* VSEL1: EN_CORE_DVFS_N low for DVFS */ +- ti,vsel1-state-low; +- }; +- }; +- +- /* SPI4: CAN2 */ +- spi@7000da00 { +- status = "okay"; +- spi-max-frequency = <10000000>; +- +- can@1 { +- compatible = "microchip,mcp2515"; +- reg = <1>; +- clocks = <&clk16m>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- spi-max-frequency = <10000000>; +- }; +- }; +- +- /* SPI6: CAN1 */ +- spi@7000de00 { +- status = "okay"; +- spi-max-frequency = <10000000>; +- +- can@0 { +- compatible = "microchip,mcp2515"; +- reg = <0>; +- clocks = <&clk16m>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- spi-max-frequency = <10000000>; +- }; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <5000>; +- nvidia,cpu-pwr-off-time = <5000>; +- nvidia,core-pwr-good-time = <3845 3845>; +- nvidia,core-pwr-off-time = <0>; +- nvidia,core-power-req-active-high; +- nvidia,sys-clock-req-active-high; +- +- /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ +- i2c-thermtrip { +- nvidia,i2c-controller-id = <4>; +- nvidia,bus-addr = <0x2d>; +- nvidia,reg-addr = <0x3f>; +- nvidia,reg-data = <0x1>; +- }; +- }; +- +- hda@70030000 { +- status = "okay"; +- }; +- +- ahub@70080000 { +- i2s@70080500 { +- status = "okay"; +- }; +- }; +- +- /* eMMC */ +- mmc@78000600 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- vmmc-supply = <®_module_3v3>; /* VCC */ +- vqmmc-supply = <®_1v8_vio>; /* VCCQ */ +- mmc-ddr-1_8v; +- }; +- +- clk32k_in: xtal1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- clk16m: osc4 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <16000000>; +- }; +- +- reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { +- compatible = "regulator-fixed"; +- regulator-name = "+V1.8_AVDD_HDMI_PLL"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- enable-active-high; +- gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; +- vin-supply = <®_1v8_vio>; +- }; +- +- reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3_AVDD_HDMI"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; +- vin-supply = <®_module_3v3>; +- }; +- +- reg_5v0_charge_pump: regulator-5v0-charge-pump { +- compatible = "regulator-fixed"; +- regulator-name = "+V5.0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_module_3v3: regulator-module-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_module_3v3_audio: regulator-module-3v3-audio { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3_AUDIO_AVDD_S"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- sound { +- compatible = "toradex,tegra-audio-sgtl5000-apalis_t30", +- "nvidia,tegra-audio-sgtl5000"; +- nvidia,model = "Toradex Apalis T30"; +- nvidia,audio-routing = +- "Headphone Jack", "HP_OUT", +- "LINE_IN", "Line In Jack", +- "MIC_IN", "Mic Jack"; +- nvidia,i2s-controller = <&tegra_i2s2>; +- nvidia,audio-codec = <&sgtl5000>; +- clocks = <&tegra_car TEGRA30_CLK_PLL_A>, +- <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- +- assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- +- assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA30_CLK_EXTERN1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-apalis.dtsi b/scripts/dtc/include-prefixes/arm/tegra30-apalis.dtsi +deleted file mode 100644 +index b2ac51fb15b1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-apalis.dtsi ++++ /dev/null +@@ -1,1185 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "tegra30.dtsi" +- +-/* +- * Toradex Apalis T30 Module Device Tree +- * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C, V1.0E +- */ +-/ { +- memory@80000000 { +- reg = <0x80000000 0x40000000>; +- }; +- +- pcie@3000 { +- status = "okay"; +- avdd-pexa-supply = <&vdd2_reg>; +- avdd-pexb-supply = <&vdd2_reg>; +- avdd-pex-pll-supply = <&vdd2_reg>; +- avdd-plle-supply = <&ldo6_reg>; +- hvdd-pex-supply = <®_module_3v3>; +- vddio-pex-ctl-supply = <®_module_3v3>; +- vdd-pexa-supply = <&vdd2_reg>; +- vdd-pexb-supply = <&vdd2_reg>; +- +- /* Apalis type specific */ +- pci@1,0 { +- nvidia,num-lanes = <4>; +- }; +- +- /* Apalis PCIe */ +- pci@2,0 { +- nvidia,num-lanes = <1>; +- }; +- +- /* I210/I211 Gigabit Ethernet Controller (on-module) */ +- pci@3,0 { +- status = "okay"; +- nvidia,num-lanes = <1>; +- +- ethernet@0,0 { +- reg = <0 0 0 0 0>; +- local-mac-address = [00 00 00 00 00 00]; +- }; +- }; +- }; +- +- host1x@50000000 { +- hdmi@54280000 { +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = +- <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; +- pll-supply = <®_1v8_avdd_hdmi_pll>; +- vdd-supply = <®_3v3_avdd_hdmi>; +- }; +- }; +- +- pinmux@70000868 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- /* Analogue Audio (On-module) */ +- clk1-out-pw4 { +- nvidia,pins = "clk1_out_pw4"; +- nvidia,function = "extperiph1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3-fs-pp0 { +- nvidia,pins = "dap3_fs_pp0", +- "dap3_sclk_pp3", +- "dap3_din_pp1", +- "dap3_dout_pp2"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis BKL1_ON */ +- pv2 { +- nvidia,pins = "pv2"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis BKL1_PWM */ +- uart3-rts-n-pc0 { +- nvidia,pins = "uart3_rts_n_pc0"; +- nvidia,function = "pwm0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ +- uart3-cts-n-pa1 { +- nvidia,pins = "uart3_cts_n_pa1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis CAN1 on SPI6 */ +- spi2-cs0-n-px3 { +- nvidia,pins = "spi2_cs0_n_px3", +- "spi2_miso_px1", +- "spi2_mosi_px0", +- "spi2_sck_px2"; +- nvidia,function = "spi6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- /* CAN_INT1 */ +- spi2-cs1-n-pw2 { +- nvidia,pins = "spi2_cs1_n_pw2"; +- nvidia,function = "spi3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis CAN2 on SPI4 */ +- gmi-a16-pj7 { +- nvidia,pins = "gmi_a16_pj7", +- "gmi_a17_pb0", +- "gmi_a18_pb1", +- "gmi_a19_pk7"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* CAN_INT2 */ +- spi2-cs2-n-pw3 { +- nvidia,pins = "spi2_cs2_n_pw3"; +- nvidia,function = "spi3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis Digital Audio */ +- clk1-req-pee2 { +- nvidia,pins = "clk1_req_pee2"; +- nvidia,function = "hda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- clk2-out-pw5 { +- nvidia,pins = "clk2_out_pw5"; +- nvidia,function = "extperiph2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1-fs-pn0 { +- nvidia,pins = "dap1_fs_pn0", +- "dap1_din_pn1", +- "dap1_dout_pn2", +- "dap1_sclk_pn3"; +- nvidia,function = "hda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis GPIO */ +- kb-col0-pq0 { +- nvidia,pins = "kb_col0_pq0", +- "kb_col1_pq1", +- "kb_row10_ps2", +- "kb_row11_ps3", +- "kb_row12_ps4", +- "kb_row13_ps5", +- "kb_row14_ps6", +- "kb_row15_ps7"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* Multiplexed and therefore disabled */ +- owr { +- nvidia,pins = "owr"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis HDMI1 */ +- hdmi-cec-pee3 { +- nvidia,pins = "hdmi_cec_pee3"; +- nvidia,function = "cec"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- hdmi-int-pn7 { +- nvidia,pins = "hdmi_int_pn7"; +- nvidia,function = "hdmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis I2C1 */ +- gen1-i2c-scl-pc4 { +- nvidia,pins = "gen1_i2c_scl_pc4", +- "gen1_i2c_sda_pc5"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* Apalis I2C2 (DDC) */ +- ddc-scl-pv4 { +- nvidia,pins = "ddc_scl_pv4", +- "ddc_sda_pv5"; +- nvidia,function = "i2c4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis I2C3 (CAM) */ +- cam-i2c-scl-pbb1 { +- nvidia,pins = "cam_i2c_scl_pbb1", +- "cam_i2c_sda_pbb2"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* Apalis LCD1 */ +- lcd-d0-pe0 { +- nvidia,pins = "lcd_d0_pe0", +- "lcd_d1_pe1", +- "lcd_d2_pe2", +- "lcd_d3_pe3", +- "lcd_d4_pe4", +- "lcd_d5_pe5", +- "lcd_d6_pe6", +- "lcd_d7_pe7", +- "lcd_d8_pf0", +- "lcd_d9_pf1", +- "lcd_d10_pf2", +- "lcd_d11_pf3", +- "lcd_d12_pf4", +- "lcd_d13_pf5", +- "lcd_d14_pf6", +- "lcd_d15_pf7", +- "lcd_d16_pm0", +- "lcd_d17_pm1", +- "lcd_d18_pm2", +- "lcd_d19_pm3", +- "lcd_d20_pm4", +- "lcd_d21_pm5", +- "lcd_d22_pm6", +- "lcd_d23_pm7", +- "lcd_de_pj1", +- "lcd_hsync_pj3", +- "lcd_pclk_pb3", +- "lcd_vsync_pj4"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis MMC1 */ +- sdmmc3-clk-pa6 { +- nvidia,pins = "sdmmc3_clk_pa6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- sdmmc3-dat0-pb7 { +- nvidia,pins = "sdmmc3_cmd_pa7", +- "sdmmc3_dat0_pb7", +- "sdmmc3_dat1_pb6", +- "sdmmc3_dat2_pb5", +- "sdmmc3_dat3_pb4", +- "sdmmc3_dat4_pd1", +- "sdmmc3_dat5_pd0", +- "sdmmc3_dat6_pd3", +- "sdmmc3_dat7_pd4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- /* Apalis MMC1_CD# */ +- pv3 { +- nvidia,pins = "pv3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis Parallel Camera */ +- cam-mclk-pcc0 { +- nvidia,pins = "cam_mclk_pcc0"; +- nvidia,function = "vi_alt3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi-vsync-pd6 { +- nvidia,pins = "vi_d0_pt4", +- "vi_d1_pd5", +- "vi_d2_pl0", +- "vi_d3_pl1", +- "vi_d4_pl2", +- "vi_d5_pl3", +- "vi_d6_pl4", +- "vi_d7_pl5", +- "vi_d8_pl6", +- "vi_d9_pl7", +- "vi_d10_pt2", +- "vi_d11_pt3", +- "vi_hsync_pd7", +- "vi_pclk_pt0", +- "vi_vsync_pd6"; +- nvidia,function = "vi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* Multiplexed and therefore disabled */ +- kb-col2-pq2 { +- nvidia,pins = "kb_col2_pq2", +- "kb_col3_pq3", +- "kb_col4_pq4", +- "kb_row4_pr4"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row0-pr0 { +- nvidia,pins = "kb_row0_pr0", +- "kb_row1_pr1", +- "kb_row2_pr2", +- "kb_row3_pr3"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row5-pr5 { +- nvidia,pins = "kb_row5_pr5", +- "kb_row6_pr6", +- "kb_row7_pr7"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* +- * VI level-shifter direction +- * (pull-down => default direction input) +- */ +- vi-mclk-pt1 { +- nvidia,pins = "vi_mclk_pt1"; +- nvidia,function = "vi_alt3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis PWM1 */ +- pu6 { +- nvidia,pins = "pu6"; +- nvidia,function = "pwm3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis PWM2 */ +- pu5 { +- nvidia,pins = "pu5"; +- nvidia,function = "pwm2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis PWM3 */ +- pu4 { +- nvidia,pins = "pu4"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis PWM4 */ +- pu3 { +- nvidia,pins = "pu3"; +- nvidia,function = "pwm0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis RESET_MOCI# */ +- gmi-rst-n-pi4 { +- nvidia,pins = "gmi_rst_n_pi4"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis SATA1_ACT# */ +- pex-l0-prsnt-n-pdd0 { +- nvidia,pins = "pex_l0_prsnt_n_pdd0"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis SD1 */ +- sdmmc1-clk-pz0 { +- nvidia,pins = "sdmmc1_clk_pz0"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- sdmmc1-cmd-pz1 { +- nvidia,pins = "sdmmc1_cmd_pz1", +- "sdmmc1_dat0_py7", +- "sdmmc1_dat1_py6", +- "sdmmc1_dat2_py5", +- "sdmmc1_dat3_py4"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- /* Apalis SD1_CD# */ +- clk2-req-pcc5 { +- nvidia,pins = "clk2_req_pcc5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis SPDIF1 */ +- spdif-out-pk5 { +- nvidia,pins = "spdif_out_pk5", +- "spdif_in_pk6"; +- nvidia,function = "spdif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis SPI1 */ +- spi1-sck-px5 { +- nvidia,pins = "spi1_sck_px5", +- "spi1_mosi_px4", +- "spi1_miso_px7", +- "spi1_cs0_n_px6"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis SPI2 */ +- lcd-sck-pz4 { +- nvidia,pins = "lcd_sck_pz4", +- "lcd_sdout_pn5", +- "lcd_sdin_pz2", +- "lcd_cs0_n_pn4"; +- nvidia,function = "spi5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* +- * Apalis TS (Low-speed type specific) +- * pins may be used as GPIOs +- */ +- kb-col5-pq5 { +- nvidia,pins = "kb_col5_pq5"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-col6-pq6 { +- nvidia,pins = "kb_col6_pq6", +- "kb_col7_pq7", +- "kb_row8_ps0", +- "kb_row9_ps1"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis UART1 */ +- ulpi-data0 { +- nvidia,pins = "ulpi_data0_po1", +- "ulpi_data1_po2", +- "ulpi_data2_po3", +- "ulpi_data3_po4", +- "ulpi_data4_po5", +- "ulpi_data5_po6", +- "ulpi_data6_po7", +- "ulpi_data7_po0"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis UART2 */ +- ulpi-clk-py0 { +- nvidia,pins = "ulpi_clk_py0", +- "ulpi_dir_py1", +- "ulpi_nxt_py2", +- "ulpi_stp_py3"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis UART3 */ +- uart2-rxd-pc3 { +- nvidia,pins = "uart2_rxd_pc3", +- "uart2_txd_pc2"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis UART4 */ +- uart3-rxd-pw7 { +- nvidia,pins = "uart3_rxd_pw7", +- "uart3_txd_pw6"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis USBH_EN */ +- pex-l0-rst-n-pdd1 { +- nvidia,pins = "pex_l0_rst_n_pdd1"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis USBH_OC# */ +- pex-l0-clkreq-n-pdd2 { +- nvidia,pins = "pex_l0_clkreq_n_pdd2"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis USBO1_EN */ +- gen2-i2c-scl-pt5 { +- nvidia,pins = "gen2_i2c_scl_pt5"; +- nvidia,function = "rsvd4"; +- nvidia,open-drain = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Apalis USBO1_OC# */ +- gen2-i2c-sda-pt6 { +- nvidia,pins = "gen2_i2c_sda_pt6"; +- nvidia,function = "rsvd4"; +- nvidia,open-drain = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis VGA1 not supported and therefore disabled */ +- crt-hsync-pv6 { +- nvidia,pins = "crt_hsync_pv6", +- "crt_vsync_pv7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Apalis WAKE1_MICO */ +- pv1 { +- nvidia,pins = "pv1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* eMMC (On-module) */ +- sdmmc4-clk-pcc4 { +- nvidia,pins = "sdmmc4_clk_pcc4", +- "sdmmc4_cmd_pt7", +- "sdmmc4_rst_n_pcc3"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-dat0-paa0 { +- nvidia,pins = "sdmmc4_dat0_paa0", +- "sdmmc4_dat1_paa1", +- "sdmmc4_dat2_paa2", +- "sdmmc4_dat3_paa3", +- "sdmmc4_dat4_paa4", +- "sdmmc4_dat5_paa5", +- "sdmmc4_dat6_paa6", +- "sdmmc4_dat7_paa7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */ +- pex-l2-prsnt-n-pdd7 { +- nvidia,pins = "pex_l2_prsnt_n_pdd7", +- "pex_l2_rst_n_pcc6"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */ +- pex-wake-n-pdd3 { +- nvidia,pins = "pex_wake_n_pdd3", +- "pex_l2_clkreq_n_pcc7"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* LAN i210/i211 SMB_ALERT_N (On-module) */ +- sys-clk-req-pz5 { +- nvidia,pins = "sys_clk_req_pz5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* LVDS Transceiver Configuration */ +- pbb0 { +- nvidia,pins = "pbb0", +- "pbb7", +- "pcc1", +- "pcc2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb3 { +- nvidia,pins = "pbb3", +- "pbb4", +- "pbb5", +- "pbb6"; +- nvidia,function = "displayb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Not connected and therefore disabled */ +- clk-32k-out-pa0 { +- nvidia,pins = "clk3_out_pee0", +- "clk3_req_pee1", +- "clk_32k_out_pa0", +- "dap4_din_pp5", +- "dap4_dout_pp6", +- "dap4_fs_pp4", +- "dap4_sclk_pp7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2-fs-pa2 { +- nvidia,pins = "dap2_fs_pa2", +- "dap2_sclk_pa3", +- "dap2_din_pa4", +- "dap2_dout_pa5", +- "lcd_dc0_pn6", +- "lcd_m1_pw1", +- "lcd_pwr1_pc1", +- "pex_l1_clkreq_n_pdd6", +- "pex_l1_prsnt_n_pdd4", +- "pex_l1_rst_n_pdd5"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi-ad0-pg0 { +- nvidia,pins = "gmi_ad0_pg0", +- "gmi_ad2_pg2", +- "gmi_ad3_pg3", +- "gmi_ad4_pg4", +- "gmi_ad5_pg5", +- "gmi_ad6_pg6", +- "gmi_ad7_pg7", +- "gmi_ad8_ph0", +- "gmi_ad9_ph1", +- "gmi_ad10_ph2", +- "gmi_ad11_ph3", +- "gmi_ad12_ph4", +- "gmi_ad13_ph5", +- "gmi_ad14_ph6", +- "gmi_ad15_ph7", +- "gmi_adv_n_pk0", +- "gmi_clk_pk1", +- "gmi_cs4_n_pk2", +- "gmi_cs2_n_pk3", +- "gmi_dqs_pi2", +- "gmi_iordy_pi5", +- "gmi_oe_n_pi1", +- "gmi_wait_pi7", +- "gmi_wr_n_pi0", +- "lcd_cs1_n_pw0", +- "pu0", +- "pu1", +- "pu2"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi-cs0-n-pj0 { +- nvidia,pins = "gmi_cs0_n_pj0", +- "gmi_cs1_n_pj2", +- "gmi_cs3_n_pk4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi-cs6-n-pi3 { +- nvidia,pins = "gmi_cs6_n_pi3"; +- nvidia,function = "sata"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi-cs7-n-pi6 { +- nvidia,pins = "gmi_cs7_n_pi6"; +- nvidia,function = "gmi_alt"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd-pwr0-pb2 { +- nvidia,pins = "lcd_pwr0_pb2", +- "lcd_pwr2_pc6", +- "lcd_wr_n_pz3"; +- nvidia,function = "hdcp"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2-cts-n-pj5 { +- nvidia,pins = "uart2_cts_n_pj5", +- "uart2_rts_n_pj6"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Power I2C (On-module) */ +- pwr-i2c-scl-pz6 { +- nvidia,pins = "pwr_i2c_scl_pz6", +- "pwr_i2c_sda_pz7"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* +- * THERMD_ALERT#, unlatched I2C address pin of LM95245 +- * temperature sensor therefore requires disabling for +- * now +- */ +- lcd-dc1-pd2 { +- nvidia,pins = "lcd_dc1_pd2"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* TOUCH_PEN_INT# (On-module) */ +- pv0 { +- nvidia,pins = "pv0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- }; +- }; +- +- serial@70006040 { +- compatible = "nvidia,tegra30-hsuart"; +- }; +- +- serial@70006200 { +- compatible = "nvidia,tegra30-hsuart"; +- }; +- +- serial@70006300 { +- compatible = "nvidia,tegra30-hsuart"; +- }; +- +- hdmi_ddc: i2c@7000c700 { +- clock-frequency = <10000>; +- }; +- +- /* +- * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and +- * touch screen controller +- */ +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <100000>; +- +- /* SGTL5000 audio codec */ +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- VDDA-supply = <®_module_3v3_audio>; +- VDDD-supply = <®_1v8_vio>; +- VDDIO-supply = <®_module_3v3>; +- clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; +- }; +- +- pmic: pmic@2d { +- compatible = "ti,tps65911"; +- reg = <0x2d>; +- +- interrupts = ; +- #interrupt-cells = <2>; +- interrupt-controller; +- wakeup-source; +- +- ti,system-power-controller; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- vcc1-supply = <®_module_3v3>; +- vcc2-supply = <®_module_3v3>; +- vcc3-supply = <®_1v8_vio>; +- vcc4-supply = <®_module_3v3>; +- vcc5-supply = <®_module_3v3>; +- vcc6-supply = <®_1v8_vio>; +- vcc7-supply = <®_5v0_charge_pump>; +- vccio-supply = <®_module_3v3>; +- +- regulators { +- vdd1_reg: vdd1 { +- regulator-name = "+V1.35_VDDIO_DDR"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- }; +- +- vdd2_reg: vdd2 { +- regulator-name = "+V1.05"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- vddctrl_reg: vddctrl { +- regulator-name = "+V1.0_VDD_CPU"; +- regulator-min-microvolt = <1150000>; +- regulator-max-microvolt = <1150000>; +- regulator-always-on; +- }; +- +- reg_1v8_vio: vio { +- regulator-name = "+V1.8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- /* LDO1: unused */ +- +- /* +- * EN_+V3.3 switching via FET: +- * +V3.3_AUDIO_AVDD_S, +V3.3 +- * see also +V3.3 fixed supply +- */ +- ldo2_reg: ldo2 { +- regulator-name = "EN_+V3.3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo3_reg: ldo3 { +- regulator-name = "+V1.2_CSI"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo4_reg: ldo4 { +- regulator-name = "+V1.2_VDD_RTC"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- /* +- * +V2.8_AVDD_VDAC: +- * only required for (unsupported) analog RGB +- */ +- ldo5_reg: ldo5 { +- regulator-name = "+V2.8_AVDD_VDAC"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- /* +- * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V +- * but LDO6 can't set voltage in 50mV +- * granularity +- */ +- ldo6_reg: ldo6 { +- regulator-name = "+V1.05_AVDD_PLLE"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- ldo7_reg: ldo7 { +- regulator-name = "+V1.2_AVDD_PLL"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo8_reg: ldo8 { +- regulator-name = "+V1.0_VDD_DDR_HS"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- }; +- }; +- +- /* STMPE811 touch screen controller */ +- touchscreen@41 { +- compatible = "st,stmpe811"; +- reg = <0x41>; +- irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- id = <0>; +- blocks = <0x5>; +- irq-trigger = <0x1>; +- /* 3.25 MHz ADC clock speed */ +- st,adc-freq = <1>; +- /* 12-bit ADC */ +- st,mod-12b = <1>; +- /* internal ADC reference */ +- st,ref-sel = <0>; +- /* ADC converstion time: 80 clocks */ +- st,sample-time = <4>; +- +- stmpe_touchscreen { +- compatible = "st,stmpe-ts"; +- /* 8 sample average control */ +- st,ave-ctrl = <3>; +- /* 7 length fractional part in z */ +- st,fraction-z = <7>; +- /* +- * 50 mA typical 80 mA max touchscreen drivers +- * current limit value +- */ +- st,i-drive = <1>; +- /* 1 ms panel driver settling time */ +- st,settling = <3>; +- /* 5 ms touch detect interrupt delay */ +- st,touch-det-delay = <5>; +- }; +- +- stmpe_adc { +- compatible = "st,stmpe-adc"; +- /* forbid to use ADC channels 3-0 (touch) */ +- st,norequest-mask = <0x0F>; +- }; +- }; +- +- /* +- * LM95245 temperature sensor +- * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN +- */ +- temp-sensor@4c { +- compatible = "national,lm95245"; +- reg = <0x4c>; +- }; +- +- /* SW: +V1.2_VDD_CORE */ +- regulator@60 { +- compatible = "ti,tps62362"; +- reg = <0x60>; +- +- regulator-name = "tps62362-vout"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- regulator-always-on; +- ti,vsel0-state-low; +- /* VSEL1: EN_CORE_DVFS_N low for DVFS */ +- ti,vsel1-state-low; +- }; +- }; +- +- /* SPI4: CAN2 */ +- spi@7000da00 { +- status = "okay"; +- spi-max-frequency = <10000000>; +- +- can@1 { +- compatible = "microchip,mcp2515"; +- reg = <1>; +- clocks = <&clk16m>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- spi-max-frequency = <10000000>; +- }; +- }; +- +- /* SPI6: CAN1 */ +- spi@7000de00 { +- status = "okay"; +- spi-max-frequency = <10000000>; +- +- can@0 { +- compatible = "microchip,mcp2515"; +- reg = <0>; +- clocks = <&clk16m>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- spi-max-frequency = <10000000>; +- }; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <5000>; +- nvidia,cpu-pwr-off-time = <5000>; +- nvidia,core-pwr-good-time = <3845 3845>; +- nvidia,core-pwr-off-time = <0>; +- nvidia,core-power-req-active-high; +- nvidia,sys-clock-req-active-high; +- +- /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ +- i2c-thermtrip { +- nvidia,i2c-controller-id = <4>; +- nvidia,bus-addr = <0x2d>; +- nvidia,reg-addr = <0x3f>; +- nvidia,reg-data = <0x1>; +- }; +- }; +- +- hda@70030000 { +- status = "okay"; +- }; +- +- ahub@70080000 { +- i2s@70080500 { +- status = "okay"; +- }; +- }; +- +- /* eMMC */ +- mmc@78000600 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- vmmc-supply = <®_module_3v3>; /* VCC */ +- vqmmc-supply = <®_1v8_vio>; /* VCCQ */ +- mmc-ddr-1_8v; +- }; +- +- clk32k_in: xtal1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- clk16m: osc4 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <16000000>; +- }; +- +- reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { +- compatible = "regulator-fixed"; +- regulator-name = "+V1.8_AVDD_HDMI_PLL"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- enable-active-high; +- gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; +- vin-supply = <®_1v8_vio>; +- }; +- +- reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3_AVDD_HDMI"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; +- vin-supply = <®_module_3v3>; +- }; +- +- reg_5v0_charge_pump: regulator-5v0-charge-pump { +- compatible = "regulator-fixed"; +- regulator-name = "+V5.0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_module_3v3: regulator-module-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_module_3v3_audio: regulator-module-3v3-audio { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3_AUDIO_AVDD_S"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- sound { +- compatible = "toradex,tegra-audio-sgtl5000-apalis_t30", +- "nvidia,tegra-audio-sgtl5000"; +- nvidia,model = "Toradex Apalis T30"; +- nvidia,audio-routing = +- "Headphone Jack", "HP_OUT", +- "LINE_IN", "Line In Jack", +- "MIC_IN", "Mic Jack"; +- nvidia,i2s-controller = <&tegra_i2s2>; +- nvidia,audio-codec = <&sgtl5000>; +- clocks = <&tegra_car TEGRA30_CLK_PLL_A>, +- <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- +- assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- +- assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA30_CLK_EXTERN1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper-E1565.dts b/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper-E1565.dts +deleted file mode 100644 +index a25b8560b0cd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper-E1565.dts ++++ /dev/null +@@ -1,9 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "tegra30-asus-nexus7-grouper-maxim-pmic.dtsi" +-#include "tegra30-asus-nexus7-grouper.dtsi" +- +-/ { +- model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) E1565"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper-PM269.dts b/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper-PM269.dts +deleted file mode 100644 +index 06ef13ea5df8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper-PM269.dts ++++ /dev/null +@@ -1,9 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "tegra30-asus-nexus7-grouper-ti-pmic.dtsi" +-#include "tegra30-asus-nexus7-grouper.dtsi" +- +-/ { +- model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) PM269"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper-common.dtsi b/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper-common.dtsi +deleted file mode 100644 +index 9732cd6f20b7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper-common.dtsi ++++ /dev/null +@@ -1,1341 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include +-#include +-#include +-#include +- +-#include "tegra30.dtsi" +-#include "tegra30-cpu-opp.dtsi" +-#include "tegra30-cpu-opp-microvolt.dtsi" +- +-/ { +- aliases { +- mmc0 = &sdmmc4; /* eMMC */ +- mmc1 = &sdmmc3; /* WiFi */ +- +- rtc0 = &pmic; +- rtc1 = "/rtc@7000e000"; +- +- serial1 = &uartc; /* Bluetooth */ +- serial2 = &uartb; /* GPS */ +- }; +- +- /* +- * The decompressor and also some bootloaders rely on a +- * pre-existing /chosen node to be available to insert the +- * command line and merge other ATAGS info. +- */ +- chosen {}; +- +- memory@80000000 { +- reg = <0x80000000 0x40000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- linux,cma@80000000 { +- compatible = "shared-dma-pool"; +- alloc-ranges = <0x80000000 0x30000000>; +- size = <0x10000000>; /* 256MiB */ +- linux,cma-default; +- reusable; +- }; +- +- ramoops@bfdf0000 { +- compatible = "ramoops"; +- reg = <0xbfdf0000 0x10000>; /* 64kB */ +- console-size = <0x8000>; /* 32kB */ +- record-size = <0x400>; /* 1kB */ +- ecc-size = <16>; +- }; +- +- trustzone@bfe00000 { +- reg = <0xbfe00000 0x200000>; +- no-map; +- }; +- }; +- +- host1x@50000000 { +- dc@54200000 { +- rgb { +- status = "okay"; +- +- port@0 { +- lcd_output: endpoint { +- remote-endpoint = <&lvds_encoder_input>; +- bus-width = <24>; +- }; +- }; +- }; +- }; +- }; +- +- gpio@6000d000 { +- init-mode-hog { +- gpio-hog; +- gpios = , +- , +- ; +- output-low; +- }; +- +- init-low-power-mode-hog { +- gpio-hog; +- gpios = ; +- input; +- }; +- }; +- +- pinmux@70000868 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- clk_32k_out_pa0 { +- nvidia,pins = "clk_32k_out_pa0"; +- nvidia,function = "blink"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_cts_n_pa1 { +- nvidia,pins = "uart3_cts_n_pa1", +- "uart3_rxd_pw7"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_fs_pa2 { +- nvidia,pins = "dap2_fs_pa2", +- "dap2_sclk_pa3", +- "dap2_din_pa4", +- "dap2_dout_pa5"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_clk_pa6 { +- nvidia,pins = "sdmmc3_clk_pa6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_cmd_pa7 { +- nvidia,pins = "sdmmc3_cmd_pa7", +- "sdmmc3_dat3_pb4", +- "sdmmc3_dat2_pb5", +- "sdmmc3_dat1_pb6", +- "sdmmc3_dat0_pb7", +- "sdmmc3_dat4_pd1", +- "sdmmc3_dat6_pd3", +- "sdmmc3_dat7_pd4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_a17_pb0 { +- nvidia,pins = "gmi_a17_pb0", +- "gmi_a18_pb1"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_pwr0_pb2 { +- nvidia,pins = "lcd_pwr0_pb2", +- "lcd_pwr1_pc1", +- "lcd_m1_pw1"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_pclk_pb3 { +- nvidia,pins = "lcd_pclk_pb3", +- "lcd_d0_pe0", +- "lcd_d1_pe1", +- "lcd_d2_pe2", +- "lcd_d3_pe3", +- "lcd_d4_pe4", +- "lcd_d5_pe5", +- "lcd_d6_pe6", +- "lcd_d7_pe7", +- "lcd_d8_pf0", +- "lcd_d9_pf1", +- "lcd_d10_pf2", +- "lcd_d11_pf3", +- "lcd_d12_pf4", +- "lcd_d13_pf5", +- "lcd_d14_pf6", +- "lcd_d15_pf7", +- "lcd_de_pj1", +- "lcd_hsync_pj3", +- "lcd_vsync_pj4", +- "lcd_d16_pm0", +- "lcd_d17_pm1", +- "lcd_d18_pm2", +- "lcd_d19_pm3", +- "lcd_d20_pm4", +- "lcd_d21_pm5", +- "lcd_d22_pm6", +- "lcd_d23_pm7", +- "lcd_cs0_n_pn4", +- "lcd_sdout_pn5", +- "lcd_dc0_pn6", +- "lcd_cs1_n_pw0", +- "lcd_sdin_pz2", +- "lcd_sck_pz4"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_rts_n_pc0 { +- nvidia,pins = "uart3_rts_n_pc0", +- "uart3_txd_pw6"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_txd_pc2 { +- nvidia,pins = "uart2_txd_pc2", +- "uart2_rts_n_pj6"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_rxd_pc3 { +- nvidia,pins = "uart2_rxd_pc3", +- "uart2_cts_n_pj5"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gen1_i2c_scl_pc4 { +- nvidia,pins = "gen1_i2c_scl_pc4", +- "gen1_i2c_sda_pc5"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gmi_wp_n_pc7 { +- nvidia,pins = "gmi_wp_n_pc7", +- "gmi_wait_pi7", +- "gmi_cs4_n_pk2", +- "gmi_cs3_n_pk4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad12_ph4 { +- nvidia,pins = "gmi_ad12_ph4", +- "gmi_cs0_n_pj0", +- "gmi_cs1_n_pj2", +- "gmi_cs2_n_pk3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat5_pd0 { +- nvidia,pins = "sdmmc3_dat5_pd0"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad0_pg0 { +- nvidia,pins = "gmi_ad0_pg0", +- "gmi_ad1_pg1", +- "gmi_ad14_ph6", +- "pu1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad2_pg2 { +- nvidia,pins = "gmi_ad2_pg2", +- "gmi_ad3_pg3", +- "gmi_ad6_pg6", +- "gmi_ad7_pg7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad4_pg4 { +- nvidia,pins = "gmi_ad4_pg4", +- "gmi_ad5_pg5"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad8_ph0 { +- nvidia,pins = "gmi_ad8_ph0"; +- nvidia,function = "pwm0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad9_ph1 { +- nvidia,pins = "gmi_ad9_ph1"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad10_ph2 { +- nvidia,pins = "gmi_ad10_ph2"; +- nvidia,function = "pwm2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad11_ph3 { +- nvidia,pins = "gmi_ad11_ph3"; +- nvidia,function = "pwm3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad13_ph5 { +- nvidia,pins = "gmi_ad13_ph5", +- "gmi_wr_n_pi0", +- "gmi_oe_n_pi1", +- "gmi_adv_n_pk0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad15_ph7 { +- nvidia,pins = "gmi_ad15_ph7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_dqs_pi2 { +- nvidia,pins = "gmi_dqs_pi2", +- "pu2", +- "pv1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_rst_n_pi4 { +- nvidia,pins = "gmi_rst_n_pi4"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_iordy_pi5 { +- nvidia,pins = "gmi_iordy_pi5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_cs7_n_pi6 { +- nvidia,pins = "gmi_cs7_n_pi6", +- "gmi_clk_pk1"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_a16_pj7 { +- nvidia,pins = "gmi_a16_pj7", +- "gmi_a19_pk7"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spdif_out_pk5 { +- nvidia,pins = "spdif_out_pk5"; +- nvidia,function = "spdif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spdif_in_pk6 { +- nvidia,pins = "spdif_in_pk6"; +- nvidia,function = "spdif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_fs_pn0 { +- nvidia,pins = "dap1_fs_pn0", +- "dap1_din_pn1", +- "dap1_dout_pn2", +- "dap1_sclk_pn3"; +- nvidia,function = "i2s0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- hdmi_int_pn7 { +- nvidia,pins = "hdmi_int_pn7"; +- nvidia,function = "hdmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data7_po0 { +- nvidia,pins = "ulpi_data7_po0"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data3_po4 { +- nvidia,pins = "ulpi_data3_po4"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_fs_pp0 { +- nvidia,pins = "dap3_fs_pp0"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_fs_pp4 { +- nvidia,pins = "dap4_fs_pp4", +- "dap4_din_pp5", +- "dap4_dout_pp6", +- "dap4_sclk_pp7"; +- nvidia,function = "i2s3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col0_pq0 { +- nvidia,pins = "kb_col0_pq0", +- "kb_col1_pq1", +- "kb_row1_pr1"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col2_pq2 { +- nvidia,pins = "kb_col2_pq2", +- "kb_col3_pq3"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col4_pq4 { +- nvidia,pins = "kb_col4_pq4", +- "kb_col5_pq5", +- "kb_col7_pq7", +- "kb_row2_pr2", +- "kb_row4_pr4", +- "kb_row5_pr5", +- "kb_row14_ps6"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row0_pr0 { +- nvidia,pins = "kb_row0_pr0"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row6_pr6 { +- nvidia,pins = "kb_row6_pr6", +- "kb_row8_ps0", +- "kb_row9_ps1", +- "kb_row10_ps2"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row11_ps3 { +- nvidia,pins = "kb_row11_ps3", +- "kb_row12_ps4"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gen2_i2c_scl_pt5 { +- nvidia,pins = "gen2_i2c_scl_pt5", +- "gen2_i2c_sda_pt6"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc4_cmd_pt7 { +- nvidia,pins = "sdmmc4_cmd_pt7", +- "sdmmc4_dat0_paa0", +- "sdmmc4_dat1_paa1", +- "sdmmc4_dat2_paa2", +- "sdmmc4_dat3_paa3", +- "sdmmc4_dat4_paa4", +- "sdmmc4_dat5_paa5", +- "sdmmc4_dat6_paa6", +- "sdmmc4_dat7_paa7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu0 { +- nvidia,pins = "pu0", +- "pu6"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- jtag_rtck_pu7 { +- nvidia,pins = "jtag_rtck_pu7"; +- nvidia,function = "rtck"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv0 { +- nvidia,pins = "pv0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ddc_scl_pv4 { +- nvidia,pins = "ddc_scl_pv4", +- "ddc_sda_pv5"; +- nvidia,function = "i2c4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- crt_hsync_pv6 { +- nvidia,pins = "crt_hsync_pv6", +- "crt_vsync_pv7"; +- nvidia,function = "crt"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi2_cs1_n_pw2 { +- nvidia,pins = "spi2_cs1_n_pw2", +- "spi2_miso_px1", +- "spi2_sck_px2"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk1_out_pw4 { +- nvidia,pins = "clk1_out_pw4"; +- nvidia,function = "extperiph1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2_out_pw5 { +- nvidia,pins = "clk2_out_pw5"; +- nvidia,function = "extperiph2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi2_cs0_n_px3 { +- nvidia,pins = "spi2_cs0_n_px3"; +- nvidia,function = "spi6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi1_mosi_px4 { +- nvidia,pins = "spi1_mosi_px4", +- "spi1_cs0_n_px6"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_clk_py0 { +- nvidia,pins = "ulpi_clk_py0", +- "ulpi_dir_py1"; +- nvidia,function = "ulpi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat3_py4 { +- nvidia,pins = "sdmmc1_dat3_py4", +- "sdmmc1_dat2_py5", +- "sdmmc1_dat1_py6", +- "sdmmc1_dat0_py7", +- "sdmmc1_cmd_pz1"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_clk_pz0 { +- nvidia,pins = "sdmmc1_clk_pz0"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_wr_n_pz3 { +- nvidia,pins = "lcd_wr_n_pz3"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sys_clk_req_pz5 { +- nvidia,pins = "sys_clk_req_pz5"; +- nvidia,function = "sysclk"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pwr_i2c_scl_pz6 { +- nvidia,pins = "pwr_i2c_scl_pz6", +- "pwr_i2c_sda_pz7"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pbb0 { +- nvidia,pins = "pbb0", +- "pcc1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cam_i2c_scl_pbb1 { +- nvidia,pins = "cam_i2c_scl_pbb1", +- "cam_i2c_sda_pbb2"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pbb3 { +- nvidia,pins = "pbb3"; +- nvidia,function = "vgp3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb4 { +- nvidia,pins = "pbb4"; +- nvidia,function = "vgp4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb5 { +- nvidia,pins = "pbb5"; +- nvidia,function = "vgp5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb6 { +- nvidia,pins = "pbb6"; +- nvidia,function = "vgp6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb7 { +- nvidia,pins = "pbb7", +- "pcc2"; +- nvidia,function = "i2s4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cam_mclk_pcc0 { +- nvidia,pins = "cam_mclk_pcc0"; +- nvidia,function = "vi_alt3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_rst_n_pcc3 { +- nvidia,pins = "sdmmc4_rst_n_pcc3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_clk_pcc4 { +- nvidia,pins = "sdmmc4_clk_pcc4"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2_req_pcc5 { +- nvidia,pins = "clk2_req_pcc5"; +- nvidia,function = "dap"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l2_rst_n_pcc6 { +- nvidia,pins = "pex_l2_rst_n_pcc6", +- "pex_l2_clkreq_n_pcc7"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_wake_n_pdd3 { +- nvidia,pins = "pex_wake_n_pdd3", +- "pex_l2_prsnt_n_pdd7"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3_out_pee0 { +- nvidia,pins = "clk3_out_pee0"; +- nvidia,function = "extperiph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk1_req_pee2 { +- nvidia,pins = "clk1_req_pee2"; +- nvidia,function = "dap"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- hdmi_cec_pee3 { +- nvidia,pins = "hdmi_cec_pee3"; +- nvidia,function = "cec"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- owr { +- nvidia,pins = "owr"; +- nvidia,function = "owr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- drive_dap1 { +- nvidia,pins = "drive_dap1", +- "drive_dap2", +- "drive_dbg", +- "drive_at5", +- "drive_gme", +- "drive_ddc", +- "drive_ao1", +- "drive_uart3"; +- nvidia,high-speed-mode = <0>; +- nvidia,schmitt = ; +- nvidia,low-power-mode = ; +- nvidia,pull-down-strength = <31>; +- nvidia,pull-up-strength = <31>; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- }; +- drive_sdio1 { +- nvidia,pins = "drive_sdio1", +- "drive_sdio3"; +- nvidia,high-speed-mode = <0>; +- nvidia,schmitt = ; +- nvidia,pull-down-strength = <46>; +- nvidia,pull-up-strength = <42>; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- }; +- drive_gma { +- nvidia,pins = "drive_gma", +- "drive_gmb", +- "drive_gmc", +- "drive_gmd"; +- nvidia,pull-down-strength = <9>; +- nvidia,pull-up-strength = <9>; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- }; +- }; +- }; +- +- uartb: serial@70006040 { +- compatible = "nvidia,tegra30-hsuart"; +- /* GPS BCM4751 */ +- }; +- +- uartc: serial@70006200 { +- compatible = "nvidia,tegra30-hsuart"; +- status = "okay"; +- +- nvidia,adjust-baud-rates = <0 9600 100>, +- <9600 115200 200>, +- <1000000 4000000 136>; +- +- /* Azurewave AW-NH665 BCM4330B1 */ +- bluetooth { +- compatible = "brcm,bcm4330-bt"; +- +- max-speed = <4000000>; +- +- clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; +- clock-names = "txco"; +- +- vbat-supply = <&vdd_3v3_sys>; +- vddio-supply = <&vdd_1v8>; +- +- device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- pwm: pwm@7000a000 { +- status = "okay"; +- }; +- +- i2c@7000c400 { +- clock-frequency = <400000>; +- status = "okay"; +- +- touchscreen@10 { +- compatible ="elan,ektf3624"; +- reg = <0x10>; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; +- +- vcc33-supply = <&vcc_3v3_ts>; +- vccio-supply = <&vcc_3v3_ts>; +- +- touchscreen-size-x = <2112>; +- touchscreen-size-y = <1280>; +- touchscreen-swapped-x-y; +- touchscreen-inverted-x; +- }; +- }; +- +- i2c@7000c500 { +- clock-frequency = <100000>; +- status = "okay"; +- +- compass@e { +- compatible = "asahi-kasei,ak8974"; +- reg = <0x0e>; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- avdd-supply = <&vdd_3v3_sys>; +- dvdd-supply = <&vdd_1v8>; +- +- mount-matrix = "0", "-1", "0", +- "-1", "0", "0", +- "0", "0", "-1"; +- }; +- +- light-sensor@1c { +- compatible = "dynaimage,al3010"; +- reg = <0x1c>; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- vdd-supply = <&vdd_3v3_sys>; +- }; +- +- accelerometer@68 { +- compatible = "invensense,mpu6050"; +- reg = <0x68>; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- vdd-supply = <&vdd_3v3_sys>; +- vddio-supply = <&vdd_1v8>; +- +- mount-matrix = "0", "-1", "0", +- "-1", "0", "0", +- "0", "0", "-1"; +- }; +- }; +- +- i2c@7000d000 { +- clock-frequency = <100000>; +- status = "okay"; +- +- rt5640: audio-codec@1c { +- compatible = "realtek,rt5640"; +- reg = <0x1c>; +- +- realtek,dmic1-data-pin = <1>; +- }; +- +- nct72: temperature-sensor@4c { +- compatible = "onnn,nct1008"; +- reg = <0x4c>; +- vcc-supply = <&vdd_3v3_sys>; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- #thermal-sensor-cells = <1>; +- }; +- +- fuel-gauge@55 { +- compatible = "ti,bq27541"; +- reg = <0x55>; +- power-supplies = <&power_supply>; +- }; +- +- power_supply: charger@6a { +- compatible = "summit,smb347"; +- reg = <0x6a>; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- summit,enable-charge-control = ; +- summit,enable-usb-charging; +- +- monitored-battery = <&battery_cell>; +- }; +- }; +- +- pmc@7000e400 { +- status = "okay"; +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <2000>; +- nvidia,cpu-pwr-off-time = <200>; +- nvidia,core-pwr-good-time = <3845 3845>; +- nvidia,core-pwr-off-time = <0>; +- nvidia,core-power-req-active-high; +- nvidia,sys-clock-req-active-high; +- }; +- +- ahub@70080000 { +- i2s@70080400 { +- status = "okay"; +- }; +- }; +- +- brcm_wifi_pwrseq: wifi-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- +- clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; +- clock-names = "ext_clock"; +- +- reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; +- post-power-on-delay-ms = <300>; +- power-off-delay-us = <300>; +- }; +- +- sdmmc3: mmc@78000400 { +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; +- assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; +- assigned-clock-rates = <50000000>; +- +- max-frequency = <50000000>; +- keep-power-in-suspend; +- bus-width = <4>; +- non-removable; +- +- mmc-pwrseq = <&brcm_wifi_pwrseq>; +- vmmc-supply = <&vdd_3v3_sys>; +- vqmmc-supply = <&vdd_1v8>; +- +- /* Azurewave AW-NH665 BCM4330 */ +- wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&gpio>; +- interrupts = ; +- interrupt-names = "host-wake"; +- }; +- }; +- +- sdmmc4: mmc@78000600 { +- status = "okay"; +- bus-width = <8>; +- vmmc-supply = <&vcore_emmc>; +- vqmmc-supply = <&vdd_1v8>; +- non-removable; +- }; +- +- usb@7d000000 { +- compatible = "nvidia,tegra30-udc"; +- status = "okay"; +- dr_mode = "peripheral"; +- }; +- +- usb-phy@7d000000 { +- status = "okay"; +- dr_mode = "peripheral"; +- nvidia,hssync-start-delay = <0>; +- nvidia,xcvr-lsfslew = <2>; +- nvidia,xcvr-lsrslew = <2>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- +- power-supply = <&vdd_5v0_sys>; +- pwms = <&pwm 0 50000>; +- +- brightness-levels = <1 255>; +- num-interpolated-steps = <254>; +- default-brightness-level = <15>; +- }; +- +- battery_cell: battery-cell { +- compatible = "simple-battery"; +- constant-charge-current-max-microamp = <1800000>; +- operating-range-celsius = <0 45>; +- }; +- +- /* PMIC has a built-in 32KHz oscillator which is used by PMC */ +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "pmic-oscillator"; +- }; +- +- cpus { +- cpu0: cpu@0 { +- cpu-supply = <&vdd_cpu>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- cpu-supply = <&vdd_cpu>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- cpu-supply = <&vdd_cpu>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- cpu-supply = <&vdd_cpu>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- }; +- +- display-panel { +- /* +- * Nexus 7 supports two compatible panel models: +- * +- * 1. hydis,hv070wx2-1e0 +- * 2. chunghwa,claa070wp03xg +- * +- * We want to use timing which is optimized for Nexus 7, +- * hence we need to customize the timing. +- */ +- compatible = "panel-lvds"; +- +- power-supply = <&vdd_pnl>; +- backlight = <&backlight>; +- +- width-mm = <94>; +- height-mm = <150>; +- rotation = <180>; +- +- data-mapping = "jeida-24"; +- +- port { +- panel_input: endpoint { +- remote-endpoint = <&lvds_encoder_output>; +- }; +- }; +- }; +- +- firmware { +- trusted-foundations { +- compatible = "tlm,trusted-foundations"; +- tlm,version-major = <0x0>; +- tlm,version-minor = <0x0>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- hall-sensor { +- label = "Lid"; +- gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; +- linux,input-type = ; +- linux,code = ; +- debounce-interval = <500>; +- wakeup-event-action = ; +- wakeup-source; +- }; +- +- power { +- label = "Power"; +- gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-event-action = ; +- wakeup-source; +- }; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-event-action = ; +- wakeup-source; +- }; +- +- volume-down { +- label = "Volume Down"; +- gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-event-action = ; +- wakeup-source; +- }; +- }; +- +- lvds-encoder { +- compatible = "ti,sn75lvds83", "lvds-encoder"; +- +- powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; +- power-supply = <&vdd_3v3_sys>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- lvds_encoder_input: endpoint { +- remote-endpoint = <&lcd_output>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lvds_encoder_output: endpoint { +- remote-endpoint = <&panel_input>; +- }; +- }; +- }; +- }; +- +- vdd_5v0_sys: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_3v3_sys: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_pnl: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_panel"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <300000>; +- gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_3v3_sys>; +- }; +- +- vcc_3v3_ts: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "ldo_s-1167_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- sound { +- compatible = "nvidia,tegra-audio-rt5640-grouper", +- "nvidia,tegra-audio-rt5640"; +- nvidia,model = "ASUS Google Nexus 7 ALC5642"; +- +- nvidia,audio-routing = +- "Headphones", "HPOR", +- "Headphones", "HPOL", +- "Speakers", "SPORP", +- "Speakers", "SPORN", +- "Speakers", "SPOLP", +- "Speakers", "SPOLN", +- "DMIC1", "Mic Jack"; +- +- nvidia,i2s-controller = <&tegra_i2s1>; +- nvidia,audio-codec = <&rt5640>; +- +- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; +- +- clocks = <&tegra_car TEGRA30_CLK_PLL_A>, +- <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- +- assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- +- assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA30_CLK_EXTERN1>; +- }; +- +- thermal-zones { +- /* +- * NCT72 has two sensors: +- * +- * 0: internal that monitors ambient/skin temperature +- * 1: external that is connected to the CPU's diode +- * +- * Ideally we should use userspace thermal governor, +- * but it's a much more complex solution. The "skin" +- * zone is a simpler solution which prevents Nexus 7 +- * from getting too hot from a user's tactile perspective. +- * The CPU zone is intended to protect silicon from damage. +- */ +- +- skin-thermal { +- polling-delay-passive = <1000>; /* milliseconds */ +- polling-delay = <5000>; /* milliseconds */ +- +- thermal-sensors = <&nct72 0>; +- +- trips { +- trip0: skin-alert { +- /* throttle at 57C until temperature drops to 56.8C */ +- temperature = <57000>; +- hysteresis = <200>; +- type = "passive"; +- }; +- +- trip1: skin-crit { +- /* shut down at 65C */ +- temperature = <65000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&trip0>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&actmon THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu-thermal { +- polling-delay-passive = <1000>; /* milliseconds */ +- polling-delay = <5000>; /* milliseconds */ +- +- thermal-sensors = <&nct72 1>; +- +- trips { +- trip2: cpu-alert { +- /* throttle at 85C until temperature drops to 84.8C */ +- temperature = <85000>; +- hysteresis = <200>; +- type = "passive"; +- }; +- +- trip3: cpu-crit { +- /* shut down at 90C */ +- temperature = <90000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map1 { +- trip = <&trip2>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&actmon THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi +deleted file mode 100644 +index 53966fa4eef2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi ++++ /dev/null +@@ -1,194 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include +-#include +-#include +- +-/ { +- i2c@7000d000 { +- pmic: pmic@3c { +- compatible = "maxim,max77663"; +- reg = <0x3c>; +- +- interrupts = ; +- #interrupt-cells = <2>; +- interrupt-controller; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- system-power-controller; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&max77620_default>; +- +- max77620_default: pinmux { +- gpio4 { +- pins = "gpio4"; +- function = "32k-out1"; +- }; +- }; +- +- cpu-pwr-req-hog { +- gpio-hog; +- gpios = <6 GPIO_ACTIVE_HIGH>; +- input; +- }; +- +- fps { +- fps0 { +- maxim,fps-event-source = ; +- }; +- +- fps1 { +- maxim,fps-event-source = ; +- }; +- +- fps2 { +- maxim,fps-event-source = ; +- }; +- }; +- +- regulators { +- in-sd0-supply = <&vdd_5v0_sys>; +- in-sd1-supply = <&vdd_5v0_sys>; +- in-sd2-supply = <&vdd_5v0_sys>; +- in-sd3-supply = <&vdd_5v0_sys>; +- in-sd4-supply = <&vdd_5v0_sys>; +- +- in-ldo0-1-supply = <&vdd_1v35>; +- in-ldo2-supply = <&vdd_3v3_sys>; +- in-ldo3-5-supply = <&vdd_3v3_sys>; +- in-ldo4-6-supply = <&vdd_5v0_sys>; +- in-ldo7-8-supply = <&vdd_1v35>; +- +- vdd_cpu: sd0 { +- regulator-name = "vdd_cpu"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1250000>; +- regulator-coupled-with = <&vdd_core>; +- regulator-coupled-max-spread = <300000>; +- regulator-max-step-microvolt = <100000>; +- regulator-always-on; +- regulator-boot-on; +- +- nvidia,tegra-cpu-regulator; +- }; +- +- vdd_core: sd1 { +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1350000>; +- regulator-coupled-with = <&vdd_cpu>; +- regulator-coupled-max-spread = <300000>; +- regulator-max-step-microvolt = <100000>; +- regulator-always-on; +- regulator-boot-on; +- +- nvidia,tegra-core-regulator; +- }; +- +- vdd_1v8: sd2 { +- regulator-name = "vdd_gen1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v35: sd3 { +- regulator-name = "vdd_ddr3l_1v35"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo0 { +- regulator-name = "vdd_ddr_hs"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo2 { +- regulator-name = "vdd_ddr_rx"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcore_emmc: ldo3 { +- regulator-name = "vcore_emmc"; +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <3100000>; +- regulator-always-on; +- }; +- +- ldo4 { +- regulator-name = "vdd_rtc"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo5 { +- regulator-name = "vdd_camera"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo6 { +- regulator-name = "vddio_sdmmc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo7 { +- regulator-name = "avdd_dsi_csi"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo8 { +- regulator-name = "avdd_pll"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +- }; +- +- vdd_3v3_sys: regulator@1 { +- gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- regulator@4 { +- compatible = "regulator-fixed"; +- regulator-name = "avdd_usb"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_3v3_sys>; +- }; +- +- pmc@7000e400 { +- i2c-thermtrip { +- nvidia,i2c-controller-id = <4>; +- nvidia,bus-addr = <0x3c>; +- nvidia,reg-addr = <0x41>; +- nvidia,reg-data = <0xe0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper-memory-timings.dtsi b/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper-memory-timings.dtsi +deleted file mode 100644 +index bcff0997ee51..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper-memory-timings.dtsi ++++ /dev/null +@@ -1,1577 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/ { +- memory-controller@7000f000 { +- emc-timings-0 { +- nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */ +- +- timing-25500000 { +- clock-frequency = <25500000>; +- +- nvidia,emem-configuration = < +- 0x00020001 /* MC_EMEM_ARB_CFG */ +- 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ +- 0x74830303 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-51000000 { +- clock-frequency = <51000000>; +- +- nvidia,emem-configuration = < +- 0x00010001 /* MC_EMEM_ARB_CFG */ +- 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ +- 0x73430303 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-102000000 { +- clock-frequency = <102000000>; +- +- nvidia,emem-configuration = < +- 0x00000001 /* MC_EMEM_ARB_CFG */ +- 0xc0000030 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ +- 0x72830504 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-204000000 { +- clock-frequency = <204000000>; +- +- nvidia,emem-configuration = < +- 0x00000003 /* MC_EMEM_ARB_CFG */ +- 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ +- 0x72440a06 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-333500000 { +- clock-frequency = <333500000>; +- +- nvidia,emem-configuration = < +- 0x00000005 /* MC_EMEM_ARB_CFG */ +- 0xc000003d /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000b0608 /* MC_EMEM_ARB_DA_COVERS */ +- 0x70850f09 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-667000000 { +- clock-frequency = <667000000>; +- +- nvidia,emem-configuration = < +- 0x0000000a /* MC_EMEM_ARB_CFG */ +- 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000010 /* MC_EMEM_ARB_TIMING_RC */ +- 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */ +- 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x00130b10 /* MC_EMEM_ARB_DA_COVERS */ +- 0x70ea1f11 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- }; +- +- emc-timings-1 { +- nvidia,ram-code = <1>; /* Hynix H5TC2G83CFR */ +- +- timing-25500000 { +- clock-frequency = <25500000>; +- +- nvidia,emem-configuration = < +- 0x00020001 /* MC_EMEM_ARB_CFG */ +- 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ +- 0x74830303 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-51000000 { +- clock-frequency = <51000000>; +- +- nvidia,emem-configuration = < +- 0x00010001 /* MC_EMEM_ARB_CFG */ +- 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ +- 0x73430303 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-102000000 { +- clock-frequency = <102000000>; +- +- nvidia,emem-configuration = < +- 0x00000001 /* MC_EMEM_ARB_CFG */ +- 0xc0000030 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ +- 0x72830504 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-204000000 { +- clock-frequency = <204000000>; +- +- nvidia,emem-configuration = < +- 0x00000003 /* MC_EMEM_ARB_CFG */ +- 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ +- 0x72440a06 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-333500000 { +- clock-frequency = <333500000>; +- +- nvidia,emem-configuration = < +- 0x00000005 /* MC_EMEM_ARB_CFG */ +- 0xc000003d /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000b0608 /* MC_EMEM_ARB_DA_COVERS */ +- 0x70850f09 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- +- timing-667000000 { +- clock-frequency = <667000000>; +- +- nvidia,emem-configuration = < +- 0x0000000a /* MC_EMEM_ARB_CFG */ +- 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000010 /* MC_EMEM_ARB_TIMING_RC */ +- 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */ +- 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x00130b10 /* MC_EMEM_ARB_DA_COVERS */ +- 0x70ea1f11 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- }; +- }; +- +- memory-controller@7000f400 { +- emc-timings-0 { +- nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */ +- +- timing-25500000 { +- clock-frequency = <25500000>; +- +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-cfg-periodic-qrst; +- +- nvidia,emc-configuration = < +- 0x00000001 /* EMC_RC */ +- 0x00000004 /* EMC_RFC */ +- 0x00000000 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x000000c0 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000005 /* EMC_TXSR */ +- 0x00000005 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000001 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x000000c7 /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x007800a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00000000 /* EMC_ZCAL_INTERVAL */ +- 0x00000040 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- +- timing-51000000 { +- clock-frequency = <51000000>; +- +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-cfg-periodic-qrst; +- +- nvidia,emc-configuration = < +- 0x00000002 /* EMC_RC */ +- 0x00000008 /* EMC_RFC */ +- 0x00000001 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x00000181 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000009 /* EMC_TXSR */ +- 0x00000009 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000002 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x0000018e /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x007800a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00000000 /* EMC_ZCAL_INTERVAL */ +- 0x00000040 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- +- timing-102000000 { +- clock-frequency = <102000000>; +- +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-cfg-periodic-qrst; +- +- nvidia,emc-configuration = < +- 0x00000005 /* EMC_RC */ +- 0x00000010 /* EMC_RFC */ +- 0x00000003 /* EMC_RAS */ +- 0x00000001 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000001 /* EMC_RD_RCD */ +- 0x00000001 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x00000303 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000012 /* EMC_TXSR */ +- 0x00000012 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000004 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x0000031c /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x007800a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00000000 /* EMC_ZCAL_INTERVAL */ +- 0x00000040 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- +- timing-204000000 { +- clock-frequency = <204000000>; +- +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-cfg-periodic-qrst; +- +- nvidia,emc-configuration = < +- 0x0000000a /* EMC_RC */ +- 0x00000020 /* EMC_RFC */ +- 0x00000007 /* EMC_RAS */ +- 0x00000002 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000002 /* EMC_RD_RCD */ +- 0x00000002 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x00000607 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000023 /* EMC_TXSR */ +- 0x00000023 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000007 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000638 /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000006 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x004400a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00080000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00020000 /* EMC_ZCAL_INTERVAL */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- +- timing-333500000 { +- clock-frequency = <333500000>; +- +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200000>; +- nvidia,emc-mode-reset = <0x80000321>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- +- nvidia,emc-configuration = < +- 0x0000000f /* EMC_RC */ +- 0x00000034 /* EMC_RFC */ +- 0x0000000a /* EMC_RAS */ +- 0x00000003 /* EMC_RP */ +- 0x00000003 /* EMC_R2W */ +- 0x00000008 /* EMC_W2R */ +- 0x00000002 /* EMC_R2P */ +- 0x00000009 /* EMC_W2P */ +- 0x00000003 /* EMC_RD_RCD */ +- 0x00000003 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000004 /* EMC_WDV */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000c /* EMC_RDV */ +- 0x000009e9 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x0000027a /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000001 /* EMC_PDEX2WR */ +- 0x00000008 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000e /* EMC_RW2PDEN */ +- 0x00000039 /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x0000000a /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000a2a /* EMC_TREFBW */ +- 0x00000000 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00007088 /* EMC_FBIO_CFG5 */ +- 0x002600a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00014000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00014000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00014000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00014000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800013d /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f508 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x080001e8 /* EMC_XM2QUSEPADCTRL */ +- 0x08000021 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00020000 /* EMC_ZCAL_INTERVAL */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x018b000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x800014d4 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff89 /* EMC_CFG_RSV */ +- >; +- }; +- +- timing-667000000 { +- clock-frequency = <667000000>; +- +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200018>; +- nvidia,emc-mode-reset = <0x80000b71>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-periodic-qrst; +- +- nvidia,emc-configuration = < +- 0x0000001f /* EMC_RC */ +- 0x00000069 /* EMC_RFC */ +- 0x00000017 /* EMC_RAS */ +- 0x00000007 /* EMC_RP */ +- 0x00000005 /* EMC_R2W */ +- 0x0000000c /* EMC_W2R */ +- 0x00000003 /* EMC_R2P */ +- 0x00000011 /* EMC_W2P */ +- 0x00000007 /* EMC_RD_RCD */ +- 0x00000007 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000007 /* EMC_WDV */ +- 0x0000000b /* EMC_QUSE */ +- 0x00000009 /* EMC_QRST */ +- 0x0000000b /* EMC_QSAFE */ +- 0x00000011 /* EMC_RDV */ +- 0x00001412 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x0000000e /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x0000000c /* EMC_AR2PDEN */ +- 0x00000016 /* EMC_RW2PDEN */ +- 0x00000072 /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000005 /* EMC_TCKE */ +- 0x00000015 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000006 /* EMC_TCLKSTABLE */ +- 0x00000007 /* EMC_TCLKSTOP */ +- 0x00001453 /* EMC_TREFBW */ +- 0x0000000c /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00005088 /* EMC_FBIO_CFG5 */ +- 0xf00b0191 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00000008 /* EMC_DLL_XFORM_DQS0 */ +- 0x00000008 /* EMC_DLL_XFORM_DQS1 */ +- 0x00000008 /* EMC_DLL_XFORM_DQS2 */ +- 0x00000008 /* EMC_DLL_XFORM_DQS3 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS4 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS5 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS6 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x0000000c /* EMC_DLL_XFORM_DQ0 */ +- 0x0000000c /* EMC_DLL_XFORM_DQ1 */ +- 0x0000000c /* EMC_DLL_XFORM_DQ2 */ +- 0x0000000c /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0600013d /* EMC_XM2DQSPADCTRL2 */ +- 0x22220000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f501 /* EMC_XM2COMPPADCTRL */ +- 0x07077404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x080001e8 /* EMC_XM2QUSEPADCTRL */ +- 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00020000 /* EMC_ZCAL_INTERVAL */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x0156000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xf8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff49 /* EMC_CFG_RSV */ +- >; +- }; +- }; +- +- emc-timings-1 { +- nvidia,ram-code = <1>; /* Hynix H5TC2G83CFR */ +- +- timing-25500000 { +- clock-frequency = <25500000>; +- +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-cfg-periodic-qrst; +- +- nvidia,emc-configuration = < +- 0x00000001 /* EMC_RC */ +- 0x00000004 /* EMC_RFC */ +- 0x00000000 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x000000c0 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000005 /* EMC_TXSR */ +- 0x00000005 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000001 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x000000c7 /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x007800a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00000000 /* EMC_ZCAL_INTERVAL */ +- 0x00000040 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- +- timing-51000000 { +- clock-frequency = <51000000>; +- +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-cfg-periodic-qrst; +- +- nvidia,emc-configuration = < +- 0x00000002 /* EMC_RC */ +- 0x00000008 /* EMC_RFC */ +- 0x00000001 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x00000181 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000009 /* EMC_TXSR */ +- 0x00000009 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000002 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x0000018e /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x007800a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00000000 /* EMC_ZCAL_INTERVAL */ +- 0x00000040 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- +- timing-102000000 { +- clock-frequency = <102000000>; +- +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-cfg-periodic-qrst; +- +- nvidia,emc-configuration = < +- 0x00000005 /* EMC_RC */ +- 0x00000010 /* EMC_RFC */ +- 0x00000003 /* EMC_RAS */ +- 0x00000001 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000001 /* EMC_RD_RCD */ +- 0x00000001 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x00000303 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000012 /* EMC_TXSR */ +- 0x00000012 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000004 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x0000031c /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x007800a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00000000 /* EMC_ZCAL_INTERVAL */ +- 0x00000040 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- +- timing-204000000 { +- clock-frequency = <204000000>; +- +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-cfg-periodic-qrst; +- +- nvidia,emc-configuration = < +- 0x0000000a /* EMC_RC */ +- 0x00000020 /* EMC_RFC */ +- 0x00000007 /* EMC_RAS */ +- 0x00000002 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000002 /* EMC_RD_RCD */ +- 0x00000002 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x00000607 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000023 /* EMC_TXSR */ +- 0x00000023 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000007 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000638 /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000006 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x004400a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00080000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00020000 /* EMC_ZCAL_INTERVAL */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- +- timing-333500000 { +- clock-frequency = <333500000>; +- +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200000>; +- nvidia,emc-mode-reset = <0x80000321>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- +- nvidia,emc-configuration = < +- 0x0000000f /* EMC_RC */ +- 0x00000034 /* EMC_RFC */ +- 0x0000000a /* EMC_RAS */ +- 0x00000003 /* EMC_RP */ +- 0x00000003 /* EMC_R2W */ +- 0x00000008 /* EMC_W2R */ +- 0x00000002 /* EMC_R2P */ +- 0x00000009 /* EMC_W2P */ +- 0x00000003 /* EMC_RD_RCD */ +- 0x00000003 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000004 /* EMC_WDV */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000c /* EMC_RDV */ +- 0x000009e9 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x0000027a /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000001 /* EMC_PDEX2WR */ +- 0x00000008 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000e /* EMC_RW2PDEN */ +- 0x00000039 /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x0000000a /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000a2a /* EMC_TREFBW */ +- 0x00000000 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00007088 /* EMC_FBIO_CFG5 */ +- 0x002600a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00014000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00014000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00014000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00014000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0600013d /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f508 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x080001e8 /* EMC_XM2QUSEPADCTRL */ +- 0x08000021 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00020000 /* EMC_ZCAL_INTERVAL */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x018b000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x800014d4 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xf8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff89 /* EMC_CFG_RSV */ +- >; +- }; +- +- timing-667000000 { +- clock-frequency = <667000000>; +- +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200018>; +- nvidia,emc-mode-reset = <0x80000b71>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-periodic-qrst; +- +- nvidia,emc-configuration = < +- 0x00000020 /* EMC_RC */ +- 0x0000006a /* EMC_RFC */ +- 0x00000017 /* EMC_RAS */ +- 0x00000007 /* EMC_RP */ +- 0x00000005 /* EMC_R2W */ +- 0x0000000c /* EMC_W2R */ +- 0x00000003 /* EMC_R2P */ +- 0x00000011 /* EMC_W2P */ +- 0x00000007 /* EMC_RD_RCD */ +- 0x00000007 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000007 /* EMC_WDV */ +- 0x0000000a /* EMC_QUSE */ +- 0x00000009 /* EMC_QRST */ +- 0x0000000b /* EMC_QSAFE */ +- 0x00000011 /* EMC_RDV */ +- 0x00001412 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x0000000e /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x0000000c /* EMC_AR2PDEN */ +- 0x00000016 /* EMC_RW2PDEN */ +- 0x00000072 /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000005 /* EMC_TCKE */ +- 0x00000015 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000006 /* EMC_TCLKSTABLE */ +- 0x00000007 /* EMC_TCLKSTOP */ +- 0x00001453 /* EMC_TREFBW */ +- 0x0000000b /* EMC_QUSE_EXTRA */ +- 0x00000006 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00005088 /* EMC_FBIO_CFG5 */ +- 0xf00b0191 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x0000000a /* EMC_DLL_XFORM_DQS0 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS1 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS2 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS3 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS4 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS5 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS6 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x0000000c /* EMC_DLL_XFORM_DQ0 */ +- 0x0000000c /* EMC_DLL_XFORM_DQ1 */ +- 0x0000000c /* EMC_DLL_XFORM_DQ2 */ +- 0x0000000c /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0400013d /* EMC_XM2DQSPADCTRL2 */ +- 0x22220000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f501 /* EMC_XM2COMPPADCTRL */ +- 0x07077404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x080001e8 /* EMC_XM2QUSEPADCTRL */ +- 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00020000 /* EMC_ZCAL_INTERVAL */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x0155000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff49 /* EMC_CFG_RSV */ +- >; +- }; +- }; +- }; +-}; +- +-&emc_icc_dvfs_opp_table { +- /delete-node/ opp@750000000,1300; +- /delete-node/ opp@800000000,1300; +- /delete-node/ opp@900000000,1350; +-}; +- +-&emc_bw_dfs_opp_table { +- /delete-node/ opp@750000000; +- /delete-node/ opp@800000000; +- /delete-node/ opp@900000000; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper-ti-pmic.dtsi b/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper-ti-pmic.dtsi +deleted file mode 100644 +index 9365ae607239..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper-ti-pmic.dtsi ++++ /dev/null +@@ -1,159 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include +-#include +- +-/ { +- i2c@7000d000 { +- pmic: pmic@2d { +- compatible = "ti,tps65911"; +- reg = <0x2d>; +- +- interrupts = ; +- #interrupt-cells = <2>; +- interrupt-controller; +- wakeup-source; +- +- ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; +- ti,system-power-controller; +- ti,sleep-keep-ck32k; +- ti,sleep-enable; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- vcc1-supply = <&vdd_5v0_sys>; +- vcc2-supply = <&vdd_5v0_sys>; +- vcc3-supply = <&vdd_1v8>; +- vcc4-supply = <&vdd_5v0_sys>; +- vcc5-supply = <&vdd_5v0_sys>; +- vcc6-supply = <&vdd2_reg>; +- vcc7-supply = <&vdd_5v0_sys>; +- vccio-supply = <&vdd_5v0_sys>; +- +- regulators { +- vdd1 { +- regulator-name = "vddio_ddr_1v2"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- ti,regulator-ext-sleep-control = <8>; +- }; +- +- vdd2_reg: vdd2 { +- regulator-name = "vdd2_1v2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_cpu: vddctrl { +- regulator-name = "vdd_cpu,vdd_sys"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1250000>; +- regulator-coupled-with = <&vdd_core>; +- regulator-coupled-max-spread = <300000>; +- regulator-max-step-microvolt = <100000>; +- regulator-always-on; +- ti,regulator-ext-sleep-control = <1>; +- +- nvidia,tegra-cpu-regulator; +- }; +- +- vdd_1v8: vio { +- regulator-name = "vdd_1v8_gen"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcore_emmc: ldo1 { +- regulator-name = "vdd_pexa,vdd_pexb"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo2 { +- regulator-name = "vdd_sata,avdd_plle"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- /* LDO3 is not connected to anything */ +- +- ldo4 { +- regulator-name = "vdd_rtc"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo5 { +- regulator-name = "vddio_sdmmc,avdd_vdac"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo6 { +- regulator-name = "avdd_dsi_csi,pwrdet_mipi"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo7 { +- regulator-name = "vdd_pllm,x,u,a_p_c_s"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- ti,regulator-ext-sleep-control = <8>; +- }; +- +- ldo8 { +- regulator-name = "vdd_ddr_hs"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- ti,regulator-ext-sleep-control = <8>; +- }; +- }; +- }; +- +- vdd_core: core-regulator@60 { +- compatible = "ti,tps62361"; +- reg = <0x60>; +- +- regulator-name = "tps62361-vout"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1350000>; +- regulator-coupled-with = <&vdd_cpu>; +- regulator-coupled-max-spread = <300000>; +- regulator-max-step-microvolt = <100000>; +- regulator-boot-on; +- regulator-always-on; +- ti,enable-vout-discharge; +- ti,vsel0-state-high; +- ti,vsel1-state-high; +- +- nvidia,tegra-core-regulator; +- }; +- }; +- +- vdd_3v3_sys: regulator@1 { +- gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- pmc@7000e400 { +- i2c-thermtrip { +- nvidia,i2c-controller-id = <4>; +- nvidia,bus-addr = <0x2d>; +- nvidia,reg-addr = <0x3f>; +- nvidia,reg-data = <0x80>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper.dtsi b/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper.dtsi +deleted file mode 100644 +index a044dbd200a9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-grouper.dtsi ++++ /dev/null +@@ -1,149 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include "tegra30-asus-nexus7-grouper-common.dtsi" +-#include "tegra30-asus-nexus7-grouper-memory-timings.dtsi" +- +-/ { +- compatible = "asus,grouper", "nvidia,tegra30"; +- +- display-panel { +- panel-timing { +- clock-frequency = <68000000>; +- hactive = <800>; +- vactive = <1280>; +- hfront-porch = <24>; +- hback-porch = <32>; +- hsync-len = <24>; +- vsync-len = <1>; +- vfront-porch = <5>; +- vback-porch = <32>; +- }; +- }; +- +- pinmux@70000868 { +- state_default: pinmux { +- lcd_dc1_pd2 { +- nvidia,pins = "lcd_dc1_pd2"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_pwr2_pc6 { +- nvidia,pins = "lcd_pwr2_pc6"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi2_cs2_n_pw3 { +- nvidia,pins = "spi2_cs2_n_pw3"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi1_sck_px5 { +- nvidia,pins = "spi1_sck_px5"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu5 { +- nvidia,pins = "pu5"; +- nvidia,function = "pwm2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi1_miso_px7 { +- nvidia,pins = "spi1_miso_px7"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi2_mosi_px0 { +- nvidia,pins = "spi2_mosi_px0"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row7_pr7 { +- nvidia,pins = "kb_row7_pr7"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu3 { +- nvidia,pins = "pu3"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu4 { +- nvidia,pins = "pu4"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row15_ps7 { +- nvidia,pins = "kb_row15_ps7"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row3_pr3 { +- nvidia,pins = "kb_row3_pr3"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row13_ps5 { +- nvidia,pins = "kb_row13_ps5"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_wp_n_pc7 { +- nvidia,pins = "gmi_wp_n_pc7", +- "gmi_wait_pi7", +- "gmi_cs4_n_pk2", +- "gmi_cs3_n_pk4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_cs6_n_pi3 { +- nvidia,pins = "gmi_cs6_n_pi3"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- }; +- }; +- +- i2c@7000c500 { +- nfc@28 { +- compatible = "nxp,pn544-i2c"; +- reg = <0x28>; +- clock-frequency = <100000>; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- enable-gpios = <&gpio TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>; +- firmware-gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-tilapia-E1565.dts b/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-tilapia-E1565.dts +deleted file mode 100644 +index f1c63feb4af9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-tilapia-E1565.dts ++++ /dev/null +@@ -1,9 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "tegra30-asus-nexus7-grouper-maxim-pmic.dtsi" +-#include "tegra30-asus-nexus7-tilapia.dtsi" +- +-/ { +- model = "ASUS Google Nexus 7 (Project Bach / ME370TG) E1565"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-tilapia-memory-timings.dtsi b/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-tilapia-memory-timings.dtsi +deleted file mode 100644 +index 9169de34fa00..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-tilapia-memory-timings.dtsi ++++ /dev/null +@@ -1,325 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include "tegra30-asus-nexus7-grouper-memory-timings.dtsi" +- +-/ { +- /* +- * Tilapia's memory timings are pretty much the same as the Grouper's +- * ones. There are few minor tunings made for a higher clock rates, +- * these differentiating timings are overridden here for Tilapia. +- */ +- +- memory-controller@7000f400 { +- emc-timings-0 { +- timing-667000000 { +- clock-frequency = <667000000>; +- +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200018>; +- nvidia,emc-mode-reset = <0x80000b71>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-periodic-qrst; +- +- nvidia,emc-configuration = < +- 0x0000001f /* EMC_RC */ +- 0x00000069 /* EMC_RFC */ +- 0x00000017 /* EMC_RAS */ +- 0x00000007 /* EMC_RP */ +- 0x00000005 /* EMC_R2W */ +- 0x0000000c /* EMC_W2R */ +- 0x00000003 /* EMC_R2P */ +- 0x00000011 /* EMC_W2P */ +- 0x00000007 /* EMC_RD_RCD */ +- 0x00000007 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000007 /* EMC_WDV */ +- 0x0000000b /* EMC_QUSE */ +- 0x00000009 /* EMC_QRST */ +- 0x0000000b /* EMC_QSAFE */ +- 0x00000011 /* EMC_RDV */ +- 0x00001412 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x0000000e /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x0000000c /* EMC_AR2PDEN */ +- 0x00000016 /* EMC_RW2PDEN */ +- 0x00000072 /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000005 /* EMC_TCKE */ +- 0x00000015 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000006 /* EMC_TCLKSTABLE */ +- 0x00000007 /* EMC_TCLKSTOP */ +- 0x00001453 /* EMC_TREFBW */ +- 0x0000000c /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00005088 /* EMC_FBIO_CFG5 */ +- 0xf00b0191 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00000008 /* EMC_DLL_XFORM_DQS0 */ +- 0x00000008 /* EMC_DLL_XFORM_DQS1 */ +- 0x00000008 /* EMC_DLL_XFORM_DQS2 */ +- 0x00000008 /* EMC_DLL_XFORM_DQS3 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS4 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS5 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS6 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x0000000c /* EMC_DLL_XFORM_DQ0 */ +- 0x0000000c /* EMC_DLL_XFORM_DQ1 */ +- 0x0000000c /* EMC_DLL_XFORM_DQ2 */ +- 0x0000000c /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800013d /* EMC_XM2DQSPADCTRL2 */ +- 0x22220000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f501 /* EMC_XM2COMPPADCTRL */ +- 0x07077404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x080001e8 /* EMC_XM2QUSEPADCTRL */ +- 0x08000021 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00020000 /* EMC_ZCAL_INTERVAL */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x0156000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff49 /* EMC_CFG_RSV */ +- >; +- }; +- }; +- +- emc-timings-1 { +- timing-333500000 { +- clock-frequency = <333500000>; +- +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200000>; +- nvidia,emc-mode-reset = <0x80000321>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- +- nvidia,emc-configuration = < +- 0x0000000f /* EMC_RC */ +- 0x00000034 /* EMC_RFC */ +- 0x0000000a /* EMC_RAS */ +- 0x00000003 /* EMC_RP */ +- 0x00000003 /* EMC_R2W */ +- 0x00000008 /* EMC_W2R */ +- 0x00000002 /* EMC_R2P */ +- 0x00000009 /* EMC_W2P */ +- 0x00000003 /* EMC_RD_RCD */ +- 0x00000003 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000004 /* EMC_WDV */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000c /* EMC_RDV */ +- 0x000009e9 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x0000027a /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000001 /* EMC_PDEX2WR */ +- 0x00000008 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000e /* EMC_RW2PDEN */ +- 0x00000039 /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x0000000a /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000a2a /* EMC_TREFBW */ +- 0x00000000 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00007088 /* EMC_FBIO_CFG5 */ +- 0x002600a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00014000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00014000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00014000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00014000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800013d /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f508 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x080001e8 /* EMC_XM2QUSEPADCTRL */ +- 0x08000021 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00020000 /* EMC_ZCAL_INTERVAL */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x018b000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x800014d4 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff89 /* EMC_CFG_RSV */ +- >; +- }; +- +- timing-667000000 { +- clock-frequency = <667000000>; +- +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200018>; +- nvidia,emc-mode-reset = <0x80000b71>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-periodic-qrst; +- +- nvidia,emc-configuration = < +- 0x00000020 /* EMC_RC */ +- 0x0000006a /* EMC_RFC */ +- 0x00000017 /* EMC_RAS */ +- 0x00000007 /* EMC_RP */ +- 0x00000005 /* EMC_R2W */ +- 0x0000000c /* EMC_W2R */ +- 0x00000003 /* EMC_R2P */ +- 0x00000011 /* EMC_W2P */ +- 0x00000007 /* EMC_RD_RCD */ +- 0x00000007 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000007 /* EMC_WDV */ +- 0x0000000a /* EMC_QUSE */ +- 0x00000009 /* EMC_QRST */ +- 0x0000000b /* EMC_QSAFE */ +- 0x00000011 /* EMC_RDV */ +- 0x00001412 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x0000000e /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x0000000c /* EMC_AR2PDEN */ +- 0x00000016 /* EMC_RW2PDEN */ +- 0x00000072 /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000005 /* EMC_TCKE */ +- 0x00000015 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000006 /* EMC_TCLKSTABLE */ +- 0x00000007 /* EMC_TCLKSTOP */ +- 0x00001453 /* EMC_TREFBW */ +- 0x0000000b /* EMC_QUSE_EXTRA */ +- 0x00000006 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00005088 /* EMC_FBIO_CFG5 */ +- 0xf00b0191 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00000008 /* EMC_DLL_XFORM_DQS0 */ +- 0x00000008 /* EMC_DLL_XFORM_DQS1 */ +- 0x00000008 /* EMC_DLL_XFORM_DQS2 */ +- 0x00000008 /* EMC_DLL_XFORM_DQS3 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS4 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS5 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS6 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS7 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ0 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ1 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ2 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800013d /* EMC_XM2DQSPADCTRL2 */ +- 0x22220000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f501 /* EMC_XM2COMPPADCTRL */ +- 0x07077404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x080001e8 /* EMC_XM2QUSEPADCTRL */ +- 0x0c000021 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00020000 /* EMC_ZCAL_INTERVAL */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x0155000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff49 /* EMC_CFG_RSV */ +- >; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-tilapia.dtsi b/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-tilapia.dtsi +deleted file mode 100644 +index a681ad51fddd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-asus-nexus7-tilapia.dtsi ++++ /dev/null +@@ -1,235 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include "tegra30-asus-nexus7-grouper-common.dtsi" +-#include "tegra30-asus-nexus7-tilapia-memory-timings.dtsi" +- +-/ { +- compatible = "asus,tilapia", "asus,grouper", "nvidia,tegra30"; +- +- display-panel { +- enable-gpios = <&gpio TEGRA_GPIO(V, 6) GPIO_ACTIVE_HIGH>; +- +- panel-timing { +- clock-frequency = <81750000>; +- hactive = <800>; +- vactive = <1280>; +- hfront-porch = <64>; +- hback-porch = <128>; +- hsync-len = <64>; +- vsync-len = <1>; +- vfront-porch = <5>; +- vback-porch = <2>; +- }; +- }; +- +- gpio@6000d000 { +- init-mode-3g-hog { +- gpio-hog; +- gpios = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- output-low; +- }; +- }; +- +- pinmux@70000868 { +- state_default: pinmux { +- lcd_dc1_pd2 { +- nvidia,pins = "lcd_dc1_pd2"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_pwr2_pc6 { +- nvidia,pins = "lcd_pwr2_pc6"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi2_cs2_n_pw3 { +- nvidia,pins = "spi2_cs2_n_pw3"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_din_pp1 { +- nvidia,pins = "dap3_din_pp1"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi1_sck_px5 { +- nvidia,pins = "spi1_sck_px5"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu5 { +- nvidia,pins = "pu5"; +- nvidia,function = "pwm2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi1_miso_px7 { +- nvidia,pins = "spi1_miso_px7"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi2_mosi_px0 { +- nvidia,pins = "spi2_mosi_px0"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3_req_pee1 { +- nvidia,pins = "clk3_req_pee1"; +- nvidia,function = "dev3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_nxt_py2 { +- nvidia,pins = "ulpi_nxt_py2"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_stp_py3 { +- nvidia,pins = "ulpi_stp_py3"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row7_pr7 { +- nvidia,pins = "kb_row7_pr7"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu4 { +- nvidia,pins = "pu4"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu3 { +- nvidia,pins = "pu3"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row15_ps7 { +- nvidia,pins = "kb_row15_ps7"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_sclk_pp3 { +- nvidia,pins = "dap3_sclk_pp3"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row3_pr3 { +- nvidia,pins = "kb_row3_pr3", +- "kb_row13_ps5"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row13_ps5 { +- nvidia,pins = "kb_row13_ps5"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_wp_n_pc7 { +- nvidia,pins = "gmi_wp_n_pc7", +- "gmi_wait_pi7", +- "gmi_cs4_n_pk2", +- "gmi_cs3_n_pk4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_cs6_n_pi3 { +- nvidia,pins = "gmi_cs6_n_pi3"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- }; +- }; +- +- i2c@7000c500 { +- proximity-sensor@28 { +- compatible = "microchip,cap1106"; +- reg = <0x28>; +- +- /* +- * Binding doesn't support specifying linux,input-type +- * and this results in unwanted key-presses handled by +- * applications, hence keep it disabled for now. +- */ +- status = "disabled"; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- linux,keycodes = , +- , +- , +- , +- , +- ; +- }; +- +- nfc@2a { +- compatible = "nxp,pn544-i2c"; +- reg = <0x2a>; +- +- clock-frequency = <100000>; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- enable-gpios = <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>; +- firmware-gpios = <&gpio TEGRA_GPIO(P, 3) GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-beaver.dts b/scripts/dtc/include-prefixes/arm/tegra30-beaver.dts +deleted file mode 100644 +index e159feeedef7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-beaver.dts ++++ /dev/null +@@ -1,2136 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "tegra30.dtsi" +-#include "tegra30-cpu-opp.dtsi" +-#include "tegra30-cpu-opp-microvolt.dtsi" +- +-/ { +- model = "NVIDIA Tegra30 Beaver evaluation board"; +- compatible = "nvidia,beaver", "nvidia,tegra30"; +- +- aliases { +- rtc0 = "/i2c@7000d000/tps65911@2d"; +- rtc1 = "/rtc@7000e000"; +- serial0 = &uarta; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x7ff00000>; +- }; +- +- pcie@3000 { +- status = "okay"; +- +- avdd-pexa-supply = <&ldo1_reg>; +- vdd-pexa-supply = <&ldo1_reg>; +- avdd-pexb-supply = <&ldo1_reg>; +- vdd-pexb-supply = <&ldo1_reg>; +- avdd-pex-pll-supply = <&ldo1_reg>; +- avdd-plle-supply = <&ldo1_reg>; +- vddio-pex-ctl-supply = <&sys_3v3_reg>; +- hvdd-pex-supply = <&sys_3v3_pexs_reg>; +- +- pci@1,0 { +- status = "okay"; +- nvidia,num-lanes = <2>; +- }; +- +- pci@2,0 { +- nvidia,num-lanes = <2>; +- }; +- +- pci@3,0 { +- status = "okay"; +- nvidia,num-lanes = <2>; +- }; +- }; +- +- host1x@50000000 { +- hdmi@54280000 { +- status = "okay"; +- +- hdmi-supply = <&vdd_5v0_hdmi>; +- vdd-supply = <&sys_3v3_reg>; +- pll-supply = <&vio_reg>; +- +- nvidia,hpd-gpio = +- <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; +- nvidia,ddc-i2c-bus = <&hdmiddc>; +- }; +- }; +- +- pinmux@70000868 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- clk_32k_out_pa0 { +- nvidia,pins = "clk_32k_out_pa0"; +- nvidia,function = "blink"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_cts_n_pa1 { +- nvidia,pins = "uart3_cts_n_pa1"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_fs_pa2 { +- nvidia,pins = "dap2_fs_pa2"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_sclk_pa3 { +- nvidia,pins = "dap2_sclk_pa3"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_din_pa4 { +- nvidia,pins = "dap2_din_pa4"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_dout_pa5 { +- nvidia,pins = "dap2_dout_pa5"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_clk_pa6 { +- nvidia,pins = "sdmmc3_clk_pa6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_cmd_pa7 { +- nvidia,pins = "sdmmc3_cmd_pa7"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_a17_pb0 { +- nvidia,pins = "gmi_a17_pb0"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_a18_pb1 { +- nvidia,pins = "gmi_a18_pb1"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_pwr0_pb2 { +- nvidia,pins = "lcd_pwr0_pb2"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_pclk_pb3 { +- nvidia,pins = "lcd_pclk_pb3"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat3_pb4 { +- nvidia,pins = "sdmmc3_dat3_pb4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat2_pb5 { +- nvidia,pins = "sdmmc3_dat2_pb5"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat1_pb6 { +- nvidia,pins = "sdmmc3_dat1_pb6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat0_pb7 { +- nvidia,pins = "sdmmc3_dat0_pb7"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_rts_n_pc0 { +- nvidia,pins = "uart3_rts_n_pc0"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_pwr1_pc1 { +- nvidia,pins = "lcd_pwr1_pc1"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_txd_pc2 { +- nvidia,pins = "uart2_txd_pc2"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_rxd_pc3 { +- nvidia,pins = "uart2_rxd_pc3"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gen1_i2c_scl_pc4 { +- nvidia,pins = "gen1_i2c_scl_pc4"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen1_i2c_sda_pc5 { +- nvidia,pins = "gen1_i2c_sda_pc5"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_pwr2_pc6 { +- nvidia,pins = "lcd_pwr2_pc6"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_wp_n_pc7 { +- nvidia,pins = "gmi_wp_n_pc7"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat5_pd0 { +- nvidia,pins = "sdmmc3_dat5_pd0"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat4_pd1 { +- nvidia,pins = "sdmmc3_dat4_pd1"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_dc1_pd2 { +- nvidia,pins = "lcd_dc1_pd2"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat6_pd3 { +- nvidia,pins = "sdmmc3_dat6_pd3"; +- nvidia,function = "spdif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat7_pd4 { +- nvidia,pins = "sdmmc3_dat7_pd4"; +- nvidia,function = "spdif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d1_pd5 { +- nvidia,pins = "vi_d1_pd5"; +- nvidia,function = "sdmmc2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_vsync_pd6 { +- nvidia,pins = "vi_vsync_pd6"; +- nvidia,function = "ddr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_hsync_pd7 { +- nvidia,pins = "vi_hsync_pd7"; +- nvidia,function = "ddr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d0_pe0 { +- nvidia,pins = "lcd_d0_pe0"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d1_pe1 { +- nvidia,pins = "lcd_d1_pe1"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d2_pe2 { +- nvidia,pins = "lcd_d2_pe2"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d3_pe3 { +- nvidia,pins = "lcd_d3_pe3"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d4_pe4 { +- nvidia,pins = "lcd_d4_pe4"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d5_pe5 { +- nvidia,pins = "lcd_d5_pe5"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d6_pe6 { +- nvidia,pins = "lcd_d6_pe6"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d7_pe7 { +- nvidia,pins = "lcd_d7_pe7"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d8_pf0 { +- nvidia,pins = "lcd_d8_pf0"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d9_pf1 { +- nvidia,pins = "lcd_d9_pf1"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d10_pf2 { +- nvidia,pins = "lcd_d10_pf2"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d11_pf3 { +- nvidia,pins = "lcd_d11_pf3"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d12_pf4 { +- nvidia,pins = "lcd_d12_pf4"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d13_pf5 { +- nvidia,pins = "lcd_d13_pf5"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d14_pf6 { +- nvidia,pins = "lcd_d14_pf6"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d15_pf7 { +- nvidia,pins = "lcd_d15_pf7"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad0_pg0 { +- nvidia,pins = "gmi_ad0_pg0"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad1_pg1 { +- nvidia,pins = "gmi_ad1_pg1"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad2_pg2 { +- nvidia,pins = "gmi_ad2_pg2"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad3_pg3 { +- nvidia,pins = "gmi_ad3_pg3"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad4_pg4 { +- nvidia,pins = "gmi_ad4_pg4"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad5_pg5 { +- nvidia,pins = "gmi_ad5_pg5"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad6_pg6 { +- nvidia,pins = "gmi_ad6_pg6"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad7_pg7 { +- nvidia,pins = "gmi_ad7_pg7"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad8_ph0 { +- nvidia,pins = "gmi_ad8_ph0"; +- nvidia,function = "pwm0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad9_ph1 { +- nvidia,pins = "gmi_ad9_ph1"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad10_ph2 { +- nvidia,pins = "gmi_ad10_ph2"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad11_ph3 { +- nvidia,pins = "gmi_ad11_ph3"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad12_ph4 { +- nvidia,pins = "gmi_ad12_ph4"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad13_ph5 { +- nvidia,pins = "gmi_ad13_ph5"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad14_ph6 { +- nvidia,pins = "gmi_ad14_ph6"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_wr_n_pi0 { +- nvidia,pins = "gmi_wr_n_pi0"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_oe_n_pi1 { +- nvidia,pins = "gmi_oe_n_pi1"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_dqs_pi2 { +- nvidia,pins = "gmi_dqs_pi2"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_iordy_pi5 { +- nvidia,pins = "gmi_iordy_pi5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_cs7_n_pi6 { +- nvidia,pins = "gmi_cs7_n_pi6"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_wait_pi7 { +- nvidia,pins = "gmi_wait_pi7"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_de_pj1 { +- nvidia,pins = "lcd_de_pj1"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_hsync_pj3 { +- nvidia,pins = "lcd_hsync_pj3"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_vsync_pj4 { +- nvidia,pins = "lcd_vsync_pj4"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_cts_n_pj5 { +- nvidia,pins = "uart2_cts_n_pj5"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_rts_n_pj6 { +- nvidia,pins = "uart2_rts_n_pj6"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_a16_pj7 { +- nvidia,pins = "gmi_a16_pj7"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_adv_n_pk0 { +- nvidia,pins = "gmi_adv_n_pk0"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_clk_pk1 { +- nvidia,pins = "gmi_clk_pk1"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_cs2_n_pk3 { +- nvidia,pins = "gmi_cs2_n_pk3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_cs3_n_pk4 { +- nvidia,pins = "gmi_cs3_n_pk4"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spdif_out_pk5 { +- nvidia,pins = "spdif_out_pk5"; +- nvidia,function = "spdif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spdif_in_pk6 { +- nvidia,pins = "spdif_in_pk6"; +- nvidia,function = "spdif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_a19_pk7 { +- nvidia,pins = "gmi_a19_pk7"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d2_pl0 { +- nvidia,pins = "vi_d2_pl0"; +- nvidia,function = "sdmmc2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d3_pl1 { +- nvidia,pins = "vi_d3_pl1"; +- nvidia,function = "sdmmc2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d4_pl2 { +- nvidia,pins = "vi_d4_pl2"; +- nvidia,function = "vi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d5_pl3 { +- nvidia,pins = "vi_d5_pl3"; +- nvidia,function = "sdmmc2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d6_pl4 { +- nvidia,pins = "vi_d6_pl4"; +- nvidia,function = "vi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d7_pl5 { +- nvidia,pins = "vi_d7_pl5"; +- nvidia,function = "sdmmc2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d8_pl6 { +- nvidia,pins = "vi_d8_pl6"; +- nvidia,function = "sdmmc2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d9_pl7 { +- nvidia,pins = "vi_d9_pl7"; +- nvidia,function = "sdmmc2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d16_pm0 { +- nvidia,pins = "lcd_d16_pm0"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d17_pm1 { +- nvidia,pins = "lcd_d17_pm1"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d18_pm2 { +- nvidia,pins = "lcd_d18_pm2"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d19_pm3 { +- nvidia,pins = "lcd_d19_pm3"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d20_pm4 { +- nvidia,pins = "lcd_d20_pm4"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d21_pm5 { +- nvidia,pins = "lcd_d21_pm5"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d22_pm6 { +- nvidia,pins = "lcd_d22_pm6"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d23_pm7 { +- nvidia,pins = "lcd_d23_pm7"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_fs_pn0 { +- nvidia,pins = "dap1_fs_pn0"; +- nvidia,function = "i2s0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_din_pn1 { +- nvidia,pins = "dap1_din_pn1"; +- nvidia,function = "i2s0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_dout_pn2 { +- nvidia,pins = "dap1_dout_pn2"; +- nvidia,function = "i2s0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_sclk_pn3 { +- nvidia,pins = "dap1_sclk_pn3"; +- nvidia,function = "i2s0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_cs0_n_pn4 { +- nvidia,pins = "lcd_cs0_n_pn4"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_sdout_pn5 { +- nvidia,pins = "lcd_sdout_pn5"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_dc0_pn6 { +- nvidia,pins = "lcd_dc0_pn6"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- hdmi_int_pn7 { +- nvidia,pins = "hdmi_int_pn7"; +- nvidia,function = "hdmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data7_po0 { +- nvidia,pins = "ulpi_data7_po0"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data0_po1 { +- nvidia,pins = "ulpi_data0_po1"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data1_po2 { +- nvidia,pins = "ulpi_data1_po2"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data2_po3 { +- nvidia,pins = "ulpi_data2_po3"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data3_po4 { +- nvidia,pins = "ulpi_data3_po4"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data4_po5 { +- nvidia,pins = "ulpi_data4_po5"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data5_po6 { +- nvidia,pins = "ulpi_data5_po6"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data6_po7 { +- nvidia,pins = "ulpi_data6_po7"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_fs_pp0 { +- nvidia,pins = "dap3_fs_pp0"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_din_pp1 { +- nvidia,pins = "dap3_din_pp1"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_dout_pp2 { +- nvidia,pins = "dap3_dout_pp2"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_sclk_pp3 { +- nvidia,pins = "dap3_sclk_pp3"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_fs_pp4 { +- nvidia,pins = "dap4_fs_pp4"; +- nvidia,function = "i2s3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_din_pp5 { +- nvidia,pins = "dap4_din_pp5"; +- nvidia,function = "i2s3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_dout_pp6 { +- nvidia,pins = "dap4_dout_pp6"; +- nvidia,function = "i2s3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_sclk_pp7 { +- nvidia,pins = "dap4_sclk_pp7"; +- nvidia,function = "i2s3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col0_pq0 { +- nvidia,pins = "kb_col0_pq0"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col1_pq1 { +- nvidia,pins = "kb_col1_pq1"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col2_pq2 { +- nvidia,pins = "kb_col2_pq2"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col3_pq3 { +- nvidia,pins = "kb_col3_pq3"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col4_pq4 { +- nvidia,pins = "kb_col4_pq4"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col5_pq5 { +- nvidia,pins = "kb_col5_pq5"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col6_pq6 { +- nvidia,pins = "kb_col6_pq6"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col7_pq7 { +- nvidia,pins = "kb_col7_pq7"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row0_pr0 { +- nvidia,pins = "kb_row0_pr0"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row1_pr1 { +- nvidia,pins = "kb_row1_pr1"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row2_pr2 { +- nvidia,pins = "kb_row2_pr2"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row3_pr3 { +- nvidia,pins = "kb_row3_pr3"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row4_pr4 { +- nvidia,pins = "kb_row4_pr4"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row5_pr5 { +- nvidia,pins = "kb_row5_pr5"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row6_pr6 { +- nvidia,pins = "kb_row6_pr6"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row7_pr7 { +- nvidia,pins = "kb_row7_pr7"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row8_ps0 { +- nvidia,pins = "kb_row8_ps0"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row9_ps1 { +- nvidia,pins = "kb_row9_ps1"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row10_ps2 { +- nvidia,pins = "kb_row10_ps2"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row11_ps3 { +- nvidia,pins = "kb_row11_ps3"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row12_ps4 { +- nvidia,pins = "kb_row12_ps4"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row13_ps5 { +- nvidia,pins = "kb_row13_ps5"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row14_ps6 { +- nvidia,pins = "kb_row14_ps6"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row15_ps7 { +- nvidia,pins = "kb_row15_ps7"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_pclk_pt0 { +- nvidia,pins = "vi_pclk_pt0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_mclk_pt1 { +- nvidia,pins = "vi_mclk_pt1"; +- nvidia,function = "vi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d10_pt2 { +- nvidia,pins = "vi_d10_pt2"; +- nvidia,function = "ddr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d11_pt3 { +- nvidia,pins = "vi_d11_pt3"; +- nvidia,function = "ddr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d0_pt4 { +- nvidia,pins = "vi_d0_pt4"; +- nvidia,function = "ddr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gen2_i2c_scl_pt5 { +- nvidia,pins = "gen2_i2c_scl_pt5"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen2_i2c_sda_pt6 { +- nvidia,pins = "gen2_i2c_sda_pt6"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc4_cmd_pt7 { +- nvidia,pins = "sdmmc4_cmd_pt7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu0 { +- nvidia,pins = "pu0"; +- nvidia,function = "owr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu1 { +- nvidia,pins = "pu1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu2 { +- nvidia,pins = "pu2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu3 { +- nvidia,pins = "pu3"; +- nvidia,function = "pwm0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu4 { +- nvidia,pins = "pu4"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu5 { +- nvidia,pins = "pu5"; +- nvidia,function = "pwm2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu6 { +- nvidia,pins = "pu6"; +- nvidia,function = "pwm3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- jtag_rtck_pu7 { +- nvidia,pins = "jtag_rtck_pu7"; +- nvidia,function = "rtck"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv0 { +- nvidia,pins = "pv0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv2 { +- nvidia,pins = "pv2"; +- nvidia,function = "owr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv3 { +- nvidia,pins = "pv3"; +- nvidia,function = "clk_12m_out"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ddc_scl_pv4 { +- nvidia,pins = "ddc_scl_pv4"; +- nvidia,function = "i2c4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ddc_sda_pv5 { +- nvidia,pins = "ddc_sda_pv5"; +- nvidia,function = "i2c4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- crt_hsync_pv6 { +- nvidia,pins = "crt_hsync_pv6"; +- nvidia,function = "crt"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- crt_vsync_pv7 { +- nvidia,pins = "crt_vsync_pv7"; +- nvidia,function = "crt"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_cs1_n_pw0 { +- nvidia,pins = "lcd_cs1_n_pw0"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_m1_pw1 { +- nvidia,pins = "lcd_m1_pw1"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi2_cs1_n_pw2 { +- nvidia,pins = "spi2_cs1_n_pw2"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk1_out_pw4 { +- nvidia,pins = "clk1_out_pw4"; +- nvidia,function = "extperiph1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2_out_pw5 { +- nvidia,pins = "clk2_out_pw5"; +- nvidia,function = "extperiph2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_txd_pw6 { +- nvidia,pins = "uart3_txd_pw6"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_rxd_pw7 { +- nvidia,pins = "uart3_rxd_pw7"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi2_sck_px2 { +- nvidia,pins = "spi2_sck_px2"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi1_mosi_px4 { +- nvidia,pins = "spi1_mosi_px4"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi1_sck_px5 { +- nvidia,pins = "spi1_sck_px5"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi1_cs0_n_px6 { +- nvidia,pins = "spi1_cs0_n_px6"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi1_miso_px7 { +- nvidia,pins = "spi1_miso_px7"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_clk_py0 { +- nvidia,pins = "ulpi_clk_py0"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_dir_py1 { +- nvidia,pins = "ulpi_dir_py1"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_nxt_py2 { +- nvidia,pins = "ulpi_nxt_py2"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_stp_py3 { +- nvidia,pins = "ulpi_stp_py3"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat3_py4 { +- nvidia,pins = "sdmmc1_dat3_py4"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat2_py5 { +- nvidia,pins = "sdmmc1_dat2_py5"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat1_py6 { +- nvidia,pins = "sdmmc1_dat1_py6"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat0_py7 { +- nvidia,pins = "sdmmc1_dat0_py7"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_clk_pz0 { +- nvidia,pins = "sdmmc1_clk_pz0"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_cmd_pz1 { +- nvidia,pins = "sdmmc1_cmd_pz1"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_sdin_pz2 { +- nvidia,pins = "lcd_sdin_pz2"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_wr_n_pz3 { +- nvidia,pins = "lcd_wr_n_pz3"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_sck_pz4 { +- nvidia,pins = "lcd_sck_pz4"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sys_clk_req_pz5 { +- nvidia,pins = "sys_clk_req_pz5"; +- nvidia,function = "sysclk"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pwr_i2c_scl_pz6 { +- nvidia,pins = "pwr_i2c_scl_pz6"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pwr_i2c_sda_pz7 { +- nvidia,pins = "pwr_i2c_sda_pz7"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc4_dat0_paa0 { +- nvidia,pins = "sdmmc4_dat0_paa0"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat1_paa1 { +- nvidia,pins = "sdmmc4_dat1_paa1"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat2_paa2 { +- nvidia,pins = "sdmmc4_dat2_paa2"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat3_paa3 { +- nvidia,pins = "sdmmc4_dat3_paa3"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat4_paa4 { +- nvidia,pins = "sdmmc4_dat4_paa4"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat5_paa5 { +- nvidia,pins = "sdmmc4_dat5_paa5"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat6_paa6 { +- nvidia,pins = "sdmmc4_dat6_paa6"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_dat7_paa7 { +- nvidia,pins = "sdmmc4_dat7_paa7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb0 { +- nvidia,pins = "pbb0"; +- nvidia,function = "i2s4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cam_i2c_scl_pbb1 { +- nvidia,pins = "cam_i2c_scl_pbb1"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_i2c_sda_pbb2 { +- nvidia,pins = "cam_i2c_sda_pbb2"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pbb3 { +- nvidia,pins = "pbb3"; +- nvidia,function = "vgp3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb4 { +- nvidia,pins = "pbb4"; +- nvidia,function = "vgp4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb5 { +- nvidia,pins = "pbb5"; +- nvidia,function = "vgp5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb6 { +- nvidia,pins = "pbb6"; +- nvidia,function = "vgp6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb7 { +- nvidia,pins = "pbb7"; +- nvidia,function = "i2s4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cam_mclk_pcc0 { +- nvidia,pins = "cam_mclk_pcc0"; +- nvidia,function = "vi_alt3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pcc1 { +- nvidia,pins = "pcc1"; +- nvidia,function = "i2s4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pcc2 { +- nvidia,pins = "pcc2"; +- nvidia,function = "i2s4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_rst_n_pcc3 { +- nvidia,pins = "sdmmc4_rst_n_pcc3"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_clk_pcc4 { +- nvidia,pins = "sdmmc4_clk_pcc4"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2_req_pcc5 { +- nvidia,pins = "clk2_req_pcc5"; +- nvidia,function = "dap"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l2_rst_n_pcc6 { +- nvidia,pins = "pex_l2_rst_n_pcc6"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l2_clkreq_n_pcc7 { +- nvidia,pins = "pex_l2_clkreq_n_pcc7"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l0_prsnt_n_pdd0 { +- nvidia,pins = "pex_l0_prsnt_n_pdd0"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l0_rst_n_pdd1 { +- nvidia,pins = "pex_l0_rst_n_pdd1"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l0_clkreq_n_pdd2 { +- nvidia,pins = "pex_l0_clkreq_n_pdd2"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_wake_n_pdd3 { +- nvidia,pins = "pex_wake_n_pdd3"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l1_prsnt_n_pdd4 { +- nvidia,pins = "pex_l1_prsnt_n_pdd4"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l1_rst_n_pdd5 { +- nvidia,pins = "pex_l1_rst_n_pdd5"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l1_clkreq_n_pdd6 { +- nvidia,pins = "pex_l1_clkreq_n_pdd6"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l2_prsnt_n_pdd7 { +- nvidia,pins = "pex_l2_prsnt_n_pdd7"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3_out_pee0 { +- nvidia,pins = "clk3_out_pee0"; +- nvidia,function = "extperiph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3_req_pee1 { +- nvidia,pins = "clk3_req_pee1"; +- nvidia,function = "dev3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk1_req_pee2 { +- nvidia,pins = "clk1_req_pee2"; +- nvidia,function = "dap"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- hdmi_cec_pee3 { +- nvidia,pins = "hdmi_cec_pee3"; +- nvidia,function = "cec"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- owr { +- nvidia,pins = "owr"; +- nvidia,function = "owr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdio3 { +- nvidia,pins = "drive_sdio3"; +- nvidia,high-speed-mode = ; +- nvidia,schmitt = ; +- nvidia,pull-down-strength = <46>; +- nvidia,pull-up-strength = <42>; +- nvidia,slew-rate-rising = <1>; +- nvidia,slew-rate-falling = <1>; +- }; +- gpv { +- nvidia,pins = "drive_gpv"; +- nvidia,pull-up-strength = <16>; +- }; +- }; +- }; +- +- serial@70006000 { +- status = "okay"; +- }; +- +- i2c@7000c000 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- i2c@7000c400 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- i2c@7000c500 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- hdmiddc: i2c@7000c700 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <100000>; +- +- rt5640: rt5640@1c { +- compatible = "realtek,rt5640"; +- reg = <0x1c>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- realtek,ldo1-en-gpios = +- <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; +- }; +- +- pmic: tps65911@2d { +- compatible = "ti,tps65911"; +- reg = <0x2d>; +- +- interrupts = ; +- #interrupt-cells = <2>; +- interrupt-controller; +- wakeup-source; +- +- ti,system-power-controller; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- vcc1-supply = <&vdd_5v_in_reg>; +- vcc2-supply = <&vdd_5v_in_reg>; +- vcc3-supply = <&vio_reg>; +- vcc4-supply = <&vdd_5v_in_reg>; +- vcc5-supply = <&vdd_5v_in_reg>; +- vcc6-supply = <&vdd2_reg>; +- vcc7-supply = <&vdd_5v_in_reg>; +- vccio-supply = <&vdd_5v_in_reg>; +- +- regulators { +- vdd1_reg: vdd1 { +- regulator-name = "vddio_ddr_1v2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vdd2_reg: vdd2 { +- regulator-name = "vdd_1v5_gen"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- +- vddctrl_reg: vddctrl { +- regulator-name = "vdd_cpu,vdd_sys"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1250000>; +- regulator-coupled-with = <&core_vdd_reg>; +- regulator-coupled-max-spread = <300000>; +- regulator-max-step-microvolt = <100000>; +- regulator-always-on; +- +- nvidia,tegra-cpu-regulator; +- }; +- +- vio_reg: vio { +- regulator-name = "vdd_1v8_gen"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo1_reg: ldo1 { +- regulator-name = "vdd_pexa,vdd_pexb"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- ldo2_reg: ldo2 { +- regulator-name = "vdd_sata,avdd_plle"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- /* LDO3 is not connected to anything */ +- +- ldo4_reg: ldo4 { +- regulator-name = "vdd_rtc"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo5_reg: ldo5 { +- regulator-name = "vddio_sdmmc,avdd_vdac"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo6_reg: ldo6 { +- regulator-name = "avdd_dsi_csi,pwrdet_mipi"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo7_reg: ldo7 { +- regulator-name = "vdd_pllm,x,u,a_p_c_s"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo8_reg: ldo8 { +- regulator-name = "vdd_ddr_hs"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- }; +- }; +- +- core_vdd_reg: tps62361@60 { +- compatible = "ti,tps62361"; +- reg = <0x60>; +- +- regulator-name = "tps62361-vout"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1500000>; +- regulator-coupled-with = <&vddctrl_reg>; +- regulator-coupled-max-spread = <300000>; +- regulator-max-step-microvolt = <100000>; +- regulator-boot-on; +- regulator-always-on; +- ti,vsel0-state-high; +- ti,vsel1-state-high; +- +- nvidia,tegra-core-regulator; +- }; +- }; +- +- spi@7000da00 { +- status = "okay"; +- spi-max-frequency = <25000000>; +- spi-flash@1 { +- compatible = "winbond,w25q32", "jedec,spi-nor"; +- reg = <1>; +- spi-max-frequency = <20000000>; +- }; +- }; +- +- pmc@7000e400 { +- status = "okay"; +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <2000>; +- nvidia,cpu-pwr-off-time = <200>; +- nvidia,core-pwr-good-time = <3845 3845>; +- nvidia,core-pwr-off-time = <0>; +- nvidia,core-power-req-active-high; +- nvidia,sys-clock-req-active-high; +- }; +- +- ahub@70080000 { +- i2s@70080400 { +- status = "okay"; +- }; +- }; +- +- mmc@78000000 { +- status = "okay"; +- vqmmc-supply = <&ldo5_reg>; +- cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; +- power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; +- bus-width = <4>; +- }; +- +- mmc@78000600 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- }; +- +- usb@7d000000 { +- compatible = "nvidia,tegra30-udc"; +- status = "okay"; +- dr_mode = "peripheral"; +- }; +- +- usb-phy@7d000000 { +- status = "okay"; +- }; +- +- usb@7d004000 { +- status = "okay"; +- }; +- +- phy2: usb-phy@7d004000 { +- vbus-supply = <&sys_3v3_reg>; +- status = "okay"; +- }; +- +- usb@7d008000 { +- status = "okay"; +- }; +- +- usb-phy@7d008000 { +- vbus-supply = <&usb3_vbus_reg>; +- status = "okay"; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- gpled1 { +- label = "LED1"; /* CR5A1 (blue) */ +- gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>; +- }; +- gpled2 { +- label = "LED2"; /* CR4A2 (green) */ +- gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- vdd_5v_in_reg: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_5v_in"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- chargepump_5v_reg: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "chargepump_5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- enable-active-high; +- gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; +- }; +- +- ddr_reg: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_ddr"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; +- vin-supply = <&vdd_5v_in_reg>; +- }; +- +- vdd_5v_sata_reg: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_5v_sata"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; +- vin-supply = <&vdd_5v_in_reg>; +- }; +- +- usb1_vbus_reg: regulator@4 { +- compatible = "regulator-fixed"; +- regulator-name = "usb1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; +- gpio-open-drain; +- vin-supply = <&vdd_5v_in_reg>; +- }; +- +- usb3_vbus_reg: regulator@5 { +- compatible = "regulator-fixed"; +- regulator-name = "usb3_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; +- gpio-open-drain; +- vin-supply = <&vdd_5v_in_reg>; +- }; +- +- sys_3v3_reg: regulator@6 { +- compatible = "regulator-fixed"; +- regulator-name = "sys_3v3,vdd_3v3_alw"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; +- vin-supply = <&vdd_5v_in_reg>; +- }; +- +- sys_3v3_pexs_reg: regulator@7 { +- compatible = "regulator-fixed"; +- regulator-name = "sys_3v3_pexs"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; +- vin-supply = <&sys_3v3_reg>; +- }; +- +- vdd_5v0_hdmi: regulator@8 { +- compatible = "regulator-fixed"; +- regulator-name = "+VDD_5V_HDMI"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&sys_3v3_reg>; +- }; +- +- sound { +- compatible = "nvidia,tegra-audio-rt5640-beaver", +- "nvidia,tegra-audio-rt5640"; +- nvidia,model = "NVIDIA Tegra Beaver"; +- +- nvidia,audio-routing = +- "Headphones", "HPOR", +- "Headphones", "HPOL", +- "Mic Jack", "MICBIAS1", +- "IN2P", "Mic Jack"; +- +- nvidia,i2s-controller = <&tegra_i2s1>; +- nvidia,audio-codec = <&rt5640>; +- +- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; +- +- clocks = <&tegra_car TEGRA30_CLK_PLL_A>, +- <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- +- assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- +- assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA30_CLK_EXTERN1>; +- }; +- +- cpus { +- cpu0: cpu@0 { +- cpu-supply = <&vddctrl_reg>; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- cpu@1 { +- cpu-supply = <&vddctrl_reg>; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- cpu@2 { +- cpu-supply = <&vddctrl_reg>; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- cpu@3 { +- cpu-supply = <&vddctrl_reg>; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-cardhu-a02.dts b/scripts/dtc/include-prefixes/arm/tegra30-cardhu-a02.dts +deleted file mode 100644 +index 4899e05a0d9c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-cardhu-a02.dts ++++ /dev/null +@@ -1,83 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "tegra30-cardhu.dtsi" +- +-/* This dts file support the cardhu A02 version of board */ +- +-/ { +- model = "NVIDIA Tegra30 Cardhu A02 evaluation board"; +- compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30"; +- +- mmc@78000400 { +- status = "okay"; +- power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; +- bus-width = <4>; +- keep-power-in-suspend; +- }; +- +- ddr_reg: regulator@100 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_ddr"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; +- }; +- +- sys_3v3_reg: regulator@101 { +- compatible = "regulator-fixed"; +- regulator-name = "sys_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; +- }; +- +- usb1_vbus_reg: regulator@102 { +- compatible = "regulator-fixed"; +- regulator-name = "usb1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; +- gpio-open-drain; +- vin-supply = <&vdd_5v0_reg>; +- }; +- +- usb3_vbus_reg: regulator@103 { +- compatible = "regulator-fixed"; +- regulator-name = "usb3_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; +- gpio-open-drain; +- vin-supply = <&vdd_5v0_reg>; +- }; +- +- vdd_5v0_reg: regulator@104 { +- compatible = "regulator-fixed"; +- regulator-name = "5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; +- }; +- +- vdd_bl_reg: regulator@105 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_bl"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-cardhu-a04.dts b/scripts/dtc/include-prefixes/arm/tegra30-cardhu-a04.dts +deleted file mode 100644 +index a11028b8b67b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-cardhu-a04.dts ++++ /dev/null +@@ -1,93 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "tegra30-cardhu.dtsi" +- +-/* This dts file support the cardhu A04 and later versions of board */ +- +-/ { +- model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board"; +- compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30"; +- +- mmc@78000400 { +- status = "okay"; +- power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>; +- bus-width = <4>; +- keep-power-in-suspend; +- }; +- +- ddr_reg: regulator@100 { +- compatible = "regulator-fixed"; +- regulator-name = "ddr"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; +- }; +- +- sys_3v3_reg: regulator@101 { +- compatible = "regulator-fixed"; +- regulator-name = "sys_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; +- }; +- +- usb1_vbus_reg: regulator@102 { +- compatible = "regulator-fixed"; +- regulator-name = "usb1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; +- gpio-open-drain; +- vin-supply = <&vdd_5v0_reg>; +- }; +- +- usb3_vbus_reg: regulator@103 { +- compatible = "regulator-fixed"; +- regulator-name = "usb3_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; +- gpio-open-drain; +- vin-supply = <&vdd_5v0_reg>; +- }; +- +- vdd_5v0_reg: regulator@104 { +- compatible = "regulator-fixed"; +- regulator-name = "5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; +- }; +- +- vdd_bl_reg: regulator@105 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_bl"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; +- }; +- +- vdd_bl2_reg: regulator@106 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_bl2"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-cardhu.dtsi b/scripts/dtc/include-prefixes/arm/tegra30-cardhu.dtsi +deleted file mode 100644 +index 448f1397e64a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-cardhu.dtsi ++++ /dev/null +@@ -1,708 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +-#include "tegra30.dtsi" +-#include "tegra30-cpu-opp.dtsi" +-#include "tegra30-cpu-opp-microvolt.dtsi" +- +-/** +- * This file contains common DT entry for all fab version of Cardhu. +- * There is multiple fab version of Cardhu starting from A01 to A07. +- * Cardhu fab version A01 and A03 are not supported. Cardhu fab version +- * A02 will have different sets of GPIOs for fixed regulator compare to +- * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are +- * compatible with fab version A04. Based on Cardhu fab version, the +- * related dts file need to be chosen like for Cardhu fab version A02, +- * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use +- * tegra30-cardhu-a04.dts. +- * The identification of board is done in two ways, by looking the sticker +- * on PCB and by reading board id eeprom. +- * The sticker will have number like 600-81291-1000-002 C.3. In this 4th +- * number is the fab version like here it is 002 and hence fab version A02. +- * The (downstream internal) U-Boot of Cardhu display the board-id as +- * follows: +- * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00 +- * In this Fab version is 02 i.e. A02. +- * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56). +- * The location 0x8 of this eeprom contains the Fab version. It is 1 byte +- * wide. +- */ +- +-/ { +- model = "NVIDIA Tegra30 Cardhu evaluation board"; +- compatible = "nvidia,cardhu", "nvidia,tegra30"; +- +- aliases { +- rtc0 = "/i2c@7000d000/tps65911@2d"; +- rtc1 = "/rtc@7000e000"; +- serial0 = &uarta; +- serial1 = &uartc; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x40000000>; +- }; +- +- pcie@3000 { +- status = "okay"; +- +- /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */ +- avdd-pexb-supply = <&ldo1_reg>; +- vdd-pexb-supply = <&ldo1_reg>; +- avdd-pex-pll-supply = <&ldo1_reg>; +- hvdd-pex-supply = <&pex_hvdd_3v3_reg>; +- vddio-pex-ctl-supply = <&sys_3v3_reg>; +- avdd-plle-supply = <&ldo2_reg>; +- +- pci@1,0 { +- nvidia,num-lanes = <4>; +- }; +- +- pci@2,0 { +- nvidia,num-lanes = <1>; +- }; +- +- pci@3,0 { +- status = "okay"; +- nvidia,num-lanes = <1>; +- }; +- }; +- +- host1x@50000000 { +- dc@54200000 { +- rgb { +- status = "okay"; +- +- nvidia,panel = <&panel>; +- }; +- }; +- }; +- +- pinmux@70000868 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- sdmmc1_clk_pz0 { +- nvidia,pins = "sdmmc1_clk_pz0"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- sdmmc1_cmd_pz1 { +- nvidia,pins = "sdmmc1_cmd_pz1", +- "sdmmc1_dat0_py7", +- "sdmmc1_dat1_py6", +- "sdmmc1_dat2_py5", +- "sdmmc1_dat3_py4"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- sdmmc3_clk_pa6 { +- nvidia,pins = "sdmmc3_clk_pa6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- sdmmc3_cmd_pa7 { +- nvidia,pins = "sdmmc3_cmd_pa7", +- "sdmmc3_dat0_pb7", +- "sdmmc3_dat1_pb6", +- "sdmmc3_dat2_pb5", +- "sdmmc3_dat3_pb4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- sdmmc4_clk_pcc4 { +- nvidia,pins = "sdmmc4_clk_pcc4", +- "sdmmc4_rst_n_pcc3"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- sdmmc4_dat0_paa0 { +- nvidia,pins = "sdmmc4_dat0_paa0", +- "sdmmc4_dat1_paa1", +- "sdmmc4_dat2_paa2", +- "sdmmc4_dat3_paa3", +- "sdmmc4_dat4_paa4", +- "sdmmc4_dat5_paa5", +- "sdmmc4_dat6_paa6", +- "sdmmc4_dat7_paa7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- dap2_fs_pa2 { +- nvidia,pins = "dap2_fs_pa2", +- "dap2_sclk_pa3", +- "dap2_din_pa4", +- "dap2_dout_pa5"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- sdio3 { +- nvidia,pins = "drive_sdio3"; +- nvidia,high-speed-mode = ; +- nvidia,schmitt = ; +- nvidia,pull-down-strength = <46>; +- nvidia,pull-up-strength = <42>; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- }; +- uart3_txd_pw6 { +- nvidia,pins = "uart3_txd_pw6", +- "uart3_cts_n_pa1", +- "uart3_rts_n_pc0", +- "uart3_rxd_pw7"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- }; +- }; +- +- serial@70006000 { +- status = "okay"; +- }; +- +- serial@70006200 { +- compatible = "nvidia,tegra30-hsuart"; +- status = "okay"; +- }; +- +- pwm@7000a000 { +- status = "okay"; +- }; +- +- panelddc: i2c@7000c000 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- i2c@7000c400 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- i2c@7000c500 { +- status = "okay"; +- clock-frequency = <100000>; +- +- /* ALS and Proximity sensor */ +- isl29028@44 { +- compatible = "isil,isl29028"; +- reg = <0x44>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- }; +- +- i2cmux@70 { +- compatible = "nxp,pca9546"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- reset-gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>; +- }; +- }; +- +- i2c@7000c700 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <100000>; +- +- wm8903: wm8903@1a { +- compatible = "wlf,wm8903"; +- reg = <0x1a>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- micdet-cfg = <0>; +- micdet-delay = <100>; +- gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; +- }; +- +- pmic: tps65911@2d { +- compatible = "ti,tps65911"; +- reg = <0x2d>; +- +- interrupts = ; +- #interrupt-cells = <2>; +- interrupt-controller; +- wakeup-source; +- +- ti,system-power-controller; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- vcc1-supply = <&vdd_ac_bat_reg>; +- vcc2-supply = <&vdd_ac_bat_reg>; +- vcc3-supply = <&vio_reg>; +- vcc4-supply = <&vdd_5v0_reg>; +- vcc5-supply = <&vdd_ac_bat_reg>; +- vcc6-supply = <&vdd2_reg>; +- vcc7-supply = <&vdd_ac_bat_reg>; +- vccio-supply = <&vdd_ac_bat_reg>; +- +- regulators { +- vdd1_reg: vdd1 { +- regulator-name = "vddio_ddr_1v2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vdd2_reg: vdd2 { +- regulator-name = "vdd_1v5_gen"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- +- vddctrl_reg: vddctrl { +- regulator-name = "vdd_cpu,vdd_sys"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1250000>; +- regulator-coupled-with = <&vdd_core>; +- regulator-coupled-max-spread = <300000>; +- regulator-max-step-microvolt = <100000>; +- regulator-always-on; +- +- nvidia,tegra-cpu-regulator; +- }; +- +- vio_reg: vio { +- regulator-name = "vdd_1v8_gen"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo1_reg: ldo1 { +- regulator-name = "vdd_pexa,vdd_pexb"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- ldo2_reg: ldo2 { +- regulator-name = "vdd_sata,avdd_plle"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- /* LDO3 is not connected to anything */ +- +- ldo4_reg: ldo4 { +- regulator-name = "vdd_rtc"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo5_reg: ldo5 { +- regulator-name = "vddio_sdmmc,avdd_vdac"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo6_reg: ldo6 { +- regulator-name = "avdd_dsi_csi,pwrdet_mipi"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo7_reg: ldo7 { +- regulator-name = "vdd_pllm,x,u,a_p_c_s"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo8_reg: ldo8 { +- regulator-name = "vdd_ddr_hs"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- }; +- }; +- +- nct1008: temperature-sensor@4c { +- compatible = "onnn,nct1008"; +- reg = <0x4c>; +- vcc-supply = <&sys_3v3_reg>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- #thermal-sensor-cells = <1>; +- }; +- +- vdd_core: tps62361@60 { +- compatible = "ti,tps62361"; +- reg = <0x60>; +- +- regulator-name = "tps62361-vout"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1500000>; +- regulator-coupled-with = <&vddctrl_reg>; +- regulator-coupled-max-spread = <300000>; +- regulator-max-step-microvolt = <100000>; +- regulator-boot-on; +- regulator-always-on; +- ti,vsel0-state-high; +- ti,vsel1-state-high; +- +- nvidia,tegra-core-regulator; +- }; +- }; +- +- spi@7000da00 { +- status = "okay"; +- spi-max-frequency = <25000000>; +- spi-flash@1 { +- compatible = "winbond,w25q32", "jedec,spi-nor"; +- reg = <1>; +- spi-max-frequency = <20000000>; +- }; +- }; +- +- pmc@7000e400 { +- status = "okay"; +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <2000>; +- nvidia,cpu-pwr-off-time = <200>; +- nvidia,core-pwr-good-time = <3845 3845>; +- nvidia,core-pwr-off-time = <0>; +- nvidia,core-power-req-active-high; +- nvidia,sys-clock-req-active-high; +- }; +- +- ahub@70080000 { +- i2s@70080400 { +- status = "okay"; +- }; +- }; +- +- mmc@78000000 { +- status = "okay"; +- cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; +- power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; +- bus-width = <4>; +- }; +- +- mmc@78000600 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- }; +- +- usb@7d008000 { +- status = "okay"; +- }; +- +- usb-phy@7d008000 { +- vbus-supply = <&usb3_vbus_reg>; +- status = "okay"; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- +- enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; +- power-supply = <&vdd_bl_reg>; +- pwms = <&pwm 0 5000000>; +- +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- cpus { +- cpu0: cpu@0 { +- cpu-supply = <&vddctrl_reg>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- cpu-supply = <&vddctrl_reg>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- cpu-supply = <&vddctrl_reg>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- cpu-supply = <&vddctrl_reg>; +- operating-points-v2 = <&cpu0_opp_table>; +- #cooling-cells = <2>; +- }; +- }; +- +- panel: panel { +- compatible = "chunghwa,claa101wb01"; +- ddc-i2c-bus = <&panelddc>; +- +- power-supply = <&vdd_pnl1_reg>; +- enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>; +- +- backlight = <&backlight>; +- }; +- +- vdd_ac_bat_reg: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_ac_bat"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- cam_1v8_reg: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "cam_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; +- vin-supply = <&vio_reg>; +- }; +- +- cp_5v_reg: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "cp_5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- enable-active-high; +- gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; +- }; +- +- emmc_3v3_reg: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "emmc_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>; +- vin-supply = <&sys_3v3_reg>; +- }; +- +- modem_3v3_reg: regulator@4 { +- compatible = "regulator-fixed"; +- regulator-name = "modem_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; +- }; +- +- pex_hvdd_3v3_reg: regulator@5 { +- compatible = "regulator-fixed"; +- regulator-name = "pex_hvdd_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; +- vin-supply = <&sys_3v3_reg>; +- }; +- +- vdd_cam1_ldo_reg: regulator@6 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_cam1_ldo"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>; +- vin-supply = <&sys_3v3_reg>; +- }; +- +- vdd_cam2_ldo_reg: regulator@7 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_cam2_ldo"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; +- vin-supply = <&sys_3v3_reg>; +- }; +- +- vdd_cam3_ldo_reg: regulator@8 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_cam3_ldo"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; +- vin-supply = <&sys_3v3_reg>; +- }; +- +- vdd_com_reg: regulator@9 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_com"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; +- vin-supply = <&sys_3v3_reg>; +- }; +- +- vdd_fuse_3v3_reg: regulator@10 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_fuse_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; +- vin-supply = <&sys_3v3_reg>; +- }; +- +- vdd_pnl1_reg: regulator@11 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_pnl1"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>; +- vin-supply = <&sys_3v3_reg>; +- }; +- +- vdd_vid_reg: regulator@12 { +- compatible = "regulator-fixed"; +- regulator-name = "vddio_vid"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; +- gpio-open-drain; +- vin-supply = <&vdd_5v0_reg>; +- }; +- +- sound { +- compatible = "nvidia,tegra-audio-wm8903-cardhu", +- "nvidia,tegra-audio-wm8903"; +- nvidia,model = "NVIDIA Tegra Cardhu"; +- +- nvidia,audio-routing = +- "Headphone Jack", "HPOUTR", +- "Headphone Jack", "HPOUTL", +- "Int Spk", "ROP", +- "Int Spk", "RON", +- "Int Spk", "LOP", +- "Int Spk", "LON", +- "Mic Jack", "MICBIAS", +- "IN1L", "Mic Jack"; +- +- nvidia,i2s-controller = <&tegra_i2s1>; +- nvidia,audio-codec = <&wm8903>; +- +- nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; +- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) +- GPIO_ACTIVE_LOW>; +- +- clocks = <&tegra_car TEGRA30_CLK_PLL_A>, +- <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- +- assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- +- assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA30_CLK_EXTERN1>; +- }; +- +- thermal-zones { +- cpu-thermal { +- polling-delay-passive = <1000>; /* milliseconds */ +- polling-delay = <5000>; /* milliseconds */ +- +- thermal-sensors = <&nct1008 1>; +- +- trips { +- trip0: cpu-alert0 { +- /* throttle at 57C until temperature drops to 56.8C */ +- temperature = <57000>; +- hysteresis = <200>; +- type = "passive"; +- }; +- +- trip1: cpu-crit { +- /* shut down at 60C */ +- temperature = <60000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&trip0>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "Power"; +- interrupt-parent = <&pmic>; +- interrupts = <2 0>; +- linux,code = ; +- debounce-interval = <100>; +- wakeup-source; +- }; +- +- volume-down { +- label = "Volume Down"; +- gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <10>; +- }; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <10>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-colibri-eval-v3.dts b/scripts/dtc/include-prefixes/arm/tegra30-colibri-eval-v3.dts +deleted file mode 100644 +index 7d4a6ca4936a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-colibri-eval-v3.dts ++++ /dev/null +@@ -1,198 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include "tegra30-colibri.dtsi" +- +-/ { +- model = "Toradex Colibri T30 on Colibri Evaluation Board"; +- compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30", +- "nvidia,tegra30"; +- +- aliases { +- rtc0 = "/i2c@7000c000/rtc@68"; +- rtc1 = "/i2c@7000d000/pmic@2d"; +- rtc2 = "/rtc@7000e000"; +- serial0 = &uarta; +- serial1 = &uartb; +- serial2 = &uartd; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- host1x@50000000 { +- dc@54200000 { +- rgb { +- status = "okay"; +- nvidia,panel = <&panel>; +- }; +- }; +- +- hdmi@54280000 { +- status = "okay"; +- hdmi-supply = <®_5v0>; +- }; +- }; +- +- /* Colibri UART-A */ +- serial@70006000 { +- status = "okay"; +- }; +- +- /* Colibri UART-C */ +- serial@70006040 { +- status = "okay"; +- }; +- +- /* Colibri UART-B */ +- serial@70006300 { +- status = "okay"; +- }; +- +- pwm@7000a000 { +- status = "okay"; +- }; +- +- /* +- * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier +- * board) +- */ +- i2c@7000c000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- /* M41T0M6 real time clock on carrier board */ +- rtc@68 { +- compatible = "st,m41t0"; +- reg = <0x68>; +- }; +- }; +- +- /* GEN2_I2C: unused */ +- +- /* CAM_I2C (I2C3): unused */ +- +- /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ +- i2c@7000c700 { +- status = "okay"; +- }; +- +- /* SPI1: Colibri SSP */ +- spi@7000d400 { +- status = "okay"; +- spi-max-frequency = <25000000>; +- +- can@0 { +- compatible = "microchip,mcp2515"; +- reg = <0>; +- clocks = <&clk16m>; +- interrupt-parent = <&gpio>; +- /* CAN_INT */ +- interrupts = ; +- spi-max-frequency = <10000000>; +- vdd-supply = <®_3v3>; +- xceiver-supply = <®_5v0>; +- }; +- }; +- +- /* SD/MMC */ +- mmc@78000200 { +- status = "okay"; +- bus-width = <4>; +- cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ +- no-1-8-v; +- }; +- +- /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ +- usb@7d000000 { +- status = "okay"; +- dr_mode = "otg"; +- }; +- +- usb-phy@7d000000 { +- status = "okay"; +- vbus-supply = <®_usbc_vbus>; +- }; +- +- /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ +- usb@7d008000 { +- status = "okay"; +- }; +- +- usb-phy@7d008000 { +- status = "okay"; +- vbus-supply = <®_usbh_vbus>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- brightness-levels = <255 128 64 32 16 8 4 0>; +- default-brightness-level = <6>; +- /* BL_ON */ +- enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; +- power-supply = <®_3v3>; +- pwms = <&pwm 0 5000000>; /* PWM */ +- }; +- +- clk16m: osc3 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <16000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- wakeup { +- label = "SODIMM pin 45 wakeup"; +- gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- panel: panel { +- /* +- * edt,et057090dhu: EDT 5.7" LCD TFT +- * edt,et070080dh6: EDT 7.0" LCD TFT +- */ +- compatible = "edt,et057090dhu"; +- backlight = <&backlight>; +- power-supply = <®_3v3>; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3.3V_SW"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_5v0: regulator-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "5V_SW"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usbc_vbus: regulator-usbc-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_USB5"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <®_5v0>; +- }; +- +- /* USBH_PEN resp. USB_P_EN */ +- reg_usbh_vbus: regulator-usbh-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_USB[1-4]"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; +- vin-supply = <®_5v0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-colibri.dtsi b/scripts/dtc/include-prefixes/arm/tegra30-colibri.dtsi +deleted file mode 100644 +index 413e35215804..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-colibri.dtsi ++++ /dev/null +@@ -1,1053 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "tegra30.dtsi" +- +-/* +- * Toradex Colibri T30 Module Device Tree +- * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E, V1.1F; IT: V1.1A, V1.1B +- */ +-/ { +- memory@80000000 { +- reg = <0x80000000 0x40000000>; +- }; +- +- host1x@50000000 { +- hdmi@54280000 { +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = +- <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; +- pll-supply = <®_1v8_avdd_hdmi_pll>; +- vdd-supply = <®_3v3_avdd_hdmi>; +- }; +- }; +- +- pinmux@70000868 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- state_default: pinmux { +- /* Analogue Audio (On-module) */ +- clk1-out-pw4 { +- nvidia,pins = "clk1_out_pw4"; +- nvidia,function = "extperiph1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3-fs-pp0 { +- nvidia,pins = "dap3_fs_pp0", +- "dap3_sclk_pp3", +- "dap3_din_pp1", +- "dap3_dout_pp2"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri Address/Data Bus (GMI) */ +- gmi-ad0-pg0 { +- nvidia,pins = "gmi_ad0_pg0", +- "gmi_ad2_pg2", +- "gmi_ad3_pg3", +- "gmi_ad4_pg4", +- "gmi_ad5_pg5", +- "gmi_ad6_pg6", +- "gmi_ad7_pg7", +- "gmi_ad8_ph0", +- "gmi_ad9_ph1", +- "gmi_ad10_ph2", +- "gmi_ad11_ph3", +- "gmi_ad12_ph4", +- "gmi_ad13_ph5", +- "gmi_ad14_ph6", +- "gmi_ad15_ph7", +- "gmi_adv_n_pk0", +- "gmi_clk_pk1", +- "gmi_cs4_n_pk2", +- "gmi_cs2_n_pk3", +- "gmi_iordy_pi5", +- "gmi_oe_n_pi1", +- "gmi_wait_pi7", +- "gmi_wr_n_pi0", +- "dap1_fs_pn0", +- "dap1_din_pn1", +- "dap1_dout_pn2", +- "dap1_sclk_pn3", +- "dap2_fs_pa2", +- "dap2_sclk_pa3", +- "dap2_din_pa4", +- "dap2_dout_pa5", +- "spi1_sck_px5", +- "spi1_mosi_px4", +- "spi1_cs0_n_px6", +- "spi2_cs0_n_px3", +- "spi2_miso_px1", +- "spi2_mosi_px0", +- "spi2_sck_px2", +- "uart2_cts_n_pj5", +- "uart2_rts_n_pj6"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* Further pins may be used as GPIOs */ +- dap4-din-pp5 { +- nvidia,pins = "dap4_din_pp5", +- "dap4_dout_pp6", +- "dap4_fs_pp4", +- "dap4_sclk_pp7", +- "pbb7", +- "sdmmc1_clk_pz0", +- "sdmmc1_cmd_pz1", +- "sdmmc1_dat0_py7", +- "sdmmc1_dat1_py6", +- "sdmmc1_dat3_py4", +- "uart3_cts_n_pa1", +- "uart3_txd_pw6", +- "uart3_rxd_pw7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd-d18-pm2 { +- nvidia,pins = "lcd_d18_pm2", +- "lcd_d19_pm3", +- "lcd_d20_pm4", +- "lcd_d21_pm5", +- "lcd_d22_pm6", +- "lcd_d23_pm7", +- "lcd_dc0_pn6", +- "pex_l2_clkreq_n_pcc7"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd-cs0-n-pn4 { +- nvidia,pins = "lcd_cs0_n_pn4", +- "lcd_sdin_pz2", +- "pu0", +- "pu1", +- "pu2", +- "pu3", +- "pu4", +- "pu5", +- "pu6", +- "spi1_miso_px7", +- "uart3_rts_n_pc0"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd-pwr0-pb2 { +- nvidia,pins = "lcd_pwr0_pb2", +- "lcd_sck_pz4", +- "lcd_sdout_pn5", +- "lcd_wr_n_pz3"; +- nvidia,function = "hdcp"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb4 { +- nvidia,pins = "pbb4", +- "pbb5", +- "pbb6"; +- nvidia,function = "displayb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* Multiplexed RDnWR and therefore disabled */ +- lcd-cs1-n-pw0 { +- nvidia,pins = "lcd_cs1_n_pw0"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* Multiplexed GMI_CLK and therefore disabled */ +- owr { +- nvidia,pins = "owr"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* Tri-stating GMI_WR_N on nPWE SODIMM pin 99 */ +- sdmmc3-dat4-pd1 { +- nvidia,pins = "sdmmc3_dat4_pd1"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* Not tri-stating GMI_WR_N on RDnWR SODIMM pin 93 */ +- sdmmc3-dat5-pd0 { +- nvidia,pins = "sdmmc3_dat5_pd0"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Colibri BL_ON */ +- pv2 { +- nvidia,pins = "pv2"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri Backlight PWM */ +- sdmmc3-dat3-pb4 { +- nvidia,pins = "sdmmc3_dat3_pb4"; +- nvidia,function = "pwm0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri CAN_INT */ +- kb-row8-ps0 { +- nvidia,pins = "kb_row8_ps0"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Colibri DDC */ +- ddc-scl-pv4 { +- nvidia,pins = "ddc_scl_pv4", +- "ddc_sda_pv5"; +- nvidia,function = "i2c4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Colibri EXT_IO* */ +- gen2-i2c-scl-pt5 { +- nvidia,pins = "gen2_i2c_scl_pt5", +- "gen2_i2c_sda_pt6"; +- nvidia,function = "rsvd4"; +- nvidia,open-drain = ; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spdif-in-pk6 { +- nvidia,pins = "spdif_in_pk6"; +- nvidia,function = "hda"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Colibri GPIO */ +- clk2-out-pw5 { +- nvidia,pins = "clk2_out_pw5", +- "pcc2", +- "pv3", +- "sdmmc1_dat2_py5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd-pwr1-pc1 { +- nvidia,pins = "lcd_pwr1_pc1", +- "pex_l1_clkreq_n_pdd6", +- "pex_l1_rst_n_pdd5"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv1 { +- nvidia,pins = "pv1", +- "sdmmc3_dat0_pb7", +- "sdmmc3_dat1_pb6"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Colibri HOTPLUG_DETECT (HDMI) */ +- hdmi-int-pn7 { +- nvidia,pins = "hdmi_int_pn7"; +- nvidia,function = "hdmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Colibri I2C */ +- gen1-i2c-scl-pc4 { +- nvidia,pins = "gen1_i2c_scl_pc4", +- "gen1_i2c_sda_pc5"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* Colibri LCD (L_* resp. LDD<*>) */ +- lcd-d0-pe0 { +- nvidia,pins = "lcd_d0_pe0", +- "lcd_d1_pe1", +- "lcd_d2_pe2", +- "lcd_d3_pe3", +- "lcd_d4_pe4", +- "lcd_d5_pe5", +- "lcd_d6_pe6", +- "lcd_d7_pe7", +- "lcd_d8_pf0", +- "lcd_d9_pf1", +- "lcd_d10_pf2", +- "lcd_d11_pf3", +- "lcd_d12_pf4", +- "lcd_d13_pf5", +- "lcd_d14_pf6", +- "lcd_d15_pf7", +- "lcd_d16_pm0", +- "lcd_d17_pm1", +- "lcd_de_pj1", +- "lcd_hsync_pj3", +- "lcd_pclk_pb3", +- "lcd_vsync_pj4"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* +- * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE +- * today's display need DE, disable LCD_M1 +- */ +- lcd-m1-pw1 { +- nvidia,pins = "lcd_m1_pw1"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Colibri MMC */ +- kb-row10-ps2 { +- nvidia,pins = "kb_row10_ps2"; +- nvidia,function = "sdmmc2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- kb-row11-ps3 { +- nvidia,pins = "kb_row11_ps3", +- "kb_row12_ps4", +- "kb_row13_ps5", +- "kb_row14_ps6", +- "kb_row15_ps7"; +- nvidia,function = "sdmmc2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- /* Colibri MMC_CD */ +- gmi-wp-n-pc7 { +- nvidia,pins = "gmi_wp_n_pc7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* Multiplexed and therefore disabled */ +- cam-mclk-pcc0 { +- nvidia,pins = "cam_mclk_pcc0"; +- nvidia,function = "vi_alt3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cam-i2c-scl-pbb1 { +- nvidia,pins = "cam_i2c_scl_pbb1", +- "cam_i2c_sda_pbb2"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pbb0 { +- nvidia,pins = "pbb0", +- "pcc1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb3 { +- nvidia,pins = "pbb3"; +- nvidia,function = "displayb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Colibri nRESET_OUT */ +- gmi-rst-n-pi4 { +- nvidia,pins = "gmi_rst_n_pi4"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* +- * Colibri Parallel Camera (Optional) +- * pins multiplexed with others and therefore disabled +- */ +- vi-vsync-pd6 { +- nvidia,pins = "vi_d0_pt4", +- "vi_d1_pd5", +- "vi_d2_pl0", +- "vi_d3_pl1", +- "vi_d4_pl2", +- "vi_d5_pl3", +- "vi_d6_pl4", +- "vi_d7_pl5", +- "vi_d8_pl6", +- "vi_d9_pl7", +- "vi_d10_pt2", +- "vi_d11_pt3", +- "vi_hsync_pd7", +- "vi_mclk_pt1", +- "vi_pclk_pt0", +- "vi_vsync_pd6"; +- nvidia,function = "vi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Colibri PWM */ +- sdmmc3-dat2-pb5 { +- nvidia,pins = "sdmmc3_dat2_pb5"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri PWM */ +- sdmmc3-clk-pa6 { +- nvidia,pins = "sdmmc3_clk_pa6"; +- nvidia,function = "pwm2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri PWM */ +- sdmmc3-cmd-pa7 { +- nvidia,pins = "sdmmc3_cmd_pa7"; +- nvidia,function = "pwm3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri SSP */ +- ulpi-clk-py0 { +- nvidia,pins = "ulpi_clk_py0", +- "ulpi_dir_py1", +- "ulpi_nxt_py2", +- "ulpi_stp_py3"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- /* Multiplexed SSPFRM, SSPTXD and therefore disabled */ +- sdmmc3-dat6-pd3 { +- nvidia,pins = "sdmmc3_dat6_pd3", +- "sdmmc3_dat7_pd4"; +- nvidia,function = "spdif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Colibri UART-A */ +- ulpi-data0 { +- nvidia,pins = "ulpi_data0_po1", +- "ulpi_data1_po2", +- "ulpi_data2_po3", +- "ulpi_data3_po4", +- "ulpi_data4_po5", +- "ulpi_data5_po6", +- "ulpi_data6_po7", +- "ulpi_data7_po0"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri UART-B */ +- gmi-a16-pj7 { +- nvidia,pins = "gmi_a16_pj7", +- "gmi_a17_pb0", +- "gmi_a18_pb1", +- "gmi_a19_pk7"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri UART-C */ +- uart2-rxd { +- nvidia,pins = "uart2_rxd_pc3", +- "uart2_txd_pc2"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri USBC_DET */ +- spdif-out-pk5 { +- nvidia,pins = "spdif_out_pk5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Colibri USBH_PEN */ +- spi2-cs1-n-pw2 { +- nvidia,pins = "spi2_cs1_n_pw2"; +- nvidia,function = "spi2_alt"; +- nvidia,pull = ; +- nvidia,tristate = ; +- }; +- +- /* Colibri USBH_OC */ +- spi2-cs2-n-pw3 { +- nvidia,pins = "spi2_cs2_n_pw3"; +- nvidia,function = "spi2_alt"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Colibri VGA not supported and therefore disabled */ +- crt-hsync-pv6 { +- nvidia,pins = "crt_hsync_pv6", +- "crt_vsync_pv7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* eMMC (On-module) */ +- sdmmc4-clk-pcc4 { +- nvidia,pins = "sdmmc4_clk_pcc4", +- "sdmmc4_cmd_pt7", +- "sdmmc4_rst_n_pcc3"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4-dat0-paa0 { +- nvidia,pins = "sdmmc4_dat0_paa0", +- "sdmmc4_dat1_paa1", +- "sdmmc4_dat2_paa2", +- "sdmmc4_dat3_paa3", +- "sdmmc4_dat4_paa4", +- "sdmmc4_dat5_paa5", +- "sdmmc4_dat6_paa6", +- "sdmmc4_dat7_paa7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* LAN_EXT_WAKEUP#, LAN_PME (On-module) */ +- pex-l0-rst-n-pdd1 { +- nvidia,pins = "pex_l0_rst_n_pdd1", +- "pex_wake_n_pdd3"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- /* LAN_V_BUS, LAN_RESET# (On-module) */ +- pex-l0-clkreq-n-pdd2 { +- nvidia,pins = "pex_l0_clkreq_n_pdd2", +- "pex_l0_prsnt_n_pdd0"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* nBATT_FAULT(SENSE), nVDD_FAULT(SENSE) */ +- pex-l2-rst-n-pcc6 { +- nvidia,pins = "pex_l2_rst_n_pcc6", +- "pex_l2_prsnt_n_pdd7"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Not connected and therefore disabled */ +- clk1-req-pee2 { +- nvidia,pins = "clk1_req_pee2", +- "pex_l1_prsnt_n_pdd4"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2-req-pcc5 { +- nvidia,pins = "clk2_req_pcc5", +- "clk3_out_pee0", +- "clk3_req_pee1", +- "clk_32k_out_pa0", +- "hdmi_cec_pee3", +- "sys_clk_req_pz5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi-dqs-pi2 { +- nvidia,pins = "gmi_dqs_pi2", +- "kb_col2_pq2", +- "kb_col3_pq3", +- "kb_col4_pq4", +- "kb_col5_pq5", +- "kb_row4_pr4"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-col0-pq0 { +- nvidia,pins = "kb_col0_pq0", +- "kb_col1_pq1", +- "kb_col6_pq6", +- "kb_col7_pq7", +- "kb_row5_pr5", +- "kb_row6_pr6", +- "kb_row7_pr7", +- "kb_row9_ps1"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb-row0-pr0 { +- nvidia,pins = "kb_row0_pr0", +- "kb_row1_pr1", +- "kb_row2_pr2", +- "kb_row3_pr3"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd-pwr2-pc6 { +- nvidia,pins = "lcd_pwr2_pc6"; +- nvidia,function = "hdcp"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* Power I2C (On-module) */ +- pwr-i2c-scl-pz6 { +- nvidia,pins = "pwr_i2c_scl_pz6", +- "pwr_i2c_sda_pz7"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- +- /* +- * THERMD_ALERT#, unlatched I2C address pin of LM95245 +- * temperature sensor therefore requires disabling for +- * now +- */ +- lcd-dc1-pd2 { +- nvidia,pins = "lcd_dc1_pd2"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- +- /* TOUCH_PEN_INT# (On-module) */ +- pv0 { +- nvidia,pins = "pv0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- }; +- }; +- +- serial@70006040 { +- compatible = "nvidia,tegra30-hsuart"; +- }; +- +- serial@70006300 { +- compatible = "nvidia,tegra30-hsuart"; +- }; +- +- hdmi_ddc: i2c@7000c700 { +- clock-frequency = <10000>; +- }; +- +- /* +- * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and +- * touch screen controller (On-module) +- */ +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <100000>; +- +- /* SGTL5000 audio codec */ +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- #sound-dai-cells = <0>; +- VDDA-supply = <®_module_3v3_audio>; +- VDDD-supply = <®_1v8_vio>; +- VDDIO-supply = <®_module_3v3>; +- clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; +- }; +- +- pmic: pmic@2d { +- compatible = "ti,tps65911"; +- reg = <0x2d>; +- +- interrupts = ; +- #interrupt-cells = <2>; +- interrupt-controller; +- wakeup-source; +- +- ti,system-power-controller; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- vcc1-supply = <®_module_3v3>; +- vcc2-supply = <®_module_3v3>; +- vcc3-supply = <®_1v8_vio>; +- vcc4-supply = <®_module_3v3>; +- vcc5-supply = <®_module_3v3>; +- vcc6-supply = <®_1v8_vio>; +- vcc7-supply = <®_5v0_charge_pump>; +- vccio-supply = <®_module_3v3>; +- +- regulators { +- vdd1_reg: vdd1 { +- regulator-name = "+V1.35_VDDIO_DDR"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- }; +- +- /* SW2: unused */ +- +- vddctrl_reg: vddctrl { +- regulator-name = "+V1.0_VDD_CPU"; +- regulator-min-microvolt = <1150000>; +- regulator-max-microvolt = <1150000>; +- regulator-always-on; +- }; +- +- reg_1v8_vio: vio { +- regulator-name = "+V1.8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- /* LDO1: unused */ +- +- /* +- * EN_+V3.3 switching via FET: +- * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN +- * see also +V3.3 fixed supply +- */ +- ldo2_reg: ldo2 { +- regulator-name = "EN_+V3.3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- /* LDO3: unused */ +- +- ldo4_reg: ldo4 { +- regulator-name = "+V1.2_VDD_RTC"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- /* +- * +V2.8_AVDD_VDAC: +- * only required for (unsupported) analog RGB +- */ +- ldo5_reg: ldo5 { +- regulator-name = "+V2.8_AVDD_VDAC"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- /* +- * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V +- * but LDO6 can't set voltage in 50mV +- * granularity +- */ +- ldo6_reg: ldo6 { +- regulator-name = "+V1.05_AVDD_PLLE"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- ldo7_reg: ldo7 { +- regulator-name = "+V1.2_AVDD_PLL"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo8_reg: ldo8 { +- regulator-name = "+V1.0_VDD_DDR_HS"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- }; +- }; +- +- /* STMPE811 touch screen controller */ +- touchscreen@41 { +- compatible = "st,stmpe811"; +- reg = <0x41>; +- irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- id = <0>; +- blocks = <0x5>; +- irq-trigger = <0x1>; +- /* 3.25 MHz ADC clock speed */ +- st,adc-freq = <1>; +- /* 12-bit ADC */ +- st,mod-12b = <1>; +- /* internal ADC reference */ +- st,ref-sel = <0>; +- /* ADC converstion time: 80 clocks */ +- st,sample-time = <4>; +- /* forbid to use ADC channels 3-0 (touch) */ +- +- stmpe_touchscreen { +- compatible = "st,stmpe-ts"; +- /* 8 sample average control */ +- st,ave-ctrl = <3>; +- /* 7 length fractional part in z */ +- st,fraction-z = <7>; +- /* +- * 50 mA typical 80 mA max touchscreen drivers +- * current limit value +- */ +- st,i-drive = <1>; +- /* 1 ms panel driver settling time */ +- st,settling = <3>; +- /* 5 ms touch detect interrupt delay */ +- st,touch-det-delay = <5>; +- }; +- +- stmpe_adc { +- compatible = "st,stmpe-adc"; +- st,norequest-mask = <0x0F>; +- }; +- }; +- +- /* +- * LM95245 temperature sensor +- * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN +- */ +- temp-sensor@4c { +- compatible = "national,lm95245"; +- reg = <0x4c>; +- }; +- +- /* SW: +V1.2_VDD_CORE */ +- regulator@60 { +- compatible = "ti,tps62362"; +- reg = <0x60>; +- +- regulator-name = "tps62362-vout"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- regulator-always-on; +- ti,vsel0-state-low; +- /* VSEL1: EN_CORE_DVFS_N low for DVFS */ +- ti,vsel1-state-low; +- }; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <5000>; +- nvidia,cpu-pwr-off-time = <5000>; +- nvidia,core-pwr-good-time = <3845 3845>; +- nvidia,core-pwr-off-time = <0>; +- nvidia,core-power-req-active-high; +- nvidia,sys-clock-req-active-high; +- +- /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ +- i2c-thermtrip { +- nvidia,i2c-controller-id = <4>; +- nvidia,bus-addr = <0x2d>; +- nvidia,reg-addr = <0x3f>; +- nvidia,reg-data = <0x1>; +- }; +- }; +- +- hda@70030000 { +- status = "okay"; +- }; +- +- ahub@70080000 { +- i2s@70080500 { +- status = "okay"; +- }; +- }; +- +- /* eMMC */ +- mmc@78000600 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- vmmc-supply = <®_module_3v3>; /* VCC */ +- vqmmc-supply = <®_1v8_vio>; /* VCCQ */ +- mmc-ddr-1_8v; +- }; +- +- /* EHCI instance 1: USB2_DP/N -> AX88772B (On-module) */ +- usb@7d004000 { +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- asix@1 { +- reg = <1>; +- local-mac-address = [00 00 00 00 00 00]; +- }; +- }; +- +- usb-phy@7d004000 { +- status = "okay"; +- vbus-supply = <®_lan_v_bus>; +- }; +- +- clk32k_in: xtal1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { +- compatible = "regulator-fixed"; +- regulator-name = "+V1.8_AVDD_HDMI_PLL"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- enable-active-high; +- gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; +- vin-supply = <®_1v8_vio>; +- }; +- +- reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3_AVDD_HDMI"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; +- vin-supply = <®_module_3v3>; +- }; +- +- reg_5v0_charge_pump: regulator-5v0-charge-pump { +- compatible = "regulator-fixed"; +- regulator-name = "+V5.0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_lan_v_bus: regulator-lan-v-bus { +- compatible = "regulator-fixed"; +- regulator-name = "LAN_V_BUS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; +- }; +- +- reg_module_3v3: regulator-module-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_module_3v3_audio: regulator-module-3v3-audio { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3_AUDIO_AVDD_S"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- sound { +- compatible = "toradex,tegra-audio-sgtl5000-colibri_t30", +- "nvidia,tegra-audio-sgtl5000"; +- nvidia,model = "Toradex Colibri T30"; +- nvidia,audio-routing = +- "Headphone Jack", "HP_OUT", +- "LINE_IN", "Line In Jack", +- "MIC_IN", "Mic Jack"; +- nvidia,i2s-controller = <&tegra_i2s2>; +- nvidia,audio-codec = <&sgtl5000>; +- clocks = <&tegra_car TEGRA30_CLK_PLL_A>, +- <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- clock-names = "pll_a", "pll_a_out0", "mclk"; +- +- assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, +- <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; +- +- assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA30_CLK_EXTERN1>; +- }; +-}; +- +-&gpio { +- lan-reset-n { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "LAN_RESET#"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-cpu-opp-microvolt.dtsi b/scripts/dtc/include-prefixes/arm/tegra30-cpu-opp-microvolt.dtsi +deleted file mode 100644 +index 1be715d2a442..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-cpu-opp-microvolt.dtsi ++++ /dev/null +@@ -1,289 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/ { +- cpu0_opp_table: cpu_opp_table0 { +- opp@51000000,800 { +- opp-microvolt = <800000 800000 1250000>; +- }; +- +- opp@51000000,850 { +- opp-microvolt = <850000 850000 1250000>; +- }; +- +- opp@51000000,912 { +- opp-microvolt = <912000 912000 1250000>; +- }; +- +- opp@102000000,800 { +- opp-microvolt = <800000 800000 1250000>; +- }; +- +- opp@102000000,850 { +- opp-microvolt = <850000 850000 1250000>; +- }; +- +- opp@102000000,912 { +- opp-microvolt = <912000 912000 1250000>; +- }; +- +- opp@204000000,800 { +- opp-microvolt = <800000 800000 1250000>; +- }; +- +- opp@204000000,850 { +- opp-microvolt = <850000 850000 1250000>; +- }; +- +- opp@204000000,912 { +- opp-microvolt = <912000 912000 1250000>; +- }; +- +- opp@312000000,850 { +- opp-microvolt = <850000 850000 1250000>; +- }; +- +- opp@312000000,912 { +- opp-microvolt = <912000 912000 1250000>; +- }; +- +- opp@340000000,800 { +- opp-microvolt = <800000 800000 1250000>; +- }; +- +- opp@340000000,850 { +- opp-microvolt = <850000 850000 1250000>; +- }; +- +- opp@370000000,800 { +- opp-microvolt = <800000 800000 1250000>; +- }; +- +- opp@456000000,850 { +- opp-microvolt = <850000 850000 1250000>; +- }; +- +- opp@456000000,912 { +- opp-microvolt = <912000 912000 1250000>; +- }; +- +- opp@475000000,800 { +- opp-microvolt = <800000 800000 1250000>; +- }; +- +- opp@475000000,850 { +- opp-microvolt = <850000 850000 1250000>; +- }; +- +- opp@608000000,850 { +- opp-microvolt = <850000 850000 1250000>; +- }; +- +- opp@608000000,912 { +- opp-microvolt = <912000 912000 1250000>; +- }; +- +- opp@620000000,850 { +- opp-microvolt = <850000 850000 1250000>; +- }; +- +- opp@640000000,850 { +- opp-microvolt = <850000 850000 1250000>; +- }; +- +- opp@640000000,900 { +- opp-microvolt = <900000 900000 1250000>; +- }; +- +- opp@760000000,850 { +- opp-microvolt = <850000 850000 1250000>; +- }; +- +- opp@760000000,900 { +- opp-microvolt = <900000 900000 1250000>; +- }; +- +- opp@760000000,912 { +- opp-microvolt = <912000 912000 1250000>; +- }; +- +- opp@760000000,975 { +- opp-microvolt = <975000 975000 1250000>; +- }; +- +- opp@816000000,850 { +- opp-microvolt = <850000 850000 1250000>; +- }; +- +- opp@816000000,912 { +- opp-microvolt = <912000 912000 1250000>; +- }; +- +- opp@860000000,850 { +- opp-microvolt = <850000 850000 1250000>; +- }; +- +- opp@860000000,900 { +- opp-microvolt = <900000 900000 1250000>; +- }; +- +- opp@860000000,975 { +- opp-microvolt = <975000 975000 1250000>; +- }; +- +- opp@860000000,1000 { +- opp-microvolt = <1000000 1000000 1250000>; +- }; +- +- opp@910000000,900 { +- opp-microvolt = <900000 900000 1250000>; +- }; +- +- opp@1000000000,900 { +- opp-microvolt = <900000 900000 1250000>; +- }; +- +- opp@1000000000,975 { +- opp-microvolt = <975000 975000 1250000>; +- }; +- +- opp@1000000000,1000 { +- opp-microvolt = <1000000 1000000 1250000>; +- }; +- +- opp@1000000000,1025 { +- opp-microvolt = <1025000 1025000 1250000>; +- }; +- +- opp@1100000000,900 { +- opp-microvolt = <900000 900000 1250000>; +- }; +- +- opp@1100000000,975 { +- opp-microvolt = <975000 975000 1250000>; +- }; +- +- opp@1100000000,1000 { +- opp-microvolt = <1000000 1000000 1250000>; +- }; +- +- opp@1100000000,1025 { +- opp-microvolt = <1025000 1025000 1250000>; +- }; +- +- opp@1100000000,1075 { +- opp-microvolt = <1075000 1075000 1250000>; +- }; +- +- opp@1150000000,975 { +- opp-microvolt = <975000 975000 1250000>; +- }; +- +- opp@1200000000,975 { +- opp-microvolt = <975000 975000 1250000>; +- }; +- +- opp@1200000000,1000 { +- opp-microvolt = <1000000 1000000 1250000>; +- }; +- +- opp@1200000000,1025 { +- opp-microvolt = <1025000 1025000 1250000>; +- }; +- +- opp@1200000000,1050 { +- opp-microvolt = <1050000 1050000 1250000>; +- }; +- +- opp@1200000000,1075 { +- opp-microvolt = <1075000 1075000 1250000>; +- }; +- +- opp@1200000000,1100 { +- opp-microvolt = <1100000 1100000 1250000>; +- }; +- +- opp@1300000000,1000 { +- opp-microvolt = <1000000 1000000 1250000>; +- }; +- +- opp@1300000000,1025 { +- opp-microvolt = <1025000 1025000 1250000>; +- }; +- +- opp@1300000000,1050 { +- opp-microvolt = <1050000 1050000 1250000>; +- }; +- +- opp@1300000000,1075 { +- opp-microvolt = <1075000 1075000 1250000>; +- }; +- +- opp@1300000000,1100 { +- opp-microvolt = <1100000 1100000 1250000>; +- }; +- +- opp@1300000000,1125 { +- opp-microvolt = <1125000 1125000 1250000>; +- }; +- +- opp@1300000000,1150 { +- opp-microvolt = <1150000 1150000 1250000>; +- }; +- +- opp@1300000000,1175 { +- opp-microvolt = <1175000 1175000 1250000>; +- }; +- +- opp@1400000000,1100 { +- opp-microvolt = <1100000 1100000 1250000>; +- }; +- +- opp@1400000000,1125 { +- opp-microvolt = <1125000 1125000 1250000>; +- }; +- +- opp@1400000000,1150 { +- opp-microvolt = <1150000 1150000 1250000>; +- }; +- +- opp@1400000000,1175 { +- opp-microvolt = <1175000 1175000 1250000>; +- }; +- +- opp@1400000000,1237 { +- opp-microvolt = <1237000 1237000 1250000>; +- }; +- +- opp@1500000000,1125 { +- opp-microvolt = <1125000 1125000 1250000>; +- }; +- +- opp@1500000000,1150 { +- opp-microvolt = <1150000 1150000 1250000>; +- }; +- +- opp@1500000000,1200 { +- opp-microvolt = <1200000 1200000 1250000>; +- }; +- +- opp@1500000000,1237 { +- opp-microvolt = <1237000 1237000 1250000>; +- }; +- +- opp@1600000000,1212 { +- opp-microvolt = <1212000 1212000 1250000>; +- }; +- +- opp@1600000000,1237 { +- opp-microvolt = <1237000 1237000 1250000>; +- }; +- +- opp@1700000000,1212 { +- opp-microvolt = <1212000 1212000 1250000>; +- }; +- +- opp@1700000000,1237 { +- opp-microvolt = <1237000 1237000 1250000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-cpu-opp.dtsi b/scripts/dtc/include-prefixes/arm/tegra30-cpu-opp.dtsi +deleted file mode 100644 +index 72f2fe26cc0e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-cpu-opp.dtsi ++++ /dev/null +@@ -1,499 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/ { +- cpu0_opp_table: cpu_opp_table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp@51000000,800 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1F 0x31FE>; +- opp-hz = /bits/ 64 <51000000>; +- }; +- +- opp@51000000,850 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1F 0x0C01>; +- opp-hz = /bits/ 64 <51000000>; +- }; +- +- opp@51000000,912 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1F 0x0200>; +- opp-hz = /bits/ 64 <51000000>; +- }; +- +- opp@102000000,800 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1F 0x31FE>; +- opp-hz = /bits/ 64 <102000000>; +- }; +- +- opp@102000000,850 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1F 0x0C01>; +- opp-hz = /bits/ 64 <102000000>; +- }; +- +- opp@102000000,912 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1F 0x0200>; +- opp-hz = /bits/ 64 <102000000>; +- }; +- +- opp@204000000,800 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1F 0x31FE>; +- opp-hz = /bits/ 64 <204000000>; +- opp-suspend; +- }; +- +- opp@204000000,850 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1F 0x0C01>; +- opp-hz = /bits/ 64 <204000000>; +- opp-suspend; +- }; +- +- opp@204000000,912 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1F 0x0200>; +- opp-hz = /bits/ 64 <204000000>; +- opp-suspend; +- }; +- +- opp@312000000,850 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1F 0x0C00>; +- opp-hz = /bits/ 64 <312000000>; +- }; +- +- opp@312000000,912 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1F 0x0200>; +- opp-hz = /bits/ 64 <312000000>; +- }; +- +- opp@340000000,800 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1F 0x0192>; +- opp-hz = /bits/ 64 <340000000>; +- }; +- +- opp@340000000,850 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x0F 0x0001>; +- opp-hz = /bits/ 64 <340000000>; +- }; +- +- opp@370000000,800 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1E 0x306C>; +- opp-hz = /bits/ 64 <370000000>; +- }; +- +- opp@456000000,850 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1F 0x0C00>; +- opp-hz = /bits/ 64 <456000000>; +- }; +- +- opp@456000000,912 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1F 0x0200>; +- opp-hz = /bits/ 64 <456000000>; +- }; +- +- opp@475000000,800 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1E 0x31FE>; +- opp-hz = /bits/ 64 <475000000>; +- }; +- +- opp@475000000,850 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x0F 0x0001>, <0x01 0x0002>, +- <0x01 0x0010>, <0x01 0x0080>, +- <0x01 0x0100>; +- opp-hz = /bits/ 64 <475000000>; +- }; +- +- opp@608000000,850 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1F 0x0400>; +- opp-hz = /bits/ 64 <608000000>; +- }; +- +- opp@608000000,912 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1F 0x0200>; +- opp-hz = /bits/ 64 <608000000>; +- }; +- +- opp@620000000,850 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1E 0x306C>; +- opp-hz = /bits/ 64 <620000000>; +- }; +- +- opp@640000000,850 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x0F 0x0001>, <0x02 0x0002>, +- <0x04 0x0002>, <0x08 0x0002>, +- <0x02 0x0010>, <0x04 0x0010>, +- <0x08 0x0010>, <0x02 0x0080>, +- <0x04 0x0080>, <0x08 0x0080>, +- <0x10 0x0080>, <0x02 0x0100>, +- <0x04 0x0100>, <0x08 0x0100>, +- <0x10 0x0100>; +- opp-hz = /bits/ 64 <640000000>; +- }; +- +- opp@640000000,900 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x01 0x0192>; +- opp-hz = /bits/ 64 <640000000>; +- }; +- +- opp@760000000,850 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1E 0x3461>, <0x08 0x0002>, +- <0x08 0x0004>, <0x08 0x0008>, +- <0x08 0x0010>, <0x08 0x0080>, +- <0x10 0x0080>, <0x08 0x0100>, +- <0x10 0x0100>, <0x01 0x0400>; +- opp-hz = /bits/ 64 <760000000>; +- }; +- +- opp@760000000,900 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x01 0x0001>, <0x02 0x0002>, +- <0x04 0x0002>, <0x02 0x0004>, +- <0x04 0x0004>, <0x02 0x0008>, +- <0x04 0x0008>, <0x02 0x0010>, +- <0x04 0x0010>, <0x02 0x0080>, +- <0x04 0x0080>, <0x02 0x0100>, +- <0x04 0x0100>; +- opp-hz = /bits/ 64 <760000000>; +- }; +- +- opp@760000000,912 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1F 0x0200>; +- opp-hz = /bits/ 64 <760000000>; +- }; +- +- opp@760000000,975 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x01 0x0192>; +- opp-hz = /bits/ 64 <760000000>; +- }; +- +- opp@816000000,850 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1F 0x0400>; +- opp-hz = /bits/ 64 <816000000>; +- }; +- +- opp@816000000,912 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x1F 0x0200>; +- opp-hz = /bits/ 64 <816000000>; +- }; +- +- opp@860000000,850 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x0C 0x0001>; +- opp-hz = /bits/ 64 <860000000>; +- }; +- +- opp@860000000,900 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x02 0x0001>, <0x04 0x0002>, +- <0x08 0x0002>, <0x04 0x0004>, +- <0x08 0x0004>, <0x04 0x0008>, +- <0x08 0x0008>, <0x04 0x0010>, +- <0x08 0x0010>, <0x04 0x0080>, +- <0x08 0x0080>, <0x10 0x0080>, +- <0x04 0x0100>, <0x08 0x0100>, +- <0x10 0x0100>; +- opp-hz = /bits/ 64 <860000000>; +- }; +- +- opp@860000000,975 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x01 0x0001>, <0x02 0x0002>, +- <0x02 0x0004>, <0x02 0x0008>, +- <0x02 0x0010>, <0x02 0x0080>, +- <0x02 0x0100>; +- opp-hz = /bits/ 64 <860000000>; +- }; +- +- opp@860000000,1000 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x01 0x0192>; +- opp-hz = /bits/ 64 <860000000>; +- }; +- +- opp@910000000,900 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x18 0x3060>; +- opp-hz = /bits/ 64 <910000000>; +- }; +- +- opp@1000000000,900 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x0C 0x0001>; +- opp-hz = /bits/ 64 <1000000000>; +- }; +- +- opp@1000000000,975 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x03 0x0001>, <0x04 0x0002>, +- <0x08 0x0002>, <0x04 0x0004>, +- <0x08 0x0004>, <0x04 0x0008>, +- <0x08 0x0008>, <0x04 0x0010>, +- <0x08 0x0010>, <0x04 0x0080>, +- <0x08 0x0080>, <0x10 0x0080>, +- <0x04 0x0100>, <0x08 0x0100>, +- <0x10 0x0100>; +- opp-hz = /bits/ 64 <1000000000>; +- }; +- +- opp@1000000000,1000 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x02 0x019E>; +- opp-hz = /bits/ 64 <1000000000>; +- }; +- +- opp@1000000000,1025 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x01 0x0192>; +- opp-hz = /bits/ 64 <1000000000>; +- }; +- +- opp@1100000000,900 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x08 0x0001>; +- opp-hz = /bits/ 64 <1100000000>; +- }; +- +- opp@1100000000,975 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x06 0x0001>, <0x08 0x0002>, +- <0x08 0x0004>, <0x08 0x0008>, +- <0x08 0x0010>, <0x08 0x0080>, +- <0x10 0x0080>, <0x08 0x0100>, +- <0x10 0x0100>; +- opp-hz = /bits/ 64 <1100000000>; +- }; +- +- opp@1100000000,1000 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x01 0x0001>, <0x04 0x0002>, +- <0x04 0x0004>, <0x04 0x0008>, +- <0x04 0x0010>, <0x04 0x0080>, +- <0x04 0x0100>; +- opp-hz = /bits/ 64 <1100000000>; +- }; +- +- opp@1100000000,1025 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x02 0x019E>; +- opp-hz = /bits/ 64 <1100000000>; +- }; +- +- opp@1100000000,1075 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x01 0x0192>; +- opp-hz = /bits/ 64 <1100000000>; +- }; +- +- opp@1150000000,975 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x18 0x3060>; +- opp-hz = /bits/ 64 <1150000000>; +- }; +- +- opp@1200000000,975 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x08 0x0001>; +- opp-hz = /bits/ 64 <1200000000>; +- }; +- +- opp@1200000000,1000 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x04 0x0001>, <0x08 0x0002>, +- <0x08 0x0004>, <0x08 0x0008>, +- <0x08 0x0010>, <0x08 0x0080>, +- <0x10 0x0080>, <0x08 0x0100>, +- <0x10 0x0100>; +- opp-hz = /bits/ 64 <1200000000>; +- }; +- +- opp@1200000000,1025 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x02 0x0001>, <0x04 0x0002>, +- <0x04 0x0004>, <0x04 0x0008>, +- <0x04 0x0010>, <0x04 0x0080>, +- <0x04 0x0100>; +- opp-hz = /bits/ 64 <1200000000>; +- }; +- +- opp@1200000000,1050 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x02 0x019E>; +- opp-hz = /bits/ 64 <1200000000>; +- }; +- +- opp@1200000000,1075 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x01 0x0001>; +- opp-hz = /bits/ 64 <1200000000>; +- }; +- +- opp@1200000000,1100 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x01 0x0192>; +- opp-hz = /bits/ 64 <1200000000>; +- }; +- +- opp@1300000000,1000 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x08 0x0001>, <0x10 0x0080>, +- <0x10 0x0100>; +- opp-hz = /bits/ 64 <1300000000>; +- }; +- +- opp@1300000000,1025 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x04 0x0001>, <0x08 0x0002>, +- <0x08 0x0080>, <0x08 0x0100>; +- opp-hz = /bits/ 64 <1300000000>; +- }; +- +- opp@1300000000,1050 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x12 0x3061>, <0x04 0x0002>, +- <0x08 0x0004>, <0x08 0x0008>, +- <0x08 0x0010>, <0x08 0x0020>, +- <0x08 0x0040>, <0x04 0x0080>, +- <0x04 0x0100>, <0x08 0x1000>, +- <0x08 0x2000>; +- opp-hz = /bits/ 64 <1300000000>; +- }; +- +- opp@1300000000,1075 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x02 0x0182>, <0x04 0x0004>, +- <0x04 0x0008>, <0x04 0x0010>; +- opp-hz = /bits/ 64 <1300000000>; +- }; +- +- opp@1300000000,1100 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x02 0x001C>; +- opp-hz = /bits/ 64 <1300000000>; +- }; +- +- opp@1300000000,1125 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x01 0x0001>; +- opp-hz = /bits/ 64 <1300000000>; +- }; +- +- opp@1300000000,1150 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x01 0x0182>; +- opp-hz = /bits/ 64 <1300000000>; +- }; +- +- opp@1300000000,1175 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x01 0x0010>; +- opp-hz = /bits/ 64 <1300000000>; +- }; +- +- opp@1400000000,1100 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x18 0x307C>; +- opp-hz = /bits/ 64 <1400000000>; +- }; +- +- opp@1400000000,1125 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x04 0x000C>; +- opp-hz = /bits/ 64 <1400000000>; +- }; +- +- opp@1400000000,1150 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x02 0x000C>, <0x04 0x0010>; +- opp-hz = /bits/ 64 <1400000000>; +- }; +- +- opp@1400000000,1175 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x02 0x0010>; +- opp-hz = /bits/ 64 <1400000000>; +- }; +- +- opp@1400000000,1237 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x01 0x0010>; +- opp-hz = /bits/ 64 <1400000000>; +- }; +- +- opp@1500000000,1125 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x08 0x0010>, <0x10 0x0020>, +- <0x10 0x0040>, <0x10 0x1000>, +- <0x10 0x2000>; +- opp-hz = /bits/ 64 <1500000000>; +- }; +- +- opp@1500000000,1150 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x04 0x0010>, <0x08 0x0020>, +- <0x08 0x0040>, <0x08 0x1000>, +- <0x08 0x2000>; +- opp-hz = /bits/ 64 <1500000000>; +- }; +- +- opp@1500000000,1200 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x02 0x0010>; +- opp-hz = /bits/ 64 <1500000000>; +- }; +- +- opp@1500000000,1237 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x01 0x0010>; +- opp-hz = /bits/ 64 <1500000000>; +- }; +- +- opp@1600000000,1212 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x10 0x3060>; +- opp-hz = /bits/ 64 <1600000000>; +- }; +- +- opp@1600000000,1237 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x08 0x3060>; +- opp-hz = /bits/ 64 <1600000000>; +- }; +- +- opp@1700000000,1212 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x10 0x3060>; +- opp-hz = /bits/ 64 <1700000000>; +- }; +- +- opp@1700000000,1237 { +- clock-latency-ns = <100000>; +- opp-supported-hw = <0x08 0x3060>; +- opp-hz = /bits/ 64 <1700000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-ouya.dts b/scripts/dtc/include-prefixes/arm/tegra30-ouya.dts +deleted file mode 100644 +index 90db5ff72537..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-ouya.dts ++++ /dev/null +@@ -1,4528 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +-#include +- +-#include "tegra30.dtsi" +-#include "tegra30-cpu-opp.dtsi" +-#include "tegra30-cpu-opp-microvolt.dtsi" +- +-/ { +- model = "Ouya Game Console"; +- compatible = "ouya,ouya", "nvidia,tegra30"; +- +- aliases { +- mmc0 = &sdmmc4; /* eMMC */ +- mmc1 = &sdmmc3; /* WiFi */ +- rtc0 = &pmic; +- rtc1 = "/rtc@7000e000"; +- serial0 = &uartd; /* Debug Port */ +- serial1 = &uartc; /* Bluetooth */ +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@80000000 { +- reg = <0x80000000 0x40000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- linux,cma@80000000 { +- compatible = "shared-dma-pool"; +- alloc-ranges = <0x80000000 0x30000000>; +- size = <0x10000000>; /* 256MiB */ +- linux,cma-default; +- reusable; +- }; +- +- ramoops@bfdf0000 { +- compatible = "ramoops"; +- reg = <0xbfdf0000 0x10000>; /* 64kB */ +- console-size = <0x8000>; /* 32kB */ +- record-size = <0x400>; /* 1kB */ +- ecc-size = <16>; +- }; +- +- trustzone@bfe00000 { +- reg = <0xbfe00000 0x200000>; +- no-map; +- }; +- }; +- +- host1x@50000000 { +- hdmi@54280000 { +- status = "okay"; +- vdd-supply = <&vdd_vid_reg>; +- pll-supply = <&ldo7_reg>; +- hdmi-supply = <&sys_3v3_reg>; +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gpio: gpio@6000d000 { +- gpio-ranges = <&pinmux 0 0 248>; +- #reset-cells = <1>; +- }; +- +- pinmux@70000868 { +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- state_default: pinmux { +- /* located at $state_default below */ +- }; +- }; +- +- uartc: serial@70006200 { +- status = "okay"; +- compatible = "nvidia,tegra30-hsuart"; +- +- nvidia,adjust-baud-rates = <0 9600 100>, +- <9600 115200 200>, +- <1000000 4000000 136>; +- +- /* Azurewave AW-NH660 BCM4330B1 */ +- bluetooth { +- compatible = "brcm,bcm4330-bt"; +- +- max-speed = <4000000>; +- +- clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; +- clock-names = "txco"; +- +- vbat-supply = <&sys_3v3_reg>; +- vddio-supply = <&vdd_1v8>; +- +- shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; +- device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- uartd: serial@70006300 { +- status = "okay"; +- }; +- +- hdmi_ddc: i2c@7000c700 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- cpu_temp: nct1008@4c { +- compatible = "onnn,nct1008"; +- reg = <0x4c>; +- vcc-supply = <&sys_3v3_reg>; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- #thermal-sensor-cells = <1>; +- }; +- +- pmic: pmic@2d { +- compatible = "ti,tps65911"; +- reg = <0x2d>; +- +- interrupts = ; +- #interrupt-cells = <2>; +- interrupt-controller; +- wakeup-source; +- +- ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>; +- ti,system-power-controller; +- ti,sleep-keep-ck32k; +- ti,sleep-enable; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- vcc1-supply = <&vdd_5v0_reg>; +- vcc2-supply = <&vdd_5v0_reg>; +- vcc3-supply = <&vdd_1v8>; +- vcc4-supply = <&vdd_5v0_reg>; +- vcc5-supply = <&vdd_5v0_reg>; +- vcc6-supply = <&vdd2_reg>; +- vcc7-supply = <&vdd_5v0_reg>; +- vccio-supply = <&vdd_5v0_reg>; +- +- regulators { +- vdd1_reg: vdd1 { +- regulator-name = "vddio_ddr_1v2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vdd2_reg: vdd2 { +- regulator-name = "vdd_1v5_gen"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- +- vdd_cpu: vddctrl { +- regulator-name = "vdd_cpu,vdd_sys"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1270000>; +- regulator-coupled-with = <&vdd_core>; +- regulator-coupled-max-spread = <300000>; +- regulator-max-step-microvolt = <100000>; +- regulator-always-on; +- +- nvidia,tegra-cpu-regulator; +- }; +- +- vdd_1v8: vio { +- regulator-name = "vdd_1v8_gen"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo1_reg: ldo1 { +- regulator-name = "vdd_pexa,vdd_pexb"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-always-on; +- }; +- +- ldo2_reg: ldo2 { +- regulator-name = "vdd_sata,avdd_plle"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-always-on; +- }; +- +- /* LDO3 is not connected to anything */ +- +- ldo4_reg: ldo4 { +- regulator-name = "vdd_rtc"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo5_reg: ldo5 { +- regulator-name = "vddio_sdmmc,avdd_vdac"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo6_reg: ldo6 { +- regulator-name = "avdd_dsi_csi,pwrdet_mipi"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo7_reg: ldo7 { +- regulator-name = "vdd_pllm,x,u,a_p_c_s"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- ldo8_reg: ldo8 { +- regulator-name = "vdd_ddr_hs"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- }; +- }; +- +- vdd_core: tps62361@60 { +- compatible = "ti,tps62361"; +- reg = <0x60>; +- +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1350000>; +- regulator-coupled-with = <&vdd_cpu>; +- regulator-coupled-max-spread = <300000>; +- regulator-max-step-microvolt = <100000>; +- regulator-boot-on; +- regulator-always-on; +- ti,vsel0-state-high; +- ti,vsel1-state-high; +- ti,enable-vout-discharge; +- +- nvidia,tegra-core-regulator; +- }; +- }; +- +- pmc@7000e400 { +- status = "okay"; +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <1>; +- nvidia,cpu-pwr-good-time = <2000>; +- nvidia,cpu-pwr-off-time = <200>; +- nvidia,core-pwr-good-time = <3845 3845>; +- nvidia,core-pwr-off-time = <458>; +- nvidia,core-power-req-active-high; +- nvidia,sys-clock-req-active-high; +- }; +- +- mc_timings: memory-controller@7000f000 { +- /* timings located at &mc_timings below */ +- }; +- +- emc_timings: memory-controller@7000f400 { +- /* timings located at &emc_timings below */ +- }; +- +- hda@70030000 { +- status = "okay"; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- +- clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; +- clock-names = "ext_clock"; +- +- reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; +- post-power-on-delay-ms = <300>; +- power-off-delay-us = <300>; +- }; +- +- sdmmc3: mmc@78000400 { +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; +- assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; +- assigned-clock-rates = <50000000>; +- +- max-frequency = <50000000>; +- keep-power-in-suspend; +- +- bus-width = <4>; +- non-removable; +- +- mmc-pwrseq = <&wifi_pwrseq>; +- vmmc-supply = <&sdmmc_3v3_reg>; +- vqmmc-supply = <&vdd_1v8>; +- +- /* Azurewave AW-NH660 BCM4330 */ +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&gpio>; +- interrupts = ; +- interrupt-names = "host-wake"; +- }; +- }; +- +- sdmmc4: mmc@78000600 { +- status = "okay"; +- +- keep-power-in-suspend; +- bus-width = <8>; +- non-removable; +- vmmc-supply = <&sys_3v3_reg>; +- vqmmc-supply = <&vdd_1v8>; +- nvidia,default-tap = <0x0F>; +- max-frequency = <25500000>; +- }; +- +- usb@7d000000 { +- compatible = "nvidia,tegra30-udc"; +- status = "okay"; +- }; +- +- usb-phy@7d000000 { +- status = "okay"; +- dr_mode = "peripheral"; +- }; +- +- usb@7d004000 { +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- smsc@2 { /* SMSC 10/100T Ethernet Controller */ +- compatible = "usb424,9e00"; +- reg = <2>; +- local-mac-address = [00 11 22 33 44 55]; +- }; +- }; +- +- usb-phy@7d004000 { +- vbus-supply = <&vdd_smsc>; +- status = "okay"; +- }; +- +- usb@7d008000 { +- status = "okay"; +- }; +- +- usb-phy@7d008000 { +- vbus-supply = <&usb3_vbus_reg>; +- status = "okay"; +- }; +- +- /* PMIC has a built-in 32KHz oscillator which is used by PMC */ +- clk32k_in: clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "pmic-oscillator"; +- }; +- +- cpus { +- cpu0: cpu@0 { +- operating-points-v2 = <&cpu0_opp_table>; +- cpu-supply = <&vdd_cpu>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- operating-points-v2 = <&cpu0_opp_table>; +- cpu-supply = <&vdd_cpu>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- operating-points-v2 = <&cpu0_opp_table>; +- cpu-supply = <&vdd_cpu>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- operating-points-v2 = <&cpu0_opp_table>; +- cpu-supply = <&vdd_cpu>; +- #cooling-cells = <2>; +- }; +- }; +- +- firmware { +- trusted-foundations { +- compatible = "tlm,trusted-foundations"; +- tlm,version-major = <0x0>; +- tlm,version-minor = <0x0>; +- }; +- }; +- +- fan: gpio_fan { +- compatible = "gpio-fan"; +- gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>; +- gpio-fan,speed-map = <0 0 +- 4500 1>; +- #cooling-cells = <2>; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay = <5000>; +- polling-delay-passive = <5000>; +- +- thermal-sensors = <&cpu_temp 1>; +- +- trips { +- cpu_alert0: cpu-alert0 { +- temperature = <50000>; +- hysteresis = <10000>; +- type = "active"; +- }; +- cpu_alert1: cpu-alert1 { +- temperature = <70000>; +- hysteresis = <5000>; +- type = "passive"; +- }; +- cpu_crit: cpu-crit { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu_alert1>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&actmon THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- vdd_12v_in: vdd_12v_in { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_12v_in"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- }; +- +- sdmmc_3v3_reg: sdmmc_3v3_reg { +- compatible = "regulator-fixed"; +- regulator-name = "sdmmc_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- regulator-always-on; +- gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; +- vin-supply = <&sys_3v3_reg>; +- }; +- +- vdd_fuse_3v3_reg: vdd_fuse_3v3_reg { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_fuse_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; +- vin-supply = <&sys_3v3_reg>; +- regulator-always-on; +- }; +- +- vdd_vid_reg: vdd_vid_reg { +- compatible = "regulator-fixed"; +- regulator-name = "vddio_vid"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; +- vin-supply = <&vdd_5v0_reg>; +- regulator-boot-on; +- }; +- +- ddr_reg: ddr_reg { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_ddr"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- enable-active-high; +- gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; +- regulator-boot-on; +- vin-supply = <&vdd_12v_in>; +- }; +- +- sys_3v3_reg: sys_3v3_reg { +- compatible = "regulator-fixed"; +- regulator-name = "sys_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_12v_in>; +- }; +- +- vdd_5v0_reg: vdd_5v0_reg { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_12v_in>; +- }; +- +- vdd_smsc: vdd_smsc { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_smsc"; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>; +- }; +- +- usb3_vbus_reg: usb3_vbus_reg { +- compatible = "regulator-fixed"; +- regulator-name = "usb3_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; +- vin-supply = <&vdd_5v0_reg>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; +- debounce-interval = <10>; +- linux,code = ; +- wakeup-event-action = ; +- wakeup-source; +- }; +- }; +- +- +- leds { +- compatible = "gpio-leds"; +- +- led-power { +- label = "power-led"; +- gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- retain-state-suspended; +- }; +- }; +-}; +-&mc_timings { +- emc-timings-0 { +- nvidia,ram-code = <0>; /* Samsung RAM */ +- timing-25500000 { +- clock-frequency = <25500000>; +- nvidia,emem-configuration = < +- 0x00030003 /* MC_EMEM_ARB_CFG */ +- 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ +- 0x75830303 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- timing-51000000 { +- clock-frequency = <51000000>; +- nvidia,emem-configuration = < +- 0x00010003 /* MC_EMEM_ARB_CFG */ +- 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ +- 0x74630303 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- timing-102000000 { +- clock-frequency = <102000000>; +- nvidia,emem-configuration = < +- 0x00000003 /* MC_EMEM_ARB_CFG */ +- 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ +- 0x73c30504 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- timing-204000000 { +- clock-frequency = <204000000>; +- nvidia,emem-configuration = < +- 0x00000006 /* MC_EMEM_ARB_CFG */ +- 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ +- 0x73840a06 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- timing-400000000 { +- clock-frequency = <400000000>; +- nvidia,emem-configuration = < +- 0x0000000c /* MC_EMEM_ARB_CFG */ +- 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ +- 0x7086120a /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- timing-800000000 { +- clock-frequency = <800000000>; +- nvidia,emem-configuration = < +- 0x00000018 /* MC_EMEM_ARB_CFG */ +- 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ +- 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ +- 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ +- 0x712c2414 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- }; +- emc-timings-1 { +- nvidia,ram-code = <1>; /* Hynix M RAM */ +- timing-25500000 { +- clock-frequency = <25500000>; +- nvidia,emem-configuration = < +- 0x00030003 /* MC_EMEM_ARB_CFG */ +- 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ +- 0x75830303 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- timing-51000000 { +- clock-frequency = <51000000>; +- nvidia,emem-configuration = < +- 0x00010003 /* MC_EMEM_ARB_CFG */ +- 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ +- 0x74630303 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- timing-102000000 { +- clock-frequency = <102000000>; +- nvidia,emem-configuration = < +- 0x00000003 /* MC_EMEM_ARB_CFG */ +- 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ +- 0x73c30504 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- timing-204000000 { +- clock-frequency = <204000000>; +- nvidia,emem-configuration = < +- 0x00000006 /* MC_EMEM_ARB_CFG */ +- 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ +- 0x73840a06 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- timing-400000000 { +- clock-frequency = <400000000>; +- nvidia,emem-configuration = < +- 0x0000000c /* MC_EMEM_ARB_CFG */ +- 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ +- 0x7086120a /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- timing-800000000 { +- clock-frequency = <800000000>; +- nvidia,emem-configuration = < +- 0x00000018 /* MC_EMEM_ARB_CFG */ +- 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ +- 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ +- 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ +- 0x712c2414 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- }; +- emc-timings-2 { +- nvidia,ram-code = <2>; /* Hynix A RAM */ +- timing-25500000 { +- clock-frequency = <25500000>; +- nvidia,emem-configuration = < +- 0x00030003 /* MC_EMEM_ARB_CFG */ +- 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ +- 0x75e30303 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- timing-51000000 { +- clock-frequency = <51000000>; +- nvidia,emem-configuration = < +- 0x00010003 /* MC_EMEM_ARB_CFG */ +- 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ +- 0x74e30303 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- timing-102000000 { +- clock-frequency = <102000000>; +- nvidia,emem-configuration = < +- 0x00000003 /* MC_EMEM_ARB_CFG */ +- 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ +- 0x74430504 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- timing-204000000 { +- clock-frequency = <204000000>; +- nvidia,emem-configuration = < +- 0x00000006 /* MC_EMEM_ARB_CFG */ +- 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ +- 0x74040a06 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- timing-400000000 { +- clock-frequency = <400000000>; +- nvidia,emem-configuration = < +- 0x0000000c /* MC_EMEM_ARB_CFG */ +- 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ +- 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ +- 0x7086120a /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- timing-800000000 { +- clock-frequency = <800000000>; +- nvidia,emem-configuration = < +- 0x00000018 /* MC_EMEM_ARB_CFG */ +- 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ +- 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ +- 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ +- 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ +- 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ +- 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ +- 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ +- 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ +- 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ +- 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ +- 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ +- 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ +- 0x712c2414 /* MC_EMEM_ARB_MISC0 */ +- 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ +- >; +- }; +- }; +-}; +-&emc_timings { +- emc-timings-0 { +- nvidia,ram-code = <0>; /* Samsung RAM */ +- timing-25500000 { +- clock-frequency = <25500000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-periodic-qrst; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-configuration = < +- 0x00000001 /* EMC_RC */ +- 0x00000006 /* EMC_RFC */ +- 0x00000000 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x000000c0 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000007 /* EMC_TXSR */ +- 0x00000007 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000002 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x000000c7 /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x007800a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00000000 /* EMC_ZCAL_INTERVAL */ +- 0x00000040 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- timing-51000000 { +- clock-frequency = <51000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-periodic-qrst; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-configuration = < +- 0x00000002 /* EMC_RC */ +- 0x0000000d /* EMC_RFC */ +- 0x00000001 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x00000181 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x0000000e /* EMC_TXSR */ +- 0x0000000e /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000003 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x0000018e /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x007800a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00000000 /* EMC_ZCAL_INTERVAL */ +- 0x00000040 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- timing-102000000 { +- clock-frequency = <102000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-periodic-qrst; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-configuration = < +- 0x00000004 /* EMC_RC */ +- 0x0000001a /* EMC_RFC */ +- 0x00000003 /* EMC_RAS */ +- 0x00000001 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000001 /* EMC_RD_RCD */ +- 0x00000001 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x00000303 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x0000001c /* EMC_TXSR */ +- 0x0000001c /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x0000031c /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x007800a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00000000 /* EMC_ZCAL_INTERVAL */ +- 0x00000040 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- timing-204000000 { +- clock-frequency = <204000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-periodic-qrst; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-configuration = < +- 0x00000009 /* EMC_RC */ +- 0x00000035 /* EMC_RFC */ +- 0x00000007 /* EMC_RAS */ +- 0x00000002 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000002 /* EMC_RD_RCD */ +- 0x00000002 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x00000607 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000038 /* EMC_TXSR */ +- 0x00000038 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000009 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000638 /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000006 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x004400a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00080000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00020000 /* EMC_ZCAL_INTERVAL */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- timing-400000000 { +- clock-frequency = <400000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200000>; +- nvidia,emc-mode-reset = <0x80000521>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-configuration = < +- 0x00000012 /* EMC_RC */ +- 0x00000066 /* EMC_RFC */ +- 0x0000000c /* EMC_RAS */ +- 0x00000004 /* EMC_RP */ +- 0x00000003 /* EMC_R2W */ +- 0x00000008 /* EMC_W2R */ +- 0x00000002 /* EMC_R2P */ +- 0x0000000a /* EMC_W2P */ +- 0x00000004 /* EMC_RD_RCD */ +- 0x00000004 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000004 /* EMC_WDV */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000c /* EMC_RDV */ +- 0x00000bf0 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000001 /* EMC_PDEX2WR */ +- 0x00000008 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000008 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x0000006c /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000010 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000c30 /* EMC_TREFBW */ +- 0x00000000 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00007088 /* EMC_FBIO_CFG5 */ +- 0x001d0084 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800013d /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f508 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x080001e8 /* EMC_XM2QUSEPADCTRL */ +- 0x08000021 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00020000 /* EMC_ZCAL_INTERVAL */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x0158000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff89 /* EMC_CFG_RSV */ +- >; +- }; +- timing-800000000 { +- clock-frequency = <800000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200018>; +- nvidia,emc-mode-reset = <0x80000d71>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-periodic-qrst; +- nvidia,emc-configuration = < +- 0x00000025 /* EMC_RC */ +- 0x000000ce /* EMC_RFC */ +- 0x0000001a /* EMC_RAS */ +- 0x00000009 /* EMC_RP */ +- 0x00000005 /* EMC_R2W */ +- 0x0000000d /* EMC_W2R */ +- 0x00000004 /* EMC_R2P */ +- 0x00000013 /* EMC_W2P */ +- 0x00000009 /* EMC_RD_RCD */ +- 0x00000009 /* EMC_WR_RCD */ +- 0x00000004 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000007 /* EMC_WDV */ +- 0x0000000a /* EMC_QUSE */ +- 0x00000009 /* EMC_QRST */ +- 0x0000000b /* EMC_QSAFE */ +- 0x00000011 /* EMC_RDV */ +- 0x00001820 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000003 /* EMC_PDEX2WR */ +- 0x00000012 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x0000000f /* EMC_AR2PDEN */ +- 0x00000018 /* EMC_RW2PDEN */ +- 0x000000d8 /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000005 /* EMC_TCKE */ +- 0x00000020 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000007 /* EMC_TCLKSTABLE */ +- 0x00000008 /* EMC_TCLKSTOP */ +- 0x00001860 /* EMC_TREFBW */ +- 0x0000000b /* EMC_QUSE_EXTRA */ +- 0x00000006 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00005088 /* EMC_FBIO_CFG5 */ +- 0xf0070191 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x0000800a /* EMC_DLL_XFORM_DQS0 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS1 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS2 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS3 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS4 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS5 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS6 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS7 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ0 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ1 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ2 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0600013d /* EMC_XM2DQSPADCTRL2 */ +- 0x22220000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f501 /* EMC_XM2COMPPADCTRL */ +- 0x07077404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x080001e8 /* EMC_XM2QUSEPADCTRL */ +- 0x08000021 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00020000 /* EMC_ZCAL_INTERVAL */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x00f0000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff49 /* EMC_CFG_RSV */ +- >; +- }; +- }; +- emc-timings-1 { +- nvidia,ram-code = <1>; /* Hynix M RAM */ +- timing-25500000 { +- clock-frequency = <25500000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-periodic-qrst; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-configuration = < +- 0x00000001 /* EMC_RC */ +- 0x00000006 /* EMC_RFC */ +- 0x00000000 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x000000c0 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000007 /* EMC_TXSR */ +- 0x00000007 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000002 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x000000c7 /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x007800a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00000000 /* EMC_ZCAL_INTERVAL */ +- 0x00000040 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- timing-51000000 { +- clock-frequency = <51000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-periodic-qrst; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-configuration = < +- 0x00000002 /* EMC_RC */ +- 0x0000000d /* EMC_RFC */ +- 0x00000001 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x00000181 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x0000000e /* EMC_TXSR */ +- 0x0000000e /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000003 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x0000018e /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x007800a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00000000 /* EMC_ZCAL_INTERVAL */ +- 0x00000040 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- timing-102000000 { +- clock-frequency = <102000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-periodic-qrst; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-configuration = < +- 0x00000004 /* EMC_RC */ +- 0x0000001a /* EMC_RFC */ +- 0x00000003 /* EMC_RAS */ +- 0x00000001 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000001 /* EMC_RD_RCD */ +- 0x00000001 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x00000303 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x0000001c /* EMC_TXSR */ +- 0x0000001c /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x0000031c /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x007800a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00000000 /* EMC_ZCAL_INTERVAL */ +- 0x00000040 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- timing-204000000 { +- clock-frequency = <204000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-periodic-qrst; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-configuration = < +- 0x00000009 /* EMC_RC */ +- 0x00000035 /* EMC_RFC */ +- 0x00000007 /* EMC_RAS */ +- 0x00000002 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000002 /* EMC_RD_RCD */ +- 0x00000002 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x00000607 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000038 /* EMC_TXSR */ +- 0x00000038 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000009 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000638 /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000006 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x004400a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00080000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00020000 /* EMC_ZCAL_INTERVAL */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- timing-400000000 { +- clock-frequency = <400000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200000>; +- nvidia,emc-mode-reset = <0x80000521>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-configuration = < +- 0x00000012 /* EMC_RC */ +- 0x00000066 /* EMC_RFC */ +- 0x0000000c /* EMC_RAS */ +- 0x00000004 /* EMC_RP */ +- 0x00000003 /* EMC_R2W */ +- 0x00000008 /* EMC_W2R */ +- 0x00000002 /* EMC_R2P */ +- 0x0000000a /* EMC_W2P */ +- 0x00000004 /* EMC_RD_RCD */ +- 0x00000004 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000004 /* EMC_WDV */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000c /* EMC_RDV */ +- 0x00000bf0 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000001 /* EMC_PDEX2WR */ +- 0x00000008 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000008 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x0000006c /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000010 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000c30 /* EMC_TREFBW */ +- 0x00000000 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00007088 /* EMC_FBIO_CFG5 */ +- 0x001d0084 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ +- 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00048000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800013d /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f508 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x080001e8 /* EMC_XM2QUSEPADCTRL */ +- 0x08000021 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00020000 /* EMC_ZCAL_INTERVAL */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x0158000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff89 /* EMC_CFG_RSV */ +- >; +- }; +- timing-800000000 { +- clock-frequency = <800000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200018>; +- nvidia,emc-mode-reset = <0x80000d71>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-periodic-qrst; +- nvidia,emc-configuration = < +- 0x00000025 /* EMC_RC */ +- 0x000000ce /* EMC_RFC */ +- 0x0000001a /* EMC_RAS */ +- 0x00000009 /* EMC_RP */ +- 0x00000005 /* EMC_R2W */ +- 0x0000000d /* EMC_W2R */ +- 0x00000004 /* EMC_R2P */ +- 0x00000013 /* EMC_W2P */ +- 0x00000009 /* EMC_RD_RCD */ +- 0x00000009 /* EMC_WR_RCD */ +- 0x00000004 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000007 /* EMC_WDV */ +- 0x0000000a /* EMC_QUSE */ +- 0x00000009 /* EMC_QRST */ +- 0x0000000b /* EMC_QSAFE */ +- 0x00000011 /* EMC_RDV */ +- 0x00001820 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000003 /* EMC_PDEX2WR */ +- 0x00000012 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x0000000f /* EMC_AR2PDEN */ +- 0x00000018 /* EMC_RW2PDEN */ +- 0x000000d8 /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000005 /* EMC_TCKE */ +- 0x00000020 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000007 /* EMC_TCLKSTABLE */ +- 0x00000008 /* EMC_TCLKSTOP */ +- 0x00001860 /* EMC_TREFBW */ +- 0x0000000b /* EMC_QUSE_EXTRA */ +- 0x00000006 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00005088 /* EMC_FBIO_CFG5 */ +- 0xf0070191 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x0000800a /* EMC_DLL_XFORM_DQS0 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS1 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS2 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS3 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS4 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS5 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS6 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS7 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ0 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ1 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ2 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0600013d /* EMC_XM2DQSPADCTRL2 */ +- 0x22220000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f501 /* EMC_XM2COMPPADCTRL */ +- 0x07077404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x080001e8 /* EMC_XM2QUSEPADCTRL */ +- 0x08000021 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00020000 /* EMC_ZCAL_INTERVAL */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x00f0000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff49 /* EMC_CFG_RSV */ +- >; +- }; +- }; +- emc-timings-2 { +- nvidia,ram-code = <2>; /* Hynix A RAM */ +- timing-25500000 { +- clock-frequency = <25500000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-periodic-qrst; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-configuration = < +- 0x00000001 /* EMC_RC */ +- 0x00000007 /* EMC_RFC */ +- 0x00000000 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x000000c0 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000008 /* EMC_TXSR */ +- 0x00000008 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000002 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x000000c7 /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x007800a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00000000 /* EMC_ZCAL_INTERVAL */ +- 0x00000040 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- timing-51000000 { +- clock-frequency = <51000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-periodic-qrst; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-configuration = < +- 0x00000002 /* EMC_RC */ +- 0x0000000f /* EMC_RFC */ +- 0x00000001 /* EMC_RAS */ +- 0x00000000 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000000 /* EMC_RD_RCD */ +- 0x00000000 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x00000181 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000010 /* EMC_TXSR */ +- 0x00000010 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000003 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x0000018e /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x007800a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00000000 /* EMC_ZCAL_INTERVAL */ +- 0x00000040 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- timing-102000000 { +- clock-frequency = <102000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-periodic-qrst; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-configuration = < +- 0x00000004 /* EMC_RC */ +- 0x0000001e /* EMC_RFC */ +- 0x00000003 /* EMC_RAS */ +- 0x00000001 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000001 /* EMC_RD_RCD */ +- 0x00000001 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x00000303 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000020 /* EMC_TXSR */ +- 0x00000020 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000005 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x0000031c /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x007800a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ +- 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00000000 /* EMC_ZCAL_INTERVAL */ +- 0x00000040 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- timing-204000000 { +- clock-frequency = <204000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100003>; +- nvidia,emc-mode-2 = <0x80200008>; +- nvidia,emc-mode-reset = <0x80001221>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-periodic-qrst; +- nvidia,emc-cfg-dyn-self-ref; +- nvidia,emc-configuration = < +- 0x00000009 /* EMC_RC */ +- 0x0000003d /* EMC_RFC */ +- 0x00000007 /* EMC_RAS */ +- 0x00000002 /* EMC_RP */ +- 0x00000002 /* EMC_R2W */ +- 0x0000000a /* EMC_W2R */ +- 0x00000005 /* EMC_R2P */ +- 0x0000000b /* EMC_W2P */ +- 0x00000002 /* EMC_RD_RCD */ +- 0x00000002 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000005 /* EMC_WDV */ +- 0x00000005 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000b /* EMC_RDV */ +- 0x00000607 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000002 /* EMC_PDEX2WR */ +- 0x00000002 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000007 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x00000040 /* EMC_TXSR */ +- 0x00000040 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000009 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000638 /* EMC_TREFBW */ +- 0x00000006 /* EMC_QUSE_EXTRA */ +- 0x00000006 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00004288 /* EMC_FBIO_CFG5 */ +- 0x004400a4 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00080000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00080000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00080000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800211c /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f108 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x08000168 /* EMC_XM2QUSEPADCTRL */ +- 0x08000000 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00020000 /* EMC_ZCAL_INTERVAL */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x000c000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff00 /* EMC_CFG_RSV */ +- >; +- }; +- timing-400000000 { +- clock-frequency = <400000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200000>; +- nvidia,emc-mode-reset = <0x80000521>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-configuration = < +- 0x00000012 /* EMC_RC */ +- 0x00000076 /* EMC_RFC */ +- 0x0000000c /* EMC_RAS */ +- 0x00000004 /* EMC_RP */ +- 0x00000003 /* EMC_R2W */ +- 0x00000008 /* EMC_W2R */ +- 0x00000002 /* EMC_R2P */ +- 0x0000000a /* EMC_W2P */ +- 0x00000004 /* EMC_RD_RCD */ +- 0x00000004 /* EMC_WR_RCD */ +- 0x00000002 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000004 /* EMC_WDV */ +- 0x00000006 /* EMC_QUSE */ +- 0x00000004 /* EMC_QRST */ +- 0x0000000a /* EMC_QSAFE */ +- 0x0000000c /* EMC_RDV */ +- 0x00000bf0 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000001 /* EMC_PDEX2WR */ +- 0x00000008 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x00000008 /* EMC_AR2PDEN */ +- 0x0000000f /* EMC_RW2PDEN */ +- 0x0000007c /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000004 /* EMC_TCKE */ +- 0x00000010 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000004 /* EMC_TCLKSTABLE */ +- 0x00000005 /* EMC_TCLKSTOP */ +- 0x00000c30 /* EMC_TREFBW */ +- 0x00000000 /* EMC_QUSE_EXTRA */ +- 0x00000004 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00007088 /* EMC_FBIO_CFG5 */ +- 0x001d0084 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x00044000 /* EMC_DLL_XFORM_DQS0 */ +- 0x00044000 /* EMC_DLL_XFORM_DQS1 */ +- 0x00044000 /* EMC_DLL_XFORM_DQS2 */ +- 0x00044000 /* EMC_DLL_XFORM_DQS3 */ +- 0x00044000 /* EMC_DLL_XFORM_DQS4 */ +- 0x00044000 /* EMC_DLL_XFORM_DQS5 */ +- 0x00044000 /* EMC_DLL_XFORM_DQS6 */ +- 0x00044000 /* EMC_DLL_XFORM_DQS7 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x00058000 /* EMC_DLL_XFORM_DQ0 */ +- 0x00058000 /* EMC_DLL_XFORM_DQ1 */ +- 0x00058000 /* EMC_DLL_XFORM_DQ2 */ +- 0x00058000 /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0800013d /* EMC_XM2DQSPADCTRL2 */ +- 0x00000000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f508 /* EMC_XM2COMPPADCTRL */ +- 0x05057404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x080001e8 /* EMC_XM2QUSEPADCTRL */ +- 0x08000021 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00020000 /* EMC_ZCAL_INTERVAL */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x0148000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff89 /* EMC_CFG_RSV */ +- >; +- }; +- timing-800000000 { +- clock-frequency = <800000000>; +- nvidia,emc-auto-cal-interval = <0x001fffff>; +- nvidia,emc-mode-1 = <0x80100002>; +- nvidia,emc-mode-2 = <0x80200018>; +- nvidia,emc-mode-reset = <0x80000d71>; +- nvidia,emc-zcal-cnt-long = <0x00000040>; +- nvidia,emc-cfg-periodic-qrst; +- nvidia,emc-configuration = < +- 0x00000025 /* EMC_RC */ +- 0x000000ee /* EMC_RFC */ +- 0x0000001a /* EMC_RAS */ +- 0x00000009 /* EMC_RP */ +- 0x00000005 /* EMC_R2W */ +- 0x0000000d /* EMC_W2R */ +- 0x00000004 /* EMC_R2P */ +- 0x00000013 /* EMC_W2P */ +- 0x00000009 /* EMC_RD_RCD */ +- 0x00000009 /* EMC_WR_RCD */ +- 0x00000003 /* EMC_RRD */ +- 0x00000001 /* EMC_REXT */ +- 0x00000000 /* EMC_WEXT */ +- 0x00000007 /* EMC_WDV */ +- 0x0000000a /* EMC_QUSE */ +- 0x00000009 /* EMC_QRST */ +- 0x0000000b /* EMC_QSAFE */ +- 0x00000011 /* EMC_RDV */ +- 0x00001820 /* EMC_REFRESH */ +- 0x00000000 /* EMC_BURST_REFRESH_NUM */ +- 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ +- 0x00000003 /* EMC_PDEX2WR */ +- 0x00000012 /* EMC_PDEX2RD */ +- 0x00000001 /* EMC_PCHG2PDEN */ +- 0x00000000 /* EMC_ACT2PDEN */ +- 0x0000000f /* EMC_AR2PDEN */ +- 0x00000018 /* EMC_RW2PDEN */ +- 0x000000f8 /* EMC_TXSR */ +- 0x00000200 /* EMC_TXSRDLL */ +- 0x00000005 /* EMC_TCKE */ +- 0x00000020 /* EMC_TFAW */ +- 0x00000000 /* EMC_TRPAB */ +- 0x00000007 /* EMC_TCLKSTABLE */ +- 0x00000008 /* EMC_TCLKSTOP */ +- 0x00001860 /* EMC_TREFBW */ +- 0x0000000b /* EMC_QUSE_EXTRA */ +- 0x00000006 /* EMC_FBIO_CFG6 */ +- 0x00000000 /* EMC_ODT_WRITE */ +- 0x00000000 /* EMC_ODT_READ */ +- 0x00005088 /* EMC_FBIO_CFG5 */ +- 0xf0070191 /* EMC_CFG_DIG_DLL */ +- 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ +- 0x0000000c /* EMC_DLL_XFORM_DQS0 */ +- 0x007fc00a /* EMC_DLL_XFORM_DQS1 */ +- 0x00000008 /* EMC_DLL_XFORM_DQS2 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS3 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS4 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS5 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS6 */ +- 0x0000000a /* EMC_DLL_XFORM_DQS7 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ +- 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ +- 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ0 */ +- 0x0000000c /* EMC_DLL_XFORM_DQ1 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ2 */ +- 0x0000000a /* EMC_DLL_XFORM_DQ3 */ +- 0x000002a0 /* EMC_XM2CMDPADCTRL */ +- 0x0600013d /* EMC_XM2DQSPADCTRL2 */ +- 0x22220000 /* EMC_XM2DQPADCTRL2 */ +- 0x77fff884 /* EMC_XM2CLKPADCTRL */ +- 0x01f1f501 /* EMC_XM2COMPPADCTRL */ +- 0x07077404 /* EMC_XM2VTTGENPADCTRL */ +- 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ +- 0x080001e8 /* EMC_XM2QUSEPADCTRL */ +- 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ +- 0x00000802 /* EMC_CTT_TERM_CTRL */ +- 0x00020000 /* EMC_ZCAL_INTERVAL */ +- 0x00000100 /* EMC_ZCAL_WAIT_CNT */ +- 0x00d0000c /* EMC_MRS_WAIT_CNT */ +- 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ +- 0x00000000 /* EMC_CTT */ +- 0x00000000 /* EMC_CTT_DURATION */ +- 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ +- 0xe8000000 /* EMC_FBIO_SPARE */ +- 0xff00ff49 /* EMC_CFG_RSV */ +- >; +- }; +- }; +-}; +-&state_default { +- clk_32k_out_pa0 { +- nvidia,pins = "clk_32k_out_pa0"; +- nvidia,function = "blink"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_cts_n_pa1 { +- nvidia,pins = "uart3_cts_n_pa1"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_fs_pa2 { +- nvidia,pins = "dap2_fs_pa2"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_sclk_pa3 { +- nvidia,pins = "dap2_sclk_pa3"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_din_pa4 { +- nvidia,pins = "dap2_din_pa4"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_dout_pa5 { +- nvidia,pins = "dap2_dout_pa5"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_clk_pa6 { +- nvidia,pins = "sdmmc3_clk_pa6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_cmd_pa7 { +- nvidia,pins = "sdmmc3_cmd_pa7"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_a17_pb0 { +- nvidia,pins = "gmi_a17_pb0"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_a18_pb1 { +- nvidia,pins = "gmi_a18_pb1"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_pwr0_pb2 { +- nvidia,pins = "lcd_pwr0_pb2"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_pclk_pb3 { +- nvidia,pins = "lcd_pclk_pb3"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat3_pb4 { +- nvidia,pins = "sdmmc3_dat3_pb4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat2_pb5 { +- nvidia,pins = "sdmmc3_dat2_pb5"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat1_pb6 { +- nvidia,pins = "sdmmc3_dat1_pb6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat0_pb7 { +- nvidia,pins = "sdmmc3_dat0_pb7"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_rts_n_pc0 { +- nvidia,pins = "uart3_rts_n_pc0"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_pwr1_pc1 { +- nvidia,pins = "lcd_pwr1_pc1"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_txd_pc2 { +- nvidia,pins = "uart2_txd_pc2"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_rxd_pc3 { +- nvidia,pins = "uart2_rxd_pc3"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gen1_i2c_scl_pc4 { +- nvidia,pins = "gen1_i2c_scl_pc4"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen1_i2c_sda_pc5 { +- nvidia,pins = "gen1_i2c_sda_pc5"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_pwr2_pc6 { +- nvidia,pins = "lcd_pwr2_pc6"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_wp_n_pc7 { +- nvidia,pins = "gmi_wp_n_pc7"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat5_pd0 { +- nvidia,pins = "sdmmc3_dat5_pd0"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat4_pd1 { +- nvidia,pins = "sdmmc3_dat4_pd1"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_dc1_pd2 { +- nvidia,pins = "lcd_dc1_pd2"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat6_pd3 { +- nvidia,pins = "sdmmc3_dat6_pd3"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_dat7_pd4 { +- nvidia,pins = "sdmmc3_dat7_pd4"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d1_pd5 { +- nvidia,pins = "vi_d1_pd5"; +- nvidia,function = "sdmmc2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_vsync_pd6 { +- nvidia,pins = "vi_vsync_pd6"; +- nvidia,function = "ddr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_hsync_pd7 { +- nvidia,pins = "vi_hsync_pd7"; +- nvidia,function = "ddr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d0_pe0 { +- nvidia,pins = "lcd_d0_pe0"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d1_pe1 { +- nvidia,pins = "lcd_d1_pe1"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d2_pe2 { +- nvidia,pins = "lcd_d2_pe2"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d3_pe3 { +- nvidia,pins = "lcd_d3_pe3"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d4_pe4 { +- nvidia,pins = "lcd_d4_pe4"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d5_pe5 { +- nvidia,pins = "lcd_d5_pe5"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d6_pe6 { +- nvidia,pins = "lcd_d6_pe6"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d7_pe7 { +- nvidia,pins = "lcd_d7_pe7"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d8_pf0 { +- nvidia,pins = "lcd_d8_pf0"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d9_pf1 { +- nvidia,pins = "lcd_d9_pf1"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d10_pf2 { +- nvidia,pins = "lcd_d10_pf2"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d11_pf3 { +- nvidia,pins = "lcd_d11_pf3"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d12_pf4 { +- nvidia,pins = "lcd_d12_pf4"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d13_pf5 { +- nvidia,pins = "lcd_d13_pf5"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d14_pf6 { +- nvidia,pins = "lcd_d14_pf6"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d15_pf7 { +- nvidia,pins = "lcd_d15_pf7"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad0_pg0 { +- nvidia,pins = "gmi_ad0_pg0"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad1_pg1 { +- nvidia,pins = "gmi_ad1_pg1"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad2_pg2 { +- nvidia,pins = "gmi_ad2_pg2"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad3_pg3 { +- nvidia,pins = "gmi_ad3_pg3"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad4_pg4 { +- nvidia,pins = "gmi_ad4_pg4"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad5_pg5 { +- nvidia,pins = "gmi_ad5_pg5"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad6_pg6 { +- nvidia,pins = "gmi_ad6_pg6"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad7_pg7 { +- nvidia,pins = "gmi_ad7_pg7"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad8_ph0 { +- nvidia,pins = "gmi_ad8_ph0"; +- nvidia,function = "pwm0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad9_ph1 { +- nvidia,pins = "gmi_ad9_ph1"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad10_ph2 { +- nvidia,pins = "gmi_ad10_ph2"; +- nvidia,function = "pwm2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad11_ph3 { +- nvidia,pins = "gmi_ad11_ph3"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad12_ph4 { +- nvidia,pins = "gmi_ad12_ph4"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad13_ph5 { +- nvidia,pins = "gmi_ad13_ph5"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_ad14_ph6 { +- nvidia,pins = "gmi_ad14_ph6"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_wr_n_pi0 { +- nvidia,pins = "gmi_wr_n_pi0"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_oe_n_pi1 { +- nvidia,pins = "gmi_oe_n_pi1"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_dqs_pi2 { +- nvidia,pins = "gmi_dqs_pi2"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_iordy_pi5 { +- nvidia,pins = "gmi_iordy_pi5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_cs7_n_pi6 { +- nvidia,pins = "gmi_cs7_n_pi6"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_wait_pi7 { +- nvidia,pins = "gmi_wait_pi7"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_de_pj1 { +- nvidia,pins = "lcd_de_pj1"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_cs1_n_pj2 { +- nvidia,pins = "gmi_cs1_n_pj2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_hsync_pj3 { +- nvidia,pins = "lcd_hsync_pj3"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_vsync_pj4 { +- nvidia,pins = "lcd_vsync_pj4"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_cts_n_pj5 { +- nvidia,pins = "uart2_cts_n_pj5"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart2_rts_n_pj6 { +- nvidia,pins = "uart2_rts_n_pj6"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_a16_pj7 { +- nvidia,pins = "gmi_a16_pj7"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_adv_n_pk0 { +- nvidia,pins = "gmi_adv_n_pk0"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_clk_pk1 { +- nvidia,pins = "gmi_clk_pk1"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_cs2_n_pk3 { +- nvidia,pins = "gmi_cs2_n_pk3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_cs3_n_pk4 { +- nvidia,pins = "gmi_cs3_n_pk4"; +- nvidia,function = "nand"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spdif_out_pk5 { +- nvidia,pins = "spdif_out_pk5"; +- nvidia,function = "spdif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spdif_in_pk6 { +- nvidia,pins = "spdif_in_pk6"; +- nvidia,function = "spdif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gmi_a19_pk7 { +- nvidia,pins = "gmi_a19_pk7"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d2_pl0 { +- nvidia,pins = "vi_d2_pl0"; +- nvidia,function = "sdmmc2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d3_pl1 { +- nvidia,pins = "vi_d3_pl1"; +- nvidia,function = "sdmmc2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d4_pl2 { +- nvidia,pins = "vi_d4_pl2"; +- nvidia,function = "vi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d5_pl3 { +- nvidia,pins = "vi_d5_pl3"; +- nvidia,function = "sdmmc2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d6_pl4 { +- nvidia,pins = "vi_d6_pl4"; +- nvidia,function = "vi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d7_pl5 { +- nvidia,pins = "vi_d7_pl5"; +- nvidia,function = "sdmmc2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d8_pl6 { +- nvidia,pins = "vi_d8_pl6"; +- nvidia,function = "sdmmc2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d9_pl7 { +- nvidia,pins = "vi_d9_pl7"; +- nvidia,function = "sdmmc2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d16_pm0 { +- nvidia,pins = "lcd_d16_pm0"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d17_pm1 { +- nvidia,pins = "lcd_d17_pm1"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d18_pm2 { +- nvidia,pins = "lcd_d18_pm2"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d19_pm3 { +- nvidia,pins = "lcd_d19_pm3"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d20_pm4 { +- nvidia,pins = "lcd_d20_pm4"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d21_pm5 { +- nvidia,pins = "lcd_d21_pm5"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d22_pm6 { +- nvidia,pins = "lcd_d22_pm6"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_d23_pm7 { +- nvidia,pins = "lcd_d23_pm7"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_fs_pn0 { +- nvidia,pins = "dap1_fs_pn0"; +- nvidia,function = "i2s0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_din_pn1 { +- nvidia,pins = "dap1_din_pn1"; +- nvidia,function = "i2s0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_dout_pn2 { +- nvidia,pins = "dap1_dout_pn2"; +- nvidia,function = "i2s0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap1_sclk_pn3 { +- nvidia,pins = "dap1_sclk_pn3"; +- nvidia,function = "i2s0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_cs0_n_pn4 { +- nvidia,pins = "lcd_cs0_n_pn4"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_sdout_pn5 { +- nvidia,pins = "lcd_sdout_pn5"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_dc0_pn6 { +- nvidia,pins = "lcd_dc0_pn6"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- hdmi_int_pn7 { +- nvidia,pins = "hdmi_int_pn7"; +- nvidia,function = "hdmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data7_po0 { +- nvidia,pins = "ulpi_data7_po0"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data0_po1 { +- nvidia,pins = "ulpi_data0_po1"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data1_po2 { +- nvidia,pins = "ulpi_data1_po2"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data2_po3 { +- nvidia,pins = "ulpi_data2_po3"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data3_po4 { +- nvidia,pins = "ulpi_data3_po4"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data4_po5 { +- nvidia,pins = "ulpi_data4_po5"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data5_po6 { +- nvidia,pins = "ulpi_data5_po6"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_data6_po7 { +- nvidia,pins = "ulpi_data6_po7"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_fs_pp0 { +- nvidia,pins = "dap3_fs_pp0"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_din_pp1 { +- nvidia,pins = "dap3_din_pp1"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_dout_pp2 { +- nvidia,pins = "dap3_dout_pp2"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_sclk_pp3 { +- nvidia,pins = "dap3_sclk_pp3"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_fs_pp4 { +- nvidia,pins = "dap4_fs_pp4"; +- nvidia,function = "i2s3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_din_pp5 { +- nvidia,pins = "dap4_din_pp5"; +- nvidia,function = "i2s3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_dout_pp6 { +- nvidia,pins = "dap4_dout_pp6"; +- nvidia,function = "i2s3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap4_sclk_pp7 { +- nvidia,pins = "dap4_sclk_pp7"; +- nvidia,function = "i2s3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col0_pq0 { +- nvidia,pins = "kb_col0_pq0"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col1_pq1 { +- nvidia,pins = "kb_col1_pq1"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col2_pq2 { +- nvidia,pins = "kb_col2_pq2"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col3_pq3 { +- nvidia,pins = "kb_col3_pq3"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col4_pq4 { +- nvidia,pins = "kb_col4_pq4"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col5_pq5 { +- nvidia,pins = "kb_col5_pq5"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col6_pq6 { +- nvidia,pins = "kb_col6_pq6"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col7_pq7 { +- nvidia,pins = "kb_col7_pq7"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row0_pr0 { +- nvidia,pins = "kb_row0_pr0"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row1_pr1 { +- nvidia,pins = "kb_row1_pr1"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row2_pr2 { +- nvidia,pins = "kb_row2_pr2"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row3_pr3 { +- nvidia,pins = "kb_row3_pr3"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row4_pr4 { +- nvidia,pins = "kb_row4_pr4"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row5_pr5 { +- nvidia,pins = "kb_row5_pr5"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row6_pr6 { +- nvidia,pins = "kb_row6_pr6"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row7_pr7 { +- nvidia,pins = "kb_row7_pr7"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row8_ps0 { +- nvidia,pins = "kb_row8_ps0"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row9_ps1 { +- nvidia,pins = "kb_row9_ps1"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row10_ps2 { +- nvidia,pins = "kb_row10_ps2"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row11_ps3 { +- nvidia,pins = "kb_row11_ps3"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row12_ps4 { +- nvidia,pins = "kb_row12_ps4"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row13_ps5 { +- nvidia,pins = "kb_row13_ps5"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row14_ps6 { +- nvidia,pins = "kb_row14_ps6"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row15_ps7 { +- nvidia,pins = "kb_row15_ps7"; +- nvidia,function = "kbc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_pclk_pt0 { +- nvidia,pins = "vi_pclk_pt0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_mclk_pt1 { +- nvidia,pins = "vi_mclk_pt1"; +- nvidia,function = "vi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d10_pt2 { +- nvidia,pins = "vi_d10_pt2"; +- nvidia,function = "ddr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d11_pt3 { +- nvidia,pins = "vi_d11_pt3"; +- nvidia,function = "ddr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- vi_d0_pt4 { +- nvidia,pins = "vi_d0_pt4"; +- nvidia,function = "ddr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gen2_i2c_scl_pt5 { +- nvidia,pins = "gen2_i2c_scl_pt5"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen2_i2c_sda_pt6 { +- nvidia,pins = "gen2_i2c_sda_pt6"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc4_cmd_pt7 { +- nvidia,pins = "sdmmc4_cmd_pt7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,io-reset = ; +- }; +- pu0 { +- nvidia,pins = "pu0"; +- nvidia,function = "owr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu1 { +- nvidia,pins = "pu1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu2 { +- nvidia,pins = "pu2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu3 { +- nvidia,pins = "pu3"; +- nvidia,function = "pwm0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu4 { +- nvidia,pins = "pu4"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu5 { +- nvidia,pins = "pu5"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pu6 { +- nvidia,pins = "pu6"; +- nvidia,function = "pwm3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- jtag_rtck_pu7 { +- nvidia,pins = "jtag_rtck_pu7"; +- nvidia,function = "rtck"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv0 { +- nvidia,pins = "pv0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv1 { +- nvidia,pins = "pv1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv2 { +- nvidia,pins = "pv2"; +- nvidia,function = "owr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pv3 { +- nvidia,pins = "pv3"; +- nvidia,function = "clk_12m_out"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ddc_scl_pv4 { +- nvidia,pins = "ddc_scl_pv4"; +- nvidia,function = "i2c4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ddc_sda_pv5 { +- nvidia,pins = "ddc_sda_pv5"; +- nvidia,function = "i2c4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- crt_hsync_pv6 { +- nvidia,pins = "crt_hsync_pv6"; +- nvidia,function = "crt"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- crt_vsync_pv7 { +- nvidia,pins = "crt_vsync_pv7"; +- nvidia,function = "crt"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_cs1_n_pw0 { +- nvidia,pins = "lcd_cs1_n_pw0"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_m1_pw1 { +- nvidia,pins = "lcd_m1_pw1"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi2_cs1_n_pw2 { +- nvidia,pins = "spi2_cs1_n_pw2"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk1_out_pw4 { +- nvidia,pins = "clk1_out_pw4"; +- nvidia,function = "extperiph1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk2_out_pw5 { +- nvidia,pins = "clk2_out_pw5"; +- nvidia,function = "extperiph2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_txd_pw6 { +- nvidia,pins = "uart3_txd_pw6"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- uart3_rxd_pw7 { +- nvidia,pins = "uart3_rxd_pw7"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi2_sck_px2 { +- nvidia,pins = "spi2_sck_px2"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi1_mosi_px4 { +- nvidia,pins = "spi1_mosi_px4"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi1_sck_px5 { +- nvidia,pins = "spi1_sck_px5"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi1_cs0_n_px6 { +- nvidia,pins = "spi1_cs0_n_px6"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spi1_miso_px7 { +- nvidia,pins = "spi1_miso_px7"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_clk_py0 { +- nvidia,pins = "ulpi_clk_py0"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_dir_py1 { +- nvidia,pins = "ulpi_dir_py1"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_nxt_py2 { +- nvidia,pins = "ulpi_nxt_py2"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_stp_py3 { +- nvidia,pins = "ulpi_stp_py3"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat3_py4 { +- nvidia,pins = "sdmmc1_dat3_py4"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat2_py5 { +- nvidia,pins = "sdmmc1_dat2_py5"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat1_py6 { +- nvidia,pins = "sdmmc1_dat1_py6"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_dat0_py7 { +- nvidia,pins = "sdmmc1_dat0_py7"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_clk_pz0 { +- nvidia,pins = "sdmmc1_clk_pz0"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_cmd_pz1 { +- nvidia,pins = "sdmmc1_cmd_pz1"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_sdin_pz2 { +- nvidia,pins = "lcd_sdin_pz2"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_wr_n_pz3 { +- nvidia,pins = "lcd_wr_n_pz3"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_sck_pz4 { +- nvidia,pins = "lcd_sck_pz4"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sys_clk_req_pz5 { +- nvidia,pins = "sys_clk_req_pz5"; +- nvidia,function = "sysclk"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pwr_i2c_scl_pz6 { +- nvidia,pins = "pwr_i2c_scl_pz6"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pwr_i2c_sda_pz7 { +- nvidia,pins = "pwr_i2c_sda_pz7"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc4_dat0_paa0 { +- nvidia,pins = "sdmmc4_dat0_paa0"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,io-reset = ; +- }; +- sdmmc4_dat1_paa1 { +- nvidia,pins = "sdmmc4_dat1_paa1"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,io-reset = ; +- }; +- sdmmc4_dat2_paa2 { +- nvidia,pins = "sdmmc4_dat2_paa2"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,io-reset = ; +- }; +- sdmmc4_dat3_paa3 { +- nvidia,pins = "sdmmc4_dat3_paa3"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,io-reset = ; +- }; +- sdmmc4_dat4_paa4 { +- nvidia,pins = "sdmmc4_dat4_paa4"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,io-reset = ; +- }; +- sdmmc4_dat5_paa5 { +- nvidia,pins = "sdmmc4_dat5_paa5"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,io-reset = ; +- }; +- sdmmc4_dat6_paa6 { +- nvidia,pins = "sdmmc4_dat6_paa6"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,io-reset = ; +- }; +- sdmmc4_dat7_paa7 { +- nvidia,pins = "sdmmc4_dat7_paa7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,io-reset = ; +- }; +- pbb0 { +- nvidia,pins = "pbb0"; +- nvidia,function = "i2s4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cam_i2c_scl_pbb1 { +- nvidia,pins = "cam_i2c_scl_pbb1"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_i2c_sda_pbb2 { +- nvidia,pins = "cam_i2c_sda_pbb2"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pbb3 { +- nvidia,pins = "pbb3"; +- nvidia,function = "vgp3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb4 { +- nvidia,pins = "pbb4"; +- nvidia,function = "vgp4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb5 { +- nvidia,pins = "pbb5"; +- nvidia,function = "vgp5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb6 { +- nvidia,pins = "pbb6"; +- nvidia,function = "vgp6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pbb7 { +- nvidia,pins = "pbb7"; +- nvidia,function = "i2s4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cam_mclk_pcc0 { +- nvidia,pins = "cam_mclk_pcc0"; +- nvidia,function = "vi_alt3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pcc1 { +- nvidia,pins = "pcc1"; +- nvidia,function = "i2s4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pcc2 { +- nvidia,pins = "pcc2"; +- nvidia,function = "i2s4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_rst_n_pcc3 { +- nvidia,pins = "sdmmc4_rst_n_pcc3"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,io-reset = ; +- }; +- sdmmc4_clk_pcc4 { +- nvidia,pins = "sdmmc4_clk_pcc4"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,io-reset = ; +- }; +- clk2_req_pcc5 { +- nvidia,pins = "clk2_req_pcc5"; +- nvidia,function = "dap"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l2_rst_n_pcc6 { +- nvidia,pins = "pex_l2_rst_n_pcc6"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l2_clkreq_n_pcc7 { +- nvidia,pins = "pex_l2_clkreq_n_pcc7"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l0_prsnt_n_pdd0 { +- nvidia,pins = "pex_l0_prsnt_n_pdd0"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l0_rst_n_pdd1 { +- nvidia,pins = "pex_l0_rst_n_pdd1"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l0_clkreq_n_pdd2 { +- nvidia,pins = "pex_l0_clkreq_n_pdd2"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_wake_n_pdd3 { +- nvidia,pins = "pex_wake_n_pdd3"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l1_prsnt_n_pdd4 { +- nvidia,pins = "pex_l1_prsnt_n_pdd4"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l1_rst_n_pdd5 { +- nvidia,pins = "pex_l1_rst_n_pdd5"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l1_clkreq_n_pdd6 { +- nvidia,pins = "pex_l1_clkreq_n_pdd6"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pex_l2_prsnt_n_pdd7 { +- nvidia,pins = "pex_l2_prsnt_n_pdd7"; +- nvidia,function = "pcie"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3_out_pee0 { +- nvidia,pins = "clk3_out_pee0"; +- nvidia,function = "extperiph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3_req_pee1 { +- nvidia,pins = "clk3_req_pee1"; +- nvidia,function = "dev3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk1_req_pee2 { +- nvidia,pins = "clk1_req_pee2"; +- nvidia,function = "dap"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- hdmi_cec_pee3 { +- nvidia,pins = "hdmi_cec_pee3"; +- nvidia,function = "cec"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- owr { +- nvidia,pins = "owr"; +- nvidia,function = "owr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- drive_groups { +- nvidia,pins = "drive_gma", +- "drive_gmb", +- "drive_gmc", +- "drive_gmd"; +- nvidia,pull-down-strength = <9>; +- nvidia,pull-up-strength = <9>; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- }; +-}; +- +-&emc_icc_dvfs_opp_table { +- /delete-node/ opp@900000000,1350; +-}; +- +-&emc_bw_dfs_opp_table { +- /delete-node/ opp@900000000; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30-peripherals-opp.dtsi b/scripts/dtc/include-prefixes/arm/tegra30-peripherals-opp.dtsi +deleted file mode 100644 +index 2c9780319725..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30-peripherals-opp.dtsi ++++ /dev/null +@@ -1,386 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/ { +- emc_icc_dvfs_opp_table: emc-dvfs-opp-table { +- compatible = "operating-points-v2"; +- +- opp@12750000,950 { +- opp-microvolt = <950000 950000 1350000>; +- opp-hz = /bits/ 64 <12750000>; +- opp-supported-hw = <0x0006>; +- }; +- +- opp@12750000,1000 { +- opp-microvolt = <1000000 1000000 1350000>; +- opp-hz = /bits/ 64 <12750000>; +- opp-supported-hw = <0x0001>; +- }; +- +- opp@12750000,1250 { +- opp-microvolt = <1250000 1250000 1350000>; +- opp-hz = /bits/ 64 <12750000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@25500000,950 { +- opp-microvolt = <950000 950000 1350000>; +- opp-hz = /bits/ 64 <25500000>; +- opp-supported-hw = <0x0006>; +- }; +- +- opp@25500000,1000 { +- opp-microvolt = <1000000 1000000 1350000>; +- opp-hz = /bits/ 64 <25500000>; +- opp-supported-hw = <0x0001>; +- }; +- +- opp@25500000,1250 { +- opp-microvolt = <1250000 1250000 1350000>; +- opp-hz = /bits/ 64 <25500000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@27000000,950 { +- opp-microvolt = <950000 950000 1350000>; +- opp-hz = /bits/ 64 <27000000>; +- opp-supported-hw = <0x0006>; +- }; +- +- opp@27000000,1000 { +- opp-microvolt = <1000000 1000000 1350000>; +- opp-hz = /bits/ 64 <27000000>; +- opp-supported-hw = <0x0001>; +- }; +- +- opp@27000000,1250 { +- opp-microvolt = <1250000 1250000 1350000>; +- opp-hz = /bits/ 64 <27000000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@51000000,950 { +- opp-microvolt = <950000 950000 1350000>; +- opp-hz = /bits/ 64 <51000000>; +- opp-supported-hw = <0x0006>; +- }; +- +- opp@51000000,1000 { +- opp-microvolt = <1000000 1000000 1350000>; +- opp-hz = /bits/ 64 <51000000>; +- opp-supported-hw = <0x0001>; +- }; +- +- opp@51000000,1250 { +- opp-microvolt = <1250000 1250000 1350000>; +- opp-hz = /bits/ 64 <51000000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@54000000,950 { +- opp-microvolt = <950000 950000 1350000>; +- opp-hz = /bits/ 64 <54000000>; +- opp-supported-hw = <0x0006>; +- }; +- +- opp@54000000,1000 { +- opp-microvolt = <1000000 1000000 1350000>; +- opp-hz = /bits/ 64 <54000000>; +- opp-supported-hw = <0x0001>; +- }; +- +- opp@54000000,1250 { +- opp-microvolt = <1250000 1250000 1350000>; +- opp-hz = /bits/ 64 <54000000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@102000000,950 { +- opp-microvolt = <950000 950000 1350000>; +- opp-hz = /bits/ 64 <102000000>; +- opp-supported-hw = <0x0006>; +- }; +- +- opp@102000000,1000 { +- opp-microvolt = <1000000 1000000 1350000>; +- opp-hz = /bits/ 64 <102000000>; +- opp-supported-hw = <0x0001>; +- }; +- +- opp@102000000,1250 { +- opp-microvolt = <1250000 1250000 1350000>; +- opp-hz = /bits/ 64 <102000000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@108000000,1000 { +- opp-microvolt = <1000000 1000000 1350000>; +- opp-hz = /bits/ 64 <108000000>; +- opp-supported-hw = <0x0007>; +- }; +- +- opp@108000000,1250 { +- opp-microvolt = <1250000 1250000 1350000>; +- opp-hz = /bits/ 64 <108000000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@204000000,1000 { +- opp-microvolt = <1000000 1000000 1350000>; +- opp-hz = /bits/ 64 <204000000>; +- opp-supported-hw = <0x0007>; +- opp-suspend; +- }; +- +- opp@204000000,1250 { +- opp-microvolt = <1250000 1250000 1350000>; +- opp-hz = /bits/ 64 <204000000>; +- opp-supported-hw = <0x0008>; +- opp-suspend; +- }; +- +- opp@333500000,1000 { +- opp-microvolt = <1000000 1000000 1350000>; +- opp-hz = /bits/ 64 <333500000>; +- opp-supported-hw = <0x0006>; +- }; +- +- opp@333500000,1200 { +- opp-microvolt = <1200000 1200000 1350000>; +- opp-hz = /bits/ 64 <333500000>; +- opp-supported-hw = <0x0001>; +- }; +- +- opp@333500000,1250 { +- opp-microvolt = <1250000 1250000 1350000>; +- opp-hz = /bits/ 64 <333500000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@375000000,1000 { +- opp-microvolt = <1000000 1000000 1350000>; +- opp-hz = /bits/ 64 <375000000>; +- opp-supported-hw = <0x0006>; +- }; +- +- opp@375000000,1200 { +- opp-microvolt = <1200000 1200000 1350000>; +- opp-hz = /bits/ 64 <375000000>; +- opp-supported-hw = <0x0001>; +- }; +- +- opp@375000000,1250 { +- opp-microvolt = <1250000 1250000 1350000>; +- opp-hz = /bits/ 64 <375000000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@400000000,1000 { +- opp-microvolt = <1000000 1000000 1350000>; +- opp-hz = /bits/ 64 <400000000>; +- opp-supported-hw = <0x0006>; +- }; +- +- opp@400000000,1200 { +- opp-microvolt = <1200000 1200000 1350000>; +- opp-hz = /bits/ 64 <400000000>; +- opp-supported-hw = <0x0001>; +- }; +- +- opp@400000000,1250 { +- opp-microvolt = <1250000 1250000 1350000>; +- opp-hz = /bits/ 64 <400000000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@416000000,1200 { +- opp-microvolt = <1200000 1200000 1350000>; +- opp-hz = /bits/ 64 <416000000>; +- opp-supported-hw = <0x0007>; +- }; +- +- opp@416000000,1250 { +- opp-microvolt = <1250000 1250000 1350000>; +- opp-hz = /bits/ 64 <416000000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@450000000,1200 { +- opp-microvolt = <1200000 1200000 1350000>; +- opp-hz = /bits/ 64 <450000000>; +- opp-supported-hw = <0x0007>; +- }; +- +- opp@450000000,1250 { +- opp-microvolt = <1250000 1250000 1350000>; +- opp-hz = /bits/ 64 <450000000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@533000000,1200 { +- opp-microvolt = <1200000 1200000 1350000>; +- opp-hz = /bits/ 64 <533000000>; +- opp-supported-hw = <0x0007>; +- }; +- +- opp@533000000,1250 { +- opp-microvolt = <1250000 1250000 1350000>; +- opp-hz = /bits/ 64 <533000000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@625000000,1200 { +- opp-microvolt = <1200000 1200000 1350000>; +- opp-hz = /bits/ 64 <625000000>; +- opp-supported-hw = <0x0006>; +- }; +- +- opp@625000000,1250 { +- opp-microvolt = <1250000 1250000 1350000>; +- opp-hz = /bits/ 64 <625000000>; +- opp-supported-hw = <0x0008>; +- }; +- +- opp@667000000,1200 { +- opp-microvolt = <1200000 1200000 1350000>; +- opp-hz = /bits/ 64 <667000000>; +- opp-supported-hw = <0x0006>; +- }; +- +- opp@750000000,1300 { +- opp-microvolt = <1300000 1300000 1350000>; +- opp-hz = /bits/ 64 <750000000>; +- opp-supported-hw = <0x0004>; +- }; +- +- opp@800000000,1300 { +- opp-microvolt = <1300000 1300000 1350000>; +- opp-hz = /bits/ 64 <800000000>; +- opp-supported-hw = <0x0004>; +- }; +- +- opp@900000000,1350 { +- opp-microvolt = <1350000 1350000 1350000>; +- opp-hz = /bits/ 64 <900000000>; +- opp-supported-hw = <0x0004>; +- }; +- }; +- +- emc_bw_dfs_opp_table: emc-bandwidth-opp-table { +- compatible = "operating-points-v2"; +- +- opp@12750000 { +- opp-hz = /bits/ 64 <12750000>; +- opp-supported-hw = <0x000F>; +- opp-peak-kBps = <102000>; +- }; +- +- opp@25500000 { +- opp-hz = /bits/ 64 <25500000>; +- opp-supported-hw = <0x000F>; +- opp-peak-kBps = <204000>; +- }; +- +- opp@27000000 { +- opp-hz = /bits/ 64 <27000000>; +- opp-supported-hw = <0x000F>; +- opp-peak-kBps = <216000>; +- }; +- +- opp@51000000 { +- opp-hz = /bits/ 64 <51000000>; +- opp-supported-hw = <0x000F>; +- opp-peak-kBps = <408000>; +- }; +- +- opp@54000000 { +- opp-hz = /bits/ 64 <54000000>; +- opp-supported-hw = <0x000F>; +- opp-peak-kBps = <432000>; +- }; +- +- opp@102000000 { +- opp-hz = /bits/ 64 <102000000>; +- opp-supported-hw = <0x000F>; +- opp-peak-kBps = <816000>; +- }; +- +- opp@108000000 { +- opp-hz = /bits/ 64 <108000000>; +- opp-supported-hw = <0x000F>; +- opp-peak-kBps = <864000>; +- }; +- +- opp@204000000 { +- opp-hz = /bits/ 64 <204000000>; +- opp-supported-hw = <0x000F>; +- opp-peak-kBps = <1632000>; +- opp-suspend; +- }; +- +- opp@333500000 { +- opp-hz = /bits/ 64 <333500000>; +- opp-supported-hw = <0x000F>; +- opp-peak-kBps = <2668000>; +- }; +- +- opp@375000000 { +- opp-hz = /bits/ 64 <375000000>; +- opp-supported-hw = <0x000F>; +- opp-peak-kBps = <3000000>; +- }; +- +- opp@400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-supported-hw = <0x000F>; +- opp-peak-kBps = <3200000>; +- }; +- +- opp@416000000 { +- opp-hz = /bits/ 64 <416000000>; +- opp-supported-hw = <0x000F>; +- opp-peak-kBps = <3328000>; +- }; +- +- opp@450000000 { +- opp-hz = /bits/ 64 <450000000>; +- opp-supported-hw = <0x000F>; +- opp-peak-kBps = <3600000>; +- }; +- +- opp@533000000 { +- opp-hz = /bits/ 64 <533000000>; +- opp-supported-hw = <0x000F>; +- opp-peak-kBps = <4264000>; +- }; +- +- opp@625000000 { +- opp-hz = /bits/ 64 <625000000>; +- opp-supported-hw = <0x000E>; +- opp-peak-kBps = <5000000>; +- }; +- +- opp@667000000 { +- opp-hz = /bits/ 64 <667000000>; +- opp-supported-hw = <0x0006>; +- opp-peak-kBps = <5336000>; +- }; +- +- opp@750000000 { +- opp-hz = /bits/ 64 <750000000>; +- opp-supported-hw = <0x0004>; +- opp-peak-kBps = <6000000>; +- }; +- +- opp@800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-supported-hw = <0x0004>; +- opp-peak-kBps = <6400000>; +- }; +- +- opp@900000000 { +- opp-hz = /bits/ 64 <900000000>; +- opp-supported-hw = <0x0004>; +- opp-peak-kBps = <7200000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tegra30.dtsi b/scripts/dtc/include-prefixes/arm/tegra30.dtsi +deleted file mode 100644 +index eaf4951d9ff8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tegra30.dtsi ++++ /dev/null +@@ -1,1184 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include "tegra30-peripherals-opp.dtsi" +- +-/ { +- compatible = "nvidia,tegra30"; +- interrupt-parent = <&lic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x0>; +- }; +- +- pcie@3000 { +- compatible = "nvidia,tegra30-pcie"; +- device_type = "pci"; +- reg = <0x00003000 0x00000800>, /* PADS registers */ +- <0x00003800 0x00000200>, /* AFI registers */ +- <0x10000000 0x10000000>; /* configuration space */ +- reg-names = "pads", "afi", "cs"; +- interrupts = , /* controller interrupt */ +- ; /* MSI interrupt */ +- interrupt-names = "intr", "msi"; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; +- +- bus-range = <0x00 0xff>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */ +- <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */ +- <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */ +- <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */ +- <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */ +- <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ +- +- clocks = <&tegra_car TEGRA30_CLK_PCIE>, +- <&tegra_car TEGRA30_CLK_AFI>, +- <&tegra_car TEGRA30_CLK_PLL_E>, +- <&tegra_car TEGRA30_CLK_CML0>; +- clock-names = "pex", "afi", "pll_e", "cml"; +- resets = <&tegra_car 70>, +- <&tegra_car 72>, +- <&tegra_car 74>; +- reset-names = "pex", "afi", "pcie_x"; +- status = "disabled"; +- +- pci@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; +- reg = <0x000800 0 0 0 0>; +- bus-range = <0x00 0xff>; +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- ranges; +- +- nvidia,num-lanes = <2>; +- }; +- +- pci@2,0 { +- device_type = "pci"; +- assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; +- reg = <0x001000 0 0 0 0>; +- bus-range = <0x00 0xff>; +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- ranges; +- +- nvidia,num-lanes = <2>; +- }; +- +- pci@3,0 { +- device_type = "pci"; +- assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; +- reg = <0x001800 0 0 0 0>; +- bus-range = <0x00 0xff>; +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- ranges; +- +- nvidia,num-lanes = <2>; +- }; +- }; +- +- sram@40000000 { +- compatible = "mmio-sram"; +- reg = <0x40000000 0x40000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x40000000 0x40000>; +- +- vde_pool: sram@400 { +- reg = <0x400 0x3fc00>; +- pool; +- }; +- }; +- +- host1x@50000000 { +- compatible = "nvidia,tegra30-host1x"; +- reg = <0x50000000 0x00024000>; +- interrupts = , /* syncpt */ +- ; /* general */ +- interrupt-names = "syncpt", "host1x"; +- clocks = <&tegra_car TEGRA30_CLK_HOST1X>; +- clock-names = "host1x"; +- resets = <&tegra_car 28>; +- reset-names = "host1x"; +- iommus = <&mc TEGRA_SWGROUP_HC>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0x54000000 0x54000000 0x04000000>; +- +- mpe@54040000 { +- compatible = "nvidia,tegra30-mpe"; +- reg = <0x54040000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_MPE>; +- resets = <&tegra_car 60>; +- reset-names = "mpe"; +- +- iommus = <&mc TEGRA_SWGROUP_MPE>; +- }; +- +- vi@54080000 { +- compatible = "nvidia,tegra30-vi"; +- reg = <0x54080000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_VI>; +- resets = <&tegra_car 20>; +- reset-names = "vi"; +- +- iommus = <&mc TEGRA_SWGROUP_VI>; +- }; +- +- epp@540c0000 { +- compatible = "nvidia,tegra30-epp"; +- reg = <0x540c0000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_EPP>; +- resets = <&tegra_car 19>; +- reset-names = "epp"; +- +- iommus = <&mc TEGRA_SWGROUP_EPP>; +- }; +- +- isp@54100000 { +- compatible = "nvidia,tegra30-isp"; +- reg = <0x54100000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_ISP>; +- resets = <&tegra_car 23>; +- reset-names = "isp"; +- +- iommus = <&mc TEGRA_SWGROUP_ISP>; +- }; +- +- gr2d@54140000 { +- compatible = "nvidia,tegra30-gr2d"; +- reg = <0x54140000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_GR2D>; +- resets = <&tegra_car 21>; +- reset-names = "2d"; +- +- iommus = <&mc TEGRA_SWGROUP_G2>; +- }; +- +- gr3d@54180000 { +- compatible = "nvidia,tegra30-gr3d"; +- reg = <0x54180000 0x00040000>; +- clocks = <&tegra_car TEGRA30_CLK_GR3D>, +- <&tegra_car TEGRA30_CLK_GR3D2>; +- clock-names = "3d", "3d2"; +- resets = <&tegra_car 24>, +- <&tegra_car 98>; +- reset-names = "3d", "3d2"; +- +- iommus = <&mc TEGRA_SWGROUP_NV>, +- <&mc TEGRA_SWGROUP_NV2>; +- }; +- +- dc@54200000 { +- compatible = "nvidia,tegra30-dc"; +- reg = <0x54200000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_DISP1>, +- <&tegra_car TEGRA30_CLK_PLL_P>; +- clock-names = "dc", "parent"; +- resets = <&tegra_car 27>; +- reset-names = "dc"; +- +- iommus = <&mc TEGRA_SWGROUP_DC>; +- +- nvidia,head = <0>; +- +- interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>, +- <&mc TEGRA30_MC_DISPLAY0B &emc>, +- <&mc TEGRA30_MC_DISPLAY1B &emc>, +- <&mc TEGRA30_MC_DISPLAY0C &emc>, +- <&mc TEGRA30_MC_DISPLAYHC &emc>; +- interconnect-names = "wina", +- "winb", +- "winb-vfilter", +- "winc", +- "cursor"; +- +- rgb { +- status = "disabled"; +- }; +- }; +- +- dc@54240000 { +- compatible = "nvidia,tegra30-dc"; +- reg = <0x54240000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_DISP2>, +- <&tegra_car TEGRA30_CLK_PLL_P>; +- clock-names = "dc", "parent"; +- resets = <&tegra_car 26>; +- reset-names = "dc"; +- +- iommus = <&mc TEGRA_SWGROUP_DCB>; +- +- nvidia,head = <1>; +- +- interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>, +- <&mc TEGRA30_MC_DISPLAY0BB &emc>, +- <&mc TEGRA30_MC_DISPLAY1BB &emc>, +- <&mc TEGRA30_MC_DISPLAY0CB &emc>, +- <&mc TEGRA30_MC_DISPLAYHCB &emc>; +- interconnect-names = "wina", +- "winb", +- "winb-vfilter", +- "winc", +- "cursor"; +- +- rgb { +- status = "disabled"; +- }; +- }; +- +- hdmi@54280000 { +- compatible = "nvidia,tegra30-hdmi"; +- reg = <0x54280000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_HDMI>, +- <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; +- clock-names = "hdmi", "parent"; +- resets = <&tegra_car 51>; +- reset-names = "hdmi"; +- status = "disabled"; +- }; +- +- tvo@542c0000 { +- compatible = "nvidia,tegra30-tvo"; +- reg = <0x542c0000 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_TVO>; +- status = "disabled"; +- }; +- +- dsi@54300000 { +- compatible = "nvidia,tegra30-dsi"; +- reg = <0x54300000 0x00040000>; +- clocks = <&tegra_car TEGRA30_CLK_DSIA>, +- <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; +- clock-names = "dsi", "parent"; +- resets = <&tegra_car 48>; +- reset-names = "dsi"; +- status = "disabled"; +- }; +- +- dsi@54400000 { +- compatible = "nvidia,tegra30-dsi"; +- reg = <0x54400000 0x00040000>; +- clocks = <&tegra_car TEGRA30_CLK_DSIB>, +- <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; +- clock-names = "dsi", "parent"; +- resets = <&tegra_car 84>; +- reset-names = "dsi"; +- status = "disabled"; +- }; +- }; +- +- timer@50040600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x50040600 0x20>; +- interrupt-parent = <&intc>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_TWD>; +- }; +- +- intc: interrupt-controller@50041000 { +- compatible = "arm,cortex-a9-gic"; +- reg = <0x50041000 0x1000>, +- <0x50040100 0x0100>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&intc>; +- }; +- +- cache-controller@50043000 { +- compatible = "arm,pl310-cache"; +- reg = <0x50043000 0x1000>; +- arm,data-latency = <6 6 2>; +- arm,tag-latency = <5 5 2>; +- cache-unified; +- cache-level = <2>; +- }; +- +- lic: interrupt-controller@60004000 { +- compatible = "nvidia,tegra30-ictlr"; +- reg = <0x60004000 0x100>, +- <0x60004100 0x50>, +- <0x60004200 0x50>, +- <0x60004300 0x50>, +- <0x60004400 0x50>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&intc>; +- }; +- +- timer@60005000 { +- compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; +- reg = <0x60005000 0x400>; +- interrupts = , +- , +- , +- , +- , +- ; +- clocks = <&tegra_car TEGRA30_CLK_TIMER>; +- }; +- +- tegra_car: clock@60006000 { +- compatible = "nvidia,tegra30-car"; +- reg = <0x60006000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- flow-controller@60007000 { +- compatible = "nvidia,tegra30-flowctrl"; +- reg = <0x60007000 0x1000>; +- }; +- +- apbdma: dma@6000a000 { +- compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; +- reg = <0x6000a000 0x1400>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&tegra_car TEGRA30_CLK_APBDMA>; +- resets = <&tegra_car 34>; +- reset-names = "dma"; +- #dma-cells = <1>; +- }; +- +- ahb: ahb@6000c000 { +- compatible = "nvidia,tegra30-ahb"; +- reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ +- }; +- +- actmon: actmon@6000c800 { +- compatible = "nvidia,tegra30-actmon"; +- reg = <0x6000c800 0x400>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_ACTMON>, +- <&tegra_car TEGRA30_CLK_EMC>; +- clock-names = "actmon", "emc"; +- resets = <&tegra_car TEGRA30_CLK_ACTMON>; +- reset-names = "actmon"; +- operating-points-v2 = <&emc_bw_dfs_opp_table>; +- interconnects = <&mc TEGRA30_MC_MPCORER &emc>; +- interconnect-names = "cpu-read"; +- #cooling-cells = <2>; +- }; +- +- gpio: gpio@6000d000 { +- compatible = "nvidia,tegra30-gpio"; +- reg = <0x6000d000 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- #gpio-cells = <2>; +- gpio-controller; +- #interrupt-cells = <2>; +- interrupt-controller; +- /* +- gpio-ranges = <&pinmux 0 0 248>; +- */ +- }; +- +- vde@6001a000 { +- compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde"; +- reg = <0x6001a000 0x1000>, /* Syntax Engine */ +- <0x6001b000 0x1000>, /* Video Bitstream Engine */ +- <0x6001c000 0x100>, /* Macroblock Engine */ +- <0x6001c200 0x100>, /* Post-processing Engine */ +- <0x6001c400 0x100>, /* Motion Compensation Engine */ +- <0x6001c600 0x100>, /* Transform Engine */ +- <0x6001c800 0x100>, /* Pixel prediction block */ +- <0x6001ca00 0x100>, /* Video DMA */ +- <0x6001d800 0x400>; /* Video frame controls */ +- reg-names = "sxe", "bsev", "mbe", "ppe", "mce", +- "tfe", "ppb", "vdma", "frameid"; +- iram = <&vde_pool>; /* IRAM region */ +- interrupts = , /* Sync token interrupt */ +- , /* BSE-V interrupt */ +- ; /* SXE interrupt */ +- interrupt-names = "sync-token", "bsev", "sxe"; +- clocks = <&tegra_car TEGRA30_CLK_VDE>; +- reset-names = "vde", "mc"; +- resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>; +- iommus = <&mc TEGRA_SWGROUP_VDE>; +- }; +- +- apbmisc@70000800 { +- compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; +- reg = <0x70000800 0x64>, /* Chip revision */ +- <0x70000008 0x04>; /* Strapping options */ +- }; +- +- pinmux: pinmux@70000868 { +- compatible = "nvidia,tegra30-pinmux"; +- reg = <0x70000868 0x0d4>, /* Pad control registers */ +- <0x70003000 0x3e4>; /* Mux registers */ +- }; +- +- /* +- * There are two serial driver i.e. 8250 based simple serial +- * driver and APB DMA based serial driver for higher baudrate +- * and performace. To enable the 8250 based driver, the compatible +- * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable +- * the APB DMA based serial driver, the compatible is +- * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". +- */ +- uarta: serial@70006000 { +- compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; +- reg = <0x70006000 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_UARTA>; +- resets = <&tegra_car 6>; +- reset-names = "serial"; +- dmas = <&apbdma 8>, <&apbdma 8>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uartb: serial@70006040 { +- compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; +- reg = <0x70006040 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_UARTB>; +- resets = <&tegra_car 7>; +- reset-names = "serial"; +- dmas = <&apbdma 9>, <&apbdma 9>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uartc: serial@70006200 { +- compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; +- reg = <0x70006200 0x100>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_UARTC>; +- resets = <&tegra_car 55>; +- reset-names = "serial"; +- dmas = <&apbdma 10>, <&apbdma 10>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uartd: serial@70006300 { +- compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; +- reg = <0x70006300 0x100>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_UARTD>; +- resets = <&tegra_car 65>; +- reset-names = "serial"; +- dmas = <&apbdma 19>, <&apbdma 19>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uarte: serial@70006400 { +- compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; +- reg = <0x70006400 0x100>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_UARTE>; +- resets = <&tegra_car 66>; +- reset-names = "serial"; +- dmas = <&apbdma 20>, <&apbdma 20>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- gmi@70009000 { +- compatible = "nvidia,tegra30-gmi"; +- reg = <0x70009000 0x1000>; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0 0x48000000 0x7ffffff>; +- clocks = <&tegra_car TEGRA30_CLK_NOR>; +- clock-names = "gmi"; +- resets = <&tegra_car 42>; +- reset-names = "gmi"; +- status = "disabled"; +- }; +- +- pwm: pwm@7000a000 { +- compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; +- reg = <0x7000a000 0x100>; +- #pwm-cells = <2>; +- clocks = <&tegra_car TEGRA30_CLK_PWM>; +- resets = <&tegra_car 17>; +- reset-names = "pwm"; +- status = "disabled"; +- }; +- +- rtc@7000e000 { +- compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; +- reg = <0x7000e000 0x100>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_RTC>; +- }; +- +- i2c@7000c000 { +- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; +- reg = <0x7000c000 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA30_CLK_I2C1>, +- <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; +- clock-names = "div-clk", "fast-clk"; +- resets = <&tegra_car 12>; +- reset-names = "i2c"; +- dmas = <&apbdma 21>, <&apbdma 21>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000c400 { +- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; +- reg = <0x7000c400 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA30_CLK_I2C2>, +- <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; +- clock-names = "div-clk", "fast-clk"; +- resets = <&tegra_car 54>; +- reset-names = "i2c"; +- dmas = <&apbdma 22>, <&apbdma 22>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000c500 { +- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; +- reg = <0x7000c500 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA30_CLK_I2C3>, +- <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; +- clock-names = "div-clk", "fast-clk"; +- resets = <&tegra_car 67>; +- reset-names = "i2c"; +- dmas = <&apbdma 23>, <&apbdma 23>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000c700 { +- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; +- reg = <0x7000c700 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA30_CLK_I2C4>, +- <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; +- resets = <&tegra_car 103>; +- reset-names = "i2c"; +- clock-names = "div-clk", "fast-clk"; +- dmas = <&apbdma 26>, <&apbdma 26>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000d000 { +- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; +- reg = <0x7000d000 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA30_CLK_I2C5>, +- <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; +- clock-names = "div-clk", "fast-clk"; +- resets = <&tegra_car 47>; +- reset-names = "i2c"; +- dmas = <&apbdma 24>, <&apbdma 24>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000d400 { +- compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; +- reg = <0x7000d400 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA30_CLK_SBC1>; +- resets = <&tegra_car 41>; +- reset-names = "spi"; +- dmas = <&apbdma 15>, <&apbdma 15>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000d600 { +- compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; +- reg = <0x7000d600 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA30_CLK_SBC2>; +- resets = <&tegra_car 44>; +- reset-names = "spi"; +- dmas = <&apbdma 16>, <&apbdma 16>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000d800 { +- compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; +- reg = <0x7000d800 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA30_CLK_SBC3>; +- resets = <&tegra_car 46>; +- reset-names = "spi"; +- dmas = <&apbdma 17>, <&apbdma 17>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000da00 { +- compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; +- reg = <0x7000da00 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA30_CLK_SBC4>; +- resets = <&tegra_car 68>; +- reset-names = "spi"; +- dmas = <&apbdma 18>, <&apbdma 18>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000dc00 { +- compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; +- reg = <0x7000dc00 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA30_CLK_SBC5>; +- resets = <&tegra_car 104>; +- reset-names = "spi"; +- dmas = <&apbdma 27>, <&apbdma 27>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000de00 { +- compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; +- reg = <0x7000de00 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA30_CLK_SBC6>; +- resets = <&tegra_car 106>; +- reset-names = "spi"; +- dmas = <&apbdma 28>, <&apbdma 28>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- kbc@7000e200 { +- compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; +- reg = <0x7000e200 0x100>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_KBC>; +- resets = <&tegra_car 36>; +- reset-names = "kbc"; +- status = "disabled"; +- }; +- +- tegra_pmc: pmc@7000e400 { +- compatible = "nvidia,tegra30-pmc"; +- reg = <0x7000e400 0x400>; +- clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; +- clock-names = "pclk", "clk32k_in"; +- #clock-cells = <1>; +- }; +- +- mc: memory-controller@7000f000 { +- compatible = "nvidia,tegra30-mc"; +- reg = <0x7000f000 0x400>; +- clocks = <&tegra_car TEGRA30_CLK_MC>; +- clock-names = "mc"; +- +- interrupts = ; +- +- #iommu-cells = <1>; +- #reset-cells = <1>; +- #interconnect-cells = <1>; +- }; +- +- emc: memory-controller@7000f400 { +- compatible = "nvidia,tegra30-emc"; +- reg = <0x7000f400 0x400>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_EMC>; +- +- nvidia,memory-controller = <&mc>; +- operating-points-v2 = <&emc_icc_dvfs_opp_table>; +- +- #interconnect-cells = <0>; +- }; +- +- fuse@7000f800 { +- compatible = "nvidia,tegra30-efuse"; +- reg = <0x7000f800 0x400>; +- clocks = <&tegra_car TEGRA30_CLK_FUSE>; +- clock-names = "fuse"; +- resets = <&tegra_car 39>; +- reset-names = "fuse"; +- }; +- +- tsensor: tsensor@70014000 { +- compatible = "nvidia,tegra30-tsensor"; +- reg = <0x70014000 0x500>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_TSENSOR>; +- resets = <&tegra_car TEGRA30_CLK_TSENSOR>; +- +- assigned-clocks = <&tegra_car TEGRA30_CLK_TSENSOR>; +- assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>; +- assigned-clock-rates = <500000>; +- +- #thermal-sensor-cells = <1>; +- }; +- +- hda@70030000 { +- compatible = "nvidia,tegra30-hda"; +- reg = <0x70030000 0x10000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_HDA>, +- <&tegra_car TEGRA30_CLK_HDA2HDMI>, +- <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>; +- clock-names = "hda", "hda2hdmi", "hda2codec_2x"; +- resets = <&tegra_car 125>, /* hda */ +- <&tegra_car 128>, /* hda2hdmi */ +- <&tegra_car 111>; /* hda2codec_2x */ +- reset-names = "hda", "hda2hdmi", "hda2codec_2x"; +- status = "disabled"; +- }; +- +- ahub@70080000 { +- compatible = "nvidia,tegra30-ahub"; +- reg = <0x70080000 0x200>, +- <0x70080200 0x100>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, +- <&tegra_car TEGRA30_CLK_APBIF>; +- clock-names = "d_audio", "apbif"; +- resets = <&tegra_car 106>, /* d_audio */ +- <&tegra_car 107>, /* apbif */ +- <&tegra_car 30>, /* i2s0 */ +- <&tegra_car 11>, /* i2s1 */ +- <&tegra_car 18>, /* i2s2 */ +- <&tegra_car 101>, /* i2s3 */ +- <&tegra_car 102>, /* i2s4 */ +- <&tegra_car 108>, /* dam0 */ +- <&tegra_car 109>, /* dam1 */ +- <&tegra_car 110>, /* dam2 */ +- <&tegra_car 10>; /* spdif */ +- reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", +- "i2s3", "i2s4", "dam0", "dam1", "dam2", +- "spdif"; +- dmas = <&apbdma 1>, <&apbdma 1>, +- <&apbdma 2>, <&apbdma 2>, +- <&apbdma 3>, <&apbdma 3>, +- <&apbdma 4>, <&apbdma 4>; +- dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", +- "rx3", "tx3"; +- ranges; +- #address-cells = <1>; +- #size-cells = <1>; +- +- tegra_i2s0: i2s@70080300 { +- compatible = "nvidia,tegra30-i2s"; +- reg = <0x70080300 0x100>; +- nvidia,ahub-cif-ids = <4 4>; +- clocks = <&tegra_car TEGRA30_CLK_I2S0>; +- resets = <&tegra_car 30>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- +- tegra_i2s1: i2s@70080400 { +- compatible = "nvidia,tegra30-i2s"; +- reg = <0x70080400 0x100>; +- nvidia,ahub-cif-ids = <5 5>; +- clocks = <&tegra_car TEGRA30_CLK_I2S1>; +- resets = <&tegra_car 11>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- +- tegra_i2s2: i2s@70080500 { +- compatible = "nvidia,tegra30-i2s"; +- reg = <0x70080500 0x100>; +- nvidia,ahub-cif-ids = <6 6>; +- clocks = <&tegra_car TEGRA30_CLK_I2S2>; +- resets = <&tegra_car 18>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- +- tegra_i2s3: i2s@70080600 { +- compatible = "nvidia,tegra30-i2s"; +- reg = <0x70080600 0x100>; +- nvidia,ahub-cif-ids = <7 7>; +- clocks = <&tegra_car TEGRA30_CLK_I2S3>; +- resets = <&tegra_car 101>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- +- tegra_i2s4: i2s@70080700 { +- compatible = "nvidia,tegra30-i2s"; +- reg = <0x70080700 0x100>; +- nvidia,ahub-cif-ids = <8 8>; +- clocks = <&tegra_car TEGRA30_CLK_I2S4>; +- resets = <&tegra_car 102>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- }; +- +- mmc@78000000 { +- compatible = "nvidia,tegra30-sdhci"; +- reg = <0x78000000 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; +- clock-names = "sdhci"; +- resets = <&tegra_car 14>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- mmc@78000200 { +- compatible = "nvidia,tegra30-sdhci"; +- reg = <0x78000200 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; +- clock-names = "sdhci"; +- resets = <&tegra_car 9>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- mmc@78000400 { +- compatible = "nvidia,tegra30-sdhci"; +- reg = <0x78000400 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; +- clock-names = "sdhci"; +- resets = <&tegra_car 69>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- mmc@78000600 { +- compatible = "nvidia,tegra30-sdhci"; +- reg = <0x78000600 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; +- clock-names = "sdhci"; +- resets = <&tegra_car 15>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- usb@7d000000 { +- compatible = "nvidia,tegra30-ehci", "usb-ehci"; +- reg = <0x7d000000 0x4000>; +- interrupts = ; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA30_CLK_USBD>; +- resets = <&tegra_car 22>; +- reset-names = "usb"; +- nvidia,needs-double-reset; +- nvidia,phy = <&phy1>; +- status = "disabled"; +- }; +- +- phy1: usb-phy@7d000000 { +- compatible = "nvidia,tegra30-usb-phy"; +- reg = <0x7d000000 0x4000>, +- <0x7d000000 0x4000>; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA30_CLK_USBD>, +- <&tegra_car TEGRA30_CLK_PLL_U>, +- <&tegra_car TEGRA30_CLK_USBD>; +- clock-names = "reg", "pll_u", "utmi-pads"; +- resets = <&tegra_car 22>, <&tegra_car 22>; +- reset-names = "usb", "utmi-pads"; +- #phy-cells = <0>; +- nvidia,hssync-start-delay = <9>; +- nvidia,idle-wait-delay = <17>; +- nvidia,elastic-limit = <16>; +- nvidia,term-range-adj = <6>; +- nvidia,xcvr-setup = <51>; +- nvidia,xcvr-setup-use-fuses; +- nvidia,xcvr-lsfslew = <1>; +- nvidia,xcvr-lsrslew = <1>; +- nvidia,xcvr-hsslew = <32>; +- nvidia,hssquelch-level = <2>; +- nvidia,hsdiscon-level = <5>; +- nvidia,has-utmi-pad-registers; +- status = "disabled"; +- }; +- +- usb@7d004000 { +- compatible = "nvidia,tegra30-ehci", "usb-ehci"; +- reg = <0x7d004000 0x4000>; +- interrupts = ; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA30_CLK_USB2>; +- resets = <&tegra_car 58>; +- reset-names = "usb"; +- nvidia,phy = <&phy2>; +- status = "disabled"; +- }; +- +- phy2: usb-phy@7d004000 { +- compatible = "nvidia,tegra30-usb-phy"; +- reg = <0x7d004000 0x4000>, +- <0x7d000000 0x4000>; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA30_CLK_USB2>, +- <&tegra_car TEGRA30_CLK_PLL_U>, +- <&tegra_car TEGRA30_CLK_USBD>; +- clock-names = "reg", "pll_u", "utmi-pads"; +- resets = <&tegra_car 58>, <&tegra_car 22>; +- reset-names = "usb", "utmi-pads"; +- #phy-cells = <0>; +- nvidia,hssync-start-delay = <9>; +- nvidia,idle-wait-delay = <17>; +- nvidia,elastic-limit = <16>; +- nvidia,term-range-adj = <6>; +- nvidia,xcvr-setup = <51>; +- nvidia,xcvr-setup-use-fuses; +- nvidia,xcvr-lsfslew = <2>; +- nvidia,xcvr-lsrslew = <2>; +- nvidia,xcvr-hsslew = <32>; +- nvidia,hssquelch-level = <2>; +- nvidia,hsdiscon-level = <5>; +- status = "disabled"; +- }; +- +- usb@7d008000 { +- compatible = "nvidia,tegra30-ehci", "usb-ehci"; +- reg = <0x7d008000 0x4000>; +- interrupts = ; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA30_CLK_USB3>; +- resets = <&tegra_car 59>; +- reset-names = "usb"; +- nvidia,phy = <&phy3>; +- status = "disabled"; +- }; +- +- phy3: usb-phy@7d008000 { +- compatible = "nvidia,tegra30-usb-phy"; +- reg = <0x7d008000 0x4000>, +- <0x7d000000 0x4000>; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA30_CLK_USB3>, +- <&tegra_car TEGRA30_CLK_PLL_U>, +- <&tegra_car TEGRA30_CLK_USBD>; +- clock-names = "reg", "pll_u", "utmi-pads"; +- resets = <&tegra_car 59>, <&tegra_car 22>; +- reset-names = "usb", "utmi-pads"; +- #phy-cells = <0>; +- nvidia,hssync-start-delay = <0>; +- nvidia,idle-wait-delay = <17>; +- nvidia,elastic-limit = <16>; +- nvidia,term-range-adj = <6>; +- nvidia,xcvr-setup = <51>; +- nvidia,xcvr-setup-use-fuses; +- nvidia,xcvr-lsfslew = <2>; +- nvidia,xcvr-lsrslew = <2>; +- nvidia,xcvr-hsslew = <32>; +- nvidia,hssquelch-level = <2>; +- nvidia,hsdiscon-level = <5>; +- status = "disabled"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <1>; +- clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <2>; +- clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <3>; +- clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; +- #cooling-cells = <2>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&{/cpus/cpu@0}>, +- <&{/cpus/cpu@1}>, +- <&{/cpus/cpu@2}>, +- <&{/cpus/cpu@3}>; +- }; +- +- thermal-zones { +- tsensor0-thermal { +- polling-delay-passive = <1000>; /* milliseconds */ +- polling-delay = <5000>; /* milliseconds */ +- +- thermal-sensors = <&tsensor 0>; +- +- trips { +- level1_trip: dvfs-alert { +- /* throttle at 80C until temperature drops to 79.8C */ +- temperature = <80000>; +- hysteresis = <200>; +- type = "passive"; +- }; +- +- level2_trip: cpu-div2-throttle { +- /* hardware CPU x2 freq throttle at 85C */ +- temperature = <85000>; +- hysteresis = <200>; +- type = "hot"; +- }; +- +- level3_trip: soc-critical { +- /* hardware shut down at 90C */ +- temperature = <90000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&level1_trip>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&actmon THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- tsensor1-thermal { +- status = "disabled"; +- +- polling-delay-passive = <1000>; /* milliseconds */ +- polling-delay = <0>; /* milliseconds */ +- +- thermal-sensors = <&tsensor 1>; +- +- trips { +- dvfs-alert { +- temperature = <80000>; +- hysteresis = <200>; +- type = "passive"; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tny_a9260.dts b/scripts/dtc/include-prefixes/arm/tny_a9260.dts +deleted file mode 100644 +index ef6d586ce887..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tny_a9260.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * tny_a9260.dts - Device Tree file for Caloa TNY A9260 board +- * +- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +-/dts-v1/; +-#include "at91sam9260.dtsi" +-#include "tny_a9260_common.dtsi" +- +-/ { +- model = "Calao TNY A9260"; +- compatible = "calao,tny-a9260", "atmel,at91sam9260", "atmel,at91sam9"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tny_a9260_common.dtsi b/scripts/dtc/include-prefixes/arm/tny_a9260_common.dtsi +deleted file mode 100644 +index 70e5635c78ed..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tny_a9260_common.dtsi ++++ /dev/null +@@ -1,112 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * tny_a9260_common.dtsi - Device Tree file for Caloa TNY A926x board +- * +- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +- +-/ { +- chosen { +- bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock6 rw rootfstype=ubifs"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- ahb { +- apb { +- tcb0: timer@fffa0000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +- }; +- +- dbgu: serial@fffff200 { +- status = "okay"; +- }; +- }; +- +- ebi: ebi@10000000 { +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; +- pinctrl-names = "default"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "soft"; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x20000>; +- }; +- +- barebox@20000 { +- label = "barebox"; +- reg = <0x20000 0x40000>; +- }; +- +- bareboxenv@60000 { +- label = "bareboxenv"; +- reg = <0x60000 0x20000>; +- }; +- +- bareboxenv2@80000 { +- label = "bareboxenv2"; +- reg = <0x80000 0x20000>; +- }; +- +- oftree@80000 { +- label = "oftree"; +- reg = <0xa0000 0x20000>; +- }; +- +- kernel@a0000 { +- label = "kernel"; +- reg = <0xc0000 0x400000>; +- }; +- +- rootfs@4a0000 { +- label = "rootfs"; +- reg = <0x4c0000 0x7800000>; +- }; +- +- data@7ca0000 { +- label = "data"; +- reg = <0x7cc0000 0x8340000>; +- }; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tny_a9263.dts b/scripts/dtc/include-prefixes/arm/tny_a9263.dts +deleted file mode 100644 +index 62b7d9f9a926..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tny_a9263.dts ++++ /dev/null +@@ -1,126 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * usb_a9263.dts - Device Tree file for Caloa USB A9293 board +- * +- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +-/dts-v1/; +-#include "at91sam9263.dtsi" +- +-/ { +- model = "Calao TNY A9263"; +- compatible = "atmel,tny-a9263", "atmel,at91sam9263", "atmel,at91sam9"; +- +- chosen { +- bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- ahb { +- apb { +- dbgu: serial@ffffee00 { +- status = "okay"; +- }; +- +- tcb0: timer@fff7c000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +- }; +- +- usb1: gadget@fff78000 { +- atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- }; +- +- ebi0: ebi@10000000 { +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; +- pinctrl-names = "default"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "soft"; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x20000>; +- }; +- +- barebox@20000 { +- label = "barebox"; +- reg = <0x20000 0x40000>; +- }; +- +- bareboxenv@60000 { +- label = "bareboxenv"; +- reg = <0x60000 0x20000>; +- }; +- +- bareboxenv2@80000 { +- label = "bareboxenv2"; +- reg = <0x80000 0x20000>; +- }; +- +- oftree@80000 { +- label = "oftree"; +- reg = <0xa0000 0x20000>; +- }; +- +- kernel@a0000 { +- label = "kernel"; +- reg = <0xc0000 0x400000>; +- }; +- +- rootfs@4a0000 { +- label = "rootfs"; +- reg = <0x4c0000 0x7800000>; +- }; +- +- data@7ca0000 { +- label = "data"; +- reg = <0x7cc0000 0x8340000>; +- }; +- }; +- }; +- }; +- }; +- }; +- +- i2c-gpio-0 { +- status = "okay"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tny_a9g20.dts b/scripts/dtc/include-prefixes/arm/tny_a9g20.dts +deleted file mode 100644 +index 118d766a1265..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tny_a9g20.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * tny_a9g20.dts - Device Tree file for Caloa TNY A9G20 board +- * +- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +-/dts-v1/; +-#include "at91sam9g20.dtsi" +-#include "tny_a9260_common.dtsi" +- +-/ { +- model = "Calao TNY A9G20"; +- compatible = "calao,tny-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tps6507x.dtsi b/scripts/dtc/include-prefixes/arm/tps6507x.dtsi +deleted file mode 100644 +index db4809d308f9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tps6507x.dtsi ++++ /dev/null +@@ -1,44 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ +- */ +- +-/* +- * Integrated Power Management Chip +- * http://www.ti.com/lit/ds/symlink/tps65070.pdf +- */ +- +-&tps { +- compatible = "ti,tps6507x"; +- +- regulators { +- #address-cells = <1>; +- #size-cells = <0>; +- +- vdcdc1_reg: regulator@0 { +- reg = <0>; +- regulator-compatible = "VDCDC1"; +- }; +- +- vdcdc2_reg: regulator@1 { +- reg = <1>; +- regulator-compatible = "VDCDC2"; +- }; +- +- vdcdc3_reg: regulator@2 { +- reg = <2>; +- regulator-compatible = "VDCDC3"; +- }; +- +- ldo1_reg: regulator@3 { +- reg = <3>; +- regulator-compatible = "LDO1"; +- }; +- +- ldo2_reg: regulator@4 { +- reg = <4>; +- regulator-compatible = "LDO2"; +- }; +- +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tps65217.dtsi b/scripts/dtc/include-prefixes/arm/tps65217.dtsi +deleted file mode 100644 +index 0d463de5650f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tps65217.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ +- */ +- +-/* +- * Integrated Power Management Chip +- * http://www.ti.com/lit/ds/symlink/tps65217.pdf +- */ +- +-&tps { +- compatible = "ti,tps65217"; +- interrupt-controller; +- #interrupt-cells = <1>; +- +- charger { +- compatible = "ti,tps65217-charger"; +- interrupts = <0>, <1>; +- interrupt-names = "USB", "AC"; +- status = "disabled"; +- }; +- +- pwrbutton { +- compatible = "ti,tps65217-pwrbutton"; +- interrupts = <2>; +- status = "disabled"; +- }; +- +- regulators { +- #address-cells = <1>; +- #size-cells = <0>; +- +- dcdc1_reg: regulator@0 { +- reg = <0>; +- regulator-compatible = "dcdc1"; +- }; +- +- dcdc2_reg: regulator@1 { +- reg = <1>; +- regulator-compatible = "dcdc2"; +- }; +- +- dcdc3_reg: regulator@2 { +- reg = <2>; +- regulator-compatible = "dcdc3"; +- }; +- +- ldo1_reg: regulator@3 { +- reg = <3>; +- regulator-compatible = "ldo1"; +- }; +- +- ldo2_reg: regulator@4 { +- reg = <4>; +- regulator-compatible = "ldo2"; +- }; +- +- ldo3_reg: regulator@5 { +- reg = <5>; +- regulator-compatible = "ldo3"; +- }; +- +- ldo4_reg: regulator@6 { +- reg = <6>; +- regulator-compatible = "ldo4"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/tps65910.dtsi b/scripts/dtc/include-prefixes/arm/tps65910.dtsi +deleted file mode 100644 +index a941d1e62328..000000000000 +--- a/scripts/dtc/include-prefixes/arm/tps65910.dtsi ++++ /dev/null +@@ -1,88 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ +- */ +- +-/* +- * Integrated Power Management Chip +- * http://www.ti.com/lit/ds/symlink/tps65910.pdf +- */ +- +-&tps { +- compatible = "ti,tps65910"; +- +- regulators { +- #address-cells = <1>; +- #size-cells = <0>; +- +- vrtc_reg: regulator@0 { +- reg = <0>; +- regulator-compatible = "vrtc"; +- }; +- +- vio_reg: regulator@1 { +- reg = <1>; +- regulator-compatible = "vio"; +- }; +- +- vdd1_reg: regulator@2 { +- reg = <2>; +- regulator-compatible = "vdd1"; +- }; +- +- vdd2_reg: regulator@3 { +- reg = <3>; +- regulator-compatible = "vdd2"; +- }; +- +- vdd3_reg: regulator@4 { +- reg = <4>; +- regulator-compatible = "vdd3"; +- }; +- +- vdig1_reg: regulator@5 { +- reg = <5>; +- regulator-compatible = "vdig1"; +- }; +- +- vdig2_reg: regulator@6 { +- reg = <6>; +- regulator-compatible = "vdig2"; +- }; +- +- vpll_reg: regulator@7 { +- reg = <7>; +- regulator-compatible = "vpll"; +- }; +- +- vdac_reg: regulator@8 { +- reg = <8>; +- regulator-compatible = "vdac"; +- }; +- +- vaux1_reg: regulator@9 { +- reg = <9>; +- regulator-compatible = "vaux1"; +- }; +- +- vaux2_reg: regulator@10 { +- reg = <10>; +- regulator-compatible = "vaux2"; +- }; +- +- vaux33_reg: regulator@11 { +- reg = <11>; +- regulator-compatible = "vaux33"; +- }; +- +- vmmc_reg: regulator@12 { +- reg = <12>; +- regulator-compatible = "vmmc"; +- }; +- +- vbb_reg: regulator@13 { +- reg = <13>; +- regulator-compatible = "vbb"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/twl4030.dtsi b/scripts/dtc/include-prefixes/arm/twl4030.dtsi +deleted file mode 100644 +index 93e07c18781b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/twl4030.dtsi ++++ /dev/null +@@ -1,160 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +- */ +- +-/* +- * Integrated Power Management Chip +- */ +-&twl { +- compatible = "ti,twl4030"; +- interrupt-controller; +- #interrupt-cells = <1>; +- +- rtc { +- compatible = "ti,twl4030-rtc"; +- interrupts = <11>; +- }; +- +- charger: bci { +- compatible = "ti,twl4030-bci"; +- interrupts = <9>, <2>; +- bci3v1-supply = <&vusb3v1>; +- io-channels = <&twl_madc 11>; +- io-channel-names = "vac"; +- }; +- +- watchdog { +- compatible = "ti,twl4030-wdt"; +- }; +- +- vaux1: regulator-vaux1 { +- compatible = "ti,twl4030-vaux1"; +- }; +- +- vaux2: regulator-vaux2 { +- compatible = "ti,twl4030-vaux2"; +- }; +- +- vaux3: regulator-vaux3 { +- compatible = "ti,twl4030-vaux3"; +- }; +- +- vaux4: regulator-vaux4 { +- compatible = "ti,twl4030-vaux4"; +- }; +- +- vcc: regulator-vdd1 { +- compatible = "ti,twl4030-vdd1"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1450000>; +- }; +- +- vdac: regulator-vdac { +- compatible = "ti,twl4030-vdac"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vio: regulator-vio { +- compatible = "ti,twl4030-vio"; +- }; +- +- vintana1: regulator-vintana1 { +- compatible = "ti,twl4030-vintana1"; +- }; +- +- vintana2: regulator-vintana2 { +- compatible = "ti,twl4030-vintana2"; +- }; +- +- vintdig: regulator-vintdig { +- compatible = "ti,twl4030-vintdig"; +- }; +- +- vmmc1: regulator-vmmc1 { +- compatible = "ti,twl4030-vmmc1"; +- regulator-min-microvolt = <1850000>; +- regulator-max-microvolt = <3150000>; +- }; +- +- vmmc2: regulator-vmmc2 { +- compatible = "ti,twl4030-vmmc2"; +- regulator-min-microvolt = <1850000>; +- regulator-max-microvolt = <3150000>; +- }; +- +- vusb1v5: regulator-vusb1v5 { +- compatible = "ti,twl4030-vusb1v5"; +- }; +- +- vusb1v8: regulator-vusb1v8 { +- compatible = "ti,twl4030-vusb1v8"; +- }; +- +- vusb3v1: regulator-vusb3v1 { +- compatible = "ti,twl4030-vusb3v1"; +- }; +- +- vpll1: regulator-vpll1 { +- compatible = "ti,twl4030-vpll1"; +- }; +- +- vpll2: regulator-vpll2 { +- compatible = "ti,twl4030-vpll2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vsim: regulator-vsim { +- compatible = "ti,twl4030-vsim"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- twl_gpio: gpio { +- compatible = "ti,twl4030-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- usb2_phy: twl4030-usb { +- compatible = "ti,twl4030-usb"; +- interrupts = <10>, <4>; +- usb1v5-supply = <&vusb1v5>; +- usb1v8-supply = <&vusb1v8>; +- usb3v1-supply = <&vusb3v1>; +- usb_mode = <1>; +- #phy-cells = <0>; +- }; +- +- twl_pwm: pwm { +- compatible = "ti,twl4030-pwm"; +- #pwm-cells = <2>; +- }; +- +- twl_pwmled: pwmled { +- compatible = "ti,twl4030-pwmled"; +- #pwm-cells = <2>; +- }; +- +- twl_pwrbutton: pwrbutton { +- compatible = "ti,twl4030-pwrbutton"; +- interrupts = <8>; +- }; +- +- twl_keypad: keypad { +- compatible = "ti,twl4030-keypad"; +- interrupts = <1>; +- keypad,num-rows = <8>; +- keypad,num-columns = <8>; +- }; +- +- twl_madc: madc { +- compatible = "ti,twl4030-madc"; +- interrupts = <3>; +- #io-channel-cells = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/twl4030_omap3.dtsi b/scripts/dtc/include-prefixes/arm/twl4030_omap3.dtsi +deleted file mode 100644 +index 683419d5c0e5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/twl4030_omap3.dtsi ++++ /dev/null +@@ -1,39 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013 Linaro, Ltd. +- */ +- +-&twl { +- pinctrl-names = "default"; +- pinctrl-0 = <&twl4030_pins &twl4030_vpins>; +-}; +- +-&omap3_pmx_core { +- /* +- * On most OMAP3 platforms, the twl4030 IRQ line is connected +- * to the SYS_NIRQ line on OMAP. Therefore, configure the +- * defaults for the SYS_NIRQ pin here. +- */ +- twl4030_pins: pinmux_twl4030_pins { +- pinctrl-single,pins = < +- OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */ +- >; +- }; +-}; +- +-/* +- * If your board is not using the I2C4 pins with twl4030, then don't include +- * this file. For proper idle mode signaling with sys_clkreq and sys_off_mode +- * pins we need to configure I2C4, or else use the legacy sys_nvmode1 and +- * sys_nvmode2 signaling. +- */ +-&omap3_pmx_wkup { +- twl4030_vpins: pinmux_twl4030_vpins { +- pinctrl-single,pins = < +- OMAP3_WKUP_IOPAD(0x2a00, PIN_INPUT | MUX_MODE0) /* i2c4_scl.i2c4_scl */ +- OMAP3_WKUP_IOPAD(0x2a02, PIN_INPUT | MUX_MODE0) /* i2c4_sda.i2c4_sda */ +- OMAP3_WKUP_IOPAD(0x2a06, PIN_OUTPUT | MUX_MODE0) /* sys_clkreq.sys_clkreq */ +- OMAP3_WKUP_IOPAD(0x2a18, PIN_OUTPUT | MUX_MODE0) /* sys_off_mode.sys_off_mode */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/twl6030.dtsi b/scripts/dtc/include-prefixes/arm/twl6030.dtsi +deleted file mode 100644 +index 9d588cfaa5cb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/twl6030.dtsi ++++ /dev/null +@@ -1,105 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +- */ +- +-/* +- * Integrated Power Management Chip +- * http://www.ti.com/lit/ds/symlink/twl6030.pdf +- */ +-&twl { +- compatible = "ti,twl6030"; +- interrupt-controller; +- #interrupt-cells = <1>; +- +- rtc { +- compatible = "ti,twl4030-rtc"; +- interrupts = <11>; +- }; +- +- vaux1: regulator-vaux1 { +- compatible = "ti,twl6030-vaux1"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- vaux2: regulator-vaux2 { +- compatible = "ti,twl6030-vaux2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- vaux3: regulator-vaux3 { +- compatible = "ti,twl6030-vaux3"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- vmmc: regulator-vmmc { +- compatible = "ti,twl6030-vmmc"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- vpp: regulator-vpp { +- compatible = "ti,twl6030-vpp"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2500000>; +- }; +- +- vusim: regulator-vusim { +- compatible = "ti,twl6030-vusim"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <2900000>; +- }; +- +- vdac: regulator-vdac { +- compatible = "ti,twl6030-vdac"; +- }; +- +- vana: regulator-vana { +- compatible = "ti,twl6030-vana"; +- }; +- +- vcxio: regulator-vcxio { +- compatible = "ti,twl6030-vcxio"; +- regulator-always-on; +- }; +- +- vusb: regulator-vusb { +- compatible = "ti,twl6030-vusb"; +- }; +- +- v1v8: regulator-v1v8 { +- compatible = "ti,twl6030-v1v8"; +- regulator-always-on; +- }; +- +- v2v1: regulator-v2v1 { +- compatible = "ti,twl6030-v2v1"; +- regulator-always-on; +- }; +- +- twl_usb_comparator: usb-comparator { +- compatible = "ti,twl6030-usb"; +- interrupts = <4>, <10>; +- }; +- +- twl_pwm: pwm { +- /* provides two PWMs (id 0, 1 for PWM1 and PWM2) */ +- compatible = "ti,twl6030-pwm"; +- #pwm-cells = <2>; +- }; +- +- twl_pwmled: pwmled { +- /* provides one PWM (id 0 for Charging indicator LED) */ +- compatible = "ti,twl6030-pwmled"; +- #pwm-cells = <2>; +- }; +- +- gpadc { +- compatible = "ti,twl6030-gpadc"; +- interrupts = <3>; +- #io-channel-cells = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/twl6030_omap4.dtsi b/scripts/dtc/include-prefixes/arm/twl6030_omap4.dtsi +deleted file mode 100644 +index 5730e46b0067..000000000000 +--- a/scripts/dtc/include-prefixes/arm/twl6030_omap4.dtsi ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-&twl { +- /* +- * On most OMAP4 platforms, the twl6030 IRQ line is connected +- * to the SYS_NIRQ1 line on OMAP and the twl6030 MSECURE line is +- * connected to the fref_clk0_out.sys_drm_msecure line. +- * Therefore, configure the defaults for the SYS_NIRQ1 and +- * fref_clk0_out.sys_drm_msecure pins here. +- */ +- pinctrl-names = "default"; +- pinctrl-0 = < +- &twl6030_pins +- &twl6030_wkup_pins +- >; +-}; +- +-&omap4_pmx_wkup { +- twl6030_wkup_pins: pinmux_twl6030_wkup_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x054, PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */ +- >; +- }; +-}; +- +-&omap4_pmx_core { +- twl6030_pins: pinmux_twl6030_pins { +- pinctrl-single,pins = < +- OMAP4_IOPAD(0x19e, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/uniphier-ld4-ref.dts b/scripts/dtc/include-prefixes/arm/uniphier-ld4-ref.dts +deleted file mode 100644 +index c46c2e8a10a7..000000000000 +--- a/scripts/dtc/include-prefixes/arm/uniphier-ld4-ref.dts ++++ /dev/null +@@ -1,88 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier LD4 Reference Board +-// +-// Copyright (C) 2015-2016 Socionext Inc. +-// Author: Masahiro Yamada +- +-/dts-v1/; +-#include "uniphier-ld4.dtsi" +-#include "uniphier-ref-daughter.dtsi" +-#include "uniphier-support-card.dtsi" +- +-/ { +- model = "UniPhier LD4 Reference Board"; +- compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serialsc; +- serial2 = &serial2; +- serial3 = &serial3; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +-}; +- +-ðsc { +- interrupts = <1 8>; +-}; +- +-&serialsc { +- interrupts = <1 8>; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&serial2 { +- status = "okay"; +-}; +- +-&serial3 { +- status = "okay"; +-}; +- +-&gpio { +- xirq1 { +- gpio-hog; +- gpios = ; +- input; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&sd { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&nand { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/uniphier-ld4.dtsi b/scripts/dtc/include-prefixes/arm/uniphier-ld4.dtsi +deleted file mode 100644 +index b52957ccda0d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/uniphier-ld4.dtsi ++++ /dev/null +@@ -1,421 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier LD4 SoC +-// +-// Copyright (C) 2015-2016 Socionext Inc. +-// Author: Masahiro Yamada +- +-#include +- +-/ { +- compatible = "socionext,uniphier-ld4"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- clocks { +- refclk: ref { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +- +- arm_timer_clk: arm-timer { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- interrupt-parent = <&intc>; +- +- l2: cache-controller@500c0000 { +- compatible = "socionext,uniphier-system-cache"; +- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, +- <0x506c0000 0x400>; +- interrupts = <0 174 4>, <0 175 4>; +- cache-unified; +- cache-size = <(512 * 1024)>; +- cache-sets = <256>; +- cache-line-size = <128>; +- cache-level = <2>; +- }; +- +- spi: spi@54006000 { +- compatible = "socionext,uniphier-scssi"; +- status = "disabled"; +- reg = <0x54006000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 39 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0>; +- clocks = <&peri_clk 11>; +- resets = <&peri_rst 11>; +- }; +- +- serial0: serial@54006800 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006800 0x40>; +- interrupts = <0 33 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- clocks = <&peri_clk 0>; +- resets = <&peri_rst 0>; +- }; +- +- serial1: serial@54006900 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006900 0x40>; +- interrupts = <0 35 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- clocks = <&peri_clk 1>; +- resets = <&peri_rst 1>; +- }; +- +- serial2: serial@54006a00 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006a00 0x40>; +- interrupts = <0 37 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- clocks = <&peri_clk 2>; +- resets = <&peri_rst 2>; +- }; +- +- serial3: serial@54006b00 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006b00 0x40>; +- interrupts = <0 29 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- clocks = <&peri_clk 3>; +- resets = <&peri_rst 3>; +- }; +- +- gpio: gpio@55000000 { +- compatible = "socionext,uniphier-gpio"; +- reg = <0x55000000 0x200>; +- interrupt-parent = <&aidet>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 0 0>; +- gpio-ranges-group-names = "gpio_range"; +- ngpios = <136>; +- socionext,interrupt-ranges = <0 48 13>, <14 62 2>; +- }; +- +- i2c0: i2c@58400000 { +- compatible = "socionext,uniphier-i2c"; +- status = "disabled"; +- reg = <0x58400000 0x40>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 41 1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0>; +- clocks = <&peri_clk 4>; +- resets = <&peri_rst 4>; +- clock-frequency = <100000>; +- }; +- +- i2c1: i2c@58480000 { +- compatible = "socionext,uniphier-i2c"; +- status = "disabled"; +- reg = <0x58480000 0x40>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 42 1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clocks = <&peri_clk 5>; +- resets = <&peri_rst 5>; +- clock-frequency = <100000>; +- }; +- +- /* chip-internal connection for DMD */ +- i2c2: i2c@58500000 { +- compatible = "socionext,uniphier-i2c"; +- reg = <0x58500000 0x40>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 43 1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clocks = <&peri_clk 6>; +- resets = <&peri_rst 6>; +- clock-frequency = <400000>; +- }; +- +- i2c3: i2c@58580000 { +- compatible = "socionext,uniphier-i2c"; +- status = "disabled"; +- reg = <0x58580000 0x40>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 44 1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- clocks = <&peri_clk 7>; +- resets = <&peri_rst 7>; +- clock-frequency = <100000>; +- }; +- +- system_bus: system-bus@58c00000 { +- compatible = "socionext,uniphier-system-bus"; +- status = "disabled"; +- reg = <0x58c00000 0x400>; +- #address-cells = <2>; +- #size-cells = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_system_bus>; +- }; +- +- smpctrl@59801000 { +- compatible = "socionext,uniphier-smpctrl"; +- reg = <0x59801000 0x400>; +- }; +- +- mioctrl@59810000 { +- compatible = "socionext,uniphier-ld4-mioctrl", +- "simple-mfd", "syscon"; +- reg = <0x59810000 0x800>; +- +- mio_clk: clock { +- compatible = "socionext,uniphier-ld4-mio-clock"; +- #clock-cells = <1>; +- }; +- +- mio_rst: reset { +- compatible = "socionext,uniphier-ld4-mio-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- perictrl@59820000 { +- compatible = "socionext,uniphier-ld4-perictrl", +- "simple-mfd", "syscon"; +- reg = <0x59820000 0x200>; +- +- peri_clk: clock { +- compatible = "socionext,uniphier-ld4-peri-clock"; +- #clock-cells = <1>; +- }; +- +- peri_rst: reset { +- compatible = "socionext,uniphier-ld4-peri-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- dmac: dma-controller@5a000000 { +- compatible = "socionext,uniphier-mio-dmac"; +- reg = <0x5a000000 0x1000>; +- interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, +- <0 71 4>, <0 72 4>, <0 73 4>; +- clocks = <&mio_clk 7>; +- resets = <&mio_rst 7>; +- #dma-cells = <1>; +- }; +- +- sd: mmc@5a400000 { +- compatible = "socionext,uniphier-sd-v2.91"; +- status = "disabled"; +- reg = <0x5a400000 0x200>; +- interrupts = <0 76 4>; +- pinctrl-names = "default", "uhs"; +- pinctrl-0 = <&pinctrl_sd>; +- pinctrl-1 = <&pinctrl_sd_uhs>; +- clocks = <&mio_clk 0>; +- reset-names = "host", "bridge"; +- resets = <&mio_rst 0>, <&mio_rst 3>; +- dma-names = "rx-tx"; +- dmas = <&dmac 4>; +- bus-width = <4>; +- cap-sd-highspeed; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- }; +- +- emmc: mmc@5a500000 { +- compatible = "socionext,uniphier-sd-v2.91"; +- status = "disabled"; +- reg = <0x5a500000 0x200>; +- interrupts = <0 78 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_emmc>; +- clocks = <&mio_clk 1>; +- reset-names = "host", "bridge", "hw"; +- resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; +- dma-names = "rx-tx"; +- dmas = <&dmac 6>; +- bus-width = <8>; +- cap-mmc-highspeed; +- cap-mmc-hw-reset; +- non-removable; +- }; +- +- usb0: usb@5a800100 { +- compatible = "socionext,uniphier-ehci", "generic-ehci"; +- status = "disabled"; +- reg = <0x5a800100 0x100>; +- interrupts = <0 80 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb0>; +- clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, +- <&mio_clk 12>; +- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, +- <&mio_rst 12>; +- has-transaction-translator; +- }; +- +- usb1: usb@5a810100 { +- compatible = "socionext,uniphier-ehci", "generic-ehci"; +- status = "disabled"; +- reg = <0x5a810100 0x100>; +- interrupts = <0 81 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb1>; +- clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, +- <&mio_clk 13>; +- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, +- <&mio_rst 13>; +- has-transaction-translator; +- }; +- +- usb2: usb@5a820100 { +- compatible = "socionext,uniphier-ehci", "generic-ehci"; +- status = "disabled"; +- reg = <0x5a820100 0x100>; +- interrupts = <0 82 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb2>; +- clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, +- <&mio_clk 14>; +- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, +- <&mio_rst 14>; +- has-transaction-translator; +- }; +- +- soc-glue@5f800000 { +- compatible = "socionext,uniphier-ld4-soc-glue", +- "simple-mfd", "syscon"; +- reg = <0x5f800000 0x2000>; +- +- pinctrl: pinctrl { +- compatible = "socionext,uniphier-ld4-pinctrl"; +- }; +- }; +- +- soc-glue@5f900000 { +- compatible = "socionext,uniphier-ld4-soc-glue-debug", +- "simple-mfd"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x5f900000 0x2000>; +- +- efuse@100 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x100 0x28>; +- }; +- +- efuse@130 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x130 0x8>; +- }; +- }; +- +- timer@60000200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0x60000200 0x20>; +- interrupts = <1 11 0x104>; +- clocks = <&arm_timer_clk>; +- }; +- +- timer@60000600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x60000600 0x20>; +- interrupts = <1 13 0x104>; +- clocks = <&arm_timer_clk>; +- }; +- +- intc: interrupt-controller@60001000 { +- compatible = "arm,cortex-a9-gic"; +- reg = <0x60001000 0x1000>, +- <0x60000100 0x100>; +- #interrupt-cells = <3>; +- interrupt-controller; +- }; +- +- aidet: interrupt-controller@61830000 { +- compatible = "socionext,uniphier-ld4-aidet"; +- reg = <0x61830000 0x200>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- sysctrl@61840000 { +- compatible = "socionext,uniphier-ld4-sysctrl", +- "simple-mfd", "syscon"; +- reg = <0x61840000 0x10000>; +- +- sys_clk: clock { +- compatible = "socionext,uniphier-ld4-clock"; +- #clock-cells = <1>; +- }; +- +- sys_rst: reset { +- compatible = "socionext,uniphier-ld4-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- nand: nand-controller@68000000 { +- compatible = "socionext,uniphier-denali-nand-v5a"; +- status = "disabled"; +- reg-names = "nand_data", "denali_reg"; +- reg = <0x68000000 0x20>, <0x68100000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 65 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nand>; +- clock-names = "nand", "nand_x", "ecc"; +- clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; +- reset-names = "nand", "reg"; +- resets = <&sys_rst 2>, <&sys_rst 2>; +- }; +- }; +-}; +- +-#include "uniphier-pinctrl.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/uniphier-ld6b-ref.dts b/scripts/dtc/include-prefixes/arm/uniphier-ld6b-ref.dts +deleted file mode 100644 +index 5bc7fe11b517..000000000000 +--- a/scripts/dtc/include-prefixes/arm/uniphier-ld6b-ref.dts ++++ /dev/null +@@ -1,103 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier LD6b Reference Board +-// +-// Copyright (C) 2015-2016 Socionext Inc. +-// Author: Masahiro Yamada +- +-/dts-v1/; +-#include "uniphier-ld6b.dtsi" +-#include "uniphier-ref-daughter.dtsi" +-#include "uniphier-support-card.dtsi" +- +-/ { +- model = "UniPhier LD6b Reference Board"; +- compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serialsc; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- ethernet0 = ð +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x80000000>; +- }; +-}; +- +-ðsc { +- interrupts = <4 8>; +-}; +- +-&serialsc { +- interrupts = <4 8>; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&serial1 { +- status = "okay"; +-}; +- +-&serial2 { +- status = "okay"; +-}; +- +-&gpio { +- xirq4 { +- gpio-hog; +- gpios = ; +- input; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&sd { +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- phy-handle = <ðphy>; +-}; +- +-&mdio { +- ethphy: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&nand { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/uniphier-ld6b.dtsi b/scripts/dtc/include-prefixes/arm/uniphier-ld6b.dtsi +deleted file mode 100644 +index 4d07a94c6b34..000000000000 +--- a/scripts/dtc/include-prefixes/arm/uniphier-ld6b.dtsi ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier LD6b SoC +-// +-// Copyright (C) 2015-2016 Socionext Inc. +-// Author: Masahiro Yamada +- +-/* +- * LD6b consists of two silicon dies: D-chip and A-chip. +- * The D-chip (digital chip) is the same as the PXs2 die. +- * Reuse the PXs2 device tree with some properties overridden. +- */ +-#include "uniphier-pxs2.dtsi" +- +-/ { +- compatible = "socionext,uniphier-ld6b"; +-}; +- +-/* UART3 unavailable: the pads are not wired to the package balls */ +-&serial3 { +- status = "disabled"; +-}; +- +-/* +- * LD6b and PXs2 have completely different packages, +- * which makes the pinctrl driver unshareable. +- */ +-&pinctrl { +- compatible = "socionext,uniphier-ld6b-pinctrl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/uniphier-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm/uniphier-pinctrl.dtsi +deleted file mode 100644 +index c0fd029b37e5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/uniphier-pinctrl.dtsi ++++ /dev/null +@@ -1,213 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier SoCs default pinctrl settings +-// +-// Copyright (C) 2015-2017 Socionext Inc. +-// Author: Masahiro Yamada +- +-&pinctrl { +- pinctrl_aout: aout { +- groups = "aout"; +- function = "aout"; +- }; +- +- pinctrl_ain1: ain1 { +- groups = "ain1"; +- function = "ain1"; +- }; +- +- pinctrl_ain2: ain2 { +- groups = "ain2"; +- function = "ain2"; +- }; +- +- pinctrl_ainiec1: ainiec1 { +- groups = "ainiec1"; +- function = "ainiec1"; +- }; +- +- pinctrl_aout1: aout1 { +- groups = "aout1"; +- function = "aout1"; +- }; +- +- pinctrl_aout2: aout2 { +- groups = "aout2"; +- function = "aout2"; +- }; +- +- pinctrl_aout3: aout3 { +- groups = "aout3"; +- function = "aout3"; +- }; +- +- pinctrl_aoutiec1: aoutiec1 { +- groups = "aoutiec1"; +- function = "aoutiec1"; +- }; +- +- pinctrl_aoutiec2: aoutiec2 { +- groups = "aoutiec2"; +- function = "aoutiec2"; +- }; +- +- pinctrl_emmc: emmc { +- groups = "emmc", "emmc_dat8"; +- function = "emmc"; +- }; +- +- pinctrl_ether_mii: ether-mii { +- groups = "ether_mii"; +- function = "ether_mii"; +- }; +- +- pinctrl_ether_rgmii: ether-rgmii { +- groups = "ether_rgmii"; +- function = "ether_rgmii"; +- }; +- +- pinctrl_ether_rmii: ether-rmii { +- groups = "ether_rmii"; +- function = "ether_rmii"; +- }; +- +- pinctrl_ether1_rgmii: ether1-rgmii { +- groups = "ether1_rgmii"; +- function = "ether1_rgmii"; +- }; +- +- pinctrl_ether1_rmii: ether1-rmii { +- groups = "ether1_rmii"; +- function = "ether1_rmii"; +- }; +- +- pinctrl_i2c0: i2c0 { +- groups = "i2c0"; +- function = "i2c0"; +- }; +- +- pinctrl_i2c1: i2c1 { +- groups = "i2c1"; +- function = "i2c1"; +- }; +- +- pinctrl_i2c2: i2c2 { +- groups = "i2c2"; +- function = "i2c2"; +- }; +- +- pinctrl_i2c3: i2c3 { +- groups = "i2c3"; +- function = "i2c3"; +- }; +- +- pinctrl_i2c4: i2c4 { +- groups = "i2c4"; +- function = "i2c4"; +- }; +- +- pinctrl_i2c5: i2c5 { +- groups = "i2c5"; +- function = "i2c5"; +- }; +- +- pinctrl_i2c6: i2c6 { +- groups = "i2c6"; +- function = "i2c6"; +- }; +- +- pinctrl_nand: nand { +- groups = "nand"; +- function = "nand"; +- }; +- +- pinctrl_nand2cs: nand2cs { +- groups = "nand", "nand_cs1"; +- function = "nand"; +- }; +- +- pinctrl_pcie: pcie { +- groups = "pcie"; +- function = "pcie"; +- }; +- +- pinctrl_sd: sd { +- groups = "sd"; +- function = "sd"; +- }; +- +- pinctrl_sd_uhs: sd-uhs { +- groups = "sd"; +- function = "sd"; +- }; +- +- pinctrl_sd1: sd1 { +- groups = "sd1"; +- function = "sd1"; +- }; +- +- pinctrl_spi0: spi0 { +- groups = "spi0"; +- function = "spi0"; +- }; +- +- pinctrl_spi1: spi1 { +- groups = "spi1"; +- function = "spi1"; +- }; +- +- pinctrl_spi2: spi2 { +- groups = "spi2"; +- function = "spi2"; +- }; +- +- pinctrl_spi3: spi3 { +- groups = "spi3"; +- function = "spi3"; +- }; +- +- pinctrl_system_bus: system-bus { +- groups = "system_bus", "system_bus_cs1"; +- function = "system_bus"; +- }; +- +- pinctrl_uart0: uart0 { +- groups = "uart0"; +- function = "uart0"; +- }; +- +- pinctrl_uart1: uart1 { +- groups = "uart1"; +- function = "uart1"; +- }; +- +- pinctrl_uart2: uart2 { +- groups = "uart2"; +- function = "uart2"; +- }; +- +- pinctrl_uart3: uart3 { +- groups = "uart3"; +- function = "uart3"; +- }; +- +- pinctrl_usb0: usb0 { +- groups = "usb0"; +- function = "usb0"; +- }; +- +- pinctrl_usb1: usb1 { +- groups = "usb1"; +- function = "usb1"; +- }; +- +- pinctrl_usb2: usb2 { +- groups = "usb2"; +- function = "usb2"; +- }; +- +- pinctrl_usb3: usb3 { +- groups = "usb3"; +- function = "usb3"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/uniphier-pro4-ace.dts b/scripts/dtc/include-prefixes/arm/uniphier-pro4-ace.dts +deleted file mode 100644 +index 27ff2b7b9d0e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/uniphier-pro4-ace.dts ++++ /dev/null +@@ -1,101 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier Pro4 Ace Board +-// +-// Copyright (C) 2016 Socionext Inc. +-// Author: Masahiro Yamada +- +-/dts-v1/; +-#include "uniphier-pro4.dtsi" +- +-/ { +- model = "UniPhier Pro4 Ace Board"; +- compatible = "socionext,uniphier-pro4-ace", "socionext,uniphier-pro4"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- ethernet0 = ð +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; +- }; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&serial1 { +- status = "okay"; +-}; +- +-&serial2 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- eeprom@54 { +- compatible = "st,24c64", "atmel,24c64"; +- reg = <0x54>; +- pagesize = <32>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&sd { +- status = "okay"; +-}; +- +-&usb2 { +- status = "okay"; +-}; +- +-&usb3 { +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- phy-handle = <ðphy>; +-}; +- +-&mdio { +- ethphy: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/uniphier-pro4-ref.dts b/scripts/dtc/include-prefixes/arm/uniphier-pro4-ref.dts +deleted file mode 100644 +index 3b9b61314d01..000000000000 +--- a/scripts/dtc/include-prefixes/arm/uniphier-pro4-ref.dts ++++ /dev/null +@@ -1,110 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier Pro4 Reference Board +-// +-// Copyright (C) 2015-2016 Socionext Inc. +-// Author: Masahiro Yamada +- +-/dts-v1/; +-#include "uniphier-pro4.dtsi" +-#include "uniphier-ref-daughter.dtsi" +-#include "uniphier-support-card.dtsi" +- +-/ { +- model = "UniPhier Pro4 Reference Board"; +- compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serialsc; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- ethernet0 = ð +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; +- }; +-}; +- +-ðsc { +- interrupts = <2 8>; +-}; +- +-&serialsc { +- interrupts = <2 8>; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&serial1 { +- status = "okay"; +-}; +- +-&serial2 { +- status = "okay"; +-}; +- +-&gpio { +- xirq2 { +- gpio-hog; +- gpios = ; +- input; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&sd { +- status = "okay"; +-}; +- +-&usb2 { +- status = "okay"; +-}; +- +-&usb3 { +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- phy-handle = <ðphy>; +-}; +- +-&mdio { +- ethphy: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&nand { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/uniphier-pro4-sanji.dts b/scripts/dtc/include-prefixes/arm/uniphier-pro4-sanji.dts +deleted file mode 100644 +index 7b6faf2e795e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/uniphier-pro4-sanji.dts ++++ /dev/null +@@ -1,96 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier Pro4 Sanji Board +-// +-// Copyright (C) 2016 Socionext Inc. +-// Author: Masahiro Yamada +- +-/dts-v1/; +-#include "uniphier-pro4.dtsi" +- +-/ { +- model = "UniPhier Pro4 Sanji Board"; +- compatible = "socionext,uniphier-pro4-sanji", "socionext,uniphier-pro4"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- ethernet0 = ð +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x80000000>; +- }; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&serial1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- eeprom@54 { +- compatible = "st,24c64", "atmel,24c64"; +- reg = <0x54>; +- pagesize = <32>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&usb2 { +- status = "okay"; +-}; +- +-&usb3 { +- status = "okay"; +-}; +- +-&emmc { +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- phy-handle = <ðphy>; +-}; +- +-&mdio { +- ethphy: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/uniphier-pro4.dtsi b/scripts/dtc/include-prefixes/arm/uniphier-pro4.dtsi +deleted file mode 100644 +index a53b73ee93e9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/uniphier-pro4.dtsi ++++ /dev/null +@@ -1,619 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier Pro4 SoC +-// +-// Copyright (C) 2015-2016 Socionext Inc. +-// Author: Masahiro Yamada +- +-#include +- +-/ { +- compatible = "socionext,uniphier-pro4"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <1>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- clocks { +- refclk: ref { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- arm_timer_clk: arm-timer { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- interrupt-parent = <&intc>; +- +- l2: cache-controller@500c0000 { +- compatible = "socionext,uniphier-system-cache"; +- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, +- <0x506c0000 0x400>; +- interrupts = <0 174 4>, <0 175 4>; +- cache-unified; +- cache-size = <(768 * 1024)>; +- cache-sets = <256>; +- cache-line-size = <128>; +- cache-level = <2>; +- }; +- +- spi0: spi@54006000 { +- compatible = "socionext,uniphier-scssi"; +- status = "disabled"; +- reg = <0x54006000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 39 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0>; +- clocks = <&peri_clk 11>; +- resets = <&peri_rst 11>; +- }; +- +- serial0: serial@54006800 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006800 0x40>; +- interrupts = <0 33 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- clocks = <&peri_clk 0>; +- resets = <&peri_rst 0>; +- }; +- +- serial1: serial@54006900 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006900 0x40>; +- interrupts = <0 35 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- clocks = <&peri_clk 1>; +- resets = <&peri_rst 1>; +- }; +- +- serial2: serial@54006a00 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006a00 0x40>; +- interrupts = <0 37 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- clocks = <&peri_clk 2>; +- resets = <&peri_rst 2>; +- }; +- +- serial3: serial@54006b00 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006b00 0x40>; +- interrupts = <0 177 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- clocks = <&peri_clk 3>; +- resets = <&peri_rst 3>; +- }; +- +- gpio: gpio@55000000 { +- compatible = "socionext,uniphier-gpio"; +- reg = <0x55000000 0x200>; +- interrupt-parent = <&aidet>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 0 0>; +- gpio-ranges-group-names = "gpio_range"; +- ngpios = <248>; +- socionext,interrupt-ranges = <0 48 16>, <16 154 5>; +- }; +- +- i2c0: i2c@58780000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58780000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 41 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0>; +- clocks = <&peri_clk 4>; +- resets = <&peri_rst 4>; +- clock-frequency = <100000>; +- }; +- +- i2c1: i2c@58781000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58781000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 42 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clocks = <&peri_clk 5>; +- resets = <&peri_rst 5>; +- clock-frequency = <100000>; +- }; +- +- i2c2: i2c@58782000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58782000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 43 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clocks = <&peri_clk 6>; +- resets = <&peri_rst 6>; +- clock-frequency = <100000>; +- }; +- +- i2c3: i2c@58783000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58783000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 44 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- clocks = <&peri_clk 7>; +- resets = <&peri_rst 7>; +- clock-frequency = <100000>; +- }; +- +- /* i2c4 does not exist */ +- +- /* chip-internal connection for DMD */ +- i2c5: i2c@58785000 { +- compatible = "socionext,uniphier-fi2c"; +- reg = <0x58785000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 25 4>; +- clocks = <&peri_clk 9>; +- resets = <&peri_rst 9>; +- clock-frequency = <400000>; +- }; +- +- /* chip-internal connection for HDMI */ +- i2c6: i2c@58786000 { +- compatible = "socionext,uniphier-fi2c"; +- reg = <0x58786000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 26 4>; +- clocks = <&peri_clk 10>; +- resets = <&peri_rst 10>; +- clock-frequency = <400000>; +- }; +- +- system_bus: system-bus@58c00000 { +- compatible = "socionext,uniphier-system-bus"; +- status = "disabled"; +- reg = <0x58c00000 0x400>; +- #address-cells = <2>; +- #size-cells = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_system_bus>; +- }; +- +- smpctrl@59801000 { +- compatible = "socionext,uniphier-smpctrl"; +- reg = <0x59801000 0x400>; +- }; +- +- mioctrl@59810000 { +- compatible = "socionext,uniphier-pro4-mioctrl", +- "simple-mfd", "syscon"; +- reg = <0x59810000 0x800>; +- +- mio_clk: clock { +- compatible = "socionext,uniphier-pro4-mio-clock"; +- #clock-cells = <1>; +- }; +- +- mio_rst: reset { +- compatible = "socionext,uniphier-pro4-mio-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- perictrl@59820000 { +- compatible = "socionext,uniphier-pro4-perictrl", +- "simple-mfd", "syscon"; +- reg = <0x59820000 0x200>; +- +- peri_clk: clock { +- compatible = "socionext,uniphier-pro4-peri-clock"; +- #clock-cells = <1>; +- }; +- +- peri_rst: reset { +- compatible = "socionext,uniphier-pro4-peri-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- dmac: dma-controller@5a000000 { +- compatible = "socionext,uniphier-mio-dmac"; +- reg = <0x5a000000 0x1000>; +- interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, +- <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>; +- clocks = <&mio_clk 7>; +- resets = <&mio_rst 7>; +- #dma-cells = <1>; +- }; +- +- sd: mmc@5a400000 { +- compatible = "socionext,uniphier-sd-v2.91"; +- status = "disabled"; +- reg = <0x5a400000 0x200>; +- interrupts = <0 76 4>; +- pinctrl-names = "default", "uhs"; +- pinctrl-0 = <&pinctrl_sd>; +- pinctrl-1 = <&pinctrl_sd_uhs>; +- clocks = <&mio_clk 0>; +- reset-names = "host", "bridge"; +- resets = <&mio_rst 0>, <&mio_rst 3>; +- dma-names = "rx-tx"; +- dmas = <&dmac 4>; +- bus-width = <4>; +- cap-sd-highspeed; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- }; +- +- emmc: mmc@5a500000 { +- compatible = "socionext,uniphier-sd-v2.91"; +- status = "disabled"; +- reg = <0x5a500000 0x200>; +- interrupts = <0 78 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_emmc>; +- clocks = <&mio_clk 1>; +- reset-names = "host", "bridge", "hw"; +- resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; +- dma-names = "rx-tx"; +- dmas = <&dmac 5>; +- bus-width = <8>; +- cap-mmc-highspeed; +- cap-mmc-hw-reset; +- non-removable; +- }; +- +- sd1: mmc@5a600000 { +- compatible = "socionext,uniphier-sd-v2.91"; +- status = "disabled"; +- reg = <0x5a600000 0x200>; +- interrupts = <0 85 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sd1>; +- clocks = <&mio_clk 2>; +- reset-names = "host", "bridge"; +- resets = <&mio_rst 2>, <&mio_rst 5>; +- dma-names = "rx-tx"; +- dmas = <&dmac 6>; +- bus-width = <4>; +- cap-sd-highspeed; +- }; +- +- usb2: usb@5a800100 { +- compatible = "socionext,uniphier-ehci", "generic-ehci"; +- status = "disabled"; +- reg = <0x5a800100 0x100>; +- interrupts = <0 80 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb2>; +- clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, +- <&mio_clk 12>; +- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, +- <&mio_rst 12>; +- phy-names = "usb"; +- phys = <&usb_phy0>; +- has-transaction-translator; +- }; +- +- usb3: usb@5a810100 { +- compatible = "socionext,uniphier-ehci", "generic-ehci"; +- status = "disabled"; +- reg = <0x5a810100 0x100>; +- interrupts = <0 81 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb3>; +- clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, +- <&mio_clk 13>; +- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, +- <&mio_rst 13>; +- phy-names = "usb"; +- phys = <&usb_phy1>; +- has-transaction-translator; +- }; +- +- soc_glue: soc-glue@5f800000 { +- compatible = "socionext,uniphier-pro4-soc-glue", +- "simple-mfd", "syscon"; +- reg = <0x5f800000 0x2000>; +- +- pinctrl: pinctrl { +- compatible = "socionext,uniphier-pro4-pinctrl"; +- }; +- +- usb-phy { +- compatible = "socionext,uniphier-pro4-usb2-phy"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- usb_phy0: phy@0 { +- reg = <0>; +- #phy-cells = <0>; +- }; +- +- usb_phy1: phy@1 { +- reg = <1>; +- #phy-cells = <0>; +- }; +- +- usb_phy2: phy@2 { +- reg = <2>; +- #phy-cells = <0>; +- vbus-supply = <&usb0_vbus>; +- }; +- +- usb_phy3: phy@3 { +- reg = <3>; +- #phy-cells = <0>; +- vbus-supply = <&usb1_vbus>; +- }; +- }; +- }; +- +- soc-glue@5f900000 { +- compatible = "socionext,uniphier-pro4-soc-glue-debug", +- "simple-mfd"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x5f900000 0x2000>; +- +- efuse@100 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x100 0x28>; +- }; +- +- efuse@130 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x130 0x8>; +- }; +- +- efuse@200 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x200 0x14>; +- }; +- }; +- +- xdmac: dma-controller@5fc10000 { +- compatible = "socionext,uniphier-xdmac"; +- reg = <0x5fc10000 0x5300>; +- interrupts = <0 188 4>; +- dma-channels = <16>; +- #dma-cells = <2>; +- }; +- +- aidet: interrupt-controller@5fc20000 { +- compatible = "socionext,uniphier-pro4-aidet"; +- reg = <0x5fc20000 0x200>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- timer@60000200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0x60000200 0x20>; +- interrupts = <1 11 0x304>; +- clocks = <&arm_timer_clk>; +- }; +- +- timer@60000600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x60000600 0x20>; +- interrupts = <1 13 0x304>; +- clocks = <&arm_timer_clk>; +- }; +- +- intc: interrupt-controller@60001000 { +- compatible = "arm,cortex-a9-gic"; +- reg = <0x60001000 0x1000>, +- <0x60000100 0x100>; +- #interrupt-cells = <3>; +- interrupt-controller; +- }; +- +- sysctrl@61840000 { +- compatible = "socionext,uniphier-pro4-sysctrl", +- "simple-mfd", "syscon"; +- reg = <0x61840000 0x10000>; +- +- sys_clk: clock { +- compatible = "socionext,uniphier-pro4-clock"; +- #clock-cells = <1>; +- }; +- +- sys_rst: reset { +- compatible = "socionext,uniphier-pro4-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- eth: ethernet@65000000 { +- compatible = "socionext,uniphier-pro4-ave4"; +- status = "disabled"; +- reg = <0x65000000 0x8500>; +- interrupts = <0 66 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ether_rgmii>; +- clock-names = "gio", "ether", "ether-gb", "ether-phy"; +- clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>, +- <&sys_clk 10>; +- reset-names = "gio", "ether"; +- resets = <&sys_rst 12>, <&sys_rst 6>; +- phy-mode = "rgmii"; +- local-mac-address = [00 00 00 00 00 00]; +- socionext,syscon-phy-mode = <&soc_glue 0>; +- +- mdio: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- usb0: usb@65a00000 { +- compatible = "socionext,uniphier-dwc3", "snps,dwc3"; +- status = "disabled"; +- reg = <0x65a00000 0xcd00>; +- interrupt-names = "host", "peripheral"; +- interrupts = <0 134 4>, <0 135 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb0>; +- clock-names = "ref", "bus_early", "suspend"; +- clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; +- resets = <&usb0_rst 4>; +- phys = <&usb_phy2>, <&usb0_ssphy>; +- dr_mode = "host"; +- }; +- +- usb-glue@65b00000 { +- compatible = "socionext,uniphier-pro4-dwc3-glue", +- "simple-mfd"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x65b00000 0x100>; +- +- usb0_vbus: regulator@0 { +- compatible = "socionext,uniphier-pro4-usb3-regulator"; +- reg = <0 0x10>; +- clock-names = "gio", "link"; +- clocks = <&sys_clk 12>, <&sys_clk 14>; +- reset-names = "gio", "link"; +- resets = <&sys_rst 12>, <&sys_rst 14>; +- }; +- +- usb0_ssphy: ss-phy@10 { +- compatible = "socionext,uniphier-pro4-usb3-ssphy"; +- reg = <0x10 0x10>; +- #phy-cells = <0>; +- clock-names = "gio", "link"; +- clocks = <&sys_clk 12>, <&sys_clk 14>; +- reset-names = "gio", "link"; +- resets = <&sys_rst 12>, <&sys_rst 14>; +- vbus-supply = <&usb0_vbus>; +- }; +- +- usb0_rst: reset@40 { +- compatible = "socionext,uniphier-pro4-usb3-reset"; +- reg = <0x40 0x4>; +- #reset-cells = <1>; +- clock-names = "gio", "link"; +- clocks = <&sys_clk 12>, <&sys_clk 14>; +- reset-names = "gio", "link"; +- resets = <&sys_rst 12>, <&sys_rst 14>; +- }; +- }; +- +- usb1: usb@65c00000 { +- compatible = "socionext,uniphier-dwc3", "snps,dwc3"; +- status = "disabled"; +- reg = <0x65c00000 0xcd00>; +- interrupt-names = "host", "peripheral"; +- interrupts = <0 137 4>, <0 138 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb1>; +- clock-names = "ref", "bus_early", "suspend"; +- clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; +- resets = <&usb1_rst 4>; +- phys = <&usb_phy3>; +- dr_mode = "host"; +- }; +- +- usb-glue@65d00000 { +- compatible = "socionext,uniphier-pro4-dwc3-glue", +- "simple-mfd"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x65d00000 0x100>; +- +- usb1_vbus: regulator@0 { +- compatible = "socionext,uniphier-pro4-usb3-regulator"; +- reg = <0 0x10>; +- clock-names = "gio", "link"; +- clocks = <&sys_clk 12>, <&sys_clk 15>; +- reset-names = "gio", "link"; +- resets = <&sys_rst 12>, <&sys_rst 15>; +- }; +- +- usb1_rst: reset@40 { +- compatible = "socionext,uniphier-pro4-usb3-reset"; +- reg = <0x40 0x4>; +- #reset-cells = <1>; +- clock-names = "gio", "link"; +- clocks = <&sys_clk 12>, <&sys_clk 15>; +- reset-names = "gio", "link"; +- resets = <&sys_rst 12>, <&sys_rst 15>; +- }; +- }; +- +- nand: nand-controller@68000000 { +- compatible = "socionext,uniphier-denali-nand-v5a"; +- status = "disabled"; +- reg-names = "nand_data", "denali_reg"; +- reg = <0x68000000 0x20>, <0x68100000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 65 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nand>; +- clock-names = "nand", "nand_x", "ecc"; +- clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; +- reset-names = "nand", "reg"; +- resets = <&sys_rst 2>, <&sys_rst 2>; +- }; +- }; +-}; +- +-#include "uniphier-pinctrl.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/uniphier-pro5.dtsi b/scripts/dtc/include-prefixes/arm/uniphier-pro5.dtsi +deleted file mode 100644 +index 3525125832dd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/uniphier-pro5.dtsi ++++ /dev/null +@@ -1,698 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier Pro5 SoC +-// +-// Copyright (C) 2015-2016 Socionext Inc. +-// Author: Masahiro Yamada +- +-/ { +- compatible = "socionext,uniphier-pro5"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- clocks = <&sys_clk 32>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- operating-points-v2 = <&cpu_opp>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <1>; +- clocks = <&sys_clk 32>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- operating-points-v2 = <&cpu_opp>; +- }; +- }; +- +- cpu_opp: opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- clock-latency-ns = <300>; +- }; +- opp-116667000 { +- opp-hz = /bits/ 64 <116667000>; +- clock-latency-ns = <300>; +- }; +- opp-150000000 { +- opp-hz = /bits/ 64 <150000000>; +- clock-latency-ns = <300>; +- }; +- opp-175000000 { +- opp-hz = /bits/ 64 <175000000>; +- clock-latency-ns = <300>; +- }; +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- clock-latency-ns = <300>; +- }; +- opp-233334000 { +- opp-hz = /bits/ 64 <233334000>; +- clock-latency-ns = <300>; +- }; +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- clock-latency-ns = <300>; +- }; +- opp-350000000 { +- opp-hz = /bits/ 64 <350000000>; +- clock-latency-ns = <300>; +- }; +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- clock-latency-ns = <300>; +- }; +- opp-466667000 { +- opp-hz = /bits/ 64 <466667000>; +- clock-latency-ns = <300>; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- clock-latency-ns = <300>; +- }; +- opp-700000000 { +- opp-hz = /bits/ 64 <700000000>; +- clock-latency-ns = <300>; +- }; +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- clock-latency-ns = <300>; +- }; +- opp-933334000 { +- opp-hz = /bits/ 64 <933334000>; +- clock-latency-ns = <300>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- clock-latency-ns = <300>; +- }; +- opp-1400000000 { +- opp-hz = /bits/ 64 <1400000000>; +- clock-latency-ns = <300>; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- clocks { +- refclk: ref { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <20000000>; +- }; +- +- arm_timer_clk: arm-timer { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- interrupt-parent = <&intc>; +- +- l2: cache-controller@500c0000 { +- compatible = "socionext,uniphier-system-cache"; +- reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, +- <0x506c0000 0x400>; +- interrupts = <0 190 4>, <0 191 4>; +- cache-unified; +- cache-size = <(2 * 1024 * 1024)>; +- cache-sets = <512>; +- cache-line-size = <128>; +- cache-level = <2>; +- next-level-cache = <&l3>; +- }; +- +- l3: cache-controller@500c8000 { +- compatible = "socionext,uniphier-system-cache"; +- reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, +- <0x506c8000 0x400>; +- interrupts = <0 174 4>, <0 175 4>; +- cache-unified; +- cache-size = <(2 * 1024 * 1024)>; +- cache-sets = <512>; +- cache-line-size = <256>; +- cache-level = <3>; +- }; +- +- spi0: spi@54006000 { +- compatible = "socionext,uniphier-scssi"; +- status = "disabled"; +- reg = <0x54006000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 39 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0>; +- clocks = <&peri_clk 11>; +- resets = <&peri_rst 11>; +- }; +- +- spi1: spi@54006100 { +- compatible = "socionext,uniphier-scssi"; +- status = "disabled"; +- reg = <0x54006100 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 216 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1>; +- clocks = <&peri_clk 11>; /* common with spi0 */ +- resets = <&peri_rst 12>; +- }; +- +- serial0: serial@54006800 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006800 0x40>; +- interrupts = <0 33 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- clocks = <&peri_clk 0>; +- resets = <&peri_rst 0>; +- }; +- +- serial1: serial@54006900 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006900 0x40>; +- interrupts = <0 35 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- clocks = <&peri_clk 1>; +- resets = <&peri_rst 1>; +- }; +- +- serial2: serial@54006a00 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006a00 0x40>; +- interrupts = <0 37 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- clocks = <&peri_clk 2>; +- resets = <&peri_rst 2>; +- }; +- +- serial3: serial@54006b00 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006b00 0x40>; +- interrupts = <0 177 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- clocks = <&peri_clk 3>; +- resets = <&peri_rst 3>; +- }; +- +- gpio: gpio@55000000 { +- compatible = "socionext,uniphier-gpio"; +- reg = <0x55000000 0x200>; +- interrupt-parent = <&aidet>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 0 0>; +- gpio-ranges-group-names = "gpio_range"; +- ngpios = <248>; +- socionext,interrupt-ranges = <0 48 16>, <16 154 5>; +- }; +- +- i2c0: i2c@58780000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58780000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 41 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0>; +- clocks = <&peri_clk 4>; +- resets = <&peri_rst 4>; +- clock-frequency = <100000>; +- }; +- +- i2c1: i2c@58781000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58781000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 42 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clocks = <&peri_clk 5>; +- resets = <&peri_rst 5>; +- clock-frequency = <100000>; +- }; +- +- i2c2: i2c@58782000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58782000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 43 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clocks = <&peri_clk 6>; +- resets = <&peri_rst 6>; +- clock-frequency = <100000>; +- }; +- +- i2c3: i2c@58783000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58783000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 44 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- clocks = <&peri_clk 7>; +- resets = <&peri_rst 7>; +- clock-frequency = <100000>; +- }; +- +- /* i2c4 does not exist */ +- +- /* chip-internal connection for DMD */ +- i2c5: i2c@58785000 { +- compatible = "socionext,uniphier-fi2c"; +- reg = <0x58785000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 25 4>; +- clocks = <&peri_clk 9>; +- resets = <&peri_rst 9>; +- clock-frequency = <400000>; +- }; +- +- /* chip-internal connection for HDMI */ +- i2c6: i2c@58786000 { +- compatible = "socionext,uniphier-fi2c"; +- reg = <0x58786000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 26 4>; +- clocks = <&peri_clk 10>; +- resets = <&peri_rst 10>; +- clock-frequency = <400000>; +- }; +- +- system_bus: system-bus@58c00000 { +- compatible = "socionext,uniphier-system-bus"; +- status = "disabled"; +- reg = <0x58c00000 0x400>; +- #address-cells = <2>; +- #size-cells = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_system_bus>; +- }; +- +- smpctrl@59801000 { +- compatible = "socionext,uniphier-smpctrl"; +- reg = <0x59801000 0x400>; +- }; +- +- sdctrl@59810000 { +- compatible = "socionext,uniphier-pro5-sdctrl", +- "simple-mfd", "syscon"; +- reg = <0x59810000 0x400>; +- +- sd_clk: clock { +- compatible = "socionext,uniphier-pro5-sd-clock"; +- #clock-cells = <1>; +- }; +- +- sd_rst: reset { +- compatible = "socionext,uniphier-pro5-sd-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- perictrl@59820000 { +- compatible = "socionext,uniphier-pro5-perictrl", +- "simple-mfd", "syscon"; +- reg = <0x59820000 0x200>; +- +- peri_clk: clock { +- compatible = "socionext,uniphier-pro5-peri-clock"; +- #clock-cells = <1>; +- }; +- +- peri_rst: reset { +- compatible = "socionext,uniphier-pro5-peri-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- soc-glue@5f800000 { +- compatible = "socionext,uniphier-pro5-soc-glue", +- "simple-mfd", "syscon"; +- reg = <0x5f800000 0x2000>; +- +- pinctrl: pinctrl { +- compatible = "socionext,uniphier-pro5-pinctrl"; +- }; +- }; +- +- soc-glue@5f900000 { +- compatible = "socionext,uniphier-pro5-soc-glue-debug", +- "simple-mfd"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x5f900000 0x2000>; +- +- efuse@100 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x100 0x28>; +- }; +- +- efuse@130 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x130 0x8>; +- }; +- +- efuse@200 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x200 0x28>; +- }; +- +- efuse@300 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x300 0x14>; +- }; +- +- efuse@400 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x400 0x8>; +- }; +- }; +- +- xdmac: dma-controller@5fc10000 { +- compatible = "socionext,uniphier-xdmac"; +- reg = <0x5fc10000 0x5300>; +- interrupts = <0 188 4>; +- dma-channels = <16>; +- #dma-cells = <2>; +- }; +- +- aidet: interrupt-controller@5fc20000 { +- compatible = "socionext,uniphier-pro5-aidet"; +- reg = <0x5fc20000 0x200>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- timer@60000200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0x60000200 0x20>; +- interrupts = <1 11 0x304>; +- clocks = <&arm_timer_clk>; +- }; +- +- timer@60000600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x60000600 0x20>; +- interrupts = <1 13 0x304>; +- clocks = <&arm_timer_clk>; +- }; +- +- intc: interrupt-controller@60001000 { +- compatible = "arm,cortex-a9-gic"; +- reg = <0x60001000 0x1000>, +- <0x60000100 0x100>; +- #interrupt-cells = <3>; +- interrupt-controller; +- }; +- +- sysctrl@61840000 { +- compatible = "socionext,uniphier-pro5-sysctrl", +- "simple-mfd", "syscon"; +- reg = <0x61840000 0x10000>; +- +- sys_clk: clock { +- compatible = "socionext,uniphier-pro5-clock"; +- #clock-cells = <1>; +- }; +- +- sys_rst: reset { +- compatible = "socionext,uniphier-pro5-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- usb0: usb@65a00000 { +- compatible = "socionext,uniphier-dwc3", "snps,dwc3"; +- status = "disabled"; +- reg = <0x65a00000 0xcd00>; +- interrupt-names = "host"; +- interrupts = <0 134 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb0>; +- clock-names = "ref", "bus_early", "suspend"; +- clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; +- resets = <&usb0_rst 15>; +- phys = <&usb0_hsphy0>, <&usb0_ssphy0>; +- dr_mode = "host"; +- }; +- +- usb-glue@65b00000 { +- compatible = "socionext,uniphier-pro5-dwc3-glue", +- "simple-mfd"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x65b00000 0x400>; +- +- usb0_rst: reset@0 { +- compatible = "socionext,uniphier-pro5-usb3-reset"; +- reg = <0x0 0x4>; +- #reset-cells = <1>; +- clock-names = "gio", "link"; +- clocks = <&sys_clk 12>, <&sys_clk 14>; +- reset-names = "gio", "link"; +- resets = <&sys_rst 12>, <&sys_rst 14>; +- }; +- +- usb0_vbus0: regulator@100 { +- compatible = "socionext,uniphier-pro5-usb3-regulator"; +- reg = <0x100 0x10>; +- clock-names = "gio", "link"; +- clocks = <&sys_clk 12>, <&sys_clk 14>; +- reset-names = "gio", "link"; +- resets = <&sys_rst 12>, <&sys_rst 14>; +- }; +- +- usb0_hsphy0: hs-phy@280 { +- compatible = "socionext,uniphier-pro5-usb3-hsphy"; +- reg = <0x280 0x10>; +- #phy-cells = <0>; +- clock-names = "gio", "link"; +- clocks = <&sys_clk 12>, <&sys_clk 14>; +- reset-names = "gio", "link"; +- resets = <&sys_rst 12>, <&sys_rst 14>; +- vbus-supply = <&usb0_vbus0>; +- }; +- +- usb0_ssphy0: ss-phy@380 { +- compatible = "socionext,uniphier-pro5-usb3-ssphy"; +- reg = <0x380 0x10>; +- #phy-cells = <0>; +- clock-names = "gio", "link"; +- clocks = <&sys_clk 12>, <&sys_clk 14>; +- reset-names = "gio", "link"; +- resets = <&sys_rst 12>, <&sys_rst 14>; +- vbus-supply = <&usb0_vbus0>; +- }; +- }; +- +- usb1: usb@65c00000 { +- compatible = "socionext,uniphier-dwc3", "snps,dwc3"; +- status = "disabled"; +- reg = <0x65c00000 0xcd00>; +- interrupt-names = "host"; +- interrupts = <0 137 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; +- clock-names = "ref", "bus_early", "suspend"; +- clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; +- resets = <&usb1_rst 15>; +- phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>; +- dr_mode = "host"; +- }; +- +- usb-glue@65d00000 { +- compatible = "socionext,uniphier-pro5-dwc3-glue", +- "simple-mfd"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x65d00000 0x400>; +- +- usb1_rst: reset@0 { +- compatible = "socionext,uniphier-pro5-usb3-reset"; +- reg = <0x0 0x4>; +- #reset-cells = <1>; +- clock-names = "gio", "link"; +- clocks = <&sys_clk 12>, <&sys_clk 15>; +- reset-names = "gio", "link"; +- resets = <&sys_rst 12>, <&sys_rst 15>; +- }; +- +- usb1_vbus0: regulator@100 { +- compatible = "socionext,uniphier-pro5-usb3-regulator"; +- reg = <0x100 0x10>; +- clock-names = "gio", "link"; +- clocks = <&sys_clk 12>, <&sys_clk 15>; +- reset-names = "gio", "link"; +- resets = <&sys_rst 12>, <&sys_rst 15>; +- }; +- +- usb1_vbus1: regulator@110 { +- compatible = "socionext,uniphier-pro5-usb3-regulator"; +- reg = <0x110 0x10>; +- clock-names = "gio", "link"; +- clocks = <&sys_clk 12>, <&sys_clk 15>; +- reset-names = "gio", "link"; +- resets = <&sys_rst 12>, <&sys_rst 15>; +- }; +- +- usb1_hsphy0: hs-phy@280 { +- compatible = "socionext,uniphier-pro5-usb3-hsphy"; +- reg = <0x280 0x10>; +- #phy-cells = <0>; +- clock-names = "gio", "link"; +- clocks = <&sys_clk 12>, <&sys_clk 15>; +- reset-names = "gio", "link"; +- resets = <&sys_rst 12>, <&sys_rst 15>; +- vbus-supply = <&usb1_vbus0>; +- }; +- +- usb1_hsphy1: hs-phy@290 { +- compatible = "socionext,uniphier-pro5-usb3-hsphy"; +- reg = <0x290 0x10>; +- #phy-cells = <0>; +- clock-names = "gio", "link"; +- clocks = <&sys_clk 12>, <&sys_clk 15>; +- reset-names = "gio", "link"; +- resets = <&sys_rst 12>, <&sys_rst 15>; +- vbus-supply = <&usb1_vbus1>; +- }; +- +- usb1_ssphy0: ss-phy@380 { +- compatible = "socionext,uniphier-pro5-usb3-ssphy"; +- reg = <0x380 0x10>; +- #phy-cells = <0>; +- clock-names = "gio", "link"; +- clocks = <&sys_clk 12>, <&sys_clk 15>; +- reset-names = "gio", "link"; +- resets = <&sys_rst 12>, <&sys_rst 15>; +- vbus-supply = <&usb1_vbus0>; +- }; +- }; +- +- pcie_ep: pcie-ep@66000000 { +- compatible = "socionext,uniphier-pro5-pcie-ep", +- "snps,dw-pcie-ep"; +- status = "disabled"; +- reg-names = "dbi", "dbi2", "link", "addr_space"; +- reg = <0x66000000 0x1000>, <0x66001000 0x1000>, +- <0x66010000 0x10000>, <0x67000000 0x400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie>; +- clock-names = "gio", "link"; +- clocks = <&sys_clk 12>, <&sys_clk 24>; +- reset-names = "gio", "link"; +- resets = <&sys_rst 12>, <&sys_rst 24>; +- num-ib-windows = <16>; +- num-ob-windows = <16>; +- num-lanes = <4>; +- phy-names = "pcie-phy"; +- phys = <&pcie_phy>; +- }; +- +- pcie_phy: phy@66038000 { +- compatible = "socionext,uniphier-pro5-pcie-phy"; +- reg = <0x66038000 0x4000>; +- #phy-cells = <0>; +- clock-names = "gio", "link"; +- clocks = <&sys_clk 12>, <&sys_clk 24>; +- reset-names = "gio", "link"; +- resets = <&sys_rst 12>, <&sys_rst 24>; +- }; +- +- nand: nand-controller@68000000 { +- compatible = "socionext,uniphier-denali-nand-v5b"; +- status = "disabled"; +- reg-names = "nand_data", "denali_reg"; +- reg = <0x68000000 0x20>, <0x68100000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 65 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nand>; +- clock-names = "nand", "nand_x", "ecc"; +- clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; +- reset-names = "nand", "reg"; +- resets = <&sys_rst 2>, <&sys_rst 2>; +- }; +- +- emmc: mmc@68400000 { +- compatible = "socionext,uniphier-sd-v3.1"; +- status = "disabled"; +- reg = <0x68400000 0x800>; +- interrupts = <0 78 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_emmc>; +- clocks = <&sd_clk 1>; +- reset-names = "host", "hw"; +- resets = <&sd_rst 1>, <&sd_rst 6>; +- bus-width = <8>; +- cap-mmc-highspeed; +- cap-mmc-hw-reset; +- non-removable; +- }; +- +- sd: mmc@68800000 { +- compatible = "socionext,uniphier-sd-v3.1"; +- status = "disabled"; +- reg = <0x68800000 0x800>; +- interrupts = <0 76 4>; +- pinctrl-names = "default", "uhs"; +- pinctrl-0 = <&pinctrl_sd>; +- pinctrl-1 = <&pinctrl_sd_uhs>; +- clocks = <&sd_clk 0>; +- reset-names = "host"; +- resets = <&sd_rst 0>; +- bus-width = <4>; +- cap-sd-highspeed; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- }; +- }; +-}; +- +-#include "uniphier-pinctrl.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/uniphier-pxs2-gentil.dts b/scripts/dtc/include-prefixes/arm/uniphier-pxs2-gentil.dts +deleted file mode 100644 +index 759384b60663..000000000000 +--- a/scripts/dtc/include-prefixes/arm/uniphier-pxs2-gentil.dts ++++ /dev/null +@@ -1,101 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier PXs2 Gentil Board +-// +-// Copyright (C) 2015-2016 Socionext Inc. +-// Author: Masahiro Yamada +- +-/dts-v1/; +-#include "uniphier-pxs2.dtsi" +- +-/ { +- model = "UniPhier PXs2 Gentil Board"; +- compatible = "socionext,uniphier-pxs2-gentil", +- "socionext,uniphier-pxs2"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- serial0 = &serial2; +- serial1 = &serial0; +- serial2 = &serial1; +- i2c0 = &i2c0; +- i2c2 = &i2c2; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- ethernet0 = ð +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x80000000>; +- }; +- +- sound { +- compatible = "audio-graph-card"; +- label = "UniPhier PXs2"; +- dais = <&i2s_port2>; +- }; +-}; +- +-&serial2 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- eeprom@54 { +- compatible = "st,24c64", "atmel,24c64"; +- reg = <0x54>; +- pagesize = <32>; +- }; +-}; +- +-&i2s_aux { +- dai-format = "i2s"; +- remote-endpoint = <&wm_speaker>; +-}; +- +-&i2c2 { +- status = "okay"; +- +- wm8960@1a { +- compatible = "wlf,wm8960"; +- reg = <0x1a>; +- #sound-dai-cells = <0>; +- +- port@0 { +- wm_speaker: endpoint { +- dai-format = "i2s"; +- remote-endpoint = <&i2s_aux>; +- }; +- }; +- }; +-}; +- +-&emmc { +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- phy-handle = <ðphy>; +-}; +- +-&mdio { +- ethphy: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/uniphier-pxs2-vodka.dts b/scripts/dtc/include-prefixes/arm/uniphier-pxs2-vodka.dts +deleted file mode 100644 +index 7e08a459f7d8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/uniphier-pxs2-vodka.dts ++++ /dev/null +@@ -1,98 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier PXs2 Vodka Board +-// +-// Copyright (C) 2015-2016 Socionext Inc. +-// Author: Masahiro Yamada +- +-/dts-v1/; +-#include "uniphier-pxs2.dtsi" +- +-/ { +- model = "UniPhier PXs2 Vodka Board"; +- compatible = "socionext,uniphier-pxs2-vodka", "socionext,uniphier-pxs2"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- serial0 = &serial2; +- serial1 = &serial0; +- serial2 = &serial1; +- i2c0 = &i2c0; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- ethernet0 = ð +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x80000000>; +- }; +- +- sound { +- compatible = "audio-graph-card"; +- label = "UniPhier PXs2"; +- dais = <&spdif_port0 +- &comp_spdif_port0>; +- }; +- +- spdif-out { +- compatible = "linux,spdif-dit"; +- #sound-dai-cells = <0>; +- +- port@0 { +- spdif_tx: endpoint { +- remote-endpoint = <&spdif_hiecout1>; +- }; +- }; +- }; +- +- comp-spdif-out { +- compatible = "linux,spdif-dit"; +- #sound-dai-cells = <0>; +- +- port@0 { +- comp_spdif_tx: endpoint { +- remote-endpoint = <&comp_spdif_hiecout1>; +- }; +- }; +- }; +-}; +- +-&serial2 { +- status = "okay"; +-}; +- +-&spdif_hiecout1 { +- remote-endpoint = <&spdif_tx>; +-}; +- +-&comp_spdif_hiecout1 { +- remote-endpoint = <&comp_spdif_tx>; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&emmc { +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- phy-handle = <ðphy>; +-}; +- +-&mdio { +- ethphy: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&usb0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/uniphier-pxs2.dtsi b/scripts/dtc/include-prefixes/arm/uniphier-pxs2.dtsi +deleted file mode 100644 +index e81e5937a60a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/uniphier-pxs2.dtsi ++++ /dev/null +@@ -1,794 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier PXs2 SoC +-// +-// Copyright (C) 2015-2016 Socionext Inc. +-// Author: Masahiro Yamada +- +-#include +-#include +- +-/ { +- compatible = "socionext,uniphier-pxs2"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- clocks = <&sys_clk 32>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- operating-points-v2 = <&cpu_opp>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <1>; +- clocks = <&sys_clk 32>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- operating-points-v2 = <&cpu_opp>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <2>; +- clocks = <&sys_clk 32>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- operating-points-v2 = <&cpu_opp>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <3>; +- clocks = <&sys_clk 32>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- operating-points-v2 = <&cpu_opp>; +- #cooling-cells = <2>; +- }; +- }; +- +- cpu_opp: opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- clock-latency-ns = <300>; +- }; +- opp-150000000 { +- opp-hz = /bits/ 64 <150000000>; +- clock-latency-ns = <300>; +- }; +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- clock-latency-ns = <300>; +- }; +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- clock-latency-ns = <300>; +- }; +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- clock-latency-ns = <300>; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- clock-latency-ns = <300>; +- }; +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- clock-latency-ns = <300>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- clock-latency-ns = <300>; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- clocks { +- refclk: ref { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- arm_timer_clk: arm-timer { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- }; +- }; +- +- thermal-zones { +- cpu-thermal { +- polling-delay-passive = <250>; /* 250ms */ +- polling-delay = <1000>; /* 1000ms */ +- thermal-sensors = <&pvtctl>; +- +- trips { +- cpu_crit: cpu-crit { +- temperature = <95000>; /* 95C */ +- hysteresis = <2000>; +- type = "critical"; +- }; +- cpu_alert: cpu-alert { +- temperature = <85000>; /* 85C */ +- hysteresis = <2000>; +- type = "passive"; +- }; +- }; +- +- cooling-maps { +- map { +- trip = <&cpu_alert>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- interrupt-parent = <&intc>; +- +- l2: cache-controller@500c0000 { +- compatible = "socionext,uniphier-system-cache"; +- reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, +- <0x506c0000 0x400>; +- interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; +- cache-unified; +- cache-size = <(1280 * 1024)>; +- cache-sets = <512>; +- cache-line-size = <128>; +- cache-level = <2>; +- }; +- +- spi0: spi@54006000 { +- compatible = "socionext,uniphier-scssi"; +- status = "disabled"; +- reg = <0x54006000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 39 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0>; +- clocks = <&peri_clk 11>; +- resets = <&peri_rst 11>; +- }; +- +- spi1: spi@54006100 { +- compatible = "socionext,uniphier-scssi"; +- status = "disabled"; +- reg = <0x54006100 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 216 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1>; +- clocks = <&peri_clk 12>; +- resets = <&peri_rst 12>; +- }; +- +- serial0: serial@54006800 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006800 0x40>; +- interrupts = <0 33 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- clocks = <&peri_clk 0>; +- resets = <&peri_rst 0>; +- }; +- +- serial1: serial@54006900 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006900 0x40>; +- interrupts = <0 35 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- clocks = <&peri_clk 1>; +- resets = <&peri_rst 1>; +- }; +- +- serial2: serial@54006a00 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006a00 0x40>; +- interrupts = <0 37 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- clocks = <&peri_clk 2>; +- resets = <&peri_rst 2>; +- }; +- +- serial3: serial@54006b00 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006b00 0x40>; +- interrupts = <0 177 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- clocks = <&peri_clk 3>; +- resets = <&peri_rst 3>; +- }; +- +- gpio: gpio@55000000 { +- compatible = "socionext,uniphier-gpio"; +- reg = <0x55000000 0x200>; +- interrupt-parent = <&aidet>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 0 0>, +- <&pinctrl 96 0 0>; +- gpio-ranges-group-names = "gpio_range0", +- "gpio_range1"; +- ngpios = <232>; +- socionext,interrupt-ranges = <0 48 16>, <16 154 5>, +- <21 217 3>; +- }; +- +- audio@56000000 { +- compatible = "socionext,uniphier-pxs2-aio"; +- reg = <0x56000000 0x80000>; +- interrupts = <0 144 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ain1>, +- <&pinctrl_ain2>, +- <&pinctrl_ainiec1>, +- <&pinctrl_aout2>, +- <&pinctrl_aout3>, +- <&pinctrl_aoutiec1>, +- <&pinctrl_aoutiec2>; +- clock-names = "aio"; +- clocks = <&sys_clk 40>; +- reset-names = "aio"; +- resets = <&sys_rst 40>; +- #sound-dai-cells = <1>; +- socionext,syscon = <&soc_glue>; +- +- i2s_port0: port@0 { +- i2s_hdmi: endpoint { +- }; +- }; +- +- i2s_port1: port@1 { +- i2s_line: endpoint { +- }; +- }; +- +- i2s_port2: port@2 { +- i2s_aux: endpoint { +- }; +- }; +- +- spdif_port0: port@3 { +- spdif_hiecout1: endpoint { +- }; +- }; +- +- spdif_port1: port@4 { +- spdif_iecout1: endpoint { +- }; +- }; +- +- comp_spdif_port0: port@5 { +- comp_spdif_hiecout1: endpoint { +- }; +- }; +- +- comp_spdif_port1: port@6 { +- comp_spdif_iecout1: endpoint { +- }; +- }; +- }; +- +- i2c0: i2c@58780000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58780000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 41 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0>; +- clocks = <&peri_clk 4>; +- resets = <&peri_rst 4>; +- clock-frequency = <100000>; +- }; +- +- i2c1: i2c@58781000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58781000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 42 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clocks = <&peri_clk 5>; +- resets = <&peri_rst 5>; +- clock-frequency = <100000>; +- }; +- +- i2c2: i2c@58782000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58782000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 43 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clocks = <&peri_clk 6>; +- resets = <&peri_rst 6>; +- clock-frequency = <100000>; +- }; +- +- i2c3: i2c@58783000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58783000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 44 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- clocks = <&peri_clk 7>; +- resets = <&peri_rst 7>; +- clock-frequency = <100000>; +- }; +- +- /* chip-internal connection for DMD */ +- i2c4: i2c@58784000 { +- compatible = "socionext,uniphier-fi2c"; +- reg = <0x58784000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 45 4>; +- clocks = <&peri_clk 8>; +- resets = <&peri_rst 8>; +- clock-frequency = <400000>; +- }; +- +- /* chip-internal connection for STM */ +- i2c5: i2c@58785000 { +- compatible = "socionext,uniphier-fi2c"; +- reg = <0x58785000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 25 4>; +- clocks = <&peri_clk 9>; +- resets = <&peri_rst 9>; +- clock-frequency = <400000>; +- }; +- +- /* chip-internal connection for HDMI */ +- i2c6: i2c@58786000 { +- compatible = "socionext,uniphier-fi2c"; +- reg = <0x58786000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 26 4>; +- clocks = <&peri_clk 10>; +- resets = <&peri_rst 10>; +- clock-frequency = <400000>; +- }; +- +- system_bus: system-bus@58c00000 { +- compatible = "socionext,uniphier-system-bus"; +- status = "disabled"; +- reg = <0x58c00000 0x400>; +- #address-cells = <2>; +- #size-cells = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_system_bus>; +- }; +- +- smpctrl@59801000 { +- compatible = "socionext,uniphier-smpctrl"; +- reg = <0x59801000 0x400>; +- }; +- +- sdctrl@59810000 { +- compatible = "socionext,uniphier-pxs2-sdctrl", +- "simple-mfd", "syscon"; +- reg = <0x59810000 0x400>; +- +- sd_clk: clock { +- compatible = "socionext,uniphier-pxs2-sd-clock"; +- #clock-cells = <1>; +- }; +- +- sd_rst: reset { +- compatible = "socionext,uniphier-pxs2-sd-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- perictrl@59820000 { +- compatible = "socionext,uniphier-pxs2-perictrl", +- "simple-mfd", "syscon"; +- reg = <0x59820000 0x200>; +- +- peri_clk: clock { +- compatible = "socionext,uniphier-pxs2-peri-clock"; +- #clock-cells = <1>; +- }; +- +- peri_rst: reset { +- compatible = "socionext,uniphier-pxs2-peri-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- emmc: mmc@5a000000 { +- compatible = "socionext,uniphier-sd-v3.1.1"; +- status = "disabled"; +- reg = <0x5a000000 0x800>; +- interrupts = <0 78 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_emmc>; +- clocks = <&sd_clk 1>; +- reset-names = "host", "hw"; +- resets = <&sd_rst 1>, <&sd_rst 6>; +- bus-width = <8>; +- cap-mmc-highspeed; +- cap-mmc-hw-reset; +- non-removable; +- }; +- +- sd: mmc@5a400000 { +- compatible = "socionext,uniphier-sd-v3.1.1"; +- status = "disabled"; +- reg = <0x5a400000 0x800>; +- interrupts = <0 76 4>; +- pinctrl-names = "default", "uhs"; +- pinctrl-0 = <&pinctrl_sd>; +- pinctrl-1 = <&pinctrl_sd_uhs>; +- clocks = <&sd_clk 0>; +- reset-names = "host"; +- resets = <&sd_rst 0>; +- bus-width = <4>; +- cap-sd-highspeed; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- }; +- +- soc_glue: soc-glue@5f800000 { +- compatible = "socionext,uniphier-pxs2-soc-glue", +- "simple-mfd", "syscon"; +- reg = <0x5f800000 0x2000>; +- +- pinctrl: pinctrl { +- compatible = "socionext,uniphier-pxs2-pinctrl"; +- }; +- }; +- +- soc-glue@5f900000 { +- compatible = "socionext,uniphier-pxs2-soc-glue-debug", +- "simple-mfd"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x5f900000 0x2000>; +- +- efuse@100 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x100 0x28>; +- }; +- +- efuse@200 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x200 0x58>; +- }; +- }; +- +- xdmac: dma-controller@5fc10000 { +- compatible = "socionext,uniphier-xdmac"; +- reg = <0x5fc10000 0x5300>; +- interrupts = <0 188 4>; +- dma-channels = <16>; +- #dma-cells = <2>; +- }; +- +- aidet: interrupt-controller@5fc20000 { +- compatible = "socionext,uniphier-pxs2-aidet"; +- reg = <0x5fc20000 0x200>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- timer@60000200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0x60000200 0x20>; +- interrupts = <1 11 0xf04>; +- clocks = <&arm_timer_clk>; +- }; +- +- timer@60000600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x60000600 0x20>; +- interrupts = <1 13 0xf04>; +- clocks = <&arm_timer_clk>; +- }; +- +- intc: interrupt-controller@60001000 { +- compatible = "arm,cortex-a9-gic"; +- reg = <0x60001000 0x1000>, +- <0x60000100 0x100>; +- #interrupt-cells = <3>; +- interrupt-controller; +- }; +- +- sysctrl@61840000 { +- compatible = "socionext,uniphier-pxs2-sysctrl", +- "simple-mfd", "syscon"; +- reg = <0x61840000 0x10000>; +- +- sys_clk: clock { +- compatible = "socionext,uniphier-pxs2-clock"; +- #clock-cells = <1>; +- }; +- +- sys_rst: reset { +- compatible = "socionext,uniphier-pxs2-reset"; +- #reset-cells = <1>; +- }; +- +- pvtctl: pvtctl { +- compatible = "socionext,uniphier-pxs2-thermal"; +- interrupts = <0 3 4>; +- #thermal-sensor-cells = <0>; +- socionext,tmod-calibration = <0x0f86 0x6844>; +- }; +- }; +- +- eth: ethernet@65000000 { +- compatible = "socionext,uniphier-pxs2-ave4"; +- status = "disabled"; +- reg = <0x65000000 0x8500>; +- interrupts = <0 66 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ether_rgmii>; +- clock-names = "ether"; +- clocks = <&sys_clk 6>; +- reset-names = "ether"; +- resets = <&sys_rst 6>; +- phy-mode = "rgmii-id"; +- local-mac-address = [00 00 00 00 00 00]; +- socionext,syscon-phy-mode = <&soc_glue 0>; +- +- mdio: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- usb0: usb@65a00000 { +- compatible = "socionext,uniphier-dwc3", "snps,dwc3"; +- status = "disabled"; +- reg = <0x65a00000 0xcd00>; +- interrupt-names = "host", "peripheral"; +- interrupts = <0 134 4>, <0 135 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; +- clock-names = "ref", "bus_early", "suspend"; +- clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; +- resets = <&usb0_rst 15>; +- phys = <&usb0_hsphy0>, <&usb0_hsphy1>, +- <&usb0_ssphy0>, <&usb0_ssphy1>; +- dr_mode = "host"; +- }; +- +- usb-glue@65b00000 { +- compatible = "socionext,uniphier-pxs2-dwc3-glue", +- "simple-mfd"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x65b00000 0x400>; +- +- usb0_rst: reset@0 { +- compatible = "socionext,uniphier-pxs2-usb3-reset"; +- reg = <0x0 0x4>; +- #reset-cells = <1>; +- clock-names = "link"; +- clocks = <&sys_clk 14>; +- reset-names = "link"; +- resets = <&sys_rst 14>; +- }; +- +- usb0_vbus0: regulator@100 { +- compatible = "socionext,uniphier-pxs2-usb3-regulator"; +- reg = <0x100 0x10>; +- clock-names = "link"; +- clocks = <&sys_clk 14>; +- reset-names = "link"; +- resets = <&sys_rst 14>; +- }; +- +- usb0_vbus1: regulator@110 { +- compatible = "socionext,uniphier-pxs2-usb3-regulator"; +- reg = <0x110 0x10>; +- clock-names = "link"; +- clocks = <&sys_clk 14>; +- reset-names = "link"; +- resets = <&sys_rst 14>; +- }; +- +- usb0_hsphy0: hs-phy@200 { +- compatible = "socionext,uniphier-pxs2-usb3-hsphy"; +- reg = <0x200 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy"; +- clocks = <&sys_clk 14>, <&sys_clk 16>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 14>, <&sys_rst 16>; +- vbus-supply = <&usb0_vbus0>; +- }; +- +- usb0_hsphy1: hs-phy@210 { +- compatible = "socionext,uniphier-pxs2-usb3-hsphy"; +- reg = <0x210 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy"; +- clocks = <&sys_clk 14>, <&sys_clk 16>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 14>, <&sys_rst 16>; +- vbus-supply = <&usb0_vbus1>; +- }; +- +- usb0_ssphy0: ss-phy@300 { +- compatible = "socionext,uniphier-pxs2-usb3-ssphy"; +- reg = <0x300 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy"; +- clocks = <&sys_clk 14>, <&sys_clk 17>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 14>, <&sys_rst 17>; +- vbus-supply = <&usb0_vbus0>; +- }; +- +- usb0_ssphy1: ss-phy@310 { +- compatible = "socionext,uniphier-pxs2-usb3-ssphy"; +- reg = <0x310 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy"; +- clocks = <&sys_clk 14>, <&sys_clk 18>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 14>, <&sys_rst 18>; +- vbus-supply = <&usb0_vbus1>; +- }; +- }; +- +- usb1: usb@65c00000 { +- compatible = "socionext,uniphier-dwc3", "snps,dwc3"; +- status = "disabled"; +- reg = <0x65c00000 0xcd00>; +- interrupt-names = "host", "peripheral"; +- interrupts = <0 137 4>, <0 138 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; +- clock-names = "ref", "bus_early", "suspend"; +- clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>; +- resets = <&usb1_rst 15>; +- phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>; +- dr_mode = "host"; +- }; +- +- usb-glue@65d00000 { +- compatible = "socionext,uniphier-pxs2-dwc3-glue", +- "simple-mfd"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x65d00000 0x400>; +- +- usb1_rst: reset@0 { +- compatible = "socionext,uniphier-pxs2-usb3-reset"; +- reg = <0x0 0x4>; +- #reset-cells = <1>; +- clock-names = "link"; +- clocks = <&sys_clk 15>; +- reset-names = "link"; +- resets = <&sys_rst 15>; +- }; +- +- usb1_vbus0: regulator@100 { +- compatible = "socionext,uniphier-pxs2-usb3-regulator"; +- reg = <0x100 0x10>; +- clock-names = "link"; +- clocks = <&sys_clk 15>; +- reset-names = "link"; +- resets = <&sys_rst 15>; +- }; +- +- usb1_vbus1: regulator@110 { +- compatible = "socionext,uniphier-pxs2-usb3-regulator"; +- reg = <0x110 0x10>; +- clock-names = "link"; +- clocks = <&sys_clk 15>; +- reset-names = "link"; +- resets = <&sys_rst 15>; +- }; +- +- usb1_hsphy0: hs-phy@200 { +- compatible = "socionext,uniphier-pxs2-usb3-hsphy"; +- reg = <0x200 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy"; +- clocks = <&sys_clk 15>, <&sys_clk 20>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 15>, <&sys_rst 20>; +- vbus-supply = <&usb1_vbus0>; +- }; +- +- usb1_hsphy1: hs-phy@210 { +- compatible = "socionext,uniphier-pxs2-usb3-hsphy"; +- reg = <0x210 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy"; +- clocks = <&sys_clk 15>, <&sys_clk 20>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 15>, <&sys_rst 20>; +- vbus-supply = <&usb1_vbus1>; +- }; +- +- usb1_ssphy0: ss-phy@300 { +- compatible = "socionext,uniphier-pxs2-usb3-ssphy"; +- reg = <0x300 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy"; +- clocks = <&sys_clk 15>, <&sys_clk 21>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 15>, <&sys_rst 21>; +- vbus-supply = <&usb1_vbus0>; +- }; +- }; +- +- nand: nand-controller@68000000 { +- compatible = "socionext,uniphier-denali-nand-v5b"; +- status = "disabled"; +- reg-names = "nand_data", "denali_reg"; +- reg = <0x68000000 0x20>, <0x68100000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 65 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nand>; +- clock-names = "nand", "nand_x", "ecc"; +- clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; +- reset-names = "nand", "reg"; +- resets = <&sys_rst 2>, <&sys_rst 2>; +- }; +- }; +-}; +- +-#include "uniphier-pinctrl.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/uniphier-ref-daughter.dtsi b/scripts/dtc/include-prefixes/arm/uniphier-ref-daughter.dtsi +deleted file mode 100644 +index a11897669c26..000000000000 +--- a/scripts/dtc/include-prefixes/arm/uniphier-ref-daughter.dtsi ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier Reference Daughter Board +-// +-// Copyright (C) 2015-2017 Socionext Inc. +-// Author: Masahiro Yamada +- +-&i2c0 { +- eeprom@50 { +- compatible = "microchip,24lc128", "atmel,24c128"; +- reg = <0x50>; +- pagesize = <64>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/uniphier-sld8-ref.dts b/scripts/dtc/include-prefixes/arm/uniphier-sld8-ref.dts +deleted file mode 100644 +index 6db949ec7411..000000000000 +--- a/scripts/dtc/include-prefixes/arm/uniphier-sld8-ref.dts ++++ /dev/null +@@ -1,92 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier sLD8 Reference Board +-// +-// Copyright (C) 2015-2016 Socionext Inc. +-// Author: Masahiro Yamada +- +-/dts-v1/; +-#include "uniphier-sld8.dtsi" +-#include "uniphier-ref-daughter.dtsi" +-#include "uniphier-support-card.dtsi" +- +-/ { +- model = "UniPhier sLD8 Reference Board"; +- compatible = "socionext,uniphier-sld8-ref", "socionext,uniphier-sld8"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serialsc; +- serial2 = &serial2; +- serial3 = &serial3; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +-}; +- +-ðsc { +- interrupts = <0 8>; +-}; +- +-&serialsc { +- interrupts = <0 8>; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&serial2 { +- status = "okay"; +-}; +- +-&serial3 { +- status = "okay"; +-}; +- +-&gpio { +- xirq0 { +- gpio-hog; +- gpios = ; +- input; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&sd { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&usb2 { +- status = "okay"; +-}; +- +-&nand { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/uniphier-sld8.dtsi b/scripts/dtc/include-prefixes/arm/uniphier-sld8.dtsi +deleted file mode 100644 +index 96a766deb8d1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/uniphier-sld8.dtsi ++++ /dev/null +@@ -1,425 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier sLD8 SoC +-// +-// Copyright (C) 2015-2016 Socionext Inc. +-// Author: Masahiro Yamada +- +-#include +- +-/ { +- compatible = "socionext,uniphier-sld8"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- clocks { +- refclk: ref { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- arm_timer_clk: arm-timer { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- interrupt-parent = <&intc>; +- +- l2: cache-controller@500c0000 { +- compatible = "socionext,uniphier-system-cache"; +- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, +- <0x506c0000 0x400>; +- interrupts = <0 174 4>, <0 175 4>; +- cache-unified; +- cache-size = <(256 * 1024)>; +- cache-sets = <256>; +- cache-line-size = <128>; +- cache-level = <2>; +- }; +- +- spi: spi@54006000 { +- compatible = "socionext,uniphier-scssi"; +- status = "disabled"; +- reg = <0x54006000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 39 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0>; +- clocks = <&peri_clk 11>; +- resets = <&peri_rst 11>; +- }; +- +- serial0: serial@54006800 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006800 0x40>; +- interrupts = <0 33 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- clocks = <&peri_clk 0>; +- resets = <&peri_rst 0>; +- }; +- +- serial1: serial@54006900 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006900 0x40>; +- interrupts = <0 35 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- clocks = <&peri_clk 1>; +- resets = <&peri_rst 1>; +- }; +- +- serial2: serial@54006a00 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006a00 0x40>; +- interrupts = <0 37 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- clocks = <&peri_clk 2>; +- resets = <&peri_rst 2>; +- }; +- +- serial3: serial@54006b00 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006b00 0x40>; +- interrupts = <0 29 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- clocks = <&peri_clk 3>; +- resets = <&peri_rst 3>; +- }; +- +- gpio: gpio@55000000 { +- compatible = "socionext,uniphier-gpio"; +- reg = <0x55000000 0x200>; +- interrupt-parent = <&aidet>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 0 0>, +- <&pinctrl 104 0 0>, +- <&pinctrl 112 0 0>; +- gpio-ranges-group-names = "gpio_range0", +- "gpio_range1", +- "gpio_range2"; +- ngpios = <136>; +- socionext,interrupt-ranges = <0 48 13>, <14 62 2>; +- }; +- +- i2c0: i2c@58400000 { +- compatible = "socionext,uniphier-i2c"; +- status = "disabled"; +- reg = <0x58400000 0x40>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 41 1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0>; +- clocks = <&peri_clk 4>; +- resets = <&peri_rst 4>; +- clock-frequency = <100000>; +- }; +- +- i2c1: i2c@58480000 { +- compatible = "socionext,uniphier-i2c"; +- status = "disabled"; +- reg = <0x58480000 0x40>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 42 1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clocks = <&peri_clk 5>; +- resets = <&peri_rst 5>; +- clock-frequency = <100000>; +- }; +- +- /* chip-internal connection for DMD */ +- i2c2: i2c@58500000 { +- compatible = "socionext,uniphier-i2c"; +- reg = <0x58500000 0x40>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 43 1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clocks = <&peri_clk 6>; +- resets = <&peri_rst 6>; +- clock-frequency = <400000>; +- }; +- +- i2c3: i2c@58580000 { +- compatible = "socionext,uniphier-i2c"; +- status = "disabled"; +- reg = <0x58580000 0x40>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 44 1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- clocks = <&peri_clk 7>; +- resets = <&peri_rst 7>; +- clock-frequency = <100000>; +- }; +- +- system_bus: system-bus@58c00000 { +- compatible = "socionext,uniphier-system-bus"; +- status = "disabled"; +- reg = <0x58c00000 0x400>; +- #address-cells = <2>; +- #size-cells = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_system_bus>; +- }; +- +- smpctrl@59801000 { +- compatible = "socionext,uniphier-smpctrl"; +- reg = <0x59801000 0x400>; +- }; +- +- mioctrl@59810000 { +- compatible = "socionext,uniphier-sld8-mioctrl", +- "simple-mfd", "syscon"; +- reg = <0x59810000 0x800>; +- +- mio_clk: clock { +- compatible = "socionext,uniphier-sld8-mio-clock"; +- #clock-cells = <1>; +- }; +- +- mio_rst: reset { +- compatible = "socionext,uniphier-sld8-mio-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- perictrl@59820000 { +- compatible = "socionext,uniphier-sld8-perictrl", +- "simple-mfd", "syscon"; +- reg = <0x59820000 0x200>; +- +- peri_clk: clock { +- compatible = "socionext,uniphier-sld8-peri-clock"; +- #clock-cells = <1>; +- }; +- +- peri_rst: reset { +- compatible = "socionext,uniphier-sld8-peri-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- dmac: dma-controller@5a000000 { +- compatible = "socionext,uniphier-mio-dmac"; +- reg = <0x5a000000 0x1000>; +- interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, +- <0 71 4>, <0 72 4>, <0 73 4>; +- clocks = <&mio_clk 7>; +- resets = <&mio_rst 7>; +- #dma-cells = <1>; +- }; +- +- sd: mmc@5a400000 { +- compatible = "socionext,uniphier-sd-v2.91"; +- status = "disabled"; +- reg = <0x5a400000 0x200>; +- interrupts = <0 76 4>; +- pinctrl-names = "default", "uhs"; +- pinctrl-0 = <&pinctrl_sd>; +- pinctrl-1 = <&pinctrl_sd_uhs>; +- clocks = <&mio_clk 0>; +- reset-names = "host", "bridge"; +- resets = <&mio_rst 0>, <&mio_rst 3>; +- dma-names = "rx-tx"; +- dmas = <&dmac 4>; +- bus-width = <4>; +- cap-sd-highspeed; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- }; +- +- emmc: mmc@5a500000 { +- compatible = "socionext,uniphier-sd-v2.91"; +- status = "disabled"; +- reg = <0x5a500000 0x200>; +- interrupts = <0 78 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_emmc>; +- clocks = <&mio_clk 1>; +- reset-names = "host", "bridge", "hw"; +- resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; +- dma-names = "rx-tx"; +- dmas = <&dmac 6>; +- bus-width = <8>; +- cap-mmc-highspeed; +- cap-mmc-hw-reset; +- non-removable; +- }; +- +- usb0: usb@5a800100 { +- compatible = "socionext,uniphier-ehci", "generic-ehci"; +- status = "disabled"; +- reg = <0x5a800100 0x100>; +- interrupts = <0 80 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb0>; +- clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, +- <&mio_clk 12>; +- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, +- <&mio_rst 12>; +- has-transaction-translator; +- }; +- +- usb1: usb@5a810100 { +- compatible = "socionext,uniphier-ehci", "generic-ehci"; +- status = "disabled"; +- reg = <0x5a810100 0x100>; +- interrupts = <0 81 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb1>; +- clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, +- <&mio_clk 13>; +- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, +- <&mio_rst 13>; +- has-transaction-translator; +- }; +- +- usb2: usb@5a820100 { +- compatible = "socionext,uniphier-ehci", "generic-ehci"; +- status = "disabled"; +- reg = <0x5a820100 0x100>; +- interrupts = <0 82 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb2>; +- clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, +- <&mio_clk 14>; +- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, +- <&mio_rst 14>; +- has-transaction-translator; +- }; +- +- soc-glue@5f800000 { +- compatible = "socionext,uniphier-sld8-soc-glue", +- "simple-mfd", "syscon"; +- reg = <0x5f800000 0x2000>; +- +- pinctrl: pinctrl { +- compatible = "socionext,uniphier-sld8-pinctrl"; +- }; +- }; +- +- soc-glue@5f900000 { +- compatible = "socionext,uniphier-sld8-soc-glue-debug", +- "simple-mfd"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x5f900000 0x2000>; +- +- efuse@100 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x100 0x28>; +- }; +- +- efuse@200 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x200 0x14>; +- }; +- }; +- +- timer@60000200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0x60000200 0x20>; +- interrupts = <1 11 0x104>; +- clocks = <&arm_timer_clk>; +- }; +- +- timer@60000600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x60000600 0x20>; +- interrupts = <1 13 0x104>; +- clocks = <&arm_timer_clk>; +- }; +- +- intc: interrupt-controller@60001000 { +- compatible = "arm,cortex-a9-gic"; +- reg = <0x60001000 0x1000>, +- <0x60000100 0x100>; +- #interrupt-cells = <3>; +- interrupt-controller; +- }; +- +- aidet: interrupt-controller@61830000 { +- compatible = "socionext,uniphier-sld8-aidet"; +- reg = <0x61830000 0x200>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- sysctrl@61840000 { +- compatible = "socionext,uniphier-sld8-sysctrl", +- "simple-mfd", "syscon"; +- reg = <0x61840000 0x10000>; +- +- sys_clk: clock { +- compatible = "socionext,uniphier-sld8-clock"; +- #clock-cells = <1>; +- }; +- +- sys_rst: reset { +- compatible = "socionext,uniphier-sld8-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- nand: nand-controller@68000000 { +- compatible = "socionext,uniphier-denali-nand-v5a"; +- status = "disabled"; +- reg-names = "nand_data", "denali_reg"; +- reg = <0x68000000 0x20>, <0x68100000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 65 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nand>; +- clock-names = "nand", "nand_x", "ecc"; +- clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; +- reset-names = "nand", "reg"; +- resets = <&sys_rst 2>, <&sys_rst 2>; +- }; +- }; +-}; +- +-#include "uniphier-pinctrl.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm/uniphier-support-card.dtsi b/scripts/dtc/include-prefixes/arm/uniphier-support-card.dtsi +deleted file mode 100644 +index 444802fee9fb..000000000000 +--- a/scripts/dtc/include-prefixes/arm/uniphier-support-card.dtsi ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier Support Card (Expansion Board) +-// +-// Copyright (C) 2015-2017 Socionext Inc. +-// Author: Masahiro Yamada +- +-&system_bus { +- status = "okay"; +- ranges = <1 0x00000000 0x42000000 0x02000000>; +- interrupt-parent = <&gpio>; +- +- ethsc: ethernet@1,1f00000 { +- compatible = "smsc,lan9118", "smsc,lan9115"; +- reg = <1 0x01f00000 0x1000>; +- phy-mode = "mii"; +- reg-io-width = <4>; +- }; +- +- serialsc: serial@1,1fb0000 { +- compatible = "ns16550a"; +- reg = <1 0x01fb0000 0x20>; +- clock-frequency = <12288000>; +- reg-shift = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/usb_a9260.dts b/scripts/dtc/include-prefixes/arm/usb_a9260.dts +deleted file mode 100644 +index 6cfa83921ac2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/usb_a9260.dts ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * usb_a9260.dts - Device Tree file for Caloa USB A9260 board +- * +- * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +-/dts-v1/; +-#include "at91sam9260.dtsi" +-#include "usb_a9260_common.dtsi" +- +-/ { +- model = "Calao USB A9260"; +- compatible = "calao,usb-a9260", "atmel,at91sam9260", "atmel,at91sam9"; +- +- chosen { +- bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +- +- ahb { +- apb { +- shdwc@fffffd10 { +- atmel,wakeup-counter = <10>; +- atmel,wakeup-rtt-timer; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/usb_a9260_common.dtsi b/scripts/dtc/include-prefixes/arm/usb_a9260_common.dtsi +deleted file mode 100644 +index 8744b5f6f792..000000000000 +--- a/scripts/dtc/include-prefixes/arm/usb_a9260_common.dtsi ++++ /dev/null +@@ -1,146 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * usb_a926x.dts - Device Tree file for Caloa USB A926x board +- * +- * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +- +-/ { +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- ahb { +- apb { +- dbgu: serial@fffff200 { +- status = "okay"; +- }; +- +- tcb0: timer@fffa0000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +- }; +- +- macb0: ethernet@fffc4000 { +- phy-mode = "rmii"; +- status = "okay"; +- }; +- +- usb1: gadget@fffa4000 { +- atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- }; +- +- ebi: ebi@10000000 { +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; +- pinctrl-names = "default"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "soft"; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x20000>; +- }; +- +- barebox@20000 { +- label = "barebox"; +- reg = <0x20000 0x40000>; +- }; +- +- bareboxenv@60000 { +- label = "bareboxenv"; +- reg = <0x60000 0x20000>; +- }; +- +- bareboxenv2@80000 { +- label = "bareboxenv2"; +- reg = <0x80000 0x20000>; +- }; +- +- oftree@80000 { +- label = "oftree"; +- reg = <0xa0000 0x20000>; +- }; +- +- kernel@a0000 { +- label = "kernel"; +- reg = <0xc0000 0x400000>; +- }; +- +- rootfs@4a0000 { +- label = "rootfs"; +- reg = <0x4c0000 0x7800000>; +- }; +- +- data@7ca0000 { +- label = "data"; +- reg = <0x7cc0000 0x8340000>; +- }; +- }; +- }; +- }; +- }; +- +- usb0: ohci@500000 { +- num-ports = <2>; +- status = "okay"; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- user_led { +- label = "user_led"; +- gpios = <&pioB 21 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- user_pb { +- label = "user_pb"; +- gpios = <&pioB 10 GPIO_ACTIVE_LOW>; +- linux,code = <28>; +- wakeup-source; +- }; +- }; +- +- i2c-gpio-0 { +- status = "okay"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/usb_a9263.dts b/scripts/dtc/include-prefixes/arm/usb_a9263.dts +deleted file mode 100644 +index 8a0cfbfd0c45..000000000000 +--- a/scripts/dtc/include-prefixes/arm/usb_a9263.dts ++++ /dev/null +@@ -1,174 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * usb_a9263.dts - Device Tree file for Caloa USB A9293 board +- * +- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD +- */ +-/dts-v1/; +-#include "at91sam9263.dtsi" +- +-/ { +- model = "Calao USB A9263"; +- compatible = "atmel,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9"; +- +- chosen { +- bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +- +- clocks { +- slow_xtal { +- clock-frequency = <32768>; +- }; +- +- main_xtal { +- clock-frequency = <12000000>; +- }; +- }; +- +- ahb { +- apb { +- dbgu: serial@ffffee00 { +- status = "okay"; +- }; +- +- tcb0: timer@fff7c000 { +- timer@0 { +- compatible = "atmel,tcb-timer"; +- reg = <0>, <1>; +- }; +- +- timer@2 { +- compatible = "atmel,tcb-timer"; +- reg = <2>; +- }; +- }; +- +- macb0: ethernet@fffbc000 { +- phy-mode = "rmii"; +- status = "okay"; +- }; +- +- usb1: gadget@fff78000 { +- atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- spi0: spi@fffa4000 { +- cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- mtd_dataflash@0 { +- compatible = "atmel,at45", "atmel,dataflash"; +- reg = <0>; +- spi-max-frequency = <15000000>; +- }; +- }; +- +- shdwc@fffffd10 { +- atmel,wakeup-counter = <10>; +- atmel,wakeup-rtt-timer; +- }; +- }; +- +- ebi0: ebi@10000000 { +- status = "okay"; +- +- nand_controller: nand-controller { +- status = "okay"; +- pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; +- pinctrl-names = "default"; +- +- nand@3 { +- reg = <0x3 0x0 0x800000>; +- rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; +- nand-bus-width = <8>; +- nand-ecc-mode = "soft"; +- nand-on-flash-bbt; +- label = "atmel_nand"; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x20000>; +- }; +- +- barebox@20000 { +- label = "barebox"; +- reg = <0x20000 0x40000>; +- }; +- +- bareboxenv@60000 { +- label = "bareboxenv"; +- reg = <0x60000 0x20000>; +- }; +- +- bareboxenv2@80000 { +- label = "bareboxenv2"; +- reg = <0x80000 0x20000>; +- }; +- +- oftree@80000 { +- label = "oftree"; +- reg = <0xa0000 0x20000>; +- }; +- +- kernel@a0000 { +- label = "kernel"; +- reg = <0xc0000 0x400000>; +- }; +- +- rootfs@4a0000 { +- label = "rootfs"; +- reg = <0x4c0000 0x7800000>; +- }; +- +- data@7ca0000 { +- label = "data"; +- reg = <0x7cc0000 0x8340000>; +- }; +- }; +- }; +- }; +- }; +- +- usb0: ohci@a00000 { +- num-ports = <2>; +- status = "okay"; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- user_led { +- label = "user_led"; +- gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- user_pb { +- label = "user_pb"; +- gpios = <&pioB 10 GPIO_ACTIVE_LOW>; +- linux,code = <28>; +- wakeup-source; +- }; +- }; +- +- i2c-gpio-0 { +- status = "okay"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/usb_a9g20-dab-mmx.dtsi b/scripts/dtc/include-prefixes/arm/usb_a9g20-dab-mmx.dtsi +deleted file mode 100644 +index 08d58081201a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/usb_a9g20-dab-mmx.dtsi ++++ /dev/null +@@ -1,95 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * calao-dab-mmx.dtsi - Device Tree Include file for Calao DAB-MMX Daughter Board +- * +- * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD +- */ +- +-/ { +- ahb { +- apb { +- usart1: serial@fffb4000 { +- status = "okay"; +- }; +- +- usart3: serial@fffd0000 { +- status = "okay"; +- }; +- }; +- }; +- +- i2c-gpio@0 { +- status = "okay"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- user_led1 { +- label = "user_led1"; +- gpios = <&pioB 20 GPIO_ACTIVE_LOW>; +- }; +- +-/* +-* led already used by mother board but active as high +-* user_led2 { +-* label = "user_led2"; +-* gpios = <&pioB 21 GPIO_ACTIVE_LOW>; +-* }; +-*/ +- user_led3 { +- label = "user_led3"; +- gpios = <&pioB 22 GPIO_ACTIVE_LOW>; +- }; +- +- user_led4 { +- label = "user_led4"; +- gpios = <&pioB 23 GPIO_ACTIVE_LOW>; +- }; +- +- red { +- label = "red"; +- gpios = <&pioB 24 GPIO_ACTIVE_LOW>; +- }; +- +- orange { +- label = "orange"; +- gpios = <&pioB 30 GPIO_ACTIVE_LOW>; +- }; +- +- green { +- label = "green"; +- gpios = <&pioB 31 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- user_pb1 { +- label = "user_pb1"; +- gpios = <&pioB 25 GPIO_ACTIVE_LOW>; +- linux,code = <0x100>; +- }; +- +- user_pb2 { +- label = "user_pb2"; +- gpios = <&pioB 13 GPIO_ACTIVE_LOW>; +- linux,code = <0x101>; +- }; +- +- user_pb3 { +- label = "user_pb3"; +- gpios = <&pioA 26 GPIO_ACTIVE_LOW>; +- linux,code = <0x102>; +- }; +- +- user_pb4 { +- label = "user_pb4"; +- gpios = <&pioC 9 GPIO_ACTIVE_LOW>; +- linux,code = <0x103>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/usb_a9g20.dts b/scripts/dtc/include-prefixes/arm/usb_a9g20.dts +deleted file mode 100644 +index 2f667b083e81..000000000000 +--- a/scripts/dtc/include-prefixes/arm/usb_a9g20.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board +- * +- * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD +- */ +-/dts-v1/; +-#include "usb_a9g20_common.dtsi" +- +-/ { +- model = "Calao USB A9G20"; +- compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/usb_a9g20_common.dtsi b/scripts/dtc/include-prefixes/arm/usb_a9g20_common.dtsi +deleted file mode 100644 +index 7d10b36db1ee..000000000000 +--- a/scripts/dtc/include-prefixes/arm/usb_a9g20_common.dtsi ++++ /dev/null +@@ -1,27 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board +- * +- * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD +- */ +- +-#include "at91sam9g20.dtsi" +-#include "usb_a9260_common.dtsi" +- +-/ { +- chosen { +- bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@20000000 { +- reg = <0x20000000 0x4000000>; +- }; +- +- i2c-gpio-0 { +- rtc@56 { +- compatible = "microcrystal,rv3029"; +- reg = <0x56>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/usb_a9g20_lpw.dts b/scripts/dtc/include-prefixes/arm/usb_a9g20_lpw.dts +deleted file mode 100644 +index f65712015d40..000000000000 +--- a/scripts/dtc/include-prefixes/arm/usb_a9g20_lpw.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * usb_a9g20_lpw.dts - Device Tree file for Caloa USB A9G20 Low Power board +- * +- * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD +- */ +-/dts-v1/; +-#include "usb_a9g20_common.dtsi" +- +-/ { +- model = "Calao USB A9G20 Low Power"; +- compatible = "calao,usb-a9g20-lpw", "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; +- +- ahb { +- apb { +- spi1: spi@fffcc000 { +- cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- mmc-slot@0 { +- compatible = "mmc-spi-slot"; +- reg = <0>; +- voltage-ranges = <3200 3400>; +- spi-max-frequency = <25000000>; +- interrupt-parent = <&pioC>; +- interrupts = <4 IRQ_TYPE_EDGE_BOTH>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/versatile-ab-ib2.dts b/scripts/dtc/include-prefixes/arm/versatile-ab-ib2.dts +deleted file mode 100644 +index c577ff4bb4be..000000000000 +--- a/scripts/dtc/include-prefixes/arm/versatile-ab-ib2.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * The Versatile AB with the IB2 expansion board mounted. +- * This works as a superset of the Versatile AB. +- */ +- +-#include "versatile-ab.dts" +- +-/ { +- model = "ARM Versatile AB + IB2 board"; +- +- /* Special IB2 control register */ +- syscon@27000000 { +- compatible = "arm,versatile-ib2-syscon", "syscon", "simple-mfd"; +- reg = <0x27000000 0x4>; +- +- led@00.4 { +- compatible = "register-bit-led"; +- offset = <0x00>; +- mask = <0x10>; +- label = "versatile-ib2:0"; +- linux,default-trigger = "heartbeat"; +- default-state = "on"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/versatile-ab.dts b/scripts/dtc/include-prefixes/arm/versatile-ab.dts +deleted file mode 100644 +index 151c0220047d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/versatile-ab.dts ++++ /dev/null +@@ -1,439 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-/ { +- model = "ARM Versatile AB"; +- compatible = "arm,versatile-ab"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&vic>; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- i2c0 = &i2c0; +- }; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x08000000>; +- }; +- +- xtal24mhz: xtal24mhz@24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- bridge { +- compatible = "ti,ths8134b", "ti,ths8134"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- vga_bridge_in: endpoint { +- remote-endpoint = <&clcd_pads_vga_dac>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- vga_bridge_out: endpoint { +- remote-endpoint = <&vga_con_in>; +- }; +- }; +- }; +- }; +- +- vga { +- compatible = "vga-connector"; +- +- port { +- vga_con_in: endpoint { +- remote-endpoint = <&vga_bridge_out>; +- }; +- }; +- }; +- +- core-module@10000000 { +- compatible = "arm,core-module-versatile", "syscon", "simple-mfd"; +- reg = <0x10000000 0x200>; +- +- led@08.0 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x01>; +- label = "versatile:0"; +- linux,default-trigger = "heartbeat"; +- default-state = "on"; +- }; +- led@08.1 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x02>; +- label = "versatile:1"; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- led@08.2 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x04>; +- label = "versatile:2"; +- linux,default-trigger = "cpu0"; +- default-state = "off"; +- }; +- led@08.3 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x08>; +- label = "versatile:3"; +- default-state = "off"; +- }; +- led@08.4 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x10>; +- label = "versatile:4"; +- default-state = "off"; +- }; +- led@08.5 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x20>; +- label = "versatile:5"; +- default-state = "off"; +- }; +- led@08.6 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x40>; +- label = "versatile:6"; +- default-state = "off"; +- }; +- led@08.7 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x80>; +- label = "versatile:7"; +- default-state = "off"; +- }; +- +- /* OSC1 on AB, OSC4 on PB */ +- osc1: cm_aux_osc@24M { +- #clock-cells = <0>; +- compatible = "arm,versatile-cm-auxosc"; +- clocks = <&xtal24mhz>; +- }; +- +- /* The timer clock is the 24 MHz oscillator divided to 1MHz */ +- timclk: timclk@1M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <24>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- +- pclk: pclk@24M { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <1>; +- clock-mult = <1>; +- clocks = <&xtal24mhz>; +- }; +- }; +- +- flash@34000000 { +- /* 64 MiB NOR flash in non-interleaved chips */ +- compatible = "arm,versatile-flash", "cfi-flash"; +- reg = <0x34000000 0x04000000>; +- bank-width = <4>; +- partitions { +- compatible = "arm,arm-firmware-suite"; +- }; +- }; +- +- i2c0: i2c@10002000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "arm,versatile-i2c"; +- reg = <0x10002000 0x1000>; +- +- rtc@68 { +- compatible = "dallas,ds1338"; +- reg = <0x68>; +- }; +- }; +- +- net@10010000 { +- compatible = "smsc,lan91c111"; +- reg = <0x10010000 0x10000>; +- interrupts = <25>; +- }; +- +- lcd@10008000 { +- compatible = "arm,versatile-lcd"; +- reg = <0x10008000 0x1000>; +- }; +- +- amba { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- vic: interrupt-controller@10140000 { +- compatible = "arm,versatile-vic"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x10140000 0x1000>; +- valid-mask = <0xffffffff>; +- }; +- +- sic: interrupt-controller@10003000 { +- compatible = "arm,versatile-sic"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0x10003000 0x1000>; +- interrupt-parent = <&vic>; +- interrupts = <31>; /* Cascaded to vic */ +- clear-mask = <0xffffffff>; +- /* +- * Valid interrupt lines mask according to +- * table 4-36 page 4-50 of ARM DUI 0225D +- */ +- valid-mask = <0x0760031b>; +- }; +- +- dma@10130000 { +- compatible = "arm,pl081", "arm,primecell"; +- reg = <0x10130000 0x1000>; +- interrupts = <17>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- uart0: uart@101f1000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x101f1000 0x1000>; +- interrupts = <12>; +- clocks = <&xtal24mhz>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- uart1: uart@101f2000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x101f2000 0x1000>; +- interrupts = <13>; +- clocks = <&xtal24mhz>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- uart2: uart@101f3000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x101f3000 0x1000>; +- interrupts = <14>; +- clocks = <&xtal24mhz>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- smc@10100000 { +- compatible = "arm,primecell"; +- reg = <0x10100000 0x1000>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- mpmc@10110000 { +- compatible = "arm,primecell"; +- reg = <0x10110000 0x1000>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- display@10120000 { +- compatible = "arm,pl110", "arm,primecell"; +- reg = <0x10120000 0x1000>; +- interrupts = <16>; +- clocks = <&osc1>, <&pclk>; +- clock-names = "clcdclk", "apb_pclk"; +- /* 800x600 16bpp @ 36MHz works fine */ +- max-memory-bandwidth = <54000000>; +- +- /* +- * This port is routed through a PLD (Programmable +- * Logic Device) that routes the output from the CLCD +- * (after transformations) to the VGA DAC and also an +- * external panel connector. The PLD is essential for +- * supporting RGB565/BGR565. +- * +- * The signals from the port thus reaches two endpoints. +- * The PLD is managed through a few special bits in the +- * FPGA "sysreg". +- * +- * This arrangement can be clearly seen in +- * ARM DUI 0225D, page 3-41, figure 3-19. +- */ +- port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- clcd_pads_panel: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_in>; +- arm,pl11x,tft-r0g0b0-pads = <0 8 16>; +- }; +- clcd_pads_vga_dac: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vga_bridge_in>; +- arm,pl11x,tft-r0g0b0-pads = <0 8 16>; +- }; +- }; +- }; +- +- sctl@101e0000 { +- compatible = "arm,primecell"; +- reg = <0x101e0000 0x1000>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- watchdog@101e1000 { +- compatible = "arm,primecell"; +- reg = <0x101e1000 0x1000>; +- interrupts = <0>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- timer@101e2000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x101e2000 0x1000>; +- interrupts = <4>; +- clocks = <&timclk>, <&timclk>, <&pclk>; +- clock-names = "timer0", "timer1", "apb_pclk"; +- }; +- +- timer@101e3000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x101e3000 0x1000>; +- interrupts = <5>; +- clocks = <&timclk>, <&timclk>, <&pclk>; +- clock-names = "timer0", "timer1", "apb_pclk"; +- }; +- +- gpio0: gpio@101e4000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x101e4000 0x1000>; +- gpio-controller; +- interrupts = <6>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- gpio1: gpio@101e5000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x101e5000 0x1000>; +- interrupts = <7>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- rtc@101e8000 { +- compatible = "arm,pl030", "arm,primecell"; +- reg = <0x101e8000 0x1000>; +- interrupts = <10>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- sci@101f0000 { +- compatible = "arm,primecell"; +- reg = <0x101f0000 0x1000>; +- interrupts = <15>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- spi@101f4000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x101f4000 0x1000>; +- interrupts = <11>; +- clocks = <&xtal24mhz>, <&pclk>; +- clock-names = "SSPCLK", "apb_pclk"; +- }; +- +- fpga { +- compatible = "arm,versatile-fpga", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x10000000 0x10000>; +- +- sysreg@0 { +- compatible = "arm,versatile-sysreg", "syscon", "simple-mfd"; +- reg = <0x00000 0x1000>; +- +- panel: display@0 { +- compatible = "arm,versatile-tft-panel"; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&clcd_pads_panel>; +- }; +- }; +- }; +- }; +- +- aaci@4000 { +- compatible = "arm,primecell"; +- reg = <0x4000 0x1000>; +- interrupts = <24>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- mmc@5000 { +- compatible = "arm,pl180", "arm,primecell"; +- reg = <0x5000 0x1000>; +- interrupts-extended = <&vic 22 &sic 1>; +- clocks = <&xtal24mhz>, <&pclk>; +- clock-names = "mclk", "apb_pclk"; +- }; +- kmi@6000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x6000 0x1000>; +- interrupt-parent = <&sic>; +- interrupts = <3>; +- clocks = <&xtal24mhz>, <&pclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- kmi@7000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x7000 0x1000>; +- interrupt-parent = <&sic>; +- interrupts = <4>; +- clocks = <&xtal24mhz>, <&pclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/versatile-pb.dts b/scripts/dtc/include-prefixes/arm/versatile-pb.dts +deleted file mode 100644 +index e7e751a858d8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/versatile-pb.dts ++++ /dev/null +@@ -1,114 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "versatile-ab.dts" +- +-/ { +- model = "ARM Versatile PB"; +- compatible = "arm,versatile-pb"; +- +- amba { +- /* The Versatile PB is using more SIC IRQ lines than the AB */ +- sic: interrupt-controller@10003000 { +- clear-mask = <0xffffffff>; +- /* +- * Valid interrupt lines mask according to +- * figure 3-30 page 3-74 of ARM DUI 0224B +- */ +- valid-mask = <0x7fe003ff>; +- }; +- +- gpio2: gpio@101e6000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x101e6000 0x1000>; +- interrupts = <8>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- gpio3: gpio@101e7000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x101e7000 0x1000>; +- interrupts = <9>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&pclk>; +- clock-names = "apb_pclk"; +- }; +- +- pci@10001000 { +- compatible = "arm,versatile-pci"; +- device_type = "pci"; +- reg = <0x10001000 0x1000 +- 0x41000000 0x10000 +- 0x42000000 0x100000>; +- bus-range = <0 0xff>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- +- ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */ +- 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */ +- 0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */ +- +- interrupt-map-mask = <0x1800 0 0 7>; +- interrupt-map = <0x1800 0 0 1 &sic 28 +- 0x1800 0 0 2 &sic 29 +- 0x1800 0 0 3 &sic 30 +- 0x1800 0 0 4 &sic 27 +- +- 0x1000 0 0 1 &sic 27 +- 0x1000 0 0 2 &sic 28 +- 0x1000 0 0 3 &sic 29 +- 0x1000 0 0 4 &sic 30 +- +- 0x0800 0 0 1 &sic 30 +- 0x0800 0 0 2 &sic 27 +- 0x0800 0 0 3 &sic 28 +- 0x0800 0 0 4 &sic 29 +- +- 0x0000 0 0 1 &sic 29 +- 0x0000 0 0 2 &sic 30 +- 0x0000 0 0 3 &sic 27 +- 0x0000 0 0 4 &sic 28>; +- }; +- +- fpga { +- mmc@5000 { +- /* +- * Overrides the interrupt assignment from +- * the Versatile AB board file. +- */ +- interrupts-extended = <&sic 22 &sic 23>; +- }; +- uart@9000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x9000 0x1000>; +- interrupt-parent = <&sic>; +- interrupts = <6>; +- clocks = <&xtal24mhz>, <&pclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- sci@a000 { +- compatible = "arm,primecell"; +- reg = <0xa000 0x1000>; +- interrupt-parent = <&sic>; +- interrupts = <5>; +- clocks = <&xtal24mhz>; +- clock-names = "apb_pclk"; +- }; +- mmc@b000 { +- compatible = "arm,pl180", "arm,primecell"; +- reg = <0xb000 0x1000>; +- interrupt-parent = <&sic>; +- interrupts = <1>, <2>; +- clocks = <&xtal24mhz>, <&pclk>; +- clock-names = "mclk", "apb_pclk"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vexpress-v2m-rs1.dtsi b/scripts/dtc/include-prefixes/arm/vexpress-v2m-rs1.dtsi +deleted file mode 100644 +index 8af4b77fe655..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vexpress-v2m-rs1.dtsi ++++ /dev/null +@@ -1,494 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * ARM Ltd. Versatile Express +- * +- * Motherboard Express uATX +- * V2M-P1 +- * +- * HBI-0190D +- * +- * RS1 memory map ("ARM Cortex-A Series memory map" in the board's +- * Technical Reference Manual) +- * +- * WARNING! The hardware described in this file is independent from the +- * original variant (vexpress-v2m.dtsi), but there is a strong +- * correspondence between the two configurations. +- * +- * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT +- * CHANGES TO vexpress-v2m.dtsi! +- */ +-#include +- +-/ { +- v2m_fixed_3v3: fixed-regulator-0 { +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- v2m_clk24mhz: clk24mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "v2m:clk24mhz"; +- }; +- +- v2m_refclk1mhz: refclk1mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <1000000>; +- clock-output-names = "v2m:refclk1mhz"; +- }; +- +- v2m_refclk32khz: refclk32khz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "v2m:refclk32khz"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-1 { +- label = "v2m:green:user1"; +- gpios = <&v2m_led_gpios 0 0>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-2 { +- label = "v2m:green:user2"; +- gpios = <&v2m_led_gpios 1 0>; +- linux,default-trigger = "disk-activity"; +- }; +- +- led-3 { +- label = "v2m:green:user3"; +- gpios = <&v2m_led_gpios 2 0>; +- linux,default-trigger = "cpu0"; +- }; +- +- led-4 { +- label = "v2m:green:user4"; +- gpios = <&v2m_led_gpios 3 0>; +- linux,default-trigger = "cpu1"; +- }; +- +- led-5 { +- label = "v2m:green:user5"; +- gpios = <&v2m_led_gpios 4 0>; +- linux,default-trigger = "cpu2"; +- }; +- +- led-6 { +- label = "v2m:green:user6"; +- gpios = <&v2m_led_gpios 5 0>; +- linux,default-trigger = "cpu3"; +- }; +- +- led-7 { +- label = "v2m:green:user7"; +- gpios = <&v2m_led_gpios 6 0>; +- linux,default-trigger = "cpu4"; +- }; +- +- led-8 { +- label = "v2m:green:user8"; +- gpios = <&v2m_led_gpios 7 0>; +- linux,default-trigger = "cpu5"; +- }; +- }; +- +- bus@8000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 63>; +- interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, +- <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, +- <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, +- <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, +- <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, +- <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, +- <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, +- <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, +- <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, +- <0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, +- <0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, +- <0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, +- <0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, +- <0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, +- <0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, +- <0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, +- <0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, +- <0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, +- <0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, +- <0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, +- <0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, +- <0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, +- <0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, +- <0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, +- <0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, +- <0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, +- <0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, +- <0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, +- <0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, +- <0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, +- <0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, +- <0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, +- <0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, +- <0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, +- <0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, +- <0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, +- <0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, +- <0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, +- <0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, +- <0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, +- <0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, +- <0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, +- <0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; +- +- motherboard-bus@8000000 { +- arm,hbi = <0x190>; +- arm,vexpress,site = <0>; +- compatible = "arm,vexpress,v2m-p1", "simple-bus"; +- #address-cells = <2>; /* SMB chipselect number and offset */ +- #size-cells = <1>; +- ranges = <0 0 0x08000000 0x04000000>, +- <1 0 0x14000000 0x04000000>, +- <2 0 0x18000000 0x04000000>, +- <3 0 0x1c000000 0x04000000>, +- <4 0 0x0c000000 0x04000000>, +- <5 0 0x10000000 0x04000000>; +- +- nor_flash: flash@0 { +- compatible = "arm,vexpress-flash", "cfi-flash"; +- reg = <0 0x00000000 0x04000000>, +- <4 0x00000000 0x04000000>; +- bank-width = <4>; +- partitions { +- compatible = "arm,arm-firmware-suite"; +- }; +- }; +- +- psram@100000000 { +- compatible = "arm,vexpress-psram", "mtd-ram"; +- reg = <1 0x00000000 0x02000000>; +- bank-width = <4>; +- }; +- +- ethernet@202000000 { +- compatible = "smsc,lan9118", "smsc,lan9115"; +- reg = <2 0x02000000 0x10000>; +- interrupts = <15>; +- phy-mode = "mii"; +- reg-io-width = <4>; +- smsc,irq-active-high; +- smsc,irq-push-pull; +- vdd33a-supply = <&v2m_fixed_3v3>; +- vddvario-supply = <&v2m_fixed_3v3>; +- }; +- +- usb@203000000 { +- compatible = "nxp,usb-isp1761"; +- reg = <2 0x03000000 0x20000>; +- interrupts = <16>; +- dr_mode = "peripheral"; +- }; +- +- iofpga-bus@300000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 3 0 0x200000>; +- +- v2m_sysreg: sysreg@10000 { +- compatible = "arm,vexpress-sysreg"; +- reg = <0x010000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x10000 0x1000>; +- +- v2m_led_gpios: gpio@8 { +- compatible = "arm,vexpress-sysreg,sys_led"; +- reg = <0x008 4>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- v2m_mmc_gpios: gpio@48 { +- compatible = "arm,vexpress-sysreg,sys_mci"; +- reg = <0x048 4>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- v2m_flash_gpios: gpio@4c { +- compatible = "arm,vexpress-sysreg,sys_flash"; +- reg = <0x04c 4>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +- +- v2m_sysctl: sysctl@20000 { +- compatible = "arm,sp810", "arm,primecell"; +- reg = <0x020000 0x1000>; +- clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; +- clock-names = "refclk", "timclk", "apb_pclk"; +- #clock-cells = <1>; +- clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; +- assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; +- assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; +- }; +- +- /* PCI-E I2C bus */ +- v2m_i2c_pcie: i2c@30000 { +- compatible = "arm,versatile-i2c"; +- reg = <0x030000 0x1000>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- pcie-switch@60 { +- compatible = "idt,89hpes32h8"; +- reg = <0x60>; +- }; +- }; +- +- aaci@40000 { +- compatible = "arm,pl041", "arm,primecell"; +- reg = <0x040000 0x1000>; +- interrupts = <11>; +- clocks = <&smbclk>; +- clock-names = "apb_pclk"; +- }; +- +- mmc@50000 { +- compatible = "arm,pl180", "arm,primecell"; +- reg = <0x050000 0x1000>; +- interrupts = <9>, <10>; +- cd-gpios = <&v2m_mmc_gpios 0 0>; +- wp-gpios = <&v2m_mmc_gpios 1 0>; +- max-frequency = <12000000>; +- vmmc-supply = <&v2m_fixed_3v3>; +- clocks = <&v2m_clk24mhz>, <&smbclk>; +- clock-names = "mclk", "apb_pclk"; +- }; +- +- kmi@60000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x060000 0x1000>; +- interrupts = <12>; +- clocks = <&v2m_clk24mhz>, <&smbclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- kmi@70000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x070000 0x1000>; +- interrupts = <13>; +- clocks = <&v2m_clk24mhz>, <&smbclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- v2m_serial0: serial@90000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x090000 0x1000>; +- interrupts = <5>; +- clocks = <&v2m_oscclk2>, <&smbclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- v2m_serial1: serial@a0000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0a0000 0x1000>; +- interrupts = <6>; +- clocks = <&v2m_oscclk2>, <&smbclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- v2m_serial2: serial@b0000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0b0000 0x1000>; +- interrupts = <7>; +- clocks = <&v2m_oscclk2>, <&smbclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- v2m_serial3: serial@c0000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0c0000 0x1000>; +- interrupts = <8>; +- clocks = <&v2m_oscclk2>, <&smbclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- watchdog@f0000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0f0000 0x1000>; +- interrupts = <0>; +- clocks = <&v2m_refclk32khz>, <&smbclk>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- v2m_timer01: timer@110000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x110000 0x1000>; +- interrupts = <2>; +- clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; +- clock-names = "timclken1", "timclken2", "apb_pclk"; +- }; +- +- v2m_timer23: timer@120000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x120000 0x1000>; +- interrupts = <3>; +- clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; +- clock-names = "timclken1", "timclken2", "apb_pclk"; +- }; +- +- /* DVI I2C bus */ +- v2m_i2c_dvi: i2c@160000 { +- compatible = "arm,versatile-i2c"; +- reg = <0x160000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- dvi-transmitter@39 { +- compatible = "sil,sii9022-tpi", "sil,sii9022"; +- reg = <0x39>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dvi_bridge_in: endpoint { +- remote-endpoint = <&clcd_pads>; +- }; +- }; +- }; +- }; +- +- dvi-transmitter@60 { +- compatible = "sil,sii9022-cpi", "sil,sii9022"; +- reg = <0x60>; +- }; +- }; +- +- rtc@170000 { +- compatible = "arm,pl031", "arm,primecell"; +- reg = <0x170000 0x1000>; +- interrupts = <4>; +- clocks = <&smbclk>; +- clock-names = "apb_pclk"; +- }; +- +- compact-flash@1a0000 { +- compatible = "arm,vexpress-cf", "ata-generic"; +- reg = <0x1a0000 0x100 +- 0x1a0100 0xf00>; +- reg-shift = <2>; +- }; +- +- clcd@1f0000 { +- compatible = "arm,pl111", "arm,primecell"; +- reg = <0x1f0000 0x1000>; +- interrupt-names = "combined"; +- interrupts = <14>; +- clocks = <&v2m_oscclk1>, <&smbclk>; +- clock-names = "clcdclk", "apb_pclk"; +- /* 800x600 16bpp @36MHz works fine */ +- max-memory-bandwidth = <54000000>; +- memory-region = <&vram>; +- +- port { +- clcd_pads: endpoint { +- remote-endpoint = <&dvi_bridge_in>; +- arm,pl11x,tft-r0g0b0-pads = <0 8 16>; +- }; +- }; +- }; +- +- mcc { +- compatible = "arm,vexpress,config-bus"; +- arm,vexpress,config-bridge = <&v2m_sysreg>; +- +- oscclk0 { +- /* MCC static memory clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 0>; +- freq-range = <25000000 60000000>; +- #clock-cells = <0>; +- clock-output-names = "v2m:oscclk0"; +- }; +- +- v2m_oscclk1: oscclk1 { +- /* CLCD clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 1>; +- freq-range = <23750000 65000000>; +- #clock-cells = <0>; +- clock-output-names = "v2m:oscclk1"; +- }; +- +- v2m_oscclk2: oscclk2 { +- /* IO FPGA peripheral clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 2>; +- freq-range = <24000000 24000000>; +- #clock-cells = <0>; +- clock-output-names = "v2m:oscclk2"; +- }; +- +- volt-vio { +- /* Logic level voltage */ +- compatible = "arm,vexpress-volt"; +- arm,vexpress-sysreg,func = <2 0>; +- regulator-name = "VIO"; +- regulator-always-on; +- label = "VIO"; +- }; +- +- temp-mcc { +- /* MCC internal operating temperature */ +- compatible = "arm,vexpress-temp"; +- arm,vexpress-sysreg,func = <4 0>; +- label = "MCC"; +- }; +- +- reset { +- compatible = "arm,vexpress-reset"; +- arm,vexpress-sysreg,func = <5 0>; +- }; +- +- muxfpga { +- compatible = "arm,vexpress-muxfpga"; +- arm,vexpress-sysreg,func = <7 0>; +- }; +- +- shutdown { +- compatible = "arm,vexpress-shutdown"; +- arm,vexpress-sysreg,func = <8 0>; +- }; +- +- reboot { +- compatible = "arm,vexpress-reboot"; +- arm,vexpress-sysreg,func = <9 0>; +- }; +- +- dvimode { +- compatible = "arm,vexpress-dvimode"; +- arm,vexpress-sysreg,func = <11 0>; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vexpress-v2m.dtsi b/scripts/dtc/include-prefixes/arm/vexpress-v2m.dtsi +deleted file mode 100644 +index f434fe5cf4a1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vexpress-v2m.dtsi ++++ /dev/null +@@ -1,509 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * ARM Ltd. Versatile Express +- * +- * Motherboard Express uATX +- * V2M-P1 +- * +- * HBI-0190D +- * +- * Original memory map ("Legacy memory map" in the board's +- * Technical Reference Manual) +- * +- * WARNING! The hardware described in this file is independent from the +- * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong +- * correspondence between the two configurations. +- * +- * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT +- * CHANGES TO vexpress-v2m-rs1.dtsi! +- */ +-#include +- +-/ { +- bus@40000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x40000000 0x40000000 0x10000000>, +- <0x10000000 0x10000000 0x00020000>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 63>; +- interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, +- <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, +- <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, +- <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, +- <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, +- <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, +- <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, +- <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, +- <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, +- <0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, +- <0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, +- <0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, +- <0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, +- <0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, +- <0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, +- <0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, +- <0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, +- <0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, +- <0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, +- <0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, +- <0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, +- <0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, +- <0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, +- <0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, +- <0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, +- <0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, +- <0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, +- <0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, +- <0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, +- <0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, +- <0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, +- <0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, +- <0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, +- <0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, +- <0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, +- <0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, +- <0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, +- <0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, +- <0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, +- <0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, +- <0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, +- <0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, +- <0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; +- +- motherboard-bus@40000000 { +- arm,hbi = <0x190>; +- arm,vexpress,site = <0>; +- compatible = "arm,vexpress,v2m-p1", "simple-bus"; +- #address-cells = <2>; /* SMB chipselect number and offset */ +- #size-cells = <1>; +- ranges = <0 0 0x40000000 0x04000000>, +- <1 0 0x44000000 0x04000000>, +- <2 0 0x48000000 0x04000000>, +- <3 0 0x4c000000 0x04000000>, +- <7 0 0x10000000 0x00020000>; +- +- flash@0,00000000 { +- compatible = "arm,vexpress-flash", "cfi-flash"; +- reg = <0 0x00000000 0x04000000>, +- <1 0x00000000 0x04000000>; +- bank-width = <4>; +- partitions { +- compatible = "arm,arm-firmware-suite"; +- }; +- }; +- +- psram@2,00000000 { +- compatible = "arm,vexpress-psram", "mtd-ram"; +- reg = <2 0x00000000 0x02000000>; +- bank-width = <4>; +- }; +- +- ethernet@3,02000000 { +- compatible = "smsc,lan9118", "smsc,lan9115"; +- reg = <3 0x02000000 0x10000>; +- interrupts = <15>; +- phy-mode = "mii"; +- reg-io-width = <4>; +- smsc,irq-active-high; +- smsc,irq-push-pull; +- vdd33a-supply = <&v2m_fixed_3v3>; +- vddvario-supply = <&v2m_fixed_3v3>; +- }; +- +- usb@3,03000000 { +- compatible = "nxp,usb-isp1761"; +- reg = <3 0x03000000 0x20000>; +- interrupts = <16>; +- dr_mode = "peripheral"; +- }; +- +- iofpga@7,00000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 7 0 0x20000>; +- +- v2m_sysreg: sysreg@0 { +- compatible = "arm,vexpress-sysreg"; +- reg = <0x00000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x1000>; +- +- v2m_led_gpios: gpio@8 { +- compatible = "arm,vexpress-sysreg,sys_led"; +- reg = <0x008 4>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- v2m_mmc_gpios: gpio@48 { +- compatible = "arm,vexpress-sysreg,sys_mci"; +- reg = <0x048 4>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- v2m_flash_gpios: gpio@4c { +- compatible = "arm,vexpress-sysreg,sys_flash"; +- reg = <0x04c 4>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +- +- v2m_sysctl: sysctl@1000 { +- compatible = "arm,sp810", "arm,primecell"; +- reg = <0x01000 0x1000>; +- clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; +- clock-names = "refclk", "timclk", "apb_pclk"; +- #clock-cells = <1>; +- clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; +- assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; +- assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; +- }; +- +- /* PCI-E I2C bus */ +- v2m_i2c_pcie: i2c@2000 { +- compatible = "arm,versatile-i2c"; +- reg = <0x02000 0x1000>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- pcie-switch@60 { +- compatible = "idt,89hpes32h8"; +- reg = <0x60>; +- }; +- }; +- +- aaci@4000 { +- compatible = "arm,pl041", "arm,primecell"; +- reg = <0x04000 0x1000>; +- interrupts = <11>; +- clocks = <&smbclk>; +- clock-names = "apb_pclk"; +- }; +- +- mmci@5000 { +- compatible = "arm,pl180", "arm,primecell"; +- reg = <0x05000 0x1000>; +- interrupts = <9>, <10>; +- cd-gpios = <&v2m_mmc_gpios 0 0>; +- wp-gpios = <&v2m_mmc_gpios 1 0>; +- max-frequency = <12000000>; +- vmmc-supply = <&v2m_fixed_3v3>; +- clocks = <&v2m_clk24mhz>, <&smbclk>; +- clock-names = "mclk", "apb_pclk"; +- }; +- +- kmi@6000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x06000 0x1000>; +- interrupts = <12>; +- clocks = <&v2m_clk24mhz>, <&smbclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- kmi@7000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x07000 0x1000>; +- interrupts = <13>; +- clocks = <&v2m_clk24mhz>, <&smbclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- v2m_serial0: uart@9000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x09000 0x1000>; +- interrupts = <5>; +- clocks = <&v2m_oscclk2>, <&smbclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- v2m_serial1: uart@a000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0a000 0x1000>; +- interrupts = <6>; +- clocks = <&v2m_oscclk2>, <&smbclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- v2m_serial2: uart@b000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0b000 0x1000>; +- interrupts = <7>; +- clocks = <&v2m_oscclk2>, <&smbclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- v2m_serial3: uart@c000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0c000 0x1000>; +- interrupts = <8>; +- clocks = <&v2m_oscclk2>, <&smbclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- wdt@f000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0f000 0x1000>; +- interrupts = <0>; +- clocks = <&v2m_refclk32khz>, <&smbclk>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- v2m_timer01: timer@11000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x11000 0x1000>; +- interrupts = <2>; +- clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; +- clock-names = "timclken1", "timclken2", "apb_pclk"; +- }; +- +- v2m_timer23: timer@12000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x12000 0x1000>; +- interrupts = <3>; +- clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; +- clock-names = "timclken1", "timclken2", "apb_pclk"; +- }; +- +- /* DVI I2C bus */ +- v2m_i2c_dvi: i2c@16000 { +- compatible = "arm,versatile-i2c"; +- reg = <0x16000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- dvi-transmitter@39 { +- compatible = "sil,sii9022-tpi", "sil,sii9022"; +- reg = <0x39>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* +- * Both the core tile and the motherboard routes their output +- * pads to this transmitter. The motherboard system controller +- * can select one of them as input using a mux register in +- * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is +- * the only platform with this specific set-up. +- */ +- port@0 { +- reg = <0>; +- dvi_bridge_in_ct: endpoint { +- remote-endpoint = <&clcd_pads_ct>; +- }; +- }; +- port@1 { +- reg = <1>; +- dvi_bridge_in_mb: endpoint { +- remote-endpoint = <&clcd_pads_mb>; +- }; +- }; +- }; +- }; +- +- dvi-transmitter@60 { +- compatible = "sil,sii9022-cpi", "sil,sii9022"; +- reg = <0x60>; +- }; +- }; +- +- rtc@17000 { +- compatible = "arm,pl031", "arm,primecell"; +- reg = <0x17000 0x1000>; +- interrupts = <4>; +- clocks = <&smbclk>; +- clock-names = "apb_pclk"; +- }; +- +- compact-flash@1a000 { +- compatible = "arm,vexpress-cf", "ata-generic"; +- reg = <0x1a000 0x100 +- 0x1a100 0xf00>; +- reg-shift = <2>; +- }; +- +- +- clcd@1f000 { +- compatible = "arm,pl111", "arm,primecell"; +- reg = <0x1f000 0x1000>; +- interrupt-names = "combined"; +- interrupts = <14>; +- clocks = <&v2m_oscclk1>, <&smbclk>; +- clock-names = "clcdclk", "apb_pclk"; +- /* 800x600 16bpp @36MHz works fine */ +- max-memory-bandwidth = <54000000>; +- memory-region = <&vram>; +- +- port { +- clcd_pads_mb: endpoint { +- remote-endpoint = <&dvi_bridge_in_mb>; +- arm,pl11x,tft-r0g0b0-pads = <0 8 16>; +- }; +- }; +- }; +- }; +- +- v2m_fixed_3v3: fixed-regulator-0 { +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- v2m_clk24mhz: clk24mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "v2m:clk24mhz"; +- }; +- +- v2m_refclk1mhz: refclk1mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <1000000>; +- clock-output-names = "v2m:refclk1mhz"; +- }; +- +- v2m_refclk32khz: refclk32khz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "v2m:refclk32khz"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- user1 { +- label = "v2m:green:user1"; +- gpios = <&v2m_led_gpios 0 0>; +- linux,default-trigger = "heartbeat"; +- }; +- +- user2 { +- label = "v2m:green:user2"; +- gpios = <&v2m_led_gpios 1 0>; +- linux,default-trigger = "mmc0"; +- }; +- +- user3 { +- label = "v2m:green:user3"; +- gpios = <&v2m_led_gpios 2 0>; +- linux,default-trigger = "cpu0"; +- }; +- +- user4 { +- label = "v2m:green:user4"; +- gpios = <&v2m_led_gpios 3 0>; +- linux,default-trigger = "cpu1"; +- }; +- +- user5 { +- label = "v2m:green:user5"; +- gpios = <&v2m_led_gpios 4 0>; +- linux,default-trigger = "cpu2"; +- }; +- +- user6 { +- label = "v2m:green:user6"; +- gpios = <&v2m_led_gpios 5 0>; +- linux,default-trigger = "cpu3"; +- }; +- +- user7 { +- label = "v2m:green:user7"; +- gpios = <&v2m_led_gpios 6 0>; +- linux,default-trigger = "cpu4"; +- }; +- +- user8 { +- label = "v2m:green:user8"; +- gpios = <&v2m_led_gpios 7 0>; +- linux,default-trigger = "cpu5"; +- }; +- }; +- +- mcc { +- compatible = "arm,vexpress,config-bus"; +- arm,vexpress,config-bridge = <&v2m_sysreg>; +- +- oscclk0 { +- /* MCC static memory clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 0>; +- freq-range = <25000000 60000000>; +- #clock-cells = <0>; +- clock-output-names = "v2m:oscclk0"; +- }; +- +- v2m_oscclk1: oscclk1 { +- /* CLCD clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 1>; +- freq-range = <23750000 65000000>; +- #clock-cells = <0>; +- clock-output-names = "v2m:oscclk1"; +- }; +- +- v2m_oscclk2: oscclk2 { +- /* IO FPGA peripheral clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 2>; +- freq-range = <24000000 24000000>; +- #clock-cells = <0>; +- clock-output-names = "v2m:oscclk2"; +- }; +- +- volt-vio { +- /* Logic level voltage */ +- compatible = "arm,vexpress-volt"; +- arm,vexpress-sysreg,func = <2 0>; +- regulator-name = "VIO"; +- regulator-always-on; +- label = "VIO"; +- }; +- +- temp-mcc { +- /* MCC internal operating temperature */ +- compatible = "arm,vexpress-temp"; +- arm,vexpress-sysreg,func = <4 0>; +- label = "MCC"; +- }; +- +- reset { +- compatible = "arm,vexpress-reset"; +- arm,vexpress-sysreg,func = <5 0>; +- }; +- +- muxfpga { +- compatible = "arm,vexpress-muxfpga"; +- arm,vexpress-sysreg,func = <7 0>; +- }; +- +- shutdown { +- compatible = "arm,vexpress-shutdown"; +- arm,vexpress-sysreg,func = <8 0>; +- }; +- +- reboot { +- compatible = "arm,vexpress-reboot"; +- arm,vexpress-sysreg,func = <9 0>; +- }; +- +- dvimode { +- compatible = "arm,vexpress-dvimode"; +- arm,vexpress-sysreg,func = <11 0>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vexpress-v2p-ca15-tc1.dts b/scripts/dtc/include-prefixes/arm/vexpress-v2p-ca15-tc1.dts +deleted file mode 100644 +index 679537e17ff5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vexpress-v2p-ca15-tc1.dts ++++ /dev/null +@@ -1,255 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * ARM Ltd. Versatile Express +- * +- * CoreTile Express A15x2 (version with Test Chip 1) +- * Cortex-A15 MPCore (V2P-CA15) +- * +- * HBI-0237A +- */ +- +-/dts-v1/; +-#include "vexpress-v2m-rs1.dtsi" +- +-/ { +- model = "V2P-CA15"; +- arm,hbi = <0x237>; +- arm,vexpress,site = <0xf>; +- compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- chosen { }; +- +- aliases { +- serial0 = &v2m_serial0; +- serial1 = &v2m_serial1; +- serial2 = &v2m_serial2; +- serial3 = &v2m_serial3; +- i2c0 = &v2m_i2c_dvi; +- i2c1 = &v2m_i2c_pcie; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <1>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0 0x80000000 0 0x40000000>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- /* Chipselect 2 is physically at 0x18000000 */ +- vram: vram@18000000 { +- /* 8 MB of designated video RAM */ +- compatible = "shared-dma-pool"; +- reg = <0 0x18000000 0 0x00800000>; +- no-map; +- }; +- }; +- +- hdlcd@2b000000 { +- compatible = "arm,hdlcd"; +- reg = <0 0x2b000000 0 0x1000>; +- interrupts = <0 85 4>; +- clocks = <&hdlcd_clk>; +- clock-names = "pxlclk"; +- }; +- +- memory-controller@2b0a0000 { +- compatible = "arm,pl341", "arm,primecell"; +- reg = <0 0x2b0a0000 0 0x1000>; +- clocks = <&sys_pll>; +- clock-names = "apb_pclk"; +- }; +- +- wdt@2b060000 { +- compatible = "arm,sp805", "arm,primecell"; +- status = "disabled"; +- reg = <0 0x2b060000 0 0x1000>; +- interrupts = <0 98 4>; +- clocks = <&sys_pll>, <&sys_pll>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- gic: interrupt-controller@2c001000 { +- compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0 0x2c001000 0 0x1000>, +- <0 0x2c002000 0 0x2000>, +- <0 0x2c004000 0 0x2000>, +- <0 0x2c006000 0 0x2000>; +- interrupts = <1 9 0xf04>; +- }; +- +- memory-controller@7ffd0000 { +- compatible = "arm,pl354", "arm,primecell"; +- reg = <0 0x7ffd0000 0 0x1000>; +- interrupts = <0 86 4>, +- <0 87 4>; +- clocks = <&sys_pll>; +- clock-names = "apb_pclk"; +- }; +- +- dma@7ffb0000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0 0x7ffb0000 0 0x1000>; +- interrupts = <0 92 4>, +- <0 88 4>, +- <0 89 4>, +- <0 90 4>, +- <0 91 4>; +- clocks = <&sys_pll>; +- clock-names = "apb_pclk"; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = <1 13 0xf08>, +- <1 14 0xf08>, +- <1 11 0xf08>, +- <1 10 0xf08>; +- }; +- +- pmu { +- compatible = "arm,cortex-a15-pmu"; +- interrupts = <0 68 4>, +- <0 69 4>; +- }; +- +- dcc { +- compatible = "arm,vexpress,config-bus"; +- arm,vexpress,config-bridge = <&v2m_sysreg>; +- +- oscclk0 { +- /* CPU PLL reference clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 0>; +- freq-range = <50000000 60000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk0"; +- }; +- +- oscclk4 { +- /* Multiplexed AXI master clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 4>; +- freq-range = <20000000 40000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk4"; +- }; +- +- hdlcd_clk: oscclk5 { +- /* HDLCD PLL reference clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 5>; +- freq-range = <23750000 165000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk5"; +- }; +- +- smbclk: oscclk6 { +- /* SMB clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 6>; +- freq-range = <20000000 50000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk6"; +- }; +- +- sys_pll: oscclk7 { +- /* SYS PLL reference clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 7>; +- freq-range = <20000000 60000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk7"; +- }; +- +- oscclk8 { +- /* DDR2 PLL reference clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 8>; +- freq-range = <40000000 40000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk8"; +- }; +- +- volt-cores { +- /* CPU core voltage */ +- compatible = "arm,vexpress-volt"; +- arm,vexpress-sysreg,func = <2 0>; +- regulator-name = "Cores"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1050000>; +- regulator-always-on; +- label = "Cores"; +- }; +- +- amp-cores { +- /* Total current for the two cores */ +- compatible = "arm,vexpress-amp"; +- arm,vexpress-sysreg,func = <3 0>; +- label = "Cores"; +- }; +- +- temp-dcc { +- /* DCC internal temperature */ +- compatible = "arm,vexpress-temp"; +- arm,vexpress-sysreg,func = <4 0>; +- label = "DCC"; +- }; +- +- power-cores { +- /* Total power */ +- compatible = "arm,vexpress-power"; +- arm,vexpress-sysreg,func = <12 0>; +- label = "Cores"; +- }; +- +- energy { +- /* Total energy */ +- compatible = "arm,vexpress-energy"; +- arm,vexpress-sysreg,func = <13 0>; +- label = "Cores"; +- }; +- }; +- +- bus@8000000 { +- ranges = <0x8000000 0 0x8000000 0x18000000>; +- }; +- +- site2: hsb@40000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x40000000 0x3fef0000>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 3>; +- interrupt-map = <0 0 &gic 0 36 4>, +- <0 1 &gic 0 37 4>, +- <0 2 &gic 0 38 4>, +- <0 3 &gic 0 39 4>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vexpress-v2p-ca15_a7.dts b/scripts/dtc/include-prefixes/arm/vexpress-v2p-ca15_a7.dts +deleted file mode 100644 +index 511e87cc2bc5..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vexpress-v2p-ca15_a7.dts ++++ /dev/null +@@ -1,636 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * ARM Ltd. Versatile Express +- * +- * CoreTile Express A15x2 A7x3 +- * Cortex-A15_A7 MPCore (V2P-CA15_A7) +- * +- * HBI-0249A +- */ +- +-/dts-v1/; +-#include "vexpress-v2m-rs1.dtsi" +- +-/ { +- model = "V2P-CA15_CA7"; +- arm,hbi = <0x249>; +- arm,vexpress,site = <0xf>; +- compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- chosen { }; +- +- aliases { +- serial0 = &v2m_serial0; +- serial1 = &v2m_serial1; +- serial2 = &v2m_serial2; +- serial3 = &v2m_serial3; +- i2c0 = &v2m_i2c_dvi; +- i2c1 = &v2m_i2c_pcie; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0>; +- cci-control-port = <&cci_control1>; +- cpu-idle-states = <&CLUSTER_SLEEP_BIG>; +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <990>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <1>; +- cci-control-port = <&cci_control1>; +- cpu-idle-states = <&CLUSTER_SLEEP_BIG>; +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <990>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x100>; +- cci-control-port = <&cci_control2>; +- cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; +- capacity-dmips-mhz = <516>; +- dynamic-power-coefficient = <133>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x101>; +- cci-control-port = <&cci_control2>; +- cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; +- capacity-dmips-mhz = <516>; +- dynamic-power-coefficient = <133>; +- }; +- +- cpu4: cpu@4 { +- device_type = "cpu"; +- compatible = "arm,cortex-a7"; +- reg = <0x102>; +- cci-control-port = <&cci_control2>; +- cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; +- capacity-dmips-mhz = <516>; +- dynamic-power-coefficient = <133>; +- }; +- +- idle-states { +- CLUSTER_SLEEP_BIG: cluster-sleep-big { +- compatible = "arm,idle-state"; +- local-timer-stop; +- entry-latency-us = <1000>; +- exit-latency-us = <700>; +- min-residency-us = <2000>; +- }; +- +- CLUSTER_SLEEP_LITTLE: cluster-sleep-little { +- compatible = "arm,idle-state"; +- local-timer-stop; +- entry-latency-us = <1000>; +- exit-latency-us = <500>; +- min-residency-us = <2500>; +- }; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0 0x80000000 0 0x40000000>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- /* Chipselect 2 is physically at 0x18000000 */ +- vram: vram@18000000 { +- /* 8 MB of designated video RAM */ +- compatible = "shared-dma-pool"; +- reg = <0 0x18000000 0 0x00800000>; +- no-map; +- }; +- }; +- +- wdt@2a490000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0 0x2a490000 0 0x1000>; +- interrupts = <0 98 4>; +- clocks = <&oscclk6a>, <&oscclk6a>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- hdlcd@2b000000 { +- compatible = "arm,hdlcd"; +- reg = <0 0x2b000000 0 0x1000>; +- interrupts = <0 85 4>; +- clocks = <&hdlcd_clk>; +- clock-names = "pxlclk"; +- }; +- +- memory-controller@2b0a0000 { +- compatible = "arm,pl341", "arm,primecell"; +- reg = <0 0x2b0a0000 0 0x1000>; +- clocks = <&oscclk6a>; +- clock-names = "apb_pclk"; +- }; +- +- gic: interrupt-controller@2c001000 { +- compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0 0x2c001000 0 0x1000>, +- <0 0x2c002000 0 0x2000>, +- <0 0x2c004000 0 0x2000>, +- <0 0x2c006000 0 0x2000>; +- interrupts = <1 9 0xf04>; +- }; +- +- cci@2c090000 { +- compatible = "arm,cci-400"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0 0x2c090000 0 0x1000>; +- ranges = <0x0 0x0 0x2c090000 0x10000>; +- +- cci_control1: slave-if@4000 { +- compatible = "arm,cci-400-ctrl-if"; +- interface-type = "ace"; +- reg = <0x4000 0x1000>; +- }; +- +- cci_control2: slave-if@5000 { +- compatible = "arm,cci-400-ctrl-if"; +- interface-type = "ace"; +- reg = <0x5000 0x1000>; +- }; +- +- pmu@9000 { +- compatible = "arm,cci-400-pmu,r0"; +- reg = <0x9000 0x5000>; +- interrupts = <0 105 4>, +- <0 101 4>, +- <0 102 4>, +- <0 103 4>, +- <0 104 4>; +- }; +- }; +- +- memory-controller@7ffd0000 { +- compatible = "arm,pl354", "arm,primecell"; +- reg = <0 0x7ffd0000 0 0x1000>; +- interrupts = <0 86 4>, +- <0 87 4>; +- clocks = <&oscclk6a>; +- clock-names = "apb_pclk"; +- }; +- +- dma@7ff00000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0 0x7ff00000 0 0x1000>; +- interrupts = <0 92 4>, +- <0 88 4>, +- <0 89 4>, +- <0 90 4>, +- <0 91 4>; +- clocks = <&oscclk6a>; +- clock-names = "apb_pclk"; +- }; +- +- scc@7fff0000 { +- compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; +- reg = <0 0x7fff0000 0 0x1000>; +- interrupts = <0 95 4>; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = <1 13 0xf08>, +- <1 14 0xf08>, +- <1 11 0xf08>, +- <1 10 0xf08>; +- }; +- +- pmu-a15 { +- compatible = "arm,cortex-a15-pmu"; +- interrupts = <0 68 4>, +- <0 69 4>; +- interrupt-affinity = <&cpu0>, +- <&cpu1>; +- }; +- +- pmu-a7 { +- compatible = "arm,cortex-a7-pmu"; +- interrupts = <0 128 4>, +- <0 129 4>, +- <0 130 4>; +- interrupt-affinity = <&cpu2>, +- <&cpu3>, +- <&cpu4>; +- }; +- +- oscclk6a: oscclk6a { +- /* Reference 24MHz clock */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "oscclk6a"; +- }; +- +- dcc { +- compatible = "arm,vexpress,config-bus"; +- arm,vexpress,config-bridge = <&v2m_sysreg>; +- +- oscclk0 { +- /* A15 PLL 0 reference clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 0>; +- freq-range = <17000000 50000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk0"; +- }; +- +- oscclk1 { +- /* A15 PLL 1 reference clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 1>; +- freq-range = <17000000 50000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk1"; +- }; +- +- oscclk2 { +- /* A7 PLL 0 reference clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 2>; +- freq-range = <17000000 50000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk2"; +- }; +- +- oscclk3 { +- /* A7 PLL 1 reference clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 3>; +- freq-range = <17000000 50000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk3"; +- }; +- +- oscclk4 { +- /* External AXI master clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 4>; +- freq-range = <20000000 40000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk4"; +- }; +- +- hdlcd_clk: oscclk5 { +- /* HDLCD PLL reference clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 5>; +- freq-range = <23750000 165000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk5"; +- }; +- +- smbclk: oscclk6 { +- /* Static memory controller clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 6>; +- freq-range = <20000000 40000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk6"; +- }; +- +- oscclk7 { +- /* SYS PLL reference clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 7>; +- freq-range = <17000000 50000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk7"; +- }; +- +- oscclk8 { +- /* DDR2 PLL reference clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 8>; +- freq-range = <20000000 50000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk8"; +- }; +- +- volt-a15 { +- /* A15 CPU core voltage */ +- compatible = "arm,vexpress-volt"; +- arm,vexpress-sysreg,func = <2 0>; +- regulator-name = "A15 Vcore"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1050000>; +- regulator-always-on; +- label = "A15 Vcore"; +- }; +- +- volt-a7 { +- /* A7 CPU core voltage */ +- compatible = "arm,vexpress-volt"; +- arm,vexpress-sysreg,func = <2 1>; +- regulator-name = "A7 Vcore"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1050000>; +- regulator-always-on; +- label = "A7 Vcore"; +- }; +- +- amp-a15 { +- /* Total current for the two A15 cores */ +- compatible = "arm,vexpress-amp"; +- arm,vexpress-sysreg,func = <3 0>; +- label = "A15 Icore"; +- }; +- +- amp-a7 { +- /* Total current for the three A7 cores */ +- compatible = "arm,vexpress-amp"; +- arm,vexpress-sysreg,func = <3 1>; +- label = "A7 Icore"; +- }; +- +- temp-dcc { +- /* DCC internal temperature */ +- compatible = "arm,vexpress-temp"; +- arm,vexpress-sysreg,func = <4 0>; +- label = "DCC"; +- }; +- +- power-a15 { +- /* Total power for the two A15 cores */ +- compatible = "arm,vexpress-power"; +- arm,vexpress-sysreg,func = <12 0>; +- label = "A15 Pcore"; +- }; +- +- power-a7 { +- /* Total power for the three A7 cores */ +- compatible = "arm,vexpress-power"; +- arm,vexpress-sysreg,func = <12 1>; +- label = "A7 Pcore"; +- }; +- +- energy-a15 { +- /* Total energy for the two A15 cores */ +- compatible = "arm,vexpress-energy"; +- arm,vexpress-sysreg,func = <13 0>, <13 1>; +- label = "A15 Jcore"; +- }; +- +- energy-a7 { +- /* Total energy for the three A7 cores */ +- compatible = "arm,vexpress-energy"; +- arm,vexpress-sysreg,func = <13 2>, <13 3>; +- label = "A7 Jcore"; +- }; +- }; +- +- etb@20010000 { +- compatible = "arm,coresight-etb10", "arm,primecell"; +- reg = <0 0x20010000 0 0x1000>; +- +- clocks = <&oscclk6a>; +- clock-names = "apb_pclk"; +- in-ports { +- port { +- etb_in_port: endpoint { +- remote-endpoint = <&replicator_out_port0>; +- }; +- }; +- }; +- }; +- +- tpiu@20030000 { +- compatible = "arm,coresight-tpiu", "arm,primecell"; +- reg = <0 0x20030000 0 0x1000>; +- +- clocks = <&oscclk6a>; +- clock-names = "apb_pclk"; +- in-ports { +- port { +- tpiu_in_port: endpoint { +- remote-endpoint = <&replicator_out_port1>; +- }; +- }; +- }; +- }; +- +- replicator { +- /* non-configurable replicators don't show up on the +- * AMBA bus. As such no need to add "arm,primecell". +- */ +- compatible = "arm,coresight-static-replicator"; +- +- out-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- replicator_out_port0: endpoint { +- remote-endpoint = <&etb_in_port>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- replicator_out_port1: endpoint { +- remote-endpoint = <&tpiu_in_port>; +- }; +- }; +- }; +- +- in-ports { +- port { +- replicator_in_port0: endpoint { +- remote-endpoint = <&funnel_out_port0>; +- }; +- }; +- }; +- }; +- +- funnel@20040000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x20040000 0 0x1000>; +- +- clocks = <&oscclk6a>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- funnel_out_port0: endpoint { +- remote-endpoint = +- <&replicator_in_port0>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- funnel_in_port0: endpoint { +- remote-endpoint = <&ptm0_out_port>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- funnel_in_port1: endpoint { +- remote-endpoint = <&ptm1_out_port>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- funnel_in_port2: endpoint { +- remote-endpoint = <&etm0_out_port>; +- }; +- }; +- +- /* Input port #3 is for ITM, not supported here */ +- +- port@4 { +- reg = <4>; +- funnel_in_port4: endpoint { +- remote-endpoint = <&etm1_out_port>; +- }; +- }; +- +- port@5 { +- reg = <5>; +- funnel_in_port5: endpoint { +- remote-endpoint = <&etm2_out_port>; +- }; +- }; +- }; +- }; +- +- ptm@2201c000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0x2201c000 0 0x1000>; +- +- cpu = <&cpu0>; +- clocks = <&oscclk6a>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- ptm0_out_port: endpoint { +- remote-endpoint = <&funnel_in_port0>; +- }; +- }; +- }; +- }; +- +- ptm@2201d000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0x2201d000 0 0x1000>; +- +- cpu = <&cpu1>; +- clocks = <&oscclk6a>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- ptm1_out_port: endpoint { +- remote-endpoint = <&funnel_in_port1>; +- }; +- }; +- }; +- }; +- +- etm@2203c000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0x2203c000 0 0x1000>; +- +- cpu = <&cpu2>; +- clocks = <&oscclk6a>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- etm0_out_port: endpoint { +- remote-endpoint = <&funnel_in_port2>; +- }; +- }; +- }; +- }; +- +- etm@2203d000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0x2203d000 0 0x1000>; +- +- cpu = <&cpu3>; +- clocks = <&oscclk6a>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- etm1_out_port: endpoint { +- remote-endpoint = <&funnel_in_port4>; +- }; +- }; +- }; +- }; +- +- etm@2203e000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0 0x2203e000 0 0x1000>; +- +- cpu = <&cpu4>; +- clocks = <&oscclk6a>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- etm2_out_port: endpoint { +- remote-endpoint = <&funnel_in_port5>; +- }; +- }; +- }; +- }; +- +- smb: bus@8000000 { +- ranges = <0x8000000 0 0x8000000 0x18000000>; +- }; +- +- site2: hsb@40000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x40000000 0x3fef0000>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 3>; +- interrupt-map = <0 0 &gic 0 36 4>, +- <0 1 &gic 0 37 4>, +- <0 2 &gic 0 38 4>, +- <0 3 &gic 0 39 4>; +- }; +-}; +- +-&nor_flash { +- /* +- * Unfortunately, accessing the flash disturbs the CPU idle states +- * (suspend) and CPU hotplug of this platform. For this reason, flash +- * hardware access is disabled by default on this platform alone. +- */ +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vexpress-v2p-ca5s.dts b/scripts/dtc/include-prefixes/arm/vexpress-v2p-ca5s.dts +deleted file mode 100644 +index 3b88209bacea..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vexpress-v2p-ca5s.dts ++++ /dev/null +@@ -1,225 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * ARM Ltd. Versatile Express +- * +- * CoreTile Express A5x2 +- * Cortex-A5 MPCore (V2P-CA5s) +- * +- * HBI-0225B +- */ +- +-/dts-v1/; +-#include "vexpress-v2m-rs1.dtsi" +- +-/ { +- model = "V2P-CA5s"; +- arm,hbi = <0x225>; +- arm,vexpress,site = <0xf>; +- compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- chosen { }; +- +- aliases { +- serial0 = &v2m_serial0; +- serial1 = &v2m_serial1; +- serial2 = &v2m_serial2; +- serial3 = &v2m_serial3; +- i2c0 = &v2m_i2c_dvi; +- i2c1 = &v2m_i2c_pcie; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a5"; +- reg = <0>; +- next-level-cache = <&L2>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a5"; +- reg = <1>; +- next-level-cache = <&L2>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x40000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* Chipselect 2 is physically at 0x18000000 */ +- vram: vram@18000000 { +- /* 8 MB of designated video RAM */ +- compatible = "shared-dma-pool"; +- reg = <0x18000000 0x00800000>; +- no-map; +- }; +- }; +- +- hdlcd@2a110000 { +- compatible = "arm,hdlcd"; +- reg = <0x2a110000 0x1000>; +- interrupts = <0 85 4>; +- clocks = <&hdlcd_clk>; +- clock-names = "pxlclk"; +- }; +- +- memory-controller@2a150000 { +- compatible = "arm,pl341", "arm,primecell"; +- reg = <0x2a150000 0x1000>; +- clocks = <&axi_clk>; +- clock-names = "apb_pclk"; +- }; +- +- memory-controller@2a190000 { +- compatible = "arm,pl354", "arm,primecell"; +- reg = <0x2a190000 0x1000>; +- interrupts = <0 86 4>, +- <0 87 4>; +- clocks = <&axi_clk>; +- clock-names = "apb_pclk"; +- }; +- +- scu@2c000000 { +- compatible = "arm,cortex-a5-scu"; +- reg = <0x2c000000 0x58>; +- }; +- +- timer@2c000600 { +- compatible = "arm,cortex-a5-twd-timer"; +- reg = <0x2c000600 0x20>; +- interrupts = <1 13 0x304>; +- }; +- +- timer@2c000200 { +- compatible = "arm,cortex-a5-global-timer", +- "arm,cortex-a9-global-timer"; +- reg = <0x2c000200 0x20>; +- interrupts = <1 11 0x304>; +- clocks = <&cpu_clk>; +- }; +- +- watchdog@2c000620 { +- compatible = "arm,cortex-a5-twd-wdt"; +- reg = <0x2c000620 0x20>; +- interrupts = <1 14 0x304>; +- }; +- +- gic: interrupt-controller@2c001000 { +- compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x2c001000 0x1000>, +- <0x2c000100 0x100>; +- }; +- +- L2: cache-controller@2c0f0000 { +- compatible = "arm,pl310-cache"; +- reg = <0x2c0f0000 0x1000>; +- interrupts = <0 84 4>; +- cache-level = <2>; +- }; +- +- pmu { +- compatible = "arm,cortex-a5-pmu"; +- interrupts = <0 68 4>, +- <0 69 4>; +- }; +- +- dcc { +- compatible = "arm,vexpress,config-bus"; +- arm,vexpress,config-bridge = <&v2m_sysreg>; +- +- cpu_clk: oscclk0 { +- /* CPU and internal AXI reference clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 0>; +- freq-range = <50000000 100000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk0"; +- }; +- +- axi_clk: oscclk1 { +- /* Multiplexed AXI master clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 1>; +- freq-range = <5000000 50000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk1"; +- }; +- +- oscclk2 { +- /* DDR2 */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 2>; +- freq-range = <80000000 120000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk2"; +- }; +- +- hdlcd_clk: oscclk3 { +- /* HDLCD */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 3>; +- freq-range = <23750000 165000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk3"; +- }; +- +- oscclk4 { +- /* Test chip gate configuration */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 4>; +- freq-range = <80000000 80000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk4"; +- }; +- +- smbclk: oscclk5 { +- /* SMB clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 5>; +- freq-range = <25000000 60000000>; +- #clock-cells = <0>; +- clock-output-names = "oscclk5"; +- }; +- +- temp-dcc { +- /* DCC internal operating temperature */ +- compatible = "arm,vexpress-temp"; +- arm,vexpress-sysreg,func = <4 0>; +- label = "DCC"; +- }; +- }; +- +- smb: bus@8000000 { +- ranges = <0 0x8000000 0x18000000>; +- }; +- +- site2: hsb@40000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x40000000 0x40000000>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 3>; +- interrupt-map = <0 0 &gic 0 36 4>, +- <0 1 &gic 0 37 4>, +- <0 2 &gic 0 38 4>, +- <0 3 &gic 0 39 4>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vexpress-v2p-ca9.dts b/scripts/dtc/include-prefixes/arm/vexpress-v2p-ca9.dts +deleted file mode 100644 +index 5916e4877eac..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vexpress-v2p-ca9.dts ++++ /dev/null +@@ -1,310 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * ARM Ltd. Versatile Express +- * +- * CoreTile Express A9x4 +- * Cortex-A9 MPCore (V2P-CA9) +- * +- * HBI-0191B +- */ +- +-/dts-v1/; +-#include "vexpress-v2m.dtsi" +- +-/ { +- model = "V2P-CA9"; +- arm,hbi = <0x191>; +- arm,vexpress,site = <0xf>; +- compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- chosen { }; +- +- aliases { +- serial0 = &v2m_serial0; +- serial1 = &v2m_serial1; +- serial2 = &v2m_serial2; +- serial3 = &v2m_serial3; +- i2c0 = &v2m_i2c_dvi; +- i2c1 = &v2m_i2c_pcie; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- A9_0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- next-level-cache = <&L2>; +- }; +- +- A9_1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <1>; +- next-level-cache = <&L2>; +- }; +- +- A9_2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <2>; +- next-level-cache = <&L2>; +- }; +- +- A9_3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <3>; +- next-level-cache = <&L2>; +- }; +- }; +- +- memory@60000000 { +- device_type = "memory"; +- reg = <0x60000000 0x40000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* Chipselect 3 is physically at 0x4c000000 */ +- vram: vram@4c000000 { +- /* 8 MB of designated video RAM */ +- compatible = "shared-dma-pool"; +- reg = <0x4c000000 0x00800000>; +- no-map; +- }; +- }; +- +- clcd@10020000 { +- compatible = "arm,pl111", "arm,primecell"; +- reg = <0x10020000 0x1000>; +- interrupt-names = "combined"; +- interrupts = <0 44 4>; +- clocks = <&oscclk1>, <&oscclk2>; +- clock-names = "clcdclk", "apb_pclk"; +- /* 1024x768 16bpp @65MHz */ +- max-memory-bandwidth = <95000000>; +- +- port { +- clcd_pads_ct: endpoint { +- remote-endpoint = <&dvi_bridge_in_ct>; +- arm,pl11x,tft-r0g0b0-pads = <0 8 16>; +- }; +- }; +- }; +- +- memory-controller@100e0000 { +- compatible = "arm,pl341", "arm,primecell"; +- reg = <0x100e0000 0x1000>; +- clocks = <&oscclk2>; +- clock-names = "apb_pclk"; +- }; +- +- memory-controller@100e1000 { +- compatible = "arm,pl354", "arm,primecell"; +- reg = <0x100e1000 0x1000>; +- interrupts = <0 45 4>, +- <0 46 4>; +- clocks = <&oscclk2>; +- clock-names = "apb_pclk"; +- }; +- +- timer@100e4000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x100e4000 0x1000>; +- interrupts = <0 48 4>, +- <0 49 4>; +- clocks = <&oscclk2>, <&oscclk2>, <&oscclk2>; +- clock-names = "timer0clk", "timer1clk", "apb_pclk"; +- status = "disabled"; +- }; +- +- watchdog@100e5000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x100e5000 0x1000>; +- interrupts = <0 51 4>; +- clocks = <&oscclk2>, <&oscclk2>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- scu@1e000000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0x1e000000 0x58>; +- }; +- +- timer@1e000600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x1e000600 0x20>; +- interrupts = <1 13 0xf04>; +- }; +- +- watchdog@1e000620 { +- compatible = "arm,cortex-a9-twd-wdt"; +- reg = <0x1e000620 0x20>; +- interrupts = <1 14 0xf04>; +- }; +- +- gic: interrupt-controller@1e001000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x1e001000 0x1000>, +- <0x1e000100 0x100>; +- }; +- +- L2: cache-controller@1e00a000 { +- compatible = "arm,pl310-cache"; +- reg = <0x1e00a000 0x1000>; +- interrupts = <0 43 4>; +- cache-unified; +- cache-level = <2>; +- arm,data-latency = <1 1 1>; +- arm,tag-latency = <1 1 1>; +- }; +- +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = <0 60 4>, +- <0 61 4>, +- <0 62 4>, +- <0 63 4>; +- interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; +- +- }; +- +- dcc { +- compatible = "arm,vexpress,config-bus"; +- arm,vexpress,config-bridge = <&v2m_sysreg>; +- +- oscclk0: extsaxiclk { +- /* ACLK clock to the AXI master port on the test chip */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 0>; +- freq-range = <30000000 50000000>; +- #clock-cells = <0>; +- clock-output-names = "extsaxiclk"; +- }; +- +- oscclk1: clcdclk { +- /* Reference clock for the CLCD */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 1>; +- freq-range = <10000000 80000000>; +- #clock-cells = <0>; +- clock-output-names = "clcdclk"; +- }; +- +- smbclk: oscclk2: tcrefclk { +- /* Reference clock for the test chip internal PLLs */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 2>; +- freq-range = <33000000 100000000>; +- #clock-cells = <0>; +- clock-output-names = "tcrefclk"; +- }; +- +- volt-vd10 { +- /* Test Chip internal logic voltage */ +- compatible = "arm,vexpress-volt"; +- arm,vexpress-sysreg,func = <2 0>; +- regulator-name = "VD10"; +- regulator-always-on; +- label = "VD10"; +- }; +- +- volt-vd10-s2 { +- /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ +- compatible = "arm,vexpress-volt"; +- arm,vexpress-sysreg,func = <2 1>; +- regulator-name = "VD10_S2"; +- regulator-always-on; +- label = "VD10_S2"; +- }; +- +- volt-vd10-s3 { +- /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ +- compatible = "arm,vexpress-volt"; +- arm,vexpress-sysreg,func = <2 2>; +- regulator-name = "VD10_S3"; +- regulator-always-on; +- label = "VD10_S3"; +- }; +- +- volt-vcc1v8 { +- /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ +- compatible = "arm,vexpress-volt"; +- arm,vexpress-sysreg,func = <2 3>; +- regulator-name = "VCC1V8"; +- regulator-always-on; +- label = "VCC1V8"; +- }; +- +- volt-ddr2vtt { +- /* DDR2 SDRAM VTT termination voltage */ +- compatible = "arm,vexpress-volt"; +- arm,vexpress-sysreg,func = <2 4>; +- regulator-name = "DDR2VTT"; +- regulator-always-on; +- label = "DDR2VTT"; +- }; +- +- volt-vcc3v3 { +- /* Local board supply for miscellaneous logic external to the Test Chip */ +- arm,vexpress-sysreg,func = <2 5>; +- compatible = "arm,vexpress-volt"; +- regulator-name = "VCC3V3"; +- regulator-always-on; +- label = "VCC3V3"; +- }; +- +- amp-vd10-s2 { +- /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ +- compatible = "arm,vexpress-amp"; +- arm,vexpress-sysreg,func = <3 0>; +- label = "VD10_S2"; +- }; +- +- amp-vd10-s3 { +- /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ +- compatible = "arm,vexpress-amp"; +- arm,vexpress-sysreg,func = <3 1>; +- label = "VD10_S3"; +- }; +- +- power-vd10-s2 { +- /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ +- compatible = "arm,vexpress-power"; +- arm,vexpress-sysreg,func = <12 0>; +- label = "PVD10_S2"; +- }; +- +- power-vd10-s3 { +- /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ +- compatible = "arm,vexpress-power"; +- arm,vexpress-sysreg,func = <12 1>; +- label = "PVD10_S3"; +- }; +- }; +- +- site2: hsb@e0000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xe0000000 0x20000000>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 3>; +- interrupt-map = <0 0 &gic 0 36 4>, +- <0 1 &gic 0 37 4>, +- <0 2 &gic 0 38 4>, +- <0 3 &gic 0 39 4>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf-colibri-eval-v3.dtsi b/scripts/dtc/include-prefixes/arm/vf-colibri-eval-v3.dtsi +deleted file mode 100644 +index c12a1b8bc086..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf-colibri-eval-v3.dtsi ++++ /dev/null +@@ -1,152 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2014-2020 Toradex +- */ +- +-/ { +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- clk16m: clk16m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <16000000>; +- }; +- +- panel: panel { +- compatible = "edt,et057090dhu"; +- backlight = <&bl>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&dcu_out>; +- }; +- }; +- }; +- +- reg_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_5v0: regulator-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usbh_vbus: regulator-usbh-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbh1_reg>; +- regulator-name = "VCC_USB[1-4]"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; /* USBH_PEN resp. USBH_P_EN */ +- vin-supply = <®_5v0>; +- }; +-}; +- +-&bl { +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- power-supply = <®_3v3>; +- status = "okay"; +-}; +- +-&dcu0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dcu0_1>; +- status = "okay"; +- +- port { +- dcu_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +-}; +- +-&dspi1 { +- status = "okay"; +- +- mcp2515can: can@0 { +- compatible = "microchip,mcp2515"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can_int>; +- reg = <0>; +- clocks = <&clk16m>; +- spi-max-frequency = <10000000>; +- interrupt-parent = <&gpio1>; +- interrupts = <11 IRQ_TYPE_EDGE_RISING>; +- }; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&fec1 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- /* M41T0M6 real time clock on carrier board */ +- rtc: m41t0m6@68 { +- compatible = "st,m41t0"; +- reg = <0x68>; +- }; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-®_module_3v3 { +- vin-supply = <®_3v3>; +-}; +- +-&tcon0 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usbh1 { +- vbus-supply = <®_usbh_vbus>; +-}; +- +-&iomuxc { +- vf610-colibri { +- pinctrl_can_int: can_int { +- fsl,pins = < +- VF610_PAD_PTB21__GPIO_43 0x22ed +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf-colibri.dtsi b/scripts/dtc/include-prefixes/arm/vf-colibri.dtsi +deleted file mode 100644 +index cc1e069c44e6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf-colibri.dtsi ++++ /dev/null +@@ -1,350 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2014-2020 Toradex +- * +- */ +- +-/ { +- aliases { +- ethernet0 = &fec1; +- ethernet1 = &fec0; +- }; +- +- bl: backlight { +- compatible = "pwm-backlight"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_bl_on>; +- pwms = <&pwm0 0 5000000 0>; +- enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; +- status = "disabled"; +- }; +- +- reg_module_3v3: regulator-module-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_module_3v3_avdd: regulator-module-3v3-avdd { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3_AVDD_AUDIO"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&adc0 { +- status = "okay"; +- vref-supply = <®_module_3v3_avdd>; +-}; +- +-&adc1 { +- status = "okay"; +- vref-supply = <®_module_3v3_avdd>; +-}; +- +-&can0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan0>; +- status = "disabled"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- status = "disabled"; +-}; +- +-&clks { +- assigned-clocks = <&clks VF610_CLK_ENET_SEL>, +- <&clks VF610_CLK_ENET_TS_SEL>; +- assigned-clock-parents = <&clks VF610_CLK_ENET_50M>, +- <&clks VF610_CLK_ENET_50M>; +-}; +- +-&dspi1 { +- bus-num = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dspi1>; +-}; +- +-&edma0 { +- status = "okay"; +-}; +- +-&edma1 { +- status = "okay"; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- bus-width = <4>; +- cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; +- disable-wp; +-}; +- +-&fec1 { +- phy-mode = "rmii"; +- phy-supply = <®_module_3v3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c0>; +- pinctrl-1 = <&pinctrl_i2c0_gpio>; +- scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +-}; +- +-&nfc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nfc>; +- status = "okay"; +- +- nand@0 { +- compatible = "fsl,vf610-nfc-nandcs"; +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- nand-bus-width = <8>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <32>; +- nand-ecc-step-size = <2048>; +- nand-on-flash-bbt; +- }; +-}; +- +-&pwm0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0>; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +-}; +- +-&usbdev0 { +- disable-over-current; +- status = "okay"; +-}; +- +-&usbh1 { +- disable-over-current; +- status = "okay"; +-}; +- +-&usbmisc0 { +- status = "okay"; +-}; +- +-&usbmisc1 { +- status = "okay"; +-}; +- +-&usbphy0 { +- status = "okay"; +-}; +- +-&usbphy1 { +- status = "okay"; +-}; +- +-&iomuxc { +- vf610-colibri { +- pinctrl_flexcan0: can0grp { +- fsl,pins = < +- VF610_PAD_PTB14__CAN0_RX 0x31F1 +- VF610_PAD_PTB15__CAN0_TX 0x31F2 +- >; +- }; +- +- pinctrl_flexcan1: can1grp { +- fsl,pins = < +- VF610_PAD_PTB16__CAN1_RX 0x31F1 +- VF610_PAD_PTB17__CAN1_TX 0x31F2 +- >; +- }; +- +- pinctrl_gpio_ext: gpio_ext { +- fsl,pins = < +- VF610_PAD_PTD10__GPIO_89 0x22ed /* EXT_IO_0 */ +- VF610_PAD_PTD9__GPIO_88 0x22ed /* EXT_IO_1 */ +- VF610_PAD_PTD26__GPIO_68 0x22ed /* EXT_IO_2 */ +- >; +- }; +- +- pinctrl_dcu0_1: dcu0grp_1 { +- fsl,pins = < +- VF610_PAD_PTE0__DCU0_HSYNC 0x1902 +- VF610_PAD_PTE1__DCU0_VSYNC 0x1902 +- VF610_PAD_PTE2__DCU0_PCLK 0x1902 +- VF610_PAD_PTE4__DCU0_DE 0x1902 +- VF610_PAD_PTE5__DCU0_R0 0x1902 +- VF610_PAD_PTE6__DCU0_R1 0x1902 +- VF610_PAD_PTE7__DCU0_R2 0x1902 +- VF610_PAD_PTE8__DCU0_R3 0x1902 +- VF610_PAD_PTE9__DCU0_R4 0x1902 +- VF610_PAD_PTE10__DCU0_R5 0x1902 +- VF610_PAD_PTE11__DCU0_R6 0x1902 +- VF610_PAD_PTE12__DCU0_R7 0x1902 +- VF610_PAD_PTE13__DCU0_G0 0x1902 +- VF610_PAD_PTE14__DCU0_G1 0x1902 +- VF610_PAD_PTE15__DCU0_G2 0x1902 +- VF610_PAD_PTE16__DCU0_G3 0x1902 +- VF610_PAD_PTE17__DCU0_G4 0x1902 +- VF610_PAD_PTE18__DCU0_G5 0x1902 +- VF610_PAD_PTE19__DCU0_G6 0x1902 +- VF610_PAD_PTE20__DCU0_G7 0x1902 +- VF610_PAD_PTE21__DCU0_B0 0x1902 +- VF610_PAD_PTE22__DCU0_B1 0x1902 +- VF610_PAD_PTE23__DCU0_B2 0x1902 +- VF610_PAD_PTE24__DCU0_B3 0x1902 +- VF610_PAD_PTE25__DCU0_B4 0x1902 +- VF610_PAD_PTE26__DCU0_B5 0x1902 +- VF610_PAD_PTE27__DCU0_B6 0x1902 +- VF610_PAD_PTE28__DCU0_B7 0x1902 +- >; +- }; +- +- pinctrl_dspi1: dspi1grp { +- fsl,pins = < +- VF610_PAD_PTD5__DSPI1_CS0 0x33e2 +- VF610_PAD_PTD6__DSPI1_SIN 0x33e1 +- VF610_PAD_PTD7__DSPI1_SOUT 0x33e2 +- VF610_PAD_PTD8__DSPI1_SCK 0x33e2 +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- VF610_PAD_PTA24__ESDHC1_CLK 0x31ef +- VF610_PAD_PTA25__ESDHC1_CMD 0x31ef +- VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef +- VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef +- VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef +- VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef +- VF610_PAD_PTB20__GPIO_42 0x219d +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- VF610_PAD_PTA6__RMII_CLKOUT 0x30d2 +- VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 +- VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 +- VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 +- VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 +- VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 +- VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 +- VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 +- VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 +- VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 +- >; +- }; +- +- pinctrl_gpio_bl_on: gpio_bl_on { +- fsl,pins = < +- VF610_PAD_PTC0__GPIO_45 0x22ef +- >; +- }; +- +- pinctrl_i2c0: i2c0grp { +- fsl,pins = < +- VF610_PAD_PTB14__I2C0_SCL 0x37ff +- VF610_PAD_PTB15__I2C0_SDA 0x37ff +- >; +- }; +- +- pinctrl_i2c0_gpio: i2c0gpiogrp { +- fsl,pins = < +- VF610_PAD_PTB14__GPIO_36 0x37ff +- VF610_PAD_PTB15__GPIO_37 0x37ff +- >; +- }; +- +- pinctrl_nfc: nfcgrp { +- fsl,pins = < +- VF610_PAD_PTD23__NF_IO7 0x28df +- VF610_PAD_PTD22__NF_IO6 0x28df +- VF610_PAD_PTD21__NF_IO5 0x28df +- VF610_PAD_PTD20__NF_IO4 0x28df +- VF610_PAD_PTD19__NF_IO3 0x28df +- VF610_PAD_PTD18__NF_IO2 0x28df +- VF610_PAD_PTD17__NF_IO1 0x28df +- VF610_PAD_PTD16__NF_IO0 0x28df +- VF610_PAD_PTB24__NF_WE_B 0x28c2 +- VF610_PAD_PTB25__NF_CE0_B 0x28c2 +- VF610_PAD_PTB27__NF_RE_B 0x28c2 +- VF610_PAD_PTC26__NF_RB_B 0x283d +- VF610_PAD_PTC27__NF_ALE 0x28c2 +- VF610_PAD_PTC28__NF_CLE 0x28c2 +- >; +- }; +- +- pinctrl_pwm0: pwm0grp { +- fsl,pins = < +- VF610_PAD_PTB0__FTM0_CH0 0x1182 +- VF610_PAD_PTB1__FTM0_CH1 0x1182 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- VF610_PAD_PTB8__FTM1_CH0 0x1182 +- VF610_PAD_PTB9__FTM1_CH1 0x1182 +- >; +- }; +- +- pinctrl_uart0: uart0grp { +- fsl,pins = < +- VF610_PAD_PTB10__UART0_TX 0x21a2 +- VF610_PAD_PTB11__UART0_RX 0x21a1 +- VF610_PAD_PTB12__UART0_RTS 0x21a2 +- VF610_PAD_PTB13__UART0_CTS 0x21a1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- VF610_PAD_PTB4__UART1_TX 0x21a2 +- VF610_PAD_PTB5__UART1_RX 0x21a1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- VF610_PAD_PTD0__UART2_TX 0x21a2 +- VF610_PAD_PTD1__UART2_RX 0x21a1 +- VF610_PAD_PTD2__UART2_RTS 0x21a2 +- VF610_PAD_PTD3__UART2_CTS 0x21a1 +- >; +- }; +- +- pinctrl_usbh1_reg: gpio_usb_vbus { +- fsl,pins = < +- VF610_PAD_PTD4__GPIO_83 0x22ed +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf500-colibri-eval-v3.dts b/scripts/dtc/include-prefixes/arm/vf500-colibri-eval-v3.dts +deleted file mode 100644 +index 088964f8dc4b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf500-colibri-eval-v3.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2014-2020 Toradex +- */ +- +-/dts-v1/; +-#include "vf500-colibri.dtsi" +-#include "vf-colibri-eval-v3.dtsi" +- +-/ { +- model = "Toradex Colibri VF50 on Colibri Evaluation Board"; +- compatible = "toradex,vf500-colibri_vf50-on-eval", "toradex,vf500-colibri_vf50", "fsl,vf500"; +-}; +- +-&touchscreen { +- vf50-ts-min-pressure = <200>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf500-colibri.dtsi b/scripts/dtc/include-prefixes/arm/vf500-colibri.dtsi +deleted file mode 100644 +index 8af7ed56e653..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf500-colibri.dtsi ++++ /dev/null +@@ -1,69 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2014-2020 Toradex +- */ +- +-#include "vf500.dtsi" +-#include "vf-colibri.dtsi" +- +-/ { +- model = "Toradex Colibri VF50 COM"; +- compatible = "toradex,vf500-colibri_vf50", "fsl,vf500"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x8000000>; +- }; +- +- touchscreen: vf50-touchscreen { +- compatible = "toradex,vf50-touchscreen"; +- io-channels = <&adc1 0>,<&adc0 0>, +- <&adc0 1>,<&adc1 2>; +- xp-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; +- xm-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; +- yp-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; +- ym-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; +- interrupt-parent = <&gpio0>; +- interrupts = <8 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "idle","default","gpios"; +- pinctrl-0 = <&pinctrl_touchctrl_idle>; +- pinctrl-1 = <&pinctrl_touchctrl_default>; +- pinctrl-2 = <&pinctrl_touchctrl_gpios>; +- vf50-ts-min-pressure = <200>; +- status = "disabled"; +- }; +-}; +- +-&nfc { +- assigned-clocks = <&clks VF610_CLK_NFC>; +- assigned-clock-rates = <33000000>; +-}; +- +-&iomuxc { +- vf610-colibri { +- pinctrl_touchctrl_idle: touchctrl_idle { +- fsl,pins = < +- VF610_PAD_PTA18__GPIO_8 0x006d +- VF610_PAD_PTA19__GPIO_9 0x006c +- >; +- }; +- +- pinctrl_touchctrl_default: touchctrl_default { +- fsl,pins = < +- VF610_PAD_PTA18__ADC0_SE0 0x0040 +- VF610_PAD_PTA19__ADC0_SE1 0x0040 +- VF610_PAD_PTA16__ADC1_SE0 0x0040 +- VF610_PAD_PTB2__ADC1_SE2 0x0040 +- >; +- }; +- +- pinctrl_touchctrl_gpios: touchctrl_gpios { +- fsl,pins = < +- VF610_PAD_PTA23__GPIO_13 0x22e9 +- VF610_PAD_PTB23__GPIO_93 0x22e9 +- VF610_PAD_PTA22__GPIO_12 0x22e9 +- VF610_PAD_PTA11__GPIO_4 0x22e9 +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf500.dtsi b/scripts/dtc/include-prefixes/arm/vf500.dtsi +deleted file mode 100644 +index 0c0dd442300a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf500.dtsi ++++ /dev/null +@@ -1,64 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright 2013 Freescale Semiconductor, Inc. +- +-#include "vfxxx.dtsi" +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- chosen { }; +- aliases { }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- a5_cpu: cpu@0 { +- compatible = "arm,cortex-a5"; +- device_type = "cpu"; +- reg = <0x0>; +- }; +- }; +- +- soc { +- bus@40000000 { +- +- intc: interrupt-controller@40003000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- interrupt-parent = <&intc>; +- reg = <0x40003000 0x1000>, +- <0x40002100 0x100>; +- }; +- +- global_timer: timer@40002200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0x40002200 0x20>; +- interrupts = ; +- interrupt-parent = <&intc>; +- clocks = <&clks VF610_CLK_PLATFORM_BUS>; +- }; +- }; +- +- bus@40080000 { +- pmu@40089000 { +- compatible = "arm,cortex-a5-pmu"; +- interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&a5_cpu>; +- reg = <0x40089000 0x1000>; +- }; +- }; +- +- }; +-}; +- +-&mscm_ir { +- interrupt-parent = <&intc>; +-}; +- +-&wdoga5 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf610-bk4.dts b/scripts/dtc/include-prefixes/arm/vf610-bk4.dts +deleted file mode 100644 +index 830c85476b3d..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf610-bk4.dts ++++ /dev/null +@@ -1,537 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2018 +- * Lukasz Majewski, DENX Software Engineering, lukma@denx.de +- */ +- +-/dts-v1/; +-#include "vf610.dtsi" +- +-/ { +- model = "Liebherr BK4 controller"; +- compatible = "lwn,bk4", "fsl,vf610"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x8000000>; +- }; +- +- audio_ext: oscillator-audio { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +- +- enet_ext: oscillator-ethernet { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- /* LED D5 */ +- led0: heartbeat { +- label = "heartbeat"; +- gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_vcc_3v3_mcu: regulator-vcc3v3mcu { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_3v3_mcu"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- spi-gpio { +- compatible = "spi-gpio"; +- pinctrl-0 = <&pinctrl_gpio_spi>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- /* PTD12 ->RPIO[91] */ +- sck-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; +- /* PTD10 ->RPIO[89] */ +- miso-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; +- num-chipselects = <0>; +- +- gpio@0 { +- compatible = "pisosr-gpio"; +- reg = <0>; +- gpio-controller; +- #gpio-cells = <2>; +- /* PTB18 -> RGPIO[40] */ +- load-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; +- spi-max-frequency = <100000>; +- }; +- }; +-}; +- +-&adc0 { +- vref-supply = <®_vcc_3v3_mcu>; +- status = "okay"; +-}; +- +-&adc1 { +- vref-supply = <®_vcc_3v3_mcu>; +- status = "okay"; +-}; +- +-&can0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can0>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can1>; +- status = "okay"; +-}; +- +-&clks { +- clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>; +- clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext"; +-}; +- +-&dspi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dspi0>; +- bus-num = <0>; +- status = "okay"; +- +- spidev0@0 { +- compatible = "lwn,bk4"; +- spi-max-frequency = <30000000>; +- reg = <0>; +- fsl,spi-cs-sck-delay = <200>; +- fsl,spi-sck-cs-delay = <400>; +- }; +-}; +- +-&dspi3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dspi3>; +- bus-num = <3>; +- status = "okay"; +- spi-slave; +- #address-cells = <0>; +- +- slave { +- compatible = "lwn,bk4"; +- spi-max-frequency = <30000000>; +- }; +-}; +- +-&edma0 { +- status = "okay"; +-}; +- +-&edma1 { +- status = "okay"; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- bus-width = <4>; +- cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&fec0 { +- phy-mode = "rmii"; +- phy-handle = <ðphy0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec0>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@1 { +- reg = <1>; +- clocks = <&clks VF610_CLK_ENET_50M>; +- clock-names = "rmii-ref"; +- }; +- }; +-}; +- +-&fec1 { +- phy-mode = "rmii"; +- phy-handle = <ðphy1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- clocks = <&clks VF610_CLK_ENET_50M>; +- clock-names = "rmii-ref"; +- }; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- at24c256: eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- }; +- +- m41t62: rtc@68 { +- compatible = "st,m41t62"; +- reg = <0x68>; +- }; +-}; +- +-&nfc { +- assigned-clocks = <&clks VF610_CLK_NFC>; +- assigned-clock-rates = <33000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nfc>; +- status = "okay"; +- +- nand@0 { +- compatible = "fsl,vf610-nfc-nandcs"; +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- nand-bus-width = <16>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <24>; +- nand-ecc-step-size = <2048>; +- nand-on-flash-bbt; +- }; +-}; +- +-&qspi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_qspi0>; +- status = "okay"; +- +- n25q128a13_4: flash@0 { +- compatible = "n25q128a13", "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <66000000>; +- spi-rx-bus-width = <4>; +- reg = <0>; +- }; +- +- n25q128a13_2: flash@2 { +- compatible = "n25q128a13", "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <66000000>; +- spi-rx-bus-width = <2>; +- reg = <2>; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- /delete-property/dma-names; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- /delete-property/dma-names; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- /delete-property/dma-names; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- /delete-property/dma-names; +- status = "okay"; +-}; +- +-&usbdev0 { +- disable-over-current; +- status = "okay"; +-}; +- +-&usbh1 { +- disable-over-current; +- status = "okay"; +-}; +- +-&usbmisc0 { +- status = "okay"; +-}; +- +-&usbmisc1 { +- status = "okay"; +-}; +- +-&usbphy0 { +- status = "okay"; +-}; +- +-&usbphy1 { +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- /* One_Wire_PSU_EN */ +- VF610_PAD_PTC29__GPIO_102 0x1183 +- /* SPI ENABLE */ +- VF610_PAD_PTB26__GPIO_96 0x1183 +- /* EB control */ +- VF610_PAD_PTE14__GPIO_119 0x1183 +- VF610_PAD_PTE4__GPIO_109 0x1181 +- /* Feedback_Lines */ +- VF610_PAD_PTC31__GPIO_104 0x1181 +- VF610_PAD_PTA7__GPIO_134 0x1181 +- VF610_PAD_PTD9__GPIO_88 0x1181 +- VF610_PAD_PTE1__GPIO_106 0x1183 +- VF610_PAD_PTB2__GPIO_24 0x1181 +- VF610_PAD_PTB3__GPIO_25 0x1181 +- VF610_PAD_PTB1__GPIO_23 0x1181 +- /* SDHC Enable */ +- VF610_PAD_PTE19__GPIO_124 0x1183 +- /* SDHC Overcurrent */ +- VF610_PAD_PTB23__GPIO_93 0x1181 +- /* GPI */ +- VF610_PAD_PTE2__GPIO_107 0x1181 +- VF610_PAD_PTE3__GPIO_108 0x1181 +- VF610_PAD_PTE5__GPIO_110 0x1181 +- VF610_PAD_PTE6__GPIO_111 0x1181 +- /* GPO */ +- VF610_PAD_PTE0__GPIO_105 0x1183 +- VF610_PAD_PTE7__GPIO_112 0x1183 +- /* RS485 Control */ +- VF610_PAD_PTB8__GPIO_30 0x1183 +- VF610_PAD_PTB9__GPIO_31 0x1183 +- VF610_PAD_PTE8__GPIO_113 0x1183 +- /* MPBUS MPB_EN */ +- VF610_PAD_PTE28__GPIO_133 0x1183 +- /* MISC */ +- VF610_PAD_PTE10__GPIO_115 0x1183 +- VF610_PAD_PTE11__GPIO_116 0x1183 +- VF610_PAD_PTE17__GPIO_122 0x1183 +- VF610_PAD_PTC30__GPIO_103 0x1183 +- VF610_PAD_PTB0__GPIO_22 0x1181 +- /* RESETINFO */ +- VF610_PAD_PTE26__GPIO_131 0x1183 +- VF610_PAD_PTD6__GPIO_85 0x1181 +- VF610_PAD_PTE27__GPIO_132 0x1181 +- VF610_PAD_PTE13__GPIO_118 0x1181 +- VF610_PAD_PTE21__GPIO_126 0x1181 +- VF610_PAD_PTE22__GPIO_127 0x1181 +- /* EE_5V_EN */ +- VF610_PAD_PTE18__GPIO_123 0x1183 +- /* EE_5V_OC_N */ +- VF610_PAD_PTE25__GPIO_130 0x1181 +- >; +- }; +- +- pinctrl_can0: can0grp { +- fsl,pins = < +- VF610_PAD_PTB14__CAN0_RX 0x1181 +- VF610_PAD_PTB15__CAN0_TX 0x1182 +- >; +- }; +- +- pinctrl_can1: can1grp { +- fsl,pins = < +- VF610_PAD_PTB16__CAN1_RX 0x1181 +- VF610_PAD_PTB17__CAN1_TX 0x1182 +- >; +- }; +- +- pinctrl_dspi0: dspi0grp { +- fsl,pins = < +- VF610_PAD_PTB18__DSPI0_CS1 0x1182 +- VF610_PAD_PTB19__DSPI0_CS0 0x1182 +- VF610_PAD_PTB20__DSPI0_SIN 0x1181 +- VF610_PAD_PTB21__DSPI0_SOUT 0x1182 +- VF610_PAD_PTB22__DSPI0_SCK 0x1182 +- >; +- }; +- +- pinctrl_dspi3: dspi3grp { +- fsl,pins = < +- VF610_PAD_PTD10__DSPI3_CS0 0x1181 +- VF610_PAD_PTD11__DSPI3_SIN 0x1181 +- VF610_PAD_PTD12__DSPI3_SOUT 0x1182 +- VF610_PAD_PTD13__DSPI3_SCK 0x1181 +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- VF610_PAD_PTA24__ESDHC1_CLK 0x31ef +- VF610_PAD_PTA25__ESDHC1_CMD 0x31ef +- VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef +- VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef +- VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef +- VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef +- VF610_PAD_PTB28__GPIO_98 0x219d +- >; +- }; +- +- pinctrl_fec0: fec0grp { +- fsl,pins = < +- VF610_PAD_PTA6__RMII_CLKIN 0x30dd +- VF610_PAD_PTC0__ENET_RMII0_MDC 0x30de +- VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30df +- VF610_PAD_PTC2__ENET_RMII0_CRS 0x30dd +- VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30dd +- VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30dd +- VF610_PAD_PTC5__ENET_RMII0_RXER 0x30dd +- VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30de +- VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30de +- VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30de +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- VF610_PAD_PTC9__ENET_RMII1_MDC 0x30de +- VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30df +- VF610_PAD_PTC11__ENET_RMII1_CRS 0x30dd +- VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30dd +- VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30dd +- VF610_PAD_PTC14__ENET_RMII1_RXER 0x30dd +- VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30de +- VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30de +- VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30de +- >; +- }; +- +- pinctrl_gpio_leds: gpioledsgrp { +- fsl,pins = < +- /* Heart bit LED */ +- VF610_PAD_PTE12__GPIO_117 0x1183 +- /* LEDS */ +- VF610_PAD_PTE15__GPIO_120 0x1183 +- VF610_PAD_PTA12__GPIO_5 0x1183 +- VF610_PAD_PTA16__GPIO_6 0x1183 +- VF610_PAD_PTE9__GPIO_114 0x1183 +- VF610_PAD_PTE20__GPIO_125 0x1183 +- VF610_PAD_PTE23__GPIO_128 0x1183 +- VF610_PAD_PTE16__GPIO_121 0x1183 +- >; +- }; +- +- pinctrl_gpio_spi: pinctrl-gpio-spi { +- fsl,pins = < +- VF610_PAD_PTB18__GPIO_40 0x1183 +- VF610_PAD_PTD10__GPIO_89 0x1183 +- VF610_PAD_PTD12__GPIO_91 0x1183 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- VF610_PAD_PTA22__I2C2_SCL 0x34df +- VF610_PAD_PTA23__I2C2_SDA 0x34df +- >; +- }; +- +- pinctrl_nfc: nfcgrp { +- fsl,pins = < +- VF610_PAD_PTD23__NF_IO7 0x28df +- VF610_PAD_PTD22__NF_IO6 0x28df +- VF610_PAD_PTD21__NF_IO5 0x28df +- VF610_PAD_PTD20__NF_IO4 0x28df +- VF610_PAD_PTD19__NF_IO3 0x28df +- VF610_PAD_PTD18__NF_IO2 0x28df +- VF610_PAD_PTD17__NF_IO1 0x28df +- VF610_PAD_PTD16__NF_IO0 0x28df +- VF610_PAD_PTB24__NF_WE_B 0x28c2 +- VF610_PAD_PTB25__NF_CE0_B 0x28c2 +- VF610_PAD_PTB27__NF_RE_B 0x28c2 +- VF610_PAD_PTC26__NF_RB_B 0x283d +- VF610_PAD_PTC27__NF_ALE 0x28c2 +- VF610_PAD_PTC28__NF_CLE 0x28c2 +- >; +- }; +- +- pinctrl_qspi0: qspi0grp { +- fsl,pins = < +- VF610_PAD_PTD0__QSPI0_A_QSCK 0x397f +- VF610_PAD_PTD1__QSPI0_A_CS0 0x397f +- VF610_PAD_PTD2__QSPI0_A_DATA3 0x397f +- VF610_PAD_PTD3__QSPI0_A_DATA2 0x397f +- VF610_PAD_PTD4__QSPI0_A_DATA1 0x397f +- VF610_PAD_PTD5__QSPI0_A_DATA0 0x397f +- VF610_PAD_PTD7__QSPI0_B_QSCK 0x397f +- VF610_PAD_PTD8__QSPI0_B_CS0 0x397f +- VF610_PAD_PTD11__QSPI0_B_DATA1 0x397f +- VF610_PAD_PTD12__QSPI0_B_DATA0 0x397f +- >; +- }; +- +- pinctrl_uart0: uart0grp { +- fsl,pins = < +- VF610_PAD_PTB10__UART0_TX 0x21a2 +- VF610_PAD_PTB11__UART0_RX 0x21a1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- VF610_PAD_PTB4__UART1_TX 0x21a2 +- VF610_PAD_PTB5__UART1_RX 0x21a1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- VF610_PAD_PTB6__UART2_TX 0x21a2 +- VF610_PAD_PTB7__UART2_RX 0x21a1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- VF610_PAD_PTA20__UART3_TX 0x21a2 +- VF610_PAD_PTA21__UART3_RX 0x21a1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf610-colibri-eval-v3.dts b/scripts/dtc/include-prefixes/arm/vf610-colibri-eval-v3.dts +deleted file mode 100644 +index fb661e8a2dc6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf610-colibri-eval-v3.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2014-2020 Toradex +- */ +- +-/dts-v1/; +-#include "vf610-colibri.dtsi" +-#include "vf-colibri-eval-v3.dtsi" +- +-/ { +- model = "Toradex Colibri VF61 on Colibri Evaluation Board"; +- compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf610-colibri.dtsi b/scripts/dtc/include-prefixes/arm/vf610-colibri.dtsi +deleted file mode 100644 +index 607cec2df861..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf610-colibri.dtsi ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2014-2020 Toradex +- */ +- +-#include "vf610.dtsi" +-#include "vf-colibri.dtsi" +- +-/ { +- model = "Toradex Colibri VF61 COM"; +- compatible = "toradex,vf610-colibri_vf61", "fsl,vf610"; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; +- }; +-}; +- +-&nfc { +- assigned-clocks = <&clks VF610_CLK_NFC>; +- assigned-clock-rates = <50000000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf610-cosmic.dts b/scripts/dtc/include-prefixes/arm/vf610-cosmic.dts +deleted file mode 100644 +index 703f375d7e24..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf610-cosmic.dts ++++ /dev/null +@@ -1,90 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- * Copyright 2013 Linaro Limited +- */ +- +-/dts-v1/; +-#include "vf610.dtsi" +- +-/ { +- model = "PHYTEC Cosmic/Cosmic+ Board"; +- compatible = "phytec,vf610-cosmic", "fsl,vf610"; +- +- chosen { +- bootargs = "console=ttyLP1,115200"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; +- }; +- +- enet_ext: enet_ext { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- }; +-}; +- +-&clks { +- clocks = <&sxosc>, <&fxosc>, <&enet_ext>; +- clock-names = "sxosc", "fxosc", "enet_ext"; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&fec1 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- status = "okay"; +-}; +- +-&iomuxc { +- vf610-cosmic { +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- VF610_PAD_PTA24__ESDHC1_CLK 0x31ef +- VF610_PAD_PTA25__ESDHC1_CMD 0x31ef +- VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef +- VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef +- VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef +- VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef +- VF610_PAD_PTB28__GPIO_98 0x219d +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 +- VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 +- VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 +- VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 +- VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 +- VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 +- VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 +- VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 +- VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- VF610_PAD_PTB4__UART1_TX 0x21a2 +- VF610_PAD_PTB5__UART1_RX 0x21a1 +- >; +- }; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf610-pinfunc.h b/scripts/dtc/include-prefixes/arm/vf610-pinfunc.h +deleted file mode 100644 +index f1e5a7cf58a9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf610-pinfunc.h ++++ /dev/null +@@ -1,806 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __DTS_VF610_PINFUNC_H +-#define __DTS_VF610_PINFUNC_H +- +-/* +- * The pin function ID for VF610 is a tuple of: +- * +- */ +- +-#define ALT0 0x0 +-#define ALT1 0x1 +-#define ALT2 0x2 +-#define ALT3 0x3 +-#define ALT4 0x4 +-#define ALT5 0x5 +-#define ALT6 0x6 +-#define ALT7 0x7 +- +- +-#define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 +-#define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 +-#define VF610_PAD_PTA6__RMII_CLKIN 0x000 0x2F0 ALT2 0x0 +-#define VF610_PAD_PTA6__DCU1_TCON11 0x000 0x000 ALT4 0x0 +-#define VF610_PAD_PTA6__DCU1_R2 0x000 0x000 ALT7 0x0 +-#define VF610_PAD_PTA8__GPIO_1 0x004 0x000 ALT0 0x0 +-#define VF610_PAD_PTA8__TCLK 0x004 0x000 ALT1 0x0 +-#define VF610_PAD_PTA8__DCU0_R0 0x004 0x000 ALT4 0x0 +-#define VF610_PAD_PTA8__MLB_CLK 0x004 0x354 ALT7 0x0 +-#define VF610_PAD_PTA9__GPIO_2 0x008 0x000 ALT0 0x0 +-#define VF610_PAD_PTA9__TDI 0x008 0x000 ALT1 0x0 +-#define VF610_PAD_PTA9__RMII_CLKOUT 0x008 0x000 ALT2 0x0 +-#define VF610_PAD_PTA9__RMII_CLKIN 0x008 0x2F0 ALT3 0x1 +-#define VF610_PAD_PTA9__DCU0_R1 0x008 0x000 ALT4 0x0 +-#define VF610_PAD_PTA9__WDOG_B 0x008 0x000 ALT6 0x0 +-#define VF610_PAD_PTA10__GPIO_3 0x00C 0x000 ALT0 0x0 +-#define VF610_PAD_PTA10__TDO 0x00C 0x000 ALT1 0x0 +-#define VF610_PAD_PTA10__EXT_AUDIO_MCLK 0x00C 0x2EC ALT2 0x0 +-#define VF610_PAD_PTA10__DCU0_G0 0x00C 0x000 ALT4 0x0 +-#define VF610_PAD_PTA10__ENET_TS_CLKIN 0x00C 0x2F4 ALT6 0x0 +-#define VF610_PAD_PTA10__MLB_SIGNAL 0x00C 0x35C ALT7 0x0 +-#define VF610_PAD_PTA11__GPIO_4 0x010 0x000 ALT0 0x0 +-#define VF610_PAD_PTA11__TMS 0x010 0x000 ALT1 0x0 +-#define VF610_PAD_PTA11__DCU0_G1 0x010 0x000 ALT4 0x0 +-#define VF610_PAD_PTA11__MLB_DATA 0x010 0x358 ALT7 0x0 +-#define VF610_PAD_PTA12__GPIO_5 0x014 0x000 ALT0 0x0 +-#define VF610_PAD_PTA12__TRACECK 0x014 0x000 ALT1 0x0 +-#define VF610_PAD_PTA12__EXT_AUDIO_MCLK 0x014 0x2EC ALT2 0x1 +-#define VF610_PAD_PTA12__VIU_DATA13 0x014 0x000 ALT6 0x0 +-#define VF610_PAD_PTA12__I2C0_SCL 0x014 0x33C ALT7 0x0 +-#define VF610_PAD_PTA16__GPIO_6 0x018 0x000 ALT0 0x0 +-#define VF610_PAD_PTA16__TRACED0 0x018 0x000 ALT1 0x0 +-#define VF610_PAD_PTA16__USB0_VBUS_EN 0x018 0x000 ALT2 0x0 +-#define VF610_PAD_PTA16__ADC1_SE0 0x018 0x000 ALT3 0x0 +-#define VF610_PAD_PTA16__LCD29 0x018 0x000 ALT4 0x0 +-#define VF610_PAD_PTA16__SAI2_TX_BCLK 0x018 0x370 ALT5 0x0 +-#define VF610_PAD_PTA16__VIU_DATA14 0x018 0x000 ALT6 0x0 +-#define VF610_PAD_PTA16__I2C0_SDA 0x018 0x340 ALT7 0x0 +-#define VF610_PAD_PTA17__GPIO_7 0x01C 0x000 ALT0 0x0 +-#define VF610_PAD_PTA17__TRACED1 0x01C 0x000 ALT1 0x0 +-#define VF610_PAD_PTA17__USB0_VBUS_OC 0x01C 0x000 ALT2 0x0 +-#define VF610_PAD_PTA17__ADC1_SE1 0x01C 0x000 ALT3 0x0 +-#define VF610_PAD_PTA17__LCD30 0x01C 0x000 ALT4 0x0 +-#define VF610_PAD_PTA17__USB0_SOF_PULSE 0x01C 0x000 ALT5 0x0 +-#define VF610_PAD_PTA17__VIU_DATA15 0x01C 0x000 ALT6 0x0 +-#define VF610_PAD_PTA17__I2C1_SCL 0x01C 0x344 ALT7 0x0 +-#define VF610_PAD_PTA18__GPIO_8 0x020 0x000 ALT0 0x0 +-#define VF610_PAD_PTA18__TRACED2 0x020 0x000 ALT1 0x0 +-#define VF610_PAD_PTA18__ADC0_SE0 0x020 0x000 ALT2 0x0 +-#define VF610_PAD_PTA18__FTM1_QD_PHA 0x020 0x334 ALT3 0x0 +-#define VF610_PAD_PTA18__LCD31 0x020 0x000 ALT4 0x0 +-#define VF610_PAD_PTA18__SAI2_TX_DATA 0x020 0x000 ALT5 0x0 +-#define VF610_PAD_PTA18__VIU_DATA16 0x020 0x000 ALT6 0x0 +-#define VF610_PAD_PTA18__I2C1_SDA 0x020 0x348 ALT7 0x0 +-#define VF610_PAD_PTA19__GPIO_9 0x024 0x000 ALT0 0x0 +-#define VF610_PAD_PTA19__TRACED3 0x024 0x000 ALT1 0x0 +-#define VF610_PAD_PTA19__ADC0_SE1 0x024 0x000 ALT2 0x0 +-#define VF610_PAD_PTA19__FTM1_QD_PHB 0x024 0x338 ALT3 0x0 +-#define VF610_PAD_PTA19__LCD32 0x024 0x000 ALT4 0x0 +-#define VF610_PAD_PTA19__SAI2_TX_SYNC 0x024 0x000 ALT5 0x0 +-#define VF610_PAD_PTA19__VIU_DATA17 0x024 0x000 ALT6 0x0 +-#define VF610_PAD_PTA19__QSPI1_A_QSCK 0x024 0x374 ALT7 0x0 +-#define VF610_PAD_PTA20__GPIO_10 0x028 0x000 ALT0 0x0 +-#define VF610_PAD_PTA20__TRACED4 0x028 0x000 ALT1 0x0 +-#define VF610_PAD_PTA20__LCD33 0x028 0x000 ALT4 0x0 +-#define VF610_PAD_PTA20__UART3_TX 0x028 0x394 ALT6 0x0 +-#define VF610_PAD_PTA20__DCU1_HSYNC 0x028 0x000 ALT7 0x0 +-#define VF610_PAD_PTA21__GPIO_11 0x02C 0x000 ALT0 0x0 +-#define VF610_PAD_PTA21__TRACED5 0x02C 0x000 ALT1 0x0 +-#define VF610_PAD_PTA21__SAI2_RX_BCLK 0x02C 0x364 ALT5 0x0 +-#define VF610_PAD_PTA21__UART3_RX 0x02C 0x390 ALT6 0x0 +-#define VF610_PAD_PTA21__DCU1_VSYNC 0x02C 0x000 ALT7 0x0 +-#define VF610_PAD_PTA22__GPIO_12 0x030 0x000 ALT0 0x0 +-#define VF610_PAD_PTA22__TRACED6 0x030 0x000 ALT1 0x0 +-#define VF610_PAD_PTA22__SAI2_RX_DATA 0x030 0x368 ALT5 0x0 +-#define VF610_PAD_PTA22__I2C2_SCL 0x030 0x34C ALT6 0x0 +-#define VF610_PAD_PTA22__DCU1_TAG 0x030 0x000 ALT7 0x0 +-#define VF610_PAD_PTA23__GPIO_13 0x034 0x000 ALT0 0x0 +-#define VF610_PAD_PTA23__TRACED7 0x034 0x000 ALT1 0x0 +-#define VF610_PAD_PTA23__SAI2_RX_SYNC 0x034 0x36C ALT5 0x0 +-#define VF610_PAD_PTA23__I2C2_SDA 0x034 0x350 ALT6 0x0 +-#define VF610_PAD_PTA23__DCU1_DE 0x034 0x000 ALT7 0x0 +-#define VF610_PAD_PTA24__GPIO_14 0x038 0x000 ALT0 0x0 +-#define VF610_PAD_PTA24__TRACED8 0x038 0x000 ALT1 0x0 +-#define VF610_PAD_PTA24__USB1_VBUS_EN 0x038 0x000 ALT2 0x0 +-#define VF610_PAD_PTA24__ESDHC1_CLK 0x038 0x000 ALT5 0x0 +-#define VF610_PAD_PTA24__DCU1_TCON4 0x038 0x000 ALT6 0x0 +-#define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL 0x038 0x000 ALT7 0x0 +-#define VF610_PAD_PTA25__GPIO_15 0x03C 0x000 ALT0 0x0 +-#define VF610_PAD_PTA25__TRACED9 0x03C 0x000 ALT1 0x0 +-#define VF610_PAD_PTA25__USB1_VBUS_OC 0x03C 0x000 ALT2 0x0 +-#define VF610_PAD_PTA25__ESDHC1_CMD 0x03C 0x000 ALT5 0x0 +-#define VF610_PAD_PTA25__DCU1_TCON5 0x03C 0x000 ALT6 0x0 +-#define VF610_PAD_PTA26__GPIO_16 0x040 0x000 ALT0 0x0 +-#define VF610_PAD_PTA26__TRACED10 0x040 0x000 ALT1 0x0 +-#define VF610_PAD_PTA26__SAI3_TX_BCLK 0x040 0x000 ALT2 0x0 +-#define VF610_PAD_PTA26__ESDHC1_DAT0 0x040 0x000 ALT5 0x0 +-#define VF610_PAD_PTA26__DCU1_TCON6 0x040 0x000 ALT6 0x0 +-#define VF610_PAD_PTA27__GPIO_17 0x044 0x000 ALT0 0x0 +-#define VF610_PAD_PTA27__TRACED11 0x044 0x000 ALT1 0x0 +-#define VF610_PAD_PTA27__SAI3_RX_BCLK 0x044 0x000 ALT2 0x0 +-#define VF610_PAD_PTA27__ESDHC1_DAT1 0x044 0x000 ALT5 0x0 +-#define VF610_PAD_PTA27__DCU1_TCON7 0x044 0x000 ALT6 0x0 +-#define VF610_PAD_PTA28__GPIO_18 0x048 0x000 ALT0 0x0 +-#define VF610_PAD_PTA28__TRACED12 0x048 0x000 ALT1 0x0 +-#define VF610_PAD_PTA28__SAI3_RX_DATA 0x048 0x000 ALT2 0x0 +-#define VF610_PAD_PTA28__ENET1_1588_TMR0 0x048 0x000 ALT3 0x0 +-#define VF610_PAD_PTA28__UART4_TX 0x048 0x000 ALT4 0x0 +-#define VF610_PAD_PTA28__ESDHC1_DATA2 0x048 0x000 ALT5 0x0 +-#define VF610_PAD_PTA28__DCU1_TCON8 0x048 0x000 ALT6 0x0 +-#define VF610_PAD_PTA29__GPIO_19 0x04C 0x000 ALT0 0x0 +-#define VF610_PAD_PTA29__TRACED13 0x04C 0x000 ALT1 0x0 +-#define VF610_PAD_PTA29__SAI3_TX_DATA 0x04C 0x000 ALT2 0x0 +-#define VF610_PAD_PTA29__ENET1_1588_TMR1 0x04C 0x000 ALT3 0x0 +-#define VF610_PAD_PTA29__UART4_RX 0x04C 0x000 ALT4 0x0 +-#define VF610_PAD_PTA29__ESDHC1_DAT3 0x04C 0x000 ALT5 0x0 +-#define VF610_PAD_PTA29__DCU1_TCON9 0x04C 0x000 ALT6 0x0 +-#define VF610_PAD_PTA30__GPIO_20 0x050 0x000 ALT0 0x0 +-#define VF610_PAD_PTA30__TRACED14 0x050 0x000 ALT1 0x0 +-#define VF610_PAD_PTA30__SAI3_RX_SYNC 0x050 0x000 ALT2 0x0 +-#define VF610_PAD_PTA30__ENET1_1588_TMR2 0x050 0x000 ALT3 0x0 +-#define VF610_PAD_PTA30__UART4_RTS 0x050 0x000 ALT4 0x0 +-#define VF610_PAD_PTA30__I2C3_SCL 0x050 0x000 ALT5 0x0 +-#define VF610_PAD_PTA30__UART3_TX 0x050 0x394 ALT7 0x1 +-#define VF610_PAD_PTA31__GPIO_21 0x054 0x000 ALT0 0x0 +-#define VF610_PAD_PTA31__TRACED15 0x054 0x000 ALT1 0x0 +-#define VF610_PAD_PTA31__SAI3_TX_SYNC 0x054 0x000 ALT2 0x0 +-#define VF610_PAD_PTA31__ENET1_1588_TMR3 0x054 0x000 ALT3 0x0 +-#define VF610_PAD_PTA31__UART4_CTS 0x054 0x000 ALT4 0x0 +-#define VF610_PAD_PTA31__I2C3_SDA 0x054 0x000 ALT5 0x0 +-#define VF610_PAD_PTA31__UART3_RX 0x054 0x390 ALT7 0x1 +-#define VF610_PAD_PTB0__GPIO_22 0x058 0x000 ALT0 0x0 +-#define VF610_PAD_PTB0__FTM0_CH0 0x058 0x000 ALT1 0x0 +-#define VF610_PAD_PTB0__ADC0_SE2 0x058 0x000 ALT2 0x0 +-#define VF610_PAD_PTB0__TRACE_CTL 0x058 0x000 ALT3 0x0 +-#define VF610_PAD_PTB0__LCD34 0x058 0x000 ALT4 0x0 +-#define VF610_PAD_PTB0__SAI2_RX_BCLK 0x058 0x364 ALT5 0x1 +-#define VF610_PAD_PTB0__VIU_DATA18 0x058 0x000 ALT6 0x0 +-#define VF610_PAD_PTB0__QSPI1_A_QPCS0 0x058 0x000 ALT7 0x0 +-#define VF610_PAD_PTB1__GPIO_23 0x05C 0x000 ALT0 0x0 +-#define VF610_PAD_PTB1__FTM0_CH1 0x05C 0x000 ALT1 0x0 +-#define VF610_PAD_PTB1__ADC0_SE3 0x05C 0x000 ALT2 0x0 +-#define VF610_PAD_PTB1__SRC_RCON30 0x05C 0x000 ALT3 0x0 +-#define VF610_PAD_PTB1__LCD35 0x05C 0x000 ALT4 0x0 +-#define VF610_PAD_PTB1__SAI2_RX_DATA 0x05C 0x368 ALT5 0x1 +-#define VF610_PAD_PTB1__VIU_DATA19 0x05C 0x000 ALT6 0x0 +-#define VF610_PAD_PTB1__QSPI1_A_DATA3 0x05C 0x000 ALT7 0x0 +-#define VF610_PAD_PTB2__GPIO_24 0x060 0x000 ALT0 0x0 +-#define VF610_PAD_PTB2__FTM0_CH2 0x060 0x000 ALT1 0x0 +-#define VF610_PAD_PTB2__ADC1_SE2 0x060 0x000 ALT2 0x0 +-#define VF610_PAD_PTB2__SRC_RCON31 0x060 0x000 ALT3 0x0 +-#define VF610_PAD_PTB2__LCD36 0x060 0x000 ALT4 0x0 +-#define VF610_PAD_PTB2__SAI2_RX_SYNC 0x060 0x36C ALT5 0x1 +-#define VF610_PAD_PTB2__VIDEO_IN0_DATA20 0x060 0x000 ALT6 0x0 +-#define VF610_PAD_PTB2__QSPI1_A_DATA2 0x060 0x000 ALT7 0x0 +-#define VF610_PAD_PTB3__GPIO_25 0x064 0x000 ALT0 0x0 +-#define VF610_PAD_PTB3__FTM0_CH3 0x064 0x000 ALT1 0x0 +-#define VF610_PAD_PTB3__ADC1_SE3 0x064 0x000 ALT2 0x0 +-#define VF610_PAD_PTB3__PDB_EXTRIG 0x064 0x000 ALT3 0x0 +-#define VF610_PAD_PTB3__LCD37 0x064 0x000 ALT4 0x0 +-#define VF610_PAD_PTB3__VIU_DATA21 0x064 0x000 ALT6 0x0 +-#define VF610_PAD_PTB3__QSPI1_A_DATA1 0x064 0x000 ALT7 0x0 +-#define VF610_PAD_PTB4__GPIO_26 0x068 0x000 ALT0 0x0 +-#define VF610_PAD_PTB4__FTM0_CH4 0x068 0x000 ALT1 0x0 +-#define VF610_PAD_PTB4__UART1_TX 0x068 0x380 ALT2 0x0 +-#define VF610_PAD_PTB4__ADC0_SE4 0x068 0x000 ALT3 0x0 +-#define VF610_PAD_PTB4__LCD38 0x068 0x000 ALT4 0x0 +-#define VF610_PAD_PTB4__VIU_FID 0x068 0x3A8 ALT5 0x0 +-#define VF610_PAD_PTB4__VIU_DATA22 0x068 0x000 ALT6 0x0 +-#define VF610_PAD_PTB4__QSPI1_A_DATA0 0x068 0x000 ALT7 0x0 +-#define VF610_PAD_PTB5__GPIO_27 0x06C 0x000 ALT0 0x0 +-#define VF610_PAD_PTB5__FTM0_CH5 0x06C 0x000 ALT1 0x0 +-#define VF610_PAD_PTB5__UART1_RX 0x06C 0x37C ALT2 0x0 +-#define VF610_PAD_PTB5__ADC1_SE4 0x06C 0x000 ALT3 0x0 +-#define VF610_PAD_PTB5__LCD39 0x06C 0x000 ALT4 0x0 +-#define VF610_PAD_PTB5__VIU_DE 0x06C 0x3A4 ALT5 0x0 +-#define VF610_PAD_PTB5__QSPI1_A_DQS 0x06C 0x000 ALT7 0x0 +-#define VF610_PAD_PTB6__GPIO_28 0x070 0x000 ALT0 0x0 +-#define VF610_PAD_PTB6__FTM0_CH6 0x070 0x000 ALT1 0x0 +-#define VF610_PAD_PTB6__UART1_RTS 0x070 0x000 ALT2 0x0 +-#define VF610_PAD_PTB6__QSPI0_QPCS1_A 0x070 0x000 ALT3 0x0 +-#define VF610_PAD_PTB6__LCD_LCD40 0x070 0x000 ALT4 0x0 +-#define VF610_PAD_PTB6__FB_CLKOUT 0x070 0x000 ALT5 0x0 +-#define VF610_PAD_PTB6__VIU_HSYNC 0x070 0x000 ALT6 0x0 +-#define VF610_PAD_PTB6__UART2_TX 0x070 0x38C ALT7 0x0 +-#define VF610_PAD_PTB7__GPIO_29 0x074 0x000 ALT0 0x0 +-#define VF610_PAD_PTB7__FTM0_CH7 0x074 0x000 ALT1 0x0 +-#define VF610_PAD_PTB7__UART1_CTS 0x074 0x378 ALT2 0x0 +-#define VF610_PAD_PTB7__QSPI0_B_QPCS1 0x074 0x000 ALT3 0x0 +-#define VF610_PAD_PTB7__LCD41 0x074 0x000 ALT4 0x0 +-#define VF610_PAD_PTB7__VIU_VSYNC 0x074 0x000 ALT6 0x0 +-#define VF610_PAD_PTB7__UART2_RX 0x074 0x388 ALT7 0x0 +-#define VF610_PAD_PTB8__GPIO_30 0x078 0x000 ALT0 0x0 +-#define VF610_PAD_PTB8__FTM1_CH0 0x078 0x32C ALT1 0x0 +-#define VF610_PAD_PTB8__FTM1_QD_PHA 0x078 0x334 ALT3 0x1 +-#define VF610_PAD_PTB8__VIU_DE 0x078 0x3A4 ALT5 0x1 +-#define VF610_PAD_PTB8__DCU1_R6 0x078 0x000 ALT7 0x0 +-#define VF610_PAD_PTB9__GPIO_31 0x07C 0x000 ALT0 0x0 +-#define VF610_PAD_PTB9__FTM1_CH1 0x07C 0x330 ALT1 0x0 +-#define VF610_PAD_PTB9__FTM1_QD_PHB 0x07C 0x338 ALT3 0x1 +-#define VF610_PAD_PTB9__DCU1_R7 0x07C 0x000 ALT7 0x0 +-#define VF610_PAD_PTB10__GPIO_32 0x080 0x000 ALT0 0x0 +-#define VF610_PAD_PTB10__UART0_TX 0x080 0x000 ALT1 0x0 +-#define VF610_PAD_PTB10__DCU0_TCON4 0x080 0x000 ALT4 0x0 +-#define VF610_PAD_PTB10__VIU_DE 0x080 0x3A4 ALT5 0x2 +-#define VF610_PAD_PTB10__CKO1 0x080 0x000 ALT6 0x0 +-#define VF610_PAD_PTB10__ENET_TS_CLKIN 0x080 0x2F4 ALT7 0x1 +-#define VF610_PAD_PTB11__GPIO_33 0x084 0x000 ALT0 0x0 +-#define VF610_PAD_PTB11__UART0_RX 0x084 0x000 ALT1 0x0 +-#define VF610_PAD_PTB11__DCU0_TCON5 0x084 0x000 ALT4 0x0 +-#define VF610_PAD_PTB11__SNVS_ALARM_OUT_B 0x084 0x000 ALT5 0x0 +-#define VF610_PAD_PTB11__CKO2 0x084 0x000 ALT6 0x0 +-#define VF610_PAD_PTB11_ENET0_1588_TMR0 0x084 0x304 ALT7 0x0 +-#define VF610_PAD_PTB12__GPIO_34 0x088 0x000 ALT0 0x0 +-#define VF610_PAD_PTB12__UART0_RTS 0x088 0x000 ALT1 0x0 +-#define VF610_PAD_PTB12__DSPI0_CS5 0x088 0x000 ALT3 0x0 +-#define VF610_PAD_PTB12__DCU0_TCON6 0x088 0x000 ALT4 0x0 +-#define VF610_PAD_PTB12__FB_AD1 0x088 0x000 ALT5 0x0 +-#define VF610_PAD_PTB12__NMI 0x088 0x000 ALT6 0x0 +-#define VF610_PAD_PTB12__ENET0_1588_TMR1 0x088 0x308 ALT7 0x0 +-#define VF610_PAD_PTB13__GPIO_35 0x08C 0x000 ALT0 0x0 +-#define VF610_PAD_PTB13__UART0_CTS 0x08C 0x000 ALT1 0x0 +-#define VF610_PAD_PTB13__DSPI0_CS4 0x08C 0x000 ALT3 0x0 +-#define VF610_PAD_PTB13__DCU0_TCON7 0x08C 0x000 ALT4 0x0 +-#define VF610_PAD_PTB13__FB_AD0 0x08C 0x000 ALT5 0x0 +-#define VF610_PAD_PTB13__TRACE_CTL 0x08C 0x000 ALT6 0x0 +-#define VF610_PAD_PTB14__GPIO_36 0x090 0x000 ALT0 0x0 +-#define VF610_PAD_PTB14__CAN0_RX 0x090 0x000 ALT1 0x0 +-#define VF610_PAD_PTB14__I2C0_SCL 0x090 0x33C ALT2 0x1 +-#define VF610_PAD_PTB14__DCU0_TCON8 0x090 0x000 ALT4 0x0 +-#define VF610_PAD_PTB14__DCU1_PCLK 0x090 0x000 ALT7 0x0 +-#define VF610_PAD_PTB15__GPIO_37 0x094 0x000 ALT0 0x0 +-#define VF610_PAD_PTB15__CAN0_TX 0x094 0x000 ALT1 0x0 +-#define VF610_PAD_PTB15__I2C0_SDA 0x094 0x340 ALT2 0x1 +-#define VF610_PAD_PTB15__DCU0_TCON9 0x094 0x000 ALT4 0x0 +-#define VF610_PAD_PTB15__VIU_PIX_CLK 0x094 0x3AC ALT7 0x0 +-#define VF610_PAD_PTB16__GPIO_38 0x098 0x000 ALT0 0x0 +-#define VF610_PAD_PTB16__CAN1_RX 0x098 0x000 ALT1 0x0 +-#define VF610_PAD_PTB16__I2C1_SCL 0x098 0x344 ALT2 0x1 +-#define VF610_PAD_PTB16__DCU0_TCON10 0x098 0x000 ALT4 0x0 +-#define VF610_PAD_PTB17__GPIO_39 0x09C 0x000 ALT0 0x0 +-#define VF610_PAD_PTB17__CAN1_TX 0x09C 0x000 ALT1 0x0 +-#define VF610_PAD_PTB17__I2C1_SDA 0x09C 0x348 ALT2 0x1 +-#define VF610_PAD_PTB17__DCU0_TCON11 0x09C 0x000 ALT4 0x0 +-#define VF610_PAD_PTB18__GPIO_40 0x0A0 0x000 ALT0 0x0 +-#define VF610_PAD_PTB18__DSPI0_CS1 0x0A0 0x000 ALT1 0x0 +-#define VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x0A0 0x2EC ALT2 0x2 +-#define VF610_PAD_PTB18__VIU_DATA9 0x0A0 0x000 ALT6 0x0 +-#define VF610_PAD_PTB19__GPIO_41 0x0A4 0x000 ALT0 0x0 +-#define VF610_PAD_PTB19__DSPI0_CS0 0x0A4 0x000 ALT1 0x0 +-#define VF610_PAD_PTB19__VIU_DATA10 0x0A4 0x000 ALT6 0x0 +-#define VF610_PAD_PTB20__GPIO_42 0x0A8 0x000 ALT0 0x0 +-#define VF610_PAD_PTB20__DSPI0_SIN 0x0A8 0x000 ALT1 0x0 +-#define VF610_PAD_PTB20__LCD42 0x0A8 0x000 ALT4 0x0 +-#define VF610_PAD_PTB20__VIU_DATA11 0x0A8 0x000 ALT6 0x0 +-#define VF610_PAD_PTB21__GPIO_43 0x0AC 0x000 ALT0 0x0 +-#define VF610_PAD_PTB21__DSPI0_SOUT 0x0AC 0x000 ALT1 0x0 +-#define VF610_PAD_PTB21__LCD43 0x0AC 0x000 ALT4 0x0 +-#define VF610_PAD_PTB21__VIU_DATA12 0x0AC 0x000 ALT6 0x0 +-#define VF610_PAD_PTB21__DCU1_PCLK 0x0AC 0x000 ALT7 0x0 +-#define VF610_PAD_PTB22__GPIO_44 0x0B0 0x000 ALT0 0x0 +-#define VF610_PAD_PTB22__DSPI0_SCK 0x0B0 0x000 ALT1 0x0 +-#define VF610_PAD_PTB22__VLCD 0x0B0 0x000 ALT4 0x0 +-#define VF610_PAD_PTB22__VIU_FID 0x0B0 0x3A8 ALT5 0x1 +-#define VF610_PAD_PTC0__GPIO_45 0x0B4 0x000 ALT0 0x0 +-#define VF610_PAD_PTC0__ENET_RMII0_MDC 0x0B4 0x000 ALT1 0x0 +-#define VF610_PAD_PTC0__FTM1_CH0 0x0B4 0x32C ALT2 0x1 +-#define VF610_PAD_PTC0__DSPI0_CS3 0x0B4 0x000 ALT3 0x0 +-#define VF610_PAD_PTC0__ESAI_SCKT 0x0B4 0x310 ALT4 0x0 +-#define VF610_PAD_PTC0__ESDHC0_CLK 0x0B4 0x000 ALT5 0x0 +-#define VF610_PAD_PTC0__VIU_DATA0 0x0B4 0x000 ALT6 0x0 +-#define VF610_PAD_PTC0__SRC_RCON18 0x0B4 0x398 ALT7 0x0 +-#define VF610_PAD_PTC1__GPIO_46 0x0B8 0x000 ALT0 0x0 +-#define VF610_PAD_PTC1__ENET_RMII0_MDIO 0x0B8 0x000 ALT1 0x0 +-#define VF610_PAD_PTC1__FTM1_CH1 0x0B8 0x330 ALT2 0x1 +-#define VF610_PAD_PTC1__DSPI0_CS2 0x0B8 0x000 ALT3 0x0 +-#define VF610_PAD_PTC1__ESAI_FST 0x0B8 0x30C ALT4 0x0 +-#define VF610_PAD_PTC1__ESDHC0_CMD 0x0B8 0x000 ALT5 0x0 +-#define VF610_PAD_PTC1__VIU_DATA1 0x0B8 0x000 ALT6 0x0 +-#define VF610_PAD_PTC1__SRC_RCON19 0x0B8 0x39C ALT7 0x0 +-#define VF610_PAD_PTC2__GPIO_47 0x0BC 0x000 ALT0 0x0 +-#define VF610_PAD_PTC2__ENET_RMII0_CRS 0x0BC 0x000 ALT1 0x0 +-#define VF610_PAD_PTC2__UART1_TX 0x0BC 0x380 ALT2 0x1 +-#define VF610_PAD_PTC2__ESAI_SDO0 0x0BC 0x314 ALT4 0x0 +-#define VF610_PAD_PTC2__ESDHC0_DAT0 0x0BC 0x000 ALT5 0x0 +-#define VF610_PAD_PTC2__VIU_DATA2 0x0BC 0x000 ALT6 0x0 +-#define VF610_PAD_PTC2__SRC_RCON20 0x0BC 0x3A0 ALT7 0x0 +-#define VF610_PAD_PTC3__GPIO_48 0x0C0 0x000 ALT0 0x0 +-#define VF610_PAD_PTC3__ENET_RMII0_RXD1 0x0C0 0x000 ALT1 0x0 +-#define VF610_PAD_PTC3__UART1_RX 0x0C0 0x37C ALT2 0x1 +-#define VF610_PAD_PTC3__ESAI_SDO1 0x0C0 0x318 ALT4 0x0 +-#define VF610_PAD_PTC3__ESDHC0_DAT1 0x0C0 0x000 ALT5 0x0 +-#define VF610_PAD_PTC3__VIU_DATA3 0x0C0 0x000 ALT6 0x0 +-#define VF610_PAD_PTC3__DCU0_R0 0x0C0 0x000 ALT7 0x0 +-#define VF610_PAD_PTC4__GPIO_49 0x0C4 0x000 ALT0 0x0 +-#define VF610_PAD_PTC4__ENET_RMII0_RXD0 0x0C4 0x000 ALT1 0x0 +-#define VF610_PAD_PTC4__UART1_RTS 0x0C4 0x000 ALT2 0x0 +-#define VF610_PAD_PTC4__DSPI1_CS1 0x0C4 0x000 ALT3 0x0 +-#define VF610_PAD_PTC4__ESAI_SDO2 0x0C4 0x31C ALT4 0x0 +-#define VF610_PAD_PTC4__ESDHC0_DAT2 0x0C4 0x000 ALT5 0x0 +-#define VF610_PAD_PTC4__VIU_DATA4 0x0C4 0x000 ALT6 0x0 +-#define VF610_PAD_PTC4__DCU0_R1 0x0C4 0x000 ALT7 0x0 +-#define VF610_PAD_PTC5__GPIO_50 0x0C8 0x000 ALT0 0x0 +-#define VF610_PAD_PTC5__ENET_RMII0_RXER 0x0C8 0x000 ALT1 0x0 +-#define VF610_PAD_PTC5__UART1_CTS 0x0C8 0x378 ALT2 0x1 +-#define VF610_PAD_PTC5__DSPI1_CS0 0x0C8 0x300 ALT3 0x0 +-#define VF610_PAD_PTC5__ESAI_SDO3 0x0C8 0x320 ALT4 0x0 +-#define VF610_PAD_PTC5__ESDHC0_DAT3 0x0C8 0x000 ALT5 0x0 +-#define VF610_PAD_PTC5__VIU_DATA5 0x0C8 0x000 ALT6 0x0 +-#define VF610_PAD_PTC5__DCU0_G0 0x0C8 0x000 ALT7 0x0 +-#define VF610_PAD_PTC6__GPIO_51 0x0CC 0x000 ALT0 0x0 +-#define VF610_PAD_PTC6__ENET_RMII0_TXD1 0x0CC 0x000 ALT1 0x0 +-#define VF610_PAD_PTC6__DSPI1_SIN 0x0CC 0x2FC ALT3 0x0 +-#define VF610_PAD_PTC6__ESAI_SDI0 0x0CC 0x328 ALT4 0x0 +-#define VF610_PAD_PTC6__ESDHC0_WP 0x0CC 0x000 ALT5 0x0 +-#define VF610_PAD_PTC6__VIU_DATA6 0x0CC 0x000 ALT6 0x0 +-#define VF610_PAD_PTC6__DCU0_G1 0x0CC 0x000 ALT7 0x0 +-#define VF610_PAD_PTC7__GPIO_52 0x0D0 0x000 ALT0 0x0 +-#define VF610_PAD_PTC7__ENET_RMII0_TXD0 0x0D0 0x000 ALT1 0x0 +-#define VF610_PAD_PTC7__DSPI1_SOUT 0x0D0 0x000 ALT3 0x0 +-#define VF610_PAD_PTC7__ESAI_SDI1 0x0D0 0x324 ALT4 0x0 +-#define VF610_PAD_PTC7__VIU_DATA7 0x0D0 0x000 ALT6 0x0 +-#define VF610_PAD_PTC7__DCU0_B0 0x0D0 0x000 ALT7 0x0 +-#define VF610_PAD_PTC8__GPIO_53 0x0D4 0x000 ALT0 0x0 +-#define VF610_PAD_PTC8__ENET_RMII0_TXEN 0x0D4 0x000 ALT1 0x0 +-#define VF610_PAD_PTC8__DSPI1_SCK 0x0D4 0x2F8 ALT3 0x0 +-#define VF610_PAD_PTC8__VIU_DATA8 0x0D4 0x000 ALT6 0x0 +-#define VF610_PAD_PTC8__DCU0_B1 0x0D4 0x000 ALT7 0x0 +-#define VF610_PAD_PTC9__GPIO_54 0x0D8 0x000 ALT0 0x0 +-#define VF610_PAD_PTC9__ENET_RMII1_MDC 0x0D8 0x000 ALT1 0x0 +-#define VF610_PAD_PTC9__ESAI_SCKT 0x0D8 0x310 ALT3 0x1 +-#define VF610_PAD_PTC9__MLB_CLK 0x0D8 0x354 ALT6 0x1 +-#define VF610_PAD_PTC9__DEBUG_OUT0 0x0D8 0x000 ALT7 0x0 +-#define VF610_PAD_PTC10__GPIO_55 0x0DC 0x000 ALT0 0x0 +-#define VF610_PAD_PTC10__ENET_RMII1_MDIO 0x0DC 0x000 ALT1 0x0 +-#define VF610_PAD_PTC10__ESAI_FST 0x0DC 0x30C ALT3 0x1 +-#define VF610_PAD_PTC10__MLB_SIGNAL 0x0DC 0x35C ALT6 0x1 +-#define VF610_PAD_PTC10__DEBUG_OUT1 0x0DC 0x000 ALT7 0x0 +-#define VF610_PAD_PTC11__GPIO_56 0x0E0 0x000 ALT0 0x0 +-#define VF610_PAD_PTC11__ENET_RMII1_CRS 0x0E0 0x000 ALT1 0x0 +-#define VF610_PAD_PTC11__ESAI_SDO0 0x0E0 0x314 ALT3 0x1 +-#define VF610_PAD_PTC11__MLB_DATA 0x0E0 0x358 ALT6 0x1 +-#define VF610_PAD_PTC11__DEBUG_OUT 0x0E0 0x000 ALT7 0x0 +-#define VF610_PAD_PTC12__GPIO_57 0x0E4 0x000 ALT0 0x0 +-#define VF610_PAD_PTC12__ENET_RMII1_RXD1 0x0E4 0x000 ALT1 0x0 +-#define VF610_PAD_PTC12__ESAI_SDO1 0x0E4 0x318 ALT3 0x1 +-#define VF610_PAD_PTC12__SAI2_TX_BCLK 0x0E4 0x370 ALT5 0x1 +-#define VF610_PAD_PTC12__DEBUG_OUT3 0x0E4 0x000 ALT7 0x0 +-#define VF610_PAD_PTC13__GPIO_58 0x0E8 0x000 ALT0 0x0 +-#define VF610_PAD_PTC13__ENET_RMII1_RXD0 0x0E8 0x000 ALT1 0x0 +-#define VF610_PAD_PTC13__ESAI_SDO2 0x0E8 0x31C ALT3 0x1 +-#define VF610_PAD_PTC13__SAI2_RX_BCLK 0x0E8 0x364 ALT5 0x2 +-#define VF610_PAD_PTC13__DEBUG_OUT4 0x0E8 0x000 ALT7 0x0 +-#define VF610_PAD_PTC14__GPIO_59 0x0EC 0x000 ALT0 0x0 +-#define VF610_PAD_PTC14__ENET_RMII1_RXER 0x0EC 0x000 ALT1 0x0 +-#define VF610_PAD_PTC14__ESAI_SDO3 0x0EC 0x320 ALT3 0x1 +-#define VF610_PAD_PTC14__UART5_TX 0x0EC 0x000 ALT4 0x0 +-#define VF610_PAD_PTC14__SAI2_RX_DATA 0x0EC 0x368 ALT5 0x2 +-#define VF610_PAD_PTC14__ADC0_SE6 0x0EC 0x000 ALT6 0x0 +-#define VF610_PAD_PTC14__DEBUG_OUT5 0x0EC 0x000 ALT7 0x0 +-#define VF610_PAD_PTC15__GPIO_60 0x0F0 0x000 ALT0 0x0 +-#define VF610_PAD_PTC15__ENET_RMII1_TXD1 0x0F0 0x000 ALT1 0x0 +-#define VF610_PAD_PTC15__ESAI_SDI0 0x0F0 0x328 ALT3 0x1 +-#define VF610_PAD_PTC15__UART5_RX 0x0F0 0x000 ALT4 0x0 +-#define VF610_PAD_PTC15__SAI2_TX_DATA 0x0F0 0x000 ALT5 0x0 +-#define VF610_PAD_PTC15__ADC0_SE7 0x0F0 0x000 ALT6 0x0 +-#define VF610_PAD_PTC15__DEBUG_OUT6 0x0F0 0x000 ALT7 0x0 +-#define VF610_PAD_PTC16__GPIO_61 0x0F4 0x000 ALT0 0x0 +-#define VF610_PAD_PTC16__ENET_RMII1_TXD0 0x0F4 0x000 ALT1 0x0 +-#define VF610_PAD_PTC16__ESAI_SDI1 0x0F4 0x324 ALT3 0x1 +-#define VF610_PAD_PTC16__UART5_RTS 0x0F4 0x000 ALT4 0x0 +-#define VF610_PAD_PTC16__SAI2_RX_SYNC 0x0F4 0x36C ALT5 0x2 +-#define VF610_PAD_PTC16__ADC1_SE6 0x0F4 0x000 ALT6 0x0 +-#define VF610_PAD_PTC16__DEBUG_OUT7 0x0F4 0x000 ALT7 0x0 +-#define VF610_PAD_PTC17__GPIO_62 0x0F8 0x000 ALT0 0x0 +-#define VF610_PAD_PTC17__ENET_RMII1_TXEN 0x0F8 0x000 ALT1 0x0 +-#define VF610_PAD_PTC17__ADC1_SE7 0x0F8 0x000 ALT3 0x0 +-#define VF610_PAD_PTC17__UART5_CTS 0x0F8 0x000 ALT4 0x0 +-#define VF610_PAD_PTC17__SAI2_TX_SYNC 0x0F8 0x374 ALT5 0x1 +-#define VF610_PAD_PTC17__USB1_SOF_PULSE 0x0F8 0x000 ALT6 0x0 +-#define VF610_PAD_PTC17__DEBUG_OUT8 0x0F8 0x000 ALT7 0x0 +-#define VF610_PAD_PTD31__GPIO_63 0x0FC 0x000 ALT0 0x0 +-#define VF610_PAD_PTD31__FB_AD31 0x0FC 0x000 ALT1 0x0 +-#define VF610_PAD_PTD31__NF_IO15 0x0FC 0x000 ALT2 0x0 +-#define VF610_PAD_PTD31__FTM3_CH0 0x0FC 0x000 ALT4 0x0 +-#define VF610_PAD_PTD31__DSPI2_CS1 0x0FC 0x000 ALT5 0x0 +-#define VF610_PAD_PTD31__DEBUG_OUT9 0x0FC 0x000 ALT7 0x0 +-#define VF610_PAD_PTD30__GPIO_64 0x100 0x000 ALT0 0x0 +-#define VF610_PAD_PTD30__FB_AD30 0x100 0x000 ALT1 0x0 +-#define VF610_PAD_PTD30__NF_IO14 0x100 0x000 ALT2 0x0 +-#define VF610_PAD_PTD30__FTM3_CH1 0x100 0x000 ALT4 0x0 +-#define VF610_PAD_PTD30__DSPI2_CS0 0x100 0x000 ALT5 0x0 +-#define VF610_PAD_PTD30__DEBUG_OUT10 0x100 0x000 ALT7 0x0 +-#define VF610_PAD_PTD29__GPIO_65 0x104 0x000 ALT0 0x0 +-#define VF610_PAD_PTD29__FB_AD29 0x104 0x000 ALT1 0x0 +-#define VF610_PAD_PTD29__NF_IO13 0x104 0x000 ALT2 0x0 +-#define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0 +-#define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0 +-#define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0 +-#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0 +-#define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0 +-#define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0 +-#define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1 +-#define VF610_PAD_PTD28__FTM3_CH3 0x108 0x000 ALT4 0x0 +-#define VF610_PAD_PTD28__DSPI2_SOUT 0x108 0x000 ALT5 0x0 +-#define VF610_PAD_PTD28__DEBUG_OUT12 0x108 0x000 ALT7 0x0 +-#define VF610_PAD_PTD27__GPIO_67 0x10C 0x000 ALT0 0x0 +-#define VF610_PAD_PTD27__FB_AD27 0x10C 0x000 ALT1 0x0 +-#define VF610_PAD_PTD27__NF_IO11 0x10C 0x000 ALT2 0x0 +-#define VF610_PAD_PTD27__I2C2_SDA 0x10C 0x350 ALT3 0x1 +-#define VF610_PAD_PTD27__FTM3_CH4 0x10C 0x000 ALT4 0x0 +-#define VF610_PAD_PTD27__DSPI2_SCK 0x10C 0x000 ALT5 0x0 +-#define VF610_PAD_PTD27__DEBUG_OUT13 0x10C 0x000 ALT7 0x0 +-#define VF610_PAD_PTD26__GPIO_68 0x110 0x000 ALT0 0x0 +-#define VF610_PAD_PTD26__FB_AD26 0x110 0x000 ALT1 0x0 +-#define VF610_PAD_PTD26__NF_IO10 0x110 0x000 ALT2 0x0 +-#define VF610_PAD_PTD26__FTM3_CH5 0x110 0x000 ALT4 0x0 +-#define VF610_PAD_PTD26__ESDHC1_WP 0x110 0x000 ALT5 0x0 +-#define VF610_PAD_PTD26__DEBUG_OUT14 0x110 0x000 ALT7 0x0 +-#define VF610_PAD_PTD25__GPIO_69 0x114 0x000 ALT0 0x0 +-#define VF610_PAD_PTD25__FB_AD25 0x114 0x000 ALT1 0x0 +-#define VF610_PAD_PTD25__NF_IO9 0x114 0x000 ALT2 0x0 +-#define VF610_PAD_PTD25__FTM3_CH6 0x114 0x000 ALT4 0x0 +-#define VF610_PAD_PTD25__DEBUG_OUT15 0x114 0x000 ALT7 0x0 +-#define VF610_PAD_PTD24__GPIO_70 0x118 0x000 ALT0 0x0 +-#define VF610_PAD_PTD24__FB_AD24 0x118 0x000 ALT1 0x0 +-#define VF610_PAD_PTD24__NF_IO8 0x118 0x000 ALT2 0x0 +-#define VF610_PAD_PTD24__FTM3_CH7 0x118 0x000 ALT4 0x0 +-#define VF610_PAD_PTD24__DEBUG_OUT16 0x118 0x000 ALT7 0x0 +-#define VF610_PAD_PTD23__GPIO_71 0x11C 0x000 ALT0 0x0 +-#define VF610_PAD_PTD23__FB_AD23 0x11C 0x000 ALT1 0x0 +-#define VF610_PAD_PTD23__NF_IO7 0x11C 0x000 ALT2 0x0 +-#define VF610_PAD_PTD23__FTM2_CH0 0x11C 0x000 ALT3 0x0 +-#define VF610_PAD_PTD23__ENET0_1588_TMR0 0x11C 0x304 ALT4 0x1 +-#define VF610_PAD_PTD23__ESDHC0_DAT4 0x11C 0x000 ALT5 0x0 +-#define VF610_PAD_PTD23__UART2_TX 0x11C 0x38C ALT6 0x1 +-#define VF610_PAD_PTD23__DCU1_R3 0x11C 0x000 ALT7 0x0 +-#define VF610_PAD_PTD22__GPIO_72 0x120 0x000 ALT0 0x0 +-#define VF610_PAD_PTD22__FB_AD22 0x120 0x000 ALT1 0x0 +-#define VF610_PAD_PTD22__NF_IO6 0x120 0x000 ALT2 0x0 +-#define VF610_PAD_PTD22__FTM2_CH1 0x120 0x000 ALT3 0x0 +-#define VF610_PAD_PTD22__ENET0_1588_TMR1 0x120 0x308 ALT4 0x1 +-#define VF610_PAD_PTD22__ESDHC0_DAT5 0x120 0x000 ALT5 0x0 +-#define VF610_PAD_PTD22__UART2_RX 0x120 0x388 ALT6 0x1 +-#define VF610_PAD_PTD22__DCU1_R4 0x120 0x000 ALT7 0x0 +-#define VF610_PAD_PTD21__GPIO_73 0x124 0x000 ALT0 0x0 +-#define VF610_PAD_PTD21__FB_AD21 0x124 0x000 ALT1 0x0 +-#define VF610_PAD_PTD21__NF_IO5 0x124 0x000 ALT2 0x0 +-#define VF610_PAD_PTD21__ENET0_1588_TMR2 0x124 0x000 ALT4 0x0 +-#define VF610_PAD_PTD21__ESDHC0_DAT6 0x124 0x000 ALT5 0x0 +-#define VF610_PAD_PTD21__UART2_RTS 0x124 0x000 ALT6 0x0 +-#define VF610_PAD_PTD21__DCU1_R5 0x124 0x000 ALT7 0x0 +-#define VF610_PAD_PTD20__GPIO_74 0x128 0x000 ALT0 0x0 +-#define VF610_PAD_PTD20__FB_AD20 0x128 0x000 ALT1 0x0 +-#define VF610_PAD_PTD20__NF_IO4 0x128 0x000 ALT2 0x0 +-#define VF610_PAD_PTD20__ENET0_1588_TMR3 0x128 0x000 ALT4 0x0 +-#define VF610_PAD_PTD20__ESDHC0_DAT7 0x128 0x000 ALT5 0x0 +-#define VF610_PAD_PTD20__UART2_CTS 0x128 0x384 ALT6 0x0 +-#define VF610_PAD_PTD20__DCU1_R0 0x128 0x000 ALT7 0x0 +-#define VF610_PAD_PTD19__GPIO_75 0x12C 0x000 ALT0 0x0 +-#define VF610_PAD_PTD19__FB_AD19 0x12C 0x000 ALT1 0x0 +-#define VF610_PAD_PTD19__NF_IO3 0x12C 0x000 ALT2 0x0 +-#define VF610_PAD_PTD19__ESAI_SCKR 0x12C 0x000 ALT3 0x0 +-#define VF610_PAD_PTD19__I2C0_SCL 0x12C 0x33C ALT4 0x2 +-#define VF610_PAD_PTD19__FTM2_QD_PHA 0x12C 0x000 ALT5 0x0 +-#define VF610_PAD_PTD19__DCU1_R1 0x12C 0x000 ALT7 0x0 +-#define VF610_PAD_PTD18__GPIO_76 0x130 0x000 ALT0 0x0 +-#define VF610_PAD_PTD18__FB_AD18 0x130 0x000 ALT1 0x0 +-#define VF610_PAD_PTD18__NF_IO2 0x130 0x000 ALT2 0x0 +-#define VF610_PAD_PTD18__ESAI_FSR 0x130 0x000 ALT3 0x0 +-#define VF610_PAD_PTD18__I2C0_SDA 0x130 0x340 ALT4 0x2 +-#define VF610_PAD_PTD18__FTM2_QD_PHB 0x130 0x000 ALT5 0x0 +-#define VF610_PAD_PTD18__DCU1_G0 0x130 0x000 ALT7 0x0 +-#define VF610_PAD_PTD17__GPIO_77 0x134 0x000 ALT0 0x0 +-#define VF610_PAD_PTD17__FB_AD17 0x134 0x000 ALT1 0x0 +-#define VF610_PAD_PTD17__NF_IO1 0x134 0x000 ALT2 0x0 +-#define VF610_PAD_PTD17__ESAI_HCKR 0x134 0x000 ALT3 0x0 +-#define VF610_PAD_PTD17__I2C1_SCL 0x134 0x344 ALT4 0x2 +-#define VF610_PAD_PTD17__DCU1_G1 0x134 0x000 ALT7 0x0 +-#define VF610_PAD_PTD16__GPIO_78 0x138 0x000 ALT0 0x0 +-#define VF610_PAD_PTD16__FB_AD16 0x138 0x000 ALT1 0x0 +-#define VF610_PAD_PTD16__NF_IO0 0x138 0x000 ALT2 0x0 +-#define VF610_PAD_PTD16__ESAI_HCKT 0x138 0x000 ALT3 0x0 +-#define VF610_PAD_PTD16__I2C1_SDA 0x138 0x348 ALT4 0x2 +-#define VF610_PAD_PTD16__DCU1_G2 0x138 0x000 ALT7 0x0 +-#define VF610_PAD_PTD0__GPIO_79 0x13C 0x000 ALT0 0x0 +-#define VF610_PAD_PTD0__QSPI0_A_QSCK 0x13C 0x000 ALT1 0x0 +-#define VF610_PAD_PTD0__UART2_TX 0x13C 0x38C ALT2 0x2 +-#define VF610_PAD_PTD0__FB_AD15 0x13C 0x000 ALT4 0x0 +-#define VF610_PAD_PTD0__SPDIF_EXTCLK 0x13C 0x000 ALT5 0x0 +-#define VF610_PAD_PTD0__DEBUG_OUT17 0x13C 0x000 ALT7 0x0 +-#define VF610_PAD_PTD1__GPIO_80 0x140 0x000 ALT0 0x0 +-#define VF610_PAD_PTD1__QSPI0_A_CS0 0x140 0x000 ALT1 0x0 +-#define VF610_PAD_PTD1__UART2_RX 0x140 0x388 ALT2 0x2 +-#define VF610_PAD_PTD1__FB_AD14 0x140 0x000 ALT4 0x0 +-#define VF610_PAD_PTD1__SPDIF_IN1 0x140 0x000 ALT5 0x0 +-#define VF610_PAD_PTD1__DEBUG_OUT18 0x140 0x000 ALT7 0x0 +-#define VF610_PAD_PTD2__GPIO_81 0x144 0x000 ALT0 0x0 +-#define VF610_PAD_PTD2__QSPI0_A_DATA3 0x144 0x000 ALT1 0x0 +-#define VF610_PAD_PTD2__UART2_RTS 0x144 0x000 ALT2 0x0 +-#define VF610_PAD_PTD2__DSPI1_CS3 0x144 0x000 ALT3 0x0 +-#define VF610_PAD_PTD2__FB_AD13 0x144 0x000 ALT4 0x0 +-#define VF610_PAD_PTD2__SPDIF_OUT1 0x144 0x000 ALT5 0x0 +-#define VF610_PAD_PTD2__DEBUG_OUT19 0x144 0x000 ALT7 0x0 +-#define VF610_PAD_PTD3__GPIO_82 0x148 0x000 ALT0 0x0 +-#define VF610_PAD_PTD3__QSPI0_A_DATA2 0x148 0x000 ALT1 0x0 +-#define VF610_PAD_PTD3__UART2_CTS 0x148 0x384 ALT2 0x1 +-#define VF610_PAD_PTD3__DSPI1_CS2 0x148 0x000 ALT3 0x0 +-#define VF610_PAD_PTD3__FB_AD12 0x148 0x000 ALT4 0x0 +-#define VF610_PAD_PTD3__SPDIF_PLOCK 0x148 0x000 ALT5 0x0 +-#define VF610_PAD_PTD3__DEBUG_OUT20 0x148 0x000 ALT7 0x0 +-#define VF610_PAD_PTD4__GPIO_83 0x14C 0x000 ALT0 0x0 +-#define VF610_PAD_PTD4__QSPI0_A_DATA1 0x14C 0x000 ALT1 0x0 +-#define VF610_PAD_PTD4__DSPI1_CS1 0x14C 0x000 ALT3 0x0 +-#define VF610_PAD_PTD4__FB_AD11 0x14C 0x000 ALT4 0x0 +-#define VF610_PAD_PTD4__SPDIF_SRCLK 0x14C 0x000 ALT5 0x0 +-#define VF610_PAD_PTD4__DEBUG_OUT21 0x14C 0x000 ALT7 0x0 +-#define VF610_PAD_PTD5__GPIO_84 0x150 0x000 ALT0 0x0 +-#define VF610_PAD_PTD5__QSPI0_A_DATA0 0x150 0x000 ALT1 0x0 +-#define VF610_PAD_PTD5__DSPI1_CS0 0x150 0x300 ALT3 0x1 +-#define VF610_PAD_PTD5__FB_AD10 0x150 0x000 ALT4 0x0 +-#define VF610_PAD_PTD5__DEBUG_OUT22 0x150 0x000 ALT7 0x0 +-#define VF610_PAD_PTD6__GPIO_85 0x154 0x000 ALT0 0x0 +-#define VF610_PAD_PTD6__QSPI1_A_DQS 0x154 0x000 ALT1 0x0 +-#define VF610_PAD_PTD6__DSPI1_SIN 0x154 0x2FC ALT3 0x1 +-#define VF610_PAD_PTD6__FB_AD9 0x154 0x000 ALT4 0x0 +-#define VF610_PAD_PTD6__DEBUG_OUT23 0x154 0x000 ALT7 0x0 +-#define VF610_PAD_PTD7__GPIO_86 0x158 0x000 ALT0 0x0 +-#define VF610_PAD_PTD7__QSPI0_B_QSCK 0x158 0x000 ALT1 0x0 +-#define VF610_PAD_PTD7__DSPI1_SOUT 0x158 0x000 ALT3 0x0 +-#define VF610_PAD_PTD7__FB_AD8 0x158 0x000 ALT4 0x0 +-#define VF610_PAD_PTD7__DEBUG_OUT24 0x158 0x000 ALT7 0x0 +-#define VF610_PAD_PTD8__GPIO_87 0x15C 0x000 ALT0 0x0 +-#define VF610_PAD_PTD8__QSPI0_B_CS0 0x15C 0x000 ALT1 0x0 +-#define VF610_PAD_PTD8__FB_CLKOUT 0x15C 0x000 ALT2 0x0 +-#define VF610_PAD_PTD8__DSPI1_SCK 0x15C 0x2F8 ALT3 0x1 +-#define VF610_PAD_PTD8__FB_AD7 0x15C 0x000 ALT4 0x0 +-#define VF610_PAD_PTD8__DEBUG_OUT25 0x15C 0x000 ALT7 0x0 +-#define VF610_PAD_PTD9__GPIO_88 0x160 0x000 ALT0 0x0 +-#define VF610_PAD_PTD9__QSPI0_B_DATA3 0x160 0x000 ALT1 0x0 +-#define VF610_PAD_PTD9__DSPI3_CS1 0x160 0x000 ALT2 0x0 +-#define VF610_PAD_PTD9__FB_AD6 0x160 0x000 ALT4 0x0 +-#define VF610_PAD_PTD9__SAI1_TX_SYNC 0x160 0x360 ALT6 0x0 +-#define VF610_PAD_PTD9__DCU1_B0 0x160 0x000 ALT7 0x0 +-#define VF610_PAD_PTD10__GPIO_89 0x164 0x000 ALT0 0x0 +-#define VF610_PAD_PTD10__QSPI0_B_DATA2 0x164 0x000 ALT1 0x0 +-#define VF610_PAD_PTD10__DSPI3_CS0 0x164 0x000 ALT2 0x0 +-#define VF610_PAD_PTD10__FB_AD5 0x164 0x000 ALT4 0x0 +-#define VF610_PAD_PTD10__DCU1_B1 0x164 0x000 ALT7 0x0 +-#define VF610_PAD_PTD11__GPIO_90 0x168 0x000 ALT0 0x0 +-#define VF610_PAD_PTD11__QSPI0_B_DATA1 0x168 0x000 ALT1 0x0 +-#define VF610_PAD_PTD11__DSPI3_SIN 0x168 0x000 ALT2 0x0 +-#define VF610_PAD_PTD11__FB_AD4 0x168 0x000 ALT4 0x0 +-#define VF610_PAD_PTD11__DEBUG_OUT26 0x168 0x000 ALT7 0x0 +-#define VF610_PAD_PTD12__GPIO_91 0x16C 0x000 ALT0 0x0 +-#define VF610_PAD_PTD12__QSPI0_B_DATA0 0x16C 0x000 ALT1 0x0 +-#define VF610_PAD_PTD12__DSPI3_SOUT 0x16C 0x000 ALT2 0x0 +-#define VF610_PAD_PTD12__FB_AD3 0x16C 0x000 ALT4 0x0 +-#define VF610_PAD_PTD12__DEBUG_OUT27 0x16C 0x000 ALT7 0x0 +-#define VF610_PAD_PTD13__GPIO_92 0x170 0x000 ALT0 0x0 +-#define VF610_PAD_PTD13__QSPI0_B_DQS 0x170 0x000 ALT1 0x0 +-#define VF610_PAD_PTD13__DSPI3_SCK 0x170 0x000 ALT2 0x0 +-#define VF610_PAD_PTD13__FB_AD2 0x170 0x000 ALT4 0x0 +-#define VF610_PAD_PTD13__DEBUG_OUT28 0x170 0x000 ALT7 0x0 +-#define VF610_PAD_PTB23__GPIO_93 0x174 0x000 ALT0 0x0 +-#define VF610_PAD_PTB23__SAI0_TX_BCLK 0x174 0x000 ALT1 0x0 +-#define VF610_PAD_PTB23__UART1_TX 0x174 0x380 ALT2 0x2 +-#define VF610_PAD_PTB23__SRC_RCON18 0x174 0x398 ALT3 0x1 +-#define VF610_PAD_PTB23__FB_MUXED_ALE 0x174 0x000 ALT4 0x0 +-#define VF610_PAD_PTB23__FB_TS_B 0x174 0x000 ALT5 0x0 +-#define VF610_PAD_PTB23__UART3_RTS 0x174 0x000 ALT6 0x0 +-#define VF610_PAD_PTB23__DCU1_G3 0x174 0x000 ALT7 0x0 +-#define VF610_PAD_PTB24__GPIO_94 0x178 0x000 ALT0 0x0 +-#define VF610_PAD_PTB24__SAI0_RX_BCLK 0x178 0x000 ALT1 0x0 +-#define VF610_PAD_PTB24__UART1_RX 0x178 0x37C ALT2 0x2 +-#define VF610_PAD_PTB24__SRC_RCON19 0x178 0x39C ALT3 0x1 +-#define VF610_PAD_PTB24__FB_MUXED_TSIZ0 0x178 0x000 ALT4 0x0 +-#define VF610_PAD_PTB24__NF_WE_B 0x178 0x000 ALT5 0x0 +-#define VF610_PAD_PTB24__UART3_CTS 0x178 0x000 ALT6 0x0 +-#define VF610_PAD_PTB24__DCU1_G4 0x178 0x000 ALT7 0x0 +-#define VF610_PAD_PTB25__GPIO_95 0x17C 0x000 ALT0 0x0 +-#define VF610_PAD_PTB25__SAI0_RX_DATA 0x17C 0x000 ALT1 0x0 +-#define VF610_PAD_PTB25__UART1_RTS 0x17C 0x000 ALT2 0x0 +-#define VF610_PAD_PTB25__SRC_RCON20 0x17C 0x3A0 ALT3 0x1 +-#define VF610_PAD_PTB25__FB_CS1_B 0x17C 0x000 ALT4 0x0 +-#define VF610_PAD_PTB25__NF_CE0_B 0x17C 0x000 ALT5 0x0 +-#define VF610_PAD_PTB25__DCU1_G5 0x17C 0x000 ALT7 0x0 +-#define VF610_PAD_PTB26__GPIO_96 0x180 0x000 ALT0 0x0 +-#define VF610_PAD_PTB26__SAI0_TX_DATA 0x180 0x000 ALT1 0x0 +-#define VF610_PAD_PTB26__UART1_CTS 0x180 0x378 ALT2 0x2 +-#define VF610_PAD_PTB26__SRC_RCON21 0x180 0x000 ALT3 0x0 +-#define VF610_PAD_PTB26__FB_CS0_B 0x180 0x000 ALT4 0x0 +-#define VF610_PAD_PTB26__NF_CE1_B 0x180 0x000 ALT5 0x0 +-#define VF610_PAD_PTB26__DCU1_G6 0x180 0x000 ALT7 0x0 +-#define VF610_PAD_PTB27__GPIO_97 0x184 0x000 ALT0 0x0 +-#define VF610_PAD_PTB27__SAI0_RX_SYNC 0x184 0x000 ALT1 0x0 +-#define VF610_PAD_PTB27__SRC_RCON22 0x184 0x000 ALT3 0x0 +-#define VF610_PAD_PTB27__FB_OE_B 0x184 0x000 ALT4 0x0 +-#define VF610_PAD_PTB27__FB_MUXED_TBST_B 0x184 0x000 ALT5 0x0 +-#define VF610_PAD_PTB27__NF_RE_B 0x184 0x000 ALT6 0x0 +-#define VF610_PAD_PTB27__DCU1_G7 0x184 0x000 ALT7 0x0 +-#define VF610_PAD_PTB28__GPIO_98 0x188 0x000 ALT0 0x0 +-#define VF610_PAD_PTB28__SAI0_TX_SYNC 0x188 0x000 ALT1 0x0 +-#define VF610_PAD_PTB28__SRC_RCON23 0x188 0x000 ALT3 0x0 +-#define VF610_PAD_PTB28__FB_RW_B 0x188 0x000 ALT4 0x0 +-#define VF610_PAD_PTB28__DCU1_B6 0x188 0x000 ALT7 0x0 +-#define VF610_PAD_PTC26__GPIO_99 0x18C 0x000 ALT0 0x0 +-#define VF610_PAD_PTC26__SAI1_TX_BCLK 0x18C 0x000 ALT1 0x0 +-#define VF610_PAD_PTC26__DSPI0_CS5 0x18C 0x000 ALT2 0x0 +-#define VF610_PAD_PTC26__SRC_RCON24 0x18C 0x000 ALT3 0x0 +-#define VF610_PAD_PTC26__FB_TA_B 0x18C 0x000 ALT4 0x0 +-#define VF610_PAD_PTC26__NF_RB_B 0x18C 0x000 ALT5 0x0 +-#define VF610_PAD_PTC26__DCU1_B7 0x18C 0x000 ALT7 0x0 +-#define VF610_PAD_PTC27__GPIO_100 0x190 0x000 ALT0 0x0 +-#define VF610_PAD_PTC27__SAI1_RX_BCLK 0x190 0x000 ALT1 0x0 +-#define VF610_PAD_PTC27__DSPI0_CS4 0x190 0x000 ALT2 0x0 +-#define VF610_PAD_PTC27__SRC_RCON25 0x190 0x000 ALT3 0x0 +-#define VF610_PAD_PTC27__FB_BE3_B 0x190 0x000 ALT4 0x0 +-#define VF610_PAD_PTC27__FB_CS3_B 0x190 0x000 ALT5 0x0 +-#define VF610_PAD_PTC27__NF_ALE 0x190 0x000 ALT6 0x0 +-#define VF610_PAD_PTC27__DCU1_B2 0x190 0x000 ALT7 0x0 +-#define VF610_PAD_PTC28__GPIO_101 0x194 0x000 ALT0 0x0 +-#define VF610_PAD_PTC28__SAI1_RX_DATA 0x194 0x000 ALT1 0x0 +-#define VF610_PAD_PTC28__DSPI0_CS3 0x194 0x000 ALT2 0x0 +-#define VF610_PAD_PTC28__SRC_RCON26 0x194 0x000 ALT3 0x0 +-#define VF610_PAD_PTC28__FB_BE2_B 0x194 0x000 ALT4 0x0 +-#define VF610_PAD_PTC28__FB_CS2_B 0x194 0x000 ALT5 0x0 +-#define VF610_PAD_PTC28__NF_CLE 0x194 0x000 ALT6 0x0 +-#define VF610_PAD_PTC28__DCU1_B3 0x194 0x000 ALT7 0x0 +-#define VF610_PAD_PTC29__GPIO_102 0x198 0x000 ALT0 0x0 +-#define VF610_PAD_PTC29__SAI1_TX_DATA 0x198 0x000 ALT1 0x0 +-#define VF610_PAD_PTC29__DSPI0_CS2 0x198 0x000 ALT2 0x0 +-#define VF610_PAD_PTC29__SRC_RCON27 0x198 0x000 ALT3 0x0 +-#define VF610_PAD_PTC29__FB_BE1_B 0x198 0x000 ALT4 0x0 +-#define VF610_PAD_PTC29__FB_MUXED_TSIZE1 0x198 0x000 ALT5 0x0 +-#define VF610_PAD_PTC29__DCU1_B4 0x198 0x000 ALT7 0x0 +-#define VF610_PAD_PTC30__GPIO_103 0x19C 0x000 ALT0 0x0 +-#define VF610_PAD_PTC30__SAI1_RX_SYNC 0x19C 0x000 ALT1 0x0 +-#define VF610_PAD_PTC30__DSPI1_CS2 0x19C 0x000 ALT2 0x0 +-#define VF610_PAD_PTC30__SRC_RCON28 0x19C 0x000 ALT3 0x0 +-#define VF610_PAD_PTC30__FB_MUXED_BE0_B 0x19C 0x000 ALT4 0x0 +-#define VF610_PAD_PTC30__FB_TSIZ0 0x19C 0x000 ALT5 0x0 +-#define VF610_PAD_PTC30__ADC0_SE5 0x19C 0x000 ALT6 0x0 +-#define VF610_PAD_PTC30__DCU1_B5 0x19C 0x000 ALT7 0x0 +-#define VF610_PAD_PTC31__GPIO_104 0x1A0 0x000 ALT0 0x0 +-#define VF610_PAD_PTC31__SAI1_TX_SYNC 0x1A0 0x360 ALT1 0x1 +-#define VF610_PAD_PTC31__SRC_RCON29 0x1A0 0x000 ALT3 0x0 +-#define VF610_PAD_PTC31__ADC1_SE5 0x1A0 0x000 ALT6 0x0 +-#define VF610_PAD_PTC31__DCU1_B6 0x1A0 0x000 ALT7 0x0 +-#define VF610_PAD_PTE0__GPIO_105 0x1A4 0x000 ALT0 0x0 +-#define VF610_PAD_PTE0__DCU0_HSYNC 0x1A4 0x000 ALT1 0x0 +-#define VF610_PAD_PTE0__SRC_BMODE1 0x1A4 0x000 ALT2 0x0 +-#define VF610_PAD_PTE0__LCD0 0x1A4 0x000 ALT4 0x0 +-#define VF610_PAD_PTE0__DEBUG_OUT29 0x1A4 0x000 ALT7 0x0 +-#define VF610_PAD_PTE1__GPIO_106 0x1A8 0x000 ALT0 0x0 +-#define VF610_PAD_PTE1__DCU0_VSYNC 0x1A8 0x000 ALT1 0x0 +-#define VF610_PAD_PTE1__SRC_BMODE0 0x1A8 0x000 ALT2 0x0 +-#define VF610_PAD_PTE1__LCD1 0x1A8 0x000 ALT4 0x0 +-#define VF610_PAD_PTE1__DEBUG_OUT30 0x1A8 0x000 ALT7 0x0 +-#define VF610_PAD_PTE2__GPIO_107 0x1AC 0x000 ALT0 0x0 +-#define VF610_PAD_PTE2__DCU0_PCLK 0x1AC 0x000 ALT1 0x0 +-#define VF610_PAD_PTE2__LCD2 0x1AC 0x000 ALT4 0x0 +-#define VF610_PAD_PTE2__DEBUG_OUT31 0x1AC 0x000 ALT7 0x0 +-#define VF610_PAD_PTE3__GPIO_108 0x1B0 0x000 ALT0 0x0 +-#define VF610_PAD_PTE3__DCU0_TAG 0x1B0 0x000 ALT1 0x0 +-#define VF610_PAD_PTE3__LCD3 0x1B0 0x000 ALT4 0x0 +-#define VF610_PAD_PTE3__DEBUG_OUT32 0x1B0 0x000 ALT7 0x0 +-#define VF610_PAD_PTE4__GPIO_109 0x1B4 0x000 ALT0 0x0 +-#define VF610_PAD_PTE4__DCU0_DE 0x1B4 0x000 ALT1 0x0 +-#define VF610_PAD_PTE4__LCD4 0x1B4 0x000 ALT4 0x0 +-#define VF610_PAD_PTE4__DEBUG_OUT33 0x1B4 0x000 ALT7 0x0 +-#define VF610_PAD_PTE5__GPIO_110 0x1B8 0x000 ALT0 0x0 +-#define VF610_PAD_PTE5__DCU0_R0 0x1B8 0x000 ALT1 0x0 +-#define VF610_PAD_PTE5__LCD5 0x1B8 0x000 ALT4 0x0 +-#define VF610_PAD_PTE5__DEBUG_OUT34 0x1B8 0x000 ALT7 0x0 +-#define VF610_PAD_PTE6__GPIO_111 0x1BC 0x000 ALT0 0x0 +-#define VF610_PAD_PTE6__DCU0_R1 0x1BC 0x000 ALT1 0x0 +-#define VF610_PAD_PTE6__LCD6 0x1BC 0x000 ALT4 0x0 +-#define VF610_PAD_PTE6__DEBUG_OUT35 0x1BC 0x000 ALT7 0x0 +-#define VF610_PAD_PTE7__GPIO_112 0x1C0 0x000 ALT0 0x0 +-#define VF610_PAD_PTE7__DCU0_R2 0x1C0 0x000 ALT1 0x0 +-#define VF610_PAD_PTE7__SRC_RCON0 0x1C0 0x000 ALT3 0x0 +-#define VF610_PAD_PTE7__LCD7 0x1C0 0x000 ALT4 0x0 +-#define VF610_PAD_PTE7__DEBUG_OUT36 0x1C0 0x000 ALT7 0x0 +-#define VF610_PAD_PTE8__GPIO_113 0x1C4 0x000 ALT0 0x0 +-#define VF610_PAD_PTE8__DCU0_R3 0x1C4 0x000 ALT1 0x0 +-#define VF610_PAD_PTE8__SRC_RCON1 0x1C4 0x000 ALT3 0x0 +-#define VF610_PAD_PTE8__LCD8 0x1C4 0x000 ALT4 0x0 +-#define VF610_PAD_PTE8__DEBUG_OUT37 0x1C4 0x000 ALT7 0x0 +-#define VF610_PAD_PTE9__GPIO_114 0x1C8 0x000 ALT0 0x0 +-#define VF610_PAD_PTE9__DCU0_R4 0x1C8 0x000 ALT1 0x0 +-#define VF610_PAD_PTE9__SRC_RCON2 0x1C8 0x000 ALT3 0x0 +-#define VF610_PAD_PTE9__LCD9 0x1C8 0x000 ALT4 0x0 +-#define VF610_PAD_PTE9__DEBUG_OUT38 0x1C8 0x000 ALT7 0x0 +-#define VF610_PAD_PTE10__GPIO_115 0x1CC 0x000 ALT0 0x0 +-#define VF610_PAD_PTE10__DCU0_R5 0x1CC 0x000 ALT1 0x0 +-#define VF610_PAD_PTE10__SRC_RCON3 0x1CC 0x000 ALT3 0x0 +-#define VF610_PAD_PTE10__LCD10 0x1CC 0x000 ALT4 0x0 +-#define VF610_PAD_PTE10__DEBUG_OUT39 0x1CC 0x000 ALT7 0x0 +-#define VF610_PAD_PTE11__GPIO_116 0x1D0 0x000 ALT0 0x0 +-#define VF610_PAD_PTE11__DCU0_R6 0x1D0 0x000 ALT1 0x0 +-#define VF610_PAD_PTE11__SRC_RCON4 0x1D0 0x000 ALT3 0x0 +-#define VF610_PAD_PTE11__LCD11 0x1D0 0x000 ALT4 0x0 +-#define VF610_PAD_PTE11__DEBUG_OUT40 0x1D0 0x000 ALT7 0x0 +-#define VF610_PAD_PTE12__GPIO_117 0x1D4 0x000 ALT0 0x0 +-#define VF610_PAD_PTE12__DCU0_R7 0x1D4 0x000 ALT1 0x0 +-#define VF610_PAD_PTE12__DSPI1_CS3 0x1D4 0x000 ALT2 0x0 +-#define VF610_PAD_PTE12__SRC_RCON5 0x1D4 0x000 ALT3 0x0 +-#define VF610_PAD_PTE12__LCD12 0x1D4 0x000 ALT4 0x0 +-#define VF610_PAD_PTE12__LPT_ALT0 0x1D4 0x000 ALT7 0x0 +-#define VF610_PAD_PTE13__GPIO_118 0x1D8 0x000 ALT0 0x0 +-#define VF610_PAD_PTE13__DCU0_G0 0x1D8 0x000 ALT1 0x0 +-#define VF610_PAD_PTE13__LCD13 0x1D8 0x000 ALT4 0x0 +-#define VF610_PAD_PTE13__DEBUG_OUT41 0x1D8 0x000 ALT7 0x0 +-#define VF610_PAD_PTE14__GPIO_119 0x1DC 0x000 ALT0 0x0 +-#define VF610_PAD_PTE14__DCU0_G1 0x1DC 0x000 ALT1 0x0 +-#define VF610_PAD_PTE14__LCD14 0x1DC 0x000 ALT4 0x0 +-#define VF610_PAD_PTE14__DEBUG_OUT42 0x1DC 0x000 ALT7 0x0 +-#define VF610_PAD_PTE15__GPIO_120 0x1E0 0x000 ALT0 0x0 +-#define VF610_PAD_PTE15__DCU0_G2 0x1E0 0x000 ALT1 0x0 +-#define VF610_PAD_PTE15__SRC_RCON6 0x1E0 0x000 ALT3 0x0 +-#define VF610_PAD_PTE15__LCD15 0x1E0 0x000 ALT4 0x0 +-#define VF610_PAD_PTE15__DEBUG_OUT43 0x1E0 0x000 ALT7 0x0 +-#define VF610_PAD_PTE16__GPIO_121 0x1E4 0x000 ALT0 0x0 +-#define VF610_PAD_PTE16__DCU0_G3 0x1E4 0x000 ALT1 0x0 +-#define VF610_PAD_PTE16__SRC_RCON7 0x1E4 0x000 ALT3 0x0 +-#define VF610_PAD_PTE16__LCD16 0x1E4 0x000 ALT4 0x0 +-#define VF610_PAD_PTE17__GPIO_122 0x1E8 0x000 ALT0 0x0 +-#define VF610_PAD_PTE17__DCU0_G4 0x1E8 0x000 ALT1 0x0 +-#define VF610_PAD_PTE17__SRC_RCON8 0x1E8 0x000 ALT3 0x0 +-#define VF610_PAD_PTE17__LCD17 0x1E8 0x000 ALT4 0x0 +-#define VF610_PAD_PTE18__GPIO_123 0x1EC 0x000 ALT0 0x0 +-#define VF610_PAD_PTE18__DCU0_G5 0x1EC 0x000 ALT1 0x0 +-#define VF610_PAD_PTE18__SRC_RCON9 0x1EC 0x000 ALT3 0x0 +-#define VF610_PAD_PTE18__LCD18 0x1EC 0x000 ALT4 0x0 +-#define VF610_PAD_PTE19__GPIO_124 0x1F0 0x000 ALT0 0x0 +-#define VF610_PAD_PTE19__DCU0_G6 0x1F0 0x000 ALT1 0x0 +-#define VF610_PAD_PTE19__SRC_RCON10 0x1F0 0x000 ALT3 0x0 +-#define VF610_PAD_PTE19__LCD19 0x1F0 0x000 ALT4 0x0 +-#define VF610_PAD_PTE19__I2C0_SCL 0x1F0 0x33C ALT5 0x3 +-#define VF610_PAD_PTE20__GPIO_125 0x1F4 0x000 ALT0 0x0 +-#define VF610_PAD_PTE20__DCU0_G7 0x1F4 0x000 ALT1 0x0 +-#define VF610_PAD_PTE20__SRC_RCON11 0x1F4 0x000 ALT3 0x0 +-#define VF610_PAD_PTE20__LCD20 0x1F4 0x000 ALT4 0x0 +-#define VF610_PAD_PTE20__I2C0_SDA 0x1F4 0x340 ALT5 0x3 +-#define VF610_PAD_PTE20__EWM_IN 0x1F4 0x000 ALT7 0x0 +-#define VF610_PAD_PTE21__GPIO_126 0x1F8 0x000 ALT0 0x0 +-#define VF610_PAD_PTE21__DCU0_B0 0x1F8 0x000 ALT1 0x0 +-#define VF610_PAD_PTE21__LCD21 0x1F8 0x000 ALT4 0x0 +-#define VF610_PAD_PTE22__GPIO_127 0x1FC 0x000 ALT0 0x0 +-#define VF610_PAD_PTE22__DCU0_B1 0x1FC 0x000 ALT1 0x0 +-#define VF610_PAD_PTE22__LCD22 0x1FC 0x000 ALT4 0x0 +-#define VF610_PAD_PTE23__GPIO_128 0x200 0x000 ALT0 0x0 +-#define VF610_PAD_PTE23__DCU0_B2 0x200 0x000 ALT1 0x0 +-#define VF610_PAD_PTE23__SRC_RCON12 0x200 0x000 ALT3 0x0 +-#define VF610_PAD_PTE23__LCD23 0x200 0x000 ALT4 0x0 +-#define VF610_PAD_PTE24__GPIO_129 0x204 0x000 ALT0 0x0 +-#define VF610_PAD_PTE24__DCU0_B3 0x204 0x000 ALT1 0x0 +-#define VF610_PAD_PTE24__SRC_RCON13 0x204 0x000 ALT3 0x0 +-#define VF610_PAD_PTE24__LCD24 0x204 0x000 ALT4 0x0 +-#define VF610_PAD_PTE25__GPIO_130 0x208 0x000 ALT0 0x0 +-#define VF610_PAD_PTE25__DCU0_B4 0x208 0x000 ALT1 0x0 +-#define VF610_PAD_PTE25__SRC_RCON14 0x208 0x000 ALT3 0x0 +-#define VF610_PAD_PTE25__LCD25 0x208 0x000 ALT4 0x0 +-#define VF610_PAD_PTE26__GPIO_131 0x20C 0x000 ALT0 0x0 +-#define VF610_PAD_PTE26__DCU0_B5 0x20C 0x000 ALT1 0x0 +-#define VF610_PAD_PTE26__SRC_RCON15 0x20C 0x000 ALT3 0x0 +-#define VF610_PAD_PTE26__LCD26 0x20C 0x000 ALT4 0x0 +-#define VF610_PAD_PTE27__GPIO_132 0x210 0x000 ALT0 0x0 +-#define VF610_PAD_PTE27__DCU0_B6 0x210 0x000 ALT1 0x0 +-#define VF610_PAD_PTE27__SRC_RCON16 0x210 0x000 ALT3 0x0 +-#define VF610_PAD_PTE27__LCD27 0x210 0x000 ALT4 0x0 +-#define VF610_PAD_PTE27__I2C1_SCL 0x210 0x344 ALT5 0x3 +-#define VF610_PAD_PTE28__GPIO_133 0x214 0x000 ALT0 0x0 +-#define VF610_PAD_PTE28__DCU0_B7 0x214 0x000 ALT1 0x0 +-#define VF610_PAD_PTE28__SRC_RCON17 0x214 0x000 ALT3 0x0 +-#define VF610_PAD_PTE28__LCD28 0x214 0x000 ALT4 0x0 +-#define VF610_PAD_PTE28__I2C1_SDA 0x214 0x348 ALT5 0x3 +-#define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0 +-#define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0 +-#define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/arm/vf610-twr.dts b/scripts/dtc/include-prefixes/arm/vf610-twr.dts +deleted file mode 100644 +index dbb5ffcdcec4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf610-twr.dts ++++ /dev/null +@@ -1,373 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright 2013 Freescale Semiconductor, Inc. +- +-/dts-v1/; +-#include "vf610.dtsi" +- +-/ { +- model = "VF610 Tower Board"; +- compatible = "fsl,vf610-twr", "fsl,vf610"; +- +- chosen { +- bootargs = "console=ttyLP1,115200"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x8000000>; +- }; +- +- audio_ext: mclk_osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +- +- enet_ext: eth_osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- }; +- +- regulators { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_3p3v: regulator@0 { +- compatible = "regulator-fixed"; +- reg = <0>; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_vcc_3v3_mcu: regulator@1 { +- compatible = "regulator-fixed"; +- reg = <1>; +- regulator-name = "vcc_3v3_mcu"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,widgets = +- "Microphone", "Microphone Jack", +- "Headphone", "Headphone Jack", +- "Speaker", "Speaker Ext", +- "Line", "Line In Jack"; +- simple-audio-card,routing = +- "MIC_IN", "Microphone Jack", +- "Microphone Jack", "Mic Bias", +- "LINE_IN", "Line In Jack", +- "Headphone Jack", "HP_OUT", +- "Speaker Ext", "LINE_OUT"; +- +- simple-audio-card,cpu { +- sound-dai = <&sai2>; +- frame-master; +- bitclock-master; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&codec>; +- frame-master; +- bitclock-master; +- }; +- }; +-}; +- +-&adc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc0_ad5>; +- vref-supply = <®_vcc_3v3_mcu>; +- status = "okay"; +-}; +- +-&clks { +- clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>; +- clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext"; +- assigned-clocks = <&clks VF610_CLK_ENET_SEL>, +- <&clks VF610_CLK_ENET_TS_SEL>; +- assigned-clock-parents = <&clks VF610_CLK_ENET_EXT>, +- <&clks VF610_CLK_ENET_EXT>; +-}; +- +-&dspi0 { +- bus-num = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dspi0>; +- status = "okay"; +- +- sflash: at26df081a@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "atmel,at26df081a"; +- spi-max-frequency = <16000000>; +- spi-cpol; +- spi-cpha; +- reg = <0>; +- }; +-}; +- +-&edma0 { +- status = "okay"; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- bus-width = <4>; +- cd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&fec0 { +- phy-mode = "rmii"; +- phy-handle = <ðphy0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec0>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- reg = <1>; +- }; +- }; +-}; +- +-&fec1 { +- phy-mode = "rmii"; +- phy-handle = <ðphy1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0>; +- status = "okay"; +- +- codec: sgtl5000@a { +- #sound-dai-cells = <0>; +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; +- clocks = <&clks VF610_CLK_SAI2>; +- }; +-}; +- +-&iomuxc { +- vf610-twr { +- pinctrl_adc0_ad5: adc0ad5grp { +- fsl,pins = < +- VF610_PAD_PTC30__ADC0_SE5 0xa1 +- >; +- }; +- +- pinctrl_dspi0: dspi0grp { +- fsl,pins = < +- VF610_PAD_PTB19__DSPI0_CS0 0x1182 +- VF610_PAD_PTB20__DSPI0_SIN 0x1181 +- VF610_PAD_PTB21__DSPI0_SOUT 0x1182 +- VF610_PAD_PTB22__DSPI0_SCK 0x1182 +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- VF610_PAD_PTA24__ESDHC1_CLK 0x31ef +- VF610_PAD_PTA25__ESDHC1_CMD 0x31ef +- VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef +- VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef +- VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef +- VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef +- VF610_PAD_PTA7__GPIO_134 0x219d +- >; +- }; +- +- pinctrl_fec0: fec0grp { +- fsl,pins = < +- VF610_PAD_PTA6__RMII_CLKIN 0x30d1 +- VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3 +- VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 +- VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 +- VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 +- VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 +- VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 +- VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 +- VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 +- VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 +- VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 +- VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 +- VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 +- VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 +- VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 +- VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 +- VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 +- VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 +- >; +- }; +- +- pinctrl_i2c0: i2c0grp { +- fsl,pins = < +- VF610_PAD_PTB14__I2C0_SCL 0x30d3 +- VF610_PAD_PTB15__I2C0_SDA 0x30d3 +- >; +- }; +- +- pinctrl_nfc: nfcgrp { +- fsl,pins = < +- VF610_PAD_PTD31__NF_IO15 0x28df +- VF610_PAD_PTD30__NF_IO14 0x28df +- VF610_PAD_PTD29__NF_IO13 0x28df +- VF610_PAD_PTD28__NF_IO12 0x28df +- VF610_PAD_PTD27__NF_IO11 0x28df +- VF610_PAD_PTD26__NF_IO10 0x28df +- VF610_PAD_PTD25__NF_IO9 0x28df +- VF610_PAD_PTD24__NF_IO8 0x28df +- VF610_PAD_PTD23__NF_IO7 0x28df +- VF610_PAD_PTD22__NF_IO6 0x28df +- VF610_PAD_PTD21__NF_IO5 0x28df +- VF610_PAD_PTD20__NF_IO4 0x28df +- VF610_PAD_PTD19__NF_IO3 0x28df +- VF610_PAD_PTD18__NF_IO2 0x28df +- VF610_PAD_PTD17__NF_IO1 0x28df +- VF610_PAD_PTD16__NF_IO0 0x28df +- VF610_PAD_PTB24__NF_WE_B 0x28c2 +- VF610_PAD_PTB25__NF_CE0_B 0x28c2 +- VF610_PAD_PTB27__NF_RE_B 0x28c2 +- VF610_PAD_PTC26__NF_RB_B 0x283d +- VF610_PAD_PTC27__NF_ALE 0x28c2 +- VF610_PAD_PTC28__NF_CLE 0x28c2 +- >; +- }; +- +- pinctrl_pwm0: pwm0grp { +- fsl,pins = < +- VF610_PAD_PTB0__FTM0_CH0 0x1582 +- VF610_PAD_PTB1__FTM0_CH1 0x1582 +- VF610_PAD_PTB2__FTM0_CH2 0x1582 +- VF610_PAD_PTB3__FTM0_CH3 0x1582 +- >; +- }; +- +- pinctrl_sai2: sai2grp { +- fsl,pins = < +- VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed +- VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee +- VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed +- VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed +- VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed +- VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed +- VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- VF610_PAD_PTB4__UART1_TX 0x21a2 +- VF610_PAD_PTB5__UART1_RX 0x21a1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- VF610_PAD_PTB6__UART2_TX 0x21a2 +- VF610_PAD_PTB7__UART2_RX 0x21a1 +- >; +- }; +- }; +-}; +- +-&nfc { +- assigned-clocks = <&clks VF610_CLK_NFC>; +- assigned-clock-rates = <33000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nfc>; +- status = "okay"; +- +- nand@0 { +- compatible = "fsl,vf610-nfc-nandcs"; +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- nand-bus-width = <16>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <24>; +- nand-ecc-step-size = <2048>; +- nand-on-flash-bbt; +- }; +-}; +- +-&pwm0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm0>; +- status = "okay"; +-}; +- +-&sai2 { +- #sound-dai-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai2>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usbdev0 { +- disable-over-current; +- status = "okay"; +-}; +- +-&usbh1 { +- disable-over-current; +- status = "okay"; +-}; +- +-&usbmisc0 { +- status = "okay"; +-}; +- +-&usbmisc1 { +- status = "okay"; +-}; +- +-&usbphy0 { +- status = "okay"; +-}; +- +-&usbphy1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf610-zii-cfu1.dts b/scripts/dtc/include-prefixes/arm/vf610-zii-cfu1.dts +deleted file mode 100644 +index 96495d965163..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf610-zii-cfu1.dts ++++ /dev/null +@@ -1,368 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +- +-/* +- * Copyright (C) 2018 Zodiac Inflight Innovations +- */ +- +-/dts-v1/; +-#include "vf610.dtsi" +- +-/ { +- model = "ZII VF610 CFU1 Board"; +- compatible = "zii,vf610cfu1", "zii,vf610dev", "fsl,vf610"; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pinctrl_leds_debug>; +- pinctrl-names = "default"; +- +- led-debug { +- label = "zii:green:debug1"; +- gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-fail { +- label = "zii:red:fail"; +- gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led-status { +- label = "zii:green:status"; +- gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-debug-a { +- label = "zii:green:debug_a"; +- gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-debug-b { +- label = "zii:green:debug_b"; +- gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_3v3_mcu"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- sff: sfp { +- compatible = "sff,sff"; +- pinctrl-0 = <&pinctrl_optical>; +- pinctrl-names = "default"; +- i2c-bus = <&i2c0>; +- los-gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; +- tx-disable-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- }; +- +- supply-voltage-monitor { +- compatible = "iio-hwmon"; +- io-channels = <&adc0 8>, /* 28VDC_IN */ +- <&adc0 9>, /* +3.3V */ +- <&adc1 8>, /* VCC_1V5 */ +- <&adc1 9>; /* VCC_1V2 */ +- }; +-}; +- +-&adc0 { +- vref-supply = <®_vcc_3v3_mcu>; +- status = "okay"; +-}; +- +-&adc1 { +- vref-supply = <®_vcc_3v3_mcu>; +- status = "okay"; +-}; +- +-&dspi1 { +- bus-num = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dspi1>; +- /* +- * Some CFU1s come with SPI-NOR chip DNPed, so we leave this +- * node disabled by default and rely on bootloader to enable +- * it when appropriate. +- */ +- status = "disabled"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p128", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- +- partition@0 { +- label = "m25p128-0"; +- reg = <0x0 0x01000000>; +- }; +- }; +-}; +- +-&edma0 { +- status = "okay"; +-}; +- +-&edma1 { +- status = "okay"; +-}; +- +-&esdhc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc0>; +- bus-width = <8>; +- non-removable; +- no-1-8-v; +- keep-power-in-suspend; +- no-sdio; +- no-sd; +- status = "okay"; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- bus-width = <4>; +- no-sdio; +- status = "okay"; +-}; +- +-&fec1 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- status = "okay"; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- +- mdio1: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <12500000>; +- suppress-preamble; +- status = "okay"; +- +- switch0: switch0@0 { +- compatible = "marvell,mv88e6085"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_switch>; +- reg = <0>; +- eeprom-length = <512>; +- interrupt-parent = <&gpio3>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "eth_cu_1000_1"; +- }; +- +- port@1 { +- reg = <1>; +- label = "eth_cu_1000_2"; +- }; +- +- port@2 { +- reg = <2>; +- label = "eth_cu_1000_3"; +- }; +- +- port@5 { +- reg = <5>; +- label = "eth_fc_1000_1"; +- phy-mode = "1000base-x"; +- managed = "in-band-status"; +- sfp = <&sff>; +- }; +- +- port@6 { +- reg = <6>; +- label = "cpu"; +- ethernet = <&fec1>; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&i2c0 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0>; +- status = "okay"; +- +- io-expander@22 { +- compatible = "nxp,pca9554"; +- reg = <0x22>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- lm75@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c04"; +- reg = <0x52>; +- label = "nvm"; +- }; +- +- eeprom@54 { +- compatible = "atmel,24c04"; +- reg = <0x54>; +- label = "nameplate"; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- watchdog@38 { +- compatible = "zii,rave-wdt"; +- reg = <0x38>; +- }; +-}; +- +-&snvsrtc { +- status = "disabled"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_dspi1: dspi1grp { +- fsl,pins = < +- VF610_PAD_PTD5__DSPI1_CS0 0x1182 +- VF610_PAD_PTC6__DSPI1_SIN 0x1181 +- VF610_PAD_PTC7__DSPI1_SOUT 0x1182 +- VF610_PAD_PTC8__DSPI1_SCK 0x1182 +- >; +- }; +- +- pinctrl_esdhc0: esdhc0grp { +- fsl,pins = < +- VF610_PAD_PTC0__ESDHC0_CLK 0x31ef +- VF610_PAD_PTC1__ESDHC0_CMD 0x31ef +- VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef +- VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef +- VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef +- VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef +- VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef +- VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef +- VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef +- VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- VF610_PAD_PTA24__ESDHC1_CLK 0x31ef +- VF610_PAD_PTA25__ESDHC1_CMD 0x31ef +- VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef +- VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef +- VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef +- VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- VF610_PAD_PTA6__RMII_CLKIN 0x30d1 +- VF610_PAD_PTC9__ENET_RMII1_MDC 0x30fe +- VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 +- VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 +- VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 +- VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 +- VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 +- VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 +- VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 +- VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 +- >; +- }; +- +- pinctrl_i2c0: i2c0grp { +- fsl,pins = < +- VF610_PAD_PTB14__I2C0_SCL 0x37ff +- VF610_PAD_PTB15__I2C0_SDA 0x37ff +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- VF610_PAD_PTB16__I2C1_SCL 0x37ff +- VF610_PAD_PTB17__I2C1_SDA 0x37ff +- >; +- }; +- +- pinctrl_leds_debug: pinctrl-leds-debug { +- fsl,pins = < +- VF610_PAD_PTD3__GPIO_82 0x31c2 +- VF610_PAD_PTE3__GPIO_108 0x31c2 +- VF610_PAD_PTE4__GPIO_109 0x31c2 +- VF610_PAD_PTE5__GPIO_110 0x31c2 +- VF610_PAD_PTE6__GPIO_111 0x31c2 +- >; +- }; +- +- pinctrl_optical: optical-grp { +- fsl,pins = < +- /* SFF SD input */ +- VF610_PAD_PTE27__GPIO_132 0x3061 +- +- /* SFF Transmit disable output */ +- VF610_PAD_PTE13__GPIO_118 0x3043 +- >; +- }; +- +- pinctrl_switch: switch-grp { +- fsl,pins = < +- VF610_PAD_PTB28__GPIO_98 0x3061 +- >; +- }; +- +- pinctrl_uart0: uart0grp { +- fsl,pins = < +- VF610_PAD_PTB10__UART0_TX 0x21a2 +- VF610_PAD_PTB11__UART0_RX 0x21a1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf610-zii-dev-rev-b.dts b/scripts/dtc/include-prefixes/arm/vf610-zii-dev-rev-b.dts +deleted file mode 100644 +index 043ddd70372f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf610-zii-dev-rev-b.dts ++++ /dev/null +@@ -1,442 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2015, 2016 Zodiac Inflight Innovations +- */ +- +-/dts-v1/; +-#include "vf610-zii-dev.dtsi" +- +-/ { +- model = "ZII VF610 Development Board, Rev B"; +- compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610"; +- +- mdio-mux { +- compatible = "mdio-mux-gpio"; +- pinctrl-0 = <&pinctrl_mdio_mux>; +- pinctrl-names = "default"; +- gpios = <&gpio0 8 GPIO_ACTIVE_HIGH +- &gpio0 9 GPIO_ACTIVE_HIGH +- &gpio0 24 GPIO_ACTIVE_HIGH +- &gpio0 25 GPIO_ACTIVE_HIGH>; +- mdio-parent-bus = <&mdio1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- mdio_mux_1: mdio@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch0: switch@0 { +- compatible = "marvell,mv88e6085"; +- pinctrl-0 = <&pinctrl_gpio_switch0>; +- pinctrl-names = "default"; +- reg = <0>; +- dsa,member = <0 0>; +- interrupt-parent = <&gpio0>; +- interrupts = <27 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <2>; +- eeprom-length = <512>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan0"; +- phy-handle = <&switch0phy0>; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan1"; +- phy-handle = <&switch0phy1>; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- phy-handle = <&switch0phy2>; +- }; +- +- switch0port5: port@5 { +- reg = <5>; +- label = "dsa"; +- phy-mode = "rgmii-txid"; +- link = <&switch1port6 +- &switch2port9>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- port@6 { +- reg = <6>; +- label = "cpu"; +- ethernet = <&fec1>; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +- }; +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- switch0phy0: switch0phy0@0 { +- reg = <0>; +- interrupt-parent = <&switch0>; +- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; +- }; +- switch0phy1: switch1phy0@1 { +- reg = <1>; +- interrupt-parent = <&switch0>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; +- }; +- switch0phy2: switch1phy0@2 { +- reg = <2>; +- interrupt-parent = <&switch0>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; +- }; +- }; +- }; +- }; +- +- mdio_mux_2: mdio@2 { +- reg = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch1: switch@0 { +- compatible = "marvell,mv88e6085"; +- pinctrl-0 = <&pinctrl_gpio_switch1>; +- pinctrl-names = "default"; +- reg = <0>; +- dsa,member = <0 1>; +- interrupt-parent = <&gpio0>; +- interrupts = <26 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <2>; +- eeprom-length = <512>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan3"; +- phy-handle = <&switch1phy0>; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan4"; +- phy-handle = <&switch1phy1>; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan5"; +- phy-handle = <&switch1phy2>; +- }; +- +- switch1port5: port@5 { +- reg = <5>; +- label = "dsa"; +- link = <&switch2port9>; +- phy-mode = "rgmii-txid"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- switch1port6: port@6 { +- reg = <6>; +- label = "dsa"; +- phy-mode = "rgmii-txid"; +- link = <&switch0port5>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch1phy0: switch1phy0@0 { +- reg = <0>; +- interrupt-parent = <&switch1>; +- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switch1phy1: switch1phy0@1 { +- reg = <1>; +- interrupt-parent = <&switch1>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switch1phy2: switch1phy0@2 { +- reg = <2>; +- interrupt-parent = <&switch1>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; +- }; +- }; +- }; +- }; +- +- mdio_mux_4: mdio@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- +- switch2: switch@0 { +- compatible = "marvell,mv88e6085"; +- reg = <0>; +- dsa,member = <0 2>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan6"; +- phy-handle = <&switch2phy0>; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan7"; +- phy-handle = <&switch2phy1>; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan8"; +- phy-handle = <&switch2phy2>; +- }; +- +- port@3 { +- reg = <3>; +- label = "optical3"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- link-gpios = <&gpio6 2 +- GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- port@4 { +- reg = <4>; +- label = "optical4"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- link-gpios = <&gpio6 3 +- GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- switch2port9: port@9 { +- reg = <9>; +- label = "dsa"; +- phy-mode = "rgmii-txid"; +- link = <&switch1port5 +- &switch0port5>; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch2phy0: phy@0 { +- reg = <0>; +- }; +- switch2phy1: phy@1 { +- reg = <1>; +- }; +- switch2phy2: phy@2 { +- reg = <2>; +- }; +- }; +- }; +- }; +- +- mdio_mux_8: mdio@8 { +- reg = <8>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- spi0 { +- compatible = "spi-gpio"; +- pinctrl-0 = <&pinctrl_gpio_spi0>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>; +- gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>; +- gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW +- &gpio1 8 GPIO_ACTIVE_HIGH>; +- num-chipselects = <2>; +- +- flash@0 { +- compatible = "m25p128", "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- +- at93c46d@1 { +- compatible = "atmel,at93c46d"; +- pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>; +- pinctrl-names = "default"; +- reg = <1>; +- spi-max-frequency = <500000>; +- spi-cs-high; +- data-size = <16>; +- select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&i2c0 { +- gpio5: io-expander@20 { +- compatible = "nxp,pca9554"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- +- }; +- +- gpio6: io-expander@22 { +- compatible = "nxp,pca9554"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pca9554_22>; +- reg = <0x22>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- interrupt-parent = <&gpio3>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c2 { +- tca9548@70 { +- compatible = "nxp,pca9548"; +- pinctrl-0 = <&pinctrl_i2c_mux_reset>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- sfp1: eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- }; +- }; +- +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- sfp2: eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- }; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- sfp3: eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- sfp4: eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- }; +- }; +- +- i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- }; +-}; +- +-&mdio1 { +- clock-frequency = <5000000>; +-}; +- +-&iomuxc { +- pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 { +- fsl,pins = < +- VF610_PAD_PTE27__GPIO_132 0x33e2 +- >; +- }; +- +- pinctrl_gpio_spi0: pinctrl-gpio-spi0 { +- fsl,pins = < +- VF610_PAD_PTB22__GPIO_44 0x33e2 +- VF610_PAD_PTB21__GPIO_43 0x33e2 +- VF610_PAD_PTB20__GPIO_42 0x33e1 +- VF610_PAD_PTB19__GPIO_41 0x33e2 +- VF610_PAD_PTB18__GPIO_40 0x33e2 +- >; +- }; +- +- pinctrl_mdio_mux: pinctrl-mdio-mux { +- fsl,pins = < +- VF610_PAD_PTA18__GPIO_8 0x31c2 +- VF610_PAD_PTA19__GPIO_9 0x31c2 +- VF610_PAD_PTB2__GPIO_24 0x31c2 +- VF610_PAD_PTB3__GPIO_25 0x31c2 +- >; +- }; +- +- pinctrl_pca9554_22: pinctrl-pca95540-22 { +- fsl,pins = < +- VF610_PAD_PTB28__GPIO_98 0x219d +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf610-zii-dev-rev-c.dts b/scripts/dtc/include-prefixes/arm/vf610-zii-dev-rev-c.dts +deleted file mode 100644 +index de79dcfd32e6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf610-zii-dev-rev-c.dts ++++ /dev/null +@@ -1,456 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2015, 2016 Zodiac Inflight Innovations +- */ +- +-/dts-v1/; +-#include "vf610-zii-dev.dtsi" +- +-/ { +- model = "ZII VF610 Development Board, Rev C"; +- compatible = "zii,vf610dev-c", "zii,vf610dev", "fsl,vf610"; +- +- mdio-mux { +- compatible = "mdio-mux-gpio"; +- pinctrl-0 = <&pinctrl_mdio_mux>; +- pinctrl-names = "default"; +- gpios = <&gpio0 8 GPIO_ACTIVE_HIGH +- &gpio0 9 GPIO_ACTIVE_HIGH +- &gpio0 25 GPIO_ACTIVE_HIGH>; +- mdio-parent-bus = <&mdio1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- mdio_mux_1: mdio@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch0: switch@0 { +- compatible = "marvell,mv88e6190"; +- pinctrl-0 = <&pinctrl_gpio_switch0>; +- pinctrl-names = "default"; +- reg = <0>; +- dsa,member = <0 0>; +- eeprom-length = <65536>; +- interrupt-parent = <&gpio0>; +- interrupts = <27 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "cpu"; +- ethernet = <&fec1>; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan1"; +- phy-handle = <&switch0phy1>; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- phy-handle = <&switch0phy2>; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan3"; +- phy-handle = <&switch0phy3>; +- }; +- +- port@4 { +- reg = <4>; +- label = "lan4"; +- phy-handle = <&switch0phy4>; +- }; +- +- switch0port10: port@10 { +- reg = <10>; +- label = "dsa"; +- phy-mode = "xaui"; +- link = <&switch1port10>; +- }; +- }; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch0phy1: switch0phy@1 { +- reg = <1>; +- interrupt-parent = <&switch0>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switch0phy2: switch0phy@2 { +- reg = <2>; +- interrupt-parent = <&switch0>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switch0phy3: switch0phy@3 { +- reg = <3>; +- interrupt-parent = <&switch0>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switch0phy4: switch0phy@4 { +- reg = <4>; +- interrupt-parent = <&switch0>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +- }; +- }; +- }; +- }; +- +- mdio_mux_2: mdio@2 { +- reg = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch1: switch@0 { +- compatible = "marvell,mv88e6190"; +- pinctrl-0 = <&pinctrl_gpio_switch1>; +- pinctrl-names = "default"; +- reg = <0>; +- dsa,member = <0 1>; +- eeprom-length = <65536>; +- interrupt-parent = <&gpio0>; +- interrupts = <26 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <1>; +- label = "lan5"; +- phy-handle = <&switch1phy1>; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan6"; +- phy-handle = <&switch1phy2>; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan7"; +- phy-handle = <&switch1phy3>; +- }; +- +- port@4 { +- reg = <4>; +- label = "lan8"; +- phy-handle = <&switch1phy4>; +- }; +- +- port@9 { +- reg = <9>; +- label = "sff2"; +- phy-mode = "1000base-x"; +- managed = "in-band-status"; +- sfp = <&sff2>; +- }; +- +- switch1port10: port@10 { +- reg = <10>; +- label = "dsa"; +- phy-mode = "xaui"; +- link = <&switch0port10>; +- }; +- }; +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch1phy1: switch1phy@1 { +- reg = <1>; +- interrupt-parent = <&switch1>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switch1phy2: switch1phy@2 { +- reg = <2>; +- interrupt-parent = <&switch1>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switch1phy3: switch1phy@3 { +- reg = <3>; +- interrupt-parent = <&switch1>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switch1phy4: switch1phy@4 { +- reg = <4>; +- interrupt-parent = <&switch1>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +- }; +- }; +- }; +- }; +- +- mdio_mux_4: mdio@4 { +- reg = <4>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- sff2: sff2 { +- /* lower */ +- compatible = "sff,sff"; +- i2c-bus = <&sff2_i2c>; +- los-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; +- tx-disable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; +- }; +- +- sff3: sff3 { +- /* upper */ +- compatible = "sff,sff"; +- i2c-bus = <&sff3_i2c>; +- los-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; +- tx-disable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&dspi0 { +- bus-num = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dspi0>; +- status = "okay"; +- spi-num-chipselects = <2>; +- +- flash@0 { +- compatible = "m25p128", "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- +- atzb-rf-233@1 { +- compatible = "atmel,at86rf233"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctr_atzb_rf_233>; +- +- spi-max-frequency = <7500000>; +- reg = <1>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&gpio3>; +- xtal-trim = /bits/ 8 <0x06>; +- +- sleep-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>; +- reset-gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>; +- +- fsl,spi-cs-sck-delay = <180>; +- fsl,spi-sck-cs-delay = <250>; +- }; +-}; +- +-&i2c0 { +- /* +- * U712 +- * +- * Exposed signals: +- * P1 - WE2_CMD +- * P2 - WE2_CLK +- */ +- gpio5: io-expander@18 { +- compatible = "nxp,pca9557"; +- reg = <0x18>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- /* +- * U121 +- * +- * Exposed signals: +- * I/O0 - ENET_SWR_EN +- * I/O1 - ESW1_RESETn +- * I/O2 - ARINC_RESET +- * I/O3 - DD1_IO_RESET +- * I/O4 - ESW2_RESETn +- * I/O5 - ESW3_RESETn +- * I/O6 - ESW4_RESETn +- * I/O8 - TP909 +- * I/O9 - FEM_SEL +- * I/O10 - WIFI_RESETn +- * I/O11 - PHY_RSTn +- * I/O12 - OPT1_SD +- * I/O13 - OPT2_SD +- * I/O14 - OPT1_TX_DIS +- * I/O15 - OPT2_TX_DIS +- */ +- gpio6: sx1503@20 { +- compatible = "semtech,sx1503q"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sx1503_20>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- reg = <0x20>; +- interrupt-parent = <&gpio0>; +- interrupts = <23 IRQ_TYPE_EDGE_FALLING>; +- gpio-controller; +- interrupt-controller; +- }; +- +- /* +- * U715 +- * +- * Exposed signals: +- * IO0 - WE1_CLK +- * IO1 - WE1_CMD +- */ +- gpio7: io-expander@22 { +- compatible = "nxp,pca9554"; +- reg = <0x22>; +- gpio-controller; +- #gpio-cells = <2>; +- +- }; +-}; +- +-&i2c1 { +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- read-only; +- }; +-}; +- +-&i2c2 { +- tca9548@70 { +- compatible = "nxp,pca9548"; +- pinctrl-0 = <&pinctrl_i2c_mux_reset>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- sff2_i2c: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- sff3_i2c: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&gpio0 { +- eth0_intrp { +- gpio-hog; +- gpios = <23 GPIO_ACTIVE_HIGH>; +- input; +- line-name = "sx1503-irq"; +- }; +-}; +- +-&gpio3 { +- eth0_intrp { +- gpio-hog; +- gpios = <2 GPIO_ACTIVE_HIGH>; +- input; +- line-name = "eth0-intrp"; +- }; +-}; +- +-&fec0 { +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec0_phy_int>; +- +- interrupt-parent = <&gpio3>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- reg = <0>; +- }; +- }; +-}; +- +-&iomuxc { +- pinctr_atzb_rf_233: pinctrl-atzb-rf-233 { +- fsl,pins = < +- VF610_PAD_PTB2__GPIO_24 0x31c2 +- VF610_PAD_PTE27__GPIO_132 0x33e2 +- >; +- }; +- +- +- pinctrl_sx1503_20: pinctrl-sx1503-20 { +- fsl,pins = < +- VF610_PAD_PTB1__GPIO_23 0x219d +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- VF610_PAD_PTA20__UART3_TX 0x21a2 +- VF610_PAD_PTA21__UART3_RX 0x21a1 +- >; +- }; +- +- pinctrl_mdio_mux: pinctrl-mdio-mux { +- fsl,pins = < +- VF610_PAD_PTA18__GPIO_8 0x31c2 +- VF610_PAD_PTA19__GPIO_9 0x31c2 +- VF610_PAD_PTB3__GPIO_25 0x31c2 +- >; +- }; +- +- pinctrl_fec0_phy_int: pinctrl-fec0-phy-int { +- fsl,pins = < +- VF610_PAD_PTB28__GPIO_98 0x219d +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf610-zii-dev.dtsi b/scripts/dtc/include-prefixes/arm/vf610-zii-dev.dtsi +deleted file mode 100644 +index f8299f33a692..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf610-zii-dev.dtsi ++++ /dev/null +@@ -1,450 +0,0 @@ +-/* +- * Copyright (C) 2015, 2016 Zodiac Inflight Innovations +- * +- * Based on an original 'vf610-twr.dts' which is Copyright 2015, +- * Freescale Semiconductor, Inc. +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "vf610.dtsi" +- +-/ { +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pinctrl_leds_debug>; +- pinctrl-names = "default"; +- +- debug { +- label = "zii:green:debug1"; +- gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_3v3_mcu"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- usb0_vbus: regulator-usb0-vbus { +- compatible = "regulator-fixed"; +- pinctrl-0 = <&pinctrl_usb_vbus>; +- regulator-name = "usb_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio0 6 0>; +- }; +- +- supply-voltage-monitor { +- compatible = "iio-hwmon"; +- io-channels = <&adc0 8>, /* VCC_1V5 */ +- <&adc0 9>, /* VCC_1V8 */ +- <&adc1 8>, /* VCC_1V0 */ +- <&adc1 9>; /* VCC_1V2 */ +- }; +-}; +- +-&adc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_adc0_ad5>; +- vref-supply = <®_vcc_3v3_mcu>; +- status = "okay"; +-}; +- +-&edma0 { +- status = "okay"; +-}; +- +-&edma1 { +- status = "okay"; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&fec0 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec0>; +- status = "okay"; +-}; +- +-&fec1 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- status = "okay"; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- +- mdio1: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <12500000>; +- suppress-preamble; +- status = "okay"; +- }; +-}; +- +-&i2c0 { +- clock-frequency = <100000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c0>; +- pinctrl-1 = <&pinctrl_i2c0_gpio>; +- scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- +- lm75@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c04"; +- reg = <0x50>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c04"; +- reg = <0x52>; +- }; +- +- ds1682@6b { +- compatible = "dallas,ds1682"; +- reg = <0x6b>; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&qspi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_qspi0>; +- status = "okay"; +- +- /* +- * Attached MT25QL02 can go up to 90Mhz in DTR and 166 in STR +- * modes, so, spi-max-frequency is limited to 90MHz +- */ +- flash@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <90000000>; +- spi-rx-bus-width = <4>; +- reg = <0>; +- m25p,fast-read; +- }; +- +- flash@2 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <90000000>; +- spi-rx-bus-width = <4>; +- reg = <2>; +- m25p,fast-read; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usbdev0 { +- disable-over-current; +- vbus-supply = <&usb0_vbus>; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbh1 { +- disable-over-current; +- status = "okay"; +-}; +- +-&usbmisc0 { +- status = "okay"; +-}; +- +-&usbmisc1 { +- status = "okay"; +-}; +- +-&usbphy0 { +- status = "okay"; +-}; +- +-&usbphy1 { +- status = "okay"; +-}; +- +-&tempsensor { +- io-channels = <&adc0 16>; +-}; +- +-&iomuxc { +- pinctrl_adc0_ad5: adc0ad5grp { +- fsl,pins = < +- VF610_PAD_PTC30__ADC0_SE5 0x00a1 +- >; +- }; +- +- pinctrl_dspi0: dspi0grp { +- fsl,pins = < +- VF610_PAD_PTB18__DSPI0_CS1 0x1182 +- VF610_PAD_PTB19__DSPI0_CS0 0x1182 +- VF610_PAD_PTB20__DSPI0_SIN 0x1181 +- VF610_PAD_PTB21__DSPI0_SOUT 0x1182 +- VF610_PAD_PTB22__DSPI0_SCK 0x1182 +- >; +- }; +- +- pinctrl_dspi2: dspi2grp { +- fsl,pins = < +- VF610_PAD_PTD31__DSPI2_CS1 0x1182 +- VF610_PAD_PTD30__DSPI2_CS0 0x1182 +- VF610_PAD_PTD29__DSPI2_SIN 0x1181 +- VF610_PAD_PTD28__DSPI2_SOUT 0x1182 +- VF610_PAD_PTD27__DSPI2_SCK 0x1182 +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- VF610_PAD_PTA24__ESDHC1_CLK 0x31ef +- VF610_PAD_PTA25__ESDHC1_CMD 0x31ef +- VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef +- VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef +- VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef +- VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef +- VF610_PAD_PTA7__GPIO_134 0x219d +- >; +- }; +- +- pinctrl_fec0: fec0grp { +- fsl,pins = < +- VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d2 +- VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d3 +- VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 +- VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 +- VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 +- VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 +- VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 +- VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 +- VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- VF610_PAD_PTA6__RMII_CLKIN 0x30d1 +- VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 +- VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 +- VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 +- VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 +- VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 +- VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 +- VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 +- VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 +- VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 +- >; +- }; +- +- pinctrl_gpio_spi0: pinctrl-gpio-spi0 { +- fsl,pins = < +- VF610_PAD_PTB22__GPIO_44 0x33e2 +- VF610_PAD_PTB21__GPIO_43 0x33e2 +- VF610_PAD_PTB20__GPIO_42 0x33e1 +- VF610_PAD_PTB19__GPIO_41 0x33e2 +- VF610_PAD_PTB18__GPIO_40 0x33e2 +- >; +- }; +- +- pinctrl_gpio_switch0: pinctrl-gpio-switch0 { +- fsl,pins = < +- VF610_PAD_PTB5__GPIO_27 0x219d +- >; +- }; +- +- pinctrl_gpio_switch1: pinctrl-gpio-switch1 { +- fsl,pins = < +- VF610_PAD_PTB4__GPIO_26 0x219d +- >; +- }; +- +- pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset { +- fsl,pins = < +- VF610_PAD_PTE14__GPIO_119 0x31c2 +- >; +- }; +- +- pinctrl_i2c0: i2c0grp { +- fsl,pins = < +- VF610_PAD_PTB14__I2C0_SCL 0x37ff +- VF610_PAD_PTB15__I2C0_SDA 0x37ff +- >; +- }; +- +- pinctrl_i2c0_gpio: i2c0grp-gpio { +- fsl,pins = < +- VF610_PAD_PTB14__GPIO_36 0x31c2 +- VF610_PAD_PTB15__GPIO_37 0x31c2 +- >; +- }; +- +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- VF610_PAD_PTB16__I2C1_SCL 0x37ff +- VF610_PAD_PTB17__I2C1_SDA 0x37ff +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- VF610_PAD_PTA22__I2C2_SCL 0x37ff +- VF610_PAD_PTA23__I2C2_SDA 0x37ff +- >; +- }; +- +- pinctrl_leds_debug: pinctrl-leds-debug { +- fsl,pins = < +- VF610_PAD_PTD20__GPIO_74 0x31c2 +- >; +- }; +- +- pinctrl_qspi0: qspi0grp { +- fsl,pins = < +- VF610_PAD_PTD0__QSPI0_A_QSCK 0x38c2 +- VF610_PAD_PTD1__QSPI0_A_CS0 0x38c2 +- VF610_PAD_PTD2__QSPI0_A_DATA3 0x38c3 +- VF610_PAD_PTD3__QSPI0_A_DATA2 0x38c3 +- VF610_PAD_PTD4__QSPI0_A_DATA1 0x38c3 +- VF610_PAD_PTD5__QSPI0_A_DATA0 0x38c3 +- VF610_PAD_PTD7__QSPI0_B_QSCK 0x38c2 +- VF610_PAD_PTD8__QSPI0_B_CS0 0x38c2 +- VF610_PAD_PTD9__QSPI0_B_DATA3 0x38c3 +- VF610_PAD_PTD10__QSPI0_B_DATA2 0x38c3 +- VF610_PAD_PTD11__QSPI0_B_DATA1 0x38c3 +- VF610_PAD_PTD12__QSPI0_B_DATA0 0x38c3 +- >; +- }; +- +- pinctrl_uart0: uart0grp { +- fsl,pins = < +- VF610_PAD_PTB10__UART0_TX 0x21a2 +- VF610_PAD_PTB11__UART0_RX 0x21a1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- VF610_PAD_PTB23__UART1_TX 0x21a2 +- VF610_PAD_PTB24__UART1_RX 0x21a1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- VF610_PAD_PTD23__UART2_TX 0x21a2 +- VF610_PAD_PTD22__UART2_RX 0x21a1 +- >; +- }; +- +- pinctrl_usb_vbus: pinctrl-usb-vbus { +- fsl,pins = < +- VF610_PAD_PTA16__GPIO_6 0x31c2 +- >; +- }; +- +- pinctrl_usb0_host: usb0-host-grp { +- fsl,pins = < +- VF610_PAD_PTD6__GPIO_85 0x0062 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf610-zii-scu4-aib.dts b/scripts/dtc/include-prefixes/arm/vf610-zii-scu4-aib.dts +deleted file mode 100644 +index 040a1f8b6130..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf610-zii-scu4-aib.dts ++++ /dev/null +@@ -1,846 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// +-// Copyright (C) 2016-2018 Zodiac Inflight Innovations +- +-/dts-v1/; +-#include "vf610.dtsi" +- +-/ { +- model = "ZII VF610 SCU4 AIB"; +- compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610"; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pinctrl_leds_debug>; +- pinctrl-names = "default"; +- +- debug { +- label = "zii:green:debug1"; +- gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- mdio-mux { +- compatible = "mdio-mux-gpio"; +- pinctrl-0 = <&pinctrl_mdio_mux>; +- pinctrl-names = "default"; +- gpios = <&gpio4 4 GPIO_ACTIVE_HIGH +- &gpio4 5 GPIO_ACTIVE_HIGH +- &gpio3 30 GPIO_ACTIVE_HIGH +- &gpio3 31 GPIO_ACTIVE_HIGH>; +- mdio-parent-bus = <&mdio1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- mdio_mux_1: mdio@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch0: switch0@0 { +- compatible = "marvell,mv88e6190"; +- reg = <0>; +- dsa,member = <0 0>; +- eeprom-length = <65536>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "cpu"; +- ethernet = <&fec1>; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +- +- port@1 { +- reg = <1>; +- label = "aib2main_1"; +- }; +- +- port@2 { +- reg = <2>; +- label = "aib2main_2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "eth_cu_1000_5"; +- }; +- +- port@4 { +- reg = <4>; +- label = "eth_cu_1000_6"; +- }; +- +- port@5 { +- reg = <5>; +- label = "eth_cu_1000_4"; +- }; +- +- port@6 { +- reg = <6>; +- label = "eth_cu_1000_7"; +- }; +- +- port@7 { +- reg = <7>; +- label = "modem_pic"; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +- +- switch0port10: port@10 { +- reg = <10>; +- label = "dsa"; +- phy-mode = "xgmii"; +- link = <&switch1port10 +- &switch3port10 +- &switch2port10>; +- }; +- }; +- }; +- }; +- +- mdio_mux_2: mdio@2 { +- reg = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch1: switch1@0 { +- compatible = "marvell,mv88e6190"; +- reg = <0>; +- dsa,member = <0 1>; +- eeprom-length = <65536>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <1>; +- label = "eth_cu_1000_3"; +- }; +- +- port@2 { +- reg = <2>; +- label = "eth_cu_100_2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "eth_cu_100_3"; +- }; +- +- switch1port9: port@9 { +- reg = <9>; +- label = "dsa"; +- phy-mode = "xgmii"; +- link = <&switch3port10 +- &switch2port10>; +- }; +- +- switch1port10: port@10 { +- reg = <10>; +- label = "dsa"; +- phy-mode = "xgmii"; +- link = <&switch0port10>; +- }; +- }; +- }; +- }; +- +- mdio_mux_4: mdio@4 { +- reg = <4>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch2: switch2@0 { +- compatible = "marvell,mv88e6190"; +- reg = <0>; +- dsa,member = <0 2>; +- eeprom-length = <65536>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@2 { +- reg = <2>; +- label = "eth_fc_1000_2"; +- phy-mode = "1000base-x"; +- managed = "in-band-status"; +- sfp = <&sff1>; +- }; +- +- port@3 { +- reg = <3>; +- label = "eth_fc_1000_3"; +- phy-mode = "1000base-x"; +- managed = "in-band-status"; +- sfp = <&sff2>; +- }; +- +- port@4 { +- reg = <4>; +- label = "eth_fc_1000_4"; +- phy-mode = "1000base-x"; +- managed = "in-band-status"; +- sfp = <&sff3>; +- }; +- +- port@5 { +- reg = <5>; +- label = "eth_fc_1000_5"; +- phy-mode = "1000base-x"; +- managed = "in-band-status"; +- sfp = <&sff4>; +- }; +- +- port@6 { +- reg = <6>; +- label = "eth_fc_1000_6"; +- phy-mode = "1000base-x"; +- managed = "in-band-status"; +- sfp = <&sff5>; +- }; +- +- port@7 { +- reg = <7>; +- label = "eth_fc_1000_7"; +- phy-mode = "1000base-x"; +- managed = "in-band-status"; +- sfp = <&sff6>; +- }; +- +- port@9 { +- reg = <9>; +- label = "eth_fc_1000_1"; +- phy-mode = "1000base-x"; +- managed = "in-band-status"; +- sfp = <&sff0>; +- }; +- +- switch2port10: port@10 { +- reg = <10>; +- label = "dsa"; +- phy-mode = "2500base-x"; +- link = <&switch3port9 +- &switch1port9 +- &switch0port10>; +- }; +- }; +- }; +- }; +- +- mdio_mux_8: mdio@8 { +- reg = <8>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch3: switch3@0 { +- compatible = "marvell,mv88e6190"; +- reg = <0>; +- dsa,member = <0 3>; +- eeprom-length = <65536>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@2 { +- reg = <2>; +- label = "eth_fc_1000_8"; +- phy-mode = "1000base-x"; +- managed = "in-band-status"; +- sfp = <&sff7>; +- }; +- +- port@3 { +- reg = <3>; +- label = "eth_fc_1000_9"; +- phy-mode = "1000base-x"; +- managed = "in-band-status"; +- sfp = <&sff8>; +- }; +- +- port@4 { +- reg = <4>; +- label = "eth_fc_1000_10"; +- phy-mode = "1000base-x"; +- managed = "in-band-status"; +- sfp = <&sff9>; +- }; +- +- switch3port9: port@9 { +- reg = <9>; +- label = "dsa"; +- phy-mode = "2500base-x"; +- link = <&switch2port10>; +- }; +- +- switch3port10: port@10 { +- reg = <10>; +- label = "dsa"; +- phy-mode = "xgmii"; +- link = <&switch1port9 +- &switch0port10>; +- }; +- }; +- }; +- }; +- }; +- +- sff0: sff0 { +- compatible = "sff,sff"; +- i2c-bus = <&sff0_i2c>; +- los-gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>; +- tx-disable-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; +- }; +- +- sff1: sff1 { +- compatible = "sff,sff"; +- i2c-bus = <&sff1_i2c>; +- los-gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>; +- tx-disable-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; +- }; +- +- sff2: sff2 { +- compatible = "sff,sff"; +- i2c-bus = <&sff2_i2c>; +- los-gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; +- tx-disable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; +- }; +- +- sff3: sff3 { +- compatible = "sff,sff"; +- i2c-bus = <&sff3_i2c>; +- los-gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; +- tx-disable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; +- }; +- +- sff4: sff4 { +- compatible = "sff,sff"; +- i2c-bus = <&sff4_i2c>; +- los-gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>; +- tx-disable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; +- }; +- +- sff5: sff5 { +- compatible = "sff,sff"; +- i2c-bus = <&sff5_i2c>; +- los-gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>; +- tx-disable-gpios = <&gpio7 5 GPIO_ACTIVE_HIGH>; +- }; +- +- sff6: sff6 { +- compatible = "sff,sff"; +- i2c-bus = <&sff6_i2c>; +- los-gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>; +- tx-disable-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; +- }; +- +- sff7: sff7 { +- compatible = "sff,sff"; +- i2c-bus = <&sff7_i2c>; +- los-gpios = <&gpio9 7 GPIO_ACTIVE_HIGH>; +- tx-disable-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; +- }; +- +- sff8: sff8 { +- compatible = "sff,sff"; +- i2c-bus = <&sff8_i2c>; +- los-gpios = <&gpio9 8 GPIO_ACTIVE_HIGH>; +- tx-disable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; +- }; +- +- sff9: sff9 { +- compatible = "sff,sff"; +- i2c-bus = <&sff9_i2c>; +- los-gpios = <&gpio9 9 GPIO_ACTIVE_HIGH>; +- tx-disable-gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_3v3_mcu"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&dspi0 { +- pinctrl-0 = <&pinctrl_dspi0>; +- pinctrl-names = "default"; +- bus-num = <0>; +- status = "okay"; +- +- adc@5 { +- compatible = "holt,hi8435"; +- reg = <5>; +- gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; +- spi-max-frequency = <1000000>; +- }; +-}; +- +-&dspi1 { +- bus-num = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dspi1>; +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- +- partition@0 { +- label = "m25p128-0"; +- reg = <0x0 0x01000000>; +- }; +- }; +- +- flash@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <1>; +- spi-max-frequency = <50000000>; +- +- partition@0 { +- label = "m25p128-1"; +- reg = <0x0 0x01000000>; +- }; +- }; +-}; +- +-&adc0 { +- vref-supply = <®_vcc_3v3_mcu>; +- status = "okay"; +-}; +- +-&adc1 { +- vref-supply = <®_vcc_3v3_mcu>; +- status = "okay"; +-}; +- +-&edma0 { +- status = "okay"; +-}; +- +-&edma1 { +- status = "okay"; +-}; +- +-&esdhc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc0>; +- bus-width = <8>; +- non-removable; +- no-1-8-v; +- no-sd; +- no-sdio; +- keep-power-in-suspend; +- status = "okay"; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- bus-width = <4>; +- no-sdio; +- status = "okay"; +-}; +- +-&fec1 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- status = "okay"; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- +- mdio1: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +- +-&i2c0 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0>; +- status = "okay"; +- +- gpio5: io-expander@20 { +- compatible = "nxp,pca9554"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpio6: io-expander@22 { +- compatible = "nxp,pca9554"; +- reg = <0x22>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- temp-sensor@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c04"; +- reg = <0x50>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c04"; +- reg = <0x52>; +- }; +- +- elapsed-time-recorder@6b { +- compatible = "dallas,ds1682"; +- reg = <0x6b>; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- watchdog@38 { +- compatible = "zii,rave-wdt"; +- reg = <0x38>; +- }; +- +- adc@4a { +- compatible = "adi,adt7411"; +- reg = <0x4a>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- gpio9: io-expander@20 { +- compatible = "semtech,sx1503q"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sx1503_20>; +- #gpio-cells = <2>; +- reg = <0x20>; +- gpio-controller; +- interrupt-parent = <&gpio1>; +- interrupts = <31 IRQ_TYPE_EDGE_FALLING>; +- }; +- +- temp-sensor@4e { +- compatible = "national,lm75"; +- reg = <0x4e>; +- }; +- +- temp-sensor@4f { +- compatible = "national,lm75"; +- reg = <0x4f>; +- }; +- +- gpio7: io-expander@23 { +- compatible = "nxp,pca9555"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x23>; +- }; +- +- adc@4a { +- compatible = "adi,adt7411"; +- reg = <0x4a>; +- }; +- +- eeprom@54 { +- compatible = "atmel,24c08"; +- reg = <0x54>; +- }; +- +- i2c-mux@70 { +- compatible = "nxp,pca9548"; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- i2c-mux-idle-disconnect; +- +- sff0_i2c: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- sff1_i2c: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- sff2_i2c: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- sff3_i2c: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- sff4_i2c: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- }; +- +- i2c-mux@71 { +- compatible = "nxp,pca9548"; +- pinctrl-names = "default"; +- reg = <0x71>; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-mux-idle-disconnect; +- +- sff5_i2c: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- sff6_i2c: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- sff7_i2c: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- +- sff8_i2c: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- sff9_i2c: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- }; +-}; +- +-&snvsrtc { +- status = "disabled"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- status = "okay"; +-}; +- +-&uart1 { +- linux,rs485-enabled-at-boot-time; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- linux,rs485-enabled-at-boot-time; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_dspi0: dspi0grp { +- fsl,pins = < +- VF610_PAD_PTB19__DSPI0_CS0 0x1182 +- VF610_PAD_PTB18__DSPI0_CS1 0x1182 +- VF610_PAD_PTB13__DSPI0_CS4 0x1182 +- VF610_PAD_PTB12__DSPI0_CS5 0x1182 +- VF610_PAD_PTB20__DSPI0_SIN 0x1181 +- VF610_PAD_PTB21__DSPI0_SOUT 0x1182 +- VF610_PAD_PTB22__DSPI0_SCK 0x1182 +- >; +- }; +- +- pinctrl_dspi1: dspi1grp { +- fsl,pins = < +- VF610_PAD_PTD5__DSPI1_CS0 0x1182 +- VF610_PAD_PTD4__DSPI1_CS1 0x1182 +- VF610_PAD_PTC6__DSPI1_SIN 0x1181 +- VF610_PAD_PTC7__DSPI1_SOUT 0x1182 +- VF610_PAD_PTC8__DSPI1_SCK 0x1182 +- >; +- }; +- +- pinctrl_dspi2: dspi2gpio { +- fsl,pins = < +- VF610_PAD_PTD30__GPIO_64 0x33e2 +- VF610_PAD_PTD29__GPIO_65 0x33e1 +- VF610_PAD_PTD28__GPIO_66 0x33e2 +- VF610_PAD_PTD27__GPIO_67 0x33e2 +- VF610_PAD_PTD26__GPIO_68 0x31c2 +- >; +- }; +- +- pinctrl_esdhc0: esdhc0grp { +- fsl,pins = < +- VF610_PAD_PTC0__ESDHC0_CLK 0x31ef +- VF610_PAD_PTC1__ESDHC0_CMD 0x31ef +- VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef +- VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef +- VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef +- VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef +- VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef +- VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef +- VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef +- VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- VF610_PAD_PTA24__ESDHC1_CLK 0x31ef +- VF610_PAD_PTA25__ESDHC1_CMD 0x31ef +- VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef +- VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef +- VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef +- VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- VF610_PAD_PTA6__RMII_CLKIN 0x30d1 +- VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 +- VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 +- VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 +- VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 +- VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 +- VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 +- VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 +- VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 +- VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 +- >; +- }; +- +- pinctrl_i2c0: i2c0grp { +- fsl,pins = < +- VF610_PAD_PTB14__I2C0_SCL 0x37ff +- VF610_PAD_PTB15__I2C0_SDA 0x37ff +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- VF610_PAD_PTB16__I2C1_SCL 0x37ff +- VF610_PAD_PTB17__I2C1_SDA 0x37ff +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- VF610_PAD_PTA22__I2C2_SCL 0x37ff +- VF610_PAD_PTA23__I2C2_SDA 0x37ff +- >; +- }; +- +- pinctrl_leds_debug: pinctrl-leds-debug { +- fsl,pins = < +- VF610_PAD_PTB26__GPIO_96 0x31c2 +- >; +- }; +- +- pinctrl_mdio_mux: pinctrl-mdio-mux { +- fsl,pins = < +- VF610_PAD_PTE27__GPIO_132 0x31c2 +- VF610_PAD_PTE28__GPIO_133 0x31c2 +- VF610_PAD_PTE21__GPIO_126 0x31c2 +- VF610_PAD_PTE22__GPIO_127 0x31c2 +- >; +- }; +- +- pinctrl_qspi0: qspi0grp { +- fsl,pins = < +- VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3 +- VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff +- VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3 +- VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3 +- VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3 +- VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3 +- >; +- }; +- +- pinctrl_sx1503_20: pinctrl-sx1503-20 { +- fsl,pins = < +- VF610_PAD_PTD31__GPIO_63 0x219d +- >; +- }; +- +- pinctrl_uart0: uart0grp { +- fsl,pins = < +- VF610_PAD_PTB10__UART0_TX 0x21a2 +- VF610_PAD_PTB11__UART0_RX 0x21a1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- VF610_PAD_PTB23__UART1_TX 0x21a2 +- VF610_PAD_PTB24__UART1_RX 0x21a1 +- VF610_PAD_PTB25__UART1_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */ +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- VF610_PAD_PTD0__UART2_TX 0x21a2 +- VF610_PAD_PTD1__UART2_RX 0x21a1 +- VF610_PAD_PTD2__UART2_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */ +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf610-zii-spb4.dts b/scripts/dtc/include-prefixes/arm/vf610-zii-spb4.dts +deleted file mode 100644 +index 6c6ec46fd015..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf610-zii-spb4.dts ++++ /dev/null +@@ -1,379 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +- +-/* +- * Device tree file for ZII's SPB4 board +- * +- * SPB - Seat Power Box +- * +- * Copyright (C) 2019 Zodiac Inflight Innovations +- */ +- +-/dts-v1/; +-#include "vf610.dtsi" +- +-/ { +- model = "ZII VF610 SPB4 Board"; +- compatible = "zii,vf610spb4", "zii,vf610dev", "fsl,vf610"; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pinctrl_leds_debug>; +- pinctrl-names = "default"; +- +- led-debug { +- label = "zii:green:debug1"; +- gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_3v3_mcu"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- supply-voltage-monitor { +- compatible = "iio-hwmon"; +- io-channels = <&adc0 8>, /* 28V_SW */ +- <&adc0 9>, /* +3.3V */ +- <&adc1 8>, /* VCC_1V5 */ +- <&adc1 9>; /* VCC_1V2 */ +- }; +-}; +- +-&adc0 { +- vref-supply = <®_vcc_3v3_mcu>; +- status = "okay"; +-}; +- +-&adc1 { +- vref-supply = <®_vcc_3v3_mcu>; +- status = "okay"; +-}; +- +-&dspi1 { +- bus-num = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dspi1>; +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p128", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- }; +-}; +- +-&edma0 { +- status = "okay"; +-}; +- +-&edma1 { +- status = "okay"; +-}; +- +-&esdhc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc0>; +- bus-width = <8>; +- non-removable; +- no-1-8-v; +- keep-power-in-suspend; +- no-sdio; +- no-sd; +- status = "okay"; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- bus-width = <4>; +- no-sdio; +- status = "okay"; +-}; +- +-&fec1 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- status = "okay"; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- +- mdio1: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <12500000>; +- suppress-preamble; +- status = "okay"; +- +- switch0: switch0@0 { +- compatible = "marvell,mv88e6190"; +- pinctrl-0 = <&pinctrl_gpio_switch0>; +- pinctrl-names = "default"; +- reg = <0>; +- eeprom-length = <65536>; +- interrupt-parent = <&gpio3>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "cpu"; +- ethernet = <&fec1>; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +- +- port@1 { +- reg = <1>; +- label = "eth_cu_1000_1"; +- }; +- +- port@2 { +- reg = <2>; +- label = "eth_cu_1000_2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "eth_cu_1000_3"; +- }; +- +- port@4 { +- reg = <4>; +- label = "eth_cu_1000_4"; +- }; +- +- port@5 { +- reg = <5>; +- label = "eth_cu_1000_5"; +- }; +- +- port@6 { +- reg = <6>; +- label = "eth_cu_1000_6"; +- }; +- }; +- }; +- }; +-}; +- +-&i2c0 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0>; +- status = "okay"; +- +- io-expander@22 { +- compatible = "nxp,pca9554"; +- reg = <0x22>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c04"; +- reg = <0x50>; +- label = "nameplate"; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c04"; +- reg = <0x52>; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- watchdog@38 { +- compatible = "zii,rave-wdt"; +- reg = <0x38>; +- }; +-}; +- +-&snvsrtc { +- status = "disabled"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +- +- rave-sp { +- compatible = "zii,rave-sp-rdu2"; +- current-speed = <1000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- watchdog { +- compatible = "zii,rave-sp-watchdog"; +- }; +- +- eeprom@a3 { +- compatible = "zii,rave-sp-eeprom"; +- reg = <0xa3 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- zii,eeprom-name = "main-eeprom"; +- }; +- }; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&wdoga5 { +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_dspi1: dspi1grp { +- fsl,pins = < +- VF610_PAD_PTD5__DSPI1_CS0 0x1182 +- VF610_PAD_PTD4__DSPI1_CS1 0x1182 +- VF610_PAD_PTC6__DSPI1_SIN 0x1181 +- VF610_PAD_PTC7__DSPI1_SOUT 0x1182 +- VF610_PAD_PTC8__DSPI1_SCK 0x1182 +- >; +- }; +- +- pinctrl_esdhc0: esdhc0grp { +- fsl,pins = < +- VF610_PAD_PTC0__ESDHC0_CLK 0x31ef +- VF610_PAD_PTC1__ESDHC0_CMD 0x31ef +- VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef +- VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef +- VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef +- VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef +- VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef +- VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef +- VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef +- VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- VF610_PAD_PTA24__ESDHC1_CLK 0x31ef +- VF610_PAD_PTA25__ESDHC1_CMD 0x31ef +- VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef +- VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef +- VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef +- VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- VF610_PAD_PTA6__RMII_CLKIN 0x30d1 +- VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 +- VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 +- VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 +- VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 +- VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 +- VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 +- VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 +- VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 +- VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 +- >; +- }; +- +- pinctrl_gpio_switch0: pinctrl-gpio-switch0 { +- fsl,pins = < +- VF610_PAD_PTB28__GPIO_98 0x219d +- >; +- }; +- +- pinctrl_i2c0: i2c0grp { +- fsl,pins = < +- VF610_PAD_PTB14__I2C0_SCL 0x37ff +- VF610_PAD_PTB15__I2C0_SDA 0x37ff +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- VF610_PAD_PTB16__I2C1_SCL 0x37ff +- VF610_PAD_PTB17__I2C1_SDA 0x37ff +- >; +- }; +- +- pinctrl_leds_debug: pinctrl-leds-debug { +- fsl,pins = < +- VF610_PAD_PTD3__GPIO_82 0x31c2 +- >; +- }; +- +- pinctrl_uart0: uart0grp { +- fsl,pins = < +- VF610_PAD_PTB10__UART0_TX 0x21a2 +- VF610_PAD_PTB11__UART0_RX 0x21a1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- VF610_PAD_PTB23__UART1_TX 0x21a2 +- VF610_PAD_PTB24__UART1_RX 0x21a1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- VF610_PAD_PTD0__UART2_TX 0x21a2 +- VF610_PAD_PTD1__UART2_RX 0x21a1 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- VF610_PAD_PTA30__UART3_TX 0x21a2 +- VF610_PAD_PTA31__UART3_RX 0x21a1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf610-zii-ssmb-dtu.dts b/scripts/dtc/include-prefixes/arm/vf610-zii-ssmb-dtu.dts +deleted file mode 100644 +index 73fdace4cb42..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf610-zii-ssmb-dtu.dts ++++ /dev/null +@@ -1,325 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +- +-/* +- * Device tree file for ZII's SSMB DTU board +- * +- * SSMB - SPU3 Switch Management Board +- * DTU - Digital Tapping Unit +- * +- * Copyright (C) 2015-2019 Zodiac Inflight Innovations +- * +- * Based on an original 'vf610-twr.dts' which is Copyright 2015, +- * Freescale Semiconductor, Inc. +- */ +- +-/dts-v1/; +-#include "vf610.dtsi" +- +-/ { +- model = "ZII VF610 SSMB DTU Board"; +- compatible = "zii,vf610dtu", "zii,vf610dev", "fsl,vf610"; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pinctrl_leds_debug>; +- pinctrl-names = "default"; +- +- led-debug { +- label = "zii:green:debug1"; +- gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- reg_vcc_3v3_mcu: regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_3v3_mcu"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- supply-voltage-monitor { +- compatible = "iio-hwmon"; +- io-channels = <&adc0 8>, /* 12V_MAIN */ +- <&adc0 9>, /* +3.3V */ +- <&adc1 8>, /* VCC_1V5 */ +- <&adc1 9>; /* VCC_1V2 */ +- }; +-}; +- +-&adc0 { +- vref-supply = <®_vcc_3v3_mcu>; +- status = "okay"; +-}; +- +-&adc1 { +- vref-supply = <®_vcc_3v3_mcu>; +- status = "okay"; +-}; +- +-&edma0 { +- status = "okay"; +-}; +- +-&edma1 { +- status = "okay"; +-}; +- +-&esdhc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc0>; +- bus-width = <8>; +- non-removable; +- no-1-8-v; +- keep-power-in-suspend; +- no-sdio; +- no-sd; +- status = "okay"; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- bus-width = <4>; +- no-sdio; +- status = "okay"; +-}; +- +-&fec1 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- status = "okay"; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- +- mdio1: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <12500000>; +- suppress-preamble; +- status = "okay"; +- +- switch0: switch0@0 { +- compatible = "marvell,mv88e6190"; +- pinctrl-0 = <&pinctrl_gpio_switch0>; +- pinctrl-names = "default"; +- reg = <0>; +- eeprom-length = <65536>; +- interrupt-parent = <&gpio3>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "cpu"; +- ethernet = <&fec1>; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +- +- port@1 { +- reg = <1>; +- label = "eth_cu_100_3"; +- }; +- +- port@5 { +- reg = <5>; +- label = "eth_cu_1000_4"; +- }; +- +- port@6 { +- reg = <6>; +- label = "eth_cu_1000_5"; +- }; +- +- port@8 { +- reg = <8>; +- label = "eth_cu_1000_1"; +- }; +- +- port@9 { +- reg = <9>; +- label = "eth_cu_1000_2"; +- phy-handle = <&phy9>; +- phy-mode = "sgmii"; +- managed = "in-band-status"; +- }; +- }; +- +- mdio1 { +- compatible = "marvell,mv88e6xxx-mdio-external"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy9: phy9@0 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- pinctrl-0 = <&pinctrl_gpio_phy9>; +- pinctrl-names = "default"; +- interrupt-parent = <&gpio2>; +- interrupts = <30 IRQ_TYPE_LEVEL_LOW>; +- reg = <0>; +- }; +- }; +- }; +- }; +-}; +- +-&i2c0 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0>; +- status = "okay"; +- +- gpio6: gpio-expander@22 { +- compatible = "nxp,pca9554"; +- reg = <0x22>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- /* On SSMB */ +- temperature-sensor@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +- +- /* On DSB */ +- temperature-sensor@4d { +- compatible = "national,lm75"; +- reg = <0x4d>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c04"; +- reg = <0x50>; +- label = "nameplate"; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c04"; +- reg = <0x52>; +- }; +-}; +- +-&snvsrtc { +- status = "disabled"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_dspi1: dspi1grp { +- fsl,pins = < +- VF610_PAD_PTD5__DSPI1_CS0 0x1182 +- VF610_PAD_PTD4__DSPI1_CS1 0x1182 +- VF610_PAD_PTC6__DSPI1_SIN 0x1181 +- VF610_PAD_PTC7__DSPI1_SOUT 0x1182 +- VF610_PAD_PTC8__DSPI1_SCK 0x1182 +- >; +- }; +- +- pinctrl_esdhc0: esdhc0grp { +- fsl,pins = < +- VF610_PAD_PTC0__ESDHC0_CLK 0x31ef +- VF610_PAD_PTC1__ESDHC0_CMD 0x31ef +- VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef +- VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef +- VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef +- VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef +- VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef +- VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef +- VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef +- VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- VF610_PAD_PTA24__ESDHC1_CLK 0x31ef +- VF610_PAD_PTA25__ESDHC1_CMD 0x31ef +- VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef +- VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef +- VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef +- VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- VF610_PAD_PTA6__RMII_CLKIN 0x30d1 +- VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 +- VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 +- VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 +- VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 +- VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 +- VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 +- VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 +- VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 +- VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 +- >; +- }; +- +- pinctrl_gpio_phy9: pinctrl-gpio-phy9 { +- fsl,pins = < +- VF610_PAD_PTB24__GPIO_94 0x219d +- >; +- }; +- +- pinctrl_gpio_switch0: pinctrl-gpio-switch0 { +- fsl,pins = < +- VF610_PAD_PTB28__GPIO_98 0x219d +- >; +- }; +- +- pinctrl_i2c0: i2c0grp { +- fsl,pins = < +- VF610_PAD_PTB14__I2C0_SCL 0x37ff +- VF610_PAD_PTB15__I2C0_SDA 0x37ff +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- VF610_PAD_PTB16__I2C1_SCL 0x37ff +- VF610_PAD_PTB17__I2C1_SDA 0x37ff +- >; +- }; +- +- pinctrl_leds_debug: pinctrl-leds-debug { +- fsl,pins = < +- VF610_PAD_PTD3__GPIO_82 0x31c2 +- >; +- }; +- +- pinctrl_uart0: uart0grp { +- fsl,pins = < +- VF610_PAD_PTB10__UART0_TX 0x21a2 +- VF610_PAD_PTB11__UART0_RX 0x21a1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf610-zii-ssmb-spu3.dts b/scripts/dtc/include-prefixes/arm/vf610-zii-ssmb-spu3.dts +deleted file mode 100644 +index fe600ab2e4bd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf610-zii-ssmb-spu3.dts ++++ /dev/null +@@ -1,372 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +- +-/* +- * Device tree file for ZII's SSMB SPU3 board +- * +- * SSMB - SPU3 Switch Management Board +- * SPU - Seat Power Unit +- * +- * Copyright (C) 2015, 2016 Zodiac Inflight Innovations +- * +- * Based on an original 'vf610-twr.dts' which is Copyright 2015, +- * Freescale Semiconductor, Inc. +- */ +- +-/dts-v1/; +-#include "vf610.dtsi" +- +-/ { +- model = "ZII VF610 SSMB SPU3 Board"; +- compatible = "zii,vf610spu3", "zii,vf610dev", "fsl,vf610"; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000>; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&pinctrl_leds_debug>; +- pinctrl-names = "default"; +- +- led-debug { +- label = "zii:green:debug1"; +- gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- reg_vcc_3v3_mcu: regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_3v3_mcu"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- supply-voltage-monitor { +- compatible = "iio-hwmon"; +- io-channels = <&adc0 8>, /* 12V_MAIN */ +- <&adc0 9>, /* +3.3V */ +- <&adc1 8>, /* VCC_1V5 */ +- <&adc1 9>; /* VCC_1V2 */ +- }; +-}; +- +-&adc0 { +- vref-supply = <®_vcc_3v3_mcu>; +- status = "okay"; +-}; +- +-&adc1 { +- vref-supply = <®_vcc_3v3_mcu>; +- status = "okay"; +-}; +- +-&dspi1 { +- bus-num = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dspi1>; +- /* +- * Some SPU3s come with SPI-NOR chip DNPed, so we leave this +- * node disabled by default and rely on bootloader to enable +- * it when appropriate. +- */ +- status = "disabled"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p128", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- +- partition@0 { +- label = "m25p128-0"; +- reg = <0x0 0x01000000>; +- }; +- }; +-}; +- +-&edma0 { +- status = "okay"; +-}; +- +-&edma1 { +- status = "okay"; +-}; +- +-&esdhc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc0>; +- bus-width = <8>; +- non-removable; +- no-1-8-v; +- keep-power-in-suspend; +- no-sdio; +- no-sd; +- status = "okay"; +-}; +- +-&esdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_esdhc1>; +- bus-width = <4>; +- no-sdio; +- status = "okay"; +-}; +- +-&fec1 { +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- status = "okay"; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- +- mdio1: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <12500000>; +- suppress-preamble; +- status = "okay"; +- +- switch0: switch0@0 { +- compatible = "marvell,mv88e6190"; +- pinctrl-0 = <&pinctrl_gpio_switch0>; +- pinctrl-names = "default"; +- reg = <0>; +- eeprom-length = <65536>; +- interrupt-parent = <&gpio3>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "cpu"; +- ethernet = <&fec1>; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +- +- port@1 { +- reg = <1>; +- label = "eth_cu_1000_1"; +- }; +- +- port@2 { +- reg = <2>; +- label = "eth_cu_1000_2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "eth_cu_1000_3"; +- }; +- +- port@4 { +- reg = <4>; +- label = "eth_cu_1000_4"; +- }; +- +- port@5 { +- reg = <5>; +- label = "eth_cu_1000_5"; +- }; +- +- port@6 { +- reg = <6>; +- label = "eth_cu_1000_6"; +- }; +- }; +- }; +- }; +-}; +- +-&i2c0 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0>; +- status = "okay"; +- +- gpio6: io-expander@22 { +- compatible = "nxp,pca9554"; +- reg = <0x22>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- lm75@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c04"; +- reg = <0x50>; +- label = "nameplate"; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c04"; +- reg = <0x52>; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- watchdog@38 { +- compatible = "zii,rave-wdt"; +- reg = <0x38>; +- }; +-}; +- +-&snvsrtc { +- status = "disabled"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +- +- rave-sp { +- compatible = "zii,rave-sp-rdu2"; +- current-speed = <1000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- watchdog { +- compatible = "zii,rave-sp-watchdog"; +- }; +- +- eeprom@a3 { +- compatible = "zii,rave-sp-eeprom"; +- reg = <0xa3 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- zii,eeprom-name = "main-eeprom"; +- }; +- }; +-}; +- +-&wdoga5 { +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_dspi1: dspi1grp { +- fsl,pins = < +- VF610_PAD_PTD5__DSPI1_CS0 0x1182 +- VF610_PAD_PTD4__DSPI1_CS1 0x1182 +- VF610_PAD_PTC6__DSPI1_SIN 0x1181 +- VF610_PAD_PTC7__DSPI1_SOUT 0x1182 +- VF610_PAD_PTC8__DSPI1_SCK 0x1182 +- >; +- }; +- +- pinctrl_esdhc0: esdhc0grp { +- fsl,pins = < +- VF610_PAD_PTC0__ESDHC0_CLK 0x31ef +- VF610_PAD_PTC1__ESDHC0_CMD 0x31ef +- VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef +- VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef +- VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef +- VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef +- VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef +- VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef +- VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef +- VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef +- >; +- }; +- +- pinctrl_esdhc1: esdhc1grp { +- fsl,pins = < +- VF610_PAD_PTA24__ESDHC1_CLK 0x31ef +- VF610_PAD_PTA25__ESDHC1_CMD 0x31ef +- VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef +- VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef +- VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef +- VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- VF610_PAD_PTA6__RMII_CLKIN 0x30d1 +- VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 +- VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 +- VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 +- VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 +- VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 +- VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 +- VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 +- VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 +- VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 +- >; +- }; +- +- pinctrl_gpio_switch0: pinctrl-gpio-switch0 { +- fsl,pins = < +- VF610_PAD_PTB28__GPIO_98 0x219d +- >; +- }; +- +- pinctrl_i2c0: i2c0grp { +- fsl,pins = < +- VF610_PAD_PTB14__I2C0_SCL 0x37ff +- VF610_PAD_PTB15__I2C0_SDA 0x37ff +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- VF610_PAD_PTB16__I2C1_SCL 0x37ff +- VF610_PAD_PTB17__I2C1_SDA 0x37ff +- >; +- }; +- +- pinctrl_leds_debug: pinctrl-leds-debug { +- fsl,pins = < +- VF610_PAD_PTD3__GPIO_82 0x31c2 +- >; +- }; +- +- pinctrl_uart0: uart0grp { +- fsl,pins = < +- VF610_PAD_PTB10__UART0_TX 0x21a2 +- VF610_PAD_PTB11__UART0_RX 0x21a1 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- VF610_PAD_PTB23__UART1_TX 0x21a2 +- VF610_PAD_PTB24__UART1_RX 0x21a1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf610.dtsi b/scripts/dtc/include-prefixes/arm/vf610.dtsi +deleted file mode 100644 +index 956182d08e74..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf610.dtsi ++++ /dev/null +@@ -1,21 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright 2013 Freescale Semiconductor, Inc. +- +- +-#include "vf500.dtsi" +- +-&a5_cpu { +- next-level-cache = <&L2>; +-}; +- +-&aips0 { +- L2: cache-controller@40006000 { +- compatible = "arm,pl310-cache"; +- reg = <0x40006000 0x1000>; +- cache-unified; +- cache-level = <2>; +- arm,data-latency = <3 3 3>; +- arm,tag-latency = <2 2 2>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf610m4-colibri.dts b/scripts/dtc/include-prefixes/arm/vf610m4-colibri.dts +deleted file mode 100644 +index 2c2db47af441..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf610m4-colibri.dts ++++ /dev/null +@@ -1,63 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Device tree for Colibri VF61 Cortex-M4 support +- * +- * Copyright (C) 2015 Stefan Agner +- */ +- +-/dts-v1/; +-#include "vf610m4.dtsi" +- +-/ { +- model = "VF610 Cortex-M4"; +- compatible = "fsl,vf610m4"; +- +- chosen { +- bootargs = "clk_ignore_unused init=/linuxrc rw"; +- stdout-path = "serial2:115200"; +- }; +- +- memory@8c000000 { +- device_type = "memory"; +- reg = <0x8c000000 0x3000000>; +- }; +-}; +- +-&gpio0 { +- status = "disabled"; +-}; +- +-&gpio1 { +- status = "disabled"; +-}; +- +-&gpio2 { +- status = "disabled"; +-}; +- +-&gpio3 { +- status = "disabled"; +-}; +- +-&gpio4 { +- status = "disabled"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&iomuxc { +- vf610-colibri { +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- VF610_PAD_PTD0__UART2_TX 0x21a2 +- VF610_PAD_PTD1__UART2_RX 0x21a1 +- VF610_PAD_PTD2__UART2_RTS 0x21a2 +- VF610_PAD_PTD3__UART2_CTS 0x21a1 +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf610m4-cosmic.dts b/scripts/dtc/include-prefixes/arm/vf610m4-cosmic.dts +deleted file mode 100644 +index f7474c11aabd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf610m4-cosmic.dts ++++ /dev/null +@@ -1,90 +0,0 @@ +-/* +- * Device tree for Cosmic+ VF6xx Cortex-M4 support +- * +- * Copyright (C) 2015 +- * +- * Based on vf610m4 Colibri +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +-#include "vf610m4.dtsi" +- +-/ { +- model = "VF610 Cortex-M4"; +- compatible = "fsl,vf610m4"; +-}; +- +-&gpio0 { +- status = "disabled"; +-}; +- +-&gpio1 { +- status = "disabled"; +-}; +- +-&gpio2 { +- status = "disabled"; +-}; +- +-&gpio3 { +- status = "disabled"; +-}; +- +-&gpio4 { +- status = "disabled"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&iomuxc { +- vf610-cosmic { +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- VF610_PAD_PTA20__UART3_TX 0x21a2 +- VF610_PAD_PTA21__UART3_RX 0x21a1 +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vf610m4.dtsi b/scripts/dtc/include-prefixes/arm/vf610m4.dtsi +deleted file mode 100644 +index 76bbfd5e32b6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vf610m4.dtsi ++++ /dev/null +@@ -1,57 +0,0 @@ +-/* +- * Device tree for VF6xx Cortex-M4 support +- * +- * Copyright (C) 2015 Stefan Agner +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "armv7-m.dtsi" +-#include "vfxxx.dtsi" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- chosen { }; +- aliases { }; +-}; +- +-&mscm_ir { +- interrupt-parent = <&nvic>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vfxxx.dtsi b/scripts/dtc/include-prefixes/arm/vfxxx.dtsi +deleted file mode 100644 +index d53f9c9db8bf..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vfxxx.dtsi ++++ /dev/null +@@ -1,756 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Copyright 2013 Freescale Semiconductor, Inc. +- +-#include "vf610-pinfunc.h" +-#include +-#include +-#include +- +-/ { +- aliases { +- can0 = &can0; +- can1 = &can1; +- ethernet0 = &fec0; +- ethernet1 = &fec1; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- serial5 = &uart5; +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- gpio2 = &gpio2; +- gpio3 = &gpio3; +- gpio4 = &gpio4; +- usbphy0 = &usbphy0; +- usbphy1 = &usbphy1; +- }; +- +- fxosc: fxosc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- }; +- +- sxosc: sxosc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- reboot: syscon-reboot { +- compatible = "syscon-reboot"; +- regmap = <&src>; +- offset = <0x0>; +- mask = <0x1000>; +- }; +- +- tempsensor: iio-hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc0 16>, <&adc1 16>; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- interrupt-parent = <&mscm_ir>; +- ranges; +- +- aips0: bus@40000000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x40000000 0x00070000>; +- ranges; +- +- mscm_cpucfg: cpucfg@40001000 { +- compatible = "fsl,vf610-mscm-cpucfg", "syscon"; +- reg = <0x40001000 0x800>; +- }; +- +- mscm_ir: interrupt-controller@40001800 { +- compatible = "fsl,vf610-mscm-ir"; +- reg = <0x40001800 0x400>; +- fsl,cpucfg = <&mscm_cpucfg>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- edma0: dma-controller@40018000 { +- #dma-cells = <2>; +- compatible = "fsl,vf610-edma"; +- reg = <0x40018000 0x2000>, +- <0x40024000 0x1000>, +- <0x40025000 0x1000>; +- dma-channels = <32>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, +- <9 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "edma-tx", "edma-err"; +- clock-names = "dmamux0", "dmamux1"; +- clocks = <&clks VF610_CLK_DMAMUX0>, +- <&clks VF610_CLK_DMAMUX1>; +- status = "disabled"; +- }; +- +- can0: can@40020000 { +- compatible = "fsl,vf610-flexcan"; +- reg = <0x40020000 0x4000>; +- interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_FLEXCAN0>, +- <&clks VF610_CLK_FLEXCAN0>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart0: serial@40027000 { +- compatible = "fsl,vf610-lpuart"; +- reg = <0x40027000 0x1000>; +- interrupts = <61 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_UART0>; +- clock-names = "ipg"; +- dmas = <&edma0 0 2>, +- <&edma0 0 3>; +- dma-names = "rx","tx"; +- status = "disabled"; +- }; +- +- uart1: serial@40028000 { +- compatible = "fsl,vf610-lpuart"; +- reg = <0x40028000 0x1000>; +- interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_UART1>; +- clock-names = "ipg"; +- dmas = <&edma0 0 4>, +- <&edma0 0 5>; +- dma-names = "rx","tx"; +- status = "disabled"; +- }; +- +- uart2: serial@40029000 { +- compatible = "fsl,vf610-lpuart"; +- reg = <0x40029000 0x1000>; +- interrupts = <63 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_UART2>; +- clock-names = "ipg"; +- dmas = <&edma0 0 6>, +- <&edma0 0 7>; +- dma-names = "rx","tx"; +- status = "disabled"; +- }; +- +- uart3: serial@4002a000 { +- compatible = "fsl,vf610-lpuart"; +- reg = <0x4002a000 0x1000>; +- interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_UART3>; +- clock-names = "ipg"; +- dmas = <&edma0 0 8>, +- <&edma0 0 9>; +- dma-names = "rx","tx"; +- status = "disabled"; +- }; +- +- dspi0: spi@4002c000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,vf610-dspi"; +- reg = <0x4002c000 0x1000>; +- interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_DSPI0>; +- clock-names = "dspi"; +- spi-num-chipselects = <6>; +- dmas = <&edma1 1 12>, +- <&edma1 1 13>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- dspi1: spi@4002d000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,vf610-dspi"; +- reg = <0x4002d000 0x1000>; +- interrupts = <68 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_DSPI1>; +- clock-names = "dspi"; +- spi-num-chipselects = <4>; +- dmas = <&edma1 1 14>, +- <&edma1 1 15>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sai0: sai@4002f000 { +- compatible = "fsl,vf610-sai"; +- reg = <0x4002f000 0x1000>; +- interrupts = <84 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_SAI0>, +- <&clks VF610_CLK_SAI0_DIV>, +- <&clks 0>, <&clks 0>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dma-names = "tx", "rx"; +- dmas = <&edma0 0 17>, +- <&edma0 0 16>; +- status = "disabled"; +- }; +- +- sai1: sai@40030000 { +- compatible = "fsl,vf610-sai"; +- reg = <0x40030000 0x1000>; +- interrupts = <85 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_SAI1>, +- <&clks VF610_CLK_SAI1_DIV>, +- <&clks 0>, <&clks 0>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dma-names = "tx", "rx"; +- dmas = <&edma0 0 19>, +- <&edma0 0 18>; +- status = "disabled"; +- }; +- +- sai2: sai@40031000 { +- compatible = "fsl,vf610-sai"; +- reg = <0x40031000 0x1000>; +- interrupts = <86 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_SAI2>, +- <&clks VF610_CLK_SAI2_DIV>, +- <&clks 0>, <&clks 0>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dma-names = "tx", "rx"; +- dmas = <&edma0 0 21>, +- <&edma0 0 20>; +- status = "disabled"; +- }; +- +- sai3: sai@40032000 { +- compatible = "fsl,vf610-sai"; +- reg = <0x40032000 0x1000>; +- interrupts = <87 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_SAI3>, +- <&clks VF610_CLK_SAI3_DIV>, +- <&clks 0>, <&clks 0>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dma-names = "tx", "rx"; +- dmas = <&edma0 1 9>, +- <&edma0 1 8>; +- status = "disabled"; +- }; +- +- pit: pit@40037000 { +- compatible = "fsl,vf610-pit"; +- reg = <0x40037000 0x1000>; +- interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_PIT>; +- clock-names = "pit"; +- }; +- +- pwm0: pwm@40038000 { +- compatible = "fsl,vf610-ftm-pwm"; +- #pwm-cells = <3>; +- reg = <0x40038000 0x1000>; +- clock-names = "ftm_sys", "ftm_ext", +- "ftm_fix", "ftm_cnt_clk_en"; +- clocks = <&clks VF610_CLK_FTM0>, +- <&clks VF610_CLK_FTM0_EXT_SEL>, +- <&clks VF610_CLK_FTM0_FIX_SEL>, +- <&clks VF610_CLK_FTM0_EXT_FIX_EN>; +- status = "disabled"; +- }; +- +- pwm1: pwm@40039000 { +- compatible = "fsl,vf610-ftm-pwm"; +- #pwm-cells = <3>; +- reg = <0x40039000 0x1000>; +- clock-names = "ftm_sys", "ftm_ext", +- "ftm_fix", "ftm_cnt_clk_en"; +- clocks = <&clks VF610_CLK_FTM1>, +- <&clks VF610_CLK_FTM1_EXT_SEL>, +- <&clks VF610_CLK_FTM1_FIX_SEL>, +- <&clks VF610_CLK_FTM1_EXT_FIX_EN>; +- status = "disabled"; +- }; +- +- adc0: adc@4003b000 { +- compatible = "fsl,vf610-adc"; +- reg = <0x4003b000 0x1000>; +- interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_ADC0>; +- clock-names = "adc"; +- #io-channel-cells = <1>; +- status = "disabled"; +- fsl,adck-max-frequency = <30000000>, <40000000>, +- <20000000>; +- }; +- +- tcon0: timing-controller@4003d000 { +- compatible = "fsl,vf610-tcon"; +- reg = <0x4003d000 0x1000>; +- clocks = <&clks VF610_CLK_TCON0>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- wdoga5: watchdog@4003e000 { +- compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; +- reg = <0x4003e000 0x1000>; +- interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_WDT>; +- clock-names = "wdog"; +- status = "disabled"; +- }; +- +- qspi0: spi@40044000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,vf610-qspi"; +- reg = <0x40044000 0x1000>, <0x20000000 0x10000000>; +- reg-names = "QuadSPI", "QuadSPI-memory"; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_QSPI0_EN>, +- <&clks VF610_CLK_QSPI0>; +- clock-names = "qspi_en", "qspi"; +- status = "disabled"; +- }; +- +- iomuxc: iomuxc@40048000 { +- compatible = "fsl,vf610-iomuxc"; +- reg = <0x40048000 0x1000>; +- }; +- +- gpio0: gpio@40049000 { +- compatible = "fsl,vf610-gpio"; +- reg = <0x40049000 0x1000 0x400ff000 0x40>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 0 32>; +- }; +- +- gpio1: gpio@4004a000 { +- compatible = "fsl,vf610-gpio"; +- reg = <0x4004a000 0x1000 0x400ff040 0x40>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = <108 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 32 32>; +- }; +- +- gpio2: gpio@4004b000 { +- compatible = "fsl,vf610-gpio"; +- reg = <0x4004b000 0x1000 0x400ff080 0x40>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 64 32>; +- }; +- +- gpio3: gpio@4004c000 { +- compatible = "fsl,vf610-gpio"; +- reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = <110 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 96 32>; +- }; +- +- gpio4: gpio@4004d000 { +- compatible = "fsl,vf610-gpio"; +- reg = <0x4004d000 0x1000 0x400ff100 0x40>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 128 7>; +- }; +- +- anatop: anatop@40050000 { +- compatible = "fsl,vf610-anatop", "syscon"; +- reg = <0x40050000 0x400>; +- }; +- +- usbphy0: usbphy@40050800 { +- compatible = "fsl,vf610-usbphy"; +- reg = <0x40050800 0x400>; +- interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_USBPHY0>; +- fsl,anatop = <&anatop>; +- status = "disabled"; +- }; +- +- usbphy1: usbphy@40050c00 { +- compatible = "fsl,vf610-usbphy"; +- reg = <0x40050c00 0x400>; +- interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_USBPHY1>; +- fsl,anatop = <&anatop>; +- status = "disabled"; +- }; +- +- dcu0: dcu@40058000 { +- compatible = "fsl,vf610-dcu"; +- reg = <0x40058000 0x1200>; +- interrupts = <30 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_DCU0>, +- <&clks VF610_CLK_DCU0_DIV>; +- clock-names = "dcu", "pix"; +- fsl,tcon = <&tcon0>; +- status = "disabled"; +- }; +- +- i2c0: i2c@40066000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,vf610-i2c"; +- reg = <0x40066000 0x1000>; +- interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_I2C0>; +- clock-names = "ipg"; +- dmas = <&edma0 0 50>, +- <&edma0 0 51>; +- dma-names = "rx","tx"; +- status = "disabled"; +- }; +- +- i2c1: i2c@40067000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,vf610-i2c"; +- reg = <0x40067000 0x1000>; +- interrupts = <72 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_I2C1>; +- clock-names = "ipg"; +- dmas = <&edma0 0 52>, +- <&edma0 0 53>; +- dma-names = "rx","tx"; +- status = "disabled"; +- }; +- +- clks: ccm@4006b000 { +- compatible = "fsl,vf610-ccm"; +- reg = <0x4006b000 0x1000>; +- clocks = <&sxosc>, <&fxosc>; +- clock-names = "sxosc", "fxosc"; +- #clock-cells = <1>; +- }; +- +- usbdev0: usb@40034000 { +- compatible = "fsl,vf610-usb", "fsl,imx27-usb"; +- reg = <0x40034000 0x800>; +- interrupts = <75 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_USBC0>; +- fsl,usbphy = <&usbphy0>; +- fsl,usbmisc = <&usbmisc0 0>; +- dr_mode = "peripheral"; +- status = "disabled"; +- }; +- +- usbmisc0: usb@40034800 { +- #index-cells = <1>; +- compatible = "fsl,vf610-usbmisc"; +- reg = <0x40034800 0x200>; +- clocks = <&clks VF610_CLK_USBC0>; +- status = "disabled"; +- }; +- +- src: src@4006e000 { +- compatible = "fsl,vf610-src", "syscon"; +- reg = <0x4006e000 0x1000>; +- interrupts = <96 IRQ_TYPE_LEVEL_HIGH>; +- }; +- }; +- +- aips1: bus@40080000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x40080000 0x0007f000>; +- ranges; +- +- edma1: dma-controller@40098000 { +- #dma-cells = <2>; +- compatible = "fsl,vf610-edma"; +- reg = <0x40098000 0x2000>, +- <0x400a1000 0x1000>, +- <0x400a2000 0x1000>; +- dma-channels = <32>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, +- <11 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "edma-tx", "edma-err"; +- clock-names = "dmamux0", "dmamux1"; +- clocks = <&clks VF610_CLK_DMAMUX2>, +- <&clks VF610_CLK_DMAMUX3>; +- status = "disabled"; +- }; +- +- ocotp: ocotp@400a5000 { +- compatible = "fsl,vf610-ocotp", "syscon"; +- reg = <0x400a5000 0x1000>; +- clocks = <&clks VF610_CLK_OCOTP>; +- }; +- +- snvs0: snvs@400a7000 { +- compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; +- reg = <0x400a7000 0x2000>; +- +- snvsrtc: snvs-rtc-lp { +- compatible = "fsl,sec-v4.0-mon-rtc-lp"; +- regmap = <&snvs0>; +- offset = <0x34>; +- interrupts = <100 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_SNVS>; +- clock-names = "snvs-rtc"; +- }; +- }; +- +- uart4: serial@400a9000 { +- compatible = "fsl,vf610-lpuart"; +- reg = <0x400a9000 0x1000>; +- interrupts = <65 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_UART4>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- uart5: serial@400aa000 { +- compatible = "fsl,vf610-lpuart"; +- reg = <0x400aa000 0x1000>; +- interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_UART5>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- dspi2: spi@400ac000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,vf610-dspi"; +- reg = <0x400ac000 0x1000>; +- interrupts = <69 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_DSPI2>; +- clock-names = "dspi"; +- spi-num-chipselects = <2>; +- dmas = <&edma1 0 10>, +- <&edma1 0 11>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- dspi3: spi@400ad000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,vf610-dspi"; +- reg = <0x400ad000 0x1000>; +- interrupts = <70 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_DSPI3>; +- clock-names = "dspi"; +- spi-num-chipselects = <2>; +- dmas = <&edma1 0 12>, +- <&edma1 0 13>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- adc1: adc@400bb000 { +- compatible = "fsl,vf610-adc"; +- reg = <0x400bb000 0x1000>; +- interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_ADC1>; +- clock-names = "adc"; +- #io-channel-cells = <1>; +- status = "disabled"; +- fsl,adck-max-frequency = <30000000>, <40000000>, +- <20000000>; +- }; +- +- esdhc0: esdhc@400b1000 { +- compatible = "fsl,imx53-esdhc"; +- reg = <0x400b1000 0x1000>; +- interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_IPG_BUS>, +- <&clks VF610_CLK_PLATFORM_BUS>, +- <&clks VF610_CLK_ESDHC0>; +- clock-names = "ipg", "ahb", "per"; +- status = "disabled"; +- }; +- +- esdhc1: esdhc@400b2000 { +- compatible = "fsl,imx53-esdhc"; +- reg = <0x400b2000 0x1000>; +- interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_IPG_BUS>, +- <&clks VF610_CLK_PLATFORM_BUS>, +- <&clks VF610_CLK_ESDHC1>; +- clock-names = "ipg", "ahb", "per"; +- status = "disabled"; +- }; +- +- usbh1: usb@400b4000 { +- compatible = "fsl,vf610-usb", "fsl,imx27-usb"; +- reg = <0x400b4000 0x800>; +- interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_USBC1>; +- fsl,usbphy = <&usbphy1>; +- fsl,usbmisc = <&usbmisc1 0>; +- dr_mode = "host"; +- status = "disabled"; +- }; +- +- usbmisc1: usb@400b4800 { +- #index-cells = <1>; +- compatible = "fsl,vf610-usbmisc"; +- reg = <0x400b4800 0x200>; +- clocks = <&clks VF610_CLK_USBC1>; +- status = "disabled"; +- }; +- +- ftm: ftm@400b8000 { +- compatible = "fsl,ftm-timer"; +- reg = <0x400b8000 0x1000 0x400b9000 0x1000>; +- interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; +- clock-names = "ftm-evt", "ftm-src", +- "ftm-evt-counter-en", "ftm-src-counter-en"; +- clocks = <&clks VF610_CLK_FTM2>, +- <&clks VF610_CLK_FTM3>, +- <&clks VF610_CLK_FTM2_EXT_FIX_EN>, +- <&clks VF610_CLK_FTM3_EXT_FIX_EN>; +- status = "disabled"; +- }; +- +- qspi1: spi@400c4000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,vf610-qspi"; +- reg = <0x400c4000 0x1000>, <0x50000000 0x10000000>; +- reg-names = "QuadSPI", "QuadSPI-memory"; +- interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_QSPI1_EN>, +- <&clks VF610_CLK_QSPI1>; +- clock-names = "qspi_en", "qspi"; +- status = "disabled"; +- }; +- +- dac0: dac@400cc000 { +- compatible = "fsl,vf610-dac"; +- reg = <0x400cc000 1000>; +- interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; +- clock-names = "dac"; +- clocks = <&clks VF610_CLK_DAC0>; +- status = "disabled"; +- }; +- +- dac1: dac@400cd000 { +- compatible = "fsl,vf610-dac"; +- reg = <0x400cd000 1000>; +- interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; +- clock-names = "dac"; +- clocks = <&clks VF610_CLK_DAC1>; +- status = "disabled"; +- }; +- +- fec0: ethernet@400d0000 { +- compatible = "fsl,mvf600-fec"; +- reg = <0x400d0000 0x1000>; +- interrupts = <78 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_ENET0>, +- <&clks VF610_CLK_ENET0>, +- <&clks VF610_CLK_ENET>; +- clock-names = "ipg", "ahb", "ptp"; +- status = "disabled"; +- }; +- +- fec1: ethernet@400d1000 { +- compatible = "fsl,mvf600-fec"; +- reg = <0x400d1000 0x1000>; +- interrupts = <79 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_ENET1>, +- <&clks VF610_CLK_ENET1>, +- <&clks VF610_CLK_ENET>; +- clock-names = "ipg", "ahb", "ptp"; +- status = "disabled"; +- }; +- +- can1: can@400d4000 { +- compatible = "fsl,vf610-flexcan"; +- reg = <0x400d4000 0x4000>; +- interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_FLEXCAN1>, +- <&clks VF610_CLK_FLEXCAN1>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- nfc: nand@400e0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,vf610-nfc"; +- reg = <0x400e0000 0x4000>; +- interrupts = <83 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_NFC>; +- clock-names = "nfc"; +- status = "disabled"; +- }; +- +- i2c2: i2c@400e6000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,vf610-i2c"; +- reg = <0x400e6000 0x1000>; +- interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_I2C2>; +- clock-names = "ipg"; +- dmas = <&edma0 1 36>, +- <&edma0 1 37>; +- dma-names = "rx","tx"; +- status = "disabled"; +- }; +- +- i2c3: i2c@400e7000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,vf610-i2c"; +- reg = <0x400e7000 0x1000>; +- interrupts = <74 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clks VF610_CLK_I2C3>; +- clock-names = "ipg"; +- dmas = <&edma0 1 38>, +- <&edma0 1 39>; +- dma-names = "rx","tx"; +- status = "disabled"; +- }; +- +- crypto: crypto@400f0000 { +- compatible = "fsl,sec-v4.0"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x400f0000 0x9000>; +- ranges = <0 0x400f0000 0x9000>; +- clocks = <&clks VF610_CLK_CAAM>; +- clock-names = "ipg"; +- +- sec_jr0: jr0@1000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x1000 0x1000>; +- interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- sec_jr1: jr1@2000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x2000 0x1000>; +- interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vt8500-bv07.dts b/scripts/dtc/include-prefixes/arm/vt8500-bv07.dts +deleted file mode 100644 +index e9f55bd30bd4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vt8500-bv07.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * vt8500-bv07.dts - Device tree file for Benign BV07 Netbook +- * +- * Copyright (C) 2012 Tony Prisk +- */ +- +-/dts-v1/; +-/include/ "vt8500.dtsi" +- +-/ { +- model = "Benign BV07 Netbook"; +-}; +- +-&fb { +- bits-per-pixel = <16>; +- display-timings { +- native-mode = <&timing0>; +- timing0: 800x480 { +- clock-frequency = <0>; /* unused but required */ +- hactive = <800>; +- vactive = <480>; +- hfront-porch = <40>; +- hback-porch = <88>; +- hsync-len = <0>; +- vback-porch = <32>; +- vfront-porch = <11>; +- vsync-len = <1>; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/vt8500.dtsi b/scripts/dtc/include-prefixes/arm/vt8500.dtsi +deleted file mode 100644 +index b7e09eff5bb2..000000000000 +--- a/scripts/dtc/include-prefixes/arm/vt8500.dtsi ++++ /dev/null +@@ -1,179 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * vt8500.dtsi - Device tree file for VIA VT8500 SoC +- * +- * Copyright (C) 2012 Tony Prisk +- */ +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "via,vt8500"; +- +- cpus { +- #address-cells = <0>; +- #size-cells = <0>; +- +- cpu { +- device_type = "cpu"; +- compatible = "arm,arm926ej-s"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; +- }; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges; +- interrupt-parent = <&intc>; +- +- intc: interrupt-controller@d8140000 { +- compatible = "via,vt8500-intc"; +- interrupt-controller; +- reg = <0xd8140000 0x10000>; +- #interrupt-cells = <1>; +- }; +- +- pinctrl: pinctrl@d8110000 { +- compatible = "via,vt8500-pinctrl"; +- reg = <0xd8110000 0x10000>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- pmc@d8130000 { +- compatible = "via,vt8500-pmc"; +- reg = <0xd8130000 0x1000>; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ref24: ref24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- clkuart0: uart0 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x250>; +- enable-bit = <1>; +- }; +- +- clkuart1: uart1 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x250>; +- enable-bit = <2>; +- }; +- +- clkuart2: uart2 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x250>; +- enable-bit = <3>; +- }; +- +- clkuart3: uart3 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x250>; +- enable-bit = <4>; +- }; +- }; +- }; +- +- timer@d8130100 { +- compatible = "via,vt8500-timer"; +- reg = <0xd8130100 0x28>; +- interrupts = <36>; +- }; +- +- ehci@d8007900 { +- compatible = "via,vt8500-ehci"; +- reg = <0xd8007900 0x200>; +- interrupts = <43>; +- }; +- +- uhci@d8007b00 { +- compatible = "platform-uhci"; +- reg = <0xd8007b00 0x200>; +- interrupts = <43>; +- }; +- +- fb: fb@d8050800 { +- compatible = "via,vt8500-fb"; +- reg = <0xd800e400 0x400>; +- interrupts = <12>; +- }; +- +- ge_rops@d8050400 { +- compatible = "wm,prizm-ge-rops"; +- reg = <0xd8050400 0x100>; +- }; +- +- uart0: serial@d8200000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd8200000 0x1040>; +- interrupts = <32>; +- clocks = <&clkuart0>; +- status = "disabled"; +- }; +- +- uart1: serial@d82b0000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd82b0000 0x1040>; +- interrupts = <33>; +- clocks = <&clkuart1>; +- status = "disabled"; +- }; +- +- uart2: serial@d8210000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd8210000 0x1040>; +- interrupts = <47>; +- clocks = <&clkuart2>; +- status = "disabled"; +- }; +- +- uart3: serial@d82c0000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd82c0000 0x1040>; +- interrupts = <50>; +- clocks = <&clkuart3>; +- status = "disabled"; +- }; +- +- rtc@d8100000 { +- compatible = "via,vt8500-rtc"; +- reg = <0xd8100000 0x10000>; +- interrupts = <48>; +- }; +- +- ethernet@d8004000 { +- compatible = "via,vt8500-rhine"; +- reg = <0xd8004000 0x100>; +- interrupts = <10>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/wm8505-ref.dts b/scripts/dtc/include-prefixes/arm/wm8505-ref.dts +deleted file mode 100644 +index 2d77c087676e..000000000000 +--- a/scripts/dtc/include-prefixes/arm/wm8505-ref.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * wm8505-ref.dts - Device tree file for Wondermedia WM8505 reference netbook +- * +- * Copyright (C) 2012 Tony Prisk +- */ +- +-/dts-v1/; +-/include/ "wm8505.dtsi" +- +-/ { +- model = "Wondermedia WM8505 Netbook"; +-}; +- +-&fb { +- bits-per-pixel = <32>; +- display-timings { +- native-mode = <&timing0>; +- timing0: 800x480 { +- clock-frequency = <0>; /* unused but required */ +- hactive = <800>; +- vactive = <480>; +- hfront-porch = <40>; +- hback-porch = <88>; +- hsync-len = <0>; +- vback-porch = <32>; +- vfront-porch = <11>; +- vsync-len = <1>; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/wm8505.dtsi b/scripts/dtc/include-prefixes/arm/wm8505.dtsi +deleted file mode 100644 +index 168cd12b07bc..000000000000 +--- a/scripts/dtc/include-prefixes/arm/wm8505.dtsi ++++ /dev/null +@@ -1,294 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC +- * +- * Copyright (C) 2012 Tony Prisk +- */ +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "wm,wm8505"; +- +- cpus { +- #address-cells = <0>; +- #size-cells = <0>; +- +- cpu { +- device_type = "cpu"; +- compatible = "arm,arm926ej-s"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; +- }; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- serial5 = &uart5; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges; +- interrupt-parent = <&intc0>; +- +- intc0: interrupt-controller@d8140000 { +- compatible = "via,vt8500-intc"; +- interrupt-controller; +- reg = <0xd8140000 0x10000>; +- #interrupt-cells = <1>; +- }; +- +- /* Secondary IC cascaded to intc0 */ +- intc1: interrupt-controller@d8150000 { +- compatible = "via,vt8500-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0xD8150000 0x10000>; +- interrupts = <56 57 58 59 60 61 62 63>; +- }; +- +- pinctrl: pinctrl@d8110000 { +- compatible = "wm,wm8505-pinctrl"; +- reg = <0xd8110000 0x10000>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- pmc@d8130000 { +- compatible = "via,vt8500-pmc"; +- reg = <0xd8130000 0x1000>; +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ref24: ref24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- ref25: ref25M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25000000>; +- }; +- +- plla: plla { +- #clock-cells = <0>; +- compatible = "via,vt8500-pll-clock"; +- clocks = <&ref25>; +- reg = <0x200>; +- }; +- +- pllb: pllb { +- #clock-cells = <0>; +- compatible = "via,vt8500-pll-clock"; +- clocks = <&ref25>; +- reg = <0x204>; +- }; +- +- pllc: pllc { +- #clock-cells = <0>; +- compatible = "via,vt8500-pll-clock"; +- clocks = <&ref25>; +- reg = <0x208>; +- }; +- +- plld: plld { +- #clock-cells = <0>; +- compatible = "via,vt8500-pll-clock"; +- clocks = <&ref25>; +- reg = <0x20c>; +- }; +- +- clkarm: arm { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&plla>; +- divisor-reg = <0x300>; +- }; +- +- clkahb: ahb { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&pllb>; +- divisor-reg = <0x304>; +- }; +- +- clkapb: apb { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&pllb>; +- divisor-reg = <0x350>; +- }; +- +- clkddr: ddr { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&plld>; +- divisor-reg = <0x310>; +- }; +- +- clkuart0: uart0 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x250>; +- enable-bit = <1>; +- }; +- +- clkuart1: uart1 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x250>; +- enable-bit = <2>; +- }; +- +- clkuart2: uart2 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x250>; +- enable-bit = <3>; +- }; +- +- clkuart3: uart3 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x250>; +- enable-bit = <4>; +- }; +- +- clkuart4: uart4 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x250>; +- enable-bit = <22>; +- }; +- +- clkuart5: uart5 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x250>; +- enable-bit = <23>; +- }; +- +- clksdhc: sdhc { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&pllb>; +- divisor-reg = <0x328>; +- divisor-mask = <0x3f>; +- enable-reg = <0x254>; +- enable-bit = <18>; +- }; +- }; +- }; +- +- timer@d8130100 { +- compatible = "via,vt8500-timer"; +- reg = <0xd8130100 0x28>; +- interrupts = <36>; +- }; +- +- ehci@d8007100 { +- compatible = "via,vt8500-ehci"; +- reg = <0xd8007100 0x200>; +- interrupts = <1>; +- }; +- +- uhci@d8007300 { +- compatible = "platform-uhci"; +- reg = <0xd8007300 0x200>; +- interrupts = <0>; +- }; +- +- fb: fb@d8050800 { +- compatible = "wm,wm8505-fb"; +- reg = <0xd8050800 0x200>; +- }; +- +- ge_rops@d8050400 { +- compatible = "wm,prizm-ge-rops"; +- reg = <0xd8050400 0x100>; +- }; +- +- uart0: serial@d8200000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd8200000 0x1040>; +- interrupts = <32>; +- clocks = <&clkuart0>; +- status = "disabled"; +- }; +- +- uart1: serial@d82b0000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd82b0000 0x1040>; +- interrupts = <33>; +- clocks = <&clkuart1>; +- status = "disabled"; +- }; +- +- uart2: serial@d8210000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd8210000 0x1040>; +- interrupts = <47>; +- clocks = <&clkuart2>; +- status = "disabled"; +- }; +- +- uart3: serial@d82c0000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd82c0000 0x1040>; +- interrupts = <50>; +- clocks = <&clkuart3>; +- status = "disabled"; +- }; +- +- uart4: serial@d8370000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd8370000 0x1040>; +- interrupts = <31>; +- clocks = <&clkuart4>; +- status = "disabled"; +- }; +- +- uart5: serial@d8380000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd8380000 0x1040>; +- interrupts = <30>; +- clocks = <&clkuart5>; +- status = "disabled"; +- }; +- +- rtc@d8100000 { +- compatible = "via,vt8500-rtc"; +- reg = <0xd8100000 0x10000>; +- interrupts = <48>; +- }; +- +- sdhc@d800a000 { +- compatible = "wm,wm8505-sdhc"; +- reg = <0xd800a000 0x400>; +- interrupts = <20>, <21>; +- clocks = <&clksdhc>; +- bus-width = <4>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/wm8650-mid.dts b/scripts/dtc/include-prefixes/arm/wm8650-mid.dts +deleted file mode 100644 +index f6a42149a0a0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/wm8650-mid.dts ++++ /dev/null +@@ -1,36 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * wm8650-mid.dts - Device tree file for Wondermedia WM8650-MID Tablet +- * +- * Copyright (C) 2012 Tony Prisk +- */ +- +-/dts-v1/; +-/include/ "wm8650.dtsi" +- +-/ { +- model = "Wondermedia WM8650-MID Tablet"; +-}; +- +-&fb { +- bits-per-pixel = <16>; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: 800x480 { +- clock-frequency = <0>; /* unused but required */ +- hactive = <800>; +- vactive = <480>; +- hfront-porch = <40>; +- hback-porch = <88>; +- hsync-len = <0>; +- vback-porch = <32>; +- vfront-porch = <11>; +- vsync-len = <1>; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/wm8650.dtsi b/scripts/dtc/include-prefixes/arm/wm8650.dtsi +deleted file mode 100644 +index bc057b6f7d16..000000000000 +--- a/scripts/dtc/include-prefixes/arm/wm8650.dtsi ++++ /dev/null +@@ -1,241 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC +- * +- * Copyright (C) 2012 Tony Prisk +- */ +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "wm,wm8650"; +- +- cpus { +- #address-cells = <0>; +- #size-cells = <0>; +- +- cpu { +- device_type = "cpu"; +- compatible = "arm,arm926ej-s"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; +- }; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges; +- interrupt-parent = <&intc0>; +- +- intc0: interrupt-controller@d8140000 { +- compatible = "via,vt8500-intc"; +- interrupt-controller; +- reg = <0xd8140000 0x10000>; +- #interrupt-cells = <1>; +- }; +- +- /* Secondary IC cascaded to intc0 */ +- intc1: interrupt-controller@d8150000 { +- compatible = "via,vt8500-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0xD8150000 0x10000>; +- interrupts = <56 57 58 59 60 61 62 63>; +- }; +- +- pinctrl: pinctrl@d8110000 { +- compatible = "wm,wm8650-pinctrl"; +- reg = <0xd8110000 0x10000>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- pmc@d8130000 { +- compatible = "via,vt8500-pmc"; +- reg = <0xd8130000 0x1000>; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ref25: ref25M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25000000>; +- }; +- +- ref24: ref24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- plla: plla { +- #clock-cells = <0>; +- compatible = "wm,wm8650-pll-clock"; +- clocks = <&ref25>; +- reg = <0x200>; +- }; +- +- pllb: pllb { +- #clock-cells = <0>; +- compatible = "wm,wm8650-pll-clock"; +- clocks = <&ref25>; +- reg = <0x204>; +- }; +- +- pllc: pllc { +- #clock-cells = <0>; +- compatible = "wm,wm8650-pll-clock"; +- clocks = <&ref25>; +- reg = <0x208>; +- }; +- +- plld: plld { +- #clock-cells = <0>; +- compatible = "wm,wm8650-pll-clock"; +- clocks = <&ref25>; +- reg = <0x20c>; +- }; +- +- plle: plle { +- #clock-cells = <0>; +- compatible = "wm,wm8650-pll-clock"; +- clocks = <&ref25>; +- reg = <0x210>; +- }; +- +- clkarm: arm { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&plla>; +- divisor-reg = <0x300>; +- }; +- +- clkahb: ahb { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&pllb>; +- divisor-reg = <0x304>; +- }; +- +- clkapb: apb { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&pllb>; +- divisor-reg = <0x320>; +- }; +- +- clkddr: ddr { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&plld>; +- divisor-reg = <0x310>; +- }; +- +- clkuart0: uart0 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x250>; +- enable-bit = <1>; +- }; +- +- clkuart1: uart1 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x250>; +- enable-bit = <2>; +- }; +- +- clksdhc: sdhc { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&pllb>; +- divisor-reg = <0x328>; +- divisor-mask = <0x3f>; +- enable-reg = <0x254>; +- enable-bit = <18>; +- }; +- }; +- }; +- +- timer@d8130100 { +- compatible = "via,vt8500-timer"; +- reg = <0xd8130100 0x28>; +- interrupts = <36>; +- }; +- +- ehci@d8007900 { +- compatible = "via,vt8500-ehci"; +- reg = <0xd8007900 0x200>; +- interrupts = <43>; +- }; +- +- uhci@d8007b00 { +- compatible = "platform-uhci"; +- reg = <0xd8007b00 0x200>; +- interrupts = <43>; +- }; +- +- sdhc@d800a000 { +- compatible = "wm,wm8505-sdhc"; +- reg = <0xd800a000 0x400>; +- interrupts = <20>, <21>; +- clocks = <&clksdhc>; +- bus-width = <4>; +- sdon-inverted; +- }; +- +- fb: fb@d8050800 { +- compatible = "wm,wm8505-fb"; +- reg = <0xd8050800 0x200>; +- }; +- +- ge_rops@d8050400 { +- compatible = "wm,prizm-ge-rops"; +- reg = <0xd8050400 0x100>; +- }; +- +- uart0: serial@d8200000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd8200000 0x1040>; +- interrupts = <32>; +- clocks = <&clkuart0>; +- status = "disabled"; +- }; +- +- uart1: serial@d82b0000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd82b0000 0x1040>; +- interrupts = <33>; +- clocks = <&clkuart1>; +- status = "disabled"; +- }; +- +- rtc@d8100000 { +- compatible = "via,vt8500-rtc"; +- reg = <0xd8100000 0x10000>; +- interrupts = <48>; +- }; +- +- ethernet@d8004000 { +- compatible = "via,vt8500-rhine"; +- reg = <0xd8004000 0x100>; +- interrupts = <10>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/wm8750-apc8750.dts b/scripts/dtc/include-prefixes/arm/wm8750-apc8750.dts +deleted file mode 100644 +index 136e812bc1e4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/wm8750-apc8750.dts ++++ /dev/null +@@ -1,29 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * wm8750-apc8750.dts +- * - Device tree file for VIA APC8750 +- * +- * Copyright (C) 2012 Tony Prisk +- */ +- +-/dts-v1/; +-/include/ "wm8750.dtsi" +- +-/ { +- model = "VIA APC8750"; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c>; +- +- i2c: i2c { +- wm,pins = <168 169 170 171>; +- wm,function = <2>; /* alt */ +- wm,pull = <2>; /* pull-up */ +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/wm8750.dtsi b/scripts/dtc/include-prefixes/arm/wm8750.dtsi +deleted file mode 100644 +index 33aeb37491f4..000000000000 +--- a/scripts/dtc/include-prefixes/arm/wm8750.dtsi ++++ /dev/null +@@ -1,351 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC +- * +- * Copyright (C) 2012 Tony Prisk +- */ +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "wm,wm8750"; +- +- cpus { +- #address-cells = <0>; +- #size-cells = <0>; +- +- cpu { +- device_type = "cpu"; +- compatible = "arm,arm1176jzf"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; +- }; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- serial5 = &uart5; +- i2c0 = &i2c_0; +- i2c1 = &i2c_1; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges; +- interrupt-parent = <&intc0>; +- +- intc0: interrupt-controller@d8140000 { +- compatible = "via,vt8500-intc"; +- interrupt-controller; +- reg = <0xd8140000 0x10000>; +- #interrupt-cells = <1>; +- }; +- +- /* Secondary IC cascaded to intc0 */ +- intc1: interrupt-controller@d8150000 { +- compatible = "via,vt8500-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0xD8150000 0x10000>; +- interrupts = <56 57 58 59 60 61 62 63>; +- }; +- +- pinctrl: pinctrl@d8110000 { +- compatible = "wm,wm8750-pinctrl"; +- reg = <0xd8110000 0x10000>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- pmc@d8130000 { +- compatible = "via,vt8500-pmc"; +- reg = <0xd8130000 0x1000>; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ref24: ref24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- ref25: ref25M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25000000>; +- }; +- +- plla: plla { +- #clock-cells = <0>; +- compatible = "wm,wm8750-pll-clock"; +- clocks = <&ref25>; +- reg = <0x200>; +- }; +- +- pllb: pllb { +- #clock-cells = <0>; +- compatible = "wm,wm8750-pll-clock"; +- clocks = <&ref25>; +- reg = <0x204>; +- }; +- +- pllc: pllc { +- #clock-cells = <0>; +- compatible = "wm,wm8750-pll-clock"; +- clocks = <&ref25>; +- reg = <0x208>; +- }; +- +- plld: plld { +- #clock-cells = <0>; +- compatible = "wm,wm8750-pll-clock"; +- clocks = <&ref25>; +- reg = <0x20C>; +- }; +- +- plle: plle { +- #clock-cells = <0>; +- compatible = "wm,wm8750-pll-clock"; +- clocks = <&ref25>; +- reg = <0x210>; +- }; +- +- clkarm: arm { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&plla>; +- divisor-reg = <0x300>; +- }; +- +- clkahb: ahb { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&pllb>; +- divisor-reg = <0x304>; +- }; +- +- clkapb: apb { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&pllb>; +- divisor-reg = <0x320>; +- }; +- +- clkddr: ddr { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&plld>; +- divisor-reg = <0x310>; +- }; +- +- clkuart0: uart0 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x254>; +- enable-bit = <24>; +- }; +- +- clkuart1: uart1 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x254>; +- enable-bit = <25>; +- }; +- +- clkuart2: uart2 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x254>; +- enable-bit = <26>; +- }; +- +- clkuart3: uart3 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x254>; +- enable-bit = <27>; +- }; +- +- clkuart4: uart4 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x254>; +- enable-bit = <28>; +- }; +- +- clkuart5: uart5 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x254>; +- enable-bit = <29>; +- }; +- +- clkpwm: pwm { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&pllb>; +- divisor-reg = <0x350>; +- enable-reg = <0x250>; +- enable-bit = <17>; +- }; +- +- clksdhc: sdhc { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&pllb>; +- divisor-reg = <0x330>; +- divisor-mask = <0x3f>; +- enable-reg = <0x250>; +- enable-bit = <0>; +- }; +- +- clki2c0: i2c0clk { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&pllb>; +- divisor-reg = <0x3A0>; +- enable-reg = <0x250>; +- enable-bit = <8>; +- }; +- +- clki2c1: i2c1clk { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&pllb>; +- divisor-reg = <0x3A4>; +- enable-reg = <0x250>; +- enable-bit = <9>; +- }; +- }; +- }; +- +- pwm: pwm@d8220000 { +- #pwm-cells = <3>; +- compatible = "via,vt8500-pwm"; +- reg = <0xd8220000 0x100>; +- clocks = <&clkpwm>; +- }; +- +- timer@d8130100 { +- compatible = "via,vt8500-timer"; +- reg = <0xd8130100 0x28>; +- interrupts = <36>; +- }; +- +- ehci@d8007900 { +- compatible = "via,vt8500-ehci"; +- reg = <0xd8007900 0x200>; +- interrupts = <26>; +- }; +- +- uhci@d8007b00 { +- compatible = "platform-uhci"; +- reg = <0xd8007b00 0x200>; +- interrupts = <26>; +- }; +- +- uhci@d8008d00 { +- compatible = "platform-uhci"; +- reg = <0xd8008d00 0x200>; +- interrupts = <26>; +- }; +- +- uart0: serial@d8200000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd8200000 0x1040>; +- interrupts = <32>; +- clocks = <&clkuart0>; +- status = "disabled"; +- }; +- +- uart1: serial@d82b0000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd82b0000 0x1040>; +- interrupts = <33>; +- clocks = <&clkuart1>; +- status = "disabled"; +- }; +- +- uart2: serial@d8210000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd8210000 0x1040>; +- interrupts = <47>; +- clocks = <&clkuart2>; +- status = "disabled"; +- }; +- +- uart3: serial@d82c0000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd82c0000 0x1040>; +- interrupts = <50>; +- clocks = <&clkuart3>; +- status = "disabled"; +- }; +- +- uart4: serial@d8370000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd8370000 0x1040>; +- interrupts = <30>; +- clocks = <&clkuart4>; +- status = "disabled"; +- }; +- +- uart5: serial@d8380000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd8380000 0x1040>; +- interrupts = <43>; +- clocks = <&clkuart5>; +- status = "disabled"; +- }; +- +- rtc@d8100000 { +- compatible = "via,vt8500-rtc"; +- reg = <0xd8100000 0x10000>; +- interrupts = <48>; +- }; +- +- sdhc@d800a000 { +- compatible = "wm,wm8505-sdhc"; +- reg = <0xd800a000 0x1000>; +- interrupts = <20 21>; +- clocks = <&clksdhc>; +- bus-width = <4>; +- sdon-inverted; +- }; +- +- i2c_0: i2c@d8280000 { +- compatible = "wm,wm8505-i2c"; +- reg = <0xd8280000 0x1000>; +- interrupts = <19>; +- clocks = <&clki2c0>; +- clock-frequency = <400000>; +- }; +- +- i2c_1: i2c@d8320000 { +- compatible = "wm,wm8505-i2c"; +- reg = <0xd8320000 0x1000>; +- interrupts = <18>; +- clocks = <&clki2c1>; +- clock-frequency = <400000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/wm8850-w70v2.dts b/scripts/dtc/include-prefixes/arm/wm8850-w70v2.dts +deleted file mode 100644 +index c7a6fe0ce48f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/wm8850-w70v2.dts ++++ /dev/null +@@ -1,47 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * wm8850-w70v2.dts +- * - Device tree file for Wondermedia WM8850 Tablet +- * - 'W70-V2' mainboard +- * - HongLianYing 'HLY070ML268-21A' 7" LCD panel +- * +- * Copyright (C) 2012 Tony Prisk +- */ +- +-/dts-v1/; +-/include/ "wm8850.dtsi" +-#include +- +-/ { +- model = "Wondermedia WM8850-W70v2 Tablet"; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; +- +- brightness-levels = <0 40 60 80 100 130 190 255>; +- default-brightness-level = <5>; +- }; +-}; +- +-&fb { +- bits-per-pixel = <16>; +- display-timings { +- native-mode = <&timing0>; +- timing0: 800x480 { +- clock-frequency = <0>; /* unused but required */ +- hactive = <800>; +- vactive = <480>; +- hfront-porch = <40>; +- hback-porch = <88>; +- hsync-len = <0>; +- vback-porch = <32>; +- vfront-porch = <11>; +- vsync-len = <1>; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/wm8850.dtsi b/scripts/dtc/include-prefixes/arm/wm8850.dtsi +deleted file mode 100644 +index 65c9271050e6..000000000000 +--- a/scripts/dtc/include-prefixes/arm/wm8850.dtsi ++++ /dev/null +@@ -1,312 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC +- * +- * Copyright (C) 2012 Tony Prisk +- */ +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "wm,wm8850"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0x0>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; +- }; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges; +- interrupt-parent = <&intc0>; +- +- intc0: interrupt-controller@d8140000 { +- compatible = "via,vt8500-intc"; +- interrupt-controller; +- reg = <0xd8140000 0x10000>; +- #interrupt-cells = <1>; +- }; +- +- /* Secondary IC cascaded to intc0 */ +- intc1: interrupt-controller@d8150000 { +- compatible = "via,vt8500-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reg = <0xD8150000 0x10000>; +- interrupts = <56 57 58 59 60 61 62 63>; +- }; +- +- pinctrl: pinctrl@d8110000 { +- compatible = "wm,wm8850-pinctrl"; +- reg = <0xd8110000 0x10000>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- pmc@d8130000 { +- compatible = "via,vt8500-pmc"; +- reg = <0xd8130000 0x1000>; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ref25: ref25M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25000000>; +- }; +- +- ref24: ref24M { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- plla: plla { +- #clock-cells = <0>; +- compatible = "wm,wm8850-pll-clock"; +- clocks = <&ref24>; +- reg = <0x200>; +- }; +- +- pllb: pllb { +- #clock-cells = <0>; +- compatible = "wm,wm8850-pll-clock"; +- clocks = <&ref24>; +- reg = <0x204>; +- }; +- +- pllc: pllc { +- #clock-cells = <0>; +- compatible = "wm,wm8850-pll-clock"; +- clocks = <&ref24>; +- reg = <0x208>; +- }; +- +- plld: plld { +- #clock-cells = <0>; +- compatible = "wm,wm8850-pll-clock"; +- clocks = <&ref24>; +- reg = <0x20c>; +- }; +- +- plle: plle { +- #clock-cells = <0>; +- compatible = "wm,wm8850-pll-clock"; +- clocks = <&ref24>; +- reg = <0x210>; +- }; +- +- pllf: pllf { +- #clock-cells = <0>; +- compatible = "wm,wm8850-pll-clock"; +- clocks = <&ref24>; +- reg = <0x214>; +- }; +- +- pllg: pllg { +- #clock-cells = <0>; +- compatible = "wm,wm8850-pll-clock"; +- clocks = <&ref24>; +- reg = <0x218>; +- }; +- +- clkarm: arm { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&plla>; +- divisor-reg = <0x300>; +- }; +- +- clkahb: ahb { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&pllb>; +- divisor-reg = <0x304>; +- }; +- +- clkapb: apb { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&pllb>; +- divisor-reg = <0x320>; +- }; +- +- clkddr: ddr { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&plld>; +- divisor-reg = <0x310>; +- }; +- +- clkuart0: uart0 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x254>; +- enable-bit = <24>; +- }; +- +- clkuart1: uart1 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x254>; +- enable-bit = <25>; +- }; +- +- clkuart2: uart2 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x254>; +- enable-bit = <26>; +- }; +- +- clkuart3: uart3 { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&ref24>; +- enable-reg = <0x254>; +- enable-bit = <27>; +- }; +- +- clkpwm: pwm { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&pllb>; +- divisor-reg = <0x350>; +- enable-reg = <0x250>; +- enable-bit = <17>; +- }; +- +- clksdhc: sdhc { +- #clock-cells = <0>; +- compatible = "via,vt8500-device-clock"; +- clocks = <&pllb>; +- divisor-reg = <0x330>; +- divisor-mask = <0x3f>; +- enable-reg = <0x250>; +- enable-bit = <0>; +- }; +- }; +- }; +- +- fb: fb@d8051700 { +- compatible = "wm,wm8505-fb"; +- reg = <0xd8051700 0x200>; +- }; +- +- ge_rops@d8050400 { +- compatible = "wm,prizm-ge-rops"; +- reg = <0xd8050400 0x100>; +- }; +- +- pwm: pwm@d8220000 { +- #pwm-cells = <3>; +- compatible = "via,vt8500-pwm"; +- reg = <0xd8220000 0x100>; +- clocks = <&clkpwm>; +- }; +- +- timer@d8130100 { +- compatible = "via,vt8500-timer"; +- reg = <0xd8130100 0x28>; +- interrupts = <36>; +- }; +- +- ehci@d8007900 { +- compatible = "via,vt8500-ehci"; +- reg = <0xd8007900 0x200>; +- interrupts = <26>; +- }; +- +- uhci@d8007b00 { +- compatible = "platform-uhci"; +- reg = <0xd8007b00 0x200>; +- interrupts = <26>; +- }; +- +- uhci@d8008d00 { +- compatible = "platform-uhci"; +- reg = <0xd8008d00 0x200>; +- interrupts = <26>; +- }; +- +- uart0: serial@d8200000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd8200000 0x1040>; +- interrupts = <32>; +- clocks = <&clkuart0>; +- status = "disabled"; +- }; +- +- uart1: serial@d82b0000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd82b0000 0x1040>; +- interrupts = <33>; +- clocks = <&clkuart1>; +- status = "disabled"; +- }; +- +- uart2: serial@d8210000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd8210000 0x1040>; +- interrupts = <47>; +- clocks = <&clkuart2>; +- status = "disabled"; +- }; +- +- uart3: serial@d82c0000 { +- compatible = "via,vt8500-uart"; +- reg = <0xd82c0000 0x1040>; +- interrupts = <50>; +- clocks = <&clkuart3>; +- status = "disabled"; +- }; +- +- rtc@d8100000 { +- compatible = "via,vt8500-rtc"; +- reg = <0xd8100000 0x10000>; +- interrupts = <48>; +- }; +- +- sdhc@d800a000 { +- compatible = "wm,wm8505-sdhc"; +- reg = <0xd800a000 0x1000>; +- interrupts = <20 21>; +- clocks = <&clksdhc>; +- bus-width = <4>; +- sdon-inverted; +- }; +- +- ethernet@d8004000 { +- compatible = "via,vt8500-rhine"; +- reg = <0xd8004000 0x100>; +- interrupts = <10>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/xenvm-4.2.dts b/scripts/dtc/include-prefixes/arm/xenvm-4.2.dts +deleted file mode 100644 +index 384cd92f1f84..000000000000 +--- a/scripts/dtc/include-prefixes/arm/xenvm-4.2.dts ++++ /dev/null +@@ -1,82 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Xen Virtual Machine for unprivileged guests +- * +- * Based on ARM Ltd. Versatile Express CoreTile Express (single CPU) +- * Cortex-A15 MPCore (V2P-CA15) +- * +- */ +- +-/dts-v1/; +- +-/ { +- model = "XENVM-4.2"; +- compatible = "xen,xenvm-4.2", "xen,xenvm"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- chosen { +- /* this field is going to be adjusted by the hypervisor */ +- bootargs = "console=hvc0 root=/dev/xvda"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <0>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a15"; +- reg = <1>; +- }; +- }; +- +- psci { +- compatible = "arm,psci"; +- method = "hvc"; +- cpu_off = <1>; +- cpu_on = <2>; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- /* this field is going to be adjusted by the hypervisor */ +- reg = <0 0x80000000 0 0x08000000>; +- }; +- +- gic: interrupt-controller@2c001000 { +- compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0 0x2c001000 0 0x1000>, +- <0 0x2c002000 0 0x100>; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = <1 13 0xf08>, +- <1 14 0xf08>, +- <1 11 0xf08>, +- <1 10 0xf08>; +- }; +- +- hypervisor { +- compatible = "xen,xen-4.2", "xen,xen"; +- /* this field is going to be adjusted by the hypervisor */ +- reg = <0 0xb0000000 0 0x20000>; +- /* this field is going to be adjusted by the hypervisor */ +- interrupts = <1 15 0xf08>; +- }; +- +- motherboard { +- arm,v2m-memory-map = "rs1"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/zynq-7000.dtsi b/scripts/dtc/include-prefixes/arm/zynq-7000.dtsi +deleted file mode 100644 +index 47c2a4b14c06..000000000000 +--- a/scripts/dtc/include-prefixes/arm/zynq-7000.dtsi ++++ /dev/null +@@ -1,525 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2011 - 2014 Xilinx +- */ +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "xlnx,zynq-7000"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <0>; +- clocks = <&clkc 3>; +- clock-latency = <1000>; +- cpu0-supply = <®ulator_vccpint>; +- operating-points = < +- /* kHz uV */ +- 666667 1000000 +- 333334 1000000 +- >; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a9"; +- device_type = "cpu"; +- reg = <1>; +- clocks = <&clkc 3>; +- }; +- }; +- +- fpga_full: fpga-full { +- compatible = "fpga-region"; +- fpga-mgr = <&devcfg>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- }; +- +- pmu@f8891000 { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = <0 5 4>, <0 6 4>; +- interrupt-parent = <&intc>; +- reg = <0xf8891000 0x1000>, +- <0xf8893000 0x1000>; +- }; +- +- regulator_vccpint: fixedregulator { +- compatible = "regulator-fixed"; +- regulator-name = "VCCPINT"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- replicator { +- compatible = "arm,coresight-static-replicator"; +- clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; +- clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; +- +- out-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* replicator output ports */ +- port@0 { +- reg = <0>; +- replicator_out_port0: endpoint { +- remote-endpoint = <&tpiu_in_port>; +- }; +- }; +- port@1 { +- reg = <1>; +- replicator_out_port1: endpoint { +- remote-endpoint = <&etb_in_port>; +- }; +- }; +- }; +- in-ports { +- /* replicator input port */ +- port { +- replicator_in_port0: endpoint { +- remote-endpoint = <&funnel_out_port>; +- }; +- }; +- }; +- }; +- +- amba: axi { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&intc>; +- ranges; +- +- adc: adc@f8007100 { +- compatible = "xlnx,zynq-xadc-1.00.a"; +- reg = <0xf8007100 0x20>; +- interrupts = <0 7 4>; +- interrupt-parent = <&intc>; +- clocks = <&clkc 12>; +- }; +- +- can0: can@e0008000 { +- compatible = "xlnx,zynq-can-1.0"; +- status = "disabled"; +- clocks = <&clkc 19>, <&clkc 36>; +- clock-names = "can_clk", "pclk"; +- reg = <0xe0008000 0x1000>; +- interrupts = <0 28 4>; +- interrupt-parent = <&intc>; +- tx-fifo-depth = <0x40>; +- rx-fifo-depth = <0x40>; +- }; +- +- can1: can@e0009000 { +- compatible = "xlnx,zynq-can-1.0"; +- status = "disabled"; +- clocks = <&clkc 20>, <&clkc 37>; +- clock-names = "can_clk", "pclk"; +- reg = <0xe0009000 0x1000>; +- interrupts = <0 51 4>; +- interrupt-parent = <&intc>; +- tx-fifo-depth = <0x40>; +- rx-fifo-depth = <0x40>; +- }; +- +- gpio0: gpio@e000a000 { +- compatible = "xlnx,zynq-gpio-1.0"; +- #gpio-cells = <2>; +- clocks = <&clkc 42>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupt-parent = <&intc>; +- interrupts = <0 20 4>; +- reg = <0xe000a000 0x1000>; +- }; +- +- i2c0: i2c@e0004000 { +- compatible = "cdns,i2c-r1p10"; +- status = "disabled"; +- clocks = <&clkc 38>; +- interrupt-parent = <&intc>; +- interrupts = <0 25 4>; +- reg = <0xe0004000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c1: i2c@e0005000 { +- compatible = "cdns,i2c-r1p10"; +- status = "disabled"; +- clocks = <&clkc 39>; +- interrupt-parent = <&intc>; +- interrupts = <0 48 4>; +- reg = <0xe0005000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- intc: interrupt-controller@f8f01000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0xF8F01000 0x1000>, +- <0xF8F00100 0x100>; +- }; +- +- L2: cache-controller@f8f02000 { +- compatible = "arm,pl310-cache"; +- reg = <0xF8F02000 0x1000>; +- interrupts = <0 2 4>; +- arm,data-latency = <3 2 2>; +- arm,tag-latency = <2 2 2>; +- cache-unified; +- cache-level = <2>; +- }; +- +- mc: memory-controller@f8006000 { +- compatible = "xlnx,zynq-ddrc-a05"; +- reg = <0xf8006000 0x1000>; +- }; +- +- uart0: serial@e0000000 { +- compatible = "xlnx,xuartps", "cdns,uart-r1p8"; +- status = "disabled"; +- clocks = <&clkc 23>, <&clkc 40>; +- clock-names = "uart_clk", "pclk"; +- reg = <0xE0000000 0x1000>; +- interrupts = <0 27 4>; +- }; +- +- uart1: serial@e0001000 { +- compatible = "xlnx,xuartps", "cdns,uart-r1p8"; +- status = "disabled"; +- clocks = <&clkc 24>, <&clkc 41>; +- clock-names = "uart_clk", "pclk"; +- reg = <0xE0001000 0x1000>; +- interrupts = <0 50 4>; +- }; +- +- spi0: spi@e0006000 { +- compatible = "xlnx,zynq-spi-r1p6"; +- reg = <0xe0006000 0x1000>; +- status = "disabled"; +- interrupt-parent = <&intc>; +- interrupts = <0 26 4>; +- clocks = <&clkc 25>, <&clkc 34>; +- clock-names = "ref_clk", "pclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spi1: spi@e0007000 { +- compatible = "xlnx,zynq-spi-r1p6"; +- reg = <0xe0007000 0x1000>; +- status = "disabled"; +- interrupt-parent = <&intc>; +- interrupts = <0 49 4>; +- clocks = <&clkc 26>, <&clkc 35>; +- clock-names = "ref_clk", "pclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- gem0: ethernet@e000b000 { +- compatible = "cdns,zynq-gem", "cdns,gem"; +- reg = <0xe000b000 0x1000>; +- status = "disabled"; +- interrupts = <0 22 4>; +- clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; +- clock-names = "pclk", "hclk", "tx_clk"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- gem1: ethernet@e000c000 { +- compatible = "cdns,zynq-gem", "cdns,gem"; +- reg = <0xe000c000 0x1000>; +- status = "disabled"; +- interrupts = <0 45 4>; +- clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; +- clock-names = "pclk", "hclk", "tx_clk"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- smcc: memory-controller@e000e000 { +- compatible = "arm,pl353-smc-r2p1", "arm,primecell"; +- reg = <0xe000e000 0x0001000>; +- status = "disabled"; +- clock-names = "memclk", "apb_pclk"; +- clocks = <&clkc 11>, <&clkc 44>; +- ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ +- 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ +- 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ +- #address-cells = <2>; +- #size-cells = <1>; +- +- nfc0: nand-controller@0,0 { +- compatible = "arm,pl353-nand-r2p1"; +- reg = <0 0 0x1000000>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- sdhci0: mmc@e0100000 { +- compatible = "arasan,sdhci-8.9a"; +- status = "disabled"; +- clock-names = "clk_xin", "clk_ahb"; +- clocks = <&clkc 21>, <&clkc 32>; +- interrupt-parent = <&intc>; +- interrupts = <0 24 4>; +- reg = <0xe0100000 0x1000>; +- }; +- +- sdhci1: mmc@e0101000 { +- compatible = "arasan,sdhci-8.9a"; +- status = "disabled"; +- clock-names = "clk_xin", "clk_ahb"; +- clocks = <&clkc 22>, <&clkc 33>; +- interrupt-parent = <&intc>; +- interrupts = <0 47 4>; +- reg = <0xe0101000 0x1000>; +- }; +- +- slcr: slcr@f8000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; +- reg = <0xF8000000 0x1000>; +- ranges; +- clkc: clkc@100 { +- #clock-cells = <1>; +- compatible = "xlnx,ps7-clkc"; +- fclk-enable = <0>; +- clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", +- "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", +- "dci", "lqspi", "smc", "pcap", "gem0", "gem1", +- "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", +- "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", +- "dma", "usb0_aper", "usb1_aper", "gem0_aper", +- "gem1_aper", "sdio0_aper", "sdio1_aper", +- "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", +- "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", +- "gpio_aper", "lqspi_aper", "smc_aper", "swdt", +- "dbg_trc", "dbg_apb"; +- reg = <0x100 0x100>; +- }; +- +- rstc: rstc@200 { +- compatible = "xlnx,zynq-reset"; +- reg = <0x200 0x48>; +- #reset-cells = <1>; +- syscon = <&slcr>; +- }; +- +- pinctrl0: pinctrl@700 { +- compatible = "xlnx,pinctrl-zynq"; +- reg = <0x700 0x200>; +- syscon = <&slcr>; +- }; +- }; +- +- dmac_s: dmac@f8003000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0xf8003000 0x1000>; +- interrupt-parent = <&intc>; +- interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", +- "dma4", "dma5", "dma6", "dma7"; +- interrupts = <0 13 4>, +- <0 14 4>, <0 15 4>, +- <0 16 4>, <0 17 4>, +- <0 40 4>, <0 41 4>, +- <0 42 4>, <0 43 4>; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <4>; +- clocks = <&clkc 27>; +- clock-names = "apb_pclk"; +- }; +- +- devcfg: devcfg@f8007000 { +- compatible = "xlnx,zynq-devcfg-1.0"; +- reg = <0xf8007000 0x100>; +- interrupt-parent = <&intc>; +- interrupts = <0 8 4>; +- clocks = <&clkc 12>; +- clock-names = "ref_clk"; +- syscon = <&slcr>; +- }; +- +- global_timer: timer@f8f00200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0xf8f00200 0x20>; +- interrupts = <1 11 0x301>; +- interrupt-parent = <&intc>; +- clocks = <&clkc 4>; +- }; +- +- ttc0: timer@f8001000 { +- interrupt-parent = <&intc>; +- interrupts = <0 10 4>, <0 11 4>, <0 12 4>; +- compatible = "cdns,ttc"; +- clocks = <&clkc 6>; +- reg = <0xF8001000 0x1000>; +- }; +- +- ttc1: timer@f8002000 { +- interrupt-parent = <&intc>; +- interrupts = <0 37 4>, <0 38 4>, <0 39 4>; +- compatible = "cdns,ttc"; +- clocks = <&clkc 6>; +- reg = <0xF8002000 0x1000>; +- }; +- +- scutimer: timer@f8f00600 { +- interrupt-parent = <&intc>; +- interrupts = <1 13 0x301>; +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0xf8f00600 0x20>; +- clocks = <&clkc 4>; +- }; +- +- usb0: usb@e0002000 { +- compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; +- status = "disabled"; +- clocks = <&clkc 28>; +- interrupt-parent = <&intc>; +- interrupts = <0 21 4>; +- reg = <0xe0002000 0x1000>; +- phy_type = "ulpi"; +- }; +- +- usb1: usb@e0003000 { +- compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; +- status = "disabled"; +- clocks = <&clkc 29>; +- interrupt-parent = <&intc>; +- interrupts = <0 44 4>; +- reg = <0xe0003000 0x1000>; +- phy_type = "ulpi"; +- }; +- +- watchdog0: watchdog@f8005000 { +- clocks = <&clkc 45>; +- compatible = "cdns,wdt-r1p2"; +- interrupt-parent = <&intc>; +- interrupts = <0 9 1>; +- reg = <0xf8005000 0x1000>; +- timeout-sec = <10>; +- }; +- +- etb@f8801000 { +- compatible = "arm,coresight-etb10", "arm,primecell"; +- reg = <0xf8801000 0x1000>; +- clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; +- clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; +- in-ports { +- port { +- etb_in_port: endpoint { +- remote-endpoint = <&replicator_out_port1>; +- }; +- }; +- }; +- }; +- +- tpiu@f8803000 { +- compatible = "arm,coresight-tpiu", "arm,primecell"; +- reg = <0xf8803000 0x1000>; +- clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; +- clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; +- in-ports { +- port { +- tpiu_in_port: endpoint { +- remote-endpoint = <&replicator_out_port0>; +- }; +- }; +- }; +- }; +- +- funnel@f8804000 { +- compatible = "arm,coresight-static-funnel", "arm,primecell"; +- reg = <0xf8804000 0x1000>; +- clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; +- clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; +- +- /* funnel output ports */ +- out-ports { +- port { +- funnel_out_port: endpoint { +- remote-endpoint = +- <&replicator_in_port0>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* funnel input ports */ +- port@0 { +- reg = <0>; +- funnel0_in_port0: endpoint { +- remote-endpoint = <&ptm0_out_port>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- funnel0_in_port1: endpoint { +- remote-endpoint = <&ptm1_out_port>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- funnel0_in_port2: endpoint { +- }; +- }; +- /* The other input ports are not connect to anything */ +- }; +- }; +- +- ptm@f889c000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0xf889c000 0x1000>; +- clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; +- clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; +- cpu = <&cpu0>; +- out-ports { +- port { +- ptm0_out_port: endpoint { +- remote-endpoint = <&funnel0_in_port0>; +- }; +- }; +- }; +- }; +- +- ptm@f889d000 { +- compatible = "arm,coresight-etm3x", "arm,primecell"; +- reg = <0xf889d000 0x1000>; +- clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; +- clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; +- cpu = <&cpu1>; +- out-ports { +- port { +- ptm1_out_port: endpoint { +- remote-endpoint = <&funnel0_in_port1>; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/zynq-cc108.dts b/scripts/dtc/include-prefixes/arm/zynq-cc108.dts +deleted file mode 100644 +index 8b9ab9bba23b..000000000000 +--- a/scripts/dtc/include-prefixes/arm/zynq-cc108.dts ++++ /dev/null +@@ -1,75 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Xilinx CC108 board DTS +- * +- * (C) Copyright 2007-2018 Xilinx, Inc. +- * (C) Copyright 2007-2013 Michal Simek +- * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd +- * +- * Michal SIMEK +- */ +-/dts-v1/; +-/include/ "zynq-7000.dtsi" +- +-/ { +- model = "Xilinx CC108 board"; +- compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000"; +- +- aliases { +- ethernet0 = &gem0; +- serial0 = &uart0; +- }; +- +- chosen { +- bootargs = ""; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x20000000>; +- }; +- +- usb_phy0: phy0 { +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- }; +- +- usb_phy1: phy1 { +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- }; +-}; +- +-&gem0 { +- status = "okay"; +- phy-mode = "rgmii-id"; +- phy-handle = <ðernet_phy>; +- +- ethernet_phy: ethernet-phy@1 { +- reg = <1>; +- device_type = "ethernet-phy"; +- }; +-}; +- +-&sdhci1 { +- status = "okay"; +- broken-cd ; +- wp-inverted ; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +- usb-phy = <&usb_phy0>; +-}; +- +-&usb1 { +- status = "okay"; +- dr_mode = "host"; +- usb-phy = <&usb_phy1>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/zynq-ebaz4205.dts b/scripts/dtc/include-prefixes/arm/zynq-ebaz4205.dts +deleted file mode 100644 +index 53fa6dbfd8fd..000000000000 +--- a/scripts/dtc/include-prefixes/arm/zynq-ebaz4205.dts ++++ /dev/null +@@ -1,144 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2021 Michael Walle +- */ +-/dts-v1/; +-/include/ "zynq-7000.dtsi" +- +-/ { +- model = "Ebang EBAZ4205"; +- compatible = "ebang,ebaz4205", "xlnx,zynq-7000"; +- +- aliases { +- ethernet0 = &gem0; +- serial0 = &uart1; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x10000000>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&clkc { +- ps-clk-frequency = <33333333>; +- fclk-enable = <8>; +-}; +- +-&gem0 { +- status = "okay"; +- phy-mode = "mii"; +- phy-handle = <&phy>; +- +- /* PHY clock */ +- assigned-clocks = <&clkc 18>; +- assigned-clock-rates = <25000000>; +- +- phy: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&gpio0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio0_default>; +-}; +- +-&nfc0 { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- }; +-}; +- +-&pinctrl0 { +- pinctrl_gpio0_default: gpio0-default { +- mux { +- groups = "gpio0_20_grp", "gpio0_32_grp"; +- function = "gpio0"; +- }; +- +- conf { +- groups = "gpio0_20_grp", "gpio0_32_grp"; +- io-standard = <3>; +- slew-rate = <0>; +- }; +- +- conf-pull-up { +- pins = "MIO20", "MIO32"; +- bias-disable; +- }; +- }; +- +- pinctrl_sdhci0_default: sdhci0-default { +- mux { +- groups = "sdio0_2_grp"; +- function = "sdio0"; +- }; +- +- conf { +- groups = "sdio0_2_grp"; +- io-standard = <3>; +- slew-rate = <0>; +- bias-disable; +- }; +- +- mux-cd { +- groups = "gpio0_34_grp"; +- function = "sdio0_cd"; +- }; +- +- conf-cd { +- groups = "gpio0_34_grp"; +- io-standard = <3>; +- slew-rate = <0>; +- bias-high-impedance; +- bias-pull-up; +- }; +- }; +- +- pinctrl_uart1_default: uart1-default { +- mux { +- groups = "uart1_4_grp"; +- function = "uart1"; +- }; +- +- conf { +- groups = "uart1_4_grp"; +- io-standard = <3>; +- slew-rate = <0>; +- }; +- +- conf-rx { +- pins = "MIO25"; +- bias-high-impedance; +- }; +- +- conf-tx { +- pins = "MIO24"; +- bias-disable; +- }; +- }; +-}; +- +-&smcc { +- status = "okay"; +-}; +- +-&sdhci0 { +- status = "okay"; +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdhci0_default>; +-}; +- +-&uart1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1_default>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/zynq-microzed.dts b/scripts/dtc/include-prefixes/arm/zynq-microzed.dts +deleted file mode 100644 +index 6ed84fb15902..000000000000 +--- a/scripts/dtc/include-prefixes/arm/zynq-microzed.dts ++++ /dev/null +@@ -1,88 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2011 - 2014 Xilinx +- * Copyright (C) 2016 Jagan Teki +- */ +-/dts-v1/; +-/include/ "zynq-7000.dtsi" +- +-/ { +- model = "Avnet MicroZed board"; +- compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000"; +- +- aliases { +- ethernet0 = &gem0; +- serial0 = &uart1; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x40000000>; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "serial0:115200n8"; +- }; +- +- usb_phy0: phy0 { +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- }; +-}; +- +-&clkc { +- ps-clk-frequency = <33333333>; +-}; +- +-&gem0 { +- status = "okay"; +- phy-mode = "rgmii-id"; +- phy-handle = <ðernet_phy>; +- +- ethernet_phy: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&sdhci0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +- usb-phy = <&usb_phy0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb0_default>; +-}; +- +-&pinctrl0 { +- pinctrl_usb0_default: usb0-default { +- mux { +- groups = "usb0_0_grp"; +- function = "usb0"; +- }; +- +- conf { +- groups = "usb0_0_grp"; +- slew-rate = <0>; +- io-standard = <1>; +- }; +- +- conf-rx { +- pins = "MIO29", "MIO31", "MIO36"; +- bias-high-impedance; +- }; +- +- conf-tx { +- pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", +- "MIO35", "MIO37", "MIO38", "MIO39"; +- bias-disable; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/zynq-parallella.dts b/scripts/dtc/include-prefixes/arm/zynq-parallella.dts +deleted file mode 100644 +index 54592aeb92b9..000000000000 +--- a/scripts/dtc/include-prefixes/arm/zynq-parallella.dts ++++ /dev/null +@@ -1,88 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2014 SUSE LINUX Products GmbH +- * +- * Derived from zynq-zed.dts: +- * +- * Copyright (C) 2011 Xilinx +- * Copyright (C) 2012 National Instruments Corp. +- * Copyright (C) 2013 Xilinx +- */ +-/dts-v1/; +-/include/ "zynq-7000.dtsi" +- +-/ { +- model = "Adapteva Parallella board"; +- compatible = "adapteva,parallella", "xlnx,zynq-7000"; +- +- aliases { +- ethernet0 = &gem0; +- serial0 = &uart1; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x40000000>; +- }; +- +- chosen { +- bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait"; +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&clkc { +- fclk-enable = <0xf>; +- ps-clk-frequency = <33333333>; +-}; +- +-&gem0 { +- status = "okay"; +- phy-mode = "rgmii-id"; +- phy-handle = <ðernet_phy>; +- +- ethernet_phy: ethernet-phy@0 { +- /* Marvell 88E1318 */ +- compatible = "ethernet-phy-id0141.0e90", +- "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- device_type = "ethernet-phy"; +- marvell,reg-init = <0x3 0x10 0xff00 0x1e>, +- <0x3 0x11 0xfff0 0xa>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- isl9305: isl9305@68 { +- compatible = "isil,isl9305"; +- reg = <0x68>; +- +- regulators { +- dcd1 { +- regulator-name = "VDD_DSP"; +- regulator-always-on; +- }; +- dcd2 { +- regulator-name = "1P35V"; +- regulator-always-on; +- }; +- ldo1 { +- regulator-name = "VDD_ADJ"; +- }; +- ldo2 { +- regulator-name = "VDD_GPIO"; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&sdhci1 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/zynq-zc702.dts b/scripts/dtc/include-prefixes/arm/zynq-zc702.dts +deleted file mode 100644 +index cf70aff26c66..000000000000 +--- a/scripts/dtc/include-prefixes/arm/zynq-zc702.dts ++++ /dev/null +@@ -1,407 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2011 - 2014 Xilinx +- * Copyright (C) 2012 National Instruments Corp. +- */ +-/dts-v1/; +-#include "zynq-7000.dtsi" +- +-/ { +- model = "Xilinx ZC702 board"; +- compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; +- +- aliases { +- ethernet0 = &gem0; +- i2c0 = &i2c0; +- serial0 = &uart1; +- mmc0 = &sdhci0; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x40000000>; +- }; +- +- chosen { +- bootargs = ""; +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- sw14 { +- label = "sw14"; +- gpios = <&gpio0 12 0>; +- linux,code = <108>; /* down */ +- wakeup-source; +- autorepeat; +- }; +- sw13 { +- label = "sw13"; +- gpios = <&gpio0 14 0>; +- linux,code = <103>; /* up */ +- wakeup-source; +- autorepeat; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-ds23 { +- label = "ds23"; +- gpios = <&gpio0 10 0>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- usb_phy0: phy0 { +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- }; +-}; +- +-&amba { +- ocm: sram@fffc0000 { +- compatible = "mmio-sram"; +- reg = <0xfffc0000 0x10000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xfffc0000 0x10000>; +- ocm-sram@0 { +- reg = <0x0 0x10000>; +- }; +- }; +-}; +- +-&can0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can0_default>; +-}; +- +-&clkc { +- ps-clk-frequency = <33333333>; +-}; +- +-&gem0 { +- status = "okay"; +- phy-mode = "rgmii-id"; +- phy-handle = <ðernet_phy>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gem0_default>; +- +- ethernet_phy: ethernet-phy@7 { +- reg = <7>; +- device_type = "ethernet-phy"; +- }; +-}; +- +-&gpio0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio0_default>; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0_default>; +- +- i2c-mux@74 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x74>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- si570: clock-generator@5d { +- #clock-cells = <0>; +- compatible = "silabs,si570"; +- temperature-stability = <50>; +- reg = <0x5d>; +- factory-fout = <156250000>; +- clock-frequency = <148500000>; +- }; +- }; +- +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- adv7511: hdmi-tx@39 { +- compatible = "adi,adv7511"; +- reg = <0x39>; +- adi,input-depth = <8>; +- adi,input-colorspace = "yuv422"; +- adi,input-clock = "1x"; +- adi,input-style = <3>; +- adi,input-justification = "right"; +- }; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- eeprom@54 { +- compatible = "atmel,24c08"; +- reg = <0x54>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- gpio@21 { +- compatible = "ti,tca6416"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +- +- i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- }; +- +- i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- hwmon@34 { +- compatible = "ti,ucd9248"; +- reg = <0x34>; +- }; +- hwmon@35 { +- compatible = "ti,ucd9248"; +- reg = <0x35>; +- }; +- hwmon@36 { +- compatible = "ti,ucd9248"; +- reg = <0x36>; +- }; +- }; +- }; +-}; +- +-&pinctrl0 { +- pinctrl_can0_default: can0-default { +- mux { +- function = "can0"; +- groups = "can0_9_grp"; +- }; +- +- conf { +- groups = "can0_9_grp"; +- slew-rate = <0>; +- io-standard = <1>; +- }; +- +- conf-rx { +- pins = "MIO46"; +- bias-high-impedance; +- }; +- +- conf-tx { +- pins = "MIO47"; +- bias-disable; +- }; +- }; +- +- pinctrl_gem0_default: gem0-default { +- mux { +- function = "ethernet0"; +- groups = "ethernet0_0_grp"; +- }; +- +- conf { +- groups = "ethernet0_0_grp"; +- slew-rate = <0>; +- io-standard = <4>; +- }; +- +- conf-rx { +- pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; +- bias-high-impedance; +- low-power-disable; +- }; +- +- conf-tx { +- pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; +- bias-disable; +- low-power-enable; +- }; +- +- mux-mdio { +- function = "mdio0"; +- groups = "mdio0_0_grp"; +- }; +- +- conf-mdio { +- groups = "mdio0_0_grp"; +- slew-rate = <0>; +- io-standard = <1>; +- bias-disable; +- }; +- }; +- +- pinctrl_gpio0_default: gpio0-default { +- mux { +- function = "gpio0"; +- groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", +- "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", +- "gpio0_13_grp", "gpio0_14_grp"; +- }; +- +- conf { +- groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", +- "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", +- "gpio0_13_grp", "gpio0_14_grp"; +- slew-rate = <0>; +- io-standard = <1>; +- }; +- +- conf-pull-up { +- pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; +- bias-pull-up; +- }; +- +- conf-pull-none { +- pins = "MIO7", "MIO8"; +- bias-disable; +- }; +- }; +- +- pinctrl_i2c0_default: i2c0-default { +- mux { +- groups = "i2c0_10_grp"; +- function = "i2c0"; +- }; +- +- conf { +- groups = "i2c0_10_grp"; +- bias-pull-up; +- slew-rate = <0>; +- io-standard = <1>; +- }; +- }; +- +- pinctrl_sdhci0_default: sdhci0-default { +- mux { +- groups = "sdio0_2_grp"; +- function = "sdio0"; +- }; +- +- conf { +- groups = "sdio0_2_grp"; +- slew-rate = <0>; +- io-standard = <1>; +- bias-disable; +- }; +- +- mux-cd { +- groups = "gpio0_0_grp"; +- function = "sdio0_cd"; +- }; +- +- conf-cd { +- groups = "gpio0_0_grp"; +- bias-high-impedance; +- bias-pull-up; +- slew-rate = <0>; +- io-standard = <1>; +- }; +- +- mux-wp { +- groups = "gpio0_15_grp"; +- function = "sdio0_wp"; +- }; +- +- conf-wp { +- groups = "gpio0_15_grp"; +- bias-high-impedance; +- bias-pull-up; +- slew-rate = <0>; +- io-standard = <1>; +- }; +- }; +- +- pinctrl_uart1_default: uart1-default { +- mux { +- groups = "uart1_10_grp"; +- function = "uart1"; +- }; +- +- conf { +- groups = "uart1_10_grp"; +- slew-rate = <0>; +- io-standard = <1>; +- }; +- +- conf-rx { +- pins = "MIO49"; +- bias-high-impedance; +- }; +- +- conf-tx { +- pins = "MIO48"; +- bias-disable; +- }; +- }; +- +- pinctrl_usb0_default: usb0-default { +- mux { +- groups = "usb0_0_grp"; +- function = "usb0"; +- }; +- +- conf { +- groups = "usb0_0_grp"; +- slew-rate = <0>; +- io-standard = <1>; +- }; +- +- conf-rx { +- pins = "MIO29", "MIO31", "MIO36"; +- bias-high-impedance; +- }; +- +- conf-tx { +- pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", +- "MIO35", "MIO37", "MIO38", "MIO39"; +- bias-disable; +- }; +- }; +-}; +- +-&sdhci0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdhci0_default>; +-}; +- +-&uart1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1_default>; +-}; +- +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +- usb-phy = <&usb_phy0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb0_default>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/zynq-zc706.dts b/scripts/dtc/include-prefixes/arm/zynq-zc706.dts +deleted file mode 100644 +index 77943c16d33f..000000000000 +--- a/scripts/dtc/include-prefixes/arm/zynq-zc706.dts ++++ /dev/null +@@ -1,324 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2011 - 2014 Xilinx +- * Copyright (C) 2012 National Instruments Corp. +- */ +-/dts-v1/; +-#include "zynq-7000.dtsi" +- +-/ { +- model = "Xilinx ZC706 board"; +- compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; +- +- aliases { +- ethernet0 = &gem0; +- i2c0 = &i2c0; +- serial0 = &uart1; +- mmc0 = &sdhci0; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x40000000>; +- }; +- +- chosen { +- bootargs = ""; +- stdout-path = "serial0:115200n8"; +- }; +- +- usb_phy0: phy0 { +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- }; +-}; +- +-&clkc { +- ps-clk-frequency = <33333333>; +-}; +- +-&gem0 { +- status = "okay"; +- phy-mode = "rgmii-id"; +- phy-handle = <ðernet_phy>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gem0_default>; +- +- ethernet_phy: ethernet-phy@7 { +- reg = <7>; +- device_type = "ethernet-phy"; +- }; +-}; +- +-&gpio0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio0_default>; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0_default>; +- +- i2c-mux@74 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x74>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- si570: clock-generator@5d { +- #clock-cells = <0>; +- compatible = "silabs,si570"; +- temperature-stability = <50>; +- reg = <0x5d>; +- factory-fout = <156250000>; +- clock-frequency = <148500000>; +- }; +- }; +- +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- adv7511: hdmi-tx@39 { +- compatible = "adi,adv7511"; +- reg = <0x39>; +- adi,input-depth = <8>; +- adi,input-colorspace = "yuv422"; +- adi,input-clock = "1x"; +- adi,input-style = <3>; +- adi,input-justification = "evenly"; +- }; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- eeprom@54 { +- compatible = "atmel,24c08"; +- reg = <0x54>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- gpio@21 { +- compatible = "ti,tca6416"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +- +- i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- }; +- +- i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- ucd90120@65 { +- compatible = "ti,ucd90120"; +- reg = <0x65>; +- }; +- }; +- }; +-}; +- +-&pinctrl0 { +- pinctrl_gem0_default: gem0-default { +- mux { +- function = "ethernet0"; +- groups = "ethernet0_0_grp"; +- }; +- +- conf { +- groups = "ethernet0_0_grp"; +- slew-rate = <0>; +- io-standard = <4>; +- }; +- +- conf-rx { +- pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; +- bias-high-impedance; +- low-power-disable; +- }; +- +- conf-tx { +- pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; +- low-power-enable; +- bias-disable; +- }; +- +- mux-mdio { +- function = "mdio0"; +- groups = "mdio0_0_grp"; +- }; +- +- conf-mdio { +- groups = "mdio0_0_grp"; +- slew-rate = <0>; +- io-standard = <1>; +- bias-disable; +- }; +- }; +- +- pinctrl_gpio0_default: gpio0-default { +- mux { +- function = "gpio0"; +- groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; +- }; +- +- conf { +- groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; +- slew-rate = <0>; +- io-standard = <1>; +- }; +- +- conf-pull-up { +- pins = "MIO46", "MIO47"; +- bias-pull-up; +- }; +- +- conf-pull-none { +- pins = "MIO7"; +- bias-disable; +- }; +- }; +- +- pinctrl_i2c0_default: i2c0-default { +- mux { +- groups = "i2c0_10_grp"; +- function = "i2c0"; +- }; +- +- conf { +- groups = "i2c0_10_grp"; +- bias-pull-up; +- slew-rate = <0>; +- io-standard = <1>; +- }; +- }; +- +- pinctrl_sdhci0_default: sdhci0-default { +- mux { +- groups = "sdio0_2_grp"; +- function = "sdio0"; +- }; +- +- conf { +- groups = "sdio0_2_grp"; +- slew-rate = <0>; +- io-standard = <1>; +- bias-disable; +- }; +- +- mux-cd { +- groups = "gpio0_14_grp"; +- function = "sdio0_cd"; +- }; +- +- conf-cd { +- groups = "gpio0_14_grp"; +- bias-high-impedance; +- bias-pull-up; +- slew-rate = <0>; +- io-standard = <1>; +- }; +- +- mux-wp { +- groups = "gpio0_15_grp"; +- function = "sdio0_wp"; +- }; +- +- conf-wp { +- groups = "gpio0_15_grp"; +- bias-high-impedance; +- bias-pull-up; +- slew-rate = <0>; +- io-standard = <1>; +- }; +- }; +- +- pinctrl_uart1_default: uart1-default { +- mux { +- groups = "uart1_10_grp"; +- function = "uart1"; +- }; +- +- conf { +- groups = "uart1_10_grp"; +- slew-rate = <0>; +- io-standard = <1>; +- }; +- +- conf-rx { +- pins = "MIO49"; +- bias-high-impedance; +- }; +- +- conf-tx { +- pins = "MIO48"; +- bias-disable; +- }; +- }; +- +- pinctrl_usb0_default: usb0-default { +- mux { +- groups = "usb0_0_grp"; +- function = "usb0"; +- }; +- +- conf { +- groups = "usb0_0_grp"; +- slew-rate = <0>; +- io-standard = <1>; +- }; +- +- conf-rx { +- pins = "MIO29", "MIO31", "MIO36"; +- bias-high-impedance; +- }; +- +- conf-tx { +- pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", +- "MIO35", "MIO37", "MIO38", "MIO39"; +- bias-disable; +- }; +- }; +-}; +- +-&sdhci0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdhci0_default>; +-}; +- +-&uart1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1_default>; +-}; +- +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +- usb-phy = <&usb_phy0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb0_default>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/zynq-zc770-xm010.dts b/scripts/dtc/include-prefixes/arm/zynq-zc770-xm010.dts +deleted file mode 100644 +index 0dd352289a45..000000000000 +--- a/scripts/dtc/include-prefixes/arm/zynq-zc770-xm010.dts ++++ /dev/null +@@ -1,95 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Xilinx ZC770 XM010 board DTS +- * +- * Copyright (C) 2013-2018 Xilinx, Inc. +- */ +-/dts-v1/; +-#include "zynq-7000.dtsi" +- +-/ { +- model = "Xilinx ZC770 XM010 board"; +- compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; +- +- aliases { +- ethernet0 = &gem0; +- i2c0 = &i2c0; +- serial0 = &uart1; +- spi1 = &spi1; +- }; +- +- chosen { +- bootargs = ""; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x40000000>; +- }; +- +- usb_phy0: phy0 { +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- }; +-}; +- +-&can0 { +- status = "okay"; +-}; +- +-&gem0 { +- status = "okay"; +- phy-mode = "rgmii-id"; +- phy-handle = <ðernet_phy>; +- +- ethernet_phy: ethernet-phy@7 { +- reg = <7>; +- device_type = "ethernet-phy"; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <400000>; +- +- eeprom: eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- }; +- +-}; +- +-&sdhci0 { +- status = "okay"; +-}; +- +-&spi1 { +- status = "okay"; +- num-cs = <4>; +- is-decoded-cs = <0>; +- flash@1 { +- compatible = "sst25wf080", "jedec,spi-nor"; +- reg = <1>; +- spi-max-frequency = <1000000>; +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "data"; +- reg = <0x0 0x100000>; +- }; +- }; +- }; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +- usb-phy = <&usb_phy0>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/zynq-zc770-xm011.dts b/scripts/dtc/include-prefixes/arm/zynq-zc770-xm011.dts +deleted file mode 100644 +index 56732e8f6ca1..000000000000 +--- a/scripts/dtc/include-prefixes/arm/zynq-zc770-xm011.dts ++++ /dev/null +@@ -1,64 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Xilinx ZC770 XM011 board DTS +- * +- * Copyright (C) 2013-2018 Xilinx, Inc. +- */ +-/dts-v1/; +-#include "zynq-7000.dtsi" +- +-/ { +- model = "Xilinx ZC770 XM011 board"; +- compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000"; +- +- aliases { +- i2c0 = &i2c1; +- serial0 = &uart1; +- spi0 = &spi0; +- }; +- +- chosen { +- bootargs = ""; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x40000000>; +- }; +- +- usb_phy1: phy1 { +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- }; +-}; +- +-&can0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- eeprom: eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- num-cs = <4>; +- is-decoded-cs = <0>; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +- dr_mode = "host"; +- usb-phy = <&usb_phy1>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/zynq-zc770-xm012.dts b/scripts/dtc/include-prefixes/arm/zynq-zc770-xm012.dts +deleted file mode 100644 +index d2359b789eb8..000000000000 +--- a/scripts/dtc/include-prefixes/arm/zynq-zc770-xm012.dts ++++ /dev/null +@@ -1,64 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Xilinx ZC770 XM012 board DTS +- * +- * Copyright (C) 2013-2018 Xilinx, Inc. +- */ +-/dts-v1/; +-#include "zynq-7000.dtsi" +- +-/ { +- model = "Xilinx ZC770 XM012 board"; +- compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- serial0 = &uart1; +- spi0 = &spi1; +- }; +- +- chosen { +- bootargs = ""; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x40000000>; +- }; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <400000>; +- +- eeprom0: eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- eeprom1: eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- }; +-}; +- +-&spi1 { +- status = "okay"; +- num-cs = <4>; +- is-decoded-cs = <0>; +-}; +- +-&uart1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/zynq-zc770-xm013.dts b/scripts/dtc/include-prefixes/arm/zynq-zc770-xm013.dts +deleted file mode 100644 +index 38d96adc870c..000000000000 +--- a/scripts/dtc/include-prefixes/arm/zynq-zc770-xm013.dts ++++ /dev/null +@@ -1,77 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Xilinx ZC770 XM013 board DTS +- * +- * Copyright (C) 2013 Xilinx, Inc. +- */ +-/dts-v1/; +-#include "zynq-7000.dtsi" +- +-/ { +- model = "Xilinx ZC770 XM013 board"; +- compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; +- +- aliases { +- ethernet0 = &gem1; +- i2c0 = &i2c1; +- serial0 = &uart0; +- spi1 = &spi0; +- }; +- +- chosen { +- bootargs = ""; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x40000000>; +- }; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&gem1 { +- status = "okay"; +- phy-mode = "rgmii-id"; +- phy-handle = <ðernet_phy>; +- +- ethernet_phy: ethernet-phy@7 { +- reg = <7>; +- device_type = "ethernet-phy"; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- si570: clock-generator@55 { +- #clock-cells = <0>; +- compatible = "silabs,si570"; +- temperature-stability = <50>; +- reg = <0x55>; +- factory-fout = <156250000>; +- clock-frequency = <148500000>; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- num-cs = <4>; +- is-decoded-cs = <0>; +- eeprom: eeprom@2 { +- compatible = "atmel,at25"; +- reg = <2>; +- spi-max-frequency = <1000000>; +- size = <8192>; +- address-width = <16>; +- pagesize = <32>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/zynq-zed.dts b/scripts/dtc/include-prefixes/arm/zynq-zed.dts +deleted file mode 100644 +index 6a5a93aa6552..000000000000 +--- a/scripts/dtc/include-prefixes/arm/zynq-zed.dts ++++ /dev/null +@@ -1,62 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2011 - 2014 Xilinx +- * Copyright (C) 2012 National Instruments Corp. +- */ +-/dts-v1/; +-#include "zynq-7000.dtsi" +- +-/ { +- model = "Avnet ZedBoard board"; +- compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000"; +- +- aliases { +- ethernet0 = &gem0; +- serial0 = &uart1; +- mmc0 = &sdhci0; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x20000000>; +- }; +- +- chosen { +- bootargs = ""; +- stdout-path = "serial0:115200n8"; +- }; +- +- usb_phy0: phy0 { +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- }; +-}; +- +-&clkc { +- ps-clk-frequency = <33333333>; +-}; +- +-&gem0 { +- status = "okay"; +- phy-mode = "rgmii-id"; +- phy-handle = <ðernet_phy>; +- +- ethernet_phy: ethernet-phy@0 { +- reg = <0>; +- device_type = "ethernet-phy"; +- }; +-}; +- +-&sdhci0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +- usb-phy = <&usb_phy0>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/zynq-zturn-common.dtsi b/scripts/dtc/include-prefixes/arm/zynq-zturn-common.dtsi +deleted file mode 100644 +index bf5d1c4568b0..000000000000 +--- a/scripts/dtc/include-prefixes/arm/zynq-zturn-common.dtsi ++++ /dev/null +@@ -1,112 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2015 Andrea Merello +- * Copyright (C) 2017 Alexander Graf +- * +- * Based on zynq-zed.dts which is: +- * Copyright (C) 2011 - 2014 Xilinx +- * Copyright (C) 2012 National Instruments Corp. +- * +- */ +- +-/dts-v1/; +-/include/ "zynq-7000.dtsi" +- +-/ { +- compatible = "xlnx,zynq-7000"; +- +- aliases { +- ethernet0 = &gem0; +- serial0 = &uart1; +- serial1 = &uart0; +- mmc0 = &sdhci0; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x40000000>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- usr-led1 { +- label = "usr-led1"; +- gpios = <&gpio0 0x0 0x1>; +- default-state = "off"; +- }; +- +- usr-led2 { +- label = "usr-led2"; +- gpios = <&gpio0 0x9 0x1>; +- default-state = "off"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- K1 { +- label = "K1"; +- gpios = <&gpio0 0x32 0x1>; +- linux,code = <0x66>; +- wakeup-source; +- autorepeat; +- }; +- }; +-}; +- +-&clkc { +- ps-clk-frequency = <33333333>; +-}; +- +-&gem0 { +- status = "okay"; +- phy-mode = "rgmii-id"; +- phy-handle = <ðernet_phy>; +- +- ethernet_phy: ethernet-phy@0 { +- }; +-}; +- +-&sdhci0 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&can0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <400000>; +- +- stlm75@49 { +- status = "okay"; +- compatible = "lm75"; +- reg = <0x49>; +- }; +- +- accelerometer@53 { +- compatible = "adi,adxl345"; +- reg = <0x53>; +- interrupt-parent = <&intc>; +- interrupts = <0x0 0x1e 0x4>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/zynq-zturn-v5.dts b/scripts/dtc/include-prefixes/arm/zynq-zturn-v5.dts +deleted file mode 100644 +index 536632a09a25..000000000000 +--- a/scripts/dtc/include-prefixes/arm/zynq-zturn-v5.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/dts-v1/; +-/include/ "zynq-zturn-common.dtsi" +- +-/ { +- model = "Zynq Z-Turn MYIR Board V5"; +- compatible = "myir,zynq-zturn-v5", "xlnx,zynq-7000"; +-}; +- +-&gem0 { +- ethernet_phy: ethernet-phy@0 { +- reg = <0x3>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/zynq-zturn.dts b/scripts/dtc/include-prefixes/arm/zynq-zturn.dts +deleted file mode 100644 +index 620b24a25e06..000000000000 +--- a/scripts/dtc/include-prefixes/arm/zynq-zturn.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/dts-v1/; +-/include/ "zynq-zturn-common.dtsi" +- +-/ { +- model = "Zynq Z-Turn MYIR Board"; +- compatible = "myir,zynq-zturn", "xlnx,zynq-7000"; +-}; +- +-&gem0 { +- ethernet_phy: ethernet-phy@0 { +- reg = <0x0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/zynq-zybo-z7.dts b/scripts/dtc/include-prefixes/arm/zynq-zybo-z7.dts +deleted file mode 100644 +index 7b87e10d3953..000000000000 +--- a/scripts/dtc/include-prefixes/arm/zynq-zybo-z7.dts ++++ /dev/null +@@ -1,68 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/dts-v1/; +-#include "zynq-7000.dtsi" +-#include +- +-/ { +- model = "Digilent Zybo Z7 board"; +- compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000"; +- +- aliases { +- ethernet0 = &gem0; +- serial0 = &uart1; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x40000000>; +- }; +- +- chosen { +- bootargs = ""; +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- led-ld4 { +- label = "zynq-zybo-z7:green:ld4"; +- gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- usb_phy0: phy0 { +- #phy-cells = <0>; +- compatible = "usb-nop-xceiv"; +- reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&clkc { +- ps-clk-frequency = <33333333>; +-}; +- +-&gem0 { +- status = "okay"; +- phy-mode = "rgmii-id"; +- phy-handle = <ðernet_phy>; +- +- ethernet_phy: ethernet-phy@0 { +- reg = <0>; +- device_type = "ethernet-phy"; +- }; +-}; +- +-&sdhci0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +- usb-phy = <&usb_phy0>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm/zynq-zybo.dts b/scripts/dtc/include-prefixes/arm/zynq-zybo.dts +deleted file mode 100644 +index 755f6f109d5a..000000000000 +--- a/scripts/dtc/include-prefixes/arm/zynq-zybo.dts ++++ /dev/null +@@ -1,63 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2011 - 2014 Xilinx +- * Copyright (C) 2012 National Instruments Corp. +- */ +-/dts-v1/; +-#include "zynq-7000.dtsi" +- +-/ { +- model = "Digilent Zybo board"; +- compatible = "digilent,zynq-zybo", "xlnx,zynq-7000"; +- +- aliases { +- ethernet0 = &gem0; +- serial0 = &uart1; +- mmc0 = &sdhci0; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x20000000>; +- }; +- +- chosen { +- bootargs = ""; +- stdout-path = "serial0:115200n8"; +- }; +- +- usb_phy0: phy0 { +- #phy-cells = <0>; +- compatible = "usb-nop-xceiv"; +- reset-gpios = <&gpio0 46 1>; +- }; +-}; +- +-&clkc { +- ps-clk-frequency = <50000000>; +-}; +- +-&gem0 { +- status = "okay"; +- phy-mode = "rgmii-id"; +- phy-handle = <ðernet_phy>; +- +- ethernet_phy: ethernet-phy@0 { +- reg = <0>; +- device_type = "ethernet-phy"; +- }; +-}; +- +-&sdhci0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +- usb-phy = <&usb_phy0>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64 b/scripts/dtc/include-prefixes/arm64 +new file mode 120000 +index 000000000000..275c42c21d71 +--- /dev/null ++++ b/scripts/dtc/include-prefixes/arm64 +@@ -0,0 +1 @@ ++../../../arch/arm64/boot/dts +\ No newline at end of file +diff --git a/scripts/dtc/include-prefixes/arm64/Makefile b/scripts/dtc/include-prefixes/arm64/Makefile +deleted file mode 100644 +index 727146feabf4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/Makefile ++++ /dev/null +@@ -1,33 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-subdir-y += actions +-subdir-y += allwinner +-subdir-y += altera +-subdir-y += amazon +-subdir-y += amd +-subdir-y += amlogic +-subdir-y += apm +-subdir-y += apple +-subdir-y += arm +-subdir-y += bitmain +-subdir-y += broadcom +-subdir-y += cavium +-subdir-y += exynos +-subdir-y += freescale +-subdir-y += hailo +-subdir-y += hisilicon +-subdir-y += intel +-subdir-y += lg +-subdir-y += marvell +-subdir-y += mediatek +-subdir-y += microchip +-subdir-y += nvidia +-subdir-y += qcom +-subdir-y += realtek +-subdir-y += renesas +-subdir-y += rockchip +-subdir-y += socionext +-subdir-y += sprd +-subdir-y += synaptics +-subdir-y += ti +-subdir-y += toshiba +-subdir-y += xilinx +diff --git a/scripts/dtc/include-prefixes/arm64/actions/Makefile b/scripts/dtc/include-prefixes/arm64/actions/Makefile +deleted file mode 100644 +index b57fd2372ecd..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/actions/Makefile ++++ /dev/null +@@ -1,5 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0+ +- +-dtb-$(CONFIG_ARCH_ACTIONS) += s700-cubieboard7.dtb +- +-dtb-$(CONFIG_ARCH_ACTIONS) += s900-bubblegum-96.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/actions/s700-cubieboard7.dts b/scripts/dtc/include-prefixes/arm64/actions/s700-cubieboard7.dts +deleted file mode 100644 +index 63e375cd9eb4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/actions/s700-cubieboard7.dts ++++ /dev/null +@@ -1,92 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "s700.dtsi" +- +-/ { +- compatible = "cubietech,cubieboard7", "actions,s700"; +- model = "CubieBoard7"; +- +- aliases { +- serial3 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial3:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- memory@1,e0000000 { +- device_type = "memory"; +- reg = <0x1 0xe0000000 0x0 0x0>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_default>; +-}; +- +-&i2c1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_default>; +-}; +- +-&i2c2 { +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_default>; +-}; +- +-&pinctrl { +- i2c0_default: i2c0_default { +- pinmux { +- groups = "i2c0_mfp"; +- function = "i2c0"; +- }; +- pinconf { +- pins = "i2c0_sclk", "i2c0_sdata"; +- bias-pull-up; +- }; +- }; +- +- i2c1_default: i2c1_default { +- pinmux { +- groups = "i2c1_dummy"; +- function = "i2c1"; +- }; +- pinconf { +- pins = "i2c1_sclk", "i2c1_sdata"; +- bias-pull-up; +- }; +- }; +- +- i2c2_default: i2c2_default { +- pinmux { +- groups = "i2c2_dummy"; +- function = "i2c2"; +- }; +- pinconf { +- pins = "i2c2_sclk", "i2c2_sdata"; +- bias-pull-up; +- }; +- }; +-}; +- +-&timer { +- clocks = <&hosc>; +-}; +- +-&uart3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/actions/s700.dtsi b/scripts/dtc/include-prefixes/arm64/actions/s700.dtsi +deleted file mode 100644 +index 2c78caebf515..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/actions/s700.dtsi ++++ /dev/null +@@ -1,263 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Andreas Färber +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "actions,s700"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- }; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- secmon@1f000000 { +- reg = <0x0 0x1f000000 0x0 0x1000000>; +- no-map; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- hosc: hosc { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- #clock-cells = <0>; +- }; +- +- losc: losc { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gic: interrupt-controller@e00f1000 { +- compatible = "arm,gic-400"; +- reg = <0x0 0xe00f1000 0x0 0x1000>, +- <0x0 0xe00f2000 0x0 0x2000>, +- <0x0 0xe00f4000 0x0 0x2000>, +- <0x0 0xe00f6000 0x0 0x2000>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- +- uart0: serial@e0120000 { +- compatible = "actions,s900-uart", "actions,owl-uart"; +- reg = <0x0 0xe0120000 0x0 0x2000>; +- clocks = <&cmu CLK_UART0>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart1: serial@e0122000 { +- compatible = "actions,s900-uart", "actions,owl-uart"; +- reg = <0x0 0xe0122000 0x0 0x2000>; +- clocks = <&cmu CLK_UART1>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart2: serial@e0124000 { +- compatible = "actions,s900-uart", "actions,owl-uart"; +- reg = <0x0 0xe0124000 0x0 0x2000>; +- clocks = <&cmu CLK_UART2>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart3: serial@e0126000 { +- compatible = "actions,s900-uart", "actions,owl-uart"; +- reg = <0x0 0xe0126000 0x0 0x2000>; +- clocks = <&cmu CLK_UART3>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart4: serial@e0128000 { +- compatible = "actions,s900-uart", "actions,owl-uart"; +- reg = <0x0 0xe0128000 0x0 0x2000>; +- clocks = <&cmu CLK_UART4>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart5: serial@e012a000 { +- compatible = "actions,s900-uart", "actions,owl-uart"; +- reg = <0x0 0xe012a000 0x0 0x2000>; +- clocks = <&cmu CLK_UART5>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart6: serial@e012c000 { +- compatible = "actions,s900-uart", "actions,owl-uart"; +- reg = <0x0 0xe012c000 0x0 0x2000>; +- clocks = <&cmu CLK_UART6>; +- interrupts = ; +- status = "disabled"; +- }; +- +- cmu: clock-controller@e0168000 { +- compatible = "actions,s700-cmu"; +- reg = <0x0 0xe0168000 0x0 0x1000>; +- clocks = <&hosc>, <&losc>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- i2c0: i2c@e0170000 { +- compatible = "actions,s700-i2c"; +- reg = <0 0xe0170000 0 0x1000>; +- clocks = <&cmu CLK_I2C0>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e0174000 { +- compatible = "actions,s700-i2c"; +- reg = <0 0xe0174000 0 0x1000>; +- clocks = <&cmu CLK_I2C1>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e0178000 { +- compatible = "actions,s700-i2c"; +- reg = <0 0xe0178000 0 0x1000>; +- clocks = <&cmu CLK_I2C2>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e017c000 { +- compatible = "actions,s700-i2c"; +- reg = <0 0xe017c000 0 0x1000>; +- clocks = <&cmu CLK_I2C3>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- sps: power-controller@e01b0100 { +- compatible = "actions,s700-sps"; +- reg = <0x0 0xe01b0100 0x0 0x100>; +- #power-domain-cells = <1>; +- }; +- +- timer: timer@e024c000 { +- compatible = "actions,s700-timer"; +- reg = <0x0 0xe024c000 0x0 0x4000>; +- interrupts = ; +- interrupt-names = "timer1"; +- }; +- +- pinctrl: pinctrl@e01b0000 { +- compatible = "actions,s700-pinctrl"; +- reg = <0x0 0xe01b0000 0x0 0x100>; +- clocks = <&cmu CLK_GPIO>; +- gpio-controller; +- gpio-ranges = <&pinctrl 0 0 136>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = , +- , +- , +- , +- ; +- }; +- +- dma: dma-controller@e0230000 { +- compatible = "actions,s700-dma"; +- reg = <0x0 0xe0230000 0x0 0x1000>; +- interrupts = , +- , +- , +- ; +- #dma-cells = <1>; +- dma-channels = <10>; +- dma-requests = <44>; +- clocks = <&cmu CLK_DMAC>; +- power-domains = <&sps S700_PD_DMA>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/actions/s900-bubblegum-96.dts b/scripts/dtc/include-prefixes/arm64/actions/s900-bubblegum-96.dts +deleted file mode 100644 +index 59291e0ea1ee..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/actions/s900-bubblegum-96.dts ++++ /dev/null +@@ -1,314 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "s900.dtsi" +- +-/ { +- compatible = "ucrobotics,bubblegum-96", "actions,s900"; +- model = "Bubblegum-96"; +- +- aliases { +- mmc0 = &mmc0; +- mmc1 = &mmc1; +- mmc2 = &mmc2; +- serial5 = &uart5; +- }; +- +- chosen { +- stdout-path = "serial5:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- /* Fixed regulator used in the absence of PMIC */ +- vcc_3v1: vcc-3v1 { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.1V"; +- regulator-min-microvolt = <3100000>; +- regulator-max-microvolt = <3100000>; +- regulator-always-on; +- }; +- +- /* Fixed regulator used in the absence of PMIC */ +- sd_vcc: sd-vcc { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.1V"; +- regulator-min-microvolt = <3100000>; +- regulator-max-microvolt = <3100000>; +- regulator-always-on; +- }; +-}; +- +-&i2c0 { +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_default>; +-}; +- +-&i2c1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_default>; +-}; +- +-&i2c2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_default>; +-}; +- +-/* +- * GPIO name legend: proper name = the GPIO line is used as GPIO +- * NC = not connected (pin out but not routed from the chip to +- * anything the board) +- * "[PER]" = pin is muxed for [peripheral] (not GPIO) +- * LSEC = Low Speed External Connector +- * HSEC = High Speed External Connector +- * +- * Line names are taken from the schematic "Schematics Bubblegum96" +- * version v1.0 +- * +- * For the lines routed to the external connectors the +- * lines are named after the 96Boards CE Specification 1.0, +- * Appendix "Expansion Connector Signal Description". +- * +- * When the 96Boards naming of a line and the schematic name of +- * the same line are in conflict, the 96Boards specification +- * takes precedence, which means that the external UART on the +- * LSEC is named UART0 while the schematic and SoC names this +- * UART2. Only exception is the I2C lines for which the schematic +- * naming has been preferred. This is only for the informational +- * lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L" +- * are the only ones actually used for GPIO. +- */ +- +-&pinctrl { +- gpio-line-names = +- "GPIO-A", /* GPIO_0, LSEC pin 23 */ +- "GPIO-B", /* GPIO_1, LSEC pin 24 */ +- "GPIO-C", /* GPIO_2, LSEC pin 25 */ +- "GPIO-D", /* GPIO_3, LSEC pin 26 */ +- "GPIO-E", /* GPIO_4, LSEC pin 27 */ +- "GPIO-F", /* GPIO_5, LSEC pin 28 */ +- "GPIO-G", /* GPIO_6, LSEC pin 29 */ +- "GPIO-H", /* GPIO_7, LSEC pin 30 */ +- "GPIO-I", /* GPIO_8, LSEC pin 31 */ +- "GPIO-J", /* GPIO_9, LSEC pin 32 */ +- "NC", /* GPIO_10 */ +- "NC", /* GPIO_11 */ +- "SIRQ2_1V8", /* GPIO_12 */ +- "PCM0_OUT", /* GPIO_13 */ +- "WIFI_LED", /* GPIO_14 */ +- "PCM0_SYNC", /* GPIO_15 */ +- "PCM0_CLK", /* GPIO_16 */ +- "PCM0_IN", /* GPIO_17 */ +- "BT_LED", /* GPIO_18 */ +- "LED0", /* GPIO_19 */ +- "LED1", /* GPIO_20 */ +- "JTAG_TCK", /* GPIO_21 */ +- "JTAG_TMS", /* GPIO_22 */ +- "JTAG_TDI", /* GPIO_23 */ +- "JTAG_TDO", /* GPIO_24 */ +- "[UART1_RxD]", /* GPIO_25, LSEC pin 13 */ +- "NC", /* GPIO_26 */ +- "[UART1_TxD]", /* GPIO_27, LSEC pin 11 */ +- "SD0_D0", /* GPIO_28 */ +- "SD0_D1", /* GPIO_29 */ +- "SD0_D2", /* GPIO_30 */ +- "SD0_D3", /* GPIO_31 */ +- "SD1_D0", /* GPIO_32 */ +- "SD1_D1", /* GPIO_33 */ +- "SD1_D2", /* GPIO_34 */ +- "SD1_D3", /* GPIO_35 */ +- "SD0_CMD", /* GPIO_36 */ +- "SD0_CLK", /* GPIO_37 */ +- "SD1_CMD", /* GPIO_38 */ +- "SD1_CLK", /* GPIO_39 */ +- "SPI0_SCLK", /* GPIO_40, LSEC pin 8 */ +- "SPI0_CS", /* GPIO_41, LSEC pin 12 */ +- "SPI0_DIN", /* GPIO_42, LSEC pin 10 */ +- "SPI0_DOUT", /* GPIO_43, LSEC pin 14 */ +- "I2C5_SDATA", /* GPIO_44, HSEC pin 36 */ +- "I2C5_SCLK", /* GPIO_45, HSEC pin 38 */ +- "UART0_RX", /* GPIO_46, LSEC pin 7 */ +- "UART0_TX", /* GPIO_47, LSEC pin 5 */ +- "UART0_RTSB", /* GPIO_48, LSEC pin 9 */ +- "UART0_CTSB", /* GPIO_49, LSEC pin 3 */ +- "I2C4_SCLK", /* GPIO_50, HSEC pin 32 */ +- "I2C4_SDATA", /* GPIO_51, HSEC pin 34 */ +- "I2C0_SCLK", /* GPIO_52 */ +- "I2C0_SDATA", /* GPIO_53 */ +- "I2C1_SCLK", /* GPIO_54, LSEC pin 15 */ +- "I2C1_SDATA", /* GPIO_55, LSEC pin 17 */ +- "I2C2_SCLK", /* GPIO_56, LSEC pin 19 */ +- "I2C2_SDATA", /* GPIO_57, LSEC pin 21 */ +- "CSI0_DN0", /* GPIO_58, HSEC pin 10 */ +- "CSI0_DP0", /* GPIO_59, HSEC pin 8 */ +- "CSI0_DN1", /* GPIO_60, HSEC pin 16 */ +- "CSI0_DP1", /* GPIO_61, HSEC pin 14 */ +- "CSI0_CN", /* GPIO_62, HSEC pin 4 */ +- "CSI0_CP", /* GPIO_63, HSEC pin 2 */ +- "CSI0_DN2", /* GPIO_64, HSEC pin 22 */ +- "CSI0_DP2", /* GPIO_65, HSEC pin 20 */ +- "CSI0_DN3", /* GPIO_66, HSEC pin 28 */ +- "CSI0_DP3", /* GPIO_67, HSEC pin 26 */ +- "[CLK0]", /* GPIO_68, HSEC pin 15 */ +- "CSI1_DN0", /* GPIO_69, HSEC pin 44 */ +- "CSI1_DP0", /* GPIO_70, HSEC pin 42 */ +- "CSI1_DN1", /* GPIO_71, HSEC pin 50 */ +- "CSI1_DP1", /* GPIO_72, HSEC pin 48 */ +- "CSI1_CN", /* GPIO_73, HSEC pin 56 */ +- "CSI1_CP", /* GPIO_74, HSEC pin 54 */ +- "[CLK1]", /* GPIO_75, HSEC pin 17 */ +- "[GPIOD0]", /* GPIO_76 */ +- "[GPIOD1]", /* GPIO_77 */ +- "BT_RST_N", /* GPIO_78 */ +- "EXT_DC_EN", /* GPIO_79 */ +- "[PCM_DI]", /* GPIO_80, LSEC pin 22 */ +- "[PCM_DO]", /* GPIO_81, LSEC pin 20 */ +- "[PCM_CLK]", /* GPIO_82, LSEC pin 18 */ +- "[PCM_FS]", /* GPIO_83, LSEC pin 16 */ +- "WAKE_BT", /* GPIO_84 */ +- "WL_REG_ON", /* GPIO_85 */ +- "NC", /* GPIO_86 */ +- "NC", /* GPIO_87 */ +- "NC", /* GPIO_88 */ +- "NC", /* GPIO_89 */ +- "NC", /* GPIO_90 */ +- "WIFI_WAKE", /* GPIO_91 */ +- "BT_WAKE", /* GPIO_92 */ +- "NC", /* GPIO_93 */ +- "OTG_EN2", /* GPIO_94 */ +- "OTG_EN", /* GPIO_95 */ +- "DSI_DP3", /* GPIO_96, HSEC pin 45 */ +- "DSI_DN3", /* GPIO_97, HSEC pin 47 */ +- "DSI_DP1", /* GPIO_98, HSEC pin 33 */ +- "DSI_DN1", /* GPIO_99, HSEC pin 35 */ +- "DSI_CP", /* GPIO_100, HSEC pin 21 */ +- "DSI_CN", /* GPIO_101, HSEC pin 23 */ +- "DSI_DP0", /* GPIO_102, HSEC pin 27 */ +- "DSI_DN0", /* GPIO_103, HSEC pin 29 */ +- "DSI_DP2", /* GPIO_104, HSEC pin 39 */ +- "DSI_DN2", /* GPIO_105, HSEC pin 41 */ +- "N0_D0", /* GPIO_106 */ +- "N0_D1", /* GPIO_107 */ +- "N0_D2", /* GPIO_108 */ +- "N0_D3", /* GPIO_109 */ +- "N0_D4", /* GPIO_110 */ +- "N0_D5", /* GPIO_111 */ +- "N0_D6", /* GPIO_112 */ +- "N0_D7", /* GPIO_113 */ +- "N0_DQS", /* GPIO_114 */ +- "N0_DQSN", /* GPIO_115 */ +- "NC", /* GPIO_116 */ +- "NC", /* GPIO_117 */ +- "NC", /* GPIO_118 */ +- "N0_CEB1", /* GPIO_119 */ +- "CARD_DT", /* GPIO_120 */ +- "N0_CEB3", /* GPIO_121 */ +- "SD_DAT0", /* GPIO_122, HSEC pin 1 */ +- "SD_DAT1", /* GPIO_123, HSEC pin 3 */ +- "SD_DAT2", /* GPIO_124, HSEC pin 5 */ +- "SD_DAT3", /* GPIO_125, HSEC pin 7 */ +- "NC", /* GPIO_126 */ +- "NC", /* GPIO_127 */ +- "[PWR_BTN_N]", /* GPIO_128, LSEC pin 4 */ +- "[RST_BTN_N]", /* GPIO_129, LSEC pin 6 */ +- "NC", /* GPIO_130 */ +- "SD_CMD", /* GPIO_131 */ +- "GPIO-L", /* GPIO_132, LSEC pin 34 */ +- "GPIO-K", /* GPIO_133, LSEC pin 33 */ +- "NC", /* GPIO_134 */ +- "SD_SCLK", /* GPIO_135 */ +- "NC", /* GPIO_136 */ +- "JTAG_TRST", /* GPIO_137 */ +- "I2C3_SCLK", /* GPIO_138 */ +- "LED2", /* GPIO_139 */ +- "LED3", /* GPIO_140 */ +- "I2C3_SDATA", /* GPIO_141 */ +- "UART3_RX", /* GPIO_142 */ +- "UART3_TX", /* GPIO_143 */ +- "UART3_RTSB", /* GPIO_144 */ +- "UART3_CTSB"; /* GPIO_145 */ +- +- i2c0_default: i2c0-default { +- pinmux { +- groups = "i2c0_mfp"; +- function = "i2c0"; +- }; +- pinconf { +- pins = "i2c0_sclk", "i2c0_sdata"; +- bias-pull-up; +- }; +- }; +- +- i2c1_default: i2c1-default { +- pinconf { +- pins = "i2c1_sclk", "i2c1_sdata"; +- bias-pull-up; +- }; +- }; +- +- i2c2_default: i2c2-default { +- pinconf { +- pins = "i2c2_sclk", "i2c2_sdata"; +- bias-pull-up; +- }; +- }; +- +- mmc0_default: mmc0_default { +- pinmux { +- groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp", +- "sd0_cmd_mfp", "sd0_clk_mfp"; +- function = "sd0"; +- }; +- }; +- +- mmc2_default: mmc2_default { +- pinmux { +- groups = "nand0_d0_ceb3_mfp"; +- function = "sd2"; +- }; +- }; +-}; +- +-/* uSD */ +-&mmc0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_default>; +- no-sdio; +- no-mmc; +- no-1-8-v; +- cd-gpios = <&pinctrl 120 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- vmmc-supply = <&sd_vcc>; +- vqmmc-supply = <&sd_vcc>; +-}; +- +-/* eMMC */ +-&mmc2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_default>; +- no-sdio; +- no-sd; +- non-removable; +- bus-width = <8>; +- vmmc-supply = <&vcc_3v1>; +-}; +- +-&timer { +- clocks = <&hosc>; +-}; +- +-&uart5 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/actions/s900.dtsi b/scripts/dtc/include-prefixes/arm64/actions/s900.dtsi +deleted file mode 100644 +index eb35cf78ab73..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/actions/s900.dtsi ++++ /dev/null +@@ -1,333 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Andreas Färber +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "actions,s900"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- }; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- secmon@1f000000 { +- reg = <0x0 0x1f000000 0x0 0x1000000>; +- no-map; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- hosc: hosc { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- #clock-cells = <0>; +- }; +- +- losc: losc { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- diff24M: diff24M { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- #clock-cells = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gic: interrupt-controller@e00f1000 { +- compatible = "arm,gic-400"; +- reg = <0x0 0xe00f1000 0x0 0x1000>, +- <0x0 0xe00f2000 0x0 0x2000>, +- <0x0 0xe00f4000 0x0 0x2000>, +- <0x0 0xe00f6000 0x0 0x2000>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- +- uart0: serial@e0120000 { +- compatible = "actions,s900-uart", "actions,owl-uart"; +- reg = <0x0 0xe0120000 0x0 0x2000>; +- clocks = <&cmu CLK_UART0>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart1: serial@e0122000 { +- compatible = "actions,s900-uart", "actions,owl-uart"; +- reg = <0x0 0xe0122000 0x0 0x2000>; +- clocks = <&cmu CLK_UART1>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart2: serial@e0124000 { +- compatible = "actions,s900-uart", "actions,owl-uart"; +- reg = <0x0 0xe0124000 0x0 0x2000>; +- clocks = <&cmu CLK_UART2>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart3: serial@e0126000 { +- compatible = "actions,s900-uart", "actions,owl-uart"; +- reg = <0x0 0xe0126000 0x0 0x2000>; +- clocks = <&cmu CLK_UART3>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart4: serial@e0128000 { +- compatible = "actions,s900-uart", "actions,owl-uart"; +- reg = <0x0 0xe0128000 0x0 0x2000>; +- clocks = <&cmu CLK_UART4>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart5: serial@e012a000 { +- compatible = "actions,s900-uart", "actions,owl-uart"; +- reg = <0x0 0xe012a000 0x0 0x2000>; +- clocks = <&cmu CLK_UART5>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart6: serial@e012c000 { +- compatible = "actions,s900-uart", "actions,owl-uart"; +- reg = <0x0 0xe012c000 0x0 0x2000>; +- clocks = <&cmu CLK_UART6>; +- interrupts = ; +- status = "disabled"; +- }; +- +- sps: power-controller@e012e000 { +- compatible = "actions,s900-sps"; +- reg = <0x0 0xe012e000 0x0 0x2000>; +- #power-domain-cells = <1>; +- }; +- +- cmu: clock-controller@e0160000 { +- compatible = "actions,s900-cmu"; +- reg = <0x0 0xe0160000 0x0 0x1000>; +- clocks = <&hosc>, <&losc>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- i2c0: i2c@e0170000 { +- compatible = "actions,s900-i2c"; +- reg = <0 0xe0170000 0 0x1000>; +- clocks = <&cmu CLK_I2C0>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e0172000 { +- compatible = "actions,s900-i2c"; +- reg = <0 0xe0172000 0 0x1000>; +- clocks = <&cmu CLK_I2C1>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e0174000 { +- compatible = "actions,s900-i2c"; +- reg = <0 0xe0174000 0 0x1000>; +- clocks = <&cmu CLK_I2C2>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e0176000 { +- compatible = "actions,s900-i2c"; +- reg = <0 0xe0176000 0 0x1000>; +- clocks = <&cmu CLK_I2C3>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e0178000 { +- compatible = "actions,s900-i2c"; +- reg = <0 0xe0178000 0 0x1000>; +- clocks = <&cmu CLK_I2C4>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c5: i2c@e017a000 { +- compatible = "actions,s900-i2c"; +- reg = <0 0xe017a000 0 0x1000>; +- clocks = <&cmu CLK_I2C5>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pinctrl: pinctrl@e01b0000 { +- compatible = "actions,s900-pinctrl"; +- reg = <0x0 0xe01b0000 0x0 0x1000>; +- clocks = <&cmu CLK_GPIO>; +- gpio-controller; +- gpio-ranges = <&pinctrl 0 0 146>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = , +- , +- , +- , +- , +- ; +- }; +- +- timer: timer@e0228000 { +- compatible = "actions,s900-timer"; +- reg = <0x0 0xe0228000 0x0 0x8000>; +- interrupts = ; +- interrupt-names = "timer1"; +- }; +- +- dma: dma-controller@e0260000 { +- compatible = "actions,s900-dma"; +- reg = <0x0 0xe0260000 0x0 0x1000>; +- interrupts = , +- , +- , +- ; +- #dma-cells = <1>; +- dma-channels = <12>; +- dma-requests = <46>; +- clocks = <&cmu CLK_DMAC>; +- }; +- +- mmc0: mmc@e0330000 { +- compatible = "actions,owl-mmc"; +- reg = <0x0 0xe0330000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cmu CLK_SD0>; +- resets = <&cmu RESET_SD0>; +- dmas = <&dma 2>; +- dma-names = "mmc"; +- status = "disabled"; +- }; +- +- mmc1: mmc@e0334000 { +- compatible = "actions,owl-mmc"; +- reg = <0x0 0xe0334000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cmu CLK_SD1>; +- resets = <&cmu RESET_SD1>; +- dmas = <&dma 3>; +- dma-names = "mmc"; +- status = "disabled"; +- }; +- +- mmc2: mmc@e0338000 { +- compatible = "actions,owl-mmc"; +- reg = <0x0 0xe0338000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cmu CLK_SD2>; +- resets = <&cmu RESET_SD2>; +- dmas = <&dma 4>; +- dma-names = "mmc"; +- status = "disabled"; +- }; +- +- mmc3: mmc@e033c000 { +- compatible = "actions,owl-mmc"; +- reg = <0x0 0xe033c000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cmu CLK_SD3>; +- resets = <&cmu RESET_SD3>; +- dmas = <&dma 46>; +- dma-names = "mmc"; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/Makefile b/scripts/dtc/include-prefixes/arm64/allwinner/Makefile +deleted file mode 100644 +index a96d9d2d8dd8..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/Makefile ++++ /dev/null +@@ -1,39 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-amarula-relic.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-oceanic-5205-5inmfd.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-emmc.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-lts.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.0.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.1.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.2.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab-early-adopter.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a100-allwinner-perf1.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-emlid-neutis-n5-devboard.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-cc.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-it.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h5-cc.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-beelink-gs1.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb +-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/axp803.dtsi b/scripts/dtc/include-prefixes/arm64/allwinner/axp803.dtsi +deleted file mode 100644 +index 10e9186a76bf..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/axp803.dtsi ++++ /dev/null +@@ -1,155 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright 2017 Icenowy Zheng +- +-/* +- * AXP803 Integrated Power Management Chip +- * http://files.pine64.org/doc/datasheet/pine64/AXP803_Datasheet_V1.0.pdf +- */ +- +-&axp803 { +- interrupt-controller; +- #interrupt-cells = <1>; +- +- ac_power_supply: ac-power-supply { +- compatible = "x-powers,axp803-ac-power-supply", +- "x-powers,axp813-ac-power-supply"; +- status = "disabled"; +- }; +- +- axp_adc: adc { +- compatible = "x-powers,axp803-adc", "x-powers,axp813-adc"; +- #io-channel-cells = <1>; +- }; +- +- axp_gpio: gpio { +- compatible = "x-powers,axp803-gpio", "x-powers,axp813-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- +- gpio0_ldo: gpio0-ldo { +- pins = "GPIO0"; +- function = "ldo"; +- }; +- +- gpio1_ldo: gpio1-ldo { +- pins = "GPIO1"; +- function = "ldo"; +- }; +- }; +- +- battery_power_supply: battery-power-supply { +- compatible = "x-powers,axp803-battery-power-supply", +- "x-powers,axp813-battery-power-supply"; +- status = "disabled"; +- }; +- +- regulators { +- /* Default work frequency for buck regulators */ +- x-powers,dcdc-freq = <3000>; +- +- reg_aldo1: aldo1 { +- regulator-name = "aldo1"; +- }; +- +- reg_aldo2: aldo2 { +- regulator-name = "aldo2"; +- }; +- +- reg_aldo3: aldo3 { +- regulator-name = "aldo3"; +- }; +- +- reg_dc1sw: dc1sw { +- regulator-name = "dc1sw"; +- }; +- +- reg_dcdc1: dcdc1 { +- regulator-name = "dcdc1"; +- }; +- +- reg_dcdc2: dcdc2 { +- regulator-name = "dcdc2"; +- }; +- +- reg_dcdc3: dcdc3 { +- regulator-name = "dcdc3"; +- }; +- +- reg_dcdc4: dcdc4 { +- regulator-name = "dcdc4"; +- }; +- +- reg_dcdc5: dcdc5 { +- regulator-name = "dcdc5"; +- }; +- +- reg_dcdc6: dcdc6 { +- regulator-name = "dcdc6"; +- }; +- +- reg_dldo1: dldo1 { +- regulator-name = "dldo1"; +- }; +- +- reg_dldo2: dldo2 { +- regulator-name = "dldo2"; +- }; +- +- reg_dldo3: dldo3 { +- regulator-name = "dldo3"; +- }; +- +- reg_dldo4: dldo4 { +- regulator-name = "dldo4"; +- }; +- +- reg_eldo1: eldo1 { +- regulator-name = "eldo1"; +- }; +- +- reg_eldo2: eldo2 { +- regulator-name = "eldo2"; +- }; +- +- reg_eldo3: eldo3 { +- regulator-name = "eldo3"; +- }; +- +- reg_fldo1: fldo1 { +- regulator-name = "fldo1"; +- }; +- +- reg_fldo2: fldo2 { +- regulator-name = "fldo2"; +- }; +- +- reg_ldo_io0: ldo-io0 { +- regulator-name = "ldo-io0"; +- status = "disabled"; +- }; +- +- reg_ldo_io1: ldo-io1 { +- regulator-name = "ldo-io1"; +- status = "disabled"; +- }; +- +- reg_rtc_ldo: rtc-ldo { +- /* RTC_LDO is a fixed, always-on regulator */ +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "rtc-ldo"; +- }; +- +- reg_drivevbus: drivevbus { +- regulator-name = "drivevbus"; +- status = "disabled"; +- }; +- }; +- +- usb_power_supply: usb-power-supply { +- compatible = "x-powers,axp803-usb-power-supply", +- "x-powers,axp813-usb-power-supply"; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a100-allwinner-perf1.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a100-allwinner-perf1.dts +deleted file mode 100644 +index d34c2bb1079f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a100-allwinner-perf1.dts ++++ /dev/null +@@ -1,180 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ or MIT) +-/* +- * Copyright (c) 2020 Yangtao Li +- */ +- +-/dts-v1/; +- +-#include "sun50i-a100.dtsi" +- +-/{ +- model = "Allwinner A100 Perf1"; +- compatible = "allwinner,a100-perf1", "allwinner,sun50i-a100"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&pio { +- vcc-pb-supply = <®_dcdc1>; +- vcc-pc-supply = <®_eldo1>; +- vcc-pd-supply = <®_dcdc1>; +- vcc-pe-supply = <®_dldo2>; +- vcc-pf-supply = <®_dcdc1>; +- vcc-pg-supply = <®_dldo1>; +- vcc-ph-supply = <®_dcdc1>; +-}; +- +-&r_pio { +- /* +- * FIXME: We can't add that supply for now since it would +- * create a circular dependency between pinctrl, the regulator +- * and the RSB Bus. +- * +- * vcc-pl-supply = <®_aldo3>; +- */ +-}; +- +-&r_i2c0 { +- status = "okay"; +- +- axp803: pmic@34 { +- compatible = "x-powers,axp803"; +- reg = <0x34>; +- interrupt-parent = <&r_intc>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ +- }; +-}; +- +-#include "axp803.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-®_aldo1 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-pll-avcc"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-dram-1"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-usb-pl"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-io-usb-pd-emmc-nand-card"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- /* +- * FIXME: update min and max before support dvfs. +- */ +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-cpux"; +-}; +- +-/* DCDC3 is polyphased with DCDC2 */ +- +-®_dcdc4 { +- regulator-always-on; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <950000>; +- regulator-name = "vdd-sys-usb-dram"; +-}; +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram-2"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pg-dcxo-wifi"; +-}; +- +-®_dldo2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "vcc-pe-csi"; +-}; +- +-®_dldo3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "ldo-avdd-csi"; +-}; +- +-®_dldo4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "avcc-csi"; +-}; +- +-®_eldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-pc-lvds-csi-efuse-emmc-nand"; +-}; +- +-®_eldo2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "dvdd-csi"; +-}; +- +-®_eldo3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-mipi-lcd"; +-}; +- +-®_fldo1 { +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-name = "vdd-cpus-usb"; +-}; +- +-®_ldo_io0 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-ctp"; +- status = "okay"; +-}; +- +-®_drivevbus { +- regulator-name = "usb0-vbus"; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a100.dtsi b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a100.dtsi +deleted file mode 100644 +index f6d7d7f7fdab..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a100.dtsi ++++ /dev/null +@@ -1,364 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ or MIT) +-/* +- * Copyright (c) 2020 Yangtao Li +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0>; +- enable-method = "psci"; +- }; +- +- cpu@1 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x1>; +- enable-method = "psci"; +- }; +- +- cpu@2 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x2>; +- enable-method = "psci"; +- }; +- +- cpu@3 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x3>; +- enable-method = "psci"; +- }; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- dcxo24M: dcxo24M-clk { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "dcxo24M"; +- #clock-cells = <0>; +- }; +- +- iosc: internal-osc-clk { +- compatible = "fixed-clock"; +- clock-frequency = <16000000>; +- clock-accuracy = <300000000>; +- clock-output-names = "iosc"; +- #clock-cells = <0>; +- }; +- +- osc32k: osc32k-clk { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-output-names = "osc32k"; +- #clock-cells = <0>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0 0x3fffffff>; +- +- ccu: clock@3001000 { +- compatible = "allwinner,sun50i-a100-ccu"; +- reg = <0x03001000 0x1000>; +- clocks = <&dcxo24M>, <&osc32k>, <&iosc>; +- clock-names = "hosc", "losc", "iosc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- gic: interrupt-controller@3021000 { +- compatible = "arm,gic-400"; +- reg = <0x03021000 0x1000>, <0x03022000 0x2000>, +- <0x03024000 0x2000>, <0x03026000 0x2000>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- +- efuse@3006000 { +- compatible = "allwinner,sun50i-a100-sid", +- "allwinner,sun50i-a64-sid"; +- reg = <0x03006000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ths_calibration: calib@14 { +- reg = <0x14 8>; +- }; +- }; +- +- pio: pinctrl@300b000 { +- compatible = "allwinner,sun50i-a100-pinctrl"; +- reg = <0x0300b000 0x400>; +- interrupts = , +- , +- , +- , +- , +- , +- ; +- clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>; +- clock-names = "apb", "hosc", "losc"; +- gpio-controller; +- #gpio-cells = <3>; +- interrupt-controller; +- #interrupt-cells = <3>; +- +- uart0_pb_pins: uart0-pb-pins { +- pins = "PB9", "PB10"; +- function = "uart0"; +- }; +- }; +- +- uart0: serial@5000000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x05000000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART0>; +- resets = <&ccu RST_BUS_UART0>; +- status = "disabled"; +- }; +- +- uart1: serial@5000400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x05000400 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART1>; +- resets = <&ccu RST_BUS_UART1>; +- status = "disabled"; +- }; +- +- uart2: serial@5000800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x05000800 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART2>; +- resets = <&ccu RST_BUS_UART2>; +- status = "disabled"; +- }; +- +- uart3: serial@5000c00 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x05000c00 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART3>; +- resets = <&ccu RST_BUS_UART3>; +- status = "disabled"; +- }; +- +- uart4: serial@5001000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x05001000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART4>; +- resets = <&ccu RST_BUS_UART4>; +- status = "disabled"; +- }; +- +- i2c0: i2c@5002000 { +- compatible = "allwinner,sun50i-a100-i2c", +- "allwinner,sun6i-a31-i2c"; +- reg = <0x05002000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C0>; +- resets = <&ccu RST_BUS_I2C0>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c1: i2c@5002400 { +- compatible = "allwinner,sun50i-a100-i2c", +- "allwinner,sun6i-a31-i2c"; +- reg = <0x05002400 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C1>; +- resets = <&ccu RST_BUS_I2C1>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c2: i2c@5002800 { +- compatible = "allwinner,sun50i-a100-i2c", +- "allwinner,sun6i-a31-i2c"; +- reg = <0x05002800 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C2>; +- resets = <&ccu RST_BUS_I2C2>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c3: i2c@5002c00 { +- compatible = "allwinner,sun50i-a100-i2c", +- "allwinner,sun6i-a31-i2c"; +- reg = <0x05002c00 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C3>; +- resets = <&ccu RST_BUS_I2C3>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- ths: thermal-sensor@5070400 { +- compatible = "allwinner,sun50i-a100-ths"; +- reg = <0x05070400 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_THS>; +- clock-names = "bus"; +- resets = <&ccu RST_BUS_THS>; +- nvmem-cells = <&ths_calibration>; +- nvmem-cell-names = "calibration"; +- #thermal-sensor-cells = <1>; +- }; +- +- r_ccu: clock@7010000 { +- compatible = "allwinner,sun50i-a100-r-ccu"; +- reg = <0x07010000 0x300>; +- clocks = <&dcxo24M>, <&osc32k>, <&iosc>, +- <&ccu CLK_PLL_PERIPH0>; +- clock-names = "hosc", "losc", "iosc", "pll-periph"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- r_intc: interrupt-controller@7010320 { +- compatible = "allwinner,sun50i-a100-nmi", +- "allwinner,sun9i-a80-nmi"; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x07010320 0xc>; +- interrupts = ; +- }; +- +- r_pio: pinctrl@7022000 { +- compatible = "allwinner,sun50i-a100-r-pinctrl"; +- reg = <0x07022000 0x400>; +- interrupts = ; +- clocks = <&r_ccu CLK_R_APB1>, <&dcxo24M>, <&osc32k>; +- clock-names = "apb", "hosc", "losc"; +- gpio-controller; +- #gpio-cells = <3>; +- interrupt-controller; +- #interrupt-cells = <3>; +- +- r_i2c0_pins: r-i2c0-pins { +- pins = "PL0", "PL1"; +- function = "s_i2c0"; +- }; +- +- r_i2c1_pins: r-i2c1-pins { +- pins = "PL8", "PL9"; +- function = "s_i2c1"; +- }; +- }; +- +- r_uart: serial@7080000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x07080000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&r_ccu CLK_R_APB2_UART>; +- resets = <&r_ccu RST_R_APB2_UART>; +- status = "disabled"; +- }; +- +- r_i2c0: i2c@7081400 { +- compatible = "allwinner,sun50i-a100-i2c", +- "allwinner,sun6i-a31-i2c"; +- reg = <0x07081400 0x400>; +- interrupts = ; +- clocks = <&r_ccu CLK_R_APB2_I2C0>; +- resets = <&r_ccu RST_R_APB2_I2C0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&r_i2c0_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- r_i2c1: i2c@7081800 { +- compatible = "allwinner,sun50i-a100-i2c", +- "allwinner,sun6i-a31-i2c"; +- reg = <0x07081800 0x400>; +- interrupts = ; +- clocks = <&r_ccu CLK_R_APB2_I2C1>; +- resets = <&r_ccu RST_R_APB2_I2C1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&r_i2c1_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- thermal-zones { +- cpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&ths 0>; +- }; +- +- ddr-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&ths 2>; +- }; +- +- gpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&ths 1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-amarula-relic.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-amarula-relic.dts +deleted file mode 100644 +index f17cc89f472d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-amarula-relic.dts ++++ /dev/null +@@ -1,320 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2018 Amarula Solutions B.V. +-// Author: Jagan Teki +- +-/dts-v1/; +- +-#include "sun50i-a64.dtsi" +-#include "sun50i-a64-cpu-opp.dtsi" +- +-#include +- +-/ { +- model = "Amarula A64-Relic"; +- compatible = "amarula,a64-relic", "allwinner,sun50i-a64"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- i2c { +- compatible = "i2c-gpio"; +- sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; +- i2c-gpio,delay-us = <5>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ov5640: camera@3c { +- compatible = "ovti,ov5640"; +- reg = <0x3c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&csi_mclk_pin>; +- clocks = <&ccu CLK_CSI_MCLK>; +- clock-names = "xclk"; +- +- AVDD-supply = <®_aldo1>; +- DOVDD-supply = <®_dldo3>; +- DVDD-supply = <®_eldo3>; +- reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* CSI-RST-R: PE14 */ +- powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* CSI-STBY-R: PE15 */ +- +- port { +- ov5640_ep: endpoint { +- remote-endpoint = <&csi_ep>; +- bus-width = <8>; +- hsync-active = <1>; /* Active high */ +- vsync-active = <0>; /* Active low */ +- data-active = <1>; /* Active high */ +- pclk-sample = <1>; /* Rising */ +- }; +- }; +- }; +- }; +- +- wifi_pwrseq: wifi-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&rtc 1>; +- clock-names = "ext_clock"; +- reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* WL-PMU-EN: PL2 */ +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu1 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu2 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu3 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&csi { +- status = "okay"; +- +- port { +- csi_ep: endpoint { +- remote-endpoint = <&ov5640_ep>; +- bus-width = <8>; +- hsync-active = <1>; /* Active high */ +- vsync-active = <0>; /* Active low */ +- data-active = <1>; /* Active high */ +- pclk-sample = <1>; /* Rising */ +- }; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- sensor@48 { +- compatible = "st,stlm75"; +- reg = <0x48>; +- }; +-}; +- +-&i2c0_pins { +- bias-pull-up; +-}; +- +-&i2c1 { +- status = "okay"; +- +- touchscreen@5d { +- compatible = "goodix,gt5663"; +- reg = <0x5d>; +- AVDD28-supply = <®_ldo_io0>; /* VCC-CTP: GPIO0-LDO */ +- interrupt-parent = <&pio>; +- interrupts = <7 4 IRQ_TYPE_EDGE_FALLING>; +- irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* CTP-INT: PH4 */ +- reset-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* CTP-RST: PH8 */ +- touchscreen-inverted-x; +- touchscreen-inverted-y; +- }; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <®_dcdc1>; +- /* +- * Schematic shows both dldo4 and eldo1 connected for vcc-io-wifi, but +- * dldo4 connection shows DNP(Do Not Populate) and eldo1 connected with +- * 0Ohm register to vcc-io-wifi so eldo1 is used. +- */ +- vqmmc-supply = <®_eldo1>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&r_pio>; +- interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* WL-WAKE-AP: PL3 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- vmmc-supply = <®_dcdc1>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp803: pmic@3a3 { +- compatible = "x-powers,axp803"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ +- }; +-}; +- +-#include "axp803.dtsi" +- +-®_aldo1 { +- regulator-always-on; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "avdd-csi"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pl"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-pll-avcc"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1040000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-cpux"; +-}; +- +-/* DCDC3 is polyphased with DCDC2 */ +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dcdc6 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-hdmi-dsi-sensor"; +-}; +- +-®_dldo2 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-mipi"; +-}; +- +-®_dldo3 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "dovdd-csi"; +-}; +- +-®_dldo4 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-io"; +-}; +- +-®_drivevbus { +- regulator-name = "usb0-vbus"; +- status = "okay"; +-}; +- +-®_eldo1 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "cpvdd"; +-}; +- +-®_eldo3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "dvdd-csi"; +-}; +- +-®_fldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-1v2-hsic"; +-}; +- +-/* +- * The A64 chip cannot work without this regulator off, although +- * it seems to be only driving the AR100 core. +- * Maybe we don't still know well about CPUs domain. +- */ +-®_fldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_ldo_io0 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "vcc-ctp"; +- status = "okay"; +-}; +- +-®_rtc_ldo { +- regulator-name = "vcc-rtc"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ +- usb0_vbus-supply = <®_drivevbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-bananapi-m64.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-bananapi-m64.dts +deleted file mode 100644 +index 997a19372683..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-bananapi-m64.dts ++++ /dev/null +@@ -1,382 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (c) 2016 ARM Ltd. +- +-/dts-v1/; +- +-#include "sun50i-a64.dtsi" +-#include "sun50i-a64-cpu-opp.dtsi" +- +-#include +- +-/ { +- model = "BananaPi-M64"; +- compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64"; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "bananapi-m64:red:pwr"; +- gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ +- default-state = "on"; +- }; +- +- led-1 { +- label = "bananapi-m64:green:user"; +- gpios = <&pio 4 14 GPIO_ACTIVE_HIGH>; /* PE14 */ +- }; +- +- led-2 { +- label = "bananapi-m64:blue:user"; +- gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */ +- }; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ +- clocks = <&rtc 1>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&codec_analog { +- cpvdd-supply = <®_eldo1>; +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu1 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu2 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu3 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&dai { +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- phy-mode = "rgmii-id"; +- phy-handle = <&ext_rgmii_phy>; +- phy-supply = <®_dc1sw>; +- status = "okay"; +-}; +- +-&hdmi { +- hvcc-supply = <®_dldo1>; +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c1_pins { +- bias-pull-up; +-}; +- +-&mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_dcdc1>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; +- disable-wp; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <®_dldo2>; +- vqmmc-supply = <®_dldo4>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&r_pio>; +- interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>; +- vmmc-supply = <®_dcdc1>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp803: pmic@3a3 { +- compatible = "x-powers,axp803"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ +- }; +-}; +- +-#include "axp803.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_aldo1 { +- /* +- * This regulator also drives the PE pingroup GPIOs, +- * which also controls two LEDs. +- */ +- regulator-always-on; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "afvcc-csi"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pl"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-pll-avcc"; +-}; +- +-®_dc1sw { +- /* +- * This regulator also indirectly drives the PD pingroup GPIOs, +- * which also controls the power LED. +- */ +- regulator-always-on; +- regulator-name = "vcc-phy"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1040000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-cpux"; +-}; +- +-/* DCDC3 is polyphased with DCDC2 */ +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dcdc6 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-hdmi-dsi"; +-}; +- +-®_dldo2 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-®_dldo4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-io"; +-}; +- +-®_drivevbus { +- regulator-name = "usb0-vbus"; +- status = "okay"; +-}; +- +-®_eldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "cpvdd"; +-}; +- +-®_fldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-1v2-hsic"; +-}; +- +-/* +- * The A64 chip cannot work without this regulator off, although +- * it seems to be only driving the AR100 core. +- * Maybe we don't still know well about CPUs domain. +- */ +-®_fldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_rtc_ldo { +- regulator-name = "vcc-rtc"; +-}; +- +-&simplefb_hdmi { +- vcc-hdmi-supply = <®_dldo1>; +-}; +- +-&sound { +- status = "okay"; +- simple-audio-card,widgets = "Headphone", "Headphone Jack", +- "Microphone", "Microphone Jack", +- "Microphone", "Onboard Microphone"; +- simple-audio-card,routing = +- "Left DAC", "DACL", +- "Right DAC", "DACR", +- "ADCL", "Left ADC", +- "ADCR", "Right ADC", +- "Headphone Jack", "HP", +- "MIC2", "Microphone Jack", +- "Onboard Microphone", "MBIAS", +- "MIC1", "Onboard Microphone"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&rtc 1>; +- clock-names = "lpo"; +- vbat-supply = <®_dldo2>; +- vddio-supply = <®_dldo4>; +- device-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ +- host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ +- shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ +- }; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_drivevbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-cpu-opp.dtsi b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-cpu-opp.dtsi +deleted file mode 100644 +index e39db51eb448..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-cpu-opp.dtsi ++++ /dev/null +@@ -1,75 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2020 Vasily khoruzhick +- */ +- +-/ { +- cpu0_opp_table: opp-table-cpu { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-648000000 { +- opp-hz = /bits/ 64 <648000000>; +- opp-microvolt = <1040000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-816000000 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <1100000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-912000000 { +- opp-hz = /bits/ 64 <912000000>; +- opp-microvolt = <1120000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-960000000 { +- opp-hz = /bits/ 64 <960000000>; +- opp-microvolt = <1160000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-1008000000 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <1200000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-1056000000 { +- opp-hz = /bits/ 64 <1056000000>; +- opp-microvolt = <1240000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-1104000000 { +- opp-hz = /bits/ 64 <1104000000>; +- opp-microvolt = <1260000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-1152000000 { +- opp-hz = /bits/ 64 <1152000000>; +- opp-microvolt = <1300000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- }; +-}; +- +-&cpu0 { +- operating-points-v2 = <&cpu0_opp_table>; +-}; +- +-&cpu1 { +- operating-points-v2 = <&cpu0_opp_table>; +-}; +- +-&cpu2 { +- operating-points-v2 = <&cpu0_opp_table>; +-}; +- +-&cpu3 { +- operating-points-v2 = <&cpu0_opp_table>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-nanopi-a64.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-nanopi-a64.dts +deleted file mode 100644 +index e47ff06a6fa9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-nanopi-a64.dts ++++ /dev/null +@@ -1,263 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2017 Jagan Teki +- +-/dts-v1/; +- +-#include "sun50i-a64.dtsi" +-#include "sun50i-a64-cpu-opp.dtsi" +- +-#include +- +-/ { +- model = "FriendlyARM NanoPi A64"; +- compatible = "friendlyarm,nanopi-a64", "allwinner,sun50i-a64"; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led { +- label = "nanopi-a64:blue:status"; +- gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ +- }; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&rtc 1>; +- clock-names = "ext_clock"; +- reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu1 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu2 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu3 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- phy-mode = "rgmii"; +- phy-handle = <&ext_rgmii_phy>; +- phy-supply = <®_dcdc1>; +- status = "okay"; +-}; +- +-&hdmi { +- hvcc-supply = <®_dldo1>; +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-/* i2c1 connected with gpio headers like pine64, bananapi */ +-&i2c1_pins { +- bias-pull-up; +-}; +- +-&mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <7>; +- }; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_dcdc1>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; +- disable-wp; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_dldo4>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- rtl8189etv: wifi@1 { +- reg = <1>; +- interrupt-parent = <&r_pio>; +- interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp803: pmic@3a3 { +- compatible = "x-powers,axp803"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- }; +-}; +- +-#include "axp803.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pl"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-pll-avcc"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1040000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-cpux"; +-}; +- +-/* DCDC3 is polyphased with DCDC2 */ +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dcdc6 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dldo1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-hdmi-dsi"; +-}; +- +-®_dldo4 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-pg-wifi-io"; +-}; +- +-®_eldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "cpvdd"; +-}; +- +-®_fldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-1v2-hsic"; +-}; +- +-/* +- * The A64 chip cannot work without this regulator off, although +- * it seems to be only driving the AR100 core. +- * Maybe we don't still know well about CPUs domain. +- */ +-®_fldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_rtc_ldo { +- regulator-name = "vcc-rtc"; +-}; +- +-&simplefb_hdmi { +- vcc-hdmi-supply = <®_dldo1>; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts +deleted file mode 100644 +index 577f9e1d08a1..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts ++++ /dev/null +@@ -1,89 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2019 Oceanic Systems (UK) Ltd. +-// Copyright (C) 2019 Amarula Solutions B.V. +-// Author: Jagan Teki +- +-/dts-v1/; +- +-#include "sun50i-a64-sopine.dtsi" +- +-/ { +- model = "Oceanic 5205 5inMFD"; +- compatible = "oceanic,5205-5inmfd", "allwinner,sun50i-a64"; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- phy-mode = "rgmii"; +- phy-handle = <&ext_rgmii_phy>; +- phy-supply = <®_dc1sw>; +- allwinner,tx-delay-ps = <600>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- touchscreen@5d { +- compatible = "goodix,gt911"; +- reg = <0x5d>; +- AVDD28-supply = <®_ldo_io0>; /* VDD_CTP: GPIO0-LDO */ +- interrupt-parent = <&pio>; +- interrupts = <7 4 IRQ_TYPE_EDGE_FALLING>; +- irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* CTP-INT: PH4 */ +- reset-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* CTP-RST: PH11 */ +- touchscreen-inverted-x; +- touchscreen-inverted-y; +- }; +-}; +- +-&mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-®_dc1sw { +- regulator-name = "vcc-phy"; +-}; +- +-®_ldo_io0 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "vdd-ctp"; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-olinuxino-emmc.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-olinuxino-emmc.dts +deleted file mode 100644 +index efb20846de49..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-olinuxino-emmc.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2018 Martin Ayotte +-// Copyright (C) 2019 Sunil Mohan Adapa +- +-#include "sun50i-a64-olinuxino.dts" +- +-/ { +- model = "Olimex A64-Olinuxino-eMMC"; +- compatible = "olimex,a64-olinuxino-emmc", "allwinner,sun50i-a64"; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_eldo1>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&pio { +- vcc-pc-supply = <®_eldo1>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-olinuxino.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-olinuxino.dts +deleted file mode 100644 +index ec7e2c0e82c1..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-olinuxino.dts ++++ /dev/null +@@ -1,347 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2017 Jagan Teki +- +-/dts-v1/; +- +-#include "sun50i-a64.dtsi" +-#include "sun50i-a64-cpu-opp.dtsi" +- +-#include +- +-/ { +- model = "Olimex A64-Olinuxino"; +- compatible = "olimex,a64-olinuxino", "allwinner,sun50i-a64"; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "a64-olinuxino:red:user"; +- gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ +- }; +- }; +- +- reg_usb1_vbus: usb1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb1-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- enable-active-high; +- gpio = <&pio 6 9 GPIO_ACTIVE_HIGH>; /* PG9 */ +- status = "okay"; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu1 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu2 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu3 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- phy-mode = "rgmii"; +- phy-handle = <&ext_rgmii_phy>; +- phy-supply = <®_dcdc1>; +- allwinner,tx-delay-ps = <600>; +- status = "okay"; +-}; +- +-&hdmi { +- hvcc-supply = <®_dldo1>; +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_dcdc1>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; +- disable-wp; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_dldo4>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- rtl8723bs: wifi@1 { +- reg = <1>; +- interrupt-parent = <&r_pio>; +- interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&pio { +- vcc-pc-supply = <®_dcdc1>; +- vcc-pd-supply = <®_dcdc1>; +- vcc-pe-supply = <®_aldo1>; +- vcc-pg-supply = <®_dldo4>; +-}; +- +-&r_pio { +- /* +- * FIXME: We can't add that supply for now since it would +- * create a circular dependency between pinctrl, the regulator +- * and the RSB Bus. +- * +- * vcc-pl-supply = <®_aldo2>; +- */ +-}; +- +-&pio { +- vcc-pa-supply = <®_dcdc1>; +- vcc-pb-supply = <®_dcdc1>; +- vcc-pc-supply = <®_dcdc1>; +- vcc-pd-supply = <®_dcdc1>; +- vcc-pe-supply = <®_aldo1>; +- vcc-pf-supply = <®_dcdc1>; +- vcc-pg-supply = <®_dldo4>; +- vcc-ph-supply = <®_dcdc1>; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp803: pmic@3a3 { +- compatible = "x-powers,axp803"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ +- }; +-}; +- +-/* VCC-PL is powered by aldo2 but we cannot add it as the RSB */ +-/* interface used to talk to the PMIC in on the PL pins */ +-/* &r_pio { */ +-/* vcc-pl-supply = <®_aldo2>; */ +-/* }; */ +- +-#include "axp803.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_aldo1 { +- regulator-always-on; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "vcc-pe"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pl"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-pll-avcc"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1040000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-cpux"; +-}; +- +-/* DCDC3 is polyphased with DCDC2 */ +- +-/* +- * The board uses DDR3L DRAM chips. 1.36V is the closest to the nominal +- * 1.35V that the PMIC can drive. +- */ +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1360000>; +- regulator-max-microvolt = <1360000>; +- regulator-name = "vcc-ddr3"; +-}; +- +-®_dcdc6 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-hdmi"; +-}; +- +-®_dldo2 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-mipi"; +-}; +- +-®_dldo3 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "vcc-avdd-csi"; +-}; +- +-®_dldo4 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-io"; +-}; +- +-®_drivevbus { +- regulator-name = "usb0-vbus"; +- status = "okay"; +-}; +- +-®_eldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "cpvdd"; +-}; +- +-®_eldo2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-dvdd-csi"; +-}; +- +-®_fldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-1v2-hsic"; +-}; +- +-/* +- * The A64 chip cannot work without this regulator off, although +- * it seems to be only driving the AR100 core. +- * Maybe we don't still know well about CPUs domain. +- */ +-®_fldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_rtc_ldo { +- regulator-name = "vcc-rtc"; +-}; +- +-&simplefb_hdmi { +- vcc-hdmi-supply = <®_dldo1>; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +- usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ +- usb0_vbus-supply = <®_drivevbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-orangepi-win.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-orangepi-win.dts +deleted file mode 100644 +index 097a5511523a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-orangepi-win.dts ++++ /dev/null +@@ -1,413 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2017 Jagan Teki +-// Copyright (C) 2017-2018 Samuel Holland +- +-/dts-v1/; +- +-#include "sun50i-a64.dtsi" +-#include "sun50i-a64-cpu-opp.dtsi" +- +-#include +- +-/ { +- model = "OrangePi Win/Win Plus"; +- compatible = "xunlong,orangepi-win", "allwinner,sun50i-a64"; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- status { +- label = "orangepi:green:status"; +- gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ +- }; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- enable-active-high; +- gpio = <&pio 3 14 GPIO_ACTIVE_HIGH>; /* PD14 */ +- status = "okay"; +- }; +- +- reg_usb1_vbus: usb1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb1-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- enable-active-high; +- gpio = <&pio 3 7 GPIO_ACTIVE_HIGH>; /* PD7 */ +- status = "okay"; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ +- clocks = <&rtc 1>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&codec_analog { +- cpvdd-supply = <®_eldo1>; +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu1 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu2 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu3 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&dai { +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- phy-mode = "rgmii-id"; +- phy-handle = <&ext_rgmii_phy>; +- phy-supply = <®_gmac_3v3>; +- status = "okay"; +-}; +- +-&hdmi { +- hvcc-supply = <®_dldo1>; +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_dcdc1>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- disable-wp; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <®_dldo2>; +- vqmmc-supply = <®_dldo4>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&r_pio>; +- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&r_ir { +- status = "okay"; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp803: pmic@3a3 { +- compatible = "x-powers,axp803"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ +- }; +-}; +- +-#include "axp803.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_aldo1 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "afvcc-csi"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pl"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-pll-avcc"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1040000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-cpux"; +-}; +- +-/* DCDC3 is polyphased with DCDC2 */ +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dcdc6 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-hdmi-dsi"; +-}; +- +-®_dldo2 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-®_dldo3 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "avdd-csi"; +-}; +- +-®_dldo4 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-io"; +-}; +- +-®_drivevbus { +- regulator-name = "usb0-vbus"; +- status = "okay"; +-}; +- +-®_eldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "cpvdd"; +-}; +- +-®_eldo3 { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "dvdd-csi"; +-}; +- +-®_fldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-1v2-hsic"; +-}; +- +-/* +- * The A64 chip cannot work without this regulator off, although +- * it seems to be only driving the AR100 core. +- * Maybe we don't still know well about CPUs domain. +- */ +-®_fldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_rtc_ldo { +- regulator-name = "vcc-rtc"; +-}; +- +-&simplefb_hdmi { +- vcc-hdmi-supply = <®_dldo1>; +-}; +- +-&sound { +- status = "okay"; +- simple-audio-card,widgets = "Headphone", "Headphone Jack", +- "Microphone", "Microphone Jack", +- "Microphone", "Onboard Microphone"; +- simple-audio-card,routing = +- "Left DAC", "DACL", +- "Right DAC", "DACR", +- "ADCL", "Left ADC", +- "ADCR", "Right ADC", +- "Headphone Jack", "HP", +- "MIC2", "Microphone Jack", +- "Onboard Microphone", "MBIAS", +- "MIC1", "Onboard Microphone"; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- compatible = "mxicy,mx25l1606e", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <80000000>; +- m25p,fast-read; +- status = "okay"; +- }; +-}; +- +-/* On debug connector */ +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-/* Bluetooth */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- max-speed = <1500000>; +- clocks = <&rtc 1>; +- clock-names = "lpo"; +- vbat-supply = <®_dldo2>; +- vddio-supply = <®_dldo4>; +- device-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ +- host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ +- shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ +- }; +-}; +- +-/* On Pi-2 connector, RTS/CTS optional */ +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "disabled"; +-}; +- +-/* On Pi-2 connector, RTS/CTS optional */ +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- status = "disabled"; +-}; +- +-/* On Pi-2 connector (labeled for SPI1), RTS/CTS optional */ +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pins>; +- status = "disabled"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ +- usb0_vbus-supply = <®_drivevbus>; +- usb1_vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pine64-lts.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pine64-lts.dts +deleted file mode 100644 +index 596a25907432..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pine64-lts.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (c) 2018 ARM Ltd. +- +-#include +-#include "sun50i-a64-sopine-baseboard.dts" +- +-/ { +- model = "Pine64 LTS"; +- compatible = "pine64,pine64-lts", "allwinner,sun50i-r18", +- "allwinner,sun50i-a64"; +- +- leds { +- compatible = "gpio-leds"; +- +- led { +- function = LED_FUNCTION_STATUS; +- color = ; +- gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ +- }; +- }; +-}; +- +-&mmc0 { +- broken-cd; /* card detect is broken on *some* boards */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pine64-plus.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pine64-plus.dts +deleted file mode 100644 +index b54099b654c8..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pine64-plus.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (c) 2016 ARM Ltd. +- +-#include "sun50i-a64-pine64.dts" +- +-/ { +- model = "Pine64+"; +- compatible = "pine64,pine64-plus", "allwinner,sun50i-a64"; +- +- /* TODO: Camera, touchscreen, etc. */ +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- phy-mode = "rgmii-txid"; +- phy-handle = <&ext_rgmii_phy>; +- status = "okay"; +-}; +- +-&mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-®_dc1sw { +- /* +- * Ethernet PHY needs 30ms to properly power up and some more +- * to initialize. 100ms should be plenty of time to finish +- * whole process. +- */ +- regulator-enable-ramp-delay = <100000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pine64.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pine64.dts +deleted file mode 100644 +index 2accb5ddf783..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pine64.dts ++++ /dev/null +@@ -1,320 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (c) 2016 ARM Ltd. +- +-/dts-v1/; +- +-#include "sun50i-a64.dtsi" +-#include "sun50i-a64-cpu-opp.dtsi" +- +-#include +- +-/ { +- model = "Pine64"; +- compatible = "pine64,pine64", "allwinner,sun50i-a64"; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&codec_analog { +- cpvdd-supply = <®_eldo1>; +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu1 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu2 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu3 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&dai { +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&rmii_pins>; +- phy-mode = "rmii"; +- phy-handle = <&ext_rmii_phy1>; +- phy-supply = <®_dc1sw>; +- status = "okay"; +- +-}; +- +-&hdmi { +- hvcc-supply = <®_dldo1>; +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c1_pins { +- bias-pull-up; +-}; +- +-&mdio { +- ext_rmii_phy1: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_dcdc1>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; +- disable-wp; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp803: pmic@3a3 { +- compatible = "x-powers,axp803"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- }; +-}; +- +-#include "axp803.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pl"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-pll-avcc"; +-}; +- +-®_dc1sw { +- regulator-name = "vcc-phy"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1040000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-cpux"; +-}; +- +-/* DCDC3 is polyphased with DCDC2 */ +- +-/* +- * The DRAM chips used by Pine64 boards are DDR3L-compatible, so they can +- * work at 1.35V with less power consumption. +- * As AXP803 DCDC5 cannot reach 1.35V accurately, use 1.36V instead. +- */ +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1360000>; +- regulator-max-microvolt = <1360000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dcdc6 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-hdmi"; +-}; +- +-®_dldo2 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-mipi"; +-}; +- +-®_dldo4 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-®_eldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "cpvdd"; +-}; +- +-®_fldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-1v2-hsic"; +-}; +- +-/* +- * The A64 chip cannot work without this regulator off, although +- * it seems to be only driving the AR100 core. +- * Maybe we don't still know well about CPUs domain. +- */ +-®_fldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_rtc_ldo { +- regulator-name = "vcc-rtc"; +-}; +- +-&simplefb_hdmi { +- vcc-hdmi-supply = <®_dldo1>; +-}; +- +-&sound { +- simple-audio-card,aux-devs = <&codec_analog>; +- simple-audio-card,widgets = "Microphone", "Microphone Jack", +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "Left DAC", "DACL", +- "Right DAC", "DACR", +- "Headphone Jack", "HP", +- "ADCL", "Left ADC", +- "ADCR", "Right ADC", +- "MIC2", "Microphone Jack"; +- status = "okay"; +-}; +- +-/* On Euler connector */ +-&spdif { +- status = "disabled"; +-}; +- +-/* On Exp and Euler connectors */ +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-/* On Wifi/BT connector, with RTS/CTS */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; +- status = "disabled"; +-}; +- +-/* On Pi-2 connector */ +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "disabled"; +-}; +- +-/* On Euler connector */ +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- status = "disabled"; +-}; +- +-/* On Euler connector, RTS/CTS optional */ +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pins>; +- status = "disabled"; +-}; +- +-&usb_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinebook.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinebook.dts +deleted file mode 100644 +index 34e67f5f8297..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinebook.dts ++++ /dev/null +@@ -1,416 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2017 Icenowy Zheng +-// Copyright (C) 2018 Vasily Khoruzhick +- +-/dts-v1/; +- +-#include "sun50i-a64.dtsi" +-#include "sun50i-a64-cpu-opp.dtsi" +- +-#include +-#include +-#include +-#include +- +-/ { +- model = "Pinebook"; +- compatible = "pine64,pinebook", "allwinner,sun50i-a64"; +- +- aliases { +- serial0 = &uart0; +- ethernet0 = &rtl8723cs; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 50000 0>; +- brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>; +- default-brightness-level = <2>; +- enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ +- power-supply = <®_vbklt>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- lid_switch { +- label = "Lid Switch"; +- gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */ +- linux,input-type = ; +- linux,code = ; +- linux,can-disable; +- wakeup-source; +- wakeup-event-action = ; +- }; +- }; +- +- panel_edp: panel-edp { +- compatible = "neweast,wjfh116008a"; +- backlight = <&backlight>; +- power-supply = <®_dc1sw>; +- +- port { +- panel_edp_in: endpoint { +- remote-endpoint = <&anx6345_out_edp>; +- }; +- }; +- }; +- +- reg_vbklt: vbklt { +- compatible = "regulator-fixed"; +- regulator-name = "vbklt"; +- regulator-min-microvolt = <18000000>; +- regulator-max-microvolt = <18000000>; +- gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ +- enable-active-high; +- }; +- +- reg_vcc5v0: vcc5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ +- }; +- +- speaker_amp: audio-amplifier { +- compatible = "simple-audio-amplifier"; +- VCC-supply = <®_vcc5v0>; +- enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ +- sound-name-prefix = "Speaker Amp"; +- }; +- +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&codec_analog { +- cpvdd-supply = <®_eldo1>; +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu1 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu2 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu3 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&dai { +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&mixer0 { +- status = "okay"; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_dcdc1>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- disable-wp; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <®_dldo4>; +- vqmmc-supply = <®_eldo1>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- rtl8723cs: wifi@1 { +- reg = <1>; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>; +- vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_eldo1>; +- max-frequency = <200000000>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- mmc-hs200-1_8v; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&pio { +- vcc-pc-supply = <®_eldo1>; +- vcc-pd-supply = <®_dcdc1>; +- vcc-pe-supply = <®_aldo1>; +- vcc-pg-supply = <®_eldo1>; +-}; +- +-&pwm { +- status = "okay"; +-}; +- +-&r_i2c { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&r_i2c_pl89_pins>; +- status = "okay"; +- +- anx6345: anx6345@38 { +- compatible = "analogix,anx6345"; +- reg = <0x38>; +- reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ +- dvdd25-supply = <®_dldo2>; +- dvdd12-supply = <®_fldo1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- anx6345_in: port@0 { +- reg = <0>; +- anx6345_in_tcon0: endpoint { +- remote-endpoint = <&tcon0_out_anx6345>; +- }; +- }; +- +- anx6345_out: port@1 { +- reg = <1>; +- anx6345_out_edp: endpoint { +- remote-endpoint = <&panel_edp_in>; +- }; +- }; +- }; +- }; +-}; +- +-&r_pio { +- /* +- * FIXME: We can't add that supply for now since it would +- * create a circular dependency between pinctrl, the regulator +- * and the RSB Bus. +- * +- * vcc-pl-supply = <®_aldo2>; +- */ +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp803: pmic@3a3 { +- compatible = "x-powers,axp803"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- }; +-}; +- +-#include "axp803.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_aldo1 { +- regulator-name = "vcc-pe"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pl"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pll-avcc"; +-}; +- +-®_dc1sw { +- regulator-name = "vcc-lcd"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-cpux"; +-}; +- +-/* DCDC3 is polyphased with DCDC2 */ +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dcdc6 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-hdmi"; +-}; +- +-®_dldo2 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-name = "vcc-edp"; +-}; +- +-®_dldo4 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-®_eldo1 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "cpvdd"; +-}; +- +-®_fldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-1v2-hsic"; +-}; +- +-®_fldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_rtc_ldo { +- regulator-name = "vcc-rtc"; +-}; +- +-&simplefb_lcd { +- panel-supply = <®_dc1sw>; +- dvdd25-supply = <®_dldo2>; +- dvdd12-supply = <®_fldo1>; +-}; +- +-&simplefb_hdmi { +- vcc-hdmi-supply = <®_dldo1>; +-}; +- +-&sound { +- status = "okay"; +- simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; +- simple-audio-card,widgets = "Microphone", "Internal Microphone Left", +- "Microphone", "Internal Microphone Right", +- "Headphone", "Headphone Jack", +- "Speaker", "Internal Speaker"; +- simple-audio-card,routing = +- "Left DAC", "DACL", +- "Right DAC", "DACR", +- "Speaker Amp INL", "LINEOUT", +- "Speaker Amp INR", "LINEOUT", +- "Internal Speaker", "Speaker Amp OUTL", +- "Internal Speaker", "Speaker Amp OUTR", +- "Headphone Jack", "HP", +- "ADCL", "Left ADC", +- "ADCR", "Right ADC", +- "Internal Microphone Left", "MBIAS", +- "MIC1", "Internal Microphone Left", +- "Internal Microphone Right", "HBIAS", +- "MIC2", "Internal Microphone Right"; +-}; +- +-&tcon0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_rgb666_pins>; +- +- status = "okay"; +-}; +- +-&tcon0_out { +- tcon0_out_anx6345: endpoint { +- remote-endpoint = <&anx6345_in_tcon0>; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "host"; +-}; +- +-&usbphy { +- usb0_vbus-supply = <®_vcc5v0>; +- usb1_vbus-supply = <®_vcc5v0>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinephone-1.0.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinephone-1.0.dts +deleted file mode 100644 +index fb65319a3bd3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinephone-1.0.dts ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2020 Ondrej Jirman +- +-/dts-v1/; +- +-#include "sun50i-a64-pinephone.dtsi" +- +-/ { +- model = "Pine64 PinePhone Developer Batch (1.0)"; +- compatible = "pine64,pinephone-1.0", "pine64,pinephone", "allwinner,sun50i-a64"; +-}; +- +-&sgm3140 { +- enable-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */ +- flash-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinephone-1.1.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinephone-1.1.dts +deleted file mode 100644 +index 5e59d3752178..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinephone-1.1.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2020 Ondrej Jirman +- +-/dts-v1/; +- +-#include "sun50i-a64-pinephone.dtsi" +- +-/ { +- model = "Pine64 PinePhone Braveheart (1.1)"; +- compatible = "pine64,pinephone-1.1", "pine64,pinephone", "allwinner,sun50i-a64"; +-}; +- +-&backlight { +- power-supply = <®_ldo_io0>; +- /* +- * PWM backlight circuit on this PinePhone revision was changed since +- * 1.0, and the lowest PWM duty cycle that doesn't lead to backlight +- * being off is around 20%. Duty cycle for the lowest brightness level +- * also varries quite a bit between individual boards, so the lowest +- * value here was chosen as a safe default. +- */ +- brightness-levels = < +- 774 793 814 842 +- 882 935 1003 1088 +- 1192 1316 1462 1633 +- 1830 2054 2309 2596 +- 2916 3271 3664 4096>; +- num-interpolated-steps = <50>; +- default-brightness-level = <400>; +-}; +- +-&sgm3140 { +- enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ +- flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinephone-1.2.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinephone-1.2.dts +deleted file mode 100644 +index 4e7e237cb46a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinephone-1.2.dts ++++ /dev/null +@@ -1,54 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2020 Ondrej Jirman +- +-/dts-v1/; +- +-#include "sun50i-a64-pinephone.dtsi" +- +-/ { +- model = "Pine64 PinePhone (1.2)"; +- compatible = "pine64,pinephone-1.2", "pine64,pinephone", "allwinner,sun50i-a64"; +- +- wifi_pwrseq: wifi-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ +- }; +-}; +- +-&backlight { +- power-supply = <®_ldo_io0>; +- /* +- * PWM backlight circuit on this PinePhone revision was changed since 1.0, +- * and the lowest PWM duty cycle that doesn't lead to backlight being off +- * is around 10%. Duty cycle for the lowest brightness level also varries +- * quite a bit between individual boards, so the lowest value here was +- * chosen as a safe default. +- */ +- brightness-levels = < +- 5000 5248 5506 5858 6345 +- 6987 7805 8823 10062 11543 +- 13287 15317 17654 20319 23336 +- 26724 30505 34702 39335 44427 +- 50000 +- >; +- num-interpolated-steps = <50>; +- default-brightness-level = <500>; +-}; +- +-&lis3mdl { +- /* +- * Board revision 1.2 fixed routing of the interrupt to DRDY pin, +- * enable interrupts. +- */ +- interrupt-parent = <&pio>; +- interrupts = <1 1 IRQ_TYPE_EDGE_RISING>; /* PB1 */ +-}; +- +-&mmc1 { +- mmc-pwrseq = <&wifi_pwrseq>; +-}; +- +-&sgm3140 { +- enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ +- flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinephone.dtsi b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinephone.dtsi +deleted file mode 100644 +index 5b44a979f250..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinephone.dtsi ++++ /dev/null +@@ -1,514 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2019 Icenowy Zheng +-// Copyright (C) 2020 Martijn Braam +-// Copyright (C) 2020 Ondrej Jirman +- +-#include "sun50i-a64.dtsi" +-#include "sun50i-a64-cpu-opp.dtsi" +- +-#include +-#include +-#include +-#include +- +-/ { +- aliases { +- ethernet0 = &rtl8723cs; +- serial0 = &uart0; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&r_pwm 0 50000 PWM_POLARITY_INVERTED>; +- enable-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ +- power-supply = <®_ps>; +- /* Backlight configuration differs per PinePhone revision. */ +- }; +- +- bt_sco_codec: bt-sco-codec { +- #sound-dai-cells = <1>; +- compatible = "linux,bt-sco"; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- function = LED_FUNCTION_INDICATOR; +- color = ; +- gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ +- }; +- +- led-1 { +- function = LED_FUNCTION_INDICATOR; +- color = ; +- gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */ +- }; +- +- led-2 { +- function = LED_FUNCTION_INDICATOR; +- color = ; +- gpios = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ +- }; +- }; +- +- reg_ps: ps-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "ps"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- }; +- +- reg_vbat_wifi: vbat-wifi { +- compatible = "regulator-fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vbat-wifi"; +- }; +- +- sgm3140: led-controller { +- compatible = "sgmicro,sgm3140"; +- vin-supply = <®_dcdc1>; +- +- sgm3140_flash: led { +- function = LED_FUNCTION_FLASH; +- color = ; +- flash-max-timeout-us = <250000>; +- }; +- }; +- +- speaker_amp: audio-amplifier { +- compatible = "simple-audio-amplifier"; +- enable-gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */ +- sound-name-prefix = "Speaker Amp"; +- }; +- +- vibrator { +- compatible = "gpio-vibrator"; +- enable-gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */ +- vcc-supply = <®_dcdc1>; +- }; +-}; +- +-&codec { +- pinctrl-names = "default"; +- pinctrl-0 = <&aif3_pins>; +- status = "okay"; +-}; +- +-&codec_analog { +- cpvdd-supply = <®_eldo1>; +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu1 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu2 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu3 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&dai { +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&dphy { +- status = "okay"; +-}; +- +-&dsi { +- vcc-dsi-supply = <®_dldo1>; +- status = "okay"; +- +- panel@0 { +- compatible = "xingbangda,xbd599"; +- reg = <0>; +- reset-gpios = <&pio 3 23 GPIO_ACTIVE_LOW>; /* PD23 */ +- iovcc-supply = <®_dldo2>; +- vcc-supply = <®_ldo_io0>; +- backlight = <&backlight>; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- touchscreen@5d { +- compatible = "goodix,gt917s"; +- reg = <0x5d>; +- interrupt-parent = <&pio>; +- interrupts = <7 4 IRQ_TYPE_LEVEL_HIGH>; /* PH4 */ +- irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ +- reset-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ +- AVDD28-supply = <®_ldo_io0>; +- VDDIO-supply = <®_ldo_io0>; +- touchscreen-size-x = <720>; +- touchscreen-size-y = <1440>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- /* Magnetometer */ +- lis3mdl: magnetometer@1e { +- compatible = "st,lis3mdl-magn"; +- reg = <0x1e>; +- vdd-supply = <®_dldo1>; +- vddio-supply = <®_dldo1>; +- }; +- +- /* Light/proximity sensor */ +- light-sensor@48 { +- compatible = "sensortek,stk3311"; +- reg = <0x48>; +- interrupt-parent = <&pio>; +- interrupts = <1 0 IRQ_TYPE_EDGE_FALLING>; /* PB0 */ +- }; +- +- /* Accelerometer/gyroscope */ +- accelerometer@68 { +- compatible = "invensense,mpu6050"; +- reg = <0x68>; +- interrupt-parent = <&pio>; +- interrupts = <7 5 IRQ_TYPE_EDGE_RISING>; /* PH5 */ +- vdd-supply = <®_dldo1>; +- vddio-supply = <®_dldo1>; +- }; +-}; +- +-/* Connected to pogo pins (external spring based pinheader for user addons) */ +-&i2c2 { +- status = "okay"; +-}; +- +-&lradc { +- vref-supply = <®_aldo3>; +- wakeup-source; +- status = "okay"; +- +- button-200 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <200000>; +- }; +- +- button-400 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <400000>; +- }; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_dcdc1>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- disable-wp; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <®_vbat_wifi>; +- vqmmc-supply = <®_dldo4>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- rtl8723cs: wifi@1 { +- reg = <1>; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_dcdc1>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&pio { +- vcc-pb-supply = <®_dcdc1>; +- vcc-pc-supply = <®_dcdc1>; +- vcc-pd-supply = <®_dcdc1>; +- vcc-pe-supply = <®_aldo1>; +- vcc-pf-supply = <®_dcdc1>; +- vcc-pg-supply = <®_dldo4>; +- vcc-ph-supply = <®_dcdc1>; +-}; +- +-&r_pio { +- /* +- * FIXME: We can't add that supply for now since it would +- * create a circular dependency between pinctrl, the regulator +- * and the RSB Bus. +- * +- * vcc-pl-supply = <®_aldo2>; +- */ +-}; +- +-&r_pwm { +- status = "okay"; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp803: pmic@3a3 { +- compatible = "x-powers,axp803"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- }; +-}; +- +-#include "axp803.dtsi" +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_aldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "dovdd-csi"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-pl"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-pll-avcc"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-cpux"; +-}; +- +-/* DCDC3 is polyphased with DCDC2 */ +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dcdc6 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-dsi-sensor"; +-}; +- +-®_dldo2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-mipi-io"; +-}; +- +-®_dldo3 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "avdd-csi"; +-}; +- +-®_dldo4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-wifi-io"; +-}; +- +-®_eldo1 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-lpddr"; +-}; +- +-®_eldo3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "dvdd-1v8-csi"; +-}; +- +-®_fldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-1v2-hsic"; +-}; +- +-®_fldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_ldo_io0 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-lcd-ctp-stk"; +- status = "okay"; +-}; +- +-®_ldo_io1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-1v8-typec"; +- status = "okay"; +-}; +- +-®_rtc_ldo { +- regulator-name = "vcc-rtc"; +-}; +- +-&sound { +- status = "okay"; +- simple-audio-card,name = "PinePhone"; +- simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; +- simple-audio-card,widgets = "Microphone", "Headset Microphone", +- "Microphone", "Internal Microphone", +- "Headphone", "Headphone Jack", +- "Speaker", "Internal Earpiece", +- "Speaker", "Internal Speaker"; +- simple-audio-card,routing = +- "Headphone Jack", "HP", +- "Internal Earpiece", "EARPIECE", +- "Internal Speaker", "Speaker Amp OUTL", +- "Internal Speaker", "Speaker Amp OUTR", +- "Speaker Amp INL", "LINEOUT", +- "Speaker Amp INR", "LINEOUT", +- "Left DAC", "DACL", +- "Right DAC", "DACR", +- "ADCL", "Left ADC", +- "ADCR", "Right ADC", +- "Internal Microphone", "MBIAS", +- "MIC1", "Internal Microphone", +- "Headset Microphone", "HBIAS", +- "MIC2", "Headset Microphone"; +- +- simple-audio-card,dai-link@2 { +- format = "dsp_a"; +- frame-master = <&link2_codec>; +- bitclock-master = <&link2_codec>; +- bitclock-inversion; +- +- link2_cpu: cpu { +- sound-dai = <&bt_sco_codec 0>; +- }; +- +- link2_codec: codec { +- sound-dai = <&codec 2>; +- dai-tdm-slot-num = <1>; +- dai-tdm-slot-width = <32>; +- }; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; +- status = "okay"; +- +- bluetooth { +- compatible = "realtek,rtl8723cs-bt"; +- device-wake-gpios = <&pio 7 6 GPIO_ACTIVE_LOW>; /* PH6 */ +- enable-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ +- host-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ +- }; +-}; +- +-/* Connected to the modem (hardware flow control can't be used) */ +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinetab-early-adopter.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinetab-early-adopter.dts +deleted file mode 100644 +index 6265360ce623..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinetab-early-adopter.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2020 Icenowy Zheng +- * +- */ +- +-/dts-v1/; +- +-#include "sun50i-a64-pinetab.dts" +- +-/ { +- model = "PineTab, Early Adopter's version"; +- compatible = "pine64,pinetab-early-adopter", "allwinner,sun50i-a64"; +-}; +- +-&dsi { +- /delete-node/ panel@0; +- +- panel@0 { +- compatible = "feixin,k101-im2byl02", "ilitek,ili9881c"; +- reg = <0>; +- power-supply = <®_dc1sw>; +- reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ +- backlight = <&backlight>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinetab.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinetab.dts +deleted file mode 100644 +index 7ef96f9ff7ae..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-pinetab.dts ++++ /dev/null +@@ -1,457 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 Icenowy Zheng +- * +- */ +- +-/dts-v1/; +- +-#include "sun50i-a64.dtsi" +-#include "sun50i-a64-cpu-opp.dtsi" +- +-#include +-#include +-#include +- +-/ { +- model = "PineTab, Development Sample"; +- compatible = "pine64,pinetab", "allwinner,sun50i-a64"; +- +- aliases { +- serial0 = &uart0; +- ethernet0 = &rtl8723cs; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; +- brightness-levels = <0 16 18 20 22 24 26 29 32 35 38 42 46 51 56 62 68 75 83 91 100>; +- default-brightness-level = <15>; +- enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ +- power-supply = <&vdd_bl>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- i2c-csi { +- compatible = "i2c-gpio"; +- sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>; /* PE13 */ +- scl-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; /* PE12 */ +- i2c-gpio,delay-us = <5>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Rear camera */ +- ov5640: camera@3c { +- compatible = "ovti,ov5640"; +- reg = <0x3c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&csi_mclk_pin>; +- clocks = <&ccu CLK_CSI_MCLK>; +- clock-names = "xclk"; +- +- AVDD-supply = <®_dldo3>; +- DOVDD-supply = <®_aldo1>; +- DVDD-supply = <®_eldo3>; +- reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* PE14 */ +- powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */ +- +- port { +- ov5640_ep: endpoint { +- remote-endpoint = <&csi_ep>; +- bus-width = <8>; +- hsync-active = <1>; /* Active high */ +- vsync-active = <0>; /* Active low */ +- data-active = <1>; /* Active high */ +- pclk-sample = <1>; /* Rising */ +- }; +- }; +- }; +- }; +- +- speaker_amp: audio-amplifier { +- compatible = "simple-audio-amplifier"; +- enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ +- sound-name-prefix = "Speaker Amp"; +- }; +- +- vdd_bl: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "bl-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ +- enable-active-high; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ +- post-power-on-delay-ms = <200>; +- }; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&codec_analog { +- cpvdd-supply = <®_eldo1>; +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu1 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu2 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu3 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&csi { +- status = "okay"; +- +- port { +- csi_ep: endpoint { +- remote-endpoint = <&ov5640_ep>; +- bus-width = <8>; +- hsync-active = <1>; /* Active high */ +- vsync-active = <0>; /* Active low */ +- data-active = <1>; /* Active high */ +- pclk-sample = <1>; /* Rising */ +- }; +- }; +-}; +- +-&dai { +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&dphy { +- status = "okay"; +-}; +- +-&dsi { +- vcc-dsi-supply = <®_dldo1>; +- status = "okay"; +- +- panel@0 { +- compatible = "feixin,k101-im2ba02"; +- reg = <0>; +- avdd-supply = <®_dc1sw>; +- dvdd-supply = <®_dc1sw>; +- cvdd-supply = <®_ldo_io1>; +- reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ +- backlight = <&backlight>; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- touchscreen@5d { +- compatible = "goodix,gt9271"; +- reg = <0x5d>; +- interrupt-parent = <&pio>; +- interrupts = <7 4 IRQ_TYPE_LEVEL_HIGH>; /* PH4 */ +- irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ +- reset-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ +- AVDD28-supply = <®_ldo_io1>; +- }; +-}; +- +-&i2c0_pins { +- bias-pull-up; +-}; +- +-&i2c1 { +- status = "okay"; +- +- /* TODO: add Bochs BMA223 accelerometer here */ +-}; +- +-&lradc { +- vref-supply = <®_aldo3>; +- status = "okay"; +- +- button-200 { +- label = "Volume Up"; +- linux,code = ; +- channel = <0>; +- voltage = <200000>; +- }; +- +- button-400 { +- label = "Volume Down"; +- linux,code = ; +- channel = <0>; +- voltage = <400000>; +- }; +-}; +- +-&mixer1 { +- status = "okay"; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_dcdc1>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; +- disable-wp; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <®_dldo4>; +- vqmmc-supply = <®_eldo1>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- rtl8723cs: wifi@1 { +- reg = <1>; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_dcdc1>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&pwm { +- status = "okay"; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp803: pmic@3a3 { +- compatible = "x-powers,axp803"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- x-powers,drive-vbus-en; +- }; +-}; +- +-#include "axp803.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_aldo1 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "dovdd-csi"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pl"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pll-avcc"; +-}; +- +-®_dc1sw { +- regulator-name = "vcc-lcd"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-cpux"; +-}; +- +-/* DCDC3 is polyphased with DCDC2 */ +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dcdc6 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dldo1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-hdmi-dsi-sensor"; +-}; +- +-®_dldo3 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "avdd-csi"; +-}; +- +-®_dldo4 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-®_drivevbus { +- regulator-name = "usb0-vbus"; +- status = "okay"; +-}; +- +-®_eldo1 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "cpvdd"; +-}; +- +-®_eldo2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcca-1v8"; +-}; +- +-®_eldo3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "dvdd-1v8-csi"; +-}; +- +-®_fldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-1v2-hsic"; +-}; +- +-®_fldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_ldo_io0 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-usb"; +- status = "okay"; +-}; +- +-®_ldo_io1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <3500000>; +- regulator-name = "vcc-touchscreen"; +- status = "okay"; +-}; +- +-®_rtc_ldo { +- regulator-name = "vcc-rtc"; +-}; +- +-&sound { +- status = "okay"; +- simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; +- simple-audio-card,widgets = "Microphone", "Internal Microphone Left", +- "Microphone", "Internal Microphone Right", +- "Headphone", "Headphone Jack", +- "Speaker", "Internal Speaker"; +- simple-audio-card,routing = +- "Left DAC", "DACL", +- "Right DAC", "DACR", +- "Speaker Amp INL", "LINEOUT", +- "Speaker Amp INR", "LINEOUT", +- "Internal Speaker", "Speaker Amp OUTL", +- "Internal Speaker", "Speaker Amp OUTR", +- "Headphone Jack", "HP", +- "ADCL", "Left ADC", +- "ADCR", "Right ADC", +- "Internal Microphone Left", "MBIAS", +- "MIC1", "Internal Microphone Left", +- "Internal Microphone Right", "HBIAS", +- "MIC2", "Internal Microphone Right"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb_power_supply { +- status = "okay"; +-}; +- +-&usbphy { +- usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ +- usb0_vbus_power-supply = <&usb_power_supply>; +- usb0_vbus-supply = <®_drivevbus>; +- usb1_vbus-supply = <®_ldo_io0>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-sopine-baseboard.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-sopine-baseboard.dts +deleted file mode 100644 +index 5e66ce1a334f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-sopine-baseboard.dts ++++ /dev/null +@@ -1,206 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (c) 2017 Icenowy Zheng +-// Based on sun50i-a64-pine64.dts, which is: +-// Copyright (c) 2016 ARM Ltd. +- +-/dts-v1/; +- +-#include "sun50i-a64-sopine.dtsi" +- +-/ { +- model = "SoPine with baseboard"; +- compatible = "pine64,sopine-baseboard", "pine64,sopine", +- "allwinner,sun50i-a64"; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- reg_vcc1v8: vcc1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +-}; +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&codec_analog { +- status = "okay"; +-}; +- +-&dai { +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- phy-mode = "rgmii-txid"; +- phy-handle = <&ext_rgmii_phy>; +- phy-supply = <®_dc1sw>; +- status = "okay"; +-}; +- +-&hdmi { +- hvcc-supply = <®_dldo1>; +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_vcc1v8>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- mmc-hs200-1_8v; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-®_dc1sw { +- /* +- * Ethernet PHY needs 30ms to properly power up and some more +- * to initialize. 100ms should be plenty of time to finish +- * whole process. +- */ +- regulator-enable-ramp-delay = <100000>; +- regulator-name = "vcc-phy"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-hdmi"; +-}; +- +-®_dldo2 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-mipi"; +-}; +- +-®_dldo4 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi"; +-}; +- +-&simplefb_hdmi { +- vcc-hdmi-supply = <®_dldo1>; +-}; +- +-&sound { +- simple-audio-card,aux-devs = <&codec_analog>; +- simple-audio-card,widgets = "Microphone", "Microphone Jack", +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "Left DAC", "DACL", +- "Right DAC", "DACR", +- "Headphone Jack", "HP", +- "ADCL", "Left ADC", +- "ADCR", "Right ADC", +- "MIC2", "Microphone Jack"; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-/* On Pi-2 connector */ +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "disabled"; +-}; +- +-/* On Euler connector */ +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- status = "disabled"; +-}; +- +-/* On Euler connector, RTS/CTS optional */ +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pins>; +- status = "disabled"; +-}; +- +-&usb_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-sopine.dtsi b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-sopine.dtsi +deleted file mode 100644 +index 6d78a1c98f10..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-sopine.dtsi ++++ /dev/null +@@ -1,137 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (c) 2017 Icenowy Zheng +-// Based on sun50i-a64-pine64.dts, which is: +-// Copyright (c) 2016 ARM Ltd. +- +-#include "sun50i-a64.dtsi" +-#include "sun50i-a64-cpu-opp.dtsi" +- +-#include +- +-&codec_analog { +- cpvdd-supply = <®_eldo1>; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu1 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu2 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu3 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_dcdc1>; +- disable-wp; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 push-pull switch */ +- status = "okay"; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp803: pmic@3a3 { +- compatible = "x-powers,axp803"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; +- }; +-}; +- +-#include "axp803.dtsi" +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pl"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-pll-avcc"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1040000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-cpux"; +-}; +- +-/* DCDC3 is polyphased with DCDC2 */ +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-dram"; +-}; +- +-®_dcdc6 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_eldo1 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vdd-1v8-lpddr"; +-}; +- +-®_fldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-1v2-hsic"; +-}; +- +-/* +- * The A64 chip cannot work without this regulator off, although +- * it seems to be only driving the AR100 core. +- * Maybe we don't still know well about CPUs domain. +- */ +-®_fldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_rtc_ldo { +- regulator-name = "vcc-rtc"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-teres-i.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-teres-i.dts +deleted file mode 100644 +index 45e1abdf70a0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64-teres-i.dts ++++ /dev/null +@@ -1,382 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// Copyright (C) Harald Geyer +-// based on sun50i-a64-olinuxino.dts by Jagan Teki +- +-/dts-v1/; +- +-#include "sun50i-a64.dtsi" +-#include "sun50i-a64-cpu-opp.dtsi" +- +-#include +-#include +-#include +- +-/ { +- model = "Olimex A64 Teres-I"; +- compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 0 50000 0>; +- power-supply = <®_dcdc1>; +- brightness-levels = <0 5 7 10 14 20 28 40 56 80 112>; +- default-brightness-level = <5>; +- enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- +- framebuffer-lcd { +- eDP25-supply = <®_dldo2>; +- eDP12-supply = <®_dldo3>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- lid-switch { +- label = "Lid Switch"; +- gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ +- linux,input-type = ; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "teres-i:green:capslock"; +- gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */ +- }; +- +- led-1 { +- label = "teres-i:green:numlock"; +- gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */ +- }; +- }; +- +- reg_usb1_vbus: usb1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb1-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ +- status = "okay"; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ +- }; +- +- speaker_amp: audio-amplifier { +- compatible = "simple-audio-amplifier"; +- enable-gpios = <&r_pio 0 12 GPIO_ACTIVE_HIGH>; /* PL12 */ +- sound-name-prefix = "Speaker Amp"; +- }; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&codec_analog { +- cpvdd-supply = <®_eldo1>; +- status = "okay"; +-}; +- +-&dai { +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu1 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu2 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&cpu3 { +- cpu-supply = <®_dcdc2>; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +- +-&i2c0 { +- clock-frequency = <100000>; +- status = "okay"; +- +- anx6345: anx6345@38 { +- compatible = "analogix,anx6345"; +- reg = <0x38>; +- reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ +- dvdd25-supply = <®_dldo2>; +- dvdd12-supply = <®_dldo3>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- anx6345_in: endpoint { +- remote-endpoint = <&tcon0_out_anx6345>; +- }; +- }; +- }; +- }; +-}; +- +-&mixer0 { +- status = "okay"; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_dcdc1>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; +- disable-wp; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&mmc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <®_aldo2>; +- vqmmc-supply = <®_dldo4>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- rtl8723bs: wifi@1 { +- reg = <1>; +- interrupt-parent = <&r_pio>; +- interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_dcdc1>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&pwm { +- status = "okay"; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp803: pmic@3a3 { +- compatible = "x-powers,axp803"; +- reg = <0x3a3>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- wakeup-source; +- }; +-}; +- +-#include "axp803.dtsi" +- +-&ac_power_supply { +- status = "okay"; +-}; +- +-&battery_power_supply { +- status = "okay"; +-}; +- +-®_aldo1 { +- regulator-always-on; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-name = "vcc-pe"; +-}; +- +-®_aldo2 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pl"; +-}; +- +-®_aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc-pll-avcc"; +-}; +- +-®_dcdc1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +-}; +- +-®_dcdc2 { +- regulator-always-on; +- regulator-min-microvolt = <1040000>; +- regulator-max-microvolt = <1300000>; +- regulator-name = "vdd-cpux"; +-}; +- +-/* DCDC3 is polyphased with DCDC2 */ +- +-®_dcdc5 { +- regulator-always-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc-ddr3"; +-}; +- +-®_dcdc6 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-sys"; +-}; +- +-®_dldo1 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-hdmi"; +-}; +- +-®_dldo2 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-name = "vcc-pd"; +-}; +- +-®_dldo3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vdd-edp"; +-}; +- +-®_dldo4 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-io"; +-}; +- +-®_eldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "cpvdd"; +-}; +- +-®_eldo2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-dvdd-csi"; +-}; +- +-®_fldo1 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-1v2-hsic"; +-}; +- +-/* +- * The A64 chip cannot work with this regulator off, although +- * it seems to be only driving the AR100 core. +- * Maybe we don't still know well about CPUs domain. +- */ +-®_fldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-name = "vdd-cpus"; +-}; +- +-®_rtc_ldo { +- regulator-name = "vcc-rtc"; +-}; +- +-&simplefb_hdmi { +- vcc-hdmi-supply = <®_dldo1>; +-}; +- +-&sound { +- simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; +- simple-audio-card,widgets = "Headphone", "Headphone Jack", +- "Microphone", "Headset Microphone", +- "Microphone", "Internal Microphone", +- "Speaker", "Internal Speaker"; +- simple-audio-card,routing = +- "Left DAC", "DACL", +- "Right DAC", "DACR", +- "ADCL", "Left ADC", +- "ADCR", "Right ADC", +- "Headphone Jack", "HP", +- "Speaker Amp INL", "LINEOUT", +- "Speaker Amp INR", "LINEOUT", +- "Internal Speaker", "Speaker Amp OUTL", +- "Internal Speaker", "Speaker Amp OUTR", +- "Internal Microphone", "MBIAS", +- "MIC1", "Internal Microphone", +- "Headset Microphone", "HBIAS", +- "MIC2", "Headset Microphone"; +- status = "okay"; +-}; +- +-&tcon0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_rgb666_pins>; +- +- status = "okay"; +-}; +- +-&tcon0_out { +- tcon0_out_anx6345: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&anx6345_in>; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pb_pins>; +- status = "okay"; +-}; +- +-&usbphy { +- usb1_vbus-supply = <®_usb1_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64.dtsi b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64.dtsi +deleted file mode 100644 +index 6ddb717f2f98..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-a64.dtsi ++++ /dev/null +@@ -1,1363 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2016 ARM Ltd. +-// based on the Allwinner H3 dtsi: +-// Copyright (C) 2015 Jens Kuske +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- chosen { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- simplefb_lcd: framebuffer-lcd { +- compatible = "allwinner,simple-framebuffer", +- "simple-framebuffer"; +- allwinner,pipeline = "mixer0-lcd0"; +- clocks = <&ccu CLK_TCON0>, +- <&display_clocks CLK_MIXER0>; +- status = "disabled"; +- }; +- +- simplefb_hdmi: framebuffer-hdmi { +- compatible = "allwinner,simple-framebuffer", +- "simple-framebuffer"; +- allwinner,pipeline = "mixer1-lcd1-hdmi"; +- clocks = <&display_clocks CLK_MIXER1>, +- <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; +- status = "disabled"; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0>; +- enable-method = "psci"; +- next-level-cache = <&L2>; +- clocks = <&ccu CLK_CPUX>; +- clock-names = "cpu"; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <1>; +- enable-method = "psci"; +- next-level-cache = <&L2>; +- clocks = <&ccu CLK_CPUX>; +- clock-names = "cpu"; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <2>; +- enable-method = "psci"; +- next-level-cache = <&L2>; +- clocks = <&ccu CLK_CPUX>; +- clock-names = "cpu"; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <3>; +- enable-method = "psci"; +- next-level-cache = <&L2>; +- clocks = <&ccu CLK_CPUX>; +- clock-names = "cpu"; +- #cooling-cells = <2>; +- }; +- +- L2: l2-cache { +- compatible = "cache"; +- cache-level = <2>; +- }; +- }; +- +- de: display-engine { +- compatible = "allwinner,sun50i-a64-display-engine"; +- allwinner,pipelines = <&mixer0>, +- <&mixer1>; +- status = "disabled"; +- }; +- +- osc24M: osc24M_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "osc24M"; +- }; +- +- osc32k: osc32k_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-output-names = "ext-osc32k"; +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- sound: sound { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "simple-audio-card"; +- simple-audio-card,name = "sun50i-a64-audio"; +- simple-audio-card,aux-devs = <&codec_analog>; +- simple-audio-card,routing = +- "Left DAC", "DACL", +- "Right DAC", "DACR", +- "ADCL", "Left ADC", +- "ADCR", "Right ADC"; +- status = "disabled"; +- +- simple-audio-card,dai-link@0 { +- format = "i2s"; +- frame-master = <&link0_cpu>; +- bitclock-master = <&link0_cpu>; +- mclk-fs = <128>; +- +- link0_cpu: cpu { +- sound-dai = <&dai>; +- }; +- +- link0_codec: codec { +- sound-dai = <&codec 0>; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- allwinner,erratum-unknown1; +- arm,no-tick-in-suspend; +- interrupts = , +- , +- , +- ; +- }; +- +- thermal-zones { +- cpu_thermal: cpu0-thermal { +- /* milliseconds */ +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&ths 0>; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu_alert1>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- +- trips { +- cpu_alert0: cpu_alert0 { +- /* milliCelsius */ +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_alert1: cpu_alert1 { +- /* milliCelsius */ +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- cpu_crit: cpu_crit { +- /* milliCelsius */ +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- gpu0_thermal: gpu0-thermal { +- /* milliseconds */ +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&ths 1>; +- }; +- +- gpu1_thermal: gpu1-thermal { +- /* milliseconds */ +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&ths 2>; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- bus@1000000 { +- compatible = "allwinner,sun50i-a64-de2"; +- reg = <0x1000000 0x400000>; +- allwinner,sram = <&de2_sram 1>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1000000 0x400000>; +- +- display_clocks: clock@0 { +- compatible = "allwinner,sun50i-a64-de2-clk"; +- reg = <0x0 0x10000>; +- clocks = <&ccu CLK_BUS_DE>, +- <&ccu CLK_DE>; +- clock-names = "bus", +- "mod"; +- resets = <&ccu RST_BUS_DE>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- rotate: rotate@20000 { +- compatible = "allwinner,sun50i-a64-de2-rotate", +- "allwinner,sun8i-a83t-de2-rotate"; +- reg = <0x20000 0x10000>; +- interrupts = ; +- clocks = <&display_clocks CLK_BUS_ROT>, +- <&display_clocks CLK_ROT>; +- clock-names = "bus", +- "mod"; +- resets = <&display_clocks RST_ROT>; +- }; +- +- mixer0: mixer@100000 { +- compatible = "allwinner,sun50i-a64-de2-mixer-0"; +- reg = <0x100000 0x100000>; +- clocks = <&display_clocks CLK_BUS_MIXER0>, +- <&display_clocks CLK_MIXER0>; +- clock-names = "bus", +- "mod"; +- resets = <&display_clocks RST_MIXER0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mixer0_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- mixer0_out_tcon0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&tcon0_in_mixer0>; +- }; +- +- mixer0_out_tcon1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tcon1_in_mixer0>; +- }; +- }; +- }; +- }; +- +- mixer1: mixer@200000 { +- compatible = "allwinner,sun50i-a64-de2-mixer-1"; +- reg = <0x200000 0x100000>; +- clocks = <&display_clocks CLK_BUS_MIXER1>, +- <&display_clocks CLK_MIXER1>; +- clock-names = "bus", +- "mod"; +- resets = <&display_clocks RST_MIXER1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mixer1_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- mixer1_out_tcon0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&tcon0_in_mixer1>; +- }; +- +- mixer1_out_tcon1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tcon1_in_mixer1>; +- }; +- }; +- }; +- }; +- }; +- +- syscon: syscon@1c00000 { +- compatible = "allwinner,sun50i-a64-system-control"; +- reg = <0x01c00000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- sram_c: sram@18000 { +- compatible = "mmio-sram"; +- reg = <0x00018000 0x28000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00018000 0x28000>; +- +- de2_sram: sram-section@0 { +- compatible = "allwinner,sun50i-a64-sram-c"; +- reg = <0x0000 0x28000>; +- }; +- }; +- +- sram_c1: sram@1d00000 { +- compatible = "mmio-sram"; +- reg = <0x01d00000 0x40000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x01d00000 0x40000>; +- +- ve_sram: sram-section@0 { +- compatible = "allwinner,sun50i-a64-sram-c1", +- "allwinner,sun4i-a10-sram-c1"; +- reg = <0x000000 0x40000>; +- }; +- }; +- }; +- +- dma: dma-controller@1c02000 { +- compatible = "allwinner,sun50i-a64-dma"; +- reg = <0x01c02000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_DMA>; +- dma-channels = <8>; +- dma-requests = <27>; +- resets = <&ccu RST_BUS_DMA>; +- #dma-cells = <1>; +- }; +- +- tcon0: lcd-controller@1c0c000 { +- compatible = "allwinner,sun50i-a64-tcon-lcd", +- "allwinner,sun8i-a83t-tcon-lcd"; +- reg = <0x01c0c000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; +- clock-names = "ahb", "tcon-ch0"; +- clock-output-names = "tcon-pixel-clock"; +- #clock-cells = <0>; +- resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; +- reset-names = "lcd", "lvds"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon0_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- tcon0_in_mixer0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&mixer0_out_tcon0>; +- }; +- +- tcon0_in_mixer1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&mixer1_out_tcon0>; +- }; +- }; +- +- tcon0_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tcon0_out_dsi: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&dsi_in_tcon0>; +- allwinner,tcon-channel = <1>; +- }; +- }; +- }; +- }; +- +- tcon1: lcd-controller@1c0d000 { +- compatible = "allwinner,sun50i-a64-tcon-tv", +- "allwinner,sun8i-a83t-tcon-tv"; +- reg = <0x01c0d000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; +- clock-names = "ahb", "tcon-ch1"; +- resets = <&ccu RST_BUS_TCON1>; +- reset-names = "lcd"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon1_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- tcon1_in_mixer0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&mixer0_out_tcon1>; +- }; +- +- tcon1_in_mixer1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&mixer1_out_tcon1>; +- }; +- }; +- +- tcon1_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tcon1_out_hdmi: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&hdmi_in_tcon1>; +- }; +- }; +- }; +- }; +- +- video-codec@1c0e000 { +- compatible = "allwinner,sun50i-a64-video-engine"; +- reg = <0x01c0e000 0x1000>; +- clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, +- <&ccu CLK_DRAM_VE>; +- clock-names = "ahb", "mod", "ram"; +- resets = <&ccu RST_BUS_VE>; +- interrupts = ; +- allwinner,sram = <&ve_sram 1>; +- }; +- +- mmc0: mmc@1c0f000 { +- compatible = "allwinner,sun50i-a64-mmc"; +- reg = <0x01c0f000 0x1000>; +- clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; +- clock-names = "ahb", "mmc"; +- resets = <&ccu RST_BUS_MMC0>; +- reset-names = "ahb"; +- interrupts = ; +- max-frequency = <150000000>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc1: mmc@1c10000 { +- compatible = "allwinner,sun50i-a64-mmc"; +- reg = <0x01c10000 0x1000>; +- clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; +- clock-names = "ahb", "mmc"; +- resets = <&ccu RST_BUS_MMC1>; +- reset-names = "ahb"; +- interrupts = ; +- max-frequency = <150000000>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc2: mmc@1c11000 { +- compatible = "allwinner,sun50i-a64-emmc"; +- reg = <0x01c11000 0x1000>; +- clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; +- clock-names = "ahb", "mmc"; +- resets = <&ccu RST_BUS_MMC2>; +- reset-names = "ahb"; +- interrupts = ; +- max-frequency = <150000000>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- sid: eeprom@1c14000 { +- compatible = "allwinner,sun50i-a64-sid"; +- reg = <0x1c14000 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ths_calibration: thermal-sensor-calibration@34 { +- reg = <0x34 0x8>; +- }; +- }; +- +- crypto: crypto@1c15000 { +- compatible = "allwinner,sun50i-a64-crypto"; +- reg = <0x01c15000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; +- clock-names = "bus", "mod"; +- resets = <&ccu RST_BUS_CE>; +- }; +- +- msgbox: mailbox@1c17000 { +- compatible = "allwinner,sun50i-a64-msgbox", +- "allwinner,sun6i-a31-msgbox"; +- reg = <0x01c17000 0x1000>; +- clocks = <&ccu CLK_BUS_MSGBOX>; +- resets = <&ccu RST_BUS_MSGBOX>; +- interrupts = ; +- #mbox-cells = <1>; +- }; +- +- usb_otg: usb@1c19000 { +- compatible = "allwinner,sun8i-a33-musb"; +- reg = <0x01c19000 0x0400>; +- clocks = <&ccu CLK_BUS_OTG>; +- resets = <&ccu RST_BUS_OTG>; +- interrupts = ; +- interrupt-names = "mc"; +- phys = <&usbphy 0>; +- phy-names = "usb"; +- extcon = <&usbphy 0>; +- dr_mode = "otg"; +- status = "disabled"; +- }; +- +- usbphy: phy@1c19400 { +- compatible = "allwinner,sun50i-a64-usb-phy"; +- reg = <0x01c19400 0x14>, +- <0x01c1a800 0x4>, +- <0x01c1b800 0x4>; +- reg-names = "phy_ctrl", +- "pmu0", +- "pmu1"; +- clocks = <&ccu CLK_USB_PHY0>, +- <&ccu CLK_USB_PHY1>; +- clock-names = "usb0_phy", +- "usb1_phy"; +- resets = <&ccu RST_USB_PHY0>, +- <&ccu RST_USB_PHY1>; +- reset-names = "usb0_reset", +- "usb1_reset"; +- status = "disabled"; +- #phy-cells = <1>; +- }; +- +- ehci0: usb@1c1a000 { +- compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; +- reg = <0x01c1a000 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_OHCI0>, +- <&ccu CLK_BUS_EHCI0>, +- <&ccu CLK_USB_OHCI0>; +- resets = <&ccu RST_BUS_OHCI0>, +- <&ccu RST_BUS_EHCI0>; +- phys = <&usbphy 0>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci0: usb@1c1a400 { +- compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; +- reg = <0x01c1a400 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_OHCI0>, +- <&ccu CLK_USB_OHCI0>; +- resets = <&ccu RST_BUS_OHCI0>; +- phys = <&usbphy 0>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ehci1: usb@1c1b000 { +- compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; +- reg = <0x01c1b000 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_OHCI1>, +- <&ccu CLK_BUS_EHCI1>, +- <&ccu CLK_USB_OHCI1>; +- resets = <&ccu RST_BUS_OHCI1>, +- <&ccu RST_BUS_EHCI1>; +- phys = <&usbphy 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci1: usb@1c1b400 { +- compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; +- reg = <0x01c1b400 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_OHCI1>, +- <&ccu CLK_USB_OHCI1>; +- resets = <&ccu RST_BUS_OHCI1>; +- phys = <&usbphy 1>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ccu: clock@1c20000 { +- compatible = "allwinner,sun50i-a64-ccu"; +- reg = <0x01c20000 0x400>; +- clocks = <&osc24M>, <&rtc 0>; +- clock-names = "hosc", "losc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pio: pinctrl@1c20800 { +- compatible = "allwinner,sun50i-a64-pinctrl"; +- reg = <0x01c20800 0x400>; +- interrupt-parent = <&r_intc>; +- interrupts = , +- , +- ; +- clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; +- clock-names = "apb", "hosc", "losc"; +- gpio-controller; +- #gpio-cells = <3>; +- interrupt-controller; +- #interrupt-cells = <3>; +- +- /omit-if-no-ref/ +- aif2_pins: aif2-pins { +- pins = "PB4", "PB5", "PB6", "PB7"; +- function = "aif2"; +- }; +- +- /omit-if-no-ref/ +- aif3_pins: aif3-pins { +- pins = "PG10", "PG11", "PG12", "PG13"; +- function = "aif3"; +- }; +- +- csi_pins: csi-pins { +- pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", +- "PE7", "PE8", "PE9", "PE10", "PE11"; +- function = "csi"; +- }; +- +- /omit-if-no-ref/ +- csi_mclk_pin: csi-mclk-pin { +- pins = "PE1"; +- function = "csi"; +- }; +- +- i2c0_pins: i2c0-pins { +- pins = "PH0", "PH1"; +- function = "i2c0"; +- }; +- +- i2c1_pins: i2c1-pins { +- pins = "PH2", "PH3"; +- function = "i2c1"; +- }; +- +- i2c2_pins: i2c2-pins { +- pins = "PE14", "PE15"; +- function = "i2c2"; +- }; +- +- /omit-if-no-ref/ +- lcd_rgb666_pins: lcd-rgb666-pins { +- pins = "PD0", "PD1", "PD2", "PD3", "PD4", +- "PD5", "PD6", "PD7", "PD8", "PD9", +- "PD10", "PD11", "PD12", "PD13", +- "PD14", "PD15", "PD16", "PD17", +- "PD18", "PD19", "PD20", "PD21"; +- function = "lcd0"; +- }; +- +- mmc0_pins: mmc0-pins { +- pins = "PF0", "PF1", "PF2", "PF3", +- "PF4", "PF5"; +- function = "mmc0"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc1_pins: mmc1-pins { +- pins = "PG0", "PG1", "PG2", "PG3", +- "PG4", "PG5"; +- function = "mmc1"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc2_pins: mmc2-pins { +- pins = "PC5", "PC6", "PC8", "PC9", +- "PC10","PC11", "PC12", "PC13", +- "PC14", "PC15", "PC16"; +- function = "mmc2"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc2_ds_pin: mmc2-ds-pin { +- pins = "PC1"; +- function = "mmc2"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- pwm_pin: pwm-pin { +- pins = "PD22"; +- function = "pwm"; +- }; +- +- rmii_pins: rmii-pins { +- pins = "PD10", "PD11", "PD13", "PD14", "PD17", +- "PD18", "PD19", "PD20", "PD22", "PD23"; +- function = "emac"; +- drive-strength = <40>; +- }; +- +- rgmii_pins: rgmii-pins { +- pins = "PD8", "PD9", "PD10", "PD11", "PD12", +- "PD13", "PD15", "PD16", "PD17", "PD18", +- "PD19", "PD20", "PD21", "PD22", "PD23"; +- function = "emac"; +- drive-strength = <40>; +- }; +- +- spdif_tx_pin: spdif-tx-pin { +- pins = "PH8"; +- function = "spdif"; +- }; +- +- spi0_pins: spi0-pins { +- pins = "PC0", "PC1", "PC2", "PC3"; +- function = "spi0"; +- }; +- +- spi1_pins: spi1-pins { +- pins = "PD0", "PD1", "PD2", "PD3"; +- function = "spi1"; +- }; +- +- uart0_pb_pins: uart0-pb-pins { +- pins = "PB8", "PB9"; +- function = "uart0"; +- }; +- +- uart1_pins: uart1-pins { +- pins = "PG6", "PG7"; +- function = "uart1"; +- }; +- +- uart1_rts_cts_pins: uart1-rts-cts-pins { +- pins = "PG8", "PG9"; +- function = "uart1"; +- }; +- +- uart2_pins: uart2-pins { +- pins = "PB0", "PB1"; +- function = "uart2"; +- }; +- +- uart3_pins: uart3-pins { +- pins = "PD0", "PD1"; +- function = "uart3"; +- }; +- +- uart4_pins: uart4-pins { +- pins = "PD2", "PD3"; +- function = "uart4"; +- }; +- +- uart4_rts_cts_pins: uart4-rts-cts-pins { +- pins = "PD4", "PD5"; +- function = "uart4"; +- }; +- }; +- +- timer@1c20c00 { +- compatible = "allwinner,sun50i-a64-timer", +- "allwinner,sun8i-a23-timer"; +- reg = <0x01c20c00 0xa0>; +- interrupts = , +- ; +- clocks = <&osc24M>; +- }; +- +- wdt0: watchdog@1c20ca0 { +- compatible = "allwinner,sun50i-a64-wdt", +- "allwinner,sun6i-a31-wdt"; +- reg = <0x01c20ca0 0x20>; +- interrupts = ; +- clocks = <&osc24M>; +- }; +- +- spdif: spdif@1c21000 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun50i-a64-spdif", +- "allwinner,sun8i-h3-spdif"; +- reg = <0x01c21000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; +- resets = <&ccu RST_BUS_SPDIF>; +- clock-names = "apb", "spdif"; +- dmas = <&dma 2>; +- dma-names = "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spdif_tx_pin>; +- status = "disabled"; +- }; +- +- lradc: lradc@1c21800 { +- compatible = "allwinner,sun50i-a64-lradc", +- "allwinner,sun8i-a83t-r-lradc"; +- reg = <0x01c21800 0x400>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- status = "disabled"; +- }; +- +- i2s0: i2s@1c22000 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun50i-a64-i2s", +- "allwinner,sun8i-h3-i2s"; +- reg = <0x01c22000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; +- clock-names = "apb", "mod"; +- resets = <&ccu RST_BUS_I2S0>; +- dma-names = "rx", "tx"; +- dmas = <&dma 3>, <&dma 3>; +- status = "disabled"; +- }; +- +- i2s1: i2s@1c22400 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun50i-a64-i2s", +- "allwinner,sun8i-h3-i2s"; +- reg = <0x01c22400 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; +- clock-names = "apb", "mod"; +- resets = <&ccu RST_BUS_I2S1>; +- dma-names = "rx", "tx"; +- dmas = <&dma 4>, <&dma 4>; +- status = "disabled"; +- }; +- +- i2s2: i2s@1c22800 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun50i-a64-i2s", +- "allwinner,sun8i-h3-i2s"; +- reg = <0x01c22800 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; +- clock-names = "apb", "mod"; +- resets = <&ccu RST_BUS_I2S2>; +- dma-names = "rx", "tx"; +- dmas = <&dma 27>, <&dma 27>; +- status = "disabled"; +- }; +- +- dai: dai@1c22c00 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun50i-a64-codec-i2s"; +- reg = <0x01c22c00 0x200>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; +- clock-names = "apb", "mod"; +- resets = <&ccu RST_BUS_CODEC>; +- dmas = <&dma 15>, <&dma 15>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- codec: codec@1c22e00 { +- #sound-dai-cells = <1>; +- compatible = "allwinner,sun50i-a64-codec", +- "allwinner,sun8i-a33-codec"; +- reg = <0x01c22e00 0x600>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; +- clock-names = "bus", "mod"; +- status = "disabled"; +- }; +- +- ths: thermal-sensor@1c25000 { +- compatible = "allwinner,sun50i-a64-ths"; +- reg = <0x01c25000 0x100>; +- clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; +- clock-names = "bus", "mod"; +- interrupts = ; +- resets = <&ccu RST_BUS_THS>; +- nvmem-cells = <&ths_calibration>; +- nvmem-cell-names = "calibration"; +- #thermal-sensor-cells = <1>; +- }; +- +- uart0: serial@1c28000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART0>; +- resets = <&ccu RST_BUS_UART0>; +- status = "disabled"; +- }; +- +- uart1: serial@1c28400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28400 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART1>; +- resets = <&ccu RST_BUS_UART1>; +- status = "disabled"; +- }; +- +- uart2: serial@1c28800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28800 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART2>; +- resets = <&ccu RST_BUS_UART2>; +- status = "disabled"; +- }; +- +- uart3: serial@1c28c00 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28c00 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART3>; +- resets = <&ccu RST_BUS_UART3>; +- status = "disabled"; +- }; +- +- uart4: serial@1c29000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c29000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART4>; +- resets = <&ccu RST_BUS_UART4>; +- status = "disabled"; +- }; +- +- i2c0: i2c@1c2ac00 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2ac00 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C0>; +- resets = <&ccu RST_BUS_I2C0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c1: i2c@1c2b000 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2b000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C1>; +- resets = <&ccu RST_BUS_I2C1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c2: i2c@1c2b400 { +- compatible = "allwinner,sun6i-a31-i2c"; +- reg = <0x01c2b400 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C2>; +- resets = <&ccu RST_BUS_I2C2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spi0: spi@1c68000 { +- compatible = "allwinner,sun8i-h3-spi"; +- reg = <0x01c68000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; +- clock-names = "ahb", "mod"; +- dmas = <&dma 23>, <&dma 23>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins>; +- resets = <&ccu RST_BUS_SPI0>; +- status = "disabled"; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spi1: spi@1c69000 { +- compatible = "allwinner,sun8i-h3-spi"; +- reg = <0x01c69000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; +- clock-names = "ahb", "mod"; +- dmas = <&dma 24>, <&dma 24>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins>; +- resets = <&ccu RST_BUS_SPI1>; +- status = "disabled"; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- emac: ethernet@1c30000 { +- compatible = "allwinner,sun50i-a64-emac"; +- syscon = <&syscon>; +- reg = <0x01c30000 0x10000>; +- interrupts = ; +- interrupt-names = "macirq"; +- resets = <&ccu RST_BUS_EMAC>; +- reset-names = "stmmaceth"; +- clocks = <&ccu CLK_BUS_EMAC>; +- clock-names = "stmmaceth"; +- status = "disabled"; +- +- mdio: mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- mali: gpu@1c40000 { +- compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; +- reg = <0x01c40000 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "gp", +- "gpmmu", +- "pp0", +- "ppmmu0", +- "pp1", +- "ppmmu1", +- "pmu"; +- clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; +- clock-names = "bus", "core"; +- resets = <&ccu RST_BUS_GPU>; +- }; +- +- gic: interrupt-controller@1c81000 { +- compatible = "arm,gic-400"; +- reg = <0x01c81000 0x1000>, +- <0x01c82000 0x2000>, +- <0x01c84000 0x2000>, +- <0x01c86000 0x2000>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- +- pwm: pwm@1c21400 { +- compatible = "allwinner,sun50i-a64-pwm", +- "allwinner,sun5i-a13-pwm"; +- reg = <0x01c21400 0x400>; +- clocks = <&osc24M>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- mbus: dram-controller@1c62000 { +- compatible = "allwinner,sun50i-a64-mbus"; +- reg = <0x01c62000 0x1000>; +- clocks = <&ccu 112>; +- #address-cells = <1>; +- #size-cells = <1>; +- dma-ranges = <0x00000000 0x40000000 0xc0000000>; +- #interconnect-cells = <1>; +- }; +- +- csi: csi@1cb0000 { +- compatible = "allwinner,sun50i-a64-csi"; +- reg = <0x01cb0000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_CSI>, +- <&ccu CLK_CSI_SCLK>, +- <&ccu CLK_DRAM_CSI>; +- clock-names = "bus", "mod", "ram"; +- resets = <&ccu RST_BUS_CSI>; +- pinctrl-names = "default"; +- pinctrl-0 = <&csi_pins>; +- status = "disabled"; +- }; +- +- dsi: dsi@1ca0000 { +- compatible = "allwinner,sun50i-a64-mipi-dsi"; +- reg = <0x01ca0000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_MIPI_DSI>; +- resets = <&ccu RST_BUS_MIPI_DSI>; +- phys = <&dphy>; +- phy-names = "dphy"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- port { +- dsi_in_tcon0: endpoint { +- remote-endpoint = <&tcon0_out_dsi>; +- }; +- }; +- }; +- +- dphy: d-phy@1ca1000 { +- compatible = "allwinner,sun50i-a64-mipi-dphy", +- "allwinner,sun6i-a31-mipi-dphy"; +- reg = <0x01ca1000 0x1000>; +- clocks = <&ccu CLK_BUS_MIPI_DSI>, +- <&ccu CLK_DSI_DPHY>; +- clock-names = "bus", "mod"; +- resets = <&ccu RST_BUS_MIPI_DSI>; +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- deinterlace: deinterlace@1e00000 { +- compatible = "allwinner,sun50i-a64-deinterlace", +- "allwinner,sun8i-h3-deinterlace"; +- reg = <0x01e00000 0x20000>; +- clocks = <&ccu CLK_BUS_DEINTERLACE>, +- <&ccu CLK_DEINTERLACE>, +- <&ccu CLK_DRAM_DEINTERLACE>; +- clock-names = "bus", "mod", "ram"; +- resets = <&ccu RST_BUS_DEINTERLACE>; +- interrupts = ; +- interconnects = <&mbus 9>; +- interconnect-names = "dma-mem"; +- }; +- +- hdmi: hdmi@1ee0000 { +- compatible = "allwinner,sun50i-a64-dw-hdmi", +- "allwinner,sun8i-a83t-dw-hdmi"; +- reg = <0x01ee0000 0x10000>; +- reg-io-width = <1>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, +- <&ccu CLK_HDMI>; +- clock-names = "iahb", "isfr", "tmds"; +- resets = <&ccu RST_BUS_HDMI1>; +- reset-names = "ctrl"; +- phys = <&hdmi_phy>; +- phy-names = "phy"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- hdmi_in: port@0 { +- reg = <0>; +- +- hdmi_in_tcon1: endpoint { +- remote-endpoint = <&tcon1_out_hdmi>; +- }; +- }; +- +- hdmi_out: port@1 { +- reg = <1>; +- }; +- }; +- }; +- +- hdmi_phy: hdmi-phy@1ef0000 { +- compatible = "allwinner,sun50i-a64-hdmi-phy"; +- reg = <0x01ef0000 0x10000>; +- clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, +- <&ccu CLK_PLL_VIDEO0>; +- clock-names = "bus", "mod", "pll-0"; +- resets = <&ccu RST_BUS_HDMI0>; +- reset-names = "phy"; +- #phy-cells = <0>; +- }; +- +- rtc: rtc@1f00000 { +- compatible = "allwinner,sun50i-a64-rtc", +- "allwinner,sun8i-h3-rtc"; +- reg = <0x01f00000 0x400>; +- interrupt-parent = <&r_intc>; +- interrupts = , +- ; +- clock-output-names = "osc32k", "osc32k-out", "iosc"; +- clocks = <&osc32k>; +- #clock-cells = <1>; +- }; +- +- r_intc: interrupt-controller@1f00c00 { +- compatible = "allwinner,sun50i-a64-r-intc", +- "allwinner,sun6i-a31-r-intc"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x01f00c00 0x400>; +- interrupts = ; +- }; +- +- r_ccu: clock@1f01400 { +- compatible = "allwinner,sun50i-a64-r-ccu"; +- reg = <0x01f01400 0x100>; +- clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, +- <&ccu CLK_PLL_PERIPH0>; +- clock-names = "hosc", "losc", "iosc", "pll-periph"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- codec_analog: codec-analog@1f015c0 { +- compatible = "allwinner,sun50i-a64-codec-analog"; +- reg = <0x01f015c0 0x4>; +- status = "disabled"; +- }; +- +- r_i2c: i2c@1f02400 { +- compatible = "allwinner,sun50i-a64-i2c", +- "allwinner,sun6i-a31-i2c"; +- reg = <0x01f02400 0x400>; +- interrupts = ; +- clocks = <&r_ccu CLK_APB0_I2C>; +- resets = <&r_ccu RST_APB0_I2C>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- r_ir: ir@1f02000 { +- compatible = "allwinner,sun50i-a64-ir", +- "allwinner,sun6i-a31-ir"; +- reg = <0x01f02000 0x400>; +- clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; +- clock-names = "apb", "ir"; +- resets = <&r_ccu RST_APB0_IR>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&r_ir_rx_pin>; +- status = "disabled"; +- }; +- +- r_pwm: pwm@1f03800 { +- compatible = "allwinner,sun50i-a64-pwm", +- "allwinner,sun5i-a13-pwm"; +- reg = <0x01f03800 0x400>; +- clocks = <&osc24M>; +- pinctrl-names = "default"; +- pinctrl-0 = <&r_pwm_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- r_pio: pinctrl@1f02c00 { +- compatible = "allwinner,sun50i-a64-r-pinctrl"; +- reg = <0x01f02c00 0x400>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; +- clock-names = "apb", "hosc", "losc"; +- gpio-controller; +- #gpio-cells = <3>; +- interrupt-controller; +- #interrupt-cells = <3>; +- +- r_i2c_pl89_pins: r-i2c-pl89-pins { +- pins = "PL8", "PL9"; +- function = "s_i2c"; +- }; +- +- r_ir_rx_pin: r-ir-rx-pin { +- pins = "PL11"; +- function = "s_cir_rx"; +- }; +- +- r_pwm_pin: r-pwm-pin { +- pins = "PL10"; +- function = "s_pwm"; +- }; +- +- r_rsb_pins: r-rsb-pins { +- pins = "PL0", "PL1"; +- function = "s_rsb"; +- }; +- }; +- +- r_rsb: rsb@1f03400 { +- compatible = "allwinner,sun8i-a23-rsb"; +- reg = <0x01f03400 0x400>; +- interrupts = ; +- clocks = <&r_ccu 6>; +- clock-frequency = <3000000>; +- resets = <&r_ccu 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&r_rsb_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts +deleted file mode 100644 +index 8857a3791593..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2018 Chen-Yu Tsai +- +-/dts-v1/; +-#include "sun50i-h5.dtsi" +-#include "sun50i-h5-cpu-opp.dtsi" +-#include +- +-/ { +- model = "Banana Pi BPI-M2-Plus v1.2 H5"; +- compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun50i-h5"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-bananapi-m2-plus.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-bananapi-m2-plus.dts +deleted file mode 100644 +index 77661006dfba..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-bananapi-m2-plus.dts ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2018 Chen-Yu Tsai +- +-/dts-v1/; +-#include "sun50i-h5.dtsi" +-#include +- +-/ { +- model = "Banana Pi BPI-M2-Plus H5"; +- compatible = "sinovoip,bpi-m2-plus", "allwinner,sun50i-h5"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-cpu-opp.dtsi b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-cpu-opp.dtsi +deleted file mode 100644 +index 1afad8b437d7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-cpu-opp.dtsi ++++ /dev/null +@@ -1,79 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2020 Chen-Yu Tsai +- +-/ { +- cpu_opp_table: opp-table-cpu { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-408000000 { +- opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <1000000 1000000 1310000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-648000000 { +- opp-hz = /bits/ 64 <648000000>; +- opp-microvolt = <1040000 1040000 1310000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-816000000 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <1080000 1080000 1310000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-912000000 { +- opp-hz = /bits/ 64 <912000000>; +- opp-microvolt = <1120000 1120000 1310000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-960000000 { +- opp-hz = /bits/ 64 <960000000>; +- opp-microvolt = <1160000 1160000 1310000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-1008000000 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <1200000 1200000 1310000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-1056000000 { +- opp-hz = /bits/ 64 <1056000000>; +- opp-microvolt = <1240000 1240000 1310000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-1104000000 { +- opp-hz = /bits/ 64 <1104000000>; +- opp-microvolt = <1260000 1260000 1310000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- +- opp-1152000000 { +- opp-hz = /bits/ 64 <1152000000>; +- opp-microvolt = <1300000 1300000 1310000>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- }; +- }; +-}; +- +-&cpu0 { +- operating-points-v2 = <&cpu_opp_table>; +-}; +- +-&cpu1 { +- operating-points-v2 = <&cpu_opp_table>; +-}; +- +-&cpu2 { +- operating-points-v2 = <&cpu_opp_table>; +-}; +- +-&cpu3 { +- operating-points-v2 = <&cpu_opp_table>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts +deleted file mode 100644 +index 076a0b983101..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts ++++ /dev/null +@@ -1,71 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-// Copyright (C) 2018 Aleksandr Aleksandrov +- +-/* +- * DTS for Emlid Neutis N5 Dev board. +- */ +- +-/dts-v1/; +- +-#include "sun50i-h5-emlid-neutis-n5.dtsi" +- +-/ { +- model = "Emlid Neutis N5 Developer board"; +- compatible = "emlid,neutis-n5-devboard", +- "emlid,neutis-n5", +- "allwinner,sun50i-h5"; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- vdd_cpux: gpio-regulator { +- compatible = "regulator-gpio"; +- regulator-name = "vdd-cpux"; +- regulator-type = "voltage"; +- regulator-boot-on; +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1300000>; +- regulator-ramp-delay = <50>; /* 4ms */ +- gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ +- gpios-states = <0x1>; +- states = <1100000 0>, <1300000 1>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_cpux>; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&int_mii_phy>; +- phy-mode = "mii"; +- allwinner,leds-active-low; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-emlid-neutis-n5.dtsi b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-emlid-neutis-n5.dtsi +deleted file mode 100644 +index fc570011495f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-emlid-neutis-n5.dtsi ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +-// Copyright (C) 2018 Aleksandr Aleksandrov +- +-/* +- * DTSI for Emlid Neutis N5 SoM. +- */ +- +-/dts-v1/; +- +-#include "sun50i-h5.dtsi" +-#include +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-libretech-all-h3-cc.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-libretech-all-h3-cc.dts +deleted file mode 100644 +index d811df332824..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-libretech-all-h3-cc.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2018 BayLibre, SAS +-// Author: Neil Armstrong +- +-/dts-v1/; +-#include "sun50i-h5.dtsi" +-#include "sun50i-h5-cpu-opp.dtsi" +-#include +- +-/ { +- model = "Libre Computer Board ALL-H3-CC H5"; +- compatible = "libretech,all-h3-cc-h5", "allwinner,sun50i-h5"; +-}; +- +-&mmc2 { +- mmc-ddr-3_3v; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-libretech-all-h3-it.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-libretech-all-h3-it.dts +deleted file mode 100644 +index e59d68b525fc..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-libretech-all-h3-it.dts ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2019 Chen-Yu Tsai +- +-/dts-v1/; +-#include "sun50i-h5.dtsi" +-#include +- +-/ { +- model = "Libre Computer Board ALL-H3-IT H5"; +- compatible = "libretech,all-h3-it-h5", "allwinner,sun50i-h5"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-libretech-all-h5-cc.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-libretech-all-h5-cc.dts +deleted file mode 100644 +index 6e30a564c87f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-libretech-all-h5-cc.dts ++++ /dev/null +@@ -1,61 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2020 Chen-Yu Tsai +- +-#include "sun50i-h5-libretech-all-h3-cc.dts" +- +-/ { +- model = "Libre Computer Board ALL-H5-CC H5"; +- compatible = "libretech,all-h5-cc-h5", "allwinner,sun50i-h5"; +- +- aliases { +- spi0 = &spi0; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <5000>; +- enable-active-high; +- gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; +- vin-supply = <®_vcc5v0>; +- }; +-}; +- +-&codec { +- /* No line out; only onboard microphone */ +- allwinner,audio-routing = +- "MIC1", "Mic", +- "Mic", "MBIAS"; +-}; +- +-/* This board has external PHY */ +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_rgmii_pins>; +- phy-supply = <®_gmac_3v3>; +- phy-handle = <&ext_rgmii_phy>; +- phy-mode = "rgmii-id"; +- /delete-property/ allwinner,leds-active-low; +- status = "okay"; +-}; +- +-&external_mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-nanopi-neo-plus2.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-nanopi-neo-plus2.dts +deleted file mode 100644 +index 4c3921ac236c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-nanopi-neo-plus2.dts ++++ /dev/null +@@ -1,163 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2017 Antony Antony +-// Copyright (C) 2016 ARM Ltd. +- +-/dts-v1/; +-#include "sun50i-h5.dtsi" +- +-#include +-#include +-#include +- +-/ { +- model = "FriendlyARM NanoPi NEO Plus2"; +- compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5"; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "nanopi:green:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- led-1 { +- label = "nanopi:red:status"; +- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- enable-active-high; +- gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_vcc3v3: vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vdd_cpux: gpio-regulator { +- compatible = "regulator-gpio"; +- regulator-name = "vdd-cpux"; +- regulator-type = "voltage"; +- regulator-boot-on; +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1300000>; +- regulator-ramp-delay = <50>; /* 4ms */ +- gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; +- gpios-states = <0x1>; +- states = <1100000 0>, <1300000 1>; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ +- post-power-on-delay-ms = <200>; +- }; +-}; +- +-&codec { +- allwinner,audio-routing = +- "Line Out", "LINEOUT", +- "MIC1", "Mic", +- "Mic", "MBIAS"; +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci3 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_rgmii_pins>; +- phy-supply = <®_gmac_3v3>; +- phy-handle = <&ext_rgmii_phy>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&external_mdio { +- ext_rgmii_phy: ethernet-phy@7 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <7>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- vqmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_pins>; +- vmmc-supply = <®_vcc3v3>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci3 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbphy { +- /* USB Type-A ports' VBUS is always on */ +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-nanopi-neo2.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-nanopi-neo2.dts +deleted file mode 100644 +index 05486cccee1c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-nanopi-neo2.dts ++++ /dev/null +@@ -1,120 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2017 Icenowy Zheng +- +-/dts-v1/; +-#include "sun50i-h5.dtsi" +- +-#include +- +-/ { +- model = "FriendlyARM NanoPi NEO 2"; +- compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "nanopi:green:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- led-1 { +- label = "nanopi:blue:status"; +- gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- enable-active-high; +- gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_vcc3v3: vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_usb0_vbus: usb0-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb0-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ +- status = "okay"; +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci3 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_rgmii_pins>; +- phy-supply = <®_gmac_3v3>; +- phy-handle = <&ext_rgmii_phy>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&external_mdio { +- ext_rgmii_phy: ethernet-phy@7 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <7>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci3 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- /* USB Type-A port's VBUS is always on */ +- usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-nanopi-r1s-h5.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-nanopi-r1s-h5.dts +deleted file mode 100644 +index 55bcdf8d1a07..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-nanopi-r1s-h5.dts ++++ /dev/null +@@ -1,195 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2021 Chukun Pan +- * +- * Based on sun50i-h5-nanopi-neo-plus2.dts, which is: +- * Copyright (C) 2017 Antony Antony +- * Copyright (C) 2016 ARM Ltd. +- */ +- +-/dts-v1/; +-#include "sun50i-h5.dtsi" +-#include "sun50i-h5-cpu-opp.dtsi" +- +-#include +-#include +-#include +- +-/ { +- model = "FriendlyARM NanoPi R1S H5"; +- compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5"; +- +- aliases { +- ethernet0 = &emac; +- ethernet1 = &rtl8189etv; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- function = LED_FUNCTION_LAN; +- color = ; +- gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; +- }; +- +- led-1 { +- function = LED_FUNCTION_STATUS; +- color = ; +- gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-2 { +- function = LED_FUNCTION_WAN; +- color = ; +- gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- r-gpio-keys { +- compatible = "gpio-keys"; +- +- reset { +- label = "reset"; +- linux,code = ; +- gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- enable-active-high; +- gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_vcc3v3: vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_usb0_vbus: usb0-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb0-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ +- status = "okay"; +- }; +- +- vdd_cpux: gpio-regulator { +- compatible = "regulator-gpio"; +- regulator-name = "vdd-cpux"; +- regulator-type = "voltage"; +- regulator-boot-on; +- regulator-always-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1300000>; +- regulator-ramp-delay = <50>; /* 4ms */ +- gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; +- gpios-states = <0x1>; +- states = <1100000 0x0>, <1300000 0x1>; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ +- post-power-on-delay-ms = <200>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_cpux>; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_rgmii_pins>; +- phy-supply = <®_gmac_3v3>; +- phy-handle = <&ext_rgmii_phy>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&external_mdio { +- ext_rgmii_phy: ethernet-phy@7 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <7>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- eeprom@51 { +- compatible = "microchip,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- vqmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- rtl8189etv: sdio_wifi@1 { +- reg = <1>; +- }; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usbphy { +- /* USB Type-A port's VBUS is always on */ +- usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-orangepi-pc2.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-orangepi-pc2.dts +deleted file mode 100644 +index 1010c1b22d2e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-orangepi-pc2.dts ++++ /dev/null +@@ -1,232 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2016 ARM Ltd. +- +-/dts-v1/; +-#include "sun50i-h5.dtsi" +- +-#include +-#include +-#include +- +-/ { +- model = "Xunlong Orange Pi PC 2"; +- compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5"; +- +- reg_vcc3v3: vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "orangepi:green:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- led-1 { +- label = "orangepi:red:status"; +- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- r-gpio-keys { +- compatible = "gpio-keys"; +- +- sw4 { +- label = "sw4"; +- linux,code = ; +- gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; +- wakeup-source; +- }; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- enable-active-high; +- gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_usb0_vbus: usb0-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb0-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ +- status = "okay"; +- }; +-}; +- +-&codec { +- allwinner,audio-routing = +- "Line Out", "LINEOUT", +- "MIC1", "Mic", +- "Mic", "MBIAS"; +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <®_vdd_cpux>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&ehci3 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_rgmii_pins>; +- phy-supply = <®_gmac_3v3>; +- phy-handle = <&ext_rgmii_phy>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&external_mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&ir { +- pinctrl-names = "default"; +- pinctrl-0 = <&r_ir_rx_pin>; +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-&ohci3 { +- status = "okay"; +-}; +- +-&r_i2c { +- status = "okay"; +- +- reg_vdd_cpux: regulator@65 { +- compatible = "silergy,sy8106a"; +- reg = <0x65>; +- regulator-name = "vdd-cpux"; +- silergy,fixed-microvolt = <1100000>; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1400000>; +- regulator-ramp-delay = <200>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- status = "disabled"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "disabled"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- /* USB Type-A ports' VBUS is always on */ +- usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-orangepi-prime.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-orangepi-prime.dts +deleted file mode 100644 +index 74e0444af19b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-orangepi-prime.dts ++++ /dev/null +@@ -1,213 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2017 Icenowy Zheng +-// Based on sun50i-h5-orangepi-pc2.dts, which is: +-// Copyright (C) 2016 ARM Ltd. +- +-/dts-v1/; +-#include "sun50i-h5.dtsi" +- +-#include +-#include +- +-/ { +- model = "Xunlong Orange Pi Prime"; +- compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5"; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "orangepi:green:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- led-1 { +- label = "orangepi:red:status"; +- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- r-gpio-keys { +- compatible = "gpio-keys"; +- +- sw4 { +- label = "sw4"; +- linux,code = ; +- gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- enable-active-high; +- gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; +- }; +- +- reg_vcc3v3: vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_usb0_vbus: usb0-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb0-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ +- status = "okay"; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pio 2 14 GPIO_ACTIVE_LOW>; /* PC14 */ +- }; +-}; +- +-&codec { +- allwinner,audio-routing = +- "Line Out", "LINEOUT", +- "MIC1", "Mic", +- "Mic", "MBIAS"; +- status = "okay"; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&ehci3 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_rgmii_pins>; +- phy-supply = <®_gmac_3v3>; +- phy-handle = <&ext_rgmii_phy>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&external_mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&ir { +- pinctrl-names = "default"; +- pinctrl-0 = <&r_ir_rx_pin>; +- status = "okay"; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-&ohci3 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- status = "disabled"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "disabled"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usbphy { +- /* USB Type-A ports' VBUS is always on */ +- usb0_id_det-gpios = <&pio 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */ +- usb0_vbus-supply = <®_usb0_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-orangepi-zero-plus.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-orangepi-zero-plus.dts +deleted file mode 100644 +index 7ec5ac850a0d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-orangepi-zero-plus.dts ++++ /dev/null +@@ -1,140 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2016 ARM Ltd. +-// Copyright (C) 2018 Hauke Mehrtens +- +-/dts-v1/; +-#include "sun50i-h5.dtsi" +- +-#include +-#include +-#include +- +-/ { +- model = "Xunlong Orange Pi Zero Plus"; +- compatible = "xunlong,orangepi-zero-plus", "allwinner,sun50i-h5"; +- +- reg_vcc3v3: vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- aliases { +- ethernet0 = &emac; +- ethernet1 = &rtl8189ftv; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "orangepi:green:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ +- default-state = "on"; +- }; +- +- led-1 { +- label = "orangepi:red:status"; +- gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */ +- }; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- enable-active-high; +- gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ +- }; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&emac_rgmii_pins>; +- phy-supply = <®_gmac_3v3>; +- phy-handle = <&ext_rgmii_phy>; +- phy-mode = "rgmii-id"; +- status = "okay"; +-}; +- +-&external_mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- /* +- * Explicitly define the sdio device, so that we can add an ethernet +- * alias for it (which e.g. makes u-boot set a mac-address). +- */ +- rtl8189ftv: sdio_wifi@1 { +- reg = <1>; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mxicy,mx25l1606e", "winbond,w25q128"; +- reg = <0>; +- spi-max-frequency = <40000000>; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usbphy { +- /* USB Type-A ports' VBUS is always on */ +- usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-orangepi-zero-plus2.dts +deleted file mode 100644 +index 22530ace12d5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5-orangepi-zero-plus2.dts ++++ /dev/null +@@ -1,143 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2017 Jagan Teki +- +-/dts-v1/; +- +-#include "sun50i-h5.dtsi" +- +-#include +- +-/ { +- model = "OrangePi Zero Plus2"; +- compatible = "xunlong,orangepi-zero-plus2", "allwinner,sun50i-h5"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "orangepi:green:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- led-1 { +- label = "orangepi:red:status"; +- gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- reg_vcc3v3: vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ +- post-power-on-delay-ms = <200>; +- }; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_vcc3v3>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc3v3>; +- vqmmc-supply = <®_vcc3v3>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&r_pio>; +- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&mmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_8bit_pins>; +- vmmc-supply = <®_vcc3v3>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pa_pins>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; +- status = "okay"; +-}; +- +-&usb_otg { +- /* +- * According to schematics CN1 MicroUSB port can be used to take +- * external 5V to power up the board VBUS. On the contrary CN1 MicroUSB +- * port cannot provide power externally even if the board is powered +- * via GPIO pins. It thus makes sense to force peripheral mode. +- */ +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usbphy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5.dtsi b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5.dtsi +deleted file mode 100644 +index 9988e87ea7b3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h5.dtsi ++++ /dev/null +@@ -1,270 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2016 ARM Ltd. +- +-#include +- +-#include +- +-/ { +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0>; +- enable-method = "psci"; +- clocks = <&ccu CLK_CPUX>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <1>; +- enable-method = "psci"; +- clocks = <&ccu CLK_CPUX>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <2>; +- enable-method = "psci"; +- clocks = <&ccu CLK_CPUX>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <3>; +- enable-method = "psci"; +- clocks = <&ccu CLK_CPUX>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- #cooling-cells = <2>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- arm,no-tick-in-suspend; +- interrupts = , +- , +- , +- ; +- }; +- +- soc { +- syscon: system-control@1c00000 { +- compatible = "allwinner,sun50i-h5-system-control"; +- reg = <0x01c00000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- sram_c1: sram@18000 { +- compatible = "mmio-sram"; +- reg = <0x00018000 0x1c000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00018000 0x1c000>; +- +- ve_sram: sram-section@0 { +- compatible = "allwinner,sun50i-h5-sram-c1", +- "allwinner,sun4i-a10-sram-c1"; +- reg = <0x000000 0x1c000>; +- }; +- }; +- }; +- +- video-codec@1c0e000 { +- compatible = "allwinner,sun50i-h5-video-engine"; +- reg = <0x01c0e000 0x1000>; +- clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, +- <&ccu CLK_DRAM_VE>; +- clock-names = "ahb", "mod", "ram"; +- resets = <&ccu RST_BUS_VE>; +- interrupts = ; +- allwinner,sram = <&ve_sram 1>; +- }; +- +- crypto: crypto@1c15000 { +- compatible = "allwinner,sun50i-h5-crypto"; +- reg = <0x01c15000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; +- clock-names = "bus", "mod"; +- resets = <&ccu RST_BUS_CE>; +- }; +- +- deinterlace: deinterlace@1e00000 { +- compatible = "allwinner,sun8i-h3-deinterlace"; +- reg = <0x01e00000 0x20000>; +- clocks = <&ccu CLK_BUS_DEINTERLACE>, +- <&ccu CLK_DEINTERLACE>, +- <&ccu CLK_DRAM_DEINTERLACE>; +- clock-names = "bus", "mod", "ram"; +- resets = <&ccu RST_BUS_DEINTERLACE>; +- interrupts = ; +- interconnects = <&mbus 9>; +- interconnect-names = "dma-mem"; +- }; +- +- mali: gpu@1e80000 { +- compatible = "allwinner,sun50i-h5-mali", "arm,mali-450"; +- reg = <0x01e80000 0x30000>; +- /* +- * While the datasheet lists an interrupt for the +- * PMU, the actual silicon does not have the PMU +- * block. Reads all return zero, and writes are +- * ignored. +- */ +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "gp", +- "gpmmu", +- "pp", +- "pp0", +- "ppmmu0", +- "pp1", +- "ppmmu1", +- "pp2", +- "ppmmu2", +- "pp3", +- "ppmmu3"; +- clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; +- clock-names = "bus", "core"; +- resets = <&ccu RST_BUS_GPU>; +- +- assigned-clocks = <&ccu CLK_GPU>; +- assigned-clock-rates = <384000000>; +- }; +- +- ths: thermal-sensor@1c25000 { +- compatible = "allwinner,sun50i-h5-ths"; +- reg = <0x01c25000 0x400>; +- interrupts = ; +- resets = <&ccu RST_BUS_THS>; +- clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; +- clock-names = "bus", "mod"; +- nvmem-cells = <&ths_calibration>; +- nvmem-cell-names = "calibration"; +- #thermal-sensor-cells = <1>; +- }; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&ths 0>; +- +- trips { +- cpu_hot_trip: cpu-hot { +- temperature = <80000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_very_hot_trip: cpu-very-hot { +- temperature = <100000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- cpu-hot-limit { +- trip = <&cpu_hot_trip>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- gpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&ths 1>; +- }; +- }; +-}; +- +-&ccu { +- compatible = "allwinner,sun50i-h5-ccu"; +-}; +- +-&display_clocks { +- compatible = "allwinner,sun50i-h5-de2-clk"; +-}; +- +-&mmc0 { +- compatible = "allwinner,sun50i-h5-mmc", +- "allwinner,sun50i-a64-mmc"; +- clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; +- clock-names = "ahb", "mmc"; +-}; +- +-&mmc1 { +- compatible = "allwinner,sun50i-h5-mmc", +- "allwinner,sun50i-a64-mmc"; +- clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; +- clock-names = "ahb", "mmc"; +-}; +- +-&mmc2 { +- compatible = "allwinner,sun50i-h5-emmc", +- "allwinner,sun50i-a64-emmc"; +- clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; +- clock-names = "ahb", "mmc"; +-}; +- +-&pio { +- interrupts = , +- , +- ; +- compatible = "allwinner,sun50i-h5-pinctrl"; +-}; +- +-&rtc { +- compatible = "allwinner,sun50i-h5-rtc"; +-}; +- +-&sid { +- compatible = "allwinner,sun50i-h5-sid"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-beelink-gs1.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-beelink-gs1.dts +deleted file mode 100644 +index 6249e9e02928..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-beelink-gs1.dts ++++ /dev/null +@@ -1,314 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2019 Clément Péron +- +-/dts-v1/; +- +-#include "sun50i-h6.dtsi" +-#include "sun50i-h6-cpu-opp.dtsi" +- +-#include +- +-/ { +- model = "Beelink GS1"; +- compatible = "azw,beelink-gs1", "allwinner,sun50i-h6"; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- ext_osc32k: ext_osc32k_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-output-names = "ext_osc32k"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led { +- label = "beelink:white:power"; +- gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ +- default-state = "on"; +- }; +- }; +- +- reg_vcc5v: vcc5v { +- /* board wide 5V supply directly from the DC jack */ +- compatible = "regulator-fixed"; +- regulator-name = "vcc-5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- sound-spdif { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "sun50i-h6-spdif"; +- +- simple-audio-card,cpu { +- sound-dai = <&spdif>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&spdif_out>; +- }; +- }; +- +- spdif_out: spdif-out { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdca>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&dwc3 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&ext_rgmii_pins>; +- phy-mode = "rgmii-id"; +- phy-handle = <&ext_rgmii_phy>; +- phy-supply = <®_aldo2>; +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <®_dcdcc>; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_cldo1>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&mmc2 { +- vmmc-supply = <®_cldo1>; +- vqmmc-supply = <®_bldo2>; +- non-removable; +- cap-mmc-hw-reset; +- bus-width = <8>; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&pio { +- vcc-pd-supply = <®_cldo1>; +- vcc-pg-supply = <®_aldo1>; +-}; +- +-&r_ir { +- linux,rc-map-name = "rc-beelink-gs1"; +- status = "okay"; +-}; +- +-&r_pio { +- /* +- * FIXME: We can't add that supply for now since it would +- * create a circular dependency between pinctrl, the regulator +- * and the RSB Bus. +- * +- * vcc-pl-supply = <®_aldo1>; +- */ +- vcc-pm-supply = <®_aldo1>; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp805: pmic@745 { +- compatible = "x-powers,axp805", "x-powers,axp806"; +- reg = <0x745>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- x-powers,self-working-mode; +- vina-supply = <®_vcc5v>; +- vinb-supply = <®_vcc5v>; +- vinc-supply = <®_vcc5v>; +- vind-supply = <®_vcc5v>; +- vine-supply = <®_vcc5v>; +- aldoin-supply = <®_vcc5v>; +- bldoin-supply = <®_vcc5v>; +- cldoin-supply = <®_vcc5v>; +- +- regulators { +- reg_aldo1: aldo1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pl"; +- }; +- +- reg_aldo2: aldo2 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-ac200"; +- regulator-enable-ramp-delay = <100000>; +- }; +- +- reg_aldo3: aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc25-dram"; +- }; +- +- reg_bldo1: bldo1 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-bias-pll"; +- }; +- +- reg_bldo2: bldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-efuse-pcie-hdmi-io"; +- }; +- +- reg_bldo3: bldo3 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-dcxoio"; +- }; +- +- bldo4 { +- /* unused */ +- }; +- +- reg_cldo1: cldo1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +- }; +- +- reg_cldo2: cldo2 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-1"; +- }; +- +- reg_cldo3: cldo3 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-2"; +- }; +- +- reg_dcdca: dcdca { +- regulator-always-on; +- regulator-min-microvolt = <810000>; +- regulator-max-microvolt = <1160000>; +- regulator-ramp-delay = <2500>; +- regulator-name = "vdd-cpu"; +- }; +- +- reg_dcdcc: dcdcc { +- regulator-enable-ramp-delay = <32000>; +- regulator-min-microvolt = <810000>; +- regulator-max-microvolt = <1080000>; +- regulator-ramp-delay = <2500>; +- regulator-name = "vdd-gpu"; +- }; +- +- reg_dcdcd: dcdcd { +- regulator-always-on; +- regulator-min-microvolt = <960000>; +- regulator-max-microvolt = <960000>; +- regulator-name = "vdd-sys"; +- }; +- +- reg_dcdce: dcdce { +- regulator-always-on; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-dram"; +- }; +- +- sw { +- /* unused */ +- }; +- }; +- }; +-}; +- +-&spdif { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ph_pins>; +- status = "okay"; +-}; +- +-&usb2otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb2phy { +- usb0_vbus-supply = <®_vcc5v>; +- status = "okay"; +-}; +- +-&usb3phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-cpu-opp.dtsi b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-cpu-opp.dtsi +deleted file mode 100644 +index 0baf0f8e4d27..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-cpu-opp.dtsi ++++ /dev/null +@@ -1,117 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2020 Ondrej Jirman +-// Copyright (C) 2020 Clément Péron +- +-/ { +- cpu_opp_table: opp-table-cpu { +- compatible = "allwinner,sun50i-h6-operating-points"; +- nvmem-cells = <&cpu_speed_grade>; +- opp-shared; +- +- opp-480000000 { +- clock-latency-ns = <244144>; /* 8 32k periods */ +- opp-hz = /bits/ 64 <480000000>; +- +- opp-microvolt-speed0 = <880000 880000 1200000>; +- opp-microvolt-speed1 = <820000 820000 1200000>; +- opp-microvolt-speed2 = <820000 820000 1200000>; +- }; +- +- opp-720000000 { +- clock-latency-ns = <244144>; /* 8 32k periods */ +- opp-hz = /bits/ 64 <720000000>; +- +- opp-microvolt-speed0 = <880000 880000 1200000>; +- opp-microvolt-speed1 = <820000 820000 1200000>; +- opp-microvolt-speed2 = <820000 820000 1200000>; +- }; +- +- opp-816000000 { +- clock-latency-ns = <244144>; /* 8 32k periods */ +- opp-hz = /bits/ 64 <816000000>; +- +- opp-microvolt-speed0 = <880000 880000 1200000>; +- opp-microvolt-speed1 = <820000 820000 1200000>; +- opp-microvolt-speed2 = <820000 820000 1200000>; +- }; +- +- opp-888000000 { +- clock-latency-ns = <244144>; /* 8 32k periods */ +- opp-hz = /bits/ 64 <888000000>; +- +- opp-microvolt-speed0 = <880000 880000 1200000>; +- opp-microvolt-speed1 = <820000 820000 1200000>; +- opp-microvolt-speed2 = <820000 820000 1200000>; +- }; +- +- opp-1080000000 { +- clock-latency-ns = <244144>; /* 8 32k periods */ +- opp-hz = /bits/ 64 <1080000000>; +- +- opp-microvolt-speed0 = <940000 940000 1200000>; +- opp-microvolt-speed1 = <880000 880000 1200000>; +- opp-microvolt-speed2 = <880000 880000 1200000>; +- }; +- +- opp-1320000000 { +- clock-latency-ns = <244144>; /* 8 32k periods */ +- opp-hz = /bits/ 64 <1320000000>; +- +- opp-microvolt-speed0 = <1000000 1000000 1200000>; +- opp-microvolt-speed1 = <940000 940000 1200000>; +- opp-microvolt-speed2 = <940000 940000 1200000>; +- }; +- +- opp-1488000000 { +- clock-latency-ns = <244144>; /* 8 32k periods */ +- opp-hz = /bits/ 64 <1488000000>; +- +- opp-microvolt-speed0 = <1060000 1060000 1200000>; +- opp-microvolt-speed1 = <1000000 1000000 1200000>; +- opp-microvolt-speed2 = <1000000 1000000 1200000>; +- }; +- +- opp-1608000000 { +- clock-latency-ns = <244144>; /* 8 32k periods */ +- opp-hz = /bits/ 64 <1608000000>; +- +- opp-microvolt-speed0 = <1090000 1090000 1200000>; +- opp-microvolt-speed1 = <1030000 1030000 1200000>; +- opp-microvolt-speed2 = <1030000 1030000 1200000>; +- }; +- +- opp-1704000000 { +- clock-latency-ns = <244144>; /* 8 32k periods */ +- opp-hz = /bits/ 64 <1704000000>; +- +- opp-microvolt-speed0 = <1120000 1120000 1200000>; +- opp-microvolt-speed1 = <1060000 1060000 1200000>; +- opp-microvolt-speed2 = <1060000 1060000 1200000>; +- }; +- +- opp-1800000000 { +- clock-latency-ns = <244144>; /* 8 32k periods */ +- opp-hz = /bits/ 64 <1800000000>; +- +- opp-microvolt-speed0 = <1160000 1160000 1200000>; +- opp-microvolt-speed1 = <1100000 1100000 1200000>; +- opp-microvolt-speed2 = <1100000 1100000 1200000>; +- }; +- }; +-}; +- +-&cpu0 { +- operating-points-v2 = <&cpu_opp_table>; +-}; +- +-&cpu1 { +- operating-points-v2 = <&cpu_opp_table>; +-}; +- +-&cpu2 { +- operating-points-v2 = <&cpu_opp_table>; +-}; +- +-&cpu3 { +- operating-points-v2 = <&cpu_opp_table>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-orangepi-3.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-orangepi-3.dts +deleted file mode 100644 +index c45d7b7fb39a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-orangepi-3.dts ++++ /dev/null +@@ -1,345 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2019 Ondřej Jirman +- +-/dts-v1/; +- +-#include "sun50i-h6.dtsi" +-#include "sun50i-h6-cpu-opp.dtsi" +- +-#include +- +-/ { +- model = "OrangePi 3"; +- compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- ext_osc32k: ext_osc32k_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-output-names = "ext_osc32k"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "orangepi:red:power"; +- gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ +- default-state = "on"; +- }; +- +- led-1 { +- label = "orangepi:green:status"; +- gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ +- }; +- }; +- +- reg_vcc5v: vcc5v { +- /* board wide 5V supply directly from the DC jack */ +- compatible = "regulator-fixed"; +- regulator-name = "vcc-5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_vcc33_wifi: vcc33-wifi { +- /* Always on 3.3V regulator for WiFi and BT */ +- compatible = "regulator-fixed"; +- regulator-name = "vcc33-wifi"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- vin-supply = <®_vcc5v>; +- }; +- +- reg_vcc_wifi_io: vcc-wifi-io { +- /* Always on 1.8V/300mA regulator for WiFi and BT IO */ +- compatible = "regulator-fixed"; +- regulator-name = "vcc-wifi-io"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- vin-supply = <®_vcc33_wifi>; +- }; +- +- wifi_pwrseq: wifi-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&rtc 1>; +- clock-names = "ext_clock"; +- reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ +- post-power-on-delay-ms = <200>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdca>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&dwc3 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci3 { +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <®_dcdcc>; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_cldo1>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +- bus-width = <4>; +- status = "okay"; +-}; +- +-&mmc1 { +- vmmc-supply = <®_vcc33_wifi>; +- vqmmc-supply = <®_vcc_wifi_io>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- brcm: sdio-wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&r_pio>; +- interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-&mmc2 { +- vmmc-supply = <®_cldo1>; +- vqmmc-supply = <®_bldo2>; +- cap-mmc-hw-reset; +- non-removable; +- bus-width = <8>; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci3 { +- status = "okay"; +-}; +- +-&pio { +- vcc-pc-supply = <®_bldo2>; +- vcc-pd-supply = <®_cldo1>; +- vcc-pg-supply = <®_vcc_wifi_io>; +-}; +- +-&r_ir { +- status = "okay"; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp805: pmic@745 { +- compatible = "x-powers,axp805", "x-powers,axp806"; +- reg = <0x745>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- x-powers,self-working-mode; +- vina-supply = <®_vcc5v>; +- vinb-supply = <®_vcc5v>; +- vinc-supply = <®_vcc5v>; +- vind-supply = <®_vcc5v>; +- vine-supply = <®_vcc5v>; +- aldoin-supply = <®_vcc5v>; +- bldoin-supply = <®_vcc5v>; +- cldoin-supply = <®_vcc5v>; +- +- regulators { +- reg_aldo1: aldo1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pl-led-ir"; +- }; +- +- reg_aldo2: aldo2 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc33-audio-tv-ephy-mac"; +- }; +- +- /* ALDO3 is shorted to CLDO1 */ +- reg_aldo3: aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1"; +- }; +- +- reg_bldo1: bldo1 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc18-dram-bias-pll"; +- }; +- +- reg_bldo2: bldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-efuse-pcie-hdmi-pc"; +- }; +- +- bldo3 { +- /* unused */ +- }; +- +- bldo4 { +- /* unused */ +- }; +- +- reg_cldo1: cldo1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2"; +- }; +- +- cldo2 { +- /* unused */ +- }; +- +- cldo3 { +- /* unused */ +- }; +- +- reg_dcdca: dcdca { +- regulator-always-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1160000>; +- regulator-ramp-delay = <2500>; +- regulator-name = "vdd-cpu"; +- }; +- +- reg_dcdcc: dcdcc { +- regulator-enable-ramp-delay = <32000>; +- regulator-min-microvolt = <810000>; +- regulator-max-microvolt = <1080000>; +- regulator-ramp-delay = <2500>; +- regulator-name = "vdd-gpu"; +- }; +- +- reg_dcdcd: dcdcd { +- regulator-always-on; +- regulator-min-microvolt = <960000>; +- regulator-max-microvolt = <960000>; +- regulator-name = "vdd-sys"; +- }; +- +- reg_dcdce: dcdce { +- regulator-always-on; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-dram"; +- }; +- +- sw { +- /* unused */ +- }; +- }; +- }; +-}; +- +-&rtc { +- clocks = <&ext_osc32k>; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ph_pins>; +- status = "okay"; +-}; +- +-/* There's the BT part of the AP6256 connected to that UART */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm4345c5"; +- clocks = <&rtc 1>; +- clock-names = "lpo"; +- device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ +- host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ +- shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ +- max-speed = <1500000>; +- }; +-}; +- +-&usb2otg { +- /* +- * This board doesn't have a controllable VBUS even though it +- * does have an ID pin. Using it as anything but a USB host is +- * unsafe. +- */ +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb2phy { +- usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */ +- usb0_vbus-supply = <®_vcc5v>; +- usb3_vbus-supply = <®_vcc5v>; +- status = "okay"; +-}; +- +-&usb3phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-orangepi-lite2.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-orangepi-lite2.dts +deleted file mode 100644 +index e8770858b5d0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-orangepi-lite2.dts ++++ /dev/null +@@ -1,74 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2018 Jagan Teki +- +-#include "sun50i-h6-orangepi.dtsi" +- +-/ { +- model = "OrangePi Lite2"; +- compatible = "xunlong,orangepi-lite2", "allwinner,sun50i-h6"; +- +- aliases { +- serial1 = &uart1; /* BT-UART */ +- }; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&rtc 1>; +- clock-names = "ext_clock"; +- reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ +- post-power-on-delay-ms = <200>; +- }; +-}; +- +-&mmc1 { +- vmmc-supply = <®_cldo2>; +- vqmmc-supply = <®_bldo3>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +- +- brcm: sdio-wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&r_pio>; +- interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ +- interrupt-names = "host-wake"; +- }; +-}; +- +-®_cldo2 { +- /* +- * This regulator is connected with CLDO3. +- * Before the kernel can support synchronized +- * enable of coupled regulators, keep them +- * both always on as a ugly hack. +- */ +- regulator-always-on; +-}; +- +-®_cldo3 { +- /* +- * This regulator is connected with CLDO2. +- * See the comments for CLDO2. +- */ +- regulator-always-on; +-}; +- +-/* There's the BT part of the AP6255 connected to that UART */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm4345c5"; +- clocks = <&rtc 1>; +- clock-names = "lpo"; +- device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ +- host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ +- shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ +- max-speed = <1500000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-orangepi-one-plus.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-orangepi-one-plus.dts +deleted file mode 100644 +index 29a081e72a9b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-orangepi-one-plus.dts ++++ /dev/null +@@ -1,43 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2018 Amarula Solutions +-// Author: Jagan Teki +- +-#include "sun50i-h6-orangepi.dtsi" +- +-/ { +- model = "OrangePi One Plus"; +- compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6"; +- +- aliases { +- ethernet0 = &emac; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc-gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- enable-active-high; +- gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ +- vin-supply = <®_aldo2>; +- }; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&ext_rgmii_pins>; +- phy-mode = "rgmii-id"; +- phy-handle = <&ext_rgmii_phy>; +- phy-supply = <®_gmac_3v3>; +- allwinner,rx-delay-ps = <200>; +- allwinner,tx-delay-ps = <200>; +- status = "okay"; +-}; +- +-&mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-orangepi.dtsi b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-orangepi.dtsi +deleted file mode 100644 +index 92745128fcfe..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-orangepi.dtsi ++++ /dev/null +@@ -1,268 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2018 Amarula Solutions +-// Author: Jagan Teki +- +-/dts-v1/; +- +-#include "sun50i-h6.dtsi" +- +-#include +- +-/ { +- model = "OrangePi One Plus"; +- compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- ext_osc32k: ext_osc32k_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-output-names = "ext_osc32k"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "orangepi:red:power"; +- gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ +- default-state = "on"; +- }; +- +- led-1 { +- label = "orangepi:green:status"; +- gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ +- }; +- }; +- +- reg_vcc5v: vcc5v { +- /* board wide 5V supply directly from the DC jack */ +- compatible = "regulator-fixed"; +- regulator-name = "vcc-5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci3 { +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <®_dcdcc>; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_cldo1>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci3 { +- status = "okay"; +-}; +- +-&pio { +- vcc-pc-supply = <®_bldo2>; +- vcc-pd-supply = <®_cldo1>; +- vcc-pg-supply = <®_aldo1>; +-}; +- +-&r_ir { +- status = "okay"; +-}; +- +-&r_pio { +- vcc-pm-supply = <®_bldo3>; +-}; +- +-&r_rsb { +- status = "okay"; +- +- axp805: pmic@745 { +- compatible = "x-powers,axp805", "x-powers,axp806"; +- reg = <0x745>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- x-powers,self-working-mode; +- vina-supply = <®_vcc5v>; +- vinb-supply = <®_vcc5v>; +- vinc-supply = <®_vcc5v>; +- vind-supply = <®_vcc5v>; +- vine-supply = <®_vcc5v>; +- aldoin-supply = <®_vcc5v>; +- bldoin-supply = <®_vcc5v>; +- cldoin-supply = <®_vcc5v>; +- +- regulators { +- reg_aldo1: aldo1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pl"; +- }; +- +- reg_aldo2: aldo2 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-ac200"; +- }; +- +- reg_aldo3: aldo3 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc25-dram"; +- }; +- +- reg_bldo1: bldo1 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-bias-pll"; +- }; +- +- reg_bldo2: bldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-efuse-pcie-hdmi-io"; +- }; +- +- reg_bldo3: bldo3 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-dcxoio"; +- }; +- +- bldo4 { +- /* unused */ +- }; +- +- reg_cldo1: cldo1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3"; +- }; +- +- reg_cldo2: cldo2 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-1"; +- }; +- +- reg_cldo3: cldo3 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-2"; +- }; +- +- reg_dcdca: dcdca { +- regulator-always-on; +- regulator-min-microvolt = <810000>; +- regulator-max-microvolt = <1080000>; +- regulator-name = "vdd-cpu"; +- }; +- +- reg_dcdcc: dcdcc { +- regulator-enable-ramp-delay = <32000>; +- regulator-min-microvolt = <810000>; +- regulator-max-microvolt = <1080000>; +- regulator-name = "vdd-gpu"; +- }; +- +- reg_dcdcd: dcdcd { +- regulator-always-on; +- regulator-min-microvolt = <960000>; +- regulator-max-microvolt = <960000>; +- regulator-name = "vdd-sys"; +- }; +- +- reg_dcdce: dcdce { +- regulator-always-on; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-dram"; +- }; +- +- sw { +- /* unused */ +- }; +- }; +- }; +-}; +- +-&rtc { +- clocks = <&ext_osc32k>; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ph_pins>; +- status = "okay"; +-}; +- +-&usb2otg { +- /* +- * OrangePi Lite 2 and One Plus, where this DT is used, don't +- * have a controllable VBUS even though they do have an ID pin. +- * Using it as anything but a USB host is unsafe. +- */ +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb2phy { +- usb0_id_det-gpios = <&pio 2 6 GPIO_ACTIVE_HIGH>; /* PC6 */ +- usb0_vbus-supply = <®_vcc5v>; +- usb3_vbus-supply = <®_vcc5v>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-pine-h64-model-b.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-pine-h64-model-b.dts +deleted file mode 100644 +index 686f58e77004..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-pine-h64-model-b.dts ++++ /dev/null +@@ -1,51 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ or MIT) +-/* +- * Copyright (C) 2019 Corentin LABBE +- */ +- +-#include "sun50i-h6-pine-h64.dts" +- +-/ { +- model = "Pine H64 model B"; +- compatible = "pine64,pine-h64-model-b", "allwinner,sun50i-h6"; +- +- /delete-node/ reg_gmac_3v3; +- +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ +- post-power-on-delay-ms = <200>; +- }; +-}; +- +-&hdmi_connector { +- /delete-property/ ddc-en-gpios; +-}; +- +-&emac { +- phy-supply = <®_aldo2>; +-}; +- +-&mmc1 { +- vmmc-supply = <®_cldo3>; +- vqmmc-supply = <®_aldo1>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- non-removable; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "realtek,rtl8723bs-bt"; +- device-wake-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ +- host-wake-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ +- enable-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ +- max-speed = <1500000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-pine-h64.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-pine-h64.dts +deleted file mode 100644 +index 1ffd68f43f87..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-pine-h64.dts ++++ /dev/null +@@ -1,334 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (c) 2017 Icenowy Zheng +- +-/dts-v1/; +- +-#include "sun50i-h6.dtsi" +-#include "sun50i-h6-cpu-opp.dtsi" +- +-#include +- +-/ { +- model = "Pine H64 model A"; +- compatible = "pine64,pine-h64", "allwinner,sun50i-h6"; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- spi0 = &spi0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- ext_osc32k: ext_osc32k_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-output-names = "ext_osc32k"; +- }; +- +- hdmi_connector: connector { +- compatible = "hdmi-connector"; +- type = "a"; +- ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "pine-h64:green:heartbeat"; +- gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ +- }; +- +- led-1 { +- label = "pine-h64:white:link"; +- gpios = <&r_pio 0 3 GPIO_ACTIVE_HIGH>; /* PL3 */ +- }; +- +- led-2 { +- label = "pine-h64:blue:status"; +- gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ +- }; +- }; +- +- reg_gmac_3v3: gmac-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc-gmac-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <100000>; +- gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_vbus: vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- startup-delay-us = <100000>; +- gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_dcdca>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci3 { +- status = "okay"; +-}; +- +-&emac { +- pinctrl-names = "default"; +- pinctrl-0 = <&ext_rgmii_pins>; +- phy-mode = "rgmii-id"; +- phy-handle = <&ext_rgmii_phy>; +- phy-supply = <®_gmac_3v3>; +- allwinner,rx-delay-ps = <200>; +- allwinner,tx-delay-ps = <200>; +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <®_dcdcc>; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&mmc0 { +- vmmc-supply = <®_cldo1>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&mmc2 { +- vmmc-supply = <®_cldo1>; +- vqmmc-supply = <®_bldo2>; +- non-removable; +- cap-mmc-hw-reset; +- mmc-hs200-1_8v; +- bus-width = <8>; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci3 { +- status = "okay"; +-}; +- +-&pio { +- vcc-pc-supply = <®_bldo2>; +- vcc-pd-supply = <®_cldo1>; +- vcc-pg-supply = <®_aldo1>; +-}; +- +-&r_i2c { +- status = "okay"; +- +- axp805: pmic@36 { +- compatible = "x-powers,axp805", "x-powers,axp806"; +- reg = <0x36>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- x-powers,self-working-mode; +- +- regulators { +- reg_aldo1: aldo1 { +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-pl"; +- }; +- +- reg_aldo2: aldo2 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-ac200"; +- regulator-enable-ramp-delay = <100000>; +- }; +- +- reg_aldo3: aldo3 { +- /* This regulator is connected with CLDO1 */ +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3-1"; +- }; +- +- reg_bldo1: bldo1 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-bias-pll"; +- }; +- +- reg_bldo2: bldo2 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-efuse-pcie-hdmi-io"; +- }; +- +- reg_bldo3: bldo3 { +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc-dcxoio"; +- }; +- +- bldo4 { +- /* unused */ +- }; +- +- reg_cldo1: cldo1 { +- /* This regulator is connected with ALDO3 */ +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-3v3-2"; +- }; +- +- reg_cldo2: cldo2 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-1"; +- }; +- +- reg_cldo3: cldo3 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc-wifi-2"; +- }; +- +- reg_dcdca: dcdca { +- regulator-always-on; +- regulator-min-microvolt = <810000>; +- regulator-max-microvolt = <1160000>; +- regulator-ramp-delay = <2500>; +- regulator-name = "vdd-cpu"; +- }; +- +- reg_dcdcc: dcdcc { +- regulator-enable-ramp-delay = <32000>; +- regulator-min-microvolt = <810000>; +- regulator-max-microvolt = <1080000>; +- regulator-ramp-delay = <2500>; +- regulator-name = "vdd-gpu"; +- }; +- +- reg_dcdcd: dcdcd { +- regulator-always-on; +- regulator-min-microvolt = <960000>; +- regulator-max-microvolt = <960000>; +- regulator-name = "vdd-sys"; +- }; +- +- reg_dcdce: dcdce { +- regulator-always-on; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "vcc-dram"; +- }; +- +- sw { +- /* unused */ +- }; +- }; +- }; +- +- pcf8563: rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- interrupt-parent = <&r_intc>; +- interrupts = ; +- #clock-cells = <0>; +- }; +-}; +- +-&r_ir { +- status = "okay"; +-}; +- +-&r_pio { +- vcc-pm-supply = <®_aldo1>; +-}; +- +-&rtc { +- clocks = <&ext_osc32k>; +-}; +- +-/* +- * The CS pin is shared with the MMC2 CMD pin, so we cannot have the SPI +- * flash and eMMC at the same time, as one of them would fail probing. +- * Disable SPI0 in here, to prefer the more useful eMMC. U-Boot can +- * fix this up in no eMMC is connected. +- */ +-&spi0 { +- pinctrl-0 = <&spi0_pins>, <&spi0_cs_pin>; +- pinctrl-names = "default"; +- status = "disabled"; +- +- flash@0 { +- compatible = "winbond,w25q128", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <4000000>; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ph_pins>; +- status = "okay"; +-}; +- +-&usb2otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb2phy { +- usb0_vbus-supply = <®_usb_vbus>; +- usb3_vbus-supply = <®_usb_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-tanix-tx6.dts b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-tanix-tx6.dts +deleted file mode 100644 +index 8f2a80f128de..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6-tanix-tx6.dts ++++ /dev/null +@@ -1,147 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (c) 2019 Jernej Skrabec +- +-/dts-v1/; +- +-#include "sun50i-h6.dtsi" +-#include "sun50i-h6-cpu-opp.dtsi" +- +-#include +- +-/ { +- model = "Tanix TX6"; +- compatible = "oranth,tanix-tx6", "allwinner,sun50i-h6"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- connector { +- compatible = "hdmi-connector"; +- ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- +- reg_vcc1v8: regulator-vcc1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- reg_vcc3v3: regulator-vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-cpu-gpu"; +- regulator-min-microvolt = <1135000>; +- regulator-max-microvolt = <1135000>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <®_vdd_cpu_gpu>; +-}; +- +-&de { +- status = "okay"; +-}; +- +-&dwc3 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci3 { +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <®_vdd_cpu_gpu>; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_vcc3v3>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&mmc2 { +- vmmc-supply = <®_vcc3v3>; +- vqmmc-supply = <®_vcc1v8>; +- bus-width = <8>; +- non-removable; +- cap-mmc-hw-reset; +- mmc-hs200-1_8v; +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci3 { +- status = "okay"; +-}; +- +-&pio { +- vcc-pc-supply = <®_vcc1v8>; +- vcc-pd-supply = <®_vcc3v3>; +- vcc-pg-supply = <®_vcc1v8>; +-}; +- +-&r_ir { +- linux,rc-map-name = "rc-tanix-tx5max"; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_ph_pins>; +- status = "okay"; +-}; +- +-&usb2otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb2phy { +- status = "okay"; +-}; +- +-&usb3phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6.dtsi b/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6.dtsi +deleted file mode 100644 +index 30d396e8c762..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/allwinner/sun50i-h6.dtsi ++++ /dev/null +@@ -1,1069 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2017 Icenowy Zheng +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0>; +- enable-method = "psci"; +- clocks = <&ccu CLK_CPUX>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <1>; +- enable-method = "psci"; +- clocks = <&ccu CLK_CPUX>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <2>; +- enable-method = "psci"; +- clocks = <&ccu CLK_CPUX>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <3>; +- enable-method = "psci"; +- clocks = <&ccu CLK_CPUX>; +- clock-latency-ns = <244144>; /* 8 32k periods */ +- #cooling-cells = <2>; +- }; +- }; +- +- de: display-engine { +- compatible = "allwinner,sun50i-h6-display-engine"; +- allwinner,pipelines = <&mixer0>; +- status = "disabled"; +- }; +- +- osc24M: osc24M_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "osc24M"; +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- arm,no-tick-in-suspend; +- interrupts = , +- , +- , +- ; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- bus@1000000 { +- compatible = "allwinner,sun50i-h6-de3", +- "allwinner,sun50i-a64-de2"; +- reg = <0x1000000 0x400000>; +- allwinner,sram = <&de2_sram 1>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x1000000 0x400000>; +- +- display_clocks: clock@0 { +- compatible = "allwinner,sun50i-h6-de3-clk"; +- reg = <0x0 0x10000>; +- clocks = <&ccu CLK_DE>, +- <&ccu CLK_BUS_DE>; +- clock-names = "mod", +- "bus"; +- resets = <&ccu RST_BUS_DE>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- mixer0: mixer@100000 { +- compatible = "allwinner,sun50i-h6-de3-mixer-0"; +- reg = <0x100000 0x100000>; +- clocks = <&display_clocks CLK_BUS_MIXER0>, +- <&display_clocks CLK_MIXER0>; +- clock-names = "bus", +- "mod"; +- resets = <&display_clocks RST_MIXER0>; +- iommus = <&iommu 0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mixer0_out: port@1 { +- reg = <1>; +- +- mixer0_out_tcon_top_mixer0: endpoint { +- remote-endpoint = <&tcon_top_mixer0_in_mixer0>; +- }; +- }; +- }; +- }; +- }; +- +- video-codec@1c0e000 { +- compatible = "allwinner,sun50i-h6-video-engine"; +- reg = <0x01c0e000 0x2000>; +- clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, +- <&ccu CLK_MBUS_VE>; +- clock-names = "ahb", "mod", "ram"; +- resets = <&ccu RST_BUS_VE>; +- interrupts = ; +- allwinner,sram = <&ve_sram 1>; +- iommus = <&iommu 3>; +- }; +- +- gpu: gpu@1800000 { +- compatible = "allwinner,sun50i-h6-mali", +- "arm,mali-t720"; +- reg = <0x01800000 0x4000>; +- interrupts = , +- , +- ; +- interrupt-names = "job", "mmu", "gpu"; +- clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; +- clock-names = "core", "bus"; +- resets = <&ccu RST_BUS_GPU>; +- status = "disabled"; +- }; +- +- crypto: crypto@1904000 { +- compatible = "allwinner,sun50i-h6-crypto"; +- reg = <0x01904000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>; +- clock-names = "bus", "mod", "ram"; +- resets = <&ccu RST_BUS_CE>; +- }; +- +- syscon: syscon@3000000 { +- compatible = "allwinner,sun50i-h6-system-control", +- "allwinner,sun50i-a64-system-control"; +- reg = <0x03000000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- sram_c: sram@28000 { +- compatible = "mmio-sram"; +- reg = <0x00028000 0x1e000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x00028000 0x1e000>; +- +- de2_sram: sram-section@0 { +- compatible = "allwinner,sun50i-h6-sram-c", +- "allwinner,sun50i-a64-sram-c"; +- reg = <0x0000 0x1e000>; +- }; +- }; +- +- sram_c1: sram@1a00000 { +- compatible = "mmio-sram"; +- reg = <0x01a00000 0x200000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x01a00000 0x200000>; +- +- ve_sram: sram-section@0 { +- compatible = "allwinner,sun50i-h6-sram-c1", +- "allwinner,sun4i-a10-sram-c1"; +- reg = <0x000000 0x200000>; +- }; +- }; +- }; +- +- ccu: clock@3001000 { +- compatible = "allwinner,sun50i-h6-ccu"; +- reg = <0x03001000 0x1000>; +- clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; +- clock-names = "hosc", "losc", "iosc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- dma: dma-controller@3002000 { +- compatible = "allwinner,sun50i-h6-dma"; +- reg = <0x03002000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; +- clock-names = "bus", "mbus"; +- dma-channels = <16>; +- dma-requests = <46>; +- resets = <&ccu RST_BUS_DMA>; +- #dma-cells = <1>; +- }; +- +- msgbox: mailbox@3003000 { +- compatible = "allwinner,sun50i-h6-msgbox", +- "allwinner,sun6i-a31-msgbox"; +- reg = <0x03003000 0x1000>; +- clocks = <&ccu CLK_BUS_MSGBOX>; +- resets = <&ccu RST_BUS_MSGBOX>; +- interrupts = ; +- #mbox-cells = <1>; +- }; +- +- sid: efuse@3006000 { +- compatible = "allwinner,sun50i-h6-sid"; +- reg = <0x03006000 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ths_calibration: thermal-sensor-calibration@14 { +- reg = <0x14 0x8>; +- }; +- +- cpu_speed_grade: cpu-speed-grade@1c { +- reg = <0x1c 0x4>; +- }; +- }; +- +- timer@3009000 { +- compatible = "allwinner,sun50i-h6-timer", +- "allwinner,sun8i-a23-timer"; +- reg = <0x03009000 0xa0>; +- interrupts = , +- ; +- clocks = <&osc24M>; +- }; +- +- watchdog: watchdog@30090a0 { +- compatible = "allwinner,sun50i-h6-wdt", +- "allwinner,sun6i-a31-wdt"; +- reg = <0x030090a0 0x20>; +- interrupts = ; +- clocks = <&osc24M>; +- /* Broken on some H6 boards */ +- status = "disabled"; +- }; +- +- pwm: pwm@300a000 { +- compatible = "allwinner,sun50i-h6-pwm"; +- reg = <0x0300a000 0x400>; +- clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; +- clock-names = "mod", "bus"; +- resets = <&ccu RST_BUS_PWM>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pio: pinctrl@300b000 { +- compatible = "allwinner,sun50i-h6-pinctrl"; +- reg = <0x0300b000 0x400>; +- interrupt-parent = <&r_intc>; +- interrupts = , +- , +- , +- ; +- clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; +- clock-names = "apb", "hosc", "losc"; +- gpio-controller; +- #gpio-cells = <3>; +- interrupt-controller; +- #interrupt-cells = <3>; +- +- ext_rgmii_pins: rgmii-pins { +- pins = "PD0", "PD1", "PD2", "PD3", "PD4", +- "PD5", "PD7", "PD8", "PD9", "PD10", +- "PD11", "PD12", "PD13", "PD19", "PD20"; +- function = "emac"; +- drive-strength = <40>; +- }; +- +- hdmi_pins: hdmi-pins { +- pins = "PH8", "PH9", "PH10"; +- function = "hdmi"; +- }; +- +- i2c0_pins: i2c0-pins { +- pins = "PD25", "PD26"; +- function = "i2c0"; +- }; +- +- i2c1_pins: i2c1-pins { +- pins = "PH5", "PH6"; +- function = "i2c1"; +- }; +- +- i2c2_pins: i2c2-pins { +- pins = "PD23", "PD24"; +- function = "i2c2"; +- }; +- +- mmc0_pins: mmc0-pins { +- pins = "PF0", "PF1", "PF2", "PF3", +- "PF4", "PF5"; +- function = "mmc0"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- /omit-if-no-ref/ +- mmc1_pins: mmc1-pins { +- pins = "PG0", "PG1", "PG2", "PG3", +- "PG4", "PG5"; +- function = "mmc1"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- mmc2_pins: mmc2-pins { +- pins = "PC1", "PC4", "PC5", "PC6", +- "PC7", "PC8", "PC9", "PC10", +- "PC11", "PC12", "PC13", "PC14"; +- function = "mmc2"; +- drive-strength = <30>; +- bias-pull-up; +- }; +- +- /omit-if-no-ref/ +- spi0_pins: spi0-pins { +- pins = "PC0", "PC2", "PC3"; +- function = "spi0"; +- }; +- +- /* pin shared with MMC2-CMD (eMMC) */ +- /omit-if-no-ref/ +- spi0_cs_pin: spi0-cs-pin { +- pins = "PC5"; +- function = "spi0"; +- }; +- +- /omit-if-no-ref/ +- spi1_pins: spi1-pins { +- pins = "PH4", "PH5", "PH6"; +- function = "spi1"; +- }; +- +- /omit-if-no-ref/ +- spi1_cs_pin: spi1-cs-pin { +- pins = "PH3"; +- function = "spi1"; +- }; +- +- spdif_tx_pin: spdif-tx-pin { +- pins = "PH7"; +- function = "spdif"; +- }; +- +- uart0_ph_pins: uart0-ph-pins { +- pins = "PH0", "PH1"; +- function = "uart0"; +- }; +- +- uart1_pins: uart1-pins { +- pins = "PG6", "PG7"; +- function = "uart1"; +- }; +- +- uart1_rts_cts_pins: uart1-rts-cts-pins { +- pins = "PG8", "PG9"; +- function = "uart1"; +- }; +- }; +- +- gic: interrupt-controller@3021000 { +- compatible = "arm,gic-400"; +- reg = <0x03021000 0x1000>, +- <0x03022000 0x2000>, +- <0x03024000 0x2000>, +- <0x03026000 0x2000>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- +- iommu: iommu@30f0000 { +- compatible = "allwinner,sun50i-h6-iommu"; +- reg = <0x030f0000 0x10000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_IOMMU>; +- resets = <&ccu RST_BUS_IOMMU>; +- #iommu-cells = <1>; +- }; +- +- mmc0: mmc@4020000 { +- compatible = "allwinner,sun50i-h6-mmc", +- "allwinner,sun50i-a64-mmc"; +- reg = <0x04020000 0x1000>; +- clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; +- clock-names = "ahb", "mmc"; +- resets = <&ccu RST_BUS_MMC0>; +- reset-names = "ahb"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- max-frequency = <150000000>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc1: mmc@4021000 { +- compatible = "allwinner,sun50i-h6-mmc", +- "allwinner,sun50i-a64-mmc"; +- reg = <0x04021000 0x1000>; +- clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; +- clock-names = "ahb", "mmc"; +- resets = <&ccu RST_BUS_MMC1>; +- reset-names = "ahb"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- max-frequency = <150000000>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc2: mmc@4022000 { +- compatible = "allwinner,sun50i-h6-emmc", +- "allwinner,sun50i-a64-emmc"; +- reg = <0x04022000 0x1000>; +- clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; +- clock-names = "ahb", "mmc"; +- resets = <&ccu RST_BUS_MMC2>; +- reset-names = "ahb"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins>; +- max-frequency = <150000000>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- uart0: serial@5000000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x05000000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART0>; +- resets = <&ccu RST_BUS_UART0>; +- status = "disabled"; +- }; +- +- uart1: serial@5000400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x05000400 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART1>; +- resets = <&ccu RST_BUS_UART1>; +- status = "disabled"; +- }; +- +- uart2: serial@5000800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x05000800 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART2>; +- resets = <&ccu RST_BUS_UART2>; +- status = "disabled"; +- }; +- +- uart3: serial@5000c00 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x05000c00 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&ccu CLK_BUS_UART3>; +- resets = <&ccu RST_BUS_UART3>; +- status = "disabled"; +- }; +- +- i2c0: i2c@5002000 { +- compatible = "allwinner,sun50i-h6-i2c", +- "allwinner,sun6i-a31-i2c"; +- reg = <0x05002000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C0>; +- resets = <&ccu RST_BUS_I2C0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c1: i2c@5002400 { +- compatible = "allwinner,sun50i-h6-i2c", +- "allwinner,sun6i-a31-i2c"; +- reg = <0x05002400 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C1>; +- resets = <&ccu RST_BUS_I2C1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c2: i2c@5002800 { +- compatible = "allwinner,sun50i-h6-i2c", +- "allwinner,sun6i-a31-i2c"; +- reg = <0x05002800 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2C2>; +- resets = <&ccu RST_BUS_I2C2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spi0: spi@5010000 { +- compatible = "allwinner,sun50i-h6-spi", +- "allwinner,sun8i-h3-spi"; +- reg = <0x05010000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; +- clock-names = "ahb", "mod"; +- dmas = <&dma 22>, <&dma 22>; +- dma-names = "rx", "tx"; +- resets = <&ccu RST_BUS_SPI0>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spi1: spi@5011000 { +- compatible = "allwinner,sun50i-h6-spi", +- "allwinner,sun8i-h3-spi"; +- reg = <0x05011000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; +- clock-names = "ahb", "mod"; +- dmas = <&dma 23>, <&dma 23>; +- dma-names = "rx", "tx"; +- resets = <&ccu RST_BUS_SPI1>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- emac: ethernet@5020000 { +- compatible = "allwinner,sun50i-h6-emac", +- "allwinner,sun50i-a64-emac"; +- syscon = <&syscon>; +- reg = <0x05020000 0x10000>; +- interrupts = ; +- interrupt-names = "macirq"; +- resets = <&ccu RST_BUS_EMAC>; +- reset-names = "stmmaceth"; +- clocks = <&ccu CLK_BUS_EMAC>; +- clock-names = "stmmaceth"; +- status = "disabled"; +- +- mdio: mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- i2s1: i2s@5091000 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun50i-h6-i2s"; +- reg = <0x05091000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; +- clock-names = "apb", "mod"; +- dmas = <&dma 4>, <&dma 4>; +- resets = <&ccu RST_BUS_I2S1>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spdif: spdif@5093000 { +- #sound-dai-cells = <0>; +- compatible = "allwinner,sun50i-h6-spdif"; +- reg = <0x05093000 0x400>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; +- clock-names = "apb", "spdif"; +- resets = <&ccu RST_BUS_SPDIF>; +- dmas = <&dma 2>; +- dma-names = "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spdif_tx_pin>; +- status = "disabled"; +- }; +- +- usb2otg: usb@5100000 { +- compatible = "allwinner,sun50i-h6-musb", +- "allwinner,sun8i-a33-musb"; +- reg = <0x05100000 0x0400>; +- clocks = <&ccu CLK_BUS_OTG>; +- resets = <&ccu RST_BUS_OTG>; +- interrupts = ; +- interrupt-names = "mc"; +- phys = <&usb2phy 0>; +- phy-names = "usb"; +- extcon = <&usb2phy 0>; +- status = "disabled"; +- }; +- +- usb2phy: phy@5100400 { +- compatible = "allwinner,sun50i-h6-usb-phy"; +- reg = <0x05100400 0x24>, +- <0x05101800 0x4>, +- <0x05311800 0x4>; +- reg-names = "phy_ctrl", +- "pmu0", +- "pmu3"; +- clocks = <&ccu CLK_USB_PHY0>, +- <&ccu CLK_USB_PHY3>; +- clock-names = "usb0_phy", +- "usb3_phy"; +- resets = <&ccu RST_USB_PHY0>, +- <&ccu RST_USB_PHY3>; +- reset-names = "usb0_reset", +- "usb3_reset"; +- status = "disabled"; +- #phy-cells = <1>; +- }; +- +- ehci0: usb@5101000 { +- compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; +- reg = <0x05101000 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_OHCI0>, +- <&ccu CLK_BUS_EHCI0>, +- <&ccu CLK_USB_OHCI0>; +- resets = <&ccu RST_BUS_OHCI0>, +- <&ccu RST_BUS_EHCI0>; +- phys = <&usb2phy 0>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci0: usb@5101400 { +- compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; +- reg = <0x05101400 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_OHCI0>, +- <&ccu CLK_USB_OHCI0>; +- resets = <&ccu RST_BUS_OHCI0>; +- phys = <&usb2phy 0>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- dwc3: usb@5200000 { +- compatible = "snps,dwc3"; +- reg = <0x05200000 0x10000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_XHCI>, +- <&ccu CLK_BUS_XHCI>, +- <&rtc 0>; +- clock-names = "ref", "bus_early", "suspend"; +- resets = <&ccu RST_BUS_XHCI>; +- /* +- * The datasheet of the chip doesn't declare the +- * peripheral function, and there's no boards known +- * to have a USB Type-B port routed to the port. +- * In addition, no one has tested the peripheral +- * function yet. +- * So set the dr_mode to "host" in the DTSI file. +- */ +- dr_mode = "host"; +- phys = <&usb3phy>; +- phy-names = "usb3-phy"; +- status = "disabled"; +- }; +- +- usb3phy: phy@5210000 { +- compatible = "allwinner,sun50i-h6-usb3-phy"; +- reg = <0x5210000 0x10000>; +- clocks = <&ccu CLK_USB_PHY1>; +- resets = <&ccu RST_USB_PHY1>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- ehci3: usb@5311000 { +- compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; +- reg = <0x05311000 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_OHCI3>, +- <&ccu CLK_BUS_EHCI3>, +- <&ccu CLK_USB_OHCI3>; +- resets = <&ccu RST_BUS_OHCI3>, +- <&ccu RST_BUS_EHCI3>; +- phys = <&usb2phy 3>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ohci3: usb@5311400 { +- compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; +- reg = <0x05311400 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_OHCI3>, +- <&ccu CLK_USB_OHCI3>; +- resets = <&ccu RST_BUS_OHCI3>; +- phys = <&usb2phy 3>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- hdmi: hdmi@6000000 { +- compatible = "allwinner,sun50i-h6-dw-hdmi"; +- reg = <0x06000000 0x10000>; +- reg-io-width = <1>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, +- <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, +- <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; +- clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", +- "hdcp-bus"; +- resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; +- reset-names = "ctrl", "hdcp"; +- phys = <&hdmi_phy>; +- phy-names = "phy"; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_pins>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- hdmi_in: port@0 { +- reg = <0>; +- +- hdmi_in_tcon_top: endpoint { +- remote-endpoint = <&tcon_top_hdmi_out_hdmi>; +- }; +- }; +- +- hdmi_out: port@1 { +- reg = <1>; +- }; +- }; +- }; +- +- hdmi_phy: hdmi-phy@6010000 { +- compatible = "allwinner,sun50i-h6-hdmi-phy"; +- reg = <0x06010000 0x10000>; +- clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; +- clock-names = "bus", "mod"; +- resets = <&ccu RST_BUS_HDMI>; +- reset-names = "phy"; +- #phy-cells = <0>; +- }; +- +- tcon_top: tcon-top@6510000 { +- compatible = "allwinner,sun50i-h6-tcon-top"; +- reg = <0x06510000 0x1000>; +- clocks = <&ccu CLK_BUS_TCON_TOP>, +- <&ccu CLK_TCON_TV0>; +- clock-names = "bus", +- "tcon-tv0"; +- clock-output-names = "tcon-top-tv0"; +- resets = <&ccu RST_BUS_TCON_TOP>; +- #clock-cells = <1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon_top_mixer0_in: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- tcon_top_mixer0_in_mixer0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&mixer0_out_tcon_top_mixer0>; +- }; +- }; +- +- tcon_top_mixer0_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tcon_top_mixer0_out_tcon_tv: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; +- }; +- }; +- +- tcon_top_hdmi_in: port@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- +- tcon_top_hdmi_in_tcon_tv: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&tcon_tv_out_tcon_top>; +- }; +- }; +- +- tcon_top_hdmi_out: port@5 { +- reg = <5>; +- +- tcon_top_hdmi_out_hdmi: endpoint { +- remote-endpoint = <&hdmi_in_tcon_top>; +- }; +- }; +- }; +- }; +- +- tcon_tv: lcd-controller@6515000 { +- compatible = "allwinner,sun50i-h6-tcon-tv", +- "allwinner,sun8i-r40-tcon-tv"; +- reg = <0x06515000 0x1000>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_TCON_TV0>, +- <&tcon_top CLK_TCON_TOP_TV0>; +- clock-names = "ahb", +- "tcon-ch1"; +- resets = <&ccu RST_BUS_TCON_TV0>; +- reset-names = "lcd"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- tcon_tv_in: port@0 { +- reg = <0>; +- +- tcon_tv_in_tcon_top_mixer0: endpoint { +- remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; +- }; +- }; +- +- tcon_tv_out: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- tcon_tv_out_tcon_top: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; +- }; +- }; +- }; +- }; +- +- rtc: rtc@7000000 { +- compatible = "allwinner,sun50i-h6-rtc"; +- reg = <0x07000000 0x400>; +- interrupt-parent = <&r_intc>; +- interrupts = , +- ; +- clock-output-names = "osc32k", "osc32k-out", "iosc"; +- #clock-cells = <1>; +- }; +- +- r_ccu: clock@7010000 { +- compatible = "allwinner,sun50i-h6-r-ccu"; +- reg = <0x07010000 0x400>; +- clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, +- <&ccu CLK_PLL_PERIPH0>; +- clock-names = "hosc", "losc", "iosc", "pll-periph"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- r_watchdog: watchdog@7020400 { +- compatible = "allwinner,sun50i-h6-wdt", +- "allwinner,sun6i-a31-wdt"; +- reg = <0x07020400 0x20>; +- interrupts = ; +- clocks = <&osc24M>; +- }; +- +- r_intc: interrupt-controller@7021000 { +- compatible = "allwinner,sun50i-h6-r-intc"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x07021000 0x400>; +- interrupts = ; +- }; +- +- r_pio: pinctrl@7022000 { +- compatible = "allwinner,sun50i-h6-r-pinctrl"; +- reg = <0x07022000 0x400>; +- interrupt-parent = <&r_intc>; +- interrupts = , +- ; +- clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; +- clock-names = "apb", "hosc", "losc"; +- gpio-controller; +- #gpio-cells = <3>; +- interrupt-controller; +- #interrupt-cells = <3>; +- +- r_i2c_pins: r-i2c-pins { +- pins = "PL0", "PL1"; +- function = "s_i2c"; +- }; +- +- r_ir_rx_pin: r-ir-rx-pin { +- pins = "PL9"; +- function = "s_cir_rx"; +- }; +- +- r_rsb_pins: r-rsb-pins { +- pins = "PL0", "PL1"; +- function = "s_rsb"; +- }; +- }; +- +- r_ir: ir@7040000 { +- compatible = "allwinner,sun50i-h6-ir", +- "allwinner,sun6i-a31-ir"; +- reg = <0x07040000 0x400>; +- interrupts = ; +- clocks = <&r_ccu CLK_R_APB1_IR>, +- <&r_ccu CLK_IR>; +- clock-names = "apb", "ir"; +- resets = <&r_ccu RST_R_APB1_IR>; +- pinctrl-names = "default"; +- pinctrl-0 = <&r_ir_rx_pin>; +- status = "disabled"; +- }; +- +- r_i2c: i2c@7081400 { +- compatible = "allwinner,sun50i-h6-i2c", +- "allwinner,sun6i-a31-i2c"; +- reg = <0x07081400 0x400>; +- interrupts = ; +- clocks = <&r_ccu CLK_R_APB2_I2C>; +- resets = <&r_ccu RST_R_APB2_I2C>; +- pinctrl-names = "default"; +- pinctrl-0 = <&r_i2c_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- r_rsb: rsb@7083000 { +- compatible = "allwinner,sun8i-a23-rsb"; +- reg = <0x07083000 0x400>; +- interrupts = ; +- clocks = <&r_ccu CLK_R_APB2_RSB>; +- clock-frequency = <3000000>; +- resets = <&r_ccu RST_R_APB2_RSB>; +- pinctrl-names = "default"; +- pinctrl-0 = <&r_rsb_pins>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- ths: thermal-sensor@5070400 { +- compatible = "allwinner,sun50i-h6-ths"; +- reg = <0x05070400 0x100>; +- interrupts = ; +- clocks = <&ccu CLK_BUS_THS>; +- clock-names = "bus"; +- resets = <&ccu RST_BUS_THS>; +- nvmem-cells = <&ths_calibration>; +- nvmem-cell-names = "calibration"; +- #thermal-sensor-cells = <1>; +- }; +- }; +- +- thermal-zones { +- cpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&ths 0>; +- +- trips { +- cpu_alert: cpu-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu-crit { +- temperature = <100000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- gpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&ths 1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/altera/Makefile b/scripts/dtc/include-prefixes/arm64/altera/Makefile +deleted file mode 100644 +index 4db83fbeb115..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/altera/Makefile ++++ /dev/null +@@ -1,3 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0-only +-dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_stratix10_socdk.dtb \ +- socfpga_stratix10_socdk_nand.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/altera/socfpga_stratix10.dtsi b/scripts/dtc/include-prefixes/arm64/altera/socfpga_stratix10.dtsi +deleted file mode 100644 +index d301ac0d406b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/altera/socfpga_stratix10.dtsi ++++ /dev/null +@@ -1,623 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright Altera Corporation (C) 2015. All rights reserved. +- */ +- +-/dts-v1/; +-#include +-#include +-#include +- +-/ { +- compatible = "altr,socfpga-stratix10"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- service_reserved: svcbuffer@0 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x0 0x0 0x1000000>; +- alignment = <0x1000>; +- no-map; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "psci"; +- reg = <0x0>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "psci"; +- reg = <0x1>; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "psci"; +- reg = <0x2>; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "psci"; +- reg = <0x3>; +- }; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = <0 170 4>, +- <0 171 4>, +- <0 172 4>, +- <0 173 4>; +- interrupt-affinity = <&cpu0>, +- <&cpu1>, +- <&cpu2>, +- <&cpu3>; +- interrupt-parent = <&intc>; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- intc: interrupt-controller@fffc1000 { +- compatible = "arm,gic-400", "arm,cortex-a15-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x0 0xfffc1000 0x0 0x1000>, +- <0x0 0xfffc2000 0x0 0x2000>, +- <0x0 0xfffc4000 0x0 0x2000>, +- <0x0 0xfffc6000 0x0 0x2000>; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- device_type = "soc"; +- interrupt-parent = <&intc>; +- ranges = <0 0 0 0xffffffff>; +- +- base_fpga_region { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- +- compatible = "fpga-region"; +- fpga-mgr = <&fpga_mgr>; +- }; +- +- clkmgr: clock-controller@ffd10000 { +- compatible = "intel,stratix10-clkmgr"; +- reg = <0xffd10000 0x1000>; +- #clock-cells = <1>; +- }; +- +- clocks { +- cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- }; +- +- cb_intosc_ls_clk: cb-intosc-ls-clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- }; +- +- f2s_free_clk: f2s-free-clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- }; +- +- osc1: osc1 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- }; +- +- qspi_clk: qspi-clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <200000000>; +- }; +- }; +- +- gmac0: ethernet@ff800000 { +- compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; +- reg = <0xff800000 0x2000>; +- interrupts = <0 90 4>; +- interrupt-names = "macirq"; +- mac-address = [00 00 00 00 00 00]; +- resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; +- reset-names = "stmmaceth", "stmmaceth-ocp"; +- clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; +- clock-names = "stmmaceth", "ptp_ref"; +- tx-fifo-depth = <16384>; +- rx-fifo-depth = <16384>; +- snps,multicast-filter-bins = <256>; +- iommus = <&smmu 1>; +- altr,sysmgr-syscon = <&sysmgr 0x44 0>; +- status = "disabled"; +- }; +- +- gmac1: ethernet@ff802000 { +- compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; +- reg = <0xff802000 0x2000>; +- interrupts = <0 91 4>; +- interrupt-names = "macirq"; +- mac-address = [00 00 00 00 00 00]; +- resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; +- reset-names = "stmmaceth", "stmmaceth-ocp"; +- clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; +- clock-names = "stmmaceth", "ptp_ref"; +- tx-fifo-depth = <16384>; +- rx-fifo-depth = <16384>; +- snps,multicast-filter-bins = <256>; +- iommus = <&smmu 2>; +- altr,sysmgr-syscon = <&sysmgr 0x48 8>; +- status = "disabled"; +- }; +- +- gmac2: ethernet@ff804000 { +- compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; +- reg = <0xff804000 0x2000>; +- interrupts = <0 92 4>; +- interrupt-names = "macirq"; +- mac-address = [00 00 00 00 00 00]; +- resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; +- reset-names = "stmmaceth", "stmmaceth-ocp"; +- clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; +- clock-names = "stmmaceth", "ptp_ref"; +- tx-fifo-depth = <16384>; +- rx-fifo-depth = <16384>; +- snps,multicast-filter-bins = <256>; +- iommus = <&smmu 3>; +- altr,sysmgr-syscon = <&sysmgr 0x4c 16>; +- status = "disabled"; +- }; +- +- gpio0: gpio@ffc03200 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dw-apb-gpio"; +- reg = <0xffc03200 0x100>; +- resets = <&rst GPIO0_RESET>; +- status = "disabled"; +- +- porta: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <24>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <0 110 4>; +- }; +- }; +- +- gpio1: gpio@ffc03300 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dw-apb-gpio"; +- reg = <0xffc03300 0x100>; +- resets = <&rst GPIO1_RESET>; +- status = "disabled"; +- +- portb: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <24>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <0 111 4>; +- }; +- }; +- +- i2c0: i2c@ffc02800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xffc02800 0x100>; +- interrupts = <0 103 4>; +- resets = <&rst I2C0_RESET>; +- clocks = <&clkmgr STRATIX10_L4_SP_CLK>; +- status = "disabled"; +- }; +- +- i2c1: i2c@ffc02900 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xffc02900 0x100>; +- interrupts = <0 104 4>; +- resets = <&rst I2C1_RESET>; +- clocks = <&clkmgr STRATIX10_L4_SP_CLK>; +- status = "disabled"; +- }; +- +- i2c2: i2c@ffc02a00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xffc02a00 0x100>; +- interrupts = <0 105 4>; +- resets = <&rst I2C2_RESET>; +- clocks = <&clkmgr STRATIX10_L4_SP_CLK>; +- status = "disabled"; +- }; +- +- i2c3: i2c@ffc02b00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xffc02b00 0x100>; +- interrupts = <0 106 4>; +- resets = <&rst I2C3_RESET>; +- clocks = <&clkmgr STRATIX10_L4_SP_CLK>; +- status = "disabled"; +- }; +- +- i2c4: i2c@ffc02c00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xffc02c00 0x100>; +- interrupts = <0 107 4>; +- resets = <&rst I2C4_RESET>; +- clocks = <&clkmgr STRATIX10_L4_SP_CLK>; +- status = "disabled"; +- }; +- +- mmc: dwmmc0@ff808000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "altr,socfpga-dw-mshc"; +- reg = <0xff808000 0x1000>; +- interrupts = <0 96 4>; +- fifo-depth = <0x400>; +- resets = <&rst SDMMC_RESET>; +- reset-names = "reset"; +- clocks = <&clkmgr STRATIX10_L4_MP_CLK>, +- <&clkmgr STRATIX10_SDMMC_CLK>; +- clock-names = "biu", "ciu"; +- iommus = <&smmu 5>; +- status = "disabled"; +- }; +- +- nand: nand-controller@ffb90000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "altr,socfpga-denali-nand"; +- reg = <0xffb90000 0x10000>, +- <0xffb80000 0x1000>; +- reg-names = "nand_data", "denali_reg"; +- interrupts = <0 97 4>; +- clocks = <&clkmgr STRATIX10_NAND_CLK>, +- <&clkmgr STRATIX10_NAND_X_CLK>, +- <&clkmgr STRATIX10_NAND_ECC_CLK>; +- clock-names = "nand", "nand_x", "ecc"; +- resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; +- status = "disabled"; +- }; +- +- ocram: sram@ffe00000 { +- compatible = "mmio-sram"; +- reg = <0xffe00000 0x100000>; +- }; +- +- pdma: pdma@ffda0000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0xffda0000 0x1000>; +- interrupts = <0 81 4>, +- <0 82 4>, +- <0 83 4>, +- <0 84 4>, +- <0 85 4>, +- <0 86 4>, +- <0 87 4>, +- <0 88 4>, +- <0 89 4>; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; +- clock-names = "apb_pclk"; +- resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; +- reset-names = "dma", "dma-ocp"; +- }; +- +- rst: rstmgr@ffd11000 { +- #reset-cells = <1>; +- compatible = "altr,stratix10-rst-mgr"; +- reg = <0xffd11000 0x1000>; +- }; +- +- smmu: iommu@fa000000 { +- compatible = "arm,mmu-500", "arm,smmu-v2"; +- reg = <0xfa000000 0x40000>; +- #global-interrupts = <2>; +- #iommu-cells = <1>; +- clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; +- clock-names = "iommu"; +- interrupt-parent = <&intc>; +- interrupts = <0 128 4>, /* Global Secure Fault */ +- <0 129 4>, /* Global Non-secure Fault */ +- /* Non-secure Context Interrupts (32) */ +- <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, +- <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, +- <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, +- <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, +- <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, +- <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, +- <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, +- <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; +- stream-match-mask = <0x7ff0>; +- status = "disabled"; +- }; +- +- spi0: spi@ffda4000 { +- compatible = "snps,dw-apb-ssi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xffda4000 0x1000>; +- interrupts = <0 99 4>; +- resets = <&rst SPIM0_RESET>; +- reset-names = "spi"; +- reg-io-width = <4>; +- num-cs = <4>; +- clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; +- status = "disabled"; +- }; +- +- spi1: spi@ffda5000 { +- compatible = "snps,dw-apb-ssi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xffda5000 0x1000>; +- interrupts = <0 100 4>; +- resets = <&rst SPIM1_RESET>; +- reset-names = "spi"; +- reg-io-width = <4>; +- num-cs = <4>; +- clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; +- status = "disabled"; +- }; +- +- sysmgr: sysmgr@ffd12000 { +- compatible = "altr,sys-mgr-s10","altr,sys-mgr"; +- reg = <0xffd12000 0x228>; +- }; +- +- /* Local timer */ +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = <1 13 0xf08>, +- <1 14 0xf08>, +- <1 11 0xf08>, +- <1 10 0xf08>; +- }; +- +- timer0: timer0@ffc03000 { +- compatible = "snps,dw-apb-timer"; +- interrupts = <0 113 4>; +- reg = <0xffc03000 0x100>; +- clocks = <&clkmgr STRATIX10_L4_SP_CLK>; +- clock-names = "timer"; +- }; +- +- timer1: timer1@ffc03100 { +- compatible = "snps,dw-apb-timer"; +- interrupts = <0 114 4>; +- reg = <0xffc03100 0x100>; +- clocks = <&clkmgr STRATIX10_L4_SP_CLK>; +- clock-names = "timer"; +- }; +- +- timer2: timer2@ffd00000 { +- compatible = "snps,dw-apb-timer"; +- interrupts = <0 115 4>; +- reg = <0xffd00000 0x100>; +- clocks = <&clkmgr STRATIX10_L4_SP_CLK>; +- clock-names = "timer"; +- }; +- +- timer3: timer3@ffd00100 { +- compatible = "snps,dw-apb-timer"; +- interrupts = <0 116 4>; +- reg = <0xffd00100 0x100>; +- clocks = <&clkmgr STRATIX10_L4_SP_CLK>; +- clock-names = "timer"; +- }; +- +- uart0: serial@ffc02000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0xffc02000 0x100>; +- interrupts = <0 108 4>; +- reg-shift = <2>; +- reg-io-width = <4>; +- resets = <&rst UART0_RESET>; +- clocks = <&clkmgr STRATIX10_L4_SP_CLK>; +- status = "disabled"; +- }; +- +- uart1: serial@ffc02100 { +- compatible = "snps,dw-apb-uart"; +- reg = <0xffc02100 0x100>; +- interrupts = <0 109 4>; +- reg-shift = <2>; +- reg-io-width = <4>; +- resets = <&rst UART1_RESET>; +- clocks = <&clkmgr STRATIX10_L4_SP_CLK>; +- status = "disabled"; +- }; +- +- usbphy0: usbphy@0 { +- #phy-cells = <0>; +- compatible = "usb-nop-xceiv"; +- status = "okay"; +- }; +- +- usb0: usb@ffb00000 { +- compatible = "snps,dwc2"; +- reg = <0xffb00000 0x40000>; +- interrupts = <0 93 4>; +- phys = <&usbphy0>; +- phy-names = "usb2-phy"; +- resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; +- reset-names = "dwc2", "dwc2-ecc"; +- clocks = <&clkmgr STRATIX10_USB_CLK>; +- iommus = <&smmu 6>; +- status = "disabled"; +- }; +- +- usb1: usb@ffb40000 { +- compatible = "snps,dwc2"; +- reg = <0xffb40000 0x40000>; +- interrupts = <0 94 4>; +- phys = <&usbphy0>; +- phy-names = "usb2-phy"; +- resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; +- reset-names = "dwc2", "dwc2-ecc"; +- clocks = <&clkmgr STRATIX10_USB_CLK>; +- iommus = <&smmu 7>; +- status = "disabled"; +- }; +- +- watchdog0: watchdog@ffd00200 { +- compatible = "snps,dw-wdt"; +- reg = <0xffd00200 0x100>; +- interrupts = <0 117 4>; +- resets = <&rst WATCHDOG0_RESET>; +- clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; +- status = "disabled"; +- }; +- +- watchdog1: watchdog@ffd00300 { +- compatible = "snps,dw-wdt"; +- reg = <0xffd00300 0x100>; +- interrupts = <0 118 4>; +- resets = <&rst WATCHDOG1_RESET>; +- clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; +- status = "disabled"; +- }; +- +- watchdog2: watchdog@ffd00400 { +- compatible = "snps,dw-wdt"; +- reg = <0xffd00400 0x100>; +- interrupts = <0 125 4>; +- resets = <&rst WATCHDOG2_RESET>; +- clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; +- status = "disabled"; +- }; +- +- watchdog3: watchdog@ffd00500 { +- compatible = "snps,dw-wdt"; +- reg = <0xffd00500 0x100>; +- interrupts = <0 126 4>; +- resets = <&rst WATCHDOG3_RESET>; +- clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; +- status = "disabled"; +- }; +- +- sdr: sdr@f8011100 { +- compatible = "altr,sdr-ctl", "syscon"; +- reg = <0xf8011100 0xc0>; +- }; +- +- eccmgr { +- compatible = "altr,socfpga-s10-ecc-manager", +- "altr,socfpga-a10-ecc-manager"; +- altr,sysmgr-syscon = <&sysmgr>; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupts = <0 15 4>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ranges; +- +- sdramedac { +- compatible = "altr,sdram-edac-s10"; +- altr,sdr-syscon = <&sdr>; +- interrupts = <16 4>; +- }; +- +- ocram-ecc@ff8cc000 { +- compatible = "altr,socfpga-s10-ocram-ecc", +- "altr,socfpga-a10-ocram-ecc"; +- reg = <0xff8cc000 0x100>; +- altr,ecc-parent = <&ocram>; +- interrupts = <1 4>; +- }; +- +- usb0-ecc@ff8c4000 { +- compatible = "altr,socfpga-s10-usb-ecc", +- "altr,socfpga-usb-ecc"; +- reg = <0xff8c4000 0x100>; +- altr,ecc-parent = <&usb0>; +- interrupts = <2 4>; +- }; +- +- emac0-rx-ecc@ff8c0000 { +- compatible = "altr,socfpga-s10-eth-mac-ecc", +- "altr,socfpga-eth-mac-ecc"; +- reg = <0xff8c0000 0x100>; +- altr,ecc-parent = <&gmac0>; +- interrupts = <4 4>; +- }; +- +- emac0-tx-ecc@ff8c0400 { +- compatible = "altr,socfpga-s10-eth-mac-ecc", +- "altr,socfpga-eth-mac-ecc"; +- reg = <0xff8c0400 0x100>; +- altr,ecc-parent = <&gmac0>; +- interrupts = <5 4>; +- }; +- +- }; +- +- qspi: spi@ff8d2000 { +- compatible = "cdns,qspi-nor"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xff8d2000 0x100>, +- <0xff900000 0x100000>; +- interrupts = <0 3 4>; +- cdns,fifo-depth = <128>; +- cdns,fifo-width = <4>; +- cdns,trigger-address = <0x00000000>; +- clocks = <&qspi_clk>; +- +- status = "disabled"; +- }; +- +- firmware { +- svc { +- compatible = "intel,stratix10-svc"; +- method = "smc"; +- memory-region = <&service_reserved>; +- +- fpga_mgr: fpga-mgr { +- compatible = "intel,stratix10-soc-fpga-mgr"; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/altera/socfpga_stratix10_socdk.dts b/scripts/dtc/include-prefixes/arm64/altera/socfpga_stratix10_socdk.dts +deleted file mode 100644 +index 46e558ab7729..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/altera/socfpga_stratix10_socdk.dts ++++ /dev/null +@@ -1,191 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright Altera Corporation (C) 2015. All rights reserved. +- */ +- +-#include "socfpga_stratix10.dtsi" +- +-/ { +- model = "SoCFPGA Stratix 10 SoCDK"; +- +- aliases { +- serial0 = &uart0; +- ethernet0 = &gmac0; +- ethernet1 = &gmac1; +- ethernet2 = &gmac2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- hps0 { +- label = "hps_led0"; +- gpios = <&portb 20 GPIO_ACTIVE_HIGH>; +- }; +- +- hps1 { +- label = "hps_led1"; +- gpios = <&portb 19 GPIO_ACTIVE_HIGH>; +- }; +- +- hps2 { +- label = "hps_led2"; +- gpios = <&portb 21 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- /* We expect the bootloader to fill in the reg */ +- reg = <0 0 0 0>; +- }; +- +- ref_033v: 033-v-ref { +- compatible = "regulator-fixed"; +- regulator-name = "0.33V"; +- regulator-min-microvolt = <330000>; +- regulator-max-microvolt = <330000>; +- }; +- +- soc { +- clocks { +- osc1 { +- clock-frequency = <25000000>; +- }; +- }; +- +- eccmgr { +- sdmmca-ecc@ff8c8c00 { +- compatible = "altr,socfpga-s10-sdmmc-ecc", +- "altr,socfpga-sdmmc-ecc"; +- reg = <0xff8c8c00 0x100>; +- altr,ecc-parent = <&mmc>; +- interrupts = <14 4>, +- <15 4>; +- }; +- }; +- }; +-}; +- +-&gpio1 { +- status = "okay"; +-}; +- +-&gmac0 { +- status = "okay"; +- phy-mode = "rgmii"; +- phy-handle = <&phy0>; +- +- max-frame-size = <9000>; +- +- mdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy0: ethernet-phy@0 { +- reg = <4>; +- +- txd0-skew-ps = <0>; /* -420ps */ +- txd1-skew-ps = <0>; /* -420ps */ +- txd2-skew-ps = <0>; /* -420ps */ +- txd3-skew-ps = <0>; /* -420ps */ +- rxd0-skew-ps = <420>; /* 0ps */ +- rxd1-skew-ps = <420>; /* 0ps */ +- rxd2-skew-ps = <420>; /* 0ps */ +- rxd3-skew-ps = <420>; /* 0ps */ +- txen-skew-ps = <0>; /* -420ps */ +- txc-skew-ps = <900>; /* 0ps */ +- rxdv-skew-ps = <420>; /* 0ps */ +- rxc-skew-ps = <1680>; /* 780ps */ +- }; +- }; +-}; +- +-&mmc { +- status = "okay"; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- broken-cd; +- bus-width = <4>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- disable-over-current; +-}; +- +-&watchdog0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <100000>; +- i2c-sda-falling-time-ns = <890>; /* hcnt */ +- i2c-sdl-falling-time-ns = <890>; /* lcnt */ +- +- adc@14 { +- compatible = "lltc,ltc2497"; +- reg = <0x14>; +- vref-supply = <&ref_033v>; +- }; +- +- temp@4c { +- compatible = "maxim,max1619"; +- reg = <0x4c>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c32"; +- reg = <0x51>; +- pagesize = <32>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +-}; +- +-&qspi { +- status = "okay"; +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,mt25qu02g", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <100000000>; +- +- m25p,fast-read; +- cdns,page-size = <256>; +- cdns,block-size = <16>; +- cdns,read-delay = <1>; +- cdns,tshsl-ns = <50>; +- cdns,tsd2d-ns = <50>; +- cdns,tchsh-ns = <4>; +- cdns,tslch-ns = <4>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- qspi_boot: partition@0 { +- label = "Boot and fpga data"; +- reg = <0x0 0x03FE0000>; +- }; +- +- qspi_rootfs: partition@3FE0000 { +- label = "Root Filesystem - JFFS2"; +- reg = <0x03FE0000 0x0C020000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/altera/socfpga_stratix10_socdk_nand.dts b/scripts/dtc/include-prefixes/arm64/altera/socfpga_stratix10_socdk_nand.dts +deleted file mode 100644 +index f9b4a39683cf..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/altera/socfpga_stratix10_socdk_nand.dts ++++ /dev/null +@@ -1,224 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright Altera Corporation (C) 2015. All rights reserved. +- */ +- +-#include "socfpga_stratix10.dtsi" +- +-/ { +- model = "SoCFPGA Stratix 10 SoCDK"; +- +- aliases { +- serial0 = &uart0; +- ethernet0 = &gmac0; +- ethernet1 = &gmac1; +- ethernet2 = &gmac2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- hps0 { +- label = "hps_led0"; +- gpios = <&portb 20 GPIO_ACTIVE_HIGH>; +- }; +- +- hps1 { +- label = "hps_led1"; +- gpios = <&portb 19 GPIO_ACTIVE_HIGH>; +- }; +- +- hps2 { +- label = "hps_led2"; +- gpios = <&portb 21 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- /* We expect the bootloader to fill in the reg */ +- reg = <0 0 0 0>; +- }; +- +- ref_033v: 033-v-ref { +- compatible = "regulator-fixed"; +- regulator-name = "0.33V"; +- regulator-min-microvolt = <330000>; +- regulator-max-microvolt = <330000>; +- }; +- +- soc { +- clocks { +- osc1 { +- clock-frequency = <25000000>; +- }; +- }; +- +- eccmgr { +- sdmmca-ecc@ff8c8c00 { +- compatible = "altr,socfpga-s10-sdmmc-ecc", +- "altr,socfpga-sdmmc-ecc"; +- reg = <0xff8c8c00 0x100>; +- altr,ecc-parent = <&mmc>; +- interrupts = <14 4>, +- <15 4>; +- }; +- }; +- }; +-}; +- +-&gpio1 { +- status = "okay"; +-}; +- +-&gmac2 { +- status = "okay"; +- phy-mode = "rgmii"; +- phy-handle = <&phy0>; +- +- max-frame-size = <9000>; +- +- mdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy0: ethernet-phy@0 { +- reg = <4>; +- +- txd0-skew-ps = <0>; /* -420ps */ +- txd1-skew-ps = <0>; /* -420ps */ +- txd2-skew-ps = <0>; /* -420ps */ +- txd3-skew-ps = <0>; /* -420ps */ +- rxd0-skew-ps = <420>; /* 0ps */ +- rxd1-skew-ps = <420>; /* 0ps */ +- rxd2-skew-ps = <420>; /* 0ps */ +- rxd3-skew-ps = <420>; /* 0ps */ +- txen-skew-ps = <0>; /* -420ps */ +- txc-skew-ps = <900>; /* 0ps */ +- rxdv-skew-ps = <420>; /* 0ps */ +- rxc-skew-ps = <1680>; /* 780ps */ +- }; +- }; +-}; +- +-&nand { +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- nand-bus-width = <16>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0 0x200000>; +- }; +- +- partition@200000 { +- label = "env"; +- reg = <0x200000 0x40000>; +- }; +- +- partition@240000 { +- label = "dtb"; +- reg = <0x240000 0x40000>; +- }; +- +- partition@280000 { +- label = "kernel"; +- reg = <0x280000 0x2000000>; +- }; +- +- partition@2280000 { +- label = "misc"; +- reg = <0x2280000 0x2000000>; +- }; +- +- partition@4280000 { +- label = "rootfs"; +- reg = <0x4280000 0x3bd80000>; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- disable-over-current; +-}; +- +-&watchdog0 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +- clock-frequency = <100000>; +- i2c-sda-falling-time-ns = <890>; /* hcnt */ +- i2c-sdl-falling-time-ns = <890>; /* lcnt */ +- +- adc@14 { +- compatible = "lltc,ltc2497"; +- reg = <0x14>; +- vref-supply = <&ref_033v>; +- }; +- +- temp@4c { +- compatible = "maxim,max1619"; +- reg = <0x4c>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c32"; +- reg = <0x51>; +- pagesize = <32>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +-}; +- +-&qspi { +- status = "okay"; +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,mt25qu02g", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <100000000>; +- +- m25p,fast-read; +- cdns,page-size = <256>; +- cdns,block-size = <16>; +- cdns,read-delay = <1>; +- cdns,tshsl-ns = <50>; +- cdns,tsd2d-ns = <50>; +- cdns,tchsh-ns = <4>; +- cdns,tslch-ns = <4>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- qspi_boot: partition@0 { +- label = "Boot and fpga data"; +- reg = <0x0 0x03FE0000>; +- }; +- +- qspi_rootfs: partition@3FE0000 { +- label = "Root Filesystem - JFFS2"; +- reg = <0x03FE0000 0x0C020000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amazon/Makefile b/scripts/dtc/include-prefixes/arm64/amazon/Makefile +deleted file mode 100644 +index ba9e11544905..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amazon/Makefile ++++ /dev/null +@@ -1,3 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0-only +-dtb-$(CONFIG_ARCH_ALPINE) += alpine-v2-evp.dtb +-dtb-$(CONFIG_ARCH_ALPINE) += alpine-v3-evp.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/amazon/alpine-v2-evp.dts b/scripts/dtc/include-prefixes/arm64/amazon/alpine-v2-evp.dts +deleted file mode 100644 +index a079d7b3063e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amazon/alpine-v2-evp.dts ++++ /dev/null +@@ -1,53 +0,0 @@ +-/* +- * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +- * +- * Antoine Tenart +- * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * BSD license below: +- * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. +- */ +- +-#include "alpine-v2.dtsi" +- +-/ { +- model = "Annapurna Labs Alpine v2 EVP"; +- compatible = "al,alpine-v2-evp", "al,alpine-v2"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&uart0 { status = "okay"; }; +diff --git a/scripts/dtc/include-prefixes/arm64/amazon/alpine-v2.dtsi b/scripts/dtc/include-prefixes/arm64/amazon/alpine-v2.dtsi +deleted file mode 100644 +index 4eb2cd14e00b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amazon/alpine-v2.dtsi ++++ /dev/null +@@ -1,236 +0,0 @@ +-/* +- * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +- * +- * Antoine Tenart +- * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * BSD license below: +- * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include +- +-/ { +- model = "Annapurna Labs Alpine v2"; +- compatible = "al,alpine-v2"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,cortex-a57"; +- device_type = "cpu"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- }; +- +- cpu@1 { +- compatible = "arm,cortex-a57"; +- device_type = "cpu"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- }; +- +- cpu@2 { +- compatible = "arm,cortex-a57"; +- device_type = "cpu"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- }; +- +- cpu@3 { +- compatible = "arm,cortex-a57"; +- device_type = "cpu"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2", "arm,psci"; +- method = "smc"; +- cpu_suspend = <0x84000001>; +- cpu_off = <0x84000002>; +- cpu_on = <0x84000003>; +- }; +- +- sbclk: sbclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <1000000>; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- interrupt-parent = <&gic>; +- ranges; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = , +- , +- , +- ; +- }; +- +- gic: interrupt-controller@f0200000 { +- compatible = "arm,gic-v3"; +- reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */ +- <0x0 0xf0280000 0x0 0x200000>, /* GICR */ +- <0x0 0xf0100000 0x0 0x2000>, /* GICC */ +- <0x0 0xf0110000 0x0 0x2000>, /* GICV */ +- <0x0 0xf0120000 0x0 0x2000>; /* GICH */ +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- +- pci@fbc00000 { +- compatible = "pci-host-ecam-generic"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- #interrupt-cells = <1>; +- reg = <0x0 0xfbc00000 0x0 0x100000>; +- interrupt-map-mask = <0xf800 0 0 7>; +- /* add legacy interrupts for SATA only */ +- interrupt-map = <0x4000 0 0 1 &gic 0 53 4>, +- <0x4800 0 0 1 &gic 0 54 4>; +- /* 32 bit non prefetchable memory space */ +- ranges = <0x2000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>; +- bus-range = <0x00 0x00>; +- msi-parent = <&msix>; +- }; +- +- msix: msix@fbe00000 { +- compatible = "al,alpine-msix"; +- reg = <0x0 0xfbe00000 0x0 0x100000>; +- interrupt-controller; +- msi-controller; +- al,msi-base-spi = <160>; +- al,msi-num-spis = <160>; +- }; +- +- io-fabric { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0xfc000000 0x2000000>; +- +- uart0: serial@1883000 { +- compatible = "ns16550a"; +- device_type = "serial"; +- reg = <0x1883000 0x1000>; +- interrupts = ; +- clock-frequency = <500000000>; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart1: serial@1884000 { +- compatible = "ns16550a"; +- device_type = "serial"; +- reg = <0x1884000 0x1000>; +- interrupts = ; +- clock-frequency = <500000000>; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart2: serial@1885000 { +- compatible = "ns16550a"; +- device_type = "serial"; +- reg = <0x1885000 0x1000>; +- interrupts = ; +- clock-frequency = <500000000>; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart3: serial@1886000 { +- compatible = "ns16550a"; +- device_type = "serial"; +- reg = <0x1886000 0x1000>; +- interrupts = ; +- clock-frequency = <500000000>; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- timer0: timer@1890000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x1890000 0x1000>; +- interrupts = ; +- clocks = <&sbclk>; +- }; +- +- timer1: timer@1891000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x1891000 0x1000>; +- interrupts = ; +- clocks = <&sbclk>; +- status = "disabled"; +- }; +- +- timer2: timer@1892000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x1892000 0x1000>; +- interrupts = ; +- clocks = <&sbclk>; +- status = "disabled"; +- }; +- +- timer3: timer@1893000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x1893000 0x1000>; +- interrupts = ; +- clocks = <&sbclk>; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amazon/alpine-v3-evp.dts b/scripts/dtc/include-prefixes/arm64/amazon/alpine-v3-evp.dts +deleted file mode 100644 +index 48078f5ea545..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amazon/alpine-v3-evp.dts ++++ /dev/null +@@ -1,24 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +- */ +- +-#include "alpine-v3.dtsi" +- +-/ { +- model = "Amazon's Annapurna Labs Alpine v3 Evaluation Platform (EVP)"; +- compatible = "amazon,al-alpine-v3-evp", "amazon,al-alpine-v3"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&uart0 { status = "okay"; }; +diff --git a/scripts/dtc/include-prefixes/arm64/amazon/alpine-v3.dtsi b/scripts/dtc/include-prefixes/arm64/amazon/alpine-v3.dtsi +deleted file mode 100644 +index 73a352ea8fd5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amazon/alpine-v3.dtsi ++++ /dev/null +@@ -1,408 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2020, Amazon.com, Inc. or its affiliates. All Rights Reserved +- */ +- +-/dts-v1/; +- +-#include +- +-/ { +- model = "Amazon's Annapurna Labs Alpine v3"; +- compatible = "amazon,al-alpine-v3"; +- +- interrupt-parent = <&gic>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x0>; +- enable-method = "psci"; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- next-level-cache = <&cluster0_l2>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x1>; +- enable-method = "psci"; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- next-level-cache = <&cluster0_l2>; +- }; +- +- cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x2>; +- enable-method = "psci"; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- next-level-cache = <&cluster0_l2>; +- }; +- +- cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x3>; +- enable-method = "psci"; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- next-level-cache = <&cluster0_l2>; +- }; +- +- cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x100>; +- enable-method = "psci"; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- next-level-cache = <&cluster1_l2>; +- }; +- +- cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x101>; +- enable-method = "psci"; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- next-level-cache = <&cluster1_l2>; +- }; +- +- cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x102>; +- enable-method = "psci"; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- next-level-cache = <&cluster1_l2>; +- }; +- +- cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x103>; +- enable-method = "psci"; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- next-level-cache = <&cluster1_l2>; +- }; +- +- cpu@200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x200>; +- enable-method = "psci"; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- next-level-cache = <&cluster2_l2>; +- }; +- +- cpu@201 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x201>; +- enable-method = "psci"; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- next-level-cache = <&cluster2_l2>; +- }; +- +- cpu@202 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x202>; +- enable-method = "psci"; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- next-level-cache = <&cluster2_l2>; +- }; +- +- cpu@203 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x203>; +- enable-method = "psci"; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- next-level-cache = <&cluster2_l2>; +- }; +- +- cpu@300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x300>; +- enable-method = "psci"; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- next-level-cache = <&cluster3_l2>; +- }; +- +- cpu@301 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x301>; +- enable-method = "psci"; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- next-level-cache = <&cluster3_l2>; +- }; +- +- cpu@302 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x302>; +- enable-method = "psci"; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- next-level-cache = <&cluster3_l2>; +- }; +- +- cpu@303 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x303>; +- enable-method = "psci"; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- next-level-cache = <&cluster3_l2>; +- }; +- +- cluster0_l2: cache@0 { +- compatible = "cache"; +- cache-size = <0x200000>; +- cache-line-size = <64>; +- cache-sets = <2048>; +- cache-level = <2>; +- }; +- +- cluster1_l2: cache@100 { +- compatible = "cache"; +- cache-size = <0x200000>; +- cache-line-size = <64>; +- cache-sets = <2048>; +- cache-level = <2>; +- }; +- +- cluster2_l2: cache@200 { +- compatible = "cache"; +- cache-size = <0x200000>; +- cache-line-size = <64>; +- cache-sets = <2048>; +- cache-level = <2>; +- }; +- +- cluster3_l2: cache@300 { +- compatible = "cache"; +- cache-size = <0x200000>; +- cache-line-size = <64>; +- cache-sets = <2048>; +- cache-level = <2>; +- }; +- +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- secmon@0 { +- reg = <0x0 0x0 0x0 0x100000>; +- no-map; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,cortex-a72-pmu"; +- interrupts = ; +- }; +- +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gic: interrupt-controller@f0000000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x0 0xf0800000 0 0x10000>, /* GICD */ +- <0x0 0xf0a00000 0 0x200000>, /* GICR */ +- <0x0 0xf0000000 0 0x2000>, /* GICC */ +- <0x0 0xf0010000 0 0x1000>, /* GICH */ +- <0x0 0xf0020000 0 0x2000>; /* GICV */ +- interrupts = ; +- }; +- +- pcie@fbd00000 { +- compatible = "pci-host-ecam-generic"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- #interrupt-cells = <1>; +- reg = <0x0 0xfbd00000 0x0 0x100000>; +- interrupt-map-mask = <0xf800 0 0 7>; +- /* 8 x legacy interrupts for SATA only */ +- interrupt-map = <0x4000 0 0 1 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, +- <0x4800 0 0 1 &gic 0 58 IRQ_TYPE_LEVEL_HIGH>, +- <0x5000 0 0 1 &gic 0 59 IRQ_TYPE_LEVEL_HIGH>, +- <0x5800 0 0 1 &gic 0 60 IRQ_TYPE_LEVEL_HIGH>, +- <0x6000 0 0 1 &gic 0 61 IRQ_TYPE_LEVEL_HIGH>, +- <0x6800 0 0 1 &gic 0 62 IRQ_TYPE_LEVEL_HIGH>, +- <0x7000 0 0 1 &gic 0 63 IRQ_TYPE_LEVEL_HIGH>, +- <0x7800 0 0 1 &gic 0 64 IRQ_TYPE_LEVEL_HIGH>; +- ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>; +- bus-range = <0x00 0x00>; +- msi-parent = <&msix>; +- }; +- +- msix: msix@fbe00000 { +- compatible = "al,alpine-msix"; +- reg = <0x0 0xfbe00000 0x0 0x100000>; +- interrupt-controller; +- msi-controller; +- al,msi-base-spi = <336>; +- al,msi-num-spis = <959>; +- interrupt-parent = <&gic>; +- }; +- +- io-fabric { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0xfc000000 0x2000000>; +- +- uart0: serial@1883000 { +- compatible = "ns16550a"; +- reg = <0x1883000 0x1000>; +- interrupts = ; +- clock-frequency = <0>; /* Filled by firmware */ +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart1: serial@1884000 { +- compatible = "ns16550a"; +- reg = <0x1884000 0x1000>; +- interrupts = ; +- clock-frequency = <0>; /* Filled by firmware */ +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart2: serial@1885000 { +- compatible = "ns16550a"; +- reg = <0x1885000 0x1000>; +- interrupts = ; +- clock-frequency = <0>; /* Filled by firmware */ +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart3: serial@1886000 { +- compatible = "ns16550a"; +- reg = <0x1886000 0x1000>; +- interrupts = ; +- clock-frequency = <0>; /* Filled by firmware */ +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amd/Makefile b/scripts/dtc/include-prefixes/arm64/amd/Makefile +deleted file mode 100644 +index 6a6093064a32..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amd/Makefile ++++ /dev/null +@@ -1,4 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive.dtb \ +- amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb \ +- husky.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/amd/amd-overdrive-rev-b0.dts b/scripts/dtc/include-prefixes/arm64/amd/amd-overdrive-rev-b0.dts +deleted file mode 100644 +index 8e341be9a399..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amd/amd-overdrive-rev-b0.dts ++++ /dev/null +@@ -1,88 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * DTS file for AMD Seattle Overdrive Development Board +- * Note: For Seattle Rev.B0 +- * +- * Copyright (C) 2015 Advanced Micro Devices, Inc. +- */ +- +-/dts-v1/; +- +-/include/ "amd-seattle-soc.dtsi" +- +-/ { +- model = "AMD Seattle (Rev.B0) Development Board (Overdrive)"; +- compatible = "amd,seattle-overdrive", "amd,seattle"; +- +- chosen { +- stdout-path = &serial0; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +-}; +- +-&ccp0 { +- status = "ok"; +- amd,zlib-support = <1>; +-}; +- +-/** +- * NOTE: In Rev.B, gpio0 is reserved. +- */ +-&gpio1 { +- status = "ok"; +-}; +- +-&gpio2 { +- status = "ok"; +-}; +- +-&gpio3 { +- status = "ok"; +-}; +- +-&gpio4 { +- status = "ok"; +-}; +- +-&i2c0 { +- status = "ok"; +-}; +- +-&i2c1 { +- status = "ok"; +-}; +- +-&pcie0 { +- status = "ok"; +-}; +- +-&spi0 { +- status = "ok"; +-}; +- +-&spi1 { +- status = "ok"; +- sdcard0: sdcard@0 { +- compatible = "mmc-spi-slot"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- voltage-ranges = <3200 3400>; +- pl022,hierarchy = <0>; +- pl022,interface = <0>; +- pl022,com-mode = <0x0>; +- pl022,rx-level-trig = <0>; +- pl022,tx-level-trig = <0>; +- }; +-}; +- +-&ipmi_kcs { +- status = "ok"; +-}; +- +-&smb0 { +- /include/ "amd-seattle-xgbe-b.dtsi" +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amd/amd-overdrive-rev-b1.dts b/scripts/dtc/include-prefixes/arm64/amd/amd-overdrive-rev-b1.dts +deleted file mode 100644 +index 92cef05c6b74..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amd/amd-overdrive-rev-b1.dts ++++ /dev/null +@@ -1,92 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * DTS file for AMD Seattle Overdrive Development Board +- * Note: For Seattle Rev.B1 +- * +- * Copyright (C) 2015 Advanced Micro Devices, Inc. +- */ +- +-/dts-v1/; +- +-/include/ "amd-seattle-soc.dtsi" +- +-/ { +- model = "AMD Seattle (Rev.B1) Development Board (Overdrive)"; +- compatible = "amd,seattle-overdrive", "amd,seattle"; +- +- chosen { +- stdout-path = &serial0; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +-}; +- +-&ccp0 { +- status = "ok"; +- amd,zlib-support = <1>; +-}; +- +-/** +- * NOTE: In Rev.B, gpio0 is reserved. +- */ +-&gpio1 { +- status = "ok"; +-}; +- +-&gpio2 { +- status = "ok"; +-}; +- +-&gpio3 { +- status = "ok"; +-}; +- +-&gpio4 { +- status = "ok"; +-}; +- +-&i2c0 { +- status = "ok"; +-}; +- +-&i2c1 { +- status = "ok"; +-}; +- +-&pcie0 { +- status = "ok"; +-}; +- +-&sata1 { +- status = "ok"; +-}; +- +-&spi0 { +- status = "ok"; +-}; +- +-&spi1 { +- status = "ok"; +- sdcard0: sdcard@0 { +- compatible = "mmc-spi-slot"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- voltage-ranges = <3200 3400>; +- pl022,hierarchy = <0>; +- pl022,interface = <0>; +- pl022,com-mode = <0x0>; +- pl022,rx-level-trig = <0>; +- pl022,tx-level-trig = <0>; +- }; +-}; +- +-&ipmi_kcs { +- status = "ok"; +-}; +- +-&smb0 { +- /include/ "amd-seattle-xgbe-b.dtsi" +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amd/amd-overdrive.dts b/scripts/dtc/include-prefixes/arm64/amd/amd-overdrive.dts +deleted file mode 100644 +index 41b3a6c0993d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amd/amd-overdrive.dts ++++ /dev/null +@@ -1,66 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * DTS file for AMD Seattle Overdrive Development Board +- * +- * Copyright (C) 2014 Advanced Micro Devices, Inc. +- */ +- +-/dts-v1/; +- +-/include/ "amd-seattle-soc.dtsi" +- +-/ { +- model = "AMD Seattle Development Board (Overdrive)"; +- compatible = "amd,seattle-overdrive", "amd,seattle"; +- +- chosen { +- stdout-path = &serial0; +- }; +-}; +- +-&ccp0 { +- status = "ok"; +-}; +- +-&gpio0 { +- status = "ok"; +-}; +- +-&gpio1 { +- status = "ok"; +-}; +- +-&i2c0 { +- status = "ok"; +-}; +- +-&pcie0 { +- status = "ok"; +-}; +- +-&spi0 { +- status = "ok"; +-}; +- +-&spi1 { +- status = "ok"; +- sdcard0: sdcard@0 { +- compatible = "mmc-spi-slot"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- voltage-ranges = <3200 3400>; +- gpios = <&gpio0 7 0>; +- interrupt-parent = <&gpio0>; +- interrupts = <7 3>; +- pl022,hierarchy = <0>; +- pl022,interface = <0>; +- pl022,com-mode = <0x0>; +- pl022,rx-level-trig = <0>; +- pl022,tx-level-trig = <0>; +- }; +-}; +- +-&v2m0 { +- arm,msi-base-spi = <64>; +- arm,msi-num-spis = <256>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amd/amd-seattle-clks.dtsi b/scripts/dtc/include-prefixes/arm64/amd/amd-seattle-clks.dtsi +deleted file mode 100644 +index 2dd2c28171ee..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amd/amd-seattle-clks.dtsi ++++ /dev/null +@@ -1,55 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * DTS file for AMD Seattle Clocks +- * +- * Copyright (C) 2014 Advanced Micro Devices, Inc. +- */ +- +- adl3clk_100mhz: clk100mhz_0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- clock-output-names = "adl3clk_100mhz"; +- }; +- +- ccpclk_375mhz: clk375mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <375000000>; +- clock-output-names = "ccpclk_375mhz"; +- }; +- +- sataclk_333mhz: clk333mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <333000000>; +- clock-output-names = "sataclk_333mhz"; +- }; +- +- pcieclk_500mhz: clk500mhz_0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <500000000>; +- clock-output-names = "pcieclk_500mhz"; +- }; +- +- dmaclk_500mhz: clk500mhz_1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <500000000>; +- clock-output-names = "dmaclk_500mhz"; +- }; +- +- miscclk_250mhz: clk250mhz_4 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <250000000>; +- clock-output-names = "miscclk_250mhz"; +- }; +- +- uartspiclk_100mhz: clk100mhz_1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- clock-output-names = "uartspiclk_100mhz"; +- }; +diff --git a/scripts/dtc/include-prefixes/arm64/amd/amd-seattle-soc.dtsi b/scripts/dtc/include-prefixes/arm64/amd/amd-seattle-soc.dtsi +deleted file mode 100644 +index b664e7af74eb..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amd/amd-seattle-soc.dtsi ++++ /dev/null +@@ -1,251 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * DTS file for AMD Seattle SoC +- * +- * Copyright (C) 2014 Advanced Micro Devices, Inc. +- */ +- +-/ { +- compatible = "amd,seattle"; +- interrupt-parent = <&gic0>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- gic0: interrupt-controller@e1101000 { +- compatible = "arm,gic-400", "arm,cortex-a15-gic"; +- interrupt-controller; +- #interrupt-cells = <3>; +- #address-cells = <2>; +- #size-cells = <2>; +- reg = <0x0 0xe1110000 0 0x1000>, +- <0x0 0xe112f000 0 0x2000>, +- <0x0 0xe1140000 0 0x2000>, +- <0x0 0xe1160000 0 0x2000>; +- interrupts = <1 9 0xf04>; +- ranges = <0 0 0 0xe1100000 0 0x100000>; +- v2m0: v2m@e0080000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x0 0x00080000 0 0x1000>; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = <1 13 0xff04>, +- <1 14 0xff04>, +- <1 11 0xff04>, +- <1 10 0xff04>; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = <0 7 4>, +- <0 8 4>, +- <0 9 4>, +- <0 10 4>, +- <0 11 4>, +- <0 12 4>, +- <0 13 4>, +- <0 14 4>; +- }; +- +- smb0: smb { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- /* +- * dma-ranges is 40-bit address space containing: +- * - GICv2m MSI register is at 0xe0080000 +- * - DRAM range [0x8000000000 to 0xffffffffff] +- */ +- dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; +- +- /include/ "amd-seattle-clks.dtsi" +- +- sata0: sata@e0300000 { +- compatible = "snps,dwc-ahci"; +- reg = <0 0xe0300000 0 0xf0000>; +- interrupts = <0 355 4>; +- clocks = <&sataclk_333mhz>; +- dma-coherent; +- }; +- +- /* This is for Rev B only */ +- sata1: sata@e0d00000 { +- status = "disabled"; +- compatible = "snps,dwc-ahci"; +- reg = <0 0xe0d00000 0 0xf0000>; +- interrupts = <0 354 4>; +- clocks = <&sataclk_333mhz>; +- dma-coherent; +- }; +- +- i2c0: i2c@e1000000 { +- status = "disabled"; +- compatible = "snps,designware-i2c"; +- reg = <0 0xe1000000 0 0x1000>; +- interrupts = <0 357 4>; +- clocks = <&miscclk_250mhz>; +- }; +- +- i2c1: i2c@e0050000 { +- status = "disabled"; +- compatible = "snps,designware-i2c"; +- reg = <0 0xe0050000 0 0x1000>; +- interrupts = <0 340 4>; +- clocks = <&miscclk_250mhz>; +- }; +- +- serial0: serial@e1010000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0 0xe1010000 0 0x1000>; +- interrupts = <0 328 4>; +- clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- spi0: spi@e1020000 { +- status = "disabled"; +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0 0xe1020000 0 0x1000>; +- spi-controller; +- interrupts = <0 330 4>; +- clocks = <&uartspiclk_100mhz>; +- clock-names = "apb_pclk"; +- }; +- +- spi1: spi@e1030000 { +- status = "disabled"; +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0 0xe1030000 0 0x1000>; +- spi-controller; +- interrupts = <0 329 4>; +- clocks = <&uartspiclk_100mhz>; +- clock-names = "apb_pclk"; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- gpio0: gpio@e1040000 { /* Not available to OS for B0 */ +- status = "disabled"; +- compatible = "arm,pl061", "arm,primecell"; +- #gpio-cells = <2>; +- reg = <0 0xe1040000 0 0x1000>; +- gpio-controller; +- interrupts = <0 359 4>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&miscclk_250mhz>; +- clock-names = "apb_pclk"; +- }; +- +- gpio1: gpio@e1050000 { /* [0:7] */ +- status = "disabled"; +- compatible = "arm,pl061", "arm,primecell"; +- #gpio-cells = <2>; +- reg = <0 0xe1050000 0 0x1000>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <0 358 4>; +- clocks = <&miscclk_250mhz>; +- clock-names = "apb_pclk"; +- }; +- +- gpio2: gpio@e0020000 { /* [8:15] */ +- status = "disabled"; +- compatible = "arm,pl061", "arm,primecell"; +- #gpio-cells = <2>; +- reg = <0 0xe0020000 0 0x1000>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <0 366 4>; +- clocks = <&miscclk_250mhz>; +- clock-names = "apb_pclk"; +- }; +- +- gpio3: gpio@e0030000 { /* [16:23] */ +- status = "disabled"; +- compatible = "arm,pl061", "arm,primecell"; +- #gpio-cells = <2>; +- reg = <0 0xe0030000 0 0x1000>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <0 365 4>; +- clocks = <&miscclk_250mhz>; +- clock-names = "apb_pclk"; +- }; +- +- gpio4: gpio@e0080000 { /* [24] */ +- status = "disabled"; +- compatible = "arm,pl061", "arm,primecell"; +- #gpio-cells = <2>; +- reg = <0 0xe0080000 0 0x1000>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <0 361 4>; +- clocks = <&miscclk_250mhz>; +- clock-names = "apb_pclk"; +- }; +- +- ccp0: ccp@e0100000 { +- status = "disabled"; +- compatible = "amd,ccp-seattle-v1a"; +- reg = <0 0xe0100000 0 0x10000>; +- interrupts = <0 3 4>; +- dma-coherent; +- }; +- +- pcie0: pcie@f0000000 { +- compatible = "pci-host-ecam-generic"; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- bus-range = <0 0x7f>; +- msi-parent = <&v2m0>; +- reg = <0 0xf0000000 0 0x10000000>; +- +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = +- <0x1000 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>, +- <0x1000 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>, +- <0x1000 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>, +- <0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>; +- +- dma-coherent; +- dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; +- ranges = +- /* I/O Memory (size=64K) */ +- <0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>, +- /* 32-bit MMIO (size=2G) */ +- <0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>, +- /* 64-bit MMIO (size= 124G) */ +- <0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>; +- }; +- +- /* Perf CCN504 PMU */ +- ccn: ccn@e8000000 { +- compatible = "arm,ccn-504"; +- reg = <0x0 0xe8000000 0 0x1000000>; +- interrupts = <0 380 4>; +- }; +- +- ipmi_kcs: kcs@e0010000 { +- status = "disabled"; +- compatible = "ipmi-kcs"; +- device_type = "ipmi"; +- reg = <0x0 0xe0010000 0 0x8>; +- interrupts = <0 389 4>; +- reg-size = <1>; +- reg-spacing = <4>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amd/amd-seattle-xgbe-b.dtsi b/scripts/dtc/include-prefixes/arm64/amd/amd-seattle-xgbe-b.dtsi +deleted file mode 100644 +index d97498361ce3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amd/amd-seattle-xgbe-b.dtsi ++++ /dev/null +@@ -1,118 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * DTS file for AMD Seattle XGBE (RevB) +- * +- * Copyright (C) 2015 Advanced Micro Devices, Inc. +- */ +- +- xgmacclk0_dma_250mhz: clk250mhz_0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <250000000>; +- clock-output-names = "xgmacclk0_dma_250mhz"; +- }; +- +- xgmacclk0_ptp_250mhz: clk250mhz_1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <250000000>; +- clock-output-names = "xgmacclk0_ptp_250mhz"; +- }; +- +- xgmacclk1_dma_250mhz: clk250mhz_2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <250000000>; +- clock-output-names = "xgmacclk1_dma_250mhz"; +- }; +- +- xgmacclk1_ptp_250mhz: clk250mhz_3 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <250000000>; +- clock-output-names = "xgmacclk1_ptp_250mhz"; +- }; +- +- xgmac0: xgmac@e0700000 { +- compatible = "amd,xgbe-seattle-v1a"; +- reg = <0 0xe0700000 0 0x80000>, +- <0 0xe0780000 0 0x80000>, +- <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */ +- <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */ +- <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */ +- interrupts = <0 325 4>, +- <0 346 1>, <0 347 1>, <0 348 1>, <0 349 1>, +- <0 323 4>; +- amd,per-channel-interrupt; +- amd,speed-set = <0>; +- amd,serdes-blwc = <1>, <1>, <0>; +- amd,serdes-cdr-rate = <2>, <2>, <7>; +- amd,serdes-pq-skew = <10>, <10>, <18>; +- amd,serdes-tx-amp = <0>, <0>, <0>; +- amd,serdes-dfe-tap-config = <3>, <3>, <3>; +- amd,serdes-dfe-tap-enable = <0>, <0>, <7>; +- mac-address = [ 02 A1 A2 A3 A4 A5 ]; +- clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>; +- clock-names = "dma_clk", "ptp_clk"; +- phy-mode = "xgmii"; +- #stream-id-cells = <16>; +- dma-coherent; +- }; +- +- xgmac1: xgmac@e0900000 { +- compatible = "amd,xgbe-seattle-v1a"; +- reg = <0 0xe0900000 0 0x80000>, +- <0 0xe0980000 0 0x80000>, +- <0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */ +- <0 0xe1250080 0 0x00060>, /* SERDES IR 1/2 */ +- <0 0xe12500fc 0 0x00004>; /* SERDES IR 2/2 */ +- interrupts = <0 324 4>, +- <0 341 1>, <0 342 1>, <0 343 1>, <0 344 1>, +- <0 322 4>; +- amd,per-channel-interrupt; +- amd,speed-set = <0>; +- amd,serdes-blwc = <1>, <1>, <0>; +- amd,serdes-cdr-rate = <2>, <2>, <7>; +- amd,serdes-pq-skew = <10>, <10>, <18>; +- amd,serdes-tx-amp = <0>, <0>, <0>; +- amd,serdes-dfe-tap-config = <3>, <3>, <3>; +- amd,serdes-dfe-tap-enable = <0>, <0>, <7>; +- mac-address = [ 02 B1 B2 B3 B4 B5 ]; +- clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>; +- clock-names = "dma_clk", "ptp_clk"; +- phy-mode = "xgmii"; +- #stream-id-cells = <16>; +- dma-coherent; +- }; +- +- xgmac0_smmu: smmu@e0600000 { +- compatible = "arm,mmu-401"; +- reg = <0 0xe0600000 0 0x10000>; +- #global-interrupts = <1>; +- interrupts = /* Uses combined intr for both +- * global and context +- */ +- <0 336 4>, +- <0 336 4>; +- +- mmu-masters = <&xgmac0 +- 0 1 2 3 4 5 6 7 +- 16 17 18 19 20 21 22 23 +- >; +- }; +- +- xgmac1_smmu: smmu@e0800000 { +- compatible = "arm,mmu-401"; +- reg = <0 0xe0800000 0 0x10000>; +- #global-interrupts = <1>; +- interrupts = /* Uses combined intr for both +- * global and context +- */ +- <0 335 4>, +- <0 335 4>; +- +- mmu-masters = <&xgmac1 +- 0 1 2 3 4 5 6 7 +- 16 17 18 19 20 21 22 23 +- >; +- }; +diff --git a/scripts/dtc/include-prefixes/arm64/amd/husky.dts b/scripts/dtc/include-prefixes/arm64/amd/husky.dts +deleted file mode 100644 +index 7acde34772cb..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amd/husky.dts ++++ /dev/null +@@ -1,84 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * DTS file for AMD/Linaro 96Boards Enterprise Edition Server (Husky) Board +- * Note: Based-on AMD Seattle Rev.B0 +- * +- * Copyright (C) 2015 Advanced Micro Devices, Inc. +- */ +- +-/dts-v1/; +- +-/include/ "amd-seattle-soc.dtsi" +- +-/ { +- model = "Linaro 96Boards Enterprise Edition Server (Husky) Board"; +- compatible = "amd,seattle-overdrive", "amd,seattle"; +- +- chosen { +- stdout-path = &serial0; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +-}; +- +-&ccp0 { +- status = "ok"; +- amd,zlib-support = <1>; +-}; +- +-/** +- * NOTE: In Rev.B, gpio0 is reserved. +- */ +-&gpio1 { +- status = "ok"; +-}; +- +-&gpio2 { +- status = "ok"; +-}; +- +-&gpio3 { +- status = "ok"; +-}; +- +-&gpio4 { +- status = "ok"; +-}; +- +-&i2c0 { +- status = "ok"; +-}; +- +-&i2c1 { +- status = "ok"; +-}; +- +-&pcie0 { +- status = "ok"; +-}; +- +-&spi0 { +- status = "ok"; +-}; +- +-&spi1 { +- status = "ok"; +- sdcard0: sdcard@0 { +- compatible = "mmc-spi-slot"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- voltage-ranges = <3200 3400>; +- pl022,hierarchy = <0>; +- pl022,interface = <0>; +- pl022,com-mode = <0x0>; +- pl022,rx-level-trig = <0>; +- pl022,tx-level-trig = <0>; +- }; +-}; +- +-&smb0 { +- /include/ "amd-seattle-xgbe-b.dtsi" +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/Makefile b/scripts/dtc/include-prefixes/arm64/amlogic/Makefile +deleted file mode 100644 +index faa0a79a34f5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/Makefile ++++ /dev/null +@@ -1,56 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-g12a-sei510.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gsking-x.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-kii-pro.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p200.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p201.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-hub.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-play2.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-libretech-ac.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc-v2.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-mecool-kii-pro.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-phicomm-n1.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-sml5442tw.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-libretech-pc.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxm-mecool-kiii-pro.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxm-minix-neo-u9h.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-libretech-pc.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m5.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb +-dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-a1-ad401.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-a1-ad401.dts +deleted file mode 100644 +index 69c25c68c358..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-a1-ad401.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Amlogic, Inc. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "meson-a1.dtsi" +- +-/ { +- compatible = "amlogic,ad401", "amlogic,a1"; +- model = "Amlogic Meson A1 AD401 Development Board"; +- +- aliases { +- serial0 = &uart_AO_B; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x8000000>; +- }; +-}; +- +-&uart_AO_B { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-a1.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-a1.dtsi +deleted file mode 100644 +index b4000cf65a9a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-a1.dtsi ++++ /dev/null +@@ -1,161 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Amlogic, Inc. All rights reserved. +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "amlogic,a1"; +- +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- }; +- +- l2: l2-cache0 { +- compatible = "cache"; +- }; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- linux,cma { +- compatible = "shared-dma-pool"; +- reusable; +- size = <0x0 0x800000>; +- alignment = <0x0 0x400000>; +- linux,cma-default; +- }; +- }; +- +- sm: secure-monitor { +- compatible = "amlogic,meson-gxbb-sm"; +- +- pwrc: power-controller { +- compatible = "amlogic,meson-a1-pwrc"; +- #power-domain-cells = <1>; +- status = "okay"; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- apb: bus@fe000000 { +- compatible = "simple-bus"; +- reg = <0x0 0xfe000000 0x0 0x1000000>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; +- +- +- reset: reset-controller@0 { +- compatible = "amlogic,meson-a1-reset"; +- reg = <0x0 0x0 0x0 0x8c>; +- #reset-cells = <1>; +- }; +- +- periphs_pinctrl: pinctrl@400 { +- compatible = "amlogic,meson-a1-periphs-pinctrl"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gpio: bank@400 { +- reg = <0x0 0x0400 0x0 0x003c>, +- <0x0 0x0480 0x0 0x0118>; +- reg-names = "mux", "gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&periphs_pinctrl 0 0 62>; +- }; +- +- }; +- +- uart_AO: serial@1c00 { +- compatible = "amlogic,meson-gx-uart", +- "amlogic,meson-ao-uart"; +- reg = <0x0 0x1c00 0x0 0x18>; +- interrupts = ; +- clocks = <&xtal>, <&xtal>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +- status = "disabled"; +- }; +- +- uart_AO_B: serial@2000 { +- compatible = "amlogic,meson-gx-uart", +- "amlogic,meson-ao-uart"; +- reg = <0x0 0x2000 0x0 0x18>; +- interrupts = ; +- clocks = <&xtal>, <&xtal>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +- status = "disabled"; +- }; +- }; +- +- gic: interrupt-controller@ff901000 { +- compatible = "arm,gic-400"; +- reg = <0x0 0xff901000 0x0 0x1000>, +- <0x0 0xff902000 0x0 0x2000>, +- <0x0 0xff904000 0x0 0x2000>, +- <0x0 0xff906000 0x0 0x2000>; +- interrupt-controller; +- interrupts = ; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- xtal: xtal-clk { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "xtal"; +- #clock-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-axg-s400.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-axg-s400.dts +deleted file mode 100644 +index 359589d1dfa9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-axg-s400.dts ++++ /dev/null +@@ -1,602 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Amlogic, Inc. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "meson-axg.dtsi" +-#include +- +-/ { +- compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg"; +- model = "Amlogic Meson AXG S400 Development Board"; +- +- adc_keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 0>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1800000>; +- +- button-next { +- label = "Next"; +- linux,code = ; +- press-threshold-microvolt = <1116000>; /* 62% */ +- }; +- +- button-prev { +- label = "Previous"; +- linux,code = ; +- press-threshold-microvolt = <900000>; /* 50% */ +- }; +- +- button-wifi { +- label = "Wifi"; +- linux,code = ; +- press-threshold-microvolt = <684000>; /* 38% */ +- }; +- +- button-up { +- label = "Volume Up"; +- linux,code = ; +- press-threshold-microvolt = <468000>; /* 26% */ +- }; +- +- button-down { +- label = "Volume Down"; +- linux,code = ; +- press-threshold-microvolt = <252000>; /* 14% */ +- }; +- +- button-voice { +- label = "Voice"; +- linux,code = ; +- press-threshold-microvolt = <0>; /* 0% */ +- }; +- }; +- +- aliases { +- serial0 = &uart_AO; +- serial1 = &uart_A; +- }; +- +- linein: audio-codec-0 { +- #sound-dai-cells = <0>; +- compatible = "everest,es7241"; +- VDDA-supply = <&vcc_3v3>; +- VDDP-supply = <&vcc_3v3>; +- VDDD-supply = <&vcc_3v3>; +- status = "okay"; +- sound-name-prefix = "Linein"; +- }; +- +- lineout: audio-codec-1 { +- #sound-dai-cells = <0>; +- compatible = "everest,es7154"; +- VDD-supply = <&vcc_3v3>; +- PVDD-supply = <&vcc_5v>; +- status = "okay"; +- sound-name-prefix = "Lineout"; +- }; +- +- spdif_dit: audio-codec-2 { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- status = "okay"; +- sound-name-prefix = "DIT"; +- }; +- +- dmics: audio-codec-3 { +- #sound-dai-cells = <0>; +- compatible = "dmic-codec"; +- num-channels = <7>; +- wakeup-delay-ms = <50>; +- status = "okay"; +- sound-name-prefix = "MIC"; +- }; +- +- spdif_dir: audio-codec-4 { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dir"; +- status = "okay"; +- sound-name-prefix = "DIR"; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x40000000>; +- }; +- +- main_12v: regulator-main_12v { +- compatible = "regulator-fixed"; +- regulator-name = "12V"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- }; +- +- vcc_5v: regulator-vcc_5v { +- compatible = "regulator-fixed"; +- regulator-name = "VCC5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&main_12v>; +- +- gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vddao_3v3: regulator-vddao_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&main_12v>; +- regulator-always-on; +- }; +- +- vddio_ao18: regulator-vddio_ao18 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- }; +- +- vddio_boot: regulator-vddio_boot { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_BOOT"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- }; +- +- usb_pwr: regulator-usb_pwr { +- compatible = "regulator-fixed"; +- regulator-name = "USB_PWR"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc_5v>; +- +- gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>; +- clocks = <&wifi32k>; +- clock-names = "ext_clock"; +- }; +- +- speaker-leds { +- compatible = "gpio-leds"; +- +- aled1 { +- label = "speaker:aled1"; +- gpios = <&gpio_speaker 7 0>; +- }; +- +- aled2 { +- label = "speaker:aled2"; +- gpios = <&gpio_speaker 6 0>; +- }; +- +- aled3 { +- label = "speaker:aled3"; +- gpios = <&gpio_speaker 5 0>; +- }; +- +- aled4 { +- label = "speaker:aled4"; +- gpios = <&gpio_speaker 4 0>; +- }; +- +- aled5 { +- label = "speaker:aled5"; +- gpios = <&gpio_speaker 3 0>; +- }; +- +- aled6 { +- label = "speaker:aled6"; +- gpios = <&gpio_speaker 2 0>; +- }; +- }; +- +- sound { +- compatible = "amlogic,axg-sound-card"; +- model = "AXG-S400"; +- audio-aux-devs = <&tdmin_a>, <&tdmin_b>, <&tdmin_c>, +- <&tdmin_lb>, <&tdmout_c>; +- audio-widgets = "Line", "Lineout", +- "Line", "Linein", +- "Speaker", "Speaker1 Left", +- "Speaker", "Speaker1 Right"; +- audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2", +- "SPDIFOUT IN 0", "FRDDR_A OUT 3", +- "TDMOUT_C IN 1", "FRDDR_B OUT 2", +- "SPDIFOUT IN 1", "FRDDR_B OUT 3", +- "TDMOUT_C IN 2", "FRDDR_C OUT 2", +- "SPDIFOUT IN 2", "FRDDR_C OUT 3", +- "TDM_C Playback", "TDMOUT_C OUT", +- "TDMIN_A IN 2", "TDM_C Capture", +- "TDMIN_A IN 5", "TDM_C Loopback", +- "TDMIN_B IN 2", "TDM_C Capture", +- "TDMIN_B IN 5", "TDM_C Loopback", +- "TDMIN_C IN 2", "TDM_C Capture", +- "TDMIN_C IN 5", "TDM_C Loopback", +- "TDMIN_LB IN 2", "TDM_C Loopback", +- "TDMIN_LB IN 5", "TDM_C Capture", +- "TODDR_A IN 0", "TDMIN_A OUT", +- "TODDR_B IN 0", "TDMIN_A OUT", +- "TODDR_C IN 0", "TDMIN_A OUT", +- "TODDR_A IN 1", "TDMIN_B OUT", +- "TODDR_B IN 1", "TDMIN_B OUT", +- "TODDR_C IN 1", "TDMIN_B OUT", +- "TODDR_A IN 2", "TDMIN_C OUT", +- "TODDR_B IN 2", "TDMIN_C OUT", +- "TODDR_C IN 2", "TDMIN_C OUT", +- "TODDR_A IN 3", "SPDIFIN Capture", +- "TODDR_B IN 3", "SPDIFIN Capture", +- "TODDR_C IN 3", "SPDIFIN Capture", +- "TODDR_A IN 4", "PDM Capture", +- "TODDR_B IN 4", "PDM Capture", +- "TODDR_C IN 4", "PDM Capture", +- "TODDR_A IN 6", "TDMIN_LB OUT", +- "TODDR_B IN 6", "TDMIN_LB OUT", +- "TODDR_C IN 6", "TDMIN_LB OUT", +- "Lineout", "Lineout AOUTL", +- "Lineout", "Lineout AOUTR", +- "Speaker1 Left", "SPK1 OUT_A", +- "Speaker1 Left", "SPK1 OUT_B", +- "Speaker1 Right", "SPK1 OUT_C", +- "Speaker1 Right", "SPK1 OUT_D", +- "Linein AINL", "Linein", +- "Linein AINR", "Linein"; +- assigned-clocks = <&clkc CLKID_HIFI_PLL>, +- <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <589824000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&frddr_a>; +- }; +- +- dai-link-1 { +- sound-dai = <&frddr_b>; +- }; +- +- dai-link-2 { +- sound-dai = <&frddr_c>; +- }; +- +- dai-link-3 { +- sound-dai = <&toddr_a>; +- }; +- +- dai-link-4 { +- sound-dai = <&toddr_b>; +- }; +- +- dai-link-5 { +- sound-dai = <&toddr_c>; +- }; +- +- dai-link-6 { +- sound-dai = <&tdmif_c>; +- dai-format = "i2s"; +- dai-tdm-slot-tx-mask-2 = <1 1>; +- dai-tdm-slot-rx-mask-1 = <1 1>; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&lineout>; +- }; +- +- codec-1 { +- sound-dai = <&speaker_amp1>; +- }; +- +- codec-2 { +- sound-dai = <&linein>; +- }; +- +- }; +- +- dai-link-7 { +- sound-dai = <&spdifout>; +- +- codec { +- sound-dai = <&spdif_dit>; +- }; +- }; +- +- dai-link-8 { +- sound-dai = <&spdifin>; +- +- codec { +- sound-dai = <&spdif_dir>; +- }; +- }; +- +- dai-link-9 { +- sound-dai = <&pdm>; +- +- codec { +- sound-dai = <&dmics>; +- }; +- }; +- }; +- +- wifi32k: wifi32k { +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */ +- }; +-}; +- +-ðmac { +- status = "okay"; +- pinctrl-0 = <ð_rgmii_y_pins>; +- pinctrl-names = "default"; +- phy-handle = <ð_phy0>; +- phy-mode = "rgmii"; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eth_phy0: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- interrupt-parent = <&gpio_intc>; +- interrupts = <98 IRQ_TYPE_LEVEL_LOW>; +- eee-broken-1000t; +- }; +- }; +-}; +- +-&frddr_a { +- status = "okay"; +-}; +- +-&frddr_b { +- status = "okay"; +-}; +- +-&frddr_c { +- status = "okay"; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&i2c1 { +- status = "okay"; +- pinctrl-0 = <&i2c1_z_pins>; +- pinctrl-names = "default"; +- +- speaker_amp1: audio-codec@1b { +- compatible = "ti,tas5707"; +- reg = <0x1b>; +- reset-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; +- #sound-dai-cells = <0>; +- AVDD-supply = <&vcc_3v3>; +- DVDD-supply = <&vcc_3v3>; +- PVDD_A-supply = <&main_12v>; +- PVDD_B-supply = <&main_12v>; +- PVDD_C-supply = <&main_12v>; +- PVDD_D-supply = <&main_12v>; +- sound-name-prefix = "SPK1"; +- }; +-}; +- +-&i2c_AO { +- status = "okay"; +- pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>; +- pinctrl-names = "default"; +- +- gpio_speaker: gpio-controller@1f { +- compatible = "nxp,pca9557"; +- reg = <0x1f>; +- gpio-controller; +- #gpio-cells = <2>; +- vcc-supply = <&vddao_3v3>; +- }; +-}; +- +-&pdm { +- pinctrl-0 = <&pdm_dclk_a14_pins>, <&pdm_din0_pins>, +- <&pdm_din1_pins>, <&pdm_din2_pins>, <&pdm_din3_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&pcieA { +- reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pcieB { +- reset-gpios = <&gpio GPIOZ_10 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; +- status = "okay"; +-}; +- +-&pwm_ab { +- status = "okay"; +- pinctrl-0 = <&pwm_a_x20_pins>; +- pinctrl-names = "default"; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vddio_ao18>; +-}; +- +-/* wifi module */ +-&sd_emmc_b { +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pinctrl-0 = <&sdio_pins>; +- pinctrl-1 = <&sdio_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- sd-uhs-sdr104; +- max-frequency = <200000000>; +- non-removable; +- disable-wp; +- +- mmc-pwrseq = <&sdio_pwrseq>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_boot>; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* emmc storage */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- max-frequency = <200000000>; +- non-removable; +- disable-wp; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-&spdifin { +- pinctrl-0 = <&spdif_in_a19_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&spdifout { +- pinctrl-0 = <&spdif_out_a20_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&tdmif_a { +- pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>, +- <&tdma_din0_pins>, <&tdma_dout0_x15_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&tdmif_b { +- pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>, +- <&tdmb_din3_pins>, <&mclk_b_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&tdmif_c { +- pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>, +- <&tdmc_din1_pins>, <&tdmc_dout2_pins>, +- <&mclk_c_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&tdmin_a { +- status = "okay"; +-}; +- +-&tdmin_b { +- status = "okay"; +-}; +- +-&tdmin_c { +- status = "okay"; +-}; +- +-&tdmin_lb { +- status = "okay"; +-}; +- +-&tdmout_c { +- status = "okay"; +-}; +- +-&toddr_a { +- status = "okay"; +-}; +- +-&toddr_b { +- status = "okay"; +-}; +- +-&toddr_c { +- status = "okay"; +-}; +- +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- shutdown-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- status = "okay"; +- dr_mode = "otg"; +- vbus-supply = <&usb_pwr>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-axg.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-axg.dtsi +deleted file mode 100644 +index 3f5254eeb47b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-axg.dtsi ++++ /dev/null +@@ -1,1957 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Amlogic, Inc. All rights reserved. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "amlogic,meson-axg"; +- +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- tdmif_a: audio-controller-0 { +- compatible = "amlogic,axg-tdm-iface"; +- #sound-dai-cells = <0>; +- sound-name-prefix = "TDM_A"; +- clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, +- <&clkc_audio AUD_CLKID_MST_A_SCLK>, +- <&clkc_audio AUD_CLKID_MST_A_LRCLK>; +- clock-names = "mclk", "sclk", "lrclk"; +- status = "disabled"; +- }; +- +- tdmif_b: audio-controller-1 { +- compatible = "amlogic,axg-tdm-iface"; +- #sound-dai-cells = <0>; +- sound-name-prefix = "TDM_B"; +- clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, +- <&clkc_audio AUD_CLKID_MST_B_SCLK>, +- <&clkc_audio AUD_CLKID_MST_B_LRCLK>; +- clock-names = "mclk", "sclk", "lrclk"; +- status = "disabled"; +- }; +- +- tdmif_c: audio-controller-2 { +- compatible = "amlogic,axg-tdm-iface"; +- #sound-dai-cells = <0>; +- sound-name-prefix = "TDM_C"; +- clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, +- <&clkc_audio AUD_CLKID_MST_C_SCLK>, +- <&clkc_audio AUD_CLKID_MST_C_LRCLK>; +- clock-names = "mclk", "sclk", "lrclk"; +- status = "disabled"; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- cpus { +- #address-cells = <0x2>; +- #size-cells = <0x0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- clocks = <&scpi_dvfs 0>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- clocks = <&scpi_dvfs 0>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- clocks = <&scpi_dvfs 0>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- clocks = <&scpi_dvfs 0>; +- }; +- +- l2: l2-cache0 { +- compatible = "cache"; +- }; +- }; +- +- sm: secure-monitor { +- compatible = "amlogic,meson-gxbb-sm"; +- }; +- +- efuse: efuse { +- compatible = "amlogic,meson-gxbb-efuse"; +- clocks = <&clkc CLKID_EFUSE>; +- #address-cells = <1>; +- #size-cells = <1>; +- read-only; +- secure-monitor = <&sm>; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- /* 16 MiB reserved for Hardware ROM Firmware */ +- hwrom_reserved: hwrom@0 { +- reg = <0x0 0x0 0x0 0x1000000>; +- no-map; +- }; +- +- /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ +- secmon_reserved: secmon@5000000 { +- reg = <0x0 0x05000000 0x0 0x300000>; +- no-map; +- }; +- }; +- +- scpi { +- compatible = "arm,scpi-pre-1.0"; +- mboxes = <&mailbox 1 &mailbox 2>; +- shmem = <&cpu_scp_lpri &cpu_scp_hpri>; +- +- scpi_clocks: clocks { +- compatible = "arm,scpi-clocks"; +- +- scpi_dvfs: clock-controller { +- compatible = "arm,scpi-dvfs-clocks"; +- #clock-cells = <1>; +- clock-indices = <0>; +- clock-output-names = "vcpu"; +- }; +- }; +- +- scpi_sensors: sensors { +- compatible = "amlogic,meson-gxbb-scpi-sensors"; +- #thermal-sensor-cells = <1>; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- pcieA: pcie@f9800000 { +- compatible = "amlogic,axg-pcie", "snps,dw-pcie"; +- reg = <0x0 0xf9800000 0x0 0x400000>, +- <0x0 0xff646000 0x0 0x2000>, +- <0x0 0xf9f00000 0x0 0x100000>; +- reg-names = "elbi", "cfg", "config"; +- interrupts = ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; +- bus-range = <0x0 0xff>; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>; +- +- clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>; +- clock-names = "general", "pclk", "port"; +- resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>; +- reset-names = "port", "apb"; +- num-lanes = <1>; +- phys = <&pcie_phy>; +- phy-names = "pcie"; +- status = "disabled"; +- }; +- +- pcieB: pcie@fa000000 { +- compatible = "amlogic,axg-pcie", "snps,dw-pcie"; +- reg = <0x0 0xfa000000 0x0 0x400000>, +- <0x0 0xff648000 0x0 0x2000>, +- <0x0 0xfa400000 0x0 0x100000>; +- reg-names = "elbi", "cfg", "config"; +- interrupts = ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; +- bus-range = <0x0 0xff>; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>; +- +- clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>; +- clock-names = "general", "pclk", "port"; +- resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>; +- reset-names = "port", "apb"; +- num-lanes = <1>; +- phys = <&pcie_phy>; +- phy-names = "pcie"; +- status = "disabled"; +- }; +- +- usb: usb@ffe09080 { +- compatible = "amlogic,meson-axg-usb-ctrl"; +- reg = <0x0 0xffe09080 0x0 0x20>; +- interrupts = ; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; +- clock-names = "usb_ctrl", "ddr"; +- resets = <&reset RESET_USB_OTG>; +- +- dr_mode = "otg"; +- +- phys = <&usb2_phy1>; +- phy-names = "usb2-phy1"; +- +- dwc2: usb@ff400000 { +- compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; +- reg = <0x0 0xff400000 0x0 0x40000>; +- interrupts = ; +- clocks = <&clkc CLKID_USB1>; +- clock-names = "otg"; +- phys = <&usb2_phy1>; +- dr_mode = "peripheral"; +- g-rx-fifo-size = <192>; +- g-np-tx-fifo-size = <128>; +- g-tx-fifo-size = <128 128 16 16 16>; +- }; +- +- dwc3: usb@ff500000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0xff500000 0x0 0x100000>; +- interrupts = ; +- dr_mode = "host"; +- maximum-speed = "high-speed"; +- snps,dis_u2_susphy_quirk; +- }; +- }; +- +- ethmac: ethernet@ff3f0000 { +- compatible = "amlogic,meson-axg-dwmac", +- "snps,dwmac-3.70a", +- "snps,dwmac"; +- reg = <0x0 0xff3f0000 0x0 0x10000>, +- <0x0 0xff634540 0x0 0x8>; +- interrupts = ; +- interrupt-names = "macirq"; +- clocks = <&clkc CLKID_ETH>, +- <&clkc CLKID_FCLK_DIV2>, +- <&clkc CLKID_MPLL2>, +- <&clkc CLKID_FCLK_DIV2>; +- clock-names = "stmmaceth", "clkin0", "clkin1", +- "timing-adjustment"; +- rx-fifo-depth = <4096>; +- tx-fifo-depth = <2048>; +- power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>; +- status = "disabled"; +- }; +- +- pcie_phy: phy@ff644000 { +- compatible = "amlogic,axg-pcie-phy"; +- reg = <0x0 0xff644000 0x0 0x1c>; +- resets = <&reset RESET_PCIE_PHY>; +- phys = <&mipi_pcie_analog_dphy>; +- phy-names = "analog"; +- #phy-cells = <0>; +- }; +- +- pdm: audio-controller@ff632000 { +- compatible = "amlogic,axg-pdm"; +- reg = <0x0 0xff632000 0x0 0x34>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "PDM"; +- clocks = <&clkc_audio AUD_CLKID_PDM>, +- <&clkc_audio AUD_CLKID_PDM_DCLK>, +- <&clkc_audio AUD_CLKID_PDM_SYSCLK>; +- clock-names = "pclk", "dclk", "sysclk"; +- status = "disabled"; +- }; +- +- periphs: bus@ff634000 { +- compatible = "simple-bus"; +- reg = <0x0 0xff634000 0x0 0x2000>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; +- +- hwrng: rng@18 { +- compatible = "amlogic,meson-rng"; +- reg = <0x0 0x18 0x0 0x4>; +- clocks = <&clkc CLKID_RNG0>; +- clock-names = "core"; +- }; +- +- pinctrl_periphs: pinctrl@480 { +- compatible = "amlogic,meson-axg-periphs-pinctrl"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gpio: bank@480 { +- reg = <0x0 0x00480 0x0 0x40>, +- <0x0 0x004e8 0x0 0x14>, +- <0x0 0x00520 0x0 0x14>, +- <0x0 0x00430 0x0 0x3c>; +- reg-names = "mux", "pull", "pull-enable", "gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl_periphs 0 0 86>; +- }; +- +- i2c0_pins: i2c0 { +- mux { +- groups = "i2c0_sck", +- "i2c0_sda"; +- function = "i2c0"; +- bias-disable; +- }; +- }; +- +- i2c1_x_pins: i2c1_x { +- mux { +- groups = "i2c1_sck_x", +- "i2c1_sda_x"; +- function = "i2c1"; +- bias-disable; +- }; +- }; +- +- i2c1_z_pins: i2c1_z { +- mux { +- groups = "i2c1_sck_z", +- "i2c1_sda_z"; +- function = "i2c1"; +- bias-disable; +- }; +- }; +- +- i2c2_a_pins: i2c2_a { +- mux { +- groups = "i2c2_sck_a", +- "i2c2_sda_a"; +- function = "i2c2"; +- bias-disable; +- }; +- }; +- +- i2c2_x_pins: i2c2_x { +- mux { +- groups = "i2c2_sck_x", +- "i2c2_sda_x"; +- function = "i2c2"; +- bias-disable; +- }; +- }; +- +- i2c3_a6_pins: i2c3_a6 { +- mux { +- groups = "i2c3_sda_a6", +- "i2c3_sck_a7"; +- function = "i2c3"; +- bias-disable; +- }; +- }; +- +- i2c3_a12_pins: i2c3_a12 { +- mux { +- groups = "i2c3_sda_a12", +- "i2c3_sck_a13"; +- function = "i2c3"; +- bias-disable; +- }; +- }; +- +- i2c3_a19_pins: i2c3_a19 { +- mux { +- groups = "i2c3_sda_a19", +- "i2c3_sck_a20"; +- function = "i2c3"; +- bias-disable; +- }; +- }; +- +- emmc_pins: emmc { +- mux-0 { +- groups = "emmc_nand_d0", +- "emmc_nand_d1", +- "emmc_nand_d2", +- "emmc_nand_d3", +- "emmc_nand_d4", +- "emmc_nand_d5", +- "emmc_nand_d6", +- "emmc_nand_d7", +- "emmc_cmd"; +- function = "emmc"; +- bias-pull-up; +- }; +- +- mux-1 { +- groups = "emmc_clk"; +- function = "emmc"; +- bias-disable; +- }; +- }; +- +- emmc_ds_pins: emmc_ds { +- mux { +- groups = "emmc_ds"; +- function = "emmc"; +- bias-pull-down; +- }; +- }; +- +- emmc_clk_gate_pins: emmc_clk_gate { +- mux { +- groups = "BOOT_8"; +- function = "gpio_periphs"; +- bias-pull-down; +- }; +- }; +- +- eth_rgmii_x_pins: eth-x-rgmii { +- mux { +- groups = "eth_mdio_x", +- "eth_mdc_x", +- "eth_rgmii_rx_clk_x", +- "eth_rx_dv_x", +- "eth_rxd0_x", +- "eth_rxd1_x", +- "eth_rxd2_rgmii", +- "eth_rxd3_rgmii", +- "eth_rgmii_tx_clk", +- "eth_txen_x", +- "eth_txd0_x", +- "eth_txd1_x", +- "eth_txd2_rgmii", +- "eth_txd3_rgmii"; +- function = "eth"; +- bias-disable; +- }; +- }; +- +- eth_rgmii_y_pins: eth-y-rgmii { +- mux { +- groups = "eth_mdio_y", +- "eth_mdc_y", +- "eth_rgmii_rx_clk_y", +- "eth_rx_dv_y", +- "eth_rxd0_y", +- "eth_rxd1_y", +- "eth_rxd2_rgmii", +- "eth_rxd3_rgmii", +- "eth_rgmii_tx_clk", +- "eth_txen_y", +- "eth_txd0_y", +- "eth_txd1_y", +- "eth_txd2_rgmii", +- "eth_txd3_rgmii"; +- function = "eth"; +- bias-disable; +- }; +- }; +- +- eth_rmii_x_pins: eth-x-rmii { +- mux { +- groups = "eth_mdio_x", +- "eth_mdc_x", +- "eth_rgmii_rx_clk_x", +- "eth_rx_dv_x", +- "eth_rxd0_x", +- "eth_rxd1_x", +- "eth_txen_x", +- "eth_txd0_x", +- "eth_txd1_x"; +- function = "eth"; +- bias-disable; +- }; +- }; +- +- eth_rmii_y_pins: eth-y-rmii { +- mux { +- groups = "eth_mdio_y", +- "eth_mdc_y", +- "eth_rgmii_rx_clk_y", +- "eth_rx_dv_y", +- "eth_rxd0_y", +- "eth_rxd1_y", +- "eth_txen_y", +- "eth_txd0_y", +- "eth_txd1_y"; +- function = "eth"; +- bias-disable; +- }; +- }; +- +- mclk_b_pins: mclk_b { +- mux { +- groups = "mclk_b"; +- function = "mclk_b"; +- bias-disable; +- }; +- }; +- +- mclk_c_pins: mclk_c { +- mux { +- groups = "mclk_c"; +- function = "mclk_c"; +- bias-disable; +- }; +- }; +- +- pdm_dclk_a14_pins: pdm_dclk_a14 { +- mux { +- groups = "pdm_dclk_a14"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_dclk_a19_pins: pdm_dclk_a19 { +- mux { +- groups = "pdm_dclk_a19"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_din0_pins: pdm_din0 { +- mux { +- groups = "pdm_din0"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_din1_pins: pdm_din1 { +- mux { +- groups = "pdm_din1"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_din2_pins: pdm_din2 { +- mux { +- groups = "pdm_din2"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_din3_pins: pdm_din3 { +- mux { +- groups = "pdm_din3"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pwm_a_a_pins: pwm_a_a { +- mux { +- groups = "pwm_a_a"; +- function = "pwm_a"; +- bias-disable; +- }; +- }; +- +- pwm_a_x18_pins: pwm_a_x18 { +- mux { +- groups = "pwm_a_x18"; +- function = "pwm_a"; +- bias-disable; +- }; +- }; +- +- pwm_a_x20_pins: pwm_a_x20 { +- mux { +- groups = "pwm_a_x20"; +- function = "pwm_a"; +- bias-disable; +- }; +- }; +- +- pwm_a_z_pins: pwm_a_z { +- mux { +- groups = "pwm_a_z"; +- function = "pwm_a"; +- bias-disable; +- }; +- }; +- +- pwm_b_a_pins: pwm_b_a { +- mux { +- groups = "pwm_b_a"; +- function = "pwm_b"; +- bias-disable; +- }; +- }; +- +- pwm_b_x_pins: pwm_b_x { +- mux { +- groups = "pwm_b_x"; +- function = "pwm_b"; +- bias-disable; +- }; +- }; +- +- pwm_b_z_pins: pwm_b_z { +- mux { +- groups = "pwm_b_z"; +- function = "pwm_b"; +- bias-disable; +- }; +- }; +- +- pwm_c_a_pins: pwm_c_a { +- mux { +- groups = "pwm_c_a"; +- function = "pwm_c"; +- bias-disable; +- }; +- }; +- +- pwm_c_x10_pins: pwm_c_x10 { +- mux { +- groups = "pwm_c_x10"; +- function = "pwm_c"; +- bias-disable; +- }; +- }; +- +- pwm_c_x17_pins: pwm_c_x17 { +- mux { +- groups = "pwm_c_x17"; +- function = "pwm_c"; +- bias-disable; +- }; +- }; +- +- pwm_d_x11_pins: pwm_d_x11 { +- mux { +- groups = "pwm_d_x11"; +- function = "pwm_d"; +- bias-disable; +- }; +- }; +- +- pwm_d_x16_pins: pwm_d_x16 { +- mux { +- groups = "pwm_d_x16"; +- function = "pwm_d"; +- bias-disable; +- }; +- }; +- +- sdio_pins: sdio { +- mux-0 { +- groups = "sdio_d0", +- "sdio_d1", +- "sdio_d2", +- "sdio_d3", +- "sdio_cmd"; +- function = "sdio"; +- bias-pull-up; +- }; +- +- mux-1 { +- groups = "sdio_clk"; +- function = "sdio"; +- bias-disable; +- }; +- }; +- +- sdio_clk_gate_pins: sdio_clk_gate { +- mux { +- groups = "GPIOX_4"; +- function = "gpio_periphs"; +- bias-pull-down; +- }; +- }; +- +- spdif_in_z_pins: spdif_in_z { +- mux { +- groups = "spdif_in_z"; +- function = "spdif_in"; +- bias-disable; +- }; +- }; +- +- spdif_in_a1_pins: spdif_in_a1 { +- mux { +- groups = "spdif_in_a1"; +- function = "spdif_in"; +- bias-disable; +- }; +- }; +- +- spdif_in_a7_pins: spdif_in_a7 { +- mux { +- groups = "spdif_in_a7"; +- function = "spdif_in"; +- bias-disable; +- }; +- }; +- +- spdif_in_a19_pins: spdif_in_a19 { +- mux { +- groups = "spdif_in_a19"; +- function = "spdif_in"; +- bias-disable; +- }; +- }; +- +- spdif_in_a20_pins: spdif_in_a20 { +- mux { +- groups = "spdif_in_a20"; +- function = "spdif_in"; +- bias-disable; +- }; +- }; +- +- spdif_out_a1_pins: spdif_out_a1 { +- mux { +- groups = "spdif_out_a1"; +- function = "spdif_out"; +- bias-disable; +- }; +- }; +- +- spdif_out_a11_pins: spdif_out_a11 { +- mux { +- groups = "spdif_out_a11"; +- function = "spdif_out"; +- bias-disable; +- }; +- }; +- +- spdif_out_a19_pins: spdif_out_a19 { +- mux { +- groups = "spdif_out_a19"; +- function = "spdif_out"; +- bias-disable; +- }; +- }; +- +- spdif_out_a20_pins: spdif_out_a20 { +- mux { +- groups = "spdif_out_a20"; +- function = "spdif_out"; +- bias-disable; +- }; +- }; +- +- spdif_out_z_pins: spdif_out_z { +- mux { +- groups = "spdif_out_z"; +- function = "spdif_out"; +- bias-disable; +- }; +- }; +- +- spi0_pins: spi0 { +- mux { +- groups = "spi0_miso", +- "spi0_mosi", +- "spi0_clk"; +- function = "spi0"; +- bias-disable; +- }; +- }; +- +- spi0_ss0_pins: spi0_ss0 { +- mux { +- groups = "spi0_ss0"; +- function = "spi0"; +- bias-disable; +- }; +- }; +- +- spi0_ss1_pins: spi0_ss1 { +- mux { +- groups = "spi0_ss1"; +- function = "spi0"; +- bias-disable; +- }; +- }; +- +- spi0_ss2_pins: spi0_ss2 { +- mux { +- groups = "spi0_ss2"; +- function = "spi0"; +- bias-disable; +- }; +- }; +- +- spi1_a_pins: spi1_a { +- mux { +- groups = "spi1_miso_a", +- "spi1_mosi_a", +- "spi1_clk_a"; +- function = "spi1"; +- bias-disable; +- }; +- }; +- +- spi1_ss0_a_pins: spi1_ss0_a { +- mux { +- groups = "spi1_ss0_a"; +- function = "spi1"; +- bias-disable; +- }; +- }; +- +- spi1_ss1_pins: spi1_ss1 { +- mux { +- groups = "spi1_ss1"; +- function = "spi1"; +- bias-disable; +- }; +- }; +- +- spi1_x_pins: spi1_x { +- mux { +- groups = "spi1_miso_x", +- "spi1_mosi_x", +- "spi1_clk_x"; +- function = "spi1"; +- bias-disable; +- }; +- }; +- +- spi1_ss0_x_pins: spi1_ss0_x { +- mux { +- groups = "spi1_ss0_x"; +- function = "spi1"; +- bias-disable; +- }; +- }; +- +- tdma_din0_pins: tdma_din0 { +- mux { +- groups = "tdma_din0"; +- function = "tdma"; +- bias-disable; +- }; +- }; +- +- tdma_dout0_x14_pins: tdma_dout0_x14 { +- mux { +- groups = "tdma_dout0_x14"; +- function = "tdma"; +- bias-disable; +- }; +- }; +- +- tdma_dout0_x15_pins: tdma_dout0_x15 { +- mux { +- groups = "tdma_dout0_x15"; +- function = "tdma"; +- bias-disable; +- }; +- }; +- +- tdma_dout1_pins: tdma_dout1 { +- mux { +- groups = "tdma_dout1"; +- function = "tdma"; +- bias-disable; +- }; +- }; +- +- tdma_din1_pins: tdma_din1 { +- mux { +- groups = "tdma_din1"; +- function = "tdma"; +- bias-disable; +- }; +- }; +- +- tdma_fs_pins: tdma_fs { +- mux { +- groups = "tdma_fs"; +- function = "tdma"; +- bias-disable; +- }; +- }; +- +- tdma_fs_slv_pins: tdma_fs_slv { +- mux { +- groups = "tdma_fs_slv"; +- function = "tdma"; +- bias-disable; +- }; +- }; +- +- tdma_sclk_pins: tdma_sclk { +- mux { +- groups = "tdma_sclk"; +- function = "tdma"; +- bias-disable; +- }; +- }; +- +- tdma_sclk_slv_pins: tdma_sclk_slv { +- mux { +- groups = "tdma_sclk_slv"; +- function = "tdma"; +- bias-disable; +- }; +- }; +- +- tdmb_din0_pins: tdmb_din0 { +- mux { +- groups = "tdmb_din0"; +- function = "tdmb"; +- bias-disable; +- }; +- }; +- +- tdmb_din1_pins: tdmb_din1 { +- mux { +- groups = "tdmb_din1"; +- function = "tdmb"; +- bias-disable; +- }; +- }; +- +- tdmb_din2_pins: tdmb_din2 { +- mux { +- groups = "tdmb_din2"; +- function = "tdmb"; +- bias-disable; +- }; +- }; +- +- tdmb_din3_pins: tdmb_din3 { +- mux { +- groups = "tdmb_din3"; +- function = "tdmb"; +- bias-disable; +- }; +- }; +- +- tdmb_dout0_pins: tdmb_dout0 { +- mux { +- groups = "tdmb_dout0"; +- function = "tdmb"; +- bias-disable; +- }; +- }; +- +- tdmb_dout1_pins: tdmb_dout1 { +- mux { +- groups = "tdmb_dout1"; +- function = "tdmb"; +- bias-disable; +- }; +- }; +- +- tdmb_dout2_pins: tdmb_dout2 { +- mux { +- groups = "tdmb_dout2"; +- function = "tdmb"; +- bias-disable; +- }; +- }; +- +- tdmb_dout3_pins: tdmb_dout3 { +- mux { +- groups = "tdmb_dout3"; +- function = "tdmb"; +- bias-disable; +- }; +- }; +- +- tdmb_fs_pins: tdmb_fs { +- mux { +- groups = "tdmb_fs"; +- function = "tdmb"; +- bias-disable; +- }; +- }; +- +- tdmb_fs_slv_pins: tdmb_fs_slv { +- mux { +- groups = "tdmb_fs_slv"; +- function = "tdmb"; +- bias-disable; +- }; +- }; +- +- tdmb_sclk_pins: tdmb_sclk { +- mux { +- groups = "tdmb_sclk"; +- function = "tdmb"; +- bias-disable; +- }; +- }; +- +- tdmb_sclk_slv_pins: tdmb_sclk_slv { +- mux { +- groups = "tdmb_sclk_slv"; +- function = "tdmb"; +- bias-disable; +- }; +- }; +- +- tdmc_fs_pins: tdmc_fs { +- mux { +- groups = "tdmc_fs"; +- function = "tdmc"; +- bias-disable; +- }; +- }; +- +- tdmc_fs_slv_pins: tdmc_fs_slv { +- mux { +- groups = "tdmc_fs_slv"; +- function = "tdmc"; +- bias-disable; +- }; +- }; +- +- tdmc_sclk_pins: tdmc_sclk { +- mux { +- groups = "tdmc_sclk"; +- function = "tdmc"; +- bias-disable; +- }; +- }; +- +- tdmc_sclk_slv_pins: tdmc_sclk_slv { +- mux { +- groups = "tdmc_sclk_slv"; +- function = "tdmc"; +- bias-disable; +- }; +- }; +- +- tdmc_din0_pins: tdmc_din0 { +- mux { +- groups = "tdmc_din0"; +- function = "tdmc"; +- bias-disable; +- }; +- }; +- +- tdmc_din1_pins: tdmc_din1 { +- mux { +- groups = "tdmc_din1"; +- function = "tdmc"; +- bias-disable; +- }; +- }; +- +- tdmc_din2_pins: tdmc_din2 { +- mux { +- groups = "tdmc_din2"; +- function = "tdmc"; +- bias-disable; +- }; +- }; +- +- tdmc_din3_pins: tdmc_din3 { +- mux { +- groups = "tdmc_din3"; +- function = "tdmc"; +- bias-disable; +- }; +- }; +- +- tdmc_dout0_pins: tdmc_dout0 { +- mux { +- groups = "tdmc_dout0"; +- function = "tdmc"; +- bias-disable; +- }; +- }; +- +- tdmc_dout1_pins: tdmc_dout1 { +- mux { +- groups = "tdmc_dout1"; +- function = "tdmc"; +- bias-disable; +- }; +- }; +- +- tdmc_dout2_pins: tdmc_dout2 { +- mux { +- groups = "tdmc_dout2"; +- function = "tdmc"; +- bias-disable; +- }; +- }; +- +- tdmc_dout3_pins: tdmc_dout3 { +- mux { +- groups = "tdmc_dout3"; +- function = "tdmc"; +- bias-disable; +- }; +- }; +- +- uart_a_pins: uart_a { +- mux { +- groups = "uart_tx_a", +- "uart_rx_a"; +- function = "uart_a"; +- bias-disable; +- }; +- }; +- +- uart_a_cts_rts_pins: uart_a_cts_rts { +- mux { +- groups = "uart_cts_a", +- "uart_rts_a"; +- function = "uart_a"; +- bias-disable; +- }; +- }; +- +- uart_b_x_pins: uart_b_x { +- mux { +- groups = "uart_tx_b_x", +- "uart_rx_b_x"; +- function = "uart_b"; +- bias-disable; +- }; +- }; +- +- uart_b_x_cts_rts_pins: uart_b_x_cts_rts { +- mux { +- groups = "uart_cts_b_x", +- "uart_rts_b_x"; +- function = "uart_b"; +- bias-disable; +- }; +- }; +- +- uart_b_z_pins: uart_b_z { +- mux { +- groups = "uart_tx_b_z", +- "uart_rx_b_z"; +- function = "uart_b"; +- bias-disable; +- }; +- }; +- +- uart_b_z_cts_rts_pins: uart_b_z_cts_rts { +- mux { +- groups = "uart_cts_b_z", +- "uart_rts_b_z"; +- function = "uart_b"; +- bias-disable; +- }; +- }; +- +- uart_ao_b_z_pins: uart_ao_b_z { +- mux { +- groups = "uart_ao_tx_b_z", +- "uart_ao_rx_b_z"; +- function = "uart_ao_b_z"; +- bias-disable; +- }; +- }; +- +- uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { +- mux { +- groups = "uart_ao_cts_b_z", +- "uart_ao_rts_b_z"; +- function = "uart_ao_b_z"; +- bias-disable; +- }; +- }; +- }; +- }; +- +- hiubus: bus@ff63c000 { +- compatible = "simple-bus"; +- reg = <0x0 0xff63c000 0x0 0x1c00>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; +- +- sysctrl: system-controller@0 { +- compatible = "amlogic,meson-axg-hhi-sysctrl", +- "simple-mfd", "syscon"; +- reg = <0 0 0 0x400>; +- +- clkc: clock-controller { +- compatible = "amlogic,axg-clkc"; +- #clock-cells = <1>; +- clocks = <&xtal>; +- clock-names = "xtal"; +- }; +- +- pwrc: power-controller { +- compatible = "amlogic,meson-axg-pwrc"; +- #power-domain-cells = <1>; +- amlogic,ao-sysctrl = <&sysctrl_AO>; +- resets = <&reset RESET_VIU>, +- <&reset RESET_VENC>, +- <&reset RESET_VCBUS>, +- <&reset RESET_VENCL>, +- <&reset RESET_VID_LOCK>; +- reset-names = "viu", "venc", "vcbus", +- "vencl", "vid_lock"; +- clocks = <&clkc CLKID_VPU>, +- <&clkc CLKID_VAPB>; +- clock-names = "vpu", "vapb"; +- /* +- * VPU clocking is provided by two identical clock paths +- * VPU_0 and VPU_1 muxed to a single clock by a glitch +- * free mux to safely change frequency while running. +- * Same for VAPB but with a final gate after the glitch free mux. +- */ +- assigned-clocks = <&clkc CLKID_VPU_0_SEL>, +- <&clkc CLKID_VPU_0>, +- <&clkc CLKID_VPU>, /* Glitch free mux */ +- <&clkc CLKID_VAPB_0_SEL>, +- <&clkc CLKID_VAPB_0>, +- <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ +- assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>, +- <0>, /* Do Nothing */ +- <&clkc CLKID_VPU_0>, +- <&clkc CLKID_FCLK_DIV4>, +- <0>, /* Do Nothing */ +- <&clkc CLKID_VAPB_0>; +- assigned-clock-rates = <0>, /* Do Nothing */ +- <250000000>, +- <0>, /* Do Nothing */ +- <0>, /* Do Nothing */ +- <250000000>, +- <0>; /* Do Nothing */ +- }; +- +- mipi_pcie_analog_dphy: phy { +- compatible = "amlogic,axg-mipi-pcie-analog-phy"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- }; +- +- mailbox: mailbox@ff63c404 { +- compatible = "amlogic,meson-gxbb-mhu"; +- reg = <0 0xff63c404 0 0x4c>; +- interrupts = , +- , +- ; +- #mbox-cells = <1>; +- }; +- +- mipi_dphy: phy@ff640000 { +- compatible = "amlogic,axg-mipi-dphy"; +- reg = <0x0 0xff640000 0x0 0x100>; +- clocks = <&clkc CLKID_MIPI_DSI_PHY>; +- clock-names = "pclk"; +- resets = <&reset RESET_MIPI_PHY>; +- reset-names = "phy"; +- phys = <&mipi_pcie_analog_dphy>; +- phy-names = "analog"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- audio: bus@ff642000 { +- compatible = "simple-bus"; +- reg = <0x0 0xff642000 0x0 0x2000>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; +- +- clkc_audio: clock-controller@0 { +- compatible = "amlogic,axg-audio-clkc"; +- reg = <0x0 0x0 0x0 0xb4>; +- #clock-cells = <1>; +- +- clocks = <&clkc CLKID_AUDIO>, +- <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>, +- <&clkc CLKID_MPLL2>, +- <&clkc CLKID_MPLL3>, +- <&clkc CLKID_HIFI_PLL>, +- <&clkc CLKID_FCLK_DIV3>, +- <&clkc CLKID_FCLK_DIV4>, +- <&clkc CLKID_GP0_PLL>; +- clock-names = "pclk", +- "mst_in0", +- "mst_in1", +- "mst_in2", +- "mst_in3", +- "mst_in4", +- "mst_in5", +- "mst_in6", +- "mst_in7"; +- +- resets = <&reset RESET_AUDIO>; +- }; +- +- toddr_a: audio-controller@100 { +- compatible = "amlogic,axg-toddr"; +- reg = <0x0 0x100 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "TODDR_A"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_TODDR_A>; +- resets = <&arb AXG_ARB_TODDR_A>; +- amlogic,fifo-depth = <512>; +- status = "disabled"; +- }; +- +- toddr_b: audio-controller@140 { +- compatible = "amlogic,axg-toddr"; +- reg = <0x0 0x140 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "TODDR_B"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_TODDR_B>; +- resets = <&arb AXG_ARB_TODDR_B>; +- amlogic,fifo-depth = <256>; +- status = "disabled"; +- }; +- +- toddr_c: audio-controller@180 { +- compatible = "amlogic,axg-toddr"; +- reg = <0x0 0x180 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "TODDR_C"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_TODDR_C>; +- resets = <&arb AXG_ARB_TODDR_C>; +- amlogic,fifo-depth = <256>; +- status = "disabled"; +- }; +- +- frddr_a: audio-controller@1c0 { +- compatible = "amlogic,axg-frddr"; +- reg = <0x0 0x1c0 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "FRDDR_A"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; +- resets = <&arb AXG_ARB_FRDDR_A>; +- amlogic,fifo-depth = <512>; +- status = "disabled"; +- }; +- +- frddr_b: audio-controller@200 { +- compatible = "amlogic,axg-frddr"; +- reg = <0x0 0x200 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "FRDDR_B"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; +- resets = <&arb AXG_ARB_FRDDR_B>; +- amlogic,fifo-depth = <256>; +- status = "disabled"; +- }; +- +- frddr_c: audio-controller@240 { +- compatible = "amlogic,axg-frddr"; +- reg = <0x0 0x240 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "FRDDR_C"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; +- resets = <&arb AXG_ARB_FRDDR_C>; +- amlogic,fifo-depth = <256>; +- status = "disabled"; +- }; +- +- arb: reset-controller@280 { +- compatible = "amlogic,meson-axg-audio-arb"; +- reg = <0x0 0x280 0x0 0x4>; +- #reset-cells = <1>; +- clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; +- }; +- +- tdmin_a: audio-controller@300 { +- compatible = "amlogic,axg-tdmin"; +- reg = <0x0 0x300 0x0 0x40>; +- sound-name-prefix = "TDMIN_A"; +- clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, +- <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- tdmin_b: audio-controller@340 { +- compatible = "amlogic,axg-tdmin"; +- reg = <0x0 0x340 0x0 0x40>; +- sound-name-prefix = "TDMIN_B"; +- clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, +- <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- tdmin_c: audio-controller@380 { +- compatible = "amlogic,axg-tdmin"; +- reg = <0x0 0x380 0x0 0x40>; +- sound-name-prefix = "TDMIN_C"; +- clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, +- <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- tdmin_lb: audio-controller@3c0 { +- compatible = "amlogic,axg-tdmin"; +- reg = <0x0 0x3c0 0x0 0x40>; +- sound-name-prefix = "TDMIN_LB"; +- clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, +- <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- spdifin: audio-controller@400 { +- compatible = "amlogic,axg-spdifin"; +- reg = <0x0 0x400 0x0 0x30>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "SPDIFIN"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, +- <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; +- clock-names = "pclk", "refclk"; +- status = "disabled"; +- }; +- +- spdifout: audio-controller@480 { +- compatible = "amlogic,axg-spdifout"; +- reg = <0x0 0x480 0x0 0x50>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "SPDIFOUT"; +- clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, +- <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; +- clock-names = "pclk", "mclk"; +- status = "disabled"; +- }; +- +- tdmout_a: audio-controller@500 { +- compatible = "amlogic,axg-tdmout"; +- reg = <0x0 0x500 0x0 0x40>; +- sound-name-prefix = "TDMOUT_A"; +- clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, +- <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, +- <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- tdmout_b: audio-controller@540 { +- compatible = "amlogic,axg-tdmout"; +- reg = <0x0 0x540 0x0 0x40>; +- sound-name-prefix = "TDMOUT_B"; +- clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, +- <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, +- <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- tdmout_c: audio-controller@580 { +- compatible = "amlogic,axg-tdmout"; +- reg = <0x0 0x580 0x0 0x40>; +- sound-name-prefix = "TDMOUT_C"; +- clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, +- <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, +- <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- }; +- +- aobus: bus@ff800000 { +- compatible = "simple-bus"; +- reg = <0x0 0xff800000 0x0 0x100000>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; +- +- sysctrl_AO: sys-ctrl@0 { +- compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; +- reg = <0x0 0x0 0x0 0x100>; +- +- clkc_AO: clock-controller { +- compatible = "amlogic,meson-axg-aoclkc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- clocks = <&xtal>, <&clkc CLKID_CLK81>; +- clock-names = "xtal", "mpeg-clk"; +- }; +- }; +- +- pinctrl_aobus: pinctrl@14 { +- compatible = "amlogic,meson-axg-aobus-pinctrl"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gpio_ao: bank@14 { +- reg = <0x0 0x00014 0x0 0x8>, +- <0x0 0x0002c 0x0 0x4>, +- <0x0 0x00024 0x0 0x8>; +- reg-names = "mux", "pull", "gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl_aobus 0 0 15>; +- }; +- +- i2c_ao_sck_4_pins: i2c_ao_sck_4 { +- mux { +- groups = "i2c_ao_sck_4"; +- function = "i2c_ao"; +- bias-disable; +- }; +- }; +- +- i2c_ao_sck_8_pins: i2c_ao_sck_8 { +- mux { +- groups = "i2c_ao_sck_8"; +- function = "i2c_ao"; +- bias-disable; +- }; +- }; +- +- i2c_ao_sck_10_pins: i2c_ao_sck_10 { +- mux { +- groups = "i2c_ao_sck_10"; +- function = "i2c_ao"; +- bias-disable; +- }; +- }; +- +- i2c_ao_sda_5_pins: i2c_ao_sda_5 { +- mux { +- groups = "i2c_ao_sda_5"; +- function = "i2c_ao"; +- bias-disable; +- }; +- }; +- +- i2c_ao_sda_9_pins: i2c_ao_sda_9 { +- mux { +- groups = "i2c_ao_sda_9"; +- function = "i2c_ao"; +- bias-disable; +- }; +- }; +- +- i2c_ao_sda_11_pins: i2c_ao_sda_11 { +- mux { +- groups = "i2c_ao_sda_11"; +- function = "i2c_ao"; +- bias-disable; +- }; +- }; +- +- remote_input_ao_pins: remote_input_ao { +- mux { +- groups = "remote_input_ao"; +- function = "remote_input_ao"; +- bias-disable; +- }; +- }; +- +- uart_ao_a_pins: uart_ao_a { +- mux { +- groups = "uart_ao_tx_a", +- "uart_ao_rx_a"; +- function = "uart_ao_a"; +- bias-disable; +- }; +- }; +- +- uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { +- mux { +- groups = "uart_ao_cts_a", +- "uart_ao_rts_a"; +- function = "uart_ao_a"; +- bias-disable; +- }; +- }; +- +- uart_ao_b_pins: uart_ao_b { +- mux { +- groups = "uart_ao_tx_b", +- "uart_ao_rx_b"; +- function = "uart_ao_b"; +- bias-disable; +- }; +- }; +- +- uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { +- mux { +- groups = "uart_ao_cts_b", +- "uart_ao_rts_b"; +- function = "uart_ao_b"; +- bias-disable; +- }; +- }; +- }; +- +- sec_AO: ao-secure@140 { +- compatible = "amlogic,meson-gx-ao-secure", "syscon"; +- reg = <0x0 0x140 0x0 0x140>; +- amlogic,has-chip-id; +- }; +- +- pwm_AO_cd: pwm@2000 { +- compatible = "amlogic,meson-axg-ao-pwm"; +- reg = <0x0 0x02000 0x0 0x20>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- uart_AO: serial@3000 { +- compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; +- reg = <0x0 0x3000 0x0 0x18>; +- interrupts = ; +- clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +- status = "disabled"; +- }; +- +- uart_AO_B: serial@4000 { +- compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; +- reg = <0x0 0x4000 0x0 0x18>; +- interrupts = ; +- clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +- status = "disabled"; +- }; +- +- i2c_AO: i2c@5000 { +- compatible = "amlogic,meson-axg-i2c"; +- reg = <0x0 0x05000 0x0 0x20>; +- interrupts = ; +- clocks = <&clkc CLKID_AO_I2C>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pwm_AO_ab: pwm@7000 { +- compatible = "amlogic,meson-axg-ao-pwm"; +- reg = <0x0 0x07000 0x0 0x20>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- ir: ir@8000 { +- compatible = "amlogic,meson-gxbb-ir"; +- reg = <0x0 0x8000 0x0 0x20>; +- interrupts = ; +- status = "disabled"; +- }; +- +- saradc: adc@9000 { +- compatible = "amlogic,meson-axg-saradc", +- "amlogic,meson-saradc"; +- reg = <0x0 0x9000 0x0 0x38>; +- #io-channel-cells = <1>; +- interrupts = ; +- clocks = <&xtal>, +- <&clkc_AO CLKID_AO_SAR_ADC>, +- <&clkc_AO CLKID_AO_SAR_ADC_CLK>, +- <&clkc_AO CLKID_AO_SAR_ADC_SEL>; +- clock-names = "clkin", "core", "adc_clk", "adc_sel"; +- status = "disabled"; +- }; +- }; +- +- ge2d: ge2d@ff940000 { +- compatible = "amlogic,axg-ge2d"; +- reg = <0x0 0xff940000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clkc CLKID_VAPB>; +- resets = <&reset RESET_GE2D>; +- }; +- +- gic: interrupt-controller@ffc01000 { +- compatible = "arm,gic-400"; +- reg = <0x0 0xffc01000 0 0x1000>, +- <0x0 0xffc02000 0 0x2000>, +- <0x0 0xffc04000 0 0x2000>, +- <0x0 0xffc06000 0 0x2000>; +- interrupt-controller; +- interrupts = ; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- }; +- +- cbus: bus@ffd00000 { +- compatible = "simple-bus"; +- reg = <0x0 0xffd00000 0x0 0x25000>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; +- +- reset: reset-controller@1004 { +- compatible = "amlogic,meson-axg-reset"; +- reg = <0x0 0x01004 0x0 0x9c>; +- #reset-cells = <1>; +- }; +- +- gpio_intc: interrupt-controller@f080 { +- compatible = "amlogic,meson-axg-gpio-intc", +- "amlogic,meson-gpio-intc"; +- reg = <0x0 0xf080 0x0 0x10>; +- interrupt-controller; +- #interrupt-cells = <2>; +- amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; +- }; +- +- watchdog@f0d0 { +- compatible = "amlogic,meson-gxbb-wdt"; +- reg = <0x0 0xf0d0 0x0 0x10>; +- clocks = <&xtal>; +- }; +- +- pwm_ab: pwm@1b000 { +- compatible = "amlogic,meson-axg-ee-pwm"; +- reg = <0x0 0x1b000 0x0 0x20>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm_cd: pwm@1a000 { +- compatible = "amlogic,meson-axg-ee-pwm"; +- reg = <0x0 0x1a000 0x0 0x20>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- spicc0: spi@13000 { +- compatible = "amlogic,meson-axg-spicc"; +- reg = <0x0 0x13000 0x0 0x3c>; +- interrupts = ; +- clocks = <&clkc CLKID_SPICC0>; +- clock-names = "core"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spicc1: spi@15000 { +- compatible = "amlogic,meson-axg-spicc"; +- reg = <0x0 0x15000 0x0 0x3c>; +- interrupts = ; +- clocks = <&clkc CLKID_SPICC1>; +- clock-names = "core"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- clk_msr: clock-measure@18000 { +- compatible = "amlogic,meson-axg-clk-measure"; +- reg = <0x0 0x18000 0x0 0x10>; +- }; +- +- i2c3: i2c@1c000 { +- compatible = "amlogic,meson-axg-i2c"; +- reg = <0x0 0x1c000 0x0 0x20>; +- interrupts = ; +- clocks = <&clkc CLKID_I2C>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@1d000 { +- compatible = "amlogic,meson-axg-i2c"; +- reg = <0x0 0x1d000 0x0 0x20>; +- interrupts = ; +- clocks = <&clkc CLKID_I2C>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@1e000 { +- compatible = "amlogic,meson-axg-i2c"; +- reg = <0x0 0x1e000 0x0 0x20>; +- interrupts = ; +- clocks = <&clkc CLKID_I2C>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c0: i2c@1f000 { +- compatible = "amlogic,meson-axg-i2c"; +- reg = <0x0 0x1f000 0x0 0x20>; +- interrupts = ; +- clocks = <&clkc CLKID_I2C>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- uart_B: serial@23000 { +- compatible = "amlogic,meson-gx-uart"; +- reg = <0x0 0x23000 0x0 0x18>; +- interrupts = ; +- status = "disabled"; +- clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +- }; +- +- uart_A: serial@24000 { +- compatible = "amlogic,meson-gx-uart"; +- reg = <0x0 0x24000 0x0 0x18>; +- interrupts = ; +- status = "disabled"; +- clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +- fifo-size = <128>; +- }; +- }; +- +- apb: bus@ffe00000 { +- compatible = "simple-bus"; +- reg = <0x0 0xffe00000 0x0 0x200000>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; +- +- sd_emmc_b: sd@5000 { +- compatible = "amlogic,meson-axg-mmc"; +- reg = <0x0 0x5000 0x0 0x800>; +- interrupts = ; +- status = "disabled"; +- clocks = <&clkc CLKID_SD_EMMC_B>, +- <&clkc CLKID_SD_EMMC_B_CLK0>, +- <&clkc CLKID_FCLK_DIV2>; +- clock-names = "core", "clkin0", "clkin1"; +- resets = <&reset RESET_SD_EMMC_B>; +- }; +- +- sd_emmc_c: mmc@7000 { +- compatible = "amlogic,meson-axg-mmc"; +- reg = <0x0 0x7000 0x0 0x800>; +- interrupts = ; +- status = "disabled"; +- clocks = <&clkc CLKID_SD_EMMC_C>, +- <&clkc CLKID_SD_EMMC_C_CLK0>, +- <&clkc CLKID_FCLK_DIV2>; +- clock-names = "core", "clkin0", "clkin1"; +- resets = <&reset RESET_SD_EMMC_C>; +- }; +- +- usb2_phy1: phy@9020 { +- compatible = "amlogic,meson-gxl-usb2-phy"; +- #phy-cells = <0>; +- reg = <0x0 0x9020 0x0 0x20>; +- clocks = <&clkc CLKID_USB>; +- clock-names = "phy"; +- resets = <&reset RESET_USB_OTG>; +- reset-names = "phy"; +- }; +- }; +- +- sram: sram@fffc0000 { +- compatible = "mmio-sram"; +- reg = <0x0 0xfffc0000 0x0 0x20000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x0 0xfffc0000 0x20000>; +- +- cpu_scp_lpri: scp-sram@13000 { +- compatible = "amlogic,meson-axg-scp-shmem"; +- reg = <0x13000 0x400>; +- }; +- +- cpu_scp_hpri: scp-sram@13400 { +- compatible = "amlogic,meson-axg-scp-shmem"; +- reg = <0x13400 0x400>; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- xtal: xtal-clk { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "xtal"; +- #clock-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12-common.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12-common.dtsi +deleted file mode 100644 +index a3a1ea0f2134..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12-common.dtsi ++++ /dev/null +@@ -1,2444 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Amlogic, Inc. All rights reserved. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- mmc0 = &sd_emmc_b; /* SD card */ +- mmc1 = &sd_emmc_c; /* eMMC */ +- mmc2 = &sd_emmc_a; /* SDIO */ +- }; +- +- chosen { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- simplefb_cvbs: framebuffer-cvbs { +- compatible = "amlogic,simple-framebuffer", +- "simple-framebuffer"; +- amlogic,pipeline = "vpu-cvbs"; +- clocks = <&clkc CLKID_HDMI>, +- <&clkc CLKID_HTX_PCLK>, +- <&clkc CLKID_VPU_INTR>; +- status = "disabled"; +- }; +- +- simplefb_hdmi: framebuffer-hdmi { +- compatible = "amlogic,simple-framebuffer", +- "simple-framebuffer"; +- amlogic,pipeline = "vpu-hdmi"; +- clocks = <&clkc CLKID_HDMI>, +- <&clkc CLKID_HTX_PCLK>, +- <&clkc CLKID_VPU_INTR>; +- status = "disabled"; +- }; +- }; +- +- efuse: efuse { +- compatible = "amlogic,meson-gxbb-efuse"; +- clocks = <&clkc CLKID_EFUSE>; +- #address-cells = <1>; +- #size-cells = <1>; +- read-only; +- secure-monitor = <&sm>; +- }; +- +- gpu_opp_table: opp-table-gpu { +- compatible = "operating-points-v2"; +- +- opp-124999998 { +- opp-hz = /bits/ 64 <124999998>; +- opp-microvolt = <800000>; +- }; +- opp-249999996 { +- opp-hz = /bits/ 64 <249999996>; +- opp-microvolt = <800000>; +- }; +- opp-285714281 { +- opp-hz = /bits/ 64 <285714281>; +- opp-microvolt = <800000>; +- }; +- opp-399999994 { +- opp-hz = /bits/ 64 <399999994>; +- opp-microvolt = <800000>; +- }; +- opp-499999992 { +- opp-hz = /bits/ 64 <499999992>; +- opp-microvolt = <800000>; +- }; +- opp-666666656 { +- opp-hz = /bits/ 64 <666666656>; +- opp-microvolt = <800000>; +- }; +- opp-799999987 { +- opp-hz = /bits/ 64 <799999987>; +- opp-microvolt = <800000>; +- }; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ +- secmon_reserved: secmon@5000000 { +- reg = <0x0 0x05000000 0x0 0x300000>; +- no-map; +- }; +- +- /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ +- secmon_reserved_bl32: secmon@5300000 { +- reg = <0x0 0x05300000 0x0 0x2000000>; +- no-map; +- }; +- +- linux,cma { +- compatible = "shared-dma-pool"; +- reusable; +- size = <0x0 0x10000000>; +- alignment = <0x0 0x400000>; +- linux,cma-default; +- }; +- }; +- +- sm: secure-monitor { +- compatible = "amlogic,meson-gxbb-sm"; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- pcie: pcie@fc000000 { +- compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; +- reg = <0x0 0xfc000000 0x0 0x400000>, +- <0x0 0xff648000 0x0 0x2000>, +- <0x0 0xfc400000 0x0 0x200000>; +- reg-names = "elbi", "cfg", "config"; +- interrupts = ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; +- bus-range = <0x0 0xff>; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000>, +- <0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; +- +- clocks = <&clkc CLKID_PCIE_PHY +- &clkc CLKID_PCIE_COMB +- &clkc CLKID_PCIE_PLL>; +- clock-names = "general", +- "pclk", +- "port"; +- resets = <&reset RESET_PCIE_CTRL_A>, +- <&reset RESET_PCIE_APB>; +- reset-names = "port", +- "apb"; +- num-lanes = <1>; +- phys = <&usb3_pcie_phy PHY_TYPE_PCIE>; +- phy-names = "pcie"; +- status = "disabled"; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay = <1000>; +- polling-delay-passive = <100>; +- thermal-sensors = <&cpu_temp>; +- +- trips { +- cpu_passive: cpu-passive { +- temperature = <85000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- +- cpu_hot: cpu-hot { +- temperature = <95000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "hot"; +- }; +- +- cpu_critical: cpu-critical { +- temperature = <110000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- }; +- +- ddr_thermal: ddr-thermal { +- polling-delay = <1000>; +- polling-delay-passive = <100>; +- thermal-sensors = <&ddr_temp>; +- +- trips { +- ddr_passive: ddr-passive { +- temperature = <85000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- +- ddr_critical: ddr-critical { +- temperature = <110000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map { +- trip = <&ddr_passive>; +- cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- ethmac: ethernet@ff3f0000 { +- compatible = "amlogic,meson-g12a-dwmac", +- "snps,dwmac-3.70a", +- "snps,dwmac"; +- reg = <0x0 0xff3f0000 0x0 0x10000>, +- <0x0 0xff634540 0x0 0x8>; +- interrupts = ; +- interrupt-names = "macirq"; +- clocks = <&clkc CLKID_ETH>, +- <&clkc CLKID_FCLK_DIV2>, +- <&clkc CLKID_MPLL2>, +- <&clkc CLKID_FCLK_DIV2>; +- clock-names = "stmmaceth", "clkin0", "clkin1", +- "timing-adjustment"; +- rx-fifo-depth = <4096>; +- tx-fifo-depth = <2048>; +- status = "disabled"; +- +- mdio0: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- }; +- }; +- +- apb: bus@ff600000 { +- compatible = "simple-bus"; +- reg = <0x0 0xff600000 0x0 0x200000>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; +- +- hdmi_tx: hdmi-tx@0 { +- compatible = "amlogic,meson-g12a-dw-hdmi"; +- reg = <0x0 0x0 0x0 0x10000>; +- interrupts = ; +- resets = <&reset RESET_HDMITX_CAPB3>, +- <&reset RESET_HDMITX_PHY>, +- <&reset RESET_HDMITX>; +- reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; +- clocks = <&clkc CLKID_HDMI>, +- <&clkc CLKID_HTX_PCLK>, +- <&clkc CLKID_VPU_INTR>; +- clock-names = "isfr", "iahb", "venci"; +- #address-cells = <1>; +- #size-cells = <0>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- +- /* VPU VENC Input */ +- hdmi_tx_venc_port: port@0 { +- reg = <0>; +- +- hdmi_tx_in: endpoint { +- remote-endpoint = <&hdmi_tx_out>; +- }; +- }; +- +- /* TMDS Output */ +- hdmi_tx_tmds_port: port@1 { +- reg = <1>; +- }; +- }; +- +- apb_efuse: bus@30000 { +- compatible = "simple-bus"; +- reg = <0x0 0x30000 0x0 0x2000>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; +- +- hwrng: rng@218 { +- compatible = "amlogic,meson-rng"; +- reg = <0x0 0x218 0x0 0x4>; +- clocks = <&clkc CLKID_RNG0>; +- clock-names = "core"; +- }; +- }; +- +- acodec: audio-controller@32000 { +- compatible = "amlogic,t9015"; +- reg = <0x0 0x32000 0x0 0x14>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "ACODEC"; +- clocks = <&clkc CLKID_AUDIO_CODEC>; +- clock-names = "pclk"; +- resets = <&reset RESET_AUDIO_CODEC>; +- status = "disabled"; +- }; +- +- periphs: bus@34400 { +- compatible = "simple-bus"; +- reg = <0x0 0x34400 0x0 0x400>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; +- +- periphs_pinctrl: pinctrl@40 { +- compatible = "amlogic,meson-g12a-periphs-pinctrl"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gpio: bank@40 { +- reg = <0x0 0x40 0x0 0x4c>, +- <0x0 0xe8 0x0 0x18>, +- <0x0 0x120 0x0 0x18>, +- <0x0 0x2c0 0x0 0x40>, +- <0x0 0x340 0x0 0x1c>; +- reg-names = "gpio", +- "pull", +- "pull-enable", +- "mux", +- "ds"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&periphs_pinctrl 0 0 86>; +- }; +- +- cec_ao_a_h_pins: cec_ao_a_h { +- mux { +- groups = "cec_ao_a_h"; +- function = "cec_ao_a_h"; +- bias-disable; +- }; +- }; +- +- cec_ao_b_h_pins: cec_ao_b_h { +- mux { +- groups = "cec_ao_b_h"; +- function = "cec_ao_b_h"; +- bias-disable; +- }; +- }; +- +- emmc_ctrl_pins: emmc-ctrl { +- mux-0 { +- groups = "emmc_cmd"; +- function = "emmc"; +- bias-pull-up; +- drive-strength-microamp = <4000>; +- }; +- +- mux-1 { +- groups = "emmc_clk"; +- function = "emmc"; +- bias-disable; +- drive-strength-microamp = <4000>; +- }; +- }; +- +- emmc_data_4b_pins: emmc-data-4b { +- mux-0 { +- groups = "emmc_nand_d0", +- "emmc_nand_d1", +- "emmc_nand_d2", +- "emmc_nand_d3"; +- function = "emmc"; +- bias-pull-up; +- drive-strength-microamp = <4000>; +- }; +- }; +- +- emmc_data_8b_pins: emmc-data-8b { +- mux-0 { +- groups = "emmc_nand_d0", +- "emmc_nand_d1", +- "emmc_nand_d2", +- "emmc_nand_d3", +- "emmc_nand_d4", +- "emmc_nand_d5", +- "emmc_nand_d6", +- "emmc_nand_d7"; +- function = "emmc"; +- bias-pull-up; +- drive-strength-microamp = <4000>; +- }; +- }; +- +- emmc_ds_pins: emmc-ds { +- mux { +- groups = "emmc_nand_ds"; +- function = "emmc"; +- bias-pull-down; +- drive-strength-microamp = <4000>; +- }; +- }; +- +- emmc_clk_gate_pins: emmc_clk_gate { +- mux { +- groups = "BOOT_8"; +- function = "gpio_periphs"; +- bias-pull-down; +- drive-strength-microamp = <4000>; +- }; +- }; +- +- hdmitx_ddc_pins: hdmitx_ddc { +- mux { +- groups = "hdmitx_sda", +- "hdmitx_sck"; +- function = "hdmitx"; +- bias-disable; +- drive-strength-microamp = <4000>; +- }; +- }; +- +- hdmitx_hpd_pins: hdmitx_hpd { +- mux { +- groups = "hdmitx_hpd_in"; +- function = "hdmitx"; +- bias-disable; +- }; +- }; +- +- +- i2c0_sda_c_pins: i2c0-sda-c { +- mux { +- groups = "i2c0_sda_c"; +- function = "i2c0"; +- bias-disable; +- drive-strength-microamp = <3000>; +- +- }; +- }; +- +- i2c0_sck_c_pins: i2c0-sck-c { +- mux { +- groups = "i2c0_sck_c"; +- function = "i2c0"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c0_sda_z0_pins: i2c0-sda-z0 { +- mux { +- groups = "i2c0_sda_z0"; +- function = "i2c0"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c0_sck_z1_pins: i2c0-sck-z1 { +- mux { +- groups = "i2c0_sck_z1"; +- function = "i2c0"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c0_sda_z7_pins: i2c0-sda-z7 { +- mux { +- groups = "i2c0_sda_z7"; +- function = "i2c0"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c0_sda_z8_pins: i2c0-sda-z8 { +- mux { +- groups = "i2c0_sda_z8"; +- function = "i2c0"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c1_sda_x_pins: i2c1-sda-x { +- mux { +- groups = "i2c1_sda_x"; +- function = "i2c1"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c1_sck_x_pins: i2c1-sck-x { +- mux { +- groups = "i2c1_sck_x"; +- function = "i2c1"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c1_sda_h2_pins: i2c1-sda-h2 { +- mux { +- groups = "i2c1_sda_h2"; +- function = "i2c1"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c1_sck_h3_pins: i2c1-sck-h3 { +- mux { +- groups = "i2c1_sck_h3"; +- function = "i2c1"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c1_sda_h6_pins: i2c1-sda-h6 { +- mux { +- groups = "i2c1_sda_h6"; +- function = "i2c1"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c1_sck_h7_pins: i2c1-sck-h7 { +- mux { +- groups = "i2c1_sck_h7"; +- function = "i2c1"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c2_sda_x_pins: i2c2-sda-x { +- mux { +- groups = "i2c2_sda_x"; +- function = "i2c2"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c2_sck_x_pins: i2c2-sck-x { +- mux { +- groups = "i2c2_sck_x"; +- function = "i2c2"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c2_sda_z_pins: i2c2-sda-z { +- mux { +- groups = "i2c2_sda_z"; +- function = "i2c2"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c2_sck_z_pins: i2c2-sck-z { +- mux { +- groups = "i2c2_sck_z"; +- function = "i2c2"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c3_sda_h_pins: i2c3-sda-h { +- mux { +- groups = "i2c3_sda_h"; +- function = "i2c3"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c3_sck_h_pins: i2c3-sck-h { +- mux { +- groups = "i2c3_sck_h"; +- function = "i2c3"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c3_sda_a_pins: i2c3-sda-a { +- mux { +- groups = "i2c3_sda_a"; +- function = "i2c3"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c3_sck_a_pins: i2c3-sck-a { +- mux { +- groups = "i2c3_sck_a"; +- function = "i2c3"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- mclk0_a_pins: mclk0-a { +- mux { +- groups = "mclk0_a"; +- function = "mclk0"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- mclk1_a_pins: mclk1-a { +- mux { +- groups = "mclk1_a"; +- function = "mclk1"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- mclk1_x_pins: mclk1-x { +- mux { +- groups = "mclk1_x"; +- function = "mclk1"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- mclk1_z_pins: mclk1-z { +- mux { +- groups = "mclk1_z"; +- function = "mclk1"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- nor_pins: nor { +- mux { +- groups = "nor_d", +- "nor_q", +- "nor_c", +- "nor_cs"; +- function = "nor"; +- bias-disable; +- }; +- }; +- +- pdm_din0_a_pins: pdm-din0-a { +- mux { +- groups = "pdm_din0_a"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_din0_c_pins: pdm-din0-c { +- mux { +- groups = "pdm_din0_c"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_din0_x_pins: pdm-din0-x { +- mux { +- groups = "pdm_din0_x"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_din0_z_pins: pdm-din0-z { +- mux { +- groups = "pdm_din0_z"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_din1_a_pins: pdm-din1-a { +- mux { +- groups = "pdm_din1_a"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_din1_c_pins: pdm-din1-c { +- mux { +- groups = "pdm_din1_c"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_din1_x_pins: pdm-din1-x { +- mux { +- groups = "pdm_din1_x"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_din1_z_pins: pdm-din1-z { +- mux { +- groups = "pdm_din1_z"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_din2_a_pins: pdm-din2-a { +- mux { +- groups = "pdm_din2_a"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_din2_c_pins: pdm-din2-c { +- mux { +- groups = "pdm_din2_c"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_din2_x_pins: pdm-din2-x { +- mux { +- groups = "pdm_din2_x"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_din2_z_pins: pdm-din2-z { +- mux { +- groups = "pdm_din2_z"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_din3_a_pins: pdm-din3-a { +- mux { +- groups = "pdm_din3_a"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_din3_c_pins: pdm-din3-c { +- mux { +- groups = "pdm_din3_c"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_din3_x_pins: pdm-din3-x { +- mux { +- groups = "pdm_din3_x"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_din3_z_pins: pdm-din3-z { +- mux { +- groups = "pdm_din3_z"; +- function = "pdm"; +- bias-disable; +- }; +- }; +- +- pdm_dclk_a_pins: pdm-dclk-a { +- mux { +- groups = "pdm_dclk_a"; +- function = "pdm"; +- bias-disable; +- drive-strength-microamp = <500>; +- }; +- }; +- +- pdm_dclk_c_pins: pdm-dclk-c { +- mux { +- groups = "pdm_dclk_c"; +- function = "pdm"; +- bias-disable; +- drive-strength-microamp = <500>; +- }; +- }; +- +- pdm_dclk_x_pins: pdm-dclk-x { +- mux { +- groups = "pdm_dclk_x"; +- function = "pdm"; +- bias-disable; +- drive-strength-microamp = <500>; +- }; +- }; +- +- pdm_dclk_z_pins: pdm-dclk-z { +- mux { +- groups = "pdm_dclk_z"; +- function = "pdm"; +- bias-disable; +- drive-strength-microamp = <500>; +- }; +- }; +- +- pwm_a_pins: pwm-a { +- mux { +- groups = "pwm_a"; +- function = "pwm_a"; +- bias-disable; +- }; +- }; +- +- pwm_b_x7_pins: pwm-b-x7 { +- mux { +- groups = "pwm_b_x7"; +- function = "pwm_b"; +- bias-disable; +- }; +- }; +- +- pwm_b_x19_pins: pwm-b-x19 { +- mux { +- groups = "pwm_b_x19"; +- function = "pwm_b"; +- bias-disable; +- }; +- }; +- +- pwm_c_c_pins: pwm-c-c { +- mux { +- groups = "pwm_c_c"; +- function = "pwm_c"; +- bias-disable; +- }; +- }; +- +- pwm_c_x5_pins: pwm-c-x5 { +- mux { +- groups = "pwm_c_x5"; +- function = "pwm_c"; +- bias-disable; +- }; +- }; +- +- pwm_c_x8_pins: pwm-c-x8 { +- mux { +- groups = "pwm_c_x8"; +- function = "pwm_c"; +- bias-disable; +- }; +- }; +- +- pwm_d_x3_pins: pwm-d-x3 { +- mux { +- groups = "pwm_d_x3"; +- function = "pwm_d"; +- bias-disable; +- }; +- }; +- +- pwm_d_x6_pins: pwm-d-x6 { +- mux { +- groups = "pwm_d_x6"; +- function = "pwm_d"; +- bias-disable; +- }; +- }; +- +- pwm_e_pins: pwm-e { +- mux { +- groups = "pwm_e"; +- function = "pwm_e"; +- bias-disable; +- }; +- }; +- +- pwm_f_x_pins: pwm-f-x { +- mux { +- groups = "pwm_f_x"; +- function = "pwm_f"; +- bias-disable; +- }; +- }; +- +- pwm_f_h_pins: pwm-f-h { +- mux { +- groups = "pwm_f_h"; +- function = "pwm_f"; +- bias-disable; +- }; +- }; +- +- sdcard_c_pins: sdcard_c { +- mux-0 { +- groups = "sdcard_d0_c", +- "sdcard_d1_c", +- "sdcard_d2_c", +- "sdcard_d3_c", +- "sdcard_cmd_c"; +- function = "sdcard"; +- bias-pull-up; +- drive-strength-microamp = <4000>; +- }; +- +- mux-1 { +- groups = "sdcard_clk_c"; +- function = "sdcard"; +- bias-disable; +- drive-strength-microamp = <4000>; +- }; +- }; +- +- sdcard_clk_gate_c_pins: sdcard_clk_gate_c { +- mux { +- groups = "GPIOC_4"; +- function = "gpio_periphs"; +- bias-pull-down; +- drive-strength-microamp = <4000>; +- }; +- }; +- +- sdcard_z_pins: sdcard_z { +- mux-0 { +- groups = "sdcard_d0_z", +- "sdcard_d1_z", +- "sdcard_d2_z", +- "sdcard_d3_z", +- "sdcard_cmd_z"; +- function = "sdcard"; +- bias-pull-up; +- drive-strength-microamp = <4000>; +- }; +- +- mux-1 { +- groups = "sdcard_clk_z"; +- function = "sdcard"; +- bias-disable; +- drive-strength-microamp = <4000>; +- }; +- }; +- +- sdcard_clk_gate_z_pins: sdcard_clk_gate_z { +- mux { +- groups = "GPIOZ_6"; +- function = "gpio_periphs"; +- bias-pull-down; +- drive-strength-microamp = <4000>; +- }; +- }; +- +- sdio_pins: sdio { +- mux { +- groups = "sdio_d0", +- "sdio_d1", +- "sdio_d2", +- "sdio_d3", +- "sdio_clk", +- "sdio_cmd"; +- function = "sdio"; +- bias-disable; +- drive-strength-microamp = <4000>; +- }; +- }; +- +- sdio_clk_gate_pins: sdio_clk_gate { +- mux { +- groups = "GPIOX_4"; +- function = "gpio_periphs"; +- bias-pull-down; +- drive-strength-microamp = <4000>; +- }; +- }; +- +- spdif_in_a10_pins: spdif-in-a10 { +- mux { +- groups = "spdif_in_a10"; +- function = "spdif_in"; +- bias-disable; +- }; +- }; +- +- spdif_in_a12_pins: spdif-in-a12 { +- mux { +- groups = "spdif_in_a12"; +- function = "spdif_in"; +- bias-disable; +- }; +- }; +- +- spdif_in_h_pins: spdif-in-h { +- mux { +- groups = "spdif_in_h"; +- function = "spdif_in"; +- bias-disable; +- }; +- }; +- +- spdif_out_h_pins: spdif-out-h { +- mux { +- groups = "spdif_out_h"; +- function = "spdif_out"; +- drive-strength-microamp = <500>; +- bias-disable; +- }; +- }; +- +- spdif_out_a11_pins: spdif-out-a11 { +- mux { +- groups = "spdif_out_a11"; +- function = "spdif_out"; +- drive-strength-microamp = <500>; +- bias-disable; +- }; +- }; +- +- spdif_out_a13_pins: spdif-out-a13 { +- mux { +- groups = "spdif_out_a13"; +- function = "spdif_out"; +- drive-strength-microamp = <500>; +- bias-disable; +- }; +- }; +- +- spicc0_x_pins: spicc0-x { +- mux { +- groups = "spi0_mosi_x", +- "spi0_miso_x", +- "spi0_clk_x"; +- function = "spi0"; +- drive-strength-microamp = <4000>; +- bias-disable; +- }; +- }; +- +- spicc0_ss0_x_pins: spicc0-ss0-x { +- mux { +- groups = "spi0_ss0_x"; +- function = "spi0"; +- drive-strength-microamp = <4000>; +- bias-disable; +- }; +- }; +- +- spicc0_c_pins: spicc0-c { +- mux { +- groups = "spi0_mosi_c", +- "spi0_miso_c", +- "spi0_ss0_c", +- "spi0_clk_c"; +- function = "spi0"; +- drive-strength-microamp = <4000>; +- bias-disable; +- }; +- }; +- +- spicc1_pins: spicc1 { +- mux { +- groups = "spi1_mosi", +- "spi1_miso", +- "spi1_clk"; +- function = "spi1"; +- drive-strength-microamp = <4000>; +- }; +- }; +- +- spicc1_ss0_pins: spicc1-ss0 { +- mux { +- groups = "spi1_ss0"; +- function = "spi1"; +- drive-strength-microamp = <4000>; +- bias-disable; +- }; +- }; +- +- tdm_a_din0_pins: tdm-a-din0 { +- mux { +- groups = "tdm_a_din0"; +- function = "tdm_a"; +- bias-disable; +- }; +- }; +- +- +- tdm_a_din1_pins: tdm-a-din1 { +- mux { +- groups = "tdm_a_din1"; +- function = "tdm_a"; +- bias-disable; +- }; +- }; +- +- tdm_a_dout0_pins: tdm-a-dout0 { +- mux { +- groups = "tdm_a_dout0"; +- function = "tdm_a"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_a_dout1_pins: tdm-a-dout1 { +- mux { +- groups = "tdm_a_dout1"; +- function = "tdm_a"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_a_fs_pins: tdm-a-fs { +- mux { +- groups = "tdm_a_fs"; +- function = "tdm_a"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_a_sclk_pins: tdm-a-sclk { +- mux { +- groups = "tdm_a_sclk"; +- function = "tdm_a"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_a_slv_fs_pins: tdm-a-slv-fs { +- mux { +- groups = "tdm_a_slv_fs"; +- function = "tdm_a"; +- bias-disable; +- }; +- }; +- +- +- tdm_a_slv_sclk_pins: tdm-a-slv-sclk { +- mux { +- groups = "tdm_a_slv_sclk"; +- function = "tdm_a"; +- bias-disable; +- }; +- }; +- +- tdm_b_din0_pins: tdm-b-din0 { +- mux { +- groups = "tdm_b_din0"; +- function = "tdm_b"; +- bias-disable; +- }; +- }; +- +- tdm_b_din1_pins: tdm-b-din1 { +- mux { +- groups = "tdm_b_din1"; +- function = "tdm_b"; +- bias-disable; +- }; +- }; +- +- tdm_b_din2_pins: tdm-b-din2 { +- mux { +- groups = "tdm_b_din2"; +- function = "tdm_b"; +- bias-disable; +- }; +- }; +- +- tdm_b_din3_a_pins: tdm-b-din3-a { +- mux { +- groups = "tdm_b_din3_a"; +- function = "tdm_b"; +- bias-disable; +- }; +- }; +- +- tdm_b_din3_h_pins: tdm-b-din3-h { +- mux { +- groups = "tdm_b_din3_h"; +- function = "tdm_b"; +- bias-disable; +- }; +- }; +- +- tdm_b_dout0_pins: tdm-b-dout0 { +- mux { +- groups = "tdm_b_dout0"; +- function = "tdm_b"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_b_dout1_pins: tdm-b-dout1 { +- mux { +- groups = "tdm_b_dout1"; +- function = "tdm_b"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_b_dout2_pins: tdm-b-dout2 { +- mux { +- groups = "tdm_b_dout2"; +- function = "tdm_b"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_b_dout3_a_pins: tdm-b-dout3-a { +- mux { +- groups = "tdm_b_dout3_a"; +- function = "tdm_b"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_b_dout3_h_pins: tdm-b-dout3-h { +- mux { +- groups = "tdm_b_dout3_h"; +- function = "tdm_b"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_b_fs_pins: tdm-b-fs { +- mux { +- groups = "tdm_b_fs"; +- function = "tdm_b"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_b_sclk_pins: tdm-b-sclk { +- mux { +- groups = "tdm_b_sclk"; +- function = "tdm_b"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_b_slv_fs_pins: tdm-b-slv-fs { +- mux { +- groups = "tdm_b_slv_fs"; +- function = "tdm_b"; +- bias-disable; +- }; +- }; +- +- tdm_b_slv_sclk_pins: tdm-b-slv-sclk { +- mux { +- groups = "tdm_b_slv_sclk"; +- function = "tdm_b"; +- bias-disable; +- }; +- }; +- +- tdm_c_din0_a_pins: tdm-c-din0-a { +- mux { +- groups = "tdm_c_din0_a"; +- function = "tdm_c"; +- bias-disable; +- }; +- }; +- +- tdm_c_din0_z_pins: tdm-c-din0-z { +- mux { +- groups = "tdm_c_din0_z"; +- function = "tdm_c"; +- bias-disable; +- }; +- }; +- +- tdm_c_din1_a_pins: tdm-c-din1-a { +- mux { +- groups = "tdm_c_din1_a"; +- function = "tdm_c"; +- bias-disable; +- }; +- }; +- +- tdm_c_din1_z_pins: tdm-c-din1-z { +- mux { +- groups = "tdm_c_din1_z"; +- function = "tdm_c"; +- bias-disable; +- }; +- }; +- +- tdm_c_din2_a_pins: tdm-c-din2-a { +- mux { +- groups = "tdm_c_din2_a"; +- function = "tdm_c"; +- bias-disable; +- }; +- }; +- +- eth_leds_pins: eth-leds { +- mux { +- groups = "eth_link_led", +- "eth_act_led"; +- function = "eth"; +- bias-disable; +- }; +- }; +- +- eth_pins: eth { +- mux { +- groups = "eth_mdio", +- "eth_mdc", +- "eth_rgmii_rx_clk", +- "eth_rx_dv", +- "eth_rxd0", +- "eth_rxd1", +- "eth_txen", +- "eth_txd0", +- "eth_txd1"; +- function = "eth"; +- drive-strength-microamp = <4000>; +- bias-disable; +- }; +- }; +- +- eth_rgmii_pins: eth-rgmii { +- mux { +- groups = "eth_rxd2_rgmii", +- "eth_rxd3_rgmii", +- "eth_rgmii_tx_clk", +- "eth_txd2_rgmii", +- "eth_txd3_rgmii"; +- function = "eth"; +- drive-strength-microamp = <4000>; +- bias-disable; +- }; +- }; +- +- tdm_c_din2_z_pins: tdm-c-din2-z { +- mux { +- groups = "tdm_c_din2_z"; +- function = "tdm_c"; +- bias-disable; +- }; +- }; +- +- tdm_c_din3_a_pins: tdm-c-din3-a { +- mux { +- groups = "tdm_c_din3_a"; +- function = "tdm_c"; +- bias-disable; +- }; +- }; +- +- tdm_c_din3_z_pins: tdm-c-din3-z { +- mux { +- groups = "tdm_c_din3_z"; +- function = "tdm_c"; +- bias-disable; +- }; +- }; +- +- tdm_c_dout0_a_pins: tdm-c-dout0-a { +- mux { +- groups = "tdm_c_dout0_a"; +- function = "tdm_c"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_c_dout0_z_pins: tdm-c-dout0-z { +- mux { +- groups = "tdm_c_dout0_z"; +- function = "tdm_c"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_c_dout1_a_pins: tdm-c-dout1-a { +- mux { +- groups = "tdm_c_dout1_a"; +- function = "tdm_c"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_c_dout1_z_pins: tdm-c-dout1-z { +- mux { +- groups = "tdm_c_dout1_z"; +- function = "tdm_c"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_c_dout2_a_pins: tdm-c-dout2-a { +- mux { +- groups = "tdm_c_dout2_a"; +- function = "tdm_c"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_c_dout2_z_pins: tdm-c-dout2-z { +- mux { +- groups = "tdm_c_dout2_z"; +- function = "tdm_c"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_c_dout3_a_pins: tdm-c-dout3-a { +- mux { +- groups = "tdm_c_dout3_a"; +- function = "tdm_c"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_c_dout3_z_pins: tdm-c-dout3-z { +- mux { +- groups = "tdm_c_dout3_z"; +- function = "tdm_c"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_c_fs_a_pins: tdm-c-fs-a { +- mux { +- groups = "tdm_c_fs_a"; +- function = "tdm_c"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_c_fs_z_pins: tdm-c-fs-z { +- mux { +- groups = "tdm_c_fs_z"; +- function = "tdm_c"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_c_sclk_a_pins: tdm-c-sclk-a { +- mux { +- groups = "tdm_c_sclk_a"; +- function = "tdm_c"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_c_sclk_z_pins: tdm-c-sclk-z { +- mux { +- groups = "tdm_c_sclk_z"; +- function = "tdm_c"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { +- mux { +- groups = "tdm_c_slv_fs_a"; +- function = "tdm_c"; +- bias-disable; +- }; +- }; +- +- tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { +- mux { +- groups = "tdm_c_slv_fs_z"; +- function = "tdm_c"; +- bias-disable; +- }; +- }; +- +- tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { +- mux { +- groups = "tdm_c_slv_sclk_a"; +- function = "tdm_c"; +- bias-disable; +- }; +- }; +- +- tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { +- mux { +- groups = "tdm_c_slv_sclk_z"; +- function = "tdm_c"; +- bias-disable; +- }; +- }; +- +- uart_a_pins: uart-a { +- mux { +- groups = "uart_a_tx", +- "uart_a_rx"; +- function = "uart_a"; +- bias-disable; +- }; +- }; +- +- uart_a_cts_rts_pins: uart-a-cts-rts { +- mux { +- groups = "uart_a_cts", +- "uart_a_rts"; +- function = "uart_a"; +- bias-disable; +- }; +- }; +- +- uart_b_pins: uart-b { +- mux { +- groups = "uart_b_tx", +- "uart_b_rx"; +- function = "uart_b"; +- bias-disable; +- }; +- }; +- +- uart_c_pins: uart-c { +- mux { +- groups = "uart_c_tx", +- "uart_c_rx"; +- function = "uart_c"; +- bias-disable; +- }; +- }; +- +- uart_c_cts_rts_pins: uart-c-cts-rts { +- mux { +- groups = "uart_c_cts", +- "uart_c_rts"; +- function = "uart_c"; +- bias-disable; +- }; +- }; +- }; +- }; +- +- cpu_temp: temperature-sensor@34800 { +- compatible = "amlogic,g12a-cpu-thermal", +- "amlogic,g12a-thermal"; +- reg = <0x0 0x34800 0x0 0x50>; +- interrupts = ; +- clocks = <&clkc CLKID_TS>; +- #thermal-sensor-cells = <0>; +- amlogic,ao-secure = <&sec_AO>; +- }; +- +- ddr_temp: temperature-sensor@34c00 { +- compatible = "amlogic,g12a-ddr-thermal", +- "amlogic,g12a-thermal"; +- reg = <0x0 0x34c00 0x0 0x50>; +- interrupts = ; +- clocks = <&clkc CLKID_TS>; +- #thermal-sensor-cells = <0>; +- amlogic,ao-secure = <&sec_AO>; +- }; +- +- usb2_phy0: phy@36000 { +- compatible = "amlogic,g12a-usb2-phy"; +- reg = <0x0 0x36000 0x0 0x2000>; +- clocks = <&xtal>; +- clock-names = "xtal"; +- resets = <&reset RESET_USB_PHY20>; +- reset-names = "phy"; +- #phy-cells = <0>; +- }; +- +- dmc: bus@38000 { +- compatible = "simple-bus"; +- reg = <0x0 0x38000 0x0 0x400>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; +- +- canvas: video-lut@48 { +- compatible = "amlogic,canvas"; +- reg = <0x0 0x48 0x0 0x14>; +- }; +- }; +- +- usb2_phy1: phy@3a000 { +- compatible = "amlogic,g12a-usb2-phy"; +- reg = <0x0 0x3a000 0x0 0x2000>; +- clocks = <&xtal>; +- clock-names = "xtal"; +- resets = <&reset RESET_USB_PHY21>; +- reset-names = "phy"; +- #phy-cells = <0>; +- }; +- +- hiu: bus@3c000 { +- compatible = "simple-bus"; +- reg = <0x0 0x3c000 0x0 0x1400>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; +- +- hhi: system-controller@0 { +- compatible = "amlogic,meson-gx-hhi-sysctrl", +- "simple-mfd", "syscon"; +- reg = <0 0 0 0x400>; +- +- clkc: clock-controller { +- compatible = "amlogic,g12a-clkc"; +- #clock-cells = <1>; +- clocks = <&xtal>; +- clock-names = "xtal"; +- }; +- +- pwrc: power-controller { +- compatible = "amlogic,meson-g12a-pwrc"; +- #power-domain-cells = <1>; +- amlogic,ao-sysctrl = <&rti>; +- resets = <&reset RESET_VIU>, +- <&reset RESET_VENC>, +- <&reset RESET_VCBUS>, +- <&reset RESET_BT656>, +- <&reset RESET_RDMA>, +- <&reset RESET_VENCI>, +- <&reset RESET_VENCP>, +- <&reset RESET_VDAC>, +- <&reset RESET_VDI6>, +- <&reset RESET_VENCL>, +- <&reset RESET_VID_LOCK>; +- reset-names = "viu", "venc", "vcbus", "bt656", +- "rdma", "venci", "vencp", "vdac", +- "vdi6", "vencl", "vid_lock"; +- clocks = <&clkc CLKID_VPU>, +- <&clkc CLKID_VAPB>; +- clock-names = "vpu", "vapb"; +- /* +- * VPU clocking is provided by two identical clock paths +- * VPU_0 and VPU_1 muxed to a single clock by a glitch +- * free mux to safely change frequency while running. +- * Same for VAPB but with a final gate after the glitch free mux. +- */ +- assigned-clocks = <&clkc CLKID_VPU_0_SEL>, +- <&clkc CLKID_VPU_0>, +- <&clkc CLKID_VPU>, /* Glitch free mux */ +- <&clkc CLKID_VAPB_0_SEL>, +- <&clkc CLKID_VAPB_0>, +- <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ +- assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, +- <0>, /* Do Nothing */ +- <&clkc CLKID_VPU_0>, +- <&clkc CLKID_FCLK_DIV4>, +- <0>, /* Do Nothing */ +- <&clkc CLKID_VAPB_0>; +- assigned-clock-rates = <0>, /* Do Nothing */ +- <666666666>, +- <0>, /* Do Nothing */ +- <0>, /* Do Nothing */ +- <250000000>, +- <0>; /* Do Nothing */ +- }; +- }; +- }; +- +- usb3_pcie_phy: phy@46000 { +- compatible = "amlogic,g12a-usb3-pcie-phy"; +- reg = <0x0 0x46000 0x0 0x2000>; +- clocks = <&clkc CLKID_PCIE_PLL>; +- clock-names = "ref_clk"; +- resets = <&reset RESET_PCIE_PHY>; +- reset-names = "phy"; +- assigned-clocks = <&clkc CLKID_PCIE_PLL>; +- assigned-clock-rates = <100000000>; +- #phy-cells = <1>; +- }; +- +- eth_phy: mdio-multiplexer@4c000 { +- compatible = "amlogic,g12a-mdio-mux"; +- reg = <0x0 0x4c000 0x0 0xa4>; +- clocks = <&clkc CLKID_ETH_PHY>, +- <&xtal>, +- <&clkc CLKID_MPLL_50M>; +- clock-names = "pclk", "clkin0", "clkin1"; +- mdio-parent-bus = <&mdio0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ext_mdio: mdio@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- int_mdio: mdio@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- internal_ephy: ethernet_phy@8 { +- compatible = "ethernet-phy-id0180.3301", +- "ethernet-phy-ieee802.3-c22"; +- interrupts = ; +- reg = <8>; +- max-speed = <100>; +- }; +- }; +- }; +- }; +- +- aobus: bus@ff800000 { +- compatible = "simple-bus"; +- reg = <0x0 0xff800000 0x0 0x100000>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; +- +- rti: sys-ctrl@0 { +- compatible = "amlogic,meson-gx-ao-sysctrl", +- "simple-mfd", "syscon"; +- reg = <0x0 0x0 0x0 0x100>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; +- +- clkc_AO: clock-controller { +- compatible = "amlogic,meson-g12a-aoclkc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- clocks = <&xtal>, <&clkc CLKID_CLK81>; +- clock-names = "xtal", "mpeg-clk"; +- }; +- +- ao_pinctrl: pinctrl@14 { +- compatible = "amlogic,meson-g12a-aobus-pinctrl"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gpio_ao: bank@14 { +- reg = <0x0 0x14 0x0 0x8>, +- <0x0 0x1c 0x0 0x8>, +- <0x0 0x24 0x0 0x14>; +- reg-names = "mux", +- "ds", +- "gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&ao_pinctrl 0 0 15>; +- }; +- +- i2c_ao_sck_pins: i2c_ao_sck_pins { +- mux { +- groups = "i2c_ao_sck"; +- function = "i2c_ao"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c_ao_sda_pins: i2c_ao_sda { +- mux { +- groups = "i2c_ao_sda"; +- function = "i2c_ao"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c_ao_sck_e_pins: i2c_ao_sck_e { +- mux { +- groups = "i2c_ao_sck_e"; +- function = "i2c_ao"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- i2c_ao_sda_e_pins: i2c_ao_sda_e { +- mux { +- groups = "i2c_ao_sda_e"; +- function = "i2c_ao"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- mclk0_ao_pins: mclk0-ao { +- mux { +- groups = "mclk0_ao"; +- function = "mclk0_ao"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_ao_b_din0_pins: tdm-ao-b-din0 { +- mux { +- groups = "tdm_ao_b_din0"; +- function = "tdm_ao_b"; +- bias-disable; +- }; +- }; +- +- spdif_ao_out_pins: spdif-ao-out { +- mux { +- groups = "spdif_ao_out"; +- function = "spdif_ao_out"; +- drive-strength-microamp = <500>; +- bias-disable; +- }; +- }; +- +- tdm_ao_b_din1_pins: tdm-ao-b-din1 { +- mux { +- groups = "tdm_ao_b_din1"; +- function = "tdm_ao_b"; +- bias-disable; +- }; +- }; +- +- tdm_ao_b_din2_pins: tdm-ao-b-din2 { +- mux { +- groups = "tdm_ao_b_din2"; +- function = "tdm_ao_b"; +- bias-disable; +- }; +- }; +- +- tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { +- mux { +- groups = "tdm_ao_b_dout0"; +- function = "tdm_ao_b"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { +- mux { +- groups = "tdm_ao_b_dout1"; +- function = "tdm_ao_b"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { +- mux { +- groups = "tdm_ao_b_dout2"; +- function = "tdm_ao_b"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_ao_b_fs_pins: tdm-ao-b-fs { +- mux { +- groups = "tdm_ao_b_fs"; +- function = "tdm_ao_b"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_ao_b_sclk_pins: tdm-ao-b-sclk { +- mux { +- groups = "tdm_ao_b_sclk"; +- function = "tdm_ao_b"; +- bias-disable; +- drive-strength-microamp = <3000>; +- }; +- }; +- +- tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { +- mux { +- groups = "tdm_ao_b_slv_fs"; +- function = "tdm_ao_b"; +- bias-disable; +- }; +- }; +- +- tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { +- mux { +- groups = "tdm_ao_b_slv_sclk"; +- function = "tdm_ao_b"; +- bias-disable; +- }; +- }; +- +- uart_ao_a_pins: uart-a-ao { +- mux { +- groups = "uart_ao_a_tx", +- "uart_ao_a_rx"; +- function = "uart_ao_a"; +- bias-disable; +- }; +- }; +- +- uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { +- mux { +- groups = "uart_ao_a_cts", +- "uart_ao_a_rts"; +- function = "uart_ao_a"; +- bias-disable; +- }; +- }; +- +- pwm_a_e_pins: pwm-a-e { +- mux { +- groups = "pwm_a_e"; +- function = "pwm_a_e"; +- bias-disable; +- }; +- }; +- +- pwm_ao_a_pins: pwm-ao-a { +- mux { +- groups = "pwm_ao_a"; +- function = "pwm_ao_a"; +- bias-disable; +- }; +- }; +- +- pwm_ao_b_pins: pwm-ao-b { +- mux { +- groups = "pwm_ao_b"; +- function = "pwm_ao_b"; +- bias-disable; +- }; +- }; +- +- pwm_ao_c_4_pins: pwm-ao-c-4 { +- mux { +- groups = "pwm_ao_c_4"; +- function = "pwm_ao_c"; +- bias-disable; +- }; +- }; +- +- pwm_ao_c_6_pins: pwm-ao-c-6 { +- mux { +- groups = "pwm_ao_c_6"; +- function = "pwm_ao_c"; +- bias-disable; +- }; +- }; +- +- pwm_ao_d_5_pins: pwm-ao-d-5 { +- mux { +- groups = "pwm_ao_d_5"; +- function = "pwm_ao_d"; +- bias-disable; +- }; +- }; +- +- pwm_ao_d_10_pins: pwm-ao-d-10 { +- mux { +- groups = "pwm_ao_d_10"; +- function = "pwm_ao_d"; +- bias-disable; +- }; +- }; +- +- pwm_ao_d_e_pins: pwm-ao-d-e { +- mux { +- groups = "pwm_ao_d_e"; +- function = "pwm_ao_d"; +- }; +- }; +- +- remote_input_ao_pins: remote-input-ao { +- mux { +- groups = "remote_ao_input"; +- function = "remote_ao_input"; +- bias-disable; +- }; +- }; +- }; +- }; +- +- vrtc: rtc@a8 { +- compatible = "amlogic,meson-vrtc"; +- reg = <0x0 0x000a8 0x0 0x4>; +- }; +- +- cec_AO: cec@100 { +- compatible = "amlogic,meson-gx-ao-cec"; +- reg = <0x0 0x00100 0x0 0x14>; +- interrupts = ; +- clocks = <&clkc_AO CLKID_AO_CEC>; +- clock-names = "core"; +- status = "disabled"; +- }; +- +- sec_AO: ao-secure@140 { +- compatible = "amlogic,meson-gx-ao-secure", "syscon"; +- reg = <0x0 0x140 0x0 0x140>; +- amlogic,has-chip-id; +- }; +- +- cecb_AO: cec@280 { +- compatible = "amlogic,meson-g12a-ao-cec"; +- reg = <0x0 0x00280 0x0 0x1c>; +- interrupts = ; +- clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; +- clock-names = "oscin"; +- status = "disabled"; +- }; +- +- pwm_AO_cd: pwm@2000 { +- compatible = "amlogic,meson-g12a-ao-pwm-cd"; +- reg = <0x0 0x2000 0x0 0x20>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- uart_AO: serial@3000 { +- compatible = "amlogic,meson-gx-uart", +- "amlogic,meson-ao-uart"; +- reg = <0x0 0x3000 0x0 0x18>; +- interrupts = ; +- clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +- status = "disabled"; +- }; +- +- uart_AO_B: serial@4000 { +- compatible = "amlogic,meson-gx-uart", +- "amlogic,meson-ao-uart"; +- reg = <0x0 0x4000 0x0 0x18>; +- interrupts = ; +- clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +- status = "disabled"; +- }; +- +- i2c_AO: i2c@5000 { +- compatible = "amlogic,meson-axg-i2c"; +- status = "disabled"; +- reg = <0x0 0x05000 0x0 0x20>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clkc CLKID_I2C>; +- }; +- +- pwm_AO_ab: pwm@7000 { +- compatible = "amlogic,meson-g12a-ao-pwm-ab"; +- reg = <0x0 0x7000 0x0 0x20>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- ir: ir@8000 { +- compatible = "amlogic,meson-gxbb-ir"; +- reg = <0x0 0x8000 0x0 0x20>; +- interrupts = ; +- status = "disabled"; +- }; +- +- saradc: adc@9000 { +- compatible = "amlogic,meson-g12a-saradc", +- "amlogic,meson-saradc"; +- reg = <0x0 0x9000 0x0 0x48>; +- #io-channel-cells = <1>; +- interrupts = ; +- clocks = <&xtal>, +- <&clkc_AO CLKID_AO_SAR_ADC>, +- <&clkc_AO CLKID_AO_SAR_ADC_CLK>, +- <&clkc_AO CLKID_AO_SAR_ADC_SEL>; +- clock-names = "clkin", "core", "adc_clk", "adc_sel"; +- status = "disabled"; +- }; +- }; +- +- vdec: video-decoder@ff620000 { +- compatible = "amlogic,g12a-vdec"; +- reg = <0x0 0xff620000 0x0 0x10000>, +- <0x0 0xffd0e180 0x0 0xe4>; +- reg-names = "dos", "esparser"; +- interrupts = , +- ; +- interrupt-names = "vdec", "esparser"; +- +- amlogic,ao-sysctrl = <&rti>; +- amlogic,canvas = <&canvas>; +- +- clocks = <&clkc CLKID_PARSER>, +- <&clkc CLKID_DOS>, +- <&clkc CLKID_VDEC_1>, +- <&clkc CLKID_VDEC_HEVC>, +- <&clkc CLKID_VDEC_HEVCF>; +- clock-names = "dos_parser", "dos", "vdec_1", +- "vdec_hevc", "vdec_hevcf"; +- resets = <&reset RESET_PARSER>; +- reset-names = "esparser"; +- }; +- +- vpu: vpu@ff900000 { +- compatible = "amlogic,meson-g12a-vpu"; +- reg = <0x0 0xff900000 0x0 0x100000>, +- <0x0 0xff63c000 0x0 0x1000>; +- reg-names = "vpu", "hhi"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- amlogic,canvas = <&canvas>; +- +- /* CVBS VDAC output port */ +- cvbs_vdac_port: port@0 { +- reg = <0>; +- }; +- +- /* HDMI-TX output port */ +- hdmi_tx_port: port@1 { +- reg = <1>; +- +- hdmi_tx_out: endpoint { +- remote-endpoint = <&hdmi_tx_in>; +- }; +- }; +- }; +- +- gic: interrupt-controller@ffc01000 { +- compatible = "arm,gic-400"; +- reg = <0x0 0xffc01000 0 0x1000>, +- <0x0 0xffc02000 0 0x2000>, +- <0x0 0xffc04000 0 0x2000>, +- <0x0 0xffc06000 0 0x2000>; +- interrupt-controller; +- interrupts = ; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- }; +- +- cbus: bus@ffd00000 { +- compatible = "simple-bus"; +- reg = <0x0 0xffd00000 0x0 0x100000>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; +- +- reset: reset-controller@1004 { +- compatible = "amlogic,meson-axg-reset"; +- reg = <0x0 0x1004 0x0 0x9c>; +- #reset-cells = <1>; +- }; +- +- gpio_intc: interrupt-controller@f080 { +- compatible = "amlogic,meson-g12a-gpio-intc", +- "amlogic,meson-gpio-intc"; +- reg = <0x0 0xf080 0x0 0x10>; +- interrupt-controller; +- #interrupt-cells = <2>; +- amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; +- }; +- +- watchdog: watchdog@f0d0 { +- compatible = "amlogic,meson-gxbb-wdt"; +- reg = <0x0 0xf0d0 0x0 0x10>; +- clocks = <&xtal>; +- }; +- +- spicc0: spi@13000 { +- compatible = "amlogic,meson-g12a-spicc"; +- reg = <0x0 0x13000 0x0 0x44>; +- interrupts = ; +- clocks = <&clkc CLKID_SPICC0>, +- <&clkc CLKID_SPICC0_SCLK>; +- clock-names = "core", "pclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spicc1: spi@15000 { +- compatible = "amlogic,meson-g12a-spicc"; +- reg = <0x0 0x15000 0x0 0x44>; +- interrupts = ; +- clocks = <&clkc CLKID_SPICC1>, +- <&clkc CLKID_SPICC1_SCLK>; +- clock-names = "core", "pclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spifc: spi@14000 { +- compatible = "amlogic,meson-gxbb-spifc"; +- status = "disabled"; +- reg = <0x0 0x14000 0x0 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clkc CLKID_CLK81>; +- }; +- +- pwm_ef: pwm@19000 { +- compatible = "amlogic,meson-g12a-ee-pwm"; +- reg = <0x0 0x19000 0x0 0x20>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm_cd: pwm@1a000 { +- compatible = "amlogic,meson-g12a-ee-pwm"; +- reg = <0x0 0x1a000 0x0 0x20>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm_ab: pwm@1b000 { +- compatible = "amlogic,meson-g12a-ee-pwm"; +- reg = <0x0 0x1b000 0x0 0x20>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- i2c3: i2c@1c000 { +- compatible = "amlogic,meson-axg-i2c"; +- status = "disabled"; +- reg = <0x0 0x1c000 0x0 0x20>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clkc CLKID_I2C>; +- }; +- +- i2c2: i2c@1d000 { +- compatible = "amlogic,meson-axg-i2c"; +- status = "disabled"; +- reg = <0x0 0x1d000 0x0 0x20>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clkc CLKID_I2C>; +- }; +- +- i2c1: i2c@1e000 { +- compatible = "amlogic,meson-axg-i2c"; +- status = "disabled"; +- reg = <0x0 0x1e000 0x0 0x20>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clkc CLKID_I2C>; +- }; +- +- i2c0: i2c@1f000 { +- compatible = "amlogic,meson-axg-i2c"; +- status = "disabled"; +- reg = <0x0 0x1f000 0x0 0x20>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clkc CLKID_I2C>; +- }; +- +- clk_msr: clock-measure@18000 { +- compatible = "amlogic,meson-g12a-clk-measure"; +- reg = <0x0 0x18000 0x0 0x10>; +- }; +- +- uart_C: serial@22000 { +- compatible = "amlogic,meson-gx-uart"; +- reg = <0x0 0x22000 0x0 0x18>; +- interrupts = ; +- clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +- status = "disabled"; +- }; +- +- uart_B: serial@23000 { +- compatible = "amlogic,meson-gx-uart"; +- reg = <0x0 0x23000 0x0 0x18>; +- interrupts = ; +- clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +- status = "disabled"; +- }; +- +- uart_A: serial@24000 { +- compatible = "amlogic,meson-gx-uart"; +- reg = <0x0 0x24000 0x0 0x18>; +- interrupts = ; +- clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +- status = "disabled"; +- fifo-size = <128>; +- }; +- }; +- +- sd_emmc_a: sd@ffe03000 { +- compatible = "amlogic,meson-axg-mmc"; +- reg = <0x0 0xffe03000 0x0 0x800>; +- interrupts = ; +- status = "disabled"; +- clocks = <&clkc CLKID_SD_EMMC_A>, +- <&clkc CLKID_SD_EMMC_A_CLK0>, +- <&clkc CLKID_FCLK_DIV2>; +- clock-names = "core", "clkin0", "clkin1"; +- resets = <&reset RESET_SD_EMMC_A>; +- }; +- +- sd_emmc_b: sd@ffe05000 { +- compatible = "amlogic,meson-axg-mmc"; +- reg = <0x0 0xffe05000 0x0 0x800>; +- interrupts = ; +- status = "disabled"; +- clocks = <&clkc CLKID_SD_EMMC_B>, +- <&clkc CLKID_SD_EMMC_B_CLK0>, +- <&clkc CLKID_FCLK_DIV2>; +- clock-names = "core", "clkin0", "clkin1"; +- resets = <&reset RESET_SD_EMMC_B>; +- }; +- +- sd_emmc_c: mmc@ffe07000 { +- compatible = "amlogic,meson-axg-mmc"; +- reg = <0x0 0xffe07000 0x0 0x800>; +- interrupts = ; +- status = "disabled"; +- clocks = <&clkc CLKID_SD_EMMC_C>, +- <&clkc CLKID_SD_EMMC_C_CLK0>, +- <&clkc CLKID_FCLK_DIV2>; +- clock-names = "core", "clkin0", "clkin1"; +- resets = <&reset RESET_SD_EMMC_C>; +- }; +- +- usb: usb@ffe09000 { +- status = "disabled"; +- compatible = "amlogic,meson-g12a-usb-ctrl"; +- reg = <0x0 0xffe09000 0x0 0xa0>; +- interrupts = ; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clocks = <&clkc CLKID_USB>; +- resets = <&reset RESET_USB>; +- +- dr_mode = "otg"; +- +- phys = <&usb2_phy0>, <&usb2_phy1>, +- <&usb3_pcie_phy PHY_TYPE_USB3>; +- phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; +- +- dwc2: usb@ff400000 { +- compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; +- reg = <0x0 0xff400000 0x0 0x40000>; +- interrupts = ; +- clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; +- clock-names = "otg"; +- phys = <&usb2_phy1>; +- phy-names = "usb2-phy"; +- dr_mode = "peripheral"; +- g-rx-fifo-size = <192>; +- g-np-tx-fifo-size = <128>; +- g-tx-fifo-size = <128 128 16 16 16>; +- }; +- +- dwc3: usb@ff500000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0xff500000 0x0 0x100000>; +- interrupts = ; +- dr_mode = "host"; +- snps,dis_u2_susphy_quirk; +- snps,quirk-frame-length-adjustment = <0x20>; +- snps,parkmode-disable-ss-quirk; +- }; +- }; +- +- mali: gpu@ffe40000 { +- compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; +- reg = <0x0 0xffe40000 0x0 0x40000>; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- ; +- interrupt-names = "job", "mmu", "gpu"; +- clocks = <&clkc CLKID_MALI>; +- resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; +- operating-points-v2 = <&gpu_opp_table>; +- #cooling-cells = <2>; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- arm,no-tick-in-suspend; +- }; +- +- xtal: xtal-clk { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "xtal"; +- #clock-cells = <0>; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12.dtsi +deleted file mode 100644 +index 6a1f4dcf6488..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12.dtsi ++++ /dev/null +@@ -1,385 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Jerome Brunet +- */ +- +-#include "meson-g12-common.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- tdmif_a: audio-controller-0 { +- compatible = "amlogic,axg-tdm-iface"; +- #sound-dai-cells = <0>; +- sound-name-prefix = "TDM_A"; +- clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, +- <&clkc_audio AUD_CLKID_MST_A_SCLK>, +- <&clkc_audio AUD_CLKID_MST_A_LRCLK>; +- clock-names = "mclk", "sclk", "lrclk"; +- status = "disabled"; +- }; +- +- tdmif_b: audio-controller-1 { +- compatible = "amlogic,axg-tdm-iface"; +- #sound-dai-cells = <0>; +- sound-name-prefix = "TDM_B"; +- clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, +- <&clkc_audio AUD_CLKID_MST_B_SCLK>, +- <&clkc_audio AUD_CLKID_MST_B_LRCLK>; +- clock-names = "mclk", "sclk", "lrclk"; +- status = "disabled"; +- }; +- +- tdmif_c: audio-controller-2 { +- compatible = "amlogic,axg-tdm-iface"; +- #sound-dai-cells = <0>; +- sound-name-prefix = "TDM_C"; +- clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, +- <&clkc_audio AUD_CLKID_MST_C_SCLK>, +- <&clkc_audio AUD_CLKID_MST_C_LRCLK>; +- clock-names = "mclk", "sclk", "lrclk"; +- status = "disabled"; +- }; +-}; +- +-&apb { +- pdm: audio-controller@40000 { +- compatible = "amlogic,g12a-pdm", +- "amlogic,axg-pdm"; +- reg = <0x0 0x40000 0x0 0x34>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "PDM"; +- clocks = <&clkc_audio AUD_CLKID_PDM>, +- <&clkc_audio AUD_CLKID_PDM_DCLK>, +- <&clkc_audio AUD_CLKID_PDM_SYSCLK>; +- clock-names = "pclk", "dclk", "sysclk"; +- resets = <&clkc_audio AUD_RESET_PDM>; +- status = "disabled"; +- }; +- +- audio: bus@42000 { +- compatible = "simple-bus"; +- reg = <0x0 0x42000 0x0 0x2000>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; +- +- clkc_audio: clock-controller@0 { +- status = "disabled"; +- compatible = "amlogic,g12a-audio-clkc"; +- reg = <0x0 0x0 0x0 0xb4>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- +- clocks = <&clkc CLKID_AUDIO>, +- <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>, +- <&clkc CLKID_MPLL2>, +- <&clkc CLKID_MPLL3>, +- <&clkc CLKID_HIFI_PLL>, +- <&clkc CLKID_FCLK_DIV3>, +- <&clkc CLKID_FCLK_DIV4>, +- <&clkc CLKID_GP0_PLL>; +- clock-names = "pclk", +- "mst_in0", +- "mst_in1", +- "mst_in2", +- "mst_in3", +- "mst_in4", +- "mst_in5", +- "mst_in6", +- "mst_in7"; +- +- resets = <&reset RESET_AUDIO>; +- }; +- +- toddr_a: audio-controller@100 { +- compatible = "amlogic,g12a-toddr", +- "amlogic,axg-toddr"; +- reg = <0x0 0x100 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "TODDR_A"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_TODDR_A>; +- resets = <&arb AXG_ARB_TODDR_A>, +- <&clkc_audio AUD_RESET_TODDR_A>; +- reset-names = "arb", "rst"; +- amlogic,fifo-depth = <512>; +- status = "disabled"; +- }; +- +- toddr_b: audio-controller@140 { +- compatible = "amlogic,g12a-toddr", +- "amlogic,axg-toddr"; +- reg = <0x0 0x140 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "TODDR_B"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_TODDR_B>; +- resets = <&arb AXG_ARB_TODDR_B>, +- <&clkc_audio AUD_RESET_TODDR_B>; +- reset-names = "arb", "rst"; +- amlogic,fifo-depth = <256>; +- status = "disabled"; +- }; +- +- toddr_c: audio-controller@180 { +- compatible = "amlogic,g12a-toddr", +- "amlogic,axg-toddr"; +- reg = <0x0 0x180 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "TODDR_C"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_TODDR_C>; +- resets = <&arb AXG_ARB_TODDR_C>, +- <&clkc_audio AUD_RESET_TODDR_C>; +- reset-names = "arb", "rst"; +- amlogic,fifo-depth = <256>; +- status = "disabled"; +- }; +- +- frddr_a: audio-controller@1c0 { +- compatible = "amlogic,g12a-frddr", +- "amlogic,axg-frddr"; +- reg = <0x0 0x1c0 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "FRDDR_A"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; +- resets = <&arb AXG_ARB_FRDDR_A>, +- <&clkc_audio AUD_RESET_FRDDR_A>; +- reset-names = "arb", "rst"; +- amlogic,fifo-depth = <512>; +- status = "disabled"; +- }; +- +- frddr_b: audio-controller@200 { +- compatible = "amlogic,g12a-frddr", +- "amlogic,axg-frddr"; +- reg = <0x0 0x200 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "FRDDR_B"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; +- resets = <&arb AXG_ARB_FRDDR_B>, +- <&clkc_audio AUD_RESET_FRDDR_B>; +- reset-names = "arb", "rst"; +- amlogic,fifo-depth = <256>; +- status = "disabled"; +- }; +- +- frddr_c: audio-controller@240 { +- compatible = "amlogic,g12a-frddr", +- "amlogic,axg-frddr"; +- reg = <0x0 0x240 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "FRDDR_C"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; +- resets = <&arb AXG_ARB_FRDDR_C>, +- <&clkc_audio AUD_RESET_FRDDR_C>; +- reset-names = "arb", "rst"; +- amlogic,fifo-depth = <256>; +- status = "disabled"; +- }; +- +- arb: reset-controller@280 { +- status = "disabled"; +- compatible = "amlogic,meson-axg-audio-arb"; +- reg = <0x0 0x280 0x0 0x4>; +- #reset-cells = <1>; +- clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; +- }; +- +- tdmin_a: audio-controller@300 { +- compatible = "amlogic,g12a-tdmin", +- "amlogic,axg-tdmin"; +- reg = <0x0 0x300 0x0 0x40>; +- sound-name-prefix = "TDMIN_A"; +- resets = <&clkc_audio AUD_RESET_TDMIN_A>; +- clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, +- <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- tdmin_b: audio-controller@340 { +- compatible = "amlogic,g12a-tdmin", +- "amlogic,axg-tdmin"; +- reg = <0x0 0x340 0x0 0x40>; +- sound-name-prefix = "TDMIN_B"; +- resets = <&clkc_audio AUD_RESET_TDMIN_B>; +- clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, +- <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- tdmin_c: audio-controller@380 { +- compatible = "amlogic,g12a-tdmin", +- "amlogic,axg-tdmin"; +- reg = <0x0 0x380 0x0 0x40>; +- sound-name-prefix = "TDMIN_C"; +- resets = <&clkc_audio AUD_RESET_TDMIN_C>; +- clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, +- <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- tdmin_lb: audio-controller@3c0 { +- compatible = "amlogic,g12a-tdmin", +- "amlogic,axg-tdmin"; +- reg = <0x0 0x3c0 0x0 0x40>; +- sound-name-prefix = "TDMIN_LB"; +- resets = <&clkc_audio AUD_RESET_TDMIN_LB>; +- clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, +- <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- spdifin: audio-controller@400 { +- compatible = "amlogic,g12a-spdifin", +- "amlogic,axg-spdifin"; +- reg = <0x0 0x400 0x0 0x30>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "SPDIFIN"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, +- <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; +- clock-names = "pclk", "refclk"; +- resets = <&clkc_audio AUD_RESET_SPDIFIN>; +- status = "disabled"; +- }; +- +- spdifout: audio-controller@480 { +- compatible = "amlogic,g12a-spdifout", +- "amlogic,axg-spdifout"; +- reg = <0x0 0x480 0x0 0x50>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "SPDIFOUT"; +- clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, +- <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; +- clock-names = "pclk", "mclk"; +- resets = <&clkc_audio AUD_RESET_SPDIFOUT>; +- status = "disabled"; +- }; +- +- tdmout_a: audio-controller@500 { +- compatible = "amlogic,g12a-tdmout"; +- reg = <0x0 0x500 0x0 0x40>; +- sound-name-prefix = "TDMOUT_A"; +- resets = <&clkc_audio AUD_RESET_TDMOUT_A>; +- clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, +- <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, +- <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- tdmout_b: audio-controller@540 { +- compatible = "amlogic,g12a-tdmout"; +- reg = <0x0 0x540 0x0 0x40>; +- sound-name-prefix = "TDMOUT_B"; +- resets = <&clkc_audio AUD_RESET_TDMOUT_B>; +- clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, +- <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, +- <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- tdmout_c: audio-controller@580 { +- compatible = "amlogic,g12a-tdmout"; +- reg = <0x0 0x580 0x0 0x40>; +- sound-name-prefix = "TDMOUT_C"; +- resets = <&clkc_audio AUD_RESET_TDMOUT_C>; +- clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, +- <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, +- <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- spdifout_b: audio-controller@680 { +- compatible = "amlogic,g12a-spdifout", +- "amlogic,axg-spdifout"; +- reg = <0x0 0x680 0x0 0x50>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "SPDIFOUT_B"; +- clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, +- <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; +- clock-names = "pclk", "mclk"; +- resets = <&clkc_audio AUD_RESET_SPDIFOUT_B>; +- status = "disabled"; +- }; +- +- toacodec: audio-controller@740 { +- compatible = "amlogic,g12a-toacodec"; +- reg = <0x0 0x740 0x0 0x4>; +- #sound-dai-cells = <1>; +- sound-name-prefix = "TOACODEC"; +- resets = <&clkc_audio AUD_RESET_TOACODEC>; +- status = "disabled"; +- }; +- +- tohdmitx: audio-controller@744 { +- compatible = "amlogic,g12a-tohdmitx"; +- reg = <0x0 0x744 0x0 0x4>; +- #sound-dai-cells = <1>; +- sound-name-prefix = "TOHDMITX"; +- resets = <&clkc_audio AUD_RESET_TOHDMITX>; +- status = "disabled"; +- }; +- }; +-}; +- +-ðmac { +- power-domains = <&pwrc PWRC_G12A_ETH_ID>; +-}; +- +-&vpu { +- power-domains = <&pwrc PWRC_G12A_VPU_ID>; +-}; +- +-&sd_emmc_a { +- amlogic,dram-access-quirk; +-}; +- +-&simplefb_cvbs { +- power-domains = <&pwrc PWRC_G12A_VPU_ID>; +-}; +- +-&simplefb_hdmi { +- power-domains = <&pwrc PWRC_G12A_VPU_ID>; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12a-sei510.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12a-sei510.dts +deleted file mode 100644 +index 4fb31c2ba31c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12a-sei510.dts ++++ /dev/null +@@ -1,558 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre SAS. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "meson-g12a.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "seirobotics,sei510", "amlogic,g12a"; +- model = "SEI Robotics SEI510"; +- +- adc_keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 0>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1800000>; +- +- button-onoff { +- label = "On/Off"; +- linux,code = ; +- press-threshold-microvolt = <1700000>; +- }; +- }; +- +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- mono_dac: audio-codec-0 { +- compatible = "maxim,max98357a"; +- #sound-dai-cells = <0>; +- sound-name-prefix = "U16"; +- sdmode-gpios = <&gpio GPIOX_8 GPIO_ACTIVE_HIGH>; +- }; +- +- dmics: audio-codec-1 { +- #sound-dai-cells = <0>; +- compatible = "dmic-codec"; +- num-channels = <2>; +- wakeup-delay-ms = <50>; +- status = "okay"; +- sound-name-prefix = "MIC"; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- cvbs-connector { +- compatible = "composite-video-connector"; +- +- port { +- cvbs_connector_in: endpoint { +- remote-endpoint = <&cvbs_vdac_out>; +- }; +- }; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x40000000>; +- }; +- +- ao_5v: regulator-ao_5v { +- compatible = "regulator-fixed"; +- regulator-name = "AO_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&dc_in>; +- regulator-always-on; +- }; +- +- dc_in: regulator-dc_in { +- compatible = "regulator-fixed"; +- regulator-name = "DC_IN"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- emmc_1v8: regulator-emmc_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "EMMC_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- }; +- +- vddao_3v3: regulator-vddao_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&dc_in>; +- regulator-always-on; +- }; +- +- vddao_3v3_t: regultor-vddao_3v3_t { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3_T"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vddao_3v3>; +- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; +- enable-active-high; +- }; +- +- vddcpu: regulator-vddcpu { +- /* +- * SY8120B1ABC DC/DC Regulator. +- */ +- compatible = "pwm-regulator"; +- +- regulator-name = "VDDCPU"; +- regulator-min-microvolt = <721000>; +- regulator-max-microvolt = <1022000>; +- +- pwm-supply = <&dc_in>; +- +- pwms = <&pwm_AO_cd 1 1250 0>; +- pwm-dutycycle-range = <100 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vddio_ao1v8: regulator-vddio_ao1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; +- clocks = <&wifi32k>; +- clock-names = "ext_clock"; +- }; +- +- wifi32k: wifi32k { +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ +- }; +- +- sound { +- compatible = "amlogic,axg-sound-card"; +- model = "SEI510"; +- audio-aux-devs = <&tdmout_a>, <&tdmout_b>, +- <&tdmin_a>, <&tdmin_b>; +- audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", +- "TDMOUT_A IN 1", "FRDDR_B OUT 0", +- "TDMOUT_A IN 2", "FRDDR_C OUT 0", +- "TDM_A Playback", "TDMOUT_A OUT", +- "TDMOUT_B IN 0", "FRDDR_A OUT 1", +- "TDMOUT_B IN 1", "FRDDR_B OUT 1", +- "TDMOUT_B IN 2", "FRDDR_C OUT 1", +- "TDM_B Playback", "TDMOUT_B OUT", +- "TODDR_A IN 4", "PDM Capture", +- "TODDR_B IN 4", "PDM Capture", +- "TODDR_C IN 4", "PDM Capture", +- "TDMIN_A IN 0", "TDM_A Capture", +- "TDMIN_A IN 3", "TDM_A Loopback", +- "TDMIN_B IN 0", "TDM_A Capture", +- "TDMIN_B IN 3", "TDM_A Loopback", +- "TDMIN_A IN 1", "TDM_B Capture", +- "TDMIN_A IN 4", "TDM_B Loopback", +- "TDMIN_B IN 1", "TDM_B Capture", +- "TDMIN_B IN 4", "TDM_B Loopback", +- "TODDR_A IN 0", "TDMIN_A OUT", +- "TODDR_B IN 0", "TDMIN_A OUT", +- "TODDR_C IN 0", "TDMIN_A OUT", +- "TODDR_A IN 1", "TDMIN_B OUT", +- "TODDR_B IN 1", "TDMIN_B OUT", +- "TODDR_C IN 1", "TDMIN_B OUT"; +- +- assigned-clocks = <&clkc CLKID_MPLL2>, +- <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&frddr_a>; +- }; +- +- dai-link-1 { +- sound-dai = <&frddr_b>; +- }; +- +- dai-link-2 { +- sound-dai = <&frddr_c>; +- }; +- +- dai-link-3 { +- sound-dai = <&toddr_a>; +- }; +- +- dai-link-4 { +- sound-dai = <&toddr_b>; +- }; +- +- dai-link-5 { +- sound-dai = <&toddr_c>; +- }; +- +- /* internal speaker interface */ +- dai-link-6 { +- sound-dai = <&tdmif_a>; +- dai-format = "i2s"; +- dai-tdm-slot-tx-mask-0 = <1 1>; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&mono_dac>; +- }; +- +- codec-1 { +- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; +- }; +- }; +- +- /* 8ch hdmi interface */ +- dai-link-7 { +- sound-dai = <&tdmif_b>; +- dai-format = "i2s"; +- dai-tdm-slot-tx-mask-0 = <1 1>; +- dai-tdm-slot-tx-mask-1 = <1 1>; +- dai-tdm-slot-tx-mask-2 = <1 1>; +- dai-tdm-slot-tx-mask-3 = <1 1>; +- mclk-fs = <256>; +- +- codec { +- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; +- }; +- }; +- +- /* internal digital mics */ +- dai-link-8 { +- sound-dai = <&pdm>; +- +- codec { +- sound-dai = <&dmics>; +- }; +- }; +- +- /* hdmi glue */ +- dai-link-9 { +- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; +- +- codec { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +-}; +- +-&arb { +- status = "okay"; +-}; +- +-&cec_AO { +- pinctrl-0 = <&cec_ao_a_h_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cecb_AO { +- pinctrl-0 = <&cec_ao_b_h_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&clkc_audio { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu1 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu2 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu3 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cvbs_vdac_port { +- cvbs_vdac_out: endpoint { +- remote-endpoint = <&cvbs_connector_in>; +- }; +-}; +- +-ðmac { +- status = "okay"; +- phy-handle = <&internal_ephy>; +- phy-mode = "rmii"; +-}; +- +-&frddr_a { +- status = "okay"; +-}; +- +-&frddr_b { +- status = "okay"; +-}; +- +-&frddr_c { +- status = "okay"; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; +- pinctrl-names = "default"; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +- pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&pwm_AO_cd { +- pinctrl-0 = <&pwm_ao_d_e_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>; +- clock-names = "clkin1"; +- status = "okay"; +-}; +- +-&pwm_ef { +- status = "okay"; +- pinctrl-0 = <&pwm_e_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>; +- clock-names = "clkin0"; +-}; +- +-&pdm { +- pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_din1_z_pins>, +- <&pdm_din2_z_pins>, <&pdm_din3_z_pins>, +- <&pdm_dclk_z_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vddio_ao1v8>; +-}; +- +-/* SDIO */ +-&sd_emmc_a { +- status = "okay"; +- pinctrl-0 = <&sdio_pins>; +- pinctrl-1 = <&sdio_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- bus-width = <4>; +- cap-sd-highspeed; +- sd-uhs-sdr50; +- max-frequency = <100000000>; +- +- non-removable; +- disable-wp; +- +- /* WiFi firmware requires power to be kept while in suspend */ +- keep-power-in-suspend; +- +- mmc-pwrseq = <&sdio_pwrseq>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_ao1v8>; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_c_pins>; +- pinctrl-1 = <&sdcard_clk_gate_c_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- disable-wp; +- +- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddao_3v3>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- max-frequency = <200000000>; +- non-removable; +- disable-wp; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&emmc_1v8>; +-}; +- +-&tdmif_a { +- pinctrl-0 = <&tdm_a_dout0_pins>, <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD0>, +- <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD0>; +- assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_A_SCLK>, +- <&clkc_audio AUD_CLKID_MST_A_LRCLK>; +- assigned-clock-rates = <0>, <0>; +-}; +- +-&tdmif_b { +- status = "okay"; +-}; +- +-&tdmin_a { +- status = "okay"; +-}; +- +-&tdmin_b { +- status = "okay"; +-}; +- +-&tdmout_a { +- status = "okay"; +-}; +- +-&tdmout_b { +- status = "okay"; +-}; +- +-&toddr_a { +- status = "okay"; +-}; +- +-&toddr_b { +- status = "okay"; +-}; +- +-&toddr_c { +- status = "okay"; +-}; +- +-&tohdmitx { +- status = "okay"; +-}; +- +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; +- max-speed = <2000000>; +- clocks = <&wifi32k>; +- clock-names = "lpo"; +- vbat-supply = <&vddao_3v3>; +- vddio-supply = <&vddio_ao1v8>; +- }; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- status = "okay"; +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12a-u200.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12a-u200.dts +deleted file mode 100644 +index 4b5d11e56364..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12a-u200.dts ++++ /dev/null +@@ -1,308 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Amlogic, Inc. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "meson-g12a.dtsi" +-#include +-#include +- +-/ { +- compatible = "amlogic,u200", "amlogic,g12a"; +- model = "Amlogic Meson G12A U200 Development Board"; +- +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- cvbs-connector { +- compatible = "composite-video-connector"; +- +- port { +- cvbs_connector_in: endpoint { +- remote-endpoint = <&cvbs_vdac_out>; +- }; +- }; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x40000000>; +- }; +- +- flash_1v8: regulator-flash_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "FLASH_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_3v3>; +- regulator-always-on; +- }; +- +- main_12v: regulator-main_12v { +- compatible = "regulator-fixed"; +- regulator-name = "12V"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- }; +- +- usb_pwr_en: regulator-usb_pwr_en { +- compatible = "regulator-fixed"; +- regulator-name = "USB_PWR_EN"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc_5v>; +- +- gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vcc_1v8: regulator-vcc_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_3v3>; +- regulator-always-on; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- /* FIXME: actually controlled by VDDCPU_B_EN */ +- }; +- +- vcc_5v: regulator-vcc_5v { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&main_12v>; +- +- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; +- enable-active-high; +- }; +- +- vddao_1v8: regulator-vddao_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- }; +- +- vddao_3v3: regulator-vddao_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&main_12v>; +- regulator-always-on; +- }; +- +- vddcpu: regulator-vddcpu { +- /* +- * MP8756GD Regulator. +- */ +- compatible = "pwm-regulator"; +- +- regulator-name = "VDDCPU"; +- regulator-min-microvolt = <721000>; +- regulator-max-microvolt = <1022000>; +- +- pwm-supply = <&main_12v>; +- +- pwms = <&pwm_AO_cd 1 1250 0>; +- pwm-dutycycle-range = <100 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&cec_AO { +- pinctrl-0 = <&cec_ao_a_h_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cecb_AO { +- pinctrl-0 = <&cec_ao_b_h_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cpu0 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu1 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu2 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu3 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cvbs_vdac_port { +- cvbs_vdac_out: endpoint { +- remote-endpoint = <&cvbs_connector_in>; +- }; +-}; +- +-ðmac { +- status = "okay"; +- phy-handle = <&internal_ephy>; +- phy-mode = "rmii"; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; +- pinctrl-names = "default"; +- hdmi-supply = <&vcc_5v>; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-/* i2c Touch */ +-&i2c0 { +- status = "okay"; +- pinctrl-0 = <&i2c0_sda_z0_pins>, <&i2c0_sck_z1_pins>; +- pinctrl-names = "default"; +-}; +- +-/* i2c CM */ +-&i2c2 { +- status = "okay"; +- pinctrl-0 = <&i2c2_sda_z_pins>, <&i2c2_sck_z_pins>; +- pinctrl-names = "default"; +-}; +- +-/* i2c Audio */ +-&i2c3 { +- status = "okay"; +- pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&pwm_AO_cd { +- pinctrl-0 = <&pwm_ao_d_e_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>; +- clock-names = "clkin1"; +- status = "okay"; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_c_pins>; +- pinctrl-1 = <&sdcard_clk_gate_c_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- disable-wp; +- +- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddao_3v3>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- max-frequency = <200000000>; +- non-removable; +- disable-wp; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&flash_1v8>; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- status = "okay"; +- vbus-supply = <&usb_pwr_en>; +-}; +- +-&usb2_phy0 { +- phy-supply = <&vcc_5v>; +-}; +- +-&usb2_phy1 { +- phy-supply = <&vcc_5v>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12a-x96-max.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12a-x96-max.dts +deleted file mode 100644 +index b4e86196e346..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12a-x96-max.dts ++++ /dev/null +@@ -1,481 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 BayLibre SAS. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "meson-g12a.dtsi" +-#include +-#include +-#include +- +-/ { +- compatible = "amediatech,x96-max", "amlogic,g12a"; +- model = "Shenzhen Amediatech Technology Co., Ltd X96 Max"; +- +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- spdif_dit: audio-codec-1 { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- status = "okay"; +- sound-name-prefix = "DIT"; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x40000000>; +- }; +- +- cvbs-connector { +- compatible = "composite-video-connector"; +- +- port { +- cvbs_connector_in: endpoint { +- remote-endpoint = <&cvbs_vdac_out>; +- }; +- }; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; +- clocks = <&wifi32k>; +- clock-names = "ext_clock"; +- }; +- +- flash_1v8: regulator-flash_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "FLASH_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_3v3>; +- regulator-always-on; +- }; +- +- dc_in: regulator-dc_in { +- compatible = "regulator-fixed"; +- regulator-name = "DC_IN"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- vcc_1v8: regulator-vcc_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_3v3>; +- regulator-always-on; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- /* FIXME: actually controlled by VDDCPU_B_EN */ +- }; +- +- vcc_5v: regulator-vcc_5v { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&dc_in>; +- +- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; +- enable-active-low; +- }; +- +- vddao_1v8: regulator-vddao_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- }; +- +- vddao_3v3: regulator-vddao_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&dc_in>; +- regulator-always-on; +- }; +- +- vddcpu: regulator-vddcpu { +- compatible = "pwm-regulator"; +- +- regulator-name = "VDDCPU"; +- regulator-min-microvolt = <721000>; +- regulator-max-microvolt = <1022000>; +- +- pwm-supply = <&dc_in>; +- +- pwms = <&pwm_AO_cd 1 1250 0>; +- pwm-dutycycle-range = <100 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sound { +- compatible = "amlogic,axg-sound-card"; +- model = "X96-MAX"; +- audio-aux-devs = <&tdmout_b>; +- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", +- "TDMOUT_B IN 1", "FRDDR_B OUT 1", +- "TDMOUT_B IN 2", "FRDDR_C OUT 1", +- "TDM_B Playback", "TDMOUT_B OUT", +- "SPDIFOUT IN 0", "FRDDR_A OUT 3", +- "SPDIFOUT IN 1", "FRDDR_B OUT 3", +- "SPDIFOUT IN 2", "FRDDR_C OUT 3"; +- +- assigned-clocks = <&clkc CLKID_MPLL2>, +- <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&frddr_a>; +- }; +- +- dai-link-1 { +- sound-dai = <&frddr_b>; +- }; +- +- dai-link-2 { +- sound-dai = <&frddr_c>; +- }; +- +- /* 8ch hdmi interface */ +- dai-link-3 { +- sound-dai = <&tdmif_b>; +- dai-format = "i2s"; +- dai-tdm-slot-tx-mask-0 = <1 1>; +- dai-tdm-slot-tx-mask-1 = <1 1>; +- dai-tdm-slot-tx-mask-2 = <1 1>; +- dai-tdm-slot-tx-mask-3 = <1 1>; +- mclk-fs = <256>; +- +- codec { +- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; +- }; +- }; +- +- /* spdif hdmi or toslink interface */ +- dai-link-4 { +- sound-dai = <&spdifout>; +- +- codec-0 { +- sound-dai = <&spdif_dit>; +- }; +- +- codec-1 { +- sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>; +- }; +- }; +- +- /* spdif hdmi interface */ +- dai-link-5 { +- sound-dai = <&spdifout_b>; +- +- codec { +- sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>; +- }; +- }; +- +- /* hdmi glue */ +- dai-link-6 { +- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; +- +- codec { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +- +- wifi32k: wifi32k { +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ +- }; +-}; +- +-&arb { +- status = "okay"; +-}; +- +-&cec_AO { +- pinctrl-0 = <&cec_ao_a_h_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cecb_AO { +- pinctrl-0 = <&cec_ao_b_h_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&clkc_audio { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu1 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu2 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu3 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cvbs_vdac_port { +- cvbs_vdac_out: endpoint { +- remote-endpoint = <&cvbs_connector_in>; +- }; +-}; +- +-&frddr_a { +- status = "okay"; +-}; +- +-&frddr_b { +- status = "okay"; +-}; +- +-&frddr_c { +- status = "okay"; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; +- pinctrl-names = "default"; +- hdmi-supply = <&vcc_5v>; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +- linux,rc-map-name = "rc-x96max"; +-}; +- +-&pwm_AO_cd { +- pinctrl-0 = <&pwm_ao_d_e_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>; +- clock-names = "clkin1"; +- status = "okay"; +-}; +- +-&ext_mdio { +- external_phy: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- max-speed = <1000>; +- eee-broken-1000t; +- +- reset-assert-us = <10000>; +- reset-deassert-us = <80000>; +- reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; +- +- interrupt-parent = <&gpio_intc>; +- /* MAC_INTR on GPIOZ_14 */ +- interrupts = <26 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-ðmac { +- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy-mode = "rgmii"; +- phy-handle = <&external_phy>; +- amlogic,tx-delay-ns = <2>; +-}; +- +-&pwm_ef { +- status = "okay"; +- pinctrl-0 = <&pwm_e_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>; +- clock-names = "clkin0"; +-}; +- +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; +- max-speed = <2000000>; +- clocks = <&wifi32k>; +- clock-names = "lpo"; +- }; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-/* SDIO */ +-&sd_emmc_a { +- status = "okay"; +- pinctrl-0 = <&sdio_pins>; +- pinctrl-1 = <&sdio_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- bus-width = <4>; +- cap-sd-highspeed; +- sd-uhs-sdr50; +- max-frequency = <100000000>; +- +- non-removable; +- disable-wp; +- +- /* WiFi firmware requires power to be kept while in suspend */ +- keep-power-in-suspend; +- +- mmc-pwrseq = <&sdio_pwrseq>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddao_1v8>; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_c_pins>; +- pinctrl-1 = <&sdcard_clk_gate_c_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <100000000>; +- disable-wp; +- +- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddao_3v3>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- max-frequency = <100000000>; +- non-removable; +- disable-wp; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&flash_1v8>; +-}; +- +-&spdifout { +- pinctrl-0 = <&spdif_out_h_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&spdifout_b { +- status = "okay"; +-}; +- +-&tdmif_b { +- status = "okay"; +-}; +- +-&tdmout_b { +- status = "okay"; +-}; +- +-&tohdmitx { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12a.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12a.dtsi +deleted file mode 100644 +index fb0ab27d1f64..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12a.dtsi ++++ /dev/null +@@ -1,135 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Amlogic, Inc. All rights reserved. +- */ +- +-#include "meson-g12.dtsi" +- +-/ { +- compatible = "amlogic,g12a"; +- +- cpus { +- #address-cells = <0x2>; +- #size-cells = <0x0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- #cooling-cells = <2>; +- }; +- +- l2: l2-cache0 { +- compatible = "cache"; +- }; +- }; +- +- cpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-250000000 { +- opp-hz = /bits/ 64 <250000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-667000000 { +- opp-hz = /bits/ 64 <666666666>; +- opp-microvolt = <731000>; +- }; +- +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-1398000000 { +- opp-hz = /bits/ 64 <1398000000>; +- opp-microvolt = <761000>; +- }; +- +- opp-1512000000 { +- opp-hz = /bits/ 64 <1512000000>; +- opp-microvolt = <791000>; +- }; +- +- opp-1608000000 { +- opp-hz = /bits/ 64 <1608000000>; +- opp-microvolt = <831000>; +- }; +- +- opp-1704000000 { +- opp-hz = /bits/ 64 <1704000000>; +- opp-microvolt = <861000>; +- }; +- +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <981000>; +- }; +- }; +-}; +- +-&cpu_thermal { +- cooling-maps { +- map0 { +- trip = <&cpu_passive>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- +- map1 { +- trip = <&cpu_hot>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-a311d-khadas-vim3.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-a311d-khadas-vim3.dts +deleted file mode 100644 +index 124a80901084..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-a311d-khadas-vim3.dts ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- * Copyright (c) 2019 Christian Hewitt +- */ +- +-/dts-v1/; +- +-#include "meson-g12b-a311d.dtsi" +-#include "meson-khadas-vim3.dtsi" +-#include "meson-g12b-khadas-vim3.dtsi" +- +-/ { +- compatible = "khadas,vim3", "amlogic,a311d", "amlogic,g12b"; +-}; +- +-/* +- * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential +- * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between +- * an USB3.0 Type A connector and a M.2 Key M slot. +- * The PHY driving these differential lines is shared between +- * the USB3.0 controller and the PCIe Controller, thus only +- * a single controller can use it. +- * If the MCU is configured to mux the PCIe/USB3.0 differential lines +- * to the M.2 Key M slot, uncomment the following block to disable +- * USB3.0 from the USB Complex and enable the PCIe controller. +- * The End User is not expected to uncomment the following except for +- * testing purposes, but instead rely on the firmware/bootloader to +- * update these nodes accordingly if PCIe mode is selected by the MCU. +- */ +-/* +-&pcie { +- status = "okay"; +-}; +- +-&usb { +- phys = <&usb2_phy0>, <&usb2_phy1>; +- phy-names = "usb2-phy0", "usb2-phy1"; +-}; +- */ +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-a311d.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-a311d.dtsi +deleted file mode 100644 +index d61f43052a34..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-a311d.dtsi ++++ /dev/null +@@ -1,149 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- */ +- +-#include "meson-g12b.dtsi" +- +-/ { +- cpu_opp_table_0: opp-table-0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-250000000 { +- opp-hz = /bits/ 64 <250000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-667000000 { +- opp-hz = /bits/ 64 <667000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <761000>; +- }; +- +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <781000>; +- }; +- +- opp-1398000000 { +- opp-hz = /bits/ 64 <1398000000>; +- opp-microvolt = <811000>; +- }; +- +- opp-1512000000 { +- opp-hz = /bits/ 64 <1512000000>; +- opp-microvolt = <861000>; +- }; +- +- opp-1608000000 { +- opp-hz = /bits/ 64 <1608000000>; +- opp-microvolt = <901000>; +- }; +- +- opp-1704000000 { +- opp-hz = /bits/ 64 <1704000000>; +- opp-microvolt = <951000>; +- }; +- +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <1001000>; +- }; +- }; +- +- cpub_opp_table_1: opp-table-1 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-250000000 { +- opp-hz = /bits/ 64 <250000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-667000000 { +- opp-hz = /bits/ 64 <667000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <751000>; +- }; +- +- opp-1398000000 { +- opp-hz = /bits/ 64 <1398000000>; +- opp-microvolt = <771000>; +- }; +- +- opp-1512000000 { +- opp-hz = /bits/ 64 <1512000000>; +- opp-microvolt = <771000>; +- }; +- +- opp-1608000000 { +- opp-hz = /bits/ 64 <1608000000>; +- opp-microvolt = <781000>; +- }; +- +- opp-1704000000 { +- opp-hz = /bits/ 64 <1704000000>; +- opp-microvolt = <791000>; +- }; +- +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <831000>; +- }; +- +- opp-1908000000 { +- opp-hz = /bits/ 64 <1908000000>; +- opp-microvolt = <861000>; +- }; +- +- opp-2016000000 { +- opp-hz = /bits/ 64 <2016000000>; +- opp-microvolt = <911000>; +- }; +- +- opp-2108000000 { +- opp-hz = /bits/ 64 <2108000000>; +- opp-microvolt = <951000>; +- }; +- +- opp-2208000000 { +- opp-hz = /bits/ 64 <2208000000>; +- opp-microvolt = <1011000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-gsking-x.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-gsking-x.dts +deleted file mode 100644 +index 6c7bfacbad78..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-gsking-x.dts ++++ /dev/null +@@ -1,133 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- * Copyright (c) 2019 Christian Hewitt +- */ +- +-/dts-v1/; +- +-#include "meson-g12b-w400.dtsi" +-#include +-#include +- +-/ { +- compatible = "azw,gsking-x", "amlogic,s922x", "amlogic,g12b"; +- model = "Beelink GS-King X"; +- +- aliases { +- rtc0 = &rtc; +- rtc1 = &vrtc; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- #address-cells = <1>; +- #size-cells = <0>; +- poll-interval = <100>; +- +- power-button { +- label = "power"; +- linux,code = ; +- gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- sound { +- compatible = "amlogic,axg-sound-card"; +- model = "GSKING-X"; +- audio-aux-devs = <&tdmout_a>; +- audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 1", +- "TDMOUT_A IN 1", "FRDDR_B OUT 1", +- "TDMOUT_A IN 2", "FRDDR_C OUT 1", +- "TDM_A Playback", "TDMOUT_A OUT"; +- +- assigned-clocks = <&clkc CLKID_MPLL2>, +- <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&frddr_a>; +- }; +- +- dai-link-1 { +- sound-dai = <&frddr_b>; +- }; +- +- dai-link-2 { +- sound-dai = <&frddr_c>; +- }; +- +- /* 8ch hdmi interface */ +- dai-link-3 { +- sound-dai = <&tdmif_a>; +- dai-format = "i2s"; +- dai-tdm-slot-tx-mask-0 = <1 1>; +- dai-tdm-slot-tx-mask-1 = <1 1>; +- dai-tdm-slot-tx-mask-2 = <1 1>; +- dai-tdm-slot-tx-mask-3 = <1 1>; +- mclk-fs = <256>; +- +- codec { +- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; +- }; +- }; +- +- dai-link-4 { +- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; +- +- codec { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +-}; +- +-&arb { +- status = "okay"; +-}; +- +-&clkc_audio { +- status = "okay"; +-}; +- +-&frddr_a { +- status = "okay"; +-}; +- +-&frddr_b { +- status = "okay"; +-}; +- +-&frddr_c { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +- pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; +- pinctrl-names = "default"; +- +- rtc: rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- wakeup-source; +- }; +-}; +- +-&tdmif_a { +- status = "okay"; +-}; +- +-&tdmout_a { +- status = "okay"; +-}; +- +-&tohdmitx { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-gtking-pro.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-gtking-pro.dts +deleted file mode 100644 +index 707daf92787b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-gtking-pro.dts ++++ /dev/null +@@ -1,142 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- * Copyright (c) 2019 Christian Hewitt +- */ +- +-/dts-v1/; +- +-#include "meson-g12b-w400.dtsi" +-#include +- +-/ { +- compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b"; +- model = "Beelink GT-King Pro"; +- +- aliases { +- rtc0 = &rtc; +- rtc1 = &vrtc; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- #address-cells = <1>; +- #size-cells = <0>; +- poll-interval = <100>; +- +- power-button { +- label = "power"; +- linux,code = ; +- gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-white { +- label = "power:white"; +- gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- sound { +- compatible = "amlogic,axg-sound-card"; +- model = "GTKING-PRO"; +- audio-aux-devs = <&tdmout_b>; +- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", +- "TDMOUT_B IN 1", "FRDDR_B OUT 1", +- "TDMOUT_B IN 2", "FRDDR_C OUT 1", +- "TDM_B Playback", "TDMOUT_B OUT"; +- +- assigned-clocks = <&clkc CLKID_MPLL2>, +- <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&frddr_a>; +- }; +- +- dai-link-1 { +- sound-dai = <&frddr_b>; +- }; +- +- dai-link-2 { +- sound-dai = <&frddr_c>; +- }; +- +- /* 8ch hdmi interface */ +- dai-link-3 { +- sound-dai = <&tdmif_b>; +- dai-format = "i2s"; +- dai-tdm-slot-tx-mask-0 = <1 1>; +- dai-tdm-slot-tx-mask-1 = <1 1>; +- dai-tdm-slot-tx-mask-2 = <1 1>; +- dai-tdm-slot-tx-mask-3 = <1 1>; +- mclk-fs = <256>; +- +- codec { +- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; +- }; +- }; +- +- dai-link-4 { +- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; +- +- codec { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +-}; +- +-&arb { +- status = "okay"; +-}; +- +-&clkc_audio { +- status = "okay"; +-}; +- +-&frddr_a { +- status = "okay"; +-}; +- +-&frddr_b { +- status = "okay"; +-}; +- +-&frddr_c { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +- pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; +- pinctrl-names = "default"; +- +- rtc: rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- wakeup-source; +- }; +-}; +- +-&tdmif_b { +- status = "okay"; +-}; +- +-&tdmout_b { +- status = "okay"; +-}; +- +-&tohdmitx { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-gtking.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-gtking.dts +deleted file mode 100644 +index 5d96c1449050..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-gtking.dts ++++ /dev/null +@@ -1,163 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- * Copyright (c) 2019 Christian Hewitt +- */ +- +-/dts-v1/; +- +-#include "meson-g12b-w400.dtsi" +-#include +- +-/ { +- compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b"; +- model = "Beelink GT-King"; +- +- aliases { +- rtc0 = &rtc; +- rtc1 = &vrtc; +- }; +- +- spdif_dit: audio-codec-1 { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- status = "okay"; +- sound-name-prefix = "DIT"; +- }; +- +- sound { +- compatible = "amlogic,axg-sound-card"; +- model = "GTKING"; +- audio-aux-devs = <&tdmout_b>; +- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", +- "TDMOUT_B IN 1", "FRDDR_B OUT 1", +- "TDMOUT_B IN 2", "FRDDR_C OUT 1", +- "TDM_B Playback", "TDMOUT_B OUT", +- "SPDIFOUT IN 0", "FRDDR_A OUT 3", +- "SPDIFOUT IN 1", "FRDDR_B OUT 3", +- "SPDIFOUT IN 2", "FRDDR_C OUT 3"; +- +- assigned-clocks = <&clkc CLKID_MPLL2>, +- <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&frddr_a>; +- }; +- +- dai-link-1 { +- sound-dai = <&frddr_b>; +- }; +- +- dai-link-2 { +- sound-dai = <&frddr_c>; +- }; +- +- /* 8ch hdmi interface */ +- dai-link-3 { +- sound-dai = <&tdmif_b>; +- dai-format = "i2s"; +- dai-tdm-slot-tx-mask-0 = <1 1>; +- dai-tdm-slot-tx-mask-1 = <1 1>; +- dai-tdm-slot-tx-mask-2 = <1 1>; +- dai-tdm-slot-tx-mask-3 = <1 1>; +- mclk-fs = <256>; +- +- codec { +- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; +- }; +- }; +- +- /* spdif hdmi or toslink interface */ +- dai-link-4 { +- sound-dai = <&spdifout>; +- +- codec-0 { +- sound-dai = <&spdif_dit>; +- }; +- +- codec-1 { +- sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>; +- }; +- }; +- +- /* spdif hdmi interface */ +- dai-link-5 { +- sound-dai = <&spdifout_b>; +- +- codec { +- sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>; +- }; +- }; +- +- /* hdmi glue */ +- dai-link-6 { +- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; +- +- codec { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +-}; +- +-&arb { +- status = "okay"; +-}; +- +-&clkc_audio { +- status = "okay"; +-}; +- +-&frddr_a { +- status = "okay"; +-}; +- +-&frddr_b { +- status = "okay"; +-}; +- +-&frddr_c { +- status = "okay"; +-}; +- +- +-&i2c3 { +- status = "okay"; +- pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; +- pinctrl-names = "default"; +- +- rtc: rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- wakeup-source; +- }; +-}; +- +-&spdifout { +- pinctrl-0 = <&spdif_out_h_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&spdifout_b { +- status = "okay"; +-}; +- +-&tdmif_b { +- status = "okay"; +-}; +- +-&tdmout_b { +- status = "okay"; +-}; +- +-&tohdmitx { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-khadas-vim3.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-khadas-vim3.dtsi +deleted file mode 100644 +index 16dd409051b4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-khadas-vim3.dtsi ++++ /dev/null +@@ -1,107 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- * Copyright (c) 2019 Christian Hewitt +- */ +- +-/ { +- model = "Khadas VIM3"; +- +- vddcpu_a: regulator-vddcpu-a { +- /* +- * MP8756GD Regulator. +- */ +- compatible = "pwm-regulator"; +- +- regulator-name = "VDDCPU_A"; +- regulator-min-microvolt = <690000>; +- regulator-max-microvolt = <1050000>; +- +- pwm-supply = <&dc_in>; +- +- pwms = <&pwm_ab 0 1250 0>; +- pwm-dutycycle-range = <100 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vddcpu_b: regulator-vddcpu-b { +- /* +- * Silergy SY8030DEC Regulator. +- */ +- compatible = "pwm-regulator"; +- +- regulator-name = "VDDCPU_B"; +- regulator-min-microvolt = <690000>; +- regulator-max-microvolt = <1050000>; +- +- pwm-supply = <&vsys_3v3>; +- +- pwms = <&pwm_AO_cd 1 1250 0>; +- pwm-dutycycle-range = <100 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vddcpu_b>; +- operating-points-v2 = <&cpu_opp_table_0>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu1 { +- cpu-supply = <&vddcpu_b>; +- operating-points-v2 = <&cpu_opp_table_0>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu100 { +- cpu-supply = <&vddcpu_a>; +- operating-points-v2 = <&cpub_opp_table_1>; +- clocks = <&clkc CLKID_CPUB_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu101 { +- cpu-supply = <&vddcpu_a>; +- operating-points-v2 = <&cpub_opp_table_1>; +- clocks = <&clkc CLKID_CPUB_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu102 { +- cpu-supply = <&vddcpu_a>; +- operating-points-v2 = <&cpub_opp_table_1>; +- clocks = <&clkc CLKID_CPUB_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu103 { +- cpu-supply = <&vddcpu_a>; +- operating-points-v2 = <&cpub_opp_table_1>; +- clocks = <&clkc CLKID_CPUB_CLK>; +- clock-latency = <50000>; +-}; +- +-&pwm_ab { +- pinctrl-0 = <&pwm_a_e_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>; +- clock-names = "clkin0"; +- status = "okay"; +-}; +- +-&pwm_AO_cd { +- pinctrl-0 = <&pwm_ao_d_e_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>; +- clock-names = "clkin1"; +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-odroid-n2-plus.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-odroid-n2-plus.dts +deleted file mode 100644 +index ce1198ad34e4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-odroid-n2-plus.dts ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- */ +- +-/dts-v1/; +- +-/* The Amlogic S922X Rev. C supports the same OPPs as the A311D variant */ +-#include "meson-g12b-a311d.dtsi" +-#include "meson-g12b-odroid-n2.dtsi" +- +-/ { +- compatible = "hardkernel,odroid-n2-plus", "amlogic,s922x", "amlogic,g12b"; +- model = "Hardkernel ODROID-N2Plus"; +-}; +- +-&vddcpu_a { +- regulator-min-microvolt = <680000>; +- regulator-max-microvolt = <1040000>; +- +- pwms = <&pwm_ab 0 1500 0>; +-}; +- +-&vddcpu_b { +- regulator-min-microvolt = <680000>; +- regulator-max-microvolt = <1040000>; +- +- pwms = <&pwm_AO_cd 1 1500 0>; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-odroid-n2.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-odroid-n2.dts +deleted file mode 100644 +index a198a91259ec..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-odroid-n2.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- */ +- +-/dts-v1/; +- +-#include "meson-g12b-s922x.dtsi" +-#include "meson-g12b-odroid-n2.dtsi" +- +-/ { +- compatible = "hardkernel,odroid-n2", "amlogic,s922x", "amlogic,g12b"; +- model = "Hardkernel ODROID-N2"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-odroid-n2.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-odroid-n2.dtsi +deleted file mode 100644 +index d33e54b5e196..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-odroid-n2.dtsi ++++ /dev/null +@@ -1,689 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- rtc0 = &rtc; +- rtc1 = &vrtc; +- }; +- +- dio2133: audio-amplifier-0 { +- compatible = "simple-audio-amplifier"; +- enable-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; +- VCC-supply = <&vcc_5v>; +- sound-name-prefix = "U19"; +- status = "okay"; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x40000000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-blue { +- label = "n2:blue"; +- gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- tflash_vdd: regulator-tflash_vdd { +- compatible = "regulator-fixed"; +- +- regulator-name = "TFLASH_VDD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- tf_io: gpio-regulator-tf_io { +- compatible = "regulator-gpio"; +- +- regulator-name = "TF_IO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; +- gpios-states = <0>; +- +- states = <3300000 0>, +- <1800000 1>; +- }; +- +- flash_1v8: regulator-flash_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "FLASH_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_3v3>; +- regulator-always-on; +- }; +- +- main_12v: regulator-main_12v { +- compatible = "regulator-fixed"; +- regulator-name = "12V"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- }; +- +- vcc_5v: regulator-vcc_5v { +- compatible = "regulator-fixed"; +- regulator-name = "5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- vin-supply = <&main_12v>; +- }; +- +- vcc_1v8: regulator-vcc_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_3v3>; +- regulator-always-on; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- /* FIXME: actually controlled by VDDCPU_B_EN */ +- }; +- +- vddcpu_a: regulator-vddcpu-a { +- /* +- * MP8756GD Regulator. +- */ +- compatible = "pwm-regulator"; +- +- regulator-name = "VDDCPU_A"; +- regulator-min-microvolt = <721000>; +- regulator-max-microvolt = <1022000>; +- +- pwm-supply = <&main_12v>; +- +- pwms = <&pwm_ab 0 1250 0>; +- pwm-dutycycle-range = <100 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vddcpu_b: regulator-vddcpu-b { +- /* +- * Silergy SY8120B1ABC Regulator. +- */ +- compatible = "pwm-regulator"; +- +- regulator-name = "VDDCPU_B"; +- regulator-min-microvolt = <721000>; +- regulator-max-microvolt = <1022000>; +- +- pwm-supply = <&main_12v>; +- +- pwms = <&pwm_AO_cd 1 1250 0>; +- pwm-dutycycle-range = <100 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +- +- hub_5v: regulator-hub_5v { +- compatible = "regulator-fixed"; +- regulator-name = "HUB_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc_5v>; +- +- /* Connected to the Hub CHIPENABLE, LOW sets low power state */ +- gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- usb_pwr_en: regulator-usb_pwr_en { +- compatible = "regulator-fixed"; +- regulator-name = "USB_PWR_EN"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc_5v>; +- +- /* Connected to the microUSB port power enable */ +- gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vddao_1v8: regulator-vddao_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- }; +- +- vddao_3v3: regulator-vddao_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&main_12v>; +- regulator-always-on; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- sound { +- compatible = "amlogic,axg-sound-card"; +- model = "ODROID-N2"; +- audio-widgets = "Line", "Lineout"; +- audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>, +- <&tdmin_b>, <&tdmin_c>, <&tdmin_lb>, +- <&dio2133>; +- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", +- "TDMOUT_B IN 1", "FRDDR_B OUT 1", +- "TDMOUT_B IN 2", "FRDDR_C OUT 1", +- "TDM_B Playback", "TDMOUT_B OUT", +- "TDMOUT_C IN 0", "FRDDR_A OUT 2", +- "TDMOUT_C IN 1", "FRDDR_B OUT 2", +- "TDMOUT_C IN 2", "FRDDR_C OUT 2", +- "TDM_C Playback", "TDMOUT_C OUT", +- "TDMIN_A IN 4", "TDM_B Loopback", +- "TDMIN_B IN 4", "TDM_B Loopback", +- "TDMIN_C IN 4", "TDM_B Loopback", +- "TDMIN_LB IN 1", "TDM_B Loopback", +- "TDMIN_A IN 5", "TDM_C Loopback", +- "TDMIN_B IN 5", "TDM_C Loopback", +- "TDMIN_C IN 5", "TDM_C Loopback", +- "TDMIN_LB IN 2", "TDM_C Loopback", +- "TODDR_A IN 0", "TDMIN_A OUT", +- "TODDR_B IN 0", "TDMIN_A OUT", +- "TODDR_C IN 0", "TDMIN_A OUT", +- "TODDR_A IN 1", "TDMIN_B OUT", +- "TODDR_B IN 1", "TDMIN_B OUT", +- "TODDR_C IN 1", "TDMIN_B OUT", +- "TODDR_A IN 2", "TDMIN_C OUT", +- "TODDR_B IN 2", "TDMIN_C OUT", +- "TODDR_C IN 2", "TDMIN_C OUT", +- "TODDR_A IN 6", "TDMIN_LB OUT", +- "TODDR_B IN 6", "TDMIN_LB OUT", +- "TODDR_C IN 6", "TDMIN_LB OUT", +- "U19 INL", "ACODEC LOLP", +- "U19 INR", "ACODEC LORP", +- "Lineout", "U19 OUTL", +- "Lineout", "U19 OUTR"; +- +- assigned-clocks = <&clkc CLKID_MPLL2>, +- <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&frddr_a>; +- }; +- +- dai-link-1 { +- sound-dai = <&frddr_b>; +- }; +- +- dai-link-2 { +- sound-dai = <&frddr_c>; +- }; +- +- dai-link-3 { +- sound-dai = <&toddr_a>; +- }; +- +- dai-link-4 { +- sound-dai = <&toddr_b>; +- }; +- +- dai-link-5 { +- sound-dai = <&toddr_c>; +- }; +- +- /* 8ch hdmi interface */ +- dai-link-6 { +- sound-dai = <&tdmif_b>; +- dai-format = "i2s"; +- dai-tdm-slot-tx-mask-0 = <1 1>; +- dai-tdm-slot-tx-mask-1 = <1 1>; +- dai-tdm-slot-tx-mask-2 = <1 1>; +- dai-tdm-slot-tx-mask-3 = <1 1>; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; +- }; +- +- codec-1 { +- sound-dai = <&toacodec TOACODEC_IN_B>; +- }; +- }; +- +- /* i2s jack output interface */ +- dai-link-7 { +- sound-dai = <&tdmif_c>; +- dai-format = "i2s"; +- dai-tdm-slot-tx-mask-0 = <1 1>; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>; +- }; +- +- codec-1 { +- sound-dai = <&toacodec TOACODEC_IN_C>; +- }; +- }; +- +- /* hdmi glue */ +- dai-link-8 { +- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; +- +- codec { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- +- /* acodec glue */ +- dai-link-9 { +- sound-dai = <&toacodec TOACODEC_OUT>; +- +- codec { +- sound-dai = <&acodec>; +- }; +- }; +- }; +-}; +- +-&acodec { +- AVDD-supply = <&vddao_1v8>; +- status = "okay"; +-}; +- +-&arb { +- status = "okay"; +-}; +- +-&cec_AO { +- pinctrl-0 = <&cec_ao_a_h_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cecb_AO { +- pinctrl-0 = <&cec_ao_b_h_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&clkc_audio { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <&vddcpu_b>; +- operating-points-v2 = <&cpu_opp_table_0>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu1 { +- cpu-supply = <&vddcpu_b>; +- operating-points-v2 = <&cpu_opp_table_0>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu100 { +- cpu-supply = <&vddcpu_a>; +- operating-points-v2 = <&cpub_opp_table_1>; +- clocks = <&clkc CLKID_CPUB_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu101 { +- cpu-supply = <&vddcpu_a>; +- operating-points-v2 = <&cpub_opp_table_1>; +- clocks = <&clkc CLKID_CPUB_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu102 { +- cpu-supply = <&vddcpu_a>; +- operating-points-v2 = <&cpub_opp_table_1>; +- clocks = <&clkc CLKID_CPUB_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu103 { +- cpu-supply = <&vddcpu_a>; +- operating-points-v2 = <&cpub_opp_table_1>; +- clocks = <&clkc CLKID_CPUB_CLK>; +- clock-latency = <50000>; +-}; +- +-&ext_mdio { +- external_phy: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- max-speed = <1000>; +- +- reset-assert-us = <10000>; +- reset-deassert-us = <80000>; +- reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; +- +- interrupt-parent = <&gpio_intc>; +- /* MAC_INTR on GPIOZ_14 */ +- interrupts = <26 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-ðmac { +- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy-mode = "rgmii"; +- phy-handle = <&external_phy>; +- amlogic,tx-delay-ns = <2>; +-}; +- +-&frddr_a { +- status = "okay"; +-}; +- +-&frddr_b { +- status = "okay"; +-}; +- +-&frddr_c { +- status = "okay"; +-}; +- +-&gpio { +- gpio-line-names = +- /* GPIOZ */ +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- /* GPIOH */ +- "", "", "", "", "", "", "", "", +- "", +- /* BOOT */ +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- /* GPIOC */ +- "", "", "", "", "", "", "", "", +- /* GPIOA */ +- "PIN_44", /* GPIOA_0 */ +- "PIN_46", /* GPIOA_1 */ +- "PIN_45", /* GPIOA_2 */ +- "PIN_47", /* GPIOA_3 */ +- "PIN_26", /* GPIOA_4 */ +- "", "", "", "", "", "", +- "PIN_42", /* GPIOA_11 */ +- "PIN_32", /* GPIOA_12 */ +- "PIN_7", /* GPIOA_13 */ +- "PIN_27", /* GPIOA_14 */ +- "PIN_28", /* GPIOA_15 */ +- /* GPIOX */ +- "PIN_16", /* GPIOX_0 */ +- "PIN_18", /* GPIOX_1 */ +- "PIN_22", /* GPIOX_2 */ +- "PIN_11", /* GPIOX_3 */ +- "PIN_13", /* GPIOX_4 */ +- "PIN_33", /* GPIOX_5 */ +- "PIN_35", /* GPIOX_6 */ +- "PIN_15", /* GPIOX_7 */ +- "PIN_19", /* GPIOX_8 */ +- "PIN_21", /* GPIOX_9 */ +- "PIN_24", /* GPIOX_10 */ +- "PIN_23", /* GPIOX_11 */ +- "PIN_8", /* GPIOX_12 */ +- "PIN_10", /* GPIOX_13 */ +- "PIN_29", /* GPIOX_14 */ +- "PIN_31", /* GPIOX_15 */ +- "PIN_12", /* GPIOX_16 */ +- "PIN_3", /* GPIOX_17 */ +- "PIN_5", /* GPIOX_18 */ +- "PIN_36"; /* GPIOX_19 */ +- /* +- * WARNING: The USB Hub on the Odroid-N2 needs a reset signal +- * to be turned high in order to be detected by the USB Controller +- * This signal should be handled by a USB specific power sequence +- * in order to reset the Hub when USB bus is powered down. +- */ +- hog-0 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "usb-hub-reset"; +- }; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; +- pinctrl-names = "default"; +- hdmi-supply = <&vcc_5v>; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +- linux,rc-map-name = "rc-odroid"; +-}; +- +-&i2c3 { +- status = "okay"; +- pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; +- pinctrl-names = "default"; +- +- rtc: rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- wakeup-source; +- }; +-}; +- +-&pwm_ab { +- pinctrl-0 = <&pwm_a_e_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>; +- clock-names = "clkin0"; +- status = "okay"; +-}; +- +-&pwm_AO_cd { +- pinctrl-0 = <&pwm_ao_d_e_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>; +- clock-names = "clkin1"; +- status = "okay"; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vddao_1v8>; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_c_pins>; +- pinctrl-1 = <&sdcard_clk_gate_c_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- disable-wp; +- +- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; +- vmmc-supply = <&tflash_vdd>; +- vqmmc-supply = <&tf_io>; +- +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- max-frequency = <200000000>; +- disable-wp; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&flash_1v8>; +-}; +- +-/* +- * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins +- * and eMMC Data 4 to 7 pins. +- * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0, +- * and change bus-width to 4 then spifc can be enabled. +- * The SW1 slide should also be set to the correct position. +- */ +-&spifc { +- status = "disabled"; +- pinctrl-0 = <&nor_pins>; +- pinctrl-names = "default"; +- +- mx25u64: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mxicy,mx25u6435f", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <104000000>; +- }; +-}; +- +-&tdmif_b { +- status = "okay"; +-}; +- +-&tdmif_c { +- status = "okay"; +-}; +- +-&tdmin_a { +- status = "okay"; +-}; +- +-&tdmin_b { +- status = "okay"; +-}; +- +-&tdmin_c { +- status = "okay"; +-}; +- +-&tdmin_lb { +- status = "okay"; +-}; +- +-&tdmout_b { +- status = "okay"; +-}; +- +-&tdmout_c { +- status = "okay"; +-}; +- +-&toacodec { +- status = "okay"; +-}; +- +-&tohdmitx { +- status = "okay"; +-}; +- +-&toddr_a { +- status = "okay"; +-}; +- +-&toddr_b { +- status = "okay"; +-}; +- +-&toddr_c { +- status = "okay"; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- status = "okay"; +- vbus-supply = <&usb_pwr_en>; +-}; +- +-&usb2_phy0 { +- phy-supply = <&vcc_5v>; +-}; +- +-&usb2_phy1 { +- /* Enable the hub which is connected to this port */ +- phy-supply = <&hub_5v>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-s922x-khadas-vim3.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-s922x-khadas-vim3.dts +deleted file mode 100644 +index bba98f982ad6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-s922x-khadas-vim3.dts ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- * Copyright (c) 2019 Christian Hewitt +- */ +- +-/dts-v1/; +- +-#include "meson-g12b-s922x.dtsi" +-#include "meson-khadas-vim3.dtsi" +-#include "meson-g12b-khadas-vim3.dtsi" +- +-/ { +- compatible = "khadas,vim3", "amlogic,s922x", "amlogic,g12b"; +-}; +- +-/* +- * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential +- * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between +- * an USB3.0 Type A connector and a M.2 Key M slot. +- * The PHY driving these differential lines is shared between +- * the USB3.0 controller and the PCIe Controller, thus only +- * a single controller can use it. +- * If the MCU is configured to mux the PCIe/USB3.0 differential lines +- * to the M.2 Key M slot, uncomment the following block to disable +- * USB3.0 from the USB Complex and enable the PCIe controller. +- * The End User is not expected to uncomment the following except for +- * testing purposes, but instead rely on the firmware/bootloader to +- * update these nodes accordingly if PCIe mode is selected by the MCU. +- */ +-/* +-&pcie { +- status = "okay"; +-}; +- +-&usb { +- phys = <&usb2_phy0>, <&usb2_phy1>; +- phy-names = "usb2-phy0", "usb2-phy1"; +-}; +- */ +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-s922x.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-s922x.dtsi +deleted file mode 100644 +index 1e5d0ee5d541..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-s922x.dtsi ++++ /dev/null +@@ -1,139 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- */ +- +-#include "meson-g12b.dtsi" +- +-/ { +- cpu_opp_table_0: opp-table-0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-250000000 { +- opp-hz = /bits/ 64 <250000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-667000000 { +- opp-hz = /bits/ 64 <667000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <731000>; +- }; +- +- opp-1398000000 { +- opp-hz = /bits/ 64 <1398000000>; +- opp-microvolt = <761000>; +- }; +- +- opp-1512000000 { +- opp-hz = /bits/ 64 <1512000000>; +- opp-microvolt = <791000>; +- }; +- +- opp-1608000000 { +- opp-hz = /bits/ 64 <1608000000>; +- opp-microvolt = <831000>; +- }; +- +- opp-1704000000 { +- opp-hz = /bits/ 64 <1704000000>; +- opp-microvolt = <861000>; +- }; +- +- opp-1896000000 { +- opp-hz = /bits/ 64 <1896000000>; +- opp-microvolt = <981000>; +- }; +- +- opp-1992000000 { +- opp-hz = /bits/ 64 <1992000000>; +- opp-microvolt = <1001000>; +- }; +- }; +- +- cpub_opp_table_1: opp-table-1 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- opp-microvolt = <751000>; +- }; +- +- opp-250000000 { +- opp-hz = /bits/ 64 <250000000>; +- opp-microvolt = <751000>; +- }; +- +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <751000>; +- }; +- +- opp-667000000 { +- opp-hz = /bits/ 64 <667000000>; +- opp-microvolt = <751000>; +- }; +- +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <771000>; +- }; +- +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <771000>; +- }; +- +- opp-1398000000 { +- opp-hz = /bits/ 64 <1398000000>; +- opp-microvolt = <791000>; +- }; +- +- opp-1512000000 { +- opp-hz = /bits/ 64 <1512000000>; +- opp-microvolt = <821000>; +- }; +- +- opp-1608000000 { +- opp-hz = /bits/ 64 <1608000000>; +- opp-microvolt = <861000>; +- }; +- +- opp-1704000000 { +- opp-hz = /bits/ 64 <1704000000>; +- opp-microvolt = <891000>; +- }; +- +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <981000>; +- }; +- +- opp-1908000000 { +- opp-hz = /bits/ 64 <1908000000>; +- opp-microvolt = <1022000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-ugoos-am6.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-ugoos-am6.dts +deleted file mode 100644 +index 0c7892600d56..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-ugoos-am6.dts ++++ /dev/null +@@ -1,184 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- * Copyright (c) 2019 Christian Hewitt +- */ +- +-/dts-v1/; +- +-#include "meson-g12b-w400.dtsi" +-#include +- +-/ { +- compatible = "ugoos,am6", "amlogic,s922x", "amlogic,g12b"; +- model = "Ugoos AM6"; +- +- spdif_dit: audio-codec-1 { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- status = "okay"; +- sound-name-prefix = "DIT"; +- }; +- +- sound { +- compatible = "amlogic,axg-sound-card"; +- model = "UGOOS-AM6"; +- audio-aux-devs = <&tdmout_b>; +- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", +- "TDMOUT_B IN 1", "FRDDR_B OUT 1", +- "TDMOUT_B IN 2", "FRDDR_C OUT 1", +- "TDM_B Playback", "TDMOUT_B OUT", +- "SPDIFOUT IN 0", "FRDDR_A OUT 3", +- "SPDIFOUT IN 1", "FRDDR_B OUT 3", +- "SPDIFOUT IN 2", "FRDDR_C OUT 3"; +- +- assigned-clocks = <&clkc CLKID_MPLL2>, +- <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&frddr_a>; +- }; +- +- dai-link-1 { +- sound-dai = <&frddr_b>; +- }; +- +- dai-link-2 { +- sound-dai = <&frddr_c>; +- }; +- +- /* 8ch hdmi interface */ +- dai-link-3 { +- sound-dai = <&tdmif_b>; +- dai-format = "i2s"; +- dai-tdm-slot-tx-mask-0 = <1 1>; +- dai-tdm-slot-tx-mask-1 = <1 1>; +- dai-tdm-slot-tx-mask-2 = <1 1>; +- dai-tdm-slot-tx-mask-3 = <1 1>; +- mclk-fs = <256>; +- +- codec { +- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; +- }; +- }; +- +- /* spdif hdmi or toslink interface */ +- dai-link-4 { +- sound-dai = <&spdifout>; +- +- codec-0 { +- sound-dai = <&spdif_dit>; +- }; +- +- codec-1 { +- sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>; +- }; +- }; +- +- /* spdif hdmi interface */ +- dai-link-5 { +- sound-dai = <&spdifout_b>; +- +- codec { +- sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>; +- }; +- }; +- +- /* hdmi glue */ +- dai-link-6 { +- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; +- +- codec { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +-}; +- +-&arb { +- status = "okay"; +-}; +- +-&clkc_audio { +- status = "okay"; +-}; +- +-&frddr_a { +- status = "okay"; +-}; +- +-&frddr_b { +- status = "okay"; +-}; +- +-&frddr_c { +- status = "okay"; +-}; +- +-&ir { +- linux,rc-map-name = "rc-khadas"; +-}; +- +-&spdifout { +- pinctrl-0 = <&spdif_out_h_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&spdifout_b { +- status = "okay"; +-}; +- +-&tdmif_b { +- status = "okay"; +-}; +- +-&tdmout_b { +- status = "okay"; +-}; +- +-&tohdmitx { +- status = "okay"; +-}; +- +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; +- max-speed = <2000000>; +- clocks = <&wifi32k>; +- clock-names = "lpo"; +- }; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- status = "okay"; +- dr_mode = "host"; +- vbus-supply = <&usb_pwr_en>; +-}; +- +-&usb2_phy0 { +- phy-supply = <&usb1_pow>; +-}; +- +-&usb2_phy1 { +- phy-supply = <&usb1_pow>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-w400.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-w400.dtsi +deleted file mode 100644 +index b40d2c1002c9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b-w400.dtsi ++++ /dev/null +@@ -1,425 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- * Copyright (c) 2019 Christian Hewitt +- */ +- +-/dts-v1/; +- +-#include "meson-g12b.dtsi" +-#include "meson-g12b-s922x.dtsi" +-#include +-#include +- +-/ { +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x40000000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; +- clocks = <&wifi32k>; +- clock-names = "ext_clock"; +- }; +- +- flash_1v8: regulator-flash_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "FLASH_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_3v3>; +- regulator-always-on; +- }; +- +- main_12v: regulator-main_12v { +- compatible = "regulator-fixed"; +- regulator-name = "12V"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- }; +- +- vcc_5v: regulator-vcc_5v { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&main_12v>; +- +- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; +- enable-active-high; +- }; +- +- vcc_1v8: regulator-vcc_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_3v3>; +- regulator-always-on; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- /* FIXME: actually controlled by VDDCPU_B_EN */ +- }; +- +- vddcpu_a: regulator-vddcpu-a { +- /* +- * MP1653 Regulator. +- */ +- compatible = "pwm-regulator"; +- +- regulator-name = "VDDCPU_A"; +- regulator-min-microvolt = <721000>; +- regulator-max-microvolt = <1022000>; +- +- pwm-supply = <&main_12v>; +- +- pwms = <&pwm_ab 0 1250 0>; +- pwm-dutycycle-range = <100 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vddcpu_b: regulator-vddcpu-b { +- /* +- * MP1652 Regulator. +- */ +- compatible = "pwm-regulator"; +- +- regulator-name = "VDDCPU_B"; +- regulator-min-microvolt = <721000>; +- regulator-max-microvolt = <1022000>; +- +- pwm-supply = <&main_12v>; +- +- pwms = <&pwm_AO_cd 1 1250 0>; +- pwm-dutycycle-range = <100 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +- +- usb1_pow: regulator-usb1-pow { +- compatible = "regulator-fixed"; +- regulator-name = "USB1_POW"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc_5v>; +- +- /* connected to SY6280A Power Switch */ +- gpio = <&gpio GPIOA_8 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- usb_pwr_en: regulator-usb-pwr-en { +- compatible = "regulator-fixed"; +- regulator-name = "USB_PWR_EN"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc_5v>; +- +- /* Connected to USB3 Type-A Port power enable */ +- gpio = <&gpio GPIOAO_7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vddao_1v8: regulator-vddao-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- }; +- +- vddao_3v3: regulator-vddao-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&main_12v>; +- regulator-always-on; +- }; +- +- cvbs-connector { +- compatible = "composite-video-connector"; +- +- port { +- cvbs_connector_in: endpoint { +- remote-endpoint = <&cvbs_vdac_out>; +- }; +- }; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- wifi32k: wifi32k { +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ +- }; +-}; +- +-&cec_AO { +- pinctrl-0 = <&cec_ao_a_h_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cecb_AO { +- pinctrl-0 = <&cec_ao_b_h_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cpu0 { +- cpu-supply = <&vddcpu_b>; +- operating-points-v2 = <&cpu_opp_table_0>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu1 { +- cpu-supply = <&vddcpu_b>; +- operating-points-v2 = <&cpu_opp_table_0>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu100 { +- cpu-supply = <&vddcpu_a>; +- operating-points-v2 = <&cpub_opp_table_1>; +- clocks = <&clkc CLKID_CPUB_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu101 { +- cpu-supply = <&vddcpu_a>; +- operating-points-v2 = <&cpub_opp_table_1>; +- clocks = <&clkc CLKID_CPUB_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu102 { +- cpu-supply = <&vddcpu_a>; +- operating-points-v2 = <&cpub_opp_table_1>; +- clocks = <&clkc CLKID_CPUB_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu103 { +- cpu-supply = <&vddcpu_a>; +- operating-points-v2 = <&cpub_opp_table_1>; +- clocks = <&clkc CLKID_CPUB_CLK>; +- clock-latency = <50000>; +-}; +- +-&cvbs_vdac_port { +- cvbs_vdac_out: endpoint { +- remote-endpoint = <&cvbs_connector_in>; +- }; +-}; +- +-&ext_mdio { +- external_phy: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- max-speed = <1000>; +- +- reset-assert-us = <10000>; +- reset-deassert-us = <80000>; +- reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; +- +- interrupt-parent = <&gpio_intc>; +- /* MAC_INTR on GPIOZ_14 */ +- interrupts = <26 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-ðmac { +- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy-mode = "rgmii"; +- phy-handle = <&external_phy>; +- amlogic,tx-delay-ns = <2>; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; +- pinctrl-names = "default"; +- hdmi-supply = <&vcc_5v>; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&pwm_ab { +- pinctrl-0 = <&pwm_a_e_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>; +- clock-names = "clkin0"; +- status = "okay"; +-}; +- +-&pwm_AO_cd { +- pinctrl-0 = <&pwm_ao_d_e_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>; +- clock-names = "clkin1"; +- status = "okay"; +-}; +- +-&pwm_ef { +- pinctrl-0 = <&pwm_e_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>; +- clock-names = "clkin0"; +- status = "okay"; +-}; +- +-/* SDIO */ +-&sd_emmc_a { +- status = "okay"; +- pinctrl-0 = <&sdio_pins>; +- pinctrl-1 = <&sdio_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <100000000>; +- +- /* WiFi firmware requires power to be kept while in suspend */ +- keep-power-in-suspend; +- +- non-removable; +- disable-wp; +- +- mmc-pwrseq = <&sdio_pwrseq>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddao_1v8>; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_c_pins>; +- pinctrl-1 = <&sdcard_clk_gate_c_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- disable-wp; +- +- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddao_3v3>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- max-frequency = <100000000>; +- disable-wp; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&flash_1v8>; +-}; +- +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; +- max-speed = <2000000>; +- clocks = <&wifi32k>; +- clock-names = "lpo"; +- }; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- status = "okay"; +- dr_mode = "host"; +- vbus-supply = <&usb_pwr_en>; +-}; +- +-&usb2_phy0 { +- phy-supply = <&usb1_pow>; +-}; +- +-&usb2_phy1 { +- phy-supply = <&usb1_pow>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b.dtsi +deleted file mode 100644 +index ee8fcae9f9f0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-g12b.dtsi ++++ /dev/null +@@ -1,141 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- */ +- +-#include "meson-g12.dtsi" +- +-/ { +- compatible = "amlogic,g12b"; +- +- cpus { +- #address-cells = <0x2>; +- #size-cells = <0x0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- +- core1 { +- cpu = <&cpu1>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&cpu100>; +- }; +- +- core1 { +- cpu = <&cpu101>; +- }; +- +- core2 { +- cpu = <&cpu102>; +- }; +- +- core3 { +- cpu = <&cpu103>; +- }; +- }; +- }; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- capacity-dmips-mhz = <592>; +- next-level-cache = <&l2>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- capacity-dmips-mhz = <592>; +- next-level-cache = <&l2>; +- #cooling-cells = <2>; +- }; +- +- cpu100: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a73"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- next-level-cache = <&l2>; +- #cooling-cells = <2>; +- }; +- +- cpu101: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a73"; +- reg = <0x0 0x101>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- next-level-cache = <&l2>; +- #cooling-cells = <2>; +- }; +- +- cpu102: cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a73"; +- reg = <0x0 0x102>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- next-level-cache = <&l2>; +- #cooling-cells = <2>; +- }; +- +- cpu103: cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a73"; +- reg = <0x0 0x103>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- next-level-cache = <&l2>; +- #cooling-cells = <2>; +- }; +- +- l2: l2-cache0 { +- compatible = "cache"; +- }; +- }; +-}; +- +-&clkc { +- compatible = "amlogic,g12b-clkc"; +-}; +- +-&cpu_thermal { +- cooling-maps { +- map0 { +- trip = <&cpu_passive>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu_hot>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +-}; +- +-&mali { +- dma-coherent; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gx-libretech-pc.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gx-libretech-pc.dtsi +deleted file mode 100644 +index 2d7032f41e4b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gx-libretech-pc.dtsi ++++ /dev/null +@@ -1,447 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019 BayLibre SAS. +- * Author: Jerome Brunet +- */ +- +-/* Libretech Amlogic GX PC form factor - AKA: Tartiflette */ +- +-#include +-#include +-#include +- +-/ { +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 0>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1800000>; +- +- update-button { +- label = "update"; +- linux,code = ; +- press-threshold-microvolt = <1300000>; +- }; +- }; +- +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- spi0 = &spifc; +- }; +- +- dio2133: analog-amplifier { +- compatible = "simple-audio-amplifier"; +- sound-name-prefix = "AU2"; +- VCC-supply = <&vcc5v>; +- enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- cvbs-connector { +- compatible = "composite-video-connector"; +- status = "disabled"; +- +- port { +- cvbs_connector_in: endpoint { +- remote-endpoint = <&cvbs_vdac_out>; +- }; +- }; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- poll-interval = <100>; +- +- power-button { +- label = "power"; +- linux,code = ; +- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- ao_5v: regulator-ao_5v { +- compatible = "regulator-fixed"; +- regulator-name = "AO_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&dc_in>; +- regulator-always-on; +- }; +- +- dc_in: regulator-dc_in { +- compatible = "regulator-fixed"; +- regulator-name = "DC_IN"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-green { +- color = ; +- function = LED_FUNCTION_DISK_ACTIVITY; +- gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "disk-activity"; +- }; +- +- led-blue { +- color = ; +- function = LED_FUNCTION_STATUS; +- gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- panic-indicator; +- }; +- }; +- +- vcc_card: regulator-vcc_card { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_CARD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vddio_ao3v3>; +- +- gpio = <&gpio GPIODV_4 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vcc5v: regulator-vcc5v { +- compatible = "regulator-fixed"; +- regulator-name = "VCC5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&ao_5v>; +- +- gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>; +- }; +- +- vddio_ao18: regulator-vddio_ao18 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&ao_5v>; +- regulator-always-on; +- }; +- +- vddio_ao3v3: regulator-vddio_ao3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&ao_5v>; +- regulator-always-on; +- }; +- +- vddio_boot: regulator-vddio_boot { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_BOOT"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vddio_ao3v3>; +- regulator-always-on; +- }; +- +- vddio_card: regulator-vddio-card { +- compatible = "regulator-gpio"; +- regulator-name = "VDDIO_CARD"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio GPIODV_5 GPIO_ACTIVE_HIGH>; +- gpios-states = <0>; +- +- states = <3300000 0>, +- <1800000 1>; +- +- regulator-settling-time-up-us = <200>; +- regulator-settling-time-down-us = <50000>; +- }; +- +- sound { +- compatible = "amlogic,gx-sound-card"; +- model = "LIBRETECH-PC"; +- audio-aux-devs = <&dio2133>; +- audio-widgets = "Speaker", "7J4-14 LEFT", +- "Speaker", "7J4-11 RIGHT"; +- audio-routing = "AU2 INL", "ACODEC LOLN", +- "AU2 INR", "ACODEC LORN", +- "7J4-14 LEFT", "AU2 OUTL", +- "7J4-11 RIGHT", "AU2 OUTR"; +- assigned-clocks = <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>, +- <&clkc CLKID_MPLL2>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; +- }; +- +- dai-link-1 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; +- dai-format = "i2s"; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&aiu AIU_HDMI CTRL_I2S>; +- }; +- +- codec-1 { +- sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; +- }; +- }; +- +- dai-link-2 { +- sound-dai = <&aiu AIU_HDMI CTRL_OUT>; +- +- codec-0 { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- +- dai-link-3 { +- sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; +- +- codec-0 { +- sound-dai = <&acodec>; +- }; +- }; +- }; +-}; +- +-&acodec { +- AVDD-supply = <&vddio_ao18>; +- status = "okay"; +-}; +- +-&aiu { +- status = "okay"; +-}; +- +-&cec_AO { +- pinctrl-0 = <&ao_cec_pins>; +- pinctrl-names = "default"; +- hdmi-phandle = <&hdmi_tx>; +- status = "okay"; +-}; +- +-&cvbs_vdac_port { +- cvbs_vdac_out: endpoint { +- remote-endpoint = <&cvbs_connector_in>; +- }; +-}; +- +-ðmac { +- pinctrl-0 = <ð_pins>, <ð_phy_irq_pins>; +- pinctrl-names = "default"; +- phy-handle = <&external_phy>; +- amlogic,tx-delay-ns = <2>; +- phy-mode = "rgmii"; +- status = "okay"; +-}; +- +-&external_mdio { +- external_phy: ethernet-phy@0 { +- reg = <0>; +- max-speed = <1000>; +- reset-assert-us = <10000>; +- reset-deassert-us = <30000>; +- reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; +- interrupt-parent = <&gpio_intc>; +- interrupts = <25 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&pinctrl_periphs { +- /* +- * Make sure the reset pin of the usb HUB is driven high to take +- * it out of reset. +- */ +- usb1_rst_pins: usb1_rst_irq { +- mux { +- groups = "GPIODV_3"; +- function = "gpio_periphs"; +- bias-disable; +- output-high; +- }; +- }; +- +- /* Make sure the phy irq pin is properly configured as input */ +- eth_phy_irq_pins: eth_phy_irq { +- mux { +- groups = "GPIOZ_15"; +- function = "gpio_periphs"; +- bias-disable; +- output-disable; +- }; +- }; +-}; +- +-&hdmi_tx { +- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +- pinctrl-names = "default"; +- hdmi-supply = <&vcc5v>; +- status = "okay"; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&ir { +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&i2c_C { +- pinctrl-0 = <&i2c_c_dv18_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- rtc: rtc@51 { +- reg = <0x51>; +- compatible = "nxp,pcf8563"; +- #clock-cells = <0>; +- clock-output-names = "rtc_clkout"; +- }; +-}; +- +-&pwm_AO_ab { +- pinctrl-0 = <&pwm_ao_a_3_pins>; +- pinctrl-names = "default"; +- clocks = <&clkc CLKID_FCLK_DIV4>; +- clock-names = "clkin0"; +- status = "okay"; +-}; +- +-&pwm_ab { +- pinctrl-0 = <&pwm_b_pins>; +- pinctrl-names = "default"; +- clocks = <&clkc CLKID_FCLK_DIV4>; +- clock-names = "clkin0"; +- status = "okay"; +-}; +- +-&pwm_ef { +- pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; +- pinctrl-names = "default"; +- clocks = <&clkc CLKID_FCLK_DIV4>; +- clock-names = "clkin0"; +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vddio_ao18>; +- status = "okay"; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- pinctrl-0 = <&sdcard_pins>; +- pinctrl-1 = <&sdcard_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-ddr50; +- max-frequency = <200000000>; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&vcc_card>; +- vqmmc-supply = <&vddio_card>; +- +- status = "okay"; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- pinctrl-0 = <&emmc_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- max-frequency = <200000000>; +- disable-wp; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vddio_ao3v3>; +- vqmmc-supply = <&vddio_boot>; +- +- status = "okay"; +-}; +- +-&spifc { +- pinctrl-0 = <&nor_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- gd25lq128: spi-flash@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- spi-max-frequency = <12000000>; +- }; +-}; +- +-&uart_AO { +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&usb { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&usb2_phy0 { +- pinctrl-0 = <&usb1_rst_pins>; +- pinctrl-names = "default"; +- phy-supply = <&vcc5v>; +-}; +- +-&usb2_phy1 { +- phy-supply = <&vcc5v>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gx-mali450.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gx-mali450.dtsi +deleted file mode 100644 +index f9771b51c852..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gx-mali450.dtsi ++++ /dev/null +@@ -1,61 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 BayLibre SAS +- * Author: Neil Armstrong +- */ +- +-/ { +- gpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-125000000 { +- opp-hz = /bits/ 64 <125000000>; +- opp-microvolt = <950000>; +- }; +- opp-250000000 { +- opp-hz = /bits/ 64 <250000000>; +- opp-microvolt = <950000>; +- }; +- opp-285714285 { +- opp-hz = /bits/ 64 <285714285>; +- opp-microvolt = <950000>; +- }; +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <950000>; +- }; +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <950000>; +- }; +- opp-666666666 { +- opp-hz = /bits/ 64 <666666666>; +- opp-microvolt = <950000>; +- }; +- opp-744000000 { +- opp-hz = /bits/ 64 <744000000>; +- opp-microvolt = <950000>; +- }; +- }; +-}; +- +-&apb { +- mali: gpu@c0000 { +- compatible = "arm,mali-450"; +- reg = <0x0 0xc0000 0x0 0x40000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "gp", "gpmmu", "pp", "pmu", +- "pp0", "ppmmu0", "pp1", "ppmmu1", +- "pp2", "ppmmu2"; +- operating-points-v2 = <&gpu_opp_table>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gx-p23x-q20x.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gx-p23x-q20x.dtsi +deleted file mode 100644 +index dafc841f7c16..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gx-p23x-q20x.dtsi ++++ /dev/null +@@ -1,324 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Endless Computers, Inc. +- * Author: Carlo Caione +- */ +- +-/* Common DTSI for same Amlogic Q200/Q201 and P230/P231 boards using either +- * the pin-compatible S912 (GXM) or S905D (GXL) SoCs. +- */ +- +-#include +- +-/ { +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- dio2133: analog-amplifier { +- compatible = "simple-audio-amplifier"; +- sound-name-prefix = "AU2"; +- VCC-supply = <&hdmi_5v>; +- enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; +- }; +- +- spdif_dit: audio-codec-0 { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- status = "okay"; +- sound-name-prefix = "DIT"; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- hdmi_5v: regulator-hdmi-5v { +- compatible = "regulator-fixed"; +- +- regulator-name = "HDMI_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- vddio_ao18: regulator-vddio_ao18 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vddio_boot: regulator-vddio_boot { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_BOOT"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vddao_3v3: regulator-vddao_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- wifi32k: wifi32k { +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; +- clocks = <&wifi32k>; +- clock-names = "ext_clock"; +- }; +- +- cvbs-connector { +- compatible = "composite-video-connector"; +- +- port { +- cvbs_connector_in: endpoint { +- remote-endpoint = <&cvbs_vdac_out>; +- }; +- }; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- sound { +- compatible = "amlogic,gx-sound-card"; +- model = "P230-Q200"; +- audio-aux-devs = <&dio2133>; +- audio-widgets = "Line", "Lineout"; +- audio-routing = "AU2 INL", "ACODEC LOLP", +- "AU2 INR", "ACODEC LORP", +- "AU2 INL", "ACODEC LOLN", +- "AU2 INR", "ACODEC LORN", +- "Lineout", "AU2 OUTL", +- "Lineout", "AU2 OUTR"; +- assigned-clocks = <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>, +- <&clkc CLKID_MPLL2>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; +- }; +- +- dai-link-1 { +- sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>; +- }; +- +- dai-link-2 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; +- dai-format = "i2s"; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&aiu AIU_HDMI CTRL_I2S>; +- }; +- +- codec-1 { +- sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; +- }; +- }; +- +- dai-link-3 { +- sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>; +- +- codec-0 { +- sound-dai = <&spdif_dit>; +- }; +- }; +- +- dai-link-4 { +- sound-dai = <&aiu AIU_HDMI CTRL_OUT>; +- +- codec-0 { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- +- dai-link-5 { +- sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; +- +- codec-0 { +- sound-dai = <&acodec>; +- }; +- }; +- }; +-}; +- +-&acodec { +- AVDD-supply = <&vddio_ao18>; +- status = "okay"; +-}; +- +-&aiu { +- status = "okay"; +- pinctrl-0 = <&spdif_out_h_pins>; +- pinctrl-names = "default"; +- +-}; +- +-&cec_AO { +- status = "okay"; +- pinctrl-0 = <&ao_cec_pins>; +- pinctrl-names = "default"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cvbs_vdac_port { +- cvbs_vdac_out: endpoint { +- remote-endpoint = <&cvbs_connector_in>; +- }; +-}; +- +-ðmac { +- status = "okay"; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +- pinctrl-names = "default"; +- hdmi-supply = <&hdmi_5v>; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&pwm_ef { +- status = "okay"; +- pinctrl-0 = <&pwm_e_pins>; +- pinctrl-names = "default"; +- clocks = <&clkc CLKID_FCLK_DIV4>; +- clock-names = "clkin0"; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vddio_ao18>; +-}; +- +-/* Wireless SDIO Module */ +-&sd_emmc_a { +- status = "okay"; +- pinctrl-0 = <&sdio_pins>; +- pinctrl-1 = <&sdio_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- +- non-removable; +- disable-wp; +- +- /* WiFi firmware requires power to be kept while in suspend */ +- keep-power-in-suspend; +- +- mmc-pwrseq = <&sdio_pwrseq>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_pins>; +- pinctrl-1 = <&sdcard_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- max-frequency = <200000000>; +- non-removable; +- disable-wp; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-/* This UART is brought out to the DB9 connector */ +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- status = "okay"; +- dr_mode = "otg"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gx.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gx.dtsi +deleted file mode 100644 +index aa14ea017a61..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gx.dtsi ++++ /dev/null +@@ -1,674 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Andreas Färber +- * +- * Copyright (c) 2016 BayLibre, SAS. +- * Author: Neil Armstrong +- * +- * Copyright (c) 2016 Endless Computers, Inc. +- * Author: Carlo Caione +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- mmc0 = &sd_emmc_b; /* SD card */ +- mmc1 = &sd_emmc_c; /* eMMC */ +- mmc2 = &sd_emmc_a; /* SDIO */ +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- /* 16 MiB reserved for Hardware ROM Firmware */ +- hwrom_reserved: hwrom@0 { +- reg = <0x0 0x0 0x0 0x1000000>; +- no-map; +- }; +- +- /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ +- secmon_reserved: secmon@10000000 { +- reg = <0x0 0x10000000 0x0 0x200000>; +- no-map; +- }; +- +- /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ +- secmon_reserved_alt: secmon@5000000 { +- reg = <0x0 0x05000000 0x0 0x300000>; +- no-map; +- }; +- +- /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ +- secmon_reserved_bl32: secmon@5300000 { +- reg = <0x0 0x05300000 0x0 0x2000000>; +- no-map; +- }; +- +- linux,cma { +- compatible = "shared-dma-pool"; +- reusable; +- size = <0x0 0x10000000>; +- alignment = <0x0 0x400000>; +- linux,cma-default; +- }; +- }; +- +- chosen { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- simplefb_cvbs: framebuffer-cvbs { +- compatible = "amlogic,simple-framebuffer", +- "simple-framebuffer"; +- amlogic,pipeline = "vpu-cvbs"; +- power-domains = <&pwrc PWRC_GXBB_VPU_ID>; +- status = "disabled"; +- }; +- +- simplefb_hdmi: framebuffer-hdmi { +- compatible = "amlogic,simple-framebuffer", +- "simple-framebuffer"; +- amlogic,pipeline = "vpu-hdmi"; +- power-domains = <&pwrc PWRC_GXBB_VPU_ID>; +- status = "disabled"; +- }; +- }; +- +- cpus { +- #address-cells = <0x2>; +- #size-cells = <0x0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- clocks = <&scpi_dvfs 0>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- clocks = <&scpi_dvfs 0>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- clocks = <&scpi_dvfs 0>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- clocks = <&scpi_dvfs 0>; +- #cooling-cells = <2>; +- }; +- +- l2: l2-cache0 { +- compatible = "cache"; +- }; +- }; +- +- thermal-zones { +- cpu-thermal { +- polling-delay-passive = <250>; /* milliseconds */ +- polling-delay = <1000>; /* milliseconds */ +- +- thermal-sensors = <&scpi_sensors 0>; +- +- trips { +- cpu_passive: cpu-passive { +- temperature = <80000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- +- cpu_hot: cpu-hot { +- temperature = <90000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "hot"; +- }; +- +- cpu_critical: cpu-critical { +- temperature = <110000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- +- cpu_cooling_maps: cooling-maps { +- map0 { +- trip = <&cpu_passive>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- +- map1 { +- trip = <&cpu_hot>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- xtal: xtal-clk { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "xtal"; +- #clock-cells = <0>; +- }; +- +- firmware { +- sm: secure-monitor { +- compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; +- }; +- }; +- +- efuse: efuse { +- compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse"; +- #address-cells = <1>; +- #size-cells = <1>; +- read-only; +- secure-monitor = <&sm>; +- +- sn: sn@14 { +- reg = <0x14 0x10>; +- }; +- +- eth_mac: eth_mac@34 { +- reg = <0x34 0x10>; +- }; +- +- bid: bid@46 { +- reg = <0x46 0x30>; +- }; +- }; +- +- scpi { +- compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; +- mboxes = <&mailbox 1 &mailbox 2>; +- shmem = <&cpu_scp_lpri &cpu_scp_hpri>; +- +- scpi_clocks: clocks { +- compatible = "arm,scpi-clocks"; +- +- scpi_dvfs: scpi_clocks@0 { +- compatible = "arm,scpi-dvfs-clocks"; +- #clock-cells = <1>; +- clock-indices = <0>; +- clock-output-names = "vcpu"; +- }; +- }; +- +- scpi_sensors: sensors { +- compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; +- #thermal-sensor-cells = <1>; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- cbus: bus@c1100000 { +- compatible = "simple-bus"; +- reg = <0x0 0xc1100000 0x0 0x100000>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; +- +- gpio_intc: interrupt-controller@9880 { +- compatible = "amlogic,meson-gpio-intc"; +- reg = <0x0 0x9880 0x0 0x10>; +- interrupt-controller; +- #interrupt-cells = <2>; +- amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; +- status = "disabled"; +- }; +- +- reset: reset-controller@4404 { +- compatible = "amlogic,meson-gxbb-reset"; +- reg = <0x0 0x04404 0x0 0x9c>; +- #reset-cells = <1>; +- }; +- +- aiu: audio-controller@5400 { +- compatible = "amlogic,aiu"; +- #sound-dai-cells = <2>; +- sound-name-prefix = "AIU"; +- reg = <0x0 0x5400 0x0 0x2ac>; +- interrupts = , +- ; +- interrupt-names = "i2s", "spdif"; +- status = "disabled"; +- }; +- +- uart_A: serial@84c0 { +- compatible = "amlogic,meson-gx-uart"; +- reg = <0x0 0x84c0 0x0 0x18>; +- interrupts = ; +- status = "disabled"; +- fifo-size = <128>; +- }; +- +- uart_B: serial@84dc { +- compatible = "amlogic,meson-gx-uart"; +- reg = <0x0 0x84dc 0x0 0x18>; +- interrupts = ; +- status = "disabled"; +- }; +- +- i2c_A: i2c@8500 { +- compatible = "amlogic,meson-gxbb-i2c"; +- reg = <0x0 0x08500 0x0 0x20>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pwm_ab: pwm@8550 { +- compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; +- reg = <0x0 0x08550 0x0 0x10>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm_cd: pwm@8650 { +- compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; +- reg = <0x0 0x08650 0x0 0x10>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- saradc: adc@8680 { +- compatible = "amlogic,meson-saradc"; +- reg = <0x0 0x8680 0x0 0x34>; +- #io-channel-cells = <1>; +- interrupts = ; +- status = "disabled"; +- }; +- +- pwm_ef: pwm@86c0 { +- compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; +- reg = <0x0 0x086c0 0x0 0x10>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- uart_C: serial@8700 { +- compatible = "amlogic,meson-gx-uart"; +- reg = <0x0 0x8700 0x0 0x18>; +- interrupts = ; +- status = "disabled"; +- }; +- +- clock-measure@8758 { +- compatible = "amlogic,meson-gx-clk-measure"; +- reg = <0x0 0x8758 0x0 0x10>; +- }; +- +- i2c_B: i2c@87c0 { +- compatible = "amlogic,meson-gxbb-i2c"; +- reg = <0x0 0x087c0 0x0 0x20>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c_C: i2c@87e0 { +- compatible = "amlogic,meson-gxbb-i2c"; +- reg = <0x0 0x087e0 0x0 0x20>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spicc: spi@8d80 { +- compatible = "amlogic,meson-gx-spicc"; +- reg = <0x0 0x08d80 0x0 0x80>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spifc: spi@8c80 { +- compatible = "amlogic,meson-gxbb-spifc"; +- reg = <0x0 0x08c80 0x0 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- watchdog@98d0 { +- compatible = "amlogic,meson-gxbb-wdt"; +- reg = <0x0 0x098d0 0x0 0x10>; +- clocks = <&xtal>; +- }; +- }; +- +- gic: interrupt-controller@c4301000 { +- compatible = "arm,gic-400"; +- reg = <0x0 0xc4301000 0 0x1000>, +- <0x0 0xc4302000 0 0x2000>, +- <0x0 0xc4304000 0 0x2000>, +- <0x0 0xc4306000 0 0x2000>; +- interrupt-controller; +- interrupts = ; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- }; +- +- sram: sram@c8000000 { +- compatible = "mmio-sram"; +- reg = <0x0 0xc8000000 0x0 0x14000>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x0 0xc8000000 0x14000>; +- +- cpu_scp_lpri: scp-sram@0 { +- compatible = "amlogic,meson-gxbb-scp-shmem"; +- reg = <0x13000 0x400>; +- }; +- +- cpu_scp_hpri: scp-sram@200 { +- compatible = "amlogic,meson-gxbb-scp-shmem"; +- reg = <0x13400 0x400>; +- }; +- }; +- +- aobus: bus@c8100000 { +- compatible = "simple-bus"; +- reg = <0x0 0xc8100000 0x0 0x100000>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; +- +- sysctrl_AO: sys-ctrl@0 { +- compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon"; +- reg = <0x0 0x0 0x0 0x100>; +- +- clkc_AO: clock-controller { +- compatible = "amlogic,meson-gx-aoclkc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- }; +- +- cec_AO: cec@100 { +- compatible = "amlogic,meson-gx-ao-cec"; +- reg = <0x0 0x00100 0x0 0x14>; +- interrupts = ; +- status = "disabled"; +- }; +- +- sec_AO: ao-secure@140 { +- compatible = "amlogic,meson-gx-ao-secure", "syscon"; +- reg = <0x0 0x140 0x0 0x140>; +- amlogic,has-chip-id; +- }; +- +- uart_AO: serial@4c0 { +- compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; +- reg = <0x0 0x004c0 0x0 0x18>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart_AO_B: serial@4e0 { +- compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; +- reg = <0x0 0x004e0 0x0 0x18>; +- interrupts = ; +- status = "disabled"; +- }; +- +- i2c_AO: i2c@500 { +- compatible = "amlogic,meson-gxbb-i2c"; +- reg = <0x0 0x500 0x0 0x20>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pwm_AO_ab: pwm@550 { +- compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm"; +- reg = <0x0 0x00550 0x0 0x10>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- ir: ir@580 { +- compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir"; +- reg = <0x0 0x00580 0x0 0x40>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- vdec: video-codec@c8820000 { +- compatible = "amlogic,gx-vdec"; +- reg = <0x0 0xc8820000 0x0 0x10000>, +- <0x0 0xc110a580 0x0 0xe4>; +- reg-names = "dos", "esparser"; +- +- interrupts = , +- ; +- interrupt-names = "vdec", "esparser"; +- +- amlogic,ao-sysctrl = <&sysctrl_AO>; +- amlogic,canvas = <&canvas>; +- }; +- +- periphs: bus@c8834000 { +- compatible = "simple-bus"; +- reg = <0x0 0xc8834000 0x0 0x2000>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; +- +- hwrng: rng { +- compatible = "amlogic,meson-rng"; +- reg = <0x0 0x0 0x0 0x4>; +- }; +- }; +- +- dmcbus: bus@c8838000 { +- compatible = "simple-bus"; +- reg = <0x0 0xc8838000 0x0 0x400>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>; +- +- canvas: video-lut@48 { +- compatible = "amlogic,canvas"; +- reg = <0x0 0x48 0x0 0x14>; +- }; +- }; +- +- hiubus: bus@c883c000 { +- compatible = "simple-bus"; +- reg = <0x0 0xc883c000 0x0 0x2000>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; +- +- sysctrl: system-controller@0 { +- compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"; +- reg = <0 0 0 0x400>; +- +- pwrc: power-controller { +- compatible = "amlogic,meson-gxbb-pwrc"; +- #power-domain-cells = <1>; +- amlogic,ao-sysctrl = <&sysctrl_AO>; +- }; +- }; +- +- mailbox: mailbox@404 { +- compatible = "amlogic,meson-gxbb-mhu"; +- reg = <0 0x404 0 0x4c>; +- interrupts = , +- , +- ; +- #mbox-cells = <1>; +- }; +- }; +- +- ethmac: ethernet@c9410000 { +- compatible = "amlogic,meson-gxbb-dwmac", +- "snps,dwmac-3.70a", +- "snps,dwmac"; +- reg = <0x0 0xc9410000 0x0 0x10000>, +- <0x0 0xc8834540 0x0 0x4>; +- interrupts = ; +- interrupt-names = "macirq"; +- rx-fifo-depth = <4096>; +- tx-fifo-depth = <2048>; +- power-domains = <&pwrc PWRC_GXBB_ETHERNET_MEM_ID>; +- status = "disabled"; +- }; +- +- apb: apb@d0000000 { +- compatible = "simple-bus"; +- reg = <0x0 0xd0000000 0x0 0x200000>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; +- +- sd_emmc_a: mmc@70000 { +- compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; +- reg = <0x0 0x70000 0x0 0x800>; +- interrupts = ; +- status = "disabled"; +- }; +- +- sd_emmc_b: mmc@72000 { +- compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; +- reg = <0x0 0x72000 0x0 0x800>; +- interrupts = ; +- status = "disabled"; +- }; +- +- sd_emmc_c: mmc@74000 { +- compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; +- reg = <0x0 0x74000 0x0 0x800>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- vpu: vpu@d0100000 { +- compatible = "amlogic,meson-gx-vpu"; +- reg = <0x0 0xd0100000 0x0 0x100000>, +- <0x0 0xc883c000 0x0 0x1000>; +- reg-names = "vpu", "hhi"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- amlogic,canvas = <&canvas>; +- +- /* CVBS VDAC output port */ +- cvbs_vdac_port: port@0 { +- reg = <0>; +- }; +- +- /* HDMI-TX output port */ +- hdmi_tx_port: port@1 { +- reg = <1>; +- +- hdmi_tx_out: endpoint { +- remote-endpoint = <&hdmi_tx_in>; +- }; +- }; +- }; +- +- hdmi_tx: hdmi-tx@c883a000 { +- compatible = "amlogic,meson-gx-dw-hdmi"; +- reg = <0x0 0xc883a000 0x0 0x1c>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "HDMITX"; +- status = "disabled"; +- +- /* VPU VENC Input */ +- hdmi_tx_venc_port: port@0 { +- reg = <0>; +- +- hdmi_tx_in: endpoint { +- remote-endpoint = <&hdmi_tx_out>; +- }; +- }; +- +- /* TMDS Output */ +- hdmi_tx_tmds_port: port@1 { +- reg = <1>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-kii-pro.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-kii-pro.dts +deleted file mode 100644 +index e8394a8269ee..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-kii-pro.dts ++++ /dev/null +@@ -1,82 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Mohammad Rasim +- */ +- +-/dts-v1/; +- +-#include "meson-gxbb-p20x.dtsi" +- +-#include +-#include +-#include +-/ { +- compatible = "videostrong,kii-pro", "amlogic,meson-gxbb"; +- model = "Videostrong KII Pro"; +- +- leds { +- compatible = "gpio-leds"; +- status { +- gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- color = ; +- function = LED_FUNCTION_STATUS; +- }; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- #address-cells = <1>; +- #size-cells = <0>; +- poll-interval = <20>; +- +- button-reset { +- label = "reset"; +- linux,code = ; +- gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +-}; +- +- +- +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- +- bluetooth { +- compatible = "brcm,bcm4335a0"; +- }; +-}; +- +- +- +-ðmac { +- status = "okay"; +- pinctrl-0 = <ð_rmii_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <ð_phy0>; +- phy-mode = "rmii"; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eth_phy0: ethernet-phy@0 { +- /* IC Plus IP101GR (0x02430c54) */ +- reg = <0>; +- reset-assert-us = <10000>; +- reset-deassert-us = <10000>; +- reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&ir { +- linux,rc-map-name = "rc-videostrong-kii-pro"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-nanopi-k2.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-nanopi-k2.dts +deleted file mode 100644 +index 7d94160f5802..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-nanopi-k2.dts ++++ /dev/null +@@ -1,426 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "meson-gxbb.dtsi" +-#include +-#include +- +-/ { +- compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb"; +- model = "FriendlyARM NanoPi K2"; +- +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-stat { +- label = "nanopi-k2:blue:stat"; +- gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- panic-indicator; +- }; +- }; +- +- vdd_5v: regulator-vdd-5v { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- vddio_ao18: regulator-vddio-ao18 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vddio_ao3v3: regulator-vddio-ao3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vddio_tf: regulator-vddio-tf { +- compatible = "regulator-gpio"; +- +- regulator-name = "VDDIO_TF"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; +- gpios-states = <0>; +- +- states = <3300000 0>, +- <1800000 1>; +- +- regulator-settling-time-up-us = <100>; +- regulator-settling-time-down-us = <5000>; +- }; +- +- wifi_32k: wifi-32k { +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; +- clocks = <&wifi_32k>; +- clock-names = "ext_clock"; +- }; +- +- vcc1v8: regulator-vcc1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vcc3v3: regulator-vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- /* CVBS is available on CON1 pin 36, disabled by default */ +- cvbs-connector { +- compatible = "composite-video-connector"; +- status = "disabled"; +- +- port { +- cvbs_connector_in: endpoint { +- remote-endpoint = <&cvbs_vdac_out>; +- }; +- }; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- sound { +- compatible = "amlogic,gx-sound-card"; +- model = "NANOPI-K2"; +- assigned-clocks = <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>, +- <&clkc CLKID_MPLL2>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; +- }; +- +- dai-link-1 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; +- dai-format = "i2s"; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&aiu AIU_HDMI CTRL_I2S>; +- }; +- }; +- +- dai-link-2 { +- sound-dai = <&aiu AIU_HDMI CTRL_OUT>; +- +- codec-0 { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +-}; +- +-&aiu { +- status = "okay"; +-}; +- +-&cec_AO { +- status = "okay"; +- pinctrl-0 = <&ao_cec_pins>; +- pinctrl-names = "default"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cvbs_vdac_port { +- cvbs_vdac_out: endpoint { +- remote-endpoint = <&cvbs_connector_in>; +- }; +-}; +- +-ðmac { +- status = "okay"; +- pinctrl-0 = <ð_rgmii_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <ð_phy0>; +- phy-mode = "rgmii"; +- +- amlogic,tx-delay-ns = <2>; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eth_phy0: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- +- reset-assert-us = <10000>; +- reset-deassert-us = <80000>; +- reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; +- +- interrupt-parent = <&gpio_intc>; +- /* MAC_INTR on GPIOZ_15 */ +- interrupts = <29 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +- pinctrl-names = "default"; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&gpio_ao { +- gpio-line-names = "UART TX", "UART RX", "Power Control", "Power Key In", +- "VCCK En", "CON1 Header Pin31", +- "I2S Header Pin6", "IR In", "I2S Header Pin7", +- "I2S Header Pin3", "I2S Header Pin4", +- "I2S Header Pin5", "HDMI CEC", "SYS LED", +- /* GPIO_TEST_N */ +- ""; +-}; +- +-&gpio { +- gpio-line-names = /* Bank GPIOZ */ +- "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk", +- "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2", +- "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En", +- "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3", +- "Eth PHY nRESET", "Eth PHY Intc", +- /* Bank GPIOH */ +- "HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", +- "CON1 Header Pin33", +- /* Bank BOOT */ +- "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4", +- "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk", +- "eMMC Reset", "eMMC CMD", +- "", "", "", "", "eMMC DS", +- "", "", +- /* Bank CARD */ +- "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", +- "SDCard D3", "SDCard D2", "SDCard Det", +- /* Bank GPIODV */ +- "", "", "", "", "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", "", "", +- "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", +- "VDDEE Regulator", "VCCK Regulator", +- /* Bank GPIOY */ +- "CON1 Header Pin7", "CON1 Header Pin11", +- "CON1 Header Pin13", "CON1 Header Pin15", +- "CON1 Header Pin18", "CON1 Header Pin19", +- "CON1 Header Pin22", "CON1 Header Pin21", +- "CON1 Header Pin24", "CON1 Header Pin23", +- "CON1 Header Pin26", "CON1 Header Pin29", +- "CON1 Header Pin32", "CON1 Header Pin8", +- "CON1 Header Pin10", "CON1 Header Pin16", +- "CON1 Header Pin12", +- /* Bank GPIOX */ +- "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2", +- "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD", +- "WIFI Power Enable", "WIFI WAKE HOST", +- "Bluetooth PCM DOUT", "Bluetooth PCM DIN", +- "Bluetooth PCM SYNC", "Bluetooth PCM CLK", +- "Bluetooth UART TX", "Bluetooth UART RX", +- "Bluetooth UART CTS", "Bluetooth UART RTS", +- "", "", "", "WIFI 32K", "Bluetooth Enable", +- "Bluetooth WAKE HOST", "", +- /* Bank GPIOCLK */ +- "", "CON1 Header Pin35", "", ""; +-}; +- +-&pwm_ef { +- status = "okay"; +- pinctrl-0 = <&pwm_e_pins>; +- pinctrl-names = "default"; +- clocks = <&clkc CLKID_FCLK_DIV4>; +- clock-names = "clkin0"; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vddio_ao18>; +-}; +- +-/* SDIO */ +-&sd_emmc_a { +- status = "okay"; +- pinctrl-0 = <&sdio_pins>, <&sdio_irq_pins>; +- pinctrl-1 = <&sdio_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- +- non-removable; +- disable-wp; +- +- /* WiFi firmware requires power to be kept while in suspend */ +- keep-power-in-suspend; +- +- mmc-pwrseq = <&sdio_pwrseq>; +- +- vmmc-supply = <&vddio_ao3v3>; +- vqmmc-supply = <&vddio_ao18>; +- +- brcmf: wifi@1 { +- compatible = "brcm,bcm4329-fmac"; +- reg = <1>; +- }; +-}; +- +-/* SD */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_pins>; +- pinctrl-1 = <&sdcard_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-ddr50; +- max-frequency = <100000000>; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&vddio_ao3v3>; +- vqmmc-supply = <&vddio_tf>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "disabled"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- max-frequency = <200000000>; +- non-removable; +- disable-wp; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc3v3>; +- vqmmc-supply = <&vcc1v8>; +-}; +- +-/* DBG_UART */ +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-/* Bluetooth on AP6212 */ +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&wifi_32k>; +- clock-names = "lpo"; +- vbat-supply = <&vddio_ao3v3>; +- vddio-supply = <&vddio_ao18>; +- host-wakeup-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-/* 40-pin CON1 */ +-&uart_C { +- status = "disabled"; +- pinctrl-0 = <&uart_c_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb0_phy { +- status = "okay"; +- phy-supply = <&vdd_5v>; +-}; +- +-&usb1_phy { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-nexbox-a95x.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-nexbox-a95x.dts +deleted file mode 100644 +index f887bfb445fd..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-nexbox-a95x.dts ++++ /dev/null +@@ -1,331 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Andreas Färber +- * Copyright (c) 2016 BayLibre, Inc. +- * Author: Neil Armstrong +- */ +- +-/dts-v1/; +- +-#include "meson-gxbb.dtsi" +-#include +-#include +-#include +- +-/ { +- compatible = "nexbox,a95x", "amlogic,meson-gxbb"; +- model = "NEXBOX A95X"; +- +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x40000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-blue { +- label = "a95x:system-status"; +- gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- #address-cells = <1>; +- #size-cells = <0>; +- poll-interval = <100>; +- +- button@0 { +- label = "reset"; +- linux,code = ; +- gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- usb_pwr: regulator-usb-pwrs { +- compatible = "regulator-fixed"; +- +- regulator-name = "USB_PWR"; +- +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vddio_card: gpio-regulator { +- compatible = "regulator-gpio"; +- +- regulator-name = "VDDIO_CARD"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- +- /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ +- states = <1800000 0>, +- <3300000 1>; +- }; +- +- vddio_boot: regulator-vddio_boot { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_BOOT"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vddao_3v3: regulator-vddao_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- wifi32k: wifi32k { +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; +- clocks = <&wifi32k>; +- clock-names = "ext_clock"; +- }; +- +- cvbs-connector { +- compatible = "composite-video-connector"; +- +- port { +- cvbs_connector_in: endpoint { +- remote-endpoint = <&cvbs_vdac_out>; +- }; +- }; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- sound { +- compatible = "amlogic,gx-sound-card"; +- model = "NEXBOX-A95X"; +- assigned-clocks = <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>, +- <&clkc CLKID_MPLL2>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; +- }; +- +- dai-link-1 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; +- dai-format = "i2s"; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&aiu AIU_HDMI CTRL_I2S>; +- }; +- }; +- +- dai-link-2 { +- sound-dai = <&aiu AIU_HDMI CTRL_OUT>; +- +- codec-0 { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +-}; +- +-&aiu { +- status = "okay"; +-}; +- +-&cvbs_vdac_port { +- cvbs_vdac_out: endpoint { +- remote-endpoint = <&cvbs_connector_in>; +- }; +-}; +- +-&cec_AO { +- status = "okay"; +- pinctrl-0 = <&ao_cec_pins>; +- pinctrl-names = "default"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-ðmac { +- status = "okay"; +- pinctrl-0 = <ð_rmii_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <ð_phy0>; +- phy-mode = "rmii"; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eth_phy0: ethernet-phy@0 { +- /* IC Plus IP101GR (0x02430c54) */ +- reg = <0>; +- +- reset-assert-us = <10000>; +- reset-deassert-us = <10000>; +- reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +- pinctrl-names = "default"; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&pwm_ef { +- status = "okay"; +- pinctrl-0 = <&pwm_e_pins>; +- pinctrl-names = "default"; +- clocks = <&clkc CLKID_FCLK_DIV4>; +- clock-names = "clkin0"; +-}; +- +-/* Wireless SDIO Module */ +-&sd_emmc_a { +- status = "okay"; +- pinctrl-0 = <&sdio_pins>; +- pinctrl-1 = <&sdio_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <100000000>; +- +- non-removable; +- disable-wp; +- +- /* WiFi firmware requires power to be kept while in suspend */ +- keep-power-in-suspend; +- +- mmc-pwrseq = <&sdio_pwrseq>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_pins>; +- pinctrl-1 = <&sdcard_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_card>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- max-frequency = <200000000>; +- non-removable; +- disable-wp; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb0_phy { +- status = "okay"; +- phy-supply = <&usb_pwr>; +-}; +- +-&usb1_phy { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-odroidc2.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-odroidc2.dts +deleted file mode 100644 +index 201596247fd9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-odroidc2.dts ++++ /dev/null +@@ -1,418 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Andreas Färber +- * Copyright (c) 2016 BayLibre, Inc. +- * Author: Kevin Hilman +- */ +- +-/dts-v1/; +- +-#include "meson-gxbb.dtsi" +-#include +-#include +- +-/ { +- compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb"; +- model = "Hardkernel ODROID-C2"; +- +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- usb_otg_pwr: regulator-usb-pwrs { +- compatible = "regulator-fixed"; +- +- regulator-name = "USB_OTG_PWR"; +- +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- /* +- * signal name from schematics: PWREN +- */ +- gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- /* +- * signal name from schematics: USB_POWER +- */ +- vin-supply = <&p5v0>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-blue { +- label = "c2:blue:alive"; +- gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- }; +- +- p5v0: regulator-p5v0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "P5V0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- hdmi_p5v0: regulator-hdmi_p5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "HDMI_P5V0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- /* AP2331SA-7 */ +- vin-supply = <&p5v0>; +- }; +- +- tflash_vdd: regulator-tflash_vdd { +- compatible = "regulator-fixed"; +- +- regulator-name = "TFLASH_VDD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- /* +- * signal name from schematics: TFLASH_VDD_EN +- */ +- gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- /* U16 RT9179GB */ +- vin-supply = <&vddio_ao3v3>; +- }; +- +- tf_io: gpio-regulator-tf_io { +- compatible = "regulator-gpio"; +- +- regulator-name = "TF_IO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- /* +- * signal name from schematics: TF_3V3N_1V8_EN +- */ +- gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; +- gpios-states = <0>; +- +- states = <3300000 0>, +- <1800000 1>; +- /* U12/U13 RT9179GB */ +- vin-supply = <&vddio_ao3v3>; +- }; +- +- vcc1v8: regulator-vcc1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- /* U18 RT9179GB */ +- vin-supply = <&vddio_ao3v3>; +- }; +- +- vcc3v3: regulator-vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vddio_ao1v8: regulator-vddio-ao1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- /* U17 RT9179GB */ +- vin-supply = <&p5v0>; +- }; +- +- vddio_ao3v3: regulator-vddio-ao3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- /* U11 MP2161GJ-C499 */ +- vin-supply = <&p5v0>; +- }; +- +- ddr3_1v5: regulator-ddr3_1v5 { +- compatible = "regulator-fixed"; +- regulator-name = "DDR3_1V5"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- /* U15 MP2161GJ-C499 */ +- vin-supply = <&p5v0>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- sound { +- compatible = "amlogic,gx-sound-card"; +- model = "ODROID-C2"; +- assigned-clocks = <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>, +- <&clkc CLKID_MPLL2>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; +- }; +- +- dai-link-1 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; +- dai-format = "i2s"; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&aiu AIU_HDMI CTRL_I2S>; +- }; +- }; +- +- dai-link-2 { +- sound-dai = <&aiu AIU_HDMI CTRL_OUT>; +- +- codec-0 { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +-}; +- +-&aiu { +- status = "okay"; +-}; +- +-&cec_AO { +- status = "okay"; +- pinctrl-0 = <&ao_cec_pins>; +- pinctrl-names = "default"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-ðmac { +- status = "okay"; +- pinctrl-0 = <ð_rgmii_pins>; +- pinctrl-names = "default"; +- phy-handle = <ð_phy0>; +- phy-mode = "rgmii"; +- +- amlogic,tx-delay-ns = <2>; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eth_phy0: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- +- reset-assert-us = <10000>; +- reset-deassert-us = <80000>; +- reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; +- +- interrupt-parent = <&gpio_intc>; +- /* MAC_INTR on GPIOZ_15 */ +- interrupts = <29 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +-}; +- +-&gpio_ao { +- /* +- * WARNING: The USB Hub on the Odroid-C2 needs a reset signal +- * to be turned high in order to be detected by the USB Controller +- * This signal should be handled by a USB specific power sequence +- * in order to reset the Hub when USB bus is powered down. +- */ +- hog-0 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "usb-hub-reset"; +- }; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +- pinctrl-names = "default"; +- hdmi-supply = <&hdmi_p5v0>; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&i2c_A { +- status = "okay"; +- pinctrl-0 = <&i2c_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +- linux,rc-map-name = "rc-odroid"; +-}; +- +-&gpio_ao { +- gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En", +- "USB HUB nRESET", "USB OTG Power En", +- "J7 Header Pin2", "IR In", "J7 Header Pin4", +- "J7 Header Pin6", "J7 Header Pin5", "J7 Header Pin7", +- "HDMI CEC", "SYS LED", +- /* GPIO_TEST_N */ +- ""; +-}; +- +-&gpio { +- gpio-line-names = /* Bank GPIOZ */ +- "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk", +- "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2", +- "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En", +- "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3", +- "Eth PHY nRESET", "Eth PHY Intc", +- /* Bank GPIOH */ +- "HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", "", +- /* Bank BOOT */ +- "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4", +- "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk", +- "eMMC Reset", "eMMC CMD", +- "", "", "", "", "", "", "", +- /* Bank CARD */ +- "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", +- "SDCard D3", "SDCard D2", "SDCard Det", +- /* Bank GPIODV */ +- "", "", "", "", "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", "", "", +- "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", +- "PWM D", "PWM B", +- /* Bank GPIOY */ +- "Revision Bit0", "Revision Bit1", "", +- "J2 Header Pin35", "", "", "", "J2 Header Pin36", +- "J2 Header Pin31", "", "", "", "TF VDD En", +- "J2 Header Pin32", "J2 Header Pin26", "", "", +- /* Bank GPIOX */ +- "J2 Header Pin29", "J2 Header Pin24", +- "J2 Header Pin23", "J2 Header Pin22", +- "J2 Header Pin21", "J2 Header Pin18", +- "J2 Header Pin33", "J2 Header Pin19", +- "J2 Header Pin16", "J2 Header Pin15", +- "J2 Header Pin12", "J2 Header Pin13", +- "J2 Header Pin8", "J2 Header Pin10", +- "", "", "", "", "", +- "J2 Header Pin11", "", "J2 Header Pin7", "", +- /* Bank GPIOCLK */ +- "", "", "", ""; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vcc1v8>; +-}; +- +-&scpi_clocks { +- status = "disabled"; +-}; +- +-/* SD */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_pins>; +- pinctrl-1 = <&sdcard_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-ddr50; +- max-frequency = <100000000>; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&tflash_vdd>; +- vqmmc-supply = <&tf_io>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- max-frequency = <200000000>; +- non-removable; +- disable-wp; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc3v3>; +- vqmmc-supply = <&vcc1v8>; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb0_phy { +- status = "disabled"; +- phy-supply = <&usb_otg_pwr>; +-}; +- +-&usb1_phy { +- status = "okay"; +- phy-supply = <&usb_otg_pwr>; +-}; +- +-&usb0 { +- status = "disabled"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-p200.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-p200.dts +deleted file mode 100644 +index 3c93d1898b40..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-p200.dts ++++ /dev/null +@@ -1,100 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Andreas Färber +- * Copyright (c) 2016 BayLibre, Inc. +- * Author: Kevin Hilman +- */ +- +-/dts-v1/; +- +-#include "meson-gxbb-p20x.dtsi" +-#include +- +-/ { +- compatible = "amlogic,p200", "amlogic,meson-gxbb"; +- model = "Amlogic Meson GXBB P200 Development Board"; +- +- avdd18_usb_adc: regulator-avdd18_usb_adc { +- compatible = "regulator-fixed"; +- regulator-name = "AVDD18_USB_ADC"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- adc_keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 0>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1800000>; +- +- button-home { +- label = "Home"; +- linux,code = ; +- press-threshold-microvolt = <900000>; /* 50% */ +- }; +- +- button-esc { +- label = "Esc"; +- linux,code = ; +- press-threshold-microvolt = <684000>; /* 38% */ +- }; +- +- button-up { +- label = "Volume Up"; +- linux,code = ; +- press-threshold-microvolt = <468000>; /* 26% */ +- }; +- +- button-down { +- label = "Volume Down"; +- linux,code = ; +- press-threshold-microvolt = <252000>; /* 14% */ +- }; +- +- button-menu { +- label = "Menu"; +- linux,code = ; +- press-threshold-microvolt = <0>; /* 0% */ +- }; +- }; +-}; +- +-ðmac { +- status = "okay"; +- pinctrl-0 = <ð_rgmii_pins>; +- pinctrl-names = "default"; +- phy-handle = <ð_phy0>; +- phy-mode = "rgmii"; +- +- amlogic,tx-delay-ns = <2>; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eth_phy0: ethernet-phy@3 { +- /* Micrel KSZ9031 (0x00221620) */ +- reg = <3>; +- +- reset-assert-us = <10000>; +- reset-deassert-us = <30000>; +- reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; +- +- interrupt-parent = <&gpio_intc>; +- /* MAC_INTR on GPIOZ_15 */ +- interrupts = <29 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +-}; +- +-&i2c_B { +- status = "okay"; +- pinctrl-0 = <&i2c_b_pins>; +- pinctrl-names = "default"; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&avdd18_usb_adc>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-p201.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-p201.dts +deleted file mode 100644 +index 150a82f3b2d7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-p201.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Andreas Färber +- * Copyright (c) 2016 BayLibre, Inc. +- * Author: Kevin Hilman +- */ +- +-/dts-v1/; +- +-#include "meson-gxbb-p20x.dtsi" +- +-/ { +- compatible = "amlogic,p201", "amlogic,meson-gxbb"; +- model = "Amlogic Meson GXBB P201 Development Board"; +-}; +- +-ðmac { +- status = "okay"; +- pinctrl-0 = <ð_rmii_pins>; +- pinctrl-names = "default"; +- phy-mode = "rmii"; +- +- snps,reset-gpio = <&gpio GPIOZ_14 0>; +- snps,reset-delays-us = <0>, <10000>, <1000000>; +- snps,reset-active-low; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-p20x.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-p20x.dtsi +deleted file mode 100644 +index e803a466fe4e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-p20x.dtsi ++++ /dev/null +@@ -1,250 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Andreas Färber +- * Copyright (c) 2016 BayLibre, Inc. +- * Author: Kevin Hilman +- */ +- +-#include "meson-gxbb.dtsi" +- +-/ { +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x40000000>; +- }; +- +- usb_pwr: regulator-usb-pwrs { +- compatible = "regulator-fixed"; +- +- regulator-name = "USB_PWR"; +- +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- /* signal name in schematic: USB_PWR_EN */ +- gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vddio_card: gpio-regulator { +- compatible = "regulator-gpio"; +- +- regulator-name = "VDDIO_CARD"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- +- /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ +- states = <1800000 0>, +- <3300000 1>; +- +- regulator-settling-time-up-us = <10000>; +- regulator-settling-time-down-us = <150000>; +- }; +- +- vddio_boot: regulator-vddio_boot { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_BOOT"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vddao_3v3: regulator-vddao_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- wifi32k: wifi32k { +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; +- clocks = <&wifi32k>; +- clock-names = "ext_clock"; +- }; +- +- cvbs_connector: cvbs-connector { +- compatible = "composite-video-connector"; +- +- port { +- cvbs_connector_in: endpoint { +- remote-endpoint = <&cvbs_vdac_out>; +- }; +- }; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +-}; +- +-&cec_AO { +- status = "okay"; +- pinctrl-0 = <&ao_cec_pins>; +- pinctrl-names = "default"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cvbs_vdac_port { +- cvbs_vdac_out: endpoint { +- remote-endpoint = <&cvbs_connector_in>; +- }; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +- pinctrl-names = "default"; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&pwm_ef { +- status = "okay"; +- pinctrl-0 = <&pwm_e_pins>; +- pinctrl-names = "default"; +- clocks = <&clkc CLKID_FCLK_DIV4>; +- clock-names = "clkin0"; +-}; +- +-/* Wireless SDIO Module */ +-&sd_emmc_a { +- status = "okay"; +- pinctrl-0 = <&sdio_pins>; +- pinctrl-1 = <&sdio_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- +- non-removable; +- disable-wp; +- +- /* WiFi firmware requires power to be kept while in suspend */ +- keep-power-in-suspend; +- +- mmc-pwrseq = <&sdio_pwrseq>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_boot>; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_pins>; +- pinctrl-1 = <&sdcard_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- max-frequency = <100000000>; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_card>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- max-frequency = <200000000>; +- non-removable; +- disable-wp; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-/* This UART is brought out to the DB9 connector */ +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb0_phy { +- status = "okay"; +- phy-supply = <&usb_pwr>; +-}; +- +-&usb1_phy { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-vega-s95-meta.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-vega-s95-meta.dts +deleted file mode 100644 +index c928adf85388..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-vega-s95-meta.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "meson-gxbb-vega-s95.dtsi" +- +-/ { +- compatible = "tronsmart,vega-s95-meta", "tronsmart,vega-s95", "amlogic,meson-gxbb"; +- model = "Tronsmart Vega S95 Meta"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-vega-s95-pro.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-vega-s95-pro.dts +deleted file mode 100644 +index e81e1d68b5fa..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-vega-s95-pro.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "meson-gxbb-vega-s95.dtsi" +- +-/ { +- compatible = "tronsmart,vega-s95-pro", "tronsmart,vega-s95", "amlogic,meson-gxbb"; +- model = "Tronsmart Vega S95 Pro"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x40000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-vega-s95-telos.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-vega-s95-telos.dts +deleted file mode 100644 +index a8fca0c6903f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-vega-s95-telos.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "meson-gxbb-vega-s95.dtsi" +- +-/ { +- compatible = "tronsmart,vega-s95-telos", "tronsmart,vega-s95", "amlogic,meson-gxbb"; +- model = "Tronsmart Vega S95 Telos"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-vega-s95.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-vega-s95.dtsi +deleted file mode 100644 +index 66daf3af34c3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-vega-s95.dtsi ++++ /dev/null +@@ -1,337 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Andreas Färber +- */ +- +-#include "meson-gxbb.dtsi" +-#include +- +-/ { +- compatible = "tronsmart,vega-s95", "amlogic,meson-gxbb"; +- +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- spdif_dit: audio-codec-0 { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- status = "okay"; +- sound-name-prefix = "DIT"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-blue { +- label = "vega-s95:blue:on"; +- gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- panic-indicator; +- }; +- }; +- +- usb_pwr: regulator-usb-pwrs { +- compatible = "regulator-fixed"; +- +- regulator-name = "USB_PWR"; +- +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vddio_boot: regulator-vddio_boot { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_BOOT"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vddao_3v3: regulator-vddao_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vddio_ao18: regulator-vddio_ao18 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- wifi32k: wifi32k { +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; +- clocks = <&wifi32k>; +- clock-names = "ext_clock"; +- }; +- +- sound { +- compatible = "amlogic,gx-sound-card"; +- model = "VEGA-S95"; +- assigned-clocks = <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>, +- <&clkc CLKID_MPLL2>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; +- }; +- +- dai-link-1 { +- sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>; +- }; +- +- dai-link-2 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; +- dai-format = "i2s"; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&aiu AIU_HDMI CTRL_I2S>; +- }; +- }; +- +- dai-link-3 { +- sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>; +- +- codec-0 { +- sound-dai = <&spdif_dit>; +- }; +- }; +- +- dai-link-4 { +- sound-dai = <&aiu AIU_HDMI CTRL_OUT>; +- +- codec-0 { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +-}; +- +-&aiu { +- status = "okay"; +- pinctrl-0 = <&spdif_out_y_pins>; +- pinctrl-names = "default"; +-}; +- +-&cec_AO { +- status = "okay"; +- pinctrl-0 = <&ao_cec_pins>; +- pinctrl-names = "default"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-ðmac { +- status = "okay"; +- pinctrl-0 = <ð_rgmii_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <ð_phy0>; +- phy-mode = "rgmii"; +- +- amlogic,tx-delay-ns = <2>; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eth_phy0: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- +- reset-assert-us = <10000>; +- reset-deassert-us = <80000>; +- reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; +- +- interrupt-parent = <&gpio_intc>; +- /* MAC_INTR on GPIOZ_15 */ +- interrupts = <29 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +- pinctrl-names = "default"; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +- linux,rc-map-name = "rc-vega-s9x"; +-}; +- +-&pwm_ef { +- status = "okay"; +- pinctrl-0 = <&pwm_e_pins>; +- pinctrl-names = "default"; +- clocks = <&clkc CLKID_FCLK_DIV4>; +- clock-names = "clkin0"; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vddio_ao18>; +-}; +- +-/* Wireless SDIO Module */ +-&sd_emmc_a { +- status = "okay"; +- pinctrl-0 = <&sdio_pins>; +- pinctrl-1 = <&sdio_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- +- non-removable; +- disable-wp; +- +- /* WiFi firmware requires power to be kept while in suspend */ +- keep-power-in-suspend; +- +- mmc-pwrseq = <&sdio_pwrseq>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_boot>; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_pins>; +- pinctrl-1 = <&sdcard_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vcc_3v3>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- max-frequency = <200000000>; +- non-removable; +- disable-wp; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-/* This is connected to the Bluetooth module: */ +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; +- pinctrl-names = "default"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; +- max-speed = <2000000>; +- clocks = <&wifi32k>; +- clock-names = "lpo"; +- }; +-}; +- +-/* This UART is brought out to the DB9 connector */ +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb0_phy { +- status = "okay"; +- phy-supply = <&usb_pwr>; +-}; +- +-&usb1_phy { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-wetek-hub.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-wetek-hub.dts +deleted file mode 100644 +index 58733017eda8..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-wetek-hub.dts ++++ /dev/null +@@ -1,58 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 BayLibre, Inc. +- * Author: Neil Armstrong +- */ +- +-/dts-v1/; +- +-#include "meson-gxbb-wetek.dtsi" +-#include +- +-/ { +- compatible = "wetek,hub", "amlogic,meson-gxbb"; +- model = "WeTek Hub"; +- +- sound { +- compatible = "amlogic,gx-sound-card"; +- model = "WETEK-HUB"; +- assigned-clocks = <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>, +- <&clkc CLKID_MPLL2>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; +- }; +- +- dai-link-1 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; +- dai-format = "i2s"; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&aiu AIU_HDMI CTRL_I2S>; +- }; +- }; +- +- dai-link-2 { +- sound-dai = <&aiu AIU_HDMI CTRL_OUT>; +- +- codec-0 { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +-}; +- +-&aiu { +- status = "okay"; +-}; +- +-&ir { +- linux,rc-map-name = "rc-wetek-hub"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-wetek-play2.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-wetek-play2.dts +deleted file mode 100644 +index 6eae692792ec..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-wetek-play2.dts ++++ /dev/null +@@ -1,121 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 BayLibre, Inc. +- * Author: Neil Armstrong +- */ +- +-/dts-v1/; +- +-#include "meson-gxbb-wetek.dtsi" +-#include +-#include +- +-/ { +- compatible = "wetek,play2", "amlogic,meson-gxbb"; +- model = "WeTek Play 2"; +- +- spdif_dit: audio-codec-0 { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- status = "okay"; +- sound-name-prefix = "DIT"; +- }; +- +- leds { +- led-wifi { +- label = "wetek-play:wifi-status"; +- gpios = <&gpio GPIODV_26 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-ethernet { +- label = "wetek-play:ethernet-status"; +- gpios = <&gpio GPIODV_27 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- #address-cells = <1>; +- #size-cells = <0>; +- poll-interval = <100>; +- +- button@0 { +- label = "reset"; +- linux,code = ; +- gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- sound { +- compatible = "amlogic,gx-sound-card"; +- model = "WETEK-PLAY2"; +- assigned-clocks = <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>, +- <&clkc CLKID_MPLL2>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; +- }; +- +- dai-link-1 { +- sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>; +- }; +- +- dai-link-2 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; +- dai-format = "i2s"; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&aiu AIU_HDMI CTRL_I2S>; +- }; +- }; +- +- dai-link-3 { +- sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>; +- +- codec-0 { +- sound-dai = <&spdif_dit>; +- }; +- }; +- +- dai-link-4 { +- sound-dai = <&aiu AIU_HDMI CTRL_OUT>; +- +- codec-0 { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +-}; +- +-&aiu { +- status = "okay"; +- pinctrl-0 = <&spdif_out_y_pins>; +- pinctrl-names = "default"; +-}; +- +-&i2c_A { +- status = "okay"; +- pinctrl-0 = <&i2c_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb1_phy { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&ir { +- linux,rc-map-name = "rc-wetek-play2"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-wetek.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-wetek.dtsi +deleted file mode 100644 +index a4d34398da35..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb-wetek.dtsi ++++ /dev/null +@@ -1,289 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Andreas Färber +- * Copyright (c) 2016 BayLibre, Inc. +- * Author: Kevin Hilman +- */ +- +-#include "meson-gxbb.dtsi" +-#include +- +-/ { +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x40000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-system { +- label = "wetek-play:system-status"; +- gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- panic-indicator; +- }; +- }; +- +- usb_pwr: regulator-usb-pwrs { +- compatible = "regulator-fixed"; +- +- regulator-name = "USB_PWR"; +- +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vddio_boot: regulator-vddio_boot { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_BOOT"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vddao_3v3: regulator-vddao_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vddio_ao18: regulator-vddio_ao18 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- wifi32k: wifi32k { +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; +- clocks = <&wifi32k>; +- clock-names = "ext_clock"; +- }; +- +- cvbs-connector { +- compatible = "composite-video-connector"; +- +- port { +- cvbs_connector_in: endpoint { +- remote-endpoint = <&cvbs_vdac_out>; +- }; +- }; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +-}; +- +-&cec_AO { +- status = "okay"; +- pinctrl-0 = <&ao_cec_pins>; +- pinctrl-names = "default"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cvbs_vdac_port { +- cvbs_vdac_out: endpoint { +- remote-endpoint = <&cvbs_connector_in>; +- }; +-}; +- +-ðmac { +- status = "okay"; +- pinctrl-0 = <ð_rgmii_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <ð_phy0>; +- phy-mode = "rgmii"; +- +- amlogic,tx-delay-ns = <2>; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eth_phy0: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- +- reset-assert-us = <10000>; +- reset-deassert-us = <80000>; +- reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; +- +- interrupt-parent = <&gpio_intc>; +- /* MAC_INTR on GPIOZ_15 */ +- interrupts = <29 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +- pinctrl-names = "default"; +- hdmi-supply = <&vddio_ao18>; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&pwm_ef { +- status = "okay"; +- pinctrl-0 = <&pwm_e_pins>; +- pinctrl-names = "default"; +- clocks = <&clkc CLKID_FCLK_DIV4>; +- clock-names = "clkin0"; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vddio_ao18>; +-}; +- +-/* Wireless SDIO Module */ +-&sd_emmc_a { +- status = "okay"; +- pinctrl-0 = <&sdio_pins>; +- pinctrl-1 = <&sdio_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- +- non-removable; +- disable-wp; +- +- /* WiFi firmware requires power to be kept while in suspend */ +- keep-power-in-suspend; +- +- mmc-pwrseq = <&sdio_pwrseq>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_boot>; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_pins>; +- pinctrl-1 = <&sdcard_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vcc_3v3>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- max-frequency = <200000000>; +- non-removable; +- disable-wp; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-/* This is connected to the Bluetooth module: */ +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-/* This UART is brought out to the DB9 connector */ +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb0_phy { +- status = "okay"; +- phy-supply = <&usb_pwr>; +-}; +- +-&usb0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb.dtsi +deleted file mode 100644 +index 7c029f552a23..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxbb.dtsi ++++ /dev/null +@@ -1,856 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Andreas Färber +- */ +- +-#include "meson-gx.dtsi" +-#include "meson-gx-mali450.dtsi" +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "amlogic,meson-gxbb"; +- +- soc { +- usb0_phy: phy@c0000000 { +- compatible = "amlogic,meson-gxbb-usb2-phy"; +- #phy-cells = <0>; +- reg = <0x0 0xc0000000 0x0 0x20>; +- resets = <&reset RESET_USB_OTG>; +- clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; +- clock-names = "usb_general", "usb"; +- status = "disabled"; +- }; +- +- usb1_phy: phy@c0000020 { +- compatible = "amlogic,meson-gxbb-usb2-phy"; +- #phy-cells = <0>; +- reg = <0x0 0xc0000020 0x0 0x20>; +- resets = <&reset RESET_USB_OTG>; +- clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; +- clock-names = "usb_general", "usb"; +- status = "disabled"; +- }; +- +- usb0: usb@c9000000 { +- compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; +- reg = <0x0 0xc9000000 0x0 0x40000>; +- interrupts = ; +- clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; +- clock-names = "otg"; +- phys = <&usb0_phy>; +- phy-names = "usb2-phy"; +- dr_mode = "host"; +- status = "disabled"; +- }; +- +- usb1: usb@c9100000 { +- compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; +- reg = <0x0 0xc9100000 0x0 0x40000>; +- interrupts = ; +- clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; +- clock-names = "otg"; +- phys = <&usb1_phy>; +- phy-names = "usb2-phy"; +- dr_mode = "host"; +- status = "disabled"; +- }; +- }; +-}; +- +-&aiu { +- compatible = "amlogic,aiu-gxbb", "amlogic,aiu"; +- clocks = <&clkc CLKID_AIU_GLUE>, +- <&clkc CLKID_I2S_OUT>, +- <&clkc CLKID_AOCLK_GATE>, +- <&clkc CLKID_CTS_AMCLK>, +- <&clkc CLKID_MIXER_IFACE>, +- <&clkc CLKID_IEC958>, +- <&clkc CLKID_IEC958_GATE>, +- <&clkc CLKID_CTS_MCLK_I958>, +- <&clkc CLKID_CTS_I958>; +- clock-names = "pclk", +- "i2s_pclk", +- "i2s_aoclk", +- "i2s_mclk", +- "i2s_mixer", +- "spdif_pclk", +- "spdif_aoclk", +- "spdif_mclk", +- "spdif_mclk_sel"; +- resets = <&reset RESET_AIU>; +-}; +- +-&aobus { +- pinctrl_aobus: pinctrl@14 { +- compatible = "amlogic,meson-gxbb-aobus-pinctrl"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gpio_ao: bank@14 { +- reg = <0x0 0x00014 0x0 0x8>, +- <0x0 0x0002c 0x0 0x4>, +- <0x0 0x00024 0x0 0x8>; +- reg-names = "mux", "pull", "gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl_aobus 0 0 14>; +- }; +- +- uart_ao_a_pins: uart_ao_a { +- mux { +- groups = "uart_tx_ao_a", "uart_rx_ao_a"; +- function = "uart_ao"; +- bias-disable; +- }; +- }; +- +- uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { +- mux { +- groups = "uart_cts_ao_a", +- "uart_rts_ao_a"; +- function = "uart_ao"; +- bias-disable; +- }; +- }; +- +- uart_ao_b_pins: uart_ao_b { +- mux { +- groups = "uart_tx_ao_b", "uart_rx_ao_b"; +- function = "uart_ao_b"; +- bias-disable; +- }; +- }; +- +- uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { +- mux { +- groups = "uart_cts_ao_b", +- "uart_rts_ao_b"; +- function = "uart_ao_b"; +- bias-disable; +- }; +- }; +- +- remote_input_ao_pins: remote_input_ao { +- mux { +- groups = "remote_input_ao"; +- function = "remote_input_ao"; +- bias-disable; +- }; +- }; +- +- i2c_ao_pins: i2c_ao { +- mux { +- groups = "i2c_sck_ao", +- "i2c_sda_ao"; +- function = "i2c_ao"; +- bias-disable; +- }; +- }; +- +- pwm_ao_a_3_pins: pwm_ao_a_3 { +- mux { +- groups = "pwm_ao_a_3"; +- function = "pwm_ao_a_3"; +- bias-disable; +- }; +- }; +- +- pwm_ao_a_6_pins: pwm_ao_a_6 { +- mux { +- groups = "pwm_ao_a_6"; +- function = "pwm_ao_a_6"; +- bias-disable; +- }; +- }; +- +- pwm_ao_a_12_pins: pwm_ao_a_12 { +- mux { +- groups = "pwm_ao_a_12"; +- function = "pwm_ao_a_12"; +- bias-disable; +- }; +- }; +- +- pwm_ao_b_pins: pwm_ao_b { +- mux { +- groups = "pwm_ao_b"; +- function = "pwm_ao_b"; +- bias-disable; +- }; +- }; +- +- i2s_am_clk_pins: i2s_am_clk { +- mux { +- groups = "i2s_am_clk"; +- function = "i2s_out_ao"; +- bias-disable; +- }; +- }; +- +- i2s_out_ao_clk_pins: i2s_out_ao_clk { +- mux { +- groups = "i2s_out_ao_clk"; +- function = "i2s_out_ao"; +- bias-disable; +- }; +- }; +- +- i2s_out_lr_clk_pins: i2s_out_lr_clk { +- mux { +- groups = "i2s_out_lr_clk"; +- function = "i2s_out_ao"; +- bias-disable; +- }; +- }; +- +- i2s_out_ch01_ao_pins: i2s_out_ch01_ao { +- mux { +- groups = "i2s_out_ch01_ao"; +- function = "i2s_out_ao"; +- bias-disable; +- }; +- }; +- +- i2s_out_ch23_ao_pins: i2s_out_ch23_ao { +- mux { +- groups = "i2s_out_ch23_ao"; +- function = "i2s_out_ao"; +- bias-disable; +- }; +- }; +- +- i2s_out_ch45_ao_pins: i2s_out_ch45_ao { +- mux { +- groups = "i2s_out_ch45_ao"; +- function = "i2s_out_ao"; +- bias-disable; +- }; +- }; +- +- spdif_out_ao_6_pins: spdif_out_ao_6 { +- mux { +- groups = "spdif_out_ao_6"; +- function = "spdif_out_ao"; +- }; +- }; +- +- spdif_out_ao_13_pins: spdif_out_ao_13 { +- mux { +- groups = "spdif_out_ao_13"; +- function = "spdif_out_ao"; +- bias-disable; +- }; +- }; +- +- ao_cec_pins: ao_cec { +- mux { +- groups = "ao_cec"; +- function = "cec_ao"; +- bias-disable; +- }; +- }; +- +- ee_cec_pins: ee_cec { +- mux { +- groups = "ee_cec"; +- function = "cec_ao"; +- bias-disable; +- }; +- }; +- }; +-}; +- +-&cbus { +- spifc: spi@8c80 { +- compatible = "amlogic,meson-gxbb-spifc"; +- reg = <0x0 0x08c80 0x0 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clkc CLKID_SPI>; +- status = "disabled"; +- }; +-}; +- +-&cec_AO { +- clocks = <&clkc_AO CLKID_AO_CEC_32K>; +- clock-names = "core"; +-}; +- +-&clkc_AO { +- compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; +- clocks = <&xtal>, <&clkc CLKID_CLK81>; +- clock-names = "xtal", "mpeg-clk"; +-}; +- +-&efuse { +- clocks = <&clkc CLKID_EFUSE>; +-}; +- +-ðmac { +- clocks = <&clkc CLKID_ETH>, +- <&clkc CLKID_FCLK_DIV2>, +- <&clkc CLKID_MPLL2>, +- <&clkc CLKID_FCLK_DIV2>; +- clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; +-}; +- +-&gpio_intc { +- compatible = "amlogic,meson-gpio-intc", +- "amlogic,meson-gxbb-gpio-intc"; +- status = "okay"; +-}; +- +-&hdmi_tx { +- compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; +- resets = <&reset RESET_HDMITX_CAPB3>, +- <&reset RESET_HDMI_SYSTEM_RESET>, +- <&reset RESET_HDMI_TX>; +- reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; +- clocks = <&clkc CLKID_HDMI_PCLK>, +- <&clkc CLKID_CLK81>, +- <&clkc CLKID_GCLK_VENCI_INT0>; +- clock-names = "isfr", "iahb", "venci"; +-}; +- +-&sysctrl { +- clkc: clock-controller { +- compatible = "amlogic,gxbb-clkc"; +- #clock-cells = <1>; +- clocks = <&xtal>; +- clock-names = "xtal"; +- }; +-}; +- +-&hwrng { +- clocks = <&clkc CLKID_RNG0>; +- clock-names = "core"; +-}; +- +-&i2c_A { +- clocks = <&clkc CLKID_I2C>; +-}; +- +-&i2c_AO { +- clocks = <&clkc CLKID_AO_I2C>; +-}; +- +-&i2c_B { +- clocks = <&clkc CLKID_I2C>; +-}; +- +-&i2c_C { +- clocks = <&clkc CLKID_I2C>; +-}; +- +-&mali { +- compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; +- +- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; +- clock-names = "bus", "core"; +- +- assigned-clocks = <&clkc CLKID_GP0_PLL>; +- assigned-clock-rates = <744000000>; +-}; +- +-&periphs { +- pinctrl_periphs: pinctrl@4b0 { +- compatible = "amlogic,meson-gxbb-periphs-pinctrl"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gpio: bank@4b0 { +- reg = <0x0 0x004b0 0x0 0x28>, +- <0x0 0x004e8 0x0 0x14>, +- <0x0 0x00520 0x0 0x14>, +- <0x0 0x00430 0x0 0x40>; +- reg-names = "mux", "pull", "pull-enable", "gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl_periphs 0 0 119>; +- }; +- +- emmc_pins: emmc { +- mux-0 { +- groups = "emmc_nand_d07", +- "emmc_cmd"; +- function = "emmc"; +- bias-pull-up; +- }; +- +- mux-1 { +- groups = "emmc_clk"; +- function = "emmc"; +- bias-disable; +- }; +- }; +- +- emmc_ds_pins: emmc-ds { +- mux { +- groups = "emmc_ds"; +- function = "emmc"; +- bias-pull-down; +- }; +- }; +- +- emmc_clk_gate_pins: emmc_clk_gate { +- mux { +- groups = "BOOT_8"; +- function = "gpio_periphs"; +- bias-pull-down; +- }; +- }; +- +- nor_pins: nor { +- mux { +- groups = "nor_d", +- "nor_q", +- "nor_c", +- "nor_cs"; +- function = "nor"; +- bias-disable; +- }; +- }; +- +- spi_pins: spi-pins { +- mux { +- groups = "spi_miso", +- "spi_mosi", +- "spi_sclk"; +- function = "spi"; +- bias-disable; +- }; +- }; +- +- spi_ss0_pins: spi-ss0 { +- mux { +- groups = "spi_ss0"; +- function = "spi"; +- bias-disable; +- }; +- }; +- +- sdcard_pins: sdcard { +- mux-0 { +- groups = "sdcard_d0", +- "sdcard_d1", +- "sdcard_d2", +- "sdcard_d3", +- "sdcard_cmd"; +- function = "sdcard"; +- bias-pull-up; +- }; +- +- mux-1 { +- groups = "sdcard_clk"; +- function = "sdcard"; +- bias-disable; +- }; +- }; +- +- sdcard_clk_gate_pins: sdcard_clk_gate { +- mux { +- groups = "CARD_2"; +- function = "gpio_periphs"; +- bias-pull-down; +- }; +- }; +- +- sdio_pins: sdio { +- mux-0 { +- groups = "sdio_d0", +- "sdio_d1", +- "sdio_d2", +- "sdio_d3", +- "sdio_cmd"; +- function = "sdio"; +- bias-pull-up; +- }; +- +- mux-1 { +- groups = "sdio_clk"; +- function = "sdio"; +- bias-disable; +- }; +- }; +- +- sdio_clk_gate_pins: sdio_clk_gate { +- mux { +- groups = "GPIOX_4"; +- function = "gpio_periphs"; +- bias-pull-down; +- }; +- }; +- +- sdio_irq_pins: sdio_irq { +- mux { +- groups = "sdio_irq"; +- function = "sdio"; +- bias-disable; +- }; +- }; +- +- uart_a_pins: uart_a { +- mux { +- groups = "uart_tx_a", +- "uart_rx_a"; +- function = "uart_a"; +- bias-disable; +- }; +- }; +- +- uart_a_cts_rts_pins: uart_a_cts_rts { +- mux { +- groups = "uart_cts_a", +- "uart_rts_a"; +- function = "uart_a"; +- bias-disable; +- }; +- }; +- +- uart_b_pins: uart_b { +- mux { +- groups = "uart_tx_b", +- "uart_rx_b"; +- function = "uart_b"; +- bias-disable; +- }; +- }; +- +- uart_b_cts_rts_pins: uart_b_cts_rts { +- mux { +- groups = "uart_cts_b", +- "uart_rts_b"; +- function = "uart_b"; +- bias-disable; +- }; +- }; +- +- uart_c_pins: uart_c { +- mux { +- groups = "uart_tx_c", +- "uart_rx_c"; +- function = "uart_c"; +- bias-disable; +- }; +- }; +- +- uart_c_cts_rts_pins: uart_c_cts_rts { +- mux { +- groups = "uart_cts_c", +- "uart_rts_c"; +- function = "uart_c"; +- bias-disable; +- }; +- }; +- +- i2c_a_pins: i2c_a { +- mux { +- groups = "i2c_sck_a", +- "i2c_sda_a"; +- function = "i2c_a"; +- bias-disable; +- }; +- }; +- +- i2c_b_pins: i2c_b { +- mux { +- groups = "i2c_sck_b", +- "i2c_sda_b"; +- function = "i2c_b"; +- bias-disable; +- }; +- }; +- +- i2c_c_pins: i2c_c { +- mux { +- groups = "i2c_sck_c", +- "i2c_sda_c"; +- function = "i2c_c"; +- bias-disable; +- }; +- }; +- +- eth_rgmii_pins: eth-rgmii { +- mux { +- groups = "eth_mdio", +- "eth_mdc", +- "eth_clk_rx_clk", +- "eth_rx_dv", +- "eth_rxd0", +- "eth_rxd1", +- "eth_rxd2", +- "eth_rxd3", +- "eth_rgmii_tx_clk", +- "eth_tx_en", +- "eth_txd0", +- "eth_txd1", +- "eth_txd2", +- "eth_txd3"; +- function = "eth"; +- bias-disable; +- }; +- }; +- +- eth_rmii_pins: eth-rmii { +- mux { +- groups = "eth_mdio", +- "eth_mdc", +- "eth_clk_rx_clk", +- "eth_rx_dv", +- "eth_rxd0", +- "eth_rxd1", +- "eth_tx_en", +- "eth_txd0", +- "eth_txd1"; +- function = "eth"; +- bias-disable; +- }; +- }; +- +- pwm_a_x_pins: pwm_a_x { +- mux { +- groups = "pwm_a_x"; +- function = "pwm_a_x"; +- bias-disable; +- }; +- }; +- +- pwm_a_y_pins: pwm_a_y { +- mux { +- groups = "pwm_a_y"; +- function = "pwm_a_y"; +- bias-disable; +- }; +- }; +- +- pwm_b_pins: pwm_b { +- mux { +- groups = "pwm_b"; +- function = "pwm_b"; +- bias-disable; +- }; +- }; +- +- pwm_d_pins: pwm_d { +- mux { +- groups = "pwm_d"; +- function = "pwm_d"; +- bias-disable; +- }; +- }; +- +- pwm_e_pins: pwm_e { +- mux { +- groups = "pwm_e"; +- function = "pwm_e"; +- bias-disable; +- }; +- }; +- +- pwm_f_x_pins: pwm_f_x { +- mux { +- groups = "pwm_f_x"; +- function = "pwm_f_x"; +- bias-disable; +- }; +- }; +- +- pwm_f_y_pins: pwm_f_y { +- mux { +- groups = "pwm_f_y"; +- function = "pwm_f_y"; +- bias-disable; +- }; +- }; +- +- hdmi_hpd_pins: hdmi_hpd { +- mux { +- groups = "hdmi_hpd"; +- function = "hdmi_hpd"; +- bias-disable; +- }; +- }; +- +- hdmi_i2c_pins: hdmi_i2c { +- mux { +- groups = "hdmi_sda", "hdmi_scl"; +- function = "hdmi_i2c"; +- bias-disable; +- }; +- }; +- +- i2sout_ch23_y_pins: i2sout_ch23_y { +- mux { +- groups = "i2sout_ch23_y"; +- function = "i2s_out"; +- bias-disable; +- }; +- }; +- +- i2sout_ch45_y_pins: i2sout_ch45_y { +- mux { +- groups = "i2sout_ch45_y"; +- function = "i2s_out"; +- bias-disable; +- }; +- }; +- +- i2sout_ch67_y_pins: i2sout_ch67_y { +- mux { +- groups = "i2sout_ch67_y"; +- function = "i2s_out"; +- bias-disable; +- }; +- }; +- +- spdif_out_y_pins: spdif_out_y { +- mux { +- groups = "spdif_out_y"; +- function = "spdif_out"; +- bias-disable; +- }; +- }; +- }; +-}; +- +-&pwrc { +- resets = <&reset RESET_VIU>, +- <&reset RESET_VENC>, +- <&reset RESET_VCBUS>, +- <&reset RESET_BT656>, +- <&reset RESET_DVIN_RESET>, +- <&reset RESET_RDMA>, +- <&reset RESET_VENCI>, +- <&reset RESET_VENCP>, +- <&reset RESET_VDAC>, +- <&reset RESET_VDI6>, +- <&reset RESET_VENCL>, +- <&reset RESET_VID_LOCK>; +- reset-names = "viu", "venc", "vcbus", "bt656", +- "dvin", "rdma", "venci", "vencp", +- "vdac", "vdi6", "vencl", "vid_lock"; +- clocks = <&clkc CLKID_VPU>, +- <&clkc CLKID_VAPB>; +- clock-names = "vpu", "vapb"; +- /* +- * VPU clocking is provided by two identical clock paths +- * VPU_0 and VPU_1 muxed to a single clock by a glitch +- * free mux to safely change frequency while running. +- * Same for VAPB but with a final gate after the glitch free mux. +- */ +- assigned-clocks = <&clkc CLKID_VPU_0_SEL>, +- <&clkc CLKID_VPU_0>, +- <&clkc CLKID_VPU>, /* Glitch free mux */ +- <&clkc CLKID_VAPB_0_SEL>, +- <&clkc CLKID_VAPB_0>, +- <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ +- assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, +- <0>, /* Do Nothing */ +- <&clkc CLKID_VPU_0>, +- <&clkc CLKID_FCLK_DIV4>, +- <0>, /* Do Nothing */ +- <&clkc CLKID_VAPB_0>; +- assigned-clock-rates = <0>, /* Do Nothing */ +- <666666666>, +- <0>, /* Do Nothing */ +- <0>, /* Do Nothing */ +- <250000000>, +- <0>; /* Do Nothing */ +-}; +- +-&saradc { +- compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc"; +- clocks = <&xtal>, +- <&clkc CLKID_SAR_ADC>, +- <&clkc CLKID_SAR_ADC_CLK>, +- <&clkc CLKID_SAR_ADC_SEL>; +- clock-names = "clkin", "core", "adc_clk", "adc_sel"; +-}; +- +-&sd_emmc_a { +- clocks = <&clkc CLKID_SD_EMMC_A>, +- <&clkc CLKID_SD_EMMC_A_CLK0>, +- <&clkc CLKID_FCLK_DIV2>; +- clock-names = "core", "clkin0", "clkin1"; +- resets = <&reset RESET_SD_EMMC_A>; +-}; +- +-&sd_emmc_b { +- clocks = <&clkc CLKID_SD_EMMC_B>, +- <&clkc CLKID_SD_EMMC_B_CLK0>, +- <&clkc CLKID_FCLK_DIV2>; +- clock-names = "core", "clkin0", "clkin1"; +- resets = <&reset RESET_SD_EMMC_B>; +-}; +- +-&sd_emmc_c { +- clocks = <&clkc CLKID_SD_EMMC_C>, +- <&clkc CLKID_SD_EMMC_C_CLK0>, +- <&clkc CLKID_FCLK_DIV2>; +- clock-names = "core", "clkin0", "clkin1"; +- resets = <&reset RESET_SD_EMMC_C>; +-}; +- +-&simplefb_hdmi { +- clocks = <&clkc CLKID_HDMI_PCLK>, +- <&clkc CLKID_CLK81>, +- <&clkc CLKID_GCLK_VENCI_INT0>; +-}; +- +-&spicc { +- clocks = <&clkc CLKID_SPICC>; +- clock-names = "core"; +- resets = <&reset RESET_PERIPHS_SPICC>; +- num-cs = <1>; +-}; +- +-&spifc { +- clocks = <&clkc CLKID_SPI>; +-}; +- +-&uart_A { +- clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&uart_AO { +- clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&uart_AO_B { +- clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&uart_B { +- clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&uart_C { +- clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&vpu { +- compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu"; +- power-domains = <&pwrc PWRC_GXBB_VPU_ID>; +-}; +- +-&vdec { +- compatible = "amlogic,gxbb-vdec", "amlogic,gx-vdec"; +- clocks = <&clkc CLKID_DOS_PARSER>, +- <&clkc CLKID_DOS>, +- <&clkc CLKID_VDEC_1>, +- <&clkc CLKID_VDEC_HEVC>; +- clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc"; +- resets = <&reset RESET_PARSER>; +- reset-names = "esparser"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-mali.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-mali.dtsi +deleted file mode 100644 +index 478e755cc87c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-mali.dtsi ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 BayLibre SAS +- * Author: Neil Armstrong +- */ +- +-#include "meson-gx-mali450.dtsi" +- +-&mali { +- compatible = "amlogic,meson-gxl-mali", "arm,mali-450"; +- +- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; +- clock-names = "bus", "core"; +- +- assigned-clocks = <&clkc CLKID_GP0_PLL>; +- assigned-clock-rates = <744000000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s805x-libretech-ac.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s805x-libretech-ac.dts +deleted file mode 100644 +index 2d769203f671..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s805x-libretech-ac.dts ++++ /dev/null +@@ -1,319 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 BayLibre, SAS. +- * Author: Neil Armstrong +- * Author: Jerome Brunet +- */ +- +-/dts-v1/; +- +-#include +-#include +- +-#include "meson-gxl-s805x.dtsi" +- +-/ { +- compatible = "libretech,aml-s805x-ac", "amlogic,s805x", +- "amlogic,meson-gxl"; +- model = "Libre Computer AML-S805X-AC"; +- +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- spi0 = &spifc; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- cvbs-connector { +- /* +- * The pads are present but no connector is soldered on +- * 2J2, so keep this off by default. +- */ +- status = "disabled"; +- compatible = "composite-video-connector"; +- +- port { +- cvbs_connector_in: endpoint { +- remote-endpoint = <&cvbs_vdac_out>; +- }; +- }; +- }; +- +- dc_5v: regulator-dc_5v { +- compatible = "regulator-fixed"; +- regulator-name = "DC_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x20000000>; +- }; +- +- vcck: regulator-vcck { +- compatible = "regulator-fixed"; +- regulator-name = "VCCK"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&dc_5v>; +- +- /* +- * This is controlled by GPIOAO_9 we reserve this but +- * claiming it as done below reset the board anyway +- * Need to investigate this +- * +- * gpio = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; +- * enable-active-high; +- */ +- regulator-always-on; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&dc_5v>; +- regulator-always-on; +- }; +- +- vddio_ao18: regulator-vddio_ao18 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_3v3>; +- regulator-always-on; +- }; +- +- vddio_boot: regulator-vddio_boot { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_BOOT"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_3v3>; +- regulator-always-on; +- }; +- +- sound { +- compatible = "amlogic,gx-sound-card"; +- model = "LIBRETECH-AC"; +- audio-widgets = "Speaker", "9J5-3 LEFT", +- "Speaker", "9J5-2 RIGHT"; +- audio-routing = "9J5-3 LEFT", "ACODEC LOLN", +- "9J5-2 RIGHT", "ACODEC LORN"; +- assigned-clocks = <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>, +- <&clkc CLKID_MPLL2>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; +- }; +- +- dai-link-1 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; +- dai-format = "i2s"; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&aiu AIU_HDMI CTRL_I2S>; +- }; +- +- codec-1 { +- sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; +- }; +- }; +- +- dai-link-2 { +- sound-dai = <&aiu AIU_HDMI CTRL_OUT>; +- +- codec-0 { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- +- dai-link-3 { +- sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; +- +- codec-0 { +- sound-dai = <&acodec>; +- }; +- }; +- }; +-}; +- +-&acodec { +- AVDD-supply = <&vddio_ao18>; +- status = "okay"; +-}; +- +-&aiu { +- status = "okay"; +-}; +- +-&cec_AO { +- status = "okay"; +- pinctrl-0 = <&ao_cec_pins>; +- pinctrl-names = "default"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cvbs_vdac_port { +- cvbs_vdac_out: endpoint { +- remote-endpoint = <&cvbs_connector_in>; +- }; +-}; +- +-ðmac { +- status = "okay"; +-}; +- +-&internal_phy { +- pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; +- pinctrl-names = "default"; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +- pinctrl-names = "default"; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&gpio_ao { +- gpio-line-names = "UART TX", +- "UART RX", +- "7J1 Header Pin31", +- "", "", "", "", +- "IR In", +- "HDMI CEC", +- "5V VCCK Regulator", +- /* GPIO_TEST_N */ +- ""; +-}; +- +-&gpio { +- gpio-line-names = /* Bank GPIOZ */ +- "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", +- "Eth Link LED", "Eth Activity LED", +- /* Bank GPIOH */ +- "HDMI HPD", "HDMI SDA", "HDMI SCL", +- "", "7J1 Header Pin13", +- "7J1 Header Pin15", +- "7J1 Header Pin7", +- "7J1 Header Pin12", +- "7J1 Header Pin16", +- "7J1 Header Pin18", +- /* Bank BOOT */ +- "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", +- "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", +- "eMMC Clk", "eMMC Reset", "eMMC CMD", +- "SPI NOR MOSI", "SPI NOR MISO", "SPI NOR Clk", +- "", "SPI NOR Chip Select", +- /* Bank CARD */ +- "", "", "", "", "", "", "", +- /* Bank GPIODV */ +- "", "", "", "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", "", "", "", +- "7J1 Header Pin27", "7J1 Header Pin28", "", +- "7J1 Header Pin29", +- "VCCK Regulator", "VDDEE Regulator", +- /* Bank GPIOX */ +- "7J1 Header Pin22", "7J1 Header Pin26", +- "7J1 Header Pin36", "7J1 Header Pin38", +- "7J1 Header Pin40", "7J1 Header Pin37", +- "7J1 Header Pin33", "7J1 Header Pin35", +- "7J1 Header Pin19", "7J1 Header Pin21", +- "7J1 Header Pin24", "7J1 Header Pin23", +- "7J1 Header Pin8", "7J1 Header Pin10", +- "", "", "7J1 Header Pin32", "", "", +- /* Bank GPIOCLK */ +- "", ""; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vddio_boot>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- max-frequency = <200000000>; +- disable-wp; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-&spifc { +- status = "okay"; +- pinctrl-0 = <&nor_pins>; +- pinctrl-names = "default"; +- +- w25q32: spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <3000000>; +- }; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- status = "okay"; +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s805x-p241.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s805x-p241.dts +deleted file mode 100644 +index eb7f5a3fefd4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s805x-p241.dts ++++ /dev/null +@@ -1,222 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 BayLibre, SAS. +- * Author: Neil Armstrong +- * Author: Jerome Brunet +- */ +- +-/dts-v1/; +- +-#include +- +-#include "meson-gxl-s805x.dtsi" +- +-/ { +- compatible = "amlogic,p241", "amlogic,s805x", "amlogic,meson-gxl"; +- model = "Amlogic Meson GXL (S805X) P241 Development Board"; +- +- aliases { +- serial0 = &uart_AO; +- serial1 = &uart_A; +- ethernet0 = ðmac; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- cvbs-connector { +- compatible = "composite-video-connector"; +- +- port { +- cvbs_connector_in: endpoint { +- remote-endpoint = <&cvbs_vdac_out>; +- }; +- }; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x20000000>; +- }; +- +- vddio_boot: regulator-vddio_boot { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_BOOT"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vddao_3v3: regulator-vddao_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vddio_ao18: regulator-vddio_ao18 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- wifi32k: wifi32k { +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; +- clocks = <&wifi32k>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&cec_AO { +- status = "okay"; +- pinctrl-0 = <&ao_cec_pins>; +- pinctrl-names = "default"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cvbs_vdac_port { +- cvbs_vdac_out: endpoint { +- remote-endpoint = <&cvbs_connector_in>; +- }; +-}; +- +-ðmac { +- status = "okay"; +-}; +- +-&internal_phy { +- pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; +- pinctrl-names = "default"; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +- pinctrl-names = "default"; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vddio_ao18>; +-}; +- +-/* Wireless SDIO Module */ +-&sd_emmc_a { +- status = "okay"; +- pinctrl-0 = <&sdio_pins>; +- pinctrl-1 = <&sdio_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- +- non-removable; +- disable-wp; +- +- /* WiFi firmware requires power to be kept while in suspend */ +- keep-power-in-suspend; +- +- mmc-pwrseq = <&sdio_pwrseq>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- max-frequency = <200000000>; +- non-removable; +- disable-wp; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-&pwm_ef { +- status = "okay"; +- pinctrl-0 = <&pwm_e_pins>; +- pinctrl-names = "default"; +- clocks = <&clkc CLKID_FCLK_DIV4>; +- clock-names = "clkin0"; +-}; +- +-/* This is connected to the Bluetooth module: */ +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- status = "okay"; +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s805x.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s805x.dtsi +deleted file mode 100644 +index 29975849822c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s805x.dtsi ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 BayLibre SAS +- * Author: Neil Armstrong +- */ +- +-#include "meson-gxl-s905x.dtsi" +- +-/ { +- compatible = "amlogic,s805x", "amlogic,meson-gxl"; +-}; +- +-/* The S805X Package doesn't seem to handle the 744MHz OPP correctly */ +-&gpu_opp_table { +- opp-744000000 { +- status = "disabled"; +- }; +-}; +- +-&mali { +- /delete-property/ assigned-clocks; +- /delete-property/ assigned-clock-rates; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d-libretech-pc.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d-libretech-pc.dts +deleted file mode 100644 +index 100a1cfeea15..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d-libretech-pc.dts ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019 BayLibre SAS. All rights reserved. +- * Author: Jerome Brunet +- */ +- +-/dts-v1/; +- +-#include "meson-gxl-s905d.dtsi" +-#include "meson-gx-libretech-pc.dtsi" +- +-/ { +- compatible = "libretech,aml-s905d-pc", "amlogic,s905d", +- "amlogic,meson-gxl"; +- model = "Libre Computer AML-S905D-PC"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d-mecool-kii-pro.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d-mecool-kii-pro.dts +deleted file mode 100644 +index c529b6c860a4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d-mecool-kii-pro.dts ++++ /dev/null +@@ -1,86 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-/* +- * Author: Christian Hewitt +- */ +- +-/dts-v1/; +- +-#include "meson-gxl-s905d.dtsi" +-#include "meson-gx-p23x-q20x.dtsi" +-#include +-#include +- +-/ { +- compatible = "videostrong,gxl-kii-pro", "amlogic,s905d", "amlogic,meson-gxl"; +- model = "MeCool KII Pro"; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 0>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1710000>; +- +- button-function { +- label = "Update"; +- linux,code = ; +- press-threshold-microvolt = <10000>; +- }; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- #address-cells = <1>; +- #size-cells = <0>; +- poll-interval = <100>; +- +- button@0 { +- label = "power"; +- linux,code = ; +- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-blue { +- color = ; +- function = LED_FUNCTION_POWER; +- gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- panic-indicator; +- }; +- }; +-}; +- +-ðmac { +- phy-mode = "rmii"; +- phy-handle = <&internal_phy>; +-}; +- +-&ir { +- linux,rc-map-name = "rc-mecool-kii-pro"; +-}; +- +-&sd_emmc_a { +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; +- max-speed = <2000000>; +- clocks = <&wifi32k>; +- clock-names = "lpo"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d-p230.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d-p230.dts +deleted file mode 100644 +index b2ab05c22090..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d-p230.dts ++++ /dev/null +@@ -1,111 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Endless Computers, Inc. +- * Author: Carlo Caione +- */ +- +-/dts-v1/; +- +-#include +- +-#include "meson-gxl-s905d.dtsi" +-#include "meson-gx-p23x-q20x.dtsi" +- +-/ { +- compatible = "amlogic,p230", "amlogic,s905d", "amlogic,meson-gxl"; +- model = "Amlogic Meson GXL (S905D) P230 Development Board"; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 0>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1710000>; +- +- button-function { +- label = "Update"; +- linux,code = ; +- press-threshold-microvolt = <10000>; +- }; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- #address-cells = <1>; +- #size-cells = <0>; +- poll-interval = <100>; +- +- button@0 { +- label = "power"; +- linux,code = ; +- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +-}; +- +-&cec_AO { +- status = "okay"; +- pinctrl-0 = <&ao_cec_pins>; +- pinctrl-names = "default"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-/* P230 has exclusive choice between internal or external PHY */ +-ðmac { +- pinctrl-0 = <ð_pins>; +- pinctrl-names = "default"; +- +- /* Select external PHY by default */ +- phy-handle = <&external_phy>; +- +- amlogic,tx-delay-ns = <2>; +- +- /* External PHY is in RGMII */ +- phy-mode = "rgmii"; +-}; +- +-&external_mdio { +- external_phy: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- max-speed = <1000>; +- +- /* External PHY reset is shared with internal PHY Led signal */ +- reset-assert-us = <10000>; +- reset-deassert-us = <80000>; +- reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; +- +- interrupt-parent = <&gpio_intc>; +- interrupts = <29 IRQ_TYPE_LEVEL_LOW>; +- eee-broken-1000t; +- }; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +- pinctrl-names = "default"; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&sd_emmc_a { +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d-p231.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d-p231.dts +deleted file mode 100644 +index 92c425d0259c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d-p231.dts ++++ /dev/null +@@ -1,28 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Endless Computers, Inc. +- * Author: Carlo Caione +- */ +- +-/dts-v1/; +- +-#include "meson-gxl-s905d.dtsi" +-#include "meson-gx-p23x-q20x.dtsi" +- +-/ { +- compatible = "amlogic,p231", "amlogic,s905d", "amlogic,meson-gxl"; +- model = "Amlogic Meson GXL (S905D) P231 Development Board"; +-}; +- +-/* P231 has only internal PHY port */ +-ðmac { +- phy-mode = "rmii"; +- phy-handle = <&internal_phy>; +-}; +- +-&sd_emmc_a { +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d-phicomm-n1.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d-phicomm-n1.dts +deleted file mode 100644 +index 9ef210f17b4a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d-phicomm-n1.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 He Yangxuan +- */ +- +-/dts-v1/; +- +-#include "meson-gxl-s905d-p230.dts" +- +-/ { +- compatible = "phicomm,n1", "amlogic,s905d", "amlogic,meson-gxl"; +- model = "Phicomm N1"; +- +- cvbs-connector { +- status = "disabled"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- status { +- label = "n1:white:status"; +- gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +-}; +- +-&cvbs_vdac_port { +- status = "disabled"; +-}; +- +-&usb { +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d-sml5442tw.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d-sml5442tw.dts +deleted file mode 100644 +index b331a013572f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d-sml5442tw.dts ++++ /dev/null +@@ -1,84 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) Christian Hewitt +- */ +- +-/dts-v1/; +- +-#include "meson-gxl-s905d.dtsi" +-#include "meson-gx-p23x-q20x.dtsi" +-#include +- +-/ { +- compatible = "smartlabs,sml5442tw", "amlogic,s905d", "amlogic,meson-gxl"; +- model = "SmartLabs SML-5442TW"; +- +- leds { +- compatible = "gpio-leds"; +- +- led-yellow { +- color = ; +- function = LED_FUNCTION_STATUS; +- gpios = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-blue { +- color = ; +- function = LED_FUNCTION_STATUS; +- gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-green { +- color = ; +- function = LED_FUNCTION_STATUS; +- gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- led-red { +- color = ; +- function = LED_FUNCTION_STATUS; +- gpios = <&gpio GPIODV_27 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +-}; +- +-ðmac { +- status = "okay"; +- phy-mode = "rmii"; +- phy-handle = <&internal_phy>; +-}; +- +-&i2c_A { +- status = "okay"; +- pinctrl-0 = <&i2c_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&internal_phy { +- pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; +- pinctrl-names = "default"; +-}; +- +-&ir { +- linux,rc-map-name = "rc-khamsin"; +-}; +- +-/* This is connected to the Bluetooth module: */ +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- +- bluetooth { +- compatible = "qcom,qca9377-bt"; +- enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; +- max-speed = <2000000>; +- clocks = <&wifi32k>; +- clock-names = "lpo"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d.dtsi +deleted file mode 100644 +index 43321919547a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905d.dtsi ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Endless Computers, Inc. +- * Author: Carlo Caione +- */ +- +-#include "meson-gxl.dtsi" +-#include "meson-gxl-mali.dtsi" +- +-/ { +- compatible = "amlogic,s905d", "amlogic,meson-gxl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905w-p281.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905w-p281.dts +deleted file mode 100644 +index ecc9df7ca023..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905w-p281.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Martin Blumenstingl . +- * Based on meson-gxl-s905d-p231.dts: +- * - Copyright (c) 2016 Endless Computers, Inc. +- * Author: Carlo Caione +- */ +- +-/dts-v1/; +- +-#include "meson-gxl-s905x.dtsi" +-#include "meson-gx-p23x-q20x.dtsi" +- +-/ { +- compatible = "amlogic,p281", "amlogic,s905w", "amlogic,meson-gxl"; +- model = "Amlogic Meson GXL (S905W) P281 Development Board"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x40000000>; +- }; +-}; +- +-&usb { +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905w-tx3-mini.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905w-tx3-mini.dts +deleted file mode 100644 +index 6705c2082a78..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905w-tx3-mini.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Martin Blumenstingl . +- * Based on meson-gxl-s905d-p231.dts: +- * - Copyright (c) 2016 Endless Computers, Inc. +- * Author: Carlo Caione +- */ +- +-/dts-v1/; +- +-#include "meson-gxl-s905x.dtsi" +-#include "meson-gx-p23x-q20x.dtsi" +- +-/ { +- compatible = "oranth,tx3-mini", "amlogic,s905w", "amlogic,meson-gxl"; +- model = "Oranth Tanix TX3 Mini"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x40000000>; /* 1 GiB or 2 GiB */ +- }; +-}; +- +-&ir { +- linux,rc-map-name = "rc-tanix-tx3mini"; +-}; +- +-&usb { +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-hwacom-amazetv.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-hwacom-amazetv.dts +deleted file mode 100644 +index c8d74e61dec1..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-hwacom-amazetv.dts ++++ /dev/null +@@ -1,164 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Carlo Caione +- * Copyright (c) 2016 BayLibre, Inc. +- * Author: Neil Armstrong +- */ +- +-/dts-v1/; +- +-#include "meson-gxl-s905x.dtsi" +- +-/ { +- compatible = "hwacom,amazetv", "amlogic,s905x", "amlogic,meson-gxl"; +- model = "Hwacom AmazeTV (S905X)"; +- +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- vddio_card: gpio-regulator { +- compatible = "regulator-gpio"; +- +- regulator-name = "VDDIO_CARD"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- +- /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ +- states = <1800000 0>, +- <3300000 1>; +- }; +- +- vddio_boot: regulator-vddio_boot { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_BOOT"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vddao_3v3: regulator-vddao_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- wifi32k: wifi32k { +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; +- clocks = <&wifi32k>; +- clock-names = "ext_clock"; +- }; +- +- cvbs-connector { +- compatible = "composite-video-connector"; +- +- port { +- cvbs_connector_in: endpoint { +- remote-endpoint = <&cvbs_vdac_out>; +- }; +- }; +- }; +-}; +- +-&cvbs_vdac_port { +- cvbs_vdac_out: endpoint { +- remote-endpoint = <&cvbs_connector_in>; +- }; +-}; +- +-ðmac { +- status = "okay"; +- phy-mode = "rmii"; +- phy-handle = <&internal_phy>; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&pwm_ef { +- status = "okay"; +- pinctrl-0 = <&pwm_e_pins>; +- pinctrl-names = "default"; +- clocks = <&clkc CLKID_FCLK_DIV4>; +- clock-names = "clkin0"; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_pins>; +- pinctrl-1 = <&sdcard_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <100000000>; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_card>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- max-frequency = <100000000>; +- non-removable; +- disable-wp; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts +deleted file mode 100644 +index 6ab1cc125b96..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts ++++ /dev/null +@@ -1,253 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Martin Blumenstingl . +- */ +- +-/dts-v1/; +- +-#include "meson-gxl-s905x-p212.dtsi" +-#include +-#include +- +-/ { +- compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl"; +- model = "Khadas VIM"; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 0>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1710000>; +- +- button-function { +- label = "Function"; +- linux,code = ; +- press-threshold-microvolt = <10000>; +- }; +- }; +- +- aliases { +- serial2 = &uart_AO_B; +- ethernet0 = ðmac; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- poll-interval = <100>; +- +- power-button { +- label = "power"; +- linux,code = ; +- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- led-controller { +- compatible = "pwm-leds"; +- +- led-1 { +- label = "vim:red:power"; +- pwms = <&pwm_AO_ab 1 7812500 0>; +- max-brightness = <255>; +- linux,default-trigger = "default-on"; +- }; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- sound { +- compatible = "amlogic,gx-sound-card"; +- model = "KHADAS-VIM"; +- assigned-clocks = <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>, +- <&clkc CLKID_MPLL2>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; +- }; +- +- dai-link-1 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; +- dai-format = "i2s"; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&aiu AIU_HDMI CTRL_I2S>; +- }; +- }; +- +- dai-link-2 { +- sound-dai = <&aiu AIU_HDMI CTRL_OUT>; +- +- codec-0 { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +-}; +- +-&aiu { +- status = "okay"; +-}; +- +-&cec_AO { +- status = "okay"; +- pinctrl-0 = <&ao_cec_pins>; +- pinctrl-names = "default"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +- pinctrl-names = "default"; +- hdmi-supply = <&hdmi_5v>; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&i2c_A { +- status = "okay"; +- pinctrl-0 = <&i2c_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&i2c_B { +- status = "okay"; +- pinctrl-0 = <&i2c_b_pins>; +- pinctrl-names = "default"; +- +- rtc: rtc@51 { +- status = "okay"; +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "xin32k"; +- }; +-}; +- +-&ir { +- linux,rc-map-name = "rc-khadas"; +-}; +- +-&gpio_ao { +- gpio-line-names = "UART TX", +- "UART RX", +- "Power Key In", +- "J9 Header Pin35", +- "J9 Header Pin16", +- "J9 Header Pin15", +- "J9 Header Pin33", +- "IR In", +- "HDMI CEC", +- "SYS LED", +- /* GPIO_TEST_N */ +- ""; +-}; +- +-&gpio { +- gpio-line-names = /* Bank GPIOZ */ +- "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", +- "Power OFF", +- "VCCK Enable", +- /* Bank GPIOH */ +- "HDMI HPD", "HDMI SDA", "HDMI SCL", +- "HDMI_5V_EN", "SPDIF", +- "J9 Header Pin37", +- "J9 Header Pin30", +- "J9 Header Pin29", +- "J9 Header Pin32", +- "J9 Header Pin31", +- /* Bank BOOT */ +- "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", +- "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", +- "eMMC Clk", "eMMC Reset", "eMMC CMD", +- "", "BOOT_MODE", "", "", "eMMC Data Strobe", +- /* Bank CARD */ +- "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", +- "SDCard D3", "SDCard D2", "SDCard Det", +- /* Bank GPIODV */ +- "", "", "", "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", "", "", "", +- "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", +- "VCCK Regulator", "VDDEE Regulator", +- /* Bank GPIOX */ +- "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2", +- "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD", +- "WIFI Power Enable", "WIFI WAKE HOST", +- "Bluetooth PCM DOUT", "Bluetooth PCM DIN", +- "Bluetooth PCM SYNC", "Bluetooth PCM CLK", +- "Bluetooth UART TX", "Bluetooth UART RX", +- "Bluetooth UART CTS", "Bluetooth UART RTS", +- "WIFI 32K", "Bluetooth Enable", +- "Bluetooth WAKE HOST", +- /* Bank GPIOCLK */ +- "", "J9 Header Pin39"; +-}; +- +-&pwm_AO_ab { +- status = "okay"; +- pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal> , <&xtal>; +- clock-names = "clkin0", "clkin1" ; +-}; +- +-&pwm_ef { +- pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; +-}; +- +-&sd_emmc_a { +- max-frequency = <100000000>; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-&uart_A { +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; +- max-speed = <2000000>; +- clocks = <&wifi32k>; +- clock-names = "lpo"; +- }; +-}; +- +-/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */ +-&uart_AO { +- status = "okay"; +-}; +- +-/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */ +-&uart_AO_B { +- status = "okay"; +- pinctrl-0 = <&uart_ao_b_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- dr_mode = "peripheral"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-libretech-cc-v2.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-libretech-cc-v2.dts +deleted file mode 100644 +index 93d8f8aff70d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-libretech-cc-v2.dts ++++ /dev/null +@@ -1,314 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 BayLibre, SAS. +- * Author: Jerome Brunet +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +- +-#include "meson-gxl-s905x.dtsi" +- +-/ { +- compatible = "libretech,aml-s905x-cc-v2", "amlogic,s905x", +- "amlogic,meson-gxl"; +- model = "Libre Computer AML-S905X-CC V2"; +- +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- spi0 = &spifc; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-blue { +- color = ; +- function = LED_FUNCTION_STATUS; +- gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- panic-indicator; +- }; +- +- led-green { +- color = ; +- function = LED_FUNCTION_DISK_ACTIVITY; +- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "disk-activity"; +- }; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- ao_5v: regulator-ao_5v { +- compatible = "regulator-fixed"; +- regulator-name = "AO_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&dc_in>; +- regulator-always-on; +- }; +- +- dc_in: regulator-dc_in { +- compatible = "regulator-fixed"; +- regulator-name = "DC_IN"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- vcck: regulator-vcck { +- compatible = "regulator-fixed"; +- regulator-name = "VCCK"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&ao_5v>; +- regulator-always-on; +- }; +- +- vcc_card: regulator-vcc_card { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_CARD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vddio_ao3v3>; +- +- gpio = <&gpio GPIOCLK_1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vcc5v: regulator-vcc5v { +- compatible = "regulator-fixed"; +- regulator-name = "VCC5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&ao_5v>; +- +- gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>; +- }; +- +- vddio_ao3v3: regulator-vddio_ao3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&ao_5v>; +- regulator-always-on; +- }; +- +- vddio_card: regulator-vddio-card { +- compatible = "regulator-gpio"; +- regulator-name = "VDDIO_CARD"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; +- gpios-states = <0>; +- +- states = <3300000 0>, +- <1800000 1>; +- +- regulator-settling-time-up-us = <200>; +- regulator-settling-time-down-us = <50000>; +- }; +- +- vddio_ao18: regulator-vddio_ao18 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vddio_ao3v3>; +- regulator-always-on; +- }; +- +- vcc_1v8: regulator-vcc_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC 1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vddio_ao3v3>; +- regulator-always-on; +- }; +- +- sound { +- compatible = "amlogic,gx-sound-card"; +- model = "LIBRETECH-CC-V2"; +- assigned-clocks = <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>, +- <&clkc CLKID_MPLL2>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; +- }; +- +- dai-link-1 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; +- dai-format = "i2s"; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&aiu AIU_HDMI CTRL_I2S>; +- }; +- }; +- +- dai-link-2 { +- sound-dai = <&aiu AIU_HDMI CTRL_OUT>; +- +- codec-0 { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +-}; +- +-&aiu { +- status = "okay"; +-}; +- +-&cec_AO { +- status = "okay"; +- pinctrl-0 = <&ao_cec_pins>; +- pinctrl-names = "default"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-ðmac { +- status = "okay"; +-}; +- +-&internal_phy { +- pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; +- pinctrl-names = "default"; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +- hdmi-supply = <&vcc5v>; +- pinctrl-names = "default"; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vddio_ao18>; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- pinctrl-0 = <&sdcard_pins>; +- pinctrl-1 = <&sdcard_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-ddr50; +- max-frequency = <100000000>; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&vcc_card>; +- vqmmc-supply = <&vddio_card>; +- +- status = "okay"; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- pinctrl-0 = <&emmc_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +- max-frequency = <200000000>; +- disable-wp; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vddio_ao3v3>; +- vqmmc-supply = <&vcc_1v8>; +- +- status = "okay"; +-}; +- +-&spifc { +- status = "okay"; +- pinctrl-0 = <&nor_pins>; +- pinctrl-names = "default"; +- +- nor_4u1: spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <3000000>; +- }; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&usb2_phy0 { +- pinctrl-names = "default"; +- phy-supply = <&vcc5v>; +-}; +- +-&usb2_phy1 { +- phy-supply = <&vcc5v>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts +deleted file mode 100644 +index 82bfabfbd39c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts ++++ /dev/null +@@ -1,356 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 BayLibre, SAS. +- * Author: Neil Armstrong +- * Author: Jerome Brunet +- */ +- +-/dts-v1/; +- +-#include +-#include +- +-#include "meson-gxl-s905x.dtsi" +- +-/ { +- compatible = "libretech,aml-s905x-cc", "amlogic,s905x", +- "amlogic,meson-gxl"; +- model = "Libre Computer AML-S905X-CC"; +- +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- dio2133: analog-amplifier { +- compatible = "simple-audio-amplifier"; +- sound-name-prefix = "AU2"; +- VCC-supply = <&hdmi_5v>; +- enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- cvbs-connector { +- compatible = "composite-video-connector"; +- +- port { +- cvbs_connector_in: endpoint { +- remote-endpoint = <&cvbs_vdac_out>; +- }; +- }; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-system { +- label = "librecomputer:system-status"; +- gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- panic-indicator; +- }; +- +- led-blue { +- label = "librecomputer:blue"; +- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- hdmi_5v: regulator-hdmi-5v { +- compatible = "regulator-fixed"; +- +- regulator-name = "HDMI_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vcc_card: regulator-vcc-card { +- compatible = "regulator-gpio"; +- +- regulator-name = "VCC_CARD"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; +- gpios-states = <0>; +- +- states = <3300000 0>, +- <1800000 1>; +- +- regulator-settling-time-up-us = <200>; +- regulator-settling-time-down-us = <50000>; +- }; +- +- vddio_ao18: regulator-vddio_ao18 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- /* This is provided by LDOs on the eMMC daugther card */ +- vddio_boot: regulator-vddio_boot { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_BOOT"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_3v3>; +- }; +- +- sound { +- compatible = "amlogic,gx-sound-card"; +- model = "LIBRETECH-CC"; +- audio-aux-devs = <&dio2133>; +- audio-widgets = "Line", "Lineout"; +- audio-routing = "AU2 INL", "ACODEC LOLN", +- "AU2 INR", "ACODEC LORN", +- "Lineout", "AU2 OUTL", +- "Lineout", "AU2 OUTR"; +- assigned-clocks = <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>, +- <&clkc CLKID_MPLL2>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; +- }; +- +- dai-link-1 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; +- dai-format = "i2s"; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&aiu AIU_HDMI CTRL_I2S>; +- }; +- +- codec-1 { +- sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; +- }; +- }; +- +- dai-link-2 { +- sound-dai = <&aiu AIU_HDMI CTRL_OUT>; +- +- codec-0 { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- +- dai-link-3 { +- sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; +- +- codec-0 { +- sound-dai = <&acodec>; +- }; +- }; +- }; +-}; +- +-&acodec { +- AVDD-supply = <&vddio_ao18>; +- status = "okay"; +-}; +- +-&aiu { +- status = "okay"; +-}; +- +-&cec_AO { +- status = "okay"; +- pinctrl-0 = <&ao_cec_pins>; +- pinctrl-names = "default"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cvbs_vdac_port { +- cvbs_vdac_out: endpoint { +- remote-endpoint = <&cvbs_connector_in>; +- }; +-}; +- +-ðmac { +- status = "okay"; +-}; +- +-&internal_phy { +- pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; +- pinctrl-names = "default"; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +- pinctrl-names = "default"; +- hdmi-supply = <&hdmi_5v>; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&gpio_ao { +- gpio-line-names = "UART TX", +- "UART RX", +- "Blue LED", +- "SDCard Voltage Switch", +- "7J1 Header Pin5", +- "7J1 Header Pin3", +- "7J1 Header Pin12", +- "IR In", +- "9J3 Switch HDMI CEC/7J1 Header Pin11", +- "7J1 Header Pin13", +- /* GPIO_TEST_N */ +- "7J1 Header Pin15"; +-}; +- +-&gpio { +- gpio-line-names = /* Bank GPIOZ */ +- "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", +- "Eth Link LED", "Eth Activity LED", +- /* Bank GPIOH */ +- "HDMI HPD", "HDMI SDA", "HDMI SCL", +- "HDMI_5V_EN", "9J1 Header Pin2", +- "Analog Audio Mute", +- "2J3 Header Pin6", +- "2J3 Header Pin5", +- "2J3 Header Pin4", +- "2J3 Header Pin3", +- /* Bank BOOT */ +- "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", +- "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", +- "eMMC Clk", "eMMC Reset", "eMMC CMD", +- "ALT BOOT MODE", "", "", "", "eMMC Data Strobe", +- /* Bank CARD */ +- "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", +- "SDCard D3", "SDCard D2", "SDCard Det", +- /* Bank GPIODV */ +- "", "", "", "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", "", "", "", +- "Green LED", "VCCK Enable", +- "7J1 Header Pin27", "7J1 Header Pin28", +- "VCCK Regulator", "VDDEE Regulator", +- /* Bank GPIOX */ +- "7J1 Header Pin22", "7J1 Header Pin26", +- "7J1 Header Pin36", "7J1 Header Pin38", +- "7J1 Header Pin40", "7J1 Header Pin37", +- "7J1 Header Pin33", "7J1 Header Pin35", +- "7J1 Header Pin19", "7J1 Header Pin21", +- "7J1 Header Pin24", "7J1 Header Pin23", +- "7J1 Header Pin8", "7J1 Header Pin10", +- "7J1 Header Pin16", "7J1 Header Pin18", +- "7J1 Header Pin32", "7J1 Header Pin29", +- "7J1 Header Pin31", +- /* Bank GPIOCLK */ +- "7J1 Header Pin7", ""; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vddio_ao18>; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_pins>; +- pinctrl-1 = <&sdcard_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&vcc_card>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- max-frequency = <200000000>; +- disable-wp; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&usb2_phy0 { +- /* +- * even though the schematics don't show it: +- * HDMI_5V is also used as supply for the USB VBUS. +- */ +- phy-supply = <&hdmi_5v>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts +deleted file mode 100644 +index f1acca5c4434..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts ++++ /dev/null +@@ -1,224 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Andreas Färber +- * Copyright (c) 2016 BayLibre, Inc. +- * Author: Neil Armstrong +- */ +- +-/dts-v1/; +- +-#include "meson-gxl-s905x.dtsi" +- +-/ { +- compatible = "nexbox,a95x", "amlogic,s905x", "amlogic,meson-gxl"; +- model = "NEXBOX A95X (S905X)"; +- +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- vddio_card: gpio-regulator { +- compatible = "regulator-gpio"; +- +- regulator-name = "VDDIO_CARD"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- +- /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ +- states = <1800000 0>, +- <3300000 1>; +- }; +- +- vddio_boot: regulator-vddio_boot { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_BOOT"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vddao_3v3: regulator-vddao_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- wifi32k: wifi32k { +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; +- clocks = <&wifi32k>; +- clock-names = "ext_clock"; +- }; +- +- cvbs-connector { +- compatible = "composite-video-connector"; +- +- port { +- cvbs_connector_in: endpoint { +- remote-endpoint = <&cvbs_vdac_out>; +- }; +- }; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +-}; +- +-&cec_AO { +- status = "okay"; +- pinctrl-0 = <&ao_cec_pins>; +- pinctrl-names = "default"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cvbs_vdac_port { +- cvbs_vdac_out: endpoint { +- remote-endpoint = <&cvbs_connector_in>; +- }; +-}; +- +-ðmac { +- status = "okay"; +- phy-mode = "rmii"; +- phy-handle = <&internal_phy>; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +- pinctrl-names = "default"; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&pwm_ef { +- status = "okay"; +- pinctrl-0 = <&pwm_e_pins>; +- pinctrl-names = "default"; +- clocks = <&clkc CLKID_FCLK_DIV4>; +- clock-names = "clkin0"; +-}; +- +-/* Wireless SDIO Module */ +-&sd_emmc_a { +- status = "okay"; +- pinctrl-0 = <&sdio_pins>; +- pinctrl-1 = <&sdio_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <100000000>; +- +- non-removable; +- disable-wp; +- +- /* WiFi firmware requires power to be kept while in suspend */ +- keep-power-in-suspend; +- +- mmc-pwrseq = <&sdio_pwrseq>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_pins>; +- pinctrl-1 = <&sdcard_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_card>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- max-frequency = <200000000>; +- non-removable; +- disable-wp; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- status = "okay"; +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-p212.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-p212.dts +deleted file mode 100644 +index 2602940c2077..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-p212.dts ++++ /dev/null +@@ -1,66 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Endless Computers, Inc. +- * Author: Carlo Caione +- */ +- +-/dts-v1/; +- +-#include "meson-gxl-s905x-p212.dtsi" +- +-/ { +- compatible = "amlogic,p212", "amlogic,s905x", "amlogic,meson-gxl"; +- model = "Amlogic Meson GXL (S905X) P212 Development Board"; +- +- cvbs-connector { +- compatible = "composite-video-connector"; +- +- port { +- cvbs_connector_in: endpoint { +- remote-endpoint = <&cvbs_vdac_out>; +- }; +- }; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +-}; +- +-&cec_AO { +- status = "okay"; +- pinctrl-0 = <&ao_cec_pins>; +- pinctrl-names = "default"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cvbs_vdac_port { +- cvbs_vdac_out: endpoint { +- remote-endpoint = <&cvbs_connector_in>; +- }; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +- pinctrl-names = "default"; +- hdmi-supply = <&hdmi_5v>; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-/* This UART is brought out to the DB9 connector */ +-&uart_AO { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-p212.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-p212.dtsi +deleted file mode 100644 +index 05cb2f5e5c36..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x-p212.dtsi ++++ /dev/null +@@ -1,208 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Martin Blumenstingl . +- * Based on meson-gx-p23x-q20x.dtsi: +- * - Copyright (c) 2016 Endless Computers, Inc. +- * Author: Carlo Caione +- * - Copyright (c) 2016 BayLibre, SAS. +- * Author: Neil Armstrong +- */ +- +-/* Common DTSI for devices which are based on the P212 reference board. */ +- +-#include "meson-gxl-s905x.dtsi" +- +-/ { +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- hdmi_5v: regulator-hdmi-5v { +- compatible = "regulator-fixed"; +- +- regulator-name = "HDMI_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- vddio_boot: regulator-vddio_boot { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_BOOT"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vddao_3v3: regulator-vddao_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vddio_ao18: regulator-vddio_ao18 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- wifi32k: wifi32k { +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; +- clocks = <&wifi32k>; +- clock-names = "ext_clock"; +- }; +-}; +- +-ðmac { +- status = "okay"; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vddio_ao18>; +-}; +- +-/* Wireless SDIO Module */ +-&sd_emmc_a { +- status = "okay"; +- pinctrl-0 = <&sdio_pins>; +- pinctrl-1 = <&sdio_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- +- non-removable; +- disable-wp; +- +- /* WiFi firmware requires power to be kept while in suspend */ +- keep-power-in-suspend; +- +- mmc-pwrseq = <&sdio_pwrseq>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_pins>; +- pinctrl-1 = <&sdcard_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- max-frequency = <200000000>; +- non-removable; +- disable-wp; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-&pwm_ef { +- status = "okay"; +- pinctrl-0 = <&pwm_e_pins>; +- pinctrl-names = "default"; +- clocks = <&clkc CLKID_FCLK_DIV4>; +- clock-names = "clkin0"; +-}; +- +-/* This is connected to the Bluetooth module: */ +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; +- max-speed = <2000000>; +- clocks = <&wifi32k>; +- clock-names = "lpo"; +- }; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&usb2_phy0 { +- /* +- * HDMI_5V is also used as supply for the USB VBUS. +- */ +- phy-supply = <&hdmi_5v>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x.dtsi +deleted file mode 100644 +index 40c19f69e9dc..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl-s905x.dtsi ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Endless Computers, Inc. +- * Author: Carlo Caione +- */ +- +-#include "meson-gxl.dtsi" +-#include "meson-gxl-mali.dtsi" +- +-/ { +- compatible = "amlogic,s905x", "amlogic,meson-gxl"; +-}; +- +-/* S905X only has access to its internal PHY */ +-ðmac { +- phy-mode = "rmii"; +- phy-handle = <&internal_phy>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl.dtsi +deleted file mode 100644 +index c3ac531c4f84..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxl.dtsi ++++ /dev/null +@@ -1,925 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Endless Computers, Inc. +- * Author: Carlo Caione +- */ +- +-#include "meson-gx.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "amlogic,meson-gxl"; +- +- soc { +- usb: usb@d0078080 { +- compatible = "amlogic,meson-gxl-usb-ctrl"; +- reg = <0x0 0xd0078080 0x0 0x20>; +- interrupts = ; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; +- clock-names = "usb_ctrl", "ddr"; +- resets = <&reset RESET_USB_OTG>; +- +- dr_mode = "otg"; +- +- phys = <&usb2_phy0>, <&usb2_phy1>; +- phy-names = "usb2-phy0", "usb2-phy1"; +- +- dwc2: usb@c9100000 { +- compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; +- reg = <0x0 0xc9100000 0x0 0x40000>; +- interrupts = ; +- clocks = <&clkc CLKID_USB1>; +- clock-names = "otg"; +- phys = <&usb2_phy1>; +- dr_mode = "peripheral"; +- g-rx-fifo-size = <192>; +- g-np-tx-fifo-size = <128>; +- g-tx-fifo-size = <128 128 16 16 16>; +- }; +- +- dwc3: usb@c9000000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0xc9000000 0x0 0x100000>; +- interrupts = ; +- dr_mode = "host"; +- maximum-speed = "high-speed"; +- snps,dis_u2_susphy_quirk; +- }; +- }; +- +- acodec: audio-controller@c8832000 { +- compatible = "amlogic,t9015"; +- reg = <0x0 0xc8832000 0x0 0x14>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "ACODEC"; +- clocks = <&clkc CLKID_ACODEC>; +- clock-names = "pclk"; +- resets = <&reset RESET_ACODEC>; +- status = "disabled"; +- }; +- +- crypto: crypto@c883e000 { +- compatible = "amlogic,gxl-crypto"; +- reg = <0x0 0xc883e000 0x0 0x36>; +- interrupts = , +- ; +- clocks = <&clkc CLKID_BLKMV>; +- clock-names = "blkmv"; +- status = "okay"; +- }; +- }; +-}; +- +-&aiu { +- compatible = "amlogic,aiu-gxl", "amlogic,aiu"; +- clocks = <&clkc CLKID_AIU_GLUE>, +- <&clkc CLKID_I2S_OUT>, +- <&clkc CLKID_AOCLK_GATE>, +- <&clkc CLKID_CTS_AMCLK>, +- <&clkc CLKID_MIXER_IFACE>, +- <&clkc CLKID_IEC958>, +- <&clkc CLKID_IEC958_GATE>, +- <&clkc CLKID_CTS_MCLK_I958>, +- <&clkc CLKID_CTS_I958>; +- clock-names = "pclk", +- "i2s_pclk", +- "i2s_aoclk", +- "i2s_mclk", +- "i2s_mixer", +- "spdif_pclk", +- "spdif_aoclk", +- "spdif_mclk", +- "spdif_mclk_sel"; +- resets = <&reset RESET_AIU>; +-}; +- +-&apb { +- usb2_phy0: phy@78000 { +- compatible = "amlogic,meson-gxl-usb2-phy"; +- #phy-cells = <0>; +- reg = <0x0 0x78000 0x0 0x20>; +- clocks = <&clkc CLKID_USB>; +- clock-names = "phy"; +- resets = <&reset RESET_USB_OTG>; +- reset-names = "phy"; +- status = "okay"; +- }; +- +- usb2_phy1: phy@78020 { +- compatible = "amlogic,meson-gxl-usb2-phy"; +- #phy-cells = <0>; +- reg = <0x0 0x78020 0x0 0x20>; +- clocks = <&clkc CLKID_USB>; +- clock-names = "phy"; +- resets = <&reset RESET_USB_OTG>; +- reset-names = "phy"; +- status = "okay"; +- }; +-}; +- +-&efuse { +- clocks = <&clkc CLKID_EFUSE>; +-}; +- +-ðmac { +- clocks = <&clkc CLKID_ETH>, +- <&clkc CLKID_FCLK_DIV2>, +- <&clkc CLKID_MPLL2>, +- <&clkc CLKID_FCLK_DIV2>; +- clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; +- +- mdio0: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- }; +-}; +- +-&aobus { +- pinctrl_aobus: pinctrl@14 { +- compatible = "amlogic,meson-gxl-aobus-pinctrl"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gpio_ao: bank@14 { +- reg = <0x0 0x00014 0x0 0x8>, +- <0x0 0x0002c 0x0 0x4>, +- <0x0 0x00024 0x0 0x8>; +- reg-names = "mux", "pull", "gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl_aobus 0 0 14>; +- }; +- +- uart_ao_a_pins: uart_ao_a { +- mux { +- groups = "uart_tx_ao_a", "uart_rx_ao_a"; +- function = "uart_ao"; +- bias-disable; +- }; +- }; +- +- uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { +- mux { +- groups = "uart_cts_ao_a", +- "uart_rts_ao_a"; +- function = "uart_ao"; +- bias-disable; +- }; +- }; +- +- uart_ao_b_pins: uart_ao_b { +- mux { +- groups = "uart_tx_ao_b", "uart_rx_ao_b"; +- function = "uart_ao_b"; +- bias-disable; +- }; +- }; +- +- uart_ao_b_0_1_pins: uart_ao_b_0_1 { +- mux { +- groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1"; +- function = "uart_ao_b"; +- bias-disable; +- }; +- }; +- +- uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { +- mux { +- groups = "uart_cts_ao_b", +- "uart_rts_ao_b"; +- function = "uart_ao_b"; +- bias-disable; +- }; +- }; +- +- remote_input_ao_pins: remote_input_ao { +- mux { +- groups = "remote_input_ao"; +- function = "remote_input_ao"; +- bias-disable; +- }; +- }; +- +- i2c_ao_pins: i2c_ao { +- mux { +- groups = "i2c_sck_ao", +- "i2c_sda_ao"; +- function = "i2c_ao"; +- bias-disable; +- }; +- }; +- +- pwm_ao_a_3_pins: pwm_ao_a_3 { +- mux { +- groups = "pwm_ao_a_3"; +- function = "pwm_ao_a"; +- bias-disable; +- }; +- }; +- +- pwm_ao_a_8_pins: pwm_ao_a_8 { +- mux { +- groups = "pwm_ao_a_8"; +- function = "pwm_ao_a"; +- bias-disable; +- }; +- }; +- +- pwm_ao_b_pins: pwm_ao_b { +- mux { +- groups = "pwm_ao_b"; +- function = "pwm_ao_b"; +- bias-disable; +- }; +- }; +- +- pwm_ao_b_6_pins: pwm_ao_b_6 { +- mux { +- groups = "pwm_ao_b_6"; +- function = "pwm_ao_b"; +- bias-disable; +- }; +- }; +- +- i2s_out_ch23_ao_pins: i2s_out_ch23_ao { +- mux { +- groups = "i2s_out_ch23_ao"; +- function = "i2s_out_ao"; +- bias-disable; +- }; +- }; +- +- i2s_out_ch45_ao_pins: i2s_out_ch45_ao { +- mux { +- groups = "i2s_out_ch45_ao"; +- function = "i2s_out_ao"; +- bias-disable; +- }; +- }; +- +- spdif_out_ao_6_pins: spdif_out_ao_6 { +- mux { +- groups = "spdif_out_ao_6"; +- function = "spdif_out_ao"; +- bias-disable; +- }; +- }; +- +- spdif_out_ao_9_pins: spdif_out_ao_9 { +- mux { +- groups = "spdif_out_ao_9"; +- function = "spdif_out_ao"; +- bias-disable; +- }; +- }; +- +- ao_cec_pins: ao_cec { +- mux { +- groups = "ao_cec"; +- function = "cec_ao"; +- bias-disable; +- }; +- }; +- +- ee_cec_pins: ee_cec { +- mux { +- groups = "ee_cec"; +- function = "cec_ao"; +- bias-disable; +- }; +- }; +- }; +-}; +- +-&cec_AO { +- clocks = <&clkc_AO CLKID_AO_CEC_32K>; +- clock-names = "core"; +-}; +- +-&clkc_AO { +- compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc"; +- clocks = <&xtal>, <&clkc CLKID_CLK81>; +- clock-names = "xtal", "mpeg-clk"; +-}; +- +-&gpio_intc { +- compatible = "amlogic,meson-gpio-intc", +- "amlogic,meson-gxl-gpio-intc"; +- status = "okay"; +-}; +- +-&hdmi_tx { +- compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; +- resets = <&reset RESET_HDMITX_CAPB3>, +- <&reset RESET_HDMI_SYSTEM_RESET>, +- <&reset RESET_HDMI_TX>; +- reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; +- clocks = <&clkc CLKID_HDMI_PCLK>, +- <&clkc CLKID_CLK81>, +- <&clkc CLKID_GCLK_VENCI_INT0>; +- clock-names = "isfr", "iahb", "venci"; +-}; +- +-&sysctrl { +- clkc: clock-controller { +- compatible = "amlogic,gxl-clkc"; +- #clock-cells = <1>; +- clocks = <&xtal>; +- clock-names = "xtal"; +- }; +-}; +- +-&hwrng { +- clocks = <&clkc CLKID_RNG0>; +- clock-names = "core"; +-}; +- +-&i2c_A { +- clocks = <&clkc CLKID_I2C>; +-}; +- +-&i2c_AO { +- clocks = <&clkc CLKID_AO_I2C>; +-}; +- +-&i2c_B { +- clocks = <&clkc CLKID_I2C>; +-}; +- +-&i2c_C { +- clocks = <&clkc CLKID_I2C>; +-}; +- +-&periphs { +- pinctrl_periphs: pinctrl@4b0 { +- compatible = "amlogic,meson-gxl-periphs-pinctrl"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gpio: bank@4b0 { +- reg = <0x0 0x004b0 0x0 0x28>, +- <0x0 0x004e8 0x0 0x14>, +- <0x0 0x00520 0x0 0x14>, +- <0x0 0x00430 0x0 0x40>; +- reg-names = "mux", "pull", "pull-enable", "gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl_periphs 0 0 100>; +- }; +- +- emmc_pins: emmc { +- mux-0 { +- groups = "emmc_nand_d07", +- "emmc_cmd"; +- function = "emmc"; +- bias-pull-up; +- }; +- +- mux-1 { +- groups = "emmc_clk"; +- function = "emmc"; +- bias-disable; +- }; +- }; +- +- emmc_ds_pins: emmc-ds { +- mux { +- groups = "emmc_ds"; +- function = "emmc"; +- bias-pull-down; +- }; +- }; +- +- emmc_clk_gate_pins: emmc_clk_gate { +- mux { +- groups = "BOOT_8"; +- function = "gpio_periphs"; +- bias-pull-down; +- }; +- }; +- +- nor_pins: nor { +- mux { +- groups = "nor_d", +- "nor_q", +- "nor_c", +- "nor_cs"; +- function = "nor"; +- bias-disable; +- }; +- }; +- +- spi_pins: spi-pins { +- mux { +- groups = "spi_miso", +- "spi_mosi", +- "spi_sclk"; +- function = "spi"; +- bias-disable; +- }; +- }; +- +- spi_ss0_pins: spi-ss0 { +- mux { +- groups = "spi_ss0"; +- function = "spi"; +- bias-disable; +- }; +- }; +- +- sdcard_pins: sdcard { +- mux-0 { +- groups = "sdcard_d0", +- "sdcard_d1", +- "sdcard_d2", +- "sdcard_d3", +- "sdcard_cmd"; +- function = "sdcard"; +- bias-pull-up; +- }; +- +- mux-1 { +- groups = "sdcard_clk"; +- function = "sdcard"; +- bias-disable; +- }; +- }; +- +- sdcard_clk_gate_pins: sdcard_clk_gate { +- mux { +- groups = "CARD_2"; +- function = "gpio_periphs"; +- bias-pull-down; +- }; +- }; +- +- sdio_pins: sdio { +- mux-0 { +- groups = "sdio_d0", +- "sdio_d1", +- "sdio_d2", +- "sdio_d3", +- "sdio_cmd"; +- function = "sdio"; +- bias-pull-up; +- }; +- +- mux-1 { +- groups = "sdio_clk"; +- function = "sdio"; +- bias-disable; +- }; +- }; +- +- sdio_clk_gate_pins: sdio_clk_gate { +- mux { +- groups = "GPIOX_4"; +- function = "gpio_periphs"; +- bias-pull-down; +- }; +- }; +- +- sdio_irq_pins: sdio_irq { +- mux { +- groups = "sdio_irq"; +- function = "sdio"; +- bias-disable; +- }; +- }; +- +- uart_a_pins: uart_a { +- mux { +- groups = "uart_tx_a", +- "uart_rx_a"; +- function = "uart_a"; +- bias-disable; +- }; +- }; +- +- uart_a_cts_rts_pins: uart_a_cts_rts { +- mux { +- groups = "uart_cts_a", +- "uart_rts_a"; +- function = "uart_a"; +- bias-disable; +- }; +- }; +- +- uart_b_pins: uart_b { +- mux { +- groups = "uart_tx_b", +- "uart_rx_b"; +- function = "uart_b"; +- bias-disable; +- }; +- }; +- +- uart_b_cts_rts_pins: uart_b_cts_rts { +- mux { +- groups = "uart_cts_b", +- "uart_rts_b"; +- function = "uart_b"; +- bias-disable; +- }; +- }; +- +- uart_c_pins: uart_c { +- mux { +- groups = "uart_tx_c", +- "uart_rx_c"; +- function = "uart_c"; +- bias-disable; +- }; +- }; +- +- uart_c_cts_rts_pins: uart_c_cts_rts { +- mux { +- groups = "uart_cts_c", +- "uart_rts_c"; +- function = "uart_c"; +- bias-disable; +- }; +- }; +- +- i2c_a_pins: i2c_a { +- mux { +- groups = "i2c_sck_a", +- "i2c_sda_a"; +- function = "i2c_a"; +- bias-disable; +- }; +- }; +- +- i2c_b_pins: i2c_b { +- mux { +- groups = "i2c_sck_b", +- "i2c_sda_b"; +- function = "i2c_b"; +- bias-disable; +- }; +- }; +- +- i2c_c_pins: i2c_c { +- mux { +- groups = "i2c_sck_c", +- "i2c_sda_c"; +- function = "i2c_c"; +- bias-disable; +- }; +- }; +- +- i2c_c_dv18_pins: i2c_c_dv18 { +- mux { +- groups = "i2c_sck_c_dv19", +- "i2c_sda_c_dv18"; +- function = "i2c_c"; +- bias-disable; +- }; +- }; +- +- eth_pins: eth_c { +- mux { +- groups = "eth_mdio", +- "eth_mdc", +- "eth_clk_rx_clk", +- "eth_rx_dv", +- "eth_rxd0", +- "eth_rxd1", +- "eth_rxd2", +- "eth_rxd3", +- "eth_rgmii_tx_clk", +- "eth_tx_en", +- "eth_txd0", +- "eth_txd1", +- "eth_txd2", +- "eth_txd3"; +- function = "eth"; +- bias-disable; +- }; +- }; +- +- eth_link_led_pins: eth_link_led { +- mux { +- groups = "eth_link_led"; +- function = "eth_led"; +- bias-disable; +- }; +- }; +- +- eth_act_led_pins: eth_act_led { +- mux { +- groups = "eth_act_led"; +- function = "eth_led"; +- }; +- }; +- +- pwm_a_pins: pwm_a { +- mux { +- groups = "pwm_a"; +- function = "pwm_a"; +- bias-disable; +- }; +- }; +- +- pwm_b_pins: pwm_b { +- mux { +- groups = "pwm_b"; +- function = "pwm_b"; +- bias-disable; +- }; +- }; +- +- pwm_c_pins: pwm_c { +- mux { +- groups = "pwm_c"; +- function = "pwm_c"; +- bias-disable; +- }; +- }; +- +- pwm_d_pins: pwm_d { +- mux { +- groups = "pwm_d"; +- function = "pwm_d"; +- bias-disable; +- }; +- }; +- +- pwm_e_pins: pwm_e { +- mux { +- groups = "pwm_e"; +- function = "pwm_e"; +- bias-disable; +- }; +- }; +- +- pwm_f_clk_pins: pwm_f_clk { +- mux { +- groups = "pwm_f_clk"; +- function = "pwm_f"; +- bias-disable; +- }; +- }; +- +- pwm_f_x_pins: pwm_f_x { +- mux { +- groups = "pwm_f_x"; +- function = "pwm_f"; +- bias-disable; +- }; +- }; +- +- hdmi_hpd_pins: hdmi_hpd { +- mux { +- groups = "hdmi_hpd"; +- function = "hdmi_hpd"; +- bias-disable; +- }; +- }; +- +- hdmi_i2c_pins: hdmi_i2c { +- mux { +- groups = "hdmi_sda", "hdmi_scl"; +- function = "hdmi_i2c"; +- bias-disable; +- }; +- }; +- +- i2s_am_clk_pins: i2s_am_clk { +- mux { +- groups = "i2s_am_clk"; +- function = "i2s_out"; +- bias-disable; +- }; +- }; +- +- i2s_out_ao_clk_pins: i2s_out_ao_clk { +- mux { +- groups = "i2s_out_ao_clk"; +- function = "i2s_out"; +- bias-disable; +- }; +- }; +- +- i2s_out_lr_clk_pins: i2s_out_lr_clk { +- mux { +- groups = "i2s_out_lr_clk"; +- function = "i2s_out"; +- bias-disable; +- }; +- }; +- +- i2s_out_ch01_pins: i2s_out_ch01 { +- mux { +- groups = "i2s_out_ch01"; +- function = "i2s_out"; +- bias-disable; +- }; +- }; +- i2sout_ch23_z_pins: i2sout_ch23_z { +- mux { +- groups = "i2sout_ch23_z"; +- function = "i2s_out"; +- bias-disable; +- }; +- }; +- +- i2sout_ch45_z_pins: i2sout_ch45_z { +- mux { +- groups = "i2sout_ch45_z"; +- function = "i2s_out"; +- bias-disable; +- }; +- }; +- +- i2sout_ch67_z_pins: i2sout_ch67_z { +- mux { +- groups = "i2sout_ch67_z"; +- function = "i2s_out"; +- bias-disable; +- }; +- }; +- +- spdif_out_h_pins: spdif_out_ao_h { +- mux { +- groups = "spdif_out_h"; +- function = "spdif_out"; +- bias-disable; +- }; +- }; +- }; +- +- eth-phy-mux { +- compatible = "mdio-mux-mmioreg", "mdio-mux"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x55c 0x0 0x4>; +- mux-mask = <0xffffffff>; +- mdio-parent-bus = <&mdio0>; +- +- internal_mdio: mdio@e40908ff { +- reg = <0xe40908ff>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- internal_phy: ethernet-phy@8 { +- compatible = "ethernet-phy-id0181.4400"; +- interrupts = ; +- reg = <8>; +- max-speed = <100>; +- }; +- }; +- +- external_mdio: mdio@2009087f { +- reg = <0x2009087f>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +-}; +- +-&pwrc { +- resets = <&reset RESET_VIU>, +- <&reset RESET_VENC>, +- <&reset RESET_VCBUS>, +- <&reset RESET_BT656>, +- <&reset RESET_DVIN_RESET>, +- <&reset RESET_RDMA>, +- <&reset RESET_VENCI>, +- <&reset RESET_VENCP>, +- <&reset RESET_VDAC>, +- <&reset RESET_VDI6>, +- <&reset RESET_VENCL>, +- <&reset RESET_VID_LOCK>; +- reset-names = "viu", "venc", "vcbus", "bt656", +- "dvin", "rdma", "venci", "vencp", +- "vdac", "vdi6", "vencl", "vid_lock"; +- clocks = <&clkc CLKID_VPU>, +- <&clkc CLKID_VAPB>; +- clock-names = "vpu", "vapb"; +- /* +- * VPU clocking is provided by two identical clock paths +- * VPU_0 and VPU_1 muxed to a single clock by a glitch +- * free mux to safely change frequency while running. +- * Same for VAPB but with a final gate after the glitch free mux. +- */ +- assigned-clocks = <&clkc CLKID_VPU_0_SEL>, +- <&clkc CLKID_VPU_0>, +- <&clkc CLKID_VPU>, /* Glitch free mux */ +- <&clkc CLKID_VAPB_0_SEL>, +- <&clkc CLKID_VAPB_0>, +- <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ +- assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, +- <0>, /* Do Nothing */ +- <&clkc CLKID_VPU_0>, +- <&clkc CLKID_FCLK_DIV4>, +- <0>, /* Do Nothing */ +- <&clkc CLKID_VAPB_0>; +- assigned-clock-rates = <0>, /* Do Nothing */ +- <666666666>, +- <0>, /* Do Nothing */ +- <0>, /* Do Nothing */ +- <250000000>, +- <0>; /* Do Nothing */ +-}; +- +-&saradc { +- compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc"; +- clocks = <&xtal>, +- <&clkc CLKID_SAR_ADC>, +- <&clkc CLKID_SAR_ADC_CLK>, +- <&clkc CLKID_SAR_ADC_SEL>; +- clock-names = "clkin", "core", "adc_clk", "adc_sel"; +-}; +- +-&sd_emmc_a { +- clocks = <&clkc CLKID_SD_EMMC_A>, +- <&clkc CLKID_SD_EMMC_A_CLK0>, +- <&clkc CLKID_FCLK_DIV2>; +- clock-names = "core", "clkin0", "clkin1"; +- resets = <&reset RESET_SD_EMMC_A>; +-}; +- +-&sd_emmc_b { +- clocks = <&clkc CLKID_SD_EMMC_B>, +- <&clkc CLKID_SD_EMMC_B_CLK0>, +- <&clkc CLKID_FCLK_DIV2>; +- clock-names = "core", "clkin0", "clkin1"; +- resets = <&reset RESET_SD_EMMC_B>; +-}; +- +-&sd_emmc_c { +- clocks = <&clkc CLKID_SD_EMMC_C>, +- <&clkc CLKID_SD_EMMC_C_CLK0>, +- <&clkc CLKID_FCLK_DIV2>; +- clock-names = "core", "clkin0", "clkin1"; +- resets = <&reset RESET_SD_EMMC_C>; +-}; +- +-&simplefb_hdmi { +- clocks = <&clkc CLKID_HDMI_PCLK>, +- <&clkc CLKID_CLK81>, +- <&clkc CLKID_GCLK_VENCI_INT0>; +-}; +- +-&spicc { +- clocks = <&clkc CLKID_SPICC>; +- clock-names = "core"; +- resets = <&reset RESET_PERIPHS_SPICC>; +- num-cs = <1>; +-}; +- +-&spifc { +- clocks = <&clkc CLKID_SPI>; +-}; +- +-&uart_A { +- clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&uart_AO { +- clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&uart_AO_B { +- clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&uart_B { +- clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&uart_C { +- clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; +- clock-names = "xtal", "pclk", "baud"; +-}; +- +-&vpu { +- compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu"; +- power-domains = <&pwrc PWRC_GXBB_VPU_ID>; +-}; +- +-&vdec { +- compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec"; +- clocks = <&clkc CLKID_DOS_PARSER>, +- <&clkc CLKID_DOS>, +- <&clkc CLKID_VDEC_1>, +- <&clkc CLKID_VDEC_HEVC>; +- clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc"; +- resets = <&reset RESET_PARSER>; +- reset-names = "esparser"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-khadas-vim2.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-khadas-vim2.dts +deleted file mode 100644 +index 86bdc0baf032..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-khadas-vim2.dts ++++ /dev/null +@@ -1,424 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Martin Blumenstingl . +- * Copyright (c) 2017 BayLibre, SAS +- * Author: Neil Armstrong +- */ +- +-/dts-v1/; +- +-#include "meson-gxm.dtsi" +-#include +-#include +- +-/ { +- compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm"; +- model = "Khadas VIM2"; +- +- aliases { +- serial0 = &uart_AO; +- serial2 = &uart_AO_B; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 0>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1710000>; +- +- button-function { +- label = "Function"; +- linux,code = ; +- press-threshold-microvolt = <10000>; +- }; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- gpio_fan: gpio-fan { +- compatible = "gpio-fan"; +- gpios = <&gpio GPIODV_14 GPIO_ACTIVE_HIGH +- &gpio GPIODV_15 GPIO_ACTIVE_HIGH>; +- /* Dummy RPM values since fan is optional */ +- gpio-fan,speed-map = <0 0 +- 1 1 +- 2 2 +- 3 3>; +- #cooling-cells = <2>; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- poll-interval = <100>; +- +- power-button { +- label = "power"; +- linux,code = ; +- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- led-controller { +- compatible = "pwm-leds"; +- +- led-1 { +- label = "vim:red:power"; +- pwms = <&pwm_AO_ab 1 7812500 0>; +- max-brightness = <255>; +- linux,default-trigger = "default-on"; +- }; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; +- clocks = <&wifi32k>; +- clock-names = "ext_clock"; +- }; +- +- hdmi_5v: regulator-hdmi-5v { +- compatible = "regulator-fixed"; +- +- regulator-name = "HDMI_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vddio_ao18: regulator-vddio_ao18 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vddio_boot: regulator-vddio_boot { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_BOOT"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vddao_3v3: regulator-vddao_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- wifi32k: wifi32k { +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ +- }; +- +- sound { +- compatible = "amlogic,gx-sound-card"; +- model = "KHADAS-VIM2"; +- assigned-clocks = <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>, +- <&clkc CLKID_MPLL2>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; +- }; +- +- dai-link-1 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; +- dai-format = "i2s"; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&aiu AIU_HDMI CTRL_I2S>; +- }; +- }; +- +- dai-link-2 { +- sound-dai = <&aiu AIU_HDMI CTRL_OUT>; +- +- codec-0 { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +-}; +- +-&aiu { +- status = "okay"; +-}; +- +-&cec_AO { +- status = "okay"; +- pinctrl-0 = <&ao_cec_pins>; +- pinctrl-names = "default"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cpu_cooling_maps { +- map0 { +- cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>; +- }; +- +- map1 { +- cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>, +- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +-}; +- +-ðmac { +- pinctrl-0 = <ð_pins>; +- pinctrl-names = "default"; +- +- /* Select external PHY by default */ +- phy-handle = <&external_phy>; +- +- amlogic,tx-delay-ns = <2>; +- +- /* External PHY is in RGMII */ +- phy-mode = "rgmii"; +- +- status = "okay"; +-}; +- +-&external_mdio { +- external_phy: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- +- reset-assert-us = <10000>; +- reset-deassert-us = <80000>; +- reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; +- +- interrupt-parent = <&gpio_intc>; +- /* MAC_INTR on GPIOZ_15 */ +- interrupts = <25 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +- pinctrl-names = "default"; +- hdmi-supply = <&hdmi_5v>; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&i2c_A { +- status = "okay"; +- pinctrl-0 = <&i2c_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&i2c_B { +- status = "okay"; +- pinctrl-0 = <&i2c_b_pins>; +- pinctrl-names = "default"; +- +- rtc: rtc@51 { +- status = "okay"; +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "xin32k"; +- }; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +- linux,rc-map-name = "rc-khadas"; +-}; +- +-&pwm_AO_ab { +- status = "okay"; +- pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; +- pinctrl-names = "default"; +- clocks = <&clkc CLKID_FCLK_DIV4>; +- clock-names = "clkin0"; +-}; +- +-&pwm_ef { +- status = "okay"; +- pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; +- pinctrl-names = "default"; +- clocks = <&clkc CLKID_FCLK_DIV4>; +- clock-names = "clkin0"; +-}; +- +-&sd_emmc_a { +- status = "okay"; +- pinctrl-0 = <&sdio_pins>; +- pinctrl-1 = <&sdio_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <100000000>; +- +- non-removable; +- disable-wp; +- +- /* WiFi firmware requires power to be kept while in suspend */ +- keep-power-in-suspend; +- +- mmc-pwrseq = <&sdio_pwrseq>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_boot>; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_pins>; +- pinctrl-1 = <&sdcard_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- max-frequency = <200000000>; +- non-removable; +- disable-wp; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-/* +- * EMMC_DS pin is shared between SPI NOR CS and eMMC Data Strobe +- * Remove emmc_ds_pins from sd_emmc_c pinctrl-0 then spifc can be enabled +- */ +-&spifc { +- status = "disabled"; +- pinctrl-0 = <&nor_pins>; +- pinctrl-names = "default"; +- +- w25q32: spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "winbond,w25q16", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <104000000>; +- }; +-}; +- +-/* This one is connected to the Bluetooth module */ +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; +- max-speed = <2000000>; +- clocks = <&wifi32k>; +- clock-names = "lpo"; +- }; +-}; +- +-/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */ +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */ +-&uart_AO_B { +- status = "okay"; +- pinctrl-0 = <&uart_ao_b_pins>; +- pinctrl-names = "default"; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vddio_ao18>; +-}; +- +-&usb { +- status = "okay"; +- dr_mode = "peripheral"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-mecool-kiii-pro.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-mecool-kiii-pro.dts +deleted file mode 100644 +index ebebf344b715..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-mecool-kiii-pro.dts ++++ /dev/null +@@ -1,113 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-/* +- * Author: Christian Hewitt +- */ +- +-/dts-v1/; +- +-#include "meson-gxm.dtsi" +-#include "meson-gx-p23x-q20x.dtsi" +-#include +-#include +- +-/ { +- compatible = "videostrong,gxm-kiii-pro", "amlogic,s912", "amlogic,meson-gxm"; +- model = "MeCool KIII Pro"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0xC0000000>; +- }; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 0>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1710000>; +- +- button-function { +- label = "Update"; +- linux,code = ; +- press-threshold-microvolt = <10000>; +- }; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- #address-cells = <1>; +- #size-cells = <0>; +- poll-interval = <100>; +- +- button@0 { +- label = "power"; +- linux,code = ; +- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-blue { +- color = ; +- function = LED_FUNCTION_POWER; +- gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- panic-indicator; +- }; +- }; +-}; +- +-ðmac { +- pinctrl-0 = <ð_pins>; +- pinctrl-names = "default"; +- +- phy-handle = <&external_phy>; +- +- amlogic,tx-delay-ns = <2>; +- +- phy-mode = "rgmii"; +-}; +- +-&external_mdio { +- external_phy: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- max-speed = <1000>; +- +- reset-assert-us = <10000>; +- reset-deassert-us = <80000>; +- reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; +- +- interrupt-parent = <&gpio_intc>; +- /* MAC_INTR on GPIOZ_15 */ +- interrupts = <25 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&ir { +- linux,rc-map-name = "rc-mecool-kiii-pro"; +-}; +- +-&sd_emmc_a { +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; +- max-speed = <2000000>; +- clocks = <&wifi32k>; +- clock-names = "lpo"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-minix-neo-u9h.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-minix-neo-u9h.dts +deleted file mode 100644 +index ea9f234d1fc7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-minix-neo-u9h.dts ++++ /dev/null +@@ -1,120 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) Christian Hewitt +- */ +- +-/dts-v1/; +- +-#include "meson-gxm.dtsi" +-#include "meson-gx-p23x-q20x.dtsi" +-#include +-#include +- +-/ { +- compatible = "minix,neo-u9h", "amlogic,s912", "amlogic,meson-gxm"; +- model = "Minix Neo U9-H"; +- +- leds { +- compatible = "gpio-leds"; +- +- led-white { +- color = ; +- function = LED_FUNCTION_POWER; +- gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- panic-indicator; +- }; +- }; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 0>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1710000>; +- +- button-function { +- label = "update"; +- linux,code = ; +- press-threshold-microvolt = <10000>; +- }; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- #address-cells = <1>; +- #size-cells = <0>; +- poll-interval = <100>; +- +- button@0 { +- label = "power"; +- linux,code = ; +- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-ðmac { +- pinctrl-0 = <ð_pins>; +- pinctrl-names = "default"; +- phy-handle = <&external_phy>; +- amlogic,tx-delay-ns = <2>; +- phy-mode = "rgmii"; +-}; +- +-&external_mdio { +- external_phy: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- max-speed = <1000>; +- +- reset-assert-us = <10000>; +- reset-deassert-us = <80000>; +- reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; +- +- interrupt-parent = <&gpio_intc>; +- /* MAC_INTR on GPIOZ_15 */ +- interrupts = <25 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&ir { +- linux,rc-map-name = "rc-minix-neo"; +-}; +- +-&i2c_B { +- status = "okay"; +- pinctrl-0 = <&i2c_b_pins>; +- pinctrl-names = "default"; +- +- rtc: rtc@51 { +- status = "okay"; +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "xin32k"; +- wakeup-source; +- }; +-}; +- +-&sd_emmc_a { +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; +- max-speed = <2000000>; +- clocks = <&wifi32k>; +- clock-names = "lpo"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-nexbox-a1.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-nexbox-a1.dts +deleted file mode 100644 +index 236c0a144142..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-nexbox-a1.dts ++++ /dev/null +@@ -1,246 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 BayLibre, SAS. +- * Author: Neil Armstrong +- * +- * Copyright (c) 2016 Endless Computers, Inc. +- * Author: Carlo Caione +- */ +- +-/dts-v1/; +- +-#include "meson-gxm.dtsi" +-#include +- +-/ { +- compatible = "nexbox,a1", "amlogic,s912", "amlogic,meson-gxm"; +- model = "NEXBOX A1"; +- +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- spdif_dit: audio-codec-0 { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- status = "okay"; +- sound-name-prefix = "DIT"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- vddio_boot: regulator-vddio-boot { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_BOOT"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vddao_3v3: regulator-vddao-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vcc_3v3: regulator-vcc-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- cvbs-connector { +- compatible = "composite-video-connector"; +- +- port { +- cvbs_connector_in: endpoint { +- remote-endpoint = <&cvbs_vdac_out>; +- }; +- }; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- sound { +- compatible = "amlogic,gx-sound-card"; +- model = "NEXBOX-A1"; +- assigned-clocks = <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>, +- <&clkc CLKID_MPLL2>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; +- }; +- +- dai-link-1 { +- sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>; +- }; +- +- dai-link-2 { +- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; +- dai-format = "i2s"; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&aiu AIU_HDMI CTRL_I2S>; +- }; +- }; +- +- dai-link-3 { +- sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>; +- +- codec-0 { +- sound-dai = <&spdif_dit>; +- }; +- }; +- +- dai-link-4 { +- sound-dai = <&aiu AIU_HDMI CTRL_OUT>; +- +- codec-0 { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +-}; +- +-&aiu { +- status = "okay"; +- pinctrl-0 = <&spdif_out_h_pins>; +- pinctrl-names = "default"; +-}; +- +-&cec_AO { +- status = "okay"; +- pinctrl-0 = <&ao_cec_pins>; +- pinctrl-names = "default"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cvbs_vdac_port { +- cvbs_vdac_out: endpoint { +- remote-endpoint = <&cvbs_connector_in>; +- }; +-}; +- +-ðmac { +- status = "okay"; +- +- pinctrl-0 = <ð_pins>; +- pinctrl-names = "default"; +- +- /* Select external PHY by default */ +- phy-handle = <&external_phy>; +- +- amlogic,tx-delay-ns = <2>; +- +- /* External PHY is in RGMII */ +- phy-mode = "rgmii"; +-}; +- +-&external_mdio { +- external_phy: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- max-speed = <1000>; +- +- reset-assert-us = <10000>; +- reset-deassert-us = <80000>; +- reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +- pinctrl-names = "default"; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_pins>; +- pinctrl-1 = <&sdcard_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- max-frequency = <200000000>; +- non-removable; +- disable-wp; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- status = "okay"; +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-q200.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-q200.dts +deleted file mode 100644 +index 8edbfe040805..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-q200.dts ++++ /dev/null +@@ -1,81 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Endless Computers, Inc. +- * Author: Carlo Caione +- */ +- +-/dts-v1/; +- +-#include +- +-#include "meson-gxm.dtsi" +-#include "meson-gx-p23x-q20x.dtsi" +- +-/ { +- compatible = "amlogic,q200", "amlogic,s912", "amlogic,meson-gxm"; +- model = "Amlogic Meson GXM (S912) Q200 Development Board"; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 0>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1710000>; +- +- button-function { +- label = "Update"; +- linux,code = ; +- press-threshold-microvolt = <10000>; +- }; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- #address-cells = <1>; +- #size-cells = <0>; +- poll-interval = <100>; +- +- button@0 { +- label = "power"; +- linux,code = ; +- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-/* Q200 has exclusive choice between internal or external PHY */ +-ðmac { +- pinctrl-0 = <ð_pins>; +- pinctrl-names = "default"; +- +- /* Select external PHY by default */ +- phy-handle = <&external_phy>; +- +- amlogic,tx-delay-ns = <2>; +- +- /* External PHY is in RGMII */ +- phy-mode = "rgmii"; +-}; +- +-&external_mdio { +- external_phy: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- max-speed = <1000>; +- +- /* External PHY reset is shared with internal PHY Led signal */ +- reset-assert-us = <10000>; +- reset-deassert-us = <80000>; +- reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; +- +- interrupt-parent = <&gpio_intc>; +- /* MAC_INTR on GPIOZ_15 */ +- interrupts = <25 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&sd_emmc_a { +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-q201.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-q201.dts +deleted file mode 100644 +index d02b80d77378..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-q201.dts ++++ /dev/null +@@ -1,28 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Endless Computers, Inc. +- * Author: Carlo Caione +- */ +- +-/dts-v1/; +- +-#include "meson-gxm.dtsi" +-#include "meson-gx-p23x-q20x.dtsi" +- +-/ { +- compatible = "amlogic,q201", "amlogic,s912", "amlogic,meson-gxm"; +- model = "Amlogic Meson GXM (S912) Q201 Development Board"; +-}; +- +-/* Q201 has only internal PHY port */ +-ðmac { +- phy-mode = "rmii"; +- phy-handle = <&internal_phy>; +-}; +- +-&sd_emmc_a { +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-rbox-pro.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-rbox-pro.dts +deleted file mode 100644 +index dde7cfe12cff..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-rbox-pro.dts ++++ /dev/null +@@ -1,205 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016-2017 Andreas Färber +- * +- * Based on nexbox-a1: +- * +- * Copyright (c) 2016 BayLibre, SAS. +- * Author: Neil Armstrong +- * +- * Copyright (c) 2016 Endless Computers, Inc. +- * Author: Carlo Caione +- */ +- +-/dts-v1/; +- +-#include "meson-gxm.dtsi" +- +-/ { +- compatible = "kingnovel,r-box-pro", "amlogic,s912", "amlogic,meson-gxm"; +- model = "R-Box Pro"; +- +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 3 GiB */ +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-blue { +- label = "rbox-pro:blue:on"; +- gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- led-red { +- label = "rbox-pro:red:standby"; +- gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- retain-state-suspended; +- panic-indicator; +- }; +- }; +- +- vddio_boot: regulator-vddio-boot { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_BOOT"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vddao_3v3: regulator-vddao-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vcc_3v3: regulator-vcc-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; +- }; +- +- wifi32k: wifi32k { +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; +- clocks = <&wifi32k>; +- clock-names = "ext_clock"; +- }; +-}; +- +-ðmac { +- status = "okay"; +- +- pinctrl-0 = <ð_pins>; +- pinctrl-names = "default"; +- +- /* Select external PHY by default */ +- phy-handle = <&external_phy>; +- +- amlogic,tx-delay-ns = <2>; +- +- /* External PHY is in RGMII */ +- phy-mode = "rgmii"; +-}; +- +-&external_mdio { +- external_phy: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- max-speed = <1000>; +- +- reset-assert-us = <10000>; +- reset-deassert-us = <80000>; +- reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&pwm_ef { +- status = "okay"; +- pinctrl-0 = <&pwm_e_pins>; +- pinctrl-names = "default"; +- clocks = <&clkc CLKID_FCLK_DIV4>; +- clock-names = "clkin0"; +-}; +- +-/* Wireless SDIO Module */ +-&sd_emmc_a { +- status = "okay"; +- pinctrl-0 = <&sdio_pins>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- +- non-removable; +- disable-wp; +- +- /* WiFi firmware requires power to be kept while in suspend */ +- keep-power-in-suspend; +- +- mmc-pwrseq = <&sdio_pwrseq>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_boot>; +- +- brcmf: brcmf@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_pins>; +- pinctrl-names = "default"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- disable-wp; +- +- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; +- pinctrl-names = "default"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- max-frequency = <200000000>; +- non-removable; +- disable-wp; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&vddio_boot>; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-s912-libretech-pc.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-s912-libretech-pc.dts +deleted file mode 100644 +index 444c249863cb..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-s912-libretech-pc.dts ++++ /dev/null +@@ -1,62 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019 BayLibre SAS. All rights reserved. +- * Author: Jerome Brunet +- */ +- +-/dts-v1/; +- +-#include "meson-gxm.dtsi" +-#include "meson-gx-libretech-pc.dtsi" +- +-/ { +- compatible = "libretech,aml-s912-pc", "amlogic,s912", +- "amlogic,meson-gxm"; +- model = "Libre Computer AML-S912-PC"; +- +- typec2_vbus: regulator-typec2_vbus { +- compatible = "regulator-fixed"; +- regulator-name = "TYPEC2_VBUS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc5v>; +- +- gpio = <&gpio GPIODV_1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&pinctrl_periphs { +- /* +- * Make sure the irq pin of the TYPE C controller is not driven +- * by the SoC. +- */ +- fusb302_irq_pins: fusb302_irq { +- mux { +- groups = "GPIODV_0"; +- function = "gpio_periphs"; +- bias-pull-up; +- output-disable; +- }; +- }; +-}; +- +-&i2c_C { +- fusb302@22 { +- compatible = "fcs,fusb302"; +- reg = <0x22>; +- +- pinctrl-0 = <&fusb302_irq_pins>; +- pinctrl-names = "default"; +- interrupt-parent = <&gpio_intc>; +- interrupts = <59 IRQ_TYPE_LEVEL_LOW>; +- +- vbus-supply = <&typec2_vbus>; +- +- status = "okay"; +- }; +-}; +- +-&usb2_phy2 { +- phy-supply = <&typec2_vbus>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-vega-s96.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-vega-s96.dts +deleted file mode 100644 +index d3fdba4da9a6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-vega-s96.dts ++++ /dev/null +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 BayLibre, SAS. +- * Author: Neil Armstrong +- * Copyright (c) 2017 Oleg +- */ +- +-/dts-v1/; +- +-#include "meson-gxm.dtsi" +-#include "meson-gx-p23x-q20x.dtsi" +- +-/ { +- compatible = "tronsmart,vega-s96", "amlogic,s912", "amlogic,meson-gxm"; +- model = "Tronsmart Vega S96"; +- +-}; +- +-ðmac { +- pinctrl-0 = <ð_pins>; +- pinctrl-names = "default"; +- +- /* Select external PHY by default */ +- phy-handle = <&external_phy>; +- +- amlogic,tx-delay-ns = <2>; +- +- /* External PHY is in RGMII */ +- phy-mode = "rgmii"; +-}; +- +-&external_mdio { +- external_phy: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- }; +-}; +- +-&ir { +- linux,rc-map-name = "rc-vega-s9x"; +-}; +- +-&usb { +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-wetek-core2.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-wetek-core2.dts +deleted file mode 100644 +index 1e7f77f9b533..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm-wetek-core2.dts ++++ /dev/null +@@ -1,87 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Christian Hewitt +- */ +- +-/dts-v1/; +- +-#include "meson-gxm.dtsi" +-#include "meson-gx-p23x-q20x.dtsi" +-#include +-#include +- +-/ { +- compatible = "wetek,core2", "amlogic,s912", "amlogic,meson-gxm"; +- model = "WeTek Core 2"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 3 GiB */ +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-blue { +- color = ; +- function = LED_FUNCTION_STATUS; +- gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 0>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1710000>; +- +- button-update { +- label = "update"; +- linux,code = ; +- press-threshold-microvolt = <10000>; +- }; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- #address-cells = <1>; +- #size-cells = <0>; +- poll-interval = <100>; +- +- button-power { +- label = "power"; +- linux,code = ; +- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-/* Disabled as Realtek RTL8152 USB provides Ethernet */ +-ðmac { +- status = "disabled"; +-}; +- +-&internal_phy { +- status = "disabled"; +-}; +- +-&ir { +- linux,rc-map-name = "rc-wetek-play2"; +-}; +- +-/* This is connected to the Bluetooth module: */ +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; +- max-speed = <2000000>; +- clocks = <&wifi32k>; +- clock-names = "lpo"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm.dtsi +deleted file mode 100644 +index 411cc312fc62..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-gxm.dtsi ++++ /dev/null +@@ -1,216 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Endless Computers, Inc. +- * Author: Carlo Caione +- */ +- +-#include "meson-gxl.dtsi" +- +-/ { +- compatible = "amlogic,meson-gxm"; +- +- cpus { +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- core2 { +- cpu = <&cpu2>; +- }; +- core3 { +- cpu = <&cpu3>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&cpu4>; +- }; +- core1 { +- cpu = <&cpu5>; +- }; +- core2 { +- cpu = <&cpu6>; +- }; +- core3 { +- cpu = <&cpu7>; +- }; +- }; +- }; +- +- cpu0: cpu@0 { +- capacity-dmips-mhz = <1024>; +- }; +- +- cpu1: cpu@1 { +- capacity-dmips-mhz = <1024>; +- }; +- +- cpu2: cpu@2 { +- capacity-dmips-mhz = <1024>; +- }; +- +- cpu3: cpu@3 { +- capacity-dmips-mhz = <1024>; +- }; +- +- cpu4: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- next-level-cache = <&l2>; +- clocks = <&scpi_dvfs 1>; +- #cooling-cells = <2>; +- }; +- +- cpu5: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x101>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- next-level-cache = <&l2>; +- clocks = <&scpi_dvfs 1>; +- #cooling-cells = <2>; +- }; +- +- cpu6: cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x102>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- next-level-cache = <&l2>; +- clocks = <&scpi_dvfs 1>; +- #cooling-cells = <2>; +- }; +- +- cpu7: cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x103>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- next-level-cache = <&l2>; +- clocks = <&scpi_dvfs 1>; +- #cooling-cells = <2>; +- }; +- }; +- +- gpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-125000000 { +- opp-hz = /bits/ 64 <125000000>; +- opp-microvolt = <950000>; +- }; +- opp-250000000 { +- opp-hz = /bits/ 64 <250000000>; +- opp-microvolt = <950000>; +- }; +- opp-285714285 { +- opp-hz = /bits/ 64 <285714285>; +- opp-microvolt = <950000>; +- }; +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <950000>; +- }; +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <950000>; +- }; +- opp-666666666 { +- opp-hz = /bits/ 64 <666666666>; +- opp-microvolt = <950000>; +- }; +- }; +-}; +- +-&apb { +- usb2_phy2: phy@78040 { +- compatible = "amlogic,meson-gxl-usb2-phy"; +- #phy-cells = <0>; +- reg = <0x0 0x78040 0x0 0x20>; +- clocks = <&clkc CLKID_USB>; +- clock-names = "phy"; +- resets = <&reset RESET_USB_OTG>; +- reset-names = "phy"; +- status = "okay"; +- }; +- +- mali: gpu@c0000 { +- compatible = "amlogic,meson-gxm-mali", "arm,mali-t820"; +- reg = <0x0 0xc0000 0x0 0x40000>; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- ; +- interrupt-names = "job", "mmu", "gpu"; +- clocks = <&clkc CLKID_MALI>; +- resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>; +- operating-points-v2 = <&gpu_opp_table>; +- }; +-}; +- +-&clkc_AO { +- compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc"; +-}; +- +-&cpu_cooling_maps { +- map0 { +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- +- map1 { +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +-}; +- +-&saradc { +- compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc"; +-}; +- +-&scpi_dvfs { +- clock-indices = <0 1>; +- clock-output-names = "vbig", "vlittle"; +-}; +- +-&vpu { +- compatible = "amlogic,meson-gxm-vpu", "amlogic,meson-gx-vpu"; +-}; +- +-&hdmi_tx { +- compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; +-}; +- +-&usb { +- compatible = "amlogic,meson-gxm-usb-ctrl"; +- +- phy-names = "usb2-phy0", "usb2-phy1", "usb2-phy2"; +- phys = <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>; +-}; +- +-&vdec { +- compatible = "amlogic,gxm-vdec", "amlogic,gx-vdec"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-khadas-vim3.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-khadas-vim3.dtsi +deleted file mode 100644 +index 3cf4ecb6d52e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-khadas-vim3.dtsi ++++ /dev/null +@@ -1,534 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- * Copyright (c) 2019 Christian Hewitt +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- rtc0 = &rtc; +- rtc1 = &vrtc; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 2>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1710000>; +- +- button-function { +- label = "Function"; +- linux,code = ; +- press-threshold-microvolt = <10000>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-white { +- color = ; +- function = LED_FUNCTION_STATUS; +- gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-red { +- color = ; +- function = LED_FUNCTION_STATUS; +- gpios = <&gpio_expander 5 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- poll-interval = <100>; +- +- power-button { +- label = "power"; +- linux,code = ; +- gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; +- clocks = <&wifi32k>; +- clock-names = "ext_clock"; +- }; +- +- dc_in: regulator-dc_in { +- compatible = "regulator-fixed"; +- regulator-name = "DC_IN"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- vcc_5v: regulator-vcc_5v { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&dc_in>; +- +- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; +- enable-active-high; +- }; +- +- vcc_1v8: regulator-vcc_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_3v3>; +- regulator-always-on; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vsys_3v3>; +- regulator-always-on; +- /* FIXME: actually controlled by VDDCPU_B_EN */ +- }; +- +- vddao_1v8: regulator-vddao_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vsys_3v3>; +- regulator-always-on; +- }; +- +- emmc_1v8: regulator-emmc_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "EMMC_AO1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_3v3>; +- regulator-always-on; +- }; +- +- vsys_3v3: regulator-vsys_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VSYS_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&dc_in>; +- regulator-always-on; +- }; +- +- usb_pwr: regulator-usb_pwr { +- compatible = "regulator-fixed"; +- regulator-name = "USB_PWR"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc_5v>; +- +- gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- +- sound { +- compatible = "amlogic,axg-sound-card"; +- model = "KHADAS-VIM3"; +- audio-aux-devs = <&tdmin_a>, <&tdmout_a>; +- audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", +- "TDMOUT_A IN 1", "FRDDR_B OUT 0", +- "TDMOUT_A IN 2", "FRDDR_C OUT 0", +- "TDM_A Playback", "TDMOUT_A OUT", +- "TDMIN_A IN 0", "TDM_A Capture", +- "TDMIN_A IN 3", "TDM_A Loopback", +- "TODDR_A IN 0", "TDMIN_A OUT", +- "TODDR_B IN 0", "TDMIN_A OUT", +- "TODDR_C IN 0", "TDMIN_A OUT"; +- +- assigned-clocks = <&clkc CLKID_MPLL2>, +- <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&frddr_a>; +- }; +- +- dai-link-1 { +- sound-dai = <&frddr_b>; +- }; +- +- dai-link-2 { +- sound-dai = <&frddr_c>; +- }; +- +- dai-link-3 { +- sound-dai = <&toddr_a>; +- }; +- +- dai-link-4 { +- sound-dai = <&toddr_b>; +- }; +- +- dai-link-5 { +- sound-dai = <&toddr_c>; +- }; +- +- /* 8ch hdmi interface */ +- dai-link-6 { +- sound-dai = <&tdmif_a>; +- dai-format = "i2s"; +- dai-tdm-slot-tx-mask-0 = <1 1>; +- dai-tdm-slot-tx-mask-1 = <1 1>; +- dai-tdm-slot-tx-mask-2 = <1 1>; +- dai-tdm-slot-tx-mask-3 = <1 1>; +- mclk-fs = <256>; +- +- codec { +- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; +- }; +- }; +- +- /* hdmi glue */ +- dai-link-7 { +- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; +- +- codec { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +- +- wifi32k: wifi32k { +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ +- }; +-}; +- +-&arb { +- status = "okay"; +-}; +- +-&clkc_audio { +- status = "okay"; +-}; +- +-&cec_AO { +- pinctrl-0 = <&cec_ao_a_h_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cecb_AO { +- pinctrl-0 = <&cec_ao_b_h_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cpu_thermal { +- trips { +- cpu_active: cpu-active { +- temperature = <80000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "active"; +- }; +- }; +- +- cooling-maps { +- map { +- trip = <&cpu_active>; +- cooling-device = <&khadas_mcu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +-}; +- +-&ext_mdio { +- external_phy: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- max-speed = <1000>; +- +- interrupt-parent = <&gpio_intc>; +- /* MAC_INTR on GPIOZ_14 */ +- interrupts = <26 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-ðmac { +- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy-mode = "rgmii"; +- phy-handle = <&external_phy>; +- amlogic,tx-delay-ns = <2>; +-}; +- +-&frddr_a { +- status = "okay"; +-}; +- +-&frddr_b { +- status = "okay"; +-}; +- +-&frddr_c { +- status = "okay"; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; +- pinctrl-names = "default"; +- hdmi-supply = <&vcc_5v>; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&i2c_AO { +- status = "okay"; +- pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>; +- pinctrl-names = "default"; +- +- khadas_mcu: system-controller@18 { +- compatible = "khadas,mcu"; +- reg = <0x18>; +- #cooling-cells = <2>; +- }; +- +- gpio_expander: gpio-controller@20 { +- compatible = "ti,tca6408"; +- reg = <0x20>; +- vcc-supply = <&vcc_3v3>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- rtc: rtc@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- }; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +- linux,rc-map-name = "rc-khadas"; +-}; +- +-&pcie { +- reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>; +-}; +- +-&pwm_ef { +- status = "okay"; +- pinctrl-0 = <&pwm_e_pins>; +- pinctrl-names = "default"; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vddao_1v8>; +-}; +- +-/* SDIO */ +-&sd_emmc_a { +- status = "okay"; +- pinctrl-0 = <&sdio_pins>; +- pinctrl-1 = <&sdio_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <100000000>; +- +- non-removable; +- disable-wp; +- +- /* WiFi firmware requires power to be kept while in suspend */ +- keep-power-in-suspend; +- +- mmc-pwrseq = <&sdio_pwrseq>; +- +- vmmc-supply = <&vsys_3v3>; +- vqmmc-supply = <&vddao_1v8>; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_c_pins>; +- pinctrl-1 = <&sdcard_clk_gate_c_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- disable-wp; +- +- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; +- vmmc-supply = <&vsys_3v3>; +- vqmmc-supply = <&vsys_3v3>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- max-frequency = <200000000>; +- disable-wp; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&emmc_1v8>; +-}; +- +-/* +- * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR CS +- * and eMMC Data 4 to 7 pins. +- * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0, +- * and change bus-width to 4 then spifc can be enabled. +- */ +-&spifc { +- status = "disabled"; +- pinctrl-0 = <&nor_pins>; +- pinctrl-names = "default"; +- +- w25q128: spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "winbond,w25q128fw", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <104000000>; +- }; +-}; +- +-&tdmif_a { +- status = "okay"; +-}; +- +-&tdmin_a { +- status = "okay"; +-}; +- +-&tdmout_a { +- status = "okay"; +-}; +- +-&toddr_a { +- status = "okay"; +-}; +- +-&toddr_b { +- status = "okay"; +-}; +- +-&toddr_c { +- status = "okay"; +-}; +- +-&tohdmitx { +- status = "okay"; +-}; +- +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; +- max-speed = <2000000>; +- clocks = <&wifi32k>; +- clock-names = "lpo"; +- }; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb2_phy0 { +- phy-supply = <&dc_in>; +-}; +- +-&usb2_phy1 { +- phy-supply = <&usb_pwr>; +-}; +- +-&usb3_pcie_phy { +- phy-supply = <&usb_pwr>; +-}; +- +-&usb { +- status = "okay"; +- dr_mode = "peripheral"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1-bananapi-m5.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1-bananapi-m5.dts +deleted file mode 100644 +index 5751c48620ed..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1-bananapi-m5.dts ++++ /dev/null +@@ -1,646 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2021 BayLibre SAS +- * Author: Neil Armstrong +- */ +- +-/dts-v1/; +- +-#include "meson-sm1.dtsi" +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "bananapi,bpi-m5", "amlogic,sm1"; +- model = "Banana Pi BPI-M5"; +- +- adc_keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 2>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1800000>; +- +- key { +- label = "SW3"; +- linux,code = ; +- press-threshold-microvolt = <1700000>; +- }; +- }; +- +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- /* TOFIX: handle CVBS_DET on SARADC channel 0 */ +- cvbs-connector { +- compatible = "composite-video-connector"; +- +- port { +- cvbs_connector_in: endpoint { +- remote-endpoint = <&cvbs_vdac_out>; +- }; +- }; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- key { +- label = "SW1"; +- linux,code = ; +- gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; +- interrupt-parent = <&gpio_intc>; +- interrupts = <3 IRQ_TYPE_EDGE_BOTH>; +- }; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- green { +- color = ; +- function = LED_FUNCTION_STATUS; +- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; +- }; +- +- blue { +- color = ; +- function = LED_FUNCTION_STATUS; +- gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x40000000>; +- }; +- +- emmc_1v8: regulator-emmc_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "EMMC_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- }; +- +- dc_in: regulator-dc_in { +- compatible = "regulator-fixed"; +- regulator-name = "DC_IN"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- vddio_c: regulator-vddio_c { +- compatible = "regulator-gpio"; +- regulator-name = "VDDIO_C"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- enable-gpio = <&gpio_ao GPIOE_2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- +- gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>; +- gpios-states = <1>; +- +- states = <1800000 0>, +- <3300000 1>; +- }; +- +- tflash_vdd: regulator-tflash_vdd { +- compatible = "regulator-fixed"; +- regulator-name = "TFLASH_VDD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&dc_in>; +- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; +- enable-active-high; +- regulator-always-on; +- }; +- +- vddao_1v8: regulator-vddao_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- }; +- +- vddao_3v3: regulator-vddao_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&dc_in>; +- regulator-always-on; +- }; +- +- vddcpu: regulator-vddcpu { +- /* +- * SY8120B1ABC DC/DC Regulator. +- */ +- compatible = "pwm-regulator"; +- +- regulator-name = "VDDCPU"; +- regulator-min-microvolt = <690000>; +- regulator-max-microvolt = <1050000>; +- +- pwm-supply = <&dc_in>; +- +- pwms = <&pwm_AO_cd 1 1250 0>; +- pwm-dutycycle-range = <100 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* USB Hub Power Enable */ +- vl_pwr_en: regulator-vl_pwr_en { +- compatible = "regulator-fixed"; +- regulator-name = "VL_PWR_EN"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&dc_in>; +- +- gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sound { +- compatible = "amlogic,axg-sound-card"; +- model = "BPI-M5"; +- audio-widgets = "Line", "Lineout"; +- audio-aux-devs = <&tdmout_b>, <&tdmout_c>, +- <&tdmin_a>, <&tdmin_b>, <&tdmin_c>; +- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", +- "TDMOUT_B IN 1", "FRDDR_B OUT 1", +- "TDMOUT_B IN 2", "FRDDR_C OUT 1", +- "TDM_B Playback", "TDMOUT_B OUT", +- "TDMOUT_C IN 0", "FRDDR_A OUT 2", +- "TDMOUT_C IN 1", "FRDDR_B OUT 2", +- "TDMOUT_C IN 2", "FRDDR_C OUT 2", +- "TDM_C Playback", "TDMOUT_C OUT", +- "TDMIN_A IN 4", "TDM_B Loopback", +- "TDMIN_B IN 4", "TDM_B Loopback", +- "TDMIN_C IN 4", "TDM_B Loopback", +- "TDMIN_A IN 5", "TDM_C Loopback", +- "TDMIN_B IN 5", "TDM_C Loopback", +- "TDMIN_C IN 5", "TDM_C Loopback", +- "TODDR_A IN 0", "TDMIN_A OUT", +- "TODDR_B IN 0", "TDMIN_A OUT", +- "TODDR_C IN 0", "TDMIN_A OUT", +- "TODDR_A IN 1", "TDMIN_B OUT", +- "TODDR_B IN 1", "TDMIN_B OUT", +- "TODDR_C IN 1", "TDMIN_B OUT", +- "TODDR_A IN 2", "TDMIN_C OUT", +- "TODDR_B IN 2", "TDMIN_C OUT", +- "TODDR_C IN 2", "TDMIN_C OUT", +- "Lineout", "ACODEC LOLP", +- "Lineout", "ACODEC LORP"; +- +- assigned-clocks = <&clkc CLKID_MPLL2>, +- <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&frddr_a>; +- }; +- +- dai-link-1 { +- sound-dai = <&frddr_b>; +- }; +- +- dai-link-2 { +- sound-dai = <&frddr_c>; +- }; +- +- dai-link-3 { +- sound-dai = <&toddr_a>; +- }; +- +- dai-link-4 { +- sound-dai = <&toddr_b>; +- }; +- +- dai-link-5 { +- sound-dai = <&toddr_c>; +- }; +- +- /* 8ch hdmi interface */ +- dai-link-6 { +- sound-dai = <&tdmif_b>; +- dai-format = "i2s"; +- dai-tdm-slot-tx-mask-0 = <1 1>; +- dai-tdm-slot-tx-mask-1 = <1 1>; +- dai-tdm-slot-tx-mask-2 = <1 1>; +- dai-tdm-slot-tx-mask-3 = <1 1>; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; +- }; +- +- codec-1 { +- sound-dai = <&toacodec TOACODEC_IN_B>; +- }; +- }; +- +- /* i2s jack output interface */ +- dai-link-7 { +- sound-dai = <&tdmif_c>; +- dai-format = "i2s"; +- dai-tdm-slot-tx-mask-0 = <1 1>; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>; +- }; +- +- codec-1 { +- sound-dai = <&toacodec TOACODEC_IN_C>; +- }; +- }; +- +- /* hdmi glue */ +- dai-link-8 { +- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; +- +- codec { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- +- /* acodec glue */ +- dai-link-9 { +- sound-dai = <&toacodec TOACODEC_OUT>; +- +- codec { +- sound-dai = <&acodec>; +- }; +- }; +- }; +-}; +- +-&acodec { +- AVDD-supply = <&vddao_1v8>; +- status = "okay"; +-}; +- +-&arb { +- status = "okay"; +-}; +- +-&clkc_audio { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu1 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU1_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu2 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU2_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu3 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU3_CLK>; +- clock-latency = <50000>; +-}; +- +-&cvbs_vdac_port { +- cvbs_vdac_out: endpoint { +- remote-endpoint = <&cvbs_connector_in>; +- }; +-}; +- +-&ext_mdio { +- external_phy: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- max-speed = <1000>; +- +- interrupt-parent = <&gpio_intc>; +- /* MAC_INTR on GPIOZ_14 */ +- interrupts = <26 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-ðmac { +- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy-mode = "rgmii-txid"; +- phy-handle = <&external_phy>; +-}; +- +-&frddr_a { +- status = "okay"; +-}; +- +-&frddr_b { +- status = "okay"; +-}; +- +-&frddr_c { +- status = "okay"; +-}; +- +-&gpio { +- gpio-line-names = +- /* GPIOZ */ +- "ETH_MDIO", /* GPIOZ_0 */ +- "ETH_MDC", /* GPIOZ_1 */ +- "ETH_RXCLK", /* GPIOZ_2 */ +- "ETH_RX_DV", /* GPIOZ_3 */ +- "ETH_RXD0", /* GPIOZ_4 */ +- "ETH_RXD1", /* GPIOZ_5 */ +- "ETH_RXD2", /* GPIOZ_6 */ +- "ETH_RXD3", /* GPIOZ_7 */ +- "ETH_TXCLK", /* GPIOZ_8 */ +- "ETH_TXEN", /* GPIOZ_9 */ +- "ETH_TXD0", /* GPIOZ_10 */ +- "ETH_TXD1", /* GPIOZ_11 */ +- "ETH_TXD2", /* GPIOZ_12 */ +- "ETH_TXD3", /* GPIOZ_13 */ +- "ETH_INTR", /* GPIOZ_14 */ +- "ETH_NRST", /* GPIOZ_15 */ +- /* GPIOH */ +- "HDMI_SDA", /* GPIOH_0 */ +- "HDMI_SCL", /* GPIOH_1 */ +- "HDMI_HPD", /* GPIOH_2 */ +- "HDMI_CEC", /* GPIOH_3 */ +- "VL-RST_N", /* GPIOH_4 */ +- "CON1-P36", /* GPIOH_5 */ +- "VL-PWREN", /* GPIOH_6 */ +- "WiFi_3V3_1V8", /* GPIOH_7 */ +- "TFLASH_VDD_EN", /* GPIOH_8 */ +- /* BOOT */ +- "eMMC_D0", /* BOOT_0 */ +- "eMMC_D1", /* BOOT_1 */ +- "eMMC_D2", /* BOOT_2 */ +- "eMMC_D3", /* BOOT_3 */ +- "eMMC_D4", /* BOOT_4 */ +- "eMMC_D5", /* BOOT_5 */ +- "eMMC_D6", /* BOOT_6 */ +- "eMMC_D7", /* BOOT_7 */ +- "eMMC_CLK", /* BOOT_8 */ +- "", +- "eMMC_CMD", /* BOOT_10 */ +- "", +- "eMMC_RST#", /* BOOT_12 */ +- "eMMC_DS", /* BOOT_13 */ +- /* GPIOC */ +- "SD_D0_B", /* GPIOC_0 */ +- "SD_D1_B", /* GPIOC_1 */ +- "SD_D2_B", /* GPIOC_2 */ +- "SD_D3_B", /* GPIOC_3 */ +- "SD_CLK_B", /* GPIOC_4 */ +- "SD_CMD_B", /* GPIOC_5 */ +- "CARD_EN_DET", /* GPIOC_6 */ +- "", +- /* GPIOA */ +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", +- "CON1-P27", /* GPIOA_14 */ +- "CON1-P28", /* GPIOA_15 */ +- /* GPIOX */ +- "CON1-P16", /* GPIOX_0 */ +- "CON1-P18", /* GPIOX_1 */ +- "CON1-P22", /* GPIOX_2 */ +- "CON1-P11", /* GPIOX_3 */ +- "CON1-P13", /* GPIOX_4 */ +- "CON1-P07", /* GPIOX_5 */ +- "CON1-P33", /* GPIOX_6 */ +- "CON1-P15", /* GPIOX_7 */ +- "CON1-P19", /* GPIOX_8 */ +- "CON1-P21", /* GPIOX_9 */ +- "CON1-P24", /* GPIOX_10 */ +- "CON1-P23", /* GPIOX_11 */ +- "CON1-P08", /* GPIOX_12 */ +- "CON1-P10", /* GPIOX_13 */ +- "CON1-P29", /* GPIOX_14 */ +- "CON1-P31", /* GPIOX_15 */ +- "CON1-P26", /* GPIOX_16 */ +- "CON1-P03", /* GPIOX_17 */ +- "CON1-P05", /* GPIOX_18 */ +- "CON1-P32"; /* GPIOX_19 */ +- +- /* +- * WARNING: The USB Hub on the BPI-M5 needs a reset signal +- * to be turned high in order to be detected by the USB Controller +- * This signal should be handled by a USB specific power sequence +- * in order to reset the Hub when USB bus is powered down. +- */ +- usb-hub { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "usb-hub-reset"; +- }; +-}; +- +-&gpio_ao { +- gpio-line-names = +- /* GPIOAO */ +- "DEBUG TX", /* GPIOAO_0 */ +- "DEBUG RX", /* GPIOAO_1 */ +- "SYS_LED2", /* GPIOAO_2 */ +- "UPDATE_KEY", /* GPIOAO_3 */ +- "CON1-P40", /* GPIOAO_4 */ +- "IR_IN", /* GPIOAO_5 */ +- "TF_3V3N_1V8_EN", /* GPIOAO_6 */ +- "CON1-P35", /* GPIOAO_7 */ +- "CON1-P12", /* GPIOAO_8 */ +- "CON1-P37", /* GPIOAO_9 */ +- "CON1-P38", /* GPIOAO_10 */ +- "SYS_LED", /* GPIOAO_11 */ +- /* GPIOE */ +- "VDDEE_PWM", /* GPIOE_0 */ +- "VDDCPU_PWM", /* GPIOE_1 */ +- "TF_PWR_EN"; /* GPIOE_2 */ +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; +- pinctrl-names = "default"; +- hdmi-supply = <&dc_in>; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&pwm_AO_cd { +- pinctrl-0 = <&pwm_ao_d_e_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>; +- clock-names = "clkin1"; +- status = "okay"; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vddao_1v8>; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_c_pins>; +- pinctrl-1 = <&sdcard_clk_gate_c_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- disable-wp; +- +- /* TOFIX: SD card is barely usable in SDR modes */ +- +- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; +- vmmc-supply = <&tflash_vdd>; +- vqmmc-supply = <&vddio_c>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- max-frequency = <200000000>; +- disable-wp; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&emmc_1v8>; +-}; +- +-&tdmif_b { +- status = "okay"; +-}; +- +-&tdmif_c { +- status = "okay"; +-}; +- +-&tdmin_a { +- status = "okay"; +-}; +- +-&tdmin_b { +- status = "okay"; +-}; +- +-&tdmin_c { +- status = "okay"; +-}; +- +-&tdmout_b { +- status = "okay"; +-}; +- +-&tdmout_c { +- status = "okay"; +-}; +- +-&toacodec { +- status = "okay"; +-}; +- +-&tohdmitx { +- status = "okay"; +-}; +- +-&toddr_a { +- status = "okay"; +-}; +- +-&toddr_b { +- status = "okay"; +-}; +- +-&toddr_c { +- status = "okay"; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- status = "okay"; +-}; +- +-&usb2_phy0 { +- phy-supply = <&dc_in>; +-}; +- +-&usb2_phy1 { +- /* Enable the hub which is connected to this port */ +- phy-supply = <&vl_pwr_en>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1-khadas-vim3l.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1-khadas-vim3l.dts +deleted file mode 100644 +index 9c0b544e2209..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1-khadas-vim3l.dts ++++ /dev/null +@@ -1,113 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- */ +- +-/dts-v1/; +- +-#include "meson-sm1.dtsi" +-#include "meson-khadas-vim3.dtsi" +-#include +- +-/ { +- compatible = "khadas,vim3l", "amlogic,sm1"; +- model = "Khadas VIM3L"; +- +- vddcpu: regulator-vddcpu { +- /* +- * Silergy SY8030DEC Regulator. +- */ +- compatible = "pwm-regulator"; +- +- regulator-name = "VDDCPU"; +- regulator-min-microvolt = <690000>; +- regulator-max-microvolt = <1050000>; +- +- pwm-supply = <&vsys_3v3>; +- +- pwms = <&pwm_AO_cd 1 1250 0>; +- pwm-dutycycle-range = <100 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sound { +- model = "G12B-KHADAS-VIM3L"; +- audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", +- "TDMOUT_A IN 1", "FRDDR_B OUT 0", +- "TDMOUT_A IN 2", "FRDDR_C OUT 0", +- "TDM_A Playback", "TDMOUT_A OUT", +- "TDMIN_A IN 0", "TDM_A Capture", +- "TDMIN_A IN 13", "TDM_A Loopback", +- "TODDR_A IN 0", "TDMIN_A OUT", +- "TODDR_B IN 0", "TDMIN_A OUT", +- "TODDR_C IN 0", "TDMIN_A OUT"; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu1 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU1_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu2 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU2_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu3 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU3_CLK>; +- clock-latency = <50000>; +-}; +- +-&pwm_AO_cd { +- pinctrl-0 = <&pwm_ao_d_e_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>; +- clock-names = "clkin1"; +- status = "okay"; +-}; +- +-/* +- * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential +- * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between +- * an USB3.0 Type A connector and a M.2 Key M slot. +- * The PHY driving these differential lines is shared between +- * the USB3.0 controller and the PCIe Controller, thus only +- * a single controller can use it. +- * If the MCU is configured to mux the PCIe/USB3.0 differential lines +- * to the M.2 Key M slot, uncomment the following block to disable +- * USB3.0 from the USB Complex and enable the PCIe controller. +- * The End User is not expected to uncomment the following except for +- * testing purposes, but instead rely on the firmware/bootloader to +- * update these nodes accordingly if PCIe mode is selected by the MCU. +- */ +-/* +-&pcie { +- status = "okay"; +-}; +- +-&usb { +- phys = <&usb2_phy0>, <&usb2_phy1>; +- phy-names = "usb2-phy0", "usb2-phy1"; +-}; +- */ +- +-&sd_emmc_a { +- sd-uhs-sdr50; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1-odroid-c4.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1-odroid-c4.dts +deleted file mode 100644 +index 8c30ce63686e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1-odroid-c4.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Dongjin Kim +- */ +- +-/dts-v1/; +- +-#include "meson-sm1-odroid.dtsi" +- +-/ { +- compatible = "hardkernel,odroid-c4", "amlogic,sm1"; +- model = "Hardkernel ODROID-C4"; +- +- leds { +- compatible = "gpio-leds"; +- +- led-blue { +- color = ; +- function = LED_FUNCTION_STATUS; +- gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- panic-indicator; +- }; +- }; +- +- sound { +- model = "ODROID-C4"; +- }; +-}; +- +-&gpio { +- /* +- * WARNING: The USB Hub on the Odroid-C4 needs a reset signal +- * to be turned high in order to be detected by the USB Controller +- * This signal should be handled by a USB specific power sequence +- * in order to reset the Hub when USB bus is powered down. +- */ +- hog-0 { +- gpio-hog; +- gpios = ; +- output-high; +- line-name = "usb-hub-reset"; +- }; +-}; +- +-&ir { +- linux,rc-map-name = "rc-odroid"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1-odroid-hc4.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1-odroid-hc4.dts +deleted file mode 100644 +index f3f953225bf5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1-odroid-hc4.dts ++++ /dev/null +@@ -1,140 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Dongjin Kim +- */ +- +-/dts-v1/; +- +-#include "meson-sm1-odroid.dtsi" +- +-/ { +- compatible = "hardkernel,odroid-hc4", "amlogic,sm1"; +- model = "Hardkernel ODROID-HC4"; +- +- aliases { +- rtc0 = &rtc; +- rtc1 = &vrtc; +- }; +- +- fan0: pwm-fan { +- compatible = "pwm-fan"; +- #cooling-cells = <2>; +- cooling-min-state = <0>; +- cooling-max-state = <3>; +- cooling-levels = <0 120 170 220>; +- pwms = <&pwm_cd 1 40000 0>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-blue { +- color = ; +- function = LED_FUNCTION_STATUS; +- gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- panic-indicator; +- }; +- +- led-red { +- color = ; +- function = LED_FUNCTION_POWER; +- gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- /* Powers the SATA Disk 0 regulator, which is enabled when a disk load is detected */ +- p12v_0: regulator-p12v_0 { +- compatible = "regulator-fixed"; +- regulator-name = "P12V_0"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- vin-supply = <&main_12v>; +- +- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; +- enable-active-high; +- regulator-always-on; +- }; +- +- /* Powers the SATA Disk 1 regulator, which is enabled when a disk load is detected */ +- p12v_1: regulator-p12v_1 { +- compatible = "regulator-fixed"; +- regulator-name = "P12V_1"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- vin-supply = <&main_12v>; +- +- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; +- enable-active-high; +- regulator-always-on; +- }; +- +- sound { +- model = "ODROID-HC4"; +- }; +-}; +- +-&cpu_thermal { +- cooling-maps { +- map { +- trip = <&cpu_passive>; +- cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +-}; +- +-&ir { +- linux,rc-map-name = "rc-odroid"; +-}; +- +-&i2c2 { +- status = "okay"; +- pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>; +- pinctrl-names = "default"; +- +- rtc: rtc@51 { +- status = "okay"; +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- wakeup-source; +- }; +-}; +- +-&pcie { +- status = "okay"; +- reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; +-}; +- +-&pwm_cd { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm_d_x6_pins>; +-}; +- +-&sd_emmc_c { +- status = "disabled"; +-}; +- +-&spifc { +- status = "okay"; +- pinctrl-0 = <&nor_pins>; +- pinctrl-names = "default"; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <104000000>; +- }; +-}; +- +-&usb { +- phys = <&usb2_phy1>; +- phy-names = "usb2-phy1"; +-}; +- +-&usb2_phy0 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1-odroid.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1-odroid.dtsi +deleted file mode 100644 +index 76ad052fbf0c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1-odroid.dtsi ++++ /dev/null +@@ -1,453 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Dongjin Kim +- */ +- +-#include "meson-sm1.dtsi" +-#include +-#include +-#include +- +-/ { +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x40000000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; +- }; +- +- tflash_vdd: regulator-tflash_vdd { +- compatible = "regulator-fixed"; +- +- regulator-name = "TFLASH_VDD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>; +- enable-active-high; +- regulator-always-on; +- }; +- +- tf_io: gpio-regulator-tf_io { +- compatible = "regulator-gpio"; +- +- regulator-name = "TF_IO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc_5v>; +- +- enable-gpio = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>; +- enable-active-high; +- regulator-always-on; +- +- gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE>; +- gpios-states = <0>; +- +- states = <3300000 0>, +- <1800000 1>; +- }; +- +- flash_1v8: regulator-flash_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "FLASH_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_3v3>; +- regulator-always-on; +- }; +- +- main_12v: regulator-main_12v { +- compatible = "regulator-fixed"; +- regulator-name = "12V"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- }; +- +- vcc_5v: regulator-vcc_5v { +- compatible = "regulator-fixed"; +- regulator-name = "5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- vin-supply = <&main_12v>; +- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; +- enable-active-high; +- }; +- +- vcc_1v8: regulator-vcc_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_3v3>; +- regulator-always-on; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- /* FIXME: actually controlled by VDDCPU_B_EN */ +- }; +- +- vddcpu: regulator-vddcpu { +- /* +- * MP8756GD Regulator. +- */ +- compatible = "pwm-regulator"; +- +- regulator-name = "VDDCPU"; +- regulator-min-microvolt = <721000>; +- regulator-max-microvolt = <1022000>; +- +- pwm-supply = <&main_12v>; +- +- pwms = <&pwm_AO_cd 1 1250 0>; +- pwm-dutycycle-range = <100 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +- +- usb_pwr_en: regulator-usb_pwr_en { +- compatible = "regulator-fixed"; +- regulator-name = "USB_PWR_EN"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc_5v>; +- +- /* Connected to the microUSB port power enable */ +- gpio = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vddao_1v8: regulator-vddao_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- }; +- +- vddao_3v3: regulator-vddao_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&main_12v>; +- regulator-always-on; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- sound { +- compatible = "amlogic,axg-sound-card"; +- audio-aux-devs = <&tdmout_b>; +- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", +- "TDMOUT_B IN 1", "FRDDR_B OUT 1", +- "TDMOUT_B IN 2", "FRDDR_C OUT 1", +- "TDM_B Playback", "TDMOUT_B OUT"; +- +- assigned-clocks = <&clkc CLKID_MPLL2>, +- <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&frddr_a>; +- }; +- +- dai-link-1 { +- sound-dai = <&frddr_b>; +- }; +- +- dai-link-2 { +- sound-dai = <&frddr_c>; +- }; +- +- /* 8ch hdmi interface */ +- dai-link-3 { +- sound-dai = <&tdmif_b>; +- dai-format = "i2s"; +- dai-tdm-slot-tx-mask-0 = <1 1>; +- dai-tdm-slot-tx-mask-1 = <1 1>; +- dai-tdm-slot-tx-mask-2 = <1 1>; +- dai-tdm-slot-tx-mask-3 = <1 1>; +- mclk-fs = <256>; +- +- codec { +- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; +- }; +- }; +- +- /* hdmi glue */ +- dai-link-4 { +- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; +- +- codec { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +-}; +- +-&arb { +- status = "okay"; +-}; +- +-&clkc_audio { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu1 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU1_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu2 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU2_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu3 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU3_CLK>; +- clock-latency = <50000>; +-}; +- +-&ext_mdio { +- external_phy: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- max-speed = <1000>; +- +- reset-assert-us = <10000>; +- reset-deassert-us = <80000>; +- reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; +- +- interrupt-parent = <&gpio_intc>; +- /* MAC_INTR on GPIOZ_14 */ +- interrupts = <26 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-ðmac { +- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy-mode = "rgmii"; +- phy-handle = <&external_phy>; +- amlogic,tx-delay-ns = <2>; +-}; +- +-&frddr_a { +- status = "okay"; +-}; +- +-&frddr_b { +- status = "okay"; +-}; +- +-&frddr_c { +- status = "okay"; +-}; +- +-&gpio { +- gpio-line-names = +- /* GPIOZ */ +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- /* GPIOH */ +- "", "", "", "", "", +- "PIN_36", /* GPIOH_5 */ +- "PIN_26", /* GPIOH_6 */ +- "PIN_32", /* GPIOH_7 */ +- "", +- /* BOOT */ +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- /* GPIOC */ +- "", "", "", "", "", "", "", "", +- /* GPIOA */ +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", +- "PIN_27", /* GPIOA_14 */ +- "PIN_28", /* GPIOA_15 */ +- /* GPIOX */ +- "PIN_16", /* GPIOX_0 */ +- "PIN_18", /* GPIOX_1 */ +- "PIN_22", /* GPIOX_2 */ +- "PIN_11", /* GPIOX_3 */ +- "PIN_13", /* GPIOX_4 */ +- "PIN_7", /* GPIOX_5 */ +- "PIN_33", /* GPIOX_6 */ +- "PIN_15", /* GPIOX_7 */ +- "PIN_19", /* GPIOX_8 */ +- "PIN_21", /* GPIOX_9 */ +- "PIN_24", /* GPIOX_10 */ +- "PIN_23", /* GPIOX_11 */ +- "PIN_8", /* GPIOX_12 */ +- "PIN_10", /* GPIOX_13 */ +- "PIN_29", /* GPIOX_14 */ +- "PIN_31", /* GPIOX_15 */ +- "PIN_12", /* GPIOX_16 */ +- "PIN_3", /* GPIOX_17 */ +- "PIN_5", /* GPIOX_18 */ +- "PIN_35"; /* GPIOX_19 */ +-}; +- +-&gpio_ao { +- gpio-line-names = +- /* GPIOAO */ +- "", "", "", "", +- "PIN_47", /* GPIOAO_4 */ +- "", "", +- "PIN_45", /* GPIOAO_7 */ +- "PIN_46", /* GPIOAO_8 */ +- "PIN_44", /* GPIOAO_9 */ +- "PIN_42", /* GPIOAO_10 */ +- "", +- /* GPIOE */ +- "", "", ""; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; +- pinctrl-names = "default"; +- hdmi-supply = <&vcc_5v>; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&pwm_AO_cd { +- pinctrl-0 = <&pwm_ao_d_e_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>; +- clock-names = "clkin1"; +- status = "okay"; +-}; +- +-&saradc { +- status = "okay"; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_c_pins>; +- pinctrl-1 = <&sdcard_clk_gate_c_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <200000000>; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- disable-wp; +- +- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; +- vmmc-supply = <&tflash_vdd>; +- vqmmc-supply = <&tf_io>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- max-frequency = <200000000>; +- disable-wp; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&flash_1v8>; +-}; +- +-&tdmif_b { +- status = "okay"; +-}; +- +-&tdmout_b { +- status = "okay"; +-}; +- +-&tohdmitx { +- status = "okay"; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- status = "okay"; +- vbus-supply = <&usb_pwr_en>; +-}; +- +-&usb2_phy0 { +- phy-supply = <&vcc_5v>; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1-sei610.dts b/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1-sei610.dts +deleted file mode 100644 +index a5d79f2f7c19..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1-sei610.dts ++++ /dev/null +@@ -1,608 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre SAS. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "meson-sm1.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "seirobotics,sei610", "amlogic,sm1"; +- model = "SEI Robotics SEI610"; +- +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- mono_dac: audio-codec-0 { +- compatible = "maxim,max98357a"; +- #sound-dai-cells = <0>; +- sound-name-prefix = "U16"; +- sdmode-gpios = <&gpio GPIOX_8 GPIO_ACTIVE_HIGH>; +- }; +- +- dmics: audio-codec-1 { +- #sound-dai-cells = <0>; +- compatible = "dmic-codec"; +- num-channels = <2>; +- wakeup-delay-ms = <50>; +- status = "okay"; +- sound-name-prefix = "MIC"; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- key1 { +- label = "A"; +- linux,code = ; +- gpios = <&gpio GPIOH_6 GPIO_ACTIVE_LOW>; +- interrupt-parent = <&gpio_intc>; +- interrupts = <34 IRQ_TYPE_EDGE_BOTH>; +- }; +- +- key2 { +- label = "B"; +- linux,code = ; +- gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>; +- interrupt-parent = <&gpio_intc>; +- interrupts = <35 IRQ_TYPE_EDGE_BOTH>; +- }; +- +- key3 { +- label = "C"; +- linux,code = ; +- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; +- interrupt-parent = <&gpio_intc>; +- interrupts = <2 IRQ_TYPE_EDGE_BOTH>; +- }; +- +- mic_mute { +- label = "MicMute"; +- linux,code = ; +- linux,input-type = ; +- gpios = <&gpio_ao GPIOE_2 GPIO_ACTIVE_LOW>; +- interrupt-parent = <&gpio_intc>; +- interrupts = <99 IRQ_TYPE_EDGE_BOTH>; +- }; +- +- power_key { +- label = "PowerKey"; +- linux,code = ; +- gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; +- interrupt-parent = <&gpio_intc>; +- interrupts = <3 IRQ_TYPE_EDGE_BOTH>; +- }; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- +- led-controller-1 { +- compatible = "gpio-leds"; +- +- led-1 { +- label = "sei610:blue:bt"; +- gpios = <&gpio GPIOC_7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; +- default-state = "off"; +- }; +- }; +- +- led-controller-2 { +- compatible = "pwm-leds"; +- +- led-2 { +- label = "sei610:red:power"; +- pwms = <&pwm_AO_ab 0 30518 0>; +- max-brightness = <255>; +- linux,default-trigger = "default-on"; +- active-low; +- }; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x40000000>; +- }; +- +- ao_5v: regulator-ao_5v { +- compatible = "regulator-fixed"; +- regulator-name = "AO_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&dc_in>; +- regulator-always-on; +- }; +- +- dc_in: regulator-dc_in { +- compatible = "regulator-fixed"; +- regulator-name = "DC_IN"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- emmc_1v8: regulator-emmc_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "EMMC_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- }; +- +- vddao_3v3: regulator-vddao_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&dc_in>; +- regulator-always-on; +- }; +- +- /* Used by Tuner, RGB Led & IR Emitter LED array */ +- vddao_3v3_t: regulator-vddao_3v3_t { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3_T"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vddao_3v3>; +- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; +- enable-active-low; +- regulator-always-on; +- }; +- +- vddcpu: regulator-vddcpu { +- /* +- * SY8120B1ABC DC/DC Regulator. +- */ +- compatible = "pwm-regulator"; +- +- regulator-name = "VDDCPU"; +- regulator-min-microvolt = <690000>; +- regulator-max-microvolt = <1050000>; +- +- pwm-supply = <&dc_in>; +- +- pwms = <&pwm_AO_cd 1 1500 0>; +- pwm-dutycycle-range = <100 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vddio_ao1v8: regulator-vddio_ao1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDIO_AO1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; +- clocks = <&wifi32k>; +- clock-names = "ext_clock"; +- }; +- +- sound { +- compatible = "amlogic,axg-sound-card"; +- model = "SEI610"; +- audio-aux-devs = <&tdmout_a>, <&tdmout_b>, +- <&tdmin_a>, <&tdmin_b>; +- audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", +- "TDMOUT_A IN 1", "FRDDR_B OUT 0", +- "TDMOUT_A IN 2", "FRDDR_C OUT 0", +- "TDM_A Playback", "TDMOUT_A OUT", +- "TDMOUT_B IN 0", "FRDDR_A OUT 1", +- "TDMOUT_B IN 1", "FRDDR_B OUT 1", +- "TDMOUT_B IN 2", "FRDDR_C OUT 1", +- "TDM_B Playback", "TDMOUT_B OUT", +- "TODDR_A IN 4", "PDM Capture", +- "TODDR_B IN 4", "PDM Capture", +- "TODDR_C IN 4", "PDM Capture", +- "TDMIN_A IN 0", "TDM_A Capture", +- "TDMIN_A IN 3", "TDM_A Loopback", +- "TDMIN_B IN 0", "TDM_A Capture", +- "TDMIN_B IN 3", "TDM_A Loopback", +- "TDMIN_A IN 1", "TDM_B Capture", +- "TDMIN_A IN 4", "TDM_B Loopback", +- "TDMIN_B IN 1", "TDM_B Capture", +- "TDMIN_B IN 4", "TDM_B Loopback", +- "TODDR_A IN 0", "TDMIN_A OUT", +- "TODDR_B IN 0", "TDMIN_A OUT", +- "TODDR_C IN 0", "TDMIN_A OUT", +- "TODDR_A IN 1", "TDMIN_B OUT", +- "TODDR_B IN 1", "TDMIN_B OUT", +- "TODDR_C IN 1", "TDMIN_B OUT"; +- +- assigned-clocks = <&clkc CLKID_MPLL2>, +- <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&frddr_a>; +- }; +- +- dai-link-1 { +- sound-dai = <&frddr_b>; +- }; +- +- dai-link-2 { +- sound-dai = <&frddr_c>; +- }; +- +- dai-link-3 { +- sound-dai = <&toddr_a>; +- }; +- +- dai-link-4 { +- sound-dai = <&toddr_b>; +- }; +- +- dai-link-5 { +- sound-dai = <&toddr_c>; +- }; +- +- /* internal speaker interface */ +- dai-link-6 { +- sound-dai = <&tdmif_a>; +- dai-format = "i2s"; +- dai-tdm-slot-tx-mask-0 = <1 1>; +- mclk-fs = <256>; +- +- codec-0 { +- sound-dai = <&mono_dac>; +- }; +- +- codec-1 { +- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; +- }; +- }; +- +- /* 8ch hdmi interface */ +- dai-link-7 { +- sound-dai = <&tdmif_b>; +- dai-format = "i2s"; +- dai-tdm-slot-tx-mask-0 = <1 1>; +- dai-tdm-slot-tx-mask-1 = <1 1>; +- dai-tdm-slot-tx-mask-2 = <1 1>; +- dai-tdm-slot-tx-mask-3 = <1 1>; +- mclk-fs = <256>; +- +- codec { +- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; +- }; +- }; +- +- /* internal digital mics */ +- dai-link-8 { +- sound-dai = <&pdm>; +- +- codec { +- sound-dai = <&dmics>; +- }; +- }; +- +- /* hdmi glue */ +- dai-link-9 { +- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; +- +- codec { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +- +- wifi32k: wifi32k { +- compatible = "pwm-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ +- }; +-}; +- +-&arb { +- status = "okay"; +-}; +- +-&cec_AO { +- pinctrl-0 = <&cec_ao_a_h_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&cecb_AO { +- pinctrl-0 = <&cec_ao_b_h_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- hdmi-phandle = <&hdmi_tx>; +-}; +- +-&clkc_audio { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu1 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU1_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu2 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU2_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu3 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU3_CLK>; +- clock-latency = <50000>; +-}; +- +-ðmac { +- status = "okay"; +- phy-handle = <&internal_ephy>; +- phy-mode = "rmii"; +-}; +- +-&frddr_a { +- status = "okay"; +-}; +- +-&frddr_b { +- status = "okay"; +-}; +- +-&frddr_c { +- status = "okay"; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; +- pinctrl-names = "default"; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +- pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; +-}; +- +-&pdm { +- pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_dclk_z_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&pwm_AO_ab { +- status = "okay"; +- pinctrl-0 = <&pwm_ao_a_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>; +- clock-names = "clkin0"; +-}; +- +-&pwm_AO_cd { +- pinctrl-0 = <&pwm_ao_d_e_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>; +- clock-names = "clkin1"; +- status = "okay"; +-}; +- +-&pwm_ef { +- status = "okay"; +- pinctrl-0 = <&pwm_e_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>; +- clock-names = "clkin0"; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vddio_ao1v8>; +-}; +- +-/* SDIO */ +-&sd_emmc_a { +- status = "okay"; +- pinctrl-0 = <&sdio_pins>; +- pinctrl-1 = <&sdio_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- bus-width = <4>; +- cap-sd-highspeed; +- sd-uhs-sdr50; +- max-frequency = <100000000>; +- +- non-removable; +- disable-wp; +- +- /* WiFi firmware requires power to be kept while in suspend */ +- keep-power-in-suspend; +- +- mmc-pwrseq = <&sdio_pwrseq>; +- +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddio_ao1v8>; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_c_pins>; +- pinctrl-1 = <&sdcard_clk_gate_c_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <50000000>; +- disable-wp; +- +- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&vddao_3v3>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- max-frequency = <200000000>; +- non-removable; +- disable-wp; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vddao_3v3>; +- vqmmc-supply = <&emmc_1v8>; +-}; +- +-&tdmif_a { +- pinctrl-0 = <&tdm_a_dout0_pins>, <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD0>, +- <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD0>; +- assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_A_SCLK>, +- <&clkc_audio AUD_CLKID_MST_A_LRCLK>; +- assigned-clock-rates = <0>, <0>; +-}; +- +-&tdmif_b { +- status = "okay"; +-}; +- +-&tdmin_a { +- status = "okay"; +-}; +- +-&tdmin_b { +- status = "okay"; +-}; +- +-&tdmout_a { +- status = "okay"; +-}; +- +-&tdmout_b { +- status = "okay"; +-}; +- +-&toddr_a { +- status = "okay"; +-}; +- +-&toddr_b { +- status = "okay"; +-}; +- +-&toddr_c { +- status = "okay"; +-}; +- +-&tohdmitx { +- status = "okay"; +-}; +- +-&uart_A { +- status = "okay"; +- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- interrupt-parent = <&gpio_intc>; +- interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "host-wakeup"; +- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; +- max-speed = <2000000>; +- clocks = <&wifi32k>; +- clock-names = "lpo"; +- vbat-supply = <&vddao_3v3>; +- vddio-supply = <&vddio_ao1v8>; +- }; +-}; +- +-/* Exposed via the on-board USB to Serial FT232RL IC */ +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- status = "okay"; +- dr_mode = "otg"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1.dtsi b/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1.dtsi +deleted file mode 100644 +index 3d8b1f4f2001..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/amlogic/meson-sm1.dtsi ++++ /dev/null +@@ -1,538 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- */ +- +-#include "meson-g12-common.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "amlogic,sm1"; +- +- tdmif_a: audio-controller-0 { +- compatible = "amlogic,axg-tdm-iface"; +- #sound-dai-cells = <0>; +- sound-name-prefix = "TDM_A"; +- clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, +- <&clkc_audio AUD_CLKID_MST_A_SCLK>, +- <&clkc_audio AUD_CLKID_MST_A_LRCLK>; +- clock-names = "mclk", "sclk", "lrclk"; +- status = "disabled"; +- }; +- +- tdmif_b: audio-controller-1 { +- compatible = "amlogic,axg-tdm-iface"; +- #sound-dai-cells = <0>; +- sound-name-prefix = "TDM_B"; +- clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, +- <&clkc_audio AUD_CLKID_MST_B_SCLK>, +- <&clkc_audio AUD_CLKID_MST_B_LRCLK>; +- clock-names = "mclk", "sclk", "lrclk"; +- status = "disabled"; +- }; +- +- tdmif_c: audio-controller-2 { +- compatible = "amlogic,axg-tdm-iface"; +- #sound-dai-cells = <0>; +- sound-name-prefix = "TDM_C"; +- clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, +- <&clkc_audio AUD_CLKID_MST_C_SCLK>, +- <&clkc_audio AUD_CLKID_MST_C_LRCLK>; +- clock-names = "mclk", "sclk", "lrclk"; +- status = "disabled"; +- }; +- +- cpus { +- #address-cells = <0x2>; +- #size-cells = <0x0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- #cooling-cells = <2>; +- }; +- +- l2: l2-cache0 { +- compatible = "cache"; +- }; +- }; +- +- cpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- opp-microvolt = <730000>; +- }; +- +- opp-250000000 { +- opp-hz = /bits/ 64 <250000000>; +- opp-microvolt = <730000>; +- }; +- +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <730000>; +- }; +- +- opp-667000000 { +- opp-hz = /bits/ 64 <666666666>; +- opp-microvolt = <750000>; +- }; +- +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <770000>; +- }; +- +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <780000>; +- }; +- +- opp-1404000000 { +- opp-hz = /bits/ 64 <1404000000>; +- opp-microvolt = <790000>; +- }; +- +- opp-1500000000 { +- opp-hz = /bits/ 64 <1500000000>; +- opp-microvolt = <800000>; +- }; +- +- opp-1608000000 { +- opp-hz = /bits/ 64 <1608000000>; +- opp-microvolt = <810000>; +- }; +- +- opp-1704000000 { +- opp-hz = /bits/ 64 <1704000000>; +- opp-microvolt = <850000>; +- }; +- +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <900000>; +- }; +- +- opp-1908000000 { +- opp-hz = /bits/ 64 <1908000000>; +- opp-microvolt = <950000>; +- }; +- }; +-}; +- +-&apb { +- audio: bus@60000 { +- compatible = "simple-bus"; +- reg = <0x0 0x60000 0x0 0x1000>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0x60000 0x0 0x1000>; +- +- clkc_audio: clock-controller@0 { +- status = "disabled"; +- compatible = "amlogic,sm1-audio-clkc"; +- reg = <0x0 0x0 0x0 0xb4>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- +- clocks = <&clkc CLKID_AUDIO>, +- <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>, +- <&clkc CLKID_MPLL2>, +- <&clkc CLKID_MPLL3>, +- <&clkc CLKID_HIFI_PLL>, +- <&clkc CLKID_FCLK_DIV3>, +- <&clkc CLKID_FCLK_DIV4>, +- <&clkc CLKID_FCLK_DIV5>; +- clock-names = "pclk", +- "mst_in0", +- "mst_in1", +- "mst_in2", +- "mst_in3", +- "mst_in4", +- "mst_in5", +- "mst_in6", +- "mst_in7"; +- +- resets = <&reset RESET_AUDIO>; +- }; +- +- toddr_a: audio-controller@100 { +- compatible = "amlogic,sm1-toddr", +- "amlogic,axg-toddr"; +- reg = <0x0 0x100 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "TODDR_A"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_TODDR_A>; +- resets = <&arb AXG_ARB_TODDR_A>, +- <&clkc_audio AUD_RESET_TODDR_A>; +- reset-names = "arb", "rst"; +- amlogic,fifo-depth = <8192>; +- status = "disabled"; +- }; +- +- toddr_b: audio-controller@140 { +- compatible = "amlogic,sm1-toddr", +- "amlogic,axg-toddr"; +- reg = <0x0 0x140 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "TODDR_B"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_TODDR_B>; +- resets = <&arb AXG_ARB_TODDR_B>, +- <&clkc_audio AUD_RESET_TODDR_B>; +- reset-names = "arb", "rst"; +- amlogic,fifo-depth = <256>; +- status = "disabled"; +- }; +- +- toddr_c: audio-controller@180 { +- compatible = "amlogic,sm1-toddr", +- "amlogic,axg-toddr"; +- reg = <0x0 0x180 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "TODDR_C"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_TODDR_C>; +- resets = <&arb AXG_ARB_TODDR_C>, +- <&clkc_audio AUD_RESET_TODDR_C>; +- reset-names = "arb", "rst"; +- amlogic,fifo-depth = <256>; +- status = "disabled"; +- }; +- +- frddr_a: audio-controller@1c0 { +- compatible = "amlogic,sm1-frddr", +- "amlogic,axg-frddr"; +- reg = <0x0 0x1c0 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "FRDDR_A"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; +- resets = <&arb AXG_ARB_FRDDR_A>, +- <&clkc_audio AUD_RESET_FRDDR_A>; +- reset-names = "arb", "rst"; +- amlogic,fifo-depth = <512>; +- status = "disabled"; +- }; +- +- frddr_b: audio-controller@200 { +- compatible = "amlogic,sm1-frddr", +- "amlogic,axg-frddr"; +- reg = <0x0 0x200 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "FRDDR_B"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; +- resets = <&arb AXG_ARB_FRDDR_B>, +- <&clkc_audio AUD_RESET_FRDDR_B>; +- reset-names = "arb", "rst"; +- amlogic,fifo-depth = <256>; +- status = "disabled"; +- }; +- +- frddr_c: audio-controller@240 { +- compatible = "amlogic,sm1-frddr", +- "amlogic,axg-frddr"; +- reg = <0x0 0x240 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "FRDDR_C"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; +- resets = <&arb AXG_ARB_FRDDR_C>, +- <&clkc_audio AUD_RESET_FRDDR_C>; +- reset-names = "arb", "rst"; +- amlogic,fifo-depth = <256>; +- status = "disabled"; +- }; +- +- arb: reset-controller@280 { +- status = "disabled"; +- compatible = "amlogic,meson-sm1-audio-arb"; +- reg = <0x0 0x280 0x0 0x4>; +- #reset-cells = <1>; +- clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; +- }; +- +- tdmin_a: audio-controller@300 { +- compatible = "amlogic,sm1-tdmin", +- "amlogic,axg-tdmin"; +- reg = <0x0 0x300 0x0 0x40>; +- sound-name-prefix = "TDMIN_A"; +- resets = <&clkc_audio AUD_RESET_TDMIN_A>; +- clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, +- <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- tdmin_b: audio-controller@340 { +- compatible = "amlogic,sm1-tdmin", +- "amlogic,axg-tdmin"; +- reg = <0x0 0x340 0x0 0x40>; +- sound-name-prefix = "TDMIN_B"; +- resets = <&clkc_audio AUD_RESET_TDMIN_B>; +- clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, +- <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- tdmin_c: audio-controller@380 { +- compatible = "amlogic,sm1-tdmin", +- "amlogic,axg-tdmin"; +- reg = <0x0 0x380 0x0 0x40>; +- sound-name-prefix = "TDMIN_C"; +- resets = <&clkc_audio AUD_RESET_TDMIN_C>; +- clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, +- <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- tdmin_lb: audio-controller@3c0 { +- compatible = "amlogic,sm1-tdmin", +- "amlogic,axg-tdmin"; +- reg = <0x0 0x3c0 0x0 0x40>; +- sound-name-prefix = "TDMIN_LB"; +- resets = <&clkc_audio AUD_RESET_TDMIN_LB>; +- clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, +- <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- tdmout_a: audio-controller@500 { +- compatible = "amlogic,sm1-tdmout"; +- reg = <0x0 0x500 0x0 0x40>; +- sound-name-prefix = "TDMOUT_A"; +- resets = <&clkc_audio AUD_RESET_TDMOUT_A>; +- clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, +- <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, +- <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- tdmout_b: audio-controller@540 { +- compatible = "amlogic,sm1-tdmout"; +- reg = <0x0 0x540 0x0 0x40>; +- sound-name-prefix = "TDMOUT_B"; +- resets = <&clkc_audio AUD_RESET_TDMOUT_B>; +- clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, +- <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, +- <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- tdmout_c: audio-controller@580 { +- compatible = "amlogic,sm1-tdmout"; +- reg = <0x0 0x580 0x0 0x40>; +- sound-name-prefix = "TDMOUT_C"; +- resets = <&clkc_audio AUD_RESET_TDMOUT_C>; +- clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, +- <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, +- <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, +- <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, +- <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; +- clock-names = "pclk", "sclk", "sclk_sel", +- "lrclk", "lrclk_sel"; +- status = "disabled"; +- }; +- +- toacodec: audio-controller@740 { +- compatible = "amlogic,sm1-toacodec", +- "amlogic,g12a-toacodec"; +- reg = <0x0 0x740 0x0 0x4>; +- #sound-dai-cells = <1>; +- sound-name-prefix = "TOACODEC"; +- resets = <&clkc_audio AUD_RESET_TOACODEC>; +- status = "disabled"; +- }; +- +- tohdmitx: audio-controller@744 { +- compatible = "amlogic,sm1-tohdmitx", +- "amlogic,g12a-tohdmitx"; +- reg = <0x0 0x744 0x0 0x4>; +- #sound-dai-cells = <1>; +- sound-name-prefix = "TOHDMITX"; +- resets = <&clkc_audio AUD_RESET_TOHDMITX>; +- status = "disabled"; +- }; +- +- toddr_d: audio-controller@840 { +- compatible = "amlogic,sm1-toddr", +- "amlogic,axg-toddr"; +- reg = <0x0 0x840 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "TODDR_D"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_TODDR_D>; +- resets = <&arb AXG_ARB_TODDR_D>, +- <&clkc_audio AUD_RESET_TODDR_D>; +- reset-names = "arb", "rst"; +- amlogic,fifo-depth = <256>; +- status = "disabled"; +- }; +- +- frddr_d: audio-controller@880 { +- compatible = "amlogic,sm1-frddr", +- "amlogic,axg-frddr"; +- reg = <0x0 0x880 0x0 0x2c>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "FRDDR_D"; +- interrupts = ; +- clocks = <&clkc_audio AUD_CLKID_FRDDR_D>; +- resets = <&arb AXG_ARB_FRDDR_D>, +- <&clkc_audio AUD_RESET_FRDDR_D>; +- reset-names = "arb", "rst"; +- amlogic,fifo-depth = <256>; +- status = "disabled"; +- }; +- }; +- +- pdm: audio-controller@61000 { +- compatible = "amlogic,sm1-pdm", +- "amlogic,axg-pdm"; +- reg = <0x0 0x61000 0x0 0x34>; +- #sound-dai-cells = <0>; +- sound-name-prefix = "PDM"; +- clocks = <&clkc_audio AUD_CLKID_PDM>, +- <&clkc_audio AUD_CLKID_PDM_DCLK>, +- <&clkc_audio AUD_CLKID_PDM_SYSCLK>; +- clock-names = "pclk", "dclk", "sysclk"; +- resets = <&clkc_audio AUD_RESET_PDM>; +- status = "disabled"; +- }; +-}; +- +-&cecb_AO { +- compatible = "amlogic,meson-sm1-ao-cec"; +-}; +- +-&clk_msr { +- compatible = "amlogic,meson-sm1-clk-measure"; +-}; +- +- +-&clkc { +- compatible = "amlogic,sm1-clkc"; +-}; +- +-&cpu_thermal { +- cooling-maps { +- map0 { +- trip = <&cpu_passive>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- +- map1 { +- trip = <&cpu_hot>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +-}; +- +-ðmac { +- power-domains = <&pwrc PWRC_SM1_ETH_ID>; +-}; +- +-&gpio_intc { +- compatible = "amlogic,meson-sm1-gpio-intc", +- "amlogic,meson-gpio-intc"; +-}; +- +-&pcie { +- power-domains = <&pwrc PWRC_SM1_PCIE_ID>; +-}; +- +-&pwrc { +- compatible = "amlogic,meson-sm1-pwrc"; +-}; +- +-&simplefb_cvbs { +- power-domains = <&pwrc PWRC_SM1_VPU_ID>; +-}; +- +-&simplefb_hdmi { +- power-domains = <&pwrc PWRC_SM1_VPU_ID>; +-}; +- +-&vdec { +- compatible = "amlogic,sm1-vdec"; +-}; +- +-&vpu { +- power-domains = <&pwrc PWRC_SM1_VPU_ID>; +-}; +- +-&usb { +- power-domains = <&pwrc PWRC_SM1_USB_ID>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/apm/Makefile b/scripts/dtc/include-prefixes/arm64/apm/Makefile +deleted file mode 100644 +index 55b5cdca13b8..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/apm/Makefile ++++ /dev/null +@@ -1,3 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb +-dtb-$(CONFIG_ARCH_XGENE) += apm-merlin.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/apm/apm-merlin.dts b/scripts/dtc/include-prefixes/arm64/apm/apm-merlin.dts +deleted file mode 100644 +index 217d7728b63a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/apm/apm-merlin.dts ++++ /dev/null +@@ -1,87 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * dts file for AppliedMicro (APM) Merlin Board +- * +- * Copyright (C) 2015, Applied Micro Circuits Corporation +- */ +- +-/dts-v1/; +- +-/include/ "apm-shadowcat.dtsi" +- +-/ { +- model = "APM X-Gene Merlin board"; +- compatible = "apm,merlin", "apm,xgene-shadowcat"; +- +- chosen { }; +- +- memory { +- device_type = "memory"; +- reg = < 0x1 0x00000000 0x0 0x80000000 >; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- button@1 { +- label = "POWER"; +- linux,code = <116>; +- linux,input-type = <0x1>; +- interrupt-parent = <&sbgpio>; +- interrupts = <0x0 0x1>; +- }; +- }; +- +- poweroff_mbox: poweroff_mbox@10548000 { +- compatible = "syscon"; +- reg = <0x0 0x10548000 0x0 0x30>; +- }; +- +- poweroff: poweroff@10548010 { +- compatible = "syscon-poweroff"; +- regmap = <&poweroff_mbox>; +- offset = <0x10>; +- mask = <0x1>; +- }; +-}; +- +-&serial0 { +- status = "ok"; +-}; +- +-&sata1 { +- status = "ok"; +-}; +- +-&sata2 { +- status = "ok"; +-}; +- +-&sata3 { +- status = "ok"; +-}; +- +-&sgenet0 { +- status = "ok"; +-}; +- +-&xgenet1 { +- status = "ok"; +-}; +- +-&mmc0 { +- status = "ok"; +-}; +- +-&i2c4 { +- rtc68: rtc@68 { +- compatible = "dallas,ds1337"; +- reg = <0x68>; +- status = "ok"; +- }; +-}; +- +-&mdio { +- sgenet0phy: phy@0 { +- reg = <0x0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/apm/apm-mustang.dts b/scripts/dtc/include-prefixes/arm64/apm/apm-mustang.dts +deleted file mode 100644 +index e927811ade28..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/apm/apm-mustang.dts ++++ /dev/null +@@ -1,90 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * dts file for AppliedMicro (APM) Mustang Board +- * +- * Copyright (C) 2013, Applied Micro Circuits Corporation +- */ +- +-/dts-v1/; +- +-/include/ "apm-storm.dtsi" +- +-/ { +- model = "APM X-Gene Mustang board"; +- compatible = "apm,mustang", "apm,xgene-storm"; +- +- chosen { }; +- +- memory { +- device_type = "memory"; +- reg = < 0x1 0x00000000 0x0 0x80000000 >; /* Updated by bootloader */ +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- button@1 { +- label = "POWER"; +- linux,code = <116>; +- linux,input-type = <0x1>; +- interrupt-parent = <&sbgpio>; +- interrupts = <0x5 0x1>; +- }; +- }; +- +- poweroff_mbox: poweroff_mbox@10548000 { +- compatible = "syscon"; +- reg = <0x0 0x10548000 0x0 0x30>; +- }; +- +- poweroff: poweroff@10548010 { +- compatible = "syscon-poweroff"; +- regmap = <&poweroff_mbox>; +- offset = <0x10>; +- mask = <0x1>; +- }; +-}; +- +-&pcie0clk { +- status = "ok"; +-}; +- +-&pcie0 { +- status = "ok"; +-}; +- +-&serial0 { +- status = "ok"; +-}; +- +-&menet { +- status = "ok"; +-}; +- +-&sgenet0 { +- status = "ok"; +-}; +- +-&sgenet1 { +- status = "ok"; +-}; +- +-&xgenet { +- status = "ok"; +- rxlos-gpios = <&sbgpio 12 1>; +-}; +- +-&mmc0 { +- status = "ok"; +-}; +- +-&mdio { +- menet0phy: phy@3 { +- reg = <0x3>; +- }; +- sgenet0phy: phy@4 { +- reg = <0x4>; +- }; +- sgenet1phy: phy@5 { +- reg = <0x5>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/apm/apm-shadowcat.dtsi b/scripts/dtc/include-prefixes/arm64/apm/apm-shadowcat.dtsi +deleted file mode 100644 +index a83c82c50e29..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/apm/apm-shadowcat.dtsi ++++ /dev/null +@@ -1,818 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC +- * +- * Copyright (C) 2015, Applied Micro Circuits Corporation +- */ +- +-/ { +- compatible = "apm,xgene-shadowcat"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "apm,strega"; +- reg = <0x0 0x000>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x1 0x0000fff8>; +- next-level-cache = <&xgene_L2_0>; +- #clock-cells = <1>; +- clocks = <&pmd0clk 0>; +- }; +- cpu@1 { +- device_type = "cpu"; +- compatible = "apm,strega"; +- reg = <0x0 0x001>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x1 0x0000fff8>; +- next-level-cache = <&xgene_L2_0>; +- #clock-cells = <1>; +- clocks = <&pmd0clk 0>; +- }; +- cpu@100 { +- device_type = "cpu"; +- compatible = "apm,strega"; +- reg = <0x0 0x100>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x1 0x0000fff8>; +- next-level-cache = <&xgene_L2_1>; +- #clock-cells = <1>; +- clocks = <&pmd1clk 0>; +- }; +- cpu@101 { +- device_type = "cpu"; +- compatible = "apm,strega"; +- reg = <0x0 0x101>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x1 0x0000fff8>; +- next-level-cache = <&xgene_L2_1>; +- #clock-cells = <1>; +- clocks = <&pmd1clk 0>; +- }; +- cpu@200 { +- device_type = "cpu"; +- compatible = "apm,strega"; +- reg = <0x0 0x200>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x1 0x0000fff8>; +- next-level-cache = <&xgene_L2_2>; +- #clock-cells = <1>; +- clocks = <&pmd2clk 0>; +- }; +- cpu@201 { +- device_type = "cpu"; +- compatible = "apm,strega"; +- reg = <0x0 0x201>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x1 0x0000fff8>; +- next-level-cache = <&xgene_L2_2>; +- #clock-cells = <1>; +- clocks = <&pmd2clk 0>; +- }; +- cpu@300 { +- device_type = "cpu"; +- compatible = "apm,strega"; +- reg = <0x0 0x300>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x1 0x0000fff8>; +- next-level-cache = <&xgene_L2_3>; +- #clock-cells = <1>; +- clocks = <&pmd3clk 0>; +- }; +- cpu@301 { +- device_type = "cpu"; +- compatible = "apm,strega"; +- reg = <0x0 0x301>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x1 0x0000fff8>; +- next-level-cache = <&xgene_L2_3>; +- #clock-cells = <1>; +- clocks = <&pmd3clk 0>; +- }; +- xgene_L2_0: l2-cache-0 { +- compatible = "cache"; +- }; +- xgene_L2_1: l2-cache-1 { +- compatible = "cache"; +- }; +- xgene_L2_2: l2-cache-2 { +- compatible = "cache"; +- }; +- xgene_L2_3: l2-cache-3 { +- compatible = "cache"; +- }; +- }; +- +- gic: interrupt-controller@78090000 { +- compatible = "arm,cortex-a15-gic"; +- #interrupt-cells = <3>; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-controller; +- interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ +- ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */ +- reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */ +- <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */ +- <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */ +- <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */ +- v2m0: v2m@0 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x0 0x0 0x0 0x1000>; +- }; +- v2m1: v2m@10000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x0 0x10000 0x0 0x1000>; +- }; +- v2m2: v2m@20000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x0 0x20000 0x0 0x1000>; +- }; +- v2m3: v2m@30000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x0 0x30000 0x0 0x1000>; +- }; +- v2m4: v2m@40000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x0 0x40000 0x0 0x1000>; +- }; +- v2m5: v2m@50000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x0 0x50000 0x0 0x1000>; +- }; +- v2m6: v2m@60000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x0 0x60000 0x0 0x1000>; +- }; +- v2m7: v2m@70000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x0 0x70000 0x0 0x1000>; +- }; +- v2m8: v2m@80000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x0 0x80000 0x0 0x1000>; +- }; +- v2m9: v2m@90000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x0 0x90000 0x0 0x1000>; +- }; +- v2m10: v2m@a0000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x0 0xa0000 0x0 0x1000>; +- }; +- v2m11: v2m@b0000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x0 0xb0000 0x0 0x1000>; +- }; +- v2m12: v2m@c0000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x0 0xc0000 0x0 0x1000>; +- }; +- v2m13: v2m@d0000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x0 0xd0000 0x0 0x1000>; +- }; +- v2m14: v2m@e0000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x0 0xe0000 0x0 0x1000>; +- }; +- v2m15: v2m@f0000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x0 0xf0000 0x0 0x1000>; +- }; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = <1 12 0xff04>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ +- <1 13 0xff08>, /* Non-secure Phys IRQ */ +- <1 14 0xff08>, /* Virt IRQ */ +- <1 15 0xff08>; /* Hyp IRQ */ +- clock-frequency = <50000000>; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clocks { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- refclk: refclk { +- compatible = "fixed-clock"; +- #clock-cells = <1>; +- clock-frequency = <100000000>; +- clock-output-names = "refclk"; +- }; +- +- pmdpll: pmdpll@170000f0 { +- compatible = "apm,xgene-pcppll-v2-clock"; +- #clock-cells = <1>; +- clocks = <&refclk 0>; +- reg = <0x0 0x170000f0 0x0 0x10>; +- clock-output-names = "pmdpll"; +- }; +- +- pmd0clk: pmd0clk@7e200200 { +- compatible = "apm,xgene-pmd-clock"; +- #clock-cells = <1>; +- clocks = <&pmdpll 0>; +- reg = <0x0 0x7e200200 0x0 0x10>; +- clock-output-names = "pmd0clk"; +- }; +- +- pmd1clk: pmd1clk@7e200210 { +- compatible = "apm,xgene-pmd-clock"; +- #clock-cells = <1>; +- clocks = <&pmdpll 0>; +- reg = <0x0 0x7e200210 0x0 0x10>; +- clock-output-names = "pmd1clk"; +- }; +- +- pmd2clk: pmd2clk@7e200220 { +- compatible = "apm,xgene-pmd-clock"; +- #clock-cells = <1>; +- clocks = <&pmdpll 0>; +- reg = <0x0 0x7e200220 0x0 0x10>; +- clock-output-names = "pmd2clk"; +- }; +- +- pmd3clk: pmd3clk@7e200230 { +- compatible = "apm,xgene-pmd-clock"; +- #clock-cells = <1>; +- clocks = <&pmdpll 0>; +- reg = <0x0 0x7e200230 0x0 0x10>; +- clock-output-names = "pmd3clk"; +- }; +- +- socpll: socpll@17000120 { +- compatible = "apm,xgene-socpll-v2-clock"; +- #clock-cells = <1>; +- clocks = <&refclk 0>; +- reg = <0x0 0x17000120 0x0 0x1000>; +- clock-output-names = "socpll"; +- }; +- +- socplldiv2: socplldiv2 { +- compatible = "fixed-factor-clock"; +- #clock-cells = <1>; +- clocks = <&socpll 0>; +- clock-mult = <1>; +- clock-div = <2>; +- clock-output-names = "socplldiv2"; +- }; +- +- ahbclk: ahbclk@17000000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x17000000 0x0 0x2000>; +- reg-names = "div-reg"; +- divider-offset = <0x164>; +- divider-width = <0x5>; +- divider-shift = <0x0>; +- clock-output-names = "ahbclk"; +- }; +- +- sbapbclk: sbapbclk@1704c000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&ahbclk 0>; +- reg = <0x0 0x1704c000 0x0 0x2000>; +- reg-names = "div-reg"; +- divider-offset = <0x10>; +- divider-width = <0x2>; +- divider-shift = <0x0>; +- clock-output-names = "sbapbclk"; +- }; +- +- sdioclk: sdioclk@1f2ac000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f2ac000 0x0 0x1000 +- 0x0 0x17000000 0x0 0x2000>; +- reg-names = "csr-reg", "div-reg"; +- csr-offset = <0x0>; +- csr-mask = <0x2>; +- enable-offset = <0x8>; +- enable-mask = <0x2>; +- divider-offset = <0x178>; +- divider-width = <0x8>; +- divider-shift = <0x0>; +- clock-output-names = "sdioclk"; +- }; +- +- pcie0clk: pcie0clk@1f2bc000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f2bc000 0x0 0x1000>; +- reg-names = "csr-reg"; +- clock-output-names = "pcie0clk"; +- }; +- +- pcie1clk: pcie1clk@1f2cc000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f2cc000 0x0 0x1000>; +- reg-names = "csr-reg"; +- clock-output-names = "pcie1clk"; +- }; +- +- xge0clk: xge0clk@1f61c000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f61c000 0x0 0x1000>; +- reg-names = "csr-reg"; +- enable-mask = <0x3>; +- csr-mask = <0x3>; +- clock-output-names = "xge0clk"; +- }; +- +- xge1clk: xge1clk@1f62c000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f62c000 0x0 0x1000>; +- reg-names = "csr-reg"; +- enable-mask = <0x3>; +- csr-mask = <0x3>; +- clock-output-names = "xge1clk"; +- }; +- +- rngpkaclk: rngpkaclk@17000000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x17000000 0x0 0x2000>; +- reg-names = "csr-reg"; +- csr-offset = <0xc>; +- csr-mask = <0x10>; +- enable-offset = <0x10>; +- enable-mask = <0x10>; +- clock-output-names = "rngpkaclk"; +- }; +- +- i2c4clk: i2c4clk@1704c000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&sbapbclk 0>; +- reg = <0x0 0x1704c000 0x0 0x1000>; +- reg-names = "csr-reg"; +- csr-offset = <0x0>; +- csr-mask = <0x40>; +- enable-offset = <0x8>; +- enable-mask = <0x40>; +- clock-output-names = "i2c4clk"; +- }; +- }; +- +- scu: system-clk-controller@17000000 { +- compatible = "apm,xgene-scu","syscon"; +- reg = <0x0 0x17000000 0x0 0x400>; +- }; +- +- reboot: reboot@17000014 { +- compatible = "syscon-reboot"; +- regmap = <&scu>; +- offset = <0x14>; +- mask = <0x1>; +- }; +- +- csw: csw@7e200000 { +- compatible = "apm,xgene-csw", "syscon"; +- reg = <0x0 0x7e200000 0x0 0x1000>; +- }; +- +- mcba: mcba@7e700000 { +- compatible = "apm,xgene-mcb", "syscon"; +- reg = <0x0 0x7e700000 0x0 0x1000>; +- }; +- +- mcbb: mcbb@7e720000 { +- compatible = "apm,xgene-mcb", "syscon"; +- reg = <0x0 0x7e720000 0x0 0x1000>; +- }; +- +- efuse: efuse@1054a000 { +- compatible = "apm,xgene-efuse", "syscon"; +- reg = <0x0 0x1054a000 0x0 0x20>; +- }; +- +- edac@78800000 { +- compatible = "apm,xgene-edac"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- regmap-csw = <&csw>; +- regmap-mcba = <&mcba>; +- regmap-mcbb = <&mcbb>; +- regmap-efuse = <&efuse>; +- reg = <0x0 0x78800000 0x0 0x100>; +- interrupts = <0x0 0x20 0x4>, +- <0x0 0x21 0x4>, +- <0x0 0x27 0x4>; +- +- edacmc@7e800000 { +- compatible = "apm,xgene-edac-mc"; +- reg = <0x0 0x7e800000 0x0 0x1000>; +- memory-controller = <0>; +- }; +- +- edacmc@7e840000 { +- compatible = "apm,xgene-edac-mc"; +- reg = <0x0 0x7e840000 0x0 0x1000>; +- memory-controller = <1>; +- }; +- +- edacmc@7e880000 { +- compatible = "apm,xgene-edac-mc"; +- reg = <0x0 0x7e880000 0x0 0x1000>; +- memory-controller = <2>; +- }; +- +- edacmc@7e8c0000 { +- compatible = "apm,xgene-edac-mc"; +- reg = <0x0 0x7e8c0000 0x0 0x1000>; +- memory-controller = <3>; +- }; +- +- edacpmd@7c000000 { +- compatible = "apm,xgene-edac-pmd"; +- reg = <0x0 0x7c000000 0x0 0x200000>; +- pmd-controller = <0>; +- }; +- +- edacpmd@7c200000 { +- compatible = "apm,xgene-edac-pmd"; +- reg = <0x0 0x7c200000 0x0 0x200000>; +- pmd-controller = <1>; +- }; +- +- edacpmd@7c400000 { +- compatible = "apm,xgene-edac-pmd"; +- reg = <0x0 0x7c400000 0x0 0x200000>; +- pmd-controller = <2>; +- }; +- +- edacpmd@7c600000 { +- compatible = "apm,xgene-edac-pmd"; +- reg = <0x0 0x7c600000 0x0 0x200000>; +- pmd-controller = <3>; +- }; +- +- edacl3@7e600000 { +- compatible = "apm,xgene-edac-l3-v2"; +- reg = <0x0 0x7e600000 0x0 0x1000>; +- }; +- +- edacsoc@7e930000 { +- compatible = "apm,xgene-edac-soc"; +- reg = <0x0 0x7e930000 0x0 0x1000>; +- }; +- }; +- +- pmu: pmu@78810000 { +- compatible = "apm,xgene-pmu-v2"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- regmap-csw = <&csw>; +- regmap-mcba = <&mcba>; +- regmap-mcbb = <&mcbb>; +- reg = <0x0 0x78810000 0x0 0x1000>; +- interrupts = <0x0 0x22 0x4>; +- +- pmul3c@7e610000 { +- compatible = "apm,xgene-pmu-l3c"; +- reg = <0x0 0x7e610000 0x0 0x1000>; +- }; +- +- pmuiob@7e940000 { +- compatible = "apm,xgene-pmu-iob"; +- reg = <0x0 0x7e940000 0x0 0x1000>; +- }; +- +- pmucmcb@7e710000 { +- compatible = "apm,xgene-pmu-mcb"; +- reg = <0x0 0x7e710000 0x0 0x1000>; +- enable-bit-index = <0>; +- }; +- +- pmucmcb@7e730000 { +- compatible = "apm,xgene-pmu-mcb"; +- reg = <0x0 0x7e730000 0x0 0x1000>; +- enable-bit-index = <1>; +- }; +- +- pmucmc@7e810000 { +- compatible = "apm,xgene-pmu-mc"; +- reg = <0x0 0x7e810000 0x0 0x1000>; +- enable-bit-index = <0>; +- }; +- +- pmucmc@7e850000 { +- compatible = "apm,xgene-pmu-mc"; +- reg = <0x0 0x7e850000 0x0 0x1000>; +- enable-bit-index = <1>; +- }; +- +- pmucmc@7e890000 { +- compatible = "apm,xgene-pmu-mc"; +- reg = <0x0 0x7e890000 0x0 0x1000>; +- enable-bit-index = <2>; +- }; +- +- pmucmc@7e8d0000 { +- compatible = "apm,xgene-pmu-mc"; +- reg = <0x0 0x7e8d0000 0x0 0x1000>; +- enable-bit-index = <3>; +- }; +- }; +- +- mailbox: mailbox@10540000 { +- compatible = "apm,xgene-slimpro-mbox"; +- reg = <0x0 0x10540000 0x0 0x8000>; +- #mbox-cells = <1>; +- interrupts = <0x0 0x0 0x4 +- 0x0 0x1 0x4 +- 0x0 0x2 0x4 +- 0x0 0x3 0x4 +- 0x0 0x4 0x4 +- 0x0 0x5 0x4 +- 0x0 0x6 0x4 +- 0x0 0x7 0x4>; +- }; +- +- i2cslimpro { +- compatible = "apm,xgene-slimpro-i2c"; +- mboxes = <&mailbox 0>; +- }; +- +- hwmonslimpro { +- compatible = "apm,xgene-slimpro-hwmon"; +- mboxes = <&mailbox 7>; +- }; +- +- serial0: serial@10600000 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0 0x10600000 0x0 0x1000>; +- reg-shift = <2>; +- clock-frequency = <10000000>; +- interrupt-parent = <&gic>; +- interrupts = <0x0 0x4c 0x4>; +- }; +- +- /* Do not change dwusb name, coded for backward compatibility */ +- usb0: dwusb@19000000 { +- status = "disabled"; +- compatible = "snps,dwc3"; +- reg = <0x0 0x19000000 0x0 0x100000>; +- interrupts = <0x0 0x5d 0x4>; +- dma-coherent; +- dr_mode = "host"; +- }; +- +- pcie0: pcie@1f2b0000 { +- status = "disabled"; +- device_type = "pci"; +- compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ +- 0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */ +- reg-names = "csr", "cfg"; +- ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ +- 0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */ +- 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */ +- dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 +- 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4 +- 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4 +- 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x4 +- 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x4>; +- dma-coherent; +- clocks = <&pcie0clk 0>; +- msi-parent = <&v2m0>; +- }; +- +- pcie1: pcie@1f2c0000 { +- status = "disabled"; +- device_type = "pci"; +- compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ +- 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ +- reg-names = "csr", "cfg"; +- ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ +- 0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */ +- 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ +- dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 +- 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4 +- 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4 +- 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x4 +- 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x4>; +- dma-coherent; +- clocks = <&pcie1clk 0>; +- msi-parent = <&v2m0>; +- }; +- +- sata1: sata@1a000000 { +- compatible = "apm,xgene-ahci-v2"; +- reg = <0x0 0x1a000000 0x0 0x1000>, +- <0x0 0x1f200000 0x0 0x1000>, +- <0x0 0x1f20d000 0x0 0x1000>, +- <0x0 0x1f20e000 0x0 0x1000>; +- interrupts = <0x0 0x5a 0x4>; +- dma-coherent; +- }; +- +- sata2: sata@1a200000 { +- compatible = "apm,xgene-ahci-v2"; +- reg = <0x0 0x1a200000 0x0 0x1000>, +- <0x0 0x1f210000 0x0 0x1000>, +- <0x0 0x1f21d000 0x0 0x1000>, +- <0x0 0x1f21e000 0x0 0x1000>; +- interrupts = <0x0 0x5b 0x4>; +- dma-coherent; +- }; +- +- sata3: sata@1a400000 { +- compatible = "apm,xgene-ahci-v2"; +- reg = <0x0 0x1a400000 0x0 0x1000>, +- <0x0 0x1f220000 0x0 0x1000>, +- <0x0 0x1f22d000 0x0 0x1000>, +- <0x0 0x1f22e000 0x0 0x1000>; +- interrupts = <0x0 0x5c 0x4>; +- dma-coherent; +- }; +- +- mmc0: mmc@1c000000 { +- compatible = "arasan,sdhci-4.9a"; +- reg = <0x0 0x1c000000 0x0 0x100>; +- interrupts = <0x0 0x49 0x4>; +- dma-coherent; +- no-1-8-v; +- clock-names = "clk_xin", "clk_ahb"; +- clocks = <&sdioclk 0>, <&ahbclk 0>; +- }; +- +- gfcgpio: gpio@1f63c000 { +- compatible = "apm,xgene-gpio"; +- reg = <0x0 0x1f63c000 0x0 0x40>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- dwgpio: gpio@1c024000 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x0 0x1c024000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- porta: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <32>; +- reg = <0>; +- }; +- }; +- +- sbgpio: gpio@17001000{ +- compatible = "apm,xgene-gpio-sb"; +- reg = <0x0 0x17001000 0x0 0x400>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupts = <0x0 0x28 0x1>, +- <0x0 0x29 0x1>, +- <0x0 0x2a 0x1>, +- <0x0 0x2b 0x1>, +- <0x0 0x2c 0x1>, +- <0x0 0x2d 0x1>, +- <0x0 0x2e 0x1>, +- <0x0 0x2f 0x1>; +- interrupt-parent = <&gic>; +- #interrupt-cells = <2>; +- interrupt-controller; +- apm,nr-gpios = <22>; +- apm,nr-irqs = <8>; +- apm,irq-start = <8>; +- }; +- +- mdio: mdio@1f610000 { +- compatible = "apm,xgene-mdio-xfi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x1f610000 0x0 0xd100>; +- clocks = <&xge0clk 0>; +- }; +- +- sgenet0: ethernet@1f610000 { +- compatible = "apm,xgene2-sgenet"; +- status = "disabled"; +- reg = <0x0 0x1f610000 0x0 0xd100>, +- <0x0 0x1f600000 0x0 0xd100>, +- <0x0 0x20000000 0x0 0x20000>; +- interrupts = <0 96 4>, +- <0 97 4>; +- dma-coherent; +- clocks = <&xge0clk 0>; +- local-mac-address = [00 01 73 00 00 01]; +- phy-connection-type = "sgmii"; +- phy-handle = <&sgenet0phy>; +- }; +- +- xgenet1: ethernet@1f620000 { +- compatible = "apm,xgene2-xgenet"; +- status = "disabled"; +- reg = <0x0 0x1f620000 0x0 0x10000>, +- <0x0 0x1f600000 0x0 0xd100>, +- <0x0 0x20000000 0x0 0x220000>; +- interrupts = <0 108 4>, +- <0 109 4>, +- <0 110 4>, +- <0 111 4>, +- <0 112 4>, +- <0 113 4>, +- <0 114 4>, +- <0 115 4>; +- channel = <12>; +- port-id = <1>; +- dma-coherent; +- clocks = <&xge1clk 0>; +- local-mac-address = [00 01 73 00 00 02]; +- phy-connection-type = "xgmii"; +- }; +- +- rng: rng@10520000 { +- compatible = "apm,xgene-rng"; +- reg = <0x0 0x10520000 0x0 0x100>; +- interrupts = <0x0 0x41 0x4>; +- clocks = <&rngpkaclk 0>; +- }; +- +- i2c1: i2c@10511000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0x0 0x10511000 0x0 0x1000>; +- interrupts = <0 0x45 0x4>; +- #clock-cells = <1>; +- clocks = <&sbapbclk 0>; +- bus_num = <1>; +- }; +- +- i2c4: i2c@10640000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0x0 0x10640000 0x0 0x1000>; +- interrupts = <0 0x3a 0x4>; +- clocks = <&i2c4clk 0>; +- bus_num = <4>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/apm/apm-storm.dtsi b/scripts/dtc/include-prefixes/arm64/apm/apm-storm.dtsi +deleted file mode 100644 +index 0f37e77f5459..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/apm/apm-storm.dtsi ++++ /dev/null +@@ -1,1098 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * dts file for AppliedMicro (APM) X-Gene Storm SOC +- * +- * Copyright (C) 2013, Applied Micro Circuits Corporation +- */ +- +-/ { +- compatible = "apm,xgene-storm"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "apm,potenza"; +- reg = <0x0 0x000>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x1 0x0000fff8>; +- next-level-cache = <&xgene_L2_0>; +- }; +- cpu@1 { +- device_type = "cpu"; +- compatible = "apm,potenza"; +- reg = <0x0 0x001>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x1 0x0000fff8>; +- next-level-cache = <&xgene_L2_0>; +- }; +- cpu@100 { +- device_type = "cpu"; +- compatible = "apm,potenza"; +- reg = <0x0 0x100>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x1 0x0000fff8>; +- next-level-cache = <&xgene_L2_1>; +- }; +- cpu@101 { +- device_type = "cpu"; +- compatible = "apm,potenza"; +- reg = <0x0 0x101>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x1 0x0000fff8>; +- next-level-cache = <&xgene_L2_1>; +- }; +- cpu@200 { +- device_type = "cpu"; +- compatible = "apm,potenza"; +- reg = <0x0 0x200>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x1 0x0000fff8>; +- next-level-cache = <&xgene_L2_2>; +- }; +- cpu@201 { +- device_type = "cpu"; +- compatible = "apm,potenza"; +- reg = <0x0 0x201>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x1 0x0000fff8>; +- next-level-cache = <&xgene_L2_2>; +- }; +- cpu@300 { +- device_type = "cpu"; +- compatible = "apm,potenza"; +- reg = <0x0 0x300>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x1 0x0000fff8>; +- next-level-cache = <&xgene_L2_3>; +- }; +- cpu@301 { +- device_type = "cpu"; +- compatible = "apm,potenza"; +- reg = <0x0 0x301>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x1 0x0000fff8>; +- next-level-cache = <&xgene_L2_3>; +- }; +- xgene_L2_0: l2-cache-0 { +- compatible = "cache"; +- }; +- xgene_L2_1: l2-cache-1 { +- compatible = "cache"; +- }; +- xgene_L2_2: l2-cache-2 { +- compatible = "cache"; +- }; +- xgene_L2_3: l2-cache-3 { +- compatible = "cache"; +- }; +- }; +- +- gic: interrupt-controller@78010000 { +- compatible = "arm,cortex-a15-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ +- <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */ +- <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */ +- <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */ +- interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ +- <1 13 0xff08>, /* Non-secure Phys IRQ */ +- <1 14 0xff08>, /* Virt IRQ */ +- <1 15 0xff08>; /* Hyp IRQ */ +- clock-frequency = <50000000>; +- }; +- +- pmu { +- compatible = "apm,potenza-pmu", "arm,armv8-pmuv3"; +- interrupts = <1 12 0xff04>; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>; +- +- clocks { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- refclk: refclk { +- compatible = "fixed-clock"; +- #clock-cells = <1>; +- clock-frequency = <100000000>; +- clock-output-names = "refclk"; +- }; +- +- pcppll: pcppll@17000100 { +- compatible = "apm,xgene-pcppll-clock"; +- #clock-cells = <1>; +- clocks = <&refclk 0>; +- clock-names = "pcppll"; +- reg = <0x0 0x17000100 0x0 0x1000>; +- clock-output-names = "pcppll"; +- type = <0>; +- }; +- +- socpll: socpll@17000120 { +- compatible = "apm,xgene-socpll-clock"; +- #clock-cells = <1>; +- clocks = <&refclk 0>; +- clock-names = "socpll"; +- reg = <0x0 0x17000120 0x0 0x1000>; +- clock-output-names = "socpll"; +- type = <1>; +- }; +- +- socplldiv2: socplldiv2 { +- compatible = "fixed-factor-clock"; +- #clock-cells = <1>; +- clocks = <&socpll 0>; +- clock-names = "socplldiv2"; +- clock-mult = <1>; +- clock-div = <2>; +- clock-output-names = "socplldiv2"; +- }; +- +- ahbclk: ahbclk@17000000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x17000000 0x0 0x2000>; +- reg-names = "div-reg"; +- divider-offset = <0x164>; +- divider-width = <0x5>; +- divider-shift = <0x0>; +- clock-output-names = "ahbclk"; +- }; +- +- sdioclk: sdioclk@1f2ac000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f2ac000 0x0 0x1000 +- 0x0 0x17000000 0x0 0x2000>; +- reg-names = "csr-reg", "div-reg"; +- csr-offset = <0x0>; +- csr-mask = <0x2>; +- enable-offset = <0x8>; +- enable-mask = <0x2>; +- divider-offset = <0x178>; +- divider-width = <0x8>; +- divider-shift = <0x0>; +- clock-output-names = "sdioclk"; +- }; +- +- ethclk: ethclk { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- clock-names = "ethclk"; +- reg = <0x0 0x17000000 0x0 0x1000>; +- reg-names = "div-reg"; +- divider-offset = <0x238>; +- divider-width = <0x9>; +- divider-shift = <0x0>; +- clock-output-names = "ethclk"; +- }; +- +- menetclk: menetclk { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <ðclk 0>; +- reg = <0x0 0x1702c000 0x0 0x1000>; +- reg-names = "csr-reg"; +- clock-output-names = "menetclk"; +- }; +- +- sge0clk: sge0clk@1f21c000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f21c000 0x0 0x1000>; +- reg-names = "csr-reg"; +- csr-mask = <0xa>; +- enable-mask = <0xf>; +- clock-output-names = "sge0clk"; +- }; +- +- xge0clk: xge0clk@1f61c000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f61c000 0x0 0x1000>; +- reg-names = "csr-reg"; +- csr-mask = <0x3>; +- clock-output-names = "xge0clk"; +- }; +- +- xge1clk: xge1clk@1f62c000 { +- compatible = "apm,xgene-device-clock"; +- status = "disabled"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f62c000 0x0 0x1000>; +- reg-names = "csr-reg"; +- csr-mask = <0x3>; +- clock-output-names = "xge1clk"; +- }; +- +- sataphy1clk: sataphy1clk@1f21c000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f21c000 0x0 0x1000>; +- reg-names = "csr-reg"; +- clock-output-names = "sataphy1clk"; +- status = "disabled"; +- csr-offset = <0x4>; +- csr-mask = <0x00>; +- enable-offset = <0x0>; +- enable-mask = <0x06>; +- }; +- +- sataphy2clk: sataphy1clk@1f22c000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f22c000 0x0 0x1000>; +- reg-names = "csr-reg"; +- clock-output-names = "sataphy2clk"; +- status = "ok"; +- csr-offset = <0x4>; +- csr-mask = <0x3a>; +- enable-offset = <0x0>; +- enable-mask = <0x06>; +- }; +- +- sataphy3clk: sataphy1clk@1f23c000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f23c000 0x0 0x1000>; +- reg-names = "csr-reg"; +- clock-output-names = "sataphy3clk"; +- status = "ok"; +- csr-offset = <0x4>; +- csr-mask = <0x3a>; +- enable-offset = <0x0>; +- enable-mask = <0x06>; +- }; +- +- sata01clk: sata01clk@1f21c000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f21c000 0x0 0x1000>; +- reg-names = "csr-reg"; +- clock-output-names = "sata01clk"; +- csr-offset = <0x4>; +- csr-mask = <0x05>; +- enable-offset = <0x0>; +- enable-mask = <0x39>; +- }; +- +- sata23clk: sata23clk@1f22c000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f22c000 0x0 0x1000>; +- reg-names = "csr-reg"; +- clock-output-names = "sata23clk"; +- csr-offset = <0x4>; +- csr-mask = <0x05>; +- enable-offset = <0x0>; +- enable-mask = <0x39>; +- }; +- +- sata45clk: sata45clk@1f23c000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f23c000 0x0 0x1000>; +- reg-names = "csr-reg"; +- clock-output-names = "sata45clk"; +- csr-offset = <0x4>; +- csr-mask = <0x05>; +- enable-offset = <0x0>; +- enable-mask = <0x39>; +- }; +- +- rtcclk: rtcclk@17000000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x17000000 0x0 0x2000>; +- reg-names = "csr-reg"; +- csr-offset = <0xc>; +- csr-mask = <0x2>; +- enable-offset = <0x10>; +- enable-mask = <0x2>; +- clock-output-names = "rtcclk"; +- }; +- +- rngpkaclk: rngpkaclk@17000000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x17000000 0x0 0x2000>; +- reg-names = "csr-reg"; +- csr-offset = <0xc>; +- csr-mask = <0x10>; +- enable-offset = <0x10>; +- enable-mask = <0x10>; +- clock-output-names = "rngpkaclk"; +- }; +- +- pcie0clk: pcie0clk@1f2bc000 { +- status = "disabled"; +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f2bc000 0x0 0x1000>; +- reg-names = "csr-reg"; +- clock-output-names = "pcie0clk"; +- }; +- +- pcie1clk: pcie1clk@1f2cc000 { +- status = "disabled"; +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f2cc000 0x0 0x1000>; +- reg-names = "csr-reg"; +- clock-output-names = "pcie1clk"; +- }; +- +- pcie2clk: pcie2clk@1f2dc000 { +- status = "disabled"; +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f2dc000 0x0 0x1000>; +- reg-names = "csr-reg"; +- clock-output-names = "pcie2clk"; +- }; +- +- pcie3clk: pcie3clk@1f50c000 { +- status = "disabled"; +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f50c000 0x0 0x1000>; +- reg-names = "csr-reg"; +- clock-output-names = "pcie3clk"; +- }; +- +- pcie4clk: pcie4clk@1f51c000 { +- status = "disabled"; +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f51c000 0x0 0x1000>; +- reg-names = "csr-reg"; +- clock-output-names = "pcie4clk"; +- }; +- +- dmaclk: dmaclk@1f27c000 { +- compatible = "apm,xgene-device-clock"; +- #clock-cells = <1>; +- clocks = <&socplldiv2 0>; +- reg = <0x0 0x1f27c000 0x0 0x1000>; +- reg-names = "csr-reg"; +- clock-output-names = "dmaclk"; +- }; +- }; +- +- msi: msi@79000000 { +- compatible = "apm,xgene1-msi"; +- msi-controller; +- reg = <0x00 0x79000000 0x0 0x900000>; +- interrupts = < 0x0 0x10 0x4 +- 0x0 0x11 0x4 +- 0x0 0x12 0x4 +- 0x0 0x13 0x4 +- 0x0 0x14 0x4 +- 0x0 0x15 0x4 +- 0x0 0x16 0x4 +- 0x0 0x17 0x4 +- 0x0 0x18 0x4 +- 0x0 0x19 0x4 +- 0x0 0x1a 0x4 +- 0x0 0x1b 0x4 +- 0x0 0x1c 0x4 +- 0x0 0x1d 0x4 +- 0x0 0x1e 0x4 +- 0x0 0x1f 0x4>; +- }; +- +- scu: system-clk-controller@17000000 { +- compatible = "apm,xgene-scu","syscon"; +- reg = <0x0 0x17000000 0x0 0x400>; +- }; +- +- reboot: reboot@17000014 { +- compatible = "syscon-reboot"; +- regmap = <&scu>; +- offset = <0x14>; +- mask = <0x1>; +- }; +- +- csw: csw@7e200000 { +- compatible = "apm,xgene-csw", "syscon"; +- reg = <0x0 0x7e200000 0x0 0x1000>; +- }; +- +- mcba: mcba@7e700000 { +- compatible = "apm,xgene-mcb", "syscon"; +- reg = <0x0 0x7e700000 0x0 0x1000>; +- }; +- +- mcbb: mcbb@7e720000 { +- compatible = "apm,xgene-mcb", "syscon"; +- reg = <0x0 0x7e720000 0x0 0x1000>; +- }; +- +- efuse: efuse@1054a000 { +- compatible = "apm,xgene-efuse", "syscon"; +- reg = <0x0 0x1054a000 0x0 0x20>; +- }; +- +- rb: rb@7e000000 { +- compatible = "apm,xgene-rb", "syscon"; +- reg = <0x0 0x7e000000 0x0 0x10>; +- }; +- +- edac@78800000 { +- compatible = "apm,xgene-edac"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- regmap-csw = <&csw>; +- regmap-mcba = <&mcba>; +- regmap-mcbb = <&mcbb>; +- regmap-efuse = <&efuse>; +- regmap-rb = <&rb>; +- reg = <0x0 0x78800000 0x0 0x100>; +- interrupts = <0x0 0x20 0x4>, +- <0x0 0x21 0x4>, +- <0x0 0x27 0x4>; +- +- edacmc@7e800000 { +- compatible = "apm,xgene-edac-mc"; +- reg = <0x0 0x7e800000 0x0 0x1000>; +- memory-controller = <0>; +- }; +- +- edacmc@7e840000 { +- compatible = "apm,xgene-edac-mc"; +- reg = <0x0 0x7e840000 0x0 0x1000>; +- memory-controller = <1>; +- }; +- +- edacmc@7e880000 { +- compatible = "apm,xgene-edac-mc"; +- reg = <0x0 0x7e880000 0x0 0x1000>; +- memory-controller = <2>; +- }; +- +- edacmc@7e8c0000 { +- compatible = "apm,xgene-edac-mc"; +- reg = <0x0 0x7e8c0000 0x0 0x1000>; +- memory-controller = <3>; +- }; +- +- edacpmd@7c000000 { +- compatible = "apm,xgene-edac-pmd"; +- reg = <0x0 0x7c000000 0x0 0x200000>; +- pmd-controller = <0>; +- }; +- +- edacpmd@7c200000 { +- compatible = "apm,xgene-edac-pmd"; +- reg = <0x0 0x7c200000 0x0 0x200000>; +- pmd-controller = <1>; +- }; +- +- edacpmd@7c400000 { +- compatible = "apm,xgene-edac-pmd"; +- reg = <0x0 0x7c400000 0x0 0x200000>; +- pmd-controller = <2>; +- }; +- +- edacpmd@7c600000 { +- compatible = "apm,xgene-edac-pmd"; +- reg = <0x0 0x7c600000 0x0 0x200000>; +- pmd-controller = <3>; +- }; +- +- edacl3@7e600000 { +- compatible = "apm,xgene-edac-l3"; +- reg = <0x0 0x7e600000 0x0 0x1000>; +- }; +- +- edacsoc@7e930000 { +- compatible = "apm,xgene-edac-soc-v1"; +- reg = <0x0 0x7e930000 0x0 0x1000>; +- }; +- }; +- +- pmu: pmu@78810000 { +- compatible = "apm,xgene-pmu-v2"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- regmap-csw = <&csw>; +- regmap-mcba = <&mcba>; +- regmap-mcbb = <&mcbb>; +- reg = <0x0 0x78810000 0x0 0x1000>; +- interrupts = <0x0 0x22 0x4>; +- +- pmul3c@7e610000 { +- compatible = "apm,xgene-pmu-l3c"; +- reg = <0x0 0x7e610000 0x0 0x1000>; +- }; +- +- pmuiob@7e940000 { +- compatible = "apm,xgene-pmu-iob"; +- reg = <0x0 0x7e940000 0x0 0x1000>; +- }; +- +- pmucmcb@7e710000 { +- compatible = "apm,xgene-pmu-mcb"; +- reg = <0x0 0x7e710000 0x0 0x1000>; +- enable-bit-index = <0>; +- }; +- +- pmucmcb@7e730000 { +- compatible = "apm,xgene-pmu-mcb"; +- reg = <0x0 0x7e730000 0x0 0x1000>; +- enable-bit-index = <1>; +- }; +- +- pmucmc@7e810000 { +- compatible = "apm,xgene-pmu-mc"; +- reg = <0x0 0x7e810000 0x0 0x1000>; +- enable-bit-index = <0>; +- }; +- +- pmucmc@7e850000 { +- compatible = "apm,xgene-pmu-mc"; +- reg = <0x0 0x7e850000 0x0 0x1000>; +- enable-bit-index = <1>; +- }; +- +- pmucmc@7e890000 { +- compatible = "apm,xgene-pmu-mc"; +- reg = <0x0 0x7e890000 0x0 0x1000>; +- enable-bit-index = <2>; +- }; +- +- pmucmc@7e8d0000 { +- compatible = "apm,xgene-pmu-mc"; +- reg = <0x0 0x7e8d0000 0x0 0x1000>; +- enable-bit-index = <3>; +- }; +- }; +- +- pcie0: pcie@1f2b0000 { +- status = "disabled"; +- device_type = "pci"; +- compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ +- 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ +- reg-names = "csr", "cfg"; +- ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ +- 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */ +- 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */ +- dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 +- 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4 +- 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4 +- 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4 +- 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>; +- dma-coherent; +- clocks = <&pcie0clk 0>; +- msi-parent = <&msi>; +- }; +- +- pcie1: pcie@1f2c0000 { +- status = "disabled"; +- device_type = "pci"; +- compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ +- 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */ +- reg-names = "csr", "cfg"; +- ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */ +- 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */ +- 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */ +- dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 +- 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4 +- 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4 +- 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4 +- 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>; +- dma-coherent; +- clocks = <&pcie1clk 0>; +- msi-parent = <&msi>; +- }; +- +- pcie2: pcie@1f2d0000 { +- status = "disabled"; +- device_type = "pci"; +- compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */ +- 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */ +- reg-names = "csr", "cfg"; +- ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */ +- 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */ +- 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */ +- dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 +- 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4 +- 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4 +- 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4 +- 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>; +- dma-coherent; +- clocks = <&pcie2clk 0>; +- msi-parent = <&msi>; +- }; +- +- pcie3: pcie@1f500000 { +- status = "disabled"; +- device_type = "pci"; +- compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */ +- 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ +- reg-names = "csr", "cfg"; +- ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ +- 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */ +- 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ +- dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 +- 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4 +- 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4 +- 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4 +- 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>; +- dma-coherent; +- clocks = <&pcie3clk 0>; +- msi-parent = <&msi>; +- }; +- +- pcie4: pcie@1f510000 { +- status = "disabled"; +- device_type = "pci"; +- compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */ +- 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */ +- reg-names = "csr", "cfg"; +- ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ +- 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */ +- 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */ +- dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 +- 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4 +- 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4 +- 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4 +- 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>; +- dma-coherent; +- clocks = <&pcie4clk 0>; +- msi-parent = <&msi>; +- }; +- +- mailbox: mailbox@10540000 { +- compatible = "apm,xgene-slimpro-mbox"; +- reg = <0x0 0x10540000 0x0 0xa000>; +- #mbox-cells = <1>; +- interrupts = <0x0 0x0 0x4>, +- <0x0 0x1 0x4>, +- <0x0 0x2 0x4>, +- <0x0 0x3 0x4>, +- <0x0 0x4 0x4>, +- <0x0 0x5 0x4>, +- <0x0 0x6 0x4>, +- <0x0 0x7 0x4>; +- }; +- +- i2cslimpro { +- compatible = "apm,xgene-slimpro-i2c"; +- mboxes = <&mailbox 0>; +- }; +- +- hwmonslimpro { +- compatible = "apm,xgene-slimpro-hwmon"; +- mboxes = <&mailbox 7>; +- }; +- +- serial0: serial@1c020000 { +- status = "disabled"; +- device_type = "serial"; +- compatible = "ns16550a"; +- reg = <0 0x1c020000 0x0 0x1000>; +- reg-shift = <2>; +- clock-frequency = <10000000>; /* Updated by bootloader */ +- interrupt-parent = <&gic>; +- interrupts = <0x0 0x4c 0x4>; +- }; +- +- serial1: serial@1c021000 { +- status = "disabled"; +- device_type = "serial"; +- compatible = "ns16550a"; +- reg = <0 0x1c021000 0x0 0x1000>; +- reg-shift = <2>; +- clock-frequency = <10000000>; /* Updated by bootloader */ +- interrupt-parent = <&gic>; +- interrupts = <0x0 0x4d 0x4>; +- }; +- +- serial2: serial@1c022000 { +- status = "disabled"; +- device_type = "serial"; +- compatible = "ns16550a"; +- reg = <0 0x1c022000 0x0 0x1000>; +- reg-shift = <2>; +- clock-frequency = <10000000>; /* Updated by bootloader */ +- interrupt-parent = <&gic>; +- interrupts = <0x0 0x4e 0x4>; +- }; +- +- serial3: serial@1c023000 { +- status = "disabled"; +- device_type = "serial"; +- compatible = "ns16550a"; +- reg = <0 0x1c023000 0x0 0x1000>; +- reg-shift = <2>; +- clock-frequency = <10000000>; /* Updated by bootloader */ +- interrupt-parent = <&gic>; +- interrupts = <0x0 0x4f 0x4>; +- }; +- +- mmc0: mmc@1c000000 { +- compatible = "arasan,sdhci-4.9a"; +- reg = <0x0 0x1c000000 0x0 0x100>; +- interrupts = <0x0 0x49 0x4>; +- dma-coherent; +- no-1-8-v; +- clock-names = "clk_xin", "clk_ahb"; +- clocks = <&sdioclk 0>, <&ahbclk 0>; +- }; +- +- gfcgpio: gpio0@1701c000 { +- compatible = "apm,xgene-gpio"; +- reg = <0x0 0x1701c000 0x0 0x40>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- dwgpio: gpio@1c024000 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x0 0x1c024000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- porta: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <32>; +- reg = <0>; +- }; +- }; +- +- i2c0: i2c@10512000 { +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0x0 0x10512000 0x0 0x1000>; +- interrupts = <0 0x44 0x4>; +- #clock-cells = <1>; +- clocks = <&ahbclk 0>; +- bus_num = <0>; +- }; +- +- phy1: phy@1f21a000 { +- compatible = "apm,xgene-phy"; +- reg = <0x0 0x1f21a000 0x0 0x100>; +- #phy-cells = <1>; +- clocks = <&sataphy1clk 0>; +- status = "disabled"; +- apm,tx-boost-gain = <30 30 30 30 30 30>; +- apm,tx-eye-tuning = <2 10 10 2 10 10>; +- }; +- +- phy2: phy@1f22a000 { +- compatible = "apm,xgene-phy"; +- reg = <0x0 0x1f22a000 0x0 0x100>; +- #phy-cells = <1>; +- clocks = <&sataphy2clk 0>; +- status = "ok"; +- apm,tx-boost-gain = <30 30 30 30 30 30>; +- apm,tx-eye-tuning = <1 10 10 2 10 10>; +- }; +- +- phy3: phy@1f23a000 { +- compatible = "apm,xgene-phy"; +- reg = <0x0 0x1f23a000 0x0 0x100>; +- #phy-cells = <1>; +- clocks = <&sataphy3clk 0>; +- status = "ok"; +- apm,tx-boost-gain = <31 31 31 31 31 31>; +- apm,tx-eye-tuning = <2 10 10 2 10 10>; +- }; +- +- sata1: sata@1a000000 { +- compatible = "apm,xgene-ahci"; +- reg = <0x0 0x1a000000 0x0 0x1000>, +- <0x0 0x1f210000 0x0 0x1000>, +- <0x0 0x1f21d000 0x0 0x1000>, +- <0x0 0x1f21e000 0x0 0x1000>, +- <0x0 0x1f217000 0x0 0x1000>; +- interrupts = <0x0 0x86 0x4>; +- dma-coherent; +- status = "disabled"; +- clocks = <&sata01clk 0>; +- phys = <&phy1 0>; +- phy-names = "sata-phy"; +- }; +- +- sata2: sata@1a400000 { +- compatible = "apm,xgene-ahci"; +- reg = <0x0 0x1a400000 0x0 0x1000>, +- <0x0 0x1f220000 0x0 0x1000>, +- <0x0 0x1f22d000 0x0 0x1000>, +- <0x0 0x1f22e000 0x0 0x1000>, +- <0x0 0x1f227000 0x0 0x1000>; +- interrupts = <0x0 0x87 0x4>; +- dma-coherent; +- status = "ok"; +- clocks = <&sata23clk 0>; +- phys = <&phy2 0>; +- phy-names = "sata-phy"; +- }; +- +- sata3: sata@1a800000 { +- compatible = "apm,xgene-ahci"; +- reg = <0x0 0x1a800000 0x0 0x1000>, +- <0x0 0x1f230000 0x0 0x1000>, +- <0x0 0x1f23d000 0x0 0x1000>, +- <0x0 0x1f23e000 0x0 0x1000>; +- interrupts = <0x0 0x88 0x4>; +- dma-coherent; +- status = "ok"; +- clocks = <&sata45clk 0>; +- phys = <&phy3 0>; +- phy-names = "sata-phy"; +- }; +- +- /* Do not change dwusb name, coded for backward compatibility */ +- usb0: dwusb@19000000 { +- status = "disabled"; +- compatible = "snps,dwc3"; +- reg = <0x0 0x19000000 0x0 0x100000>; +- interrupts = <0x0 0x89 0x4>; +- dma-coherent; +- dr_mode = "host"; +- }; +- +- usb1: dwusb@19800000 { +- status = "disabled"; +- compatible = "snps,dwc3"; +- reg = <0x0 0x19800000 0x0 0x100000>; +- interrupts = <0x0 0x8a 0x4>; +- dma-coherent; +- dr_mode = "host"; +- }; +- +- sbgpio: gpio@17001000{ +- compatible = "apm,xgene-gpio-sb"; +- reg = <0x0 0x17001000 0x0 0x400>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupts = <0x0 0x28 0x1>, +- <0x0 0x29 0x1>, +- <0x0 0x2a 0x1>, +- <0x0 0x2b 0x1>, +- <0x0 0x2c 0x1>, +- <0x0 0x2d 0x1>; +- interrupt-parent = <&gic>; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- rtc: rtc@10510000 { +- compatible = "apm,xgene-rtc"; +- reg = <0x0 0x10510000 0x0 0x400>; +- interrupts = <0x0 0x46 0x4>; +- #clock-cells = <1>; +- clocks = <&rtcclk 0>; +- }; +- +- mdio: mdio@17020000 { +- compatible = "apm,xgene-mdio-rgmii"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x17020000 0x0 0xd100>; +- clocks = <&menetclk 0>; +- }; +- +- menet: ethernet@17020000 { +- compatible = "apm,xgene-enet"; +- status = "disabled"; +- reg = <0x0 0x17020000 0x0 0xd100>, +- <0x0 0x17030000 0x0 0xc300>, +- <0x0 0x10000000 0x0 0x200>; +- reg-names = "enet_csr", "ring_csr", "ring_cmd"; +- interrupts = <0x0 0x3c 0x4>; +- dma-coherent; +- clocks = <&menetclk 0>; +- /* mac address will be overwritten by the bootloader */ +- local-mac-address = [00 00 00 00 00 00]; +- phy-connection-type = "rgmii"; +- phy-handle = <&menetphy>,<&menet0phy>; +- mdio { +- compatible = "apm,xgene-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- menetphy: menetphy@3 { +- compatible = "ethernet-phy-id001c.c915"; +- reg = <0x3>; +- }; +- +- }; +- }; +- +- sgenet0: ethernet@1f210000 { +- compatible = "apm,xgene1-sgenet"; +- status = "disabled"; +- reg = <0x0 0x1f210000 0x0 0xd100>, +- <0x0 0x1f200000 0x0 0xc300>, +- <0x0 0x1b000000 0x0 0x200>; +- reg-names = "enet_csr", "ring_csr", "ring_cmd"; +- interrupts = <0x0 0xa0 0x4>, +- <0x0 0xa1 0x4>; +- dma-coherent; +- clocks = <&sge0clk 0>; +- local-mac-address = [00 00 00 00 00 00]; +- phy-connection-type = "sgmii"; +- phy-handle = <&sgenet0phy>; +- }; +- +- sgenet1: ethernet@1f210030 { +- compatible = "apm,xgene1-sgenet"; +- status = "disabled"; +- reg = <0x0 0x1f210030 0x0 0xd100>, +- <0x0 0x1f200000 0x0 0xc300>, +- <0x0 0x1b000000 0x0 0x8000>; +- reg-names = "enet_csr", "ring_csr", "ring_cmd"; +- interrupts = <0x0 0xac 0x4>, +- <0x0 0xad 0x4>; +- port-id = <1>; +- dma-coherent; +- local-mac-address = [00 00 00 00 00 00]; +- phy-connection-type = "sgmii"; +- phy-handle = <&sgenet1phy>; +- }; +- +- xgenet: ethernet@1f610000 { +- compatible = "apm,xgene1-xgenet"; +- status = "disabled"; +- reg = <0x0 0x1f610000 0x0 0xd100>, +- <0x0 0x1f600000 0x0 0xc300>, +- <0x0 0x18000000 0x0 0x200>; +- reg-names = "enet_csr", "ring_csr", "ring_cmd"; +- interrupts = <0x0 0x60 0x4>, +- <0x0 0x61 0x4>, +- <0x0 0x62 0x4>, +- <0x0 0x63 0x4>, +- <0x0 0x64 0x4>, +- <0x0 0x65 0x4>, +- <0x0 0x66 0x4>, +- <0x0 0x67 0x4>; +- channel = <0>; +- dma-coherent; +- clocks = <&xge0clk 0>; +- /* mac address will be overwritten by the bootloader */ +- local-mac-address = [00 00 00 00 00 00]; +- phy-connection-type = "xgmii"; +- }; +- +- xgenet1: ethernet@1f620000 { +- compatible = "apm,xgene1-xgenet"; +- status = "disabled"; +- reg = <0x0 0x1f620000 0x0 0xd100>, +- <0x0 0x1f600000 0x0 0xc300>, +- <0x0 0x18000000 0x0 0x8000>; +- reg-names = "enet_csr", "ring_csr", "ring_cmd"; +- interrupts = <0x0 0x6c 0x4>, +- <0x0 0x6d 0x4>; +- port-id = <1>; +- dma-coherent; +- clocks = <&xge1clk 0>; +- /* mac address will be overwritten by the bootloader */ +- local-mac-address = [00 00 00 00 00 00]; +- phy-connection-type = "xgmii"; +- }; +- +- rng: rng@10520000 { +- compatible = "apm,xgene-rng"; +- reg = <0x0 0x10520000 0x0 0x100>; +- interrupts = <0x0 0x41 0x4>; +- clocks = <&rngpkaclk 0>; +- }; +- +- dma: dma@1f270000 { +- compatible = "apm,xgene-storm-dma"; +- device_type = "dma"; +- reg = <0x0 0x1f270000 0x0 0x10000>, +- <0x0 0x1f200000 0x0 0x10000>, +- <0x0 0x1b000000 0x0 0x400000>, +- <0x0 0x1054a000 0x0 0x100>; +- interrupts = <0x0 0x82 0x4>, +- <0x0 0xb8 0x4>, +- <0x0 0xb9 0x4>, +- <0x0 0xba 0x4>, +- <0x0 0xbb 0x4>; +- dma-coherent; +- clocks = <&dmaclk 0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/apple/Makefile b/scripts/dtc/include-prefixes/arm64/apple/Makefile +deleted file mode 100644 +index cbbd701ebf05..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/apple/Makefile ++++ /dev/null +@@ -1,2 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_APPLE) += t8103-j274.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/apple/t8103-j274.dts b/scripts/dtc/include-prefixes/arm64/apple/t8103-j274.dts +deleted file mode 100644 +index e0f6775b9878..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/apple/t8103-j274.dts ++++ /dev/null +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Apple Mac mini (M1, 2020) +- * +- * target-type: J274 +- * +- * Copyright The Asahi Linux Contributors +- */ +- +-/dts-v1/; +- +-#include "t8103.dtsi" +- +-/ { +- compatible = "apple,j274", "apple,t8103", "apple,arm-platform"; +- model = "Apple Mac mini (M1, 2020)"; +- +- aliases { +- serial0 = &serial0; +- }; +- +- chosen { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- stdout-path = "serial0"; +- +- framebuffer0: framebuffer@0 { +- compatible = "apple,simple-framebuffer", "simple-framebuffer"; +- reg = <0 0 0 0>; /* To be filled by loader */ +- /* Format properties will be added by loader */ +- status = "disabled"; +- }; +- }; +- +- memory@800000000 { +- device_type = "memory"; +- reg = <0x8 0 0x2 0>; /* To be filled by loader */ +- }; +-}; +- +-&serial0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/apple/t8103.dtsi b/scripts/dtc/include-prefixes/arm64/apple/t8103.dtsi +deleted file mode 100644 +index a1e22a2ea2e5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/apple/t8103.dtsi ++++ /dev/null +@@ -1,135 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Apple T8103 "M1" SoC +- * +- * Other names: H13G, "Tonga" +- * +- * Copyright The Asahi Linux Contributors +- */ +- +-#include +-#include +- +-/ { +- compatible = "apple,t8103", "apple,arm-platform"; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "apple,icestorm"; +- device_type = "cpu"; +- reg = <0x0 0x0>; +- enable-method = "spin-table"; +- cpu-release-addr = <0 0>; /* To be filled by loader */ +- }; +- +- cpu1: cpu@1 { +- compatible = "apple,icestorm"; +- device_type = "cpu"; +- reg = <0x0 0x1>; +- enable-method = "spin-table"; +- cpu-release-addr = <0 0>; /* To be filled by loader */ +- }; +- +- cpu2: cpu@2 { +- compatible = "apple,icestorm"; +- device_type = "cpu"; +- reg = <0x0 0x2>; +- enable-method = "spin-table"; +- cpu-release-addr = <0 0>; /* To be filled by loader */ +- }; +- +- cpu3: cpu@3 { +- compatible = "apple,icestorm"; +- device_type = "cpu"; +- reg = <0x0 0x3>; +- enable-method = "spin-table"; +- cpu-release-addr = <0 0>; /* To be filled by loader */ +- }; +- +- cpu4: cpu@10100 { +- compatible = "apple,firestorm"; +- device_type = "cpu"; +- reg = <0x0 0x10100>; +- enable-method = "spin-table"; +- cpu-release-addr = <0 0>; /* To be filled by loader */ +- }; +- +- cpu5: cpu@10101 { +- compatible = "apple,firestorm"; +- device_type = "cpu"; +- reg = <0x0 0x10101>; +- enable-method = "spin-table"; +- cpu-release-addr = <0 0>; /* To be filled by loader */ +- }; +- +- cpu6: cpu@10102 { +- compatible = "apple,firestorm"; +- device_type = "cpu"; +- reg = <0x0 0x10102>; +- enable-method = "spin-table"; +- cpu-release-addr = <0 0>; /* To be filled by loader */ +- }; +- +- cpu7: cpu@10103 { +- compatible = "apple,firestorm"; +- device_type = "cpu"; +- reg = <0x0 0x10103>; +- enable-method = "spin-table"; +- cpu-release-addr = <0 0>; /* To be filled by loader */ +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupt-parent = <&aic>; +- interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; +- interrupts = , +- , +- , +- ; +- }; +- +- clk24: clock-24m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "clk24"; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- ranges; +- nonposted-mmio; +- +- serial0: serial@235200000 { +- compatible = "apple,s5l-uart"; +- reg = <0x2 0x35200000 0x0 0x1000>; +- reg-io-width = <4>; +- interrupt-parent = <&aic>; +- interrupts = ; +- /* +- * TODO: figure out the clocking properly, there may +- * be a third selectable clock. +- */ +- clocks = <&clk24>, <&clk24>; +- clock-names = "uart", "clk_uart_baud0"; +- status = "disabled"; +- }; +- +- aic: interrupt-controller@23b100000 { +- compatible = "apple,t8103-aic", "apple,aic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x2 0x3b100000 0x0 0x8000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/arm/Makefile b/scripts/dtc/include-prefixes/arm64/arm/Makefile +deleted file mode 100644 +index 800da2e84f3f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/Makefile ++++ /dev/null +@@ -1,8 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_VEXPRESS) += \ +- foundation-v8.dtb foundation-v8-psci.dtb \ +- foundation-v8-gicv3.dtb foundation-v8-gicv3-psci.dtb +-dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb +-dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb +-dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb +-dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-gicv2.dtsi b/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-gicv2.dtsi +deleted file mode 100644 +index 655fdcce1561..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-gicv2.dtsi ++++ /dev/null +@@ -1,19 +0,0 @@ +-/* +- * ARM Ltd. +- * +- * ARMv8 Foundation model DTS (GICv2 configuration) +- */ +- +-/ { +- gic: interrupt-controller@2c001000 { +- compatible = "arm,gic-400", "arm,cortex-a15-gic"; +- #interrupt-cells = <3>; +- #address-cells = <1>; +- interrupt-controller; +- reg = <0x0 0x2c001000 0 0x1000>, +- <0x0 0x2c002000 0 0x2000>, +- <0x0 0x2c004000 0 0x2000>, +- <0x0 0x2c006000 0 0x2000>; +- interrupts = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-gicv3-psci.dts b/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-gicv3-psci.dts +deleted file mode 100644 +index e096e670bec3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-gicv3-psci.dts ++++ /dev/null +@@ -1,9 +0,0 @@ +-/* +- * ARM Ltd. +- * +- * ARMv8 Foundation model DTS (GICv3+PSCI configuration) +- */ +- +-#include "foundation-v8.dtsi" +-#include "foundation-v8-gicv3.dtsi" +-#include "foundation-v8-psci.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-gicv3.dts b/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-gicv3.dts +deleted file mode 100644 +index c87380e87f59..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-gicv3.dts ++++ /dev/null +@@ -1,10 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * ARM Ltd. +- * +- * ARMv8 Foundation model DTS (GICv3 configuration) +- */ +- +-#include "foundation-v8.dtsi" +-#include "foundation-v8-gicv3.dtsi" +-#include "foundation-v8-spin-table.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-gicv3.dtsi b/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-gicv3.dtsi +deleted file mode 100644 +index e4a3c7dbcc20..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-gicv3.dtsi ++++ /dev/null +@@ -1,29 +0,0 @@ +-/* +- * ARM Ltd. +- * +- * ARMv8 Foundation model DTS (GICv3 configuration) +- */ +- +-/ { +- gic: interrupt-controller@2f000000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x2f000000 0x100000>; +- interrupt-controller; +- reg = <0x0 0x2f000000 0x0 0x10000>, +- <0x0 0x2f100000 0x0 0x200000>, +- <0x0 0x2c000000 0x0 0x2000>, +- <0x0 0x2c010000 0x0 0x2000>, +- <0x0 0x2c02f000 0x0 0x2000>; +- interrupts = ; +- +- its: msi-controller@2f020000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0x20000 0x20000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-psci.dts b/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-psci.dts +deleted file mode 100644 +index 723f23c7cd31..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-psci.dts ++++ /dev/null +@@ -1,9 +0,0 @@ +-/* +- * ARM Ltd. +- * +- * ARMv8 Foundation model DTS (GICv2+PSCI configuration) +- */ +- +-#include "foundation-v8.dtsi" +-#include "foundation-v8-gicv2.dtsi" +-#include "foundation-v8-psci.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-psci.dtsi b/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-psci.dtsi +deleted file mode 100644 +index 16cdf395728b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-psci.dtsi ++++ /dev/null +@@ -1,28 +0,0 @@ +-/* +- * ARM Ltd. +- * +- * ARMv8 Foundation model DTS (PSCI configuration) +- */ +- +-/ { +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +-}; +- +-&cpu0 { +- enable-method = "psci"; +-}; +- +-&cpu1 { +- enable-method = "psci"; +-}; +- +-&cpu2 { +- enable-method = "psci"; +-}; +- +-&cpu3 { +- enable-method = "psci"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-spin-table.dtsi b/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-spin-table.dtsi +deleted file mode 100644 +index 4d4186ba0e8c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/foundation-v8-spin-table.dtsi ++++ /dev/null +@@ -1,25 +0,0 @@ +-/* +- * ARM Ltd. +- * +- * ARMv8 Foundation model DTS (spin table configuration) +- */ +- +-&cpu0 { +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x8000fff8>; +-}; +- +-&cpu1 { +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x8000fff8>; +-}; +- +-&cpu2 { +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x8000fff8>; +-}; +- +-&cpu3 { +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x8000fff8>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/arm/foundation-v8.dts b/scripts/dtc/include-prefixes/arm64/arm/foundation-v8.dts +deleted file mode 100644 +index b17347d75ec6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/foundation-v8.dts ++++ /dev/null +@@ -1,10 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * ARM Ltd. +- * +- * ARMv8 Foundation model DTS (GICv2 configuration) +- */ +- +-#include "foundation-v8.dtsi" +-#include "foundation-v8-gicv2.dtsi" +-#include "foundation-v8-spin-table.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/arm/foundation-v8.dtsi b/scripts/dtc/include-prefixes/arm64/arm/foundation-v8.dtsi +deleted file mode 100644 +index fbf13f7c2baf..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/foundation-v8.dtsi ++++ /dev/null +@@ -1,230 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * ARM Ltd. +- * +- * ARMv8 Foundation model DTS +- */ +- +-/dts-v1/; +- +-#include +- +-/memreserve/ 0x80000000 0x00010000; +- +-/ { +- model = "Foundation-v8A"; +- compatible = "arm,foundation-aarch64", "arm,vexpress"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- chosen { }; +- +- aliases { +- serial0 = &v2m_serial0; +- serial1 = &v2m_serial1; +- serial2 = &v2m_serial2; +- serial3 = &v2m_serial3; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,armv8"; +- reg = <0x0 0x0>; +- next-level-cache = <&L2_0>; +- }; +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,armv8"; +- reg = <0x0 0x1>; +- next-level-cache = <&L2_0>; +- }; +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,armv8"; +- reg = <0x0 0x2>; +- next-level-cache = <&L2_0>; +- }; +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,armv8"; +- reg = <0x0 0x3>; +- next-level-cache = <&L2_0>; +- }; +- +- L2_0: l2-cache0 { +- compatible = "cache"; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0 0x80000000>, +- <0x00000008 0x80000000 0 0x80000000>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- clock-frequency = <100000000>; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = , +- , +- , +- ; +- }; +- +- watchdog@2a440000 { +- compatible = "arm,sbsa-gwdt"; +- reg = <0x0 0x2a440000 0 0x1000>, +- <0x0 0x2a450000 0 0x1000>; +- interrupts = ; +- timeout-sec = <30>; +- }; +- +- v2m_clk24mhz: clk24mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "v2m:clk24mhz"; +- }; +- +- v2m_refclk1mhz: refclk1mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <1000000>; +- clock-output-names = "v2m:refclk1mhz"; +- }; +- +- v2m_refclk32khz: refclk32khz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "v2m:refclk32khz"; +- }; +- +- bus@8000000 { +- compatible = "arm,vexpress,v2m-p1", "simple-bus"; +- #address-cells = <2>; /* SMB chipselect number and offset */ +- #size-cells = <1>; +- +- ranges = <0 0 0 0x08000000 0x04000000>, +- <1 0 0 0x14000000 0x04000000>, +- <2 0 0 0x18000000 0x04000000>, +- <3 0 0 0x1c000000 0x04000000>, +- <4 0 0 0x0c000000 0x04000000>, +- <5 0 0 0x10000000 0x04000000>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 63>; +- interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 8 &gic 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 9 &gic 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; +- +- ethernet@202000000 { +- compatible = "smsc,lan91c111"; +- reg = <2 0x02000000 0x10000>; +- interrupts = <15>; +- }; +- +- iofpga-bus@300000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 3 0 0x200000>; +- +- v2m_sysreg: sysreg@10000 { +- compatible = "arm,vexpress-sysreg"; +- reg = <0x010000 0x1000>; +- }; +- +- v2m_serial0: serial@90000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x090000 0x1000>; +- interrupts = <5>; +- clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- v2m_serial1: serial@a0000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0a0000 0x1000>; +- interrupts = <6>; +- clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- v2m_serial2: serial@b0000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0b0000 0x1000>; +- interrupts = <7>; +- clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- v2m_serial3: serial@c0000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0c0000 0x1000>; +- interrupts = <8>; +- clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- virtio-block@130000 { +- compatible = "virtio,mmio"; +- reg = <0x130000 0x200>; +- interrupts = <42>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/arm/fvp-base-revc.dts b/scripts/dtc/include-prefixes/arm64/arm/fvp-base-revc.dts +deleted file mode 100644 +index 269b649934b5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/fvp-base-revc.dts ++++ /dev/null +@@ -1,246 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * ARM Ltd. Fast Models +- * +- * Architecture Envelope Model (AEM) ARMv8-A +- * ARMAEMv8AMPCT +- * +- * FVP Base RevC +- */ +- +-/dts-v1/; +- +-#include +- +-/memreserve/ 0x80000000 0x00010000; +- +-#include "rtsm_ve-motherboard.dtsi" +-#include "rtsm_ve-motherboard-rs2.dtsi" +- +-/ { +- model = "FVP Base RevC"; +- compatible = "arm,fvp-base-revc", "arm,vexpress"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- chosen { }; +- +- aliases { +- serial0 = &v2m_serial0; +- serial1 = &v2m_serial1; +- serial2 = &v2m_serial2; +- serial3 = &v2m_serial3; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,armv8"; +- reg = <0x0 0x000>; +- enable-method = "psci"; +- }; +- cpu1: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,armv8"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- }; +- cpu2: cpu@200 { +- device_type = "cpu"; +- compatible = "arm,armv8"; +- reg = <0x0 0x200>; +- enable-method = "psci"; +- }; +- cpu3: cpu@300 { +- device_type = "cpu"; +- compatible = "arm,armv8"; +- reg = <0x0 0x300>; +- enable-method = "psci"; +- }; +- cpu4: cpu@10000 { +- device_type = "cpu"; +- compatible = "arm,armv8"; +- reg = <0x0 0x10000>; +- enable-method = "psci"; +- }; +- cpu5: cpu@10100 { +- device_type = "cpu"; +- compatible = "arm,armv8"; +- reg = <0x0 0x10100>; +- enable-method = "psci"; +- }; +- cpu6: cpu@10200 { +- device_type = "cpu"; +- compatible = "arm,armv8"; +- reg = <0x0 0x10200>; +- enable-method = "psci"; +- }; +- cpu7: cpu@10300 { +- device_type = "cpu"; +- compatible = "arm,armv8"; +- reg = <0x0 0x10300>; +- enable-method = "psci"; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0 0x80000000>, +- <0x00000008 0x80000000 0 0x80000000>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- /* Chipselect 2,00000000 is physically at 0x18000000 */ +- vram: vram@18000000 { +- /* 8 MB of designated video RAM */ +- compatible = "shared-dma-pool"; +- reg = <0x00000000 0x18000000 0 0x00800000>; +- no-map; +- }; +- }; +- +- gic: interrupt-controller@2f000000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- interrupt-controller; +- reg = <0x0 0x2f000000 0 0x10000>, // GICD +- <0x0 0x2f100000 0 0x200000>, // GICR +- <0x0 0x2c000000 0 0x2000>, // GICC +- <0x0 0x2c010000 0 0x2000>, // GICH +- <0x0 0x2c02f000 0 0x2000>; // GICV +- interrupts = ; +- +- its: msi-controller@2f020000 { +- #msi-cells = <1>; +- compatible = "arm,gic-v3-its"; +- reg = <0x0 0x2f020000 0x0 0x20000>; // GITS +- msi-controller; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = ; +- }; +- +- spe-pmu { +- compatible = "arm,statistical-profiling-extension-v1"; +- interrupts = ; +- }; +- +- pci: pci@40000000 { +- #address-cells = <0x3>; +- #size-cells = <0x2>; +- #interrupt-cells = <0x1>; +- compatible = "pci-host-ecam-generic"; +- device_type = "pci"; +- bus-range = <0x0 0x1>; +- reg = <0x0 0x40000000 0x0 0x10000000>; +- ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>; +- interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- msi-map = <0x0 &its 0x0 0x10000>; +- iommu-map = <0x0 &smmu 0x0 0x10000>; +- +- dma-coherent; +- }; +- +- smmu: iommu@2b400000 { +- compatible = "arm,smmu-v3"; +- reg = <0x0 0x2b400000 0x0 0x100000>; +- interrupts = , +- , +- , +- ; +- interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; +- dma-coherent; +- #iommu-cells = <1>; +- msi-parent = <&its 0x10000>; +- }; +- +- panel { +- compatible = "arm,rtsm-display", "panel-dpi"; +- port { +- panel_in: endpoint { +- remote-endpoint = <&clcd_pads>; +- }; +- }; +- }; +- +- bus@8000000 { +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 63>; +- interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/arm/juno-base.dtsi b/scripts/dtc/include-prefixes/arm64/arm/juno-base.dtsi +deleted file mode 100644 +index a2635b14da30..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/juno-base.dtsi ++++ /dev/null +@@ -1,830 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "juno-clocks.dtsi" +-#include "juno-motherboard.dtsi" +- +-/ { +- /* +- * Devices shared by all Juno boards +- */ +- +- memtimer: timer@2a810000 { +- compatible = "arm,armv7-timer-mem"; +- reg = <0x0 0x2a810000 0x0 0x10000>; +- clock-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x0 0x2a820000 0x20000>; +- status = "disabled"; +- frame@2a830000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0x10000 0x10000>; +- }; +- }; +- +- mailbox: mhu@2b1f0000 { +- compatible = "arm,mhu", "arm,primecell"; +- reg = <0x0 0x2b1f0000 0x0 0x1000>; +- interrupts = , +- ; +- #mbox-cells = <1>; +- clocks = <&soc_refclk100mhz>; +- clock-names = "apb_pclk"; +- }; +- +- smmu_gpu: iommu@2b400000 { +- compatible = "arm,mmu-400", "arm,smmu-v1"; +- reg = <0x0 0x2b400000 0x0 0x10000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- #global-interrupts = <1>; +- power-domains = <&scpi_devpd 1>; +- dma-coherent; +- status = "disabled"; +- }; +- +- smmu_pcie: iommu@2b500000 { +- compatible = "arm,mmu-401", "arm,smmu-v1"; +- reg = <0x0 0x2b500000 0x0 0x10000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- #global-interrupts = <1>; +- dma-coherent; +- status = "disabled"; +- }; +- +- smmu_etr: iommu@2b600000 { +- compatible = "arm,mmu-401", "arm,smmu-v1"; +- reg = <0x0 0x2b600000 0x0 0x10000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- #global-interrupts = <1>; +- dma-coherent; +- power-domains = <&scpi_devpd 0>; +- }; +- +- gic: interrupt-controller@2c010000 { +- compatible = "arm,gic-400", "arm,cortex-a15-gic"; +- reg = <0x0 0x2c010000 0 0x1000>, +- <0x0 0x2c02f000 0 0x2000>, +- <0x0 0x2c04f000 0 0x2000>, +- <0x0 0x2c06f000 0 0x2000>; +- #address-cells = <1>; +- #interrupt-cells = <3>; +- #size-cells = <1>; +- interrupt-controller; +- interrupts = ; +- ranges = <0 0 0x2c1c0000 0x40000>; +- +- v2m_0: v2m@0 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0 0x10000>; +- }; +- +- v2m@10000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x10000 0x10000>; +- }; +- +- v2m@20000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x20000 0x10000>; +- }; +- +- v2m@30000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x30000 0x10000>; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- /* +- * Juno TRMs specify the size for these coresight components as 64K. +- * The actual size is just 4K though 64K is reserved. Access to the +- * unmapped reserved region results in a DECERR response. +- */ +- etf@20010000 { /* etf0 */ +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0x20010000 0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- +- in-ports { +- port { +- etf0_in_port: endpoint { +- remote-endpoint = <&main_funnel_out_port>; +- }; +- }; +- }; +- +- out-ports { +- port { +- etf0_out_port: endpoint { +- }; +- }; +- }; +- }; +- +- tpiu@20030000 { +- compatible = "arm,coresight-tpiu", "arm,primecell"; +- reg = <0 0x20030000 0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- in-ports { +- port { +- tpiu_in_port: endpoint { +- remote-endpoint = <&replicator_out_port0>; +- }; +- }; +- }; +- }; +- +- /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/ +- main_funnel: funnel@20040000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x20040000 0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- +- out-ports { +- port { +- main_funnel_out_port: endpoint { +- remote-endpoint = <&etf0_in_port>; +- }; +- }; +- }; +- +- main_funnel_in_ports: in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- main_funnel_in_port0: endpoint { +- remote-endpoint = <&cluster0_funnel_out_port>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- main_funnel_in_port1: endpoint { +- remote-endpoint = <&cluster1_funnel_out_port>; +- }; +- }; +- }; +- }; +- +- etr@20070000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0x20070000 0 0x1000>; +- iommus = <&smmu_etr 0>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- arm,scatter-gather; +- in-ports { +- port { +- etr_in_port: endpoint { +- remote-endpoint = <&replicator_out_port1>; +- }; +- }; +- }; +- }; +- +- stm@20100000 { +- compatible = "arm,coresight-stm", "arm,primecell"; +- reg = <0 0x20100000 0 0x1000>, +- <0 0x28000000 0 0x1000000>; +- reg-names = "stm-base", "stm-stimulus-base"; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- out-ports { +- port { +- stm_out_port: endpoint { +- }; +- }; +- }; +- }; +- +- replicator@20120000 { +- compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; +- reg = <0 0x20120000 0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- +- out-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* replicator output ports */ +- port@0 { +- reg = <0>; +- replicator_out_port0: endpoint { +- remote-endpoint = <&tpiu_in_port>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- replicator_out_port1: endpoint { +- remote-endpoint = <&etr_in_port>; +- }; +- }; +- }; +- in-ports { +- port { +- replicator_in_port0: endpoint { +- }; +- }; +- }; +- }; +- +- cpu_debug0: cpu-debug@22010000 { +- compatible = "arm,coresight-cpu-debug", "arm,primecell"; +- reg = <0x0 0x22010000 0x0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- }; +- +- etm0: etm@22040000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x22040000 0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- out-ports { +- port { +- cluster0_etm0_out_port: endpoint { +- remote-endpoint = <&cluster0_funnel_in_port0>; +- }; +- }; +- }; +- }; +- +- funnel@220c0000 { /* cluster0 funnel */ +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x220c0000 0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- out-ports { +- port { +- cluster0_funnel_out_port: endpoint { +- remote-endpoint = <&main_funnel_in_port0>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- cluster0_funnel_in_port0: endpoint { +- remote-endpoint = <&cluster0_etm0_out_port>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- cluster0_funnel_in_port1: endpoint { +- remote-endpoint = <&cluster0_etm1_out_port>; +- }; +- }; +- }; +- }; +- +- cpu_debug1: cpu-debug@22110000 { +- compatible = "arm,coresight-cpu-debug", "arm,primecell"; +- reg = <0x0 0x22110000 0x0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- }; +- +- etm1: etm@22140000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x22140000 0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- out-ports { +- port { +- cluster0_etm1_out_port: endpoint { +- remote-endpoint = <&cluster0_funnel_in_port1>; +- }; +- }; +- }; +- }; +- +- cpu_debug2: cpu-debug@23010000 { +- compatible = "arm,coresight-cpu-debug", "arm,primecell"; +- reg = <0x0 0x23010000 0x0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- }; +- +- etm2: etm@23040000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x23040000 0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- out-ports { +- port { +- cluster1_etm0_out_port: endpoint { +- remote-endpoint = <&cluster1_funnel_in_port0>; +- }; +- }; +- }; +- }; +- +- funnel@230c0000 { /* cluster1 funnel */ +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x230c0000 0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- out-ports { +- port { +- cluster1_funnel_out_port: endpoint { +- remote-endpoint = <&main_funnel_in_port1>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- cluster1_funnel_in_port0: endpoint { +- remote-endpoint = <&cluster1_etm0_out_port>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- cluster1_funnel_in_port1: endpoint { +- remote-endpoint = <&cluster1_etm1_out_port>; +- }; +- }; +- port@2 { +- reg = <2>; +- cluster1_funnel_in_port2: endpoint { +- remote-endpoint = <&cluster1_etm2_out_port>; +- }; +- }; +- port@3 { +- reg = <3>; +- cluster1_funnel_in_port3: endpoint { +- remote-endpoint = <&cluster1_etm3_out_port>; +- }; +- }; +- }; +- }; +- +- cpu_debug3: cpu-debug@23110000 { +- compatible = "arm,coresight-cpu-debug", "arm,primecell"; +- reg = <0x0 0x23110000 0x0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- }; +- +- etm3: etm@23140000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x23140000 0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- out-ports { +- port { +- cluster1_etm1_out_port: endpoint { +- remote-endpoint = <&cluster1_funnel_in_port1>; +- }; +- }; +- }; +- }; +- +- cpu_debug4: cpu-debug@23210000 { +- compatible = "arm,coresight-cpu-debug", "arm,primecell"; +- reg = <0x0 0x23210000 0x0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- }; +- +- etm4: etm@23240000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x23240000 0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- out-ports { +- port { +- cluster1_etm2_out_port: endpoint { +- remote-endpoint = <&cluster1_funnel_in_port2>; +- }; +- }; +- }; +- }; +- +- cpu_debug5: cpu-debug@23310000 { +- compatible = "arm,coresight-cpu-debug", "arm,primecell"; +- reg = <0x0 0x23310000 0x0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- }; +- +- etm5: etm@23340000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x23340000 0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- out-ports { +- port { +- cluster1_etm3_out_port: endpoint { +- remote-endpoint = <&cluster1_funnel_in_port3>; +- }; +- }; +- }; +- }; +- +- gpu: gpu@2d000000 { +- compatible = "arm,juno-mali", "arm,mali-t624"; +- reg = <0 0x2d000000 0 0x10000>; +- interrupts = , +- , +- ; +- interrupt-names = "job", "mmu", "gpu"; +- clocks = <&scpi_dvfs 2>; +- power-domains = <&scpi_devpd 1>; +- dma-coherent; +- /* The SMMU is only really of interest to bare-metal hypervisors */ +- /* iommus = <&smmu_gpu 0>; */ +- status = "disabled"; +- }; +- +- sram: sram@2e000000 { +- compatible = "arm,juno-sram-ns", "mmio-sram"; +- reg = <0x0 0x2e000000 0x0 0x8000>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x0 0x2e000000 0x8000>; +- +- cpu_scp_lpri: scp-sram@0 { +- compatible = "arm,juno-scp-shmem"; +- reg = <0x0 0x200>; +- }; +- +- cpu_scp_hpri: scp-sram@200 { +- compatible = "arm,juno-scp-shmem"; +- reg = <0x200 0x200>; +- }; +- }; +- +- pcie_ctlr: pcie@40000000 { +- compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic"; +- device_type = "pci"; +- reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */ +- bus-range = <0 255>; +- linux,pci-domain = <0>; +- #address-cells = <3>; +- #size-cells = <2>; +- dma-coherent; +- ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>, +- <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>, +- <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; +- /* Standard AXI Translation entries as programmed by EDK2 */ +- dma-ranges = <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>, +- <0x43000000 0x8 0x00000000 0x8 0x00000000 0x2 0x00000000>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; +- msi-parent = <&v2m_0>; +- status = "disabled"; +- iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */ +- iommu-map = <0x0 &smmu_pcie 0x0 0x1>; +- }; +- +- scpi { +- compatible = "arm,scpi"; +- mboxes = <&mailbox 1>; +- shmem = <&cpu_scp_hpri>; +- +- clocks { +- compatible = "arm,scpi-clocks"; +- +- scpi_dvfs: clocks-0 { +- compatible = "arm,scpi-dvfs-clocks"; +- #clock-cells = <1>; +- clock-indices = <0>, <1>, <2>; +- clock-output-names = "atlclk", "aplclk","gpuclk"; +- }; +- scpi_clk: clocks-1 { +- compatible = "arm,scpi-variable-clocks"; +- #clock-cells = <1>; +- clock-indices = <3>; +- clock-output-names = "pxlclk"; +- }; +- }; +- +- scpi_devpd: power-controller { +- compatible = "arm,scpi-power-domains"; +- num-domains = <2>; +- #power-domain-cells = <1>; +- }; +- +- scpi_sensors0: sensors { +- compatible = "arm,scpi-sensors"; +- #thermal-sensor-cells = <1>; +- }; +- }; +- +- thermal-zones { +- pmic { +- polling-delay = <1000>; +- polling-delay-passive = <100>; +- thermal-sensors = <&scpi_sensors0 0>; +- }; +- +- soc { +- polling-delay = <1000>; +- polling-delay-passive = <100>; +- thermal-sensors = <&scpi_sensors0 3>; +- }; +- +- big_cluster_thermal_zone: big-cluster { +- polling-delay = <1000>; +- polling-delay-passive = <100>; +- thermal-sensors = <&scpi_sensors0 21>; +- status = "disabled"; +- }; +- +- little_cluster_thermal_zone: little-cluster { +- polling-delay = <1000>; +- polling-delay-passive = <100>; +- thermal-sensors = <&scpi_sensors0 22>; +- status = "disabled"; +- }; +- +- gpu0_thermal_zone: gpu0 { +- polling-delay = <1000>; +- polling-delay-passive = <100>; +- thermal-sensors = <&scpi_sensors0 23>; +- status = "disabled"; +- }; +- +- gpu1_thermal_zone: gpu1 { +- polling-delay = <1000>; +- polling-delay-passive = <100>; +- thermal-sensors = <&scpi_sensors0 24>; +- status = "disabled"; +- }; +- }; +- +- smmu_dma: iommu@7fb00000 { +- compatible = "arm,mmu-401", "arm,smmu-v1"; +- reg = <0x0 0x7fb00000 0x0 0x10000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- #global-interrupts = <1>; +- dma-coherent; +- }; +- +- smmu_hdlcd1: iommu@7fb10000 { +- compatible = "arm,mmu-401", "arm,smmu-v1"; +- reg = <0x0 0x7fb10000 0x0 0x10000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- #global-interrupts = <1>; +- }; +- +- smmu_hdlcd0: iommu@7fb20000 { +- compatible = "arm,mmu-401", "arm,smmu-v1"; +- reg = <0x0 0x7fb20000 0x0 0x10000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- #global-interrupts = <1>; +- }; +- +- smmu_usb: iommu@7fb30000 { +- compatible = "arm,mmu-401", "arm,smmu-v1"; +- reg = <0x0 0x7fb30000 0x0 0x10000>; +- interrupts = , +- ; +- #iommu-cells = <1>; +- #global-interrupts = <1>; +- dma-coherent; +- }; +- +- dma@7ff00000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0x7ff00000 0 0x1000>; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- iommus = <&smmu_dma 0>, +- <&smmu_dma 1>, +- <&smmu_dma 2>, +- <&smmu_dma 3>, +- <&smmu_dma 4>, +- <&smmu_dma 5>, +- <&smmu_dma 6>, +- <&smmu_dma 7>, +- <&smmu_dma 8>; +- clocks = <&soc_faxiclk>; +- clock-names = "apb_pclk"; +- }; +- +- hdlcd@7ff50000 { +- compatible = "arm,hdlcd"; +- reg = <0 0x7ff50000 0 0x1000>; +- interrupts = ; +- iommus = <&smmu_hdlcd1 0>; +- clocks = <&scpi_clk 3>; +- clock-names = "pxlclk"; +- +- port { +- hdlcd1_output: endpoint { +- remote-endpoint = <&tda998x_1_input>; +- }; +- }; +- }; +- +- hdlcd@7ff60000 { +- compatible = "arm,hdlcd"; +- reg = <0 0x7ff60000 0 0x1000>; +- interrupts = ; +- iommus = <&smmu_hdlcd0 0>; +- clocks = <&scpi_clk 3>; +- clock-names = "pxlclk"; +- +- port { +- hdlcd0_output: endpoint { +- remote-endpoint = <&tda998x_0_input>; +- }; +- }; +- }; +- +- soc_uart0: serial@7ff80000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0x7ff80000 0x0 0x1000>; +- interrupts = ; +- clocks = <&soc_uartclk>, <&soc_refclk100mhz>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- i2c@7ffa0000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0x7ffa0000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clock-frequency = <400000>; +- i2c-sda-hold-time-ns = <500>; +- clocks = <&soc_smc50mhz>; +- +- hdmi-transmitter@70 { +- compatible = "nxp,tda998x"; +- reg = <0x70>; +- port { +- tda998x_0_input: endpoint { +- remote-endpoint = <&hdlcd0_output>; +- }; +- }; +- }; +- +- hdmi-transmitter@71 { +- compatible = "nxp,tda998x"; +- reg = <0x71>; +- port { +- tda998x_1_input: endpoint { +- remote-endpoint = <&hdlcd1_output>; +- }; +- }; +- }; +- }; +- +- usb@7ffb0000 { +- compatible = "generic-ohci"; +- reg = <0x0 0x7ffb0000 0x0 0x10000>; +- interrupts = ; +- iommus = <&smmu_usb 0>; +- clocks = <&soc_usb48mhz>; +- }; +- +- usb@7ffc0000 { +- compatible = "generic-ehci"; +- reg = <0x0 0x7ffc0000 0x0 0x10000>; +- interrupts = ; +- iommus = <&smmu_usb 0>; +- clocks = <&soc_usb48mhz>; +- }; +- +- memory-controller@7ffd0000 { +- compatible = "arm,pl354", "arm,primecell"; +- reg = <0 0x7ffd0000 0 0x1000>; +- interrupts = , +- ; +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- /* last 16MB of the first memory area is reserved for secure world use by firmware */ +- reg = <0x00000000 0x80000000 0x0 0x7f000000>, +- <0x00000008 0x80000000 0x1 0x80000000>; +- }; +- +- bus@8000000 { +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 15>; +- interrupt-map = <0 0 0 &gic 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 1 &gic 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 2 &gic 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- site2: tlx-bus@60000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x60000000 0x10000000>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0>; +- interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/arm/juno-clocks.dtsi b/scripts/dtc/include-prefixes/arm64/arm/juno-clocks.dtsi +deleted file mode 100644 +index 2870b5eeb198..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/juno-clocks.dtsi ++++ /dev/null +@@ -1,45 +0,0 @@ +-/* +- * ARM Juno Platform clocks +- * +- * Copyright (c) 2013-2014 ARM Ltd +- * +- * This file is licensed under a dual GPLv2 or BSD license. +- * +- */ +-/ { +- /* SoC fixed clocks */ +- soc_uartclk: refclk7372800hz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <7372800>; +- clock-output-names = "juno:uartclk"; +- }; +- +- soc_usb48mhz: clk48mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <48000000>; +- clock-output-names = "clk48mhz"; +- }; +- +- soc_smc50mhz: clk50mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- clock-output-names = "smc_clk"; +- }; +- +- soc_refclk100mhz: refclk100mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- clock-output-names = "apb_pclk"; +- }; +- +- soc_faxiclk: refclk400mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <400000000>; +- clock-output-names = "faxi_clk"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/arm/juno-cs-r1r2.dtsi b/scripts/dtc/include-prefixes/arm64/arm/juno-cs-r1r2.dtsi +deleted file mode 100644 +index eda3d9e18af6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/juno-cs-r1r2.dtsi ++++ /dev/null +@@ -1,85 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- funnel@20130000 { /* cssys1 */ +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x20130000 0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- out-ports { +- port { +- csys1_funnel_out_port: endpoint { +- remote-endpoint = <&etf1_in_port>; +- }; +- }; +- }; +- in-ports { +- port { +- csys1_funnel_in_port0: endpoint { +- }; +- }; +- +- }; +- }; +- +- etf@20140000 { /* etf1 */ +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0x20140000 0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- in-ports { +- port { +- etf1_in_port: endpoint { +- remote-endpoint = <&csys1_funnel_out_port>; +- }; +- }; +- }; +- out-ports { +- port { +- etf1_out_port: endpoint { +- remote-endpoint = <&csys2_funnel_in_port1>; +- }; +- }; +- }; +- }; +- +- funnel@20150000 { /* cssys2 */ +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x20150000 0 0x1000>; +- +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- power-domains = <&scpi_devpd 0>; +- out-ports { +- port { +- csys2_funnel_out_port: endpoint { +- remote-endpoint = <&replicator_in_port0>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- csys2_funnel_in_port0: endpoint { +- slave-mode; +- remote-endpoint = <&etf0_out_port>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- csys2_funnel_in_port1: endpoint { +- slave-mode; +- remote-endpoint = <&etf1_out_port>; +- }; +- }; +- +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/arm/juno-motherboard.dtsi b/scripts/dtc/include-prefixes/arm64/arm/juno-motherboard.dtsi +deleted file mode 100644 +index fefd2b5f0176..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/juno-motherboard.dtsi ++++ /dev/null +@@ -1,302 +0,0 @@ +-/* +- * ARM Juno Platform motherboard peripherals +- * +- * Copyright (c) 2013-2014 ARM Ltd +- * +- * This file is licensed under a dual GPLv2 or BSD license. +- * +- */ +- +-/ { +- mb_clk24mhz: clk24mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "juno_mb:clk24mhz"; +- }; +- +- mb_clk25mhz: clk25mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- clock-output-names = "juno_mb:clk25mhz"; +- }; +- +- v2m_refclk1mhz: refclk1mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <1000000>; +- clock-output-names = "juno_mb:refclk1mhz"; +- }; +- +- v2m_refclk32khz: refclk32khz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "juno_mb:refclk32khz"; +- }; +- +- mb_fixed_3v3: mcc-sb-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "MCC_SB_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power-button { +- debounce-interval = <50>; +- wakeup-source; +- linux,code = <116>; +- label = "POWER"; +- gpios = <&iofpga_gpio0 0 0x4>; +- }; +- home-button { +- debounce-interval = <50>; +- wakeup-source; +- linux,code = <102>; +- label = "HOME"; +- gpios = <&iofpga_gpio0 1 0x4>; +- }; +- rlock-button { +- debounce-interval = <50>; +- wakeup-source; +- linux,code = <152>; +- label = "RLOCK"; +- gpios = <&iofpga_gpio0 2 0x4>; +- }; +- vol-up-button { +- debounce-interval = <50>; +- wakeup-source; +- linux,code = <115>; +- label = "VOL+"; +- gpios = <&iofpga_gpio0 3 0x4>; +- }; +- vol-down-button { +- debounce-interval = <50>; +- wakeup-source; +- linux,code = <114>; +- label = "VOL-"; +- gpios = <&iofpga_gpio0 4 0x4>; +- }; +- nmi-button { +- debounce-interval = <50>; +- wakeup-source; +- linux,code = <99>; +- label = "NMI"; +- gpios = <&iofpga_gpio0 5 0x4>; +- }; +- }; +- +- bus@8000000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0x8000000 0 0x8000000 0x18000000>; +- +- motherboard-bus@8000000 { +- compatible = "arm,vexpress,v2p-p1", "simple-bus"; +- #address-cells = <2>; /* SMB chipselect number and offset */ +- #size-cells = <1>; +- ranges = <0 0 0 0x08000000 0x04000000>, +- <1 0 0 0x14000000 0x04000000>, +- <2 0 0 0x18000000 0x04000000>, +- <3 0 0 0x1c000000 0x04000000>, +- <4 0 0 0x0c000000 0x04000000>, +- <5 0 0 0x10000000 0x04000000>; +- arm,hbi = <0x252>; +- arm,vexpress,site = <0>; +- +- flash@0 { +- /* 2 * 32MiB NOR Flash memory mounted on CS0 */ +- compatible = "arm,vexpress-flash", "cfi-flash"; +- reg = <0 0x00000000 0x04000000>; +- bank-width = <4>; +- /* +- * Unfortunately, accessing the flash disturbs +- * the CPU idle states (suspend) and CPU +- * hotplug of the platform. For this reason, +- * flash hardware access is disabled by default. +- */ +- status = "disabled"; +- partitions { +- compatible = "arm,arm-firmware-suite"; +- }; +- }; +- +- ethernet@200000000 { +- compatible = "smsc,lan9118", "smsc,lan9115"; +- reg = <2 0x00000000 0x10000>; +- interrupts = <3>; +- phy-mode = "mii"; +- reg-io-width = <4>; +- smsc,irq-active-high; +- smsc,irq-push-pull; +- clocks = <&mb_clk25mhz>; +- vdd33a-supply = <&mb_fixed_3v3>; +- vddvario-supply = <&mb_fixed_3v3>; +- }; +- +- iofpga-bus@300000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 3 0 0x200000>; +- +- v2m_sysctl: sysctl@20000 { +- compatible = "arm,sp810", "arm,primecell"; +- reg = <0x020000 0x1000>; +- clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>; +- clock-names = "refclk", "timclk", "apb_pclk"; +- #clock-cells = <1>; +- clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; +- assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; +- assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; +- }; +- +- apbregs@10000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x010000 0x1000>; +- +- led0 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x01>; +- label = "vexpress:0"; +- linux,default-trigger = "heartbeat"; +- default-state = "on"; +- }; +- led1 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x02>; +- label = "vexpress:1"; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- led2 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x04>; +- label = "vexpress:2"; +- linux,default-trigger = "cpu0"; +- default-state = "off"; +- }; +- led3 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x08>; +- label = "vexpress:3"; +- linux,default-trigger = "cpu1"; +- default-state = "off"; +- }; +- led4 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x10>; +- label = "vexpress:4"; +- linux,default-trigger = "cpu2"; +- default-state = "off"; +- }; +- led5 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x20>; +- label = "vexpress:5"; +- linux,default-trigger = "cpu3"; +- default-state = "off"; +- }; +- led6 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x40>; +- label = "vexpress:6"; +- default-state = "off"; +- }; +- led7 { +- compatible = "register-bit-led"; +- offset = <0x08>; +- mask = <0x80>; +- label = "vexpress:7"; +- default-state = "off"; +- }; +- }; +- +- mmc@50000 { +- compatible = "arm,pl180", "arm,primecell"; +- reg = <0x050000 0x1000>; +- interrupts = <5>; +- /* cd-gpios = <&v2m_mmc_gpios 0 0>; +- wp-gpios = <&v2m_mmc_gpios 1 0>; */ +- max-frequency = <12000000>; +- vmmc-supply = <&mb_fixed_3v3>; +- clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; +- clock-names = "mclk", "apb_pclk"; +- }; +- +- kmi@60000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x060000 0x1000>; +- interrupts = <8>; +- clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- kmi@70000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x070000 0x1000>; +- interrupts = <8>; +- clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- watchdog@f0000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0f0000 0x10000>; +- interrupts = <7>; +- clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- v2m_timer01: timer@110000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x110000 0x10000>; +- interrupts = <9>; +- clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>; +- clock-names = "timclken1", "timclken2", "apb_pclk"; +- }; +- +- v2m_timer23: timer@120000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x120000 0x10000>; +- interrupts = <9>; +- clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>; +- clock-names = "timclken1", "timclken2", "apb_pclk"; +- }; +- +- rtc@170000 { +- compatible = "arm,pl031", "arm,primecell"; +- reg = <0x170000 0x10000>; +- interrupts = <0>; +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- }; +- +- iofpga_gpio0: gpio@1d0000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x1d0000 0x1000>; +- interrupts = <6>; +- clocks = <&soc_smc50mhz>; +- clock-names = "apb_pclk"; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/arm/juno-r1.dts b/scripts/dtc/include-prefixes/arm64/arm/juno-r1.dts +deleted file mode 100644 +index 0e24e29eb9b1..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/juno-r1.dts ++++ /dev/null +@@ -1,315 +0,0 @@ +-/* +- * ARM Ltd. Juno Platform +- * +- * Copyright (c) 2015 ARM Ltd. +- * +- * This file is licensed under a dual GPLv2 or BSD license. +- */ +- +-/dts-v1/; +- +-#include +-#include "juno-base.dtsi" +-#include "juno-cs-r1r2.dtsi" +- +-/ { +- model = "ARM Juno development board (r1)"; +- compatible = "arm,juno-r1", "arm,juno", "arm,vexpress"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- serial0 = &soc_uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&A57_0>; +- }; +- core1 { +- cpu = <&A57_1>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&A53_0>; +- }; +- core1 { +- cpu = <&A53_1>; +- }; +- core2 { +- cpu = <&A53_2>; +- }; +- core3 { +- cpu = <&A53_3>; +- }; +- }; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP_0: cpu-sleep-0 { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x0010000>; +- local-timer-stop; +- entry-latency-us = <300>; +- exit-latency-us = <1200>; +- min-residency-us = <2000>; +- }; +- +- CLUSTER_SLEEP_0: cluster-sleep-0 { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x1010000>; +- local-timer-stop; +- entry-latency-us = <400>; +- exit-latency-us = <1200>; +- min-residency-us = <2500>; +- }; +- }; +- +- A57_0: cpu@0 { +- compatible = "arm,cortex-a57"; +- reg = <0x0 0x0>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&A57_L2>; +- clocks = <&scpi_dvfs 0>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <1024>; +- }; +- +- A57_1: cpu@1 { +- compatible = "arm,cortex-a57"; +- reg = <0x0 0x1>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&A57_L2>; +- clocks = <&scpi_dvfs 0>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <1024>; +- }; +- +- A53_0: cpu@100 { +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x100>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&A53_L2>; +- clocks = <&scpi_dvfs 1>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <578>; +- }; +- +- A53_1: cpu@101 { +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x101>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&A53_L2>; +- clocks = <&scpi_dvfs 1>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <578>; +- }; +- +- A53_2: cpu@102 { +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x102>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&A53_L2>; +- clocks = <&scpi_dvfs 1>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <578>; +- }; +- +- A53_3: cpu@103 { +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x103>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&A53_L2>; +- clocks = <&scpi_dvfs 1>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <578>; +- }; +- +- A57_L2: l2-cache0 { +- compatible = "cache"; +- cache-size = <0x200000>; +- cache-line-size = <64>; +- cache-sets = <2048>; +- }; +- +- A53_L2: l2-cache1 { +- compatible = "cache"; +- cache-size = <0x100000>; +- cache-line-size = <64>; +- cache-sets = <1024>; +- }; +- }; +- +- pmu-a57 { +- compatible = "arm,cortex-a57-pmu"; +- interrupts = , +- ; +- interrupt-affinity = <&A57_0>, +- <&A57_1>; +- }; +- +- pmu-a53 { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&A53_0>, +- <&A53_1>, +- <&A53_2>, +- <&A53_3>; +- }; +-}; +- +-&memtimer { +- status = "okay"; +-}; +- +-&pcie_ctlr { +- status = "okay"; +-}; +- +-&smmu_pcie { +- status = "okay"; +-}; +- +-&etm0 { +- cpu = <&A57_0>; +-}; +- +-&etm1 { +- cpu = <&A57_1>; +-}; +- +-&etm2 { +- cpu = <&A53_0>; +-}; +- +-&etm3 { +- cpu = <&A53_1>; +-}; +- +-&etm4 { +- cpu = <&A53_2>; +-}; +- +-&etm5 { +- cpu = <&A53_3>; +-}; +- +-&big_cluster_thermal_zone { +- status = "okay"; +-}; +- +-&little_cluster_thermal_zone { +- status = "okay"; +-}; +- +-&gpu0_thermal_zone { +- status = "okay"; +-}; +- +-&gpu1_thermal_zone { +- status = "okay"; +-}; +- +-&etf0_out_port { +- remote-endpoint = <&csys2_funnel_in_port0>; +-}; +- +-&replicator_in_port0 { +- remote-endpoint = <&csys2_funnel_out_port>; +-}; +- +-&csys1_funnel_in_port0 { +- remote-endpoint = <&stm_out_port>; +-}; +- +-&stm_out_port { +- remote-endpoint = <&csys1_funnel_in_port0>; +-}; +- +-&cpu_debug0 { +- cpu = <&A57_0>; +-}; +- +-&cpu_debug1 { +- cpu = <&A57_1>; +-}; +- +-&cpu_debug2 { +- cpu = <&A53_0>; +-}; +- +-&cpu_debug3 { +- cpu = <&A53_1>; +-}; +- +-&cpu_debug4 { +- cpu = <&A53_2>; +-}; +- +-&cpu_debug5 { +- cpu = <&A53_3>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/arm/juno-r2.dts b/scripts/dtc/include-prefixes/arm64/arm/juno-r2.dts +deleted file mode 100644 +index e609420ce3e4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/juno-r2.dts ++++ /dev/null +@@ -1,321 +0,0 @@ +-/* +- * ARM Ltd. Juno Platform +- * +- * Copyright (c) 2015 ARM Ltd. +- * +- * This file is licensed under a dual GPLv2 or BSD license. +- */ +- +-/dts-v1/; +- +-#include +-#include "juno-base.dtsi" +-#include "juno-cs-r1r2.dtsi" +- +-/ { +- model = "ARM Juno development board (r2)"; +- compatible = "arm,juno-r2", "arm,juno", "arm,vexpress"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- serial0 = &soc_uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&A72_0>; +- }; +- core1 { +- cpu = <&A72_1>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&A53_0>; +- }; +- core1 { +- cpu = <&A53_1>; +- }; +- core2 { +- cpu = <&A53_2>; +- }; +- core3 { +- cpu = <&A53_3>; +- }; +- }; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP_0: cpu-sleep-0 { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x0010000>; +- local-timer-stop; +- entry-latency-us = <300>; +- exit-latency-us = <1200>; +- min-residency-us = <2000>; +- }; +- +- CLUSTER_SLEEP_0: cluster-sleep-0 { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x1010000>; +- local-timer-stop; +- entry-latency-us = <400>; +- exit-latency-us = <1200>; +- min-residency-us = <2500>; +- }; +- }; +- +- A72_0: cpu@0 { +- compatible = "arm,cortex-a72"; +- reg = <0x0 0x0>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&A72_L2>; +- clocks = <&scpi_dvfs 0>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <450>; +- }; +- +- A72_1: cpu@1 { +- compatible = "arm,cortex-a72"; +- reg = <0x0 0x1>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&A72_L2>; +- clocks = <&scpi_dvfs 0>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <450>; +- }; +- +- A53_0: cpu@100 { +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x100>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&A53_L2>; +- clocks = <&scpi_dvfs 1>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <485>; +- dynamic-power-coefficient = <140>; +- }; +- +- A53_1: cpu@101 { +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x101>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&A53_L2>; +- clocks = <&scpi_dvfs 1>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <485>; +- dynamic-power-coefficient = <140>; +- }; +- +- A53_2: cpu@102 { +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x102>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&A53_L2>; +- clocks = <&scpi_dvfs 1>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <485>; +- dynamic-power-coefficient = <140>; +- }; +- +- A53_3: cpu@103 { +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x103>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&A53_L2>; +- clocks = <&scpi_dvfs 1>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <485>; +- dynamic-power-coefficient = <140>; +- }; +- +- A72_L2: l2-cache0 { +- compatible = "cache"; +- cache-size = <0x200000>; +- cache-line-size = <64>; +- cache-sets = <2048>; +- }; +- +- A53_L2: l2-cache1 { +- compatible = "cache"; +- cache-size = <0x100000>; +- cache-line-size = <64>; +- cache-sets = <1024>; +- }; +- }; +- +- pmu-a72 { +- compatible = "arm,cortex-a72-pmu"; +- interrupts = , +- ; +- interrupt-affinity = <&A72_0>, +- <&A72_1>; +- }; +- +- pmu-a53 { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&A53_0>, +- <&A53_1>, +- <&A53_2>, +- <&A53_3>; +- }; +-}; +- +-&memtimer { +- status = "okay"; +-}; +- +-&pcie_ctlr { +- status = "okay"; +-}; +- +-&smmu_pcie { +- status = "okay"; +-}; +- +-&etm0 { +- cpu = <&A72_0>; +-}; +- +-&etm1 { +- cpu = <&A72_1>; +-}; +- +-&etm2 { +- cpu = <&A53_0>; +-}; +- +-&etm3 { +- cpu = <&A53_1>; +-}; +- +-&etm4 { +- cpu = <&A53_2>; +-}; +- +-&etm5 { +- cpu = <&A53_3>; +-}; +- +-&big_cluster_thermal_zone { +- status = "okay"; +-}; +- +-&little_cluster_thermal_zone { +- status = "okay"; +-}; +- +-&gpu0_thermal_zone { +- status = "okay"; +-}; +- +-&gpu1_thermal_zone { +- status = "okay"; +-}; +- +-&etf0_out_port { +- remote-endpoint = <&csys2_funnel_in_port0>; +-}; +- +-&replicator_in_port0 { +- remote-endpoint = <&csys2_funnel_out_port>; +-}; +- +-&csys1_funnel_in_port0 { +- remote-endpoint = <&stm_out_port>; +-}; +- +-&stm_out_port { +- remote-endpoint = <&csys1_funnel_in_port0>; +-}; +- +-&cpu_debug0 { +- cpu = <&A72_0>; +-}; +- +-&cpu_debug1 { +- cpu = <&A72_1>; +-}; +- +-&cpu_debug2 { +- cpu = <&A53_0>; +-}; +- +-&cpu_debug3 { +- cpu = <&A53_1>; +-}; +- +-&cpu_debug4 { +- cpu = <&A53_2>; +-}; +- +-&cpu_debug5 { +- cpu = <&A53_3>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/arm/juno.dts b/scripts/dtc/include-prefixes/arm64/arm/juno.dts +deleted file mode 100644 +index f00cffbd032c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/juno.dts ++++ /dev/null +@@ -1,297 +0,0 @@ +-/* +- * ARM Ltd. Juno Platform +- * +- * Copyright (c) 2013-2014 ARM Ltd. +- * +- * This file is licensed under a dual GPLv2 or BSD license. +- */ +- +-/dts-v1/; +- +-#include +-#include "juno-base.dtsi" +- +-/ { +- model = "ARM Juno development board (r0)"; +- compatible = "arm,juno", "arm,vexpress"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- serial0 = &soc_uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&A57_0>; +- }; +- core1 { +- cpu = <&A57_1>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&A53_0>; +- }; +- core1 { +- cpu = <&A53_1>; +- }; +- core2 { +- cpu = <&A53_2>; +- }; +- core3 { +- cpu = <&A53_3>; +- }; +- }; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP_0: cpu-sleep-0 { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x0010000>; +- local-timer-stop; +- entry-latency-us = <300>; +- exit-latency-us = <1200>; +- min-residency-us = <2000>; +- }; +- +- CLUSTER_SLEEP_0: cluster-sleep-0 { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x1010000>; +- local-timer-stop; +- entry-latency-us = <400>; +- exit-latency-us = <1200>; +- min-residency-us = <2500>; +- }; +- }; +- +- A57_0: cpu@0 { +- compatible = "arm,cortex-a57"; +- reg = <0x0 0x0>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&A57_L2>; +- clocks = <&scpi_dvfs 0>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <530>; +- }; +- +- A57_1: cpu@1 { +- compatible = "arm,cortex-a57"; +- reg = <0x0 0x1>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&A57_L2>; +- clocks = <&scpi_dvfs 0>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <530>; +- }; +- +- A53_0: cpu@100 { +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x100>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&A53_L2>; +- clocks = <&scpi_dvfs 1>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <578>; +- dynamic-power-coefficient = <140>; +- }; +- +- A53_1: cpu@101 { +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x101>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&A53_L2>; +- clocks = <&scpi_dvfs 1>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <578>; +- dynamic-power-coefficient = <140>; +- }; +- +- A53_2: cpu@102 { +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x102>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&A53_L2>; +- clocks = <&scpi_dvfs 1>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <578>; +- dynamic-power-coefficient = <140>; +- }; +- +- A53_3: cpu@103 { +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x103>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&A53_L2>; +- clocks = <&scpi_dvfs 1>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <578>; +- dynamic-power-coefficient = <140>; +- }; +- +- A57_L2: l2-cache0 { +- compatible = "cache"; +- cache-size = <0x200000>; +- cache-line-size = <64>; +- cache-sets = <2048>; +- }; +- +- A53_L2: l2-cache1 { +- compatible = "cache"; +- cache-size = <0x100000>; +- cache-line-size = <64>; +- cache-sets = <1024>; +- }; +- }; +- +- pmu-a57 { +- compatible = "arm,cortex-a57-pmu"; +- interrupts = , +- ; +- interrupt-affinity = <&A57_0>, +- <&A57_1>; +- }; +- +- pmu-a53 { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&A53_0>, +- <&A53_1>, +- <&A53_2>, +- <&A53_3>; +- }; +-}; +- +-&etm0 { +- cpu = <&A57_0>; +-}; +- +-&etm1 { +- cpu = <&A57_1>; +-}; +- +-&etm2 { +- cpu = <&A53_0>; +-}; +- +-&etm3 { +- cpu = <&A53_1>; +-}; +- +-&etm4 { +- cpu = <&A53_2>; +-}; +- +-&etm5 { +- cpu = <&A53_3>; +-}; +- +-&etf0_out_port { +- remote-endpoint = <&replicator_in_port0>; +-}; +- +-&replicator_in_port0 { +- remote-endpoint = <&etf0_out_port>; +-}; +- +-&stm_out_port { +- remote-endpoint = <&main_funnel_in_port2>; +-}; +- +-&main_funnel_in_ports { +- port@2 { +- reg = <2>; +- main_funnel_in_port2: endpoint { +- remote-endpoint = <&stm_out_port>; +- }; +- }; +-}; +- +-&cpu_debug0 { +- cpu = <&A57_0>; +-}; +- +-&cpu_debug1 { +- cpu = <&A57_1>; +-}; +- +-&cpu_debug2 { +- cpu = <&A53_0>; +-}; +- +-&cpu_debug3 { +- cpu = <&A53_1>; +-}; +- +-&cpu_debug4 { +- cpu = <&A53_2>; +-}; +- +-&cpu_debug5 { +- cpu = <&A53_3>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/arm/rtsm_ve-aemv8a.dts b/scripts/dtc/include-prefixes/arm64/arm/rtsm_ve-aemv8a.dts +deleted file mode 100644 +index 258991ad7cc0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/rtsm_ve-aemv8a.dts ++++ /dev/null +@@ -1,182 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * ARM Ltd. Fast Models +- * +- * Architecture Envelope Model (AEM) ARMv8-A +- * ARMAEMv8AMPCT +- * +- * RTSM_VE_AEMv8A.lisa +- */ +- +-/dts-v1/; +- +-#include +- +-/memreserve/ 0x80000000 0x00010000; +- +-#include "rtsm_ve-motherboard.dtsi" +- +-/ { +- model = "RTSM_VE_AEMv8A"; +- compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- chosen { }; +- +- aliases { +- serial0 = &v2m_serial0; +- serial1 = &v2m_serial1; +- serial2 = &v2m_serial2; +- serial3 = &v2m_serial3; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,armv8"; +- reg = <0x0 0x0>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x8000fff8>; +- next-level-cache = <&L2_0>; +- }; +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,armv8"; +- reg = <0x0 0x1>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x8000fff8>; +- next-level-cache = <&L2_0>; +- }; +- cpu@2 { +- device_type = "cpu"; +- compatible = "arm,armv8"; +- reg = <0x0 0x2>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x8000fff8>; +- next-level-cache = <&L2_0>; +- }; +- cpu@3 { +- device_type = "cpu"; +- compatible = "arm,armv8"; +- reg = <0x0 0x3>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x8000fff8>; +- next-level-cache = <&L2_0>; +- }; +- +- L2_0: l2-cache0 { +- compatible = "cache"; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0 0x80000000>, +- <0x00000008 0x80000000 0 0x80000000>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- /* Chipselect 2,00000000 is physically at 0x18000000 */ +- vram: vram@18000000 { +- /* 8 MB of designated video RAM */ +- compatible = "shared-dma-pool"; +- reg = <0x00000000 0x18000000 0 0x00800000>; +- no-map; +- }; +- }; +- +- gic: interrupt-controller@2c001000 { +- compatible = "arm,gic-400", "arm,cortex-a15-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x0 0x2c001000 0 0x1000>, +- <0x0 0x2c002000 0 0x2000>, +- <0x0 0x2c004000 0 0x2000>, +- <0x0 0x2c006000 0 0x2000>; +- interrupts = ; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- clock-frequency = <100000000>; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = , +- , +- , +- ; +- }; +- +- panel { +- compatible = "arm,rtsm-display"; +- port { +- panel_in: endpoint { +- remote-endpoint = <&clcd_pads>; +- }; +- }; +- }; +- +- bus@8000000 { +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 63>; +- interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/arm/rtsm_ve-motherboard-rs2.dtsi b/scripts/dtc/include-prefixes/arm64/arm/rtsm_ve-motherboard-rs2.dtsi +deleted file mode 100644 +index 33182d9e5826..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/rtsm_ve-motherboard-rs2.dtsi ++++ /dev/null +@@ -1,27 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * ARM Ltd. Fast Models +- * +- * "rs2" extension for the v2m motherboard +- */ +-/ { +- bus@8000000 { +- motherboard-bus@8000000 { +- arm,v2m-memory-map = "rs2"; +- +- iofpga-bus@300000000 { +- virtio-p9@140000 { +- compatible = "virtio,mmio"; +- reg = <0x140000 0x200>; +- interrupts = <43>; +- }; +- +- virtio-net@150000 { +- compatible = "virtio,mmio"; +- reg = <0x150000 0x200>; +- interrupts = <44>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/arm/rtsm_ve-motherboard.dtsi b/scripts/dtc/include-prefixes/arm64/arm/rtsm_ve-motherboard.dtsi +deleted file mode 100644 +index 5f6cab668aa0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/rtsm_ve-motherboard.dtsi ++++ /dev/null +@@ -1,258 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * ARM Ltd. Fast Models +- * +- * Versatile Express (VE) system model +- * Motherboard component +- * +- * VEMotherBoard.lisa +- */ +-/ { +- v2m_clk24mhz: clk24mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "v2m:clk24mhz"; +- }; +- +- v2m_refclk1mhz: refclk1mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <1000000>; +- clock-output-names = "v2m:refclk1mhz"; +- }; +- +- v2m_refclk32khz: refclk32khz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "v2m:refclk32khz"; +- }; +- +- v2m_fixed_3v3: v2m-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- mcc { +- compatible = "arm,vexpress,config-bus"; +- arm,vexpress,config-bridge = <&v2m_sysreg>; +- +- v2m_oscclk1: oscclk1 { +- /* CLCD clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 1>; +- freq-range = <23750000 63500000>; +- #clock-cells = <0>; +- clock-output-names = "v2m:oscclk1"; +- }; +- +- reset { +- compatible = "arm,vexpress-reset"; +- arm,vexpress-sysreg,func = <5 0>; +- }; +- +- muxfpga { +- compatible = "arm,vexpress-muxfpga"; +- arm,vexpress-sysreg,func = <7 0>; +- }; +- +- shutdown { +- compatible = "arm,vexpress-shutdown"; +- arm,vexpress-sysreg,func = <8 0>; +- }; +- +- reboot { +- compatible = "arm,vexpress-reboot"; +- arm,vexpress-sysreg,func = <9 0>; +- }; +- +- dvimode { +- compatible = "arm,vexpress-dvimode"; +- arm,vexpress-sysreg,func = <11 0>; +- }; +- }; +- +- bus@8000000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0x8000000 0 0x8000000 0x18000000>; +- +- motherboard-bus@8000000 { +- compatible = "arm,vexpress,v2m-p1", "simple-bus"; +- #address-cells = <2>; /* SMB chipselect number and offset */ +- #size-cells = <1>; +- ranges = <0 0 0 0x08000000 0x04000000>, +- <1 0 0 0x14000000 0x04000000>, +- <2 0 0 0x18000000 0x04000000>, +- <3 0 0 0x1c000000 0x04000000>, +- <4 0 0 0x0c000000 0x04000000>, +- <5 0 0 0x10000000 0x04000000>; +- +- flash@0 { +- compatible = "arm,vexpress-flash", "cfi-flash"; +- reg = <0 0x00000000 0x04000000>, +- <4 0x00000000 0x04000000>; +- bank-width = <4>; +- }; +- +- ethernet@202000000 { +- compatible = "smsc,lan91c111"; +- reg = <2 0x02000000 0x10000>; +- interrupts = <15>; +- }; +- +- iofpga-bus@300000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 3 0 0x200000>; +- +- v2m_sysreg: sysreg@10000 { +- compatible = "arm,vexpress-sysreg"; +- reg = <0x010000 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- v2m_sysctl: sysctl@20000 { +- compatible = "arm,sp810", "arm,primecell"; +- reg = <0x020000 0x1000>; +- clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; +- clock-names = "refclk", "timclk", "apb_pclk"; +- #clock-cells = <1>; +- clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; +- assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; +- assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; +- }; +- +- aaci@40000 { +- compatible = "arm,pl041", "arm,primecell"; +- reg = <0x040000 0x1000>; +- interrupts = <11>; +- clocks = <&v2m_clk24mhz>; +- clock-names = "apb_pclk"; +- }; +- +- mmc@50000 { +- compatible = "arm,pl180", "arm,primecell"; +- reg = <0x050000 0x1000>; +- interrupts = <9>, <10>; +- cd-gpios = <&v2m_sysreg 0 0>; +- wp-gpios = <&v2m_sysreg 1 0>; +- max-frequency = <12000000>; +- vmmc-supply = <&v2m_fixed_3v3>; +- clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; +- clock-names = "mclk", "apb_pclk"; +- }; +- +- kmi@60000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x060000 0x1000>; +- interrupts = <12>; +- clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- kmi@70000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x070000 0x1000>; +- interrupts = <13>; +- clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- v2m_serial0: serial@90000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x090000 0x1000>; +- interrupts = <5>; +- clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- v2m_serial1: serial@a0000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0a0000 0x1000>; +- interrupts = <6>; +- clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- v2m_serial2: serial@b0000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0b0000 0x1000>; +- interrupts = <7>; +- clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- v2m_serial3: serial@c0000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0c0000 0x1000>; +- interrupts = <8>; +- clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- watchdog@f0000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0f0000 0x1000>; +- interrupts = <0>; +- clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- v2m_timer01: timer@110000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x110000 0x1000>; +- interrupts = <2>; +- clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; +- clock-names = "timclken1", "timclken2", "apb_pclk"; +- }; +- +- v2m_timer23: timer@120000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x120000 0x1000>; +- interrupts = <3>; +- clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; +- clock-names = "timclken1", "timclken2", "apb_pclk"; +- }; +- +- virtio-block@130000 { +- compatible = "virtio,mmio"; +- reg = <0x130000 0x200>; +- interrupts = <42>; +- }; +- +- rtc@170000 { +- compatible = "arm,pl031", "arm,primecell"; +- reg = <0x170000 0x1000>; +- interrupts = <4>; +- clocks = <&v2m_clk24mhz>; +- clock-names = "apb_pclk"; +- }; +- +- clcd@1f0000 { +- compatible = "arm,pl111", "arm,primecell"; +- reg = <0x1f0000 0x1000>; +- interrupt-names = "combined"; +- interrupts = <14>; +- clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; +- clock-names = "clcdclk", "apb_pclk"; +- memory-region = <&vram>; +- +- port { +- clcd_pads: endpoint { +- remote-endpoint = <&panel_in>; +- arm,pl11x,tft-r0g0b0-pads = <0 8 16>; +- }; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts b/scripts/dtc/include-prefixes/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts +deleted file mode 100644 +index 5b6d9d8e934d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts ++++ /dev/null +@@ -1,150 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * ARM Ltd. Versatile Express +- * +- * LogicTile Express 20MG +- * V2F-1XV7 +- * +- * Cortex-A53 (2 cores) Soft Macrocell Model +- * +- * HBI-0247C +- */ +- +-/dts-v1/; +- +-#include +-#include "vexpress-v2m-rs1.dtsi" +- +-/ { +- model = "V2F-1XV7 Cortex-A53x2 SMM"; +- arm,hbi = <0x247>; +- arm,vexpress,site = <0xf>; +- compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- chosen { +- stdout-path = "serial0:38400n8"; +- }; +- +- aliases { +- serial0 = &v2m_serial0; +- serial1 = &v2m_serial1; +- serial2 = &v2m_serial2; +- serial3 = &v2m_serial3; +- i2c0 = &v2m_i2c_dvi; +- i2c1 = &v2m_i2c_pcie; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0 0>; +- next-level-cache = <&L2_0>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0 1>; +- next-level-cache = <&L2_0>; +- }; +- +- L2_0: l2-cache0 { +- compatible = "cache"; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */ +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- /* Chipselect 2 is physically at 0x18000000 */ +- vram: vram@18000000 { +- /* 8 MB of designated video RAM */ +- compatible = "shared-dma-pool"; +- reg = <0 0x18000000 0 0x00800000>; +- no-map; +- }; +- }; +- +- gic: interrupt-controller@2c001000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0 0x2c001000 0 0x1000>, +- <0 0x2c002000 0 0x2000>, +- <0 0x2c004000 0 0x2000>, +- <0 0x2c006000 0 0x2000>; +- interrupts = ; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = , +- ; +- }; +- +- dcc { +- compatible = "arm,vexpress,config-bus"; +- arm,vexpress,config-bridge = <&v2m_sysreg>; +- +- smbclk: smclk { +- /* SMC clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 4>; +- freq-range = <40000000 40000000>; +- #clock-cells = <0>; +- clock-output-names = "smclk"; +- }; +- +- volt-vio { +- /* VIO to expansion board above */ +- compatible = "arm,vexpress-volt"; +- arm,vexpress-sysreg,func = <2 0>; +- regulator-name = "VIO_UP"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- volt-12v { +- /* 12V from power connector J6 */ +- compatible = "arm,vexpress-volt"; +- arm,vexpress-sysreg,func = <2 1>; +- regulator-name = "12"; +- regulator-always-on; +- }; +- +- temp-fpga { +- /* FPGA temperature */ +- compatible = "arm,vexpress-temp"; +- arm,vexpress-sysreg,func = <4 0>; +- label = "FPGA"; +- }; +- }; +- +- smb: bus@8000000 { +- ranges = <0x8000000 0 0x8000000 0x18000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/arm/vexpress-v2m-rs1.dtsi b/scripts/dtc/include-prefixes/arm64/arm/vexpress-v2m-rs1.dtsi +deleted file mode 100644 +index 8af4b77fe655..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/arm/vexpress-v2m-rs1.dtsi ++++ /dev/null +@@ -1,494 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * ARM Ltd. Versatile Express +- * +- * Motherboard Express uATX +- * V2M-P1 +- * +- * HBI-0190D +- * +- * RS1 memory map ("ARM Cortex-A Series memory map" in the board's +- * Technical Reference Manual) +- * +- * WARNING! The hardware described in this file is independent from the +- * original variant (vexpress-v2m.dtsi), but there is a strong +- * correspondence between the two configurations. +- * +- * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT +- * CHANGES TO vexpress-v2m.dtsi! +- */ +-#include +- +-/ { +- v2m_fixed_3v3: fixed-regulator-0 { +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- v2m_clk24mhz: clk24mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "v2m:clk24mhz"; +- }; +- +- v2m_refclk1mhz: refclk1mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <1000000>; +- clock-output-names = "v2m:refclk1mhz"; +- }; +- +- v2m_refclk32khz: refclk32khz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "v2m:refclk32khz"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-1 { +- label = "v2m:green:user1"; +- gpios = <&v2m_led_gpios 0 0>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-2 { +- label = "v2m:green:user2"; +- gpios = <&v2m_led_gpios 1 0>; +- linux,default-trigger = "disk-activity"; +- }; +- +- led-3 { +- label = "v2m:green:user3"; +- gpios = <&v2m_led_gpios 2 0>; +- linux,default-trigger = "cpu0"; +- }; +- +- led-4 { +- label = "v2m:green:user4"; +- gpios = <&v2m_led_gpios 3 0>; +- linux,default-trigger = "cpu1"; +- }; +- +- led-5 { +- label = "v2m:green:user5"; +- gpios = <&v2m_led_gpios 4 0>; +- linux,default-trigger = "cpu2"; +- }; +- +- led-6 { +- label = "v2m:green:user6"; +- gpios = <&v2m_led_gpios 5 0>; +- linux,default-trigger = "cpu3"; +- }; +- +- led-7 { +- label = "v2m:green:user7"; +- gpios = <&v2m_led_gpios 6 0>; +- linux,default-trigger = "cpu4"; +- }; +- +- led-8 { +- label = "v2m:green:user8"; +- gpios = <&v2m_led_gpios 7 0>; +- linux,default-trigger = "cpu5"; +- }; +- }; +- +- bus@8000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 63>; +- interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, +- <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, +- <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, +- <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, +- <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, +- <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, +- <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, +- <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, +- <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, +- <0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, +- <0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, +- <0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, +- <0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, +- <0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, +- <0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, +- <0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, +- <0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, +- <0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, +- <0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, +- <0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, +- <0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, +- <0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, +- <0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, +- <0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, +- <0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, +- <0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, +- <0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, +- <0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, +- <0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, +- <0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, +- <0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, +- <0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, +- <0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, +- <0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, +- <0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, +- <0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, +- <0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, +- <0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, +- <0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, +- <0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, +- <0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, +- <0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, +- <0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; +- +- motherboard-bus@8000000 { +- arm,hbi = <0x190>; +- arm,vexpress,site = <0>; +- compatible = "arm,vexpress,v2m-p1", "simple-bus"; +- #address-cells = <2>; /* SMB chipselect number and offset */ +- #size-cells = <1>; +- ranges = <0 0 0x08000000 0x04000000>, +- <1 0 0x14000000 0x04000000>, +- <2 0 0x18000000 0x04000000>, +- <3 0 0x1c000000 0x04000000>, +- <4 0 0x0c000000 0x04000000>, +- <5 0 0x10000000 0x04000000>; +- +- nor_flash: flash@0 { +- compatible = "arm,vexpress-flash", "cfi-flash"; +- reg = <0 0x00000000 0x04000000>, +- <4 0x00000000 0x04000000>; +- bank-width = <4>; +- partitions { +- compatible = "arm,arm-firmware-suite"; +- }; +- }; +- +- psram@100000000 { +- compatible = "arm,vexpress-psram", "mtd-ram"; +- reg = <1 0x00000000 0x02000000>; +- bank-width = <4>; +- }; +- +- ethernet@202000000 { +- compatible = "smsc,lan9118", "smsc,lan9115"; +- reg = <2 0x02000000 0x10000>; +- interrupts = <15>; +- phy-mode = "mii"; +- reg-io-width = <4>; +- smsc,irq-active-high; +- smsc,irq-push-pull; +- vdd33a-supply = <&v2m_fixed_3v3>; +- vddvario-supply = <&v2m_fixed_3v3>; +- }; +- +- usb@203000000 { +- compatible = "nxp,usb-isp1761"; +- reg = <2 0x03000000 0x20000>; +- interrupts = <16>; +- dr_mode = "peripheral"; +- }; +- +- iofpga-bus@300000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 3 0 0x200000>; +- +- v2m_sysreg: sysreg@10000 { +- compatible = "arm,vexpress-sysreg"; +- reg = <0x010000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x10000 0x1000>; +- +- v2m_led_gpios: gpio@8 { +- compatible = "arm,vexpress-sysreg,sys_led"; +- reg = <0x008 4>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- v2m_mmc_gpios: gpio@48 { +- compatible = "arm,vexpress-sysreg,sys_mci"; +- reg = <0x048 4>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- v2m_flash_gpios: gpio@4c { +- compatible = "arm,vexpress-sysreg,sys_flash"; +- reg = <0x04c 4>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +- +- v2m_sysctl: sysctl@20000 { +- compatible = "arm,sp810", "arm,primecell"; +- reg = <0x020000 0x1000>; +- clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; +- clock-names = "refclk", "timclk", "apb_pclk"; +- #clock-cells = <1>; +- clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; +- assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; +- assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; +- }; +- +- /* PCI-E I2C bus */ +- v2m_i2c_pcie: i2c@30000 { +- compatible = "arm,versatile-i2c"; +- reg = <0x030000 0x1000>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- pcie-switch@60 { +- compatible = "idt,89hpes32h8"; +- reg = <0x60>; +- }; +- }; +- +- aaci@40000 { +- compatible = "arm,pl041", "arm,primecell"; +- reg = <0x040000 0x1000>; +- interrupts = <11>; +- clocks = <&smbclk>; +- clock-names = "apb_pclk"; +- }; +- +- mmc@50000 { +- compatible = "arm,pl180", "arm,primecell"; +- reg = <0x050000 0x1000>; +- interrupts = <9>, <10>; +- cd-gpios = <&v2m_mmc_gpios 0 0>; +- wp-gpios = <&v2m_mmc_gpios 1 0>; +- max-frequency = <12000000>; +- vmmc-supply = <&v2m_fixed_3v3>; +- clocks = <&v2m_clk24mhz>, <&smbclk>; +- clock-names = "mclk", "apb_pclk"; +- }; +- +- kmi@60000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x060000 0x1000>; +- interrupts = <12>; +- clocks = <&v2m_clk24mhz>, <&smbclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- kmi@70000 { +- compatible = "arm,pl050", "arm,primecell"; +- reg = <0x070000 0x1000>; +- interrupts = <13>; +- clocks = <&v2m_clk24mhz>, <&smbclk>; +- clock-names = "KMIREFCLK", "apb_pclk"; +- }; +- +- v2m_serial0: serial@90000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x090000 0x1000>; +- interrupts = <5>; +- clocks = <&v2m_oscclk2>, <&smbclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- v2m_serial1: serial@a0000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0a0000 0x1000>; +- interrupts = <6>; +- clocks = <&v2m_oscclk2>, <&smbclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- v2m_serial2: serial@b0000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0b0000 0x1000>; +- interrupts = <7>; +- clocks = <&v2m_oscclk2>, <&smbclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- v2m_serial3: serial@c0000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0c0000 0x1000>; +- interrupts = <8>; +- clocks = <&v2m_oscclk2>, <&smbclk>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- watchdog@f0000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0f0000 0x1000>; +- interrupts = <0>; +- clocks = <&v2m_refclk32khz>, <&smbclk>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- v2m_timer01: timer@110000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x110000 0x1000>; +- interrupts = <2>; +- clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; +- clock-names = "timclken1", "timclken2", "apb_pclk"; +- }; +- +- v2m_timer23: timer@120000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x120000 0x1000>; +- interrupts = <3>; +- clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; +- clock-names = "timclken1", "timclken2", "apb_pclk"; +- }; +- +- /* DVI I2C bus */ +- v2m_i2c_dvi: i2c@160000 { +- compatible = "arm,versatile-i2c"; +- reg = <0x160000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- dvi-transmitter@39 { +- compatible = "sil,sii9022-tpi", "sil,sii9022"; +- reg = <0x39>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dvi_bridge_in: endpoint { +- remote-endpoint = <&clcd_pads>; +- }; +- }; +- }; +- }; +- +- dvi-transmitter@60 { +- compatible = "sil,sii9022-cpi", "sil,sii9022"; +- reg = <0x60>; +- }; +- }; +- +- rtc@170000 { +- compatible = "arm,pl031", "arm,primecell"; +- reg = <0x170000 0x1000>; +- interrupts = <4>; +- clocks = <&smbclk>; +- clock-names = "apb_pclk"; +- }; +- +- compact-flash@1a0000 { +- compatible = "arm,vexpress-cf", "ata-generic"; +- reg = <0x1a0000 0x100 +- 0x1a0100 0xf00>; +- reg-shift = <2>; +- }; +- +- clcd@1f0000 { +- compatible = "arm,pl111", "arm,primecell"; +- reg = <0x1f0000 0x1000>; +- interrupt-names = "combined"; +- interrupts = <14>; +- clocks = <&v2m_oscclk1>, <&smbclk>; +- clock-names = "clcdclk", "apb_pclk"; +- /* 800x600 16bpp @36MHz works fine */ +- max-memory-bandwidth = <54000000>; +- memory-region = <&vram>; +- +- port { +- clcd_pads: endpoint { +- remote-endpoint = <&dvi_bridge_in>; +- arm,pl11x,tft-r0g0b0-pads = <0 8 16>; +- }; +- }; +- }; +- +- mcc { +- compatible = "arm,vexpress,config-bus"; +- arm,vexpress,config-bridge = <&v2m_sysreg>; +- +- oscclk0 { +- /* MCC static memory clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 0>; +- freq-range = <25000000 60000000>; +- #clock-cells = <0>; +- clock-output-names = "v2m:oscclk0"; +- }; +- +- v2m_oscclk1: oscclk1 { +- /* CLCD clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 1>; +- freq-range = <23750000 65000000>; +- #clock-cells = <0>; +- clock-output-names = "v2m:oscclk1"; +- }; +- +- v2m_oscclk2: oscclk2 { +- /* IO FPGA peripheral clock */ +- compatible = "arm,vexpress-osc"; +- arm,vexpress-sysreg,func = <1 2>; +- freq-range = <24000000 24000000>; +- #clock-cells = <0>; +- clock-output-names = "v2m:oscclk2"; +- }; +- +- volt-vio { +- /* Logic level voltage */ +- compatible = "arm,vexpress-volt"; +- arm,vexpress-sysreg,func = <2 0>; +- regulator-name = "VIO"; +- regulator-always-on; +- label = "VIO"; +- }; +- +- temp-mcc { +- /* MCC internal operating temperature */ +- compatible = "arm,vexpress-temp"; +- arm,vexpress-sysreg,func = <4 0>; +- label = "MCC"; +- }; +- +- reset { +- compatible = "arm,vexpress-reset"; +- arm,vexpress-sysreg,func = <5 0>; +- }; +- +- muxfpga { +- compatible = "arm,vexpress-muxfpga"; +- arm,vexpress-sysreg,func = <7 0>; +- }; +- +- shutdown { +- compatible = "arm,vexpress-shutdown"; +- arm,vexpress-sysreg,func = <8 0>; +- }; +- +- reboot { +- compatible = "arm,vexpress-reboot"; +- arm,vexpress-sysreg,func = <9 0>; +- }; +- +- dvimode { +- compatible = "arm,vexpress-dvimode"; +- arm,vexpress-sysreg,func = <11 0>; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/bitmain/Makefile b/scripts/dtc/include-prefixes/arm64/bitmain/Makefile +deleted file mode 100644 +index be90a6071be0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/bitmain/Makefile ++++ /dev/null +@@ -1,3 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0+ +- +-dtb-$(CONFIG_ARCH_BITMAIN) += bm1880-sophon-edge.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/bitmain/bm1880-sophon-edge.dts b/scripts/dtc/include-prefixes/arm64/bitmain/bm1880-sophon-edge.dts +deleted file mode 100644 +index 7a2c7f9c2660..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/bitmain/bm1880-sophon-edge.dts ++++ /dev/null +@@ -1,184 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Linaro Ltd. +- * Author: Manivannan Sadhasivam +- */ +- +-/dts-v1/; +- +-#include "bm1880.dtsi" +- +-/* +- * GPIO name legend: proper name = the GPIO line is used as GPIO +- * NC = not connected (pin out but not routed from the chip to +- * anything the board) +- * "[PER]" = pin is muxed for [peripheral] (not GPIO) +- * LSEC = Low Speed External Connector +- * HSEC = High Speed External Connector +- * +- * Line names are taken from the schematic "sophon-edge-schematics" +- * version, 1.0210. +- * +- * For the lines routed to the external connectors the +- * lines are named after the 96Boards CE Specification 1.0, +- * Appendix "Expansion Connector Signal Description". +- * +- * When the 96Board naming of a line and the schematic name of +- * the same line are in conflict, the 96Board specification +- * takes precedence. This is only for the informational +- * lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L" +- * are the only ones actually used for GPIO. +- */ +- +-/ { +- compatible = "bitmain,sophon-edge", "bitmain,bm1880"; +- model = "Sophon Edge"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart2; +- serial2 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB +- }; +- +- soc { +- gpio0: gpio@50027000 { +- porta: gpio-controller@0 { +- gpio-line-names = +- "GPIO-A", /* GPIO0, LSEC pin 23 */ +- "GPIO-C", /* GPIO1, LSEC pin 25 */ +- "[GPIO2_PHY0_RST]", /* GPIO2 */ +- "GPIO-E", /* GPIO3, LSEC pin 27 */ +- "[USB_DET]", /* GPIO4 */ +- "[EN_P5V]", /* GPIO5 */ +- "[VDDIO_MS1_SEL]", /* GPIO6 */ +- "GPIO-G", /* GPIO7, LSEC pin 29 */ +- "[BM_TUSB_RST_L]", /* GPIO8 */ +- "[EN_P5V_USBHUB]", /* GPIO9 */ +- "NC", +- "LED_WIFI", /* GPIO11 */ +- "LED_BT", /* GPIO12 */ +- "[BM_BLM8221_EN_L]", /* GPIO13 */ +- "NC", /* GPIO14 */ +- "NC", /* GPIO15 */ +- "NC", /* GPIO16 */ +- "NC", /* GPIO17 */ +- "NC", /* GPIO18 */ +- "NC", /* GPIO19 */ +- "NC", /* GPIO20 */ +- "NC", /* GPIO21 */ +- "NC", /* GPIO22 */ +- "NC", /* GPIO23 */ +- "NC", /* GPIO24 */ +- "NC", /* GPIO25 */ +- "NC", /* GPIO26 */ +- "NC", /* GPIO27 */ +- "NC", /* GPIO28 */ +- "NC", /* GPIO29 */ +- "NC", /* GPIO30 */ +- "NC"; /* GPIO31 */ +- }; +- }; +- +- gpio1: gpio@50027400 { +- portb: gpio-controller@0 { +- gpio-line-names = +- "NC", /* GPIO32 */ +- "NC", /* GPIO33 */ +- "[I2C0_SDA]", /* GPIO34, LSEC pin 17 */ +- "[I2C0_SCL]", /* GPIO35, LSEC pin 15 */ +- "[JTAG0_TDO]", /* GPIO36 */ +- "[JTAG0_TCK]", /* GPIO37 */ +- "[JTAG0_TDI]", /* GPIO38 */ +- "[JTAG0_TMS]", /* GPIO39 */ +- "[JTAG0_TRST_X]", /* GPIO40 */ +- "[JTAG1_TDO]", /* GPIO41 */ +- "[JTAG1_TCK]", /* GPIO42 */ +- "[JTAG1_TDI]", /* GPIO43 */ +- "[CPU_TX]", /* GPIO44 */ +- "[CPU_RX]", /* GPIO45 */ +- "[UART1_TXD]", /* GPIO46 */ +- "[UART1_RXD]", /* GPIO47 */ +- "[UART0_TXD]", /* GPIO48 */ +- "[UART0_RXD]", /* GPIO49 */ +- "GPIO-I", /* GPIO50, LSEC pin 31 */ +- "GPIO-K", /* GPIO51, LSEC pin 33 */ +- "USER_LED2", /* GPIO52 */ +- "USER_LED1", /* GPIO53 */ +- "[UART0_RTS]", /* GPIO54 */ +- "[UART0_CTS]", /* GPIO55 */ +- "USER_LED4", /* GPIO56, JTAG1_TRST_X */ +- "USER_LED3", /* GPIO57, JTAG1_TMS */ +- "[I2S0_SCLK]", /* GPIO58 */ +- "[I2S0_FS]", /* GPIO59 */ +- "[I2S0_SDI]", /* GPIO60 */ +- "[I2S0_SDO]", /* GPIO61 */ +- "GPIO-B", /* GPIO62, LSEC pin 24 */ +- "GPIO-F"; /* GPIO63, I2S1_SCLK, LSEC pin 28 */ +- }; +- }; +- +- gpio2: gpio@50027800 { +- portc: gpio-controller@0 { +- gpio-line-names = +- "GPIO-D", /* GPIO64, I2S1_FS, LSEC pin 26 */ +- "GPIO-J", /* GPIO65, I2S1_SDI, LSEC pin 32 */ +- "GPIO-H", /* GPIO66, I2S1_SDO, LSEC pin 30 */ +- "GPIO-L", /* GPIO67, LSEC pin 34 */ +- "[SPI0_CS]", /* GPIO68, SPI1_CS, LSEC pin 12 */ +- "[SPI0_DIN]", /* GPIO69, SPI1_SDI, LSEC pin 10 */ +- "[SPI0_DOUT]", /* GPIO70, SPI1_SDO, LSEC pin 14 */ +- "[SPI0_SCLK]"; /* GPIO71, SPI1_SCK, LSEC pin 8 */ +- }; +- }; +- }; +-}; +- +-&pinctrl { +- pinctrl_uart0_default: pinctrl-uart0-default { +- pinmux { +- groups = "uart0_grp"; +- function = "uart0"; +- }; +- }; +- +- pinctrl_uart1_default: pinctrl-uart1-default { +- pinmux { +- groups = "uart1_grp"; +- function = "uart1"; +- }; +- }; +- +- pinctrl_uart2_default: pinctrl-uart2-default { +- pinmux { +- groups = "uart2_grp"; +- function = "uart2"; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0_default>; +-}; +- +-&uart1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1_default>; +-}; +- +-&uart2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2_default>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/bitmain/bm1880.dtsi b/scripts/dtc/include-prefixes/arm64/bitmain/bm1880.dtsi +deleted file mode 100644 +index 53a9b76057aa..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/bitmain/bm1880.dtsi ++++ /dev/null +@@ -1,226 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Linaro Ltd. +- * Author: Manivannan Sadhasivam +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "bitmain,bm1880"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0>; +- enable-method = "psci"; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x1>; +- enable-method = "psci"; +- }; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- secmon@100000000 { +- reg = <0x1 0x00000000 0x0 0x20000>; +- no-map; +- }; +- +- jpu@130000000 { +- reg = <0x1 0x30000000 0x0 0x08000000>; // 128M +- no-map; +- }; +- +- vpu@138000000 { +- reg = <0x1 0x38000000 0x0 0x08000000>; // 128M +- no-map; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- osc: osc { +- compatible = "fixed-clock"; +- clock-frequency = <25000000>; +- #clock-cells = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gic: interrupt-controller@50001000 { +- compatible = "arm,gic-400"; +- reg = <0x0 0x50001000 0x0 0x1000>, +- <0x0 0x50002000 0x0 0x2000>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- +- sctrl: system-controller@50010000 { +- compatible = "bitmain,bm1880-sctrl", "syscon", +- "simple-mfd"; +- reg = <0x0 0x50010000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x50010000 0x1000>; +- +- pinctrl: pinctrl@400 { +- compatible = "bitmain,bm1880-pinctrl"; +- reg = <0x400 0x120>; +- }; +- +- clk: clock-controller@e8 { +- compatible = "bitmain,bm1880-clk"; +- reg = <0xe8 0x0c>, <0x800 0xb0>; +- reg-names = "pll", "sys"; +- clocks = <&osc>; +- clock-names = "osc"; +- #clock-cells = <1>; +- }; +- +- rst: reset-controller@c00 { +- compatible = "bitmain,bm1880-reset"; +- reg = <0xc00 0x8>; +- #reset-cells = <1>; +- }; +- }; +- +- gpio0: gpio@50027000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dw-apb-gpio"; +- reg = <0x0 0x50027000 0x0 0x400>; +- +- porta: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- }; +- +- gpio1: gpio@50027400 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dw-apb-gpio"; +- reg = <0x0 0x50027400 0x0 0x400>; +- +- portb: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- }; +- +- gpio2: gpio@50027800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dw-apb-gpio"; +- reg = <0x0 0x50027800 0x0 0x400>; +- +- portc: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <8>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- }; +- +- uart0: serial@58018000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x0 0x58018000 0x0 0x2000>; +- clocks = <&clk BM1880_CLK_UART_500M>, +- <&clk BM1880_CLK_APB_UART>; +- clock-names = "baudclk", "apb_pclk"; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- resets = <&rst BM1880_RST_UART0_1_CLK>; +- status = "disabled"; +- }; +- +- uart1: serial@5801A000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x0 0x5801a000 0x0 0x2000>; +- clocks = <&clk BM1880_CLK_UART_500M>, +- <&clk BM1880_CLK_APB_UART>; +- clock-names = "baudclk", "apb_pclk"; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- resets = <&rst BM1880_RST_UART0_1_ACLK>; +- status = "disabled"; +- }; +- +- uart2: serial@5801C000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x0 0x5801c000 0x0 0x2000>; +- clocks = <&clk BM1880_CLK_UART_500M>, +- <&clk BM1880_CLK_APB_UART>; +- clock-names = "baudclk", "apb_pclk"; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- resets = <&rst BM1880_RST_UART2_3_CLK>; +- status = "disabled"; +- }; +- +- uart3: serial@5801E000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x0 0x5801e000 0x0 0x2000>; +- clocks = <&clk BM1880_CLK_UART_500M>, +- <&clk BM1880_CLK_APB_UART>; +- clock-names = "baudclk", "apb_pclk"; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- resets = <&rst BM1880_RST_UART2_3_ACLK>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/Makefile b/scripts/dtc/include-prefixes/arm64/broadcom/Makefile +deleted file mode 100644 +index 11eae3e3a944..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/Makefile ++++ /dev/null +@@ -1,11 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \ +- bcm2711-rpi-4-b.dtb \ +- bcm2837-rpi-3-a-plus.dtb \ +- bcm2837-rpi-3-b.dtb \ +- bcm2837-rpi-3-b-plus.dtb \ +- bcm2837-rpi-cm3-io3.dtb +- +-subdir-y += bcm4908 +-subdir-y += northstar2 +-subdir-y += stingray +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/bcm2711-rpi-4-b.dts b/scripts/dtc/include-prefixes/arm64/broadcom/bcm2711-rpi-4-b.dts +deleted file mode 100644 +index d24c53682e44..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/bcm2711-rpi-4-b.dts ++++ /dev/null +@@ -1,2 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "arm/bcm2711-rpi-4-b.dts" +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/bcm2711-rpi-400.dts b/scripts/dtc/include-prefixes/arm64/broadcom/bcm2711-rpi-400.dts +deleted file mode 100644 +index b9000f58beb5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/bcm2711-rpi-400.dts ++++ /dev/null +@@ -1,2 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "arm/bcm2711-rpi-400.dts" +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/bcm2837-rpi-3-a-plus.dts b/scripts/dtc/include-prefixes/arm64/broadcom/bcm2837-rpi-3-a-plus.dts +deleted file mode 100644 +index f0ec56a1c4d7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/bcm2837-rpi-3-a-plus.dts ++++ /dev/null +@@ -1,2 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "arm/bcm2837-rpi-3-a-plus.dts" +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/bcm2837-rpi-3-b-plus.dts b/scripts/dtc/include-prefixes/arm64/broadcom/bcm2837-rpi-3-b-plus.dts +deleted file mode 100644 +index 46ad2023cccf..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/bcm2837-rpi-3-b-plus.dts ++++ /dev/null +@@ -1,2 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "arm/bcm2837-rpi-3-b-plus.dts" +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/bcm2837-rpi-3-b.dts b/scripts/dtc/include-prefixes/arm64/broadcom/bcm2837-rpi-3-b.dts +deleted file mode 100644 +index 89b78d6c19bf..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/bcm2837-rpi-3-b.dts ++++ /dev/null +@@ -1,2 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "arm/bcm2837-rpi-3-b.dts" +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/bcm2837-rpi-cm3-io3.dts b/scripts/dtc/include-prefixes/arm64/broadcom/bcm2837-rpi-cm3-io3.dts +deleted file mode 100644 +index b1c4ab212c64..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/bcm2837-rpi-cm3-io3.dts ++++ /dev/null +@@ -1,2 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "arm/bcm2837-rpi-cm3-io3.dts" +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/bcm4908/Makefile b/scripts/dtc/include-prefixes/arm64/broadcom/bcm4908/Makefile +deleted file mode 100644 +index cc75854519ac..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/bcm4908/Makefile ++++ /dev/null +@@ -1,4 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-netgear-r8000p.dtb +-dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-tplink-archer-c2300-v1.dtb +-dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/bcm4908/bcm4906-netgear-r8000p.dts b/scripts/dtc/include-prefixes/arm64/broadcom/bcm4908/bcm4906-netgear-r8000p.dts +deleted file mode 100644 +index 2dd028438c22..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/bcm4908/bcm4906-netgear-r8000p.dts ++++ /dev/null +@@ -1,157 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +- +-#include +-#include +-#include +- +-#include "bcm4906.dtsi" +- +-/ { +- compatible = "netgear,r8000p", "brcm,bcm4906", "brcm,bcm4908"; +- model = "Netgear R8000P"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00 0x00 0x00 0x20000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-power-white { +- function = LED_FUNCTION_POWER; +- color = ; +- gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; +- }; +- +- led-power-amber { +- function = LED_FUNCTION_POWER; +- color = ; +- gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; +- }; +- +- led-wps { +- function = LED_FUNCTION_WPS; +- color = ; +- gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; +- }; +- +- led-2ghz { +- function = "2ghz"; +- color = ; +- gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; +- }; +- +- led-5ghz-1 { +- function = "5ghz-1"; +- color = ; +- gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; +- }; +- +- led-5ghz-2 { +- function = "5ghz-2"; +- color = ; +- gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; +- }; +- +- led-usb2 { +- function = "usb2"; +- color = ; +- gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; +- }; +- +- led-usb3 { +- function = "usb3"; +- color = ; +- gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; +- }; +- +- led-wifi { +- function = "wifi"; +- color = ; +- gpios = <&gpio0 56 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&enet { +- nvmem-cells = <&base_mac_addr>; +- nvmem-cell-names = "mac-address"; +-}; +- +-&usb_phy { +- brcm,ioc = <1>; +- status = "okay"; +-}; +- +-&ehci { +- status = "okay"; +-}; +- +-&ohci { +- status = "okay"; +-}; +- +-&xhci { +- status = "okay"; +-}; +- +-&ports { +- port@0 { +- label = "lan4"; +- }; +- +- port@1 { +- label = "lan3"; +- }; +- +- port@2 { +- label = "lan2"; +- }; +- +- port@3 { +- label = "lan1"; +- }; +- +- port@7 { +- reg = <7>; +- phy-mode = "internal"; +- phy-handle = <&phy12>; +- label = "wan"; +- }; +-}; +- +-&nandcs { +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- nand-on-flash-bbt; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- compatible = "nvmem-cells"; +- label = "cferom"; +- reg = <0x0 0x100000>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x0 0x100000>; +- +- base_mac_addr: mac@106a0 { +- reg = <0x106a0 0x6>; +- }; +- }; +- +- partition@100000 { +- compatible = "brcm,bcm4908-firmware"; +- label = "firmware"; +- reg = <0x100000 0x4400000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts b/scripts/dtc/include-prefixes/arm64/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts +deleted file mode 100644 +index b63eefab48bd..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts ++++ /dev/null +@@ -1,182 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +- +-#include +-#include +-#include +- +-#include "bcm4906.dtsi" +- +-/ { +- compatible = "tplink,archer-c2300-v1", "brcm,bcm4906", "brcm,bcm4908"; +- model = "TP-Link Archer C2300 V1"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00 0x00 0x00 0x20000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-power { +- function = LED_FUNCTION_POWER; +- color = ; +- gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; +- }; +- +- led-2ghz { +- function = "2ghz"; +- color = ; +- gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; +- }; +- +- led-5ghz { +- function = "5ghz"; +- color = ; +- gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; +- }; +- +- led-wan-amber { +- function = LED_FUNCTION_WAN; +- color = ; +- gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; +- }; +- +- led-wan-blue { +- function = LED_FUNCTION_WAN; +- color = ; +- gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; +- }; +- +- led-lan { +- function = LED_FUNCTION_LAN; +- color = ; +- gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; +- }; +- +- led-wps { +- function = LED_FUNCTION_WPS; +- color = ; +- gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; +- }; +- +- led-usb2 { +- function = "usb2"; +- color = ; +- gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; +- }; +- +- led-usb3 { +- function = "usbd3"; +- color = ; +- gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; +- }; +- +- led-brightness { +- function = LED_FUNCTION_BACKLIGHT; +- color = ; +- gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- poll-interval = <100>; +- +- brightness { +- label = "LEDs"; +- linux,code = ; +- gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; +- }; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; +- }; +- +- wifi { +- label = "WiFi"; +- linux,code = ; +- gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&usb_phy { +- brcm,ioc = <1>; +- status = "okay"; +-}; +- +-&ehci { +- status = "okay"; +-}; +- +-&ohci { +- status = "okay"; +-}; +- +-&xhci { +- status = "okay"; +-}; +- +-&ports { +- port@0 { +- label = "lan4"; +- }; +- +- port@1 { +- label = "lan3"; +- }; +- +- port@2 { +- label = "lan2"; +- }; +- +- port@3 { +- label = "lan1"; +- }; +- +- port@7 { +- reg = <7>; +- phy-mode = "internal"; +- phy-handle = <&phy12>; +- label = "wan"; +- }; +-}; +- +-&nandcs { +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- nand-on-flash-bbt; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- partitions { +- compatible = "brcm,bcm4908-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "cferom"; +- reg = <0x0 0x100000>; +- }; +- +- partition@100000 { +- compatible = "brcm,bcm4908-firmware"; +- reg = <0x100000 0x3900000>; +- }; +- +- partition@5800000 { +- compatible = "brcm,bcm4908-firmware"; +- reg = <0x3a00000 0x3900000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/bcm4908/bcm4906.dtsi b/scripts/dtc/include-prefixes/arm64/broadcom/bcm4908/bcm4906.dtsi +deleted file mode 100644 +index 66023d553524..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/bcm4908/bcm4906.dtsi ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +- +-#include "bcm4908.dtsi" +- +-/ { +- cpus { +- /delete-node/ cpu@2; +- +- /delete-node/ cpu@3; +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts b/scripts/dtc/include-prefixes/arm64/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts +deleted file mode 100644 +index 169fbb7cfd34..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts ++++ /dev/null +@@ -1,159 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +- +-#include +-#include +- +-#include "bcm4908.dtsi" +- +-/ { +- compatible = "asus,gt-ac5300", "brcm,bcm4908"; +- model = "Asus GT-AC5300"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00 0x00 0x00 0x40000000>; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- poll-interval = <100>; +- +- wifi { +- label = "WiFi"; +- linux,code = ; +- gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; +- }; +- +- wps { +- label = "WPS"; +- linux,code = ; +- gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; +- }; +- +- restart { +- label = "Reset"; +- linux,code = ; +- gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; +- }; +- +- brightness { +- label = "LEDs"; +- linux,code = ; +- gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&enet { +- nvmem-cells = <&base_mac_addr>; +- nvmem-cell-names = "mac-address"; +-}; +- +-&usb_phy { +- brcm,ioc = <1>; +- status = "okay"; +-}; +- +-&ehci { +- status = "okay"; +-}; +- +-&ohci { +- status = "okay"; +-}; +- +-&xhci { +- status = "okay"; +-}; +- +-&ports { +- port@0 { +- label = "lan2"; +- }; +- +- port@1 { +- label = "lan1"; +- }; +- +- port@2 { +- label = "lan6"; +- }; +- +- port@3 { +- label = "lan5"; +- }; +- +- /* External BCM53134S switch */ +- port@7 { +- label = "sw"; +- reg = <7>; +- phy-mode = "rgmii"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +-}; +- +-&mdio { +- /* lan8 */ +- ethernet-phy@0 { +- reg = <0>; +- }; +- +- /* lan7 */ +- ethernet-phy@1 { +- reg = <1>; +- }; +- +- /* lan4 */ +- ethernet-phy@2 { +- reg = <2>; +- }; +- +- /* lan3 */ +- ethernet-phy@3 { +- reg = <3>; +- }; +-}; +- +-&nandcs { +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- nand-on-flash-bbt; +- brcm,nand-has-wp; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- partitions { +- compatible = "brcm,bcm4908-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- compatible = "nvmem-cells"; +- label = "cferom"; +- reg = <0x0 0x100000>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x0 0x100000>; +- +- base_mac_addr: mac@106a0 { +- reg = <0x106a0 0x6>; +- }; +- }; +- +- partition@100000 { +- compatible = "brcm,bcm4908-firmware"; +- reg = <0x100000 0x5700000>; +- }; +- +- partition@5800000 { +- compatible = "brcm,bcm4908-firmware"; +- reg = <0x5800000 0x5700000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/bcm4908/bcm4908.dtsi b/scripts/dtc/include-prefixes/arm64/broadcom/bcm4908/bcm4908.dtsi +deleted file mode 100644 +index 5118816b1ed7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/bcm4908/bcm4908.dtsi ++++ /dev/null +@@ -1,337 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +- +-#include +-#include +-#include +-#include +- +-/dts-v1/; +- +-/ { +- interrupt-parent = <&gic>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "brcm,brahma-b53"; +- reg = <0x0>; +- next-level-cache = <&l2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "brcm,brahma-b53"; +- reg = <0x1>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0xfff8>; +- next-level-cache = <&l2>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "brcm,brahma-b53"; +- reg = <0x2>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0xfff8>; +- next-level-cache = <&l2>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "brcm,brahma-b53"; +- reg = <0x3>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0xfff8>; +- next-level-cache = <&l2>; +- }; +- +- l2: l2-cache0 { +- compatible = "cache"; +- }; +- }; +- +- axi@81000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00 0x00 0x81000000 0x4000>; +- +- gic: interrupt-controller@1000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x1000 0x1000>, +- <0x2000 0x2000>; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- clocks { +- periph_clk: periph_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- clock-output-names = "periph"; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00 0x00 0x80000000 0x281000>; +- +- enet: ethernet@2000 { +- compatible = "brcm,bcm4908-enet"; +- reg = <0x2000 0x1000>; +- +- interrupts = , +- ; +- interrupt-names = "rx", "tx"; +- }; +- +- usb_phy: usb-phy@c200 { +- compatible = "brcm,bcm4908-usb-phy"; +- reg = <0xc200 0x100>; +- reg-names = "ctrl"; +- power-domains = <&pmb BCM_PMB_HOST_USB>; +- dr_mode = "host"; +- brcm,has-xhci; +- brcm,has-eohci; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- ehci: usb@c300 { +- compatible = "generic-ehci"; +- reg = <0xc300 0x100>; +- interrupts = ; +- phys = <&usb_phy PHY_TYPE_USB2>; +- status = "disabled"; +- }; +- +- ohci: usb@c400 { +- compatible = "generic-ohci"; +- reg = <0xc400 0x100>; +- interrupts = ; +- phys = <&usb_phy PHY_TYPE_USB2>; +- status = "disabled"; +- }; +- +- xhci: usb@d000 { +- compatible = "generic-xhci"; +- reg = <0xd000 0x8c8>; +- interrupts = ; +- phys = <&usb_phy PHY_TYPE_USB3>; +- status = "disabled"; +- }; +- +- bus@80000 { +- compatible = "simple-bus"; +- #size-cells = <1>; +- #address-cells = <1>; +- ranges = <0 0x80000 0x50000>; +- +- ethernet-switch@0 { +- compatible = "brcm,bcm4908-switch"; +- reg = <0x0 0x40000>, +- <0x40000 0x110>, +- <0x40340 0x30>, +- <0x40380 0x30>, +- <0x40600 0x34>, +- <0x40800 0x208>; +- reg-names = "core", "reg", "intrl2_0", +- "intrl2_1", "fcb", "acb"; +- interrupts = , +- ; +- brcm,num-gphy = <5>; +- brcm,num-rgmii-ports = <2>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports: ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- phy-mode = "internal"; +- phy-handle = <&phy8>; +- }; +- +- port@1 { +- reg = <1>; +- phy-mode = "internal"; +- phy-handle = <&phy9>; +- }; +- +- port@2 { +- reg = <2>; +- phy-mode = "internal"; +- phy-handle = <&phy10>; +- }; +- +- port@3 { +- reg = <3>; +- phy-mode = "internal"; +- phy-handle = <&phy11>; +- }; +- +- port@8 { +- reg = <8>; +- phy-mode = "internal"; +- ethernet = <&enet>; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; +- +- mdio: mdio@405c0 { +- compatible = "brcm,unimac-mdio"; +- reg = <0x405c0 0x8>; +- reg-names = "mdio"; +- #size-cells = <0>; +- #address-cells = <1>; +- +- phy8: ethernet-phy@8 { +- reg = <8>; +- }; +- +- phy9: ethernet-phy@9 { +- reg = <9>; +- }; +- +- phy10: ethernet-phy@a { +- reg = <10>; +- }; +- +- phy11: ethernet-phy@b { +- reg = <11>; +- }; +- +- phy12: ethernet-phy@c { +- reg = <12>; +- }; +- }; +- }; +- +- procmon: syscon@280000 { +- compatible = "simple-bus"; +- reg = <0x280000 0x1000>; +- ranges; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- pmb: power-controller@2800c0 { +- compatible = "brcm,bcm4908-pmb"; +- reg = <0x2800c0 0x40>; +- #power-domain-cells = <1>; +- }; +- }; +- }; +- +- bus@ff800000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00 0x00 0xff800000 0x3000>; +- +- timer: timer@400 { +- compatible = "brcm,bcm6328-timer", "syscon"; +- reg = <0x400 0x3c>; +- }; +- +- gpio0: gpio-controller@500 { +- compatible = "brcm,bcm6345-gpio"; +- reg-names = "dirout", "dat"; +- reg = <0x500 0x28>, <0x528 0x28>; +- +- #gpio-cells = <2>; +- gpio-controller; +- }; +- +- uart0: serial@640 { +- compatible = "brcm,bcm6345-uart"; +- reg = <0x640 0x18>; +- interrupts = ; +- clocks = <&periph_clk>; +- clock-names = "refclk"; +- status = "okay"; +- }; +- +- nand@1800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; +- reg = <0x1800 0x600>, <0x2000 0x10>; +- reg-names = "nand", "nand-int-base"; +- interrupts = ; +- interrupt-names = "nand"; +- status = "okay"; +- +- nandcs: nand@0 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- }; +- }; +- +- misc@2600 { +- compatible = "brcm,misc", "simple-mfd"; +- reg = <0x2600 0xe4>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00 0x2600 0xe4>; +- +- reset-controller@2644 { +- compatible = "brcm,bcm4908-misc-pcie-reset"; +- reg = <0x44 0x04>; +- #reset-cells = <1>; +- }; +- }; +- }; +- +- reboot { +- compatible = "syscon-reboot"; +- regmap = <&timer>; +- offset = <0x34>; +- mask = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/northstar2/Makefile b/scripts/dtc/include-prefixes/arm64/broadcom/northstar2/Makefile +deleted file mode 100644 +index 601e1e631260..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/northstar2/Makefile ++++ /dev/null +@@ -1,3 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0-only +-dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb +-dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-xmc.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/northstar2/ns2-clock.dtsi b/scripts/dtc/include-prefixes/arm64/broadcom/northstar2/ns2-clock.dtsi +deleted file mode 100644 +index 99009fdf10a4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/northstar2/ns2-clock.dtsi ++++ /dev/null +@@ -1,105 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright (c) 2016 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#include +- +- osc: oscillator { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25000000>; +- }; +- +- lcpll_ddr: lcpll_ddr@6501d058 { +- #clock-cells = <1>; +- compatible = "brcm,ns2-lcpll-ddr"; +- reg = <0x6501d058 0x20>, +- <0x6501c020 0x4>, +- <0x6501d04c 0x4>; +- clocks = <&osc>; +- clock-output-names = "lcpll_ddr", "pcie_sata_usb", +- "ddr", "ddr_ch2_unused", +- "ddr_ch3_unused", "ddr_ch4_unused", +- "ddr_ch5_unused"; +- }; +- +- lcpll_ports: lcpll_ports@6501d078 { +- #clock-cells = <1>; +- compatible = "brcm,ns2-lcpll-ports"; +- reg = <0x6501d078 0x20>, +- <0x6501c020 0x4>, +- <0x6501d054 0x4>; +- clocks = <&osc>; +- clock-output-names = "lcpll_ports", "wan", "rgmii", +- "ports_ch2_unused", +- "ports_ch3_unused", +- "ports_ch4_unused", +- "ports_ch5_unused"; +- }; +- +- genpll_scr: genpll_scr@6501d098 { +- #clock-cells = <1>; +- compatible = "brcm,ns2-genpll-scr"; +- reg = <0x6501d098 0x32>, +- <0x6501c020 0x4>, +- <0x6501d044 0x4>; +- clocks = <&osc>; +- clock-output-names = "genpll_scr", "scr", "fs", +- "audio_ref", "scr_ch3_unused", +- "scr_ch4_unused", "scr_ch5_unused"; +- }; +- +- iprocmed: iprocmed { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- iprocslow: iprocslow { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; +- clock-div = <4>; +- clock-mult = <1>; +- }; +- +- genpll_sw: genpll_sw@6501d0c4 { +- #clock-cells = <1>; +- compatible = "brcm,ns2-genpll-sw"; +- reg = <0x6501d0c4 0x32>, +- <0x6501c020 0x4>, +- <0x6501d044 0x4>; +- clocks = <&osc>; +- clock-output-names = "genpll_sw", "rpe", "250", "nic", +- "chimp", "port", "sdio"; +- }; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/northstar2/ns2-svk.dts b/scripts/dtc/include-prefixes/arm64/broadcom/northstar2/ns2-svk.dts +deleted file mode 100644 +index ec19fbf928a1..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/northstar2/ns2-svk.dts ++++ /dev/null +@@ -1,236 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2015 Broadcom Corporation. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "ns2.dtsi" +- +-/ { +- model = "Broadcom NS2 SVK"; +- compatible = "brcm,ns2-svk", "brcm,ns2"; +- +- aliases { +- serial0 = &uart3; +- serial1 = &uart0; +- serial2 = &uart1; +- serial3 = &uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- bootargs = "earlycon=uart8250,mmio32,0x66130000"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x000000000 0x80000000 0x00000000 0x40000000>; +- }; +-}; +- +-&enet { +- status = "okay"; +-}; +- +-&pci_phy0 { +- status = "okay"; +-}; +- +-&pci_phy1 { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie4 { +- status = "okay"; +-}; +- +-&pcie8 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&ssp0 { +- status = "okay"; +- +- slic@0 { +- compatible = "silabs,si3226x"; +- reg = <0>; +- spi-max-frequency = <5000000>; +- spi-cpha = <1>; +- spi-cpol = <1>; +- pl022,hierarchy = <0>; +- pl022,interface = <0>; +- pl022,slave-tx-disable = <0>; +- pl022,com-mode = <0>; +- pl022,rx-level-trig = <1>; +- pl022,tx-level-trig = <1>; +- pl022,ctrl-len = <11>; +- pl022,wait-state = <0>; +- pl022,duplex = <0>; +- }; +-}; +- +-&ssp1 { +- status = "okay"; +- +- at25@0 { +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <5000000>; +- at25,byte-len = <0x8000>; +- at25,addr-mode = <2>; +- at25,page-size = <64>; +- spi-cpha = <1>; +- spi-cpol = <1>; +- pl022,hierarchy = <0>; +- pl022,interface = <0>; +- pl022,slave-tx-disable = <0>; +- pl022,com-mode = <0>; +- pl022,rx-level-trig = <1>; +- pl022,tx-level-trig = <1>; +- pl022,ctrl-len = <11>; +- pl022,wait-state = <0>; +- pl022,duplex = <0>; +- }; +-}; +- +-&sata_phy0 { +- status = "okay"; +-}; +- +-&sata_phy1 { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&sdio0 { +- status = "okay"; +-}; +- +-&sdio1 { +- status = "okay"; +-}; +- +-&nand { +- nandcs@0 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <8>; +- nand-ecc-step-size = <512>; +- nand-bus-width = <16>; +- brcm,nand-oob-sector-size = <16>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&mdio_mux_iproc { +- mdio@10 { +- gphy0: eth-phy@10 { +- enet-phy-lane-swap; +- reg = <0x10>; +- }; +- }; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&nand_sel>; +- nand_sel: nand_sel { +- function = "nand"; +- groups = "nand_grp"; +- }; +-}; +- +-&qspi { +- bspi-sel = <0>; +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p80"; +- reg = <0x0>; +- spi-max-frequency = <12500000>; +- m25p,fast-read; +- spi-cpol; +- spi-cpha; +- +- partition@0 { +- label = "boot"; +- reg = <0x00000000 0x000a0000>; +- }; +- +- partition@a0000 { +- label = "env"; +- reg = <0x000a0000 0x00060000>; +- }; +- +- partition@100000 { +- label = "system"; +- reg = <0x00100000 0x00600000>; +- }; +- +- partition@700000 { +- label = "rootfs"; +- reg = <0x00700000 0x01900000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/northstar2/ns2-xmc.dts b/scripts/dtc/include-prefixes/arm64/broadcom/northstar2/ns2-xmc.dts +deleted file mode 100644 +index f00c21e0767e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/northstar2/ns2-xmc.dts ++++ /dev/null +@@ -1,191 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2016 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "ns2.dtsi" +- +-/ { +- model = "Broadcom NS2 XMC"; +- compatible = "brcm,ns2-xmc", "brcm,ns2"; +- +- aliases { +- serial0 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- bootargs = "earlycon=uart8250,mmio32,0x66130000"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x000000000 0x80000000 0x00000001 0x00000000>; +- }; +-}; +- +-&enet { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&mdio_mux_iproc { +- mdio@10 { +- gphy0: eth-phy@10 { +- reg = <0x10>; +- }; +- }; +-}; +- +-&nand { +- nandcs@0 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <8>; +- nand-ecc-step-size = <512>; +- nand-bus-width = <16>; +- brcm,nand-oob-sector-size = <16>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "nboot"; +- reg = <0x00000000 0x00280000>; /* 2.5MB */ +- read-only; +- }; +- +- partition@280000 { +- label = "nenv"; +- reg = <0x00280000 0x00040000>; /* 0.25MB */ +- read-only; +- }; +- +- partition@2c0000 { +- label = "ndtb"; +- reg = <0x002c0000 0x00040000>; /* 0.25MB */ +- read-only; +- }; +- +- partition@300000 { +- label = "nsystem"; +- reg = <0x00300000 0x03d00000>; /* 61MB */ +- read-only; +- }; +- +- partition@4000000 { +- label = "nrootfs"; +- reg = <0x04000000 0x06400000>; /* 100MB */ +- }; +- +- partition@a400000{ +- label = "ncustfs"; +- reg = <0x0a400000 0x35c00000>; /* 860MB */ +- }; +- }; +-}; +- +-&pci_phy0 { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie8 { +- status = "okay"; +-}; +- +-&sata_phy0 { +- status = "okay"; +-}; +- +-&sata_phy1 { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&qspi { +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p80"; +- spi-max-frequency = <62500000>; +- m25p,default-addr-width = <3>; +- reg = <0x0 0x0>; +- +- partition@0 { +- label = "bl0"; +- reg = <0x00000000 0x00080000>; /* 512KB */ +- }; +- +- partition@80000 { +- label = "fip"; +- reg = <0x00080000 0x00150000>; /* 1344KB */ +- }; +- +- partition@1e0000 { +- label = "env"; +- reg = <0x001e0000 0x00010000>;/* 64KB */ +- }; +- +- partition@1f0000 { +- label = "dtb"; +- reg = <0x001f0000 0x00010000>; /* 64KB */ +- }; +- +- partition@200000 { +- label = "kernel"; +- reg = <0x00200000 0x00e00000>; /* 14MB */ +- }; +- +- partition@1000000 { +- label = "rootfs"; +- reg = <0x01000000 0x01000000>; /* 16MB */ +- }; +- }; +-}; +- +-&uart3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/northstar2/ns2.dtsi b/scripts/dtc/include-prefixes/arm64/broadcom/northstar2/ns2.dtsi +deleted file mode 100644 +index 2cfeaf3b0a87..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/northstar2/ns2.dtsi ++++ /dev/null +@@ -1,765 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright (c) 2015 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/memreserve/ 0x81000000 0x00200000; +- +-#include +-#include +- +-/ { +- compatible = "brcm,ns2"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- A57_0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0 0>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER0_L2>; +- }; +- +- A57_1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0 1>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER0_L2>; +- }; +- +- A57_2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0 2>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER0_L2>; +- }; +- +- A57_3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0 3>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER0_L2>; +- }; +- +- CLUSTER0_L2: l2-cache@0 { +- compatible = "cache"; +- }; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&A57_0>, +- <&A57_1>, +- <&A57_2>, +- <&A57_3>; +- }; +- +- pcie0: pcie@20020000 { +- compatible = "brcm,iproc-pcie"; +- reg = <0 0x20020000 0 0x1000>; +- dma-coherent; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; +- +- linux,pci-domain = <0>; +- +- bus-range = <0x00 0xff>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>; +- +- brcm,pcie-ob; +- brcm,pcie-ob-oarr-size; +- brcm,pcie-ob-axi-offset = <0x00000000>; +- brcm,pcie-ob-window-size = <256>; +- +- status = "disabled"; +- +- phys = <&pci_phy0>; +- phy-names = "pcie-phy"; +- +- msi-parent = <&v2m0>; +- }; +- +- pcie4: pcie@50020000 { +- compatible = "brcm,iproc-pcie"; +- reg = <0 0x50020000 0 0x1000>; +- dma-coherent; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; +- +- linux,pci-domain = <4>; +- +- bus-range = <0x00 0xff>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>; +- +- brcm,pcie-ob; +- brcm,pcie-ob-oarr-size; +- brcm,pcie-ob-axi-offset = <0x30000000>; +- brcm,pcie-ob-window-size = <256>; +- +- status = "disabled"; +- +- phys = <&pci_phy1>; +- phy-names = "pcie-phy"; +- +- msi-parent = <&v2m0>; +- }; +- +- pcie8: pcie@60c00000 { +- compatible = "brcm,iproc-pcie-paxc"; +- reg = <0 0x60c00000 0 0x1000>; +- dma-coherent; +- linux,pci-domain = <8>; +- +- bus-range = <0x0 0x1>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x83000000 0 0x00000000 0 0x60000000 0 0x00c00000>; +- +- status = "disabled"; +- +- msi-parent = <&v2m0>; +- }; +- +- soc: soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0 0xffffffff>; +- +- #include "ns2-clock.dtsi" +- +- enet: ethernet@61000000 { +- compatible = "brcm,ns2-amac"; +- reg = <0x61000000 0x1000>, +- <0x61090000 0x1000>, +- <0x61030000 0x100>; +- reg-names = "amac_base", "idm_base", "nicpm_base"; +- interrupts = ; +- dma-coherent; +- phy-handle = <&gphy0>; +- phy-mode = "rgmii"; +- status = "disabled"; +- }; +- +- pdc0: iproc-pdc0@612c0000 { +- compatible = "brcm,iproc-pdc-mbox"; +- reg = <0x612c0000 0x445>; /* PDC FS0 regs */ +- interrupts = ; +- #mbox-cells = <1>; +- dma-coherent; +- brcm,rx-status-len = <32>; +- brcm,use-bcm-hdr; +- }; +- +- crypto0: crypto@612d0000 { +- compatible = "brcm,spum-crypto"; +- reg = <0x612d0000 0x900>; +- mboxes = <&pdc0 0>; +- }; +- +- pdc1: iproc-pdc1@612e0000 { +- compatible = "brcm,iproc-pdc-mbox"; +- reg = <0x612e0000 0x445>; /* PDC FS1 regs */ +- interrupts = ; +- #mbox-cells = <1>; +- dma-coherent; +- brcm,rx-status-len = <32>; +- brcm,use-bcm-hdr; +- }; +- +- crypto1: crypto@612f0000 { +- compatible = "brcm,spum-crypto"; +- reg = <0x612f0000 0x900>; +- mboxes = <&pdc1 0>; +- }; +- +- pdc2: iproc-pdc2@61300000 { +- compatible = "brcm,iproc-pdc-mbox"; +- reg = <0x61300000 0x445>; /* PDC FS2 regs */ +- interrupts = ; +- #mbox-cells = <1>; +- dma-coherent; +- brcm,rx-status-len = <32>; +- brcm,use-bcm-hdr; +- }; +- +- crypto2: crypto@61310000 { +- compatible = "brcm,spum-crypto"; +- reg = <0x61310000 0x900>; +- mboxes = <&pdc2 0>; +- }; +- +- pdc3: iproc-pdc3@61320000 { +- compatible = "brcm,iproc-pdc-mbox"; +- reg = <0x61320000 0x445>; /* PDC FS3 regs */ +- interrupts = ; +- #mbox-cells = <1>; +- dma-coherent; +- brcm,rx-status-len = <32>; +- brcm,use-bcm-hdr; +- }; +- +- crypto3: crypto@61330000 { +- compatible = "brcm,spum-crypto"; +- reg = <0x61330000 0x900>; +- mboxes = <&pdc3 0>; +- }; +- +- dma0: dma@61360000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x61360000 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- clocks = <&iprocslow>; +- clock-names = "apb_pclk"; +- }; +- +- smmu: mmu@64000000 { +- compatible = "arm,mmu-500"; +- reg = <0x64000000 0x40000>; +- #global-interrupts = <2>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- #iommu-cells = <1>; +- }; +- +- pinctrl: pinctrl@6501d130 { +- compatible = "brcm,ns2-pinmux"; +- reg = <0x6501d130 0x08>, +- <0x660a0028 0x04>, +- <0x660009b0 0x40>; +- }; +- +- gpio_aon: gpio@65024800 { +- compatible = "brcm,iproc-gpio"; +- reg = <0x65024800 0x50>, +- <0x65024008 0x18>; +- ngpios = <6>; +- #gpio-cells = <2>; +- gpio-controller; +- }; +- +- gic: interrupt-controller@65210000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x65210000 0x1000>, +- <0x65220000 0x1000>, +- <0x65240000 0x2000>, +- <0x65260000 0x1000>; +- interrupts = ; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x652e0000 0x80000>; +- +- v2m0: v2m@0 { +- compatible = "arm,gic-v2m-frame"; +- interrupt-parent = <&gic>; +- msi-controller; +- reg = <0x00000 0x1000>; +- arm,msi-base-spi = <72>; +- arm,msi-num-spis = <16>; +- }; +- +- v2m1: v2m@10000 { +- compatible = "arm,gic-v2m-frame"; +- interrupt-parent = <&gic>; +- msi-controller; +- reg = <0x10000 0x1000>; +- arm,msi-base-spi = <88>; +- arm,msi-num-spis = <16>; +- }; +- +- v2m2: v2m@20000 { +- compatible = "arm,gic-v2m-frame"; +- interrupt-parent = <&gic>; +- msi-controller; +- reg = <0x20000 0x1000>; +- arm,msi-base-spi = <104>; +- arm,msi-num-spis = <16>; +- }; +- +- v2m3: v2m@30000 { +- compatible = "arm,gic-v2m-frame"; +- interrupt-parent = <&gic>; +- msi-controller; +- reg = <0x30000 0x1000>; +- arm,msi-base-spi = <120>; +- arm,msi-num-spis = <16>; +- }; +- +- v2m4: v2m@40000 { +- compatible = "arm,gic-v2m-frame"; +- interrupt-parent = <&gic>; +- msi-controller; +- reg = <0x40000 0x1000>; +- arm,msi-base-spi = <136>; +- arm,msi-num-spis = <16>; +- }; +- +- v2m5: v2m@50000 { +- compatible = "arm,gic-v2m-frame"; +- interrupt-parent = <&gic>; +- msi-controller; +- reg = <0x50000 0x1000>; +- arm,msi-base-spi = <152>; +- arm,msi-num-spis = <16>; +- }; +- +- v2m6: v2m@60000 { +- compatible = "arm,gic-v2m-frame"; +- interrupt-parent = <&gic>; +- msi-controller; +- reg = <0x60000 0x1000>; +- arm,msi-base-spi = <168>; +- arm,msi-num-spis = <16>; +- }; +- +- v2m7: v2m@70000 { +- compatible = "arm,gic-v2m-frame"; +- interrupt-parent = <&gic>; +- msi-controller; +- reg = <0x70000 0x1000>; +- arm,msi-base-spi = <184>; +- arm,msi-num-spis = <16>; +- }; +- }; +- +- cci@65590000 { +- compatible = "arm,cci-400"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x65590000 0x1000>; +- ranges = <0 0x65590000 0x10000>; +- +- pmu@9000 { +- compatible = "arm,cci-400-pmu,r1", +- "arm,cci-400-pmu"; +- reg = <0x9000 0x4000>; +- interrupts = , +- , +- , +- , +- , +- ; +- }; +- }; +- +- usbdrd_phy: phy@66000960 { +- #phy-cells = <0>; +- compatible = "brcm,ns2-drd-phy"; +- reg = <0x66000960 0x24>, +- <0x67012800 0x4>, +- <0x6501d148 0x4>, +- <0x664d0700 0x4>; +- reg-names = "icfg", "rst-ctrl", +- "crmu-ctrl", "usb2-strap"; +- id-gpios = <&gpio_g 30 0>; +- vbus-gpios = <&gpio_g 31 0>; +- status = "disabled"; +- }; +- +- pwm: pwm@66010000 { +- compatible = "brcm,iproc-pwm"; +- reg = <0x66010000 0x28>; +- clocks = <&osc>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- mdio_mux_iproc: mdio-mux@66020000 { +- compatible = "brcm,mdio-mux-iproc"; +- reg = <0x66020000 0x250>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- mdio@0 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pci_phy0: pci-phy@0 { +- compatible = "brcm,ns2-pcie-phy"; +- reg = <0x0>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- mdio@7 { +- reg = <0x7>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pci_phy1: pci-phy@0 { +- compatible = "brcm,ns2-pcie-phy"; +- reg = <0x0>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- mdio@10 { +- reg = <0x10>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- timer0: timer@66030000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x66030000 0x1000>; +- interrupts = ; +- clocks = <&iprocslow>, +- <&iprocslow>, +- <&iprocslow>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- }; +- +- timer1: timer@66040000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x66040000 0x1000>; +- interrupts = ; +- clocks = <&iprocslow>, +- <&iprocslow>, +- <&iprocslow>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- }; +- +- timer2: timer@66050000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x66050000 0x1000>; +- interrupts = ; +- clocks = <&iprocslow>, +- <&iprocslow>, +- <&iprocslow>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- }; +- +- timer3: timer@66060000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x66060000 0x1000>; +- interrupts = ; +- clocks = <&iprocslow>, +- <&iprocslow>, +- <&iprocslow>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- }; +- +- i2c0: i2c@66080000 { +- compatible = "brcm,iproc-i2c"; +- reg = <0x66080000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clock-frequency = <100000>; +- status = "disabled"; +- }; +- +- wdt0: watchdog@66090000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x66090000 0x1000>; +- interrupts = ; +- clocks = <&iprocslow>, <&iprocslow>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- gpio_g: gpio@660a0000 { +- compatible = "brcm,iproc-gpio"; +- reg = <0x660a0000 0x50>; +- ngpios = <32>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupts = ; +- }; +- +- i2c1: i2c@660b0000 { +- compatible = "brcm,iproc-i2c"; +- reg = <0x660b0000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clock-frequency = <100000>; +- status = "disabled"; +- }; +- +- uart0: serial@66100000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x66100000 0x100>; +- interrupts = ; +- clocks = <&iprocslow>; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart1: serial@66110000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x66110000 0x100>; +- interrupts = ; +- clocks = <&iprocslow>; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart2: serial@66120000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x66120000 0x100>; +- interrupts = ; +- clocks = <&iprocslow>; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart3: serial@66130000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x66130000 0x100>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&osc>; +- status = "disabled"; +- }; +- +- ssp0: spi@66180000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x66180000 0x1000>; +- interrupts = ; +- clocks = <&iprocslow>, <&iprocslow>; +- clock-names = "spiclk", "apb_pclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- ssp1: spi@66190000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x66190000 0x1000>; +- interrupts = ; +- clocks = <&iprocslow>, <&iprocslow>; +- clock-names = "spiclk", "apb_pclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- hwrng: hwrng@66220000 { +- compatible = "brcm,iproc-rng200"; +- reg = <0x66220000 0x28>; +- }; +- +- sata_phy: sata_phy@663f0100 { +- compatible = "brcm,iproc-ns2-sata-phy"; +- reg = <0x663f0100 0x1f00>, +- <0x663f004c 0x10>; +- reg-names = "phy", "phy-ctrl"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- sata_phy0: sata-phy@0 { +- reg = <0>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- sata_phy1: sata-phy@1 { +- reg = <1>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- sata: ahci@663f2000 { +- compatible = "brcm,iproc-ahci", "generic-ahci"; +- reg = <0x663f2000 0x1000>; +- dma-coherent; +- reg-names = "ahci"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- sata0: sata-port@0 { +- reg = <0>; +- phys = <&sata_phy0>; +- phy-names = "sata-phy"; +- }; +- +- sata1: sata-port@1 { +- reg = <1>; +- phys = <&sata_phy1>; +- phy-names = "sata-phy"; +- }; +- }; +- +- sdio0: sdhci@66420000 { +- compatible = "brcm,sdhci-iproc-cygnus"; +- reg = <0x66420000 0x100>; +- interrupts = ; +- dma-coherent; +- bus-width = <8>; +- clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; +- status = "disabled"; +- }; +- +- sdio1: sdhci@66430000 { +- compatible = "brcm,sdhci-iproc-cygnus"; +- reg = <0x66430000 0x100>; +- interrupts = ; +- dma-coherent; +- bus-width = <8>; +- clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; +- status = "disabled"; +- }; +- +- nand: nand@66460000 { +- compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; +- reg = <0x66460000 0x600>, +- <0x67015408 0x600>, +- <0x66460f00 0x20>; +- reg-names = "nand", "iproc-idm", "iproc-ext"; +- interrupts = ; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- brcm,nand-has-wp; +- }; +- +- qspi: spi@66470200 { +- compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi"; +- reg = <0x66470200 0x184>, +- <0x66470000 0x124>, +- <0x67017408 0x004>, +- <0x664703a0 0x01c>; +- reg-names = "mspi", "bspi", "intr_regs", +- "intr_status_reg"; +- interrupts = ; +- interrupt-names = "spi_l1_intr"; +- clocks = <&iprocmed>; +- clock-names = "iprocmed"; +- num-cs = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/Makefile b/scripts/dtc/include-prefixes/arm64/broadcom/stingray/Makefile +deleted file mode 100644 +index 20c7d0aa6cb7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/Makefile ++++ /dev/null +@@ -1,5 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958742k.dtb +-dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958742t.dtb +- +-dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958802a802x.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/bcm958742-base.dtsi b/scripts/dtc/include-prefixes/arm64/broadcom/stingray/bcm958742-base.dtsi +deleted file mode 100644 +index 8fe7325cfbb2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/bcm958742-base.dtsi ++++ /dev/null +@@ -1,112 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2016-2017 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#include "stingray-board-base.dtsi" +- +-/ { +- sdio0_vddo_ctrl_reg: sdio0_vddo_ctrl { +- compatible = "regulator-gpio"; +- regulator-name = "sdio0_vddo_ctrl_reg"; +- regulator-type = "voltage"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- gpios = <&pca9505 18 0>; +- states = <3300000 0x0 +- 1800000 0x1>; +- }; +- +- sdio1_vddo_ctrl_reg: sdio1_vddo_ctrl { +- compatible = "regulator-gpio"; +- regulator-name = "sdio1_vddo_ctrl_reg"; +- regulator-type = "voltage"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- gpios = <&pca9505 19 0>; +- states = <3300000 0x0 +- 1800000 0x1>; +- }; +-}; +- +-&pwm { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- pca9505: pca9505@20 { +- compatible = "nxp,pca9505"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x20>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- pcf8574: pcf8574@27 { +- compatible = "nxp,pcf8574a"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x27>; +- }; +-}; +- +-&enet { +- status = "okay"; +-}; +- +-&nand { +- status = "okay"; +- nandcs@0 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <8>; +- nand-ecc-step-size = <512>; +- nand-bus-width = <16>; +- brcm,nand-oob-sector-size = <16>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&sdio0 { +- vqmmc-supply = <&sdio0_vddo_ctrl_reg>; +- status = "okay"; +-}; +- +-&sdio1 { +- vqmmc-supply = <&sdio1_vddo_ctrl_reg>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/bcm958742k.dts b/scripts/dtc/include-prefixes/arm64/broadcom/stingray/bcm958742k.dts +deleted file mode 100644 +index 77efa28c4dd5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/bcm958742k.dts ++++ /dev/null +@@ -1,86 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2016-2017 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "bcm958742-base.dtsi" +- +-/ { +- compatible = "brcm,bcm958742k", "brcm,stingray"; +- model = "Stingray Combo SVK (BCM958742K)"; +-}; +- +-&gphy0 { +- enet-phy-lane-swap; +-}; +- +-&sdio0 { +- mmc-ddr-1_8v; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&ssp0 { +- pinctrl-0 = <&spi0_pins>; +- pinctrl-names = "default"; +- cs-gpios = <&gpio_hsls 34 0>; +- status = "okay"; +- +- spi-flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&ssp1 { +- pinctrl-0 = <&spi1_pins>; +- pinctrl-names = "default"; +- cs-gpios = <&gpio_hsls 96 0>; +- status = "okay"; +- +- spi-flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/bcm958742t.dts b/scripts/dtc/include-prefixes/arm64/broadcom/stingray/bcm958742t.dts +deleted file mode 100644 +index 55ba495ef56e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/bcm958742t.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2017 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "bcm958742-base.dtsi" +- +-/ { +- compatible = "brcm,bcm958742t", "brcm,stingray"; +- model = "Stingray SST100 (BCM958742T)"; +-}; +- +-&gphy0 { +- enet-phy-lane-swap; +-}; +- +-&sdio0 { +- mmc-ddr-1_8v; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/bcm958802a802x.dts b/scripts/dtc/include-prefixes/arm64/broadcom/stingray/bcm958802a802x.dts +deleted file mode 100644 +index a41facd7d79b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/bcm958802a802x.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) +-/* +- *Copyright(c) 2018 Broadcom +- */ +- +-/dts-v1/; +- +-#include "stingray-board-base.dtsi" +- +-/ { +- compatible = "brcm,bcm958802a802x", "brcm,stingray"; +- model = "Stingray PS225xx (BCM958802A802x)"; +-}; +- +-&enet { +- status = "disabled"; +-}; +- +-&sdio0 { +- no-1-8-v; +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray-board-base.dtsi b/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray-board-base.dtsi +deleted file mode 100644 +index 82a24711d0d8..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray-board-base.dtsi ++++ /dev/null +@@ -1,51 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) +-/* +- * Copyright(c) 2016-2018 Broadcom +- */ +- +-#include "stingray.dtsi" +-#include +- +-/ { +- aliases { +- serial0 = &uart1; +- serial1 = &uart0; +- serial2 = &uart2; +- serial3 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&memory { /* Default DRAM banks */ +- reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ +- <0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */ +-}; +- +-&enet { +- phy-mode = "rgmii-id"; +- phy-handle = <&gphy0>; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&sdio0 { +- non-removable; +- full-pwr-cycle; +-}; +- +-&sdio1 { +- full-pwr-cycle; +-}; +- +-&mdio_mux_iproc { +- mdio@10 { +- gphy0: eth-phy@10 { +- reg = <0x10>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray-clock.dtsi b/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray-clock.dtsi +deleted file mode 100644 +index 10a106aca229..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray-clock.dtsi ++++ /dev/null +@@ -1,182 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2016-2017 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#include +- +- osc: oscillator { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- }; +- +- crmu_ref25m: crmu_ref25m { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&osc>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- genpll0: genpll0@1d104 { +- #clock-cells = <1>; +- compatible = "brcm,sr-genpll0"; +- reg = <0x0001d104 0x32>, +- <0x0001c854 0x4>; +- clocks = <&osc>; +- clock-output-names = "genpll0", "clk_125m", "clk_scr", +- "clk_250", "clk_pcie_axi", +- "clk_paxc_axi_x2", +- "clk_paxc_axi"; +- }; +- +- genpll2: genpll2@1d1ac { +- #clock-cells = <1>; +- compatible = "brcm,sr-genpll2"; +- reg = <0x0001d1ac 0x32>, +- <0x0001c854 0x4>; +- clocks = <&osc>; +- clock-output-names = "genpll2", "clk_nic", +- "clk_ts_500_ref", "clk_125_nitro", +- "clk_chimp", "clk_nic_flash", +- "clk_fs"; +- }; +- +- genpll3: genpll3@1d1e0 { +- #clock-cells = <1>; +- compatible = "brcm,sr-genpll3"; +- reg = <0x0001d1e0 0x32>, +- <0x0001c854 0x4>; +- clocks = <&osc>; +- clock-output-names = "genpll3", "clk_hsls", +- "clk_sdio"; +- }; +- +- genpll4: genpll4@1d214 { +- #clock-cells = <1>; +- compatible = "brcm,sr-genpll4"; +- reg = <0x0001d214 0x32>, +- <0x0001c854 0x4>; +- clocks = <&osc>; +- clock-output-names = "genpll4", "clk_ccn", +- "clk_tpiu_pll", "clk_noc", +- "clk_chclk_fs4", +- "clk_bridge_fscpu"; +- }; +- +- genpll5: genpll5@1d248 { +- #clock-cells = <1>; +- compatible = "brcm,sr-genpll5"; +- reg = <0x0001d248 0x32>, +- <0x0001c870 0x4>; +- clocks = <&osc>; +- clock-output-names = "genpll5", "clk_fs4_hf", +- "clk_crypto_ae", "clk_raid_ae"; +- }; +- +- lcpll0: lcpll0@1d0c4 { +- #clock-cells = <1>; +- compatible = "brcm,sr-lcpll0"; +- reg = <0x0001d0c4 0x3c>, +- <0x0001c870 0x4>; +- clocks = <&osc>; +- clock-output-names = "lcpll0", "clk_sata_refp", +- "clk_sata_refn", "clk_sata_350", +- "clk_sata_500"; +- }; +- +- lcpll1: lcpll1@1d138 { +- #clock-cells = <1>; +- compatible = "brcm,sr-lcpll1"; +- reg = <0x0001d138 0x3c>, +- <0x0001c870 0x4>; +- clocks = <&osc>; +- clock-output-names = "lcpll1", "clk_wan", +- "clk_usb_ref", +- "clk_crmu_ts"; +- }; +- +- hsls_clk: hsls_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&genpll3 1>; +- clock-div = <1>; +- clock-mult = <1>; +- }; +- +- hsls_div2_clk: hsls_div2_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; +- clock-div = <2>; +- clock-mult = <1>; +- +- }; +- +- hsls_div4_clk: hsls_div4_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; +- clock-div = <4>; +- clock-mult = <1>; +- }; +- +- hsls_25m_clk: hsls_25m_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&crmu_ref25m>; +- clock-div = <1>; +- clock-mult = <1>; +- }; +- +- hsls_25m_div2_clk: hsls_25m_div2_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&hsls_25m_clk>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- sdio0_clk: sdio0_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; +- clock-div = <1>; +- clock-mult = <1>; +- }; +- +- sdio1_clk: sdio1_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; +- clock-div = <1>; +- clock-mult = <1>; +- }; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray-fs4.dtsi b/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray-fs4.dtsi +deleted file mode 100644 +index 9666969c8c88..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray-fs4.dtsi ++++ /dev/null +@@ -1,118 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2016-2017 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +- fs4: fs4 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x67000000 0x00800000>; +- +- crypto_mbox: crypto_mbox@0 { +- compatible = "brcm,iproc-flexrm-mbox"; +- reg = <0x00000000 0x200000>; +- msi-parent = <&gic_its 0x4100>; +- #mbox-cells = <3>; +- dma-coherent; +- }; +- +- raid_mbox: raid_mbox@400000 { +- compatible = "brcm,iproc-flexrm-mbox"; +- reg = <0x00400000 0x200000>; +- dma-coherent; +- msi-parent = <&gic_its 0x4300>; +- #mbox-cells = <3>; +- }; +- +- raid0: raid@0 { +- compatible = "brcm,iproc-sba-v2"; +- mboxes = <&raid_mbox 0 0x1 0xff00>, +- <&raid_mbox 1 0x1 0xff00>, +- <&raid_mbox 2 0x1 0xff00>, +- <&raid_mbox 3 0x1 0xff00>; +- }; +- +- raid1: raid@1 { +- compatible = "brcm,iproc-sba-v2"; +- mboxes = <&raid_mbox 4 0x1 0xff00>, +- <&raid_mbox 5 0x1 0xff00>, +- <&raid_mbox 6 0x1 0xff00>, +- <&raid_mbox 7 0x1 0xff00>; +- }; +- +- raid2: raid@2 { +- compatible = "brcm,iproc-sba-v2"; +- mboxes = <&raid_mbox 8 0x1 0xff00>, +- <&raid_mbox 9 0x1 0xff00>, +- <&raid_mbox 10 0x1 0xff00>, +- <&raid_mbox 11 0x1 0xff00>; +- }; +- +- raid3: raid@3 { +- compatible = "brcm,iproc-sba-v2"; +- mboxes = <&raid_mbox 12 0x1 0xff00>, +- <&raid_mbox 13 0x1 0xff00>, +- <&raid_mbox 14 0x1 0xff00>, +- <&raid_mbox 15 0x1 0xff00>; +- }; +- +- raid4: raid@4 { +- compatible = "brcm,iproc-sba-v2"; +- mboxes = <&raid_mbox 16 0x1 0xff00>, +- <&raid_mbox 17 0x1 0xff00>, +- <&raid_mbox 18 0x1 0xff00>, +- <&raid_mbox 19 0x1 0xff00>; +- }; +- +- raid5: raid@5 { +- compatible = "brcm,iproc-sba-v2"; +- mboxes = <&raid_mbox 20 0x1 0xff00>, +- <&raid_mbox 21 0x1 0xff00>, +- <&raid_mbox 22 0x1 0xff00>, +- <&raid_mbox 23 0x1 0xff00>; +- }; +- +- raid6: raid@6 { +- compatible = "brcm,iproc-sba-v2"; +- mboxes = <&raid_mbox 24 0x1 0xff00>, +- <&raid_mbox 25 0x1 0xff00>, +- <&raid_mbox 26 0x1 0xff00>, +- <&raid_mbox 27 0x1 0xff00>; +- }; +- +- raid7: raid@7 { +- compatible = "brcm,iproc-sba-v2"; +- mboxes = <&raid_mbox 28 0x1 0xff00>, +- <&raid_mbox 29 0x1 0xff00>, +- <&raid_mbox 30 0x1 0xff00>, +- <&raid_mbox 31 0x1 0xff00>; +- }; +- }; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray-pcie.dtsi b/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray-pcie.dtsi +deleted file mode 100644 +index 33a472ab17e8..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray-pcie.dtsi ++++ /dev/null +@@ -1,54 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) +-/* +- *Copyright(c) 2018 Broadcom +- */ +- +-pcie8: pcie@60400000 { +- compatible = "brcm,iproc-pcie-paxc-v2"; +- reg = <0 0x60400000 0 0x1000>; +- linux,pci-domain = <8>; +- +- bus-range = <0x0 0x1>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>; +- +- dma-coherent; +- +- msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */ +- <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */ +- <0x101 &gic_its 0x2080 0x1>, /* PF1 */ +- <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */ +- <0x102 &gic_its 0x2100 0x1>, /* PF2 */ +- <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */ +- <0x103 &gic_its 0x2180 0x1>, /* PF3 */ +- <0x120 &gic_its 0x21d8 0x8>, /* PF3-VF24-31 */ +- <0x104 &gic_its 0x2200 0x1>, /* PF4 */ +- <0x128 &gic_its 0x2260 0x8>, /* PF4-VF32-39 */ +- <0x105 &gic_its 0x2280 0x1>, /* PF5 */ +- <0x130 &gic_its 0x22e8 0x8>, /* PF5-VF40-47 */ +- <0x106 &gic_its 0x2300 0x1>, /* PF6 */ +- <0x138 &gic_its 0x2370 0x8>, /* PF6-VF48-55 */ +- <0x107 &gic_its 0x2380 0x1>, /* PF7 */ +- <0x140 &gic_its 0x23f8 0x8>; /* PF7-VF56-63 */ +- +- phys = <&pcie_phy 8>; +- phy-names = "pcie-phy"; +-}; +- +-pcie-ss { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x40000000 0x800>; +- +- pcie_phy: phy@0 { +- compatible = "brcm,sr-pcie-phy"; +- reg = <0x0 0x200>; +- brcm,sr-cdru = <&cdru>; +- brcm,sr-mhb = <&mhb>; +- #phy-cells = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray-pinctrl.dtsi +deleted file mode 100644 +index 56789ccf9454..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray-pinctrl.dtsi ++++ /dev/null +@@ -1,346 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2016-2017 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#include +- +- pinconf: pinconf@140000 { +- compatible = "pinconf-single"; +- reg = <0x00140000 0x250>; +- pinctrl-single,register-width = <32>; +- +- /* pinconf functions */ +- }; +- +- pinmux: pinmux@14029c { +- compatible = "pinctrl-single"; +- reg = <0x0014029c 0x26c>; +- #address-cells = <1>; +- #size-cells = <1>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0xf>; +- pinctrl-single,gpio-range = < +- &range 0 91 MODE_GPIO +- &range 95 60 MODE_GPIO +- >; +- range: gpio-range { +- #pinctrl-single,gpio-range-cells = <3>; +- }; +- +- /* pinctrl functions */ +- tsio_pins: pinmux_gpio_14 { +- pinctrl-single,pins = < +- 0x038 MODE_NITRO /* tsio_0 */ +- 0x03c MODE_NITRO /* tsio_1 */ +- >; +- }; +- +- nor_pins: pinmux_pnor_adv_n { +- pinctrl-single,pins = < +- 0x0ac MODE_PNOR /* nand_ce1_n */ +- 0x0b0 MODE_PNOR /* nand_ce0_n */ +- 0x0b4 MODE_PNOR /* nand_we_n */ +- 0x0b8 MODE_PNOR /* nand_wp_n */ +- 0x0bc MODE_PNOR /* nand_re_n */ +- 0x0c0 MODE_PNOR /* nand_rdy_bsy_n */ +- 0x0c4 MODE_PNOR /* nand_io0_0 */ +- 0x0c8 MODE_PNOR /* nand_io1_0 */ +- 0x0cc MODE_PNOR /* nand_io2_0 */ +- 0x0d0 MODE_PNOR /* nand_io3_0 */ +- 0x0d4 MODE_PNOR /* nand_io4_0 */ +- 0x0d8 MODE_PNOR /* nand_io5_0 */ +- 0x0dc MODE_PNOR /* nand_io6_0 */ +- 0x0e0 MODE_PNOR /* nand_io7_0 */ +- 0x0e4 MODE_PNOR /* nand_io8_0 */ +- 0x0e8 MODE_PNOR /* nand_io9_0 */ +- 0x0ec MODE_PNOR /* nand_io10_0 */ +- 0x0f0 MODE_PNOR /* nand_io11_0 */ +- 0x0f4 MODE_PNOR /* nand_io12_0 */ +- 0x0f8 MODE_PNOR /* nand_io13_0 */ +- 0x0fc MODE_PNOR /* nand_io14_0 */ +- 0x100 MODE_PNOR /* nand_io15_0 */ +- 0x104 MODE_PNOR /* nand_ale_0 */ +- 0x108 MODE_PNOR /* nand_cle_0 */ +- 0x040 MODE_PNOR /* pnor_adv_n */ +- 0x044 MODE_PNOR /* pnor_baa_n */ +- 0x048 MODE_PNOR /* pnor_bls_0_n */ +- 0x04c MODE_PNOR /* pnor_bls_1_n */ +- 0x050 MODE_PNOR /* pnor_cre */ +- 0x054 MODE_PNOR /* pnor_cs_2_n */ +- 0x058 MODE_PNOR /* pnor_cs_1_n */ +- 0x05c MODE_PNOR /* pnor_cs_0_n */ +- 0x060 MODE_PNOR /* pnor_we_n */ +- 0x064 MODE_PNOR /* pnor_oe_n */ +- 0x068 MODE_PNOR /* pnor_intr */ +- 0x06c MODE_PNOR /* pnor_dat_0 */ +- 0x070 MODE_PNOR /* pnor_dat_1 */ +- 0x074 MODE_PNOR /* pnor_dat_2 */ +- 0x078 MODE_PNOR /* pnor_dat_3 */ +- 0x07c MODE_PNOR /* pnor_dat_4 */ +- 0x080 MODE_PNOR /* pnor_dat_5 */ +- 0x084 MODE_PNOR /* pnor_dat_6 */ +- 0x088 MODE_PNOR /* pnor_dat_7 */ +- 0x08c MODE_PNOR /* pnor_dat_8 */ +- 0x090 MODE_PNOR /* pnor_dat_9 */ +- 0x094 MODE_PNOR /* pnor_dat_10 */ +- 0x098 MODE_PNOR /* pnor_dat_11 */ +- 0x09c MODE_PNOR /* pnor_dat_12 */ +- 0x0a0 MODE_PNOR /* pnor_dat_13 */ +- 0x0a4 MODE_PNOR /* pnor_dat_14 */ +- 0x0a8 MODE_PNOR /* pnor_dat_15 */ +- >; +- }; +- +- nand_pins: pinmux_nand_ce1_n { +- pinctrl-single,pins = < +- 0x0ac MODE_NAND /* nand_ce1_n */ +- 0x0b0 MODE_NAND /* nand_ce0_n */ +- 0x0b4 MODE_NAND /* nand_we_n */ +- 0x0b8 MODE_NAND /* nand_wp_n */ +- 0x0bc MODE_NAND /* nand_re_n */ +- 0x0c0 MODE_NAND /* nand_rdy_bsy_n */ +- 0x0c4 MODE_NAND /* nand_io0_0 */ +- 0x0c8 MODE_NAND /* nand_io1_0 */ +- 0x0cc MODE_NAND /* nand_io2_0 */ +- 0x0d0 MODE_NAND /* nand_io3_0 */ +- 0x0d4 MODE_NAND /* nand_io4_0 */ +- 0x0d8 MODE_NAND /* nand_io5_0 */ +- 0x0dc MODE_NAND /* nand_io6_0 */ +- 0x0e0 MODE_NAND /* nand_io7_0 */ +- 0x0e4 MODE_NAND /* nand_io8_0 */ +- 0x0e8 MODE_NAND /* nand_io9_0 */ +- 0x0ec MODE_NAND /* nand_io10_0 */ +- 0x0f0 MODE_NAND /* nand_io11_0 */ +- 0x0f4 MODE_NAND /* nand_io12_0 */ +- 0x0f8 MODE_NAND /* nand_io13_0 */ +- 0x0fc MODE_NAND /* nand_io14_0 */ +- 0x100 MODE_NAND /* nand_io15_0 */ +- 0x104 MODE_NAND /* nand_ale_0 */ +- 0x108 MODE_NAND /* nand_cle_0 */ +- >; +- }; +- +- pwm0_pins: pinmux_pwm_0 { +- pinctrl-single,pins = < +- 0x10c MODE_NITRO +- >; +- }; +- +- pwm1_pins: pinmux_pwm_1 { +- pinctrl-single,pins = < +- 0x110 MODE_NITRO +- >; +- }; +- +- pwm2_pins: pinmux_pwm_2 { +- pinctrl-single,pins = < +- 0x114 MODE_NITRO +- >; +- }; +- +- pwm3_pins: pinmux_pwm_3 { +- pinctrl-single,pins = < +- 0x118 MODE_NITRO +- >; +- }; +- +- dbu_rxd_pins: pinmux_uart1_sin_nitro { +- pinctrl-single,pins = < +- 0x11c MODE_NITRO /* dbu_rxd */ +- 0x120 MODE_NITRO /* dbu_txd */ +- >; +- }; +- +- uart1_pins: pinmux_uart1_sin_nand { +- pinctrl-single,pins = < +- 0x11c MODE_NAND /* uart1_sin */ +- 0x120 MODE_NAND /* uart1_out */ +- >; +- }; +- +- uart2_pins: pinmux_uart2_sin { +- pinctrl-single,pins = < +- 0x124 MODE_NITRO /* uart2_sin */ +- 0x128 MODE_NITRO /* uart2_out */ +- >; +- }; +- +- uart3_pins: pinmux_uart3_sin { +- pinctrl-single,pins = < +- 0x12c MODE_NITRO /* uart3_sin */ +- 0x130 MODE_NITRO /* uart3_out */ +- >; +- }; +- +- i2s_pins: pinmux_i2s_bitclk { +- pinctrl-single,pins = < +- 0x134 MODE_NITRO /* i2s_bitclk */ +- 0x138 MODE_NITRO /* i2s_sdout */ +- 0x13c MODE_NITRO /* i2s_sdin */ +- 0x140 MODE_NITRO /* i2s_ws */ +- 0x144 MODE_NITRO /* i2s_mclk */ +- 0x148 MODE_NITRO /* i2s_spdif_out */ +- >; +- }; +- +- qspi_pins: pinumx_qspi_hold_n { +- pinctrl-single,pins = < +- 0x14c MODE_NAND /* qspi_hold_n */ +- 0x150 MODE_NAND /* qspi_wp_n */ +- 0x154 MODE_NAND /* qspi_sck */ +- 0x158 MODE_NAND /* qspi_cs_n */ +- 0x15c MODE_NAND /* qspi_mosi */ +- 0x160 MODE_NAND /* qspi_miso */ +- >; +- }; +- +- mdio_pins: pinumx_ext_mdio { +- pinctrl-single,pins = < +- 0x164 MODE_NITRO /* ext_mdio */ +- 0x168 MODE_NITRO /* ext_mdc */ +- >; +- }; +- +- i2c0_pins: pinmux_i2c0_sda { +- pinctrl-single,pins = < +- 0x16c MODE_NITRO /* i2c0_sda */ +- 0x170 MODE_NITRO /* i2c0_scl */ +- >; +- }; +- +- i2c1_pins: pinmux_i2c1_sda { +- pinctrl-single,pins = < +- 0x174 MODE_NITRO /* i2c1_sda */ +- 0x178 MODE_NITRO /* i2c1_scl */ +- >; +- }; +- +- sdio0_pins: pinmux_sdio0_cd_l { +- pinctrl-single,pins = < +- 0x17c MODE_NITRO /* sdio0_cd_l */ +- 0x180 MODE_NITRO /* sdio0_clk_sdcard */ +- 0x184 MODE_NITRO /* sdio0_data0 */ +- 0x188 MODE_NITRO /* sdio0_data1 */ +- 0x18c MODE_NITRO /* sdio0_data2 */ +- 0x190 MODE_NITRO /* sdio0_data3 */ +- 0x194 MODE_NITRO /* sdio0_data4 */ +- 0x198 MODE_NITRO /* sdio0_data5 */ +- 0x19c MODE_NITRO /* sdio0_data6 */ +- 0x1a0 MODE_NITRO /* sdio0_data7 */ +- 0x1a4 MODE_NITRO /* sdio0_cmd */ +- 0x1a8 MODE_NITRO /* sdio0_emmc_rst_n */ +- 0x1ac MODE_NITRO /* sdio0_led_on */ +- 0x1b0 MODE_NITRO /* sdio0_wp */ +- >; +- }; +- +- sdio1_pins: pinmux_sdio1_cd_l { +- pinctrl-single,pins = < +- 0x1b4 MODE_NITRO /* sdio1_cd_l */ +- 0x1b8 MODE_NITRO /* sdio1_clk_sdcard */ +- 0x1bc MODE_NITRO /* sdio1_data0 */ +- 0x1c0 MODE_NITRO /* sdio1_data1 */ +- 0x1c4 MODE_NITRO /* sdio1_data2 */ +- 0x1c8 MODE_NITRO /* sdio1_data3 */ +- 0x1cc MODE_NITRO /* sdio1_data4 */ +- 0x1d0 MODE_NITRO /* sdio1_data5 */ +- 0x1d4 MODE_NITRO /* sdio1_data6 */ +- 0x1d8 MODE_NITRO /* sdio1_data7 */ +- 0x1dc MODE_NITRO /* sdio1_cmd */ +- 0x1e0 MODE_NITRO /* sdio1_emmc_rst_n */ +- 0x1e4 MODE_NITRO /* sdio1_led_on */ +- 0x1e8 MODE_NITRO /* sdio1_wp */ +- >; +- }; +- +- spi0_pins: pinmux_spi0_sck_nand { +- pinctrl-single,pins = < +- 0x1ec MODE_NITRO /* spi0_sck */ +- 0x1f0 MODE_NITRO /* spi0_rxd */ +- 0x1f4 MODE_NITRO /* spi0_fss */ +- 0x1f8 MODE_NITRO /* spi0_txd */ +- >; +- }; +- +- spi1_pins: pinmux_spi1_sck_nand { +- pinctrl-single,pins = < +- 0x1fc MODE_NITRO /* spi1_sck */ +- 0x200 MODE_NITRO /* spi1_rxd */ +- 0x204 MODE_NITRO /* spi1_fss */ +- 0x208 MODE_NITRO /* spi1_txd */ +- >; +- }; +- +- nuart_pins: pinmux_uart0_sin_nitro { +- pinctrl-single,pins = < +- 0x20c MODE_NITRO /* nuart_rxd */ +- 0x210 MODE_NITRO /* nuart_txd */ +- >; +- }; +- +- uart0_pins: pinumux_uart0_sin_nand { +- pinctrl-single,pins = < +- 0x20c MODE_NAND /* uart0_sin */ +- 0x210 MODE_NAND /* uart0_out */ +- 0x214 MODE_NAND /* uart0_rts */ +- 0x218 MODE_NAND /* uart0_cts */ +- 0x21c MODE_NAND /* uart0_dtr */ +- 0x220 MODE_NAND /* uart0_dcd */ +- 0x224 MODE_NAND /* uart0_dsr */ +- 0x228 MODE_NAND /* uart0_ri */ +- >; +- }; +- +- drdu2_pins: pinmux_drdu2_overcurrent { +- pinctrl-single,pins = < +- 0x22c MODE_NITRO /* drdu2_overcurrent */ +- 0x230 MODE_NITRO /* drdu2_vbus_ppc */ +- 0x234 MODE_NITRO /* drdu2_vbus_present */ +- 0x238 MODE_NITRO /* drdu2_id */ +- >; +- }; +- +- drdu3_pins: pinmux_drdu3_overcurrent { +- pinctrl-single,pins = < +- 0x23c MODE_NITRO /* drdu3_overcurrent */ +- 0x240 MODE_NITRO /* drdu3_vbus_ppc */ +- 0x244 MODE_NITRO /* drdu3_vbus_present */ +- 0x248 MODE_NITRO /* drdu3_id */ +- >; +- }; +- +- usb3h_pins: pinmux_usb3h_overcurrent { +- pinctrl-single,pins = < +- 0x24c MODE_NITRO /* usb3h_overcurrent */ +- 0x250 MODE_NITRO /* usb3h_vbus_ppc */ +- >; +- }; +- }; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray-usb.dtsi b/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray-usb.dtsi +deleted file mode 100644 +index 5401a646c840..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray-usb.dtsi ++++ /dev/null +@@ -1,77 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) +-/* +- *Copyright(c) 2018 Broadcom +- */ +- usb { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0x68500000 0x0 0x00400000>; +- +- /* +- * Internally, USB bus to the interconnect can only address up +- * to 40-bit +- */ +- dma-ranges = <0 0 0 0 0x100 0x0>; +- +- usbphy0: usb-phy@0 { +- compatible = "brcm,sr-usb-combo-phy"; +- reg = <0x0 0x00000000 0x0 0x100>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- xhci0: usb@1000 { +- compatible = "generic-xhci"; +- reg = <0x0 0x00001000 0x0 0x1000>; +- interrupts = ; +- phys = <&usbphy0 1>, <&usbphy0 0>; +- phy-names = "phy0", "phy1"; +- dma-coherent; +- status = "disabled"; +- }; +- +- bdc0: usb@2000 { +- compatible = "brcm,bdc-v0.16"; +- reg = <0x0 0x00002000 0x0 0x1000>; +- interrupts = ; +- phys = <&usbphy0 0>, <&usbphy0 1>; +- phy-names = "phy0", "phy1"; +- dma-coherent; +- status = "disabled"; +- }; +- +- usbphy1: usb-phy@10000 { +- compatible = "brcm,sr-usb-combo-phy"; +- reg = <0x0 0x00010000 0x0 0x100>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- usbphy2: usb-phy@20000 { +- compatible = "brcm,sr-usb-hs-phy"; +- reg = <0x0 0x00020000 0x0 0x100>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- xhci1: usb@11000 { +- compatible = "generic-xhci"; +- reg = <0x0 0x00011000 0x0 0x1000>; +- interrupts = ; +- phys = <&usbphy1 1>, <&usbphy2>, <&usbphy1 0>; +- phy-names = "phy0", "phy1", "phy2"; +- dma-coherent; +- status = "disabled"; +- }; +- +- bdc1: usb@21000 { +- compatible = "brcm,bdc-v0.16"; +- reg = <0x0 0x00021000 0x0 0x1000>; +- interrupts = ; +- phys = <&usbphy2>; +- phy-names = "phy0"; +- dma-coherent; +- status = "disabled"; +- }; +- }; +diff --git a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray.dtsi b/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray.dtsi +deleted file mode 100644 +index 7b04dfe67bef..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/broadcom/stingray/stingray.dtsi ++++ /dev/null +@@ -1,715 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2015-2017 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#include +- +-/ { +- compatible = "brcm,stingray"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER0_L2>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER0_L2>; +- }; +- +- cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER1_L2>; +- }; +- +- cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x0 0x101>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER1_L2>; +- }; +- +- cpu@200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x0 0x200>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER2_L2>; +- }; +- +- cpu@201 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x0 0x201>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER2_L2>; +- }; +- +- cpu@300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x0 0x300>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER3_L2>; +- }; +- +- cpu@301 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x0 0x301>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER3_L2>; +- }; +- +- CLUSTER0_L2: l2-cache@0 { +- compatible = "cache"; +- }; +- +- CLUSTER1_L2: l2-cache@100 { +- compatible = "cache"; +- }; +- +- CLUSTER2_L2: l2-cache@200 { +- compatible = "cache"; +- }; +- +- CLUSTER3_L2: l2-cache@300 { +- compatible = "cache"; +- }; +- }; +- +- memory: memory@80000000 { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0 0x40000000>; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = ; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- mhb: syscon@60401000 { +- compatible = "brcm,sr-mhb", "syscon"; +- reg = <0 0x60401000 0 0x38c>; +- }; +- +- scr { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x61000000 0x05000000>; +- +- ccn: ccn@0 { +- compatible = "arm,ccn-502"; +- reg = <0x00000000 0x900000>; +- interrupts = ; +- }; +- +- gic: interrupt-controller@2c00000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- interrupt-controller; +- reg = <0x02c00000 0x010000>, /* GICD */ +- <0x02e00000 0x600000>; /* GICR */ +- interrupts = ; +- +- gic_its: gic-its@63c20000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0x02c20000 0x10000>; +- }; +- }; +- +- smmu: mmu@3000000 { +- compatible = "arm,mmu-500"; +- reg = <0x03000000 0x80000>; +- #global-interrupts = <1>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- #iommu-cells = <2>; +- }; +- }; +- +- crmu: crmu { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x66400000 0x100000>; +- +- #include "stingray-clock.dtsi" +- +- otp: otp@1c400 { +- compatible = "brcm,ocotp-v2"; +- reg = <0x0001c400 0x68>; +- brcm,ocotp-size = <2048>; +- status = "okay"; +- }; +- +- cdru: syscon@1d000 { +- compatible = "brcm,sr-cdru", "syscon"; +- reg = <0x0001d000 0x400>; +- }; +- +- gpio_crmu: gpio@24800 { +- compatible = "brcm,iproc-gpio"; +- reg = <0x00024800 0x4c>; +- ngpios = <6>; +- #gpio-cells = <2>; +- gpio-controller; +- }; +- }; +- +- #include "stingray-fs4.dtsi" +- #include "stingray-pcie.dtsi" +- #include "stingray-usb.dtsi" +- +- hsls { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x68900000 0x17700000>; +- +- #include "stingray-pinctrl.dtsi" +- +- mdio_mux_iproc: mdio-mux@20000 { +- compatible = "brcm,mdio-mux-iproc"; +- reg = <0x00020000 0x250>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- mdio@0 { /* PCIe serdes */ +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mdio@3 { /* USB */ +- reg = <0x3>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mdio@10 { /* RGMII */ +- reg = <0x10>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- pwm: pwm@10000 { +- compatible = "brcm,iproc-pwm"; +- reg = <0x00010000 0x1000>; +- clocks = <&crmu_ref25m>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer0: timer@30000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x00030000 0x1000>; +- interrupts = ; +- clocks = <&hsls_25m_div2_clk>, +- <&hsls_25m_div2_clk>, +- <&hsls_div4_clk>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- status = "disabled"; +- }; +- +- timer1: timer@40000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x00040000 0x1000>; +- interrupts = ; +- clocks = <&hsls_25m_div2_clk>, +- <&hsls_25m_div2_clk>, +- <&hsls_div4_clk>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- }; +- +- timer2: timer@50000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x00050000 0x1000>; +- interrupts = ; +- clocks = <&hsls_25m_div2_clk>, +- <&hsls_25m_div2_clk>, +- <&hsls_div4_clk>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- status = "disabled"; +- }; +- +- timer3: timer@60000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x00060000 0x1000>; +- interrupts = ; +- clocks = <&hsls_25m_div2_clk>, +- <&hsls_25m_div2_clk>, +- <&hsls_div4_clk>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- status = "disabled"; +- }; +- +- timer4: timer@70000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x00070000 0x1000>; +- interrupts = ; +- clocks = <&hsls_25m_div2_clk>, +- <&hsls_25m_div2_clk>, +- <&hsls_div4_clk>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- status = "disabled"; +- }; +- +- timer5: timer@80000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x00080000 0x1000>; +- interrupts = ; +- clocks = <&hsls_25m_div2_clk>, +- <&hsls_25m_div2_clk>, +- <&hsls_div4_clk>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- status = "disabled"; +- }; +- +- timer6: timer@90000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x00090000 0x1000>; +- interrupts = ; +- clocks = <&hsls_25m_div2_clk>, +- <&hsls_25m_div2_clk>, +- <&hsls_div4_clk>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- status = "disabled"; +- }; +- +- timer7: timer@a0000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x000a0000 0x1000>; +- interrupts = ; +- clocks = <&hsls_25m_div2_clk>, +- <&hsls_25m_div2_clk>, +- <&hsls_div4_clk>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- status = "disabled"; +- }; +- +- i2c0: i2c@b0000 { +- compatible = "brcm,iproc-i2c"; +- reg = <0x000b0000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clock-frequency = <100000>; +- status = "disabled"; +- }; +- +- wdt0: watchdog@c0000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x000c0000 0x1000>; +- interrupts = ; +- clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>; +- clock-names = "wdog_clk", "apb_pclk"; +- timeout-sec = <60>; +- }; +- +- gpio_hsls: gpio@d0000 { +- compatible = "brcm,iproc-gpio"; +- reg = <0x000d0000 0x864>; +- ngpios = <151>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupts = ; +- gpio-ranges = <&pinmux 0 0 16>, +- <&pinmux 16 71 2>, +- <&pinmux 18 131 8>, +- <&pinmux 26 83 6>, +- <&pinmux 32 123 4>, +- <&pinmux 36 43 24>, +- <&pinmux 60 89 2>, +- <&pinmux 62 73 4>, +- <&pinmux 66 95 28>, +- <&pinmux 94 127 4>, +- <&pinmux 98 139 10>, +- <&pinmux 108 16 27>, +- <&pinmux 135 77 6>, +- <&pinmux 141 67 4>, +- <&pinmux 145 149 6>; +- }; +- +- i2c1: i2c@e0000 { +- compatible = "brcm,iproc-i2c"; +- reg = <0x000e0000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clock-frequency = <100000>; +- status = "disabled"; +- }; +- +- uart0: serial@100000 { +- device_type = "serial"; +- compatible = "snps,dw-apb-uart"; +- reg = <0x00100000 0x1000>; +- reg-shift = <2>; +- clock-frequency = <25000000>; +- interrupt-parent = <&gic>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart1: serial@110000 { +- device_type = "serial"; +- compatible = "snps,dw-apb-uart"; +- reg = <0x00110000 0x1000>; +- reg-shift = <2>; +- clock-frequency = <25000000>; +- interrupt-parent = <&gic>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart2: serial@120000 { +- device_type = "serial"; +- compatible = "snps,dw-apb-uart"; +- reg = <0x00120000 0x1000>; +- reg-shift = <2>; +- clock-frequency = <25000000>; +- interrupt-parent = <&gic>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart3: serial@130000 { +- device_type = "serial"; +- compatible = "snps,dw-apb-uart"; +- reg = <0x00130000 0x1000>; +- reg-shift = <2>; +- clock-frequency = <25000000>; +- interrupt-parent = <&gic>; +- interrupts = ; +- status = "disabled"; +- }; +- +- ssp0: spi@180000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x00180000 0x1000>; +- interrupts = ; +- clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; +- clock-names = "spiclk", "apb_pclk"; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- ssp1: spi@190000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x00190000 0x1000>; +- interrupts = ; +- clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; +- clock-names = "spiclk", "apb_pclk"; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- hwrng: hwrng@220000 { +- compatible = "brcm,iproc-rng200"; +- reg = <0x00220000 0x28>; +- }; +- +- dma0: dma@310000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x00310000 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- clocks = <&hsls_div2_clk>; +- clock-names = "apb_pclk"; +- iommus = <&smmu 0x6000 0x0000>; +- }; +- +- enet: ethernet@340000{ +- compatible = "brcm,amac"; +- reg = <0x00340000 0x1000>; +- reg-names = "amac_base"; +- dma-coherent; +- interrupts = ; +- status= "disabled"; +- }; +- +- nand: nand@360000 { +- compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; +- reg = <0x00360000 0x600>, +- <0x0050a408 0x600>, +- <0x00360f00 0x20>; +- reg-names = "nand", "iproc-idm", "iproc-ext"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- brcm,nand-has-wp; +- status = "disabled"; +- }; +- +- sdio0: sdhci@3f1000 { +- compatible = "brcm,sdhci-iproc"; +- reg = <0x003f1000 0x100>; +- interrupts = ; +- bus-width = <8>; +- clocks = <&sdio0_clk>; +- iommus = <&smmu 0x6002 0x0000>; +- status = "disabled"; +- }; +- +- sdio1: sdhci@3f2000 { +- compatible = "brcm,sdhci-iproc"; +- reg = <0x003f2000 0x100>; +- interrupts = ; +- bus-width = <8>; +- clocks = <&sdio1_clk>; +- iommus = <&smmu 0x6003 0x0000>; +- status = "disabled"; +- }; +- }; +- +- tmons { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x8f100000 0x100>; +- +- tmon: tmon@0 { +- compatible = "brcm,sr-thermal"; +- reg = <0x0 0x40>; +- brcm,tmon-mask = <0x3f>; +- #thermal-sensor-cells = <1>; +- }; +- }; +- +- thermal-zones { +- ihost0_thermal: ihost0-thermal { +- polling-delay-passive = <0>; +- polling-delay = <1000>; +- thermal-sensors = <&tmon 0>; +- trips { +- cpu-crit { +- temperature = <105000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- ihost1_thermal: ihost1-thermal { +- polling-delay-passive = <0>; +- polling-delay = <1000>; +- thermal-sensors = <&tmon 1>; +- trips { +- cpu-crit { +- temperature = <105000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- ihost2_thermal: ihost2-thermal { +- polling-delay-passive = <0>; +- polling-delay = <1000>; +- thermal-sensors = <&tmon 2>; +- trips { +- cpu-crit { +- temperature = <105000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- ihost3_thermal: ihost3-thermal { +- polling-delay-passive = <0>; +- polling-delay = <1000>; +- thermal-sensors = <&tmon 3>; +- trips { +- cpu-crit { +- temperature = <105000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- crmu_thermal: crmu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <1000>; +- thermal-sensors = <&tmon 4>; +- trips { +- cpu-crit { +- temperature = <105000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- nitro_thermal: nitro-thermal { +- polling-delay-passive = <0>; +- polling-delay = <1000>; +- thermal-sensors = <&tmon 5>; +- trips { +- cpu-crit { +- temperature = <105000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- nic-hsls { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x0 0x7fffffff>; +- +- nic_i2c0: i2c@60826100 { +- compatible = "brcm,iproc-nic-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x60826100 0x100>, +- <0x60e00408 0x1000>; +- brcm,ape-hsls-addr-mask = <0x03400000>; +- clock-frequency = <100000>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/cavium/Makefile b/scripts/dtc/include-prefixes/arm64/cavium/Makefile +deleted file mode 100644 +index c178f7e06e18..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/cavium/Makefile ++++ /dev/null +@@ -1,3 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb +-dtb-$(CONFIG_ARCH_THUNDER2) += thunder2-99xx.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/cavium/thunder-88xx.dts b/scripts/dtc/include-prefixes/arm64/cavium/thunder-88xx.dts +deleted file mode 100644 +index 5ec2bfa5f714..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/cavium/thunder-88xx.dts ++++ /dev/null +@@ -1,67 +0,0 @@ +-/* +- * Cavium Thunder DTS file - Thunder board description +- * +- * Copyright (C) 2014, Cavium Inc. +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This library is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This library is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this library; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-/include/ "thunder-88xx.dtsi" +- +-/ { +- model = "Cavium ThunderX CN88XX board"; +- compatible = "cavium,thunder-88xx"; +- +- aliases { +- serial0 = &uaa0; +- serial1 = &uaa1; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x00000000 0x0 0x80000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/cavium/thunder-88xx.dtsi b/scripts/dtc/include-prefixes/arm64/cavium/thunder-88xx.dtsi +deleted file mode 100644 +index e0a71795261b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/cavium/thunder-88xx.dtsi ++++ /dev/null +@@ -1,415 +0,0 @@ +-/* +- * Cavium Thunder DTS file - Thunder SoC description +- * +- * Copyright (C) 2014, Cavium Inc. +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This library is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This library is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this library; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/ { +- compatible = "cavium,thunder-88xx"; +- interrupt-parent = <&gic0>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x000>; +- enable-method = "psci"; +- }; +- cpu@1 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x001>; +- enable-method = "psci"; +- }; +- cpu@2 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x002>; +- enable-method = "psci"; +- }; +- cpu@3 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x003>; +- enable-method = "psci"; +- }; +- cpu@4 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x004>; +- enable-method = "psci"; +- }; +- cpu@5 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x005>; +- enable-method = "psci"; +- }; +- cpu@6 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x006>; +- enable-method = "psci"; +- }; +- cpu@7 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x007>; +- enable-method = "psci"; +- }; +- cpu@8 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x008>; +- enable-method = "psci"; +- }; +- cpu@9 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x009>; +- enable-method = "psci"; +- }; +- cpu@a { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x00a>; +- enable-method = "psci"; +- }; +- cpu@b { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x00b>; +- enable-method = "psci"; +- }; +- cpu@c { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x00c>; +- enable-method = "psci"; +- }; +- cpu@d { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x00d>; +- enable-method = "psci"; +- }; +- cpu@e { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x00e>; +- enable-method = "psci"; +- }; +- cpu@f { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x00f>; +- enable-method = "psci"; +- }; +- cpu@100 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- }; +- cpu@101 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x101>; +- enable-method = "psci"; +- }; +- cpu@102 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x102>; +- enable-method = "psci"; +- }; +- cpu@103 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x103>; +- enable-method = "psci"; +- }; +- cpu@104 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x104>; +- enable-method = "psci"; +- }; +- cpu@105 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x105>; +- enable-method = "psci"; +- }; +- cpu@106 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x106>; +- enable-method = "psci"; +- }; +- cpu@107 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x107>; +- enable-method = "psci"; +- }; +- cpu@108 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x108>; +- enable-method = "psci"; +- }; +- cpu@109 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x109>; +- enable-method = "psci"; +- }; +- cpu@10a { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x10a>; +- enable-method = "psci"; +- }; +- cpu@10b { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x10b>; +- enable-method = "psci"; +- }; +- cpu@10c { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x10c>; +- enable-method = "psci"; +- }; +- cpu@10d { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x10d>; +- enable-method = "psci"; +- }; +- cpu@10e { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x10e>; +- enable-method = "psci"; +- }; +- cpu@10f { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x10f>; +- enable-method = "psci"; +- }; +- cpu@200 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x200>; +- enable-method = "psci"; +- }; +- cpu@201 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x201>; +- enable-method = "psci"; +- }; +- cpu@202 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x202>; +- enable-method = "psci"; +- }; +- cpu@203 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x203>; +- enable-method = "psci"; +- }; +- cpu@204 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x204>; +- enable-method = "psci"; +- }; +- cpu@205 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x205>; +- enable-method = "psci"; +- }; +- cpu@206 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x206>; +- enable-method = "psci"; +- }; +- cpu@207 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x207>; +- enable-method = "psci"; +- }; +- cpu@208 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x208>; +- enable-method = "psci"; +- }; +- cpu@209 { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x209>; +- enable-method = "psci"; +- }; +- cpu@20a { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x20a>; +- enable-method = "psci"; +- }; +- cpu@20b { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x20b>; +- enable-method = "psci"; +- }; +- cpu@20c { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x20c>; +- enable-method = "psci"; +- }; +- cpu@20d { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x20d>; +- enable-method = "psci"; +- }; +- cpu@20e { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x20e>; +- enable-method = "psci"; +- }; +- cpu@20f { +- device_type = "cpu"; +- compatible = "cavium,thunder"; +- reg = <0x0 0x20f>; +- enable-method = "psci"; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = <1 13 4>, +- <1 14 4>, +- <1 11 4>, +- <1 10 4>; +- }; +- +- pmu { +- compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3"; +- interrupts = <1 7 4>; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- refclk50mhz: refclk50mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- clock-output-names = "refclk50mhz"; +- }; +- +- gic0: interrupt-controller@8010,00000000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- interrupt-controller; +- reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */ +- <0x8010 0x80000000 0x0 0x600000>; /* GICR */ +- interrupts = <1 9 0xf04>; +- +- its: gic-its@8010,00020000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- reg = <0x8010 0x20000 0x0 0x200000>; +- }; +- }; +- +- uaa0: serial@87e0,24000000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x87e0 0x24000000 0x0 0x1000>; +- interrupts = <1 21 4>; +- clocks = <&refclk50mhz>; +- clock-names = "apb_pclk"; +- }; +- +- uaa1: serial@87e0,25000000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x87e0 0x25000000 0x0 0x1000>; +- interrupts = <1 22 4>; +- clocks = <&refclk50mhz>; +- clock-names = "apb_pclk"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/cavium/thunder2-99xx.dts b/scripts/dtc/include-prefixes/arm64/cavium/thunder2-99xx.dts +deleted file mode 100644 +index d005e1e79c3d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/cavium/thunder2-99xx.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * dts file for Cavium ThunderX2 CN99XX Evaluation Platform +- * +- * Copyright (c) 2017 Cavium Inc. +- * Copyright (c) 2013-2016 Broadcom +- */ +- +-/dts-v1/; +- +-#include "thunder2-99xx.dtsi" +- +-/ { +- model = "Cavium ThunderX2 CN99XX"; +- compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ +- <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/cavium/thunder2-99xx.dtsi b/scripts/dtc/include-prefixes/arm64/cavium/thunder2-99xx.dtsi +deleted file mode 100644 +index dfb41705a9a9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/cavium/thunder2-99xx.dtsi ++++ /dev/null +@@ -1,145 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * dtsi file for Cavium ThunderX2 CN99XX processor +- * +- * Copyright (c) 2017 Cavium Inc. +- * Copyright (c) 2013-2016 Broadcom +- * Author: Zi Shen Lim +- */ +- +-#include +- +-/ { +- model = "Cavium ThunderX2 CN99XX"; +- compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- /* just 4 cpus now, 128 needed in full config */ +- cpus { +- #address-cells = <0x2>; +- #size-cells = <0x0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "cavium,thunder2", "brcm,vulcan"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "cavium,thunder2", "brcm,vulcan"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- }; +- +- cpu@2 { +- device_type = "cpu"; +- compatible = "cavium,thunder2", "brcm,vulcan"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- }; +- +- cpu@3 { +- device_type = "cpu"; +- compatible = "cavium,thunder2", "brcm,vulcan"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- gic: interrupt-controller@400080000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- interrupt-controller; +- #redistributor-regions = <1>; +- reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ +- <0x04 0x01000000 0x0 0x1000000>; /* GICR */ +- interrupts = ; +- +- gicits: gic-its@40010000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; +- interrupts = ; /* PMU overflow */ +- }; +- +- clk125mhz: uart_clk125mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- clock-output-names = "clk125mhz"; +- }; +- +- pcie@30000000 { +- compatible = "pci-host-ecam-generic"; +- device_type = "pci"; +- #interrupt-cells = <1>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- /* ECAM at 0x3000_0000 - 0x4000_0000 */ +- reg = <0x0 0x30000000 0x0 0x10000000>; +- reg-names = "PCI ECAM"; +- +- /* +- * PCI ranges: +- * IO no supported +- * MEM 0x4000_0000 - 0x6000_0000 +- * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 +- */ +- ranges = +- <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 +- 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; +- bus-range = <0 0xff>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = +- /* addr pin ic icaddr icintr */ +- <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH +- 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH +- 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH +- 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; +- msi-parent = <&gicits>; +- dma-coherent; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- uart0: serial@402020000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x04 0x02020000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = ; +- clocks = <&clk125mhz>; +- clock-names = "apb_pclk"; +- }; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/exynos/Makefile b/scripts/dtc/include-prefixes/arm64/exynos/Makefile +deleted file mode 100644 +index e0a2facde6a2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/exynos/Makefile ++++ /dev/null +@@ -1,5 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_EXYNOS) += \ +- exynos5433-tm2.dtb \ +- exynos5433-tm2e.dtb \ +- exynos7-espresso.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/exynos/exynos5433-bus.dtsi b/scripts/dtc/include-prefixes/arm64/exynos/exynos5433-bus.dtsi +deleted file mode 100644 +index 8997f8f2b96c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/exynos/exynos5433-bus.dtsi ++++ /dev/null +@@ -1,194 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos5433 SoC Memory interface and AMBA bus device tree source +- * +- * Copyright (c) 2016 Samsung Electronics Co., Ltd. +- * Chanwoo Choi +- */ +- +-&soc { +- bus_g2d_400: bus0 { +- compatible = "samsung,exynos-bus"; +- clocks = <&cmu_top CLK_ACLK_G2D_400>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_g2d_400_opp_table>; +- status = "disabled"; +- }; +- +- bus_g2d_266: bus1 { +- compatible = "samsung,exynos-bus"; +- clocks = <&cmu_top CLK_ACLK_G2D_266>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_g2d_266_opp_table>; +- status = "disabled"; +- }; +- +- bus_gscl: bus2 { +- compatible = "samsung,exynos-bus"; +- clocks = <&cmu_top CLK_ACLK_GSCL_333>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_gscl_opp_table>; +- status = "disabled"; +- }; +- +- bus_hevc: bus3 { +- compatible = "samsung,exynos-bus"; +- clocks = <&cmu_top CLK_ACLK_HEVC_400>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_hevc_opp_table>; +- status = "disabled"; +- }; +- +- bus_jpeg: bus4 { +- compatible = "samsung,exynos-bus"; +- clocks = <&cmu_top CLK_SCLK_JPEG_MSCL>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_g2d_400_opp_table>; +- status = "disabled"; +- }; +- +- bus_mfc: bus5 { +- compatible = "samsung,exynos-bus"; +- clocks = <&cmu_top CLK_ACLK_MFC_400>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_g2d_400_opp_table>; +- status = "disabled"; +- }; +- +- bus_mscl: bus6 { +- compatible = "samsung,exynos-bus"; +- clocks = <&cmu_top CLK_ACLK_MSCL_400>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_g2d_400_opp_table>; +- status = "disabled"; +- }; +- +- bus_noc0: bus7 { +- compatible = "samsung,exynos-bus"; +- clocks = <&cmu_top CLK_ACLK_BUS0_400>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_hevc_opp_table>; +- status = "disabled"; +- }; +- +- bus_noc1: bus8 { +- compatible = "samsung,exynos-bus"; +- clocks = <&cmu_top CLK_ACLK_BUS1_400>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_hevc_opp_table>; +- status = "disabled"; +- }; +- +- bus_noc2: bus9 { +- compatible = "samsung,exynos-bus"; +- clocks = <&cmu_mif CLK_ACLK_BUS2_400>; +- clock-names = "bus"; +- operating-points-v2 = <&bus_noc2_opp_table>; +- status = "disabled"; +- }; +- +- bus_g2d_400_opp_table: opp-table2 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <1075000>; +- }; +- opp-267000000 { +- opp-hz = /bits/ 64 <267000000>; +- opp-microvolt = <1000000>; +- }; +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- opp-microvolt = <975000>; +- }; +- opp-160000000 { +- opp-hz = /bits/ 64 <160000000>; +- opp-microvolt = <962500>; +- }; +- opp-134000000 { +- opp-hz = /bits/ 64 <134000000>; +- opp-microvolt = <950000>; +- }; +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- opp-microvolt = <937500>; +- }; +- }; +- +- bus_g2d_266_opp_table: opp-table3 { +- compatible = "operating-points-v2"; +- +- opp-267000000 { +- opp-hz = /bits/ 64 <267000000>; +- }; +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- }; +- opp-160000000 { +- opp-hz = /bits/ 64 <160000000>; +- }; +- opp-134000000 { +- opp-hz = /bits/ 64 <134000000>; +- }; +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- }; +- }; +- +- bus_gscl_opp_table: opp-table4 { +- compatible = "operating-points-v2"; +- +- opp-333000000 { +- opp-hz = /bits/ 64 <333000000>; +- }; +- opp-222000000 { +- opp-hz = /bits/ 64 <222000000>; +- }; +- opp-166500000 { +- opp-hz = /bits/ 64 <166500000>; +- }; +- }; +- +- bus_hevc_opp_table: opp-table5 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- }; +- opp-267000000 { +- opp-hz = /bits/ 64 <267000000>; +- }; +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- }; +- opp-160000000 { +- opp-hz = /bits/ 64 <160000000>; +- }; +- opp-134000000 { +- opp-hz = /bits/ 64 <134000000>; +- }; +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- }; +- }; +- +- bus_noc2_opp_table: opp-table6 { +- compatible = "operating-points-v2"; +- +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- }; +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- }; +- opp-134000000 { +- opp-hz = /bits/ 64 <134000000>; +- }; +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/exynos/exynos5433-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm64/exynos/exynos5433-pinctrl.dtsi +deleted file mode 100644 +index 32a6518517e5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/exynos/exynos5433-pinctrl.dtsi ++++ /dev/null +@@ -1,790 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source +- * +- * Copyright (c) 2016 Samsung Electronics Co., Ltd. +- * Chanwoo Choi +- * +- * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device +- * tree nodes are listed in this file. +- */ +- +-#include +- +-#define PIN(_func, _pin, _pull, _drv) \ +- _pin { \ +- samsung,pins = #_pin; \ +- samsung,pin-function = ; \ +- samsung,pin-pud = ; \ +- samsung,pin-drv = ; \ +- } +- +-&pinctrl_alive { +- gpa0: gpa0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- #interrupt-cells = <2>; +- }; +- +- gpa1: gpa1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- #interrupt-cells = <2>; +- }; +- +- gpa2: gpa2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpa3: gpa3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf1: gpf1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf2: gpf2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf3: gpf3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf4: gpf4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf5: gpf5 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +-}; +- +-&pinctrl_aud { +- gpz0: gpz0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpz1: gpz1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- i2s0_bus: i2s0-bus { +- samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3", +- "gpz0-4", "gpz0-5", "gpz0-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pcm0_bus: pcm0-bus { +- samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart_aud_bus: uart-aud-bus { +- samsung,pins = "gpz1-3", "gpz1-2", "gpz1-1", "gpz1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_cpif { +- gpv6: gpv6 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +-}; +- +-&pinctrl_ese { +- gpj2: gpj2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +-}; +- +-&pinctrl_finger { +- gpd5: gpd5 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- spi2_bus: spi2-bus { +- samsung,pins = "gpd5-0", "gpd5-2", "gpd5-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hs_i2c6_bus: hs-i2c6-bus { +- samsung,pins = "gpd5-3", "gpd5-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_fsys { +- gph1: gph1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpr4: gpr4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpr0: gpr0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpr1: gpr1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpr2: gpr2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpr3: gpr3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- sd0_clk: sd0-clk { +- samsung,pins = "gpr0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_cmd: sd0-cmd { +- samsung,pins = "gpr0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_rdqs: sd0-rdqs { +- samsung,pins = "gpr0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_qrdy: sd0-qrdy { +- samsung,pins = "gpr0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus1: sd0-bus-width1 { +- samsung,pins = "gpr1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus4: sd0-bus-width4 { +- samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus8: sd0-bus-width8 { +- samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_clk: sd1-clk { +- samsung,pins = "gpr2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_cmd: sd1-cmd { +- samsung,pins = "gpr2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus1: sd1-bus-width1 { +- samsung,pins = "gpr3-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus4: sd1-bus-width4 { +- samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus8: sd1-bus-width8 { +- samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pcie_bus: pcie_bus { +- samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- sd2_clk: sd2-clk { +- samsung,pins = "gpr4-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cmd: sd2-cmd { +- samsung,pins = "gpr4-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cd: sd2-cd { +- samsung,pins = "gpr4-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus1: sd2-bus-width1 { +- samsung,pins = "gpr4-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus4: sd2-bus-width4 { +- samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_clk_output: sd2-clk-output { +- samsung,pins = "gpr4-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cmd_output: sd2-cmd-output { +- samsung,pins = "gpr4-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_imem { +- gpf0: gpf0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +-}; +- +-&pinctrl_nfc { +- gpj0: gpj0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- hs_i2c4_bus: hs-i2c4-bus { +- samsung,pins = "gpj0-1", "gpj0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_peric { +- gpv7: gpv7 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpb0: gpb0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc0: gpc0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc1: gpc1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc2: gpc2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc3: gpc3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg0: gpg0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd0: gpd0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd1: gpd1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd2: gpd2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd4: gpd4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd8: gpd8 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd6: gpd6 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd7: gpd7 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg1: gpg1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg2: gpg2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg3: gpg3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- hs_i2c8_bus: hs-i2c8-bus { +- samsung,pins = "gpb0-1", "gpb0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hs_i2c9_bus: hs-i2c9-bus { +- samsung,pins = "gpb0-3", "gpb0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- i2s1_bus: i2s1-bus { +- samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", +- "gpd4-3", "gpd4-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pcm1_bus: pcm1-bus { +- samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", +- "gpd4-3", "gpd4-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spdif_bus: spdif-bus { +- samsung,pins = "gpd4-3", "gpd4-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- fimc_is_spi_pin0: fimc-is-spi-pin0 { +- samsung,pins = "gpc3-3", "gpc3-2", "gpc3-1", "gpc3-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- fimc_is_spi_pin1: fimc-is-spi-pin1 { +- samsung,pins = "gpc3-7", "gpc3-6", "gpc3-5", "gpc3-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart0_bus: uart0-bus { +- samsung,pins = "gpd0-3", "gpd0-2", "gpd0-1", "gpd0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- hs_i2c2_bus: hs-i2c2-bus { +- samsung,pins = "gpd0-3", "gpd0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart2_bus: uart2-bus { +- samsung,pins = "gpd1-5", "gpd1-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- uart1_bus: uart1-bus { +- samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- }; +- +- hs_i2c3_bus: hs-i2c3-bus { +- samsung,pins = "gpd1-3", "gpd1-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hs_i2c0_bus: hs-i2c0-bus { +- samsung,pins = "gpd2-1", "gpd2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hs_i2c1_bus: hs-i2c1-bus { +- samsung,pins = "gpd2-3", "gpd2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm0_out: pwm0-out { +- samsung,pins = "gpd2-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm1_out: pwm1-out { +- samsung,pins = "gpd2-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm2_out: pwm2-out { +- samsung,pins = "gpd2-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm3_out: pwm3-out { +- samsung,pins = "gpd2-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi1_bus: spi1-bus { +- samsung,pins = "gpd6-2", "gpd6-4", "gpd6-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hs_i2c7_bus: hs-i2c7-bus { +- samsung,pins = "gpd2-7", "gpd2-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi0_bus: spi0-bus { +- samsung,pins = "gpd8-0", "gpd6-0", "gpd6-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hs_i2c10_bus: hs-i2c10-bus { +- samsung,pins = "gpg3-1", "gpg3-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hs_i2c11_bus: hs-i2c11-bus { +- samsung,pins = "gpg3-3", "gpg3-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi3_bus: spi3-bus { +- samsung,pins = "gpg3-4", "gpg3-6", "gpg3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi4_bus: spi4-bus { +- samsung,pins = "gpv7-1", "gpv7-3", "gpv7-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- fimc_is_uart: fimc-is-uart { +- samsung,pins = "gpc1-1", "gpc0-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- fimc_is_ch0_i2c: fimc-is-ch0_i2c { +- samsung,pins = "gpc2-1", "gpc2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- fimc_is_ch0_mclk: fimc-is-ch0_mclk { +- samsung,pins = "gpd7-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- fimc_is_ch1_i2c: fimc-is-ch1-i2c { +- samsung,pins = "gpc2-3", "gpc2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- fimc_is_ch1_mclk: fimc-is-ch1-mclk { +- samsung,pins = "gpd7-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- fimc_is_ch2_i2c: fimc-is-ch2-i2c { +- samsung,pins = "gpc2-5", "gpc2-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- fimc_is_ch2_mclk: fimc-is-ch2-mclk { +- samsung,pins = "gpd7-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_touch { +- gpj1: gpj1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- hs_i2c5_bus: hs-i2c5-bus { +- samsung,pins = "gpj1-1", "gpj1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/exynos/exynos5433-tm2-common.dtsi b/scripts/dtc/include-prefixes/arm64/exynos/exynos5433-tm2-common.dtsi +deleted file mode 100644 +index cbcc01a66aab..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/exynos/exynos5433-tm2-common.dtsi ++++ /dev/null +@@ -1,1355 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung Exynos5433 TM2 board device tree source +- * +- * Copyright (c) 2016 Samsung Electronics Co., Ltd. +- * +- * Common device tree source file for Samsung's TM2 and TM2E boards +- * which are based on Samsung Exynos5433 SoC. +- */ +- +-/dts-v1/; +-#include "exynos5433.dtsi" +-#include +-#include +-#include +-#include +-#include +- +-/ { +- aliases { +- gsc0 = &gsc_0; +- gsc1 = &gsc_1; +- gsc2 = &gsc_2; +- pinctrl0 = &pinctrl_alive; +- pinctrl1 = &pinctrl_aud; +- pinctrl2 = &pinctrl_cpif; +- pinctrl3 = &pinctrl_ese; +- pinctrl4 = &pinctrl_finger; +- pinctrl5 = &pinctrl_fsys; +- pinctrl6 = &pinctrl_imem; +- pinctrl7 = &pinctrl_nfc; +- pinctrl8 = &pinctrl_peric; +- pinctrl9 = &pinctrl_touch; +- serial0 = &serial_0; +- serial1 = &serial_1; +- serial2 = &serial_2; +- serial3 = &serial_3; +- spi0 = &spi_0; +- spi1 = &spi_1; +- spi2 = &spi_2; +- spi3 = &spi_3; +- spi4 = &spi_4; +- mshc0 = &mshc_0; +- mshc2 = &mshc_2; +- }; +- +- chosen { +- stdout-path = &serial_1; +- }; +- +- memory@20000000 { +- device_type = "memory"; +- reg = <0x0 0x20000000 0x0 0xc0000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power-key { +- gpios = <&gpa2 7 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "power key"; +- debounce-interval = <10>; +- }; +- +- volume-up-key { +- gpios = <&gpa2 0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "volume-up key"; +- debounce-interval = <10>; +- }; +- +- volume-down-key { +- gpios = <&gpa2 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "volume-down key"; +- debounce-interval = <10>; +- }; +- +- homepage-key { +- gpios = <&gpa0 3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "homepage key"; +- debounce-interval = <10>; +- }; +- }; +- +- i2c_max98504: i2c-gpio-0 { +- compatible = "i2c-gpio"; +- sda-gpios = <&gpd0 1 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&gpd0 0 GPIO_ACTIVE_HIGH>; +- i2c-gpio,delay-us = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- max98504: amplifier@31 { +- compatible = "maxim,max98504"; +- reg = <0x31>; +- maxim,rx-path = <1>; +- maxim,tx-path = <1>; +- maxim,tx-channel-mask = <3>; +- maxim,tx-channel-source = <2>; +- }; +- }; +- +- irda_regulator: irda-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpr3 3 GPIO_ACTIVE_HIGH>; +- regulator-name = "irda_regulator"; +- }; +- +- sound { +- compatible = "samsung,tm2-audio"; +- audio-codec = <&wm5110>, <&hdmi>; +- i2s-controller = <&i2s0 0>, <&i2s1 0>; +- audio-amplifier = <&max98504>; +- mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>; +- model = "wm5110"; +- samsung,audio-routing = +- /* Headphone */ +- "HP", "HPOUT1L", +- "HP", "HPOUT1R", +- +- /* Speaker */ +- "SPK", "SPKOUT", +- "SPKOUT", "HPOUT2L", +- "SPKOUT", "HPOUT2R", +- +- /* Receiver */ +- "RCV", "HPOUT3L", +- "RCV", "HPOUT3R"; +- status = "okay"; +- }; +-}; +- +-&adc { +- vdd-supply = <&ldo3_reg>; +- status = "okay"; +- +- thermistor-ap { +- compatible = "murata,ncp03wf104"; +- pullup-uv = <1800000>; +- pullup-ohm = <100000>; +- pulldown-ohm = <0>; +- io-channels = <&adc 0>; +- }; +- +- thermistor-battery { +- compatible = "murata,ncp03wf104"; +- pullup-uv = <1800000>; +- pullup-ohm = <100000>; +- pulldown-ohm = <0>; +- io-channels = <&adc 1>; +- #thermal-sensor-cells = <0>; +- }; +- +- thermistor-charger { +- compatible = "murata,ncp03wf104"; +- pullup-uv = <1800000>; +- pullup-ohm = <100000>; +- pulldown-ohm = <0>; +- io-channels = <&adc 2>; +- }; +-}; +- +-&bus_g2d_400 { +- devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>; +- vdd-supply = <&buck4_reg>; +- exynos,saturation-ratio = <10>; +- status = "okay"; +-}; +- +-&bus_g2d_266 { +- devfreq = <&bus_g2d_400>; +- status = "okay"; +-}; +- +-&bus_gscl { +- devfreq = <&bus_g2d_400>; +- status = "okay"; +-}; +- +-&bus_hevc { +- devfreq = <&bus_g2d_400>; +- status = "okay"; +-}; +- +-&bus_jpeg { +- devfreq = <&bus_g2d_400>; +- status = "okay"; +-}; +- +-&bus_mfc { +- devfreq = <&bus_g2d_400>; +- status = "okay"; +-}; +- +-&bus_mscl { +- devfreq = <&bus_g2d_400>; +- status = "okay"; +-}; +- +-&bus_noc0 { +- devfreq = <&bus_g2d_400>; +- status = "okay"; +-}; +- +-&bus_noc1 { +- devfreq = <&bus_g2d_400>; +- status = "okay"; +-}; +- +-&bus_noc2 { +- devfreq = <&bus_g2d_400>; +- status = "okay"; +-}; +- +-&cmu_aud { +- assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>, +- <&cmu_aud CLK_MOUT_SCLK_AUD_I2S>, +- <&cmu_aud CLK_MOUT_SCLK_AUD_PCM>, +- <&cmu_top CLK_MOUT_AUD_PLL>, +- <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, +- <&cmu_top CLK_MOUT_SCLK_AUDIO0>, +- <&cmu_top CLK_MOUT_SCLK_AUDIO1>, +- <&cmu_top CLK_MOUT_SCLK_SPDIF>, +- +- <&cmu_aud CLK_DIV_AUD_CA5>, +- <&cmu_aud CLK_DIV_ACLK_AUD>, +- <&cmu_aud CLK_DIV_PCLK_DBG_AUD>, +- <&cmu_aud CLK_DIV_SCLK_AUD_I2S>, +- <&cmu_aud CLK_DIV_SCLK_AUD_PCM>, +- <&cmu_aud CLK_DIV_SCLK_AUD_SLIMBUS>, +- <&cmu_aud CLK_DIV_SCLK_AUD_UART>, +- <&cmu_top CLK_DIV_SCLK_AUDIO0>, +- <&cmu_top CLK_DIV_SCLK_AUDIO1>, +- <&cmu_top CLK_DIV_SCLK_PCM1>, +- <&cmu_top CLK_DIV_SCLK_I2S1>; +- +- assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>, +- <&cmu_aud CLK_MOUT_AUD_PLL_USER>, +- <&cmu_aud CLK_MOUT_AUD_PLL_USER>, +- <&cmu_top CLK_FOUT_AUD_PLL>, +- <&cmu_top CLK_MOUT_AUD_PLL>, +- <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, +- <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, +- <&cmu_top CLK_SCLK_AUDIO0>; +- +- assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, +- <196608001>, <65536001>, <32768001>, <49152001>, +- <2048001>, <24576001>, <196608001>, +- <24576001>, <98304001>, <2048001>, <49152001>; +-}; +- +-&cmu_fsys { +- assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>, +- <&cmu_top CLK_MOUT_SCLK_USBHOST30>, +- <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>, +- <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>, +- <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>, +- <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>, +- <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>, +- <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>, +- <&cmu_top CLK_DIV_SCLK_USBDRD30>, +- <&cmu_top CLK_DIV_SCLK_USBHOST30>; +- assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>, +- <&cmu_top CLK_MOUT_BUS_PLL_USER>, +- <&cmu_top CLK_SCLK_USBDRD30_FSYS>, +- <&cmu_top CLK_SCLK_USBHOST30_FSYS>, +- <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>, +- <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>, +- <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>, +- <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>; +- assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, +- <66700000>, <66700000>; +-}; +- +-&cmu_gscl { +- assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>, +- <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>; +- assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>, +- <&cmu_top CLK_ACLK_GSCL_333>; +-}; +- +-&cmu_mfc { +- assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>; +- assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>; +-}; +- +-&cmu_mif { +- assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>; +- assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>; +- assigned-clock-rates = <0>, <333000000>; +-}; +- +-&cmu_mscl { +- assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>, +- <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>, +- <&cmu_mscl CLK_MOUT_SCLK_JPEG>, +- <&cmu_top CLK_MOUT_SCLK_JPEG_A>; +- assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>, +- <&cmu_top CLK_SCLK_JPEG_MSCL>, +- <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>, +- <&cmu_top CLK_MOUT_BUS_PLL_USER>; +-}; +- +-&cmu_top { +- assigned-clocks = <&cmu_top CLK_FOUT_AUD_PLL>; +- assigned-clock-rates = <196608001>; +-}; +- +-&cpu0 { +- cpu-supply = <&buck3_reg>; +-}; +- +-&cpu4 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&decon { +- status = "okay"; +-}; +- +-&decon_tv { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- tv_to_hdmi: endpoint { +- remote-endpoint = <&hdmi_to_tv>; +- }; +- }; +- }; +-}; +- +-&dsi { +- status = "okay"; +- vddcore-supply = <&ldo6_reg>; +- vddio-supply = <&ldo7_reg>; +- samsung,burst-clock-frequency = <512000000>; +- samsung,esc-clock-frequency = <16000000>; +- samsung,pll-clock-frequency = <24000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&te_irq>; +-}; +- +-&gpu { +- mali-supply = <&buck6_reg>; +- status = "okay"; +-}; +- +-&hdmi { +- hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- vdd-supply = <&ldo6_reg>; +- vdd_osc-supply = <&ldo7_reg>; +- vdd_pll-supply = <&ldo6_reg>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- hdmi_to_tv: endpoint { +- remote-endpoint = <&tv_to_hdmi>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- hdmi_to_mhl: endpoint { +- remote-endpoint = <&mhl_to_hdmi>; +- }; +- }; +- }; +-}; +- +-&hsi2c_0 { +- status = "okay"; +- clock-frequency = <2500000>; +- +- pmic@66 { +- compatible = "samsung,s2mps13-pmic"; +- interrupt-parent = <&gpa0>; +- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x66>; +- samsung,s2mps11-wrstbi-ground; +- wakeup-source; +- +- s2mps13_osc: clocks { +- compatible = "samsung,s2mps13-clk"; +- #clock-cells = <1>; +- clock-output-names = "s2mps13_ap", "s2mps13_cp", +- "s2mps13_bt"; +- }; +- +- regulators { +- ldo1_reg: LDO1 { +- regulator-name = "VDD_ALIVE_0.9V_AP"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-always-on; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "VDDQ_MMC2_2.8V_AP"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "VDD1_E_1.8V_AP"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "VDD10_MIF_PLL_1.0V_AP"; +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "VDD10_DPLL_1.0V_AP"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "VDD10_MIPI2L_1.0V_AP"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "VDD18_MIPI2L_1.8V_AP"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "VDD18_LLI_1.8V_AP"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "VDD18_ABB_ETC_1.8V_AP"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "VDD33_USB30_3.0V_AP"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "VDD_INT_M_1.0V_AP"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "VDD_KFC_M_1.1V_AP"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "VDD_G3D_M_0.95V_AP"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <950000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "VDDQ_M1_LDO_1.2V_AP"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo15_reg: LDO15 { +- regulator-name = "VDDQ_M2_LDO_1.2V_AP"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- ldo16_reg: LDO16 { +- regulator-name = "VDDQ_EFUSE"; +- regulator-min-microvolt = <1400000>; +- regulator-max-microvolt = <3400000>; +- regulator-always-on; +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "V_TFLASH_2.8V_AP"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo18_reg: LDO18 { +- regulator-name = "V_CODEC_1.8V_AP"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo19_reg: LDO19 { +- regulator-name = "VDDA_1.8V_COMP"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo20_reg: LDO20 { +- regulator-name = "VCC_2.8V_AP"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- ldo21_reg: LDO21 { +- regulator-name = "VT_CAM_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo22_reg: LDO22 { +- regulator-name = "CAM_IO_1.8V_AP"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo23_reg: LDO23 { +- regulator-name = "CAM_SEN_CORE_1.05V_AP"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- ldo24_reg: LDO24 { +- regulator-name = "VT_CAM_1.2V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- ldo25_reg: LDO25 { +- regulator-name = "UNUSED_LDO25"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo26_reg: LDO26 { +- regulator-name = "CAM_AF_2.8V_AP"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo27_reg: LDO27 { +- regulator-name = "VCC_3.0V_LCD_AP"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- ldo28_reg: LDO28 { +- regulator-name = "VCC_1.8V_LCD_AP"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo29_reg: LDO29 { +- regulator-name = "VT_CAM_2.8V"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- ldo30_reg: LDO30 { +- regulator-name = "TSP_AVDD_3.3V_AP"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo31_reg: LDO31 { +- /* +- * LDO31 differs from target to target, +- * its definition is in the .dts +- */ +- }; +- +- ldo32_reg: LDO32 { +- regulator-name = "VTOUCH_1.8V_AP"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo33_reg: LDO33 { +- regulator-name = "VTOUCH_LED_3.3V"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <3300000>; +- regulator-ramp-delay = <12500>; +- }; +- +- ldo34_reg: LDO34 { +- regulator-name = "VCC_1.8V_MHL_AP"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <2100000>; +- }; +- +- ldo35_reg: LDO35 { +- regulator-name = "OIS_VM_2.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo36_reg: LDO36 { +- regulator-name = "VSIL_1.0V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- ldo37_reg: LDO37 { +- regulator-name = "VF_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo38_reg: LDO38 { +- /* +- * LDO38 differs from target to target, +- * its definition is in the .dts +- */ +- }; +- +- ldo39_reg: LDO39 { +- regulator-name = "V_HRM_1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo40_reg: LDO40 { +- regulator-name = "V_HRM_3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "VDD_MIF_0.9V_AP"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "VDD_EGL_1.0V_AP"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "VDD_KFC_1.0V_AP"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "VDD_INT_0.95V_AP"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "VDD_DISP_CAM0_0.9V_AP"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck6_reg: BUCK6 { +- regulator-name = "VDD_G3D_0.9V_AP"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- buck7_reg: BUCK7 { +- regulator-name = "VDD_MEM1_1.2V_AP"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- buck8_reg: BUCK8 { +- regulator-name = "VDD_LLDO_1.35V_AP"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- buck9_reg: BUCK9 { +- regulator-name = "VDD_MLDO_2.0V_AP"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- buck10_reg: BUCK10 { +- regulator-name = "vdd_mem2"; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&hsi2c_4 { +- status = "okay"; +- +- s3fwrn5: nfc@27 { +- compatible = "samsung,s3fwrn5-i2c"; +- reg = <0x27>; +- interrupt-parent = <&gpa1>; +- interrupts = <3 IRQ_TYPE_EDGE_RISING>; +- en-gpios = <&gpf1 4 GPIO_ACTIVE_HIGH>; +- wake-gpios = <&gpj0 2 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&hsi2c_5 { +- status = "okay"; +- +- stmfts: touchscreen@49 { +- compatible = "st,stmfts"; +- reg = <0x49>; +- interrupt-parent = <&gpa1>; +- interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +- avdd-supply = <&ldo30_reg>; +- vdd-supply = <&ldo31_reg>; +- }; +-}; +- +-&hsi2c_7 { +- status = "okay"; +- clock-frequency = <1000000>; +- +- bridge@39 { +- reg = <0x39>; +- compatible = "sil,sii8620"; +- cvcc10-supply = <&ldo36_reg>; +- iovcc18-supply = <&ldo34_reg>; +- interrupt-parent = <&gpf0>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; +- reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>; +- clocks = <&pmu_system_controller 0>; +- clock-names = "xtal"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- mhl_to_hdmi: endpoint { +- remote-endpoint = <&hdmi_to_mhl>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- mhl_to_musb_con: endpoint { +- remote-endpoint = <&musb_con_to_mhl>; +- }; +- }; +- }; +- }; +-}; +- +-&hsi2c_8 { +- status = "okay"; +- +- pmic@66 { +- compatible = "maxim,max77843"; +- interrupt-parent = <&gpa1>; +- interrupts = <5 IRQ_TYPE_EDGE_FALLING>; +- reg = <0x66>; +- +- muic: max77843-muic { +- compatible = "maxim,max77843-muic"; +- +- musb_con: musb-connector { +- compatible = "samsung,usb-connector-11pin", +- "usb-b-connector"; +- label = "micro-USB"; +- type = "micro"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@3 { +- reg = <3>; +- musb_con_to_mhl: endpoint { +- remote-endpoint = <&mhl_to_musb_con>; +- }; +- }; +- }; +- }; +- +- ports { +- port { +- muic_to_usb: endpoint { +- remote-endpoint = <&usb_to_muic>; +- }; +- }; +- }; +- }; +- +- regulators { +- compatible = "maxim,max77843-regulator"; +- safeout1_reg: SAFEOUT1 { +- regulator-name = "SAFEOUT1"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <4950000>; +- }; +- +- safeout2_reg: SAFEOUT2 { +- regulator-name = "SAFEOUT2"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <4950000>; +- }; +- +- charger_reg: CHARGER { +- regulator-name = "CHARGER"; +- regulator-min-microamp = <100000>; +- regulator-max-microamp = <3150000>; +- }; +- }; +- +- haptic: max77843-haptic { +- compatible = "maxim,max77843-haptic"; +- haptic-supply = <&ldo38_reg>; +- pwms = <&pwm 0 33670 0>; +- pwm-names = "haptic"; +- }; +- }; +-}; +- +-&hsi2c_11 { +- status = "okay"; +-}; +- +-&i2s0 { +- status = "okay"; +-}; +- +-&i2s1 { +- assigned-clocks = <&i2s1 CLK_I2S_RCLK_SRC>; +- assigned-clock-parents = <&cmu_peric CLK_SCLK_I2S1>; +- status = "okay"; +-}; +- +-&mshc_0 { +- status = "okay"; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- cap-mmc-highspeed; +- non-removable; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <0 4>; +- samsung,dw-mshc-ddr-timing = <0 2>; +- samsung,dw-mshc-hs400-timing = <0 3>; +- samsung,read-strobe-delay = <90>; +- fifo-depth = <0x80>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4 +- &sd0_bus8 &sd0_rdqs>; +- bus-width = <8>; +- assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>; +- assigned-clock-rates = <800000000>; +-}; +- +-&mshc_2 { +- status = "okay"; +- cap-sd-highspeed; +- disable-wp; +- cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>; +- card-detect-delay = <200>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <0 4>; +- samsung,dw-mshc-ddr-timing = <0 2>; +- fifo-depth = <0x80>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>; +- bus-width = <4>; +-}; +- +-&pcie { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_bus &pcie_wlanen>; +- vdd10-supply = <&ldo6_reg>; +- vdd18-supply = <&ldo7_reg>; +- assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_PCIE_100_USER>, +- <&cmu_top CLK_MOUT_SCLK_PCIE_100>; +- assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>, +- <&cmu_top CLK_MOUT_BUS_PLL_USER>; +- assigned-clock-rates = <0>, <100000000>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; +-}; +- +-&pcie_phy { +- status = "okay"; +-}; +- +-&ppmu_d0_general { +- status = "okay"; +- events { +- ppmu_event0_d0_general: ppmu-event0-d0-general { +- event-name = "ppmu-event0-d0-general"; +- }; +- }; +-}; +- +-&ppmu_d1_general { +- status = "okay"; +- events { +- ppmu_event0_d1_general: ppmu-event0-d1-general { +- event-name = "ppmu-event0-d1-general"; +- }; +- }; +-}; +- +-&pinctrl_alive { +- pinctrl-names = "default"; +- pinctrl-0 = <&initial_alive>; +- +- initial_alive: initial-state { +- PIN(INPUT, gpa0-0, DOWN, FAST_SR1); +- PIN(INPUT, gpa0-1, NONE, FAST_SR1); +- PIN(INPUT, gpa0-2, DOWN, FAST_SR1); +- PIN(INPUT, gpa0-3, NONE, FAST_SR1); +- PIN(INPUT, gpa0-4, NONE, FAST_SR1); +- PIN(INPUT, gpa0-5, DOWN, FAST_SR1); +- PIN(INPUT, gpa0-6, NONE, FAST_SR1); +- PIN(INPUT, gpa0-7, NONE, FAST_SR1); +- +- PIN(INPUT, gpa1-0, UP, FAST_SR1); +- PIN(INPUT, gpa1-1, UP, FAST_SR1); +- PIN(INPUT, gpa1-2, NONE, FAST_SR1); +- PIN(INPUT, gpa1-3, DOWN, FAST_SR1); +- PIN(INPUT, gpa1-4, DOWN, FAST_SR1); +- PIN(INPUT, gpa1-5, NONE, FAST_SR1); +- PIN(INPUT, gpa1-6, NONE, FAST_SR1); +- PIN(INPUT, gpa1-7, NONE, FAST_SR1); +- +- PIN(INPUT, gpa2-0, NONE, FAST_SR1); +- PIN(INPUT, gpa2-1, NONE, FAST_SR1); +- PIN(INPUT, gpa2-2, NONE, FAST_SR1); +- PIN(INPUT, gpa2-3, DOWN, FAST_SR1); +- PIN(INPUT, gpa2-4, NONE, FAST_SR1); +- PIN(INPUT, gpa2-5, DOWN, FAST_SR1); +- PIN(INPUT, gpa2-6, DOWN, FAST_SR1); +- PIN(INPUT, gpa2-7, NONE, FAST_SR1); +- +- PIN(INPUT, gpa3-0, DOWN, FAST_SR1); +- PIN(INPUT, gpa3-1, DOWN, FAST_SR1); +- PIN(INPUT, gpa3-2, NONE, FAST_SR1); +- PIN(INPUT, gpa3-3, DOWN, FAST_SR1); +- PIN(INPUT, gpa3-4, NONE, FAST_SR1); +- PIN(INPUT, gpa3-5, DOWN, FAST_SR1); +- PIN(INPUT, gpa3-6, DOWN, FAST_SR1); +- PIN(INPUT, gpa3-7, DOWN, FAST_SR1); +- +- PIN(INPUT, gpf1-0, NONE, FAST_SR1); +- PIN(INPUT, gpf1-1, NONE, FAST_SR1); +- PIN(INPUT, gpf1-2, DOWN, FAST_SR1); +- PIN(INPUT, gpf1-4, UP, FAST_SR1); +- PIN(OUTPUT, gpf1-5, NONE, FAST_SR1); +- PIN(INPUT, gpf1-6, DOWN, FAST_SR1); +- PIN(INPUT, gpf1-7, DOWN, FAST_SR1); +- +- PIN(INPUT, gpf2-0, DOWN, FAST_SR1); +- PIN(INPUT, gpf2-1, DOWN, FAST_SR1); +- PIN(INPUT, gpf2-2, DOWN, FAST_SR1); +- PIN(INPUT, gpf2-3, DOWN, FAST_SR1); +- +- PIN(INPUT, gpf3-0, DOWN, FAST_SR1); +- PIN(INPUT, gpf3-1, DOWN, FAST_SR1); +- PIN(INPUT, gpf3-2, NONE, FAST_SR1); +- PIN(INPUT, gpf3-3, DOWN, FAST_SR1); +- +- PIN(INPUT, gpf4-0, DOWN, FAST_SR1); +- PIN(INPUT, gpf4-1, DOWN, FAST_SR1); +- PIN(INPUT, gpf4-2, DOWN, FAST_SR1); +- PIN(INPUT, gpf4-3, DOWN, FAST_SR1); +- PIN(INPUT, gpf4-4, DOWN, FAST_SR1); +- PIN(INPUT, gpf4-5, DOWN, FAST_SR1); +- PIN(INPUT, gpf4-6, DOWN, FAST_SR1); +- PIN(INPUT, gpf4-7, DOWN, FAST_SR1); +- +- PIN(INPUT, gpf5-0, DOWN, FAST_SR1); +- PIN(INPUT, gpf5-1, DOWN, FAST_SR1); +- PIN(INPUT, gpf5-2, DOWN, FAST_SR1); +- PIN(INPUT, gpf5-3, DOWN, FAST_SR1); +- PIN(OUTPUT, gpf5-4, NONE, FAST_SR1); +- PIN(INPUT, gpf5-5, DOWN, FAST_SR1); +- PIN(INPUT, gpf5-6, DOWN, FAST_SR1); +- PIN(INPUT, gpf5-7, DOWN, FAST_SR1); +- }; +- +- te_irq: te-irq { +- samsung,pins = "gpf1-3"; +- samsung,pin-function = <0xf>; +- }; +-}; +- +-&pinctrl_cpif { +- pinctrl-names = "default"; +- pinctrl-0 = <&initial_cpif>; +- +- initial_cpif: initial-state { +- PIN(INPUT, gpv6-0, DOWN, FAST_SR1); +- PIN(INPUT, gpv6-1, DOWN, FAST_SR1); +- }; +-}; +- +-&pinctrl_ese { +- pinctrl-names = "default"; +- pinctrl-0 = <&initial_ese>; +- +- pcie_wlanen: pcie-wlanen { +- PIN(INPUT, gpj2-0, UP, FAST_SR4); +- }; +- +- initial_ese: initial-state { +- PIN(INPUT, gpj2-1, DOWN, FAST_SR1); +- PIN(INPUT, gpj2-2, DOWN, FAST_SR1); +- }; +-}; +- +-&pinctrl_fsys { +- pinctrl-names = "default"; +- pinctrl-0 = <&initial_fsys>; +- +- initial_fsys: initial-state { +- PIN(INPUT, gpr3-0, NONE, FAST_SR1); +- PIN(INPUT, gpr3-1, DOWN, FAST_SR1); +- PIN(INPUT, gpr3-2, DOWN, FAST_SR1); +- PIN(INPUT, gpr3-3, DOWN, FAST_SR1); +- PIN(INPUT, gpr3-7, NONE, FAST_SR1); +- }; +-}; +- +-&pinctrl_imem { +- pinctrl-names = "default"; +- pinctrl-0 = <&initial_imem>; +- +- initial_imem: initial-state { +- PIN(INPUT, gpf0-0, UP, FAST_SR1); +- PIN(INPUT, gpf0-1, UP, FAST_SR1); +- PIN(INPUT, gpf0-2, DOWN, FAST_SR1); +- PIN(INPUT, gpf0-3, UP, FAST_SR1); +- PIN(INPUT, gpf0-4, DOWN, FAST_SR1); +- PIN(INPUT, gpf0-5, NONE, FAST_SR1); +- PIN(INPUT, gpf0-6, DOWN, FAST_SR1); +- PIN(INPUT, gpf0-7, UP, FAST_SR1); +- }; +-}; +- +-&pinctrl_nfc { +- pinctrl-names = "default"; +- pinctrl-0 = <&initial_nfc>; +- +- initial_nfc: initial-state { +- PIN(INPUT, gpj0-2, DOWN, FAST_SR1); +- }; +-}; +- +-&pinctrl_peric { +- pinctrl-names = "default"; +- pinctrl-0 = <&initial_peric>; +- +- initial_peric: initial-state { +- PIN(INPUT, gpv7-0, DOWN, FAST_SR1); +- PIN(INPUT, gpv7-1, DOWN, FAST_SR1); +- PIN(INPUT, gpv7-2, NONE, FAST_SR1); +- PIN(INPUT, gpv7-3, DOWN, FAST_SR1); +- PIN(INPUT, gpv7-4, DOWN, FAST_SR1); +- PIN(INPUT, gpv7-5, DOWN, FAST_SR1); +- +- PIN(INPUT, gpb0-4, DOWN, FAST_SR1); +- +- PIN(INPUT, gpc0-2, DOWN, FAST_SR1); +- PIN(INPUT, gpc0-5, DOWN, FAST_SR1); +- PIN(INPUT, gpc0-7, DOWN, FAST_SR1); +- +- PIN(INPUT, gpc1-1, DOWN, FAST_SR1); +- +- PIN(INPUT, gpc3-4, NONE, FAST_SR1); +- PIN(INPUT, gpc3-5, NONE, FAST_SR1); +- PIN(INPUT, gpc3-6, NONE, FAST_SR1); +- PIN(INPUT, gpc3-7, NONE, FAST_SR1); +- +- PIN(OUTPUT, gpg0-0, NONE, FAST_SR1); +- PIN(2, gpg0-1, DOWN, FAST_SR1); +- +- PIN(INPUT, gpd2-5, DOWN, FAST_SR1); +- +- PIN(INPUT, gpd4-0, NONE, FAST_SR1); +- PIN(INPUT, gpd4-1, DOWN, FAST_SR1); +- PIN(INPUT, gpd4-2, DOWN, FAST_SR1); +- PIN(INPUT, gpd4-3, DOWN, FAST_SR1); +- PIN(INPUT, gpd4-4, DOWN, FAST_SR1); +- +- PIN(INPUT, gpd6-3, DOWN, FAST_SR1); +- +- PIN(INPUT, gpd8-1, UP, FAST_SR1); +- +- PIN(INPUT, gpg1-0, DOWN, FAST_SR1); +- PIN(INPUT, gpg1-1, DOWN, FAST_SR1); +- PIN(INPUT, gpg1-2, DOWN, FAST_SR1); +- PIN(INPUT, gpg1-3, DOWN, FAST_SR1); +- PIN(INPUT, gpg1-4, DOWN, FAST_SR1); +- +- PIN(INPUT, gpg2-0, DOWN, FAST_SR1); +- PIN(INPUT, gpg2-1, DOWN, FAST_SR1); +- +- PIN(INPUT, gpg3-0, DOWN, FAST_SR1); +- PIN(INPUT, gpg3-1, DOWN, FAST_SR1); +- PIN(INPUT, gpg3-5, DOWN, FAST_SR1); +- }; +-}; +- +-&pinctrl_touch { +- pinctrl-names = "default"; +- pinctrl-0 = <&initial_touch>; +- +- initial_touch: initial-state { +- PIN(INPUT, gpj1-2, DOWN, FAST_SR1); +- }; +-}; +- +-&pwm { +- pinctrl-0 = <&pwm0_out>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&mic { +- status = "okay"; +-}; +- +-&pmu_system_controller { +- assigned-clocks = <&pmu_system_controller 0>; +- assigned-clock-parents = <&xxti>; +-}; +- +-&serial_1 { +- status = "okay"; +-}; +- +-&serial_3 { +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- max-speed = <3000000>; +- shutdown-gpios = <&gpd4 0 GPIO_ACTIVE_HIGH>; +- device-wakeup-gpios = <&gpr3 7 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpa2 2 GPIO_ACTIVE_HIGH>; +- clocks = <&s2mps13_osc S2MPS11_CLK_BT>; +- clock-names = "extclk"; +- }; +-}; +- +-&spi_1 { +- cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- +- wm5110: audio-codec@0 { +- compatible = "wlf,wm5110"; +- reg = <0x0>; +- spi-max-frequency = <20000000>; +- interrupt-parent = <&gpa0>; +- interrupts = <4 IRQ_TYPE_NONE>; +- clocks = <&pmu_system_controller 0>, +- <&s2mps13_osc S2MPS11_CLK_BT>; +- clock-names = "mclk1", "mclk2"; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- wlf,micd-detect-debounce = <300>; +- wlf,micd-bias-start-time = <0x1>; +- wlf,micd-rate = <0x7>; +- wlf,micd-dbtime = <0x1>; +- wlf,micd-force-micbias; +- wlf,micd-configs = <0x0 1 0>; +- wlf,hpdet-channel = <1>; +- wlf,gpsw = <0x1>; +- wlf,inmode = <2 0 2 0>; +- +- wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>; +- wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>; +- +- /* core supplies */ +- AVDD-supply = <&ldo18_reg>; +- DBVDD1-supply = <&ldo18_reg>; +- CPVDD-supply = <&ldo18_reg>; +- DBVDD2-supply = <&ldo18_reg>; +- DBVDD3-supply = <&ldo18_reg>; +- +- controller-data { +- samsung,spi-feedback-delay = <0>; +- }; +- }; +-}; +- +-&spi_3 { +- status = "okay"; +- no-cs-readback; +- +- irled@0 { +- compatible = "ir-spi-led"; +- reg = <0x0>; +- spi-max-frequency = <5000000>; +- power-supply = <&irda_regulator>; +- duty-cycle = <60>; +- led-active-low; +- +- controller-data { +- samsung,spi-feedback-delay = <0>; +- }; +- }; +-}; +- +-&timer { +- clock-frequency = <24000000>; +-}; +- +-&tmu_atlas0 { +- vtmu-supply = <&ldo3_reg>; +- status = "okay"; +-}; +- +-&tmu_apollo { +- vtmu-supply = <&ldo3_reg>; +- status = "okay"; +-}; +- +-&tmu_g3d { +- vtmu-supply = <&ldo3_reg>; +- status = "okay"; +-}; +- +-&usbdrd30 { +- vdd33-supply = <&ldo10_reg>; +- vdd10-supply = <&ldo6_reg>; +- status = "okay"; +-}; +- +-&usbdrd_dwc3 { +- dr_mode = "otg"; +-}; +- +-&usbdrd30_phy { +- vbus-supply = <&safeout1_reg>; +- status = "okay"; +- +- port { +- usb_to_muic: endpoint { +- remote-endpoint = <&muic_to_usb>; +- }; +- }; +-}; +- +-&xxti { +- clock-frequency = <24000000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/exynos/exynos5433-tm2.dts b/scripts/dtc/include-prefixes/arm64/exynos/exynos5433-tm2.dts +deleted file mode 100644 +index fdd0796b29d4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/exynos/exynos5433-tm2.dts ++++ /dev/null +@@ -1,93 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung Exynos5433 TM2 board device tree source +- * +- * Copyright (c) 2016 Samsung Electronics Co., Ltd. +- * +- * Device tree source file for Samsung's TM2 board which is based on +- * Samsung Exynos5433 SoC. +- */ +- +-#include "exynos5433-tm2-common.dtsi" +- +-/ { +- model = "Samsung TM2 board"; +- compatible = "samsung,tm2", "samsung,exynos5433"; +-}; +- +-&cmu_disp { +- /* +- * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned +- * clocks properties for DISP CMU for each board to keep them together +- * for easier review and maintenance. +- */ +- assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>, +- <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, +- <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>, +- <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, +- <&cmu_disp CLK_MOUT_SCLK_DSIM0>, +- <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, +- <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>, +- <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, +- <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>, +- <&cmu_disp CLK_MOUT_DISP_PLL>, +- <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, +- <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, +- <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>, +- <&cmu_disp CLK_MOUT_SCLK_DSD_USER>; +- assigned-clock-parents = <0>, <0>, +- <&cmu_mif CLK_ACLK_DISP_333>, +- <&cmu_mif CLK_SCLK_DSIM0_DISP>, +- <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, +- <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, +- <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, +- <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>, +- <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>, +- <&cmu_disp CLK_FOUT_DISP_PLL>, +- <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, +- <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, +- <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, +- <&cmu_mif CLK_SCLK_DSD_DISP>; +- assigned-clock-rates = <250000000>, <400000000>; +-}; +- +-&dsi { +- panel@0 { +- compatible = "samsung,s6e3ha2"; +- reg = <0>; +- vdd3-supply = <&ldo27_reg>; +- vci-supply = <&ldo28_reg>; +- reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>; +- enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&hsi2c_9 { +- status = "okay"; +- +- touchkey@20 { +- compatible = "cypress,tm2-touchkey"; +- reg = <0x20>; +- interrupt-parent = <&gpa3>; +- interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +- vcc-supply = <&ldo32_reg>; +- vdd-supply = <&ldo33_reg>; +- }; +-}; +- +-&ldo31_reg { +- regulator-name = "TSP_VDD_1.85V_AP"; +- regulator-min-microvolt = <1850000>; +- regulator-max-microvolt = <1850000>; +-}; +- +-&ldo38_reg { +- regulator-name = "VCC_3.0V_MOTOR_AP"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +-}; +- +-&stmfts { +- touchscreen-size-x = <1439>; +- touchscreen-size-y = <2559>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/exynos/exynos5433-tm2e.dts b/scripts/dtc/include-prefixes/arm64/exynos/exynos5433-tm2e.dts +deleted file mode 100644 +index 089fc7a1af67..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/exynos/exynos5433-tm2e.dts ++++ /dev/null +@@ -1,80 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung Exynos5433 TM2E board device tree source +- * +- * Copyright (c) 2016 Samsung Electronics Co., Ltd. +- * +- * Device tree source file for Samsung's TM2E(TM2 EDGE) board which is based on +- * Samsung Exynos5433 SoC. +- */ +- +-#include "exynos5433-tm2-common.dtsi" +- +-/ { +- model = "Samsung TM2E board"; +- compatible = "samsung,tm2e", "samsung,exynos5433"; +-}; +- +-&cmu_disp { +- /* +- * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned +- * clocks properties for DISP CMU for each board to keep them together +- * for easier review and maintenance. +- */ +- assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>, +- <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, +- <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>, +- <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, +- <&cmu_disp CLK_MOUT_SCLK_DSIM0>, +- <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, +- <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>, +- <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, +- <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>, +- <&cmu_disp CLK_MOUT_DISP_PLL>, +- <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, +- <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, +- <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; +- assigned-clock-parents = <0>, <0>, +- <&cmu_mif CLK_ACLK_DISP_333>, +- <&cmu_mif CLK_SCLK_DSIM0_DISP>, +- <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, +- <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, +- <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, +- <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>, +- <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>, +- <&cmu_disp CLK_FOUT_DISP_PLL>, +- <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, +- <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, +- <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; +- assigned-clock-rates = <278000000>, <400000000>; +-}; +- +-&dsi { +- panel@0 { +- compatible = "samsung,s6e3hf2"; +- reg = <0>; +- vdd3-supply = <&ldo27_reg>; +- vci-supply = <&ldo28_reg>; +- reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>; +- enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&ldo31_reg { +- regulator-name = "TSP_VDD_1.8V_AP"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +-}; +- +-&ldo38_reg { +- regulator-name = "VCC_3.3V_MOTOR_AP"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +-}; +- +-&stmfts { +- touchscreen-size-x = <1599>; +- touchscreen-size-y = <2559>; +- touch-key-connected; +- ledvdd-supply = <&ldo33_reg>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/exynos/exynos5433-tmu.dtsi b/scripts/dtc/include-prefixes/arm64/exynos/exynos5433-tmu.dtsi +deleted file mode 100644 +index 81b72393dd0d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/exynos/exynos5433-tmu.dtsi ++++ /dev/null +@@ -1,305 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device tree sources for Exynos5433 thermal zone +- * +- * Copyright (c) 2016 Chanwoo Choi +- */ +- +-#include +- +-/ { +-thermal-zones { +- atlas0_thermal: atlas0-thermal { +- thermal-sensors = <&tmu_atlas0>; +- polling-delay-passive = <0>; +- polling-delay = <0>; +- trips { +- atlas0_alert_0: atlas0-alert-0 { +- temperature = <65000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- atlas0_alert_1: atlas0-alert-1 { +- temperature = <70000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- atlas0_alert_2: atlas0-alert-2 { +- temperature = <75000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- atlas0_alert_3: atlas0-alert-3 { +- temperature = <80000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- atlas0_alert_4: atlas0-alert-4 { +- temperature = <85000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- atlas0_alert_5: atlas0-alert-5 { +- temperature = <90000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- atlas0_alert_6: atlas0-alert-6 { +- temperature = <95000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- }; +- +- cooling-maps { +- map0 { +- /* Set maximum frequency as 1800MHz */ +- trip = <&atlas0_alert_0>; +- cooling-device = <&cpu4 1 2>, <&cpu5 1 2>, +- <&cpu6 1 2>, <&cpu7 1 2>; +- }; +- map1 { +- /* Set maximum frequency as 1700MHz */ +- trip = <&atlas0_alert_1>; +- cooling-device = <&cpu4 2 3>, <&cpu5 2 3>, +- <&cpu6 2 3>, <&cpu7 2 3>; +- }; +- map2 { +- /* Set maximum frequency as 1600MHz */ +- trip = <&atlas0_alert_2>; +- cooling-device = <&cpu4 3 4>, <&cpu5 3 4>, +- <&cpu6 3 4>, <&cpu7 3 4>; +- }; +- map3 { +- /* Set maximum frequency as 1500MHz */ +- trip = <&atlas0_alert_3>; +- cooling-device = <&cpu4 4 5>, <&cpu5 4 5>, +- <&cpu6 4 5>, <&cpu7 4 5>; +- }; +- map4 { +- /* Set maximum frequency as 1400MHz */ +- trip = <&atlas0_alert_4>; +- cooling-device = <&cpu4 5 7>, <&cpu5 5 7>, +- <&cpu6 5 7>, <&cpu7 5 7>; +- }; +- map5 { +- /* Set maximum frequencyas 1200MHz */ +- trip = <&atlas0_alert_5>; +- cooling-device = <&cpu4 7 9>, <&cpu5 7 9>, +- <&cpu6 7 9>, <&cpu7 7 9>; +- }; +- map6 { +- /* Set maximum frequency as 1000MHz */ +- trip = <&atlas0_alert_6>; +- cooling-device = <&cpu4 9 14>, <&cpu5 9 14>, +- <&cpu6 9 14>, <&cpu7 9 14>; +- }; +- }; +- }; +- +- atlas1_thermal: atlas1-thermal { +- thermal-sensors = <&tmu_atlas1>; +- polling-delay-passive = <0>; +- polling-delay = <0>; +- trips { +- atlas1_alert_0: atlas1-alert-0 { +- temperature = <65000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- atlas1_alert_1: atlas1-alert-1 { +- temperature = <70000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- atlas1_alert_2: atlas1-alert-2 { +- temperature = <75000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- atlas1_alert_3: atlas1-alert-3 { +- temperature = <80000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- atlas1_alert_4: atlas1-alert-4 { +- temperature = <85000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- atlas1_alert_5: atlas1-alert-5 { +- temperature = <90000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- atlas1_alert_6: atlas1-alert-6 { +- temperature = <95000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- }; +- }; +- +- g3d_thermal: g3d-thermal { +- thermal-sensors = <&tmu_g3d>; +- polling-delay-passive = <0>; +- polling-delay = <0>; +- trips { +- g3d_alert_0: g3d-alert-0 { +- temperature = <70000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- g3d_alert_1: g3d-alert-1 { +- temperature = <75000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- g3d_alert_2: g3d-alert-2 { +- temperature = <80000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- g3d_alert_3: g3d-alert-3 { +- temperature = <85000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- g3d_alert_4: g3d-alert-4 { +- temperature = <90000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- g3d_alert_5: g3d-alert-5 { +- temperature = <95000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- g3d_alert_6: g3d-alert-6 { +- temperature = <100000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- }; +- }; +- +- apollo_thermal: apollo-thermal { +- thermal-sensors = <&tmu_apollo>; +- polling-delay-passive = <0>; +- polling-delay = <0>; +- trips { +- apollo_alert_0: apollo-alert-0 { +- temperature = <65000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- apollo_alert_1: apollo-alert-1 { +- temperature = <70000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- apollo_alert_2: apollo-alert-2 { +- temperature = <75000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- apollo_alert_3: apollo-alert-3 { +- temperature = <80000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- apollo_alert_4: apollo-alert-4 { +- temperature = <85000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- apollo_alert_5: apollo-alert-5 { +- temperature = <90000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- apollo_alert_6: apollo-alert-6 { +- temperature = <95000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- }; +- +- cooling-maps { +- map0 { +- /* Set maximum frequency as 1200MHz */ +- trip = <&apollo_alert_2>; +- cooling-device = <&cpu0 1 2>, <&cpu1 1 2>, +- <&cpu2 1 2>, <&cpu3 1 2>; +- }; +- map1 { +- /* Set maximum frequency as 1100MHz */ +- trip = <&apollo_alert_3>; +- cooling-device = <&cpu0 2 3>, <&cpu1 2 3>, +- <&cpu2 2 3>, <&cpu3 2 3>; +- }; +- map2 { +- /* Set maximum frequency as 1000MHz */ +- trip = <&apollo_alert_4>; +- cooling-device = <&cpu0 3 4>, <&cpu1 3 4>, +- <&cpu2 3 4>, <&cpu3 3 4>; +- }; +- map3 { +- /* Set maximum frequency as 900MHz */ +- trip = <&apollo_alert_5>; +- cooling-device = <&cpu0 4 5>, <&cpu1 4 5>, +- <&cpu2 4 5>, <&cpu3 4 5>; +- }; +- map4 { +- /* Set maximum frequency as 800MHz */ +- trip = <&apollo_alert_6>; +- cooling-device = <&cpu0 5 9>, <&cpu1 5 9>, +- <&cpu2 5 9>, <&cpu3 5 9>; +- }; +- }; +- }; +- +- isp_thermal: isp-thermal { +- thermal-sensors = <&tmu_isp>; +- polling-delay-passive = <0>; +- polling-delay = <0>; +- trips { +- isp_alert_0: isp-alert-0 { +- temperature = <80000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- isp_alert_1: isp-alert-1 { +- temperature = <85000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- isp_alert_2: isp-alert-2 { +- temperature = <90000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- isp_alert_3: isp-alert-3 { +- temperature = <95000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- isp_alert_4: isp-alert-4 { +- temperature = <100000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- isp_alert_5: isp-alert-5 { +- temperature = <105000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- isp_alert_6: isp-alert-6 { +- temperature = <110000>; /* millicelsius */ +- hysteresis = <1000>; /* millicelsius */ +- type = "active"; +- }; +- }; +- }; +-}; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/exynos/exynos5433.dtsi b/scripts/dtc/include-prefixes/arm64/exynos/exynos5433.dtsi +deleted file mode 100644 +index 6a6f7dd1d65c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/exynos/exynos5433.dtsi ++++ /dev/null +@@ -1,1987 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos5433 SoC device tree source +- * +- * Copyright (c) 2016 Samsung Electronics Co., Ltd. +- * +- * Samsung's Exynos5433 SoC device nodes are listed in this file. +- * Exynos5433 based board files can include this file and provide +- * values for board specific bindings. +- * +- * Note: This file does not include device nodes for all the controllers in +- * Exynos5433 SoC. As device tree coverage for Exynos5433 increases, +- * additional nodes can be added to this file. +- */ +- +-#include +-#include +- +-/ { +- compatible = "samsung,exynos5433"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- interrupt-parent = <&gic>; +- +- arm-a53-pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- arm-a57-pmu { +- compatible = "arm,cortex-a57-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; +- }; +- +- xxti: clock { +- /* XXTI */ +- compatible = "fixed-clock"; +- clock-output-names = "oscclk"; +- #clock-cells = <0>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- core2 { +- cpu = <&cpu2>; +- }; +- core3 { +- cpu = <&cpu3>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&cpu4>; +- }; +- core1 { +- cpu = <&cpu5>; +- }; +- core2 { +- cpu = <&cpu6>; +- }; +- core3 { +- cpu = <&cpu7>; +- }; +- }; +- }; +- +- cpu0: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x100>; +- clock-frequency = <1300000000>; +- clocks = <&cmu_apollo CLK_SCLK_APOLLO>; +- clock-names = "apolloclk"; +- operating-points-v2 = <&cluster_a53_opp_table>; +- #cooling-cells = <2>; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&cluster_a53_l2>; +- }; +- +- cpu1: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x101>; +- clock-frequency = <1300000000>; +- operating-points-v2 = <&cluster_a53_opp_table>; +- #cooling-cells = <2>; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&cluster_a53_l2>; +- }; +- +- cpu2: cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x102>; +- clock-frequency = <1300000000>; +- operating-points-v2 = <&cluster_a53_opp_table>; +- #cooling-cells = <2>; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&cluster_a53_l2>; +- }; +- +- cpu3: cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x103>; +- clock-frequency = <1300000000>; +- operating-points-v2 = <&cluster_a53_opp_table>; +- #cooling-cells = <2>; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&cluster_a53_l2>; +- }; +- +- cpu4: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- enable-method = "psci"; +- reg = <0x0>; +- clock-frequency = <1900000000>; +- clocks = <&cmu_atlas CLK_SCLK_ATLAS>; +- clock-names = "atlasclk"; +- operating-points-v2 = <&cluster_a57_opp_table>; +- #cooling-cells = <2>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&cluster_a57_l2>; +- }; +- +- cpu5: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- enable-method = "psci"; +- reg = <0x1>; +- clock-frequency = <1900000000>; +- operating-points-v2 = <&cluster_a57_opp_table>; +- #cooling-cells = <2>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&cluster_a57_l2>; +- }; +- +- cpu6: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- enable-method = "psci"; +- reg = <0x2>; +- clock-frequency = <1900000000>; +- operating-points-v2 = <&cluster_a57_opp_table>; +- #cooling-cells = <2>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&cluster_a57_l2>; +- }; +- +- cpu7: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- enable-method = "psci"; +- reg = <0x3>; +- clock-frequency = <1900000000>; +- operating-points-v2 = <&cluster_a57_opp_table>; +- #cooling-cells = <2>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&cluster_a57_l2>; +- }; +- +- cluster_a57_l2: l2-cache0 { +- compatible = "cache"; +- cache-size = <0x200000>; +- cache-line-size = <64>; +- cache-sets = <2048>; +- }; +- +- cluster_a53_l2: l2-cache1 { +- compatible = "cache"; +- cache-size = <0x40000>; +- cache-line-size = <64>; +- cache-sets = <256>; +- }; +- }; +- +- cluster_a53_opp_table: opp-table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <900000>; +- }; +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <925000>; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <950000>; +- }; +- opp-700000000 { +- opp-hz = /bits/ 64 <700000000>; +- opp-microvolt = <975000>; +- }; +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <1000000>; +- }; +- opp-900000000 { +- opp-hz = /bits/ 64 <900000000>; +- opp-microvolt = <1050000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <1075000>; +- }; +- opp-1100000000 { +- opp-hz = /bits/ 64 <1100000000>; +- opp-microvolt = <1112500>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <1112500>; +- }; +- opp-1300000000 { +- opp-hz = /bits/ 64 <1300000000>; +- opp-microvolt = <1150000>; +- }; +- }; +- +- cluster_a57_opp_table: opp-table1 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <900000>; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <900000>; +- }; +- opp-700000000 { +- opp-hz = /bits/ 64 <700000000>; +- opp-microvolt = <912500>; +- }; +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <912500>; +- }; +- opp-900000000 { +- opp-hz = /bits/ 64 <900000000>; +- opp-microvolt = <937500>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <975000>; +- }; +- opp-1100000000 { +- opp-hz = /bits/ 64 <1100000000>; +- opp-microvolt = <1012500>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <1037500>; +- }; +- opp-1300000000 { +- opp-hz = /bits/ 64 <1300000000>; +- opp-microvolt = <1062500>; +- }; +- opp-1400000000 { +- opp-hz = /bits/ 64 <1400000000>; +- opp-microvolt = <1087500>; +- }; +- opp-1500000000 { +- opp-hz = /bits/ 64 <1500000000>; +- opp-microvolt = <1125000>; +- }; +- opp-1600000000 { +- opp-hz = /bits/ 64 <1600000000>; +- opp-microvolt = <1137500>; +- }; +- opp-1700000000 { +- opp-hz = /bits/ 64 <1700000000>; +- opp-microvolt = <1175000>; +- }; +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <1212500>; +- }; +- opp-1900000000 { +- opp-hz = /bits/ 64 <1900000000>; +- opp-microvolt = <1262500>; +- }; +- }; +- +- psci { +- compatible = "arm,psci"; +- method = "smc"; +- cpu_off = <0x84000002>; +- cpu_on = <0xC4000003>; +- }; +- +- soc: soc@0 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x0 0x18000000>; +- +- chipid@10000000 { +- compatible = "samsung,exynos4210-chipid"; +- reg = <0x10000000 0x100>; +- }; +- +- cmu_top: clock-controller@10030000 { +- compatible = "samsung,exynos5433-cmu-top"; +- reg = <0x10030000 0x1000>; +- #clock-cells = <1>; +- +- clock-names = "oscclk", +- "sclk_mphy_pll", +- "sclk_mfc_pll", +- "sclk_bus_pll"; +- clocks = <&xxti>, +- <&cmu_cpif CLK_SCLK_MPHY_PLL>, +- <&cmu_mif CLK_SCLK_MFC_PLL>, +- <&cmu_mif CLK_SCLK_BUS_PLL>; +- }; +- +- cmu_cpif: clock-controller@10fc0000 { +- compatible = "samsung,exynos5433-cmu-cpif"; +- reg = <0x10fc0000 0x1000>; +- #clock-cells = <1>; +- +- clock-names = "oscclk"; +- clocks = <&xxti>; +- }; +- +- cmu_mif: clock-controller@105b0000 { +- compatible = "samsung,exynos5433-cmu-mif"; +- reg = <0x105b0000 0x2000>; +- #clock-cells = <1>; +- +- clock-names = "oscclk", +- "sclk_mphy_pll"; +- clocks = <&xxti>, +- <&cmu_cpif CLK_SCLK_MPHY_PLL>; +- }; +- +- cmu_peric: clock-controller@14c80000 { +- compatible = "samsung,exynos5433-cmu-peric"; +- reg = <0x14c80000 0x1000>; +- #clock-cells = <1>; +- }; +- +- cmu_peris: clock-controller@10040000 { +- compatible = "samsung,exynos5433-cmu-peris"; +- reg = <0x10040000 0x1000>; +- #clock-cells = <1>; +- }; +- +- cmu_fsys: clock-controller@156e0000 { +- compatible = "samsung,exynos5433-cmu-fsys"; +- reg = <0x156e0000 0x1000>; +- #clock-cells = <1>; +- +- clock-names = "oscclk", +- "sclk_ufs_mphy", +- "aclk_fsys_200", +- "sclk_pcie_100_fsys", +- "sclk_ufsunipro_fsys", +- "sclk_mmc2_fsys", +- "sclk_mmc1_fsys", +- "sclk_mmc0_fsys", +- "sclk_usbhost30_fsys", +- "sclk_usbdrd30_fsys"; +- clocks = <&xxti>, +- <&cmu_cpif CLK_SCLK_UFS_MPHY>, +- <&cmu_top CLK_ACLK_FSYS_200>, +- <&cmu_top CLK_SCLK_PCIE_100_FSYS>, +- <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, +- <&cmu_top CLK_SCLK_MMC2_FSYS>, +- <&cmu_top CLK_SCLK_MMC1_FSYS>, +- <&cmu_top CLK_SCLK_MMC0_FSYS>, +- <&cmu_top CLK_SCLK_USBHOST30_FSYS>, +- <&cmu_top CLK_SCLK_USBDRD30_FSYS>; +- }; +- +- cmu_g2d: clock-controller@12460000 { +- compatible = "samsung,exynos5433-cmu-g2d"; +- reg = <0x12460000 0x1000>; +- #clock-cells = <1>; +- +- clock-names = "oscclk", +- "aclk_g2d_266", +- "aclk_g2d_400"; +- clocks = <&xxti>, +- <&cmu_top CLK_ACLK_G2D_266>, +- <&cmu_top CLK_ACLK_G2D_400>; +- power-domains = <&pd_g2d>; +- }; +- +- cmu_disp: clock-controller@13b90000 { +- compatible = "samsung,exynos5433-cmu-disp"; +- reg = <0x13b90000 0x1000>; +- #clock-cells = <1>; +- +- clock-names = "oscclk", +- "sclk_dsim1_disp", +- "sclk_dsim0_disp", +- "sclk_dsd_disp", +- "sclk_decon_tv_eclk_disp", +- "sclk_decon_vclk_disp", +- "sclk_decon_eclk_disp", +- "sclk_decon_tv_vclk_disp", +- "aclk_disp_333"; +- clocks = <&xxti>, +- <&cmu_mif CLK_SCLK_DSIM1_DISP>, +- <&cmu_mif CLK_SCLK_DSIM0_DISP>, +- <&cmu_mif CLK_SCLK_DSD_DISP>, +- <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, +- <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, +- <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, +- <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, +- <&cmu_mif CLK_ACLK_DISP_333>; +- power-domains = <&pd_disp>; +- }; +- +- cmu_aud: clock-controller@114c0000 { +- compatible = "samsung,exynos5433-cmu-aud"; +- reg = <0x114c0000 0x1000>; +- #clock-cells = <1>; +- clock-names = "oscclk", "fout_aud_pll"; +- clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; +- power-domains = <&pd_aud>; +- }; +- +- cmu_bus0: clock-controller@13600000 { +- compatible = "samsung,exynos5433-cmu-bus0"; +- reg = <0x13600000 0x1000>; +- #clock-cells = <1>; +- +- clock-names = "aclk_bus0_400"; +- clocks = <&cmu_top CLK_ACLK_BUS0_400>; +- }; +- +- cmu_bus1: clock-controller@14800000 { +- compatible = "samsung,exynos5433-cmu-bus1"; +- reg = <0x14800000 0x1000>; +- #clock-cells = <1>; +- +- clock-names = "aclk_bus1_400"; +- clocks = <&cmu_top CLK_ACLK_BUS1_400>; +- }; +- +- cmu_bus2: clock-controller@13400000 { +- compatible = "samsung,exynos5433-cmu-bus2"; +- reg = <0x13400000 0x1000>; +- #clock-cells = <1>; +- +- clock-names = "oscclk", "aclk_bus2_400"; +- clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; +- }; +- +- cmu_g3d: clock-controller@14aa0000 { +- compatible = "samsung,exynos5433-cmu-g3d"; +- reg = <0x14aa0000 0x2000>; +- #clock-cells = <1>; +- +- clock-names = "oscclk", "aclk_g3d_400"; +- clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; +- power-domains = <&pd_g3d>; +- }; +- +- cmu_gscl: clock-controller@13cf0000 { +- compatible = "samsung,exynos5433-cmu-gscl"; +- reg = <0x13cf0000 0x1000>; +- #clock-cells = <1>; +- +- clock-names = "oscclk", +- "aclk_gscl_111", +- "aclk_gscl_333"; +- clocks = <&xxti>, +- <&cmu_top CLK_ACLK_GSCL_111>, +- <&cmu_top CLK_ACLK_GSCL_333>; +- power-domains = <&pd_gscl>; +- }; +- +- cmu_apollo: clock-controller@11900000 { +- compatible = "samsung,exynos5433-cmu-apollo"; +- reg = <0x11900000 0x2000>; +- #clock-cells = <1>; +- +- clock-names = "oscclk", "sclk_bus_pll_apollo"; +- clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; +- }; +- +- cmu_atlas: clock-controller@11800000 { +- compatible = "samsung,exynos5433-cmu-atlas"; +- reg = <0x11800000 0x2000>; +- #clock-cells = <1>; +- +- clock-names = "oscclk", "sclk_bus_pll_atlas"; +- clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; +- }; +- +- cmu_mscl: clock-controller@150d0000 { +- compatible = "samsung,exynos5433-cmu-mscl"; +- reg = <0x150d0000 0x1000>; +- #clock-cells = <1>; +- +- clock-names = "oscclk", +- "sclk_jpeg_mscl", +- "aclk_mscl_400"; +- clocks = <&xxti>, +- <&cmu_top CLK_SCLK_JPEG_MSCL>, +- <&cmu_top CLK_ACLK_MSCL_400>; +- power-domains = <&pd_mscl>; +- }; +- +- cmu_mfc: clock-controller@15280000 { +- compatible = "samsung,exynos5433-cmu-mfc"; +- reg = <0x15280000 0x1000>; +- #clock-cells = <1>; +- +- clock-names = "oscclk", "aclk_mfc_400"; +- clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; +- power-domains = <&pd_mfc>; +- }; +- +- cmu_hevc: clock-controller@14f80000 { +- compatible = "samsung,exynos5433-cmu-hevc"; +- reg = <0x14f80000 0x1000>; +- #clock-cells = <1>; +- +- clock-names = "oscclk", "aclk_hevc_400"; +- clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; +- power-domains = <&pd_hevc>; +- }; +- +- cmu_isp: clock-controller@146d0000 { +- compatible = "samsung,exynos5433-cmu-isp"; +- reg = <0x146d0000 0x1000>; +- #clock-cells = <1>; +- +- clock-names = "oscclk", +- "aclk_isp_dis_400", +- "aclk_isp_400"; +- clocks = <&xxti>, +- <&cmu_top CLK_ACLK_ISP_DIS_400>, +- <&cmu_top CLK_ACLK_ISP_400>; +- power-domains = <&pd_isp>; +- }; +- +- cmu_cam0: clock-controller@120d0000 { +- compatible = "samsung,exynos5433-cmu-cam0"; +- reg = <0x120d0000 0x1000>; +- #clock-cells = <1>; +- +- clock-names = "oscclk", +- "aclk_cam0_333", +- "aclk_cam0_400", +- "aclk_cam0_552"; +- clocks = <&xxti>, +- <&cmu_top CLK_ACLK_CAM0_333>, +- <&cmu_top CLK_ACLK_CAM0_400>, +- <&cmu_top CLK_ACLK_CAM0_552>; +- power-domains = <&pd_cam0>; +- }; +- +- cmu_cam1: clock-controller@145d0000 { +- compatible = "samsung,exynos5433-cmu-cam1"; +- reg = <0x145d0000 0x1000>; +- #clock-cells = <1>; +- +- clock-names = "oscclk", +- "sclk_isp_uart_cam1", +- "sclk_isp_spi1_cam1", +- "sclk_isp_spi0_cam1", +- "aclk_cam1_333", +- "aclk_cam1_400", +- "aclk_cam1_552"; +- clocks = <&xxti>, +- <&cmu_top CLK_SCLK_ISP_UART_CAM1>, +- <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, +- <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, +- <&cmu_top CLK_ACLK_CAM1_333>, +- <&cmu_top CLK_ACLK_CAM1_400>, +- <&cmu_top CLK_ACLK_CAM1_552>; +- power-domains = <&pd_cam1>; +- }; +- +- cmu_imem: clock-controller@11060000 { +- compatible = "samsung,exynos5433-cmu-imem"; +- reg = <0x11060000 0x1000>; +- #clock-cells = <1>; +- +- clock-names = "oscclk", +- "aclk_imem_sssx_266", +- "aclk_imem_266", +- "aclk_imem_200"; +- clocks = <&xxti>, +- <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>, +- <&cmu_top CLK_DIV_ACLK_IMEM_266>, +- <&cmu_top CLK_DIV_ACLK_IMEM_200>; +- }; +- +- slim_sss: slim-sss@11140000 { +- compatible = "samsung,exynos5433-slim-sss"; +- reg = <0x11140000 0x1000>; +- interrupts = ; +- clock-names = "pclk", "aclk"; +- clocks = <&cmu_imem CLK_PCLK_SLIMSSS>, +- <&cmu_imem CLK_ACLK_SLIMSSS>; +- }; +- +- pd_gscl: power-domain@105c4000 { +- compatible = "samsung,exynos5433-pd"; +- reg = <0x105c4000 0x20>; +- #power-domain-cells = <0>; +- label = "GSCL"; +- }; +- +- pd_cam0: power-domain@105c4020 { +- compatible = "samsung,exynos5433-pd"; +- reg = <0x105c4020 0x20>; +- #power-domain-cells = <0>; +- power-domains = <&pd_cam1>; +- label = "CAM0"; +- }; +- +- pd_mscl: power-domain@105c4040 { +- compatible = "samsung,exynos5433-pd"; +- reg = <0x105c4040 0x20>; +- #power-domain-cells = <0>; +- label = "MSCL"; +- }; +- +- pd_g3d: power-domain@105c4060 { +- compatible = "samsung,exynos5433-pd"; +- reg = <0x105c4060 0x20>; +- #power-domain-cells = <0>; +- label = "G3D"; +- }; +- +- pd_disp: power-domain@105c4080 { +- compatible = "samsung,exynos5433-pd"; +- reg = <0x105c4080 0x20>; +- #power-domain-cells = <0>; +- label = "DISP"; +- }; +- +- pd_cam1: power-domain@105c40a0 { +- compatible = "samsung,exynos5433-pd"; +- reg = <0x105c40a0 0x20>; +- #power-domain-cells = <0>; +- label = "CAM1"; +- }; +- +- pd_aud: power-domain@105c40c0 { +- compatible = "samsung,exynos5433-pd"; +- reg = <0x105c40c0 0x20>; +- #power-domain-cells = <0>; +- label = "AUD"; +- }; +- +- pd_g2d: power-domain@105c4120 { +- compatible = "samsung,exynos5433-pd"; +- reg = <0x105c4120 0x20>; +- #power-domain-cells = <0>; +- label = "G2D"; +- }; +- +- pd_isp: power-domain@105c4140 { +- compatible = "samsung,exynos5433-pd"; +- reg = <0x105c4140 0x20>; +- #power-domain-cells = <0>; +- power-domains = <&pd_cam0>; +- label = "ISP"; +- }; +- +- pd_mfc: power-domain@105c4180 { +- compatible = "samsung,exynos5433-pd"; +- reg = <0x105c4180 0x20>; +- #power-domain-cells = <0>; +- label = "MFC"; +- }; +- +- pd_hevc: power-domain@105c41c0 { +- compatible = "samsung,exynos5433-pd"; +- reg = <0x105c41c0 0x20>; +- #power-domain-cells = <0>; +- label = "HEVC"; +- }; +- +- tmu_atlas0: tmu@10060000 { +- compatible = "samsung,exynos5433-tmu"; +- reg = <0x10060000 0x200>; +- interrupts = ; +- clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, +- <&cmu_peris CLK_SCLK_TMU0>; +- clock-names = "tmu_apbif", "tmu_sclk"; +- #thermal-sensor-cells = <0>; +- status = "disabled"; +- }; +- +- tmu_atlas1: tmu@10068000 { +- compatible = "samsung,exynos5433-tmu"; +- reg = <0x10068000 0x200>; +- interrupts = ; +- clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, +- <&cmu_peris CLK_SCLK_TMU0>; +- clock-names = "tmu_apbif", "tmu_sclk"; +- #thermal-sensor-cells = <0>; +- status = "disabled"; +- }; +- +- tmu_g3d: tmu@10070000 { +- compatible = "samsung,exynos5433-tmu"; +- reg = <0x10070000 0x200>; +- interrupts = ; +- clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, +- <&cmu_peris CLK_SCLK_TMU1>; +- clock-names = "tmu_apbif", "tmu_sclk"; +- #thermal-sensor-cells = <0>; +- status = "disabled"; +- }; +- +- tmu_apollo: tmu@10078000 { +- compatible = "samsung,exynos5433-tmu"; +- reg = <0x10078000 0x200>; +- interrupts = ; +- clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, +- <&cmu_peris CLK_SCLK_TMU1>; +- clock-names = "tmu_apbif", "tmu_sclk"; +- #thermal-sensor-cells = <0>; +- status = "disabled"; +- }; +- +- tmu_isp: tmu@1007c000 { +- compatible = "samsung,exynos5433-tmu"; +- reg = <0x1007c000 0x200>; +- interrupts = ; +- clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, +- <&cmu_peris CLK_SCLK_TMU1>; +- clock-names = "tmu_apbif", "tmu_sclk"; +- #thermal-sensor-cells = <0>; +- status = "disabled"; +- }; +- +- timer@101c0000 { +- compatible = "samsung,exynos4210-mct"; +- reg = <0x101c0000 0x800>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>; +- clock-names = "fin_pll", "mct"; +- }; +- +- ppmu_d0_cpu: ppmu@10480000 { +- compatible = "samsung,exynos-ppmu-v2"; +- reg = <0x10480000 0x2000>; +- status = "disabled"; +- }; +- +- ppmu_d0_general: ppmu@10490000 { +- compatible = "samsung,exynos-ppmu-v2"; +- reg = <0x10490000 0x2000>; +- status = "disabled"; +- }; +- +- ppmu_d1_cpu: ppmu@104b0000 { +- compatible = "samsung,exynos-ppmu-v2"; +- reg = <0x104b0000 0x2000>; +- status = "disabled"; +- }; +- +- ppmu_d1_general: ppmu@104c0000 { +- compatible = "samsung,exynos-ppmu-v2"; +- reg = <0x104c0000 0x2000>; +- status = "disabled"; +- }; +- +- pinctrl_alive: pinctrl@10580000 { +- compatible = "samsung,exynos5433-pinctrl"; +- reg = <0x10580000 0x1a20>, <0x11090000 0x100>; +- +- wakeup-interrupt-controller { +- compatible = "samsung,exynos7-wakeup-eint"; +- interrupts = ; +- }; +- }; +- +- pinctrl_aud: pinctrl@114b0000 { +- compatible = "samsung,exynos5433-pinctrl"; +- reg = <0x114b0000 0x1000>; +- interrupts = ; +- power-domains = <&pd_aud>; +- }; +- +- pinctrl_cpif: pinctrl@10fe0000 { +- compatible = "samsung,exynos5433-pinctrl"; +- reg = <0x10fe0000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_ese: pinctrl@14ca0000 { +- compatible = "samsung,exynos5433-pinctrl"; +- reg = <0x14ca0000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_finger: pinctrl@14cb0000 { +- compatible = "samsung,exynos5433-pinctrl"; +- reg = <0x14cb0000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_fsys: pinctrl@15690000 { +- compatible = "samsung,exynos5433-pinctrl"; +- reg = <0x15690000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_imem: pinctrl@11090000 { +- compatible = "samsung,exynos5433-pinctrl"; +- reg = <0x11090000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_nfc: pinctrl@14cd0000 { +- compatible = "samsung,exynos5433-pinctrl"; +- reg = <0x14cd0000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_peric: pinctrl@14cc0000 { +- compatible = "samsung,exynos5433-pinctrl"; +- reg = <0x14cc0000 0x1100>; +- interrupts = ; +- }; +- +- pinctrl_touch: pinctrl@14ce0000 { +- compatible = "samsung,exynos5433-pinctrl"; +- reg = <0x14ce0000 0x1100>; +- interrupts = ; +- }; +- +- pmu_system_controller: system-controller@105c0000 { +- compatible = "samsung,exynos5433-pmu", "syscon"; +- reg = <0x105c0000 0x5008>; +- #clock-cells = <1>; +- clock-names = "clkout16"; +- clocks = <&xxti>; +- +- reboot: syscon-reboot { +- compatible = "syscon-reboot"; +- regmap = <&pmu_system_controller>; +- offset = <0x400>; /* SWRESET */ +- mask = <0x1>; +- }; +- }; +- +- gic: interrupt-controller@11001000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x11001000 0x1000>, +- <0x11002000 0x2000>, +- <0x11004000 0x2000>, +- <0x11006000 0x2000>; +- interrupts = ; +- }; +- +- mipi_phy: video-phy { +- compatible = "samsung,exynos5433-mipi-video-phy"; +- #phy-cells = <1>; +- samsung,pmu-syscon = <&pmu_system_controller>; +- samsung,cam0-sysreg = <&syscon_cam0>; +- samsung,cam1-sysreg = <&syscon_cam1>; +- samsung,disp-sysreg = <&syscon_disp>; +- }; +- +- decon: decon@13800000 { +- compatible = "samsung,exynos5433-decon"; +- reg = <0x13800000 0x2104>; +- clocks = <&cmu_disp CLK_PCLK_DECON>, +- <&cmu_disp CLK_ACLK_DECON>, +- <&cmu_disp CLK_ACLK_SMMU_DECON0X>, +- <&cmu_disp CLK_ACLK_XIU_DECON0X>, +- <&cmu_disp CLK_PCLK_SMMU_DECON0X>, +- <&cmu_disp CLK_ACLK_SMMU_DECON1X>, +- <&cmu_disp CLK_ACLK_XIU_DECON1X>, +- <&cmu_disp CLK_PCLK_SMMU_DECON1X>, +- <&cmu_disp CLK_SCLK_DECON_VCLK>, +- <&cmu_disp CLK_SCLK_DECON_ECLK>, +- <&cmu_disp CLK_SCLK_DSD>; +- clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", +- "aclk_xiu_decon0x", "pclk_smmu_decon0x", +- "aclk_smmu_decon1x", "aclk_xiu_decon1x", +- "pclk_smmu_decon1x", "sclk_decon_vclk", +- "sclk_decon_eclk", "dsd"; +- power-domains = <&pd_disp>; +- interrupt-names = "fifo", "vsync", "lcd_sys"; +- interrupts = , +- , +- ; +- samsung,disp-sysreg = <&syscon_disp>; +- status = "disabled"; +- iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>; +- iommu-names = "m0", "m1"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- decon_to_mic: endpoint { +- remote-endpoint = +- <&mic_to_decon>; +- }; +- }; +- }; +- }; +- +- decon_tv: decon@13880000 { +- compatible = "samsung,exynos5433-decon-tv"; +- reg = <0x13880000 0x20b8>; +- clocks = <&cmu_disp CLK_PCLK_DECON_TV>, +- <&cmu_disp CLK_ACLK_DECON_TV>, +- <&cmu_disp CLK_ACLK_SMMU_TV0X>, +- <&cmu_disp CLK_ACLK_XIU_TV0X>, +- <&cmu_disp CLK_PCLK_SMMU_TV0X>, +- <&cmu_disp CLK_ACLK_SMMU_TV1X>, +- <&cmu_disp CLK_ACLK_XIU_TV1X>, +- <&cmu_disp CLK_PCLK_SMMU_TV1X>, +- <&cmu_disp CLK_SCLK_DECON_TV_VCLK>, +- <&cmu_disp CLK_SCLK_DECON_TV_ECLK>, +- <&cmu_disp CLK_SCLK_DSD>; +- clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", +- "aclk_xiu_decon0x", "pclk_smmu_decon0x", +- "aclk_smmu_decon1x", "aclk_xiu_decon1x", +- "pclk_smmu_decon1x", "sclk_decon_vclk", +- "sclk_decon_eclk", "dsd"; +- samsung,disp-sysreg = <&syscon_disp>; +- power-domains = <&pd_disp>; +- interrupt-names = "fifo", "vsync", "lcd_sys"; +- interrupts = , +- , +- ; +- status = "disabled"; +- iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>; +- iommu-names = "m0", "m1"; +- }; +- +- dsi: dsi@13900000 { +- compatible = "samsung,exynos5433-mipi-dsi"; +- reg = <0x13900000 0xC0>; +- interrupts = ; +- phys = <&mipi_phy 1>; +- phy-names = "dsim"; +- clocks = <&cmu_disp CLK_PCLK_DSIM0>, +- <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>, +- <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>, +- <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>, +- <&cmu_disp CLK_SCLK_DSIM0>; +- clock-names = "bus_clk", +- "phyclk_mipidphy0_bitclkdiv8", +- "phyclk_mipidphy0_rxclkesc0", +- "sclk_rgb_vclk_to_dsim0", +- "sclk_mipi"; +- power-domains = <&pd_disp>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dsi_to_mic: endpoint { +- remote-endpoint = <&mic_to_dsi>; +- }; +- }; +- }; +- }; +- +- mic: mic@13930000 { +- compatible = "samsung,exynos5433-mic"; +- reg = <0x13930000 0x48>; +- clocks = <&cmu_disp CLK_PCLK_MIC0>, +- <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>; +- clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0"; +- power-domains = <&pd_disp>; +- samsung,disp-syscon = <&syscon_disp>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- mic_to_decon: endpoint { +- remote-endpoint = +- <&decon_to_mic>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- mic_to_dsi: endpoint { +- remote-endpoint = <&dsi_to_mic>; +- }; +- }; +- }; +- }; +- +- hdmi: hdmi@13970000 { +- compatible = "samsung,exynos5433-hdmi"; +- reg = <0x13970000 0x70000>; +- interrupts = ; +- clocks = <&cmu_disp CLK_PCLK_HDMI>, +- <&cmu_disp CLK_PCLK_HDMIPHY>, +- <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>, +- <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>, +- <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>, +- <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>, +- <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>, +- <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>, +- <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>; +- clock-names = "hdmi_pclk", "hdmi_i_pclk", +- "i_tmds_clk", "i_pixel_clk", +- "tmds_clko", "tmds_clko_user", +- "pixel_clko", "pixel_clko_user", +- "oscclk", "i_spdif_clk"; +- phy = <&hdmiphy>; +- ddc = <&hsi2c_11>; +- samsung,syscon-phandle = <&pmu_system_controller>; +- samsung,sysreg-phandle = <&syscon_disp>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- hdmiphy: hdmiphy@13af0000 { +- reg = <0x13af0000 0x80>; +- }; +- +- syscon_disp: syscon@13b80000 { +- compatible = "samsung,exynos5433-sysreg", "syscon"; +- reg = <0x13b80000 0x1010>; +- }; +- +- syscon_cam0: syscon@120f0000 { +- compatible = "samsung,exynos5433-sysreg", "syscon"; +- reg = <0x120f0000 0x1020>; +- }; +- +- syscon_cam1: syscon@145f0000 { +- compatible = "samsung,exynos5433-sysreg", "syscon"; +- reg = <0x145f0000 0x1038>; +- }; +- +- syscon_fsys: syscon@156f0000 { +- compatible = "syscon"; +- reg = <0x156f0000 0x1044>; +- }; +- +- gsc_0: video-scaler@13c00000 { +- compatible = "samsung,exynos5433-gsc"; +- reg = <0x13c00000 0x1000>; +- interrupts = ; +- clock-names = "pclk", "aclk", "aclk_xiu", +- "aclk_gsclbend", "gsd"; +- clocks = <&cmu_gscl CLK_PCLK_GSCL0>, +- <&cmu_gscl CLK_ACLK_GSCL0>, +- <&cmu_gscl CLK_ACLK_XIU_GSCLX>, +- <&cmu_gscl CLK_ACLK_GSCLBEND_333>, +- <&cmu_gscl CLK_ACLK_GSD>; +- iommus = <&sysmmu_gscl0>; +- power-domains = <&pd_gscl>; +- }; +- +- gsc_1: video-scaler@13c10000 { +- compatible = "samsung,exynos5433-gsc"; +- reg = <0x13c10000 0x1000>; +- interrupts = ; +- clock-names = "pclk", "aclk", "aclk_xiu", +- "aclk_gsclbend", "gsd"; +- clocks = <&cmu_gscl CLK_PCLK_GSCL1>, +- <&cmu_gscl CLK_ACLK_GSCL1>, +- <&cmu_gscl CLK_ACLK_XIU_GSCLX>, +- <&cmu_gscl CLK_ACLK_GSCLBEND_333>, +- <&cmu_gscl CLK_ACLK_GSD>; +- iommus = <&sysmmu_gscl1>; +- power-domains = <&pd_gscl>; +- }; +- +- gsc_2: video-scaler@13c20000 { +- compatible = "samsung,exynos5433-gsc"; +- reg = <0x13c20000 0x1000>; +- interrupts = ; +- clock-names = "pclk", "aclk", "aclk_xiu", +- "aclk_gsclbend", "gsd"; +- clocks = <&cmu_gscl CLK_PCLK_GSCL2>, +- <&cmu_gscl CLK_ACLK_GSCL2>, +- <&cmu_gscl CLK_ACLK_XIU_GSCLX>, +- <&cmu_gscl CLK_ACLK_GSCLBEND_333>, +- <&cmu_gscl CLK_ACLK_GSD>; +- iommus = <&sysmmu_gscl2>; +- power-domains = <&pd_gscl>; +- }; +- +- gpu: gpu@14ac0000 { +- compatible = "samsung,exynos5433-mali", "arm,mali-t760"; +- reg = <0x14ac0000 0x5000>; +- interrupts = , +- , +- ; +- interrupt-names = "job", "mmu", "gpu"; +- clocks = <&cmu_g3d CLK_ACLK_G3D>; +- clock-names = "core"; +- power-domains = <&pd_g3d>; +- operating-points-v2 = <&gpu_opp_table>; +- status = "disabled"; +- +- gpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-160000000 { +- opp-hz = /bits/ 64 <160000000>; +- opp-microvolt = <1000000>; +- }; +- opp-267000000 { +- opp-hz = /bits/ 64 <267000000>; +- opp-microvolt = <1000000>; +- }; +- opp-350000000 { +- opp-hz = /bits/ 64 <350000000>; +- opp-microvolt = <1025000>; +- }; +- opp-420000000 { +- opp-hz = /bits/ 64 <420000000>; +- opp-microvolt = <1025000>; +- }; +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <1075000>; +- }; +- opp-550000000 { +- opp-hz = /bits/ 64 <550000000>; +- opp-microvolt = <1125000>; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <1150000>; +- }; +- opp-700000000 { +- opp-hz = /bits/ 64 <700000000>; +- opp-microvolt = <1150000>; +- }; +- }; +- }; +- +- scaler_0: scaler@15000000 { +- compatible = "samsung,exynos5433-scaler"; +- reg = <0x15000000 0x1294>; +- interrupts = <0 402 IRQ_TYPE_LEVEL_HIGH>; +- clock-names = "pclk", "aclk", "aclk_xiu"; +- clocks = <&cmu_mscl CLK_PCLK_M2MSCALER0>, +- <&cmu_mscl CLK_ACLK_M2MSCALER0>, +- <&cmu_mscl CLK_ACLK_XIU_MSCLX>; +- iommus = <&sysmmu_scaler_0>; +- power-domains = <&pd_mscl>; +- }; +- +- scaler_1: scaler@15010000 { +- compatible = "samsung,exynos5433-scaler"; +- reg = <0x15010000 0x1294>; +- interrupts = <0 403 IRQ_TYPE_LEVEL_HIGH>; +- clock-names = "pclk", "aclk", "aclk_xiu"; +- clocks = <&cmu_mscl CLK_PCLK_M2MSCALER1>, +- <&cmu_mscl CLK_ACLK_M2MSCALER1>, +- <&cmu_mscl CLK_ACLK_XIU_MSCLX>; +- iommus = <&sysmmu_scaler_1>; +- power-domains = <&pd_mscl>; +- }; +- +- jpeg: codec@15020000 { +- compatible = "samsung,exynos5433-jpeg"; +- reg = <0x15020000 0x10000>; +- interrupts = ; +- clock-names = "pclk", "aclk", "aclk_xiu", "sclk"; +- clocks = <&cmu_mscl CLK_PCLK_JPEG>, +- <&cmu_mscl CLK_ACLK_JPEG>, +- <&cmu_mscl CLK_ACLK_XIU_MSCLX>, +- <&cmu_mscl CLK_SCLK_JPEG>; +- iommus = <&sysmmu_jpeg>; +- power-domains = <&pd_mscl>; +- }; +- +- mfc: codec@152e0000 { +- compatible = "samsung,exynos5433-mfc"; +- reg = <0x152E0000 0x10000>; +- interrupts = ; +- clock-names = "pclk", "aclk", "aclk_xiu"; +- clocks = <&cmu_mfc CLK_PCLK_MFC>, +- <&cmu_mfc CLK_ACLK_MFC>, +- <&cmu_mfc CLK_ACLK_XIU_MFCX>; +- iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>; +- iommu-names = "left", "right"; +- power-domains = <&pd_mfc>; +- }; +- +- sysmmu_decon0x: sysmmu@13a00000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13a00000 0x1000>; +- interrupts = ; +- clock-names = "aclk", "pclk"; +- clocks = <&cmu_disp CLK_ACLK_SMMU_DECON0X>, +- <&cmu_disp CLK_PCLK_SMMU_DECON0X>; +- power-domains = <&pd_disp>; +- #iommu-cells = <0>; +- }; +- +- sysmmu_decon1x: sysmmu@13a10000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13a10000 0x1000>; +- interrupts = ; +- clock-names = "aclk", "pclk"; +- clocks = <&cmu_disp CLK_ACLK_SMMU_DECON1X>, +- <&cmu_disp CLK_PCLK_SMMU_DECON1X>; +- #iommu-cells = <0>; +- power-domains = <&pd_disp>; +- }; +- +- sysmmu_tv0x: sysmmu@13a20000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13a20000 0x1000>; +- interrupts = ; +- clock-names = "aclk", "pclk"; +- clocks = <&cmu_disp CLK_ACLK_SMMU_TV0X>, +- <&cmu_disp CLK_PCLK_SMMU_TV0X>; +- #iommu-cells = <0>; +- power-domains = <&pd_disp>; +- }; +- +- sysmmu_tv1x: sysmmu@13a30000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13a30000 0x1000>; +- interrupts = ; +- clock-names = "aclk", "pclk"; +- clocks = <&cmu_disp CLK_ACLK_SMMU_TV1X>, +- <&cmu_disp CLK_PCLK_SMMU_TV1X>; +- #iommu-cells = <0>; +- power-domains = <&pd_disp>; +- }; +- +- sysmmu_gscl0: sysmmu@13c80000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13C80000 0x1000>; +- interrupts = ; +- clock-names = "aclk", "pclk"; +- clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>, +- <&cmu_gscl CLK_PCLK_SMMU_GSCL0>; +- #iommu-cells = <0>; +- power-domains = <&pd_gscl>; +- }; +- +- sysmmu_gscl1: sysmmu@13c90000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13C90000 0x1000>; +- interrupts = ; +- clock-names = "aclk", "pclk"; +- clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>, +- <&cmu_gscl CLK_PCLK_SMMU_GSCL1>; +- #iommu-cells = <0>; +- power-domains = <&pd_gscl>; +- }; +- +- sysmmu_gscl2: sysmmu@13ca0000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x13CA0000 0x1000>; +- interrupts = ; +- clock-names = "aclk", "pclk"; +- clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>, +- <&cmu_gscl CLK_PCLK_SMMU_GSCL2>; +- #iommu-cells = <0>; +- power-domains = <&pd_gscl>; +- }; +- +- sysmmu_scaler_0: sysmmu@15040000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x15040000 0x1000>; +- interrupts = ; +- clock-names = "aclk", "pclk"; +- clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>, +- <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>; +- #iommu-cells = <0>; +- power-domains = <&pd_mscl>; +- }; +- +- sysmmu_scaler_1: sysmmu@15050000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x15050000 0x1000>; +- interrupts = ; +- clock-names = "aclk", "pclk"; +- clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>, +- <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>; +- #iommu-cells = <0>; +- power-domains = <&pd_mscl>; +- }; +- +- sysmmu_jpeg: sysmmu@15060000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x15060000 0x1000>; +- interrupts = ; +- clock-names = "aclk", "pclk"; +- clocks = <&cmu_mscl CLK_ACLK_SMMU_JPEG>, +- <&cmu_mscl CLK_PCLK_SMMU_JPEG>; +- #iommu-cells = <0>; +- power-domains = <&pd_mscl>; +- }; +- +- sysmmu_mfc_0: sysmmu@15200000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x15200000 0x1000>; +- interrupts = ; +- clock-names = "aclk", "pclk"; +- clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_0>, +- <&cmu_mfc CLK_PCLK_SMMU_MFC_0>; +- #iommu-cells = <0>; +- power-domains = <&pd_mfc>; +- }; +- +- sysmmu_mfc_1: sysmmu@15210000 { +- compatible = "samsung,exynos-sysmmu"; +- reg = <0x15210000 0x1000>; +- interrupts = ; +- clock-names = "aclk", "pclk"; +- clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_1>, +- <&cmu_mfc CLK_PCLK_SMMU_MFC_1>; +- #iommu-cells = <0>; +- power-domains = <&pd_mfc>; +- }; +- +- serial_0: serial@14c10000 { +- compatible = "samsung,exynos5433-uart"; +- reg = <0x14c10000 0x100>; +- interrupts = ; +- clocks = <&cmu_peric CLK_PCLK_UART0>, +- <&cmu_peric CLK_SCLK_UART0>; +- clock-names = "uart", "clk_uart_baud0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_bus>; +- status = "disabled"; +- }; +- +- serial_1: serial@14c20000 { +- compatible = "samsung,exynos5433-uart"; +- reg = <0x14c20000 0x100>; +- interrupts = ; +- clocks = <&cmu_peric CLK_PCLK_UART1>, +- <&cmu_peric CLK_SCLK_UART1>; +- clock-names = "uart", "clk_uart_baud0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_bus>; +- status = "disabled"; +- }; +- +- serial_2: serial@14c30000 { +- compatible = "samsung,exynos5433-uart"; +- reg = <0x14c30000 0x100>; +- interrupts = ; +- clocks = <&cmu_peric CLK_PCLK_UART2>, +- <&cmu_peric CLK_SCLK_UART2>; +- clock-names = "uart", "clk_uart_baud0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_bus>; +- status = "disabled"; +- }; +- +- spi_0: spi@14d20000 { +- compatible = "samsung,exynos5433-spi"; +- reg = <0x14d20000 0x100>; +- interrupts = ; +- dmas = <&pdma0 9>, <&pdma0 8>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cmu_peric CLK_PCLK_SPI0>, +- <&cmu_peric CLK_SCLK_SPI0>, +- <&cmu_peric CLK_SCLK_IOCLK_SPI0>; +- clock-names = "spi", "spi_busclk0", "spi_ioclk"; +- samsung,spi-src-clk = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_bus>; +- num-cs = <1>; +- status = "disabled"; +- }; +- +- spi_1: spi@14d30000 { +- compatible = "samsung,exynos5433-spi"; +- reg = <0x14d30000 0x100>; +- interrupts = ; +- dmas = <&pdma0 11>, <&pdma0 10>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cmu_peric CLK_PCLK_SPI1>, +- <&cmu_peric CLK_SCLK_SPI1>, +- <&cmu_peric CLK_SCLK_IOCLK_SPI1>; +- clock-names = "spi", "spi_busclk0", "spi_ioclk"; +- samsung,spi-src-clk = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_bus>; +- num-cs = <1>; +- status = "disabled"; +- }; +- +- spi_2: spi@14d40000 { +- compatible = "samsung,exynos5433-spi"; +- reg = <0x14d40000 0x100>; +- interrupts = ; +- dmas = <&pdma0 13>, <&pdma0 12>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cmu_peric CLK_PCLK_SPI2>, +- <&cmu_peric CLK_SCLK_SPI2>, +- <&cmu_peric CLK_SCLK_IOCLK_SPI2>; +- clock-names = "spi", "spi_busclk0", "spi_ioclk"; +- samsung,spi-src-clk = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_bus>; +- num-cs = <1>; +- status = "disabled"; +- }; +- +- spi_3: spi@14d50000 { +- compatible = "samsung,exynos5433-spi"; +- reg = <0x14d50000 0x100>; +- interrupts = ; +- dmas = <&pdma0 23>, <&pdma0 22>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cmu_peric CLK_PCLK_SPI3>, +- <&cmu_peric CLK_SCLK_SPI3>, +- <&cmu_peric CLK_SCLK_IOCLK_SPI3>; +- clock-names = "spi", "spi_busclk0", "spi_ioclk"; +- samsung,spi-src-clk = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi3_bus>; +- num-cs = <1>; +- status = "disabled"; +- }; +- +- spi_4: spi@14d00000 { +- compatible = "samsung,exynos5433-spi"; +- reg = <0x14d00000 0x100>; +- interrupts = ; +- dmas = <&pdma0 25>, <&pdma0 24>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cmu_peric CLK_PCLK_SPI4>, +- <&cmu_peric CLK_SCLK_SPI4>, +- <&cmu_peric CLK_SCLK_IOCLK_SPI4>; +- clock-names = "spi", "spi_busclk0", "spi_ioclk"; +- samsung,spi-src-clk = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi4_bus>; +- num-cs = <1>; +- status = "disabled"; +- }; +- +- adc: adc@14d10000 { +- compatible = "samsung,exynos7-adc"; +- reg = <0x14d10000 0x100>; +- interrupts = ; +- clock-names = "adc"; +- clocks = <&cmu_peric CLK_PCLK_ADCIF>; +- #io-channel-cells = <1>; +- status = "disabled"; +- }; +- +- i2s1: i2s@14d60000 { +- compatible = "samsung,exynos7-i2s"; +- reg = <0x14d60000 0x100>; +- dmas = <&pdma0 31>, <&pdma0 30>; +- dma-names = "tx", "rx"; +- interrupts = ; +- clocks = <&cmu_peric CLK_PCLK_I2S1>, +- <&cmu_peric CLK_PCLK_I2S1>, +- <&cmu_peric CLK_SCLK_I2S1>; +- clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; +- #clock-cells = <1>; +- #sound-dai-cells = <1>; +- status = "disabled"; +- }; +- +- pwm: pwm@14dd0000 { +- compatible = "samsung,exynos4210-pwm"; +- reg = <0x14dd0000 0x100>; +- interrupts = , +- , +- , +- , +- ; +- samsung,pwm-outputs = <0>, <1>, <2>, <3>; +- clocks = <&cmu_peric CLK_PCLK_PWM>; +- clock-names = "timers"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- hsi2c_0: hsi2c@14e40000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x14e40000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c0_bus>; +- clocks = <&cmu_peric CLK_PCLK_HSI2C0>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_1: hsi2c@14e50000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x14e50000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c1_bus>; +- clocks = <&cmu_peric CLK_PCLK_HSI2C1>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_2: hsi2c@14e60000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x14e60000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c2_bus>; +- clocks = <&cmu_peric CLK_PCLK_HSI2C2>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_3: hsi2c@14e70000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x14e70000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c3_bus>; +- clocks = <&cmu_peric CLK_PCLK_HSI2C3>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_4: hsi2c@14ec0000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x14ec0000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c4_bus>; +- clocks = <&cmu_peric CLK_PCLK_HSI2C4>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_5: hsi2c@14ed0000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x14ed0000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c5_bus>; +- clocks = <&cmu_peric CLK_PCLK_HSI2C5>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_6: hsi2c@14ee0000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x14ee0000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c6_bus>; +- clocks = <&cmu_peric CLK_PCLK_HSI2C6>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_7: hsi2c@14ef0000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x14ef0000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c7_bus>; +- clocks = <&cmu_peric CLK_PCLK_HSI2C7>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_8: hsi2c@14d90000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x14d90000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c8_bus>; +- clocks = <&cmu_peric CLK_PCLK_HSI2C8>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_9: hsi2c@14da0000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x14da0000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c9_bus>; +- clocks = <&cmu_peric CLK_PCLK_HSI2C9>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_10: hsi2c@14de0000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x14de0000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c10_bus>; +- clocks = <&cmu_peric CLK_PCLK_HSI2C10>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_11: hsi2c@14df0000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x14df0000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c11_bus>; +- clocks = <&cmu_peric CLK_PCLK_HSI2C11>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- usbdrd30: usbdrd { +- compatible = "samsung,exynos5433-dwusb3"; +- clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, +- <&cmu_fsys CLK_SCLK_USBDRD30>, +- <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>, +- <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>; +- clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- +- usbdrd_dwc3: usb@15400000 { +- compatible = "snps,dwc3"; +- clocks = <&cmu_fsys CLK_SCLK_USBDRD30>, +- <&cmu_fsys CLK_ACLK_USBDRD30>, +- <&cmu_fsys CLK_SCLK_USBDRD30>; +- clock-names = "ref", "bus_early", "suspend"; +- reg = <0x15400000 0x10000>; +- interrupts = ; +- phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>; +- phy-names = "usb2-phy", "usb3-phy"; +- }; +- }; +- +- usbdrd30_phy: phy@15500000 { +- compatible = "samsung,exynos5433-usbdrd-phy"; +- reg = <0x15500000 0x100>; +- clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>, +- <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>, +- <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>, +- <&cmu_fsys CLK_SCLK_USBDRD30>; +- clock-names = "phy", "ref", "phy_utmi", "phy_pipe", +- "itp"; +- #phy-cells = <1>; +- samsung,pmu-syscon = <&pmu_system_controller>; +- status = "disabled"; +- }; +- +- usbhost30_phy: phy@15580000 { +- compatible = "samsung,exynos5433-usbdrd-phy"; +- reg = <0x15580000 0x100>; +- clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>, +- <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>, +- <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>, +- <&cmu_fsys CLK_SCLK_USBHOST30>; +- clock-names = "phy", "ref", "phy_utmi", "phy_pipe", +- "itp"; +- #phy-cells = <1>; +- samsung,pmu-syscon = <&pmu_system_controller>; +- status = "disabled"; +- }; +- +- usbhost30: usbhost { +- compatible = "samsung,exynos5433-dwusb3"; +- clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, +- <&cmu_fsys CLK_SCLK_USBHOST30>, +- <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>, +- <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>; +- clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- +- usbhost_dwc3: usb@15a00000 { +- compatible = "snps,dwc3"; +- clocks = <&cmu_fsys CLK_SCLK_USBHOST30>, +- <&cmu_fsys CLK_ACLK_USBHOST30>, +- <&cmu_fsys CLK_SCLK_USBHOST30>; +- clock-names = "ref", "bus_early", "suspend"; +- reg = <0x15a00000 0x10000>; +- interrupts = ; +- phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>; +- phy-names = "usb2-phy", "usb3-phy"; +- }; +- }; +- +- mshc_0: mshc@15540000 { +- compatible = "samsung,exynos7-dw-mshc-smu"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x15540000 0x2000>; +- clocks = <&cmu_fsys CLK_ACLK_MMC0>, +- <&cmu_fsys CLK_SCLK_MMC0>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x40>; +- status = "disabled"; +- }; +- +- mshc_1: mshc@15550000 { +- compatible = "samsung,exynos7-dw-mshc-smu"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x15550000 0x2000>; +- clocks = <&cmu_fsys CLK_ACLK_MMC1>, +- <&cmu_fsys CLK_SCLK_MMC1>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x40>; +- status = "disabled"; +- }; +- +- mshc_2: mshc@15560000 { +- compatible = "samsung,exynos7-dw-mshc-smu"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x15560000 0x2000>; +- clocks = <&cmu_fsys CLK_ACLK_MMC2>, +- <&cmu_fsys CLK_SCLK_MMC2>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x40>; +- status = "disabled"; +- }; +- +- pdma0: pdma@15610000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x15610000 0x1000>; +- interrupts = ; +- clocks = <&cmu_fsys CLK_PDMA0>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- }; +- +- pdma1: pdma@15600000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x15600000 0x1000>; +- interrupts = ; +- clocks = <&cmu_fsys CLK_PDMA1>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- }; +- +- audio-subsystem@11400000 { +- compatible = "samsung,exynos5433-lpass"; +- reg = <0x11400000 0x100>, <0x11500000 0x08>; +- clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>; +- clock-names = "sfr0_ctrl"; +- samsung,pmu-syscon = <&pmu_system_controller>; +- power-domains = <&pd_aud>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- adma: adma@11420000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x11420000 0x1000>; +- interrupts = ; +- clocks = <&cmu_aud CLK_ACLK_DMAC>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- power-domains = <&pd_aud>; +- }; +- +- i2s0: i2s@11440000 { +- compatible = "samsung,exynos7-i2s"; +- reg = <0x11440000 0x100>; +- dmas = <&adma 0>, <&adma 2>; +- dma-names = "tx", "rx"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cmu_aud CLK_PCLK_AUD_I2S>, +- <&cmu_aud CLK_SCLK_AUD_I2S>, +- <&cmu_aud CLK_SCLK_I2S_BCLK>; +- clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; +- #clock-cells = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s0_bus>; +- power-domains = <&pd_aud>; +- #sound-dai-cells = <1>; +- status = "disabled"; +- }; +- +- serial_3: serial@11460000 { +- compatible = "samsung,exynos5433-uart"; +- reg = <0x11460000 0x100>; +- interrupts = ; +- clocks = <&cmu_aud CLK_PCLK_AUD_UART>, +- <&cmu_aud CLK_SCLK_AUD_UART>; +- clock-names = "uart", "clk_uart_baud0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart_aud_bus>; +- power-domains = <&pd_aud>; +- status = "disabled"; +- }; +- }; +- +- pcie_phy: pcie-phy@15680000 { +- compatible = "samsung,exynos5433-pcie-phy"; +- reg = <0x15680000 0x1000>; +- samsung,pmu-syscon = <&pmu_system_controller>; +- samsung,fsys-sysreg = <&syscon_fsys>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- pcie: pcie@15700000 { +- compatible = "samsung,exynos5433-pcie"; +- reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, +- <0x0c000000 0x1000>; +- reg-names = "dbi", "elbi", "config"; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- interrupts = ; +- clocks = <&cmu_fsys CLK_PCIE>, +- <&cmu_fsys CLK_PCLK_PCIE_PHY>; +- clock-names = "pcie", "pcie_bus"; +- num-lanes = <1>; +- num-viewport = <3>; +- bus-range = <0x00 0xff>; +- phys = <&pcie_phy>; +- ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, +- <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; +- status = "disabled"; +- }; +- }; +- +- timer: timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +-}; +- +-#include "exynos5433-bus.dtsi" +-#include "exynos5433-pinctrl.dtsi" +-#include "exynos5433-tmu.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/exynos/exynos7-espresso.dts b/scripts/dtc/include-prefixes/arm64/exynos/exynos7-espresso.dts +deleted file mode 100644 +index 125c03f351d9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/exynos/exynos7-espresso.dts ++++ /dev/null +@@ -1,418 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung Exynos7 Espresso board device tree source +- * +- * Copyright (c) 2014 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-/dts-v1/; +-#include "exynos7.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "Samsung Exynos7 Espresso board based on Exynos7"; +- compatible = "samsung,exynos7-espresso", "samsung,exynos7"; +- +- aliases { +- serial0 = &serial_2; +- mshc0 = &mmc_0; +- mshc2 = &mmc_2; +- }; +- +- chosen { +- stdout-path = &serial_2; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x0 0x40000000 0x0 0xC0000000>; +- }; +- +- usb30_vbus_reg: regulator-usb30 { +- compatible = "regulator-fixed"; +- regulator-name = "VBUS_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gph1 1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb30_vbus_en>; +- enable-active-high; +- }; +- +- usb3drd_boost_5v: regulator-usb3drd-boost { +- compatible = "regulator-fixed"; +- regulator-name = "VUSB_VBUS_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpf4 1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb3drd_boost_en>; +- enable-active-high; +- }; +- +-}; +- +-&fin_pll { +- clock-frequency = <24000000>; +-}; +- +-&gpu { +- mali-supply = <&buck6_reg>; +- status = "okay"; +-}; +- +-&serial_2 { +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +- clocks = <&clock_ccore PCLK_RTC>, <&s2mps15_osc S2MPS11_CLK_AP>; +- clock-names = "rtc", "rtc_src"; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-&adc { +- status = "okay"; +-}; +- +-&hsi2c_4 { +- samsung,i2c-sda-delay = <100>; +- samsung,i2c-max-bus-freq = <200000>; +- status = "okay"; +- +- pmic@66 { +- compatible = "samsung,s2mps15-pmic"; +- reg = <0x66>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- interrupt-parent = <&gpa0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_irq>; +- wakeup-source; +- +- s2mps15_osc: clocks { +- compatible = "samsung,s2mps13-clk"; +- #clock-cells = <1>; +- clock-output-names = "s2mps13_ap", "s2mps13_cp", +- "s2mps13_bt"; +- }; +- +- regulators { +- ldo1_reg: LDO1 { +- regulator-name = "vdd_ldo1"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <900000>; +- regulator-always-on; +- regulator-enable-ramp-delay = <125>; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "vqmmc-sdcard"; +- regulator-min-microvolt = <1620000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-enable-ramp-delay = <125>; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "vdd_ldo3"; +- regulator-min-microvolt = <1620000>; +- regulator-max-microvolt = <1980000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-enable-ramp-delay = <125>; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "vdd_ldo4"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1110000>; +- regulator-always-on; +- regulator-enable-ramp-delay = <125>; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "vdd_ldo5"; +- regulator-min-microvolt = <1620000>; +- regulator-max-microvolt = <1980000>; +- regulator-always-on; +- regulator-enable-ramp-delay = <125>; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "vdd_ldo6"; +- regulator-min-microvolt = <2250000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <125>; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "vdd_ldo7"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1150000>; +- regulator-enable-ramp-delay = <125>; +- regulator-always-on; +- }; +- +- ldo8_reg: LDO8 { +- regulator-name = "vdd_ldo8"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1000000>; +- regulator-enable-ramp-delay = <125>; +- }; +- +- ldo9_reg: LDO9 { +- regulator-name = "vdd_ldo9"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1000000>; +- regulator-enable-ramp-delay = <125>; +- }; +- +- ldo10_reg: LDO10 { +- regulator-name = "vdd_ldo10"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1000000>; +- regulator-enable-ramp-delay = <125>; +- }; +- +- ldo11_reg: LDO11 { +- regulator-name = "vdd_ldo11"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-enable-ramp-delay = <125>; +- }; +- +- ldo12_reg: LDO12 { +- regulator-name = "vdd_ldo12"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1300000>; +- regulator-enable-ramp-delay = <125>; +- regulator-always-on; +- }; +- +- ldo13_reg: LDO13 { +- regulator-name = "vdd_ldo13"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1300000>; +- regulator-always-on; +- regulator-enable-ramp-delay = <125>; +- }; +- +- ldo14_reg: LDO14 { +- regulator-name = "vdd_ldo14"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3375000>; +- regulator-enable-ramp-delay = <125>; +- }; +- +- ldo17_reg: LDO17 { +- regulator-name = "vmmc-sdcard"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3375000>; +- regulator-enable-ramp-delay = <125>; +- }; +- +- ldo18_reg: LDO18 { +- regulator-name = "vdd_ldo18"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <2275000>; +- regulator-enable-ramp-delay = <125>; +- }; +- +- ldo19_reg: LDO19 { +- regulator-name = "vdd_ldo19"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3375000>; +- regulator-enable-ramp-delay = <125>; +- }; +- +- ldo21_reg: LDO21 { +- regulator-name = "vdd_ldo21"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3375000>; +- regulator-enable-ramp-delay = <125>; +- }; +- +- ldo23_reg: LDO23 { +- regulator-name = "vdd_ldo23"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <2275000>; +- regulator-enable-ramp-delay = <125>; +- }; +- +- ldo25_reg: LDO25 { +- regulator-name = "vdd_ldo25"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3375000>; +- regulator-enable-ramp-delay = <125>; +- }; +- +- ldo26_reg: LDO26 { +- regulator-name = "vdd_ldo26"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1470000>; +- regulator-enable-ramp-delay = <125>; +- }; +- +- ldo27_reg: LDO27 { +- regulator-name = "vdd_ldo27"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <2275000>; +- regulator-enable-ramp-delay = <125>; +- }; +- +- buck1_reg: BUCK1 { +- regulator-name = "vdd_mif"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-ramp-delay = <25000>; +- regulator-enable-ramp-delay = <250>; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "vdd_atlas"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-ramp-delay = <12500>; +- regulator-enable-ramp-delay = <250>; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "vdd_int"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-ramp-delay = <12500>; +- regulator-enable-ramp-delay = <250>; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "vdd_buck5"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1300000>; +- regulator-ramp-delay = <25000>; +- regulator-enable-ramp-delay = <250>; +- }; +- +- buck6_reg: BUCK6 { +- regulator-name = "vdd_g3d"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1400000>; +- regulator-ramp-delay = <12500>; +- regulator-enable-ramp-delay = <250>; +- }; +- +- buck7_reg: BUCK7 { +- regulator-name = "vdd_buck7"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-ramp-delay = <25000>; +- regulator-enable-ramp-delay = <250>; +- }; +- +- buck8_reg: BUCK8 { +- regulator-name = "vdd_buck8"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-ramp-delay = <25000>; +- regulator-enable-ramp-delay = <250>; +- }; +- +- buck9_reg: BUCK9 { +- regulator-name = "vdd_buck9"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2100000>; +- regulator-always-on; +- regulator-ramp-delay = <25000>; +- regulator-enable-ramp-delay = <250>; +- }; +- +- buck10_reg: BUCK10 { +- regulator-name = "vdd_buck10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-ramp-delay = <25000>; +- regulator-enable-ramp-delay = <250>; +- }; +- }; +- }; +-}; +- +-&pinctrl_alive { +- pmic_irq: pmic-irq { +- samsung,pins = "gpa0-2"; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&mmc_0 { +- status = "okay"; +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +- non-removable; +- card-detect-delay = <200>; +- clock-frequency = <800000000>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <0 4>; +- samsung,dw-mshc-ddr-timing = <0 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4 &sd0_bus8>; +- bus-width = <8>; +-}; +- +-&mmc_2 { +- status = "okay"; +- cap-sd-highspeed; +- card-detect-delay = <200>; +- clock-frequency = <400000000>; +- samsung,dw-mshc-ciu-div = <3>; +- samsung,dw-mshc-sdr-timing = <2 3>; +- samsung,dw-mshc-ddr-timing = <1 2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; +- bus-width = <4>; +- vmmc-supply = <&ldo17_reg>; +- vqmmc-supply = <&ldo2_reg>; +- disable-wp; +-}; +- +-&pinctrl_bus1 { +- usb30_vbus_en: usb30-vbus-en { +- samsung,pins = "gph1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- usb3drd_boost_en: usb3drd-boost-en { +- samsung,pins = "gpf4-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&ufs { +- status = "okay"; +-}; +- +-&usbdrd_phy { +- vbus-supply = <&usb30_vbus_reg>; +- vbus-boost-supply = <&usb3drd_boost_5v>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/exynos/exynos7-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm64/exynos/exynos7-pinctrl.dtsi +deleted file mode 100644 +index 472dd649aa7e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/exynos/exynos7-pinctrl.dtsi ++++ /dev/null +@@ -1,702 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung's Exynos7 SoC pin-mux and pin-config device tree source +- * +- * Copyright (c) 2014 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * +- * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as +- * device tree nodes in this file. +- */ +- +-#include +- +-&pinctrl_alive { +- gpa0: gpa0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- interrupt-parent = <&gic>; +- #interrupt-cells = <2>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- }; +- +- gpa1: gpa1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- interrupt-parent = <&gic>; +- #interrupt-cells = <2>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- }; +- +- gpa2: gpa2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpa3: gpa3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +-}; +- +-&pinctrl_bus0 { +- gpb0: gpb0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc0: gpc0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc1: gpc1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc2: gpc2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpc3: gpc3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd0: gpd0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd1: gpd1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd2: gpd2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd4: gpd4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd5: gpd5 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd6: gpd6 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd7: gpd7 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpd8: gpd8 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg0: gpg0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg3: gpg3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- hs_i2c10_bus: hs-i2c10-bus { +- samsung,pins = "gpb0-1", "gpb0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hs_i2c11_bus: hs-i2c11-bus { +- samsung,pins = "gpb0-3", "gpb0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hs_i2c2_bus: hs-i2c2-bus { +- samsung,pins = "gpd0-3", "gpd0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart0_data: uart0-data { +- samsung,pins = "gpd0-0", "gpd0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart0_fctl: uart0-fctl { +- samsung,pins = "gpd0-2", "gpd0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart2_data: uart2-data { +- samsung,pins = "gpd1-4", "gpd1-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hs_i2c3_bus: hs-i2c3-bus { +- samsung,pins = "gpd1-3", "gpd1-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart1_data: uart1-data { +- samsung,pins = "gpd1-0", "gpd1-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart1_fctl: uart1-fctl { +- samsung,pins = "gpd1-2", "gpd1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hs_i2c0_bus: hs-i2c0-bus { +- samsung,pins = "gpd2-1", "gpd2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hs_i2c1_bus: hs-i2c1-bus { +- samsung,pins = "gpd2-3", "gpd2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hs_i2c9_bus: hs-i2c9-bus { +- samsung,pins = "gpd2-7", "gpd2-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm0_out: pwm0-out { +- samsung,pins = "gpd2-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm1_out: pwm1-out { +- samsung,pins = "gpd2-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm2_out: pwm2-out { +- samsung,pins = "gpd2-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- pwm3_out: pwm3-out { +- samsung,pins = "gpd2-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hs_i2c8_bus: hs-i2c8-bus { +- samsung,pins = "gpd5-3", "gpd5-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- uart3_data: uart3-data { +- samsung,pins = "gpd5-0", "gpd5-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi2_bus: spi2-bus { +- samsung,pins = "gpd5-0", "gpd5-1", "gpd5-2", "gpd5-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi1_bus: spi1-bus { +- samsung,pins = "gpd6-2", "gpd6-3", "gpd6-4", "gpd6-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- spi0_bus: spi0-bus { +- samsung,pins = "gpd8-0", "gpd8-1", "gpd6-0", "gpd6-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hs_i2c4_bus: hs-i2c4-bus { +- samsung,pins = "gpg3-1", "gpg3-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- hs_i2c5_bus: hs-i2c5-bus { +- samsung,pins = "gpg3-3", "gpg3-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_nfc { +- gpj0: gpj0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- hs_i2c6_bus: hs-i2c6-bus { +- samsung,pins = "gpj0-1", "gpj0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_touch { +- gpj1: gpj1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- hs_i2c7_bus: hs-i2c7-bus { +- samsung,pins = "gpj1-1", "gpj1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_ff { +- gpg4: gpg4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- spi3_bus: spi3-bus { +- samsung,pins = "gpg4-0", "gpg4-1", "gpg4-2", "gpg4-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_ese { +- gpv7: gpv7 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- spi4_bus: spi4-bus { +- samsung,pins = "gpv7-0", "gpv7-1", "gpv7-2", "gpv7-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_fsys0 { +- gpr4: gpr4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- sd2_clk: sd2-clk { +- samsung,pins = "gpr4-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cmd: sd2-cmd { +- samsung,pins = "gpr4-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_cd: sd2-cd { +- samsung,pins = "gpr4-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus1: sd2-bus-width1 { +- samsung,pins = "gpr4-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd2_bus4: sd2-bus-width4 { +- samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_fsys1 { +- gpr0: gpr0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpr1: gpr1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpr2: gpr2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpr3: gpr3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- sd0_clk: sd0-clk { +- samsung,pins = "gpr0-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_cmd: sd0-cmd { +- samsung,pins = "gpr0-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_ds: sd0-ds { +- samsung,pins = "gpr0-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_qrdy: sd0-qrdy { +- samsung,pins = "gpr0-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus1: sd0-bus-width1 { +- samsung,pins = "gpr1-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus4: sd0-bus-width4 { +- samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd0_bus8: sd0-bus-width8 { +- samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_clk: sd1-clk { +- samsung,pins = "gpr2-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_cmd: sd1-cmd { +- samsung,pins = "gpr2-1"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_ds: sd1-ds { +- samsung,pins = "gpr2-2"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_qrdy: sd1-qrdy { +- samsung,pins = "gpr2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_int: sd1-int { +- samsung,pins = "gpr2-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus1: sd1-bus-width1 { +- samsung,pins = "gpr3-0"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus4: sd1-bus-width4 { +- samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- sd1_bus8: sd1-bus-width8 { +- samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +- +-&pinctrl_bus1 { +- gpf0: gpf0 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf1: gpf1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf2: gpf2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf3: gpf3 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf4: gpf4 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpf5: gpf5 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg1: gpg1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpg2: gpg2 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gph1: gph1 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpv6: gpv6 { +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- spi5_bus: spi5-bus { +- samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- ufs_refclk_out: ufs-refclk-out { +- samsung,pins = "gpg2-4"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +- +- ufs_rst_n: ufs-rst-n { +- samsung,pins = "gph1-5"; +- samsung,pin-function = ; +- samsung,pin-pud = ; +- samsung,pin-drv = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/exynos/exynos7-trip-points.dtsi b/scripts/dtc/include-prefixes/arm64/exynos/exynos7-trip-points.dtsi +deleted file mode 100644 +index d3301b8bd364..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/exynos/exynos7-trip-points.dtsi ++++ /dev/null +@@ -1,50 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device tree sources for default Exynos7 thermal zone definition +- * +- * Copyright (c) 2016 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-trips { +- cpu-alert-0 { +- temperature = <75000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu-alert-1 { +- temperature = <80000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu-alert-2 { +- temperature = <85000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu-alert-3 { +- temperature = <90000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu-alert-4 { +- temperature = <95000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu-alert-5 { +- temperature = <100000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu-alert-6 { +- temperature = <110000>; /* millicelsius */ +- hysteresis = <10000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu-crit-0 { +- temperature = <115000>; /* millicelsius */ +- hysteresis = <0>; /* millicelsius */ +- type = "critical"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/exynos/exynos7.dtsi b/scripts/dtc/include-prefixes/arm64/exynos/exynos7.dtsi +deleted file mode 100644 +index c73a597ca66e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/exynos/exynos7.dtsi ++++ /dev/null +@@ -1,719 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Samsung Exynos7 SoC device tree source +- * +- * Copyright (c) 2014 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- */ +- +-#include +-#include +- +-/ { +- compatible = "samsung,exynos7"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- pinctrl0 = &pinctrl_alive; +- pinctrl1 = &pinctrl_bus0; +- pinctrl2 = &pinctrl_nfc; +- pinctrl3 = &pinctrl_touch; +- pinctrl4 = &pinctrl_ff; +- pinctrl5 = &pinctrl_ese; +- pinctrl6 = &pinctrl_fsys0; +- pinctrl7 = &pinctrl_fsys1; +- pinctrl8 = &pinctrl_bus1; +- tmuctrl0 = &tmuctrl_0; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a57-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>, +- <&cpu_atlas2>, <&cpu_atlas3>; +- }; +- +- fin_pll: clock { +- /* XXTI */ +- compatible = "fixed-clock"; +- clock-output-names = "fin_pll"; +- #clock-cells = <0>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu_atlas0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x0>; +- enable-method = "psci"; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&atlas_l2>; +- }; +- +- cpu_atlas1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x1>; +- enable-method = "psci"; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&atlas_l2>; +- }; +- +- cpu_atlas2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x2>; +- enable-method = "psci"; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&atlas_l2>; +- }; +- +- cpu_atlas3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x3>; +- enable-method = "psci"; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&atlas_l2>; +- }; +- +- atlas_l2: l2-cache0 { +- compatible = "cache"; +- cache-size = <0x200000>; +- cache-line-size = <64>; +- cache-sets = <2048>; +- }; +- }; +- +- psci { +- compatible = "arm,psci"; +- method = "smc"; +- cpu_off = <0x84000002>; +- cpu_on = <0xC4000003>; +- }; +- +- soc: soc@0 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0 0x18000000>; +- +- chipid@10000000 { +- compatible = "samsung,exynos4210-chipid"; +- reg = <0x10000000 0x100>; +- }; +- +- gic: interrupt-controller@11001000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x11001000 0x1000>, +- <0x11002000 0x2000>, +- <0x11004000 0x2000>, +- <0x11006000 0x2000>; +- }; +- +- pdma0: pdma@10e10000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x10E10000 0x1000>; +- interrupts = ; +- clocks = <&clock_fsys0 ACLK_PDMA0>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- }; +- +- pdma1: pdma@10eb0000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x10EB0000 0x1000>; +- interrupts = ; +- clocks = <&clock_fsys0 ACLK_PDMA1>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- }; +- +- clock_topc: clock-controller@10570000 { +- compatible = "samsung,exynos7-clock-topc"; +- reg = <0x10570000 0x10000>; +- #clock-cells = <1>; +- }; +- +- clock_top0: clock-controller@105d0000 { +- compatible = "samsung,exynos7-clock-top0"; +- reg = <0x105d0000 0xb000>; +- #clock-cells = <1>; +- clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, +- <&clock_topc DOUT_SCLK_BUS1_PLL>, +- <&clock_topc DOUT_SCLK_CC_PLL>, +- <&clock_topc DOUT_SCLK_MFC_PLL>; +- clock-names = "fin_pll", "dout_sclk_bus0_pll", +- "dout_sclk_bus1_pll", "dout_sclk_cc_pll", +- "dout_sclk_mfc_pll"; +- }; +- +- clock_top1: clock-controller@105e0000 { +- compatible = "samsung,exynos7-clock-top1"; +- reg = <0x105e0000 0xb000>; +- #clock-cells = <1>; +- clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, +- <&clock_topc DOUT_SCLK_BUS1_PLL>, +- <&clock_topc DOUT_SCLK_CC_PLL>, +- <&clock_topc DOUT_SCLK_MFC_PLL>; +- clock-names = "fin_pll", "dout_sclk_bus0_pll", +- "dout_sclk_bus1_pll", "dout_sclk_cc_pll", +- "dout_sclk_mfc_pll"; +- }; +- +- clock_ccore: clock-controller@105b0000 { +- compatible = "samsung,exynos7-clock-ccore"; +- reg = <0x105b0000 0xd00>; +- #clock-cells = <1>; +- clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>; +- clock-names = "fin_pll", "dout_aclk_ccore_133"; +- }; +- +- clock_peric0: clock-controller@13610000 { +- compatible = "samsung,exynos7-clock-peric0"; +- reg = <0x13610000 0xd00>; +- #clock-cells = <1>; +- clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>, +- <&clock_top0 CLK_SCLK_UART0>; +- clock-names = "fin_pll", "dout_aclk_peric0_66", +- "sclk_uart0"; +- }; +- +- clock_peric1: clock-controller@14c80000 { +- compatible = "samsung,exynos7-clock-peric1"; +- reg = <0x14c80000 0xd00>; +- #clock-cells = <1>; +- clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>, +- <&clock_top0 CLK_SCLK_UART1>, +- <&clock_top0 CLK_SCLK_UART2>, +- <&clock_top0 CLK_SCLK_UART3>; +- clock-names = "fin_pll", "dout_aclk_peric1_66", +- "sclk_uart1", "sclk_uart2", "sclk_uart3"; +- }; +- +- clock_peris: clock-controller@10040000 { +- compatible = "samsung,exynos7-clock-peris"; +- reg = <0x10040000 0xd00>; +- #clock-cells = <1>; +- clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>; +- clock-names = "fin_pll", "dout_aclk_peris_66"; +- }; +- +- clock_fsys0: clock-controller@10e90000 { +- compatible = "samsung,exynos7-clock-fsys0"; +- reg = <0x10e90000 0xd00>; +- #clock-cells = <1>; +- clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>, +- <&clock_top1 DOUT_SCLK_MMC2>; +- clock-names = "fin_pll", "dout_aclk_fsys0_200", +- "dout_sclk_mmc2"; +- }; +- +- clock_fsys1: clock-controller@156e0000 { +- compatible = "samsung,exynos7-clock-fsys1"; +- reg = <0x156e0000 0xd00>; +- #clock-cells = <1>; +- clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>, +- <&clock_top1 DOUT_SCLK_MMC0>, +- <&clock_top1 DOUT_SCLK_MMC1>, +- <&clock_top1 DOUT_SCLK_UFSUNIPRO20>, +- <&clock_top1 DOUT_SCLK_PHY_FSYS1>, +- <&clock_top1 DOUT_SCLK_PHY_FSYS1_26M>; +- clock-names = "fin_pll", "dout_aclk_fsys1_200", +- "dout_sclk_mmc0", "dout_sclk_mmc1", +- "dout_sclk_ufsunipro20", "dout_sclk_phy_fsys1", +- "dout_sclk_phy_fsys1_26m"; +- }; +- +- serial_0: serial@13630000 { +- compatible = "samsung,exynos4210-uart"; +- reg = <0x13630000 0x100>; +- interrupts = ; +- clocks = <&clock_peric0 PCLK_UART0>, +- <&clock_peric0 SCLK_UART0>; +- clock-names = "uart", "clk_uart_baud0"; +- status = "disabled"; +- }; +- +- serial_1: serial@14c20000 { +- compatible = "samsung,exynos4210-uart"; +- reg = <0x14c20000 0x100>; +- interrupts = ; +- clocks = <&clock_peric1 PCLK_UART1>, +- <&clock_peric1 SCLK_UART1>; +- clock-names = "uart", "clk_uart_baud0"; +- status = "disabled"; +- }; +- +- serial_2: serial@14c30000 { +- compatible = "samsung,exynos4210-uart"; +- reg = <0x14c30000 0x100>; +- interrupts = ; +- clocks = <&clock_peric1 PCLK_UART2>, +- <&clock_peric1 SCLK_UART2>; +- clock-names = "uart", "clk_uart_baud0"; +- status = "disabled"; +- }; +- +- serial_3: serial@14c40000 { +- compatible = "samsung,exynos4210-uart"; +- reg = <0x14c40000 0x100>; +- interrupts = ; +- clocks = <&clock_peric1 PCLK_UART3>, +- <&clock_peric1 SCLK_UART3>; +- clock-names = "uart", "clk_uart_baud0"; +- status = "disabled"; +- }; +- +- pinctrl_alive: pinctrl@10580000 { +- compatible = "samsung,exynos7-pinctrl"; +- reg = <0x10580000 0x1000>; +- +- wakeup-interrupt-controller { +- compatible = "samsung,exynos7-wakeup-eint"; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +- +- pinctrl_bus0: pinctrl@13470000 { +- compatible = "samsung,exynos7-pinctrl"; +- reg = <0x13470000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_nfc: pinctrl@14cd0000 { +- compatible = "samsung,exynos7-pinctrl"; +- reg = <0x14cd0000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_touch: pinctrl@14ce0000 { +- compatible = "samsung,exynos7-pinctrl"; +- reg = <0x14ce0000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_ff: pinctrl@14c90000 { +- compatible = "samsung,exynos7-pinctrl"; +- reg = <0x14c90000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_ese: pinctrl@14ca0000 { +- compatible = "samsung,exynos7-pinctrl"; +- reg = <0x14ca0000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_fsys0: pinctrl@10e60000 { +- compatible = "samsung,exynos7-pinctrl"; +- reg = <0x10e60000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_fsys1: pinctrl@15690000 { +- compatible = "samsung,exynos7-pinctrl"; +- reg = <0x15690000 0x1000>; +- interrupts = ; +- }; +- +- pinctrl_bus1: pinctrl@14870000 { +- compatible = "samsung,exynos7-pinctrl"; +- reg = <0x14870000 0x1000>; +- interrupts = ; +- }; +- +- hsi2c_0: hsi2c@13640000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x13640000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c0_bus>; +- clocks = <&clock_peric0 PCLK_HSI2C0>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_1: hsi2c@13650000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x13650000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c1_bus>; +- clocks = <&clock_peric0 PCLK_HSI2C1>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_2: hsi2c@14e60000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x14e60000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c2_bus>; +- clocks = <&clock_peric1 PCLK_HSI2C2>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_3: hsi2c@14e70000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x14e70000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c3_bus>; +- clocks = <&clock_peric1 PCLK_HSI2C3>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_4: hsi2c@13660000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x13660000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c4_bus>; +- clocks = <&clock_peric0 PCLK_HSI2C4>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_5: hsi2c@13670000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x13670000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c5_bus>; +- clocks = <&clock_peric0 PCLK_HSI2C5>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_6: hsi2c@14e00000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x14e00000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c6_bus>; +- clocks = <&clock_peric1 PCLK_HSI2C6>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_7: hsi2c@13e10000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x13e10000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c7_bus>; +- clocks = <&clock_peric1 PCLK_HSI2C7>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_8: hsi2c@14e20000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x14e20000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c8_bus>; +- clocks = <&clock_peric1 PCLK_HSI2C8>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_9: hsi2c@13680000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x13680000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c9_bus>; +- clocks = <&clock_peric0 PCLK_HSI2C9>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_10: hsi2c@13690000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x13690000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c10_bus>; +- clocks = <&clock_peric0 PCLK_HSI2C10>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- hsi2c_11: hsi2c@136a0000 { +- compatible = "samsung,exynos7-hsi2c"; +- reg = <0x136a0000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hs_i2c11_bus>; +- clocks = <&clock_peric0 PCLK_HSI2C11>; +- clock-names = "hsi2c"; +- status = "disabled"; +- }; +- +- pmu_system_controller: system-controller@105c0000 { +- compatible = "samsung,exynos7-pmu", "syscon"; +- reg = <0x105c0000 0x5000>; +- }; +- +- rtc: rtc@10590000 { +- compatible = "samsung,s3c6410-rtc"; +- reg = <0x10590000 0x100>; +- interrupts = , +- ; +- clocks = <&clock_ccore PCLK_RTC>; +- clock-names = "rtc"; +- status = "disabled"; +- }; +- +- watchdog: watchdog@101d0000 { +- compatible = "samsung,exynos7-wdt"; +- reg = <0x101d0000 0x100>; +- interrupts = ; +- clocks = <&clock_peris PCLK_WDT>; +- clock-names = "watchdog"; +- samsung,syscon-phandle = <&pmu_system_controller>; +- status = "disabled"; +- }; +- +- gpu: gpu@14ac0000 { +- compatible = "samsung,exynos5433-mali", "arm,mali-t760"; +- reg = <0x14ac0000 0x5000>; +- interrupts = , +- , +- ; +- interrupt-names = "job", "mmu", "gpu"; +- status = "disabled"; +- /* TODO: operating points for DVFS, cooling device */ +- }; +- +- mmc_0: mmc@15740000 { +- compatible = "samsung,exynos7-dw-mshc-smu"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x15740000 0x2000>; +- clocks = <&clock_fsys1 ACLK_MMC0>, +- <&clock_top1 CLK_SCLK_MMC0>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x40>; +- status = "disabled"; +- }; +- +- mmc_1: mmc@15750000 { +- compatible = "samsung,exynos7-dw-mshc"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x15750000 0x2000>; +- clocks = <&clock_fsys1 ACLK_MMC1>, +- <&clock_top1 CLK_SCLK_MMC1>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x40>; +- status = "disabled"; +- }; +- +- mmc_2: mmc@15560000 { +- compatible = "samsung,exynos7-dw-mshc-smu"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x15560000 0x2000>; +- clocks = <&clock_fsys0 ACLK_MMC2>, +- <&clock_top1 CLK_SCLK_MMC2>; +- clock-names = "biu", "ciu"; +- fifo-depth = <0x40>; +- status = "disabled"; +- }; +- +- adc: adc@13620000 { +- compatible = "samsung,exynos7-adc"; +- reg = <0x13620000 0x100>; +- interrupts = ; +- clocks = <&clock_peric0 PCLK_ADCIF>; +- clock-names = "adc"; +- #io-channel-cells = <1>; +- status = "disabled"; +- }; +- +- pwm: pwm@136c0000 { +- compatible = "samsung,exynos4210-pwm"; +- reg = <0x136c0000 0x100>; +- interrupts = , +- , +- , +- , +- ; +- samsung,pwm-outputs = <0>, <1>, <2>, <3>; +- #pwm-cells = <3>; +- clocks = <&clock_peric0 PCLK_PWM>; +- clock-names = "timers"; +- }; +- +- tmuctrl_0: tmu@10060000 { +- compatible = "samsung,exynos7-tmu"; +- reg = <0x10060000 0x200>; +- interrupts = ; +- clocks = <&clock_peris PCLK_TMU>, +- <&clock_peris SCLK_TMU>; +- clock-names = "tmu_apbif", "tmu_sclk"; +- #thermal-sensor-cells = <0>; +- }; +- +- ufs: ufs@15570000 { +- compatible = "samsung,exynos7-ufs"; +- reg = <0x15570000 0x100>, /* 0: HCI standard */ +- <0x15570100 0x100>, /* 1: Vendor specificed */ +- <0x15571000 0x200>, /* 2: UNIPRO */ +- <0x15572000 0x300>; /* 3: UFS protector */ +- reg-names = "hci", "vs_hci", "unipro", "ufsp"; +- interrupts = ; +- clocks = <&clock_fsys1 ACLK_UFS20_LINK>, +- <&clock_fsys1 SCLK_UFSUNIPRO20_USER>; +- clock-names = "core_clk", "sclk_unipro_main"; +- freq-table-hz = <0 0>, <0 0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; +- phys = <&ufs_phy>; +- phy-names = "ufs-phy"; +- status = "disabled"; +- }; +- +- ufs_phy: ufs-phy@15571800 { +- compatible = "samsung,exynos7-ufs-phy"; +- reg = <0x15571800 0x240>; +- reg-names = "phy-pma"; +- samsung,pmu-syscon = <&pmu_system_controller>; +- #phy-cells = <0>; +- clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>, +- <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>, +- <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>, +- <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>; +- clock-names = "ref_clk", "rx1_symbol_clk", +- "rx0_symbol_clk", +- "tx0_symbol_clk"; +- }; +- +- usbdrd_phy: phy@15500000 { +- compatible = "samsung,exynos7-usbdrd-phy"; +- reg = <0x15500000 0x100>; +- clocks = <&clock_fsys0 ACLK_USBDRD300>, +- <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>, +- <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, +- <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>, +- <&clock_fsys0 SCLK_USBDRD300_REFCLK>; +- clock-names = "phy", "ref", "phy_pipe", +- "phy_utmi", "itp"; +- samsung,pmu-syscon = <&pmu_system_controller>; +- #phy-cells = <1>; +- }; +- +- usbdrd3 { +- compatible = "samsung,exynos7-dwusb3"; +- clocks = <&clock_fsys0 ACLK_USBDRD300>, +- <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>, +- <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>; +- clock-names = "usbdrd30", "usbdrd30_susp_clk", +- "usbdrd30_axius_clk"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- usb@15400000 { +- compatible = "snps,dwc3"; +- reg = <0x15400000 0x10000>; +- interrupts = ; +- phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; +- phy-names = "usb2-phy", "usb3-phy"; +- }; +- }; +- }; +- +- thermal-zones { +- atlas_thermal: cluster0-thermal { +- polling-delay-passive = <0>; /* milliseconds */ +- polling-delay = <0>; /* milliseconds */ +- thermal-sensors = <&tmuctrl_0>; +- #include "exynos7-trip-points.dtsi" +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +-}; +- +-#include "exynos7-pinctrl.dtsi" +-#include "arm/exynos-syscon-restart.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/Makefile b/scripts/dtc/include-prefixes/arm64/freescale/Makefile +deleted file mode 100644 +index db9e36ebe932..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/Makefile ++++ /dev/null +@@ -1,73 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-kbox-a-230-ls.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var1.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-ten64.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb +-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb +- +-dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r4.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mq-mnt-reform2.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mq-phanbell.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb +-dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb +- +-dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1012a-frdm.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1012a-frdm.dts +deleted file mode 100644 +index 2517528f684f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1012a-frdm.dts ++++ /dev/null +@@ -1,119 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Freescale LS1012A Freedom Board. +- * +- * Copyright 2016 Freescale Semiconductor, Inc. +- * +- */ +-/dts-v1/; +- +-#include +-#include "fsl-ls1012a.dtsi" +- +-/ { +- model = "LS1012A Freedom Board"; +- compatible = "fsl,ls1012a-frdm", "fsl,ls1012a"; +- +- sys_mclk: clock-mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,widgets = +- "Microphone", "Microphone Jack", +- "Headphone", "Headphone Jack", +- "Speaker", "Speaker Ext", +- "Line", "Line In Jack"; +- simple-audio-card,routing = +- "MIC_IN", "Microphone Jack", +- "Microphone Jack", "Mic Bias", +- "LINE_IN", "Line In Jack", +- "Headphone Jack", "HP_OUT", +- "Speaker Ext", "LINE_OUT"; +- +- simple-audio-card,cpu { +- sound-dai = <&sai2>; +- frame-master; +- bitclock-master; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&codec>; +- frame-master; +- bitclock-master; +- system-clock-frequency = <25000000>; +- }; +- }; +-}; +- +-&dspi { +- bus-num = <0>; +- status = "okay"; +- +- serial@0 { +- compatible = "nxp,sc16is740"; +- reg = <0>; +- spi-max-frequency = <4000000>; +- clocks = <&sc16is7xx_clk>; +- interrupt-parent = <&gpio1>; +- interrupts = <13 IRQ_TYPE_EDGE_FALLING>; +- +- sc16is7xx_clk: clock-sc16is7xx { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- }; +- }; +-}; +- +-&duart0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- codec: sgtl5000@a { +- #sound-dai-cells = <0>; +- compatible = "fsl,sgtl5000"; +- reg = <0xa>; +- VDDA-supply = <®_1p8v>; +- VDDIO-supply = <®_1p8v>; +- clocks = <&sys_mclk>; +- }; +-}; +- +-&qspi { +- status = "okay"; +- +- s25fs512s0: flash@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <50000000>; +- m25p,fast-read; +- reg = <0>; +- spi-rx-bus-width = <2>; +- spi-tx-bus-width = <2>; +- }; +-}; +- +-&sai2 { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1012a-frwy.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1012a-frwy.dts +deleted file mode 100644 +index e8562585d4ac..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1012a-frwy.dts ++++ /dev/null +@@ -1,44 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Freescale LS1012A FRWY Board. +- * +- * Copyright 2018 NXP +- * +- * Pramod Kumar +- * +- */ +-/dts-v1/; +- +-#include "fsl-ls1012a.dtsi" +- +-/ { +- model = "LS1012A FRWY Board"; +- compatible = "fsl,ls1012a-frwy", "fsl,ls1012a"; +-}; +- +-&duart0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +- +-&qspi { +- status = "okay"; +- +- w25q16dw0: flash@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- m25p,fast-read; +- spi-max-frequency = <50000000>; +- reg = <0>; +- spi-rx-bus-width = <2>; +- spi-tx-bus-width = <2>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1012a-oxalis.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1012a-oxalis.dts +deleted file mode 100644 +index 242f4b0cb344..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1012a-oxalis.dts ++++ /dev/null +@@ -1,100 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Oxalis +- * +- * Copyright (c) 2019 Manivannan Sadhasivam +- * +- */ +- +-/dts-v1/; +- +-#include "fsl-ls1012a.dtsi" +- +-/ { +- model = "Oxalis"; +- compatible = "ebs-systart,oxalis", "fsl,ls1012a"; +- +- sys_mclk: clock-mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,widgets = +- "Microphone", "Microphone Jack", +- "Headphone", "Headphone Jack", +- "Speaker", "Speaker Ext", +- "Line", "Line In Jack"; +- simple-audio-card,routing = +- "MIC_IN", "Microphone Jack", +- "Microphone Jack", "Mic Bias", +- "LINE_IN", "Line In Jack", +- "Headphone Jack", "HP_OUT", +- "Speaker Ext", "LINE_OUT"; +- +- simple-audio-card,cpu { +- sound-dai = <&sai2>; +- frame-master; +- bitclock-master; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&codec>; +- frame-master; +- bitclock-master; +- system-clock-frequency = <25000000>; +- }; +- }; +-}; +- +-&duart0 { +- status = "okay"; +-}; +- +-&duart1 { +- status = "okay"; +-}; +- +-&esdhc1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- codec: audio-codec@a { +- #sound-dai-cells = <0>; +- compatible = "fsl,sgtl5000"; +- reg = <0xa>; +- VDDA-supply = <®_1p8v>; +- VDDIO-supply = <®_1p8v>; +- clocks = <&sys_mclk>; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +- +-&sai2 { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1012a-qds.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1012a-qds.dts +deleted file mode 100644 +index e22c5e77fecd..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1012a-qds.dts ++++ /dev/null +@@ -1,157 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Freescale LS1012A QDS Board. +- * +- * Copyright 2016 Freescale Semiconductor, Inc. +- * +- */ +-/dts-v1/; +- +-#include "fsl-ls1012a.dtsi" +- +-/ { +- model = "LS1012A QDS Board"; +- compatible = "fsl,ls1012a-qds", "fsl,ls1012a"; +- +- aliases { +- mmc0 = &esdhc0; +- mmc1 = &esdhc1; +- }; +- +- sys_mclk: clock-mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,widgets = +- "Microphone", "Microphone Jack", +- "Headphone", "Headphone Jack", +- "Speaker", "Speaker Ext", +- "Line", "Line In Jack"; +- simple-audio-card,routing = +- "MIC_IN", "Microphone Jack", +- "Microphone Jack", "Mic Bias", +- "LINE_IN", "Line In Jack", +- "Headphone Jack", "HP_OUT", +- "Speaker Ext", "LINE_OUT"; +- +- simple-audio-card,cpu { +- sound-dai = <&sai2>; +- frame-master; +- bitclock-master; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&codec>; +- frame-master; +- bitclock-master; +- system-clock-frequency = <24576000>; +- }; +- }; +-}; +- +-&dspi { +- bus-num = <0>; +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "n25q128a11", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <10000000>; +- }; +- +- flash@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "sst25wf040b", "jedec,spi-nor"; +- spi-cpol; +- spi-cpha; +- reg = <1>; +- spi-max-frequency = <10000000>; +- }; +- +- flash@2 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "en25s64", "jedec,spi-nor"; +- spi-cpol; +- spi-cpha; +- reg = <2>; +- spi-max-frequency = <10000000>; +- }; +-}; +- +-&duart0 { +- status = "okay"; +-}; +- +-&esdhc0 { +- status = "okay"; +-}; +- +-&esdhc1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- pca9547@77 { +- compatible = "nxp,pca9547"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x4>; +- +- codec: sgtl5000@a { +- #sound-dai-cells = <0>; +- compatible = "fsl,sgtl5000"; +- reg = <0xa>; +- VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; +- clocks = <&sys_mclk>; +- }; +- }; +- }; +-}; +- +-&qspi { +- status = "okay"; +- +- s25fs512s0: flash@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <50000000>; +- m25p,fast-read; +- reg = <0>; +- spi-rx-bus-width = <2>; +- spi-tx-bus-width = <2>; +- }; +-}; +- +-&sai2 { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1012a-rdb.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1012a-rdb.dts +deleted file mode 100644 +index e662677a6e28..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1012a-rdb.dts ++++ /dev/null +@@ -1,106 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Freescale LS1012A RDB Board. +- * +- * Copyright 2016 Freescale Semiconductor, Inc. +- * +- */ +-/dts-v1/; +- +-#include +-#include "fsl-ls1012a.dtsi" +- +-/ { +- model = "LS1012A RDB Board"; +- compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; +- +- aliases { +- serial0 = &duart0; +- mmc0 = &esdhc0; +- mmc1 = &esdhc1; +- }; +-}; +- +-&duart0 { +- status = "okay"; +-}; +- +-&esdhc0 { +- sd-uhs-sdr104; +- sd-uhs-sdr50; +- sd-uhs-sdr25; +- sd-uhs-sdr12; +- status = "okay"; +-}; +- +-&esdhc1 { +- mmc-hs200-1_8v; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- accelerometer@1e { +- compatible = "nxp,fxos8700"; +- reg = <0x1e>; +- interrupt-parent = <&gpio26>; +- interrupts = <13 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "INT1"; +- }; +- +- gyroscope@20 { +- compatible = "nxp,fxas21002c"; +- reg = <0x20>; +- }; +- +- gpio@24 { +- compatible = "nxp,pcal9555a"; +- reg = <0x24>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpio@25 { +- compatible = "nxp,pcal9555a"; +- reg = <0x25>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpio26: gpio@26 { +- compatible = "nxp,pcal9555a"; +- reg = <0x26>; +- interrupt-parent = <&gpio0>; +- interrupts = <13 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- current-sensor@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <2000>; +- }; +-}; +- +-&qspi { +- status = "okay"; +- +- s25fs512s0: flash@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <50000000>; +- m25p,fast-read; +- reg = <0>; +- spi-rx-bus-width = <2>; +- spi-tx-bus-width = <2>; +- }; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1012a.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1012a.dtsi +deleted file mode 100644 +index 50a72cda4727..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1012a.dtsi ++++ /dev/null +@@ -1,569 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for NXP Layerscape-1012A family SoC. +- * +- * Copyright 2016 Freescale Semiconductor, Inc. +- * Copyright 2019-2020 NXP +- * +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "fsl,ls1012a"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- crypto = &crypto; +- rtc1 = &ftm_alarm0; +- rtic-a = &rtic_a; +- rtic-b = &rtic_b; +- rtic-c = &rtic_c; +- rtic-d = &rtic_d; +- sec-mon = &sec_mon; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0>; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- #cooling-cells = <2>; +- cpu-idle-states = <&CPU_PH20>; +- }; +- }; +- +- idle-states { +- /* +- * PSCI node is not added default, U-boot will add missing +- * parts if it determines to use PSCI. +- */ +- entry-method = "psci"; +- +- CPU_PH20: cpu-ph20 { +- compatible = "arm,idle-state"; +- idle-state-name = "PH20"; +- arm,psci-suspend-param = <0x0>; +- entry-latency-us = <1000>; +- exit-latency-us = <1000>; +- min-residency-us = <3000>; +- }; +- }; +- +- sysclk: sysclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- clock-output-names = "sysclk"; +- }; +- +- coreclk: coreclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- clock-output-names = "coreclk"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ +- <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ +- <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ +- <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- gic: interrupt-controller@1400000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x0 0x1401000 0 0x1000>, /* GICD */ +- <0x0 0x1402000 0 0x2000>, /* GICC */ +- <0x0 0x1404000 0 0x2000>, /* GICH */ +- <0x0 0x1406000 0 0x2000>; /* GICV */ +- interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>; +- }; +- +- reboot { +- compatible = "syscon-reboot"; +- regmap = <&dcfg>; +- offset = <0xb0>; +- mask = <0x02>; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 0>; +- +- trips { +- cpu_alert: cpu-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_crit: cpu-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert>; +- cooling-device = +- <&cpu0 THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- qspi: spi@1550000 { +- compatible = "fsl,ls1021a-qspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x1550000 0x0 0x10000>, +- <0x0 0x40000000 0x0 0x10000000>; +- reg-names = "QuadSPI", "QuadSPI-memory"; +- interrupts = ; +- clock-names = "qspi_en", "qspi"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- status = "disabled"; +- }; +- +- esdhc0: esdhc@1560000 { +- compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; +- reg = <0x0 0x1560000 0x0 0x10000>; +- interrupts = <0 62 0x4>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- voltage-ranges = <1800 1800 3300 3300>; +- sdhci,auto-cmd12; +- big-endian; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- scfg: scfg@1570000 { +- compatible = "fsl,ls1012a-scfg", "syscon"; +- reg = <0x0 0x1570000 0x0 0x10000>; +- big-endian; +- }; +- +- esdhc1: esdhc@1580000 { +- compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; +- reg = <0x0 0x1580000 0x0 0x10000>; +- interrupts = <0 65 0x4>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- voltage-ranges = <1800 1800 3300 3300>; +- sdhci,auto-cmd12; +- big-endian; +- broken-cd; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- crypto: crypto@1700000 { +- compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", +- "fsl,sec-v4.0"; +- fsl,sec-era = <8>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x00 0x1700000 0x100000>; +- reg = <0x00 0x1700000 0x0 0x100000>; +- interrupts = ; +- dma-coherent; +- +- sec_jr0: jr@10000 { +- compatible = "fsl,sec-v5.4-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x10000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr1: jr@20000 { +- compatible = "fsl,sec-v5.4-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x20000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr2: jr@30000 { +- compatible = "fsl,sec-v5.4-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x30000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr3: jr@40000 { +- compatible = "fsl,sec-v5.4-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x40000 0x10000>; +- interrupts = ; +- }; +- +- rtic@60000 { +- compatible = "fsl,sec-v5.4-rtic", +- "fsl,sec-v5.0-rtic", +- "fsl,sec-v4.0-rtic"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x60000 0x100>, <0x60e00 0x18>; +- ranges = <0x0 0x60100 0x500>; +- +- rtic_a: rtic-a@0 { +- compatible = "fsl,sec-v5.4-rtic-memory", +- "fsl,sec-v5.0-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x00 0x20>, <0x100 0x100>; +- }; +- +- rtic_b: rtic-b@20 { +- compatible = "fsl,sec-v5.4-rtic-memory", +- "fsl,sec-v5.0-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x20 0x20>, <0x200 0x100>; +- }; +- +- rtic_c: rtic-c@40 { +- compatible = "fsl,sec-v5.4-rtic-memory", +- "fsl,sec-v5.0-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x40 0x20>, <0x300 0x100>; +- }; +- +- rtic_d: rtic-d@60 { +- compatible = "fsl,sec-v5.4-rtic-memory", +- "fsl,sec-v5.0-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x60 0x20>, <0x400 0x100>; +- }; +- }; +- }; +- +- sec_mon: sec_mon@1e90000 { +- compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon", +- "fsl,sec-v4.0-mon"; +- reg = <0x0 0x1e90000 0x0 0x10000>; +- interrupts = , +- ; +- }; +- +- dcfg: dcfg@1ee0000 { +- compatible = "fsl,ls1012a-dcfg", +- "syscon"; +- reg = <0x0 0x1ee0000 0x0 0x10000>; +- big-endian; +- }; +- +- clockgen: clocking@1ee1000 { +- compatible = "fsl,ls1012a-clockgen"; +- reg = <0x0 0x1ee1000 0x0 0x1000>; +- #clock-cells = <2>; +- clocks = <&sysclk &coreclk>; +- clock-names = "sysclk", "coreclk"; +- }; +- +- tmu: tmu@1f00000 { +- compatible = "fsl,qoriq-tmu"; +- reg = <0x0 0x1f00000 0x0 0x10000>; +- interrupts = <0 33 0x4>; +- fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>; +- fsl,tmu-calibration = <0x00000000 0x00000025 +- 0x00000001 0x0000002c +- 0x00000002 0x00000032 +- 0x00000003 0x00000039 +- 0x00000004 0x0000003f +- 0x00000005 0x00000046 +- 0x00000006 0x0000004c +- 0x00000007 0x00000053 +- 0x00000008 0x00000059 +- 0x00000009 0x0000005f +- 0x0000000a 0x00000066 +- 0x0000000b 0x0000006c +- +- 0x00010000 0x00000026 +- 0x00010001 0x0000002d +- 0x00010002 0x00000035 +- 0x00010003 0x0000003d +- 0x00010004 0x00000045 +- 0x00010005 0x0000004d +- 0x00010006 0x00000055 +- 0x00010007 0x0000005d +- 0x00010008 0x00000065 +- 0x00010009 0x0000006d +- +- 0x00020000 0x00000026 +- 0x00020001 0x00000030 +- 0x00020002 0x0000003a +- 0x00020003 0x00000044 +- 0x00020004 0x0000004e +- 0x00020005 0x00000059 +- 0x00020006 0x00000063 +- +- 0x00030000 0x00000014 +- 0x00030001 0x00000021 +- 0x00030002 0x0000002e +- 0x00030003 0x0000003a +- 0x00030004 0x00000047 +- 0x00030005 0x00000053 +- 0x00030006 0x00000060>; +- big-endian; +- #thermal-sensor-cells = <1>; +- }; +- +- i2c0: i2c@2180000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2180000 0x0 0x10000>; +- interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- status = "disabled"; +- }; +- +- i2c1: i2c@2190000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2190000 0x0 0x10000>; +- interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- status = "disabled"; +- }; +- +- dspi: spi@2100000 { +- compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2100000 0x0 0x10000>; +- interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>; +- clock-names = "dspi"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- spi-num-chipselects = <5>; +- big-endian; +- status = "disabled"; +- }; +- +- duart0: serial@21c0500 { +- compatible = "fsl,ns16550", "ns16550a"; +- reg = <0x00 0x21c0500 0x0 0x100>; +- interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- status = "disabled"; +- }; +- +- duart1: serial@21c0600 { +- compatible = "fsl,ns16550", "ns16550a"; +- reg = <0x00 0x21c0600 0x0 0x100>; +- interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- status = "disabled"; +- }; +- +- gpio0: gpio@2300000 { +- compatible = "fsl,qoriq-gpio"; +- reg = <0x0 0x2300000 0x0 0x10000>; +- interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio@2310000 { +- compatible = "fsl,qoriq-gpio"; +- reg = <0x0 0x2310000 0x0 0x10000>; +- interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- wdog0: watchdog@2ad0000 { +- compatible = "fsl,ls1012a-wdt", +- "fsl,imx21-wdt"; +- reg = <0x0 0x2ad0000 0x0 0x10000>; +- interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; +- big-endian; +- }; +- +- sai1: sai@2b50000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,vf610-sai"; +- reg = <0x0 0x2b50000 0x0 0x10000>; +- interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dma-names = "tx", "rx"; +- dmas = <&edma0 1 47>, +- <&edma0 1 46>; +- status = "disabled"; +- }; +- +- sai2: sai@2b60000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,vf610-sai"; +- reg = <0x0 0x2b60000 0x0 0x10000>; +- interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dma-names = "tx", "rx"; +- dmas = <&edma0 1 45>, +- <&edma0 1 44>; +- status = "disabled"; +- }; +- +- edma0: edma@2c00000 { +- #dma-cells = <2>; +- compatible = "fsl,vf610-edma"; +- reg = <0x0 0x2c00000 0x0 0x10000>, +- <0x0 0x2c10000 0x0 0x10000>, +- <0x0 0x2c20000 0x0 0x10000>; +- interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>, +- <0 103 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "edma-tx", "edma-err"; +- dma-channels = <32>; +- big-endian; +- clock-names = "dmamux0", "dmamux1"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- }; +- +- usb0: usb@2f00000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0x2f00000 0x0 0x10000>; +- interrupts = <0 60 0x4>; +- dr_mode = "host"; +- snps,quirk-frame-length-adjustment = <0x20>; +- snps,dis_rxdet_inp3_quirk; +- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; +- }; +- +- sata: sata@3200000 { +- compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci"; +- reg = <0x0 0x3200000 0x0 0x10000>, +- <0x0 0x20140520 0x0 0x4>; +- reg-names = "ahci", "sata-ecc"; +- interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- dma-coherent; +- status = "disabled"; +- }; +- +- usb1: usb@8600000 { +- compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; +- reg = <0x0 0x8600000 0x0 0x1000>; +- interrupts = <0 139 0x4>; +- dr_mode = "host"; +- phy_type = "ulpi"; +- }; +- +- msi: msi-controller1@1572000 { +- compatible = "fsl,ls1012a-msi"; +- reg = <0x0 0x1572000 0x0 0x8>; +- msi-controller; +- interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- pcie1: pcie@3400000 { +- compatible = "fsl,ls1012a-pcie"; +- reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ +- <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "regs", "config"; +- interrupts = <0 118 0x4>, /* controller interrupt */ +- <0 117 0x4>; /* PME interrupt */ +- interrupt-names = "aer", "pme"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- num-viewport = <2>; +- bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ +- 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&msi>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +- +- rcpm: power-controller@1ee2140 { +- compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+"; +- reg = <0x0 0x1ee2140 0x0 0x4>; +- #fsl,rcpm-wakeup-cells = <1>; +- }; +- +- ftm_alarm0: timer@29d0000 { +- compatible = "fsl,ls1012a-ftm-alarm"; +- reg = <0x0 0x29d0000 0x0 0x10000>; +- fsl,rcpm-wakeup = <&rcpm 0x20000>; +- interrupts = ; +- big-endian; +- }; +- }; +- +- firmware { +- optee { +- compatible = "linaro,optee-tz"; +- method = "smc"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts +deleted file mode 100644 +index 6b575efd84a7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts ++++ /dev/null +@@ -1,113 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Device Tree File for the Kontron KBox A-230-LS. +- * +- * This consists of a Kontron SMARC-sAL28 (Dual PHY) and a special +- * carrier (s1914). +- * +- * Copyright (C) 2019 Michael Walle +- * +- */ +- +-/dts-v1/; +-#include "fsl-ls1028a-kontron-sl28-var4.dts" +-#include +- +-/ { +- model = "Kontron KBox A-230-LS"; +- compatible = "kontron,kbox-a-230-ls", "kontron,sl28-var4", +- "kontron,sl28", "fsl,ls1028a"; +- +- leds { +- compatible = "gpio-leds"; +- +- alarm-led { +- function = LED_FUNCTION_ALARM; +- color = ; +- gpios = <&sl28cpld_gpio0 0 GPIO_ACTIVE_HIGH>; +- }; +- +- power-led { +- linux,default-trigger = "default-on"; +- function = LED_FUNCTION_POWER; +- color = ; +- gpios = <&sl28cpld_gpio1 3 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&enetc_mdio_pf3 { +- /* BCM54140 QSGMII quad PHY */ +- qsgmii_phy0: ethernet-phy@7 { +- reg = <7>; +- }; +- +- qsgmii_phy1: ethernet-phy@8 { +- reg = <8>; +- }; +- +- qsgmii_phy2: ethernet-phy@9 { +- reg = <9>; +- }; +- +- qsgmii_phy3: ethernet-phy@10 { +- reg = <10>; +- }; +-}; +- +-&enetc_port2 { +- status = "okay"; +-}; +- +-&i2c3 { +- eeprom@57 { +- compatible = "atmel,24c32"; +- reg = <0x57>; +- pagesize = <32>; +- }; +-}; +- +-&mscc_felix { +- status = "okay"; +-}; +- +-&mscc_felix_port0 { +- label = "swp0"; +- managed = "in-band-status"; +- phy-handle = <&qsgmii_phy0>; +- phy-mode = "qsgmii"; +- status = "okay"; +-}; +- +-&mscc_felix_port1 { +- label = "swp1"; +- managed = "in-band-status"; +- phy-handle = <&qsgmii_phy1>; +- phy-mode = "qsgmii"; +- status = "okay"; +-}; +- +-&mscc_felix_port2 { +- label = "swp2"; +- managed = "in-band-status"; +- phy-handle = <&qsgmii_phy2>; +- phy-mode = "qsgmii"; +- status = "okay"; +-}; +- +-&mscc_felix_port3 { +- label = "swp3"; +- managed = "in-band-status"; +- phy-handle = <&qsgmii_phy3>; +- phy-mode = "qsgmii"; +- status = "okay"; +-}; +- +-&mscc_felix_port4 { +- ethernet = <&enetc_port2>; +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-kontron-sl28-var1.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-kontron-sl28-var1.dts +deleted file mode 100644 +index e8d31279b7a3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-kontron-sl28-var1.dts ++++ /dev/null +@@ -1,63 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Device Tree file for the Kontron SMARC-sAL28 board. +- * +- * This is for the network variant 1 which has one ethernet port. It is +- * different than the base variant, which also has one port, but here the +- * port is connected via RGMII. This port is not TSN aware. +- * None of the four SerDes lanes are used by the module, instead they are +- * all led out to the carrier for customer use. +- * +- * Copyright (C) 2020 Michael Walle +- * +- */ +- +-/dts-v1/; +-#include "fsl-ls1028a-kontron-sl28.dts" +-#include +- +-/ { +- model = "Kontron SMARC-sAL28 (4 Lanes)"; +- compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a"; +-}; +- +-&enetc_port0 { +- status = "disabled"; +- /* +- * Delete both the phy-handle to the old phy0 label as well as +- * the mdio node with the old phy node with the old phy0 label. +- */ +- /delete-property/ phy-handle; +- /delete-node/ mdio; +-}; +- +-&enetc_port1 { +- phy-handle = <&phy0>; +- phy-connection-type = "rgmii-id"; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: ethernet-phy@4 { +- reg = <0x4>; +- eee-broken-1000t; +- eee-broken-100tx; +- qca,clk-out-frequency = <125000000>; +- qca,clk-out-strength = ; +- qca,keep-pll-enabled; +- vddio-supply = <&vddio>; +- +- vddio: vddio-regulator { +- regulator-name = "VDDIO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vddh: vddh-regulator { +- regulator-name = "VDDH"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-kontron-sl28-var2.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-kontron-sl28-var2.dts +deleted file mode 100644 +index f6a79c8080d1..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-kontron-sl28-var2.dts ++++ /dev/null +@@ -1,74 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Device Tree file for the Kontron SMARC-sAL28 board. +- * +- * This is for the network variant 2 which has two ethernet ports. These +- * ports are connected to the internal switch. +- * +- * Copyright (C) 2020 Michael Walle +- * +- */ +- +-/dts-v1/; +-#include "fsl-ls1028a-kontron-sl28.dts" +- +-/ { +- model = "Kontron SMARC-sAL28 (TSN-on-module)"; +- compatible = "kontron,sl28-var2", "kontron,sl28", "fsl,ls1028a"; +-}; +- +-&enetc_mdio_pf3 { +- phy0: ethernet-phy@5 { +- reg = <0x5>; +- eee-broken-1000t; +- eee-broken-100tx; +- }; +- +- phy1: ethernet-phy@4 { +- reg = <0x4>; +- eee-broken-1000t; +- eee-broken-100tx; +- }; +-}; +- +-&enetc_port0 { +- status = "disabled"; +- /* +- * In the base device tree the PHY was registered in the mdio +- * subnode as it is PHY for this port. On this module this PHY +- * is connected to a switch port instead and registered above. +- * Therefore, delete the mdio subnode as well as the phy-handle +- * property here. +- */ +- /delete-property/ phy-handle; +- /delete-node/ mdio; +-}; +- +-&enetc_port2 { +- status = "okay"; +-}; +- +-&mscc_felix { +- status = "okay"; +-}; +- +-&mscc_felix_port0 { +- label = "swp0"; +- managed = "in-band-status"; +- phy-handle = <&phy0>; +- phy-mode = "sgmii"; +- status = "okay"; +-}; +- +-&mscc_felix_port1 { +- label = "swp1"; +- managed = "in-band-status"; +- phy-handle = <&phy1>; +- phy-mode = "sgmii"; +- status = "okay"; +-}; +- +-&mscc_felix_port4 { +- ethernet = <&enetc_port2>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts +deleted file mode 100644 +index ed4e69e87e30..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts ++++ /dev/null +@@ -1,129 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Device Tree file for the Kontron SMARC-sAL28 board on a SMARC Eval 2.0 +- * carrier (ADS2). +- * +- * Copyright (C) 2019 Michael Walle +- * +- */ +- +-/dts-v1/; +- +-#include +-#include "fsl-ls1028a-kontron-sl28.dts" +- +-/ { +- model = "Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier"; +- compatible = "kontron,sl28-var3-ads2", "kontron,sl28-var3", +- "kontron,sl28", "fsl,ls1028a"; +- +- pwm-fan { +- compatible = "pwm-fan"; +- cooling-min-state = <0>; +- cooling-max-state = <3>; +- #cooling-cells = <2>; +- pwms = <&sl28cpld_pwm0 0 4000000>; +- cooling-levels = <1 128 192 255>; +- }; +- +- sound { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "simple-audio-card"; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack", +- "Line", "Line Out Jack", +- "Microphone", "Microphone Jack", +- "Line", "Line In Jack"; +- simple-audio-card,routing = +- "Line Out Jack", "LINEOUTR", +- "Line Out Jack", "LINEOUTL", +- "Headphone Jack", "HPOUTR", +- "Headphone Jack", "HPOUTL", +- "IN1L", "Line In Jack", +- "IN1R", "Line In Jack", +- "Microphone Jack", "MICBIAS", +- "IN2L", "Microphone Jack", +- "IN2R", "Microphone Jack"; +- simple-audio-card,mclk-fs = <256>; +- +- simple-audio-card,dai-link@0 { +- reg = <0>; +- bitclock-master = <&dailink0_master>; +- frame-master = <&dailink0_master>; +- format = "i2s"; +- +- cpu { +- sound-dai = <&sai6>; +- }; +- +- dailink0_master: codec { +- sound-dai = <&wm8904>; +- }; +- }; +- +- simple-audio-card,dai-link@1 { +- reg = <1>; +- bitclock-master = <&dailink1_master>; +- frame-master = <&dailink1_master>; +- format = "i2s"; +- +- cpu { +- sound-dai = <&sai5>; +- }; +- +- dailink1_master: codec { +- sound-dai = <&wm8904>; +- }; +- }; +- }; +-}; +- +-&dspi2 { +- flash@0 { +- compatible = "jedec,spi-nor"; +- m25p,fast-read; +- spi-max-frequency = <100000000>; +- reg = <0>; +- }; +-}; +- +-&i2c3 { +- eeprom@57 { +- compatible = "atmel,24c64"; +- reg = <0x57>; +- pagesize = <32>; +- }; +-}; +- +-&i2c4 { +- status = "okay"; +- +- wm8904: audio-codec@1a { +- #sound-dai-cells = <0>; +- compatible = "wlf,wm8904"; +- reg = <0x1a>; +- clocks = <&mclk>; +- clock-names = "mclk"; +- assigned-clocks = <&mclk>; +- assigned-clock-rates = <1250000>; +- }; +-}; +- +-&sai5 { +- status = "okay"; +-}; +- +-&sai6 { +- status = "okay"; +-}; +- +-&soc { +- mclk: clock-mclk@f130080 { +- compatible = "fsl,vf610-sai-clock"; +- reg = <0x0 0xf130080 0x0 0x80>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- #clock-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-kontron-sl28-var4.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-kontron-sl28-var4.dts +deleted file mode 100644 +index e65d1c477e2c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-kontron-sl28-var4.dts ++++ /dev/null +@@ -1,50 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Device Tree file for the Kontron SMARC-sAL28 board. +- * +- * This is for the network variant 4 which has two ethernet ports. It +- * extends the base and provides one more port connected via RGMII. +- * +- * Copyright (C) 2019 Michael Walle +- * +- */ +- +-/dts-v1/; +-#include "fsl-ls1028a-kontron-sl28.dts" +-#include +- +-/ { +- model = "Kontron SMARC-sAL28 (Dual PHY)"; +- compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a"; +-}; +- +-&enetc_port1 { +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy1: ethernet-phy@4 { +- reg = <0x4>; +- eee-broken-1000t; +- eee-broken-100tx; +- qca,clk-out-frequency = <125000000>; +- qca,clk-out-strength = ; +- qca,keep-pll-enabled; +- vddio-supply = <&vddio>; +- +- vddio: vddio-regulator { +- regulator-name = "VDDIO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vddh: vddh-regulator { +- regulator-name = "VDDH"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-kontron-sl28.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-kontron-sl28.dts +deleted file mode 100644 +index a92ecb331cdc..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-kontron-sl28.dts ++++ /dev/null +@@ -1,311 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Device Tree file for the Kontron SMARC-sAL28 board. +- * +- * Copyright (C) 2019 Michael Walle +- * +- */ +- +-/dts-v1/; +-#include "fsl-ls1028a.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "Kontron SMARC-sAL28"; +- compatible = "kontron,sl28", "fsl,ls1028a"; +- +- aliases { +- crypto = &crypto; +- serial0 = &duart0; +- serial1 = &duart1; +- serial2 = &lpuart1; +- spi0 = &fspi; +- spi1 = &dspi2; +- mmc0 = &esdhc1; +- mmc1 = &esdhc; +- rtc0 = &rtc; +- rtc1 = &ftm_alarm0; +- }; +- +- buttons0 { +- compatible = "gpio-keys"; +- +- power-button { +- interrupts-extended = <&sl28cpld_intc +- 4 IRQ_TYPE_EDGE_BOTH>; +- linux,code = ; +- label = "Power"; +- }; +- +- sleep-button { +- interrupts-extended = <&sl28cpld_intc +- 5 IRQ_TYPE_EDGE_BOTH>; +- linux,code = ; +- label = "Sleep"; +- }; +- }; +- +- buttons1 { +- compatible = "gpio-keys-polled"; +- poll-interval = <200>; +- +- lid-switch { +- linux,input-type = ; +- linux,code = ; +- gpios = <&sl28cpld_gpio3 4 GPIO_ACTIVE_LOW>; +- label = "Lid"; +- }; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&can0 { +- status = "okay"; +-}; +- +-&dspi2 { +- status = "okay"; +-}; +- +-&duart0 { +- status = "okay"; +-}; +- +-&duart1 { +- status = "okay"; +-}; +- +-&enetc_port0 { +- phy-handle = <&phy0>; +- phy-connection-type = "sgmii"; +- managed = "in-band-status"; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: ethernet-phy@5 { +- reg = <0x5>; +- eee-broken-1000t; +- eee-broken-100tx; +- }; +- }; +-}; +- +-&esdhc { +- sd-uhs-sdr104; +- sd-uhs-sdr50; +- sd-uhs-sdr25; +- sd-uhs-sdr12; +- status = "okay"; +-}; +- +-&esdhc1 { +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- bus-width = <8>; +- status = "okay"; +-}; +- +-&fspi { +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- m25p,fast-read; +- spi-max-frequency = <133000000>; +- reg = <0>; +- /* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */ +- spi-rx-bus-width = <2>; /* 2 SPI Rx lines */ +- spi-tx-bus-width = <1>; /* 1 SPI Tx line */ +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- reg = <0x000000 0x010000>; +- label = "rcw"; +- read-only; +- }; +- +- partition@10000 { +- reg = <0x010000 0x1d0000>; +- label = "failsafe bootloader"; +- read-only; +- }; +- +- partition@200000 { +- reg = <0x200000 0x010000>; +- label = "configuration store"; +- }; +- +- partition@210000 { +- reg = <0x210000 0x1d0000>; +- label = "bootloader"; +- }; +- +- partition@3e0000 { +- reg = <0x3e0000 0x020000>; +- label = "bootloader environment"; +- }; +- }; +- }; +-}; +- +-&gpio1 { +- gpio-line-names = +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "TDO", "TCK", +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio2 { +- gpio-line-names = +- "", "", "", "", "", "", "TMS", "TDI", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", ""; +-}; +- +-&i2c0 { +- status = "okay"; +- +- rtc: rtc@32 { +- compatible = "microcrystal,rv8803"; +- reg = <0x32>; +- }; +- +- sl28cpld@4a { +- compatible = "kontron,sl28cpld"; +- reg = <0x4a>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- watchdog@4 { +- compatible = "kontron,sl28cpld-wdt"; +- reg = <0x4>; +- kontron,assert-wdt-timeout-pin; +- }; +- +- hwmon@b { +- compatible = "kontron,sl28cpld-fan"; +- reg = <0xb>; +- }; +- +- sl28cpld_pwm0: pwm@c { +- compatible = "kontron,sl28cpld-pwm"; +- reg = <0xc>; +- #pwm-cells = <2>; +- }; +- +- sl28cpld_pwm1: pwm@e { +- compatible = "kontron,sl28cpld-pwm"; +- reg = <0xe>; +- #pwm-cells = <2>; +- }; +- +- sl28cpld_gpio0: gpio@10 { +- compatible = "kontron,sl28cpld-gpio"; +- reg = <0x10>; +- interrupts-extended = <&gpio2 6 +- IRQ_TYPE_EDGE_FALLING>; +- +- gpio-controller; +- #gpio-cells = <2>; +- gpio-line-names = +- "GPIO0_CAM0_PWR_N", "GPIO1_CAM1_PWR_N", +- "GPIO2_CAM0_RST_N", "GPIO3_CAM1_RST_N", +- "GPIO4_HDA_RST_N", "GPIO5_PWM_OUT", +- "GPIO6_TACHIN", "GPIO7"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- sl28cpld_gpio1: gpio@15 { +- compatible = "kontron,sl28cpld-gpio"; +- reg = <0x15>; +- interrupts-extended = <&gpio2 6 +- IRQ_TYPE_EDGE_FALLING>; +- +- gpio-controller; +- #gpio-cells = <2>; +- gpio-line-names = +- "GPIO8", "GPIO9", "GPIO10", "GPIO11", +- "", "", "", ""; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- sl28cpld_gpio2: gpio@1a { +- compatible = "kontron,sl28cpld-gpo"; +- reg = <0x1a>; +- +- gpio-controller; +- #gpio-cells = <2>; +- gpio-line-names = +- "LCD0 voltage enable", +- "LCD0 backlight enable", +- "eMMC reset", "LVDS bridge reset", +- "LVDS bridge power-down", +- "SDIO power enable", +- "", ""; +- }; +- +- sl28cpld_gpio3: gpio@1b { +- compatible = "kontron,sl28cpld-gpi"; +- reg = <0x1b>; +- +- gpio-controller; +- #gpio-cells = <2>; +- gpio-line-names = +- "Power button", "Force recovery", "Sleep", +- "Battery low", "Lid state", "Charging", +- "Charger present", ""; +- }; +- +- sl28cpld_intc: interrupt-controller@1c { +- compatible = "kontron,sl28cpld-intc"; +- reg = <0x1c>; +- interrupts-extended = <&gpio2 6 +- IRQ_TYPE_EDGE_FALLING>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c32"; +- reg = <0x50>; +- pagesize = <32>; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c32"; +- reg = <0x50>; +- pagesize = <32>; +- }; +-}; +- +-&lpuart1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-qds.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-qds.dts +deleted file mode 100644 +index 2f92e62ecafe..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-qds.dts ++++ /dev/null +@@ -1,341 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for NXP LS1028A QDS Board. +- * +- * Copyright 2018 NXP +- * +- * Harninder Rai +- * +- */ +- +-/dts-v1/; +- +-#include "fsl-ls1028a.dtsi" +- +-/ { +- model = "LS1028A QDS Board"; +- compatible = "fsl,ls1028a-qds", "fsl,ls1028a"; +- +- aliases { +- crypto = &crypto; +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- serial0 = &duart0; +- serial1 = &duart1; +- mmc0 = &esdhc; +- mmc1 = &esdhc1; +- rtc1 = &ftm_alarm0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x1 0x00000000>; +- }; +- +- sys_mclk: clock-mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- sb_3v3: regulator-sb3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3v3_vbus"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,widgets = +- "Microphone", "Microphone Jack", +- "Headphone", "Headphone Jack", +- "Speaker", "Speaker Ext", +- "Line", "Line In Jack"; +- simple-audio-card,routing = +- "MIC_IN", "Microphone Jack", +- "Microphone Jack", "Mic Bias", +- "LINE_IN", "Line In Jack", +- "Headphone Jack", "HP_OUT", +- "Speaker Ext", "LINE_OUT"; +- +- simple-audio-card,cpu { +- sound-dai = <&sai1>; +- frame-master; +- bitclock-master; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- frame-master; +- bitclock-master; +- system-clock-frequency = <25000000>; +- }; +- }; +- +- mdio-mux { +- compatible = "mdio-mux-multiplexer"; +- mux-controls = <&mux 0>; +- mdio-parent-bus = <&enetc_mdio_pf3>; +- #address-cells=<1>; +- #size-cells = <0>; +- +- /* on-board RGMII PHY */ +- mdio@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- qds_phy1: ethernet-phy@5 { +- /* Atheros 8035 */ +- reg = <5>; +- }; +- }; +- }; +-}; +- +-&can0 { +- status = "okay"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&dspi0 { +- bus-num = <0>; +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- spi-cpol; +- spi-cpha; +- reg = <0>; +- spi-max-frequency = <10000000>; +- }; +- +- flash@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- spi-cpol; +- spi-cpha; +- reg = <1>; +- spi-max-frequency = <10000000>; +- }; +- +- flash@2 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- spi-cpol; +- spi-cpha; +- reg = <2>; +- spi-max-frequency = <10000000>; +- }; +-}; +- +-&dspi1 { +- bus-num = <1>; +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- spi-cpol; +- spi-cpha; +- reg = <0>; +- spi-max-frequency = <10000000>; +- }; +- +- flash@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- spi-cpol; +- spi-cpha; +- reg = <1>; +- spi-max-frequency = <10000000>; +- }; +- +- flash@2 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- spi-cpol; +- spi-cpha; +- reg = <2>; +- spi-max-frequency = <10000000>; +- }; +-}; +- +-&dspi2 { +- bus-num = <2>; +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- spi-cpol; +- spi-cpha; +- reg = <0>; +- spi-max-frequency = <10000000>; +- }; +-}; +- +-&duart0 { +- status = "okay"; +-}; +- +-&duart1 { +- status = "okay"; +-}; +- +-&esdhc { +- status = "okay"; +-}; +- +-&esdhc1 { +- status = "okay"; +-}; +- +-&fspi { +- status = "okay"; +- +- mt35xu02g0: flash@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <50000000>; +- /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ +- spi-rx-bus-width = <8>; /* 8 SPI Rx lines */ +- spi-tx-bus-width = <1>; /* 1 SPI Tx line */ +- reg = <0>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- i2c-mux@77 { +- compatible = "nxp,pca9547"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; +- +- current-monitor@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <1000>; +- }; +- +- current-monitor@41 { +- compatible = "ti,ina220"; +- reg = <0x41>; +- shunt-resistor = <1000>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3>; +- +- temperature-sensor@4c { +- compatible = "nxp,sa56004"; +- reg = <0x4c>; +- vcc-supply = <&sb_3v3>; +- }; +- +- eeprom@56 { +- compatible = "atmel,24c512"; +- reg = <0x56>; +- }; +- +- eeprom@57 { +- compatible = "atmel,24c512"; +- reg = <0x57>; +- }; +- }; +- +- i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x5>; +- +- sgtl5000: audio-codec@a { +- #sound-dai-cells = <0>; +- compatible = "fsl,sgtl5000"; +- reg = <0xa>; +- VDDA-supply = <®_1p8v>; +- VDDIO-supply = <®_1p8v>; +- clocks = <&sys_mclk>; +- }; +- }; +- }; +- +- fpga@66 { +- compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c", +- "simple-mfd"; +- reg = <0x66>; +- +- mux: mux-controller { +- compatible = "reg-mux"; +- #mux-control-cells = <1>; +- mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */ +- }; +- }; +- +-}; +- +-&i2c1 { +- status = "okay"; +- +- rtc@51 { +- compatible = "nxp,pcf2129"; +- reg = <0x51>; +- }; +-}; +- +-&enetc_port1 { +- phy-handle = <&qds_phy1>; +- phy-connection-type = "rgmii-id"; +- status = "okay"; +-}; +- +-&lpuart0 { +- status = "okay"; +-}; +- +-&sai1 { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-rdb.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-rdb.dts +deleted file mode 100644 +index d7b527272500..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a-rdb.dts ++++ /dev/null +@@ -1,292 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for NXP LS1028A RDB Board. +- * +- * Copyright 2018 NXP +- * +- * Harninder Rai +- * +- */ +- +-/dts-v1/; +-#include "fsl-ls1028a.dtsi" +- +-/ { +- model = "LS1028A RDB Board"; +- compatible = "fsl,ls1028a-rdb", "fsl,ls1028a"; +- +- aliases { +- crypto = &crypto; +- serial0 = &duart0; +- serial1 = &duart1; +- mmc0 = &esdhc; +- mmc1 = &esdhc1; +- rtc1 = &ftm_alarm0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x1 0x0000000>; +- }; +- +- sys_mclk: clock-mclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- sb_3v3: regulator-sb3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3v3_vbus"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,widgets = +- "Microphone", "Microphone Jack", +- "Headphone", "Headphone Jack", +- "Speaker", "Speaker Ext", +- "Line", "Line In Jack"; +- simple-audio-card,routing = +- "MIC_IN", "Microphone Jack", +- "Microphone Jack", "Mic Bias", +- "LINE_IN", "Line In Jack", +- "Headphone Jack", "HP_OUT", +- "Speaker Ext", "LINE_OUT"; +- +- simple-audio-card,cpu { +- sound-dai = <&sai4>; +- frame-master; +- bitclock-master; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- frame-master; +- bitclock-master; +- system-clock-frequency = <25000000>; +- }; +- }; +-}; +- +-&can0 { +- status = "okay"; +- +- can-transceiver { +- max-bitrate = <5000000>; +- }; +-}; +- +-&can1 { +- status = "okay"; +- +- can-transceiver { +- max-bitrate = <5000000>; +- }; +-}; +- +-&esdhc { +- sd-uhs-sdr104; +- sd-uhs-sdr50; +- sd-uhs-sdr25; +- sd-uhs-sdr12; +- status = "okay"; +-}; +- +-&esdhc1 { +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- bus-width = <8>; +- status = "okay"; +-}; +- +-&fspi { +- status = "okay"; +- +- mt35xu02g0: flash@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <50000000>; +- /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ +- spi-rx-bus-width = <8>; /* 8 SPI Rx lines */ +- spi-tx-bus-width = <1>; /* 1 SPI Tx line */ +- reg = <0>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- i2c-mux@77 { +- compatible = "nxp,pca9847"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x1>; +- +- sgtl5000: audio-codec@a { +- #sound-dai-cells = <0>; +- compatible = "fsl,sgtl5000"; +- reg = <0xa>; +- VDDA-supply = <®_1p8v>; +- VDDIO-supply = <®_1p8v>; +- clocks = <&sys_mclk>; +- sclk-strength = <3>; +- }; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x02>; +- +- current-monitor@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <500>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3>; +- +- temperature-sensor@4c { +- compatible = "nxp,sa56004"; +- reg = <0x4c>; +- vcc-supply = <&sb_3v3>; +- }; +- +- rtc@51 { +- compatible = "nxp,pcf2129"; +- reg = <0x51>; +- }; +- }; +- }; +-}; +- +-&duart0 { +- status = "okay"; +-}; +- +-&duart1 { +- status = "okay"; +-}; +- +-&enetc_mdio_pf3 { +- /* VSC8514 QSGMII quad PHY */ +- qsgmii_phy0: ethernet-phy@10 { +- reg = <0x10>; +- }; +- +- qsgmii_phy1: ethernet-phy@11 { +- reg = <0x11>; +- }; +- +- qsgmii_phy2: ethernet-phy@12 { +- reg = <0x12>; +- }; +- +- qsgmii_phy3: ethernet-phy@13 { +- reg = <0x13>; +- }; +-}; +- +-&enetc_port0 { +- phy-handle = <&sgmii_phy0>; +- phy-connection-type = "sgmii"; +- managed = "in-band-status"; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- sgmii_phy0: ethernet-phy@2 { +- reg = <0x2>; +- }; +- }; +-}; +- +-&enetc_port2 { +- status = "okay"; +-}; +- +-&mscc_felix { +- status = "okay"; +-}; +- +-&mscc_felix_port0 { +- label = "swp0"; +- managed = "in-band-status"; +- phy-handle = <&qsgmii_phy0>; +- phy-mode = "qsgmii"; +- status = "okay"; +-}; +- +-&mscc_felix_port1 { +- label = "swp1"; +- managed = "in-band-status"; +- phy-handle = <&qsgmii_phy1>; +- phy-mode = "qsgmii"; +- status = "okay"; +-}; +- +-&mscc_felix_port2 { +- label = "swp2"; +- managed = "in-band-status"; +- phy-handle = <&qsgmii_phy2>; +- phy-mode = "qsgmii"; +- status = "okay"; +-}; +- +-&mscc_felix_port3 { +- label = "swp3"; +- managed = "in-band-status"; +- phy-handle = <&qsgmii_phy3>; +- phy-mode = "qsgmii"; +- status = "okay"; +-}; +- +-&mscc_felix_port4 { +- ethernet = <&enetc_port2>; +- status = "okay"; +-}; +- +-&optee { +- status = "okay"; +-}; +- +-&sai4 { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&usb1 { +- dr_mode = "otg"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a.dtsi +deleted file mode 100644 +index 06b36cc65865..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1028a.dtsi ++++ /dev/null +@@ -1,1162 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for NXP Layerscape-1028A family SoC. +- * +- * Copyright 2018-2020 NXP +- * +- * Harninder Rai +- * +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "fsl,ls1028a"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x0>; +- enable-method = "psci"; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- next-level-cache = <&l2>; +- cpu-idle-states = <&CPU_PW20>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x1>; +- enable-method = "psci"; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- next-level-cache = <&l2>; +- cpu-idle-states = <&CPU_PW20>; +- #cooling-cells = <2>; +- }; +- +- l2: l2-cache { +- compatible = "cache"; +- }; +- }; +- +- idle-states { +- /* +- * PSCI node is not added default, U-boot will add missing +- * parts if it determines to use PSCI. +- */ +- entry-method = "psci"; +- +- CPU_PW20: cpu-pw20 { +- compatible = "arm,idle-state"; +- idle-state-name = "PW20"; +- arm,psci-suspend-param = <0x0>; +- entry-latency-us = <2000>; +- exit-latency-us = <2000>; +- min-residency-us = <6000>; +- }; +- }; +- +- sysclk: sysclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- clock-output-names = "sysclk"; +- }; +- +- osc_27m: clock-osc-27m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- clock-output-names = "phy_27m"; +- }; +- +- dpclk: clock-controller@f1f0000 { +- compatible = "fsl,ls1028a-plldig"; +- reg = <0x0 0xf1f0000 0x0 0xffff>; +- #clock-cells = <0>; +- clocks = <&osc_27m>; +- }; +- +- firmware { +- optee: optee { +- compatible = "linaro,optee-tz"; +- method = "smc"; +- status = "disabled"; +- }; +- }; +- +- reboot { +- compatible ="syscon-reboot"; +- regmap = <&rst>; +- offset = <0>; +- mask = <0x02>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,cortex-a72-pmu"; +- interrupts = ; +- }; +- +- gic: interrupt-controller@6000000 { +- compatible= "arm,gic-v3"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ +- <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ +- #interrupt-cells= <3>; +- interrupt-controller; +- interrupts = ; +- its: gic-its@6020000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ +- }; +- }; +- +- thermal-zones { +- ddr-controller { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 0>; +- +- trips { +- ddr-ctrler-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- ddr-ctrler-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- core-cluster { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 1>; +- +- trips { +- core_cluster_alert: core-cluster-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- core_cluster_crit: core-cluster-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&core_cluster_alert>; +- cooling-device = +- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- soc: soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ddr: memory-controller@1080000 { +- compatible = "fsl,qoriq-memory-controller"; +- reg = <0x0 0x1080000 0x0 0x1000>; +- interrupts = ; +- little-endian; +- }; +- +- dcfg: syscon@1e00000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd"; +- reg = <0x0 0x1e00000 0x0 0x10000>; +- ranges = <0x0 0x0 0x1e00000 0x10000>; +- little-endian; +- +- fspi_clk: clock-controller@900 { +- compatible = "fsl,ls1028a-flexspi-clk"; +- reg = <0x900 0x4>; +- #clock-cells = <0>; +- clocks = <&clockgen QORIQ_CLK_HWACCEL 0>; +- clock-output-names = "fspi_clk"; +- }; +- }; +- +- rst: syscon@1e60000 { +- compatible = "syscon"; +- reg = <0x0 0x1e60000 0x0 0x10000>; +- little-endian; +- }; +- +- scfg: syscon@1fc0000 { +- compatible = "fsl,ls1028a-scfg", "syscon"; +- reg = <0x0 0x1fc0000 0x0 0x10000>; +- big-endian; +- }; +- +- clockgen: clock-controller@1300000 { +- compatible = "fsl,ls1028a-clockgen"; +- reg = <0x0 0x1300000 0x0 0xa0000>; +- #clock-cells = <2>; +- clocks = <&sysclk>; +- }; +- +- i2c0: i2c@2000000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2000000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- status = "disabled"; +- }; +- +- i2c1: i2c@2010000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2010000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- status = "disabled"; +- }; +- +- i2c2: i2c@2020000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2020000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- status = "disabled"; +- }; +- +- i2c3: i2c@2030000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2030000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- status = "disabled"; +- }; +- +- i2c4: i2c@2040000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2040000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- status = "disabled"; +- }; +- +- i2c5: i2c@2050000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2050000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- status = "disabled"; +- }; +- +- i2c6: i2c@2060000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2060000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- status = "disabled"; +- }; +- +- i2c7: i2c@2070000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2070000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- status = "disabled"; +- }; +- +- fspi: spi@20c0000 { +- compatible = "nxp,lx2160a-fspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x20c0000 0x0 0x10000>, +- <0x0 0x20000000 0x0 0x10000000>; +- reg-names = "fspi_base", "fspi_mmap"; +- interrupts = ; +- clocks = <&fspi_clk>, <&fspi_clk>; +- clock-names = "fspi_en", "fspi"; +- status = "disabled"; +- }; +- +- dspi0: spi@2100000 { +- compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2100000 0x0 0x10000>; +- interrupts = ; +- clock-names = "dspi"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- dmas = <&edma0 0 62>, <&edma0 0 60>; +- dma-names = "tx", "rx"; +- spi-num-chipselects = <4>; +- little-endian; +- status = "disabled"; +- }; +- +- dspi1: spi@2110000 { +- compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2110000 0x0 0x10000>; +- interrupts = ; +- clock-names = "dspi"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- dmas = <&edma0 0 58>, <&edma0 0 56>; +- dma-names = "tx", "rx"; +- spi-num-chipselects = <4>; +- little-endian; +- status = "disabled"; +- }; +- +- dspi2: spi@2120000 { +- compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2120000 0x0 0x10000>; +- interrupts = ; +- clock-names = "dspi"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- dmas = <&edma0 0 54>, <&edma0 0 2>; +- dma-names = "tx", "rx"; +- spi-num-chipselects = <3>; +- little-endian; +- status = "disabled"; +- }; +- +- esdhc: mmc@2140000 { +- compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; +- reg = <0x0 0x2140000 0x0 0x10000>; +- interrupts = ; +- clock-frequency = <0>; /* fixed up by bootloader */ +- clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; +- voltage-ranges = <1800 1800 3300 3300>; +- sdhci,auto-cmd12; +- little-endian; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- esdhc1: mmc@2150000 { +- compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; +- reg = <0x0 0x2150000 0x0 0x10000>; +- interrupts = ; +- clock-frequency = <0>; /* fixed up by bootloader */ +- clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; +- voltage-ranges = <1800 1800>; +- sdhci,auto-cmd12; +- non-removable; +- little-endian; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- can0: can@2180000 { +- compatible = "fsl,lx2160ar1-flexcan"; +- reg = <0x0 0x2180000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- can1: can@2190000 { +- compatible = "fsl,lx2160ar1-flexcan"; +- reg = <0x0 0x2190000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- duart0: serial@21c0500 { +- compatible = "fsl,ns16550", "ns16550a"; +- reg = <0x00 0x21c0500 0x0 0x100>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- status = "disabled"; +- }; +- +- duart1: serial@21c0600 { +- compatible = "fsl,ns16550", "ns16550a"; +- reg = <0x00 0x21c0600 0x0 0x100>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- status = "disabled"; +- }; +- +- +- lpuart0: serial@2260000 { +- compatible = "fsl,ls1028a-lpuart"; +- reg = <0x0 0x2260000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- clock-names = "ipg"; +- dma-names = "rx","tx"; +- dmas = <&edma0 1 32>, +- <&edma0 1 33>; +- status = "disabled"; +- }; +- +- lpuart1: serial@2270000 { +- compatible = "fsl,ls1028a-lpuart"; +- reg = <0x0 0x2270000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- clock-names = "ipg"; +- dma-names = "rx","tx"; +- dmas = <&edma0 1 30>, +- <&edma0 1 31>; +- status = "disabled"; +- }; +- +- lpuart2: serial@2280000 { +- compatible = "fsl,ls1028a-lpuart"; +- reg = <0x0 0x2280000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- clock-names = "ipg"; +- dma-names = "rx","tx"; +- dmas = <&edma0 1 28>, +- <&edma0 1 29>; +- status = "disabled"; +- }; +- +- lpuart3: serial@2290000 { +- compatible = "fsl,ls1028a-lpuart"; +- reg = <0x0 0x2290000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- clock-names = "ipg"; +- dma-names = "rx","tx"; +- dmas = <&edma0 1 26>, +- <&edma0 1 27>; +- status = "disabled"; +- }; +- +- lpuart4: serial@22a0000 { +- compatible = "fsl,ls1028a-lpuart"; +- reg = <0x0 0x22a0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- clock-names = "ipg"; +- dma-names = "rx","tx"; +- dmas = <&edma0 1 24>, +- <&edma0 1 25>; +- status = "disabled"; +- }; +- +- lpuart5: serial@22b0000 { +- compatible = "fsl,ls1028a-lpuart"; +- reg = <0x0 0x22b0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- clock-names = "ipg"; +- dma-names = "rx","tx"; +- dmas = <&edma0 1 22>, +- <&edma0 1 23>; +- status = "disabled"; +- }; +- +- edma0: dma-controller@22c0000 { +- #dma-cells = <2>; +- compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; +- reg = <0x0 0x22c0000 0x0 0x10000>, +- <0x0 0x22d0000 0x0 0x10000>, +- <0x0 0x22e0000 0x0 0x10000>; +- interrupts = , +- ; +- interrupt-names = "edma-tx", "edma-err"; +- dma-channels = <32>; +- clock-names = "dmamux0", "dmamux1"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- }; +- +- gpio1: gpio@2300000 { +- compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; +- reg = <0x0 0x2300000 0x0 0x10000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- little-endian; +- }; +- +- gpio2: gpio@2310000 { +- compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; +- reg = <0x0 0x2310000 0x0 0x10000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- little-endian; +- }; +- +- gpio3: gpio@2320000 { +- compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; +- reg = <0x0 0x2320000 0x0 0x10000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- little-endian; +- }; +- +- usb0: usb@3100000 { +- compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; +- reg = <0x0 0x3100000 0x0 0x10000>; +- interrupts = ; +- dr_mode = "host"; +- snps,dis_rxdet_inp3_quirk; +- snps,quirk-frame-length-adjustment = <0x20>; +- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; +- }; +- +- usb1: usb@3110000 { +- compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; +- reg = <0x0 0x3110000 0x0 0x10000>; +- interrupts = ; +- dr_mode = "host"; +- snps,dis_rxdet_inp3_quirk; +- snps,quirk-frame-length-adjustment = <0x20>; +- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; +- }; +- +- sata: sata@3200000 { +- compatible = "fsl,ls1028a-ahci"; +- reg = <0x0 0x3200000 0x0 0x10000>, +- <0x7 0x100520 0x0 0x4>; +- reg-names = "ahci", "sata-ecc"; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- status = "disabled"; +- }; +- +- pcie1: pcie@3400000 { +- compatible = "fsl,ls1028a-pcie"; +- reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ +- <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "regs", "config"; +- interrupts = , /* PME interrupt */ +- ; /* aer interrupt */ +- interrupt-names = "pme", "aer"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- num-viewport = <8>; +- bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ +- 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&its>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; +- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ +- status = "disabled"; +- }; +- +- pcie2: pcie@3500000 { +- compatible = "fsl,ls1028a-pcie"; +- reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ +- <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "regs", "config"; +- interrupts = , +- ; +- interrupt-names = "pme", "aer"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- num-viewport = <8>; +- bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ +- 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&its>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; +- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ +- status = "disabled"; +- }; +- +- smmu: iommu@5000000 { +- compatible = "arm,mmu-500"; +- reg = <0 0x5000000 0 0x800000>; +- #global-interrupts = <8>; +- #iommu-cells = <1>; +- stream-match-mask = <0x7c00>; +- /* global secure fault */ +- interrupts = , +- /* combined secure interrupt */ +- , +- /* global non-secure fault */ +- , +- /* combined non-secure interrupt */ +- , +- /* performance counter interrupts 0-7 */ +- , , +- , , +- /* per context interrupt, 64 interrupts */ +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , , +- , ; +- }; +- +- crypto: crypto@8000000 { +- compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; +- fsl,sec-era = <10>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x00 0x8000000 0x100000>; +- reg = <0x00 0x8000000 0x0 0x100000>; +- interrupts = ; +- dma-coherent; +- +- sec_jr0: jr@10000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x10000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr1: jr@20000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x20000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr2: jr@30000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x30000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr3: jr@40000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x40000 0x10000>; +- interrupts = ; +- }; +- }; +- +- qdma: dma-controller@8380000 { +- compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; +- reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ +- <0x0 0x8390000 0x0 0x10000>, /* Status regs */ +- <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ +- interrupts = , +- , +- , +- , +- ; +- interrupt-names = "qdma-error", "qdma-queue0", +- "qdma-queue1", "qdma-queue2", "qdma-queue3"; +- dma-channels = <8>; +- block-number = <1>; +- block-offset = <0x10000>; +- fsl,dma-queues = <2>; +- status-sizes = <64>; +- queue-sizes = <64 64>; +- }; +- +- cluster1_core0_watchdog: watchdog@c000000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xc000000 0x0 0x1000>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- cluster1_core1_watchdog: watchdog@c010000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xc010000 0x0 0x1000>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- sai1: audio-controller@f100000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,vf610-sai"; +- reg = <0x0 0xf100000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dma-names = "tx", "rx"; +- dmas = <&edma0 1 4>, +- <&edma0 1 3>; +- fsl,sai-asynchronous; +- status = "disabled"; +- }; +- +- sai2: audio-controller@f110000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,vf610-sai"; +- reg = <0x0 0xf110000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dma-names = "tx", "rx"; +- dmas = <&edma0 1 6>, +- <&edma0 1 5>; +- fsl,sai-asynchronous; +- status = "disabled"; +- }; +- +- sai3: audio-controller@f120000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,vf610-sai"; +- reg = <0x0 0xf120000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dma-names = "tx", "rx"; +- dmas = <&edma0 1 8>, +- <&edma0 1 7>; +- fsl,sai-asynchronous; +- status = "disabled"; +- }; +- +- sai4: audio-controller@f130000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,vf610-sai"; +- reg = <0x0 0xf130000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dma-names = "tx", "rx"; +- dmas = <&edma0 1 10>, +- <&edma0 1 9>; +- fsl,sai-asynchronous; +- status = "disabled"; +- }; +- +- sai5: audio-controller@f140000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,vf610-sai"; +- reg = <0x0 0xf140000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dma-names = "tx", "rx"; +- dmas = <&edma0 1 12>, +- <&edma0 1 11>; +- fsl,sai-asynchronous; +- status = "disabled"; +- }; +- +- sai6: audio-controller@f150000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,vf610-sai"; +- reg = <0x0 0xf150000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dma-names = "tx", "rx"; +- dmas = <&edma0 1 14>, +- <&edma0 1 13>; +- fsl,sai-asynchronous; +- status = "disabled"; +- }; +- +- tmu: tmu@1f80000 { +- compatible = "fsl,qoriq-tmu"; +- reg = <0x0 0x1f80000 0x0 0x10000>; +- interrupts = <0 23 0x4>; +- fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; +- fsl,tmu-calibration = <0x00000000 0x00000024 +- 0x00000001 0x0000002b +- 0x00000002 0x00000031 +- 0x00000003 0x00000038 +- 0x00000004 0x0000003f +- 0x00000005 0x00000045 +- 0x00000006 0x0000004c +- 0x00000007 0x00000053 +- 0x00000008 0x00000059 +- 0x00000009 0x00000060 +- 0x0000000a 0x00000066 +- 0x0000000b 0x0000006d +- +- 0x00010000 0x0000001c +- 0x00010001 0x00000024 +- 0x00010002 0x0000002c +- 0x00010003 0x00000035 +- 0x00010004 0x0000003d +- 0x00010005 0x00000045 +- 0x00010006 0x0000004d +- 0x00010007 0x00000055 +- 0x00010008 0x0000005e +- 0x00010009 0x00000066 +- 0x0001000a 0x0000006e +- +- 0x00020000 0x00000018 +- 0x00020001 0x00000022 +- 0x00020002 0x0000002d +- 0x00020003 0x00000038 +- 0x00020004 0x00000043 +- 0x00020005 0x0000004d +- 0x00020006 0x00000058 +- 0x00020007 0x00000063 +- 0x00020008 0x0000006e +- +- 0x00030000 0x00000010 +- 0x00030001 0x0000001c +- 0x00030002 0x00000029 +- 0x00030003 0x00000036 +- 0x00030004 0x00000042 +- 0x00030005 0x0000004f +- 0x00030006 0x0000005b +- 0x00030007 0x00000068>; +- little-endian; +- #thermal-sensor-cells = <1>; +- }; +- +- pcie@1f0000000 { /* Integrated Endpoint Root Complex */ +- compatible = "pci-host-ecam-generic"; +- reg = <0x01 0xf0000000 0x0 0x100000>; +- #address-cells = <3>; +- #size-cells = <2>; +- msi-parent = <&its>; +- device_type = "pci"; +- bus-range = <0x0 0x0>; +- dma-coherent; +- msi-map = <0 &its 0x17 0xe>; +- iommu-map = <0 &smmu 0x17 0xe>; +- /* PF0-6 BAR0 - non-prefetchable memory */ +- ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000 +- /* PF0-6 BAR2 - prefetchable memory */ +- 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000 +- /* PF0: VF0-1 BAR0 - non-prefetchable memory */ +- 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000 +- /* PF0: VF0-1 BAR2 - prefetchable memory */ +- 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000 +- /* PF1: VF0-1 BAR0 - non-prefetchable memory */ +- 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000 +- /* PF1: VF0-1 BAR2 - prefetchable memory */ +- 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000 +- /* BAR4 (PF5) - non-prefetchable memory */ +- 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>; +- +- enetc_port0: ethernet@0,0 { +- compatible = "fsl,enetc"; +- reg = <0x000000 0 0 0 0>; +- status = "disabled"; +- }; +- +- enetc_port1: ethernet@0,1 { +- compatible = "fsl,enetc"; +- reg = <0x000100 0 0 0 0>; +- status = "disabled"; +- }; +- +- enetc_port2: ethernet@0,2 { +- compatible = "fsl,enetc"; +- reg = <0x000200 0 0 0 0>; +- phy-mode = "internal"; +- status = "disabled"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- }; +- }; +- +- enetc_mdio_pf3: mdio@0,3 { +- compatible = "fsl,enetc-mdio"; +- reg = <0x000300 0 0 0 0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- ethernet@0,4 { +- compatible = "fsl,enetc-ptp"; +- reg = <0x000400 0 0 0 0>; +- clocks = <&clockgen QORIQ_CLK_HWACCEL 3>; +- little-endian; +- fsl,extts-fifo; +- }; +- +- mscc_felix: ethernet-switch@0,5 { +- reg = <0x000500 0 0 0 0>; +- /* IEP INT_B */ +- interrupts = ; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* External ports */ +- mscc_felix_port0: port@0 { +- reg = <0>; +- status = "disabled"; +- }; +- +- mscc_felix_port1: port@1 { +- reg = <1>; +- status = "disabled"; +- }; +- +- mscc_felix_port2: port@2 { +- reg = <2>; +- status = "disabled"; +- }; +- +- mscc_felix_port3: port@3 { +- reg = <3>; +- status = "disabled"; +- }; +- +- /* Internal ports */ +- mscc_felix_port4: port@4 { +- reg = <4>; +- phy-mode = "internal"; +- status = "disabled"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- }; +- }; +- +- mscc_felix_port5: port@5 { +- reg = <5>; +- phy-mode = "internal"; +- status = "disabled"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; +- +- enetc_port3: ethernet@0,6 { +- compatible = "fsl,enetc"; +- reg = <0x000600 0 0 0 0>; +- phy-mode = "internal"; +- status = "disabled"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- rcec@1f,0 { +- reg = <0x00f800 0 0 0 0>; +- /* IEP INT_A */ +- interrupts = ; +- }; +- }; +- +- /* Integrated Endpoint Register Block */ +- ierb@1f0800000 { +- compatible = "fsl,ls1028a-enetc-ierb"; +- reg = <0x01 0xf0800000 0x0 0x10000>; +- }; +- +- rcpm: power-controller@1e34040 { +- compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; +- reg = <0x0 0x1e34040 0x0 0x1c>; +- #fsl,rcpm-wakeup-cells = <7>; +- little-endian; +- }; +- +- ftm_alarm0: timer@2800000 { +- compatible = "fsl,ls1028a-ftm-alarm"; +- reg = <0x0 0x2800000 0x0 0x10000>; +- fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; +- interrupts = ; +- }; +- }; +- +- malidp0: display@f080000 { +- compatible = "arm,mali-dp500"; +- reg = <0x0 0xf080000 0x0 0x10000>; +- interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, +- <0 223 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "DE", "SE"; +- clocks = <&dpclk>, +- <&clockgen QORIQ_CLK_HWACCEL 2>, +- <&clockgen QORIQ_CLK_HWACCEL 2>, +- <&clockgen QORIQ_CLK_HWACCEL 2>; +- clock-names = "pxlclk", "mclk", "aclk", "pclk"; +- arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; +- arm,malidp-arqos-value = <0xd000d000>; +- +- port { +- dp0_out: endpoint { +- +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1043-post.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1043-post.dtsi +deleted file mode 100644 +index d237162a8744..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1043-post.dtsi ++++ /dev/null +@@ -1,46 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * QorIQ FMan v3 device tree nodes for ls1043 +- * +- * Copyright 2015-2016 Freescale Semiconductor Inc. +- */ +- +-&soc { +- +-/* include used FMan blocks */ +-#include "qoriq-fman3-0.dtsi" +-#include "qoriq-fman3-0-1g-0.dtsi" +-#include "qoriq-fman3-0-1g-1.dtsi" +-#include "qoriq-fman3-0-1g-2.dtsi" +-#include "qoriq-fman3-0-1g-3.dtsi" +-#include "qoriq-fman3-0-1g-4.dtsi" +-#include "qoriq-fman3-0-1g-5.dtsi" +-#include "qoriq-fman3-0-10g-0.dtsi" +- +-}; +- +-&fman0 { +- fsl,erratum-a050385; +- +- /* these aliases provide the FMan ports mapping */ +- enet0: ethernet@e0000 { +- }; +- +- enet1: ethernet@e2000 { +- }; +- +- enet2: ethernet@e4000 { +- }; +- +- enet3: ethernet@e6000 { +- }; +- +- enet4: ethernet@e8000 { +- }; +- +- enet5: ethernet@ea000 { +- }; +- +- enet6: ethernet@f0000 { +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1043a-qds.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1043a-qds.dts +deleted file mode 100644 +index fea167d222cf..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1043a-qds.dts ++++ /dev/null +@@ -1,155 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Freescale Layerscape-1043A family SoC. +- * +- * Copyright 2014-2015 Freescale Semiconductor, Inc. +- * Copyright 2018 NXP +- * +- * Mingkai Hu +- */ +- +-/dts-v1/; +-#include "fsl-ls1043a.dtsi" +- +-/ { +- model = "LS1043A QDS Board"; +- compatible = "fsl,ls1043a-qds", "fsl,ls1043a"; +- +- aliases { +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- gpio3 = &gpio4; +- serial0 = &duart0; +- serial1 = &duart1; +- serial2 = &duart2; +- serial3 = &duart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&duart0 { +- status = "okay"; +-}; +- +-&duart1 { +- status = "okay"; +-}; +- +-&ifc { +- #address-cells = <2>; +- #size-cells = <1>; +- /* NOR, NAND Flashes and FPGA on board */ +- ranges = <0x0 0x0 0x0 0x60000000 0x08000000 +- 0x1 0x0 0x0 0x7e800000 0x00010000 +- 0x2 0x0 0x0 0x7fb00000 0x00000100>; +- status = "okay"; +- +- nor@0,0 { +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- big-endian; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@1,0 { +- compatible = "fsl,ifc-nand"; +- reg = <0x1 0x0 0x10000>; +- }; +- +- fpga: board-control@2,0 { +- compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis"; +- reg = <0x2 0x0 0x0000100>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- pca9547@77 { +- compatible = "nxp,pca9547"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0>; +- +- rtc@68 { +- compatible = "dallas,ds3232"; +- reg = <0x68>; +- /* IRQ10_B */ +- interrupts = <0 150 0x4>; +- }; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; +- +- ina220@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <1000>; +- }; +- +- ina220@41 { +- compatible = "ti,ina220"; +- reg = <0x41>; +- shunt-resistor = <1000>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3>; +- +- eeprom@56 { +- compatible = "atmel,24c512"; +- reg = <0x56>; +- }; +- +- eeprom@57 { +- compatible = "atmel,24c512"; +- reg = <0x57>; +- }; +- +- temp-sensor@4c { +- compatible = "adi,adt7461a"; +- reg = <0x4c>; +- }; +- }; +- }; +-}; +- +-&lpuart0 { +- status = "okay"; +-}; +- +-&qspi { +- status = "okay"; +- +- qflash0: flash@0 { +- compatible = "spansion,m25p80"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <20000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <4>; +- reg = <0>; +- }; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-#include "fsl-ls1043-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1043a-rdb.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1043a-rdb.dts +deleted file mode 100644 +index 3516af4726a5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1043a-rdb.dts ++++ /dev/null +@@ -1,219 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Freescale Layerscape-1043A family SoC. +- * +- * Copyright 2014-2015 Freescale Semiconductor, Inc. +- * Copyright 2018 NXP +- * +- * Mingkai Hu +- */ +- +-/dts-v1/; +-#include "fsl-ls1043a.dtsi" +- +-/ { +- model = "LS1043A RDB Board"; +- compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; +- +- aliases { +- serial0 = &duart0; +- serial1 = &duart1; +- serial2 = &duart2; +- serial3 = &duart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- ina220@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <1000>; +- }; +- adt7461a@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- eeprom@52 { +- compatible = "atmel,24c512"; +- reg = <0x52>; +- }; +- eeprom@53 { +- compatible = "atmel,24c512"; +- reg = <0x53>; +- }; +- rtc@68 { +- compatible = "pericom,pt7c4338"; +- reg = <0x68>; +- }; +-}; +- +-&ifc { +- status = "okay"; +- #address-cells = <2>; +- #size-cells = <1>; +- /* NOR, NAND Flashes and FPGA on board */ +- ranges = <0x0 0x0 0x0 0x60000000 0x08000000 +- 0x1 0x0 0x0 0x7e800000 0x00010000 +- 0x2 0x0 0x0 0x7fb00000 0x00000100>; +- +- nor@0,0 { +- compatible = "cfi-flash"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x0 0x0 0x8000000>; +- big-endian; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@1,0 { +- compatible = "fsl,ifc-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x1 0x0 0x10000>; +- }; +- +- cpld: board-control@2,0 { +- compatible = "fsl,ls1043ardb-cpld"; +- reg = <0x2 0x0 0x0000100>; +- }; +-}; +- +-&dspi0 { +- bus-num = <0>; +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */ +- reg = <0>; +- spi-max-frequency = <1000000>; /* input clock */ +- }; +- +- slic@2 { +- compatible = "maxim,ds26522"; +- reg = <2>; +- spi-max-frequency = <2000000>; +- fsl,spi-cs-sck-delay = <100>; +- fsl,spi-sck-cs-delay = <50>; +- }; +- +- slic@3 { +- compatible = "maxim,ds26522"; +- reg = <3>; +- spi-max-frequency = <2000000>; +- fsl,spi-cs-sck-delay = <100>; +- fsl,spi-sck-cs-delay = <50>; +- }; +-}; +- +-&duart0 { +- status = "okay"; +-}; +- +-&duart1 { +- status = "okay"; +-}; +- +-#include "fsl-ls1043-post.dtsi" +- +-&fman0 { +- ethernet@e0000 { +- phy-handle = <&qsgmii_phy1>; +- phy-connection-type = "qsgmii"; +- }; +- +- ethernet@e2000 { +- phy-handle = <&qsgmii_phy2>; +- phy-connection-type = "qsgmii"; +- }; +- +- ethernet@e4000 { +- phy-handle = <&rgmii_phy1>; +- phy-connection-type = "rgmii-id"; +- }; +- +- ethernet@e6000 { +- phy-handle = <&rgmii_phy2>; +- phy-connection-type = "rgmii-id"; +- }; +- +- ethernet@e8000 { +- phy-handle = <&qsgmii_phy3>; +- phy-connection-type = "qsgmii"; +- }; +- +- ethernet@ea000 { +- phy-handle = <&qsgmii_phy4>; +- phy-connection-type = "qsgmii"; +- }; +- +- ethernet@f0000 { /* 10GEC1 */ +- phy-handle = <&aqr105_phy>; +- phy-connection-type = "xgmii"; +- }; +- +- mdio@fc000 { +- rgmii_phy1: ethernet-phy@1 { +- reg = <0x1>; +- }; +- +- rgmii_phy2: ethernet-phy@2 { +- reg = <0x2>; +- }; +- +- qsgmii_phy1: ethernet-phy@4 { +- reg = <0x4>; +- }; +- +- qsgmii_phy2: ethernet-phy@5 { +- reg = <0x5>; +- }; +- +- qsgmii_phy3: ethernet-phy@6 { +- reg = <0x6>; +- }; +- +- qsgmii_phy4: ethernet-phy@7 { +- reg = <0x7>; +- }; +- }; +- +- mdio@fd000 { +- aqr105_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- interrupts = <0 132 4>; +- reg = <0x1>; +- }; +- }; +-}; +- +-&uqe { +- ucc_hdlc: ucc@2000 { +- compatible = "fsl,ucc-hdlc"; +- rx-clock-name = "clk8"; +- tx-clock-name = "clk9"; +- fsl,rx-sync-clock = "rsync_pin"; +- fsl,tx-sync-clock = "tsync_pin"; +- fsl,tx-timeslot-mask = <0xfffffffe>; +- fsl,rx-timeslot-mask = <0xfffffffe>; +- fsl,tdm-framer-type = "e1"; +- fsl,tdm-id = <0>; +- fsl,siram-entry-id = <0>; +- fsl,tdm-interface; +- }; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1043a.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1043a.dtsi +deleted file mode 100644 +index 01b01e320411..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1043a.dtsi ++++ /dev/null +@@ -1,994 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for NXP Layerscape-1043A family SoC. +- * +- * Copyright 2014-2015 Freescale Semiconductor, Inc. +- * Copyright 2018, 2020 NXP +- * +- * Mingkai Hu +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "fsl,ls1043a"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- crypto = &crypto; +- fman0 = &fman0; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- ethernet4 = &enet4; +- ethernet5 = &enet5; +- ethernet6 = &enet6; +- rtc1 = &ftm_alarm0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* +- * We expect the enable-method for cpu's to be "psci", but this +- * is dependent on the SoC FW, which will fill this in. +- * +- * Currently supported enable-method is psci v0.2 +- */ +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0>; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- next-level-cache = <&l2>; +- cpu-idle-states = <&CPU_PH20>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x1>; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- next-level-cache = <&l2>; +- cpu-idle-states = <&CPU_PH20>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x2>; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- next-level-cache = <&l2>; +- cpu-idle-states = <&CPU_PH20>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x3>; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- next-level-cache = <&l2>; +- cpu-idle-states = <&CPU_PH20>; +- #cooling-cells = <2>; +- }; +- +- l2: l2-cache { +- compatible = "cache"; +- }; +- }; +- +- idle-states { +- /* +- * PSCI node is not added default, U-boot will add missing +- * parts if it determines to use PSCI. +- */ +- entry-method = "psci"; +- +- CPU_PH20: cpu-ph20 { +- compatible = "arm,idle-state"; +- idle-state-name = "PH20"; +- arm,psci-suspend-param = <0x0>; +- entry-latency-us = <1000>; +- exit-latency-us = <1000>; +- min-residency-us = <3000>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0 0x80000000>; +- /* DRAM space 1, size: 2GiB DRAM */ +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- compatible = "shared-dma-pool"; +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- no-map; +- }; +- +- qman_fqd: qman-fqd { +- compatible = "shared-dma-pool"; +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- no-map; +- }; +- +- qman_pfdr: qman-pfdr { +- compatible = "shared-dma-pool"; +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- no-map; +- }; +- }; +- +- sysclk: sysclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- clock-output-names = "sysclk"; +- }; +- +- reboot { +- compatible ="syscon-reboot"; +- regmap = <&dcfg>; +- offset = <0xb0>; +- mask = <0x02>; +- }; +- +- thermal-zones { +- ddr-controller { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 0>; +- +- trips { +- ddr-ctrler-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- ddr-ctrler-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- serdes { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 1>; +- +- trips { +- serdes-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- serdes-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- fman { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 2>; +- +- trips { +- fman-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- fman-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- core-cluster { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 3>; +- +- trips { +- core_cluster_alert: core-cluster-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- core_cluster_crit: core-cluster-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&core_cluster_alert>; +- cooling-device = +- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- sec { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 4>; +- +- trips { +- sec-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- sec-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = <1 13 0xf08>, /* Physical Secure PPI */ +- <1 14 0xf08>, /* Physical Non-Secure PPI */ +- <1 11 0xf08>, /* Virtual PPI */ +- <1 10 0xf08>; /* Hypervisor PPI */ +- fsl,erratum-a008585; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = <0 106 0x4>, +- <0 107 0x4>, +- <0 95 0x4>, +- <0 97 0x4>; +- interrupt-affinity = <&cpu0>, +- <&cpu1>, +- <&cpu2>, +- <&cpu3>; +- }; +- +- gic: interrupt-controller@1400000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x0 0x1401000 0 0x1000>, /* GICD */ +- <0x0 0x1402000 0 0x2000>, /* GICC */ +- <0x0 0x1404000 0 0x2000>, /* GICH */ +- <0x0 0x1406000 0 0x2000>; /* GICV */ +- interrupts = <1 9 0xf08>; +- }; +- +- soc: soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clockgen: clocking@1ee1000 { +- compatible = "fsl,ls1043a-clockgen"; +- reg = <0x0 0x1ee1000 0x0 0x1000>; +- #clock-cells = <2>; +- clocks = <&sysclk>; +- }; +- +- scfg: scfg@1570000 { +- compatible = "fsl,ls1043a-scfg", "syscon"; +- reg = <0x0 0x1570000 0x0 0x10000>; +- big-endian; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1570000 0x10000>; +- +- extirq: interrupt-controller@1ac { +- compatible = "fsl,ls1043a-extirq"; +- #interrupt-cells = <2>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x1ac 4>; +- interrupt-map = +- <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, +- <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, +- <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, +- <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, +- <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, +- <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, +- <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, +- <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, +- <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, +- <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, +- <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, +- <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-map-mask = <0xffffffff 0x0>; +- }; +- }; +- +- crypto: crypto@1700000 { +- compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", +- "fsl,sec-v4.0"; +- fsl,sec-era = <3>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x00 0x1700000 0x100000>; +- reg = <0x00 0x1700000 0x0 0x100000>; +- interrupts = <0 75 0x4>; +- dma-coherent; +- +- sec_jr0: jr@10000 { +- compatible = "fsl,sec-v5.4-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x10000 0x10000>; +- interrupts = <0 71 0x4>; +- }; +- +- sec_jr1: jr@20000 { +- compatible = "fsl,sec-v5.4-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x20000 0x10000>; +- interrupts = <0 72 0x4>; +- }; +- +- sec_jr2: jr@30000 { +- compatible = "fsl,sec-v5.4-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x30000 0x10000>; +- interrupts = <0 73 0x4>; +- }; +- +- sec_jr3: jr@40000 { +- compatible = "fsl,sec-v5.4-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x40000 0x10000>; +- interrupts = <0 74 0x4>; +- }; +- }; +- +- dcfg: dcfg@1ee0000 { +- compatible = "fsl,ls1043a-dcfg", "syscon"; +- reg = <0x0 0x1ee0000 0x0 0x10000>; +- big-endian; +- }; +- +- ifc: ifc@1530000 { +- compatible = "fsl,ifc", "simple-bus"; +- reg = <0x0 0x1530000 0x0 0x10000>; +- interrupts = <0 43 0x4>; +- }; +- +- qspi: spi@1550000 { +- compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x1550000 0x0 0x10000>, +- <0x0 0x40000000 0x0 0x4000000>; +- reg-names = "QuadSPI", "QuadSPI-memory"; +- interrupts = <0 99 0x4>; +- clock-names = "qspi_en", "qspi"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- status = "disabled"; +- }; +- +- esdhc: esdhc@1560000 { +- compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; +- reg = <0x0 0x1560000 0x0 0x10000>; +- interrupts = <0 62 0x4>; +- clock-frequency = <0>; +- voltage-ranges = <1800 1800 3300 3300>; +- sdhci,auto-cmd12; +- big-endian; +- bus-width = <4>; +- }; +- +- ddr: memory-controller@1080000 { +- compatible = "fsl,qoriq-memory-controller"; +- reg = <0x0 0x1080000 0x0 0x1000>; +- interrupts = <0 144 0x4>; +- big-endian; +- }; +- +- tmu: tmu@1f00000 { +- compatible = "fsl,qoriq-tmu"; +- reg = <0x0 0x1f00000 0x0 0x10000>; +- interrupts = <0 33 0x4>; +- fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; +- fsl,tmu-calibration = <0x00000000 0x00000023 +- 0x00000001 0x0000002a +- 0x00000002 0x00000031 +- 0x00000003 0x00000037 +- 0x00000004 0x0000003e +- 0x00000005 0x00000044 +- 0x00000006 0x0000004b +- 0x00000007 0x00000051 +- 0x00000008 0x00000058 +- 0x00000009 0x0000005e +- 0x0000000a 0x00000065 +- 0x0000000b 0x0000006b +- +- 0x00010000 0x00000023 +- 0x00010001 0x0000002b +- 0x00010002 0x00000033 +- 0x00010003 0x0000003b +- 0x00010004 0x00000043 +- 0x00010005 0x0000004b +- 0x00010006 0x00000054 +- 0x00010007 0x0000005c +- 0x00010008 0x00000064 +- 0x00010009 0x0000006c +- +- 0x00020000 0x00000021 +- 0x00020001 0x0000002c +- 0x00020002 0x00000036 +- 0x00020003 0x00000040 +- 0x00020004 0x0000004b +- 0x00020005 0x00000055 +- 0x00020006 0x0000005f +- +- 0x00030000 0x00000013 +- 0x00030001 0x0000001d +- 0x00030002 0x00000028 +- 0x00030003 0x00000032 +- 0x00030004 0x0000003d +- 0x00030005 0x00000047 +- 0x00030006 0x00000052 +- 0x00030007 0x0000005c>; +- #thermal-sensor-cells = <1>; +- }; +- +- qman: qman@1880000 { +- compatible = "fsl,qman"; +- reg = <0x0 0x1880000 0x0 0x10000>; +- interrupts = ; +- memory-region = <&qman_fqd &qman_pfdr>; +- }; +- +- bman: bman@1890000 { +- compatible = "fsl,bman"; +- reg = <0x0 0x1890000 0x0 0x10000>; +- interrupts = ; +- memory-region = <&bman_fbpr>; +- }; +- +- bportals: bman-portals@508000000 { +- ranges = <0x0 0x5 0x08000000 0x8000000>; +- }; +- +- qportals: qman-portals@500000000 { +- ranges = <0x0 0x5 0x00000000 0x8000000>; +- }; +- +- dspi0: spi@2100000 { +- compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2100000 0x0 0x10000>; +- interrupts = <0 64 0x4>; +- clock-names = "dspi"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- spi-num-chipselects = <5>; +- big-endian; +- status = "disabled"; +- }; +- +- dspi1: spi@2110000 { +- compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2110000 0x0 0x10000>; +- interrupts = <0 65 0x4>; +- clock-names = "dspi"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- spi-num-chipselects = <5>; +- big-endian; +- status = "disabled"; +- }; +- +- i2c0: i2c@2180000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2180000 0x0 0x10000>; +- interrupts = <0 56 0x4>; +- clock-names = "i2c"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- dmas = <&edma0 1 39>, +- <&edma0 1 38>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- i2c1: i2c@2190000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2190000 0x0 0x10000>; +- interrupts = <0 57 0x4>; +- clock-names = "i2c"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- status = "disabled"; +- }; +- +- i2c2: i2c@21a0000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x21a0000 0x0 0x10000>; +- interrupts = <0 58 0x4>; +- clock-names = "i2c"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- status = "disabled"; +- }; +- +- i2c3: i2c@21b0000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x21b0000 0x0 0x10000>; +- interrupts = <0 59 0x4>; +- clock-names = "i2c"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- status = "disabled"; +- }; +- +- duart0: serial@21c0500 { +- compatible = "fsl,ns16550", "ns16550a"; +- reg = <0x00 0x21c0500 0x0 0x100>; +- interrupts = <0 54 0x4>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- }; +- +- duart1: serial@21c0600 { +- compatible = "fsl,ns16550", "ns16550a"; +- reg = <0x00 0x21c0600 0x0 0x100>; +- interrupts = <0 54 0x4>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- }; +- +- duart2: serial@21d0500 { +- compatible = "fsl,ns16550", "ns16550a"; +- reg = <0x0 0x21d0500 0x0 0x100>; +- interrupts = <0 55 0x4>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- }; +- +- duart3: serial@21d0600 { +- compatible = "fsl,ns16550", "ns16550a"; +- reg = <0x0 0x21d0600 0x0 0x100>; +- interrupts = <0 55 0x4>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- }; +- +- gpio1: gpio@2300000 { +- compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; +- reg = <0x0 0x2300000 0x0 0x10000>; +- interrupts = <0 66 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@2310000 { +- compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; +- reg = <0x0 0x2310000 0x0 0x10000>; +- interrupts = <0 67 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio@2320000 { +- compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; +- reg = <0x0 0x2320000 0x0 0x10000>; +- interrupts = <0 68 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio4: gpio@2330000 { +- compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; +- reg = <0x0 0x2330000 0x0 0x10000>; +- interrupts = <0 134 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- uqe: uqe@2400000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,qe", "simple-bus"; +- ranges = <0x0 0x0 0x2400000 0x40000>; +- reg = <0x0 0x2400000 0x0 0x480>; +- brg-frequency = <100000000>; +- bus-frequency = <200000000>; +- fsl,qe-num-riscs = <1>; +- fsl,qe-num-snums = <28>; +- +- qeic: qeic@80 { +- compatible = "fsl,qe-ic"; +- reg = <0x80 0x80>; +- #address-cells = <0>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupts = , +- ; +- }; +- +- si1: si@700 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,ls1043-qe-si", +- "fsl,t1040-qe-si"; +- reg = <0x700 0x80>; +- }; +- +- siram1: siram@1000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,ls1043-qe-siram", +- "fsl,t1040-qe-siram"; +- reg = <0x1000 0x800>; +- }; +- +- ucc@2000 { +- cell-index = <1>; +- reg = <0x2000 0x200>; +- interrupts = <32>; +- interrupt-parent = <&qeic>; +- }; +- +- ucc@2200 { +- cell-index = <3>; +- reg = <0x2200 0x200>; +- interrupts = <34>; +- interrupt-parent = <&qeic>; +- }; +- +- muram@10000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,qe-muram", "fsl,cpm-muram"; +- ranges = <0x0 0x10000 0x6000>; +- +- data-only@0 { +- compatible = "fsl,qe-muram-data", +- "fsl,cpm-muram-data"; +- reg = <0x0 0x6000>; +- }; +- }; +- }; +- +- lpuart0: serial@2950000 { +- compatible = "fsl,ls1021a-lpuart"; +- reg = <0x0 0x2950000 0x0 0x1000>; +- interrupts = <0 48 0x4>; +- clocks = <&clockgen QORIQ_CLK_SYSCLK 0>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- lpuart1: serial@2960000 { +- compatible = "fsl,ls1021a-lpuart"; +- reg = <0x0 0x2960000 0x0 0x1000>; +- interrupts = <0 49 0x4>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- lpuart2: serial@2970000 { +- compatible = "fsl,ls1021a-lpuart"; +- reg = <0x0 0x2970000 0x0 0x1000>; +- interrupts = <0 50 0x4>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- lpuart3: serial@2980000 { +- compatible = "fsl,ls1021a-lpuart"; +- reg = <0x0 0x2980000 0x0 0x1000>; +- interrupts = <0 51 0x4>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- lpuart4: serial@2990000 { +- compatible = "fsl,ls1021a-lpuart"; +- reg = <0x0 0x2990000 0x0 0x1000>; +- interrupts = <0 52 0x4>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- lpuart5: serial@29a0000 { +- compatible = "fsl,ls1021a-lpuart"; +- reg = <0x0 0x29a0000 0x0 0x1000>; +- interrupts = <0 53 0x4>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- wdog0: watchdog@2ad0000 { +- compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; +- reg = <0x0 0x2ad0000 0x0 0x10000>; +- interrupts = <0 83 0x4>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- clock-names = "wdog"; +- big-endian; +- }; +- +- edma0: edma@2c00000 { +- #dma-cells = <2>; +- compatible = "fsl,vf610-edma"; +- reg = <0x0 0x2c00000 0x0 0x10000>, +- <0x0 0x2c10000 0x0 0x10000>, +- <0x0 0x2c20000 0x0 0x10000>; +- interrupts = <0 103 0x4>, +- <0 103 0x4>; +- interrupt-names = "edma-tx", "edma-err"; +- dma-channels = <32>; +- big-endian; +- clock-names = "dmamux0", "dmamux1"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- }; +- +- usb0: usb@2f00000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0x2f00000 0x0 0x10000>; +- interrupts = <0 60 0x4>; +- dr_mode = "host"; +- snps,quirk-frame-length-adjustment = <0x20>; +- snps,dis_rxdet_inp3_quirk; +- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; +- status = "disabled"; +- }; +- +- usb1: usb@3000000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0x3000000 0x0 0x10000>; +- interrupts = <0 61 0x4>; +- dr_mode = "host"; +- snps,quirk-frame-length-adjustment = <0x20>; +- snps,dis_rxdet_inp3_quirk; +- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; +- status = "disabled"; +- }; +- +- usb2: usb@3100000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0x3100000 0x0 0x10000>; +- interrupts = <0 63 0x4>; +- dr_mode = "host"; +- snps,quirk-frame-length-adjustment = <0x20>; +- snps,dis_rxdet_inp3_quirk; +- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; +- status = "disabled"; +- }; +- +- sata: sata@3200000 { +- compatible = "fsl,ls1043a-ahci"; +- reg = <0x0 0x3200000 0x0 0x10000>, +- <0x0 0x20140520 0x0 0x4>; +- reg-names = "ahci", "sata-ecc"; +- interrupts = <0 69 0x4>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- dma-coherent; +- }; +- +- msi1: msi-controller1@1571000 { +- compatible = "fsl,ls1043a-msi"; +- reg = <0x0 0x1571000 0x0 0x8>; +- msi-controller; +- interrupts = <0 116 0x4>; +- }; +- +- msi2: msi-controller2@1572000 { +- compatible = "fsl,ls1043a-msi"; +- reg = <0x0 0x1572000 0x0 0x8>; +- msi-controller; +- interrupts = <0 126 0x4>; +- }; +- +- msi3: msi-controller3@1573000 { +- compatible = "fsl,ls1043a-msi"; +- reg = <0x0 0x1573000 0x0 0x8>; +- msi-controller; +- interrupts = <0 160 0x4>; +- }; +- +- pcie1: pcie@3400000 { +- compatible = "fsl,ls1043a-pcie"; +- reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ +- <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "regs", "config"; +- interrupts = <0 118 0x4>, /* controller interrupt */ +- <0 117 0x4>; /* PME interrupt */ +- interrupt-names = "intr", "pme"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- num-viewport = <6>; +- bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ +- 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&msi1>, <&msi2>, <&msi3>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, +- <0000 0 0 2 &gic 0 111 0x4>, +- <0000 0 0 3 &gic 0 112 0x4>, +- <0000 0 0 4 &gic 0 113 0x4>; +- status = "disabled"; +- }; +- +- pcie2: pcie@3500000 { +- compatible = "fsl,ls1043a-pcie"; +- reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ +- <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "regs", "config"; +- interrupts = <0 128 0x4>, +- <0 127 0x4>; +- interrupt-names = "intr", "pme"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- num-viewport = <6>; +- bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ +- 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&msi1>, <&msi2>, <&msi3>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, +- <0000 0 0 2 &gic 0 121 0x4>, +- <0000 0 0 3 &gic 0 122 0x4>, +- <0000 0 0 4 &gic 0 123 0x4>; +- status = "disabled"; +- }; +- +- pcie3: pcie@3600000 { +- compatible = "fsl,ls1043a-pcie"; +- reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ +- <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "regs", "config"; +- interrupts = <0 162 0x4>, +- <0 161 0x4>; +- interrupt-names = "intr", "pme"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- num-viewport = <6>; +- bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ +- 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&msi1>, <&msi2>, <&msi3>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, +- <0000 0 0 2 &gic 0 155 0x4>, +- <0000 0 0 3 &gic 0 156 0x4>, +- <0000 0 0 4 &gic 0 157 0x4>; +- status = "disabled"; +- }; +- +- qdma: dma-controller@8380000 { +- compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma"; +- reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ +- <0x0 0x8390000 0x0 0x10000>, /* Status regs */ +- <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ +- interrupts = , +- , +- , +- , +- ; +- interrupt-names = "qdma-error", "qdma-queue0", +- "qdma-queue1", "qdma-queue2", "qdma-queue3"; +- dma-channels = <8>; +- block-number = <1>; +- block-offset = <0x10000>; +- fsl,dma-queues = <2>; +- status-sizes = <64>; +- queue-sizes = <64 64>; +- big-endian; +- }; +- +- rcpm: power-controller@1ee2140 { +- compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+"; +- reg = <0x0 0x1ee2140 0x0 0x4>; +- #fsl,rcpm-wakeup-cells = <1>; +- }; +- +- ftm_alarm0: timer@29d0000 { +- compatible = "fsl,ls1043a-ftm-alarm"; +- reg = <0x0 0x29d0000 0x0 0x10000>; +- fsl,rcpm-wakeup = <&rcpm 0x20000>; +- interrupts = ; +- big-endian; +- }; +- }; +- +- firmware { +- optee { +- compatible = "linaro,optee-tz"; +- method = "smc"; +- }; +- }; +- +-}; +- +-#include "qoriq-qman-portals.dtsi" +-#include "qoriq-bman-portals.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1046-post.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1046-post.dtsi +deleted file mode 100644 +index d6caaea57d90..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1046-post.dtsi ++++ /dev/null +@@ -1,48 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * QorIQ FMan v3 device tree nodes for ls1046 +- * +- * Copyright 2015-2016 Freescale Semiconductor Inc. +- * +- */ +- +-&soc { +- +-/* include used FMan blocks */ +-#include "qoriq-fman3-0.dtsi" +-#include "qoriq-fman3-0-1g-0.dtsi" +-#include "qoriq-fman3-0-1g-1.dtsi" +-#include "qoriq-fman3-0-1g-2.dtsi" +-#include "qoriq-fman3-0-1g-3.dtsi" +-#include "qoriq-fman3-0-1g-4.dtsi" +-#include "qoriq-fman3-0-1g-5.dtsi" +-#include "qoriq-fman3-0-10g-0.dtsi" +-#include "qoriq-fman3-0-10g-1.dtsi" +-}; +- +-&fman0 { +- /* these aliases provide the FMan ports mapping */ +- enet0: ethernet@e0000 { +- }; +- +- enet1: ethernet@e2000 { +- }; +- +- enet2: ethernet@e4000 { +- }; +- +- enet3: ethernet@e6000 { +- }; +- +- enet4: ethernet@e8000 { +- }; +- +- enet5: ethernet@ea000 { +- }; +- +- enet6: ethernet@f0000 { +- }; +- +- enet7: ethernet@f2000 { +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1046a-frwy.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1046a-frwy.dts +deleted file mode 100644 +index 6d22efbd645c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1046a-frwy.dts ++++ /dev/null +@@ -1,163 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Freescale Layerscape-1046A family SoC. +- * +- * Copyright 2019 NXP. +- * +- */ +- +-/dts-v1/; +- +-#include "fsl-ls1046a.dtsi" +- +-/ { +- model = "LS1046A FRWY Board"; +- compatible = "fsl,ls1046a-frwy", "fsl,ls1046a"; +- +- aliases { +- serial0 = &duart0; +- serial1 = &duart1; +- serial2 = &duart2; +- serial3 = &duart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- sb_3v3: regulator-sb3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "LT8642SEV-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&duart0 { +- status = "okay"; +-}; +- +-&duart1 { +- status = "okay"; +-}; +- +-&duart2 { +- status = "okay"; +-}; +- +-&duart3 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- i2c-mux@77 { +- compatible = "nxp,pca9546"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- power-monitor@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <1000>; +- }; +- +- temperature-sensor@4c { +- compatible = "nxp,sa56004"; +- reg = <0x4c>; +- vcc-supply = <&sb_3v3>; +- }; +- +- rtc@51 { +- compatible = "nxp,pcf2129"; +- reg = <0x51>; +- }; +- +- eeprom@52 { +- compatible = "onnn,cat24c04", "atmel,24c04"; +- reg = <0x52>; +- }; +- }; +- }; +-}; +- +-&ifc { +- #address-cells = <2>; +- #size-cells = <1>; +- /* NAND Flash */ +- ranges = <0x0 0x0 0x0 0x7e800000 0x00010000>; +- status = "okay"; +- +- nand@0,0 { +- compatible = "fsl,ifc-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x0 0x0 0x10000>; +- }; +- +-}; +- +-&qspi { +- status = "okay"; +- +- mt25qu512a0: flash@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <50000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <1>; +- reg = <0>; +- }; +-}; +- +-#include "fsl-ls1046-post.dtsi" +- +-&fman0 { +- ethernet@e0000 { +- phy-handle = <&qsgmii_phy4>; +- phy-connection-type = "qsgmii"; +- }; +- +- ethernet@e8000 { +- phy-handle = <&qsgmii_phy2>; +- phy-connection-type = "qsgmii"; +- }; +- +- ethernet@ea000 { +- phy-handle = <&qsgmii_phy1>; +- phy-connection-type = "qsgmii"; +- }; +- +- ethernet@f2000 { +- phy-handle = <&qsgmii_phy3>; +- phy-connection-type = "qsgmii"; +- }; +- +- mdio@fd000 { +- qsgmii_phy1: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- qsgmii_phy2: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- qsgmii_phy3: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- qsgmii_phy4: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1046a-qds.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1046a-qds.dts +deleted file mode 100644 +index eec62c63dafe..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1046a-qds.dts ++++ /dev/null +@@ -1,179 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Freescale Layerscape-1046A family SoC. +- * +- * Copyright 2016 Freescale Semiconductor, Inc. +- * Copyright 2018 NXP +- * +- * Shaohui Xie +- */ +- +-/dts-v1/; +- +-#include "fsl-ls1046a.dtsi" +- +-/ { +- model = "LS1046A QDS Board"; +- compatible = "fsl,ls1046a-qds", "fsl,ls1046a"; +- +- aliases { +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- gpio2 = &gpio2; +- gpio3 = &gpio3; +- serial0 = &duart0; +- serial1 = &duart1; +- serial2 = &duart2; +- serial3 = &duart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&dspi { +- bus-num = <0>; +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "n25q128a11", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <10000000>; +- }; +- +- flash@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "sst25wf040b", "jedec,spi-nor"; +- spi-cpol; +- spi-cpha; +- reg = <1>; +- spi-max-frequency = <10000000>; +- }; +- +- flash@2 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "en25s64", "jedec,spi-nor"; +- spi-cpol; +- spi-cpha; +- reg = <2>; +- spi-max-frequency = <10000000>; +- }; +-}; +- +-&duart0 { +- status = "okay"; +-}; +- +-&duart1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- pca9547@77 { +- compatible = "nxp,pca9547"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; +- +- ina220@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <1000>; +- }; +- +- ina220@41 { +- compatible = "ti,ina220"; +- reg = <0x41>; +- shunt-resistor = <1000>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3>; +- +- rtc@51 { +- compatible = "nxp,pcf2129"; +- reg = <0x51>; +- /* IRQ10_B */ +- interrupts = <0 150 0x4>; +- }; +- +- eeprom@56 { +- compatible = "atmel,24c512"; +- reg = <0x56>; +- }; +- +- eeprom@57 { +- compatible = "atmel,24c512"; +- reg = <0x57>; +- }; +- +- temp-sensor@4c { +- compatible = "adi,adt7461a"; +- reg = <0x4c>; +- }; +- }; +- }; +-}; +- +-&ifc { +- #address-cells = <2>; +- #size-cells = <1>; +- /* NOR, NAND Flashes and FPGA on board */ +- ranges = <0x0 0x0 0x0 0x60000000 0x08000000 +- 0x1 0x0 0x0 0x7e800000 0x00010000 +- 0x2 0x0 0x0 0x7fb00000 0x00000100>; +- status = "okay"; +- +- nor@0,0 { +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- big-endian; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@1,0 { +- compatible = "fsl,ifc-nand"; +- reg = <0x1 0x0 0x10000>; +- }; +- +- fpga: board-control@2,0 { +- compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis"; +- reg = <0x2 0x0 0x0000100>; +- }; +-}; +- +-&lpuart0 { +- status = "okay"; +-}; +- +-&qspi { +- status = "okay"; +- +- qflash0: flash@0 { +- compatible = "spansion,m25p80"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <20000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <4>; +- reg = <0>; +- }; +-}; +- +-#include "fsl-ls1046-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1046a-rdb.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1046a-rdb.dts +deleted file mode 100644 +index 7025aad8ae89..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1046a-rdb.dts ++++ /dev/null +@@ -1,185 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Freescale Layerscape-1046A family SoC. +- * +- * Copyright 2016 Freescale Semiconductor, Inc. +- * Copyright 2019-2020 NXP +- * +- * Mingkai Hu +- */ +- +-/dts-v1/; +- +-#include "fsl-ls1046a.dtsi" +- +-/ { +- model = "LS1046A RDB Board"; +- compatible = "fsl,ls1046a-rdb", "fsl,ls1046a"; +- +- aliases { +- serial0 = &duart0; +- serial1 = &duart1; +- serial2 = &duart2; +- serial3 = &duart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&duart0 { +- status = "okay"; +-}; +- +-&duart1 { +- status = "okay"; +-}; +- +-&esdhc { +- mmc-hs200-1_8v; +- sd-uhs-sdr104; +- sd-uhs-sdr50; +- sd-uhs-sdr25; +- sd-uhs-sdr12; +-}; +- +-&i2c0 { +- status = "okay"; +- +- ina220@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <1000>; +- }; +- +- temp-sensor@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- +- eeprom@52 { +- compatible = "onnn,cat24c05", "atmel,24c04"; +- reg = <0x52>; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +- +- rtc@51 { +- compatible = "nxp,pcf2129"; +- reg = <0x51>; +- /* IRQ_RTC_B -> IRQ05, active low */ +- interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&ifc { +- #address-cells = <2>; +- #size-cells = <1>; +- /* NAND Flashe and CPLD on board */ +- ranges = <0x0 0x0 0x0 0x7e800000 0x00010000 +- 0x2 0x0 0x0 0x7fb00000 0x00000100>; +- status = "okay"; +- +- nand@0,0 { +- compatible = "fsl,ifc-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x0 0x0 0x10000>; +- }; +- +- cpld: board-control@2,0 { +- compatible = "fsl,ls1046ardb-cpld"; +- reg = <0x2 0x0 0x0000100>; +- }; +-}; +- +-&qspi { +- status = "okay"; +- +- s25fs512s0: flash@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <50000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <1>; +- reg = <0>; +- }; +- +- s25fs512s1: flash@1 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <50000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <1>; +- reg = <1>; +- }; +-}; +- +-&usb1 { +- dr_mode = "otg"; +-}; +- +-#include "fsl-ls1046-post.dtsi" +- +-&fman0 { +- ethernet@e4000 { +- phy-handle = <&rgmii_phy1>; +- phy-connection-type = "rgmii-id"; +- }; +- +- ethernet@e6000 { +- phy-handle = <&rgmii_phy2>; +- phy-connection-type = "rgmii-id"; +- }; +- +- ethernet@e8000 { +- phy-handle = <&sgmii_phy1>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@ea000 { +- phy-handle = <&sgmii_phy2>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@f0000 { /* 10GEC1 */ +- phy-handle = <&aqr106_phy>; +- phy-connection-type = "xgmii"; +- }; +- +- ethernet@f2000 { /* 10GEC2 */ +- fixed-link = <0 1 1000 0 0>; +- phy-connection-type = "xgmii"; +- }; +- +- mdio@fc000 { +- rgmii_phy1: ethernet-phy@1 { +- reg = <0x1>; +- }; +- +- rgmii_phy2: ethernet-phy@2 { +- reg = <0x2>; +- }; +- +- sgmii_phy1: ethernet-phy@3 { +- reg = <0x3>; +- }; +- +- sgmii_phy2: ethernet-phy@4 { +- reg = <0x4>; +- }; +- }; +- +- mdio@fd000 { +- aqr106_phy: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- interrupts = <0 131 4>; +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1046a.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1046a.dtsi +deleted file mode 100644 +index 687fea6d8afa..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1046a.dtsi ++++ /dev/null +@@ -1,954 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for NXP Layerscape-1046A family SoC. +- * +- * Copyright 2016 Freescale Semiconductor, Inc. +- * Copyright 2018, 2020 NXP +- * +- * Mingkai Hu +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "fsl,ls1046a"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- crypto = &crypto; +- fman0 = &fman0; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- ethernet4 = &enet4; +- ethernet5 = &enet5; +- ethernet6 = &enet6; +- ethernet7 = &enet7; +- rtc1 = &ftm_alarm0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x0>; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- next-level-cache = <&l2>; +- cpu-idle-states = <&CPU_PH20>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x1>; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- next-level-cache = <&l2>; +- cpu-idle-states = <&CPU_PH20>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x2>; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- next-level-cache = <&l2>; +- cpu-idle-states = <&CPU_PH20>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x3>; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- next-level-cache = <&l2>; +- cpu-idle-states = <&CPU_PH20>; +- #cooling-cells = <2>; +- }; +- +- l2: l2-cache { +- compatible = "cache"; +- }; +- }; +- +- idle-states { +- /* +- * PSCI node is not added default, U-boot will add missing +- * parts if it determines to use PSCI. +- */ +- entry-method = "psci"; +- +- CPU_PH20: cpu-ph20 { +- compatible = "arm,idle-state"; +- idle-state-name = "PH20"; +- arm,psci-suspend-param = <0x0>; +- entry-latency-us = <1000>; +- exit-latency-us = <1000>; +- min-residency-us = <3000>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- /* Real size will be filled by bootloader */ +- reg = <0x0 0x80000000 0x0 0x0>; +- }; +- +- sysclk: sysclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- clock-output-names = "sysclk"; +- }; +- +- reboot { +- compatible ="syscon-reboot"; +- regmap = <&dcfg>; +- offset = <0xb0>; +- mask = <0x02>; +- }; +- +- thermal-zones { +- ddr-controller { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 0>; +- +- trips { +- ddr-ctrler-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- ddr-ctrler-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- serdes { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 1>; +- +- trips { +- serdes-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- serdes-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- fman { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 2>; +- +- trips { +- fman-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- fman-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- core-cluster { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 3>; +- +- trips { +- core_cluster_alert: core-cluster-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- core_cluster_crit: core-cluster-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&core_cluster_alert>; +- cooling-device = +- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- sec { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 4>; +- +- trips { +- sec-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- sec-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,cortex-a72-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, +- <&cpu1>, +- <&cpu2>, +- <&cpu3>; +- }; +- +- gic: interrupt-controller@1400000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x0 0x1410000 0 0x10000>, /* GICD */ +- <0x0 0x1420000 0 0x20000>, /* GICC */ +- <0x0 0x1440000 0 0x20000>, /* GICH */ +- <0x0 0x1460000 0 0x20000>; /* GICV */ +- interrupts = ; +- }; +- +- soc: soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ddr: memory-controller@1080000 { +- compatible = "fsl,qoriq-memory-controller"; +- reg = <0x0 0x1080000 0x0 0x1000>; +- interrupts = ; +- big-endian; +- }; +- +- ifc: ifc@1530000 { +- compatible = "fsl,ifc", "simple-bus"; +- reg = <0x0 0x1530000 0x0 0x10000>; +- interrupts = ; +- status = "disabled"; +- }; +- +- qspi: spi@1550000 { +- compatible = "fsl,ls1021a-qspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x1550000 0x0 0x10000>, +- <0x0 0x40000000 0x0 0x10000000>; +- reg-names = "QuadSPI", "QuadSPI-memory"; +- interrupts = ; +- clock-names = "qspi_en", "qspi"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- status = "disabled"; +- }; +- +- esdhc: esdhc@1560000 { +- compatible = "fsl,ls1046a-esdhc", "fsl,esdhc"; +- reg = <0x0 0x1560000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; +- voltage-ranges = <1800 1800 3300 3300>; +- sdhci,auto-cmd12; +- big-endian; +- bus-width = <4>; +- }; +- +- scfg: scfg@1570000 { +- compatible = "fsl,ls1046a-scfg", "syscon"; +- reg = <0x0 0x1570000 0x0 0x10000>; +- big-endian; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1570000 0x10000>; +- +- extirq: interrupt-controller@1ac { +- compatible = "fsl,ls1046a-extirq", "fsl,ls1043a-extirq"; +- #interrupt-cells = <2>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x1ac 4>; +- interrupt-map = +- <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, +- <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, +- <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, +- <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, +- <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, +- <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, +- <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, +- <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, +- <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, +- <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, +- <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, +- <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-map-mask = <0xffffffff 0x0>; +- }; +- }; +- +- crypto: crypto@1700000 { +- compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", +- "fsl,sec-v4.0"; +- fsl,sec-era = <8>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x00 0x1700000 0x100000>; +- reg = <0x00 0x1700000 0x0 0x100000>; +- interrupts = ; +- dma-coherent; +- +- sec_jr0: jr@10000 { +- compatible = "fsl,sec-v5.4-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x10000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr1: jr@20000 { +- compatible = "fsl,sec-v5.4-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x20000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr2: jr@30000 { +- compatible = "fsl,sec-v5.4-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x30000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr3: jr@40000 { +- compatible = "fsl,sec-v5.4-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x40000 0x10000>; +- interrupts = ; +- }; +- }; +- +- qman: qman@1880000 { +- compatible = "fsl,qman"; +- reg = <0x0 0x1880000 0x0 0x10000>; +- interrupts = ; +- memory-region = <&qman_fqd &qman_pfdr>; +- +- }; +- +- bman: bman@1890000 { +- compatible = "fsl,bman"; +- reg = <0x0 0x1890000 0x0 0x10000>; +- interrupts = ; +- memory-region = <&bman_fbpr>; +- +- }; +- +- qportals: qman-portals@500000000 { +- ranges = <0x0 0x5 0x00000000 0x8000000>; +- }; +- +- bportals: bman-portals@508000000 { +- ranges = <0x0 0x5 0x08000000 0x8000000>; +- }; +- +- dcfg: dcfg@1ee0000 { +- compatible = "fsl,ls1046a-dcfg", "syscon"; +- reg = <0x0 0x1ee0000 0x0 0x1000>; +- big-endian; +- }; +- +- clockgen: clocking@1ee1000 { +- compatible = "fsl,ls1046a-clockgen"; +- reg = <0x0 0x1ee1000 0x0 0x1000>; +- #clock-cells = <2>; +- clocks = <&sysclk>; +- }; +- +- tmu: tmu@1f00000 { +- compatible = "fsl,qoriq-tmu"; +- reg = <0x0 0x1f00000 0x0 0x10000>; +- interrupts = <0 33 0x4>; +- fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; +- fsl,tmu-calibration = +- /* Calibration data group 1 */ +- <0x00000000 0x00000023 +- 0x00000001 0x00000029 +- 0x00000002 0x0000002f +- 0x00000003 0x00000036 +- 0x00000004 0x0000003c +- 0x00000005 0x00000042 +- 0x00000006 0x00000049 +- 0x00000007 0x0000004f +- 0x00000008 0x00000055 +- 0x00000009 0x0000005c +- 0x0000000a 0x00000062 +- 0x0000000b 0x00000068 +- /* Calibration data group 2 */ +- 0x00010000 0x00000022 +- 0x00010001 0x0000002a +- 0x00010002 0x00000032 +- 0x00010003 0x0000003a +- 0x00010004 0x00000042 +- 0x00010005 0x0000004a +- 0x00010006 0x00000052 +- 0x00010007 0x0000005a +- 0x00010008 0x00000062 +- 0x00010009 0x0000006a +- /* Calibration data group 3 */ +- 0x00020000 0x00000021 +- 0x00020001 0x0000002b +- 0x00020002 0x00000035 +- 0x00020003 0x0000003e +- 0x00020004 0x00000048 +- 0x00020005 0x00000052 +- 0x00020006 0x0000005c +- /* Calibration data group 4 */ +- 0x00030000 0x00000011 +- 0x00030001 0x0000001a +- 0x00030002 0x00000024 +- 0x00030003 0x0000002e +- 0x00030004 0x00000038 +- 0x00030005 0x00000042 +- 0x00030006 0x0000004c +- 0x00030007 0x00000056>; +- big-endian; +- #thermal-sensor-cells = <1>; +- }; +- +- dspi: spi@2100000 { +- compatible = "fsl,ls1021a-v1.0-dspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2100000 0x0 0x10000>; +- interrupts = ; +- clock-names = "dspi"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- spi-num-chipselects = <5>; +- big-endian; +- status = "disabled"; +- }; +- +- i2c0: i2c@2180000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2180000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- dmas = <&edma0 1 39>, +- <&edma0 1 38>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- i2c1: i2c@2190000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2190000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- status = "disabled"; +- }; +- +- i2c2: i2c@21a0000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x21a0000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- status = "disabled"; +- }; +- +- i2c3: i2c@21b0000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x21b0000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- status = "disabled"; +- }; +- +- duart0: serial@21c0500 { +- compatible = "fsl,ns16550", "ns16550a"; +- reg = <0x00 0x21c0500 0x0 0x100>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- status = "disabled"; +- }; +- +- duart1: serial@21c0600 { +- compatible = "fsl,ns16550", "ns16550a"; +- reg = <0x00 0x21c0600 0x0 0x100>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- status = "disabled"; +- }; +- +- duart2: serial@21d0500 { +- compatible = "fsl,ns16550", "ns16550a"; +- reg = <0x0 0x21d0500 0x0 0x100>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- status = "disabled"; +- }; +- +- duart3: serial@21d0600 { +- compatible = "fsl,ns16550", "ns16550a"; +- reg = <0x0 0x21d0600 0x0 0x100>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- status = "disabled"; +- }; +- +- gpio0: gpio@2300000 { +- compatible = "fsl,qoriq-gpio"; +- reg = <0x0 0x2300000 0x0 0x10000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio@2310000 { +- compatible = "fsl,qoriq-gpio"; +- reg = <0x0 0x2310000 0x0 0x10000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@2320000 { +- compatible = "fsl,qoriq-gpio"; +- reg = <0x0 0x2320000 0x0 0x10000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio@2330000 { +- compatible = "fsl,qoriq-gpio"; +- reg = <0x0 0x2330000 0x0 0x10000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- lpuart0: serial@2950000 { +- compatible = "fsl,ls1021a-lpuart"; +- reg = <0x0 0x2950000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- lpuart1: serial@2960000 { +- compatible = "fsl,ls1021a-lpuart"; +- reg = <0x0 0x2960000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- lpuart2: serial@2970000 { +- compatible = "fsl,ls1021a-lpuart"; +- reg = <0x0 0x2970000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- lpuart3: serial@2980000 { +- compatible = "fsl,ls1021a-lpuart"; +- reg = <0x0 0x2980000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- lpuart4: serial@2990000 { +- compatible = "fsl,ls1021a-lpuart"; +- reg = <0x0 0x2990000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- lpuart5: serial@29a0000 { +- compatible = "fsl,ls1021a-lpuart"; +- reg = <0x0 0x29a0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- wdog0: watchdog@2ad0000 { +- compatible = "fsl,imx21-wdt"; +- reg = <0x0 0x2ad0000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- big-endian; +- }; +- +- edma0: edma@2c00000 { +- #dma-cells = <2>; +- compatible = "fsl,vf610-edma"; +- reg = <0x0 0x2c00000 0x0 0x10000>, +- <0x0 0x2c10000 0x0 0x10000>, +- <0x0 0x2c20000 0x0 0x10000>; +- interrupts = , +- ; +- interrupt-names = "edma-tx", "edma-err"; +- dma-channels = <32>; +- big-endian; +- clock-names = "dmamux0", "dmamux1"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- }; +- +- usb0: usb@2f00000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0x2f00000 0x0 0x10000>; +- interrupts = ; +- dr_mode = "host"; +- snps,quirk-frame-length-adjustment = <0x20>; +- snps,dis_rxdet_inp3_quirk; +- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; +- }; +- +- usb1: usb@3000000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0x3000000 0x0 0x10000>; +- interrupts = ; +- dr_mode = "host"; +- snps,quirk-frame-length-adjustment = <0x20>; +- snps,dis_rxdet_inp3_quirk; +- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; +- }; +- +- usb2: usb@3100000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0x3100000 0x0 0x10000>; +- interrupts = ; +- dr_mode = "host"; +- snps,quirk-frame-length-adjustment = <0x20>; +- snps,dis_rxdet_inp3_quirk; +- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; +- }; +- +- sata: sata@3200000 { +- compatible = "fsl,ls1046a-ahci"; +- reg = <0x0 0x3200000 0x0 0x10000>, +- <0x0 0x20140520 0x0 0x4>; +- reg-names = "ahci", "sata-ecc"; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- }; +- +- msi1: msi-controller@1580000 { +- compatible = "fsl,ls1046a-msi"; +- msi-controller; +- reg = <0x0 0x1580000 0x0 0x10000>; +- interrupts = , +- , +- , +- ; +- }; +- +- msi2: msi-controller@1590000 { +- compatible = "fsl,ls1046a-msi"; +- msi-controller; +- reg = <0x0 0x1590000 0x0 0x10000>; +- interrupts = , +- , +- , +- ; +- }; +- +- msi3: msi-controller@15a0000 { +- compatible = "fsl,ls1046a-msi"; +- msi-controller; +- reg = <0x0 0x15a0000 0x0 0x10000>; +- interrupts = , +- , +- , +- ; +- }; +- +- pcie1: pcie@3400000 { +- compatible = "fsl,ls1046a-pcie"; +- reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ +- <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "regs", "config"; +- interrupts = , /* controller interrupt */ +- ; /* PME interrupt */ +- interrupt-names = "aer", "pme"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- num-viewport = <8>; +- bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ +- 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&msi1>, <&msi2>, <&msi3>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +- +- pcie_ep1: pcie_ep@3400000 { +- compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; +- reg = <0x00 0x03400000 0x0 0x00100000>, +- <0x40 0x00000000 0x8 0x00000000>; +- reg-names = "regs", "addr_space"; +- num-ib-windows = <6>; +- num-ob-windows = <8>; +- status = "disabled"; +- }; +- +- pcie2: pcie@3500000 { +- compatible = "fsl,ls1046a-pcie"; +- reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ +- <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "regs", "config"; +- interrupts = , /* controller interrupt */ +- ; /* PME interrupt */ +- interrupt-names = "aer", "pme"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- num-viewport = <8>; +- bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ +- 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&msi2>, <&msi3>, <&msi1>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +- +- pcie_ep2: pcie_ep@3500000 { +- compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; +- reg = <0x00 0x03500000 0x0 0x00100000>, +- <0x48 0x00000000 0x8 0x00000000>; +- reg-names = "regs", "addr_space"; +- num-ib-windows = <6>; +- num-ob-windows = <8>; +- status = "disabled"; +- }; +- +- pcie3: pcie@3600000 { +- compatible = "fsl,ls1046a-pcie"; +- reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ +- <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "regs", "config"; +- interrupts = , /* controller interrupt */ +- ; /* PME interrupt */ +- interrupt-names = "aer", "pme"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- num-viewport = <8>; +- bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ +- 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&msi3>, <&msi1>, <&msi2>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +- +- pcie_ep3: pcie_ep@3600000 { +- compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"; +- reg = <0x00 0x03600000 0x0 0x00100000>, +- <0x50 0x00000000 0x8 0x00000000>; +- reg-names = "regs", "addr_space"; +- num-ib-windows = <6>; +- num-ob-windows = <8>; +- status = "disabled"; +- }; +- +- qdma: dma-controller@8380000 { +- compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma"; +- reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ +- <0x0 0x8390000 0x0 0x10000>, /* Status regs */ +- <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ +- interrupts = , +- , +- , +- , +- ; +- interrupt-names = "qdma-error", "qdma-queue0", +- "qdma-queue1", "qdma-queue2", "qdma-queue3"; +- dma-channels = <8>; +- block-number = <1>; +- block-offset = <0x10000>; +- fsl,dma-queues = <2>; +- status-sizes = <64>; +- queue-sizes = <64 64>; +- big-endian; +- }; +- +- rcpm: power-controller@1ee2140 { +- compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+"; +- reg = <0x0 0x1ee2140 0x0 0x4>; +- #fsl,rcpm-wakeup-cells = <1>; +- }; +- +- ftm_alarm0: timer@29d0000 { +- compatible = "fsl,ls1046a-ftm-alarm"; +- reg = <0x0 0x29d0000 0x0 0x10000>; +- fsl,rcpm-wakeup = <&rcpm 0x20000>; +- interrupts = ; +- big-endian; +- }; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- compatible = "shared-dma-pool"; +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- no-map; +- }; +- +- qman_fqd: qman-fqd { +- compatible = "shared-dma-pool"; +- size = <0 0x800000>; +- alignment = <0 0x800000>; +- no-map; +- }; +- +- qman_pfdr: qman-pfdr { +- compatible = "shared-dma-pool"; +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- no-map; +- }; +- }; +- +- firmware { +- optee { +- compatible = "linaro,optee-tz"; +- method = "smc"; +- }; +- }; +-}; +- +-#include "qoriq-qman-portals.dtsi" +-#include "qoriq-bman-portals.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1088a-qds.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1088a-qds.dts +deleted file mode 100644 +index 41d8b15f25a5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1088a-qds.dts ++++ /dev/null +@@ -1,172 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for NXP LS1088A QDS Board. +- * +- * Copyright 2017 NXP +- * +- * Harninder Rai +- * +- */ +- +-/dts-v1/; +- +-#include "fsl-ls1088a.dtsi" +- +-/ { +- model = "LS1088A QDS Board"; +- compatible = "fsl,ls1088a-qds", "fsl,ls1088a"; +-}; +- +-&dspi { +- bus-num = <0>; +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- +- flash@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- spi-cpol; +- spi-cpha; +- spi-max-frequency = <3500000>; +- reg = <1>; +- }; +- +- flash@2 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- spi-cpol; +- spi-cpha; +- spi-max-frequency = <3500000>; +- reg = <2>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- i2c-switch@77 { +- compatible = "nxp,pca9547"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; +- +- ina220@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <1000>; +- }; +- +- ina220@41 { +- compatible = "ti,ina220"; +- reg = <0x41>; +- shunt-resistor = <1000>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3>; +- +- temp-sensor@4c { +- compatible = "adi,adt7461a"; +- reg = <0x4c>; +- }; +- +- rtc@51 { +- compatible = "nxp,pcf2129"; +- reg = <0x51>; +- /* IRQ10_B */ +- interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- eeprom@56 { +- compatible = "atmel,24c512"; +- reg = <0x56>; +- }; +- +- eeprom@57 { +- compatible = "atmel,24c512"; +- reg = <0x57>; +- }; +- }; +- }; +-}; +- +-&ifc { +- ranges = <0 0 0x5 0x80000000 0x08000000 +- 2 0 0x5 0x30000000 0x00010000 +- 3 0 0x5 0x20000000 0x00010000>; +- status = "okay"; +- +- nor@0,0 { +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@2,0 { +- compatible = "fsl,ifc-nand"; +- reg = <0x2 0x0 0x10000>; +- }; +- +- fpga: board-control@3,0 { +- compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis"; +- reg = <0x3 0x0 0x0000100>; +- }; +-}; +- +-&duart0 { +- status = "okay"; +-}; +- +-&duart1 { +- status = "okay"; +-}; +- +-&esdhc { +- status = "okay"; +-}; +- +-&qspi { +- status = "okay"; +- +- s25fs512s0: flash@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <50000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <1>; +- reg = <0>; +- }; +- +- s25fs512s1: flash@1 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <50000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <1>; +- reg = <1>; +- }; +-}; +- +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1088a-rdb.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1088a-rdb.dts +deleted file mode 100644 +index 1bfbce69cc8b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1088a-rdb.dts ++++ /dev/null +@@ -1,253 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for NXP LS1088A RDB Board. +- * +- * Copyright 2017-2020 NXP +- * +- * Harninder Rai +- * +- */ +- +-/dts-v1/; +- +-#include "fsl-ls1088a.dtsi" +- +-/ { +- model = "LS1088A RDB Board"; +- compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; +-}; +- +-&dpmac2 { +- phy-handle = <&mdio2_aquantia_phy>; +- phy-connection-type = "10gbase-r"; +- pcs-handle = <&pcs2>; +-}; +- +-&dpmac3 { +- phy-handle = <&mdio1_phy5>; +- phy-connection-type = "qsgmii"; +- managed = "in-band-status"; +- pcs-handle = <&pcs3_0>; +-}; +- +-&dpmac4 { +- phy-handle = <&mdio1_phy6>; +- phy-connection-type = "qsgmii"; +- managed = "in-band-status"; +- pcs-handle = <&pcs3_1>; +-}; +- +-&dpmac5 { +- phy-handle = <&mdio1_phy7>; +- phy-connection-type = "qsgmii"; +- managed = "in-band-status"; +- pcs-handle = <&pcs3_2>; +-}; +- +-&dpmac6 { +- phy-handle = <&mdio1_phy8>; +- phy-connection-type = "qsgmii"; +- managed = "in-band-status"; +- pcs-handle = <&pcs3_3>; +-}; +- +-&dpmac7 { +- phy-handle = <&mdio1_phy1>; +- phy-connection-type = "qsgmii"; +- managed = "in-band-status"; +- pcs-handle = <&pcs7_0>; +-}; +- +-&dpmac8 { +- phy-handle = <&mdio1_phy2>; +- phy-connection-type = "qsgmii"; +- managed = "in-band-status"; +- pcs-handle = <&pcs7_1>; +-}; +- +-&dpmac9 { +- phy-handle = <&mdio1_phy3>; +- phy-connection-type = "qsgmii"; +- managed = "in-band-status"; +- pcs-handle = <&pcs7_2>; +-}; +- +-&dpmac10 { +- phy-handle = <&mdio1_phy4>; +- phy-connection-type = "qsgmii"; +- managed = "in-band-status"; +- pcs-handle = <&pcs7_3>; +-}; +- +-&emdio1 { +- status = "okay"; +- +- mdio1_phy5: ethernet-phy@c { +- interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>; +- reg = <0xc>; +- }; +- +- mdio1_phy6: ethernet-phy@d { +- interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>; +- reg = <0xd>; +- }; +- +- mdio1_phy7: ethernet-phy@e { +- interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>; +- reg = <0xe>; +- }; +- +- mdio1_phy8: ethernet-phy@f { +- interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>; +- reg = <0xf>; +- }; +- +- mdio1_phy1: ethernet-phy@1c { +- interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x1c>; +- }; +- +- mdio1_phy2: ethernet-phy@1d { +- interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x1d>; +- }; +- +- mdio1_phy3: ethernet-phy@1e { +- interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x1e>; +- }; +- +- mdio1_phy4: ethernet-phy@1f { +- interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x1f>; +- }; +-}; +- +-&emdio2 { +- status = "okay"; +- +- mdio2_aquantia_phy: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x0>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- i2c-switch@77 { +- compatible = "nxp,pca9547"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; +- +- ina220@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <1000>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3>; +- +- temp-sensor@4c { +- compatible = "adi,adt7461a"; +- reg = <0x4c>; +- }; +- +- rtc@51 { +- compatible = "nxp,pcf2129"; +- reg = <0x51>; +- /* IRQ_RTC_B -> IRQ0_B(CPLD) -> IRQ00(CPU), active low */ +- interrupts-extended = <&extirq 0 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +- }; +-}; +- +-&ifc { +- ranges = <0 0 0x5 0x30000000 0x00010000 +- 2 0 0x5 0x20000000 0x00010000>; +- status = "okay"; +- +- nand@0,0 { +- compatible = "fsl,ifc-nand"; +- reg = <0x0 0x0 0x10000>; +- }; +- +- fpga: board-control@2,0 { +- compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis"; +- reg = <0x2 0x0 0x0000100>; +- }; +-}; +- +-&duart0 { +- status = "okay"; +-}; +- +-&duart1 { +- status = "okay"; +-}; +- +-&esdhc { +- mmc-hs200-1_8v; +- status = "okay"; +-}; +- +-&pcs_mdio2 { +- status = "okay"; +-}; +- +-&pcs_mdio3 { +- status = "okay"; +-}; +- +-&pcs_mdio7 { +- status = "okay"; +-}; +- +-&qspi { +- status = "okay"; +- +- s25fs512s0: flash@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <50000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <1>; +- reg = <0>; +- }; +- +- s25fs512s1: flash@1 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <50000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <1>; +- reg = <1>; +- }; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- dr_mode = "otg"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1088a-ten64.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1088a-ten64.dts +deleted file mode 100644 +index d3f03dcbb8c3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1088a-ten64.dts ++++ /dev/null +@@ -1,387 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Travese Ten64 (LS1088) board +- * Based on fsl-ls1088a-rdb.dts +- * Copyright 2017-2020 NXP +- * Copyright 2019-2021 Traverse Technologies +- * +- * Author: Mathew McBride +- */ +- +-/dts-v1/; +- +-#include "fsl-ls1088a.dtsi" +- +-#include +-#include +- +-/ { +- model = "Traverse Ten64"; +- compatible = "traverse,ten64", "fsl,ls1088a"; +- +- aliases { +- serial0 = &duart0; +- serial1 = &duart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- buttons { +- compatible = "gpio-keys"; +- +- /* Fired by system controller when +- * external power off (e.g ATX Power Button) +- * asserted +- */ +- powerdn { +- label = "External Power Down"; +- gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- /* Rear Panel 'ADMIN' button (GPIO_H) */ +- admin { +- label = "ADMIN button"; +- gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- sfp1down { +- label = "ten64:green:sfp1:down"; +- gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; +- }; +- +- sfp2up { +- label = "ten64:green:sfp2:up"; +- gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; +- }; +- +- admin { +- label = "ten64:admin"; +- gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- sfp_xg0: dpmac2-sfp { +- compatible = "sff,sfp"; +- i2c-bus = <&sfplower_i2c>; +- tx-fault-gpios = <&sfpgpio 0 GPIO_ACTIVE_HIGH>; +- tx-disable-gpios = <&sfpgpio 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sfpgpio 2 GPIO_ACTIVE_LOW>; +- los-gpios = <&sfpgpio 3 GPIO_ACTIVE_HIGH>; +- maximum-power-milliwatt = <2000>; +- }; +- +- sfp_xg1: dpmac1-sfp { +- compatible = "sff,sfp"; +- i2c-bus = <&sfpupper_i2c>; +- tx-fault-gpios = <&sfpgpio 4 GPIO_ACTIVE_HIGH>; +- tx-disable-gpios = <&sfpgpio 5 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sfpgpio 6 GPIO_ACTIVE_LOW>; +- los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>; +- maximum-power-milliwatt = <2000>; +- }; +-}; +- +-/* XG1 - Upper SFP */ +-&dpmac1 { +- sfp = <&sfp_xg1>; +- pcs-handle = <&pcs1>; +- phy-connection-type = "10gbase-r"; +- managed = "in-band-status"; +-}; +- +-/* XG0 - Lower SFP */ +-&dpmac2 { +- sfp = <&sfp_xg0>; +- pcs-handle = <&pcs2>; +- phy-connection-type = "10gbase-r"; +- managed = "in-band-status"; +-}; +- +-/* DPMAC3..6 is GE4 to GE8 */ +-&dpmac3 { +- phy-handle = <&mdio1_phy5>; +- phy-connection-type = "qsgmii"; +- managed = "in-band-status"; +- pcs-handle = <&pcs3_0>; +-}; +- +-&dpmac4 { +- phy-handle = <&mdio1_phy6>; +- phy-connection-type = "qsgmii"; +- managed = "in-band-status"; +- pcs-handle = <&pcs3_1>; +-}; +- +-&dpmac5 { +- phy-handle = <&mdio1_phy7>; +- phy-connection-type = "qsgmii"; +- managed = "in-band-status"; +- pcs-handle = <&pcs3_2>; +-}; +- +-&dpmac6 { +- phy-handle = <&mdio1_phy8>; +- phy-connection-type = "qsgmii"; +- managed = "in-band-status"; +- pcs-handle = <&pcs3_3>; +-}; +- +-/* DPMAC7..10 is GE0 to GE3 */ +-&dpmac7 { +- phy-handle = <&mdio1_phy1>; +- phy-connection-type = "qsgmii"; +- managed = "in-band-status"; +- pcs-handle = <&pcs7_0>; +-}; +- +-&dpmac8 { +- phy-handle = <&mdio1_phy2>; +- phy-connection-type = "qsgmii"; +- managed = "in-band-status"; +- pcs-handle = <&pcs7_1>; +-}; +- +-&dpmac9 { +- phy-handle = <&mdio1_phy3>; +- phy-connection-type = "qsgmii"; +- managed = "in-band-status"; +- pcs-handle = <&pcs7_2>; +-}; +- +-&dpmac10 { +- phy-handle = <&mdio1_phy4>; +- phy-connection-type = "qsgmii"; +- managed = "in-band-status"; +- pcs-handle = <&pcs7_3>; +-}; +- +-&duart0 { +- status = "okay"; +-}; +- +-&duart1 { +- status = "okay"; +-}; +- +-&emdio1 { +- status = "okay"; +- +- mdio1_phy5: ethernet-phy@c { +- reg = <0xc>; +- }; +- +- mdio1_phy6: ethernet-phy@d { +- reg = <0xd>; +- }; +- +- mdio1_phy7: ethernet-phy@e { +- reg = <0xe>; +- }; +- +- mdio1_phy8: ethernet-phy@f { +- reg = <0xf>; +- }; +- +- mdio1_phy1: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- mdio1_phy2: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- mdio1_phy3: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- mdio1_phy4: ethernet-phy@1f { +- reg = <0x1f>; +- }; +-}; +- +-&esdhc { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- sfpgpio: gpio@76 { +- compatible = "ti,tca9539"; +- reg = <0x76>; +- #gpio-cells = <2>; +- gpio-controller; +- +- admin_led_lower { +- gpio-hog; +- gpios = <13 GPIO_ACTIVE_HIGH>; +- output-low; +- }; +- }; +- +- at97sc: tpm@29 { +- compatible = "atmel,at97sc3204t"; +- reg = <0x29>; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- +- rx8035: rtc@32 { +- compatible = "epson,rx8035"; +- reg = <0x32>; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +- +- i2c-switch@70 { +- compatible = "nxp,pca9540"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- +- sfpupper_i2c: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- sfplower_i2c: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- }; +-}; +- +-&pcs_mdio1 { +- status = "okay"; +-}; +- +-&pcs_mdio2 { +- status = "okay"; +-}; +- +-&pcs_mdio3 { +- status = "okay"; +-}; +- +-&pcs_mdio7 { +- status = "okay"; +-}; +- +-&qspi { +- status = "okay"; +- +- en25s64: flash@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- spi-max-frequency = <20000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <4>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "bl2"; +- reg = <0 0x100000>; +- }; +- +- partition@100000 { +- label = "bl3"; +- reg = <0x100000 0x200000>; +- }; +- +- partition@300000 { +- label = "mcfirmware"; +- reg = <0x300000 0x200000>; +- }; +- +- partition@500000 { +- label = "ubootenv"; +- reg = <0x500000 0x80000>; +- }; +- +- partition@580000 { +- label = "dpl"; +- reg = <0x580000 0x40000>; +- }; +- +- partition@5C0000 { +- label = "dpc"; +- reg = <0x5C0000 0x40000>; +- }; +- +- partition@600000 { +- label = "devicetree"; +- reg = <0x600000 0x40000>; +- }; +- }; +- }; +- +- nand: flash@1 { +- compatible = "spi-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <1>; +- spi-max-frequency = <20000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <4>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* reserved for future boot direct from NAND flash +- * (this would use the same layout as the 8MiB NOR flash) +- */ +- partition@0 { +- label = "nand-boot-reserved"; +- reg = <0 0x800000>; +- }; +- +- /* recovery / install environment */ +- partition@800000 { +- label = "recovery"; +- reg = <0x800000 0x2000000>; +- }; +- +- /* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */ +- partition@2800000 { +- label = "ubia"; +- reg = <0x2800000 0x6C00000>; +- }; +- +- /* ubib (second OpenWrt) */ +- partition@9400000 { +- label = "ubib"; +- reg = <0x9400000 0x6C00000>; +- }; +- }; +- }; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1088a.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1088a.dtsi +deleted file mode 100644 +index 605072317243..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1088a.dtsi ++++ /dev/null +@@ -1,1023 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for NXP Layerscape-1088A family SoC. +- * +- * Copyright 2017-2020 NXP +- * +- * Harninder Rai +- * +- */ +-#include +-#include +-#include +- +-/ { +- compatible = "fsl,ls1088a"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- crypto = &crypto; +- rtc1 = &ftm_alarm0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* We have 2 clusters having 4 Cortex-A53 cores each */ +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0>; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- cpu-idle-states = <&CPU_PH20>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x1>; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- cpu-idle-states = <&CPU_PH20>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x2>; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- cpu-idle-states = <&CPU_PH20>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x3>; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- cpu-idle-states = <&CPU_PH20>; +- #cooling-cells = <2>; +- }; +- +- cpu4: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x100>; +- clocks = <&clockgen QORIQ_CLK_CMUX 1>; +- cpu-idle-states = <&CPU_PH20>; +- #cooling-cells = <2>; +- }; +- +- cpu5: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x101>; +- clocks = <&clockgen QORIQ_CLK_CMUX 1>; +- cpu-idle-states = <&CPU_PH20>; +- #cooling-cells = <2>; +- }; +- +- cpu6: cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x102>; +- clocks = <&clockgen QORIQ_CLK_CMUX 1>; +- cpu-idle-states = <&CPU_PH20>; +- #cooling-cells = <2>; +- }; +- +- cpu7: cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x103>; +- clocks = <&clockgen QORIQ_CLK_CMUX 1>; +- cpu-idle-states = <&CPU_PH20>; +- #cooling-cells = <2>; +- }; +- +- CPU_PH20: cpu-ph20 { +- compatible = "arm,idle-state"; +- idle-state-name = "PH20"; +- arm,psci-suspend-param = <0x0>; +- entry-latency-us = <1000>; +- exit-latency-us = <1000>; +- min-residency-us = <3000>; +- }; +- }; +- +- gic: interrupt-controller@6000000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ +- <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ +- <0x0 0x0c0c0000 0 0x2000>, /* GICC */ +- <0x0 0x0c0d0000 0 0x1000>, /* GICH */ +- <0x0 0x0c0e0000 0 0x20000>; /* GICV */ +- interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- its: gic-its@6020000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- reg = <0x0 0x6020000 0 0x20000>; +- }; +- }; +- +- thermal-zones { +- core-cluster { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 0>; +- +- trips { +- core_cluster_alert: core-cluster-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- core-cluster-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&core_cluster_alert>; +- cooling-device = +- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- soc { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 1>; +- +- trips { +- soc-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ +- <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ +- <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ +- <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- sysclk: sysclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- clock-output-names = "sysclk"; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; +- +- clockgen: clocking@1300000 { +- compatible = "fsl,ls1088a-clockgen"; +- reg = <0 0x1300000 0 0xa0000>; +- #clock-cells = <2>; +- clocks = <&sysclk>; +- }; +- +- dcfg: dcfg@1e00000 { +- compatible = "fsl,ls1088a-dcfg", "syscon"; +- reg = <0x0 0x1e00000 0x0 0x10000>; +- little-endian; +- }; +- +- isc: syscon@1f70000 { +- compatible = "fsl,ls1088a-isc", "syscon"; +- reg = <0x0 0x1f70000 0x0 0x10000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1f70000 0x10000>; +- +- extirq: interrupt-controller@14 { +- compatible = "fsl,ls1088a-extirq"; +- #interrupt-cells = <2>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x14 4>; +- interrupt-map = +- <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, +- <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, +- <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, +- <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, +- <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, +- <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, +- <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, +- <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, +- <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, +- <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, +- <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, +- <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-map-mask = <0xffffffff 0x0>; +- }; +- }; +- +- tmu: tmu@1f80000 { +- compatible = "fsl,qoriq-tmu"; +- reg = <0x0 0x1f80000 0x0 0x10000>; +- interrupts = <0 23 0x4>; +- fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; +- fsl,tmu-calibration = +- /* Calibration data group 1 */ +- <0x00000000 0x00000023 +- 0x00000001 0x0000002a +- 0x00000002 0x00000030 +- 0x00000003 0x00000037 +- 0x00000004 0x0000003d +- 0x00000005 0x00000044 +- 0x00000006 0x0000004a +- 0x00000007 0x00000051 +- 0x00000008 0x00000057 +- 0x00000009 0x0000005e +- 0x0000000a 0x00000064 +- 0x0000000b 0x0000006b +- /* Calibration data group 2 */ +- 0x00010000 0x00000022 +- 0x00010001 0x0000002a +- 0x00010002 0x00000032 +- 0x00010003 0x0000003a +- 0x00010004 0x00000042 +- 0x00010005 0x0000004a +- 0x00010006 0x00000052 +- 0x00010007 0x0000005a +- 0x00010008 0x00000062 +- 0x00010009 0x0000006a +- /* Calibration data group 3 */ +- 0x00020000 0x00000021 +- 0x00020001 0x0000002b +- 0x00020002 0x00000035 +- 0x00020003 0x00000040 +- 0x00020004 0x0000004a +- 0x00020005 0x00000054 +- 0x00020006 0x0000005e +- /* Calibration data group 4 */ +- 0x00030000 0x00000010 +- 0x00030001 0x0000001c +- 0x00030002 0x00000027 +- 0x00030003 0x00000032 +- 0x00030004 0x0000003e +- 0x00030005 0x00000049 +- 0x00030006 0x00000054 +- 0x00030007 0x00000060>; +- little-endian; +- #thermal-sensor-cells = <1>; +- }; +- +- dspi: spi@2100000 { +- compatible = "fsl,ls1088a-dspi", +- "fsl,ls1021a-v1.0-dspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2100000 0x0 0x10000>; +- interrupts = ; +- clock-names = "dspi"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- spi-num-chipselects = <6>; +- status = "disabled"; +- }; +- +- duart0: serial@21c0500 { +- compatible = "fsl,ns16550", "ns16550a"; +- reg = <0x0 0x21c0500 0x0 0x100>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +- +- duart1: serial@21c0600 { +- compatible = "fsl,ns16550", "ns16550a"; +- reg = <0x0 0x21c0600 0x0 0x100>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +- +- gpio0: gpio@2300000 { +- compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; +- reg = <0x0 0x2300000 0x0 0x10000>; +- interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; +- little-endian; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio@2310000 { +- compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; +- reg = <0x0 0x2310000 0x0 0x10000>; +- interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; +- little-endian; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@2320000 { +- compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; +- reg = <0x0 0x2320000 0x0 0x10000>; +- interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; +- little-endian; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio@2330000 { +- compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; +- reg = <0x0 0x2330000 0x0 0x10000>; +- interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; +- little-endian; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- ifc: ifc@2240000 { +- compatible = "fsl,ifc", "simple-bus"; +- reg = <0x0 0x2240000 0x0 0x20000>; +- interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; +- little-endian; +- #address-cells = <2>; +- #size-cells = <1>; +- status = "disabled"; +- }; +- +- i2c0: i2c@2000000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2000000 0x0 0x10000>; +- interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(8)>; +- status = "disabled"; +- }; +- +- i2c1: i2c@2010000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2010000 0x0 0x10000>; +- interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(8)>; +- status = "disabled"; +- }; +- +- i2c2: i2c@2020000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2020000 0x0 0x10000>; +- interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(8)>; +- status = "disabled"; +- }; +- +- i2c3: i2c@2030000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2030000 0x0 0x10000>; +- interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(8)>; +- status = "disabled"; +- }; +- +- qspi: spi@20c0000 { +- compatible = "fsl,ls2080a-qspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x20c0000 0x0 0x10000>, +- <0x0 0x20000000 0x0 0x10000000>; +- reg-names = "QuadSPI", "QuadSPI-memory"; +- interrupts = ; +- clock-names = "qspi_en", "qspi"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- status = "disabled"; +- }; +- +- esdhc: esdhc@2140000 { +- compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; +- reg = <0x0 0x2140000 0x0 0x10000>; +- interrupts = <0 28 0x4>; /* Level high type */ +- clock-frequency = <0>; +- clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; +- voltage-ranges = <1800 1800 3300 3300>; +- sdhci,auto-cmd12; +- little-endian; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usb0: usb@3100000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0x3100000 0x0 0x10000>; +- interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; +- dr_mode = "host"; +- snps,quirk-frame-length-adjustment = <0x20>; +- snps,dis_rxdet_inp3_quirk; +- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; +- status = "disabled"; +- }; +- +- usb1: usb@3110000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0x3110000 0x0 0x10000>; +- interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; +- dr_mode = "host"; +- snps,quirk-frame-length-adjustment = <0x20>; +- snps,dis_rxdet_inp3_quirk; +- status = "disabled"; +- }; +- +- sata: sata@3200000 { +- compatible = "fsl,ls1088a-ahci"; +- reg = <0x0 0x3200000 0x0 0x10000>, +- <0x7 0x100520 0x0 0x4>; +- reg-names = "ahci", "sata-ecc"; +- interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- dma-coherent; +- status = "disabled"; +- }; +- +- crypto: crypto@8000000 { +- compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; +- fsl,sec-era = <8>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x00 0x8000000 0x100000>; +- reg = <0x00 0x8000000 0x0 0x100000>; +- interrupts = ; +- dma-coherent; +- +- sec_jr0: jr@10000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x10000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr1: jr@20000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x20000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr2: jr@30000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x30000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr3: jr@40000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x40000 0x10000>; +- interrupts = ; +- }; +- }; +- +- pcie1: pcie@3400000 { +- compatible = "fsl,ls1088a-pcie"; +- reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ +- <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "regs", "config"; +- interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ +- interrupt-names = "aer"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- num-viewport = <256>; +- bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ +- 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&its>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; +- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ +- status = "disabled"; +- }; +- +- pcie_ep1: pcie-ep@3400000 { +- compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; +- reg = <0x00 0x03400000 0x0 0x00100000>, +- <0x20 0x00000000 0x8 0x00000000>; +- reg-names = "regs", "addr_space"; +- num-ib-windows = <24>; +- num-ob-windows = <256>; +- max-functions = /bits/ 8 <2>; +- status = "disabled"; +- }; +- +- pcie2: pcie@3500000 { +- compatible = "fsl,ls1088a-pcie"; +- reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ +- <0x28 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "regs", "config"; +- interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ +- interrupt-names = "aer"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- num-viewport = <6>; +- bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ +- 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&its>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; +- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ +- status = "disabled"; +- }; +- +- pcie_ep2: pcie-ep@3500000 { +- compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; +- reg = <0x00 0x03500000 0x0 0x00100000>, +- <0x28 0x00000000 0x8 0x00000000>; +- reg-names = "regs", "addr_space"; +- num-ib-windows = <6>; +- num-ob-windows = <6>; +- status = "disabled"; +- }; +- +- pcie3: pcie@3600000 { +- compatible = "fsl,ls1088a-pcie"; +- reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ +- <0x30 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "regs", "config"; +- interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ +- interrupt-names = "aer"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- num-viewport = <6>; +- bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ +- 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&its>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; +- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ +- status = "disabled"; +- }; +- +- pcie_ep3: pcie-ep@3600000 { +- compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; +- reg = <0x00 0x03600000 0x0 0x00100000>, +- <0x30 0x00000000 0x8 0x00000000>; +- reg-names = "regs", "addr_space"; +- num-ib-windows = <6>; +- num-ob-windows = <6>; +- status = "disabled"; +- }; +- +- smmu: iommu@5000000 { +- compatible = "arm,mmu-500"; +- reg = <0 0x5000000 0 0x800000>; +- #iommu-cells = <1>; +- stream-match-mask = <0x7C00>; +- #global-interrupts = <12>; +- // global secure fault +- interrupts = , +- // combined secure +- , +- // global non-secure fault +- , +- // combined non-secure +- , +- // performance counter interrupts 0-7 +- , +- , +- , +- , +- , +- , +- , +- , +- // per context interrupt, 64 interrupts +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- }; +- +- console@8340020 { +- compatible = "fsl,dpaa2-console"; +- reg = <0x00000000 0x08340020 0 0x2>; +- }; +- +- ptp-timer@8b95000 { +- compatible = "fsl,dpaa2-ptp"; +- reg = <0x0 0x8b95000 0x0 0x100>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(1)>; +- little-endian; +- fsl,extts-fifo; +- }; +- +- emdio1: mdio@8b96000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8b96000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- emdio2: mdio@8b97000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8b97000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pcs_mdio1: mdio@8c07000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c07000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs1: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio2: mdio@8c0b000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c0b000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs2: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio3: mdio@8c0f000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c0f000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs3_0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- pcs3_1: ethernet-phy@1 { +- reg = <1>; +- }; +- +- pcs3_2: ethernet-phy@2 { +- reg = <2>; +- }; +- +- pcs3_3: ethernet-phy@3 { +- reg = <3>; +- }; +- }; +- +- pcs_mdio7: mdio@8c1f000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c1f000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs7_0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- pcs7_1: ethernet-phy@1 { +- reg = <1>; +- }; +- +- pcs7_2: ethernet-phy@2 { +- reg = <2>; +- }; +- +- pcs7_3: ethernet-phy@3 { +- reg = <3>; +- }; +- }; +- +- cluster1_core0_watchdog: wdt@c000000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xc000000 0x0 0x1000>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- cluster1_core1_watchdog: wdt@c010000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xc010000 0x0 0x1000>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- cluster1_core2_watchdog: wdt@c020000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xc020000 0x0 0x1000>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- cluster1_core3_watchdog: wdt@c030000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xc030000 0x0 0x1000>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- cluster2_core0_watchdog: wdt@c100000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xc100000 0x0 0x1000>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- cluster2_core1_watchdog: wdt@c110000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xc110000 0x0 0x1000>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- cluster2_core2_watchdog: wdt@c120000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xc120000 0x0 0x1000>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- cluster2_core3_watchdog: wdt@c130000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xc130000 0x0 0x1000>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- fsl_mc: fsl-mc@80c000000 { +- compatible = "fsl,qoriq-mc"; +- reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ +- <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ +- msi-parent = <&its>; +- iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ +- dma-coherent; +- #address-cells = <3>; +- #size-cells = <1>; +- +- /* +- * Region type 0x0 - MC portals +- * Region type 0x1 - QBMAN portals +- */ +- ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 +- 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; +- +- dpmacs { +- #address-cells = <1>; +- #size-cells = <0>; +- +- dpmac1: ethernet@1 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <1>; +- }; +- +- dpmac2: ethernet@2 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <2>; +- }; +- +- dpmac3: ethernet@3 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <3>; +- }; +- +- dpmac4: ethernet@4 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <4>; +- }; +- +- dpmac5: ethernet@5 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <5>; +- }; +- +- dpmac6: ethernet@6 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <6>; +- }; +- +- dpmac7: ethernet@7 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <7>; +- }; +- +- dpmac8: ethernet@8 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <8>; +- }; +- +- dpmac9: ethernet@9 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <9>; +- }; +- +- dpmac10: ethernet@a { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0xa>; +- }; +- }; +- }; +- +- rcpm: power-controller@1e34040 { +- compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+"; +- reg = <0x0 0x1e34040 0x0 0x18>; +- #fsl,rcpm-wakeup-cells = <6>; +- little-endian; +- }; +- +- ftm_alarm0: timer@2800000 { +- compatible = "fsl,ls1088a-ftm-alarm"; +- reg = <0x0 0x2800000 0x0 0x10000>; +- fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; +- interrupts = ; +- }; +- }; +- +- firmware { +- optee { +- compatible = "linaro,optee-tz"; +- method = "smc"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2080a-qds.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2080a-qds.dts +deleted file mode 100644 +index f6c3ee78ace0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2080a-qds.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Freescale LS2080a QDS Board. +- * +- * Copyright 2015-2016 Freescale Semiconductor, Inc. +- * Copyright 2017 NXP +- * +- * Abhimanyu Saini +- * Bhupesh Sharma +- * +- */ +- +-/dts-v1/; +- +-#include "fsl-ls2080a.dtsi" +-#include "fsl-ls208xa-qds.dtsi" +- +-/ { +- model = "Freescale Layerscape 2080a QDS Board"; +- compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2080a-rdb.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2080a-rdb.dts +deleted file mode 100644 +index 44894356059c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2080a-rdb.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Freescale LS2080a RDB Board. +- * +- * Copyright 2016 Freescale Semiconductor, Inc. +- * Copyright 2017 NXP +- * +- * Abhimanyu Saini +- * Bhupesh Sharma +- * +- */ +- +-/dts-v1/; +- +-#include "fsl-ls2080a.dtsi" +-#include "fsl-ls208xa-rdb.dtsi" +- +-/ { +- model = "Freescale Layerscape 2080a RDB Board"; +- compatible = "fsl,ls2080a-rdb", "fsl,ls2080a"; +- +- chosen { +- stdout-path = "serial1:115200n8"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2080a-simu.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2080a-simu.dts +deleted file mode 100644 +index 5517305039a4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2080a-simu.dts ++++ /dev/null +@@ -1,29 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Freescale LS2080a software Simulator model +- * +- * Copyright 2014-2015 Freescale Semiconductor, Inc. +- * +- * Bhupesh Sharma +- * +- */ +- +-/dts-v1/; +- +-#include "fsl-ls2080a.dtsi" +- +-/ { +- model = "Freescale Layerscape 2080a software Simulator model"; +- compatible = "fsl,ls2080a-simu", "fsl,ls2080a"; +- +- ethernet@2210000 { +- compatible = "smsc,lan91c111"; +- reg = <0x0 0x2210000 0x0 0x100>; +- interrupts = <0 58 0x1>; +- }; +-}; +- +-&ifc { +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2080a.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2080a.dtsi +deleted file mode 100644 +index 6f6667b70028..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2080a.dtsi ++++ /dev/null +@@ -1,152 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Freescale Layerscape-2080A family SoC. +- * +- * Copyright 2014-2016 Freescale Semiconductor, Inc. +- * +- * Abhimanyu Saini +- * Bhupesh Sharma +- * +- */ +- +-#include +-#include "fsl-ls208xa.dtsi" +- +-&cpu { +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x0>; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- cpu-idle-states = <&CPU_PW20>; +- next-level-cache = <&cluster0_l2>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x1>; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- cpu-idle-states = <&CPU_PW20>; +- next-level-cache = <&cluster0_l2>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x100>; +- clocks = <&clockgen QORIQ_CLK_CMUX 1>; +- cpu-idle-states = <&CPU_PW20>; +- next-level-cache = <&cluster1_l2>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x101>; +- clocks = <&clockgen QORIQ_CLK_CMUX 1>; +- cpu-idle-states = <&CPU_PW20>; +- next-level-cache = <&cluster1_l2>; +- #cooling-cells = <2>; +- }; +- +- cpu4: cpu@200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x200>; +- clocks = <&clockgen QORIQ_CLK_CMUX 2>; +- cpu-idle-states = <&CPU_PW20>; +- next-level-cache = <&cluster2_l2>; +- #cooling-cells = <2>; +- }; +- +- cpu5: cpu@201 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x201>; +- clocks = <&clockgen QORIQ_CLK_CMUX 2>; +- cpu-idle-states = <&CPU_PW20>; +- next-level-cache = <&cluster2_l2>; +- #cooling-cells = <2>; +- }; +- +- cpu6: cpu@300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x300>; +- clocks = <&clockgen QORIQ_CLK_CMUX 3>; +- next-level-cache = <&cluster3_l2>; +- cpu-idle-states = <&CPU_PW20>; +- #cooling-cells = <2>; +- }; +- +- cpu7: cpu@301 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x301>; +- clocks = <&clockgen QORIQ_CLK_CMUX 3>; +- cpu-idle-states = <&CPU_PW20>; +- next-level-cache = <&cluster3_l2>; +- #cooling-cells = <2>; +- }; +- +- cluster0_l2: l2-cache0 { +- compatible = "cache"; +- }; +- +- cluster1_l2: l2-cache1 { +- compatible = "cache"; +- }; +- +- cluster2_l2: l2-cache2 { +- compatible = "cache"; +- }; +- +- cluster3_l2: l2-cache3 { +- compatible = "cache"; +- }; +- +- CPU_PW20: cpu-pw20 { +- compatible = "arm,idle-state"; +- idle-state-name = "PW20"; +- arm,psci-suspend-param = <0x00010000>; +- entry-latency-us = <2000>; +- exit-latency-us = <2000>; +- min-residency-us = <6000>; +- }; +-}; +- +-&pcie1 { +- reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ +- <0x10 0x00000000 0x0 0x00002000>; /* configuration space */ +- +- ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ +- 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +-}; +- +-&pcie2 { +- reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ +- <0x12 0x00000000 0x0 0x00002000>; /* configuration space */ +- +- ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ +- 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +-}; +- +-&pcie3 { +- reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ +- <0x14 0x00000000 0x0 0x00002000>; /* configuration space */ +- +- ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ +- 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +-}; +- +-&pcie4 { +- reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ +- <0x16 0x00000000 0x0 0x00002000>; /* configuration space */ +- +- ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ +- 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2088a-qds.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2088a-qds.dts +deleted file mode 100644 +index 7c17b1bd4529..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2088a-qds.dts ++++ /dev/null +@@ -1,24 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Freescale LS2088A QDS Board. +- * +- * Copyright 2016 Freescale Semiconductor, Inc. +- * Copyright 2017 NXP +- * +- * Abhimanyu Saini +- * +- */ +- +-/dts-v1/; +- +-#include "fsl-ls2088a.dtsi" +-#include "fsl-ls208xa-qds.dtsi" +- +-/ { +- model = "Freescale Layerscape 2088A QDS Board"; +- compatible = "fsl,ls2088a-qds", "fsl,ls2088a"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2088a-rdb.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2088a-rdb.dts +deleted file mode 100644 +index 3e4e857db13f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2088a-rdb.dts ++++ /dev/null +@@ -1,148 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Freescale LS2088A RDB Board. +- * +- * Copyright 2016 Freescale Semiconductor, Inc. +- * Copyright 2017 NXP +- * +- * Abhimanyu Saini +- * +- */ +- +-/dts-v1/; +- +-#include "fsl-ls2088a.dtsi" +-#include "fsl-ls208xa-rdb.dtsi" +- +-/ { +- model = "Freescale Layerscape 2088A RDB Board"; +- compatible = "fsl,ls2088a-rdb", "fsl,ls2088a"; +- +- chosen { +- stdout-path = "serial1:115200n8"; +- }; +-}; +- +-&dpmac1 { +- phy-handle = <&mdio1_phy1>; +- phy-connection-type = "10gbase-r"; +-}; +- +-&dpmac2 { +- phy-handle = <&mdio1_phy2>; +- phy-connection-type = "10gbase-r"; +-}; +- +-&dpmac3 { +- phy-handle = <&mdio1_phy3>; +- phy-connection-type = "10gbase-r"; +-}; +- +-&dpmac4 { +- phy-handle = <&mdio1_phy4>; +- phy-connection-type = "10gbase-r"; +-}; +- +-&dpmac5 { +- phy-handle = <&mdio2_phy1>; +- phy-connection-type = "10gbase-r"; +-}; +- +-&dpmac6 { +- phy-handle = <&mdio2_phy2>; +- phy-connection-type = "10gbase-r"; +-}; +- +-&dpmac7 { +- phy-handle = <&mdio2_phy3>; +- phy-connection-type = "10gbase-r"; +-}; +- +-&dpmac8 { +- phy-handle = <&mdio2_phy4>; +- phy-connection-type = "10gbase-r"; +-}; +- +-&emdio1 { +- status = "okay"; +- +- mdio1_phy1: ethernet-phy@10 { +- compatible = "ethernet-phy-id13e5.1002"; +- reg = <0x10>; +- }; +- +- mdio1_phy2: ethernet-phy@11 { +- compatible = "ethernet-phy-id13e5.1002"; +- reg = <0x11>; +- }; +- +- mdio1_phy3: ethernet-phy@12 { +- compatible = "ethernet-phy-id13e5.1002"; +- reg = <0x12>; +- }; +- +- mdio1_phy4: ethernet-phy@13 { +- compatible = "ethernet-phy-id13e5.1002"; +- reg = <0x13>; +- }; +-}; +- +-&emdio2 { +- status = "okay"; +- +- mdio2_phy1: ethernet-phy@0 { +- compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; +- interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x0>; +- }; +- +- mdio2_phy2: ethernet-phy@1 { +- compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; +- interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x1>; +- }; +- +- mdio2_phy3: ethernet-phy@2 { +- compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; +- interrupts-extended = <&extirq 4 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x2>; +- }; +- +- mdio2_phy4: ethernet-phy@3 { +- compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; +- interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x3>; +- }; +-}; +- +-&pcs_mdio1 { +- status = "okay"; +-}; +- +-&pcs_mdio2 { +- status = "okay"; +-}; +- +-&pcs_mdio3 { +- status = "okay"; +-}; +- +-&pcs_mdio4 { +- status = "okay"; +-}; +- +-&pcs_mdio5 { +- status = "okay"; +-}; +- +-&pcs_mdio6 { +- status = "okay"; +-}; +- +-&pcs_mdio7 { +- status = "okay"; +-}; +- +-&pcs_mdio8 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2088a.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2088a.dtsi +deleted file mode 100644 +index c3dc38188c17..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls2088a.dtsi ++++ /dev/null +@@ -1,156 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Freescale Layerscape-2088A family SoC. +- * +- * Copyright 2016 Freescale Semiconductor, Inc. +- * Copyright 2017 NXP +- * +- * Abhimanyu Saini +- * +- */ +- +-#include +-#include "fsl-ls208xa.dtsi" +- +-&cpu { +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x0>; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- cpu-idle-states = <&CPU_PW20>; +- next-level-cache = <&cluster0_l2>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x1>; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- cpu-idle-states = <&CPU_PW20>; +- next-level-cache = <&cluster0_l2>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x100>; +- clocks = <&clockgen QORIQ_CLK_CMUX 1>; +- cpu-idle-states = <&CPU_PW20>; +- next-level-cache = <&cluster1_l2>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x101>; +- clocks = <&clockgen QORIQ_CLK_CMUX 1>; +- cpu-idle-states = <&CPU_PW20>; +- next-level-cache = <&cluster1_l2>; +- #cooling-cells = <2>; +- }; +- +- cpu4: cpu@200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x200>; +- clocks = <&clockgen QORIQ_CLK_CMUX 2>; +- next-level-cache = <&cluster2_l2>; +- cpu-idle-states = <&CPU_PW20>; +- #cooling-cells = <2>; +- }; +- +- cpu5: cpu@201 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x201>; +- clocks = <&clockgen QORIQ_CLK_CMUX 2>; +- cpu-idle-states = <&CPU_PW20>; +- next-level-cache = <&cluster2_l2>; +- #cooling-cells = <2>; +- }; +- +- cpu6: cpu@300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x300>; +- clocks = <&clockgen QORIQ_CLK_CMUX 3>; +- cpu-idle-states = <&CPU_PW20>; +- next-level-cache = <&cluster3_l2>; +- #cooling-cells = <2>; +- }; +- +- cpu7: cpu@301 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x301>; +- clocks = <&clockgen QORIQ_CLK_CMUX 3>; +- cpu-idle-states = <&CPU_PW20>; +- next-level-cache = <&cluster3_l2>; +- #cooling-cells = <2>; +- }; +- +- cluster0_l2: l2-cache0 { +- compatible = "cache"; +- }; +- +- cluster1_l2: l2-cache1 { +- compatible = "cache"; +- }; +- +- cluster2_l2: l2-cache2 { +- compatible = "cache"; +- }; +- +- cluster3_l2: l2-cache3 { +- compatible = "cache"; +- }; +- +- CPU_PW20: cpu-pw20 { +- compatible = "arm,idle-state"; +- idle-state-name = "PW20"; +- arm,psci-suspend-param = <0x0>; +- entry-latency-us = <2000>; +- exit-latency-us = <2000>; +- min-residency-us = <6000>; +- }; +-}; +- +-&pcie1 { +- compatible = "fsl,ls2088a-pcie"; +- reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ +- <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ +- +- ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 +- 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; +-}; +- +-&pcie2 { +- compatible = "fsl,ls2088a-pcie"; +- reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ +- <0x28 0x00000000 0x0 0x00002000>; /* configuration space */ +- +- ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 +- 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; +-}; +- +-&pcie3 { +- compatible = "fsl,ls2088a-pcie"; +- reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ +- <0x30 0x00000000 0x0 0x00002000>; /* configuration space */ +- +- ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 +- 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; +-}; +- +-&pcie4 { +- compatible = "fsl,ls2088a-pcie"; +- reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ +- <0x38 0x00000000 0x0 0x00002000>; /* configuration space */ +- +- ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000 +- 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls208xa-qds.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls208xa-qds.dtsi +deleted file mode 100644 +index 10d2fe091965..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls208xa-qds.dtsi ++++ /dev/null +@@ -1,166 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Freescale LS2080A QDS Board. +- * +- * Copyright 2016 Freescale Semiconductor, Inc. +- * Copyright 2017 NXP +- * +- * Abhimanyu Saini +- * +- */ +- +-&esdhc { +- mmc-hs200-1_8v; +- status = "okay"; +-}; +- +-&ifc { +- status = "okay"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x5 0x80000000 0x08000000 +- 0x2 0x0 0x5 0x30000000 0x00010000 +- 0x3 0x0 0x5 0x20000000 0x00010000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@2,0 { +- compatible = "fsl,ifc-nand"; +- reg = <0x2 0x0 0x10000>; +- }; +- +- cpld@3,0 { +- reg = <0x3 0x0 0x10000>; +- compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis"; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- pca9547@77 { +- compatible = "nxp,pca9547"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x00>; +- rtc@68 { +- compatible = "dallas,ds3232"; +- reg = <0x68>; +- }; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x02>; +- +- ina220@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <500>; +- }; +- +- ina220@41 { +- compatible = "ti,ina220"; +- reg = <0x41>; +- shunt-resistor = <1000>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3>; +- +- adt7481@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- status = "disabled"; +-}; +- +-&i2c2 { +- status = "disabled"; +-}; +- +-&i2c3 { +- status = "disabled"; +-}; +- +-&dspi { +- status = "okay"; +- dflash0: n25q128a@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p80"; +- spi-max-frequency = <3000000>; +- reg = <0>; +- }; +- dflash1: sst25wf040b@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p80"; +- spi-max-frequency = <3000000>; +- reg = <1>; +- }; +- dflash2: en25s64@2 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p80"; +- spi-max-frequency = <3000000>; +- reg = <2>; +- }; +-}; +- +-&qspi { +- status = "okay"; +- flash0: s25fl256s1@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p80"; +- spi-max-frequency = <20000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <4>; +- reg = <0>; +- }; +- flash2: s25fl256s1@2 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p80"; +- spi-max-frequency = <20000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <4>; +- reg = <2>; +- }; +-}; +- +-&sata0 { +- status = "okay"; +-}; +- +-&sata1 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls208xa-rdb.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls208xa-rdb.dtsi +deleted file mode 100644 +index 4b71c4fcb35f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls208xa-rdb.dtsi ++++ /dev/null +@@ -1,138 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Freescale LS2080A RDB Board. +- * +- * Copyright 2016 Freescale Semiconductor, Inc. +- * Copyright 2017-2020 NXP +- * +- * Abhimanyu Saini +- * +- */ +- +-&esdhc { +- status = "okay"; +-}; +- +-&ifc { +- status = "okay"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x5 0x80000000 0x08000000 +- 0x2 0x0 0x5 0x30000000 0x00010000 +- 0x3 0x0 0x5 0x20000000 0x00010000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@2,0 { +- compatible = "fsl,ifc-nand"; +- reg = <0x2 0x0 0x10000>; +- }; +- +- cpld@3,0 { +- reg = <0x3 0x0 0x10000>; +- compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis"; +- }; +- +-}; +- +-&i2c0 { +- status = "okay"; +- pca9547@75 { +- compatible = "nxp,pca9547"; +- reg = <0x75>; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x01>; +- rtc@68 { +- compatible = "dallas,ds3232"; +- reg = <0x68>; +- /* IRQ_RTC_B -> IRQ06, active low */ +- interrupts-extended = <&extirq 6 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x02>; +- +- ina220@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <500>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3>; +- +- adt7481@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- status = "disabled"; +-}; +- +-&i2c2 { +- status = "disabled"; +-}; +- +-&i2c3 { +- status = "disabled"; +-}; +- +-&dspi { +- status = "okay"; +- dflash0: n25q512a@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "st,m25p80"; +- spi-max-frequency = <3000000>; +- reg = <0>; +- }; +-}; +- +-&qspi { +- status = "okay"; +- +- s25fs512s0: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- reg = <0>; +- }; +-}; +- +-&sata0 { +- status = "okay"; +-}; +- +-&sata1 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls208xa.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls208xa.dtsi +deleted file mode 100644 +index 1282b61da8a5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls208xa.dtsi ++++ /dev/null +@@ -1,1239 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Freescale Layerscape-2080A family SoC. +- * +- * Copyright 2016 Freescale Semiconductor, Inc. +- * Copyright 2017-2020 NXP +- * +- * Abhimanyu Saini +- * +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "fsl,ls2080a"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- crypto = &crypto; +- rtc1 = &ftm_alarm0; +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- }; +- +- cpu: cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0 0x80000000>; +- /* DRAM space - 1, size : 2 GB DRAM */ +- }; +- +- sysclk: sysclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- clock-output-names = "sysclk"; +- }; +- +- gic: interrupt-controller@6000000 { +- compatible = "arm,gic-v3"; +- reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ +- <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ +- <0x0 0x0c0c0000 0 0x2000>, /* GICC */ +- <0x0 0x0c0d0000 0 0x1000>, /* GICH */ +- <0x0 0x0c0e0000 0 0x20000>; /* GICV */ +- #interrupt-cells = <3>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- interrupt-controller; +- interrupts = <1 9 0x4>; +- +- its: gic-its@6020000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- reg = <0x0 0x6020000 0 0x20000>; +- }; +- }; +- +- rstcr: syscon@1e60000 { +- compatible = "fsl,ls2080a-rstcr", "syscon"; +- reg = <0x0 0x1e60000 0x0 0x4>; +- }; +- +- reboot { +- compatible ="syscon-reboot"; +- regmap = <&rstcr>; +- offset = <0x0>; +- mask = <0x2>; +- }; +- +- thermal-zones { +- ddr-controller1 { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 1>; +- +- trips { +- ddr-ctrler1-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- ddr-controller2 { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 2>; +- +- trips { +- ddr-ctrler2-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- ddr-controller3 { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 3>; +- +- trips { +- ddr-ctrler3-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- core-cluster1 { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 4>; +- +- trips { +- core_cluster1_alert: core-cluster1-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- core-cluster1-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&core_cluster1_alert>; +- cooling-device = +- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- core-cluster2 { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 5>; +- +- trips { +- core_cluster2_alert: core-cluster2-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- core-cluster2-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&core_cluster2_alert>; +- cooling-device = +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- core-cluster3 { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 6>; +- +- trips { +- core_cluster3_alert: core-cluster3-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- core-cluster3-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&core_cluster3_alert>; +- cooling-device = +- <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- core-cluster4 { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 7>; +- +- trips { +- core_cluster4_alert: core-cluster4-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- core-cluster4-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&core_cluster4_alert>; +- cooling-device = +- <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = <1 13 4>, /* Physical Secure PPI, active-low */ +- <1 14 4>, /* Physical Non-Secure PPI, active-low */ +- <1 11 4>, /* Virtual PPI, active-low */ +- <1 10 4>; /* Hypervisor PPI, active-low */ +- fsl,erratum-a008585; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; +- +- clockgen: clocking@1300000 { +- compatible = "fsl,ls2080a-clockgen"; +- reg = <0 0x1300000 0 0xa0000>; +- #clock-cells = <2>; +- clocks = <&sysclk>; +- }; +- +- dcfg: dcfg@1e00000 { +- compatible = "fsl,ls2080a-dcfg", "syscon"; +- reg = <0x0 0x1e00000 0x0 0x10000>; +- little-endian; +- }; +- +- isc: syscon@1f70000 { +- compatible = "fsl,ls2080a-isc", "syscon"; +- reg = <0x0 0x1f70000 0x0 0x10000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1f70000 0x10000>; +- +- extirq: interrupt-controller@14 { +- compatible = "fsl,ls2080a-extirq", "fsl,ls1088a-extirq"; +- #interrupt-cells = <2>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x14 4>; +- interrupt-map = +- <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, +- <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, +- <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, +- <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, +- <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, +- <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, +- <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, +- <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, +- <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, +- <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, +- <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, +- <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-map-mask = <0xffffffff 0x0>; +- }; +- }; +- +- tmu: tmu@1f80000 { +- compatible = "fsl,qoriq-tmu"; +- reg = <0x0 0x1f80000 0x0 0x10000>; +- interrupts = <0 23 0x4>; +- fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; +- fsl,tmu-calibration = <0x00000000 0x00000026 +- 0x00000001 0x0000002d +- 0x00000002 0x00000032 +- 0x00000003 0x00000039 +- 0x00000004 0x0000003f +- 0x00000005 0x00000046 +- 0x00000006 0x0000004d +- 0x00000007 0x00000054 +- 0x00000008 0x0000005a +- 0x00000009 0x00000061 +- 0x0000000a 0x0000006a +- 0x0000000b 0x00000071 +- +- 0x00010000 0x00000025 +- 0x00010001 0x0000002c +- 0x00010002 0x00000035 +- 0x00010003 0x0000003d +- 0x00010004 0x00000045 +- 0x00010005 0x0000004e +- 0x00010006 0x00000057 +- 0x00010007 0x00000061 +- 0x00010008 0x0000006b +- 0x00010009 0x00000076 +- +- 0x00020000 0x00000029 +- 0x00020001 0x00000033 +- 0x00020002 0x0000003d +- 0x00020003 0x00000049 +- 0x00020004 0x00000056 +- 0x00020005 0x00000061 +- 0x00020006 0x0000006d +- +- 0x00030000 0x00000021 +- 0x00030001 0x0000002a +- 0x00030002 0x0000003c +- 0x00030003 0x0000004e>; +- little-endian; +- #thermal-sensor-cells = <1>; +- }; +- +- serial0: serial@21c0500 { +- compatible = "fsl,ns16550", "ns16550a"; +- reg = <0x0 0x21c0500 0x0 0x100>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- interrupts = <0 32 0x4>; /* Level high type */ +- }; +- +- serial1: serial@21c0600 { +- compatible = "fsl,ns16550", "ns16550a"; +- reg = <0x0 0x21c0600 0x0 0x100>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- interrupts = <0 32 0x4>; /* Level high type */ +- }; +- +- serial2: serial@21d0500 { +- compatible = "fsl,ns16550", "ns16550a"; +- reg = <0x0 0x21d0500 0x0 0x100>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- interrupts = <0 33 0x4>; /* Level high type */ +- }; +- +- serial3: serial@21d0600 { +- compatible = "fsl,ns16550", "ns16550a"; +- reg = <0x0 0x21d0600 0x0 0x100>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- interrupts = <0 33 0x4>; /* Level high type */ +- }; +- +- cluster1_core0_watchdog: wdt@c000000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xc000000 0x0 0x1000>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- cluster1_core1_watchdog: wdt@c010000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xc010000 0x0 0x1000>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- cluster2_core0_watchdog: wdt@c100000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xc100000 0x0 0x1000>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- cluster2_core1_watchdog: wdt@c110000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xc110000 0x0 0x1000>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- cluster3_core0_watchdog: wdt@c200000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xc200000 0x0 0x1000>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- cluster3_core1_watchdog: wdt@c210000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xc210000 0x0 0x1000>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- cluster4_core0_watchdog: wdt@c300000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xc300000 0x0 0x1000>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- cluster4_core1_watchdog: wdt@c310000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xc310000 0x0 0x1000>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- crypto: crypto@8000000 { +- compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; +- fsl,sec-era = <8>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x00 0x8000000 0x100000>; +- reg = <0x00 0x8000000 0x0 0x100000>; +- interrupts = ; +- dma-coherent; +- +- sec_jr0: jr@10000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x10000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr1: jr@20000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x20000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr2: jr@30000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x30000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr3: jr@40000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x40000 0x10000>; +- interrupts = ; +- }; +- }; +- +- console@8340020 { +- compatible = "fsl,dpaa2-console"; +- reg = <0x00000000 0x08340020 0 0x2>; +- }; +- +- ptp-timer@8b95000 { +- compatible = "fsl,dpaa2-ptp"; +- reg = <0x0 0x8b95000 0x0 0x100>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- little-endian; +- fsl,extts-fifo; +- }; +- +- emdio1: mdio@8b96000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8b96000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- emdio2: mdio@8b97000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8b97000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pcs_mdio1: mdio@8c07000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c07000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs1: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio2: mdio@8c0b000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c0b000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs2: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio3: mdio@8c0f000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c0f000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs3: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio4: mdio@8c13000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c13000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs4: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio5: mdio@8c17000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c17000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs5: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio6: mdio@8c1b000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c1b000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs6: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio7: mdio@8c1f000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c1f000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs7: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio8: mdio@8c23000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c23000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs8: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio9: mdio@8c27000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c27000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs9: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio10: mdio@8c2b000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c2b000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs10: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio11: mdio@8c2f000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c2f000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs11: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio12: mdio@8c33000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c33000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs12: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio13: mdio@8c37000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c37000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs13: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio14: mdio@8c3b000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c3b000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs14: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio15: mdio@8c3f000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c3f000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs15: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio16: mdio@8c43000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c43000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs16: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- fsl_mc: fsl-mc@80c000000 { +- compatible = "fsl,qoriq-mc"; +- reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ +- <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ +- msi-parent = <&its>; +- iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ +- dma-coherent; +- #address-cells = <3>; +- #size-cells = <1>; +- +- /* +- * Region type 0x0 - MC portals +- * Region type 0x1 - QBMAN portals +- */ +- ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 +- 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; +- +- /* +- * Define the maximum number of MACs present on the SoC. +- */ +- dpmacs { +- #address-cells = <1>; +- #size-cells = <0>; +- +- dpmac1: ethernet@1 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x1>; +- pcs-handle = <&pcs1>; +- }; +- +- dpmac2: ethernet@2 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x2>; +- pcs-handle = <&pcs2>; +- }; +- +- dpmac3: ethernet@3 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x3>; +- pcs-handle = <&pcs3>; +- }; +- +- dpmac4: ethernet@4 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x4>; +- pcs-handle = <&pcs4>; +- }; +- +- dpmac5: ethernet@5 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x5>; +- pcs-handle = <&pcs5>; +- }; +- +- dpmac6: ethernet@6 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x6>; +- pcs-handle = <&pcs6>; +- }; +- +- dpmac7: ethernet@7 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x7>; +- pcs-handle = <&pcs7>; +- }; +- +- dpmac8: ethernet@8 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x8>; +- pcs-handle = <&pcs8>; +- }; +- +- dpmac9: ethernet@9 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x9>; +- pcs-handle = <&pcs9>; +- }; +- +- dpmac10: ethernet@a { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0xa>; +- pcs-handle = <&pcs10>; +- }; +- +- dpmac11: ethernet@b { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0xb>; +- pcs-handle = <&pcs11>; +- }; +- +- dpmac12: ethernet@c { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0xc>; +- pcs-handle = <&pcs12>; +- }; +- +- dpmac13: ethernet@d { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0xd>; +- pcs-handle = <&pcs13>; +- }; +- +- dpmac14: ethernet@e { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0xe>; +- pcs-handle = <&pcs14>; +- }; +- +- dpmac15: ethernet@f { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0xf>; +- pcs-handle = <&pcs15>; +- }; +- +- dpmac16: ethernet@10 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x10>; +- pcs-handle = <&pcs16>; +- }; +- }; +- }; +- +- smmu: iommu@5000000 { +- compatible = "arm,mmu-500"; +- reg = <0 0x5000000 0 0x800000>; +- #global-interrupts = <12>; +- #iommu-cells = <1>; +- stream-match-mask = <0x7C00>; +- dma-coherent; +- interrupts = <0 13 4>, /* global secure fault */ +- <0 14 4>, /* combined secure interrupt */ +- <0 15 4>, /* global non-secure fault */ +- <0 16 4>, /* combined non-secure interrupt */ +- /* performance counter interrupts 0-7 */ +- <0 211 4>, <0 212 4>, +- <0 213 4>, <0 214 4>, +- <0 215 4>, <0 216 4>, +- <0 217 4>, <0 218 4>, +- /* per context interrupt, 64 interrupts */ +- <0 146 4>, <0 147 4>, +- <0 148 4>, <0 149 4>, +- <0 150 4>, <0 151 4>, +- <0 152 4>, <0 153 4>, +- <0 154 4>, <0 155 4>, +- <0 156 4>, <0 157 4>, +- <0 158 4>, <0 159 4>, +- <0 160 4>, <0 161 4>, +- <0 162 4>, <0 163 4>, +- <0 164 4>, <0 165 4>, +- <0 166 4>, <0 167 4>, +- <0 168 4>, <0 169 4>, +- <0 170 4>, <0 171 4>, +- <0 172 4>, <0 173 4>, +- <0 174 4>, <0 175 4>, +- <0 176 4>, <0 177 4>, +- <0 178 4>, <0 179 4>, +- <0 180 4>, <0 181 4>, +- <0 182 4>, <0 183 4>, +- <0 184 4>, <0 185 4>, +- <0 186 4>, <0 187 4>, +- <0 188 4>, <0 189 4>, +- <0 190 4>, <0 191 4>, +- <0 192 4>, <0 193 4>, +- <0 194 4>, <0 195 4>, +- <0 196 4>, <0 197 4>, +- <0 198 4>, <0 199 4>, +- <0 200 4>, <0 201 4>, +- <0 202 4>, <0 203 4>, +- <0 204 4>, <0 205 4>, +- <0 206 4>, <0 207 4>, +- <0 208 4>, <0 209 4>; +- }; +- +- dspi: spi@2100000 { +- status = "disabled"; +- compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2100000 0x0 0x10000>; +- interrupts = <0 26 0x4>; /* Level high type */ +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- clock-names = "dspi"; +- spi-num-chipselects = <5>; +- }; +- +- esdhc: esdhc@2140000 { +- status = "disabled"; +- compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; +- reg = <0x0 0x2140000 0x0 0x10000>; +- interrupts = <0 28 0x4>; /* Level high type */ +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- voltage-ranges = <1800 1800 3300 3300>; +- sdhci,auto-cmd12; +- little-endian; +- bus-width = <4>; +- }; +- +- gpio0: gpio@2300000 { +- compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; +- reg = <0x0 0x2300000 0x0 0x10000>; +- interrupts = <0 36 0x4>; /* Level high type */ +- gpio-controller; +- little-endian; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio@2310000 { +- compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; +- reg = <0x0 0x2310000 0x0 0x10000>; +- interrupts = <0 36 0x4>; /* Level high type */ +- gpio-controller; +- little-endian; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@2320000 { +- compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; +- reg = <0x0 0x2320000 0x0 0x10000>; +- interrupts = <0 37 0x4>; /* Level high type */ +- gpio-controller; +- little-endian; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio@2330000 { +- compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; +- reg = <0x0 0x2330000 0x0 0x10000>; +- interrupts = <0 37 0x4>; /* Level high type */ +- gpio-controller; +- little-endian; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- i2c0: i2c@2000000 { +- status = "disabled"; +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2000000 0x0 0x10000>; +- interrupts = <0 34 0x4>; /* Level high type */ +- clock-names = "i2c"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- }; +- +- i2c1: i2c@2010000 { +- status = "disabled"; +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2010000 0x0 0x10000>; +- interrupts = <0 34 0x4>; /* Level high type */ +- clock-names = "i2c"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- }; +- +- i2c2: i2c@2020000 { +- status = "disabled"; +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2020000 0x0 0x10000>; +- interrupts = <0 35 0x4>; /* Level high type */ +- clock-names = "i2c"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- }; +- +- i2c3: i2c@2030000 { +- status = "disabled"; +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2030000 0x0 0x10000>; +- interrupts = <0 35 0x4>; /* Level high type */ +- clock-names = "i2c"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- }; +- +- ifc: ifc@2240000 { +- compatible = "fsl,ifc", "simple-bus"; +- reg = <0x0 0x2240000 0x0 0x20000>; +- interrupts = <0 21 0x4>; /* Level high type */ +- little-endian; +- #address-cells = <2>; +- #size-cells = <1>; +- +- ranges = <0 0 0x5 0x80000000 0x08000000 +- 2 0 0x5 0x30000000 0x00010000 +- 3 0 0x5 0x20000000 0x00010000>; +- }; +- +- qspi: spi@20c0000 { +- compatible = "fsl,ls2080a-qspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x20c0000 0x0 0x10000>, +- <0x0 0x20000000 0x0 0x10000000>; +- reg-names = "QuadSPI", "QuadSPI-memory"; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- clock-names = "qspi_en", "qspi"; +- status = "disabled"; +- }; +- +- pcie1: pcie@3400000 { +- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; +- reg-names = "regs", "config"; +- interrupts = <0 108 0x4>; /* Level high type */ +- interrupt-names = "intr"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- num-viewport = <6>; +- bus-range = <0x0 0xff>; +- msi-parent = <&its>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, +- <0000 0 0 2 &gic 0 0 0 110 4>, +- <0000 0 0 3 &gic 0 0 0 111 4>, +- <0000 0 0 4 &gic 0 0 0 112 4>; +- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ +- status = "disabled"; +- }; +- +- pcie2: pcie@3500000 { +- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; +- reg-names = "regs", "config"; +- interrupts = <0 113 0x4>; /* Level high type */ +- interrupt-names = "intr"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- num-viewport = <6>; +- bus-range = <0x0 0xff>; +- msi-parent = <&its>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, +- <0000 0 0 2 &gic 0 0 0 115 4>, +- <0000 0 0 3 &gic 0 0 0 116 4>, +- <0000 0 0 4 &gic 0 0 0 117 4>; +- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ +- status = "disabled"; +- }; +- +- pcie3: pcie@3600000 { +- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; +- reg-names = "regs", "config"; +- interrupts = <0 118 0x4>; /* Level high type */ +- interrupt-names = "intr"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- num-viewport = <256>; +- bus-range = <0x0 0xff>; +- msi-parent = <&its>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, +- <0000 0 0 2 &gic 0 0 0 120 4>, +- <0000 0 0 3 &gic 0 0 0 121 4>, +- <0000 0 0 4 &gic 0 0 0 122 4>; +- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ +- status = "disabled"; +- }; +- +- pcie4: pcie@3700000 { +- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; +- reg-names = "regs", "config"; +- interrupts = <0 123 0x4>; /* Level high type */ +- interrupt-names = "intr"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- num-viewport = <6>; +- bus-range = <0x0 0xff>; +- msi-parent = <&its>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, +- <0000 0 0 2 &gic 0 0 0 125 4>, +- <0000 0 0 3 &gic 0 0 0 126 4>, +- <0000 0 0 4 &gic 0 0 0 127 4>; +- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ +- status = "disabled"; +- }; +- +- sata0: sata@3200000 { +- status = "disabled"; +- compatible = "fsl,ls2080a-ahci"; +- reg = <0x0 0x3200000 0x0 0x10000>; +- interrupts = <0 133 0x4>; /* Level high type */ +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- dma-coherent; +- }; +- +- sata1: sata@3210000 { +- status = "disabled"; +- compatible = "fsl,ls2080a-ahci"; +- reg = <0x0 0x3210000 0x0 0x10000>; +- interrupts = <0 136 0x4>; /* Level high type */ +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- dma-coherent; +- }; +- +- usb0: usb@3100000 { +- status = "disabled"; +- compatible = "snps,dwc3"; +- reg = <0x0 0x3100000 0x0 0x10000>; +- interrupts = <0 80 0x4>; /* Level high type */ +- dr_mode = "host"; +- snps,quirk-frame-length-adjustment = <0x20>; +- snps,dis_rxdet_inp3_quirk; +- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; +- }; +- +- usb1: usb@3110000 { +- status = "disabled"; +- compatible = "snps,dwc3"; +- reg = <0x0 0x3110000 0x0 0x10000>; +- interrupts = <0 81 0x4>; /* Level high type */ +- dr_mode = "host"; +- snps,quirk-frame-length-adjustment = <0x20>; +- snps,dis_rxdet_inp3_quirk; +- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; +- }; +- +- ccn@4000000 { +- compatible = "arm,ccn-504"; +- reg = <0x0 0x04000000 0x0 0x01000000>; +- interrupts = <0 12 4>; +- }; +- +- rcpm: power-controller@1e34040 { +- compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+"; +- reg = <0x0 0x1e34040 0x0 0x18>; +- #fsl,rcpm-wakeup-cells = <6>; +- little-endian; +- }; +- +- ftm_alarm0: timer@2800000 { +- compatible = "fsl,ls208xa-ftm-alarm"; +- reg = <0x0 0x2800000 0x0 0x10000>; +- fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; +- interrupts = ; +- }; +- }; +- +- ddr1: memory-controller@1080000 { +- compatible = "fsl,qoriq-memory-controller"; +- reg = <0x0 0x1080000 0x0 0x1000>; +- interrupts = <0 17 0x4>; +- little-endian; +- }; +- +- ddr2: memory-controller@1090000 { +- compatible = "fsl,qoriq-memory-controller"; +- reg = <0x0 0x1090000 0x0 0x1000>; +- interrupts = <0 18 0x4>; +- little-endian; +- }; +- +- firmware { +- optee { +- compatible = "linaro,optee-tz"; +- method = "smc"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a-cex7.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a-cex7.dtsi +deleted file mode 100644 +index afb455210bd0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a-cex7.dtsi ++++ /dev/null +@@ -1,187 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Device Tree file for LX2160A-CEx7 +-// +-// Copyright 2019 SolidRun Ltd. +- +-/dts-v1/; +- +-#include "fsl-lx2160a.dtsi" +- +-/ { +- model = "SolidRun LX2160A COM Express Type 7 module"; +- compatible = "solidrun,lx2160a-cex7", "fsl,lx2160a"; +- +- aliases { +- crypto = &crypto; +- }; +- +- sb_3v3: regulator-sb3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "RT7290"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&crypto { +- status = "okay"; +-}; +- +-&dpmac17 { +- phy-handle = <&rgmii_phy1>; +- phy-connection-type = "rgmii-id"; +-}; +- +-&emdio1 { +- status = "okay"; +- +- rgmii_phy1: ethernet-phy@1 { +- reg = <1>; +- qca,smarteee-tw-us-1g = <24>; +- }; +-}; +- +-&esdhc1 { +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- bus-width = <8>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- i2c-switch@77 { +- compatible = "nxp,pca9547"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x77>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- eeprom@50 { +- compatible = "atmel,24c512"; +- reg = <0x50>; +- }; +- +- eeprom@51 { +- compatible = "atmel,spd"; +- reg = <0x51>; +- }; +- +- eeprom@53 { +- compatible = "atmel,spd"; +- reg = <0x53>; +- }; +- +- eeprom@57 { +- compatible = "atmel,24c02"; +- reg = <0x57>; +- }; +- }; +- +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- fan-temperature-ctrlr@18 { +- compatible = "ti,amc6821"; +- reg = <0x18>; +- cooling-min-state = <0>; +- cooling-max-state = <9>; +- #cooling-cells = <2>; +- }; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- regulator@5c { +- compatible = "lltc,ltc3882"; +- reg = <0x5c>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- temperature-sensor@48 { +- compatible = "nxp,sa56004"; +- reg = <0x48>; +- vcc-supply = <&sb_3v3>; +- }; +- }; +- +- sfp0_i2c: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- }; +- +- sfp1_i2c: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- sfp2_i2c: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- }; +- +- sfp3_i2c: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +- +- rtc@51 { +- compatible = "nxp,pcf2129"; +- reg = <0x51>; +- }; +-}; +- +-&fspi { +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,m25p80"; +- m25p,fast-read; +- spi-max-frequency = <50000000>; +- reg = <0>; +- /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ +- spi-rx-bus-width = <8>; +- spi-tx-bus-width = <1>; +- }; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a-clearfog-cx.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a-clearfog-cx.dts +deleted file mode 100644 +index 86a9b771428d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a-clearfog-cx.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Device Tree file for LX2160A Clearfog CX board +-// +-// Copyright 2019 SolidRun Ltd. +- +-/dts-v1/; +- +-#include "fsl-lx2160a-clearfog-itx.dtsi" +- +-/ { +- model = "SolidRun LX2160A Clearfog CX"; +- compatible = "solidrun,clearfog-cx", +- "solidrun,lx2160a-cex7", "fsl,lx2160a"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a-clearfog-itx.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a-clearfog-itx.dtsi +deleted file mode 100644 +index 17f8e733972a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a-clearfog-itx.dtsi ++++ /dev/null +@@ -1,133 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Device Tree file for LX2160A Clearfog ITX board; this contains the +-// common parts shared between the Clearfog CX and Honeycomb builds. +-// +-// Copyright 2019 SolidRun Ltd. +- +-/dts-v1/; +- +-#include "fsl-lx2160a-cex7.dtsi" +-#include +- +-/ { +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- key { +- label = "power"; +- linux,can-disable; +- linux,code = ; +- gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- sfp0: sfp-0 { +- compatible = "sff,sfp"; +- i2c-bus = <&sfp0_i2c>; +- mod-def0-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>; +- maximum-power-milliwatt = <2000>; +- }; +- +- sfp1: sfp-1 { +- compatible = "sff,sfp"; +- i2c-bus = <&sfp1_i2c>; +- mod-def0-gpio = <&gpio2 9 GPIO_ACTIVE_LOW>; +- maximum-power-milliwatt = <2000>; +- }; +- +- sfp2: sfp-2 { +- compatible = "sff,sfp"; +- i2c-bus = <&sfp2_i2c>; +- mod-def0-gpio = <&gpio2 10 GPIO_ACTIVE_LOW>; +- maximum-power-milliwatt = <2000>; +- }; +- +- sfp3: sfp-3 { +- compatible = "sff,sfp"; +- i2c-bus = <&sfp3_i2c>; +- mod-def0-gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; +- maximum-power-milliwatt = <2000>; +- }; +-}; +- +-&dpmac7 { +- sfp = <&sfp0>; +- managed = "in-band-status"; +-}; +- +-&dpmac8 { +- sfp = <&sfp1>; +- managed = "in-band-status"; +-}; +- +-&dpmac9 { +- sfp = <&sfp2>; +- managed = "in-band-status"; +-}; +- +-&dpmac10 { +- sfp = <&sfp3>; +- managed = "in-band-status"; +-}; +- +-&emdio2 { +- status = "okay"; +-}; +- +-&esdhc0 { +- sd-uhs-sdr104; +- sd-uhs-sdr50; +- sd-uhs-sdr25; +- sd-uhs-sdr12; +- status = "okay"; +-}; +- +-&pcs_mdio7 { +- status = "okay"; +-}; +- +-&pcs_mdio8 { +- status = "okay"; +-}; +- +-&pcs_mdio9 { +- status = "okay"; +-}; +- +-&pcs_mdio10 { +- status = "okay"; +-}; +- +-&sata0 { +- status = "okay"; +-}; +- +-&sata1 { +- status = "okay"; +-}; +- +-&sata2 { +- status = "okay"; +-}; +- +-&sata3 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a-honeycomb.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a-honeycomb.dts +deleted file mode 100644 +index fe19f3009ea5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a-honeycomb.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Device Tree file for LX2160A Honeycomb board +-// +-// Copyright 2019 SolidRun Ltd. +- +-/dts-v1/; +- +-#include "fsl-lx2160a-clearfog-itx.dtsi" +- +-/ { +- model = "SolidRun LX2160A Honeycomb"; +- compatible = "solidrun,honeycomb", +- "solidrun,lx2160a-cex7", "fsl,lx2160a"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a-qds.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a-qds.dts +deleted file mode 100644 +index d858d9c8b583..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a-qds.dts ++++ /dev/null +@@ -1,189 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Device Tree file for LX2160AQDS +-// +-// Copyright 2018 NXP +- +-/dts-v1/; +- +-#include "fsl-lx2160a.dtsi" +- +-/ { +- model = "NXP Layerscape LX2160AQDS"; +- compatible = "fsl,lx2160a-qds", "fsl,lx2160a"; +- +- aliases { +- crypto = &crypto; +- mmc0 = &esdhc0; +- mmc1 = &esdhc1; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- sb_3v3: regulator-sb3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "MC34717-3.3VSB"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&can0 { +- status = "okay"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&crypto { +- status = "okay"; +-}; +- +-&dspi0 { +- status = "okay"; +- +- dflash0: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +-}; +- +-&dspi1 { +- status = "okay"; +- +- dflash1: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +-}; +- +-&dspi2 { +- status = "okay"; +- +- dflash2: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +-}; +- +-&esdhc0 { +- status = "okay"; +-}; +- +-&esdhc1 { +- status = "okay"; +-}; +- +-&fspi { +- status = "okay"; +- +- mt35xu512aba0: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- m25p,fast-read; +- spi-max-frequency = <50000000>; +- reg = <0>; +- spi-rx-bus-width = <8>; +- spi-tx-bus-width = <8>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- i2c-mux@77 { +- compatible = "nxp,pca9547"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; +- +- power-monitor@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <500>; +- }; +- +- power-monitor@41 { +- compatible = "ti,ina220"; +- reg = <0x41>; +- shunt-resistor = <1000>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3>; +- +- temperature-sensor@4c { +- compatible = "nxp,sa56004"; +- reg = <0x4c>; +- vcc-supply = <&sb_3v3>; +- }; +- +- temperature-sensor@4d { +- compatible = "nxp,sa56004"; +- reg = <0x4d>; +- vcc-supply = <&sb_3v3>; +- }; +- +- rtc@51 { +- compatible = "nxp,pcf2129"; +- reg = <0x51>; +- }; +- }; +- }; +-}; +- +-&sata0 { +- status = "okay"; +-}; +- +-&sata1 { +- status = "okay"; +-}; +- +-&sata2 { +- status = "okay"; +-}; +- +-&sata3 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a-rdb.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a-rdb.dts +deleted file mode 100644 +index 028ff8074b9d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a-rdb.dts ++++ /dev/null +@@ -1,243 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Device Tree file for LX2160ARDB +-// +-// Copyright 2018-2020 NXP +- +-/dts-v1/; +- +-#include "fsl-lx2160a.dtsi" +- +-/ { +- model = "NXP Layerscape LX2160ARDB"; +- compatible = "fsl,lx2160a-rdb", "fsl,lx2160a"; +- +- aliases { +- crypto = &crypto; +- mmc0 = &esdhc0; +- mmc1 = &esdhc1; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- sb_3v3: regulator-sb3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "MC34717-3.3VSB"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&crypto { +- status = "okay"; +-}; +- +-&dpmac3 { +- phy-handle = <&aquantia_phy1>; +- phy-connection-type = "usxgmii"; +- managed = "in-band-status"; +-}; +- +-&dpmac4 { +- phy-handle = <&aquantia_phy2>; +- phy-connection-type = "usxgmii"; +- managed = "in-band-status"; +-}; +- +-&dpmac17 { +- phy-handle = <&rgmii_phy1>; +- phy-connection-type = "rgmii-id"; +-}; +- +-&dpmac18 { +- phy-handle = <&rgmii_phy2>; +- phy-connection-type = "rgmii-id"; +-}; +- +-&emdio1 { +- status = "okay"; +- +- rgmii_phy1: ethernet-phy@1 { +- /* AR8035 PHY */ +- compatible = "ethernet-phy-id004d.d072"; +- interrupts-extended = <&extirq 4 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x1>; +- eee-broken-1000t; +- }; +- +- rgmii_phy2: ethernet-phy@2 { +- /* AR8035 PHY */ +- compatible = "ethernet-phy-id004d.d072"; +- interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x2>; +- eee-broken-1000t; +- }; +- +- aquantia_phy1: ethernet-phy@4 { +- /* AQR107 PHY */ +- compatible = "ethernet-phy-ieee802.3-c45"; +- interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x4>; +- }; +- +- aquantia_phy2: ethernet-phy@5 { +- /* AQR107 PHY */ +- compatible = "ethernet-phy-ieee802.3-c45"; +- interrupts-extended = <&extirq 3 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x5>; +- }; +-}; +- +-&can0 { +- status = "okay"; +- +- can-transceiver { +- max-bitrate = <5000000>; +- }; +-}; +- +-&can1 { +- status = "okay"; +- +- can-transceiver { +- max-bitrate = <5000000>; +- }; +-}; +- +-&esdhc0 { +- sd-uhs-sdr104; +- sd-uhs-sdr50; +- sd-uhs-sdr25; +- sd-uhs-sdr12; +- status = "okay"; +-}; +- +-&esdhc1 { +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- bus-width = <8>; +- status = "okay"; +-}; +- +-&fspi { +- status = "okay"; +- +- mt35xu512aba0: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- m25p,fast-read; +- spi-max-frequency = <50000000>; +- reg = <0>; +- spi-rx-bus-width = <8>; +- spi-tx-bus-width = <8>; +- }; +- +- mt35xu512aba1: flash@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- m25p,fast-read; +- spi-max-frequency = <50000000>; +- reg = <1>; +- spi-rx-bus-width = <8>; +- spi-tx-bus-width = <8>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- i2c-mux@77 { +- compatible = "nxp,pca9547"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; +- +- power-monitor@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <500>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3>; +- +- temperature-sensor@4c { +- compatible = "nxp,sa56004"; +- reg = <0x4c>; +- vcc-supply = <&sb_3v3>; +- }; +- +- temperature-sensor@4d { +- compatible = "nxp,sa56004"; +- reg = <0x4d>; +- vcc-supply = <&sb_3v3>; +- }; +- }; +- }; +-}; +- +-&i2c4 { +- status = "okay"; +- +- rtc@51 { +- compatible = "nxp,pcf2129"; +- reg = <0x51>; +- /* IRQ_RTC_B -> IRQ08, active low */ +- interrupts-extended = <&extirq 8 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&pcs_mdio3 { +- status = "okay"; +-}; +- +-&pcs_mdio4 { +- status = "okay"; +-}; +- +-&sata0 { +- status = "okay"; +-}; +- +-&sata1 { +- status = "okay"; +-}; +- +-&sata2 { +- status = "okay"; +-}; +- +-&sata3 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a.dtsi +deleted file mode 100644 +index 51c4f61007cd..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2160a.dtsi ++++ /dev/null +@@ -1,1754 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Device Tree Include file for Layerscape-LX2160A family SoC. +-// +-// Copyright 2018-2020 NXP +- +-#include +-#include +-#include +-#include +- +-/memreserve/ 0x80000000 0x00010000; +- +-/ { +- compatible = "fsl,lx2160a"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- rtc1 = &ftm_alarm0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- // 8 clusters having 2 Cortex-A72 cores each +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- enable-method = "psci"; +- reg = <0x0>; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <192>; +- next-level-cache = <&cluster0_l2>; +- cpu-idle-states = <&cpu_pw15>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- enable-method = "psci"; +- reg = <0x1>; +- clocks = <&clockgen QORIQ_CLK_CMUX 0>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <192>; +- next-level-cache = <&cluster0_l2>; +- cpu-idle-states = <&cpu_pw15>; +- #cooling-cells = <2>; +- }; +- +- cpu100: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- enable-method = "psci"; +- reg = <0x100>; +- clocks = <&clockgen QORIQ_CLK_CMUX 1>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <192>; +- next-level-cache = <&cluster1_l2>; +- cpu-idle-states = <&cpu_pw15>; +- #cooling-cells = <2>; +- }; +- +- cpu101: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- enable-method = "psci"; +- reg = <0x101>; +- clocks = <&clockgen QORIQ_CLK_CMUX 1>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <192>; +- next-level-cache = <&cluster1_l2>; +- cpu-idle-states = <&cpu_pw15>; +- #cooling-cells = <2>; +- }; +- +- cpu200: cpu@200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- enable-method = "psci"; +- reg = <0x200>; +- clocks = <&clockgen QORIQ_CLK_CMUX 2>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <192>; +- next-level-cache = <&cluster2_l2>; +- cpu-idle-states = <&cpu_pw15>; +- #cooling-cells = <2>; +- }; +- +- cpu201: cpu@201 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- enable-method = "psci"; +- reg = <0x201>; +- clocks = <&clockgen QORIQ_CLK_CMUX 2>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <192>; +- next-level-cache = <&cluster2_l2>; +- cpu-idle-states = <&cpu_pw15>; +- #cooling-cells = <2>; +- }; +- +- cpu300: cpu@300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- enable-method = "psci"; +- reg = <0x300>; +- clocks = <&clockgen QORIQ_CLK_CMUX 3>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <192>; +- next-level-cache = <&cluster3_l2>; +- cpu-idle-states = <&cpu_pw15>; +- #cooling-cells = <2>; +- }; +- +- cpu301: cpu@301 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- enable-method = "psci"; +- reg = <0x301>; +- clocks = <&clockgen QORIQ_CLK_CMUX 3>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <192>; +- next-level-cache = <&cluster3_l2>; +- cpu-idle-states = <&cpu_pw15>; +- #cooling-cells = <2>; +- }; +- +- cpu400: cpu@400 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- enable-method = "psci"; +- reg = <0x400>; +- clocks = <&clockgen QORIQ_CLK_CMUX 4>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <192>; +- next-level-cache = <&cluster4_l2>; +- cpu-idle-states = <&cpu_pw15>; +- #cooling-cells = <2>; +- }; +- +- cpu401: cpu@401 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- enable-method = "psci"; +- reg = <0x401>; +- clocks = <&clockgen QORIQ_CLK_CMUX 4>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <192>; +- next-level-cache = <&cluster4_l2>; +- cpu-idle-states = <&cpu_pw15>; +- #cooling-cells = <2>; +- }; +- +- cpu500: cpu@500 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- enable-method = "psci"; +- reg = <0x500>; +- clocks = <&clockgen QORIQ_CLK_CMUX 5>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <192>; +- next-level-cache = <&cluster5_l2>; +- cpu-idle-states = <&cpu_pw15>; +- #cooling-cells = <2>; +- }; +- +- cpu501: cpu@501 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- enable-method = "psci"; +- reg = <0x501>; +- clocks = <&clockgen QORIQ_CLK_CMUX 5>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <192>; +- next-level-cache = <&cluster5_l2>; +- cpu-idle-states = <&cpu_pw15>; +- #cooling-cells = <2>; +- }; +- +- cpu600: cpu@600 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- enable-method = "psci"; +- reg = <0x600>; +- clocks = <&clockgen QORIQ_CLK_CMUX 6>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <192>; +- next-level-cache = <&cluster6_l2>; +- cpu-idle-states = <&cpu_pw15>; +- #cooling-cells = <2>; +- }; +- +- cpu601: cpu@601 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- enable-method = "psci"; +- reg = <0x601>; +- clocks = <&clockgen QORIQ_CLK_CMUX 6>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <192>; +- next-level-cache = <&cluster6_l2>; +- cpu-idle-states = <&cpu_pw15>; +- #cooling-cells = <2>; +- }; +- +- cpu700: cpu@700 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- enable-method = "psci"; +- reg = <0x700>; +- clocks = <&clockgen QORIQ_CLK_CMUX 7>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <192>; +- next-level-cache = <&cluster7_l2>; +- cpu-idle-states = <&cpu_pw15>; +- #cooling-cells = <2>; +- }; +- +- cpu701: cpu@701 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- enable-method = "psci"; +- reg = <0x701>; +- clocks = <&clockgen QORIQ_CLK_CMUX 7>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <192>; +- next-level-cache = <&cluster7_l2>; +- cpu-idle-states = <&cpu_pw15>; +- #cooling-cells = <2>; +- }; +- +- cluster0_l2: l2-cache0 { +- compatible = "cache"; +- cache-size = <0x100000>; +- cache-line-size = <64>; +- cache-sets = <1024>; +- cache-level = <2>; +- }; +- +- cluster1_l2: l2-cache1 { +- compatible = "cache"; +- cache-size = <0x100000>; +- cache-line-size = <64>; +- cache-sets = <1024>; +- cache-level = <2>; +- }; +- +- cluster2_l2: l2-cache2 { +- compatible = "cache"; +- cache-size = <0x100000>; +- cache-line-size = <64>; +- cache-sets = <1024>; +- cache-level = <2>; +- }; +- +- cluster3_l2: l2-cache3 { +- compatible = "cache"; +- cache-size = <0x100000>; +- cache-line-size = <64>; +- cache-sets = <1024>; +- cache-level = <2>; +- }; +- +- cluster4_l2: l2-cache4 { +- compatible = "cache"; +- cache-size = <0x100000>; +- cache-line-size = <64>; +- cache-sets = <1024>; +- cache-level = <2>; +- }; +- +- cluster5_l2: l2-cache5 { +- compatible = "cache"; +- cache-size = <0x100000>; +- cache-line-size = <64>; +- cache-sets = <1024>; +- cache-level = <2>; +- }; +- +- cluster6_l2: l2-cache6 { +- compatible = "cache"; +- cache-size = <0x100000>; +- cache-line-size = <64>; +- cache-sets = <1024>; +- cache-level = <2>; +- }; +- +- cluster7_l2: l2-cache7 { +- compatible = "cache"; +- cache-size = <0x100000>; +- cache-line-size = <64>; +- cache-sets = <1024>; +- cache-level = <2>; +- }; +- +- cpu_pw15: cpu-pw15 { +- compatible = "arm,idle-state"; +- idle-state-name = "PW15"; +- arm,psci-suspend-param = <0x0>; +- entry-latency-us = <2000>; +- exit-latency-us = <2000>; +- min-residency-us = <6000>; +- }; +- }; +- +- gic: interrupt-controller@6000000 { +- compatible = "arm,gic-v3"; +- reg = <0x0 0x06000000 0 0x10000>, // GIC Dist +- <0x0 0x06200000 0 0x200000>, // GICR (RD_base + +- // SGI_base) +- <0x0 0x0c0c0000 0 0x2000>, // GICC +- <0x0 0x0c0d0000 0 0x1000>, // GICH +- <0x0 0x0c0e0000 0 0x20000>; // GICV +- #interrupt-cells = <3>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- interrupt-controller; +- interrupts = ; +- +- its: gic-its@6020000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- reg = <0x0 0x6020000 0 0x20000>; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,cortex-a72-pmu"; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- memory@80000000 { +- // DRAM space - 1, size : 2 GB DRAM +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0 0x80000000>; +- }; +- +- ddr1: memory-controller@1080000 { +- compatible = "fsl,qoriq-memory-controller"; +- reg = <0x0 0x1080000 0x0 0x1000>; +- interrupts = ; +- little-endian; +- }; +- +- ddr2: memory-controller@1090000 { +- compatible = "fsl,qoriq-memory-controller"; +- reg = <0x0 0x1090000 0x0 0x1000>; +- interrupts = ; +- little-endian; +- }; +- +- // One clock unit-sysclk node which bootloader require during DT fix-up +- sysclk: sysclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; // fixed up by bootloader +- clock-output-names = "sysclk"; +- }; +- +- thermal-zones { +- cluster6-7 { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 0>; +- +- trips { +- cluster6_7_alert: cluster6-7-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cluster6_7_crit: cluster6-7-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cluster6_7_alert>; +- cooling-device = +- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- ddr-cluster5 { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 1>; +- +- trips { +- ddr-cluster5-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- ddr-cluster5-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- wriop { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 2>; +- +- trips { +- wriop-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- wriop-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- dce-qbman-hsio2 { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 3>; +- +- trips { +- dce-qbman-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- dce-qbman-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- ccn-dpaa-tbu { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 4>; +- +- trips { +- ccn-dpaa-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- ccn-dpaa-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cluster4-hsio3 { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 5>; +- +- trips { +- clust4-hsio3-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- clust4-hsio3-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cluster2-3 { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- thermal-sensors = <&tmu 6>; +- +- trips { +- cluster2-3-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cluster2-3-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; +- +- crypto: crypto@8000000 { +- compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; +- fsl,sec-era = <10>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x00 0x8000000 0x100000>; +- reg = <0x00 0x8000000 0x0 0x100000>; +- interrupts = ; +- dma-coherent; +- status = "disabled"; +- +- sec_jr0: jr@10000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x10000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr1: jr@20000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x20000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr2: jr@30000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x30000 0x10000>; +- interrupts = ; +- }; +- +- sec_jr3: jr@40000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x40000 0x10000>; +- interrupts = ; +- }; +- }; +- +- clockgen: clock-controller@1300000 { +- compatible = "fsl,lx2160a-clockgen"; +- reg = <0 0x1300000 0 0xa0000>; +- #clock-cells = <2>; +- clocks = <&sysclk>; +- }; +- +- dcfg: syscon@1e00000 { +- compatible = "fsl,lx2160a-dcfg", "syscon"; +- reg = <0x0 0x1e00000 0x0 0x10000>; +- little-endian; +- }; +- +- isc: syscon@1f70000 { +- compatible = "fsl,lx2160a-isc", "syscon"; +- reg = <0x0 0x1f70000 0x0 0x10000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1f70000 0x10000>; +- +- extirq: interrupt-controller@14 { +- compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq"; +- #interrupt-cells = <2>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x14 4>; +- interrupt-map = +- <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, +- <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, +- <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, +- <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, +- <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, +- <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, +- <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, +- <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, +- <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, +- <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, +- <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, +- <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-map-mask = <0xffffffff 0x0>; +- }; +- }; +- +- tmu: tmu@1f80000 { +- compatible = "fsl,qoriq-tmu"; +- reg = <0x0 0x1f80000 0x0 0x10000>; +- interrupts = ; +- fsl,tmu-range = <0x800000e6 0x8001017d>; +- fsl,tmu-calibration = +- /* Calibration data group 1 */ +- <0x00000000 0x00000035 +- /* Calibration data group 2 */ +- 0x00000001 0x00000154>; +- little-endian; +- #thermal-sensor-cells = <1>; +- }; +- +- i2c0: i2c@2000000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2000000 0x0 0x10000>; +- interrupts = ; +- clock-names = "i2c"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>; +- scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; +- status = "disabled"; +- }; +- +- i2c1: i2c@2010000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2010000 0x0 0x10000>; +- interrupts = ; +- clock-names = "i2c"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>; +- status = "disabled"; +- }; +- +- i2c2: i2c@2020000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2020000 0x0 0x10000>; +- interrupts = ; +- clock-names = "i2c"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>; +- status = "disabled"; +- }; +- +- i2c3: i2c@2030000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2030000 0x0 0x10000>; +- interrupts = ; +- clock-names = "i2c"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>; +- status = "disabled"; +- }; +- +- i2c4: i2c@2040000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2040000 0x0 0x10000>; +- interrupts = ; +- clock-names = "i2c"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>; +- scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; +- status = "disabled"; +- }; +- +- i2c5: i2c@2050000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2050000 0x0 0x10000>; +- interrupts = ; +- clock-names = "i2c"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>; +- status = "disabled"; +- }; +- +- i2c6: i2c@2060000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2060000 0x0 0x10000>; +- interrupts = ; +- clock-names = "i2c"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>; +- status = "disabled"; +- }; +- +- i2c7: i2c@2070000 { +- compatible = "fsl,vf610-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2070000 0x0 0x10000>; +- interrupts = ; +- clock-names = "i2c"; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(16)>; +- status = "disabled"; +- }; +- +- fspi: spi@20c0000 { +- compatible = "nxp,lx2160a-fspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x20c0000 0x0 0x10000>, +- <0x0 0x20000000 0x0 0x10000000>; +- reg-names = "fspi_base", "fspi_mmap"; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>, +- <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- clock-names = "fspi_en", "fspi"; +- status = "disabled"; +- }; +- +- dspi0: spi@2100000 { +- compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2100000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(8)>; +- clock-names = "dspi"; +- spi-num-chipselects = <5>; +- bus-num = <0>; +- status = "disabled"; +- }; +- +- dspi1: spi@2110000 { +- compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2110000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(8)>; +- clock-names = "dspi"; +- spi-num-chipselects = <5>; +- bus-num = <1>; +- status = "disabled"; +- }; +- +- dspi2: spi@2120000 { +- compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x2120000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(8)>; +- clock-names = "dspi"; +- spi-num-chipselects = <5>; +- bus-num = <2>; +- status = "disabled"; +- }; +- +- esdhc0: esdhc@2140000 { +- compatible = "fsl,esdhc"; +- reg = <0x0 0x2140000 0x0 0x10000>; +- interrupts = <0 28 0x4>; /* Level high type */ +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- dma-coherent; +- voltage-ranges = <1800 1800 3300 3300>; +- sdhci,auto-cmd12; +- little-endian; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- esdhc1: esdhc@2150000 { +- compatible = "fsl,esdhc"; +- reg = <0x0 0x2150000 0x0 0x10000>; +- interrupts = <0 63 0x4>; /* Level high type */ +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- dma-coherent; +- voltage-ranges = <1800 1800 3300 3300>; +- sdhci,auto-cmd12; +- broken-cd; +- little-endian; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- can0: can@2180000 { +- compatible = "fsl,lx2160ar1-flexcan"; +- reg = <0x0 0x2180000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(8)>, +- <&clockgen QORIQ_CLK_SYSCLK 0>; +- clock-names = "ipg", "per"; +- fsl,clk-source = <0>; +- status = "disabled"; +- }; +- +- can1: can@2190000 { +- compatible = "fsl,lx2160ar1-flexcan"; +- reg = <0x0 0x2190000 0x0 0x10000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(8)>, +- <&clockgen QORIQ_CLK_SYSCLK 0>; +- clock-names = "ipg", "per"; +- fsl,clk-source = <0>; +- status = "disabled"; +- }; +- +- uart0: serial@21c0000 { +- compatible = "arm,sbsa-uart","arm,pl011"; +- reg = <0x0 0x21c0000 0x0 0x1000>; +- interrupts = ; +- current-speed = <115200>; +- status = "disabled"; +- }; +- +- uart1: serial@21d0000 { +- compatible = "arm,sbsa-uart","arm,pl011"; +- reg = <0x0 0x21d0000 0x0 0x1000>; +- interrupts = ; +- current-speed = <115200>; +- status = "disabled"; +- }; +- +- uart2: serial@21e0000 { +- compatible = "arm,sbsa-uart","arm,pl011"; +- reg = <0x0 0x21e0000 0x0 0x1000>; +- interrupts = ; +- current-speed = <115200>; +- status = "disabled"; +- }; +- +- uart3: serial@21f0000 { +- compatible = "arm,sbsa-uart","arm,pl011"; +- reg = <0x0 0x21f0000 0x0 0x1000>; +- interrupts = ; +- current-speed = <115200>; +- status = "disabled"; +- }; +- +- gpio0: gpio@2300000 { +- compatible = "fsl,qoriq-gpio"; +- reg = <0x0 0x2300000 0x0 0x10000>; +- interrupts = ; +- gpio-controller; +- little-endian; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio@2310000 { +- compatible = "fsl,qoriq-gpio"; +- reg = <0x0 0x2310000 0x0 0x10000>; +- interrupts = ; +- gpio-controller; +- little-endian; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@2320000 { +- compatible = "fsl,qoriq-gpio"; +- reg = <0x0 0x2320000 0x0 0x10000>; +- interrupts = ; +- gpio-controller; +- little-endian; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio@2330000 { +- compatible = "fsl,qoriq-gpio"; +- reg = <0x0 0x2330000 0x0 0x10000>; +- interrupts = ; +- gpio-controller; +- little-endian; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- watchdog@23a0000 { +- compatible = "arm,sbsa-gwdt"; +- reg = <0x0 0x23a0000 0 0x1000>, +- <0x0 0x2390000 0 0x1000>; +- interrupts = ; +- timeout-sec = <30>; +- }; +- +- rcpm: power-controller@1e34040 { +- compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+"; +- reg = <0x0 0x1e34040 0x0 0x1c>; +- #fsl,rcpm-wakeup-cells = <7>; +- little-endian; +- }; +- +- ftm_alarm0: timer@2800000 { +- compatible = "fsl,lx2160a-ftm-alarm"; +- reg = <0x0 0x2800000 0x0 0x10000>; +- fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; +- interrupts = ; +- }; +- +- usb0: usb@3100000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0x3100000 0x0 0x10000>; +- interrupts = ; +- dr_mode = "host"; +- snps,quirk-frame-length-adjustment = <0x20>; +- snps,dis_rxdet_inp3_quirk; +- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; +- status = "disabled"; +- }; +- +- usb1: usb@3110000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0x3110000 0x0 0x10000>; +- interrupts = ; +- dr_mode = "host"; +- snps,quirk-frame-length-adjustment = <0x20>; +- snps,dis_rxdet_inp3_quirk; +- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; +- status = "disabled"; +- }; +- +- sata0: sata@3200000 { +- compatible = "fsl,lx2160a-ahci"; +- reg = <0x0 0x3200000 0x0 0x10000>, +- <0x7 0x100520 0x0 0x4>; +- reg-names = "ahci", "sata-ecc"; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- dma-coherent; +- status = "disabled"; +- }; +- +- sata1: sata@3210000 { +- compatible = "fsl,lx2160a-ahci"; +- reg = <0x0 0x3210000 0x0 0x10000>, +- <0x7 0x100520 0x0 0x4>; +- reg-names = "ahci", "sata-ecc"; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- dma-coherent; +- status = "disabled"; +- }; +- +- sata2: sata@3220000 { +- compatible = "fsl,lx2160a-ahci"; +- reg = <0x0 0x3220000 0x0 0x10000>, +- <0x7 0x100520 0x0 0x4>; +- reg-names = "ahci", "sata-ecc"; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- dma-coherent; +- status = "disabled"; +- }; +- +- sata3: sata@3230000 { +- compatible = "fsl,lx2160a-ahci"; +- reg = <0x0 0x3230000 0x0 0x10000>, +- <0x7 0x100520 0x0 0x4>; +- reg-names = "ahci", "sata-ecc"; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(4)>; +- dma-coherent; +- status = "disabled"; +- }; +- +- pcie1: pcie@3400000 { +- compatible = "fsl,lx2160a-pcie"; +- reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ +- <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "csr_axi_slave", "config_axi_slave"; +- interrupts = , /* AER interrupt */ +- , /* PME interrupt */ +- ; /* controller interrupt */ +- interrupt-names = "aer", "pme", "intr"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- apio-wins = <8>; +- ppio-wins = <8>; +- bus-range = <0x0 0xff>; +- ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&its>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; +- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ +- status = "disabled"; +- }; +- +- pcie2: pcie@3500000 { +- compatible = "fsl,lx2160a-pcie"; +- reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ +- <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "csr_axi_slave", "config_axi_slave"; +- interrupts = , /* AER interrupt */ +- , /* PME interrupt */ +- ; /* controller interrupt */ +- interrupt-names = "aer", "pme", "intr"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- apio-wins = <8>; +- ppio-wins = <8>; +- bus-range = <0x0 0xff>; +- ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&its>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; +- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ +- status = "disabled"; +- }; +- +- pcie3: pcie@3600000 { +- compatible = "fsl,lx2160a-pcie"; +- reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ +- <0x90 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "csr_axi_slave", "config_axi_slave"; +- interrupts = , /* AER interrupt */ +- , /* PME interrupt */ +- ; /* controller interrupt */ +- interrupt-names = "aer", "pme", "intr"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- apio-wins = <256>; +- ppio-wins = <24>; +- bus-range = <0x0 0xff>; +- ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&its>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; +- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ +- status = "disabled"; +- }; +- +- pcie4: pcie@3700000 { +- compatible = "fsl,lx2160a-pcie"; +- reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ +- <0x98 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "csr_axi_slave", "config_axi_slave"; +- interrupts = , /* AER interrupt */ +- , /* PME interrupt */ +- ; /* controller interrupt */ +- interrupt-names = "aer", "pme", "intr"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- apio-wins = <8>; +- ppio-wins = <8>; +- bus-range = <0x0 0xff>; +- ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&its>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; +- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ +- status = "disabled"; +- }; +- +- pcie5: pcie@3800000 { +- compatible = "fsl,lx2160a-pcie"; +- reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */ +- <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "csr_axi_slave", "config_axi_slave"; +- interrupts = , /* AER interrupt */ +- , /* PME interrupt */ +- ; /* controller interrupt */ +- interrupt-names = "aer", "pme", "intr"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- apio-wins = <256>; +- ppio-wins = <24>; +- bus-range = <0x0 0xff>; +- ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&its>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; +- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ +- status = "disabled"; +- }; +- +- pcie6: pcie@3900000 { +- compatible = "fsl,lx2160a-pcie"; +- reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */ +- <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ +- reg-names = "csr_axi_slave", "config_axi_slave"; +- interrupts = , /* AER interrupt */ +- , /* PME interrupt */ +- ; /* controller interrupt */ +- interrupt-names = "aer", "pme", "intr"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- apio-wins = <8>; +- ppio-wins = <8>; +- bus-range = <0x0 0xff>; +- ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&its>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, +- <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; +- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ +- status = "disabled"; +- }; +- +- smmu: iommu@5000000 { +- compatible = "arm,mmu-500"; +- reg = <0 0x5000000 0 0x800000>; +- #iommu-cells = <1>; +- #global-interrupts = <14>; +- // global secure fault +- interrupts = , +- // combined secure +- , +- // global non-secure fault +- , +- // combined non-secure +- , +- // performance counter interrupts 0-9 +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- // per context interrupt, 64 interrupts +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- dma-coherent; +- }; +- +- console@8340020 { +- compatible = "fsl,dpaa2-console"; +- reg = <0x00000000 0x08340020 0 0x2>; +- }; +- +- ptp-timer@8b95000 { +- compatible = "fsl,dpaa2-ptp"; +- reg = <0x0 0x8b95000 0x0 0x100>; +- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL +- QORIQ_CLK_PLL_DIV(2)>; +- little-endian; +- fsl,extts-fifo; +- }; +- +- /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ +- emdio1: mdio@8b96000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8b96000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- little-endian; +- status = "disabled"; +- }; +- +- emdio2: mdio@8b97000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8b97000 0x0 0x1000>; +- interrupts = ; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pcs_mdio1: mdio@8c07000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c07000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs1: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio2: mdio@8c0b000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c0b000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs2: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio3: mdio@8c0f000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c0f000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs3: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio4: mdio@8c13000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c13000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs4: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio5: mdio@8c17000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c17000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs5: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio6: mdio@8c1b000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c1b000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs6: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio7: mdio@8c1f000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c1f000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs7: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio8: mdio@8c23000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c23000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs8: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio9: mdio@8c27000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c27000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs9: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio10: mdio@8c2b000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c2b000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs10: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio11: mdio@8c2f000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c2f000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs11: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio12: mdio@8c33000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c33000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs12: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio13: mdio@8c37000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c37000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs13: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio14: mdio@8c3b000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c3b000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs14: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio15: mdio@8c3f000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c3f000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs15: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio16: mdio@8c43000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c43000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs16: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio17: mdio@8c47000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c47000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs17: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- pcs_mdio18: mdio@8c4b000 { +- compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8c4b000 0x0 0x1000>; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- pcs18: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- fsl_mc: fsl-mc@80c000000 { +- compatible = "fsl,qoriq-mc"; +- reg = <0x00000008 0x0c000000 0 0x40>, +- <0x00000000 0x08340000 0 0x40000>; +- msi-parent = <&its>; +- /* iommu-map property is fixed up by u-boot */ +- iommu-map = <0 &smmu 0 0>; +- dma-coherent; +- #address-cells = <3>; +- #size-cells = <1>; +- +- /* +- * Region type 0x0 - MC portals +- * Region type 0x1 - QBMAN portals +- */ +- ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 +- 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; +- +- /* +- * Define the maximum number of MACs present on the SoC. +- */ +- dpmacs { +- #address-cells = <1>; +- #size-cells = <0>; +- +- dpmac1: ethernet@1 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x1>; +- pcs-handle = <&pcs1>; +- }; +- +- dpmac2: ethernet@2 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x2>; +- pcs-handle = <&pcs2>; +- }; +- +- dpmac3: ethernet@3 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x3>; +- pcs-handle = <&pcs3>; +- }; +- +- dpmac4: ethernet@4 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x4>; +- pcs-handle = <&pcs4>; +- }; +- +- dpmac5: ethernet@5 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x5>; +- pcs-handle = <&pcs5>; +- }; +- +- dpmac6: ethernet@6 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x6>; +- pcs-handle = <&pcs6>; +- }; +- +- dpmac7: ethernet@7 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x7>; +- pcs-handle = <&pcs7>; +- }; +- +- dpmac8: ethernet@8 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x8>; +- pcs-handle = <&pcs8>; +- }; +- +- dpmac9: ethernet@9 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x9>; +- pcs-handle = <&pcs9>; +- }; +- +- dpmac10: ethernet@a { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0xa>; +- pcs-handle = <&pcs10>; +- }; +- +- dpmac11: ethernet@b { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0xb>; +- pcs-handle = <&pcs11>; +- }; +- +- dpmac12: ethernet@c { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0xc>; +- pcs-handle = <&pcs12>; +- }; +- +- dpmac13: ethernet@d { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0xd>; +- pcs-handle = <&pcs13>; +- }; +- +- dpmac14: ethernet@e { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0xe>; +- pcs-handle = <&pcs14>; +- }; +- +- dpmac15: ethernet@f { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0xf>; +- pcs-handle = <&pcs15>; +- }; +- +- dpmac16: ethernet@10 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x10>; +- pcs-handle = <&pcs16>; +- }; +- +- dpmac17: ethernet@11 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x11>; +- pcs-handle = <&pcs17>; +- }; +- +- dpmac18: ethernet@12 { +- compatible = "fsl,qoriq-mc-dpmac"; +- reg = <0x12>; +- pcs-handle = <&pcs18>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2162a-qds.dts b/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2162a-qds.dts +deleted file mode 100644 +index e1defee1ad27..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2162a-qds.dts ++++ /dev/null +@@ -1,336 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-// +-// Device Tree file for LX2162AQDS +-// +-// Copyright 2020 NXP +- +-/dts-v1/; +- +-#include "fsl-lx2160a.dtsi" +- +-/ { +- model = "NXP Layerscape LX2162AQDS"; +- compatible = "fsl,lx2162a-qds", "fsl,lx2160a"; +- +- aliases { +- crypto = &crypto; +- mmc0 = &esdhc0; +- mmc1 = &esdhc1; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- sb_3v3: regulator-sb3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "LTM4619-3.3VSB"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- mdio-mux-1 { +- compatible = "mdio-mux-multiplexer"; +- mux-controls = <&mux 0>; +- mdio-parent-bus = <&emdio1>; +- #address-cells=<1>; +- #size-cells = <0>; +- +- mdio@0 { /* On-board RTL8211F PHY #1 RGMII1 */ +- reg = <0x00>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rgmii_phy1: ethernet-phy@1 { +- compatible = "ethernet-phy-id001c.c916"; +- reg = <0x1>; +- eee-broken-1000t; +- }; +- }; +- +- mdio@8 { /* On-board RTL8211F PHY #2 RGMII2 */ +- reg = <0x8>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rgmii_phy2: ethernet-phy@2 { +- compatible = "ethernet-phy-id001c.c916"; +- reg = <0x2>; +- eee-broken-1000t; +- }; +- }; +- +- mdio@18 { /* Slot #1 */ +- reg = <0x18>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mdio@19 { /* Slot #2 */ +- reg = <0x19>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mdio@1a { /* Slot #3 */ +- reg = <0x1a>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mdio@1b { /* Slot #4 */ +- reg = <0x1b>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mdio@1c { /* Slot #5 */ +- reg = <0x1c>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mdio@1d { /* Slot #6 */ +- reg = <0x1d>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mdio@1e { /* Slot #7 */ +- reg = <0x1e>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mdio@1f { /* Slot #8 */ +- reg = <0x1f>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- mdio-mux-2 { +- compatible = "mdio-mux-multiplexer"; +- mux-controls = <&mux 1>; +- mdio-parent-bus = <&emdio2>; +- #address-cells=<1>; +- #size-cells = <0>; +- +- mdio@0 { /* Slot #1 (secondary EMI) */ +- reg = <0x00>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mdio@1 { /* Slot #2 (secondary EMI) */ +- reg = <0x01>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mdio@2 { /* Slot #3 (secondary EMI) */ +- reg = <0x02>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mdio@3 { /* Slot #4 (secondary EMI) */ +- reg = <0x03>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mdio@4 { /* Slot #5 (secondary EMI) */ +- reg = <0x04>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mdio@5 { /* Slot #6 (secondary EMI) */ +- reg = <0x05>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mdio@6 { /* Slot #7 (secondary EMI) */ +- reg = <0x06>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mdio@7 { /* Slot #8 (secondary EMI) */ +- reg = <0x07>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +-}; +- +-&crypto { +- status = "okay"; +-}; +- +-&dpmac17 { +- phy-handle = <&rgmii_phy1>; +- phy-connection-type = "rgmii-id"; +-}; +- +-&dpmac18 { +- phy-handle = <&rgmii_phy2>; +- phy-connection-type = "rgmii-id"; +-}; +- +-&dspi0 { +- status = "okay"; +- +- dflash0: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +-}; +- +-&dspi1 { +- status = "okay"; +- +- dflash1: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +-}; +- +-&dspi2 { +- status = "okay"; +- +- dflash2: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +-}; +- +-&emdio1 { +- status = "okay"; +-}; +- +-&emdio2 { +- status = "okay"; +-}; +- +-&esdhc0 { +- status = "okay"; +-}; +- +-&esdhc1 { +- status = "okay"; +-}; +- +-&fspi { +- status = "okay"; +- +- mt35xu512aba0: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- m25p,fast-read; +- spi-max-frequency = <50000000>; +- reg = <0>; +- spi-rx-bus-width = <8>; +- spi-tx-bus-width = <8>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- fpga@66 { +- compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c", +- "simple-mfd"; +- reg = <0x66>; +- +- mux: mux-controller { +- compatible = "reg-mux"; +- #mux-control-cells = <1>; +- mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ +- <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */ +- }; +- }; +- +- i2c-mux@77 { +- compatible = "nxp,pca9547"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; +- +- power-monitor@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <500>; +- }; +- +- power-monitor@41 { +- compatible = "ti,ina220"; +- reg = <0x41>; +- shunt-resistor = <1000>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3>; +- +- temperature-sensor@4c { +- compatible = "nxp,sa56004"; +- reg = <0x4c>; +- vcc-supply = <&sb_3v3>; +- }; +- +- rtc@51 { +- compatible = "nxp,pcf2129"; +- reg = <0x51>; +- }; +- }; +- }; +-}; +- +-&sata0 { +- status = "okay"; +-}; +- +-&sata1 { +- status = "okay"; +-}; +- +-&sata2 { +- status = "okay"; +-}; +- +-&sata3 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-adma.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-adma.dtsi +deleted file mode 100644 +index 9386d1a59e82..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-adma.dtsi ++++ /dev/null +@@ -1,8 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2018-2020 NXP +- * Dong Aisheng +- */ +- +-#include "imx8-ss-audio.dtsi" +-#include "imx8-ss-dma.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-audio.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-audio.dtsi +deleted file mode 100644 +index 6c8d75ef9250..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-audio.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2018-2019 NXP +- * Dong Aisheng +- */ +- +-#include +-#include +- +-audio_subsys: bus@59000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x59000000 0x0 0x59000000 0x1000000>; +- +- audio_ipg_clk: clock-audio-ipg { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <120000000>; +- clock-output-names = "audio_ipg_clk"; +- }; +- +- dsp_lpcg: clock-controller@59580000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x59580000 0x10000>; +- #clock-cells = <1>; +- clocks = <&audio_ipg_clk>, +- <&audio_ipg_clk>, +- <&audio_ipg_clk>; +- clock-indices = , , +- ; +- clock-output-names = "dsp_lpcg_adb_clk", +- "dsp_lpcg_ipg_clk", +- "dsp_lpcg_core_clk"; +- power-domains = <&pd IMX_SC_R_DSP>; +- }; +- +- dsp_ram_lpcg: clock-controller@59590000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x59590000 0x10000>; +- #clock-cells = <1>; +- clocks = <&audio_ipg_clk>; +- clock-indices = ; +- clock-output-names = "dsp_ram_lpcg_ipg_clk"; +- power-domains = <&pd IMX_SC_R_DSP_RAM>; +- }; +- +- dsp: dsp@596e8000 { +- compatible = "fsl,imx8qxp-dsp"; +- reg = <0x596e8000 0x88000>; +- clocks = <&dsp_lpcg IMX_LPCG_CLK_5>, +- <&dsp_ram_lpcg IMX_LPCG_CLK_4>, +- <&dsp_lpcg IMX_LPCG_CLK_7>; +- clock-names = "ipg", "ocram", "core"; +- power-domains = <&pd IMX_SC_R_MU_13A>, +- <&pd IMX_SC_R_MU_13B>, +- <&pd IMX_SC_R_DSP>, +- <&pd IMX_SC_R_DSP_RAM>; +- mbox-names = "txdb0", "txdb1", +- "rxdb0", "rxdb1"; +- mboxes = <&lsio_mu13 2 0>, +- <&lsio_mu13 2 1>, +- <&lsio_mu13 3 0>, +- <&lsio_mu13 3 1>; +- memory-region = <&dsp_reserved>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-conn.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-conn.dtsi +deleted file mode 100644 +index a79f42a9618e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-conn.dtsi ++++ /dev/null +@@ -1,198 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2018-2019 NXP +- * Dong Aisheng +- */ +- +-#include +-#include +- +-conn_subsys: bus@5b000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; +- +- conn_axi_clk: clock-conn-axi { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <333333333>; +- clock-output-names = "conn_axi_clk"; +- }; +- +- conn_ahb_clk: clock-conn-ahb { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <166666666>; +- clock-output-names = "conn_ahb_clk"; +- }; +- +- conn_ipg_clk: clock-conn-ipg { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <83333333>; +- clock-output-names = "conn_ipg_clk"; +- }; +- +- usdhc1: mmc@5b010000 { +- interrupts = ; +- reg = <0x5b010000 0x10000>; +- clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, +- <&sdhc0_lpcg IMX_LPCG_CLK_5>, +- <&sdhc0_lpcg IMX_LPCG_CLK_0>; +- clock-names = "ipg", "per", "ahb"; +- power-domains = <&pd IMX_SC_R_SDHC_0>; +- status = "disabled"; +- }; +- +- usdhc2: mmc@5b020000 { +- interrupts = ; +- reg = <0x5b020000 0x10000>; +- clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>, +- <&sdhc1_lpcg IMX_LPCG_CLK_5>, +- <&sdhc1_lpcg IMX_LPCG_CLK_0>; +- clock-names = "ipg", "per", "ahb"; +- power-domains = <&pd IMX_SC_R_SDHC_1>; +- fsl,tuning-start-tap = <20>; +- fsl,tuning-step= <2>; +- status = "disabled"; +- }; +- +- usdhc3: mmc@5b030000 { +- interrupts = ; +- reg = <0x5b030000 0x10000>; +- clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>, +- <&sdhc2_lpcg IMX_LPCG_CLK_5>, +- <&sdhc2_lpcg IMX_LPCG_CLK_0>; +- clock-names = "ipg", "per", "ahb"; +- power-domains = <&pd IMX_SC_R_SDHC_2>; +- status = "disabled"; +- }; +- +- fec1: ethernet@5b040000 { +- reg = <0x5b040000 0x10000>; +- interrupts = , +- , +- , +- ; +- clocks = <&enet0_lpcg IMX_LPCG_CLK_4>, +- <&enet0_lpcg IMX_LPCG_CLK_2>, +- <&enet0_lpcg IMX_LPCG_CLK_3>, +- <&enet0_lpcg IMX_LPCG_CLK_0>; +- clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; +- assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; +- assigned-clock-rates = <250000000>, <125000000>; +- fsl,num-tx-queues=<3>; +- fsl,num-rx-queues=<3>; +- power-domains = <&pd IMX_SC_R_ENET_0>; +- status = "disabled"; +- }; +- +- fec2: ethernet@5b050000 { +- reg = <0x5b050000 0x10000>; +- interrupts = , +- , +- , +- ; +- clocks = <&enet1_lpcg IMX_LPCG_CLK_4>, +- <&enet1_lpcg IMX_LPCG_CLK_2>, +- <&enet1_lpcg IMX_LPCG_CLK_3>, +- <&enet1_lpcg IMX_LPCG_CLK_0>; +- clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; +- assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>; +- assigned-clock-rates = <250000000>, <125000000>; +- fsl,num-tx-queues=<3>; +- fsl,num-rx-queues=<3>; +- power-domains = <&pd IMX_SC_R_ENET_1>; +- status = "disabled"; +- }; +- +- /* LPCG clocks */ +- sdhc0_lpcg: clock-controller@5b200000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5b200000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>, +- <&conn_ipg_clk>, <&conn_axi_clk>; +- clock-indices = , , +- ; +- clock-output-names = "sdhc0_lpcg_per_clk", +- "sdhc0_lpcg_ipg_clk", +- "sdhc0_lpcg_ahb_clk"; +- power-domains = <&pd IMX_SC_R_SDHC_0>; +- }; +- +- sdhc1_lpcg: clock-controller@5b210000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5b210000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>, +- <&conn_ipg_clk>, <&conn_axi_clk>; +- clock-indices = , , +- ; +- clock-output-names = "sdhc1_lpcg_per_clk", +- "sdhc1_lpcg_ipg_clk", +- "sdhc1_lpcg_ahb_clk"; +- power-domains = <&pd IMX_SC_R_SDHC_1>; +- }; +- +- sdhc2_lpcg: clock-controller@5b220000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5b220000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>, +- <&conn_ipg_clk>, <&conn_axi_clk>; +- clock-indices = , , +- ; +- clock-output-names = "sdhc2_lpcg_per_clk", +- "sdhc2_lpcg_ipg_clk", +- "sdhc2_lpcg_ahb_clk"; +- power-domains = <&pd IMX_SC_R_SDHC_2>; +- }; +- +- enet0_lpcg: clock-controller@5b230000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5b230000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, +- <&conn_axi_clk>, +- <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, +- <&conn_ipg_clk>, +- <&conn_ipg_clk>; +- clock-indices = , , +- , , +- , ; +- clock-output-names = "enet0_lpcg_timer_clk", +- "enet0_lpcg_txc_sampling_clk", +- "enet0_lpcg_ahb_clk", +- "enet0_lpcg_rgmii_txc_clk", +- "enet0_lpcg_ipg_clk", +- "enet0_lpcg_ipg_s_clk"; +- power-domains = <&pd IMX_SC_R_ENET_0>; +- }; +- +- enet1_lpcg: clock-controller@5b240000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5b240000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, +- <&conn_axi_clk>, +- <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>, +- <&conn_ipg_clk>, +- <&conn_ipg_clk>; +- clock-indices = , , +- , , +- , ; +- clock-output-names = "enet1_lpcg_timer_clk", +- "enet1_lpcg_txc_sampling_clk", +- "enet1_lpcg_ahb_clk", +- "enet1_lpcg_rgmii_txc_clk", +- "enet1_lpcg_ipg_clk", +- "enet1_lpcg_ipg_s_clk"; +- power-domains = <&pd IMX_SC_R_ENET_1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-ddr.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-ddr.dtsi +deleted file mode 100644 +index 8b5cad4e2700..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-ddr.dtsi ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2019-2020 NXP +- * Dong Aisheng +- */ +- +-ddr_subsys: bus@5c000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; +- +- ddr-pmu@5c020000 { +- compatible = "fsl,imx8-ddr-pmu"; +- reg = <0x5c020000 0x10000>; +- interrupts = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-dma.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-dma.dtsi +deleted file mode 100644 +index 960a802b8b6e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-dma.dtsi ++++ /dev/null +@@ -1,202 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2018-2019 NXP +- * Dong Aisheng +- */ +- +-#include +-#include +- +-dma_subsys: bus@5a000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; +- +- dma_ipg_clk: clock-dma-ipg { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <120000000>; +- clock-output-names = "dma_ipg_clk"; +- }; +- +- lpuart0: serial@5a060000 { +- reg = <0x5a060000 0x1000>; +- interrupts = ; +- clocks = <&uart0_lpcg IMX_LPCG_CLK_4>, +- <&uart0_lpcg IMX_LPCG_CLK_0>; +- clock-names = "ipg", "baud"; +- power-domains = <&pd IMX_SC_R_UART_0>; +- status = "disabled"; +- }; +- +- lpuart1: serial@5a070000 { +- reg = <0x5a070000 0x1000>; +- interrupts = ; +- clocks = <&uart1_lpcg IMX_LPCG_CLK_4>, +- <&uart1_lpcg IMX_LPCG_CLK_0>; +- clock-names = "ipg", "baud"; +- power-domains = <&pd IMX_SC_R_UART_1>; +- status = "disabled"; +- }; +- +- lpuart2: serial@5a080000 { +- reg = <0x5a080000 0x1000>; +- interrupts = ; +- clocks = <&uart2_lpcg IMX_LPCG_CLK_4>, +- <&uart2_lpcg IMX_LPCG_CLK_0>; +- clock-names = "ipg", "baud"; +- power-domains = <&pd IMX_SC_R_UART_2>; +- status = "disabled"; +- }; +- +- lpuart3: serial@5a090000 { +- reg = <0x5a090000 0x1000>; +- interrupts = ; +- clocks = <&uart3_lpcg IMX_LPCG_CLK_4>, +- <&uart3_lpcg IMX_LPCG_CLK_0>; +- clock-names = "ipg", "baud"; +- power-domains = <&pd IMX_SC_R_UART_3>; +- status = "disabled"; +- }; +- +- uart0_lpcg: clock-controller@5a460000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5a460000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>, +- <&dma_ipg_clk>; +- clock-indices = , ; +- clock-output-names = "uart0_lpcg_baud_clk", +- "uart0_lpcg_ipg_clk"; +- power-domains = <&pd IMX_SC_R_UART_0>; +- }; +- +- uart1_lpcg: clock-controller@5a470000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5a470000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>, +- <&dma_ipg_clk>; +- clock-indices = , ; +- clock-output-names = "uart1_lpcg_baud_clk", +- "uart1_lpcg_ipg_clk"; +- power-domains = <&pd IMX_SC_R_UART_1>; +- }; +- +- uart2_lpcg: clock-controller@5a480000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5a480000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>, +- <&dma_ipg_clk>; +- clock-indices = , ; +- clock-output-names = "uart2_lpcg_baud_clk", +- "uart2_lpcg_ipg_clk"; +- power-domains = <&pd IMX_SC_R_UART_2>; +- }; +- +- uart3_lpcg: clock-controller@5a490000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5a490000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>, +- <&dma_ipg_clk>; +- clock-indices = , ; +- clock-output-names = "uart3_lpcg_baud_clk", +- "uart3_lpcg_ipg_clk"; +- power-domains = <&pd IMX_SC_R_UART_3>; +- }; +- +- i2c0: i2c@5a800000 { +- reg = <0x5a800000 0x4000>; +- interrupts = ; +- clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>; +- clock-names = "per"; +- assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>; +- assigned-clock-rates = <24000000>; +- power-domains = <&pd IMX_SC_R_I2C_0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@5a810000 { +- reg = <0x5a810000 0x4000>; +- interrupts = ; +- clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>; +- clock-names = "per"; +- assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>; +- assigned-clock-rates = <24000000>; +- power-domains = <&pd IMX_SC_R_I2C_1>; +- status = "disabled"; +- }; +- +- i2c2: i2c@5a820000 { +- reg = <0x5a820000 0x4000>; +- interrupts = ; +- clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>; +- clock-names = "per"; +- assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>; +- assigned-clock-rates = <24000000>; +- power-domains = <&pd IMX_SC_R_I2C_2>; +- status = "disabled"; +- }; +- +- i2c3: i2c@5a830000 { +- reg = <0x5a830000 0x4000>; +- interrupts = ; +- clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>; +- clock-names = "per"; +- assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>; +- assigned-clock-rates = <24000000>; +- power-domains = <&pd IMX_SC_R_I2C_3>; +- status = "disabled"; +- }; +- +- i2c0_lpcg: clock-controller@5ac00000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5ac00000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>, +- <&dma_ipg_clk>; +- clock-indices = , ; +- clock-output-names = "i2c0_lpcg_clk", +- "i2c0_lpcg_ipg_clk"; +- power-domains = <&pd IMX_SC_R_I2C_0>; +- }; +- +- i2c1_lpcg: clock-controller@5ac10000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5ac10000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>, +- <&dma_ipg_clk>; +- clock-indices = , ; +- clock-output-names = "i2c1_lpcg_clk", +- "i2c1_lpcg_ipg_clk"; +- power-domains = <&pd IMX_SC_R_I2C_1>; +- }; +- +- i2c2_lpcg: clock-controller@5ac20000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5ac20000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>, +- <&dma_ipg_clk>; +- clock-indices = , ; +- clock-output-names = "i2c2_lpcg_clk", +- "i2c2_lpcg_ipg_clk"; +- power-domains = <&pd IMX_SC_R_I2C_2>; +- }; +- +- i2c3_lpcg: clock-controller@5ac30000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5ac30000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>, +- <&dma_ipg_clk>; +- clock-indices = , ; +- clock-output-names = "i2c3_lpcg_clk", +- "i2c3_lpcg_ipg_clk"; +- power-domains = <&pd IMX_SC_R_I2C_3>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-img.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-img.dtsi +deleted file mode 100644 +index a90654155a88..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-img.dtsi ++++ /dev/null +@@ -1,80 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2019-2021 NXP +- * Zhou Guoniu +- */ +-img_subsys: bus@58000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x58000000 0x0 0x58000000 0x1000000>; +- +- img_ipg_clk: clock-img-ipg { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <200000000>; +- clock-output-names = "img_ipg_clk"; +- }; +- +- jpegdec: jpegdec@58400000 { +- reg = <0x58400000 0x00050000>; +- interrupts = , +- , +- , +- ; +- clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>, +- <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>; +- clock-names = "per", "ipg"; +- assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>, +- <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>; +- assigned-clock-rates = <200000000>, <200000000>; +- power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>, +- <&pd IMX_SC_R_MJPEG_DEC_S0>, +- <&pd IMX_SC_R_MJPEG_DEC_S1>, +- <&pd IMX_SC_R_MJPEG_DEC_S2>, +- <&pd IMX_SC_R_MJPEG_DEC_S3>; +- }; +- +- jpegenc: jpegenc@58450000 { +- reg = <0x58450000 0x00050000>; +- interrupts = , +- , +- , +- ; +- clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>, +- <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>; +- clock-names = "per", "ipg"; +- assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>, +- <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>; +- assigned-clock-rates = <200000000>, <200000000>; +- power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>, +- <&pd IMX_SC_R_MJPEG_ENC_S0>, +- <&pd IMX_SC_R_MJPEG_ENC_S1>, +- <&pd IMX_SC_R_MJPEG_ENC_S2>, +- <&pd IMX_SC_R_MJPEG_ENC_S3>; +- }; +- +- img_jpeg_dec_lpcg: clock-controller@585d0000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x585d0000 0x10000>; +- #clock-cells = <1>; +- clocks = <&img_ipg_clk>, <&img_ipg_clk>; +- clock-indices = , +- ; +- clock-output-names = "img_jpeg_dec_lpcg_clk", +- "img_jpeg_dec_lpcg_ipg_clk"; +- power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>; +- }; +- +- img_jpeg_enc_lpcg: clock-controller@585f0000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x585f0000 0x10000>; +- #clock-cells = <1>; +- clocks = <&img_ipg_clk>, <&img_ipg_clk>; +- clock-indices = , +- ; +- clock-output-names = "img_jpeg_enc_lpcg_clk", +- "img_jpeg_enc_lpcg_ipg_clk"; +- power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-lsio.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-lsio.dtsi +deleted file mode 100644 +index ee4e585a9c39..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-lsio.dtsi ++++ /dev/null +@@ -1,311 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2018-2020 NXP +- * Dong Aisheng +- */ +- +-#include +-#include +- +-lsio_subsys: bus@5d000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; +- +- lsio_mem_clk: clock-lsio-mem { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <200000000>; +- clock-output-names = "lsio_mem_clk"; +- }; +- +- lsio_bus_clk: clock-lsio-bus { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- clock-output-names = "lsio_bus_clk"; +- }; +- +- lsio_gpio0: gpio@5d080000 { +- reg = <0x5d080000 0x10000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- power-domains = <&pd IMX_SC_R_GPIO_0>; +- }; +- +- lsio_gpio1: gpio@5d090000 { +- reg = <0x5d090000 0x10000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- power-domains = <&pd IMX_SC_R_GPIO_1>; +- }; +- +- lsio_gpio2: gpio@5d0a0000 { +- reg = <0x5d0a0000 0x10000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- power-domains = <&pd IMX_SC_R_GPIO_2>; +- }; +- +- lsio_gpio3: gpio@5d0b0000 { +- reg = <0x5d0b0000 0x10000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- power-domains = <&pd IMX_SC_R_GPIO_3>; +- }; +- +- lsio_gpio4: gpio@5d0c0000 { +- reg = <0x5d0c0000 0x10000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- power-domains = <&pd IMX_SC_R_GPIO_4>; +- }; +- +- lsio_gpio5: gpio@5d0d0000 { +- reg = <0x5d0d0000 0x10000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- power-domains = <&pd IMX_SC_R_GPIO_5>; +- }; +- +- lsio_gpio6: gpio@5d0e0000 { +- reg = <0x5d0e0000 0x10000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- power-domains = <&pd IMX_SC_R_GPIO_6>; +- }; +- +- lsio_gpio7: gpio@5d0f0000 { +- reg = <0x5d0f0000 0x10000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- power-domains = <&pd IMX_SC_R_GPIO_7>; +- }; +- +- lsio_mu0: mailbox@5d1b0000 { +- reg = <0x5d1b0000 0x10000>; +- interrupts = ; +- #mbox-cells = <2>; +- status = "disabled"; +- }; +- +- lsio_mu1: mailbox@5d1c0000 { +- reg = <0x5d1c0000 0x10000>; +- interrupts = ; +- #mbox-cells = <2>; +- }; +- +- lsio_mu2: mailbox@5d1d0000 { +- reg = <0x5d1d0000 0x10000>; +- interrupts = ; +- #mbox-cells = <2>; +- status = "disabled"; +- }; +- +- lsio_mu3: mailbox@5d1e0000 { +- reg = <0x5d1e0000 0x10000>; +- interrupts = ; +- #mbox-cells = <2>; +- status = "disabled"; +- }; +- +- lsio_mu4: mailbox@5d1f0000 { +- reg = <0x5d1f0000 0x10000>; +- interrupts = ; +- #mbox-cells = <2>; +- status = "disabled"; +- }; +- +- lsio_mu13: mailbox@5d280000 { +- reg = <0x5d280000 0x10000>; +- interrupts = ; +- #mbox-cells = <2>; +- power-domains = <&pd IMX_SC_R_MU_13A>; +- }; +- +- /* LPCG clocks */ +- pwm0_lpcg: clock-controller@5d400000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5d400000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, +- <&lsio_bus_clk>, +- <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; +- clock-indices = , , +- , , +- ; +- clock-output-names = "pwm0_lpcg_ipg_clk", +- "pwm0_lpcg_ipg_hf_clk", +- "pwm0_lpcg_ipg_s_clk", +- "pwm0_lpcg_ipg_slv_clk", +- "pwm0_lpcg_ipg_mstr_clk"; +- power-domains = <&pd IMX_SC_R_PWM_0>; +- }; +- +- pwm1_lpcg: clock-controller@5d410000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5d410000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, +- <&lsio_bus_clk>, +- <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; +- clock-indices = , , +- , , +- ; +- clock-output-names = "pwm1_lpcg_ipg_clk", +- "pwm1_lpcg_ipg_hf_clk", +- "pwm1_lpcg_ipg_s_clk", +- "pwm1_lpcg_ipg_slv_clk", +- "pwm1_lpcg_ipg_mstr_clk"; +- power-domains = <&pd IMX_SC_R_PWM_1>; +- }; +- +- pwm2_lpcg: clock-controller@5d420000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5d420000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, +- <&lsio_bus_clk>, +- <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; +- clock-indices = , , +- , , +- ; +- clock-output-names = "pwm2_lpcg_ipg_clk", +- "pwm2_lpcg_ipg_hf_clk", +- "pwm2_lpcg_ipg_s_clk", +- "pwm2_lpcg_ipg_slv_clk", +- "pwm2_lpcg_ipg_mstr_clk"; +- power-domains = <&pd IMX_SC_R_PWM_2>; +- }; +- +- pwm3_lpcg: clock-controller@5d430000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5d430000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, +- <&lsio_bus_clk>, +- <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; +- clock-indices = , , +- , , +- ; +- clock-output-names = "pwm3_lpcg_ipg_clk", +- "pwm3_lpcg_ipg_hf_clk", +- "pwm3_lpcg_ipg_s_clk", +- "pwm3_lpcg_ipg_slv_clk", +- "pwm3_lpcg_ipg_mstr_clk"; +- power-domains = <&pd IMX_SC_R_PWM_3>; +- }; +- +- pwm4_lpcg: clock-controller@5d440000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5d440000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, +- <&lsio_bus_clk>, +- <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>; +- clock-indices = , , +- , , +- ; +- clock-output-names = "pwm4_lpcg_ipg_clk", +- "pwm4_lpcg_ipg_hf_clk", +- "pwm4_lpcg_ipg_s_clk", +- "pwm4_lpcg_ipg_slv_clk", +- "pwm4_lpcg_ipg_mstr_clk"; +- power-domains = <&pd IMX_SC_R_PWM_4>; +- }; +- +- pwm5_lpcg: clock-controller@5d450000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5d450000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, +- <&lsio_bus_clk>, +- <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>; +- clock-indices = , , +- , , +- ; +- clock-output-names = "pwm5_lpcg_ipg_clk", +- "pwm5_lpcg_ipg_hf_clk", +- "pwm5_lpcg_ipg_s_clk", +- "pwm5_lpcg_ipg_slv_clk", +- "pwm5_lpcg_ipg_mstr_clk"; +- power-domains = <&pd IMX_SC_R_PWM_5>; +- }; +- +- pwm6_lpcg: clock-controller@5d460000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5d460000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, +- <&lsio_bus_clk>, +- <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>; +- clock-indices = , , +- , , +- ; +- clock-output-names = "pwm6_lpcg_ipg_clk", +- "pwm6_lpcg_ipg_hf_clk", +- "pwm6_lpcg_ipg_s_clk", +- "pwm6_lpcg_ipg_slv_clk", +- "pwm6_lpcg_ipg_mstr_clk"; +- power-domains = <&pd IMX_SC_R_PWM_6>; +- }; +- +- pwm7_lpcg: clock-controller@5d470000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5d470000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, +- <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, +- <&lsio_bus_clk>, +- <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>; +- clock-indices = , , +- , , +- ; +- clock-output-names = "pwm7_lpcg_ipg_clk", +- "pwm7_lpcg_ipg_hf_clk", +- "pwm7_lpcg_ipg_s_clk", +- "pwm7_lpcg_ipg_slv_clk", +- "pwm7_lpcg_ipg_mstr_clk"; +- power-domains = <&pd IMX_SC_R_PWM_7>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-beacon-baseboard.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-beacon-baseboard.dtsi +deleted file mode 100644 +index 6f5e63696ec0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-beacon-baseboard.dtsi ++++ /dev/null +@@ -1,284 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2020 Compass Electronics Group, LLC +- */ +- +-/ { +- leds { +- compatible = "gpio-leds"; +- +- led0 { +- label = "gen_led0"; +- gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led1 { +- label = "gen_led1"; +- gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led2 { +- label = "gen_led2"; +- gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led3>; +- label = "heartbeat"; +- gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- reg_audio: regulator-audio { +- compatible = "regulator-fixed"; +- regulator-name = "3v3_aud"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usdhc2_vmmc: regulator-usdhc2 { +- compatible = "regulator-fixed"; +- regulator-name = "VSD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sound { +- compatible = "fsl,imx-audio-wm8962"; +- model = "wm8962-audio"; +- audio-cpu = <&sai3>; +- audio-codec = <&wm8962>; +- audio-routing = +- "Headphone Jack", "HPOUTL", +- "Headphone Jack", "HPOUTR", +- "Ext Spk", "SPKOUTL", +- "Ext Spk", "SPKOUTR", +- "AMIC", "MICBIAS", +- "IN3R", "AMIC"; +- }; +-}; +- +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_espi2>; +- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- eeprom@0 { +- compatible = "microchip,at25160bn", "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <5000000>; +- spi-cpha; +- spi-cpol; +- pagesize = <32>; +- size = <2048>; +- address-width = <16>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c4 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +- +- wm8962: audio-codec@1a { +- compatible = "wlf,wm8962"; +- reg = <0x1a>; +- clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; +- DCVDD-supply = <®_audio>; +- DBVDD-supply = <®_audio>; +- AVDD-supply = <®_audio>; +- CPVDD-supply = <®_audio>; +- MICVDD-supply = <®_audio>; +- PLLVDD-supply = <®_audio>; +- SPKVDD1-supply = <®_audio>; +- SPKVDD2-supply = <®_audio>; +- gpio-cfg = < +- 0x0000 /* 0:Default */ +- 0x0000 /* 1:Default */ +- 0x0000 /* 2:FN_DMICCLK */ +- 0x0000 /* 3:Default */ +- 0x0000 /* 4:FN_DMICCDAT */ +- 0x0000 /* 5:Default */ +- >; +- }; +- +- pca6416_0: gpio@20 { +- compatible = "nxp,pcal6416"; +- reg = <0x20>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcal6414>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gpio4>; +- interrupts = <27 IRQ_TYPE_LEVEL_LOW>; +- }; +- +- pca6416_1: gpio@21 { +- compatible = "nxp,pcal6416"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gpio4>; +- interrupts = <27 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&sai3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai3>; +- assigned-clocks = <&clk IMX8MM_CLK_SAI3>; +- assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; +- assigned-clock-rates = <24576000>; +- fsl,sai-mclk-direction-output; +- status = "okay"; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +- +-&uart2 { /* console */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- assigned-clocks = <&clk IMX8MM_CLK_UART3>; +- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>; +- bus-width = <4>; +- vmmc-supply = <®_usdhc2_vmmc>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_espi2: espi2grp { +- fsl,pins = < +- MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 +- MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 +- MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 +- MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_led3: led3grp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41 +- >; +- }; +- +- pinctrl_pcal6414: pcal6414-gpiogrp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 +- >; +- }; +- +- pinctrl_sai3: sai3grp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 +- MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 +- MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 +- MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 +- MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 +- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 +- MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 +- >; +- }; +- +- pinctrl_usdhc2_gpio: usdhc2gpiogrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 +- MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 +- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 +- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 +- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-beacon-kit.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-beacon-kit.dts +deleted file mode 100644 +index 74a7b0cc10c2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-beacon-kit.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2020 Compass Electronics Group, LLC +- */ +- +-/dts-v1/; +- +-#include "imx8mm.dtsi" +-#include "imx8mm-beacon-som.dtsi" +-#include "imx8mm-beacon-baseboard.dtsi" +- +-/ { +- model = "Beacon EmbeddedWorks i.MX8M Mini Development Kit"; +- compatible = "beacon,imx8mm-beacon-kit", "fsl,imx8mm"; +- +- chosen { +- stdout-path = &uart2; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-beacon-som.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-beacon-som.dtsi +deleted file mode 100644 +index 40f5e7a3b064..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-beacon-som.dtsi ++++ /dev/null +@@ -1,462 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2020 Compass Electronics Group, LLC +- */ +- +-/ { +- aliases { +- rtc0 = &rtc; +- rtc1 = &snvs_rtc; +- }; +- +- usdhc1_pwrseq: usdhc1_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1_gpio>; +- reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; +- clocks = <&osc_32k>; +- clock-names = "ext_clock"; +- post-power-on-delay-ms = <80>; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x0 0x40000000 0 0x80000000>; +- }; +-}; +- +-&A53_0 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_1 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_2 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_3 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&ddrc { +- operating-points-v2 = <&ddrc_opp_table>; +- +- ddrc_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-25M { +- opp-hz = /bits/ 64 <25000000>; +- }; +- +- opp-100M { +- opp-hz = /bits/ 64 <100000000>; +- }; +- +- opp-750M { +- opp-hz = /bits/ 64 <750000000>; +- }; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +- }; +-}; +- +-&flexspi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexspi>; +- status = "okay"; +- +- flash@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <80000000>; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <4>; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic@4b { +- compatible = "rohm,bd71847"; +- reg = <0x4b>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio1>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- rohm,reset-snvs-powered; +- +- #clock-cells = <0>; +- clocks = <&osc_32k 0>; +- clock-output-names = "clk-32k-out"; +- +- regulators { +- buck1_reg: BUCK1 { +- regulator-name = "buck1"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "buck2"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- rohm,dvs-run-voltage = <1000000>; +- rohm,dvs-idle-voltage = <900000>; +- }; +- +- buck3_reg: BUCK3 { +- // BUCK5 in datasheet +- regulator-name = "buck3"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck4_reg: BUCK4 { +- // BUCK6 in datasheet +- regulator-name = "buck4"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck5_reg: BUCK5 { +- // BUCK7 in datasheet +- regulator-name = "buck5"; +- regulator-min-microvolt = <1605000>; +- regulator-max-microvolt = <1995000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck6_reg: BUCK6 { +- // BUCK8 in datasheet +- regulator-name = "buck6"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1_reg: LDO1 { +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1600000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "ldo2"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "ldo4"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "ldo6"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- eeprom@50 { +- compatible = "microchip,24c64", "atmel,24c64"; +- pagesize = <32>; +- read-only; /* Manufacturing EEPROM programmed at factory */ +- reg = <0x50>; +- }; +- +- rtc: rtc@51 { +- compatible = "nxp,pcf85263"; +- reg = <0x51>; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- assigned-clocks = <&clk IMX8MM_CLK_UART1>; +- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; +- device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; +- clocks = <&osc_32k>; +- max-speed = <4000000>; +- clock-names = "extclk"; +- }; +-}; +- +-&usdhc1 { +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- bus-width = <4>; +- non-removable; +- cap-power-off-card; +- pm-ignore-notify; +- keep-power-in-suspend; +- mmc-pwrseq = <&usdhc1_pwrseq>; +- status = "okay"; +- +- brcmf: bcrmf@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wlan>; +- interrupt-parent = <&gpio2>; +- interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "host-wake"; +- }; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 +- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_flexspi: flexspigrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 +- MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 +- MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 +- MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 +- MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 +- MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 +- >; +- }; +- +- pinctrl_pmic: pmicirqgrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 +- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 +- MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 +- MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 +- MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 +- MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 +- MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 +- MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 +- >; +- }; +- +- pinctrl_usdhc1_gpio: usdhc1gpiogrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 +- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 +- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 +- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 +- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 +- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 +- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 +- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 +- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 +- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 +- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 +- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 +- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 +- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 +- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 +- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 +- >; +- }; +- +- pinctrl_wlan: wlangrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-ddr4-evk.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-ddr4-evk.dts +deleted file mode 100644 +index 6c079c0a3a48..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-ddr4-evk.dts ++++ /dev/null +@@ -1,57 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2020 NXP +- */ +- +-/dts-v1/; +- +-#include "imx8mm-evk.dtsi" +- +-/ { +- model = "FSL i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board"; +- compatible = "fsl,imx8mm-ddr4-evk", "fsl,imx8mm"; +- +- leds { +- pinctrl-0 = <&pinctrl_gpio_led_2>; +- +- status { +- gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- nand-on-flash-bbt; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_gpmi_nand: gpmi-nand { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 +- MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 +- MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00000096 +- MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 +- MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 +- MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 +- MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 +- MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 +- MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 +- MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 +- MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 +- MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 +- MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 +- MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 +- MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 +- MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 +- >; +- }; +- +- pinctrl_gpio_led_2: gpioled2grp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-evk.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-evk.dts +deleted file mode 100644 +index a2b24d4d4e3e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-evk.dts ++++ /dev/null +@@ -1,128 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2019-2020 NXP +- */ +- +-/dts-v1/; +- +-#include +-#include "imx8mm-evk.dtsi" +- +-/ { +- model = "FSL i.MX8MM EVK board"; +- compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; +- +- aliases { +- spi0 = &flexspi; +- }; +-}; +- +-&ddrc { +- operating-points-v2 = <&ddrc_opp_table>; +- +- ddrc_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-25M { +- opp-hz = /bits/ 64 <25000000>; +- }; +- +- opp-100M { +- opp-hz = /bits/ 64 <100000000>; +- }; +- +- opp-750M { +- opp-hz = /bits/ 64 <750000000>; +- }; +- }; +-}; +- +-&flexspi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexspi>; +- status = "okay"; +- +- flash@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <80000000>; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <4>; +- }; +-}; +- +-&usdhc3 { +- assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; +- assigned-clock-rates = <400000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_flexspi: flexspigrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 +- MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 +- MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 +- MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 +- MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 +- MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-evk.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-evk.dtsi +deleted file mode 100644 +index e033d0257b5a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-evk.dtsi ++++ /dev/null +@@ -1,490 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2020 NXP +- */ +- +-/dts-v1/; +- +-#include +-#include "imx8mm.dtsi" +- +-/ { +- chosen { +- stdout-path = &uart2; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x0 0x40000000 0 0x80000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_led>; +- +- status { +- label = "status"; +- gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- reg_usdhc2_vmmc: regulator-usdhc2 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; +- regulator-name = "VSD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ir>; +- linux,autosuspend-period = <125>; +- }; +- +- wm8524: audio-codec { +- #sound-dai-cells = <0>; +- compatible = "wlf,wm8524"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_wlf>; +- wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; +- }; +- +- sound-wm8524 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "wm8524-audio"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,frame-master = <&cpudai>; +- simple-audio-card,bitclock-master = <&cpudai>; +- simple-audio-card,widgets = +- "Line", "Left Line Out Jack", +- "Line", "Right Line Out Jack"; +- simple-audio-card,routing = +- "Left Line Out Jack", "LINEVOUTL", +- "Right Line Out Jack", "LINEVOUTR"; +- +- cpudai: simple-audio-card,cpu { +- sound-dai = <&sai3>; +- dai-tdm-slot-num = <2>; +- dai-tdm-slot-width = <32>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&wm8524>; +- clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; +- }; +- }; +-}; +- +-&A53_0 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_1 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_2 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_3 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic@4b { +- compatible = "rohm,bd71847"; +- reg = <0x4b>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio1>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- rohm,reset-snvs-powered; +- +- #clock-cells = <0>; +- clocks = <&osc_32k 0>; +- clock-output-names = "clk-32k-out"; +- +- regulators { +- buck1_reg: BUCK1 { +- regulator-name = "buck1"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "buck2"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- rohm,dvs-run-voltage = <1000000>; +- rohm,dvs-idle-voltage = <900000>; +- }; +- +- buck3_reg: BUCK3 { +- // BUCK5 in datasheet +- regulator-name = "buck3"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck4_reg: BUCK4 { +- // BUCK6 in datasheet +- regulator-name = "buck4"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck5_reg: BUCK5 { +- // BUCK7 in datasheet +- regulator-name = "buck5"; +- regulator-min-microvolt = <1605000>; +- regulator-max-microvolt = <1995000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck6_reg: BUCK6 { +- // BUCK8 in datasheet +- regulator-name = "buck6"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1_reg: LDO1 { +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1600000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "ldo2"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "ldo4"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "ldo6"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- ptn5110: tcpc@50 { +- compatible = "nxp,ptn5110"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_typec1>; +- reg = <0x50>; +- interrupt-parent = <&gpio2>; +- interrupts = <11 8>; +- status = "okay"; +- +- port { +- typec1_dr_sw: endpoint { +- remote-endpoint = <&usb1_drd_sw>; +- }; +- }; +- +- typec1_con: connector { +- compatible = "usb-c-connector"; +- label = "USB-C"; +- power-role = "dual"; +- data-role = "dual"; +- try-power-role = "sink"; +- source-pdos = ; +- sink-pdos = ; +- op-sink-microwatt = <15000000>; +- self-powered; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- pca6416: gpio@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&sai3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai3>; +- assigned-clocks = <&clk IMX8MM_CLK_SAI3>; +- assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; +- assigned-clock-rates = <24576000>; +- status = "okay"; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +- +-&uart2 { /* console */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usbotg1 { +- dr_mode = "otg"; +- hnp-disable; +- srp-disable; +- adp-disable; +- usb-role-switch; +- disable-over-current; +- samsung,picophy-pre-emp-curr-control = <3>; +- samsung,picophy-dc-vol-level-adjust = <7>; +- status = "okay"; +- +- port { +- usb1_drd_sw: endpoint { +- remote-endpoint = <&typec1_dr_sw>; +- }; +- }; +-}; +- +-&usdhc2 { +- assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +- cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- vmmc-supply = <®_usdhc2_vmmc>; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 +- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 +- >; +- }; +- +- pinctrl_gpio_led: gpioledgrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 +- >; +- }; +- +- pinctrl_ir: irgrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f +- >; +- }; +- +- pinctrl_gpio_wlf: gpiowlfgrp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_pmic: pmicirqgrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 +- >; +- }; +- +- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 +- >; +- }; +- +- pinctrl_sai3: sai3grp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 +- MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 +- MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 +- MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 +- >; +- }; +- +- pinctrl_typec1: typec1grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 +- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 +- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 +- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 +- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-icore-mx8mm-ctouch2.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-icore-mx8mm-ctouch2.dts +deleted file mode 100644 +index 5389d6f2beba..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-icore-mx8mm-ctouch2.dts ++++ /dev/null +@@ -1,97 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 NXP +- * Copyright (c) 2019 Engicam srl +- * Copyright (c) 2020 Amarula Solutions(India) +- */ +- +-/dts-v1/; +-#include "imx8mm.dtsi" +-#include "imx8mm-icore-mx8mm.dtsi" +- +-/ { +- model = "Engicam i.Core MX8M Mini C.TOUCH 2.0"; +- compatible = "engicam,icore-mx8mm-ctouch2", "engicam,icore-mx8mm", +- "fsl,imx8mm"; +- +- chosen { +- stdout-path = &uart2; +- }; +-}; +- +-&fec1 { +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c4 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 +- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_usdhc1_gpio: usdhc1gpiogrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 +- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 +- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 +- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 +- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 +- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 +- >; +- }; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-/* SD */ +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; +- cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; +- max-frequency = <50000000>; +- bus-width = <4>; +- no-1-8-v; +- pm-ignore-notify; +- keep-power-in-suspend; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-icore-mx8mm-edimm2.2.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-icore-mx8mm-edimm2.2.dts +deleted file mode 100644 +index a4a2ada14835..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-icore-mx8mm-edimm2.2.dts ++++ /dev/null +@@ -1,97 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 NXP +- * Copyright (c) 2019 Engicam srl +- * Copyright (c) 2020 Amarula Solutions(India) +- */ +- +-/dts-v1/; +-#include "imx8mm.dtsi" +-#include "imx8mm-icore-mx8mm.dtsi" +- +-/ { +- model = "Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit"; +- compatible = "engicam,icore-mx8mm-edimm2.2", "engicam,icore-mx8mm", +- "fsl,imx8mm"; +- +- chosen { +- stdout-path = &uart2; +- }; +-}; +- +-&fec1 { +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c4 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 +- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_usdhc1_gpio: usdhc1gpiogrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 +- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 +- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 +- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 +- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 +- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 +- >; +- }; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-/* SD */ +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; +- cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; +- max-frequency = <50000000>; +- bus-width = <4>; +- no-1-8-v; +- pm-ignore-notify; +- keep-power-in-suspend; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-icore-mx8mm.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-icore-mx8mm.dtsi +deleted file mode 100644 +index b40148d728ea..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-icore-mx8mm.dtsi ++++ /dev/null +@@ -1,232 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 NXP +- * Copyright (c) 2019 Engicam srl +- * Copyright (c) 2020 Amarula Solutons(India) +- */ +- +-/ { +- compatible = "engicam,icore-mx8mm", "fsl,imx8mm"; +-}; +- +-&A53_0 { +- cpu-supply = <®_buck4>; +-}; +- +-&A53_1 { +- cpu-supply = <®_buck4>; +-}; +- +-&A53_2 { +- cpu-supply = <®_buck4>; +-}; +- +-&A53_3 { +- cpu-supply = <®_buck4>; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy>; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy@3 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <3>; +- reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic@8 { +- compatible = "nxp,pf8121a"; +- reg = <0x08>; +- +- regulators { +- reg_ldo1: ldo1 { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_ldo2: ldo2 { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_ldo3: ldo3 { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_ldo4: ldo4 { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_buck1: buck1 { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_buck2: buck2 { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_buck3: buck3 { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_buck4: buck4 { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_buck5: buck5 { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_buck6: buck6 { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_buck7: buck7 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_vsnvs: vsnvs { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&iomuxc { +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 +- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 +- >; +- }; +-}; +- +-/* eMMC */ +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-kontron-n801x-s.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-kontron-n801x-s.dts +deleted file mode 100644 +index 49d7470812ee..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-kontron-n801x-s.dts ++++ /dev/null +@@ -1,324 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright (C) 2019 Kontron Electronics GmbH +- */ +- +-/dts-v1/; +- +-#include "imx8mm-kontron-n801x-som.dtsi" +- +-/ { +- model = "Kontron i.MX8MM N801X S"; +- compatible = "kontron,imx8mm-n801x-s", "kontron,imx8mm-n801x-som", "fsl,imx8mm"; +- +- aliases { +- ethernet1 = &usbnet; +- }; +- +- /* fixed crystal dedicated to mcp2515 */ +- osc_can: clock-osc-can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <16000000>; +- clock-output-names = "osc-can"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_led>; +- +- led1 { +- label = "led1"; +- gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led2 { +- label = "led2"; +- gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; +- }; +- +- led3 { +- label = "led3"; +- gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; +- }; +- +- led4 { +- label = "led4"; +- gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; +- }; +- +- led5 { +- label = "led5"; +- gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; +- }; +- +- led6 { +- label = "led6"; +- gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- pwm-beeper { +- compatible = "pwm-beeper"; +- pwms = <&pwm2 0 5000 0>; +- }; +- +- reg_rst_eth2: regulator-rst-eth2 { +- compatible = "regulator-fixed"; +- regulator-name = "rst-usb-eth2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_eth2>; +- gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- reg_vdd_5v: regulator-5v { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +-}; +- +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- can0: can@0 { +- compatible = "microchip,mcp2515"; +- reg = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_can>; +- clocks = <&osc_can>; +- interrupt-parent = <&gpio4>; +- interrupts = <28 IRQ_TYPE_EDGE_FALLING>; +- spi-max-frequency = <10000000>; +- vdd-supply = <®_vdd_3v3>; +- xceiver-supply = <®_vdd_5v>; +- }; +-}; +- +-&ecspi3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi3>; +- cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet>; +- phy-connection-type = "rgmii-rxid"; +- phy-handle = <ðphy>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy@0 { +- reg = <0>; +- reset-assert-us = <1>; +- reset-deassert-us = <15000>; +- reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&i2c4 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +- +- rtc@32 { +- compatible = "epson,rx8900"; +- reg = <0x32>; +- }; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- linux,rs485-enabled-at-boot-time; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usbotg1 { +- dr_mode = "otg"; +- over-current-active-low; +- status = "okay"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- disable-over-current; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- usb1@1 { +- compatible = "usb424,9514"; +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- usbnet: usbether@1 { +- compatible = "usb424,ec00"; +- reg = <1>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- }; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- vmmc-supply = <®_vdd_3v3>; +- vqmmc-supply = <®_nvcc_sd>; +- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio>; +- +- pinctrl_can: cangrp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 +- MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 +- MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 +- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 +- >; +- }; +- +- pinctrl_ecspi3: ecspi3grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 +- MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 +- MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 +- MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 +- >; +- }; +- +- pinctrl_enet: enetgrp { +- fsl,pins = < +- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 +- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 /* PHY RST */ +- MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* ETH IRQ */ +- >; +- }; +- +- pinctrl_gpio_led: gpioledgrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 +- MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 +- MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 +- MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 +- MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 +- MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 +- MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 +- >; +- }; +- +- pinctrl_gpio: gpiogrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 +- MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 +- MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 +- MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 +- MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 +- MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 +- MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 +- MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 +- MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 +- MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 +- MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 +- MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 +- MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 +- MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 +- >; +- }; +- +- pinctrl_usb_eth2: usbeth2grp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 +- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-kontron-n801x-som.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-kontron-n801x-som.dtsi +deleted file mode 100644 +index 42bbbb3f532b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-kontron-n801x-som.dtsi ++++ /dev/null +@@ -1,297 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright (C) 2019 Kontron Electronics GmbH +- */ +- +-#include "imx8mm.dtsi" +- +-/ { +- model = "Kontron i.MX8MM N801X SoM"; +- compatible = "kontron,imx8mm-n801x-som", "fsl,imx8mm"; +- +- memory@40000000 { +- device_type = "memory"; +- /* +- * There are multiple SoM flavors with different DDR sizes. +- * The smallest is 1GB. For larger sizes the bootloader will +- * update the reg property. +- */ +- reg = <0x0 0x40000000 0 0x80000000>; +- }; +- +- chosen { +- stdout-path = &uart3; +- }; +-}; +- +-&A53_0 { +- cpu-supply = <®_vdd_arm>; +-}; +- +-&A53_1 { +- cpu-supply = <®_vdd_arm>; +-}; +- +-&A53_2 { +- cpu-supply = <®_vdd_arm>; +-}; +- +-&A53_3 { +- cpu-supply = <®_vdd_arm>; +-}; +- +-&ddrc { +- operating-points-v2 = <&ddrc_opp_table>; +- +- ddrc_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-25M { +- opp-hz = /bits/ 64 <25000000>; +- }; +- +- opp-100M { +- opp-hz = /bits/ 64 <100000000>; +- }; +- +- opp-750M { +- opp-hz = /bits/ 64 <750000000>; +- }; +- }; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- +- spi-flash@0 { +- compatible = "mxicy,mx25r1635f", "jedec,spi-nor"; +- spi-max-frequency = <80000000>; +- reg = <0>; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pca9450: pmic@25 { +- compatible = "nxp,pca9450a"; +- reg = <0x25>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio1>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- +- regulators { +- reg_vdd_soc: BUCK1 { +- regulator-name = "buck1"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <850000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <3125>; +- nxp,dvs-run-voltage = <850000>; +- nxp,dvs-standby-voltage = <800000>; +- }; +- +- reg_vdd_arm: BUCK2 { +- regulator-name = "buck2"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <950000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <3125>; +- nxp,dvs-run-voltage = <950000>; +- nxp,dvs-standby-voltage = <850000>; +- }; +- +- reg_vdd_dram: BUCK3 { +- regulator-name = "buck3"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <950000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_vdd_3v3: BUCK4 { +- regulator-name = "buck4"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_vdd_1v8: BUCK5 { +- regulator-name = "buck5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_nvcc_dram: BUCK6 { +- regulator-name = "buck6"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_nvcc_snvs: LDO1 { +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_vdd_snvs: LDO2 { +- regulator-name = "ldo2"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_vdda: LDO3 { +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_vdd_phy: LDO4 { +- regulator-name = "ldo4"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_nvcc_sd: LDO5 { +- regulator-name = "ldo5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +- }; +-}; +- +-&uart3 { /* console */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- vmmc-supply = <®_vdd_3v3>; +- vqmmc-supply = <®_vdd_1v8>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 +- MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 +- MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 +- MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 +- MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 +- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 +- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 +- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 +- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 +- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 +- MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 +- MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 +- MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 +- MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 +- MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 +- MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 +- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 +- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 +- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 +- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 +- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 +- MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 +- MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 +- MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 +- MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 +- MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 +- MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 +- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 +- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 +- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 +- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 +- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 +- MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 +- MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 +- MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 +- MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 +- MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 +- MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-nitrogen-r2.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-nitrogen-r2.dts +deleted file mode 100644 +index 74c09891600f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-nitrogen-r2.dts ++++ /dev/null +@@ -1,701 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Boundary Devices i.MX8MMini Nitrogen8MM Rev2 board. +- * Adrien Grassein +- */ +-/dts-v1/; +-#include "imx8mm.dtsi" +- +-/ { +- model = "Boundary Devices i.MX8MMini Nitrogen8MM Rev2"; +- compatible = "boundary,imx8mm-nitrogen8mm", "fsl,imx8mm"; +- +- reg_vref_1v8: regulator-vref-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "vref-1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- reg_vref_3v3: regulator-vref-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vref-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_wlan_vmmc: regulator-wlan-vmmc { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_wlan_vmmc>; +- regulator-name = "reg_wlan_vmmc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sound-wm8960 { +- audio-cpu = <&sai1>; +- audio-codec = <&wm8960>; +- audio-routing = +- "Headphone Jack", "HP_L", +- "Headphone Jack", "HP_R", +- "Ext Spk", "SPK_LP", +- "Ext Spk", "SPK_LN", +- "Ext Spk", "SPK_RP", +- "Ext Spk", "SPK_RN", +- "RINPUT1", "Mic Jack", +- "Mic Jack", "MICB"; +- compatible = "fsl,imx-audio-wm8960"; +- /* JD2: hp detect high for headphone*/ +- hp-det-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; +- /* Jack is not stuffed */ +- mic-det-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; +- model = "wm8960-audio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sound_wm8960>; +- }; +-}; +- +-&A53_0 { +- cpu-supply = <®_buck3>; +-}; +- +-&A53_1 { +- cpu-supply = <®_buck3>; +-}; +- +-&A53_2 { +- cpu-supply = <®_buck3>; +-}; +- +-&A53_3 { +- cpu-supply = <®_buck3>; +-}; +- +-/* J15 */ +-&ecspi2 { +- assigned-clocks = <&clk IMX8MM_CLK_ECSPI2>; +- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_40M>; +- assigned-clock-rates = <40000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@4 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <4>; +- interrupts-extended = <&gpio3 16 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +-}; +- +-&flexspi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexspi>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic@8 { +- compatible = "nxp,pf8121a"; +- reg = <0x8>; +- +- regulators { +- reg_ldo1: ldo1 { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_ldo2: ldo2 { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_ldo3: ldo3 { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_ldo4: ldo4 { +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_buck1: buck1 { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_buck2: buck2 { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_buck3: buck3 { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_buck4: buck4 { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_buck5: buck5 { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_buck6: buck6 { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_buck7: buck7 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_vsnvs: vsnvs { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- i2cmux@70 { +- compatible = "nxp,pca9540"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c3@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtc@68 { +- compatible = "microcrystal,rv4162"; +- reg = <0x68>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3a_rv4162>; +- interrupts-extended = <&gpio4 22 IRQ_TYPE_LEVEL_LOW>; +- wakeup-source; +- }; +- }; +- }; +-}; +- +-&i2c4 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +- +- wm8960: codec@1a { +- compatible = "wlf,wm8960"; +- reg = <0x1a>; +- clocks = <&clk IMX8MM_CLK_SAI1_ROOT>; +- clock-names = "mclk1"; +- wlf,shared-lrclk; +- #sound-dai-cells = <0>; +- }; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- +-&pwm2 { +- assigned-clocks = <&clk IMX8MM_CLK_PWM2>; +- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_40M>; +- assigned-clock-rates = <40000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm2>; +- status = "okay"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm3>; +- status = "okay"; +-}; +- +-&pwm4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm4>; +- status = "okay"; +-}; +- +-&sai1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai1>; +- status = "okay"; +-}; +- +-&sai2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai2>; +- status = "okay"; +-}; +- +-/* BT */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-/* console */ +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-/* J15 */ +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-/* J9 */ +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-/* eMMC */ +-&usdhc1 { +- bus-width = <8>; +- sdhci-caps-mask = <0x80000000 0x0>; +- non-removable; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- vmmc-supply = <®_vref_3v3>; +- vqmmc-supply = <®_vref_1v8>; +- status = "okay"; +-}; +- +-/* sdcard */ +-&usdhc2 { +- bus-width = <4>; +- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>; +- vqmmc-supply = <®_ldo2>; +- status = "okay"; +-}; +- +-/* wlan */ +-&usdhc3 { +- bus-width = <4>; +- sdhci-caps-mask = <0x2 0x0>; +- non-removable; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- vmmc-supply = <®_wlan_vmmc>; +- vqmmc-supply = <®_vref_1v8>; +- status = "okay"; +-}; +- +-/* USB OTG port */ +-&usbotg1 { +- dr_mode = "otg"; +- over-current-active-low; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg1>; +- power-active-high; +- status = "okay"; +-}; +- +-/* USB Host port */ +-&usbotg2 { +- dr_mode = "host"; +- over-current-active-low; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbotg2>; +- power-active-high; +- /* +- * FIXME: having USB2 enabled hangs the boot just after: +- *[ 1.655941] ci_hdrc ci_hdrc.1: EHCI Host Controller +- *[ 1.660880] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 2 +- *[ 1.681505] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00 +- *[ 1.687730] hub 2-0:1.0: USB hub found +- *[ 1.691528] hub 2-0:1.0: 1 port detected +- */ +- status = "disabled"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140 +- MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19 +- MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19 +- MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19 +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 +- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x159 +- >; +- }; +- +- pinctrl_flexspi: flexspigrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 +- MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 +- MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 +- MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 +- MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 +- MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 +- >; +- }; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x09 +- MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x09 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c3a_rv4162: i2c3a-rv4162grp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1c0 +- >; +- }; +- +- pinctrl_pwm1: pwm1grp { +- fsl,pins = < +- MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16 +- >; +- }; +- +- pinctrl_pwm2: pwm2grp { +- fsl,pins = < +- MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x16 +- >; +- }; +- +- pinctrl_pwm3: pwm3grp { +- fsl,pins = < +- MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x16 +- >; +- }; +- +- pinctrl_pwm4: pwm4grp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16 +- >; +- }; +- +- pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16 +- >; +- }; +- +- pinctrl_sai1: sai1grp { +- fsl,pins = < +- /* wm8960 */ +- MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 +- MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 +- MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 +- MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 +- MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6 +- >; +- }; +- +- pinctrl_sai2: sai2grp { +- fsl,pins = < +- /* Bluetooth PCM */ +- MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 +- MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 +- MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 +- MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 +- >; +- }; +- +- pinctrl_sound_wm8960: sound-wm8960grp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x80 +- MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x80 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 +- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 +- MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 +- MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 +- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 +- MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 +- MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 +- MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 +- MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_usbotg1: usbotg1grp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x16 +- MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x156 +- >; +- }; +- +- pinctrl_usbotg2: usbotg2grp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x16 +- MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x15 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 +- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 +- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 +- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 +- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 +- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 +- MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 +- MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 +- MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 +- MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 +- MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x141 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 +- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 +- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 +- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 +- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 +- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 +- MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 +- MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 +- MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 +- MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 +- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 +- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 +- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 +- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 +- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 +- MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 +- MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 +- MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 +- MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 +- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 +- MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x03 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-pinfunc.h b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-pinfunc.h +deleted file mode 100644 +index a003e6af3353..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-pinfunc.h ++++ /dev/null +@@ -1,645 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright 2017-2018 NXP +- */ +- +-#ifndef __DTS_IMX8MM_PINFUNC_H +-#define __DTS_IMX8MM_PINFUNC_H +- +-/* +- * The pin function ID is a tuple of +- * +- */ +- +-#define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 +-#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 +-#define MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x0FC 0x364 0x000 0x2 0x0 +-#define MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x000 0x2 0x0 +-#define MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x104 0x36C 0x000 0x2 0x0 +-#define MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x108 0x370 0x000 0x2 0x0 +-#define MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x11C 0x384 0x000 0x2 0x0 +-#define MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x120 0x388 0x000 0x2 0x0 +-#define MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x124 0x38C 0x000 0x2 0x0 +-#define MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x000 0x2 0x0 +-#define MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x130 0x398 0x000 0x2 0x0 +-#define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x138 0x3A0 0x000 0x12 0x0 +-#define MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x13C 0x3A4 0x000 0x2 0x0 +-#define MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 +-#define MX8MM_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 +-#define MX8MM_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0x144 0x3AC 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0x148 0x3B0 0x534 0x4 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0x14C 0x3B4 0x538 0x4 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 +-#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53c 0x4 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2 +-#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0x154 0x3BC 0x540 0x4 0x0 +-#define MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0 +-#define MX8MM_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0 +-#define MX8MM_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0 +-#define MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0 +-#define MX8MM_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1 +-#define MX8MM_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1 +-#define MX8MM_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1 +-#define MX8MM_IOMUXC_SAI1_RXD0_PDM_DATA0 0x164 0x3CC 0x534 0x3 0x1 +-#define MX8MM_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1 +-#define MX8MM_IOMUXC_SAI1_RXD1_PDM_DATA1 0x168 0x3D0 0x538 0x3 0x1 +-#define MX8MM_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1 +-#define MX8MM_IOMUXC_SAI1_RXD2_PDM_DATA2 0x16C 0x3D4 0x53C 0x3 0x1 +-#define MX8MM_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1 +-#define MX8MM_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD3_PDM_DATA3 0x170 0x3D8 0x540 0x3 0x1 +-#define MX8MM_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1 +-#define MX8MM_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4 +-#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3 +-#define MX8MM_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1 +-#define MX8MM_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1 +-#define MX8MM_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1 +-#define MX8MM_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1 +-#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1 +-#define MX8MM_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1 +-#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1 +-#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1 +-#define MX8MM_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1 +-#define MX8MM_IOMUXC_SAI1_TXD7_PDM_CLK 0x1A8 0x410 0x000 0x3 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0 +-#define MX8MM_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1 +-#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2 +-#define MX8MM_IOMUXC_SAI1_MCLK_PDM_CLK 0x1AC 0x414 0x000 0x3 0x0 +-#define MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 +-#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1B0 0x418 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DTE_RX 0x1B0 0x418 0x4F4 0x4 0x2 +-#define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 +-#define MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1B4 0x41C 0x4F4 0x4 0x3 +-#define MX8MM_IOMUXC_SAI2_RXC_UART1_DTE_TX 0x1B4 0x41C 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x1B8 0x420 0x4F0 0x4 0x2 +-#define MX8MM_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 0x1B8 0x420 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x1BC 0x424 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 0x1BC 0x424 0x4F0 0x4 0x3 +-#define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2 +-#define MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 +-#define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 +-#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1D0 0x438 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x1D0 0x438 0x4F8 0x4 0x2 +-#define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 +-#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1D4 0x43C 0x4F8 0x4 0x3 +-#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x1D4 0x43C 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 +-#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4Fc 0x4 0x2 +-#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 +-#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0 +-#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4Fc 0x4 0x3 +-#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2 +-#define MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3 +-#define MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 +-#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 +-#define MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 +-#define MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 +-#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 +-#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 +-#define MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 +-#define MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 +-#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 +-#define MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 +-#define MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 +-#define MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x12 0x0 +-#define MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 +-#define MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 +-#define MX8MM_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0 +-#define MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 +-#define MX8MM_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 +-#define MX8MM_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 +-#define MX8MM_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 +-#define MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 +-#define MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 +-#define MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 +-#define MX8MM_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 +-#define MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1 +-#define MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0 +-#define MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 +-#define MX8MM_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 +-#define MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 +-#define MX8MM_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 +-#define MX8MM_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1 +-#define MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 +-#define MX8MM_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0 +- +-#endif /* __DTS_IMX8MM_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-var-som-symphony.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-var-som-symphony.dts +deleted file mode 100644 +index ac1fe1530ac7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-var-som-symphony.dts ++++ /dev/null +@@ -1,255 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2020 Krzysztof Kozlowski +- */ +- +-/dts-v1/; +- +-#include "imx8mm-var-som.dtsi" +- +-/ { +- model = "Variscite VAR-SOM-MX8MM Symphony evaluation board"; +- compatible = "variscite,var-som-mx8mm-symphony", "variscite,var-som-mx8mm", "fsl,imx8mm"; +- +- reg_usdhc2_vmmc: regulator-usdhc2-vmmc { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; +- regulator-name = "VSD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_otg2_vbus: regulator-usb-otg2-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usb_otg2_vbus>; +- regulator-name = "usb_otg2_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- back { +- label = "Back"; +- gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- home { +- label = "Home"; +- gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- menu { +- label = "Menu"; +- gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led { +- label = "Heartbeat"; +- gpios = <&pca9534 0 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-ðphy { +- reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- pca9534: gpio@20 { +- compatible = "nxp,pca9534"; +- reg = <0x20>; +- gpio-controller; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pca9534>; +- interrupt-parent = <&gpio1>; +- interrupts = <7 IRQ_TYPE_EDGE_FALLING>; +- #gpio-cells = <2>; +- wakeup-source; +- +- /* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */ +- usb3-sata-sel-hog { +- gpio-hog; +- gpios = <4 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "usb3_sata_sel"; +- }; +- +- som-vselect-hog { +- gpio-hog; +- gpios = <6 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "som_vselect"; +- }; +- +- enet-sel-hog { +- gpio-hog; +- gpios = <7 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "enet_sel"; +- }; +- }; +- +- extcon_usbotg1: typec@3d { +- compatible = "nxp,ptn5150"; +- reg = <0x3d>; +- interrupt-parent = <&gpio1>; +- interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ptn5150>; +- status = "okay"; +- }; +-}; +- +-&i2c3 { +- /* Capacitive touch controller */ +- ft5x06_ts: touchscreen@38 { +- compatible = "edt,edt-ft5406"; +- reg = <0x38>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_captouch>; +- interrupt-parent = <&gpio5>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +- +- touchscreen-size-x = <800>; +- touchscreen-size-y = <480>; +- touchscreen-inverted-x; +- touchscreen-inverted-y; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1337"; +- reg = <0x68>; +- }; +-}; +- +-/* Header */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-/* Header */ +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&usbotg1 { +- disable-over-current; +- extcon = <&extcon_usbotg1>, <&extcon_usbotg1>; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- vbus-supply = <®_usb_otg2_vbus>; +- srp-disable; +- hnp-disable; +- adp-disable; +- disable-over-current; +- /delete-property/ usb-role-switch; +- /* +- * FIXME: having USB2 enabled hangs the boot just after: +- * [ 1.943365] ci_hdrc ci_hdrc.1: EHCI Host Controller +- * [ 1.948287] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 1 +- * [ 1.971006] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00 +- * [ 1.977203] hub 1-0:1.0: USB hub found +- * [ 1.980987] hub 1-0:1.0: 1 port detected +- */ +- status = "disabled"; +-}; +- +-&pinctrl_fec1 { +- fsl,pins = < +- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 +- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */ +- >; +-}; +- +-&iomuxc { +- pinctrl_captouch: captouchgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_pca9534: pca9534grp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 +- >; +- }; +- +- pinctrl_ptn5150: ptn5150grp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 +- >; +- }; +- +- pinctrl_reg_usb_otg2_vbus: regusbotg2vbusgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x16 +- >; +- }; +- +- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 +- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 +- MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-var-som.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-var-som.dtsi +deleted file mode 100644 +index 1dc9d187601c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-var-som.dtsi ++++ /dev/null +@@ -1,558 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2019 NXP +- * Copyright (C) 2020 Krzysztof Kozlowski +- */ +- +-#include "imx8mm.dtsi" +- +-/ { +- model = "Variscite VAR-SOM-MX8MM module"; +- compatible = "variscite,var-som-mx8mm", "fsl,imx8mm"; +- +- chosen { +- stdout-path = &uart4; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x0 0x40000000 0 0x80000000>; +- }; +- +- reg_eth_phy: regulator-eth-phy { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_eth_phy>; +- regulator-name = "eth_phy_pwr"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&A53_0 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_1 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_2 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_3 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&ddrc { +- operating-points-v2 = <&ddrc_opp_table>; +- +- ddrc_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-25M { +- opp-hz = /bits/ 64 <25000000>; +- }; +- +- opp-100M { +- opp-hz = /bits/ 64 <100000000>; +- }; +- +- opp-750M { +- opp-hz = /bits/ 64 <750000000>; +- }; +- }; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>, +- <&gpio1 0 GPIO_ACTIVE_LOW>; +- /delete-property/ dmas; +- /delete-property/ dma-names; +- status = "okay"; +- +- /* Resistive touch controller */ +- touchscreen@0 { +- reg = <0>; +- compatible = "ti,ads7846"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_restouch>; +- interrupt-parent = <&gpio1>; +- interrupts = <3 IRQ_TYPE_EDGE_FALLING>; +- +- spi-max-frequency = <1500000>; +- pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; +- +- ti,x-min = /bits/ 16 <125>; +- touchscreen-size-x = /bits/ 16 <4008>; +- ti,y-min = /bits/ 16 <282>; +- touchscreen-size-y = /bits/ 16 <3864>; +- ti,x-plate-ohms = /bits/ 16 <180>; +- touchscreen-max-pressure = /bits/ 16 <255>; +- touchscreen-average-samples = /bits/ 16 <10>; +- ti,debounce-tol = /bits/ 16 <3>; +- ti,debounce-rep = /bits/ 16 <1>; +- ti,settle-delay-usec = /bits/ 16 <150>; +- ti,keep-vref-on; +- wakeup-source; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii"; +- phy-handle = <ðphy>; +- phy-supply = <®_eth_phy>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy@4 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <4>; +- reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- reset-deassert-us = <10000>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic@4b { +- compatible = "rohm,bd71847"; +- reg = <0x4b>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio2>; +- interrupts = <8 IRQ_TYPE_LEVEL_LOW>; +- rohm,reset-snvs-powered; +- +- #clock-cells = <0>; +- clocks = <&osc_32k 0>; +- clock-output-names = "clk-32k-out"; +- +- regulators { +- buck1_reg: BUCK1 { +- regulator-name = "buck1"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "buck2"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- rohm,dvs-run-voltage = <1000000>; +- rohm,dvs-idle-voltage = <900000>; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "buck3"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "buck4"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "buck5"; +- regulator-min-microvolt = <1605000>; +- regulator-max-microvolt = <1995000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck6_reg: BUCK6 { +- regulator-name = "buck6"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1_reg: LDO1 { +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1600000>; +- regulator-max-microvolt = <1900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "ldo2"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "ldo4"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo5_reg: LDO5 { +- regulator-compatible = "ldo5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "ldo6"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- /* TODO: configure audio, as of now just put a placeholder */ +- wm8904: codec@1a { +- compatible = "wlf,wm8904"; +- reg = <0x1a>; +- status = "disabled"; +- }; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +- +-/* Bluetooth */ +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- assigned-clocks = <&clk IMX8MM_CLK_UART2>; +- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-/* Console */ +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbotg1 { +- dr_mode = "otg"; +- usb-role-switch; +- status = "okay"; +-}; +- +-&usbotg2 { +- dr_mode = "otg"; +- usb-role-switch; +- status = "okay"; +-}; +- +-/* WIFI */ +-&usdhc1 { +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- bus-width = <4>; +- non-removable; +- keep-power-in-suspend; +- status = "okay"; +- +- brcmf: bcrmf@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* SD */ +-&usdhc2 { +- assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +- cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- vmmc-supply = <®_usdhc2_vmmc>; +- status = "okay"; +-}; +- +-/* eMMC */ +-&usdhc3 { +- assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; +- assigned-clock-rates = <400000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 +- MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13 +- MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13 +- MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13 +- MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13 +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 +- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_pmic: pmicirqgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 +- >; +- }; +- +- pinctrl_reg_eth_phy: regethphygrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 +- >; +- }; +- +- pinctrl_restouch: restouchgrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 +- MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 +- MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 +- MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 +- MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 +- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 +- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 +- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 +- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 +- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 +- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 +- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 +- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 +- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 +- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 +- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 +- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 +- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 +- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 +- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 +- >; +- }; +- +- pinctrl_usdhc2_gpio: usdhc2gpiogrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 +- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 +- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 +- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw700x.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw700x.dtsi +deleted file mode 100644 +index 00f86cada30d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw700x.dtsi ++++ /dev/null +@@ -1,505 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2020 Gateworks Corporation +- */ +- +-#include +-#include +-#include +- +-/ { +- memory@40000000 { +- device_type = "memory"; +- reg = <0x0 0x40000000 0 0x80000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-pb { +- label = "user_pb"; +- gpios = <&gpio 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- user-pb1x { +- label = "user_pb1x"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <0>; +- }; +- +- key-erased { +- label = "key_erased"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <1>; +- }; +- +- eeprom-wp { +- label = "eeprom_wp"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <2>; +- }; +- +- tamper { +- label = "tamper"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <5>; +- }; +- +- switch-hold { +- label = "switch_hold"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <7>; +- }; +- }; +-}; +- +-&A53_0 { +- cpu-supply = <&buck3_reg>; +-}; +- +-&A53_1 { +- cpu-supply = <&buck3_reg>; +-}; +- +-&A53_2 { +- cpu-supply = <&buck3_reg>; +-}; +- +-&A53_3 { +- cpu-supply = <&buck3_reg>; +-}; +- +-&ddrc { +- operating-points-v2 = <&ddrc_opp_table>; +- +- ddrc_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-25M { +- opp-hz = /bits/ 64 <25000000>; +- }; +- +- opp-100M { +- opp-hz = /bits/ 64 <100000000>; +- }; +- +- opp-750M { +- opp-hz = /bits/ 64 <750000000>; +- }; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- ti,rx-internal-delay = ; +- ti,tx-internal-delay = ; +- tx-fifo-depth = ; +- rx-fifo-depth = ; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- gsc: gsc@20 { +- compatible = "gw,gsc"; +- reg = <0x20>; +- pinctrl-0 = <&pinctrl_gsc>; +- interrupt-parent = <&gpio2>; +- interrupts = <6 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- adc { +- compatible = "gw,gsc-adc"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@6 { +- gw,mode = <0>; +- reg = <0x06>; +- label = "temp"; +- }; +- +- channel@8 { +- gw,mode = <1>; +- reg = <0x08>; +- label = "vdd_bat"; +- }; +- +- channel@16 { +- gw,mode = <4>; +- reg = <0x16>; +- label = "fan_tach"; +- }; +- +- channel@82 { +- gw,mode = <2>; +- reg = <0x82>; +- label = "vdd_vin"; +- gw,voltage-divider-ohms = <22100 1000>; +- }; +- +- channel@84 { +- gw,mode = <2>; +- reg = <0x84>; +- label = "vdd_adc1"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- +- channel@86 { +- gw,mode = <2>; +- reg = <0x86>; +- label = "vdd_adc2"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- +- channel@88 { +- gw,mode = <2>; +- reg = <0x88>; +- label = "vdd_dram"; +- }; +- +- channel@8c { +- gw,mode = <2>; +- reg = <0x8c>; +- label = "vdd_1p2"; +- }; +- +- channel@8e { +- gw,mode = <2>; +- reg = <0x8e>; +- label = "vdd_1p0"; +- }; +- +- channel@90 { +- gw,mode = <2>; +- reg = <0x90>; +- label = "vdd_2p5"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- +- channel@92 { +- gw,mode = <2>; +- reg = <0x92>; +- label = "vdd_3p3"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- +- channel@98 { +- gw,mode = <2>; +- reg = <0x98>; +- label = "vdd_0p95"; +- }; +- +- channel@9a { +- gw,mode = <2>; +- reg = <0x9a>; +- label = "vdd_1p8"; +- }; +- +- channel@a2 { +- gw,mode = <2>; +- reg = <0xa2>; +- label = "vdd_gsc"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- }; +- +- fan-controller@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "gw,gsc-fan"; +- reg = <0x0a>; +- }; +- }; +- +- gpio: gpio@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gsc>; +- interrupts = <4>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +- +- pmic@69 { +- compatible = "mps,mp5416"; +- reg = <0x69>; +- +- regulators { +- /* vdd_0p95: DRAM/GPU/VPU */ +- buck1 { +- regulator-name = "buck1"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1000000>; +- regulator-min-microamp = <3800000>; +- regulator-max-microamp = <6800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdd_soc */ +- buck2 { +- regulator-name = "buck2"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <900000>; +- regulator-min-microamp = <2200000>; +- regulator-max-microamp = <5200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdd_arm */ +- buck3_reg: buck3 { +- regulator-name = "buck3"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1000000>; +- regulator-min-microamp = <3800000>; +- regulator-max-microamp = <6800000>; +- regulator-always-on; +- }; +- +- /* vdd_1p8 */ +- buck4 { +- regulator-name = "buck4"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-min-microamp = <2200000>; +- regulator-max-microamp = <5200000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* nvcc_snvs_1p8 */ +- ldo1 { +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdd_snvs_0p8 */ +- ldo2 { +- regulator-name = "ldo2"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdd_0p9 */ +- ldo3 { +- regulator-name = "ldo3"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdd_1p8 */ +- ldo4 { +- regulator-name = "ldo4"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- eeprom@52 { +- compatible = "atmel,24c32"; +- reg = <0x52>; +- pagesize = <32>; +- }; +-}; +- +-/* console */ +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-/* eMMC */ +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 +- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 +- >; +- }; +- +- pinctrl_gsc: gscgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x159 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 +- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw71xx-0x.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw71xx-0x.dts +deleted file mode 100644 +index 3f88c4ad5716..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw71xx-0x.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2020 Gateworks Corporation +- */ +- +-/dts-v1/; +- +-#include "imx8mm.dtsi" +-#include "imx8mm-venice-gw700x.dtsi" +-#include "imx8mm-venice-gw71xx.dtsi" +- +-/ { +- model = "Gateworks Venice GW71xx-0x i.MX8MM Development Kit"; +- compatible = "gw,imx8mm-gw71xx-0x", "fsl,imx8mm"; +- +- chosen { +- stdout-path = &uart2; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw71xx.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw71xx.dtsi +deleted file mode 100644 +index 8e4a0ce99790..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw71xx.dtsi ++++ /dev/null +@@ -1,187 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2020 Gateworks Corporation +- */ +- +-#include +-#include +- +-/ { +- aliases { +- usb0 = &usbotg1; +- usb1 = &usbotg2; +- }; +- +- led-controller { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led-0 { +- function = LED_FUNCTION_STATUS; +- color = ; +- gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-1 { +- function = LED_FUNCTION_STATUS; +- color = ; +- gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- pps { +- compatible = "pps-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pps>; +- gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- reg_usb_otg1_vbus: regulator-usb-otg1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usb1_en>; +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg1_vbus"; +- gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +-}; +- +-/* off-board header */ +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi2>; +- cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- accelerometer@19 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_accel>; +- compatible = "st,lis2de12"; +- reg = <0x19>; +- st,drdy-int-pin = <1>; +- interrupt-parent = <&gpio4>; +- interrupts = <5 IRQ_TYPE_LEVEL_LOW>; +- interrupt-names = "INT1"; +- }; +-}; +- +-/* off-board header */ +-&i2c3 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-/* GPS */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-/* off-board header */ +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&usbotg1 { +- dr_mode = "otg"; +- vbus-supply = <®_usb_otg1_vbus>; +- status = "okay"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ +- MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ +- MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ +- MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ +- MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ +- MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000041 /* DIO2 */ +- MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIO2 */ +- >; +- }; +- +- pinctrl_accel: accelgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 +- MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_pps: ppsgrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 +- >; +- }; +- +- pinctrl_reg_usb1_en: regusb1grp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 +- MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141 +- MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 +- >; +- }; +- +- pinctrl_spi2: spi2grp { +- fsl,pins = < +- MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 +- MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 +- MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 +- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 +- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 +- MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw72xx-0x.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw72xx-0x.dts +deleted file mode 100644 +index b1e7540f0281..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw72xx-0x.dts ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2020 Gateworks Corporation +- */ +- +-/dts-v1/; +- +-#include "imx8mm.dtsi" +-#include "imx8mm-venice-gw700x.dtsi" +-#include "imx8mm-venice-gw72xx.dtsi" +- +-/ { +- model = "Gateworks Venice GW72xx-0x i.MX8MM Development Kit"; +- compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm"; +- +- chosen { +- stdout-path = &uart2; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw72xx.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw72xx.dtsi +deleted file mode 100644 +index b7c91bdc21dd..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw72xx.dtsi ++++ /dev/null +@@ -1,311 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2020 Gateworks Corporation +- */ +- +-#include +-#include +- +-/ { +- aliases { +- usb0 = &usbotg1; +- usb1 = &usbotg2; +- }; +- +- led-controller { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led-0 { +- function = LED_FUNCTION_STATUS; +- color = ; +- gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-1 { +- function = LED_FUNCTION_STATUS; +- color = ; +- gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- pps { +- compatible = "pps-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pps>; +- gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_otg1_vbus: regulator-usb-otg1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usb1_en>; +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg1_vbus"; +- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usb_otg2_vbus: regulator-usb-otg2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usb2_en>; +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg2_vbus"; +- gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +-}; +- +-/* off-board header */ +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi2>; +- cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- accelerometer@19 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_accel>; +- compatible = "st,lis2de12"; +- reg = <0x19>; +- st,drdy-int-pin = <1>; +- interrupt-parent = <&gpio4>; +- interrupts = <5 IRQ_TYPE_LEVEL_LOW>; +- interrupt-names = "INT1"; +- }; +-}; +- +-/* off-board header */ +-&i2c3 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-/* off-board header */ +-&sai3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai3>; +- assigned-clocks = <&clk IMX8MM_CLK_SAI3>; +- assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; +- assigned-clock-rates = <24576000>; +- status = "okay"; +-}; +- +-/* GPS */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-/* off-board header */ +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-/* RS232 */ +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbotg1 { +- dr_mode = "otg"; +- vbus-supply = <®_usb_otg1_vbus>; +- status = "okay"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- vbus-supply = <®_usb_otg2_vbus>; +- status = "okay"; +-}; +- +-/* microSD */ +-&usdhc2 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ +- MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ +- MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ +- MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ +- MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ +- MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */ +- MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */ +- MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */ +- >; +- }; +- +- pinctrl_accel: accelgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 +- MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_pps: ppsgrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 +- >; +- }; +- +- pinctrl_reg_usb1_en: regusb1grp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 +- MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 +- >; +- }; +- +- pinctrl_reg_usb2_en: regusb2grp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41 +- >; +- }; +- +- pinctrl_sai3: sai3grp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 +- MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 +- MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 +- MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 +- MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 +- >; +- }; +- +- pinctrl_spi2: spi2grp { +- fsl,pins = < +- MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 +- MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 +- MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 +- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 +- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 +- MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 +- MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 +- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 +- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 +- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 +- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 +- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 +- >; +- }; +- +- pinctrl_usdhc2_gpio: usdhc2gpiogrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 +- MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0 +- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw73xx-0x.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw73xx-0x.dts +deleted file mode 100644 +index 6905437ff281..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw73xx-0x.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2020 Gateworks Corporation +- */ +- +-/dts-v1/; +- +-#include "imx8mm.dtsi" +-#include "imx8mm-venice-gw700x.dtsi" +-#include "imx8mm-venice-gw73xx.dtsi" +- +-/ { +- model = "Gateworks Venice GW73xx-0x i.MX8MM Development Kit"; +- compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm"; +- +- chosen { +- stdout-path = &uart2; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw73xx.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw73xx.dtsi +deleted file mode 100644 +index d2ffd62a3bd4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw73xx.dtsi ++++ /dev/null +@@ -1,362 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2020 Gateworks Corporation +- */ +- +-#include +-#include +- +-/ { +- aliases { +- usb0 = &usbotg1; +- usb1 = &usbotg2; +- }; +- +- led-controller { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led-0 { +- function = LED_FUNCTION_STATUS; +- color = ; +- gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-1 { +- function = LED_FUNCTION_STATUS; +- color = ; +- gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- pps { +- compatible = "pps-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pps>; +- gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb_otg1_vbus: regulator-usb-otg1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usb1_en>; +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg1_vbus"; +- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_usb_otg2_vbus: regulator-usb-otg2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usb2_en>; +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg2_vbus"; +- gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_wifi_en: regulator-wifi-en { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_wl>; +- compatible = "regulator-fixed"; +- regulator-name = "wl"; +- gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <100>; +- enable-active-high; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-/* off-board header */ +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi2>; +- cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- accelerometer@19 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_accel>; +- compatible = "st,lis2de12"; +- reg = <0x19>; +- st,drdy-int-pin = <1>; +- interrupt-parent = <&gpio4>; +- interrupts = <5 IRQ_TYPE_LEVEL_LOW>; +- interrupt-names = "INT1"; +- }; +-}; +- +-/* off-board header */ +-&i2c3 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-/* off-board header */ +-&sai3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai3>; +- assigned-clocks = <&clk IMX8MM_CLK_SAI3>; +- assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; +- assigned-clock-rates = <24576000>; +- status = "okay"; +-}; +- +-/* GPS */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-/* bluetooth HCI */ +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>; +- cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; +- rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm4330-bt"; +- shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-/* RS232 */ +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbotg1 { +- dr_mode = "otg"; +- vbus-supply = <®_usb_otg1_vbus>; +- status = "okay"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- vbus-supply = <®_usb_otg2_vbus>; +- status = "okay"; +-}; +- +-/* SDIO WiFi */ +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- bus-width = <4>; +- non-removable; +- vmmc-supply = <®_wifi_en>; +- status = "okay"; +-}; +- +-/* microSD */ +-&usdhc2 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ +- MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ +- MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ +- MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ +- MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ +- MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */ +- MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */ +- MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */ +- >; +- }; +- +- pinctrl_accel: accelgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 +- >; +- }; +- +- pinctrl_bten: btengrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 +- MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_pps: ppsgrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 +- >; +- }; +- +- pinctrl_reg_wl: regwlgrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 +- >; +- }; +- +- pinctrl_reg_usb1_en: regusb1grp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 +- MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 +- >; +- }; +- +- pinctrl_reg_usb2_en: regusb2grp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41 +- >; +- }; +- +- pinctrl_sai3: sai3grp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 +- MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 +- MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 +- MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 +- MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 +- >; +- }; +- +- pinctrl_spi2: spi2grp { +- fsl,pins = < +- MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 +- MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 +- MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 +- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 +- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 +- MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 +- MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x140 +- MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 +- MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 +- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 +- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 +- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 +- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 +- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 +- >; +- }; +- +- pinctrl_usdhc2_gpio: usdhc2gpiogrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 +- MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0 +- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw7901.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw7901.dts +deleted file mode 100644 +index bafd5c8ea4e2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw7901.dts ++++ /dev/null +@@ -1,1018 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2020 Gateworks Corporation +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +- +-#include "imx8mm.dtsi" +- +-/ { +- model = "Gateworks Venice GW7901 i.MX8MM board"; +- compatible = "gw,imx8mm-gw7901", "fsl,imx8mm"; +- +- aliases { +- ethernet0 = &fec1; +- ethernet1 = &lan1; +- ethernet2 = &lan2; +- ethernet3 = &lan3; +- ethernet4 = &lan4; +- usb0 = &usbotg1; +- usb1 = &usbotg2; +- }; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x0 0x40000000 0 0x80000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-pb { +- label = "user_pb"; +- gpios = <&gpio 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- user-pb1x { +- label = "user_pb1x"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <0>; +- }; +- +- key-erased { +- label = "key_erased"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <1>; +- }; +- +- eeprom-wp { +- label = "eeprom_wp"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <2>; +- }; +- +- tamper { +- label = "tamper"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <5>; +- }; +- +- switch-hold { +- label = "switch_hold"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <7>; +- }; +- }; +- +- led-controller { +- compatible = "gpio-leds"; +- +- led-0 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "led01_red"; +- gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-1 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "led01_grn"; +- gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-2 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "led02_red"; +- gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-3 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "led02_grn"; +- gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-4 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "led03_red"; +- gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-5 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "led03_grn"; +- gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-6 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "led04_red"; +- gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-7 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "led04_grn"; +- gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-8 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "led05_red"; +- gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-9 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "led05_grn"; +- gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-a { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "led06_red"; +- gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-b { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "led06_grn"; +- gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- regulator-ioexp { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_ioexp>; +- compatible = "regulator-fixed"; +- regulator-name = "ioexp"; +- gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- startup-delay-us = <100>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- regulator-isouart { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_isouart>; +- compatible = "regulator-fixed"; +- regulator-name = "iso_uart"; +- gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; +- startup-delay-us = <100>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb2_vbus: regulator-usb2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usb2>; +- compatible = "regulator-fixed"; +- regulator-name = "usb_usb2_vbus"; +- gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_wifi: regulator-wifi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_wl>; +- compatible = "regulator-fixed"; +- regulator-name = "wifi"; +- gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- startup-delay-us = <100>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&ddrc { +- operating-points-v2 = <&ddrc_opp_table>; +- +- ddrc_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-25M { +- opp-hz = /bits/ 64 <25000000>; +- }; +- +- opp-100M { +- opp-hz = /bits/ 64 <100000000>; +- }; +- +- opp-750M { +- opp-hz = /bits/ 64 <750000000>; +- }; +- }; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1>; +- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; +- status = "okay"; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- local-mac-address = [00 00 00 00 00 00]; +- status = "okay"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- gsc: gsc@20 { +- compatible = "gw,gsc"; +- reg = <0x20>; +- pinctrl-0 = <&pinctrl_gsc>; +- interrupt-parent = <&gpio4>; +- interrupts = <16 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <1>; +- +- adc { +- compatible = "gw,gsc-adc"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@6 { +- gw,mode = <0>; +- reg = <0x06>; +- label = "temp"; +- }; +- +- channel@8 { +- gw,mode = <1>; +- reg = <0x08>; +- label = "vdd_bat"; +- }; +- +- channel@82 { +- gw,mode = <2>; +- reg = <0x82>; +- label = "vin_aux1"; +- gw,voltage-divider-ohms = <22100 1000>; +- }; +- +- channel@84 { +- gw,mode = <2>; +- reg = <0x84>; +- label = "vin_aux2"; +- gw,voltage-divider-ohms = <22100 1000>; +- }; +- +- channel@86 { +- gw,mode = <2>; +- reg = <0x86>; +- label = "vdd_vin"; +- gw,voltage-divider-ohms = <22100 1000>; +- }; +- +- channel@88 { +- gw,mode = <2>; +- reg = <0x88>; +- label = "vdd_3p3"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- +- channel@8c { +- gw,mode = <2>; +- reg = <0x8c>; +- label = "vdd_2p5"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- +- channel@8e { +- gw,mode = <2>; +- reg = <0x8e>; +- label = "vdd_0p95"; +- }; +- +- channel@90 { +- gw,mode = <2>; +- reg = <0x90>; +- label = "vdd_soc"; +- }; +- +- channel@92 { +- gw,mode = <2>; +- reg = <0x92>; +- label = "vdd_arm"; +- }; +- +- channel@98 { +- gw,mode = <2>; +- reg = <0x98>; +- label = "vdd_1p8"; +- }; +- +- channel@9a { +- gw,mode = <2>; +- reg = <0x9a>; +- label = "vdd_1p2"; +- }; +- +- channel@9c { +- gw,mode = <2>; +- reg = <0x9c>; +- label = "vdd_dram"; +- }; +- +- channel@a2 { +- gw,mode = <2>; +- reg = <0xa2>; +- label = "vdd_gsc"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- }; +- }; +- +- gpio: gpio@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gsc>; +- interrupts = <4>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- pmic@4b { +- compatible = "rohm,bd71847"; +- reg = <0x4b>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio3>; +- interrupts = <20 IRQ_TYPE_LEVEL_LOW>; +- rohm,reset-snvs-powered; +- #clock-cells = <0>; +- clocks = <&osc_32k 0>; +- clock-output-names = "clk-32k-out"; +- +- regulators { +- /* vdd_soc: 0.805-0.900V (typ=0.8V) */ +- BUCK1 { +- regulator-name = "buck1"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- }; +- +- /* vdd_arm: 0.805-1.0V (typ=0.9V) */ +- BUCK2 { +- regulator-name = "buck2"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- rohm,dvs-run-voltage = <1000000>; +- rohm,dvs-idle-voltage = <900000>; +- }; +- +- /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ +- BUCK3 { +- regulator-name = "buck3"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdd_3p3 */ +- BUCK4 { +- regulator-name = "buck4"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdd_1p8 */ +- BUCK5 { +- regulator-name = "buck5"; +- regulator-min-microvolt = <1605000>; +- regulator-max-microvolt = <1995000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdd_dram */ +- BUCK6 { +- regulator-name = "buck6"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* nvcc_snvs_1p8 */ +- LDO1 { +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1600000>; +- regulator-max-microvolt = <1900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdd_snvs_0p8 */ +- LDO2 { +- regulator-name = "ldo2"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdda_1p8 */ +- LDO3 { +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- LDO4 { +- regulator-name = "ldo4"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- LDO6 { +- regulator-name = "ldo6"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- leds_gpio: gpio@20 { +- compatible = "nxp,pca9555"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- switch: switch@5f { +- compatible = "microchip,ksz9897"; +- reg = <0x5f>; +- pinctrl-0 = <&pinctrl_ksz>; +- interrupt-parent = <&gpio4>; +- interrupts = <18 IRQ_TYPE_EDGE_FALLING>; +- phy-mode = "rgmii-id"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- lan1: port@0 { +- reg = <0>; +- label = "lan1"; +- local-mac-address = [00 00 00 00 00 00]; +- }; +- +- lan2: port@1 { +- reg = <1>; +- label = "lan2"; +- local-mac-address = [00 00 00 00 00 00]; +- }; +- +- lan3: port@2 { +- reg = <2>; +- label = "lan3"; +- local-mac-address = [00 00 00 00 00 00]; +- }; +- +- lan4: port@3 { +- reg = <3>; +- label = "lan4"; +- local-mac-address = [00 00 00 00 00 00]; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <&fec1>; +- phy-mode = "rgmii-id"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; +- +- crypto@60 { +- compatible = "atmel,atecc508a"; +- reg = <0x60>; +- }; +-}; +- +-&i2c4 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; +- rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; +- cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; +- dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; +- dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-/* console */ +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; +- cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; +- rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>; +- cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; +- rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&usbotg1 { +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- vbus-supply = <®_usb2_vbus>; +- status = "okay"; +-}; +- +-/* SDIO WiFi */ +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- bus-width = <4>; +- non-removable; +- vmmc-supply = <®_wifi>; +- status = "okay"; +-}; +- +-/* microSD */ +-&usdhc2 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- vmmc-supply = <®_3p3v>; +- status = "okay"; +-}; +- +-/* eMMC */ +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */ +- MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */ +- MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */ +- MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */ +- MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */ +- MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */ +- MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */ +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 +- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */ +- MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */ +- >; +- }; +- +- pinctrl_gsc: gscgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_ksz: kszgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41 +- MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */ +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 +- >; +- }; +- +- pinctrl_reg_isouart: regisouartgrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 +- >; +- }; +- +- pinctrl_reg_ioexp: regioexpgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 +- >; +- }; +- +- pinctrl_reg_wl: regwlgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041 +- >; +- }; +- +- pinctrl_reg_usb2: regusb1grp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x41 +- MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140 +- MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x140 +- >; +- }; +- +- pinctrl_spi1: spi1grp { +- fsl,pins = < +- MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 +- MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 +- MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 +- MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 +- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 +- MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 +- MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 +- MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140 +- MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140 +- MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140 +- >; +- }; +- +- pinctrl_uart1_gpio: uart1gpiogrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */ +- MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */ +- MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */ +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 +- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 +- MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 +- MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140 +- MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 +- >; +- }; +- +- pinctrl_uart3_gpio: uart3gpiogrp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* RS232# */ +- MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* RS422# */ +- MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* RS485# */ +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 +- MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 +- MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140 +- MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140 +- >; +- }; +- +- pinctrl_uart4_gpio: uart4gpiogrp { +- fsl,pins = < +- +- MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */ +- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */ +- MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */ +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 +- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 +- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 +- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 +- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 +- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 +- >; +- }; +- +- pinctrl_usdhc2_gpio: usdhc2-gpiogrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 +- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 +- >; +- }; +-}; +- +-&cpu_alert0 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +-}; +- +-&cpu_crit0 { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "critical"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw7902.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw7902.dts +deleted file mode 100644 +index d52686f4c059..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-venice-gw7902.dts ++++ /dev/null +@@ -1,911 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2021 Gateworks Corporation +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include +- +-#include "imx8mm.dtsi" +- +-/ { +- model = "Gateworks Venice GW7902 i.MX8MM board"; +- compatible = "gw,imx8mm-gw7902", "fsl,imx8mm"; +- +- aliases { +- usb0 = &usbotg1; +- usb1 = &usbotg2; +- }; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x0 0x40000000 0 0x80000000>; +- }; +- +- can20m: can20m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <20000000>; +- clock-output-names = "can20m"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-pb { +- label = "user_pb"; +- gpios = <&gpio 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- user-pb1x { +- label = "user_pb1x"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <0>; +- }; +- +- key-erased { +- label = "key_erased"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <1>; +- }; +- +- eeprom-wp { +- label = "eeprom_wp"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <2>; +- }; +- +- tamper { +- label = "tamper"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <5>; +- }; +- +- switch-hold { +- label = "switch_hold"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <7>; +- }; +- }; +- +- led-controller { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led-0 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "panel1"; +- gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led-1 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "panel2"; +- gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led-2 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "panel3"; +- gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led-3 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "panel4"; +- gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led-4 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "panel5"; +- gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- pps { +- compatible = "pps-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pps>; +- gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb1_vbus: regulator-usb1 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usb1>; +- regulator-name = "usb_usb1_vbus"; +- gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_wifi: regulator-wifi { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_wl>; +- regulator-name = "wifi"; +- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- startup-delay-us = <100>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&A53_0 { +- cpu-supply = <&buck2>; +-}; +- +-&A53_1 { +- cpu-supply = <&buck2>; +-}; +- +-&A53_2 { +- cpu-supply = <&buck2>; +-}; +- +-&A53_3 { +- cpu-supply = <&buck2>; +-}; +- +-&ddrc { +- operating-points-v2 = <&ddrc_opp_table>; +- +- ddrc_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-25M { +- opp-hz = /bits/ 64 <25000000>; +- }; +- +- opp-100M { +- opp-hz = /bits/ 64 <100000000>; +- }; +- +- opp-750M { +- opp-hz = /bits/ 64 <750000000>; +- }; +- }; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1>; +- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- can@0 { +- compatible = "microchip,mcp2515"; +- reg = <0>; +- clocks = <&can20m>; +- oscillator-frequency = <20000000>; +- interrupt-parent = <&gpio2>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- spi-max-frequency = <10000000>; +- }; +-}; +- +-/* off-board header */ +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi2>; +- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- local-mac-address = [00 00 00 00 00 00]; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- ti,rx-internal-delay = ; +- ti,tx-internal-delay = ; +- tx-fifo-depth = ; +- rx-fifo-depth = ; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- gsc: gsc@20 { +- compatible = "gw,gsc"; +- reg = <0x20>; +- pinctrl-0 = <&pinctrl_gsc>; +- interrupt-parent = <&gpio2>; +- interrupts = <6 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <1>; +- +- adc { +- compatible = "gw,gsc-adc"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@6 { +- gw,mode = <0>; +- reg = <0x06>; +- label = "temp"; +- }; +- +- channel@8 { +- gw,mode = <1>; +- reg = <0x08>; +- label = "vdd_bat"; +- }; +- +- channel@82 { +- gw,mode = <2>; +- reg = <0x82>; +- label = "vin"; +- gw,voltage-divider-ohms = <22100 1000>; +- gw,voltage-offset-microvolt = <700000>; +- }; +- +- channel@84 { +- gw,mode = <2>; +- reg = <0x84>; +- label = "vin_4p0"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- +- channel@86 { +- gw,mode = <2>; +- reg = <0x86>; +- label = "vdd_3p3"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- +- channel@88 { +- gw,mode = <2>; +- reg = <0x88>; +- label = "vdd_0p9"; +- }; +- +- channel@8c { +- gw,mode = <2>; +- reg = <0x8c>; +- label = "vdd_soc"; +- }; +- +- channel@8e { +- gw,mode = <2>; +- reg = <0x8e>; +- label = "vdd_arm"; +- }; +- +- channel@90 { +- gw,mode = <2>; +- reg = <0x90>; +- label = "vdd_1p8"; +- }; +- +- channel@92 { +- gw,mode = <2>; +- reg = <0x92>; +- label = "vdd_dram"; +- }; +- +- channel@98 { +- gw,mode = <2>; +- reg = <0x98>; +- label = "vdd_1p0"; +- }; +- +- channel@9a { +- gw,mode = <2>; +- reg = <0x9a>; +- label = "vdd_2p5"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- +- channel@a2 { +- gw,mode = <2>; +- reg = <0xa2>; +- label = "vdd_gsc"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- }; +- }; +- +- gpio: gpio@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gsc>; +- interrupts = <4>; +- }; +- +- pmic@4b { +- compatible = "rohm,bd71847"; +- reg = <0x4b>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio3>; +- interrupts = <8 IRQ_TYPE_LEVEL_LOW>; +- rohm,reset-snvs-powered; +- #clock-cells = <0>; +- clocks = <&osc_32k 0>; +- clock-output-names = "clk-32k-out"; +- +- regulators { +- /* vdd_soc: 0.805-0.900V (typ=0.8V) */ +- BUCK1 { +- regulator-name = "buck1"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- }; +- +- /* vdd_arm: 0.805-1.0V (typ=0.9V) */ +- buck2: BUCK2 { +- regulator-name = "buck2"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- rohm,dvs-run-voltage = <1000000>; +- rohm,dvs-idle-voltage = <900000>; +- }; +- +- /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ +- BUCK3 { +- regulator-name = "buck3"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdd_3p3 */ +- BUCK4 { +- regulator-name = "buck4"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdd_1p8 */ +- BUCK5 { +- regulator-name = "buck5"; +- regulator-min-microvolt = <1605000>; +- regulator-max-microvolt = <1995000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdd_dram */ +- BUCK6 { +- regulator-name = "buck6"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* nvcc_snvs_1p8 */ +- LDO1 { +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1600000>; +- regulator-max-microvolt = <1900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdd_snvs_0p8 */ +- LDO2 { +- regulator-name = "ldo2"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdda_1p8 */ +- LDO3 { +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- LDO4 { +- regulator-name = "ldo4"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- LDO6 { +- regulator-name = "ldo6"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- accelerometer@19 { +- compatible = "st,lis2de12"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_accel>; +- reg = <0x19>; +- st,drdy-int-pin = <1>; +- interrupt-parent = <&gpio1>; +- interrupts = <12 IRQ_TYPE_LEVEL_LOW>; +- interrupt-names = "INT1"; +- }; +-}; +- +-/* off-board header */ +-&i2c3 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-/* off-board header */ +-&i2c4 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +-}; +- +-/* off-board header */ +-&sai3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai3>; +- assigned-clocks = <&clk IMX8MM_CLK_SAI3>; +- assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; +- assigned-clock-rates = <24576000>; +- status = "okay"; +-}; +- +-/* RS232/RS485/RS422 selectable */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; +- rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; +- cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-/* RS232 console */ +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-/* bluetooth HCI */ +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; +- rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +- cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm4330-bt"; +- shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */ +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; +- cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; +- dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>; +- dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; +- dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&usbotg1 { +- dr_mode = "host"; +- vbus-supply = <®_usb1_vbus>; +- disable-over-current; +- status = "okay"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- disable-over-current; +- status = "okay"; +-}; +- +-/* SDIO WiFi */ +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- non-removable; +- vmmc-supply = <®_wifi>; +- status = "okay"; +-}; +- +-/* eMMC */ +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ +- MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */ +- MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ +- MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ +- MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ +- MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */ +- MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */ +- MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */ +- MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ +- MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ +- MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ +- MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ +- MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */ +- MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */ +- MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */ +- >; +- }; +- +- pinctrl_accel: accelgrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159 +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 +- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ +- MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ +- MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141 +- MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141 +- >; +- }; +- +- pinctrl_gsc: gscgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 +- MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 +- MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 +- MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 +- MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 +- MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 +- >; +- }; +- +- pinctrl_pps: ppsgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */ +- >; +- }; +- +- pinctrl_reg_wl: regwlgrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */ +- >; +- }; +- +- pinctrl_reg_usb1: regusb1grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41 +- >; +- }; +- +- pinctrl_sai3: sai3grp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 +- MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 +- MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 +- MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 +- MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 +- >; +- }; +- +- pinctrl_spi1: spi1grp { +- fsl,pins = < +- MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 +- MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 +- MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 +- MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40 +- MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */ +- >; +- }; +- +- pinctrl_spi2: spi2grp { +- fsl,pins = < +- MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 +- MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 +- MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 +- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */ +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 +- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 +- MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 /* RTS */ +- MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 /* CTS */ +- >; +- }; +- +- pinctrl_uart1_gpio: uart1gpiogrp { +- fsl,pins = < +- MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */ +- MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */ +- MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */ +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 +- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_uart3_gpio: uart3_gpiogrp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */ +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 +- MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 +- MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */ +- MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */ +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 +- MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 +- MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x140 /* CTS */ +- MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x140 /* RTS */ +- MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* DTR */ +- MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x140 /* DSR */ +- MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* DCD */ +- MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* RI */ +- MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x140 /* GNSS_PPS */ +- MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */ +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 +- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 +- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 +- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 +- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 +- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { +- fsl,pins = < +- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 +- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 +- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 +- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 +- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 +- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 +- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 +- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 +- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 +- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 +- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mm.dtsi +deleted file mode 100644 +index 2f632e8ca388..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mm.dtsi ++++ /dev/null +@@ -1,1058 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2019 NXP +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include "imx8mm-pinfunc.h" +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- ethernet0 = &fec1; +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- gpio3 = &gpio4; +- gpio4 = &gpio5; +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- i2c3 = &i2c4; +- mmc0 = &usdhc1; +- mmc1 = &usdhc2; +- mmc2 = &usdhc3; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- spi0 = &ecspi1; +- spi1 = &ecspi2; +- spi2 = &ecspi3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- idle-states { +- entry-method = "psci"; +- +- cpu_pd_wait: cpu-pd-wait { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x0010033>; +- local-timer-stop; +- entry-latency-us = <1000>; +- exit-latency-us = <700>; +- min-residency-us = <2700>; +- }; +- }; +- +- A53_0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0>; +- clock-latency = <61036>; /* two CLK32 periods */ +- clocks = <&clk IMX8MM_CLK_ARM>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- operating-points-v2 = <&a53_opp_table>; +- nvmem-cells = <&cpu_speed_grade>; +- nvmem-cell-names = "speed_grade"; +- cpu-idle-states = <&cpu_pd_wait>; +- #cooling-cells = <2>; +- }; +- +- A53_1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x1>; +- clock-latency = <61036>; /* two CLK32 periods */ +- clocks = <&clk IMX8MM_CLK_ARM>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- operating-points-v2 = <&a53_opp_table>; +- cpu-idle-states = <&cpu_pd_wait>; +- #cooling-cells = <2>; +- }; +- +- A53_2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x2>; +- clock-latency = <61036>; /* two CLK32 periods */ +- clocks = <&clk IMX8MM_CLK_ARM>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- operating-points-v2 = <&a53_opp_table>; +- cpu-idle-states = <&cpu_pd_wait>; +- #cooling-cells = <2>; +- }; +- +- A53_3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x3>; +- clock-latency = <61036>; /* two CLK32 periods */ +- clocks = <&clk IMX8MM_CLK_ARM>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- operating-points-v2 = <&a53_opp_table>; +- cpu-idle-states = <&cpu_pd_wait>; +- #cooling-cells = <2>; +- }; +- +- A53_L2: l2-cache0 { +- compatible = "cache"; +- }; +- }; +- +- a53_opp_table: opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <850000>; +- opp-supported-hw = <0xe>, <0x7>; +- clock-latency-ns = <150000>; +- opp-suspend; +- }; +- +- opp-1600000000 { +- opp-hz = /bits/ 64 <1600000000>; +- opp-microvolt = <950000>; +- opp-supported-hw = <0xc>, <0x7>; +- clock-latency-ns = <150000>; +- opp-suspend; +- }; +- +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <1000000>; +- opp-supported-hw = <0x8>, <0x3>; +- clock-latency-ns = <150000>; +- opp-suspend; +- }; +- }; +- +- osc_32k: clock-osc-32k { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "osc_32k"; +- }; +- +- osc_24m: clock-osc-24m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "osc_24m"; +- }; +- +- clk_ext1: clock-ext1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <133000000>; +- clock-output-names = "clk_ext1"; +- }; +- +- clk_ext2: clock-ext2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <133000000>; +- clock-output-names = "clk_ext2"; +- }; +- +- clk_ext3: clock-ext3 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <133000000>; +- clock-output-names = "clk_ext3"; +- }; +- +- clk_ext4: clock-ext4 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency= <133000000>; +- clock-output-names = "clk_ext4"; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = ; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , /* Physical Secure */ +- , /* Physical Non-Secure */ +- , /* Virtual */ +- ; /* Hypervisor */ +- clock-frequency = <8000000>; +- arm,no-tick-in-suspend; +- }; +- +- thermal-zones { +- cpu-thermal { +- polling-delay-passive = <250>; +- polling-delay = <2000>; +- thermal-sensors = <&tmu>; +- trips { +- cpu_alert0: trip0 { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_crit0: trip1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- cooling-device = +- <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- usbphynop1: usbphynop1 { +- #phy-cells = <0>; +- compatible = "usb-nop-xceiv"; +- clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; +- assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; +- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; +- clock-names = "main_clk"; +- }; +- +- usbphynop2: usbphynop2 { +- #phy-cells = <0>; +- compatible = "usb-nop-xceiv"; +- clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; +- assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; +- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; +- clock-names = "main_clk"; +- }; +- +- soc@0 { +- compatible = "fsl,imx8mm-soc", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x0 0x3e000000>; +- dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; +- nvmem-cells = <&imx8mm_uid>; +- nvmem-cell-names = "soc_unique_id"; +- +- aips1: bus@30000000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- reg = <0x30000000 0x400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x30000000 0x30000000 0x400000>; +- +- spba2: spba-bus@30000000 { +- compatible = "fsl,spba-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x30000000 0x100000>; +- ranges; +- +- sai1: sai@30010000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; +- reg = <0x30010000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_SAI1_IPG>, +- <&clk IMX8MM_CLK_SAI1_ROOT>, +- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sai2: sai@30020000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; +- reg = <0x30020000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_SAI2_IPG>, +- <&clk IMX8MM_CLK_SAI2_ROOT>, +- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sai3: sai@30030000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; +- reg = <0x30030000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_SAI3_IPG>, +- <&clk IMX8MM_CLK_SAI3_ROOT>, +- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sai5: sai@30050000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; +- reg = <0x30050000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_SAI5_IPG>, +- <&clk IMX8MM_CLK_SAI5_ROOT>, +- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sai6: sai@30060000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; +- reg = <0x30060000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_SAI6_IPG>, +- <&clk IMX8MM_CLK_SAI6_ROOT>, +- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- micfil: audio-controller@30080000 { +- compatible = "fsl,imx8mm-micfil"; +- reg = <0x30080000 0x10000>; +- interrupts = , +- , +- , +- ; +- clocks = <&clk IMX8MM_CLK_PDM_IPG>, +- <&clk IMX8MM_CLK_PDM_ROOT>, +- <&clk IMX8MM_AUDIO_PLL1_OUT>, +- <&clk IMX8MM_AUDIO_PLL2_OUT>, +- <&clk IMX8MM_CLK_EXT3>; +- clock-names = "ipg_clk", "ipg_clk_app", +- "pll8k", "pll11k", "clkext3"; +- dmas = <&sdma2 24 25 0x80000000>; +- dma-names = "rx"; +- status = "disabled"; +- }; +- +- spdif1: spdif@30090000 { +- compatible = "fsl,imx35-spdif"; +- reg = <0x30090000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ +- <&clk IMX8MM_CLK_24M>, /* rxtx0 */ +- <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ +- <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ +- <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ +- <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ +- <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ +- <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ +- <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ +- <&clk IMX8MM_CLK_DUMMY>; /* spba */ +- clock-names = "core", "rxtx0", +- "rxtx1", "rxtx2", +- "rxtx3", "rxtx4", +- "rxtx5", "rxtx6", +- "rxtx7", "spba"; +- dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- }; +- +- gpio1: gpio@30200000 { +- compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; +- reg = <0x30200000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 10 30>; +- }; +- +- gpio2: gpio@30210000 { +- compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; +- reg = <0x30210000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 40 21>; +- }; +- +- gpio3: gpio@30220000 { +- compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; +- reg = <0x30220000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 61 26>; +- }; +- +- gpio4: gpio@30230000 { +- compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; +- reg = <0x30230000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 87 32>; +- }; +- +- gpio5: gpio@30240000 { +- compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; +- reg = <0x30240000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 119 30>; +- }; +- +- tmu: tmu@30260000 { +- compatible = "fsl,imx8mm-tmu"; +- reg = <0x30260000 0x10000>; +- clocks = <&clk IMX8MM_CLK_TMU_ROOT>; +- #thermal-sensor-cells = <0>; +- }; +- +- wdog1: watchdog@30280000 { +- compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; +- reg = <0x30280000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; +- status = "disabled"; +- }; +- +- wdog2: watchdog@30290000 { +- compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; +- reg = <0x30290000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; +- status = "disabled"; +- }; +- +- wdog3: watchdog@302a0000 { +- compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; +- reg = <0x302a0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; +- status = "disabled"; +- }; +- +- sdma2: dma-controller@302c0000 { +- compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; +- reg = <0x302c0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, +- <&clk IMX8MM_CLK_SDMA2_ROOT>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; +- }; +- +- sdma3: dma-controller@302b0000 { +- compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; +- reg = <0x302b0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, +- <&clk IMX8MM_CLK_SDMA3_ROOT>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; +- }; +- +- iomuxc: pinctrl@30330000 { +- compatible = "fsl,imx8mm-iomuxc"; +- reg = <0x30330000 0x10000>; +- }; +- +- gpr: iomuxc-gpr@30340000 { +- compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; +- reg = <0x30340000 0x10000>; +- }; +- +- ocotp: efuse@30350000 { +- compatible = "fsl,imx8mm-ocotp", "syscon"; +- reg = <0x30350000 0x10000>; +- clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; +- /* For nvmem subnodes */ +- #address-cells = <1>; +- #size-cells = <1>; +- +- imx8mm_uid: unique-id@410 { +- reg = <0x4 0x8>; +- }; +- +- cpu_speed_grade: speed-grade@10 { +- reg = <0x10 4>; +- }; +- +- fec_mac_address: mac-address@90 { +- reg = <0x90 6>; +- }; +- }; +- +- anatop: anatop@30360000 { +- compatible = "fsl,imx8mm-anatop", "syscon"; +- reg = <0x30360000 0x10000>; +- }; +- +- snvs: snvs@30370000 { +- compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; +- reg = <0x30370000 0x10000>; +- +- snvs_rtc: snvs-rtc-lp { +- compatible = "fsl,sec-v4.0-mon-rtc-lp"; +- regmap = <&snvs>; +- offset = <0x34>; +- interrupts = , +- ; +- clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; +- clock-names = "snvs-rtc"; +- }; +- +- snvs_pwrkey: snvs-powerkey { +- compatible = "fsl,sec-v4.0-pwrkey"; +- regmap = <&snvs>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; +- clock-names = "snvs-pwrkey"; +- linux,keycode = ; +- wakeup-source; +- status = "disabled"; +- }; +- }; +- +- clk: clock-controller@30380000 { +- compatible = "fsl,imx8mm-ccm"; +- reg = <0x30380000 0x10000>; +- #clock-cells = <1>; +- clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, +- <&clk_ext3>, <&clk_ext4>; +- clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", +- "clk_ext3", "clk_ext4"; +- assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>, +- <&clk IMX8MM_CLK_A53_CORE>, +- <&clk IMX8MM_CLK_NOC>, +- <&clk IMX8MM_CLK_AUDIO_AHB>, +- <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, +- <&clk IMX8MM_SYS_PLL3>, +- <&clk IMX8MM_VIDEO_PLL1>, +- <&clk IMX8MM_AUDIO_PLL1>, +- <&clk IMX8MM_AUDIO_PLL2>; +- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, +- <&clk IMX8MM_ARM_PLL_OUT>, +- <&clk IMX8MM_SYS_PLL3_OUT>, +- <&clk IMX8MM_SYS_PLL1_800M>; +- assigned-clock-rates = <0>, <0>, <0>, +- <400000000>, +- <400000000>, +- <750000000>, +- <594000000>, +- <393216000>, +- <361267200>; +- }; +- +- src: reset-controller@30390000 { +- compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"; +- reg = <0x30390000 0x10000>; +- interrupts = ; +- #reset-cells = <1>; +- }; +- }; +- +- aips2: bus@30400000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- reg = <0x30400000 0x400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x30400000 0x30400000 0x400000>; +- +- pwm1: pwm@30660000 { +- compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; +- reg = <0x30660000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, +- <&clk IMX8MM_CLK_PWM1_ROOT>; +- clock-names = "ipg", "per"; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm2: pwm@30670000 { +- compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; +- reg = <0x30670000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, +- <&clk IMX8MM_CLK_PWM2_ROOT>; +- clock-names = "ipg", "per"; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm3: pwm@30680000 { +- compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; +- reg = <0x30680000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, +- <&clk IMX8MM_CLK_PWM3_ROOT>; +- clock-names = "ipg", "per"; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm4: pwm@30690000 { +- compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; +- reg = <0x30690000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, +- <&clk IMX8MM_CLK_PWM4_ROOT>; +- clock-names = "ipg", "per"; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- system_counter: timer@306a0000 { +- compatible = "nxp,sysctr-timer"; +- reg = <0x306a0000 0x20000>; +- interrupts = ; +- clocks = <&osc_24m>; +- clock-names = "per"; +- }; +- }; +- +- aips3: bus@30800000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- reg = <0x30800000 0x400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x30800000 0x30800000 0x400000>, +- <0x8000000 0x8000000 0x10000000>; +- +- spba1: spba-bus@30800000 { +- compatible = "fsl,spba-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x30800000 0x100000>; +- ranges; +- +- ecspi1: spi@30820000 { +- compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x30820000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, +- <&clk IMX8MM_CLK_ECSPI1_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ecspi2: spi@30830000 { +- compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x30830000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, +- <&clk IMX8MM_CLK_ECSPI2_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ecspi3: spi@30840000 { +- compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x30840000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, +- <&clk IMX8MM_CLK_ECSPI3_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart1: serial@30860000 { +- compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; +- reg = <0x30860000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_UART1_ROOT>, +- <&clk IMX8MM_CLK_UART1_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart3: serial@30880000 { +- compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; +- reg = <0x30880000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_UART3_ROOT>, +- <&clk IMX8MM_CLK_UART3_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart2: serial@30890000 { +- compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; +- reg = <0x30890000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_UART2_ROOT>, +- <&clk IMX8MM_CLK_UART2_ROOT>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- }; +- +- crypto: crypto@30900000 { +- compatible = "fsl,sec-v4.0"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x30900000 0x40000>; +- ranges = <0 0x30900000 0x40000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_AHB>, +- <&clk IMX8MM_CLK_IPG_ROOT>; +- clock-names = "aclk", "ipg"; +- +- sec_jr0: jr@1000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x1000 0x1000>; +- interrupts = ; +- }; +- +- sec_jr1: jr@2000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x2000 0x1000>; +- interrupts = ; +- }; +- +- sec_jr2: jr@3000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x3000 0x1000>; +- interrupts = ; +- }; +- }; +- +- i2c1: i2c@30a20000 { +- compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x30a20000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; +- status = "disabled"; +- }; +- +- i2c2: i2c@30a30000 { +- compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x30a30000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; +- status = "disabled"; +- }; +- +- i2c3: i2c@30a40000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; +- reg = <0x30a40000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; +- status = "disabled"; +- }; +- +- i2c4: i2c@30a50000 { +- compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x30a50000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; +- status = "disabled"; +- }; +- +- uart4: serial@30a60000 { +- compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; +- reg = <0x30a60000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_UART4_ROOT>, +- <&clk IMX8MM_CLK_UART4_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- mu: mailbox@30aa0000 { +- compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; +- reg = <0x30aa0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_MU_ROOT>; +- #mbox-cells = <2>; +- }; +- +- usdhc1: mmc@30b40000 { +- compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; +- reg = <0x30b40000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_IPG_ROOT>, +- <&clk IMX8MM_CLK_NAND_USDHC_BUS>, +- <&clk IMX8MM_CLK_USDHC1_ROOT>; +- clock-names = "ipg", "ahb", "per"; +- fsl,tuning-start-tap = <20>; +- fsl,tuning-step= <2>; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usdhc2: mmc@30b50000 { +- compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; +- reg = <0x30b50000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_IPG_ROOT>, +- <&clk IMX8MM_CLK_NAND_USDHC_BUS>, +- <&clk IMX8MM_CLK_USDHC2_ROOT>; +- clock-names = "ipg", "ahb", "per"; +- fsl,tuning-start-tap = <20>; +- fsl,tuning-step= <2>; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usdhc3: mmc@30b60000 { +- compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; +- reg = <0x30b60000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_IPG_ROOT>, +- <&clk IMX8MM_CLK_NAND_USDHC_BUS>, +- <&clk IMX8MM_CLK_USDHC3_ROOT>; +- clock-names = "ipg", "ahb", "per"; +- fsl,tuning-start-tap = <20>; +- fsl,tuning-step= <2>; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- flexspi: spi@30bb0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "nxp,imx8mm-fspi"; +- reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; +- reg-names = "fspi_base", "fspi_mmap"; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, +- <&clk IMX8MM_CLK_QSPI_ROOT>; +- clock-names = "fspi_en", "fspi"; +- status = "disabled"; +- }; +- +- sdma1: dma-controller@30bd0000 { +- compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; +- reg = <0x30bd0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, +- <&clk IMX8MM_CLK_AHB>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; +- }; +- +- fec1: ethernet@30be0000 { +- compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; +- reg = <0x30be0000 0x10000>; +- interrupts = , +- , +- , +- ; +- clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, +- <&clk IMX8MM_CLK_ENET1_ROOT>, +- <&clk IMX8MM_CLK_ENET_TIMER>, +- <&clk IMX8MM_CLK_ENET_REF>, +- <&clk IMX8MM_CLK_ENET_PHY_REF>; +- clock-names = "ipg", "ahb", "ptp", +- "enet_clk_ref", "enet_out"; +- assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, +- <&clk IMX8MM_CLK_ENET_TIMER>, +- <&clk IMX8MM_CLK_ENET_REF>, +- <&clk IMX8MM_CLK_ENET_PHY_REF>; +- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, +- <&clk IMX8MM_SYS_PLL2_100M>, +- <&clk IMX8MM_SYS_PLL2_125M>, +- <&clk IMX8MM_SYS_PLL2_50M>; +- assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; +- fsl,num-tx-queues = <3>; +- fsl,num-rx-queues = <3>; +- nvmem-cells = <&fec_mac_address>; +- nvmem-cell-names = "mac-address"; +- nvmem_macaddr_swap; +- fsl,stop-mode = <&gpr 0x10 3>; +- status = "disabled"; +- }; +- +- }; +- +- aips4: bus@32c00000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- reg = <0x32c00000 0x400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x32c00000 0x32c00000 0x400000>; +- +- usbotg1: usb@32e40000 { +- compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; +- reg = <0x32e40000 0x200>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; +- clock-names = "usb1_ctrl_root_clk"; +- assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; +- assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; +- phys = <&usbphynop1>; +- fsl,usbmisc = <&usbmisc1 0>; +- status = "disabled"; +- }; +- +- usbmisc1: usbmisc@32e40200 { +- compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; +- #index-cells = <1>; +- reg = <0x32e40200 0x200>; +- }; +- +- usbotg2: usb@32e50000 { +- compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; +- reg = <0x32e50000 0x200>; +- interrupts = ; +- clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; +- clock-names = "usb1_ctrl_root_clk"; +- assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; +- assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; +- phys = <&usbphynop2>; +- fsl,usbmisc = <&usbmisc2 0>; +- status = "disabled"; +- }; +- +- usbmisc2: usbmisc@32e50200 { +- compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; +- #index-cells = <1>; +- reg = <0x32e50200 0x200>; +- }; +- +- }; +- +- dma_apbh: dma-controller@33000000 { +- compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; +- reg = <0x33000000 0x2000>; +- interrupts = , +- , +- , +- ; +- interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; +- #dma-cells = <1>; +- dma-channels = <4>; +- clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; +- }; +- +- gpmi: nand-controller@33002000{ +- compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x33002000 0x2000>, <0x33004000 0x4000>; +- reg-names = "gpmi-nand", "bch"; +- interrupts = ; +- interrupt-names = "bch"; +- clocks = <&clk IMX8MM_CLK_NAND_ROOT>, +- <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; +- clock-names = "gpmi_io", "gpmi_bch_apb"; +- dmas = <&dma_apbh 0>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@38800000 { +- compatible = "arm,gic-v3"; +- reg = <0x38800000 0x10000>, /* GIC Dist */ +- <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ +- #interrupt-cells = <3>; +- interrupt-controller; +- interrupts = ; +- }; +- +- ddrc: memory-controller@3d400000 { +- compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; +- reg = <0x3d400000 0x400000>; +- clock-names = "core", "pll", "alt", "apb"; +- clocks = <&clk IMX8MM_CLK_DRAM_CORE>, +- <&clk IMX8MM_DRAM_PLL>, +- <&clk IMX8MM_CLK_DRAM_ALT>, +- <&clk IMX8MM_CLK_DRAM_APB>; +- }; +- +- ddr-pmu@3d800000 { +- compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; +- reg = <0x3d800000 0x400000>; +- interrupts = ; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-beacon-baseboard.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-beacon-baseboard.dtsi +deleted file mode 100644 +index 376ca8ff7213..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-beacon-baseboard.dtsi ++++ /dev/null +@@ -1,307 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2020 Compass Electronics Group, LLC +- */ +- +-/ { +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "gen_led0"; +- gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-1 { +- label = "gen_led1"; +- gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-2 { +- label = "gen_led2"; +- gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led3>; +- label = "heartbeat"; +- gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- reg_audio: regulator-audio { +- compatible = "regulator-fixed"; +- regulator-name = "3v3_aud"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usdhc2_vmmc: regulator-usdhc2 { +- compatible = "regulator-fixed"; +- regulator-name = "vsd_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usb_otg_vbus: regulator-usb { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usb_otg>; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- sound { +- compatible = "fsl,imx-audio-wm8962"; +- model = "wm8962-audio"; +- audio-cpu = <&sai3>; +- audio-codec = <&wm8962>; +- audio-routing = +- "Headphone Jack", "HPOUTL", +- "Headphone Jack", "HPOUTR", +- "Ext Spk", "SPKOUTL", +- "Ext Spk", "SPKOUTR", +- "AMIC", "MICBIAS", +- "IN3R", "AMIC"; +- }; +-}; +- +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_espi2>; +- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- eeprom@0 { +- compatible = "microchip,at25160bn", "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <5000000>; +- spi-cpha; +- spi-cpol; +- pagesize = <32>; +- size = <2048>; +- address-width = <16>; +- }; +-}; +- +-&i2c4 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +- +- pca6416_0: gpio@20 { +- compatible = "nxp,pcal6416"; +- reg = <0x20>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcal6414>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gpio4>; +- interrupts = <27 IRQ_TYPE_LEVEL_LOW>; +- }; +- +- pca6416_1: gpio@21 { +- compatible = "nxp,pcal6416"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gpio4>; +- interrupts = <27 IRQ_TYPE_LEVEL_LOW>; +- }; +- +- wm8962: audio-codec@1a { +- compatible = "wlf,wm8962"; +- reg = <0x1a>; +- clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; +- clock-names = "xclk"; +- DCVDD-supply = <®_audio>; +- DBVDD-supply = <®_audio>; +- AVDD-supply = <®_audio>; +- CPVDD-supply = <®_audio>; +- MICVDD-supply = <®_audio>; +- PLLVDD-supply = <®_audio>; +- SPKVDD1-supply = <®_audio>; +- SPKVDD2-supply = <®_audio>; +- gpio-cfg = < +- 0x0000 /* 0:Default */ +- 0x0000 /* 1:Default */ +- 0x0000 /* 2:FN_DMICCLK */ +- 0x0000 /* 3:Default */ +- 0x0000 /* 4:FN_DMICCDAT */ +- 0x0000 /* 5:Default */ +- >; +- }; +-}; +- +-&easrc { +- fsl,asrc-rate = <48000>; +- status = "okay"; +-}; +- +-&sai3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai3>; +- assigned-clocks = <&clk IMX8MN_CLK_SAI3>; +- assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; +- assigned-clock-rates = <24576000>; +- fsl,sai-mclk-direction-output; +- status = "okay"; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +- +-&uart2 { /* console */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- assigned-clocks = <&clk IMX8MN_CLK_UART3>; +- assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; +- status = "okay"; +-}; +- +-&usbotg1 { +- vbus-supply = <®_usb_otg_vbus>; +- disable-over-current; +- dr_mode="otg"; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>; +- bus-width = <4>; +- vmmc-supply = <®_usdhc2_vmmc>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_espi2: espi2grp { +- fsl,pins = < +- MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 +- MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 +- MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 +- MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 +- MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 +- MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_led3: led3grp { +- fsl,pins = < +- MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41 +- >; +- }; +- +- pinctrl_pcal6414: pcal6414-gpiogrp { +- fsl,pins = < +- MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 +- >; +- }; +- +- pinctrl_reg_usb_otg: reg-otggrp { +- fsl,pins = < +- MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 +- >; +- }; +- +- pinctrl_sai3: sai3grp { +- fsl,pins = < +- MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 +- MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 +- MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 +- MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 +- MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 +- MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 +- MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 +- >; +- }; +- +- pinctrl_usdhc2_gpio: usdhc2gpiogrp { +- fsl,pins = < +- MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 +- MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 +- MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 +- MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 +- MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 +- MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 +- MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 +- MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { +- fsl,pins = < +- MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 +- MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 +- MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 +- MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 +- MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 +- MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 +- MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { +- fsl,pins = < +- MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 +- MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 +- MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 +- MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 +- MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 +- MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 +- MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-beacon-kit.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-beacon-kit.dts +deleted file mode 100644 +index 1392ce02587b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-beacon-kit.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2020 Compass Electronics Group, LLC +- */ +- +-/dts-v1/; +- +-#include "imx8mn.dtsi" +-#include "imx8mn-beacon-som.dtsi" +-#include "imx8mn-beacon-baseboard.dtsi" +- +-/ { +- model = "Beacon EmbeddedWorks i.MX8M Nano Development Kit"; +- compatible = "beacon,imx8mn-beacon-kit", "fsl,imx8mn"; +- +- chosen { +- stdout-path = &uart2; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-beacon-som.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-beacon-som.dtsi +deleted file mode 100644 +index 3b2d627a0342..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-beacon-som.dtsi ++++ /dev/null +@@ -1,473 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2020 Compass Electronics Group, LLC +- */ +- +-/ { +- aliases { +- rtc0 = &rtc; +- rtc1 = &snvs_rtc; +- spi0 = &flexspi; +- }; +- +- usdhc1_pwrseq: usdhc1_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1_gpio>; +- reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; +- clocks = <&osc_32k>; +- clock-names = "ext_clock"; +- post-power-on-delay-ms = <80>; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x0 0x40000000 0 0x80000000>; +- }; +-}; +- +-&A53_0 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_1 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_2 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_3 { +- cpu-supply = <&buck2_reg>; +-}; +- +-/* DDR controller is running LPDDR at 800MHz which requires 0.95V */ +-&a53_opp_table { +- opp-1200000000 { +- opp-microvolt = <950000>; +- }; +-}; +- +-&ddrc { +- operating-points-v2 = <&ddrc_opp_table>; +- +- ddrc_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-25M { +- opp-hz = /bits/ 64 <25000000>; +- }; +- +- opp-100M { +- opp-hz = /bits/ 64 <100000000>; +- }; +- +- opp-800M { +- opp-hz = /bits/ 64 <800000000>; +- }; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- phy-supply = <&buck6_reg>; +- phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +- }; +-}; +- +-&flexspi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexspi>; +- status = "okay"; +- +- flash@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <80000000>; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <4>; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic@4b { +- compatible = "rohm,bd71847"; +- reg = <0x4b>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio1>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- rohm,reset-snvs-powered; +- #clock-cells = <0>; +- clocks = <&osc_32k 0>; +- clock-output-names = "clk-32k-out"; +- +- regulators { +- buck1_reg: BUCK1 { +- regulator-name = "buck1"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "buck2"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- rohm,dvs-run-voltage = <1000000>; +- rohm,dvs-idle-voltage = <900000>; +- }; +- +- buck3_reg: BUCK3 { +- // BUCK5 in datasheet +- regulator-name = "buck3"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck4_reg: BUCK4 { +- // BUCK6 in datasheet +- regulator-name = "buck4"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck5_reg: BUCK5 { +- // BUCK7 in datasheet +- regulator-name = "buck5"; +- regulator-min-microvolt = <1605000>; +- regulator-max-microvolt = <1995000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck6_reg: BUCK6 { +- // BUCK8 in datasheet +- regulator-name = "buck6"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1_reg: LDO1 { +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1600000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "ldo2"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "ldo4"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "ldo6"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- eeprom@50 { +- compatible = "microchip,24c64", "atmel,24c64"; +- pagesize = <32>; +- read-only; /* Manufacturing EEPROM programmed at factory */ +- reg = <0x50>; +- }; +- +- rtc: rtc@51 { +- compatible = "nxp,pcf85263"; +- reg = <0x51>; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- assigned-clocks = <&clk IMX8MN_CLK_UART1>; +- assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; +- device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; +- clocks = <&osc_32k>; +- max-speed = <4000000>; +- clock-names = "extclk"; +- }; +-}; +- +-&usdhc1 { +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- vmmc-supply = <&buck4_reg>; +- vqmmc-supply = <&buck5_reg>; +- bus-width = <4>; +- non-removable; +- cap-power-off-card; +- pm-ignore-notify; +- keep-power-in-suspend; +- mmc-pwrseq = <&usdhc1_pwrseq>; +- status = "okay"; +- +- brcmf: bcrmf@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wlan>; +- interrupt-parent = <&gpio2>; +- interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "host-wake"; +- }; +-}; +- +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 +- MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 +- MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 +- MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_flexspi: flexspigrp { +- fsl,pins = < +- MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 +- MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 +- MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 +- MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 +- MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 +- MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 +- >; +- }; +- +- pinctrl_pmic: pmicirqgrp { +- fsl,pins = < +- MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 +- MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 +- MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 +- MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 +- MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 +- MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 +- MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 +- MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 +- >; +- }; +- +- pinctrl_usdhc1_gpio: usdhc1gpiogrp { +- fsl,pins = < +- MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 +- MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 +- MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 +- MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 +- MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 +- MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { +- fsl,pins = < +- MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 +- MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 +- MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 +- MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 +- MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 +- MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { +- fsl,pins = < +- MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 +- MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 +- MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 +- MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 +- MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 +- MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 +- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 +- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 +- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 +- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 +- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 +- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 +- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 +- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 +- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 +- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { +- fsl,pins = < +- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 +- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 +- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 +- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 +- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 +- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 +- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 +- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 +- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 +- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 +- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { +- fsl,pins = < +- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 +- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 +- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 +- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 +- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 +- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 +- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 +- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 +- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 +- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 +- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 +- >; +- }; +- +- pinctrl_wlan: wlangrp { +- fsl,pins = < +- MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-ddr4-evk.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-ddr4-evk.dts +deleted file mode 100644 +index 7dfee715a2c4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-ddr4-evk.dts ++++ /dev/null +@@ -1,156 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2019 NXP +- */ +- +-/dts-v1/; +- +-#include "imx8mn.dtsi" +-#include "imx8mn-evk.dtsi" +- +-/ { +- model = "NXP i.MX8MNano DDR4 EVK board"; +- compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn"; +-}; +- +-&A53_0 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_1 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_2 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_3 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&ddrc { +- operating-points-v2 = <&ddrc_opp_table>; +- +- ddrc_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-25M { +- opp-hz = /bits/ 64 <25000000>; +- }; +- +- opp-100M { +- opp-hz = /bits/ 64 <100000000>; +- }; +- +- opp-600M { +- opp-hz = /bits/ 64 <600000000>; +- }; +- }; +-}; +- +-&i2c1 { +- pmic@4b { +- compatible = "rohm,bd71847"; +- reg = <0x4b>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio1>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- rohm,reset-snvs-powered; +- +- regulators { +- buck1_reg: BUCK1 { +- regulator-name = "buck1"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "buck2"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- }; +- +- buck3_reg: BUCK3 { +- // BUCK5 in datasheet +- regulator-name = "buck3"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- }; +- +- buck4_reg: BUCK4 { +- // BUCK6 in datasheet +- regulator-name = "buck4"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck5_reg: BUCK5 { +- // BUCK7 in datasheet +- regulator-name = "buck5"; +- regulator-min-microvolt = <1605000>; +- regulator-max-microvolt = <1995000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck6_reg: BUCK6 { +- // BUCK8 in datasheet +- regulator-name = "buck6"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1_reg: LDO1 { +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1600000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "ldo2"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "ldo4"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "ldo6"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-evk.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-evk.dts +deleted file mode 100644 +index b4225cfcb6d9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-evk.dts ++++ /dev/null +@@ -1,128 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2019 NXP +- */ +- +-/dts-v1/; +- +-#include "imx8mn.dtsi" +-#include "imx8mn-evk.dtsi" +-#include +- +-/ { +- model = "NXP i.MX8MNano EVK board"; +- compatible = "fsl,imx8mn-evk", "fsl,imx8mn"; +-}; +- +-&A53_0 { +- cpu-supply = <&buck2>; +-}; +- +-&A53_1 { +- cpu-supply = <&buck2>; +-}; +- +-&A53_2 { +- cpu-supply = <&buck2>; +-}; +- +-&A53_3 { +- cpu-supply = <&buck2>; +-}; +- +-&i2c1 { +- pmic: pmic@25 { +- compatible = "nxp,pca9450b"; +- reg = <0x25>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio1>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- +- regulators { +- buck1: BUCK1{ +- regulator-name = "BUCK1"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <2187500>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <3125>; +- }; +- +- buck2: BUCK2 { +- regulator-name = "BUCK2"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <2187500>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <3125>; +- nxp,dvs-run-voltage = <950000>; +- nxp,dvs-standby-voltage = <850000>; +- }; +- +- buck4: BUCK4{ +- regulator-name = "BUCK4"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <3400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck5: BUCK5{ +- regulator-name = "BUCK5"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <3400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck6: BUCK6 { +- regulator-name = "BUCK6"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <3400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1: LDO1 { +- regulator-name = "LDO1"; +- regulator-min-microvolt = <1600000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo2: LDO2 { +- regulator-name = "LDO2"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo3: LDO3 { +- regulator-name = "LDO3"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo4: LDO4 { +- regulator-name = "LDO4"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo5: LDO5 { +- regulator-name = "LDO5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-evk.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-evk.dtsi +deleted file mode 100644 +index 85e65f8719ea..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-evk.dtsi ++++ /dev/null +@@ -1,436 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2019 NXP +- */ +- +-#include +-#include "imx8mn.dtsi" +- +-/ { +- chosen { +- stdout-path = &uart2; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_led>; +- +- status { +- label = "yellow:status"; +- gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x0 0x40000000 0 0x80000000>; +- }; +- +- reg_usdhc2_vmmc: regulator-usdhc2 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; +- regulator-name = "VSD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ir>; +- linux,autosuspend-period = <125>; +- }; +- +- wm8524: audio-codec { +- #sound-dai-cells = <0>; +- compatible = "wlf,wm8524"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_wlf>; +- wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; +- clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; +- clock-names = "mclk"; +- }; +- +- sound-wm8524 { +- compatible = "fsl,imx-audio-wm8524"; +- model = "wm8524-audio"; +- audio-cpu = <&sai3>; +- audio-codec = <&wm8524>; +- audio-asrc = <&easrc>; +- audio-routing = +- "Line Out Jack", "LINEVOUTL", +- "Line Out Jack", "LINEVOUTR"; +- }; +- +- sound-spdif { +- compatible = "fsl,imx-audio-spdif"; +- model = "imx-spdif"; +- spdif-controller = <&spdif1>; +- spdif-out; +- spdif-in; +- }; +-}; +- +-&easrc { +- fsl,asrc-rate = <48000>; +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- ptn5110: tcpc@50 { +- compatible = "nxp,ptn5110"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_typec1>; +- reg = <0x50>; +- interrupt-parent = <&gpio2>; +- interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +- status = "okay"; +- +- port { +- typec1_dr_sw: endpoint { +- remote-endpoint = <&usb1_drd_sw>; +- }; +- }; +- +- typec1_con: connector { +- compatible = "usb-c-connector"; +- label = "USB-C"; +- power-role = "dual"; +- data-role = "dual"; +- try-power-role = "sink"; +- source-pdos = ; +- sink-pdos = ; +- op-sink-microwatt = <15000000>; +- self-powered; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- pca6416: gpio@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&sai3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai3>; +- assigned-clocks = <&clk IMX8MN_CLK_SAI3>; +- assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; +- assigned-clock-rates = <24576000>; +- fsl,sai-mclk-direction-output; +- status = "okay"; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +- +-&spdif1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spdif1>; +- assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>; +- assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; +- assigned-clock-rates = <24576000>; +- status = "okay"; +-}; +- +-&uart2 { /* console */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usbotg1 { +- dr_mode = "otg"; +- hnp-disable; +- srp-disable; +- adp-disable; +- usb-role-switch; +- disable-over-current; +- samsung,picophy-pre-emp-curr-control = <3>; +- samsung,picophy-dc-vol-level-adjust = <7>; +- status = "okay"; +- +- port { +- usb1_drd_sw: endpoint { +- remote-endpoint = <&typec1_dr_sw>; +- }; +- }; +-}; +- +-&usdhc2 { +- assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +- cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- vmmc-supply = <®_usdhc2_vmmc>; +- status = "okay"; +-}; +- +-&usdhc3 { +- assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; +- assigned-clock-rates = <400000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 +- MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 +- >; +- }; +- +- pinctrl_gpio_led: gpioledgrp { +- fsl,pins = < +- MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 +- >; +- }; +- +- pinctrl_gpio_wlf: gpiowlfgrp { +- fsl,pins = < +- MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 +- >; +- }; +- +- pinctrl_ir: irgrp { +- fsl,pins = < +- MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 +- MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 +- MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 +- MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_pmic: pmicirqgrp { +- fsl,pins = < +- MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 +- >; +- }; +- +- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { +- fsl,pins = < +- MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 +- >; +- }; +- +- pinctrl_sai3: sai3grp { +- fsl,pins = < +- MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 +- MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 +- MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 +- MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 +- >; +- }; +- +- pinctrl_spdif1: spdif1grp { +- fsl,pins = < +- MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 +- MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 +- >; +- }; +- +- pinctrl_typec1: typec1grp { +- fsl,pins = < +- MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 +- MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_usdhc2_gpio: usdhc2gpiogrp { +- fsl,pins = < +- MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 +- MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 +- MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 +- MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 +- MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 +- MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 +- MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { +- fsl,pins = < +- MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 +- MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 +- MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 +- MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 +- MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 +- MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 +- MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { +- fsl,pins = < +- MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 +- MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 +- MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 +- MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 +- MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 +- MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 +- MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 +- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 +- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 +- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 +- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 +- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 +- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 +- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 +- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 +- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 +- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { +- fsl,pins = < +- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 +- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 +- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 +- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 +- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 +- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 +- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 +- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 +- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 +- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 +- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { +- fsl,pins = < +- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 +- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 +- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 +- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 +- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 +- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 +- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 +- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 +- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 +- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 +- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-pinfunc.h b/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-pinfunc.h +deleted file mode 100644 +index faf1e69e742b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-pinfunc.h ++++ /dev/null +@@ -1,646 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright 2018-2019 NXP +- */ +- +-#ifndef __DTS_IMX8MN_PINFUNC_H +-#define __DTS_IMX8MN_PINFUNC_H +- +-/* +- * The pin function ID is a tuple of +- * +- */ +- +-#define MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3 +-#define MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3 +-#define MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x4BC 0x5 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x4C0 0x1 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO08_PWM1_OUT 0x048 0x2B0 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO09_PWM2_OUT 0x04C 0x2B4 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x04C 0x2B4 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO10_PWM3_OUT 0x050 0x2B8 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO11_PWM2_OUT 0x054 0x2BC 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x054 0x2BC 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 +-#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x060 0x2C8 0x598 0x4 0x2 +-#define MX8MN_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO15_USDHC3_WP 0x064 0x2CC 0x5B8 0x4 0x2 +-#define MX8MN_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_ENET_MDC_SAI6_TX_DATA0 0x068 0x2D0 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_ENET_MDC_PDM_BIT_STREAM3 0x068 0x2D0 0x540 0x3 0x1 +-#define MX8MN_IOMUXC_ENET_MDC_SPDIF1_OUT 0x068 0x2D0 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ENET_MDC_USDHC3_STROBE 0x068 0x2D0 0x59C 0x6 0x1 +-#define MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 +-#define MX8MN_IOMUXC_ENET_MDIO_SAI6_TX_SYNC 0x06C 0x2D4 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_ENET_MDIO_PDM_BIT_STREAM2 0x06C 0x2D4 0x53C 0x3 0x1 +-#define MX8MN_IOMUXC_ENET_MDIO_SPDIF1_IN 0x06C 0x2D4 0x5CC 0x4 0x1 +-#define MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ENET_MDIO_USDHC3_DATA5 0x06C 0x2D4 0x550 0x6 0x1 +-#define MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_ENET_TD3_SAI6_TX_BCLK 0x070 0x2D8 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_ENET_TD3_PDM_BIT_STREAM1 0x070 0x2D8 0x538 0x3 0x1 +-#define MX8MN_IOMUXC_ENET_TD3_SPDIF1_EXT_CLK 0x070 0x2D8 0x568 0x4 0x1 +-#define MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ENET_TD3_USDHC3_DATA6 0x070 0x2D8 0x584 0x6 0x1 +-#define MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x5A4 0x1 0x0 +-#define MX8MN_IOMUXC_ENET_TD2_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x074 0x2DC 0x5A4 0x1 0x0 +-#define MX8MN_IOMUXC_ENET_TD2_SAI6_RX_DATA0 0x074 0x2DC 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_ENET_TD2_PDM_BIT_STREAM3 0x074 0x2DC 0x540 0x3 0x2 +-#define MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ENET_TD2_USDHC3_DATA7 0x074 0x2DC 0x54C 0x6 0x1 +-#define MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_ENET_TD1_SAI6_RX_SYNC 0x078 0x2E0 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_ENET_TD1_PDM_BIT_STREAM2 0x078 0x2E0 0x53C 0x3 0x2 +-#define MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ENET_TD1_USDHC3_CD_B 0x078 0x2E0 0x598 0x6 0x3 +-#define MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_ENET_TD0_SAI6_RX_BCLK 0x07C 0x2E4 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_ENET_TD0_PDM_BIT_STREAM1 0x07C 0x2E4 0x538 0x3 0x2 +-#define MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ENET_TD0_USDHC3_WP 0x07C 0x2E4 0x5B8 0x6 0x3 +-#define MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_ENET_TX_CTL_SAI6_MCLK 0x080 0x2E8 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ENET_TX_CTL_USDHC3_DATA0 0x080 0x2E8 0x5B4 0x6 0x1 +-#define MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_ENET_TXC_SAI7_TX_DATA0 0x084 0x2EC 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ENET_TXC_USDHC3_DATA1 0x084 0x2EC 0x5B0 0x6 0x1 +-#define MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x574 0x0 0x0 +-#define MX8MN_IOMUXC_ENET_RX_CTL_SAI7_TX_SYNC 0x088 0x2F0 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM3 0x088 0x2F0 0x540 0x3 0x3 +-#define MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ENET_RX_CTL_USDHC3_DATA2 0x088 0x2F0 0x5E4 0x6 0x1 +-#define MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x5C8 0x1 0x0 +-#define MX8MN_IOMUXC_ENET_RXC_SAI7_TX_BCLK 0x08C 0x2F4 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_ENET_RXC_PDM_BIT_STREAM2 0x08C 0x2F4 0x53C 0x3 0x3 +-#define MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ENET_RXC_USDHC3_DATA3 0x08C 0x2F4 0x5E0 0x6 0x1 +-#define MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x57C 0x0 0x0 +-#define MX8MN_IOMUXC_ENET_RD0_SAI7_RX_DATA0 0x090 0x2F8 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_ENET_RD0_PDM_BIT_STREAM1 0x090 0x2F8 0x538 0x3 0x3 +-#define MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ENET_RD0_USDHC3_DATA4 0x090 0x2F8 0x558 0x6 0x1 +-#define MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x554 0x0 0x0 +-#define MX8MN_IOMUXC_ENET_RD1_SAI7_RX_SYNC 0x094 0x2FC 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_ENET_RD1_PDM_BIT_STREAM0 0x094 0x2FC 0x534 0x3 0x1 +-#define MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ENET_RD1_USDHC3_RESET_B 0x094 0x2FC 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_ENET_RD2_SAI7_RX_BCLK 0x098 0x300 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_ENET_RD2_PDM_CLK 0x098 0x300 0x000 0x3 0x0 +-#define MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ENET_RD2_USDHC3_CLK 0x098 0x300 0x5A0 0x6 0x1 +-#define MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_ENET_RD3_SAI7_MCLK 0x09C 0x304 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_ENET_RD3_SPDIF1_IN 0x09C 0x304 0x5CC 0x3 0x5 +-#define MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ENET_RD3_USDHC3_CMD 0x09C 0x304 0x5DC 0x6 0x1 +-#define MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD1_CLK_ENET1_MDC 0x0A0 0x308 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_SD1_CLK_UART1_DCE_TX 0x0A0 0x308 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SD1_CLK_UART1_DTE_RX 0x0A0 0x308 0x4F4 0x4 0x4 +-#define MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD1_CMD_ENET1_MDIO 0x0A4 0x30C 0x4C0 0x1 0x3 +-#define MX8MN_IOMUXC_SD1_CMD_UART1_DCE_RX 0x0A4 0x30C 0x4F4 0x4 0x5 +-#define MX8MN_IOMUXC_SD1_CMD_UART1_DTE_TX 0x0A4 0x30C 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD1_DATA0_ENET1_RGMII_TD1 0x0A8 0x310 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_SD1_DATA0_UART1_DCE_RTS_B 0x0A8 0x310 0x4F0 0x4 0x4 +-#define MX8MN_IOMUXC_SD1_DATA0_UART1_DTE_CTS_B 0x0A8 0x310 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD1_DATA1_ENET1_RGMII_TD0 0x0AC 0x314 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_SD1_DATA1_UART1_DCE_CTS_B 0x0AC 0x314 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SD1_DATA1_UART1_DTE_RTS_B 0x0AC 0x314 0x4F0 0x4 0x5 +-#define MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD1_DATA2_ENET1_RGMII_RD0 0x0B0 0x318 0x57C 0x1 0x1 +-#define MX8MN_IOMUXC_SD1_DATA2_UART2_DCE_TX 0x0B0 0x318 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SD1_DATA2_UART2_DTE_RX 0x0B0 0x318 0x4FC 0x4 0x4 +-#define MX8MN_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD1_DATA3_ENET1_RGMII_RD1 0x0B4 0x31C 0x554 0x1 0x1 +-#define MX8MN_IOMUXC_SD1_DATA3_UART2_DCE_RX 0x0B4 0x31C 0x4FC 0x4 0x5 +-#define MX8MN_IOMUXC_SD1_DATA3_UART2_DTE_TX 0x0B4 0x31C 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD1_DATA4_ENET1_RGMII_TX_CTL 0x0B8 0x320 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_SD1_DATA4_I2C1_SCL 0x0B8 0x320 0x55C 0x3 0x1 +-#define MX8MN_IOMUXC_SD1_DATA4_UART2_DCE_RTS_B 0x0B8 0x320 0x4F8 0x4 0x4 +-#define MX8MN_IOMUXC_SD1_DATA4_UART2_DTE_CTS_B 0x0B8 0x320 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD1_DATA5_ENET1_TX_ER 0x0BC 0x324 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_SD1_DATA5_I2C1_SDA 0x0BC 0x324 0x56C 0x3 0x1 +-#define MX8MN_IOMUXC_SD1_DATA5_UART2_DCE_CTS_B 0x0BC 0x324 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SD1_DATA5_UART2_DTE_RTS_B 0x0BC 0x324 0x4F8 0x4 0x5 +-#define MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD1_DATA6_ENET1_RGMII_RX_CTL 0x0C0 0x328 0x574 0x1 0x1 +-#define MX8MN_IOMUXC_SD1_DATA6_I2C2_SCL 0x0C0 0x328 0x5D0 0x3 0x1 +-#define MX8MN_IOMUXC_SD1_DATA6_UART3_DCE_TX 0x0C0 0x328 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SD1_DATA6_UART3_DTE_RX 0x0C0 0x328 0x504 0x4 0x4 +-#define MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD1_DATA7_ENET1_RX_ER 0x0C4 0x32C 0x5C8 0x1 0x1 +-#define MX8MN_IOMUXC_SD1_DATA7_I2C2_SDA 0x0C4 0x32C 0x560 0x3 0x1 +-#define MX8MN_IOMUXC_SD1_DATA7_UART3_DCE_RX 0x0C4 0x32C 0x504 0x4 0x5 +-#define MX8MN_IOMUXC_SD1_DATA7_UART3_DTE_TX 0x0C4 0x32C 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD1_RESET_B_ENET1_TX_CLK 0x0C8 0x330 0x5A4 0x1 0x1 +-#define MX8MN_IOMUXC_SD1_RESET_B_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x0C8 0x330 0x5A4 0x1 0x0 +-#define MX8MN_IOMUXC_SD1_RESET_B_I2C3_SCL 0x0C8 0x330 0x588 0x3 0x1 +-#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DCE_RTS_B 0x0C8 0x330 0x500 0x4 0x2 +-#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DTE_CTS_B 0x0C8 0x330 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD1_STROBE_I2C3_SDA 0x0CC 0x334 0x5BC 0x3 0x1 +-#define MX8MN_IOMUXC_SD1_STROBE_UART3_DCE_CTS_B 0x0CC 0x334 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SD1_STROBE_UART3_DTE_RTS_B 0x0CC 0x334 0x500 0x4 0x3 +-#define MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD2_CD_B_CCMSRCGPCMIX_TESTER_ACK 0x0D0 0x338 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD2_CLK_SAI5_RX_SYNC 0x0D4 0x33C 0x4E4 0x1 0x1 +-#define MX8MN_IOMUXC_SD2_CLK_ECSPI2_SCLK 0x0D4 0x33C 0x580 0x2 0x1 +-#define MX8MN_IOMUXC_SD2_CLK_UART4_DCE_RX 0x0D4 0x33C 0x50C 0x3 0x4 +-#define MX8MN_IOMUXC_SD2_CLK_UART4_DTE_TX 0x0D4 0x33C 0x000 0x3 0x0 +-#define MX8MN_IOMUXC_SD2_CLK_SAI5_MCLK 0x0D4 0x33C 0x594 0x4 0x1 +-#define MX8MN_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD2_CMD_SAI5_RX_BCLK 0x0D8 0x340 0x4D0 0x1 0x1 +-#define MX8MN_IOMUXC_SD2_CMD_ECSPI2_MOSI 0x0D8 0x340 0x590 0x2 0x1 +-#define MX8MN_IOMUXC_SD2_CMD_UART4_DCE_TX 0x0D8 0x340 0x000 0x3 0x0 +-#define MX8MN_IOMUXC_SD2_CMD_UART4_DTE_RX 0x0D8 0x340 0x50C 0x3 0x5 +-#define MX8MN_IOMUXC_SD2_CMD_PDM_CLK 0x0D8 0x340 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD2_DATA0_SAI5_RX_DATA0 0x0DC 0x344 0x4D4 0x1 0x1 +-#define MX8MN_IOMUXC_SD2_DATA0_I2C4_SDA 0x0DC 0x344 0x58C 0x2 0x1 +-#define MX8MN_IOMUXC_SD2_DATA0_UART2_DCE_RX 0x0DC 0x344 0x4FC 0x3 0x6 +-#define MX8MN_IOMUXC_SD2_DATA0_UART2_DTE_TX 0x0DC 0x344 0x000 0x3 0x0 +-#define MX8MN_IOMUXC_SD2_DATA0_PDM_BIT_STREAM0 0x0DC 0x344 0x534 0x4 0x2 +-#define MX8MN_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD2_DATA1_SAI5_TX_SYNC 0x0E0 0x348 0x4EC 0x1 0x1 +-#define MX8MN_IOMUXC_SD2_DATA1_I2C4_SCL 0x0E0 0x348 0x5D4 0x2 0x1 +-#define MX8MN_IOMUXC_SD2_DATA1_UART2_DCE_TX 0x0E0 0x348 0x000 0x3 0x0 +-#define MX8MN_IOMUXC_SD2_DATA1_UART2_DTE_RX 0x0E0 0x348 0x4FC 0x3 0x7 +-#define MX8MN_IOMUXC_SD2_DATA1_PDM_BIT_STREAM1 0x0E0 0x348 0x538 0x4 0x4 +-#define MX8MN_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD2_DATA2_SAI5_TX_BCLK 0x0E4 0x34C 0x4E8 0x1 0x1 +-#define MX8MN_IOMUXC_SD2_DATA2_ECSPI2_SS0 0x0E4 0x34C 0x570 0x2 0x2 +-#define MX8MN_IOMUXC_SD2_DATA2_SPDIF1_OUT 0x0E4 0x34C 0x000 0x3 0x0 +-#define MX8MN_IOMUXC_SD2_DATA2_PDM_BIT_STREAM2 0x0E4 0x34C 0x53C 0x4 0x4 +-#define MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD2_DATA3_SAI5_TX_DATA0 0x0E8 0x350 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_SD2_DATA3_ECSPI2_MISO 0x0E8 0x350 0x578 0x2 0x1 +-#define MX8MN_IOMUXC_SD2_DATA3_SPDIF1_IN 0x0E8 0x350 0x5CC 0x3 0x2 +-#define MX8MN_IOMUXC_SD2_DATA3_PDM_BIT_STREAM3 0x0E8 0x350 0x540 0x4 0x4 +-#define MX8MN_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SD2_WP_CORESIGHT_EVENTI 0x0F0 0x358 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_NAND_ALE_PDM_BIT_STREAM0 0x0F4 0x35C 0x534 0x3 0x3 +-#define MX8MN_IOMUXC_NAND_ALE_UART3_DCE_RX 0x0F4 0x35C 0x504 0x4 0x6 +-#define MX8MN_IOMUXC_NAND_ALE_UART3_DTE_TX 0x0F4 0x35C 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK 0x0F4 0x35C 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_NAND_CE0_B_PDM_BIT_STREAM1 0x0F8 0x360 0x538 0x3 0x5 +-#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DCE_TX 0x0F8 0x360 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DTE_RX 0x0F8 0x360 0x504 0x4 0x7 +-#define MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL 0x0F8 0x360 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x0FC 0x364 0x59C 0x2 0x0 +-#define MX8MN_IOMUXC_NAND_CE1_B_PDM_BIT_STREAM0 0x0FC 0x364 0x534 0x3 0x4 +-#define MX8MN_IOMUXC_NAND_CE1_B_I2C4_SCL 0x0FC 0x364 0x5D4 0x4 0x2 +-#define MX8MN_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_NAND_CE1_B_CORESIGHT_TRACE0 0x0FC 0x364 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x550 0x2 0x0 +-#define MX8MN_IOMUXC_NAND_CE2_B_PDM_BIT_STREAM1 0x100 0x368 0x538 0x3 0x6 +-#define MX8MN_IOMUXC_NAND_CE2_B_I2C4_SDA 0x100 0x368 0x58C 0x4 0x2 +-#define MX8MN_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_NAND_CE2_B_CORESIGHT_TRACE1 0x100 0x368 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x104 0x36C 0x584 0x2 0x0 +-#define MX8MN_IOMUXC_NAND_CE3_B_PDM_BIT_STREAM2 0x104 0x36C 0x53C 0x3 0x5 +-#define MX8MN_IOMUXC_NAND_CE3_B_I2C3_SDA 0x104 0x36C 0x5BC 0x4 0x2 +-#define MX8MN_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_NAND_CE3_B_CORESIGHT_TRACE2 0x104 0x36C 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x108 0x370 0x54C 0x2 0x0 +-#define MX8MN_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_NAND_CLE_CORESIGHT_TRACE3 0x108 0x370 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_NAND_DATA00_PDM_BIT_STREAM2 0x10C 0x374 0x53C 0x3 0x6 +-#define MX8MN_IOMUXC_NAND_DATA00_UART4_DCE_RX 0x10C 0x374 0x50C 0x4 0x6 +-#define MX8MN_IOMUXC_NAND_DATA00_UART4_DTE_TX 0x10C 0x374 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_NAND_DATA00_CORESIGHT_TRACE4 0x10C 0x374 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_NAND_DATA01_PDM_BIT_STREAM3 0x110 0x378 0x540 0x3 0x5 +-#define MX8MN_IOMUXC_NAND_DATA01_UART4_DCE_TX 0x110 0x378 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_NAND_DATA01_UART4_DTE_RX 0x110 0x378 0x50C 0x4 0x7 +-#define MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_NAND_DATA01_CORESIGHT_TRACE5 0x110 0x378 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_NAND_DATA02_USDHC3_CD_B 0x114 0x37C 0x598 0x2 0x0 +-#define MX8MN_IOMUXC_NAND_DATA02_I2C4_SDA 0x114 0x37C 0x58C 0x4 0x3 +-#define MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_NAND_DATA02_CORESIGHT_TRACE6 0x114 0x37C 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_NAND_DATA03_USDHC3_WP 0x118 0x380 0x5B8 0x2 0x0 +-#define MX8MN_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_NAND_DATA03_CORESIGHT_TRACE7 0x118 0x380 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x11C 0x384 0x5B4 0x2 0x0 +-#define MX8MN_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_NAND_DATA04_CORESIGHT_TRACE8 0x11C 0x384 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x120 0x388 0x5B0 0x2 0x0 +-#define MX8MN_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_NAND_DATA05_CORESIGHT_TRACE9 0x120 0x388 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x124 0x38C 0x5E4 0x2 0x0 +-#define MX8MN_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_NAND_DATA06_CORESIGHT_TRACE10 0x124 0x38C 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x5E0 0x2 0x0 +-#define MX8MN_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_NAND_DATA07_CORESIGHT_TRACE11 0x128 0x390 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_NAND_DQS_PDM_CLK 0x12C 0x394 0x000 0x3 0x0 +-#define MX8MN_IOMUXC_NAND_DQS_I2C3_SCL 0x12C 0x394 0x588 0x4 0x2 +-#define MX8MN_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_NAND_DQS_CORESIGHT_TRACE12 0x12C 0x394 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x130 0x398 0x558 0x2 0x0 +-#define MX8MN_IOMUXC_NAND_RE_B_PDM_BIT_STREAM1 0x130 0x398 0x538 0x3 0x7 +-#define MX8MN_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_NAND_RE_B_CORESIGHT_TRACE13 0x130 0x398 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x134 0x39C 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_NAND_READY_B_PDM_BIT_STREAM3 0x134 0x39C 0x540 0x3 0x6 +-#define MX8MN_IOMUXC_NAND_READY_B_I2C3_SCL 0x134 0x39C 0x588 0x4 0x3 +-#define MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_NAND_READY_B_CORESIGHT_TRACE14 0x134 0x39C 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x138 0x3A0 0x5A0 0x2 0x0 +-#define MX8MN_IOMUXC_NAND_WE_B_I2C3_SDA 0x138 0x3A0 0x5BC 0x4 0x3 +-#define MX8MN_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_NAND_WE_B_CORESIGHT_TRACE15 0x138 0x3A0 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x13C 0x3A4 0x5DC 0x2 0x0 +-#define MX8MN_IOMUXC_NAND_WP_B_I2C4_SDA 0x13C 0x3A4 0x58C 0x4 0x4 +-#define MX8MN_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_NAND_WP_B_CORESIGHT_EVENTO 0x13C 0x3A4 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 +-#define MX8MN_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 +-#define MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0x144 0x3AC 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 +-#define MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x148 0x3B0 0x534 0x4 0x0 +-#define MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 +-#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 +-#define MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x14C 0x3B4 0x538 0x4 0x0 +-#define MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 +-#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 +-#define MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x150 0x3B8 0x53C 0x4 0x0 +-#define MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 +-#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 +-#define MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x154 0x3BC 0x540 0x4 0x0 +-#define MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x594 0x0 0x0 +-#define MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 +-#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x1B0 0x418 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x1B0 0x418 0x5AC 0x3 0x0 +-#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1B0 0x418 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DTE_RX 0x1B0 0x418 0x4F4 0x4 0x2 +-#define MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI2_RXFS_PDM_BIT_STREAM2 0x1B0 0x418 0x53C 0x6 0x7 +-#define MX8MN_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 +-#define MX8MN_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1B4 0x41C 0x4F4 0x4 0x3 +-#define MX8MN_IOMUXC_SAI2_RXC_UART1_DTE_TX 0x1B4 0x41C 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI2_RXC_PDM_BIT_STREAM1 0x1B4 0x41C 0x538 0x6 0x8 +-#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_TX_DATA1 0x1B8 0x420 0x000 0x3 0x0 +-#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x1B8 0x420 0x4F0 0x4 0x2 +-#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 0x1B8 0x420 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI2_RXD0_PDM_BIT_STREAM3 0x1B8 0x420 0x540 0x6 0x7 +-#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x1BC 0x424 0x000 0x3 0x0 +-#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x1BC 0x424 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 0x1BC 0x424 0x4F0 0x4 0x3 +-#define MX8MN_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI2_TXFS_PDM_BIT_STREAM2 0x1BC 0x424 0x53C 0x6 0x8 +-#define MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI2_TXC_PDM_BIT_STREAM1 0x1C0 0x428 0x538 0x6 0x9 +-#define MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI2_TXD0_CCMSRCGPCMIX_BOOT_MODE4 0x1C4 0x42C 0x540 0x6 0x8 +-#define MX8MN_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x594 0x1 0x2 +-#define MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI2_MCLK_SAI3_MCLK 0x1C8 0x430 0x5C0 0x6 0x1 +-#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x5F0 0x1 0x0 +-#define MX8MN_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 +-#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x1CC 0x434 0x000 0x3 0x0 +-#define MX8MN_IOMUXC_SAI3_RXFS_SPDIF1_IN 0x1CC 0x434 0x5CC 0x4 0x3 +-#define MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI3_RXFS_PDM_BIT_STREAM0 0x1CC 0x434 0x534 0x6 0x5 +-#define MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x5E8 0x1 0x0 +-#define MX8MN_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 +-#define MX8MN_IOMUXC_SAI3_RXC_SAI2_RX_DATA1 0x1D0 0x438 0x5AC 0x3 0x2 +-#define MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1D0 0x438 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x1D0 0x438 0x4F8 0x4 0x2 +-#define MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI3_RXC_PDM_CLK 0x1D0 0x438 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 +-#define MX8MN_IOMUXC_SAI3_RXD_SAI3_TX_DATA1 0x1D4 0x43C 0x000 0x3 0x0 +-#define MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1D4 0x43C 0x4F8 0x4 0x3 +-#define MX8MN_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x1D4 0x43C 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI3_RXD_PDM_BIT_STREAM1 0x1D4 0x43C 0x538 0x6 0x10 +-#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x5EC 0x1 0x0 +-#define MX8MN_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x1 +-#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x1D8 0x440 0x000 0x3 0x0 +-#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4FC 0x4 0x2 +-#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI3_TXFS_PDM_BIT_STREAM3 0x1D8 0x440 0x540 0x6 0x9 +-#define MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x1 +-#define MX8MN_IOMUXC_SAI3_TXC_SAI2_TX_DATA1 0x1DC 0x444 0x000 0x3 0x0 +-#define MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4FC 0x4 0x3 +-#define MX8MN_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI3_TXC_PDM_BIT_STREAM2 0x1DC 0x444 0x53C 0x6 0x9 +-#define MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x1 +-#define MX8MN_IOMUXC_SAI3_TXD_SPDIF1_EXT_CLK 0x1E0 0x448 0x568 0x4 0x2 +-#define MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI3_TXD_CCMSRCGPCMIX_BOOT_MODE5 0x1E0 0x448 0x000 0x6 0x0 +-#define MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x5C0 0x0 0x0 +-#define MX8MN_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x594 0x2 0x3 +-#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_OUT 0x1E4 0x44C 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_IN 0x1E4 0x44C 0x5CC 0x6 0x4 +-#define MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x5CC 0x0 0x0 +-#define MX8MN_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x568 0x0 0x0 +-#define MX8MN_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x5D8 0x0 0x0 +-#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 +-#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_ECSPI1_SCLK_I2C1_SCL 0x1F4 0x45C 0x55C 0x2 0x2 +-#define MX8MN_IOMUXC_ECSPI1_SCLK_SAI5_RX_SYNC 0x1F4 0x45C 0x4DC 0x3 0x2 +-#define MX8MN_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x5A8 0x0 0x0 +-#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 +-#define MX8MN_IOMUXC_ECSPI1_MOSI_I2C1_SDA 0x1F8 0x460 0x56C 0x2 0x2 +-#define MX8MN_IOMUXC_ECSPI1_MOSI_SAI5_RX_BCLK 0x1F8 0x460 0x4D0 0x3 0x3 +-#define MX8MN_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x5C4 0x0 0x0 +-#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 +-#define MX8MN_IOMUXC_ECSPI1_MISO_I2C2_SCL 0x1FC 0x464 0x5D0 0x2 0x2 +-#define MX8MN_IOMUXC_ECSPI1_MISO_SAI5_RX_DATA0 0x1FC 0x464 0x4D4 0x3 0x3 +-#define MX8MN_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x564 0x0 0x0 +-#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 +-#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_ECSPI1_SS0_I2C2_SDA 0x200 0x468 0x560 0x2 0x2 +-#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_RX_DATA1 0x200 0x468 0x4D8 0x3 0x2 +-#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_TX_SYNC 0x200 0x468 0x4EC 0x4 0x3 +-#define MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x580 0x0 0x0 +-#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 +-#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_ECSPI2_SCLK_I2C3_SCL 0x204 0x46C 0x588 0x2 0x4 +-#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_RX_DATA2 0x204 0x46C 0x000 0x3 0x0 +-#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_TX_BCLK 0x204 0x46C 0x4E8 0x4 0x3 +-#define MX8MN_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x590 0x0 0x0 +-#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 +-#define MX8MN_IOMUXC_ECSPI2_MOSI_I2C3_SDA 0x208 0x470 0x5BC 0x2 0x4 +-#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_RX_DATA3 0x208 0x470 0x4E0 0x3 0x2 +-#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_TX_DATA0 0x208 0x470 0x000 0x4 0x0 +-#define MX8MN_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x578 0x0 0x0 +-#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 +-#define MX8MN_IOMUXC_ECSPI2_MISO_I2C4_SCL 0x20C 0x474 0x5D4 0x2 0x3 +-#define MX8MN_IOMUXC_ECSPI2_MISO_SAI5_MCLK 0x20C 0x474 0x594 0x3 0x4 +-#define MX8MN_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x570 0x0 0x0 +-#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 +-#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_ECSPI2_SS0_I2C4_SDA 0x210 0x478 0x58C 0x2 0x5 +-#define MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x55C 0x0 0x0 +-#define MX8MN_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_I2C1_SCL_ECSPI1_SCLK 0x214 0x47C 0x5D8 0x3 0x1 +-#define MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x56C 0x0 0x0 +-#define MX8MN_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 +-#define MX8MN_IOMUXC_I2C1_SDA_ECSPI1_MOSI 0x218 0x480 0x5A8 0x3 0x1 +-#define MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x5D0 0x0 0x0 +-#define MX8MN_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_I2C2_SCL_USDHC3_CD_B 0x21C 0x484 0x598 0x2 0x1 +-#define MX8MN_IOMUXC_I2C2_SCL_ECSPI1_MISO 0x21C 0x484 0x5C4 0x3 0x1 +-#define MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x560 0x0 0x0 +-#define MX8MN_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_I2C2_SDA_USDHC3_WP 0x220 0x488 0x5B8 0x2 0x1 +-#define MX8MN_IOMUXC_I2C2_SDA_ECSPI1_SS0 0x220 0x488 0x564 0x3 0x1 +-#define MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x588 0x0 0x0 +-#define MX8MN_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_I2C3_SCL_ECSPI2_SCLK 0x224 0x48C 0x580 0x3 0x2 +-#define MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x5BC 0x0 0x0 +-#define MX8MN_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_I2C3_SDA_ECSPI2_MOSI 0x228 0x490 0x590 0x3 0x2 +-#define MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x5D4 0x0 0x0 +-#define MX8MN_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_I2C4_SCL_ECSPI2_MISO 0x22C 0x494 0x578 0x3 0x2 +-#define MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x58C 0x0 0x0 +-#define MX8MN_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_I2C4_SDA_ECSPI2_SS0 0x230 0x498 0x570 0x3 0x1 +-#define MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 +-#define MX8MN_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x1 +-#define MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 +-#define MX8MN_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_UART2_RXD_GPT1_COMPARE3 0x23C 0x4A4 0x000 0x3 0x0 +-#define MX8MN_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 +-#define MX8MN_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_UART2_TXD_GPT1_COMPARE2 0x240 0x4A8 0x000 0x3 0x0 +-#define MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 +-#define MX8MN_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 +-#define MX8MN_IOMUXC_UART3_RXD_USDHC3_RESET_B 0x244 0x4AC 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_UART3_RXD_GPT1_CAPTURE2 0x244 0x4AC 0x5EC 0x3 0x1 +-#define MX8MN_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 +-#define MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 +-#define MX8MN_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_UART3_TXD_USDHC3_VSELECT 0x248 0x4B0 0x000 0x2 0x0 +-#define MX8MN_IOMUXC_UART3_TXD_GPT1_CLK 0x248 0x4B0 0x5E8 0x3 0x1 +-#define MX8MN_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 +-#define MX8MN_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 +-#define MX8MN_IOMUXC_UART4_RXD_GPT1_COMPARE1 0x24C 0x4B4 0x000 0x3 0x0 +-#define MX8MN_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 +-#define MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 +-#define MX8MN_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 +-#define MX8MN_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 +-#define MX8MN_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 +-#define MX8MN_IOMUXC_UART4_TXD_GPT1_CAPTURE1 0x250 0x4B8 0x5F0 0x3 0x1 +-#define MX8MN_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 +- +-#endif /* __DTS_IMX8MN_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-var-som-symphony.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-var-som-symphony.dts +deleted file mode 100644 +index f61c48776cf3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-var-som-symphony.dts ++++ /dev/null +@@ -1,240 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2019-2020 Variscite Ltd. +- * Copyright (C) 2020 Krzysztof Kozlowski +- */ +- +-/dts-v1/; +- +-#include "imx8mn-var-som.dtsi" +- +-/ { +- model = "Variscite VAR-SOM-MX8MN Symphony evaluation board"; +- compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn"; +- +- reg_usdhc2_vmmc: regulator-usdhc2-vmmc { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; +- regulator-name = "VSD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- back { +- label = "Back"; +- gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- home { +- label = "Home"; +- gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- menu { +- label = "Menu"; +- gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led { +- label = "Heartbeat"; +- gpios = <&pca9534 0 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-ðphy { +- reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- pca9534: gpio@20 { +- compatible = "nxp,pca9534"; +- reg = <0x20>; +- gpio-controller; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pca9534>; +- interrupt-parent = <&gpio1>; +- interrupts = <7 IRQ_TYPE_EDGE_FALLING>; +- #gpio-cells = <2>; +- wakeup-source; +- +- /* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */ +- usb3-sata-sel-hog { +- gpio-hog; +- gpios = <4 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "usb3_sata_sel"; +- }; +- +- som-vselect-hog { +- gpio-hog; +- gpios = <6 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "som_vselect"; +- }; +- +- enet-sel-hog { +- gpio-hog; +- gpios = <7 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "enet_sel"; +- }; +- }; +- +- extcon_usbotg1: typec@3d { +- compatible = "nxp,ptn5150"; +- reg = <0x3d>; +- interrupt-parent = <&gpio1>; +- interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ptn5150>; +- status = "okay"; +- }; +-}; +- +-&i2c3 { +- /* Capacitive touch controller */ +- ft5x06_ts: touchscreen@38 { +- compatible = "edt,edt-ft5406"; +- reg = <0x38>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_captouch>; +- interrupt-parent = <&gpio5>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +- +- touchscreen-size-x = <800>; +- touchscreen-size-y = <480>; +- touchscreen-inverted-x; +- touchscreen-inverted-y; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1337"; +- reg = <0x68>; +- }; +-}; +- +-/* Header */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-/* Header */ +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&usbotg1 { +- disable-over-current; +- extcon = <&extcon_usbotg1>, <&extcon_usbotg1>; +-}; +- +-&pinctrl_fec1 { +- fsl,pins = < +- MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 +- MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */ +- >; +-}; +- +-&pinctrl_fec1_sleep { +- fsl,pins = < +- MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120 +- MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120 +- MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120 +- MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120 +- MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120 +- MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120 +- MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120 +- MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120 +- MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120 +- MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120 +- MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120 +- MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120 +- MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120 +- MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120 +- /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */ +- >; +-}; +- +-&iomuxc { +- pinctrl_captouch: captouchgrp { +- fsl,pins = < +- MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 +- MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_pca9534: pca9534grp { +- fsl,pins = < +- MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 +- >; +- }; +- +- pinctrl_ptn5150: ptn5150grp { +- fsl,pins = < +- MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 +- >; +- }; +- +- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { +- fsl,pins = < +- MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 +- MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 +- MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-var-som.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-var-som.dtsi +deleted file mode 100644 +index b16c7caf34c1..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-var-som.dtsi ++++ /dev/null +@@ -1,548 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2019 NXP +- * Copyright 2019-2020 Variscite Ltd. +- * Copyright (C) 2020 Krzysztof Kozlowski +- */ +- +-#include "imx8mn.dtsi" +- +-/ { +- model = "Variscite VAR-SOM-MX8MN module"; +- compatible = "variscite,var-som-mx8mn", "fsl,imx8mn"; +- +- chosen { +- stdout-path = &uart4; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x0 0x40000000 0 0x40000000>; +- }; +- +- reg_eth_phy: regulator-eth-phy { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_eth_phy>; +- regulator-name = "eth_phy_pwr"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&A53_0 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_1 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_2 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_3 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>, +- <&gpio1 0 GPIO_ACTIVE_LOW>; +- /delete-property/ dmas; +- /delete-property/ dma-names; +- status = "okay"; +- +- /* Resistive touch controller */ +- touchscreen@0 { +- reg = <0>; +- compatible = "ti,ads7846"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_restouch>; +- interrupt-parent = <&gpio1>; +- interrupts = <3 IRQ_TYPE_EDGE_FALLING>; +- +- spi-max-frequency = <1500000>; +- pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; +- +- ti,x-min = /bits/ 16 <125>; +- touchscreen-size-x = /bits/ 16 <4008>; +- ti,y-min = /bits/ 16 <282>; +- touchscreen-size-y = /bits/ 16 <3864>; +- ti,x-plate-ohms = /bits/ 16 <180>; +- touchscreen-max-pressure = /bits/ 16 <255>; +- touchscreen-average-samples = /bits/ 16 <10>; +- ti,debounce-tol = /bits/ 16 <3>; +- ti,debounce-rep = /bits/ 16 <1>; +- ti,settle-delay-usec = /bits/ 16 <150>; +- ti,keep-vref-on; +- wakeup-source; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&pinctrl_fec1>; +- pinctrl-1 = <&pinctrl_fec1_sleep>; +- phy-mode = "rgmii"; +- phy-handle = <ðphy>; +- phy-supply = <®_eth_phy>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy@4 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <4>; +- reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic@4b { +- compatible = "rohm,bd71847"; +- reg = <0x4b>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio2>; +- interrupts = <8 IRQ_TYPE_LEVEL_LOW>; +- rohm,reset-snvs-powered; +- +- regulators { +- buck1_reg: BUCK1 { +- regulator-name = "buck1"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "buck2"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- rohm,dvs-run-voltage = <1000000>; +- rohm,dvs-idle-voltage = <900000>; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "buck3"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "buck4"; +- regulator-min-microvolt = <2600000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "buck5"; +- regulator-min-microvolt = <1605000>; +- regulator-max-microvolt = <1995000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck6_reg: BUCK6 { +- regulator-name = "buck6"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1_reg: LDO1 { +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1600000>; +- regulator-max-microvolt = <1900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "ldo2"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "ldo4"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo5_reg: LDO5 { +- regulator-compatible = "ldo5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "ldo6"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- /* TODO: configure audio, as of now just put a placeholder */ +- wm8904: codec@1a { +- compatible = "wlf,wm8904"; +- reg = <0x1a>; +- status = "disabled"; +- }; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +- +-/* Bluetooth */ +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- assigned-clocks = <&clk IMX8MN_CLK_UART2>; +- assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-/* Console */ +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbotg1 { +- dr_mode = "otg"; +- usb-role-switch; +- status = "okay"; +-}; +- +-/* WIFI */ +-&usdhc1 { +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- bus-width = <4>; +- non-removable; +- keep-power-in-suspend; +- status = "okay"; +- +- brcmf: bcrmf@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* SD */ +-&usdhc2 { +- assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +- cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- vmmc-supply = <®_usdhc2_vmmc>; +- status = "okay"; +-}; +- +-/* eMMC */ +-&usdhc3 { +- assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; +- assigned-clock-rates = <400000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 +- MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13 +- MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13 +- MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13 +- MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13 +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 +- MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 +- >; +- }; +- +- pinctrl_fec1_sleep: fec1sleepgrp { +- fsl,pins = < +- MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120 +- MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120 +- MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120 +- MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120 +- MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120 +- MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120 +- MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120 +- MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120 +- MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120 +- MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120 +- MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120 +- MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120 +- MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120 +- MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120 +- MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 +- MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 +- MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_pmic: pmicirqgrp { +- fsl,pins = < +- MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 +- >; +- }; +- +- pinctrl_reg_eth_phy: regethphygrp { +- fsl,pins = < +- MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 +- >; +- }; +- +- pinctrl_restouch: restouchgrp { +- fsl,pins = < +- MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 +- MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 +- MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 +- MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 +- MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 +- MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 +- MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 +- MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 +- MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 +- MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { +- fsl,pins = < +- MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 +- MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 +- MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 +- MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 +- MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 +- MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { +- fsl,pins = < +- MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 +- MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 +- MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 +- MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 +- MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 +- MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 +- >; +- }; +- +- pinctrl_usdhc2_gpio: usdhc2gpiogrp { +- fsl,pins = < +- MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 +- MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 +- MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 +- MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 +- MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 +- MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 +- MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { +- fsl,pins = < +- MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 +- MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 +- MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 +- MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 +- MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 +- MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 +- MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { +- fsl,pins = < +- MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 +- MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 +- MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 +- MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 +- MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 +- MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 +- MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 +- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 +- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 +- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 +- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 +- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 +- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 +- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 +- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 +- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 +- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { +- fsl,pins = < +- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 +- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 +- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 +- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 +- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 +- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 +- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 +- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 +- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 +- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 +- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { +- fsl,pins = < +- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 +- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 +- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 +- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 +- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 +- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 +- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 +- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 +- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 +- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 +- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-venice-gw7902.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-venice-gw7902.dts +deleted file mode 100644 +index 236f425e1570..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-venice-gw7902.dts ++++ /dev/null +@@ -1,884 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2021 Gateworks Corporation +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include +- +-#include "imx8mn.dtsi" +- +-/ { +- model = "Gateworks Venice GW7902 i.MX8MN board"; +- compatible = "gw,imx8mn-gw7902", "fsl,imx8mn"; +- +- aliases { +- usb0 = &usbotg1; +- }; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x0 0x40000000 0 0x80000000>; +- }; +- +- can20m: can20m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <20000000>; +- clock-output-names = "can20m"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-pb { +- label = "user_pb"; +- gpios = <&gpio 2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- user-pb1x { +- label = "user_pb1x"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <0>; +- }; +- +- key-erased { +- label = "key_erased"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <1>; +- }; +- +- eeprom-wp { +- label = "eeprom_wp"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <2>; +- }; +- +- tamper { +- label = "tamper"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <5>; +- }; +- +- switch-hold { +- label = "switch_hold"; +- linux,code = ; +- interrupt-parent = <&gsc>; +- interrupts = <7>; +- }; +- }; +- +- led-controller { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led-0 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "panel1"; +- gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led-1 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "panel2"; +- gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led-2 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "panel3"; +- gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led-3 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "panel4"; +- gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led-4 { +- function = LED_FUNCTION_STATUS; +- color = ; +- label = "panel5"; +- gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- pps { +- compatible = "pps-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pps>; +- gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usb1_vbus: regulator-usb1 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usb1>; +- regulator-name = "usb_usb1_vbus"; +- gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_wifi: regulator-wifi { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_wl>; +- regulator-name = "wifi"; +- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- startup-delay-us = <100>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&A53_0 { +- cpu-supply = <&buck2>; +-}; +- +-&A53_1 { +- cpu-supply = <&buck2>; +-}; +- +-&A53_2 { +- cpu-supply = <&buck2>; +-}; +- +-&A53_3 { +- cpu-supply = <&buck2>; +-}; +- +-&ddrc { +- operating-points-v2 = <&ddrc_opp_table>; +- +- ddrc_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-25M { +- opp-hz = /bits/ 64 <25000000>; +- }; +- +- opp-100M { +- opp-hz = /bits/ 64 <100000000>; +- }; +- +- opp-750M { +- opp-hz = /bits/ 64 <750000000>; +- }; +- }; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1>; +- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- can@0 { +- compatible = "microchip,mcp2515"; +- reg = <0>; +- clocks = <&can20m>; +- oscillator-frequency = <20000000>; +- interrupt-parent = <&gpio2>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- spi-max-frequency = <10000000>; +- }; +-}; +- +-/* off-board header */ +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi2>; +- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- local-mac-address = [00 00 00 00 00 00]; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- ti,rx-internal-delay = ; +- ti,tx-internal-delay = ; +- tx-fifo-depth = ; +- rx-fifo-depth = ; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- gsc: gsc@20 { +- compatible = "gw,gsc"; +- reg = <0x20>; +- pinctrl-0 = <&pinctrl_gsc>; +- interrupt-parent = <&gpio2>; +- interrupts = <6 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <1>; +- +- adc { +- compatible = "gw,gsc-adc"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@6 { +- gw,mode = <0>; +- reg = <0x06>; +- label = "temp"; +- }; +- +- channel@8 { +- gw,mode = <1>; +- reg = <0x08>; +- label = "vdd_bat"; +- }; +- +- channel@82 { +- gw,mode = <2>; +- reg = <0x82>; +- label = "vin"; +- gw,voltage-divider-ohms = <22100 1000>; +- gw,voltage-offset-microvolt = <700000>; +- }; +- +- channel@84 { +- gw,mode = <2>; +- reg = <0x84>; +- label = "vin_4p0"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- +- channel@86 { +- gw,mode = <2>; +- reg = <0x86>; +- label = "vdd_3p3"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- +- channel@88 { +- gw,mode = <2>; +- reg = <0x88>; +- label = "vdd_0p9"; +- }; +- +- channel@8c { +- gw,mode = <2>; +- reg = <0x8c>; +- label = "vdd_soc"; +- }; +- +- channel@8e { +- gw,mode = <2>; +- reg = <0x8e>; +- label = "vdd_arm"; +- }; +- +- channel@90 { +- gw,mode = <2>; +- reg = <0x90>; +- label = "vdd_1p8"; +- }; +- +- channel@92 { +- gw,mode = <2>; +- reg = <0x92>; +- label = "vdd_dram"; +- }; +- +- channel@98 { +- gw,mode = <2>; +- reg = <0x98>; +- label = "vdd_1p0"; +- }; +- +- channel@9a { +- gw,mode = <2>; +- reg = <0x9a>; +- label = "vdd_2p5"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- +- channel@a2 { +- gw,mode = <2>; +- reg = <0xa2>; +- label = "vdd_gsc"; +- gw,voltage-divider-ohms = <10000 10000>; +- }; +- }; +- }; +- +- gpio: gpio@23 { +- compatible = "nxp,pca9555"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gsc>; +- interrupts = <4>; +- }; +- +- pmic@4b { +- compatible = "rohm,bd71847"; +- reg = <0x4b>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio3>; +- interrupts = <8 IRQ_TYPE_LEVEL_LOW>; +- rohm,reset-snvs-powered; +- #clock-cells = <0>; +- clocks = <&osc_32k 0>; +- clock-output-names = "clk-32k-out"; +- +- regulators { +- /* vdd_soc: 0.805-0.900V (typ=0.8V) */ +- BUCK1 { +- regulator-name = "buck1"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- }; +- +- /* vdd_arm: 0.805-1.0V (typ=0.9V) */ +- buck2: BUCK2 { +- regulator-name = "buck2"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- rohm,dvs-run-voltage = <1000000>; +- rohm,dvs-idle-voltage = <900000>; +- }; +- +- /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ +- BUCK3 { +- regulator-name = "buck3"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdd_3p3 */ +- BUCK4 { +- regulator-name = "buck4"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdd_1p8 */ +- BUCK5 { +- regulator-name = "buck5"; +- regulator-min-microvolt = <1605000>; +- regulator-max-microvolt = <1995000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdd_dram */ +- BUCK6 { +- regulator-name = "buck6"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* nvcc_snvs_1p8 */ +- LDO1 { +- regulator-name = "ldo1"; +- regulator-min-microvolt = <1600000>; +- regulator-max-microvolt = <1900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdd_snvs_0p8 */ +- LDO2 { +- regulator-name = "ldo2"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- /* vdda_1p8 */ +- LDO3 { +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- LDO4 { +- regulator-name = "ldo4"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- LDO6 { +- regulator-name = "ldo6"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c02"; +- reg = <0x52>; +- pagesize = <16>; +- }; +- +- eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1672"; +- reg = <0x68>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- accelerometer@19 { +- compatible = "st,lis2de12"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_accel>; +- reg = <0x19>; +- st,drdy-int-pin = <1>; +- interrupt-parent = <&gpio1>; +- interrupts = <12 IRQ_TYPE_LEVEL_LOW>; +- interrupt-names = "INT1"; +- }; +-}; +- +-/* off-board header */ +-&i2c3 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-/* off-board header */ +-&i2c4 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +-}; +- +-/* off-board header */ +-&sai3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai3>; +- assigned-clocks = <&clk IMX8MN_CLK_SAI3>; +- assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; +- assigned-clock-rates = <24576000>; +- status = "okay"; +-}; +- +-/* RS232/RS485/RS422 selectable */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; +- status = "okay"; +-}; +- +-/* RS232 console */ +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-/* bluetooth HCI */ +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; +- rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +- cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm4330-bt"; +- shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */ +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&usbotg1 { +- dr_mode = "host"; +- vbus-supply = <®_usb1_vbus>; +- disable-over-current; +- status = "okay"; +-}; +- +-/* SDIO WiFi */ +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- non-removable; +- vmmc-supply = <®_wifi>; +- status = "okay"; +-}; +- +-/* eMMC */ +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ +- MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */ +- MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ +- MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ +- MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ +- MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ +- MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ +- MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ +- MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */ +- MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */ +- MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */ +- >; +- }; +- +- pinctrl_accel: accelgrp { +- fsl,pins = < +- MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159 +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 +- MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ +- MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ +- MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141 +- MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141 +- >; +- }; +- +- pinctrl_gsc: gscgrp { +- fsl,pins = < +- MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 +- MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 +- MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 +- MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 +- MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_gpio_leds: gpioledgrp { +- fsl,pins = < +- MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 +- MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 +- MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 +- MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 +- MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 +- >; +- }; +- +- pinctrl_pps: ppsgrp { +- fsl,pins = < +- MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */ +- >; +- }; +- +- pinctrl_reg_wl: regwlgrp { +- fsl,pins = < +- MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */ +- >; +- }; +- +- pinctrl_reg_usb1: regusb1grp { +- fsl,pins = < +- MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41 +- >; +- }; +- +- pinctrl_sai3: sai3grp { +- fsl,pins = < +- MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 +- MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 +- MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 +- MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 +- MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 +- >; +- }; +- +- pinctrl_spi1: spi1grp { +- fsl,pins = < +- MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 +- MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 +- MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 +- MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40 +- MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */ +- >; +- }; +- +- pinctrl_spi2: spi2grp { +- fsl,pins = < +- MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 +- MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 +- MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 +- MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */ +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 +- MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_uart1_gpio: uart1gpiogrp { +- fsl,pins = < +- MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */ +- MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */ +- MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */ +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 +- MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 +- >; +- }; +- +- pinctrl_uart3_gpio: uart3_gpiogrp { +- fsl,pins = < +- MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */ +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 +- MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 +- MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */ +- MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */ +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 +- MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 +- MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */ +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 +- MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 +- MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 +- MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 +- MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 +- MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 +- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 +- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 +- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 +- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 +- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 +- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 +- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 +- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 +- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 +- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { +- fsl,pins = < +- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 +- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 +- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 +- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 +- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 +- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 +- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 +- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 +- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 +- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 +- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { +- fsl,pins = < +- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 +- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 +- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 +- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 +- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 +- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 +- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 +- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 +- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 +- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 +- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mn.dtsi +deleted file mode 100644 +index da6c942fb7f9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mn.dtsi ++++ /dev/null +@@ -1,1048 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2019 NXP +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include "imx8mn-pinfunc.h" +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- ethernet0 = &fec1; +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- gpio3 = &gpio4; +- gpio4 = &gpio5; +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- i2c3 = &i2c4; +- mmc0 = &usdhc1; +- mmc1 = &usdhc2; +- mmc2 = &usdhc3; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- spi0 = &ecspi1; +- spi1 = &ecspi2; +- spi2 = &ecspi3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- idle-states { +- entry-method = "psci"; +- +- cpu_pd_wait: cpu-pd-wait { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x0010033>; +- local-timer-stop; +- entry-latency-us = <1000>; +- exit-latency-us = <700>; +- min-residency-us = <2700>; +- }; +- }; +- +- A53_0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0>; +- clock-latency = <61036>; +- clocks = <&clk IMX8MN_CLK_ARM>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- operating-points-v2 = <&a53_opp_table>; +- nvmem-cells = <&cpu_speed_grade>; +- nvmem-cell-names = "speed_grade"; +- cpu-idle-states = <&cpu_pd_wait>; +- #cooling-cells = <2>; +- }; +- +- A53_1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x1>; +- clock-latency = <61036>; +- clocks = <&clk IMX8MN_CLK_ARM>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- operating-points-v2 = <&a53_opp_table>; +- cpu-idle-states = <&cpu_pd_wait>; +- #cooling-cells = <2>; +- }; +- +- A53_2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x2>; +- clock-latency = <61036>; +- clocks = <&clk IMX8MN_CLK_ARM>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- operating-points-v2 = <&a53_opp_table>; +- cpu-idle-states = <&cpu_pd_wait>; +- #cooling-cells = <2>; +- }; +- +- A53_3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x3>; +- clock-latency = <61036>; +- clocks = <&clk IMX8MN_CLK_ARM>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- operating-points-v2 = <&a53_opp_table>; +- cpu-idle-states = <&cpu_pd_wait>; +- #cooling-cells = <2>; +- }; +- +- A53_L2: l2-cache0 { +- compatible = "cache"; +- }; +- }; +- +- a53_opp_table: opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <850000>; +- opp-supported-hw = <0xb00>, <0x7>; +- clock-latency-ns = <150000>; +- opp-suspend; +- }; +- +- opp-1400000000 { +- opp-hz = /bits/ 64 <1400000000>; +- opp-microvolt = <950000>; +- opp-supported-hw = <0x300>, <0x7>; +- clock-latency-ns = <150000>; +- opp-suspend; +- }; +- +- opp-1500000000 { +- opp-hz = /bits/ 64 <1500000000>; +- opp-microvolt = <1000000>; +- opp-supported-hw = <0x100>, <0x3>; +- clock-latency-ns = <150000>; +- opp-suspend; +- }; +- }; +- +- osc_32k: clock-osc-32k { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "osc_32k"; +- }; +- +- osc_24m: clock-osc-24m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "osc_24m"; +- }; +- +- clk_ext1: clock-ext1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <133000000>; +- clock-output-names = "clk_ext1"; +- }; +- +- clk_ext2: clock-ext2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <133000000>; +- clock-output-names = "clk_ext2"; +- }; +- +- clk_ext3: clock-ext3 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <133000000>; +- clock-output-names = "clk_ext3"; +- }; +- +- clk_ext4: clock-ext4 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency= <133000000>; +- clock-output-names = "clk_ext4"; +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- thermal-zones { +- cpu-thermal { +- polling-delay-passive = <250>; +- polling-delay = <2000>; +- thermal-sensors = <&tmu>; +- trips { +- cpu_alert0: trip0 { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_crit0: trip1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- cooling-device = +- <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- clock-frequency = <8000000>; +- arm,no-tick-in-suspend; +- }; +- +- soc@0 { +- compatible = "fsl,imx8mn-soc", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x0 0x3e000000>; +- dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; +- nvmem-cells = <&imx8mn_uid>; +- nvmem-cell-names = "soc_unique_id"; +- +- aips1: bus@30000000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- reg = <0x30000000 0x400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- spba2: spba-bus@30000000 { +- compatible = "fsl,spba-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x30000000 0x100000>; +- ranges; +- +- sai2: sai@30020000 { +- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; +- reg = <0x30020000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_SAI2_IPG>, +- <&clk IMX8MN_CLK_DUMMY>, +- <&clk IMX8MN_CLK_SAI2_ROOT>, +- <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; +- clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; +- dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sai3: sai@30030000 { +- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; +- reg = <0x30030000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_SAI3_IPG>, +- <&clk IMX8MN_CLK_DUMMY>, +- <&clk IMX8MN_CLK_SAI3_ROOT>, +- <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; +- clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; +- dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sai5: sai@30050000 { +- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; +- reg = <0x30050000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_SAI5_IPG>, +- <&clk IMX8MN_CLK_DUMMY>, +- <&clk IMX8MN_CLK_SAI5_ROOT>, +- <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; +- clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; +- dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; +- dma-names = "rx", "tx"; +- fsl,shared-interrupt; +- fsl,dataline = <0 0xf 0xf>; +- status = "disabled"; +- }; +- +- sai6: sai@30060000 { +- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; +- reg = <0x30060000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_SAI6_IPG>, +- <&clk IMX8MN_CLK_DUMMY>, +- <&clk IMX8MN_CLK_SAI6_ROOT>, +- <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; +- clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; +- dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- micfil: audio-controller@30080000 { +- compatible = "fsl,imx8mm-micfil"; +- reg = <0x30080000 0x10000>; +- interrupts = , +- , +- , +- ; +- clocks = <&clk IMX8MN_CLK_PDM_IPG>, +- <&clk IMX8MN_CLK_PDM_ROOT>, +- <&clk IMX8MN_AUDIO_PLL1_OUT>, +- <&clk IMX8MN_AUDIO_PLL2_OUT>, +- <&clk IMX8MN_CLK_EXT3>; +- clock-names = "ipg_clk", "ipg_clk_app", +- "pll8k", "pll11k", "clkext3"; +- dmas = <&sdma2 24 25 0x80000000>; +- dma-names = "rx"; +- status = "disabled"; +- }; +- +- spdif1: spdif@30090000 { +- compatible = "fsl,imx35-spdif"; +- reg = <0x30090000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */ +- <&clk IMX8MN_CLK_24M>, /* rxtx0 */ +- <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */ +- <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */ +- <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */ +- <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */ +- <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */ +- <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */ +- <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */ +- <&clk IMX8MN_CLK_DUMMY>; /* spba */ +- clock-names = "core", "rxtx0", +- "rxtx1", "rxtx2", +- "rxtx3", "rxtx4", +- "rxtx5", "rxtx6", +- "rxtx7", "spba"; +- dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sai7: sai@300b0000 { +- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; +- reg = <0x300b0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_SAI7_IPG>, +- <&clk IMX8MN_CLK_DUMMY>, +- <&clk IMX8MN_CLK_SAI7_ROOT>, +- <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; +- clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; +- dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- easrc: easrc@300c0000 { +- compatible = "fsl,imx8mn-easrc"; +- reg = <0x300c0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; +- clock-names = "mem"; +- dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, +- <&sdma2 18 23 0> , <&sdma2 19 23 0>, +- <&sdma2 20 23 0> , <&sdma2 21 23 0>, +- <&sdma2 22 23 0> , <&sdma2 23 23 0>; +- dma-names = "ctx0_rx", "ctx0_tx", +- "ctx1_rx", "ctx1_tx", +- "ctx2_rx", "ctx2_tx", +- "ctx3_rx", "ctx3_tx"; +- firmware-name = "imx/easrc/easrc-imx8mn.bin"; +- fsl,asrc-rate = <8000>; +- fsl,asrc-format = <2>; +- status = "disabled"; +- }; +- }; +- +- gpio1: gpio@30200000 { +- compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; +- reg = <0x30200000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 10 30>; +- }; +- +- gpio2: gpio@30210000 { +- compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; +- reg = <0x30210000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 40 21>; +- }; +- +- gpio3: gpio@30220000 { +- compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; +- reg = <0x30220000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 61 26>; +- }; +- +- gpio4: gpio@30230000 { +- compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; +- reg = <0x30230000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 21 108 11>; +- }; +- +- gpio5: gpio@30240000 { +- compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; +- reg = <0x30240000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 119 30>; +- }; +- +- tmu: tmu@30260000 { +- compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; +- reg = <0x30260000 0x10000>; +- clocks = <&clk IMX8MN_CLK_TMU_ROOT>; +- #thermal-sensor-cells = <0>; +- }; +- +- wdog1: watchdog@30280000 { +- compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; +- reg = <0x30280000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>; +- status = "disabled"; +- }; +- +- wdog2: watchdog@30290000 { +- compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; +- reg = <0x30290000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>; +- status = "disabled"; +- }; +- +- wdog3: watchdog@302a0000 { +- compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; +- reg = <0x302a0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>; +- status = "disabled"; +- }; +- +- sdma3: dma-controller@302b0000 { +- compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; +- reg = <0x302b0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, +- <&clk IMX8MN_CLK_SDMA3_ROOT>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; +- }; +- +- sdma2: dma-controller@302c0000 { +- compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; +- reg = <0x302c0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, +- <&clk IMX8MN_CLK_SDMA2_ROOT>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; +- }; +- +- iomuxc: pinctrl@30330000 { +- compatible = "fsl,imx8mn-iomuxc"; +- reg = <0x30330000 0x10000>; +- }; +- +- gpr: iomuxc-gpr@30340000 { +- compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; +- reg = <0x30340000 0x10000>; +- }; +- +- ocotp: efuse@30350000 { +- compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; +- reg = <0x30350000 0x10000>; +- clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- imx8mn_uid: unique-id@410 { +- reg = <0x4 0x8>; +- }; +- +- cpu_speed_grade: speed-grade@10 { +- reg = <0x10 4>; +- }; +- +- fec_mac_address: mac-address@90 { +- reg = <0x90 6>; +- }; +- }; +- +- anatop: anatop@30360000 { +- compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop", +- "syscon"; +- reg = <0x30360000 0x10000>; +- }; +- +- snvs: snvs@30370000 { +- compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; +- reg = <0x30370000 0x10000>; +- +- snvs_rtc: snvs-rtc-lp { +- compatible = "fsl,sec-v4.0-mon-rtc-lp"; +- regmap = <&snvs>; +- offset = <0x34>; +- interrupts = , +- ; +- clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; +- clock-names = "snvs-rtc"; +- }; +- +- snvs_pwrkey: snvs-powerkey { +- compatible = "fsl,sec-v4.0-pwrkey"; +- regmap = <&snvs>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; +- clock-names = "snvs-pwrkey"; +- linux,keycode = ; +- wakeup-source; +- status = "disabled"; +- }; +- }; +- +- clk: clock-controller@30380000 { +- compatible = "fsl,imx8mn-ccm"; +- reg = <0x30380000 0x10000>; +- #clock-cells = <1>; +- clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, +- <&clk_ext3>, <&clk_ext4>; +- clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", +- "clk_ext3", "clk_ext4"; +- assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, +- <&clk IMX8MN_CLK_A53_CORE>, +- <&clk IMX8MN_CLK_NOC>, +- <&clk IMX8MN_CLK_AUDIO_AHB>, +- <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, +- <&clk IMX8MN_SYS_PLL3>, +- <&clk IMX8MN_AUDIO_PLL1>, +- <&clk IMX8MN_AUDIO_PLL2>; +- assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, +- <&clk IMX8MN_ARM_PLL_OUT>, +- <&clk IMX8MN_SYS_PLL3_OUT>, +- <&clk IMX8MN_SYS_PLL1_800M>; +- assigned-clock-rates = <0>, <0>, <0>, +- <400000000>, +- <400000000>, +- <600000000>, +- <393216000>, +- <361267200>; +- }; +- +- src: reset-controller@30390000 { +- compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"; +- reg = <0x30390000 0x10000>; +- interrupts = ; +- #reset-cells = <1>; +- }; +- }; +- +- aips2: bus@30400000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- reg = <0x30400000 0x400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- pwm1: pwm@30660000 { +- compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; +- reg = <0x30660000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, +- <&clk IMX8MN_CLK_PWM1_ROOT>; +- clock-names = "ipg", "per"; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm2: pwm@30670000 { +- compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; +- reg = <0x30670000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, +- <&clk IMX8MN_CLK_PWM2_ROOT>; +- clock-names = "ipg", "per"; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm3: pwm@30680000 { +- compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; +- reg = <0x30680000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, +- <&clk IMX8MN_CLK_PWM3_ROOT>; +- clock-names = "ipg", "per"; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm4: pwm@30690000 { +- compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; +- reg = <0x30690000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, +- <&clk IMX8MN_CLK_PWM4_ROOT>; +- clock-names = "ipg", "per"; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- system_counter: timer@306a0000 { +- compatible = "nxp,sysctr-timer"; +- reg = <0x306a0000 0x20000>; +- interrupts = ; +- clocks = <&osc_24m>; +- clock-names = "per"; +- }; +- }; +- +- aips3: bus@30800000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- reg = <0x30800000 0x400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- spba1: spba-bus@30800000 { +- compatible = "fsl,spba-bus", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x30800000 0x100000>; +- ranges; +- +- ecspi1: spi@30820000 { +- compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x30820000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, +- <&clk IMX8MN_CLK_ECSPI1_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ecspi2: spi@30830000 { +- compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x30830000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, +- <&clk IMX8MN_CLK_ECSPI2_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ecspi3: spi@30840000 { +- compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x30840000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, +- <&clk IMX8MN_CLK_ECSPI3_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart1: serial@30860000 { +- compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; +- reg = <0x30860000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_UART1_ROOT>, +- <&clk IMX8MN_CLK_UART1_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart3: serial@30880000 { +- compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; +- reg = <0x30880000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_UART3_ROOT>, +- <&clk IMX8MN_CLK_UART3_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart2: serial@30890000 { +- compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; +- reg = <0x30890000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_UART2_ROOT>, +- <&clk IMX8MN_CLK_UART2_ROOT>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- }; +- +- crypto: crypto@30900000 { +- compatible = "fsl,sec-v4.0"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x30900000 0x40000>; +- ranges = <0 0x30900000 0x40000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_AHB>, +- <&clk IMX8MN_CLK_IPG_ROOT>; +- clock-names = "aclk", "ipg"; +- +- sec_jr0: jr@1000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x1000 0x1000>; +- interrupts = ; +- }; +- +- sec_jr1: jr@2000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x2000 0x1000>; +- interrupts = ; +- }; +- +- sec_jr2: jr@3000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x3000 0x1000>; +- interrupts = ; +- }; +- }; +- +- i2c1: i2c@30a20000 { +- compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x30a20000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_I2C1_ROOT>; +- status = "disabled"; +- }; +- +- i2c2: i2c@30a30000 { +- compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x30a30000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_I2C2_ROOT>; +- status = "disabled"; +- }; +- +- i2c3: i2c@30a40000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; +- reg = <0x30a40000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_I2C3_ROOT>; +- status = "disabled"; +- }; +- +- i2c4: i2c@30a50000 { +- compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x30a50000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_I2C4_ROOT>; +- status = "disabled"; +- }; +- +- uart4: serial@30a60000 { +- compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; +- reg = <0x30a60000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_UART4_ROOT>, +- <&clk IMX8MN_CLK_UART4_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- mu: mailbox@30aa0000 { +- compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu"; +- reg = <0x30aa0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_MU_ROOT>; +- #mbox-cells = <2>; +- }; +- +- usdhc1: mmc@30b40000 { +- compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; +- reg = <0x30b40000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_IPG_ROOT>, +- <&clk IMX8MN_CLK_NAND_USDHC_BUS>, +- <&clk IMX8MN_CLK_USDHC1_ROOT>; +- clock-names = "ipg", "ahb", "per"; +- fsl,tuning-start-tap = <20>; +- fsl,tuning-step= <2>; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usdhc2: mmc@30b50000 { +- compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; +- reg = <0x30b50000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_IPG_ROOT>, +- <&clk IMX8MN_CLK_NAND_USDHC_BUS>, +- <&clk IMX8MN_CLK_USDHC2_ROOT>; +- clock-names = "ipg", "ahb", "per"; +- fsl,tuning-start-tap = <20>; +- fsl,tuning-step= <2>; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usdhc3: mmc@30b60000 { +- compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; +- reg = <0x30b60000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_IPG_ROOT>, +- <&clk IMX8MN_CLK_NAND_USDHC_BUS>, +- <&clk IMX8MN_CLK_USDHC3_ROOT>; +- clock-names = "ipg", "ahb", "per"; +- fsl,tuning-start-tap = <20>; +- fsl,tuning-step= <2>; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- flexspi: spi@30bb0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "nxp,imx8mm-fspi"; +- reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; +- reg-names = "fspi_base", "fspi_mmap"; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, +- <&clk IMX8MN_CLK_QSPI_ROOT>; +- clock-names = "fspi_en", "fspi"; +- status = "disabled"; +- }; +- +- sdma1: dma-controller@30bd0000 { +- compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; +- reg = <0x30bd0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, +- <&clk IMX8MN_CLK_AHB>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; +- }; +- +- fec1: ethernet@30be0000 { +- compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; +- reg = <0x30be0000 0x10000>; +- interrupts = , +- , +- , +- ; +- clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, +- <&clk IMX8MN_CLK_ENET1_ROOT>, +- <&clk IMX8MN_CLK_ENET_TIMER>, +- <&clk IMX8MN_CLK_ENET_REF>, +- <&clk IMX8MN_CLK_ENET_PHY_REF>; +- clock-names = "ipg", "ahb", "ptp", +- "enet_clk_ref", "enet_out"; +- assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, +- <&clk IMX8MN_CLK_ENET_TIMER>, +- <&clk IMX8MN_CLK_ENET_REF>, +- <&clk IMX8MN_CLK_ENET_PHY_REF>; +- assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, +- <&clk IMX8MN_SYS_PLL2_100M>, +- <&clk IMX8MN_SYS_PLL2_125M>, +- <&clk IMX8MN_SYS_PLL2_50M>; +- assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; +- fsl,num-tx-queues = <3>; +- fsl,num-rx-queues = <3>; +- nvmem-cells = <&fec_mac_address>; +- nvmem-cell-names = "mac-address"; +- nvmem_macaddr_swap; +- fsl,stop-mode = <&gpr 0x10 3>; +- status = "disabled"; +- }; +- +- }; +- +- aips4: bus@32c00000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- reg = <0x32c00000 0x400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- usbotg1: usb@32e40000 { +- compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; +- reg = <0x32e40000 0x200>; +- interrupts = ; +- clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; +- clock-names = "usb1_ctrl_root_clk"; +- assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; +- assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; +- phys = <&usbphynop1>; +- fsl,usbmisc = <&usbmisc1 0>; +- status = "disabled"; +- }; +- +- usbmisc1: usbmisc@32e40200 { +- compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; +- #index-cells = <1>; +- reg = <0x32e40200 0x200>; +- }; +- }; +- +- dma_apbh: dma-controller@33000000 { +- compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; +- reg = <0x33000000 0x2000>; +- interrupts = , +- , +- , +- ; +- interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; +- #dma-cells = <1>; +- dma-channels = <4>; +- clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; +- }; +- +- gpmi: nand-controller@33002000 { +- compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x33002000 0x2000>, <0x33004000 0x4000>; +- reg-names = "gpmi-nand", "bch"; +- interrupts = ; +- interrupt-names = "bch"; +- clocks = <&clk IMX8MN_CLK_NAND_ROOT>, +- <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; +- clock-names = "gpmi_io", "gpmi_bch_apb"; +- dmas = <&dma_apbh 0>; +- dma-names = "rx-tx"; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@38800000 { +- compatible = "arm,gic-v3"; +- reg = <0x38800000 0x10000>, +- <0x38880000 0xc0000>; +- #interrupt-cells = <3>; +- interrupt-controller; +- interrupts = ; +- }; +- +- ddrc: memory-controller@3d400000 { +- compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; +- reg = <0x3d400000 0x400000>; +- clock-names = "core", "pll", "alt", "apb"; +- clocks = <&clk IMX8MN_CLK_DRAM_CORE>, +- <&clk IMX8MN_DRAM_PLL>, +- <&clk IMX8MN_CLK_DRAM_ALT>, +- <&clk IMX8MN_CLK_DRAM_APB>; +- }; +- +- ddr-pmu@3d800000 { +- compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; +- reg = <0x3d800000 0x400000>; +- interrupts = ; +- }; +- }; +- +- usbphynop1: usbphynop1 { +- #phy-cells = <0>; +- compatible = "usb-nop-xceiv"; +- clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; +- assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; +- assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; +- clock-names = "main_clk"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mp-evk.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mp-evk.dts +deleted file mode 100644 +index 7b99fad6e4d6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mp-evk.dts ++++ /dev/null +@@ -1,492 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2019 NXP +- */ +- +-/dts-v1/; +- +-#include "imx8mp.dtsi" +- +-/ { +- model = "NXP i.MX8MPlus EVK board"; +- compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_led>; +- +- status { +- label = "yellow:status"; +- gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x0 0x40000000 0 0xc0000000>, +- <0x1 0x00000000 0 0xc0000000>; +- }; +- +- reg_can1_stby: regulator-can1-stby { +- compatible = "regulator-fixed"; +- regulator-name = "can1-stby"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1_reg>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_can2_stby: regulator-can2-stby { +- compatible = "regulator-fixed"; +- regulator-name = "can2-stby"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2_reg>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usdhc2_vmmc: regulator-usdhc2 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; +- regulator-name = "VSD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&flexcan1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- xceiver-supply = <®_can1_stby>; +- status = "okay"; +-}; +- +-&flexcan2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- xceiver-supply = <®_can2_stby>; +- status = "disabled";/* can2 pin conflict with pdm */ +-}; +- +-&eqos { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_eqos>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- status = "okay"; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- eee-broken-1000t; +- }; +- }; +-}; +- +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy1>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy1: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- eee-broken-1000t; +- reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- reset-deassert-us = <80000>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic@25 { +- compatible = "nxp,pca9450c"; +- reg = <0x25>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio1>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- +- regulators { +- BUCK1 { +- regulator-name = "BUCK1"; +- regulator-min-microvolt = <720000>; +- regulator-max-microvolt = <1000000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <3125>; +- }; +- +- BUCK2 { +- regulator-name = "BUCK2"; +- regulator-min-microvolt = <720000>; +- regulator-max-microvolt = <1025000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <3125>; +- nxp,dvs-run-voltage = <950000>; +- nxp,dvs-standby-voltage = <850000>; +- }; +- +- BUCK4 { +- regulator-name = "BUCK4"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3600000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- BUCK5 { +- regulator-name = "BUCK5"; +- regulator-min-microvolt = <1650000>; +- regulator-max-microvolt = <1950000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- BUCK6 { +- regulator-name = "BUCK6"; +- regulator-min-microvolt = <1045000>; +- regulator-max-microvolt = <1155000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- LDO1 { +- regulator-name = "LDO1"; +- regulator-min-microvolt = <1650000>; +- regulator-max-microvolt = <1950000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- LDO3 { +- regulator-name = "LDO3"; +- regulator-min-microvolt = <1710000>; +- regulator-max-microvolt = <1890000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- LDO5 { +- regulator-name = "LDO5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- pca6416: gpio@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +- +-&uart2 { +- /* console */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usb3_phy1 { +- status = "okay"; +-}; +- +-&usb3_1 { +- status = "okay"; +-}; +- +-&usb_dwc3_1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb1_vbus>; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc2 { +- assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; +- assigned-clock-rates = <400000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_usdhc2_vmmc>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&usdhc3 { +- assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; +- assigned-clock-rates = <400000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_eqos: eqosgrp { +- fsl,pins = < +- MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 +- MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 +- MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 +- MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 +- MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 +- MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 +- MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 +- MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 +- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f +- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f +- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f +- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f +- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f +- MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f +- MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 +- >; +- }; +- +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 +- MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 +- MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 +- MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 +- MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 +- MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 +- MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 +- MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 +- MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f +- MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f +- MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f +- MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f +- MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f +- MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f +- MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 +- MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 +- MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 +- >; +- }; +- +- pinctrl_flexcan1_reg: flexcan1reggrp { +- fsl,pins = < +- MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ +- >; +- }; +- +- pinctrl_flexcan2_reg: flexcan2reggrp { +- fsl,pins = < +- MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ +- >; +- }; +- +- pinctrl_gpio_led: gpioledgrp { +- fsl,pins = < +- MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 +- MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 +- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 +- >; +- }; +- +- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { +- fsl,pins = < +- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 +- MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 +- >; +- }; +- +- pinctrl_usb1_vbus: usb1grp { +- fsl,pins = < +- MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 +- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 +- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 +- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 +- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 +- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 +- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { +- fsl,pins = < +- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 +- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 +- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 +- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 +- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 +- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 +- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { +- fsl,pins = < +- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 +- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 +- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 +- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 +- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 +- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 +- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_gpio: usdhc2gpiogrp { +- fsl,pins = < +- MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 +- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 +- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 +- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 +- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 +- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 +- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 +- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 +- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 +- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 +- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { +- fsl,pins = < +- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 +- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 +- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 +- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 +- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 +- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 +- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 +- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 +- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 +- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 +- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { +- fsl,pins = < +- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 +- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 +- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 +- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 +- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 +- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 +- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 +- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 +- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 +- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 +- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mp-phyboard-pollux-rdk.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mp-phyboard-pollux-rdk.dts +deleted file mode 100644 +index 984a6b9ded8d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mp-phyboard-pollux-rdk.dts ++++ /dev/null +@@ -1,205 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2020 PHYTEC Messtechnik GmbH +- * Author: Teresa Remmet +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "imx8mp-phycore-som.dtsi" +- +-/ { +- model = "PHYTEC phyBOARD-Pollux i.MX8MP"; +- compatible = "phytec,imx8mp-phyboard-pollux-rdk", +- "phytec,imx8mp-phycore-som", "fsl,imx8mp"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- reg_usdhc2_vmmc: regulator-usdhc2 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; +- regulator-name = "VSD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- startup-delay-us = <100>; +- off-on-delay-us = <12000>; +- }; +-}; +- +-&eqos { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_eqos>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- status = "okay"; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0x1>; +- ti,rx-internal-delay = ; +- ti,tx-internal-delay = ; +- ti,fifo-depth = ; +- ti,clk-output-sel = ; +- enet-phy-lane-no-swap; +- }; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c2>; +- pinctrl-1 = <&pinctrl_i2c2_gpio>; +- sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +- +- eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- pagesize = <16>; +- }; +- +- leds@62 { +- compatible = "nxp,pca9533"; +- reg = <0x62>; +- +- led1 { +- type = ; +- }; +- +- led2 { +- type = ; +- }; +- +- led3 { +- type = ; +- }; +- }; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +- +-/* debug console */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-/* SD-Card */ +-&usdhc2 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>; +- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_usdhc2_vmmc>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_eqos: eqosgrp { +- fsl,pins = < +- MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 +- MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 +- MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 +- MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 +- MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 +- MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 +- MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 +- MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 +- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f +- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f +- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f +- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f +- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f +- MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f +- MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 +- MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c2_gpio: i2c2gpiogrp { +- fsl,pins = < +- MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e3 +- MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e3 +- >; +- }; +- +- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { +- fsl,pins = < +- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49 +- MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49 +- >; +- }; +- +- pinctrl_usdhc2_pins: usdhc2-gpiogrp { +- fsl,pins = < +- MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 +- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 +- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 +- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 +- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 +- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 +- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { +- fsl,pins = < +- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 +- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 +- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 +- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 +- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 +- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 +- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { +- fsl,pins = < +- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 +- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 +- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 +- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 +- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 +- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 +- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mp-phycore-som.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mp-phycore-som.dtsi +deleted file mode 100644 +index fc178eebf8aa..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mp-phycore-som.dtsi ++++ /dev/null +@@ -1,318 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2020 PHYTEC Messtechnik GmbH +- * Author: Teresa Remmet +- */ +- +-#include +-#include "imx8mp.dtsi" +- +-/ { +- model = "PHYTEC phyCORE-i.MX8MP"; +- compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp"; +- +- aliases { +- rtc0 = &rv3028; +- rtc1 = &snvs_rtc; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x0 0x40000000 0 0x80000000>; +- }; +-}; +- +-&A53_0 { +- cpu-supply = <&buck2>; +-}; +- +-&A53_1 { +- cpu-supply = <&buck2>; +-}; +- +-&A53_2 { +- cpu-supply = <&buck2>; +-}; +- +-&A53_3 { +- cpu-supply = <&buck2>; +-}; +- +-/* ethernet 1 */ +-&fec { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy1>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy1: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- interrupt-parent = <&gpio1>; +- interrupts = <15 IRQ_TYPE_EDGE_FALLING>; +- ti,rx-internal-delay = ; +- ti,tx-internal-delay = ; +- ti,fifo-depth = ; +- ti,clk-output-sel = ; +- enet-phy-lane-no-swap; +- }; +- }; +-}; +- +-&flexspi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexspi0>; +- status = "okay"; +- +- som_flash: flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <80000000>; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <4>; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default", "gpio"; +- pinctrl-0 = <&pinctrl_i2c1>; +- pinctrl-1 = <&pinctrl_i2c1_gpio>; +- sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- status = "okay"; +- +- pmic: pmic@25 { +- reg = <0x25>; +- compatible = "nxp,pca9450c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- interrupt-parent = <&gpio4>; +- interrupts = <18 IRQ_TYPE_LEVEL_LOW>; +- +- regulators { +- buck1: BUCK1 { +- regulator-compatible = "BUCK1"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <2187500>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <3125>; +- }; +- +- buck2: BUCK2 { +- regulator-compatible = "BUCK2"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <2187500>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <3125>; +- }; +- +- buck4: BUCK4 { +- regulator-compatible = "BUCK4"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <3400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck5: BUCK5 { +- regulator-compatible = "BUCK5"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <3400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck6: BUCK6 { +- regulator-compatible = "BUCK6"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <3400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1: LDO1 { +- regulator-compatible = "LDO1"; +- regulator-min-microvolt = <1600000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo2: LDO2 { +- regulator-compatible = "LDO2"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1150000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo3: LDO3 { +- regulator-compatible = "LDO3"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo4: LDO4 { +- regulator-compatible = "LDO4"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo5: LDO5 { +- regulator-compatible = "LDO5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c32"; +- reg = <0x51>; +- pagesize = <32>; +- }; +- +- rv3028: rtc@52 { +- compatible = "microcrystal,rv3028"; +- reg = <0x52>; +- trickle-resistor-ohms = <3000>; +- }; +-}; +- +-/* eMMC */ +-&usdhc3 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc3>; +- pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_fec: fecgrp { +- fsl,pins = < +- MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 +- MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 +- MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 +- MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 +- MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 +- MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 +- MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 +- MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 +- MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f +- MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f +- MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f +- MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f +- MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f +- MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f +- MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11 +- >; +- }; +- +- pinctrl_flexspi0: flexspi0grp { +- fsl,pins = < +- MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 +- MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 +- MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 +- MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 +- MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 +- MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 +- MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 +- >; +- }; +- +- pinctrl_i2c1_gpio: i2c1gpiogrp { +- fsl,pins = < +- MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3 +- MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3 +- >; +- }; +- +- pinctrl_pmic: pmicirqgrp { +- fsl,pins = < +- MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141 +- >; +- }; +- +- pinctrl_usdhc3: usdhc3grp { +- fsl,pins = < +- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 +- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 +- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 +- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 +- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 +- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 +- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 +- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 +- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 +- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 +- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 +- >; +- }; +- +- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { +- fsl,pins = < +- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 +- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 +- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 +- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 +- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 +- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 +- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 +- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 +- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 +- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 +- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 +- >; +- }; +- +- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { +- fsl,pins = < +- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 +- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 +- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 +- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 +- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 +- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 +- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 +- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 +- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 +- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 +- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mp-pinfunc.h b/scripts/dtc/include-prefixes/arm64/freescale/imx8mp-pinfunc.h +deleted file mode 100644 +index 0fef066471ba..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mp-pinfunc.h ++++ /dev/null +@@ -1,799 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright 2019 NXP +- */ +- +-#ifndef __DTS_IMX8MP_PINFUNC_H +-#define __DTS_IMX8MP_PINFUNC_H +- +-/* +- * The pin function ID is a tuple of +- * +- */ +-#define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO02__ISP_FLASH_TRIG_0 0x01C 0x27C 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_ANY 0x01C 0x27C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO02__SJC_DE_B 0x01C 0x27C 0x000 0x7 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x020 0x280 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x020 0x280 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO03__ISP_PRELIGHT_TRIG_0 0x020 0x280 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO03__SDMA1_EXT_EVENT00 0x020 0x280 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x024 0x284 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x024 0x284 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO04__ISP_SHUTTER_OPEN_0 0x024 0x284 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO04__SDMA1_EXT_EVENT01 0x024 0x284 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x028 0x288 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO05__M7_NMI 0x028 0x288 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO05__ISP_FL_TRIG_1 0x028 0x288 0x5D8 0x3 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO05__CCM_PMIC_READY 0x028 0x288 0x554 0x5 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x02C 0x28C 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO06__ENET_QOS_MDC 0x02C 0x28C 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO06__ISP_SHUTTER_TRIG_1 0x02C 0x28C 0x5E0 0x3 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B 0x02C 0x28C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO06__CCM_EXT_CLK3 0x02C 0x28C 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x030 0x290 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO07__ENET_QOS_MDIO 0x030 0x290 0x590 0x1 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO07__ISP_FLASH_TRIG_1 0x030 0x290 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP 0x030 0x290 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO07__CCM_EXT_CLK4 0x030 0x290 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x034 0x294 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN 0x034 0x294 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO08__PWM1_OUT 0x034 0x294 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO08__ISP_PRELIGHT_TRIG_1 0x034 0x294 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN 0x034 0x294 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO08__USDHC2_RESET_B 0x034 0x294 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x038 0x298 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x038 0x298 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x038 0x298 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO09__ISP_SHUTTER_OPEN_1 0x038 0x298 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x038 0x298 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO09__SDMA2_EXT_EVENT00 0x038 0x298 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x03C 0x29C 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x03C 0x29C 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x03C 0x29C 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x040 0x2A0 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID 0x040 0x2A0 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x040 0x2A0 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO11__USDHC3_VSELECT 0x040 0x2A0 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO11__CCM_PMIC_READY 0x040 0x2A0 0x554 0x5 0x1 +-#define MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x044 0x2A4 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x044 0x2A4 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO12__SDMA2_EXT_EVENT01 0x044 0x2A4 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x048 0x2A8 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x048 0x2A8 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT 0x048 0x2A8 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04C 0x2AC 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x04C 0x2AC 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO14__USDHC3_CD_B 0x04C 0x2AC 0x608 0x4 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x04C 0x2AC 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x04C 0x2AC 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x050 0x2B0 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x050 0x2B0 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO15__USDHC3_WP 0x050 0x2B0 0x634 0x4 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x050 0x2B0 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x050 0x2B0 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x054 0x2B4 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00 0x054 0x2B4 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 0x054 0x2B4 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ENET_MDC__USDHC3_STROBE 0x054 0x2B4 0x630 0x6 0x0 +-#define MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x058 0x2B8 0x590 0x0 0x1 +-#define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC 0x058 0x2B8 0x528 0x2 0x0 +-#define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_PDM_BIT_STREAM03 0x058 0x2B8 0x4CC 0x3 0x0 +-#define MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 0x058 0x2B8 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ENET_MDIO__USDHC3_DATA5 0x058 0x2B8 0x624 0x6 0x0 +-#define MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x05C 0x2BC 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK 0x05C 0x2BC 0x524 0x2 0x0 +-#define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_PDM_BIT_STREAM02 0x05C 0x2BC 0x4C8 0x3 0x0 +-#define MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x05C 0x2BC 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ENET_TD3__USDHC3_DATA6 0x05C 0x2BC 0x628 0x6 0x0 +-#define MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x060 0x2C0 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x060 0x2C0 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00 0x060 0x2C0 0x51C 0x2 0x0 +-#define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_PDM_BIT_STREAM01 0x060 0x2C0 0x4C4 0x3 0x0 +-#define MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 0x060 0x2C0 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ENET_TD2__USDHC3_DATA7 0x060 0x2C0 0x62C 0x6 0x0 +-#define MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x064 0x2C4 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC 0x064 0x2C4 0x520 0x2 0x0 +-#define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_PDM_BIT_STREAM00 0x064 0x2C4 0x4C0 0x3 0x0 +-#define MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 0x064 0x2C4 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ENET_TD1__USDHC3_CD_B 0x064 0x2C4 0x608 0x6 0x1 +-#define MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x068 0x2C8 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK 0x068 0x2C8 0x518 0x2 0x0 +-#define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_PDM_CLK 0x068 0x2C8 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 0x068 0x2C8 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ENET_TD0__USDHC3_WP 0x068 0x2C8 0x634 0x6 0x1 +-#define MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x06C 0x2CC 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK 0x06C 0x2CC 0x514 0x2 0x0 +-#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SPDIF1_OUT 0x06C 0x2CC 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 0x06C 0x2CC 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ENET_TX_CTL__USDHC3_DATA0 0x06C 0x2CC 0x610 0x6 0x0 +-#define MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x070 0x2D0 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_ENET_TXC__ENET_QOS_TX_ER 0x070 0x2D0 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00 0x070 0x2D0 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 0x070 0x2D0 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ENET_TXC__USDHC3_DATA1 0x070 0x2D0 0x614 0x6 0x0 +-#define MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x074 0x2D4 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC 0x074 0x2D4 0x540 0x2 0x0 +-#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_PDM_BIT_STREAM03 0x074 0x2D4 0x4CC 0x3 0x1 +-#define MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x074 0x2D4 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2 0x074 0x2D4 0x618 0x6 0x0 +-#define MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x078 0x2D8 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x078 0x2D8 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK 0x078 0x2D8 0x53C 0x2 0x0 +-#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_PDM_BIT_STREAM02 0x078 0x2D8 0x4C8 0x3 0x1 +-#define MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 0x078 0x2D8 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3 0x078 0x2D8 0x61C 0x6 0x0 +-#define MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x07C 0x2DC 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00 0x07C 0x2DC 0x534 0x2 0x0 +-#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_PDM_BIT_STREAM01 0x07C 0x2DC 0x4C4 0x3 0x1 +-#define MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 0x07C 0x2DC 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4 0x07C 0x2DC 0x620 0x6 0x0 +-#define MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x080 0x2E0 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC 0x080 0x2E0 0x538 0x2 0x0 +-#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_PDM_BIT_STREAM00 0x080 0x2E0 0x4C0 0x3 0x1 +-#define MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 0x080 0x2E0 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ENET_RD1__USDHC3_RESET_B 0x080 0x2E0 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x084 0x2E4 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK 0x084 0x2E4 0x530 0x2 0x0 +-#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_PDM_CLK 0x084 0x2E4 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x084 0x2E4 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ENET_RD2__USDHC3_CLK 0x084 0x2E4 0x604 0x6 0x0 +-#define MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x088 0x2E8 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SAI7_MCLK 0x088 0x2E8 0x52C 0x2 0x0 +-#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SPDIF1_IN 0x088 0x2E8 0x544 0x3 0x0 +-#define MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x088 0x2E8 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ENET_RD3__USDHC3_CMD 0x088 0x2E8 0x60C 0x6 0x0 +-#define MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x08C 0x2EC 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD1_CLK__ENET1_MDC 0x08C 0x2EC 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SD1_CLK__I2C5_SCL 0x08C 0x2EC 0x5C4 0x3 0x0 +-#define MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x08C 0x2EC 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SD1_CLK__UART1_DTE_RX 0x08C 0x2EC 0x5E8 0x4 0x0 +-#define MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x08C 0x2EC 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x090 0x2F0 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD1_CMD__ENET1_MDIO 0x090 0x2F0 0x57C 0x1 0x0 +-#define MX8MP_IOMUXC_SD1_CMD__I2C5_SDA 0x090 0x2F0 0x5C8 0x3 0x0 +-#define MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x090 0x2F0 0x5E8 0x4 0x1 +-#define MX8MP_IOMUXC_SD1_CMD__UART1_DTE_TX 0x090 0x2F0 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x090 0x2F0 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x094 0x2F4 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD1_DATA0__ENET1_RGMII_TD1 0x094 0x2F4 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x094 0x2F4 0x5CC 0x3 0x0 +-#define MX8MP_IOMUXC_SD1_DATA0__UART1_DCE_RTS 0x094 0x2F4 0x5E4 0x4 0x0 +-#define MX8MP_IOMUXC_SD1_DATA0__UART1_DTE_CTS 0x094 0x2F4 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x094 0x2F4 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x098 0x2F8 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD1_DATA1__ENET1_RGMII_TD0 0x098 0x2F8 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x098 0x2F8 0x5D0 0x3 0x0 +-#define MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x098 0x2F8 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SD1_DATA1__UART1_DTE_RTS 0x098 0x2F8 0x5E4 0x4 0x1 +-#define MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x098 0x2F8 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x09C 0x2FC 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD1_DATA2__ENET1_RGMII_RD0 0x09C 0x2FC 0x580 0x1 0x0 +-#define MX8MP_IOMUXC_SD1_DATA2__I2C4_SCL 0x09C 0x2FC 0x5BC 0x3 0x0 +-#define MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x09C 0x2FC 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SD1_DATA2__UART2_DTE_RX 0x09C 0x2FC 0x5F0 0x4 0x0 +-#define MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x09C 0x2FC 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x0A0 0x300 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD1_DATA3__ENET1_RGMII_RD1 0x0A0 0x300 0x584 0x1 0x0 +-#define MX8MP_IOMUXC_SD1_DATA3__I2C4_SDA 0x0A0 0x300 0x5C0 0x3 0x0 +-#define MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x0A0 0x300 0x5F0 0x4 0x1 +-#define MX8MP_IOMUXC_SD1_DATA3__UART2_DTE_TX 0x0A0 0x300 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x0A0 0x300 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x0A4 0x304 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD1_DATA4__ENET1_RGMII_TX_CTL 0x0A4 0x304 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL 0x0A4 0x304 0x5A4 0x3 0x0 +-#define MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x0A4 0x304 0x5EC 0x4 0x0 +-#define MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS 0x0A4 0x304 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x0A4 0x304 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x0A8 0x308 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD1_DATA5__ENET1_TX_ER 0x0A8 0x308 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x0A8 0x308 0x5A8 0x3 0x0 +-#define MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x0A8 0x308 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS 0x0A8 0x308 0x5EC 0x4 0x1 +-#define MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x0A8 0x308 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x0AC 0x30C 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD1_DATA6__ENET1_RGMII_RX_CTL 0x0AC 0x30C 0x588 0x1 0x0 +-#define MX8MP_IOMUXC_SD1_DATA6__I2C2_SCL 0x0AC 0x30C 0x5AC 0x3 0x0 +-#define MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x0AC 0x30C 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX 0x0AC 0x30C 0x5F8 0x4 0x0 +-#define MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x0AC 0x30C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x0B0 0x310 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD1_DATA7__ENET1_RX_ER 0x0B0 0x310 0x58C 0x1 0x0 +-#define MX8MP_IOMUXC_SD1_DATA7__I2C2_SDA 0x0B0 0x310 0x5B0 0x3 0x0 +-#define MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x0B0 0x310 0x5F8 0x4 0x1 +-#define MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX 0x0B0 0x310 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x0B0 0x310 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x0B4 0x314 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD1_RESET_B__ENET1_TX_CLK 0x0B4 0x314 0x578 0x1 0x0 +-#define MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL 0x0B4 0x314 0x5B4 0x3 0x0 +-#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x0B4 0x314 0x5F4 0x4 0x0 +-#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CTS 0x0B4 0x314 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x0B4 0x314 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x0B8 0x318 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA 0x0B8 0x318 0x5B8 0x3 0x0 +-#define MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x0B8 0x318 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS 0x0B8 0x318 0x5F4 0x4 0x1 +-#define MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x0B8 0x318 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x0BC 0x31C 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0BC 0x31C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x0C0 0x320 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD2_CLK__ECSPI2_SCLK 0x0C0 0x320 0x568 0x2 0x0 +-#define MX8MP_IOMUXC_SD2_CLK__UART4_DCE_RX 0x0C0 0x320 0x600 0x3 0x0 +-#define MX8MP_IOMUXC_SD2_CLK__UART4_DTE_TX 0x0C0 0x320 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x0C0 0x320 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x0C4 0x324 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD2_CMD__ECSPI2_MOSI 0x0C4 0x324 0x570 0x2 0x0 +-#define MX8MP_IOMUXC_SD2_CMD__UART4_DCE_TX 0x0C4 0x324 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_SD2_CMD__UART4_DTE_RX 0x0C4 0x324 0x600 0x3 0x1 +-#define MX8MP_IOMUXC_SD2_CMD__AUDIOMIX_PDM_CLK 0x0C4 0x324 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x0C4 0x324 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x0C8 0x328 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD2_DATA0__I2C4_SDA 0x0C8 0x328 0x5C0 0x2 0x1 +-#define MX8MP_IOMUXC_SD2_DATA0__UART2_DCE_RX 0x0C8 0x328 0x5F0 0x3 0x2 +-#define MX8MP_IOMUXC_SD2_DATA0__UART2_DTE_TX 0x0C8 0x328 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_PDM_BIT_STREAM00 0x0C8 0x328 0x4C0 0x4 0x2 +-#define MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x0C8 0x328 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x0CC 0x32C 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD2_DATA1__I2C4_SCL 0x0CC 0x32C 0x5BC 0x2 0x1 +-#define MX8MP_IOMUXC_SD2_DATA1__UART2_DCE_TX 0x0CC 0x32C 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_SD2_DATA1__UART2_DTE_RX 0x0CC 0x32C 0x5F0 0x3 0x3 +-#define MX8MP_IOMUXC_SD2_DATA1__AUDIOMIX_PDM_BIT_STREAM01 0x0CC 0x32C 0x4C4 0x4 0x2 +-#define MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x0CC 0x32C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x0D0 0x330 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD2_DATA2__ECSPI2_SS0 0x0D0 0x330 0x574 0x2 0x0 +-#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_SPDIF1_OUT 0x0D0 0x330 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_PDM_BIT_STREAM02 0x0D0 0x330 0x4C8 0x4 0x2 +-#define MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x0D0 0x330 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x0D4 0x334 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD2_DATA3__ECSPI2_MISO 0x0D4 0x334 0x56C 0x2 0x0 +-#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF1_IN 0x0D4 0x334 0x544 0x3 0x1 +-#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_PDM_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x2 +-#define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x0D4 0x334 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD2_DATA3__SRC_EARLY_RESET 0x0D4 0x334 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x0D8 0x338 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0D8 0x338 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD2_RESET_B__SRC_SYSTEM_RESET 0x0D8 0x338 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x0DC 0x33C 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x0DC 0x33C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SD2_WP__CORESIGHT_EVENTI 0x0DC 0x33C 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_NAND_ALE__NAND_ALE 0x0E0 0x340 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x0E0 0x340 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK 0x0E0 0x340 0x4E8 0x2 0x0 +-#define MX8MP_IOMUXC_NAND_ALE__ISP_FL_TRIG_0 0x0E0 0x340 0x5D4 0x3 0x1 +-#define MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX 0x0E0 0x340 0x5F8 0x4 0x2 +-#define MX8MP_IOMUXC_NAND_ALE__UART3_DTE_TX 0x0E0 0x340 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x0E0 0x340 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_NAND_ALE__CORESIGHT_TRACE_CLK 0x0E0 0x340 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_NAND_CE0_B__NAND_CE0_B 0x0E4 0x344 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x0E4 0x344 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00 0x0E4 0x344 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_NAND_CE0_B__ISP_SHUTTER_TRIG_0 0x0E4 0x344 0x5DC 0x3 0x1 +-#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX 0x0E4 0x344 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DTE_RX 0x0E4 0x344 0x5F8 0x4 0x3 +-#define MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x0E4 0x344 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_NAND_CE0_B__CORESIGHT_TRACE_CTL 0x0E4 0x344 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_NAND_CE1_B__NAND_CE1_B 0x0E8 0x348 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_NAND_CE1_B__FLEXSPI_A_SS1_B 0x0E8 0x348 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x0E8 0x348 0x630 0x2 0x1 +-#define MX8MP_IOMUXC_NAND_CE1_B__I2C4_SCL 0x0E8 0x348 0x5BC 0x4 0x2 +-#define MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x0E8 0x348 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_NAND_CE1_B__CORESIGHT_TRACE00 0x0E8 0x348 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_NAND_CE2_B__NAND_CE2_B 0x0EC 0x34C 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_NAND_CE2_B__FLEXSPI_B_SS0_B 0x0EC 0x34C 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x0EC 0x34C 0x624 0x2 0x1 +-#define MX8MP_IOMUXC_NAND_CE2_B__I2C4_SDA 0x0EC 0x34C 0x5C0 0x4 0x2 +-#define MX8MP_IOMUXC_NAND_CE2_B__GPIO3_IO03 0x0EC 0x34C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_NAND_CE2_B__CORESIGHT_TRACE01 0x0EC 0x34C 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_NAND_CE3_B__NAND_CE3_B 0x0F0 0x350 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_NAND_CE3_B__FLEXSPI_B_SS1_B 0x0F0 0x350 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x0F0 0x350 0x628 0x2 0x1 +-#define MX8MP_IOMUXC_NAND_CE3_B__I2C3_SDA 0x0F0 0x350 0x5B8 0x4 0x1 +-#define MX8MP_IOMUXC_NAND_CE3_B__GPIO3_IO04 0x0F0 0x350 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_NAND_CE3_B__CORESIGHT_TRACE02 0x0F0 0x350 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_NAND_CLE__NAND_CLE 0x0F4 0x354 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_NAND_CLE__FLEXSPI_B_SCLK 0x0F4 0x354 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x0F4 0x354 0x62C 0x2 0x1 +-#define MX8MP_IOMUXC_NAND_CLE__UART4_DCE_RX 0x0F4 0x354 0x600 0x4 0x2 +-#define MX8MP_IOMUXC_NAND_CLE__UART4_DTE_TX 0x0F4 0x354 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_NAND_CLE__GPIO3_IO05 0x0F4 0x354 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_NAND_CLE__CORESIGHT_TRACE03 0x0F4 0x354 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_NAND_DATA00__NAND_DATA00 0x0F8 0x358 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x0F8 0x358 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00 0x0F8 0x358 0x4E4 0x2 0x0 +-#define MX8MP_IOMUXC_NAND_DATA00__ISP_FLASH_TRIG_0 0x0F8 0x358 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX 0x0F8 0x358 0x600 0x4 0x3 +-#define MX8MP_IOMUXC_NAND_DATA00__UART4_DTE_TX 0x0F8 0x358 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x0F8 0x358 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_NAND_DATA00__CORESIGHT_TRACE04 0x0F8 0x358 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_NAND_DATA01__NAND_DATA01 0x0FC 0x35C 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x0FC 0x35C 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC 0x0FC 0x35C 0x4EC 0x2 0x0 +-#define MX8MP_IOMUXC_NAND_DATA01__ISP_PRELIGHT_TRIG_0 0x0FC 0x35C 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_NAND_DATA01__UART4_DCE_TX 0x0FC 0x35C 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_NAND_DATA01__UART4_DTE_RX 0x0FC 0x35C 0x600 0x4 0x4 +-#define MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x0FC 0x35C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_NAND_DATA01__CORESIGHT_TRACE05 0x0FC 0x35C 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_NAND_DATA02__NAND_DATA02 0x100 0x360 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x100 0x360 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_NAND_DATA02__USDHC3_CD_B 0x100 0x360 0x608 0x2 0x2 +-#define MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x100 0x360 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_NAND_DATA02__UART4_DTE_RTS 0x100 0x360 0x5FC 0x3 0x0 +-#define MX8MP_IOMUXC_NAND_DATA02__I2C4_SDA 0x100 0x360 0x5C0 0x4 0x3 +-#define MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x100 0x360 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_NAND_DATA02__CORESIGHT_TRACE06 0x100 0x360 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_NAND_DATA03__NAND_DATA03 0x104 0x364 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x104 0x364 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_NAND_DATA03__USDHC3_WP 0x104 0x364 0x634 0x2 0x2 +-#define MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x104 0x364 0x5FC 0x3 0x1 +-#define MX8MP_IOMUXC_NAND_DATA03__UART4_DTE_CTS 0x104 0x364 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_NAND_DATA03__ISP_FL_TRIG_1 0x104 0x364 0x5D8 0x4 0x1 +-#define MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x104 0x364 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_NAND_DATA03__CORESIGHT_TRACE07 0x104 0x364 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_NAND_DATA04__NAND_DATA04 0x108 0x368 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_B_DATA00 0x108 0x368 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x108 0x368 0x610 0x2 0x1 +-#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_A_DATA04 0x108 0x368 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_NAND_DATA04__ISP_SHUTTER_TRIG_1 0x108 0x368 0x5E0 0x4 0x1 +-#define MX8MP_IOMUXC_NAND_DATA04__GPIO3_IO10 0x108 0x368 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_NAND_DATA04__CORESIGHT_TRACE08 0x108 0x368 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_NAND_DATA05__NAND_DATA05 0x10C 0x36C 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_B_DATA01 0x10C 0x36C 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x10C 0x36C 0x614 0x2 0x1 +-#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_A_DATA05 0x10C 0x36C 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_NAND_DATA05__ISP_FLASH_TRIG_1 0x10C 0x36C 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_NAND_DATA05__GPIO3_IO11 0x10C 0x36C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_NAND_DATA05__CORESIGHT_TRACE09 0x10C 0x36C 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_NAND_DATA06__NAND_DATA06 0x110 0x370 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_B_DATA02 0x110 0x370 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x110 0x370 0x618 0x2 0x1 +-#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_A_DATA06 0x110 0x370 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_NAND_DATA06__ISP_PRELIGHT_TRIG_1 0x110 0x370 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_NAND_DATA06__GPIO3_IO12 0x110 0x370 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_NAND_DATA06__CORESIGHT_TRACE10 0x110 0x370 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_NAND_DATA07__NAND_DATA07 0x114 0x374 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_B_DATA03 0x114 0x374 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x114 0x374 0x61C 0x2 0x1 +-#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_A_DATA07 0x114 0x374 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_NAND_DATA07__ISP_SHUTTER_OPEN_1 0x114 0x374 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_NAND_DATA07__GPIO3_IO13 0x114 0x374 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_NAND_DATA07__CORESIGHT_TRACE11 0x114 0x374 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_NAND_DQS__NAND_DQS 0x118 0x378 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x118 0x378 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_NAND_DQS__AUDIOMIX_SAI3_MCLK 0x118 0x378 0x4E0 0x2 0x0 +-#define MX8MP_IOMUXC_NAND_DQS__ISP_SHUTTER_OPEN_0 0x118 0x378 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_NAND_DQS__I2C3_SCL 0x118 0x378 0x5B4 0x4 0x1 +-#define MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x118 0x378 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_NAND_DQS__CORESIGHT_TRACE12 0x118 0x378 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_NAND_RE_B__NAND_RE_B 0x11C 0x37C 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_NAND_RE_B__FLEXSPI_B_DQS 0x11C 0x37C 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x11C 0x37C 0x620 0x2 0x1 +-#define MX8MP_IOMUXC_NAND_RE_B__UART4_DCE_TX 0x11C 0x37C 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_NAND_RE_B__UART4_DTE_RX 0x11C 0x37C 0x600 0x4 0x5 +-#define MX8MP_IOMUXC_NAND_RE_B__GPIO3_IO15 0x11C 0x37C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_NAND_RE_B__CORESIGHT_TRACE13 0x11C 0x37C 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_NAND_READY_B__NAND_READY_B 0x120 0x380 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x120 0x380 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_NAND_READY_B__I2C3_SCL 0x120 0x380 0x5B4 0x4 0x2 +-#define MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x120 0x380 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_NAND_READY_B__CORESIGHT_TRACE14 0x120 0x380 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_NAND_WE_B__NAND_WE_B 0x124 0x384 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x124 0x384 0x604 0x2 0x1 +-#define MX8MP_IOMUXC_NAND_WE_B__I2C3_SDA 0x124 0x384 0x5B8 0x4 0x2 +-#define MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17 0x124 0x384 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_NAND_WE_B__CORESIGHT_TRACE15 0x124 0x384 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_NAND_WP_B__NAND_WP_B 0x128 0x388 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x128 0x388 0x60C 0x2 0x1 +-#define MX8MP_IOMUXC_NAND_WP_B__I2C4_SCL 0x128 0x388 0x5BC 0x4 0x3 +-#define MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18 0x128 0x388 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_NAND_WP_B__CORESIGHT_EVENTO 0x128 0x388 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x12C 0x38C 0x508 0x0 0x0 +-#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x12C 0x38C 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x12C 0x38C 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x12C 0x38C 0x5CC 0x3 0x1 +-#define MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x12C 0x38C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI5_RX_BCLK 0x130 0x390 0x4F4 0x0 0x0 +-#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01 0x130 0x390 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x130 0x390 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x130 0x390 0x5D0 0x3 0x1 +-#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0x130 0x390 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x130 0x390 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x134 0x394 0x4F8 0x0 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02 0x134 0x394 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x134 0x394 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x134 0x394 0x5C4 0x3 0x1 +-#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0x134 0x394 0x4C0 0x4 0x3 +-#define MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x134 0x394 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x138 0x398 0x4FC 0x0 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03 0x138 0x398 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x138 0x398 0x4D8 0x2 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x138 0x398 0x510 0x3 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0x138 0x398 0x4C4 0x4 0x3 +-#define MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x138 0x398 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x138 0x398 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x13C 0x39C 0x500 0x0 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04 0x13C 0x39C 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC 0x13C 0x39C 0x4D8 0x2 0x1 +-#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x13C 0x39C 0x50C 0x3 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0x13C 0x39C 0x4C8 0x4 0x3 +-#define MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x13C 0x39C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x13C 0x39C 0x54C 0x6 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x140 0x3A0 0x504 0x0 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05 0x140 0x3A0 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC 0x140 0x3A0 0x4D8 0x2 0x2 +-#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x140 0x3A0 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0x140 0x3A0 0x4CC 0x4 0x3 +-#define MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x140 0x3A0 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x140 0x3A0 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x144 0x3A4 0x4F0 0x0 0x0 +-#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x144 0x3A4 0x4D4 0x1 0x0 +-#define MX8MP_IOMUXC_SAI5_MCLK__PWM1_OUT 0x144 0x3A4 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x144 0x3A4 0x5C8 0x3 0x1 +-#define MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x144 0x3A4 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x144 0x3A4 0x550 0x6 0x0 +-#define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC 0x148 0x3A8 0x4D0 0x0 0x0 +-#define MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x148 0x3A8 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x148 0x3A8 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK 0x14C 0x3AC 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_PDM_CLK 0x14C 0x3AC 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x14C 0x3AC 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x14C 0x3AC 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x150 0x3B0 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01 0x150 0x3B0 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0x150 0x3B0 0x4C0 0x3 0x4 +-#define MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x150 0x3B0 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x150 0x3B0 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 0x154 0x3B4 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0x154 0x3B4 0x4C4 0x3 0x4 +-#define MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x154 0x3B4 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x154 0x3B4 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 0x158 0x3B8 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0x158 0x3B8 0x4C8 0x3 0x4 +-#define MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x158 0x3B8 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x158 0x3B8 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03 0x15C 0x3BC 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0x15C 0x3BC 0x4CC 0x3 0x4 +-#define MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x15C 0x3BC 0x57C 0x4 0x1 +-#define MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x15C 0x3BC 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04 0x160 0x3C0 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK 0x160 0x3C0 0x524 0x1 0x1 +-#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_RX_BCLK 0x160 0x3C0 0x518 0x2 0x1 +-#define MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x160 0x3C0 0x580 0x4 0x1 +-#define MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06 0x160 0x3C0 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_DATA05 0x164 0x3C4 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_TX_DATA00 0x164 0x3C4 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00 0x164 0x3C4 0x51C 0x2 0x1 +-#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_SYNC 0x164 0x3C4 0x4D0 0x3 0x1 +-#define MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x164 0x3C4 0x584 0x4 0x1 +-#define MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07 0x164 0x3C4 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI1_RX_DATA06 0x168 0x3C8 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_TX_SYNC 0x168 0x3C8 0x528 0x1 0x1 +-#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_RX_SYNC 0x168 0x3C8 0x520 0x2 0x1 +-#define MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x168 0x3C8 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x168 0x3C8 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_RX_DATA07 0x16C 0x3CC 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI6_MCLK 0x16C 0x3CC 0x514 0x1 0x1 +-#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_SYNC 0x16C 0x3CC 0x4D8 0x2 0x3 +-#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_DATA04 0x16C 0x3CC 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x16C 0x3CC 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x16C 0x3CC 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0x170 0x3D0 0x4D8 0x0 0x4 +-#define MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x170 0x3D0 0x588 0x4 0x1 +-#define MX8MP_IOMUXC_SAI1_TXFS__GPIO4_IO10 0x170 0x3D0 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0x174 0x3D4 0x4D4 0x0 0x1 +-#define MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x174 0x3D4 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x174 0x3D4 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0x178 0x3D8 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x178 0x3D8 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x178 0x3D8 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0x17C 0x3DC 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x17C 0x3DC 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x17C 0x3DC 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0x180 0x3E0 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x180 0x3E0 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x180 0x3E0 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0x184 0x3E4 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x184 0x3E4 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x184 0x3E4 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0x188 0x3E8 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_RX_BCLK 0x188 0x3E8 0x518 0x1 0x2 +-#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_TX_BCLK 0x188 0x3E8 0x524 0x2 0x2 +-#define MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x188 0x3E8 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x188 0x3E8 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 0x18C 0x3EC 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_RX_DATA00 0x18C 0x3EC 0x51C 0x1 0x2 +-#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00 0x18C 0x3EC 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x18C 0x3EC 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x18C 0x3EC 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 0x190 0x3F0 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_RX_SYNC 0x190 0x3F0 0x520 0x1 0x2 +-#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC 0x190 0x3F0 0x528 0x2 0x2 +-#define MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x190 0x3F0 0x58C 0x4 0x1 +-#define MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x190 0x3F0 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0x194 0x3F4 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_MCLK 0x194 0x3F4 0x514 0x1 0x2 +-#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_PDM_CLK 0x194 0x3F4 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD7__ENET1_TX_ER 0x194 0x3F4 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x194 0x3F4 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x198 0x3F8 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x198 0x3F8 0x4D4 0x2 0x2 +-#define MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x198 0x3F8 0x578 0x4 0x1 +-#define MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x198 0x3F8 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_SYNC 0x19C 0x3FC 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC 0x19C 0x3FC 0x510 0x1 0x2 +-#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_DATA01 0x19C 0x3FC 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x19C 0x3FC 0x4DC 0x3 0x0 +-#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x19C 0x3FC 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DTE_RX 0x19C 0x3FC 0x5E8 0x4 0x2 +-#define MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19C 0x3FC 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_PDM_BIT_STREAM02 0x19C 0x3FC 0x4C8 0x6 0x5 +-#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK 0x1A0 0x400 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0x1A0 0x400 0x50C 0x1 0x2 +-#define MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x1A0 0x400 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x1A0 0x400 0x5E8 0x4 0x3 +-#define MX8MP_IOMUXC_SAI2_RXC__UART1_DTE_TX 0x1A0 0x400 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1A0 0x400 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_PDM_BIT_STREAM01 0x1A0 0x400 0x4C4 0x6 0x5 +-#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0x1A4 0x404 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x1A4 0x404 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x1A4 0x404 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_TX_DATA01 0x1A4 0x404 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1A4 0x404 0x5E4 0x4 0x2 +-#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x1A4 0x404 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x1A4 0x404 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_PDM_BIT_STREAM03 0x1A4 0x404 0x4CC 0x6 0x5 +-#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0x1A8 0x408 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01 0x1A8 0x408 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT 0x1A8 0x408 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1A8 0x408 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1A8 0x408 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x1A8 0x408 0x5E4 0x4 0x3 +-#define MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x1A8 0x408 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_PDM_BIT_STREAM02 0x1A8 0x408 0x4C8 0x6 0x6 +-#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0x1AC 0x40C 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02 0x1AC 0x40C 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x1AC 0x40C 0x54C 0x3 0x1 +-#define MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1AC 0x40C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_PDM_BIT_STREAM01 0x1AC 0x40C 0x4C4 0x6 0x6 +-#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0x1B0 0x410 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03 0x1B0 0x410 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1B0 0x410 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x1B0 0x410 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN 0x1B0 0x410 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x1B0 0x410 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0x1B4 0x414 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_MCLK 0x1B4 0x414 0x4F0 0x1 0x2 +-#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN 0x1B4 0x414 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x1B4 0x414 0x550 0x3 0x1 +-#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN 0x1B4 0x414 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x1B4 0x414 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI3_MCLK 0x1B4 0x414 0x4E0 0x6 0x1 +-#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0x1B8 0x418 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x1B8 0x418 0x4DC 0x1 0x1 +-#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x1B8 0x418 0x508 0x2 0x2 +-#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 0x1B8 0x418 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SPDIF1_IN 0x1B8 0x418 0x544 0x4 0x2 +-#define MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1B8 0x418 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0x1B8 0x418 0x4C0 0x6 0x5 +-#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0x1BC 0x41C 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02 0x1BC 0x41C 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK 0x1BC 0x41C 0x4F4 0x2 0x2 +-#define MX8MP_IOMUXC_SAI3_RXC__GPT1_CLK 0x1BC 0x41C 0x59C 0x3 0x0 +-#define MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x1BC 0x41C 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI3_RXC__UART2_DTE_RTS 0x1BC 0x41C 0x5EC 0x4 0x2 +-#define MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1BC 0x41C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK 0x1BC 0x41C 0x000 0x6 0x0 +-#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1C0 0x420 0x4E4 0x0 0x1 +-#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03 0x1C0 0x420 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0x1C0 0x420 0x4F8 0x2 0x2 +-#define MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x1C0 0x420 0x5EC 0x4 0x3 +-#define MX8MP_IOMUXC_SAI3_RXD__UART2_DTE_CTS 0x1C0 0x420 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x1C0 0x420 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_PDM_BIT_STREAM01 0x1C0 0x420 0x4C4 0x6 0x7 +-#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1C4 0x424 0x4EC 0x0 0x1 +-#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1C4 0x424 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI5_RX_DATA01 0x1C4 0x424 0x4FC 0x2 0x2 +-#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01 0x1C4 0x424 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x1C4 0x424 0x5F0 0x4 0x4 +-#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX 0x1C4 0x424 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x1C4 0x424 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_PDM_BIT_STREAM03 0x1C4 0x424 0x4CC 0x6 0x6 +-#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1C8 0x428 0x4E8 0x0 0x1 +-#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02 0x1C8 0x428 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI5_RX_DATA02 0x1C8 0x428 0x500 0x2 0x2 +-#define MX8MP_IOMUXC_SAI3_TXC__GPT1_CAPTURE1 0x1C8 0x428 0x594 0x3 0x0 +-#define MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x1C8 0x428 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX 0x1C8 0x428 0x5F0 0x4 0x5 +-#define MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x1C8 0x428 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_PDM_BIT_STREAM02 0x1C8 0x428 0x4C8 0x6 0x7 +-#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x1CC 0x42C 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03 0x1CC 0x42C 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03 0x1CC 0x42C 0x504 0x2 0x2 +-#define MX8MP_IOMUXC_SAI3_TXD__GPT1_CAPTURE2 0x1CC 0x42C 0x598 0x3 0x0 +-#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SPDIF1_EXT_CLK 0x1CC 0x42C 0x548 0x4 0x0 +-#define MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x1CC 0x42C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x1D0 0x430 0x4E0 0x0 0x2 +-#define MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x1D0 0x430 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_MCLK 0x1D0 0x430 0x4F0 0x2 0x3 +-#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF1_OUT 0x1D0 0x430 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1D0 0x430 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF1_IN 0x1D0 0x430 0x544 0x6 0x3 +-#define MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1_OUT 0x1D4 0x434 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x1D4 0x434 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x1D4 0x434 0x5C4 0x2 0x2 +-#define MX8MP_IOMUXC_SPDIF_TX__GPT1_COMPARE1 0x1D4 0x434 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x1D4 0x434 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x1D4 0x434 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1_IN 0x1D8 0x438 0x544 0x0 0x4 +-#define MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT 0x1D8 0x438 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x1D8 0x438 0x5C8 0x2 0x2 +-#define MX8MP_IOMUXC_SPDIF_RX__GPT1_COMPARE2 0x1D8 0x438 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x1D8 0x438 0x54C 0x4 0x2 +-#define MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1D8 0x438 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPT1_COMPARE3 0x1DC 0x43C 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x1DC 0x43C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF1_EXT_CLK 0x1DC 0x43C 0x548 0x0 0x1 +-#define MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x1DC 0x43C 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1E0 0x440 0x558 0x0 0x0 +-#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x1E0 0x440 0x5F8 0x1 0x4 +-#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DTE_TX 0x1E0 0x440 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL 0x1E0 0x440 0x5A4 0x2 0x1 +-#define MX8MP_IOMUXC_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC 0x1E0 0x440 0x538 0x3 0x1 +-#define MX8MP_IOMUXC_ECSPI1_SCLK__GPIO5_IO06 0x1E0 0x440 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1E4 0x444 0x560 0x0 0x0 +-#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x1E4 0x444 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DTE_RX 0x1E4 0x444 0x5F8 0x1 0x5 +-#define MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA 0x1E4 0x444 0x5A8 0x2 0x1 +-#define MX8MP_IOMUXC_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK 0x1E4 0x444 0x530 0x3 0x1 +-#define MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x1E4 0x444 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1E8 0x448 0x55C 0x0 0x0 +-#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x1E8 0x448 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DTE_RTS 0x1E8 0x448 0x5F4 0x1 0x2 +-#define MX8MP_IOMUXC_ECSPI1_MISO__I2C2_SCL 0x1E8 0x448 0x5AC 0x2 0x1 +-#define MX8MP_IOMUXC_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00 0x1E8 0x448 0x534 0x3 0x1 +-#define MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x1E8 0x448 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 0x1EC 0x44C 0x564 0x0 0x0 +-#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x1EC 0x44C 0x5F4 0x1 0x3 +-#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DTE_CTS 0x1EC 0x44C 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_ECSPI1_SS0__I2C2_SDA 0x1EC 0x44C 0x5B0 0x2 0x1 +-#define MX8MP_IOMUXC_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC 0x1EC 0x44C 0x540 0x3 0x1 +-#define MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1EC 0x44C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1F0 0x450 0x568 0x0 0x1 +-#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1F0 0x450 0x600 0x1 0x6 +-#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DTE_TX 0x1F0 0x450 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_ECSPI2_SCLK__I2C3_SCL 0x1F0 0x450 0x5B4 0x2 0x3 +-#define MX8MP_IOMUXC_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK 0x1F0 0x450 0x53C 0x3 0x1 +-#define MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1F0 0x450 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1F4 0x454 0x570 0x0 0x1 +-#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1F4 0x454 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DTE_RX 0x1F4 0x454 0x600 0x1 0x7 +-#define MX8MP_IOMUXC_ECSPI2_MOSI__I2C3_SDA 0x1F4 0x454 0x5B8 0x2 0x3 +-#define MX8MP_IOMUXC_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00 0x1F4 0x454 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1F4 0x454 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1F8 0x458 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1F8 0x458 0x56C 0x0 0x1 +-#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1F8 0x458 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DTE_RTS 0x1F8 0x458 0x5FC 0x1 0x2 +-#define MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x1F8 0x458 0x5BC 0x2 0x4 +-#define MX8MP_IOMUXC_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK 0x1F8 0x458 0x52C 0x3 0x1 +-#define MX8MP_IOMUXC_ECSPI2_MISO__CCM_CLKO1 0x1F8 0x458 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x1FC 0x45C 0x574 0x0 0x1 +-#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1FC 0x45C 0x5FC 0x1 0x3 +-#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DTE_CTS 0x1FC 0x45C 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x1FC 0x45C 0x5C0 0x2 0x4 +-#define MX8MP_IOMUXC_ECSPI2_SS0__CCM_CLKO2 0x1FC 0x45C 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1FC 0x45C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x200 0x460 0x5A4 0x0 0x2 +-#define MX8MP_IOMUXC_I2C1_SCL__ENET_QOS_MDC 0x200 0x460 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x200 0x460 0x558 0x3 0x1 +-#define MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x200 0x460 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x204 0x464 0x5A8 0x0 0x2 +-#define MX8MP_IOMUXC_I2C1_SDA__ENET_QOS_MDIO 0x204 0x464 0x590 0x1 0x2 +-#define MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x204 0x464 0x560 0x3 0x1 +-#define MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x204 0x464 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x208 0x468 0x5AC 0x0 0x2 +-#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_IN 0x208 0x468 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_I2C2_SCL__USDHC3_CD_B 0x208 0x468 0x608 0x2 0x3 +-#define MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x208 0x468 0x55C 0x3 0x1 +-#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN 0x208 0x468 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x208 0x468 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x20C 0x46C 0x5B0 0x0 0x2 +-#define MX8MP_IOMUXC_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT 0x20C 0x46C 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_I2C2_SDA__USDHC3_WP 0x20C 0x46C 0x634 0x2 0x3 +-#define MX8MP_IOMUXC_I2C2_SDA__ECSPI1_SS0 0x20C 0x46C 0x564 0x3 0x1 +-#define MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x20C 0x46C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x210 0x470 0x5B4 0x0 0x4 +-#define MX8MP_IOMUXC_I2C3_SCL__PWM4_OUT 0x210 0x470 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK 0x210 0x470 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_I2C3_SCL__ECSPI2_SCLK 0x210 0x470 0x568 0x3 0x2 +-#define MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x210 0x470 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x214 0x474 0x5B8 0x0 0x4 +-#define MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x214 0x474 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK 0x214 0x474 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_I2C3_SDA__ECSPI2_MOSI 0x214 0x474 0x570 0x3 0x2 +-#define MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x214 0x474 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x218 0x478 0x5BC 0x0 0x5 +-#define MX8MP_IOMUXC_I2C4_SCL__PWM2_OUT 0x218 0x478 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x218 0x478 0x5A0 0x2 0x0 +-#define MX8MP_IOMUXC_I2C4_SCL__ECSPI2_MISO 0x218 0x478 0x56C 0x3 0x2 +-#define MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x218 0x478 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x21C 0x47C 0x5C0 0x0 0x5 +-#define MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x21C 0x47C 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_I2C4_SDA__ECSPI2_SS0 0x21C 0x47C 0x574 0x3 0x2 +-#define MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x21C 0x47C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x220 0x480 0x5E8 0x0 0x4 +-#define MX8MP_IOMUXC_UART1_RXD__UART1_DTE_TX 0x220 0x480 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x220 0x480 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x220 0x480 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x224 0x484 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_UART1_TXD__UART1_DTE_RX 0x224 0x484 0x5E8 0x0 0x5 +-#define MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x224 0x484 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x224 0x484 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x228 0x488 0x5F0 0x0 0x6 +-#define MX8MP_IOMUXC_UART2_RXD__UART2_DTE_TX 0x228 0x488 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x228 0x488 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_UART2_RXD__GPT1_COMPARE3 0x228 0x488 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x228 0x488 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x22C 0x48C 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_UART2_TXD__UART2_DTE_RX 0x22C 0x48C 0x5F0 0x0 0x7 +-#define MX8MP_IOMUXC_UART2_TXD__ECSPI3_SS0 0x22C 0x48C 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_UART2_TXD__GPT1_COMPARE2 0x22C 0x48C 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x22C 0x48C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x230 0x490 0x5F8 0x0 0x6 +-#define MX8MP_IOMUXC_UART3_RXD__UART3_DTE_TX 0x230 0x490 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x230 0x490 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x230 0x490 0x5E4 0x1 0x4 +-#define MX8MP_IOMUXC_UART3_RXD__USDHC3_RESET_B 0x230 0x490 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_UART3_RXD__GPT1_CAPTURE2 0x230 0x490 0x598 0x3 0x1 +-#define MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x230 0x490 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x230 0x490 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x234 0x494 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_UART3_TXD__UART3_DTE_RX 0x234 0x494 0x5F8 0x0 0x7 +-#define MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x234 0x494 0x5E4 0x1 0x5 +-#define MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS 0x234 0x494 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_UART3_TXD__USDHC3_VSELECT 0x234 0x494 0x000 0x2 0x0 +-#define MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 0x234 0x494 0x59C 0x3 0x1 +-#define MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x234 0x494 0x550 0x4 0x2 +-#define MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x234 0x494 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x238 0x498 0x600 0x0 0x8 +-#define MX8MP_IOMUXC_UART4_RXD__UART4_DTE_TX 0x238 0x498 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 0x238 0x498 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_UART4_RXD__UART2_DTE_RTS 0x238 0x498 0x5EC 0x1 0x4 +-#define MX8MP_IOMUXC_UART4_RXD__PCIE_CLKREQ_B 0x238 0x498 0x5A0 0x2 0x1 +-#define MX8MP_IOMUXC_UART4_RXD__GPT1_COMPARE1 0x238 0x498 0x000 0x3 0x0 +-#define MX8MP_IOMUXC_UART4_RXD__I2C6_SCL 0x238 0x498 0x5CC 0x4 0x2 +-#define MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x238 0x498 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x23C 0x49C 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_UART4_TXD__UART4_DTE_RX 0x23C 0x49C 0x600 0x0 0x9 +-#define MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS 0x23C 0x49C 0x5EC 0x1 0x5 +-#define MX8MP_IOMUXC_UART4_TXD__UART2_DTE_CTS 0x23C 0x49C 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_UART4_TXD__GPT1_CAPTURE1 0x23C 0x49C 0x594 0x3 0x1 +-#define MX8MP_IOMUXC_UART4_TXD__I2C6_SDA 0x23C 0x49C 0x5D0 0x4 0x2 +-#define MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x23C 0x49C 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x240 0x4A0 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x240 0x4A0 0x5C4 0x3 0x3 +-#define MX8MP_IOMUXC_HDMI_DDC_SCL__CAN1_TX 0x240 0x4A0 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x240 0x4A0 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x244 0x4A4 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x244 0x4A4 0x5C8 0x3 0x3 +-#define MX8MP_IOMUXC_HDMI_DDC_SDA__CAN1_RX 0x244 0x4A4 0x54C 0x4 0x3 +-#define MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x244 0x4A4 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x248 0x4A8 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL 0x248 0x4A8 0x5CC 0x3 0x3 +-#define MX8MP_IOMUXC_HDMI_CEC__CAN2_TX 0x248 0x4A8 0x000 0x4 0x0 +-#define MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x248 0x4A8 0x000 0x5 0x0 +-#define MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x24C 0x4AC 0x000 0x0 0x0 +-#define MX8MP_IOMUXC_HDMI_HPD__AUDIOMIX_HDMI_HPD_O 0x24C 0x4AC 0x000 0x1 0x0 +-#define MX8MP_IOMUXC_HDMI_HPD__I2C6_SDA 0x24C 0x4AC 0x5D0 0x3 0x3 +-#define MX8MP_IOMUXC_HDMI_HPD__CAN2_RX 0x24C 0x4AC 0x550 0x4 0x3 +-#define MX8MP_IOMUXC_HDMI_HPD__GPIO3_IO29 0x24C 0x4AC 0x000 0x5 0x0 +- +-#endif /* __DTS_IMX8MP_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mp.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mp.dtsi +deleted file mode 100644 +index 9b07b26230a1..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mp.dtsi ++++ /dev/null +@@ -1,971 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2019 NXP +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include "imx8mp-pinfunc.h" +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- ethernet0 = &fec; +- ethernet1 = &eqos; +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- gpio3 = &gpio4; +- gpio4 = &gpio5; +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- i2c3 = &i2c4; +- i2c4 = &i2c5; +- i2c5 = &i2c6; +- mmc0 = &usdhc1; +- mmc1 = &usdhc2; +- mmc2 = &usdhc3; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- spi0 = &flexspi; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- A53_0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0>; +- clock-latency = <61036>; +- clocks = <&clk IMX8MP_CLK_ARM>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- #cooling-cells = <2>; +- }; +- +- A53_1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x1>; +- clock-latency = <61036>; +- clocks = <&clk IMX8MP_CLK_ARM>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- #cooling-cells = <2>; +- }; +- +- A53_2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x2>; +- clock-latency = <61036>; +- clocks = <&clk IMX8MP_CLK_ARM>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- #cooling-cells = <2>; +- }; +- +- A53_3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x3>; +- clock-latency = <61036>; +- clocks = <&clk IMX8MP_CLK_ARM>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- #cooling-cells = <2>; +- }; +- +- A53_L2: l2-cache0 { +- compatible = "cache"; +- }; +- }; +- +- osc_32k: clock-osc-32k { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "osc_32k"; +- }; +- +- osc_24m: clock-osc-24m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "osc_24m"; +- }; +- +- clk_ext1: clock-ext1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <133000000>; +- clock-output-names = "clk_ext1"; +- }; +- +- clk_ext2: clock-ext2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <133000000>; +- clock-output-names = "clk_ext2"; +- }; +- +- clk_ext3: clock-ext3 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <133000000>; +- clock-output-names = "clk_ext3"; +- }; +- +- clk_ext4: clock-ext4 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency= <133000000>; +- clock-output-names = "clk_ext4"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- dsp_reserved: dsp@92400000 { +- reg = <0 0x92400000 0 0x2000000>; +- no-map; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- thermal-zones { +- cpu-thermal { +- polling-delay-passive = <250>; +- polling-delay = <2000>; +- thermal-sensors = <&tmu 0>; +- trips { +- cpu_alert0: trip0 { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_crit0: trip1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- cooling-device = +- <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- soc-thermal { +- polling-delay-passive = <250>; +- polling-delay = <2000>; +- thermal-sensors = <&tmu 1>; +- trips { +- soc_alert0: trip0 { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- soc_crit0: trip1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&soc_alert0>; +- cooling-device = +- <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- clock-frequency = <8000000>; +- arm,no-tick-in-suspend; +- }; +- +- soc@0 { +- compatible = "fsl,imx8mp-soc", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x0 0x3e000000>; +- nvmem-cells = <&imx8mp_uid>; +- nvmem-cell-names = "soc_unique_id"; +- +- aips1: bus@30000000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- reg = <0x30000000 0x400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- gpio1: gpio@30200000 { +- compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; +- reg = <0x30200000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 5 30>; +- }; +- +- gpio2: gpio@30210000 { +- compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; +- reg = <0x30210000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 35 21>; +- }; +- +- gpio3: gpio@30220000 { +- compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; +- reg = <0x30220000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>; +- }; +- +- gpio4: gpio@30230000 { +- compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; +- reg = <0x30230000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 82 32>; +- }; +- +- gpio5: gpio@30240000 { +- compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; +- reg = <0x30240000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 114 30>; +- }; +- +- tmu: tmu@30260000 { +- compatible = "fsl,imx8mp-tmu"; +- reg = <0x30260000 0x10000>; +- clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; +- #thermal-sensor-cells = <1>; +- }; +- +- wdog1: watchdog@30280000 { +- compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; +- reg = <0x30280000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; +- status = "disabled"; +- }; +- +- wdog2: watchdog@30290000 { +- compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; +- reg = <0x30290000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>; +- status = "disabled"; +- }; +- +- wdog3: watchdog@302a0000 { +- compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; +- reg = <0x302a0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>; +- status = "disabled"; +- }; +- +- iomuxc: pinctrl@30330000 { +- compatible = "fsl,imx8mp-iomuxc"; +- reg = <0x30330000 0x10000>; +- }; +- +- gpr: iomuxc-gpr@30340000 { +- compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; +- reg = <0x30340000 0x10000>; +- }; +- +- ocotp: efuse@30350000 { +- compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; +- reg = <0x30350000 0x10000>; +- clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; +- /* For nvmem subnodes */ +- #address-cells = <1>; +- #size-cells = <1>; +- +- imx8mp_uid: unique-id@420 { +- reg = <0x8 0x8>; +- }; +- +- cpu_speed_grade: speed-grade@10 { +- reg = <0x10 4>; +- }; +- +- eth_mac1: mac-address@90 { +- reg = <0x90 6>; +- }; +- }; +- +- anatop: anatop@30360000 { +- compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop", +- "syscon"; +- reg = <0x30360000 0x10000>; +- }; +- +- snvs: snvs@30370000 { +- compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; +- reg = <0x30370000 0x10000>; +- +- snvs_rtc: snvs-rtc-lp { +- compatible = "fsl,sec-v4.0-mon-rtc-lp"; +- regmap =<&snvs>; +- offset = <0x34>; +- interrupts = , +- ; +- clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; +- clock-names = "snvs-rtc"; +- }; +- +- snvs_pwrkey: snvs-powerkey { +- compatible = "fsl,sec-v4.0-pwrkey"; +- regmap = <&snvs>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; +- clock-names = "snvs-pwrkey"; +- linux,keycode = ; +- wakeup-source; +- status = "disabled"; +- }; +- }; +- +- clk: clock-controller@30380000 { +- compatible = "fsl,imx8mp-ccm"; +- reg = <0x30380000 0x10000>; +- #clock-cells = <1>; +- clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, +- <&clk_ext3>, <&clk_ext4>; +- clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", +- "clk_ext3", "clk_ext4"; +- assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, +- <&clk IMX8MP_CLK_A53_CORE>, +- <&clk IMX8MP_CLK_NOC>, +- <&clk IMX8MP_CLK_NOC_IO>, +- <&clk IMX8MP_CLK_GIC>, +- <&clk IMX8MP_CLK_AUDIO_AHB>, +- <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, +- <&clk IMX8MP_AUDIO_PLL1>, +- <&clk IMX8MP_AUDIO_PLL2>; +- assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, +- <&clk IMX8MP_ARM_PLL_OUT>, +- <&clk IMX8MP_SYS_PLL2_1000M>, +- <&clk IMX8MP_SYS_PLL1_800M>, +- <&clk IMX8MP_SYS_PLL2_500M>, +- <&clk IMX8MP_SYS_PLL1_800M>, +- <&clk IMX8MP_SYS_PLL1_800M>; +- assigned-clock-rates = <0>, <0>, +- <1000000000>, +- <800000000>, +- <500000000>, +- <400000000>, +- <800000000>, +- <393216000>, +- <361267200>; +- }; +- +- src: reset-controller@30390000 { +- compatible = "fsl,imx8mp-src", "syscon"; +- reg = <0x30390000 0x10000>; +- interrupts = ; +- #reset-cells = <1>; +- }; +- }; +- +- aips2: bus@30400000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- reg = <0x30400000 0x400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- pwm1: pwm@30660000 { +- compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; +- reg = <0x30660000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, +- <&clk IMX8MP_CLK_PWM1_ROOT>; +- clock-names = "ipg", "per"; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm2: pwm@30670000 { +- compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; +- reg = <0x30670000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, +- <&clk IMX8MP_CLK_PWM2_ROOT>; +- clock-names = "ipg", "per"; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm3: pwm@30680000 { +- compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; +- reg = <0x30680000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, +- <&clk IMX8MP_CLK_PWM3_ROOT>; +- clock-names = "ipg", "per"; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm4: pwm@30690000 { +- compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; +- reg = <0x30690000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, +- <&clk IMX8MP_CLK_PWM4_ROOT>; +- clock-names = "ipg", "per"; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- system_counter: timer@306a0000 { +- compatible = "nxp,sysctr-timer"; +- reg = <0x306a0000 0x20000>; +- interrupts = ; +- clocks = <&osc_24m>; +- clock-names = "per"; +- }; +- }; +- +- aips3: bus@30800000 { +- compatible = "fsl,aips-bus", "simple-bus"; +- reg = <0x30800000 0x400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- ecspi1: spi@30820000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; +- reg = <0x30820000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, +- <&clk IMX8MP_CLK_ECSPI1_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ecspi2: spi@30830000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; +- reg = <0x30830000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, +- <&clk IMX8MP_CLK_ECSPI2_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ecspi3: spi@30840000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; +- reg = <0x30840000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, +- <&clk IMX8MP_CLK_ECSPI3_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart1: serial@30860000 { +- compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; +- reg = <0x30860000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_UART1_ROOT>, +- <&clk IMX8MP_CLK_UART1_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart3: serial@30880000 { +- compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; +- reg = <0x30880000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_UART3_ROOT>, +- <&clk IMX8MP_CLK_UART3_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart2: serial@30890000 { +- compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; +- reg = <0x30890000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_UART2_ROOT>, +- <&clk IMX8MP_CLK_UART2_ROOT>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- flexcan1: can@308c0000 { +- compatible = "fsl,imx8mp-flexcan"; +- reg = <0x308c0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_IPG_ROOT>, +- <&clk IMX8MP_CLK_CAN1_ROOT>; +- clock-names = "ipg", "per"; +- assigned-clocks = <&clk IMX8MP_CLK_CAN1>; +- assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; +- assigned-clock-rates = <40000000>; +- fsl,clk-source = /bits/ 8 <0>; +- fsl,stop-mode = <&gpr 0x10 4>; +- status = "disabled"; +- }; +- +- flexcan2: can@308d0000 { +- compatible = "fsl,imx8mp-flexcan"; +- reg = <0x308d0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_IPG_ROOT>, +- <&clk IMX8MP_CLK_CAN2_ROOT>; +- clock-names = "ipg", "per"; +- assigned-clocks = <&clk IMX8MP_CLK_CAN2>; +- assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; +- assigned-clock-rates = <40000000>; +- fsl,clk-source = /bits/ 8 <0>; +- fsl,stop-mode = <&gpr 0x10 5>; +- status = "disabled"; +- }; +- +- crypto: crypto@30900000 { +- compatible = "fsl,sec-v4.0"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x30900000 0x40000>; +- ranges = <0 0x30900000 0x40000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_AHB>, +- <&clk IMX8MP_CLK_IPG_ROOT>; +- clock-names = "aclk", "ipg"; +- +- sec_jr0: jr@1000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x1000 0x1000>; +- interrupts = ; +- }; +- +- sec_jr1: jr@2000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x2000 0x1000>; +- interrupts = ; +- }; +- +- sec_jr2: jr@3000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x3000 0x1000>; +- interrupts = ; +- }; +- }; +- +- i2c1: i2c@30a20000 { +- compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x30a20000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; +- status = "disabled"; +- }; +- +- i2c2: i2c@30a30000 { +- compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x30a30000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; +- status = "disabled"; +- }; +- +- i2c3: i2c@30a40000 { +- compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x30a40000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; +- status = "disabled"; +- }; +- +- i2c4: i2c@30a50000 { +- compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x30a50000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; +- status = "disabled"; +- }; +- +- uart4: serial@30a60000 { +- compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; +- reg = <0x30a60000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_UART4_ROOT>, +- <&clk IMX8MP_CLK_UART4_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- mu: mailbox@30aa0000 { +- compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; +- reg = <0x30aa0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_MU_ROOT>; +- #mbox-cells = <2>; +- }; +- +- mu2: mailbox@30e60000 { +- compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; +- reg = <0x30e60000 0x10000>; +- interrupts = ; +- #mbox-cells = <2>; +- status = "disabled"; +- }; +- +- i2c5: i2c@30ad0000 { +- compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x30ad0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; +- status = "disabled"; +- }; +- +- i2c6: i2c@30ae0000 { +- compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x30ae0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; +- status = "disabled"; +- }; +- +- usdhc1: mmc@30b40000 { +- compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; +- reg = <0x30b40000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_DUMMY>, +- <&clk IMX8MP_CLK_NAND_USDHC_BUS>, +- <&clk IMX8MP_CLK_USDHC1_ROOT>; +- clock-names = "ipg", "ahb", "per"; +- fsl,tuning-start-tap = <20>; +- fsl,tuning-step= <2>; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usdhc2: mmc@30b50000 { +- compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; +- reg = <0x30b50000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_DUMMY>, +- <&clk IMX8MP_CLK_NAND_USDHC_BUS>, +- <&clk IMX8MP_CLK_USDHC2_ROOT>; +- clock-names = "ipg", "ahb", "per"; +- fsl,tuning-start-tap = <20>; +- fsl,tuning-step= <2>; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usdhc3: mmc@30b60000 { +- compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; +- reg = <0x30b60000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_DUMMY>, +- <&clk IMX8MP_CLK_NAND_USDHC_BUS>, +- <&clk IMX8MP_CLK_USDHC3_ROOT>; +- clock-names = "ipg", "ahb", "per"; +- fsl,tuning-start-tap = <20>; +- fsl,tuning-step= <2>; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- flexspi: spi@30bb0000 { +- compatible = "nxp,imx8mp-fspi"; +- reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; +- reg-names = "fspi_base", "fspi_mmap"; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, +- <&clk IMX8MP_CLK_QSPI_ROOT>; +- clock-names = "fspi", "fspi_en"; +- assigned-clock-rates = <80000000>; +- assigned-clocks = <&clk IMX8MP_CLK_QSPI>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- sdma1: dma-controller@30bd0000 { +- compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; +- reg = <0x30bd0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, +- <&clk IMX8MP_CLK_AHB>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; +- }; +- +- fec: ethernet@30be0000 { +- compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; +- reg = <0x30be0000 0x10000>; +- interrupts = , +- , +- , +- ; +- clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, +- <&clk IMX8MP_CLK_SIM_ENET_ROOT>, +- <&clk IMX8MP_CLK_ENET_TIMER>, +- <&clk IMX8MP_CLK_ENET_REF>, +- <&clk IMX8MP_CLK_ENET_PHY_REF>; +- clock-names = "ipg", "ahb", "ptp", +- "enet_clk_ref", "enet_out"; +- assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, +- <&clk IMX8MP_CLK_ENET_TIMER>, +- <&clk IMX8MP_CLK_ENET_REF>, +- <&clk IMX8MP_CLK_ENET_PHY_REF>; +- assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, +- <&clk IMX8MP_SYS_PLL2_100M>, +- <&clk IMX8MP_SYS_PLL2_125M>, +- <&clk IMX8MP_SYS_PLL2_50M>; +- assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; +- fsl,num-tx-queues = <3>; +- fsl,num-rx-queues = <3>; +- nvmem-cells = <ð_mac1>; +- nvmem-cell-names = "mac-address"; +- fsl,stop-mode = <&gpr 0x10 3>; +- nvmem_macaddr_swap; +- status = "disabled"; +- }; +- +- eqos: ethernet@30bf0000 { +- compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; +- reg = <0x30bf0000 0x10000>; +- interrupts = , +- ; +- interrupt-names = "macirq", "eth_wake_irq"; +- clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, +- <&clk IMX8MP_CLK_QOS_ENET_ROOT>, +- <&clk IMX8MP_CLK_ENET_QOS_TIMER>, +- <&clk IMX8MP_CLK_ENET_QOS>; +- clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; +- assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, +- <&clk IMX8MP_CLK_ENET_QOS_TIMER>, +- <&clk IMX8MP_CLK_ENET_QOS>; +- assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, +- <&clk IMX8MP_SYS_PLL2_100M>, +- <&clk IMX8MP_SYS_PLL2_125M>; +- assigned-clock-rates = <0>, <100000000>, <125000000>; +- intf_mode = <&gpr 0x4>; +- status = "disabled"; +- }; +- }; +- +- gic: interrupt-controller@38800000 { +- compatible = "arm,gic-v3"; +- reg = <0x38800000 0x10000>, +- <0x38880000 0xc0000>; +- #interrupt-cells = <3>; +- interrupt-controller; +- interrupts = ; +- interrupt-parent = <&gic>; +- }; +- +- ddr-pmu@3d800000 { +- compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; +- reg = <0x3d800000 0x400000>; +- interrupts = ; +- }; +- +- usb3_phy0: usb-phy@381f0040 { +- compatible = "fsl,imx8mp-usb-phy"; +- reg = <0x381f0040 0x40>; +- clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; +- clock-names = "phy"; +- assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; +- assigned-clock-parents = <&clk IMX8MP_CLK_24M>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- usb3_0: usb@32f10100 { +- compatible = "fsl,imx8mp-dwc3"; +- reg = <0x32f10100 0x8>; +- clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, +- <&clk IMX8MP_CLK_USB_ROOT>; +- clock-names = "hsio", "suspend"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <1>; +- dma-ranges = <0x40000000 0x40000000 0xc0000000>; +- ranges; +- status = "disabled"; +- +- usb_dwc3_0: usb@38100000 { +- compatible = "snps,dwc3"; +- reg = <0x38100000 0x10000>; +- clocks = <&clk IMX8MP_CLK_HSIO_AXI>, +- <&clk IMX8MP_CLK_USB_CORE_REF>, +- <&clk IMX8MP_CLK_USB_ROOT>; +- clock-names = "bus_early", "ref", "suspend"; +- assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; +- assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; +- assigned-clock-rates = <500000000>; +- interrupts = ; +- phys = <&usb3_phy0>, <&usb3_phy0>; +- phy-names = "usb2-phy", "usb3-phy"; +- snps,dis-u2-freeclk-exists-quirk; +- }; +- +- }; +- +- usb3_phy1: usb-phy@382f0040 { +- compatible = "fsl,imx8mp-usb-phy"; +- reg = <0x382f0040 0x40>; +- clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; +- clock-names = "phy"; +- assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; +- assigned-clock-parents = <&clk IMX8MP_CLK_24M>; +- #phy-cells = <0>; +- }; +- +- usb3_1: usb@32f10108 { +- compatible = "fsl,imx8mp-dwc3"; +- reg = <0x32f10108 0x8>; +- clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, +- <&clk IMX8MP_CLK_USB_ROOT>; +- clock-names = "hsio", "suspend"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <1>; +- dma-ranges = <0x40000000 0x40000000 0xc0000000>; +- ranges; +- status = "disabled"; +- +- usb_dwc3_1: usb@38200000 { +- compatible = "snps,dwc3"; +- reg = <0x38200000 0x10000>; +- clocks = <&clk IMX8MP_CLK_HSIO_AXI>, +- <&clk IMX8MP_CLK_USB_CORE_REF>, +- <&clk IMX8MP_CLK_USB_ROOT>; +- clock-names = "bus_early", "ref", "suspend"; +- assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; +- assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; +- assigned-clock-rates = <500000000>; +- interrupts = ; +- phys = <&usb3_phy1>, <&usb3_phy1>; +- phy-names = "usb2-phy", "usb3-phy"; +- snps,dis-u2-freeclk-exists-quirk; +- }; +- }; +- +- dsp: dsp@3b6e8000 { +- compatible = "fsl,imx8mp-dsp"; +- reg = <0x3b6e8000 0x88000>; +- mbox-names = "txdb0", "txdb1", +- "rxdb0", "rxdb1"; +- mboxes = <&mu2 2 0>, <&mu2 2 1>, +- <&mu2 3 0>, <&mu2 3 1>; +- memory-region = <&dsp_reserved>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-evk.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-evk.dts +deleted file mode 100644 +index b83df77195ec..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-evk.dts ++++ /dev/null +@@ -1,621 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2017 NXP +- * Copyright (C) 2017-2018 Pengutronix, Lucas Stach +- */ +- +-/dts-v1/; +- +-#include "imx8mq.dtsi" +- +-/ { +- model = "NXP i.MX8MQ EVK"; +- compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x00000000 0x40000000 0 0xc0000000>; +- }; +- +- pcie0_refclk: pcie0-refclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- }; +- +- reg_usdhc2_vmmc: regulator-vsd-3v3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usdhc2>; +- compatible = "regulator-fixed"; +- regulator-name = "VSD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- buck2_reg: regulator-buck2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_buck2>; +- compatible = "regulator-gpio"; +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1000000>; +- gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; +- states = <1000000 0x0 +- 900000 0x1>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ir>; +- linux,autosuspend-period = <125>; +- }; +- +- wm8524: audio-codec { +- #sound-dai-cells = <0>; +- compatible = "wlf,wm8524"; +- wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; +- }; +- +- sound-wm8524 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "wm8524-audio"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,frame-master = <&cpudai>; +- simple-audio-card,bitclock-master = <&cpudai>; +- simple-audio-card,widgets = +- "Line", "Left Line Out Jack", +- "Line", "Right Line Out Jack"; +- simple-audio-card,routing = +- "Left Line Out Jack", "LINEVOUTL", +- "Right Line Out Jack", "LINEVOUTR"; +- +- cpudai: simple-audio-card,cpu { +- sound-dai = <&sai2>; +- }; +- +- link_codec: simple-audio-card,codec { +- sound-dai = <&wm8524>; +- clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; +- }; +- }; +- +- sound-spdif { +- compatible = "fsl,imx-audio-spdif"; +- model = "imx-spdif"; +- spdif-controller = <&spdif1>; +- spdif-out; +- spdif-in; +- }; +- +- sound-hdmi-arc { +- compatible = "fsl,imx-audio-spdif"; +- model = "imx-hdmi-arc"; +- spdif-controller = <&spdif2>; +- spdif-in; +- }; +-}; +- +-&A53_0 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_1 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_2 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_3 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&ddrc { +- operating-points-v2 = <&ddrc_opp_table>; +- +- ddrc_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-25M { +- opp-hz = /bits/ 64 <25000000>; +- }; +- +- opp-100M { +- opp-hz = /bits/ 64 <100000000>; +- }; +- +- /* +- * On imx8mq B0 PLL can't be bypassed so low bus is 166M +- */ +- opp-166M { +- opp-hz = /bits/ 64 <166935483>; +- }; +- +- opp-800M { +- opp-hz = /bits/ 64 <800000000>; +- }; +- }; +-}; +- +-&dphy { +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- }; +- }; +-}; +- +-&gpio5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wifi_reset>; +- +- wl-reg-on-hog { +- gpio-hog; +- gpios = <29 GPIO_ACTIVE_HIGH>; +- output-high; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x8>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <825000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <825000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3ab { +- regulator-min-microvolt = <825000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <975000>; +- regulator-always-on; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1675000>; +- regulator-max-microvolt = <1975000>; +- regulator-always-on; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1625000>; +- regulator-max-microvolt = <1875000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3625000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +- }; +-}; +- +-&lcdif { +- status = "okay"; +-}; +- +-&mipi_dsi { +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- panel@0 { +- pinctrl-0 = <&pinctrl_mipi_dsi>; +- pinctrl-names = "default"; +- compatible = "raydium,rm67191"; +- reg = <0>; +- reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; +- dsi-lanes = <4>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&mipi_dsi_out>; +- }; +- }; +- }; +- +- ports { +- port@1 { +- reg = <1>; +- mipi_dsi_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie0>; +- reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; +- clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, +- <&clk IMX8MQ_CLK_PCIE1_AUX>, +- <&clk IMX8MQ_CLK_PCIE1_PHY>, +- <&pcie0_refclk>; +- clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; +- vph-supply = <&vgen5_reg>; +- status = "okay"; +-}; +- +-&pgc_gpu { +- power-supply = <&sw1a_reg>; +-}; +- +-&qspi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_qspi>; +- status = "okay"; +- +- n25q256a: flash@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q256a", "jedec,spi-nor"; +- spi-max-frequency = <29000000>; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <4>; +- }; +-}; +- +-&sai2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai2>; +- assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>; +- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>; +- assigned-clock-rates = <0>, <24576000>; +- status = "okay"; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +- +-&spdif1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spdif1>; +- assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>; +- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; +- assigned-clock-rates = <24576000>; +- status = "okay"; +-}; +- +-&spdif2 { +- assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>; +- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; +- assigned-clock-rates = <24576000>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usb3_phy1 { +- status = "okay"; +-}; +- +-&usb_dwc3_1 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc1 { +- assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; +- assigned-clock-rates = <400000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- vqmmc-supply = <&sw4_reg>; +- bus-width = <8>; +- non-removable; +- no-sd; +- no-sdio; +- status = "okay"; +-}; +- +-&usdhc2 { +- assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_usdhc2_vmmc>; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_buck2: vddarmgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 +- MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f +- MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f +- >; +- }; +- +- pinctrl_ir: irgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f +- >; +- }; +- +- pinctrl_mipi_dsi: mipidsigrp { +- fsl,pins = < +- MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 +- >; +- }; +- +- pinctrl_pcie0: pcie0grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 +- MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 +- >; +- }; +- +- pinctrl_qspi: qspigrp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 +- MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 +- MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 +- MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 +- MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 +- MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 +- >; +- }; +- +- pinctrl_reg_usdhc2: regusdhc2gpiogrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 +- >; +- }; +- +- pinctrl_sai2: sai2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 +- MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 +- MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 +- MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 +- MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 +- >; +- }; +- +- pinctrl_spdif1: spdif1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 +- MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 +- MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1-100grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1-200grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_gpio: usdhc2gpiogrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_wdog: wdog1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 +- >; +- }; +- +- pinctrl_wifi_reset: wifiresetgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-hummingboard-pulse.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-hummingboard-pulse.dts +deleted file mode 100644 +index 366693f31992..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-hummingboard-pulse.dts ++++ /dev/null +@@ -1,264 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2018 Jon Nettleton +- */ +- +-/dts-v1/; +- +-#include "dt-bindings/usb/pd.h" +-#include "imx8mq-sr-som.dtsi" +- +-/ { +- model = "SolidRun i.MX8MQ HummingBoard Pulse"; +- compatible = "solidrun,hummingboard-pulse", "fsl,imx8mq"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- reg_usdhc2_vmmc: regulator-usdhc2-vmmc { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2_vmmc>; +- regulator-name = "VSD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; +- }; +- +- reg_v_5v0: regulator-v-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "v_5v0"; +- regulator-max-microvolt = <5000000>; +- regulator-min-microvolt = <5000000>; +- regulator-always-on; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clock-frequency = <100000>; +- status = "okay"; +- +- typec_ptn5100: usb-typec@50 { +- compatible = "nxp,ptn5110"; +- reg = <0x50>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_typec>; +- interrupt-parent = <&gpio1>; +- interrupts = <6 IRQ_TYPE_LEVEL_LOW>; +- +- connector { +- compatible = "usb-c-connector"; +- label = "USB-C"; +- data-role = "dual"; +- power-role = "dual"; +- try-power-role = "sink"; +- source-pdos = ; +- sink-pdos = ; +- op-sink-microwatt = <9000000>; +- +- port { +- typec1_dr_sw: endpoint { +- remote-endpoint = <&usb1_drd_sw>; +- }; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- clock-frequency = <100000>; +- status = "okay"; +- +- eeprom@57 { +- compatible = "atmel,24c02"; +- reg = <0x57>; +- status = "okay"; +- }; +- +- rtc@69 { +- compatible = "abracon,ab1805"; +- reg = <0x69>; +- abracon,tc-diode = "schottky"; +- abracon,tc-resistor = <3>; +- }; +-}; +- +-&uart2 { /* J35 header */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- assigned-clocks = <&clk IMX8MQ_CLK_UART2>; +- assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; +- status = "okay"; +-}; +- +-&uart3 { /* Mikrobus */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- assigned-clocks = <&clk IMX8MQ_CLK_UART3>; +- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usdhc2 { +- assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_usdhc2_vmmc>; +- status = "okay"; +-}; +- +-&usb_dwc3_0 { +- dr_mode = "otg"; +- status = "okay"; +- +- port { +- usb1_drd_sw: endpoint { +- remote-endpoint = <&typec1_dr_sw>; +- }; +- }; +-}; +- +-&usb_dwc3_1 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb3_phy0 { +- status = "okay"; +-}; +- +-&usb3_phy1 { +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- /* MikroBus Analog */ +- MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x41 +- /* MikroBus Reset */ +- MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x41 +- /* +- * The following 2 pins need to be commented out and +- * reconfigured to enable RTS/CTS on UART3 +- */ +- /* MikroBus PWM */ +- MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x41 +- /* MikroBus INT */ +- MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f +- MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f +- MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f +- >; +- }; +- +- pinctrl_typec: typecgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16 +- MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x17059 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 +- MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 +- MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 +- /* +- * These pins are by default GPIO on the Mikro Bus +- * Header. To use RTS/CTS on UART3 comment them out +- * of the hoggrp and enable them here +- */ +- /* MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 */ +- /* MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 */ +- >; +- }; +- +- pinctrl_usdhc2_gpio: usdhc2gpiogrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 +- >; +- }; +- +- pinctrl_usdhc2_vmmc: usdhc2vmmcgpiogrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x41 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-kontron-pitx-imx8m.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-kontron-pitx-imx8m.dts +deleted file mode 100644 +index 564746d5000d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-kontron-pitx-imx8m.dts ++++ /dev/null +@@ -1,613 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree File for the Kontron pitx-imx8m board. +- * +- * Copyright (C) 2021 Heiko Thiery +- */ +- +-/dts-v1/; +- +-#include "imx8mq.dtsi" +-#include +- +-/ { +- model = "Kontron pITX-imx8m"; +- compatible = "kontron,pitx-imx8m", "fsl,imx8mq"; +- +- aliases { +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- mmc0 = &usdhc1; +- mmc1 = &usdhc2; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- spi0 = &qspi0; +- spi1 = &ecspi2; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- pcie0_refclk: pcie0-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- }; +- +- pcie1_refclk: pcie1-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- }; +- +- reg_usdhc2_vmmc: regulator-usdhc2-vmmc { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usdhc2>; +- regulator-name = "V_3V3_SD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- off-on-delay-us = <20000>; +- enable-active-high; +- }; +-}; +- +-&ecspi2 { +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; +- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; +- status = "okay"; +- +- tpm@0 { +- compatible = "infineon,slb9670"; +- reg = <0>; +- spi-max-frequency = <43000000>; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- ti,rx-internal-delay = ; +- ti,tx-internal-delay = ; +- ti,fifo-depth = ; +- reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10>; +- reset-deassert-us = <280>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic@8 { +- compatible = "fsl,pfuze100"; +- fsl,pfuze-support-disable-sw; +- reg = <0x8>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-name = "V_0V9_GPU"; +- regulator-min-microvolt = <825000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- sw1c_reg: sw1c { +- regulator-name = "V_0V9_VPU"; +- regulator-min-microvolt = <825000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- sw2_reg: sw2 { +- regulator-name = "V_1V1_NVCC_DRAM"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3ab { +- regulator-name = "V_1V0_DRAM"; +- regulator-min-microvolt = <825000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-name = "V_1V8_S0"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-name = "NC"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-name = "V_0V9_SNVS"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-name = "V_0V55_VREF_DDR"; +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-name = "V_1V5_CSI"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen2_reg: vgen2 { +- regulator-name = "V_0V9_PHY"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <975000>; +- regulator-always-on; +- }; +- +- vgen3_reg: vgen3 { +- regulator-name = "V_1V8_PHY"; +- regulator-min-microvolt = <1675000>; +- regulator-max-microvolt = <1975000>; +- regulator-always-on; +- }; +- +- vgen4_reg: vgen4 { +- regulator-name = "V_1V8_VDDA"; +- regulator-min-microvolt = <1625000>; +- regulator-max-microvolt = <1875000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-name = "V_3V3_PHY"; +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3625000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-name = "V_2V8_CAM"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- }; +- }; +- +- fan-controller@1b { +- compatible = "maxim,max6650"; +- reg = <0x1b>; +- maxim,fan-microvolt = <5000000>; +- }; +- +- rtc@32 { +- compatible = "microcrystal,rv8803"; +- reg = <0x32>; +- }; +- +- sensor@4b { +- compatible = "national,lm75b"; +- reg = <0x4b>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c32"; +- reg = <0x51>; +- pagesize = <32>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-/* M.2 B-key slot */ +-&pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie0>; +- reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; +- clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, +- <&clk IMX8MQ_CLK_PCIE1_AUX>, +- <&clk IMX8MQ_CLK_PCIE1_PHY>, +- <&pcie0_refclk>; +- clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; +- status = "okay"; +-}; +- +-/* Intel Ethernet Controller I210/I211 */ +-&pcie1 { +- clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, +- <&clk IMX8MQ_CLK_PCIE2_AUX>, +- <&clk IMX8MQ_CLK_PCIE2_PHY>, +- <&pcie1_refclk>; +- clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; +- fsl,max-link-speed = <1>; +- status = "okay"; +-}; +- +-&pgc_gpu { +- power-supply = <&sw1a_reg>; +-}; +- +-&pgc_vpu { +- power-supply = <&sw1c_reg>; +-}; +- +-&qspi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_qspi>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <4>; +- m25p,fast-read; +- spi-max-frequency = <50000000>; +- }; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- assigned-clocks = <&clk IMX8MQ_CLK_UART1>; +- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- assigned-clocks = <&clk IMX8MQ_CLK_UART2>; +- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- fsl,uart-has-rtscts; +- assigned-clocks = <&clk IMX8MQ_CLK_UART3>; +- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; +- status = "okay"; +-}; +- +-&usb3_phy0 { +- status = "okay"; +-}; +- +-&usb3_phy1 { +- status = "okay"; +-}; +- +-&usb_dwc3_0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb0>; +- dr_mode = "otg"; +- hnp-disable; +- srp-disable; +- adp-disable; +- maximum-speed = "high-speed"; +- status = "okay"; +-}; +- +-&usb_dwc3_1 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc1 { +- assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; +- assigned-clock-rates = <400000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- vqmmc-supply = <&sw4_reg>; +- bus-width = <8>; +- non-removable; +- no-sd; +- no-sdio; +- status = "okay"; +-}; +- +-&usdhc2 { +- assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +- bus-width = <4>; +- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; +- vmmc-supply = <®_usdhc2_vmmc>; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* TPM Reset */ +- MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* USB2 Hub Reset */ +- >; +- }; +- +- pinctrl_gpio: gpiogrp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* GPIO0 */ +- MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 /* GPIO1 */ +- MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* GPIO2 */ +- MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* GPIO3 */ +- MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* GPIO4 */ +- MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* GPIO5 */ +- MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* GPIO6 */ +- MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x19 /* GPIO7 */ +- >; +- }; +- +- pinctrl_pcie0: pcie0grp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x16 /* PCIE_PERST */ +- MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 /* W_DISABLE */ +- >; +- }; +- +- pinctrl_reg_usdhc2: regusdhc2gpiogrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 +- MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 +- MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f +- MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f +- MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f +- MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f +- >; +- }; +- +- pinctrl_qspi: qspigrp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 +- MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 +- MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 +- MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 +- MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 +- MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19 +- MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19 +- MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19 +- >; +- }; +- +- pinctrl_ecspi2_cs: ecspi2csgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 +- MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 +- MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 +- MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 +- MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 +- MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1-100grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1-200grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_gpio: usdhc2gpiogrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 +- MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x19 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usb0: usb0grp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x19 +- MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-librem5-devkit.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-librem5-devkit.dts +deleted file mode 100644 +index 622f3787a186..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-librem5-devkit.dts ++++ /dev/null +@@ -1,1042 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2018-2019 Purism SPC +- */ +- +-/dts-v1/; +- +-#include "dt-bindings/input/input.h" +-#include +-#include "dt-bindings/pwm/pwm.h" +-#include "dt-bindings/usb/pd.h" +-#include "imx8mq.dtsi" +- +-/ { +- model = "Purism Librem 5 devkit"; +- compatible = "purism,librem5-devkit", "fsl,imx8mq"; +- +- backlight_dsi: backlight-dsi { +- compatible = "pwm-backlight"; +- /* 200 Hz for the PAM2841 */ +- pwms = <&pwm1 0 5000000>; +- brightness-levels = <0 100>; +- num-interpolated-steps = <100>; +- /* Default brightness level (index into the array defined by */ +- /* the "brightness-levels" property) */ +- default-brightness-level = <0>; +- power-supply = <®_22v4_p>; +- }; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- btn1 { +- label = "VOL_UP"; +- gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; +- wakeup-source; +- linux,code = ; +- }; +- +- btn2 { +- label = "VOL_DOWN"; +- gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; +- wakeup-source; +- linux,code = ; +- }; +- +- wwan-wake { +- label = "WWAN_WAKE"; +- gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; +- interrupt-parent = <&gpio3>; +- interrupts = <8 IRQ_TYPE_LEVEL_LOW>; +- wakeup-source; +- linux,code = ; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_leds>; +- +- led1 { +- label = "LED 1"; +- gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- pmic_osc: clock-pmic { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "pmic_osc"; +- }; +- +- reg_1v8_p: regulator-1v8-p { +- compatible = "regulator-fixed"; +- regulator-name = "1v8_p"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <®_pwr_en>; +- }; +- +- reg_2v8_p: regulator-2v8-p { +- compatible = "regulator-fixed"; +- regulator-name = "2v8_p"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- vin-supply = <®_pwr_en>; +- }; +- +- reg_3v3_p: regulator-3v3-p { +- compatible = "regulator-fixed"; +- regulator-name = "3v3_p"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <®_pwr_en>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- reg_5v_p: regulator-5v-p { +- compatible = "regulator-fixed"; +- regulator-name = "5v_p"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <®_pwr_en>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- reg_22v4_p: regulator-22v4-p { +- compatible = "regulator-fixed"; +- regulator-name = "22v4_P"; +- regulator-min-microvolt = <22400000>; +- regulator-max-microvolt = <22400000>; +- vin-supply = <®_pwr_en>; +- }; +- +- reg_pwr_en: regulator-pwr-en { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwr_en>; +- regulator-name = "PWR_EN"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- reg_usdhc2_vmmc: regulator-usdhc2-vmmc { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2_pwr>; +- regulator-name = "VSD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- wwan_codec: sound-wwan-codec { +- compatible = "option,gtm601"; +- #sound-dai-cells = <0>; +- }; +- +- mic_mux: mic-mux { +- compatible = "simple-audio-mux"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_micsel>; +- mux-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; +- sound-name-prefix = "Mic Mux"; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hpdet>; +- simple-audio-card,aux-devs = <&speaker_amp>, <&mic_mux>; +- simple-audio-card,name = "Librem 5 Devkit"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,widgets = +- "Microphone", "Builtin Microphone", +- "Microphone", "Headset Microphone", +- "Headphone", "Headphones", +- "Speaker", "Builtin Speaker"; +- simple-audio-card,routing = +- "MIC_IN", "Mic Mux OUT", +- "Mic Mux IN1", "Headset Microphone", +- "Mic Mux IN2", "Builtin Microphone", +- "Mic Mux OUT", "Mic Bias", +- "Headphones", "HP_OUT", +- "Builtin Speaker", "Speaker Amp OUTR", +- "Speaker Amp INR", "LINE_OUT"; +- simple-audio-card,hp-det-gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; +- +- simple-audio-card,cpu { +- sound-dai = <&sai2>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&sgtl5000>; +- clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; +- frame-master; +- bitclock-master; +- }; +- }; +- +- sound-wwan { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "SIMCom SIM7100"; +- simple-audio-card,format = "dsp_a"; +- +- simple-audio-card,cpu { +- sound-dai = <&sai6>; +- }; +- +- telephony_link_master: simple-audio-card,codec { +- sound-dai = <&wwan_codec>; +- frame-master; +- bitclock-master; +- }; +- }; +- +- speaker_amp: speaker-amp { +- compatible = "simple-audio-amplifier"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spkamp>; +- VCC-supply = <®_3v3_p>; +- sound-name-prefix = "Speaker Amp"; +- enable-gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; +- }; +- +- vibrator { +- compatible = "gpio-vibrator"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_haptic>; +- enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; +- vcc-supply = <®_3v3_p>; +- }; +- +- wifi_pwr_en: regulator-wifi-en { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wifi_pwr_en>; +- regulator-name = "WIFI_EN"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +-}; +- +-&A53_0 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_1 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_2 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_3 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&dphy { +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- phy-supply = <®_3v3_p>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic: pmic@4b { +- compatible = "rohm,bd71837"; +- reg = <0x4b>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- clocks = <&pmic_osc>; +- clock-names = "osc"; +- #clock-cells = <0>; +- clock-output-names = "pmic_clk"; +- interrupt-parent = <&gpio1>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- rohm,reset-snvs-powered; +- +- regulators { +- buck1_reg: BUCK1 { +- regulator-name = "buck1"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- rohm,dvs-run-voltage = <900000>; +- rohm,dvs-idle-voltage = <850000>; +- rohm,dvs-suspend-voltage = <800000>; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "buck2"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-ramp-delay = <1250>; +- rohm,dvs-run-voltage = <1000000>; +- rohm,dvs-idle-voltage = <900000>; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "buck3"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- rohm,dvs-run-voltage = <900000>; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "buck4"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- rohm,dvs-run-voltage = <1000000>; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "buck5"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck6_reg: BUCK6 { +- regulator-name = "buck6"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck7_reg: BUCK7 { +- regulator-name = "buck7"; +- regulator-min-microvolt = <1605000>; +- regulator-max-microvolt = <1995000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck8_reg: BUCK8 { +- regulator-name = "buck8"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1_reg: LDO1 { +- regulator-name = "ldo1"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- /* leave on for snvs power button */ +- regulator-always-on; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "ldo2"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-boot-on; +- /* leave on for snvs power button */ +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "ldo4"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo5_reg: LDO5 { +- regulator-name = "ldo5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo6_reg: LDO6 { +- regulator-name = "ldo6"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo7_reg: LDO7 { +- regulator-name = "ldo7"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +- +- typec_ptn5100: usb-typec@52 { +- compatible = "nxp,ptn5110"; +- reg = <0x52>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_typec>; +- interrupt-parent = <&gpio3>; +- interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +- +- connector { +- compatible = "usb-c-connector"; +- label = "USB-C"; +- data-role = "dual"; +- power-role = "dual"; +- try-power-role = "sink"; +- source-pdos = ; +- sink-pdos = ; +- op-sink-microwatt = <10000000>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- usb_con_hs: endpoint { +- remote-endpoint = <&typec_hs>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- usb_con_ss: endpoint { +- remote-endpoint = <&typec_ss>; +- }; +- }; +- }; +- }; +- }; +- +- rtc@68 { +- compatible = "microcrystal,rv4162"; +- reg = <0x68>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rtc>; +- interrupt-parent = <&gpio4>; +- interrupts = <29 IRQ_TYPE_LEVEL_LOW>; +- }; +- +- charger@6b { /* bq25896 */ +- compatible = "ti,bq25890"; +- reg = <0x6b>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_charger>; +- interrupt-parent = <&gpio3>; +- interrupts = <25 IRQ_TYPE_EDGE_FALLING>; +- ti,battery-regulation-voltage = <4192000>; /* 4.192V */ +- ti,charge-current = <1600000>; /* 1.6A */ +- ti,termination-current = <66000>; /* 66mA */ +- ti,precharge-current = <130000>; /* 130mA */ +- ti,minimum-sys-voltage = <3000000>; /* 3V */ +- ti,boost-voltage = <5000000>; /* 5V */ +- ti,boost-max-current = <50000>; /* 50mA */ +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- magnetometer@1e { +- compatible = "st,lsm9ds1-magn"; +- reg = <0x1e>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_imu>; +- interrupt-parent = <&gpio3>; +- interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; +- vdd-supply = <®_3v3_p>; +- vddio-supply = <®_3v3_p>; +- }; +- +- sgtl5000: audio-codec@a { +- compatible = "fsl,sgtl5000"; +- clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; +- assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; +- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; +- assigned-clock-rates = <24576000>; +- #sound-dai-cells = <0>; +- reg = <0x0a>; +- VDDD-supply = <®_1v8_p>; +- VDDIO-supply = <®_3v3_p>; +- VDDA-supply = <®_3v3_p>; +- }; +- +- touchscreen@5d { +- compatible = "goodix,gt5688"; +- reg = <0x5d>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ts>; +- interrupt-parent = <&gpio3>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; +- touchscreen-size-x = <720>; +- touchscreen-size-y = <1440>; +- AVDD28-supply = <®_2v8_p>; +- VDDIO-supply = <®_1v8_p>; +- }; +- +- proximity-sensor@60 { +- compatible = "vishay,vcnl4040"; +- reg = <0x60>; +- pinctrl-0 = <&pinctrl_prox>; +- }; +- +- accel-gyro@6a { +- compatible = "st,lsm9ds1-imu"; +- reg = <0x6a>; +- vdd-supply = <®_3v3_p>; +- vddio-supply = <®_3v3_p>; +- mount-matrix = "1", "0", "0", +- "0", "1", "0", +- "0", "0", "-1"; +- }; +-}; +- +-&iomuxc { +- pinctrl_bl: blgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* DSI_BL_PWM */ +- >; +- }; +- +- pinctrl_bt: btgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 /* nBT_DISABLE */ +- MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10 /* BT_HOST_WAKE */ +- >; +- }; +- +- pinctrl_charger: chargergrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80 /* CHRG_nINT */ +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 +- MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 +- MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f +- >; +- }; +- +- pinctrl_ts: tsgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16 /* TOUCH INT */ +- MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* TOUCH RST */ +- >; +- }; +- +- pinctrl_gpio_leds: gpioledgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16 +- >; +- }; +- +- pinctrl_gpio_keys: gpiokeygrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16 +- MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16 +- MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */ +- >; +- }; +- +- pinctrl_haptic: hapticgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0xc6 /* nHAPTIC */ +- >; +- }; +- +- pinctrl_hpdet: hpdetgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0xC0 /* HP_DET */ +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f +- MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f +- MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f +- >; +- }; +- +- pinctrl_imu: imugrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8 /* IMU_INT */ +- >; +- }; +- +- pinctrl_micsel: micselgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc6 /* MIC_SEL */ +- >; +- }; +- +- pinctrl_spkamp: spkamp { +- fsl,pins = < +- MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x81 /* MUTE */ +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80 /* PMIC intr */ +- >; +- }; +- +- pinctrl_prox: proxgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x80 /* prox intr */ +- >; +- }; +- +- pinctrl_pwr_en: pwrengrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06 +- >; +- }; +- +- pinctrl_rtc: rtcgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80 /* RTC intr */ +- >; +- }; +- +- pinctrl_sai2: sai2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 +- MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 +- MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 +- MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 +- MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 +- >; +- }; +- +- pinctrl_sai6: sai6grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6 +- MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6 +- MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6 +- MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6 +- >; +- }; +- +- pinctrl_typec: typecgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16 +- MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 +- MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 +- MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 +- MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 +- MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 +- MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 +- MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 +- MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 +- MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 +- MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_pwr: usdhc2pwrgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 +- >; +- }; +- +- pinctrl_usdhc2_gpio: usdhc2gpiogrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */ +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 +- >; +- }; +- +- pinctrl_wifi_pwr_en: wifipwrengrp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06 +- >; +- }; +- +- pinctrl_wwan: wwangrp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09 /* nWWAN_DISABLE */ +- MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */ +- MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */ +- >; +- }; +-}; +- +-&lcdif { +- status = "okay"; +-}; +- +-&mipi_dsi { +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- panel@0 { +- compatible = "rocktech,jh057n00900"; +- reg = <0>; +- backlight = <&backlight_dsi>; +- reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; +- iovcc-supply = <®_1v8_p>; +- vcc-supply = <®_2v8_p>; +- port { +- panel_in: endpoint { +- remote-endpoint = <&mipi_dsi_out>; +- }; +- }; +- }; +- +- ports { +- port@1 { +- reg = <1>; +- mipi_dsi_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&pgc_gpu { +- power-supply = <&buck3_reg>; +-}; +- +-&pgc_vpu { +- power-supply = <&buck4_reg>; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_bl>; +- status = "okay"; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +- +-&snvs_rtc { +- status = "disabled"; +-}; +- +-&sai2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai2>; +- assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; +- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; +- assigned-clock-rates = <24576000>; +- status = "okay"; +-}; +- +-&sai6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai6>; +- assigned-clocks = <&clk IMX8MQ_CLK_SAI6>; +- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; +- assigned-clock-rates = <24576000>; +- fsl,sai-synchronous-rx; +- status = "okay"; +-}; +- +-&uart1 { /* console */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart3 { /* GNSS */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&uart4 { /* BT */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usb3_phy0 { +- vbus-supply = <®_5v_p>; +- status = "okay"; +-}; +- +-&usb3_phy1 { +- vbus-supply = <®_5v_p>; +- status = "okay"; +-}; +- +-&usb_dwc3_0 { +- #address-cells = <1>; +- #size-cells = <0>; +- dr_mode = "otg"; +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- typec_hs: endpoint { +- remote-endpoint = <&usb_con_hs>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- typec_ss: endpoint { +- remote-endpoint = <&usb_con_ss>; +- }; +- }; +-}; +- +-&usb_dwc3_1 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc1 { +- assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; +- assigned-clock-rates = <400000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&usdhc2 { +- assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>; +- bus-width = <4>; +- vmmc-supply = <®_usdhc2_vmmc>; +- power-supply = <&wifi_pwr_en>; +- broken-cd; +- disable-wp; +- cap-sdio-irq; +- keep-power-in-suspend; +- wakeup-source; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-librem5-r2.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-librem5-r2.dts +deleted file mode 100644 +index 73bd431cbd6a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-librem5-r2.dts ++++ /dev/null +@@ -1,29 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2020 Purism SPC +-// +-// Librem 5 Chestnut +- +-/dts-v1/; +- +-#include "imx8mq-librem5.dtsi" +- +-/ { +- model = "Purism Librem 5r2"; +- compatible = "purism,librem5r2", "purism,librem5", "fsl,imx8mq"; +-}; +- +-&bq25895 { +- ti,battery-regulation-voltage = <4192000>; /* uV */ +- ti,charge-current = <1600000>; /* uA */ +- ti,termination-current = <66000>; /* uA */ +-}; +- +-&accel_gyro { +- mount-matrix = "1", "0", "0", +- "0", "-1", "0", +- "0", "0", "1"; +-}; +- +-&proximity { +- proximity-near-level = <120>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-librem5-r3.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-librem5-r3.dts +deleted file mode 100644 +index cd3c3edd48fa..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-librem5-r3.dts ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2020 Purism SPC +- +-/dts-v1/; +- +-#include "imx8mq-librem5.dtsi" +- +-/ { +- model = "Purism Librem 5r3"; +- compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq"; +-}; +- +-&a53_opp_table { +- opp-1000000000 { +- opp-microvolt = <1000000>; +- }; +-}; +- +-&accel_gyro { +- mount-matrix = "1", "0", "0", +- "0", "1", "0", +- "0", "0", "-1"; +-}; +- +-&bq25895 { +- ti,battery-regulation-voltage = <4200000>; /* uV */ +- ti,charge-current = <1500000>; /* uA */ +- ti,termination-current = <144000>; /* uA */ +-}; +- +-&buck3_reg { +- regulator-always-on; +-}; +- +-&proximity { +- proximity-near-level = <25>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-librem5-r4.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-librem5-r4.dts +deleted file mode 100644 +index cbfb49aa2563..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-librem5-r4.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (C) 2020 Purism SPC +- +-/dts-v1/; +- +-#include "imx8mq-librem5.dtsi" +- +-/ { +- model = "Purism Librem 5r4"; +- compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq"; +-}; +- +-&accel_gyro { +- mount-matrix = "1", "0", "0", +- "0", "1", "0", +- "0", "0", "-1"; +-}; +- +-&bat { +- maxim,rsns-microohm = <1667>; +-}; +- +-&bq25895 { +- ti,battery-regulation-voltage = <4200000>; /* uV */ +- ti,charge-current = <1500000>; /* uA */ +- ti,termination-current = <144000>; /* uA */ +-}; +- +-&led_backlight { +- led-max-microamp = <25000>; +-}; +- +-&proximity { +- proximity-near-level = <10>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-librem5.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-librem5.dtsi +deleted file mode 100644 +index 460ef0d86540..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-librem5.dtsi ++++ /dev/null +@@ -1,1215 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2018-2020 Purism SPC +- */ +- +-/dts-v1/; +- +-#include "dt-bindings/input/input.h" +-#include +-#include "dt-bindings/pwm/pwm.h" +-#include "dt-bindings/usb/pd.h" +-#include "imx8mq.dtsi" +- +-/ { +- model = "Purism Librem 5"; +- compatible = "purism,librem5", "fsl,imx8mq"; +- +- backlight_dsi: backlight-dsi { +- compatible = "led-backlight"; +- leds = <&led_backlight>; +- }; +- +- pmic_osc: clock-pmic { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "pmic_osc"; +- }; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_keys>; +- +- vol-down { +- label = "VOL_DOWN"; +- gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- vol-up { +- label = "VOL_UP"; +- gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- reg_aud_1v8: regulator-audio-1v8 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_audiopwr>; +- regulator-name = "AUDIO_PWR_EN"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_gnss: regulator-gnss { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gnsspwr>; +- regulator-name = "GNSS"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio3 12 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_hub: regulator-hub { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hub_pwr>; +- regulator-name = "HUB"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_lcd_1v8: regulator-lcd-1v8 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dsien>; +- regulator-name = "LCD_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <®_vdd_1v8>; +- gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- /* Otherwise i2c3 is not functional */ +- regulator-always-on; +- }; +- +- reg_lcd_3v4: regulator-lcd-3v4 { +- compatible = "regulator-fixed"; +- regulator-name = "LCD_3V4"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dsibiasen>; +- vin-supply = <®_vsys_3v4>; +- gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_vdd_sen: regulator-vdd-sen { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_SEN"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_vdd_1v8: regulator-vdd-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&buck7_reg>; +- }; +- +- reg_vdd_3v3: regulator-vdd-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_vsys_3v4: regulator-vsys-3v4 { +- compatible = "regulator-fixed"; +- regulator-name = "VSYS_3V4"; +- regulator-min-microvolt = <3400000>; +- regulator-max-microvolt = <3400000>; +- regulator-always-on; +- }; +- +- reg_wifi_3v3: regulator-wifi-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3V3_WIFI"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hp>; +- simple-audio-card,name = "Librem 5"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,widgets = +- "Headphone", "Headphones", +- "Microphone", "Headset Mic", +- "Microphone", "Digital Mic", +- "Speaker", "Speaker"; +- simple-audio-card,routing = +- "Headphones", "HPOUTL", +- "Headphones", "HPOUTR", +- "Speaker", "SPKOUTL", +- "Speaker", "SPKOUTR", +- "Headset Mic", "MICBIAS", +- "IN3R", "Headset Mic", +- "DMICDAT", "Digital Mic"; +- simple-audio-card,hp-det-gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; +- +- simple-audio-card,cpu { +- sound-dai = <&sai2>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&codec>; +- clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; +- frame-master; +- bitclock-master; +- }; +- }; +- +- sound-wwan { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "Modem"; +- simple-audio-card,format = "i2s"; +- +- simple-audio-card,cpu { +- sound-dai = <&sai6>; +- frame-inversion; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&bm818_codec>; +- frame-master; +- bitclock-master; +- }; +- }; +- +- bm818_codec: sound-wwan-codec { +- compatible = "broadmobi,bm818", "option,gtm601"; +- #sound-dai-cells = <0>; +- }; +- +- vibrator { +- compatible = "pwm-vibrator"; +- pwms = <&pwm1 0 1000000000 0>; +- pwm-names = "enable"; +- vcc-supply = <®_vdd_3v3>; +- }; +-}; +- +-&A53_0 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_1 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_2 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&A53_3 { +- cpu-supply = <&buck2_reg>; +-}; +- +-&ddrc { +- operating-points-v2 = <&ddrc_opp_table>; +- +- ddrc_opp_table: ddrc-opp-table { +- compatible = "operating-points-v2"; +- +- opp-25M { +- opp-hz = /bits/ 64 <25000000>; +- }; +- +- opp-100M { +- opp-hz = /bits/ 64 <100000000>; +- }; +- +- opp-800M { +- opp-hz = /bits/ 64 <800000000>; +- }; +- }; +-}; +- +-&dphy { +- status = "okay"; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- nor_flash: flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "protected0"; +- reg = <0x0 0x30000>; +- read-only; +- }; +- +- partition@30000 { +- label = "protected1"; +- reg = <0x30000 0x10000>; +- read-only; +- }; +- +- partition@40000 { +- label = "rw"; +- reg = <0x40000 0x1C0000>; +- }; +- }; +-}; +- +-&gpio1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic_5v>; +- +- pmic-5v-hog { +- gpio-hog; +- gpios = <1 GPIO_ACTIVE_HIGH>; +- input; +- lane-mapping = "pmic-5v"; +- }; +-}; +- +-&iomuxc { +- pinctrl_audiopwr: audiopwrgrp { +- fsl,pins = < +- /* AUDIO_POWER_EN_3V3 */ +- MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x83 +- >; +- }; +- +- pinctrl_bl: blgrp { +- fsl,pins = < +- /* BACKLINGE_EN */ +- MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x83 +- >; +- }; +- +- pinctrl_charger_in: chargeringrp { +- fsl,pins = < +- /* CHRG_INT */ +- MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x80 +- /* CHG_STATUS_B */ +- MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x80 +- >; +- }; +- +- pinctrl_dsibiasen: dsibiasengrp { +- fsl,pins = < +- /* DSI_BIAS_EN */ +- MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x83 +- >; +- }; +- +- pinctrl_dsien: dsiengrp { +- fsl,pins = < +- /* DSI_EN_3V3 */ +- MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x83 +- >; +- }; +- +- pinctrl_dsirst: dsirstgrp { +- fsl,pins = < +- /* DSI_RST */ +- MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x83 +- /* DSI_TE */ +- MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x83 +- /* TP_RST */ +- MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x83 +- >; +- }; +- +- pinctrl_ecspi1: ecspigrp { +- fsl,pins = < +- MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x83 +- MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x83 +- MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 +- MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x83 +- >; +- }; +- +- pinctrl_gauge: gaugegrp { +- fsl,pins = < +- /* BAT_LOW */ +- MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x80 +- >; +- }; +- +- pinctrl_gnsspwr: gnsspwrgrp { +- fsl,pins = < +- /* GPS3V3_EN */ +- MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x83 +- >; +- }; +- +- pinctrl_haptic: hapticgrp { +- fsl,pins = < +- /* MOTO */ +- MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x83 +- >; +- }; +- +- pinctrl_hp: hpgrp { +- fsl,pins = < +- /* HEADPHONE_DET_1V8 */ +- MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x180 +- >; +- }; +- +- pinctrl_hub_pwr: hubpwrgrp { +- fsl,pins = < +- /* HUB_PWR_3V3_EN */ +- MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x83 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000026 +- MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000026 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000026 +- MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000026 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000026 +- MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000026 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000026 +- MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000026 +- >; +- }; +- +- pinctrl_keys: keysgrp { +- fsl,pins = < +- /* VOL- */ +- MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x01C0 +- /* VOL+ */ +- MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x01C0 +- >; +- }; +- +- pinctrl_led_b: ledbgrp { +- fsl,pins = < +- /* LED_B */ +- MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x06 +- >; +- }; +- +- pinctrl_led_g: ledggrp { +- fsl,pins = < +- /* LED_G */ +- MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x06 +- >; +- }; +- +- pinctrl_led_r: ledrgrp { +- fsl,pins = < +- /* LED_R */ +- MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x06 +- >; +- }; +- +- pinctrl_mag: maggrp { +- fsl,pins = < +- /* INT_MAG */ +- MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x80 +- >; +- }; +- +- pinctrl_pmic: pmicgrp { +- fsl,pins = < +- /* PMIC_NINT */ +- MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x80 +- >; +- }; +- +- pinctrl_pmic_5v: pmic5vgrp { +- fsl,pins = < +- /* PMIC_5V */ +- MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x80 +- >; +- }; +- +- pinctrl_prox: proxgrp { +- fsl,pins = < +- /* INT_LIGHT */ +- MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x80 +- >; +- }; +- +- pinctrl_rtc: rtcgrp { +- fsl,pins = < +- /* RTC_INT */ +- MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x80 +- >; +- }; +- +- pinctrl_sai2: sai2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 +- MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 +- MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 +- MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 +- MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 +- >; +- }; +- +- pinctrl_sai6: sai6grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6 +- MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6 +- MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6 +- MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6 +- >; +- }; +- +- pinctrl_tcpc: tcpcgrp { +- fsl,pins = < +- /* TCPC_INT */ +- MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x01C0 +- >; +- }; +- +- pinctrl_touch: touchgrp { +- fsl,pins = < +- /* TP_INT */ +- MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x80 +- >; +- }; +- +- pinctrl_typec: typecgrp { +- fsl,pins = < +- /* TYPEC_MUX_EN */ +- MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x83 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 +- MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 +- MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 +- MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 +- MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 +- MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 +- MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1grp100mhz { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1grp200mhz { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 +- MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2grp100mhz { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd +- MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2grp200mhz { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf +- MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- /* nWDOG */ +- MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x1f +- >; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <387000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- typec_pd: usb-pd@3f { +- compatible = "ti,tps6598x"; +- reg = <0x3f>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_typec>, <&pinctrl_tcpc>; +- interrupt-parent = <&gpio1>; +- interrupts = <10 IRQ_TYPE_LEVEL_LOW>; +- interrupt-names = "irq"; +- +- connector { +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- usb_con_hs: endpoint { +- remote-endpoint = <&typec_hs>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- usb_con_ss: endpoint { +- remote-endpoint = <&typec_ss>; +- }; +- }; +- }; +- }; +- }; +- +- pmic: pmic@4b { +- compatible = "rohm,bd71837"; +- reg = <0x4b>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- clocks = <&pmic_osc>; +- clock-names = "osc"; +- clock-output-names = "pmic_clk"; +- interrupt-parent = <&gpio1>; +- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; +- rohm,reset-snvs-powered; +- +- regulators { +- buck1_reg: BUCK1 { +- regulator-name = "buck1"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-ramp-delay = <1250>; +- rohm,dvs-run-voltage = <900000>; +- rohm,dvs-idle-voltage = <850000>; +- rohm,dvs-suspend-voltage = <800000>; +- regulator-always-on; +- }; +- +- buck2_reg: BUCK2 { +- regulator-name = "buck2"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-ramp-delay = <1250>; +- rohm,dvs-run-voltage = <1000000>; +- rohm,dvs-idle-voltage = <900000>; +- regulator-always-on; +- }; +- +- buck3_reg: BUCK3 { +- regulator-name = "buck3"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- rohm,dvs-run-voltage = <900000>; +- }; +- +- buck4_reg: BUCK4 { +- regulator-name = "buck4"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- rohm,dvs-run-voltage = <1000000>; +- }; +- +- buck5_reg: BUCK5 { +- regulator-name = "buck5"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck6_reg: BUCK6 { +- regulator-name = "buck6"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck7_reg: BUCK7 { +- regulator-name = "buck7"; +- regulator-min-microvolt = <1605000>; +- regulator-max-microvolt = <1995000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck8_reg: BUCK8 { +- regulator-name = "buck8"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1_reg: LDO1 { +- regulator-name = "ldo1"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- /* leave on for snvs power button */ +- regulator-always-on; +- }; +- +- ldo2_reg: LDO2 { +- regulator-name = "ldo2"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-boot-on; +- /* leave on for snvs power button */ +- regulator-always-on; +- }; +- +- ldo3_reg: LDO3 { +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo4_reg: LDO4 { +- regulator-name = "ldo4"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo5_reg: LDO5 { +- /* VDD_PHY_0V9 - MIPI and HDMI domains */ +- regulator-name = "ldo5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- ldo6_reg: LDO6 { +- /* VDD_PHY_0V9 - MIPI, HDMI and USB domains */ +- regulator-name = "ldo6"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo7_reg: LDO7 { +- /* VDD_PHY_3V3 - USB domain */ +- regulator-name = "ldo7"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +- +- rtc@68 { +- compatible = "microcrystal,rv4162"; +- reg = <0x68>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_rtc>; +- interrupt-parent = <&gpio1>; +- interrupts = <9 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <387000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- magnetometer@1e { +- compatible = "st,lsm9ds1-magn"; +- reg = <0x1e>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mag>; +- interrupt-parent = <&gpio3>; +- interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; +- vdd-supply = <®_vdd_sen>; +- vddio-supply = <®_vdd_1v8>; +- }; +- +- regulator@3e { +- compatible = "tps65132"; +- reg = <0x3e>; +- +- reg_lcd_avdd: outp { +- regulator-name = "LCD_AVDD"; +- vin-supply = <®_lcd_3v4>; +- }; +- +- reg_lcd_avee: outn { +- regulator-name = "LCD_AVEE"; +- vin-supply = <®_lcd_3v4>; +- }; +- }; +- +- proximity: prox@60 { +- compatible = "vishay,vcnl4040"; +- reg = <0x60>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_prox>; +- interrupt-parent = <&gpio3>; +- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; +- }; +- +- accel_gyro: accel-gyro@6a { +- compatible = "st,lsm9ds1-imu"; +- reg = <0x6a>; +- vdd-supply = <®_vdd_sen>; +- vddio-supply = <®_vdd_1v8>; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <387000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- codec: audio-codec@1a { +- compatible = "wlf,wm8962"; +- reg = <0x1a>; +- clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; +- assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; +- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; +- assigned-clock-rates = <24576000>; +- #sound-dai-cells = <0>; +- mic-cfg = <0x200>; +- DCVDD-supply = <®_aud_1v8>; +- DBVDD-supply = <®_aud_1v8>; +- AVDD-supply = <®_aud_1v8>; +- CPVDD-supply = <®_aud_1v8>; +- MICVDD-supply = <®_aud_1v8>; +- PLLVDD-supply = <®_aud_1v8>; +- SPKVDD1-supply = <®_vsys_3v4>; +- SPKVDD2-supply = <®_vsys_3v4>; +- gpio-cfg = < +- 0x0000 /* n/c */ +- 0x0001 /* gpio2, 1: default */ +- 0x0013 /* gpio3, 2: dmicclk */ +- 0x0000 /* n/c, 3: default */ +- 0x8014 /* gpio5, 4: dmic_dat */ +- 0x0000 /* gpio6, 5: default */ +- >; +- }; +- +- backlight@36 { +- compatible = "ti,lm36922"; +- reg = <0x36>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_bl>; +- #address-cells = <1>; +- #size-cells = <0>; +- enable-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; +- vled-supply = <®_vsys_3v4>; +- ti,ovp-microvolt = <25000000>; +- +- led_backlight: led@0 { +- reg = <0>; +- label = ":backlight"; +- linux,default-trigger = "backlight"; +- led-max-microamp = <20000>; +- }; +- }; +- +- touchscreen@38 { +- compatible = "edt,edt-ft5506"; +- reg = <0x38>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_touch>; +- interrupt-parent = <&gpio1>; +- interrupts = <27 IRQ_TYPE_EDGE_FALLING>; +- touchscreen-size-x = <720>; +- touchscreen-size-y = <1440>; +- vcc-supply = <®_lcd_1v8>; +- }; +-}; +- +-&i2c4 { +- clock-frequency = <387000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +- +- bat: fuel-gauge@36 { +- compatible = "maxim,max17055"; +- reg = <0x36>; +- interrupt-parent = <&gpio3>; +- interrupts = <20 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gauge>; +- maxim,over-heat-temp = <700>; +- maxim,over-volt = <4500>; +- maxim,rsns-microohm = <5000>; +- }; +- +- bq25895: charger@6a { +- compatible = "ti,bq25895", "ti,bq25890"; +- reg = <0x6a>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_charger_in>; +- interrupt-parent = <&gpio3>; +- interrupts = <3 IRQ_TYPE_EDGE_FALLING>; +- phys = <&usb3_phy0>; +- ti,precharge-current = <130000>; /* uA */ +- ti,minimum-sys-voltage = <3700000>; /* uV */ +- ti,boost-voltage = <5000000>; /* uV */ +- ti,boost-max-current = <500000>; /* uA */ +- ti,use-vinmin-threshold = <1>; /* enable VINDPM */ +- ti,vinmin-threshold = <3900000>; /* uV */ +- monitored-battery = <&bat>; +- power-supplies = <&typec_pd>; +- }; +-}; +- +-&lcdif { +- status = "okay"; +-}; +- +-&mipi_dsi { +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- lcd_panel: panel@0 { +- compatible = "mantix,mlaf057we51-x"; +- reg = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_dsirst>; +- avdd-supply = <®_lcd_avdd>; +- avee-supply = <®_lcd_avee>; +- vddi-supply = <®_lcd_1v8>; +- backlight = <&backlight_dsi>; +- reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&mipi_dsi_out>; +- }; +- }; +- }; +- +- ports { +- port@1 { +- reg = <1>; +- +- mipi_dsi_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&pgc_gpu { +- power-supply = <&buck3_reg>; +-}; +- +-&pgc_mipi { +- power-supply = <&ldo5_reg>; +-}; +- +-&pgc_vpu { +- power-supply = <&buck4_reg>; +-}; +- +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_haptic>; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led_b>; +- status = "okay"; +-}; +- +-&pwm3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led_g>; +- status = "okay"; +-}; +- +-&pwm4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_led_r>; +- status = "okay"; +-}; +- +-&sai2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai2>; +- assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; +- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; +- assigned-clock-rates = <24576000>; +- status = "okay"; +-}; +- +-&sai6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai6>; +- assigned-clocks = <&clk IMX8MQ_CLK_SAI6>; +- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; +- assigned-clock-rates = <24576000>; +- fsl,sai-synchronous-rx; +- status = "okay"; +-}; +- +-&snvs_pwrkey { +- status = "okay"; +-}; +- +-&snvs_rtc { +- status = "disabled"; +-}; +- +-&uart1 { /* console */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { /* TPS - GPS - DEBUG */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +- +- gnss { +- compatible = "globaltop,pa6h"; +- vcc-supply = <®_gnss>; +- current-speed = <9600>; +- }; +-}; +- +-&uart3 { /* SMC */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- status = "okay"; +-}; +- +-&uart4 { /* BT */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&usb3_phy0 { +- status = "okay"; +-}; +- +-&usb3_phy1 { +- vbus-supply = <®_hub>; +- status = "okay"; +-}; +- +-&usb_dwc3_0 { +- #address-cells = <1>; +- #size-cells = <0>; +- dr_mode = "otg"; +- snps,dis_u3_susphy_quirk; +- status = "okay"; +- +- port@0 { +- reg = <0>; +- +- typec_hs: endpoint { +- remote-endpoint = <&usb_con_hs>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- typec_ss: endpoint { +- remote-endpoint = <&usb_con_ss>; +- }; +- }; +-}; +- +-&usb_dwc3_1 { +- dr_mode = "host"; +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Microchip USB2642 */ +- hub@1 { +- compatible = "usb424,2640"; +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- mass-storage@1 { +- compatible = "usb424,4041"; +- reg = <1>; +- }; +- }; +-}; +- +-&usdhc1 { +- assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; +- assigned-clock-rates = <400000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- bus-width = <8>; +- vmmc-supply = <®_vdd_3v3>; +- power-supply = <®_vdd_1v8>; +- non-removable; +- status = "okay"; +-}; +- +-&usdhc2 { +- assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>; +- bus-width = <4>; +- vmmc-supply = <®_wifi_3v3>; +- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- disable-wp; +- cap-sdio-irq; +- keep-power-in-suspend; +- wakeup-source; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-mnt-reform2.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-mnt-reform2.dts +deleted file mode 100644 +index 2535268f0984..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-mnt-reform2.dts ++++ /dev/null +@@ -1,213 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-/* +- * Copyright 2019-2021 MNT Research GmbH +- * Copyright 2021 Lucas Stach +- */ +- +-/dts-v1/; +- +-#include "imx8mq-nitrogen-som.dtsi" +- +-/ { +- model = "MNT Reform 2"; +- compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq"; +- +- pcie1_refclk: clock-pcie1-refclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- }; +- +- reg_main_5v: regulator-main-5v { +- compatible = "regulator-fixed"; +- regulator-name = "5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_main_3v3: regulator-main-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_main_usb: regulator-main-usb { +- compatible = "regulator-fixed"; +- regulator-name = "USB_PWR"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <®_main_5v>; +- }; +- +- sound { +- compatible = "fsl,imx-audio-wm8960"; +- audio-cpu = <&sai2>; +- audio-codec = <&wm8960>; +- audio-routing = +- "Headphone Jack", "HP_L", +- "Headphone Jack", "HP_R", +- "Ext Spk", "SPK_LP", +- "Ext Spk", "SPK_LN", +- "Ext Spk", "SPK_RP", +- "Ext Spk", "SPK_RN", +- "LINPUT1", "Mic Jack", +- "Mic Jack", "MICB", +- "LINPUT2", "Line In Jack", +- "RINPUT2", "Line In Jack"; +- model = "wm8960-audio"; +- }; +-}; +- +-&fec1 { +- status = "okay"; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- wm8960: codec@1a { +- compatible = "wlf,wm8960"; +- reg = <0x1a>; +- clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; +- clock-names = "mclk"; +- #sound-dai-cells = <0>; +- }; +- +- rtc@68 { +- compatible = "nxp,pcf8523"; +- reg = <0x68>; +- }; +-}; +- +-&pcie1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie1>; +- reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>; +- clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, +- <&clk IMX8MQ_CLK_PCIE2_AUX>, +- <&clk IMX8MQ_CLK_PCIE2_PHY>, +- <&pcie1_refclk>; +- clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; +- status = "okay"; +-}; +- +-®_1p8v { +- vin-supply = <®_main_5v>; +-}; +- +-®_snvs { +- vin-supply = <®_main_5v>; +-}; +- +-®_arm_dram { +- vin-supply = <®_main_5v>; +-}; +- +-®_dram_1p1v { +- vin-supply = <®_main_5v>; +-}; +- +-®_soc_gpu_vpu { +- vin-supply = <®_main_5v>; +-}; +- +-&sai2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai2>; +- assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; +- assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; +- assigned-clock-rates = <25000000>; +- fsl,sai-mclk-direction-output; +- fsl,sai-asynchronous; +- status = "okay"; +-}; +- +-&snvs_rtc { +- status = "disabled"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usb3_phy0 { +- vbus-supply = <®_main_usb>; +- status = "okay"; +-}; +- +-&usb3_phy1 { +- vbus-supply = <®_main_usb>; +- status = "okay"; +-}; +- +-&usb_dwc3_0 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb_dwc3_1 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc2 { +- assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- vqmmc-supply = <®_main_3v3>; +- vmmc-supply = <®_main_3v3>; +- bus-width = <4>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f +- MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f +- >; +- }; +- +- pinctrl_pcie1: pcie1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x16 +- >; +- }; +- +- pinctrl_sai2: sai2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 +- MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 +- MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 +- MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 +- MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6 +- MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 +- MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45 +- MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-nitrogen-som.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-nitrogen-som.dtsi +deleted file mode 100644 +index 36fc428ebe30..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-nitrogen-som.dtsi ++++ /dev/null +@@ -1,275 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2018 Boundary Devices +- * Copyright 2021 Lucas Stach +- */ +- +-#include "imx8mq.dtsi" +- +-/ { +- model = "Boundary Devices i.MX8MQ Nitrogen8M"; +- compatible = "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- reg_1p8v: regulator-fixed-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- reg_snvs: regulator-fixed-snvs { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_SNVS"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&{/opp-table/opp-800000000} { +- opp-microvolt = <1000000>; +-}; +- +-&{/opp-table/opp-1000000000} { +- opp-microvolt = <1000000>; +-}; +- +-&A53_0 { +- cpu-supply = <®_arm_dram>; +-}; +- +-&A53_1 { +- cpu-supply = <®_arm_dram>; +-}; +- +-&A53_2 { +- cpu-supply = <®_arm_dram>; +-}; +- +-&A53_3 { +- cpu-supply = <®_arm_dram>; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@4 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <4>; +- interrupt-parent = <&gpio1>; +- interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- i2c-mux@70 { +- compatible = "nxp,pca9546"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1_pca9546>; +- reg = <0x70>; +- reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c1a: i2c@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_arm_dram: regulator@60 { +- compatible = "fcs,fan53555"; +- reg = <0x60>; +- regulator-name = "VDD_ARM_DRAM_1V"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- }; +- +- i2c1b: i2c@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_dram_1p1v: regulator@60 { +- compatible = "fcs,fan53555"; +- reg = <0x60>; +- regulator-name = "NVCC_DRAM_1P1V"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- }; +- +- i2c1c: i2c@2 { +- reg = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_soc_gpu_vpu: regulator@60 { +- compatible = "fcs,fan53555"; +- reg = <0x60>; +- regulator-name = "VDD_SOC_GPU_VPU"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-always-on; +- }; +- }; +- +- i2c1d: i2c@3 { +- reg = <3>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +-}; +- +-&pgc_gpu { +- power-supply = <®_soc_gpu_vpu>; +-}; +- +-&pgc_vpu { +- power-supply = <®_soc_gpu_vpu>; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usdhc1 { +- assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; +- assigned-clock-rates = <400000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- vqmmc-supply = <®_1p8v>; +- vmmc-supply = <®_snvs>; +- bus-width = <8>; +- non-removable; +- no-mmc-hs400; +- no-sdio; +- no-sd; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 +- MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 +- MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f +- MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f +- >; +- }; +- +- pinctrl_i2c1_pca9546: i2c1-pca9546grp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45 +- MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-nitrogen.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-nitrogen.dts +deleted file mode 100644 +index f70fb32b96b0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-nitrogen.dts ++++ /dev/null +@@ -1,589 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2018 Boundary Devices +- */ +- +-/dts-v1/; +- +-#include +-#include "imx8mq.dtsi" +- +-/ { +- model = "Boundary Devices i.MX8MQ Nitrogen8M"; +- compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x00000000 0x40000000 0 0x80000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; +- +- power { +- label = "Power Button"; +- gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- ddc-i2c-bus = <&ddc_i2c_bus>; +- label = "hdmi"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <<8912_out>; +- }; +- }; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_vref_0v9: regulator-vref-0v9 { +- compatible = "regulator-fixed"; +- regulator-name = "vref-0v9"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- }; +- +- reg_vref_1v8: regulator-vref-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "vref-1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- reg_vref_2v5: regulator-vref-2v5 { +- compatible = "regulator-fixed"; +- regulator-name = "vref-2v5"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- }; +- +- reg_vref_3v3: regulator-vref-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vref-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reg_vref_5v: regulator-vref-5v { +- compatible = "regulator-fixed"; +- regulator-name = "vref-5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +-}; +- +-&dphy { +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@4 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <4>; +- interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>; +- }; +- }; +-}; +- +-/* Release reset of the USB Host HUB */ +-&gpio1 { +- usb-host-reset-hog { +- gpio-hog; +- gpios = <14 GPIO_ACTIVE_HIGH>; +- output-high; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- i2cmux@70 { +- compatible = "nxp,pca9546"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1_pca9546>; +- reg = <0x70>; +- reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c1a: i2c1@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_arm_dram: regulator@60 { +- compatible = "fcs,fan53555"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_arm_dram>; +- reg = <0x60>; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- i2c1b: i2c1@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_dram_1p1v: regulator@60 { +- compatible = "fcs,fan53555"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_dram_1p1v>; +- reg = <0x60>; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- i2c1c: i2c1@2 { +- reg = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg_soc_gpu_vpu: regulator@60 { +- compatible = "fcs,fan53555"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>; +- reg = <0x60>; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- i2c1d: i2c1@3 { +- reg = <3>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtc@68 { +- compatible = "microcrystal,rv4162"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1d_rv4162>; +- reg = <0x68>; +- interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>; +- wakeup-source; +- }; +- }; +- }; +-}; +- +-&i2c4 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +- +- pca9546: i2cmux@70 { +- compatible = "nxp,pca9546"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c4@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <100000>; +- +- hdmi-bridge@48 { +- compatible = "lontium,lt8912b"; +- reg = <0x48> ; +- reset-gpios = <&max7323 0 GPIO_ACTIVE_LOW>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- hdmi_out_in: endpoint { +- data-lanes = <1 2 3 4>; +- remote-endpoint = <&mipi_dsi_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- lt8912_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +- }; +- }; +- }; +- }; +- +- ddc_i2c_bus: i2c4@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <100000>; +- }; +- +- i2c4@3 { +- reg = <3>; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <100000>; +- +- max7323: gpio-expander@68 { +- compatible = "maxim,max7323"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_max7323>; +- gpio-controller; +- reg = <0x68>; +- #gpio-cells = <2>; +- }; +- }; +- }; +-}; +- +-&lcdif { +- status = "okay"; +-}; +- +-&mipi_dsi { +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- ports { +- port@1 { +- reg = <1>; +- +- mipi_dsi_out: endpoint { +- remote-endpoint = <&hdmi_out_in>; +- }; +- }; +- }; +-}; +- +-&uart1 { /* console */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- assigned-clocks = <&clk IMX8MQ_CLK_UART1>; +- assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- assigned-clocks = <&clk IMX8MQ_CLK_UART2>; +- assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; +- status = "okay"; +-}; +- +-&usb_dwc3_0 { +- dr_mode = "otg"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb3_0>; +- status = "okay"; +-}; +- +-&usb3_phy0 { +- vbus-supply = <®_usb_otg_vbus>; +- status = "okay"; +-}; +- +-&usb_dwc3_1 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb3_phy1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb3_1>; +- status = "okay"; +-}; +- +-&usdhc1 { +- assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; +- assigned-clock-rates = <400000000>; +- bus-width = <8>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- non-removable; +- vmmc-supply = <®_vref_1v8>; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_hog>; +- +- pinctrl_hog: hoggrp { +- fsl,pins = < +- /* J17 connector, odd */ +- MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 19 */ +- MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 21 */ +- MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 23 */ +- MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 25 */ +- MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 27 */ +- MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 29 */ +- MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 31 */ +- MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 33 */ +- MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 /* Pin 35 */ +- MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* Pin 39 */ +- MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* Pin 41 */ +- MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Pin 43 */ +- MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* Pin 45 */ +- MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* Pin 47 */ +- MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* Pin 49 */ +- MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* Pin 51 */ +- +- /* J17 connector, even */ +- MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* Pin 44 */ +- MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 /* Pin 48 */ +- MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 50 */ +- MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* Pin 54 */ +- MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* Pin 56 */ +- +- /* J18 connector, odd */ +- MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* Pin 41 */ +- MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* Pin 43 */ +- MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* Pin 45 */ +- MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* Pin 47 */ +- MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* Pin 49 */ +- MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* Pin 53 */ +- +- /* J18 connector, even */ +- MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* Pin 32 */ +- MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* Pin 36 */ +- MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* Pin 38 */ +- MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Pin 40 */ +- MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* Pin 42 */ +- MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* Pin 44 */ +- MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* Pin 46 */ +- +- /* J13 Pin 2, WL_WAKE */ +- MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xd6 +- /* J13 Pin 4, WL_IRQ, not needed for Silex */ +- MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xd6 +- /* J13 pin 9, unused */ +- MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 +- /* J13 Pin 41, BT_CLK_REQ */ +- MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xd6 +- /* J13 Pin 42, BT_HOST_WAKE */ +- MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xd6 +- +- /* Clock for both CSI1 and CSI2 */ +- MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x07 +- /* test points */ +- MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 /* TP87 */ +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 +- MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 +- MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59 +- >; +- }; +- +- pinctrl_gpio_keys: gpio-keysgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 +- >; +- }; +- +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f +- MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f +- >; +- }; +- +- pinctrl_i2c1_pca9546: i2c1-pca9546grp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49 +- >; +- }; +- +- pinctrl_i2c1d_rv4162: i2c1d-rv4162grp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f +- MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f +- >; +- }; +- +- pinctrl_max7323: max7323grp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 +- >; +- }; +- +- pinctrl_reg_arm_dram: reg-arm-dramgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16 +- >; +- }; +- +- pinctrl_reg_dram_1p1v: reg-dram-1p1vgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16 +- >; +- }; +- +- pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpugrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16 +- >; +- }; +- +- pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x16 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45 +- MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45 +- MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45 +- >; +- }; +- +- pinctrl_usb3_0: usb3-0grp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x16 +- >; +- }; +- +- pinctrl_usb3_1: usb3-1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 +- MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-phanbell.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-phanbell.dts +deleted file mode 100644 +index a3b9d615a3b4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-phanbell.dts ++++ /dev/null +@@ -1,481 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2017-2019 NXP +- */ +- +-/dts-v1/; +- +-#include "imx8mq.dtsi" +-#include +- +-/ { +- model = "Google i.MX8MQ Phanbell"; +- compatible = "google,imx8mq-phanbell", "fsl,imx8mq"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x00000000 0x40000000 0 0x40000000>; +- }; +- +- pmic_osc: clock-pmic { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "pmic_osc"; +- }; +- +- reg_usdhc2_vmmc: regulator-usdhc2-vmmc { +- compatible = "regulator-fixed"; +- regulator-name = "VSD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- fan: gpio-fan { +- compatible = "gpio-fan"; +- gpio-fan,speed-map = <0 0 8600 1>; +- gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; +- #cooling-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_fan>; +- status = "okay"; +- }; +-}; +- +-&A53_0 { +- cpu-supply = <&buck2>; +-}; +- +-&A53_1 { +- cpu-supply = <&buck2>; +-}; +- +-&A53_2 { +- cpu-supply = <&buck2>; +-}; +- +-&A53_3 { +- cpu-supply = <&buck2>; +-}; +- +-&cpu_thermal { +- trips { +- cpu_alert0: trip0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_alert1: trip1 { +- temperature = <80000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_crit0: trip3 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- +- fan_toggle0: trip4 { +- temperature = <65000>; +- hysteresis = <10000>; +- type = "active"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- cooling-device = +- <&A53_0 0 1>; /* Exclude highest OPP */ +- }; +- +- map1 { +- trip = <&cpu_alert1>; +- cooling-device = +- <&A53_0 0 2>; /* Exclude two highest OPPs */ +- }; +- +- map4 { +- trip = <&fan_toggle0>; +- cooling-device = <&fan 0 1>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic: pmic@4b { +- compatible = "rohm,bd71837"; +- reg = <0x4b>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- #clock-cells = <0>; +- clocks = <&pmic_osc>; +- clock-output-names = "pmic_clk"; +- interrupt-parent = <&gpio1>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- +- regulators { +- buck1: BUCK1 { +- regulator-name = "buck1"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-ramp-delay = <1250>; +- rohm,dvs-run-voltage = <900000>; +- rohm,dvs-idle-voltage = <900000>; +- rohm,dvs-suspend-voltage = <800000>; +- }; +- +- buck2: BUCK2 { +- regulator-name = "buck2"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1000000>; +- regulator-boot-on; +- regulator-always-on; +- rohm,dvs-run-voltage = <1000000>; +- rohm,dvs-idle-voltage = <900000>; +- }; +- +- buck3: BUCK3 { +- regulator-name = "buck3"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- rohm,dvs-run-voltage = <900000>; +- }; +- +- buck4: BUCK4 { +- regulator-name = "buck4"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-always-on; +- rohm,dvs-run-voltage = <900000>; +- }; +- +- buck5: BUCK5 { +- regulator-name = "buck5"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck6: BUCK6 { +- regulator-name = "buck6"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck7: BUCK7 { +- regulator-name = "buck7"; +- regulator-min-microvolt = <1605000>; +- regulator-max-microvolt = <1995000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- buck8: BUCK8 { +- regulator-name = "buck8"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo1: LDO1 { +- regulator-name = "ldo1"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo2: LDO2 { +- regulator-name = "ldo2"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo3: LDO3 { +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo4: LDO4 { +- regulator-name = "ldo4"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo5: LDO5 { +- regulator-name = "ldo5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo6: LDO6 { +- regulator-name = "ldo6"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo7: LDO7 { +- regulator-name = "ldo7"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- reset-deassert-us = <50000>; +- }; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +- bus-width = <4>; +- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_usdhc2_vmmc>; +- status = "okay"; +-}; +- +-&usb3_phy0 { +- status = "okay"; +-}; +- +-&usb_dwc3_0 { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&usb3_phy1 { +- status = "okay"; +-}; +- +-&usb_dwc3_1 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 +- MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 +- >; +- }; +- +- pinctrl_gpio_fan: gpiofangrp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f +- MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f +- >; +- }; +- +- pinctrl_pmic: pmicirqgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 +- MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_gpio: usdhc2gpiogrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 +- MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-pico-pi.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-pico-pi.dts +deleted file mode 100644 +index 89cbec5c41b2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-pico-pi.dts ++++ /dev/null +@@ -1,418 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2018 Wandboard, Org. +- * Copyright 2017 NXP +- * +- * Author: Richard Hu +- */ +- +-/dts-v1/; +- +-#include "imx8mq.dtsi" +-#include +- +-/ { +- model = "TechNexion PICO-PI-8M"; +- compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- pmic_osc: clock-pmic { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "pmic_osc"; +- }; +- +- reg_usb_otg_vbus: regulator-usb-otg-vbus { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_otg_vbus>; +- compatible = "regulator-fixed"; +- regulator-name = "usb_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio3 14 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic: pmic@4b { +- reg = <0x4b>; +- compatible = "rohm,bd71837"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pmic>; +- clocks = <&pmic_osc>; +- clock-names = "osc"; +- clock-output-names = "pmic_clk"; +- interrupt-parent = <&gpio1>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- interrupt-names = "irq"; +- +- regulators { +- buck1: BUCK1 { +- regulator-name = "buck1"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-ramp-delay = <1250>; +- rohm,dvs-run-voltage = <900000>; +- rohm,dvs-idle-voltage = <850000>; +- rohm,dvs-suspend-voltage = <800000>; +- }; +- +- buck2: BUCK2 { +- regulator-name = "buck2"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- regulator-ramp-delay = <1250>; +- rohm,dvs-run-voltage = <1000000>; +- rohm,dvs-idle-voltage = <900000>; +- }; +- +- buck3: BUCK3 { +- regulator-name = "buck3"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- rohm,dvs-run-voltage = <1000000>; +- }; +- +- buck4: BUCK4 { +- regulator-name = "buck4"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1300000>; +- regulator-boot-on; +- rohm,dvs-run-voltage = <1000000>; +- }; +- +- buck5: BUCK5 { +- regulator-name = "buck5"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-boot-on; +- }; +- +- buck6: BUCK6 { +- regulator-name = "buck6"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- +- buck7: BUCK7 { +- regulator-name = "buck7"; +- regulator-min-microvolt = <1605000>; +- regulator-max-microvolt = <1995000>; +- regulator-boot-on; +- }; +- +- buck8: BUCK8 { +- regulator-name = "buck8"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- }; +- +- ldo1: LDO1 { +- regulator-name = "ldo1"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo2: LDO2 { +- regulator-name = "ldo2"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- ldo3: LDO3 { +- regulator-name = "ldo3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- +- ldo4: LDO4 { +- regulator-name = "ldo4"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- }; +- +- ldo5: LDO5 { +- regulator-name = "ldo5"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- +- ldo6: LDO6 { +- regulator-name = "ldo6"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- }; +- +- ldo7: LDO7 { +- regulator-name = "ldo7"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&uart1 { /* console */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&usdhc1 { +- assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; +- assigned-clock-rates = <400000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&usdhc2 { +- assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +- bus-width = <4>; +- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&usb3_phy0 { +- status = "okay"; +-}; +- +-&usb3_phy1 { +- status = "okay"; +-}; +- +-&usb_dwc3_1 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_enet_3v3: enet3v3grp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19 +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 +- MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f +- MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f +- MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f +- >; +- }; +- +- pinctrl_otg_vbus: otgvbusgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* USB OTG VBUS Enable */ +- >; +- }; +- +- pinctrl_pmic: pmicirqgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 +- MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 +- MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 +- MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 +- MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 +- >; +- }; +- +- pinctrl_usdhc2_gpio: usdhc2gpiogrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-pinfunc.h b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-pinfunc.h +deleted file mode 100644 +index 68e8fa172974..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-pinfunc.h ++++ /dev/null +@@ -1,623 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2016 Freescale Semiconductor, Inc. +- * Copyright 2017 NXP +- */ +- +-#ifndef __DTS_IMX8MQ_PINFUNC_H +-#define __DTS_IMX8MQ_PINFUNC_H +- +-/* +- * The pin function ID is a tuple of +- * +- */ +- +-#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 +-#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 +-#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 +-#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2 +-#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 +-#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0 +-#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1 +-#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1 +-#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1 +-#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1 +-#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1 +-#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1 +-#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1 +-#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4 +-#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3 +-#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1 +-#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1 +-#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1 +-#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1 +-#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1 +-#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1 +-#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1 +-#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1 +-#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1 +-#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0 +-#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1 +-#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2 +-#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 +-#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 +-#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2 +-#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 +-#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 +-#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 +-#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 +-#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 +-#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2 +-#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3 +-#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 +-#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 +-#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 +-#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 +-#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 +-#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 +-#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 +-#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 +-#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 +-#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 +-#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 +-#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0 +-#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 +-#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 +-#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0 +-#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 +-#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 +-#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 +-#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 +-#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 +-#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 +-#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 +-#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 +-#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1 +-#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 +-#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 +-#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 +-#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1 +-#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 +-#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0 +-#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0 +-#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0 +- +-#endif /* __DTS_IMX8MQ_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-sr-som.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-sr-som.dtsi +deleted file mode 100644 +index 0187890a90c5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-sr-som.dtsi ++++ /dev/null +@@ -1,317 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2018 Jon Nettleton +- */ +- +-#include "imx8mq.dtsi" +- +-/ { +- reg_vdd_3v3: regulator-vdd-3v3 { +- compatible = "regulator-fixed"; +- regulator-always-on; +- regulator-name = "vdd_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@4 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <4>; +- reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- reset-assert-us = <2000>; +- }; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clock-frequency = <400000>; +- status = "okay"; +- +- pmic: pmic@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x08>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3ab { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- regulator-always-on; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c01"; +- reg = <0x50>; +- status = "okay"; +- }; +-}; +- +-&pgc_gpu{ +- power-supply = <&sw1a_reg>; +-}; +- +-&pgc_vpu { +- power-supply = <&sw1c_reg>; +-}; +- +-&qspi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_qspi>; +- status = "okay"; +- +- /* SPI flash; not assembled by default */ +- spi_flash: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- compatible = "micron,n25q256a", "jedec,spi-nor"; +- spi-max-frequency = <29000000>; +- status = "disabled"; +- }; +-}; +- +-&uart1 { /* console */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- assigned-clocks = <&clk IMX8MQ_CLK_UART1>; +- assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; +- assigned-clock-rates = <25000000>; +- status = "okay"; +-}; +- +-&uart4 { /* ublox BT */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- assigned-clocks = <&clk IMX8MQ_CLK_UART4>; +- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; +- assigned-clock-rates = <80000000>; +- status = "okay"; +-}; +- +-&usdhc1 { +- assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; +- assigned-clock-rates = <400000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 +- MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f +- MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f +- MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f +- MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f +- MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f +- >; +- }; +- +- pinctrl_pcie0: pcie0grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x74 +- MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x16 +- MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16 +- >; +- }; +- +- pinctrl_qspi: qspigrp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 +- MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 +- MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 +- MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 +- MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 +- MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 +- +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 +- MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 +- MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 +- >; +- }; +- +- pinctrl_uart4: uart4grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49 +- MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49 +- MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-thor96.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-thor96.dts +deleted file mode 100644 +index 5d5aa6537225..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-thor96.dts ++++ /dev/null +@@ -1,581 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2019 Einfochips +- * Copyright 2019 Linaro Ltd. +- */ +- +-/dts-v1/; +- +-#include "imx8mq.dtsi" +- +-/ { +- model = "Einfochips i.MX8MQ Thor96"; +- compatible = "einfochips,imx8mq-thor96", "fsl,imx8mq"; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x00000000 0x40000000 0 0x80000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds>; +- +- user-led1 { +- label = "green:user1"; +- gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- user-led2 { +- label = "green:user2"; +- gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "none"; +- }; +- +- user-led3 { +- label = "green:user3"; +- gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc1"; +- default-state = "off"; +- }; +- +- user-led4 { +- label = "green:user4"; +- gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; +- panic-indicator; +- linux,default-trigger = "none"; +- }; +- +- wlan-active-led { +- label = "yellow:wlan"; +- gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "phy0tx"; +- default-state = "off"; +- }; +- +- bt-active-led { +- label = "blue:bt"; +- gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "hci0-power"; +- default-state = "off"; +- }; +- }; +- +- reg_usdhc1_vmmc: reg-usdhc1-vmmc { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usdhc1_vqmmc: reg-usdhc1-vqmmc { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_1V8_EXT"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- reg_usdhc2_vmmc: reg-usdhc2-vmmc { +- compatible = "regulator-fixed"; +- regulator-name = "VSD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usdhc2>; +- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_usdhc2_vqmmc: reg-usdhc2-vqmmc { +- compatible = "regulator-fixed"; +- regulator-name = "NVCC_SD2"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wifi_reg_on>; +- gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-/* LS-SPI0 */ +-&ecspi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi2>; +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy: ethernet-phy@3 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <3>; +- reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-/* LS-I2C0 */ +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- pmic@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x8>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <300000>; +- regulator-max-microvolt = <1875000>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3ab { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1975000>; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- regulator-always-on; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +- }; +-}; +- +-/* LS-I2C1 */ +-&i2c2 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- }; +-}; +- +-/* HS-I2C2 */ +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +-}; +- +-/* HS-I2C3 */ +-&i2c4 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +-}; +- +-&pgc_gpu { +- power-supply = <&sw1a_reg>; +-}; +- +-&pgc_vpu { +- power-supply = <&sw1c_reg>; +-}; +- +-&qspi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_qspi0>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <100000000>; +- reg = <0>; +- }; +-}; +- +-/* Debug UART */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- assigned-clocks = <&clk IMX8MQ_CLK_UART1>; +- assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; +- status = "okay"; +-}; +- +-/* LS-UART0 */ +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- assigned-clocks = <&clk IMX8MQ_CLK_UART2>; +- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- device-wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_bt_gpios>; +- }; +-}; +- +-/* LS-UART1 */ +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- assigned-clocks = <&clk IMX8MQ_CLK_UART3>; +- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; +- status = "okay"; +-}; +- +-&usb3_phy1 { +- status = "okay"; +-}; +- +-&usb_dwc3_1 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-/* SDIO */ +-&usdhc1 { +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- vmmc-supply = <®_usdhc1_vmmc>; +- vqmmc-supply = <®_usdhc1_vqmmc>; +- mmc-pwrseq = <&sdio_pwrseq>; +- bus-width = <4>; +- non-removable; +- no-sd; +- no-emmc; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* uSD */ +-&usdhc2 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +- vmmc-supply = <®_usdhc2_vmmc>; +- vqmmc-supply = <®_usdhc2_vqmmc>; +- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- no-sdio; +- no-emmc; +- disable-wp; +- status = "okay"; +-}; +- +-&wdog1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wdog>; +- fsl,ext-reset-output; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_bt_gpios: btgpiosgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 +- MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 +- MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 +- >; +- }; +- +- pinctrl_ecspi2: ecspi2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x16 +- MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x16 +- MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x16 +- MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x16 +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x4 +- MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x24 +- MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1c +- MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1c +- MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1c +- MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1c +- MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 +- MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 +- MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1c +- MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 +- MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1c +- MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f +- MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f +- MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f +- MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f +- MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f +- >; +- }; +- +- pinctrl_leds: ledsgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x19 +- MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 +- MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 +- MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 +- MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 +- MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 +- >; +- }; +- +- pinctrl_qspi0: qspi0grp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 +- MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 +- MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 +- MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 +- MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 +- MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 +- +- >; +- }; +- +- pinctrl_reg_usdhc2: regusdhc2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 +- MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 +- MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 +- MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 +- MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 +- >; +- }; +- +- pinctrl_uart3: uart3grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 +- MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 +- MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd +- MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf +- MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85 +- >; +- }; +- +- pinctrl_usdhc2_gpio: usdhc2gpiogrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8c +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcc +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcc +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcc +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcc +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcc +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9c +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdc +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdc +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdc +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdc +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdc +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xcc +- >; +- }; +- +- pinctrl_wdog: wdoggrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 +- >; +- }; +- +- pinctrl_wifi_reg_on: wifiregongrp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-zii-ultra-rmb3.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-zii-ultra-rmb3.dts +deleted file mode 100644 +index be1e7d6f0ecb..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-zii-ultra-rmb3.dts ++++ /dev/null +@@ -1,188 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2019 Zodiac Inflight Innovations +- */ +- +-/dts-v1/; +- +-#include "imx8mq-zii-ultra.dtsi" +- +-/ { +- model = "ZII Ultra RMB3 Board"; +- compatible = "zii,imx8mq-ultra-rmb3", "zii,imx8mq-ultra", "fsl,imx8mq"; +- +- sound1 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "front"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sound1_codec>; +- simple-audio-card,frame-master = <&sound1_codec>; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack Front"; +- simple-audio-card,routing = +- "Headphone Jack Front", "HPA1 HPLEFT", +- "Headphone Jack Front", "HPA1 HPRIGHT", +- "HPA1 LEFTIN", "HPL", +- "HPA1 RIGHTIN", "HPR"; +- simple-audio-card,aux-devs = <&hpa1>; +- +- sound1_cpu: simple-audio-card,cpu { +- sound-dai = <&sai2>; +- }; +- +- sound1_codec: simple-audio-card,codec { +- sound-dai = <&codec1>; +- clocks = <&cs2000>; +- }; +- }; +- +- sound2 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "periph"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sound2_codec>; +- simple-audio-card,frame-master = <&sound2_codec>; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack Back"; +- simple-audio-card,routing = +- "Headphone Jack Back", "HPA1 HPLEFT", +- "Headphone Jack Back", "HPA1 HPRIGHT", +- "HPA1 LEFTIN", "HPL", +- "HPA1 RIGHTIN", "HPR"; +- simple-audio-card,aux-devs = <&hpa2>; +- +- sound2_cpu: simple-audio-card,cpu { +- sound-dai = <&sai3>; +- }; +- +- sound2_codec: simple-audio-card,codec { +- sound-dai = <&codec2>; +- clocks = <&cs2000>; +- }; +- }; +-}; +- +-&ecspi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ecspi1>; +- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- nor_flash: flash@0 { +- compatible = "st,n25q128a13", "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +- +-&hpa2 { +- sound-name-prefix = "HPA1"; +-}; +- +-&i2c1 { +- codec2: codec@18 { +- compatible = "ti,tlv320dac3100"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_codec2>; +- reg = <0x18>; +- #sound-dai-cells = <0>; +- HPVDD-supply = <®_gen_3p3>; +- SPRVDD-supply = <®_gen_3p3>; +- SPLVDD-supply = <®_gen_3p3>; +- AVDD-supply = <®_gen_3p3>; +- IOVDD-supply = <®_gen_3p3>; +- DVDD-supply = <&vgen4_reg>; +- reset-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&i2c2 { +- temp-sense@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +-}; +- +-&i2c4 { +- touchscreen@20 { +- compatible = "syna,rmi4-i2c"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ts>; +- reg = <0x20>; +- interrupt-parent = <&gpio1>; +- interrupts = <12 IRQ_TYPE_LEVEL_LOW>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- rmi4-f01@1 { +- reg = <0x1>; +- syna,nosleep-mode = <2>; +- }; +- +- rmi4-f11@11 { +- reg = <0x11>; +- touchscreen-inverted-x; +- touchscreen-swapped-x-y; +- syna,sensor-type = <1>; +- syna,delta-x-threshold = <5>; +- syna,delta-y-threshold = <10>; +- }; +- +- rmi4-f12@12 { +- reg = <0x12>; +- touchscreen-inverted-x; +- touchscreen-swapped-x-y; +- syna,sensor-type = <1>; +- }; +- }; +- +- touchscreen@2a { +- compatible = "eeti,exc3000"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ts>; +- reg = <0x2a>; +- interrupt-parent = <&gpio1>; +- interrupts = <12 IRQ_TYPE_LEVEL_LOW>; +- touchscreen-inverted-x; +- touchscreen-swapped-x-y; +- status = "disabled"; +- }; +-}; +- +-&sai3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai3>; +- status = "okay"; +-}; +- +-&usbhub { +- swap-dx-lanes = <0>; +-}; +- +-&iomuxc { +- pinctrl_codec2: dac2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x41 +- >; +- }; +- +- pinctrl_ecspi1: ecspi1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 +- MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 +- MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 +- MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 +- >; +- }; +- +- pinctrl_sai3: sai3grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 +- MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 +- MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-zii-ultra-zest.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-zii-ultra-zest.dts +deleted file mode 100644 +index f6130167a1c7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-zii-ultra-zest.dts ++++ /dev/null +@@ -1,54 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2019 Zodiac Inflight Innovations +- */ +- +-/dts-v1/; +- +-#include "imx8mq-zii-ultra.dtsi" +- +-/ { +- model = "ZII Ultra Zest Board"; +- compatible = "zii,imx8mq-ultra-zest", "zii,imx8mq-ultra", "fsl,imx8mq"; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "front"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sound_codec>; +- simple-audio-card,frame-master = <&sound_codec>; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack Front", +- "Headphone", "Headphone Jack Back"; +- simple-audio-card,routing = +- "Headphone Jack Front", "HPA1 HPLEFT", +- "Headphone Jack Front", "HPA1 HPRIGHT", +- "Headphone Jack Back", "HPA2 HPLEFT", +- "Headphone Jack Back", "HPA2 HPRIGHT", +- "HPA1 LEFTIN", "HPL", +- "HPA1 RIGHTIN", "HPR", +- "HPA2 LEFTIN", "HPL", +- "HPA2 RIGHTIN", "HPR"; +- simple-audio-card,aux-devs = <&hpa1>, <&hpa2>; +- +- sound_cpu: simple-audio-card,cpu { +- sound-dai = <&sai2>; +- }; +- +- sound_codec: simple-audio-card,codec { +- sound-dai = <&codec1>; +- clocks = <&cs2000>; +- }; +- }; +-}; +- +-&i2c4 { +- touchscreen@4a { +- compatible = "atmel,maxtouch"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ts>; +- reg = <0x4a>; +- interrupt-parent = <&gpio1>; +- interrupts = <12 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-zii-ultra.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-zii-ultra.dtsi +deleted file mode 100644 +index a08a568c31d9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq-zii-ultra.dtsi ++++ /dev/null +@@ -1,862 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2019 Zodiac Inflight Innovations +- */ +- +-#include "imx8mq.dtsi" +- +-/ { +- aliases { +- mdio-gpio0 = &mdio0; +- rtc0 = &ds1341; +- }; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- mdio0: bitbang-mdio { +- compatible = "virtual,mdio-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>; +- gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>, /* MDC */ +- <&gpio1 14 GPIO_ACTIVE_HIGH>; /* MDIO */ +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- pcie0_refclk: clock-pcie0-refclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- }; +- +- pcie1_refclk: clock-pcie1-refclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- }; +- +- reg_12p0_main: regulator-12p0-main { +- compatible = "regulator-fixed"; +- regulator-name = "12V_MAIN"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- }; +- +- reg_5p0_main: regulator-5p0-main { +- compatible = "regulator-fixed"; +- vin-supply = <®_12p0_main>; +- regulator-name = "5V_MAIN"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- reg_3p3_main: regulator-3p3-main { +- compatible = "regulator-fixed"; +- vin-supply = <®_12p0_main>; +- regulator-name = "3V3_MAIN"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_gen_3p3: regulator-gen-3p3 { +- compatible = "regulator-fixed"; +- vin-supply = <®_3p3_main>; +- regulator-name = "GEN_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- reg_usdhc2_vmmc: regulator-vsd-3v3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_usdhc2>; +- compatible = "regulator-fixed"; +- vin-supply = <®_gen_3p3>; +- regulator-name = "3V3_SD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_arm: regulator-arm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_reg_arm>; +- compatible = "regulator-gpio"; +- vin-supply = <®_12p0_main>; +- regulator-name = "0V9_ARM"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1000000>; +- gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; +- states = <1000000 0x1 +- 900000 0x0>; +- regulator-always-on; +- }; +- +- cs2000_ref: cs2000-ref { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +- +- cs2000_in_dummy: cs2000-in-dummy { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +-}; +- +-&A53_0 { +- cpu-supply = <®_arm>; +-}; +- +-&A53_1 { +- cpu-supply = <®_arm>; +-}; +- +-&A53_2 { +- cpu-supply = <®_arm>; +-}; +- +-&A53_3 { +- cpu-supply = <®_arm>; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- +- phy-handle = <&phy0>; +- phy-mode = "rmii"; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <12500000>; +- suppress-preamble; +- status = "okay"; +- +- switch: switch@0 { +- compatible = "marvell,mv88e6085"; +- pinctrl-0 = <&pinctrl_switch_irq>; +- pinctrl-names = "default"; +- reg = <0>; +- dsa,member = <0 0>; +- eeprom-length = <512>; +- interrupt-parent = <&gpio1>; +- interrupts = <15 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "gigabit_proc"; +- phy-handle = <&switchphy0>; +- }; +- +- port@1 { +- reg = <1>; +- label = "netaux"; +- phy-handle = <&switchphy1>; +- }; +- +- port@2 { +- reg = <2>; +- label = "cpu"; +- ethernet = <&fec1>; +- +- fixed-link { +- speed = <100>; +- full-duplex; +- }; +- }; +- +- port@3 { +- reg = <3>; +- label = "netright"; +- phy-handle = <&switchphy3>; +- }; +- +- port@4 { +- reg = <4>; +- label = "netleft"; +- phy-handle = <&switchphy4>; +- }; +- }; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switchphy0: switchphy@0 { +- reg = <0>; +- interrupt-parent = <&switch>; +- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switchphy1: switchphy@1 { +- reg = <1>; +- interrupt-parent = <&switch>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switchphy2: switchphy@2 { +- reg = <2>; +- interrupt-parent = <&switch>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switchphy3: switchphy@3 { +- reg = <3>; +- interrupt-parent = <&switch>; +- interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- switchphy4: switchphy@4 { +- reg = <4>; +- interrupt-parent = <&switch>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +- }; +- }; +- }; +- }; +-}; +- +-&gpio3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio3_hog>; +- +- usb-emulation-hog { +- gpio-hog; +- gpios = <10 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "usb-emulation"; +- }; +- +- usb-mode1-hog { +- gpio-hog; +- gpios = <11 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "usb-mode1"; +- }; +- +- usb-pwr-hog { +- gpio-hog; +- gpios = <12 GPIO_ACTIVE_LOW>; +- output-high; +- line-name = "usb-pwr-ctrl-en-n"; +- }; +- +- usb-mode2-hog { +- gpio-hog; +- gpios = <13 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "usb-mode2"; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +- +- accelerometer@1c { +- compatible = "fsl,mma8451"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_accel>; +- reg = <0x1c>; +- interrupt-parent = <&gpio3>; +- interrupts = <20 IRQ_TYPE_LEVEL_LOW>; +- interrupt-names = "INT2"; +- vdd-supply = <®_gen_3p3>; +- vddio-supply = <®_gen_3p3>; +- }; +- +- ucs1002: charger@32 { +- compatible = "microchip,ucs1002"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ucs1002>; +- reg = <0x32>; +- interrupt-parent = <&gpio3>; +- interrupts = <17 IRQ_TYPE_EDGE_BOTH>, +- <18 IRQ_TYPE_EDGE_FALLING>; +- interrupt-names = "a_det", "alert"; +- }; +- +- hpa2: amp@60 { +- compatible = "ti,tpa6130a2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tpa2>; +- reg = <0x60>; +- power-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; +- Vdd-supply = <®_5p0_main>; +- sound-name-prefix = "HPA2"; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +- +- pmic@8 { +- compatible = "fsl,pfuze100"; +- reg = <0x8>; +- +- regulators { +- sw1a_reg: sw1ab { +- regulator-min-microvolt = <825000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- sw1c_reg: sw1c { +- regulator-min-microvolt = <825000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- sw2_reg: sw2 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- sw3a_reg: sw3ab { +- regulator-min-microvolt = <825000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- +- sw4_reg: sw4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- swbst_reg: swbst { +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5150000>; +- }; +- +- snvs_reg: vsnvs { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- +- vref_reg: vrefddr { +- regulator-always-on; +- }; +- +- vgen1_reg: vgen1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1550000>; +- }; +- +- vgen2_reg: vgen2 { +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <975000>; +- regulator-always-on; +- }; +- +- vgen3_reg: vgen3 { +- regulator-min-microvolt = <1675000>; +- regulator-max-microvolt = <1975000>; +- regulator-always-on; +- }; +- +- vgen4_reg: vgen4 { +- regulator-min-microvolt = <1625000>; +- regulator-max-microvolt = <1875000>; +- regulator-always-on; +- }; +- +- vgen5_reg: vgen5 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3625000>; +- regulator-always-on; +- }; +- +- vgen6_reg: vgen6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +- }; +- +- codec1: codec@18 { +- compatible = "ti,tlv320dac3100"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_codec1>; +- reg = <0x18>; +- #sound-dai-cells = <0>; +- HPVDD-supply = <®_gen_3p3>; +- SPRVDD-supply = <®_gen_3p3>; +- SPLVDD-supply = <®_gen_3p3>; +- AVDD-supply = <®_gen_3p3>; +- IOVDD-supply = <®_gen_3p3>; +- DVDD-supply = <&vgen4_reg>; +- reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; +- }; +- +- eeprom@54 { +- compatible = "atmel,24c128"; +- reg = <0x54>; +- }; +- +- hpa1: amp@60 { +- compatible = "ti,tpa6130a2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tpa1>; +- reg = <0x60>; +- power-gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; +- Vdd-supply = <®_5p0_main>; +- sound-name-prefix = "HPA1"; +- }; +- +- ds1341: rtc@68 { +- compatible = "dallas,ds1341"; +- reg = <0x68>; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- status = "okay"; +- +- usbhub: usbhub@2c { +- compatible ="microchip,usb2513b"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usbhub>; +- reg = <0x2c>; +- reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; +- }; +- +- watchdog@38 { +- compatible = "zii,rave-wdt"; +- reg = <0x38>; +- }; +- +- cs2000: clkgen@4e { +- compatible = "cirrus,cs2000-cp"; +- reg = <0x4e>; +- #clock-cells = <0>; +- clock-names = "clk_in", "ref_clk"; +- clocks = <&cs2000_in_dummy>, <&cs2000_ref>; +- assigned-clocks = <&cs2000>; +- assigned-clock-rates = <24000000>; +- }; +-}; +- +-&i2c4 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- status = "okay"; +-}; +- +-&sai2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai2>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +- +- rave-sp { +- compatible = "zii,rave-sp-rdu2"; +- current-speed = <1000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- watchdog { +- compatible = "zii,rave-sp-watchdog"; +- }; +- +- backlight { +- compatible = "zii,rave-sp-backlight"; +- }; +- +- pwrbutton { +- compatible = "zii,rave-sp-pwrbutton"; +- }; +- +- eeprom@a3 { +- compatible = "zii,rave-sp-eeprom"; +- reg = <0xa3 0x4000>; +- zii,eeprom-name = "dds-eeprom"; +- }; +- +- eeprom@a4 { +- compatible = "zii,rave-sp-eeprom"; +- reg = <0xa4 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- zii,eeprom-name = "main-eeprom"; +- }; +- }; +-}; +- +-&usb3_phy0 { +- vbus-supply = <&ucs1002>; +- status = "okay"; +-}; +- +-&usb_dwc3_0 { +- dr_mode = "host"; +- maximum-speed = "high-speed"; +- status = "okay"; +-}; +- +-&usb3_phy1 { +- vbus-supply = <®_5p0_main>; +- status = "okay"; +-}; +- +-&usb_dwc3_1 { +- dr_mode = "host"; +- maximum-speed = "high-speed"; +- status = "okay"; +-}; +- +-&pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie0>; +- reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; +- clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, +- <&clk IMX8MQ_CLK_PCIE1_AUX>, +- <&clk IMX8MQ_CLK_PCIE1_PHY>, +- <&pcie0_refclk>; +- clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; +- status = "okay"; +-}; +- +-&pcie1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pcie1>; +- reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; +- clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, +- <&clk IMX8MQ_CLK_PCIE2_AUX>, +- <&clk IMX8MQ_CLK_PCIE2_PHY>, +- <&pcie1_refclk>; +- clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; +- status = "okay"; +-}; +- +-&pgc_gpu { +- power-supply = <&sw1a_reg>; +-}; +- +-&pgc_vpu { +- power-supply = <&sw1c_reg>; +-}; +- +-&usdhc1 { +- assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; +- assigned-clock-rates = <400000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- vqmmc-supply = <&sw4_reg>; +- bus-width = <8>; +- non-removable; +- no-sd; +- no-sdio; +- status = "okay"; +-}; +- +-&usdhc2 { +- assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>; +- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_usdhc2_vmmc>; +- status = "okay"; +-}; +- +-&snvs_rtc { +- status = "disabled"; +-}; +- +-&iomuxc { +- pinctrl_accel: accelgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 +- >; +- }; +- +- pinctrl_codec1: dac1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x41 +- >; +- }; +- +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +- MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 +- MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f +- MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f +- MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 +- MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 +- MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x1f +- MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x91 +- MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 +- MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f +- >; +- }; +- +- pinctrl_fec1_phy_reset: fec1phyresetgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x11 +- >; +- }; +- +- pinctrl_gpio3_hog: gpio3hoggrp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x6 +- MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x6 +- MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x6 +- MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x6 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000022 +- MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000a2 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000022 +- MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000a2 +- >; +- }; +- +- pinctrl_i2c3: i2c3grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000022 +- MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000a2 +- >; +- }; +- +- pinctrl_i2c4: i2c4grp { +- fsl,pins = < +- MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000022 +- MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x400000a2 +- >; +- }; +- +- pinctrl_mdio_bitbang: bitbangmdiogrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x44 +- MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x64 +- >; +- }; +- +- pinctrl_pcie0: pcie0grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x66 +- MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x6 +- >; +- }; +- +- pinctrl_pcie1: pcie1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x66 +- MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x6 +- >; +- }; +- +- pinctrl_reg_arm: regarmgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 +- >; +- }; +- +- pinctrl_reg_usdhc2: regusdhc2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 +- >; +- }; +- +- pinctrl_sai2: sai2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 +- MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 +- MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 +- >; +- }; +- +- pinctrl_switch_irq: switchgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 +- >; +- }; +- +- pinctrl_tpa1: tpa6130-1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x41 +- >; +- }; +- +- pinctrl_tpa2: tpa6130-2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41 +- >; +- }; +- +- pinctrl_ts: tsgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x96 +- MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x96 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 +- MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 +- MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 +- >; +- }; +- +- pinctrl_ucs1002: ucs1002grp { +- fsl,pins = < +- MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x41 +- MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x41 +- >; +- }; +- +- pinctrl_usbhub: usbhubgrp { +- fsl,pins = < +- MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x41 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1-100grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1-200grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f +- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf +- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf +- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf +- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf +- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf +- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf +- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf +- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf +- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf +- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f +- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200grp { +- fsl,pins = < +- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 +- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 +- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 +- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 +- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 +- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 +- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8mq.dtsi +deleted file mode 100644 +index fd38092bb247..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8mq.dtsi ++++ /dev/null +@@ -1,1566 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright 2017 NXP +- * Copyright (C) 2017-2018 Pengutronix, Lucas Stach +- */ +- +-#include +-#include +-#include +-#include +-#include "dt-bindings/input/input.h" +-#include +-#include +-#include +-#include "imx8mq-pinfunc.h" +- +-/ { +- interrupt-parent = <&gpc>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- ethernet0 = &fec1; +- gpio0 = &gpio1; +- gpio1 = &gpio2; +- gpio2 = &gpio3; +- gpio3 = &gpio4; +- gpio4 = &gpio5; +- i2c0 = &i2c1; +- i2c1 = &i2c2; +- i2c2 = &i2c3; +- i2c3 = &i2c4; +- mmc0 = &usdhc1; +- mmc1 = &usdhc2; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- spi0 = &ecspi1; +- spi1 = &ecspi2; +- spi2 = &ecspi3; +- }; +- +- ckil: clock-ckil { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "ckil"; +- }; +- +- osc_25m: clock-osc-25m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- clock-output-names = "osc_25m"; +- }; +- +- osc_27m: clock-osc-27m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- clock-output-names = "osc_27m"; +- }; +- +- clk_ext1: clock-ext1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <133000000>; +- clock-output-names = "clk_ext1"; +- }; +- +- clk_ext2: clock-ext2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <133000000>; +- clock-output-names = "clk_ext2"; +- }; +- +- clk_ext3: clock-ext3 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <133000000>; +- clock-output-names = "clk_ext3"; +- }; +- +- clk_ext4: clock-ext4 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency= <133000000>; +- clock-output-names = "clk_ext4"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- A53_0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0>; +- clock-latency = <61036>; /* two CLK32 periods */ +- clocks = <&clk IMX8MQ_CLK_ARM>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- operating-points-v2 = <&a53_opp_table>; +- #cooling-cells = <2>; +- nvmem-cells = <&cpu_speed_grade>; +- nvmem-cell-names = "speed_grade"; +- }; +- +- A53_1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x1>; +- clock-latency = <61036>; /* two CLK32 periods */ +- clocks = <&clk IMX8MQ_CLK_ARM>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- operating-points-v2 = <&a53_opp_table>; +- #cooling-cells = <2>; +- }; +- +- A53_2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x2>; +- clock-latency = <61036>; /* two CLK32 periods */ +- clocks = <&clk IMX8MQ_CLK_ARM>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- operating-points-v2 = <&a53_opp_table>; +- #cooling-cells = <2>; +- }; +- +- A53_3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x3>; +- clock-latency = <61036>; /* two CLK32 periods */ +- clocks = <&clk IMX8MQ_CLK_ARM>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- operating-points-v2 = <&a53_opp_table>; +- #cooling-cells = <2>; +- }; +- +- A53_L2: l2-cache0 { +- compatible = "cache"; +- }; +- }; +- +- a53_opp_table: opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <900000>; +- /* Industrial only */ +- opp-supported-hw = <0xf>, <0x4>; +- clock-latency-ns = <150000>; +- opp-suspend; +- }; +- +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <900000>; +- /* Consumer only */ +- opp-supported-hw = <0xe>, <0x3>; +- clock-latency-ns = <150000>; +- opp-suspend; +- }; +- +- opp-1300000000 { +- opp-hz = /bits/ 64 <1300000000>; +- opp-microvolt = <1000000>; +- opp-supported-hw = <0xc>, <0x4>; +- clock-latency-ns = <150000>; +- opp-suspend; +- }; +- +- opp-1500000000 { +- opp-hz = /bits/ 64 <1500000000>; +- opp-microvolt = <1000000>; +- opp-supported-hw = <0x8>, <0x3>; +- clock-latency-ns = <150000>; +- opp-suspend; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = ; +- interrupt-parent = <&gic>; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <250>; +- polling-delay = <2000>; +- thermal-sensors = <&tmu 0>; +- +- trips { +- cpu_alert: cpu-alert { +- temperature = <80000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu-crit { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert>; +- cooling-device = +- <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- gpu-thermal { +- polling-delay-passive = <250>; +- polling-delay = <2000>; +- thermal-sensors = <&tmu 1>; +- +- trips { +- gpu_alert: gpu-alert { +- temperature = <80000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- gpu-crit { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&gpu_alert>; +- cooling-device = +- <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- vpu-thermal { +- polling-delay-passive = <250>; +- polling-delay = <2000>; +- thermal-sensors = <&tmu 2>; +- +- trips { +- vpu-crit { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , /* Physical Secure */ +- , /* Physical Non-Secure */ +- , /* Virtual */ +- ; /* Hypervisor */ +- interrupt-parent = <&gic>; +- arm,no-tick-in-suspend; +- }; +- +- soc@0 { +- compatible = "fsl,imx8mq-soc", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x0 0x3e000000>; +- dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; +- nvmem-cells = <&imx8mq_uid>; +- nvmem-cell-names = "soc_unique_id"; +- +- bus@30000000 { /* AIPS1 */ +- compatible = "fsl,aips-bus", "simple-bus"; +- reg = <0x30000000 0x400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x30000000 0x30000000 0x400000>; +- +- sai1: sai@30010000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx8mq-sai"; +- reg = <0x30010000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, +- <&clk IMX8MQ_CLK_SAI1_ROOT>, +- <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sai6: sai@30030000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx8mq-sai"; +- reg = <0x30030000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, +- <&clk IMX8MQ_CLK_SAI6_ROOT>, +- <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sai5: sai@30040000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx8mq-sai"; +- reg = <0x30040000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, +- <&clk IMX8MQ_CLK_SAI5_ROOT>, +- <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sai4: sai@30050000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx8mq-sai"; +- reg = <0x30050000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, +- <&clk IMX8MQ_CLK_SAI4_ROOT>, +- <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- gpio1: gpio@30200000 { +- compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; +- reg = <0x30200000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 10 30>; +- }; +- +- gpio2: gpio@30210000 { +- compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; +- reg = <0x30210000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 40 21>; +- }; +- +- gpio3: gpio@30220000 { +- compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; +- reg = <0x30220000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 61 26>; +- }; +- +- gpio4: gpio@30230000 { +- compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; +- reg = <0x30230000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 87 32>; +- }; +- +- gpio5: gpio@30240000 { +- compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; +- reg = <0x30240000 0x10000>; +- interrupts = , +- ; +- clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&iomuxc 0 119 30>; +- }; +- +- tmu: tmu@30260000 { +- compatible = "fsl,imx8mq-tmu"; +- reg = <0x30260000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; +- little-endian; +- fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; +- fsl,tmu-calibration = <0x00000000 0x00000023 +- 0x00000001 0x00000029 +- 0x00000002 0x0000002f +- 0x00000003 0x00000035 +- 0x00000004 0x0000003d +- 0x00000005 0x00000043 +- 0x00000006 0x0000004b +- 0x00000007 0x00000051 +- 0x00000008 0x00000057 +- 0x00000009 0x0000005f +- 0x0000000a 0x00000067 +- 0x0000000b 0x0000006f +- +- 0x00010000 0x0000001b +- 0x00010001 0x00000023 +- 0x00010002 0x0000002b +- 0x00010003 0x00000033 +- 0x00010004 0x0000003b +- 0x00010005 0x00000043 +- 0x00010006 0x0000004b +- 0x00010007 0x00000055 +- 0x00010008 0x0000005d +- 0x00010009 0x00000067 +- 0x0001000a 0x00000070 +- +- 0x00020000 0x00000017 +- 0x00020001 0x00000023 +- 0x00020002 0x0000002d +- 0x00020003 0x00000037 +- 0x00020004 0x00000041 +- 0x00020005 0x0000004b +- 0x00020006 0x00000057 +- 0x00020007 0x00000063 +- 0x00020008 0x0000006f +- +- 0x00030000 0x00000015 +- 0x00030001 0x00000021 +- 0x00030002 0x0000002d +- 0x00030003 0x00000039 +- 0x00030004 0x00000045 +- 0x00030005 0x00000053 +- 0x00030006 0x0000005f +- 0x00030007 0x00000071>; +- #thermal-sensor-cells = <1>; +- }; +- +- wdog1: watchdog@30280000 { +- compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; +- reg = <0x30280000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; +- status = "disabled"; +- }; +- +- wdog2: watchdog@30290000 { +- compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; +- reg = <0x30290000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; +- status = "disabled"; +- }; +- +- wdog3: watchdog@302a0000 { +- compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; +- reg = <0x302a0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; +- status = "disabled"; +- }; +- +- sdma2: sdma@302c0000 { +- compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; +- reg = <0x302c0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, +- <&clk IMX8MQ_CLK_SDMA2_ROOT>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; +- }; +- +- lcdif: lcd-controller@30320000 { +- compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; +- reg = <0x30320000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; +- clock-names = "pix"; +- assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, +- <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, +- <&clk IMX8MQ_CLK_LCDIF_PIXEL>, +- <&clk IMX8MQ_VIDEO_PLL1>; +- assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, +- <&clk IMX8MQ_VIDEO_PLL1>, +- <&clk IMX8MQ_VIDEO_PLL1_OUT>; +- assigned-clock-rates = <0>, <0>, <0>, <594000000>; +- status = "disabled"; +- +- port { +- lcdif_mipi_dsi: endpoint { +- remote-endpoint = <&mipi_dsi_lcdif_in>; +- }; +- }; +- }; +- +- iomuxc: pinctrl@30330000 { +- compatible = "fsl,imx8mq-iomuxc"; +- reg = <0x30330000 0x10000>; +- }; +- +- iomuxc_gpr: syscon@30340000 { +- compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", +- "syscon", "simple-mfd"; +- reg = <0x30340000 0x10000>; +- +- mux: mux-controller { +- compatible = "mmio-mux"; +- #mux-control-cells = <1>; +- mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ +- }; +- }; +- +- ocotp: efuse@30350000 { +- compatible = "fsl,imx8mq-ocotp", "syscon"; +- reg = <0x30350000 0x10000>; +- clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- imx8mq_uid: soc-uid@410 { +- reg = <0x4 0x8>; +- }; +- +- cpu_speed_grade: speed-grade@10 { +- reg = <0x10 4>; +- }; +- +- fec_mac_address: mac-address@90 { +- reg = <0x90 6>; +- }; +- }; +- +- anatop: syscon@30360000 { +- compatible = "fsl,imx8mq-anatop", "syscon"; +- reg = <0x30360000 0x10000>; +- interrupts = ; +- }; +- +- snvs: snvs@30370000 { +- compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; +- reg = <0x30370000 0x10000>; +- +- snvs_rtc: snvs-rtc-lp{ +- compatible = "fsl,sec-v4.0-mon-rtc-lp"; +- regmap =<&snvs>; +- offset = <0x34>; +- interrupts = , +- ; +- clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; +- clock-names = "snvs-rtc"; +- }; +- +- snvs_pwrkey: snvs-powerkey { +- compatible = "fsl,sec-v4.0-pwrkey"; +- regmap = <&snvs>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; +- clock-names = "snvs-pwrkey"; +- linux,keycode = ; +- wakeup-source; +- status = "disabled"; +- }; +- }; +- +- clk: clock-controller@30380000 { +- compatible = "fsl,imx8mq-ccm"; +- reg = <0x30380000 0x10000>; +- interrupts = , +- ; +- #clock-cells = <1>; +- clocks = <&ckil>, <&osc_25m>, <&osc_27m>, +- <&clk_ext1>, <&clk_ext2>, +- <&clk_ext3>, <&clk_ext4>; +- clock-names = "ckil", "osc_25m", "osc_27m", +- "clk_ext1", "clk_ext2", +- "clk_ext3", "clk_ext4"; +- assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, +- <&clk IMX8MQ_CLK_A53_CORE>, +- <&clk IMX8MQ_CLK_NOC>, +- <&clk IMX8MQ_CLK_AUDIO_AHB>, +- <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, +- <&clk IMX8MQ_AUDIO_PLL2_BYPASS>, +- <&clk IMX8MQ_AUDIO_PLL1>, +- <&clk IMX8MQ_AUDIO_PLL2>; +- assigned-clock-rates = <0>, <0>, +- <800000000>, +- <0>, +- <0>, +- <0>, +- <786432000>, +- <722534400>; +- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, +- <&clk IMX8MQ_ARM_PLL_OUT>, +- <0>, +- <&clk IMX8MQ_SYS2_PLL_500M>, +- <&clk IMX8MQ_AUDIO_PLL1>, +- <&clk IMX8MQ_AUDIO_PLL2>; +- }; +- +- src: reset-controller@30390000 { +- compatible = "fsl,imx8mq-src", "syscon"; +- reg = <0x30390000 0x10000>; +- interrupts = ; +- #reset-cells = <1>; +- }; +- +- gpc: gpc@303a0000 { +- compatible = "fsl,imx8mq-gpc"; +- reg = <0x303a0000 0x10000>; +- interrupts = ; +- interrupt-parent = <&gic>; +- interrupt-controller; +- #interrupt-cells = <3>; +- +- pgc { +- #address-cells = <1>; +- #size-cells = <0>; +- +- pgc_mipi: power-domain@0 { +- #power-domain-cells = <0>; +- reg = ; +- }; +- +- /* +- * As per comment in ATF source code: +- * +- * PCIE1 and PCIE2 share the +- * same reset signal, if we +- * power down PCIE2, PCIE1 +- * will be held in reset too. +- * +- * So instead of creating two +- * separate power domains for +- * PCIE1 and PCIE2 we create a +- * link between both and use +- * it as a shared PCIE power +- * domain. +- */ +- pgc_pcie: power-domain@1 { +- #power-domain-cells = <0>; +- reg = ; +- power-domains = <&pgc_pcie2>; +- }; +- +- pgc_otg1: power-domain@2 { +- #power-domain-cells = <0>; +- reg = ; +- }; +- +- pgc_otg2: power-domain@3 { +- #power-domain-cells = <0>; +- reg = ; +- }; +- +- pgc_ddr1: power-domain@4 { +- #power-domain-cells = <0>; +- reg = ; +- }; +- +- pgc_gpu: power-domain@5 { +- #power-domain-cells = <0>; +- reg = ; +- clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, +- <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, +- <&clk IMX8MQ_CLK_GPU_AXI>, +- <&clk IMX8MQ_CLK_GPU_AHB>; +- }; +- +- pgc_vpu: power-domain@6 { +- #power-domain-cells = <0>; +- reg = ; +- clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; +- }; +- +- pgc_disp: power-domain@7 { +- #power-domain-cells = <0>; +- reg = ; +- }; +- +- pgc_mipi_csi1: power-domain@8 { +- #power-domain-cells = <0>; +- reg = ; +- }; +- +- pgc_mipi_csi2: power-domain@9 { +- #power-domain-cells = <0>; +- reg = ; +- }; +- +- pgc_pcie2: power-domain@a { +- #power-domain-cells = <0>; +- reg = ; +- }; +- }; +- }; +- }; +- +- bus@30400000 { /* AIPS2 */ +- compatible = "fsl,aips-bus", "simple-bus"; +- reg = <0x30400000 0x400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x30400000 0x30400000 0x400000>; +- +- pwm1: pwm@30660000 { +- compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; +- reg = <0x30660000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, +- <&clk IMX8MQ_CLK_PWM1_ROOT>; +- clock-names = "ipg", "per"; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm2: pwm@30670000 { +- compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; +- reg = <0x30670000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, +- <&clk IMX8MQ_CLK_PWM2_ROOT>; +- clock-names = "ipg", "per"; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm3: pwm@30680000 { +- compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; +- reg = <0x30680000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, +- <&clk IMX8MQ_CLK_PWM3_ROOT>; +- clock-names = "ipg", "per"; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm4: pwm@30690000 { +- compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; +- reg = <0x30690000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, +- <&clk IMX8MQ_CLK_PWM4_ROOT>; +- clock-names = "ipg", "per"; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- system_counter: timer@306a0000 { +- compatible = "nxp,sysctr-timer"; +- reg = <0x306a0000 0x20000>; +- interrupts = ; +- clocks = <&osc_25m>; +- clock-names = "per"; +- }; +- }; +- +- bus@30800000 { /* AIPS3 */ +- compatible = "fsl,aips-bus", "simple-bus"; +- reg = <0x30800000 0x400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x30800000 0x30800000 0x400000>, +- <0x08000000 0x08000000 0x10000000>; +- +- spdif1: spdif@30810000 { +- compatible = "fsl,imx35-spdif"; +- reg = <0x30810000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ +- <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ +- <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */ +- <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ +- <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ +- <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ +- <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ +- <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ +- <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ +- <&clk IMX8MQ_CLK_DUMMY>; /* spba */ +- clock-names = "core", "rxtx0", +- "rxtx1", "rxtx2", +- "rxtx3", "rxtx4", +- "rxtx5", "rxtx6", +- "rxtx7", "spba"; +- dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ecspi1: spi@30820000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; +- reg = <0x30820000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, +- <&clk IMX8MQ_CLK_ECSPI1_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ecspi2: spi@30830000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; +- reg = <0x30830000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, +- <&clk IMX8MQ_CLK_ECSPI2_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- ecspi3: spi@30840000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; +- reg = <0x30840000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, +- <&clk IMX8MQ_CLK_ECSPI3_ROOT>; +- clock-names = "ipg", "per"; +- dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart1: serial@30860000 { +- compatible = "fsl,imx8mq-uart", +- "fsl,imx6q-uart"; +- reg = <0x30860000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, +- <&clk IMX8MQ_CLK_UART1_ROOT>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart3: serial@30880000 { +- compatible = "fsl,imx8mq-uart", +- "fsl,imx6q-uart"; +- reg = <0x30880000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, +- <&clk IMX8MQ_CLK_UART3_ROOT>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- uart2: serial@30890000 { +- compatible = "fsl,imx8mq-uart", +- "fsl,imx6q-uart"; +- reg = <0x30890000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, +- <&clk IMX8MQ_CLK_UART2_ROOT>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- spdif2: spdif@308a0000 { +- compatible = "fsl,imx35-spdif"; +- reg = <0x308a0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ +- <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ +- <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */ +- <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ +- <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ +- <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ +- <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ +- <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ +- <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ +- <&clk IMX8MQ_CLK_DUMMY>; /* spba */ +- clock-names = "core", "rxtx0", +- "rxtx1", "rxtx2", +- "rxtx3", "rxtx4", +- "rxtx5", "rxtx6", +- "rxtx7", "spba"; +- dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sai2: sai@308b0000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx8mq-sai"; +- reg = <0x308b0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, +- <&clk IMX8MQ_CLK_SAI2_ROOT>, +- <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sai3: sai@308c0000 { +- #sound-dai-cells = <0>; +- compatible = "fsl,imx8mq-sai"; +- reg = <0x308c0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, +- <&clk IMX8MQ_CLK_SAI3_ROOT>, +- <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; +- clock-names = "bus", "mclk1", "mclk2", "mclk3"; +- dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- crypto: crypto@30900000 { +- compatible = "fsl,sec-v4.0"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x30900000 0x40000>; +- ranges = <0 0x30900000 0x40000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_AHB>, +- <&clk IMX8MQ_CLK_IPG_ROOT>; +- clock-names = "aclk", "ipg"; +- +- sec_jr0: jr@1000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x1000 0x1000>; +- interrupts = ; +- }; +- +- sec_jr1: jr@2000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x2000 0x1000>; +- interrupts = ; +- }; +- +- sec_jr2: jr@3000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x3000 0x1000>; +- interrupts = ; +- }; +- }; +- +- mipi_dsi: mipi-dsi@30a00000 { +- compatible = "fsl,imx8mq-nwl-dsi"; +- reg = <0x30a00000 0x300>; +- clocks = <&clk IMX8MQ_CLK_DSI_CORE>, +- <&clk IMX8MQ_CLK_DSI_AHB>, +- <&clk IMX8MQ_CLK_DSI_IPG_DIV>, +- <&clk IMX8MQ_CLK_DSI_PHY_REF>, +- <&clk IMX8MQ_CLK_LCDIF_PIXEL>; +- clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; +- assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>, +- <&clk IMX8MQ_CLK_DSI_CORE>, +- <&clk IMX8MQ_CLK_DSI_IPG_DIV>; +- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>, +- <&clk IMX8MQ_SYS1_PLL_266M>; +- assigned-clock-rates = <80000000>, <266000000>, <20000000>; +- interrupts = ; +- mux-controls = <&mux 0>; +- power-domains = <&pgc_mipi>; +- phys = <&dphy>; +- phy-names = "dphy"; +- resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, +- <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, +- <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, +- <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; +- reset-names = "byte", "dpi", "esc", "pclk"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- mipi_dsi_lcdif_in: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&lcdif_mipi_dsi>; +- }; +- }; +- }; +- }; +- +- dphy: dphy@30a00300 { +- compatible = "fsl,imx8mq-mipi-dphy"; +- reg = <0x30a00300 0x100>; +- clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; +- clock-names = "phy_ref"; +- assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, +- <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, +- <&clk IMX8MQ_CLK_DSI_PHY_REF>, +- <&clk IMX8MQ_VIDEO_PLL1>; +- assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, +- <&clk IMX8MQ_VIDEO_PLL1>, +- <&clk IMX8MQ_VIDEO_PLL1_OUT>; +- assigned-clock-rates = <0>, <0>, <24000000>, <594000000>; +- #phy-cells = <0>; +- power-domains = <&pgc_mipi>; +- status = "disabled"; +- }; +- +- i2c1: i2c@30a20000 { +- compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; +- reg = <0x30a20000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@30a30000 { +- compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; +- reg = <0x30a30000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@30a40000 { +- compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; +- reg = <0x30a40000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@30a50000 { +- compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; +- reg = <0x30a50000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- uart4: serial@30a60000 { +- compatible = "fsl,imx8mq-uart", +- "fsl,imx6q-uart"; +- reg = <0x30a60000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, +- <&clk IMX8MQ_CLK_UART4_ROOT>; +- clock-names = "ipg", "per"; +- status = "disabled"; +- }; +- +- mipi_csi1: csi@30a70000 { +- compatible = "fsl,imx8mq-mipi-csi2"; +- reg = <0x30a70000 0x1000>; +- clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, +- <&clk IMX8MQ_CLK_CSI1_ESC>, +- <&clk IMX8MQ_CLK_CSI1_PHY_REF>; +- clock-names = "core", "esc", "ui"; +- assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, +- <&clk IMX8MQ_CLK_CSI1_PHY_REF>, +- <&clk IMX8MQ_CLK_CSI1_ESC>; +- assigned-clock-rates = <266000000>, <333000000>, <66000000>; +- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, +- <&clk IMX8MQ_SYS2_PLL_1000M>, +- <&clk IMX8MQ_SYS1_PLL_800M>; +- power-domains = <&pgc_mipi_csi1>; +- resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>, +- <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>, +- <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>; +- fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>; +- interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>; +- interconnect-names = "dram"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <1>; +- +- csi1_mipi_ep: endpoint { +- remote-endpoint = <&csi1_ep>; +- }; +- }; +- }; +- }; +- +- csi1: csi@30a90000 { +- compatible = "fsl,imx8mq-csi", "fsl,imx7-csi"; +- reg = <0x30a90000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>; +- clock-names = "mclk"; +- status = "disabled"; +- +- port { +- csi1_ep: endpoint { +- remote-endpoint = <&csi1_mipi_ep>; +- }; +- }; +- }; +- +- mipi_csi2: csi@30b60000 { +- compatible = "fsl,imx8mq-mipi-csi2"; +- reg = <0x30b60000 0x1000>; +- clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, +- <&clk IMX8MQ_CLK_CSI2_ESC>, +- <&clk IMX8MQ_CLK_CSI2_PHY_REF>; +- clock-names = "core", "esc", "ui"; +- assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, +- <&clk IMX8MQ_CLK_CSI2_PHY_REF>, +- <&clk IMX8MQ_CLK_CSI2_ESC>; +- assigned-clock-rates = <266000000>, <333000000>, <66000000>; +- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, +- <&clk IMX8MQ_SYS2_PLL_1000M>, +- <&clk IMX8MQ_SYS1_PLL_800M>; +- power-domains = <&pgc_mipi_csi2>; +- resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>, +- <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>, +- <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>; +- fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>; +- interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>; +- interconnect-names = "dram"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <1>; +- +- csi2_mipi_ep: endpoint { +- remote-endpoint = <&csi2_ep>; +- }; +- }; +- }; +- }; +- +- csi2: csi@30b80000 { +- compatible = "fsl,imx8mq-csi", "fsl,imx7-csi"; +- reg = <0x30b80000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>; +- clock-names = "mclk"; +- status = "disabled"; +- +- port { +- csi2_ep: endpoint { +- remote-endpoint = <&csi2_mipi_ep>; +- }; +- }; +- }; +- +- mu: mailbox@30aa0000 { +- compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; +- reg = <0x30aa0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_MU_ROOT>; +- #mbox-cells = <2>; +- }; +- +- usdhc1: mmc@30b40000 { +- compatible = "fsl,imx8mq-usdhc", +- "fsl,imx7d-usdhc"; +- reg = <0x30b40000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, +- <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, +- <&clk IMX8MQ_CLK_USDHC1_ROOT>; +- clock-names = "ipg", "ahb", "per"; +- fsl,tuning-start-tap = <20>; +- fsl,tuning-step = <2>; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usdhc2: mmc@30b50000 { +- compatible = "fsl,imx8mq-usdhc", +- "fsl,imx7d-usdhc"; +- reg = <0x30b50000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, +- <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, +- <&clk IMX8MQ_CLK_USDHC2_ROOT>; +- clock-names = "ipg", "ahb", "per"; +- fsl,tuning-start-tap = <20>; +- fsl,tuning-step = <2>; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- qspi0: spi@30bb0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi"; +- reg = <0x30bb0000 0x10000>, +- <0x08000000 0x10000000>; +- reg-names = "QuadSPI", "QuadSPI-memory"; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, +- <&clk IMX8MQ_CLK_QSPI_ROOT>; +- clock-names = "qspi_en", "qspi"; +- status = "disabled"; +- }; +- +- sdma1: sdma@30bd0000 { +- compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; +- reg = <0x30bd0000 0x10000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, +- <&clk IMX8MQ_CLK_AHB>; +- clock-names = "ipg", "ahb"; +- #dma-cells = <3>; +- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; +- }; +- +- fec1: ethernet@30be0000 { +- compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; +- reg = <0x30be0000 0x10000>; +- interrupts = , +- , +- , +- ; +- clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, +- <&clk IMX8MQ_CLK_ENET1_ROOT>, +- <&clk IMX8MQ_CLK_ENET_TIMER>, +- <&clk IMX8MQ_CLK_ENET_REF>, +- <&clk IMX8MQ_CLK_ENET_PHY_REF>; +- clock-names = "ipg", "ahb", "ptp", +- "enet_clk_ref", "enet_out"; +- assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>, +- <&clk IMX8MQ_CLK_ENET_TIMER>, +- <&clk IMX8MQ_CLK_ENET_REF>, +- <&clk IMX8MQ_CLK_ENET_PHY_REF>; +- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, +- <&clk IMX8MQ_SYS2_PLL_100M>, +- <&clk IMX8MQ_SYS2_PLL_125M>, +- <&clk IMX8MQ_SYS2_PLL_50M>; +- assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; +- fsl,num-tx-queues = <3>; +- fsl,num-rx-queues = <3>; +- nvmem-cells = <&fec_mac_address>; +- nvmem-cell-names = "mac-address"; +- nvmem_macaddr_swap; +- fsl,stop-mode = <&iomuxc_gpr 0x10 3>; +- status = "disabled"; +- }; +- }; +- +- noc: interconnect@32700000 { +- compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc"; +- reg = <0x32700000 0x100000>; +- clocks = <&clk IMX8MQ_CLK_NOC>; +- fsl,ddrc = <&ddrc>; +- #interconnect-cells = <1>; +- operating-points-v2 = <&noc_opp_table>; +- +- noc_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-133M { +- opp-hz = /bits/ 64 <133333333>; +- }; +- +- opp-400M { +- opp-hz = /bits/ 64 <400000000>; +- }; +- +- opp-800M { +- opp-hz = /bits/ 64 <800000000>; +- }; +- }; +- }; +- +- bus@32c00000 { /* AIPS4 */ +- compatible = "fsl,aips-bus", "simple-bus"; +- reg = <0x32c00000 0x400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x32c00000 0x32c00000 0x400000>; +- +- irqsteer: interrupt-controller@32e2d000 { +- compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; +- reg = <0x32e2d000 0x1000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; +- clock-names = "ipg"; +- fsl,channel = <0>; +- fsl,num-irqs = <64>; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- }; +- +- gpu: gpu@38000000 { +- compatible = "vivante,gc"; +- reg = <0x38000000 0x40000>; +- interrupts = ; +- clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, +- <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, +- <&clk IMX8MQ_CLK_GPU_AXI>, +- <&clk IMX8MQ_CLK_GPU_AHB>; +- clock-names = "core", "shader", "bus", "reg"; +- #cooling-cells = <2>; +- assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, +- <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, +- <&clk IMX8MQ_CLK_GPU_AXI>, +- <&clk IMX8MQ_CLK_GPU_AHB>, +- <&clk IMX8MQ_GPU_PLL_BYPASS>; +- assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, +- <&clk IMX8MQ_GPU_PLL_OUT>, +- <&clk IMX8MQ_GPU_PLL_OUT>, +- <&clk IMX8MQ_GPU_PLL_OUT>, +- <&clk IMX8MQ_GPU_PLL>; +- assigned-clock-rates = <800000000>, <800000000>, +- <800000000>, <800000000>, <0>; +- power-domains = <&pgc_gpu>; +- }; +- +- usb_dwc3_0: usb@38100000 { +- compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; +- reg = <0x38100000 0x10000>; +- clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>, +- <&clk IMX8MQ_CLK_USB_CORE_REF>, +- <&clk IMX8MQ_CLK_32K>; +- clock-names = "bus_early", "ref", "suspend"; +- assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, +- <&clk IMX8MQ_CLK_USB_CORE_REF>; +- assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, +- <&clk IMX8MQ_SYS1_PLL_100M>; +- assigned-clock-rates = <500000000>, <100000000>; +- interrupts = ; +- phys = <&usb3_phy0>, <&usb3_phy0>; +- phy-names = "usb2-phy", "usb3-phy"; +- power-domains = <&pgc_otg1>; +- usb3-resume-missing-cas; +- status = "disabled"; +- }; +- +- usb3_phy0: usb-phy@381f0040 { +- compatible = "fsl,imx8mq-usb-phy"; +- reg = <0x381f0040 0x40>; +- clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; +- clock-names = "phy"; +- assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; +- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; +- assigned-clock-rates = <100000000>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- usb_dwc3_1: usb@38200000 { +- compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; +- reg = <0x38200000 0x10000>; +- clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>, +- <&clk IMX8MQ_CLK_USB_CORE_REF>, +- <&clk IMX8MQ_CLK_32K>; +- clock-names = "bus_early", "ref", "suspend"; +- assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, +- <&clk IMX8MQ_CLK_USB_CORE_REF>; +- assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, +- <&clk IMX8MQ_SYS1_PLL_100M>; +- assigned-clock-rates = <500000000>, <100000000>; +- interrupts = ; +- phys = <&usb3_phy1>, <&usb3_phy1>; +- phy-names = "usb2-phy", "usb3-phy"; +- power-domains = <&pgc_otg2>; +- usb3-resume-missing-cas; +- status = "disabled"; +- }; +- +- usb3_phy1: usb-phy@382f0040 { +- compatible = "fsl,imx8mq-usb-phy"; +- reg = <0x382f0040 0x40>; +- clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; +- clock-names = "phy"; +- assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; +- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; +- assigned-clock-rates = <100000000>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- vpu: video-codec@38300000 { +- compatible = "nxp,imx8mq-vpu"; +- reg = <0x38300000 0x10000>, +- <0x38310000 0x10000>, +- <0x38320000 0x10000>; +- reg-names = "g1", "g2", "ctrl"; +- interrupts = , +- ; +- interrupt-names = "g1", "g2"; +- clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, +- <&clk IMX8MQ_CLK_VPU_G2_ROOT>, +- <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; +- clock-names = "g1", "g2", "bus"; +- assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, +- <&clk IMX8MQ_CLK_VPU_G2>, +- <&clk IMX8MQ_CLK_VPU_BUS>, +- <&clk IMX8MQ_VPU_PLL_BYPASS>; +- assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, +- <&clk IMX8MQ_VPU_PLL_OUT>, +- <&clk IMX8MQ_SYS1_PLL_800M>, +- <&clk IMX8MQ_VPU_PLL>; +- assigned-clock-rates = <600000000>, <600000000>, +- <800000000>, <0>; +- power-domains = <&pgc_vpu>; +- }; +- +- pcie0: pcie@33800000 { +- compatible = "fsl,imx8mq-pcie"; +- reg = <0x33800000 0x400000>, +- <0x1ff00000 0x80000>; +- reg-names = "dbi", "config"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- bus-range = <0x00 0xff>; +- ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ +- 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ +- num-lanes = <1>; +- num-viewport = <4>; +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; +- fsl,max-link-speed = <2>; +- linux,pci-domain = <0>; +- power-domains = <&pgc_pcie>; +- resets = <&src IMX8MQ_RESET_PCIEPHY>, +- <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, +- <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; +- reset-names = "pciephy", "apps", "turnoff"; +- assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, +- <&clk IMX8MQ_CLK_PCIE1_PHY>, +- <&clk IMX8MQ_CLK_PCIE1_AUX>; +- assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, +- <&clk IMX8MQ_SYS2_PLL_100M>, +- <&clk IMX8MQ_SYS1_PLL_80M>; +- assigned-clock-rates = <250000000>, <100000000>, +- <10000000>; +- status = "disabled"; +- }; +- +- pcie1: pcie@33c00000 { +- compatible = "fsl,imx8mq-pcie"; +- reg = <0x33c00000 0x400000>, +- <0x27f00000 0x80000>; +- reg-names = "dbi", "config"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */ +- 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ +- num-lanes = <1>; +- num-viewport = <4>; +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; +- fsl,max-link-speed = <2>; +- linux,pci-domain = <1>; +- power-domains = <&pgc_pcie>; +- resets = <&src IMX8MQ_RESET_PCIEPHY2>, +- <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, +- <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; +- reset-names = "pciephy", "apps", "turnoff"; +- assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, +- <&clk IMX8MQ_CLK_PCIE2_PHY>, +- <&clk IMX8MQ_CLK_PCIE2_AUX>; +- assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, +- <&clk IMX8MQ_SYS2_PLL_100M>, +- <&clk IMX8MQ_SYS1_PLL_80M>; +- assigned-clock-rates = <250000000>, <100000000>, +- <10000000>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@38800000 { +- compatible = "arm,gic-v3"; +- reg = <0x38800000 0x10000>, /* GIC Dist */ +- <0x38880000 0xc0000>, /* GICR */ +- <0x31000000 0x2000>, /* GICC */ +- <0x31010000 0x2000>, /* GICV */ +- <0x31020000 0x2000>; /* GICH */ +- #interrupt-cells = <3>; +- interrupt-controller; +- interrupts = ; +- interrupt-parent = <&gic>; +- }; +- +- ddrc: memory-controller@3d400000 { +- compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; +- reg = <0x3d400000 0x400000>; +- clock-names = "core", "pll", "alt", "apb"; +- clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, +- <&clk IMX8MQ_DRAM_PLL_OUT>, +- <&clk IMX8MQ_CLK_DRAM_ALT>, +- <&clk IMX8MQ_CLK_DRAM_APB>; +- }; +- +- ddr-pmu@3d800000 { +- compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; +- reg = <0x3d800000 0x400000>; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8qm-mek.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8qm-mek.dts +deleted file mode 100644 +index ce9d3f0b98fc..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8qm-mek.dts ++++ /dev/null +@@ -1,144 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2018-2019 NXP +- * Dong Aisheng +- */ +- +-/dts-v1/; +- +-#include "imx8qm.dtsi" +- +-/ { +- model = "Freescale i.MX8QM MEK"; +- compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; +- +- chosen { +- stdout-path = &lpuart0; +- }; +- +- cpus { +- /delete-node/ cpu-map; +- /delete-node/ cpu@100; +- /delete-node/ cpu@101; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0 0x40000000>; +- }; +- +- reg_usdhc2_vmmc: usdhc2-vmmc { +- compatible = "regulator-fixed"; +- regulator-name = "SD1_SPWR"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&lpuart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lpuart0>; +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +- }; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- bus-width = <8>; +- no-sd; +- no-sdio; +- non-removable; +- status = "okay"; +-}; +- +-&usdhc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- vmmc-supply = <®_usdhc2_vmmc>; +- cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; +- wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 +- IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 +- IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 +- IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 +- IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 +- IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 +- IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 +- IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 +- IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 +- IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 +- IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 +- IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 +- IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 +- IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 +- >; +- }; +- +- pinctrl_lpuart0: lpuart0grp { +- fsl,pins = < +- IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 +- IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 +- IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 +- IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 +- IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 +- IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 +- IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 +- IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 +- IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 +- IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 +- IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 +- IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 +- IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 +- IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 +- IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 +- IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 +- IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 +- IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8qm-ss-conn.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8qm-ss-conn.dtsi +deleted file mode 100644 +index 42637a45701c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8qm-ss-conn.dtsi ++++ /dev/null +@@ -1,21 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2019-2020 NXP +- * Dong Aisheng +- */ +- +-&fec1 { +- compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; +-}; +- +-&fec2 { +- compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; +-}; +- +-&usdhc1 { +- compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; +-}; +- +-&usdhc2 { +- compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8qm-ss-dma.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8qm-ss-dma.dtsi +deleted file mode 100644 +index bbe5f5ecfb92..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8qm-ss-dma.dtsi ++++ /dev/null +@@ -1,51 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2018-2019 NXP +- * Dong Aisheng +- */ +- +-&dma_subsys { +- uart4_lpcg: clock-controller@5a4a0000 { +- compatible = "fsl,imx8qxp-lpcg"; +- reg = <0x5a4a0000 0x10000>; +- #clock-cells = <1>; +- clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>, +- <&dma_ipg_clk>; +- clock-indices = , ; +- clock-output-names = "uart4_lpcg_baud_clk", +- "uart4_lpcg_ipg_clk"; +- power-domains = <&pd IMX_SC_R_UART_4>; +- }; +-}; +- +-&lpuart0 { +- compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; +-}; +- +-&lpuart1 { +- compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; +-}; +- +-&lpuart2 { +- compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; +-}; +- +-&lpuart3 { +- compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; +-}; +- +-&i2c0 { +- compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +-}; +- +-&i2c1 { +- compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +-}; +- +-&i2c2 { +- compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +-}; +- +-&i2c3 { +- compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8qm-ss-img.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8qm-ss-img.dtsi +deleted file mode 100644 +index 7764b4146e0a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8qm-ss-img.dtsi ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2021 NXP +- */ +- +-&jpegdec { +- compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgdec"; +-}; +- +-&jpegenc { +- compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgenc"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8qm-ss-lsio.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8qm-ss-lsio.dtsi +deleted file mode 100644 +index 30896610c654..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8qm-ss-lsio.dtsi ++++ /dev/null +@@ -1,61 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2019-2020 NXP +- * Dong Aisheng +- */ +- +-&lsio_gpio0 { +- compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +-}; +- +-&lsio_gpio1 { +- compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +-}; +- +-&lsio_gpio2 { +- compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +-}; +- +-&lsio_gpio3 { +- compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +-}; +- +-&lsio_gpio4 { +- compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +-}; +- +-&lsio_gpio5 { +- compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +-}; +- +-&lsio_gpio6 { +- compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +-}; +- +-&lsio_gpio7 { +- compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +-}; +- +-&lsio_mu0 { +- compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +-}; +- +-&lsio_mu1 { +- compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +-}; +- +-&lsio_mu2 { +- compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +-}; +- +-&lsio_mu3 { +- compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +-}; +- +-&lsio_mu4 { +- compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +-}; +- +-&lsio_mu13 { +- compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8qm.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8qm.dtsi +deleted file mode 100644 +index aebbe2b84aa1..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8qm.dtsi ++++ /dev/null +@@ -1,178 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2018-2019 NXP +- * Dong Aisheng +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- mmc0 = &usdhc1; +- mmc1 = &usdhc2; +- mmc2 = &usdhc3; +- serial0 = &lpuart0; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&A53_0>; +- }; +- core1 { +- cpu = <&A53_1>; +- }; +- core2 { +- cpu = <&A53_2>; +- }; +- core3 { +- cpu = <&A53_3>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&A72_0>; +- }; +- core1 { +- cpu = <&A72_1>; +- }; +- }; +- }; +- +- A53_0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53", "arm,armv8"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- }; +- +- A53_1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53", "arm,armv8"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- }; +- +- A53_2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53", "arm,armv8"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- }; +- +- A53_3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53", "arm,armv8"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- }; +- +- A72_0: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72", "arm,armv8"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- next-level-cache = <&A72_L2>; +- }; +- +- A72_1: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72", "arm,armv8"; +- reg = <0x0 0x101>; +- enable-method = "psci"; +- next-level-cache = <&A72_L2>; +- }; +- +- A53_L2: l2-cache0 { +- compatible = "cache"; +- }; +- +- A72_L2: l2-cache1 { +- compatible = "cache"; +- }; +- }; +- +- gic: interrupt-controller@51a00000 { +- compatible = "arm,gic-v3"; +- reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ +- <0x0 0x51b00000 0 0xC0000>, /* GICR */ +- <0x0 0x52000000 0 0x2000>, /* GICC */ +- <0x0 0x52010000 0 0x1000>, /* GICH */ +- <0x0 0x52020000 0 0x20000>; /* GICV */ +- #interrupt-cells = <3>; +- interrupt-controller; +- interrupts = ; +- interrupt-parent = <&gic>; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , /* Physical Secure */ +- , /* Physical Non-Secure */ +- , /* Virtual */ +- ; /* Hypervisor */ +- }; +- +- scu { +- compatible = "fsl,imx-scu"; +- mbox-names = "tx0", +- "rx0", +- "gip3"; +- mboxes = <&lsio_mu1 0 0 +- &lsio_mu1 1 0 +- &lsio_mu1 3 3>; +- +- pd: imx8qx-pd { +- compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; +- #power-domain-cells = <1>; +- }; +- +- clk: clock-controller { +- compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; +- #clock-cells = <2>; +- }; +- +- iomuxc: pinctrl { +- compatible = "fsl,imx8qm-iomuxc"; +- }; +- +- }; +- +- /* sorted in register address */ +- #include "imx8-ss-img.dtsi" +- #include "imx8-ss-dma.dtsi" +- #include "imx8-ss-conn.dtsi" +- #include "imx8-ss-lsio.dtsi" +-}; +- +-#include "imx8qm-ss-img.dtsi" +-#include "imx8qm-ss-dma.dtsi" +-#include "imx8qm-ss-conn.dtsi" +-#include "imx8qm-ss-lsio.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-ai_ml.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-ai_ml.dts +deleted file mode 100644 +index 7d00e17f0447..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-ai_ml.dts ++++ /dev/null +@@ -1,253 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2018 Einfochips +- * Copyright 2019 Linaro Ltd. +- */ +- +-/dts-v1/; +- +-#include "imx8qxp.dtsi" +- +-/ { +- model = "Einfochips i.MX8QXP AI_ML"; +- compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp"; +- +- aliases { +- serial1 = &lpuart1; +- serial2 = &lpuart2; +- serial3 = &lpuart3; +- }; +- +- chosen { +- stdout-path = &lpuart2; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0 0x80000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_leds>; +- +- user-led1 { +- label = "green:user1"; +- gpios = <&lsio_gpio4 16 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- user-led2 { +- label = "green:user2"; +- gpios = <&lsio_gpio0 6 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "none"; +- }; +- +- user-led3 { +- label = "green:user3"; +- gpios = <&lsio_gpio0 7 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc1"; +- default-state = "off"; +- }; +- +- user-led4 { +- label = "green:user4"; +- gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; +- panic-indicator; +- linux,default-trigger = "none"; +- }; +- +- wlan-active-led { +- label = "yellow:wlan"; +- gpios = <&lsio_gpio4 17 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "phy0tx"; +- default-state = "off"; +- }; +- +- bt-active-led { +- label = "blue:bt"; +- gpios = <&lsio_gpio4 18 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "hci0-power"; +- default-state = "off"; +- }; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_wifi_reg_on>; +- reset-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-/* BT */ +-&lpuart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lpuart0>; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-/* LS-UART0 */ +-&lpuart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lpuart1>; +- status = "okay"; +-}; +- +-/* Debug */ +-&lpuart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lpuart2>; +- status = "okay"; +-}; +- +-/* PCI-E UART */ +-&lpuart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lpuart3>; +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +- }; +-}; +- +-/* WiFi */ +-&usdhc1 { +- #address-cells = <1>; +- #size-cells = <0>; +- assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- bus-width = <4>; +- no-sd; +- non-removable; +- mmc-pwrseq = <&sdio_pwrseq>; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-/* SD */ +-&usdhc2 { +- assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 +- IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 +- IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 +- IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 +- IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 +- IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 +- IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 +- IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 +- IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 +- IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 +- IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 +- IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 +- IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 +- IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 +- >; +- }; +- +- pinctrl_leds: ledsgrp{ +- fsl,pins = < +- IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 0x00000021 +- IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 0x00000021 +- IMX8QXP_EMMC0_DATA7_LSIO_GPIO4_IO16 0x00000021 +- IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 +- IMX8QXP_EMMC0_STROBE_LSIO_GPIO4_IO17 0x00000021 +- IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18 0x00000021 +- >; +- }; +- +- pinctrl_lpuart0: lpuart0grp { +- fsl,pins = < +- IMX8QXP_UART0_RX_ADMA_UART0_RX 0X06000020 +- IMX8QXP_UART0_TX_ADMA_UART0_TX 0X06000020 +- IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 +- IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 +- >; +- }; +- +- pinctrl_lpuart1: lpuart1grp { +- fsl,pins = < +- IMX8QXP_UART1_RX_ADMA_UART1_RX 0X06000020 +- IMX8QXP_UART1_TX_ADMA_UART1_TX 0X06000020 +- >; +- }; +- +- pinctrl_lpuart2: lpuart2grp { +- fsl,pins = < +- IMX8QXP_UART2_RX_ADMA_UART2_RX 0X06000020 +- IMX8QXP_UART2_TX_ADMA_UART2_TX 0X06000020 +- >; +- }; +- +- pinctrl_lpuart3: lpuart3grp { +- fsl,pins = < +- IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0X06000020 +- IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0X06000020 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 +- IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 +- IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 +- IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 +- IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 +- IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 +- IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 +- IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 +- IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 +- IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 +- IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 +- IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 +- IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 +- >; +- }; +- +- pinctrl_wifi_reg_on: wifiregongrp { +- fsl,pins = < +- IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x00000021 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-colibri-eval-v3.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-colibri-eval-v3.dts +deleted file mode 100644 +index 6b21a295c126..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-colibri-eval-v3.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2019 Toradex +- */ +- +-/dts-v1/; +- +-#include "imx8qxp-colibri.dtsi" +-#include "imx8qxp-colibri-eval-v3.dtsi" +- +-/ { +- model = "Toradex Colibri iMX8QXP/DX on Colibri Evaluation Board V3"; +- compatible = "toradex,colibri-imx8x-eval-v3", +- "toradex,colibri-imx8x", "fsl,imx8qxp"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-colibri-eval-v3.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-colibri-eval-v3.dtsi +deleted file mode 100644 +index 144fc9e82da7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-colibri-eval-v3.dtsi ++++ /dev/null +@@ -1,62 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2019 Toradex +- */ +- +-#include "dt-bindings/input/linux-event-codes.h" +- +-/ { +- aliases { +- rtc0 = &rtc_i2c; +- rtc1 = &rtc; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpiokeys>; +- +- wakeup { +- label = "Wake-Up"; +- gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- /* M41T0M6 real time clock on carrier board */ +- rtc_i2c: rtc@68 { +- compatible = "st,m41t0"; +- reg = <0x68>; +- }; +-}; +- +-/* Colibri UART_B */ +-&lpuart0 { +- status= "okay"; +-}; +- +-/* Colibri UART_C */ +-&lpuart2 { +- status= "okay"; +-}; +- +-/* Colibri UART_A */ +-&lpuart3 { +- status= "okay"; +-}; +- +-/* Colibri FastEthernet */ +-&fec1 { +- status = "okay"; +-}; +- +-/* Colibri SD/MMC Card */ +-&usdhc2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-colibri.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-colibri.dtsi +deleted file mode 100644 +index 89d70e030433..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-colibri.dtsi ++++ /dev/null +@@ -1,598 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-/* +- * Copyright 2019 Toradex +- */ +- +-#include "imx8qxp.dtsi" +- +-/ { +- model = "Toradex Colibri iMX8QXP/DX Module"; +- compatible = "toradex,colibri-imx8x", "fsl,imx8qxp"; +- +- chosen { +- stdout-path = &lpuart3; +- }; +- +- reg_module_3v3: regulator-module-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "+V3.3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +-}; +- +-/* On-module I2C */ +-&i2c0 { +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>; +- status = "okay"; +- +- /* Touch controller */ +- touchscreen@2c { +- compatible = "adi,ad7879-1"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ad7879_int>; +- reg = <0x2c>; +- interrupt-parent = <&lsio_gpio3>; +- interrupts = <5 IRQ_TYPE_EDGE_FALLING>; +- touchscreen-max-pressure = <4096>; +- adi,resistance-plate-x = <120>; +- adi,first-conversion-delay = /bits/ 8 <3>; +- adi,acquisition-time = /bits/ 8 <1>; +- adi,median-filter-size = /bits/ 8 <2>; +- adi,averaging = /bits/ 8 <1>; +- adi,conversion-interval = /bits/ 8 <255>; +- }; +-}; +- +-/* Colibri I2C */ +-&i2c1 { +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +-}; +- +-/* Colibri UART_B */ +-&lpuart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lpuart0>; +-}; +- +-/* Colibri UART_C */ +-&lpuart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lpuart2>; +-}; +- +-/* Colibri UART_A */ +-&lpuart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>; +-}; +- +-/* Colibri FastEthernet */ +-&fec1 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&pinctrl_fec1>; +- pinctrl-1 = <&pinctrl_fec1_sleep>; +- phy-mode = "rmii"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@2 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- max-speed = <100>; +- reg = <2>; +- }; +- }; +-}; +- +-/* On-module eMMC */ +-&usdhc1 { +- bus-width = <8>; +- non-removable; +- no-sd; +- no-sdio; +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- status = "okay"; +-}; +- +-/* Colibri SD/MMC Card */ +-&usdhc2 { +- bus-width = <4>; +- cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_module_3v3>; +- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; +- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; +- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; +- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +- pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; +- disable-wp; +-}; +- +-&iomuxc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>; +- +- /* On-module touch pen-down interrupt */ +- pinctrl_ad7879_int: ad7879intgrp { +- fsl,pins = < +- IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21 +- >; +- }; +- +- /* Colibri Analogue Inputs */ +- pinctrl_adc0: adc0grp { +- fsl,pins = < +- IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 /* SODIMM 8 */ +- IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 /* SODIMM 6 */ +- IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60 /* SODIMM 4 */ +- IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60 /* SODIMM 2 */ +- >; +- }; +- +- pinctrl_can_int: canintgrp { +- fsl,pins = < +- IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 73 */ +- >; +- }; +- +- pinctrl_csi_ctl: csictlgrp { +- fsl,pins = < +- IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20 /* SODIMM 77 */ +- IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20 /* SODIMM 89 */ +- >; +- }; +- +- pinctrl_ext_io0: extio0grp { +- fsl,pins = < +- IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040 /* SODIMM 135 */ +- >; +- }; +- +- /* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */ +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 +- IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 +- IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 +- IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061 +- IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 +- IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 +- IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 +- IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 +- IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 +- IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61 +- >; +- }; +- +- pinctrl_fec1_sleep: fec1slpgrp { +- fsl,pins = < +- IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041 +- IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041 +- IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41 +- IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41 +- IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41 +- IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41 +- IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41 +- IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41 +- IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41 +- IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41 +- >; +- }; +- +- /* Colibri optional CAN on UART_B RTS/CTS */ +- pinctrl_flexcan1: flexcan0grp { +- fsl,pins = < +- IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 /* SODIMM 32 */ +- IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 /* SODIMM 34 */ +- >; +- }; +- +- /* Colibri optional CAN on PS2 */ +- pinctrl_flexcan2: flexcan1grp { +- fsl,pins = < +- IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* SODIMM 55 */ +- IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* SODIMM 63 */ +- >; +- }; +- +- /* Colibri optional CAN on UART_A TXD/RXD */ +- pinctrl_flexcan3: flexcan2grp { +- fsl,pins = < +- IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* SODIMM 35 */ +- IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* SODIMM 33 */ +- >; +- }; +- +- /* Colibri LCD Back-Light GPIO */ +- pinctrl_gpio_bl_on: gpioblongrp { +- fsl,pins = < +- IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60 /* SODIMM 71 */ +- >; +- }; +- +- pinctrl_gpiokeys: gpiokeysgrp { +- fsl,pins = < +- IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041 /* SODIMM 45 */ +- >; +- }; +- +- pinctrl_hog0: hog0grp { +- fsl,pins = < +- IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* SODIMM 65 */ +- IMX8QXP_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */ +- IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */ +- IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */ +- IMX8QXP_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */ +- IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */ +- IMX8QXP_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */ +- IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */ +- IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */ +- IMX8QXP_CSI_D03_CI_PI_D05 0x61 /* SODIMM 97 */ +- IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */ +- IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */ +- IMX8QXP_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */ +- IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */ +- IMX8QXP_CSI_D01_CI_PI_D03 0x61 /* SODIMM 103 */ +- IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20 /* SODIMM 105 */ +- IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x20 /* SODIMM 107 */ +- IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20 /* SODIMM 127 */ +- IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20 /* SODIMM 131 */ +- IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */ +- IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20 /* SODIMM 96 */ +- IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20 /* SODIMM 98 */ +- IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */ +- IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20 /* SODIMM 102 */ +- IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20 /* SODIMM 104 */ +- IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x20 /* SODIMM 106 */ +- >; +- }; +- +- pinctrl_hog1: hog1grp { +- fsl,pins = < +- IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20 /* SODIMM 75 */ +- IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20 /* SODIMM 93 */ +- >; +- }; +- +- /* +- * This pin is used in the SCFW as a UART. Using it from +- * Linux would require rewritting the SCFW board file. +- */ +- pinctrl_hog_scfw: hogscfwgrp { +- fsl,pins = < +- IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20 /* SODIMM 144 */ +- >; +- }; +- +- /* On Module I2C */ +- pinctrl_i2c0: i2c0grp { +- fsl,pins = < +- IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021 +- IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021 +- >; +- }; +- +- /* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */ +- pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp { +- fsl,pins = < +- IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 /* SODIMM 140 */ +- IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 /* SODIMM 142 */ +- >; +- }; +- +- /* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */ +- pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp { +- fsl,pins = < +- IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* SODIMM 186 */ +- IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* SODIMM 188 */ +- >; +- }; +- +- /* Colibri I2C */ +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 /* SODIMM 196 */ +- IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 /* SODIMM 194 */ +- >; +- }; +- +- /* Colibri Parallel RGB LCD Interface */ +- pinctrl_lcdif: lcdifgrp { +- fsl,pins = < +- IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* SODIMM 56 */ +- IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* SODIMM 68 */ +- IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* SODIMM 82 */ +- IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* SODIMM 44 */ +- IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x60 /* SODIMM 44 */ +- IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* SODIMM 76 */ +- IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60 /* SODIMM 76 */ +- IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* SODIMM 70 */ +- IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* SODIMM 60 */ +- IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* SODIMM 58 */ +- IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* SODIMM 78 */ +- IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* SODIMM 72 */ +- IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* SODIMM 80 */ +- IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* SODIMM 46 */ +- IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* SODIMM 62 */ +- IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* SODIMM 48 */ +- IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* SODIMM 74 */ +- IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* SODIMM 50 */ +- IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* SODIMM 52 */ +- IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* SODIMM 54 */ +- IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* SODIMM 66 */ +- IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* SODIMM 64 */ +- IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* SODIMM 57 */ +- IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60 /* SODIMM 57 */ +- IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* SODIMM 61 */ +- >; +- }; +- +- /* Colibri SPI */ +- pinctrl_lpspi2: lpspi2grp { +- fsl,pins = < +- IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* SODIMM 86 */ +- IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* SODIMM 92 */ +- IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* SODIMM 90 */ +- IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* SODIMM 88 */ +- >; +- }; +- +- /* Colibri UART_B */ +- pinctrl_lpuart0: lpuart0grp { +- fsl,pins = < +- IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 /* SODIMM 36 */ +- IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 /* SODIMM 38 */ +- IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* SODIMM 34 */ +- IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* SODIMM 32 */ +- >; +- }; +- +- /* Colibri UART_C */ +- pinctrl_lpuart2: lpuart2grp { +- fsl,pins = < +- IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 /* SODIMM 19 */ +- IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 /* SODIMM 21 */ +- >; +- }; +- +- /* Colibri UART_A */ +- pinctrl_lpuart3: lpuart3grp { +- fsl,pins = < +- IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 /* SODIMM 33 */ +- IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 /* SODIMM 35 */ +- >; +- }; +- +- /* Colibri UART_A Control */ +- pinctrl_lpuart3_ctrl: lpuart3ctrlgrp { +- fsl,pins = < +- IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20 /* SODIMM 23 */ +- IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20 /* SODIMM 25 */ +- IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20 /* SODIMM 27 */ +- IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20 /* SODIMM 29 */ +- IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20 /* SODIMM 31 */ +- IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */ +- >; +- }; +- +- /* On module wifi module */ +- pinctrl_pcieb: pciebgrp { +- fsl,pins = < +- IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 /* SODIMM 178 */ +- IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 /* SODIMM 94 */ +- IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60 /* SODIMM 81 */ +- >; +- }; +- +- /* Colibri PWM_A */ +- pinctrl_pwm_a: pwmagrp { +- /* both pins are connected together, reserve the unused CSI_D05 */ +- fsl,pins = < +- IMX8QXP_CSI_D05_CI_PI_D07 0x61 /* SODIMM 59 */ +- IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60 /* SODIMM 59 */ +- >; +- }; +- +- /* Colibri PWM_B */ +- pinctrl_pwm_b: pwmbgrp { +- fsl,pins = < +- IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60 /* SODIMM 28 */ +- >; +- }; +- +- /* Colibri PWM_C */ +- pinctrl_pwm_c: pwmcgrp { +- fsl,pins = < +- IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60 /* SODIMM 30 */ +- >; +- }; +- +- /* Colibri PWM_D */ +- pinctrl_pwm_d: pwmdgrp { +- /* both pins are connected together, reserve the unused CSI_D04 */ +- fsl,pins = < +- IMX8QXP_CSI_D04_CI_PI_D06 0x61 /* SODIMM 67 */ +- IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* SODIMM 67 */ +- >; +- }; +- +- /* On-module I2S */ +- pinctrl_sai0: sai0grp { +- fsl,pins = < +- IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040 +- IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040 +- IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040 +- IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 +- >; +- }; +- +- /* Colibri Audio Analogue Microphone GND */ +- pinctrl_sgtl5000: sgtl5000grp { +- fsl,pins = < +- /* MIC GND EN */ +- IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41 +- >; +- }; +- +- /* On-module SGTL5000 clock */ +- pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp { +- fsl,pins = < +- IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21 +- >; +- }; +- +- /* On-module USB interrupt */ +- pinctrl_usb3503a: usb3503agrp { +- fsl,pins = < +- IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61 +- >; +- }; +- +- /* Colibri USB Client Cable Detect */ +- pinctrl_usbc_det: usbcdetgrp { +- fsl,pins = < +- IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 /* SODIMM 137 */ +- >; +- }; +- +- /* USB Host Power Enable */ +- pinctrl_usbh1_reg: usbh1reggrp { +- fsl,pins = < +- IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 /* SODIMM 129 */ +- >; +- }; +- +- /* On-module eMMC */ +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 +- IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 +- IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 +- IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 +- IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 +- IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 +- IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 +- IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 +- IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 +- IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 +- IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 +- IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { +- fsl,pins = < +- IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 +- IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 +- IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 +- IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 +- IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 +- IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 +- IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 +- IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 +- IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 +- IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 +- IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 +- IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { +- fsl,pins = < +- IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 +- IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 +- IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 +- IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 +- IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 +- IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 +- IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 +- IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 +- IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 +- IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 +- IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 +- IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 +- >; +- }; +- +- /* Colibri SD/MMC Card Detect */ +- pinctrl_usdhc2_gpio: usdhc2gpiogrp { +- fsl,pins = < +- IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 /* SODIMM 43 */ +- >; +- }; +- +- pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp { +- fsl,pins = < +- IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60 /* SODIMM 43 */ +- >; +- }; +- +- /* Colibri SD/MMC Card */ +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ +- IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ +- IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ +- IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ +- IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ +- IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ +- IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 +- >; +- }; +- +- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { +- fsl,pins = < +- IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ +- IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ +- IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ +- IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ +- IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ +- IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ +- IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 +- >; +- }; +- +- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { +- fsl,pins = < +- IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ +- IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ +- IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ +- IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ +- IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ +- IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ +- IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 +- >; +- }; +- +- pinctrl_usdhc2_sleep: usdhc2slpgrp { +- fsl,pins = < +- IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 47 */ +- IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 190 */ +- IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 192 */ +- IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 49 */ +- IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 51 */ +- IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 53 */ +- IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 +- >; +- }; +- +- pinctrl_wifi: wifigrp { +- fsl,pins = < +- IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-mek.dts b/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-mek.dts +deleted file mode 100644 +index 863232a47004..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-mek.dts ++++ /dev/null +@@ -1,272 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2017~2018 NXP +- */ +- +-/dts-v1/; +- +-#include "imx8qxp.dtsi" +- +-/ { +- model = "Freescale i.MX8QXP MEK"; +- compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; +- +- chosen { +- stdout-path = &lpuart0; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0 0x40000000>; +- }; +- +- reg_usdhc2_vmmc: usdhc2-vmmc { +- compatible = "regulator-fixed"; +- regulator-name = "SD1_SPWR"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&dsp { +- status = "okay"; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_fec1>; +- phy-mode = "rgmii-id"; +- phy-handle = <ðphy0>; +- fsl,magic-packet; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +- }; +-}; +- +-&i2c1 { +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; +- status = "okay"; +- +- i2c-switch@71 { +- compatible = "nxp,pca9646", "nxp,pca9546"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x71>; +- reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- max7322: gpio@68 { +- compatible = "maxim,max7322"; +- reg = <0x68>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- }; +- +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- pressure-sensor@60 { +- compatible = "fsl,mpl3115"; +- reg = <0x60>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- pca9557_a: gpio@1a { +- compatible = "nxp,pca9557"; +- reg = <0x1a>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- pca9557_b: gpio@1d { +- compatible = "nxp,pca9557"; +- reg = <0x1d>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- light-sensor@44 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_isl29023>; +- compatible = "isil,isl29023"; +- reg = <0x44>; +- interrupt-parent = <&lsio_gpio1>; +- interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +- }; +- }; +- }; +-}; +- +-&lpuart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lpuart0>; +- status = "okay"; +-}; +- +-&scu_key { +- status = "okay"; +-}; +- +-&thermal_zones { +- pmic-thermal0 { +- polling-delay-passive = <250>; +- polling-delay = <2000>; +- thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; +- +- trips { +- pmic_alert0: trip0 { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- pmic_crit0: trip1 { +- temperature = <125000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&pmic_alert0>; +- cooling-device = +- <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +-}; +- +-&usdhc1 { +- assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- bus-width = <8>; +- no-sd; +- no-sdio; +- non-removable; +- status = "okay"; +-}; +- +-&usdhc2 { +- assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc2>; +- bus-width = <4>; +- vmmc-supply = <®_usdhc2_vmmc>; +- cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; +- wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_fec1: fec1grp { +- fsl,pins = < +- IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 +- IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 +- IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 +- IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 +- IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 +- IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 +- IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 +- IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 +- IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 +- IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 +- IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 +- IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 +- IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 +- IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 +- >; +- }; +- +- pinctrl_ioexp_rst: ioexprstgrp { +- fsl,pins = < +- IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 +- >; +- }; +- +- pinctrl_isl29023: isl29023grp { +- fsl,pins = < +- IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 +- >; +- }; +- +- pinctrl_lpi2c1: lpi2c1grp { +- fsl,pins = < +- IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 +- IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 +- >; +- }; +- +- pinctrl_lpuart0: lpuart0grp { +- fsl,pins = < +- IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 +- IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 +- IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 +- IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 +- IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 +- IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 +- IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 +- IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 +- IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 +- IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 +- IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 +- IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 +- IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 +- IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 +- IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 +- IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 +- IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 +- IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-ss-adma.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-ss-adma.dtsi +deleted file mode 100644 +index dc1daa8dc72f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-ss-adma.dtsi ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2018-2020 NXP +- * Dong Aisheng +- */ +- +-&lpuart0 { +- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; +-}; +- +-&lpuart1 { +- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; +-}; +- +-&lpuart2 { +- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; +-}; +- +-&lpuart3 { +- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; +-}; +- +-&i2c0 { +- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; +-}; +- +-&i2c1 { +- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; +-}; +- +-&i2c2 { +- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; +-}; +- +-&i2c3 { +- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-ss-conn.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-ss-conn.dtsi +deleted file mode 100644 +index 46da21af3702..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-ss-conn.dtsi ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2018-2020 NXP +- * Dong Aisheng +- */ +- +-&usdhc1 { +- compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; +-}; +- +-&usdhc2 { +- compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; +-}; +- +-&usdhc3 { +- compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; +-}; +- +-&fec1 { +- compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec", "fsl,imx6sx-fec"; +-}; +- +-&fec2 { +- compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec", "fsl,imx6sx-fec"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-ss-img.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-ss-img.dtsi +deleted file mode 100644 +index 3a087317591d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-ss-img.dtsi ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2021 NXP +- * Dong Aisheng +- */ +- +-&jpegdec { +- compatible = "nxp,imx8qxp-jpgdec"; +-}; +- +-&jpegenc { +- compatible = "nxp,imx8qxp-jpgenc"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-ss-lsio.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-ss-lsio.dtsi +deleted file mode 100644 +index 11395479ffc0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp-ss-lsio.dtsi ++++ /dev/null +@@ -1,61 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2018-2020 NXP +- * Dong Aisheng +- */ +- +-&lsio_gpio0 { +- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +-}; +- +-&lsio_gpio1 { +- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +-}; +- +-&lsio_gpio2 { +- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +-}; +- +-&lsio_gpio3 { +- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +-}; +- +-&lsio_gpio4 { +- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +-}; +- +-&lsio_gpio5 { +- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +-}; +- +-&lsio_gpio6 { +- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +-}; +- +-&lsio_gpio7 { +- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +-}; +- +-&lsio_mu0 { +- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +-}; +- +-&lsio_mu1 { +- compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +-}; +- +-&lsio_mu2 { +- compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +-}; +- +-&lsio_mu3 { +- compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +-}; +- +-&lsio_mu4 { +- compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +-}; +- +-&lsio_mu13 { +- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp.dtsi +deleted file mode 100644 +index 617618edf77e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/imx8qxp.dtsi ++++ /dev/null +@@ -1,271 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2016 Freescale Semiconductor, Inc. +- * Copyright 2017-2020 NXP +- * Dong Aisheng +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- ethernet0 = &fec1; +- ethernet1 = &fec2; +- gpio0 = &lsio_gpio0; +- gpio1 = &lsio_gpio1; +- gpio2 = &lsio_gpio2; +- gpio3 = &lsio_gpio3; +- gpio4 = &lsio_gpio4; +- gpio5 = &lsio_gpio5; +- gpio6 = &lsio_gpio6; +- gpio7 = &lsio_gpio7; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- mmc0 = &usdhc1; +- mmc1 = &usdhc2; +- mmc2 = &usdhc3; +- mu0 = &lsio_mu0; +- mu1 = &lsio_mu1; +- mu2 = &lsio_mu2; +- mu3 = &lsio_mu3; +- mu4 = &lsio_mu4; +- serial0 = &lpuart0; +- serial1 = &lpuart1; +- serial2 = &lpuart2; +- serial3 = &lpuart3; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- /* We have 1 clusters with 4 Cortex-A35 cores */ +- A35_0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- next-level-cache = <&A35_L2>; +- clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; +- operating-points-v2 = <&a35_opp_table>; +- #cooling-cells = <2>; +- }; +- +- A35_1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- next-level-cache = <&A35_L2>; +- clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; +- operating-points-v2 = <&a35_opp_table>; +- #cooling-cells = <2>; +- }; +- +- A35_2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- next-level-cache = <&A35_L2>; +- clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; +- operating-points-v2 = <&a35_opp_table>; +- #cooling-cells = <2>; +- }; +- +- A35_3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- next-level-cache = <&A35_L2>; +- clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; +- operating-points-v2 = <&a35_opp_table>; +- #cooling-cells = <2>; +- }; +- +- A35_L2: l2-cache0 { +- compatible = "cache"; +- }; +- }; +- +- a35_opp_table: opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-900000000 { +- opp-hz = /bits/ 64 <900000000>; +- opp-microvolt = <1000000>; +- clock-latency-ns = <150000>; +- }; +- +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <1100000>; +- clock-latency-ns = <150000>; +- opp-suspend; +- }; +- }; +- +- gic: interrupt-controller@51a00000 { +- compatible = "arm,gic-v3"; +- reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ +- <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ +- #interrupt-cells = <3>; +- interrupt-controller; +- interrupts = ; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- dsp_reserved: dsp@92400000 { +- reg = <0 0x92400000 0 0x2000000>; +- no-map; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a35-pmu"; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- scu { +- compatible = "fsl,imx-scu"; +- mbox-names = "tx0", +- "rx0", +- "gip3"; +- mboxes = <&lsio_mu1 0 0 +- &lsio_mu1 1 0 +- &lsio_mu1 3 3>; +- +- pd: imx8qx-pd { +- compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; +- #power-domain-cells = <1>; +- }; +- +- clk: clock-controller { +- compatible = "fsl,imx8qxp-clk"; +- #clock-cells = <2>; +- clocks = <&xtal32k &xtal24m>; +- clock-names = "xtal_32KHz", "xtal_24Mhz"; +- }; +- +- iomuxc: pinctrl { +- compatible = "fsl,imx8qxp-iomuxc"; +- }; +- +- ocotp: imx8qx-ocotp { +- compatible = "fsl,imx8qxp-scu-ocotp"; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- scu_key: scu-key { +- compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; +- linux,keycodes = ; +- status = "disabled"; +- }; +- +- rtc: rtc { +- compatible = "fsl,imx8qxp-sc-rtc"; +- }; +- +- watchdog { +- compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; +- timeout-sec = <60>; +- }; +- +- tsens: thermal-sensor { +- compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; +- #thermal-sensor-cells = <1>; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , /* Physical Secure */ +- , /* Physical Non-Secure */ +- , /* Virtual */ +- ; /* Hypervisor */ +- }; +- +- xtal32k: clock-xtal32k { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "xtal_32KHz"; +- }; +- +- xtal24m: clock-xtal24m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "xtal_24MHz"; +- }; +- +- thermal_zones: thermal-zones { +- cpu-thermal0 { +- polling-delay-passive = <250>; +- polling-delay = <2000>; +- thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; +- +- trips { +- cpu_alert0: trip0 { +- temperature = <107000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_crit0: trip1 { +- temperature = <127000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- cooling-device = +- <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- /* sorted in register address */ +- #include "imx8-ss-img.dtsi" +- #include "imx8-ss-adma.dtsi" +- #include "imx8-ss-conn.dtsi" +- #include "imx8-ss-ddr.dtsi" +- #include "imx8-ss-lsio.dtsi" +-}; +- +-#include "imx8qxp-ss-img.dtsi" +-#include "imx8qxp-ss-adma.dtsi" +-#include "imx8qxp-ss-conn.dtsi" +-#include "imx8qxp-ss-lsio.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-bman-portals.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/qoriq-bman-portals.dtsi +deleted file mode 100644 +index ff1aba5fae7f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-bman-portals.dtsi ++++ /dev/null +@@ -1,77 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * QorIQ BMan Portals device tree +- * +- * Copyright 2011-2016 Freescale Semiconductor Inc. +- * +- */ +- +-&bportals { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- +- bman-portal@0 { +- /* +- * bootloader fix-ups are expected to provide the +- * "fsl,bman-portal-" compatible +- */ +- compatible = "fsl,bman-portal"; +- reg = <0x0 0x4000>, <0x4000000 0x4000>; +- interrupts = ; +- }; +- +- bman-portal@10000 { +- compatible = "fsl,bman-portal"; +- reg = <0x10000 0x4000>, <0x4010000 0x4000>; +- interrupts = ; +- }; +- +- bman-portal@20000 { +- compatible = "fsl,bman-portal"; +- reg = <0x20000 0x4000>, <0x4020000 0x4000>; +- interrupts = ; +- }; +- +- bman-portal@30000 { +- compatible = "fsl,bman-portal"; +- reg = <0x30000 0x4000>, <0x4030000 0x4000>; +- interrupts = ; +- }; +- +- bman-portal@40000 { +- compatible = "fsl,bman-portal"; +- reg = <0x40000 0x4000>, <0x4040000 0x4000>; +- interrupts = ; +- }; +- +- bman-portal@50000 { +- compatible = "fsl,bman-portal"; +- reg = <0x50000 0x4000>, <0x4050000 0x4000>; +- interrupts = ; +- }; +- +- bman-portal@60000 { +- compatible = "fsl,bman-portal"; +- reg = <0x60000 0x4000>, <0x4060000 0x4000>; +- interrupts = ; +- }; +- +- bman-portal@70000 { +- compatible = "fsl,bman-portal"; +- reg = <0x70000 0x4000>, <0x4070000 0x4000>; +- interrupts = ; +- }; +- +- bman-portal@80000 { +- compatible = "fsl,bman-portal"; +- reg = <0x80000 0x4000>, <0x4080000 0x4000>; +- interrupts = ; +- }; +- +- bman-portal@90000 { +- compatible = "fsl,bman-portal"; +- reg = <0x90000 0x4000>, <0x4090000 0x4000>; +- interrupts = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-10g-0.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-10g-0.dtsi +deleted file mode 100644 +index dbd2fc3ba790..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-10g-0.dtsi ++++ /dev/null +@@ -1,42 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * QorIQ FMan v3 10g port #0 device tree +- * +- * Copyright 2012-2015 Freescale Semiconductor Inc. +- * +- */ +- +-fman@1a00000 { +- fman0_rx_0x10: port@90000 { +- cell-index = <0x10>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x90000 0x1000>; +- fsl,fman-10g-port; +- }; +- +- fman0_tx_0x30: port@b0000 { +- cell-index = <0x30>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xb0000 0x1000>; +- fsl,fman-10g-port; +- }; +- +- ethernet@f0000 { +- cell-index = <0x8>; +- compatible = "fsl,fman-memac"; +- reg = <0xf0000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>; +- pcsphy-handle = <&pcsphy6>; +- }; +- +- mdio@f1000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xf1000 0x1000>; +- +- pcsphy6: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-10g-1.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-10g-1.dtsi +deleted file mode 100644 +index 6fc5d2560057..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-10g-1.dtsi ++++ /dev/null +@@ -1,42 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * QorIQ FMan v3 10g port #1 device tree +- * +- * Copyright 2012-2015 Freescale Semiconductor Inc. +- * +- */ +- +-fman@1a00000 { +- fman0_rx_0x11: port@91000 { +- cell-index = <0x11>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x91000 0x1000>; +- fsl,fman-10g-port; +- }; +- +- fman0_tx_0x31: port@b1000 { +- cell-index = <0x31>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xb1000 0x1000>; +- fsl,fman-10g-port; +- }; +- +- ethernet@f2000 { +- cell-index = <0x9>; +- compatible = "fsl,fman-memac"; +- reg = <0xf2000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>; +- pcsphy-handle = <&pcsphy7>; +- }; +- +- mdio@f3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xf3000 0x1000>; +- +- pcsphy7: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-1g-0.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-1g-0.dtsi +deleted file mode 100644 +index 4e02276fcf99..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-1g-0.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * QorIQ FMan v3 1g port #0 device tree +- * +- * Copyright 2012-2015 Freescale Semiconductor Inc. +- * +- */ +- +-fman@1a00000 { +- fman0_rx_0x08: port@88000 { +- cell-index = <0x8>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x88000 0x1000>; +- }; +- +- fman0_tx_0x28: port@a8000 { +- cell-index = <0x28>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xa8000 0x1000>; +- }; +- +- ethernet@e0000 { +- cell-index = <0>; +- compatible = "fsl,fman-memac"; +- reg = <0xe0000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>; +- ptp-timer = <&ptp_timer0>; +- pcsphy-handle = <&pcsphy0>; +- }; +- +- mdio@e1000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xe1000 0x1000>; +- +- pcsphy0: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-1g-1.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-1g-1.dtsi +deleted file mode 100644 +index 0312fa43fa77..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-1g-1.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * QorIQ FMan v3 1g port #1 device tree +- * +- * Copyright 2012-2015 Freescale Semiconductor Inc. +- * +- */ +- +-fman@1a00000 { +- fman0_rx_0x09: port@89000 { +- cell-index = <0x9>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x89000 0x1000>; +- }; +- +- fman0_tx_0x29: port@a9000 { +- cell-index = <0x29>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xa9000 0x1000>; +- }; +- +- ethernet@e2000 { +- cell-index = <1>; +- compatible = "fsl,fman-memac"; +- reg = <0xe2000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>; +- ptp-timer = <&ptp_timer0>; +- pcsphy-handle = <&pcsphy1>; +- }; +- +- mdio@e3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xe3000 0x1000>; +- +- pcsphy1: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-1g-2.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-1g-2.dtsi +deleted file mode 100644 +index af2df07971dd..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-1g-2.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * QorIQ FMan v3 1g port #2 device tree +- * +- * Copyright 2012-2015 Freescale Semiconductor Inc. +- * +- */ +- +-fman@1a00000 { +- fman0_rx_0x0a: port@8a000 { +- cell-index = <0xa>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x8a000 0x1000>; +- }; +- +- fman0_tx_0x2a: port@aa000 { +- cell-index = <0x2a>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xaa000 0x1000>; +- }; +- +- ethernet@e4000 { +- cell-index = <2>; +- compatible = "fsl,fman-memac"; +- reg = <0xe4000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>; +- ptp-timer = <&ptp_timer0>; +- pcsphy-handle = <&pcsphy2>; +- }; +- +- mdio@e5000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xe5000 0x1000>; +- +- pcsphy2: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-1g-3.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-1g-3.dtsi +deleted file mode 100644 +index 4ac98dc8b227..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-1g-3.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * QorIQ FMan v3 1g port #3 device tree +- * +- * Copyright 2012-2015 Freescale Semiconductor Inc. +- * +- */ +- +-fman@1a00000 { +- fman0_rx_0x0b: port@8b000 { +- cell-index = <0xb>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x8b000 0x1000>; +- }; +- +- fman0_tx_0x2b: port@ab000 { +- cell-index = <0x2b>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xab000 0x1000>; +- }; +- +- ethernet@e6000 { +- cell-index = <3>; +- compatible = "fsl,fman-memac"; +- reg = <0xe6000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>; +- ptp-timer = <&ptp_timer0>; +- pcsphy-handle = <&pcsphy3>; +- }; +- +- mdio@e7000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xe7000 0x1000>; +- +- pcsphy3: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-1g-4.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-1g-4.dtsi +deleted file mode 100644 +index bd932d8b0160..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-1g-4.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * QorIQ FMan v3 1g port #4 device tree +- * +- * Copyright 2012-2015 Freescale Semiconductor Inc. +- * +- */ +- +-fman@1a00000 { +- fman0_rx_0x0c: port@8c000 { +- cell-index = <0xc>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x8c000 0x1000>; +- }; +- +- fman0_tx_0x2c: port@ac000 { +- cell-index = <0x2c>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xac000 0x1000>; +- }; +- +- ethernet@e8000 { +- cell-index = <4>; +- compatible = "fsl,fman-memac"; +- reg = <0xe8000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>; +- ptp-timer = <&ptp_timer0>; +- pcsphy-handle = <&pcsphy4>; +- }; +- +- mdio@e9000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xe9000 0x1000>; +- +- pcsphy4: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-1g-5.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-1g-5.dtsi +deleted file mode 100644 +index 7de1c5203f3e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0-1g-5.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * QorIQ FMan v3 1g port #5 device tree +- * +- * Copyright 2012-2015 Freescale Semiconductor Inc. +- * +- */ +- +-fman@1a00000 { +- fman0_rx_0x0d: port@8d000 { +- cell-index = <0xd>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x8d000 0x1000>; +- }; +- +- fman0_tx_0x2d: port@ad000 { +- cell-index = <0x2d>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xad000 0x1000>; +- }; +- +- ethernet@ea000 { +- cell-index = <5>; +- compatible = "fsl,fman-memac"; +- reg = <0xea000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>; +- ptp-timer = <&ptp_timer0>; +- pcsphy-handle = <&pcsphy5>; +- }; +- +- mdio@eb000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xeb000 0x1000>; +- +- pcsphy5: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0.dtsi +deleted file mode 100644 +index ae1c2abaaf36..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-fman3-0.dtsi ++++ /dev/null +@@ -1,88 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * QorIQ FMan v3 device tree +- * +- * Copyright 2012-2015 Freescale Semiconductor Inc. +- * +- */ +- +-#include +- +-fman0: fman@1a00000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- compatible = "fsl,fman"; +- ranges = <0x0 0x0 0x1a00000 0xfe000>; +- reg = <0x0 0x1a00000 0x0 0xfe000>; +- interrupts = , +- ; +- clocks = <&clockgen QORIQ_CLK_FMAN 0>; +- clock-names = "fmanclk"; +- fsl,qman-channel-range = <0x800 0x10>; +- ptimer-handle = <&ptp_timer0>; +- dma-coherent; +- +- muram@0 { +- compatible = "fsl,fman-muram"; +- reg = <0x0 0x60000>; +- }; +- +- fman0_oh_0x2: port@82000 { +- cell-index = <0x2>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x82000 0x1000>; +- }; +- +- fman0_oh_0x3: port@83000 { +- cell-index = <0x3>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x83000 0x1000>; +- }; +- +- fman0_oh_0x4: port@84000 { +- cell-index = <0x4>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x84000 0x1000>; +- }; +- +- fman0_oh_0x5: port@85000 { +- cell-index = <0x5>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x85000 0x1000>; +- }; +- +- fman0_oh_0x6: port@86000 { +- cell-index = <0x6>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x86000 0x1000>; +- }; +- +- fman0_oh_0x7: port@87000 { +- cell-index = <0x7>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x87000 0x1000>; +- }; +- +- mdio0: mdio@fc000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xfc000 0x1000>; +- }; +- +- xmdio0: mdio@fd000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xfd000 0x1000>; +- }; +-}; +- +-ptp_timer0: ptp-timer@1afe000 { +- compatible = "fsl,fman-ptp-timer"; +- reg = <0x0 0x1afe000 0x0 0x1000>; +- interrupts = ; +- clocks = <&clockgen QORIQ_CLK_FMAN 0>; +- fsl,extts-fifo; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-qman-portals.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/qoriq-qman-portals.dtsi +deleted file mode 100644 +index e3bec08b110d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/qoriq-qman-portals.dtsi ++++ /dev/null +@@ -1,87 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * QorIQ QMan Portals device tree +- * +- * Copyright 2011-2016 Freescale Semiconductor Inc. +- * +- */ +- +-&qportals { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- +- qportal0: qman-portal@0 { +- /* +- * bootloader fix-ups are expected to provide the +- * "fsl,bman-portal-" compatible +- */ +- compatible = "fsl,qman-portal"; +- reg = <0x0 0x4000>, <0x4000000 0x4000>; +- interrupts = ; +- cell-index = <0>; +- }; +- +- qportal1: qman-portal@10000 { +- compatible = "fsl,qman-portal"; +- reg = <0x10000 0x4000>, <0x4010000 0x4000>; +- interrupts = ; +- cell-index = <1>; +- }; +- +- qportal2: qman-portal@20000 { +- compatible = "fsl,qman-portal"; +- reg = <0x20000 0x4000>, <0x4020000 0x4000>; +- interrupts = ; +- cell-index = <2>; +- }; +- +- qportal3: qman-portal@30000 { +- compatible = "fsl,qman-portal"; +- reg = <0x30000 0x4000>, <0x4030000 0x4000>; +- interrupts = ; +- cell-index = <3>; +- }; +- +- qportal4: qman-portal@40000 { +- compatible = "fsl,qman-portal"; +- reg = <0x40000 0x4000>, <0x4040000 0x4000>; +- interrupts = ; +- cell-index = <4>; +- }; +- +- qportal5: qman-portal@50000 { +- compatible = "fsl,qman-portal"; +- reg = <0x50000 0x4000>, <0x4050000 0x4000>; +- interrupts = ; +- cell-index = <5>; +- }; +- +- qportal6: qman-portal@60000 { +- compatible = "fsl,qman-portal"; +- reg = <0x60000 0x4000>, <0x4060000 0x4000>; +- interrupts = ; +- cell-index = <6>; +- }; +- +- qportal7: qman-portal@70000 { +- compatible = "fsl,qman-portal"; +- reg = <0x70000 0x4000>, <0x4070000 0x4000>; +- interrupts = ; +- cell-index = <7>; +- }; +- +- qportal8: qman-portal@80000 { +- compatible = "fsl,qman-portal"; +- reg = <0x80000 0x4000>, <0x4080000 0x4000>; +- interrupts = ; +- cell-index = <8>; +- }; +- +- qportal9: qman-portal@90000 { +- compatible = "fsl,qman-portal"; +- reg = <0x90000 0x4000>, <0x4090000 0x4000>; +- interrupts = ; +- cell-index = <9>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/s32v234-evb.dts b/scripts/dtc/include-prefixes/arm64/freescale/s32v234-evb.dts +deleted file mode 100644 +index 4b802518cefc..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/s32v234-evb.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2015-2016 Freescale Semiconductor, Inc. +- * Copyright 2016-2017 NXP +- */ +- +-/dts-v1/; +-#include "s32v234.dtsi" +- +-/ { +- model = "NXP S32V234-EVB2 Board"; +- compatible = "fsl,s32v234-evb", "fsl,s32v234"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/freescale/s32v234.dtsi b/scripts/dtc/include-prefixes/arm64/freescale/s32v234.dtsi +deleted file mode 100644 +index ba0b5305d481..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/freescale/s32v234.dtsi ++++ /dev/null +@@ -1,139 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright 2015-2016 Freescale Semiconductor, Inc. +- * Copyright 2016-2018 NXP +- */ +- +-#include +- +-/memreserve/ 0x80000000 0x00010000; +- +-/ { +- compatible = "fsl,s32v234"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x80000000>; +- next-level-cache = <&cluster0_l2_cache>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x80000000>; +- next-level-cache = <&cluster0_l2_cache>; +- }; +- +- cpu2: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x100>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x80000000>; +- next-level-cache = <&cluster1_l2_cache>; +- }; +- +- cpu3: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x101>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x80000000>; +- next-level-cache = <&cluster1_l2_cache>; +- }; +- +- cluster0_l2_cache: l2-cache0 { +- compatible = "cache"; +- }; +- +- cluster1_l2_cache: l2-cache1 { +- compatible = "cache"; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- /* clock-frequency might be modified by u-boot, depending on the +- * chip version. +- */ +- clock-frequency = <10000000>; +- }; +- +- gic: interrupt-controller@7d001000 { +- compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0 0x7d001000 0 0x1000>, +- <0 0x7d002000 0 0x2000>, +- <0 0x7d004000 0 0x2000>, +- <0 0x7d006000 0 0x2000>; +- interrupts = ; +- }; +- +- soc { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- ranges; +- +- aips0: bus@40000000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&gic>; +- reg = <0x0 0x40000000 0x0 0x7d000>; +- ranges; +- +- uart0: serial@40053000 { +- compatible = "fsl,s32v234-linflexuart"; +- reg = <0x0 0x40053000 0x0 0x1000>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- aips1: bus@40080000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&gic>; +- reg = <0x0 0x40080000 0x0 0x70000>; +- ranges; +- +- uart1: serial@400bc000 { +- compatible = "fsl,s32v234-linflexuart"; +- reg = <0x0 0x400bc000 0x0 0x1000>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/Makefile b/scripts/dtc/include-prefixes/arm64/hailo/Makefile +deleted file mode 100644 +index fac88a37a10a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/Makefile ++++ /dev/null +@@ -1,16 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_HAILO15) += hailo15-evb-2-camera-vpu.dtb +-dtb-$(CONFIG_ARCH_HAILO15) += hailo15-evb-security-camera.dtb +-dtb-$(CONFIG_ARCH_HAILO15) += hailo15-ginger-imaging-imx334.dtb +-dtb-$(CONFIG_ARCH_HAILO15) += hailo15-ginger-imaging-ov2775.dtb +-dtb-$(CONFIG_ARCH_HAILO15) += hailo15-ginger-soc-sdio0.dtb +-dtb-$(CONFIG_ARCH_HAILO15) += hailo15-ginger-soc.dtb +-dtb-$(CONFIG_ARCH_HAILO15) += hailo15-lavender-dsp.dtb +-dtb-$(CONFIG_ARCH_HAILO15) += hailo15-lavender-encoder.dtb +-dtb-$(CONFIG_ARCH_HAILO15) += hailo15-lavender.dtb +-dtb-$(CONFIG_ARCH_HAILO15) += hailo15-veloce.dtb +-dtb-$(CONFIG_ARCH_HAILO15) += hailo15l-veloce.dtb +-dtb-$(CONFIG_ARCH_HAILO15) += hailo15-vp.dtb +-dtb-$(CONFIG_ARCH_HAILO15) += hailo15l-oregano.dtb +-dtb-$(CONFIG_ARCH_HAILO15) += hailo15-sbc.dtb +-dtb-$(CONFIG_ARCH_HAILO15) += hailo10-m2.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo10-base.dtsi b/scripts/dtc/include-prefixes/arm64/hailo/hailo10-base.dtsi +deleted file mode 100644 +index ec1246f7f367..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo10-base.dtsi ++++ /dev/null +@@ -1,6 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2024 Hailo Technologies Ltd. All rights reserved. +- */ +- +-#include "hailo15-base.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo10-m2-base.dtsi b/scripts/dtc/include-prefixes/arm64/hailo/hailo10-m2-base.dtsi +deleted file mode 100644 +index a35c60b40d5a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo10-m2-base.dtsi ++++ /dev/null +@@ -1,98 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2024 Hailo Technologies Ltd. All rights reserved. +- */ +- +-#include "hailo10-base.dtsi" +-#include +- +-/ { +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0x00000002 0x00000000>; +- }; +-}; +- +-&i2c_1 { +- status = "ok"; +- ina231_3v3_pci: 3v3_pci@40 { +- status = "disabled"; +- compatible = "ti,ina231_precise"; +- reg = <0x40>; +- shunt-resistor = <10000>; +- max-current = <2500>; +- }; +- +- regulator_0p8v: regulator-0p8v@43 { +- status = "disabled"; +- compatible = "ti,tps62872"; +- reg = <0x43>; +- regulator-name = "+0.8V"; +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1037500>; +- regulator-initial-mode = <2>; +- }; +- +- /* 64 KiB EEPROM */ +- eeprom: eeprom-atmel-24cs64@50 { +- status = "disabled"; +- compatible = "atmel,24cs64"; +- reg = <0x30>; +- }; +-}; +- +-&reserved_memory { +- /* set Linux,CMA area to 1 GiB */ +- cma: linux,cma { +- size = <0x0 0x40000000>; +- alloc-ranges = <0x0 0x82000000 0x0 0x40000000>; +- }; +-}; +- +-&gpio0 { +- gpio-ranges = <&pinctrl 0 0 16>; +- +- gpio-line-names = +- "gpio_in_out_0", +- "gpio_in_out_1", +- "gpio_in_out_2", +- "gpio_in_out_3", +- "gpio_in_out_4", +- "boot_rom_led", +- "gpio_in_out_6", +- "gpio_in_out_7", +- "gpio_in_out_8", +- "sdio1_reset", /* Currently not connected */ +- "rmii_rst_n", +- "gpio_in_out_11", +- "gpio_in_out_12", +- "gpio_in_out_13", +- "gpio_in_out_14", +- "gpio_in_out_15"; +-}; +- +-&gpio1 { +- gpio-ranges = <&pinctrl 0 16 16>; +- +- gpio-line-names = +- "gpio_in_out_16", +- "gpio_in_out_17", +- "gpio_in_out_18", +- "ina_alert_n", +- "gpio_in_out_20", +- "gpio_in_out_21", +- "gpio_in_out_22", +- "gpio_in_out_23", +- "gpio_in_out_24", +- "gpio_in_out_25", +- "gpio_in_out_26", +- "gpio_in_out_27", +- "gpio_in_out_28", +- "gpio_in_out_29", +- "gpio_in_out_30", +- "gpio_in_out_31"; +-}; +- +-&hailo_pci_ep_driver { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo10-m2-devel.dts b/scripts/dtc/include-prefixes/arm64/hailo/hailo10-m2-devel.dts +deleted file mode 100644 +index 56ea2cbd46a6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo10-m2-devel.dts ++++ /dev/null +@@ -1,53 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2024 Hailo Technologies Ltd. All rights reserved. +- */ +- +-/dts-v1/; +-#include "hailo10-m2-base.dtsi" +- +-&sdio1 { +- status = "okay"; +- non-removable; +- phy-config { +- card-is-emmc = <0x1>; +- cmd-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- dat-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- rst-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- clk-pad-values = <0x2 0x2 0x0 0x0>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- sdclkdl-cnfg = <0x0 0x32>; //extdly_en, cckdl_dc +- drive-strength = <0xC 0xC>; //pad_sp, pad_sn +- }; +-}; +- +-ð { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_eth>; +- phy-mode = "rmii"; +-}; +- +-&qspi { +- status = "okay"; +- spi0_flash0: flash@0 { +- /* values for MT25QU01G */ +- spi-max-frequency = <6250000>; /* 90Mhz in DTR, 166Mhz in STR */ +- cdns,read-delay = <7>; +- cdns,tshsl-ns = <30>; +- cdns,tsd2d-ns = <30>; +- cdns,tchsh-ns = <5>; +- cdns,tslch-ns = <3>; +- }; +-}; +- +-&pinctrl { +- pinctrl_eth: eth { +- pins = "eth_rgmii_tx_clk", +- "eth_rgmii_tx_ctl", +- "eth_rgmii_txd_0", +- "eth_rgmii_txd_1", +- "eth_rgmii_txd_2", +- "eth_rgmii_txd_3"; +- drive-strength = <2>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo10-m2.dts b/scripts/dtc/include-prefixes/arm64/hailo/hailo10-m2.dts +deleted file mode 100644 +index e7d27b649823..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo10-m2.dts ++++ /dev/null +@@ -1,7 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2024 Hailo Technologies Ltd. All rights reserved. +- */ +- +-/dts-v1/; +-#include "hailo10-m2-base.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-base.dtsi b/scripts/dtc/include-prefixes/arm64/hailo/hailo15-base.dtsi +deleted file mode 100644 +index c3c257b03f02..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-base.dtsi ++++ /dev/null +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2024 Hailo Technologies Ltd. All rights reserved. +- */ +- +-#define HAILO_SOC_TYPE HAILO_SOC_HAILO15 +-#include "hailo15-family-base.dtsi" +- +- +-/ { +- soc { +- compatible = "hailo,hailo15"; +- }; +- +- sram@d0000 { +- cpu_scp_i2s_dma_shmem: scp-shmem@10a0 { +- compatible = "hailo,hailo15-i2s-shmem"; +- reg = <0 0x10a0 0 0xf60>; +- }; +- }; +- +- i2s_cpu_master: audio-controller-master@10d000 { +- compatible = "hailo,hailo15-designware-i2s-scu-dma"; +- reg = <0x0 0x10d000 0x0 0x400>; +- shmem = <&cpu_scp_i2s_dma_shmem>; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_I2S_CLK_DIV>; +- clock-names = "i2sclk"; +- #sound-dai-cells = <0>; +- interrupts = ; +- interrupt-names = "i2s_irq"; +- status = "disabled"; +- }; +- +- pl320_mailbox: mailbox { +- reg = <0 0x78002000 0 0x1000>; +- }; +- +- pinctrl: pinctrl@7c291000 { +- compatible = "hailo15,pinctrl"; +- reg = <0 0x7c291000 0 0x1000>, +- <0 0x7c292000 0 0x1000>; +- reg-names = "general_pads_config_base", "gpio_pads_config_base"; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-evb-2-camera-vpu.dts b/scripts/dtc/include-prefixes/arm64/hailo/hailo15-evb-2-camera-vpu.dts +deleted file mode 100644 +index 6264c35844e4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-evb-2-camera-vpu.dts ++++ /dev/null +@@ -1,228 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2023 Hailo Technologies Ltd. All rights reserved. +- */ +- +-/dts-v1/; +-#include "hailo15-evb-base.dtsi" +-#include +- +-&i2c_2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>, <&pinctrl_i2c2_current_src_en_out>; +-}; +- +-/ { +- sensor_clk: sensor_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- }; +-}; +- +- +-&csi2rx0 { +- ports { +- port@0 { +- csi2rx_in_sensor: endpoint { +- remote-endpoint = <&sensor_out_csi2rx>; +- }; +- }; +- }; +-}; +- +-&i2c_0 { +- imx334: camera-sensor@1a { +- status = "okay"; +- compatible = "sony,imx334"; +- reg = <0x1a>; +- clocks = <&sensor_clk>; +- clock-names = "inclk"; +- clock-frequency = <24000000>; +- csi-id = <0>; +- reset-gpios = <&gpio0 0 0>; +- port { +- sensor_out_csi2rx: endpoint { +- data-lanes = <1 2 3 4>; +- remote-endpoint = <&csi2rx_in_sensor>; +- link-frequencies = /bits/ 64 <891000000>; +- }; +- }; +- }; +-}; +- +-&sdio0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdio0_CD_in>; +- broken-cd; +-}; +- +-&sdio0_reserved { +- status = "okay"; +-}; +- +-&pinctrl { +- i2c-bus = <&i2c_1>; +- board-config = ; +- +- pinctrl_i2c2: i2c2 { +- function = "i2c2"; +- groups = "i2c2_1_grp"; +- }; +- +- pinctrl_i2c0_current_src_en_out: i2c0_current_src_en_out { +- function = "i2c0_current_src_en_out"; +- groups = "i2c0_current_src_en_out_3_grp"; +- }; +- +- pinctrl_i2c1_current_src_en_out: i2c1_current_src_en_out { +- function = "i2c1_current_src_en_out"; +- groups = "i2c1_current_src_en_out_4_grp"; +- }; +- +- pinctrl_i2c2_current_src_en_out: i2c2_current_src_en_out { +- function = "i2c2_current_src_en_out"; +- groups = "i2c2_current_src_en_out_3_grp"; +- }; +- +- pinctrl_sdio0_gp_in: sdio0_gp_in { +- function = "sdio0_gp_in"; +- groups = "sdio0_gp_in_grp"; +- }; +- +- pinctrl_sdio1_gp_in: sdio1_gp_in { +- function = "sdio1_gp_in"; +- groups = "sdio1_gp_in_grp"; +- }; +- +- pinctrl_sdio0_CD_in: sdio0_CD_in { +- function = "sdio0_CD_in"; +- groups = "sdio0_CD_in_grp"; +- }; +- +- pinctrl_sdio1_CD_in: sdio1_CD_in { +- function = "sdio1_CD_in"; +- groups = "sdio1_CD_in_grp"; +- }; +- +- pinctrl_uart0_cts_rts: uart0_cts_rts { +- function = "uart0_cts_rts"; +- groups = "uart0_cts_rts_1_grp"; +- }; +-}; +- +-&gpio0 { +- gpio-ranges = <&pinctrl 0 0 16>; +- +- gpio-line-names = +- "cam0_reset_n", +- "cam1_reset_n", +- "DSI_RST", +- "CAM_TRIG", +- "PCIe_ref_clk_en", +- "gpio_in_out_5", +- "Low_power_in", +- "Low_power_out", +- "Ext_wakeUp", +- "sdio0_gp_in", +- "sdio0_cd_in", +- "usb_overcurrent_n_in", +- "usb_drive_vbus_out", +- "sdio1_gp_in", +- "sdio1_cd_in_n", +- "pcie_mperst_out"; +- +- pin_cam1_reset_n { +- gpio-hog; +- gpios = <1 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "cam1_reset_n"; +- }; +- +- pin_DSI_RST { +- gpio-hog; +- gpios = <2 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "DSI_RST"; +- }; +- +- pin_CAM_TRIG { +- gpio-hog; +- gpios = <3 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "CAM_TRIG"; +- }; +- +- pin_PCIe_ref_clk_en { +- gpio-hog; +- gpios = <4 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "PCIe_ref_clk_en"; +- }; +- +- pin_Low_power_in { +- gpio-hog; +- gpios = <6 GPIO_ACTIVE_HIGH>; +- input; +- line-name = "Low_power_in"; +- }; +- +- pin_Low_power_out { +- gpio-hog; +- gpios = <7 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "Low_power_out"; +- }; +- +- pin_Ext_wakeUp { +- gpio-hog; +- gpios = <8 GPIO_ACTIVE_HIGH>; +- input; +- line-name = "Ext_wakeUp"; +- }; +-}; +- +-&gpio1 { +- gpio-ranges = <&pinctrl 0 16 16>; +- +- gpio-line-names = +- "gpio_in_out_16", +- "WiFi_BT_disable_n", +- "timer_ext_in0", +- "timer_ext_in1", +- "shut_down_out", +- "gpio_in_out_21", +- "i2c2_sda_in_out", +- "i2c2_scl_out", +- "i2c2_current_src_en_out", +- "i2c0_current_src_en_out", +- "i2c1_current_src_en_out", +- "gpio_in_out_27", +- "gpio_in_out_28", +- "DSI_INTR", +- "uart0_cts_pad_in", +- "uart0_rts_pad_out"; +- +- pin_WiFi_BT_disable_n { +- gpio-hog; +- gpios = <1 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "WiFi_BT_disable_n"; +- }; +- +- pin_DSI_INTR { +- gpio-hog; +- gpios = <13 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "DSI_INTR"; +- }; +-}; +- +-&torrent_phy { +- status = "okay"; +-}; +- +-&usb3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-evb-base.dtsi b/scripts/dtc/include-prefixes/arm64/hailo/hailo15-evb-base.dtsi +deleted file mode 100644 +index 0924b9bec04d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-evb-base.dtsi ++++ /dev/null +@@ -1,323 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2023 Hailo Technologies Ltd. All rights reserved. +- */ +- +-#include "hailo15-base.dtsi" +- +-/ { +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0x00000001 0x00000000>; +- }; +-}; +- +-&i2c_0 { +- status = "okay"; +-}; +- +-&i2c_1 { +- status = "okay"; +- ina231_MPP_AVDDH: MPP_AVDDH@41 { +- compatible = "ti,ina231_precise"; +- reg = <0x41>; +- shunt-resistor = <100000>; +- max-current = <100>; +- }; +- ina231_DDR_PHY_1v1: DDR_PHY_1v1@42 { +- compatible = "ti,ina231_precise"; +- reg = <0x42>; +- shunt-resistor = <50000>; +- max-current = <300>; +- }; +- ina231_ALL_PLL: ALL_PLL@43 { +- compatible = "ti,ina231_precise"; +- reg = <0x43>; +- shunt-resistor = <100000>; +- max-current = <100>; +- }; +- ina231_MIPI_AVDDH: MIPI_AVDDH@44 { +- compatible = "ti,ina231_precise"; +- reg = <0x44>; +- shunt-resistor = <100000>; +- max-current = <100>; +- }; +- ina231_USB_AVDD_IO_HV: USB_AVDD_IO_HV@45 { +- compatible = "ti,ina231_precise"; +- reg = <0x45>; +- shunt-resistor = <100000>; +- max-current = <100>; +- }; +- ina231_DDR_1V8: DDR_1V8@46 { +- compatible = "ti,ina231_precise"; +- reg = <0x46>; +- shunt-resistor = <100000>; +- max-current = <300>; +- }; +- ina231_DDR_PHY_0v8: DDR_PHY_0v8@47 { +- compatible = "ti,ina231_precise"; +- reg = <0x47>; +- shunt-resistor = <50000>; +- max-current = <1400>; +- }; +- ina231_5V_PERIPH: 5V_PERIPH@49 { +- compatible = "ti,ina231_precise"; +- reg = <0x49>; +- shunt-resistor = <1000>; +- max-current = <5500>; +- }; +- ina231_SOC_and_DRAM_5V_SRC: SOC_and_DRAM_5V_SRC@4a { +- compatible = "ti,ina231_precise"; +- reg = <0x4a>; +- shunt-resistor = <1000>; +- max-current = <3500>; +- }; +- /* Assembly only on EVB with LPDDR4X +- ina231_DDR_PHY_0v6: DDR_PHY_0v6@4c { +- compatible = "ti,ina231_precise"; +- reg = <0x4c>; +- shunt-resistor = <50000>; +- max-current = <2500>; +- }; +- */ +- ina231_IO_1v8: IO_1v8@4d { +- compatible = "ti,ina231_precise"; +- reg = <0x4d>; +- shunt-resistor = <100000>; +- max-current = <250>; +- }; +- ina231_VDD: VDD@4e { +- compatible = "ti,ina231_precise"; +- reg = <0x4e>; +- shunt-resistor = <1000>; +- max-current = <12000>; +- }; +- ina231_MIPI_MPP_USB_AVDD: MIPI_MPP_USB_AVDD@4f { +- compatible = "ti,ina231_precise"; +- reg = <0x4f>; +- shunt-resistor = <50000>; +- max-current = <600>; +- }; +- +- tmp175_NEAR_TOP_POWER: NEAR_TOP_POWER@2d { +- compatible = "ti,tmp175"; +- reg = <0x2d>; +- }; +- tmp175_NEAR_DDR: NEAR_DDR@2f { +- compatible = "ti,tmp175"; +- reg = <0x2f>; +- }; +- tmp175_NEAR_H15_SOC_0: NEAR_H15_SOC_0@2e { +- compatible = "ti,tmp175"; +- reg = <0x2e>; +- }; +- tmp175_NEAR_H15_SOC_1: NEAR_H15_SOC_1@2c { +- compatible = "ti,tmp175"; +- reg = <0x2c>; +- }; +- codec_tlv320aic3104: tlv320aic3104@18 { +- #sound-dai-cells = <0>; +- compatible = "ti,tlv320aic3104"; +- reg = <0x18>; +- ai3x-source-clk = "bclk"; +- ai3x-micbias-vg = <2>; +- /* Regulators */ +- AVDD-supply = <®ulator_3p3v>; +- IOVDD-supply = <®ulator_1p8v>; +- DRVDD-supply = <®ulator_3p3v>; +- DVDD-supply = <®ulator_1p8v>; +- }; +-}; +- +-&vision_subsys { +- status = "okay"; +-}; +- +-&csi2rx0 { +- status = "okay"; +-}; +- +-&csi2rx1 { +- status = "okay"; +-}; +- +-&hailo_vid_cap { +- status = "okay"; +-}; +- +-&hailo_isp { +- status = "okay"; +-}; +- +-&hailo_pixel_mux { +- status = "okay"; +-}; +- +-&rxwrapper0 { +- status = "okay"; +-}; +- +-&hailo_vc8000e { +- status = "okay"; +-}; +- +-&vc8000e_reserved { +- status = "okay"; +-}; +- +-&xrp { +- status = "okay"; +-}; +- +-&xrp_reserved { +- status = "okay"; +-}; +- +-&sdio0 { +- phy-config { +- card-is-emmc = <0x0>; +- cmd-pad-values = <0x1 0x3 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- dat-pad-values = <0x1 0x3 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- rst-pad-values = <0x1 0x3 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- clk-pad-values = <0x1 0x3 0x0 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- sdclkdl-cnfg = <0x0 0x32>; //extdly_en, cckdl_dc +- drive-strength = <0xC 0xC>; //pad_sp, pad_sn +- }; +-}; +-&sdio1 { +- non-removable; +- phy-config { +- card-is-emmc = <0x1>; +- cmd-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- dat-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- rst-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- clk-pad-values = <0x2 0x2 0x0 0x0>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- sdclkdl-cnfg = <0x0 0x32>; //extdly_en, cckdl_dc +- drive-strength = <0xC 0xC>; //pad_sp, pad_sn +- }; +-}; +- +-ð { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_eth>; +-}; +- +-&pinctrl { +- compatible = "hailo15-cpld,pinctrl"; +- pinctrl_eth: eth { +- pins = "eth_rgmii_tx_clk", +- "eth_rgmii_tx_ctl", +- "eth_rgmii_txd_0", +- "eth_rgmii_txd_1", +- "eth_rgmii_txd_2", +- "eth_rgmii_txd_3"; +- drive-strength = <2>; +- }; +- +- pinctrl_usb_overcurrent_n_in: pinctrl_usb_overcurrent_n_in { +- status = "disabled"; /* relevant to USB overcurrent detection is not supported */ +- function = "usb_overcurrent_in"; +- groups = "usb_overcurrent_in_grp"; +- }; +- +- pinctrl_usb_drive_vbus_out: pinctrl_usb_drive_vbus_out { +- status = "disabled"; +- function = "usb_drive_vbus_out"; +- groups = "usb_drive_vbus_out_2_grp"; +- }; +-}; +- +-&qspi { +- status = "okay"; +- +- spi0_flash0: flash@0 { +- /* values for MT25QU01G */ +- spi-max-frequency = <6250000>; /* 90Mhz in DTR, 166Mhz in STR */ +- cdns,read-delay = <7>; +- cdns,tshsl-ns = <30>; +- cdns,tsd2d-ns = <30>; +- cdns,tchsh-ns = <5>; +- cdns,tslch-ns = <3>; +- }; +-}; +- +-&i2s_cpu_master { +- status = "okay"; +- rx-sample-pace-pattern-repetitions = <2>; +- rx-sample-pace = <64 64 64>; +- rx-sample-cmp-to = "prev-val"; +- tx-sample-offset = <81>; +- tx-sample-pace = <63>; +-}; +- +-&audio_card_master { +- status = "okay"; +- simple-audio-card,bitclock-master = <&cpu_dai_master>; +- simple-audio-card,frame-master = <&cpu_dai_master>; +- +- cpu_dai_master: simple-audio-card,cpu { +- sound-dai = <&i2s_cpu_master>; +- system-clock-frequency = <1562500>; +- system-clock-direction-out; +- }; +- codec_dai_master: simple-audio-card,codec { +- sound-dai = <&codec_tlv320aic3104>; +- system-clock-frequency = <1562500>; +- }; +-}; +- +-&audio_card_slave_tx { +- simple-audio-card,bitclock-master = <&codec_dai_tx>; +- simple-audio-card,frame-master = <&codec_dai_tx>; +- +- cpu_dai_tx: simple-audio-card,cpu { +- sound-dai = <&i2s_cpu_slave_tx>; +- system-clock-frequency = <12288000>; +- }; +- codec_dai_tx: simple-audio-card,codec { +- sound-dai = <&codec_tlv320aic3104>; +- system-clock-frequency = <12288000>; +- }; +-}; +- +-&audio_card_slave_rx { +- simple-audio-card,bitclock-master = <&codec_dai_rx>; +- simple-audio-card,frame-master = <&codec_dai_rx>; +- +- cpu_dai_rx: simple-audio-card,cpu { +- sound-dai = <&i2s_cpu_slave_rx>; +- system-clock-frequency = <12288000>; +- }; +- codec_dai_rx: simple-audio-card,codec { +- sound-dai = <&codec_tlv320aic3104>; +- system-clock-frequency = <12288000>; +- }; +-}; +- +-&torrent_phy { +- torrent_phy_pcie: phy@0 { +- reg = <0>; +- resets = <&scmi_reset HAILO15_SCMI_RESET_IDX_PCIE_PHY_LANE_0>, <&scmi_reset HAILO15_SCMI_RESET_IDX_PCIE_PHY_LANE_1>; +- #phy-cells = <0>; +- cdns,phy-type = ; +- cdns,num-lanes = <2>; +- }; +- torrent_phy_usb3: phy@3 { +- reg = <3>; +- resets = <&scmi_reset HAILO15_SCMI_RESET_IDX_PCIE_PHY_LANE_3>; +- #phy-cells = <0>; +- cdns,phy-type = ; +- cdns,num-lanes = <1>; +- cdns,ssc-mode = ; +- }; +-}; +- +-&usb3 { +- dr_mode = "host"; +- phys = <&torrent_phy_usb3>; +- phy-names = "cdns3,usb3-phy"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_overcurrent_n_in>, <&pinctrl_usb_drive_vbus_out>; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-evb-security-camera.dts b/scripts/dtc/include-prefixes/arm64/hailo/hailo15-evb-security-camera.dts +deleted file mode 100644 +index ee52c73aad10..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-evb-security-camera.dts ++++ /dev/null +@@ -1,208 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2023 Hailo Technologies Ltd. All rights reserved. +- */ +- +-/dts-v1/; +-#include "hailo15-evb-base.dtsi" +-#include +- +-/ { +- sensor_clk: sensor_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- }; +-}; +- +- +-&csi2rx0 { +- ports { +- port@0 { +- csi2rx_in_sensor: endpoint { +- remote-endpoint = <&sensor_out_csi2rx>; +- }; +- }; +- }; +-}; +- +-&i2c_0 { +- sensor_0: camera-sensor@1a { +- status = "okay"; +- compatible = "sony,imx334", "sony,imx678"; +- reg = <0x1a>; +- clocks = <&sensor_clk>; +- clock-names = "inclk"; +- clock-frequency = <24000000>; +- csi-id = <0>; +- reset-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; +- port { +- sensor_out_csi2rx: endpoint { +- data-lanes = <1 2 3 4>; +- remote-endpoint = <&csi2rx_in_sensor>; +- link-frequencies = /bits/ 64 <891000000 1440000000 1782000000>; +- }; +- }; +- }; +-}; +- +-&i2c_1 { +- gyro_lsm6dsr_1: lsm6dsr_1@6b { +- compatible = "st,lsm6dsr"; +- reg = <0x6b>; +- vdd-supply = <®ulator_3p3v>; +- vddio-supply = <®ulator_3p3v>; +- interrupt-parent = <&gpio1>; +- interrupts = <14 IRQ_TYPE_EDGE_RISING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio30>; +- }; +- +- lcd@45 { +- status = "disabled"; +- compatible = "raspberrypi,7inch-touchscreen-panel"; +- reg = <0x45>; +- port { +- panel_in: endpoint { +- remote-endpoint = <&dsi0_out>; +- }; +- }; +- }; +-}; +- +-&dsi0 { +- tvg-mode-enable; +- ports { +- port@0 { +- reg = <0>; +- dsi0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&sdio0 { +- broken-cd; +-}; +- +-&sdio0_reserved { +- status = "okay"; +-}; +- +-&hailo_pci_ep_driver { +- status = "okay"; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&serial2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +-}; +- +-&serial3 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +-}; +- +-&i2c_2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +-}; +- +-&pwm { +- status = "okay"; +- hailo15_pwm,supported-channels = <2 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +-}; +- +-&pinctrl { +- i2c-bus = <&i2c_1>; +- board-config = ; +- +- pinctrl_i2c2: i2c2 { +- function = "i2c2"; +- groups = "i2c2_0_grp"; +- }; +- +- pinctrl_uart2: serial2 { +- function = "uart2"; +- groups = "uart2_3_grp"; +- }; +- +- pinctrl_uart3: serial3 { +- function = "uart3"; +- groups = "uart3_3_grp"; +- }; +- +- pinctrl_pwm1: pwm1 { +- function = "pwm1"; +- groups = "pwm1_grp"; +- }; +- +- pinctrl_gpio30: gpio30 { +- function = "gpio"; +- groups = "gpio30_grp"; +- }; +-}; +- +-&gpio0 { +- gpio-ranges = <&pinctrl 0 0 16>; +- +- gpio-line-names = +- "gpio_in_out_0", +- "gpio_in_out_1", +- "pwm_2", +- "pwm_3", +- "cam0_reset_n", +- "gpio_in_out_5", +- "i2c2_sda_in_out", +- "i2c2_scl_out", +- "uart2_rxd_pad_in", +- "uart2_txd_pad_out", +- "uart0_cts_pad_in", +- "uart0_rts_pad_out", +- "uart3_rxd_pad_in", +- "uart3_txd_pad_out", +- "gpio_in_out_14", +- "pcie_mperst_out"; +-}; +- +-&qspi { +- test_device@1 { +- compatible = "hailo,hailo-spi-slave-test"; +- spi-max-frequency = <100000>; +- reg = <1>; +- hailo,non-flash-device; +- spi-lsb-first; +- }; +-}; +- +-&gpio1 { +- gpio-ranges = <&pinctrl 0 16 16>; +- +- gpio-line-names = +- "gpio_in_out_16", +- "gpio_in_out_17", +- "gpio_in_out_18", +- "gpio_in_out_19", +- "shut_down_out", +- "gpio_in_out_21", +- "gpio_in_out_22", +- "gpio_in_out_23", +- "gpio_in_out_24", +- "gpio_in_out_25", +- "gpio_in_out_26", +- "gpio_in_out_27", +- "gpio_in_out_28", +- "gpio_in_out_29", +- "gpio_in_out_30", +- "gpio_in_out_31"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-family-base.dtsi b/scripts/dtc/include-prefixes/arm64/hailo/hailo15-family-base.dtsi +deleted file mode 100644 +index 548d89d5c41b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-family-base.dtsi ++++ /dev/null +@@ -1,1081 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2023 Hailo Technologies Ltd. All rights reserved. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/* Fist 2MB are reserve memory for the platform (currently only TrustedFirmware-A) */ +-/memreserve/ 0x80000000 0x200000; +- +-/ { +- model = "Hailo - Hailo15"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu_0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53", "arm,armv8"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- }; +- +- cpu_1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53", "arm,armv8"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- }; +- +- cpu_2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53", "arm,armv8"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- }; +- +- cpu_3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53", "arm,armv8"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- }; +- +- A53_L2: l2-cache { +- compatible = "cache"; +- cache-size = <0x100000>; +- cache-line-size = <64>; +- cache-sets = <1024>; +- }; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- gic: interrupt-controller@60600000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- interrupt-controller; +- reg = <0x0 0x60600000 0x0 0x10000>, // GICD +- <0x0 0x60680000 0x0 0x80000>, // GICR +- <0x7 0x00000000 0x0 0x40000>; // GICC +- interrupts = ; +- +- msi-controller@60620000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0 0x60620000 0 0x10000>; +- }; +- }; +- +- edac@7c060000 { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "hailo15,cdns-mc-edac"; +- reg-names = "ddr-ctrl"; +- reg = <0x0 0x7c060000 0x0 0x00002000>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- +- interrupts = , +- , +- , +- ; +- interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; +- }; +- +- gpio0: gpio@78200000 { +- compatible = "arm,cmsdk-gpio"; +- reg = <0 0x78200000 0 0x1000>, +- <0 0x7c2a10f0 0 0xC>; +- gpio-controller; +- #gpio-cells = <2>; +- cmsdk_gpio,ngpio = <16>; +- cmsdk_gpio,gpio-offset = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- +- gpio1: gpio@78201000 { +- compatible = "arm,cmsdk-gpio"; +- reg = <0 0x78201000 0 0x1000>, +- <0 0x7c2a10f0 0 0xC>; +- gpio-controller; +- #gpio-cells = <2>; +- cmsdk_gpio,ngpio = <16>; +- cmsdk_gpio,gpio-offset = <16>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- +- pwm: pwm@112000 { +- status = "disabled"; +- compatible = "hailo15,pwm"; +- reg = <0 0x112000 0 0x2000>; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_HCLK>; +- clock-names = "hclk"; +- #pwm-cells = <2>; +- }; +- +- sram@d0000 { +- compatible = "mmio-sram"; +- reg = <0 0x60000000 0 0x4000>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x0 0x0 0x60000000 0x0 0x4000>; +- +- cpu_scp_tx: scp-shmem@0 { +- compatible = "arm,scmi-shmem"; +- reg = <0 0 0 0x1000>; +- }; +- cpu_scp_rx: scp-shmem@1000 { +- compatible = "arm,scmi-shmem"; +- reg = <0 0x1000 0 0xa0>; +- }; +- cpu_nnm_ctrl_tx: scp-shmem@2000 { +- compatible = "arm,scmi-shmem"; +- reg = <0 0x2000 0 0x640>; +- }; +- cpu_nnm_ctrl_rx: scp-shmem@2640 { +- compatible = "arm,scmi-shmem"; +- reg = <0 0x2640 0 0x640>; +- }; +- cpu_nnm_evnt_rx: scp-shmem@2c80 { +- compatible = "arm"; +- reg = <0 0x2c80 0 0x640>; +- }; +- }; +- +- pl320_mailbox: mailbox { +- #mbox-cells = <4>; +- compatible = "arm,pl320-mailbox"; +- interrupts = ; +- +- arm,dev-ch-idx = <0>; +- }; +- +- torrent_phy: torrent-phy@240000 { +- compatible = "cdns,torrent-phy"; +- reg = <0x0 0x240000 0x0 0x40000>; +- reg-names = "torrent_phy"; +- resets = <&scmi_reset HAILO15_SCMI_RESET_IDX_PCIE_PHY>; +- reset-names = "torrent_reset"; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_PCIE_REFCLK>; +- clock-names = "refclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- usb3: usb3@280000 { +- compatible = "cdns,usb3"; +- #address-cells = <2>; +- #size-cells = <2>; +- reg = <0x00 0x280000 0x00 0x4000>, +- <0x00 0x288000 0x00 0x4000>, +- <0x00 0x284000 0x00 0x4000>; +- reg-names = "otg", "xhci", "dev"; +- interrupts = , +- , +- ; +- interrupt-names = "host", "peripheral", "otg"; +- maximum-speed = "super-speed-plus"; +- status = "disabled"; +- }; +- +- serial0: uart0@108000 { +- status = "disabled"; +- compatible = "snps,dw-apb-uart"; +- reg = <0 0x00108000 0 0x1000>; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_HCLK>; +- clock-names = "hclk"; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <1>; +- }; +- +- serial1: uart1@109000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0 0x00109000 0 0x1000>; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_HCLK>; +- clock-names = "hclk"; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <1>; +- }; +- +- +- serial2: uart2@10a000 { +- status = "disabled"; +- compatible = "snps,dw-apb-uart"; +- reg = <0 0x0010a000 0 0x1000>; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_HCLK>; +- clock-names = "hclk"; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <1>; +- }; +- +- serial3: uart3@10b000 { +- status = "disabled"; +- compatible = "snps,dw-apb-uart"; +- reg = <0 0x0010b000 0 0x1000>; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_HCLK>; +- clock-names = "hclk"; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <1>; +- }; +- +- i2c_0: i2c@104000 { +- status = "disabled"; +- compatible = "snps,designware-i2c"; +- reg = <0 0x104000 0 0x1000>; +- interrupts = ; +- clock-frequency = <100000>; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_HCLK>; +- clock-names = "hclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c_1: i2c@105000 { +- status = "disabled"; +- compatible = "snps,designware-i2c"; +- reg = <0 0x105000 0 0x1000>; +- interrupts = ; +- clock-frequency = <100000>; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_HCLK>; +- clock-names = "hclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c_2: i2c@106000 { +- status = "disabled"; +- compatible = "snps,designware-i2c"; +- reg = <0 0x106000 0 0x1000>; +- interrupts = ; +- clock-frequency = <100000>; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_HCLK>; +- clock-names = "hclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c_3: i2c@107000 { +- status = "disabled"; +- compatible = "snps,designware-i2c"; +- reg = <0 0x107000 0 0x1000>; +- interrupts = ; +- clock-frequency = <100000>; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_HCLK>; +- clock-names = "hclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- vision_subsys: vision_subsys { +- power-domains = <&scmi_devpd HAILO15_SCMI_POWER_DOMAIN_IDX_VISION_SUBSYS>; +- compatible = "simple-pm-bus"; +- status = "disabled"; +- ranges; +- +- csi2rx0: csi-bridge@7c011000{ +- status = "disabled"; +- compatible = "cdns,csi2rx"; +- id = <0>; +- reg = <0x0 0x7c011000 0x0 0x1000>; +- ranges; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_RX0_CLK>, <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_RX0_PCLK>, +- <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_RX0_CLK>, <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_RX0_CLK>, +- <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_RX0_CLK>, <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_RX0_CLK>; +- clock-names = "sys_clk", "p_clk", +- "pixel_if0_clk", "pixel_if1_clk", +- "pixel_if2_clk", "pixel_if3_clk"; +- interrupts = ; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- csi2rx_in_sensor: endpoint { +- clock-lanes = <0>; +- data-lanes = <1 2 3 4>; +- }; +- }; +- port@1 { +- reg = <1>; +- +- csi2rx_out_mux: endpoint { +- remote-endpoint = <&mux_in_csi2rx>; +- data-lanes = <1 2 3 4>; +- }; +- }; +- }; +- +- dphyrx0: dphy@0x7c013000L{ +- reg = <0x0 0x7c013000L 0x0 0x1000>; +- }; +- }; +- +- csi2rx1: csi-bridge@7c015000 { +- /* Unsupported in current FPGA*/ +- status = "disabled"; +- compatible = "cdns,csi2rx"; +- id = <1>; +- reg = <0x0 0x7c015000 0x0 0x1000>; +- ranges; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_RX1_CLK>, <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_RX1_PCLK>, +- <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_RX1_CLK>, <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_RX1_CLK>, +- <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_RX1_CLK>, <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_RX1_CLK>; +- clock-names = "sys_clk", "p_clk", +- "pixel_if0_clk", "pixel_if1_clk", +- "pixel_if2_clk", "pixel_if3_clk"; +- interrupts = ; +- +- dphyrx1: dphy@0x7c017000L{ +- reg = <0x0 0x7c017000L 0x0 0x1000>; +- }; +- }; +- +- dpi0: dpi@1a98000 { +- status = "disabled"; +- compatible = "hailo,dsi"; +- reg = <0x0 0x7c019000 0x0 0x1000>; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_TX0_CLK>, <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_TX0_PCLK>; +- clock-names = "dsi_sys_clk", "dsi_p_clk"; +- ports { +- port@0 { +- reg = <0>; +- xxx_dpi_output: endpoint { +- remote-endpoint = <&dsi0_dpi_input>; +- }; +- }; +- }; +- }; +- +- dsi0: dsi@7c018000 { +- status = "disabled"; +- compatible = "cdns,dsi"; +- reg = <0x0 0x7c018000 0x0 0x1000>; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_TX0_CLK>, <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_TX0_PCLK>; +- clock-names = "dsi_sys_clk", "dsi_p_clk"; +- interrupts = ; +- phys = <&dphy0>; +- phy-names = "dphy"; +- #address-cells = <1>; +- #size-cells = <0>; +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@1 { +- reg = <1>; +- dsi0_dpi_input: endpoint { +- remote-endpoint = <&xxx_dpi_output>; +- }; +- }; +- }; +- }; +- +- dphy0: dphy@0x7c01a000L{ +- status = "disabled"; +- reg = <0x0 0x7c01a000L 0x0 0x1000>; +- compatible = "cdns,dphy"; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_TX0_XTAL_CLK>, <&scmi_clk HAILO15_SCMI_CLOCK_IDX_MIPI_REF_CLK>, +- <&scmi_clk HAILO15_SCMI_CLOCK_IDX_MIPI_ESC_CLK>; +- clock-names = "psm", "pll_ref", "esc_clk"; +- #phy-cells = <0>; +- }; +- +- hailo_vid_cap: video { +- status = "disabled"; +- compatible = "hailo,vid-cap"; +- +- ports { +- port@0{ +- reg = <0>; +- vid0_in: vid0_in { +- reg = <0>; +- sink = <1>; +- path = <0>; +- remote-endpoint = <&isp_out_vid0>; +- }; +- }; +- port@1{ +- reg = <1>; +- vid1_in: vid1_in { +- reg = <1>; +- sink = <1>; +- path = <1>; +- remote-endpoint = <&isp_out_vid1>; +- }; +- }; +- +- port@2{ +- reg = <2>; +- vid2_in: vid2_in { +- reg = <2>; +- sink = <1>; +- path = <2>; +- remote-endpoint = <&rxwrapper_out_vid2>; +- }; +- }; +- }; +- }; +- +- hailo_vid_out: video_out { +- status = "ok"; +- compatible = "hailo,vid-out"; +- ports { +- port@0{ +- reg = <0>; +- vid_out_0_out: vid_out_0_out { +- reg = <0>; +- sink = <1>; +- path = <3>; +- remote-endpoint = <&isp_in_vid_out0>; +- }; +- }; +- }; +- }; +- +- hailo_isp: isp@7C000000 { +- status = "disabled"; +- compatible = "hailo,isp"; +- id = <0>; +- reg = <0 0x7C000000 0 0x10000>, <0 0x7c01e000 0 0x1000>; +- interrupts = ; +- ranges; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_ISP_WRAPPER_CLK>, <&scmi_clk HAILO15_SCMI_CLOCK_IDX_ISP_WRAPPER_PCLK>; +- clock-names = "ip_clk", "p_clk"; +- ports { +- port@0 { +- reg = <0>; +- isp_in_rxwrapper: isp_in_rxwrapper { +- sink = <1>; +- remote-endpoint = <&rxwrapper_out_isp>; +- }; +- }; +- port@2 { +- reg = <2>; +- isp_out_vid0: isp_out_vid0 { +- sink = <0>; +- remote-endpoint = <&vid0_in>; +- }; +- }; +- port@4 { +- reg = <4>; +- isp_out_vid1: isp_out_vid1{ +- sink = <0>; +- remote-endpoint = <&vid1_in>; +- }; +- }; +- port@5 { +- reg = <5>; +- isp_in_vid_out0: isp_in_vid_out0 { +- sink = <0>; +- remote-endpoint = <&vid_out_0_out>; +- }; +- }; +- }; +- }; +- +- hailo_pixel_mux: hailo_pixel_mux@7C01C000 { +- status = "disabled"; +- compatible = "hailo,hailo15-pixel-mux"; +- reg = <0 0x7C01C000 0 2000>; +- ranges; +- // vision hclk + vision clk - necessary for accessing pixel mux registers +- // csi_rx0_xtal_clk + csi_rx1_xtal_clk - if someone should open this it should be the cdns csi driver, but it doesn't so it is here. +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_VISION_CLK>, <&scmi_clk HAILO15_SCMI_CLOCK_IDX_VISION_HCLK>, +- <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_RX0_XTAL_CLK>, <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_RX1_XTAL_CLK>; +- clock-names = "vision_clk", "vision_hclk", "csi_rx0_xtal_clk", "csi_rx1_xtal_clk"; +- +- ports { +- port@0 { +- reg = <0>; +- mux_in_csi2rx: endpoint { +- data-lanes = <1 2 3 4>; +- remote-endpoint = <&csi2rx_out_mux>; +- }; +- }; +- port@2 { +- reg = <2>; +- mux_out_rxwrapper: endpoint { +- data-lanes = <1 2 3 4>; +- remote-endpoint = <&rxwrapper_in_mux>; +- }; +- }; +- }; +- }; +- +- rxwrapper0: rxwrapper0@7c010000 { +- status = "disabled"; +- compatible = "hailo,hailo15-rxwrapper"; +- reg = <0 0x7C010000 0 0x1000>; +- interrupts = <0 HW_INTERRUPTS__VISION_BUFFER_READY_AP_INT_IRQ 4>, <0 HW_INTERRUPTS__VISION_SUBSYS_ERR_INT_IRQ 4>; +- ranges; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_RX0_CLK>, <&scmi_clk HAILO15_SCMI_CLOCK_IDX_CSI_RX0_PCLK>; +- clock-names = "rxwrapper0_data_clk", "rxwrapper0_p_clk"; +- ports { +- port@0 { +- reg = <0>; +- rxwrapper_in_mux: rxwrapper_in_mux { +- data-lanes = <1 2 3 4>; +- remote-endpoint = <&mux_out_rxwrapper>; +- }; +- }; +- port@1 { +- reg = <1>; +- rxwrapper_out_vid2: rxwrapper_out_vid1 { +- sink = <0>; +- data-lanes = <1 2 3 4>; +- remote-endpoint = <&vid2_in>; +- }; +- }; +- port@2 { +- reg = <2>; +- rxwrapper_out_isp: rxwrapper_out_isp { +- sink = <0>; +- data-lanes = <1 2 3 4>; +- remote-endpoint = <&isp_in_rxwrapper>; +- }; +- }; +- }; +- }; +- +- rxwrapper1: rxwrapper1@7c014000 { +- status = "disabled"; +- compatible = "hailo,hailo15-rxwrapper"; +- reg = <0 0x7C014000 0 0x1000>; +- }; +- }; +- +- hailo_vc8000e: vc8000e@0x7C030000 { +- status = "disabled"; +- compatible = "vivante,vc8000e"; +- reg = <0 0x7C030000 0 0x10000>; +- memory-region = <&vc8000e_reserved>; +- interrupts = ; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_H265_HCLK>, <&scmi_clk HAILO15_SCMI_CLOCK_IDX_H265_CLK>; +- clock-names = "hclk", "clk"; +- }; +- +- reserved_memory: reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- // Allocate 64MiB to SDIO0 bounce buffer in the DMA window range of SDIO0 +- sdio0_reserved: buffer@0 { +- status = "disabled"; +- compatible = "restricted-dma-pool"; +- reg = <0 0xec000000 0 0x4000000>; +- }; +- +- // Allocate 2MB for DSP Firmware code +- xrp_reserved: xrp@0 { +- status = "disabled"; +- reg = <0 0xebe00000 0 0x200000>; +- }; +- +- // Allocate 128MB to vc8000e buffer in the DMA +- vc8000e_reserved: vc8000e_buffer@0 { +- status = "disabled"; +- no-map; +- alignment = <0x0 0x4000>; +- size = <0x0 0x8000000>; +- alloc-ranges = <0 0xD0000000 0 0x30000000>; +- }; +- +- /* set Linux,CMA area to 992MiB */ +- cma: linux,cma { +- compatible = "shared-dma-pool"; +- reusable; +- size = <0x0 0x3E000000>; +- linux,cma-default; +- /* TODO: allocating outside of the low 32-bit causes hailort driver allocations to be very slow. */ +- /* TODO: DSP must not cross 1GiB boundary. this is a quick workaround */ +- alloc-ranges = <0 0x80000000 0 0x40000000>; +- }; +- +- /* set Hailo,CMA area to 256MiB, must be at 0xCXXXXXXX for main2fast LUT to work +- (accessing 0x3XXXXXXX->0xCXXXXXXX in the NNM firmware) */ +- hailo_cma: hailo,cma { +- status = "disabled"; +- compatible = "shared-dma-pool"; +- reusable; +- size = <0x0 0x10000000>; +- linux,cma-hailo; +- alloc-ranges = <0 0xC0000000 0 0x10000000>; +- }; +- }; +- +- main-bus { +- compatible = "simple-bus"; +- ranges; +- #address-cells = <2>; +- #size-cells = <2>; +- // From main-bus prespective the 256MiB range from bus-address 0x40000000 to 0x50000000, +- // is mapped to physical address 0x90000000-0xa0000000 +- dma-ranges = <0 0x40000000 0 0xE0000000 0 0x10000000>; +- +- watchdog@7c2c1000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0 0x7c2c1000 0 0x1000>; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_HCLK>, <&scmi_clk HAILO15_SCMI_CLOCK_IDX_HCLK>; +- clock-names = "wdog_clk", "apb_pclk"; +- timeout-sec = <10>; +- }; +- +- sdio0: sdio0@78000000 { +- status = "disabled"; +- compatible = "hailo,dwcmshc-sdhci-0"; +- reg = <0 0x78000000 0 0x1000>; +- interrupts = ; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_HCLK>, <&scmi_clk HAILO15_SCMI_CLOCK_IDX_SDIO_0_M_HCLK>, +- <&scmi_clk HAILO15_SCMI_CLOCK_IDX_SDIO_0_CLK_DIV_BYPASS>; +- clock-names = "core", "bus", "clk_div_bypass"; +- sdhci-caps= <0 0x01000000>; // Force VOLT33 capability +- cap-mmc-hw-reset; +- disable-wp; +- memory-region = <&sdio0_reserved>; +- resets = <&scmi_reset HAILO15_SCMI_RESET_IDX_SDIO_0_CD_FROM_PINMUX>; +- reset-names = "sdio-cd-input"; +- bus-width = <4>; +- }; +- +- ddrpmu: ddrpmu@dc000 { +- compatible = "hailo,ddr-pmu"; +- reg = <0 0x000dc000 0 0x2000>; +- reg-names = "ddr_pmu_samples"; +- }; +- +- }; +- sdio1: sdio1@78001000 { +- status = "disabled"; +- compatible = "hailo,dwcmshc-sdhci-1"; +- reg = <0 0x78001000 0 0x1000>; +- interrupts = ; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_HCLK>, <&scmi_clk HAILO15_SCMI_CLOCK_IDX_SDIO_1_M_HCLK>, +- <&scmi_clk HAILO15_SCMI_CLOCK_IDX_SDIO_1_CLK_DIV_BYPASS>; +- clock-names = "core", "bus", "clk_div_bypass"; +- cap-mmc-hw-reset; +- disable-wp; +- resets = <&scmi_reset HAILO15_SCMI_RESET_IDX_SDIO1_8BIT_MUX>, <&scmi_reset HAILO15_SCMI_RESET_IDX_SDIO_1_CD_FROM_PINMUX>; +- reset-names = "sdio1-8bit-mux", "sdio-cd-input"; +- }; +- +- thermal-zones { +- pvt_ts_0: pvt-ts-0 { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&scmi_temp_sensor HAILO15_SCMI_SENSOR_IDX_PVT_TEMPERATURE_SENSOR_0>; +- trips { +- pvt_ts_0_alert_light: trip-point-ts-0-light { +- temperature = <105000>; +- hysteresis = <3000>; +- type = "passive"; +- }; +- pvt_ts_0_alert_medium: trip-point-ts-0-medium { +- temperature = <110000>; +- hysteresis = <3000>; +- type = "passive"; +- }; +- pvt_ts_0_alert_heavy: trip-point-ts-0-heavy { +- temperature = <115000>; +- hysteresis = <3000>; +- type = "passive"; +- }; +- pvt_ts_0_alert_critical: trip-point-ts-0-critical { +- temperature = <120000>; +- hysteresis = <4000>; +- type = "critical"; +- }; +- }; +- }; +- pvt_ts_1: pvt-ts-1 { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&scmi_temp_sensor HAILO15_SCMI_SENSOR_IDX_PVT_TEMPERATURE_SENSOR_1>; +- trips { +- pvt_ts_1_alert_light: trip-point-ts-0-light { +- temperature = <105000>; +- hysteresis = <3000>; +- type = "passive"; +- }; +- pvt_ts_1_alert_medium: trip-point-ts-0-medium { +- temperature = <110000>; +- hysteresis = <3000>; +- type = "passive"; +- }; +- pvt_ts_1_alert_heavy: trip-point-ts-0-heavy { +- temperature = <115000>; +- hysteresis = <3000>; +- type = "passive"; +- }; +- pvt_ts_1_alert_critical: trip-point-ts-0-critical { +- temperature = <120000>; +- hysteresis = <4000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- firmware { +- scmi { +- compatible = "arm,scmi"; +- mboxes = <&pl320_mailbox 6 1 0 PL320_MBOX_TXDONE_BY_ACK>, <&pl320_mailbox 6 9 8 PL320_MBOX_TXDONE_BY_ACK>; +- mbox-names = "tx", "rx"; +- shmem = <&cpu_scp_tx>, <&cpu_scp_rx>; +- #address-cells = <1>; +- #size-cells = <0>; +- fw-ver = ; +- +- scmi_devpd: protocol@11 { +- reg = <0x11>; +- #power-domain-cells = <1>; +- }; +- scmi_clk: protocol@14 { +- reg = <0x14>; +- #clock-cells = <1>; +- }; +- scmi_temp_sensor: protocol@15 { +- reg = <0x15>; +- #thermal-sensor-cells = <1>; +- }; +- scmi_reset: protocol@16 { +- reg = <0x16>; +- #reset-cells = <1>; +- }; +- scmi_hailo: protocol@81 { +- reg = <0x81>; +- #hailo-cells = <1>; +- }; +- }; +- }; +- +- scu_log { +- compatible = "hailo,scu-log"; +- reg = <0 0xDF000 0 0x1000>; +- }; +- +- hailort_driver { +- compatible = "hailo,hailort"; +- resets = <&scmi_reset HAILO15_SCMI_RESET_IDX_CORE_CPU>, +- <&scmi_reset HAILO15_SCMI_RESET_IDX_NN_CORE>; +- reset-names = "core-cpu", "nn-core"; +- mboxes = <&pl320_mailbox 7 3 2 PL320_MBOX_TXDONE_BY_IRQ>, +- <&pl320_mailbox 7 7 6 PL320_MBOX_TXDONE_BY_IRQ>, +- <&pl320_mailbox 7 11 10 PL320_MBOX_TXDONE_BY_IRQ>; +- mboxes-names = "nnc-control", "nnc-d2h-events", "nnc-driver-down-event"; +- shmem = <&cpu_nnm_ctrl_tx &cpu_nnm_ctrl_rx>, <&cpu_nnm_evnt_rx>; +- shmem-names = "control-tx", "control-rx", "event-rx"; +- +- reg = <0 0x5c000 0 0x14000>, <0 0x80000 0 0x240>, <0 0x80240 0 0x2ddc0>, <0 0x000af000 0 0x1000>; +- reg-names = "core-fw-code", "core-fw-isr-vector", "core-fw-data", "core-fw-log"; +- +- ranges; +- #address-cells = <1>; +- #size-cells = <1>; +- +- vdma0: vdma@0 { +- reg = <0x7c050000 0x800>, <0x7c052000 0x2000>; +- reg-names = "channel-regs", "engine-regs"; +- interrupts = ; +- }; +- +- vdma1: vdma@1 { +- reg = <0x7c054000 0x800>, <0x7c056000 0x2000>; +- reg-names = "channel-regs", "engine-regs"; +- interrupts = ; +- }; +- +- vdma2: vdma@2 { +- reg = <0x7c058000 0x800>, <0x7c05A000 0x2000>; +- reg-names = "channel-regs", "engine-regs"; +- interrupts = ; +- }; +- }; +- +- hailo_pci_ep_driver: hailo_pci_ep_driver { +- compatible = "hailo,hailo_pci_ep"; +- status = "disabled"; +- +- reg = <0 0x00222000 0 0x1e000>, <0 0x00200000 0 0x20000>, <0 0x00220000 0 0x2000>; +- reg-names = "channel-regs", "config-regs", "bridge-regs"; +- interrupts = ; +- }; +- +- gp_vdma: dma@7c05E000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "hailo,hailo15-gp_vdma"; +- reg = <0 0x7c05E000 0 0x200>; +- ranges; +- interrupts = , +- , +- , +- ; +- interrupt-names = "gp_dma_irq_0", "gp_dma_irq_1", "gp_dma_irq_2", "gp_dma_irq_3"; +- dma-channel@0 { +- reg = <0x7c05C000 0x20>; +- }; +- dma-channel@1 { +- reg = <0x7c05C020 0x20>; +- }; +- dma-channel@2 { +- reg = <0x7c05C040 0x20>; +- }; +- dma-channel@3 { +- reg = <0x7c05C060 0x20>; +- }; +- dma-channel@4 { +- reg = <0x7c05C080 0x20>; +- }; +- dma-channel@5 { +- reg = <0x7c05C0A0 0x20>; +- }; +- dma-channel@6 { +- reg = <0x7c05C0C0 0x20>; +- }; +- dma-channel@7 { +- reg = <0x7c05C0E0 0x20>; +- }; +- dma-channel@8 { +- reg = <0x7c05C100 0x20>; +- }; +- dma-channel@9 { +- reg = <0x7c05C120 0x20>; +- }; +- dma-channel@A { +- reg = <0x7c05C140 0x20>; +- }; +- dma-channel@B { +- reg = <0x7c05C160 0x20>; +- }; +- dma-channel@C { +- reg = <0x7c05C180 0x20>; +- }; +- dma-channel@D { +- reg = <0x7c05C1A0 0x20>; +- }; +- dma-channel@E { +- reg = <0x7c05C1C0 0x20>; +- }; +- dma-channel@F { +- reg = <0x7c05C1E0 0x20>; +- }; +- +- }; +- +- xrp: xrp@0 { +- status = "disabled"; +- // DSP has only 32 bit address space. address-cells must be "1" +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cdns,xrp-hailo,cma"; +- memory-region = <&xrp_reserved>, <&cma>; +- memory-region-names = "dsp-fw", "cma"; +- reg = <0 0x7c040000 0 0x4000>; // dsp config +- mboxes = <&pl320_mailbox 5 5 4 PL320_MBOX_TXDONE_BY_IRQ>; +- firmware-name = "dsp-fw.elf"; +- // FW code reserved memory is mapped to 0x80000000 in dsp address space +- ranges = < +- 0 0 0 0x80000000 +- 0x80000000 0 0xe8000000 0x8000000>; +- resets = <&scmi_reset HAILO15_SCMI_RESET_IDX_DSP>; +- reset-names = "dsp-reset"; +- clock-frequency = <700000000>; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_DSP_CONFIG>, +- <&scmi_clk HAILO15_SCMI_CLOCK_IDX_DSP_PLL>, +- <&scmi_clk HAILO15_SCMI_CLOCK_IDX_DSP>; +- clock-names = "dsp-config-clock", "dsp-pll-clock", "dsp-clock"; +- dsp@0 { +- }; +- }; +- +- eth: ethernet@1b5000 { +- status = "disabled"; +- compatible = "hailo,hailo15-gem"; +- reg = <0 0x1b5000 0 0x3000>; +- interrupts = +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_ETHERNET_PCLK>, <&scmi_clk HAILO15_SCMI_CLOCK_IDX_ETHERNET_ACLK>; +- clock-names = "pclk", "hclk"; +- phy-mode = "rgmii-id"; +- }; +- +- +- qspi: qspi@10c000 { +- compatible = "hailo,qspi-nor"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x00000000 0x0010c000 0x00000000 0x1000>, +- <0x00000000 0x70000000 0x00000000 0x08000000>; +- clocks = <&scmi_clk HAILO15_SCMI_CLOCK_IDX_HCLK>; +- +- cdns,fifo-depth = <256>; +- cdns,fifo-width = <4>; +- cdns,trigger-address = <0>; +- num-cs = <4>; +- small-fifo-size = <32>; +- cdns,enable-auto-poll; +- +- interrupts = ; +- +- status = "disabled"; +- +- spi0_flash0: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; /* chip select */ +- }; +- }; +- +- i2s_cpu_slave_rx: audio-controller-rx@10d400 { +- compatible = "snps,designware-i2s"; +- reg = <0x0 0x10d400 0x0 0x400>; +- #sound-dai-cells = <0>; +- interrupts = ; +- interrupt-names = "i2s_playback_irq"; +- status = "disabled"; +- }; +- +- i2s_cpu_slave_tx: audio-controller-tx@10d800 { +- compatible = "snps,designware-i2s"; +- reg = <0x0 0x10d800 0x0 0x400>; +- #sound-dai-cells = <0>; +- interrupts = ; +- interrupt-names = "i2s_recording_irq"; +- status = "disabled"; +- }; +- +- audio_card_master: audio-card-master{ +- compatible = "simple-audio-card"; +- simple-audio-card,name = "Hailo15-Audio-master"; +- simple-audio-card,format = "i2s"; +- status = "disabled"; +- }; +- +- audio_card_slave_rx: audio-card-slave-rx{ +- compatible = "simple-audio-card"; +- simple-audio-card,name = "Hailo15-Audio-slave-rx"; +- simple-audio-card,format = "i2s"; +- status = "disabled"; +- }; +- +- audio_card_slave_tx: audio-card-slave-tx { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "Hailo15-Audio-slave-tx"; +- simple-audio-card,format = "i2s"; +- status = "disabled"; +- }; +- +- regulator_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "regulator_3p3v"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- regulator_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "regulator_1p8v"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = ; +- interrupt-parent = <&gic>; +- }; +- +- chosen { +- stdout-path = &serial1; +- }; +- +- aliases { +- mmc0 = &sdio0; +- mmc1 = &sdio1; +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-ginger-imaging-imx334.dts b/scripts/dtc/include-prefixes/arm64/hailo/hailo15-ginger-imaging-imx334.dts +deleted file mode 100644 +index 5bc1eda7bb8c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-ginger-imaging-imx334.dts ++++ /dev/null +@@ -1,66 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2023 Hailo Technologies Ltd. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "hailo15-ginger-imaging.dtsi" +- +-&sdio1 { +- status = "okay"; +- 8-bit-mux-mode; +-}; +- +-ð { +- status = "okay"; +-}; +- +-&csi2rx0 { +- status = "okay"; +-}; +- +-&i2c_0 { +- status = "okay"; +- imx334: camera-sensor@1a { +- status = "okay"; +- compatible = "sony,imx334"; +- reg = <0x1a>; +- clocks = <&sensor_clk>; +- clock-names = "inclk"; +- clock-frequency = <24000000>; +- csi-id = <0>; +- +- port { +- sensor_out_csi2rx: endpoint { +- data-lanes = <1 2 3 4>; +- remote-endpoint = <&csi2rx_in_sensor>; +- link-frequencies = /bits/ 64 <891000000>; +- }; +- }; +- }; +-}; +- +-&i2c_1 { +- status = "okay"; +-}; +- +-&i2c_2 { +- status = "okay"; +-}; +- +-&i2c_3 { +- status = "okay"; +-}; +- +-&hailo_isp { +- status = "okay"; +-}; +- +-&hailo_pixel_mux { +- status = "okay"; +-}; +- +-&rxwrapper0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-ginger-imaging-ov2775.dts b/scripts/dtc/include-prefixes/arm64/hailo/hailo15-ginger-imaging-ov2775.dts +deleted file mode 100644 +index 1b0f1ec4f5a7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-ginger-imaging-ov2775.dts ++++ /dev/null +@@ -1,65 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2023 Hailo Technologies Ltd. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "hailo15-ginger-imaging.dtsi" +- +-&sdio1 { +- status = "okay"; +- 8-bit-mux-mode; +-}; +- +-ð { +- status = "okay"; +-}; +- +-&csi2rx0 { +- status = "okay"; +-}; +- +-&i2c_0 { +- status = "okay"; +- ov2775: camera-sensor@6c { +- status = "okay"; +- compatible = "ovti,ov2775"; +- reg = <0x6c>; +- clocks = <&sensor_clk>; +- clock-names = "xvclk"; +- clock-frequency = <24000000>; +- csi-id = <0>; +- +- port { +- sensor_out_csi2rx: endpoint { +- data-lanes = <1 2 3 4>; +- remote-endpoint = <&csi2rx_in_sensor>; +- }; +- }; +- }; +-}; +- +-&i2c_1 { +- status = "okay"; +-}; +- +-&i2c_2 { +- status = "okay"; +-}; +- +-&i2c_3 { +- status = "okay"; +-}; +- +-&hailo_isp { +- status = "okay"; +-}; +- +-&hailo_pixel_mux { +- status = "okay"; +-}; +- +-&rxwrapper0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-ginger-imaging.dtsi b/scripts/dtc/include-prefixes/arm64/hailo/hailo15-ginger-imaging.dtsi +deleted file mode 100644 +index c6665fdc9e4b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-ginger-imaging.dtsi ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2023 Hailo Technologies Ltd. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "hailo15-base.dtsi" +- +-/ { +- sensor_clk: sensor_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0x00000000 0x80000000>; +- }; +-}; +- +- +-&csi2rx0 { +- status = "disabled"; +- ports { +- port@0 { +- csi2rx_in_sensor: endpoint { +- remote-endpoint = <&sensor_out_csi2rx>; +- }; +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-ginger-soc-sdio0.dts b/scripts/dtc/include-prefixes/arm64/hailo/hailo15-ginger-soc-sdio0.dts +deleted file mode 100644 +index 8ac916a3f832..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-ginger-soc-sdio0.dts ++++ /dev/null +@@ -1,27 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2023 Hailo Technologies Ltd. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "hailo15-base.dtsi" +- +-/ { +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0x00000000 0x80000000>; +- }; +-}; +- +-ð { +- status = "okay"; +-}; +- +-&sdio0 { +- status = "okay"; +-}; +- +-&sdio0_reserved { +- status = "okay"; +-}; +\ No newline at end of file +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-ginger-soc.dts b/scripts/dtc/include-prefixes/arm64/hailo/hailo15-ginger-soc.dts +deleted file mode 100644 +index 5ab23315a621..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-ginger-soc.dts ++++ /dev/null +@@ -1,24 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2023 Hailo Technologies Ltd. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "hailo15-base.dtsi" +- +-/ { +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0x00000000 0x80000000>; +- }; +-}; +- +-ð { +- status = "okay"; +-}; +- +-&sdio1 { +- status = "okay"; +- 8-bit-mux-mode; +-}; +\ No newline at end of file +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-lavender-dsp.dts b/scripts/dtc/include-prefixes/arm64/hailo/hailo15-lavender-dsp.dts +deleted file mode 100644 +index ff255cda1300..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-lavender-dsp.dts ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2023 Hailo Technologies Ltd. All rights reserved. +- */ +-/dts-v1/; +- +-#include "hailo15-base.dtsi" +- +-/ { +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0x00000000 0x80000000>; +- }; +-}; +- +-ð { +- status = "okay"; +-}; +- +-&sdio1 { +- status = "okay"; +- 8-bit-mux-mode; +-}; +- +-&xrp { +- status = "okay"; +-}; +- +-&xrp_reserved { +- status = "okay"; +-}; +\ No newline at end of file +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-lavender-encoder.dts b/scripts/dtc/include-prefixes/arm64/hailo/hailo15-lavender-encoder.dts +deleted file mode 100644 +index 817f0f3f3f65..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-lavender-encoder.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2023 Hailo Technologies Ltd. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "hailo15-base.dtsi" +- +-ð { +- status = "okay"; +-}; +- +-&sdio1 { +- status = "okay"; +- 8-bit-mux-mode; +-}; +\ No newline at end of file +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-lavender.dts b/scripts/dtc/include-prefixes/arm64/hailo/hailo15-lavender.dts +deleted file mode 100644 +index 817f0f3f3f65..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-lavender.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2023 Hailo Technologies Ltd. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "hailo15-base.dtsi" +- +-ð { +- status = "okay"; +-}; +- +-&sdio1 { +- status = "okay"; +- 8-bit-mux-mode; +-}; +\ No newline at end of file +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-sbc.dts b/scripts/dtc/include-prefixes/arm64/hailo/hailo15-sbc.dts +deleted file mode 100644 +index d92ad7410b7d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-sbc.dts ++++ /dev/null +@@ -1,392 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2023 Hailo Technologies Ltd. All rights reserved. +- */ +- +-/dts-v1/; +-#include "hailo15-base.dtsi" +-#include +- +-/ { +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0x00000001 0x00000000>; +- }; +-}; +- +-&i2c_0 { +- status = "ok"; +- +- sensor_0: camera-sensor@1a { +- status = "ok"; +- compatible = "sony,imx334", "sony,imx675", "sony,imx678"; +- reg = <0x1a>; +- clocks = <&sensor_clk>; +- clock-names = "inclk"; +- clock-frequency = <24000000>; +- csi-id = <0>; +- reset-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; +- port { +- sensor_out_csi2rx: endpoint { +- data-lanes = <1 2 3 4>; +- remote-endpoint = <&csi2rx_in_sensor>; +- link-frequencies = /bits/ 64 <891000000 1440000000 1782000000>; +- }; +- }; +- }; +-}; +- +-&i2c_1 { +- status = "ok"; +- ina231_1v8: 1v8@40 { +- compatible = "ti,ina231_precise"; +- reg = <0x40>; +- shunt-resistor = <100000>; +- max-current = <260>; +- }; +- ina231_DDR_VDDQX: DDR_VDDQX@42 { +- compatible = "ti,ina231_precise"; +- reg = <0x42>; +- shunt-resistor = <100000>; +- max-current = <170>; +- }; +- ina231_0v8: 0v8@43 { +- compatible = "ti,ina231_precise"; +- reg = <0x43>; +- shunt-resistor = <1000>; +- max-current = <11755>; +- }; +- +- tmp175_NEAR_H15_SOC: NEAR_H15_SOC@2c { +- compatible = "ti,tmp175"; +- reg = <0x2c>; +- }; +- +- codec_tlv320aic3104: tlv320aic3104@18 { +- #sound-dai-cells = <0>; +- compatible = "ti,tlv320aic3104"; +- reg = <0x18>; +- ai3x-source-clk = "bclk"; +- ai3x-micbias-vg = <2>; +- /* Regulators */ +- AVDD-supply = <®ulator_3p3v>; +- IOVDD-supply = <®ulator_1p8v>; +- DRVDD-supply = <®ulator_3p3v>; +- DVDD-supply = <®ulator_1p8v>; +- }; +-}; +- +-&csi2rx0 { +- status = "ok"; +- ports { +- port@0 { +- csi2rx_in_sensor: endpoint { +- remote-endpoint = <&sensor_out_csi2rx>; +- }; +- }; +- }; +-}; +- +-&vision_subsys { +- status = "okay"; +-}; +- +-&csi2rx1 { +- status = "ok"; +-}; +- +-&hailo_vid_cap { +- status = "ok"; +-}; +- +-&hailo_isp { +- status = "ok"; +-}; +- +-&hailo_pixel_mux { +- status = "ok"; +-}; +- +-&rxwrapper0 { +- status = "ok"; +-}; +- +-&hailo_vc8000e { +- status = "ok"; +-}; +- +-&vc8000e_reserved { +- status = "ok"; +-}; +- +-&xrp { +- status = "ok"; +-}; +- +-&xrp_reserved { +- status = "ok"; +-}; +- +-&sdio1 { +- status = "ok"; +- broken-cd; +- sdhci-caps= <0 0x01000000>; // Force VOLT33 capability +- phy-config { +- card-is-emmc = <0x0>; +- cmd-pad-values = <0x1 0x3 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- dat-pad-values = <0x1 0x3 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- rst-pad-values = <0x1 0x3 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- clk-pad-values = <0x1 0x3 0x0 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- sdclkdl-cnfg = <0x0 0x32>; //extdly_en, cckdl_dc +- drive-strength = <0xC 0xC>; //pad_sp, pad_sn +- }; +-}; +- +-ð { +- status = "ok"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_eth>; +-}; +- +-&qspi { +- status = "ok"; +- +- spi0_flash0: flash@0 { +- /* values for MT25QU01G */ +- spi-max-frequency = <6250000>; /* 90Mhz in DTR, 166Mhz in STR */ +- cdns,read-delay = <7>; +- cdns,tshsl-ns = <30>; +- cdns,tsd2d-ns = <30>; +- cdns,tchsh-ns = <5>; +- cdns,tslch-ns = <3>; +- }; +-}; +- +-&i2s_cpu_master { +- status = "okay"; +- rx-sample-pace-pattern-repetitions = <2>; +- rx-sample-pace = <64 64 64>; +- rx-sample-cmp-to = "prev-val"; +- tx-sample-offset = <81>; +- tx-sample-pace = <63>; +-}; +- +-&audio_card_master { +- status = "ok"; +- simple-audio-card,bitclock-master = <&cpu_dai_master>; +- simple-audio-card,frame-master = <&cpu_dai_master>; +- +- cpu_dai_master: simple-audio-card,cpu { +- sound-dai = <&i2s_cpu_master>; +- system-clock-frequency = <1562500>; +- system-clock-direction-out; +- }; +- codec_dai_master: simple-audio-card,codec { +- sound-dai = <&codec_tlv320aic3104>; +- system-clock-frequency = <1562500>; +- }; +-}; +- +-&audio_card_slave_tx { +- simple-audio-card,bitclock-master = <&codec_dai_tx>; +- simple-audio-card,frame-master = <&codec_dai_tx>; +- +- cpu_dai_tx: simple-audio-card,cpu { +- sound-dai = <&i2s_cpu_slave_tx>; +- system-clock-frequency = <12288000>; +- }; +- codec_dai_tx: simple-audio-card,codec { +- sound-dai = <&codec_tlv320aic3104>; +- system-clock-frequency = <12288000>; +- }; +-}; +- +-&audio_card_slave_rx { +- simple-audio-card,bitclock-master = <&codec_dai_rx>; +- simple-audio-card,frame-master = <&codec_dai_rx>; +- +- cpu_dai_rx: simple-audio-card,cpu { +- sound-dai = <&i2s_cpu_slave_rx>; +- system-clock-frequency = <12288000>; +- }; +- codec_dai_rx: simple-audio-card,codec { +- sound-dai = <&codec_tlv320aic3104>; +- system-clock-frequency = <12288000>; +- }; +-}; +- +-/ { +- sensor_clk: sensor_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- }; +-}; +- +-&sdio0_reserved { +- status = "ok"; +-}; +- +-&serial0 { +- status = "ok"; +-}; +- +-&i2c_2 { +- status = "ok"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>, <&pinctrl_i2c2_current_src_en_out>; +-}; +- +-&pinctrl { +- +- pinctrl_eth: eth { +- pins = "eth_rgmii_tx_clk", +- "eth_rgmii_tx_ctl", +- "eth_rgmii_txd_0", +- "eth_rgmii_txd_1", +- "eth_rgmii_txd_2", +- "eth_rgmii_txd_3"; +- drive-strength = <2>; +- }; +- +- pinctrl_i2c2: i2c2 { +- function = "i2c2"; +- groups = "i2c2_1_grp"; +- }; +- +- pinctrl_i2c0_current_src_en_out: i2c0_current_src_en_out { +- function = "i2c0_current_src_en_out"; +- groups = "i2c0_current_src_en_out_3_grp"; +- }; +- +- pinctrl_i2c1_current_src_en_out: i2c1_current_src_en_out { +- function = "i2c1_current_src_en_out"; +- groups = "i2c1_current_src_en_out_4_grp"; +- }; +- +- pinctrl_i2c2_current_src_en_out: i2c2_current_src_en_out { +- function = "i2c2_current_src_en_out"; +- groups = "i2c2_current_src_en_out_3_grp"; +- }; +- +- pinctrl_sdio0_gp_in: sdio0_gp_in { +- function = "sdio0_gp_in"; +- groups = "sdio0_gp_in_grp"; +- }; +- +- pinctrl_sdio1_gp_in: sdio1_gp_in { +- function = "sdio1_gp_in"; +- groups = "sdio1_gp_in_grp"; +- }; +- +- pinctrl_sdio0_CD_in: sdio0_CD_in { +- function = "sdio0_CD_in"; +- groups = "sdio0_CD_in_grp"; +- }; +- +- pinctrl_sdio1_CD_in: sdio1_CD_in { +- function = "sdio1_CD_in"; +- groups = "sdio1_CD_in_grp"; +- }; +- +- pinctrl_uart0_cts_rts: uart0_cts_rts { +- function = "uart0_cts_rts"; +- groups = "uart0_cts_rts_1_grp"; +- }; +- +- pinctrl_usb_overcurrent_n_in: pinctrl_usb_overcurrent_n_in { +- function = "usb_overcurrent_in"; +- groups = "usb_overcurrent_in_grp"; +- }; +- +- pinctrl_usb_drive_vbus_out: pinctrl_usb_drive_vbus_out { +- function = "usb_drive_vbus_out"; +- groups = "usb_drive_vbus_out_2_grp"; +- }; +-}; +- +-&gpio0 { +- gpio-ranges = <&pinctrl 0 0 16>; +- +- gpio-line-names = +- "SPI_CS2", +- "SPI_CS2", +- "DSI_RST", +- "CAM_TRIG", +- "cam0_reset_n", +- "cam1_reset_n", +- "gpio_in_out_6", +- "gpio_in_out_7", +- "gpio_in_out_8", +- "sdio0_gp_in", +- "sdio0_cd_in", +- "usb_overcurrent_n_in", +- "usb_drive_vbus_out", +- "sdio1_gp_in", +- "sdio1_cd_in_n", +- "RVSD"; +-}; +- +-&gpio1 { +- gpio-ranges = <&pinctrl 0 16 16>; +- +- gpio-line-names = +- "gpio_in_out_16", +- "WiFi_BT_disable_n", +- "timer_ext_in0", +- "timer_ext_in1", +- "shut_down_out", +- "user_LED", +- "i2c2_sda_in_out", +- "i2c2_scl_out", +- "i2c2_current_src_en_out", +- "i2c0_current_src_en_out", +- "i2c1_current_src_en_out", +- "gpio_in_out_27", +- "gpio_in_out_28", +- "DSI_INTR", +- "uart0_cts_pad_in", +- "uart0_rts_pad_out"; +- +- pin_WiFi_BT_disable_n { +- gpio-hog; +- gpios = <1 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "WiFi_BT_disable_n"; +- }; +- +- pin_DSI_INTR { +- gpio-hog; +- gpios = <13 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "DSI_INTR"; +- }; +-}; +- +-&torrent_phy { +- status = "okay"; +- torrent_phy_pcie: phy@0 { +- reg = <0>; +- resets = <&scmi_reset HAILO15_SCMI_RESET_IDX_PCIE_PHY_LANE_0>, <&scmi_reset HAILO15_SCMI_RESET_IDX_PCIE_PHY_LANE_1>; +- #phy-cells = <0>; +- cdns,phy-type = ; +- cdns,num-lanes = <2>; +- }; +- torrent_phy_usb3: phy@3 { +- reg = <3>; +- resets = <&scmi_reset HAILO15_SCMI_RESET_IDX_PCIE_PHY_LANE_3>; +- #phy-cells = <0>; +- cdns,phy-type = ; +- cdns,num-lanes = <1>; +- cdns,ssc-mode = ; +- }; +-}; +- +-&usb3 { +- status = "okay"; +- dr_mode = "host"; +- phys = <&torrent_phy_usb3>; +- phy-names = "cdns3,usb3-phy"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb_overcurrent_n_in>, <&pinctrl_usb_drive_vbus_out>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-veloce.dts b/scripts/dtc/include-prefixes/arm64/hailo/hailo15-veloce.dts +deleted file mode 100644 +index ccd3b5bd5567..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-veloce.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2024 Hailo Technologies Ltd. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "hailo15-base.dtsi" +- +-/ { +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0x00000000 0x20000000>; +- }; +-}; +- +-ð { +- status = "okay"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-vp.dts b/scripts/dtc/include-prefixes/arm64/hailo/hailo15-vp.dts +deleted file mode 100644 +index 5bcec26f04ef..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo15-vp.dts ++++ /dev/null +@@ -1,72 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2023 Hailo Technologies Ltd. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "hailo15-base.dtsi" +- +-/ { +- ethernet@2,0 { +- compatible = "smsc,lan91c111"; +- reg = <0 0x78401000 0 0x4000>; +- interrupts = <0 15 4>; +- }; +- +- v2m_fixed_3v3: fixed-regulator-0 { +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- mmci@2,4000 { +- vmmc-supply = <&v2m_fixed_3v3>; +- compatible = "arm,pl180", "arm,primecell"; +- reg = <0 0x78405000 0 0x1000>; +- interrupts = <0 17 4 0 18 4>; +- max-frequency = <12000000>; +- clocks = <&soc_clk24mhz>, <&soc_clk24mhz>; +- clock-names = "mclk", "apb_pclk"; +- }; +- +- soc_clk24mhz: clk24mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "v2m:clk24mhz"; +- }; +- +- serial_vp: uart_vp@00109000 { +- compatible = "ns16550"; +- reg = <0 0x00109000 0 0x1000>; +- clocks = <&soc_clk24mhz>; +- interrupts = <0 2 4>; +- reg-shift = <2>; +- reg-io-width = <1>; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0x00000000 0x80000000>; +- }; +- +- chosen { +- stdout-path = &serial_vp; +- }; +-}; +- +-&xrp { +- status = "okay"; +-}; +- +-&xrp_reserved { +- status = "okay"; +-}; +- +-/* disable default uart */ +-&serial1 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo15l-base.dtsi b/scripts/dtc/include-prefixes/arm64/hailo/hailo15l-base.dtsi +deleted file mode 100644 +index 757df5171ab0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo15l-base.dtsi ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2024 Hailo Technologies Ltd. All rights reserved. +- */ +- +-#define HAILO_SOC_TYPE HAILO_SOC_HAILO15L +-#include "hailo15-family-base.dtsi" +- +-/ { +- soc { +- compatible = "hailo,hailo15l"; +- }; +- +- pl320_mailbox: mailbox { +- reg = <0 0x78003000 0 0x1000>; +- }; +- +- pinctrl: pinctrl@7c291000 { +- compatible = "hailo15l,pinctrl"; +- reg = <0 0x7c291000 0 0x1000>, +- <0 0x7c292000 0 0x1000>, +- <0 0x7c293000 0 0x1000>; +- reg-names = "general_pads_config_base", "gpio_pads_config_base", "slow_pads_config_base"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo15l-oregano.dts b/scripts/dtc/include-prefixes/arm64/hailo/hailo15l-oregano.dts +deleted file mode 100644 +index 32090787f766..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo15l-oregano.dts ++++ /dev/null +@@ -1,122 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2024 Hailo Technologies Ltd. All rights reserved. +- */ +- +-/dts-v1/; +-#include "hailo15l-base.dtsi" +- +-/ { +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0x00000000 0x80000000>; +- }; +-}; +- +-&pinctrl { +- pinctrl_eth_tx_clk: eth_tx_clk { +- function = "eth_tx_clk_out"; +- groups = "eth_tx_clk_out_grp"; +- drive-strength = <2>; +- }; +- +- pinctrl_eth_tx_ctl_en: eth_tx_ctl_en { +- function = "eth_tx_ctl_en_out"; +- groups = "eth_tx_ctl_en_out_grp"; +- drive-strength = <2>; +- }; +- +- pinctrl_eth_txd_0: eth_txd_0 { +- function = "eth_txd_0_out"; +- groups = "eth_txd_0_out_grp"; +- drive-strength = <2>; +- }; +- +- pinctrl_eth_txd_1: eth_txd_1 { +- function = "eth_txd_1_out"; +- groups = "eth_txd_1_out_grp"; +- drive-strength = <2>; +- }; +- +- pinctrl_eth_txd_2: eth_txd_2 { +- function = "eth_txd_2_out"; +- groups = "eth_txd_2_out_grp"; +- drive-strength = <2>; +- }; +- +- pinctrl_eth_txd_3: eth_txd_3 { +- function = "eth_txd_3_out"; +- groups = "eth_txd_3_out_grp"; +- drive-strength = <2>; +- }; +- +- pinctrl_uart0_rxd: uart0_rxd { +- function = "uart0_rxd_in"; +- groups = "uart0_rxd_in_0_grp"; +- }; +- +- pinctrl_uart0_txd: uart0_txd { +- function = "uart0_txd_out"; +- groups = "uart0_txd_out_0_grp"; +- }; +- +- pinctrl_uart1_rxd: uart1_rxd { +- function = "uart1_rxd_in"; +- groups = "uart1_rxd_in_0_grp"; +- }; +- +- pinctrl_uart1_txd: uart1_txd { +- function = "uart1_txd_out"; +- groups = "uart1_txd_out_0_grp"; +- }; +-}; +- +-ð { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_eth_tx_clk>, +- <&pinctrl_eth_tx_ctl_en>, +- <&pinctrl_eth_txd_0>, +- <&pinctrl_eth_txd_1>, +- <&pinctrl_eth_txd_2>, +- <&pinctrl_eth_txd_3>; +-}; +- +-&serial0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0_txd>, <&pinctrl_uart0_rxd>; +-}; +- +-&serial1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1_txd>, <&pinctrl_uart1_rxd>; +-}; +- +-&sdio0_reserved { +- status = "okay"; +-}; +-&sdio0 { +- status = "okay"; +- sdhci-caps = <0 0x01000000>; // Force VOLT33 capability +- bus-width = <4>; +- +- phy-config { +- card-is-emmc = <0x0>; +- cmd-pad-values = <0x1 0x3 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- dat-pad-values = <0x1 0x3 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- rst-pad-values = <0x1 0x3 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- clk-pad-values = <0x1 0x3 0x0 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +- sdclkdl-cnfg = <0x1 0x7F>; //extdly_en, cckdl_dc +- drive-strength = <0x9 0x8>; //pad_sp, pad_sn +- }; +-}; +- +-&gp_vdma { +- status = "disabled"; +-}; +- +-/delete-node/ &cpu_1; +-/delete-node/ &cpu_2; +-/delete-node/ &cpu_3; +diff --git a/scripts/dtc/include-prefixes/arm64/hailo/hailo15l-veloce.dts b/scripts/dtc/include-prefixes/arm64/hailo/hailo15l-veloce.dts +deleted file mode 100644 +index 485fd7dacc4c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hailo/hailo15l-veloce.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019-2024 Hailo Technologies Ltd. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "hailo15l-base.dtsi" +- +-/ { +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x80000000 0x00000000 0x20000000>; +- }; +-}; +- +-ð { +- status = "okay"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/Makefile b/scripts/dtc/include-prefixes/arm64/hisilicon/Makefile +deleted file mode 100644 +index f4d68caeba83..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/Makefile ++++ /dev/null +@@ -1,8 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb +-dtb-$(CONFIG_ARCH_HISI) += hi3670-hikey970.dtb +-dtb-$(CONFIG_ARCH_HISI) += hi3798cv200-poplar.dtb +-dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb +-dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb +-dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb +-dtb-$(CONFIG_ARCH_HISI) += hip07-d05.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/hi3660-coresight.dtsi b/scripts/dtc/include-prefixes/arm64/hisilicon/hi3660-coresight.dtsi +deleted file mode 100644 +index 79a55a0fa2f1..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/hi3660-coresight.dtsi ++++ /dev/null +@@ -1,456 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/* +- * dtsi for Hisilicon Hi3660 Coresight +- * +- * Copyright (C) 2016-2018 HiSilicon Ltd. +- * +- * Author: Wanglai Shi +- * +- */ +-/ { +- soc { +- /* A53 cluster internals */ +- etm@ecc40000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0xecc40000 0 0x1000>; +- clocks = <&crg_ctrl HI3660_PCLK>; +- clock-names = "apb_pclk"; +- cpu = <&cpu0>; +- +- out-ports { +- port { +- etm0_out: endpoint { +- remote-endpoint = +- <&cluster0_funnel_in0>; +- }; +- }; +- }; +- }; +- +- etm@ecd40000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0xecd40000 0 0x1000>; +- clocks = <&crg_ctrl HI3660_PCLK>; +- clock-names = "apb_pclk"; +- cpu = <&cpu1>; +- +- out-ports { +- port { +- etm1_out: endpoint { +- remote-endpoint = +- <&cluster0_funnel_in1>; +- }; +- }; +- }; +- }; +- +- etm@ece40000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0xece40000 0 0x1000>; +- clocks = <&crg_ctrl HI3660_PCLK>; +- clock-names = "apb_pclk"; +- cpu = <&cpu2>; +- +- out-ports { +- port { +- etm2_out: endpoint { +- remote-endpoint = +- <&cluster0_funnel_in2>; +- }; +- }; +- }; +- }; +- +- etm@ecf40000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0xecf40000 0 0x1000>; +- clocks = <&crg_ctrl HI3660_PCLK>; +- clock-names = "apb_pclk"; +- cpu = <&cpu3>; +- +- out-ports { +- port { +- etm3_out: endpoint { +- remote-endpoint = +- <&cluster0_funnel_in3>; +- }; +- }; +- }; +- }; +- +- funnel@ec801000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0xec801000 0 0x1000>; +- clocks = <&crg_ctrl HI3660_PCLK>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- cluster0_funnel_out: endpoint { +- remote-endpoint = +- <&cluster0_etf_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- cluster0_funnel_in0: endpoint { +- remote-endpoint = <&etm0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- cluster0_funnel_in1: endpoint { +- remote-endpoint = <&etm1_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- cluster0_funnel_in2: endpoint { +- remote-endpoint = <&etm2_out>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- cluster0_funnel_in3: endpoint { +- remote-endpoint = <&etm3_out>; +- }; +- }; +- }; +- }; +- +- etf@ec802000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0xec802000 0 0x1000>; +- clocks = <&crg_ctrl HI3660_PCLK>; +- clock-names = "apb_pclk"; +- +- in-ports { +- port { +- cluster0_etf_in: endpoint { +- remote-endpoint = +- <&cluster0_funnel_out>; +- }; +- }; +- }; +- +- out-ports { +- port { +- cluster0_etf_out: endpoint { +- remote-endpoint = +- <&combo_funnel_in0>; +- }; +- }; +- }; +- }; +- +- /* A73 cluster internals */ +- etm@ed440000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0xed440000 0 0x1000>; +- clocks = <&crg_ctrl HI3660_PCLK>; +- clock-names = "apb_pclk"; +- cpu = <&cpu4>; +- +- out-ports { +- port { +- etm4_out: endpoint { +- remote-endpoint = +- <&cluster1_funnel_in0>; +- }; +- }; +- }; +- }; +- +- etm@ed540000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0xed540000 0 0x1000>; +- clocks = <&crg_ctrl HI3660_PCLK>; +- clock-names = "apb_pclk"; +- cpu = <&cpu5>; +- +- out-ports { +- port { +- etm5_out: endpoint { +- remote-endpoint = +- <&cluster1_funnel_in1>; +- }; +- }; +- }; +- }; +- +- etm@ed640000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0xed640000 0 0x1000>; +- clocks = <&crg_ctrl HI3660_PCLK>; +- clock-names = "apb_pclk"; +- cpu = <&cpu6>; +- +- out-ports { +- port { +- etm6_out: endpoint { +- remote-endpoint = +- <&cluster1_funnel_in2>; +- }; +- }; +- }; +- }; +- +- etm@ed740000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0xed740000 0 0x1000>; +- clocks = <&crg_ctrl HI3660_PCLK>; +- clock-names = "apb_pclk"; +- cpu = <&cpu7>; +- +- out-ports { +- port { +- etm7_out: endpoint { +- remote-endpoint = +- <&cluster1_funnel_in3>; +- }; +- }; +- }; +- }; +- +- funnel@ed001000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0xed001000 0 0x1000>; +- clocks = <&crg_ctrl HI3660_PCLK>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- cluster1_funnel_out: endpoint { +- remote-endpoint = +- <&cluster1_etf_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- cluster1_funnel_in0: endpoint { +- remote-endpoint = <&etm4_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- cluster1_funnel_in1: endpoint { +- remote-endpoint = <&etm5_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- cluster1_funnel_in2: endpoint { +- remote-endpoint = <&etm6_out>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- cluster1_funnel_in3: endpoint { +- remote-endpoint = <&etm7_out>; +- }; +- }; +- }; +- }; +- +- etf@ed002000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0xed002000 0 0x1000>; +- clocks = <&crg_ctrl HI3660_PCLK>; +- clock-names = "apb_pclk"; +- +- in-ports { +- port { +- cluster1_etf_in: endpoint { +- remote-endpoint = +- <&cluster1_funnel_out>; +- }; +- }; +- }; +- +- out-ports { +- port { +- cluster1_etf_out: endpoint { +- remote-endpoint = +- <&combo_funnel_in1>; +- }; +- }; +- }; +- }; +- +- /* An invisible combo funnel between clusters and top funnel */ +- funnel { +- compatible = "arm,coresight-static-funnel"; +- clocks = <&crg_ctrl HI3660_PCLK>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- combo_funnel_out: endpoint { +- remote-endpoint = +- <&top_funnel_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- combo_funnel_in0: endpoint { +- remote-endpoint = +- <&cluster0_etf_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- combo_funnel_in1: endpoint { +- remote-endpoint = +- <&cluster1_etf_out>; +- }; +- }; +- }; +- }; +- +- /* Top internals */ +- funnel@ec031000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0xec031000 0 0x1000>; +- clocks = <&crg_ctrl HI3660_PCLK>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- top_funnel_out: endpoint { +- remote-endpoint = +- <&top_etf_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- top_funnel_in: endpoint { +- remote-endpoint = +- <&combo_funnel_out>; +- }; +- }; +- }; +- }; +- +- etf@ec036000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0xec036000 0 0x1000>; +- clocks = <&crg_ctrl HI3660_PCLK>; +- clock-names = "apb_pclk"; +- +- in-ports { +- port { +- top_etf_in: endpoint { +- remote-endpoint = +- <&top_funnel_out>; +- }; +- }; +- }; +- +- out-ports { +- port { +- top_etf_out: endpoint { +- remote-endpoint = +- <&replicator_in>; +- }; +- }; +- }; +- }; +- +- replicator { +- compatible = "arm,coresight-static-replicator"; +- clocks = <&crg_ctrl HI3660_PCLK>; +- clock-names = "apb_pclk"; +- +- in-ports { +- port { +- replicator_in: endpoint { +- remote-endpoint = +- <&top_etf_out>; +- }; +- }; +- }; +- +- out-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- replicator0_out0: endpoint { +- remote-endpoint = <&etr_in>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- replicator0_out1: endpoint { +- remote-endpoint = <&tpiu_in>; +- }; +- }; +- }; +- }; +- +- etr@ec033000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0xec033000 0 0x1000>; +- clocks = <&crg_ctrl HI3660_PCLK>; +- clock-names = "apb_pclk"; +- +- in-ports { +- port { +- etr_in: endpoint { +- remote-endpoint = +- <&replicator0_out0>; +- }; +- }; +- }; +- }; +- +- tpiu@ec032000 { +- compatible = "arm,coresight-tpiu", "arm,primecell"; +- reg = <0 0xec032000 0 0x1000>; +- clocks = <&crg_ctrl HI3660_PCLK>; +- clock-names = "apb_pclk"; +- +- in-ports { +- port { +- tpiu_in: endpoint { +- remote-endpoint = +- <&replicator0_out1>; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/hi3660-hikey960.dts b/scripts/dtc/include-prefixes/arm64/hisilicon/hi3660-hikey960.dts +deleted file mode 100644 +index f68580dc87d8..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/hi3660-hikey960.dts ++++ /dev/null +@@ -1,697 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * dts file for Hisilicon HiKey960 Development Board +- * +- * Copyright (C) 2016, HiSilicon Ltd. +- * +- */ +- +-/dts-v1/; +- +-#include "hi3660.dtsi" +-#include "hikey960-pinctrl.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "HiKey960"; +- compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; +- +- aliases { +- mshc1 = &dwmmc1; +- mshc2 = &dwmmc2; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- serial5 = &uart5; +- serial6 = &uart6; +- }; +- +- chosen { +- stdout-path = "serial6:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- /* rewrite this at bootloader */ +- reg = <0x0 0x0 0x0 0x0>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ramoops@32000000 { +- compatible = "ramoops"; +- reg = <0x0 0x32000000 0x0 0x00100000>; +- record-size = <0x00020000>; +- console-size = <0x00020000>; +- ftrace-size = <0x00020000>; +- }; +- }; +- +- reboot-mode-syscon@32100000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x0 0x32100000 0x0 0x00001000>; +- +- reboot-mode { +- compatible = "syscon-reboot-mode"; +- offset = <0x0>; +- +- mode-normal = <0x77665501>; +- mode-bootloader = <0x77665500>; +- mode-recovery = <0x77665502>; +- }; +- }; +- +- keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>; +- +- power { +- wakeup-source; +- gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; +- label = "GPIO Power"; +- linux,code = ; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- user_led1 { +- label = "green:user1"; +- /* gpio_150_user_led1 */ +- gpios = <&gpio18 6 0>; +- linux,default-trigger = "heartbeat"; +- }; +- +- user_led2 { +- label = "green:user2"; +- /* gpio_151_user_led2 */ +- gpios = <&gpio18 7 0>; +- linux,default-trigger = "none"; +- }; +- +- user_led3 { +- label = "green:user3"; +- /* gpio_189_user_led3 */ +- gpios = <&gpio23 5 0>; +- linux,default-trigger = "mmc0"; +- }; +- +- user_led4 { +- label = "green:user4"; +- /* gpio_190_user_led4 */ +- gpios = <&gpio23 6 0>; +- panic-indicator; +- linux,default-trigger = "none"; +- }; +- +- wlan_active_led { +- label = "yellow:wlan"; +- /* gpio_205_wifi_active */ +- gpios = <&gpio25 5 0>; +- linux,default-trigger = "phy0tx"; +- default-state = "off"; +- }; +- +- bt_active_led { +- label = "blue:bt"; +- gpios = <&gpio25 7 0>; +- /* gpio_207_user_led1 */ +- linux,default-trigger = "hci0-power"; +- default-state = "off"; +- }; +- }; +- +- pmic: pmic@fff34000 { +- compatible = "hisilicon,hi6421v530-pmic"; +- reg = <0x0 0xfff34000 0x0 0x1000>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- regulators { +- ldo3: LDO3 { /* HDMI */ +- regulator-name = "VOUT3_1V85"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2200000>; +- regulator-enable-ramp-delay = <120>; +- }; +- +- ldo9: LDO9 { /* SDCARD I/O */ +- regulator-name = "VOUT9_1V8_2V95"; +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <240>; +- }; +- +- ldo11: LDO11 { /* Low Speed Connector */ +- regulator-name = "VOUT11_1V8_2V95"; +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <240>; +- }; +- +- ldo15: LDO15 { /* UFS VCC */ +- regulator-name = "VOUT15_3V0"; +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-enable-ramp-delay = <120>; +- }; +- +- ldo16: LDO16 { /* SD VDD */ +- regulator-name = "VOUT16_2V95"; +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <3000000>; +- regulator-enable-ramp-delay = <360>; +- }; +- }; +- }; +- +- wlan_en: wlan-en-1-8v { +- compatible = "regulator-fixed"; +- regulator-name = "wlan-en-regulator"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- /* GPIO_051_WIFI_EN */ +- gpio = <&gpio6 3 0>; +- +- /* WLAN card specific delay */ +- startup-delay-us = <70000>; +- enable-active-high; +- }; +- +- firmware { +- optee { +- compatible = "linaro,optee-tz"; +- method = "smc"; +- }; +- }; +-}; +- +-/* +- * Legend: proper name = the GPIO line is used as GPIO +- * NC = not connected (pin out but not routed from the chip to +- * anything the board) +- * "[PER]" = pin is muxed for [peripheral] (not GPIO) +- * "" = no idea, schematic doesn't say, could be +- * unrouted (not connected to any external pin) +- * LSEC = Low Speed External Connector +- * HSEC = High Speed External Connector +- * +- * Line names are taken from "HiKey 960 Board ver A" schematics +- * from Huawei. The 40 pin low speed expansion connector is named +- * J2002 63453-140LF. +- * +- * For the lines routed to the external connectors the +- * lines are named after the 96Boards CE Specification 1.0, +- * Appendix "Expansion Connector Signal Description". +- * +- * When the 96Board naming of a line and the schematic name of +- * the same line are in conflict, the 96Board specification +- * takes precedence, which means that the external UART on the +- * LSEC is named UART0 while the schematic and SoC names this +- * UART3. This is only for the informational lines i.e. "[FOO]", +- * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only +- * ones actually used for GPIO. +- */ +-&gpio0 { +- /* GPIO_000-GPIO_007 */ +- gpio-line-names = +- "", +- "TP901", /* TEST_MODE connected to TP901 */ +- "[PMU0_SSI]", +- "[PMU1_SSI]", +- "[PMU2_SSI]", +- "[PMU0_CLKOUT]", +- "[JTAG_TCK]", +- "[JTAG_TMS]"; +-}; +- +-&gpio1 { +- /* GPIO_008-GPIO_015 */ +- gpio-line-names = +- "[JTAG_TRST_N]", +- "[JTAG_TDI]", +- "[JTAG_TDO]", +- "NC", "NC", +- "[I2C3_SCL]", +- "[I2C3_SDA]", +- "NC"; +-}; +- +-&gpio2 { +- /* GPIO_016-GPIO_023 */ +- gpio-line-names = +- "NC", "NC", "NC", +- "GPIO-J", /* LSEC pin 32: GPIO_019 */ +- "GPIO_020_HDMI_SEL", +- "GPIO-L", /* LSEC pin 34: GPIO_021 */ +- "GPIO_022_UFSBUCK_INT_N", +- "GPIO-G"; /* LSEC pin 29: LCD_TE0 */ +-}; +- +-&gpio3 { +- /* GPIO_024-GPIO_031 */ +- /* The rail from pin BK36 is named LCD_TE0, we assume to be muxed as GPIO for GPIO-G */ +- gpio-line-names = +- "[CSI0_MCLK]", /* HSEC pin 15: ISP_CCLK0_MCAM */ +- "[CSI1_MCLK]", /* HSEC pin 17: ISP_CCLK1_SCAM */ +- "NC", +- "[I2C2_SCL]", /* HSEC pin 32: ISP_SCL0 */ +- "[I2C2_SDA]", /* HSEC pin 34: ISP_SDA0 */ +- "[I2C3_SCL]", /* HSEC pin 36: ISP_SCL1 */ +- "[I2C3_SDA]", /* HSEC pin 38: ISP_SDA1 */ +- "NC"; +-}; +- +-&gpio4 { +- /* GPIO_032-GPIO_039 */ +- gpio-line-names = +- "NC", "NC", +- "PWR_BTN_N", /* LSEC pin 4: GPIO_034_PWRON_DET */ +- "GPIO_035_PMU2_EN", +- "GPIO_036_USB_HUB_RESET", +- "NC", "NC", "NC"; +-}; +- +-&gpio5 { +- /* GPIO_040-GPIO_047 */ +- gpio-line-names = +- "GPIO-H", /* LSEC pin 30: GPIO_040_LCD_RST_N */ +- "GPIO_041_HDMI_PD", +- "TP904", /* Test point */ +- "TP905", /* Test point */ +- "NC", "NC", +- "GPIO_046_HUB_VDD33_EN", +- "GPIO_047_PMU1_EN"; +-}; +- +-&gpio6 { +- /* GPIO_048-GPIO_055 */ +- gpio-line-names = +- "NC", "NC", "NC", +- "GPIO_051_WIFI_EN", +- "GPIO-I", /* LSEC pin 31: GPIO_052_CAM0_RST_N */ +- /* +- * These two pins should be used for SD(IO) data according to the +- * 96boards specification but seems to be repurposed for a IRDA UART. +- * They are however named according to the spec. +- */ +- "[SD_DAT1]", /* HSEC pin 3: UART0_IRDA_RXD */ +- "[SD_DAT2]", /* HSEC pin 5: UART0_IRDA_TXD */ +- "[UART1_RXD]"; /* LSEC pin 13: DEBUG_UART6_RXD */ +-}; +- +-&gpio7 { +- /* GPIO_056-GPIO_063 */ +- gpio-line-names = +- "[UART1_TXD]", /* LSEC pin 11: DEBUG_UART6_TXD */ +- "[UART0_CTS]", /* LSEC pin 3: UART3_CTS_N */ +- "[UART0_RTS]", /* LSEC pin 9: UART3_RTS_N */ +- "[UART0_RXD]", /* LSEC pin 7: UART3_RXD */ +- "[UART0_TXD]", /* LSEC pin 5: UART3_TXD */ +- "[SOC_BT_UART4_CTS_N]", +- "[SOC_BT_UART4_RTS_N]", +- "[SOC_BT_UART4_RXD]"; +-}; +- +-&gpio8 { +- /* GPIO_064-GPIO_071 */ +- gpio-line-names = +- "[SOC_BT_UART4_TXD]", +- "NC", +- "[PMU_HKADC_SSI]", +- "NC", +- "GPIO_068_SEL", +- "NC", "NC", "NC"; +- +-}; +- +-&gpio9 { +- /* GPIO_072-GPIO_079 */ +- gpio-line-names = +- "NC", "NC", "NC", +- "GPIO-K", /* LSEC pin 33: GPIO_075_CAM1_RST_N */ +- "NC", "NC", "NC", "NC"; +-}; +- +-&gpio10 { +- /* GPIO_080-GPIO_087 */ +- gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +-}; +- +-&gpio11 { +- /* GPIO_088-GPIO_095 */ +- gpio-line-names = +- "NC", +- "[PCIE_PERST_N]", +- "NC", "NC", "NC", "NC", "NC", "NC"; +-}; +- +-&gpio12 { +- /* GPIO_096-GPIO_103 */ +- gpio-line-names = "NC", "NC", "NC", "", "", "", "", "NC"; +-}; +- +-&gpio13 { +- /* GPIO_104-GPIO_111 */ +- gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +-}; +- +-&gpio14 { +- /* GPIO_112-GPIO_119 */ +- gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +-}; +- +-&gpio15 { +- /* GPIO_120-GPIO_127 */ +- gpio-line-names = +- "NC", "NC", "NC", "NC", "NC", "NC", +- "GPIO_126_BT_EN", +- "TP902"; /* GPIO_127_JTAG_SEL0 */ +-}; +- +-&gpio16 { +- /* GPIO_128-GPIO_135 */ +- gpio-line-names = "", "", "", "", "", "", "", ""; +-}; +- +-&gpio17 { +- /* GPIO_136-GPIO_143 */ +- gpio-line-names = "", "", "", "", "", "", "", ""; +-}; +- +-&gpio18 { +- /* GPIO_144-GPIO_151 */ +- gpio-line-names = +- "[UFS_REF_CLK]", +- "[UFS_RST_N]", +- "[SPI1_SCLK]", /* HSEC pin 9: GPIO_146_SPI3_CLK */ +- "[SPI1_DIN]", /* HSEC pin 11: GPIO_147_SPI3_DI */ +- "[SPI1_DOUT]", /* HSEC pin 1: GPIO_148_SPI3_DO */ +- "[SPI1_CS]", /* HSEC pin 7: GPIO_149_SPI3_CS0_N */ +- "GPIO_150_USER_LED1", +- "GPIO_151_USER_LED2"; +-}; +- +-&gpio19 { +- /* GPIO_152-GPIO_159 */ +- gpio-line-names = "NC", "NC", "NC", "NC", "", "", "", ""; +-}; +- +-&gpio20 { +- /* GPIO_160-GPIO_167 */ +- gpio-line-names = +- "[SD_CLK]", +- "[SD_CMD]", +- "[SD_DATA0]", +- "[SD_DATA1]", +- "[SD_DATA2]", +- "[SD_DATA3]", +- "", ""; +-}; +- +-&gpio21 { +- /* GPIO_168-GPIO_175 */ +- gpio-line-names = +- "[WL_SDIO_CLK]", +- "[WL_SDIO_CMD]", +- "[WL_SDIO_DATA0]", +- "[WL_SDIO_DATA1]", +- "[WL_SDIO_DATA2]", +- "[WL_SDIO_DATA3]", +- "", ""; +-}; +- +-&gpio22 { +- /* GPIO_176-GPIO_183 */ +- gpio-line-names = +- "[GPIO_176_PMU_PWR_HOLD]", +- "NA", +- "[SYSCLK_EN]", +- "GPIO_179_WL_WAKEUP_AP", +- "GPIO_180_HDMI_INT", +- "NA", +- "GPIO-F", /* LSEC pin 28: LCD_BL_PWM */ +- "[I2C0_SCL]"; /* LSEC pin 15 */ +-}; +- +-&gpio23 { +- /* GPIO_184-GPIO_191 */ +- gpio-line-names = +- "[I2C0_SDA]", /* LSEC pin 17 */ +- "[I2C1_SCL]", /* Actual SoC I2C1 */ +- "[I2C1_SDA]", /* Actual SoC I2C1 */ +- "[I2C1_SCL]", /* LSEC pin 19: I2C7_SCL */ +- "[I2C1_SDA]", /* LSEC pin 21: I2C7_SDA */ +- "GPIO_189_USER_LED3", +- "GPIO_190_USER_LED4", +- ""; +-}; +- +-&gpio24 { +- /* GPIO_192-GPIO_199 */ +- gpio-line-names = +- "[PCM_DI]", /* LSEC pin 22: GPIO_192_I2S0_DI */ +- "[PCM_DO]", /* LSEC pin 20: GPIO_193_I2S0_DO */ +- "[PCM_CLK]", /* LSEC pin 18: GPIO_194_I2S0_XCLK */ +- "[PCM_FS]", /* LSEC pin 16: GPIO_195_I2S0_XFS */ +- "[GPIO_196_I2S2_DI]", +- "[GPIO_197_I2S2_DO]", +- "[GPIO_198_I2S2_XCLK]", +- "[GPIO_199_I2S2_XFS]"; +-}; +- +-&gpio25 { +- /* GPIO_200-GPIO_207 */ +- gpio-line-names = +- "NC", +- "NC", +- "GPIO_202_VBUS_TYPEC", +- "GPIO_203_SD_DET", +- "GPIO_204_PMU12_IRQ_N", +- "GPIO_205_WIFI_ACTIVE", +- "GPIO_206_USBSW_SEL", +- "GPIO_207_BT_ACTIVE"; +-}; +- +-&gpio26 { +- /* GPIO_208-GPIO_215 */ +- gpio-line-names = +- "GPIO-A", /* LSEC pin 23: GPIO_208 */ +- "GPIO-B", /* LSEC pin 24: GPIO_209 */ +- "GPIO-C", /* LSEC pin 25: GPIO_210 */ +- "GPIO-D", /* LSEC pin 26: GPIO_211 */ +- "GPIO-E", /* LSEC pin 27: GPIO_212 */ +- "[PCIE_CLKREQ_N]", +- "[PCIE_WAKE_N]", +- "[SPI0_CLK]"; /* LSEC pin 8: SPI2_CLK */ +-}; +- +-&gpio27 { +- /* GPIO_216-GPIO_223 */ +- gpio-line-names = +- "[SPI0_DIN]", /* LSEC pin 10: SPI2_DI */ +- "[SPI0_DOUT]", /* LSEC pin 14: SPI2_DO */ +- "[SPI0_CS]", /* LSEC pin 12: SPI2_CS0_N */ +- "GPIO_219_CC_INT", +- "NC", +- "NC", +- "[PMU_INT]", +- ""; +-}; +- +-&gpio28 { +- /* GPIO_224-GPIO_231 */ +- gpio-line-names = +- "", "", "", "", "", "", "", ""; +-}; +- +-&i2c0 { +- /* On Low speed expansion */ +- label = "LS-I2C0"; +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- +- rt1711h: rt1711h@4e { +- compatible = "richtek,rt1711h"; +- reg = <0x4e>; +- status = "okay"; +- interrupt-parent = <&gpio27>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_cfg_func>; +- +- usb_con: connector { +- compatible = "usb-c-connector"; +- label = "USB-C"; +- data-role = "dual"; +- power-role = "dual"; +- try-power-role = "sink"; +- source-pdos = ; +- sink-pdos = ; +- op-sink-microwatt = <10000000>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@1 { +- reg = <1>; +- usb_con_ss: endpoint { +- remote-endpoint = <&dwc3_ss>; +- }; +- }; +- }; +- }; +- port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- rt1711h_ep: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&dwc3_role_switch>; +- }; +- }; +- }; +- +- adv7533: adv7533@39 { +- status = "okay"; +- compatible = "adi,adv7533"; +- reg = <0x39>; +- adi,dsi-lanes = <4>; +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- }; +- port@1 { +- reg = <1>; +- }; +- }; +- }; +-}; +- +-&i2c7 { +- /* On Low speed expansion */ +- label = "LS-I2C1"; +- status = "okay"; +-}; +- +-&uart3 { +- /* On Low speed expansion */ +- label = "LS-UART0"; +- status = "okay"; +-}; +- +-&uart4 { +- status = "okay"; +- +- bluetooth { +- compatible = "ti,wl1837-st"; +- enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>; +- max-speed = <3000000>; +- }; +-}; +- +-&uart6 { +- /* On Low speed expansion */ +- label = "LS-UART1"; +- status = "okay"; +-}; +- +-&spi2 { +- /* On Low speed expansion */ +- label = "LS-SPI0"; +- status = "okay"; +-}; +- +-&spi3 { +- /* On High speed expansion */ +- label = "HS-SPI1"; +- status = "okay"; +-}; +- +-&dwmmc1 { +- bus-width = <0x4>; +- cap-sd-highspeed; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- disable-wp; +- cd-gpios = <&gpio25 3 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd_pmx_func +- &sd_clk_cfg_func +- &sd_cfg_func>; +- vmmc-supply = <&ldo16>; +- vqmmc-supply = <&ldo9>; +- status = "okay"; +-}; +- +-&dwmmc2 { /* WIFI */ +- bus-width = <0x4>; +- non-removable; +- broken-cd; +- cap-power-off-card; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio_pmx_func +- &sdio_clk_cfg_func +- &sdio_cfg_func>; +- /* WL_EN */ +- vmmc-supply = <&wlan_en>; +- status = "okay"; +- +- wlcore: wlcore@2 { +- compatible = "ti,wl1837"; +- reg = <2>; /* sdio func num */ +- /* WL_IRQ, GPIO_179_WL_WAKEUP_AP */ +- interrupt-parent = <&gpio22>; +- interrupts = <3 IRQ_TYPE_EDGE_RISING>; +- }; +-}; +- +-&dwc3 { /* USB */ +- dr_mode = "otg"; +- maximum-speed = "super-speed"; +- phy_type = "utmi"; +- snps,dis-del-phy-power-chg-quirk; +- snps,lfps_filter_quirk; +- snps,dis_u2_susphy_quirk; +- snps,dis_u3_susphy_quirk; +- snps,tx_de_emphasis_quirk; +- snps,tx_de_emphasis = <1>; +- snps,dis_enblslpm_quirk; +- snps,gctl-reset-quirk; +- usb-role-switch; +- role-switch-default-mode = "host"; +- port { +- #address-cells = <1>; +- #size-cells = <0>; +- dwc3_role_switch: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&rt1711h_ep>; +- }; +- +- dwc3_ss: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&usb_con_ss>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/hi3660.dtsi b/scripts/dtc/include-prefixes/arm64/hisilicon/hi3660.dtsi +deleted file mode 100644 +index 6eabec2602e2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/hi3660.dtsi ++++ /dev/null +@@ -1,1195 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * dts file for Hisilicon Hi3660 SoC +- * +- * Copyright (C) 2016, HiSilicon Ltd. +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "hisilicon,hi3660"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- core2 { +- cpu = <&cpu2>; +- }; +- core3 { +- cpu = <&cpu3>; +- }; +- }; +- cluster1 { +- core0 { +- cpu = <&cpu4>; +- }; +- core1 { +- cpu = <&cpu5>; +- }; +- core2 { +- cpu = <&cpu6>; +- }; +- core3 { +- cpu = <&cpu7>; +- }; +- }; +- }; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <592>; +- clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; +- operating-points-v2 = <&cluster0_opp>; +- #cooling-cells = <2>; +- dynamic-power-coefficient = <110>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <592>; +- clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; +- operating-points-v2 = <&cluster0_opp>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <592>; +- clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; +- operating-points-v2 = <&cluster0_opp>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- next-level-cache = <&A53_L2>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <592>; +- clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; +- operating-points-v2 = <&cluster0_opp>; +- #cooling-cells = <2>; +- }; +- +- cpu4: cpu@100 { +- compatible = "arm,cortex-a73"; +- device_type = "cpu"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- next-level-cache = <&A73_L2>; +- cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; +- capacity-dmips-mhz = <1024>; +- clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; +- operating-points-v2 = <&cluster1_opp>; +- #cooling-cells = <2>; +- dynamic-power-coefficient = <550>; +- }; +- +- cpu5: cpu@101 { +- compatible = "arm,cortex-a73"; +- device_type = "cpu"; +- reg = <0x0 0x101>; +- enable-method = "psci"; +- next-level-cache = <&A73_L2>; +- cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; +- capacity-dmips-mhz = <1024>; +- clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; +- operating-points-v2 = <&cluster1_opp>; +- #cooling-cells = <2>; +- }; +- +- cpu6: cpu@102 { +- compatible = "arm,cortex-a73"; +- device_type = "cpu"; +- reg = <0x0 0x102>; +- enable-method = "psci"; +- next-level-cache = <&A73_L2>; +- cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; +- capacity-dmips-mhz = <1024>; +- clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; +- operating-points-v2 = <&cluster1_opp>; +- #cooling-cells = <2>; +- }; +- +- cpu7: cpu@103 { +- compatible = "arm,cortex-a73"; +- device_type = "cpu"; +- reg = <0x0 0x103>; +- enable-method = "psci"; +- next-level-cache = <&A73_L2>; +- cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; +- capacity-dmips-mhz = <1024>; +- clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; +- operating-points-v2 = <&cluster1_opp>; +- #cooling-cells = <2>; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP_0: cpu-sleep-0 { +- compatible = "arm,idle-state"; +- local-timer-stop; +- arm,psci-suspend-param = <0x0010000>; +- entry-latency-us = <400>; +- exit-latency-us = <650>; +- min-residency-us = <1500>; +- }; +- CLUSTER_SLEEP_0: cluster-sleep-0 { +- compatible = "arm,idle-state"; +- local-timer-stop; +- arm,psci-suspend-param = <0x1010000>; +- entry-latency-us = <500>; +- exit-latency-us = <1600>; +- min-residency-us = <3500>; +- }; +- +- +- CPU_SLEEP_1: cpu-sleep-1 { +- compatible = "arm,idle-state"; +- local-timer-stop; +- arm,psci-suspend-param = <0x0010000>; +- entry-latency-us = <400>; +- exit-latency-us = <550>; +- min-residency-us = <1500>; +- }; +- +- CLUSTER_SLEEP_1: cluster-sleep-1 { +- compatible = "arm,idle-state"; +- local-timer-stop; +- arm,psci-suspend-param = <0x1010000>; +- entry-latency-us = <800>; +- exit-latency-us = <2900>; +- min-residency-us = <3500>; +- }; +- }; +- +- A53_L2: l2-cache0 { +- compatible = "cache"; +- }; +- +- A73_L2: l2-cache1 { +- compatible = "cache"; +- }; +- }; +- +- cluster0_opp: opp_table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp00 { +- opp-hz = /bits/ 64 <533000000>; +- opp-microvolt = <700000>; +- clock-latency-ns = <300000>; +- }; +- +- opp01 { +- opp-hz = /bits/ 64 <999000000>; +- opp-microvolt = <800000>; +- clock-latency-ns = <300000>; +- }; +- +- opp02 { +- opp-hz = /bits/ 64 <1402000000>; +- opp-microvolt = <900000>; +- clock-latency-ns = <300000>; +- }; +- +- opp03 { +- opp-hz = /bits/ 64 <1709000000>; +- opp-microvolt = <1000000>; +- clock-latency-ns = <300000>; +- }; +- +- opp04 { +- opp-hz = /bits/ 64 <1844000000>; +- opp-microvolt = <1100000>; +- clock-latency-ns = <300000>; +- }; +- }; +- +- cluster1_opp: opp_table1 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp10 { +- opp-hz = /bits/ 64 <903000000>; +- opp-microvolt = <700000>; +- clock-latency-ns = <300000>; +- }; +- +- opp11 { +- opp-hz = /bits/ 64 <1421000000>; +- opp-microvolt = <800000>; +- clock-latency-ns = <300000>; +- }; +- +- opp12 { +- opp-hz = /bits/ 64 <1805000000>; +- opp-microvolt = <900000>; +- clock-latency-ns = <300000>; +- }; +- +- opp13 { +- opp-hz = /bits/ 64 <2112000000>; +- opp-microvolt = <1000000>; +- clock-latency-ns = <300000>; +- }; +- +- opp14 { +- opp-hz = /bits/ 64 <2362000000>; +- opp-microvolt = <1100000>; +- clock-latency-ns = <300000>; +- }; +- }; +- +- gic: interrupt-controller@e82b0000 { +- compatible = "arm,gic-400"; +- reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ +- <0x0 0xe82b2000 0 0x2000>, /* GICC */ +- <0x0 0xe82b4000 0 0x2000>, /* GICH */ +- <0x0 0xe82b6000 0 0x2000>; /* GICV */ +- #address-cells = <0>; +- #interrupt-cells = <3>; +- interrupt-controller; +- interrupts = ; +- }; +- +- a53-pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, +- <&cpu1>, +- <&cpu2>, +- <&cpu3>; +- }; +- +- a73-pmu { +- compatible = "arm,cortex-a73-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu4>, +- <&cpu5>, +- <&cpu6>, +- <&cpu7>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- crg_ctrl: crg_ctrl@fff35000 { +- compatible = "hisilicon,hi3660-crgctrl", "syscon"; +- reg = <0x0 0xfff35000 0x0 0x1000>; +- #clock-cells = <1>; +- }; +- +- crg_rst: crg_rst_controller { +- compatible = "hisilicon,hi3660-reset"; +- #reset-cells = <2>; +- hisi,rst-syscon = <&crg_ctrl>; +- }; +- +- +- pctrl: pctrl@e8a09000 { +- compatible = "hisilicon,hi3660-pctrl", "syscon"; +- reg = <0x0 0xe8a09000 0x0 0x2000>; +- #clock-cells = <1>; +- }; +- +- pmuctrl: crg_ctrl@fff34000 { +- compatible = "hisilicon,hi3660-pmuctrl", "syscon"; +- reg = <0x0 0xfff34000 0x0 0x1000>; +- #clock-cells = <1>; +- }; +- +- sctrl: sctrl@fff0a000 { +- compatible = "hisilicon,hi3660-sctrl", "syscon"; +- reg = <0x0 0xfff0a000 0x0 0x1000>; +- #clock-cells = <1>; +- }; +- +- iomcu: iomcu@ffd7e000 { +- compatible = "hisilicon,hi3660-iomcu", "syscon"; +- reg = <0x0 0xffd7e000 0x0 0x1000>; +- #clock-cells = <1>; +- +- }; +- +- iomcu_rst: reset { +- compatible = "hisilicon,hi3660-reset"; +- hisi,rst-syscon = <&iomcu>; +- #reset-cells = <2>; +- }; +- +- mailbox: mailbox@e896b000 { +- compatible = "hisilicon,hi3660-mbox"; +- reg = <0x0 0xe896b000 0x0 0x1000>; +- interrupts = , +- ; +- #mbox-cells = <3>; +- }; +- +- stub_clock: stub_clock@e896b500 { +- compatible = "hisilicon,hi3660-stub-clk"; +- reg = <0x0 0xe896b500 0x0 0x0100>; +- #clock-cells = <1>; +- mboxes = <&mailbox 13 3 0>; +- }; +- +- dual_timer0: timer@fff14000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x0 0xfff14000 0x0 0x1000>; +- interrupts = , +- ; +- clocks = <&crg_ctrl HI3660_OSC32K>, +- <&crg_ctrl HI3660_OSC32K>, +- <&crg_ctrl HI3660_OSC32K>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- }; +- +- i2c0: i2c@ffd71000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0xffd71000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <400000>; +- clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; +- resets = <&iomcu_rst 0x20 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; +- status = "disabled"; +- }; +- +- i2c1: i2c@ffd72000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0xffd72000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <400000>; +- clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; +- resets = <&iomcu_rst 0x20 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; +- status = "disabled"; +- }; +- +- i2c3: i2c@fdf0c000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0xfdf0c000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <400000>; +- clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; +- resets = <&crg_rst 0x78 7>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; +- status = "disabled"; +- }; +- +- i2c7: i2c@fdf0b000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0xfdf0b000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <400000>; +- clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; +- resets = <&crg_rst 0x60 14>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; +- status = "disabled"; +- }; +- +- uart0: serial@fdf02000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xfdf02000 0x0 0x1000>; +- interrupts = ; +- clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, +- <&crg_ctrl HI3660_PCLK>; +- clock-names = "uartclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; +- status = "disabled"; +- }; +- +- uart1: serial@fdf00000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xfdf00000 0x0 0x1000>; +- interrupts = ; +- dma-names = "rx", "tx"; +- dmas = <&dma0 2 &dma0 3>; +- clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, +- <&crg_ctrl HI3660_CLK_GATE_UART1>; +- clock-names = "uartclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; +- status = "disabled"; +- }; +- +- uart2: serial@fdf03000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xfdf03000 0x0 0x1000>; +- interrupts = ; +- dma-names = "rx", "tx"; +- dmas = <&dma0 4 &dma0 5>; +- clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, +- <&crg_ctrl HI3660_PCLK>; +- clock-names = "uartclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; +- status = "disabled"; +- }; +- +- uart3: serial@ffd74000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xffd74000 0x0 0x1000>; +- interrupts = ; +- clocks = <&crg_ctrl HI3660_FACTOR_UART3>, +- <&crg_ctrl HI3660_PCLK>; +- clock-names = "uartclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; +- status = "disabled"; +- }; +- +- uart4: serial@fdf01000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xfdf01000 0x0 0x1000>; +- interrupts = ; +- dma-names = "rx", "tx"; +- dmas = <&dma0 6 &dma0 7>; +- clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, +- <&crg_ctrl HI3660_CLK_GATE_UART4>; +- clock-names = "uartclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; +- status = "disabled"; +- }; +- +- uart5: serial@fdf05000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xfdf05000 0x0 0x1000>; +- interrupts = ; +- dma-names = "rx", "tx"; +- dmas = <&dma0 8 &dma0 9>; +- clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, +- <&crg_ctrl HI3660_CLK_GATE_UART5>; +- clock-names = "uartclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; +- status = "disabled"; +- }; +- +- uart6: serial@fff32000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xfff32000 0x0 0x1000>; +- interrupts = ; +- clocks = <&crg_ctrl HI3660_CLK_UART6>, +- <&crg_ctrl HI3660_PCLK>; +- clock-names = "uartclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; +- status = "disabled"; +- }; +- +- dma0: dma@fdf30000 { +- compatible = "hisilicon,k3-dma-1.0"; +- reg = <0x0 0xfdf30000 0x0 0x1000>; +- #dma-cells = <1>; +- dma-channels = <16>; +- dma-requests = <32>; +- dma-channel-mask = <0xfffe>; +- interrupts = ; +- clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; +- dma-no-cci; +- dma-type = "hi3660_dma"; +- }; +- +- asp_dmac: dma-controller@e804b000 { +- compatible = "hisilicon,hisi-pcm-asp-dma-1.0"; +- reg = <0x0 0xe804b000 0x0 0x1000>; +- #dma-cells = <1>; +- dma-channels = <16>; +- dma-requests = <32>; +- interrupts = ; +- interrupt-names = "asp_dma_irq"; +- }; +- +- rtc0: rtc@fff04000 { +- compatible = "arm,pl031", "arm,primecell"; +- reg = <0x0 0Xfff04000 0x0 0x1000>; +- interrupts = ; +- clocks = <&crg_ctrl HI3660_PCLK>; +- clock-names = "apb_pclk"; +- }; +- +- gpio0: gpio@e8a0b000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a0b000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 1 0 7>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; +- clock-names = "apb_pclk"; +- }; +- +- gpio1: gpio@e8a0c000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a0c000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 1 7 7>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; +- clock-names = "apb_pclk"; +- }; +- +- gpio2: gpio@e8a0d000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a0d000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 14 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio3: gpio@e8a0e000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a0e000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 22 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; +- clock-names = "apb_pclk"; +- }; +- +- gpio4: gpio@e8a0f000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a0f000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 30 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; +- clock-names = "apb_pclk"; +- }; +- +- gpio5: gpio@e8a10000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a10000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 38 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; +- clock-names = "apb_pclk"; +- }; +- +- gpio6: gpio@e8a11000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a11000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 46 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; +- clock-names = "apb_pclk"; +- }; +- +- gpio7: gpio@e8a12000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a12000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 54 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; +- clock-names = "apb_pclk"; +- }; +- +- gpio8: gpio@e8a13000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a13000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 62 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; +- clock-names = "apb_pclk"; +- }; +- +- gpio9: gpio@e8a14000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a14000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 70 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; +- clock-names = "apb_pclk"; +- }; +- +- gpio10: gpio@e8a15000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a15000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 78 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; +- clock-names = "apb_pclk"; +- }; +- +- gpio11: gpio@e8a16000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a16000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 86 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; +- clock-names = "apb_pclk"; +- }; +- +- gpio12: gpio@e8a17000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a17000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; +- clock-names = "apb_pclk"; +- }; +- +- gpio13: gpio@e8a18000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a18000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 102 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; +- clock-names = "apb_pclk"; +- }; +- +- gpio14: gpio@e8a19000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a19000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 110 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; +- clock-names = "apb_pclk"; +- }; +- +- gpio15: gpio@e8a1a000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a1a000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 118 6>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; +- clock-names = "apb_pclk"; +- }; +- +- gpio16: gpio@e8a1b000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a1b000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; +- clock-names = "apb_pclk"; +- }; +- +- gpio17: gpio@e8a1c000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a1c000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; +- clock-names = "apb_pclk"; +- }; +- +- gpio18: gpio@ff3b4000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xff3b4000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx2 0 0 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; +- clock-names = "apb_pclk"; +- }; +- +- gpio19: gpio@ff3b5000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xff3b5000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx2 0 8 4>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; +- clock-names = "apb_pclk"; +- }; +- +- gpio20: gpio@e8a1f000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a1f000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx1 0 0 6>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; +- clock-names = "apb_pclk"; +- }; +- +- gpio21: gpio@e8a20000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xe8a20000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&pmx3 0 0 6>; +- clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; +- clock-names = "apb_pclk"; +- }; +- +- gpio22: gpio@fff0b000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xfff0b000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- /* GPIO176 */ +- gpio-ranges = <&pmx4 2 0 6>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; +- clock-names = "apb_pclk"; +- }; +- +- gpio23: gpio@fff0c000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xfff0c000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- /* GPIO184 */ +- gpio-ranges = <&pmx4 0 6 7>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; +- clock-names = "apb_pclk"; +- }; +- +- gpio24: gpio@fff0d000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xfff0d000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- /* GPIO192 */ +- gpio-ranges = <&pmx4 0 13 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio25: gpio@fff0e000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xfff0e000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- /* GPIO200 */ +- gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; +- clock-names = "apb_pclk"; +- }; +- +- gpio26: gpio@fff0f000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xfff0f000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- /* GPIO208 */ +- gpio-ranges = <&pmx4 0 28 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; +- clock-names = "apb_pclk"; +- }; +- +- gpio27: gpio@fff10000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xfff10000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- /* GPIO216 */ +- gpio-ranges = <&pmx4 0 36 6>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; +- clock-names = "apb_pclk"; +- }; +- +- gpio28: gpio@fff1d000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0 0xfff1d000 0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; +- clock-names = "apb_pclk"; +- }; +- +- spi2: spi@ffd68000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x0 0xffd68000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>, <&crg_ctrl HI3660_CLK_GATE_SPI2>; +- clock-names = "sspclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>; +- num-cs = <1>; +- cs-gpios = <&gpio27 2 0>; +- status = "disabled"; +- }; +- +- spi3: spi@ff3b3000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x0 0xff3b3000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>, <&crg_ctrl HI3660_CLK_GATE_SPI3>; +- clock-names = "sspclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>; +- num-cs = <1>; +- cs-gpios = <&gpio18 5 0>; +- status = "disabled"; +- }; +- +- pcie@f4000000 { +- compatible = "hisilicon,kirin960-pcie"; +- reg = <0x0 0xf4000000 0x0 0x1000>, +- <0x0 0xff3fe000 0x0 0x1000>, +- <0x0 0xf3f20000 0x0 0x40000>, +- <0x0 0xf5000000 0x0 0x2000>; +- reg-names = "dbi", "apb", "phy", "config"; +- bus-range = <0x0 0xff>; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x02000000 0x0 0x00000000 +- 0x0 0xf6000000 +- 0x0 0x02000000>; +- num-lanes = <1>; +- #interrupt-cells = <1>; +- interrupts = <0 283 4>; +- interrupt-names = "msi"; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0x0 0 0 1 +- &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, +- <0x0 0 0 2 +- &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, +- <0x0 0 0 3 +- &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, +- <0x0 0 0 4 +- &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, +- <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, +- <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, +- <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, +- <&crg_ctrl HI3660_ACLK_GATE_PCIE>; +- clock-names = "pcie_phy_ref", "pcie_aux", +- "pcie_apb_phy", "pcie_apb_sys", +- "pcie_aclk"; +- reset-gpios = <&gpio11 1 0 >; +- }; +- +- /* UFS */ +- ufs: ufs@ff3b0000 { +- compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; +- /* 0: HCI standard */ +- /* 1: UFS SYS CTRL */ +- reg = <0x0 0xff3b0000 0x0 0x1000>, +- <0x0 0xff3b1000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = ; +- clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, +- <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; +- clock-names = "ref_clk", "phy_clk"; +- freq-table-hz = <0 0 +- 0 0>; +- /* offset: 0x84; bit: 12 */ +- resets = <&crg_rst 0x84 12>; +- reset-names = "rst"; +- }; +- +- /* SD */ +- dwmmc1: dwmmc1@ff37f000 { +- compatible = "hisilicon,hi3660-dw-mshc"; +- reg = <0x0 0xff37f000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, +- <&crg_ctrl HI3660_HCLK_GATE_SD>; +- clock-names = "ciu", "biu"; +- clock-frequency = <3200000>; +- resets = <&crg_rst 0x94 18>; +- reset-names = "reset"; +- hisilicon,peripheral-syscon = <&sctrl>; +- card-detect-delay = <200>; +- status = "disabled"; +- }; +- +- /* SDIO */ +- dwmmc2: dwmmc2@ff3ff000 { +- compatible = "hisilicon,hi3660-dw-mshc"; +- reg = <0x0 0xff3ff000 0x0 0x1000>; +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- interrupts = ; +- clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, +- <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; +- clock-names = "ciu", "biu"; +- resets = <&crg_rst 0x94 20>; +- reset-names = "reset"; +- card-detect-delay = <200>; +- status = "disabled"; +- }; +- +- watchdog0: watchdog@e8a06000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xe8a06000 0x0 0x1000>; +- interrupts = ; +- clocks = <&crg_ctrl HI3660_OSC32K>, +- <&crg_ctrl HI3660_OSC32K>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- watchdog1: watchdog@e8a07000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xe8a07000 0x0 0x1000>; +- interrupts = ; +- clocks = <&crg_ctrl HI3660_OSC32K>, +- <&crg_ctrl HI3660_OSC32K>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- tsensor: tsensor@fff30000 { +- compatible = "hisilicon,hi3660-tsensor"; +- reg = <0x0 0xfff30000 0x0 0x1000>; +- interrupts = ; +- #thermal-sensor-cells = <1>; +- }; +- +- thermal-zones { +- +- cls0: cls0-thermal { +- polling-delay = <1000>; +- polling-delay-passive = <100>; +- sustainable-power = <4500>; +- +- /* sensor ID */ +- thermal-sensors = <&tsensor 1>; +- +- trips { +- threshold: trip-point0 { +- temperature = <65000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- +- target: trip-point1 { +- temperature = <75000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&target>; +- contribution = <1024>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&target>; +- contribution = <512>; +- cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- usb3_otg_bc: usb3_otg_bc@ff200000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x0 0xff200000 0x0 0x1000>; +- +- usb_phy: usb-phy { +- compatible = "hisilicon,hi3660-usb-phy"; +- #phy-cells = <0>; +- hisilicon,pericrg-syscon = <&crg_ctrl>; +- hisilicon,pctrl-syscon = <&pctrl>; +- hisilicon,eye-diagram-param = <0x22466e4>; +- }; +- }; +- +- dwc3: usb@ff100000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0xff100000 0x0 0x100000>; +- +- clocks = <&crg_ctrl HI3660_CLK_ABB_USB>, +- <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; +- clock-names = "ref", "bus_early"; +- +- assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; +- assigned-clock-rates = <229000000>; +- +- resets = <&crg_rst 0x90 8>, +- <&crg_rst 0x90 7>, +- <&crg_rst 0x90 6>, +- <&crg_rst 0x90 5>; +- +- interrupts = <0 159 4>, <0 161 4>; +- phys = <&usb_phy>; +- phy-names = "usb3-phy"; +- }; +- }; +-}; +- +-#include "hi3660-coresight.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/hi3670-hikey970.dts b/scripts/dtc/include-prefixes/arm64/hisilicon/hi3670-hikey970.dts +deleted file mode 100644 +index d8abf442ee7e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/hi3670-hikey970.dts ++++ /dev/null +@@ -1,448 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * dts file for Hisilicon HiKey970 Development Board +- * +- * Copyright (C) 2016, HiSilicon Ltd. +- * Copyright (C) 2018, Linaro Ltd. +- * +- */ +- +-/dts-v1/; +-#include +- +-#include "hi3670.dtsi" +-#include "hikey970-pinctrl.dtsi" +- +-/ { +- model = "HiKey970"; +- compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670"; +- +- aliases { +- mshc1 = &dwmmc1; +- mshc2 = &dwmmc2; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- serial5 = &uart5; +- serial6 = &uart6; /* console UART */ +- }; +- +- chosen { +- stdout-path = "serial6:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- /* expect bootloader to fill in this region */ +- reg = <0x0 0x0 0x0 0x0>; +- }; +- +- sd_1v8: regulator-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- sd_3v3: regulator-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- wlan_en: wlan-en-1-8v { +- compatible = "regulator-fixed"; +- regulator-name = "wlan-en-regulator"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- /* GPIO_051_WIFI_EN */ +- gpio = <&gpio6 3 0>; +- +- /* WLAN card specific delay */ +- startup-delay-us = <70000>; +- enable-active-high; +- }; +-}; +- +-/* +- * Legend: proper name = the GPIO line is used as GPIO +- * NC = not connected (pin out but not routed from the chip to +- * anything the board) +- * "[PER]" = pin is muxed for [peripheral] (not GPIO) +- * "" = no idea, schematic doesn't say, could be +- * unrouted (not connected to any external pin) +- * LSEC = Low Speed External Connector +- * HSEC = High Speed External Connector +- * +- * Line names are taken from "hikey970-schematics.pdf" from HiSilicon. +- * +- * For the lines routed to the external connectors the +- * lines are named after the 96Boards CE Specification 1.0, +- * Appendix "Expansion Connector Signal Description". +- * +- * When the 96Board naming of a line and the schematic name of +- * the same line are in conflict, the 96Board specification +- * takes precedence, which means that the external UART on the +- * LSEC is named UART0 while the schematic and SoC names this +- * UART2. This is only for the informational lines i.e. "[FOO]", +- * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only +- * ones actually used for GPIO. +- */ +-&gpio0 { +- /* GPIO_000-GPIO_007 */ +- gpio-line-names = +- "", +- "TP901", /* TEST_MODE connected to TP901 */ +- "", +- "GPIO_003_USB_HUB_RESET_N", +- "NC", +- "[AP_GPS_REF_CLK]", +- "[I2C3_SCL]", +- "[I2C3_SDA]"; +-}; +- +-&gpio1 { +- /* GPIO_008-GPIO_015 */ +- gpio-line-names = +- "[UART0_CTS]", /* LSEC pin 3: GPIO_008_UART2_CTS_N */ +- "[UART0_RTS]", /* LSEC pin 9: GPIO_009_UART2_RTS_N */ +- "[UART0_TXD]", /* LSEC pin 5: GPIO_010_UART2_TXD */ +- "[UART0_RXD]", /* LSEC pin 7: GPIO_011_UART2_RXD */ +- "[USER_LED5]", +- "GPIO-I", /* LSEC pin 31: GPIO_013_CAM0_RST_N */ +- "[USER_LED3]", +- "[USER_LED4]"; +-}; +- +-&gpio2 { +- /* GPIO_016-GPIO_023 */ +- gpio-line-names = +- "GPIO-G", /* LSEC pin 29: GPIO_016_LCD_TE0 */ +- "[CSI0_MCLK]", /* HSEC pin 15: ISP_CCLK0_MCAM */ +- "[CSI1_MCLK]", /* HSEC pin 17: ISP_CCLK1_SCAM */ +- "GPIO_019_BT_ACTIVE", +- "[I2C2_SCL]", /* HSEC pin 32: ISP_SCL0 */ +- "[I2C2_SDA]", /* HSEC pin 34: ISP_SDA0 */ +- "[I2C3_SCL]", /* HSEC pin 36: ISP_SCL1 */ +- "[I2C3_SDA]"; /* HSEC pin 38: ISP_SDA1 */ +-}; +- +-&gpio3 { +- /* GPIO_024-GPIO_031 */ +- gpio-line-names = +- "GPIO_024_WIFI_ACTIVE", +- "GPIO_025_PERST_M.2", +- "[I2C4_SCL]", +- "[I2C4_SDA]", +- "NC", +- "GPIO-H", /* LSEC pin 30: GPIO_029_LCD_RST_N */ +- "[USER_LED1]", +- "GPIO-L"; /* LSEC pin 34: GPIO_031 */ +-}; +- +-&gpio4 { +- /* GPIO_032-GPIO_039 */ +- gpio-line-names = +- "GPIO-K", /* LSEC pin 33: GPIO_032_CAM1_RST_N */ +- "GPIO_033_PMU1_EN", +- "GPIO_034_USBSW_SEL", +- /* +- * These two pins should be used for SD(IO) data according +- * to the 96boards specification but seems to be repurposed +- * for UART 0. They are however named according to the spec. +- */ +- "[SD_DAT1]", /* HSEC pin 3: GPIO_035_UART0_RXD */ +- "[SD_DAT2]", /* HSEC pin 5: GPIO_036_UART0_TXD */ +- "[UART1_RXD]", /* LSEC pin 13: DEBUG_UART6_RXD */ +- "[UART1_TXD]", /* LSEC pin 11: DEBUG_UART6_TXD */ +- "[SOC_GPS_UART3_CTS_N]"; /* TP2304 */ +-}; +- +-&gpio5 { +- /* GPIO_040-GPIO_047 */ +- gpio-line-names = +- "[SOC_GPS_UART3_RTS_N]", /* TP2302 */ +- "[SOC_GPS_UART3_RXD]", /* TP2303 */ +- "[SOC_GPS_UART3_TXD]", /* TP2305 */ +- "[SOC_BT_UART4_CTS_N]", +- "[SOC_BT_UART4_RTS_N]", +- "[SOC_BT_UART4_RXD]", +- "[SOC_BT_UART4_TXD]", +- "NC"; +-}; +- +-&gpio6 { +- /* GPIO_048-GPIO_055 */ +- gpio-line-names = +- "NC", +- "GPIO_049_USER_LED6", +- "GPIO_050_CAN_RST", +- "GPIO_051_WIFI_EN", +- "GPIO-D", /* LSEC pin 26 */ +- "GPIO-J", /* LSEC pin 32 */ +- "GPIO_054_BT_EN", +- "[GPIO_055_SEL]"; +-}; +- +-&gpio7 { +- /* GPIO_056-GPIO_063 */ +- gpio-line-names = +- "[PCIE_PERST_L]", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +-}; +- +-&gpio8 { +- /* GPIO_064-GPIO_071 */ +- gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +-}; +- +-&gpio9 { +- /* GPIO_072-GPIO_079 */ +- gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +-}; +- +-&gpio10 { +- /* GPIO_080-GPIO_087 */ +- gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +-}; +- +-&gpio11 { +- /* GPIO_088-GPIO_095 */ +- gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +-}; +- +-&gpio12 { +- /* GPIO_096-GPIO_103 */ +- gpio-line-names = "NC", "", "", "", "", "", "", ""; +-}; +- +-&gpio13 { +- /* GPIO_104-GPIO_111 */ +- gpio-line-names = "", "", "", "", "", "", "", ""; +-}; +- +-&gpio14 { +- /* GPIO_112-GPIO_119 */ +- gpio-line-names = "", "", "", "", "", "", "", ""; +-}; +- +-&gpio15 { +- /* GPIO_120-GPIO_127 */ +- gpio-line-names = "", "", "", "", "", "", "", ""; +-}; +- +-&gpio16 { +- /* GPIO_128-GPIO_135 */ +- gpio-line-names = +- "[WL_SDIO_CLK]", +- "[WL_SDIO_CMD]", +- "[WL_SDIO_DATA0]", +- "[WL_SDIO_DATA1]", +- "[WL_SDIO_DATA2]", +- "[WL_SDIO_DATA3]", +- "[ETH_ISOLATE]", +- "NC"; +-}; +- +-&gpio17 { +- /* GPIO_136-GPIO_143 */ +- gpio-line-names = +- "[MINI1CLK_EN]", "NC", "", "", "", "", "", ""; +-}; +- +-&gpio18 { +- /* GPIO_144-GPIO_151 */ +- gpio-line-names = +- "[SPI1_SCLK]", /* HSEC pin 9: GPIO_144_SPI3_CLK */ +- "[SPI1_DIN]", /* HSEC pin 11: GPIO_145_SPI3_DI */ +- "[SPI1_DOUT]", /* HSEC pin 1: GPIO_146_SPI3_DO */ +- "[SPI1_CS]", /* HSEC pin 7: GPIO_147_SPI3_CS0_N */ +- "[POWER_INT_N]", +- "[CDMA_GPS_SYNC]", +- "GPIO_150_PEX_INTA", +- "GPIO_151_CAN_INT"; +-}; +- +-&gpio19 { +- /* GPIO_152-GPIO_159 */ +- gpio-line-names = "", "", "", "", "", "", "", ""; +-}; +- +-&gpio20 { +- /* GPIO_160-GPIO_167 */ +- gpio-line-names = +- "[SD_CLK]", +- "[SD_CMD]", +- "[SD_DATA0]", +- "[SD_DATA1]", +- "[SD_DATA2]", +- "[SD_DATA3]", +- "GPIO_166_ETHCLK_EN", +- "GPIO_167_USER_LED2"; +-}; +- +-&gpio21 { +- /* GPIO_168-GPIO_175 */ +- gpio-line-names = +- "GPIO_168_GPS_EN", +- "GPIO-C", /* LSEC pin 25: GPIO_169_USIM1_CLK */ +- "GPIO-E", /* LSEC pin 27: GPIO_170_USIM1_RST */ +- "GPIO-B", /* LSEC pin 24: GPIO_171_USIM1_DATA */ +- "", "", "", "", ""; +-}; +- +-&gpio22 { +- /* GPIO_176-GPIO_183 */ +- gpio-line-names = +- "[PMU_PWR_HOLD]", +- "GPIO_177_WL_WAKEUP_AP", +- "[JTAG_TCK]", +- "[JTAG_TMS]", +- "[JTAG_TDI]", +- "[JTAG_TMS]", +- "GPIO_182_FATAL_ERR", +- "NC"; +-}; +- +-&gpio23 { +- /* GPIO_184-GPIO_191 */ +- gpio-line-names = +- "GPIO_184_JTAG_SEL", +- "GPIO-F", /* LSEC pin 28: GPIO_185_LCD_BL_PWM */ +- "[I2C0_SCL]", /* LSEC pin 15: GPIO_186_I2C0_SCL */ +- "[I2C0_SDA]", /* LSEC pin 17: GPIO_187_I2C0_SDA */ +- "[GPIO_188_I2C1_SCL]", /* Actual SoC I2C1_SCL */ +- "[GPIO_189_I2C1_SDA]", /* Actual SoC I2C1_SDA */ +- "[I2C1_SCL]", /* LSEC pin 19: GPIO_190_I2C2_SCL */ +- "[I2C2_SDA]"; /* LSEC pin 21: GPIO_191_I2C2_SDA */ +-}; +- +-&gpio24 { +- /* GPIO_192-GPIO_199 */ +- gpio-line-names = +- "[SD_LED]", +- "NC", +- "[PCM_DI]", /* LSEC pin 22: GPIO_194_I2S0_DI */ +- "[PCM_DO]", /* LSEC pin 20: GPIO_195_I2S0_DO */ +- "[PCM_CLK]", /* LSEC pin 18: GPIO_196_I2S0_XCLK */ +- "[PCM_FS]", /* LSEC pin 16: GPIO_197_I2S0_XFS */ +- "", +- "[I2S2_DO]"; +-}; +- +-&gpio25 { +- /* GPIO_200-GPIO_207 */ +- gpio-line-names = +- "[I2S2_XCLK]", +- "[I2S2_XFS]", +- "GPIO_202_PERST_ETH", +- "GPIO_203_PWRON_DET", +- "GPIO_204_PMU1_IRQ_N", +- "GPIO_205_SD_DET", +- "GPIO_206_GPS_MOTION_INT", +- "GPIO_207_HDMI_SEL"; +-}; +- +-&gpio26 { +- /* GPIO_208-GPIO_215 */ +- gpio-line-names = +- "GPIO-A", /* LSEC pin 23: GPIO_208_WAKEUP_SOC */ +- "GPIO_209_VBUS_TYPEC", +- "NC", +- "NC", +- "NC", +- "[SPI0_SCLK]", /* LSEC pin 8: GPIO_213_SPI2_CLK */ +- "[SPI0_DIN]", /* LSEC pin 10: GPIO_214_SPI2_DI */ +- "[SPI0_DOUT]"; /* LSEC pin 14: GPIO_215_SPI2_DO */ +-}; +- +-&gpio27 { +- /* GPIO_216-GPIO_223 */ +- gpio-line-names = +- "[SPI0_CS]", /* LSEC pin 12: GPIO_216_SPI2_CS0_N */ +- "GPIO_217_HDMI_PD", +- "GPIO_218_GPS_WAKEUP_AP", +- "GPIO_219_M.2CLK_EN", +- "GPIO_220_PERST_MINI", +- "GPIO_221_CC_INT", +- "[PCIE_CLKREQ_L]", +- "NC"; +-}; +- +-&gpio28 { +- /* GPIO_224-GPIO_231 */ +- gpio-line-names = +- "[PMU0_INT]", +- "[SPMI_DATA]", +- "[SPMI_CLK]", +- "[CAN_SPI_CLK]", +- "[CAN_SPI_DI]", +- "[CAN_SPI_DO]", +- "[CAN_SPI_CS]", +- "GPIO_231_HDMI_INT"; +-}; +- +-&dwmmc1 { +- bus-width = <0x4>; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- cap-sd-highspeed; +- disable-wp; +- cd-inverted; +- cd-gpios = <&gpio25 5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd_pmx_func +- &sd_clk_cfg_func +- &sd_cfg_func>; +- vmmc-supply = <&sd_3v3>; +- vqmmc-supply = <&sd_1v8>; +- status = "okay"; +-}; +- +-&dwmmc2 { /* WIFI */ +- bus-width = <0x4>; +- non-removable; +- broken-cd; +- cap-power-off-card; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio_pmx_func +- &sdio_clk_cfg_func +- &sdio_cfg_func>; +- /* WL_EN */ +- vmmc-supply = <&wlan_en>; +- status = "okay"; +- +- wlcore: wlcore@2 { +- compatible = "ti,wl1837"; +- reg = <2>; /* sdio func num */ +- /* WL_IRQ, GPIO_177_WL_WAKEUP_AP */ +- interrupt-parent = <&gpio22>; +- interrupts = <1 IRQ_TYPE_EDGE_RISING>; +- }; +-}; +- +-&uart0 { +- /* On High speed expansion header */ +- label = "HS-UART0"; +- status = "okay"; +-}; +- +-&uart2 { +- /* On Low speed expansion header */ +- label = "LS-UART0"; +- status = "okay"; +-}; +- +-&uart6 { +- /* On Low speed expansion header */ +- label = "LS-UART1"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/hi3670.dtsi b/scripts/dtc/include-prefixes/arm64/hisilicon/hi3670.dtsi +deleted file mode 100644 +index 20698cfd0637..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/hi3670.dtsi ++++ /dev/null +@@ -1,789 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * dts file for Hisilicon Hi3670 SoC +- * +- * Copyright (C) 2016, HiSilicon Ltd. +- * Copyright (C) 2018, Linaro Ltd. +- */ +- +-#include +-#include +- +-/ { +- compatible = "hisilicon,hi3670"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- core2 { +- cpu = <&cpu2>; +- }; +- core3 { +- cpu = <&cpu3>; +- }; +- }; +- cluster1 { +- core0 { +- cpu = <&cpu4>; +- }; +- core1 { +- cpu = <&cpu5>; +- }; +- core2 { +- cpu = <&cpu6>; +- }; +- core3 { +- cpu = <&cpu7>; +- }; +- }; +- }; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- }; +- +- cpu4: cpu@100 { +- compatible = "arm,cortex-a73"; +- device_type = "cpu"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- }; +- +- cpu5: cpu@101 { +- compatible = "arm,cortex-a73"; +- device_type = "cpu"; +- reg = <0x0 0x101>; +- enable-method = "psci"; +- }; +- +- cpu6: cpu@102 { +- compatible = "arm,cortex-a73"; +- device_type = "cpu"; +- reg = <0x0 0x102>; +- enable-method = "psci"; +- }; +- +- cpu7: cpu@103 { +- compatible = "arm,cortex-a73"; +- device_type = "cpu"; +- reg = <0x0 0x103>; +- enable-method = "psci"; +- }; +- }; +- +- gic: interrupt-controller@e82b0000 { +- compatible = "arm,gic-400"; +- reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ +- <0x0 0xe82b2000 0 0x2000>, /* GICC */ +- <0x0 0xe82b4000 0 0x2000>, /* GICH */ +- <0x0 0xe82b6000 0 0x2000>; /* GICV */ +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupts = ; +- interrupt-controller; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- clock-frequency = <1920000>; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- crg_ctrl: crg_ctrl@fff35000 { +- compatible = "hisilicon,hi3670-crgctrl", "syscon"; +- reg = <0x0 0xfff35000 0x0 0x1000>; +- #clock-cells = <1>; +- }; +- +- crg_rst: crg_rst_controller { +- compatible = "hisilicon,hi3670-reset", +- "hisilicon,hi3660-reset"; +- #reset-cells = <2>; +- hisi,rst-syscon = <&crg_ctrl>; +- }; +- +- pctrl: pctrl@e8a09000 { +- compatible = "hisilicon,hi3670-pctrl", "syscon"; +- reg = <0x0 0xe8a09000 0x0 0x1000>; +- #clock-cells = <1>; +- }; +- +- pmuctrl: crg_ctrl@fff34000 { +- compatible = "hisilicon,hi3670-pmuctrl", "syscon"; +- reg = <0x0 0xfff34000 0x0 0x1000>; +- #clock-cells = <1>; +- }; +- +- sctrl: sctrl@fff0a000 { +- compatible = "hisilicon,hi3670-sctrl", "syscon"; +- reg = <0x0 0xfff0a000 0x0 0x1000>; +- #clock-cells = <1>; +- }; +- +- iomcu: iomcu@ffd7e000 { +- compatible = "hisilicon,hi3670-iomcu", "syscon"; +- reg = <0x0 0xffd7e000 0x0 0x1000>; +- #clock-cells = <1>; +- }; +- +- media1_crg: media1_crgctrl@e87ff000 { +- compatible = "hisilicon,hi3670-media1-crg", "syscon"; +- reg = <0x0 0xe87ff000 0x0 0x1000>; +- #clock-cells = <1>; +- }; +- +- media2_crg: media2_crgctrl@e8900000 { +- compatible = "hisilicon,hi3670-media2-crg","syscon"; +- reg = <0x0 0xe8900000 0x0 0x1000>; +- #clock-cells = <1>; +- }; +- +- iomcu_rst: reset { +- compatible = "hisilicon,hi3660-reset"; +- hisi,rst-syscon = <&iomcu>; +- #reset-cells = <2>; +- }; +- +- uart0: serial@fdf02000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xfdf02000 0x0 0x1000>; +- interrupts = ; +- clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>, +- <&crg_ctrl HI3670_PCLK>; +- clock-names = "uartclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; +- status = "disabled"; +- }; +- +- uart1: serial@fdf00000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xfdf00000 0x0 0x1000>; +- interrupts = ; +- clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>, +- <&crg_ctrl HI3670_PCLK>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- uart2: serial@fdf03000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xfdf03000 0x0 0x1000>; +- interrupts = ; +- clocks = <&crg_ctrl HI3670_CLK_GATE_UART2>, +- <&crg_ctrl HI3670_PCLK>; +- clock-names = "uartclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; +- status = "disabled"; +- }; +- +- uart3: serial@ffd74000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xffd74000 0x0 0x1000>; +- interrupts = ; +- clocks = <&crg_ctrl HI3670_CLK_GATE_UART3>, +- <&crg_ctrl HI3670_PCLK>; +- clock-names = "uartclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; +- status = "disabled"; +- }; +- +- uart4: serial@fdf01000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xfdf01000 0x0 0x1000>; +- interrupts = ; +- clocks = <&crg_ctrl HI3670_CLK_GATE_UART4>, +- <&crg_ctrl HI3670_PCLK>; +- clock-names = "uartclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; +- status = "disabled"; +- }; +- +- uart5: serial@fdf05000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xfdf05000 0x0 0x1000>; +- interrupts = ; +- clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>, +- <&crg_ctrl HI3670_PCLK>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- uart6: serial@fff32000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xfff32000 0x0 0x1000>; +- interrupts = ; +- clocks = <&crg_ctrl HI3670_CLK_UART6>, +- <&crg_ctrl HI3670_PCLK>; +- clock-names = "uartclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e8a0b000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a0b000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 1 0 1 &pmx0 3 1 5>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO0>; +- clock-names = "apb_pclk"; +- }; +- +- gpio1: gpio@e8a0c000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a0c000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO1>; +- clock-names = "apb_pclk"; +- }; +- +- gpio2: gpio@e8a0d000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a0d000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 1 6 7>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio3: gpio@e8a0e000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a0e000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO3>; +- clock-names = "apb_pclk"; +- }; +- +- gpio4: gpio@e8a0f000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a0f000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 18 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO4>; +- clock-names = "apb_pclk"; +- }; +- +- gpio5: gpio@e8a10000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a10000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 26 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO5>; +- clock-names = "apb_pclk"; +- }; +- +- gpio6: gpio@e8a11000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a11000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 1 34 7>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO6>; +- clock-names = "apb_pclk"; +- }; +- +- gpio7: gpio@e8a12000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a12000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 41 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO7>; +- clock-names = "apb_pclk"; +- }; +- +- gpio8: gpio@e8a13000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a13000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 49 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO8>; +- clock-names = "apb_pclk"; +- }; +- +- gpio9: gpio@e8a14000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a14000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 57 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO9>; +- clock-names = "apb_pclk"; +- }; +- +- gpio10: gpio@e8a15000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a15000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 65 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO10>; +- clock-names = "apb_pclk"; +- }; +- +- gpio11: gpio@e8a16000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a16000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 73 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO11>; +- clock-names = "apb_pclk"; +- }; +- +- gpio12: gpio@e8a17000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a17000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 81 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO12>; +- clock-names = "apb_pclk"; +- }; +- +- gpio13: gpio@e8a18000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a18000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO13>; +- clock-names = "apb_pclk"; +- }; +- +- gpio14: gpio@e8a19000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a19000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO14>; +- clock-names = "apb_pclk"; +- }; +- +- gpio15: gpio@e8a1a000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a1a000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO15>; +- clock-names = "apb_pclk"; +- }; +- +- gpio16: gpio@e8a1b000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a1b000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx5 0 0 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO16>; +- clock-names = "apb_pclk"; +- }; +- +- gpio17: gpio@e8a1c000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a1c000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx5 0 8 2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO17>; +- clock-names = "apb_pclk"; +- }; +- +- gpio18: gpio@fff28000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xfff28000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx1 4 42 4>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&sctrl HI3670_PCLK_GPIO18>; +- clock-names = "apb_pclk"; +- }; +- +- gpio19: gpio@fff29000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xfff29000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx1 0 61 2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&sctrl HI3670_PCLK_GPIO19>; +- clock-names = "apb_pclk"; +- }; +- +- gpio20: gpio@e8a1f000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a1f000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx7 0 0 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO20>; +- clock-names = "apb_pclk"; +- }; +- +- gpio21: gpio@e8a20000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xe8a20000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx7 0 8 4>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg_ctrl HI3670_PCLK_GPIO21>; +- clock-names = "apb_pclk"; +- }; +- +- gpio22: gpio@fff0b000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xfff0b000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- /* GPIO176 */ +- gpio-ranges = <&pmx1 2 0 6>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&sctrl HI3670_PCLK_AO_GPIO0>; +- clock-names = "apb_pclk"; +- }; +- +- gpio23: gpio@fff0c000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xfff0c000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- /* GPIO184 */ +- gpio-ranges = <&pmx1 0 6 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&sctrl HI3670_PCLK_AO_GPIO1>; +- clock-names = "apb_pclk"; +- }; +- +- gpio24: gpio@fff0d000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xfff0d000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- /* GPIO192 */ +- gpio-ranges = <&pmx1 0 14 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&sctrl HI3670_PCLK_AO_GPIO2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio25: gpio@fff0e000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xfff0e000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- /* GPIO200 */ +- gpio-ranges = <&pmx1 0 22 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&sctrl HI3670_PCLK_AO_GPIO3>; +- clock-names = "apb_pclk"; +- }; +- +- gpio26: gpio@fff0f000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xfff0f000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- /* GPIO208 */ +- gpio-ranges = <&pmx1 0 30 1>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&sctrl HI3670_PCLK_AO_GPIO4>; +- clock-names = "apb_pclk"; +- }; +- +- gpio27: gpio@fff10000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xfff10000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- /* GPIO216 */ +- gpio-ranges = <&pmx1 4 31 4>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&sctrl HI3670_PCLK_AO_GPIO5>; +- clock-names = "apb_pclk"; +- }; +- +- gpio28: gpio@fff1d000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xfff1d000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx1 1 35 7>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&sctrl HI3670_PCLK_AO_GPIO6>; +- clock-names = "apb_pclk"; +- }; +- +- /* UFS */ +- ufs: ufs@ff3c0000 { +- compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1"; +- /* 0: HCI standard */ +- /* 1: UFS SYS CTRL */ +- reg = <0x0 0xff3c0000 0x0 0x1000>, +- <0x0 0xff3e0000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = ; +- clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>, +- <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>; +- clock-names = "ref_clk", "phy_clk"; +- freq-table-hz = <0 0 +- 0 0>; +- /* offset: 0x84; bit: 12 */ +- resets = <&crg_rst 0x84 12>; +- reset-names = "rst"; +- }; +- +- /* SD */ +- dwmmc1: dwmmc1@ff37f000 { +- compatible = "hisilicon,hi3670-dw-mshc", +- "hisilicon,hi3660-dw-mshc"; +- reg = <0x0 0xff37f000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&crg_ctrl HI3670_CLK_GATE_SD>, +- <&crg_ctrl HI3670_HCLK_GATE_SD>; +- clock-names = "ciu", "biu"; +- clock-frequency = <3200000>; +- resets = <&crg_rst 0x94 18>; +- reset-names = "reset"; +- hisilicon,peripheral-syscon = <&sctrl>; +- card-detect-delay = <200>; +- status = "disabled"; +- }; +- +- /* SDIO */ +- dwmmc2: dwmmc2@fc183000 { +- compatible = "hisilicon,hi3670-dw-mshc", +- "hisilicon,hi3660-dw-mshc"; +- reg = <0x0 0xfc183000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&crg_ctrl HI3670_CLK_GATE_SDIO>, +- <&crg_ctrl HI3670_HCLK_GATE_SDIO>; +- clock-names = "ciu", "biu"; +- clock-frequency = <3200000>; +- resets = <&crg_rst 0x94 20>; +- reset-names = "reset"; +- card-detect-delay = <200>; +- status = "disabled"; +- }; +- +- /* I2C */ +- i2c0: i2c@ffd71000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0xffd71000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <400000>; +- clocks = <&iomcu HI3670_CLK_GATE_I2C0>; +- resets = <&iomcu_rst 0x20 3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; +- status = "disabled"; +- }; +- +- i2c1: i2c@ffd72000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0xffd72000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <400000>; +- clocks = <&iomcu HI3670_CLK_GATE_I2C1>; +- resets = <&iomcu_rst 0x20 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; +- status = "disabled"; +- }; +- +- i2c2: i2c@ffd73000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0xffd73000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <400000>; +- clocks = <&iomcu HI3670_CLK_GATE_I2C2>; +- resets = <&iomcu_rst 0x20 5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; +- status = "disabled"; +- }; +- +- i2c3: i2c@fdf0c000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0xfdf0c000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <400000>; +- clocks = <&crg_ctrl HI3670_CLK_GATE_I2C3>; +- resets = <&crg_rst 0x78 7>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; +- status = "disabled"; +- }; +- +- i2c4: i2c@fdf0d000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0xfdf0d000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-frequency = <400000>; +- clocks = <&crg_ctrl HI3670_CLK_GATE_I2C4>; +- resets = <&crg_rst 0x78 27>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pmx_func &i2c4_cfg_func>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/hi3798cv200-poplar.dts b/scripts/dtc/include-prefixes/arm64/hisilicon/hi3798cv200-poplar.dts +deleted file mode 100644 +index 7d370dac4c85..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/hi3798cv200-poplar.dts ++++ /dev/null +@@ -1,206 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * DTS File for HiSilicon Poplar Development Board +- * +- * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. +- */ +- +-/dts-v1/; +- +-#include +-#include "hi3798cv200.dtsi" +-#include "poplar-pinctrl.dtsi" +- +-/ { +- model = "HiSilicon Poplar Development Board"; +- compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; +- +- aliases { +- serial0 = &uart0; +- serial2 = &uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- user-led0 { +- label = "green:user1"; +- gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- +- user-led1 { +- label = "green:user2"; +- gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- +- user-led2 { +- label = "green:user3"; +- gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "mmc1"; +- default-state = "off"; +- }; +- +- user-led3 { +- label = "green:user4"; +- gpios = <&gpio10 6 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "none"; +- panic-indicator; +- default-state = "off"; +- }; +- }; +- +- reg_pcie: regulator-pcie { +- compatible = "regulator-fixed"; +- regulator-name = "3V3_PCIE0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio6 7 0>; +- enable-active-high; +- }; +-}; +- +-&ehci { +- status = "okay"; +-}; +- +-&emmc { +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_pins_1 &emmc_pins_2 +- &emmc_pins_3 &emmc_pins_4>; +- fifo-depth = <256>; +- clock-frequency = <200000000>; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- non-removable; +- bus-width = <8>; +- status = "okay"; +-}; +- +-&gmac1 { +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- phy-handle = <ð_phy1>; +- phy-mode = "rgmii"; +- hisilicon,phy-reset-delays-us = <10000 10000 30000>; +- +- eth_phy1: phy@3 { +- reg = <3>; +- }; +-}; +- +-&gpio1 { +- status = "okay"; +- gpio-line-names = "GPIO-E", "", +- "", "", +- "", "GPIO-F", +- "", "GPIO-J"; +-}; +- +-&gpio2 { +- status = "okay"; +- gpio-line-names = "GPIO-H", "GPIO-I", +- "GPIO-L", "GPIO-G", +- "GPIO-K", "", +- "", ""; +-}; +- +-&gpio3 { +- status = "okay"; +- gpio-line-names = "", "", +- "", "", +- "GPIO-C", "", +- "", "GPIO-B"; +-}; +- +-&gpio4 { +- status = "okay"; +- gpio-line-names = "", "", +- "", "", +- "", "GPIO-D", +- "", ""; +-}; +- +-&gpio5 { +- status = "okay"; +- gpio-line-names = "", "USER-LED-1", +- "USER-LED-2", "", +- "", "GPIO-A", +- "", ""; +-}; +- +-&gpio6 { +- status = "okay"; +- gpio-line-names = "", "", +- "", "USER-LED-0", +- "", "", +- "", ""; +-}; +- +-&gpio10 { +- status = "okay"; +- gpio-line-names = "", "", +- "", "", +- "", "", +- "USER-LED-3", ""; +-}; +- +-&i2c0 { +- status = "okay"; +- label = "LS-I2C0"; +-}; +- +-&i2c2 { +- status = "okay"; +- label = "LS-I2C1"; +-}; +- +-&ir { +- linux,rc-map-name = "rc-hisi-poplar"; +- status = "okay"; +-}; +- +-&ohci { +- status = "okay"; +-}; +- +-&pcie { +- reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; +- vpcie-supply = <®_pcie>; +- status = "okay"; +-}; +- +-&sd0 { +- bus-width = <4>; +- cap-sd-highspeed; +- status = "okay"; +-}; +- +-&spi0 { +- status = "okay"; +- label = "LS-SPI0"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +- label = "LS-UART0"; +-}; +-/* No optional LS-UART1 on Low Speed Expansion Connector. */ +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/hi3798cv200.dtsi b/scripts/dtc/include-prefixes/arm64/hisilicon/hi3798cv200.dtsi +deleted file mode 100644 +index a83b9d4f172e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/hi3798cv200.dtsi ++++ /dev/null +@@ -1,619 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * DTS File for HiSilicon Hi3798cv200 SoC. +- * +- * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "hisilicon,hi3798cv200"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- }; +- +- cpu@1 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- }; +- +- cpu@2 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- }; +- +- cpu@3 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- }; +- }; +- +- gic: interrupt-controller@f1001000 { +- compatible = "arm,gic-400"; +- reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ +- <0x0 0xf1002000 0x0 0x100>; /* GICC */ +- #address-cells = <0>; +- #interrupt-cells = <3>; +- interrupt-controller; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- soc: soc@f0000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0xf0000000 0x10000000>; +- +- crg: clock-reset-controller@8a22000 { +- compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd"; +- reg = <0x8a22000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <2>; +- +- gmacphyrst: reset-controller { +- compatible = "ti,syscon-reset"; +- #reset-cells = <1>; +- ti,reset-bits = < +- 0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE) +- 0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE) +- >; +- }; +- }; +- +- sysctrl: system-controller@8000000 { +- compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; +- reg = <0x8000000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <2>; +- }; +- +- perictrl: peripheral-controller@8a20000 { +- compatible = "hisilicon,hi3798cv200-perictrl", "syscon", +- "simple-mfd"; +- reg = <0x8a20000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x8a20000 0x1000>; +- +- usb2_phy1: usb2_phy@120 { +- compatible = "hisilicon,hi3798cv200-usb2-phy"; +- reg = <0x120 0x4>; +- clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; +- resets = <&crg 0xbc 4>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- usb2_phy1_port0: phy@0 { +- reg = <0>; +- #phy-cells = <0>; +- resets = <&crg 0xbc 8>; +- }; +- +- usb2_phy1_port1: phy@1 { +- reg = <1>; +- #phy-cells = <0>; +- resets = <&crg 0xbc 9>; +- }; +- }; +- +- usb2_phy2: usb2_phy@124 { +- compatible = "hisilicon,hi3798cv200-usb2-phy"; +- reg = <0x124 0x4>; +- clocks = <&crg HISTB_USB2_PHY2_REF_CLK>; +- resets = <&crg 0xbc 6>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- usb2_phy2_port0: phy@0 { +- reg = <0>; +- #phy-cells = <0>; +- resets = <&crg 0xbc 10>; +- }; +- }; +- +- combphy0: phy@850 { +- compatible = "hisilicon,hi3798cv200-combphy"; +- reg = <0x850 0x8>; +- #phy-cells = <1>; +- clocks = <&crg HISTB_COMBPHY0_CLK>; +- resets = <&crg 0x188 4>; +- assigned-clocks = <&crg HISTB_COMBPHY0_CLK>; +- assigned-clock-rates = <100000000>; +- hisilicon,fixed-mode = ; +- }; +- +- combphy1: phy@858 { +- compatible = "hisilicon,hi3798cv200-combphy"; +- reg = <0x858 0x8>; +- #phy-cells = <1>; +- clocks = <&crg HISTB_COMBPHY1_CLK>; +- resets = <&crg 0x188 12>; +- assigned-clocks = <&crg HISTB_COMBPHY1_CLK>; +- assigned-clock-rates = <100000000>; +- hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>; +- }; +- }; +- +- pmx0: pinconf@8a21000 { +- compatible = "pinconf-single"; +- reg = <0x8a21000 0x180>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <7>; +- pinctrl-single,gpio-range = < +- &range 0 8 2 /* GPIO 0 */ +- &range 8 1 0 /* GPIO 1 */ +- &range 9 4 2 +- &range 13 1 0 +- &range 14 1 1 +- &range 15 1 0 +- &range 16 5 0 /* GPIO 2 */ +- &range 21 3 1 +- &range 24 4 1 /* GPIO 3 */ +- &range 28 2 2 +- &range 86 1 1 +- &range 87 1 0 +- &range 30 4 2 /* GPIO 4 */ +- &range 34 3 0 +- &range 37 1 2 +- &range 38 3 2 /* GPIO 6 */ +- &range 41 5 0 +- &range 46 8 1 /* GPIO 7 */ +- &range 54 8 1 /* GPIO 8 */ +- &range 64 7 1 /* GPIO 9 */ +- &range 71 1 0 +- &range 72 6 1 /* GPIO 10 */ +- &range 78 1 0 +- &range 79 1 1 +- &range 80 6 1 /* GPIO 11 */ +- &range 70 2 1 +- &range 88 8 0 /* GPIO 12 */ +- >; +- +- range: gpio-range { +- #pinctrl-single,gpio-range-cells = <3>; +- }; +- }; +- +- uart0: serial@8b00000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x8b00000 0x1000>; +- interrupts = ; +- clocks = <&sysctrl HISTB_UART0_CLK>, <&sysctrl HISTB_UART0_CLK>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- uart2: serial@8b02000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x8b02000 0x1000>; +- interrupts = ; +- clocks = <&crg HISTB_UART2_CLK>, <&crg HISTB_UART2_CLK>; +- clock-names = "uartclk", "apb_pclk"; +- status = "disabled"; +- }; +- +- i2c0: i2c@8b10000 { +- compatible = "hisilicon,hix5hd2-i2c"; +- reg = <0x8b10000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clock-frequency = <400000>; +- clocks = <&crg HISTB_I2C0_CLK>; +- status = "disabled"; +- }; +- +- i2c1: i2c@8b11000 { +- compatible = "hisilicon,hix5hd2-i2c"; +- reg = <0x8b11000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clock-frequency = <400000>; +- clocks = <&crg HISTB_I2C1_CLK>; +- status = "disabled"; +- }; +- +- i2c2: i2c@8b12000 { +- compatible = "hisilicon,hix5hd2-i2c"; +- reg = <0x8b12000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clock-frequency = <400000>; +- clocks = <&crg HISTB_I2C2_CLK>; +- status = "disabled"; +- }; +- +- i2c3: i2c@8b13000 { +- compatible = "hisilicon,hix5hd2-i2c"; +- reg = <0x8b13000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clock-frequency = <400000>; +- clocks = <&crg HISTB_I2C3_CLK>; +- status = "disabled"; +- }; +- +- i2c4: i2c@8b14000 { +- compatible = "hisilicon,hix5hd2-i2c"; +- reg = <0x8b14000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clock-frequency = <400000>; +- clocks = <&crg HISTB_I2C4_CLK>; +- status = "disabled"; +- }; +- +- spi0: spi@8b1a000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x8b1a000 0x1000>; +- interrupts = ; +- num-cs = <1>; +- cs-gpios = <&gpio7 1 0>; +- clocks = <&crg HISTB_SPI0_CLK>, <&crg HISTB_SPI0_CLK>; +- clock-names = "sspclk", "apb_pclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- sd0: mmc@9820000 { +- compatible = "snps,dw-mshc"; +- reg = <0x9820000 0x10000>; +- interrupts = ; +- clocks = <&crg HISTB_SDIO0_CIU_CLK>, +- <&crg HISTB_SDIO0_BIU_CLK>; +- clock-names = "biu", "ciu"; +- resets = <&crg 0x9c 4>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- emmc: mmc@9830000 { +- compatible = "hisilicon,hi3798cv200-dw-mshc"; +- reg = <0x9830000 0x10000>; +- interrupts = ; +- clocks = <&crg HISTB_MMC_CIU_CLK>, +- <&crg HISTB_MMC_BIU_CLK>, +- <&crg HISTB_MMC_SAMPLE_CLK>, +- <&crg HISTB_MMC_DRV_CLK>; +- clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; +- resets = <&crg 0xa0 4>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- gpio0: gpio@8b20000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x8b20000 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&pmx0 0 0 8>; +- clocks = <&crg HISTB_APB_CLK>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- gpio1: gpio@8b21000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x8b21000 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = < +- &pmx0 0 8 1 +- &pmx0 1 9 4 +- &pmx0 5 13 1 +- &pmx0 6 14 1 +- &pmx0 7 15 1 +- >; +- clocks = <&crg HISTB_APB_CLK>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- gpio2: gpio@8b22000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x8b22000 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>; +- clocks = <&crg HISTB_APB_CLK>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- gpio3: gpio@8b23000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x8b23000 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = < +- &pmx0 0 24 4 +- &pmx0 4 28 2 +- &pmx0 6 86 1 +- &pmx0 7 87 1 +- >; +- clocks = <&crg HISTB_APB_CLK>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- gpio4: gpio@8b24000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x8b24000 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>; +- clocks = <&crg HISTB_APB_CLK>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- gpio5: gpio@8004000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x8004000 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&crg HISTB_APB_CLK>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- gpio6: gpio@8b26000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x8b26000 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>; +- clocks = <&crg HISTB_APB_CLK>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- gpio7: gpio@8b27000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x8b27000 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&pmx0 0 46 8>; +- clocks = <&crg HISTB_APB_CLK>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- gpio8: gpio@8b28000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x8b28000 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&pmx0 0 54 8>; +- clocks = <&crg HISTB_APB_CLK>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- gpio9: gpio@8b29000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x8b29000 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>; +- clocks = <&crg HISTB_APB_CLK>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- gpio10: gpio@8b2a000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x8b2a000 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>; +- clocks = <&crg HISTB_APB_CLK>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- gpio11: gpio@8b2b000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x8b2b000 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>; +- clocks = <&crg HISTB_APB_CLK>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- gpio12: gpio@8b2c000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x8b2c000 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&pmx0 0 88 8>; +- clocks = <&crg HISTB_APB_CLK>; +- clock-names = "apb_pclk"; +- status = "disabled"; +- }; +- +- gmac0: ethernet@9840000 { +- compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; +- reg = <0x9840000 0x1000>, +- <0x984300c 0x4>; +- interrupts = ; +- clocks = <&crg HISTB_ETH0_MAC_CLK>, +- <&crg HISTB_ETH0_MACIF_CLK>; +- clock-names = "mac_core", "mac_ifc"; +- resets = <&crg 0xcc 8>, +- <&crg 0xcc 10>, +- <&gmacphyrst 0>; +- reset-names = "mac_core", "mac_ifc", "phy"; +- status = "disabled"; +- }; +- +- gmac1: ethernet@9841000 { +- compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; +- reg = <0x9841000 0x1000>, +- <0x9843010 0x4>; +- interrupts = ; +- clocks = <&crg HISTB_ETH1_MAC_CLK>, +- <&crg HISTB_ETH1_MACIF_CLK>; +- clock-names = "mac_core", "mac_ifc"; +- resets = <&crg 0xcc 9>, +- <&crg 0xcc 11>, +- <&gmacphyrst 1>; +- reset-names = "mac_core", "mac_ifc", "phy"; +- status = "disabled"; +- }; +- +- ir: ir@8001000 { +- compatible = "hisilicon,hix5hd2-ir"; +- reg = <0x8001000 0x1000>; +- interrupts = ; +- clocks = <&sysctrl HISTB_IR_CLK>; +- status = "disabled"; +- }; +- +- pcie: pcie@9860000 { +- compatible = "hisilicon,hi3798cv200-pcie"; +- reg = <0x9860000 0x1000>, +- <0x0 0x2000>, +- <0x2000000 0x01000000>; +- reg-names = "control", "rc-dbi", "config"; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- bus-range = <0x00 0xff>; +- num-lanes = <1>; +- ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000>, +- <0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>; +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&crg HISTB_PCIE_AUX_CLK>, +- <&crg HISTB_PCIE_PIPE_CLK>, +- <&crg HISTB_PCIE_SYS_CLK>, +- <&crg HISTB_PCIE_BUS_CLK>; +- clock-names = "aux", "pipe", "sys", "bus"; +- resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>; +- reset-names = "soft", "sys", "bus"; +- phys = <&combphy1 PHY_TYPE_PCIE>; +- phy-names = "phy"; +- status = "disabled"; +- }; +- +- ohci: usb@9880000 { +- compatible = "generic-ohci"; +- reg = <0x9880000 0x10000>; +- interrupts = ; +- clocks = <&crg HISTB_USB2_BUS_CLK>, +- <&crg HISTB_USB2_12M_CLK>, +- <&crg HISTB_USB2_48M_CLK>; +- clock-names = "bus", "clk12", "clk48"; +- resets = <&crg 0xb8 12>; +- reset-names = "bus"; +- phys = <&usb2_phy1_port0>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- ehci: usb@9890000 { +- compatible = "generic-ehci"; +- reg = <0x9890000 0x10000>; +- interrupts = ; +- clocks = <&crg HISTB_USB2_BUS_CLK>, +- <&crg HISTB_USB2_PHY_CLK>, +- <&crg HISTB_USB2_UTMI_CLK>; +- clock-names = "bus", "phy", "utmi"; +- resets = <&crg 0xb8 12>, +- <&crg 0xb8 16>, +- <&crg 0xb8 13>; +- reset-names = "bus", "phy", "utmi"; +- phys = <&usb2_phy1_port0>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/hi6220-coresight.dtsi b/scripts/dtc/include-prefixes/arm64/hisilicon/hi6220-coresight.dtsi +deleted file mode 100644 +index 3f387f4cf5e0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/hi6220-coresight.dtsi ++++ /dev/null +@@ -1,482 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * dtsi file for Hisilicon Hi6220 coresight +- * +- * Copyright (C) 2017 HiSilicon Ltd. +- * +- * Author: Pengcheng Li +- * Leo Yan +- */ +- +-/ { +- soc { +- funnel@f6401000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0xf6401000 0 0x1000>; +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- soc_funnel_out: endpoint { +- remote-endpoint = +- <&etf_in>; +- }; +- }; +- }; +- +- in-ports { +- port { +- soc_funnel_in: endpoint { +- remote-endpoint = +- <&acpu_funnel_out>; +- }; +- }; +- }; +- }; +- +- etf@f6402000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0xf6402000 0 0x1000>; +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- in-ports { +- port { +- etf_in: endpoint { +- remote-endpoint = +- <&soc_funnel_out>; +- }; +- }; +- }; +- +- out-ports { +- port { +- etf_out: endpoint { +- remote-endpoint = +- <&replicator_in>; +- }; +- }; +- }; +- }; +- +- replicator { +- compatible = "arm,coresight-static-replicator"; +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- in-ports { +- port { +- replicator_in: endpoint { +- remote-endpoint = +- <&etf_out>; +- }; +- }; +- }; +- +- out-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- replicator_out0: endpoint { +- remote-endpoint = +- <&etr_in>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- replicator_out1: endpoint { +- remote-endpoint = +- <&tpiu_in>; +- }; +- }; +- }; +- }; +- +- etr@f6404000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0xf6404000 0 0x1000>; +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- in-ports { +- port { +- etr_in: endpoint { +- remote-endpoint = +- <&replicator_out0>; +- }; +- }; +- }; +- }; +- +- tpiu@f6405000 { +- compatible = "arm,coresight-tpiu", "arm,primecell"; +- reg = <0 0xf6405000 0 0x1000>; +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- in-ports { +- port { +- tpiu_in: endpoint { +- remote-endpoint = +- <&replicator_out1>; +- }; +- }; +- }; +- }; +- +- funnel@f6501000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0xf6501000 0 0x1000>; +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- acpu_funnel_out: endpoint { +- remote-endpoint = +- <&soc_funnel_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- acpu_funnel_in0: endpoint { +- remote-endpoint = +- <&etm0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- acpu_funnel_in1: endpoint { +- remote-endpoint = +- <&etm1_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- acpu_funnel_in2: endpoint { +- remote-endpoint = +- <&etm2_out>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- acpu_funnel_in3: endpoint { +- remote-endpoint = +- <&etm3_out>; +- }; +- }; +- +- port@4 { +- reg = <4>; +- acpu_funnel_in4: endpoint { +- remote-endpoint = +- <&etm4_out>; +- }; +- }; +- +- port@5 { +- reg = <5>; +- acpu_funnel_in5: endpoint { +- remote-endpoint = +- <&etm5_out>; +- }; +- }; +- +- port@6 { +- reg = <6>; +- acpu_funnel_in6: endpoint { +- remote-endpoint = +- <&etm6_out>; +- }; +- }; +- +- port@7 { +- reg = <7>; +- acpu_funnel_in7: endpoint { +- remote-endpoint = +- <&etm7_out>; +- }; +- }; +- }; +- }; +- +- etm0: etm@f659c000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0xf659c000 0 0x1000>; +- +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- cpu = <&cpu0>; +- +- out-ports { +- port { +- etm0_out: endpoint { +- remote-endpoint = +- <&acpu_funnel_in0>; +- }; +- }; +- }; +- }; +- +- etm1: etm@f659d000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0xf659d000 0 0x1000>; +- +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- cpu = <&cpu1>; +- +- out-ports { +- port { +- etm1_out: endpoint { +- remote-endpoint = +- <&acpu_funnel_in1>; +- }; +- }; +- }; +- }; +- +- etm2: etm@f659e000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0xf659e000 0 0x1000>; +- +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- cpu = <&cpu2>; +- +- out-ports { +- port { +- etm2_out: endpoint { +- remote-endpoint = +- <&acpu_funnel_in2>; +- }; +- }; +- }; +- }; +- +- etm3: etm@f659f000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0xf659f000 0 0x1000>; +- +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- cpu = <&cpu3>; +- +- out-ports { +- port { +- etm3_out: endpoint { +- remote-endpoint = +- <&acpu_funnel_in3>; +- }; +- }; +- }; +- }; +- +- etm4: etm@f65dc000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0xf65dc000 0 0x1000>; +- +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- cpu = <&cpu4>; +- +- out-ports { +- port { +- etm4_out: endpoint { +- remote-endpoint = +- <&acpu_funnel_in4>; +- }; +- }; +- }; +- }; +- +- etm5: etm@f65dd000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0xf65dd000 0 0x1000>; +- +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- cpu = <&cpu5>; +- +- out-ports { +- port { +- etm5_out: endpoint { +- remote-endpoint = +- <&acpu_funnel_in5>; +- }; +- }; +- }; +- }; +- +- etm6: etm@f65de000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0xf65de000 0 0x1000>; +- +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- cpu = <&cpu6>; +- +- out-ports { +- port { +- etm6_out: endpoint { +- remote-endpoint = +- <&acpu_funnel_in6>; +- }; +- }; +- }; +- }; +- +- etm7: etm@f65df000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0xf65df000 0 0x1000>; +- +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- cpu = <&cpu7>; +- +- out-ports { +- port { +- etm7_out: endpoint { +- remote-endpoint = +- <&acpu_funnel_in7>; +- }; +- }; +- }; +- }; +- +- /* System CTIs */ +- /* CTI 0 - TMC and TPIU connections */ +- cti@f6403000 { +- compatible = "arm,coresight-cti", "arm,primecell"; +- reg = <0 0xf6403000 0 0x1000>; +- +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- }; +- +- /* CTI - CPU-0 */ +- cti@f6598000 { +- compatible = "arm,coresight-cti-v8-arch", +- "arm,coresight-cti", "arm,primecell"; +- reg = <0 0xf6598000 0 0x1000>; +- +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- cpu = <&cpu0>; +- arm,cs-dev-assoc = <&etm0>; +- }; +- +- /* CTI - CPU-1 */ +- cti@f6599000 { +- compatible = "arm,coresight-cti-v8-arch", +- "arm,coresight-cti", "arm,primecell"; +- reg = <0 0xf6599000 0 0x1000>; +- +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- cpu = <&cpu1>; +- arm,cs-dev-assoc = <&etm1>; +- }; +- +- /* CTI - CPU-2 */ +- cti@f659a000 { +- compatible = "arm,coresight-cti-v8-arch", +- "arm,coresight-cti", "arm,primecell"; +- reg = <0 0xf659a000 0 0x1000>; +- +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- cpu = <&cpu2>; +- arm,cs-dev-assoc = <&etm2>; +- }; +- +- /* CTI - CPU-3 */ +- cti@f659b000 { +- compatible = "arm,coresight-cti-v8-arch", +- "arm,coresight-cti", "arm,primecell"; +- reg = <0 0xf659b000 0 0x1000>; +- +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- cpu = <&cpu3>; +- arm,cs-dev-assoc = <&etm3>; +- }; +- +- /* CTI - CPU-4 */ +- cti@f65d8000 { +- compatible = "arm,coresight-cti-v8-arch", +- "arm,coresight-cti", "arm,primecell"; +- reg = <0 0xf65d8000 0 0x1000>; +- +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- cpu = <&cpu4>; +- arm,cs-dev-assoc = <&etm4>; +- }; +- +- /* CTI - CPU-5 */ +- cti@f65d9000 { +- compatible = "arm,coresight-cti-v8-arch", +- "arm,coresight-cti", "arm,primecell"; +- reg = <0 0xf65d9000 0 0x1000>; +- +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- cpu = <&cpu5>; +- arm,cs-dev-assoc = <&etm5>; +- }; +- +- /* CTI - CPU-6 */ +- cti@f65da000 { +- compatible = "arm,coresight-cti-v8-arch", +- "arm,coresight-cti", "arm,primecell"; +- reg = <0 0xf65da000 0 0x1000>; +- +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- cpu = <&cpu6>; +- arm,cs-dev-assoc = <&etm6>; +- }; +- +- /* CTI - CPU-7 */ +- cti@f65db000 { +- compatible = "arm,coresight-cti-v8-arch", +- "arm,coresight-cti", "arm,primecell"; +- reg = <0 0xf65db000 0 0x1000>; +- +- clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; +- clock-names = "apb_pclk"; +- +- cpu = <&cpu7>; +- arm,cs-dev-assoc = <&etm7>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/hi6220-hikey.dts b/scripts/dtc/include-prefixes/arm64/hisilicon/hi6220-hikey.dts +deleted file mode 100644 +index 3df2afb2f637..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/hi6220-hikey.dts ++++ /dev/null +@@ -1,545 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * dts file for Hisilicon HiKey Development Board +- * +- * Copyright (C) 2015, HiSilicon Ltd. +- * +- */ +- +-/dts-v1/; +-#include "hi6220.dtsi" +-#include "hikey-pinctrl.dtsi" +-#include +- +-/ { +- model = "HiKey Development Board"; +- compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; +- +- aliases { +- serial0 = &uart0; /* On board UART0 */ +- serial1 = &uart1; /* BT UART */ +- serial2 = &uart2; /* LS Expansion UART0 */ +- serial3 = &uart3; /* LS Expansion UART1 */ +- }; +- +- chosen { +- stdout-path = "serial3:115200n8"; +- }; +- +- /* +- * Reserve below regions from memory node: +- * +- * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using +- * 0x05f0,1000 - 0x05f0,1fff: Reboot reason +- * 0x06df,f000 - 0x06df,ffff: Mailbox message data +- * 0x0740,f000 - 0x0740,ffff: MCU firmware section +- * 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer +- * 0x3e00,0000 - 0x3fff,ffff: OP-TEE +- */ +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000 0x05e00000>, +- <0x00000000 0x05f00000 0x00000000 0x00001000>, +- <0x00000000 0x05f02000 0x00000000 0x00efd000>, +- <0x00000000 0x06e00000 0x00000000 0x0060f000>, +- <0x00000000 0x07410000 0x00000000 0x1aaf0000>, +- <0x00000000 0x22000000 0x00000000 0x1c000000>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ramoops@21f00000 { +- compatible = "ramoops"; +- reg = <0x0 0x21f00000 0x0 0x00100000>; +- record-size = <0x00020000>; +- console-size = <0x00020000>; +- ftrace-size = <0x00020000>; +- }; +- +- /* global autoconfigured region for contiguous allocations */ +- linux,cma { +- compatible = "shared-dma-pool"; +- reusable; +- size = <0x00000000 0x08000000>; +- linux,cma-default; +- }; +- }; +- +- reboot-mode-syscon@5f01000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x0 0x05f01000 0x0 0x00001000>; +- +- reboot-mode { +- compatible = "syscon-reboot-mode"; +- offset = <0x0>; +- +- mode-normal = <0x77665501>; +- mode-bootloader = <0x77665500>; +- mode-recovery = <0x77665502>; +- }; +- }; +- +- reg_sys_5v: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "SYS_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_vdd_3v3: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- vin-supply = <®_sys_5v>; +- }; +- +- reg_5v_hub: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "5V_HUB"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- gpio = <&gpio0 7 0>; +- regulator-always-on; +- vin-supply = <®_sys_5v>; +- }; +- +- wl1835_pwrseq: wl1835-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- /* WLAN_EN GPIO */ +- reset-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; +- clocks = <&pmic>; +- clock-names = "ext_clock"; +- post-power-on-delay-ms = <10>; +- power-off-delay-us = <10>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- user_led1 { +- label = "green:user1"; +- gpios = <&gpio4 0 0>; /* <&gpio_user_led_1>; */ +- linux,default-trigger = "heartbeat"; +- }; +- +- user_led2 { +- label = "green:user2"; +- gpios = <&gpio4 1 0>; /* <&gpio_user_led_2>; */ +- linux,default-trigger = "mmc0"; +- }; +- +- user_led3 { +- label = "green:user3"; +- gpios = <&gpio4 2 0>; /* <&gpio_user_led_3>; */ +- linux,default-trigger = "mmc1"; +- }; +- +- user_led4 { +- label = "green:user4"; +- gpios = <&gpio4 3 0>; /* <&gpio_user_led_4>; */ +- panic-indicator; +- linux,default-trigger = "none"; +- }; +- +- wlan_active_led { +- label = "yellow:wlan"; +- gpios = <&gpio3 5 0>; /* <&gpio_wlan_active_led>; */ +- linux,default-trigger = "phy0tx"; +- default-state = "off"; +- }; +- +- bt_active_led { +- label = "blue:bt"; +- gpios = <&gpio4 7 0>; /* <&gpio_bt_active_led>; */ +- linux,default-trigger = "hci0-power"; +- default-state = "off"; +- }; +- }; +- +- pmic: pmic@f8000000 { +- compatible = "hisilicon,hi655x-pmic"; +- reg = <0x0 0xf8000000 0x0 0x1000>; +- #clock-cells = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- +- regulators { +- ldo2: LDO2 { +- regulator-name = "LDO2_2V8"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <3200000>; +- regulator-enable-ramp-delay = <120>; +- }; +- +- ldo7: LDO7 { +- regulator-name = "LDO7_SDIO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <120>; +- }; +- +- ldo10: LDO10 { +- regulator-name = "LDO10_2V85"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- regulator-enable-ramp-delay = <360>; +- }; +- +- ldo13: LDO13 { +- regulator-name = "LDO13_1V8"; +- regulator-min-microvolt = <1600000>; +- regulator-max-microvolt = <1950000>; +- regulator-enable-ramp-delay = <120>; +- }; +- +- ldo14: LDO14 { +- regulator-name = "LDO14_2V8"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <3200000>; +- regulator-enable-ramp-delay = <120>; +- }; +- +- ldo15: LDO15 { +- regulator-name = "LDO15_1V8"; +- regulator-min-microvolt = <1600000>; +- regulator-max-microvolt = <1950000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-enable-ramp-delay = <120>; +- }; +- +- ldo17: LDO17 { +- regulator-name = "LDO17_2V5"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <3200000>; +- regulator-enable-ramp-delay = <120>; +- }; +- +- ldo19: LDO19 { +- regulator-name = "LDO19_3V0"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- regulator-enable-ramp-delay = <360>; +- }; +- +- ldo21: LDO21 { +- regulator-name = "LDO21_1V8"; +- regulator-min-microvolt = <1650000>; +- regulator-max-microvolt = <2000000>; +- regulator-always-on; +- regulator-enable-ramp-delay = <120>; +- }; +- +- ldo22: LDO22 { +- regulator-name = "LDO22_1V2"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1200000>; +- regulator-boot-on; +- regulator-always-on; +- regulator-enable-ramp-delay = <120>; +- }; +- }; +- }; +- +- firmware { +- optee { +- compatible = "linaro,optee-tz"; +- method = "smc"; +- }; +- }; +- +- sound_card { +- compatible = "audio-graph-card"; +- dais = <&i2s0_port0>; +- }; +-}; +- +-&uart1 { +- assigned-clocks = <&sys_ctrl HI6220_UART1_SRC>; +- assigned-clock-rates = <150000000>; +- status = "okay"; +- +- bluetooth { +- compatible = "ti,wl1835-st"; +- enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; +- clocks = <&pmic>; +- clock-names = "ext_clock"; +- }; +-}; +- +-&uart2 { +- status = "okay"; +- label = "LS-UART0"; +-}; +- +-&uart3 { +- status = "okay"; +- label = "LS-UART1"; +-}; +- +-&ade { +- status = "okay"; +-}; +- +-&dsi { +- status = "okay"; +- +- ports { +- /* 1 for output port */ +- port@1 { +- reg = <1>; +- +- dsi_out0: endpoint@0 { +- remote-endpoint = <&adv7533_in>; +- }; +- }; +- }; +-}; +- +-&dwmmc_0 { +- cap-mmc-highspeed; +- non-removable; +- bus-width = <0x8>; +- vmmc-supply = <&ldo19>; +-}; +- +-&dwmmc_1 { +- card-detect-delay = <200>; +- cap-sd-highspeed; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- vqmmc-supply = <&ldo7>; +- vmmc-supply = <&ldo10>; +- bus-width = <0x4>; +- disable-wp; +- cd-gpios = <&gpio1 0 1>; +-}; +- +-&dwmmc_2 { +- bus-width = <0x4>; +- non-removable; +- cap-power-off-card; +- vmmc-supply = <®_vdd_3v3>; +- mmc-pwrseq = <&wl1835_pwrseq>; +- +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1835"; +- reg = <2>; /* sdio func num */ +- /* WL_IRQ, WL_HOST_WAKE_GPIO1_3 */ +- interrupt-parent = <&gpio1>; +- interrupts = <3 IRQ_TYPE_EDGE_RISING>; +- }; +-}; +- +-/* +- * Legend: proper name = the GPIO line is used as GPIO +- * NC = not connected (not routed from the SoC) +- * "[PER]" = pin is muxed for peripheral (not GPIO) +- * "" = no idea, schematic doesn't say, could be +- * unrouted (not connected to any external pin) +- * LSEC = Low Speed External Connector +- * HSEC = High Speed External Connector +- * +- * Pin assignments taken from LeMaker and CircuitCo Schematics +- * Rev A1. +- * +- * For the lines routed to the external connectors the +- * lines are named after the 96Boards CE Specification 1.0, +- * Appendix "Expansion Connector Signal Description". +- * +- * When the 96Board naming of a line and the schematic name of +- * the same line are in conflict, the 96Board specification +- * takes precedence, which means that the external UART on the +- * LSEC is named UART0 while the schematic and SoC names this +- * UART2. This is only for the informational lines i.e. "[FOO]", +- * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only +- * ones actually used for GPIO. +- */ +-&gpio0 { +- gpio-line-names = "PWR_HOLD", "DSI_SEL", +- "USB_HUB_RESET_N", "USB_SEL", "HDMI_PD", "WL_REG_ON", +- "PWRON_DET", "5V_HUB_EN"; +-}; +- +-&gpio1 { +- gpio-line-names = "SD_DET", "HDMI_INT", "PMU_IRQ_N", +- "WL_HOST_WAKE", "NC", "NC", "NC", "BT_REG_ON"; +-}; +- +-&gpio2 { +- gpio-line-names = +- "GPIO-A", /* LSEC Pin 23: GPIO2_0 */ +- "GPIO-B", /* LSEC Pin 24: GPIO2_1 */ +- "GPIO-C", /* LSEC Pin 25: GPIO2_2 */ +- "GPIO-D", /* LSEC Pin 26: GPIO2_3 */ +- "GPIO-E", /* LSEC Pin 27: GPIO2_4 */ +- "USB_ID_DET", "USB_VBUS_DET", +- "GPIO-H"; /* LSEC Pin 30: GPIO2_7 */ +-}; +- +-&gpio3 { +- gpio-line-names = "GPIO3_0", "NC", "NC", "", "NC", "", +- "WLAN_ACTIVE", "NC", "NC"; +-}; +- +-&gpio4 { +- gpio-line-names = "USER_LED1", "USER_LED2", "USER_LED3", +- "USER_LED4", "SD_SEL", "NC", "NC", "BT_ACTIVE"; +-}; +- +-&gpio5 { +- gpio-line-names = "NC", "NC", +- "[UART1_RxD]", /* LSEC Pin 11: UART3_RX */ +- "[UART1_TxD]", /* LSEC Pin 13: UART3_TX */ +- "[AUX_SSI1]", "NC", +- "[PCM_CLK]", /* LSEC Pin 18: MODEM_PCM_XCLK */ +- "[PCM_FS]"; /* LSEC Pin 16: MODEM_PCM_XFS */ +-}; +- +-&gpio6 { +- gpio-line-names = +- "[SPI0_DIN]", /* Pin 10: SPI0_DI */ +- "[SPI0_DOUT]", /* Pin 14: SPI0_DO */ +- "[SPI0_CS]", /* Pin 12: SPI0_CS_N */ +- "[SPI0_SCLK]", /* Pin 8: SPI0_SCLK */ +- "NC", "NC", "NC", +- "GPIO-G"; /* Pin 29: GPIO6_7_DSI_TE0 */ +-}; +- +-&gpio7 { +- gpio-line-names = "NC", "NC", "NC", "NC", +- "[PCM_DI]", /* Pin 22: MODEM_PCM_DI */ +- "[PCM_DO]", /* Pin 20: MODEM_PCM_DO */ +- "NC", "NC"; +-}; +- +-&gpio8 { +- gpio-line-names = "NC", "[CEC_CLK_19_2MHZ]", "NC", +- "", "", "", "", "", ""; +-}; +- +-&gpio9 { +- gpio-line-names = "", +- "GPIO-J", /* LSEC Pin 32: ISP_PWDN0_GPIO9_1 */ +- "GPIO-L", /* LSEC Pin 34: ISP_PWDN1_GPIO9_2 */ +- "NC", "NC", "NC", "NC", "[ISP_CCLK0]"; +-}; +- +-&gpio10 { +- gpio-line-names = "BOOT_SEL", +- "[ISP_CCLK1]", +- "GPIO-I", /* LSEC Pin 31: ISP_RSTB0_GPIO10_2 */ +- "GPIO-K", /* LSEC Pin 33: ISP_RSTB1_GPIO10_3 */ +- "NC", "NC", +- "[I2C2_SDA]", /* HSEC Pin 34: ISP0_SDA */ +- "[I2C2_SCL]"; /* HSEC Pin 32: ISP0_SCL */ +-}; +- +-&gpio11 { +- gpio-line-names = +- "[I2C3_SDA]", /* HSEC Pin 38: ISP1_SDA */ +- "[I2C3_SCL]", /* HSEC Pin 36: ISP1_SCL */ +- "", "NC", "NC", "NC", "", ""; +-}; +- +-&gpio12 { +- gpio-line-names = "[BT_PCM_XFS]", "[BT_PCM_DI]", +- "[BT_PCM_DO]", +- "NC", "NC", "NC", "NC", +- "GPIO-F"; /* LSEC Pin 28: BL_PWM_GPIO12_7 */ +-}; +- +-&gpio13 { +- gpio-line-names = "[UART0_RX]", "[UART0_TX]", +- "[BT_UART1_CTS]", "[BT_UART1_RTS]", +- "[BT_UART1_RX]", "[BT_UART1_TX]", +- "[UART0_CTS]", /* LSEC Pin 3: UART2_CTS_N */ +- "[UART0_RTS]"; /* LSEC Pin 9: UART2_RTS_N */ +-}; +- +-&gpio14 { +- gpio-line-names = +- "[UART0_RxD]", /* LSEC Pin 7: UART2_RX */ +- "[UART0_TxD]", /* LSEC Pin 5: UART2_TX */ +- "[I2C0_SCL]", /* LSEC Pin 15: I2C0_SCL */ +- "[I2C0_SDA]", /* LSEC Pin 17: I2C0_SDA */ +- "[I2C1_SCL]", /* LSEC Pin 19: I2C1_SCL */ +- "[I2C1_SDA]", /* LSEC Pin 21: I2C1_SDA */ +- "[I2C2_SCL]", "[I2C2_SDA]"; +-}; +- +-&gpio15 { +- gpio-line-names = "", "", "", "", "", "", "NC", ""; +-}; +- +-/* GPIO blocks 16 thru 19 do not appear to be routed to pins */ +- +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- adv7533: adv7533@39 { +- compatible = "adi,adv7533"; +- reg = <0x39>; +- interrupt-parent = <&gpio1>; +- interrupts = <1 2>; +- pd-gpios = <&gpio0 4 0>; +- adi,dsi-lanes = <4>; +- #sound-dai-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- adv7533_in: endpoint { +- remote-endpoint = <&dsi_out0>; +- }; +- }; +- port@2 { +- reg = <2>; +- codec_endpoint: endpoint { +- remote-endpoint = <&i2s0_cpu_endpoint>; +- }; +- }; +- }; +- }; +-}; +- +-&i2s0 { +- +- ports { +- i2s0_port0: port@0 { +- i2s0_cpu_endpoint: endpoint { +- remote-endpoint = <&codec_endpoint>; +- dai-format = "i2s"; +- }; +- }; +- }; +-}; +- +-&spi0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/hi6220.dtsi b/scripts/dtc/include-prefixes/arm64/hisilicon/hi6220.dtsi +deleted file mode 100644 +index e4860b8a638e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/hi6220.dtsi ++++ /dev/null +@@ -1,1066 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * dts file for Hisilicon Hi6220 SoC +- * +- * Copyright (C) 2015, HiSilicon Ltd. +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "hisilicon,hi6220"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- core2 { +- cpu = <&cpu2>; +- }; +- core3 { +- cpu = <&cpu3>; +- }; +- }; +- cluster1 { +- core0 { +- cpu = <&cpu4>; +- }; +- core1 { +- cpu = <&cpu5>; +- }; +- core2 { +- cpu = <&cpu6>; +- }; +- core3 { +- cpu = <&cpu7>; +- }; +- }; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP: cpu-sleep { +- compatible = "arm,idle-state"; +- local-timer-stop; +- arm,psci-suspend-param = <0x0010000>; +- entry-latency-us = <700>; +- exit-latency-us = <250>; +- min-residency-us = <1000>; +- }; +- +- CLUSTER_SLEEP: cluster-sleep { +- compatible = "arm,idle-state"; +- local-timer-stop; +- arm,psci-suspend-param = <0x1010000>; +- entry-latency-us = <1000>; +- exit-latency-us = <700>; +- min-residency-us = <2700>; +- wakeup-latency-us = <1500>; +- }; +- }; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER0_L2>; +- clocks = <&stub_clock 0>; +- operating-points-v2 = <&cpu_opp_table>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; +- #cooling-cells = <2>; /* min followed by max */ +- dynamic-power-coefficient = <311>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER0_L2>; +- clocks = <&stub_clock 0>; +- operating-points-v2 = <&cpu_opp_table>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; +- #cooling-cells = <2>; /* min followed by max */ +- dynamic-power-coefficient = <311>; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER0_L2>; +- clocks = <&stub_clock 0>; +- operating-points-v2 = <&cpu_opp_table>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; +- #cooling-cells = <2>; /* min followed by max */ +- dynamic-power-coefficient = <311>; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER0_L2>; +- clocks = <&stub_clock 0>; +- operating-points-v2 = <&cpu_opp_table>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; +- #cooling-cells = <2>; /* min followed by max */ +- dynamic-power-coefficient = <311>; +- }; +- +- cpu4: cpu@100 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER1_L2>; +- clocks = <&stub_clock 0>; +- operating-points-v2 = <&cpu_opp_table>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; +- #cooling-cells = <2>; /* min followed by max */ +- dynamic-power-coefficient = <311>; +- }; +- +- cpu5: cpu@101 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x101>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER1_L2>; +- clocks = <&stub_clock 0>; +- operating-points-v2 = <&cpu_opp_table>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; +- #cooling-cells = <2>; /* min followed by max */ +- dynamic-power-coefficient = <311>; +- }; +- +- cpu6: cpu@102 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x102>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER1_L2>; +- clocks = <&stub_clock 0>; +- operating-points-v2 = <&cpu_opp_table>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; +- #cooling-cells = <2>; /* min followed by max */ +- dynamic-power-coefficient = <311>; +- }; +- +- cpu7: cpu@103 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x103>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER1_L2>; +- clocks = <&stub_clock 0>; +- operating-points-v2 = <&cpu_opp_table>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; +- #cooling-cells = <2>; /* min followed by max */ +- dynamic-power-coefficient = <311>; +- }; +- +- CLUSTER0_L2: l2-cache0 { +- compatible = "cache"; +- }; +- +- CLUSTER1_L2: l2-cache1 { +- compatible = "cache"; +- }; +- }; +- +- cpu_opp_table: cpu_opp_table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp00 { +- opp-hz = /bits/ 64 <208000000>; +- opp-microvolt = <1040000>; +- clock-latency-ns = <500000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <432000000>; +- opp-microvolt = <1040000>; +- clock-latency-ns = <500000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <729000000>; +- opp-microvolt = <1090000>; +- clock-latency-ns = <500000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <960000000>; +- opp-microvolt = <1180000>; +- clock-latency-ns = <500000>; +- }; +- opp04 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <1330000>; +- clock-latency-ns = <500000>; +- }; +- }; +- +- gic: interrupt-controller@f6801000 { +- compatible = "arm,gic-400"; +- reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ +- <0x0 0xf6802000 0 0x2000>, /* GICC */ +- <0x0 0xf6804000 0 0x2000>, /* GICH */ +- <0x0 0xf6806000 0 0x2000>; /* GICV */ +- #address-cells = <0>; +- #interrupt-cells = <3>; +- interrupt-controller; +- interrupts = ; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- sram: sram@fff80000 { +- compatible = "hisilicon,hi6220-sramctrl", "syscon"; +- reg = <0x0 0xfff80000 0x0 0x12000>; +- }; +- +- ao_ctrl: ao_ctrl@f7800000 { +- compatible = "hisilicon,hi6220-aoctrl", "syscon"; +- reg = <0x0 0xf7800000 0x0 0x2000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- sys_ctrl: sys_ctrl@f7030000 { +- compatible = "hisilicon,hi6220-sysctrl", "syscon"; +- reg = <0x0 0xf7030000 0x0 0x2000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- media_ctrl: media_ctrl@f4410000 { +- compatible = "hisilicon,hi6220-mediactrl", "syscon"; +- reg = <0x0 0xf4410000 0x0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pm_ctrl: pm_ctrl@f7032000 { +- compatible = "hisilicon,hi6220-pmctrl", "syscon"; +- reg = <0x0 0xf7032000 0x0 0x1000>; +- #clock-cells = <1>; +- }; +- +- acpu_sctrl: acpu_sctrl@f6504000 { +- compatible = "hisilicon,hi6220-acpu-sctrl", "syscon"; +- reg = <0x0 0xf6504000 0x0 0x1000>; +- #clock-cells = <1>; +- }; +- +- medianoc_ade: medianoc_ade@f4520000 { +- compatible = "syscon"; +- reg = <0x0 0xf4520000 0x0 0x4000>; +- }; +- +- stub_clock: stub_clock { +- compatible = "hisilicon,hi6220-stub-clk"; +- hisilicon,hi6220-clk-sram = <&sram>; +- #clock-cells = <1>; +- mbox-names = "mbox-tx"; +- mboxes = <&mailbox 1 0 11>; +- }; +- +- uart0: serial@f8015000 { /* console */ +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xf8015000 0x0 0x1000>; +- interrupts = ; +- clocks = <&ao_ctrl HI6220_UART0_PCLK>, +- <&ao_ctrl HI6220_UART0_PCLK>; +- clock-names = "uartclk", "apb_pclk"; +- }; +- +- uart1: serial@f7111000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xf7111000 0x0 0x1000>; +- interrupts = ; +- clocks = <&sys_ctrl HI6220_UART1_PCLK>, +- <&sys_ctrl HI6220_UART1_PCLK>; +- clock-names = "uartclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>; +- dmas = <&dma0 8 &dma0 9>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uart2: serial@f7112000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xf7112000 0x0 0x1000>; +- interrupts = ; +- clocks = <&sys_ctrl HI6220_UART2_PCLK>, +- <&sys_ctrl HI6220_UART2_PCLK>; +- clock-names = "uartclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; +- status = "disabled"; +- }; +- +- uart3: serial@f7113000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xf7113000 0x0 0x1000>; +- interrupts = ; +- clocks = <&sys_ctrl HI6220_UART3_PCLK>, +- <&sys_ctrl HI6220_UART3_PCLK>; +- clock-names = "uartclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; +- status = "disabled"; +- }; +- +- uart4: serial@f7114000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xf7114000 0x0 0x1000>; +- interrupts = ; +- clocks = <&sys_ctrl HI6220_UART4_PCLK>, +- <&sys_ctrl HI6220_UART4_PCLK>; +- clock-names = "uartclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; +- status = "disabled"; +- }; +- +- dma0: dma@f7370000 { +- compatible = "hisilicon,k3-dma-1.0"; +- reg = <0x0 0xf7370000 0x0 0x1000>; +- #dma-cells = <1>; +- dma-channels = <15>; +- dma-requests = <32>; +- interrupts = <0 84 4>; +- clocks = <&sys_ctrl HI6220_EDMAC_ACLK>; +- dma-no-cci; +- dma-type = "hi6220_dma"; +- status = "okay"; +- }; +- +- dual_timer0: timer@f8008000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x0 0xf8008000 0x0 0x1000>; +- interrupts = , +- ; +- clocks = <&ao_ctrl HI6220_TIMER0_PCLK>, +- <&ao_ctrl HI6220_TIMER0_PCLK>, +- <&ao_ctrl HI6220_TIMER0_PCLK>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- }; +- +- rtc0: rtc@f8003000 { +- compatible = "arm,pl031", "arm,primecell"; +- reg = <0x0 0xf8003000 0x0 0x1000>; +- interrupts = <0 12 4>; +- clocks = <&ao_ctrl HI6220_RTC0_PCLK>; +- clock-names = "apb_pclk"; +- }; +- +- rtc1: rtc@f8004000 { +- compatible = "arm,pl031", "arm,primecell"; +- reg = <0x0 0xf8004000 0x0 0x1000>; +- interrupts = <0 8 4>; +- clocks = <&ao_ctrl HI6220_RTC1_PCLK>; +- clock-names = "apb_pclk"; +- }; +- +- pmx0: pinmux@f7010000 { +- compatible = "pinctrl-single"; +- reg = <0x0 0xf7010000 0x0 0x27c>; +- #address-cells = <1>; +- #size-cells = <1>; +- #pinctrl-cells = <1>; +- #gpio-range-cells = <3>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <7>; +- pinctrl-single,gpio-range = < +- &range 80 8 MUX_M0 /* gpio 3: [0..7] */ +- &range 88 8 MUX_M0 /* gpio 4: [0..7] */ +- &range 96 8 MUX_M0 /* gpio 5: [0..7] */ +- &range 104 8 MUX_M0 /* gpio 6: [0..7] */ +- &range 112 8 MUX_M0 /* gpio 7: [0..7] */ +- &range 120 2 MUX_M0 /* gpio 8: [0..1] */ +- &range 2 6 MUX_M1 /* gpio 8: [2..7] */ +- &range 8 8 MUX_M1 /* gpio 9: [0..7] */ +- &range 0 1 MUX_M1 /* gpio 10: [0] */ +- &range 16 7 MUX_M1 /* gpio 10: [1..7] */ +- &range 23 3 MUX_M1 /* gpio 11: [0..2] */ +- &range 28 5 MUX_M1 /* gpio 11: [3..7] */ +- &range 33 3 MUX_M1 /* gpio 12: [0..2] */ +- &range 43 5 MUX_M1 /* gpio 12: [3..7] */ +- &range 48 8 MUX_M1 /* gpio 13: [0..7] */ +- &range 56 8 MUX_M1 /* gpio 14: [0..7] */ +- &range 74 6 MUX_M1 /* gpio 15: [0..5] */ +- &range 122 1 MUX_M1 /* gpio 15: [6] */ +- &range 126 1 MUX_M1 /* gpio 15: [7] */ +- &range 127 8 MUX_M1 /* gpio 16: [0..7] */ +- &range 135 8 MUX_M1 /* gpio 17: [0..7] */ +- &range 143 8 MUX_M1 /* gpio 18: [0..7] */ +- &range 151 8 MUX_M1 /* gpio 19: [0..7] */ +- >; +- range: gpio-range { +- #pinctrl-single,gpio-range-cells = <3>; +- }; +- }; +- +- pmx1: pinmux@f7010800 { +- compatible = "pinconf-single"; +- reg = <0x0 0xf7010800 0x0 0x28c>; +- #address-cells = <1>; +- #size-cells = <1>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <32>; +- }; +- +- pmx2: pinmux@f8001800 { +- compatible = "pinconf-single"; +- reg = <0x0 0xf8001800 0x0 0x78>; +- #address-cells = <1>; +- #size-cells = <1>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <32>; +- }; +- +- gpio0: gpio@f8011000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf8011000 0x0 0x1000>; +- interrupts = <0 52 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio1: gpio@f8012000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf8012000 0x0 0x1000>; +- interrupts = <0 53 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio2: gpio@f8013000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf8013000 0x0 0x1000>; +- interrupts = <0 54 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio3: gpio@f8014000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf8014000 0x0 0x1000>; +- interrupts = <0 55 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 80 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio4: gpio@f7020000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf7020000 0x0 0x1000>; +- interrupts = <0 56 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 88 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio5: gpio@f7021000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf7021000 0x0 0x1000>; +- interrupts = <0 57 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 96 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio6: gpio@f7022000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf7022000 0x0 0x1000>; +- interrupts = <0 58 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 104 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio7: gpio@f7023000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf7023000 0x0 0x1000>; +- interrupts = <0 59 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 112 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio8: gpio@f7024000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf7024000 0x0 0x1000>; +- interrupts = <0 60 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio9: gpio@f7025000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf7025000 0x0 0x1000>; +- interrupts = <0 61 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 8 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio10: gpio@f7026000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf7026000 0x0 0x1000>; +- interrupts = <0 62 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio11: gpio@f7027000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf7027000 0x0 0x1000>; +- interrupts = <0 63 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio12: gpio@f7028000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf7028000 0x0 0x1000>; +- interrupts = <0 64 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio13: gpio@f7029000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf7029000 0x0 0x1000>; +- interrupts = <0 65 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 48 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio14: gpio@f702a000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf702a000 0x0 0x1000>; +- interrupts = <0 66 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 56 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio15: gpio@f702b000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf702b000 0x0 0x1000>; +- interrupts = <0 67 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = < +- &pmx0 0 74 6 +- &pmx0 6 122 1 +- &pmx0 7 126 1 +- >; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio16: gpio@f702c000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf702c000 0x0 0x1000>; +- interrupts = <0 68 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 127 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio17: gpio@f702d000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf702d000 0x0 0x1000>; +- interrupts = <0 69 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 135 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio18: gpio@f702e000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf702e000 0x0 0x1000>; +- interrupts = <0 70 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 143 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- gpio19: gpio@f702f000 { +- compatible = "arm,pl061", "arm,primecell"; +- reg = <0x0 0xf702f000 0x0 0x1000>; +- interrupts = <0 71 0x4>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmx0 0 151 8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&ao_ctrl 2>; +- clock-names = "apb_pclk"; +- }; +- +- spi0: spi@f7106000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x0 0xf7106000 0x0 0x1000>; +- interrupts = <0 50 4>; +- bus-id = <0>; +- enable-dma = <0>; +- clocks = <&sys_ctrl HI6220_SPI_CLK>, <&sys_ctrl HI6220_SPI_CLK>; +- clock-names = "sspclk", "apb_pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; +- num-cs = <1>; +- cs-gpios = <&gpio6 2 0>; +- status = "disabled"; +- }; +- +- i2c0: i2c@f7100000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0xf7100000 0x0 0x1000>; +- interrupts = <0 44 4>; +- clocks = <&sys_ctrl HI6220_I2C0_CLK>; +- i2c-sda-hold-time-ns = <300>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; +- status = "disabled"; +- }; +- +- i2c1: i2c@f7101000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0xf7101000 0x0 0x1000>; +- clocks = <&sys_ctrl HI6220_I2C1_CLK>; +- interrupts = <0 45 4>; +- i2c-sda-hold-time-ns = <300>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; +- status = "disabled"; +- }; +- +- i2c2: i2c@f7102000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0xf7102000 0x0 0x1000>; +- clocks = <&sys_ctrl HI6220_I2C2_CLK>; +- interrupts = <0 46 4>; +- i2c-sda-hold-time-ns = <300>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; +- status = "disabled"; +- }; +- +- usb_phy: usbphy { +- compatible = "hisilicon,hi6220-usb-phy"; +- #phy-cells = <0>; +- phy-supply = <®_5v_hub>; +- hisilicon,peripheral-syscon = <&sys_ctrl>; +- }; +- +- usb: usb@f72c0000 { +- compatible = "hisilicon,hi6220-usb"; +- reg = <0x0 0xf72c0000 0x0 0x40000>; +- phys = <&usb_phy>; +- phy-names = "usb2-phy"; +- clocks = <&sys_ctrl HI6220_USBOTG_HCLK>; +- clock-names = "otg"; +- dr_mode = "otg"; +- g-rx-fifo-size = <512>; +- g-np-tx-fifo-size = <128>; +- g-tx-fifo-size = <128 128 128 128 128 128 128 128 +- 16 16 16 16 16 16 16>; +- interrupts = <0 77 0x4>; +- }; +- +- mailbox: mailbox@f7510000 { +- compatible = "hisilicon,hi6220-mbox"; +- reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */ +- <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */ +- interrupts = ; +- #mbox-cells = <3>; +- }; +- +- dwmmc_0: dwmmc0@f723d000 { +- compatible = "hisilicon,hi6220-dw-mshc"; +- reg = <0x0 0xf723d000 0x0 0x1000>; +- interrupts = <0x0 0x48 0x4>; +- clocks = <&sys_ctrl 2>, <&sys_ctrl 1>; +- clock-names = "ciu", "biu"; +- resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>; +- reset-names = "reset"; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func +- &emmc_cfg_func &emmc_rst_cfg_func>; +- }; +- +- dwmmc_1: dwmmc1@f723e000 { +- compatible = "hisilicon,hi6220-dw-mshc"; +- hisilicon,peripheral-syscon = <&ao_ctrl>; +- reg = <0x0 0xf723e000 0x0 0x1000>; +- interrupts = <0x0 0x49 0x4>; +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- clocks = <&sys_ctrl 4>, <&sys_ctrl 3>; +- clock-names = "ciu", "biu"; +- resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>; +- reset-names = "reset"; +- pinctrl-names = "default", "idle"; +- pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; +- pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; +- }; +- +- dwmmc_2: dwmmc2@f723f000 { +- compatible = "hisilicon,hi6220-dw-mshc"; +- reg = <0x0 0xf723f000 0x0 0x1000>; +- interrupts = <0x0 0x4a 0x4>; +- clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; +- clock-names = "ciu", "biu"; +- resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>; +- reset-names = "reset"; +- pinctrl-names = "default", "idle"; +- pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>; +- pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; +- }; +- +- watchdog0: watchdog@f8005000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xf8005000 0x0 0x1000>; +- interrupts = ; +- clocks = <&ao_ctrl HI6220_WDT0_PCLK>, +- <&ao_ctrl HI6220_WDT0_PCLK>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- +- tsensor: tsensor@0,f7030700 { +- compatible = "hisilicon,tsensor"; +- reg = <0x0 0xf7030700 0x0 0x1000>; +- interrupts = ; +- clocks = <&sys_ctrl 22>; +- clock-names = "thermal_clk"; +- #thermal-sensor-cells = <1>; +- }; +- +- i2s0: i2s@f7118000{ +- compatible = "hisilicon,hi6210-i2s"; +- reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */ +- interrupts = ; /* 155 "DigACodec_intr"-32 */ +- clocks = <&sys_ctrl HI6220_DACODEC_PCLK>, +- <&sys_ctrl HI6220_BBPPLL0_DIV>; +- clock-names = "dacodec", "i2s-base"; +- dmas = <&dma0 15 &dma0 14>; +- dma-names = "rx", "tx"; +- hisilicon,sysctrl-syscon = <&sys_ctrl>; +- #sound-dai-cells = <1>; +- }; +- +- thermal-zones { +- +- cls0: cls0-thermal { +- polling-delay = <1000>; +- polling-delay-passive = <100>; +- sustainable-power = <3326>; +- +- /* sensor ID */ +- thermal-sensors = <&tsensor 2>; +- +- trips { +- threshold: trip-point0 { +- temperature = <65000>; +- hysteresis = <0>; +- type = "passive"; +- }; +- +- target: trip-point1 { +- temperature = <75000>; +- hysteresis = <0>; +- type = "passive"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&target>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- ade: ade@f4100000 { +- compatible = "hisilicon,hi6220-ade"; +- reg = <0x0 0xf4100000 0x0 0x7800>; +- reg-names = "ade_base"; +- hisilicon,noc-syscon = <&medianoc_ade>; +- resets = <&media_ctrl MEDIA_ADE>; +- interrupts = <0 115 4>; /* ldi interrupt */ +- +- clocks = <&media_ctrl HI6220_ADE_CORE>, +- <&media_ctrl HI6220_CODEC_JPEG>, +- <&media_ctrl HI6220_ADE_PIX_SRC>; +- /*clock name*/ +- clock-names = "clk_ade_core", +- "clk_codec_jpeg", +- "clk_ade_pix"; +- +- assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, +- <&media_ctrl HI6220_CODEC_JPEG>; +- assigned-clock-rates = <360000000>, <288000000>; +- dma-coherent; +- status = "disabled"; +- +- port { +- ade_out: endpoint { +- remote-endpoint = <&dsi_in>; +- }; +- }; +- }; +- +- dsi: dsi@f4107800 { +- compatible = "hisilicon,hi6220-dsi"; +- reg = <0x0 0xf4107800 0x0 0x100>; +- clocks = <&media_ctrl HI6220_DSI_PCLK>; +- clock-names = "pclk"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* 0 for input port */ +- port@0 { +- reg = <0>; +- dsi_in: endpoint { +- remote-endpoint = <&ade_out>; +- }; +- }; +- }; +- }; +- +- debug@f6590000 { +- compatible = "arm,coresight-cpu-debug","arm,primecell"; +- reg = <0 0xf6590000 0 0x1000>; +- clocks = <&sys_ctrl HI6220_DAPB_CLK>; +- clock-names = "apb_pclk"; +- cpu = <&cpu0>; +- }; +- +- debug@f6592000 { +- compatible = "arm,coresight-cpu-debug","arm,primecell"; +- reg = <0 0xf6592000 0 0x1000>; +- clocks = <&sys_ctrl HI6220_DAPB_CLK>; +- clock-names = "apb_pclk"; +- cpu = <&cpu1>; +- }; +- +- debug@f6594000 { +- compatible = "arm,coresight-cpu-debug","arm,primecell"; +- reg = <0 0xf6594000 0 0x1000>; +- clocks = <&sys_ctrl HI6220_DAPB_CLK>; +- clock-names = "apb_pclk"; +- cpu = <&cpu2>; +- }; +- +- debug@f6596000 { +- compatible = "arm,coresight-cpu-debug","arm,primecell"; +- reg = <0 0xf6596000 0 0x1000>; +- clocks = <&sys_ctrl HI6220_DAPB_CLK>; +- clock-names = "apb_pclk"; +- cpu = <&cpu3>; +- }; +- +- debug@f65d0000 { +- compatible = "arm,coresight-cpu-debug","arm,primecell"; +- reg = <0 0xf65d0000 0 0x1000>; +- clocks = <&sys_ctrl HI6220_DAPB_CLK>; +- clock-names = "apb_pclk"; +- cpu = <&cpu4>; +- }; +- +- debug@f65d2000 { +- compatible = "arm,coresight-cpu-debug","arm,primecell"; +- reg = <0 0xf65d2000 0 0x1000>; +- clocks = <&sys_ctrl HI6220_DAPB_CLK>; +- clock-names = "apb_pclk"; +- cpu = <&cpu5>; +- }; +- +- debug@f65d4000 { +- compatible = "arm,coresight-cpu-debug","arm,primecell"; +- reg = <0 0xf65d4000 0 0x1000>; +- clocks = <&sys_ctrl HI6220_DAPB_CLK>; +- clock-names = "apb_pclk"; +- cpu = <&cpu6>; +- }; +- +- debug@f65d6000 { +- compatible = "arm,coresight-cpu-debug","arm,primecell"; +- reg = <0 0xf65d6000 0 0x1000>; +- clocks = <&sys_ctrl HI6220_DAPB_CLK>; +- clock-names = "apb_pclk"; +- cpu = <&cpu7>; +- }; +- +- mali: gpu@f4080000 { +- compatible = "hisilicon,hi6220-mali", "arm,mali-450"; +- reg = <0x0 0xf4080000 0x0 0x00040000>; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- +- interrupt-names = "gp", +- "gpmmu", +- "pp", +- "pp0", +- "ppmmu0", +- "pp1", +- "ppmmu1", +- "pp2", +- "ppmmu2", +- "pp3", +- "ppmmu3"; +- clocks = <&media_ctrl HI6220_G3D_CLK>, +- <&media_ctrl HI6220_G3D_PCLK>; +- clock-names = "bus", "core"; +- assigned-clocks = <&media_ctrl HI6220_G3D_CLK>, +- <&media_ctrl HI6220_G3D_PCLK>; +- assigned-clock-rates = <500000000>, <144000000>; +- reset-names = "ao_g3d", "media_g3d"; +- resets = <&ao_ctrl AO_G3D>, <&media_ctrl MEDIA_G3D>; +- }; +- }; +-}; +- +-#include "hi6220-coresight.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/hikey-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm64/hisilicon/hikey-pinctrl.dtsi +deleted file mode 100644 +index e7d22619a4c0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/hikey-pinctrl.dtsi ++++ /dev/null +@@ -1,706 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * pinctrl dts fils for Hislicon HiKey development board +- * +- */ +-#include +- +-/ { +- soc { +- pmx0: pinmux@f7010000 { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &boot_sel_pmx_func +- &hkadc_ssi_pmx_func +- &codec_clk_pmx_func +- &pwm_in_pmx_func +- &bl_pwm_pmx_func +- >; +- +- boot_sel_pmx_func: boot_sel_pmx_func { +- pinctrl-single,pins = < +- 0x0 MUX_M0 /* BOOT_SEL (IOMG000) */ +- >; +- }; +- +- emmc_pmx_func: emmc_pmx_func { +- pinctrl-single,pins = < +- 0x100 MUX_M0 /* EMMC_CLK (IOMG064) */ +- 0x104 MUX_M0 /* EMMC_CMD (IOMG065) */ +- 0x108 MUX_M0 /* EMMC_DATA0 (IOMG066) */ +- 0x10c MUX_M0 /* EMMC_DATA1 (IOMG067) */ +- 0x110 MUX_M0 /* EMMC_DATA2 (IOMG068) */ +- 0x114 MUX_M0 /* EMMC_DATA3 (IOMG069) */ +- 0x118 MUX_M0 /* EMMC_DATA4 (IOMG070) */ +- 0x11c MUX_M0 /* EMMC_DATA5 (IOMG071) */ +- 0x120 MUX_M0 /* EMMC_DATA6 (IOMG072) */ +- 0x124 MUX_M0 /* EMMC_DATA7 (IOMG073) */ +- >; +- }; +- +- sd_pmx_func: sd_pmx_func { +- pinctrl-single,pins = < +- 0xc MUX_M0 /* SD_CLK (IOMG003) */ +- 0x10 MUX_M0 /* SD_CMD (IOMG004) */ +- 0x14 MUX_M0 /* SD_DATA0 (IOMG005) */ +- 0x18 MUX_M0 /* SD_DATA1 (IOMG006) */ +- 0x1c MUX_M0 /* SD_DATA2 (IOMG007) */ +- 0x20 MUX_M0 /* SD_DATA3 (IOMG008) */ +- >; +- }; +- sd_pmx_idle: sd_pmx_idle { +- pinctrl-single,pins = < +- 0xc MUX_M1 /* SD_CLK (IOMG003) */ +- 0x10 MUX_M1 /* SD_CMD (IOMG004) */ +- 0x14 MUX_M1 /* SD_DATA0 (IOMG005) */ +- 0x18 MUX_M1 /* SD_DATA1 (IOMG006) */ +- 0x1c MUX_M1 /* SD_DATA2 (IOMG007) */ +- 0x20 MUX_M1 /* SD_DATA3 (IOMG008) */ +- >; +- }; +- +- sdio_pmx_func: sdio_pmx_func { +- pinctrl-single,pins = < +- 0x128 MUX_M0 /* SDIO_CLK (IOMG074) */ +- 0x12c MUX_M0 /* SDIO_CMD (IOMG075) */ +- 0x130 MUX_M0 /* SDIO_DATA0 (IOMG076) */ +- 0x134 MUX_M0 /* SDIO_DATA1 (IOMG077) */ +- 0x138 MUX_M0 /* SDIO_DATA2 (IOMG078) */ +- 0x13c MUX_M0 /* SDIO_DATA3 (IOMG079) */ +- >; +- }; +- sdio_pmx_idle: sdio_pmx_idle { +- pinctrl-single,pins = < +- 0x128 MUX_M1 /* SDIO_CLK (IOMG074) */ +- 0x12c MUX_M1 /* SDIO_CMD (IOMG075) */ +- 0x130 MUX_M1 /* SDIO_DATA0 (IOMG076) */ +- 0x134 MUX_M1 /* SDIO_DATA1 (IOMG077) */ +- 0x138 MUX_M1 /* SDIO_DATA2 (IOMG078) */ +- 0x13c MUX_M1 /* SDIO_DATA3 (IOMG079) */ +- >; +- }; +- +- isp_pmx_func: isp_pmx_func { +- pinctrl-single,pins = < +- 0x24 MUX_M0 /* ISP_PWDN0 (IOMG009) */ +- 0x28 MUX_M0 /* ISP_PWDN1 (IOMG010) */ +- 0x2c MUX_M0 /* ISP_PWDN2 (IOMG011) */ +- 0x30 MUX_M1 /* ISP_SHUTTER0 (IOMG012) */ +- 0x34 MUX_M1 /* ISP_SHUTTER1 (IOMG013) */ +- 0x38 MUX_M1 /* ISP_PWM (IOMG014) */ +- 0x3c MUX_M0 /* ISP_CCLK0 (IOMG015) */ +- 0x40 MUX_M0 /* ISP_CCLK1 (IOMG016) */ +- 0x44 MUX_M0 /* ISP_RESETB0 (IOMG017) */ +- 0x48 MUX_M0 /* ISP_RESETB1 (IOMG018) */ +- 0x4c MUX_M1 /* ISP_STROBE0 (IOMG019) */ +- 0x50 MUX_M1 /* ISP_STROBE1 (IOMG020) */ +- 0x54 MUX_M0 /* ISP_SDA0 (IOMG021) */ +- 0x58 MUX_M0 /* ISP_SCL0 (IOMG022) */ +- 0x5c MUX_M0 /* ISP_SDA1 (IOMG023) */ +- 0x60 MUX_M0 /* ISP_SCL1 (IOMG024) */ +- >; +- }; +- +- hkadc_ssi_pmx_func: hkadc_ssi_pmx_func { +- pinctrl-single,pins = < +- 0x68 MUX_M0 /* HKADC_SSI (IOMG026) */ +- >; +- }; +- +- codec_clk_pmx_func: codec_clk_pmx_func { +- pinctrl-single,pins = < +- 0x6c MUX_M0 /* CODEC_CLK (IOMG027) */ +- >; +- }; +- +- codec_pmx_func: codec_pmx_func { +- pinctrl-single,pins = < +- 0x70 MUX_M1 /* DMIC_CLK (IOMG028) */ +- 0x74 MUX_M0 /* CODEC_SYNC (IOMG029) */ +- 0x78 MUX_M0 /* CODEC_DI (IOMG030) */ +- 0x7c MUX_M0 /* CODEC_DO (IOMG031) */ +- >; +- }; +- +- fm_pmx_func: fm_pmx_func { +- pinctrl-single,pins = < +- 0x80 MUX_M1 /* FM_XCLK (IOMG032) */ +- 0x84 MUX_M1 /* FM_XFS (IOMG033) */ +- 0x88 MUX_M1 /* FM_DI (IOMG034) */ +- 0x8c MUX_M1 /* FM_DO (IOMG035) */ +- >; +- }; +- +- bt_pmx_func: bt_pmx_func { +- pinctrl-single,pins = < +- 0x90 MUX_M0 /* BT_XCLK (IOMG036) */ +- 0x94 MUX_M0 /* BT_XFS (IOMG037) */ +- 0x98 MUX_M0 /* BT_DI (IOMG038) */ +- 0x9c MUX_M0 /* BT_DO (IOMG039) */ +- >; +- }; +- +- pwm_in_pmx_func: pwm_in_pmx_func { +- pinctrl-single,pins = < +- 0xb8 MUX_M1 /* PWM_IN (IOMG046) */ +- >; +- }; +- +- bl_pwm_pmx_func: bl_pwm_pmx_func { +- pinctrl-single,pins = < +- 0xbc MUX_M1 /* BL_PWM (IOMG047) */ +- >; +- }; +- +- uart0_pmx_func: uart0_pmx_func { +- pinctrl-single,pins = < +- 0xc0 MUX_M0 /* UART0_RXD (IOMG048) */ +- 0xc4 MUX_M0 /* UART0_TXD (IOMG049) */ +- >; +- }; +- +- uart1_pmx_func: uart1_pmx_func { +- pinctrl-single,pins = < +- 0xc8 MUX_M0 /* UART1_CTS_N (IOMG050) */ +- 0xcc MUX_M0 /* UART1_RTS_N (IOMG051) */ +- 0xd0 MUX_M0 /* UART1_RXD (IOMG052) */ +- 0xd4 MUX_M0 /* UART1_TXD (IOMG053) */ +- >; +- }; +- +- uart2_pmx_func: uart2_pmx_func { +- pinctrl-single,pins = < +- 0xd8 MUX_M0 /* UART2_CTS_N (IOMG054) */ +- 0xdc MUX_M0 /* UART2_RTS_N (IOMG055) */ +- 0xe0 MUX_M0 /* UART2_RXD (IOMG056) */ +- 0xe4 MUX_M0 /* UART2_TXD (IOMG057) */ +- >; +- }; +- +- uart3_pmx_func: uart3_pmx_func { +- pinctrl-single,pins = < +- 0x180 MUX_M1 /* UART3_CTS_N (IOMG096) */ +- 0x184 MUX_M1 /* UART3_RTS_N (IOMG097) */ +- 0x188 MUX_M1 /* UART3_RXD (IOMG098) */ +- 0x18c MUX_M1 /* UART3_TXD (IOMG099) */ +- >; +- }; +- +- uart4_pmx_func: uart4_pmx_func { +- pinctrl-single,pins = < +- 0x1d0 MUX_M1 /* UART4_CTS_N (IOMG116) */ +- 0x1d4 MUX_M1 /* UART4_RTS_N (IOMG117) */ +- 0x1d8 MUX_M1 /* UART4_RXD (IOMG118) */ +- 0x1dc MUX_M1 /* UART4_TXD (IOMG119) */ +- >; +- }; +- +- uart5_pmx_func: uart5_pmx_func { +- pinctrl-single,pins = < +- 0x1c8 MUX_M1 /* UART5_RXD (IOMG114) */ +- 0x1cc MUX_M1 /* UART5_TXD (IOMG115) */ +- >; +- }; +- +- i2c0_pmx_func: i2c0_pmx_func { +- pinctrl-single,pins = < +- 0xe8 MUX_M0 /* I2C0_SCL (IOMG058) */ +- 0xec MUX_M0 /* I2C0_SDA (IOMG059) */ +- >; +- }; +- +- i2c1_pmx_func: i2c1_pmx_func { +- pinctrl-single,pins = < +- 0xf0 MUX_M0 /* I2C1_SCL (IOMG060) */ +- 0xf4 MUX_M0 /* I2C1_SDA (IOMG061) */ +- >; +- }; +- +- i2c2_pmx_func: i2c2_pmx_func { +- pinctrl-single,pins = < +- 0xf8 MUX_M0 /* I2C2_SCL (IOMG062) */ +- 0xfc MUX_M0 /* I2C2_SDA (IOMG063) */ +- >; +- }; +- +- spi0_pmx_func: spi0_pmx_func { +- pinctrl-single,pins = < +- 0x1a0 MUX_M1 /* SPI0_DI (IOMG104) */ +- 0x1a4 MUX_M1 /* SPI0_DO (IOMG105) */ +- 0x1a8 MUX_M1 /* SPI0_CS_N (IOMG106) */ +- 0x1ac MUX_M1 /* SPI0_CLK (IOMG107) */ +- >; +- }; +- }; +- +- pmx1: pinmux@f7010800 { +- +- pinctrl-names = "default"; +- pinctrl-0 = < +- &boot_sel_cfg_func +- &hkadc_ssi_cfg_func +- &codec_clk_cfg_func +- &pwm_in_cfg_func +- &bl_pwm_cfg_func +- >; +- +- boot_sel_cfg_func: boot_sel_cfg_func { +- pinctrl-single,pins = < +- 0x0 0x0 /* BOOT_SEL (IOCFG000) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- hkadc_ssi_cfg_func: hkadc_ssi_cfg_func { +- pinctrl-single,pins = < +- 0x6c 0x0 /* HKADC_SSI (IOCFG027) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- emmc_clk_cfg_func: emmc_clk_cfg_func { +- pinctrl-single,pins = < +- 0x104 0x0 /* EMMC_CLK (IOCFG065) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- emmc_cfg_func: emmc_cfg_func { +- pinctrl-single,pins = < +- 0x108 0x0 /* EMMC_CMD (IOCFG066) */ +- 0x10c 0x0 /* EMMC_DATA0 (IOCFG067) */ +- 0x110 0x0 /* EMMC_DATA1 (IOCFG068) */ +- 0x114 0x0 /* EMMC_DATA2 (IOCFG069) */ +- 0x118 0x0 /* EMMC_DATA3 (IOCFG070) */ +- 0x11c 0x0 /* EMMC_DATA4 (IOCFG071) */ +- 0x120 0x0 /* EMMC_DATA5 (IOCFG072) */ +- 0x124 0x0 /* EMMC_DATA6 (IOCFG073) */ +- 0x128 0x0 /* EMMC_DATA7 (IOCFG074) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- emmc_rst_cfg_func: emmc_rst_cfg_func { +- pinctrl-single,pins = < +- 0x12c 0x0 /* EMMC_RST_N (IOCFG075) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- sd_clk_cfg_func: sd_clk_cfg_func { +- pinctrl-single,pins = < +- 0xc 0x0 /* SD_CLK (IOCFG003) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- sd_clk_cfg_idle: sd_clk_cfg_idle { +- pinctrl-single,pins = < +- 0xc 0x0 /* SD_CLK (IOCFG003) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- sd_cfg_func: sd_cfg_func { +- pinctrl-single,pins = < +- 0x10 0x0 /* SD_CMD (IOCFG004) */ +- 0x14 0x0 /* SD_DATA0 (IOCFG005) */ +- 0x18 0x0 /* SD_DATA1 (IOCFG006) */ +- 0x1c 0x0 /* SD_DATA2 (IOCFG007) */ +- 0x20 0x0 /* SD_DATA3 (IOCFG008) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- sd_cfg_idle: sd_cfg_idle { +- pinctrl-single,pins = < +- 0x10 0x0 /* SD_CMD (IOCFG004) */ +- 0x14 0x0 /* SD_DATA0 (IOCFG005) */ +- 0x18 0x0 /* SD_DATA1 (IOCFG006) */ +- 0x1c 0x0 /* SD_DATA2 (IOCFG007) */ +- 0x20 0x0 /* SD_DATA3 (IOCFG008) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- sdio_clk_cfg_func: sdio_clk_cfg_func { +- pinctrl-single,pins = < +- 0x134 0x0 /* SDIO_CLK (IOCFG077) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- sdio_clk_cfg_idle: sdio_clk_cfg_idle { +- pinctrl-single,pins = < +- 0x134 0x0 /* SDIO_CLK (IOCFG077) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- sdio_cfg_func: sdio_cfg_func { +- pinctrl-single,pins = < +- 0x138 0x0 /* SDIO_CMD (IOCFG078) */ +- 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */ +- 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */ +- 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */ +- 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- sdio_cfg_idle: sdio_cfg_idle { +- pinctrl-single,pins = < +- 0x138 0x0 /* SDIO_CMD (IOCFG078) */ +- 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */ +- 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */ +- 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */ +- 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- isp_cfg_func1: isp_cfg_func1 { +- pinctrl-single,pins = < +- 0x28 0x0 /* ISP_PWDN0 (IOCFG010) */ +- 0x2c 0x0 /* ISP_PWDN1 (IOCFG011) */ +- 0x30 0x0 /* ISP_PWDN2 (IOCFG012) */ +- 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */ +- 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */ +- 0x3c 0x0 /* ISP_PWM (IOCFG015) */ +- 0x40 0x0 /* ISP_CCLK0 (IOCFG016) */ +- 0x44 0x0 /* ISP_CCLK1 (IOCFG017) */ +- 0x48 0x0 /* ISP_RESETB0 (IOCFG018) */ +- 0x4c 0x0 /* ISP_RESETB1 (IOCFG019) */ +- 0x50 0x0 /* ISP_STROBE0 (IOCFG020) */ +- 0x58 0x0 /* ISP_SDA0 (IOCFG022) */ +- 0x5c 0x0 /* ISP_SCL0 (IOCFG023) */ +- 0x60 0x0 /* ISP_SDA1 (IOCFG024) */ +- 0x64 0x0 /* ISP_SCL1 (IOCFG025) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- isp_cfg_idle1: isp_cfg_idle1 { +- pinctrl-single,pins = < +- 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */ +- 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- isp_cfg_func2: isp_cfg_func2 { +- pinctrl-single,pins = < +- 0x54 0x0 /* ISP_STROBE1 (IOCFG021) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- codec_clk_cfg_func: codec_clk_cfg_func { +- pinctrl-single,pins = < +- 0x70 0x0 /* CODEC_CLK (IOCFG028) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- codec_clk_cfg_idle: codec_clk_cfg_idle { +- pinctrl-single,pins = < +- 0x70 0x0 /* CODEC_CLK (IOCFG028) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- codec_cfg_func1: codec_cfg_func1 { +- pinctrl-single,pins = < +- 0x74 0x0 /* DMIC_CLK (IOCFG029) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- codec_cfg_func2: codec_cfg_func2 { +- pinctrl-single,pins = < +- 0x78 0x0 /* CODEC_SYNC (IOCFG030) */ +- 0x7c 0x0 /* CODEC_DI (IOCFG031) */ +- 0x80 0x0 /* CODEC_DO (IOCFG032) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- codec_cfg_idle2: codec_cfg_idle2 { +- pinctrl-single,pins = < +- 0x78 0x0 /* CODEC_SYNC (IOCFG030) */ +- 0x7c 0x0 /* CODEC_DI (IOCFG031) */ +- 0x80 0x0 /* CODEC_DO (IOCFG032) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- fm_cfg_func: fm_cfg_func { +- pinctrl-single,pins = < +- 0x84 0x0 /* FM_XCLK (IOCFG033) */ +- 0x88 0x0 /* FM_XFS (IOCFG034) */ +- 0x8c 0x0 /* FM_DI (IOCFG035) */ +- 0x90 0x0 /* FM_DO (IOCFG036) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- bt_cfg_func: bt_cfg_func { +- pinctrl-single,pins = < +- 0x94 0x0 /* BT_XCLK (IOCFG037) */ +- 0x98 0x0 /* BT_XFS (IOCFG038) */ +- 0x9c 0x0 /* BT_DI (IOCFG039) */ +- 0xa0 0x0 /* BT_DO (IOCFG040) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- bt_cfg_idle: bt_cfg_idle { +- pinctrl-single,pins = < +- 0x94 0x0 /* BT_XCLK (IOCFG037) */ +- 0x98 0x0 /* BT_XFS (IOCFG038) */ +- 0x9c 0x0 /* BT_DI (IOCFG039) */ +- 0xa0 0x0 /* BT_DO (IOCFG040) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- pwm_in_cfg_func: pwm_in_cfg_func { +- pinctrl-single,pins = < +- 0xbc 0x0 /* PWM_IN (IOCFG047) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- bl_pwm_cfg_func: bl_pwm_cfg_func { +- pinctrl-single,pins = < +- 0xc0 0x0 /* BL_PWM (IOCFG048) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- uart0_cfg_func1: uart0_cfg_func1 { +- pinctrl-single,pins = < +- 0xc4 0x0 /* UART0_RXD (IOCFG049) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- uart0_cfg_func2: uart0_cfg_func2 { +- pinctrl-single,pins = < +- 0xc8 0x0 /* UART0_TXD (IOCFG050) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- uart1_cfg_func1: uart1_cfg_func1 { +- pinctrl-single,pins = < +- 0xcc 0x0 /* UART1_CTS_N (IOCFG051) */ +- 0xd4 0x0 /* UART1_RXD (IOCFG053) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- uart1_cfg_func2: uart1_cfg_func2 { +- pinctrl-single,pins = < +- 0xd0 0x0 /* UART1_RTS_N (IOCFG052) */ +- 0xd8 0x0 /* UART1_TXD (IOCFG054) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- uart2_cfg_func: uart2_cfg_func { +- pinctrl-single,pins = < +- 0xdc 0x0 /* UART2_CTS_N (IOCFG055) */ +- 0xe0 0x0 /* UART2_RTS_N (IOCFG056) */ +- 0xe4 0x0 /* UART2_RXD (IOCFG057) */ +- 0xe8 0x0 /* UART2_TXD (IOCFG058) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- uart3_cfg_func: uart3_cfg_func { +- pinctrl-single,pins = < +- 0x190 0x0 /* UART3_CTS_N (IOCFG100) */ +- 0x194 0x0 /* UART3_RTS_N (IOCFG101) */ +- 0x198 0x0 /* UART3_RXD (IOCFG102) */ +- 0x19c 0x0 /* UART3_TXD (IOCFG103) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- uart4_cfg_func: uart4_cfg_func { +- pinctrl-single,pins = < +- 0x1e0 0x0 /* UART4_CTS_N (IOCFG120) */ +- 0x1e4 0x0 /* UART4_RTS_N (IOCFG121) */ +- 0x1e8 0x0 /* UART4_RXD (IOCFG122) */ +- 0x1ec 0x0 /* UART4_TXD (IOCFG123) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- uart5_cfg_func: uart5_cfg_func { +- pinctrl-single,pins = < +- 0x1d8 0x0 /* UART4_RXD (IOCFG118) */ +- 0x1dc 0x0 /* UART4_TXD (IOCFG119) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- i2c0_cfg_func: i2c0_cfg_func { +- pinctrl-single,pins = < +- 0xec 0x0 /* I2C0_SCL (IOCFG059) */ +- 0xf0 0x0 /* I2C0_SDA (IOCFG060) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- i2c1_cfg_func: i2c1_cfg_func { +- pinctrl-single,pins = < +- 0xf4 0x0 /* I2C1_SCL (IOCFG061) */ +- 0xf8 0x0 /* I2C1_SDA (IOCFG062) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- i2c2_cfg_func: i2c2_cfg_func { +- pinctrl-single,pins = < +- 0xfc 0x0 /* I2C2_SCL (IOCFG063) */ +- 0x100 0x0 /* I2C2_SDA (IOCFG064) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- spi0_cfg_func: spi0_cfg_func { +- pinctrl-single,pins = < +- 0x1b0 0x0 /* SPI0_DI (IOCFG108) */ +- 0x1b4 0x0 /* SPI0_DO (IOCFG109) */ +- 0x1b8 0x0 /* SPI0_CS_N (IOCFG110) */ +- 0x1bc 0x0 /* SPI0_CLK (IOCFG111) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- }; +- +- pmx2: pinmux@f8001800 { +- +- pinctrl-names = "default"; +- pinctrl-0 = < +- &rstout_n_cfg_func +- >; +- +- rstout_n_cfg_func: rstout_n_cfg_func { +- pinctrl-single,pins = < +- 0x0 0x0 /* RSTOUT_N (IOCFG000) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- pmu_peri_en_cfg_func: pmu_peri_en_cfg_func { +- pinctrl-single,pins = < +- 0x4 0x0 /* PMU_PERI_EN (IOCFG001) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- sysclk0_en_cfg_func: sysclk0_en_cfg_func { +- pinctrl-single,pins = < +- 0x8 0x0 /* SYSCLK0_EN (IOCFG002) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- jtag_tdo_cfg_func: jtag_tdo_cfg_func { +- pinctrl-single,pins = < +- 0xc 0x0 /* JTAG_TDO (IOCFG003) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- +- rf_reset_cfg_func: rf_reset_cfg_func { +- pinctrl-single,pins = < +- 0x70 0x0 /* RF_RESET0 (IOCFG028) */ +- 0x74 0x0 /* RF_RESET1 (IOCFG029) */ +- >; +- pinctrl-single,bias-pulldown = ; +- pinctrl-single,bias-pullup = ; +- pinctrl-single,drive-strength = ; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/hikey960-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm64/hisilicon/hikey960-pinctrl.dtsi +deleted file mode 100644 +index 920a3111c66d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/hikey960-pinctrl.dtsi ++++ /dev/null +@@ -1,1060 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * pinctrl dts fils for Hislicon HiKey960 development board +- * +- */ +- +-#include +- +-/ { +- soc { +- /* [IOMG_000, IOMG_123] */ +- range: gpio-range { +- #pinctrl-single,gpio-range-cells = <3>; +- }; +- +- pmx0: pinmux@e896c000 { +- compatible = "pinctrl-single"; +- reg = <0x0 0xe896c000 0x0 0x1f0>; +- #pinctrl-cells = <1>; +- #gpio-range-cells = <0x3>; +- pinctrl-single,register-width = <0x20>; +- pinctrl-single,function-mask = <0x7>; +- /* pin base, nr pins & gpio function */ +- pinctrl-single,gpio-range = < +- &range 0 7 0 +- &range 8 116 0>; +- +- pmu_pmx_func: pmu_pmx_func { +- pinctrl-single,pins = < +- 0x008 MUX_M1 /* PMU1_SSI */ +- 0x00c MUX_M1 /* PMU2_SSI */ +- 0x010 MUX_M1 /* PMU_CLKOUT */ +- 0x100 MUX_M1 /* PMU_HKADC_SSI */ +- >; +- }; +- +- csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func { +- pinctrl-single,pins = < +- 0x044 MUX_M0 /* CSI0_PWD_N */ +- >; +- }; +- +- csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func { +- pinctrl-single,pins = < +- 0x04c MUX_M0 /* CSI1_PWD_N */ +- >; +- }; +- +- isp0_pmx_func: isp0_pmx_func { +- pinctrl-single,pins = < +- 0x058 MUX_M1 /* ISP_CLK0 */ +- 0x064 MUX_M1 /* ISP_SCL0 */ +- 0x068 MUX_M1 /* ISP_SDA0 */ +- >; +- }; +- +- isp1_pmx_func: isp1_pmx_func { +- pinctrl-single,pins = < +- 0x05c MUX_M1 /* ISP_CLK1 */ +- 0x06c MUX_M1 /* ISP_SCL1 */ +- 0x070 MUX_M1 /* ISP_SDA1 */ +- >; +- }; +- +- pwr_key_pmx_func: pwr_key_pmx_func { +- pinctrl-single,pins = < +- 0x080 MUX_M0 /* GPIO_034 */ +- >; +- }; +- +- i2c3_pmx_func: i2c3_pmx_func { +- pinctrl-single,pins = < +- 0x02c MUX_M1 /* I2C3_SCL */ +- 0x030 MUX_M1 /* I2C3_SDA */ +- >; +- }; +- +- i2c4_pmx_func: i2c4_pmx_func { +- pinctrl-single,pins = < +- 0x090 MUX_M1 /* I2C4_SCL */ +- 0x094 MUX_M1 /* I2C4_SDA */ +- >; +- }; +- +- pcie_perstn_pmx_func: pcie_perstn_pmx_func { +- pinctrl-single,pins = < +- 0x15c MUX_M1 /* PCIE_PERST_N */ +- >; +- }; +- +- usbhub5734_pmx_func: usbhub5734_pmx_func { +- pinctrl-single,pins = < +- 0x11c MUX_M0 /* GPIO_073 */ +- 0x120 MUX_M0 /* GPIO_074 */ +- >; +- }; +- +- uart0_pmx_func: uart0_pmx_func { +- pinctrl-single,pins = < +- 0x0cc MUX_M2 /* UART0_RXD */ +- 0x0d0 MUX_M2 /* UART0_TXD */ +- >; +- }; +- +- uart1_pmx_func: uart1_pmx_func { +- pinctrl-single,pins = < +- 0x0b0 MUX_M2 /* UART1_CTS_N */ +- 0x0b4 MUX_M2 /* UART1_RTS_N */ +- 0x0a8 MUX_M2 /* UART1_RXD */ +- 0x0ac MUX_M2 /* UART1_TXD */ +- >; +- }; +- +- uart2_pmx_func: uart2_pmx_func { +- pinctrl-single,pins = < +- 0x0bc MUX_M2 /* UART2_CTS_N */ +- 0x0c0 MUX_M2 /* UART2_RTS_N */ +- 0x0c8 MUX_M2 /* UART2_RXD */ +- 0x0c4 MUX_M2 /* UART2_TXD */ +- >; +- }; +- +- uart3_pmx_func: uart3_pmx_func { +- pinctrl-single,pins = < +- 0x0dc MUX_M1 /* UART3_CTS_N */ +- 0x0e0 MUX_M1 /* UART3_RTS_N */ +- 0x0e4 MUX_M1 /* UART3_RXD */ +- 0x0e8 MUX_M1 /* UART3_TXD */ +- >; +- }; +- +- uart4_pmx_func: uart4_pmx_func { +- pinctrl-single,pins = < +- 0x0ec MUX_M1 /* UART4_CTS_N */ +- 0x0f0 MUX_M1 /* UART4_RTS_N */ +- 0x0f4 MUX_M1 /* UART4_RXD */ +- 0x0f8 MUX_M1 /* UART4_TXD */ +- >; +- }; +- +- uart5_pmx_func: uart5_pmx_func { +- pinctrl-single,pins = < +- 0x0c4 MUX_M3 /* UART5_CTS_N */ +- 0x0c8 MUX_M3 /* UART5_RTS_N */ +- 0x0bc MUX_M3 /* UART5_RXD */ +- 0x0c0 MUX_M3 /* UART5_TXD */ +- >; +- }; +- +- uart6_pmx_func: uart6_pmx_func { +- pinctrl-single,pins = < +- 0x0cc MUX_M1 /* UART6_CTS_N */ +- 0x0d0 MUX_M1 /* UART6_RTS_N */ +- 0x0d4 MUX_M1 /* UART6_RXD */ +- 0x0d8 MUX_M1 /* UART6_TXD */ +- >; +- }; +- +- cam0_rst_pmx_func: cam0_rst_pmx_func { +- pinctrl-single,pins = < +- 0x0c8 MUX_M0 /* CAM0_RST */ +- >; +- }; +- +- cam1_rst_pmx_func: cam1_rst_pmx_func { +- pinctrl-single,pins = < +- 0x124 MUX_M0 /* CAM1_RST */ +- >; +- }; +- }; +- +- /* [IOMG_MMC0_000, IOMG_MMC0_005] */ +- pmx1: pinmux@ff37e000 { +- compatible = "pinctrl-single"; +- reg = <0x0 0xff37e000 0x0 0x18>; +- #gpio-range-cells = <0x3>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <0x20>; +- pinctrl-single,function-mask = <0x7>; +- /* pin base, nr pins & gpio function */ +- pinctrl-single,gpio-range = <&range 0 6 0>; +- +- sd_pmx_func: sd_pmx_func { +- pinctrl-single,pins = < +- 0x000 MUX_M1 /* SD_CLK */ +- 0x004 MUX_M1 /* SD_CMD */ +- 0x008 MUX_M1 /* SD_DATA0 */ +- 0x00c MUX_M1 /* SD_DATA1 */ +- 0x010 MUX_M1 /* SD_DATA2 */ +- 0x014 MUX_M1 /* SD_DATA3 */ +- >; +- }; +- }; +- +- /* [IOMG_FIX_000, IOMG_FIX_011] */ +- pmx2: pinmux@ff3b6000 { +- compatible = "pinctrl-single"; +- reg = <0x0 0xff3b6000 0x0 0x30>; +- #pinctrl-cells = <1>; +- #gpio-range-cells = <0x3>; +- pinctrl-single,register-width = <0x20>; +- pinctrl-single,function-mask = <0x7>; +- /* pin base, nr pins & gpio function */ +- pinctrl-single,gpio-range = <&range 0 12 0>; +- +- ufs_pmx_func: ufs_pmx_func { +- pinctrl-single,pins = < +- 0x000 MUX_M1 /* UFS_REF_CLK */ +- 0x004 MUX_M1 /* UFS_RST_N */ +- >; +- }; +- +- spi3_pmx_func: spi3_pmx_func { +- pinctrl-single,pins = < +- 0x008 MUX_M1 /* SPI3_CLK */ +- 0x00c MUX_M1 /* SPI3_DI */ +- 0x010 MUX_M1 /* SPI3_DO */ +- 0x014 MUX_M1 /* SPI3_CS0_N */ +- >; +- }; +- }; +- +- /* [IOMG_MMC1_000, IOMG_MMC1_005] */ +- pmx3: pinmux@ff3fd000 { +- compatible = "pinctrl-single"; +- reg = <0x0 0xff3fd000 0x0 0x18>; +- #pinctrl-cells = <1>; +- #gpio-range-cells = <0x3>; +- pinctrl-single,register-width = <0x20>; +- pinctrl-single,function-mask = <0x7>; +- /* pin base, nr pins & gpio function */ +- pinctrl-single,gpio-range = <&range 0 6 0>; +- +- sdio_pmx_func: sdio_pmx_func { +- pinctrl-single,pins = < +- 0x000 MUX_M1 /* SDIO_CLK */ +- 0x004 MUX_M1 /* SDIO_CMD */ +- 0x008 MUX_M1 /* SDIO_DATA0 */ +- 0x00c MUX_M1 /* SDIO_DATA1 */ +- 0x010 MUX_M1 /* SDIO_DATA2 */ +- 0x014 MUX_M1 /* SDIO_DATA3 */ +- >; +- }; +- }; +- +- /* [IOMG_AO_000, IOMG_AO_041] */ +- pmx4: pinmux@fff11000 { +- compatible = "pinctrl-single"; +- reg = <0x0 0xfff11000 0x0 0xa8>; +- #pinctrl-cells = <1>; +- #gpio-range-cells = <0x3>; +- pinctrl-single,register-width = <0x20>; +- pinctrl-single,function-mask = <0x7>; +- /* pin base in node, nr pins & gpio function */ +- pinctrl-single,gpio-range = <&range 0 42 0>; +- +- i2s2_pmx_func: i2s2_pmx_func { +- pinctrl-single,pins = < +- 0x044 MUX_M1 /* I2S2_DI */ +- 0x048 MUX_M1 /* I2S2_DO */ +- 0x04c MUX_M1 /* I2S2_XCLK */ +- 0x050 MUX_M1 /* I2S2_XFS */ +- >; +- }; +- +- slimbus_pmx_func: slimbus_pmx_func { +- pinctrl-single,pins = < +- 0x02c MUX_M1 /* SLIMBUS_CLK */ +- 0x030 MUX_M1 /* SLIMBUS_DATA */ +- >; +- }; +- +- i2c0_pmx_func: i2c0_pmx_func { +- pinctrl-single,pins = < +- 0x014 MUX_M1 /* I2C0_SCL */ +- 0x018 MUX_M1 /* I2C0_SDA */ +- >; +- }; +- +- i2c1_pmx_func: i2c1_pmx_func { +- pinctrl-single,pins = < +- 0x01c MUX_M1 /* I2C1_SCL */ +- 0x020 MUX_M1 /* I2C1_SDA */ +- >; +- }; +- +- i2c7_pmx_func: i2c7_pmx_func { +- pinctrl-single,pins = < +- 0x024 MUX_M3 /* I2C7_SCL */ +- 0x028 MUX_M3 /* I2C7_SDA */ +- >; +- }; +- +- pcie_pmx_func: pcie_pmx_func { +- pinctrl-single,pins = < +- 0x084 MUX_M1 /* PCIE_CLKREQ_N */ +- 0x088 MUX_M1 /* PCIE_WAKE_N */ +- >; +- }; +- +- spi2_pmx_func: spi2_pmx_func { +- pinctrl-single,pins = < +- 0x08c MUX_M1 /* SPI2_CLK */ +- 0x090 MUX_M1 /* SPI2_DI */ +- 0x094 MUX_M1 /* SPI2_DO */ +- 0x098 MUX_M1 /* SPI2_CS0_N */ +- >; +- }; +- +- i2s0_pmx_func: i2s0_pmx_func { +- pinctrl-single,pins = < +- 0x034 MUX_M1 /* I2S0_DI */ +- 0x038 MUX_M1 /* I2S0_DO */ +- 0x03c MUX_M1 /* I2S0_XCLK */ +- 0x040 MUX_M1 /* I2S0_XFS */ +- >; +- }; +- }; +- +- pmx5: pinmux@e896c800 { +- compatible = "pinconf-single"; +- reg = <0x0 0xe896c800 0x0 0x200>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <0x20>; +- +- pmu_cfg_func: pmu_cfg_func { +- pinctrl-single,pins = < +- 0x010 0x0 /* PMU1_SSI */ +- 0x014 0x0 /* PMU2_SSI */ +- 0x018 0x0 /* PMU_CLKOUT */ +- 0x10c 0x0 /* PMU_HKADC_SSI */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_06MA DRIVE6_MASK +- >; +- }; +- +- i2c3_cfg_func: i2c3_cfg_func { +- pinctrl-single,pins = < +- 0x038 0x0 /* I2C3_SCL */ +- 0x03c 0x0 /* I2C3_SDA */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func { +- pinctrl-single,pins = < +- 0x050 0x0 /* CSI0_PWD_N */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- +- csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func { +- pinctrl-single,pins = < +- 0x058 0x0 /* CSI1_PWD_N */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- +- isp0_cfg_func: isp0_cfg_func { +- pinctrl-single,pins = < +- 0x064 0x0 /* ISP_CLK0 */ +- 0x070 0x0 /* ISP_SCL0 */ +- 0x074 0x0 /* ISP_SDA0 */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK>; +- }; +- +- isp1_cfg_func: isp1_cfg_func { +- pinctrl-single,pins = < +- 0x068 0x0 /* ISP_CLK1 */ +- 0x078 0x0 /* ISP_SCL1 */ +- 0x07c 0x0 /* ISP_SDA1 */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- +- pwr_key_cfg_func: pwr_key_cfg_func { +- pinctrl-single,pins = < +- 0x08c 0x0 /* GPIO_034 */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- uart1_cfg_func: uart1_cfg_func { +- pinctrl-single,pins = < +- 0x0b4 0x0 /* UART1_RXD */ +- 0x0b8 0x0 /* UART1_TXD */ +- 0x0bc 0x0 /* UART1_CTS_N */ +- 0x0c0 0x0 /* UART1_RTS_N */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- uart2_cfg_func: uart2_cfg_func { +- pinctrl-single,pins = < +- 0x0c8 0x0 /* UART2_CTS_N */ +- 0x0cc 0x0 /* UART2_RTS_N */ +- 0x0d0 0x0 /* UART2_TXD */ +- 0x0d4 0x0 /* UART2_RXD */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- uart5_cfg_func: uart5_cfg_func { +- pinctrl-single,pins = < +- 0x0c8 0x0 /* UART5_RXD */ +- 0x0cc 0x0 /* UART5_TXD */ +- 0x0d0 0x0 /* UART5_CTS_N */ +- 0x0d4 0x0 /* UART5_RTS_N */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- cam0_rst_cfg_func: cam0_rst_cfg_func { +- pinctrl-single,pins = < +- 0x0d4 0x0 /* CAM0_RST */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- +- uart0_cfg_func: uart0_cfg_func { +- pinctrl-single,pins = < +- 0x0d8 0x0 /* UART0_RXD */ +- 0x0dc 0x0 /* UART0_TXD */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- uart6_cfg_func: uart6_cfg_func { +- pinctrl-single,pins = < +- 0x0d8 0x0 /* UART6_CTS_N */ +- 0x0dc 0x0 /* UART6_RTS_N */ +- 0x0e0 0x0 /* UART6_RXD */ +- 0x0e4 0x0 /* UART6_TXD */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- uart3_cfg_func: uart3_cfg_func { +- pinctrl-single,pins = < +- 0x0e8 0x0 /* UART3_CTS_N */ +- 0x0ec 0x0 /* UART3_RTS_N */ +- 0x0f0 0x0 /* UART3_RXD */ +- 0x0f4 0x0 /* UART3_TXD */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- uart4_cfg_func: uart4_cfg_func { +- pinctrl-single,pins = < +- 0x0f8 0x0 /* UART4_CTS_N */ +- 0x0fc 0x0 /* UART4_RTS_N */ +- 0x100 0x0 /* UART4_RXD */ +- 0x104 0x0 /* UART4_TXD */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- cam1_rst_cfg_func: cam1_rst_cfg_func { +- pinctrl-single,pins = < +- 0x130 0x0 /* CAM1_RST */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- }; +- +- pmx6: pinmux@ff3b6800 { +- compatible = "pinconf-single"; +- reg = <0x0 0xff3b6800 0x0 0x18>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <0x20>; +- +- ufs_cfg_func: ufs_cfg_func { +- pinctrl-single,pins = < +- 0x000 0x0 /* UFS_REF_CLK */ +- 0x004 0x0 /* UFS_RST_N */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_08MA DRIVE6_MASK +- >; +- }; +- +- spi3_cfg_func: spi3_cfg_func { +- pinctrl-single,pins = < +- 0x008 0x0 /* SPI3_CLK */ +- 0x00c 0x0 /* SPI3_DI */ +- 0x010 0x0 /* SPI3_DO */ +- 0x014 0x0 /* SPI3_CS0_N */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_06MA DRIVE6_MASK +- >; +- }; +- }; +- +- pmx7: pinmux@ff3fd800 { +- compatible = "pinconf-single"; +- reg = <0x0 0xff3fd800 0x0 0x18>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <0x20>; +- +- sdio_clk_cfg_func: sdio_clk_cfg_func { +- pinctrl-single,pins = < +- 0x000 0x0 /* SDIO_CLK */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE6_32MA DRIVE6_MASK +- >; +- }; +- +- sdio_cfg_func: sdio_cfg_func { +- pinctrl-single,pins = < +- 0x004 0x0 /* SDIO_CMD */ +- 0x008 0x0 /* SDIO_DATA0 */ +- 0x00c 0x0 /* SDIO_DATA1 */ +- 0x010 0x0 /* SDIO_DATA2 */ +- 0x014 0x0 /* SDIO_DATA3 */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_UP +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE6_19MA DRIVE6_MASK +- >; +- }; +- }; +- +- pmx8: pinmux@ff37e800 { +- compatible = "pinconf-single"; +- reg = <0x0 0xff37e800 0x0 0x18>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <0x20>; +- +- sd_clk_cfg_func: sd_clk_cfg_func { +- pinctrl-single,pins = < +- 0x000 0x0 /* SD_CLK */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE6_32MA +- DRIVE6_MASK +- >; +- }; +- +- sd_cfg_func: sd_cfg_func { +- pinctrl-single,pins = < +- 0x004 0x0 /* SD_CMD */ +- 0x008 0x0 /* SD_DATA0 */ +- 0x00c 0x0 /* SD_DATA1 */ +- 0x010 0x0 /* SD_DATA2 */ +- 0x014 0x0 /* SD_DATA3 */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_UP +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE6_19MA +- DRIVE6_MASK +- >; +- }; +- }; +- +- pmx9: pinmux@fff11800 { +- compatible = "pinconf-single"; +- reg = <0x0 0xfff11800 0x0 0xbc>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <0x20>; +- +- i2c0_cfg_func: i2c0_cfg_func { +- pinctrl-single,pins = < +- 0x01c 0x0 /* I2C0_SCL */ +- 0x020 0x0 /* I2C0_SDA */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_UP +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- i2c1_cfg_func: i2c1_cfg_func { +- pinctrl-single,pins = < +- 0x024 0x0 /* I2C1_SCL */ +- 0x028 0x0 /* I2C1_SDA */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_UP +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- i2c7_cfg_func: i2c7_cfg_func { +- pinctrl-single,pins = < +- 0x02c 0x0 /* I2C7_SCL */ +- 0x030 0x0 /* I2C7_SDA */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_UP +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- slimbus_cfg_func: slimbus_cfg_func { +- pinctrl-single,pins = < +- 0x034 0x0 /* SLIMBUS_CLK */ +- 0x038 0x0 /* SLIMBUS_DATA */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_UP +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- i2s0_cfg_func: i2s0_cfg_func { +- pinctrl-single,pins = < +- 0x040 0x0 /* I2S0_DI */ +- 0x044 0x0 /* I2S0_DO */ +- 0x048 0x0 /* I2S0_XCLK */ +- 0x04c 0x0 /* I2S0_XFS */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_UP +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- i2s2_cfg_func: i2s2_cfg_func { +- pinctrl-single,pins = < +- 0x050 0x0 /* I2S2_DI */ +- 0x054 0x0 /* I2S2_DO */ +- 0x058 0x0 /* I2S2_XCLK */ +- 0x05c 0x0 /* I2S2_XFS */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_UP +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- pcie_cfg_func: pcie_cfg_func { +- pinctrl-single,pins = < +- 0x094 0x0 /* PCIE_CLKREQ_N */ +- 0x098 0x0 /* PCIE_WAKE_N */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_UP +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- spi2_cfg_func: spi2_cfg_func { +- pinctrl-single,pins = < +- 0x09c 0x0 /* SPI2_CLK */ +- 0x0a0 0x0 /* SPI2_DI */ +- 0x0a4 0x0 /* SPI2_DO */ +- 0x0a8 0x0 /* SPI2_CS0_N */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_UP +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_06MA DRIVE6_MASK +- >; +- }; +- +- usb_cfg_func: usb_cfg_func { +- pinctrl-single,pins = < +- 0x0ac 0x0 /* GPIO_219 */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_UP +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/hikey970-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm64/hisilicon/hikey970-pinctrl.dtsi +deleted file mode 100644 +index 77bd8c3a8314..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/hikey970-pinctrl.dtsi ++++ /dev/null +@@ -1,969 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Pinctrl dts file for HiSilicon HiKey970 development board +- */ +- +-#include +- +-/ { +- soc { +- range: gpio-range { +- #pinctrl-single,gpio-range-cells = <3>; +- }; +- +- pmx0: pinmux@e896c000 { +- compatible = "pinctrl-single"; +- reg = <0x0 0xe896c000 0x0 0x72c>; +- #pinctrl-cells = <1>; +- #gpio-range-cells = <0x3>; +- pinctrl-single,register-width = <0x20>; +- pinctrl-single,function-mask = <0x7>; +- /* pin base, nr pins & gpio function */ +- pinctrl-single,gpio-range = <&range 0 82 0>; +- +- uart0_pmx_func: uart0_pmx_func { +- pinctrl-single,pins = < +- 0x054 MUX_M2 /* UART0_RXD */ +- 0x058 MUX_M2 /* UART0_TXD */ +- >; +- }; +- +- uart2_pmx_func: uart2_pmx_func { +- pinctrl-single,pins = < +- 0x700 MUX_M2 /* UART2_CTS_N */ +- 0x704 MUX_M2 /* UART2_RTS_N */ +- 0x708 MUX_M2 /* UART2_RXD */ +- 0x70c MUX_M2 /* UART2_TXD */ +- >; +- }; +- +- uart3_pmx_func: uart3_pmx_func { +- pinctrl-single,pins = < +- 0x064 MUX_M1 /* UART3_CTS_N */ +- 0x068 MUX_M1 /* UART3_RTS_N */ +- 0x06c MUX_M1 /* UART3_RXD */ +- 0x070 MUX_M1 /* UART3_TXD */ +- >; +- }; +- +- uart4_pmx_func: uart4_pmx_func { +- pinctrl-single,pins = < +- 0x074 MUX_M1 /* UART4_CTS_N */ +- 0x078 MUX_M1 /* UART4_RTS_N */ +- 0x07c MUX_M1 /* UART4_RXD */ +- 0x080 MUX_M1 /* UART4_TXD */ +- >; +- }; +- +- uart6_pmx_func: uart6_pmx_func { +- pinctrl-single,pins = < +- 0x05c MUX_M1 /* UART6_RXD */ +- 0x060 MUX_M1 /* UART6_TXD */ +- >; +- }; +- +- i2c3_pmx_func: i2c3_pmx_func { +- pinctrl-single,pins = < +- 0x010 MUX_M1 /* I2C3_SCL */ +- 0x014 MUX_M1 /* I2C3_SDA */ +- >; +- }; +- +- i2c4_pmx_func: i2c4_pmx_func { +- pinctrl-single,pins = < +- 0x03c MUX_M1 /* I2C4_SCL */ +- 0x040 MUX_M1 /* I2C4_SDA */ +- >; +- }; +- +- cam0_rst_pmx_func: cam0_rst_pmx_func { +- pinctrl-single,pins = < +- 0x714 MUX_M0 /* CAM0_RST */ +- >; +- }; +- +- cam1_rst_pmx_func: cam1_rst_pmx_func { +- pinctrl-single,pins = < +- 0x048 MUX_M0 /* CAM1_RST */ +- >; +- }; +- +- cam0_pwd_n_pmx_func: cam0_pwd_n_pmx_func { +- pinctrl-single,pins = < +- 0x098 MUX_M0 /* CAM0_PWD_N */ +- >; +- }; +- +- cam1_pwd_n_pmx_func: cam1_pwd_n_pmx_func { +- pinctrl-single,pins = < +- 0x044 MUX_M0 /* CAM1_PWD_N */ +- >; +- }; +- +- isp0_pmx_func: isp0_pmx_func { +- pinctrl-single,pins = < +- 0x018 MUX_M1 /* ISP_CLK0 */ +- 0x024 MUX_M1 /* ISP_SCL0 */ +- 0x028 MUX_M1 /* ISP_SDA0 */ +- >; +- }; +- +- isp1_pmx_func: isp1_pmx_func { +- pinctrl-single,pins = < +- 0x01c MUX_M1 /* ISP_CLK1 */ +- 0x02c MUX_M1 /* ISP_SCL1 */ +- 0x030 MUX_M1 /* ISP_SDA1 */ +- >; +- }; +- }; +- +- pmx1: pinmux@fff11000 { +- compatible = "pinctrl-single"; +- reg = <0x0 0xfff11000 0x0 0x73c>; +- #gpio-range-cells = <0x3>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <0x20>; +- pinctrl-single,function-mask = <0x7>; +- /* pin base, nr pins & gpio function */ +- pinctrl-single,gpio-range = <&range 0 46 0>; +- +- pwr_key_pmx_func: pwr_key_pmx_func { +- pinctrl-single,pins = < +- 0x064 MUX_M0 /* GPIO_203 */ +- >; +- }; +- +- pd_pmx_func: pd_pmx_func{ +- pinctrl-single,pins = < +- 0x080 MUX_M0 /* GPIO_221 */ +- >; +- }; +- +- i2s2_pmx_func: i2s2_pmx_func { +- pinctrl-single,pins = < +- 0x050 MUX_M1 /* I2S2_DI */ +- 0x054 MUX_M1 /* I2S2_DO */ +- 0x058 MUX_M1 /* I2S2_XCLK */ +- 0x05c MUX_M1 /* I2S2_XFS */ +- >; +- }; +- +- spi0_pmx_func: spi0_pmx_func { +- pinctrl-single,pins = < +- 0x094 MUX_M1 /* SPI0_CLK */ +- 0x098 MUX_M1 /* SPI0_DI */ +- 0x09c MUX_M1 /* SPI0_DO */ +- 0x0a0 MUX_M1 /* SPI0_CS0_N */ +- >; +- }; +- +- spi2_pmx_func: spi2_pmx_func { +- pinctrl-single,pins = < +- 0x710 MUX_M1 /* SPI2_CLK */ +- 0x714 MUX_M1 /* SPI2_DI */ +- 0x718 MUX_M1 /* SPI2_DO */ +- 0x71c MUX_M1 /* SPI2_CS0_N */ +- >; +- }; +- +- spi3_pmx_func: spi3_pmx_func { +- pinctrl-single,pins = < +- 0x72c MUX_M1 /* SPI3_CLK */ +- 0x730 MUX_M1 /* SPI3_DI */ +- 0x734 MUX_M1 /* SPI3_DO */ +- 0x738 MUX_M1 /* SPI3_CS0_N */ +- >; +- }; +- +- i2c0_pmx_func: i2c0_pmx_func { +- pinctrl-single,pins = < +- 0x020 MUX_M1 /* I2C0_SCL */ +- 0x024 MUX_M1 /* I2C0_SDA */ +- >; +- }; +- +- i2c1_pmx_func: i2c1_pmx_func { +- pinctrl-single,pins = < +- 0x028 MUX_M1 /* I2C1_SCL */ +- 0x02c MUX_M1 /* I2C1_SDA */ +- >; +- }; +- i2c2_pmx_func: i2c2_pmx_func { +- pinctrl-single,pins = < +- 0x030 MUX_M1 /* I2C2_SCL */ +- 0x034 MUX_M1 /* I2C2_SDA */ +- >; +- }; +- +- pcie_clkreq_pmx_func: pcie_clkreq_pmx_func { +- pinctrl-single,pins = < +- 0x084 MUX_M1 /* PCIE0_CLKREQ_N */ +- >; +- }; +- +- gpio185_pmx_func: gpio185_pmx_func { +- pinctrl-single,pins = <0x01C 0x1>; +- }; +- +- gpio185_pmx_idle: gpio185_pmx_idle { +- pinctrl-single,pins = <0x01C 0x0>; +- }; +- }; +- +- pmx2: pinmux@e896c800 { +- compatible = "pinconf-single"; +- reg = <0x0 0xe896c800 0x0 0x72c>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <0x20>; +- +- uart0_cfg_func: uart0_cfg_func { +- pinctrl-single,pins = < +- 0x058 0x0 /* UART0_RXD */ +- 0x05c 0x0 /* UART0_TXD */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- +- uart2_cfg_func: uart2_cfg_func { +- pinctrl-single,pins = < +- 0x700 0x0 /* UART2_CTS_N */ +- 0x704 0x0 /* UART2_RTS_N */ +- 0x708 0x0 /* UART2_RXD */ +- 0x70c 0x0 /* UART2_TXD */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- +- uart3_cfg_func: uart3_cfg_func { +- pinctrl-single,pins = < +- 0x068 0x0 /* UART3_CTS_N */ +- 0x06c 0x0 /* UART3_RTS_N */ +- 0x070 0x0 /* UART3_RXD */ +- 0x074 0x0 /* UART3_TXD */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- +- uart4_cfg_func: uart4_cfg_func { +- pinctrl-single,pins = < +- 0x078 0x0 /* UART4_CTS_N */ +- 0x07c 0x0 /* UART4_RTS_N */ +- 0x080 0x0 /* UART4_RXD */ +- 0x084 0x0 /* UART4_TXD */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- +- uart6_cfg_func: uart6_cfg_func { +- pinctrl-single,pins = < +- 0x060 0x0 /* UART6_RXD */ +- 0x064 0x0 /* UART6_TXD */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- i2c3_cfg_func: i2c3_cfg_func { +- pinctrl-single,pins = < +- 0x014 0x0 /* I2C3_SCL */ +- 0x018 0x0 /* I2C3_SDA */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- +- i2c4_cfg_func: i2c4_cfg_func { +- pinctrl-single,pins = < +- 0x040 0x0 /* I2C4_SCL */ +- 0x044 0x0 /* I2C4_SDA */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- +- cam0_rst_cfg_func: cam0_rst_cfg_func { +- pinctrl-single,pins = < +- 0x714 0x0 /* CAM0_RST */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- +- cam1_rst_cfg_func: cam1_rst_cfg_func { +- pinctrl-single,pins = < +- 0x04C 0x0 /* CAM1_RST */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- +- cam0_pwd_n_cfg_func: cam0_pwd_n_cfg_func { +- pinctrl-single,pins = < +- 0x09C 0x0 /* CAM0_PWD_N */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- +- cam1_pwd_n_cfg_func: cam1_pwd_n_cfg_func { +- pinctrl-single,pins = < +- 0x048 0x0 /* CAM1_PWD_N */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- +- isp0_cfg_func: isp0_cfg_func { +- pinctrl-single,pins = < +- 0x01C 0x0 /* ISP_CLK0 */ +- 0x028 0x0 /* ISP_SCL0 */ +- 0x02C 0x0 /* ISP_SDA0 */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- +- isp1_cfg_func: isp1_cfg_func { +- pinctrl-single,pins = < +- 0x020 0x0 /* ISP_CLK1 */ +- 0x030 0x0 /* ISP_SCL1 */ +- 0x034 0x0 /* ISP_SDA1 */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- }; +- +- pmx5: pinmux@fc182000 { +- compatible = "pinctrl-single"; +- reg = <0x0 0xfc182000 0x0 0x028>; +- #gpio-range-cells = <3>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <0x20>; +- pinctrl-single,function-mask = <0x7>; +- /* pin base, nr pins & gpio function */ +- pinctrl-single,gpio-range = <&range 0 10 0>; +- +- sdio_pmx_func: sdio_pmx_func { +- pinctrl-single,pins = < +- 0x000 MUX_M1 /* SDIO_CLK */ +- 0x004 MUX_M1 /* SDIO_CMD */ +- 0x008 MUX_M1 /* SDIO_DATA0 */ +- 0x00c MUX_M1 /* SDIO_DATA1 */ +- 0x010 MUX_M1 /* SDIO_DATA2 */ +- 0x014 MUX_M1 /* SDIO_DATA3 */ +- >; +- }; +- }; +- +- pmx6: pinmux@fc182800 { +- compatible = "pinconf-single"; +- reg = <0x0 0xfc182800 0x0 0x028>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <0x20>; +- +- sdio_clk_cfg_func: sdio_clk_cfg_func { +- pinctrl-single,pins = < +- 0x000 0x0 /* SDIO_CLK */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE6_32MA DRIVE6_MASK +- >; +- }; +- +- sdio_cfg_func: sdio_cfg_func { +- pinctrl-single,pins = < +- 0x004 0x0 /* SDIO_CMD */ +- 0x008 0x0 /* SDIO_DATA0 */ +- 0x00c 0x0 /* SDIO_DATA1 */ +- 0x010 0x0 /* SDIO_DATA2 */ +- 0x014 0x0 /* SDIO_DATA3 */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_UP +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE6_19MA DRIVE6_MASK +- >; +- }; +- }; +- +- pmx7: pinmux@ff37e000 { +- compatible = "pinctrl-single"; +- reg = <0x0 0xff37e000 0x0 0x030>; +- #gpio-range-cells = <3>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <0x20>; +- pinctrl-single,function-mask = <7>; +- /* pin base, nr pins & gpio function */ +- pinctrl-single,gpio-range = <&range 0 12 0>; +- +- sd_pmx_func: sd_pmx_func { +- pinctrl-single,pins = < +- 0x000 MUX_M1 /* SD_CLK */ +- 0x004 MUX_M1 /* SD_CMD */ +- 0x008 MUX_M1 /* SD_DATA0 */ +- 0x00c MUX_M1 /* SD_DATA1 */ +- 0x010 MUX_M1 /* SD_DATA2 */ +- 0x014 MUX_M1 /* SD_DATA3 */ +- >; +- }; +- }; +- +- pmx8: pinmux@ff37e800 { +- compatible = "pinconf-single"; +- reg = <0x0 0xff37e800 0x0 0x030>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <0x20>; +- +- sd_clk_cfg_func: sd_clk_cfg_func { +- pinctrl-single,pins = < +- 0x000 0x0 /* SD_CLK */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE6_32MA +- DRIVE6_MASK +- >; +- }; +- +- sd_cfg_func: sd_cfg_func { +- pinctrl-single,pins = < +- 0x004 0x0 /* SD_CMD */ +- 0x008 0x0 /* SD_DATA0 */ +- 0x00c 0x0 /* SD_DATA1 */ +- 0x010 0x0 /* SD_DATA2 */ +- 0x014 0x0 /* SD_DATA3 */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_UP +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE6_19MA +- DRIVE6_MASK +- >; +- }; +- }; +- +- pmx16: pinmux@fff11800 { +- compatible = "pinconf-single"; +- reg = <0x0 0xfff11800 0x0 0x73c>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <0x20>; +- +- pwr_key_cfg_func: pwr_key_cfg_func { +- pinctrl-single,pins = < +- 0x090 0x0 /* GPIO_203 */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_UP +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- usb_cfg_func: usb_cfg_func { +- pinctrl-single,pins = < +- 0x0AC 0x0 /* GPIO_221 */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_UP +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- spi0_cfg_func: spi0_cfg_func { +- pinctrl-single,pins = < +- 0x0c8 0x0 /* SPI0_DI */ +- 0x0cc 0x0 /* SPI0_DO */ +- 0x0d0 0x0 /* SPI0_CS0_N */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_06MA DRIVE6_MASK +- >; +- }; +- +- spi2_cfg_func: spi2_cfg_func { +- pinctrl-single,pins = < +- 0x714 0x0 /* SPI2_DI */ +- 0x718 0x0 /* SPI2_DO */ +- 0x71c 0x0 /* SPI2_CS0_N */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_06MA DRIVE6_MASK +- >; +- }; +- +- spi3_cfg_func: spi3_cfg_func { +- pinctrl-single,pins = < +- 0x730 0x0 /* SPI3_DI */ +- 0x734 0x0 /* SPI3_DO */ +- 0x738 0x0 /* SPI3_CS0_N */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_06MA DRIVE6_MASK +- >; +- }; +- +- spi0_clk_cfg_func: spi0_clk_cfg_func { +- pinctrl-single,pins = < +- 0x0c4 0x0 /* SPI0_CLK */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_10MA DRIVE6_MASK +- >; +- }; +- +- spi2_clk_cfg_func: spi2_clk_cfg_func { +- pinctrl-single,pins = < +- 0x710 0x0 /* SPI2_CLK */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_10MA DRIVE6_MASK +- >; +- }; +- +- spi3_clk_cfg_func: spi3_clk_cfg_func { +- pinctrl-single,pins = < +- 0x72c 0x0 /* SPI3_CLK */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_10MA DRIVE6_MASK +- >; +- }; +- +- i2c0_cfg_func: i2c0_cfg_func { +- pinctrl-single,pins = < +- 0x04c 0x0 /* I2C0_SCL */ +- 0x050 0x0 /* I2C0_SDA */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- +- i2c1_cfg_func: i2c1_cfg_func { +- pinctrl-single,pins = < +- 0x054 0x0 /* I2C1_SCL */ +- 0x058 0x0 /* I2C1_SDA */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- +- i2c2_cfg_func: i2c2_cfg_func { +- pinctrl-single,pins = < +- 0x05c 0x0 /* I2C2_SCL */ +- 0x060 0x0 /* I2C2_SDA */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_04MA DRIVE6_MASK +- >; +- }; +- +- pcie_clkreq_cfg_func: pcie_clkreq_cfg_func { +- pinctrl-single,pins = < +- 0x0b0 0x0 +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_DIS +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_06MA DRIVE6_MASK +- >; +- }; +- i2s2_cfg_func: i2s2_cfg_func { +- pinctrl-single,pins = < +- 0x07c 0x0 /* I2S2_DI */ +- 0x080 0x0 /* I2S2_DO */ +- 0x084 0x0 /* I2S2_XCLK */ +- 0x088 0x0 /* I2S2_XFS */ +- >; +- pinctrl-single,bias-pulldown = < +- PULL_DIS +- PULL_DOWN +- PULL_DIS +- PULL_DOWN +- >; +- pinctrl-single,bias-pullup = < +- PULL_UP +- PULL_UP +- PULL_DIS +- PULL_UP +- >; +- pinctrl-single,drive-strength = < +- DRIVE7_02MA DRIVE6_MASK +- >; +- }; +- +- gpio185_cfg_func: gpio185_cfg_func { +- pinctrl-single,pins = <0x048 0>; +- pinctrl-single,bias-pulldown = <0 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- pinctrl-single,drive-strength = <0x00 0x70>; +- pinctrl-single,slew-rate = <0x0 0x80>; +- }; +- +- gpio185_cfg_idle: gpio185_cfg_idle { +- pinctrl-single,pins = <0x048 0>; +- pinctrl-single,bias-pulldown = <2 2 0 2>; +- pinctrl-single,bias-pullup = <0 1 0 1>; +- pinctrl-single,drive-strength = <0x00 0x70>; +- pinctrl-single,slew-rate = <0x0 0x80>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/hip05-d02.dts b/scripts/dtc/include-prefixes/arm64/hisilicon/hip05-d02.dts +deleted file mode 100644 +index 40f3e00ac832..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/hip05-d02.dts ++++ /dev/null +@@ -1,84 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/** +- * dts file for Hisilicon D02 Development Board +- * +- * Copyright (C) 2014,2015 HiSilicon Ltd. +- */ +- +-/dts-v1/; +- +-#include +-#include "hip05.dtsi" +- +-/ { +- model = "Hisilicon Hip05 D02 Development Board"; +- compatible = "hisilicon,hip05-d02"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x00000000 0x0 0x80000000>; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pwrbutton { +- label = "Power Button"; +- gpios = <&porta 8 GPIO_ACTIVE_LOW>; +- linux,code = <116>; +- debounce-interval = <0>; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&peri_gpio0 { +- status = "okay"; +-}; +- +-&lbc { +- status = "okay"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0 0x0 0x90000000 0x08000000>, +- <1 0 0x0 0x98000000 0x08000000>; +- +- nor-flash@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "numonyx,js28f00a", "cfi-flash"; +- reg = <0 0x0 0x08000000>; +- bank-width = <2>; +- /* The three parts may not used */ +- partition@0 { +- label = "BIOS"; +- reg = <0x0 0x300000>; +- }; +- partition@300000 { +- label = "Linux"; +- reg = <0x300000 0xa00000>; +- }; +- partition@1000000 { +- label = "Rootfs"; +- reg = <0x01000000 0x02000000>; +- }; +- }; +- +- cpld@1,0 { +- compatible = "hisilicon,hip05-cpld"; +- reg = <1 0x0 0x100>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/hip05.dtsi b/scripts/dtc/include-prefixes/arm64/hisilicon/hip05.dtsi +deleted file mode 100644 +index 7b2abd10d3d6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/hip05.dtsi ++++ /dev/null +@@ -1,365 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/** +- * dts file for Hisilicon D02 Development Board +- * +- * Copyright (C) 2014,2015 HiSilicon Ltd. +- */ +- +-#include +- +-/ { +- compatible = "hisilicon,hip05-d02"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- core2 { +- cpu = <&cpu2>; +- }; +- core3 { +- cpu = <&cpu3>; +- }; +- }; +- cluster1 { +- core0 { +- cpu = <&cpu4>; +- }; +- core1 { +- cpu = <&cpu5>; +- }; +- core2 { +- cpu = <&cpu6>; +- }; +- core3 { +- cpu = <&cpu7>; +- }; +- }; +- cluster2 { +- core0 { +- cpu = <&cpu8>; +- }; +- core1 { +- cpu = <&cpu9>; +- }; +- core2 { +- cpu = <&cpu10>; +- }; +- core3 { +- cpu = <&cpu11>; +- }; +- }; +- cluster3 { +- core0 { +- cpu = <&cpu12>; +- }; +- core1 { +- cpu = <&cpu13>; +- }; +- core2 { +- cpu = <&cpu14>; +- }; +- core3 { +- cpu = <&cpu15>; +- }; +- }; +- }; +- +- cpu0: cpu@20000 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x20000>; +- enable-method = "psci"; +- next-level-cache = <&cluster0_l2>; +- }; +- +- cpu1: cpu@20001 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x20001>; +- enable-method = "psci"; +- next-level-cache = <&cluster0_l2>; +- }; +- +- cpu2: cpu@20002 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x20002>; +- enable-method = "psci"; +- next-level-cache = <&cluster0_l2>; +- }; +- +- cpu3: cpu@20003 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x20003>; +- enable-method = "psci"; +- next-level-cache = <&cluster0_l2>; +- }; +- +- cpu4: cpu@20100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x20100>; +- enable-method = "psci"; +- next-level-cache = <&cluster1_l2>; +- }; +- +- cpu5: cpu@20101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x20101>; +- enable-method = "psci"; +- next-level-cache = <&cluster1_l2>; +- }; +- +- cpu6: cpu@20102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x20102>; +- enable-method = "psci"; +- next-level-cache = <&cluster1_l2>; +- }; +- +- cpu7: cpu@20103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x20103>; +- enable-method = "psci"; +- next-level-cache = <&cluster1_l2>; +- }; +- +- cpu8: cpu@20200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x20200>; +- enable-method = "psci"; +- next-level-cache = <&cluster2_l2>; +- }; +- +- cpu9: cpu@20201 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x20201>; +- enable-method = "psci"; +- next-level-cache = <&cluster2_l2>; +- }; +- +- cpu10: cpu@20202 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x20202>; +- enable-method = "psci"; +- next-level-cache = <&cluster2_l2>; +- }; +- +- cpu11: cpu@20203 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x20203>; +- enable-method = "psci"; +- next-level-cache = <&cluster2_l2>; +- }; +- +- cpu12: cpu@20300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x20300>; +- enable-method = "psci"; +- next-level-cache = <&cluster3_l2>; +- }; +- +- cpu13: cpu@20301 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x20301>; +- enable-method = "psci"; +- next-level-cache = <&cluster3_l2>; +- }; +- +- cpu14: cpu@20302 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x20302>; +- enable-method = "psci"; +- next-level-cache = <&cluster3_l2>; +- }; +- +- cpu15: cpu@20303 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x20303>; +- enable-method = "psci"; +- next-level-cache = <&cluster3_l2>; +- }; +- +- cluster0_l2: l2-cache0 { +- compatible = "cache"; +- }; +- +- cluster1_l2: l2-cache1 { +- compatible = "cache"; +- }; +- +- cluster2_l2: l2-cache2 { +- compatible = "cache"; +- }; +- +- cluster3_l2: l2-cache3 { +- compatible = "cache"; +- }; +- }; +- +- gic: interrupt-controller@8d000000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- interrupt-controller; +- #redistributor-regions = <1>; +- redistributor-stride = <0x0 0x30000>; +- reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ +- <0x0 0x8d100000 0 0x300000>, /* GICR */ +- <0x0 0xfe000000 0 0x10000>, /* GICC */ +- <0x0 0xfe010000 0 0x10000>, /* GICH */ +- <0x0 0xfe020000 0 0x10000>; /* GICV */ +- interrupts = ; +- +- its_peri: msi-controller@8c000000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0x0 0x8c000000 0x0 0x40000>; +- }; +- +- its_m3: msi-controller@a3000000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0x0 0xa3000000 0x0 0x40000>; +- }; +- +- its_pcie: msi-controller@b7000000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0x0 0xb7000000 0x0 0x40000>; +- }; +- +- its_dsa: msi-controller@c6000000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0x0 0xc6000000 0x0 0x40000>; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,cortex-a57-pmu"; +- interrupts = ; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- refclk200mhz: refclk200mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <200000000>; +- }; +- +- uart0: serial@80300000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x0 0x80300000 0x0 0x10000>; +- interrupts = ; +- clocks = <&refclk200mhz>, <&refclk200mhz>; +- clock-names = "baudclk", "apb_pclk"; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart1: serial@80310000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x0 0x80310000 0x0 0x10000>; +- interrupts = ; +- clocks = <&refclk200mhz>, <&refclk200mhz>; +- clock-names = "baudclk", "apb_pclk"; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- lbc: local-bus@80380000 { +- compatible = "hisilicon,hisi-localbus", "simple-bus"; +- reg = <0x0 0x80380000 0x0 0x10000>; +- status = "disabled"; +- }; +- +- peri_gpio0: gpio@802e0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dw-apb-gpio"; +- reg = <0x0 0x802e0000 0x0 0x10000>; +- status = "disabled"; +- +- porta: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- }; +- +- peri_gpio1: gpio@802f0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dw-apb-gpio"; +- reg = <0x0 0x802f0000 0x0 0x10000>; +- status = "disabled"; +- +- portb: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/hip06-d03.dts b/scripts/dtc/include-prefixes/arm64/hisilicon/hip06-d03.dts +deleted file mode 100644 +index 35af5d3821e8..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/hip06-d03.dts ++++ /dev/null +@@ -1,58 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/** +- * dts file for Hisilicon D03 Development Board +- * +- * Copyright (C) 2016 HiSilicon Ltd. +- */ +- +-/dts-v1/; +- +-#include "hip06.dtsi" +- +-/ { +- model = "Hisilicon Hip06 D03 Development Board"; +- compatible = "hisilicon,hip06-d03"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x00000000 0x0 0x40000000>; +- }; +- +- chosen { }; +-}; +- +-&ipmi0 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-ð0 { +- status = "okay"; +-}; +- +-ð1 { +- status = "okay"; +-}; +- +-ð2 { +- status = "okay"; +-}; +- +-ð3 { +- status = "okay"; +-}; +- +-&sas1 { +- status = "okay"; +-}; +- +-&usb_ohci { +- status = "okay"; +-}; +- +-&usb_ehci { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/hip06.dtsi b/scripts/dtc/include-prefixes/arm64/hisilicon/hip06.dtsi +deleted file mode 100644 +index 70d7732dd348..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/hip06.dtsi ++++ /dev/null +@@ -1,752 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/** +- * dts file for Hisilicon D03 Development Board +- * +- * Copyright (C) 2016 HiSilicon Ltd. +- */ +- +-#include +- +-/ { +- compatible = "hisilicon,hip06-d03"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- core2 { +- cpu = <&cpu2>; +- }; +- core3 { +- cpu = <&cpu3>; +- }; +- }; +- cluster1 { +- core0 { +- cpu = <&cpu4>; +- }; +- core1 { +- cpu = <&cpu5>; +- }; +- core2 { +- cpu = <&cpu6>; +- }; +- core3 { +- cpu = <&cpu7>; +- }; +- }; +- cluster2 { +- core0 { +- cpu = <&cpu8>; +- }; +- core1 { +- cpu = <&cpu9>; +- }; +- core2 { +- cpu = <&cpu10>; +- }; +- core3 { +- cpu = <&cpu11>; +- }; +- }; +- cluster3 { +- core0 { +- cpu = <&cpu12>; +- }; +- core1 { +- cpu = <&cpu13>; +- }; +- core2 { +- cpu = <&cpu14>; +- }; +- core3 { +- cpu = <&cpu15>; +- }; +- }; +- }; +- +- cpu0: cpu@10000 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x10000>; +- enable-method = "psci"; +- next-level-cache = <&cluster0_l2>; +- }; +- +- cpu1: cpu@10001 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x10001>; +- enable-method = "psci"; +- next-level-cache = <&cluster0_l2>; +- }; +- +- cpu2: cpu@10002 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x10002>; +- enable-method = "psci"; +- next-level-cache = <&cluster0_l2>; +- }; +- +- cpu3: cpu@10003 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x10003>; +- enable-method = "psci"; +- next-level-cache = <&cluster0_l2>; +- }; +- +- cpu4: cpu@10100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x10100>; +- enable-method = "psci"; +- next-level-cache = <&cluster1_l2>; +- }; +- +- cpu5: cpu@10101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x10101>; +- enable-method = "psci"; +- next-level-cache = <&cluster1_l2>; +- }; +- +- cpu6: cpu@10102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x10102>; +- enable-method = "psci"; +- next-level-cache = <&cluster1_l2>; +- }; +- +- cpu7: cpu@10103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x10103>; +- enable-method = "psci"; +- next-level-cache = <&cluster1_l2>; +- }; +- +- cpu8: cpu@10200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x10200>; +- enable-method = "psci"; +- next-level-cache = <&cluster2_l2>; +- }; +- +- cpu9: cpu@10201 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x10201>; +- enable-method = "psci"; +- next-level-cache = <&cluster2_l2>; +- }; +- +- cpu10: cpu@10202 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x10202>; +- enable-method = "psci"; +- next-level-cache = <&cluster2_l2>; +- }; +- +- cpu11: cpu@10203 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x10203>; +- enable-method = "psci"; +- next-level-cache = <&cluster2_l2>; +- }; +- +- cpu12: cpu@10300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x10300>; +- enable-method = "psci"; +- next-level-cache = <&cluster3_l2>; +- }; +- +- cpu13: cpu@10301 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x10301>; +- enable-method = "psci"; +- next-level-cache = <&cluster3_l2>; +- }; +- +- cpu14: cpu@10302 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x10302>; +- enable-method = "psci"; +- next-level-cache = <&cluster3_l2>; +- }; +- +- cpu15: cpu@10303 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x10303>; +- enable-method = "psci"; +- next-level-cache = <&cluster3_l2>; +- }; +- +- cluster0_l2: l2-cache0 { +- compatible = "cache"; +- }; +- +- cluster1_l2: l2-cache1 { +- compatible = "cache"; +- }; +- +- cluster2_l2: l2-cache2 { +- compatible = "cache"; +- }; +- +- cluster3_l2: l2-cache3 { +- compatible = "cache"; +- }; +- }; +- +- gic: interrupt-controller@4d000000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- interrupt-controller; +- #redistributor-regions = <1>; +- redistributor-stride = <0x0 0x30000>; +- reg = <0x0 0x4d000000 0 0x10000>, /* GICD */ +- <0x0 0x4d100000 0 0x300000>, /* GICR */ +- <0x0 0xfe000000 0 0x10000>, /* GICC */ +- <0x0 0xfe010000 0 0x10000>, /* GICH */ +- <0x0 0xfe020000 0 0x10000>; /* GICV */ +- interrupts = ; +- +- its_dsa: msi-controller@c6000000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0x0 0xc6000000 0x0 0x40000>; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,cortex-a57-pmu"; +- interrupts = ; +- }; +- +- mbigen_pcie@a0080000 { +- compatible = "hisilicon,mbigen-v2"; +- reg = <0x0 0xa0080000 0x0 0x10000>; +- +- mbigen_usb: intc_usb { +- msi-parent = <&its_dsa 0x40080>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <2>; +- }; +- +- mbigen_sas1: intc_sas1 { +- msi-parent = <&its_dsa 0x40000>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <128>; +- }; +- +- mbigen_sas2: intc_sas2 { +- msi-parent = <&its_dsa 0x40040>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <128>; +- }; +- +- mbigen_pcie0: intc_pcie0 { +- msi-parent = <&its_dsa 0x40085>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <10>; +- }; +- }; +- +- mbigen_dsa@c0080000 { +- compatible = "hisilicon,mbigen-v2"; +- reg = <0x0 0xc0080000 0x0 0x10000>; +- +- mbigen_dsaf0: intc_dsaf0 { +- msi-parent = <&its_dsa 0x40800>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <409>; +- }; +- +- mbigen_sas0: intc-sas0 { +- msi-parent = <&its_dsa 0x40900>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <128>; +- }; +- }; +- +- /** +- * HiSilicon erratum 161010801: This describes the limitation +- * of HiSilicon platforms hip06/hip07 to support the SMMUv3 +- * mappings for PCIe MSI transactions. +- * PCIe controller on these platforms has to differentiate the +- * MSI payload against other DMA payload and has to modify the +- * MSI payload. This makes it difficult for these platforms to +- * have a SMMU translation for MSI. In order to workaround this, +- * ARM SMMUv3 driver requires a quirk to treat the MSI regions +- * separately. Such a quirk is currently missing for DT based +- * systems. Hence please make sure that the smmu pcie node on +- * hip06 is disabled as this will break the PCIe functionality +- * when iommu-map entry is used along with the PCIe node. +- * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html +- */ +- smmu0: iommu@a0040000 { +- compatible = "arm,smmu-v3"; +- reg = <0x0 0xa0040000 0x0 0x20000>; +- #iommu-cells = <1>; +- dma-coherent; +- hisilicon,broken-prefetch-cmd; +- status = "disabled"; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- isa@a01b0000 { +- compatible = "hisilicon,hip06-lpc"; +- #size-cells = <1>; +- #address-cells = <2>; +- reg = <0x0 0xa01b0000 0x0 0x1000>; +- +- ipmi0: bt@e4 { +- compatible = "ipmi-bt"; +- device_type = "ipmi"; +- reg = <0x01 0xe4 0x04>; +- status = "disabled"; +- }; +- +- uart0: serial@2f8 { +- compatible = "ns16550a"; +- clock-frequency = <1843200>; +- reg = <0x01 0x2f8 0x08>; +- status = "disabled"; +- }; +- }; +- +- refclk: refclk { +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- #clock-cells = <0>; +- }; +- +- usb_ohci: usb@a7030000 { +- compatible = "generic-ohci"; +- reg = <0x0 0xa7030000 0x0 0x10000>; +- interrupt-parent = <&mbigen_usb>; +- interrupts = <640 4>; +- dma-coherent; +- status = "disabled"; +- }; +- +- usb_ehci: usb@a7020000 { +- compatible = "generic-ehci"; +- reg = <0x0 0xa7020000 0x0 0x10000>; +- interrupt-parent = <&mbigen_usb>; +- interrupts = <641 4>; +- dma-coherent; +- status = "disabled"; +- }; +- +- peri_c_subctrl: sub_ctrl_c@60000000 { +- compatible = "hisilicon,peri-subctrl","syscon"; +- reg = <0 0x60000000 0x0 0x10000>; +- }; +- +- dsa_subctrl: dsa_subctrl@c0000000 { +- compatible = "hisilicon,dsa-subctrl", "syscon"; +- reg = <0x0 0xc0000000 0x0 0x10000>; +- }; +- +- pcie_subctl: pcie_subctl@a0000000 { +- compatible = "hisilicon,pcie-sas-subctrl", "syscon"; +- reg = <0x0 0xa0000000 0x0 0x10000>; +- }; +- +- serdes_ctrl: sds_ctrl@c2200000 { +- compatible = "syscon"; +- reg = <0 0xc2200000 0x0 0x80000>; +- }; +- +- mdio@603c0000 { +- compatible = "hisilicon,hns-mdio"; +- reg = <0x0 0x603c0000 0x0 0x1000>; +- subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +- +- phy1: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +- }; +- +- dsaf0: dsa@c7000000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "hisilicon,hns-dsaf-v2"; +- mode = "6port-16rss"; +- reg = <0x0 0xc5000000 0x0 0x890000>, +- <0x0 0xc7000000 0x0 0x600000>; +- reg-names = "ppe-base", "dsaf-base"; +- interrupt-parent = <&mbigen_dsaf0>; +- subctrl-syscon = <&dsa_subctrl>; +- reset-field-offset = <0>; +- interrupts = +- <576 1>, <577 1>, <578 1>, <579 1>, <580 1>, +- <581 1>, <582 1>, <583 1>, <584 1>, <585 1>, +- <586 1>, <587 1>, <588 1>, <589 1>, <590 1>, +- <591 1>, <592 1>, <593 1>, <594 1>, <595 1>, +- <596 1>, <597 1>, <598 1>, <599 1>, <600 1>, +- <960 1>, <961 1>, <962 1>, <963 1>, <964 1>, +- <965 1>, <966 1>, <967 1>, <968 1>, <969 1>, +- <970 1>, <971 1>, <972 1>, <973 1>, <974 1>, +- <975 1>, <976 1>, <977 1>, <978 1>, <979 1>, +- <980 1>, <981 1>, <982 1>, <983 1>, <984 1>, +- <985 1>, <986 1>, <987 1>, <988 1>, <989 1>, +- <990 1>, <991 1>, <992 1>, <993 1>, <994 1>, +- <995 1>, <996 1>, <997 1>, <998 1>, <999 1>, +- <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>, +- <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>, +- <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>, +- <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>, +- <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>, +- <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>, +- <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>, +- <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>, +- <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>, +- <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>, +- <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>, +- <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>, +- <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>, +- <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>, +- <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>, +- <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>, +- <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>, +- <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>, +- <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>, +- <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>, +- <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>, +- <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>, +- <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>, +- <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>, +- <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>, +- <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>, +- <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>, +- <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>, +- <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>, +- <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>, +- <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>, +- <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>, +- <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>, +- <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>, +- <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>, +- <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>, +- <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>, +- <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>, +- <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>, +- <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>, +- <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>, +- <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>, +- <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>, +- <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>, +- <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>, +- <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>, +- <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>, +- <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>, +- <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>, +- <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>, +- <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>, +- <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>, +- <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>, +- <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>, +- <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>, +- <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>, +- <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>, +- <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>, +- <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>, +- <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>, +- <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>, +- <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>, +- <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>, +- <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>, +- <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>, +- <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>, +- <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>, +- <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>, +- <1340 1>, <1341 1>, <1342 1>, <1343 1>; +- +- desc-num = <0x400>; +- buf-size = <0x1000>; +- dma-coherent; +- +- port@0 { +- reg = <0>; +- serdes-syscon = <&serdes_ctrl>; +- port-rst-offset = <0>; +- port-mode-offset = <0>; +- media-type = "fiber"; +- }; +- +- port@1 { +- reg = <1>; +- serdes-syscon= <&serdes_ctrl>; +- port-rst-offset = <1>; +- port-mode-offset = <1>; +- media-type = "fiber"; +- }; +- +- port@4 { +- reg = <4>; +- phy-handle = <&phy0>; +- serdes-syscon= <&serdes_ctrl>; +- port-rst-offset = <4>; +- port-mode-offset = <2>; +- media-type = "copper"; +- }; +- +- port@5 { +- reg = <5>; +- phy-handle = <&phy1>; +- serdes-syscon= <&serdes_ctrl>; +- port-rst-offset = <5>; +- port-mode-offset = <3>; +- media-type = "copper"; +- }; +- }; +- +- eth0: ethernet-4{ +- compatible = "hisilicon,hns-nic-v2"; +- ae-handle = <&dsaf0>; +- port-idx-in-ae = <4>; +- local-mac-address = [00 00 00 00 00 00]; +- status = "disabled"; +- dma-coherent; +- }; +- +- eth1: ethernet-5{ +- compatible = "hisilicon,hns-nic-v2"; +- ae-handle = <&dsaf0>; +- port-idx-in-ae = <5>; +- local-mac-address = [00 00 00 00 00 00]; +- status = "disabled"; +- dma-coherent; +- }; +- +- eth2: ethernet-0{ +- compatible = "hisilicon,hns-nic-v2"; +- ae-handle = <&dsaf0>; +- port-idx-in-ae = <0>; +- local-mac-address = [00 00 00 00 00 00]; +- status = "disabled"; +- dma-coherent; +- }; +- +- eth3: ethernet-1{ +- compatible = "hisilicon,hns-nic-v2"; +- ae-handle = <&dsaf0>; +- port-idx-in-ae = <1>; +- local-mac-address = [00 00 00 00 00 00]; +- status = "disabled"; +- dma-coherent; +- }; +- +- sas0: sas@c3000000 { +- compatible = "hisilicon,hip06-sas-v2"; +- reg = <0 0xc3000000 0 0x10000>; +- sas-addr = [50 01 88 20 16 00 00 00]; +- hisilicon,sas-syscon = <&dsa_subctrl>; +- ctrl-reset-reg = <0xa60>; +- ctrl-reset-sts-reg = <0x5a30>; +- ctrl-clock-ena-reg = <0x338>; +- clocks = <&refclk 0>; +- queue-count = <16>; +- phy-count = <8>; +- dma-coherent; +- interrupt-parent = <&mbigen_sas0>; +- interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, +- <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, +- <75 4>,<76 4>,<77 4>,<78 4>,<79 4>, +- <80 4>,<81 4>,<82 4>,<83 4>,<84 4>, +- <85 4>,<86 4>,<87 4>,<88 4>,<89 4>, +- <90 4>,<91 4>,<92 4>,<93 4>,<94 4>, +- <95 4>,<96 4>,<97 4>,<98 4>,<99 4>, +- <100 4>,<101 4>,<102 4>,<103 4>,<104 4>, +- <105 4>,<106 4>,<107 4>,<108 4>,<109 4>, +- <110 4>,<111 4>,<112 4>,<113 4>,<114 4>, +- <115 4>,<116 4>,<117 4>,<118 4>,<119 4>, +- <120 4>,<121 4>,<122 4>,<123 4>,<124 4>, +- <125 4>,<126 4>,<127 4>,<128 4>,<129 4>, +- <130 4>,<131 4>,<132 4>,<133 4>,<134 4>, +- <135 4>,<136 4>,<137 4>,<138 4>,<139 4>, +- <140 4>,<141 4>,<142 4>,<143 4>,<144 4>, +- <145 4>,<146 4>,<147 4>,<148 4>,<149 4>, +- <150 4>,<151 4>,<152 4>,<153 4>,<154 4>, +- <155 4>,<156 4>,<157 4>,<158 4>,<159 4>, +- <160 4>,<601 1>,<602 1>,<603 1>,<604 1>, +- <605 1>,<606 1>,<607 1>,<608 1>,<609 1>, +- <610 1>,<611 1>,<612 1>,<613 1>,<614 1>, +- <615 1>,<616 1>,<617 1>,<618 1>,<619 1>, +- <620 1>,<621 1>,<622 1>,<623 1>,<624 1>, +- <625 1>,<626 1>,<627 1>,<628 1>,<629 1>, +- <630 1>,<631 1>,<632 1>; +- status = "disabled"; +- }; +- +- sas1: sas@a2000000 { +- compatible = "hisilicon,hip06-sas-v2"; +- reg = <0 0xa2000000 0 0x10000>; +- sas-addr = [50 01 88 20 16 00 00 00]; +- hisilicon,sas-syscon = <&pcie_subctl>; +- hip06-sas-v2-quirk-amt; +- ctrl-reset-reg = <0xa18>; +- ctrl-reset-sts-reg = <0x5a0c>; +- ctrl-clock-ena-reg = <0x318>; +- clocks = <&refclk 0>; +- queue-count = <16>; +- phy-count = <8>; +- dma-coherent; +- interrupt-parent = <&mbigen_sas1>; +- interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, +- <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, +- <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, +- <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, +- <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, +- <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, +- <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, +- <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, +- <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, +- <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, +- <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, +- <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, +- <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, +- <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, +- <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, +- <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, +- <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, +- <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, +- <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, +- <159 4>,<576 1>,<577 1>,<578 1>,<579 1>, +- <580 1>,<581 1>,<582 1>,<583 1>,<584 1>, +- <585 1>,<586 1>,<587 1>,<588 1>,<589 1>, +- <590 1>,<591 1>,<592 1>,<593 1>,<594 1>, +- <595 1>,<596 1>,<597 1>,<598 1>,<599 1>, +- <600 1>,<601 1>,<602 1>,<603 1>,<604 1>, +- <605 1>,<606 1>,<607 1>; +- status = "disabled"; +- }; +- +- sas2: sas@a3000000 { +- compatible = "hisilicon,hip06-sas-v2"; +- reg = <0 0xa3000000 0 0x10000>; +- sas-addr = [50 01 88 20 16 00 00 00]; +- hisilicon,sas-syscon = <&pcie_subctl>; +- ctrl-reset-reg = <0xae0>; +- ctrl-reset-sts-reg = <0x5a70>; +- ctrl-clock-ena-reg = <0x3a8>; +- clocks = <&refclk 0>; +- queue-count = <16>; +- phy-count = <9>; +- dma-coherent; +- interrupt-parent = <&mbigen_sas2>; +- interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>, +- <197 4>,<198 4>,<199 4>,<200 4>,<201 4>, +- <202 4>,<203 4>,<204 4>,<205 4>,<206 4>, +- <207 4>,<208 4>,<209 4>,<210 4>,<211 4>, +- <212 4>,<213 4>,<214 4>,<215 4>,<216 4>, +- <217 4>,<218 4>,<219 4>,<220 4>,<221 4>, +- <222 4>,<223 4>,<224 4>,<225 4>,<226 4>, +- <227 4>,<228 4>,<229 4>,<230 4>,<231 4>, +- <232 4>,<233 4>,<234 4>,<235 4>,<236 4>, +- <237 4>,<238 4>,<239 4>,<240 4>,<241 4>, +- <242 4>,<243 4>,<244 4>,<245 4>,<246 4>, +- <247 4>,<248 4>,<249 4>,<250 4>,<251 4>, +- <252 4>,<253 4>,<254 4>,<255 4>,<256 4>, +- <257 4>,<258 4>,<259 4>,<260 4>,<261 4>, +- <262 4>,<263 4>,<264 4>,<265 4>,<266 4>, +- <267 4>,<268 4>,<269 4>,<270 4>,<271 4>, +- <272 4>,<273 4>,<274 4>,<275 4>,<276 4>, +- <277 4>,<278 4>,<279 4>,<280 4>,<281 4>, +- <282 4>,<283 4>,<284 4>,<285 4>,<286 4>, +- <287 4>,<608 1>,<609 1>,<610 1>,<611 1>, +- <612 1>,<613 1>,<614 1>,<615 1>,<616 1>, +- <617 1>,<618 1>,<619 1>,<620 1>,<621 1>, +- <622 1>,<623 1>,<624 1>,<625 1>,<626 1>, +- <627 1>,<628 1>,<629 1>,<630 1>,<631 1>, +- <632 1>,<633 1>,<634 1>,<635 1>,<636 1>, +- <637 1>,<638 1>,<639 1>; +- status = "disabled"; +- }; +- +- pcie0: pcie@a0090000 { +- compatible = "hisilicon,hip06-pcie-ecam"; +- reg = <0 0xb0000000 0 0x2000000>, +- <0 0xa0090000 0 0x10000>; +- bus-range = <0 31>; +- msi-map = <0x0000 &its_dsa 0x0000 0x2000>; +- msi-map-mask = <0xffff>; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000>, +- <0x01000000 0 0 0 0xb7ff0000 0 0x10000>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4 +- 0x0 0 0 2 &mbigen_pcie0 650 4 +- 0x0 0 0 3 &mbigen_pcie0 650 4 +- 0x0 0 0 4 &mbigen_pcie0 650 4>; +- status = "disabled"; +- }; +- +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/hip07-d05.dts b/scripts/dtc/include-prefixes/arm64/hisilicon/hip07-d05.dts +deleted file mode 100644 +index c3df67845f03..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/hip07-d05.dts ++++ /dev/null +@@ -1,90 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/** +- * dts file for Hisilicon D05 Development Board +- * +- * Copyright (C) 2016 HiSilicon Ltd. +- */ +- +-/dts-v1/; +- +-#include "hip07.dtsi" +- +-/ { +- model = "Hisilicon Hip07 D05 Development Board"; +- compatible = "hisilicon,hip07-d05"; +- +- /* the mem node will be updated by UEFI. */ +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x00000000 0x0 0x40000000>; +- numa-node-id = <0>; +- }; +- +- distance-map { +- compatible = "numa-distance-map-v1"; +- distance-matrix = <0 0 10>, +- <0 1 15>, +- <0 2 20>, +- <0 3 25>, +- <1 0 15>, +- <1 1 10>, +- <1 2 25>, +- <1 3 30>, +- <2 0 20>, +- <2 1 25>, +- <2 2 10>, +- <2 3 15>, +- <3 0 25>, +- <3 1 30>, +- <3 2 15>, +- <3 3 10>; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&ipmi0 { +- status = "okay"; +-}; +- +-&usb_ohci { +- status = "okay"; +-}; +- +-&usb_ehci { +- status = "okay"; +-}; +- +-ð0 { +- status = "okay"; +-}; +- +-ð1 { +- status = "okay"; +-}; +- +-ð2 { +- status = "okay"; +-}; +- +-ð3 { +- status = "okay"; +-}; +- +-&sas1 { +- status = "okay"; +-}; +- +-&p0_pcie2_a { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/hip07.dtsi b/scripts/dtc/include-prefixes/arm64/hisilicon/hip07.dtsi +deleted file mode 100644 +index 6baf6a686450..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/hip07.dtsi ++++ /dev/null +@@ -1,1882 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/** +- * dts file for Hisilicon D05 Development Board +- * +- * Copyright (C) 2016 HiSilicon Ltd. +- */ +- +-#include +- +-/ { +- compatible = "hisilicon,hip07-d05"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- core2 { +- cpu = <&cpu2>; +- }; +- core3 { +- cpu = <&cpu3>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&cpu4>; +- }; +- core1 { +- cpu = <&cpu5>; +- }; +- core2 { +- cpu = <&cpu6>; +- }; +- core3 { +- cpu = <&cpu7>; +- }; +- }; +- +- cluster2 { +- core0 { +- cpu = <&cpu8>; +- }; +- core1 { +- cpu = <&cpu9>; +- }; +- core2 { +- cpu = <&cpu10>; +- }; +- core3 { +- cpu = <&cpu11>; +- }; +- }; +- +- cluster3 { +- core0 { +- cpu = <&cpu12>; +- }; +- core1 { +- cpu = <&cpu13>; +- }; +- core2 { +- cpu = <&cpu14>; +- }; +- core3 { +- cpu = <&cpu15>; +- }; +- }; +- +- cluster4 { +- core0 { +- cpu = <&cpu16>; +- }; +- core1 { +- cpu = <&cpu17>; +- }; +- core2 { +- cpu = <&cpu18>; +- }; +- core3 { +- cpu = <&cpu19>; +- }; +- }; +- +- cluster5 { +- core0 { +- cpu = <&cpu20>; +- }; +- core1 { +- cpu = <&cpu21>; +- }; +- core2 { +- cpu = <&cpu22>; +- }; +- core3 { +- cpu = <&cpu23>; +- }; +- }; +- +- cluster6 { +- core0 { +- cpu = <&cpu24>; +- }; +- core1 { +- cpu = <&cpu25>; +- }; +- core2 { +- cpu = <&cpu26>; +- }; +- core3 { +- cpu = <&cpu27>; +- }; +- }; +- +- cluster7 { +- core0 { +- cpu = <&cpu28>; +- }; +- core1 { +- cpu = <&cpu29>; +- }; +- core2 { +- cpu = <&cpu30>; +- }; +- core3 { +- cpu = <&cpu31>; +- }; +- }; +- +- cluster8 { +- core0 { +- cpu = <&cpu32>; +- }; +- core1 { +- cpu = <&cpu33>; +- }; +- core2 { +- cpu = <&cpu34>; +- }; +- core3 { +- cpu = <&cpu35>; +- }; +- }; +- +- cluster9 { +- core0 { +- cpu = <&cpu36>; +- }; +- core1 { +- cpu = <&cpu37>; +- }; +- core2 { +- cpu = <&cpu38>; +- }; +- core3 { +- cpu = <&cpu39>; +- }; +- }; +- +- cluster10 { +- core0 { +- cpu = <&cpu40>; +- }; +- core1 { +- cpu = <&cpu41>; +- }; +- core2 { +- cpu = <&cpu42>; +- }; +- core3 { +- cpu = <&cpu43>; +- }; +- }; +- +- cluster11 { +- core0 { +- cpu = <&cpu44>; +- }; +- core1 { +- cpu = <&cpu45>; +- }; +- core2 { +- cpu = <&cpu46>; +- }; +- core3 { +- cpu = <&cpu47>; +- }; +- }; +- +- cluster12 { +- core0 { +- cpu = <&cpu48>; +- }; +- core1 { +- cpu = <&cpu49>; +- }; +- core2 { +- cpu = <&cpu50>; +- }; +- core3 { +- cpu = <&cpu51>; +- }; +- }; +- +- cluster13 { +- core0 { +- cpu = <&cpu52>; +- }; +- core1 { +- cpu = <&cpu53>; +- }; +- core2 { +- cpu = <&cpu54>; +- }; +- core3 { +- cpu = <&cpu55>; +- }; +- }; +- +- cluster14 { +- core0 { +- cpu = <&cpu56>; +- }; +- core1 { +- cpu = <&cpu57>; +- }; +- core2 { +- cpu = <&cpu58>; +- }; +- core3 { +- cpu = <&cpu59>; +- }; +- }; +- +- cluster15 { +- core0 { +- cpu = <&cpu60>; +- }; +- core1 { +- cpu = <&cpu61>; +- }; +- core2 { +- cpu = <&cpu62>; +- }; +- core3 { +- cpu = <&cpu63>; +- }; +- }; +- }; +- +- cpu0: cpu@10000 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x10000>; +- enable-method = "psci"; +- next-level-cache = <&cluster0_l2>; +- numa-node-id = <0>; +- }; +- +- cpu1: cpu@10001 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x10001>; +- enable-method = "psci"; +- next-level-cache = <&cluster0_l2>; +- numa-node-id = <0>; +- }; +- +- cpu2: cpu@10002 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x10002>; +- enable-method = "psci"; +- next-level-cache = <&cluster0_l2>; +- numa-node-id = <0>; +- }; +- +- cpu3: cpu@10003 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x10003>; +- enable-method = "psci"; +- next-level-cache = <&cluster0_l2>; +- numa-node-id = <0>; +- }; +- +- cpu4: cpu@10100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x10100>; +- enable-method = "psci"; +- next-level-cache = <&cluster1_l2>; +- numa-node-id = <0>; +- }; +- +- cpu5: cpu@10101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x10101>; +- enable-method = "psci"; +- next-level-cache = <&cluster1_l2>; +- numa-node-id = <0>; +- }; +- +- cpu6: cpu@10102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x10102>; +- enable-method = "psci"; +- next-level-cache = <&cluster1_l2>; +- numa-node-id = <0>; +- }; +- +- cpu7: cpu@10103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x10103>; +- enable-method = "psci"; +- next-level-cache = <&cluster1_l2>; +- numa-node-id = <0>; +- }; +- +- cpu8: cpu@10200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x10200>; +- enable-method = "psci"; +- next-level-cache = <&cluster2_l2>; +- numa-node-id = <0>; +- }; +- +- cpu9: cpu@10201 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x10201>; +- enable-method = "psci"; +- next-level-cache = <&cluster2_l2>; +- numa-node-id = <0>; +- }; +- +- cpu10: cpu@10202 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x10202>; +- enable-method = "psci"; +- next-level-cache = <&cluster2_l2>; +- numa-node-id = <0>; +- }; +- +- cpu11: cpu@10203 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x10203>; +- enable-method = "psci"; +- next-level-cache = <&cluster2_l2>; +- numa-node-id = <0>; +- }; +- +- cpu12: cpu@10300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x10300>; +- enable-method = "psci"; +- next-level-cache = <&cluster3_l2>; +- numa-node-id = <0>; +- }; +- +- cpu13: cpu@10301 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x10301>; +- enable-method = "psci"; +- next-level-cache = <&cluster3_l2>; +- numa-node-id = <0>; +- }; +- +- cpu14: cpu@10302 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x10302>; +- enable-method = "psci"; +- next-level-cache = <&cluster3_l2>; +- numa-node-id = <0>; +- }; +- +- cpu15: cpu@10303 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x10303>; +- enable-method = "psci"; +- next-level-cache = <&cluster3_l2>; +- numa-node-id = <0>; +- }; +- +- cpu16: cpu@30000 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x30000>; +- enable-method = "psci"; +- next-level-cache = <&cluster4_l2>; +- numa-node-id = <1>; +- }; +- +- cpu17: cpu@30001 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x30001>; +- enable-method = "psci"; +- next-level-cache = <&cluster4_l2>; +- numa-node-id = <1>; +- }; +- +- cpu18: cpu@30002 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x30002>; +- enable-method = "psci"; +- next-level-cache = <&cluster4_l2>; +- numa-node-id = <1>; +- }; +- +- cpu19: cpu@30003 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x30003>; +- enable-method = "psci"; +- next-level-cache = <&cluster4_l2>; +- numa-node-id = <1>; +- }; +- +- cpu20: cpu@30100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x30100>; +- enable-method = "psci"; +- next-level-cache = <&cluster5_l2>; +- numa-node-id = <1>; +- }; +- +- cpu21: cpu@30101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x30101>; +- enable-method = "psci"; +- next-level-cache = <&cluster5_l2>; +- numa-node-id = <1>; +- }; +- +- cpu22: cpu@30102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x30102>; +- enable-method = "psci"; +- next-level-cache = <&cluster5_l2>; +- numa-node-id = <1>; +- }; +- +- cpu23: cpu@30103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x30103>; +- enable-method = "psci"; +- next-level-cache = <&cluster5_l2>; +- numa-node-id = <1>; +- }; +- +- cpu24: cpu@30200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x30200>; +- enable-method = "psci"; +- next-level-cache = <&cluster6_l2>; +- numa-node-id = <1>; +- }; +- +- cpu25: cpu@30201 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x30201>; +- enable-method = "psci"; +- next-level-cache = <&cluster6_l2>; +- numa-node-id = <1>; +- }; +- +- cpu26: cpu@30202 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x30202>; +- enable-method = "psci"; +- next-level-cache = <&cluster6_l2>; +- numa-node-id = <1>; +- }; +- +- cpu27: cpu@30203 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x30203>; +- enable-method = "psci"; +- next-level-cache = <&cluster6_l2>; +- numa-node-id = <1>; +- }; +- +- cpu28: cpu@30300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x30300>; +- enable-method = "psci"; +- next-level-cache = <&cluster7_l2>; +- numa-node-id = <1>; +- }; +- +- cpu29: cpu@30301 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x30301>; +- enable-method = "psci"; +- next-level-cache = <&cluster7_l2>; +- numa-node-id = <1>; +- }; +- +- cpu30: cpu@30302 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x30302>; +- enable-method = "psci"; +- next-level-cache = <&cluster7_l2>; +- numa-node-id = <1>; +- }; +- +- cpu31: cpu@30303 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x30303>; +- enable-method = "psci"; +- next-level-cache = <&cluster7_l2>; +- numa-node-id = <1>; +- }; +- +- cpu32: cpu@50000 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x50000>; +- enable-method = "psci"; +- next-level-cache = <&cluster8_l2>; +- numa-node-id = <2>; +- }; +- +- cpu33: cpu@50001 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x50001>; +- enable-method = "psci"; +- next-level-cache = <&cluster8_l2>; +- numa-node-id = <2>; +- }; +- +- cpu34: cpu@50002 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x50002>; +- enable-method = "psci"; +- next-level-cache = <&cluster8_l2>; +- numa-node-id = <2>; +- }; +- +- cpu35: cpu@50003 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x50003>; +- enable-method = "psci"; +- next-level-cache = <&cluster8_l2>; +- numa-node-id = <2>; +- }; +- +- cpu36: cpu@50100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x50100>; +- enable-method = "psci"; +- next-level-cache = <&cluster9_l2>; +- numa-node-id = <2>; +- }; +- +- cpu37: cpu@50101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x50101>; +- enable-method = "psci"; +- next-level-cache = <&cluster9_l2>; +- numa-node-id = <2>; +- }; +- +- cpu38: cpu@50102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x50102>; +- enable-method = "psci"; +- next-level-cache = <&cluster9_l2>; +- numa-node-id = <2>; +- }; +- +- cpu39: cpu@50103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x50103>; +- enable-method = "psci"; +- next-level-cache = <&cluster9_l2>; +- numa-node-id = <2>; +- }; +- +- cpu40: cpu@50200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x50200>; +- enable-method = "psci"; +- next-level-cache = <&cluster10_l2>; +- numa-node-id = <2>; +- }; +- +- cpu41: cpu@50201 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x50201>; +- enable-method = "psci"; +- next-level-cache = <&cluster10_l2>; +- numa-node-id = <2>; +- }; +- +- cpu42: cpu@50202 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x50202>; +- enable-method = "psci"; +- next-level-cache = <&cluster10_l2>; +- numa-node-id = <2>; +- }; +- +- cpu43: cpu@50203 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x50203>; +- enable-method = "psci"; +- next-level-cache = <&cluster10_l2>; +- numa-node-id = <2>; +- }; +- +- cpu44: cpu@50300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x50300>; +- enable-method = "psci"; +- next-level-cache = <&cluster11_l2>; +- numa-node-id = <2>; +- }; +- +- cpu45: cpu@50301 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x50301>; +- enable-method = "psci"; +- next-level-cache = <&cluster11_l2>; +- numa-node-id = <2>; +- }; +- +- cpu46: cpu@50302 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x50302>; +- enable-method = "psci"; +- next-level-cache = <&cluster11_l2>; +- numa-node-id = <2>; +- }; +- +- cpu47: cpu@50303 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x50303>; +- enable-method = "psci"; +- next-level-cache = <&cluster11_l2>; +- numa-node-id = <2>; +- }; +- +- cpu48: cpu@70000 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x70000>; +- enable-method = "psci"; +- next-level-cache = <&cluster12_l2>; +- numa-node-id = <3>; +- }; +- +- cpu49: cpu@70001 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x70001>; +- enable-method = "psci"; +- next-level-cache = <&cluster12_l2>; +- numa-node-id = <3>; +- }; +- +- cpu50: cpu@70002 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x70002>; +- enable-method = "psci"; +- next-level-cache = <&cluster12_l2>; +- numa-node-id = <3>; +- }; +- +- cpu51: cpu@70003 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x70003>; +- enable-method = "psci"; +- next-level-cache = <&cluster12_l2>; +- numa-node-id = <3>; +- }; +- +- cpu52: cpu@70100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x70100>; +- enable-method = "psci"; +- next-level-cache = <&cluster13_l2>; +- numa-node-id = <3>; +- }; +- +- cpu53: cpu@70101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x70101>; +- enable-method = "psci"; +- next-level-cache = <&cluster13_l2>; +- numa-node-id = <3>; +- }; +- +- cpu54: cpu@70102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x70102>; +- enable-method = "psci"; +- next-level-cache = <&cluster13_l2>; +- numa-node-id = <3>; +- }; +- +- cpu55: cpu@70103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x70103>; +- enable-method = "psci"; +- next-level-cache = <&cluster13_l2>; +- numa-node-id = <3>; +- }; +- +- cpu56: cpu@70200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x70200>; +- enable-method = "psci"; +- next-level-cache = <&cluster14_l2>; +- numa-node-id = <3>; +- }; +- +- cpu57: cpu@70201 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x70201>; +- enable-method = "psci"; +- next-level-cache = <&cluster14_l2>; +- numa-node-id = <3>; +- }; +- +- cpu58: cpu@70202 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x70202>; +- enable-method = "psci"; +- next-level-cache = <&cluster14_l2>; +- numa-node-id = <3>; +- }; +- +- cpu59: cpu@70203 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x70203>; +- enable-method = "psci"; +- next-level-cache = <&cluster14_l2>; +- numa-node-id = <3>; +- }; +- +- cpu60: cpu@70300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x70300>; +- enable-method = "psci"; +- next-level-cache = <&cluster15_l2>; +- numa-node-id = <3>; +- }; +- +- cpu61: cpu@70301 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x70301>; +- enable-method = "psci"; +- next-level-cache = <&cluster15_l2>; +- numa-node-id = <3>; +- }; +- +- cpu62: cpu@70302 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x70302>; +- enable-method = "psci"; +- next-level-cache = <&cluster15_l2>; +- numa-node-id = <3>; +- }; +- +- cpu63: cpu@70303 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x70303>; +- enable-method = "psci"; +- next-level-cache = <&cluster15_l2>; +- numa-node-id = <3>; +- }; +- +- cluster0_l2: l2-cache0 { +- compatible = "cache"; +- }; +- +- cluster1_l2: l2-cache1 { +- compatible = "cache"; +- }; +- +- cluster2_l2: l2-cache2 { +- compatible = "cache"; +- }; +- +- cluster3_l2: l2-cache3 { +- compatible = "cache"; +- }; +- +- cluster4_l2: l2-cache4 { +- compatible = "cache"; +- }; +- +- cluster5_l2: l2-cache5 { +- compatible = "cache"; +- }; +- +- cluster6_l2: l2-cache6 { +- compatible = "cache"; +- }; +- +- cluster7_l2: l2-cache7 { +- compatible = "cache"; +- }; +- +- cluster8_l2: l2-cache8 { +- compatible = "cache"; +- }; +- +- cluster9_l2: l2-cache9 { +- compatible = "cache"; +- }; +- +- cluster10_l2: l2-cache10 { +- compatible = "cache"; +- }; +- +- cluster11_l2: l2-cache11 { +- compatible = "cache"; +- }; +- +- cluster12_l2: l2-cache12 { +- compatible = "cache"; +- }; +- +- cluster13_l2: l2-cache13 { +- compatible = "cache"; +- }; +- +- cluster14_l2: l2-cache14 { +- compatible = "cache"; +- }; +- +- cluster15_l2: l2-cache15 { +- compatible = "cache"; +- }; +- }; +- +- gic: interrupt-controller@4d000000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- interrupt-controller; +- #redistributor-regions = <4>; +- redistributor-stride = <0x0 0x40000>; +- reg = <0x0 0x4d000000 0x0 0x10000>, /* GICD */ +- <0x0 0x4d100000 0x0 0x400000>, /* p0 GICR node 0 */ +- <0x0 0x6d100000 0x0 0x400000>, /* p0 GICR node 1 */ +- <0x400 0x4d100000 0x0 0x400000>, /* p1 GICR node 2 */ +- <0x400 0x6d100000 0x0 0x400000>, /* p1 GICR node 3 */ +- <0x0 0xfe000000 0x0 0x10000>, /* GICC */ +- <0x0 0xfe010000 0x0 0x10000>, /* GICH */ +- <0x0 0xfe020000 0x0 0x10000>; /* GICV */ +- interrupts = ; +- +- p0_its_peri_a: msi-controller@4c000000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0x0 0x4c000000 0x0 0x40000>; +- }; +- +- p0_its_peri_b: msi-controller@6c000000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0x0 0x6c000000 0x0 0x40000>; +- }; +- +- p0_its_dsa_a: msi-controller@c6000000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0x0 0xc6000000 0x0 0x40000>; +- }; +- +- p0_its_dsa_b: msi-controller@8c6000000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0x8 0xc6000000 0x0 0x40000>; +- }; +- +- p1_its_peri_a: msi-controller@4004c000000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0x400 0x4c000000 0x0 0x40000>; +- }; +- +- p1_its_peri_b: msi-controller@4006c000000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0x400 0x6c000000 0x0 0x40000>; +- }; +- +- p1_its_dsa_a: msi-controller@400c6000000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0x400 0xc6000000 0x0 0x40000>; +- }; +- +- p1_its_dsa_b: msi-controller@408c6000000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0x408 0xc6000000 0x0 0x40000>; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,cortex-a72-pmu"; +- interrupts = ; +- }; +- +- p0_mbigen_peri_b: interrupt-controller@60080000 { +- compatible = "hisilicon,mbigen-v2"; +- reg = <0x0 0x60080000 0x0 0x10000>; +- +- mbigen_uart: uart_intc { +- msi-parent = <&p0_its_peri_b 0x120c7>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <1>; +- }; +- }; +- +- p0_mbigen_pcie_a: interrupt-controller@a0080000 { +- compatible = "hisilicon,mbigen-v2"; +- reg = <0x0 0xa0080000 0x0 0x10000>; +- +- mbigen_pcie2_a: intc_pcie2_a { +- msi-parent = <&p0_its_dsa_a 0x40087>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <10>; +- }; +- +- mbigen_sas1: intc_sas1 { +- msi-parent = <&p0_its_dsa_a 0x40000>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <128>; +- }; +- +- mbigen_sas2: intc_sas2 { +- msi-parent = <&p0_its_dsa_a 0x40040>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <128>; +- }; +- +- mbigen_smmu_pcie: intc_smmu_pcie { +- msi-parent = <&p0_its_dsa_a 0x40b0c>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <3>; +- }; +- +- mbigen_usb: intc_usb { +- msi-parent = <&p0_its_dsa_a 0x40080>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <2>; +- }; +- }; +- p0_mbigen_alg_a:interrupt-controller@d0080000 { +- compatible = "hisilicon,mbigen-v2"; +- reg = <0x0 0xd0080000 0x0 0x10000>; +- +- p0_mbigen_sec_a: intc_sec { +- msi-parent = <&p0_its_dsa_a 0x40400>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <33>; +- }; +- p0_mbigen_smmu_alg_a: intc_smmu_alg { +- msi-parent = <&p0_its_dsa_a 0x40b1b>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <3>; +- }; +- }; +- p0_mbigen_alg_b:interrupt-controller@8,d0080000 { +- compatible = "hisilicon,mbigen-v2"; +- reg = <0x8 0xd0080000 0x0 0x10000>; +- +- p0_mbigen_sec_b: intc_sec { +- msi-parent = <&p0_its_dsa_b 0x42400>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <33>; +- }; +- p0_mbigen_smmu_alg_b: intc_smmu_alg { +- msi-parent = <&p0_its_dsa_b 0x42b1b>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <3>; +- }; +- }; +- p1_mbigen_alg_a:interrupt-controller@400,d0080000 { +- compatible = "hisilicon,mbigen-v2"; +- reg = <0x400 0xd0080000 0x0 0x10000>; +- +- p1_mbigen_sec_a: intc_sec { +- msi-parent = <&p1_its_dsa_a 0x44400>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <33>; +- }; +- p1_mbigen_smmu_alg_a: intc_smmu_alg { +- msi-parent = <&p1_its_dsa_a 0x44b1b>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <3>; +- }; +- }; +- p1_mbigen_alg_b:interrupt-controller@408,d0080000 { +- compatible = "hisilicon,mbigen-v2"; +- reg = <0x408 0xd0080000 0x0 0x10000>; +- +- p1_mbigen_sec_b: intc_sec { +- msi-parent = <&p1_its_dsa_b 0x46400>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <33>; +- }; +- p1_mbigen_smmu_alg_b: intc_smmu_alg { +- msi-parent = <&p1_its_dsa_b 0x46b1b>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <3>; +- }; +- }; +- p0_mbigen_dsa_a: interrupt-controller@c0080000 { +- compatible = "hisilicon,mbigen-v2"; +- reg = <0x0 0xc0080000 0x0 0x10000>; +- +- mbigen_dsaf0: intc_dsaf0 { +- msi-parent = <&p0_its_dsa_a 0x40800>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <409>; +- }; +- +- mbigen_dsa_roce: intc-roce { +- msi-parent = <&p0_its_dsa_a 0x40B1E>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <34>; +- }; +- +- mbigen_sas0: intc-sas0 { +- msi-parent = <&p0_its_dsa_a 0x40900>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <128>; +- }; +- +- mbigen_smmu_dsa: intc_smmu_dsa { +- msi-parent = <&p0_its_dsa_a 0x40b20>; +- interrupt-controller; +- #interrupt-cells = <2>; +- num-pins = <3>; +- }; +- }; +- +- /** +- * HiSilicon erratum 161010801: This describes the limitation +- * of HiSilicon platforms hip06/hip07 to support the SMMUv3 +- * mappings for PCIe MSI transactions. +- * PCIe controller on these platforms has to differentiate the +- * MSI payload against other DMA payload and has to modify the +- * MSI payload. This makes it difficult for these platforms to +- * have a SMMU translation for MSI. In order to workaround this, +- * ARM SMMUv3 driver requires a quirk to treat the MSI regions +- * separately. Such a quirk is currently missing for DT based +- * systems. Hence please make sure that the smmu pcie node on +- * hip07 is disabled as this will break the PCIe functionality +- * when iommu-map entry is used along with the PCIe node. +- * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html +- */ +- smmu0: iommu@a0040000 { +- compatible = "arm,smmu-v3"; +- reg = <0x0 0xa0040000 0x0 0x20000>; +- #iommu-cells = <1>; +- dma-coherent; +- hisilicon,broken-prefetch-cmd; +- status = "disabled"; +- }; +- p0_smmu_alg_a: iommu@d0040000 { +- compatible = "arm,smmu-v3"; +- reg = <0x0 0xd0040000 0x0 0x20000>; +- interrupt-parent = <&p0_mbigen_smmu_alg_a>; +- interrupts = <733 1>, +- <734 1>, +- <735 1>; +- interrupt-names = "eventq", "gerror", "priq"; +- #iommu-cells = <1>; +- dma-coherent; +- hisilicon,broken-prefetch-cmd; +- }; +- p0_smmu_alg_b: iommu@8d0040000 { +- compatible = "arm,smmu-v3"; +- reg = <0x8 0xd0040000 0x0 0x20000>; +- interrupt-parent = <&p0_mbigen_smmu_alg_b>; +- interrupts = <733 1>, +- <734 1>, +- <735 1>; +- interrupt-names = "eventq", "gerror", "priq"; +- #iommu-cells = <1>; +- dma-coherent; +- hisilicon,broken-prefetch-cmd; +- }; +- p1_smmu_alg_a: iommu@400d0040000 { +- compatible = "arm,smmu-v3"; +- reg = <0x400 0xd0040000 0x0 0x20000>; +- interrupt-parent = <&p1_mbigen_smmu_alg_a>; +- interrupts = <733 1>, +- <734 1>, +- <735 1>; +- interrupt-names = "eventq", "gerror", "priq"; +- #iommu-cells = <1>; +- dma-coherent; +- hisilicon,broken-prefetch-cmd; +- }; +- p1_smmu_alg_b: iommu@408d0040000 { +- compatible = "arm,smmu-v3"; +- reg = <0x408 0xd0040000 0x0 0x20000>; +- interrupt-parent = <&p1_mbigen_smmu_alg_b>; +- interrupts = <733 1>, +- <734 1>, +- <735 1>; +- interrupt-names = "eventq", "gerror", "priq"; +- #iommu-cells = <1>; +- dma-coherent; +- hisilicon,broken-prefetch-cmd; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- isa@a01b0000 { +- compatible = "hisilicon,hip07-lpc"; +- #size-cells = <1>; +- #address-cells = <2>; +- reg = <0x0 0xa01b0000 0x0 0x1000>; +- +- ipmi0: bt@e4 { +- compatible = "ipmi-bt"; +- device_type = "ipmi"; +- reg = <0x01 0xe4 0x04>; +- status = "disabled"; +- }; +- }; +- +- uart0: uart@602b0000 { +- compatible = "arm,sbsa-uart"; +- reg = <0x0 0x602b0000 0x0 0x1000>; +- interrupt-parent = <&mbigen_uart>; +- interrupts = <807 4>; +- current-speed = <115200>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- usb_ohci: usb@a7030000 { +- compatible = "generic-ohci"; +- reg = <0x0 0xa7030000 0x0 0x10000>; +- interrupt-parent = <&mbigen_usb>; +- interrupts = <640 4>; +- dma-coherent; +- status = "disabled"; +- }; +- +- usb_ehci: usb@a7020000 { +- compatible = "generic-ehci"; +- reg = <0x0 0xa7020000 0x0 0x10000>; +- interrupt-parent = <&mbigen_usb>; +- interrupts = <641 4>; +- dma-coherent; +- status = "disabled"; +- }; +- +- peri_c_subctrl: sub_ctrl_c@60000000 { +- compatible = "hisilicon,peri-subctrl","syscon"; +- reg = <0 0x60000000 0x0 0x10000>; +- }; +- +- dsa_subctrl: dsa_subctrl@c0000000 { +- compatible = "hisilicon,dsa-subctrl", "syscon"; +- reg = <0x0 0xc0000000 0x0 0x10000>; +- }; +- +- dsa_cpld: dsa_cpld@78000010 { +- compatible = "syscon"; +- reg = <0x0 0x78000010 0x0 0x100>; +- reg-io-width = <2>; +- }; +- +- pcie_subctl: pcie_subctl@a0000000 { +- compatible = "hisilicon,pcie-sas-subctrl", "syscon"; +- reg = <0x0 0xa0000000 0x0 0x10000>; +- }; +- +- serdes_ctrl: sds_ctrl@c2200000 { +- compatible = "syscon"; +- reg = <0 0xc2200000 0x0 0x80000>; +- }; +- +- mdio@603c0000 { +- compatible = "hisilicon,hns-mdio"; +- reg = <0x0 0x603c0000 0x0 0x1000>; +- subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 +- 0x531c 0x5a1c>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +- +- phy1: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +- }; +- +- dsaf0: dsa@c7000000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "hisilicon,hns-dsaf-v2"; +- mode = "6port-16rss"; +- reg = <0x0 0xc5000000 0x0 0x890000>, +- <0x0 0xc7000000 0x0 0x600000>; +- reg-names = "ppe-base", "dsaf-base"; +- interrupt-parent = <&mbigen_dsaf0>; +- subctrl-syscon = <&dsa_subctrl>; +- reset-field-offset = <0>; +- interrupts = +- <576 1>, <577 1>, <578 1>, <579 1>, <580 1>, +- <581 1>, <582 1>, <583 1>, <584 1>, <585 1>, +- <586 1>, <587 1>, <588 1>, <589 1>, <590 1>, +- <591 1>, <592 1>, <593 1>, <594 1>, <595 1>, +- <596 1>, <597 1>, <598 1>, <599 1>, <600 1>, +- <960 1>, <961 1>, <962 1>, <963 1>, <964 1>, +- <965 1>, <966 1>, <967 1>, <968 1>, <969 1>, +- <970 1>, <971 1>, <972 1>, <973 1>, <974 1>, +- <975 1>, <976 1>, <977 1>, <978 1>, <979 1>, +- <980 1>, <981 1>, <982 1>, <983 1>, <984 1>, +- <985 1>, <986 1>, <987 1>, <988 1>, <989 1>, +- <990 1>, <991 1>, <992 1>, <993 1>, <994 1>, +- <995 1>, <996 1>, <997 1>, <998 1>, <999 1>, +- <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>, +- <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>, +- <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>, +- <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>, +- <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>, +- <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>, +- <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>, +- <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>, +- <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>, +- <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>, +- <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>, +- <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>, +- <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>, +- <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>, +- <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>, +- <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>, +- <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>, +- <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>, +- <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>, +- <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>, +- <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>, +- <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>, +- <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>, +- <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>, +- <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>, +- <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>, +- <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>, +- <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>, +- <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>, +- <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>, +- <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>, +- <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>, +- <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>, +- <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>, +- <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>, +- <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>, +- <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>, +- <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>, +- <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>, +- <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>, +- <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>, +- <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>, +- <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>, +- <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>, +- <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>, +- <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>, +- <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>, +- <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>, +- <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>, +- <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>, +- <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>, +- <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>, +- <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>, +- <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>, +- <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>, +- <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>, +- <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>, +- <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>, +- <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>, +- <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>, +- <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>, +- <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>, +- <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>, +- <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>, +- <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>, +- <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>, +- <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>, +- <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>, +- <1340 1>, <1341 1>, <1342 1>, <1343 1>; +- +- desc-num = <0x400>; +- buf-size = <0x1000>; +- dma-coherent; +- +- port@0 { +- reg = <0>; +- serdes-syscon = <&serdes_ctrl>; +- cpld-syscon = <&dsa_cpld 0x0>; +- port-rst-offset = <0>; +- port-mode-offset = <0>; +- mc-mac-mask = [ff f0 00 00 00 00]; +- media-type = "fiber"; +- }; +- +- port@1 { +- reg = <1>; +- serdes-syscon= <&serdes_ctrl>; +- cpld-syscon = <&dsa_cpld 0x4>; +- port-rst-offset = <1>; +- port-mode-offset = <1>; +- mc-mac-mask = [ff f0 00 00 00 00]; +- media-type = "fiber"; +- }; +- +- port@4 { +- reg = <4>; +- phy-handle = <&phy0>; +- serdes-syscon= <&serdes_ctrl>; +- port-rst-offset = <4>; +- port-mode-offset = <2>; +- mc-mac-mask = [ff f0 00 00 00 00]; +- media-type = "copper"; +- }; +- +- port@5 { +- reg = <5>; +- phy-handle = <&phy1>; +- serdes-syscon= <&serdes_ctrl>; +- port-rst-offset = <5>; +- port-mode-offset = <3>; +- mc-mac-mask = [ff f0 00 00 00 00]; +- media-type = "copper"; +- }; +- }; +- +- eth0: ethernet@4{ +- compatible = "hisilicon,hns-nic-v2"; +- ae-handle = <&dsaf0>; +- port-idx-in-ae = <4>; +- local-mac-address = [00 00 00 00 00 00]; +- status = "disabled"; +- dma-coherent; +- }; +- +- eth1: ethernet@5{ +- compatible = "hisilicon,hns-nic-v2"; +- ae-handle = <&dsaf0>; +- port-idx-in-ae = <5>; +- local-mac-address = [00 00 00 00 00 00]; +- status = "disabled"; +- dma-coherent; +- }; +- +- eth2: ethernet@0{ +- compatible = "hisilicon,hns-nic-v2"; +- ae-handle = <&dsaf0>; +- port-idx-in-ae = <0>; +- local-mac-address = [00 00 00 00 00 00]; +- status = "disabled"; +- dma-coherent; +- }; +- +- eth3: ethernet@1{ +- compatible = "hisilicon,hns-nic-v2"; +- ae-handle = <&dsaf0>; +- port-idx-in-ae = <1>; +- local-mac-address = [00 00 00 00 00 00]; +- status = "disabled"; +- dma-coherent; +- }; +- +- infiniband@c4000000 { +- compatible = "hisilicon,hns-roce-v1"; +- reg = <0x0 0xc4000000 0x0 0x100000>; +- dma-coherent; +- eth-handle = <ð2 ð3 0 0 ð0 ð1>; +- dsaf-handle = <&dsaf0>; +- node-guid = [00 9A CD 00 00 01 02 03]; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mbigen_dsa_roce>; +- interrupts = <722 1>, +- <723 1>, +- <724 1>, +- <725 1>, +- <726 1>, +- <727 1>, +- <728 1>, +- <729 1>, +- <730 1>, +- <731 1>, +- <732 1>, +- <733 1>, +- <734 1>, +- <735 1>, +- <736 1>, +- <737 1>, +- <738 1>, +- <739 1>, +- <740 1>, +- <741 1>, +- <742 1>, +- <743 1>, +- <744 1>, +- <745 1>, +- <746 1>, +- <747 1>, +- <748 1>, +- <749 1>, +- <750 1>, +- <751 1>, +- <752 1>, +- <753 1>, +- <785 1>, +- <754 4>; +- +- interrupt-names = "hns-roce-comp-0", +- "hns-roce-comp-1", +- "hns-roce-comp-2", +- "hns-roce-comp-3", +- "hns-roce-comp-4", +- "hns-roce-comp-5", +- "hns-roce-comp-6", +- "hns-roce-comp-7", +- "hns-roce-comp-8", +- "hns-roce-comp-9", +- "hns-roce-comp-10", +- "hns-roce-comp-11", +- "hns-roce-comp-12", +- "hns-roce-comp-13", +- "hns-roce-comp-14", +- "hns-roce-comp-15", +- "hns-roce-comp-16", +- "hns-roce-comp-17", +- "hns-roce-comp-18", +- "hns-roce-comp-19", +- "hns-roce-comp-20", +- "hns-roce-comp-21", +- "hns-roce-comp-22", +- "hns-roce-comp-23", +- "hns-roce-comp-24", +- "hns-roce-comp-25", +- "hns-roce-comp-26", +- "hns-roce-comp-27", +- "hns-roce-comp-28", +- "hns-roce-comp-29", +- "hns-roce-comp-30", +- "hns-roce-comp-31", +- "hns-roce-async", +- "hns-roce-common"; +- }; +- +- sas0: sas@c3000000 { +- compatible = "hisilicon,hip07-sas-v2"; +- reg = <0 0xc3000000 0 0x10000>; +- sas-addr = [50 01 88 20 16 00 00 00]; +- hisilicon,sas-syscon = <&dsa_subctrl>; +- ctrl-reset-reg = <0xa60>; +- ctrl-reset-sts-reg = <0x5a30>; +- ctrl-clock-ena-reg = <0x338>; +- queue-count = <16>; +- phy-count = <8>; +- dma-coherent; +- interrupt-parent = <&mbigen_sas0>; +- interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, +- <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, +- <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, +- <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, +- <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, +- <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, +- <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, +- <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, +- <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, +- <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, +- <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, +- <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, +- <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, +- <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, +- <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, +- <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, +- <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, +- <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, +- <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, +- <159 4>,<601 1>,<602 1>,<603 1>,<604 1>, +- <605 1>,<606 1>,<607 1>,<608 1>,<609 1>, +- <610 1>,<611 1>,<612 1>,<613 1>,<614 1>, +- <615 1>,<616 1>,<617 1>,<618 1>,<619 1>, +- <620 1>,<621 1>,<622 1>,<623 1>,<624 1>, +- <625 1>,<626 1>,<627 1>,<628 1>,<629 1>, +- <630 1>,<631 1>,<632 1>; +- status = "disabled"; +- }; +- +- sas1: sas@a2000000 { +- compatible = "hisilicon,hip07-sas-v2"; +- reg = <0 0xa2000000 0 0x10000>; +- sas-addr = [50 01 88 20 16 00 00 00]; +- hisilicon,sas-syscon = <&pcie_subctl>; +- hip06-sas-v2-quirk-amt; +- ctrl-reset-reg = <0xa18>; +- ctrl-reset-sts-reg = <0x5a0c>; +- ctrl-clock-ena-reg = <0x318>; +- queue-count = <16>; +- phy-count = <8>; +- dma-coherent; +- interrupt-parent = <&mbigen_sas1>; +- interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, +- <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, +- <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, +- <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, +- <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, +- <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, +- <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, +- <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, +- <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, +- <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, +- <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, +- <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, +- <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, +- <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, +- <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, +- <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, +- <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, +- <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, +- <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, +- <159 4>,<576 1>,<577 1>,<578 1>,<579 1>, +- <580 1>,<581 1>,<582 1>,<583 1>,<584 1>, +- <585 1>,<586 1>,<587 1>,<588 1>,<589 1>, +- <590 1>,<591 1>,<592 1>,<593 1>,<594 1>, +- <595 1>,<596 1>,<597 1>,<598 1>,<599 1>, +- <600 1>,<601 1>,<602 1>,<603 1>,<604 1>, +- <605 1>,<606 1>,<607 1>; +- status = "disabled"; +- }; +- +- sas2: sas@a3000000 { +- compatible = "hisilicon,hip07-sas-v2"; +- reg = <0 0xa3000000 0 0x10000>; +- sas-addr = [50 01 88 20 16 00 00 00]; +- hisilicon,sas-syscon = <&pcie_subctl>; +- ctrl-reset-reg = <0xae0>; +- ctrl-reset-sts-reg = <0x5a70>; +- ctrl-clock-ena-reg = <0x3a8>; +- queue-count = <16>; +- phy-count = <9>; +- dma-coherent; +- interrupt-parent = <&mbigen_sas2>; +- interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>, +- <197 4>,<198 4>,<199 4>,<200 4>,<201 4>, +- <202 4>,<203 4>,<204 4>,<205 4>,<206 4>, +- <207 4>,<208 4>,<209 4>,<210 4>,<211 4>, +- <212 4>,<213 4>,<214 4>,<215 4>,<216 4>, +- <217 4>,<218 4>,<219 4>,<220 4>,<221 4>, +- <222 4>,<223 4>,<224 4>,<225 4>,<226 4>, +- <227 4>,<228 4>,<229 4>,<230 4>,<231 4>, +- <232 4>,<233 4>,<234 4>,<235 4>,<236 4>, +- <237 4>,<238 4>,<239 4>,<240 4>,<241 4>, +- <242 4>,<243 4>,<244 4>,<245 4>,<246 4>, +- <247 4>,<248 4>,<249 4>,<250 4>,<251 4>, +- <252 4>,<253 4>,<254 4>,<255 4>,<256 4>, +- <257 4>,<258 4>,<259 4>,<260 4>,<261 4>, +- <262 4>,<263 4>,<264 4>,<265 4>,<266 4>, +- <267 4>,<268 4>,<269 4>,<270 4>,<271 4>, +- <272 4>,<273 4>,<274 4>,<275 4>,<276 4>, +- <277 4>,<278 4>,<279 4>,<280 4>,<281 4>, +- <282 4>,<283 4>,<284 4>,<285 4>,<286 4>, +- <287 4>,<608 1>,<609 1>,<610 1>,<611 1>, +- <612 1>,<613 1>,<614 1>,<615 1>,<616 1>, +- <617 1>,<618 1>,<619 1>,<620 1>,<621 1>, +- <622 1>,<623 1>,<624 1>,<625 1>,<626 1>, +- <627 1>,<628 1>,<629 1>,<630 1>,<631 1>, +- <632 1>,<633 1>,<634 1>,<635 1>,<636 1>, +- <637 1>,<638 1>,<639 1>; +- status = "disabled"; +- }; +- +- p0_pcie2_a: pcie@a00a0000 { +- compatible = "hisilicon,hip07-pcie-ecam"; +- reg = <0 0xaf800000 0 0x800000>, +- <0 0xa00a0000 0 0x10000>; +- bus-range = <0xf8 0xff>; +- msi-map = <0xf800 &p0_its_dsa_a 0xf800 0x800>; +- msi-map-mask = <0xffff>; +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- dma-coherent; +- ranges = <0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000>, +- <0x01000000 0 0 0 0xaf7f0000 0 0x10000>; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4 +- 0x0 0 0 2 &mbigen_pcie2_a 671 4 +- 0x0 0 0 3 &mbigen_pcie2_a 671 4 +- 0x0 0 0 4 &mbigen_pcie2_a 671 4>; +- status = "disabled"; +- }; +- p0_sec_a: crypto@d2000000 { +- compatible = "hisilicon,hip07-sec"; +- reg = <0x0 0xd0000000 0x0 0x10000>, +- <0x0 0xd2000000 0x0 0x10000>, +- <0x0 0xd2010000 0x0 0x10000>, +- <0x0 0xd2020000 0x0 0x10000>, +- <0x0 0xd2030000 0x0 0x10000>, +- <0x0 0xd2040000 0x0 0x10000>, +- <0x0 0xd2050000 0x0 0x10000>, +- <0x0 0xd2060000 0x0 0x10000>, +- <0x0 0xd2070000 0x0 0x10000>, +- <0x0 0xd2080000 0x0 0x10000>, +- <0x0 0xd2090000 0x0 0x10000>, +- <0x0 0xd20a0000 0x0 0x10000>, +- <0x0 0xd20b0000 0x0 0x10000>, +- <0x0 0xd20c0000 0x0 0x10000>, +- <0x0 0xd20d0000 0x0 0x10000>, +- <0x0 0xd20e0000 0x0 0x10000>, +- <0x0 0xd20f0000 0x0 0x10000>, +- <0x0 0xd2100000 0x0 0x10000>; +- interrupt-parent = <&p0_mbigen_sec_a>; +- iommus = <&p0_smmu_alg_a 0x600>; +- dma-coherent; +- interrupts = <576 4>, +- <577 1>, <578 4>, +- <579 1>, <580 4>, +- <581 1>, <582 4>, +- <583 1>, <584 4>, +- <585 1>, <586 4>, +- <587 1>, <588 4>, +- <589 1>, <590 4>, +- <591 1>, <592 4>, +- <593 1>, <594 4>, +- <595 1>, <596 4>, +- <597 1>, <598 4>, +- <599 1>, <600 4>, +- <601 1>, <602 4>, +- <603 1>, <604 4>, +- <605 1>, <606 4>, +- <607 1>, <608 4>; +- }; +- p0_sec_b: crypto@8,d2000000 { +- compatible = "hisilicon,hip07-sec"; +- reg = <0x8 0xd0000000 0x0 0x10000>, +- <0x8 0xd2000000 0x0 0x10000>, +- <0x8 0xd2010000 0x0 0x10000>, +- <0x8 0xd2020000 0x0 0x10000>, +- <0x8 0xd2030000 0x0 0x10000>, +- <0x8 0xd2040000 0x0 0x10000>, +- <0x8 0xd2050000 0x0 0x10000>, +- <0x8 0xd2060000 0x0 0x10000>, +- <0x8 0xd2070000 0x0 0x10000>, +- <0x8 0xd2080000 0x0 0x10000>, +- <0x8 0xd2090000 0x0 0x10000>, +- <0x8 0xd20a0000 0x0 0x10000>, +- <0x8 0xd20b0000 0x0 0x10000>, +- <0x8 0xd20c0000 0x0 0x10000>, +- <0x8 0xd20d0000 0x0 0x10000>, +- <0x8 0xd20e0000 0x0 0x10000>, +- <0x8 0xd20f0000 0x0 0x10000>, +- <0x8 0xd2100000 0x0 0x10000>; +- interrupt-parent = <&p0_mbigen_sec_b>; +- iommus = <&p0_smmu_alg_b 0x600>; +- dma-coherent; +- interrupts = <576 4>, +- <577 1>, <578 4>, +- <579 1>, <580 4>, +- <581 1>, <582 4>, +- <583 1>, <584 4>, +- <585 1>, <586 4>, +- <587 1>, <588 4>, +- <589 1>, <590 4>, +- <591 1>, <592 4>, +- <593 1>, <594 4>, +- <595 1>, <596 4>, +- <597 1>, <598 4>, +- <599 1>, <600 4>, +- <601 1>, <602 4>, +- <603 1>, <604 4>, +- <605 1>, <606 4>, +- <607 1>, <608 4>; +- }; +- p1_sec_a: crypto@400,d2000000 { +- compatible = "hisilicon,hip07-sec"; +- reg = <0x400 0xd0000000 0x0 0x10000>, +- <0x400 0xd2000000 0x0 0x10000>, +- <0x400 0xd2010000 0x0 0x10000>, +- <0x400 0xd2020000 0x0 0x10000>, +- <0x400 0xd2030000 0x0 0x10000>, +- <0x400 0xd2040000 0x0 0x10000>, +- <0x400 0xd2050000 0x0 0x10000>, +- <0x400 0xd2060000 0x0 0x10000>, +- <0x400 0xd2070000 0x0 0x10000>, +- <0x400 0xd2080000 0x0 0x10000>, +- <0x400 0xd2090000 0x0 0x10000>, +- <0x400 0xd20a0000 0x0 0x10000>, +- <0x400 0xd20b0000 0x0 0x10000>, +- <0x400 0xd20c0000 0x0 0x10000>, +- <0x400 0xd20d0000 0x0 0x10000>, +- <0x400 0xd20e0000 0x0 0x10000>, +- <0x400 0xd20f0000 0x0 0x10000>, +- <0x400 0xd2100000 0x0 0x10000>; +- interrupt-parent = <&p1_mbigen_sec_a>; +- iommus = <&p1_smmu_alg_a 0x600>; +- dma-coherent; +- interrupts = <576 4>, +- <577 1>, <578 4>, +- <579 1>, <580 4>, +- <581 1>, <582 4>, +- <583 1>, <584 4>, +- <585 1>, <586 4>, +- <587 1>, <588 4>, +- <589 1>, <590 4>, +- <591 1>, <592 4>, +- <593 1>, <594 4>, +- <595 1>, <596 4>, +- <597 1>, <598 4>, +- <599 1>, <600 4>, +- <601 1>, <602 4>, +- <603 1>, <604 4>, +- <605 1>, <606 4>, +- <607 1>, <608 4>; +- }; +- p1_sec_b: crypto@408,d2000000 { +- compatible = "hisilicon,hip07-sec"; +- reg = <0x408 0xd0000000 0x0 0x10000>, +- <0x408 0xd2000000 0x0 0x10000>, +- <0x408 0xd2010000 0x0 0x10000>, +- <0x408 0xd2020000 0x0 0x10000>, +- <0x408 0xd2030000 0x0 0x10000>, +- <0x408 0xd2040000 0x0 0x10000>, +- <0x408 0xd2050000 0x0 0x10000>, +- <0x408 0xd2060000 0x0 0x10000>, +- <0x408 0xd2070000 0x0 0x10000>, +- <0x408 0xd2080000 0x0 0x10000>, +- <0x408 0xd2090000 0x0 0x10000>, +- <0x408 0xd20a0000 0x0 0x10000>, +- <0x408 0xd20b0000 0x0 0x10000>, +- <0x408 0xd20c0000 0x0 0x10000>, +- <0x408 0xd20d0000 0x0 0x10000>, +- <0x408 0xd20e0000 0x0 0x10000>, +- <0x408 0xd20f0000 0x0 0x10000>, +- <0x408 0xd2100000 0x0 0x10000>; +- interrupt-parent = <&p1_mbigen_sec_b>; +- iommus = <&p1_smmu_alg_b 0x600>; +- dma-coherent; +- interrupts = <576 4>, +- <577 1>, <578 4>, +- <579 1>, <580 4>, +- <581 1>, <582 4>, +- <583 1>, <584 4>, +- <585 1>, <586 4>, +- <587 1>, <588 4>, +- <589 1>, <590 4>, +- <591 1>, <592 4>, +- <593 1>, <594 4>, +- <595 1>, <596 4>, +- <597 1>, <598 4>, +- <599 1>, <600 4>, +- <601 1>, <602 4>, +- <603 1>, <604 4>, +- <605 1>, <606 4>, +- <607 1>, <608 4>; +- }; +- +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/hisilicon/poplar-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm64/hisilicon/poplar-pinctrl.dtsi +deleted file mode 100644 +index 7bb19e4b084a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/hisilicon/poplar-pinctrl.dtsi ++++ /dev/null +@@ -1,98 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Pinctrl dts file for HiSilicon Poplar board +- * +- * Copyright (c) 2016-2018 HiSilicon Technologies Co., Ltd. +- */ +- +-#include +- +-/* value, enable bits, disable bits, mask */ +-#define PINCTRL_PULLDOWN(value, enable, disable, mask) \ +- (value << 13) (enable << 13) (disable << 13) (mask << 13) +-#define PINCTRL_PULLUP(value, enable, disable, mask) \ +- (value << 12) (enable << 12) (disable << 12) (mask << 12) +-#define PINCTRL_SLEW_RATE(value, mask) (value << 8) (mask << 8) +-#define PINCTRL_DRV_STRENGTH(value, mask) (value << 4) (mask << 4) +- +-&pmx0 { +- emmc_pins_1: emmc-pins-1 { +- pinctrl-single,pins = < +- 0x000 MUX_M2 +- 0x004 MUX_M2 +- 0x008 MUX_M2 +- 0x00c MUX_M2 +- 0x010 MUX_M2 +- 0x014 MUX_M2 +- 0x018 MUX_M2 +- 0x01c MUX_M2 +- 0x024 MUX_M2 +- >; +- pinctrl-single,bias-pulldown = < +- PINCTRL_PULLDOWN(0, 1, 0, 1) +- >; +- pinctrl-single,bias-pullup = < +- PINCTRL_PULLUP(0, 1, 0, 1) +- >; +- pinctrl-single,slew-rate = < +- PINCTRL_SLEW_RATE(1, 1) +- >; +- pinctrl-single,drive-strength = < +- PINCTRL_DRV_STRENGTH(0xb, 0xf) +- >; +- }; +- +- emmc_pins_2: emmc-pins-2 { +- pinctrl-single,pins = < +- 0x028 MUX_M2 +- >; +- pinctrl-single,bias-pulldown = < +- PINCTRL_PULLDOWN(0, 1, 0, 1) +- >; +- pinctrl-single,bias-pullup = < +- PINCTRL_PULLUP(0, 1, 0, 1) +- >; +- pinctrl-single,slew-rate = < +- PINCTRL_SLEW_RATE(1, 1) +- >; +- pinctrl-single,drive-strength = < +- PINCTRL_DRV_STRENGTH(0x9, 0xf) +- >; +- }; +- +- emmc_pins_3: emmc-pins-3 { +- pinctrl-single,pins = < +- 0x02c MUX_M2 +- >; +- pinctrl-single,bias-pulldown = < +- PINCTRL_PULLDOWN(0, 1, 0, 1) +- >; +- pinctrl-single,bias-pullup = < +- PINCTRL_PULLUP(0, 1, 0, 1) +- >; +- pinctrl-single,slew-rate = < +- PINCTRL_SLEW_RATE(1, 1) +- >; +- pinctrl-single,drive-strength = < +- PINCTRL_DRV_STRENGTH(3, 3) +- >; +- }; +- +- emmc_pins_4: emmc-pins-4 { +- pinctrl-single,pins = < +- 0x030 MUX_M2 +- >; +- pinctrl-single,bias-pulldown = < +- PINCTRL_PULLDOWN(1, 1, 0, 1) +- >; +- pinctrl-single,bias-pullup = < +- PINCTRL_PULLUP(0, 1, 0, 1) +- >; +- pinctrl-single,slew-rate = < +- PINCTRL_SLEW_RATE(1, 1) +- >; +- pinctrl-single,drive-strength = < +- PINCTRL_DRV_STRENGTH(3, 3) +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/intel/Makefile b/scripts/dtc/include-prefixes/arm64/intel/Makefile +deleted file mode 100644 +index 0b5477442263..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/intel/Makefile ++++ /dev/null +@@ -1,5 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0-only +-dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_socdk.dtb \ +- socfpga_agilex_socdk_nand.dtb \ +- socfpga_n5x_socdk.dtb +-dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/intel/keembay-evm.dts b/scripts/dtc/include-prefixes/arm64/intel/keembay-evm.dts +deleted file mode 100644 +index 466c85363a29..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/intel/keembay-evm.dts ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +-/* +- * Copyright (C) 2020, Intel Corporation +- * +- * Device tree describing Keem Bay EVM board. +- */ +- +-/dts-v1/; +- +-#include "keembay-soc.dtsi" +- +-/ { +- model = "Keem Bay EVM"; +- compatible = "intel,keembay-evm", "intel,keembay"; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- serial0 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- /* 2GB of DDR memory. */ +- reg = <0x0 0x80000000 0x0 0x80000000>; +- }; +- +-}; +- +-&uart3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/intel/keembay-soc.dtsi b/scripts/dtc/include-prefixes/arm64/intel/keembay-soc.dtsi +deleted file mode 100644 +index 781761d2942b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/intel/keembay-soc.dtsi ++++ /dev/null +@@ -1,123 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +-/* +- * Copyright (C) 2020, Intel Corporation. +- * +- * Device tree describing Keem Bay SoC. +- */ +- +-#include +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0>; +- enable-method = "psci"; +- }; +- +- cpu@1 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x1>; +- enable-method = "psci"; +- }; +- +- cpu@2 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x2>; +- enable-method = "psci"; +- }; +- +- cpu@3 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x3>; +- enable-method = "psci"; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- gic: interrupt-controller@20500000 { +- compatible = "arm,gic-v3"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x0 0x20500000 0x0 0x20000>, /* GICD */ +- <0x0 0x20580000 0x0 0x80000>; /* GICR */ +- /* VGIC maintenance interrupt */ +- interrupts = ; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- /* Secure, non-secure, virtual, and hypervisor */ +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = ; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- uart0: serial@20150000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x0 0x20150000 0x0 0x100>; +- interrupts = ; +- clock-frequency = <24000000>; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart1: serial@20160000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x0 0x20160000 0x0 0x100>; +- interrupts = ; +- clock-frequency = <24000000>; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart2: serial@20170000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x0 0x20170000 0x0 0x100>; +- interrupts = ; +- clock-frequency = <24000000>; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart3: serial@20180000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x0 0x20180000 0x0 0x100>; +- interrupts = ; +- clock-frequency = <24000000>; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/intel/socfpga_agilex.dtsi b/scripts/dtc/include-prefixes/arm64/intel/socfpga_agilex.dtsi +deleted file mode 100644 +index de1e98c99ec5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/intel/socfpga_agilex.dtsi ++++ /dev/null +@@ -1,657 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2019, Intel Corporation +- */ +- +-/dts-v1/; +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "intel,socfpga-agilex"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- service_reserved: svcbuffer@0 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x0 0x0 0x2000000>; +- alignment = <0x1000>; +- no-map; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "psci"; +- reg = <0x0>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "psci"; +- reg = <0x1>; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "psci"; +- reg = <0x2>; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "psci"; +- reg = <0x3>; +- }; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, +- <&cpu1>, +- <&cpu2>, +- <&cpu3>; +- interrupt-parent = <&intc>; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- intc: interrupt-controller@fffc1000 { +- compatible = "arm,gic-400", "arm,cortex-a15-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x0 0xfffc1000 0x0 0x1000>, +- <0x0 0xfffc2000 0x0 0x2000>, +- <0x0 0xfffc4000 0x0 0x2000>, +- <0x0 0xfffc6000 0x0 0x2000>; +- }; +- +- clocks { +- cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- }; +- +- cb_intosc_ls_clk: cb-intosc-ls-clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- }; +- +- f2s_free_clk: f2s-free-clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- }; +- +- osc1: osc1 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- }; +- +- qspi_clk: qspi-clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <200000000>; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupt-parent = <&intc>; +- interrupts = , +- , +- , +- ; +- }; +- +- usbphy0: usbphy { +- #phy-cells = <0>; +- compatible = "usb-nop-xceiv"; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- device_type = "soc"; +- interrupt-parent = <&intc>; +- ranges = <0 0 0 0xffffffff>; +- +- base_fpga_region { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- compatible = "fpga-region"; +- fpga-mgr = <&fpga_mgr>; +- }; +- +- clkmgr: clock-controller@ffd10000 { +- compatible = "intel,agilex-clkmgr"; +- reg = <0xffd10000 0x1000>; +- #clock-cells = <1>; +- }; +- +- gmac0: ethernet@ff800000 { +- compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; +- reg = <0xff800000 0x2000>; +- interrupts = ; +- interrupt-names = "macirq"; +- mac-address = [00 00 00 00 00 00]; +- resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; +- reset-names = "stmmaceth", "stmmaceth-ocp"; +- tx-fifo-depth = <16384>; +- rx-fifo-depth = <16384>; +- snps,multicast-filter-bins = <256>; +- iommus = <&smmu 1>; +- altr,sysmgr-syscon = <&sysmgr 0x44 0>; +- clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; +- clock-names = "stmmaceth", "ptp_ref"; +- status = "disabled"; +- }; +- +- gmac1: ethernet@ff802000 { +- compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; +- reg = <0xff802000 0x2000>; +- interrupts = ; +- interrupt-names = "macirq"; +- mac-address = [00 00 00 00 00 00]; +- resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; +- reset-names = "stmmaceth", "stmmaceth-ocp"; +- tx-fifo-depth = <16384>; +- rx-fifo-depth = <16384>; +- snps,multicast-filter-bins = <256>; +- iommus = <&smmu 2>; +- altr,sysmgr-syscon = <&sysmgr 0x48 0>; +- clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; +- clock-names = "stmmaceth", "ptp_ref"; +- status = "disabled"; +- }; +- +- gmac2: ethernet@ff804000 { +- compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; +- reg = <0xff804000 0x2000>; +- interrupts = ; +- interrupt-names = "macirq"; +- mac-address = [00 00 00 00 00 00]; +- resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; +- reset-names = "stmmaceth", "stmmaceth-ocp"; +- tx-fifo-depth = <16384>; +- rx-fifo-depth = <16384>; +- snps,multicast-filter-bins = <256>; +- iommus = <&smmu 3>; +- altr,sysmgr-syscon = <&sysmgr 0x4c 0>; +- clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; +- clock-names = "stmmaceth", "ptp_ref"; +- status = "disabled"; +- }; +- +- gpio0: gpio@ffc03200 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dw-apb-gpio"; +- reg = <0xffc03200 0x100>; +- resets = <&rst GPIO0_RESET>; +- status = "disabled"; +- +- porta: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <24>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- }; +- +- gpio1: gpio@ffc03300 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dw-apb-gpio"; +- reg = <0xffc03300 0x100>; +- resets = <&rst GPIO1_RESET>; +- status = "disabled"; +- +- portb: gpio-controller@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- snps,nr-gpios = <24>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- }; +- +- i2c0: i2c@ffc02800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xffc02800 0x100>; +- interrupts = ; +- resets = <&rst I2C0_RESET>; +- clocks = <&clkmgr AGILEX_L4_SP_CLK>; +- status = "disabled"; +- }; +- +- i2c1: i2c@ffc02900 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xffc02900 0x100>; +- interrupts = ; +- resets = <&rst I2C1_RESET>; +- clocks = <&clkmgr AGILEX_L4_SP_CLK>; +- status = "disabled"; +- }; +- +- i2c2: i2c@ffc02a00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xffc02a00 0x100>; +- interrupts = ; +- resets = <&rst I2C2_RESET>; +- clocks = <&clkmgr AGILEX_L4_SP_CLK>; +- status = "disabled"; +- }; +- +- i2c3: i2c@ffc02b00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xffc02b00 0x100>; +- interrupts = ; +- resets = <&rst I2C3_RESET>; +- clocks = <&clkmgr AGILEX_L4_SP_CLK>; +- status = "disabled"; +- }; +- +- i2c4: i2c@ffc02c00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,designware-i2c"; +- reg = <0xffc02c00 0x100>; +- interrupts = ; +- resets = <&rst I2C4_RESET>; +- clocks = <&clkmgr AGILEX_L4_SP_CLK>; +- status = "disabled"; +- }; +- +- mmc: dwmmc0@ff808000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "altr,socfpga-dw-mshc"; +- reg = <0xff808000 0x1000>; +- interrupts = ; +- fifo-depth = <0x400>; +- resets = <&rst SDMMC_RESET>; +- reset-names = "reset"; +- clocks = <&clkmgr AGILEX_L4_MP_CLK>, +- <&clkmgr AGILEX_SDMMC_CLK>; +- clock-names = "biu", "ciu"; +- iommus = <&smmu 5>; +- status = "disabled"; +- }; +- +- nand: nand-controller@ffb90000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "altr,socfpga-denali-nand"; +- reg = <0xffb90000 0x10000>, +- <0xffb80000 0x1000>; +- reg-names = "nand_data", "denali_reg"; +- interrupts = ; +- clocks = <&clkmgr AGILEX_NAND_CLK>, +- <&clkmgr AGILEX_NAND_X_CLK>, +- <&clkmgr AGILEX_NAND_ECC_CLK>; +- clock-names = "nand", "nand_x", "ecc"; +- resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; +- status = "disabled"; +- }; +- +- ocram: sram@ffe00000 { +- compatible = "mmio-sram"; +- reg = <0xffe00000 0x40000>; +- }; +- +- pdma: pdma@ffda0000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0xffda0000 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; +- reset-names = "dma", "dma-ocp"; +- clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; +- clock-names = "apb_pclk"; +- }; +- +- rst: rstmgr@ffd11000 { +- #reset-cells = <1>; +- compatible = "altr,stratix10-rst-mgr"; +- reg = <0xffd11000 0x100>; +- }; +- +- smmu: iommu@fa000000 { +- compatible = "arm,mmu-500", "arm,smmu-v2"; +- reg = <0xfa000000 0x40000>; +- #global-interrupts = <2>; +- #iommu-cells = <1>; +- interrupt-parent = <&intc>; +- /* Global Secure Fault */ +- interrupts = , +- /* Global Non-secure Fault */ +- , +- /* Non-secure Context Interrupts (32) */ +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- stream-match-mask = <0x7ff0>; +- clocks = <&clkmgr AGILEX_MPU_CCU_CLK>, +- <&clkmgr AGILEX_L3_MAIN_FREE_CLK>, +- <&clkmgr AGILEX_L4_MAIN_CLK>; +- status = "disabled"; +- }; +- +- spi0: spi@ffda4000 { +- compatible = "snps,dw-apb-ssi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xffda4000 0x1000>; +- interrupts = ; +- resets = <&rst SPIM0_RESET>; +- reset-names = "spi"; +- reg-io-width = <4>; +- num-cs = <4>; +- clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; +- status = "disabled"; +- }; +- +- spi1: spi@ffda5000 { +- compatible = "snps,dw-apb-ssi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xffda5000 0x1000>; +- interrupts = ; +- resets = <&rst SPIM1_RESET>; +- reset-names = "spi"; +- reg-io-width = <4>; +- num-cs = <4>; +- clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; +- status = "disabled"; +- }; +- +- sysmgr: sysmgr@ffd12000 { +- compatible = "altr,sys-mgr-s10","altr,sys-mgr"; +- reg = <0xffd12000 0x500>; +- }; +- +- timer0: timer0@ffc03000 { +- compatible = "snps,dw-apb-timer"; +- interrupts = ; +- reg = <0xffc03000 0x100>; +- clocks = <&clkmgr AGILEX_L4_SP_CLK>; +- clock-names = "timer"; +- }; +- +- timer1: timer1@ffc03100 { +- compatible = "snps,dw-apb-timer"; +- interrupts = ; +- reg = <0xffc03100 0x100>; +- clocks = <&clkmgr AGILEX_L4_SP_CLK>; +- clock-names = "timer"; +- }; +- +- timer2: timer2@ffd00000 { +- compatible = "snps,dw-apb-timer"; +- interrupts = ; +- reg = <0xffd00000 0x100>; +- clocks = <&clkmgr AGILEX_L4_SP_CLK>; +- clock-names = "timer"; +- }; +- +- timer3: timer3@ffd00100 { +- compatible = "snps,dw-apb-timer"; +- interrupts = ; +- reg = <0xffd00100 0x100>; +- clocks = <&clkmgr AGILEX_L4_SP_CLK>; +- clock-names = "timer"; +- }; +- +- uart0: serial@ffc02000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0xffc02000 0x100>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- resets = <&rst UART0_RESET>; +- status = "disabled"; +- clocks = <&clkmgr AGILEX_L4_SP_CLK>; +- }; +- +- uart1: serial@ffc02100 { +- compatible = "snps,dw-apb-uart"; +- reg = <0xffc02100 0x100>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- resets = <&rst UART1_RESET>; +- clocks = <&clkmgr AGILEX_L4_SP_CLK>; +- status = "disabled"; +- }; +- +- usb0: usb@ffb00000 { +- compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; +- reg = <0xffb00000 0x40000>; +- interrupts = ; +- phys = <&usbphy0>; +- phy-names = "usb2-phy"; +- resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; +- reset-names = "dwc2", "dwc2-ecc"; +- clocks = <&clkmgr AGILEX_USB_CLK>; +- iommus = <&smmu 6>; +- status = "disabled"; +- }; +- +- usb1: usb@ffb40000 { +- compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; +- reg = <0xffb40000 0x40000>; +- interrupts = ; +- phys = <&usbphy0>; +- phy-names = "usb2-phy"; +- resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; +- reset-names = "dwc2", "dwc2-ecc"; +- iommus = <&smmu 7>; +- clocks = <&clkmgr AGILEX_USB_CLK>; +- status = "disabled"; +- }; +- +- watchdog0: watchdog@ffd00200 { +- compatible = "snps,dw-wdt"; +- reg = <0xffd00200 0x100>; +- interrupts = ; +- resets = <&rst WATCHDOG0_RESET>; +- clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; +- status = "disabled"; +- }; +- +- watchdog1: watchdog@ffd00300 { +- compatible = "snps,dw-wdt"; +- reg = <0xffd00300 0x100>; +- interrupts = ; +- resets = <&rst WATCHDOG1_RESET>; +- clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; +- status = "disabled"; +- }; +- +- watchdog2: watchdog@ffd00400 { +- compatible = "snps,dw-wdt"; +- reg = <0xffd00400 0x100>; +- interrupts = ; +- resets = <&rst WATCHDOG2_RESET>; +- clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; +- status = "disabled"; +- }; +- +- watchdog3: watchdog@ffd00500 { +- compatible = "snps,dw-wdt"; +- reg = <0xffd00500 0x100>; +- interrupts = ; +- resets = <&rst WATCHDOG3_RESET>; +- clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; +- status = "disabled"; +- }; +- +- sdr: sdr@f8011100 { +- compatible = "altr,sdr-ctl", "syscon"; +- reg = <0xf8011100 0xc0>; +- }; +- +- eccmgr { +- compatible = "altr,socfpga-s10-ecc-manager", +- "altr,socfpga-a10-ecc-manager"; +- altr,sysmgr-syscon = <&sysmgr>; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <2>; +- ranges; +- +- sdramedac { +- compatible = "altr,sdram-edac-s10"; +- altr,sdr-syscon = <&sdr>; +- interrupts = <16 4>; +- }; +- +- ocram-ecc@ff8cc000 { +- compatible = "altr,socfpga-s10-ocram-ecc", +- "altr,socfpga-a10-ocram-ecc"; +- reg = <0xff8cc000 0x100>; +- altr,ecc-parent = <&ocram>; +- interrupts = <1 4>; +- }; +- +- usb0-ecc@ff8c4000 { +- compatible = "altr,socfpga-s10-usb-ecc", +- "altr,socfpga-usb-ecc"; +- reg = <0xff8c4000 0x100>; +- altr,ecc-parent = <&usb0>; +- interrupts = <2 4>; +- }; +- +- emac0-rx-ecc@ff8c0000 { +- compatible = "altr,socfpga-s10-eth-mac-ecc", +- "altr,socfpga-eth-mac-ecc"; +- reg = <0xff8c0000 0x100>; +- altr,ecc-parent = <&gmac0>; +- interrupts = <4 4>; +- }; +- +- emac0-tx-ecc@ff8c0400 { +- compatible = "altr,socfpga-s10-eth-mac-ecc", +- "altr,socfpga-eth-mac-ecc"; +- reg = <0xff8c0400 0x100>; +- altr,ecc-parent = <&gmac0>; +- interrupts = <5 4>; +- }; +- +- sdmmca-ecc@ff8c8c00 { +- compatible = "altr,socfpga-s10-sdmmc-ecc", +- "altr,socfpga-sdmmc-ecc"; +- reg = <0xff8c8c00 0x100>; +- altr,ecc-parent = <&mmc>; +- interrupts = <14 4>, +- <15 4>; +- }; +- }; +- +- qspi: spi@ff8d2000 { +- compatible = "cdns,qspi-nor"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xff8d2000 0x100>, +- <0xff900000 0x100000>; +- interrupts = ; +- cdns,fifo-depth = <128>; +- cdns,fifo-width = <4>; +- cdns,trigger-address = <0x00000000>; +- clocks = <&qspi_clk>; +- +- status = "disabled"; +- }; +- +- firmware { +- svc { +- compatible = "intel,agilex-svc"; +- method = "smc"; +- memory-region = <&service_reserved>; +- +- fpga_mgr: fpga-mgr { +- compatible = "intel,agilex-soc-fpga-mgr"; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/intel/socfpga_agilex_socdk.dts b/scripts/dtc/include-prefixes/arm64/intel/socfpga_agilex_socdk.dts +deleted file mode 100644 +index 0f7a0ba344be..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/intel/socfpga_agilex_socdk.dts ++++ /dev/null +@@ -1,138 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2019, Intel Corporation +- */ +-#include "socfpga_agilex.dtsi" +- +-/ { +- model = "SoCFPGA Agilex SoCDK"; +- +- aliases { +- serial0 = &uart0; +- ethernet0 = &gmac0; +- ethernet1 = &gmac1; +- ethernet2 = &gmac2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- hps0 { +- label = "hps_led0"; +- gpios = <&portb 20 GPIO_ACTIVE_HIGH>; +- }; +- +- hps1 { +- label = "hps_led1"; +- gpios = <&portb 19 GPIO_ACTIVE_HIGH>; +- }; +- +- hps2 { +- label = "hps_led2"; +- gpios = <&portb 21 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- /* We expect the bootloader to fill in the reg */ +- reg = <0 0 0 0>; +- }; +-}; +- +-&gpio1 { +- status = "okay"; +-}; +- +-&gmac0 { +- status = "okay"; +- phy-mode = "rgmii"; +- phy-handle = <&phy0>; +- +- max-frame-size = <9000>; +- +- mdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy0: ethernet-phy@0 { +- reg = <4>; +- +- txd0-skew-ps = <0>; /* -420ps */ +- txd1-skew-ps = <0>; /* -420ps */ +- txd2-skew-ps = <0>; /* -420ps */ +- txd3-skew-ps = <0>; /* -420ps */ +- rxd0-skew-ps = <420>; /* 0ps */ +- rxd1-skew-ps = <420>; /* 0ps */ +- rxd2-skew-ps = <420>; /* 0ps */ +- rxd3-skew-ps = <420>; /* 0ps */ +- txen-skew-ps = <0>; /* -420ps */ +- txc-skew-ps = <900>; /* 0ps */ +- rxdv-skew-ps = <420>; /* 0ps */ +- rxc-skew-ps = <1680>; /* 780ps */ +- }; +- }; +-}; +- +-&mmc { +- status = "okay"; +- cap-sd-highspeed; +- broken-cd; +- bus-width = <4>; +-}; +- +-&osc1 { +- clock-frequency = <25000000>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- disable-over-current; +-}; +- +-&watchdog0 { +- status = "okay"; +-}; +- +-&qspi { +- status = "okay"; +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,mt25qu02g", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <100000000>; +- +- m25p,fast-read; +- cdns,page-size = <256>; +- cdns,block-size = <16>; +- cdns,read-delay = <2>; +- cdns,tshsl-ns = <50>; +- cdns,tsd2d-ns = <50>; +- cdns,tchsh-ns = <4>; +- cdns,tslch-ns = <4>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- qspi_boot: partition@0 { +- label = "Boot and fpga data"; +- reg = <0x0 0x03FE0000>; +- }; +- +- qspi_rootfs: partition@3FE0000 { +- label = "Root Filesystem - JFFS2"; +- reg = <0x03FE0000 0x0C020000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/intel/socfpga_agilex_socdk_nand.dts b/scripts/dtc/include-prefixes/arm64/intel/socfpga_agilex_socdk_nand.dts +deleted file mode 100644 +index cc2dcabf34e3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/intel/socfpga_agilex_socdk_nand.dts ++++ /dev/null +@@ -1,131 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2019, Intel Corporation +- */ +-#include "socfpga_agilex.dtsi" +- +-/ { +- model = "SoCFPGA Agilex SoCDK"; +- +- aliases { +- serial0 = &uart0; +- ethernet0 = &gmac0; +- ethernet1 = &gmac1; +- ethernet2 = &gmac2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led0 { +- label = "hps_led0"; +- gpios = <&portb 20 GPIO_ACTIVE_HIGH>; +- }; +- +- led1 { +- label = "hps_led1"; +- gpios = <&portb 19 GPIO_ACTIVE_HIGH>; +- }; +- +- led2 { +- label = "hps_led2"; +- gpios = <&portb 21 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- /* We expect the bootloader to fill in the reg */ +- reg = <0 0 0 0>; +- }; +-}; +- +-&gpio1 { +- status = "okay"; +-}; +- +-&gmac2 { +- status = "okay"; +- phy-mode = "rgmii"; +- phy-handle = <&phy0>; +- +- max-frame-size = <9000>; +- +- mdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy0: ethernet-phy@0 { +- reg = <4>; +- +- txd0-skew-ps = <0>; /* -420ps */ +- txd1-skew-ps = <0>; /* -420ps */ +- txd2-skew-ps = <0>; /* -420ps */ +- txd3-skew-ps = <0>; /* -420ps */ +- rxd0-skew-ps = <420>; /* 0ps */ +- rxd1-skew-ps = <420>; /* 0ps */ +- rxd2-skew-ps = <420>; /* 0ps */ +- rxd3-skew-ps = <420>; /* 0ps */ +- txen-skew-ps = <0>; /* -420ps */ +- txc-skew-ps = <900>; /* 0ps */ +- rxdv-skew-ps = <420>; /* 0ps */ +- rxc-skew-ps = <1680>; /* 780ps */ +- }; +- }; +-}; +- +-&nand { +- status = "okay"; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- nand-bus-width = <16>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0 0x200000>; +- }; +- partition@200000 { +- label = "env"; +- reg = <0x200000 0x40000>; +- }; +- partition@240000 { +- label = "dtb"; +- reg = <0x240000 0x40000>; +- }; +- partition@280000 { +- label = "kernel"; +- reg = <0x280000 0x2000000>; +- }; +- partition@2280000 { +- label = "misc"; +- reg = <0x2280000 0x2000000>; +- }; +- partition@4280000 { +- label = "rootfs"; +- reg = <0x4280000 0x3bd80000>; +- }; +- }; +-}; +- +-&osc1 { +- clock-frequency = <25000000>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- disable-over-current; +-}; +- +-&watchdog0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/intel/socfpga_n5x_socdk.dts b/scripts/dtc/include-prefixes/arm64/intel/socfpga_n5x_socdk.dts +deleted file mode 100644 +index 01f1307ce4ac..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/intel/socfpga_n5x_socdk.dts ++++ /dev/null +@@ -1,49 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2021, Intel Corporation +- */ +-#include "socfpga_agilex.dtsi" +- +-/ { +- model = "eASIC N5X SoCDK"; +- +- aliases { +- serial0 = &uart0; +- ethernet0 = &gmac0; +- ethernet1 = &gmac1; +- ethernet2 = &gmac2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- /* We expect the bootloader to fill in the reg */ +- reg = <0 0 0 0>; +- }; +-}; +- +-&clkmgr { +- compatible = "intel,easic-n5x-clkmgr"; +-}; +- +-&mmc { +- status = "okay"; +- cap-sd-highspeed; +- broken-cd; +- bus-width = <4>; +-}; +- +-&osc1 { +- clock-frequency = <25000000>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&watchdog0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/lg/Makefile b/scripts/dtc/include-prefixes/arm64/lg/Makefile +deleted file mode 100644 +index 4c3959e24e1b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/lg/Makefile ++++ /dev/null +@@ -1,3 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_LG1K) += lg1312-ref.dtb +-dtb-$(CONFIG_ARCH_LG1K) += lg1313-ref.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/lg/lg1312-ref.dts b/scripts/dtc/include-prefixes/arm64/lg/lg1312-ref.dts +deleted file mode 100644 +index 260a2c5b19e5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/lg/lg1312-ref.dts ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * dts file for lg1312 Reference Board. +- * +- * Copyright (C) 2016, LG Electronics +- */ +- +-/dts-v1/; +- +-#include "lg1312.dtsi" +- +-/ { +- #address-cells = <2>; +- #size-cells = <1>; +- +- model = "LG Electronics, DTV SoC LG1312 Reference Board"; +- compatible = "lge,lg1312-ref", "lge,lg1312"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x00000000 0x20000000>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/lg/lg1312.dtsi b/scripts/dtc/include-prefixes/arm64/lg/lg1312.dtsi +deleted file mode 100644 +index 081fe7a9f605..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/lg/lg1312.dtsi ++++ /dev/null +@@ -1,352 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * dts file for lg1312 SoC +- * +- * Copyright (C) 2016, LG Electronics +- */ +- +-#include +-#include +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- +- compatible = "lge,lg1312"; +- interrupt-parent = <&gic>; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- next-level-cache = <&L2_0>; +- }; +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- next-level-cache = <&L2_0>; +- }; +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- next-level-cache = <&L2_0>; +- }; +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- next-level-cache = <&L2_0>; +- }; +- L2_0: l2-cache0 { +- compatible = "cache"; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2", "arm,psci"; +- method = "smc"; +- cpu_suspend = <0x84000001>; +- cpu_off = <0x84000002>; +- cpu_on = <0x84000003>; +- }; +- +- gic: interrupt-controller@c0001000 { +- #interrupt-cells = <3>; +- compatible = "arm,gic-400"; +- interrupt-controller; +- reg = <0x0 0xc0001000 0x1000>, +- <0x0 0xc0002000 0x2000>, +- <0x0 0xc0004000 0x2000>, +- <0x0 0xc0006000 0x2000>; +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, +- <&cpu1>, +- <&cpu2>, +- <&cpu3>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- clk_bus: clk_bus { +- #clock-cells = <0>; +- +- compatible = "fixed-clock"; +- clock-frequency = <198000000>; +- clock-output-names = "BUSCLK"; +- }; +- +- soc { +- #address-cells = <2>; +- #size-cells = <1>; +- +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- ranges; +- +- eth0: ethernet@c1b00000 { +- compatible = "cdns,gem"; +- reg = <0x0 0xc1b00000 0x1000>; +- interrupts = ; +- clocks = <&clk_bus>, <&clk_bus>; +- clock-names = "hclk", "pclk"; +- phy-mode = "rmii"; +- /* Filled in by boot */ +- mac-address = [ 00 00 00 00 00 00 ]; +- }; +- }; +- +- amba { +- #address-cells = <2>; +- #size-cells = <1>; +- #interrupt-cells = <3>; +- +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- ranges; +- +- timers: timer@fd100000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x0 0xfd100000 0x1000>; +- interrupts = ; +- clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>; +- clock-names = "timer0clk", "timer1clk", "apb_pclk"; +- }; +- wdog: watchdog@fd200000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xfd200000 0x1000>; +- interrupts = ; +- clocks = <&clk_bus>, <&clk_bus>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- uart0: serial@fe000000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xfe000000 0x1000>; +- interrupts = ; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- uart1: serial@fe100000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xfe100000 0x1000>; +- interrupts = ; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- uart2: serial@fe200000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xfe200000 0x1000>; +- interrupts = ; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- spi0: spi@fe800000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x0 0xfe800000 0x1000>; +- interrupts = ; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- }; +- spi1: spi@fe900000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x0 0xfe900000 0x1000>; +- interrupts = ; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- }; +- dmac0: dma@c1128000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xc1128000 0x1000>; +- interrupts = ; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- }; +- gpio0: gpio@fd400000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd400000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio1: gpio@fd410000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd410000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio2: gpio@fd420000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd420000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio3: gpio@fd430000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd430000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- }; +- gpio4: gpio@fd440000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd440000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio5: gpio@fd450000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd450000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio6: gpio@fd460000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd460000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio7: gpio@fd470000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd470000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio8: gpio@fd480000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd480000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio9: gpio@fd490000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd490000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio10: gpio@fd4a0000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd4a0000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio11: gpio@fd4b0000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd4b0000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- }; +- gpio12: gpio@fd4c0000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd4c0000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio13: gpio@fd4d0000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd4d0000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio14: gpio@fd4e0000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd4e0000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio15: gpio@fd4f0000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd4f0000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio16: gpio@fd500000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd500000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio17: gpio@fd510000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd510000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/lg/lg1313-ref.dts b/scripts/dtc/include-prefixes/arm64/lg/lg1313-ref.dts +deleted file mode 100644 +index e89ae853788a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/lg/lg1313-ref.dts ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * dts file for lg1313 Reference Board. +- * +- * Copyright (C) 2016, LG Electronics +- */ +- +-/dts-v1/; +- +-#include "lg1313.dtsi" +- +-/ { +- #address-cells = <2>; +- #size-cells = <1>; +- +- model = "LG Electronics, DTV SoC LG1313 Reference Board"; +- compatible = "lge,lg1313-ref", "lge,lg1313"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x00000000 0x20000000>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/lg/lg1313.dtsi b/scripts/dtc/include-prefixes/arm64/lg/lg1313.dtsi +deleted file mode 100644 +index 604bb6975337..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/lg/lg1313.dtsi ++++ /dev/null +@@ -1,352 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * dts file for lg1313 SoC +- * +- * Copyright (C) 2016, LG Electronics +- */ +- +-#include +-#include +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- +- compatible = "lge,lg1313"; +- interrupt-parent = <&gic>; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- next-level-cache = <&L2_0>; +- }; +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- next-level-cache = <&L2_0>; +- }; +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- next-level-cache = <&L2_0>; +- }; +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- next-level-cache = <&L2_0>; +- }; +- L2_0: l2-cache0 { +- compatible = "cache"; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2", "arm,psci"; +- method = "smc"; +- cpu_suspend = <0x84000001>; +- cpu_off = <0x84000002>; +- cpu_on = <0x84000003>; +- }; +- +- gic: interrupt-controller@c0001000 { +- #interrupt-cells = <3>; +- compatible = "arm,gic-400"; +- interrupt-controller; +- reg = <0x0 0xc0001000 0x1000>, +- <0x0 0xc0002000 0x2000>, +- <0x0 0xc0004000 0x2000>, +- <0x0 0xc0006000 0x2000>; +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, +- <&cpu1>, +- <&cpu2>, +- <&cpu3>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- clk_bus: clk_bus { +- #clock-cells = <0>; +- +- compatible = "fixed-clock"; +- clock-frequency = <198000000>; +- clock-output-names = "BUSCLK"; +- }; +- +- soc { +- #address-cells = <2>; +- #size-cells = <1>; +- +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- ranges; +- +- eth0: ethernet@c3700000 { +- compatible = "cdns,gem"; +- reg = <0x0 0xc3700000 0x1000>; +- interrupts = ; +- clocks = <&clk_bus>, <&clk_bus>; +- clock-names = "hclk", "pclk"; +- phy-mode = "rmii"; +- /* Filled in by boot */ +- mac-address = [ 00 00 00 00 00 00 ]; +- }; +- }; +- +- amba { +- #address-cells = <2>; +- #size-cells = <1>; +- #interrupt-cells = <3>; +- +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- ranges; +- +- timers: timer@fd100000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x0 0xfd100000 0x1000>; +- interrupts = ; +- clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>; +- clock-names = "timer0clk", "timer1clk", "apb_pclk"; +- }; +- wdog: watchdog@fd200000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x0 0xfd200000 0x1000>; +- interrupts = ; +- clocks = <&clk_bus>, <&clk_bus>; +- clock-names = "wdog_clk", "apb_pclk"; +- }; +- uart0: serial@fe000000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xfe000000 0x1000>; +- interrupts = ; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- uart1: serial@fe100000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xfe100000 0x1000>; +- interrupts = ; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- uart2: serial@fe200000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0x0 0xfe200000 0x1000>; +- interrupts = ; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- spi0: spi@fe800000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x0 0xfe800000 0x1000>; +- interrupts = ; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- }; +- spi1: spi@fe900000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x0 0xfe900000 0x1000>; +- interrupts = ; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- }; +- dmac0: dma@c1128000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xc1128000 0x1000>; +- interrupts = ; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- }; +- gpio0: gpio@fd400000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd400000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio1: gpio@fd410000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd410000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio2: gpio@fd420000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd420000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio3: gpio@fd430000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd430000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- }; +- gpio4: gpio@fd440000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd440000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio5: gpio@fd450000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd450000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio6: gpio@fd460000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd460000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio7: gpio@fd470000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd470000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio8: gpio@fd480000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd480000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio9: gpio@fd490000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd490000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio10: gpio@fd4a0000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd4a0000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio11: gpio@fd4b0000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd4b0000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- }; +- gpio12: gpio@fd4c0000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd4c0000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio13: gpio@fd4d0000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd4d0000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio14: gpio@fd4e0000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd4e0000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio15: gpio@fd4f0000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd4f0000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio16: gpio@fd500000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd500000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- status="disabled"; +- }; +- gpio17: gpio@fd510000 { +- #gpio-cells = <2>; +- compatible = "arm,pl061", "arm,primecell"; +- gpio-controller; +- reg = <0x0 0xfd510000 0x1000>; +- clocks = <&clk_bus>; +- clock-names = "apb_pclk"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/Makefile b/scripts/dtc/include-prefixes/arm64/marvell/Makefile +deleted file mode 100644 +index c686a8dd3ca5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/Makefile ++++ /dev/null +@@ -1,25 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-# Mvebu SoC Family +-dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-emmc.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-ultra.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-v7.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-v7-emmc.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-turris-mox.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-puzzle-m801.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db-B.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-B.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb +-dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-371x.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-371x.dtsi +deleted file mode 100644 +index dc1182ec9fa1..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-371x.dtsi ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell Armada 371x family of SoCs +- * (also named 88F3710) +- * +- * Copyright (C) 2016 Marvell +- * +- * Gregory CLEMENT +- * +- */ +- +-#include "armada-37xx.dtsi" +- +-/ { +- model = "Marvell Armada 3710 SoC"; +- compatible = "marvell,armada3710", "marvell,armada3700"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-db.dts b/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-db.dts +deleted file mode 100644 +index 3e5789f37206..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-db.dts ++++ /dev/null +@@ -1,220 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Marvell Armada 3720 development board +- * (DB-88F3720-DDR3) +- * Copyright (C) 2016 Marvell +- * +- * Gregory CLEMENT +- * +- * This file is compatible with the version 1.4 and the version 2.0 of +- * the board, however the CON numbers are different between the 2 +- * version +- */ +- +-/dts-v1/; +- +-#include +-#include "armada-372x.dtsi" +- +-/ { +- model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3"; +- compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000 0x20000000>; +- }; +- +- exp_usb3_vbus: usb3-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb3-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- gpio = <&gpio_exp 1 GPIO_ACTIVE_HIGH>; +- }; +- +- usb3_phy: usb3-phy { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <&exp_usb3_vbus>; +- }; +- +- vcc_sd_reg1: regulator { +- compatible = "regulator-gpio"; +- regulator-name = "vcc_sd1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- +- gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; +- gpios-states = <0>; +- states = <1800000 0x1 +- 3300000 0x0>; +- enable-active-high; +- }; +- +- vcc_sd_reg2: regulator-vmcc { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sd2"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- enable-active-high; +- gpio = <&gpio_exp 4 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-/* Gigabit module on CON19(V2.0)/CON21(V1.4) */ +-ð0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- phy-mode = "rgmii-id"; +- phy = <&phy0>; +- status = "okay"; +-}; +- +-/* Gigabit module on CON18(V2.0)/CON20(V1.4) */ +-ð1 { +- phy-mode = "sgmii"; +- phy = <&phy1>; +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "okay"; +- +- gpio_exp: pca9555@22 { +- compatible = "nxp,pca9555"; +- gpio-controller; +- #gpio-cells = <2>; +- +- reg = <0x22>; +- /* +- * IO0_0: PWR_EN_USB2 IO1_0: PWR_EN_VTT +- * IO0_1: PWR_EN_USB23 IO1_1: MPCIE_WDISABLE +- * IO0_2: PWR_EN_SATA IO1_2: RGMII_DEV_RSTN +- * IO0_3: PWR_EN_PCIE IO1_3: SGMII_DEV_RSTN +- * IO0_4: PWR_EN_SD +- * IO0_5: PWR_EN_EMMC +- * IO0_6: PWR_EN_RGMII IO1_6: SATA_USB3.0_SEL +- * IO0_7: PWR_EN_SGMII IO1_7: PWR_MCI_PS +- */ +- }; +- +- rtc@68 { +- /* PT7C4337A from pericom fully compatible with the ds1337 */ +- compatible = "dallas,ds1337"; +- reg = <0x68>; +- }; +-}; +- +-&mdio { +- status = "okay"; +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-/* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */ +-&pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; +- reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-/* CON3 */ +-&sata { +- status = "okay"; +-}; +- +-&sdhci0 { +- non-removable; +- bus-width = <8>; +- mmc-ddr-1_8v; +- mmc-hs400-1_8v; +- marvell,pad-type = "fixed-1-8v"; +- status = "okay"; +-}; +- +-/* SD slot module on CON14(V2.0)/CON15(V1.4) */ +-&sdhci1 { +- wp-inverted; +- cd-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- marvell,pad-type = "sd"; +- vqmmc-supply = <&vcc_sd_reg1>; +- vmmc-supply = <&vcc_sd_reg2>; +- status = "okay"; +-}; +- +-&spi0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_quad_pins>; +- +- m25p80@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <108000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <4>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "bootloader"; +- reg = <0x0 0x200000>; +- }; +- partition@200000 { +- label = "U-boot Env"; +- reg = <0x200000 0x10000>; +- }; +- partition@210000 { +- label = "Linux"; +- reg = <0x210000 0xDF0000>; +- }; +- }; +- }; +-}; +- +-/* +- * Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through +- * an FTDI (also on CON24(V2.0)/CON26(V1.4)). +- */ +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- status = "okay"; +-}; +- +-/* CON26(V2.0)/CON28(V1.4) */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "okay"; +-}; +- +-/* CON27(V2.0)/CON29(V1.4) */ +-&usb2 { +- status = "okay"; +-}; +- +-/* CON29(V2.0)/CON31(V1.4) */ +-&usb3 { +- status = "okay"; +- usb-phy = <&usb3_phy>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-espressobin-emmc.dts b/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-espressobin-emmc.dts +deleted file mode 100644 +index 5c4d8f379704..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-espressobin-emmc.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Globalscale Marvell ESPRESSOBin Board with eMMC +- * Copyright (C) 2018 Marvell +- * +- * Romain Perier +- * Konstantin Porotchkin +- * +- */ +-/* +- * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf +- */ +- +-/dts-v1/; +- +-#include "armada-3720-espressobin.dtsi" +- +-/ { +- model = "Globalscale Marvell ESPRESSOBin Board (eMMC)"; +- compatible = "globalscale,espressobin-emmc", "globalscale,espressobin", +- "marvell,armada3720", "marvell,armada3710"; +-}; +- +-&sdhci0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-espressobin-ultra.dts b/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-espressobin-ultra.dts +deleted file mode 100644 +index c5eb3604dd5b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-espressobin-ultra.dts ++++ /dev/null +@@ -1,165 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for ESPRESSObin-Ultra board. +- * Copyright (C) 2019 Globalscale technologies, Inc. +- * +- * Jason Hung +- */ +- +-/dts-v1/; +- +-#include "armada-3720-espressobin.dtsi" +- +-/ { +- model = "Globalscale Marvell ESPRESSOBin Ultra Board"; +- compatible = "globalscale,espressobin-ultra", "marvell,armada3720", +- "marvell,armada3710"; +- +- aliases { +- /* ethernet1 is WAN port */ +- ethernet1 = &switch0port5; +- ethernet2 = &switch0port1; +- ethernet3 = &switch0port2; +- ethernet4 = &switch0port3; +- ethernet5 = &switch0port4; +- }; +- +- reg_usb3_vbus: usb3-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb3-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpionb 19 GPIO_ACTIVE_HIGH>; +- }; +- +- usb3_phy: usb3-phy { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <®_usb3_vbus>; +- }; +- +- gpio-leds { +- pinctrl-names = "default"; +- compatible = "gpio-leds"; +- /* No assigned functions to the LEDs by default */ +- led1 { +- label = "ebin-ultra:blue:led1"; +- gpios = <&gpionb 11 GPIO_ACTIVE_LOW>; +- }; +- led2 { +- label = "ebin-ultra:green:led2"; +- gpios = <&gpionb 12 GPIO_ACTIVE_LOW>; +- }; +- led3 { +- label = "ebin-ultra:red:led3"; +- gpios = <&gpionb 13 GPIO_ACTIVE_LOW>; +- }; +- led4 { +- label = "ebin-ultra:yellow:led4"; +- gpios = <&gpionb 14 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&sdhci0 { +- status = "okay"; +-}; +- +-&sdhci1 { +- status = "disabled"; +-}; +- +-&spi0 { +- flash@0 { +- spi-max-frequency = <108000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <4>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "firmware"; +- reg = <0x0 0x3e0000>; +- }; +- partition@3e0000 { +- label = "hw-info"; +- reg = <0x3e0000 0x10000>; +- read-only; +- }; +- partition@3f0000 { +- label = "u-boot-env"; +- reg = <0x3f0000 0x10000>; +- }; +- }; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- +- clock-frequency = <100000>; +- +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +-}; +- +-&usb3 { +- usb-phy = <&usb3_phy>; +- status = "disabled"; +-}; +- +-&mdio { +- extphy: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&switch0 { +- reg = <3>; +- +- ports { +- switch0port1: port@1 { +- reg = <1>; +- label = "lan0"; +- phy-handle = <&switch0phy0>; +- }; +- +- switch0port2: port@2 { +- reg = <2>; +- label = "lan1"; +- phy-handle = <&switch0phy1>; +- }; +- +- switch0port3: port@3 { +- reg = <3>; +- label = "lan2"; +- phy-handle = <&switch0phy2>; +- }; +- +- switch0port4: port@4 { +- reg = <4>; +- label = "lan3"; +- phy-handle = <&switch0phy3>; +- }; +- +- switch0port5: port@5 { +- reg = <5>; +- label = "wan"; +- phy-handle = <&extphy>; +- phy-mode = "sgmii"; +- }; +- }; +- +- mdio { +- switch0phy3: switch0phy3@14 { +- reg = <0x14>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-espressobin-v7-emmc.dts b/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-espressobin-v7-emmc.dts +deleted file mode 100644 +index 75401eab4d42..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-espressobin-v7-emmc.dts ++++ /dev/null +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Globalscale Marvell ESPRESSOBin Board V7 with eMMC +- * Copyright (C) 2018 Marvell +- * +- * Romain Perier +- * Konstantin Porotchkin +- * +- */ +-/* +- * Schematic available at http://espressobin.net/wp-content/uploads/2020/05/ESPRESSObin_V7-0_Schematic.pdf +- */ +- +-/dts-v1/; +- +-#include "armada-3720-espressobin.dtsi" +- +-/ { +- model = "Globalscale Marvell ESPRESSOBin Board V7 (eMMC)"; +- compatible = "globalscale,espressobin-v7-emmc", "globalscale,espressobin-v7", +- "globalscale,espressobin", "marvell,armada3720", +- "marvell,armada3710"; +- +- aliases { +- /* ethernet1 is wan port */ +- ethernet1 = &switch0port3; +- ethernet3 = &switch0port1; +- }; +-}; +- +-&switch0port1 { +- label = "lan1"; +-}; +- +-&switch0port3 { +- label = "wan"; +-}; +- +-&sdhci0 { +- status = "okay"; +-}; +- +-&led2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-espressobin-v7.dts b/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-espressobin-v7.dts +deleted file mode 100644 +index 48a7f50fb427..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-espressobin-v7.dts ++++ /dev/null +@@ -1,40 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Globalscale Marvell ESPRESSOBin Board V7 +- * Copyright (C) 2018 Marvell +- * +- * Romain Perier +- * Konstantin Porotchkin +- * +- */ +-/* +- * Schematic available at http://espressobin.net/wp-content/uploads/2020/05/ESPRESSObin_V7-0_Schematic.pdf +- */ +- +-/dts-v1/; +- +-#include "armada-3720-espressobin.dtsi" +- +-/ { +- model = "Globalscale Marvell ESPRESSOBin Board V7"; +- compatible = "globalscale,espressobin-v7", "globalscale,espressobin", +- "marvell,armada3720", "marvell,armada3710"; +- +- aliases { +- /* ethernet1 is wan port */ +- ethernet1 = &switch0port3; +- ethernet3 = &switch0port1; +- }; +-}; +- +-&switch0port1 { +- label = "lan1"; +-}; +- +-&switch0port3 { +- label = "wan"; +-}; +- +-&led2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-espressobin.dts b/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-espressobin.dts +deleted file mode 100644 +index 1542d836c090..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-espressobin.dts ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Globalscale Marvell ESPRESSOBin Board +- * Copyright (C) 2016 Marvell +- * +- * Romain Perier +- * +- */ +-/* +- * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf +- */ +- +-/dts-v1/; +- +-#include "armada-3720-espressobin.dtsi" +- +-/ { +- model = "Globalscale Marvell ESPRESSOBin Board"; +- compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-espressobin.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-espressobin.dtsi +deleted file mode 100644 +index 5fc613d24151..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-espressobin.dtsi ++++ /dev/null +@@ -1,218 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Globalscale Marvell ESPRESSOBin Board +- * Copyright (C) 2016 Marvell +- * +- * Romain Perier +- * +- */ +- +-#include +-#include "armada-372x.dtsi" +- +-/ { +- aliases { +- ethernet0 = ð0; +- /* for dsa slave device */ +- ethernet1 = &switch0port1; +- ethernet2 = &switch0port2; +- ethernet3 = &switch0port3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000 0x20000000>; +- }; +- +- vcc_sd_reg1: regulator { +- compatible = "regulator-gpio"; +- regulator-name = "vcc_sd1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- +- gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>; +- gpios-states = <0>; +- states = <1800000 0x1 +- 3300000 0x0>; +- enable-active-high; +- }; +- +- led2: gpio-led2 { +- /* led2 is working only on v7 board */ +- status = "disabled"; +- +- compatible = "gpio-leds"; +- +- led2 { +- label = "led2"; +- gpios = <&gpionb 2 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +-}; +- +-/* J9 */ +-&pcie0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; +- reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; +-}; +- +-/* J6 */ +-&sata { +- status = "okay"; +-}; +- +-/* U11 */ +-&sdhci0 { +- /* Main DTS file for Espressobin is without eMMC */ +- status = "disabled"; +- +- non-removable; +- bus-width = <8>; +- mmc-ddr-1_8v; +- mmc-hs400-1_8v; +- marvell,xenon-emmc; +- marvell,xenon-tun-count = <9>; +- marvell,pad-type = "fixed-1-8v"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc_pins>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- mmccard: mmccard@0 { +- compatible = "mmc-card"; +- reg = <0>; +- }; +-}; +- +-/* J1 */ +-&sdhci1 { +- wp-inverted; +- bus-width = <4>; +- cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>; +- marvell,pad-type = "sd"; +- vqmmc-supply = <&vcc_sd_reg1>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio_pins>; +- status = "okay"; +-}; +- +-&spi0 { +- status = "okay"; +- +- flash@0 { +- reg = <0>; +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <104000000>; +- m25p,fast-read; +- }; +-}; +- +-/* Exported on the micro USB connector J5 through an FTDI */ +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- status = "okay"; +-}; +- +-/* +- * Connector J17 and J18 expose a number of different features. Some pins are +- * multiplexed. This is the case for instance for the following features: +- * - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of +- * how to enable it. Beware that the signals are 1.8V TTL. +- * - I2C +- * - SPI +- * - MMC +- */ +- +-/* J7 */ +-&usb3 { +- status = "okay"; +-}; +- +-/* J8 */ +-&usb2 { +- status = "okay"; +-}; +- +-&mdio { +- switch0: switch0@1 { +- compatible = "marvell,mv88e6085"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- dsa,member = <0 0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch0port0: port@0 { +- reg = <0>; +- label = "cpu"; +- ethernet = <ð0>; +- phy-mode = "rgmii-id"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- switch0port1: port@1 { +- reg = <1>; +- label = "wan"; +- phy-handle = <&switch0phy0>; +- }; +- +- switch0port2: port@2 { +- reg = <2>; +- label = "lan0"; +- phy-handle = <&switch0phy1>; +- }; +- +- switch0port3: port@3 { +- reg = <3>; +- label = "lan1"; +- phy-handle = <&switch0phy2>; +- }; +- +- }; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch0phy0: switch0phy0@11 { +- reg = <0x11>; +- }; +- switch0phy1: switch0phy1@12 { +- reg = <0x12>; +- }; +- switch0phy2: switch0phy2@13 { +- reg = <0x13>; +- }; +- }; +- }; +-}; +- +-ð0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>, <&smi_pins>; +- phy-mode = "rgmii-id"; +- status = "okay"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-turris-mox.dts b/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-turris-mox.dts +deleted file mode 100644 +index 1cee26479bfe..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-turris-mox.dts ++++ /dev/null +@@ -1,870 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for CZ.NIC Turris Mox Board +- * 2019 by Marek Behún +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include "armada-372x.dtsi" +- +-/ { +- model = "CZ.NIC Turris Mox Board"; +- compatible = "cznic,turris-mox", "marvell,armada3720", +- "marvell,armada3710"; +- +- aliases { +- spi0 = &spi0; +- ethernet0 = ð0; +- ethernet1 = ð1; +- mmc0 = &sdhci0; +- mmc1 = &sdhci1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000 0x20000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- red { +- label = "mox:red:activity"; +- gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "default-on"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- reset { +- label = "reset"; +- linux,code = ; +- gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>; +- debounce-interval = <60>; +- }; +- }; +- +- exp_usb3_vbus: usb3-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb3-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- regulator-always-on; +- gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>; +- }; +- +- vsdc_reg: vsdc-reg { +- compatible = "regulator-gpio"; +- regulator-name = "vsdc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- +- gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; +- gpios-states = <0>; +- states = <1800000 0x1 +- 3300000 0x0>; +- enable-active-high; +- }; +- +- vsdio_reg: vsdio-reg { +- compatible = "regulator-gpio"; +- regulator-name = "vsdio"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- +- gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>; +- gpios-states = <0>; +- states = <1800000 0x1 +- 3300000 0x0>; +- enable-active-high; +- }; +- +- sdhci1_pwrseq: sdhci1-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- sfp: sfp { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c0>; +- los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>; +- tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>; +- tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>; +- rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>; +- maximum-power-milliwatt = <3000>; +- +- /* enabled by U-Boot if SFP module is present */ +- status = "disabled"; +- }; +- +- firmware { +- armada-3700-rwtm { +- compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm"; +- }; +- }; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- clock-frequency = <100000>; +- /delete-property/ mrvl,i2c-fast-mode; +- status = "okay"; +- +- rtc@6f { +- compatible = "microchip,mcp7940x"; +- reg = <0x6f>; +- }; +-}; +- +-&pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; +- status = "okay"; +- reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; +- /* +- * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property +- * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and +- * 2 size cells and also expects that the second range starts at 16 MB offset. Also it +- * expects that first range uses same address for PCI (child) and CPU (parent) cells (so +- * no remapping) and that this address is the lowest from all specified ranges. If these +- * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address +- * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window +- * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB. +- * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in +- * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix): +- * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7 +- * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf +- * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33 +- * Bug related to requirement of same child and parent addresses for first range is fixed +- * in U-Boot version 2022.04 by following commit: +- * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17 +- */ +- #address-cells = <3>; +- #size-cells = <2>; +- ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */ +- 0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */ +- +- /* enabled by U-Boot if PCIe module is present */ +- status = "disabled"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-ð0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- phy-mode = "rgmii-id"; +- phy-handle = <&phy1>; +- status = "okay"; +-}; +- +-ð1 { +- phy-mode = "2500base-x"; +- managed = "in-band-status"; +- phys = <&comphy0 1>; +-}; +- +-&sdhci0 { +- wp-inverted; +- bus-width = <4>; +- cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>; +- vqmmc-supply = <&vsdc_reg>; +- marvell,pad-type = "sd"; +- status = "okay"; +-}; +- +-&sdhci1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio_pins>; +- non-removable; +- bus-width = <4>; +- marvell,pad-type = "sd"; +- vqmmc-supply = <&vsdio_reg>; +- mmc-pwrseq = <&sdhci1_pwrseq>; +- /* forbid SDR104 for FCC purposes */ +- sdhci-caps-mask = <0x2 0x0>; +- status = "okay"; +-}; +- +-&spi0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>; +- assigned-clocks = <&nb_periph_clk 7>; +- assigned-clock-parents = <&tbg 1>; +- assigned-clock-rates = <20000000>; +- +- spi-flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "secure-firmware"; +- reg = <0x0 0x20000>; +- }; +- +- partition@20000 { +- label = "a53-firmware"; +- reg = <0x20000 0x160000>; +- }; +- +- partition@180000 { +- label = "u-boot-env"; +- reg = <0x180000 0x10000>; +- }; +- +- partition@190000 { +- label = "Rescue system"; +- reg = <0x190000 0x660000>; +- }; +- +- partition@7f0000 { +- label = "dtb"; +- reg = <0x7f0000 0x10000>; +- }; +- }; +- }; +- +- moxtet: moxtet@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "cznic,moxtet"; +- reg = <1>; +- reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; +- spi-max-frequency = <10000000>; +- spi-cpol; +- spi-cpha; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&gpiosb>; +- interrupts = <5 IRQ_TYPE_EDGE_FALLING>; +- status = "okay"; +- +- moxtet_sfp: gpio@0 { +- compatible = "cznic,moxtet-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0>; +- status = "disabled"; +- }; +- }; +-}; +- +-&usb2 { +- status = "okay"; +-}; +- +-&comphy2 { +- connector { +- compatible = "usb-a-connector"; +- phy-supply = <&exp_usb3_vbus>; +- }; +-}; +- +-&usb3 { +- status = "okay"; +- phys = <&comphy2 0>; +-}; +- +-&mdio { +- pinctrl-names = "default"; +- pinctrl-0 = <&smi_pins>; +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +- +- /* switch nodes are enabled by U-Boot if modules are present */ +- switch0@10 { +- compatible = "marvell,mv88e6190"; +- reg = <0x10 0>; +- dsa,member = <0 0>; +- interrupt-parent = <&moxtet>; +- interrupts = ; +- status = "disabled"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch0phy1: switch0phy1@1 { +- reg = <0x1>; +- }; +- +- switch0phy2: switch0phy2@2 { +- reg = <0x2>; +- }; +- +- switch0phy3: switch0phy3@3 { +- reg = <0x3>; +- }; +- +- switch0phy4: switch0phy4@4 { +- reg = <0x4>; +- }; +- +- switch0phy5: switch0phy5@5 { +- reg = <0x5>; +- }; +- +- switch0phy6: switch0phy6@6 { +- reg = <0x6>; +- }; +- +- switch0phy7: switch0phy7@7 { +- reg = <0x7>; +- }; +- +- switch0phy8: switch0phy8@8 { +- reg = <0x8>; +- }; +- }; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <0x1>; +- label = "lan1"; +- phy-handle = <&switch0phy1>; +- }; +- +- port@2 { +- reg = <0x2>; +- label = "lan2"; +- phy-handle = <&switch0phy2>; +- }; +- +- port@3 { +- reg = <0x3>; +- label = "lan3"; +- phy-handle = <&switch0phy3>; +- }; +- +- port@4 { +- reg = <0x4>; +- label = "lan4"; +- phy-handle = <&switch0phy4>; +- }; +- +- port@5 { +- reg = <0x5>; +- label = "lan5"; +- phy-handle = <&switch0phy5>; +- }; +- +- port@6 { +- reg = <0x6>; +- label = "lan6"; +- phy-handle = <&switch0phy6>; +- }; +- +- port@7 { +- reg = <0x7>; +- label = "lan7"; +- phy-handle = <&switch0phy7>; +- }; +- +- port@8 { +- reg = <0x8>; +- label = "lan8"; +- phy-handle = <&switch0phy8>; +- }; +- +- port@9 { +- reg = <0x9>; +- label = "cpu"; +- ethernet = <ð1>; +- phy-mode = "2500base-x"; +- managed = "in-band-status"; +- }; +- +- switch0port10: port@a { +- reg = <0xa>; +- label = "dsa"; +- phy-mode = "2500base-x"; +- managed = "in-band-status"; +- link = <&switch1port9 &switch2port9>; +- status = "disabled"; +- }; +- +- port-sfp@a { +- reg = <0xa>; +- label = "sfp"; +- sfp = <&sfp>; +- phy-mode = "sgmii"; +- managed = "in-band-status"; +- status = "disabled"; +- }; +- }; +- }; +- +- switch0@2 { +- compatible = "marvell,mv88e6085"; +- reg = <0x2 0>; +- dsa,member = <0 0>; +- interrupt-parent = <&moxtet>; +- interrupts = ; +- status = "disabled"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch0phy1_topaz: switch0phy1@11 { +- reg = <0x11>; +- }; +- +- switch0phy2_topaz: switch0phy2@12 { +- reg = <0x12>; +- }; +- +- switch0phy3_topaz: switch0phy3@13 { +- reg = <0x13>; +- }; +- +- switch0phy4_topaz: switch0phy4@14 { +- reg = <0x14>; +- }; +- }; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <0x1>; +- label = "lan1"; +- phy-handle = <&switch0phy1_topaz>; +- }; +- +- port@2 { +- reg = <0x2>; +- label = "lan2"; +- phy-handle = <&switch0phy2_topaz>; +- }; +- +- port@3 { +- reg = <0x3>; +- label = "lan3"; +- phy-handle = <&switch0phy3_topaz>; +- }; +- +- port@4 { +- reg = <0x4>; +- label = "lan4"; +- phy-handle = <&switch0phy4_topaz>; +- }; +- +- port@5 { +- reg = <0x5>; +- label = "cpu"; +- phy-mode = "2500base-x"; +- managed = "in-band-status"; +- ethernet = <ð1>; +- }; +- }; +- }; +- +- switch1@11 { +- compatible = "marvell,mv88e6190"; +- reg = <0x11 0>; +- dsa,member = <0 1>; +- interrupt-parent = <&moxtet>; +- interrupts = ; +- status = "disabled"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch1phy1: switch1phy1@1 { +- reg = <0x1>; +- }; +- +- switch1phy2: switch1phy2@2 { +- reg = <0x2>; +- }; +- +- switch1phy3: switch1phy3@3 { +- reg = <0x3>; +- }; +- +- switch1phy4: switch1phy4@4 { +- reg = <0x4>; +- }; +- +- switch1phy5: switch1phy5@5 { +- reg = <0x5>; +- }; +- +- switch1phy6: switch1phy6@6 { +- reg = <0x6>; +- }; +- +- switch1phy7: switch1phy7@7 { +- reg = <0x7>; +- }; +- +- switch1phy8: switch1phy8@8 { +- reg = <0x8>; +- }; +- }; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <0x1>; +- label = "lan9"; +- phy-handle = <&switch1phy1>; +- }; +- +- port@2 { +- reg = <0x2>; +- label = "lan10"; +- phy-handle = <&switch1phy2>; +- }; +- +- port@3 { +- reg = <0x3>; +- label = "lan11"; +- phy-handle = <&switch1phy3>; +- }; +- +- port@4 { +- reg = <0x4>; +- label = "lan12"; +- phy-handle = <&switch1phy4>; +- }; +- +- port@5 { +- reg = <0x5>; +- label = "lan13"; +- phy-handle = <&switch1phy5>; +- }; +- +- port@6 { +- reg = <0x6>; +- label = "lan14"; +- phy-handle = <&switch1phy6>; +- }; +- +- port@7 { +- reg = <0x7>; +- label = "lan15"; +- phy-handle = <&switch1phy7>; +- }; +- +- port@8 { +- reg = <0x8>; +- label = "lan16"; +- phy-handle = <&switch1phy8>; +- }; +- +- switch1port9: port@9 { +- reg = <0x9>; +- label = "dsa"; +- phy-mode = "2500base-x"; +- managed = "in-band-status"; +- link = <&switch0port10>; +- }; +- +- switch1port10: port@a { +- reg = <0xa>; +- label = "dsa"; +- phy-mode = "2500base-x"; +- managed = "in-band-status"; +- link = <&switch2port9>; +- status = "disabled"; +- }; +- +- port-sfp@a { +- reg = <0xa>; +- label = "sfp"; +- sfp = <&sfp>; +- phy-mode = "sgmii"; +- managed = "in-band-status"; +- status = "disabled"; +- }; +- }; +- }; +- +- switch1@2 { +- compatible = "marvell,mv88e6085"; +- reg = <0x2 0>; +- dsa,member = <0 1>; +- interrupt-parent = <&moxtet>; +- interrupts = ; +- status = "disabled"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch1phy1_topaz: switch1phy1@11 { +- reg = <0x11>; +- }; +- +- switch1phy2_topaz: switch1phy2@12 { +- reg = <0x12>; +- }; +- +- switch1phy3_topaz: switch1phy3@13 { +- reg = <0x13>; +- }; +- +- switch1phy4_topaz: switch1phy4@14 { +- reg = <0x14>; +- }; +- }; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <0x1>; +- label = "lan9"; +- phy-handle = <&switch1phy1_topaz>; +- }; +- +- port@2 { +- reg = <0x2>; +- label = "lan10"; +- phy-handle = <&switch1phy2_topaz>; +- }; +- +- port@3 { +- reg = <0x3>; +- label = "lan11"; +- phy-handle = <&switch1phy3_topaz>; +- }; +- +- port@4 { +- reg = <0x4>; +- label = "lan12"; +- phy-handle = <&switch1phy4_topaz>; +- }; +- +- port@5 { +- reg = <0x5>; +- label = "dsa"; +- phy-mode = "2500base-x"; +- managed = "in-band-status"; +- link = <&switch0port10>; +- }; +- }; +- }; +- +- switch2@12 { +- compatible = "marvell,mv88e6190"; +- reg = <0x12 0>; +- dsa,member = <0 2>; +- interrupt-parent = <&moxtet>; +- interrupts = ; +- status = "disabled"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch2phy1: switch2phy1@1 { +- reg = <0x1>; +- }; +- +- switch2phy2: switch2phy2@2 { +- reg = <0x2>; +- }; +- +- switch2phy3: switch2phy3@3 { +- reg = <0x3>; +- }; +- +- switch2phy4: switch2phy4@4 { +- reg = <0x4>; +- }; +- +- switch2phy5: switch2phy5@5 { +- reg = <0x5>; +- }; +- +- switch2phy6: switch2phy6@6 { +- reg = <0x6>; +- }; +- +- switch2phy7: switch2phy7@7 { +- reg = <0x7>; +- }; +- +- switch2phy8: switch2phy8@8 { +- reg = <0x8>; +- }; +- }; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <0x1>; +- label = "lan17"; +- phy-handle = <&switch2phy1>; +- }; +- +- port@2 { +- reg = <0x2>; +- label = "lan18"; +- phy-handle = <&switch2phy2>; +- }; +- +- port@3 { +- reg = <0x3>; +- label = "lan19"; +- phy-handle = <&switch2phy3>; +- }; +- +- port@4 { +- reg = <0x4>; +- label = "lan20"; +- phy-handle = <&switch2phy4>; +- }; +- +- port@5 { +- reg = <0x5>; +- label = "lan21"; +- phy-handle = <&switch2phy5>; +- }; +- +- port@6 { +- reg = <0x6>; +- label = "lan22"; +- phy-handle = <&switch2phy6>; +- }; +- +- port@7 { +- reg = <0x7>; +- label = "lan23"; +- phy-handle = <&switch2phy7>; +- }; +- +- port@8 { +- reg = <0x8>; +- label = "lan24"; +- phy-handle = <&switch2phy8>; +- }; +- +- switch2port9: port@9 { +- reg = <0x9>; +- label = "dsa"; +- phy-mode = "2500base-x"; +- managed = "in-band-status"; +- link = <&switch1port10 &switch0port10>; +- }; +- +- port-sfp@a { +- reg = <0xa>; +- label = "sfp"; +- sfp = <&sfp>; +- phy-mode = "sgmii"; +- managed = "in-band-status"; +- status = "disabled"; +- }; +- }; +- }; +- +- switch2@2 { +- compatible = "marvell,mv88e6085"; +- reg = <0x2 0>; +- dsa,member = <0 2>; +- interrupt-parent = <&moxtet>; +- interrupts = ; +- status = "disabled"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch2phy1_topaz: switch2phy1@11 { +- reg = <0x11>; +- }; +- +- switch2phy2_topaz: switch2phy2@12 { +- reg = <0x12>; +- }; +- +- switch2phy3_topaz: switch2phy3@13 { +- reg = <0x13>; +- }; +- +- switch2phy4_topaz: switch2phy4@14 { +- reg = <0x14>; +- }; +- }; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <0x1>; +- label = "lan17"; +- phy-handle = <&switch2phy1_topaz>; +- }; +- +- port@2 { +- reg = <0x2>; +- label = "lan18"; +- phy-handle = <&switch2phy2_topaz>; +- }; +- +- port@3 { +- reg = <0x3>; +- label = "lan19"; +- phy-handle = <&switch2phy3_topaz>; +- }; +- +- port@4 { +- reg = <0x4>; +- label = "lan20"; +- phy-handle = <&switch2phy4_topaz>; +- }; +- +- port@5 { +- reg = <0x5>; +- label = "dsa"; +- phy-mode = "2500base-x"; +- managed = "in-band-status"; +- link = <&switch1port10 &switch0port10>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-uDPU.dts b/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-uDPU.dts +deleted file mode 100644 +index 95d46e8d081c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-uDPU.dts ++++ /dev/null +@@ -1,188 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device tree for the uDPU board. +- * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3) +- * Copyright (C) 2016 Marvell +- * Copyright (C) 2019 Methode Electronics +- * Copyright (C) 2019 Telus +- * +- * Vladimir Vid +- */ +- +-/dts-v1/; +- +-#include +-#include "armada-372x.dtsi" +- +-/ { +- model = "Methode uDPU Board"; +- compatible = "methode,udpu", "marvell,armada3720"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000 0x20000000>; +- }; +- +- leds { +- pinctrl-names = "default"; +- compatible = "gpio-leds"; +- +- power1 { +- label = "udpu:green:power"; +- gpios = <&gpionb 11 GPIO_ACTIVE_LOW>; +- }; +- +- power2 { +- label = "udpu:red:power"; +- gpios = <&gpionb 12 GPIO_ACTIVE_LOW>; +- }; +- +- network1 { +- label = "udpu:green:network"; +- gpios = <&gpionb 13 GPIO_ACTIVE_LOW>; +- }; +- +- network2 { +- label = "udpu:red:network"; +- gpios = <&gpionb 14 GPIO_ACTIVE_LOW>; +- }; +- +- alarm1 { +- label = "udpu:green:alarm"; +- gpios = <&gpionb 15 GPIO_ACTIVE_LOW>; +- }; +- +- alarm2 { +- label = "udpu:red:alarm"; +- gpios = <&gpionb 16 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- sfp_eth0: sfp-eth0 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c0>; +- los-gpio = <&gpiosb 2 GPIO_ACTIVE_HIGH>; +- mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>; +- tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>; +- tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>; +- maximum-power-milliwatt = <3000>; +- }; +- +- sfp_eth1: sfp-eth1 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c1>; +- los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>; +- mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>; +- tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>; +- tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>; +- maximum-power-milliwatt = <3000>; +- }; +-}; +- +-&sdhci0 { +- status = "okay"; +- bus-width = <8>; +- mmc-ddr-1_8v; +- mmc-hs400-1_8v; +- marvell,pad-type = "fixed-1-8v"; +- non-removable; +- no-sd; +- no-sdio; +-}; +- +-&spi0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_quad_pins>; +- +- m25p80@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <54000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- /* only bootloader is located on the SPI */ +- partition@0 { +- label = "uboot"; +- reg = <0 0x400000>; +- }; +- }; +- }; +-}; +- +-&pinctrl_nb { +- i2c1_recovery_pins: i2c1-recovery-pins { +- groups = "i2c1"; +- function = "gpio"; +- }; +- +- i2c2_recovery_pins: i2c2-recovery-pins { +- groups = "i2c2"; +- function = "gpio"; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- pinctrl-names = "default", "recovery"; +- pinctrl-0 = <&i2c1_pins>; +- pinctrl-1 = <&i2c1_recovery_pins>; +- /delete-property/mrvl,i2c-fast-mode; +- scl-gpios = <&gpionb 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpionb 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +-}; +- +-&i2c1 { +- status = "okay"; +- pinctrl-names = "default", "recovery"; +- pinctrl-0 = <&i2c2_pins>; +- pinctrl-1 = <&i2c2_recovery_pins>; +- /delete-property/mrvl,i2c-fast-mode; +- scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +- +- lm75@48 { +- status = "okay"; +- compatible = "lm75"; +- reg = <0x48>; +- }; +- +- lm75@49 { +- status = "okay"; +- compatible = "lm75"; +- reg = <0x49>; +- }; +-}; +- +-ð0 { +- phy-mode = "sgmii"; +- status = "okay"; +- managed = "in-band-status"; +- phys = <&comphy1 0>; +- sfp = <&sfp_eth0>; +-}; +- +-ð1 { +- phy-mode = "sgmii"; +- status = "okay"; +- managed = "in-band-status"; +- phys = <&comphy0 1>; +- sfp = <&sfp_eth1>; +-}; +- +-&usb3 { +- status = "okay"; +- phys = <&usb2_utmi_otg_phy>; +- phy-names = "usb2-utmi-otg-phy"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-372x.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-372x.dtsi +deleted file mode 100644 +index 5ce55bdbb995..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-372x.dtsi ++++ /dev/null +@@ -1,27 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell Armada 372x family of SoCs +- * (also named 88F3720) +- * +- * Copyright (C) 2016 Marvell +- * +- * Gregory CLEMENT +- * +- */ +- +-#include "armada-37xx.dtsi" +- +-/ { +- model = "Marvell Armada 3720 SoC"; +- compatible = "marvell,armada3720", "marvell,armada3710"; +- +- cpus { +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x1>; +- clocks = <&nb_periph_clk 16>; +- enable-method = "psci"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-37xx.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-37xx.dtsi +deleted file mode 100644 +index 0adc194e46d1..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-37xx.dtsi ++++ /dev/null +@@ -1,522 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Include file for Marvell Armada 37xx family of SoCs. +- * +- * Copyright (C) 2016 Marvell +- * +- * Gregory CLEMENT +- * +- */ +- +-#include +- +-/ { +- model = "Marvell Armada 37xx SoC"; +- compatible = "marvell,armada3700"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- /* +- * The PSCI firmware region depicted below is the default one +- * and should be updated by the bootloader. +- */ +- psci-area@4000000 { +- reg = <0 0x4000000 0 0x200000>; +- no-map; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0>; +- clocks = <&nb_periph_clk 16>; +- enable-method = "psci"; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = ; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- internal-regs@d0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- /* 32M internal register @ 0xd000_0000 */ +- ranges = <0x0 0x0 0xd0000000 0x2000000>; +- +- wdt: watchdog@8300 { +- compatible = "marvell,armada-3700-wdt"; +- reg = <0x8300 0x40>; +- marvell,system-controller = <&cpu_misc>; +- clocks = <&xtalclk>; +- }; +- +- cpu_misc: system-controller@d000 { +- compatible = "marvell,armada-3700-cpu-misc", +- "syscon"; +- reg = <0xd000 0x1000>; +- }; +- +- spi0: spi@10600 { +- compatible = "marvell,armada-3700-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x10600 0xA00>; +- clocks = <&nb_periph_clk 7>; +- interrupts = ; +- num-cs = <4>; +- status = "disabled"; +- }; +- +- i2c0: i2c@11000 { +- compatible = "marvell,armada-3700-i2c"; +- reg = <0x11000 0x24>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&nb_periph_clk 10>; +- interrupts = ; +- mrvl,i2c-fast-mode; +- status = "disabled"; +- }; +- +- i2c1: i2c@11080 { +- compatible = "marvell,armada-3700-i2c"; +- reg = <0x11080 0x24>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&nb_periph_clk 9>; +- interrupts = ; +- mrvl,i2c-fast-mode; +- status = "disabled"; +- }; +- +- avs: avs@11500 { +- compatible = "marvell,armada-3700-avs", +- "syscon"; +- reg = <0x11500 0x40>; +- }; +- +- uart0: serial@12000 { +- compatible = "marvell,armada-3700-uart"; +- reg = <0x12000 0x18>; +- clocks = <&xtalclk>; +- interrupts = +- , +- , +- ; +- interrupt-names = "uart-sum", "uart-tx", "uart-rx"; +- status = "disabled"; +- }; +- +- uart1: serial@12200 { +- compatible = "marvell,armada-3700-uart-ext"; +- reg = <0x12200 0x30>; +- clocks = <&xtalclk>; +- interrupts = +- , +- ; +- interrupt-names = "uart-tx", "uart-rx"; +- status = "disabled"; +- }; +- +- nb_periph_clk: nb-periph-clk@13000 { +- compatible = "marvell,armada-3700-periph-clock-nb", +- "syscon"; +- reg = <0x13000 0x100>; +- clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, +- <&tbg 3>, <&xtalclk>; +- #clock-cells = <1>; +- }; +- +- sb_periph_clk: sb-periph-clk@18000 { +- compatible = "marvell,armada-3700-periph-clock-sb"; +- reg = <0x18000 0x100>; +- clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, +- <&tbg 3>, <&xtalclk>; +- #clock-cells = <1>; +- }; +- +- tbg: tbg@13200 { +- compatible = "marvell,armada-3700-tbg-clock"; +- reg = <0x13200 0x100>; +- clocks = <&xtalclk>; +- #clock-cells = <1>; +- }; +- +- pinctrl_nb: pinctrl@13800 { +- compatible = "marvell,armada3710-nb-pinctrl", +- "syscon", "simple-mfd"; +- reg = <0x13800 0x100>, <0x13C00 0x20>; +- /* MPP1[19:0] */ +- gpionb: gpio { +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl_nb 0 0 36>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- }; +- +- xtalclk: xtal-clk { +- compatible = "marvell,armada-3700-xtal-clock"; +- clock-output-names = "xtal"; +- #clock-cells = <0>; +- }; +- +- spi_quad_pins: spi-quad-pins { +- groups = "spi_quad"; +- function = "spi"; +- }; +- +- spi_cs1_pins: spi-cs1-pins { +- groups = "spi_cs1"; +- function = "spi"; +- }; +- +- i2c1_pins: i2c1-pins { +- groups = "i2c1"; +- function = "i2c"; +- }; +- +- i2c2_pins: i2c2-pins { +- groups = "i2c2"; +- function = "i2c"; +- }; +- +- uart1_pins: uart1-pins { +- groups = "uart1"; +- function = "uart"; +- }; +- +- uart2_pins: uart2-pins { +- groups = "uart2"; +- function = "uart"; +- }; +- +- mmc_pins: mmc-pins { +- groups = "emmc_nb"; +- function = "emmc"; +- }; +- }; +- +- nb_pm: syscon@14000 { +- compatible = "marvell,armada-3700-nb-pm", +- "syscon"; +- reg = <0x14000 0x60>; +- }; +- +- comphy: phy@18300 { +- compatible = "marvell,comphy-a3700"; +- reg = <0x18300 0x300>, +- <0x1F000 0x400>, +- <0x5C000 0x400>, +- <0xe0178 0x8>; +- reg-names = "comphy", +- "lane1_pcie_gbe", +- "lane0_usb3_gbe", +- "lane2_sata_usb3"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- comphy0: phy@0 { +- reg = <0>; +- #phy-cells = <1>; +- }; +- +- comphy1: phy@1 { +- reg = <1>; +- #phy-cells = <1>; +- }; +- +- comphy2: phy@2 { +- reg = <2>; +- #phy-cells = <1>; +- }; +- }; +- +- pinctrl_sb: pinctrl@18800 { +- compatible = "marvell,armada3710-sb-pinctrl", +- "syscon", "simple-mfd"; +- reg = <0x18800 0x100>, <0x18C00 0x20>; +- /* MPP2[23:0] */ +- gpiosb: gpio { +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl_sb 0 0 30>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = +- , +- , +- , +- , +- ; +- }; +- +- rgmii_pins: mii-pins { +- groups = "rgmii"; +- function = "mii"; +- }; +- +- smi_pins: smi-pins { +- groups = "smi"; +- function = "smi"; +- }; +- +- sdio_pins: sdio-pins { +- groups = "sdio_sb"; +- function = "sdio"; +- }; +- +- pcie_reset_pins: pcie-reset-pins { +- groups = "pcie1"; /* this actually controls "pcie1_reset" */ +- function = "gpio"; +- }; +- +- pcie_clkreq_pins: pcie-clkreq-pins { +- groups = "pcie1_clkreq"; +- function = "pcie"; +- }; +- }; +- +- eth0: ethernet@30000 { +- compatible = "marvell,armada-3700-neta"; +- reg = <0x30000 0x4000>; +- interrupts = ; +- clocks = <&sb_periph_clk 8>; +- status = "disabled"; +- }; +- +- mdio: mdio@32004 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "marvell,orion-mdio"; +- reg = <0x32004 0x4>; +- }; +- +- eth1: ethernet@40000 { +- compatible = "marvell,armada-3700-neta"; +- reg = <0x40000 0x4000>; +- interrupts = ; +- clocks = <&sb_periph_clk 7>; +- status = "disabled"; +- }; +- +- usb3: usb@58000 { +- compatible = "marvell,armada3700-xhci", +- "generic-xhci"; +- reg = <0x58000 0x4000>; +- marvell,usb-misc-reg = <&usb32_syscon>; +- interrupts = ; +- clocks = <&sb_periph_clk 12>; +- phys = <&comphy0 0>, <&usb2_utmi_otg_phy>; +- phy-names = "usb3-phy", "usb2-utmi-otg-phy"; +- status = "disabled"; +- }; +- +- usb2_utmi_otg_phy: phy@5d000 { +- compatible = "marvell,a3700-utmi-otg-phy"; +- reg = <0x5d000 0x800>; +- marvell,usb-misc-reg = <&usb32_syscon>; +- #phy-cells = <0>; +- }; +- +- usb32_syscon: system-controller@5d800 { +- compatible = "marvell,armada-3700-usb2-host-device-misc", +- "syscon"; +- reg = <0x5d800 0x800>; +- }; +- +- usb2: usb@5e000 { +- compatible = "marvell,armada-3700-ehci"; +- reg = <0x5e000 0x1000>; +- marvell,usb-misc-reg = <&usb2_syscon>; +- interrupts = ; +- phys = <&usb2_utmi_host_phy>; +- phy-names = "usb2-utmi-host-phy"; +- status = "disabled"; +- }; +- +- usb2_utmi_host_phy: phy@5f000 { +- compatible = "marvell,a3700-utmi-host-phy"; +- reg = <0x5f000 0x800>; +- marvell,usb-misc-reg = <&usb2_syscon>; +- #phy-cells = <0>; +- }; +- +- usb2_syscon: system-controller@5f800 { +- compatible = "marvell,armada-3700-usb2-host-misc", +- "syscon"; +- reg = <0x5f800 0x800>; +- }; +- +- xor@60900 { +- compatible = "marvell,armada-3700-xor"; +- reg = <0x60900 0x100>, +- <0x60b00 0x100>; +- +- xor10 { +- interrupts = ; +- }; +- xor11 { +- interrupts = ; +- }; +- }; +- +- crypto: crypto@90000 { +- compatible = "inside-secure,safexcel-eip97ies"; +- reg = <0x90000 0x20000>; +- interrupts = , +- , +- , +- , +- , +- ; +- interrupt-names = "mem", "ring0", "ring1", +- "ring2", "ring3", "eip"; +- clocks = <&nb_periph_clk 15>; +- }; +- +- rwtm: mailbox@b0000 { +- compatible = "marvell,armada-3700-rwtm-mailbox"; +- reg = <0xb0000 0x100>; +- interrupts = ; +- #mbox-cells = <1>; +- }; +- +- sdhci1: sdhci@d0000 { +- compatible = "marvell,armada-3700-sdhci", +- "marvell,sdhci-xenon"; +- reg = <0xd0000 0x300>, +- <0x1e808 0x4>; +- interrupts = ; +- clocks = <&nb_periph_clk 0>; +- clock-names = "core"; +- status = "disabled"; +- }; +- +- sdhci0: sdhci@d8000 { +- compatible = "marvell,armada-3700-sdhci", +- "marvell,sdhci-xenon"; +- reg = <0xd8000 0x300>, +- <0x17808 0x4>; +- interrupts = ; +- clocks = <&nb_periph_clk 0>; +- clock-names = "core"; +- status = "disabled"; +- }; +- +- sata: sata@e0000 { +- compatible = "marvell,armada-3700-ahci"; +- reg = <0xe0000 0x178>; +- interrupts = ; +- clocks = <&nb_periph_clk 1>; +- phys = <&comphy2 0>; +- phy-names = "sata-phy"; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@1d00000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x1d00000 0x10000>, /* GICD */ +- <0x1d40000 0x40000>, /* GICR */ +- <0x1d80000 0x2000>, /* GICC */ +- <0x1d90000 0x2000>, /* GICH */ +- <0x1da0000 0x20000>; /* GICV */ +- interrupts = ; +- }; +- }; +- +- pcie0: pcie@d0070000 { +- compatible = "marvell,armada-3700-pcie"; +- device_type = "pci"; +- status = "disabled"; +- reg = <0 0xd0070000 0 0x20000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- interrupts = ; +- #interrupt-cells = <1>; +- msi-parent = <&pcie0>; +- msi-controller; +- /* +- * The 128 MiB address range [0xe8000000-0xf0000000] is +- * dedicated for PCIe and can be assigned to 8 windows +- * with size a power of two. Use one 64 KiB window for +- * IO at the end and the remaining seven windows +- * (totaling 127 MiB) for MEM. +- */ +- ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */ +- 0x81000000 0 0x00000000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */ +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie_intc 0>, +- <0 0 0 2 &pcie_intc 1>, +- <0 0 0 3 &pcie_intc 2>, +- <0 0 0 4 &pcie_intc 3>; +- max-link-speed = <2>; +- phys = <&comphy1 0>; +- pcie_intc: interrupt-controller { +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- }; +- }; +- +- firmware { +- armada-3700-rwtm { +- compatible = "marvell,armada-3700-rwtm-firmware"; +- mboxes = <&rwtm 0>; +- status = "okay"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-7020.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-7020.dtsi +deleted file mode 100644 +index 4e46326dd123..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-7020.dtsi ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2016 Marvell Technology Group Ltd. +- * +- * Device Tree file for the Armada 7020 SoC, made of an AP806 Dual and +- * one CP110. +- */ +- +-#include "armada-ap806-dual.dtsi" +-#include "armada-70x0.dtsi" +- +-/ { +- model = "Marvell Armada 7020"; +- compatible = "marvell,armada7020", "marvell,armada-ap806-dual", +- "marvell,armada-ap806"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-7040-db.dts b/scripts/dtc/include-prefixes/arm64/marvell/armada-7040-db.dts +deleted file mode 100644 +index cd326fe224ce..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-7040-db.dts ++++ /dev/null +@@ -1,308 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2016 Marvell Technology Group Ltd. +- * +- * Device Tree file for Marvell Armada 7040 Development board platform +- */ +- +-#include +-#include "armada-7040.dtsi" +- +-/ { +- model = "Marvell Armada 7040 DB board"; +- compatible = "marvell,armada7040-db", "marvell,armada7040", +- "marvell,armada-ap806-quad", "marvell,armada-ap806"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- aliases { +- ethernet0 = &cp0_eth0; +- ethernet1 = &cp0_eth1; +- ethernet2 = &cp0_eth2; +- }; +- +- cp0_exp_usb3_0_current_regulator: gpio-regulator { +- compatible = "regulator-gpio"; +- regulator-name = "cp0-usb3-0-current-regulator"; +- regulator-type = "current"; +- regulator-min-microamp = <500000>; +- regulator-max-microamp = <900000>; +- gpios = <&expander0 4 GPIO_ACTIVE_HIGH>; +- states = <500000 0x0 +- 900000 0x1>; +- enable-active-high; +- gpios-states = <0>; +- }; +- +- cp0_exp_usb3_1_current_regulator: gpio-regulator { +- compatible = "regulator-gpio"; +- regulator-name = "cp0-usb3-1-current-regulator"; +- regulator-type = "current"; +- regulator-min-microamp = <500000>; +- regulator-max-microamp = <900000>; +- gpios = <&expander0 5 GPIO_ACTIVE_HIGH>; +- states = <500000 0x0 +- 900000 0x1>; +- enable-active-high; +- gpios-states = <0>; +- }; +- +- cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb3h0-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; +- vin-supply = <&cp0_exp_usb3_0_current_regulator>; +- }; +- +- cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb3h1-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; +- vin-supply = <&cp0_exp_usb3_1_current_regulator>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <10000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0 0x200000>; +- }; +- partition@400000 { +- label = "Filesystem"; +- reg = <0x200000 0xce0000>; +- }; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +- pinctrl-0 = <&uart0_pins>; +- pinctrl-names = "default"; +-}; +- +- +-&cp0_pcie2 { +- status = "okay"; +- phys = <&cp0_comphy5 2>; +- phy-names = "cp0-pcie2-x1-phy"; +-}; +- +-&cp0_i2c0 { +- status = "okay"; +- clock-frequency = <100000>; +- +- expander0: pca9555@21 { +- compatible = "nxp,pca9555"; +- pinctrl-names = "default"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x21>; +- /* +- * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect +- * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit +- * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN +- * IO0_3: USB2_DEVICE_DETECT +- * IO0_4: GPIO_0 IO1_4: SD_Status +- * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable +- * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC +- * IO0_7: IO1_7: SDIO_Vcntrl +- */ +- }; +-}; +- +-&cp0_nand_controller { +- /* +- * SPI on CPM and NAND have common pins on this board. We can +- * use only one at a time. To enable the NAND (which will +- * disable the SPI), the "status = "okay";" line have to be +- * added here. +- */ +- pinctrl-0 = <&nand_pins>, <&nand_rb>; +- pinctrl-names = "default"; +- +- nand@0 { +- reg = <0>; +- label = "pxa3xx_nand-0"; +- nand-rb = <0>; +- nand-on-flash-bbt; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0 0x200000>; +- }; +- +- partition@200000 { +- label = "Linux"; +- reg = <0x200000 0xe00000>; +- }; +- +- partition@1000000 { +- label = "Filesystem"; +- reg = <0x1000000 0x3f000000>; +- }; +- +- }; +- }; +-}; +- +-&cp0_spi1 { +- status = "okay"; +- +- spi-flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0x0>; +- spi-max-frequency = <20000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0x0 0x200000>; +- }; +- +- partition@400000 { +- label = "Filesystem"; +- reg = <0x200000 0xe00000>; +- }; +- }; +- }; +-}; +- +-&cp0_sata0 { +- status = "okay"; +- +- sata-port@1 { +- phys = <&cp0_comphy3 1>; +- phy-names = "cp0-sata0-1-phy"; +- }; +-}; +- +-&cp0_utmi { +- status = "okay"; +-}; +- +-&cp0_comphy1 { +- cp0_usbh0_con: connector { +- compatible = "usb-a-connector"; +- phy-supply = <&cp0_reg_usb3_0_vbus>; +- }; +-}; +- +-&cp0_usb3_0 { +- phys = <&cp0_comphy1 0>, <&cp0_utmi0>; +- phy-names = "cp0-usb3h0-comphy", "utmi"; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&cp0_comphy4 { +- cp0_usbh1_con: connector { +- compatible = "usb-a-connector"; +- phy-supply = <&cp0_reg_usb3_1_vbus>; +- }; +-}; +- +-&cp0_usb3_1 { +- phys = <&cp0_comphy4 1>, <&cp0_utmi1>; +- phy-names = "cp0-usb3h1-comphy", "utmi"; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&ap_sdhci0 { +- status = "okay"; +- bus-width = <4>; +- no-1-8-v; +- non-removable; +-}; +- +-&cp0_sdhci0 { +- status = "okay"; +- bus-width = <4>; +- no-1-8-v; +- cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>; +-}; +- +-&cp0_mdio { +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&cp0_ethernet { +- status = "okay"; +-}; +- +-&cp0_eth0 { +- status = "okay"; +- /* Network PHY */ +- phy-mode = "10gbase-r"; +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp0_comphy2 0>; +- +- fixed-link { +- speed = <10000>; +- full-duplex; +- }; +-}; +- +-&cp0_eth1 { +- status = "okay"; +- /* Network PHY */ +- phy = <&phy0>; +- phy-mode = "sgmii"; +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp0_comphy0 1>; +-}; +- +-&cp0_eth2 { +- status = "okay"; +- phy = <&phy1>; +- phy-mode = "rgmii-id"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-7040.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-7040.dtsi +deleted file mode 100644 +index 2f440711d21d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-7040.dtsi ++++ /dev/null +@@ -1,40 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2016 Marvell Technology Group Ltd. +- * +- * Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and +- * one CP110. +- */ +- +-#include "armada-ap806-quad.dtsi" +-#include "armada-70x0.dtsi" +- +-/ { +- model = "Marvell Armada 7040"; +- compatible = "marvell,armada7040", "marvell,armada-ap806-quad", +- "marvell,armada-ap806"; +-}; +- +-&cp0_pcie0 { +- iommu-map = +- <0x0 &smmu 0x480 0x20>, +- <0x100 &smmu 0x4a0 0x20>, +- <0x200 &smmu 0x4c0 0x20>; +- iommu-map-mask = <0x031f>; +-}; +- +-&cp0_sata0 { +- iommus = <&smmu 0x444>; +-}; +- +-&cp0_sdhci0 { +- iommus = <&smmu 0x445>; +-}; +- +-&cp0_usb3_0 { +- iommus = <&smmu 0x440>; +-}; +- +-&cp0_usb3_1 { +- iommus = <&smmu 0x441>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-70x0.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-70x0.dtsi +deleted file mode 100644 +index 293403a1a333..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-70x0.dtsi ++++ /dev/null +@@ -1,64 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2017 Marvell Technology Group Ltd. +- * +- * Device Tree file for the Armada 70x0 SoC +- */ +- +-/ { +- aliases { +- gpio1 = &cp0_gpio1; +- gpio2 = &cp0_gpio2; +- spi1 = &cp0_spi0; +- spi2 = &cp0_spi1; +- }; +-}; +- +-/* +- * Instantiate the CP110 +- */ +-#define CP11X_NAME cp0 +-#define CP11X_BASE f2000000 +-#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000)) +-#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 +-#define CP11X_PCIE0_BASE f2600000 +-#define CP11X_PCIE1_BASE f2620000 +-#define CP11X_PCIE2_BASE f2640000 +- +-#include "armada-cp110.dtsi" +- +-#undef CP11X_NAME +-#undef CP11X_BASE +-#undef CP11X_PCIEx_MEM_BASE +-#undef CP11X_PCIEx_MEM_SIZE +-#undef CP11X_PCIE0_BASE +-#undef CP11X_PCIE1_BASE +-#undef CP11X_PCIE2_BASE +- +-&cp0_gpio1 { +- status = "okay"; +-}; +- +-&cp0_gpio2 { +- status = "okay"; +-}; +- +-&cp0_syscon0 { +- cp0_pinctrl: pinctrl { +- compatible = "marvell,armada-7k-pinctrl"; +- +- nand_pins: nand-pins { +- marvell,pins = +- "mpp15", "mpp16", "mpp17", "mpp18", +- "mpp19", "mpp20", "mpp21", "mpp22", +- "mpp23", "mpp24", "mpp25", "mpp26", +- "mpp27"; +- marvell,function = "dev"; +- }; +- +- nand_rb: nand-rb { +- marvell,pins = "mpp13"; +- marvell,function = "nf"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-8020.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-8020.dtsi +deleted file mode 100644 +index ba1307c0fadb..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-8020.dtsi ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2016 Marvell Technology Group Ltd. +- * +- * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and +- * two CP110. +- */ +- +-#include "armada-ap806-dual.dtsi" +-#include "armada-80x0.dtsi" +- +-/ { +- model = "Marvell Armada 8020"; +- compatible = "marvell,armada8020", "marvell,armada-ap806-dual", +- "marvell,armada-ap806"; +-}; +- +-/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock +- * in CP master is not connected (by package) to the oscillator. So +- * disable it. However, the RTC clock in CP slave is connected to the +- * oscillator so this one is let enabled. +- */ +- +-&cp0_rtc { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-clearfog-gt-8k.dts b/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-clearfog-gt-8k.dts +deleted file mode 100644 +index 8729c6467303..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-clearfog-gt-8k.dts ++++ /dev/null +@@ -1,610 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2018 SolidRun ltd. +- * Based on Marvell MACCHIATOBin board +- * +- * Device Tree file for SolidRun's ClearFog GT 8K +- */ +- +-#include "armada-8040.dtsi" +- +-#include +-#include +- +-/ { +- model = "SolidRun ClearFog GT 8K"; +- compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040", +- "marvell,armada-ap806-quad", "marvell,armada-ap806"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- aliases { +- ethernet0 = &cp1_eth1; +- ethernet1 = &cp0_eth0; +- ethernet2 = &cp1_eth2; +- }; +- +- fan: pwm { +- compatible = "pwm-fan"; +- /* 20% steps */ +- cooling-levels = <0 51 102 153 204 255>; +- #cooling-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_fan_pwm_pins>; +- pwms = <&cp0_gpio2 16 40000>; +- }; +- +- v_3_3: regulator-3-3v { +- compatible = "regulator-fixed"; +- regulator-name = "v_3_3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- status = "okay"; +- }; +- +- v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { +- compatible = "regulator-fixed"; +- gpio = <&cp0_gpio2 15 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_xhci_vbus_pins>; +- regulator-name = "v_5v0_usb3_hst_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- status = "okay"; +- }; +- +- sfp_cp0_eth0: sfp-cp0-eth0 { +- compatible = "sff,sfp"; +- i2c-bus = <&cp0_i2c1>; +- mod-def0-gpio = <&cp0_gpio2 17 GPIO_ACTIVE_LOW>; +- tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_sfp_present_pins &cp1_sfp_tx_disable_pins>; +- maximum-power-milliwatt = <2000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&cp0_led0_pins +- &cp0_led1_pins>; +- pinctrl-names = "default"; +- /* No designated function for these LEDs at the moment */ +- led0 { +- label = "clearfog-gt-8k:green:led0"; +- gpios = <&cp0_gpio2 8 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- led1 { +- label = "clearfog-gt-8k:green:led1"; +- gpios = <&cp0_gpio2 9 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- }; +- +- keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&cp0_gpio_reset_pins &cp1_wps_button_pins>; +- pinctrl-names = "default"; +- +- button_0 { +- /* The rear button */ +- label = "Rear Button"; +- gpios = <&cp0_gpio2 7 GPIO_ACTIVE_LOW>; +- linux,can-disable; +- linux,code = ; +- }; +- +- button_1 { +- /* The wps button */ +- label = "WPS Button"; +- gpios = <&cp1_gpio1 30 GPIO_ACTIVE_LOW>; +- linux,can-disable; +- linux,code = ; +- }; +- }; +-}; +- +-&ap_thermal_ic { +- polling-delay = <1000>; /* milliseconds */ +- trips { +- ap_active: trip-active { +- temperature = <40000>; /* millicelsius */ +- hysteresis = <4000>; /* millicelsius */ +- type = "active"; +- }; +- }; +- cooling-maps { +- map0 { +- trip = <&ap_active>; +- cooling-device = <&fan THERMAL_NO_LIMIT 4>; +- }; +- map1 { +- trip = <&ap_crit>; +- cooling-device = <&fan 4 5>; +- }; +- }; +-}; +- +-&cp0_thermal_ic { +- polling-delay = <1000>; /* milliseconds */ +- trips { +- cp0_active0: trip-active0 { +- temperature = <40000>; /* millicelsius */ +- hysteresis = <2500>; /* millicelsius */ +- type = "active"; +- }; +- cp0_active1: trip-active1 { +- temperature = <45000>; /* millicelsius */ +- hysteresis = <2500>; /* millicelsius */ +- type = "active"; +- }; +- cp0_active2: trip-active2 { +- temperature = <50000>; /* millicelsius */ +- hysteresis = <2500>; /* millicelsius */ +- type = "active"; +- }; +- cp0_active3: trip-active3 { +- temperature = <60000>; /* millicelsius */ +- hysteresis = <2500>; /* millicelsius */ +- type = "active"; +- }; +- }; +- cooling-maps { +- map0 { +- trip = <&cp0_active0>; +- cooling-device = <&fan 0 1>; +- }; +- map1 { +- trip = <&cp0_active1>; +- cooling-device = <&fan 1 2>; +- }; +- map2 { +- trip = <&cp0_active2>; +- cooling-device = <&fan 2 3>; +- }; +- map3 { +- trip = <&cp0_active3>; +- cooling-device = <&fan 3 4>; +- }; +- map4 { +- trip = <&cp0_crit>; +- cooling-device = <&fan 4 5>; +- }; +- }; +-}; +- +-&cp1_thermal_ic { +- polling-delay = <1000>; /* milliseconds */ +- trips { +- cp1_active0: trip-active0 { +- temperature = <40000>; /* millicelsius */ +- hysteresis = <2500>; /* millicelsius */ +- type = "active"; +- }; +- cp1_active1: trip-active1 { +- temperature = <45000>; /* millicelsius */ +- hysteresis = <2500>; /* millicelsius */ +- type = "active"; +- }; +- cp1_active2: trip-active2 { +- temperature = <50000>; /* millicelsius */ +- hysteresis = <2500>; /* millicelsius */ +- type = "active"; +- }; +- cp1_active3: trip-active3 { +- temperature = <60000>; /* millicelsius */ +- hysteresis = <2500>; /* millicelsius */ +- type = "active"; +- }; +- }; +- cooling-maps { +- map0 { +- trip = <&cp1_active0>; +- cooling-device = <&fan 0 1>; +- }; +- map1 { +- trip = <&cp1_active1>; +- cooling-device = <&fan 1 2>; +- }; +- map2 { +- trip = <&cp1_active2>; +- cooling-device = <&fan 2 3>; +- }; +- map3 { +- trip = <&cp1_active3>; +- cooling-device = <&fan 3 4>; +- }; +- map4 { +- trip = <&cp1_crit>; +- cooling-device = <&fan 4 5>; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +- pinctrl-0 = <&uart0_pins>; +- pinctrl-names = "default"; +-}; +- +-&ap_sdhci0 { +- bus-width = <8>; +- no-1-8-v; +- no-sd; +- no-sdio; +- non-removable; +- status = "okay"; +- vqmmc-supply = <&v_3_3>; +-}; +- +-&cp0_i2c0 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_i2c0_pins>; +- status = "okay"; +-}; +- +-&cp0_i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_i2c1_pins>; +- status = "okay"; +-}; +- +-&cp0_pinctrl { +- /* +- * MPP Bus: +- * [0-31] = 0xff: Keep default CP0_shared_pins: +- * [11] CLKOUT_MPP_11 (out) +- * [23] LINK_RD_IN_CP2CP (in) +- * [25] CLKOUT_MPP_25 (out) +- * [29] AVS_FB_IN_CP2CP (in) +- * [32, 33, 34] pci0/1/2 reset +- * [35-38] CP0 I2C1 and I2C0 +- * [39] GPIO reset button +- * [40,41] LED0 and LED1 +- * [43] 1512 phy reset +- * [47] USB VBUS EN (active low) +- * [48] FAN PWM +- * [49] SFP+ present signal +- * [50] TPM interrupt +- * [51] WLAN0 disable +- * [52] WLAN1 disable +- * [53] LTE disable +- * [54] NFC reset +- * [55] Micro SD card detect +- * [56-61] Micro SD +- */ +- +- cp0_pci0_reset_pins: pci0-reset-pins { +- marvell,pins = "mpp32"; +- marvell,function = "gpio"; +- }; +- +- cp0_pci1_reset_pins: pci1-reset-pins { +- marvell,pins = "mpp33"; +- marvell,function = "gpio"; +- }; +- +- cp0_pci2_reset_pins: pci2-reset-pins { +- marvell,pins = "mpp34"; +- marvell,function = "gpio"; +- }; +- +- cp0_i2c1_pins: i2c1-pins { +- marvell,pins = "mpp35", "mpp36"; +- marvell,function = "i2c1"; +- }; +- +- cp0_i2c0_pins: i2c0-pins { +- marvell,pins = "mpp37", "mpp38"; +- marvell,function = "i2c0"; +- }; +- +- cp0_gpio_reset_pins: gpio-reset-pins { +- marvell,pins = "mpp39"; +- marvell,function = "gpio"; +- }; +- +- cp0_led0_pins: led0-pins { +- marvell,pins = "mpp40"; +- marvell,function = "gpio"; +- }; +- +- cp0_led1_pins: led1-pins { +- marvell,pins = "mpp41"; +- marvell,function = "gpio"; +- }; +- +- cp0_copper_eth_phy_reset: copper-eth-phy-reset { +- marvell,pins = "mpp43"; +- marvell,function = "gpio"; +- }; +- +- cp0_xhci_vbus_pins: xhci0-vbus-pins { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- +- cp0_fan_pwm_pins: fan-pwm-pins { +- marvell,pins = "mpp48"; +- marvell,function = "gpio"; +- }; +- +- cp0_sfp_present_pins: sfp-present-pins { +- marvell,pins = "mpp49"; +- marvell,function = "gpio"; +- }; +- +- cp0_tpm_irq_pins: tpm-irq-pins { +- marvell,pins = "mpp50"; +- marvell,function = "gpio"; +- }; +- +- cp0_wlan_disable_pins: wlan-disable-pins { +- marvell,pins = "mpp51"; +- marvell,function = "gpio"; +- }; +- +- cp0_sdhci_pins: sdhci-pins { +- marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59", +- "mpp60", "mpp61"; +- marvell,function = "sdio"; +- }; +-}; +- +-&cp0_pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_pci0_reset_pins &cp0_wlan_disable_pins>; +- reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>; +- phys = <&cp0_comphy0 0>; +- phy-names = "cp0-pcie0-x1-phy"; +- status = "okay"; +-}; +- +-&cp0_gpio2 { +- sata_reset { +- gpio-hog; +- gpios = <1 GPIO_ACTIVE_HIGH>; +- output-high; +- }; +- +- lte_reset { +- gpio-hog; +- gpios = <2 GPIO_ACTIVE_LOW>; +- output-low; +- }; +- +- wlan_disable { +- gpio-hog; +- gpios = <19 GPIO_ACTIVE_LOW>; +- output-low; +- }; +- +- lte_disable { +- gpio-hog; +- gpios = <21 GPIO_ACTIVE_LOW>; +- output-low; +- }; +-}; +- +-&cp0_ethernet { +- status = "okay"; +-}; +- +-/* SFP */ +-&cp0_eth0 { +- status = "okay"; +- phy-mode = "10gbase-r"; +- managed = "in-band-status"; +- phys = <&cp0_comphy2 0>; +- sfp = <&sfp_cp0_eth0>; +-}; +- +-&cp0_sdhci0 { +- broken-cd; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_sdhci_pins>; +- status = "okay"; +- vqmmc-supply = <&v_3_3>; +-}; +- +-&cp0_usb3_1 { +- status = "okay"; +-}; +- +-&cp1_pinctrl { +- /* +- * MPP Bus: +- * [0-5] TDM +- * [6] VHV Enable +- * [7] CP1 SPI0 CSn1 (FXS) +- * [8] CP1 SPI0 CSn0 (TPM) +- * [9.11]CP1 SPI0 MOSI/MISO/CLK +- * [13] CP1 SPI1 MISO (TDM and SPI ROM shared) +- * [14] CP1 SPI1 CS0n (64Mb SPI ROM) +- * [15] CP1 SPI1 MOSI (TDM and SPI ROM shared) +- * [16] CP1 SPI1 CLK (TDM and SPI ROM shared) +- * [24] Topaz switch reset +- * [26] Buzzer +- * [27] CP1 SMI MDIO +- * [28] CP1 SMI MDC +- * [29] CP0 10G SFP TX Disable +- * [30] WPS button +- * [31] Front panel button +- */ +- +- cp1_spi1_pins: spi1-pins { +- marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; +- marvell,function = "spi1"; +- }; +- +- cp1_switch_reset_pins: switch-reset-pins { +- marvell,pins = "mpp24"; +- marvell,function = "gpio"; +- }; +- +- cp1_ge_mdio_pins: ge-mdio-pins { +- marvell,pins = "mpp27", "mpp28"; +- marvell,function = "ge"; +- }; +- +- cp1_sfp_tx_disable_pins: sfp-tx-disable-pins { +- marvell,pins = "mpp29"; +- marvell,function = "gpio"; +- }; +- +- cp1_wps_button_pins: wps-button-pins { +- marvell,pins = "mpp30"; +- marvell,function = "gpio"; +- }; +-}; +- +-&cp1_sata0 { +- pinctrl-0 = <&cp0_pci1_reset_pins>; +- status = "okay"; +- +- sata-port@1 { +- phys = <&cp1_comphy0 1>; +- phy-names = "cp1-sata0-1-phy"; +- }; +-}; +- +-&cp1_mdio { +- pinctrl-names = "default"; +- pinctrl-0 = <&cp1_ge_mdio_pins>; +- status = "okay"; +- +- ge_phy: ethernet-phy@0 { +- /* LED0 - GB link +- * LED1 - on: link, blink: activity +- */ +- marvell,reg-init = <3 16 0 0x1017>; +- reg = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_copper_eth_phy_reset>; +- reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>; +- reset-assert-us = <10000>; +- reset-deassert-us = <10000>; +- }; +- +- switch0: switch0@4 { +- compatible = "marvell,mv88e6085"; +- reg = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp1_switch_reset_pins>; +- reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <1>; +- label = "lan2"; +- phy-handle = <&switch0phy0>; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan1"; +- phy-handle = <&switch0phy1>; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan4"; +- phy-handle = <&switch0phy2>; +- }; +- +- port@4 { +- reg = <4>; +- label = "lan3"; +- phy-handle = <&switch0phy3>; +- }; +- +- port@5 { +- reg = <5>; +- label = "cpu"; +- ethernet = <&cp1_eth2>; +- phy-mode = "2500base-x"; +- managed = "in-band-status"; +- }; +- }; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch0phy0: switch0phy0@11 { +- reg = <0x11>; +- }; +- +- switch0phy1: switch0phy1@12 { +- reg = <0x12>; +- }; +- +- switch0phy2: switch0phy2@13 { +- reg = <0x13>; +- }; +- +- switch0phy3: switch0phy3@14 { +- reg = <0x14>; +- }; +- }; +- }; +-}; +- +-&cp1_ethernet { +- status = "okay"; +-}; +- +-/* 1G copper */ +-&cp1_eth1 { +- status = "okay"; +- phy-mode = "sgmii"; +- phy = <&ge_phy>; +- phys = <&cp1_comphy3 1>; +-}; +- +-/* Switch uplink */ +-&cp1_eth2 { +- status = "okay"; +- phy-mode = "2500base-x"; +- phys = <&cp1_comphy5 2>; +- managed = "in-band-status"; +-}; +- +-&cp1_spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&cp1_spi1_pins>; +- status = "okay"; +- +- spi-flash@0 { +- compatible = "st,w25q32"; +- spi-max-frequency = <50000000>; +- reg = <0>; +- }; +-}; +- +-&cp1_comphy2 { +- cp1_usbh0_con: connector { +- compatible = "usb-a-connector"; +- phy-supply = <&v_5v0_usb3_hst_vbus>; +- }; +-}; +- +-&cp1_usb3_0 { +- phys = <&cp1_comphy2 0>; +- phy-names = "cp1-usb3h0-comphy"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-db.dts b/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-db.dts +deleted file mode 100644 +index f2e8e0df8865..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-db.dts ++++ /dev/null +@@ -1,375 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2016 Marvell Technology Group Ltd. +- * +- * Device Tree file for Marvell Armada 8040 Development board platform +- */ +- +-#include +-#include "armada-8040.dtsi" +- +-/ { +- model = "Marvell Armada 8040 DB board"; +- compatible = "marvell,armada8040-db", "marvell,armada8040", +- "marvell,armada-ap806-quad", "marvell,armada-ap806"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- aliases { +- ethernet0 = &cp0_eth0; +- ethernet1 = &cp0_eth2; +- ethernet2 = &cp1_eth0; +- ethernet3 = &cp1_eth1; +- i2c1 = &cp0_i2c0; +- i2c2 = &cp1_i2c0; +- }; +- +- cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "cp0-usb3h0-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; +- }; +- +- cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "cp0-usb3h1-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; +- }; +- +- cp0_usb3_0_phy: cp0-usb3-0-phy { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <&cp0_reg_usb3_0_vbus>; +- }; +- +- cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "cp1-usb3h0-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&expander1 0 GPIO_ACTIVE_HIGH>; +- }; +- +- cp1_usb3_0_phy: cp1-usb3-0-phy { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <&cp1_reg_usb3_0_vbus>; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- +- spi-flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <10000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0 0x200000>; +- }; +- partition@400000 { +- label = "Filesystem"; +- reg = <0x200000 0xce0000>; +- }; +- }; +- }; +-}; +- +-/* Accessible over the mini-USB CON9 connector on the main board */ +-&uart0 { +- status = "okay"; +- pinctrl-0 = <&uart0_pins>; +- pinctrl-names = "default"; +-}; +- +-/* CON6 on CP0 expansion */ +-&cp0_pcie0 { +- phys = <&cp0_comphy0 0>; +- phy-names = "cp0-pcie0-x1-phy"; +- status = "okay"; +-}; +- +-/* CON5 on CP0 expansion */ +-&cp0_pcie2 { +- phys = <&cp0_comphy5 2>; +- phy-names = "cp0-pcie2-x1-phy"; +- status = "okay"; +-}; +- +-&cp0_i2c0 { +- status = "okay"; +- clock-frequency = <100000>; +- +- /* U31 */ +- expander0: pca9555@21 { +- compatible = "nxp,pca9555"; +- pinctrl-names = "default"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x21>; +- }; +- +- /* U25 */ +- expander1: pca9555@25 { +- compatible = "nxp,pca9555"; +- pinctrl-names = "default"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x25>; +- }; +- +-}; +- +-/* CON4 on CP0 expansion */ +-&cp0_sata0 { +- status = "okay"; +- +- sata-port@0 { +- phys = <&cp0_comphy1 0>; +- phy-names = "cp0-sata0-0-phy"; +- }; +- sata-port@1 { +- phys = <&cp0_comphy3 1>; +- phy-names = "cp0-sata0-1-phy"; +- }; +-}; +- +-/* CON9 on CP0 expansion */ +-&cp0_utmi { +- status = "okay"; +-}; +- +-&cp0_usb3_0 { +- usb-phy = <&cp0_usb3_0_phy>; +- phys = <&cp0_utmi0>; +- phy-names = "utmi"; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&cp0_comphy4 { +- cp0_usbh1_con: connector { +- compatible = "usb-a-connector"; +- phy-supply = <&cp0_reg_usb3_1_vbus>; +- }; +-}; +- +-/* CON10 on CP0 expansion */ +-&cp0_usb3_1 { +- phys = <&cp0_comphy4 1>, <&cp0_utmi1>; +- phy-names = "usb", "utmi"; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&cp0_mdio { +- status = "okay"; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&cp0_ethernet { +- status = "okay"; +-}; +- +-&cp0_eth0 { +- status = "okay"; +- phy-mode = "10gbase-r"; +- +- fixed-link { +- speed = <10000>; +- full-duplex; +- }; +-}; +- +-&cp0_eth2 { +- status = "okay"; +- phy = <&phy1>; +- phy-mode = "rgmii-id"; +-}; +- +-/* CON6 on CP1 expansion */ +-&cp1_pcie0 { +- phys = <&cp1_comphy0 0>; +- phy-names = "cp1-pcie0-x1-phy"; +- status = "okay"; +-}; +- +-/* CON7 on CP1 expansion */ +-&cp1_pcie1 { +- phys = <&cp1_comphy4 1>; +- phy-names = "cp1-pcie1-x1-phy"; +- status = "okay"; +-}; +- +-/* CON5 on CP1 expansion */ +-&cp1_pcie2 { +- phys = <&cp1_comphy5 2>; +- phy-names = "cp1-pcie2-x1-phy"; +- status = "okay"; +-}; +- +-&cp1_i2c0 { +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&cp1_spi1 { +- status = "okay"; +- +- spi-flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0x0>; +- spi-max-frequency = <20000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "Boot"; +- reg = <0x0 0x200000>; +- }; +- partition@200000 { +- label = "Filesystem"; +- reg = <0x200000 0xd00000>; +- }; +- partition@f00000 { +- label = "Boot_2nd"; +- reg = <0xf00000 0x100000>; +- }; +- }; +- }; +-}; +- +-/* +- * Proper NAND usage will require DPR-76 to be in position 1-2, which disables +- * MDIO signal of CP1. +- */ +-&cp1_nand_controller { +- pinctrl-0 = <&nand_pins>, <&nand_rb>; +- pinctrl-names = "default"; +- +- nand@0 { +- reg = <0>; +- nand-rb = <0>; +- nand-on-flash-bbt; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0 0x200000>; +- }; +- partition@200000 { +- label = "Linux"; +- reg = <0x200000 0xe00000>; +- }; +- partition@1000000 { +- label = "Filesystem"; +- reg = <0x1000000 0x3f000000>; +- }; +- }; +- }; +-}; +- +-/* CON4 on CP1 expansion */ +-&cp1_sata0 { +- status = "okay"; +- +- sata-port@0 { +- phys = <&cp1_comphy1 0>; +- phy-names = "cp1-sata0-0-phy"; +- }; +- sata-port@1 { +- phys = <&cp1_comphy3 1>; +- phy-names = "cp1-sata0-1-phy"; +- }; +-}; +- +-&cp1_utmi { +- status = "okay"; +-}; +- +-/* CON9 on CP1 expansion */ +-&cp1_usb3_0 { +- usb-phy = <&cp1_usb3_0_phy>; +- phys = <&cp1_utmi0>; +- phy-names = "utmi"; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-/* CON10 on CP1 expansion */ +-&cp1_usb3_1 { +- phys = <&cp1_utmi1>; +- phy-names = "utmi"; +- status = "okay"; +-}; +- +-&cp1_mdio { +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&cp1_ethernet { +- status = "okay"; +-}; +- +-&cp1_eth0 { +- status = "okay"; +- phy-mode = "10gbase-r"; +- +- fixed-link { +- speed = <10000>; +- full-duplex; +- }; +-}; +- +-&cp1_eth1 { +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +-}; +- +-&ap_sdhci0 { +- status = "okay"; +- bus-width = <4>; +- non-removable; +-}; +- +-&cp0_sdhci0 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-mcbin-singleshot.dts b/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-mcbin-singleshot.dts +deleted file mode 100644 +index 411d20064271..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-mcbin-singleshot.dts ++++ /dev/null +@@ -1,51 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2016 Marvell Technology Group Ltd. +- * +- * Device Tree file for MACCHIATOBin Armada 8040 community board platform +- */ +- +-#include +- +-#include "armada-8040-mcbin.dtsi" +- +-/ { +- model = "Marvell 8040 MACCHIATOBin Single-shot"; +- compatible = "marvell,armada8040-mcbin-singleshot", +- "marvell,armada8040-mcbin", "marvell,armada8040", +- "marvell,armada-ap806-quad", "marvell,armada-ap806"; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&cp0_led18_pins>; +- pinctrl-names = "default"; +- +- led18 { +- gpios = <&cp0_gpio2 1 GPIO_ACTIVE_LOW>; +- function = LED_FUNCTION_HEARTBEAT; +- color = ; +- linux,default-trigger = "heartbeat"; +- }; +- }; +-}; +- +-&cp0_eth0 { +- status = "okay"; +- phy-mode = "10gbase-r"; +- managed = "in-band-status"; +- sfp = <&sfp_eth0>; +-}; +- +-&cp1_eth0 { +- status = "okay"; +- phy-mode = "10gbase-r"; +- managed = "in-band-status"; +- sfp = <&sfp_eth1>; +-}; +- +-&cp0_pinctrl { +- cp0_led18_pins: led18-pins { +- marvell,pins = "mpp33"; +- marvell,function = "gpio"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-mcbin.dts b/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-mcbin.dts +deleted file mode 100644 +index 1766cf58101b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-mcbin.dts ++++ /dev/null +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2016 Marvell Technology Group Ltd. +- * +- * Device Tree file for MACCHIATOBin Armada 8040 community board platform +- */ +- +-#include "armada-8040-mcbin.dtsi" +- +-/ { +- model = "Marvell 8040 MACCHIATOBin Double-shot"; +- compatible = "marvell,armada8040-mcbin-doubleshot", +- "marvell,armada8040-mcbin", "marvell,armada8040", +- "marvell,armada-ap806-quad", "marvell,armada-ap806"; +-}; +- +-&cp0_xmdio { +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0>; +- sfp = <&sfp_eth0>; +- }; +- +- phy8: ethernet-phy@8 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <8>; +- sfp = <&sfp_eth1>; +- }; +-}; +- +-&cp0_eth0 { +- status = "okay"; +- /* Network PHY */ +- phy = <&phy0>; +- phy-mode = "10gbase-r"; +-}; +- +-&cp1_eth0 { +- status = "okay"; +- /* Network PHY */ +- phy = <&phy8>; +- phy-mode = "10gbase-r"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-mcbin.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-mcbin.dtsi +deleted file mode 100644 +index adbfecc678b5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-mcbin.dtsi ++++ /dev/null +@@ -1,387 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2016 Marvell Technology Group Ltd. +- * +- * Device Tree file for MACCHIATOBin Armada 8040 community board platform +- */ +- +-#include "armada-8040.dtsi" +- +-#include +- +-/ { +- model = "Marvell 8040 MACCHIATOBin"; +- compatible = "marvell,armada8040-mcbin", "marvell,armada8040", +- "marvell,armada-ap806-quad", "marvell,armada-ap806"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- aliases { +- ethernet0 = &cp0_eth0; +- ethernet1 = &cp1_eth0; +- ethernet2 = &cp1_eth1; +- ethernet3 = &cp1_eth2; +- }; +- +- /* Regulator labels correspond with schematics */ +- v_3_3: regulator-3-3v { +- compatible = "regulator-fixed"; +- regulator-name = "v_3_3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- status = "okay"; +- }; +- +- v_vddo_h: regulator-1-8v { +- compatible = "regulator-fixed"; +- regulator-name = "v_vddo_h"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- status = "okay"; +- }; +- +- v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_xhci_vbus_pins>; +- regulator-name = "v_5v0_usb3_hst_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- status = "okay"; +- }; +- +- sfp_eth0: sfp-eth0 { +- /* CON15,16 - CPM lane 4 */ +- compatible = "sff,sfp"; +- i2c-bus = <&sfpp0_i2c>; +- los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>; +- mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>; +- tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; +- tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp1_sfpp0_pins>; +- maximum-power-milliwatt = <2000>; +- }; +- +- sfp_eth1: sfp-eth1 { +- /* CON17,18 - CPS lane 4 */ +- compatible = "sff,sfp"; +- i2c-bus = <&sfpp1_i2c>; +- los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; +- mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; +- tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>; +- tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>; +- maximum-power-milliwatt = <2000>; +- }; +- +- sfp_eth3: sfp-eth3 { +- /* CON13,14 - CPS lane 5 */ +- compatible = "sff,sfp"; +- i2c-bus = <&sfp_1g_i2c>; +- los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; +- mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>; +- tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>; +- tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>; +- maximum-power-milliwatt = <2000>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +- pinctrl-0 = <&uart0_pins>; +- pinctrl-names = "default"; +-}; +- +-&ap_sdhci0 { +- bus-width = <8>; +- /* +- * Not stable in HS modes - phy needs "more calibration", so add +- * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. +- */ +- marvell,xenon-phy-slow-mode; +- no-1-8-v; +- no-sd; +- no-sdio; +- non-removable; +- status = "okay"; +- vqmmc-supply = <&v_vddo_h>; +-}; +- +-&cp0_i2c0 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_i2c0_pins>; +- status = "okay"; +-}; +- +-&cp0_i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_i2c1_pins>; +- status = "okay"; +- +- i2c-switch@70 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- +- sfpp0_i2c: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- sfpp1_i2c: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- sfp_1g_i2c: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- }; +-}; +- +-/* J25 UART header */ +-&cp0_uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_uart1_pins>; +- status = "okay"; +-}; +- +-&cp0_mdio { +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_ge_mdio_pins>; +- status = "okay"; +- +- ge_phy: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&cp0_pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_pcie_pins>; +- num-lanes = <4>; +- num-viewport = <8>; +- reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>; +- ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>; +- phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, +- <&cp0_comphy2 0>, <&cp0_comphy3 0>; +- phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy", +- "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy"; +- status = "okay"; +-}; +- +-&cp0_pinctrl { +- cp0_ge_mdio_pins: ge-mdio-pins { +- marvell,pins = "mpp32", "mpp34"; +- marvell,function = "ge"; +- }; +- cp0_i2c1_pins: i2c1-pins { +- marvell,pins = "mpp35", "mpp36"; +- marvell,function = "i2c1"; +- }; +- cp0_i2c0_pins: i2c0-pins { +- marvell,pins = "mpp37", "mpp38"; +- marvell,function = "i2c0"; +- }; +- cp0_uart1_pins: uart1-pins { +- marvell,pins = "mpp40", "mpp41"; +- marvell,function = "uart1"; +- }; +- cp0_xhci_vbus_pins: xhci0-vbus-pins { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- cp0_sfp_1g_pins: sfp-1g-pins { +- marvell,pins = "mpp51", "mpp53", "mpp54"; +- marvell,function = "gpio"; +- }; +- cp0_pcie_pins: pcie-pins { +- marvell,pins = "mpp52"; +- marvell,function = "gpio"; +- }; +- cp0_sdhci_pins: sdhci-pins { +- marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59", +- "mpp60", "mpp61"; +- marvell,function = "sdio"; +- }; +- cp0_sfpp1_pins: sfpp1-pins { +- marvell,pins = "mpp62"; +- marvell,function = "gpio"; +- }; +-}; +- +-&cp0_ethernet { +- status = "okay"; +-}; +- +-&cp0_eth0 { +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp0_comphy4 0>; +-}; +- +-&cp0_sata0 { +- status = "okay"; +- +- /* CPM Lane 5 - U29 */ +- sata-port@1 { +- phys = <&cp0_comphy5 1>; +- phy-names = "cp0-sata0-1-phy"; +- }; +-}; +- +-&cp0_sdhci0 { +- /* U6 */ +- broken-cd; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_sdhci_pins>; +- status = "okay"; +- vqmmc-supply = <&v_3_3>; +-}; +- +-&cp0_utmi { +- status = "okay"; +-}; +- +-&cp0_usb3_0 { +- /* J38? - USB2.0 only */ +- phys = <&cp0_utmi0>; +- phy-names = "utmi"; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&cp0_usb3_1 { +- /* J38? - USB2.0 only */ +- phys = <&cp0_utmi1>; +- phy-names = "utmi"; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&cp1_ethernet { +- status = "okay"; +-}; +- +-&cp1_eth0 { +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp1_comphy4 0>; +-}; +- +-&cp1_eth1 { +- /* CPS Lane 0 - J5 (Gigabit RJ45) */ +- status = "okay"; +- /* Network PHY */ +- phy = <&ge_phy>; +- phy-mode = "sgmii"; +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp1_comphy0 1>; +-}; +- +-&cp1_eth2 { +- /* CPS Lane 5 */ +- status = "okay"; +- /* Network PHY */ +- phy-mode = "2500base-x"; +- managed = "in-band-status"; +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp1_comphy5 2>; +- sfp = <&sfp_eth3>; +-}; +- +-&cp1_pinctrl { +- cp1_sfpp1_pins: sfpp1-pins { +- marvell,pins = "mpp8", "mpp10", "mpp11"; +- marvell,function = "gpio"; +- }; +- cp1_spi1_pins: spi1-pins { +- marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16"; +- marvell,function = "spi1"; +- }; +- cp1_uart0_pins: uart0-pins { +- marvell,pins = "mpp6", "mpp7"; +- marvell,function = "uart0"; +- }; +- cp1_sfp_1g_pins: sfp-1g-pins { +- marvell,pins = "mpp24"; +- marvell,function = "gpio"; +- }; +- cp1_sfpp0_pins: sfpp0-pins { +- marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29"; +- marvell,function = "gpio"; +- }; +-}; +- +-/* J27 UART header */ +-&cp1_uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&cp1_uart0_pins>; +- status = "okay"; +-}; +- +-&cp1_sata0 { +- status = "okay"; +- +- /* CPS Lane 1 - U32 */ +- sata-port@0 { +- phys = <&cp1_comphy1 0>; +- phy-names = "cp1-sata0-0-phy"; +- }; +- +- /* CPS Lane 3 - U31 */ +- sata-port@1 { +- phys = <&cp1_comphy3 1>; +- phy-names = "cp1-sata0-1-phy"; +- }; +-}; +- +-&cp1_spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&cp1_spi1_pins>; +- status = "okay"; +- +- spi-flash@0 { +- compatible = "st,w25q32"; +- spi-max-frequency = <50000000>; +- reg = <0>; +- }; +-}; +- +-&cp1_comphy2 { +- cp1_usbh0_con: connector { +- compatible = "usb-a-connector"; +- phy-supply = <&v_5v0_usb3_hst_vbus>; +- }; +-}; +- +-&cp1_utmi { +- status = "okay"; +-}; +- +-&cp1_usb3_0 { +- /* CPS Lane 2 - CON7 */ +- phys = <&cp1_comphy2 0>, <&cp1_utmi0>; +- phy-names = "cp1-usb3h0-comphy", "utmi"; +- dr_mode = "host"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-puzzle-m801.dts b/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-puzzle-m801.dts +deleted file mode 100644 +index dac85fa748de..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-puzzle-m801.dts ++++ /dev/null +@@ -1,523 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2016 Marvell Technology Group Ltd. +- * Copyright (C) 2020 Sartura Ltd. +- * +- * Device Tree file for IEI Puzzle-M801 +- */ +- +-#include "armada-8040.dtsi" +- +-#include +-#include +- +-/ { +- model = "IEI-Puzzle-M801"; +- compatible = "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"; +- +- aliases { +- ethernet0 = &cp0_eth0; +- ethernet1 = &cp1_eth0; +- ethernet2 = &cp0_eth1; +- ethernet3 = &cp0_eth2; +- ethernet4 = &cp1_eth1; +- ethernet5 = &cp1_eth2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- /* Regulator labels correspond with schematics */ +- v_3_3: regulator-3-3v { +- compatible = "regulator-fixed"; +- regulator-name = "v_3_3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- status = "okay"; +- }; +- +- v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_xhci_vbus_pins>; +- regulator-name = "v_5v0_usb3_hst_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- status = "okay"; +- }; +- +- v_vddo_h: regulator-1-8v { +- compatible = "regulator-fixed"; +- regulator-name = "v_vddo_h"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- status = "okay"; +- }; +- +- sfp_cp0_eth0: sfp-cp0-eth0 { +- compatible = "sff,sfp"; +- i2c-bus = <&sfpplus0_i2c>; +- los-gpio = <&sfpplus_gpio 11 GPIO_ACTIVE_HIGH>; +- mod-def0-gpio = <&sfpplus_gpio 10 GPIO_ACTIVE_LOW>; +- tx-disable-gpio = <&sfpplus_gpio 9 GPIO_ACTIVE_HIGH>; +- tx-fault-gpio = <&sfpplus_gpio 8 GPIO_ACTIVE_HIGH>; +- maximum-power-milliwatt = <3000>; +- }; +- +- sfp_cp1_eth0: sfp-cp1-eth0 { +- compatible = "sff,sfp"; +- i2c-bus = <&sfpplus1_i2c>; +- los-gpio = <&sfpplus_gpio 3 GPIO_ACTIVE_HIGH>; +- mod-def0-gpio = <&sfpplus_gpio 2 GPIO_ACTIVE_LOW>; +- tx-disable-gpio = <&sfpplus_gpio 1 GPIO_ACTIVE_HIGH>; +- tx-fault-gpio = <&sfpplus_gpio 0 GPIO_ACTIVE_HIGH>; +- maximum-power-milliwatt = <3000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- status = "okay"; +- pinctrl-0 = <&cp0_sfpplus_led_pins &cp1_sfpplus_led_pins>; +- pinctrl-names = "default"; +- +- led-0 { +- /* SFP+ port 2: Activity */ +- function = LED_FUNCTION_LAN; +- function-enumerator = <0>; +- gpios = <&cp1_gpio1 6 GPIO_ACTIVE_LOW>; +- }; +- +- led-1 { +- /* SFP+ port 1: Activity */ +- function = LED_FUNCTION_LAN; +- function-enumerator = <1>; +- gpios = <&cp1_gpio1 14 GPIO_ACTIVE_LOW>; +- }; +- +- led-2 { +- /* SFP+ port 2: 10 Gbps indicator */ +- function = LED_FUNCTION_LAN; +- function-enumerator = <2>; +- gpios = <&cp1_gpio1 7 GPIO_ACTIVE_LOW>; +- }; +- +- led-3 { +- /* SFP+ port 2: 1 Gbps indicator */ +- function = LED_FUNCTION_LAN; +- function-enumerator = <3>; +- gpios = <&cp1_gpio1 8 GPIO_ACTIVE_LOW>; +- }; +- +- led-4 { +- /* SFP+ port 1: 10 Gbps indicator */ +- function = LED_FUNCTION_LAN; +- function-enumerator = <4>; +- gpios = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>; +- }; +- +- led-5 { +- /* SFP+ port 1: 1 Gbps indicator */ +- function = LED_FUNCTION_LAN; +- function-enumerator = <5>; +- gpios = <&cp1_gpio1 31 GPIO_ACTIVE_LOW>; +- }; +- +- led-6 { +- function = LED_FUNCTION_DISK; +- linux,default-trigger = "disk-activity"; +- gpios = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; +- }; +- +- }; +-}; +- +-&ap_sdhci0 { +- bus-width = <8>; +- /* +- * Not stable in HS modes - phy needs "more calibration", so add +- * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. +- */ +- marvell,xenon-phy-slow-mode; +- no-1-8-v; +- no-sd; +- no-sdio; +- non-removable; +- status = "okay"; +- vqmmc-supply = <&v_vddo_h>; +-}; +- +-&ap_thermal_cpu1 { +- trips { +- cpu_active: cpu-active { +- temperature = <44000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- }; +- cooling-maps { +- fan-map { +- trip = <&cpu_active>; +- cooling-device = <&chassis_fan_group0 64 THERMAL_NO_LIMIT>, +- <&chassis_fan_group1 64 THERMAL_NO_LIMIT>; +- }; +- }; +-}; +- +-&i2c0 { +- clock-frequency = <100000>; +- status = "okay"; +- +- rtc@32 { +- compatible = "epson,rx8010"; +- reg = <0x32>; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- spi-flash@0 { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- compatible = "jedec,spi-nor"; +- reg = <0x0>; +- spi-max-frequency = <20000000>; +- partition@u-boot { +- label = "u-boot"; +- reg = <0x00000000 0x001f0000>; +- }; +- partition@u-boot-env { +- label = "u-boot-env"; +- reg = <0x001f0000 0x00010000>; +- }; +- partition@ubi1 { +- label = "ubi1"; +- reg = <0x00200000 0x03f00000>; +- }; +- partition@ubi2 { +- label = "ubi2"; +- reg = <0x04100000 0x03f00000>; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +- pinctrl-0 = <&uart0_pins>; +- pinctrl-names = "default"; +-}; +- +-&uart1 { +- status = "okay"; +- /* IEI WT61P803 PUZZLE MCU Controller */ +- mcu { +- compatible = "iei,wt61p803-puzzle"; +- current-speed = <115200>; +- enable-beep; +- +- leds { +- compatible = "iei,wt61p803-puzzle-leds"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- led@0 { +- reg = <0>; +- function = LED_FUNCTION_POWER; +- color = ; +- }; +- }; +- +- hwmon { +- compatible = "iei,wt61p803-puzzle-hwmon"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- chassis_fan_group0:fan-group@0 { +- #cooling-cells = <2>; +- reg = <0x00>; +- cooling-levels = <64 102 170 230 250>; +- }; +- +- chassis_fan_group1:fan-group@1 { +- #cooling-cells = <2>; +- reg = <0x01>; +- cooling-levels = <64 102 170 230 250>; +- }; +- }; +- }; +-}; +- +-&cp0_rtc { +- status = "disabled"; +-}; +- +-&cp0_i2c0 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_i2c0_pins>; +- status = "okay"; +- +- sfpplus_gpio: gpio@21 { +- compatible = "nxp,pca9555"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- eeprom@54 { +- compatible = "atmel,24c04"; +- reg = <0x54>; +- }; +-}; +- +-&cp0_i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_i2c1_pins>; +- status = "okay"; +- +- i2c-switch@70 { +- compatible = "nxp,pca9544"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x70>; +- +- sfpplus0_i2c: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- sfpplus1_i2c: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- }; +-}; +- +-&cp0_uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_uart1_pins>; +- status = "okay"; +-}; +- +-&cp0_mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "okay"; +- +- ge_phy2: ethernet-phy@0 { +- reg = <0>; +- }; +- +- ge_phy3: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&cp0_pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_pcie_pins>; +- num-lanes = <1>; +- num-viewport = <8>; +- reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>; +- ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>; +- phys = <&cp0_comphy0 0>; +- phy-names = "cp0-pcie0-x1-phy"; +- status = "okay"; +-}; +- +-&cp0_pinctrl { +- cp0_ge_mdio_pins: ge-mdio-pins { +- marvell,pins = "mpp32", "mpp34"; +- marvell,function = "ge"; +- }; +- cp0_i2c1_pins: i2c1-pins { +- marvell,pins = "mpp35", "mpp36"; +- marvell,function = "i2c1"; +- }; +- cp0_i2c0_pins: i2c0-pins { +- marvell,pins = "mpp37", "mpp38"; +- marvell,function = "i2c0"; +- }; +- cp0_uart1_pins: uart1-pins { +- marvell,pins = "mpp40", "mpp41"; +- marvell,function = "uart1"; +- }; +- cp0_xhci_vbus_pins: xhci0-vbus-pins { +- marvell,pins = "mpp47"; +- marvell,function = "gpio"; +- }; +- cp0_pcie_pins: pcie-pins { +- marvell,pins = "mpp52"; +- marvell,function = "gpio"; +- }; +- cp0_sdhci_pins: sdhci-pins { +- marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59", +- "mpp60", "mpp61"; +- marvell,function = "sdio"; +- }; +- cp0_sfpplus_led_pins: sfpplus-led-pins { +- marvell,pins = "mpp54"; +- marvell,function = "gpio"; +- }; +-}; +- +-&cp0_ethernet { +- status = "okay"; +-}; +- +-&cp0_eth0 { +- status = "okay"; +- phy-mode = "10gbase-r"; +- phys = <&cp0_comphy4 0>; +- local-mac-address = [ae 00 00 00 ff 00]; +- sfp = <&sfp_cp0_eth0>; +- managed = "in-band-status"; +-}; +- +-&cp0_eth1 { +- status = "okay"; +- phy = <&ge_phy2>; +- phy-mode = "sgmii"; +- local-mac-address = [ae 00 00 00 ff 01]; +- phys = <&cp0_comphy3 1>; +-}; +- +-&cp0_eth2 { +- status = "okay"; +- phy-mode = "sgmii"; +- phys = <&cp0_comphy1 2>; +- local-mac-address = [ae 00 00 00 ff 02]; +- phy = <&ge_phy3>; +-}; +- +-&cp0_sata0 { +- status = "okay"; +- +- sata-port@0 { +- phys = <&cp0_comphy2 0>; +- phy-names = "cp0-sata0-0-phy"; +- }; +- +- sata-port@1 { +- phys = <&cp0_comphy5 1>; +- phy-names = "cp0-sata0-1-phy"; +- }; +-}; +- +-&cp0_sdhci0 { +- broken-cd; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_sdhci_pins>; +- status = "okay"; +- vqmmc-supply = <&v_3_3>; +-}; +- +-&cp0_usb3_0 { +- status = "okay"; +-}; +- +-&cp0_usb3_1 { +- status = "okay"; +-}; +- +-&cp1_i2c0 { +- clock-frequency = <100000>; +- status = "disabled"; +-}; +- +-&cp1_i2c1 { +- clock-frequency = <100000>; +- status = "disabled"; +-}; +- +-&cp1_rtc { +- status = "disabled"; +-}; +- +-&cp1_ethernet { +- status = "okay"; +-}; +- +-&cp1_eth0 { +- status = "okay"; +- phy-mode = "10gbase-r"; +- phys = <&cp1_comphy4 0>; +- local-mac-address = [ae 00 00 00 ff 03]; +- sfp = <&sfp_cp1_eth0>; +- managed = "in-band-status"; +-}; +- +-&cp1_eth1 { +- status = "okay"; +- phy = <&ge_phy4>; +- phy-mode = "sgmii"; +- local-mac-address = [ae 00 00 00 ff 04]; +- phys = <&cp1_comphy3 1>; +-}; +- +-&cp1_eth2 { +- status = "okay"; +- phy-mode = "sgmii"; +- local-mac-address = [ae 00 00 00 ff 05]; +- phys = <&cp1_comphy5 2>; +- phy = <&ge_phy5>; +-}; +- +-&cp1_pinctrl { +- cp1_sfpplus_led_pins: sfpplus-led-pins { +- marvell,pins = "mpp6", "mpp7", "mpp8", "mpp10", "mpp14", "mpp31"; +- marvell,function = "gpio"; +- }; +-}; +- +-&cp1_uart0 { +- status = "disabled"; +-}; +- +-&cp1_comphy2 { +- cp1_usbh0_con: connector { +- compatible = "usb-a-connector"; +- phy-supply = <&v_5v0_usb3_hst_vbus>; +- }; +-}; +- +-&cp1_usb3_0 { +- phys = <&cp1_comphy2 0>; +- phy-names = "cp1-usb3h0-comphy"; +- status = "okay"; +-}; +- +-&cp1_mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "okay"; +- +- ge_phy4: ethernet-phy@1 { +- reg = <1>; +- }; +- ge_phy5: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&cp1_pcie0 { +- num-lanes = <2>; +- phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>; +- phy-names = "cp1-pcie0-x2-lane0-phy", "cp1-pcie0-x2-lane1-phy"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-8040.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-8040.dtsi +deleted file mode 100644 +index 22c2d6ebf381..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-8040.dtsi ++++ /dev/null +@@ -1,61 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2016 Marvell Technology Group Ltd. +- * +- * Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and +- * two CP110. +- */ +- +-#include "armada-ap806-quad.dtsi" +-#include "armada-80x0.dtsi" +- +-/ { +- model = "Marvell Armada 8040"; +- compatible = "marvell,armada8040", "marvell,armada-ap806-quad", +- "marvell,armada-ap806"; +-}; +- +-&cp0_pcie0 { +- iommu-map = +- <0x0 &smmu 0x480 0x20>, +- <0x100 &smmu 0x4a0 0x20>, +- <0x200 &smmu 0x4c0 0x20>; +- iommu-map-mask = <0x031f>; +-}; +- +-/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock +- * in CP master is not connected (by package) to the oscillator. So +- * disable it. However, the RTC clock in CP slave is connected to the +- * oscillator so this one is let enabled. +- */ +-&cp0_rtc { +- status = "disabled"; +-}; +- +-&cp0_sata0 { +- iommus = <&smmu 0x444>; +-}; +- +-&cp0_sdhci0 { +- iommus = <&smmu 0x445>; +-}; +- +-&cp0_usb3_0 { +- iommus = <&smmu 0x440>; +-}; +- +-&cp0_usb3_1 { +- iommus = <&smmu 0x441>; +-}; +- +-&cp1_sata0 { +- iommus = <&smmu 0x454>; +-}; +- +-&cp1_usb3_0 { +- iommus = <&smmu 0x450>; +-}; +- +-&cp1_usb3_1 { +- iommus = <&smmu 0x451>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-8080-db.dts b/scripts/dtc/include-prefixes/arm64/marvell/armada-8080-db.dts +deleted file mode 100644 +index 4ba158f415ce..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-8080-db.dts ++++ /dev/null +@@ -1,28 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2017 Marvell Technology Group Ltd. +- * +- * Device Tree file for Marvell Armada-8080 Development board platform +- */ +- +-#include "armada-8080.dtsi" +- +-/ { +- model = "Marvell 8080 board"; +- compatible = "marvell,armada-8080-db", "marvell,armada-8080", +- "marvell,armada-ap810-octa", "marvell,armada-ap810"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +-}; +- +-&uart0_ap0 { +- clock-frequency = <384000>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-8080.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-8080.dtsi +deleted file mode 100644 +index 299e814d1ded..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-8080.dtsi ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2017 Marvell Technology Group Ltd. +- * +- * Device Tree file for Marvell Armada-8080 SoC, made of an AP810 OCTA. +- */ +- +-#include "armada-ap810-ap0-octa-core.dtsi" +- +-/ { +- model = "Marvell 8080 board"; +- compatible = "marvell,armada-8080", "marvell,armada-ap810-octa", +- "marvell,armada-ap810"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-80x0.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-80x0.dtsi +deleted file mode 100644 +index ee67c70bf02e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-80x0.dtsi ++++ /dev/null +@@ -1,108 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2017 Marvell Technology Group Ltd. +- * +- * Device Tree file for the Armada 80x0 SoC family +- */ +- +-/ { +- aliases { +- gpio1 = &cp1_gpio1; +- gpio2 = &cp0_gpio2; +- spi1 = &cp0_spi0; +- spi2 = &cp0_spi1; +- spi3 = &cp1_spi0; +- spi4 = &cp1_spi1; +- }; +-}; +- +-/* +- * Instantiate the master CP110 +- */ +-#define CP11X_NAME cp0 +-#define CP11X_BASE f2000000 +-#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000)) +-#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 +-#define CP11X_PCIE0_BASE f2600000 +-#define CP11X_PCIE1_BASE f2620000 +-#define CP11X_PCIE2_BASE f2640000 +- +-#include "armada-cp110.dtsi" +- +-#undef CP11X_NAME +-#undef CP11X_BASE +-#undef CP11X_PCIEx_MEM_BASE +-#undef CP11X_PCIEx_MEM_SIZE +-#undef CP11X_PCIE0_BASE +-#undef CP11X_PCIE1_BASE +-#undef CP11X_PCIE2_BASE +- +-/* +- * Instantiate the slave CP110 +- */ +-#define CP11X_NAME cp1 +-#define CP11X_BASE f4000000 +-#define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000)) +-#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 +-#define CP11X_PCIE0_BASE f4600000 +-#define CP11X_PCIE1_BASE f4620000 +-#define CP11X_PCIE2_BASE f4640000 +- +-#include "armada-cp110.dtsi" +- +-#undef CP11X_NAME +-#undef CP11X_BASE +-#undef CP11X_PCIEx_MEM_BASE +-#undef CP11X_PCIEx_MEM_SIZE +-#undef CP11X_PCIE0_BASE +-#undef CP11X_PCIE1_BASE +-#undef CP11X_PCIE2_BASE +- +-/* The 80x0 has two CP blocks, but uses only one block from each. */ +-&cp1_gpio1 { +- status = "okay"; +-}; +- +-&cp0_gpio2 { +- status = "okay"; +-}; +- +-&cp0_syscon0 { +- cp0_pinctrl: pinctrl { +- compatible = "marvell,armada-8k-cpm-pinctrl"; +- }; +-}; +- +-&cp1_syscon0 { +- cp1_pinctrl: pinctrl { +- compatible = "marvell,armada-8k-cps-pinctrl"; +- +- nand_pins: nand-pins { +- marvell,pins = +- "mpp0", "mpp1", "mpp2", "mpp3", +- "mpp4", "mpp5", "mpp6", "mpp7", +- "mpp8", "mpp9", "mpp10", "mpp11", +- "mpp15", "mpp16", "mpp17", "mpp18", +- "mpp19", "mpp20", "mpp21", "mpp22", +- "mpp23", "mpp24", "mpp25", "mpp26", +- "mpp27"; +- marvell,function = "dev"; +- }; +- +- nand_rb: nand-rb { +- marvell,pins = "mpp13", "mpp12"; +- marvell,function = "nf"; +- }; +- }; +-}; +- +-&cp1_crypto { +- /* +- * The cryptographic engine found on the cp110 +- * master is enabled by default at the SoC +- * level. Because it is not possible as of now +- * to enable two cryptographic engines in +- * parallel, disable this one by default. +- */ +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-ap806-dual.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-ap806-dual.dtsi +deleted file mode 100644 +index fcab5173fe67..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-ap806-dual.dtsi ++++ /dev/null +@@ -1,61 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2016 Marvell Technology Group Ltd. +- * +- * Device Tree file for Marvell Armada AP806. +- */ +- +-#include "armada-ap806.dtsi" +- +-/ { +- model = "Marvell Armada AP806 Dual"; +- compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x000>; +- enable-method = "psci"; +- #cooling-cells = <2>; +- clocks = <&cpu_clk 0>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2>; +- }; +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x001>; +- enable-method = "psci"; +- #cooling-cells = <2>; +- clocks = <&cpu_clk 0>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2>; +- }; +- +- l2: l2-cache { +- compatible = "cache"; +- cache-size = <0x80000>; +- cache-line-size = <64>; +- cache-sets = <512>; +- }; +- }; +- +- thermal-zones { +- /delete-node/ ap-thermal-cpu2; +- /delete-node/ ap-thermal-cpu3; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-ap806-quad.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-ap806-quad.dtsi +deleted file mode 100644 +index 3db427122f9e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-ap806-quad.dtsi ++++ /dev/null +@@ -1,93 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2016 Marvell Technology Group Ltd. +- * +- * Device Tree file for Marvell Armada AP806. +- */ +- +-#include "armada-ap806.dtsi" +- +-/ { +- model = "Marvell Armada AP806 Quad"; +- compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x000>; +- enable-method = "psci"; +- #cooling-cells = <2>; +- clocks = <&cpu_clk 0>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2_0>; +- }; +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x001>; +- enable-method = "psci"; +- #cooling-cells = <2>; +- clocks = <&cpu_clk 0>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2_0>; +- }; +- cpu2: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x100>; +- enable-method = "psci"; +- #cooling-cells = <2>; +- clocks = <&cpu_clk 1>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2_1>; +- }; +- cpu3: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x101>; +- enable-method = "psci"; +- #cooling-cells = <2>; +- clocks = <&cpu_clk 1>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2_1>; +- }; +- +- l2_0: l2-cache0 { +- compatible = "cache"; +- cache-size = <0x80000>; +- cache-line-size = <64>; +- cache-sets = <512>; +- }; +- +- l2_1: l2-cache1 { +- compatible = "cache"; +- cache-size = <0x80000>; +- cache-line-size = <64>; +- cache-sets = <512>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-ap806.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-ap806.dtsi +deleted file mode 100644 +index 866628679ac7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-ap806.dtsi ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2016 Marvell Technology Group Ltd. +- * +- * Device Tree file for Marvell Armada AP806. +- */ +- +-#define AP_NAME ap806 +-#include "armada-ap80x.dtsi" +- +-/ { +- model = "Marvell Armada AP806"; +- compatible = "marvell,armada-ap806"; +-}; +- +-&ap_syscon0 { +- ap_clk: clock { +- compatible = "marvell,ap806-clock"; +- #clock-cells = <1>; +- }; +-}; +- +-&ap_syscon1 { +- cpu_clk: clock-cpu@278 { +- compatible = "marvell,ap806-cpu-clock"; +- clocks = <&ap_clk 0>, <&ap_clk 1>; +- #clock-cells = <1>; +- reg = <0x278 0xa30>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-ap807-quad.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-ap807-quad.dtsi +deleted file mode 100644 +index 68782f161f12..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-ap807-quad.dtsi ++++ /dev/null +@@ -1,93 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Marvell Armada AP807 Quad +- * +- * Copyright (C) 2019 Marvell Technology Group Ltd. +- */ +- +-#include "armada-ap807.dtsi" +- +-/ { +- model = "Marvell Armada AP807 Quad"; +- compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x000>; +- enable-method = "psci"; +- #cooling-cells = <2>; +- clocks = <&cpu_clk 0>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2_0>; +- }; +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x001>; +- enable-method = "psci"; +- #cooling-cells = <2>; +- clocks = <&cpu_clk 0>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2_0>; +- }; +- cpu2: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x100>; +- enable-method = "psci"; +- #cooling-cells = <2>; +- clocks = <&cpu_clk 1>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2_1>; +- }; +- cpu3: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x101>; +- enable-method = "psci"; +- #cooling-cells = <2>; +- clocks = <&cpu_clk 1>; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2_1>; +- }; +- +- l2_0: l2-cache0 { +- compatible = "cache"; +- cache-size = <0x80000>; +- cache-line-size = <64>; +- cache-sets = <512>; +- }; +- +- l2_1: l2-cache1 { +- compatible = "cache"; +- cache-size = <0x80000>; +- cache-line-size = <64>; +- cache-sets = <512>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-ap807.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-ap807.dtsi +deleted file mode 100644 +index 4a23f65d475f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-ap807.dtsi ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree file for Marvell Armada AP807 +- * +- * Copyright (C) 2019 Marvell Technology Group Ltd. +- */ +- +-#define AP_NAME ap807 +-#include "armada-ap80x.dtsi" +- +-/ { +- model = "Marvell Armada AP807"; +- compatible = "marvell,armada-ap807"; +-}; +- +-&ap_syscon0 { +- ap_clk: clock { +- compatible = "marvell,ap807-clock"; +- #clock-cells = <1>; +- }; +-}; +- +-&ap_syscon1 { +- cpu_clk: clock-cpu { +- compatible = "marvell,ap807-cpu-clock"; +- clocks = <&ap_clk 0>, <&ap_clk 1>; +- #clock-cells = <1>; +- }; +-}; +- +-&ap_sdhci0 { +- compatible = "marvell,armada-ap807-sdhci", +- "marvell,armada-ap806-sdhci"; /* Backward compatibility */ +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-ap80x.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-ap80x.dtsi +deleted file mode 100644 +index 6614472100c2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-ap80x.dtsi ++++ /dev/null +@@ -1,464 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 Marvell Technology Group Ltd. +- * +- * Device Tree file for Marvell Armada AP80x. +- */ +- +-#include +-#include +- +-/dts-v1/; +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- gpio0 = &ap_gpio; +- spi0 = &spi0; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- /* +- * This area matches the mapping done with a +- * mainline U-Boot, and should be updated by the +- * bootloader. +- */ +- +- psci-area@4000000 { +- reg = <0x0 0x4000000 0x0 0x200000>; +- no-map; +- }; +- }; +- +- AP_NAME { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- ranges; +- +- config-space@f0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0x0 0x0 0xf0000000 0x1000000>; +- +- smmu: iommu@5000000 { +- compatible = "marvell,ap806-smmu-500", "arm,mmu-500"; +- reg = <0x100000 0x100000>; +- dma-coherent; +- #iommu-cells = <1>; +- #global-interrupts = <1>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@210000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- interrupt-controller; +- interrupts = ; +- reg = <0x210000 0x10000>, +- <0x220000 0x20000>, +- <0x240000 0x20000>, +- <0x260000 0x20000>; +- +- gic_v2m0: v2m@280000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x280000 0x1000>; +- arm,msi-base-spi = <160>; +- arm,msi-num-spis = <32>; +- }; +- gic_v2m1: v2m@290000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x290000 0x1000>; +- arm,msi-base-spi = <192>; +- arm,msi-num-spis = <32>; +- }; +- gic_v2m2: v2m@2a0000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x2a0000 0x1000>; +- arm,msi-base-spi = <224>; +- arm,msi-num-spis = <32>; +- }; +- gic_v2m3: v2m@2b0000 { +- compatible = "arm,gic-v2m-frame"; +- msi-controller; +- reg = <0x2b0000 0x1000>; +- arm,msi-base-spi = <256>; +- arm,msi-num-spis = <32>; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,cortex-a72-pmu"; +- interrupt-parent = <&pic>; +- interrupts = <17>; +- }; +- +- odmi: odmi@300000 { +- compatible = "marvell,odmi-controller"; +- interrupt-controller; +- msi-controller; +- marvell,odmi-frames = <4>; +- reg = <0x300000 0x4000>, +- <0x304000 0x4000>, +- <0x308000 0x4000>, +- <0x30C000 0x4000>; +- marvell,spi-base = <128>, <136>, <144>, <152>; +- }; +- +- gicp: gicp@3f0040 { +- compatible = "marvell,ap806-gicp"; +- reg = <0x3f0040 0x10>; +- marvell,spi-ranges = <64 64>, <288 64>; +- msi-controller; +- }; +- +- pic: interrupt-controller@3f0100 { +- compatible = "marvell,armada-8k-pic"; +- reg = <0x3f0100 0x10>; +- #interrupt-cells = <1>; +- interrupt-controller; +- interrupts = ; +- }; +- +- sei: interrupt-controller@3f0200 { +- compatible = "marvell,ap806-sei"; +- reg = <0x3f0200 0x40>; +- interrupts = ; +- #interrupt-cells = <1>; +- interrupt-controller; +- msi-controller; +- }; +- +- xor@400000 { +- compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; +- reg = <0x400000 0x1000>, +- <0x410000 0x1000>; +- msi-parent = <&gic_v2m0>; +- clocks = <&ap_clk 3>; +- dma-coherent; +- }; +- +- xor@420000 { +- compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; +- reg = <0x420000 0x1000>, +- <0x430000 0x1000>; +- msi-parent = <&gic_v2m0>; +- clocks = <&ap_clk 3>; +- dma-coherent; +- }; +- +- xor@440000 { +- compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; +- reg = <0x440000 0x1000>, +- <0x450000 0x1000>; +- msi-parent = <&gic_v2m0>; +- clocks = <&ap_clk 3>; +- dma-coherent; +- }; +- +- xor@460000 { +- compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; +- reg = <0x460000 0x1000>, +- <0x470000 0x1000>; +- msi-parent = <&gic_v2m0>; +- clocks = <&ap_clk 3>; +- dma-coherent; +- }; +- +- spi0: spi@510600 { +- compatible = "marvell,armada-380-spi"; +- reg = <0x510600 0x50>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&ap_clk 3>; +- status = "disabled"; +- }; +- +- i2c0: i2c@511000 { +- compatible = "marvell,mv78230-i2c"; +- reg = <0x511000 0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&ap_clk 3>; +- status = "disabled"; +- }; +- +- uart0: serial@512000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x512000 0x100>; +- reg-shift = <2>; +- interrupts = ; +- reg-io-width = <1>; +- clocks = <&ap_clk 3>; +- status = "disabled"; +- }; +- +- uart1: serial@512100 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x512100 0x100>; +- reg-shift = <2>; +- interrupts = ; +- reg-io-width = <1>; +- clocks = <&ap_clk 3>; +- status = "disabled"; +- +- }; +- +- watchdog: watchdog@610000 { +- compatible = "arm,sbsa-gwdt"; +- reg = <0x610000 0x1000>, <0x600000 0x1000>; +- interrupts = ; +- }; +- +- ap_sdhci0: sdhci@6e0000 { +- compatible = "marvell,armada-ap806-sdhci"; +- reg = <0x6e0000 0x300>; +- interrupts = ; +- clock-names = "core"; +- clocks = <&ap_clk 4>; +- dma-coherent; +- marvell,xenon-phy-slow-mode; +- status = "disabled"; +- }; +- +- ap_syscon0: system-controller@6f4000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x6f4000 0x2000>; +- +- ap_pinctrl: pinctrl { +- compatible = "marvell,ap806-pinctrl"; +- +- uart0_pins: uart0-pins { +- marvell,pins = "mpp11", "mpp19"; +- marvell,function = "uart0"; +- }; +- }; +- +- ap_gpio: gpio@1040 { +- compatible = "marvell,armada-8k-gpio"; +- offset = <0x1040>; +- ngpios = <20>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&ap_pinctrl 0 0 20>; +- marvell,pwm-offset = <0x10c0>; +- #pwm-cells = <2>; +- clocks = <&ap_clk 3>; +- }; +- }; +- +- ap_syscon1: system-controller@6f8000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x6f8000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ap_thermal: thermal-sensor@80 { +- compatible = "marvell,armada-ap806-thermal"; +- reg = <0x80 0x10>; +- interrupt-parent = <&sei>; +- interrupts = <18>; +- #thermal-sensor-cells = <1>; +- }; +- }; +- }; +- }; +- +- /* +- * The thermal IP features one internal sensor plus, if applicable, one +- * remote channel wired to one sensor per CPU. +- * +- * Only one thermal zone per AP/CP may trigger interrupts at a time, the +- * first one that will have a critical trip point will be chosen. +- */ +- thermal-zones { +- ap_thermal_ic: ap-thermal-ic { +- polling-delay-passive = <0>; /* Interrupt driven */ +- polling-delay = <0>; /* Interrupt driven */ +- +- thermal-sensors = <&ap_thermal 0>; +- +- trips { +- ap_crit: ap-crit { +- temperature = <100000>; /* mC degrees */ +- hysteresis = <2000>; /* mC degrees */ +- type = "critical"; +- }; +- }; +- +- cooling-maps { }; +- }; +- +- ap_thermal_cpu0: ap-thermal-cpu0 { +- polling-delay-passive = <1000>; +- polling-delay = <1000>; +- +- thermal-sensors = <&ap_thermal 1>; +- +- trips { +- cpu0_hot: cpu0-hot { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu0_emerg: cpu0-emerg { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- }; +- +- cooling-maps { +- map0_hot: map0-hot { +- trip = <&cpu0_hot>; +- cooling-device = <&cpu0 1 2>, +- <&cpu1 1 2>; +- }; +- map0_emerg: map0-ermerg { +- trip = <&cpu0_emerg>; +- cooling-device = <&cpu0 3 3>, +- <&cpu1 3 3>; +- }; +- }; +- }; +- +- ap_thermal_cpu1: ap-thermal-cpu1 { +- polling-delay-passive = <1000>; +- polling-delay = <1000>; +- +- thermal-sensors = <&ap_thermal 2>; +- +- trips { +- cpu1_hot: cpu1-hot { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu1_emerg: cpu1-emerg { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- }; +- +- cooling-maps { +- map1_hot: map1-hot { +- trip = <&cpu1_hot>; +- cooling-device = <&cpu0 1 2>, +- <&cpu1 1 2>; +- }; +- map1_emerg: map1-emerg { +- trip = <&cpu1_emerg>; +- cooling-device = <&cpu0 3 3>, +- <&cpu1 3 3>; +- }; +- }; +- }; +- +- ap_thermal_cpu2: ap-thermal-cpu2 { +- polling-delay-passive = <1000>; +- polling-delay = <1000>; +- +- thermal-sensors = <&ap_thermal 3>; +- +- trips { +- cpu2_hot: cpu2-hot { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu2_emerg: cpu2-emerg { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- }; +- +- cooling-maps { +- map2_hot: map2-hot { +- trip = <&cpu2_hot>; +- cooling-device = <&cpu2 1 2>, +- <&cpu3 1 2>; +- }; +- map2_emerg: map2-emerg { +- trip = <&cpu2_emerg>; +- cooling-device = <&cpu2 3 3>, +- <&cpu3 3 3>; +- }; +- }; +- }; +- +- ap_thermal_cpu3: ap-thermal-cpu3 { +- polling-delay-passive = <1000>; +- polling-delay = <1000>; +- +- thermal-sensors = <&ap_thermal 4>; +- +- trips { +- cpu3_hot: cpu3-hot { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu3_emerg: cpu3-emerg { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- }; +- +- cooling-maps { +- map3_hot: map3-bhot { +- trip = <&cpu3_hot>; +- cooling-device = <&cpu2 1 2>, +- <&cpu3 1 2>; +- }; +- map3_emerg: map3-emerg { +- trip = <&cpu3_emerg>; +- cooling-device = <&cpu2 3 3>, +- <&cpu3 3 3>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-ap810-ap0-octa-core.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-ap810-ap0-octa-core.dtsi +deleted file mode 100644 +index d1a7143ef3d4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-ap810-ap0-octa-core.dtsi ++++ /dev/null +@@ -1,65 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2017 Marvell Technology Group Ltd. +- * +- * Device Tree file for Marvell Armada AP810 OCTA cores. +- */ +- +-#include "armada-ap810-ap0.dtsi" +- +-/ { +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "marvell,armada-ap810-octa"; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x000>; +- enable-method = "psci"; +- }; +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x001>; +- enable-method = "psci"; +- }; +- cpu2: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x100>; +- enable-method = "psci"; +- }; +- cpu3: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x101>; +- enable-method = "psci"; +- }; +- cpu4: cpu@200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x200>; +- enable-method = "psci"; +- }; +- cpu5: cpu@201 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x201>; +- enable-method = "psci"; +- }; +- cpu6: cpu@300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x300>; +- enable-method = "psci"; +- }; +- cpu7: cpu@301 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x301>; +- enable-method = "psci"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-ap810-ap0.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-ap810-ap0.dtsi +deleted file mode 100644 +index 8107d120a8a7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-ap810-ap0.dtsi ++++ /dev/null +@@ -1,124 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2017 Marvell Technology Group Ltd. +- * +- * Device Tree file for Marvell Armada AP810. +- */ +- +-#include +- +-/dts-v1/; +- +-/ { +- model = "Marvell Armada AP810"; +- compatible = "marvell,armada-ap810"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- serial0 = &uart0_ap0; +- serial1 = &uart1_ap0; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- ap810-ap0 { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- ranges; +- +- config-space@e8000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0x0 0x0 0xe8000000 0x4000000>; +- interrupt-parent = <&gic>; +- +- gic: interrupt-controller@3000000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-controller; +- interrupts = ; +- ranges; +- +- reg = <0x3000000 0x10000>, /* GICD */ +- <0x3060000 0x100000>, /* GICR */ +- <0x00c0000 0x2000>, /* GICC */ +- <0x00d0000 0x1000>, /* GICH */ +- <0x00e0000 0x2000>; /* GICV */ +- +- gic_its_ap0: interrupt-controller@3040000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0x3040000 0x20000>; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- xor@400000 { +- compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; +- reg = <0x400000 0x1000>, +- <0x410000 0x1000>; +- msi-parent = <&gic_its_ap0 0xa0>; +- dma-coherent; +- }; +- +- xor@420000 { +- compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; +- reg = <0x420000 0x1000>, +- <0x430000 0x1000>; +- msi-parent = <&gic_its_ap0 0xa1>; +- dma-coherent; +- }; +- +- xor@440000 { +- compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; +- reg = <0x440000 0x1000>, +- <0x450000 0x1000>; +- msi-parent = <&gic_its_ap0 0xa2>; +- dma-coherent; +- }; +- +- xor@460000 { +- compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; +- reg = <0x460000 0x1000>, +- <0x470000 0x1000>; +- msi-parent = <&gic_its_ap0 0xa3>; +- dma-coherent; +- }; +- +- uart0_ap0: serial@512000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x512000 0x100>; +- reg-shift = <2>; +- interrupts = ; +- reg-io-width = <1>; +- status = "disabled"; +- }; +- +- uart1_ap0: serial@512100 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x512100 0x100>; +- reg-shift = <2>; +- interrupts = ; +- reg-io-width = <1>; +- status = "disabled"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-common.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-common.dtsi +deleted file mode 100644 +index c04c6c475022..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-common.dtsi ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2016 Marvell Technology Group Ltd. +- */ +- +-/* Common definitions used by Armada 7K/8K DTs */ +-#define PASTER(x, y) x ## y +-#define EVALUATOR(x, y) PASTER(x, y) +-#define CP11X_LABEL(name) EVALUATOR(CP11X_NAME, EVALUATOR(_, name)) +-#define CP11X_NODE_NAME(name) EVALUATOR(CP11X_NAME, EVALUATOR(-, name)) +-#define ADDRESSIFY(addr) EVALUATOR(0x, addr) +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-cp110.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-cp110.dtsi +deleted file mode 100644 +index 4fd33b0fa56e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-cp110.dtsi ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 Marvell Technology Group Ltd. +- * +- * Device Tree file for Marvell Armada CP110. +- */ +- +-#define CP11X_TYPE cp110 +- +-#include "armada-cp11x.dtsi" +- +-#undef CP11X_TYPE +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-cp115.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-cp115.dtsi +deleted file mode 100644 +index 1d0a9653e681..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-cp115.dtsi ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 Marvell Technology Group Ltd. +- * +- * Device Tree file for Marvell Armada CP115. +- */ +- +-#define CP11X_TYPE cp115 +- +-#include "armada-cp11x.dtsi" +- +-#undef CP11X_TYPE +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/armada-cp11x.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/armada-cp11x.dtsi +deleted file mode 100644 +index 3bd2182817fb..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/armada-cp11x.dtsi ++++ /dev/null +@@ -1,597 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2016 Marvell Technology Group Ltd. +- * +- * Device Tree file for Marvell Armada CP11x. +- */ +- +-#include +-#include +- +-#include "armada-common.dtsi" +- +-#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface)) +- +-/ { +- /* +- * The contents of the node are defined below, in order to +- * save one indentation level +- */ +- CP11X_NAME: CP11X_NAME { }; +- +- /* +- * CPs only have one sensor in the thermal IC. +- * +- * The cooling maps are empty as there are no cooling devices. +- */ +- thermal-zones { +- CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) { +- polling-delay-passive = <0>; /* Interrupt driven */ +- polling-delay = <0>; /* Interrupt driven */ +- +- thermal-sensors = <&CP11X_LABEL(thermal) 0>; +- +- trips { +- CP11X_LABEL(crit): crit { +- temperature = <100000>; /* mC degrees */ +- hysteresis = <2000>; /* mC degrees */ +- type = "critical"; +- }; +- }; +- +- cooling-maps { }; +- }; +- }; +-}; +- +-&CP11X_NAME { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "simple-bus"; +- interrupt-parent = <&CP11X_LABEL(icu_nsr)>; +- ranges; +- +- config-space@CP11X_BASE { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>; +- +- CP11X_LABEL(ethernet): ethernet@0 { +- compatible = "marvell,armada-7k-pp22"; +- reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>; +- clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>, +- <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>, +- <&CP11X_LABEL(clk) 1 18>; +- clock-names = "pp_clk", "gop_clk", +- "mg_clk", "mg_core_clk", "axi_clk"; +- marvell,system-controller = <&CP11X_LABEL(syscon0)>; +- status = "disabled"; +- dma-coherent; +- +- CP11X_LABEL(eth0): eth0 { +- interrupts = <39 IRQ_TYPE_LEVEL_HIGH>, +- <43 IRQ_TYPE_LEVEL_HIGH>, +- <47 IRQ_TYPE_LEVEL_HIGH>, +- <51 IRQ_TYPE_LEVEL_HIGH>, +- <55 IRQ_TYPE_LEVEL_HIGH>, +- <59 IRQ_TYPE_LEVEL_HIGH>, +- <63 IRQ_TYPE_LEVEL_HIGH>, +- <67 IRQ_TYPE_LEVEL_HIGH>, +- <71 IRQ_TYPE_LEVEL_HIGH>, +- <129 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "hif0", "hif1", "hif2", +- "hif3", "hif4", "hif5", "hif6", "hif7", +- "hif8", "link"; +- port-id = <0>; +- gop-port-id = <0>; +- status = "disabled"; +- }; +- +- CP11X_LABEL(eth1): eth1 { +- interrupts = <40 IRQ_TYPE_LEVEL_HIGH>, +- <44 IRQ_TYPE_LEVEL_HIGH>, +- <48 IRQ_TYPE_LEVEL_HIGH>, +- <52 IRQ_TYPE_LEVEL_HIGH>, +- <56 IRQ_TYPE_LEVEL_HIGH>, +- <60 IRQ_TYPE_LEVEL_HIGH>, +- <64 IRQ_TYPE_LEVEL_HIGH>, +- <68 IRQ_TYPE_LEVEL_HIGH>, +- <72 IRQ_TYPE_LEVEL_HIGH>, +- <128 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "hif0", "hif1", "hif2", +- "hif3", "hif4", "hif5", "hif6", "hif7", +- "hif8", "link"; +- port-id = <1>; +- gop-port-id = <2>; +- status = "disabled"; +- }; +- +- CP11X_LABEL(eth2): eth2 { +- interrupts = <41 IRQ_TYPE_LEVEL_HIGH>, +- <45 IRQ_TYPE_LEVEL_HIGH>, +- <49 IRQ_TYPE_LEVEL_HIGH>, +- <53 IRQ_TYPE_LEVEL_HIGH>, +- <57 IRQ_TYPE_LEVEL_HIGH>, +- <61 IRQ_TYPE_LEVEL_HIGH>, +- <65 IRQ_TYPE_LEVEL_HIGH>, +- <69 IRQ_TYPE_LEVEL_HIGH>, +- <73 IRQ_TYPE_LEVEL_HIGH>, +- <127 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "hif0", "hif1", "hif2", +- "hif3", "hif4", "hif5", "hif6", "hif7", +- "hif8", "link"; +- port-id = <2>; +- gop-port-id = <3>; +- status = "disabled"; +- }; +- }; +- +- CP11X_LABEL(comphy): phy@120000 { +- compatible = "marvell,comphy-cp110"; +- reg = <0x120000 0x6000>; +- marvell,system-controller = <&CP11X_LABEL(syscon0)>; +- clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>, +- <&CP11X_LABEL(clk) 1 18>; +- clock-names = "mg_clk", "mg_core_clk", "axi_clk"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- CP11X_LABEL(comphy0): phy@0 { +- reg = <0>; +- #phy-cells = <1>; +- }; +- +- CP11X_LABEL(comphy1): phy@1 { +- reg = <1>; +- #phy-cells = <1>; +- }; +- +- CP11X_LABEL(comphy2): phy@2 { +- reg = <2>; +- #phy-cells = <1>; +- }; +- +- CP11X_LABEL(comphy3): phy@3 { +- reg = <3>; +- #phy-cells = <1>; +- }; +- +- CP11X_LABEL(comphy4): phy@4 { +- reg = <4>; +- #phy-cells = <1>; +- }; +- +- CP11X_LABEL(comphy5): phy@5 { +- reg = <5>; +- #phy-cells = <1>; +- }; +- }; +- +- CP11X_LABEL(mdio): mdio@12a200 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "marvell,orion-mdio"; +- reg = <0x12a200 0x10>; +- clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1 5>, +- <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>; +- status = "disabled"; +- }; +- +- CP11X_LABEL(xmdio): mdio@12a600 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "marvell,xmdio"; +- reg = <0x12a600 0x10>; +- clocks = <&CP11X_LABEL(clk) 1 5>, +- <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>; +- status = "disabled"; +- }; +- +- CP11X_LABEL(icu): interrupt-controller@1e0000 { +- compatible = "marvell,cp110-icu"; +- reg = <0x1e0000 0x440>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- CP11X_LABEL(icu_nsr): interrupt-controller@10 { +- compatible = "marvell,cp110-icu-nsr"; +- reg = <0x10 0x20>; +- #interrupt-cells = <2>; +- interrupt-controller; +- msi-parent = <&gicp>; +- }; +- +- CP11X_LABEL(icu_sei): interrupt-controller@50 { +- compatible = "marvell,cp110-icu-sei"; +- reg = <0x50 0x10>; +- #interrupt-cells = <2>; +- interrupt-controller; +- msi-parent = <&sei>; +- }; +- }; +- +- CP11X_LABEL(rtc): rtc@284000 { +- compatible = "marvell,armada-8k-rtc"; +- reg = <0x284000 0x20>, <0x284080 0x24>; +- reg-names = "rtc", "rtc-soc"; +- interrupts = <77 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- CP11X_LABEL(syscon0): system-controller@440000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x440000 0x2000>; +- +- CP11X_LABEL(clk): clock { +- compatible = "marvell,cp110-clock"; +- #clock-cells = <2>; +- }; +- +- CP11X_LABEL(gpio1): gpio@100 { +- compatible = "marvell,armada-8k-gpio"; +- offset = <0x100>; +- ngpios = <32>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>; +- marvell,pwm-offset = <0x1f0>; +- #pwm-cells = <2>; +- interrupt-controller; +- interrupts = <86 IRQ_TYPE_LEVEL_HIGH>, +- <85 IRQ_TYPE_LEVEL_HIGH>, +- <84 IRQ_TYPE_LEVEL_HIGH>, +- <83 IRQ_TYPE_LEVEL_HIGH>; +- #interrupt-cells = <2>; +- clock-names = "core", "axi"; +- clocks = <&CP11X_LABEL(clk) 1 21>, +- <&CP11X_LABEL(clk) 1 17>; +- status = "disabled"; +- }; +- +- CP11X_LABEL(gpio2): gpio@140 { +- compatible = "marvell,armada-8k-gpio"; +- offset = <0x140>; +- ngpios = <31>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>; +- marvell,pwm-offset = <0x1f0>; +- #pwm-cells = <2>; +- interrupt-controller; +- interrupts = <82 IRQ_TYPE_LEVEL_HIGH>, +- <81 IRQ_TYPE_LEVEL_HIGH>, +- <80 IRQ_TYPE_LEVEL_HIGH>, +- <79 IRQ_TYPE_LEVEL_HIGH>; +- #interrupt-cells = <2>; +- clock-names = "core", "axi"; +- clocks = <&CP11X_LABEL(clk) 1 21>, +- <&CP11X_LABEL(clk) 1 17>; +- status = "disabled"; +- }; +- }; +- +- CP11X_LABEL(syscon1): system-controller@400000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x400000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- CP11X_LABEL(thermal): thermal-sensor@70 { +- compatible = "marvell,armada-cp110-thermal"; +- reg = <0x70 0x10>; +- interrupts-extended = +- <&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>; +- #thermal-sensor-cells = <1>; +- }; +- }; +- +- CP11X_LABEL(utmi): utmi@580000 { +- compatible = "marvell,cp110-utmi-phy"; +- reg = <0x580000 0x2000>; +- marvell,system-controller = <&CP11X_LABEL(syscon0)>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- CP11X_LABEL(utmi0): usb-phy@0 { +- reg = <0>; +- #phy-cells = <0>; +- }; +- +- CP11X_LABEL(utmi1): usb-phy@1 { +- reg = <1>; +- #phy-cells = <0>; +- }; +- }; +- +- CP11X_LABEL(usb3_0): usb@500000 { +- compatible = "marvell,armada-8k-xhci", +- "generic-xhci"; +- reg = <0x500000 0x4000>; +- dma-coherent; +- interrupts = <106 IRQ_TYPE_LEVEL_HIGH>; +- clock-names = "core", "reg"; +- clocks = <&CP11X_LABEL(clk) 1 22>, +- <&CP11X_LABEL(clk) 1 16>; +- status = "disabled"; +- }; +- +- CP11X_LABEL(usb3_1): usb@510000 { +- compatible = "marvell,armada-8k-xhci", +- "generic-xhci"; +- reg = <0x510000 0x4000>; +- dma-coherent; +- interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; +- clock-names = "core", "reg"; +- clocks = <&CP11X_LABEL(clk) 1 23>, +- <&CP11X_LABEL(clk) 1 16>; +- status = "disabled"; +- }; +- +- CP11X_LABEL(sata0): sata@540000 { +- compatible = "marvell,armada-8k-ahci", +- "generic-ahci"; +- reg = <0x540000 0x30000>; +- dma-coherent; +- interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&CP11X_LABEL(clk) 1 15>, +- <&CP11X_LABEL(clk) 1 16>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- sata-port@0 { +- reg = <0>; +- }; +- +- sata-port@1 { +- reg = <1>; +- }; +- }; +- +- CP11X_LABEL(xor0): xor@6a0000 { +- compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; +- reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>; +- dma-coherent; +- msi-parent = <&gic_v2m0>; +- clock-names = "core", "reg"; +- clocks = <&CP11X_LABEL(clk) 1 8>, +- <&CP11X_LABEL(clk) 1 14>; +- }; +- +- CP11X_LABEL(xor1): xor@6c0000 { +- compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; +- reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>; +- dma-coherent; +- msi-parent = <&gic_v2m0>; +- clock-names = "core", "reg"; +- clocks = <&CP11X_LABEL(clk) 1 7>, +- <&CP11X_LABEL(clk) 1 14>; +- }; +- +- CP11X_LABEL(spi0): spi@700600 { +- compatible = "marvell,armada-380-spi"; +- reg = <0x700600 0x50>; +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- clock-names = "core", "axi"; +- clocks = <&CP11X_LABEL(clk) 1 21>, +- <&CP11X_LABEL(clk) 1 17>; +- status = "disabled"; +- }; +- +- CP11X_LABEL(spi1): spi@700680 { +- compatible = "marvell,armada-380-spi"; +- reg = <0x700680 0x50>; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "core", "axi"; +- clocks = <&CP11X_LABEL(clk) 1 21>, +- <&CP11X_LABEL(clk) 1 17>; +- status = "disabled"; +- }; +- +- CP11X_LABEL(i2c0): i2c@701000 { +- compatible = "marvell,mv78230-i2c"; +- reg = <0x701000 0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <120 IRQ_TYPE_LEVEL_HIGH>; +- clock-names = "core", "reg"; +- clocks = <&CP11X_LABEL(clk) 1 21>, +- <&CP11X_LABEL(clk) 1 17>; +- status = "disabled"; +- }; +- +- CP11X_LABEL(i2c1): i2c@701100 { +- compatible = "marvell,mv78230-i2c"; +- reg = <0x701100 0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <121 IRQ_TYPE_LEVEL_HIGH>; +- clock-names = "core", "reg"; +- clocks = <&CP11X_LABEL(clk) 1 21>, +- <&CP11X_LABEL(clk) 1 17>; +- status = "disabled"; +- }; +- +- CP11X_LABEL(uart0): serial@702000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x702000 0x100>; +- reg-shift = <2>; +- interrupts = <122 IRQ_TYPE_LEVEL_HIGH>; +- reg-io-width = <1>; +- clock-names = "baudclk", "apb_pclk"; +- clocks = <&CP11X_LABEL(clk) 1 21>, +- <&CP11X_LABEL(clk) 1 17>; +- status = "disabled"; +- }; +- +- CP11X_LABEL(uart1): serial@702100 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x702100 0x100>; +- reg-shift = <2>; +- interrupts = <123 IRQ_TYPE_LEVEL_HIGH>; +- reg-io-width = <1>; +- clock-names = "baudclk", "apb_pclk"; +- clocks = <&CP11X_LABEL(clk) 1 21>, +- <&CP11X_LABEL(clk) 1 17>; +- status = "disabled"; +- }; +- +- CP11X_LABEL(uart2): serial@702200 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x702200 0x100>; +- reg-shift = <2>; +- interrupts = <124 IRQ_TYPE_LEVEL_HIGH>; +- reg-io-width = <1>; +- clock-names = "baudclk", "apb_pclk"; +- clocks = <&CP11X_LABEL(clk) 1 21>, +- <&CP11X_LABEL(clk) 1 17>; +- status = "disabled"; +- }; +- +- CP11X_LABEL(uart3): serial@702300 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x702300 0x100>; +- reg-shift = <2>; +- interrupts = <125 IRQ_TYPE_LEVEL_HIGH>; +- reg-io-width = <1>; +- clock-names = "baudclk", "apb_pclk"; +- clocks = <&CP11X_LABEL(clk) 1 21>, +- <&CP11X_LABEL(clk) 1 17>; +- status = "disabled"; +- }; +- +- CP11X_LABEL(nand_controller): nand@720000 { +- /* +- * Due to the limitation of the pins available +- * this controller is only usable on the CPM +- * for A7K and on the CPS for A8K. +- */ +- compatible = "marvell,armada-8k-nand-controller", +- "marvell,armada370-nand-controller"; +- reg = <0x720000 0x54>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <115 IRQ_TYPE_LEVEL_HIGH>; +- clock-names = "core", "reg"; +- clocks = <&CP11X_LABEL(clk) 1 2>, +- <&CP11X_LABEL(clk) 1 17>; +- marvell,system-controller = <&CP11X_LABEL(syscon0)>; +- status = "disabled"; +- }; +- +- CP11X_LABEL(trng): trng@760000 { +- compatible = "marvell,armada-8k-rng", +- "inside-secure,safexcel-eip76"; +- reg = <0x760000 0x7d>; +- interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; +- clock-names = "core", "reg"; +- clocks = <&CP11X_LABEL(clk) 1 25>, +- <&CP11X_LABEL(clk) 1 17>; +- status = "okay"; +- }; +- +- CP11X_LABEL(sdhci0): sdhci@780000 { +- compatible = "marvell,armada-cp110-sdhci"; +- reg = <0x780000 0x300>; +- interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; +- clock-names = "core", "axi"; +- clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1 18>; +- dma-coherent; +- status = "disabled"; +- }; +- +- CP11X_LABEL(crypto): crypto@800000 { +- compatible = "inside-secure,safexcel-eip197b"; +- reg = <0x800000 0x200000>; +- interrupts = <87 IRQ_TYPE_LEVEL_HIGH>, +- <88 IRQ_TYPE_LEVEL_HIGH>, +- <89 IRQ_TYPE_LEVEL_HIGH>, +- <90 IRQ_TYPE_LEVEL_HIGH>, +- <91 IRQ_TYPE_LEVEL_HIGH>, +- <92 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "mem", "ring0", "ring1", +- "ring2", "ring3", "eip"; +- clock-names = "core", "reg"; +- clocks = <&CP11X_LABEL(clk) 1 26>, +- <&CP11X_LABEL(clk) 1 17>; +- dma-coherent; +- }; +- }; +- +- CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE { +- compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; +- reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>, +- <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>; +- reg-names = "ctrl", "config"; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- dma-coherent; +- msi-parent = <&gic_v2m0>; +- +- bus-range = <0 0xff>; +- /* non-prefetchable memory */ +- ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>; +- interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; +- num-lanes = <1>; +- clock-names = "core", "reg"; +- clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>; +- status = "disabled"; +- }; +- +- CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE { +- compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; +- reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>, +- <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>; +- reg-names = "ctrl", "config"; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- dma-coherent; +- msi-parent = <&gic_v2m0>; +- +- bus-range = <0 0xff>; +- /* non-prefetchable memory */ +- ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; +- +- num-lanes = <1>; +- clock-names = "core", "reg"; +- clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>; +- status = "disabled"; +- }; +- +- CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE { +- compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; +- reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>, +- <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>; +- reg-names = "ctrl", "config"; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- dma-coherent; +- msi-parent = <&gic_v2m0>; +- +- bus-range = <0 0xff>; +- /* non-prefetchable memory */ +- ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>; +- interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; +- +- num-lanes = <1>; +- clock-names = "core", "reg"; +- clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/cn9130-crb-A.dts b/scripts/dtc/include-prefixes/arm64/marvell/cn9130-crb-A.dts +deleted file mode 100644 +index a7b6dfba8af5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/cn9130-crb-A.dts ++++ /dev/null +@@ -1,38 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2020 Marvell International Ltd. +- */ +- +-#include "cn9130-crb.dtsi" +- +-/ { +- model = "Marvell Armada CN9130-CRB-A"; +-}; +- +-&cp0_pcie0 { +- status = "okay"; +- num-lanes = <4>; +- num-viewport = <8>; +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp0_comphy0 0 +- &cp0_comphy1 0 +- &cp0_comphy2 0 +- &cp0_comphy3 0>; +- iommu-map = +- <0x0 &smmu 0x480 0x20>, +- <0x100 &smmu 0x4a0 0x20>, +- <0x200 &smmu 0x4c0 0x20>; +- iommu-map-mask = <0x031f>; +-}; +- +-&cp0_usb3_0 { +- status = "okay"; +- usb-phy = <&cp0_usb3_0_phy0>; +- phy-names = "usb"; +-}; +- +-&cp0_usb3_1 { +- status = "okay"; +- usb-phy = <&cp0_usb3_0_phy1>; +- phy-names = "usb"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/cn9130-crb-B.dts b/scripts/dtc/include-prefixes/arm64/marvell/cn9130-crb-B.dts +deleted file mode 100644 +index 0904cb0309ae..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/cn9130-crb-B.dts ++++ /dev/null +@@ -1,46 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2020 Marvell International Ltd. +- */ +- +-#include "cn9130-crb.dtsi" +- +-/ { +- model = "Marvell Armada CN9130-CRB-B"; +-}; +- +-&cp0_pcie0 { +- status = "okay"; +- num-lanes = <1>; +- num-viewport = <8>; +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp0_comphy0 0>; +- iommu-map = +- <0x0 &smmu 0x480 0x20>, +- <0x100 &smmu 0x4a0 0x20>, +- <0x200 &smmu 0x4c0 0x20>; +- iommu-map-mask = <0x031f>; +-}; +- +-&cp0_sata0 { +- status = "okay"; +- sata-port@0 { +- status = "okay"; +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp0_comphy2 0>; +- }; +-}; +- +-&cp0_usb3_0 { +- status = "okay"; +- usb-phy = <&cp0_usb3_0_phy0>; +- phy-names = "usb"; +- phys = <&cp0_comphy1 0>; +-}; +- +-&cp0_usb3_1 { +- status = "okay"; +- usb-phy = <&cp0_usb3_0_phy1>; +- phy-names = "usb"; +- phys = <&cp0_comphy3 1>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/cn9130-crb.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/cn9130-crb.dtsi +deleted file mode 100644 +index 505ae69289f6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/cn9130-crb.dtsi ++++ /dev/null +@@ -1,222 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2020 Marvell International Ltd. +- */ +- +-#include "cn9130.dtsi" /* include SoC device tree */ +- +-#include +- +-/ { +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- i2c0 = &cp0_i2c0; +- ethernet0 = &cp0_eth0; +- ethernet1 = &cp0_eth1; +- ethernet2 = &cp0_eth2; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- ap0_reg_mmc_vccq: ap0_mmc_vccq@0 { +- compatible = "regulator-gpio"; +- regulator-name = "ap0_mmc_vccq"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- gpios = <&expander0 5 GPIO_ACTIVE_HIGH>; +- states = <1800000 0x1 +- 3300000 0x0>; +- }; +- +- cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 { +- compatible = "regulator-fixed"; +- regulator-name = "cp0-xhci1-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&expander0 8 GPIO_ACTIVE_HIGH>; +- }; +- +- cp0_usb3_0_phy0: cp0_usb3_phy0 { +- compatible = "usb-nop-xceiv"; +- }; +- +- cp0_usb3_0_phy1: cp0_usb3_phy1 { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <&cp0_reg_usb3_vbus1>; +- }; +- +- cp0_reg_sd_vccq: cp0_sd_vccq@0 { +- compatible = "regulator-gpio"; +- regulator-name = "cp0_sd_vccq"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- gpios = <&cp0_gpio2 18 GPIO_ACTIVE_HIGH>; +- states = <1800000 0x1 +- 3300000 0x0>; +- }; +- +- cp0_reg_sd_vcc: cp0_sd_vcc@0 { +- compatible = "regulator-fixed"; +- regulator-name = "cp0_sd_vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-/* on-board eMMC U6 */ +-&ap_sdhci0 { +- pinctrl-names = "default"; +- bus-width = <8>; +- status = "okay"; +- mmc-ddr-1_8v; +- vqmmc-supply = <&ap0_reg_mmc_vccq>; +-}; +- +-&cp0_syscon0 { +- cp0_pinctrl: pinctrl { +- compatible = "marvell,cp115-standalone-pinctrl"; +- +- cp0_i2c0_pins: cp0-i2c-pins-0 { +- marvell,pins = "mpp37", "mpp38"; +- marvell,function = "i2c0"; +- }; +- cp0_i2c1_pins: cp0-i2c-pins-1 { +- marvell,pins = "mpp35", "mpp36"; +- marvell,function = "i2c1"; +- }; +- cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb { +- marvell,pins = "mpp55"; +- marvell,function = "gpio"; +- }; +- cp0_sdhci_pins: cp0-sdhi-pins-0 { +- marvell,pins = "mpp56", "mpp57", "mpp58", +- "mpp59", "mpp60", "mpp61"; +- marvell,function = "sdio"; +- }; +- cp0_spi0_pins: cp0-spi-pins-0 { +- marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; +- marvell,function = "spi1"; +- }; +- }; +-}; +- +-&cp0_i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_i2c0_pins>; +- status = "okay"; +- clock-frequency = <100000>; +- expander0: mcp23x17@20 { +- compatible = "microchip,mcp23017"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x20>; +- status = "okay"; +- }; +-}; +- +-&cp0_i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_i2c1_pins>; +- clock-frequency = <100000>; +- status = "okay"; +-}; +- +- +-&cp0_sdhci0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_sdhci_pins +- &cp0_sdhci_cd_pins_crb>; +- bus-width = <4>; +- cd-gpios = <&cp0_gpio2 23 GPIO_ACTIVE_HIGH>; +- vqmmc-supply = <&cp0_reg_sd_vccq>; +- vmmc-supply = <&cp0_reg_sd_vcc>; +- status = "okay"; +-}; +- +-&cp0_spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_spi0_pins>; +- reg = <0x700680 0x50>, /* control */ +- <0x2000000 0x1000000>; /* CS0 */ +- status = "okay"; +- +- spi-flash@0 { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- compatible = "jedec,spi-nor"; +- reg = <0x0>; +- /* On-board MUX does not allow higher frequencies */ +- spi-max-frequency = <40000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0x0 0x200000>; +- }; +- +- partition@400000 { +- label = "Filesystem"; +- reg = <0x200000 0xe00000>; +- }; +- }; +- }; +-}; +- +-&cp0_mdio { +- status = "okay"; +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&cp0_xmdio { +- status = "okay"; +- nbaset_phy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0>; +- }; +-}; +- +-&cp0_ethernet { +- status = "okay"; +-}; +- +-&cp0_eth0 { +- /* This port is connected to 88E6393X switch */ +- status = "okay"; +- phy-mode = "10gbase-r"; +- managed = "in-band-status"; +- phys = <&cp0_comphy4 0>; +-}; +- +-&cp0_eth1 { +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +-}; +- +-&cp0_eth2 { +- /* This port uses "2500base-t" phy-mode */ +- status = "disabled"; +- phy = <&nbaset_phy0>; +- phys = <&cp0_comphy5 2>; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/cn9130-db-B.dts b/scripts/dtc/include-prefixes/arm64/marvell/cn9130-db-B.dts +deleted file mode 100644 +index 57e41cacd483..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/cn9130-db-B.dts ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2020 Marvell International Ltd. +- * +- * Device tree for the CN9130-DB board (setup "B"). +- */ +- +-#include "cn9130-db.dtsi" +- +-/ { +- model = "Marvell Armada CN9130-DB setup B"; +-}; +- +-/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash. +- * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated +- * simultaneously. When NAND controller is enabled, SPI1 should be disabled. +- */ +- +-&cp0_nand_controller { +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/cn9130-db.dts b/scripts/dtc/include-prefixes/arm64/marvell/cn9130-db.dts +deleted file mode 100644 +index 994f347f2973..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/cn9130-db.dts ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 Marvell International Ltd. +- * +- * Device tree for the CN9130-DB board. +- */ +- +-#include "cn9130-db.dtsi" +- +-/ { +- model = "Marvell Armada CN9130-DB setup A"; +-}; +- +-/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash. +- * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated +- * simultaneously. When SPI controller is enabled, NAND should be disabled. +- */ +- +-&cp0_spi1 { +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/cn9130-db.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/cn9130-db.dtsi +deleted file mode 100644 +index c00b69b88bd2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/cn9130-db.dtsi ++++ /dev/null +@@ -1,410 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 Marvell International Ltd. +- * +- * Device tree for the CN9130-DB board. +- */ +- +-#include "cn9130.dtsi" +- +-#include +- +-/ { +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- gpio1 = &cp0_gpio1; +- gpio2 = &cp0_gpio2; +- i2c0 = &cp0_i2c0; +- ethernet0 = &cp0_eth0; +- ethernet1 = &cp0_eth1; +- ethernet2 = &cp0_eth2; +- spi1 = &cp0_spi0; +- spi2 = &cp0_spi1; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- ap0_reg_sd_vccq: ap0_sd_vccq@0 { +- compatible = "regulator-gpio"; +- regulator-name = "ap0_sd_vccq"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- gpios = <&expander0 8 GPIO_ACTIVE_HIGH>; +- states = <1800000 0x1 3300000 0x0>; +- }; +- +- cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 { +- compatible = "regulator-fixed"; +- regulator-name = "cp0-xhci0-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; +- }; +- +- cp0_usb3_0_phy0: cp0_usb3_phy@0 { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <&cp0_reg_usb3_vbus0>; +- }; +- +- cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 { +- compatible = "regulator-fixed"; +- regulator-name = "cp0-xhci1-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; +- }; +- +- cp0_usb3_0_phy1: cp0_usb3_phy@1 { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <&cp0_reg_usb3_vbus1>; +- }; +- +- cp0_reg_sd_vccq: cp0_sd_vccq@0 { +- compatible = "regulator-gpio"; +- regulator-name = "cp0_sd_vccq"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- gpios = <&expander0 15 GPIO_ACTIVE_HIGH>; +- states = <1800000 0x1 +- 3300000 0x0>; +- }; +- +- cp0_reg_sd_vcc: cp0_sd_vcc@0 { +- compatible = "regulator-fixed"; +- regulator-name = "cp0_sd_vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- cp0_sfp_eth0: sfp-eth@0 { +- compatible = "sff,sfp"; +- i2c-bus = <&cp0_sfpp0_i2c>; +- los-gpio = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>; +- mod-def0-gpio = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>; +- tx-disable-gpio = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>; +- tx-fault-gpio = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>; +- /* +- * SFP cages are unconnected on early PCBs because of an the I2C +- * lanes not being connected. Prevent the port for being +- * unusable by disabling the SFP node. +- */ +- status = "disabled"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-/* on-board eMMC - U9 */ +-&ap_sdhci0 { +- pinctrl-names = "default"; +- bus-width = <8>; +- vqmmc-supply = <&ap0_reg_sd_vccq>; +- status = "okay"; +-}; +- +-&cp0_crypto { +- status = "disabled"; +-}; +- +-&cp0_ethernet { +- status = "okay"; +-}; +- +-/* SLM-1521-V2, CON9 */ +-&cp0_eth0 { +- status = "okay"; +- phy-mode = "10gbase-r"; +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp0_comphy4 0>; +- managed = "in-band-status"; +- sfp = <&cp0_sfp_eth0>; +-}; +- +-/* CON56 */ +-&cp0_eth1 { +- status = "okay"; +- phy = <&phy0>; +- phy-mode = "rgmii-id"; +-}; +- +-/* CON57 */ +-&cp0_eth2 { +- status = "okay"; +- phy = <&phy1>; +- phy-mode = "rgmii-id"; +-}; +- +-&cp0_gpio1 { +- status = "okay"; +-}; +- +-&cp0_gpio2 { +- status = "okay"; +-}; +- +-&cp0_i2c0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_i2c0_pins>; +- clock-frequency = <100000>; +- +- /* U36 */ +- expander0: pca953x@21 { +- compatible = "nxp,pca9555"; +- pinctrl-names = "default"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x21>; +- status = "okay"; +- }; +- +- /* U42 */ +- eeprom0: eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- pagesize = <0x20>; +- }; +- +- /* U38 */ +- eeprom1: eeprom@57 { +- compatible = "atmel,24c64"; +- reg = <0x57>; +- pagesize = <0x20>; +- }; +-}; +- +-&cp0_i2c1 { +- status = "okay"; +- clock-frequency = <100000>; +- +- /* SLM-1521-V2 - U3 */ +- i2c-mux@72 { /* verify address - depends on dpr */ +- compatible = "nxp,pca9544"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x72>; +- cp0_sfpp0_i2c: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- /* U12 */ +- cp0_module_expander1: pca9555@21 { +- compatible = "nxp,pca9555"; +- pinctrl-names = "default"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x21>; +- }; +- +- }; +- }; +-}; +- +-&cp0_mdio { +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-/* U54 */ +-&cp0_nand_controller { +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&nand_pins &nand_rb>; +- +- nand@0 { +- reg = <0>; +- label = "main-storage"; +- nand-rb = <0>; +- nand-ecc-mode = "hw"; +- nand-on-flash-bbt; +- nand-ecc-strength = <8>; +- nand-ecc-step-size = <512>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot"; +- reg = <0 0x200000>; +- }; +- partition@200000 { +- label = "Linux"; +- reg = <0x200000 0xe00000>; +- }; +- partition@1000000 { +- label = "Filesystem"; +- reg = <0x1000000 0x3f000000>; +- }; +- }; +- }; +-}; +- +-/* SLM-1521-V2, CON6 */ +-&cp0_pcie0 { +- status = "okay"; +- num-lanes = <4>; +- num-viewport = <8>; +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp0_comphy0 0 +- &cp0_comphy1 0 +- &cp0_comphy2 0 +- &cp0_comphy3 0>; +-}; +- +-&cp0_sata0 { +- status = "okay"; +- +- /* SLM-1521-V2, CON2 */ +- sata-port@1 { +- status = "okay"; +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp0_comphy5 1>; +- }; +-}; +- +-/* CON 28 */ +-&cp0_sdhci0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_sdhci_pins +- &cp0_sdhci_cd_pins>; +- bus-width = <4>; +- cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- vqmmc-supply = <&cp0_reg_sd_vccq>; +- vmmc-supply = <&cp0_reg_sd_vcc>; +-}; +- +-/* U55 */ +-&cp0_spi1 { +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp0_spi0_pins>; +- reg = <0x700680 0x50>; +- +- spi-flash@0 { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- compatible = "jedec,spi-nor"; +- reg = <0x0>; +- /* On-board MUX does not allow higher frequencies */ +- spi-max-frequency = <40000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot-0"; +- reg = <0x0 0x200000>; +- }; +- +- partition@400000 { +- label = "Filesystem-0"; +- reg = <0x200000 0xe00000>; +- }; +- }; +- }; +-}; +- +-&cp0_syscon0 { +- cp0_pinctrl: pinctrl { +- compatible = "marvell,cp115-standalone-pinctrl"; +- +- cp0_i2c0_pins: cp0-i2c-pins-0 { +- marvell,pins = "mpp37", "mpp38"; +- marvell,function = "i2c0"; +- }; +- cp0_i2c1_pins: cp0-i2c-pins-1 { +- marvell,pins = "mpp35", "mpp36"; +- marvell,function = "i2c1"; +- }; +- cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 { +- marvell,pins = "mpp0", "mpp1", "mpp2", +- "mpp3", "mpp4", "mpp5", +- "mpp6", "mpp7", "mpp8", +- "mpp9", "mpp10", "mpp11"; +- marvell,function = "ge0"; +- }; +- cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 { +- marvell,pins = "mpp44", "mpp45", "mpp46", +- "mpp47", "mpp48", "mpp49", +- "mpp50", "mpp51", "mpp52", +- "mpp53", "mpp54", "mpp55"; +- marvell,function = "ge1"; +- }; +- cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 { +- marvell,pins = "mpp43"; +- marvell,function = "gpio"; +- }; +- cp0_sdhci_pins: cp0-sdhi-pins-0 { +- marvell,pins = "mpp56", "mpp57", "mpp58", +- "mpp59", "mpp60", "mpp61"; +- marvell,function = "sdio"; +- }; +- cp0_spi0_pins: cp0-spi-pins-0 { +- marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; +- marvell,function = "spi1"; +- }; +- nand_pins: nand-pins { +- marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18", +- "mpp19", "mpp20", "mpp21", "mpp22", +- "mpp23", "mpp24", "mpp25", "mpp26", +- "mpp27"; +- marvell,function = "dev"; +- }; +- nand_rb: nand-rb { +- marvell,pins = "mpp13"; +- marvell,function = "nf"; +- }; +- }; +-}; +- +-&cp0_utmi { +- status = "okay"; +-}; +- +-&cp0_usb3_0 { +- status = "okay"; +- usb-phy = <&cp0_usb3_0_phy0>; +- phys = <&cp0_utmi0>; +- phy-names = "utmi"; +- dr_mode = "host"; +-}; +- +-&cp0_usb3_1 { +- status = "okay"; +- usb-phy = <&cp0_usb3_0_phy1>; +- phys = <&cp0_utmi1>; +- phy-names = "utmi"; +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/cn9130.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/cn9130.dtsi +deleted file mode 100644 +index 327b04134134..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/cn9130.dtsi ++++ /dev/null +@@ -1,52 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 Marvell International Ltd. +- * +- * Device tree for the CN9130 SoC. +- */ +- +-#include "armada-ap807-quad.dtsi" +- +-/ { +- model = "Marvell Armada CN9130 SoC"; +- compatible = "marvell,cn9130", "marvell,armada-ap807-quad", +- "marvell,armada-ap807"; +- +- aliases { +- gpio1 = &cp0_gpio1; +- gpio2 = &cp0_gpio2; +- spi1 = &cp0_spi0; +- spi2 = &cp0_spi1; +- }; +-}; +- +-/* +- * Instantiate the internal CP115 +- */ +- +-#define CP11X_NAME cp0 +-#define CP11X_BASE f2000000 +-#define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \ +- 0xe0000000 + ((iface - 1) * 0x1000000)) +-#define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000) +-#define CP11X_PCIE0_BASE f2600000 +-#define CP11X_PCIE1_BASE f2620000 +-#define CP11X_PCIE2_BASE f2640000 +- +-#include "armada-cp115.dtsi" +- +-#undef CP11X_NAME +-#undef CP11X_BASE +-#undef CP11X_PCIEx_MEM_BASE +-#undef CP11X_PCIEx_MEM_SIZE +-#undef CP11X_PCIE0_BASE +-#undef CP11X_PCIE1_BASE +-#undef CP11X_PCIE2_BASE +- +-&cp0_gpio1 { +- status = "okay"; +-}; +- +-&cp0_gpio2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/cn9131-db-B.dts b/scripts/dtc/include-prefixes/arm64/marvell/cn9131-db-B.dts +deleted file mode 100644 +index 183b1ec8b1f0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/cn9131-db-B.dts ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2020 Marvell International Ltd. +- * +- * Device tree for the CN9131-DB board (setup "B"). +- */ +- +-#include "cn9131-db.dtsi" +- +-/ { +- model = "Marvell Armada CN9131-DB setup B"; +-}; +- +-/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash. +- * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated +- * simultaneously. When NAND controller is enabled, SPI1 should be disabled. +- */ +- +-&cp0_nand_controller { +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/cn9131-db.dts b/scripts/dtc/include-prefixes/arm64/marvell/cn9131-db.dts +deleted file mode 100644 +index a60fdee79bf8..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/cn9131-db.dts ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 Marvell International Ltd. +- * +- * Device tree for the CN9131-DB board. +- */ +- +-#include "cn9131-db.dtsi" +- +-/ { +- model = "Marvell Armada CN9131-DB setup A"; +-}; +- +-/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash. +- * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated +- * simultaneously. When SPI controller is enabled, NAND should be disabled. +- */ +- +-&cp0_spi1 { +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/cn9131-db.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/cn9131-db.dtsi +deleted file mode 100644 +index f995b1bcda01..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/cn9131-db.dtsi ++++ /dev/null +@@ -1,206 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2020 Marvell International Ltd. +- * +- * Device tree for the CN9131-DB board. +- */ +- +-#include "cn9130-db.dtsi" +- +-/ { +- compatible = "marvell,cn9131", "marvell,cn9130", +- "marvell,armada-ap807-quad", "marvell,armada-ap807"; +- +- aliases { +- gpio3 = &cp1_gpio1; +- gpio4 = &cp1_gpio2; +- ethernet3 = &cp1_eth0; +- ethernet4 = &cp1_eth1; +- }; +- +- cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 { +- compatible = "regulator-fixed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp1_xhci0_vbus_pins>; +- regulator-name = "cp1-xhci0-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>; +- }; +- +- cp1_usb3_0_phy0: cp1_usb3_phy0 { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <&cp1_reg_usb3_vbus0>; +- }; +- +- cp1_sfp_eth1: sfp-eth1 { +- compatible = "sff,sfp"; +- i2c-bus = <&cp1_i2c0>; +- los-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>; +- mod-def0-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>; +- tx-disable-gpio = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>; +- tx-fault-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp1_sfp_pins>; +- /* +- * SFP cages are unconnected on early PCBs because of an the I2C +- * lanes not being connected. Prevent the port for being +- * unusable by disabling the SFP node. +- */ +- status = "disabled"; +- }; +-}; +- +-/* +- * Instantiate the first slave CP115 +- */ +- +-#define CP11X_NAME cp1 +-#define CP11X_BASE f4000000 +-#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000)) +-#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 +-#define CP11X_PCIE0_BASE f4600000 +-#define CP11X_PCIE1_BASE f4620000 +-#define CP11X_PCIE2_BASE f4640000 +- +-#include "armada-cp115.dtsi" +- +-#undef CP11X_NAME +-#undef CP11X_BASE +-#undef CP11X_PCIEx_MEM_BASE +-#undef CP11X_PCIEx_MEM_SIZE +-#undef CP11X_PCIE0_BASE +-#undef CP11X_PCIE1_BASE +-#undef CP11X_PCIE2_BASE +- +-&cp1_crypto { +- status = "disabled"; +-}; +- +-&cp1_ethernet { +- status = "okay"; +-}; +- +-/* CON50 */ +-&cp1_eth0 { +- status = "okay"; +- phy-mode = "10gbase-r"; +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp1_comphy4 0>; +- managed = "in-band-status"; +- sfp = <&cp1_sfp_eth1>; +-}; +- +-&cp1_gpio1 { +- status = "okay"; +-}; +- +-&cp1_gpio2 { +- status = "okay"; +-}; +- +-&cp1_i2c0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp1_i2c0_pins>; +- clock-frequency = <100000>; +-}; +- +-/* CON40 */ +-&cp1_pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&cp1_pcie_reset_pins>; +- num-lanes = <2>; +- num-viewport = <8>; +- marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp1_comphy0 0 +- &cp1_comphy1 0>; +-}; +- +-&cp1_sata0 { +- status = "okay"; +- +- /* CON32 */ +- sata-port@1 { +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp1_comphy5 1>; +- }; +-}; +- +-/* U24 */ +-&cp1_spi1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp1_spi0_pins>; +- reg = <0x700680 0x50>; +- +- spi-flash@0 { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- compatible = "jedec,spi-nor"; +- reg = <0x0>; +- /* On-board MUX does not allow higher frequencies */ +- spi-max-frequency = <40000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "U-Boot-1"; +- reg = <0x0 0x200000>; +- }; +- +- partition@400000 { +- label = "Filesystem-1"; +- reg = <0x200000 0xe00000>; +- }; +- }; +- }; +- +-}; +- +-&cp1_syscon0 { +- cp1_pinctrl: pinctrl { +- compatible = "marvell,cp115-standalone-pinctrl"; +- +- cp1_i2c0_pins: cp1-i2c-pins-0 { +- marvell,pins = "mpp37", "mpp38"; +- marvell,function = "i2c0"; +- }; +- cp1_spi0_pins: cp1-spi-pins-0 { +- marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; +- marvell,function = "spi1"; +- }; +- cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins { +- marvell,pins = "mpp3"; +- marvell,function = "gpio"; +- }; +- cp1_sfp_pins: sfp-pins { +- marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11"; +- marvell,function = "gpio"; +- }; +- cp1_pcie_reset_pins: cp1-pcie-reset-pins { +- marvell,pins = "mpp0"; +- marvell,function = "gpio"; +- }; +- }; +-}; +- +-/* CON58 */ +-&cp1_utmi { +- status = "okay"; +-}; +- +-&cp1_usb3_1 { +- status = "okay"; +- usb-phy = <&cp1_usb3_0_phy0>; +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp1_comphy3 1>, <&cp1_utmi1>; +- phy-names = "usb", "utmi"; +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/cn9132-db-B.dts b/scripts/dtc/include-prefixes/arm64/marvell/cn9132-db-B.dts +deleted file mode 100644 +index 7137a6f22d0f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/cn9132-db-B.dts ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 Marvell International Ltd. +- * +- * Device tree for the CN9132-DB board. +- */ +- +-#include "cn9132-db.dtsi" +- +-/ { +- model = "Marvell Armada CN9132-DB setup B"; +-}; +- +-/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash. +- * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated +- * simultaneously. When NAND controller is enabled, SPI1 should be disabled. +- */ +- +-&cp0_nand_controller { +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/cn9132-db.dts b/scripts/dtc/include-prefixes/arm64/marvell/cn9132-db.dts +deleted file mode 100644 +index 1f2e6377afc3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/cn9132-db.dts ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 Marvell International Ltd. +- * +- * Device tree for the CN9132-DB board. +- */ +- +-#include "cn9132-db.dtsi" +- +-/ { +- model = "Marvell Armada CN9132-DB setup A"; +-}; +- +-/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash. +- * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated +- * simultaneously. When SPI controller is enabled, NAND should be disabled. +- */ +- +-&cp0_spi1 { +- status = "okay"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/marvell/cn9132-db.dtsi b/scripts/dtc/include-prefixes/arm64/marvell/cn9132-db.dtsi +deleted file mode 100644 +index 3f1795fb4fe7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/marvell/cn9132-db.dtsi ++++ /dev/null +@@ -1,227 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2020 Marvell International Ltd. +- * +- * Device tree for the CN9132-DB board. +- */ +- +-#include "cn9131-db.dtsi" +- +-/ { +- compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130", +- "marvell,armada-ap807-quad", "marvell,armada-ap807"; +- +- aliases { +- gpio5 = &cp2_gpio1; +- gpio6 = &cp2_gpio2; +- ethernet5 = &cp2_eth0; +- }; +- +- cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 { +- compatible = "regulator-fixed"; +- regulator-name = "cp2-xhci0-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>; +- }; +- +- cp2_usb3_0_phy0: cp2_usb3_phy0 { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <&cp2_reg_usb3_vbus0>; +- }; +- +- cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 { +- compatible = "regulator-fixed"; +- regulator-name = "cp2-xhci1-vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>; +- }; +- +- cp2_usb3_0_phy1: cp2_usb3_phy1 { +- compatible = "usb-nop-xceiv"; +- vcc-supply = <&cp2_reg_usb3_vbus1>; +- }; +- +- cp2_reg_sd_vccq: cp2_sd_vccq@0 { +- compatible = "regulator-gpio"; +- regulator-name = "cp2_sd_vcc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>; +- states = <1800000 0x1 3300000 0x0>; +- }; +- +- cp2_sfp_eth0: sfp-eth0 { +- compatible = "sff,sfp"; +- i2c-bus = <&cp2_sfpp0_i2c>; +- los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>; +- mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>; +- tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>; +- tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>; +- /* +- * SFP cages are unconnected on early PCBs because of an the I2C +- * lanes not being connected. Prevent the port for being +- * unusable by disabling the SFP node. +- */ +- status = "disabled"; +- }; +-}; +- +-/* +- * Instantiate the second slave CP115 +- */ +- +-#define CP11X_NAME cp2 +-#define CP11X_BASE f6000000 +-#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000)) +-#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 +-#define CP11X_PCIE0_BASE f6600000 +-#define CP11X_PCIE1_BASE f6620000 +-#define CP11X_PCIE2_BASE f6640000 +- +-#include "armada-cp115.dtsi" +- +-#undef CP11X_NAME +-#undef CP11X_BASE +-#undef CP11X_PCIEx_MEM_BASE +-#undef CP11X_PCIEx_MEM_SIZE +-#undef CP11X_PCIE0_BASE +-#undef CP11X_PCIE1_BASE +-#undef CP11X_PCIE2_BASE +- +-&cp2_crypto { +- status = "disabled"; +-}; +- +-&cp2_ethernet { +- status = "okay"; +-}; +- +-/* SLM-1521-V2, CON9 */ +-&cp2_eth0 { +- status = "disabled"; +- phy-mode = "10gbase-r"; +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp2_comphy4 0>; +- managed = "in-band-status"; +- sfp = <&cp2_sfp_eth0>; +-}; +- +-&cp2_gpio1 { +- status = "okay"; +-}; +- +-&cp2_gpio2 { +- status = "okay"; +-}; +- +-&cp2_i2c0 { +- clock-frequency = <100000>; +- +- /* SLM-1521-V2 - U3 */ +- i2c-mux@72 { +- compatible = "nxp,pca9544"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x72>; +- cp2_sfpp0_i2c: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- /* U12 */ +- cp2_module_expander1: pca9555@21 { +- compatible = "nxp,pca9555"; +- pinctrl-names = "default"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x21>; +- }; +- }; +- }; +-}; +- +-/* SLM-1521-V2, CON6 */ +-&cp2_pcie0 { +- status = "okay"; +- num-lanes = <2>; +- num-viewport = <8>; +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp2_comphy0 0 +- &cp2_comphy1 0>; +-}; +- +-/* SLM-1521-V2, CON8 */ +-&cp2_pcie2 { +- status = "okay"; +- num-lanes = <1>; +- num-viewport = <8>; +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp2_comphy5 2>; +-}; +- +-&cp2_sata0 { +- status = "okay"; +- +- /* SLM-1521-V2, CON4 */ +- sata-port@0 { +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp2_comphy2 0>; +- }; +-}; +- +-/* CON 2 on SLM-1683 - microSD */ +-&cp2_sdhci0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&cp2_sdhci_pins>; +- bus-width = <4>; +- cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>; +- vqmmc-supply = <&cp2_reg_sd_vccq>; +-}; +- +-&cp2_syscon0 { +- cp2_pinctrl: pinctrl { +- compatible = "marvell,cp115-standalone-pinctrl"; +- +- cp2_i2c0_pins: cp2-i2c-pins-0 { +- marvell,pins = "mpp37", "mpp38"; +- marvell,function = "i2c0"; +- }; +- cp2_sdhci_pins: cp2-sdhi-pins-0 { +- marvell,pins = "mpp56", "mpp57", "mpp58", +- "mpp59", "mpp60", "mpp61"; +- marvell,function = "sdio"; +- }; +- }; +-}; +- +-&cp2_utmi { +- status = "okay"; +-}; +- +-&cp2_usb3_0 { +- status = "okay"; +- usb-phy = <&cp2_usb3_0_phy0>; +- phys = <&cp2_utmi0>; +- phy-names = "usb"; +- dr_mode = "host"; +-}; +- +-/* SLM-1521-V2, CON11 */ +-&cp2_usb3_1 { +- status = "okay"; +- usb-phy = <&cp2_usb3_0_phy1>; +- /* Generic PHY, providing serdes lanes */ +- phys = <&cp2_comphy3 1>, <&cp2_utmi1>; +- phy-names = "usb", "utmi"; +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/Makefile b/scripts/dtc/include-prefixes/arm64/mediatek/Makefile +deleted file mode 100644 +index 4f68ebed2e31..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/Makefile ++++ /dev/null +@@ -1,35 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku288.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb +-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt2712-evb.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt2712-evb.dts +deleted file mode 100644 +index 7d369fdd3117..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt2712-evb.dts ++++ /dev/null +@@ -1,235 +0,0 @@ +-/* +- * Copyright (c) 2017 MediaTek Inc. +- * Author: YT Shen +- * +- * SPDX-License-Identifier: (GPL-2.0 OR MIT) +- */ +- +-/dts-v1/; +-#include +-#include "mt2712e.dtsi" +- +-/ { +- model = "MediaTek MT2712 evaluation board"; +- compatible = "mediatek,mt2712-evb", "mediatek,mt2712"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x80000000>; +- }; +- +- chosen { +- stdout-path = "serial0:921600n8"; +- }; +- +- cpus_fixed_vproc0: fixedregulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "vproc_buck0"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- cpus_fixed_vproc1: fixedregulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "vproc_buck1"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- extcon_usb: extcon_iddig { +- compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&pio 12 GPIO_ACTIVE_HIGH>; +- }; +- +- extcon_usb1: extcon_iddig1 { +- compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&pio 14 GPIO_ACTIVE_HIGH>; +- }; +- +- usb_p0_vbus: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "p0_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&pio 13 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- usb_p1_vbus: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "p1_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&pio 15 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- usb_p2_vbus: regulator@4 { +- compatible = "regulator-fixed"; +- regulator-name = "p2_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&pio 16 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- usb_p3_vbus: regulator@5 { +- compatible = "regulator-fixed"; +- regulator-name = "p3_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&pio 17 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +-}; +- +-&auxadc { +- status = "okay"; +-}; +- +-&cpu0 { +- proc-supply = <&cpus_fixed_vproc0>; +-}; +- +-&cpu1 { +- proc-supply = <&cpus_fixed_vproc0>; +-}; +- +-&cpu2 { +- proc-supply = <&cpus_fixed_vproc1>; +-}; +- +-ð { +- phy-mode ="rgmii-rxid"; +- phy-handle = <ðernet_phy0>; +- mediatek,tx-delay-ps = <1530>; +- snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <ð_default>; +- pinctrl-1 = <ð_sleep>; +- status = "okay"; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- ethernet_phy0: ethernet-phy@5 { +- compatible = "ethernet-phy-id0243.0d90"; +- reg = <0x5>; +- }; +- }; +-}; +- +-&pio { +- eth_default: eth_default { +- tx_pins { +- pinmux = , +- , +- , +- , +- , +- ; +- drive-strength = ; +- }; +- rx_pins { +- pinmux = , +- , +- , +- , +- , +- ; +- input-enable; +- }; +- mdio_pins { +- pinmux = , +- ; +- drive-strength = ; +- input-enable; +- }; +- }; +- +- eth_sleep: eth_sleep { +- tx_pins { +- pinmux = , +- , +- , +- , +- , +- ; +- }; +- rx_pins { +- pinmux = , +- , +- , +- , +- , +- ; +- input-disable; +- }; +- mdio_pins { +- pinmux = , +- ; +- input-disable; +- bias-disable; +- }; +- }; +- +- usb0_id_pins_float: usb0_iddig { +- pins_iddig { +- pinmux = ; +- bias-pull-up; +- }; +- }; +- +- usb1_id_pins_float: usb1_iddig { +- pins_iddig { +- pinmux = ; +- bias-pull-up; +- }; +- }; +-}; +- +-&ssusb { +- vbus-supply = <&usb_p0_vbus>; +- extcon = <&extcon_usb>; +- dr_mode = "otg"; +- wakeup-source; +- mediatek,u3p-dis-msk = <0x1>; +- //enable-manual-drd; +- //maximum-speed = "full-speed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb0_id_pins_float>; +- status = "okay"; +-}; +- +-&ssusb1 { +- vbus-supply = <&usb_p1_vbus>; +- extcon = <&extcon_usb1>; +- dr_mode = "otg"; +- //mediatek,u3p-dis-msk = <0x1>; +- enable-manual-drd; +- wakeup-source; +- //maximum-speed = "full-speed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb1_id_pins_float>; +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&usb_host0 { +- vbus-supply = <&usb_p2_vbus>; +- status = "okay"; +-}; +- +-&usb_host1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt2712-pinfunc.h b/scripts/dtc/include-prefixes/arm64/mediatek/mt2712-pinfunc.h +deleted file mode 100644 +index 385c455a7c98..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt2712-pinfunc.h ++++ /dev/null +@@ -1,1123 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2018 MediaTek Inc. +- * Author: Zhiyong Tao +- * +- */ +-#ifndef __DTS_MT2712_PINFUNC_H +-#define __DTS_MT2712_PINFUNC_H +- +-#include +- +-#define MT2712_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +-#define MT2712_PIN_0_EINT0__FUNC_EINT0 (MTK_PIN_NO(0) | 1) +-#define MT2712_PIN_0_EINT0__FUNC_MBIST_DIAG_SCANOUT (MTK_PIN_NO(0) | 2) +-#define MT2712_PIN_0_EINT0__FUNC_DSIA_TE (MTK_PIN_NO(0) | 3) +-#define MT2712_PIN_0_EINT0__FUNC_DSIC_TE (MTK_PIN_NO(0) | 4) +-#define MT2712_PIN_0_EINT0__FUNC_DIN_D3 (MTK_PIN_NO(0) | 5) +-#define MT2712_PIN_0_EINT0__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(0) | 6) +- +-#define MT2712_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +-#define MT2712_PIN_1_EINT1__FUNC_EINT1 (MTK_PIN_NO(1) | 1) +-#define MT2712_PIN_1_EINT1__FUNC_IR_IN (MTK_PIN_NO(1) | 2) +-#define MT2712_PIN_1_EINT1__FUNC_DSIB_TE (MTK_PIN_NO(1) | 3) +-#define MT2712_PIN_1_EINT1__FUNC_DSID_TE (MTK_PIN_NO(1) | 4) +-#define MT2712_PIN_1_EINT1__FUNC_DIN_D4 (MTK_PIN_NO(1) | 5) +- +-#define MT2712_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +-#define MT2712_PIN_2_EINT2__FUNC_EINT2 (MTK_PIN_NO(2) | 1) +-#define MT2712_PIN_2_EINT2__FUNC_IR_IN (MTK_PIN_NO(2) | 2) +-#define MT2712_PIN_2_EINT2__FUNC_LCM_RST1 (MTK_PIN_NO(2) | 3) +-#define MT2712_PIN_2_EINT2__FUNC_DIN_D5 (MTK_PIN_NO(2) | 5) +- +-#define MT2712_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +-#define MT2712_PIN_3_EINT3__FUNC_EINT3 (MTK_PIN_NO(3) | 1) +-#define MT2712_PIN_3_EINT3__FUNC_IR_IN (MTK_PIN_NO(3) | 2) +-#define MT2712_PIN_3_EINT3__FUNC_LCM_RST0 (MTK_PIN_NO(3) | 3) +-#define MT2712_PIN_3_EINT3__FUNC_DIN_D6 (MTK_PIN_NO(3) | 5) +- +-#define MT2712_PIN_4_PWM0__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +-#define MT2712_PIN_4_PWM0__FUNC_PWM0 (MTK_PIN_NO(4) | 1) +-#define MT2712_PIN_4_PWM0__FUNC_DISP0_PWM (MTK_PIN_NO(4) | 2) +-#define MT2712_PIN_4_PWM0__FUNC_DISP1_PWM (MTK_PIN_NO(4) | 3) +-#define MT2712_PIN_4_PWM0__FUNC_DIN_CLK (MTK_PIN_NO(4) | 5) +- +-#define MT2712_PIN_5_PWM1__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +-#define MT2712_PIN_5_PWM1__FUNC_PWM1 (MTK_PIN_NO(5) | 1) +-#define MT2712_PIN_5_PWM1__FUNC_DISP1_PWM (MTK_PIN_NO(5) | 2) +-#define MT2712_PIN_5_PWM1__FUNC_DISP0_PWM (MTK_PIN_NO(5) | 3) +-#define MT2712_PIN_5_PWM1__FUNC_DIN_VSYNC (MTK_PIN_NO(5) | 5) +- +-#define MT2712_PIN_6_PWM2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +-#define MT2712_PIN_6_PWM2__FUNC_PWM2 (MTK_PIN_NO(6) | 1) +-#define MT2712_PIN_6_PWM2__FUNC_DISP0_PWM (MTK_PIN_NO(6) | 2) +-#define MT2712_PIN_6_PWM2__FUNC_DISP1_PWM (MTK_PIN_NO(6) | 3) +-#define MT2712_PIN_6_PWM2__FUNC_DISP2_PWM (MTK_PIN_NO(6) | 4) +-#define MT2712_PIN_6_PWM2__FUNC_DIN_HSYNC (MTK_PIN_NO(6) | 5) +- +-#define MT2712_PIN_7_PWM3__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +-#define MT2712_PIN_7_PWM3__FUNC_PWM3 (MTK_PIN_NO(7) | 1) +-#define MT2712_PIN_7_PWM3__FUNC_DISP1_PWM (MTK_PIN_NO(7) | 2) +-#define MT2712_PIN_7_PWM3__FUNC_DISP0_PWM (MTK_PIN_NO(7) | 3) +-#define MT2712_PIN_7_PWM3__FUNC_LCM_RST2 (MTK_PIN_NO(7) | 4) +-#define MT2712_PIN_7_PWM3__FUNC_DIN_D0 (MTK_PIN_NO(7) | 5) +- +-#define MT2712_PIN_8_PWM4__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +-#define MT2712_PIN_8_PWM4__FUNC_PWM4 (MTK_PIN_NO(8) | 1) +-#define MT2712_PIN_8_PWM4__FUNC_DISP0_PWM (MTK_PIN_NO(8) | 2) +-#define MT2712_PIN_8_PWM4__FUNC_DISP1_PWM (MTK_PIN_NO(8) | 3) +-#define MT2712_PIN_8_PWM4__FUNC_DSIA_TE (MTK_PIN_NO(8) | 4) +-#define MT2712_PIN_8_PWM4__FUNC_DIN_D1 (MTK_PIN_NO(8) | 5) +- +-#define MT2712_PIN_9_PWM5__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +-#define MT2712_PIN_9_PWM5__FUNC_PWM5 (MTK_PIN_NO(9) | 1) +-#define MT2712_PIN_9_PWM5__FUNC_DISP1_PWM (MTK_PIN_NO(9) | 2) +-#define MT2712_PIN_9_PWM5__FUNC_DISP0_PWM (MTK_PIN_NO(9) | 3) +-#define MT2712_PIN_9_PWM5__FUNC_DSIB_TE (MTK_PIN_NO(9) | 4) +-#define MT2712_PIN_9_PWM5__FUNC_DIN_D2 (MTK_PIN_NO(9) | 5) +- +-#define MT2712_PIN_10_PWM6__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +-#define MT2712_PIN_10_PWM6__FUNC_PWM6 (MTK_PIN_NO(10) | 1) +-#define MT2712_PIN_10_PWM6__FUNC_DISP0_PWM (MTK_PIN_NO(10) | 2) +-#define MT2712_PIN_10_PWM6__FUNC_DISP1_PWM (MTK_PIN_NO(10) | 3) +-#define MT2712_PIN_10_PWM6__FUNC_LCM_RST0 (MTK_PIN_NO(10) | 4) +- +-#define MT2712_PIN_11_PWM7__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +-#define MT2712_PIN_11_PWM7__FUNC_PWM7 (MTK_PIN_NO(11) | 1) +-#define MT2712_PIN_11_PWM7__FUNC_DISP1_PWM (MTK_PIN_NO(11) | 2) +-#define MT2712_PIN_11_PWM7__FUNC_DISP0_PWM (MTK_PIN_NO(11) | 3) +-#define MT2712_PIN_11_PWM7__FUNC_LCM_RST1 (MTK_PIN_NO(11) | 4) +- +-#define MT2712_PIN_12_IDDIG_P0__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +-#define MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A (MTK_PIN_NO(12) | 1) +-#define MT2712_PIN_12_IDDIG_P0__FUNC_DIN_D7 (MTK_PIN_NO(12) | 5) +- +-#define MT2712_PIN_13_DRV_VBUS_P0__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +-#define MT2712_PIN_13_DRV_VBUS_P0__FUNC_DRV_VBUS_A (MTK_PIN_NO(13) | 1) +- +-#define MT2712_PIN_14_IDDIG_P1__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +-#define MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B (MTK_PIN_NO(14) | 1) +- +-#define MT2712_PIN_15_DRV_VBUS_P1__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +-#define MT2712_PIN_15_DRV_VBUS_P1__FUNC_DRV_VBUS_B (MTK_PIN_NO(15) | 1) +- +-#define MT2712_PIN_16_DRV_VBUS_P2__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +-#define MT2712_PIN_16_DRV_VBUS_P2__FUNC_DRV_VBUS_C (MTK_PIN_NO(16) | 1) +- +-#define MT2712_PIN_17_DRV_VBUS_P3__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +-#define MT2712_PIN_17_DRV_VBUS_P3__FUNC_DRV_VBUS_D (MTK_PIN_NO(17) | 1) +- +-#define MT2712_PIN_18_KPROW0__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +-#define MT2712_PIN_18_KPROW0__FUNC_KROW0 (MTK_PIN_NO(18) | 1) +- +-#define MT2712_PIN_19_KPCOL0__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +-#define MT2712_PIN_19_KPCOL0__FUNC_KCOL0 (MTK_PIN_NO(19) | 1) +- +-#define MT2712_PIN_20_KPROW1__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +-#define MT2712_PIN_20_KPROW1__FUNC_KROW1 (MTK_PIN_NO(20) | 1) +- +-#define MT2712_PIN_21_KPCOL1__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +-#define MT2712_PIN_21_KPCOL1__FUNC_KCOL1 (MTK_PIN_NO(21) | 1) +- +-#define MT2712_PIN_22_KPROW2__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +-#define MT2712_PIN_22_KPROW2__FUNC_KROW2 (MTK_PIN_NO(22) | 1) +-#define MT2712_PIN_22_KPROW2__FUNC_DISP1_PWM (MTK_PIN_NO(22) | 2) +- +-#define MT2712_PIN_23_KPCOL2__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +-#define MT2712_PIN_23_KPCOL2__FUNC_KCOL2 (MTK_PIN_NO(23) | 1) +-#define MT2712_PIN_23_KPCOL2__FUNC_DISP0_PWM (MTK_PIN_NO(23) | 2) +- +-#define MT2712_PIN_24_CMMCLK__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +-#define MT2712_PIN_24_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(24) | 1) +-#define MT2712_PIN_24_CMMCLK__FUNC_DBG_MON_A_1_ (MTK_PIN_NO(24) | 7) +- +-#define MT2712_PIN_25_CM2MCLK__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +-#define MT2712_PIN_25_CM2MCLK__FUNC_CM2MCLK (MTK_PIN_NO(25) | 1) +-#define MT2712_PIN_25_CM2MCLK__FUNC_DBG_MON_A_2_ (MTK_PIN_NO(25) | 7) +- +-#define MT2712_PIN_26_PCM_TX__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +-#define MT2712_PIN_26_PCM_TX__FUNC_PCM1_DO (MTK_PIN_NO(26) | 1) +-#define MT2712_PIN_26_PCM_TX__FUNC_MRG_TX (MTK_PIN_NO(26) | 2) +-#define MT2712_PIN_26_PCM_TX__FUNC_DAI_TX (MTK_PIN_NO(26) | 3) +-#define MT2712_PIN_26_PCM_TX__FUNC_MRG_RX (MTK_PIN_NO(26) | 4) +-#define MT2712_PIN_26_PCM_TX__FUNC_DAI_RX (MTK_PIN_NO(26) | 5) +-#define MT2712_PIN_26_PCM_TX__FUNC_PCM1_DI (MTK_PIN_NO(26) | 6) +-#define MT2712_PIN_26_PCM_TX__FUNC_DBG_MON_A_3_ (MTK_PIN_NO(26) | 7) +- +-#define MT2712_PIN_27_PCM_CLK__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +-#define MT2712_PIN_27_PCM_CLK__FUNC_PCM1_CLK (MTK_PIN_NO(27) | 1) +-#define MT2712_PIN_27_PCM_CLK__FUNC_MRG_CLK (MTK_PIN_NO(27) | 2) +-#define MT2712_PIN_27_PCM_CLK__FUNC_DAI_CLK (MTK_PIN_NO(27) | 3) +-#define MT2712_PIN_27_PCM_CLK__FUNC_DBG_MON_A_4_ (MTK_PIN_NO(27) | 7) +- +-#define MT2712_PIN_28_PCM_RX__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +-#define MT2712_PIN_28_PCM_RX__FUNC_PCM1_DI (MTK_PIN_NO(28) | 1) +-#define MT2712_PIN_28_PCM_RX__FUNC_MRG_RX (MTK_PIN_NO(28) | 2) +-#define MT2712_PIN_28_PCM_RX__FUNC_DAI_RX (MTK_PIN_NO(28) | 3) +-#define MT2712_PIN_28_PCM_RX__FUNC_MRG_TX (MTK_PIN_NO(28) | 4) +-#define MT2712_PIN_28_PCM_RX__FUNC_DAI_TX (MTK_PIN_NO(28) | 5) +-#define MT2712_PIN_28_PCM_RX__FUNC_PCM1_DO (MTK_PIN_NO(28) | 6) +-#define MT2712_PIN_28_PCM_RX__FUNC_DBG_MON_A_5_ (MTK_PIN_NO(28) | 7) +- +-#define MT2712_PIN_29_PCM_SYNC__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +-#define MT2712_PIN_29_PCM_SYNC__FUNC_PCM1_SYNC (MTK_PIN_NO(29) | 1) +-#define MT2712_PIN_29_PCM_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(29) | 2) +-#define MT2712_PIN_29_PCM_SYNC__FUNC_DAI_SYNC (MTK_PIN_NO(29) | 3) +-#define MT2712_PIN_29_PCM_SYNC__FUNC_DBG_MON_A_6_ (MTK_PIN_NO(29) | 7) +- +-#define MT2712_PIN_30_NCEB0__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +-#define MT2712_PIN_30_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(30) | 1) +-#define MT2712_PIN_30_NCEB0__FUNC_USB0_FT_SDA (MTK_PIN_NO(30) | 2) +-#define MT2712_PIN_30_NCEB0__FUNC_DBG_MON_A_7_ (MTK_PIN_NO(30) | 7) +- +-#define MT2712_PIN_31_NCEB1__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +-#define MT2712_PIN_31_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(31) | 1) +-#define MT2712_PIN_31_NCEB1__FUNC_USB1_FT_SCL (MTK_PIN_NO(31) | 2) +-#define MT2712_PIN_31_NCEB1__FUNC_DBG_MON_A_8_ (MTK_PIN_NO(31) | 7) +- +-#define MT2712_PIN_32_NF_DQS__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +-#define MT2712_PIN_32_NF_DQS__FUNC_NF_DQS (MTK_PIN_NO(32) | 1) +-#define MT2712_PIN_32_NF_DQS__FUNC_USB1_FT_SDA (MTK_PIN_NO(32) | 2) +-#define MT2712_PIN_32_NF_DQS__FUNC_DBG_MON_A_9_ (MTK_PIN_NO(32) | 7) +- +-#define MT2712_PIN_33_NWEB__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +-#define MT2712_PIN_33_NWEB__FUNC_NWEB (MTK_PIN_NO(33) | 1) +-#define MT2712_PIN_33_NWEB__FUNC_USB2_FT_SCL (MTK_PIN_NO(33) | 2) +-#define MT2712_PIN_33_NWEB__FUNC_DBG_MON_A_10_ (MTK_PIN_NO(33) | 7) +- +-#define MT2712_PIN_34_NREB__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +-#define MT2712_PIN_34_NREB__FUNC_NREB (MTK_PIN_NO(34) | 1) +-#define MT2712_PIN_34_NREB__FUNC_USB2_FT_SDA (MTK_PIN_NO(34) | 2) +-#define MT2712_PIN_34_NREB__FUNC_DBG_MON_A_11_ (MTK_PIN_NO(34) | 7) +- +-#define MT2712_PIN_35_NCLE__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +-#define MT2712_PIN_35_NCLE__FUNC_NCLE (MTK_PIN_NO(35) | 1) +-#define MT2712_PIN_35_NCLE__FUNC_USB3_FT_SCL (MTK_PIN_NO(35) | 2) +-#define MT2712_PIN_35_NCLE__FUNC_DBG_MON_A_12_ (MTK_PIN_NO(35) | 7) +- +-#define MT2712_PIN_36_NALE__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +-#define MT2712_PIN_36_NALE__FUNC_NALE (MTK_PIN_NO(36) | 1) +-#define MT2712_PIN_36_NALE__FUNC_USB3_FT_SDA (MTK_PIN_NO(36) | 2) +-#define MT2712_PIN_36_NALE__FUNC_DBG_MON_A_13_ (MTK_PIN_NO(36) | 7) +- +-#define MT2712_PIN_37_MSDC0E_CLK__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +-#define MT2712_PIN_37_MSDC0E_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(37) | 1) +-#define MT2712_PIN_37_MSDC0E_CLK__FUNC_USB0_FT_SCL (MTK_PIN_NO(37) | 2) +-#define MT2712_PIN_37_MSDC0E_CLK__FUNC_DBG_MON_A_0_ (MTK_PIN_NO(37) | 7) +- +-#define MT2712_PIN_38_MSDC0E_DAT7__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +-#define MT2712_PIN_38_MSDC0E_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(38) | 1) +-#define MT2712_PIN_38_MSDC0E_DAT7__FUNC_NAND_ND7 (MTK_PIN_NO(38) | 2) +-#define MT2712_PIN_38_MSDC0E_DAT7__FUNC_DBG_MON_A_14_ (MTK_PIN_NO(38) | 7) +- +-#define MT2712_PIN_39_MSDC0E_DAT6__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +-#define MT2712_PIN_39_MSDC0E_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(39) | 1) +-#define MT2712_PIN_39_MSDC0E_DAT6__FUNC_NAND_ND6 (MTK_PIN_NO(39) | 2) +-#define MT2712_PIN_39_MSDC0E_DAT6__FUNC_DBG_MON_A_15_ (MTK_PIN_NO(39) | 7) +- +-#define MT2712_PIN_40_MSDC0E_DAT5__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +-#define MT2712_PIN_40_MSDC0E_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(40) | 1) +-#define MT2712_PIN_40_MSDC0E_DAT5__FUNC_NAND_ND5 (MTK_PIN_NO(40) | 2) +-#define MT2712_PIN_40_MSDC0E_DAT5__FUNC_DBG_MON_A_16_ (MTK_PIN_NO(40) | 7) +- +-#define MT2712_PIN_41_MSDC0E_DAT4__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +-#define MT2712_PIN_41_MSDC0E_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(41) | 1) +-#define MT2712_PIN_41_MSDC0E_DAT4__FUNC_NAND_ND4 (MTK_PIN_NO(41) | 2) +-#define MT2712_PIN_41_MSDC0E_DAT4__FUNC_DBG_MON_A_17_ (MTK_PIN_NO(41) | 7) +- +-#define MT2712_PIN_42_MSDC0E_DAT3__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +-#define MT2712_PIN_42_MSDC0E_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(42) | 1) +-#define MT2712_PIN_42_MSDC0E_DAT3__FUNC_NAND_ND3 (MTK_PIN_NO(42) | 2) +-#define MT2712_PIN_42_MSDC0E_DAT3__FUNC_DBG_MON_A_18_ (MTK_PIN_NO(42) | 7) +- +-#define MT2712_PIN_43_MSDC0E_DAT2__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +-#define MT2712_PIN_43_MSDC0E_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(43) | 1) +-#define MT2712_PIN_43_MSDC0E_DAT2__FUNC_NAND_ND2 (MTK_PIN_NO(43) | 2) +-#define MT2712_PIN_43_MSDC0E_DAT2__FUNC_DBG_MON_A_19_ (MTK_PIN_NO(43) | 7) +- +-#define MT2712_PIN_44_MSDC0E_DAT1__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +-#define MT2712_PIN_44_MSDC0E_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(44) | 1) +-#define MT2712_PIN_44_MSDC0E_DAT1__FUNC_NAND_ND1 (MTK_PIN_NO(44) | 2) +-#define MT2712_PIN_44_MSDC0E_DAT1__FUNC_DBG_MON_A_20_ (MTK_PIN_NO(44) | 7) +- +-#define MT2712_PIN_45_MSDC0E_DAT0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +-#define MT2712_PIN_45_MSDC0E_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(45) | 1) +-#define MT2712_PIN_45_MSDC0E_DAT0__FUNC_NAND_ND0 (MTK_PIN_NO(45) | 2) +-#define MT2712_PIN_45_MSDC0E_DAT0__FUNC_DBG_MON_A_21_ (MTK_PIN_NO(45) | 7) +- +-#define MT2712_PIN_46_MSDC0E_CMD__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +-#define MT2712_PIN_46_MSDC0E_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(46) | 1) +-#define MT2712_PIN_46_MSDC0E_CMD__FUNC_NAND_NRNB (MTK_PIN_NO(46) | 2) +-#define MT2712_PIN_46_MSDC0E_CMD__FUNC_DBG_MON_A_22_ (MTK_PIN_NO(46) | 7) +- +-#define MT2712_PIN_47_MSDC0E_DSL__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +-#define MT2712_PIN_47_MSDC0E_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(47) | 1) +-#define MT2712_PIN_47_MSDC0E_DSL__FUNC_DBG_MON_A_23_ (MTK_PIN_NO(47) | 7) +- +-#define MT2712_PIN_48_MSDC0E_RSTB__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +-#define MT2712_PIN_48_MSDC0E_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(48) | 1) +-#define MT2712_PIN_48_MSDC0E_RSTB__FUNC_DBG_MON_A_24_ (MTK_PIN_NO(48) | 7) +- +-#define MT2712_PIN_49_MSDC3_DAT3__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +-#define MT2712_PIN_49_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(49) | 1) +-#define MT2712_PIN_49_MSDC3_DAT3__FUNC_DBG_MON_A_25_ (MTK_PIN_NO(49) | 7) +- +-#define MT2712_PIN_50_MSDC3_DAT2__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +-#define MT2712_PIN_50_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(50) | 1) +-#define MT2712_PIN_50_MSDC3_DAT2__FUNC_DBG_MON_A_26_ (MTK_PIN_NO(50) | 7) +- +-#define MT2712_PIN_51_MSDC3_DAT1__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +-#define MT2712_PIN_51_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(51) | 1) +-#define MT2712_PIN_51_MSDC3_DAT1__FUNC_DBG_MON_A_27_ (MTK_PIN_NO(51) | 7) +- +-#define MT2712_PIN_52_MSDC3_DAT0__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +-#define MT2712_PIN_52_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(52) | 1) +-#define MT2712_PIN_52_MSDC3_DAT0__FUNC_DBG_MON_A_28_ (MTK_PIN_NO(52) | 7) +- +-#define MT2712_PIN_53_MSDC3_CMD__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +-#define MT2712_PIN_53_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(53) | 1) +-#define MT2712_PIN_53_MSDC3_CMD__FUNC_DBG_MON_A_29_ (MTK_PIN_NO(53) | 7) +- +-#define MT2712_PIN_54_MSDC3_INS__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +-#define MT2712_PIN_54_MSDC3_INS__FUNC_MSDC3_INS (MTK_PIN_NO(54) | 1) +-#define MT2712_PIN_54_MSDC3_INS__FUNC_DBG_MON_A_30_ (MTK_PIN_NO(54) | 7) +- +-#define MT2712_PIN_55_MSDC3_DSL__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +-#define MT2712_PIN_55_MSDC3_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(55) | 1) +-#define MT2712_PIN_55_MSDC3_DSL__FUNC_DBG_MON_A_31_ (MTK_PIN_NO(55) | 7) +- +-#define MT2712_PIN_56_MSDC3_CLK__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +-#define MT2712_PIN_56_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(56) | 1) +-#define MT2712_PIN_56_MSDC3_CLK__FUNC_DBG_MON_A_32_ (MTK_PIN_NO(56) | 7) +- +-#define MT2712_PIN_57_NOR_CS__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +-#define MT2712_PIN_57_NOR_CS__FUNC_NOR_CS (MTK_PIN_NO(57) | 1) +- +-#define MT2712_PIN_58_NOR_CK__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +-#define MT2712_PIN_58_NOR_CK__FUNC_NOR_CK (MTK_PIN_NO(58) | 1) +- +-#define MT2712_PIN_59_NOR_IO0__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +-#define MT2712_PIN_59_NOR_IO0__FUNC_NOR_IO0 (MTK_PIN_NO(59) | 1) +- +-#define MT2712_PIN_60_NOR_IO1__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +-#define MT2712_PIN_60_NOR_IO1__FUNC_NOR_IO1 (MTK_PIN_NO(60) | 1) +- +-#define MT2712_PIN_61_NOR_IO2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +-#define MT2712_PIN_61_NOR_IO2__FUNC_NOR_IO2 (MTK_PIN_NO(61) | 1) +- +-#define MT2712_PIN_62_NOR_IO3__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +-#define MT2712_PIN_62_NOR_IO3__FUNC_NOR_IO3 (MTK_PIN_NO(62) | 1) +- +-#define MT2712_PIN_63_MSDC1_CLK__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +-#define MT2712_PIN_63_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(63) | 1) +-#define MT2712_PIN_63_MSDC1_CLK__FUNC_UDI_TCK (MTK_PIN_NO(63) | 2) +- +-#define MT2712_PIN_64_MSDC1_DAT3__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +-#define MT2712_PIN_64_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(64) | 1) +-#define MT2712_PIN_64_MSDC1_DAT3__FUNC_UDI_TDI (MTK_PIN_NO(64) | 2) +- +-#define MT2712_PIN_65_MSDC1_DAT1__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +-#define MT2712_PIN_65_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(65) | 1) +-#define MT2712_PIN_65_MSDC1_DAT1__FUNC_UDI_TMS (MTK_PIN_NO(65) | 2) +- +-#define MT2712_PIN_66_MSDC1_DAT2__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +-#define MT2712_PIN_66_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(66) | 1) +-#define MT2712_PIN_66_MSDC1_DAT2__FUNC_UDI_TDO (MTK_PIN_NO(66) | 2) +- +-#define MT2712_PIN_67_MSDC1_PSW__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +-#define MT2712_PIN_67_MSDC1_PSW__FUNC_UDI_NTRST (MTK_PIN_NO(67) | 2) +- +-#define MT2712_PIN_68_MSDC1_DAT0__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +-#define MT2712_PIN_68_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(68) | 1) +- +-#define MT2712_PIN_69_MSDC1_CMD__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +-#define MT2712_PIN_69_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(69) | 1) +- +-#define MT2712_PIN_70_MSDC1_INS__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +- +-#define MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +-#define MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3 (MTK_PIN_NO(71) | 1) +-#define MT2712_PIN_71_GBE_TXD3__FUNC_DBG_MON_B_0_ (MTK_PIN_NO(71) | 7) +- +-#define MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +-#define MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2 (MTK_PIN_NO(72) | 1) +-#define MT2712_PIN_72_GBE_TXD2__FUNC_DBG_MON_B_1_ (MTK_PIN_NO(72) | 7) +- +-#define MT2712_PIN_73_GBE_TXD1__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +-#define MT2712_PIN_73_GBE_TXD1__FUNC_GBE_TXD1 (MTK_PIN_NO(73) | 1) +-#define MT2712_PIN_73_GBE_TXD1__FUNC_DBG_MON_B_2_ (MTK_PIN_NO(73) | 7) +- +-#define MT2712_PIN_74_GBE_TXD0__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +-#define MT2712_PIN_74_GBE_TXD0__FUNC_GBE_TXD0 (MTK_PIN_NO(74) | 1) +-#define MT2712_PIN_74_GBE_TXD0__FUNC_DBG_MON_B_3_ (MTK_PIN_NO(74) | 7) +- +-#define MT2712_PIN_75_GBE_TXC__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +-#define MT2712_PIN_75_GBE_TXC__FUNC_GBE_TXC (MTK_PIN_NO(75) | 1) +-#define MT2712_PIN_75_GBE_TXC__FUNC_DBG_MON_B_4_ (MTK_PIN_NO(75) | 7) +- +-#define MT2712_PIN_76_GBE_TXEN__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +-#define MT2712_PIN_76_GBE_TXEN__FUNC_GBE_TXEN (MTK_PIN_NO(76) | 1) +-#define MT2712_PIN_76_GBE_TXEN__FUNC_DBG_MON_B_5_ (MTK_PIN_NO(76) | 7) +- +-#define MT2712_PIN_77_GBE_TXER__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +-#define MT2712_PIN_77_GBE_TXER__FUNC_GBE_TXER (MTK_PIN_NO(77) | 1) +-#define MT2712_PIN_77_GBE_TXER__FUNC_DBG_MON_B_6_ (MTK_PIN_NO(77) | 7) +- +-#define MT2712_PIN_78_GBE_RXD3__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +-#define MT2712_PIN_78_GBE_RXD3__FUNC_GBE_RXD3 (MTK_PIN_NO(78) | 1) +-#define MT2712_PIN_78_GBE_RXD3__FUNC_DBG_MON_B_7_ (MTK_PIN_NO(78) | 7) +- +-#define MT2712_PIN_79_GBE_RXD2__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +-#define MT2712_PIN_79_GBE_RXD2__FUNC_GBE_RXD2 (MTK_PIN_NO(79) | 1) +-#define MT2712_PIN_79_GBE_RXD2__FUNC_DBG_MON_B_8_ (MTK_PIN_NO(79) | 7) +- +-#define MT2712_PIN_80_GBE_RXD1__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +-#define MT2712_PIN_80_GBE_RXD1__FUNC_GBE_RXD1 (MTK_PIN_NO(80) | 1) +-#define MT2712_PIN_80_GBE_RXD1__FUNC_DBG_MON_B_9_ (MTK_PIN_NO(80) | 7) +- +-#define MT2712_PIN_81_GBE_RXD0__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +-#define MT2712_PIN_81_GBE_RXD0__FUNC_GBE_RXD0 (MTK_PIN_NO(81) | 1) +-#define MT2712_PIN_81_GBE_RXD0__FUNC_DBG_MON_B_10_ (MTK_PIN_NO(81) | 7) +- +-#define MT2712_PIN_82_GBE_RXDV__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +-#define MT2712_PIN_82_GBE_RXDV__FUNC_GBE_RXDV (MTK_PIN_NO(82) | 1) +-#define MT2712_PIN_82_GBE_RXDV__FUNC_DBG_MON_B_11_ (MTK_PIN_NO(82) | 7) +- +-#define MT2712_PIN_83_GBE_RXER__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +-#define MT2712_PIN_83_GBE_RXER__FUNC_GBE_RXER (MTK_PIN_NO(83) | 1) +-#define MT2712_PIN_83_GBE_RXER__FUNC_DBG_MON_B_12_ (MTK_PIN_NO(83) | 7) +- +-#define MT2712_PIN_84_GBE_RXC__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +-#define MT2712_PIN_84_GBE_RXC__FUNC_GBE_RXC (MTK_PIN_NO(84) | 1) +-#define MT2712_PIN_84_GBE_RXC__FUNC_DBG_MON_B_13_ (MTK_PIN_NO(84) | 7) +- +-#define MT2712_PIN_85_GBE_MDC__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +-#define MT2712_PIN_85_GBE_MDC__FUNC_GBE_MDC (MTK_PIN_NO(85) | 1) +-#define MT2712_PIN_85_GBE_MDC__FUNC_DBG_MON_B_14_ (MTK_PIN_NO(85) | 7) +- +-#define MT2712_PIN_86_GBE_MDIO__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +-#define MT2712_PIN_86_GBE_MDIO__FUNC_GBE_MDIO (MTK_PIN_NO(86) | 1) +-#define MT2712_PIN_86_GBE_MDIO__FUNC_DBG_MON_B_15_ (MTK_PIN_NO(86) | 7) +- +-#define MT2712_PIN_87_GBE_COL__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +-#define MT2712_PIN_87_GBE_COL__FUNC_GBE_COL (MTK_PIN_NO(87) | 1) +-#define MT2712_PIN_87_GBE_COL__FUNC_DBG_MON_B_16_ (MTK_PIN_NO(87) | 7) +- +-#define MT2712_PIN_88_GBE_INTR__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +-#define MT2712_PIN_88_GBE_INTR__FUNC_GBE_INTR (MTK_PIN_NO(88) | 1) +-#define MT2712_PIN_88_GBE_INTR__FUNC_GBE_CRS (MTK_PIN_NO(88) | 2) +-#define MT2712_PIN_88_GBE_INTR__FUNC_DBG_MON_B_17_ (MTK_PIN_NO(88) | 7) +- +-#define MT2712_PIN_89_MSDC2_CLK__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +-#define MT2712_PIN_89_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(89) | 1) +-#define MT2712_PIN_89_MSDC2_CLK__FUNC_DBG_MON_B_18_ (MTK_PIN_NO(89) | 7) +- +-#define MT2712_PIN_90_MSDC2_DAT3__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +-#define MT2712_PIN_90_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(90) | 1) +-#define MT2712_PIN_90_MSDC2_DAT3__FUNC_DBG_MON_B_19_ (MTK_PIN_NO(90) | 7) +- +-#define MT2712_PIN_91_MSDC2_DAT2__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +-#define MT2712_PIN_91_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(91) | 1) +-#define MT2712_PIN_91_MSDC2_DAT2__FUNC_DBG_MON_B_20_ (MTK_PIN_NO(91) | 7) +- +-#define MT2712_PIN_92_MSDC2_DAT1__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +-#define MT2712_PIN_92_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(92) | 1) +-#define MT2712_PIN_92_MSDC2_DAT1__FUNC_DBG_MON_B_21_ (MTK_PIN_NO(92) | 7) +- +-#define MT2712_PIN_93_MSDC2_DAT0__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +-#define MT2712_PIN_93_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(93) | 1) +-#define MT2712_PIN_93_MSDC2_DAT0__FUNC_DBG_MON_B_22_ (MTK_PIN_NO(93) | 7) +- +-#define MT2712_PIN_94_MSDC2_INS__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +-#define MT2712_PIN_94_MSDC2_INS__FUNC_DBG_MON_B_23_ (MTK_PIN_NO(94) | 7) +- +-#define MT2712_PIN_95_MSDC2_CMD__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +-#define MT2712_PIN_95_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(95) | 1) +-#define MT2712_PIN_95_MSDC2_CMD__FUNC_DBG_MON_B_24_ (MTK_PIN_NO(95) | 7) +- +-#define MT2712_PIN_96_MSDC2_PSW__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +-#define MT2712_PIN_96_MSDC2_PSW__FUNC_DBG_MON_B_25_ (MTK_PIN_NO(96) | 7) +- +-#define MT2712_PIN_97_URXD4__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +-#define MT2712_PIN_97_URXD4__FUNC_URXD4 (MTK_PIN_NO(97) | 1) +-#define MT2712_PIN_97_URXD4__FUNC_UTXD4 (MTK_PIN_NO(97) | 2) +-#define MT2712_PIN_97_URXD4__FUNC_MRG_CLK (MTK_PIN_NO(97) | 3) +-#define MT2712_PIN_97_URXD4__FUNC_PCM1_CLK (MTK_PIN_NO(97) | 4) +-#define MT2712_PIN_97_URXD4__FUNC_I2S_IQ2_SDQB (MTK_PIN_NO(97) | 5) +-#define MT2712_PIN_97_URXD4__FUNC_I2SO1_WS (MTK_PIN_NO(97) | 6) +-#define MT2712_PIN_97_URXD4__FUNC_DBG_MON_B_26_ (MTK_PIN_NO(97) | 7) +- +-#define MT2712_PIN_98_URTS4__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +-#define MT2712_PIN_98_URTS4__FUNC_URTS4 (MTK_PIN_NO(98) | 1) +-#define MT2712_PIN_98_URTS4__FUNC_UCTS4 (MTK_PIN_NO(98) | 2) +-#define MT2712_PIN_98_URTS4__FUNC_MRG_RX (MTK_PIN_NO(98) | 3) +-#define MT2712_PIN_98_URTS4__FUNC_PCM1_DI (MTK_PIN_NO(98) | 4) +-#define MT2712_PIN_98_URTS4__FUNC_I2S_IQ1_SDIB (MTK_PIN_NO(98) | 5) +-#define MT2712_PIN_98_URTS4__FUNC_I2SO1_MCK (MTK_PIN_NO(98) | 6) +-#define MT2712_PIN_98_URTS4__FUNC_DBG_MON_B_27_ (MTK_PIN_NO(98) | 7) +- +-#define MT2712_PIN_99_UTXD4__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +-#define MT2712_PIN_99_UTXD4__FUNC_UTXD4 (MTK_PIN_NO(99) | 1) +-#define MT2712_PIN_99_UTXD4__FUNC_URXD4 (MTK_PIN_NO(99) | 2) +-#define MT2712_PIN_99_UTXD4__FUNC_MRG_SYNC (MTK_PIN_NO(99) | 3) +-#define MT2712_PIN_99_UTXD4__FUNC_PCM1_SYNC (MTK_PIN_NO(99) | 4) +-#define MT2712_PIN_99_UTXD4__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(99) | 5) +-#define MT2712_PIN_99_UTXD4__FUNC_I2SO1_BCK (MTK_PIN_NO(99) | 6) +-#define MT2712_PIN_99_UTXD4__FUNC_DBG_MON_B_28_ (MTK_PIN_NO(99) | 7) +- +-#define MT2712_PIN_100_UCTS4__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +-#define MT2712_PIN_100_UCTS4__FUNC_UCTS4 (MTK_PIN_NO(100) | 1) +-#define MT2712_PIN_100_UCTS4__FUNC_URTS4 (MTK_PIN_NO(100) | 2) +-#define MT2712_PIN_100_UCTS4__FUNC_MRG_TX (MTK_PIN_NO(100) | 3) +-#define MT2712_PIN_100_UCTS4__FUNC_PCM1_DO (MTK_PIN_NO(100) | 4) +-#define MT2712_PIN_100_UCTS4__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(100) | 5) +-#define MT2712_PIN_100_UCTS4__FUNC_I2SO1_DO (MTK_PIN_NO(100) | 6) +-#define MT2712_PIN_100_UCTS4__FUNC_DBG_MON_B_29_ (MTK_PIN_NO(100) | 7) +- +-#define MT2712_PIN_101_URXD5__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +-#define MT2712_PIN_101_URXD5__FUNC_URXD5 (MTK_PIN_NO(101) | 1) +-#define MT2712_PIN_101_URXD5__FUNC_UTXD5 (MTK_PIN_NO(101) | 2) +-#define MT2712_PIN_101_URXD5__FUNC_I2SO3_WS (MTK_PIN_NO(101) | 3) +-#define MT2712_PIN_101_URXD5__FUNC_TDMIN_LRCK (MTK_PIN_NO(101) | 4) +-#define MT2712_PIN_101_URXD5__FUNC_I2SO0_WS (MTK_PIN_NO(101) | 6) +-#define MT2712_PIN_101_URXD5__FUNC_DBG_MON_B_30_ (MTK_PIN_NO(101) | 7) +- +-#define MT2712_PIN_102_URTS5__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +-#define MT2712_PIN_102_URTS5__FUNC_URTS5 (MTK_PIN_NO(102) | 1) +-#define MT2712_PIN_102_URTS5__FUNC_UCTS5 (MTK_PIN_NO(102) | 2) +-#define MT2712_PIN_102_URTS5__FUNC_I2SO3_MCK (MTK_PIN_NO(102) | 3) +-#define MT2712_PIN_102_URTS5__FUNC_TDMIN_MCLK (MTK_PIN_NO(102) | 4) +-#define MT2712_PIN_102_URTS5__FUNC_IR_IN (MTK_PIN_NO(102) | 5) +-#define MT2712_PIN_102_URTS5__FUNC_I2SO0_MCK (MTK_PIN_NO(102) | 6) +-#define MT2712_PIN_102_URTS5__FUNC_DBG_MON_B_31_ (MTK_PIN_NO(102) | 7) +- +-#define MT2712_PIN_103_UTXD5__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +-#define MT2712_PIN_103_UTXD5__FUNC_UTXD5 (MTK_PIN_NO(103) | 1) +-#define MT2712_PIN_103_UTXD5__FUNC_URXD5 (MTK_PIN_NO(103) | 2) +-#define MT2712_PIN_103_UTXD5__FUNC_I2SO3_BCK (MTK_PIN_NO(103) | 3) +-#define MT2712_PIN_103_UTXD5__FUNC_TDMIN_BCK (MTK_PIN_NO(103) | 4) +-#define MT2712_PIN_103_UTXD5__FUNC_I2SO0_BCK (MTK_PIN_NO(103) | 6) +-#define MT2712_PIN_103_UTXD5__FUNC_DBG_MON_B_32_ (MTK_PIN_NO(103) | 7) +- +-#define MT2712_PIN_104_UCTS5__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +-#define MT2712_PIN_104_UCTS5__FUNC_UCTS5 (MTK_PIN_NO(104) | 1) +-#define MT2712_PIN_104_UCTS5__FUNC_URTS5 (MTK_PIN_NO(104) | 2) +-#define MT2712_PIN_104_UCTS5__FUNC_I2SO0_DO1 (MTK_PIN_NO(104) | 3) +-#define MT2712_PIN_104_UCTS5__FUNC_TDMIN_DI (MTK_PIN_NO(104) | 4) +-#define MT2712_PIN_104_UCTS5__FUNC_IR_IN (MTK_PIN_NO(104) | 5) +-#define MT2712_PIN_104_UCTS5__FUNC_I2SO0_DO0 (MTK_PIN_NO(104) | 6) +- +-#define MT2712_PIN_105_I2C_SDA0__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +-#define MT2712_PIN_105_I2C_SDA0__FUNC_SDA0 (MTK_PIN_NO(105) | 1) +- +-#define MT2712_PIN_106_I2C_SDA1__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +-#define MT2712_PIN_106_I2C_SDA1__FUNC_SDA1 (MTK_PIN_NO(106) | 1) +- +-#define MT2712_PIN_107_I2C_SDA2__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +-#define MT2712_PIN_107_I2C_SDA2__FUNC_SDA2 (MTK_PIN_NO(107) | 1) +- +-#define MT2712_PIN_108_I2C_SDA3__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +-#define MT2712_PIN_108_I2C_SDA3__FUNC_SDA3 (MTK_PIN_NO(108) | 1) +- +-#define MT2712_PIN_109_I2C_SDA4__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +-#define MT2712_PIN_109_I2C_SDA4__FUNC_SDA4 (MTK_PIN_NO(109) | 1) +- +-#define MT2712_PIN_110_I2C_SDA5__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +-#define MT2712_PIN_110_I2C_SDA5__FUNC_SDA5 (MTK_PIN_NO(110) | 1) +- +-#define MT2712_PIN_111_I2C_SCL0__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +-#define MT2712_PIN_111_I2C_SCL0__FUNC_SCL0 (MTK_PIN_NO(111) | 1) +- +-#define MT2712_PIN_112_I2C_SCL1__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +-#define MT2712_PIN_112_I2C_SCL1__FUNC_SCL1 (MTK_PIN_NO(112) | 1) +- +-#define MT2712_PIN_113_I2C_SCL2__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +-#define MT2712_PIN_113_I2C_SCL2__FUNC_SCL2 (MTK_PIN_NO(113) | 1) +- +-#define MT2712_PIN_114_I2C_SCL3__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +-#define MT2712_PIN_114_I2C_SCL3__FUNC_SCL3 (MTK_PIN_NO(114) | 1) +- +-#define MT2712_PIN_115_I2C_SCL4__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +-#define MT2712_PIN_115_I2C_SCL4__FUNC_SCL4 (MTK_PIN_NO(115) | 1) +- +-#define MT2712_PIN_116_I2C_SCL5__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +-#define MT2712_PIN_116_I2C_SCL5__FUNC_SCL5 (MTK_PIN_NO(116) | 1) +- +-#define MT2712_PIN_117_URXD0__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +-#define MT2712_PIN_117_URXD0__FUNC_URXD0 (MTK_PIN_NO(117) | 1) +-#define MT2712_PIN_117_URXD0__FUNC_UTXD0 (MTK_PIN_NO(117) | 2) +- +-#define MT2712_PIN_118_URXD1__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +-#define MT2712_PIN_118_URXD1__FUNC_URXD1 (MTK_PIN_NO(118) | 1) +-#define MT2712_PIN_118_URXD1__FUNC_UTXD1 (MTK_PIN_NO(118) | 2) +- +-#define MT2712_PIN_119_URXD2__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +-#define MT2712_PIN_119_URXD2__FUNC_URXD2 (MTK_PIN_NO(119) | 1) +-#define MT2712_PIN_119_URXD2__FUNC_UTXD2 (MTK_PIN_NO(119) | 2) +- +-#define MT2712_PIN_120_UTXD0__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +-#define MT2712_PIN_120_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(120) | 1) +-#define MT2712_PIN_120_UTXD0__FUNC_URXD0 (MTK_PIN_NO(120) | 2) +- +-#define MT2712_PIN_121_UTXD1__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +-#define MT2712_PIN_121_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(121) | 1) +-#define MT2712_PIN_121_UTXD1__FUNC_URXD1 (MTK_PIN_NO(121) | 2) +- +-#define MT2712_PIN_122_UTXD2__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +-#define MT2712_PIN_122_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(122) | 1) +-#define MT2712_PIN_122_UTXD2__FUNC_URXD2 (MTK_PIN_NO(122) | 2) +- +-#define MT2712_PIN_123_URXD3__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +-#define MT2712_PIN_123_URXD3__FUNC_URXD3 (MTK_PIN_NO(123) | 1) +-#define MT2712_PIN_123_URXD3__FUNC_UTXD3 (MTK_PIN_NO(123) | 2) +-#define MT2712_PIN_123_URXD3__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(123) | 3) +- +-#define MT2712_PIN_124_UTXD3__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +-#define MT2712_PIN_124_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(124) | 1) +-#define MT2712_PIN_124_UTXD3__FUNC_URXD3 (MTK_PIN_NO(124) | 2) +-#define MT2712_PIN_124_UTXD3__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(124) | 3) +- +-#define MT2712_PIN_125_URTS3__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +-#define MT2712_PIN_125_URTS3__FUNC_URTS3 (MTK_PIN_NO(125) | 1) +-#define MT2712_PIN_125_URTS3__FUNC_UCTS3 (MTK_PIN_NO(125) | 2) +-#define MT2712_PIN_125_URTS3__FUNC_WATCH_DOG (MTK_PIN_NO(125) | 3) +- +-#define MT2712_PIN_126_UCTS3__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +-#define MT2712_PIN_126_UCTS3__FUNC_UCTS3 (MTK_PIN_NO(126) | 1) +-#define MT2712_PIN_126_UCTS3__FUNC_URTS3 (MTK_PIN_NO(126) | 2) +-#define MT2712_PIN_126_UCTS3__FUNC_SRCLKENA0 (MTK_PIN_NO(126) | 3) +- +-#define MT2712_PIN_127_SPI2_CSN__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +-#define MT2712_PIN_127_SPI2_CSN__FUNC_SPI_CS_2_ (MTK_PIN_NO(127) | 1) +-#define MT2712_PIN_127_SPI2_CSN__FUNC_SPI_CS_1_ (MTK_PIN_NO(127) | 2) +- +-#define MT2712_PIN_128_SPI2_MO__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +-#define MT2712_PIN_128_SPI2_MO__FUNC_SPI_MO_2_ (MTK_PIN_NO(128) | 1) +-#define MT2712_PIN_128_SPI2_MO__FUNC_SPI_SO_1_ (MTK_PIN_NO(128) | 2) +- +-#define MT2712_PIN_129_SPI2_MI__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +-#define MT2712_PIN_129_SPI2_MI__FUNC_SPI_MI_2_ (MTK_PIN_NO(129) | 1) +-#define MT2712_PIN_129_SPI2_MI__FUNC_SPI_SI_1_ (MTK_PIN_NO(129) | 2) +- +-#define MT2712_PIN_130_SPI2_CK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +-#define MT2712_PIN_130_SPI2_CK__FUNC_SPI_CK_2_ (MTK_PIN_NO(130) | 1) +-#define MT2712_PIN_130_SPI2_CK__FUNC_SPI_CK_1_ (MTK_PIN_NO(130) | 2) +- +-#define MT2712_PIN_131_SPI3_CSN__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +-#define MT2712_PIN_131_SPI3_CSN__FUNC_SPI_CS_3_ (MTK_PIN_NO(131) | 1) +- +-#define MT2712_PIN_132_SPI3_MO__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +-#define MT2712_PIN_132_SPI3_MO__FUNC_SPI_MO_3_ (MTK_PIN_NO(132) | 1) +- +-#define MT2712_PIN_133_SPI3_MI__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +-#define MT2712_PIN_133_SPI3_MI__FUNC_SPI_MI_3_ (MTK_PIN_NO(133) | 1) +- +-#define MT2712_PIN_134_SPI3_CK__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +-#define MT2712_PIN_134_SPI3_CK__FUNC_SPI_CK_3_ (MTK_PIN_NO(134) | 1) +- +-#define MT2712_PIN_135_KPROW3__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +-#define MT2712_PIN_135_KPROW3__FUNC_KROW3 (MTK_PIN_NO(135) | 1) +-#define MT2712_PIN_135_KPROW3__FUNC_DSIC_TE (MTK_PIN_NO(135) | 2) +- +-#define MT2712_PIN_136_KPROW4__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +-#define MT2712_PIN_136_KPROW4__FUNC_KROW4 (MTK_PIN_NO(136) | 1) +-#define MT2712_PIN_136_KPROW4__FUNC_DSID_TE (MTK_PIN_NO(136) | 2) +- +-#define MT2712_PIN_137_KPCOL3__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +-#define MT2712_PIN_137_KPCOL3__FUNC_KCOL3 (MTK_PIN_NO(137) | 1) +-#define MT2712_PIN_137_KPCOL3__FUNC_DISP2_PWM (MTK_PIN_NO(137) | 2) +- +-#define MT2712_PIN_138_KPCOL4__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +-#define MT2712_PIN_138_KPCOL4__FUNC_KCOL4 (MTK_PIN_NO(138) | 1) +-#define MT2712_PIN_138_KPCOL4__FUNC_LCM_RST2 (MTK_PIN_NO(138) | 2) +- +-#define MT2712_PIN_139_KPCOL5__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +-#define MT2712_PIN_139_KPCOL5__FUNC_KCOL5 (MTK_PIN_NO(139) | 1) +-#define MT2712_PIN_139_KPCOL5__FUNC_DSIA_TE (MTK_PIN_NO(139) | 3) +-#define MT2712_PIN_139_KPCOL5__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(139) | 4) +- +-#define MT2712_PIN_140_KPCOL6__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +-#define MT2712_PIN_140_KPCOL6__FUNC_KCOL6 (MTK_PIN_NO(140) | 1) +-#define MT2712_PIN_140_KPCOL6__FUNC_WATCH_DOG (MTK_PIN_NO(140) | 2) +-#define MT2712_PIN_140_KPCOL6__FUNC_LCM_RST1 (MTK_PIN_NO(140) | 3) +- +-#define MT2712_PIN_141_KPROW5__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +-#define MT2712_PIN_141_KPROW5__FUNC_KROW5 (MTK_PIN_NO(141) | 1) +-#define MT2712_PIN_141_KPROW5__FUNC_LCM_RST0 (MTK_PIN_NO(141) | 3) +-#define MT2712_PIN_141_KPROW5__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(141) | 4) +- +-#define MT2712_PIN_142_KPROW6__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +-#define MT2712_PIN_142_KPROW6__FUNC_KROW6 (MTK_PIN_NO(142) | 1) +-#define MT2712_PIN_142_KPROW6__FUNC_SRCLKENA0 (MTK_PIN_NO(142) | 2) +-#define MT2712_PIN_142_KPROW6__FUNC_DSIB_TE (MTK_PIN_NO(142) | 3) +- +-#define MT2712_PIN_143_JTDO_ICE__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +-#define MT2712_PIN_143_JTDO_ICE__FUNC_JTDO_ICE (MTK_PIN_NO(143) | 1) +-#define MT2712_PIN_143_JTDO_ICE__FUNC_DFD_TDO (MTK_PIN_NO(143) | 3) +- +-#define MT2712_PIN_144_JTCK_ICE__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +-#define MT2712_PIN_144_JTCK_ICE__FUNC_JTCK_ICE (MTK_PIN_NO(144) | 1) +-#define MT2712_PIN_144_JTCK_ICE__FUNC_DFD_TCK (MTK_PIN_NO(144) | 3) +- +-#define MT2712_PIN_145_JTDI_ICE__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +-#define MT2712_PIN_145_JTDI_ICE__FUNC_JTDI_ICE (MTK_PIN_NO(145) | 1) +-#define MT2712_PIN_145_JTDI_ICE__FUNC_DFD_TDI (MTK_PIN_NO(145) | 3) +- +-#define MT2712_PIN_146_JTMS_ICE__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +-#define MT2712_PIN_146_JTMS_ICE__FUNC_JTMS_ICE (MTK_PIN_NO(146) | 1) +-#define MT2712_PIN_146_JTMS_ICE__FUNC_DFD_TMS (MTK_PIN_NO(146) | 3) +- +-#define MT2712_PIN_147_JTRSTB_ICE__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +-#define MT2712_PIN_147_JTRSTB_ICE__FUNC_JTRST_B_ICE (MTK_PIN_NO(147) | 1) +-#define MT2712_PIN_147_JTRSTB_ICE__FUNC_DFD_NTRST (MTK_PIN_NO(147) | 3) +- +-#define MT2712_PIN_148_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +-#define MT2712_PIN_148_GPIO148__FUNC_JTRSTB_CM4 (MTK_PIN_NO(148) | 1) +-#define MT2712_PIN_148_GPIO148__FUNC_DFD_NTRST (MTK_PIN_NO(148) | 3) +- +-#define MT2712_PIN_149_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +-#define MT2712_PIN_149_GPIO149__FUNC_JTCK_CM4 (MTK_PIN_NO(149) | 1) +-#define MT2712_PIN_149_GPIO149__FUNC_DFD_TCK (MTK_PIN_NO(149) | 3) +- +-#define MT2712_PIN_150_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +-#define MT2712_PIN_150_GPIO150__FUNC_JTMS_CM4 (MTK_PIN_NO(150) | 1) +-#define MT2712_PIN_150_GPIO150__FUNC_DFD_TMS (MTK_PIN_NO(150) | 3) +- +-#define MT2712_PIN_151_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +-#define MT2712_PIN_151_GPIO151__FUNC_JTDI_CM4 (MTK_PIN_NO(151) | 1) +-#define MT2712_PIN_151_GPIO151__FUNC_DFD_TDI (MTK_PIN_NO(151) | 3) +- +-#define MT2712_PIN_152_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +-#define MT2712_PIN_152_GPIO152__FUNC_JTDO_CM4 (MTK_PIN_NO(152) | 1) +-#define MT2712_PIN_152_GPIO152__FUNC_DFD_TDO (MTK_PIN_NO(152) | 3) +- +-#define MT2712_PIN_153_SPI0_CSN__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +-#define MT2712_PIN_153_SPI0_CSN__FUNC_SPI_CS_0_ (MTK_PIN_NO(153) | 1) +-#define MT2712_PIN_153_SPI0_CSN__FUNC_SRCLKENA0 (MTK_PIN_NO(153) | 2) +-#define MT2712_PIN_153_SPI0_CSN__FUNC_UTXD0 (MTK_PIN_NO(153) | 3) +-#define MT2712_PIN_153_SPI0_CSN__FUNC_I2SO0_DO1 (MTK_PIN_NO(153) | 4) +-#define MT2712_PIN_153_SPI0_CSN__FUNC_TDMO0_DATA1 (MTK_PIN_NO(153) | 6) +-#define MT2712_PIN_153_SPI0_CSN__FUNC_I2S_IQ2_SDQB (MTK_PIN_NO(153) | 7) +- +-#define MT2712_PIN_154_SPI0_MI__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +-#define MT2712_PIN_154_SPI0_MI__FUNC_SPI_MI_0_ (MTK_PIN_NO(154) | 1) +-#define MT2712_PIN_154_SPI0_MI__FUNC_SRCLKENA0 (MTK_PIN_NO(154) | 2) +-#define MT2712_PIN_154_SPI0_MI__FUNC_URXD0 (MTK_PIN_NO(154) | 3) +-#define MT2712_PIN_154_SPI0_MI__FUNC_I2SO0_DO0 (MTK_PIN_NO(154) | 4) +-#define MT2712_PIN_154_SPI0_MI__FUNC_I2SO1_DO (MTK_PIN_NO(154) | 5) +-#define MT2712_PIN_154_SPI0_MI__FUNC_TDMO0_DATA (MTK_PIN_NO(154) | 6) +-#define MT2712_PIN_154_SPI0_MI__FUNC_I2S_IQ1_SDIB (MTK_PIN_NO(154) | 7) +- +-#define MT2712_PIN_155_SPI0_CK__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +-#define MT2712_PIN_155_SPI0_CK__FUNC_SPI_CK_0_ (MTK_PIN_NO(155) | 1) +-#define MT2712_PIN_155_SPI0_CK__FUNC_SC_APBIAS_OFF (MTK_PIN_NO(155) | 2) +-#define MT2712_PIN_155_SPI0_CK__FUNC_UTXD1 (MTK_PIN_NO(155) | 3) +-#define MT2712_PIN_155_SPI0_CK__FUNC_I2SO0_BCK (MTK_PIN_NO(155) | 4) +-#define MT2712_PIN_155_SPI0_CK__FUNC_I2SO1_BCK (MTK_PIN_NO(155) | 5) +-#define MT2712_PIN_155_SPI0_CK__FUNC_TDMO0_BCK (MTK_PIN_NO(155) | 6) +-#define MT2712_PIN_155_SPI0_CK__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(155) | 7) +- +-#define MT2712_PIN_156_SPI0_MO__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +-#define MT2712_PIN_156_SPI0_MO__FUNC_SPI_MO_0_ (MTK_PIN_NO(156) | 1) +-#define MT2712_PIN_156_SPI0_MO__FUNC_SC_APBIAS_OFF (MTK_PIN_NO(156) | 2) +-#define MT2712_PIN_156_SPI0_MO__FUNC_URXD1 (MTK_PIN_NO(156) | 3) +-#define MT2712_PIN_156_SPI0_MO__FUNC_I2SO0_WS (MTK_PIN_NO(156) | 4) +-#define MT2712_PIN_156_SPI0_MO__FUNC_I2SO1_WS (MTK_PIN_NO(156) | 5) +-#define MT2712_PIN_156_SPI0_MO__FUNC_TDMO0_LRCK (MTK_PIN_NO(156) | 6) +-#define MT2712_PIN_156_SPI0_MO__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(156) | 7) +- +-#define MT2712_PIN_157_SPI5_CSN__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +-#define MT2712_PIN_157_SPI5_CSN__FUNC_SPI_CS_5_ (MTK_PIN_NO(157) | 1) +-#define MT2712_PIN_157_SPI5_CSN__FUNC_LCM_RST0 (MTK_PIN_NO(157) | 2) +-#define MT2712_PIN_157_SPI5_CSN__FUNC_UTXD2 (MTK_PIN_NO(157) | 3) +-#define MT2712_PIN_157_SPI5_CSN__FUNC_I2SO0_MCK (MTK_PIN_NO(157) | 4) +-#define MT2712_PIN_157_SPI5_CSN__FUNC_I2SO1_MCK (MTK_PIN_NO(157) | 5) +-#define MT2712_PIN_157_SPI5_CSN__FUNC_TDMO0_MCLK (MTK_PIN_NO(157) | 6) +- +-#define MT2712_PIN_158_SPI5_MI__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +-#define MT2712_PIN_158_SPI5_MI__FUNC_SPI_MI_5_ (MTK_PIN_NO(158) | 1) +-#define MT2712_PIN_158_SPI5_MI__FUNC_DSIA_TE (MTK_PIN_NO(158) | 2) +-#define MT2712_PIN_158_SPI5_MI__FUNC_URXD2 (MTK_PIN_NO(158) | 3) +- +-#define MT2712_PIN_159_SPI5_MO__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +-#define MT2712_PIN_159_SPI5_MO__FUNC_SPI_MO_5_ (MTK_PIN_NO(159) | 1) +-#define MT2712_PIN_159_SPI5_MO__FUNC_DSIB_TE (MTK_PIN_NO(159) | 2) +-#define MT2712_PIN_159_SPI5_MO__FUNC_UTXD3 (MTK_PIN_NO(159) | 3) +- +-#define MT2712_PIN_160_SPI5_CK__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +-#define MT2712_PIN_160_SPI5_CK__FUNC_SPI_CK_5_ (MTK_PIN_NO(160) | 1) +-#define MT2712_PIN_160_SPI5_CK__FUNC_LCM_RST1 (MTK_PIN_NO(160) | 2) +-#define MT2712_PIN_160_SPI5_CK__FUNC_URXD3 (MTK_PIN_NO(160) | 3) +- +-#define MT2712_PIN_161_SPI1_CSN__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +-#define MT2712_PIN_161_SPI1_CSN__FUNC_SPI_CS_1_ (MTK_PIN_NO(161) | 1) +-#define MT2712_PIN_161_SPI1_CSN__FUNC_SPI_CS_4_ (MTK_PIN_NO(161) | 2) +-#define MT2712_PIN_161_SPI1_CSN__FUNC_I2S_IQ2_SDQB (MTK_PIN_NO(161) | 4) +-#define MT2712_PIN_161_SPI1_CSN__FUNC_I2SO2_DO (MTK_PIN_NO(161) | 5) +-#define MT2712_PIN_161_SPI1_CSN__FUNC_TDMO0_DATA1 (MTK_PIN_NO(161) | 6) +-#define MT2712_PIN_161_SPI1_CSN__FUNC_I2SO0_DO1 (MTK_PIN_NO(161) | 7) +- +-#define MT2712_PIN_162_SPI1_SI__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +-#define MT2712_PIN_162_SPI1_SI__FUNC_SPI_SI_1_ (MTK_PIN_NO(162) | 1) +-#define MT2712_PIN_162_SPI1_SI__FUNC_SPI_MI_4_ (MTK_PIN_NO(162) | 2) +-#define MT2712_PIN_162_SPI1_SI__FUNC_I2S_IQ1_SDIB (MTK_PIN_NO(162) | 4) +-#define MT2712_PIN_162_SPI1_SI__FUNC_I2SO2_BCK (MTK_PIN_NO(162) | 5) +-#define MT2712_PIN_162_SPI1_SI__FUNC_TDMO0_DATA (MTK_PIN_NO(162) | 6) +-#define MT2712_PIN_162_SPI1_SI__FUNC_I2SO0_DO0 (MTK_PIN_NO(162) | 7) +- +-#define MT2712_PIN_163_SPI1_CK__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +-#define MT2712_PIN_163_SPI1_CK__FUNC_SPI_CK_1_ (MTK_PIN_NO(163) | 1) +-#define MT2712_PIN_163_SPI1_CK__FUNC_SPI_CK_4_ (MTK_PIN_NO(163) | 2) +-#define MT2712_PIN_163_SPI1_CK__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(163) | 4) +-#define MT2712_PIN_163_SPI1_CK__FUNC_I2SO2_WS (MTK_PIN_NO(163) | 5) +-#define MT2712_PIN_163_SPI1_CK__FUNC_TDMO0_BCK (MTK_PIN_NO(163) | 6) +-#define MT2712_PIN_163_SPI1_CK__FUNC_I2SO0_BCK (MTK_PIN_NO(163) | 7) +- +-#define MT2712_PIN_164_SPI1_SO__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +-#define MT2712_PIN_164_SPI1_SO__FUNC_SPI_SO_1_ (MTK_PIN_NO(164) | 1) +-#define MT2712_PIN_164_SPI1_SO__FUNC_SPI_MO_4_ (MTK_PIN_NO(164) | 2) +-#define MT2712_PIN_164_SPI1_SO__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(164) | 4) +-#define MT2712_PIN_164_SPI1_SO__FUNC_I2SO2_MCK (MTK_PIN_NO(164) | 5) +-#define MT2712_PIN_164_SPI1_SO__FUNC_TDMO0_LRCK (MTK_PIN_NO(164) | 6) +-#define MT2712_PIN_164_SPI1_SO__FUNC_I2SO0_WS (MTK_PIN_NO(164) | 7) +- +-#define MT2712_PIN_165_SPI4_CSN__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +-#define MT2712_PIN_165_SPI4_CSN__FUNC_SPI_CS_4_ (MTK_PIN_NO(165) | 1) +-#define MT2712_PIN_165_SPI4_CSN__FUNC_LCM_RST0 (MTK_PIN_NO(165) | 2) +-#define MT2712_PIN_165_SPI4_CSN__FUNC_SPI_CS_1_ (MTK_PIN_NO(165) | 3) +-#define MT2712_PIN_165_SPI4_CSN__FUNC_UTXD4 (MTK_PIN_NO(165) | 4) +-#define MT2712_PIN_165_SPI4_CSN__FUNC_I2SO1_DO (MTK_PIN_NO(165) | 5) +-#define MT2712_PIN_165_SPI4_CSN__FUNC_TDMO0_MCLK (MTK_PIN_NO(165) | 6) +-#define MT2712_PIN_165_SPI4_CSN__FUNC_I2SO0_MCK (MTK_PIN_NO(165) | 7) +- +-#define MT2712_PIN_166_SPI4_MI__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +-#define MT2712_PIN_166_SPI4_MI__FUNC_SPI_MI_4_ (MTK_PIN_NO(166) | 1) +-#define MT2712_PIN_166_SPI4_MI__FUNC_DSIA_TE (MTK_PIN_NO(166) | 2) +-#define MT2712_PIN_166_SPI4_MI__FUNC_SPI_SI_1_ (MTK_PIN_NO(166) | 3) +-#define MT2712_PIN_166_SPI4_MI__FUNC_URXD4 (MTK_PIN_NO(166) | 4) +-#define MT2712_PIN_166_SPI4_MI__FUNC_I2SO1_BCK (MTK_PIN_NO(166) | 5) +- +-#define MT2712_PIN_167_SPI4_MO__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +-#define MT2712_PIN_167_SPI4_MO__FUNC_SPI_MO_4_ (MTK_PIN_NO(167) | 1) +-#define MT2712_PIN_167_SPI4_MO__FUNC_DSIB_TE (MTK_PIN_NO(167) | 2) +-#define MT2712_PIN_167_SPI4_MO__FUNC_SPI_SO_1_ (MTK_PIN_NO(167) | 3) +-#define MT2712_PIN_167_SPI4_MO__FUNC_UTXD5 (MTK_PIN_NO(167) | 4) +-#define MT2712_PIN_167_SPI4_MO__FUNC_I2SO1_WS (MTK_PIN_NO(167) | 5) +- +-#define MT2712_PIN_168_SPI4_CK__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +-#define MT2712_PIN_168_SPI4_CK__FUNC_SPI_CK_4_ (MTK_PIN_NO(168) | 1) +-#define MT2712_PIN_168_SPI4_CK__FUNC_LCM_RST1 (MTK_PIN_NO(168) | 2) +-#define MT2712_PIN_168_SPI4_CK__FUNC_SPI_CK_1_ (MTK_PIN_NO(168) | 3) +-#define MT2712_PIN_168_SPI4_CK__FUNC_URXD5 (MTK_PIN_NO(168) | 4) +-#define MT2712_PIN_168_SPI4_CK__FUNC_I2SO1_MCK (MTK_PIN_NO(168) | 5) +- +-#define MT2712_PIN_169_I2SI0_DATA__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +-#define MT2712_PIN_169_I2SI0_DATA__FUNC_I2SI0_DI (MTK_PIN_NO(169) | 1) +-#define MT2712_PIN_169_I2SI0_DATA__FUNC_I2SI1_DI (MTK_PIN_NO(169) | 2) +-#define MT2712_PIN_169_I2SI0_DATA__FUNC_I2SI2_DI (MTK_PIN_NO(169) | 3) +-#define MT2712_PIN_169_I2SI0_DATA__FUNC_TDMIN_DI (MTK_PIN_NO(169) | 4) +- +-#define MT2712_PIN_170_I2SI0_LRCK__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +-#define MT2712_PIN_170_I2SI0_LRCK__FUNC_I2SI0_WS (MTK_PIN_NO(170) | 1) +-#define MT2712_PIN_170_I2SI0_LRCK__FUNC_I2SI1_WS (MTK_PIN_NO(170) | 2) +-#define MT2712_PIN_170_I2SI0_LRCK__FUNC_I2SI2_WS (MTK_PIN_NO(170) | 3) +-#define MT2712_PIN_170_I2SI0_LRCK__FUNC_TDMIN_LRCK (MTK_PIN_NO(170) | 4) +-#define MT2712_PIN_170_I2SI0_LRCK__FUNC_TDMO0_DATA3 (MTK_PIN_NO(170) | 5) +-#define MT2712_PIN_170_I2SI0_LRCK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(170) | 6) +- +-#define MT2712_PIN_171_I2SI0_MCLK__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +-#define MT2712_PIN_171_I2SI0_MCLK__FUNC_I2SI0_MCK (MTK_PIN_NO(171) | 1) +-#define MT2712_PIN_171_I2SI0_MCLK__FUNC_I2SI1_MCK (MTK_PIN_NO(171) | 2) +-#define MT2712_PIN_171_I2SI0_MCLK__FUNC_I2SI2_MCK (MTK_PIN_NO(171) | 3) +-#define MT2712_PIN_171_I2SI0_MCLK__FUNC_TDMIN_MCLK (MTK_PIN_NO(171) | 4) +-#define MT2712_PIN_171_I2SI0_MCLK__FUNC_TDMO0_DATA2 (MTK_PIN_NO(171) | 5) +-#define MT2712_PIN_171_I2SI0_MCLK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(171) | 6) +- +-#define MT2712_PIN_172_I2SI0_BCK__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +-#define MT2712_PIN_172_I2SI0_BCK__FUNC_I2SI0_BCK (MTK_PIN_NO(172) | 1) +-#define MT2712_PIN_172_I2SI0_BCK__FUNC_I2SI1_BCK (MTK_PIN_NO(172) | 2) +-#define MT2712_PIN_172_I2SI0_BCK__FUNC_I2SI2_BCK (MTK_PIN_NO(172) | 3) +-#define MT2712_PIN_172_I2SI0_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(172) | 4) +-#define MT2712_PIN_172_I2SI0_BCK__FUNC_TDMO0_DATA1 (MTK_PIN_NO(172) | 5) +-#define MT2712_PIN_172_I2SI0_BCK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(172) | 6) +- +-#define MT2712_PIN_173_I2SI2_DATA__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +-#define MT2712_PIN_173_I2SI2_DATA__FUNC_I2SI2_DI (MTK_PIN_NO(173) | 1) +-#define MT2712_PIN_173_I2SI2_DATA__FUNC_I2SI0_DI (MTK_PIN_NO(173) | 2) +-#define MT2712_PIN_173_I2SI2_DATA__FUNC_I2SI1_DI (MTK_PIN_NO(173) | 3) +-#define MT2712_PIN_173_I2SI2_DATA__FUNC_PCM1_DI (MTK_PIN_NO(173) | 4) +-#define MT2712_PIN_173_I2SI2_DATA__FUNC_TDMIN_DI (MTK_PIN_NO(173) | 5) +-#define MT2712_PIN_173_I2SI2_DATA__FUNC_PCM1_DO (MTK_PIN_NO(173) | 6) +- +-#define MT2712_PIN_174_I2SI2_MCLK__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +-#define MT2712_PIN_174_I2SI2_MCLK__FUNC_I2SI2_MCK (MTK_PIN_NO(174) | 1) +-#define MT2712_PIN_174_I2SI2_MCLK__FUNC_I2SI0_MCK (MTK_PIN_NO(174) | 2) +-#define MT2712_PIN_174_I2SI2_MCLK__FUNC_I2SI1_MCK (MTK_PIN_NO(174) | 3) +-#define MT2712_PIN_174_I2SI2_MCLK__FUNC_PCM1_DO (MTK_PIN_NO(174) | 4) +-#define MT2712_PIN_174_I2SI2_MCLK__FUNC_TDMIN_MCLK (MTK_PIN_NO(174) | 5) +-#define MT2712_PIN_174_I2SI2_MCLK__FUNC_PCM1_DI (MTK_PIN_NO(174) | 6) +-#define MT2712_PIN_174_I2SI2_MCLK__FUNC_I2S_IQ2_SDQB (MTK_PIN_NO(174) | 7) +- +-#define MT2712_PIN_175_I2SI2_BCK__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +-#define MT2712_PIN_175_I2SI2_BCK__FUNC_I2SI2_BCK (MTK_PIN_NO(175) | 1) +-#define MT2712_PIN_175_I2SI2_BCK__FUNC_I2SI0_BCK (MTK_PIN_NO(175) | 2) +-#define MT2712_PIN_175_I2SI2_BCK__FUNC_I2SI1_BCK (MTK_PIN_NO(175) | 3) +-#define MT2712_PIN_175_I2SI2_BCK__FUNC_PCM1_CLK (MTK_PIN_NO(175) | 4) +-#define MT2712_PIN_175_I2SI2_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(175) | 5) +- +-#define MT2712_PIN_176_I2SI2_LRCK__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +-#define MT2712_PIN_176_I2SI2_LRCK__FUNC_I2SI2_WS (MTK_PIN_NO(176) | 1) +-#define MT2712_PIN_176_I2SI2_LRCK__FUNC_I2SI0_WS (MTK_PIN_NO(176) | 2) +-#define MT2712_PIN_176_I2SI2_LRCK__FUNC_I2SI1_WS (MTK_PIN_NO(176) | 3) +-#define MT2712_PIN_176_I2SI2_LRCK__FUNC_PCM1_SYNC (MTK_PIN_NO(176) | 4) +-#define MT2712_PIN_176_I2SI2_LRCK__FUNC_TDMIN_LRCK (MTK_PIN_NO(176) | 5) +- +-#define MT2712_PIN_177_I2SI1_DATA__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +-#define MT2712_PIN_177_I2SI1_DATA__FUNC_I2SI1_DI (MTK_PIN_NO(177) | 1) +-#define MT2712_PIN_177_I2SI1_DATA__FUNC_I2SI0_DI (MTK_PIN_NO(177) | 2) +-#define MT2712_PIN_177_I2SI1_DATA__FUNC_I2SI2_DI (MTK_PIN_NO(177) | 3) +-#define MT2712_PIN_177_I2SI1_DATA__FUNC_TDMIN_DI (MTK_PIN_NO(177) | 4) +- +-#define MT2712_PIN_178_I2SI1_BCK__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +-#define MT2712_PIN_178_I2SI1_BCK__FUNC_I2SI1_BCK (MTK_PIN_NO(178) | 1) +-#define MT2712_PIN_178_I2SI1_BCK__FUNC_I2SI0_BCK (MTK_PIN_NO(178) | 2) +-#define MT2712_PIN_178_I2SI1_BCK__FUNC_I2SI2_BCK (MTK_PIN_NO(178) | 3) +-#define MT2712_PIN_178_I2SI1_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(178) | 4) +-#define MT2712_PIN_178_I2SI1_BCK__FUNC_TDMO0_DATA3 (MTK_PIN_NO(178) | 5) +-#define MT2712_PIN_178_I2SI1_BCK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(178) | 6) +- +-#define MT2712_PIN_179_I2SI1_LRCK__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +-#define MT2712_PIN_179_I2SI1_LRCK__FUNC_I2SI1_WS (MTK_PIN_NO(179) | 1) +-#define MT2712_PIN_179_I2SI1_LRCK__FUNC_I2SI0_WS (MTK_PIN_NO(179) | 2) +-#define MT2712_PIN_179_I2SI1_LRCK__FUNC_I2SI2_WS (MTK_PIN_NO(179) | 3) +-#define MT2712_PIN_179_I2SI1_LRCK__FUNC_TDMIN_LRCK (MTK_PIN_NO(179) | 4) +-#define MT2712_PIN_179_I2SI1_LRCK__FUNC_TDMO0_DATA2 (MTK_PIN_NO(179) | 5) +-#define MT2712_PIN_179_I2SI1_LRCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(179) | 6) +- +-#define MT2712_PIN_180_I2SI1_MCLK__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +-#define MT2712_PIN_180_I2SI1_MCLK__FUNC_I2SI1_MCK (MTK_PIN_NO(180) | 1) +-#define MT2712_PIN_180_I2SI1_MCLK__FUNC_I2SI0_MCK (MTK_PIN_NO(180) | 2) +-#define MT2712_PIN_180_I2SI1_MCLK__FUNC_I2SI2_MCK (MTK_PIN_NO(180) | 3) +-#define MT2712_PIN_180_I2SI1_MCLK__FUNC_TDMIN_MCLK (MTK_PIN_NO(180) | 4) +-#define MT2712_PIN_180_I2SI1_MCLK__FUNC_TDMO0_DATA1 (MTK_PIN_NO(180) | 5) +-#define MT2712_PIN_180_I2SI1_MCLK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(180) | 6) +-#define MT2712_PIN_180_I2SI1_MCLK__FUNC_I2S_IQ2_SDIB (MTK_PIN_NO(180) | 7) +- +-#define MT2712_PIN_181_I2SO1_DATA0__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +-#define MT2712_PIN_181_I2SO1_DATA0__FUNC_I2SO1_DO (MTK_PIN_NO(181) | 1) +-#define MT2712_PIN_181_I2SO1_DATA0__FUNC_I2SO0_DO0 (MTK_PIN_NO(181) | 2) +-#define MT2712_PIN_181_I2SO1_DATA0__FUNC_I2SO2_DO (MTK_PIN_NO(181) | 3) +-#define MT2712_PIN_181_I2SO1_DATA0__FUNC_DAI_TX (MTK_PIN_NO(181) | 4) +-#define MT2712_PIN_181_I2SO1_DATA0__FUNC_TDMIN_MCLK (MTK_PIN_NO(181) | 5) +-#define MT2712_PIN_181_I2SO1_DATA0__FUNC_I2S_IQ2_SDIA (MTK_PIN_NO(181) | 7) +- +-#define MT2712_PIN_182_I2SO1_BCK__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +-#define MT2712_PIN_182_I2SO1_BCK__FUNC_I2SO1_BCK (MTK_PIN_NO(182) | 1) +-#define MT2712_PIN_182_I2SO1_BCK__FUNC_I2SO0_BCK (MTK_PIN_NO(182) | 2) +-#define MT2712_PIN_182_I2SO1_BCK__FUNC_I2SO2_BCK (MTK_PIN_NO(182) | 3) +-#define MT2712_PIN_182_I2SO1_BCK__FUNC_DAI_SYNC (MTK_PIN_NO(182) | 4) +-#define MT2712_PIN_182_I2SO1_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(182) | 5) +-#define MT2712_PIN_182_I2SO1_BCK__FUNC_TDMO0_DATA3 (MTK_PIN_NO(182) | 6) +-#define MT2712_PIN_182_I2SO1_BCK__FUNC_I2S_IQ2_BCK (MTK_PIN_NO(182) | 7) +- +-#define MT2712_PIN_183_I2SO1_LRCK__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +-#define MT2712_PIN_183_I2SO1_LRCK__FUNC_I2SO1_WS (MTK_PIN_NO(183) | 1) +-#define MT2712_PIN_183_I2SO1_LRCK__FUNC_I2SO0_WS (MTK_PIN_NO(183) | 2) +-#define MT2712_PIN_183_I2SO1_LRCK__FUNC_I2SO2_WS (MTK_PIN_NO(183) | 3) +-#define MT2712_PIN_183_I2SO1_LRCK__FUNC_DAI_CLK (MTK_PIN_NO(183) | 4) +-#define MT2712_PIN_183_I2SO1_LRCK__FUNC_TDMIN_DI (MTK_PIN_NO(183) | 5) +-#define MT2712_PIN_183_I2SO1_LRCK__FUNC_TDMO0_DATA2 (MTK_PIN_NO(183) | 6) +-#define MT2712_PIN_183_I2SO1_LRCK__FUNC_I2S_IQ2_WS (MTK_PIN_NO(183) | 7) +- +-#define MT2712_PIN_184_I2SO1_MCLK__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +-#define MT2712_PIN_184_I2SO1_MCLK__FUNC_I2SO1_MCK (MTK_PIN_NO(184) | 1) +-#define MT2712_PIN_184_I2SO1_MCLK__FUNC_I2SO0_MCK (MTK_PIN_NO(184) | 2) +-#define MT2712_PIN_184_I2SO1_MCLK__FUNC_I2SO2_MCK (MTK_PIN_NO(184) | 3) +-#define MT2712_PIN_184_I2SO1_MCLK__FUNC_DAI_RX (MTK_PIN_NO(184) | 4) +-#define MT2712_PIN_184_I2SO1_MCLK__FUNC_TDMIN_LRCK (MTK_PIN_NO(184) | 5) +-#define MT2712_PIN_184_I2SO1_MCLK__FUNC_TDMO0_DATA1 (MTK_PIN_NO(184) | 6) +-#define MT2712_PIN_184_I2SO1_MCLK__FUNC_I2S_IQ2_SDQA (MTK_PIN_NO(184) | 7) +- +-#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +-#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(185) | 1) +-#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(185) | 2) +-#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_I2SO1_DO (MTK_PIN_NO(185) | 3) +-#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_I2SI2_DI (MTK_PIN_NO(185) | 4) +-#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_MRG_RX (MTK_PIN_NO(185) | 5) +-#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_PCM1_DI (MTK_PIN_NO(185) | 6) +-#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(185) | 7) +- +-#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +-#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(186) | 1) +-#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(186) | 2) +-#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_I2SO0_DO1 (MTK_PIN_NO(186) | 3) +-#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_I2SI1_DI (MTK_PIN_NO(186) | 4) +-#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_MRG_TX (MTK_PIN_NO(186) | 5) +-#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_PCM1_DO (MTK_PIN_NO(186) | 6) +-#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(186) | 7) +- +-#define MT2712_PIN_187_I2SO2_BCK__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +-#define MT2712_PIN_187_I2SO2_BCK__FUNC_I2SO2_BCK (MTK_PIN_NO(187) | 1) +-#define MT2712_PIN_187_I2SO2_BCK__FUNC_I2SO0_BCK (MTK_PIN_NO(187) | 2) +-#define MT2712_PIN_187_I2SO2_BCK__FUNC_I2SO1_BCK (MTK_PIN_NO(187) | 3) +-#define MT2712_PIN_187_I2SO2_BCK__FUNC_PCM1_CLK (MTK_PIN_NO(187) | 4) +-#define MT2712_PIN_187_I2SO2_BCK__FUNC_MRG_SYNC (MTK_PIN_NO(187) | 5) +-#define MT2712_PIN_187_I2SO2_BCK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(187) | 6) +-#define MT2712_PIN_187_I2SO2_BCK__FUNC_I2S_IQ0_BCK (MTK_PIN_NO(187) | 7) +- +-#define MT2712_PIN_188_I2SO2_LRCK__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +-#define MT2712_PIN_188_I2SO2_LRCK__FUNC_I2SO2_WS (MTK_PIN_NO(188) | 1) +-#define MT2712_PIN_188_I2SO2_LRCK__FUNC_I2SO0_WS (MTK_PIN_NO(188) | 2) +-#define MT2712_PIN_188_I2SO2_LRCK__FUNC_I2SO1_WS (MTK_PIN_NO(188) | 3) +-#define MT2712_PIN_188_I2SO2_LRCK__FUNC_PCM1_SYNC (MTK_PIN_NO(188) | 4) +-#define MT2712_PIN_188_I2SO2_LRCK__FUNC_MRG_CLK (MTK_PIN_NO(188) | 5) +-#define MT2712_PIN_188_I2SO2_LRCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(188) | 6) +-#define MT2712_PIN_188_I2SO2_LRCK__FUNC_I2S_IQ0_WS (MTK_PIN_NO(188) | 7) +- +-#define MT2712_PIN_189_I2SO2_MCLK__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +-#define MT2712_PIN_189_I2SO2_MCLK__FUNC_I2SO2_MCK (MTK_PIN_NO(189) | 1) +-#define MT2712_PIN_189_I2SO2_MCLK__FUNC_I2SO0_MCK (MTK_PIN_NO(189) | 2) +-#define MT2712_PIN_189_I2SO2_MCLK__FUNC_I2SO1_MCK (MTK_PIN_NO(189) | 3) +-#define MT2712_PIN_189_I2SO2_MCLK__FUNC_PCM1_DO (MTK_PIN_NO(189) | 4) +-#define MT2712_PIN_189_I2SO2_MCLK__FUNC_MRG_RX (MTK_PIN_NO(189) | 5) +-#define MT2712_PIN_189_I2SO2_MCLK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(189) | 6) +-#define MT2712_PIN_189_I2SO2_MCLK__FUNC_I2S_IQ0_SDQA (MTK_PIN_NO(189) | 7) +- +-#define MT2712_PIN_190_I2SO2_DATA0__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +-#define MT2712_PIN_190_I2SO2_DATA0__FUNC_I2SO2_DO (MTK_PIN_NO(190) | 1) +-#define MT2712_PIN_190_I2SO2_DATA0__FUNC_I2SO0_DO0 (MTK_PIN_NO(190) | 2) +-#define MT2712_PIN_190_I2SO2_DATA0__FUNC_I2SO1_DO (MTK_PIN_NO(190) | 3) +-#define MT2712_PIN_190_I2SO2_DATA0__FUNC_PCM1_DI (MTK_PIN_NO(190) | 4) +-#define MT2712_PIN_190_I2SO2_DATA0__FUNC_MRG_TX (MTK_PIN_NO(190) | 5) +-#define MT2712_PIN_190_I2SO2_DATA0__FUNC_PCM1_DO (MTK_PIN_NO(190) | 6) +-#define MT2712_PIN_190_I2SO2_DATA0__FUNC_I2S_IQ0_SDIA (MTK_PIN_NO(190) | 7) +- +-#define MT2712_PIN_191_I2SO0_DATA1__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +-#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2SO0_DO1 (MTK_PIN_NO(191) | 1) +-#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2SI0_DI (MTK_PIN_NO(191) | 2) +-#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2SI1_DI (MTK_PIN_NO(191) | 3) +-#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2SI2_DI (MTK_PIN_NO(191) | 4) +-#define MT2712_PIN_191_I2SO0_DATA1__FUNC_DAI_TX (MTK_PIN_NO(191) | 5) +-#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(191) | 6) +-#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2S_IQ1_SDQB (MTK_PIN_NO(191) | 7) +- +-#define MT2712_PIN_192_I2SO0_MCLK__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +-#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2SO0_MCK (MTK_PIN_NO(192) | 1) +-#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2SO1_MCK (MTK_PIN_NO(192) | 2) +-#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2SO2_MCK (MTK_PIN_NO(192) | 3) +-#define MT2712_PIN_192_I2SO0_MCLK__FUNC_USB4_FT_SCL (MTK_PIN_NO(192) | 4) +-#define MT2712_PIN_192_I2SO0_MCLK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(192) | 5) +-#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(192) | 6) +-#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2S_IQ1_SDQA (MTK_PIN_NO(192) | 7) +- +-#define MT2712_PIN_193_I2SO0_DATA0__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +-#define MT2712_PIN_193_I2SO0_DATA0__FUNC_I2SO0_DO0 (MTK_PIN_NO(193) | 1) +-#define MT2712_PIN_193_I2SO0_DATA0__FUNC_I2SO1_DO (MTK_PIN_NO(193) | 2) +-#define MT2712_PIN_193_I2SO0_DATA0__FUNC_I2SO2_DO (MTK_PIN_NO(193) | 3) +-#define MT2712_PIN_193_I2SO0_DATA0__FUNC_USB4_FT_SDA (MTK_PIN_NO(193) | 4) +-#define MT2712_PIN_193_I2SO0_DATA0__FUNC_I2S_IQ1_SDIA (MTK_PIN_NO(193) | 7) +- +-#define MT2712_PIN_194_I2SO0_LRCK__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +-#define MT2712_PIN_194_I2SO0_LRCK__FUNC_I2SO0_WS (MTK_PIN_NO(194) | 1) +-#define MT2712_PIN_194_I2SO0_LRCK__FUNC_I2SO1_WS (MTK_PIN_NO(194) | 2) +-#define MT2712_PIN_194_I2SO0_LRCK__FUNC_I2SO2_WS (MTK_PIN_NO(194) | 3) +-#define MT2712_PIN_194_I2SO0_LRCK__FUNC_USB5_FT_SCL (MTK_PIN_NO(194) | 4) +-#define MT2712_PIN_194_I2SO0_LRCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(194) | 5) +-#define MT2712_PIN_194_I2SO0_LRCK__FUNC_I2S_IQ1_WS (MTK_PIN_NO(194) | 7) +- +-#define MT2712_PIN_195_I2SO0_BCK__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +-#define MT2712_PIN_195_I2SO0_BCK__FUNC_I2SO0_BCK (MTK_PIN_NO(195) | 1) +-#define MT2712_PIN_195_I2SO0_BCK__FUNC_I2SO1_BCK (MTK_PIN_NO(195) | 2) +-#define MT2712_PIN_195_I2SO0_BCK__FUNC_I2SO2_BCK (MTK_PIN_NO(195) | 3) +-#define MT2712_PIN_195_I2SO0_BCK__FUNC_USB5_FT_SDA (MTK_PIN_NO(195) | 4) +-#define MT2712_PIN_195_I2SO0_BCK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(195) | 5) +-#define MT2712_PIN_195_I2SO0_BCK__FUNC_I2S_IQ1_BCK (MTK_PIN_NO(195) | 7) +- +-#define MT2712_PIN_196_TDMO1_MCLK__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +-#define MT2712_PIN_196_TDMO1_MCLK__FUNC_TDMO1_MCLK (MTK_PIN_NO(196) | 1) +-#define MT2712_PIN_196_TDMO1_MCLK__FUNC_TDMO0_MCLK (MTK_PIN_NO(196) | 2) +-#define MT2712_PIN_196_TDMO1_MCLK__FUNC_TDMIN_MCLK (MTK_PIN_NO(196) | 3) +-#define MT2712_PIN_196_TDMO1_MCLK__FUNC_I2SO0_DO1 (MTK_PIN_NO(196) | 6) +-#define MT2712_PIN_196_TDMO1_MCLK__FUNC_I2S_IQ1_SDIB (MTK_PIN_NO(196) | 7) +- +-#define MT2712_PIN_197_TDMO1_LRCK__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +-#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO1_LRCK (MTK_PIN_NO(197) | 1) +-#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO0_LRCK (MTK_PIN_NO(197) | 2) +-#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMIN_LRCK (MTK_PIN_NO(197) | 3) +-#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO0_DATA3 (MTK_PIN_NO(197) | 4) +-#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(197) | 5) +-#define MT2712_PIN_197_TDMO1_LRCK__FUNC_I2SO3_MCK (MTK_PIN_NO(197) | 6) +-#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(197) | 7) +- +-#define MT2712_PIN_198_TDMO1_BCK__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +-#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO1_BCK (MTK_PIN_NO(198) | 1) +-#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO0_BCK (MTK_PIN_NO(198) | 2) +-#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(198) | 3) +-#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO0_DATA2 (MTK_PIN_NO(198) | 4) +-#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(198) | 5) +-#define MT2712_PIN_198_TDMO1_BCK__FUNC_I2SO3_BCK (MTK_PIN_NO(198) | 6) +-#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(198) | 7) +- +-#define MT2712_PIN_199_TDMO1_DATA__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +-#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMO1_DATA (MTK_PIN_NO(199) | 1) +-#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMO0_DATA (MTK_PIN_NO(199) | 2) +-#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMIN_DI (MTK_PIN_NO(199) | 3) +-#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMO0_DATA1 (MTK_PIN_NO(199) | 4) +-#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMO1_DATA1 (MTK_PIN_NO(199) | 5) +-#define MT2712_PIN_199_TDMO1_DATA__FUNC_I2SO3_WS (MTK_PIN_NO(199) | 6) +- +-#define MT2712_PIN_200_TDMO0_MCLK__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +-#define MT2712_PIN_200_TDMO0_MCLK__FUNC_TDMO0_MCLK0 (MTK_PIN_NO(200) | 1) +-#define MT2712_PIN_200_TDMO0_MCLK__FUNC_TDMO1_MCLK0 (MTK_PIN_NO(200) | 2) +-#define MT2712_PIN_200_TDMO0_MCLK__FUNC_PCM1_DI (MTK_PIN_NO(200) | 3) +-#define MT2712_PIN_200_TDMO0_MCLK__FUNC_TDMO0_MCLK1 (MTK_PIN_NO(200) | 4) +-#define MT2712_PIN_200_TDMO0_MCLK__FUNC_TDMO1_MCLK1 (MTK_PIN_NO(200) | 5) +-#define MT2712_PIN_200_TDMO0_MCLK__FUNC_MRG_TX (MTK_PIN_NO(200) | 6) +-#define MT2712_PIN_200_TDMO0_MCLK__FUNC_I2SO2_MCK (MTK_PIN_NO(200) | 7) +- +-#define MT2712_PIN_201_TDMO0_LRCK__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +-#define MT2712_PIN_201_TDMO0_LRCK__FUNC_TDMO0_LRCK0 (MTK_PIN_NO(201) | 1) +-#define MT2712_PIN_201_TDMO0_LRCK__FUNC_TDMO1_LRCK0 (MTK_PIN_NO(201) | 2) +-#define MT2712_PIN_201_TDMO0_LRCK__FUNC_PCM1_SYNC (MTK_PIN_NO(201) | 3) +-#define MT2712_PIN_201_TDMO0_LRCK__FUNC_TDMO0_LRCK1 (MTK_PIN_NO(201) | 4) +-#define MT2712_PIN_201_TDMO0_LRCK__FUNC_TDMO1_LRCK1 (MTK_PIN_NO(201) | 5) +-#define MT2712_PIN_201_TDMO0_LRCK__FUNC_MRG_RX (MTK_PIN_NO(201) | 6) +-#define MT2712_PIN_201_TDMO0_LRCK__FUNC_I2SO2_WS (MTK_PIN_NO(201) | 7) +- +-#define MT2712_PIN_202_TDMO0_BCK__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +-#define MT2712_PIN_202_TDMO0_BCK__FUNC_TDMO0_BCK0 (MTK_PIN_NO(202) | 1) +-#define MT2712_PIN_202_TDMO0_BCK__FUNC_TDMO1_BCK0 (MTK_PIN_NO(202) | 2) +-#define MT2712_PIN_202_TDMO0_BCK__FUNC_PCM1_CLK (MTK_PIN_NO(202) | 3) +-#define MT2712_PIN_202_TDMO0_BCK__FUNC_TDMO0_BCK1 (MTK_PIN_NO(202) | 4) +-#define MT2712_PIN_202_TDMO0_BCK__FUNC_TDMO1_BCK1 (MTK_PIN_NO(202) | 5) +-#define MT2712_PIN_202_TDMO0_BCK__FUNC_MRG_SYNC (MTK_PIN_NO(202) | 6) +-#define MT2712_PIN_202_TDMO0_BCK__FUNC_I2SO2_BCK (MTK_PIN_NO(202) | 7) +- +-#define MT2712_PIN_203_TDMO0_DATA__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) +-#define MT2712_PIN_203_TDMO0_DATA__FUNC_TDMO0_DATA0 (MTK_PIN_NO(203) | 1) +-#define MT2712_PIN_203_TDMO0_DATA__FUNC_TDMO1_DATA0 (MTK_PIN_NO(203) | 2) +-#define MT2712_PIN_203_TDMO0_DATA__FUNC_PCM1_DO (MTK_PIN_NO(203) | 3) +-#define MT2712_PIN_203_TDMO0_DATA__FUNC_TDMO0_DATA1 (MTK_PIN_NO(203) | 4) +-#define MT2712_PIN_203_TDMO0_DATA__FUNC_TDMO1_DATA1 (MTK_PIN_NO(203) | 5) +-#define MT2712_PIN_203_TDMO0_DATA__FUNC_MRG_CLK (MTK_PIN_NO(203) | 6) +-#define MT2712_PIN_203_TDMO0_DATA__FUNC_I2SO2_DO (MTK_PIN_NO(203) | 7) +- +-#define MT2712_PIN_204_PERSTB_P0__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) +-#define MT2712_PIN_204_PERSTB_P0__FUNC_PERST_B_P0 (MTK_PIN_NO(204) | 1) +- +-#define MT2712_PIN_205_CLKREQN_P0__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) +-#define MT2712_PIN_205_CLKREQN_P0__FUNC_CLKREQ_N_P0 (MTK_PIN_NO(205) | 1) +- +-#define MT2712_PIN_206_WAKEEN_P0__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) +-#define MT2712_PIN_206_WAKEEN_P0__FUNC_WAKE_EN_P0 (MTK_PIN_NO(206) | 1) +- +-#define MT2712_PIN_207_PERSTB_P1__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) +-#define MT2712_PIN_207_PERSTB_P1__FUNC_PERST_B_P1 (MTK_PIN_NO(207) | 1) +- +-#define MT2712_PIN_208_CLKREQN_P1__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) +-#define MT2712_PIN_208_CLKREQN_P1__FUNC_CLKREQ_N_P1 (MTK_PIN_NO(208) | 1) +- +-#define MT2712_PIN_209_WAKEEN_P1__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) +-#define MT2712_PIN_209_WAKEEN_P1__FUNC_WAKE_EN_P1 (MTK_PIN_NO(209) | 1) +- +-#endif /* __DTS_MT2712_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt2712e.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt2712e.dtsi +deleted file mode 100644 +index a9cca9c146fd..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt2712e.dtsi ++++ /dev/null +@@ -1,1127 +0,0 @@ +-/* +- * Copyright (c) 2017 MediaTek Inc. +- * Author: YT Shen +- * +- * SPDX-License-Identifier: (GPL-2.0 OR MIT) +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include "mt2712-pinfunc.h" +- +-/ { +- compatible = "mediatek,mt2712"; +- interrupt-parent = <&sysirq>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cluster0_opp: opp_table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- opp00 { +- opp-hz = /bits/ 64 <598000000>; +- opp-microvolt = <1000000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <702000000>; +- opp-microvolt = <1000000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <793000000>; +- opp-microvolt = <1000000>; +- }; +- }; +- +- cluster1_opp: opp_table1 { +- compatible = "operating-points-v2"; +- opp-shared; +- opp00 { +- opp-hz = /bits/ 64 <598000000>; +- opp-microvolt = <1000000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <702000000>; +- opp-microvolt = <1000000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <793000000>; +- opp-microvolt = <1000000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <897000000>; +- opp-microvolt = <1000000>; +- }; +- opp04 { +- opp-hz = /bits/ 64 <1001000000>; +- opp-microvolt = <1000000>; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&cpu2>; +- }; +- }; +- }; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x000>; +- clocks = <&mcucfg CLK_MCU_MP0_SEL>, +- <&topckgen CLK_TOP_F_MP0_PLL1>; +- clock-names = "cpu", "intermediate"; +- proc-supply = <&cpus_fixed_vproc0>; +- operating-points-v2 = <&cluster0_opp>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x001>; +- enable-method = "psci"; +- clocks = <&mcucfg CLK_MCU_MP0_SEL>, +- <&topckgen CLK_TOP_F_MP0_PLL1>; +- clock-names = "cpu", "intermediate"; +- proc-supply = <&cpus_fixed_vproc0>; +- operating-points-v2 = <&cluster0_opp>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- }; +- +- cpu2: cpu@200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x200>; +- enable-method = "psci"; +- clocks = <&mcucfg CLK_MCU_MP2_SEL>, +- <&topckgen CLK_TOP_F_BIG_PLL1>; +- clock-names = "cpu", "intermediate"; +- proc-supply = <&cpus_fixed_vproc1>; +- operating-points-v2 = <&cluster1_opp>; +- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP_0: cpu-sleep-0 { +- compatible = "arm,idle-state"; +- local-timer-stop; +- entry-latency-us = <100>; +- exit-latency-us = <80>; +- min-residency-us = <2000>; +- arm,psci-suspend-param = <0x0010000>; +- }; +- +- CLUSTER_SLEEP_0: cluster-sleep-0 { +- compatible = "arm,idle-state"; +- local-timer-stop; +- entry-latency-us = <350>; +- exit-latency-us = <80>; +- min-residency-us = <3000>; +- arm,psci-suspend-param = <0x1010000>; +- }; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- baud_clk: dummy26m { +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- #clock-cells = <0>; +- }; +- +- sys_clk: dummyclk { +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- #clock-cells = <0>; +- }; +- +- clk26m: oscillator@0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- clock-output-names = "clk26m"; +- }; +- +- clk32k: oscillator@1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "clk32k"; +- }; +- +- clkfpc: oscillator@2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- clock-output-names = "clkfpc"; +- }; +- +- clkaud_ext_i_0: oscillator@3 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <6500000>; +- clock-output-names = "clkaud_ext_i_0"; +- }; +- +- clkaud_ext_i_1: oscillator@4 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <196608000>; +- clock-output-names = "clkaud_ext_i_1"; +- }; +- +- clkaud_ext_i_2: oscillator@5 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <180633600>; +- clock-output-names = "clkaud_ext_i_2"; +- }; +- +- clki2si0_mck_i: oscillator@6 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <30000000>; +- clock-output-names = "clki2si0_mck_i"; +- }; +- +- clki2si1_mck_i: oscillator@7 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <30000000>; +- clock-output-names = "clki2si1_mck_i"; +- }; +- +- clki2si2_mck_i: oscillator@8 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <30000000>; +- clock-output-names = "clki2si2_mck_i"; +- }; +- +- clktdmin_mclk_i: oscillator@9 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <30000000>; +- clock-output-names = "clktdmin_mclk_i"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- }; +- +- topckgen: syscon@10000000 { +- compatible = "mediatek,mt2712-topckgen", "syscon"; +- reg = <0 0x10000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- infracfg: syscon@10001000 { +- compatible = "mediatek,mt2712-infracfg", "syscon"; +- reg = <0 0x10001000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- pericfg: syscon@10003000 { +- compatible = "mediatek,mt2712-pericfg", "syscon"; +- reg = <0 0x10003000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- syscfg_pctl_a: syscfg_pctl_a@10005000 { +- compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; +- reg = <0 0x10005000 0 0x1000>; +- }; +- +- pio: pinctrl@10005000 { +- compatible = "mediatek,mt2712-pinctrl"; +- reg = <0 0x1000b000 0 0x1000>; +- mediatek,pctl-regmap = <&syscfg_pctl_a>; +- pins-are-numbered; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- +- scpsys: power-controller@10006000 { +- compatible = "mediatek,mt2712-scpsys", "syscon"; +- #power-domain-cells = <1>; +- reg = <0 0x10006000 0 0x1000>; +- clocks = <&topckgen CLK_TOP_MM_SEL>, +- <&topckgen CLK_TOP_MFG_SEL>, +- <&topckgen CLK_TOP_VENC_SEL>, +- <&topckgen CLK_TOP_JPGDEC_SEL>, +- <&topckgen CLK_TOP_A1SYS_HP_SEL>, +- <&topckgen CLK_TOP_VDEC_SEL>; +- clock-names = "mm", "mfg", "venc", +- "jpgdec", "audio", "vdec"; +- infracfg = <&infracfg>; +- }; +- +- uart5: serial@1000f000 { +- compatible = "mediatek,mt2712-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x1000f000 0 0x400>; +- interrupts = ; +- clocks = <&baud_clk>, <&sys_clk>; +- clock-names = "baud", "bus"; +- dmas = <&apdma 10 +- &apdma 11>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- rtc: rtc@10011000 { +- compatible = "mediatek,mt2712-rtc"; +- reg = <0 0x10011000 0 0x1000>; +- interrupts = ; +- }; +- +- spis1: spi@10013000 { +- compatible = "mediatek,mt2712-spi-slave"; +- reg = <0 0x10013000 0 0x100>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_AO_SPI1>; +- clock-names = "spi"; +- assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; +- status = "disabled"; +- }; +- +- iommu0: iommu@10205000 { +- compatible = "mediatek,mt2712-m4u"; +- reg = <0 0x10205000 0 0x1000>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_M4U>; +- clock-names = "bclk"; +- mediatek,larbs = <&larb0 &larb1 &larb2 +- &larb3 &larb6>; +- #iommu-cells = <1>; +- }; +- +- apmixedsys: syscon@10209000 { +- compatible = "mediatek,mt2712-apmixedsys", "syscon"; +- reg = <0 0x10209000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- iommu1: iommu@1020a000 { +- compatible = "mediatek,mt2712-m4u"; +- reg = <0 0x1020a000 0 0x1000>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_M4U>; +- clock-names = "bclk"; +- mediatek,larbs = <&larb4 &larb5 &larb7>; +- #iommu-cells = <1>; +- }; +- +- mcucfg: syscon@10220000 { +- compatible = "mediatek,mt2712-mcucfg", "syscon"; +- reg = <0 0x10220000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- sysirq: interrupt-controller@10220a80 { +- compatible = "mediatek,mt2712-sysirq", +- "mediatek,mt6577-sysirq"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0 0x10220a80 0 0x40>; +- }; +- +- gic: interrupt-controller@10510000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- interrupt-controller; +- reg = <0 0x10510000 0 0x10000>, +- <0 0x10520000 0 0x20000>, +- <0 0x10540000 0 0x20000>, +- <0 0x10560000 0 0x20000>; +- interrupts = ; +- }; +- +- apdma: dma-controller@11000400 { +- compatible = "mediatek,mt2712-uart-dma", +- "mediatek,mt6577-uart-dma"; +- reg = <0 0x11000400 0 0x80>, +- <0 0x11000480 0 0x80>, +- <0 0x11000500 0 0x80>, +- <0 0x11000580 0 0x80>, +- <0 0x11000600 0 0x80>, +- <0 0x11000680 0 0x80>, +- <0 0x11000700 0 0x80>, +- <0 0x11000780 0 0x80>, +- <0 0x11000800 0 0x80>, +- <0 0x11000880 0 0x80>, +- <0 0x11000900 0 0x80>, +- <0 0x11000980 0 0x80>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- dma-requests = <12>; +- clocks = <&pericfg CLK_PERI_AP_DMA>; +- clock-names = "apdma"; +- #dma-cells = <1>; +- }; +- +- auxadc: adc@11001000 { +- compatible = "mediatek,mt2712-auxadc"; +- reg = <0 0x11001000 0 0x1000>; +- clocks = <&pericfg CLK_PERI_AUXADC>; +- clock-names = "main"; +- #io-channel-cells = <1>; +- status = "disabled"; +- }; +- +- uart0: serial@11002000 { +- compatible = "mediatek,mt2712-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11002000 0 0x400>; +- interrupts = ; +- clocks = <&baud_clk>, <&sys_clk>; +- clock-names = "baud", "bus"; +- dmas = <&apdma 0 +- &apdma 1>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- uart1: serial@11003000 { +- compatible = "mediatek,mt2712-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11003000 0 0x400>; +- interrupts = ; +- clocks = <&baud_clk>, <&sys_clk>; +- clock-names = "baud", "bus"; +- dmas = <&apdma 2 +- &apdma 3>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- uart2: serial@11004000 { +- compatible = "mediatek,mt2712-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11004000 0 0x400>; +- interrupts = ; +- clocks = <&baud_clk>, <&sys_clk>; +- clock-names = "baud", "bus"; +- dmas = <&apdma 4 +- &apdma 5>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- uart3: serial@11005000 { +- compatible = "mediatek,mt2712-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11005000 0 0x400>; +- interrupts = ; +- clocks = <&baud_clk>, <&sys_clk>; +- clock-names = "baud", "bus"; +- dmas = <&apdma 6 +- &apdma 7>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- pwm: pwm@11006000 { +- compatible = "mediatek,mt2712-pwm"; +- reg = <0 0x11006000 0 0x1000>; +- #pwm-cells = <2>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_PWM_SEL>, +- <&pericfg CLK_PERI_PWM>, +- <&pericfg CLK_PERI_PWM0>, +- <&pericfg CLK_PERI_PWM1>, +- <&pericfg CLK_PERI_PWM2>, +- <&pericfg CLK_PERI_PWM3>, +- <&pericfg CLK_PERI_PWM4>, +- <&pericfg CLK_PERI_PWM5>, +- <&pericfg CLK_PERI_PWM6>, +- <&pericfg CLK_PERI_PWM7>; +- clock-names = "top", +- "main", +- "pwm1", +- "pwm2", +- "pwm3", +- "pwm4", +- "pwm5", +- "pwm6", +- "pwm7", +- "pwm8"; +- status = "disabled"; +- }; +- +- i2c0: i2c@11007000 { +- compatible = "mediatek,mt2712-i2c"; +- reg = <0 0x11007000 0 0x90>, +- <0 0x11000180 0 0x80>; +- interrupts = ; +- clock-div = <4>; +- clocks = <&pericfg CLK_PERI_I2C0>, +- <&pericfg CLK_PERI_AP_DMA>; +- clock-names = "main", +- "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@11008000 { +- compatible = "mediatek,mt2712-i2c"; +- reg = <0 0x11008000 0 0x90>, +- <0 0x11000200 0 0x80>; +- interrupts = ; +- clock-div = <4>; +- clocks = <&pericfg CLK_PERI_I2C1>, +- <&pericfg CLK_PERI_AP_DMA>; +- clock-names = "main", +- "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@11009000 { +- compatible = "mediatek,mt2712-i2c"; +- reg = <0 0x11009000 0 0x90>, +- <0 0x11000280 0 0x80>; +- interrupts = ; +- clock-div = <4>; +- clocks = <&pericfg CLK_PERI_I2C2>, +- <&pericfg CLK_PERI_AP_DMA>; +- clock-names = "main", +- "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi0: spi@1100a000 { +- compatible = "mediatek,mt2712-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x1100a000 0 0x100>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, +- <&topckgen CLK_TOP_SPI_SEL>, +- <&pericfg CLK_PERI_SPI0>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- nandc: nfi@1100e000 { +- compatible = "mediatek,mt2712-nfc"; +- reg = <0 0x1100e000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>; +- clock-names = "nfi_clk", "pad_clk"; +- ecc-engine = <&bch>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- bch: ecc@1100f000 { +- compatible = "mediatek,mt2712-ecc"; +- reg = <0 0x1100f000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>; +- clock-names = "nfiecc_clk"; +- status = "disabled"; +- }; +- +- i2c3: i2c@11010000 { +- compatible = "mediatek,mt2712-i2c"; +- reg = <0 0x11010000 0 0x90>, +- <0 0x11000300 0 0x80>; +- interrupts = ; +- clock-div = <4>; +- clocks = <&pericfg CLK_PERI_I2C3>, +- <&pericfg CLK_PERI_AP_DMA>; +- clock-names = "main", +- "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@11011000 { +- compatible = "mediatek,mt2712-i2c"; +- reg = <0 0x11011000 0 0x90>, +- <0 0x11000380 0 0x80>; +- interrupts = ; +- clock-div = <4>; +- clocks = <&pericfg CLK_PERI_I2C4>, +- <&pericfg CLK_PERI_AP_DMA>; +- clock-names = "main", +- "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c5: i2c@11013000 { +- compatible = "mediatek,mt2712-i2c"; +- reg = <0 0x11013000 0 0x90>, +- <0 0x11000100 0 0x80>; +- interrupts = ; +- clock-div = <4>; +- clocks = <&pericfg CLK_PERI_I2C5>, +- <&pericfg CLK_PERI_AP_DMA>; +- clock-names = "main", +- "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi2: spi@11015000 { +- compatible = "mediatek,mt2712-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x11015000 0 0x100>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, +- <&topckgen CLK_TOP_SPI_SEL>, +- <&pericfg CLK_PERI_SPI2>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- spi3: spi@11016000 { +- compatible = "mediatek,mt2712-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x11016000 0 0x100>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, +- <&topckgen CLK_TOP_SPI_SEL>, +- <&pericfg CLK_PERI_SPI3>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- spi4: spi@10012000 { +- compatible = "mediatek,mt2712-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x10012000 0 0x100>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, +- <&topckgen CLK_TOP_SPI_SEL>, +- <&infracfg CLK_INFRA_AO_SPI0>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- spi5: spi@11018000 { +- compatible = "mediatek,mt2712-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x11018000 0 0x100>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, +- <&topckgen CLK_TOP_SPI_SEL>, +- <&pericfg CLK_PERI_SPI5>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- uart4: serial@11019000 { +- compatible = "mediatek,mt2712-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11019000 0 0x400>; +- interrupts = ; +- clocks = <&baud_clk>, <&sys_clk>; +- clock-names = "baud", "bus"; +- dmas = <&apdma 8 +- &apdma 9>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- stmmac_axi_setup: stmmac-axi-config { +- snps,wr_osr_lmt = <0x7>; +- snps,rd_osr_lmt = <0x7>; +- snps,blen = <0 0 0 0 16 8 4>; +- }; +- +- mtl_rx_setup: rx-queues-config { +- snps,rx-queues-to-use = <1>; +- snps,rx-sched-sp; +- queue0 { +- snps,dcb-algorithm; +- snps,map-to-dma-channel = <0x0>; +- snps,priority = <0x0>; +- }; +- }; +- +- mtl_tx_setup: tx-queues-config { +- snps,tx-queues-to-use = <3>; +- snps,tx-sched-wrr; +- queue0 { +- snps,weight = <0x10>; +- snps,dcb-algorithm; +- snps,priority = <0x0>; +- }; +- queue1 { +- snps,weight = <0x11>; +- snps,dcb-algorithm; +- snps,priority = <0x1>; +- }; +- queue2 { +- snps,weight = <0x12>; +- snps,dcb-algorithm; +- snps,priority = <0x2>; +- }; +- }; +- +- eth: ethernet@1101c000 { +- compatible = "mediatek,mt2712-gmac"; +- reg = <0 0x1101c000 0 0x1300>; +- interrupts = ; +- interrupt-names = "macirq"; +- mac-address = [00 55 7b b5 7d f7]; +- clock-names = "axi", +- "apb", +- "mac_main", +- "ptp_ref"; +- clocks = <&pericfg CLK_PERI_GMAC>, +- <&pericfg CLK_PERI_GMAC_PCLK>, +- <&topckgen CLK_TOP_ETHER_125M_SEL>, +- <&topckgen CLK_TOP_ETHER_50M_SEL>; +- assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>, +- <&topckgen CLK_TOP_ETHER_50M_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>, +- <&topckgen CLK_TOP_APLL1_D3>; +- power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>; +- mediatek,pericfg = <&pericfg>; +- snps,axi-config = <&stmmac_axi_setup>; +- snps,mtl-rx-config = <&mtl_rx_setup>; +- snps,mtl-tx-config = <&mtl_tx_setup>; +- snps,txpbl = <1>; +- snps,rxpbl = <1>; +- clk_csr = <0>; +- status = "disabled"; +- }; +- +- mmc0: mmc@11230000 { +- compatible = "mediatek,mt2712-mmc"; +- reg = <0 0x11230000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_MSDC30_0>, +- <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>, +- <&pericfg CLK_PERI_MSDC30_0_QTR_EN>, +- <&pericfg CLK_PERI_MSDC50_0_EN>; +- clock-names = "source", "hclk", "bus_clk", "source_cg"; +- status = "disabled"; +- }; +- +- mmc1: mmc@11240000 { +- compatible = "mediatek,mt2712-mmc"; +- reg = <0 0x11240000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_MSDC30_1>, +- <&topckgen CLK_TOP_AXI_SEL>, +- <&pericfg CLK_PERI_MSDC30_1_EN>; +- clock-names = "source", "hclk", "source_cg"; +- status = "disabled"; +- }; +- +- mmc2: mmc@11250000 { +- compatible = "mediatek,mt2712-mmc"; +- reg = <0 0x11250000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_MSDC30_2>, +- <&topckgen CLK_TOP_AXI_SEL>, +- <&pericfg CLK_PERI_MSDC30_2_EN>; +- clock-names = "source", "hclk", "source_cg"; +- status = "disabled"; +- }; +- +- ssusb: usb@11271000 { +- compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; +- reg = <0 0x11271000 0 0x3000>, +- <0 0x11280700 0 0x0100>; +- reg-names = "mac", "ippc"; +- interrupts = ; +- phys = <&u2port0 PHY_TYPE_USB2>, +- <&u2port1 PHY_TYPE_USB2>; +- power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; +- clocks = <&topckgen CLK_TOP_USB30_SEL>; +- clock-names = "sys_ck"; +- mediatek,syscon-wakeup = <&pericfg 0x510 2>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "disabled"; +- +- usb_host0: usb@11270000 { +- compatible = "mediatek,mt2712-xhci", +- "mediatek,mtk-xhci"; +- reg = <0 0x11270000 0 0x1000>; +- reg-names = "mac"; +- interrupts = ; +- power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; +- clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; +- clock-names = "sys_ck", "ref_ck"; +- status = "disabled"; +- }; +- }; +- +- u3phy0: t-phy@11290000 { +- compatible = "mediatek,mt2712-tphy", +- "mediatek,generic-tphy-v2"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x11290000 0x9000>; +- status = "okay"; +- +- u2port0: usb-phy@0 { +- reg = <0x0 0x700>; +- clocks = <&clk26m>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- +- u2port1: usb-phy@8000 { +- reg = <0x8000 0x700>; +- clocks = <&clk26m>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- +- u3port0: usb-phy@8700 { +- reg = <0x8700 0x900>; +- clocks = <&clk26m>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- }; +- +- ssusb1: usb@112c1000 { +- compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; +- reg = <0 0x112c1000 0 0x3000>, +- <0 0x112d0700 0 0x0100>; +- reg-names = "mac", "ippc"; +- interrupts = ; +- phys = <&u2port2 PHY_TYPE_USB2>, +- <&u2port3 PHY_TYPE_USB2>, +- <&u3port1 PHY_TYPE_USB3>; +- power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; +- clocks = <&topckgen CLK_TOP_USB30_SEL>; +- clock-names = "sys_ck"; +- mediatek,syscon-wakeup = <&pericfg 0x514 2>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "disabled"; +- +- usb_host1: usb@112c0000 { +- compatible = "mediatek,mt2712-xhci", +- "mediatek,mtk-xhci"; +- reg = <0 0x112c0000 0 0x1000>; +- reg-names = "mac"; +- interrupts = ; +- power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; +- clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; +- clock-names = "sys_ck", "ref_ck"; +- status = "disabled"; +- }; +- }; +- +- u3phy1: t-phy@112e0000 { +- compatible = "mediatek,mt2712-tphy", +- "mediatek,generic-tphy-v2"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x112e0000 0x9000>; +- status = "okay"; +- +- u2port2: usb-phy@0 { +- reg = <0x0 0x700>; +- clocks = <&clk26m>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- +- u2port3: usb-phy@8000 { +- reg = <0x8000 0x700>; +- clocks = <&clk26m>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- +- u3port1: usb-phy@8700 { +- reg = <0x8700 0x900>; +- clocks = <&clk26m>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- }; +- +- pcie: pcie@11700000 { +- compatible = "mediatek,mt2712-pcie"; +- device_type = "pci"; +- reg = <0 0x11700000 0 0x1000>, +- <0 0x112ff000 0 0x1000>; +- reg-names = "port0", "port1"; +- #address-cells = <3>; +- #size-cells = <2>; +- interrupts = , +- ; +- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, +- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, +- <&pericfg CLK_PERI_PCIE0>, +- <&pericfg CLK_PERI_PCIE1>; +- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; +- phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>; +- phy-names = "pcie-phy0", "pcie-phy1"; +- bus-range = <0x00 0xff>; +- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; +- +- pcie0: pcie@0,0 { +- device_type = "pci"; +- status = "disabled"; +- reg = <0x0000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie_intc0 0>, +- <0 0 0 2 &pcie_intc0 1>, +- <0 0 0 3 &pcie_intc0 2>, +- <0 0 0 4 &pcie_intc0 3>; +- pcie_intc0: interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- }; +- }; +- +- pcie1: pcie@1,0 { +- device_type = "pci"; +- status = "disabled"; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie_intc1 0>, +- <0 0 0 2 &pcie_intc1 1>, +- <0 0 0 3 &pcie_intc1 2>, +- <0 0 0 4 &pcie_intc1 3>; +- pcie_intc1: interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- }; +- }; +- }; +- +- mfgcfg: syscon@13000000 { +- compatible = "mediatek,mt2712-mfgcfg", "syscon"; +- reg = <0 0x13000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- mmsys: syscon@14000000 { +- compatible = "mediatek,mt2712-mmsys", "syscon"; +- reg = <0 0x14000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- larb0: larb@14021000 { +- compatible = "mediatek,mt2712-smi-larb"; +- reg = <0 0x14021000 0 0x1000>; +- mediatek,smi = <&smi_common0>; +- mediatek,larb-id = <0>; +- power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_SMI_LARB0>, +- <&mmsys CLK_MM_SMI_LARB0>; +- clock-names = "apb", "smi"; +- }; +- +- smi_common0: smi@14022000 { +- compatible = "mediatek,mt2712-smi-common"; +- reg = <0 0x14022000 0 0x1000>; +- power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_SMI_COMMON>, +- <&mmsys CLK_MM_SMI_COMMON>; +- clock-names = "apb", "smi"; +- }; +- +- larb4: larb@14027000 { +- compatible = "mediatek,mt2712-smi-larb"; +- reg = <0 0x14027000 0 0x1000>; +- mediatek,smi = <&smi_common1>; +- mediatek,larb-id = <4>; +- power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_SMI_LARB4>, +- <&mmsys CLK_MM_SMI_LARB4>; +- clock-names = "apb", "smi"; +- }; +- +- larb5: larb@14030000 { +- compatible = "mediatek,mt2712-smi-larb"; +- reg = <0 0x14030000 0 0x1000>; +- mediatek,smi = <&smi_common1>; +- mediatek,larb-id = <5>; +- power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_SMI_LARB5>, +- <&mmsys CLK_MM_SMI_LARB5>; +- clock-names = "apb", "smi"; +- }; +- +- smi_common1: smi@14031000 { +- compatible = "mediatek,mt2712-smi-common"; +- reg = <0 0x14031000 0 0x1000>; +- power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_SMI_COMMON1>, +- <&mmsys CLK_MM_SMI_COMMON1>; +- clock-names = "apb", "smi"; +- }; +- +- larb7: larb@14032000 { +- compatible = "mediatek,mt2712-smi-larb"; +- reg = <0 0x14032000 0 0x1000>; +- mediatek,smi = <&smi_common1>; +- mediatek,larb-id = <7>; +- power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_SMI_LARB7>, +- <&mmsys CLK_MM_SMI_LARB7>; +- clock-names = "apb", "smi"; +- }; +- +- imgsys: syscon@15000000 { +- compatible = "mediatek,mt2712-imgsys", "syscon"; +- reg = <0 0x15000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- larb2: larb@15001000 { +- compatible = "mediatek,mt2712-smi-larb"; +- reg = <0 0x15001000 0 0x1000>; +- mediatek,smi = <&smi_common0>; +- mediatek,larb-id = <2>; +- power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>; +- clocks = <&imgsys CLK_IMG_SMI_LARB2>, +- <&imgsys CLK_IMG_SMI_LARB2>; +- clock-names = "apb", "smi"; +- }; +- +- bdpsys: syscon@15010000 { +- compatible = "mediatek,mt2712-bdpsys", "syscon"; +- reg = <0 0x15010000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- vdecsys: syscon@16000000 { +- compatible = "mediatek,mt2712-vdecsys", "syscon"; +- reg = <0 0x16000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- larb1: larb@16010000 { +- compatible = "mediatek,mt2712-smi-larb"; +- reg = <0 0x16010000 0 0x1000>; +- mediatek,smi = <&smi_common0>; +- mediatek,larb-id = <1>; +- power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>; +- clocks = <&vdecsys CLK_VDEC_CKEN>, +- <&vdecsys CLK_VDEC_LARB1_CKEN>; +- clock-names = "apb", "smi"; +- }; +- +- vencsys: syscon@18000000 { +- compatible = "mediatek,mt2712-vencsys", "syscon"; +- reg = <0 0x18000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- larb3: larb@18001000 { +- compatible = "mediatek,mt2712-smi-larb"; +- reg = <0 0x18001000 0 0x1000>; +- mediatek,smi = <&smi_common0>; +- mediatek,larb-id = <3>; +- power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; +- clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, +- <&vencsys CLK_VENC_VENC>; +- clock-names = "apb", "smi"; +- }; +- +- larb6: larb@18002000 { +- compatible = "mediatek,mt2712-smi-larb"; +- reg = <0 0x18002000 0 0x1000>; +- mediatek,smi = <&smi_common0>; +- mediatek,larb-id = <6>; +- power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; +- clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, +- <&vencsys CLK_VENC_VENC>; +- clock-names = "apb", "smi"; +- }; +- +- jpgdecsys: syscon@19000000 { +- compatible = "mediatek,mt2712-jpgdecsys", "syscon"; +- reg = <0 0x19000000 0 0x1000>; +- #clock-cells = <1>; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt6358.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt6358.dtsi +deleted file mode 100644 +index fa159b20379e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt6358.dtsi ++++ /dev/null +@@ -1,360 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (c) 2020 MediaTek Inc. +- */ +- +-&pwrap { +- pmic: mt6358 { +- compatible = "mediatek,mt6358"; +- interrupt-controller; +- interrupt-parent = <&pio>; +- interrupts = <182 IRQ_TYPE_LEVEL_HIGH>; +- #interrupt-cells = <2>; +- +- mt6358codec: mt6358codec { +- compatible = "mediatek,mt6358-sound"; +- }; +- +- mt6358regulator: mt6358regulator { +- compatible = "mediatek,mt6358-regulator"; +- +- mt6358_vdram1_reg: buck_vdram1 { +- regulator-name = "vdram1"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <2087500>; +- regulator-ramp-delay = <12500>; +- regulator-enable-ramp-delay = <0>; +- regulator-always-on; +- regulator-allowed-modes = <0 1>; +- }; +- +- mt6358_vcore_reg: buck_vcore { +- regulator-name = "vcore"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1293750>; +- regulator-ramp-delay = <6250>; +- regulator-enable-ramp-delay = <200>; +- regulator-always-on; +- regulator-allowed-modes = <0 1>; +- }; +- +- mt6358_vpa_reg: buck_vpa { +- regulator-name = "vpa"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <3650000>; +- regulator-ramp-delay = <50000>; +- regulator-enable-ramp-delay = <250>; +- regulator-allowed-modes = <0 1>; +- }; +- +- mt6358_vproc11_reg: buck_vproc11 { +- regulator-name = "vproc11"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1293750>; +- regulator-ramp-delay = <6250>; +- regulator-enable-ramp-delay = <200>; +- regulator-always-on; +- regulator-allowed-modes = <0 1>; +- }; +- +- mt6358_vproc12_reg: buck_vproc12 { +- regulator-name = "vproc12"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1293750>; +- regulator-ramp-delay = <6250>; +- regulator-enable-ramp-delay = <200>; +- regulator-always-on; +- regulator-allowed-modes = <0 1>; +- }; +- +- mt6358_vgpu_reg: buck_vgpu { +- regulator-name = "vgpu"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1293750>; +- regulator-ramp-delay = <6250>; +- regulator-enable-ramp-delay = <200>; +- regulator-allowed-modes = <0 1>; +- }; +- +- mt6358_vs2_reg: buck_vs2 { +- regulator-name = "vs2"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <2087500>; +- regulator-ramp-delay = <12500>; +- regulator-enable-ramp-delay = <0>; +- regulator-always-on; +- }; +- +- mt6358_vmodem_reg: buck_vmodem { +- regulator-name = "vmodem"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1293750>; +- regulator-ramp-delay = <6250>; +- regulator-enable-ramp-delay = <900>; +- regulator-always-on; +- regulator-allowed-modes = <0 1>; +- }; +- +- mt6358_vs1_reg: buck_vs1 { +- regulator-name = "vs1"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <2587500>; +- regulator-ramp-delay = <12500>; +- regulator-enable-ramp-delay = <0>; +- regulator-always-on; +- }; +- +- mt6358_vdram2_reg: ldo_vdram2 { +- regulator-name = "vdram2"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <3300>; +- }; +- +- mt6358_vsim1_reg: ldo_vsim1 { +- regulator-name = "vsim1"; +- regulator-min-microvolt = <1700000>; +- regulator-max-microvolt = <3100000>; +- regulator-enable-ramp-delay = <540>; +- }; +- +- mt6358_vibr_reg: ldo_vibr { +- regulator-name = "vibr"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <60>; +- }; +- +- mt6358_vrf12_reg: ldo_vrf12 { +- compatible = "regulator-fixed"; +- regulator-name = "vrf12"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-enable-ramp-delay = <120>; +- }; +- +- mt6358_vio18_reg: ldo_vio18 { +- compatible = "regulator-fixed"; +- regulator-name = "vio18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <2700>; +- regulator-always-on; +- }; +- +- mt6358_vusb_reg: ldo_vusb { +- regulator-name = "vusb"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3100000>; +- regulator-enable-ramp-delay = <270>; +- regulator-always-on; +- }; +- +- mt6358_vcamio_reg: ldo_vcamio { +- compatible = "regulator-fixed"; +- regulator-name = "vcamio"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <325>; +- }; +- +- mt6358_vcamd_reg: ldo_vcamd { +- regulator-name = "vcamd"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <325>; +- }; +- +- mt6358_vcn18_reg: ldo_vcn18 { +- compatible = "regulator-fixed"; +- regulator-name = "vcn18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <270>; +- }; +- +- mt6358_vfe28_reg: ldo_vfe28 { +- compatible = "regulator-fixed"; +- regulator-name = "vfe28"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-enable-ramp-delay = <270>; +- }; +- +- mt6358_vsram_proc11_reg: ldo_vsram_proc11 { +- regulator-name = "vsram_proc11"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1293750>; +- regulator-ramp-delay = <6250>; +- regulator-enable-ramp-delay = <240>; +- regulator-always-on; +- }; +- +- mt6358_vcn28_reg: ldo_vcn28 { +- compatible = "regulator-fixed"; +- regulator-name = "vcn28"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-enable-ramp-delay = <270>; +- }; +- +- mt6358_vsram_others_reg: ldo_vsram_others { +- regulator-name = "vsram_others"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1293750>; +- regulator-ramp-delay = <6250>; +- regulator-enable-ramp-delay = <240>; +- regulator-always-on; +- }; +- +- mt6358_vsram_gpu_reg: ldo_vsram_gpu { +- regulator-name = "vsram_gpu"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1293750>; +- regulator-ramp-delay = <6250>; +- regulator-enable-ramp-delay = <240>; +- }; +- +- mt6358_vxo22_reg: ldo_vxo22 { +- compatible = "regulator-fixed"; +- regulator-name = "vxo22"; +- regulator-min-microvolt = <2200000>; +- regulator-max-microvolt = <2200000>; +- regulator-enable-ramp-delay = <120>; +- regulator-always-on; +- }; +- +- mt6358_vefuse_reg: ldo_vefuse { +- regulator-name = "vefuse"; +- regulator-min-microvolt = <1700000>; +- regulator-max-microvolt = <1900000>; +- regulator-enable-ramp-delay = <270>; +- }; +- +- mt6358_vaux18_reg: ldo_vaux18 { +- compatible = "regulator-fixed"; +- regulator-name = "vaux18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <270>; +- }; +- +- mt6358_vmch_reg: ldo_vmch { +- regulator-name = "vmch"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <60>; +- }; +- +- mt6358_vbif28_reg: ldo_vbif28 { +- compatible = "regulator-fixed"; +- regulator-name = "vbif28"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-enable-ramp-delay = <270>; +- }; +- +- mt6358_vsram_proc12_reg: ldo_vsram_proc12 { +- regulator-name = "vsram_proc12"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1293750>; +- regulator-ramp-delay = <6250>; +- regulator-enable-ramp-delay = <240>; +- regulator-always-on; +- }; +- +- mt6358_vcama1_reg: ldo_vcama1 { +- regulator-name = "vcama1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- regulator-enable-ramp-delay = <325>; +- }; +- +- mt6358_vemc_reg: ldo_vemc { +- regulator-name = "vemc"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <60>; +- }; +- +- mt6358_vio28_reg: ldo_vio28 { +- compatible = "regulator-fixed"; +- regulator-name = "vio28"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-enable-ramp-delay = <270>; +- }; +- +- mt6358_va12_reg: ldo_va12 { +- compatible = "regulator-fixed"; +- regulator-name = "va12"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-enable-ramp-delay = <270>; +- regulator-always-on; +- }; +- +- mt6358_vrf18_reg: ldo_vrf18 { +- compatible = "regulator-fixed"; +- regulator-name = "vrf18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <120>; +- }; +- +- mt6358_vcn33_bt_reg: ldo_vcn33_bt { +- regulator-name = "vcn33_bt"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3500000>; +- regulator-enable-ramp-delay = <270>; +- }; +- +- mt6358_vcn33_wifi_reg: ldo_vcn33_wifi { +- regulator-name = "vcn33_wifi"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3500000>; +- regulator-enable-ramp-delay = <270>; +- }; +- +- mt6358_vcama2_reg: ldo_vcama2 { +- regulator-name = "vcama2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- regulator-enable-ramp-delay = <325>; +- }; +- +- mt6358_vmc_reg: ldo_vmc { +- regulator-name = "vmc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <60>; +- }; +- +- mt6358_vldo28_reg: ldo_vldo28 { +- regulator-name = "vldo28"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <3000000>; +- regulator-enable-ramp-delay = <270>; +- }; +- +- mt6358_vaud28_reg: ldo_vaud28 { +- compatible = "regulator-fixed"; +- regulator-name = "vaud28"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-enable-ramp-delay = <270>; +- }; +- +- mt6358_vsim2_reg: ldo_vsim2 { +- regulator-name = "vsim2"; +- regulator-min-microvolt = <1700000>; +- regulator-max-microvolt = <3100000>; +- regulator-enable-ramp-delay = <540>; +- }; +- }; +- +- mt6358rtc: mt6358rtc { +- compatible = "mediatek,mt6358-rtc"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt6380.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt6380.dtsi +deleted file mode 100644 +index 53b335d2de5f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt6380.dtsi ++++ /dev/null +@@ -1,86 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * dts file for MediaTek MT6380 regulator +- * +- * Copyright (c) 2018 MediaTek Inc. +- * Author: Chenglin Xu +- * Sean Wang +- */ +- +-&pwrap { +- regulators { +- compatible = "mediatek,mt6380-regulator"; +- +- mt6380_vcpu_reg: buck-vcore1 { +- regulator-name = "vcore1"; +- regulator-min-microvolt = < 600000>; +- regulator-max-microvolt = <1393750>; +- regulator-ramp-delay = <6250>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- mt6380_vcore_reg: buck-vcore { +- regulator-name = "vcore"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1393750>; +- regulator-ramp-delay = <6250>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- mt6380_vrf_reg: buck-vrf { +- regulator-name = "vrf"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1575000>; +- regulator-ramp-delay = <0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- mt6380_vm_reg: ldo-vm { +- regulator-name = "vm"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1400000>; +- regulator-ramp-delay = <0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- mt6380_va_reg: ldo-va { +- regulator-name = "va"; +- regulator-min-microvolt = <2200000>; +- regulator-max-microvolt = <3300000>; +- regulator-ramp-delay = <0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- mt6380_vphy_reg: ldo-vphy { +- regulator-name = "vphy"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-ramp-delay = <0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- mt6380_vddr_reg: ldo-vddr { +- regulator-name = "vddr"; +- regulator-min-microvolt = <1240000>; +- regulator-max-microvolt = <1840000>; +- regulator-ramp-delay = <0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- mt6380_vt_reg: ldo-vt { +- regulator-name = "vt"; +- regulator-min-microvolt = <2200000>; +- regulator-max-microvolt = <3300000>; +- regulator-ramp-delay = <0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt6755-evb.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt6755-evb.dts +deleted file mode 100644 +index e079b7932ba3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt6755-evb.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2016 MediaTek Inc. +- * Author: Mars.C +- */ +- +-/dts-v1/; +-#include "mt6755.dtsi" +- +-/ { +- model = "MediaTek MT6755 EVB"; +- compatible = "mediatek,mt6755-evb", "mediatek,mt6755"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x1e800000>; +- }; +- +- chosen { +- stdout-path = "serial0:921600n8"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt6755.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt6755.dtsi +deleted file mode 100644 +index 01ba77669717..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt6755.dtsi ++++ /dev/null +@@ -1,145 +0,0 @@ +-/* +- * Copyright (c) 2016 MediaTek Inc. +- * Author: Mars.C +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License version 2 as +- * published by the Free Software Foundation. +- * +- * This program is distributed in the hope that it will be useful, +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#include +-#include +- +-/ { +- compatible = "mediatek,mt6755"; +- interrupt-parent = <&sysirq>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x000>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x001>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x002>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x003>; +- }; +- +- cpu4: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x100>; +- }; +- +- cpu5: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x101>; +- }; +- +- cpu6: cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x102>; +- }; +- +- cpu7: cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x103>; +- }; +- }; +- +- uart_clk: dummy26m { +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- #clock-cells = <0>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- }; +- +- sysirq: intpol-controller@10200620 { +- compatible = "mediatek,mt6755-sysirq", +- "mediatek,mt6577-sysirq"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0 0x10200620 0 0x20>; +- }; +- +- gic: interrupt-controller@10231000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- interrupt-controller; +- reg = <0 0x10231000 0 0x1000>, +- <0 0x10232000 0 0x2000>, +- <0 0x10234000 0 0x2000>, +- <0 0x10236000 0 0x2000>; +- }; +- +- uart0: serial@11002000 { +- compatible = "mediatek,mt6755-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11002000 0 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart1: serial@11003000 { +- compatible = "mediatek,mt6755-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11003000 0 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt6779-evb.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt6779-evb.dts +deleted file mode 100644 +index 164f5cbb3821..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt6779-evb.dts ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (c) 2019 MediaTek Inc. +- * Author: Mars.C +- * +- */ +- +-/dts-v1/; +-#include "mt6779.dtsi" +- +-/ { +- model = "MediaTek MT6779 EVB"; +- compatible = "mediatek,mt6779-evb", "mediatek,mt6779"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x1e800000>; +- }; +- +- chosen { +- stdout-path = "serial0:921600n8"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt6779.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt6779.dtsi +deleted file mode 100644 +index 9bdf5145966c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt6779.dtsi ++++ /dev/null +@@ -1,288 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (c) 2019 MediaTek Inc. +- * Author: Mars.C +- * +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "mediatek,mt6779"; +- interrupt-parent = <&sysirq>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- enable-method = "psci"; +- reg = <0x000>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- enable-method = "psci"; +- reg = <0x100>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- enable-method = "psci"; +- reg = <0x200>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- enable-method = "psci"; +- reg = <0x300>; +- }; +- +- cpu4: cpu@4 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- enable-method = "psci"; +- reg = <0x400>; +- }; +- +- cpu5: cpu@5 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- enable-method = "psci"; +- reg = <0x500>; +- }; +- +- cpu6: cpu@6 { +- device_type = "cpu"; +- compatible = "arm,cortex-a75"; +- enable-method = "psci"; +- reg = <0x600>; +- }; +- +- cpu7: cpu@7 { +- device_type = "cpu"; +- compatible = "arm,cortex-a75"; +- enable-method = "psci"; +- reg = <0x700>; +- }; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- +- clk26m: oscillator@0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- clock-output-names = "clk26m"; +- }; +- +- clk32k: oscillator@1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "clk32k"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- }; +- +- soc { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "simple-bus"; +- ranges; +- +- gic: interrupt-controller@0c000000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <4>; +- interrupt-parent = <&gic>; +- interrupt-controller; +- reg = <0 0x0c000000 0 0x40000>, /* GICD */ +- <0 0x0c040000 0 0x200000>; /* GICR */ +- interrupts = ; +- +- ppi-partitions { +- ppi_cluster0: interrupt-partition-0 { +- affinity = <&cpu0 &cpu1 \ +- &cpu2 &cpu3 &cpu4 &cpu5>; +- }; +- ppi_cluster1: interrupt-partition-1 { +- affinity = <&cpu6 &cpu7>; +- }; +- }; +- +- }; +- +- sysirq: intpol-controller@0c53a650 { +- compatible = "mediatek,mt6779-sysirq", +- "mediatek,mt6577-sysirq"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0 0x0c53a650 0 0x50>; +- }; +- +- topckgen: clock-controller@10000000 { +- compatible = "mediatek,mt6779-topckgen", "syscon"; +- reg = <0 0x10000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- infracfg_ao: clock-controller@10001000 { +- compatible = "mediatek,mt6779-infracfg_ao", "syscon"; +- reg = <0 0x10001000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- pio: pinctrl@10005000 { +- compatible = "mediatek,mt6779-pinctrl", "syscon"; +- reg = <0 0x10005000 0 0x1000>, +- <0 0x11c20000 0 0x1000>, +- <0 0x11d10000 0 0x1000>, +- <0 0x11e20000 0 0x1000>, +- <0 0x11e70000 0 0x1000>, +- <0 0x11ea0000 0 0x1000>, +- <0 0x11f20000 0 0x1000>, +- <0 0x11f30000 0 0x1000>, +- <0 0x1000b000 0 0x1000>; +- reg-names = "gpio", "iocfg_rm", +- "iocfg_br", "iocfg_lm", +- "iocfg_lb", "iocfg_rt", +- "iocfg_lt", "iocfg_tl", +- "eint"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pio 0 0 210>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- +- apmixed: clock-controller@1000c000 { +- compatible = "mediatek,mt6779-apmixed", "syscon"; +- reg = <0 0x1000c000 0 0xe00>; +- #clock-cells = <1>; +- }; +- +- pwrap: pwrap@1000d000 { +- compatible = "mediatek,mt6779-pwrap"; +- reg = <0 0x1000d000 0 0x1000>; +- reg-names = "pwrap"; +- interrupts = ; +- clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_PMIC_AP>; +- clock-names = "spi", "wrap"; +- }; +- +- devapc: devapc@10207000 { +- compatible = "mediatek,mt6779-devapc"; +- reg = <0 0x10207000 0 0x1000>; +- interrupts = ; +- clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>; +- clock-names = "devapc-infra-clock"; +- }; +- +- uart0: serial@11002000 { +- compatible = "mediatek,mt6779-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11002000 0 0x400>; +- interrupts = ; +- clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart1: serial@11003000 { +- compatible = "mediatek,mt6779-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11003000 0 0x400>; +- interrupts = ; +- clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart2: serial@11004000 { +- compatible = "mediatek,mt6779-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11004000 0 0x400>; +- interrupts = ; +- clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- audio: clock-controller@11210000 { +- compatible = "mediatek,mt6779-audio", "syscon"; +- reg = <0 0x11210000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- mfgcfg: clock-controller@13fbf000 { +- compatible = "mediatek,mt6779-mfgcfg", "syscon"; +- reg = <0 0x13fbf000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- mmsys: syscon@14000000 { +- compatible = "mediatek,mt6779-mmsys", "syscon"; +- reg = <0 0x14000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- imgsys: clock-controller@15020000 { +- compatible = "mediatek,mt6779-imgsys", "syscon"; +- reg = <0 0x15020000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- vdecsys: clock-controller@16000000 { +- compatible = "mediatek,mt6779-vdecsys", "syscon"; +- reg = <0 0x16000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- vencsys: clock-controller@17000000 { +- compatible = "mediatek,mt6779-vencsys", "syscon"; +- reg = <0 0x17000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- camsys: clock-controller@1a000000 { +- compatible = "mediatek,mt6779-camsys", "syscon"; +- reg = <0 0x1a000000 0 0x10000>; +- #clock-cells = <1>; +- }; +- +- ipesys: clock-controller@1b000000 { +- compatible = "mediatek,mt6779-ipesys", "syscon"; +- reg = <0 0x1b000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt6795-evb.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt6795-evb.dts +deleted file mode 100644 +index 1ed2f81edeff..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt6795-evb.dts ++++ /dev/null +@@ -1,33 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2015 MediaTek Inc. +- * Author: Mars.C +- */ +- +-/dts-v1/; +-#include "mt6795.dtsi" +- +-/ { +- model = "MediaTek MT6795 Evaluation Board"; +- compatible = "mediatek,mt6795-evb", "mediatek,mt6795"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x1e800000>; +- }; +- +- chosen { +- stdout-path = "serial0:921600n8"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt6795.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt6795.dtsi +deleted file mode 100644 +index c85659d0ff5d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt6795.dtsi ++++ /dev/null +@@ -1,175 +0,0 @@ +-/* +- * Copyright (c) 2015 MediaTek Inc. +- * Author: Mars.C +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License version 2 as +- * published by the Free Software Foundation. +- * +- * This program is distributed in the hope that it will be useful, +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#include +-#include +- +-/ { +- compatible = "mediatek,mt6795"; +- interrupt-parent = <&sysirq>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x000>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x001>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x002>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x003>; +- }; +- +- cpu4: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x100>; +- }; +- +- cpu5: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x101>; +- }; +- +- cpu6: cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x102>; +- }; +- +- cpu7: cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x103>; +- }; +- }; +- +- system_clk: dummy13m { +- compatible = "fixed-clock"; +- clock-frequency = <13000000>; +- #clock-cells = <0>; +- }; +- +- rtc_clk: dummy32k { +- compatible = "fixed-clock"; +- clock-frequency = <32000>; +- #clock-cells = <0>; +- }; +- +- uart_clk: dummy26m { +- compatible = "fixed-clock"; +- clock-frequency = <26000000>; +- #clock-cells = <0>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- }; +- +- sysirq: intpol-controller@10200620 { +- compatible = "mediatek,mt6795-sysirq", +- "mediatek,mt6577-sysirq"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0 0x10200620 0 0x20>; +- }; +- +- gic: interrupt-controller@10221000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- interrupt-controller; +- reg = <0 0x10221000 0 0x1000>, +- <0 0x10222000 0 0x2000>, +- <0 0x10224000 0 0x2000>, +- <0 0x10226000 0 0x2000>; +- }; +- +- uart0: serial@11002000 { +- compatible = "mediatek,mt6795-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11002000 0 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart1: serial@11003000 { +- compatible = "mediatek,mt6795-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11003000 0 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart2: serial@11004000 { +- compatible = "mediatek,mt6795-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11004000 0 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart3: serial@11005000 { +- compatible = "mediatek,mt6795-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11005000 0 0x400>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt6797-evb.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt6797-evb.dts +deleted file mode 100644 +index 2327e752d164..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt6797-evb.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2017 MediaTek Inc. +- * Author: Mars.C +- */ +- +-/dts-v1/; +-#include "mt6797.dtsi" +- +-/ { +- model = "MediaTek MT6797 Evaluation Board"; +- compatible = "mediatek,mt6797-evb", "mediatek,mt6797"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x1e800000>; +- }; +- +- chosen {}; +-}; +- +-&uart0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins_a>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt6797-x20-dev.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt6797-x20-dev.dts +deleted file mode 100644 +index eff9e8dbd076..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt6797-x20-dev.dts ++++ /dev/null +@@ -1,84 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for MediaTek X20 Development Board +- * +- * Copyright (C) 2018, Linaro Ltd. +- * +- */ +- +-/dts-v1/; +- +-#include "mt6797.dtsi" +- +-/ { +- model = "Mediatek X20 Development Board"; +- compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797"; +- +- aliases { +- serial0 = &uart1; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x80000000>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-/* HDMI */ +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins_a>; +- status = "okay"; +-}; +- +-/* HS - I2C2 */ +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins_a>; +- status = "okay"; +-}; +- +-/* HS - I2C3 */ +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins_a>; +- status = "okay"; +-}; +- +-/* LS - I2C0 */ +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pins_a>; +- status = "okay"; +-}; +- +-/* LS - I2C1 */ +-&i2c5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_pins_a>; +- status = "okay"; +-}; +- +-/* POWER_VPROC */ +-&i2c6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c6_pins_a>; +- status = "okay"; +-}; +- +-/* FAN53555 */ +-&i2c7 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c7_pins_a>; +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins_a>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt6797.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt6797.dtsi +deleted file mode 100644 +index 15616231022a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt6797.dtsi ++++ /dev/null +@@ -1,483 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2017 MediaTek Inc. +- * Author: Mars.C +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "mediatek,mt6797"; +- interrupt-parent = <&sysirq>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x000>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x001>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x002>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x003>; +- }; +- +- cpu4: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x100>; +- }; +- +- cpu5: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x101>; +- }; +- +- cpu6: cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x102>; +- }; +- +- cpu7: cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x103>; +- }; +- +- cpu8: cpu@200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- enable-method = "psci"; +- reg = <0x200>; +- }; +- +- cpu9: cpu@201 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- enable-method = "psci"; +- reg = <0x201>; +- }; +- }; +- +- clk26m: oscillator@0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- clock-output-names = "clk26m"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- }; +- +- topckgen: topckgen@10000000 { +- compatible = "mediatek,mt6797-topckgen"; +- reg = <0 0x10000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- infrasys: infracfg_ao@10001000 { +- compatible = "mediatek,mt6797-infracfg", "syscon"; +- reg = <0 0x10001000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- pio: pinctrl@10005000 { +- compatible = "mediatek,mt6797-pinctrl"; +- reg = <0 0x10005000 0 0x1000>, +- <0 0x10002000 0 0x400>, +- <0 0x10002400 0 0x400>, +- <0 0x10002800 0 0x400>, +- <0 0x10002C00 0 0x400>; +- reg-names = "gpio", "iocfgl", "iocfgb", +- "iocfgr", "iocfgt"; +- gpio-controller; +- #gpio-cells = <2>; +- +- uart0_pins_a: uart0 { +- pins0 { +- pinmux = , +- ; +- }; +- }; +- +- uart1_pins_a: uart1 { +- pins1 { +- pinmux = , +- ; +- }; +- }; +- +- i2c0_pins_a: i2c0 { +- pins0 { +- pinmux = , +- ; +- }; +- }; +- +- i2c1_pins_a: i2c1 { +- pins1 { +- pinmux = , +- ; +- }; +- }; +- +- i2c2_pins_a: i2c2 { +- pins2 { +- pinmux = , +- ; +- }; +- }; +- +- i2c3_pins_a: i2c3 { +- pins3 { +- pinmux = , +- ; +- }; +- }; +- +- i2c4_pins_a: i2c4 { +- pins4 { +- pinmux = , +- ; +- }; +- }; +- +- i2c5_pins_a: i2c5 { +- pins5 { +- pinmux = , +- ; +- }; +- }; +- +- i2c6_pins_a: i2c6 { +- pins6 { +- pinmux = , +- ; +- }; +- }; +- +- i2c7_pins_a: i2c7 { +- pins7 { +- pinmux = , +- ; +- }; +- }; +- }; +- +- scpsys: power-controller@10006000 { +- compatible = "mediatek,mt6797-scpsys"; +- #power-domain-cells = <1>; +- reg = <0 0x10006000 0 0x1000>; +- clocks = <&topckgen CLK_TOP_MUX_MFG>, +- <&topckgen CLK_TOP_MUX_MM>, +- <&topckgen CLK_TOP_MUX_VDEC>; +- clock-names = "mfg", "mm", "vdec"; +- infracfg = <&infrasys>; +- }; +- +- watchdog: watchdog@10007000 { +- compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt"; +- reg = <0 0x10007000 0 0x100>; +- }; +- +- apmixedsys: apmixed@1000c000 { +- compatible = "mediatek,mt6797-apmixedsys"; +- reg = <0 0x1000c000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- sysirq: intpol-controller@10200620 { +- compatible = "mediatek,mt6797-sysirq", +- "mediatek,mt6577-sysirq"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0 0x10220620 0 0x20>, +- <0 0x10220690 0 0x10>; +- }; +- +- uart0: serial@11002000 { +- compatible = "mediatek,mt6797-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11002000 0 0x400>; +- interrupts = ; +- clocks = <&infrasys CLK_INFRA_UART0>, +- <&infrasys CLK_INFRA_AP_DMA>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart1: serial@11003000 { +- compatible = "mediatek,mt6797-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11003000 0 0x400>; +- interrupts = ; +- clocks = <&infrasys CLK_INFRA_UART1>, +- <&infrasys CLK_INFRA_AP_DMA>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart2: serial@11004000 { +- compatible = "mediatek,mt6797-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11004000 0 0x400>; +- interrupts = ; +- clocks = <&infrasys CLK_INFRA_UART2>, +- <&infrasys CLK_INFRA_AP_DMA>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart3: serial@11005000 { +- compatible = "mediatek,mt6797-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11005000 0 0x400>; +- interrupts = ; +- clocks = <&infrasys CLK_INFRA_UART3>, +- <&infrasys CLK_INFRA_AP_DMA>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- i2c0: i2c@11007000 { +- compatible = "mediatek,mt6797-i2c", +- "mediatek,mt6577-i2c"; +- id = <0>; +- reg = <0 0x11007000 0 0x1000>, +- <0 0x11000100 0 0x80>; +- interrupts = ; +- clocks = <&infrasys CLK_INFRA_I2C0>, +- <&infrasys CLK_INFRA_AP_DMA>; +- clock-names = "main", "dma"; +- clock-div = <10>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@11008000 { +- compatible = "mediatek,mt6797-i2c", +- "mediatek,mt6577-i2c"; +- id = <1>; +- reg = <0 0x11008000 0 0x1000>, +- <0 0x11000180 0 0x80>; +- interrupts = ; +- clocks = <&infrasys CLK_INFRA_I2C1>, +- <&infrasys CLK_INFRA_AP_DMA>; +- clock-names = "main", "dma"; +- clock-div = <10>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c8: i2c@11009000 { +- compatible = "mediatek,mt6797-i2c", +- "mediatek,mt6577-i2c"; +- id = <8>; +- reg = <0 0x11009000 0 0x1000>, +- <0 0x11000200 0 0x80>; +- interrupts = ; +- clocks = <&infrasys CLK_INFRA_I2C2>, +- <&infrasys CLK_INFRA_AP_DMA>, +- <&infrasys CLK_INFRA_I2C2_ARB>; +- clock-names = "main", "dma", "arb"; +- clock-div = <10>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c9: i2c@1100d000 { +- compatible = "mediatek,mt6797-i2c", +- "mediatek,mt6577-i2c"; +- id = <9>; +- reg = <0 0x1100d000 0 0x1000>, +- <0 0x11000280 0 0x80>; +- interrupts = ; +- clocks = <&infrasys CLK_INFRA_I2C3>, +- <&infrasys CLK_INFRA_AP_DMA>, +- <&infrasys CLK_INFRA_I2C3_ARB>; +- clock-names = "main", "dma", "arb"; +- clock-div = <10>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c6: i2c@1100e000 { +- compatible = "mediatek,mt6797-i2c", +- "mediatek,mt6577-i2c"; +- id = <6>; +- reg = <0 0x1100e000 0 0x1000>, +- <0 0x11000500 0 0x80>; +- interrupts = ; +- clocks = <&infrasys CLK_INFRA_I2C_APPM>, +- <&infrasys CLK_INFRA_AP_DMA>; +- clock-names = "main", "dma"; +- clock-div = <10>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c7: i2c@11010000 { +- compatible = "mediatek,mt6797-i2c", +- "mediatek,mt6577-i2c"; +- id = <7>; +- reg = <0 0x11010000 0 0x1000>, +- <0 0x11000580 0 0x80>; +- interrupts = ; +- clocks = <&infrasys CLK_INFRA_I2C_GPUPM>, +- <&infrasys CLK_INFRA_AP_DMA>; +- clock-names = "main", "dma"; +- clock-div = <10>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@11011000 { +- compatible = "mediatek,mt6797-i2c", +- "mediatek,mt6577-i2c"; +- id = <4>; +- reg = <0 0x11011000 0 0x1000>, +- <0 0x11000300 0 0x80>; +- interrupts = ; +- clocks = <&infrasys CLK_INFRA_I2C4>, +- <&infrasys CLK_INFRA_AP_DMA>; +- clock-names = "main", "dma"; +- clock-div = <10>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@11013000 { +- compatible = "mediatek,mt6797-i2c", +- "mediatek,mt6577-i2c"; +- id = <2>; +- reg = <0 0x11013000 0 0x1000>, +- <0 0x11000400 0 0x80>; +- interrupts = ; +- clocks = <&infrasys CLK_INFRA_I2C2_IMM>, +- <&infrasys CLK_INFRA_AP_DMA>, +- <&infrasys CLK_INFRA_I2C2_ARB>; +- clock-names = "main", "dma", "arb"; +- clock-div = <10>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@11014000 { +- compatible = "mediatek,mt6797-i2c", +- "mediatek,mt6577-i2c"; +- id = <3>; +- reg = <0 0x11014000 0 0x1000>, +- <0 0x11000480 0 0x80>; +- interrupts = ; +- clocks = <&infrasys CLK_INFRA_I2C3_IMM>, +- <&infrasys CLK_INFRA_AP_DMA>, +- <&infrasys CLK_INFRA_I2C3_ARB>; +- clock-names = "main", "dma", "arb"; +- clock-div = <10>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c5: i2c@1101c000 { +- compatible = "mediatek,mt6797-i2c", +- "mediatek,mt6577-i2c"; +- id = <5>; +- reg = <0 0x1101c000 0 0x1000>, +- <0 0x11000380 0 0x80>; +- interrupts = ; +- clocks = <&infrasys CLK_INFRA_I2C5>, +- <&infrasys CLK_INFRA_AP_DMA>; +- clock-names = "main", "dma"; +- clock-div = <10>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- mmsys: syscon@14000000 { +- compatible = "mediatek,mt6797-mmsys", "syscon"; +- reg = <0 0x14000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- imgsys: imgsys_config@15000000 { +- compatible = "mediatek,mt6797-imgsys", "syscon"; +- reg = <0 0x15000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- vdecsys: vdec_gcon@16000000 { +- compatible = "mediatek,mt6797-vdecsys", "syscon"; +- reg = <0 0x16000000 0 0x10000>; +- #clock-cells = <1>; +- }; +- +- vencsys: venc_gcon@17000000 { +- compatible = "mediatek,mt6797-vencsys", "syscon"; +- reg = <0 0x17000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- gic: interrupt-controller@19000000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- interrupts = ; +- interrupt-controller; +- reg = <0 0x19000000 0 0x10000>, /* GICD */ +- <0 0x19200000 0 0x200000>, /* GICR */ +- <0 0x10240000 0 0x2000>; /* GICC */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt7622-bananapi-bpi-r64.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt7622-bananapi-bpi-r64.dts +deleted file mode 100644 +index 2f77dc40b9b8..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt7622-bananapi-bpi-r64.dts ++++ /dev/null +@@ -1,602 +0,0 @@ +-/* +- * Copyright (c) 2018 MediaTek Inc. +- * Author: Ryder Lee +- * +- * SPDX-License-Identifier: (GPL-2.0 OR MIT) +- */ +- +-/dts-v1/; +-#include +-#include +- +-#include "mt7622.dtsi" +-#include "mt6380.dtsi" +- +-/ { +- model = "Bananapi BPI-R64"; +- compatible = "bananapi,bpi-r64", "mediatek,mt7622"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; +- }; +- +- cpus { +- cpu@0 { +- proc-supply = <&mt6380_vcpu_reg>; +- sram-supply = <&mt6380_vm_reg>; +- }; +- +- cpu@1 { +- proc-supply = <&mt6380_vcpu_reg>; +- sram-supply = <&mt6380_vm_reg>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- factory { +- label = "factory"; +- linux,code = ; +- gpios = <&pio 0 GPIO_ACTIVE_HIGH>; +- }; +- +- wps { +- label = "wps"; +- linux,code = ; +- gpios = <&pio 102 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- green { +- label = "bpi-r64:pio:green"; +- gpios = <&pio 89 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- red { +- label = "bpi-r64:pio:red"; +- gpios = <&pio 88 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- memory { +- reg = <0 0x40000000 0 0x40000000>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_5v: regulator-5v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&bch { +- status = "disabled"; +-}; +- +-&btif { +- status = "okay"; +-}; +- +-&cir { +- pinctrl-names = "default"; +- pinctrl-0 = <&irrx_pins>; +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "2500base-x"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- +- gmac1: mac@1 { +- compatible = "mediatek,eth-mac"; +- reg = <1>; +- phy-mode = "rgmii"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- pause; +- }; +- }; +- +- mdio: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch@0 { +- compatible = "mediatek,mt7531"; +- reg = <0>; +- reset-gpios = <&pio 54 0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "wan"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan0"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan1"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan2"; +- }; +- +- port@4 { +- reg = <4>; +- label = "lan3"; +- }; +- +- port@6 { +- reg = <6>; +- label = "cpu"; +- ethernet = <&gmac0>; +- phy-mode = "2500base-x"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- }; +- }; +- +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "okay"; +-}; +- +-&mmc0 { +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&emmc_pins_default>; +- pinctrl-1 = <&emmc_pins_uhs>; +- status = "okay"; +- bus-width = <8>; +- max-frequency = <50000000>; +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_1p8v>; +- assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; +- non-removable; +-}; +- +-&mmc1 { +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&sd0_pins_default>; +- pinctrl-1 = <&sd0_pins_uhs>; +- status = "okay"; +- bus-width = <4>; +- max-frequency = <50000000>; +- cap-sd-highspeed; +- r_smpl = <1>; +- cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_3p3v>; +- assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; +-}; +- +-&nandc { +- pinctrl-names = "default"; +- pinctrl-0 = <¶llel_nand_pins>; +- status = "disabled"; +-}; +- +-&nor_flash { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_nor_pins>; +- status = "disabled"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; +- status = "okay"; +- +- pcie@0,0 { +- status = "okay"; +- }; +- +- pcie@1,0 { +- status = "okay"; +- }; +-}; +- +-&pio { +- /* Attention: GPIO 90 is used to switch between PCIe@1,0 and +- * SATA functions. i.e. output-high: PCIe, output-low: SATA +- */ +- asm_sel { +- gpio-hog; +- gpios = <90 GPIO_ACTIVE_HIGH>; +- output-high; +- }; +- +- /* eMMC is shared pin with parallel NAND */ +- emmc_pins_default: emmc-pins-default { +- mux { +- function = "emmc", "emmc_rst"; +- groups = "emmc"; +- }; +- +- /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", +- * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, +- * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively +- */ +- conf-cmd-dat { +- pins = "NDL0", "NDL1", "NDL2", +- "NDL3", "NDL4", "NDL5", +- "NDL6", "NDL7", "NRB"; +- input-enable; +- bias-pull-up; +- }; +- +- conf-clk { +- pins = "NCLE"; +- bias-pull-down; +- }; +- }; +- +- emmc_pins_uhs: emmc-pins-uhs { +- mux { +- function = "emmc"; +- groups = "emmc"; +- }; +- +- conf-cmd-dat { +- pins = "NDL0", "NDL1", "NDL2", +- "NDL3", "NDL4", "NDL5", +- "NDL6", "NDL7", "NRB"; +- input-enable; +- drive-strength = <4>; +- bias-pull-up; +- }; +- +- conf-clk { +- pins = "NCLE"; +- drive-strength = <4>; +- bias-pull-down; +- }; +- }; +- +- eth_pins: eth-pins { +- mux { +- function = "eth"; +- groups = "mdc_mdio", "rgmii_via_gmac2"; +- }; +- }; +- +- i2c1_pins: i2c1-pins { +- mux { +- function = "i2c"; +- groups = "i2c1_0"; +- }; +- }; +- +- i2c2_pins: i2c2-pins { +- mux { +- function = "i2c"; +- groups = "i2c2_0"; +- }; +- }; +- +- i2s1_pins: i2s1-pins { +- mux { +- function = "i2s"; +- groups = "i2s_out_mclk_bclk_ws", +- "i2s1_in_data", +- "i2s1_out_data"; +- }; +- +- conf { +- pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK", +- "I2S_WS", "I2S_MCLK"; +- drive-strength = <12>; +- bias-pull-down; +- }; +- }; +- +- irrx_pins: irrx-pins { +- mux { +- function = "ir"; +- groups = "ir_1_rx"; +- }; +- }; +- +- irtx_pins: irtx-pins { +- mux { +- function = "ir"; +- groups = "ir_1_tx"; +- }; +- }; +- +- /* Parallel nand is shared pin with eMMC */ +- parallel_nand_pins: parallel-nand-pins { +- mux { +- function = "flash"; +- groups = "par_nand"; +- }; +- }; +- +- pcie0_pins: pcie0-pins { +- mux { +- function = "pcie"; +- groups = "pcie0_pad_perst", +- "pcie0_1_waken", +- "pcie0_1_clkreq"; +- }; +- }; +- +- pcie1_pins: pcie1-pins { +- mux { +- function = "pcie"; +- groups = "pcie1_pad_perst", +- "pcie1_0_waken", +- "pcie1_0_clkreq"; +- }; +- }; +- +- pmic_bus_pins: pmic-bus-pins { +- mux { +- function = "pmic"; +- groups = "pmic_bus"; +- }; +- }; +- +- pwm_pins: pwm-pins { +- mux { +- function = "pwm"; +- groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */ +- "pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */ +- "pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */ +- "pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */ +- "pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */ +- "pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */ +- }; +- }; +- +- wled_pins: wled-pins { +- mux { +- function = "led"; +- groups = "wled"; +- }; +- }; +- +- sd0_pins_default: sd0-pins-default { +- mux { +- function = "sd"; +- groups = "sd_0"; +- }; +- +- /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", +- * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, +- * DAT2, DAT3, CMD, CLK for SD respectively. +- */ +- conf-cmd-data { +- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", +- "I2S2_IN","I2S4_OUT"; +- input-enable; +- drive-strength = <8>; +- bias-pull-up; +- }; +- conf-clk { +- pins = "I2S3_OUT"; +- drive-strength = <12>; +- bias-pull-down; +- }; +- conf-cd { +- pins = "TXD3"; +- bias-pull-up; +- }; +- }; +- +- sd0_pins_uhs: sd0-pins-uhs { +- mux { +- function = "sd"; +- groups = "sd_0"; +- }; +- +- conf-cmd-data { +- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", +- "I2S2_IN","I2S4_OUT"; +- input-enable; +- bias-pull-up; +- }; +- +- conf-clk { +- pins = "I2S3_OUT"; +- bias-pull-down; +- }; +- }; +- +- /* Serial NAND is shared pin with SPI-NOR */ +- serial_nand_pins: serial-nand-pins { +- mux { +- function = "flash"; +- groups = "snfi"; +- }; +- }; +- +- spic0_pins: spic0-pins { +- mux { +- function = "spi"; +- groups = "spic0_0"; +- }; +- }; +- +- spic1_pins: spic1-pins { +- mux { +- function = "spi"; +- groups = "spic1_0"; +- }; +- }; +- +- /* SPI-NOR is shared pin with serial NAND */ +- spi_nor_pins: spi-nor-pins { +- mux { +- function = "flash"; +- groups = "spi_nor"; +- }; +- }; +- +- /* serial NAND is shared pin with SPI-NOR */ +- serial_nand_pins: serial-nand-pins { +- mux { +- function = "flash"; +- groups = "snfi"; +- }; +- }; +- +- uart0_pins: uart0-pins { +- mux { +- function = "uart"; +- groups = "uart0_0_tx_rx" ; +- }; +- }; +- +- uart2_pins: uart2-pins { +- mux { +- function = "uart"; +- groups = "uart2_1_tx_rx" ; +- }; +- }; +- +- watchdog_pins: watchdog-pins { +- mux { +- function = "watchdog"; +- groups = "watchdog"; +- }; +- }; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm_pins>; +- status = "okay"; +-}; +- +-&pwrap { +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_bus_pins>; +- +- status = "okay"; +-}; +- +-&sata { +- status = "disable"; +-}; +- +-&sata_phy { +- status = "disable"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spic0_pins>; +- status = "okay"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spic1_pins>; +-}; +- +-&ssusb { +- vusb33-supply = <®_3p3v>; +- vbus-supply = <®_5v>; +- status = "okay"; +-}; +- +-&u3phy { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +-}; +- +-&watchdog { +- pinctrl-names = "default"; +- pinctrl-0 = <&watchdog_pins>; +- status = "okay"; +-}; +- +-&wmac { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt7622-rfb1.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt7622-rfb1.dts +deleted file mode 100644 +index f2dc850010f1..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt7622-rfb1.dts ++++ /dev/null +@@ -1,575 +0,0 @@ +-/* +- * Copyright (c) 2017 MediaTek Inc. +- * Author: Ming Huang +- * Sean Wang +- * +- * SPDX-License-Identifier: (GPL-2.0 OR MIT) +- */ +- +-/dts-v1/; +-#include +-#include +- +-#include "mt7622.dtsi" +-#include "mt6380.dtsi" +- +-/ { +- model = "MediaTek MT7622 RFB1 board"; +- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; +- }; +- +- cpus { +- cpu@0 { +- proc-supply = <&mt6380_vcpu_reg>; +- sram-supply = <&mt6380_vm_reg>; +- }; +- +- cpu@1 { +- proc-supply = <&mt6380_vcpu_reg>; +- sram-supply = <&mt6380_vm_reg>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- poll-interval = <100>; +- +- factory { +- label = "factory"; +- linux,code = ; +- gpios = <&pio 0 0>; +- }; +- +- wps { +- label = "wps"; +- linux,code = ; +- gpios = <&pio 102 0>; +- }; +- }; +- +- memory { +- reg = <0 0x40000000 0 0x20000000>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_5v: regulator-5v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&bch { +- status = "disabled"; +-}; +- +-&btif { +- status = "okay"; +-}; +- +-&cir { +- pinctrl-names = "default"; +- pinctrl-0 = <&irrx_pins>; +- status = "okay"; +-}; +- +-ð { +- pinctrl-names = "default"; +- pinctrl-0 = <ð_pins>; +- status = "okay"; +- +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "2500base-x"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- +- mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch@0 { +- compatible = "mediatek,mt7531"; +- reg = <0>; +- reset-gpios = <&pio 54 0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan0"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan1"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan3"; +- }; +- +- port@4 { +- reg = <4>; +- label = "wan"; +- }; +- +- port@6 { +- reg = <6>; +- label = "cpu"; +- ethernet = <&gmac0>; +- phy-mode = "2500base-x"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- }; +- }; +- +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "okay"; +-}; +- +-&mmc0 { +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&emmc_pins_default>; +- pinctrl-1 = <&emmc_pins_uhs>; +- status = "okay"; +- bus-width = <8>; +- max-frequency = <50000000>; +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_1p8v>; +- assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; +- non-removable; +-}; +- +-&mmc1 { +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&sd0_pins_default>; +- pinctrl-1 = <&sd0_pins_uhs>; +- status = "okay"; +- bus-width = <4>; +- max-frequency = <50000000>; +- cap-sd-highspeed; +- r_smpl = <1>; +- cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_3p3v>; +- assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; +-}; +- +-&nandc { +- pinctrl-names = "default"; +- pinctrl-0 = <¶llel_nand_pins>; +- status = "disabled"; +-}; +- +-&nor_flash { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_nor_pins>; +- status = "disabled"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- }; +-}; +- +-&pcie { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>; +- status = "okay"; +- +- pcie@0,0 { +- status = "okay"; +- }; +-}; +- +-&pio { +- /* eMMC is shared pin with parallel NAND */ +- emmc_pins_default: emmc-pins-default { +- mux { +- function = "emmc", "emmc_rst"; +- groups = "emmc"; +- }; +- +- /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", +- * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, +- * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively +- */ +- conf-cmd-dat { +- pins = "NDL0", "NDL1", "NDL2", +- "NDL3", "NDL4", "NDL5", +- "NDL6", "NDL7", "NRB"; +- input-enable; +- bias-pull-up; +- }; +- +- conf-clk { +- pins = "NCLE"; +- bias-pull-down; +- }; +- }; +- +- emmc_pins_uhs: emmc-pins-uhs { +- mux { +- function = "emmc"; +- groups = "emmc"; +- }; +- +- conf-cmd-dat { +- pins = "NDL0", "NDL1", "NDL2", +- "NDL3", "NDL4", "NDL5", +- "NDL6", "NDL7", "NRB"; +- input-enable; +- drive-strength = <4>; +- bias-pull-up; +- }; +- +- conf-clk { +- pins = "NCLE"; +- drive-strength = <4>; +- bias-pull-down; +- }; +- }; +- +- eth_pins: eth-pins { +- mux { +- function = "eth"; +- groups = "mdc_mdio", "rgmii_via_gmac2"; +- }; +- }; +- +- i2c1_pins: i2c1-pins { +- mux { +- function = "i2c"; +- groups = "i2c1_0"; +- }; +- }; +- +- i2c2_pins: i2c2-pins { +- mux { +- function = "i2c"; +- groups = "i2c2_0"; +- }; +- }; +- +- i2s1_pins: i2s1-pins { +- mux { +- function = "i2s"; +- groups = "i2s_out_mclk_bclk_ws", +- "i2s1_in_data", +- "i2s1_out_data"; +- }; +- +- conf { +- pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK", +- "I2S_WS", "I2S_MCLK"; +- drive-strength = <12>; +- bias-pull-down; +- }; +- }; +- +- irrx_pins: irrx-pins { +- mux { +- function = "ir"; +- groups = "ir_1_rx"; +- }; +- }; +- +- irtx_pins: irtx-pins { +- mux { +- function = "ir"; +- groups = "ir_1_tx"; +- }; +- }; +- +- /* Parallel nand is shared pin with eMMC */ +- parallel_nand_pins: parallel-nand-pins { +- mux { +- function = "flash"; +- groups = "par_nand"; +- }; +- }; +- +- pcie0_pins: pcie0-pins { +- mux { +- function = "pcie"; +- groups = "pcie0_pad_perst", +- "pcie0_1_waken", +- "pcie0_1_clkreq"; +- }; +- }; +- +- pcie1_pins: pcie1-pins { +- mux { +- function = "pcie"; +- groups = "pcie1_pad_perst", +- "pcie1_0_waken", +- "pcie1_0_clkreq"; +- }; +- }; +- +- pmic_bus_pins: pmic-bus-pins { +- mux { +- function = "pmic"; +- groups = "pmic_bus"; +- }; +- }; +- +- pwm7_pins: pwm1-2-pins { +- mux { +- function = "pwm"; +- groups = "pwm_ch7_2"; +- }; +- }; +- +- wled_pins: wled-pins { +- mux { +- function = "led"; +- groups = "wled"; +- }; +- }; +- +- sd0_pins_default: sd0-pins-default { +- mux { +- function = "sd"; +- groups = "sd_0"; +- }; +- +- /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", +- * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, +- * DAT2, DAT3, CMD, CLK for SD respectively. +- */ +- conf-cmd-data { +- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", +- "I2S2_IN","I2S4_OUT"; +- input-enable; +- drive-strength = <8>; +- bias-pull-up; +- }; +- conf-clk { +- pins = "I2S3_OUT"; +- drive-strength = <12>; +- bias-pull-down; +- }; +- conf-cd { +- pins = "TXD3"; +- bias-pull-up; +- }; +- }; +- +- sd0_pins_uhs: sd0-pins-uhs { +- mux { +- function = "sd"; +- groups = "sd_0"; +- }; +- +- conf-cmd-data { +- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", +- "I2S2_IN","I2S4_OUT"; +- input-enable; +- bias-pull-up; +- }; +- +- conf-clk { +- pins = "I2S3_OUT"; +- bias-pull-down; +- }; +- }; +- +- /* Serial NAND is shared pin with SPI-NOR */ +- serial_nand_pins: serial-nand-pins { +- mux { +- function = "flash"; +- groups = "snfi"; +- }; +- }; +- +- spic0_pins: spic0-pins { +- mux { +- function = "spi"; +- groups = "spic0_0"; +- }; +- }; +- +- spic1_pins: spic1-pins { +- mux { +- function = "spi"; +- groups = "spic1_0"; +- }; +- }; +- +- /* SPI-NOR is shared pin with serial NAND */ +- spi_nor_pins: spi-nor-pins { +- mux { +- function = "flash"; +- groups = "spi_nor"; +- }; +- }; +- +- /* serial NAND is shared pin with SPI-NOR */ +- serial_nand_pins: serial-nand-pins { +- mux { +- function = "flash"; +- groups = "snfi"; +- }; +- }; +- +- uart0_pins: uart0-pins { +- mux { +- function = "uart"; +- groups = "uart0_0_tx_rx" ; +- }; +- }; +- +- uart2_pins: uart2-pins { +- mux { +- function = "uart"; +- groups = "uart2_1_tx_rx" ; +- }; +- }; +- +- watchdog_pins: watchdog-pins { +- mux { +- function = "watchdog"; +- groups = "watchdog"; +- }; +- }; +- +- wmac_pins: wmac-pins { +- mux { +- function = "antsel"; +- groups = "antsel0", "antsel1", "antsel2", "antsel3", +- "antsel4", "antsel5", "antsel6", "antsel7", +- "antsel8", "antsel9", "antsel12", "antsel13", +- "antsel14", "antsel15", "antsel16", "antsel17"; +- }; +- }; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm7_pins>; +- status = "okay"; +-}; +- +-&pwrap { +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_bus_pins>; +- +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&sata_phy { +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spic0_pins>; +- status = "okay"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spic1_pins>; +- status = "okay"; +-}; +- +-&ssusb { +- vusb33-supply = <®_3p3v>; +- vbus-supply = <®_5v>; +- status = "okay"; +-}; +- +-&u3phy { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "okay"; +-}; +- +-&watchdog { +- pinctrl-names = "default"; +- pinctrl-0 = <&watchdog_pins>; +- status = "okay"; +-}; +- +-&wmac { +- pinctrl-names = "default"; +- pinctrl-0 = <&wmac_pins>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt7622.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt7622.dtsi +deleted file mode 100644 +index 890a942ec608..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt7622.dtsi ++++ /dev/null +@@ -1,951 +0,0 @@ +-/* +- * Copyright (c) 2017 MediaTek Inc. +- * Author: Ming Huang +- * Sean Wang +- * +- * SPDX-License-Identifier: (GPL-2.0 OR MIT) +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "mediatek,mt7622"; +- interrupt-parent = <&sysirq>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- opp-300000000 { +- opp-hz = /bits/ 64 <30000000>; +- opp-microvolt = <950000>; +- }; +- +- opp-437500000 { +- opp-hz = /bits/ 64 <437500000>; +- opp-microvolt = <1000000>; +- }; +- +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <1050000>; +- }; +- +- opp-812500000 { +- opp-hz = /bits/ 64 <812500000>; +- opp-microvolt = <1100000>; +- }; +- +- opp-1025000000 { +- opp-hz = /bits/ 64 <1025000000>; +- opp-microvolt = <1150000>; +- }; +- +- opp-1137500000 { +- opp-hz = /bits/ 64 <1137500000>; +- opp-microvolt = <1200000>; +- }; +- +- opp-1262500000 { +- opp-hz = /bits/ 64 <1262500000>; +- opp-microvolt = <1250000>; +- }; +- +- opp-1350000000 { +- opp-hz = /bits/ 64 <1350000000>; +- opp-microvolt = <1310000>; +- }; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- clocks = <&infracfg CLK_INFRA_MUX1_SEL>, +- <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; +- clock-names = "cpu", "intermediate"; +- operating-points-v2 = <&cpu_opp_table>; +- #cooling-cells = <2>; +- enable-method = "psci"; +- clock-frequency = <1300000000>; +- cci-control-port = <&cci_control2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- clocks = <&infracfg CLK_INFRA_MUX1_SEL>, +- <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; +- clock-names = "cpu", "intermediate"; +- operating-points-v2 = <&cpu_opp_table>; +- #cooling-cells = <2>; +- enable-method = "psci"; +- clock-frequency = <1300000000>; +- cci-control-port = <&cci_control2>; +- }; +- }; +- +- pwrap_clk: dummy40m { +- compatible = "fixed-clock"; +- clock-frequency = <40000000>; +- #clock-cells = <0>; +- }; +- +- clk25m: oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- clock-output-names = "clkxtal"; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ +- secmon_reserved: secmon@43000000 { +- reg = <0 0x43000000 0 0x30000>; +- no-map; +- }; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <1000>; +- polling-delay = <1000>; +- +- thermal-sensors = <&thermal 0>; +- +- trips { +- cpu_passive: cpu-passive { +- temperature = <47000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_active: cpu-active { +- temperature = <67000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- cpu_hot: cpu-hot { +- temperature = <87000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- cpu-crit { +- temperature = <107000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_passive>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- +- map1 { +- trip = <&cpu_active>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- +- map2 { +- trip = <&cpu_hot>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- }; +- +- infracfg: infracfg@10000000 { +- compatible = "mediatek,mt7622-infracfg", +- "syscon"; +- reg = <0 0x10000000 0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pwrap: pwrap@10001000 { +- compatible = "mediatek,mt7622-pwrap"; +- reg = <0 0x10001000 0 0x250>; +- reg-names = "pwrap"; +- clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>; +- clock-names = "spi", "wrap"; +- resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>; +- reset-names = "pwrap"; +- interrupts = ; +- status = "disabled"; +- }; +- +- pericfg: pericfg@10002000 { +- compatible = "mediatek,mt7622-pericfg", +- "syscon"; +- reg = <0 0x10002000 0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- scpsys: power-controller@10006000 { +- compatible = "mediatek,mt7622-scpsys", +- "syscon"; +- #power-domain-cells = <1>; +- reg = <0 0x10006000 0 0x1000>; +- interrupts = , +- , +- , +- ; +- infracfg = <&infracfg>; +- clocks = <&topckgen CLK_TOP_HIF_SEL>; +- clock-names = "hif_sel"; +- }; +- +- cir: cir@10009000 { +- compatible = "mediatek,mt7622-cir"; +- reg = <0 0x10009000 0 0x1000>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_IRRX_PD>, +- <&topckgen CLK_TOP_AXI_SEL>; +- clock-names = "clk", "bus"; +- status = "disabled"; +- }; +- +- sysirq: interrupt-controller@10200620 { +- compatible = "mediatek,mt7622-sysirq", +- "mediatek,mt6577-sysirq"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0 0x10200620 0 0x20>; +- }; +- +- efuse: efuse@10206000 { +- compatible = "mediatek,mt7622-efuse", +- "mediatek,efuse"; +- reg = <0 0x10206000 0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- thermal_calibration: calib@198 { +- reg = <0x198 0xc>; +- }; +- }; +- +- apmixedsys: apmixedsys@10209000 { +- compatible = "mediatek,mt7622-apmixedsys", +- "syscon"; +- reg = <0 0x10209000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- topckgen: topckgen@10210000 { +- compatible = "mediatek,mt7622-topckgen", +- "syscon"; +- reg = <0 0x10210000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- rng: rng@1020f000 { +- compatible = "mediatek,mt7622-rng", +- "mediatek,mt7623-rng"; +- reg = <0 0x1020f000 0 0x1000>; +- clocks = <&infracfg CLK_INFRA_TRNG>; +- clock-names = "rng"; +- }; +- +- pio: pinctrl@10211000 { +- compatible = "mediatek,mt7622-pinctrl"; +- reg = <0 0x10211000 0 0x1000>, +- <0 0x10005000 0 0x1000>; +- reg-names = "base", "eint"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pio 0 0 103>; +- interrupt-controller; +- interrupts = ; +- interrupt-parent = <&gic>; +- #interrupt-cells = <2>; +- }; +- +- watchdog: watchdog@10212000 { +- compatible = "mediatek,mt7622-wdt", +- "mediatek,mt6589-wdt"; +- reg = <0 0x10212000 0 0x800>; +- }; +- +- rtc: rtc@10212800 { +- compatible = "mediatek,mt7622-rtc", +- "mediatek,soc-rtc"; +- reg = <0 0x10212800 0 0x200>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_RTC>; +- clock-names = "rtc"; +- }; +- +- gic: interrupt-controller@10300000 { +- compatible = "arm,gic-400"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0 0x10310000 0 0x1000>, +- <0 0x10320000 0 0x1000>, +- <0 0x10340000 0 0x2000>, +- <0 0x10360000 0 0x2000>; +- }; +- +- cci: cci@10390000 { +- compatible = "arm,cci-400"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0 0x10390000 0 0x1000>; +- ranges = <0 0 0x10390000 0x10000>; +- +- cci_control0: slave-if@1000 { +- compatible = "arm,cci-400-ctrl-if"; +- interface-type = "ace-lite"; +- reg = <0x1000 0x1000>; +- }; +- +- cci_control1: slave-if@4000 { +- compatible = "arm,cci-400-ctrl-if"; +- interface-type = "ace"; +- reg = <0x4000 0x1000>; +- }; +- +- cci_control2: slave-if@5000 { +- compatible = "arm,cci-400-ctrl-if"; +- interface-type = "ace"; +- reg = <0x5000 0x1000>; +- }; +- +- pmu@9000 { +- compatible = "arm,cci-400-pmu,r1"; +- reg = <0x9000 0x5000>; +- interrupts = , +- , +- , +- , +- ; +- }; +- }; +- +- auxadc: adc@11001000 { +- compatible = "mediatek,mt7622-auxadc"; +- reg = <0 0x11001000 0 0x1000>; +- clocks = <&pericfg CLK_PERI_AUXADC_PD>; +- clock-names = "main"; +- #io-channel-cells = <1>; +- }; +- +- uart0: serial@11002000 { +- compatible = "mediatek,mt7622-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11002000 0 0x400>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_UART_SEL>, +- <&pericfg CLK_PERI_UART0_PD>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart1: serial@11003000 { +- compatible = "mediatek,mt7622-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11003000 0 0x400>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_UART_SEL>, +- <&pericfg CLK_PERI_UART1_PD>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart2: serial@11004000 { +- compatible = "mediatek,mt7622-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11004000 0 0x400>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_UART_SEL>, +- <&pericfg CLK_PERI_UART2_PD>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart3: serial@11005000 { +- compatible = "mediatek,mt7622-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11005000 0 0x400>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_UART_SEL>, +- <&pericfg CLK_PERI_UART3_PD>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- pwm: pwm@11006000 { +- compatible = "mediatek,mt7622-pwm"; +- reg = <0 0x11006000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_PWM_SEL>, +- <&pericfg CLK_PERI_PWM_PD>, +- <&pericfg CLK_PERI_PWM1_PD>, +- <&pericfg CLK_PERI_PWM2_PD>, +- <&pericfg CLK_PERI_PWM3_PD>, +- <&pericfg CLK_PERI_PWM4_PD>, +- <&pericfg CLK_PERI_PWM5_PD>, +- <&pericfg CLK_PERI_PWM6_PD>; +- clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4", +- "pwm5", "pwm6"; +- status = "disabled"; +- }; +- +- i2c0: i2c@11007000 { +- compatible = "mediatek,mt7622-i2c"; +- reg = <0 0x11007000 0 0x90>, +- <0 0x11000100 0 0x80>; +- interrupts = ; +- clock-div = <16>; +- clocks = <&pericfg CLK_PERI_I2C0_PD>, +- <&pericfg CLK_PERI_AP_DMA_PD>; +- clock-names = "main", "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@11008000 { +- compatible = "mediatek,mt7622-i2c"; +- reg = <0 0x11008000 0 0x90>, +- <0 0x11000180 0 0x80>; +- interrupts = ; +- clock-div = <16>; +- clocks = <&pericfg CLK_PERI_I2C1_PD>, +- <&pericfg CLK_PERI_AP_DMA_PD>; +- clock-names = "main", "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@11009000 { +- compatible = "mediatek,mt7622-i2c"; +- reg = <0 0x11009000 0 0x90>, +- <0 0x11000200 0 0x80>; +- interrupts = ; +- clock-div = <16>; +- clocks = <&pericfg CLK_PERI_I2C2_PD>, +- <&pericfg CLK_PERI_AP_DMA_PD>; +- clock-names = "main", "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi0: spi@1100a000 { +- compatible = "mediatek,mt7622-spi"; +- reg = <0 0x1100a000 0 0x100>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, +- <&topckgen CLK_TOP_SPI0_SEL>, +- <&pericfg CLK_PERI_SPI0_PD>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- thermal: thermal@1100b000 { +- #thermal-sensor-cells = <1>; +- compatible = "mediatek,mt7622-thermal"; +- reg = <0 0x1100b000 0 0x1000>; +- interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>; +- clocks = <&pericfg CLK_PERI_THERM_PD>, +- <&pericfg CLK_PERI_AUXADC_PD>; +- clock-names = "therm", "auxadc"; +- resets = <&pericfg MT7622_PERI_THERM_SW_RST>; +- reset-names = "therm"; +- mediatek,auxadc = <&auxadc>; +- mediatek,apmixedsys = <&apmixedsys>; +- nvmem-cells = <&thermal_calibration>; +- nvmem-cell-names = "calibration-data"; +- }; +- +- btif: serial@1100c000 { +- compatible = "mediatek,mt7622-btif", +- "mediatek,mtk-btif"; +- reg = <0 0x1100c000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_BTIF_PD>; +- clock-names = "main"; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- +- bluetooth { +- compatible = "mediatek,mt7622-bluetooth"; +- power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; +- clocks = <&clk25m>; +- clock-names = "ref"; +- }; +- }; +- +- nandc: nfi@1100d000 { +- compatible = "mediatek,mt7622-nfc"; +- reg = <0 0x1100D000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_NFI_PD>, +- <&pericfg CLK_PERI_SNFI_PD>; +- clock-names = "nfi_clk", "pad_clk"; +- ecc-engine = <&bch>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- bch: ecc@1100e000 { +- compatible = "mediatek,mt7622-ecc"; +- reg = <0 0x1100e000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_NFIECC_PD>; +- clock-names = "nfiecc_clk"; +- status = "disabled"; +- }; +- +- nor_flash: spi@11014000 { +- compatible = "mediatek,mt7622-nor", +- "mediatek,mt8173-nor"; +- reg = <0 0x11014000 0 0xe0>; +- clocks = <&pericfg CLK_PERI_FLASH_PD>, +- <&topckgen CLK_TOP_FLASH_SEL>; +- clock-names = "spi", "sf"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi1: spi@11016000 { +- compatible = "mediatek,mt7622-spi"; +- reg = <0 0x11016000 0 0x100>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, +- <&topckgen CLK_TOP_SPI1_SEL>, +- <&pericfg CLK_PERI_SPI1_PD>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- uart4: serial@11019000 { +- compatible = "mediatek,mt7622-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11019000 0 0x400>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_UART_SEL>, +- <&pericfg CLK_PERI_UART4_PD>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- audsys: clock-controller@11220000 { +- compatible = "mediatek,mt7622-audsys", "syscon"; +- reg = <0 0x11220000 0 0x2000>; +- #clock-cells = <1>; +- +- afe: audio-controller { +- compatible = "mediatek,mt7622-audio"; +- interrupts = , +- ; +- interrupt-names = "afe", "asys"; +- +- clocks = <&infracfg CLK_INFRA_AUDIO_PD>, +- <&topckgen CLK_TOP_AUD1_SEL>, +- <&topckgen CLK_TOP_AUD2_SEL>, +- <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>, +- <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>, +- <&topckgen CLK_TOP_I2S0_MCK_SEL>, +- <&topckgen CLK_TOP_I2S1_MCK_SEL>, +- <&topckgen CLK_TOP_I2S2_MCK_SEL>, +- <&topckgen CLK_TOP_I2S3_MCK_SEL>, +- <&topckgen CLK_TOP_I2S0_MCK_DIV>, +- <&topckgen CLK_TOP_I2S1_MCK_DIV>, +- <&topckgen CLK_TOP_I2S2_MCK_DIV>, +- <&topckgen CLK_TOP_I2S3_MCK_DIV>, +- <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>, +- <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>, +- <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>, +- <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>, +- <&audsys CLK_AUDIO_I2SO1>, +- <&audsys CLK_AUDIO_I2SO2>, +- <&audsys CLK_AUDIO_I2SO3>, +- <&audsys CLK_AUDIO_I2SO4>, +- <&audsys CLK_AUDIO_I2SIN1>, +- <&audsys CLK_AUDIO_I2SIN2>, +- <&audsys CLK_AUDIO_I2SIN3>, +- <&audsys CLK_AUDIO_I2SIN4>, +- <&audsys CLK_AUDIO_ASRCO1>, +- <&audsys CLK_AUDIO_ASRCO2>, +- <&audsys CLK_AUDIO_ASRCO3>, +- <&audsys CLK_AUDIO_ASRCO4>, +- <&audsys CLK_AUDIO_AFE>, +- <&audsys CLK_AUDIO_AFE_CONN>, +- <&audsys CLK_AUDIO_A1SYS>, +- <&audsys CLK_AUDIO_A2SYS>; +- +- clock-names = "infra_sys_audio_clk", +- "top_audio_mux1_sel", +- "top_audio_mux2_sel", +- "top_audio_a1sys_hp", +- "top_audio_a2sys_hp", +- "i2s0_src_sel", +- "i2s1_src_sel", +- "i2s2_src_sel", +- "i2s3_src_sel", +- "i2s0_src_div", +- "i2s1_src_div", +- "i2s2_src_div", +- "i2s3_src_div", +- "i2s0_mclk_en", +- "i2s1_mclk_en", +- "i2s2_mclk_en", +- "i2s3_mclk_en", +- "i2so0_hop_ck", +- "i2so1_hop_ck", +- "i2so2_hop_ck", +- "i2so3_hop_ck", +- "i2si0_hop_ck", +- "i2si1_hop_ck", +- "i2si2_hop_ck", +- "i2si3_hop_ck", +- "asrc0_out_ck", +- "asrc1_out_ck", +- "asrc2_out_ck", +- "asrc3_out_ck", +- "audio_afe_pd", +- "audio_afe_conn_pd", +- "audio_a1sys_pd", +- "audio_a2sys_pd"; +- +- assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>, +- <&topckgen CLK_TOP_A2SYS_HP_SEL>, +- <&topckgen CLK_TOP_A1SYS_HP_DIV>, +- <&topckgen CLK_TOP_A2SYS_HP_DIV>; +- assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>, +- <&topckgen CLK_TOP_AUD2PLL>; +- assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; +- }; +- }; +- +- mmc0: mmc@11230000 { +- compatible = "mediatek,mt7622-mmc"; +- reg = <0 0x11230000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_MSDC30_0_PD>, +- <&topckgen CLK_TOP_MSDC50_0_SEL>; +- clock-names = "source", "hclk"; +- resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>; +- reset-names = "hrst"; +- status = "disabled"; +- }; +- +- mmc1: mmc@11240000 { +- compatible = "mediatek,mt7622-mmc"; +- reg = <0 0x11240000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_MSDC30_1_PD>, +- <&topckgen CLK_TOP_AXI_SEL>; +- clock-names = "source", "hclk"; +- resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>; +- reset-names = "hrst"; +- status = "disabled"; +- }; +- +- wmac: wmac@18000000 { +- compatible = "mediatek,mt7622-wmac"; +- reg = <0 0x18000000 0 0x100000>; +- interrupts = ; +- +- mediatek,infracfg = <&infracfg>; +- status = "disabled"; +- +- power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; +- }; +- +- ssusbsys: ssusbsys@1a000000 { +- compatible = "mediatek,mt7622-ssusbsys", +- "syscon"; +- reg = <0 0x1a000000 0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- ssusb: usb@1a0c0000 { +- compatible = "mediatek,mt7622-xhci", +- "mediatek,mtk-xhci"; +- reg = <0 0x1a0c0000 0 0x01000>, +- <0 0x1a0c4700 0 0x0100>; +- reg-names = "mac", "ippc"; +- interrupts = ; +- power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>; +- clocks = <&ssusbsys CLK_SSUSB_SYS_EN>, +- <&ssusbsys CLK_SSUSB_REF_EN>, +- <&ssusbsys CLK_SSUSB_MCU_EN>, +- <&ssusbsys CLK_SSUSB_DMA_EN>; +- clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; +- phys = <&u2port0 PHY_TYPE_USB2>, +- <&u3port0 PHY_TYPE_USB3>, +- <&u2port1 PHY_TYPE_USB2>; +- +- status = "disabled"; +- }; +- +- u3phy: t-phy@1a0c4000 { +- compatible = "mediatek,mt7622-tphy", +- "mediatek,generic-tphy-v1"; +- reg = <0 0x1a0c4000 0 0x700>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "disabled"; +- +- u2port0: usb-phy@1a0c4800 { +- reg = <0 0x1a0c4800 0 0x0100>; +- #phy-cells = <1>; +- clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>; +- clock-names = "ref"; +- }; +- +- u3port0: usb-phy@1a0c4900 { +- reg = <0 0x1a0c4900 0 0x0700>; +- #phy-cells = <1>; +- clocks = <&clk25m>; +- clock-names = "ref"; +- }; +- +- u2port1: usb-phy@1a0c5000 { +- reg = <0 0x1a0c5000 0 0x0100>; +- #phy-cells = <1>; +- clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>; +- clock-names = "ref"; +- }; +- }; +- +- pciesys: pciesys@1a100800 { +- compatible = "mediatek,mt7622-pciesys", +- "syscon"; +- reg = <0 0x1a100800 0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pcie: pcie@1a140000 { +- compatible = "mediatek,mt7622-pcie"; +- device_type = "pci"; +- reg = <0 0x1a140000 0 0x1000>, +- <0 0x1a143000 0 0x1000>, +- <0 0x1a145000 0 0x1000>; +- reg-names = "subsys", "port0", "port1"; +- #address-cells = <3>; +- #size-cells = <2>; +- interrupts = , +- ; +- clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, +- <&pciesys CLK_PCIE_P1_MAC_EN>, +- <&pciesys CLK_PCIE_P0_AHB_EN>, +- <&pciesys CLK_PCIE_P0_AHB_EN>, +- <&pciesys CLK_PCIE_P0_AUX_EN>, +- <&pciesys CLK_PCIE_P1_AUX_EN>, +- <&pciesys CLK_PCIE_P0_AXI_EN>, +- <&pciesys CLK_PCIE_P1_AXI_EN>, +- <&pciesys CLK_PCIE_P0_OBFF_EN>, +- <&pciesys CLK_PCIE_P1_OBFF_EN>, +- <&pciesys CLK_PCIE_P0_PIPE_EN>, +- <&pciesys CLK_PCIE_P1_PIPE_EN>; +- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", +- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", +- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; +- power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; +- bus-range = <0x00 0xff>; +- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; +- status = "disabled"; +- +- pcie0: pcie@0,0 { +- reg = <0x0000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- status = "disabled"; +- +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie_intc0 0>, +- <0 0 0 2 &pcie_intc0 1>, +- <0 0 0 3 &pcie_intc0 2>, +- <0 0 0 4 &pcie_intc0 3>; +- pcie_intc0: interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- }; +- }; +- +- pcie1: pcie@1,0 { +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- status = "disabled"; +- +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie_intc1 0>, +- <0 0 0 2 &pcie_intc1 1>, +- <0 0 0 3 &pcie_intc1 2>, +- <0 0 0 4 &pcie_intc1 3>; +- pcie_intc1: interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- }; +- }; +- }; +- +- sata: sata@1a200000 { +- compatible = "mediatek,mt7622-ahci", +- "mediatek,mtk-ahci"; +- reg = <0 0x1a200000 0 0x1100>; +- interrupts = ; +- interrupt-names = "hostc"; +- clocks = <&pciesys CLK_SATA_AHB_EN>, +- <&pciesys CLK_SATA_AXI_EN>, +- <&pciesys CLK_SATA_ASIC_EN>, +- <&pciesys CLK_SATA_RBC_EN>, +- <&pciesys CLK_SATA_PM_EN>; +- clock-names = "ahb", "axi", "asic", "rbc", "pm"; +- phys = <&sata_port PHY_TYPE_SATA>; +- phy-names = "sata-phy"; +- ports-implemented = <0x1>; +- power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; +- resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, +- <&pciesys MT7622_SATA_PHY_SW_RST>, +- <&pciesys MT7622_SATA_PHY_REG_RST>; +- reset-names = "axi", "sw", "reg"; +- mediatek,phy-mode = <&pciesys>; +- status = "disabled"; +- }; +- +- sata_phy: t-phy@1a243000 { +- compatible = "mediatek,mt7622-tphy", +- "mediatek,generic-tphy-v1"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "disabled"; +- +- sata_port: sata-phy@1a243000 { +- reg = <0 0x1a243000 0 0x0100>; +- clocks = <&topckgen CLK_TOP_ETH_500M>; +- clock-names = "ref"; +- #phy-cells = <1>; +- }; +- }; +- +- ethsys: syscon@1b000000 { +- compatible = "mediatek,mt7622-ethsys", +- "syscon"; +- reg = <0 0x1b000000 0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- hsdma: dma-controller@1b007000 { +- compatible = "mediatek,mt7622-hsdma"; +- reg = <0 0x1b007000 0 0x1000>; +- interrupts = ; +- clocks = <ðsys CLK_ETH_HSDMA_EN>; +- clock-names = "hsdma"; +- power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; +- #dma-cells = <1>; +- }; +- +- eth: ethernet@1b100000 { +- compatible = "mediatek,mt7622-eth", +- "mediatek,mt2701-eth", +- "syscon"; +- reg = <0 0x1b100000 0 0x20000>; +- interrupts = , +- , +- ; +- clocks = <&topckgen CLK_TOP_ETH_SEL>, +- <ðsys CLK_ETH_ESW_EN>, +- <ðsys CLK_ETH_GP0_EN>, +- <ðsys CLK_ETH_GP1_EN>, +- <ðsys CLK_ETH_GP2_EN>, +- <&sgmiisys CLK_SGMII_TX250M_EN>, +- <&sgmiisys CLK_SGMII_RX250M_EN>, +- <&sgmiisys CLK_SGMII_CDR_REF>, +- <&sgmiisys CLK_SGMII_CDR_FB>, +- <&topckgen CLK_TOP_SGMIIPLL>, +- <&apmixedsys CLK_APMIXED_ETH2PLL>; +- clock-names = "ethif", "esw", "gp0", "gp1", "gp2", +- "sgmii_tx250m", "sgmii_rx250m", +- "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", +- "eth2pll"; +- power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; +- mediatek,ethsys = <ðsys>; +- mediatek,sgmiisys = <&sgmiisys>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- sgmiisys: sgmiisys@1b128000 { +- compatible = "mediatek,mt7622-sgmiisys", +- "syscon"; +- reg = <0 0x1b128000 0 0x3000>; +- #clock-cells = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8167-pinfunc.h b/scripts/dtc/include-prefixes/arm64/mediatek/mt8167-pinfunc.h +deleted file mode 100644 +index 061c3255a973..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8167-pinfunc.h ++++ /dev/null +@@ -1,744 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2020 MediaTek Inc. +- */ +-#ifndef __DTS_MT8167_PINFUNC_H +-#define __DTS_MT8167_PINFUNC_H +- +-#include +- +-#define MT8167_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +-#define MT8167_PIN_0_EINT0__FUNC_PWM_B (MTK_PIN_NO(0) | 1) +-#define MT8167_PIN_0_EINT0__FUNC_DPI_CK (MTK_PIN_NO(0) | 2) +-#define MT8167_PIN_0_EINT0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3) +-#define MT8167_PIN_0_EINT0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4) +-#define MT8167_PIN_0_EINT0__FUNC_SQICS (MTK_PIN_NO(0) | 6) +-#define MT8167_PIN_0_EINT0__FUNC_DBG_MON_A_6 (MTK_PIN_NO(0) | 7) +- +-#define MT8167_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +-#define MT8167_PIN_1_EINT1__FUNC_PWM_C (MTK_PIN_NO(1) | 1) +-#define MT8167_PIN_1_EINT1__FUNC_DPI_D12 (MTK_PIN_NO(1) | 2) +-#define MT8167_PIN_1_EINT1__FUNC_I2S2_DI (MTK_PIN_NO(1) | 3) +-#define MT8167_PIN_1_EINT1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4) +-#define MT8167_PIN_1_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(1) | 5) +-#define MT8167_PIN_1_EINT1__FUNC_SQISO (MTK_PIN_NO(1) | 6) +-#define MT8167_PIN_1_EINT1__FUNC_DBG_MON_A_7 (MTK_PIN_NO(1) | 7) +- +-#define MT8167_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +-#define MT8167_PIN_2_EINT2__FUNC_CLKM0 (MTK_PIN_NO(2) | 1) +-#define MT8167_PIN_2_EINT2__FUNC_DPI_D13 (MTK_PIN_NO(2) | 2) +-#define MT8167_PIN_2_EINT2__FUNC_I2S2_LRCK (MTK_PIN_NO(2) | 3) +-#define MT8167_PIN_2_EINT2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4) +-#define MT8167_PIN_2_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(2) | 5) +-#define MT8167_PIN_2_EINT2__FUNC_SQISI (MTK_PIN_NO(2) | 6) +-#define MT8167_PIN_2_EINT2__FUNC_DBG_MON_A_8 (MTK_PIN_NO(2) | 7) +- +-#define MT8167_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +-#define MT8167_PIN_3_EINT3__FUNC_CLKM1 (MTK_PIN_NO(3) | 1) +-#define MT8167_PIN_3_EINT3__FUNC_DPI_D14 (MTK_PIN_NO(3) | 2) +-#define MT8167_PIN_3_EINT3__FUNC_SPI_MI (MTK_PIN_NO(3) | 3) +-#define MT8167_PIN_3_EINT3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4) +-#define MT8167_PIN_3_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(3) | 5) +-#define MT8167_PIN_3_EINT3__FUNC_SQIWP (MTK_PIN_NO(3) | 6) +-#define MT8167_PIN_3_EINT3__FUNC_DBG_MON_A_9 (MTK_PIN_NO(3) | 7) +- +-#define MT8167_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +-#define MT8167_PIN_4_EINT4__FUNC_CLKM2 (MTK_PIN_NO(4) | 1) +-#define MT8167_PIN_4_EINT4__FUNC_DPI_D15 (MTK_PIN_NO(4) | 2) +-#define MT8167_PIN_4_EINT4__FUNC_SPI_MO (MTK_PIN_NO(4) | 3) +-#define MT8167_PIN_4_EINT4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4) +-#define MT8167_PIN_4_EINT4__FUNC_CONN_MCU_TCK (MTK_PIN_NO(4) | 5) +-#define MT8167_PIN_4_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(4) | 6) +-#define MT8167_PIN_4_EINT4__FUNC_DBG_MON_A_10 (MTK_PIN_NO(4) | 7) +- +-#define MT8167_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +-#define MT8167_PIN_5_EINT5__FUNC_UCTS2 (MTK_PIN_NO(5) | 1) +-#define MT8167_PIN_5_EINT5__FUNC_DPI_D16 (MTK_PIN_NO(5) | 2) +-#define MT8167_PIN_5_EINT5__FUNC_SPI_CSB (MTK_PIN_NO(5) | 3) +-#define MT8167_PIN_5_EINT5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4) +-#define MT8167_PIN_5_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(5) | 5) +-#define MT8167_PIN_5_EINT5__FUNC_CONN_TEST_CK (MTK_PIN_NO(5) | 6) +-#define MT8167_PIN_5_EINT5__FUNC_DBG_MON_A_11 (MTK_PIN_NO(5) | 7) +- +-#define MT8167_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +-#define MT8167_PIN_6_EINT6__FUNC_URTS2 (MTK_PIN_NO(6) | 1) +-#define MT8167_PIN_6_EINT6__FUNC_DPI_D17 (MTK_PIN_NO(6) | 2) +-#define MT8167_PIN_6_EINT6__FUNC_SPI_CLK (MTK_PIN_NO(6) | 3) +-#define MT8167_PIN_6_EINT6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4) +-#define MT8167_PIN_6_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(6) | 5) +-#define MT8167_PIN_6_EINT6__FUNC_MM_TEST_CK (MTK_PIN_NO(6) | 6) +-#define MT8167_PIN_6_EINT6__FUNC_DBG_MON_A_12 (MTK_PIN_NO(6) | 7) +- +-#define MT8167_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +-#define MT8167_PIN_7_EINT7__FUNC_SQIRST (MTK_PIN_NO(7) | 1) +-#define MT8167_PIN_7_EINT7__FUNC_DPI_D6 (MTK_PIN_NO(7) | 2) +-#define MT8167_PIN_7_EINT7__FUNC_SDA1_0 (MTK_PIN_NO(7) | 3) +-#define MT8167_PIN_7_EINT7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4) +-#define MT8167_PIN_7_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(7) | 5) +-#define MT8167_PIN_7_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(7) | 6) +-#define MT8167_PIN_7_EINT7__FUNC_DBG_MON_A_13 (MTK_PIN_NO(7) | 7) +- +-#define MT8167_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +-#define MT8167_PIN_8_EINT8__FUNC_SQICK (MTK_PIN_NO(8) | 1) +-#define MT8167_PIN_8_EINT8__FUNC_CLKM3 (MTK_PIN_NO(8) | 2) +-#define MT8167_PIN_8_EINT8__FUNC_SCL1_0 (MTK_PIN_NO(8) | 3) +-#define MT8167_PIN_8_EINT8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4) +-#define MT8167_PIN_8_EINT8__FUNC_ANT_SEL0 (MTK_PIN_NO(8) | 5) +-#define MT8167_PIN_8_EINT8__FUNC_DPI_D7 (MTK_PIN_NO(8) | 6) +-#define MT8167_PIN_8_EINT8__FUNC_DBG_MON_A_14 (MTK_PIN_NO(8) | 7) +- +-#define MT8167_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +-#define MT8167_PIN_9_EINT9__FUNC_CLKM4 (MTK_PIN_NO(9) | 1) +-#define MT8167_PIN_9_EINT9__FUNC_SDA2_0 (MTK_PIN_NO(9) | 2) +-#define MT8167_PIN_9_EINT9__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3) +-#define MT8167_PIN_9_EINT9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4) +-#define MT8167_PIN_9_EINT9__FUNC_ANT_SEL1 (MTK_PIN_NO(9) | 5) +-#define MT8167_PIN_9_EINT9__FUNC_DPI_D8 (MTK_PIN_NO(9) | 6) +-#define MT8167_PIN_9_EINT9__FUNC_DBG_MON_A_15 (MTK_PIN_NO(9) | 7) +- +-#define MT8167_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +-#define MT8167_PIN_10_EINT10__FUNC_CLKM5 (MTK_PIN_NO(10) | 1) +-#define MT8167_PIN_10_EINT10__FUNC_SCL2_0 (MTK_PIN_NO(10) | 2) +-#define MT8167_PIN_10_EINT10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 3) +-#define MT8167_PIN_10_EINT10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4) +-#define MT8167_PIN_10_EINT10__FUNC_ANT_SEL2 (MTK_PIN_NO(10) | 5) +-#define MT8167_PIN_10_EINT10__FUNC_DPI_D9 (MTK_PIN_NO(10) | 6) +-#define MT8167_PIN_10_EINT10__FUNC_DBG_MON_A_16 (MTK_PIN_NO(10) | 7) +- +-#define MT8167_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +-#define MT8167_PIN_11_EINT11__FUNC_CLKM4 (MTK_PIN_NO(11) | 1) +-#define MT8167_PIN_11_EINT11__FUNC_PWM_C (MTK_PIN_NO(11) | 2) +-#define MT8167_PIN_11_EINT11__FUNC_CONN_TEST_CK (MTK_PIN_NO(11) | 3) +-#define MT8167_PIN_11_EINT11__FUNC_ANT_SEL3 (MTK_PIN_NO(11) | 4) +-#define MT8167_PIN_11_EINT11__FUNC_DPI_D10 (MTK_PIN_NO(11) | 5) +-#define MT8167_PIN_11_EINT11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 6) +-#define MT8167_PIN_11_EINT11__FUNC_DBG_MON_A_17 (MTK_PIN_NO(11) | 7) +- +-#define MT8167_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +-#define MT8167_PIN_12_EINT12__FUNC_CLKM5 (MTK_PIN_NO(12) | 1) +-#define MT8167_PIN_12_EINT12__FUNC_PWM_A (MTK_PIN_NO(12) | 2) +-#define MT8167_PIN_12_EINT12__FUNC_SPDIF_OUT (MTK_PIN_NO(12) | 3) +-#define MT8167_PIN_12_EINT12__FUNC_ANT_SEL4 (MTK_PIN_NO(12) | 4) +-#define MT8167_PIN_12_EINT12__FUNC_DPI_D11 (MTK_PIN_NO(12) | 5) +-#define MT8167_PIN_12_EINT12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 6) +-#define MT8167_PIN_12_EINT12__FUNC_DBG_MON_A_18 (MTK_PIN_NO(12) | 7) +- +-#define MT8167_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +-#define MT8167_PIN_13_EINT13__FUNC_TSF_IN (MTK_PIN_NO(13) | 3) +-#define MT8167_PIN_13_EINT13__FUNC_ANT_SEL5 (MTK_PIN_NO(13) | 4) +-#define MT8167_PIN_13_EINT13__FUNC_DPI_D0 (MTK_PIN_NO(13) | 5) +-#define MT8167_PIN_13_EINT13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 6) +-#define MT8167_PIN_13_EINT13__FUNC_DBG_MON_A_19 (MTK_PIN_NO(13) | 7) +- +-#define MT8167_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +-#define MT8167_PIN_14_EINT14__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(14) | 2) +-#define MT8167_PIN_14_EINT14__FUNC_TDM_RX_MCK (MTK_PIN_NO(14) | 3) +-#define MT8167_PIN_14_EINT14__FUNC_ANT_SEL1 (MTK_PIN_NO(14) | 4) +-#define MT8167_PIN_14_EINT14__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(14) | 5) +-#define MT8167_PIN_14_EINT14__FUNC_NCLE (MTK_PIN_NO(14) | 6) +-#define MT8167_PIN_14_EINT14__FUNC_DBG_MON_B_8 (MTK_PIN_NO(14) | 7) +- +-#define MT8167_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +-#define MT8167_PIN_15_EINT15__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(15) | 2) +-#define MT8167_PIN_15_EINT15__FUNC_TDM_RX_BCK (MTK_PIN_NO(15) | 3) +-#define MT8167_PIN_15_EINT15__FUNC_ANT_SEL2 (MTK_PIN_NO(15) | 4) +-#define MT8167_PIN_15_EINT15__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(15) | 5) +-#define MT8167_PIN_15_EINT15__FUNC_NCEB1 (MTK_PIN_NO(15) | 6) +-#define MT8167_PIN_15_EINT15__FUNC_DBG_MON_B_9 (MTK_PIN_NO(15) | 7) +- +-#define MT8167_PIN_16_EINT16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +-#define MT8167_PIN_16_EINT16__FUNC_I2S_8CH_BCK (MTK_PIN_NO(16) | 2) +-#define MT8167_PIN_16_EINT16__FUNC_TDM_RX_LRCK (MTK_PIN_NO(16) | 3) +-#define MT8167_PIN_16_EINT16__FUNC_ANT_SEL3 (MTK_PIN_NO(16) | 4) +-#define MT8167_PIN_16_EINT16__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(16) | 5) +-#define MT8167_PIN_16_EINT16__FUNC_NCEB0 (MTK_PIN_NO(16) | 6) +-#define MT8167_PIN_16_EINT16__FUNC_DBG_MON_B_10 (MTK_PIN_NO(16) | 7) +- +-#define MT8167_PIN_17_EINT17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +-#define MT8167_PIN_17_EINT17__FUNC_I2S_8CH_MCK (MTK_PIN_NO(17) | 2) +-#define MT8167_PIN_17_EINT17__FUNC_TDM_RX_DI (MTK_PIN_NO(17) | 3) +-#define MT8167_PIN_17_EINT17__FUNC_IDDIG (MTK_PIN_NO(17) | 4) +-#define MT8167_PIN_17_EINT17__FUNC_ANT_SEL4 (MTK_PIN_NO(17) | 5) +-#define MT8167_PIN_17_EINT17__FUNC_NREB (MTK_PIN_NO(17) | 6) +-#define MT8167_PIN_17_EINT17__FUNC_DBG_MON_B_11 (MTK_PIN_NO(17) | 7) +- +-#define MT8167_PIN_18_EINT18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +-#define MT8167_PIN_18_EINT18__FUNC_USB_DRVVBUS (MTK_PIN_NO(18) | 2) +-#define MT8167_PIN_18_EINT18__FUNC_I2S3_LRCK (MTK_PIN_NO(18) | 3) +-#define MT8167_PIN_18_EINT18__FUNC_CLKM1 (MTK_PIN_NO(18) | 4) +-#define MT8167_PIN_18_EINT18__FUNC_ANT_SEL3 (MTK_PIN_NO(18) | 5) +-#define MT8167_PIN_18_EINT18__FUNC_I2S2_BCK (MTK_PIN_NO(18) | 6) +-#define MT8167_PIN_18_EINT18__FUNC_DBG_MON_A_20 (MTK_PIN_NO(18) | 7) +- +-#define MT8167_PIN_19_EINT19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +-#define MT8167_PIN_19_EINT19__FUNC_UCTS1 (MTK_PIN_NO(19) | 1) +-#define MT8167_PIN_19_EINT19__FUNC_IDDIG (MTK_PIN_NO(19) | 2) +-#define MT8167_PIN_19_EINT19__FUNC_I2S3_BCK (MTK_PIN_NO(19) | 3) +-#define MT8167_PIN_19_EINT19__FUNC_CLKM2 (MTK_PIN_NO(19) | 4) +-#define MT8167_PIN_19_EINT19__FUNC_ANT_SEL4 (MTK_PIN_NO(19) | 5) +-#define MT8167_PIN_19_EINT19__FUNC_I2S2_DI (MTK_PIN_NO(19) | 6) +-#define MT8167_PIN_19_EINT19__FUNC_DBG_MON_A_21 (MTK_PIN_NO(19) | 7) +- +-#define MT8167_PIN_20_EINT20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +-#define MT8167_PIN_20_EINT20__FUNC_URTS1 (MTK_PIN_NO(20) | 1) +-#define MT8167_PIN_20_EINT20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 3) +-#define MT8167_PIN_20_EINT20__FUNC_CLKM3 (MTK_PIN_NO(20) | 4) +-#define MT8167_PIN_20_EINT20__FUNC_ANT_SEL5 (MTK_PIN_NO(20) | 5) +-#define MT8167_PIN_20_EINT20__FUNC_I2S2_LRCK (MTK_PIN_NO(20) | 6) +-#define MT8167_PIN_20_EINT20__FUNC_DBG_MON_A_22 (MTK_PIN_NO(20) | 7) +- +-#define MT8167_PIN_21_EINT21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +-#define MT8167_PIN_21_EINT21__FUNC_NRNB (MTK_PIN_NO(21) | 1) +-#define MT8167_PIN_21_EINT21__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 2) +-#define MT8167_PIN_21_EINT21__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(21) | 3) +-#define MT8167_PIN_21_EINT21__FUNC_DBG_MON_B_31 (MTK_PIN_NO(21) | 7) +- +-#define MT8167_PIN_22_EINT22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +-#define MT8167_PIN_22_EINT22__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(22) | 2) +-#define MT8167_PIN_22_EINT22__FUNC_TSF_IN (MTK_PIN_NO(22) | 3) +-#define MT8167_PIN_22_EINT22__FUNC_USB_DRVVBUS (MTK_PIN_NO(22) | 4) +-#define MT8167_PIN_22_EINT22__FUNC_SPDIF_OUT (MTK_PIN_NO(22) | 5) +-#define MT8167_PIN_22_EINT22__FUNC_NRE_C (MTK_PIN_NO(22) | 6) +-#define MT8167_PIN_22_EINT22__FUNC_DBG_MON_B_12 (MTK_PIN_NO(22) | 7) +- +-#define MT8167_PIN_23_EINT23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +-#define MT8167_PIN_23_EINT23__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(23) | 2) +-#define MT8167_PIN_23_EINT23__FUNC_CLKM0 (MTK_PIN_NO(23) | 3) +-#define MT8167_PIN_23_EINT23__FUNC_IR (MTK_PIN_NO(23) | 4) +-#define MT8167_PIN_23_EINT23__FUNC_SPDIF_IN (MTK_PIN_NO(23) | 5) +-#define MT8167_PIN_23_EINT23__FUNC_NDQS_C (MTK_PIN_NO(23) | 6) +-#define MT8167_PIN_23_EINT23__FUNC_DBG_MON_B_13 (MTK_PIN_NO(23) | 7) +- +-#define MT8167_PIN_24_EINT24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +-#define MT8167_PIN_24_EINT24__FUNC_DPI_D20 (MTK_PIN_NO(24) | 1) +-#define MT8167_PIN_24_EINT24__FUNC_DPI_DE (MTK_PIN_NO(24) | 2) +-#define MT8167_PIN_24_EINT24__FUNC_ANT_SEL1 (MTK_PIN_NO(24) | 3) +-#define MT8167_PIN_24_EINT24__FUNC_UCTS2 (MTK_PIN_NO(24) | 4) +-#define MT8167_PIN_24_EINT24__FUNC_PWM_A (MTK_PIN_NO(24) | 5) +-#define MT8167_PIN_24_EINT24__FUNC_I2S0_MCK (MTK_PIN_NO(24) | 6) +-#define MT8167_PIN_24_EINT24__FUNC_DBG_MON_A_0 (MTK_PIN_NO(24) | 7) +- +-#define MT8167_PIN_25_EINT25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +-#define MT8167_PIN_25_EINT25__FUNC_DPI_D19 (MTK_PIN_NO(25) | 1) +-#define MT8167_PIN_25_EINT25__FUNC_DPI_VSYNC (MTK_PIN_NO(25) | 2) +-#define MT8167_PIN_25_EINT25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 3) +-#define MT8167_PIN_25_EINT25__FUNC_URTS2 (MTK_PIN_NO(25) | 4) +-#define MT8167_PIN_25_EINT25__FUNC_PWM_B (MTK_PIN_NO(25) | 5) +-#define MT8167_PIN_25_EINT25__FUNC_I2S_8CH_MCK (MTK_PIN_NO(25) | 6) +-#define MT8167_PIN_25_EINT25__FUNC_DBG_MON_A_1 (MTK_PIN_NO(25) | 7) +- +-#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +-#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(26) | 1) +-#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(26) | 2) +- +-#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +-#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(27) | 1) +-#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(27) | 2) +- +-#define MT8167_PIN_28_PWRAP_INT__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +-#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S0_MCK (MTK_PIN_NO(28) | 1) +-#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S_8CH_MCK (MTK_PIN_NO(28) | 4) +-#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S2_MCK (MTK_PIN_NO(28) | 5) +-#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S3_MCK (MTK_PIN_NO(28) | 6) +- +-#define MT8167_PIN_29_PWRAP_SPI0_CK__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +-#define MT8167_PIN_29_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(29) | 1) +- +-#define MT8167_PIN_30_PWRAP_SPI0_CSN__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +-#define MT8167_PIN_30_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(30) | 1) +- +-#define MT8167_PIN_31_RTC32K_CK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +-#define MT8167_PIN_31_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(31) | 1) +- +-#define MT8167_PIN_32_WATCHDOG__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +-#define MT8167_PIN_32_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(32) | 1) +- +-#define MT8167_PIN_33_SRCLKENA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +-#define MT8167_PIN_33_SRCLKENA__FUNC_SRCLKENA0 (MTK_PIN_NO(33) | 1) +- +-#define MT8167_PIN_34_URXD2__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +-#define MT8167_PIN_34_URXD2__FUNC_URXD2 (MTK_PIN_NO(34) | 1) +-#define MT8167_PIN_34_URXD2__FUNC_DPI_D5 (MTK_PIN_NO(34) | 2) +-#define MT8167_PIN_34_URXD2__FUNC_UTXD2 (MTK_PIN_NO(34) | 3) +-#define MT8167_PIN_34_URXD2__FUNC_DBG_SCL (MTK_PIN_NO(34) | 4) +-#define MT8167_PIN_34_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(34) | 6) +-#define MT8167_PIN_34_URXD2__FUNC_DBG_MON_B_0 (MTK_PIN_NO(34) | 7) +- +-#define MT8167_PIN_35_UTXD2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +-#define MT8167_PIN_35_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(35) | 1) +-#define MT8167_PIN_35_UTXD2__FUNC_DPI_HSYNC (MTK_PIN_NO(35) | 2) +-#define MT8167_PIN_35_UTXD2__FUNC_URXD2 (MTK_PIN_NO(35) | 3) +-#define MT8167_PIN_35_UTXD2__FUNC_DBG_SDA (MTK_PIN_NO(35) | 4) +-#define MT8167_PIN_35_UTXD2__FUNC_DPI_D18 (MTK_PIN_NO(35) | 5) +-#define MT8167_PIN_35_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(35) | 6) +-#define MT8167_PIN_35_UTXD2__FUNC_DBG_MON_B_1 (MTK_PIN_NO(35) | 7) +- +-#define MT8167_PIN_36_MRG_CLK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +-#define MT8167_PIN_36_MRG_CLK__FUNC_MRG_CLK (MTK_PIN_NO(36) | 1) +-#define MT8167_PIN_36_MRG_CLK__FUNC_DPI_D4 (MTK_PIN_NO(36) | 2) +-#define MT8167_PIN_36_MRG_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(36) | 3) +-#define MT8167_PIN_36_MRG_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(36) | 4) +-#define MT8167_PIN_36_MRG_CLK__FUNC_PCM0_CLK (MTK_PIN_NO(36) | 5) +-#define MT8167_PIN_36_MRG_CLK__FUNC_IR (MTK_PIN_NO(36) | 6) +-#define MT8167_PIN_36_MRG_CLK__FUNC_DBG_MON_A_2 (MTK_PIN_NO(36) | 7) +- +-#define MT8167_PIN_37_MRG_SYNC__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +-#define MT8167_PIN_37_MRG_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(37) | 1) +-#define MT8167_PIN_37_MRG_SYNC__FUNC_DPI_D3 (MTK_PIN_NO(37) | 2) +-#define MT8167_PIN_37_MRG_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(37) | 3) +-#define MT8167_PIN_37_MRG_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(37) | 4) +-#define MT8167_PIN_37_MRG_SYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(37) | 5) +-#define MT8167_PIN_37_MRG_SYNC__FUNC_EXT_COL (MTK_PIN_NO(37) | 6) +-#define MT8167_PIN_37_MRG_SYNC__FUNC_DBG_MON_A_3 (MTK_PIN_NO(37) | 7) +- +-#define MT8167_PIN_38_MRG_DI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +-#define MT8167_PIN_38_MRG_DI__FUNC_MRG_DI (MTK_PIN_NO(38) | 1) +-#define MT8167_PIN_38_MRG_DI__FUNC_DPI_D1 (MTK_PIN_NO(38) | 2) +-#define MT8167_PIN_38_MRG_DI__FUNC_I2S0_DI (MTK_PIN_NO(38) | 3) +-#define MT8167_PIN_38_MRG_DI__FUNC_I2S3_DO (MTK_PIN_NO(38) | 4) +-#define MT8167_PIN_38_MRG_DI__FUNC_PCM0_DI (MTK_PIN_NO(38) | 5) +-#define MT8167_PIN_38_MRG_DI__FUNC_EXT_MDIO (MTK_PIN_NO(38) | 6) +-#define MT8167_PIN_38_MRG_DI__FUNC_DBG_MON_A_4 (MTK_PIN_NO(38) | 7) +- +-#define MT8167_PIN_39_MRG_DO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +-#define MT8167_PIN_39_MRG_DO__FUNC_MRG_DO (MTK_PIN_NO(39) | 1) +-#define MT8167_PIN_39_MRG_DO__FUNC_DPI_D2 (MTK_PIN_NO(39) | 2) +-#define MT8167_PIN_39_MRG_DO__FUNC_I2S0_MCK (MTK_PIN_NO(39) | 3) +-#define MT8167_PIN_39_MRG_DO__FUNC_I2S3_MCK (MTK_PIN_NO(39) | 4) +-#define MT8167_PIN_39_MRG_DO__FUNC_PCM0_DO (MTK_PIN_NO(39) | 5) +-#define MT8167_PIN_39_MRG_DO__FUNC_EXT_MDC (MTK_PIN_NO(39) | 6) +-#define MT8167_PIN_39_MRG_DO__FUNC_DBG_MON_A_5 (MTK_PIN_NO(39) | 7) +- +-#define MT8167_PIN_40_KPROW0__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +-#define MT8167_PIN_40_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(40) | 1) +-#define MT8167_PIN_40_KPROW0__FUNC_IMG_TEST_CK (MTK_PIN_NO(40) | 4) +-#define MT8167_PIN_40_KPROW0__FUNC_DBG_MON_B_4 (MTK_PIN_NO(40) | 7) +- +-#define MT8167_PIN_41_KPROW1__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +-#define MT8167_PIN_41_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(41) | 1) +-#define MT8167_PIN_41_KPROW1__FUNC_IDDIG (MTK_PIN_NO(41) | 2) +-#define MT8167_PIN_41_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 3) +-#define MT8167_PIN_41_KPROW1__FUNC_MFG_TEST_CK (MTK_PIN_NO(41) | 4) +-#define MT8167_PIN_41_KPROW1__FUNC_DBG_MON_B_5 (MTK_PIN_NO(41) | 7) +- +-#define MT8167_PIN_42_KPCOL0__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +-#define MT8167_PIN_42_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(42) | 1) +-#define MT8167_PIN_42_KPCOL0__FUNC_DBG_MON_B_6 (MTK_PIN_NO(42) | 7) +- +-#define MT8167_PIN_43_KPCOL1__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +-#define MT8167_PIN_43_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(43) | 1) +-#define MT8167_PIN_43_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(43) | 2) +-#define MT8167_PIN_43_KPCOL1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(43) | 3) +-#define MT8167_PIN_43_KPCOL1__FUNC_TSF_IN (MTK_PIN_NO(43) | 4) +-#define MT8167_PIN_43_KPCOL1__FUNC_DFD_NTRST_XI (MTK_PIN_NO(43) | 5) +-#define MT8167_PIN_43_KPCOL1__FUNC_UDI_NTRST_XI (MTK_PIN_NO(43) | 6) +-#define MT8167_PIN_43_KPCOL1__FUNC_DBG_MON_B_7 (MTK_PIN_NO(43) | 7) +- +-#define MT8167_PIN_44_JTMS__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +-#define MT8167_PIN_44_JTMS__FUNC_JTMS (MTK_PIN_NO(44) | 1) +-#define MT8167_PIN_44_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(44) | 2) +-#define MT8167_PIN_44_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(44) | 3) +-#define MT8167_PIN_44_JTMS__FUNC_GPUDFD_TMS_XI (MTK_PIN_NO(44) | 4) +-#define MT8167_PIN_44_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(44) | 5) +-#define MT8167_PIN_44_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(44) | 6) +- +-#define MT8167_PIN_45_JTCK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +-#define MT8167_PIN_45_JTCK__FUNC_JTCK (MTK_PIN_NO(45) | 1) +-#define MT8167_PIN_45_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(45) | 2) +-#define MT8167_PIN_45_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(45) | 3) +-#define MT8167_PIN_45_JTCK__FUNC_GPUDFD_TCK_XI (MTK_PIN_NO(45) | 4) +-#define MT8167_PIN_45_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(45) | 5) +-#define MT8167_PIN_45_JTCK__FUNC_UDI_TCK_XI (MTK_PIN_NO(45) | 6) +- +-#define MT8167_PIN_46_JTDI__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +-#define MT8167_PIN_46_JTDI__FUNC_JTDI (MTK_PIN_NO(46) | 1) +-#define MT8167_PIN_46_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(46) | 2) +-#define MT8167_PIN_46_JTDI__FUNC_GPUDFD_TDI_XI (MTK_PIN_NO(46) | 4) +-#define MT8167_PIN_46_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(46) | 5) +-#define MT8167_PIN_46_JTDI__FUNC_UDI_TDI_XI (MTK_PIN_NO(46) | 6) +- +-#define MT8167_PIN_47_JTDO__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +-#define MT8167_PIN_47_JTDO__FUNC_JTDO (MTK_PIN_NO(47) | 1) +-#define MT8167_PIN_47_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(47) | 2) +-#define MT8167_PIN_47_JTDO__FUNC_GPUDFD_TDO (MTK_PIN_NO(47) | 4) +-#define MT8167_PIN_47_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(47) | 5) +-#define MT8167_PIN_47_JTDO__FUNC_UDI_TDO (MTK_PIN_NO(47) | 6) +- +-#define MT8167_PIN_48_SPI_CS__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +-#define MT8167_PIN_48_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(48) | 1) +-#define MT8167_PIN_48_SPI_CS__FUNC_I2S0_DI (MTK_PIN_NO(48) | 3) +-#define MT8167_PIN_48_SPI_CS__FUNC_I2S2_BCK (MTK_PIN_NO(48) | 4) +-#define MT8167_PIN_48_SPI_CS__FUNC_DBG_MON_A_23 (MTK_PIN_NO(48) | 7) +- +-#define MT8167_PIN_49_SPI_CK__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +-#define MT8167_PIN_49_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(49) | 1) +-#define MT8167_PIN_49_SPI_CK__FUNC_I2S0_LRCK (MTK_PIN_NO(49) | 3) +-#define MT8167_PIN_49_SPI_CK__FUNC_I2S2_DI (MTK_PIN_NO(49) | 4) +-#define MT8167_PIN_49_SPI_CK__FUNC_DBG_MON_A_24 (MTK_PIN_NO(49) | 7) +- +-#define MT8167_PIN_50_SPI_MI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +-#define MT8167_PIN_50_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(50) | 1) +-#define MT8167_PIN_50_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(50) | 2) +-#define MT8167_PIN_50_SPI_MI__FUNC_I2S0_BCK (MTK_PIN_NO(50) | 3) +-#define MT8167_PIN_50_SPI_MI__FUNC_I2S2_LRCK (MTK_PIN_NO(50) | 4) +-#define MT8167_PIN_50_SPI_MI__FUNC_DBG_MON_A_25 (MTK_PIN_NO(50) | 7) +- +-#define MT8167_PIN_51_SPI_MO__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +-#define MT8167_PIN_51_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(51) | 1) +-#define MT8167_PIN_51_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(51) | 2) +-#define MT8167_PIN_51_SPI_MO__FUNC_I2S0_MCK (MTK_PIN_NO(51) | 3) +-#define MT8167_PIN_51_SPI_MO__FUNC_I2S2_MCK (MTK_PIN_NO(51) | 4) +-#define MT8167_PIN_51_SPI_MO__FUNC_DBG_MON_A_26 (MTK_PIN_NO(51) | 7) +- +-#define MT8167_PIN_52_SDA1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +-#define MT8167_PIN_52_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(52) | 1) +- +-#define MT8167_PIN_53_SCL1__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +-#define MT8167_PIN_53_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(53) | 1) +- +-#define MT8167_PIN_54_DISP_PWM__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +-#define MT8167_PIN_54_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(54) | 1) +-#define MT8167_PIN_54_DISP_PWM__FUNC_PWM_B (MTK_PIN_NO(54) | 2) +-#define MT8167_PIN_54_DISP_PWM__FUNC_DBG_MON_B_2 (MTK_PIN_NO(54) | 7) +- +-#define MT8167_PIN_55_I2S_DATA_IN__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +-#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(55) | 1) +-#define MT8167_PIN_55_I2S_DATA_IN__FUNC_UCTS0 (MTK_PIN_NO(55) | 2) +-#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(55) | 3) +-#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(55) | 4) +-#define MT8167_PIN_55_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(55) | 5) +-#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S2_BCK (MTK_PIN_NO(55) | 6) +-#define MT8167_PIN_55_I2S_DATA_IN__FUNC_DBG_MON_A_28 (MTK_PIN_NO(55) | 7) +- +-#define MT8167_PIN_56_I2S_LRCK__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +-#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(56) | 1) +-#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(56) | 3) +-#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(56) | 4) +-#define MT8167_PIN_56_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(56) | 5) +-#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S2_DI (MTK_PIN_NO(56) | 6) +-#define MT8167_PIN_56_I2S_LRCK__FUNC_DBG_MON_A_29 (MTK_PIN_NO(56) | 7) +- +-#define MT8167_PIN_57_I2S_BCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +-#define MT8167_PIN_57_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(57) | 1) +-#define MT8167_PIN_57_I2S_BCK__FUNC_URTS0 (MTK_PIN_NO(57) | 2) +-#define MT8167_PIN_57_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(57) | 3) +-#define MT8167_PIN_57_I2S_BCK__FUNC_I2S_8CH_BCK (MTK_PIN_NO(57) | 4) +-#define MT8167_PIN_57_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(57) | 5) +-#define MT8167_PIN_57_I2S_BCK__FUNC_I2S2_LRCK (MTK_PIN_NO(57) | 6) +-#define MT8167_PIN_57_I2S_BCK__FUNC_DBG_MON_A_30 (MTK_PIN_NO(57) | 7) +- +-#define MT8167_PIN_58_SDA0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +-#define MT8167_PIN_58_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(58) | 1) +- +-#define MT8167_PIN_59_SCL0__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +-#define MT8167_PIN_59_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(59) | 1) +- +-#define MT8167_PIN_60_SDA2__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +-#define MT8167_PIN_60_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(60) | 1) +-#define MT8167_PIN_60_SDA2__FUNC_PWM_B (MTK_PIN_NO(60) | 2) +- +-#define MT8167_PIN_61_SCL2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +-#define MT8167_PIN_61_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(61) | 1) +-#define MT8167_PIN_61_SCL2__FUNC_PWM_C (MTK_PIN_NO(61) | 2) +- +-#define MT8167_PIN_62_URXD0__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +-#define MT8167_PIN_62_URXD0__FUNC_URXD0 (MTK_PIN_NO(62) | 1) +-#define MT8167_PIN_62_URXD0__FUNC_UTXD0 (MTK_PIN_NO(62) | 2) +- +-#define MT8167_PIN_63_UTXD0__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +-#define MT8167_PIN_63_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(63) | 1) +-#define MT8167_PIN_63_UTXD0__FUNC_URXD0 (MTK_PIN_NO(63) | 2) +- +-#define MT8167_PIN_64_URXD1__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +-#define MT8167_PIN_64_URXD1__FUNC_URXD1 (MTK_PIN_NO(64) | 1) +-#define MT8167_PIN_64_URXD1__FUNC_UTXD1 (MTK_PIN_NO(64) | 2) +-#define MT8167_PIN_64_URXD1__FUNC_DBG_MON_A_27 (MTK_PIN_NO(64) | 7) +- +-#define MT8167_PIN_65_UTXD1__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +-#define MT8167_PIN_65_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(65) | 1) +-#define MT8167_PIN_65_UTXD1__FUNC_URXD1 (MTK_PIN_NO(65) | 2) +-#define MT8167_PIN_65_UTXD1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(65) | 7) +- +-#define MT8167_PIN_66_LCM_RST__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +-#define MT8167_PIN_66_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(66) | 1) +-#define MT8167_PIN_66_LCM_RST__FUNC_I2S0_MCK (MTK_PIN_NO(66) | 3) +-#define MT8167_PIN_66_LCM_RST__FUNC_DBG_MON_B_3 (MTK_PIN_NO(66) | 7) +- +-#define MT8167_PIN_67_DSI_TE__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +-#define MT8167_PIN_67_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(67) | 1) +-#define MT8167_PIN_67_DSI_TE__FUNC_I2S_8CH_MCK (MTK_PIN_NO(67) | 3) +-#define MT8167_PIN_67_DSI_TE__FUNC_DBG_MON_B_14 (MTK_PIN_NO(67) | 7) +- +-#define MT8167_PIN_68_MSDC2_CMD__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +-#define MT8167_PIN_68_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(68) | 1) +-#define MT8167_PIN_68_MSDC2_CMD__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(68) | 2) +-#define MT8167_PIN_68_MSDC2_CMD__FUNC_SDA1_0 (MTK_PIN_NO(68) | 3) +-#define MT8167_PIN_68_MSDC2_CMD__FUNC_USB_SDA (MTK_PIN_NO(68) | 5) +-#define MT8167_PIN_68_MSDC2_CMD__FUNC_I2S3_BCK (MTK_PIN_NO(68) | 6) +-#define MT8167_PIN_68_MSDC2_CMD__FUNC_DBG_MON_B_15 (MTK_PIN_NO(68) | 7) +- +-#define MT8167_PIN_69_MSDC2_CLK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +-#define MT8167_PIN_69_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(69) | 1) +-#define MT8167_PIN_69_MSDC2_CLK__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(69) | 2) +-#define MT8167_PIN_69_MSDC2_CLK__FUNC_SCL1_0 (MTK_PIN_NO(69) | 3) +-#define MT8167_PIN_69_MSDC2_CLK__FUNC_DPI_D21 (MTK_PIN_NO(69) | 4) +-#define MT8167_PIN_69_MSDC2_CLK__FUNC_USB_SCL (MTK_PIN_NO(69) | 5) +-#define MT8167_PIN_69_MSDC2_CLK__FUNC_I2S3_LRCK (MTK_PIN_NO(69) | 6) +-#define MT8167_PIN_69_MSDC2_CLK__FUNC_DBG_MON_B_16 (MTK_PIN_NO(69) | 7) +- +-#define MT8167_PIN_70_MSDC2_DAT0__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +-#define MT8167_PIN_70_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(70) | 1) +-#define MT8167_PIN_70_MSDC2_DAT0__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(70) | 2) +-#define MT8167_PIN_70_MSDC2_DAT0__FUNC_DPI_D22 (MTK_PIN_NO(70) | 4) +-#define MT8167_PIN_70_MSDC2_DAT0__FUNC_UTXD0 (MTK_PIN_NO(70) | 5) +-#define MT8167_PIN_70_MSDC2_DAT0__FUNC_I2S3_DO (MTK_PIN_NO(70) | 6) +-#define MT8167_PIN_70_MSDC2_DAT0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(70) | 7) +- +-#define MT8167_PIN_71_MSDC2_DAT1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +-#define MT8167_PIN_71_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(71) | 1) +-#define MT8167_PIN_71_MSDC2_DAT1__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(71) | 2) +-#define MT8167_PIN_71_MSDC2_DAT1__FUNC_PWM_A (MTK_PIN_NO(71) | 3) +-#define MT8167_PIN_71_MSDC2_DAT1__FUNC_I2S3_MCK (MTK_PIN_NO(71) | 4) +-#define MT8167_PIN_71_MSDC2_DAT1__FUNC_URXD0 (MTK_PIN_NO(71) | 5) +-#define MT8167_PIN_71_MSDC2_DAT1__FUNC_PWM_B (MTK_PIN_NO(71) | 6) +-#define MT8167_PIN_71_MSDC2_DAT1__FUNC_DBG_MON_B_18 (MTK_PIN_NO(71) | 7) +- +-#define MT8167_PIN_72_MSDC2_DAT2__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +-#define MT8167_PIN_72_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(72) | 1) +-#define MT8167_PIN_72_MSDC2_DAT2__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(72) | 2) +-#define MT8167_PIN_72_MSDC2_DAT2__FUNC_SDA2_0 (MTK_PIN_NO(72) | 3) +-#define MT8167_PIN_72_MSDC2_DAT2__FUNC_DPI_D23 (MTK_PIN_NO(72) | 4) +-#define MT8167_PIN_72_MSDC2_DAT2__FUNC_UTXD1 (MTK_PIN_NO(72) | 5) +-#define MT8167_PIN_72_MSDC2_DAT2__FUNC_PWM_C (MTK_PIN_NO(72) | 6) +-#define MT8167_PIN_72_MSDC2_DAT2__FUNC_DBG_MON_B_19 (MTK_PIN_NO(72) | 7) +- +-#define MT8167_PIN_73_MSDC2_DAT3__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +-#define MT8167_PIN_73_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(73) | 1) +-#define MT8167_PIN_73_MSDC2_DAT3__FUNC_I2S_8CH_BCK (MTK_PIN_NO(73) | 2) +-#define MT8167_PIN_73_MSDC2_DAT3__FUNC_SCL2_0 (MTK_PIN_NO(73) | 3) +-#define MT8167_PIN_73_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(73) | 4) +-#define MT8167_PIN_73_MSDC2_DAT3__FUNC_URXD1 (MTK_PIN_NO(73) | 5) +-#define MT8167_PIN_73_MSDC2_DAT3__FUNC_PWM_A (MTK_PIN_NO(73) | 6) +-#define MT8167_PIN_73_MSDC2_DAT3__FUNC_DBG_MON_B_20 (MTK_PIN_NO(73) | 7) +- +-#define MT8167_PIN_74_TDN3__FUNC_GPI74 (MTK_PIN_NO(74) | 0) +-#define MT8167_PIN_74_TDN3__FUNC_TDN3 (MTK_PIN_NO(74) | 1) +- +-#define MT8167_PIN_75_TDP3__FUNC_GPI75 (MTK_PIN_NO(75) | 0) +-#define MT8167_PIN_75_TDP3__FUNC_TDP3 (MTK_PIN_NO(75) | 1) +- +-#define MT8167_PIN_76_TDN2__FUNC_GPI76 (MTK_PIN_NO(76) | 0) +-#define MT8167_PIN_76_TDN2__FUNC_TDN2 (MTK_PIN_NO(76) | 1) +- +-#define MT8167_PIN_77_TDP2__FUNC_GPI77 (MTK_PIN_NO(77) | 0) +-#define MT8167_PIN_77_TDP2__FUNC_TDP2 (MTK_PIN_NO(77) | 1) +- +-#define MT8167_PIN_78_TCN__FUNC_GPI78 (MTK_PIN_NO(78) | 0) +-#define MT8167_PIN_78_TCN__FUNC_TCN (MTK_PIN_NO(78) | 1) +- +-#define MT8167_PIN_79_TCP__FUNC_GPI79 (MTK_PIN_NO(79) | 0) +-#define MT8167_PIN_79_TCP__FUNC_TCP (MTK_PIN_NO(79) | 1) +- +-#define MT8167_PIN_80_TDN1__FUNC_GPI80 (MTK_PIN_NO(80) | 0) +-#define MT8167_PIN_80_TDN1__FUNC_TDN1 (MTK_PIN_NO(80) | 1) +- +-#define MT8167_PIN_81_TDP1__FUNC_GPI81 (MTK_PIN_NO(81) | 0) +-#define MT8167_PIN_81_TDP1__FUNC_TDP1 (MTK_PIN_NO(81) | 1) +- +-#define MT8167_PIN_82_TDN0__FUNC_GPI82 (MTK_PIN_NO(82) | 0) +-#define MT8167_PIN_82_TDN0__FUNC_TDN0 (MTK_PIN_NO(82) | 1) +- +-#define MT8167_PIN_83_TDP0__FUNC_GPI83 (MTK_PIN_NO(83) | 0) +-#define MT8167_PIN_83_TDP0__FUNC_TDP0 (MTK_PIN_NO(83) | 1) +- +-#define MT8167_PIN_84_RDN0__FUNC_GPI84 (MTK_PIN_NO(84) | 0) +-#define MT8167_PIN_84_RDN0__FUNC_RDN0 (MTK_PIN_NO(84) | 1) +- +-#define MT8167_PIN_85_RDP0__FUNC_GPI85 (MTK_PIN_NO(85) | 0) +-#define MT8167_PIN_85_RDP0__FUNC_RDP0 (MTK_PIN_NO(85) | 1) +- +-#define MT8167_PIN_86_RDN1__FUNC_GPI86 (MTK_PIN_NO(86) | 0) +-#define MT8167_PIN_86_RDN1__FUNC_RDN1 (MTK_PIN_NO(86) | 1) +- +-#define MT8167_PIN_87_RDP1__FUNC_GPI87 (MTK_PIN_NO(87) | 0) +-#define MT8167_PIN_87_RDP1__FUNC_RDP1 (MTK_PIN_NO(87) | 1) +- +-#define MT8167_PIN_88_RCN__FUNC_GPI88 (MTK_PIN_NO(88) | 0) +-#define MT8167_PIN_88_RCN__FUNC_RCN (MTK_PIN_NO(88) | 1) +- +-#define MT8167_PIN_89_RCP__FUNC_GPI89 (MTK_PIN_NO(89) | 0) +-#define MT8167_PIN_89_RCP__FUNC_RCP (MTK_PIN_NO(89) | 1) +- +-#define MT8167_PIN_90_RDN2__FUNC_GPI90 (MTK_PIN_NO(90) | 0) +-#define MT8167_PIN_90_RDN2__FUNC_RDN2 (MTK_PIN_NO(90) | 1) +-#define MT8167_PIN_90_RDN2__FUNC_CMDAT8 (MTK_PIN_NO(90) | 2) +- +-#define MT8167_PIN_91_RDP2__FUNC_GPI91 (MTK_PIN_NO(91) | 0) +-#define MT8167_PIN_91_RDP2__FUNC_RDP2 (MTK_PIN_NO(91) | 1) +-#define MT8167_PIN_91_RDP2__FUNC_CMDAT9 (MTK_PIN_NO(91) | 2) +- +-#define MT8167_PIN_92_RDN3__FUNC_GPI92 (MTK_PIN_NO(92) | 0) +-#define MT8167_PIN_92_RDN3__FUNC_RDN3 (MTK_PIN_NO(92) | 1) +-#define MT8167_PIN_92_RDN3__FUNC_CMDAT4 (MTK_PIN_NO(92) | 2) +- +-#define MT8167_PIN_93_RDP3__FUNC_GPI93 (MTK_PIN_NO(93) | 0) +-#define MT8167_PIN_93_RDP3__FUNC_RDP3 (MTK_PIN_NO(93) | 1) +-#define MT8167_PIN_93_RDP3__FUNC_CMDAT5 (MTK_PIN_NO(93) | 2) +- +-#define MT8167_PIN_94_RCN_A__FUNC_GPI94 (MTK_PIN_NO(94) | 0) +-#define MT8167_PIN_94_RCN_A__FUNC_RCN_A (MTK_PIN_NO(94) | 1) +-#define MT8167_PIN_94_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(94) | 2) +- +-#define MT8167_PIN_95_RCP_A__FUNC_GPI95 (MTK_PIN_NO(95) | 0) +-#define MT8167_PIN_95_RCP_A__FUNC_RCP_A (MTK_PIN_NO(95) | 1) +-#define MT8167_PIN_95_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(95) | 2) +- +-#define MT8167_PIN_96_RDN1_A__FUNC_GPI96 (MTK_PIN_NO(96) | 0) +-#define MT8167_PIN_96_RDN1_A__FUNC_RDN1_A (MTK_PIN_NO(96) | 1) +-#define MT8167_PIN_96_RDN1_A__FUNC_CMDAT2 (MTK_PIN_NO(96) | 2) +-#define MT8167_PIN_96_RDN1_A__FUNC_CMCSD2 (MTK_PIN_NO(96) | 3) +- +-#define MT8167_PIN_97_RDP1_A__FUNC_GPI97 (MTK_PIN_NO(97) | 0) +-#define MT8167_PIN_97_RDP1_A__FUNC_RDP1_A (MTK_PIN_NO(97) | 1) +-#define MT8167_PIN_97_RDP1_A__FUNC_CMDAT3 (MTK_PIN_NO(97) | 2) +-#define MT8167_PIN_97_RDP1_A__FUNC_CMCSD3 (MTK_PIN_NO(97) | 3) +- +-#define MT8167_PIN_98_RDN0_A__FUNC_GPI98 (MTK_PIN_NO(98) | 0) +-#define MT8167_PIN_98_RDN0_A__FUNC_RDN0_A (MTK_PIN_NO(98) | 1) +-#define MT8167_PIN_98_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(98) | 2) +- +-#define MT8167_PIN_99_RDP0_A__FUNC_GPI99 (MTK_PIN_NO(99) | 0) +-#define MT8167_PIN_99_RDP0_A__FUNC_RDP0_A (MTK_PIN_NO(99) | 1) +-#define MT8167_PIN_99_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(99) | 2) +- +-#define MT8167_PIN_100_CMDAT0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +-#define MT8167_PIN_100_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(100) | 1) +-#define MT8167_PIN_100_CMDAT0__FUNC_CMCSD0 (MTK_PIN_NO(100) | 2) +-#define MT8167_PIN_100_CMDAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(100) | 3) +-#define MT8167_PIN_100_CMDAT0__FUNC_TDM_RX_MCK (MTK_PIN_NO(100) | 5) +-#define MT8167_PIN_100_CMDAT0__FUNC_DBG_MON_B_21 (MTK_PIN_NO(100) | 7) +- +-#define MT8167_PIN_101_CMDAT1__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +-#define MT8167_PIN_101_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(101) | 1) +-#define MT8167_PIN_101_CMDAT1__FUNC_CMCSD1 (MTK_PIN_NO(101) | 2) +-#define MT8167_PIN_101_CMDAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(101) | 3) +-#define MT8167_PIN_101_CMDAT1__FUNC_CMFLASH (MTK_PIN_NO(101) | 4) +-#define MT8167_PIN_101_CMDAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(101) | 5) +-#define MT8167_PIN_101_CMDAT1__FUNC_DBG_MON_B_22 (MTK_PIN_NO(101) | 7) +- +-#define MT8167_PIN_102_CMMCLK__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +-#define MT8167_PIN_102_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(102) | 1) +-#define MT8167_PIN_102_CMMCLK__FUNC_ANT_SEL4 (MTK_PIN_NO(102) | 3) +-#define MT8167_PIN_102_CMMCLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(102) | 5) +-#define MT8167_PIN_102_CMMCLK__FUNC_DBG_MON_B_23 (MTK_PIN_NO(102) | 7) +- +-#define MT8167_PIN_103_CMPCLK__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +-#define MT8167_PIN_103_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(103) | 1) +-#define MT8167_PIN_103_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(103) | 2) +-#define MT8167_PIN_103_CMPCLK__FUNC_ANT_SEL5 (MTK_PIN_NO(103) | 3) +-#define MT8167_PIN_103_CMPCLK__FUNC_TDM_RX_DI (MTK_PIN_NO(103) | 5) +-#define MT8167_PIN_103_CMPCLK__FUNC_DBG_MON_B_24 (MTK_PIN_NO(103) | 7) +- +-#define MT8167_PIN_104_MSDC1_CMD__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +-#define MT8167_PIN_104_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(104) | 1) +-#define MT8167_PIN_104_MSDC1_CMD__FUNC_SQICS (MTK_PIN_NO(104) | 4) +-#define MT8167_PIN_104_MSDC1_CMD__FUNC_DBG_MON_B_25 (MTK_PIN_NO(104) | 7) +- +-#define MT8167_PIN_105_MSDC1_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +-#define MT8167_PIN_105_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(105) | 1) +-#define MT8167_PIN_105_MSDC1_CLK__FUNC_UDI_NTRST_XI (MTK_PIN_NO(105) | 2) +-#define MT8167_PIN_105_MSDC1_CLK__FUNC_DFD_NTRST_XI (MTK_PIN_NO(105) | 3) +-#define MT8167_PIN_105_MSDC1_CLK__FUNC_SQISO (MTK_PIN_NO(105) | 4) +-#define MT8167_PIN_105_MSDC1_CLK__FUNC_GPUEJ_NTRST_XI (MTK_PIN_NO(105) | 5) +-#define MT8167_PIN_105_MSDC1_CLK__FUNC_DBG_MON_B_26 (MTK_PIN_NO(105) | 7) +- +-#define MT8167_PIN_106_MSDC1_DAT0__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +-#define MT8167_PIN_106_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(106) | 1) +-#define MT8167_PIN_106_MSDC1_DAT0__FUNC_UDI_TMS_XI (MTK_PIN_NO(106) | 2) +-#define MT8167_PIN_106_MSDC1_DAT0__FUNC_DFD_TMS_XI (MTK_PIN_NO(106) | 3) +-#define MT8167_PIN_106_MSDC1_DAT0__FUNC_SQISI (MTK_PIN_NO(106) | 4) +-#define MT8167_PIN_106_MSDC1_DAT0__FUNC_GPUEJ_TMS_XI (MTK_PIN_NO(106) | 5) +-#define MT8167_PIN_106_MSDC1_DAT0__FUNC_DBG_MON_B_27 (MTK_PIN_NO(106) | 7) +- +-#define MT8167_PIN_107_MSDC1_DAT1__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +-#define MT8167_PIN_107_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(107) | 1) +-#define MT8167_PIN_107_MSDC1_DAT1__FUNC_UDI_TCK_XI (MTK_PIN_NO(107) | 2) +-#define MT8167_PIN_107_MSDC1_DAT1__FUNC_DFD_TCK_XI (MTK_PIN_NO(107) | 3) +-#define MT8167_PIN_107_MSDC1_DAT1__FUNC_SQIWP (MTK_PIN_NO(107) | 4) +-#define MT8167_PIN_107_MSDC1_DAT1__FUNC_GPUEJ_TCK_XI (MTK_PIN_NO(107) | 5) +-#define MT8167_PIN_107_MSDC1_DAT1__FUNC_DBG_MON_B_28 (MTK_PIN_NO(107) | 7) +- +-#define MT8167_PIN_108_MSDC1_DAT2__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +-#define MT8167_PIN_108_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(108) | 1) +-#define MT8167_PIN_108_MSDC1_DAT2__FUNC_UDI_TDI_XI (MTK_PIN_NO(108) | 2) +-#define MT8167_PIN_108_MSDC1_DAT2__FUNC_DFD_TDI_XI (MTK_PIN_NO(108) | 3) +-#define MT8167_PIN_108_MSDC1_DAT2__FUNC_SQIRST (MTK_PIN_NO(108) | 4) +-#define MT8167_PIN_108_MSDC1_DAT2__FUNC_GPUEJ_TDI_XI (MTK_PIN_NO(108) | 5) +-#define MT8167_PIN_108_MSDC1_DAT2__FUNC_DBG_MON_B_29 (MTK_PIN_NO(108) | 7) +- +-#define MT8167_PIN_109_MSDC1_DAT3__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +-#define MT8167_PIN_109_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(109) | 1) +-#define MT8167_PIN_109_MSDC1_DAT3__FUNC_UDI_TDO (MTK_PIN_NO(109) | 2) +-#define MT8167_PIN_109_MSDC1_DAT3__FUNC_DFD_TDO (MTK_PIN_NO(109) | 3) +-#define MT8167_PIN_109_MSDC1_DAT3__FUNC_SQICK (MTK_PIN_NO(109) | 4) +-#define MT8167_PIN_109_MSDC1_DAT3__FUNC_GPUEJ_TDO (MTK_PIN_NO(109) | 5) +-#define MT8167_PIN_109_MSDC1_DAT3__FUNC_DBG_MON_B_30 (MTK_PIN_NO(109) | 7) +- +-#define MT8167_PIN_110_MSDC0_DAT7__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +-#define MT8167_PIN_110_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(110) | 1) +-#define MT8167_PIN_110_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(110) | 4) +- +-#define MT8167_PIN_111_MSDC0_DAT6__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +-#define MT8167_PIN_111_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(111) | 1) +-#define MT8167_PIN_111_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(111) | 4) +- +-#define MT8167_PIN_112_MSDC0_DAT5__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +-#define MT8167_PIN_112_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(112) | 1) +-#define MT8167_PIN_112_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(112) | 4) +- +-#define MT8167_PIN_113_MSDC0_DAT4__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +-#define MT8167_PIN_113_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(113) | 1) +-#define MT8167_PIN_113_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(113) | 4) +- +-#define MT8167_PIN_114_MSDC0_RSTB__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +-#define MT8167_PIN_114_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(114) | 1) +-#define MT8167_PIN_114_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(114) | 4) +- +-#define MT8167_PIN_115_MSDC0_CMD__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +-#define MT8167_PIN_115_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(115) | 1) +-#define MT8167_PIN_115_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(115) | 4) +- +-#define MT8167_PIN_116_MSDC0_CLK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +-#define MT8167_PIN_116_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(116) | 1) +-#define MT8167_PIN_116_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(116) | 4) +- +-#define MT8167_PIN_117_MSDC0_DAT3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +-#define MT8167_PIN_117_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(117) | 1) +-#define MT8167_PIN_117_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(117) | 4) +- +-#define MT8167_PIN_118_MSDC0_DAT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +-#define MT8167_PIN_118_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(118) | 1) +-#define MT8167_PIN_118_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(118) | 4) +- +-#define MT8167_PIN_119_MSDC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +-#define MT8167_PIN_119_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(119) | 1) +-#define MT8167_PIN_119_MSDC0_DAT1__FUNC_NLD8 (MTK_PIN_NO(119) | 4) +- +-#define MT8167_PIN_120_MSDC0_DAT0__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +-#define MT8167_PIN_120_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(120) | 1) +-#define MT8167_PIN_120_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(120) | 4) +-#define MT8167_PIN_120_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(120) | 5) +- +-#define MT8167_PIN_121_CEC__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +-#define MT8167_PIN_121_CEC__FUNC_CEC (MTK_PIN_NO(121) | 1) +- +-#define MT8167_PIN_122_HTPLG__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +-#define MT8167_PIN_122_HTPLG__FUNC_HTPLG (MTK_PIN_NO(122) | 1) +- +-#define MT8167_PIN_123_HDMISCK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +-#define MT8167_PIN_123_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(123) | 1) +- +-#define MT8167_PIN_124_HDMISD__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +-#define MT8167_PIN_124_HDMISD__FUNC_HDMISD (MTK_PIN_NO(124) | 1) +- +-#endif /* __DTS_MT8167_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8167-pumpkin.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8167-pumpkin.dts +deleted file mode 100644 +index 774a2f3fb4b2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8167-pumpkin.dts ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2020 BayLibre, SAS. +- * Author: Fabien Parent +- */ +- +-/dts-v1/; +- +-#include "mt8167.dtsi" +-#include "pumpkin-common.dtsi" +- +-/ { +- model = "Pumpkin MT8167"; +- compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x80000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8167.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt8167.dtsi +deleted file mode 100644 +index 9029051624a6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8167.dtsi ++++ /dev/null +@@ -1,182 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2020 MediaTek Inc. +- * Copyright (c) 2020 BayLibre, SAS. +- * Author: Fabien Parent +- */ +- +-#include +-#include +-#include +- +-#include "mt8167-pinfunc.h" +- +-#include "mt8516.dtsi" +- +-/ { +- compatible = "mediatek,mt8167"; +- +- soc { +- topckgen: topckgen@10000000 { +- compatible = "mediatek,mt8167-topckgen", "syscon"; +- reg = <0 0x10000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- infracfg: infracfg@10001000 { +- compatible = "mediatek,mt8167-infracfg", "syscon"; +- reg = <0 0x10001000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- apmixedsys: apmixedsys@10018000 { +- compatible = "mediatek,mt8167-apmixedsys", "syscon"; +- reg = <0 0x10018000 0 0x710>; +- #clock-cells = <1>; +- }; +- +- scpsys: syscon@10006000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0 0x10006000 0 0x1000>; +- #power-domain-cells = <1>; +- +- spm: power-controller { +- compatible = "mediatek,mt8167-power-controller"; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <1>; +- +- /* power domains of the SoC */ +- power-domain@MT8167_POWER_DOMAIN_MM { +- reg = ; +- clocks = <&topckgen CLK_TOP_SMI_MM>; +- clock-names = "mm"; +- #power-domain-cells = <0>; +- mediatek,infracfg = <&infracfg>; +- }; +- +- power-domain@MT8167_POWER_DOMAIN_VDEC { +- reg = ; +- clocks = <&topckgen CLK_TOP_SMI_MM>, +- <&topckgen CLK_TOP_RG_VDEC>; +- clock-names = "mm", "vdec"; +- #power-domain-cells = <0>; +- }; +- +- power-domain@MT8167_POWER_DOMAIN_ISP { +- reg = ; +- clocks = <&topckgen CLK_TOP_SMI_MM>; +- clock-names = "mm"; +- #power-domain-cells = <0>; +- }; +- +- power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC { +- reg = ; +- clocks = <&topckgen CLK_TOP_RG_AXI_MFG>, +- <&topckgen CLK_TOP_RG_SLOW_MFG>; +- clock-names = "axi_mfg", "mfg"; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <1>; +- mediatek,infracfg = <&infracfg>; +- +- power-domain@MT8167_POWER_DOMAIN_MFG_2D { +- reg = ; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <1>; +- +- power-domain@MT8167_POWER_DOMAIN_MFG { +- reg = ; +- #power-domain-cells = <0>; +- mediatek,infracfg = <&infracfg>; +- }; +- }; +- }; +- +- power-domain@MT8167_POWER_DOMAIN_CONN { +- reg = ; +- #power-domain-cells = <0>; +- mediatek,infracfg = <&infracfg>; +- }; +- }; +- }; +- +- imgsys: syscon@15000000 { +- compatible = "mediatek,mt8167-imgsys", "syscon"; +- reg = <0 0x15000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- vdecsys: syscon@16000000 { +- compatible = "mediatek,mt8167-vdecsys", "syscon"; +- reg = <0 0x16000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- pio: pinctrl@1000b000 { +- compatible = "mediatek,mt8167-pinctrl"; +- reg = <0 0x1000b000 0 0x1000>; +- mediatek,pctl-regmap = <&syscfg_pctl>; +- pins-are-numbered; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- +- mmsys: mmsys@14000000 { +- compatible = "mediatek,mt8167-mmsys", "syscon"; +- reg = <0 0x14000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- smi_common: smi@14017000 { +- compatible = "mediatek,mt8167-smi-common"; +- reg = <0 0x14017000 0 0x1000>; +- clocks = <&mmsys CLK_MM_SMI_COMMON>, +- <&mmsys CLK_MM_SMI_COMMON>; +- clock-names = "apb", "smi"; +- power-domains = <&spm MT8167_POWER_DOMAIN_MM>; +- }; +- +- larb0: larb@14016000 { +- compatible = "mediatek,mt8167-smi-larb"; +- reg = <0 0x14016000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- clocks = <&mmsys CLK_MM_SMI_LARB0>, +- <&mmsys CLK_MM_SMI_LARB0>; +- clock-names = "apb", "smi"; +- power-domains = <&spm MT8167_POWER_DOMAIN_MM>; +- }; +- +- larb1: larb@15001000 { +- compatible = "mediatek,mt8167-smi-larb"; +- reg = <0 0x15001000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- clocks = <&imgsys CLK_IMG_LARB1_SMI>, +- <&imgsys CLK_IMG_LARB1_SMI>; +- clock-names = "apb", "smi"; +- power-domains = <&spm MT8167_POWER_DOMAIN_ISP>; +- }; +- +- larb2: larb@16010000 { +- compatible = "mediatek,mt8167-smi-larb"; +- reg = <0 0x16010000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- clocks = <&vdecsys CLK_VDEC_CKEN>, +- <&vdecsys CLK_VDEC_LARB1_CKEN>; +- clock-names = "apb", "smi"; +- power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>; +- }; +- +- iommu: m4u@10203000 { +- compatible = "mediatek,mt8167-m4u"; +- reg = <0 0x10203000 0 0x1000>; +- mediatek,larbs = <&larb0 &larb1 &larb2>; +- interrupts = ; +- #iommu-cells = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-elm-hana-rev7.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-elm-hana-rev7.dts +deleted file mode 100644 +index 44f6149c1307..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-elm-hana-rev7.dts ++++ /dev/null +@@ -1,27 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright 2019 MediaTek Inc. +- */ +- +-/dts-v1/; +-#include "mt8173-elm-hana.dtsi" +- +-/ { +- model = "Google Hanawl"; +- compatible = "google,hana-rev7", "mediatek,mt8173"; +-}; +- +-&cpu_thermal { +- trips { +- cpu_crit: cpu_crit0 { +- temperature = <100000>; +- type = "critical"; +- }; +- }; +-}; +- +-&gpio_keys { +- /delete-node/tablet_mode; +- /delete-node/volume_down; +- /delete-node/volume_up; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-elm-hana.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-elm-hana.dts +deleted file mode 100644 +index c234296755e1..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-elm-hana.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright 2016 MediaTek Inc. +- */ +- +-/dts-v1/; +-#include "mt8173-elm-hana.dtsi" +- +-/ { +- model = "Google Hana"; +- compatible = "google,hana-rev6", "google,hana-rev5", +- "google,hana-rev4", "google,hana-rev3", +- "google,hana", "mediatek,mt8173"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-elm-hana.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-elm-hana.dtsi +deleted file mode 100644 +index bdcd35cecad9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-elm-hana.dtsi ++++ /dev/null +@@ -1,70 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright 2016 MediaTek Inc. +- */ +- +-#include "mt8173-elm.dtsi" +- +-&i2c0 { +- clock-frequency = <200000>; +-}; +- +-&i2c3 { +- touchscreen2: touchscreen@34 { +- compatible = "melfas,mip4_ts"; +- reg = <0x34>; +- interrupt-parent = <&pio>; +- interrupts = <88 IRQ_TYPE_LEVEL_LOW>; +- }; +- +- /* +- * Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd +- * Gen (MTK) are using synaptics touchscreen (hid-over-i2c driver) as a +- * second source touchscreen. +- */ +- touchscreen3: touchscreen@20 { +- compatible = "hid-over-i2c"; +- reg = <0x20>; +- hid-descr-addr = <0x0020>; +- interrupt-parent = <&pio>; +- interrupts = <88 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c4 { +- /* +- * Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd +- * Gen (MTK) are using synaptics trackpad (hid-over-i2c driver) as a +- * second source trackpad. +- */ +- trackpad2: trackpad@2c { +- compatible = "hid-over-i2c"; +- interrupt-parent = <&pio>; +- interrupts = <117 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x2c>; +- hid-descr-addr = <0x0020>; +- wakeup-source; +- }; +-}; +- +-&mmc1 { +- wp-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; +-}; +- +-&pio { +- hdmi_mux_pins: hdmi_mux_pins { +- pins2 { +- pinmux = ; +- bias-pull-up; +- output-high; +- }; +- }; +- +- mmc1_pins_default: mmc1default { +- pins_wp { +- pinmux = ; +- input-enable; +- bias-pull-up; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-elm.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-elm.dts +deleted file mode 100644 +index e9e4ac0b74b2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-elm.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright 2016 MediaTek Inc. +- */ +- +-/dts-v1/; +-#include "mt8173-elm.dtsi" +- +-/ { +- model = "Google Elm"; +- compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6", +- "google,elm-rev5", "google,elm-rev4", "google,elm-rev3", +- "google,elm", "mediatek,mt8173"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-elm.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-elm.dtsi +deleted file mode 100644 +index e666ebb28980..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-elm.dtsi ++++ /dev/null +@@ -1,1183 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright 2016 MediaTek Inc. +- */ +- +-#include +-#include +-#include +-#include +-#include "mt8173.dtsi" +- +-/ { +- aliases { +- mmc0 = &mmc0; +- mmc1 = &mmc1; +- mmc2 = &mmc3; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x80000000>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm0 0 1000000>; +- power-supply = <&bl_fixed_reg>; +- enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&disp_pwm0_pins>; +- status = "okay"; +- }; +- +- bl_fixed_reg: fixedregulator2 { +- compatible = "regulator-fixed"; +- regulator-name = "bl_fixed"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- startup-delay-us = <1000>; +- enable-active-high; +- gpio = <&pio 32 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bl_fixed_pins>; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio_keys: gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_pins>; +- +- lid { +- label = "Lid"; +- gpios = <&pio 69 GPIO_ACTIVE_LOW>; +- linux,code = ; +- linux,input-type = ; +- gpio-key,wakeup; +- }; +- +- power { +- label = "Power"; +- gpios = <&pio 14 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- debounce-interval = <30>; +- gpio-key,wakeup; +- }; +- +- tablet_mode { +- label = "Tablet_mode"; +- gpios = <&pio 121 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- linux,input-type = ; +- gpio-key,wakeup; +- }; +- +- volume_down { +- label = "Volume_down"; +- gpios = <&pio 123 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- volume_up { +- label = "Volume_up"; +- gpios = <&pio 124 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- panel: panel { +- compatible = "lg,lp120up1"; +- power-supply = <&panel_fixed_3v3>; +- backlight = <&backlight>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&ps8640_out>; +- }; +- }; +- }; +- +- panel_fixed_3v3: regulator1 { +- compatible = "regulator-fixed"; +- regulator-name = "PANEL_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- gpio = <&pio 41 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&panel_fixed_pins>; +- }; +- +- ps8640_fixed_1v2: regulator2 { +- compatible = "regulator-fixed"; +- regulator-name = "PS8640_1V2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-enable-ramp-delay = <2000>; +- enable-active-high; +- regulator-boot-on; +- gpio = <&pio 30 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ps8640_fixed_pins>; +- }; +- +- sdio_fixed_3v3: fixedregulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&pio 85 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio_fixed_3v3_pins>; +- }; +- +- sound: sound { +- compatible = "mediatek,mt8173-rt5650"; +- mediatek,audio-codec = <&rt5650 &hdmi0>; +- mediatek,platform = <&afe>; +- pinctrl-names = "default"; +- pinctrl-0 = <&aud_i2s2>; +- +- mediatek,mclk = <1>; +- codec-capture { +- sound-dai = <&rt5650 1>; +- }; +- }; +- +- hdmicon: connector { +- compatible = "hdmi-connector"; +- label = "hdmi"; +- type = "a"; +- ddc-i2c-bus = <&hdmiddc0>; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi0_out>; +- }; +- }; +- }; +-}; +- +-&mfg_async { +- domain-supply = <&da9211_vgpu_reg>; +-}; +- +-&cec { +- status = "okay"; +-}; +- +-&cpu0 { +- proc-supply = <&mt6397_vpca15_reg>; +-}; +- +-&cpu1 { +- proc-supply = <&mt6397_vpca15_reg>; +-}; +- +-&cpu2 { +- proc-supply = <&da9211_vcpu_reg>; +- sram-supply = <&mt6397_vsramca7_reg>; +-}; +- +-&cpu3 { +- proc-supply = <&da9211_vcpu_reg>; +- sram-supply = <&mt6397_vsramca7_reg>; +-}; +- +-&cpu_thermal { +- sustainable-power = <4500>; /* milliwatts */ +- trips { +- threshold: trip-point0 { +- temperature = <60000>; +- }; +- +- target: trip-point1 { +- temperature = <65000>; +- }; +- }; +-}; +- +-&dsi0 { +- status = "okay"; +- ports { +- port { +- dsi0_out: endpoint { +- remote-endpoint = <&ps8640_in>; +- }; +- }; +- }; +-}; +- +-&dpi0 { +- status = "okay"; +-}; +- +-&hdmi0 { +- status = "okay"; +- ports { +- port@1 { +- reg = <1>; +- +- hdmi0_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +- }; +- }; +-}; +- +-&hdmi_phy { +- status = "okay"; +- mediatek,ibias = <0xc>; +-}; +- +-&i2c0 { +- status = "okay"; +- +- rt5650: audio-codec@1a { +- compatible = "realtek,rt5650"; +- reg = <0x1a>; +- avdd-supply = <&mt6397_vgp1_reg>; +- cpvdd-supply = <&mt6397_vcama_reg>; +- interrupt-parent = <&pio>; +- interrupts = <3 IRQ_TYPE_EDGE_BOTH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&rt5650_irq>; +- #sound-dai-cells = <1>; +- realtek,dmic1-data-pin = <2>; +- realtek,jd-mode = <2>; +- }; +- +- ps8640: edp-bridge@8 { +- compatible = "parade,ps8640"; +- reg = <0x8>; +- powerdown-gpios = <&pio 127 GPIO_ACTIVE_LOW>; +- reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ps8640_pins>; +- vdd12-supply = <&ps8640_fixed_1v2>; +- vdd33-supply = <&mt6397_vgp2_reg>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- ps8640_in: endpoint { +- remote-endpoint = <&dsi0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- ps8640_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <1500000>; +- status = "okay"; +- +- da9211: da9211@68 { +- compatible = "dlg,da9211"; +- reg = <0x68>; +- interrupt-parent = <&pio>; +- interrupts = <15 IRQ_TYPE_LEVEL_LOW>; +- +- regulators { +- da9211_vcpu_reg: BUCKA { +- regulator-name = "VBUCKA"; +- regulator-min-microvolt = < 700000>; +- regulator-max-microvolt = <1310000>; +- regulator-min-microamp = <2000000>; +- regulator-max-microamp = <4400000>; +- regulator-ramp-delay = <10000>; +- regulator-always-on; +- regulator-allowed-modes = ; +- }; +- +- da9211_vgpu_reg: BUCKB { +- regulator-name = "VBUCKB"; +- regulator-min-microvolt = < 700000>; +- regulator-max-microvolt = <1310000>; +- regulator-min-microamp = <2000000>; +- regulator-max-microamp = <3000000>; +- regulator-ramp-delay = <10000>; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- +- tpm: tpm@20 { +- compatible = "infineon,slb9645tt"; +- reg = <0x20>; +- powered-while-suspended; +- }; +-}; +- +-&i2c3 { +- clock-frequency = <400000>; +- status = "okay"; +- +- touchscreen: touchscreen@10 { +- compatible = "elan,ekth3500"; +- reg = <0x10>; +- interrupt-parent = <&pio>; +- interrupts = <88 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c4 { +- clock-frequency = <400000>; +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&trackpad_irq>; +- +- trackpad: trackpad@15 { +- compatible = "elan,ekth3000"; +- interrupt-parent = <&pio>; +- interrupts = <117 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x15>; +- vcc-supply = <&mt6397_vgp6_reg>; +- wakeup-source; +- }; +-}; +- +-&mipi_tx0 { +- status = "okay"; +-}; +- +-&mmc0 { +- status = "okay"; +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc0_pins_default>; +- pinctrl-1 = <&mmc0_pins_uhs>; +- bus-width = <8>; +- max-frequency = <200000000>; +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- cap-mmc-hw-reset; +- hs400-ds-delay = <0x14015>; +- mediatek,hs200-cmd-int-delay=<30>; +- mediatek,hs400-cmd-int-delay=<14>; +- mediatek,hs400-cmd-resp-sel-rising; +- vmmc-supply = <&mt6397_vemc_3v3_reg>; +- vqmmc-supply = <&mt6397_vio18_reg>; +- assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; +- non-removable; +-}; +- +-&mmc1 { +- status = "okay"; +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc1_pins_default>; +- pinctrl-1 = <&mmc1_pins_uhs>; +- bus-width = <4>; +- max-frequency = <200000000>; +- cap-sd-highspeed; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- cd-gpios = <&pio 1 GPIO_ACTIVE_LOW>; +- vmmc-supply = <&mt6397_vmch_reg>; +- vqmmc-supply = <&mt6397_vmc_reg>; +-}; +- +-&mmc3 { +- status = "okay"; +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc3_pins_default>; +- pinctrl-1 = <&mmc3_pins_uhs>; +- bus-width = <4>; +- max-frequency = <200000000>; +- cap-sd-highspeed; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- keep-power-in-suspend; +- enable-sdio-wakeup; +- cap-sdio-irq; +- vmmc-supply = <&sdio_fixed_3v3>; +- vqmmc-supply = <&mt6397_vgp3_reg>; +- non-removable; +- cap-power-off-card; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- btmrvl: btmrvl@2 { +- compatible = "marvell,sd8897-bt"; +- reg = <2>; +- interrupt-parent = <&pio>; +- interrupts = <119 IRQ_TYPE_LEVEL_LOW>; +- marvell,wakeup-pin = /bits/ 16 <0x0d>; +- marvell,wakeup-gap-ms = /bits/ 16 <0x64>; +- }; +- +- mwifiex: mwifiex@1 { +- compatible = "marvell,sd8897"; +- reg = <1>; +- interrupt-parent = <&pio>; +- interrupts = <38 IRQ_TYPE_LEVEL_LOW>; +- marvell,wakeup-pin = <3>; +- }; +-}; +- +-&nor_flash { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&nor_gpio1_pins>; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- }; +-}; +- +-&pio { +- gpio-line-names = "EC_INT_1V8", +- "SD_CD_L", +- "ALC5514_IRQ", +- "ALC5650_IRQ", +- /* +- * AP_FLASH_WP_L is crossystem ABI. Schematics +- * call it SFWP_B. +- */ +- "AP_FLASH_WP_L", +- "SFIN", +- "SFCS0", +- "SFHOLD", +- "SFOUT", +- "SFCK", +- "WRAP_EVENT_S_EINT10", +- "PMU_INT", +- "I2S2_WS_ALC5650", +- "I2S2_BCK_ALC5650", +- "PWR_BTN_1V8", +- "DA9212_IRQ", +- "IDDIG", +- "WATCHDOG", +- "CEC", +- "HDMISCK", +- "HDMISD", +- "HTPLG", +- "MSDC3_DAT0", +- "MSDC3_DAT1", +- "MSDC3_DAT2", +- "MSDC3_DAT3", +- "MSDC3_CLK", +- "MSDC3_CMD", +- "USB_C0_OC_FLAGB", +- "USBA_OC1_L", +- "PS8640_1V2_ENABLE", +- "THERM_ALERT_N", +- "PANEL_LCD_POWER_EN", +- "ANX7688_CHIP_PD_C", +- "EC_IN_RW_1V8", +- "ANX7688_1V_EN_C", +- "USB_DP_HPD_C", +- "TPM_DAVINT_N", +- "MARVELL8897_IRQ", +- "EN_USB_A0_PWR", +- "USBA_A0_OC_L", +- "EN_PP3300_DX_EDP", +- "", +- "SOC_I2C2_1V8_SDA_400K", +- "SOC_I2C2_1V8_SCL_400K", +- "SOC_I2C0_1V8_SDA_400K", +- "SOC_I2C0_1V8_SCL_400K", +- "EMMC_ID1", +- "EMMC_ID0", +- "MEM_CONFIG3", +- "EMMC_ID2", +- "MEM_CONFIG1", +- "MEM_CONFIG2", +- "BRD_ID2", +- "MEM_CONFIG0", +- "BRD_ID0", +- "BRD_ID1", +- "EMMC_DAT0", +- "EMMC_DAT1", +- "EMMC_DAT2", +- "EMMC_DAT3", +- "EMMC_DAT4", +- "EMMC_DAT5", +- "EMMC_DAT6", +- "EMMC_DAT7", +- "EMMC_CLK", +- "EMMC_CMD", +- "EMMC_RCLK", +- "PLT_RST_L", +- "LID_OPEN_1V8_L", +- "AUDIO_SPI_MISO_R", +- "", +- "AC_OK_1V8", +- "SD_DATA0", +- "SD_DATA1", +- "SD_DATA2", +- "SD_DATA3", +- "SD_CLK", +- "SD_CMD", +- "PWRAP_SPI0_MI", +- "PWRAP_SPI0_MO", +- "PWRAP_SPI0_CK", +- "PWRAP_SPI0_CSN", +- "", +- "", +- "WIFI_PDN", +- "RTC32K_1V8", +- "DISP_PWM0", +- "TOUCHSCREEN_INT_L", +- "", +- "SRCLKENA0", +- "SRCLKENA1", +- "PS8640_MODE_CONF", +- "TOUCHSCREEN_RESET_R", +- "PLATFORM_PROCHOT_L", +- "PANEL_POWER_EN", +- "REC_MODE_L", +- "EC_FW_UPDATE_L", +- "ACCEL2_INT_L", +- "HDMI_DP_INT", +- "ACCELGYRO3_INT_L", +- "ACCELGYRO4_INT_L", +- "SPI_EC_CLK", +- "SPI_EC_MI", +- "SPI_EC_MO", +- "SPI_EC_CSN", +- "SOC_I2C3_1V8_SDA_400K", +- "SOC_I2C3_1V8_SCL_400K", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "PS8640_SYSRSTN_1V8", +- "APIN_MAX98090_DOUT2", +- "TP_INT_1V8_L_R", +- "RST_USB_HUB_R", +- "BT_WAKE_L", +- "ACCEL1_INT_L", +- "TABLET_MODE_L", +- "", +- "V_UP_IN_L_R", +- "V_DOWN_IN_L_R", +- "SOC_I2C1_1V8_SDA_1M", +- "SOC_I2C1_1V8_SCL_1M", +- "PS8640_PDN_1V8", +- "MAX98090_LRCLK", +- "MAX98090_BCLK", +- "MAX98090_MCLK", +- "APOUT_MAX98090_DIN", +- "APIN_MAX98090_DOUT", +- "SOC_I2C4_1V8_SDA_400K", +- "SOC_I2C4_1V8_SCL_400K"; +- +- aud_i2s2: aud_i2s2 { +- pins1 { +- pinmux = , +- , +- , +- , +- , +- , +- ; +- bias-pull-down; +- }; +- }; +- +- bl_fixed_pins: bl_fixed_pins { +- pins1 { +- pinmux = ; +- output-low; +- }; +- }; +- +- bt_wake_pins: bt_wake_pins { +- pins1 { +- pinmux = ; +- bias-pull-up; +- }; +- }; +- +- disp_pwm0_pins: disp_pwm0_pins { +- pins1 { +- pinmux = ; +- output-low; +- }; +- }; +- +- gpio_keys_pins: gpio_keys_pins { +- volume_pins { +- pinmux = , +- ; +- bias-pull-up; +- }; +- +- tablet_mode_pins { +- pinmux = ; +- bias-pull-up; +- }; +- }; +- +- hdmi_mux_pins: hdmi_mux_pins { +- pins1 { +- pinmux = ; +- }; +- }; +- +- i2c1_pins_a: i2c1 { +- da9211_pins { +- pinmux = ; +- bias-pull-up; +- }; +- }; +- +- mmc0_pins_default: mmc0default { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- ; +- bias-pull-up; +- }; +- +- pins_clk { +- pinmux = ; +- bias-pull-down; +- }; +- +- pins_rst { +- pinmux = ; +- bias-pull-up; +- }; +- }; +- +- mmc1_pins_default: mmc1default { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- ; +- input-enable; +- drive-strength = ; +- bias-pull-up = ; +- }; +- +- pins_clk { +- pinmux = ; +- bias-pull-down; +- drive-strength = ; +- }; +- +- pins_insert { +- pinmux = ; +- bias-pull-up; +- }; +- }; +- +- mmc3_pins_default: mmc3default { +- pins_dat { +- pinmux = , +- , +- , +- ; +- input-enable; +- drive-strength = ; +- bias-pull-up = ; +- }; +- +- pins_cmd { +- pinmux = ; +- input-enable; +- drive-strength = ; +- bias-pull-up = ; +- }; +- +- pins_clk { +- pinmux = ; +- bias-pull-down; +- drive-strength = ; +- }; +- }; +- +- mmc0_pins_uhs: mmc0 { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- ; +- input-enable; +- drive-strength = ; +- bias-pull-up = ; +- }; +- +- pins_clk { +- pinmux = ; +- drive-strength = ; +- bias-pull-down = ; +- }; +- +- pins_ds { +- pinmux = ; +- drive-strength = ; +- bias-pull-down = ; +- }; +- +- pins_rst { +- pinmux = ; +- bias-pull-up; +- }; +- }; +- +- mmc1_pins_uhs: mmc1 { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- ; +- input-enable; +- drive-strength = ; +- bias-pull-up = ; +- }; +- +- pins_clk { +- pinmux = ; +- drive-strength = ; +- bias-pull-down = ; +- }; +- }; +- +- mmc3_pins_uhs: mmc3 { +- pins_dat { +- pinmux = , +- , +- , +- ; +- input-enable; +- drive-strength = ; +- bias-pull-up = ; +- }; +- +- pins_cmd { +- pinmux = ; +- input-enable; +- drive-strength = ; +- bias-pull-up = ; +- }; +- +- pins_clk { +- pinmux = ; +- drive-strength = ; +- bias-pull-down = ; +- }; +- }; +- +- nor_gpio1_pins: nor { +- pins1 { +- pinmux = , +- , +- ; +- input-enable; +- drive-strength = ; +- bias-pull-up; +- }; +- +- pins2 { +- pinmux = ; +- drive-strength = ; +- bias-pull-up; +- }; +- +- pins_clk { +- pinmux = ; +- input-enable; +- drive-strength = ; +- bias-pull-up; +- }; +- }; +- +- panel_fixed_pins: panel_fixed_pins { +- pins1 { +- pinmux = ; +- }; +- }; +- +- ps8640_pins: ps8640_pins { +- pins1 { +- pinmux = , +- , +- ; +- }; +- }; +- +- ps8640_fixed_pins: ps8640_fixed_pins { +- pins1 { +- pinmux = ; +- }; +- }; +- +- rt5650_irq: rt5650_irq { +- pins1 { +- pinmux = ; +- bias-pull-down; +- }; +- }; +- +- sdio_fixed_3v3_pins: sdio_fixed_3v3_pins { +- pins1 { +- pinmux = ; +- output-low; +- }; +- }; +- +- spi_pins_a: spi1 { +- pins1 { +- pinmux = ; +- bias-pull-up; +- }; +- +- pins_spi { +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- }; +- +- trackpad_irq: trackpad_irq { +- pins1 { +- pinmux = ; +- input-enable; +- bias-pull-up; +- }; +- }; +- +- usb_pins: usb { +- pins1 { +- pinmux = ; +- output-high; +- bias-disable; +- }; +- }; +- +- wifi_wake_pins: wifi_wake_pins { +- pins1 { +- pinmux = ; +- bias-pull-up; +- }; +- }; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&pwrap { +- pmic: mt6397 { +- compatible = "mediatek,mt6397"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&pio>; +- interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- clock: mt6397clock { +- compatible = "mediatek,mt6397-clk"; +- #clock-cells = <1>; +- }; +- +- pio6397: pinctrl { +- compatible = "mediatek,mt6397-pinctrl"; +- pins-are-numbered; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- regulator: mt6397regulator { +- compatible = "mediatek,mt6397-regulator"; +- +- mt6397_vpca15_reg: buck_vpca15 { +- regulator-compatible = "buck_vpca15"; +- regulator-name = "vpca15"; +- regulator-min-microvolt = < 700000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- regulator-allowed-modes = <0 1>; +- }; +- +- mt6397_vpca7_reg: buck_vpca7 { +- regulator-compatible = "buck_vpca7"; +- regulator-name = "vpca7"; +- regulator-min-microvolt = < 700000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <12500>; +- regulator-enable-ramp-delay = <115>; +- regulator-always-on; +- }; +- +- mt6397_vsramca15_reg: buck_vsramca15 { +- regulator-compatible = "buck_vsramca15"; +- regulator-name = "vsramca15"; +- regulator-min-microvolt = < 700000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- }; +- +- mt6397_vsramca7_reg: buck_vsramca7 { +- regulator-compatible = "buck_vsramca7"; +- regulator-name = "vsramca7"; +- regulator-min-microvolt = < 700000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- }; +- +- mt6397_vcore_reg: buck_vcore { +- regulator-compatible = "buck_vcore"; +- regulator-name = "vcore"; +- regulator-min-microvolt = < 700000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- }; +- +- mt6397_vgpu_reg: buck_vgpu { +- regulator-compatible = "buck_vgpu"; +- regulator-name = "vgpu"; +- regulator-min-microvolt = < 700000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <12500>; +- regulator-enable-ramp-delay = <115>; +- }; +- +- mt6397_vdrm_reg: buck_vdrm { +- regulator-compatible = "buck_vdrm"; +- regulator-name = "vdrm"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1400000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- }; +- +- mt6397_vio18_reg: buck_vio18 { +- regulator-compatible = "buck_vio18"; +- regulator-name = "vio18"; +- regulator-min-microvolt = <1620000>; +- regulator-max-microvolt = <1980000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- }; +- +- mt6397_vtcxo_reg: ldo_vtcxo { +- regulator-compatible = "ldo_vtcxo"; +- regulator-name = "vtcxo"; +- regulator-always-on; +- }; +- +- mt6397_va28_reg: ldo_va28 { +- regulator-compatible = "ldo_va28"; +- regulator-name = "va28"; +- }; +- +- mt6397_vcama_reg: ldo_vcama { +- regulator-compatible = "ldo_vcama"; +- regulator-name = "vcama"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vio28_reg: ldo_vio28 { +- regulator-compatible = "ldo_vio28"; +- regulator-name = "vio28"; +- regulator-always-on; +- }; +- +- mt6397_vusb_reg: ldo_vusb { +- regulator-compatible = "ldo_vusb"; +- regulator-name = "vusb"; +- }; +- +- mt6397_vmc_reg: ldo_vmc { +- regulator-compatible = "ldo_vmc"; +- regulator-name = "vmc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vmch_reg: ldo_vmch { +- regulator-compatible = "ldo_vmch"; +- regulator-name = "vmch"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vemc_3v3_reg: ldo_vemc3v3 { +- regulator-compatible = "ldo_vemc3v3"; +- regulator-name = "vemc_3v3"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vgp1_reg: ldo_vgp1 { +- regulator-compatible = "ldo_vgp1"; +- regulator-name = "vcamd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <240>; +- }; +- +- mt6397_vgp2_reg: ldo_vgp2 { +- regulator-compatible = "ldo_vgp2"; +- regulator-name = "vcamio"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vgp3_reg: ldo_vgp3 { +- regulator-compatible = "ldo_vgp3"; +- regulator-name = "vcamaf"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vgp4_reg: ldo_vgp4 { +- regulator-compatible = "ldo_vgp4"; +- regulator-name = "vgp4"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vgp5_reg: ldo_vgp5 { +- regulator-compatible = "ldo_vgp5"; +- regulator-name = "vgp5"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3000000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vgp6_reg: ldo_vgp6 { +- regulator-compatible = "ldo_vgp6"; +- regulator-name = "vgp6"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- regulator-always-on; +- }; +- +- mt6397_vibr_reg: ldo_vibr { +- regulator-compatible = "ldo_vibr"; +- regulator-name = "vibr"; +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- }; +- +- rtc: mt6397rtc { +- compatible = "mediatek,mt6397-rtc"; +- }; +- +- syscfg_pctl_pmic: syscfg_pctl_pmic@c000 { +- compatible = "mediatek,mt6397-pctl-pmic-syscfg", +- "syscon"; +- reg = <0 0x0000c000 0 0x0108>; +- }; +- }; +-}; +- +-&spi { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_pins_a>; +- mediatek,pad-select = <1>; +- status = "okay"; +- /* clients */ +- cros_ec: ec@0 { +- compatible = "google,cros-ec-spi"; +- reg = <0x0>; +- spi-max-frequency = <12000000>; +- interrupt-parent = <&pio>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- google,cros-ec-spi-msg-delay = <500>; +- +- i2c_tunnel: i2c-tunnel0 { +- compatible = "google,cros-ec-i2c-tunnel"; +- google,remote-bus = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- battery: sbs-battery@b { +- compatible = "sbs,sbs-battery"; +- reg = <0xb>; +- sbs,i2c-retry-count = <2>; +- sbs,poll-retry-count = <1>; +- }; +- }; +- }; +-}; +- +-&ssusb { +- dr_mode = "host"; +- wakeup-source; +- vusb33-supply = <&mt6397_vusb_reg>; +- status = "okay"; +-}; +- +-&thermal { +- bank0-supply = <&mt6397_vpca15_reg>; +- bank1-supply = <&da9211_vcpu_reg>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&usb_host { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_pins>; +- vusb33-supply = <&mt6397_vusb_reg>; +- status = "okay"; +-}; +- +-#include +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-evb.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-evb.dts +deleted file mode 100644 +index 4fa1e93302c7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-evb.dts ++++ /dev/null +@@ -1,536 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2014 MediaTek Inc. +- * Author: Eddie Huang +- */ +- +-/dts-v1/; +-#include +-#include "mt8173.dtsi" +- +-/ { +- model = "MediaTek MT8173 evaluation board"; +- compatible = "mediatek,mt8173-evb", "mediatek,mt8173"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x80000000>; +- }; +- +- chosen { }; +- +- connector { +- compatible = "hdmi-connector"; +- label = "hdmi"; +- type = "d"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi0_out>; +- }; +- }; +- }; +- +- extcon_usb: extcon_iddig { +- compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&pio 16 GPIO_ACTIVE_HIGH>; +- }; +- +- usb_p1_vbus: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "usb_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&pio 130 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- usb_p0_vbus: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&pio 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&mfg_async { +- domain-supply = <&da9211_vgpu_reg>; +-}; +- +-&cec { +- status = "okay"; +-}; +- +-&cpu0 { +- proc-supply = <&mt6397_vpca15_reg>; +-}; +- +-&cpu1 { +- proc-supply = <&mt6397_vpca15_reg>; +-}; +- +-&cpu2 { +- proc-supply = <&da9211_vcpu_reg>; +- sram-supply = <&mt6397_vsramca7_reg>; +-}; +- +-&cpu3 { +- proc-supply = <&da9211_vcpu_reg>; +- sram-supply = <&mt6397_vsramca7_reg>; +-}; +- +-&dpi0 { +- status = "okay"; +-}; +- +-&hdmi_phy { +- status = "okay"; +-}; +- +-&hdmi0 { +- status = "okay"; +- +- ports { +- port@1 { +- reg = <1>; +- +- hdmi0_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- buck: da9211@68 { +- compatible = "dlg,da9211"; +- reg = <0x68>; +- +- regulators { +- da9211_vcpu_reg: BUCKA { +- regulator-name = "VBUCKA"; +- regulator-min-microvolt = < 700000>; +- regulator-max-microvolt = <1310000>; +- regulator-min-microamp = <2000000>; +- regulator-max-microamp = <4400000>; +- regulator-ramp-delay = <10000>; +- regulator-always-on; +- }; +- +- da9211_vgpu_reg: BUCKB { +- regulator-name = "VBUCKB"; +- regulator-min-microvolt = < 700000>; +- regulator-max-microvolt = <1310000>; +- regulator-min-microamp = <2000000>; +- regulator-max-microamp = <3000000>; +- regulator-ramp-delay = <10000>; +- }; +- }; +- }; +-}; +- +-&mmc0 { +- status = "okay"; +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc0_pins_default>; +- pinctrl-1 = <&mmc0_pins_uhs>; +- bus-width = <8>; +- max-frequency = <50000000>; +- cap-mmc-highspeed; +- mediatek,hs200-cmd-int-delay=<26>; +- mediatek,hs400-cmd-int-delay=<14>; +- mediatek,hs400-cmd-resp-sel-rising; +- vmmc-supply = <&mt6397_vemc_3v3_reg>; +- vqmmc-supply = <&mt6397_vio18_reg>; +- non-removable; +-}; +- +-&mmc1 { +- status = "okay"; +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc1_pins_default>; +- pinctrl-1 = <&mmc1_pins_uhs>; +- bus-width = <4>; +- max-frequency = <50000000>; +- cap-sd-highspeed; +- sd-uhs-sdr25; +- cd-gpios = <&pio 132 0>; +- vmmc-supply = <&mt6397_vmch_reg>; +- vqmmc-supply = <&mt6397_vmc_reg>; +-}; +- +-&pio { +- disp_pwm0_pins: disp_pwm0_pins { +- pins1 { +- pinmux = ; +- output-low; +- }; +- }; +- +- mmc0_pins_default: mmc0default { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- ; +- input-enable; +- bias-pull-up; +- }; +- +- pins_clk { +- pinmux = ; +- bias-pull-down; +- }; +- +- pins_rst { +- pinmux = ; +- bias-pull-up; +- }; +- }; +- +- mmc1_pins_default: mmc1default { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- ; +- input-enable; +- drive-strength = ; +- bias-pull-up = ; +- }; +- +- pins_clk { +- pinmux = ; +- bias-pull-down; +- drive-strength = ; +- }; +- +- pins_insert { +- pinmux = ; +- bias-pull-up; +- }; +- }; +- +- mmc0_pins_uhs: mmc0 { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- ; +- input-enable; +- drive-strength = ; +- bias-pull-up = ; +- }; +- +- pins_clk { +- pinmux = ; +- drive-strength = ; +- bias-pull-down = ; +- }; +- +- pins_rst { +- pinmux = ; +- bias-pull-up; +- }; +- }; +- +- mmc1_pins_uhs: mmc1 { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- ; +- input-enable; +- drive-strength = ; +- bias-pull-up = ; +- }; +- +- pins_clk { +- pinmux = ; +- drive-strength = ; +- bias-pull-down = ; +- }; +- }; +- +- usb_id_pins_float: usb_iddig_pull_up { +- pins_iddig { +- pinmux = ; +- bias-pull-up; +- }; +- }; +- +- usb_id_pins_ground: usb_iddig_pull_down { +- pins_iddig { +- pinmux = ; +- bias-pull-down; +- }; +- }; +-}; +- +-&pwm0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&disp_pwm0_pins>; +- status = "okay"; +-}; +- +-&pwrap { +- /* Only MT8173 E1 needs USB power domain */ +- power-domains = <&spm MT8173_POWER_DOMAIN_USB>; +- +- pmic: mt6397 { +- compatible = "mediatek,mt6397"; +- interrupt-parent = <&pio>; +- interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- mt6397regulator: mt6397regulator { +- compatible = "mediatek,mt6397-regulator"; +- +- mt6397_vpca15_reg: buck_vpca15 { +- regulator-compatible = "buck_vpca15"; +- regulator-name = "vpca15"; +- regulator-min-microvolt = < 700000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- }; +- +- mt6397_vpca7_reg: buck_vpca7 { +- regulator-compatible = "buck_vpca7"; +- regulator-name = "vpca7"; +- regulator-min-microvolt = < 700000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <12500>; +- regulator-enable-ramp-delay = <115>; +- }; +- +- mt6397_vsramca15_reg: buck_vsramca15 { +- regulator-compatible = "buck_vsramca15"; +- regulator-name = "vsramca15"; +- regulator-min-microvolt = < 700000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- }; +- +- mt6397_vsramca7_reg: buck_vsramca7 { +- regulator-compatible = "buck_vsramca7"; +- regulator-name = "vsramca7"; +- regulator-min-microvolt = < 700000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- }; +- +- mt6397_vcore_reg: buck_vcore { +- regulator-compatible = "buck_vcore"; +- regulator-name = "vcore"; +- regulator-min-microvolt = < 700000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- }; +- +- mt6397_vgpu_reg: buck_vgpu { +- regulator-compatible = "buck_vgpu"; +- regulator-name = "vgpu"; +- regulator-min-microvolt = < 700000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <12500>; +- regulator-enable-ramp-delay = <115>; +- }; +- +- mt6397_vdrm_reg: buck_vdrm { +- regulator-compatible = "buck_vdrm"; +- regulator-name = "vdrm"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1400000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- }; +- +- mt6397_vio18_reg: buck_vio18 { +- regulator-compatible = "buck_vio18"; +- regulator-name = "vio18"; +- regulator-min-microvolt = <1620000>; +- regulator-max-microvolt = <1980000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- }; +- +- mt6397_vtcxo_reg: ldo_vtcxo { +- regulator-compatible = "ldo_vtcxo"; +- regulator-name = "vtcxo"; +- regulator-always-on; +- }; +- +- mt6397_va28_reg: ldo_va28 { +- regulator-compatible = "ldo_va28"; +- regulator-name = "va28"; +- regulator-always-on; +- }; +- +- mt6397_vcama_reg: ldo_vcama { +- regulator-compatible = "ldo_vcama"; +- regulator-name = "vcama"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <2800000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vio28_reg: ldo_vio28 { +- regulator-compatible = "ldo_vio28"; +- regulator-name = "vio28"; +- regulator-always-on; +- }; +- +- mt6397_vusb_reg: ldo_vusb { +- regulator-compatible = "ldo_vusb"; +- regulator-name = "vusb"; +- }; +- +- mt6397_vmc_reg: ldo_vmc { +- regulator-compatible = "ldo_vmc"; +- regulator-name = "vmc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vmch_reg: ldo_vmch { +- regulator-compatible = "ldo_vmch"; +- regulator-name = "vmch"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vemc_3v3_reg: ldo_vemc3v3 { +- regulator-compatible = "ldo_vemc3v3"; +- regulator-name = "vemc_3v3"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vgp1_reg: ldo_vgp1 { +- regulator-compatible = "ldo_vgp1"; +- regulator-name = "vcamd"; +- regulator-min-microvolt = <1220000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <240>; +- }; +- +- mt6397_vgp2_reg: ldo_vgp2 { +- regulator-compatible = "ldo_vgp2"; +- regulator-name = "vcamio"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vgp3_reg: ldo_vgp3 { +- regulator-compatible = "ldo_vgp3"; +- regulator-name = "vcamaf"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vgp4_reg: ldo_vgp4 { +- regulator-compatible = "ldo_vgp4"; +- regulator-name = "vgp4"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vgp5_reg: ldo_vgp5 { +- regulator-compatible = "ldo_vgp5"; +- regulator-name = "vgp5"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3000000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vgp6_reg: ldo_vgp6 { +- regulator-compatible = "ldo_vgp6"; +- regulator-name = "vgp6"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- +- mt6397_vibr_reg: ldo_vibr { +- regulator-compatible = "ldo_vibr"; +- regulator-name = "vibr"; +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <218>; +- }; +- }; +- }; +-}; +- +-&pio { +- spi_pins_a: spi0 { +- pins_spi { +- pinmux = , +- , +- , +- ; +- }; +- }; +-}; +- +-&spi { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_pins_a>; +- mediatek,pad-select = <0>; +- status = "okay"; +-}; +- +-&ssusb { +- vusb33-supply = <&mt6397_vusb_reg>; +- vbus-supply = <&usb_p0_vbus>; +- extcon = <&extcon_usb>; +- dr_mode = "otg"; +- wakeup-source; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_id_pins_float>; +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&usb_host { +- vusb33-supply = <&mt6397_vusb_reg>; +- vbus-supply = <&usb_p1_vbus>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-pinfunc.h b/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-pinfunc.h +deleted file mode 100644 +index a5e308dc8545..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8173-pinfunc.h ++++ /dev/null +@@ -1,674 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014 MediaTek Inc. +- * Author: Hongzhou.Yang +- */ +- +-#ifndef __DTS_MT8173_PINFUNC_H +-#define __DTS_MT8173_PINFUNC_H +- +-#include +- +-#define MT8173_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +-#define MT8173_PIN_0_EINT0__FUNC_IRDA_PDN (MTK_PIN_NO(0) | 1) +-#define MT8173_PIN_0_EINT0__FUNC_I2S1_WS (MTK_PIN_NO(0) | 2) +-#define MT8173_PIN_0_EINT0__FUNC_AUD_SPDIF (MTK_PIN_NO(0) | 3) +-#define MT8173_PIN_0_EINT0__FUNC_UTXD0 (MTK_PIN_NO(0) | 4) +-#define MT8173_PIN_0_EINT0__FUNC_DBG_MON_A_20_ (MTK_PIN_NO(0) | 7) +- +-#define MT8173_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +-#define MT8173_PIN_1_EINT1__FUNC_IRDA_RXD (MTK_PIN_NO(1) | 1) +-#define MT8173_PIN_1_EINT1__FUNC_I2S1_BCK (MTK_PIN_NO(1) | 2) +-#define MT8173_PIN_1_EINT1__FUNC_SDA5 (MTK_PIN_NO(1) | 3) +-#define MT8173_PIN_1_EINT1__FUNC_URXD0 (MTK_PIN_NO(1) | 4) +-#define MT8173_PIN_1_EINT1__FUNC_DBG_MON_A_21_ (MTK_PIN_NO(1) | 7) +- +-#define MT8173_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +-#define MT8173_PIN_2_EINT2__FUNC_IRDA_TXD (MTK_PIN_NO(2) | 1) +-#define MT8173_PIN_2_EINT2__FUNC_I2S1_MCK (MTK_PIN_NO(2) | 2) +-#define MT8173_PIN_2_EINT2__FUNC_SCL5 (MTK_PIN_NO(2) | 3) +-#define MT8173_PIN_2_EINT2__FUNC_UTXD3 (MTK_PIN_NO(2) | 4) +-#define MT8173_PIN_2_EINT2__FUNC_DBG_MON_A_22_ (MTK_PIN_NO(2) | 7) +- +-#define MT8173_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +-#define MT8173_PIN_3_EINT3__FUNC_DSI1_TE (MTK_PIN_NO(3) | 1) +-#define MT8173_PIN_3_EINT3__FUNC_I2S1_DO_1 (MTK_PIN_NO(3) | 2) +-#define MT8173_PIN_3_EINT3__FUNC_SDA3 (MTK_PIN_NO(3) | 3) +-#define MT8173_PIN_3_EINT3__FUNC_URXD3 (MTK_PIN_NO(3) | 4) +-#define MT8173_PIN_3_EINT3__FUNC_DBG_MON_A_23_ (MTK_PIN_NO(3) | 7) +- +-#define MT8173_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +-#define MT8173_PIN_4_EINT4__FUNC_DISP_PWM1 (MTK_PIN_NO(4) | 1) +-#define MT8173_PIN_4_EINT4__FUNC_I2S1_DO_2 (MTK_PIN_NO(4) | 2) +-#define MT8173_PIN_4_EINT4__FUNC_SCL3 (MTK_PIN_NO(4) | 3) +-#define MT8173_PIN_4_EINT4__FUNC_UCTS3 (MTK_PIN_NO(4) | 4) +-#define MT8173_PIN_4_EINT4__FUNC_SFWP_B (MTK_PIN_NO(4) | 6) +- +-#define MT8173_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +-#define MT8173_PIN_5_EINT5__FUNC_PCM1_CLK (MTK_PIN_NO(5) | 1) +-#define MT8173_PIN_5_EINT5__FUNC_I2S2_WS (MTK_PIN_NO(5) | 2) +-#define MT8173_PIN_5_EINT5__FUNC_SPI_CK_3_ (MTK_PIN_NO(5) | 3) +-#define MT8173_PIN_5_EINT5__FUNC_URTS3 (MTK_PIN_NO(5) | 4) +-#define MT8173_PIN_5_EINT5__FUNC_AP_MD32_JTAG_TMS (MTK_PIN_NO(5) | 5) +-#define MT8173_PIN_5_EINT5__FUNC_SFOUT (MTK_PIN_NO(5) | 6) +- +-#define MT8173_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +-#define MT8173_PIN_6_EINT6__FUNC_PCM1_SYNC (MTK_PIN_NO(6) | 1) +-#define MT8173_PIN_6_EINT6__FUNC_I2S2_BCK (MTK_PIN_NO(6) | 2) +-#define MT8173_PIN_6_EINT6__FUNC_SPI_MI_3_ (MTK_PIN_NO(6) | 3) +-#define MT8173_PIN_6_EINT6__FUNC_AP_MD32_JTAG_TCK (MTK_PIN_NO(6) | 5) +-#define MT8173_PIN_6_EINT6__FUNC_SFCS0 (MTK_PIN_NO(6) | 6) +- +-#define MT8173_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +-#define MT8173_PIN_7_EINT7__FUNC_PCM1_DI (MTK_PIN_NO(7) | 1) +-#define MT8173_PIN_7_EINT7__FUNC_I2S2_DI_1 (MTK_PIN_NO(7) | 2) +-#define MT8173_PIN_7_EINT7__FUNC_SPI_MO_3_ (MTK_PIN_NO(7) | 3) +-#define MT8173_PIN_7_EINT7__FUNC_AP_MD32_JTAG_TDI (MTK_PIN_NO(7) | 5) +-#define MT8173_PIN_7_EINT7__FUNC_SFHOLD (MTK_PIN_NO(7) | 6) +- +-#define MT8173_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +-#define MT8173_PIN_8_EINT8__FUNC_PCM1_DO (MTK_PIN_NO(8) | 1) +-#define MT8173_PIN_8_EINT8__FUNC_I2S2_DI_2 (MTK_PIN_NO(8) | 2) +-#define MT8173_PIN_8_EINT8__FUNC_SPI_CS_3_ (MTK_PIN_NO(8) | 3) +-#define MT8173_PIN_8_EINT8__FUNC_AUD_SPDIF (MTK_PIN_NO(8) | 4) +-#define MT8173_PIN_8_EINT8__FUNC_AP_MD32_JTAG_TDO (MTK_PIN_NO(8) | 5) +-#define MT8173_PIN_8_EINT8__FUNC_SFIN (MTK_PIN_NO(8) | 6) +- +-#define MT8173_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +-#define MT8173_PIN_9_EINT9__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(9) | 1) +-#define MT8173_PIN_9_EINT9__FUNC_I2S2_MCK (MTK_PIN_NO(9) | 2) +-#define MT8173_PIN_9_EINT9__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(9) | 4) +-#define MT8173_PIN_9_EINT9__FUNC_AP_MD32_JTAG_TRST (MTK_PIN_NO(9) | 5) +-#define MT8173_PIN_9_EINT9__FUNC_SFCK (MTK_PIN_NO(9) | 6) +- +-#define MT8173_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +-#define MT8173_PIN_10_EINT10__FUNC_CLKM0 (MTK_PIN_NO(10) | 1) +-#define MT8173_PIN_10_EINT10__FUNC_DSI1_TE (MTK_PIN_NO(10) | 2) +-#define MT8173_PIN_10_EINT10__FUNC_DISP_PWM1 (MTK_PIN_NO(10) | 3) +-#define MT8173_PIN_10_EINT10__FUNC_PWM4 (MTK_PIN_NO(10) | 4) +-#define MT8173_PIN_10_EINT10__FUNC_IRDA_RXD (MTK_PIN_NO(10) | 5) +- +-#define MT8173_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +-#define MT8173_PIN_11_EINT11__FUNC_CLKM1 (MTK_PIN_NO(11) | 1) +-#define MT8173_PIN_11_EINT11__FUNC_I2S3_WS (MTK_PIN_NO(11) | 2) +-#define MT8173_PIN_11_EINT11__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(11) | 3) +-#define MT8173_PIN_11_EINT11__FUNC_PWM5 (MTK_PIN_NO(11) | 4) +-#define MT8173_PIN_11_EINT11__FUNC_IRDA_TXD (MTK_PIN_NO(11) | 5) +-#define MT8173_PIN_11_EINT11__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(11) | 6) +-#define MT8173_PIN_11_EINT11__FUNC_DBG_MON_B_30_ (MTK_PIN_NO(11) | 7) +- +-#define MT8173_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +-#define MT8173_PIN_12_EINT12__FUNC_CLKM2 (MTK_PIN_NO(12) | 1) +-#define MT8173_PIN_12_EINT12__FUNC_I2S3_BCK (MTK_PIN_NO(12) | 2) +-#define MT8173_PIN_12_EINT12__FUNC_SRCLKENA0 (MTK_PIN_NO(12) | 3) +-#define MT8173_PIN_12_EINT12__FUNC_I2S2_WS (MTK_PIN_NO(12) | 5) +-#define MT8173_PIN_12_EINT12__FUNC_DBG_MON_B_32_ (MTK_PIN_NO(12) | 7) +- +-#define MT8173_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +-#define MT8173_PIN_13_EINT13__FUNC_CLKM3 (MTK_PIN_NO(13) | 1) +-#define MT8173_PIN_13_EINT13__FUNC_I2S3_MCK (MTK_PIN_NO(13) | 2) +-#define MT8173_PIN_13_EINT13__FUNC_SRCLKENA0 (MTK_PIN_NO(13) | 3) +-#define MT8173_PIN_13_EINT13__FUNC_I2S2_BCK (MTK_PIN_NO(13) | 5) +-#define MT8173_PIN_13_EINT13__FUNC_DBG_MON_A_32_ (MTK_PIN_NO(13) | 7) +- +-#define MT8173_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +-#define MT8173_PIN_14_EINT14__FUNC_CMDAT0 (MTK_PIN_NO(14) | 1) +-#define MT8173_PIN_14_EINT14__FUNC_CMCSD0 (MTK_PIN_NO(14) | 2) +-#define MT8173_PIN_14_EINT14__FUNC_CLKM2 (MTK_PIN_NO(14) | 4) +-#define MT8173_PIN_14_EINT14__FUNC_DBG_MON_B_6_ (MTK_PIN_NO(14) | 7) +- +-#define MT8173_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +-#define MT8173_PIN_15_EINT15__FUNC_CMDAT1 (MTK_PIN_NO(15) | 1) +-#define MT8173_PIN_15_EINT15__FUNC_CMCSD1 (MTK_PIN_NO(15) | 2) +-#define MT8173_PIN_15_EINT15__FUNC_CMFLASH (MTK_PIN_NO(15) | 3) +-#define MT8173_PIN_15_EINT15__FUNC_CLKM3 (MTK_PIN_NO(15) | 4) +-#define MT8173_PIN_15_EINT15__FUNC_DBG_MON_B_29_ (MTK_PIN_NO(15) | 7) +- +-#define MT8173_PIN_16_IDDIG__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +-#define MT8173_PIN_16_IDDIG__FUNC_IDDIG (MTK_PIN_NO(16) | 1) +-#define MT8173_PIN_16_IDDIG__FUNC_CMFLASH (MTK_PIN_NO(16) | 2) +-#define MT8173_PIN_16_IDDIG__FUNC_PWM5 (MTK_PIN_NO(16) | 4) +- +-#define MT8173_PIN_17_WATCHDOG__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +-#define MT8173_PIN_17_WATCHDOG__FUNC_WATCHDOG_AO (MTK_PIN_NO(17) | 1) +- +-#define MT8173_PIN_18_CEC__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +-#define MT8173_PIN_18_CEC__FUNC_CEC (MTK_PIN_NO(18) | 1) +- +-#define MT8173_PIN_19_HDMISCK__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +-#define MT8173_PIN_19_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(19) | 1) +-#define MT8173_PIN_19_HDMISCK__FUNC_HDCP_SCL (MTK_PIN_NO(19) | 2) +- +-#define MT8173_PIN_20_HDMISD__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +-#define MT8173_PIN_20_HDMISD__FUNC_HDMISD (MTK_PIN_NO(20) | 1) +-#define MT8173_PIN_20_HDMISD__FUNC_HDCP_SDA (MTK_PIN_NO(20) | 2) +- +-#define MT8173_PIN_21_HTPLG__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +-#define MT8173_PIN_21_HTPLG__FUNC_HTPLG (MTK_PIN_NO(21) | 1) +- +-#define MT8173_PIN_22_MSDC3_DAT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +-#define MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(22) | 1) +- +-#define MT8173_PIN_23_MSDC3_DAT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +-#define MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(23) | 1) +- +-#define MT8173_PIN_24_MSDC3_DAT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +-#define MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(24) | 1) +- +-#define MT8173_PIN_25_MSDC3_DAT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +-#define MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(25) | 1) +- +-#define MT8173_PIN_26_MSDC3_CLK__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +-#define MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(26) | 1) +- +-#define MT8173_PIN_27_MSDC3_CMD__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +-#define MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(27) | 1) +- +-#define MT8173_PIN_28_MSDC3_DSL__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +-#define MT8173_PIN_28_MSDC3_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(28) | 1) +- +-#define MT8173_PIN_29_UCTS2__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +-#define MT8173_PIN_29_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(29) | 1) +- +-#define MT8173_PIN_30_URTS2__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +-#define MT8173_PIN_30_URTS2__FUNC_URTS2 (MTK_PIN_NO(30) | 1) +- +-#define MT8173_PIN_31_URXD2__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +-#define MT8173_PIN_31_URXD2__FUNC_URXD2 (MTK_PIN_NO(31) | 1) +-#define MT8173_PIN_31_URXD2__FUNC_UTXD2 (MTK_PIN_NO(31) | 2) +- +-#define MT8173_PIN_32_UTXD2__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +-#define MT8173_PIN_32_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(32) | 1) +-#define MT8173_PIN_32_UTXD2__FUNC_URXD2 (MTK_PIN_NO(32) | 2) +- +-#define MT8173_PIN_33_DAICLK__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +-#define MT8173_PIN_33_DAICLK__FUNC_MRG_CLK (MTK_PIN_NO(33) | 1) +-#define MT8173_PIN_33_DAICLK__FUNC_PCM0_CLK (MTK_PIN_NO(33) | 2) +- +-#define MT8173_PIN_34_DAIPCMIN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +-#define MT8173_PIN_34_DAIPCMIN__FUNC_MRG_DI (MTK_PIN_NO(34) | 1) +-#define MT8173_PIN_34_DAIPCMIN__FUNC_PCM0_DI (MTK_PIN_NO(34) | 2) +- +-#define MT8173_PIN_35_DAIPCMOUT__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +-#define MT8173_PIN_35_DAIPCMOUT__FUNC_MRG_DO (MTK_PIN_NO(35) | 1) +-#define MT8173_PIN_35_DAIPCMOUT__FUNC_PCM0_DO (MTK_PIN_NO(35) | 2) +- +-#define MT8173_PIN_36_DAISYNC__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +-#define MT8173_PIN_36_DAISYNC__FUNC_MRG_SYNC (MTK_PIN_NO(36) | 1) +-#define MT8173_PIN_36_DAISYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(36) | 2) +- +-#define MT8173_PIN_37_EINT16__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +-#define MT8173_PIN_37_EINT16__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(37) | 1) +-#define MT8173_PIN_37_EINT16__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(37) | 2) +-#define MT8173_PIN_37_EINT16__FUNC_PWM0 (MTK_PIN_NO(37) | 3) +-#define MT8173_PIN_37_EINT16__FUNC_PWM1 (MTK_PIN_NO(37) | 4) +-#define MT8173_PIN_37_EINT16__FUNC_PWM2 (MTK_PIN_NO(37) | 5) +-#define MT8173_PIN_37_EINT16__FUNC_CLKM0 (MTK_PIN_NO(37) | 6) +- +-#define MT8173_PIN_38_CONN_RST__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +-#define MT8173_PIN_38_CONN_RST__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(38) | 1) +-#define MT8173_PIN_38_CONN_RST__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(38) | 2) +-#define MT8173_PIN_38_CONN_RST__FUNC_CLKM1 (MTK_PIN_NO(38) | 6) +- +-#define MT8173_PIN_39_CM2MCLK__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +-#define MT8173_PIN_39_CM2MCLK__FUNC_CM2MCLK (MTK_PIN_NO(39) | 1) +-#define MT8173_PIN_39_CM2MCLK__FUNC_CMCSD0 (MTK_PIN_NO(39) | 2) +-#define MT8173_PIN_39_CM2MCLK__FUNC_DBG_MON_A_17_ (MTK_PIN_NO(39) | 7) +- +-#define MT8173_PIN_40_CMPCLK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +-#define MT8173_PIN_40_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(40) | 1) +-#define MT8173_PIN_40_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(40) | 2) +-#define MT8173_PIN_40_CMPCLK__FUNC_CMCSD2 (MTK_PIN_NO(40) | 3) +-#define MT8173_PIN_40_CMPCLK__FUNC_DBG_MON_A_18_ (MTK_PIN_NO(40) | 7) +- +-#define MT8173_PIN_41_CMMCLK__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +-#define MT8173_PIN_41_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(41) | 1) +-#define MT8173_PIN_41_CMMCLK__FUNC_DBG_MON_A_19_ (MTK_PIN_NO(41) | 7) +- +-#define MT8173_PIN_42_DSI_TE__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +-#define MT8173_PIN_42_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(42) | 1) +- +-#define MT8173_PIN_43_SDA2__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +-#define MT8173_PIN_43_SDA2__FUNC_SDA2 (MTK_PIN_NO(43) | 1) +- +-#define MT8173_PIN_44_SCL2__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +-#define MT8173_PIN_44_SCL2__FUNC_SCL2 (MTK_PIN_NO(44) | 1) +- +-#define MT8173_PIN_45_SDA0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +-#define MT8173_PIN_45_SDA0__FUNC_SDA0 (MTK_PIN_NO(45) | 1) +- +-#define MT8173_PIN_46_SCL0__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +-#define MT8173_PIN_46_SCL0__FUNC_SCL0 (MTK_PIN_NO(46) | 1) +- +-#define MT8173_PIN_47_RDN0_A__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +-#define MT8173_PIN_47_RDN0_A__FUNC_CMDAT2 (MTK_PIN_NO(47) | 1) +- +-#define MT8173_PIN_48_RDP0_A__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +-#define MT8173_PIN_48_RDP0_A__FUNC_CMDAT3 (MTK_PIN_NO(48) | 1) +- +-#define MT8173_PIN_49_RDN1_A__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +-#define MT8173_PIN_49_RDN1_A__FUNC_CMDAT4 (MTK_PIN_NO(49) | 1) +- +-#define MT8173_PIN_50_RDP1_A__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +-#define MT8173_PIN_50_RDP1_A__FUNC_CMDAT5 (MTK_PIN_NO(50) | 1) +- +-#define MT8173_PIN_51_RCN_A__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +-#define MT8173_PIN_51_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(51) | 1) +- +-#define MT8173_PIN_52_RCP_A__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +-#define MT8173_PIN_52_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(52) | 1) +- +-#define MT8173_PIN_53_RDN2_A__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +-#define MT8173_PIN_53_RDN2_A__FUNC_CMDAT8 (MTK_PIN_NO(53) | 1) +-#define MT8173_PIN_53_RDN2_A__FUNC_CMCSD3 (MTK_PIN_NO(53) | 2) +- +-#define MT8173_PIN_54_RDP2_A__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +-#define MT8173_PIN_54_RDP2_A__FUNC_CMDAT9 (MTK_PIN_NO(54) | 1) +-#define MT8173_PIN_54_RDP2_A__FUNC_CMCSD2 (MTK_PIN_NO(54) | 2) +- +-#define MT8173_PIN_55_RDN3_A__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +-#define MT8173_PIN_55_RDN3_A__FUNC_CMHSYNC (MTK_PIN_NO(55) | 1) +-#define MT8173_PIN_55_RDN3_A__FUNC_CMCSD1 (MTK_PIN_NO(55) | 2) +- +-#define MT8173_PIN_56_RDP3_A__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +-#define MT8173_PIN_56_RDP3_A__FUNC_CMVSYNC (MTK_PIN_NO(56) | 1) +-#define MT8173_PIN_56_RDP3_A__FUNC_CMCSD0 (MTK_PIN_NO(56) | 2) +- +-#define MT8173_PIN_57_MSDC0_DAT0__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +-#define MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(57) | 1) +-#define MT8173_PIN_57_MSDC0_DAT0__FUNC_I2S1_WS (MTK_PIN_NO(57) | 2) +-#define MT8173_PIN_57_MSDC0_DAT0__FUNC_DBG_MON_B_7_ (MTK_PIN_NO(57) | 7) +- +-#define MT8173_PIN_58_MSDC0_DAT1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +-#define MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(58) | 1) +-#define MT8173_PIN_58_MSDC0_DAT1__FUNC_I2S1_BCK (MTK_PIN_NO(58) | 2) +-#define MT8173_PIN_58_MSDC0_DAT1__FUNC_DBG_MON_B_8_ (MTK_PIN_NO(58) | 7) +- +-#define MT8173_PIN_59_MSDC0_DAT2__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +-#define MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(59) | 1) +-#define MT8173_PIN_59_MSDC0_DAT2__FUNC_I2S1_MCK (MTK_PIN_NO(59) | 2) +-#define MT8173_PIN_59_MSDC0_DAT2__FUNC_DBG_MON_B_9_ (MTK_PIN_NO(59) | 7) +- +-#define MT8173_PIN_60_MSDC0_DAT3__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +-#define MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(60) | 1) +-#define MT8173_PIN_60_MSDC0_DAT3__FUNC_I2S1_DO_1 (MTK_PIN_NO(60) | 2) +-#define MT8173_PIN_60_MSDC0_DAT3__FUNC_DBG_MON_B_10_ (MTK_PIN_NO(60) | 7) +- +-#define MT8173_PIN_61_MSDC0_DAT4__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +-#define MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(61) | 1) +-#define MT8173_PIN_61_MSDC0_DAT4__FUNC_I2S1_DO_2 (MTK_PIN_NO(61) | 2) +-#define MT8173_PIN_61_MSDC0_DAT4__FUNC_DBG_MON_B_11_ (MTK_PIN_NO(61) | 7) +- +-#define MT8173_PIN_62_MSDC0_DAT5__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +-#define MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(62) | 1) +-#define MT8173_PIN_62_MSDC0_DAT5__FUNC_I2S2_WS (MTK_PIN_NO(62) | 2) +-#define MT8173_PIN_62_MSDC0_DAT5__FUNC_DBG_MON_B_12_ (MTK_PIN_NO(62) | 7) +- +-#define MT8173_PIN_63_MSDC0_DAT6__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +-#define MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(63) | 1) +-#define MT8173_PIN_63_MSDC0_DAT6__FUNC_I2S2_BCK (MTK_PIN_NO(63) | 2) +-#define MT8173_PIN_63_MSDC0_DAT6__FUNC_DBG_MON_B_13_ (MTK_PIN_NO(63) | 7) +- +-#define MT8173_PIN_64_MSDC0_DAT7__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +-#define MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(64) | 1) +-#define MT8173_PIN_64_MSDC0_DAT7__FUNC_I2S2_DI_1 (MTK_PIN_NO(64) | 2) +-#define MT8173_PIN_64_MSDC0_DAT7__FUNC_DBG_MON_B_14_ (MTK_PIN_NO(64) | 7) +- +-#define MT8173_PIN_65_MSDC0_CLK__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +-#define MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(65) | 1) +-#define MT8173_PIN_65_MSDC0_CLK__FUNC_DBG_MON_B_16_ (MTK_PIN_NO(65) | 7) +- +-#define MT8173_PIN_66_MSDC0_CMD__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +-#define MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(66) | 1) +-#define MT8173_PIN_66_MSDC0_CMD__FUNC_I2S2_DI_2 (MTK_PIN_NO(66) | 2) +-#define MT8173_PIN_66_MSDC0_CMD__FUNC_DBG_MON_B_15_ (MTK_PIN_NO(66) | 7) +- +-#define MT8173_PIN_67_MSDC0_DSL__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +-#define MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(67) | 1) +-#define MT8173_PIN_67_MSDC0_DSL__FUNC_DBG_MON_B_17_ (MTK_PIN_NO(67) | 7) +- +-#define MT8173_PIN_68_MSDC0_RST___FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +-#define MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB (MTK_PIN_NO(68) | 1) +-#define MT8173_PIN_68_MSDC0_RST___FUNC_I2S2_MCK (MTK_PIN_NO(68) | 2) +-#define MT8173_PIN_68_MSDC0_RST___FUNC_DBG_MON_B_18_ (MTK_PIN_NO(68) | 7) +- +-#define MT8173_PIN_69_SPI_CK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +-#define MT8173_PIN_69_SPI_CK__FUNC_SPI_CK_0_ (MTK_PIN_NO(69) | 1) +-#define MT8173_PIN_69_SPI_CK__FUNC_I2S3_DO_1 (MTK_PIN_NO(69) | 2) +-#define MT8173_PIN_69_SPI_CK__FUNC_PWM0 (MTK_PIN_NO(69) | 3) +-#define MT8173_PIN_69_SPI_CK__FUNC_PWM5 (MTK_PIN_NO(69) | 4) +-#define MT8173_PIN_69_SPI_CK__FUNC_I2S2_MCK (MTK_PIN_NO(69) | 5) +-#define MT8173_PIN_69_SPI_CK__FUNC_DBG_MON_B_19_ (MTK_PIN_NO(69) | 7) +- +-#define MT8173_PIN_70_SPI_MI__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +-#define MT8173_PIN_70_SPI_MI__FUNC_SPI_MI_0_ (MTK_PIN_NO(70) | 1) +-#define MT8173_PIN_70_SPI_MI__FUNC_I2S3_DO_2 (MTK_PIN_NO(70) | 2) +-#define MT8173_PIN_70_SPI_MI__FUNC_PWM1 (MTK_PIN_NO(70) | 3) +-#define MT8173_PIN_70_SPI_MI__FUNC_SPI_MO_0_ (MTK_PIN_NO(70) | 4) +-#define MT8173_PIN_70_SPI_MI__FUNC_I2S2_DI_1 (MTK_PIN_NO(70) | 5) +-#define MT8173_PIN_70_SPI_MI__FUNC_DSI1_TE (MTK_PIN_NO(70) | 6) +-#define MT8173_PIN_70_SPI_MI__FUNC_DBG_MON_B_20_ (MTK_PIN_NO(70) | 7) +- +-#define MT8173_PIN_71_SPI_MO__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +-#define MT8173_PIN_71_SPI_MO__FUNC_SPI_MO_0_ (MTK_PIN_NO(71) | 1) +-#define MT8173_PIN_71_SPI_MO__FUNC_I2S3_DO_3 (MTK_PIN_NO(71) | 2) +-#define MT8173_PIN_71_SPI_MO__FUNC_PWM2 (MTK_PIN_NO(71) | 3) +-#define MT8173_PIN_71_SPI_MO__FUNC_SPI_MI_0_ (MTK_PIN_NO(71) | 4) +-#define MT8173_PIN_71_SPI_MO__FUNC_I2S2_DI_2 (MTK_PIN_NO(71) | 5) +-#define MT8173_PIN_71_SPI_MO__FUNC_DBG_MON_B_21_ (MTK_PIN_NO(71) | 7) +- +-#define MT8173_PIN_72_SPI_CS__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +-#define MT8173_PIN_72_SPI_CS__FUNC_SPI_CS_0_ (MTK_PIN_NO(72) | 1) +-#define MT8173_PIN_72_SPI_CS__FUNC_I2S3_DO_4 (MTK_PIN_NO(72) | 2) +-#define MT8173_PIN_72_SPI_CS__FUNC_PWM3 (MTK_PIN_NO(72) | 3) +-#define MT8173_PIN_72_SPI_CS__FUNC_PWM6 (MTK_PIN_NO(72) | 4) +-#define MT8173_PIN_72_SPI_CS__FUNC_DISP_PWM1 (MTK_PIN_NO(72) | 5) +-#define MT8173_PIN_72_SPI_CS__FUNC_DBG_MON_B_22_ (MTK_PIN_NO(72) | 7) +- +-#define MT8173_PIN_73_MSDC1_DAT0__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +-#define MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(73) | 1) +-#define MT8173_PIN_73_MSDC1_DAT0__FUNC_DBG_MON_B_24_ (MTK_PIN_NO(73) | 7) +- +-#define MT8173_PIN_74_MSDC1_DAT1__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +-#define MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(74) | 1) +-#define MT8173_PIN_74_MSDC1_DAT1__FUNC_DBG_MON_B_25_ (MTK_PIN_NO(74) | 7) +- +-#define MT8173_PIN_75_MSDC1_DAT2__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +-#define MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(75) | 1) +-#define MT8173_PIN_75_MSDC1_DAT2__FUNC_DBG_MON_B_26_ (MTK_PIN_NO(75) | 7) +- +-#define MT8173_PIN_76_MSDC1_DAT3__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +-#define MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(76) | 1) +-#define MT8173_PIN_76_MSDC1_DAT3__FUNC_DBG_MON_B_27_ (MTK_PIN_NO(76) | 7) +- +-#define MT8173_PIN_77_MSDC1_CLK__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +-#define MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(77) | 1) +-#define MT8173_PIN_77_MSDC1_CLK__FUNC_DBG_MON_B_28_ (MTK_PIN_NO(77) | 7) +- +-#define MT8173_PIN_78_MSDC1_CMD__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +-#define MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(78) | 1) +-#define MT8173_PIN_78_MSDC1_CMD__FUNC_DBG_MON_B_23_ (MTK_PIN_NO(78) | 7) +- +-#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +-#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_PWRAP_SPIMI (MTK_PIN_NO(79) | 1) +-#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_PWRAP_SPIMO (MTK_PIN_NO(79) | 2) +- +-#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +-#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_PWRAP_SPIMO (MTK_PIN_NO(80) | 1) +-#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_PWRAP_SPIMI (MTK_PIN_NO(80) | 2) +- +-#define MT8173_PIN_81_PWRAP_SPI0_CK__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +-#define MT8173_PIN_81_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK (MTK_PIN_NO(81) | 1) +- +-#define MT8173_PIN_82_PWRAP_SPI0_CSN__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +-#define MT8173_PIN_82_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS (MTK_PIN_NO(82) | 1) +- +-#define MT8173_PIN_83_AUD_CLK_MOSI__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +-#define MT8173_PIN_83_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(83) | 1) +- +-#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +-#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_AUD_DAT_MISO (MTK_PIN_NO(84) | 1) +-#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(84) | 2) +- +-#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +-#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(85) | 1) +-#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_AUD_DAT_MISO (MTK_PIN_NO(85) | 2) +- +-#define MT8173_PIN_86_RTC32K_CK__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +-#define MT8173_PIN_86_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(86) | 1) +- +-#define MT8173_PIN_87_DISP_PWM0__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +-#define MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0 (MTK_PIN_NO(87) | 1) +-#define MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM1 (MTK_PIN_NO(87) | 2) +-#define MT8173_PIN_87_DISP_PWM0__FUNC_DBG_MON_B_31_ (MTK_PIN_NO(87) | 7) +- +-#define MT8173_PIN_88_SRCLKENAI__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +-#define MT8173_PIN_88_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(88) | 1) +- +-#define MT8173_PIN_89_SRCLKENAI2__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +-#define MT8173_PIN_89_SRCLKENAI2__FUNC_SRCLKENAI2 (MTK_PIN_NO(89) | 1) +- +-#define MT8173_PIN_90_SRCLKENA0__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +-#define MT8173_PIN_90_SRCLKENA0__FUNC_SRCLKENA0 (MTK_PIN_NO(90) | 1) +- +-#define MT8173_PIN_91_SRCLKENA1__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +-#define MT8173_PIN_91_SRCLKENA1__FUNC_SRCLKENA1 (MTK_PIN_NO(91) | 1) +- +-#define MT8173_PIN_92_PCM_CLK__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +-#define MT8173_PIN_92_PCM_CLK__FUNC_PCM1_CLK (MTK_PIN_NO(92) | 1) +-#define MT8173_PIN_92_PCM_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(92) | 2) +-#define MT8173_PIN_92_PCM_CLK__FUNC_DBG_MON_A_24_ (MTK_PIN_NO(92) | 7) +- +-#define MT8173_PIN_93_PCM_SYNC__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +-#define MT8173_PIN_93_PCM_SYNC__FUNC_PCM1_SYNC (MTK_PIN_NO(93) | 1) +-#define MT8173_PIN_93_PCM_SYNC__FUNC_I2S0_WS (MTK_PIN_NO(93) | 2) +-#define MT8173_PIN_93_PCM_SYNC__FUNC_DBG_MON_A_25_ (MTK_PIN_NO(93) | 7) +- +-#define MT8173_PIN_94_PCM_RX__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +-#define MT8173_PIN_94_PCM_RX__FUNC_PCM1_DI (MTK_PIN_NO(94) | 1) +-#define MT8173_PIN_94_PCM_RX__FUNC_I2S0_DI (MTK_PIN_NO(94) | 2) +-#define MT8173_PIN_94_PCM_RX__FUNC_DBG_MON_A_26_ (MTK_PIN_NO(94) | 7) +- +-#define MT8173_PIN_95_PCM_TX__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +-#define MT8173_PIN_95_PCM_TX__FUNC_PCM1_DO (MTK_PIN_NO(95) | 1) +-#define MT8173_PIN_95_PCM_TX__FUNC_I2S0_DO (MTK_PIN_NO(95) | 2) +-#define MT8173_PIN_95_PCM_TX__FUNC_DBG_MON_A_27_ (MTK_PIN_NO(95) | 7) +- +-#define MT8173_PIN_96_URXD1__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +-#define MT8173_PIN_96_URXD1__FUNC_URXD1 (MTK_PIN_NO(96) | 1) +-#define MT8173_PIN_96_URXD1__FUNC_UTXD1 (MTK_PIN_NO(96) | 2) +-#define MT8173_PIN_96_URXD1__FUNC_DBG_MON_A_28_ (MTK_PIN_NO(96) | 7) +- +-#define MT8173_PIN_97_UTXD1__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +-#define MT8173_PIN_97_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(97) | 1) +-#define MT8173_PIN_97_UTXD1__FUNC_URXD1 (MTK_PIN_NO(97) | 2) +-#define MT8173_PIN_97_UTXD1__FUNC_DBG_MON_A_29_ (MTK_PIN_NO(97) | 7) +- +-#define MT8173_PIN_98_URTS1__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +-#define MT8173_PIN_98_URTS1__FUNC_URTS1 (MTK_PIN_NO(98) | 1) +-#define MT8173_PIN_98_URTS1__FUNC_UCTS1 (MTK_PIN_NO(98) | 2) +-#define MT8173_PIN_98_URTS1__FUNC_DBG_MON_A_30_ (MTK_PIN_NO(98) | 7) +- +-#define MT8173_PIN_99_UCTS1__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +-#define MT8173_PIN_99_UCTS1__FUNC_UCTS1 (MTK_PIN_NO(99) | 1) +-#define MT8173_PIN_99_UCTS1__FUNC_URTS1 (MTK_PIN_NO(99) | 2) +-#define MT8173_PIN_99_UCTS1__FUNC_DBG_MON_A_31_ (MTK_PIN_NO(99) | 7) +- +-#define MT8173_PIN_100_MSDC2_DAT0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +-#define MT8173_PIN_100_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(100) | 1) +-#define MT8173_PIN_100_MSDC2_DAT0__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(100) | 3) +-#define MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5 (MTK_PIN_NO(100) | 4) +-#define MT8173_PIN_100_MSDC2_DAT0__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(100) | 5) +-#define MT8173_PIN_100_MSDC2_DAT0__FUNC_DBG_MON_B_0_ (MTK_PIN_NO(100) | 7) +- +-#define MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +-#define MT8173_PIN_101_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(101) | 1) +-#define MT8173_PIN_101_MSDC2_DAT1__FUNC_AUD_SPDIF (MTK_PIN_NO(101) | 3) +-#define MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5 (MTK_PIN_NO(101) | 4) +-#define MT8173_PIN_101_MSDC2_DAT1__FUNC_DBG_MON_B_1_ (MTK_PIN_NO(101) | 7) +- +-#define MT8173_PIN_102_MSDC2_DAT2__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +-#define MT8173_PIN_102_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(102) | 1) +-#define MT8173_PIN_102_MSDC2_DAT2__FUNC_UTXD0 (MTK_PIN_NO(102) | 3) +-#define MT8173_PIN_102_MSDC2_DAT2__FUNC_PWM0 (MTK_PIN_NO(102) | 5) +-#define MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_ (MTK_PIN_NO(102) | 6) +-#define MT8173_PIN_102_MSDC2_DAT2__FUNC_DBG_MON_B_2_ (MTK_PIN_NO(102) | 7) +- +-#define MT8173_PIN_103_MSDC2_DAT3__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +-#define MT8173_PIN_103_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(103) | 1) +-#define MT8173_PIN_103_MSDC2_DAT3__FUNC_URXD0 (MTK_PIN_NO(103) | 3) +-#define MT8173_PIN_103_MSDC2_DAT3__FUNC_PWM1 (MTK_PIN_NO(103) | 5) +-#define MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_ (MTK_PIN_NO(103) | 6) +-#define MT8173_PIN_103_MSDC2_DAT3__FUNC_DBG_MON_B_3_ (MTK_PIN_NO(103) | 7) +- +-#define MT8173_PIN_104_MSDC2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +-#define MT8173_PIN_104_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(104) | 1) +-#define MT8173_PIN_104_MSDC2_CLK__FUNC_UTXD3 (MTK_PIN_NO(104) | 3) +-#define MT8173_PIN_104_MSDC2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 4) +-#define MT8173_PIN_104_MSDC2_CLK__FUNC_PWM2 (MTK_PIN_NO(104) | 5) +-#define MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_ (MTK_PIN_NO(104) | 6) +-#define MT8173_PIN_104_MSDC2_CLK__FUNC_DBG_MON_B_4_ (MTK_PIN_NO(104) | 7) +- +-#define MT8173_PIN_105_MSDC2_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +-#define MT8173_PIN_105_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(105) | 1) +-#define MT8173_PIN_105_MSDC2_CMD__FUNC_URXD3 (MTK_PIN_NO(105) | 3) +-#define MT8173_PIN_105_MSDC2_CMD__FUNC_SCL3 (MTK_PIN_NO(105) | 4) +-#define MT8173_PIN_105_MSDC2_CMD__FUNC_PWM3 (MTK_PIN_NO(105) | 5) +-#define MT8173_PIN_105_MSDC2_CMD__FUNC_SPI_CS_1_ (MTK_PIN_NO(105) | 6) +-#define MT8173_PIN_105_MSDC2_CMD__FUNC_DBG_MON_B_5_ (MTK_PIN_NO(105) | 7) +- +-#define MT8173_PIN_106_SDA3__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +-#define MT8173_PIN_106_SDA3__FUNC_SDA3 (MTK_PIN_NO(106) | 1) +- +-#define MT8173_PIN_107_SCL3__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +-#define MT8173_PIN_107_SCL3__FUNC_SCL3 (MTK_PIN_NO(107) | 1) +- +-#define MT8173_PIN_108_JTMS__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +-#define MT8173_PIN_108_JTMS__FUNC_JTMS (MTK_PIN_NO(108) | 1) +-#define MT8173_PIN_108_JTMS__FUNC_MFG_JTAG_TMS (MTK_PIN_NO(108) | 2) +-#define MT8173_PIN_108_JTMS__FUNC_AP_MD32_JTAG_TMS (MTK_PIN_NO(108) | 5) +-#define MT8173_PIN_108_JTMS__FUNC_DFD_TMS (MTK_PIN_NO(108) | 6) +- +-#define MT8173_PIN_109_JTCK__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +-#define MT8173_PIN_109_JTCK__FUNC_JTCK (MTK_PIN_NO(109) | 1) +-#define MT8173_PIN_109_JTCK__FUNC_MFG_JTAG_TCK (MTK_PIN_NO(109) | 2) +-#define MT8173_PIN_109_JTCK__FUNC_AP_MD32_JTAG_TCK (MTK_PIN_NO(109) | 5) +-#define MT8173_PIN_109_JTCK__FUNC_DFD_TCK (MTK_PIN_NO(109) | 6) +- +-#define MT8173_PIN_110_JTDI__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +-#define MT8173_PIN_110_JTDI__FUNC_JTDI (MTK_PIN_NO(110) | 1) +-#define MT8173_PIN_110_JTDI__FUNC_MFG_JTAG_TDI (MTK_PIN_NO(110) | 2) +-#define MT8173_PIN_110_JTDI__FUNC_AP_MD32_JTAG_TDI (MTK_PIN_NO(110) | 5) +-#define MT8173_PIN_110_JTDI__FUNC_DFD_TDI (MTK_PIN_NO(110) | 6) +- +-#define MT8173_PIN_111_JTDO__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +-#define MT8173_PIN_111_JTDO__FUNC_JTDO (MTK_PIN_NO(111) | 1) +-#define MT8173_PIN_111_JTDO__FUNC_MFG_JTAG_TDO (MTK_PIN_NO(111) | 2) +-#define MT8173_PIN_111_JTDO__FUNC_AP_MD32_JTAG_TDO (MTK_PIN_NO(111) | 5) +-#define MT8173_PIN_111_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(111) | 6) +- +-#define MT8173_PIN_112_JTRST_B__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +-#define MT8173_PIN_112_JTRST_B__FUNC_JTRST_B (MTK_PIN_NO(112) | 1) +-#define MT8173_PIN_112_JTRST_B__FUNC_MFG_JTAG_TRSTN (MTK_PIN_NO(112) | 2) +-#define MT8173_PIN_112_JTRST_B__FUNC_AP_MD32_JTAG_TRST (MTK_PIN_NO(112) | 5) +-#define MT8173_PIN_112_JTRST_B__FUNC_DFD_NTRST (MTK_PIN_NO(112) | 6) +- +-#define MT8173_PIN_113_URXD0__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +-#define MT8173_PIN_113_URXD0__FUNC_URXD0 (MTK_PIN_NO(113) | 1) +-#define MT8173_PIN_113_URXD0__FUNC_UTXD0 (MTK_PIN_NO(113) | 2) +-#define MT8173_PIN_113_URXD0__FUNC_I2S2_WS (MTK_PIN_NO(113) | 6) +-#define MT8173_PIN_113_URXD0__FUNC_DBG_MON_A_0_ (MTK_PIN_NO(113) | 7) +- +-#define MT8173_PIN_114_UTXD0__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +-#define MT8173_PIN_114_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(114) | 1) +-#define MT8173_PIN_114_UTXD0__FUNC_URXD0 (MTK_PIN_NO(114) | 2) +-#define MT8173_PIN_114_UTXD0__FUNC_I2S2_BCK (MTK_PIN_NO(114) | 6) +-#define MT8173_PIN_114_UTXD0__FUNC_DBG_MON_A_1_ (MTK_PIN_NO(114) | 7) +- +-#define MT8173_PIN_115_URTS0__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +-#define MT8173_PIN_115_URTS0__FUNC_URTS0 (MTK_PIN_NO(115) | 1) +-#define MT8173_PIN_115_URTS0__FUNC_UCTS0 (MTK_PIN_NO(115) | 2) +-#define MT8173_PIN_115_URTS0__FUNC_I2S2_MCK (MTK_PIN_NO(115) | 6) +-#define MT8173_PIN_115_URTS0__FUNC_DBG_MON_A_2_ (MTK_PIN_NO(115) | 7) +- +-#define MT8173_PIN_116_UCTS0__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +-#define MT8173_PIN_116_UCTS0__FUNC_UCTS0 (MTK_PIN_NO(116) | 1) +-#define MT8173_PIN_116_UCTS0__FUNC_URTS0 (MTK_PIN_NO(116) | 2) +-#define MT8173_PIN_116_UCTS0__FUNC_I2S2_DI_1 (MTK_PIN_NO(116) | 6) +-#define MT8173_PIN_116_UCTS0__FUNC_DBG_MON_A_3_ (MTK_PIN_NO(116) | 7) +- +-#define MT8173_PIN_117_URXD3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +-#define MT8173_PIN_117_URXD3__FUNC_URXD3 (MTK_PIN_NO(117) | 1) +-#define MT8173_PIN_117_URXD3__FUNC_UTXD3 (MTK_PIN_NO(117) | 2) +-#define MT8173_PIN_117_URXD3__FUNC_DBG_MON_A_9_ (MTK_PIN_NO(117) | 7) +- +-#define MT8173_PIN_118_UTXD3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +-#define MT8173_PIN_118_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(118) | 1) +-#define MT8173_PIN_118_UTXD3__FUNC_URXD3 (MTK_PIN_NO(118) | 2) +-#define MT8173_PIN_118_UTXD3__FUNC_DBG_MON_A_10_ (MTK_PIN_NO(118) | 7) +- +-#define MT8173_PIN_119_KPROW0__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +-#define MT8173_PIN_119_KPROW0__FUNC_KROW0 (MTK_PIN_NO(119) | 1) +-#define MT8173_PIN_119_KPROW0__FUNC_DBG_MON_A_11_ (MTK_PIN_NO(119) | 7) +- +-#define MT8173_PIN_120_KPROW1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +-#define MT8173_PIN_120_KPROW1__FUNC_KROW1 (MTK_PIN_NO(120) | 1) +-#define MT8173_PIN_120_KPROW1__FUNC_PWM6 (MTK_PIN_NO(120) | 3) +-#define MT8173_PIN_120_KPROW1__FUNC_DBG_MON_A_12_ (MTK_PIN_NO(120) | 7) +- +-#define MT8173_PIN_121_KPROW2__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +-#define MT8173_PIN_121_KPROW2__FUNC_KROW2 (MTK_PIN_NO(121) | 1) +-#define MT8173_PIN_121_KPROW2__FUNC_IRDA_PDN (MTK_PIN_NO(121) | 2) +-#define MT8173_PIN_121_KPROW2__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(121) | 3) +-#define MT8173_PIN_121_KPROW2__FUNC_PWM4 (MTK_PIN_NO(121) | 4) +-#define MT8173_PIN_121_KPROW2__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(121) | 5) +-#define MT8173_PIN_121_KPROW2__FUNC_DBG_MON_A_13_ (MTK_PIN_NO(121) | 7) +- +-#define MT8173_PIN_122_KPCOL0__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +-#define MT8173_PIN_122_KPCOL0__FUNC_KCOL0 (MTK_PIN_NO(122) | 1) +-#define MT8173_PIN_122_KPCOL0__FUNC_DBG_MON_A_14_ (MTK_PIN_NO(122) | 7) +- +-#define MT8173_PIN_123_KPCOL1__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +-#define MT8173_PIN_123_KPCOL1__FUNC_KCOL1 (MTK_PIN_NO(123) | 1) +-#define MT8173_PIN_123_KPCOL1__FUNC_IRDA_RXD (MTK_PIN_NO(123) | 2) +-#define MT8173_PIN_123_KPCOL1__FUNC_PWM5 (MTK_PIN_NO(123) | 3) +-#define MT8173_PIN_123_KPCOL1__FUNC_DBG_MON_A_15_ (MTK_PIN_NO(123) | 7) +- +-#define MT8173_PIN_124_KPCOL2__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +-#define MT8173_PIN_124_KPCOL2__FUNC_KCOL2 (MTK_PIN_NO(124) | 1) +-#define MT8173_PIN_124_KPCOL2__FUNC_IRDA_TXD (MTK_PIN_NO(124) | 2) +-#define MT8173_PIN_124_KPCOL2__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(124) | 3) +-#define MT8173_PIN_124_KPCOL2__FUNC_PWM3 (MTK_PIN_NO(124) | 4) +-#define MT8173_PIN_124_KPCOL2__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(124) | 5) +-#define MT8173_PIN_124_KPCOL2__FUNC_DBG_MON_A_16_ (MTK_PIN_NO(124) | 7) +- +-#define MT8173_PIN_125_SDA1__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +-#define MT8173_PIN_125_SDA1__FUNC_SDA1 (MTK_PIN_NO(125) | 1) +- +-#define MT8173_PIN_126_SCL1__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +-#define MT8173_PIN_126_SCL1__FUNC_SCL1 (MTK_PIN_NO(126) | 1) +- +-#define MT8173_PIN_127_LCM_RST__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +-#define MT8173_PIN_127_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(127) | 1) +- +-#define MT8173_PIN_128_I2S0_LRCK__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +-#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S0_WS (MTK_PIN_NO(128) | 1) +-#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS (MTK_PIN_NO(128) | 2) +-#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S2_WS (MTK_PIN_NO(128) | 3) +-#define MT8173_PIN_128_I2S0_LRCK__FUNC_SPI_CK_2_ (MTK_PIN_NO(128) | 5) +-#define MT8173_PIN_128_I2S0_LRCK__FUNC_DBG_MON_A_4_ (MTK_PIN_NO(128) | 7) +- +-#define MT8173_PIN_129_I2S0_BCK__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +-#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(129) | 1) +-#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(129) | 2) +-#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S2_BCK (MTK_PIN_NO(129) | 3) +-#define MT8173_PIN_129_I2S0_BCK__FUNC_SPI_MI_2_ (MTK_PIN_NO(129) | 5) +-#define MT8173_PIN_129_I2S0_BCK__FUNC_DBG_MON_A_5_ (MTK_PIN_NO(129) | 7) +- +-#define MT8173_PIN_130_I2S0_MCK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +-#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S0_MCK (MTK_PIN_NO(130) | 1) +-#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK (MTK_PIN_NO(130) | 2) +-#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S2_MCK (MTK_PIN_NO(130) | 3) +-#define MT8173_PIN_130_I2S0_MCK__FUNC_SPI_MO_2_ (MTK_PIN_NO(130) | 5) +-#define MT8173_PIN_130_I2S0_MCK__FUNC_DBG_MON_A_6_ (MTK_PIN_NO(130) | 7) +- +-#define MT8173_PIN_131_I2S0_DATA0__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +-#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S0_DO (MTK_PIN_NO(131) | 1) +-#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S1_DO_1 (MTK_PIN_NO(131) | 2) +-#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S2_DI_1 (MTK_PIN_NO(131) | 3) +-#define MT8173_PIN_131_I2S0_DATA0__FUNC_SPI_CS_2_ (MTK_PIN_NO(131) | 5) +-#define MT8173_PIN_131_I2S0_DATA0__FUNC_DBG_MON_A_7_ (MTK_PIN_NO(131) | 7) +- +-#define MT8173_PIN_132_I2S0_DATA1__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +-#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S0_DI (MTK_PIN_NO(132) | 1) +-#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S1_DO_2 (MTK_PIN_NO(132) | 2) +-#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S2_DI_2 (MTK_PIN_NO(132) | 3) +-#define MT8173_PIN_132_I2S0_DATA1__FUNC_DBG_MON_A_8_ (MTK_PIN_NO(132) | 7) +- +-#define MT8173_PIN_133_SDA4__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +-#define MT8173_PIN_133_SDA4__FUNC_SDA4 (MTK_PIN_NO(133) | 1) +- +-#define MT8173_PIN_134_SCL4__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +-#define MT8173_PIN_134_SCL4__FUNC_SCL4 (MTK_PIN_NO(134) | 1) +- +-#endif /* __DTS_MT8173_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8173.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt8173.dtsi +deleted file mode 100644 +index d9e005ae5bb0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8173.dtsi ++++ /dev/null +@@ -1,1537 +0,0 @@ +-/* +- * Copyright (c) 2014 MediaTek Inc. +- * Author: Eddie Huang +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License version 2 as +- * published by the Free Software Foundation. +- * +- * This program is distributed in the hope that it will be useful, +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include "mt8173-pinfunc.h" +- +-/ { +- compatible = "mediatek,mt8173"; +- interrupt-parent = <&sysirq>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- ovl0 = &ovl0; +- ovl1 = &ovl1; +- rdma0 = &rdma0; +- rdma1 = &rdma1; +- rdma2 = &rdma2; +- wdma0 = &wdma0; +- wdma1 = &wdma1; +- color0 = &color0; +- color1 = &color1; +- split0 = &split0; +- split1 = &split1; +- dpi0 = &dpi0; +- dsi0 = &dsi0; +- dsi1 = &dsi1; +- mdp-rdma0 = &mdp_rdma0; +- mdp-rdma1 = &mdp_rdma1; +- mdp-rsz0 = &mdp_rsz0; +- mdp-rsz1 = &mdp_rsz1; +- mdp-rsz2 = &mdp_rsz2; +- mdp-wdma0 = &mdp_wdma0; +- mdp-wrot0 = &mdp_wrot0; +- mdp-wrot1 = &mdp_wrot1; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- }; +- +- cluster0_opp: opp_table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- opp-507000000 { +- opp-hz = /bits/ 64 <507000000>; +- opp-microvolt = <859000>; +- }; +- opp-702000000 { +- opp-hz = /bits/ 64 <702000000>; +- opp-microvolt = <908000>; +- }; +- opp-1001000000 { +- opp-hz = /bits/ 64 <1001000000>; +- opp-microvolt = <983000>; +- }; +- opp-1105000000 { +- opp-hz = /bits/ 64 <1105000000>; +- opp-microvolt = <1009000>; +- }; +- opp-1209000000 { +- opp-hz = /bits/ 64 <1209000000>; +- opp-microvolt = <1034000>; +- }; +- opp-1300000000 { +- opp-hz = /bits/ 64 <1300000000>; +- opp-microvolt = <1057000>; +- }; +- opp-1508000000 { +- opp-hz = /bits/ 64 <1508000000>; +- opp-microvolt = <1109000>; +- }; +- opp-1703000000 { +- opp-hz = /bits/ 64 <1703000000>; +- opp-microvolt = <1125000>; +- }; +- }; +- +- cluster1_opp: opp_table1 { +- compatible = "operating-points-v2"; +- opp-shared; +- opp-507000000 { +- opp-hz = /bits/ 64 <507000000>; +- opp-microvolt = <828000>; +- }; +- opp-702000000 { +- opp-hz = /bits/ 64 <702000000>; +- opp-microvolt = <867000>; +- }; +- opp-1001000000 { +- opp-hz = /bits/ 64 <1001000000>; +- opp-microvolt = <927000>; +- }; +- opp-1209000000 { +- opp-hz = /bits/ 64 <1209000000>; +- opp-microvolt = <968000>; +- }; +- opp-1404000000 { +- opp-hz = /bits/ 64 <1404000000>; +- opp-microvolt = <1007000>; +- }; +- opp-1612000000 { +- opp-hz = /bits/ 64 <1612000000>; +- opp-microvolt = <1049000>; +- }; +- opp-1807000000 { +- opp-hz = /bits/ 64 <1807000000>; +- opp-microvolt = <1089000>; +- }; +- opp-2106000000 { +- opp-hz = /bits/ 64 <2106000000>; +- opp-microvolt = <1125000>; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&cpu2>; +- }; +- core1 { +- cpu = <&cpu3>; +- }; +- }; +- }; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x000>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- #cooling-cells = <2>; +- dynamic-power-coefficient = <263>; +- clocks = <&infracfg CLK_INFRA_CA53SEL>, +- <&apmixedsys CLK_APMIXED_MAINPLL>; +- clock-names = "cpu", "intermediate"; +- operating-points-v2 = <&cluster0_opp>; +- capacity-dmips-mhz = <740>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x001>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- #cooling-cells = <2>; +- dynamic-power-coefficient = <263>; +- clocks = <&infracfg CLK_INFRA_CA53SEL>, +- <&apmixedsys CLK_APMIXED_MAINPLL>; +- clock-names = "cpu", "intermediate"; +- operating-points-v2 = <&cluster0_opp>; +- capacity-dmips-mhz = <740>; +- }; +- +- cpu2: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x100>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- #cooling-cells = <2>; +- dynamic-power-coefficient = <530>; +- clocks = <&infracfg CLK_INFRA_CA72SEL>, +- <&apmixedsys CLK_APMIXED_MAINPLL>; +- clock-names = "cpu", "intermediate"; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <1024>; +- }; +- +- cpu3: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x101>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- #cooling-cells = <2>; +- dynamic-power-coefficient = <530>; +- clocks = <&infracfg CLK_INFRA_CA72SEL>, +- <&apmixedsys CLK_APMIXED_MAINPLL>; +- clock-names = "cpu", "intermediate"; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <1024>; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP_0: cpu-sleep-0 { +- compatible = "arm,idle-state"; +- local-timer-stop; +- entry-latency-us = <639>; +- exit-latency-us = <680>; +- min-residency-us = <1088>; +- arm,psci-suspend-param = <0x0010000>; +- }; +- }; +- }; +- +- pmu_a53 { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- pmu_a72 { +- compatible = "arm,cortex-a72-pmu"; +- interrupts = , +- ; +- interrupt-affinity = <&cpu2>, <&cpu3>; +- }; +- +- psci { +- compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; +- method = "smc"; +- cpu_suspend = <0x84000001>; +- cpu_off = <0x84000002>; +- cpu_on = <0x84000003>; +- }; +- +- clk26m: oscillator0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- clock-output-names = "clk26m"; +- }; +- +- clk32k: oscillator1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32000>; +- clock-output-names = "clk32k"; +- }; +- +- cpum_ck: oscillator2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- clock-output-names = "cpum_ck"; +- }; +- +- thermal-zones { +- cpu_thermal: cpu_thermal { +- polling-delay-passive = <1000>; /* milliseconds */ +- polling-delay = <1000>; /* milliseconds */ +- +- thermal-sensors = <&thermal>; +- sustainable-power = <1500>; /* milliwatts */ +- +- trips { +- threshold: trip-point0 { +- temperature = <68000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- target: trip-point1 { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_crit: cpu_crit0 { +- temperature = <115000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&target>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>; +- contribution = <3072>; +- }; +- map1 { +- trip = <&target>; +- cooling-device = <&cpu2 THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>; +- contribution = <1024>; +- }; +- }; +- }; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- vpu_dma_reserved: vpu_dma_mem_region@b7000000 { +- compatible = "shared-dma-pool"; +- reg = <0 0xb7000000 0 0x500000>; +- alignment = <0x1000>; +- no-map; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- arm,no-tick-in-suspend; +- }; +- +- soc { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "simple-bus"; +- ranges; +- +- topckgen: clock-controller@10000000 { +- compatible = "mediatek,mt8173-topckgen"; +- reg = <0 0x10000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- infracfg: power-controller@10001000 { +- compatible = "mediatek,mt8173-infracfg", "syscon"; +- reg = <0 0x10001000 0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pericfg: power-controller@10003000 { +- compatible = "mediatek,mt8173-pericfg", "syscon"; +- reg = <0 0x10003000 0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- syscfg_pctl_a: syscfg_pctl_a@10005000 { +- compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; +- reg = <0 0x10005000 0 0x1000>; +- }; +- +- pio: pinctrl@1000b000 { +- compatible = "mediatek,mt8173-pinctrl"; +- reg = <0 0x1000b000 0 0x1000>; +- mediatek,pctl-regmap = <&syscfg_pctl_a>; +- pins-are-numbered; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = , +- , +- ; +- +- hdmi_pin: xxx { +- +- /*hdmi htplg pin*/ +- pins1 { +- pinmux = ; +- input-enable; +- bias-pull-down; +- }; +- }; +- +- i2c0_pins_a: i2c0 { +- pins1 { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- i2c1_pins_a: i2c1 { +- pins1 { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- i2c2_pins_a: i2c2 { +- pins1 { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- i2c3_pins_a: i2c3 { +- pins1 { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- i2c4_pins_a: i2c4 { +- pins1 { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- i2c6_pins_a: i2c6 { +- pins1 { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- }; +- +- scpsys: syscon@10006000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0 0x10006000 0 0x1000>; +- #power-domain-cells = <1>; +- +- /* System Power Manager */ +- spm: power-controller { +- compatible = "mediatek,mt8173-power-controller"; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <1>; +- +- /* power domains of the SoC */ +- power-domain@MT8173_POWER_DOMAIN_VDEC { +- reg = ; +- clocks = <&topckgen CLK_TOP_MM_SEL>; +- clock-names = "mm"; +- #power-domain-cells = <0>; +- }; +- power-domain@MT8173_POWER_DOMAIN_VENC { +- reg = ; +- clocks = <&topckgen CLK_TOP_MM_SEL>, +- <&topckgen CLK_TOP_VENC_SEL>; +- clock-names = "mm", "venc"; +- #power-domain-cells = <0>; +- }; +- power-domain@MT8173_POWER_DOMAIN_ISP { +- reg = ; +- clocks = <&topckgen CLK_TOP_MM_SEL>; +- clock-names = "mm"; +- #power-domain-cells = <0>; +- }; +- power-domain@MT8173_POWER_DOMAIN_MM { +- reg = ; +- clocks = <&topckgen CLK_TOP_MM_SEL>; +- clock-names = "mm"; +- #power-domain-cells = <0>; +- mediatek,infracfg = <&infracfg>; +- }; +- power-domain@MT8173_POWER_DOMAIN_VENC_LT { +- reg = ; +- clocks = <&topckgen CLK_TOP_MM_SEL>, +- <&topckgen CLK_TOP_VENC_LT_SEL>; +- clock-names = "mm", "venclt"; +- #power-domain-cells = <0>; +- }; +- power-domain@MT8173_POWER_DOMAIN_AUDIO { +- reg = ; +- #power-domain-cells = <0>; +- }; +- power-domain@MT8173_POWER_DOMAIN_USB { +- reg = ; +- #power-domain-cells = <0>; +- }; +- mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { +- reg = ; +- clocks = <&clk26m>; +- clock-names = "mfg"; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <1>; +- +- power-domain@MT8173_POWER_DOMAIN_MFG_2D { +- reg = ; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <1>; +- +- power-domain@MT8173_POWER_DOMAIN_MFG { +- reg = ; +- #power-domain-cells = <0>; +- mediatek,infracfg = <&infracfg>; +- }; +- }; +- }; +- }; +- }; +- +- watchdog: watchdog@10007000 { +- compatible = "mediatek,mt8173-wdt", +- "mediatek,mt6589-wdt"; +- reg = <0 0x10007000 0 0x100>; +- }; +- +- timer: timer@10008000 { +- compatible = "mediatek,mt8173-timer", +- "mediatek,mt6577-timer"; +- reg = <0 0x10008000 0 0x1000>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_CLK_13M>, +- <&topckgen CLK_TOP_RTC_SEL>; +- }; +- +- pwrap: pwrap@1000d000 { +- compatible = "mediatek,mt8173-pwrap"; +- reg = <0 0x1000d000 0 0x1000>; +- reg-names = "pwrap"; +- interrupts = ; +- resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; +- reset-names = "pwrap"; +- clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; +- clock-names = "spi", "wrap"; +- }; +- +- cec: cec@10013000 { +- compatible = "mediatek,mt8173-cec"; +- reg = <0 0x10013000 0 0xbc>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_CEC>; +- status = "disabled"; +- }; +- +- vpu: vpu@10020000 { +- compatible = "mediatek,mt8173-vpu"; +- reg = <0 0x10020000 0 0x30000>, +- <0 0x10050000 0 0x100>; +- reg-names = "tcm", "cfg_reg"; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_SCP_SEL>; +- clock-names = "main"; +- memory-region = <&vpu_dma_reserved>; +- }; +- +- sysirq: intpol-controller@10200620 { +- compatible = "mediatek,mt8173-sysirq", +- "mediatek,mt6577-sysirq"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0 0x10200620 0 0x20>; +- }; +- +- iommu: iommu@10205000 { +- compatible = "mediatek,mt8173-m4u"; +- reg = <0 0x10205000 0 0x1000>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_M4U>; +- clock-names = "bclk"; +- mediatek,larbs = <&larb0 &larb1 &larb2 +- &larb3 &larb4 &larb5>; +- #iommu-cells = <1>; +- }; +- +- efuse: efuse@10206000 { +- compatible = "mediatek,mt8173-efuse"; +- reg = <0 0x10206000 0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- thermal_calibration: calib@528 { +- reg = <0x528 0xc>; +- }; +- }; +- +- apmixedsys: clock-controller@10209000 { +- compatible = "mediatek,mt8173-apmixedsys"; +- reg = <0 0x10209000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- hdmi_phy: hdmi-phy@10209100 { +- compatible = "mediatek,mt8173-hdmi-phy"; +- reg = <0 0x10209100 0 0x24>; +- clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; +- clock-names = "pll_ref"; +- clock-output-names = "hdmitx_dig_cts"; +- mediatek,ibias = <0xa>; +- mediatek,ibias_up = <0x1c>; +- #clock-cells = <0>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- gce: mailbox@10212000 { +- compatible = "mediatek,mt8173-gce"; +- reg = <0 0x10212000 0 0x1000>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_GCE>; +- clock-names = "gce"; +- #mbox-cells = <2>; +- }; +- +- mipi_tx0: dsi-phy@10215000 { +- compatible = "mediatek,mt8173-mipi-tx"; +- reg = <0 0x10215000 0 0x1000>; +- clocks = <&clk26m>; +- clock-output-names = "mipi_tx0_pll"; +- #clock-cells = <0>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- mipi_tx1: dsi-phy@10216000 { +- compatible = "mediatek,mt8173-mipi-tx"; +- reg = <0 0x10216000 0 0x1000>; +- clocks = <&clk26m>; +- clock-output-names = "mipi_tx1_pll"; +- #clock-cells = <0>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@10221000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- interrupt-controller; +- reg = <0 0x10221000 0 0x1000>, +- <0 0x10222000 0 0x2000>, +- <0 0x10224000 0 0x2000>, +- <0 0x10226000 0 0x2000>; +- interrupts = ; +- }; +- +- auxadc: auxadc@11001000 { +- compatible = "mediatek,mt8173-auxadc"; +- reg = <0 0x11001000 0 0x1000>; +- clocks = <&pericfg CLK_PERI_AUXADC>; +- clock-names = "main"; +- #io-channel-cells = <1>; +- }; +- +- uart0: serial@11002000 { +- compatible = "mediatek,mt8173-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11002000 0 0x400>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart1: serial@11003000 { +- compatible = "mediatek,mt8173-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11003000 0 0x400>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart2: serial@11004000 { +- compatible = "mediatek,mt8173-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11004000 0 0x400>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart3: serial@11005000 { +- compatible = "mediatek,mt8173-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11005000 0 0x400>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- i2c0: i2c@11007000 { +- compatible = "mediatek,mt8173-i2c"; +- reg = <0 0x11007000 0 0x70>, +- <0 0x11000100 0 0x80>; +- interrupts = ; +- clock-div = <16>; +- clocks = <&pericfg CLK_PERI_I2C0>, +- <&pericfg CLK_PERI_AP_DMA>; +- clock-names = "main", "dma"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_a>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@11008000 { +- compatible = "mediatek,mt8173-i2c"; +- reg = <0 0x11008000 0 0x70>, +- <0 0x11000180 0 0x80>; +- interrupts = ; +- clock-div = <16>; +- clocks = <&pericfg CLK_PERI_I2C1>, +- <&pericfg CLK_PERI_AP_DMA>; +- clock-names = "main", "dma"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins_a>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@11009000 { +- compatible = "mediatek,mt8173-i2c"; +- reg = <0 0x11009000 0 0x70>, +- <0 0x11000200 0 0x80>; +- interrupts = ; +- clock-div = <16>; +- clocks = <&pericfg CLK_PERI_I2C2>, +- <&pericfg CLK_PERI_AP_DMA>; +- clock-names = "main", "dma"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins_a>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi: spi@1100a000 { +- compatible = "mediatek,mt8173-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x1100a000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, +- <&topckgen CLK_TOP_SPI_SEL>, +- <&pericfg CLK_PERI_SPI0>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- thermal: thermal@1100b000 { +- #thermal-sensor-cells = <0>; +- compatible = "mediatek,mt8173-thermal"; +- reg = <0 0x1100b000 0 0x1000>; +- interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; +- clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; +- clock-names = "therm", "auxadc"; +- resets = <&pericfg MT8173_PERI_THERM_SW_RST>; +- mediatek,auxadc = <&auxadc>; +- mediatek,apmixedsys = <&apmixedsys>; +- nvmem-cells = <&thermal_calibration>; +- nvmem-cell-names = "calibration-data"; +- }; +- +- nor_flash: spi@1100d000 { +- compatible = "mediatek,mt8173-nor"; +- reg = <0 0x1100d000 0 0xe0>; +- clocks = <&pericfg CLK_PERI_SPI>, +- <&topckgen CLK_TOP_SPINFI_IFR_SEL>; +- clock-names = "spi", "sf"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@11010000 { +- compatible = "mediatek,mt8173-i2c"; +- reg = <0 0x11010000 0 0x70>, +- <0 0x11000280 0 0x80>; +- interrupts = ; +- clock-div = <16>; +- clocks = <&pericfg CLK_PERI_I2C3>, +- <&pericfg CLK_PERI_AP_DMA>; +- clock-names = "main", "dma"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins_a>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@11011000 { +- compatible = "mediatek,mt8173-i2c"; +- reg = <0 0x11011000 0 0x70>, +- <0 0x11000300 0 0x80>; +- interrupts = ; +- clock-div = <16>; +- clocks = <&pericfg CLK_PERI_I2C4>, +- <&pericfg CLK_PERI_AP_DMA>; +- clock-names = "main", "dma"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pins_a>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- hdmiddc0: i2c@11012000 { +- compatible = "mediatek,mt8173-hdmi-ddc"; +- interrupts = ; +- reg = <0 0x11012000 0 0x1C>; +- clocks = <&pericfg CLK_PERI_I2C5>; +- clock-names = "ddc-i2c"; +- }; +- +- i2c6: i2c@11013000 { +- compatible = "mediatek,mt8173-i2c"; +- reg = <0 0x11013000 0 0x70>, +- <0 0x11000080 0 0x80>; +- interrupts = ; +- clock-div = <16>; +- clocks = <&pericfg CLK_PERI_I2C6>, +- <&pericfg CLK_PERI_AP_DMA>; +- clock-names = "main", "dma"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c6_pins_a>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- afe: audio-controller@11220000 { +- compatible = "mediatek,mt8173-afe-pcm"; +- reg = <0 0x11220000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>; +- clocks = <&infracfg CLK_INFRA_AUDIO>, +- <&topckgen CLK_TOP_AUDIO_SEL>, +- <&topckgen CLK_TOP_AUD_INTBUS_SEL>, +- <&topckgen CLK_TOP_APLL1_DIV0>, +- <&topckgen CLK_TOP_APLL2_DIV0>, +- <&topckgen CLK_TOP_I2S0_M_SEL>, +- <&topckgen CLK_TOP_I2S1_M_SEL>, +- <&topckgen CLK_TOP_I2S2_M_SEL>, +- <&topckgen CLK_TOP_I2S3_M_SEL>, +- <&topckgen CLK_TOP_I2S3_B_SEL>; +- clock-names = "infra_sys_audio_clk", +- "top_pdn_audio", +- "top_pdn_aud_intbus", +- "bck0", +- "bck1", +- "i2s0_m", +- "i2s1_m", +- "i2s2_m", +- "i2s3_m", +- "i2s3_b"; +- assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, +- <&topckgen CLK_TOP_AUD_2_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, +- <&topckgen CLK_TOP_APLL2>; +- }; +- +- mmc0: mmc@11230000 { +- compatible = "mediatek,mt8173-mmc"; +- reg = <0 0x11230000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_MSDC30_0>, +- <&topckgen CLK_TOP_MSDC50_0_H_SEL>; +- clock-names = "source", "hclk"; +- status = "disabled"; +- }; +- +- mmc1: mmc@11240000 { +- compatible = "mediatek,mt8173-mmc"; +- reg = <0 0x11240000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_MSDC30_1>, +- <&topckgen CLK_TOP_AXI_SEL>; +- clock-names = "source", "hclk"; +- status = "disabled"; +- }; +- +- mmc2: mmc@11250000 { +- compatible = "mediatek,mt8173-mmc"; +- reg = <0 0x11250000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_MSDC30_2>, +- <&topckgen CLK_TOP_AXI_SEL>; +- clock-names = "source", "hclk"; +- status = "disabled"; +- }; +- +- mmc3: mmc@11260000 { +- compatible = "mediatek,mt8173-mmc"; +- reg = <0 0x11260000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_MSDC30_3>, +- <&topckgen CLK_TOP_MSDC50_2_H_SEL>; +- clock-names = "source", "hclk"; +- status = "disabled"; +- }; +- +- ssusb: usb@11271000 { +- compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; +- reg = <0 0x11271000 0 0x3000>, +- <0 0x11280700 0 0x0100>; +- reg-names = "mac", "ippc"; +- interrupts = ; +- phys = <&u2port0 PHY_TYPE_USB2>, +- <&u3port0 PHY_TYPE_USB3>, +- <&u2port1 PHY_TYPE_USB2>; +- power-domains = <&spm MT8173_POWER_DOMAIN_USB>; +- clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; +- clock-names = "sys_ck", "ref_ck"; +- mediatek,syscon-wakeup = <&pericfg 0x400 1>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "disabled"; +- +- usb_host: usb@11270000 { +- compatible = "mediatek,mt8173-xhci", +- "mediatek,mtk-xhci"; +- reg = <0 0x11270000 0 0x1000>; +- reg-names = "mac"; +- interrupts = ; +- power-domains = <&spm MT8173_POWER_DOMAIN_USB>; +- clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; +- clock-names = "sys_ck", "ref_ck"; +- status = "disabled"; +- }; +- }; +- +- u3phy: t-phy@11290000 { +- compatible = "mediatek,mt8173-u3phy"; +- reg = <0 0x11290000 0 0x800>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "okay"; +- +- u2port0: usb-phy@11290800 { +- reg = <0 0x11290800 0 0x100>; +- clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- +- u3port0: usb-phy@11290900 { +- reg = <0 0x11290900 0 0x700>; +- clocks = <&clk26m>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- +- u2port1: usb-phy@11291000 { +- reg = <0 0x11291000 0 0x100>; +- clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- }; +- +- mmsys: syscon@14000000 { +- compatible = "mediatek,mt8173-mmsys", "syscon"; +- reg = <0 0x14000000 0 0x1000>; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; +- assigned-clock-rates = <400000000>; +- #clock-cells = <1>; +- mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, +- <&gce 1 CMDQ_THR_PRIO_HIGHEST>; +- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; +- }; +- +- mdp_rdma0: rdma@14001000 { +- compatible = "mediatek,mt8173-mdp-rdma", +- "mediatek,mt8173-mdp"; +- reg = <0 0x14001000 0 0x1000>; +- clocks = <&mmsys CLK_MM_MDP_RDMA0>, +- <&mmsys CLK_MM_MUTEX_32K>; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- iommus = <&iommu M4U_PORT_MDP_RDMA0>; +- mediatek,larb = <&larb0>; +- mediatek,vpu = <&vpu>; +- }; +- +- mdp_rdma1: rdma@14002000 { +- compatible = "mediatek,mt8173-mdp-rdma"; +- reg = <0 0x14002000 0 0x1000>; +- clocks = <&mmsys CLK_MM_MDP_RDMA1>, +- <&mmsys CLK_MM_MUTEX_32K>; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- iommus = <&iommu M4U_PORT_MDP_RDMA1>; +- mediatek,larb = <&larb4>; +- }; +- +- mdp_rsz0: rsz@14003000 { +- compatible = "mediatek,mt8173-mdp-rsz"; +- reg = <0 0x14003000 0 0x1000>; +- clocks = <&mmsys CLK_MM_MDP_RSZ0>; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- }; +- +- mdp_rsz1: rsz@14004000 { +- compatible = "mediatek,mt8173-mdp-rsz"; +- reg = <0 0x14004000 0 0x1000>; +- clocks = <&mmsys CLK_MM_MDP_RSZ1>; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- }; +- +- mdp_rsz2: rsz@14005000 { +- compatible = "mediatek,mt8173-mdp-rsz"; +- reg = <0 0x14005000 0 0x1000>; +- clocks = <&mmsys CLK_MM_MDP_RSZ2>; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- }; +- +- mdp_wdma0: wdma@14006000 { +- compatible = "mediatek,mt8173-mdp-wdma"; +- reg = <0 0x14006000 0 0x1000>; +- clocks = <&mmsys CLK_MM_MDP_WDMA>; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- iommus = <&iommu M4U_PORT_MDP_WDMA>; +- mediatek,larb = <&larb0>; +- }; +- +- mdp_wrot0: wrot@14007000 { +- compatible = "mediatek,mt8173-mdp-wrot"; +- reg = <0 0x14007000 0 0x1000>; +- clocks = <&mmsys CLK_MM_MDP_WROT0>; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- iommus = <&iommu M4U_PORT_MDP_WROT0>; +- mediatek,larb = <&larb0>; +- }; +- +- mdp_wrot1: wrot@14008000 { +- compatible = "mediatek,mt8173-mdp-wrot"; +- reg = <0 0x14008000 0 0x1000>; +- clocks = <&mmsys CLK_MM_MDP_WROT1>; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- iommus = <&iommu M4U_PORT_MDP_WROT1>; +- mediatek,larb = <&larb4>; +- }; +- +- ovl0: ovl@1400c000 { +- compatible = "mediatek,mt8173-disp-ovl"; +- reg = <0 0x1400c000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_DISP_OVL0>; +- iommus = <&iommu M4U_PORT_DISP_OVL0>; +- mediatek,larb = <&larb0>; +- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; +- }; +- +- ovl1: ovl@1400d000 { +- compatible = "mediatek,mt8173-disp-ovl"; +- reg = <0 0x1400d000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_DISP_OVL1>; +- iommus = <&iommu M4U_PORT_DISP_OVL1>; +- mediatek,larb = <&larb4>; +- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; +- }; +- +- rdma0: rdma@1400e000 { +- compatible = "mediatek,mt8173-disp-rdma"; +- reg = <0 0x1400e000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_DISP_RDMA0>; +- iommus = <&iommu M4U_PORT_DISP_RDMA0>; +- mediatek,larb = <&larb0>; +- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; +- }; +- +- rdma1: rdma@1400f000 { +- compatible = "mediatek,mt8173-disp-rdma"; +- reg = <0 0x1400f000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_DISP_RDMA1>; +- iommus = <&iommu M4U_PORT_DISP_RDMA1>; +- mediatek,larb = <&larb4>; +- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; +- }; +- +- rdma2: rdma@14010000 { +- compatible = "mediatek,mt8173-disp-rdma"; +- reg = <0 0x14010000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_DISP_RDMA2>; +- iommus = <&iommu M4U_PORT_DISP_RDMA2>; +- mediatek,larb = <&larb4>; +- mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; +- }; +- +- wdma0: wdma@14011000 { +- compatible = "mediatek,mt8173-disp-wdma"; +- reg = <0 0x14011000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_DISP_WDMA0>; +- iommus = <&iommu M4U_PORT_DISP_WDMA0>; +- mediatek,larb = <&larb0>; +- mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; +- }; +- +- wdma1: wdma@14012000 { +- compatible = "mediatek,mt8173-disp-wdma"; +- reg = <0 0x14012000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_DISP_WDMA1>; +- iommus = <&iommu M4U_PORT_DISP_WDMA1>; +- mediatek,larb = <&larb4>; +- mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; +- }; +- +- color0: color@14013000 { +- compatible = "mediatek,mt8173-disp-color"; +- reg = <0 0x14013000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_DISP_COLOR0>; +- mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; +- }; +- +- color1: color@14014000 { +- compatible = "mediatek,mt8173-disp-color"; +- reg = <0 0x14014000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_DISP_COLOR1>; +- mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; +- }; +- +- aal@14015000 { +- compatible = "mediatek,mt8173-disp-aal"; +- reg = <0 0x14015000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_DISP_AAL>; +- mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; +- }; +- +- gamma@14016000 { +- compatible = "mediatek,mt8173-disp-gamma"; +- reg = <0 0x14016000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_DISP_GAMMA>; +- mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; +- }; +- +- merge@14017000 { +- compatible = "mediatek,mt8173-disp-merge"; +- reg = <0 0x14017000 0 0x1000>; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_DISP_MERGE>; +- }; +- +- split0: split@14018000 { +- compatible = "mediatek,mt8173-disp-split"; +- reg = <0 0x14018000 0 0x1000>; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_DISP_SPLIT0>; +- }; +- +- split1: split@14019000 { +- compatible = "mediatek,mt8173-disp-split"; +- reg = <0 0x14019000 0 0x1000>; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_DISP_SPLIT1>; +- }; +- +- ufoe@1401a000 { +- compatible = "mediatek,mt8173-disp-ufoe"; +- reg = <0 0x1401a000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_DISP_UFOE>; +- }; +- +- dsi0: dsi@1401b000 { +- compatible = "mediatek,mt8173-dsi"; +- reg = <0 0x1401b000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_DSI0_ENGINE>, +- <&mmsys CLK_MM_DSI0_DIGITAL>, +- <&mipi_tx0>; +- clock-names = "engine", "digital", "hs"; +- phys = <&mipi_tx0>; +- phy-names = "dphy"; +- status = "disabled"; +- }; +- +- dsi1: dsi@1401c000 { +- compatible = "mediatek,mt8173-dsi"; +- reg = <0 0x1401c000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_DSI1_ENGINE>, +- <&mmsys CLK_MM_DSI1_DIGITAL>, +- <&mipi_tx1>; +- clock-names = "engine", "digital", "hs"; +- phys = <&mipi_tx1>; +- phy-names = "dphy"; +- status = "disabled"; +- }; +- +- dpi0: dpi@1401d000 { +- compatible = "mediatek,mt8173-dpi"; +- reg = <0 0x1401d000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_DPI_PIXEL>, +- <&mmsys CLK_MM_DPI_ENGINE>, +- <&apmixedsys CLK_APMIXED_TVDPLL>; +- clock-names = "pixel", "engine", "pll"; +- status = "disabled"; +- +- port { +- dpi0_out: endpoint { +- remote-endpoint = <&hdmi0_in>; +- }; +- }; +- }; +- +- pwm0: pwm@1401e000 { +- compatible = "mediatek,mt8173-disp-pwm", +- "mediatek,mt6595-disp-pwm"; +- reg = <0 0x1401e000 0 0x1000>; +- #pwm-cells = <2>; +- clocks = <&mmsys CLK_MM_DISP_PWM026M>, +- <&mmsys CLK_MM_DISP_PWM0MM>; +- clock-names = "main", "mm"; +- status = "disabled"; +- }; +- +- pwm1: pwm@1401f000 { +- compatible = "mediatek,mt8173-disp-pwm", +- "mediatek,mt6595-disp-pwm"; +- reg = <0 0x1401f000 0 0x1000>; +- #pwm-cells = <2>; +- clocks = <&mmsys CLK_MM_DISP_PWM126M>, +- <&mmsys CLK_MM_DISP_PWM1MM>; +- clock-names = "main", "mm"; +- status = "disabled"; +- }; +- +- mutex: mutex@14020000 { +- compatible = "mediatek,mt8173-disp-mutex"; +- reg = <0 0x14020000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_MUTEX_32K>; +- mediatek,gce-events = , +- ; +- }; +- +- larb0: larb@14021000 { +- compatible = "mediatek,mt8173-smi-larb"; +- reg = <0 0x14021000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_SMI_LARB0>, +- <&mmsys CLK_MM_SMI_LARB0>; +- clock-names = "apb", "smi"; +- }; +- +- smi_common: smi@14022000 { +- compatible = "mediatek,mt8173-smi-common"; +- reg = <0 0x14022000 0 0x1000>; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_SMI_COMMON>, +- <&mmsys CLK_MM_SMI_COMMON>; +- clock-names = "apb", "smi"; +- }; +- +- od@14023000 { +- compatible = "mediatek,mt8173-disp-od"; +- reg = <0 0x14023000 0 0x1000>; +- clocks = <&mmsys CLK_MM_DISP_OD>; +- }; +- +- hdmi0: hdmi@14025000 { +- compatible = "mediatek,mt8173-hdmi"; +- reg = <0 0x14025000 0 0x400>; +- interrupts = ; +- clocks = <&mmsys CLK_MM_HDMI_PIXEL>, +- <&mmsys CLK_MM_HDMI_PLLCK>, +- <&mmsys CLK_MM_HDMI_AUDIO>, +- <&mmsys CLK_MM_HDMI_SPDIF>; +- clock-names = "pixel", "pll", "bclk", "spdif"; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_pin>; +- phys = <&hdmi_phy>; +- phy-names = "hdmi"; +- mediatek,syscon-hdmi = <&mmsys 0x900>; +- assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; +- assigned-clock-parents = <&hdmi_phy>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- hdmi0_in: endpoint { +- remote-endpoint = <&dpi0_out>; +- }; +- }; +- }; +- }; +- +- larb4: larb@14027000 { +- compatible = "mediatek,mt8173-smi-larb"; +- reg = <0 0x14027000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- power-domains = <&spm MT8173_POWER_DOMAIN_MM>; +- clocks = <&mmsys CLK_MM_SMI_LARB4>, +- <&mmsys CLK_MM_SMI_LARB4>; +- clock-names = "apb", "smi"; +- }; +- +- imgsys: clock-controller@15000000 { +- compatible = "mediatek,mt8173-imgsys", "syscon"; +- reg = <0 0x15000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- larb2: larb@15001000 { +- compatible = "mediatek,mt8173-smi-larb"; +- reg = <0 0x15001000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- power-domains = <&spm MT8173_POWER_DOMAIN_ISP>; +- clocks = <&imgsys CLK_IMG_LARB2_SMI>, +- <&imgsys CLK_IMG_LARB2_SMI>; +- clock-names = "apb", "smi"; +- }; +- +- vdecsys: clock-controller@16000000 { +- compatible = "mediatek,mt8173-vdecsys", "syscon"; +- reg = <0 0x16000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- vcodec_dec: vcodec@16000000 { +- compatible = "mediatek,mt8173-vcodec-dec"; +- reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ +- <0 0x16020000 0 0x1000>, /* VDEC_MISC */ +- <0 0x16021000 0 0x800>, /* VDEC_LD */ +- <0 0x16021800 0 0x800>, /* VDEC_TOP */ +- <0 0x16022000 0 0x1000>, /* VDEC_CM */ +- <0 0x16023000 0 0x1000>, /* VDEC_AD */ +- <0 0x16024000 0 0x1000>, /* VDEC_AV */ +- <0 0x16025000 0 0x1000>, /* VDEC_PP */ +- <0 0x16026800 0 0x800>, /* VDEC_HWD */ +- <0 0x16027000 0 0x800>, /* VDEC_HWQ */ +- <0 0x16027800 0 0x800>, /* VDEC_HWB */ +- <0 0x16028400 0 0x400>; /* VDEC_HWG */ +- interrupts = ; +- mediatek,larb = <&larb1>; +- iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, +- <&iommu M4U_PORT_HW_VDEC_PP_EXT>, +- <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, +- <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, +- <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, +- <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, +- <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, +- <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; +- mediatek,vpu = <&vpu>; +- power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; +- clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, +- <&topckgen CLK_TOP_UNIVPLL_D2>, +- <&topckgen CLK_TOP_CCI400_SEL>, +- <&topckgen CLK_TOP_VDEC_SEL>, +- <&topckgen CLK_TOP_VCODECPLL>, +- <&apmixedsys CLK_APMIXED_VENCPLL>, +- <&topckgen CLK_TOP_VENC_LT_SEL>, +- <&topckgen CLK_TOP_VCODECPLL_370P5>; +- clock-names = "vcodecpll", +- "univpll_d2", +- "clk_cci400_sel", +- "vdec_sel", +- "vdecpll", +- "vencpll", +- "venc_lt_sel", +- "vdec_bus_clk_src"; +- assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, +- <&topckgen CLK_TOP_CCI400_SEL>, +- <&topckgen CLK_TOP_VDEC_SEL>, +- <&apmixedsys CLK_APMIXED_VCODECPLL>, +- <&apmixedsys CLK_APMIXED_VENCPLL>; +- assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, +- <&topckgen CLK_TOP_UNIVPLL_D2>, +- <&topckgen CLK_TOP_VCODECPLL>; +- assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; +- }; +- +- larb1: larb@16010000 { +- compatible = "mediatek,mt8173-smi-larb"; +- reg = <0 0x16010000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; +- clocks = <&vdecsys CLK_VDEC_CKEN>, +- <&vdecsys CLK_VDEC_LARB_CKEN>; +- clock-names = "apb", "smi"; +- }; +- +- vencsys: clock-controller@18000000 { +- compatible = "mediatek,mt8173-vencsys", "syscon"; +- reg = <0 0x18000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- larb3: larb@18001000 { +- compatible = "mediatek,mt8173-smi-larb"; +- reg = <0 0x18001000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; +- clocks = <&vencsys CLK_VENC_CKE1>, +- <&vencsys CLK_VENC_CKE0>; +- clock-names = "apb", "smi"; +- }; +- +- vcodec_enc_avc: vcodec@18002000 { +- compatible = "mediatek,mt8173-vcodec-enc"; +- reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */ +- interrupts = ; +- mediatek,larb = <&larb3>; +- iommus = <&iommu M4U_PORT_VENC_RCPU>, +- <&iommu M4U_PORT_VENC_REC>, +- <&iommu M4U_PORT_VENC_BSDMA>, +- <&iommu M4U_PORT_VENC_SV_COMV>, +- <&iommu M4U_PORT_VENC_RD_COMV>, +- <&iommu M4U_PORT_VENC_CUR_LUMA>, +- <&iommu M4U_PORT_VENC_CUR_CHROMA>, +- <&iommu M4U_PORT_VENC_REF_LUMA>, +- <&iommu M4U_PORT_VENC_REF_CHROMA>, +- <&iommu M4U_PORT_VENC_NBM_RDMA>, +- <&iommu M4U_PORT_VENC_NBM_WDMA>; +- mediatek,vpu = <&vpu>; +- clocks = <&topckgen CLK_TOP_VENC_SEL>; +- clock-names = "venc_sel"; +- assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; +- }; +- +- jpegdec: jpegdec@18004000 { +- compatible = "mediatek,mt8173-jpgdec"; +- reg = <0 0x18004000 0 0x1000>; +- interrupts = ; +- clocks = <&vencsys CLK_VENC_CKE0>, +- <&vencsys CLK_VENC_CKE3>; +- clock-names = "jpgdec-smi", +- "jpgdec"; +- power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; +- mediatek,larb = <&larb3>; +- iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, +- <&iommu M4U_PORT_JPGDEC_BSDMA>; +- }; +- +- vencltsys: clock-controller@19000000 { +- compatible = "mediatek,mt8173-vencltsys", "syscon"; +- reg = <0 0x19000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- larb5: larb@19001000 { +- compatible = "mediatek,mt8173-smi-larb"; +- reg = <0 0x19001000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>; +- clocks = <&vencltsys CLK_VENCLT_CKE1>, +- <&vencltsys CLK_VENCLT_CKE0>; +- clock-names = "apb", "smi"; +- }; +- +- vcodec_enc_vp8: vcodec@19002000 { +- compatible = "mediatek,mt8173-vcodec-enc-vp8"; +- reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ +- interrupts = ; +- iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, +- <&iommu M4U_PORT_VENC_REC_FRM_SET2>, +- <&iommu M4U_PORT_VENC_BSDMA_SET2>, +- <&iommu M4U_PORT_VENC_SV_COMA_SET2>, +- <&iommu M4U_PORT_VENC_RD_COMA_SET2>, +- <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, +- <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, +- <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, +- <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; +- mediatek,larb = <&larb5>; +- mediatek,vpu = <&vpu>; +- clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; +- clock-names = "venc_lt_sel"; +- assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; +- assigned-clock-parents = +- <&topckgen CLK_TOP_VCODECPLL_370P5>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-evb.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-evb.dts +deleted file mode 100644 +index 7bc0a6a7fadf..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-evb.dts ++++ /dev/null +@@ -1,415 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (c) 2018 MediaTek Inc. +- * Author: Ben Ho +- * Erin Lo +- */ +- +-/dts-v1/; +-#include "mt8183.dtsi" +-#include "mt6358.dtsi" +- +-/ { +- model = "MediaTek MT8183 evaluation board"; +- compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x80000000>; +- }; +- +- chosen { +- stdout-path = "serial0:921600n8"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- scp_mem_reserved: scp_mem_region { +- compatible = "shared-dma-pool"; +- reg = <0 0x50000000 0 0x2900000>; +- no-map; +- }; +- }; +-}; +- +-&auxadc { +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&mt6358_vgpu_reg>; +- sram-supply = <&mt6358_vsram_gpu_reg>; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_pins_0>; +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_pins_1>; +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_pins_2>; +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_pins_3>; +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_pins_4>; +- status = "okay"; +- clock-frequency = <1000000>; +-}; +- +-&i2c5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_pins_5>; +- status = "okay"; +- clock-frequency = <1000000>; +-}; +- +-&mmc0 { +- status = "okay"; +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc0_pins_default>; +- pinctrl-1 = <&mmc0_pins_uhs>; +- bus-width = <8>; +- max-frequency = <200000000>; +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- cap-mmc-hw-reset; +- no-sdio; +- no-sd; +- hs400-ds-delay = <0x12814>; +- vmmc-supply = <&mt6358_vemc_reg>; +- vqmmc-supply = <&mt6358_vio18_reg>; +- assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; +- assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; +- non-removable; +-}; +- +-&mmc1 { +- status = "okay"; +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc1_pins_default>; +- pinctrl-1 = <&mmc1_pins_uhs>; +- bus-width = <4>; +- max-frequency = <200000000>; +- cap-sd-highspeed; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- cap-sdio-irq; +- no-mmc; +- no-sd; +- vmmc-supply = <&mt6358_vmch_reg>; +- vqmmc-supply = <&mt6358_vmc_reg>; +- keep-power-in-suspend; +- enable-sdio-wakeup; +- non-removable; +-}; +- +-&pio { +- i2c_pins_0: i2c0{ +- pins_i2c{ +- pinmux = , +- ; +- mediatek,pull-up-adv = <3>; +- mediatek,drive-strength-adv = <00>; +- }; +- }; +- +- i2c_pins_1: i2c1{ +- pins_i2c{ +- pinmux = , +- ; +- mediatek,pull-up-adv = <3>; +- mediatek,drive-strength-adv = <00>; +- }; +- }; +- +- i2c_pins_2: i2c2{ +- pins_i2c{ +- pinmux = , +- ; +- mediatek,pull-up-adv = <3>; +- mediatek,drive-strength-adv = <00>; +- }; +- }; +- +- i2c_pins_3: i2c3{ +- pins_i2c{ +- pinmux = , +- ; +- mediatek,pull-up-adv = <3>; +- mediatek,drive-strength-adv = <00>; +- }; +- }; +- +- i2c_pins_4: i2c4{ +- pins_i2c{ +- pinmux = , +- ; +- mediatek,pull-up-adv = <3>; +- mediatek,drive-strength-adv = <00>; +- }; +- }; +- +- i2c_pins_5: i2c5{ +- pins_i2c{ +- pinmux = , +- ; +- mediatek,pull-up-adv = <3>; +- mediatek,drive-strength-adv = <00>; +- }; +- }; +- +- spi_pins_0: spi0{ +- pins_spi{ +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- }; +- +- mmc0_pins_default: mmc0default { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- ; +- input-enable; +- bias-pull-up; +- }; +- +- pins_clk { +- pinmux = ; +- bias-pull-down; +- }; +- +- pins_rst { +- pinmux = ; +- bias-pull-up; +- }; +- }; +- +- mmc0_pins_uhs: mmc0 { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- ; +- input-enable; +- drive-strength = ; +- bias-pull-up = ; +- }; +- +- pins_clk { +- pinmux = ; +- drive-strength = ; +- bias-pull-down = ; +- }; +- +- pins_ds { +- pinmux = ; +- drive-strength = ; +- bias-pull-down = ; +- }; +- +- pins_rst { +- pinmux = ; +- drive-strength = ; +- bias-pull-up; +- }; +- }; +- +- mmc1_pins_default: mmc1default { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- ; +- input-enable; +- bias-pull-up; +- }; +- +- pins_clk { +- pinmux = ; +- input-enable; +- bias-pull-down; +- }; +- +- pins_pmu { +- pinmux = , +- ; +- output-high; +- }; +- }; +- +- mmc1_pins_uhs: mmc1 { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- ; +- drive-strength = ; +- input-enable; +- bias-pull-up = ; +- }; +- +- pins_clk { +- pinmux = ; +- drive-strength = ; +- bias-pull-down = ; +- input-enable; +- }; +- }; +- +- spi_pins_1: spi1{ +- pins_spi{ +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- }; +- +- spi_pins_2: spi2{ +- pins_spi{ +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- }; +- +- spi_pins_3: spi3{ +- pins_spi{ +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- }; +- +- spi_pins_4: spi4{ +- pins_spi{ +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- }; +- +- spi_pins_5: spi5{ +- pins_spi{ +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- }; +- +- pwm_pins_1: pwm1 { +- pins_pwm { +- pinmux = ; +- }; +- }; +-}; +- +-&mfg { +- domain-supply = <&mt6358_vgpu_reg>; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_pins_0>; +- mediatek,pad-select = <0>; +- status = "okay"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_pins_1>; +- mediatek,pad-select = <0>; +- status = "okay"; +-}; +- +-&spi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_pins_2>; +- mediatek,pad-select = <0>; +- status = "okay"; +-}; +- +-&spi3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_pins_3>; +- mediatek,pad-select = <0>; +- status = "okay"; +-}; +- +-&spi4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_pins_4>; +- mediatek,pad-select = <0>; +- status = "okay"; +-}; +- +-&spi5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_pins_5>; +- mediatek,pad-select = <0>; +- status = "okay"; +- +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&pwm1 { +- status = "okay"; +- pinctrl-0 = <&pwm_pins_1>; +- pinctrl-names = "default"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-burnet.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-burnet.dts +deleted file mode 100644 +index a8d6f32ade8d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-burnet.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2021 Google LLC +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-jacuzzi.dtsi" +- +-/ { +- model = "Google burnet board"; +- compatible = "google,burnet", "mediatek,mt8183"; +-}; +- +-&mt6358codec { +- mediatek,dmic-mode = <1>; /* one-wire */ +-}; +- +-&i2c0 { +- touchscreen@2c { +- compatible = "hid-over-i2c"; +- reg = <0x2c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&touchscreen_pins>; +- interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>; +- +- post-power-on-delay-ms = <200>; +- hid-descr-addr = <0x0020>; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts +deleted file mode 100644 +index 42ba9c00866c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2021 Google LLC +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-jacuzzi.dtsi" +- +-/ { +- model = "Google damu board"; +- compatible = "google,damu", "mediatek,mt8183"; +-}; +- +-&touchscreen { +- status = "okay"; +- +- compatible = "hid-over-i2c"; +- reg = <0x10>; +- interrupt-parent = <&pio>; +- interrupts = <155 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&touchscreen_pins>; +- +- post-power-on-delay-ms = <10>; +- hid-descr-addr = <0x0001>; +-}; +- +-&qca_wifi { +- qcom,ath10k-calibration-variant = "GO_DAMU"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts +deleted file mode 100644 +index ef6257c9a2d2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts ++++ /dev/null +@@ -1,44 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2021 Google LLC +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-jacuzzi-fennel.dtsi" +- +-/ { +- model = "Google fennel sku1 board"; +- compatible = "google,fennel-sku1", "google,fennel", "mediatek,mt8183"; +- +- pwmleds { +- compatible = "pwm-leds"; +- keyboard_backlight: keyboard-backlight { +- label = "cros_ec::kbd_backlight"; +- pwms = <&cros_ec_pwm 0>; +- max-brightness = <1023>; +- }; +- }; +-}; +- +-&cros_ec_pwm { +- status = "okay"; +-}; +- +-&touchscreen { +- status = "okay"; +- +- compatible = "hid-over-i2c"; +- reg = <0x10>; +- interrupt-parent = <&pio>; +- interrupts = <155 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&touchscreen_pins>; +- +- post-power-on-delay-ms = <10>; +- hid-descr-addr = <0x0001>; +-}; +- +-&qca_wifi { +- qcom,ath10k-calibration-variant = "GO_FENNEL"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts +deleted file mode 100644 +index 899c2e42385c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2021 Google LLC +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-jacuzzi-fennel.dtsi" +- +-/ { +- model = "Google fennel sku6 board"; +- compatible = "google,fennel-sku6", "google,fennel", "mediatek,mt8183"; +-}; +- +-&touchscreen { +- status = "okay"; +- +- compatible = "hid-over-i2c"; +- reg = <0x10>; +- interrupt-parent = <&pio>; +- interrupts = <155 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&touchscreen_pins>; +- +- post-power-on-delay-ms = <10>; +- hid-descr-addr = <0x0001>; +-}; +- +- +-&qca_wifi { +- qcom,ath10k-calibration-variant = "GO_FENNEL"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi +deleted file mode 100644 +index bbe6c338f465..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi ++++ /dev/null +@@ -1,27 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2021 Google LLC +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-jacuzzi.dtsi" +- +-&mt6358codec { +- mediatek,dmic-mode = <1>; /* one-wire */ +-}; +- +-&i2c2 { +- trackpad@2c { +- compatible = "hid-over-i2c"; +- reg = <0x2c>; +- hid-descr-addr = <0x20>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&trackpad_pins>; +- +- interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>; +- +- wakeup-source; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-fennel14.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-fennel14.dts +deleted file mode 100644 +index e8c41f6b4b0d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-fennel14.dts ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2021 Google LLC +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-jacuzzi-fennel.dtsi" +- +-/ { +- model = "Google fennel14 sku0 board"; +- compatible = "google,fennel-sku0", "google,fennel", "mediatek,mt8183"; +-}; +- +-&qca_wifi { +- qcom,ath10k-calibration-variant = "GO_FENNEL14"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts +deleted file mode 100644 +index 36d2c3b3cadf..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2021 Google LLC +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-jacuzzi-juniper.dtsi" +- +-/ { +- model = "Google juniper sku16 board"; +- compatible = "google,juniper-sku16", "google,juniper", "mediatek,mt8183"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-juniper.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-juniper.dtsi +deleted file mode 100644 +index 078bc765646f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-juniper.dtsi ++++ /dev/null +@@ -1,27 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2021 Google LLC +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-jacuzzi.dtsi" +- +-&i2c2 { +- trackpad@2c { +- compatible = "hid-over-i2c"; +- reg = <0x2c>; +- hid-descr-addr = <0x20>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&trackpad_pins>; +- +- interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>; +- +- wakeup-source; +- }; +-}; +- +-&qca_wifi { +- qcom,ath10k-calibration-variant = "GO_JUNIPER"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-kappa.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-kappa.dts +deleted file mode 100644 +index b3f46c16e5d7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-kappa.dts ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2021 Google LLC +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-jacuzzi.dtsi" +- +-/ { +- model = "Google kappa board"; +- compatible = "google,kappa", "mediatek,mt8183"; +-}; +- +-&mt6358codec { +- mediatek,dmic-mode = <1>; /* one-wire */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts +deleted file mode 100644 +index 6f1aa692753a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2021 Google LLC +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-jacuzzi-juniper.dtsi" +- +-/ { +- model = "Google kenzo sku17 board"; +- compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts +deleted file mode 100644 +index 281265f082db..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2021 Google LLC +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-jacuzzi-willow.dtsi" +- +-/ { +- model = "Google willow board sku0"; +- compatible = "google,willow-sku0", "google,willow", "mediatek,mt8183"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts +deleted file mode 100644 +index 22e56bdc1ee3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2021 Google LLC +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-jacuzzi-willow.dtsi" +- +-/ { +- model = "Google willow board sku1"; +- compatible = "google,willow-sku1", "google,willow", "mediatek,mt8183"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-willow.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-willow.dtsi +deleted file mode 100644 +index 76d33540166f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi-willow.dtsi ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2021 Google LLC +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-jacuzzi.dtsi" +- +-&i2c2 { +- trackpad@2c { +- compatible = "hid-over-i2c"; +- reg = <0x2c>; +- hid-descr-addr = <0x20>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&trackpad_pins>; +- +- interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>; +- +- wakeup-source; +- }; +-}; +- +-&qca_wifi { +- qcom,ath10k-calibration-variant = "GO_JUNIPER"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi +deleted file mode 100644 +index d8826c82bcda..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi ++++ /dev/null +@@ -1,482 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2021 Google LLC +- */ +- +-#include "mt8183-kukui.dtsi" +- +-/ { +- panel: panel { +- compatible = "auo,b116xw03"; +- power-supply = <&pp3300_panel>; +- ddc-i2c-bus = <&i2c4>; +- backlight = <&backlight_lcd0>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&anx7625_out>; +- }; +- }; +- }; +- +- pp1200_mipibrdg: pp1200-mipibrdg { +- compatible = "regulator-fixed"; +- regulator-name = "pp1200_mipibrdg"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pp1200_mipibrdg_en>; +- +- enable-active-high; +- regulator-boot-on; +- +- gpio = <&pio 54 GPIO_ACTIVE_HIGH>; +- }; +- +- pp1800_mipibrdg: pp1800-mipibrdg { +- compatible = "regulator-fixed"; +- regulator-name = "pp1800_mipibrdg"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pp1800_lcd_en>; +- +- enable-active-high; +- regulator-boot-on; +- +- gpio = <&pio 36 GPIO_ACTIVE_HIGH>; +- }; +- +- pp3300_panel: pp3300-panel { +- compatible = "regulator-fixed"; +- regulator-name = "pp3300_panel"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pp3300_panel_pins>; +- +- enable-active-high; +- regulator-boot-on; +- +- gpio = <&pio 35 GPIO_ACTIVE_HIGH>; +- }; +- +- vddio_mipibrdg: vddio-mipibrdg { +- compatible = "regulator-fixed"; +- regulator-name = "vddio_mipibrdg"; +- pinctrl-names = "default"; +- pinctrl-0 = <&vddio_mipibrdg_en>; +- +- enable-active-high; +- regulator-boot-on; +- +- gpio = <&pio 37 GPIO_ACTIVE_HIGH>; +- }; +- +- volume_buttons: volume-buttons { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&volume_button_pins>; +- +- volume_down { +- label = "Volume Down"; +- linux,code = ; +- debounce-interval = <100>; +- +- gpios = <&pio 6 GPIO_ACTIVE_LOW>; +- }; +- +- volume_up { +- label = "Volume Up"; +- linux,code = ; +- debounce-interval = <100>; +- +- gpios = <&pio 5 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&cros_ec { +- cros_ec_pwm: ec-pwm { +- compatible = "google,cros-ec-pwm"; +- #pwm-cells = <1>; +- status = "disabled"; +- }; +-}; +- +-&dsi0 { +- status = "okay"; +- /delete-node/panel@0; +- ports { +- port { +- dsi_out: endpoint { +- remote-endpoint = <&anx7625_in>; +- }; +- }; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- touchscreen: touchscreen@10 { +- compatible = "elan,ekth3500"; +- reg = <0x10>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&touchscreen_pins>; +- +- interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>; +- +- reset-gpios = <&pio 156 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "okay"; +- clock-frequency = <400000>; +- +- trackpad@15 { +- compatible = "elan,ekth3000"; +- reg = <0x15>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&trackpad_pins>; +- +- interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>; +- +- wakeup-source; +- }; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pins>; +- status = "okay"; +- clock-frequency = <100000>; +- +- anx_bridge: anx7625@58 { +- compatible = "analogix,anx7625"; +- reg = <0x58>; +- pinctrl-names = "default"; +- pinctrl-0 = <&anx7625_pins>; +- panel_flags = <1>; +- enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&pio 73 GPIO_ACTIVE_HIGH>; +- vdd10-supply = <&pp1200_mipibrdg>; +- vdd18-supply = <&pp1800_mipibrdg>; +- vdd33-supply = <&vddio_mipibrdg>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- +- anx7625_in: endpoint { +- remote-endpoint = <&dsi_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- anx7625_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&i2c_tunnel { +- google,remote-bus = <2>; +-}; +- +-&pio { +- /* 192 lines */ +- gpio-line-names = +- "SPI_AP_EC_CS_L", +- "SPI_AP_EC_MOSI", +- "SPI_AP_EC_CLK", +- "I2S3_DO", +- "USB_PD_INT_ODL", +- "", +- "", +- "", +- "", +- "IT6505_HPD_L", +- "I2S3_TDM_D3", +- "SOC_I2C6_1V8_SCL", +- "SOC_I2C6_1V8_SDA", +- "DPI_D0", +- "DPI_D1", +- "DPI_D2", +- "DPI_D3", +- "DPI_D4", +- "DPI_D5", +- "DPI_D6", +- "DPI_D7", +- "DPI_D8", +- "DPI_D9", +- "DPI_D10", +- "DPI_D11", +- "DPI_HSYNC", +- "DPI_VSYNC", +- "DPI_DE", +- "DPI_CK", +- "AP_MSDC1_CLK", +- "AP_MSDC1_DAT3", +- "AP_MSDC1_CMD", +- "AP_MSDC1_DAT0", +- "AP_MSDC1_DAT2", +- "AP_MSDC1_DAT1", +- "", +- "", +- "", +- "", +- "", +- "", +- "OTG_EN", +- "DRVBUS", +- "DISP_PWM", +- "DSI_TE", +- "LCM_RST_1V8", +- "AP_CTS_WIFI_RTS", +- "AP_RTS_WIFI_CTS", +- "SOC_I2C5_1V8_SCL", +- "SOC_I2C5_1V8_SDA", +- "SOC_I2C3_1V8_SCL", +- "SOC_I2C3_1V8_SDA", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "SOC_I2C1_1V8_SDA", +- "SOC_I2C0_1V8_SDA", +- "SOC_I2C0_1V8_SCL", +- "SOC_I2C1_1V8_SCL", +- "AP_SPI_H1_MISO", +- "AP_SPI_H1_CS_L", +- "AP_SPI_H1_MOSI", +- "AP_SPI_H1_CLK", +- "I2S5_BCK", +- "I2S5_LRCK", +- "I2S5_DO", +- "BOOTBLOCK_EN_L", +- "MT8183_KPCOL0", +- "SPI_AP_EC_MISO", +- "UART_DBG_TX_AP_RX", +- "UART_AP_TX_DBG_RX", +- "I2S2_MCK", +- "I2S2_BCK", +- "CLK_5M_WCAM", +- "CLK_2M_UCAM", +- "I2S2_LRCK", +- "I2S2_DI", +- "SOC_I2C2_1V8_SCL", +- "SOC_I2C2_1V8_SDA", +- "SOC_I2C4_1V8_SCL", +- "SOC_I2C4_1V8_SDA", +- "", +- "SCL8", +- "SDA8", +- "FCAM_PWDN_L", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "", +- "", +- "", +- "", +- "", +- "", +- /* +- * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics +- * call it BIOS_FLASH_WP_R_L. +- */ +- "AP_FLASH_WP_L", +- "EC_AP_INT_ODL", +- "IT6505_INT_ODL", +- "H1_INT_OD_L", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "AP_SPI_FLASH_MISO", +- "AP_SPI_FLASH_CS_L", +- "AP_SPI_FLASH_MOSI", +- "AP_SPI_FLASH_CLK", +- "DA7219_IRQ", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- ""; +- +- pp1200_mipibrdg_en: pp1200-mipibrdg-en { +- pins1 { +- pinmux = ; +- output-low; +- }; +- }; +- +- pp1800_lcd_en: pp1800-lcd-en { +- pins1 { +- pinmux = ; +- output-low; +- }; +- }; +- +- pp3300_panel_pins: pp3300-panel-pins { +- panel_3v3_enable: panel-3v3-enable { +- pinmux = ; +- output-low; +- }; +- }; +- +- ppvarp_lcd_en: ppvarp-lcd-en { +- pins1 { +- pinmux = ; +- output-low; +- }; +- }; +- +- ppvarn_lcd_en: ppvarn-lcd-en { +- pins1 { +- pinmux = ; +- output-low; +- }; +- }; +- +- anx7625_pins: anx7625-pins { +- pins1 { +- pinmux = , +- ; +- output-low; +- }; +- pins2 { +- pinmux = ; +- input-enable; +- bias-pull-up; +- }; +- }; +- +- touchscreen_pins: touchscreen-pins { +- touch_int_odl { +- pinmux = ; +- input-enable; +- bias-pull-up; +- }; +- +- touch_rst_l { +- pinmux = ; +- output-high; +- }; +- }; +- +- trackpad_pins: trackpad-pins { +- trackpad_int { +- pinmux = ; +- input-enable; +- bias-disable; /* pulled externally */ +- }; +- }; +- +- vddio_mipibrdg_en: vddio-mipibrdg-en { +- pins1 { +- pinmux = ; +- output-low; +- }; +- }; +- +- volume_button_pins: volume-button-pins { +- voldn-btn-odl { +- pinmux = ; +- input-enable; +- bias-pull-up; +- }; +- +- volup-btn-odl { +- pinmux = ; +- input-enable; +- bias-pull-up; +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kakadu.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kakadu.dts +deleted file mode 100644 +index 20eb0dc68f09..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kakadu.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2020 Google LLC +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-kakadu.dtsi" +- +-/ { +- model = "MediaTek kakadu board"; +- compatible = "google,kakadu-rev3", "google,kakadu-rev2", +- "google,kakadu", "mediatek,mt8183"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kakadu.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kakadu.dtsi +deleted file mode 100644 +index 28966a65391b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kakadu.dtsi ++++ /dev/null +@@ -1,382 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2020 Google LLC +- */ +- +-#include "mt8183-kukui.dtsi" +-#include +- +-/ { +- ppvarn_lcd: ppvarn-lcd { +- compatible = "regulator-fixed"; +- regulator-name = "ppvarn_lcd"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ppvarn_lcd_en>; +- +- enable-active-high; +- +- gpio = <&pio 66 GPIO_ACTIVE_HIGH>; +- }; +- +- ppvarp_lcd: ppvarp-lcd { +- compatible = "regulator-fixed"; +- regulator-name = "ppvarp_lcd"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ppvarp_lcd_en>; +- +- enable-active-high; +- +- gpio = <&pio 166 GPIO_ACTIVE_HIGH>; +- }; +- +- pp1800_lcd: pp1800-lcd { +- compatible = "regulator-fixed"; +- regulator-name = "pp1800_lcd"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pp1800_lcd_en>; +- +- enable-active-high; +- +- gpio = <&pio 36 GPIO_ACTIVE_HIGH>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pen_eject>; +- +- pen-insert { +- label = "Pen Insert"; +- /* Insert = low, eject = high */ +- gpios = <&pio 6 GPIO_ACTIVE_LOW>; +- linux,code = ; +- linux,input-type = ; +- wakeup-event-action = ; +- wakeup-source; +- }; +- }; +-}; +- +-&bluetooth { +- firmware-name = "nvm_00440302_i2s_eu.bin"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- touchscreen: touchscreen@10 { +- compatible = "hid-over-i2c"; +- reg = <0x10>; +- pinctrl-names = "default"; +- pinctrl-0 = <&open_touch>; +- +- interrupt-parent = <&pio>; +- interrupts = <155 IRQ_TYPE_EDGE_FALLING>; +- +- post-power-on-delay-ms = <10>; +- hid-descr-addr = <0x0001>; +- }; +-}; +- +-&mt6358_vcama2_reg { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "okay"; +- clock-frequency = <400000>; +- vbus-supply = <&mt6358_vcamio_reg>; +- +- eeprom@58 { +- compatible = "atmel,24c32"; +- reg = <0x58>; +- pagesize = <32>; +- vcc-supply = <&mt6358_vcama2_reg>; +- }; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pins>; +- status = "okay"; +- clock-frequency = <400000>; +- vbus-supply = <&mt6358_vcn18_reg>; +- +- eeprom@54 { +- compatible = "atmel,24c32"; +- reg = <0x54>; +- pagesize = <32>; +- vcc-supply = <&mt6358_vcn18_reg>; +- }; +-}; +- +-&mipi_tx0 { +- drive-strength-microamp = <5800>; +-}; +- +-&pio { +- /* 192 lines */ +- gpio-line-names = +- "SPI_AP_EC_CS_L", +- "SPI_AP_EC_MOSI", +- "SPI_AP_EC_CLK", +- "I2S3_DO", +- "USB_PD_INT_ODL", +- "", +- "", +- "", +- "", +- "IT6505_HPD_L", +- "I2S3_TDM_D3", +- "SOC_I2C6_1V8_SCL", +- "SOC_I2C6_1V8_SDA", +- "DPI_D0", +- "DPI_D1", +- "DPI_D2", +- "DPI_D3", +- "DPI_D4", +- "DPI_D5", +- "DPI_D6", +- "DPI_D7", +- "DPI_D8", +- "DPI_D9", +- "DPI_D10", +- "DPI_D11", +- "DPI_HSYNC", +- "DPI_VSYNC", +- "DPI_DE", +- "DPI_CK", +- "AP_MSDC1_CLK", +- "AP_MSDC1_DAT3", +- "AP_MSDC1_CMD", +- "AP_MSDC1_DAT0", +- "AP_MSDC1_DAT2", +- "AP_MSDC1_DAT1", +- "", +- "", +- "", +- "", +- "", +- "", +- "OTG_EN", +- "DRVBUS", +- "DISP_PWM", +- "DSI_TE", +- "LCM_RST_1V8", +- "AP_CTS_WIFI_RTS", +- "AP_RTS_WIFI_CTS", +- "SOC_I2C5_1V8_SCL", +- "SOC_I2C5_1V8_SDA", +- "SOC_I2C3_1V8_SCL", +- "SOC_I2C3_1V8_SDA", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "SOC_I2C1_1V8_SDA", +- "SOC_I2C0_1V8_SDA", +- "SOC_I2C0_1V8_SCL", +- "SOC_I2C1_1V8_SCL", +- "AP_SPI_H1_MISO", +- "AP_SPI_H1_CS_L", +- "AP_SPI_H1_MOSI", +- "AP_SPI_H1_CLK", +- "I2S5_BCK", +- "I2S5_LRCK", +- "I2S5_DO", +- "BOOTBLOCK_EN_L", +- "MT8183_KPCOL0", +- "SPI_AP_EC_MISO", +- "UART_DBG_TX_AP_RX", +- "UART_AP_TX_DBG_RX", +- "I2S2_MCK", +- "I2S2_BCK", +- "CLK_5M_WCAM", +- "CLK_2M_UCAM", +- "I2S2_LRCK", +- "I2S2_DI", +- "SOC_I2C2_1V8_SCL", +- "SOC_I2C2_1V8_SDA", +- "SOC_I2C4_1V8_SCL", +- "SOC_I2C4_1V8_SDA", +- "", +- "SCL8", +- "SDA8", +- "FCAM_PWDN_L", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "", +- "", +- "", +- "", +- "", +- "", +- /* +- * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics +- * call it BIOS_FLASH_WP_R_L. +- */ +- "AP_FLASH_WP_L", +- "EC_AP_INT_ODL", +- "IT6505_INT_ODL", +- "H1_INT_OD_L", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "AP_SPI_FLASH_MISO", +- "AP_SPI_FLASH_CS_L", +- "AP_SPI_FLASH_MOSI", +- "AP_SPI_FLASH_CLK", +- "DA7219_IRQ", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- ""; +- +- ppvarp_lcd_en: ppvarp-lcd-en { +- pins1 { +- pinmux = ; +- output-low; +- }; +- }; +- +- ppvarn_lcd_en: ppvarn-lcd-en { +- pins1 { +- pinmux = ; +- output-low; +- }; +- }; +- +- pp1800_lcd_en: pp1800-lcd-en { +- pins1 { +- pinmux = ; +- output-low; +- }; +- }; +- +- open_touch: open_touch { +- irq_pin { +- pinmux = ; +- input-enable; +- bias-pull-up; +- }; +- +- rst_pin { +- pinmux = ; +- +- /* +- * The pen driver doesn't currently support driving +- * this reset line. By specifying output-high here +- * we're relying on the fact that this pin has a default +- * pulldown at boot (which makes sure the pen was in +- * reset if it was powered) and then we set it high here +- * to take it out of reset. Better would be if the pen +- * driver could control this and we could remove +- * "output-high" here. +- */ +- output-high; +- }; +- }; +- +- pen_eject: peneject { +- pen_eject { +- pinmux = ; +- input-enable; +- /* External pull-up. */ +- bias-disable; +- }; +- }; +-}; +- +-&qca_wifi { +- qcom,ath10k-calibration-variant = "GO_KAKADU"; +-}; +- +-&panel { +- status = "okay"; +- compatible = "boe,tv105wum-nw0"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kodama-sku16.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kodama-sku16.dts +deleted file mode 100644 +index e3dd75bdaea4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kodama-sku16.dts ++++ /dev/null +@@ -1,21 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2021 Google LLC +- * +- * SKU: 0x10 => 16 +- * - bit 8: Camera: 0 (OV5695) +- * - bits 7..4: Panel ID: 0x1 (AUO) +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-kodama.dtsi" +- +-/ { +- model = "MediaTek kodama sku16 board"; +- compatible = "google,kodama-sku16", "google,kodama", "mediatek,mt8183"; +-}; +- +-&panel { +- status = "okay"; +- compatible = "auo,b101uan08.3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kodama-sku272.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kodama-sku272.dts +deleted file mode 100644 +index d81935ae07bc..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kodama-sku272.dts ++++ /dev/null +@@ -1,21 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2020 Google LLC +- * +- * SKU: 0x110 => 272 +- * - bit 8: Camera: 1 (GC5035) +- * - bits 7..4: Panel ID: 0x1 (AUO) +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-kodama.dtsi" +- +-/ { +- model = "MediaTek kodama sku272 board"; +- compatible = "google,kodama-sku272", "google,kodama", "mediatek,mt8183"; +-}; +- +-&panel { +- status = "okay"; +- compatible = "auo,b101uan08.3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kodama-sku288.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kodama-sku288.dts +deleted file mode 100644 +index f4082fbe0517..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kodama-sku288.dts ++++ /dev/null +@@ -1,21 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2020 Google LLC +- * +- * SKU: 0x120 => 288 +- * - bit 8: Camera: 1 (GC5035) +- * - bits 7..4: Panel ID: 0x2 (BOE) +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-kodama.dtsi" +- +-/ { +- model = "MediaTek kodama sku288 board"; +- compatible = "google,kodama-sku288", "google,kodama", "mediatek,mt8183"; +-}; +- +-&panel { +- status = "okay"; +- compatible = "boe,tv101wum-n53"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kodama-sku32.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kodama-sku32.dts +deleted file mode 100644 +index 7739358008ee..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kodama-sku32.dts ++++ /dev/null +@@ -1,21 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2021 Google LLC +- * +- * SKU: 0x20 => 32 +- * - bit 8: Camera: 0 (OV5695) +- * - bits 7..4: Panel ID: 0x2 (BOE) +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-kodama.dtsi" +- +-/ { +- model = "MediaTek kodama sku32 board"; +- compatible = "google,kodama-sku32", "google,kodama", "mediatek,mt8183"; +-}; +- +-&panel { +- status = "okay"; +- compatible = "boe,tv101wum-n53"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kodama.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kodama.dtsi +deleted file mode 100644 +index 3aa79403c0c2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-kodama.dtsi ++++ /dev/null +@@ -1,347 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2021 Google LLC +- */ +- +-/dts-v1/; +-#include "mt8183-kukui.dtsi" +- +-/ { +- ppvarn_lcd: ppvarn-lcd { +- compatible = "regulator-fixed"; +- regulator-name = "ppvarn_lcd"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ppvarn_lcd_en>; +- +- enable-active-high; +- +- gpio = <&pio 66 GPIO_ACTIVE_HIGH>; +- }; +- +- ppvarp_lcd: ppvarp-lcd { +- compatible = "regulator-fixed"; +- regulator-name = "ppvarp_lcd"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ppvarp_lcd_en>; +- +- enable-active-high; +- +- gpio = <&pio 166 GPIO_ACTIVE_HIGH>; +- }; +- +- pp1800_lcd: pp1800-lcd { +- compatible = "regulator-fixed"; +- regulator-name = "pp1800_lcd"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pp1800_lcd_en>; +- +- enable-active-high; +- +- gpio = <&pio 36 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- +- touchscreen: touchscreen@10 { +- compatible = "hid-over-i2c"; +- reg = <0x10>; +- interrupt-parent = <&pio>; +- interrupts = <155 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&touch_default>; +- +- post-power-on-delay-ms = <10>; +- hid-descr-addr = <0x0001>; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "okay"; +- clock-frequency = <400000>; +- vbus-supply = <&mt6358_vcamio_reg>; +- +- eeprom@58 { +- compatible = "atmel,24c64"; +- reg = <0x58>; +- pagesize = <32>; +- vcc-supply = <&mt6358_vcamio_reg>; +- }; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pins>; +- status = "okay"; +- clock-frequency = <400000>; +- vbus-supply = <&mt6358_vcn18_reg>; +- +- eeprom@54 { +- compatible = "atmel,24c64"; +- reg = <0x54>; +- pagesize = <32>; +- vcc-supply = <&mt6358_vcn18_reg>; +- }; +-}; +- +-&mt6358_vcama2_reg { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +-}; +- +-&pio { +- /* 192 lines */ +- gpio-line-names = +- "SPI_AP_EC_CS_L", +- "SPI_AP_EC_MOSI", +- "SPI_AP_EC_CLK", +- "I2S3_DO", +- "USB_PD_INT_ODL", +- "", +- "", +- "", +- "", +- "IT6505_HPD_L", +- "I2S3_TDM_D3", +- "SOC_I2C6_1V8_SCL", +- "SOC_I2C6_1V8_SDA", +- "DPI_D0", +- "DPI_D1", +- "DPI_D2", +- "DPI_D3", +- "DPI_D4", +- "DPI_D5", +- "DPI_D6", +- "DPI_D7", +- "DPI_D8", +- "DPI_D9", +- "DPI_D10", +- "DPI_D11", +- "DPI_HSYNC", +- "DPI_VSYNC", +- "DPI_DE", +- "DPI_CK", +- "AP_MSDC1_CLK", +- "AP_MSDC1_DAT3", +- "AP_MSDC1_CMD", +- "AP_MSDC1_DAT0", +- "AP_MSDC1_DAT2", +- "AP_MSDC1_DAT1", +- "", +- "", +- "", +- "", +- "", +- "", +- "OTG_EN", +- "DRVBUS", +- "DISP_PWM", +- "DSI_TE", +- "LCM_RST_1V8", +- "AP_CTS_WIFI_RTS", +- "AP_RTS_WIFI_CTS", +- "SOC_I2C5_1V8_SCL", +- "SOC_I2C5_1V8_SDA", +- "SOC_I2C3_1V8_SCL", +- "SOC_I2C3_1V8_SDA", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "SOC_I2C1_1V8_SDA", +- "SOC_I2C0_1V8_SDA", +- "SOC_I2C0_1V8_SCL", +- "SOC_I2C1_1V8_SCL", +- "AP_SPI_H1_MISO", +- "AP_SPI_H1_CS_L", +- "AP_SPI_H1_MOSI", +- "AP_SPI_H1_CLK", +- "I2S5_BCK", +- "I2S5_LRCK", +- "I2S5_DO", +- "BOOTBLOCK_EN_L", +- "MT8183_KPCOL0", +- "SPI_AP_EC_MISO", +- "UART_DBG_TX_AP_RX", +- "UART_AP_TX_DBG_RX", +- "I2S2_MCK", +- "I2S2_BCK", +- "CLK_5M_WCAM", +- "CLK_2M_UCAM", +- "I2S2_LRCK", +- "I2S2_DI", +- "SOC_I2C2_1V8_SCL", +- "SOC_I2C2_1V8_SDA", +- "SOC_I2C4_1V8_SCL", +- "SOC_I2C4_1V8_SDA", +- "", +- "SCL8", +- "SDA8", +- "FCAM_PWDN_L", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "", +- "", +- "", +- "", +- "", +- "", +- /* +- * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics +- * call it BIOS_FLASH_WP_R_L. +- */ +- "AP_FLASH_WP_L", +- "EC_AP_INT_ODL", +- "IT6505_INT_ODL", +- "H1_INT_OD_L", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "AP_SPI_FLASH_MISO", +- "AP_SPI_FLASH_CS_L", +- "AP_SPI_FLASH_MOSI", +- "AP_SPI_FLASH_CLK", +- "DA7219_IRQ", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- ""; +- +- ppvarp_lcd_en: ppvarp-lcd-en { +- pins1 { +- pinmux = ; +- output-low; +- }; +- }; +- +- ppvarn_lcd_en: ppvarn-lcd-en { +- pins1 { +- pinmux = ; +- output-low; +- }; +- }; +- +- pp1800_lcd_en: pp1800-lcd-en { +- pins1 { +- pinmux = ; +- output-low; +- }; +- }; +- +- touch_default: touchdefault { +- pin_irq { +- pinmux = ; +- input-enable; +- bias-pull-up; +- }; +- +- touch_pin_reset: pin_reset { +- pinmux = ; +- +- /* +- * The touchscreen driver doesn't currently support driving +- * this reset line. By specifying output-high here +- * we're relying on the fact that this pin has a default +- * pulldown at boot (which makes sure the controller was in +- * reset if it was powered) and then we set it high here +- * to take it out of reset. Better would be if the touchscreen +- * driver could control this and we could remove +- * "output-high" here. +- */ +- output-high; +- }; +- }; +-}; +- +-&qca_wifi { +- qcom,ath10k-calibration-variant = "GO_KODAMA"; +-}; +- +-&i2c_tunnel { +- google,remote-bus = <2>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-krane-sku0.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-krane-sku0.dts +deleted file mode 100644 +index fb5ee91b6fe0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-krane-sku0.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2019 Google LLC +- * +- * Device-tree for Krane sku0. +- * +- * SKU is a 8-bit value (0x00 == 0): +- * - Bits 7..4: Panel ID: 0x0 (AUO) +- * - Bits 3..0: SKU ID: 0x0 (default) +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-krane.dtsi" +- +-/ { +- model = "MediaTek krane sku0 board"; +- compatible = "google,krane-sku0", "google,krane", "mediatek,mt8183"; +-}; +- +-&panel { +- status = "okay"; +- compatible = "auo,kd101n80-45na"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-krane-sku176.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-krane-sku176.dts +deleted file mode 100644 +index 721d16f9c3b4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-krane-sku176.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2019 Google LLC +- * +- * Device-tree for Krane sku176. +- * +- * SKU is a 8-bit value (0xb0 == 176): +- * - Bits 7..4: Panel ID: 0xb (BOE) +- * - Bits 3..0: SKU ID: 0x0 (default) +- */ +- +-/dts-v1/; +-#include "mt8183-kukui-krane.dtsi" +- +-/ { +- model = "MediaTek krane sku176 board"; +- compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183"; +-}; +- +-&panel { +- status = "okay"; +- compatible = "boe,tv101wum-nl6"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-krane.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-krane.dtsi +deleted file mode 100644 +index 30c183c96a54..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui-krane.dtsi ++++ /dev/null +@@ -1,347 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright 2019 Google LLC +- */ +- +-#include "mt8183-kukui.dtsi" +- +-/ { +- ppvarn_lcd: ppvarn-lcd { +- compatible = "regulator-fixed"; +- regulator-name = "ppvarn_lcd"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ppvarn_lcd_en>; +- +- enable-active-high; +- +- gpio = <&pio 66 GPIO_ACTIVE_HIGH>; +- }; +- +- ppvarp_lcd: ppvarp-lcd { +- compatible = "regulator-fixed"; +- regulator-name = "ppvarp_lcd"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ppvarp_lcd_en>; +- +- enable-active-high; +- +- gpio = <&pio 166 GPIO_ACTIVE_HIGH>; +- }; +- +- pp1800_lcd: pp1800-lcd { +- compatible = "regulator-fixed"; +- regulator-name = "pp1800_lcd"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pp1800_lcd_en>; +- +- enable-active-high; +- +- gpio = <&pio 36 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&bluetooth { +- firmware-name = "nvm_00440302_i2s_eu.bin"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- touchscreen4: touchscreen@5d { +- compatible = "hid-over-i2c"; +- reg = <0x5d>; +- pinctrl-names = "default"; +- pinctrl-0 = <&open_touch>; +- +- interrupt-parent = <&pio>; +- interrupts = <155 IRQ_TYPE_EDGE_FALLING>; +- +- post-power-on-delay-ms = <10>; +- hid-descr-addr = <0x0001>; +- }; +-}; +- +-&mt6358_vcama2_reg { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "okay"; +- clock-frequency = <400000>; +- vbus-supply = <&mt6358_vcamio_reg>; +- +- eeprom@58 { +- compatible = "atmel,24c32"; +- reg = <0x58>; +- pagesize = <32>; +- vcc-supply = <&mt6358_vcama2_reg>; +- }; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pins>; +- status = "okay"; +- clock-frequency = <400000>; +- vbus-supply = <&mt6358_vcn18_reg>; +- +- eeprom@54 { +- compatible = "atmel,24c32"; +- reg = <0x54>; +- pagesize = <32>; +- vcc-supply = <&mt6358_vcn18_reg>; +- }; +-}; +- +-&pio { +- /* 192 lines */ +- gpio-line-names = +- "SPI_AP_EC_CS_L", +- "SPI_AP_EC_MOSI", +- "SPI_AP_EC_CLK", +- "I2S3_DO", +- "USB_PD_INT_ODL", +- "", +- "", +- "", +- "", +- "IT6505_HPD_L", +- "I2S3_TDM_D3", +- "SOC_I2C6_1V8_SCL", +- "SOC_I2C6_1V8_SDA", +- "DPI_D0", +- "DPI_D1", +- "DPI_D2", +- "DPI_D3", +- "DPI_D4", +- "DPI_D5", +- "DPI_D6", +- "DPI_D7", +- "DPI_D8", +- "DPI_D9", +- "DPI_D10", +- "DPI_D11", +- "DPI_HSYNC", +- "DPI_VSYNC", +- "DPI_DE", +- "DPI_CK", +- "AP_MSDC1_CLK", +- "AP_MSDC1_DAT3", +- "AP_MSDC1_CMD", +- "AP_MSDC1_DAT0", +- "AP_MSDC1_DAT2", +- "AP_MSDC1_DAT1", +- "", +- "", +- "", +- "", +- "", +- "", +- "OTG_EN", +- "DRVBUS", +- "DISP_PWM", +- "DSI_TE", +- "LCM_RST_1V8", +- "AP_CTS_WIFI_RTS", +- "AP_RTS_WIFI_CTS", +- "SOC_I2C5_1V8_SCL", +- "SOC_I2C5_1V8_SDA", +- "SOC_I2C3_1V8_SCL", +- "SOC_I2C3_1V8_SDA", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "SOC_I2C1_1V8_SDA", +- "SOC_I2C0_1V8_SDA", +- "SOC_I2C0_1V8_SCL", +- "SOC_I2C1_1V8_SCL", +- "AP_SPI_H1_MISO", +- "AP_SPI_H1_CS_L", +- "AP_SPI_H1_MOSI", +- "AP_SPI_H1_CLK", +- "I2S5_BCK", +- "I2S5_LRCK", +- "I2S5_DO", +- "BOOTBLOCK_EN_L", +- "MT8183_KPCOL0", +- "SPI_AP_EC_MISO", +- "UART_DBG_TX_AP_RX", +- "UART_AP_TX_DBG_RX", +- "I2S2_MCK", +- "I2S2_BCK", +- "CLK_5M_WCAM", +- "CLK_2M_UCAM", +- "I2S2_LRCK", +- "I2S2_DI", +- "SOC_I2C2_1V8_SCL", +- "SOC_I2C2_1V8_SDA", +- "SOC_I2C4_1V8_SCL", +- "SOC_I2C4_1V8_SDA", +- "", +- "SCL8", +- "SDA8", +- "FCAM_PWDN_L", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "I2S_PMIC", +- "", +- "", +- "", +- "", +- "", +- "", +- /* +- * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics +- * call it BIOS_FLASH_WP_R_L. +- */ +- "AP_FLASH_WP_L", +- "EC_AP_INT_ODL", +- "IT6505_INT_ODL", +- "H1_INT_OD_L", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "AP_SPI_FLASH_MISO", +- "AP_SPI_FLASH_CS_L", +- "AP_SPI_FLASH_MOSI", +- "AP_SPI_FLASH_CLK", +- "DA7219_IRQ", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- ""; +- +- ppvarp_lcd_en: ppvarp-lcd-en { +- pins1 { +- pinmux = ; +- output-low; +- }; +- }; +- +- ppvarn_lcd_en: ppvarn-lcd-en { +- pins1 { +- pinmux = ; +- output-low; +- }; +- }; +- +- pp1800_lcd_en: pp1800-lcd-en { +- pins1 { +- pinmux = ; +- output-low; +- }; +- }; +- +- open_touch: open_touch { +- irq_pin { +- pinmux = ; +- input-enable; +- bias-pull-up; +- }; +- +- rst_pin { +- pinmux = ; +- +- /* +- * The pen driver doesn't currently support driving +- * this reset line. By specifying output-high here +- * we're relying on the fact that this pin has a default +- * pulldown at boot (which makes sure the pen was in +- * reset if it was powered) and then we set it high here +- * to take it out of reset. Better would be if the pen +- * driver could control this and we could remove +- * "output-high" here. +- */ +- output-high; +- }; +- }; +-}; +- +-&qca_wifi { +- qcom,ath10k-calibration-variant = "LE_Krane"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui.dtsi +deleted file mode 100644 +index 8e9cf36a9a41..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-kukui.dtsi ++++ /dev/null +@@ -1,917 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (c) 2018 MediaTek Inc. +- * Author: Ben Ho +- * Erin Lo +- */ +- +-#include +-#include +-#include "mt8183.dtsi" +-#include "mt6358.dtsi" +- +-/ { +- aliases { +- serial0 = &uart0; +- mmc0 = &mmc0; +- mmc1 = &mmc1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- backlight_lcd0: backlight_lcd0 { +- compatible = "pwm-backlight"; +- pwms = <&pwm0 0 500000>; +- power-supply = <&bl_pp5000>; +- enable-gpios = <&pio 176 0>; +- brightness-levels = <0 1023>; +- num-interpolated-steps = <1023>; +- default-brightness-level = <576>; +- status = "okay"; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x80000000>; +- }; +- +- clk32k: oscillator1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "clk32k"; +- }; +- +- it6505_pp18_reg: regulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "it6505_pp18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&pio 178 0>; +- enable-active-high; +- }; +- +- lcd_pp3300: regulator1 { +- compatible = "regulator-fixed"; +- regulator-name = "lcd_pp3300"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- bl_pp5000: regulator2 { +- compatible = "regulator-fixed"; +- regulator-name = "bl_pp5000"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- mmc1_fixed_power: regulator3 { +- compatible = "regulator-fixed"; +- regulator-name = "mmc1_power"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- mmc1_fixed_io: regulator4 { +- compatible = "regulator-fixed"; +- regulator-name = "mmc1_io"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pp1800_alw: regulator5 { +- compatible = "regulator-fixed"; +- regulator-name = "pp1800_alw"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pp3300_alw: regulator6 { +- compatible = "regulator-fixed"; +- regulator-name = "pp3300_alw"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- reserved_memory: reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- scp_mem_reserved: scp_mem_region { +- compatible = "shared-dma-pool"; +- reg = <0 0x50000000 0 0x2900000>; +- no-map; +- }; +- }; +- +- max98357a: codec0 { +- compatible = "maxim,max98357a"; +- sdmode-gpios = <&pio 175 0>; +- }; +- +- btsco: codec1 { +- compatible = "linux,bt-sco"; +- }; +- +- wifi_pwrseq: wifi-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_pins_pwrseq>; +- +- /* Toggle WIFI_ENABLE to reset the chip. */ +- reset-gpios = <&pio 119 1>; +- }; +- +- wifi_wakeup: wifi-wakeup { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_pins_wakeup>; +- +- wowlan { +- label = "Wake on WiFi"; +- gpios = <&pio 113 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- tboard_thermistor1: thermal-sensor1 { +- compatible = "generic-adc-thermal"; +- #thermal-sensor-cells = <0>; +- io-channels = <&auxadc 0>; +- io-channel-names = "sensor-channel"; +- temperature-lookup-table = < (-5000) 4241 +- 0 4063 +- 5000 3856 +- 10000 3621 +- 15000 3364 +- 20000 3091 +- 25000 2810 +- 30000 2526 +- 35000 2247 +- 40000 1982 +- 45000 1734 +- 50000 1507 +- 55000 1305 +- 60000 1122 +- 65000 964 +- 70000 827 +- 75000 710 +- 80000 606 +- 85000 519 +- 90000 445 +- 95000 382 +- 100000 330 +- 105000 284 +- 110000 245 +- 115000 213 +- 120000 183 +- 125000 161>; +- }; +- +- tboard_thermistor2: thermal-sensor2 { +- compatible = "generic-adc-thermal"; +- #thermal-sensor-cells = <0>; +- io-channels = <&auxadc 1>; +- io-channel-names = "sensor-channel"; +- temperature-lookup-table = < (-5000) 4241 +- 0 4063 +- 5000 3856 +- 10000 3621 +- 15000 3364 +- 20000 3091 +- 25000 2810 +- 30000 2526 +- 35000 2247 +- 40000 1982 +- 45000 1734 +- 50000 1507 +- 55000 1305 +- 60000 1122 +- 65000 964 +- 70000 827 +- 75000 710 +- 80000 606 +- 85000 519 +- 90000 445 +- 95000 382 +- 100000 330 +- 105000 284 +- 110000 245 +- 115000 213 +- 120000 183 +- 125000 161>; +- }; +-}; +- +-&auxadc { +- status = "okay"; +-}; +- +-&cpu0 { +- proc-supply = <&mt6358_vproc12_reg>; +-}; +- +-&cpu1 { +- proc-supply = <&mt6358_vproc12_reg>; +-}; +- +-&cpu2 { +- proc-supply = <&mt6358_vproc12_reg>; +-}; +- +-&cpu3 { +- proc-supply = <&mt6358_vproc12_reg>; +-}; +- +-&cpu4 { +- proc-supply = <&mt6358_vproc11_reg>; +-}; +- +-&cpu5 { +- proc-supply = <&mt6358_vproc11_reg>; +-}; +- +-&cpu6 { +- proc-supply = <&mt6358_vproc11_reg>; +-}; +- +-&cpu7 { +- proc-supply = <&mt6358_vproc11_reg>; +-}; +- +-&dsi0 { +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- panel: panel@0 { +- /* compatible will be set in board dts */ +- reg = <0>; +- enable-gpios = <&pio 45 0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&panel_pins_default>; +- avdd-supply = <&ppvarn_lcd>; +- avee-supply = <&ppvarp_lcd>; +- pp1800-supply = <&pp1800_lcd>; +- backlight = <&backlight_lcd0>; +- port { +- panel_in: endpoint { +- remote-endpoint = <&dsi_out>; +- }; +- }; +- }; +- +- ports { +- port { +- dsi_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&gpu { +- mali-supply = <&mt6358_vgpu_reg>; +- sram-supply = <&mt6358_vsram_gpu_reg>; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +- clock-frequency = <400000>; +- #address-cells = <1>; +- #size-cells = <0>; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- status = "okay"; +- clock-frequency = <100000>; +- #address-cells = <1>; +- #size-cells = <0>; +-}; +- +-&i2c5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_pins>; +- status = "okay"; +- clock-frequency = <100000>; +- #address-cells = <1>; +- #size-cells = <0>; +-}; +- +-&i2c6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c6_pins>; +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&mipi_tx0 { +- status = "okay"; +-}; +- +-&mmc0 { +- status = "okay"; +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc0_pins_default>; +- pinctrl-1 = <&mmc0_pins_uhs>; +- bus-width = <8>; +- max-frequency = <200000000>; +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- cap-mmc-hw-reset; +- no-sdio; +- no-sd; +- hs400-ds-delay = <0x12814>; +- vmmc-supply = <&mt6358_vemc_reg>; +- vqmmc-supply = <&mt6358_vio18_reg>; +- assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; +- assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; +- non-removable; +-}; +- +-&mmc1 { +- status = "okay"; +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc1_pins_default>; +- pinctrl-1 = <&mmc1_pins_uhs>; +- vmmc-supply = <&mmc1_fixed_power>; +- vqmmc-supply = <&mmc1_fixed_io>; +- mmc-pwrseq = <&wifi_pwrseq>; +- bus-width = <4>; +- max-frequency = <200000000>; +- drv-type = <2>; +- cap-sd-highspeed; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- keep-power-in-suspend; +- enable-sdio-wakeup; +- cap-sdio-irq; +- non-removable; +- no-mmc; +- no-sd; +- assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>; +- assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- qca_wifi: qca-wifi@1 { +- compatible = "qcom,ath10k"; +- reg = <1>; +- }; +-}; +- +-&mt6358_vdram2_reg { +- regulator-always-on; +-}; +- +-&mt6358codec { +- Avdd-supply = <&mt6358_vaud28_reg>; +-}; +- +-&mt6358_vsim1_reg { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +-}; +- +-&mt6358_vsim2_reg { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +-}; +- +-&pio { +- bt_pins: bt-pins { +- pins_bt_en { +- pinmux = ; +- output-low; +- }; +- }; +- +- ec_ap_int_odl: ec_ap_int_odl { +- pins1 { +- pinmux = ; +- input-enable; +- bias-pull-up; +- }; +- }; +- +- h1_int_od_l: h1_int_od_l { +- pins1 { +- pinmux = ; +- input-enable; +- }; +- }; +- +- i2c0_pins: i2c0 { +- pins_bus { +- pinmux = , +- ; +- mediatek,pull-up-adv = <3>; +- mediatek,drive-strength-adv = <00>; +- }; +- }; +- +- i2c1_pins: i2c1 { +- pins_bus { +- pinmux = , +- ; +- mediatek,pull-up-adv = <3>; +- mediatek,drive-strength-adv = <00>; +- }; +- }; +- +- i2c2_pins: i2c2 { +- pins_bus { +- pinmux = , +- ; +- bias-disable; +- mediatek,drive-strength-adv = <00>; +- }; +- }; +- +- i2c3_pins: i2c3 { +- pins_bus { +- pinmux = , +- ; +- mediatek,pull-up-adv = <3>; +- mediatek,drive-strength-adv = <00>; +- }; +- }; +- +- i2c4_pins: i2c4 { +- pins_bus { +- pinmux = , +- ; +- bias-disable; +- mediatek,drive-strength-adv = <00>; +- }; +- }; +- +- i2c5_pins: i2c5 { +- pins_bus { +- pinmux = , +- ; +- mediatek,pull-up-adv = <3>; +- mediatek,drive-strength-adv = <00>; +- }; +- }; +- +- i2c6_pins: i2c6 { +- pins_bus { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- mmc0_pins_default: mmc0-pins-default { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- ; +- input-enable; +- drive-strength = ; +- mediatek,pull-up-adv = <01>; +- }; +- +- pins_clk { +- pinmux = ; +- drive-strength = ; +- mediatek,pull-down-adv = <10>; +- }; +- +- pins_rst { +- pinmux = ; +- drive-strength = ; +- mediatek,pull-down-adv = <01>; +- }; +- }; +- +- mmc0_pins_uhs: mmc0-pins-uhs { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- ; +- input-enable; +- drive-strength = ; +- mediatek,pull-up-adv = <01>; +- }; +- +- pins_clk { +- pinmux = ; +- drive-strength = ; +- mediatek,pull-down-adv = <10>; +- }; +- +- pins_ds { +- pinmux = ; +- drive-strength = ; +- mediatek,pull-down-adv = <10>; +- }; +- +- pins_rst { +- pinmux = ; +- drive-strength = ; +- mediatek,pull-up-adv = <01>; +- }; +- }; +- +- mmc1_pins_default: mmc1-pins-default { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- ; +- input-enable; +- mediatek,pull-up-adv = <10>; +- }; +- +- pins_clk { +- pinmux = ; +- input-enable; +- mediatek,pull-down-adv = <10>; +- }; +- }; +- +- mmc1_pins_uhs: mmc1-pins-uhs { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- ; +- drive-strength = ; +- input-enable; +- mediatek,pull-up-adv = <10>; +- }; +- +- pins_clk { +- pinmux = ; +- drive-strength = ; +- mediatek,pull-down-adv = <10>; +- input-enable; +- }; +- }; +- +- panel_pins_default: panel_pins_default { +- panel_reset { +- pinmux = ; +- output-low; +- bias-pull-up; +- }; +- }; +- +- pwm0_pin_default: pwm0_pin_default { +- pins1 { +- pinmux = ; +- output-high; +- bias-pull-up; +- }; +- pins2 { +- pinmux = ; +- }; +- }; +- +- scp_pins: scp { +- pins_scp_uart { +- pinmux = , +- ; +- }; +- }; +- +- spi0_pins: spi0 { +- pins_spi{ +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- }; +- +- spi1_pins: spi1 { +- pins_spi{ +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- }; +- +- spi2_pins: spi2 { +- pins_spi{ +- pinmux = , +- , +- ; +- bias-disable; +- }; +- pins_spi_mi { +- pinmux = ; +- mediatek,pull-down-adv = <00>; +- }; +- }; +- +- spi3_pins: spi3 { +- pins_spi{ +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- }; +- +- spi4_pins: spi4 { +- pins_spi{ +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- }; +- +- spi5_pins: spi5 { +- pins_spi{ +- pinmux = , +- , +- , +- ; +- bias-disable; +- }; +- }; +- +- uart0_pins_default: uart0-pins-default { +- pins_rx { +- pinmux = ; +- input-enable; +- bias-pull-up; +- }; +- pins_tx { +- pinmux = ; +- }; +- }; +- +- uart1_pins_default: uart1-pins-default { +- pins_rx { +- pinmux = ; +- input-enable; +- bias-pull-up; +- }; +- pins_tx { +- pinmux = ; +- }; +- pins_rts { +- pinmux = ; +- output-enable; +- }; +- pins_cts { +- pinmux = ; +- input-enable; +- }; +- }; +- +- uart1_pins_sleep: uart1-pins-sleep { +- pins_rx { +- pinmux = ; +- input-enable; +- bias-pull-up; +- }; +- pins_tx { +- pinmux = ; +- }; +- pins_rts { +- pinmux = ; +- output-enable; +- }; +- pins_cts { +- pinmux = ; +- input-enable; +- }; +- }; +- +- wifi_pins_pwrseq: wifi-pins-pwrseq { +- pins_wifi_enable { +- pinmux = ; +- output-low; +- }; +- }; +- +- wifi_pins_wakeup: wifi-pins-wakeup { +- pins_wifi_wakeup { +- pinmux = ; +- input-enable; +- }; +- }; +-}; +- +-&pwm0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin_default>; +-}; +- +-&scp { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&scp_pins>; +- +- cros_ec { +- compatible = "google,cros-ec-rpmsg"; +- mtk,rpmsg-name = "cros-ec-rpmsg"; +- }; +-}; +- +-&mfg { +- domain-supply = <&mt6358_vgpu_reg>; +-}; +- +-&soc_data { +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins>; +- mediatek,pad-select = <0>; +- status = "okay"; +- cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>; +- +- cr50@0 { +- compatible = "google,cr50"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&h1_int_od_l>; +- interrupt-parent = <&pio>; +- interrupts = <153 IRQ_TYPE_EDGE_RISING>; +- }; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins>; +- mediatek,pad-select = <0>; +- status = "okay"; +- +- w25q64dw: spi-flash@0 { +- compatible = "winbond,w25q64dw", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <25000000>; +- }; +-}; +- +-&spi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pins>; +- mediatek,pad-select = <0>; +- status = "okay"; +- +- cros_ec: cros-ec@0 { +- compatible = "google,cros-ec-spi"; +- reg = <0>; +- spi-max-frequency = <3000000>; +- interrupt-parent = <&pio>; +- interrupts = <151 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ec_ap_int_odl>; +- +- i2c_tunnel: i2c-tunnel { +- compatible = "google,cros-ec-i2c-tunnel"; +- google,remote-bus = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- usbc_extcon: extcon0 { +- compatible = "google,extcon-usbc-cros-ec"; +- google,usb-port-id = <0>; +- }; +- +- cbas { +- compatible = "google,cros-cbas"; +- }; +- }; +-}; +- +-&spi3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi3_pins>; +- mediatek,pad-select = <0>; +- status = "disabled"; +-}; +- +-&spi4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi4_pins>; +- mediatek,pad-select = <0>; +- status = "disabled"; +-}; +- +-&spi5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi5_pins>; +- mediatek,pad-select = <0>; +- status = "disabled"; +-}; +- +-&ssusb { +- dr_mode = "host"; +- wakeup-source; +- vusb33-supply = <&mt6358_vusb_reg>; +- status = "okay"; +-}; +- +-&thermal_zones { +- tboard1 { +- polling-delay = <1000>; /* milliseconds */ +- polling-delay-passive = <0>; /* milliseconds */ +- thermal-sensors = <&tboard_thermistor1>; +- }; +- +- tboard2 { +- polling-delay = <1000>; /* milliseconds */ +- polling-delay-passive = <0>; /* milliseconds */ +- thermal-sensors = <&tboard_thermistor2>; +- }; +-}; +- +-&u3phy { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins_default>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&uart1_pins_default>; +- pinctrl-1 = <&uart1_pins_sleep>; +- status = "okay"; +- interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>, +- <&pio 121 IRQ_TYPE_EDGE_FALLING>; +- +- bluetooth: bluetooth { +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_pins>; +- status = "okay"; +- compatible = "qcom,qca6174-bt"; +- enable-gpios = <&pio 120 0>; +- clocks = <&clk32k>; +- firmware-name = "nvm_00440302_i2s.bin"; +- }; +-}; +- +-&usb_host { +- #address-cells = <1>; +- #size-cells = <0>; +- vusb33-supply = <&mt6358_vusb_reg>; +- status = "okay"; +- +- hub@1 { +- compatible = "usb5e3,610"; +- reg = <1>; +- }; +-}; +- +-#include +-#include +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-pumpkin.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-pumpkin.dts +deleted file mode 100644 +index ee912825cfc6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-pumpkin.dts ++++ /dev/null +@@ -1,383 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2021 BayLibre, SAS. +- * Author: Fabien Parent +- */ +- +-/dts-v1/; +- +-#include +-#include "mt8183.dtsi" +-#include "mt6358.dtsi" +- +-/ { +- model = "Pumpkin MT8183"; +- compatible = "mediatek,mt8183-pumpkin", "mediatek,mt8183"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x80000000>; +- }; +- +- chosen { +- stdout-path = "serial0:921600n8"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- scp_mem_reserved: scp_mem_region@50000000 { +- compatible = "shared-dma-pool"; +- reg = <0 0x50000000 0 0x2900000>; +- no-map; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-red { +- label = "red"; +- gpios = <&pio 155 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- led-green { +- label = "green"; +- gpios = <&pio 156 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- ntc { +- compatible = "murata,ncp03wf104"; +- pullup-uv = <1800000>; +- pullup-ohm = <390000>; +- pulldown-ohm = <0>; +- io-channels = <&auxadc 0>; +- }; +-}; +- +-&auxadc { +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&mt6358_vgpu_reg>; +- sram-supply = <&mt6358_vsram_gpu_reg>; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_pins_0>; +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_pins_1>; +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_pins_2>; +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_pins_3>; +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_pins_4>; +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&i2c5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c_pins_5>; +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&i2c6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c6_pins>; +- status = "okay"; +- clock-frequency = <100000>; +-}; +- +-&mmc0 { +- status = "okay"; +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc0_pins_default>; +- pinctrl-1 = <&mmc0_pins_uhs>; +- bus-width = <8>; +- max-frequency = <200000000>; +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- cap-mmc-hw-reset; +- no-sdio; +- no-sd; +- hs400-ds-delay = <0x12814>; +- vmmc-supply = <&mt6358_vemc_reg>; +- vqmmc-supply = <&mt6358_vio18_reg>; +- assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; +- assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; +- non-removable; +-}; +- +-&mmc1 { +- status = "okay"; +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc1_pins_default>; +- pinctrl-1 = <&mmc1_pins_uhs>; +- bus-width = <4>; +- max-frequency = <200000000>; +- cap-sd-highspeed; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- cap-sdio-irq; +- no-mmc; +- no-sd; +- vmmc-supply = <&mt6358_vmch_reg>; +- vqmmc-supply = <&mt6358_vmc_reg>; +- keep-power-in-suspend; +- enable-sdio-wakeup; +- non-removable; +-}; +- +-&pio { +- i2c_pins_0: i2c0 { +- pins_i2c{ +- pinmux = , +- ; +- mediatek,pull-up-adv = <3>; +- mediatek,drive-strength-adv = <00>; +- }; +- }; +- +- i2c_pins_1: i2c1 { +- pins_i2c{ +- pinmux = , +- ; +- mediatek,pull-up-adv = <3>; +- mediatek,drive-strength-adv = <00>; +- }; +- }; +- +- i2c_pins_2: i2c2 { +- pins_i2c{ +- pinmux = , +- ; +- mediatek,pull-up-adv = <3>; +- mediatek,drive-strength-adv = <00>; +- }; +- }; +- +- i2c_pins_3: i2c3 { +- pins_i2c{ +- pinmux = , +- ; +- mediatek,pull-up-adv = <3>; +- mediatek,drive-strength-adv = <00>; +- }; +- }; +- +- i2c_pins_4: i2c4 { +- pins_i2c{ +- pinmux = , +- ; +- mediatek,pull-up-adv = <3>; +- mediatek,drive-strength-adv = <00>; +- }; +- }; +- +- i2c_pins_5: i2c5 { +- pins_i2c{ +- pinmux = , +- ; +- mediatek,pull-up-adv = <3>; +- mediatek,drive-strength-adv = <00>; +- }; +- }; +- +- i2c6_pins: i2c6 { +- pins_cmd_dat { +- pinmux = , +- ; +- mediatek,pull-up-adv = <3>; +- }; +- }; +- +- mmc0_pins_default: mmc0-pins-default { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- ; +- input-enable; +- drive-strength = ; +- mediatek,pull-up-adv = <01>; +- }; +- +- pins_clk { +- pinmux = ; +- drive-strength = ; +- mediatek,pull-down-adv = <10>; +- }; +- +- pins_rst { +- pinmux = ; +- drive-strength = ; +- mediatek,pull-down-adv = <01>; +- }; +- }; +- +- mmc0_pins_uhs: mmc0-pins-uhs { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- ; +- input-enable; +- drive-strength = ; +- mediatek,pull-up-adv = <01>; +- }; +- +- pins_clk { +- pinmux = ; +- drive-strength = ; +- mediatek,pull-down-adv = <10>; +- }; +- +- pins_ds { +- pinmux = ; +- drive-strength = ; +- mediatek,pull-down-adv = <10>; +- }; +- +- pins_rst { +- pinmux = ; +- drive-strength = ; +- mediatek,pull-up-adv = <01>; +- }; +- }; +- +- mmc1_pins_default: mmc1-pins-default { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- ; +- input-enable; +- mediatek,pull-up-adv = <10>; +- }; +- +- pins_clk { +- pinmux = ; +- input-enable; +- mediatek,pull-down-adv = <10>; +- }; +- +- pins_pmu { +- pinmux = ; +- output-high; +- }; +- }; +- +- mmc1_pins_uhs: mmc1-pins-uhs { +- pins_cmd_dat { +- pinmux = , +- , +- , +- , +- ; +- drive-strength = ; +- input-enable; +- mediatek,pull-up-adv = <10>; +- }; +- +- pins_clk { +- pinmux = ; +- drive-strength = ; +- mediatek,pull-down-adv = <10>; +- input-enable; +- }; +- }; +-}; +- +-&mfg { +- domain-supply = <&mt6358_vgpu_reg>; +-}; +- +-&cpu0 { +- proc-supply = <&mt6358_vproc12_reg>; +-}; +- +-&cpu1 { +- proc-supply = <&mt6358_vproc12_reg>; +-}; +- +-&cpu2 { +- proc-supply = <&mt6358_vproc12_reg>; +-}; +- +-&cpu3 { +- proc-supply = <&mt6358_vproc12_reg>; +-}; +- +-&cpu4 { +- proc-supply = <&mt6358_vproc11_reg>; +-}; +- +-&cpu5 { +- proc-supply = <&mt6358_vproc11_reg>; +-}; +- +-&cpu6 { +- proc-supply = <&mt6358_vproc11_reg>; +-}; +- +-&cpu7 { +- proc-supply = <&mt6358_vproc11_reg>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&scp { +- status = "okay"; +-}; +- +-&dsi0 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt8183.dtsi +deleted file mode 100644 +index 409cf827970c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8183.dtsi ++++ /dev/null +@@ -1,1490 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (c) 2018 MediaTek Inc. +- * Author: Ben Ho +- * Erin Lo +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "mediatek,mt8183"; +- interrupt-parent = <&sysirq>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c7; +- i2c8 = &i2c8; +- i2c9 = &i2c9; +- i2c10 = &i2c10; +- i2c11 = &i2c11; +- ovl0 = &ovl0; +- ovl-2l0 = &ovl_2l0; +- ovl-2l1 = &ovl_2l1; +- rdma0 = &rdma0; +- rdma1 = &rdma1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- core2 { +- cpu = <&cpu2>; +- }; +- core3 { +- cpu = <&cpu3>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&cpu4>; +- }; +- core1 { +- cpu = <&cpu5>; +- }; +- core2 { +- cpu = <&cpu6>; +- }; +- core3 { +- cpu = <&cpu7>; +- }; +- }; +- }; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x000>; +- enable-method = "psci"; +- capacity-dmips-mhz = <741>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; +- dynamic-power-coefficient = <84>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x001>; +- enable-method = "psci"; +- capacity-dmips-mhz = <741>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; +- dynamic-power-coefficient = <84>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x002>; +- enable-method = "psci"; +- capacity-dmips-mhz = <741>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; +- dynamic-power-coefficient = <84>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x003>; +- enable-method = "psci"; +- capacity-dmips-mhz = <741>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; +- dynamic-power-coefficient = <84>; +- #cooling-cells = <2>; +- }; +- +- cpu4: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a73"; +- reg = <0x100>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; +- dynamic-power-coefficient = <211>; +- #cooling-cells = <2>; +- }; +- +- cpu5: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a73"; +- reg = <0x101>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; +- dynamic-power-coefficient = <211>; +- #cooling-cells = <2>; +- }; +- +- cpu6: cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a73"; +- reg = <0x102>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; +- dynamic-power-coefficient = <211>; +- #cooling-cells = <2>; +- }; +- +- cpu7: cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a73"; +- reg = <0x103>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; +- dynamic-power-coefficient = <211>; +- #cooling-cells = <2>; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP: cpu-sleep { +- compatible = "arm,idle-state"; +- local-timer-stop; +- arm,psci-suspend-param = <0x00010001>; +- entry-latency-us = <200>; +- exit-latency-us = <200>; +- min-residency-us = <800>; +- }; +- +- CLUSTER_SLEEP0: cluster-sleep-0 { +- compatible = "arm,idle-state"; +- local-timer-stop; +- arm,psci-suspend-param = <0x01010001>; +- entry-latency-us = <250>; +- exit-latency-us = <400>; +- min-residency-us = <1000>; +- }; +- CLUSTER_SLEEP1: cluster-sleep-1 { +- compatible = "arm,idle-state"; +- local-timer-stop; +- arm,psci-suspend-param = <0x01010001>; +- entry-latency-us = <250>; +- exit-latency-us = <400>; +- min-residency-us = <1300>; +- }; +- }; +- }; +- +- gpu_opp_table: opp_table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <625000>, <850000>; +- }; +- +- opp-320000000 { +- opp-hz = /bits/ 64 <320000000>; +- opp-microvolt = <631250>, <850000>; +- }; +- +- opp-340000000 { +- opp-hz = /bits/ 64 <340000000>; +- opp-microvolt = <637500>, <850000>; +- }; +- +- opp-360000000 { +- opp-hz = /bits/ 64 <360000000>; +- opp-microvolt = <643750>, <850000>; +- }; +- +- opp-380000000 { +- opp-hz = /bits/ 64 <380000000>; +- opp-microvolt = <650000>, <850000>; +- }; +- +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <656250>, <850000>; +- }; +- +- opp-420000000 { +- opp-hz = /bits/ 64 <420000000>; +- opp-microvolt = <662500>, <850000>; +- }; +- +- opp-460000000 { +- opp-hz = /bits/ 64 <460000000>; +- opp-microvolt = <675000>, <850000>; +- }; +- +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <687500>, <850000>; +- }; +- +- opp-540000000 { +- opp-hz = /bits/ 64 <540000000>; +- opp-microvolt = <700000>, <850000>; +- }; +- +- opp-580000000 { +- opp-hz = /bits/ 64 <580000000>; +- opp-microvolt = <712500>, <850000>; +- }; +- +- opp-620000000 { +- opp-hz = /bits/ 64 <620000000>; +- opp-microvolt = <725000>, <850000>; +- }; +- +- opp-653000000 { +- opp-hz = /bits/ 64 <653000000>; +- opp-microvolt = <743750>, <850000>; +- }; +- +- opp-698000000 { +- opp-hz = /bits/ 64 <698000000>; +- opp-microvolt = <768750>, <868750>; +- }; +- +- opp-743000000 { +- opp-hz = /bits/ 64 <743000000>; +- opp-microvolt = <793750>, <893750>; +- }; +- +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <825000>, <925000>; +- }; +- }; +- +- pmu-a53 { +- compatible = "arm,cortex-a53-pmu"; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- +- pmu-a73 { +- compatible = "arm,cortex-a73-pmu"; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- clk26m: oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- clock-output-names = "clk26m"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- }; +- +- soc { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "simple-bus"; +- ranges; +- +- soc_data: soc_data@8000000 { +- compatible = "mediatek,mt8183-efuse", +- "mediatek,efuse"; +- reg = <0 0x08000000 0 0x0010>; +- #address-cells = <1>; +- #size-cells = <1>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@c000000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <4>; +- interrupt-parent = <&gic>; +- interrupt-controller; +- reg = <0 0x0c000000 0 0x40000>, /* GICD */ +- <0 0x0c100000 0 0x200000>, /* GICR */ +- <0 0x0c400000 0 0x2000>, /* GICC */ +- <0 0x0c410000 0 0x1000>, /* GICH */ +- <0 0x0c420000 0 0x2000>; /* GICV */ +- +- interrupts = ; +- ppi-partitions { +- ppi_cluster0: interrupt-partition-0 { +- affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; +- }; +- ppi_cluster1: interrupt-partition-1 { +- affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; +- }; +- }; +- }; +- +- mcucfg: syscon@c530000 { +- compatible = "mediatek,mt8183-mcucfg", "syscon"; +- reg = <0 0x0c530000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- sysirq: interrupt-controller@c530a80 { +- compatible = "mediatek,mt8183-sysirq", +- "mediatek,mt6577-sysirq"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0 0x0c530a80 0 0x50>; +- }; +- +- topckgen: syscon@10000000 { +- compatible = "mediatek,mt8183-topckgen", "syscon"; +- reg = <0 0x10000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- infracfg: syscon@10001000 { +- compatible = "mediatek,mt8183-infracfg", "syscon"; +- reg = <0 0x10001000 0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- pericfg: syscon@10003000 { +- compatible = "mediatek,mt8183-pericfg", "syscon"; +- reg = <0 0x10003000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- pio: pinctrl@10005000 { +- compatible = "mediatek,mt8183-pinctrl"; +- reg = <0 0x10005000 0 0x1000>, +- <0 0x11f20000 0 0x1000>, +- <0 0x11e80000 0 0x1000>, +- <0 0x11e70000 0 0x1000>, +- <0 0x11e90000 0 0x1000>, +- <0 0x11d30000 0 0x1000>, +- <0 0x11d20000 0 0x1000>, +- <0 0x11c50000 0 0x1000>, +- <0 0x11f30000 0 0x1000>, +- <0 0x1000b000 0 0x1000>; +- reg-names = "iocfg0", "iocfg1", "iocfg2", +- "iocfg3", "iocfg4", "iocfg5", +- "iocfg6", "iocfg7", "iocfg8", +- "eint"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pio 0 0 192>; +- interrupt-controller; +- interrupts = ; +- #interrupt-cells = <2>; +- }; +- +- scpsys: syscon@10006000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0 0x10006000 0 0x1000>; +- #power-domain-cells = <1>; +- +- /* System Power Manager */ +- spm: power-controller { +- compatible = "mediatek,mt8183-power-controller"; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <1>; +- +- /* power domain of the SoC */ +- power-domain@MT8183_POWER_DOMAIN_AUDIO { +- reg = ; +- clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, +- <&infracfg CLK_INFRA_AUDIO>, +- <&infracfg CLK_INFRA_AUDIO_26M_BCLK>; +- clock-names = "audio", "audio1", "audio2"; +- #power-domain-cells = <0>; +- }; +- +- power-domain@MT8183_POWER_DOMAIN_CONN { +- reg = ; +- mediatek,infracfg = <&infracfg>; +- #power-domain-cells = <0>; +- }; +- +- power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { +- reg = ; +- clocks = <&topckgen CLK_TOP_MUX_MFG>; +- clock-names = "mfg"; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <1>; +- +- mfg: power-domain@MT8183_POWER_DOMAIN_MFG { +- reg = ; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <1>; +- +- power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 { +- reg = ; +- #power-domain-cells = <0>; +- }; +- +- power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 { +- reg = ; +- #power-domain-cells = <0>; +- }; +- +- power-domain@MT8183_POWER_DOMAIN_MFG_2D { +- reg = ; +- mediatek,infracfg = <&infracfg>; +- #power-domain-cells = <0>; +- }; +- }; +- }; +- +- power-domain@MT8183_POWER_DOMAIN_DISP { +- reg = ; +- clocks = <&topckgen CLK_TOP_MUX_MM>, +- <&mmsys CLK_MM_SMI_COMMON>, +- <&mmsys CLK_MM_SMI_LARB0>, +- <&mmsys CLK_MM_SMI_LARB1>, +- <&mmsys CLK_MM_GALS_COMM0>, +- <&mmsys CLK_MM_GALS_COMM1>, +- <&mmsys CLK_MM_GALS_CCU2MM>, +- <&mmsys CLK_MM_GALS_IPU12MM>, +- <&mmsys CLK_MM_GALS_IMG2MM>, +- <&mmsys CLK_MM_GALS_CAM2MM>, +- <&mmsys CLK_MM_GALS_IPU2MM>; +- clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3", +- "mm-4", "mm-5", "mm-6", "mm-7", +- "mm-8", "mm-9"; +- mediatek,infracfg = <&infracfg>; +- mediatek,smi = <&smi_common>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <1>; +- +- power-domain@MT8183_POWER_DOMAIN_CAM { +- reg = ; +- clocks = <&topckgen CLK_TOP_MUX_CAM>, +- <&camsys CLK_CAM_LARB6>, +- <&camsys CLK_CAM_LARB3>, +- <&camsys CLK_CAM_SENINF>, +- <&camsys CLK_CAM_CAMSV0>, +- <&camsys CLK_CAM_CAMSV1>, +- <&camsys CLK_CAM_CAMSV2>, +- <&camsys CLK_CAM_CCU>; +- clock-names = "cam", "cam-0", "cam-1", +- "cam-2", "cam-3", "cam-4", +- "cam-5", "cam-6"; +- mediatek,infracfg = <&infracfg>; +- mediatek,smi = <&smi_common>; +- #power-domain-cells = <0>; +- }; +- +- power-domain@MT8183_POWER_DOMAIN_ISP { +- reg = ; +- clocks = <&topckgen CLK_TOP_MUX_IMG>, +- <&imgsys CLK_IMG_LARB5>, +- <&imgsys CLK_IMG_LARB2>; +- clock-names = "isp", "isp-0", "isp-1"; +- mediatek,infracfg = <&infracfg>; +- mediatek,smi = <&smi_common>; +- #power-domain-cells = <0>; +- }; +- +- power-domain@MT8183_POWER_DOMAIN_VDEC { +- reg = ; +- mediatek,smi = <&smi_common>; +- #power-domain-cells = <0>; +- }; +- +- power-domain@MT8183_POWER_DOMAIN_VENC { +- reg = ; +- mediatek,smi = <&smi_common>; +- #power-domain-cells = <0>; +- }; +- +- power-domain@MT8183_POWER_DOMAIN_VPU_TOP { +- reg = ; +- clocks = <&topckgen CLK_TOP_MUX_IPU_IF>, +- <&topckgen CLK_TOP_MUX_DSP>, +- <&ipu_conn CLK_IPU_CONN_IPU>, +- <&ipu_conn CLK_IPU_CONN_AHB>, +- <&ipu_conn CLK_IPU_CONN_AXI>, +- <&ipu_conn CLK_IPU_CONN_ISP>, +- <&ipu_conn CLK_IPU_CONN_CAM_ADL>, +- <&ipu_conn CLK_IPU_CONN_IMG_ADL>; +- clock-names = "vpu", "vpu1", "vpu-0", "vpu-1", +- "vpu-2", "vpu-3", "vpu-4", "vpu-5"; +- mediatek,infracfg = <&infracfg>; +- mediatek,smi = <&smi_common>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <1>; +- +- power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 { +- reg = ; +- clocks = <&topckgen CLK_TOP_MUX_DSP1>; +- clock-names = "vpu2"; +- mediatek,infracfg = <&infracfg>; +- #power-domain-cells = <0>; +- }; +- +- power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 { +- reg = ; +- clocks = <&topckgen CLK_TOP_MUX_DSP2>; +- clock-names = "vpu3"; +- mediatek,infracfg = <&infracfg>; +- #power-domain-cells = <0>; +- }; +- }; +- }; +- }; +- }; +- +- watchdog: watchdog@10007000 { +- compatible = "mediatek,mt8183-wdt"; +- reg = <0 0x10007000 0 0x100>; +- #reset-cells = <1>; +- }; +- +- apmixedsys: syscon@1000c000 { +- compatible = "mediatek,mt8183-apmixedsys", "syscon"; +- reg = <0 0x1000c000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- pwrap: pwrap@1000d000 { +- compatible = "mediatek,mt8183-pwrap"; +- reg = <0 0x1000d000 0 0x1000>; +- reg-names = "pwrap"; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, +- <&infracfg CLK_INFRA_PMIC_AP>; +- clock-names = "spi", "wrap"; +- }; +- +- scp: scp@10500000 { +- compatible = "mediatek,mt8183-scp"; +- reg = <0 0x10500000 0 0x80000>, +- <0 0x105c0000 0 0x19080>; +- reg-names = "sram", "cfg"; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_SCPSYS>; +- clock-names = "main"; +- memory-region = <&scp_mem_reserved>; +- status = "disabled"; +- }; +- +- systimer: timer@10017000 { +- compatible = "mediatek,mt8183-timer", +- "mediatek,mt6765-timer"; +- reg = <0 0x10017000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_CLK13M>; +- clock-names = "clk13m"; +- }; +- +- iommu: iommu@10205000 { +- compatible = "mediatek,mt8183-m4u"; +- reg = <0 0x10205000 0 0x1000>; +- interrupts = ; +- mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 +- &larb4 &larb5 &larb6>; +- #iommu-cells = <1>; +- }; +- +- gce: mailbox@10238000 { +- compatible = "mediatek,mt8183-gce"; +- reg = <0 0x10238000 0 0x4000>; +- interrupts = ; +- #mbox-cells = <2>; +- clocks = <&infracfg CLK_INFRA_GCE>; +- clock-names = "gce"; +- }; +- +- auxadc: auxadc@11001000 { +- compatible = "mediatek,mt8183-auxadc", +- "mediatek,mt8173-auxadc"; +- reg = <0 0x11001000 0 0x1000>; +- clocks = <&infracfg CLK_INFRA_AUXADC>; +- clock-names = "main"; +- #io-channel-cells = <1>; +- status = "disabled"; +- }; +- +- uart0: serial@11002000 { +- compatible = "mediatek,mt8183-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11002000 0 0x1000>; +- interrupts = ; +- clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart1: serial@11003000 { +- compatible = "mediatek,mt8183-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11003000 0 0x1000>; +- interrupts = ; +- clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart2: serial@11004000 { +- compatible = "mediatek,mt8183-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11004000 0 0x1000>; +- interrupts = ; +- clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- i2c6: i2c@11005000 { +- compatible = "mediatek,mt8183-i2c"; +- reg = <0 0x11005000 0 0x1000>, +- <0 0x11000600 0 0x80>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_I2C6>, +- <&infracfg CLK_INFRA_AP_DMA>; +- clock-names = "main", "dma"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c0: i2c@11007000 { +- compatible = "mediatek,mt8183-i2c"; +- reg = <0 0x11007000 0 0x1000>, +- <0 0x11000080 0 0x80>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_I2C0>, +- <&infracfg CLK_INFRA_AP_DMA>; +- clock-names = "main", "dma"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@11008000 { +- compatible = "mediatek,mt8183-i2c"; +- reg = <0 0x11008000 0 0x1000>, +- <0 0x11000100 0 0x80>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_I2C1>, +- <&infracfg CLK_INFRA_AP_DMA>, +- <&infracfg CLK_INFRA_I2C1_ARBITER>; +- clock-names = "main", "dma","arb"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@11009000 { +- compatible = "mediatek,mt8183-i2c"; +- reg = <0 0x11009000 0 0x1000>, +- <0 0x11000280 0 0x80>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_I2C2>, +- <&infracfg CLK_INFRA_AP_DMA>, +- <&infracfg CLK_INFRA_I2C2_ARBITER>; +- clock-names = "main", "dma", "arb"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi0: spi@1100a000 { +- compatible = "mediatek,mt8183-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x1100a000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, +- <&topckgen CLK_TOP_MUX_SPI>, +- <&infracfg CLK_INFRA_SPI0>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- thermal: thermal@1100b000 { +- #thermal-sensor-cells = <1>; +- compatible = "mediatek,mt8183-thermal"; +- reg = <0 0x1100b000 0 0x1000>; +- clocks = <&infracfg CLK_INFRA_THERM>, +- <&infracfg CLK_INFRA_AUXADC>; +- clock-names = "therm", "auxadc"; +- resets = <&infracfg MT8183_INFRACFG_AO_THERM_SW_RST>; +- interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>; +- mediatek,auxadc = <&auxadc>; +- mediatek,apmixedsys = <&apmixedsys>; +- nvmem-cells = <&thermal_calibration>; +- nvmem-cell-names = "calibration-data"; +- }; +- +- thermal_zones: thermal-zones { +- cpu_thermal: cpu_thermal { +- polling-delay-passive = <100>; +- polling-delay = <500>; +- thermal-sensors = <&thermal 0>; +- sustainable-power = <5000>; +- +- trips { +- threshold: trip-point0 { +- temperature = <68000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- target: trip-point1 { +- temperature = <80000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu_crit: cpu-crit { +- temperature = <115000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&target>; +- cooling-device = <&cpu0 +- THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>, +- <&cpu1 +- THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>, +- <&cpu2 +- THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>, +- <&cpu3 +- THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>; +- contribution = <3072>; +- }; +- map1 { +- trip = <&target>; +- cooling-device = <&cpu4 +- THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>, +- <&cpu5 +- THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>, +- <&cpu6 +- THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>, +- <&cpu7 +- THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>; +- contribution = <1024>; +- }; +- }; +- }; +- +- /* The tzts1 ~ tzts6 don't need to polling */ +- /* The tzts1 ~ tzts6 don't need to thermal throttle */ +- +- tzts1: tzts1 { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&thermal 1>; +- sustainable-power = <5000>; +- trips {}; +- cooling-maps {}; +- }; +- +- tzts2: tzts2 { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&thermal 2>; +- sustainable-power = <5000>; +- trips {}; +- cooling-maps {}; +- }; +- +- tzts3: tzts3 { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&thermal 3>; +- sustainable-power = <5000>; +- trips {}; +- cooling-maps {}; +- }; +- +- tzts4: tzts4 { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&thermal 4>; +- sustainable-power = <5000>; +- trips {}; +- cooling-maps {}; +- }; +- +- tzts5: tzts5 { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&thermal 5>; +- sustainable-power = <5000>; +- trips {}; +- cooling-maps {}; +- }; +- +- tztsABB: tztsABB { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&thermal 6>; +- sustainable-power = <5000>; +- trips {}; +- cooling-maps {}; +- }; +- }; +- +- pwm0: pwm@1100e000 { +- compatible = "mediatek,mt8183-disp-pwm"; +- reg = <0 0x1100e000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; +- #pwm-cells = <2>; +- clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>, +- <&infracfg CLK_INFRA_DISP_PWM>; +- clock-names = "main", "mm"; +- }; +- +- pwm1: pwm@11006000 { +- compatible = "mediatek,mt8183-pwm"; +- reg = <0 0x11006000 0 0x1000>; +- #pwm-cells = <2>; +- clocks = <&infracfg CLK_INFRA_PWM>, +- <&infracfg CLK_INFRA_PWM_HCLK>, +- <&infracfg CLK_INFRA_PWM1>, +- <&infracfg CLK_INFRA_PWM2>, +- <&infracfg CLK_INFRA_PWM3>, +- <&infracfg CLK_INFRA_PWM4>; +- clock-names = "top", "main", "pwm1", "pwm2", "pwm3", +- "pwm4"; +- }; +- +- i2c3: i2c@1100f000 { +- compatible = "mediatek,mt8183-i2c"; +- reg = <0 0x1100f000 0 0x1000>, +- <0 0x11000400 0 0x80>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_I2C3>, +- <&infracfg CLK_INFRA_AP_DMA>; +- clock-names = "main", "dma"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi1: spi@11010000 { +- compatible = "mediatek,mt8183-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x11010000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, +- <&topckgen CLK_TOP_MUX_SPI>, +- <&infracfg CLK_INFRA_SPI1>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- i2c1: i2c@11011000 { +- compatible = "mediatek,mt8183-i2c"; +- reg = <0 0x11011000 0 0x1000>, +- <0 0x11000480 0 0x80>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_I2C4>, +- <&infracfg CLK_INFRA_AP_DMA>; +- clock-names = "main", "dma"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi2: spi@11012000 { +- compatible = "mediatek,mt8183-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x11012000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, +- <&topckgen CLK_TOP_MUX_SPI>, +- <&infracfg CLK_INFRA_SPI2>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- spi3: spi@11013000 { +- compatible = "mediatek,mt8183-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x11013000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, +- <&topckgen CLK_TOP_MUX_SPI>, +- <&infracfg CLK_INFRA_SPI3>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- i2c9: i2c@11014000 { +- compatible = "mediatek,mt8183-i2c"; +- reg = <0 0x11014000 0 0x1000>, +- <0 0x11000180 0 0x80>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_I2C1_IMM>, +- <&infracfg CLK_INFRA_AP_DMA>, +- <&infracfg CLK_INFRA_I2C1_ARBITER>; +- clock-names = "main", "dma", "arb"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c10: i2c@11015000 { +- compatible = "mediatek,mt8183-i2c"; +- reg = <0 0x11015000 0 0x1000>, +- <0 0x11000300 0 0x80>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_I2C2_IMM>, +- <&infracfg CLK_INFRA_AP_DMA>, +- <&infracfg CLK_INFRA_I2C2_ARBITER>; +- clock-names = "main", "dma", "arb"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c5: i2c@11016000 { +- compatible = "mediatek,mt8183-i2c"; +- reg = <0 0x11016000 0 0x1000>, +- <0 0x11000500 0 0x80>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_I2C5>, +- <&infracfg CLK_INFRA_AP_DMA>, +- <&infracfg CLK_INFRA_I2C5_ARBITER>; +- clock-names = "main", "dma", "arb"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c11: i2c@11017000 { +- compatible = "mediatek,mt8183-i2c"; +- reg = <0 0x11017000 0 0x1000>, +- <0 0x11000580 0 0x80>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_I2C5_IMM>, +- <&infracfg CLK_INFRA_AP_DMA>, +- <&infracfg CLK_INFRA_I2C5_ARBITER>; +- clock-names = "main", "dma", "arb"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi4: spi@11018000 { +- compatible = "mediatek,mt8183-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x11018000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, +- <&topckgen CLK_TOP_MUX_SPI>, +- <&infracfg CLK_INFRA_SPI4>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- spi5: spi@11019000 { +- compatible = "mediatek,mt8183-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x11019000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, +- <&topckgen CLK_TOP_MUX_SPI>, +- <&infracfg CLK_INFRA_SPI5>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- i2c7: i2c@1101a000 { +- compatible = "mediatek,mt8183-i2c"; +- reg = <0 0x1101a000 0 0x1000>, +- <0 0x11000680 0 0x80>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_I2C7>, +- <&infracfg CLK_INFRA_AP_DMA>; +- clock-names = "main", "dma"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c8: i2c@1101b000 { +- compatible = "mediatek,mt8183-i2c"; +- reg = <0 0x1101b000 0 0x1000>, +- <0 0x11000700 0 0x80>; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_I2C8>, +- <&infracfg CLK_INFRA_AP_DMA>; +- clock-names = "main", "dma"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- ssusb: usb@11201000 { +- compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3"; +- reg = <0 0x11201000 0 0x2e00>, +- <0 0x11203e00 0 0x0100>; +- reg-names = "mac", "ippc"; +- interrupts = ; +- phys = <&u2port0 PHY_TYPE_USB2>, +- <&u3port0 PHY_TYPE_USB3>; +- clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, +- <&infracfg CLK_INFRA_USB>; +- clock-names = "sys_ck", "ref_ck"; +- mediatek,syscon-wakeup = <&pericfg 0x420 101>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "disabled"; +- +- usb_host: usb@11200000 { +- compatible = "mediatek,mt8183-xhci", +- "mediatek,mtk-xhci"; +- reg = <0 0x11200000 0 0x1000>; +- reg-names = "mac"; +- interrupts = ; +- clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, +- <&infracfg CLK_INFRA_USB>; +- clock-names = "sys_ck", "ref_ck"; +- status = "disabled"; +- }; +- }; +- +- audiosys: syscon@11220000 { +- compatible = "mediatek,mt8183-audiosys", "syscon"; +- reg = <0 0x11220000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- mmc0: mmc@11230000 { +- compatible = "mediatek,mt8183-mmc"; +- reg = <0 0x11230000 0 0x1000>, +- <0 0x11f50000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, +- <&infracfg CLK_INFRA_MSDC0>, +- <&infracfg CLK_INFRA_MSDC0_SCK>; +- clock-names = "source", "hclk", "source_cg"; +- status = "disabled"; +- }; +- +- mmc1: mmc@11240000 { +- compatible = "mediatek,mt8183-mmc"; +- reg = <0 0x11240000 0 0x1000>, +- <0 0x11e10000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, +- <&infracfg CLK_INFRA_MSDC1>, +- <&infracfg CLK_INFRA_MSDC1_SCK>; +- clock-names = "source", "hclk", "source_cg"; +- status = "disabled"; +- }; +- +- mipi_tx0: dsi-phy@11e50000 { +- compatible = "mediatek,mt8183-mipi-tx"; +- reg = <0 0x11e50000 0 0x1000>; +- clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>; +- #clock-cells = <0>; +- #phy-cells = <0>; +- clock-output-names = "mipi_tx0_pll"; +- nvmem-cells = <&mipi_tx_calibration>; +- nvmem-cell-names = "calibration-data"; +- }; +- +- efuse: efuse@11f10000 { +- compatible = "mediatek,mt8183-efuse", +- "mediatek,efuse"; +- reg = <0 0x11f10000 0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- thermal_calibration: calib@180 { +- reg = <0x180 0xc>; +- }; +- +- mipi_tx_calibration: calib@190 { +- reg = <0x190 0xc>; +- }; +- }; +- +- u3phy: t-phy@11f40000 { +- compatible = "mediatek,mt8183-tphy", +- "mediatek,generic-tphy-v2"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x11f40000 0x1000>; +- status = "okay"; +- +- u2port0: usb-phy@0 { +- reg = <0x0 0x700>; +- clocks = <&clk26m>; +- clock-names = "ref"; +- #phy-cells = <1>; +- mediatek,discth = <15>; +- status = "okay"; +- }; +- +- u3port0: usb-phy@700 { +- reg = <0x0700 0x900>; +- clocks = <&clk26m>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- }; +- +- mfgcfg: syscon@13000000 { +- compatible = "mediatek,mt8183-mfgcfg", "syscon"; +- reg = <0 0x13000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- gpu: gpu@13040000 { +- compatible = "mediatek,mt8183-mali", "arm,mali-bifrost"; +- reg = <0 0x13040000 0 0x4000>; +- interrupts = +- , +- , +- ; +- interrupt-names = "job", "mmu", "gpu"; +- +- clocks = <&topckgen CLK_TOP_MFGPLL_CK>; +- +- power-domains = +- <&spm MT8183_POWER_DOMAIN_MFG_CORE0>, +- <&spm MT8183_POWER_DOMAIN_MFG_CORE1>, +- <&spm MT8183_POWER_DOMAIN_MFG_2D>; +- power-domain-names = "core0", "core1", "core2"; +- +- operating-points-v2 = <&gpu_opp_table>; +- }; +- +- mmsys: syscon@14000000 { +- compatible = "mediatek,mt8183-mmsys", "syscon"; +- reg = <0 0x14000000 0 0x1000>; +- #clock-cells = <1>; +- mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, +- <&gce 1 CMDQ_THR_PRIO_HIGHEST>; +- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; +- }; +- +- ovl0: ovl@14008000 { +- compatible = "mediatek,mt8183-disp-ovl"; +- reg = <0 0x14008000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; +- clocks = <&mmsys CLK_MM_DISP_OVL0>; +- iommus = <&iommu M4U_PORT_DISP_OVL0>; +- mediatek,larb = <&larb0>; +- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; +- }; +- +- ovl_2l0: ovl@14009000 { +- compatible = "mediatek,mt8183-disp-ovl-2l"; +- reg = <0 0x14009000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; +- clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; +- iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; +- mediatek,larb = <&larb0>; +- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; +- }; +- +- ovl_2l1: ovl@1400a000 { +- compatible = "mediatek,mt8183-disp-ovl-2l"; +- reg = <0 0x1400a000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; +- clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; +- iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; +- mediatek,larb = <&larb0>; +- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; +- }; +- +- rdma0: rdma@1400b000 { +- compatible = "mediatek,mt8183-disp-rdma"; +- reg = <0 0x1400b000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; +- clocks = <&mmsys CLK_MM_DISP_RDMA0>; +- iommus = <&iommu M4U_PORT_DISP_RDMA0>; +- mediatek,larb = <&larb0>; +- mediatek,rdma-fifo-size = <5120>; +- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; +- }; +- +- rdma1: rdma@1400c000 { +- compatible = "mediatek,mt8183-disp-rdma"; +- reg = <0 0x1400c000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; +- clocks = <&mmsys CLK_MM_DISP_RDMA1>; +- iommus = <&iommu M4U_PORT_DISP_RDMA1>; +- mediatek,larb = <&larb0>; +- mediatek,rdma-fifo-size = <2048>; +- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; +- }; +- +- color0: color@1400e000 { +- compatible = "mediatek,mt8183-disp-color", +- "mediatek,mt8173-disp-color"; +- reg = <0 0x1400e000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; +- clocks = <&mmsys CLK_MM_DISP_COLOR0>; +- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; +- }; +- +- ccorr0: ccorr@1400f000 { +- compatible = "mediatek,mt8183-disp-ccorr"; +- reg = <0 0x1400f000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; +- clocks = <&mmsys CLK_MM_DISP_CCORR0>; +- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; +- }; +- +- aal0: aal@14010000 { +- compatible = "mediatek,mt8183-disp-aal", +- "mediatek,mt8173-disp-aal"; +- reg = <0 0x14010000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; +- clocks = <&mmsys CLK_MM_DISP_AAL0>; +- mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; +- }; +- +- gamma0: gamma@14011000 { +- compatible = "mediatek,mt8183-disp-gamma"; +- reg = <0 0x14011000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; +- clocks = <&mmsys CLK_MM_DISP_GAMMA0>; +- mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; +- }; +- +- dither0: dither@14012000 { +- compatible = "mediatek,mt8183-disp-dither"; +- reg = <0 0x14012000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; +- clocks = <&mmsys CLK_MM_DISP_DITHER0>; +- mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; +- }; +- +- dsi0: dsi@14014000 { +- compatible = "mediatek,mt8183-dsi"; +- reg = <0 0x14014000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; +- mediatek,syscon-dsi = <&mmsys 0x140>; +- clocks = <&mmsys CLK_MM_DSI0_MM>, +- <&mmsys CLK_MM_DSI0_IF>, +- <&mipi_tx0>; +- clock-names = "engine", "digital", "hs"; +- phys = <&mipi_tx0>; +- phy-names = "dphy"; +- }; +- +- mutex: mutex@14016000 { +- compatible = "mediatek,mt8183-disp-mutex"; +- reg = <0 0x14016000 0 0x1000>; +- interrupts = ; +- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; +- mediatek,gce-events = , +- ; +- }; +- +- larb0: larb@14017000 { +- compatible = "mediatek,mt8183-smi-larb"; +- reg = <0 0x14017000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- clocks = <&mmsys CLK_MM_SMI_LARB0>, +- <&mmsys CLK_MM_SMI_LARB0>; +- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; +- clock-names = "apb", "smi"; +- }; +- +- smi_common: smi@14019000 { +- compatible = "mediatek,mt8183-smi-common"; +- reg = <0 0x14019000 0 0x1000>; +- clocks = <&mmsys CLK_MM_SMI_COMMON>, +- <&mmsys CLK_MM_SMI_COMMON>, +- <&mmsys CLK_MM_GALS_COMM0>, +- <&mmsys CLK_MM_GALS_COMM1>; +- clock-names = "apb", "smi", "gals0", "gals1"; +- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; +- }; +- +- imgsys: syscon@15020000 { +- compatible = "mediatek,mt8183-imgsys", "syscon"; +- reg = <0 0x15020000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- larb5: larb@15021000 { +- compatible = "mediatek,mt8183-smi-larb"; +- reg = <0 0x15021000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>, +- <&mmsys CLK_MM_GALS_IMG2MM>; +- clock-names = "apb", "smi", "gals"; +- power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; +- }; +- +- larb2: larb@1502f000 { +- compatible = "mediatek,mt8183-smi-larb"; +- reg = <0 0x1502f000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>, +- <&mmsys CLK_MM_GALS_IPU2MM>; +- clock-names = "apb", "smi", "gals"; +- power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; +- }; +- +- vdecsys: syscon@16000000 { +- compatible = "mediatek,mt8183-vdecsys", "syscon"; +- reg = <0 0x16000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- larb1: larb@16010000 { +- compatible = "mediatek,mt8183-smi-larb"; +- reg = <0 0x16010000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>; +- clock-names = "apb", "smi"; +- power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; +- }; +- +- vencsys: syscon@17000000 { +- compatible = "mediatek,mt8183-vencsys", "syscon"; +- reg = <0 0x17000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- larb4: larb@17010000 { +- compatible = "mediatek,mt8183-smi-larb"; +- reg = <0 0x17010000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- clocks = <&vencsys CLK_VENC_LARB>, +- <&vencsys CLK_VENC_LARB>; +- clock-names = "apb", "smi"; +- power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; +- }; +- +- ipu_conn: syscon@19000000 { +- compatible = "mediatek,mt8183-ipu_conn", "syscon"; +- reg = <0 0x19000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- ipu_adl: syscon@19010000 { +- compatible = "mediatek,mt8183-ipu_adl", "syscon"; +- reg = <0 0x19010000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- ipu_core0: syscon@19180000 { +- compatible = "mediatek,mt8183-ipu_core0", "syscon"; +- reg = <0 0x19180000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- ipu_core1: syscon@19280000 { +- compatible = "mediatek,mt8183-ipu_core1", "syscon"; +- reg = <0 0x19280000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- camsys: syscon@1a000000 { +- compatible = "mediatek,mt8183-camsys", "syscon"; +- reg = <0 0x1a000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- larb6: larb@1a001000 { +- compatible = "mediatek,mt8183-smi-larb"; +- reg = <0 0x1a001000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>, +- <&mmsys CLK_MM_GALS_CAM2MM>; +- clock-names = "apb", "smi", "gals"; +- power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; +- }; +- +- larb3: larb@1a002000 { +- compatible = "mediatek,mt8183-smi-larb"; +- reg = <0 0x1a002000 0 0x1000>; +- mediatek,smi = <&smi_common>; +- clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>, +- <&mmsys CLK_MM_GALS_IPU12MM>; +- clock-names = "apb", "smi", "gals"; +- power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8192-evb.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8192-evb.dts +deleted file mode 100644 +index 0205837fa698..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8192-evb.dts ++++ /dev/null +@@ -1,29 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2020 MediaTek Inc. +- * Author: Seiya Wang +- */ +-/dts-v1/; +-#include "mt8192.dtsi" +- +-/ { +- model = "MediaTek MT8192 evaluation board"; +- compatible = "mediatek,mt8192-evb", "mediatek,mt8192"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:921600n8"; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x80000000>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8192.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt8192.dtsi +deleted file mode 100644 +index 9757138a8bbd..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8192.dtsi ++++ /dev/null +@@ -1,569 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2020 MediaTek Inc. +- * Author: Seiya Wang +- */ +- +-/dts-v1/; +-#include +-#include +-#include +- +-/ { +- compatible = "mediatek,mt8192"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- clk26m: oscillator0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- clock-output-names = "clk26m"; +- }; +- +- clk32k: oscillator1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "clk32k"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x000>; +- enable-method = "psci"; +- clock-frequency = <1701000000>; +- cpu-idle-states = <&cpuoff_l &clusteroff_l>; +- next-level-cache = <&l2_0>; +- capacity-dmips-mhz = <530>; +- }; +- +- cpu1: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x100>; +- enable-method = "psci"; +- clock-frequency = <1701000000>; +- cpu-idle-states = <&cpuoff_l &clusteroff_l>; +- next-level-cache = <&l2_0>; +- capacity-dmips-mhz = <530>; +- }; +- +- cpu2: cpu@200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x200>; +- enable-method = "psci"; +- clock-frequency = <1701000000>; +- cpu-idle-states = <&cpuoff_l &clusteroff_l>; +- next-level-cache = <&l2_0>; +- capacity-dmips-mhz = <530>; +- }; +- +- cpu3: cpu@300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x300>; +- enable-method = "psci"; +- clock-frequency = <1701000000>; +- cpu-idle-states = <&cpuoff_l &clusteroff_l>; +- next-level-cache = <&l2_0>; +- capacity-dmips-mhz = <530>; +- }; +- +- cpu4: cpu@400 { +- device_type = "cpu"; +- compatible = "arm,cortex-a76"; +- reg = <0x400>; +- enable-method = "psci"; +- clock-frequency = <2171000000>; +- cpu-idle-states = <&cpuoff_b &clusteroff_b>; +- next-level-cache = <&l2_1>; +- capacity-dmips-mhz = <1024>; +- }; +- +- cpu5: cpu@500 { +- device_type = "cpu"; +- compatible = "arm,cortex-a76"; +- reg = <0x500>; +- enable-method = "psci"; +- clock-frequency = <2171000000>; +- cpu-idle-states = <&cpuoff_b &clusteroff_b>; +- next-level-cache = <&l2_1>; +- capacity-dmips-mhz = <1024>; +- }; +- +- cpu6: cpu@600 { +- device_type = "cpu"; +- compatible = "arm,cortex-a76"; +- reg = <0x600>; +- enable-method = "psci"; +- clock-frequency = <2171000000>; +- cpu-idle-states = <&cpuoff_b &clusteroff_b>; +- next-level-cache = <&l2_1>; +- capacity-dmips-mhz = <1024>; +- }; +- +- cpu7: cpu@700 { +- device_type = "cpu"; +- compatible = "arm,cortex-a76"; +- reg = <0x700>; +- enable-method = "psci"; +- clock-frequency = <2171000000>; +- cpu-idle-states = <&cpuoff_b &clusteroff_b>; +- next-level-cache = <&l2_1>; +- capacity-dmips-mhz = <1024>; +- }; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- core2 { +- cpu = <&cpu2>; +- }; +- core3 { +- cpu = <&cpu3>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&cpu4>; +- }; +- core1 { +- cpu = <&cpu5>; +- }; +- core2 { +- cpu = <&cpu6>; +- }; +- core3 { +- cpu = <&cpu7>; +- }; +- }; +- }; +- +- l2_0: l2-cache0 { +- compatible = "cache"; +- next-level-cache = <&l3_0>; +- }; +- +- l2_1: l2-cache1 { +- compatible = "cache"; +- next-level-cache = <&l3_0>; +- }; +- +- l3_0: l3-cache { +- compatible = "cache"; +- }; +- +- idle-states { +- entry-method = "arm,psci"; +- cpuoff_l: cpuoff_l { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x00010001>; +- local-timer-stop; +- entry-latency-us = <55>; +- exit-latency-us = <140>; +- min-residency-us = <780>; +- }; +- cpuoff_b: cpuoff_b { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x00010001>; +- local-timer-stop; +- entry-latency-us = <35>; +- exit-latency-us = <145>; +- min-residency-us = <720>; +- }; +- clusteroff_l: clusteroff_l { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x01010002>; +- local-timer-stop; +- entry-latency-us = <60>; +- exit-latency-us = <155>; +- min-residency-us = <860>; +- }; +- clusteroff_b: clusteroff_b { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x01010002>; +- local-timer-stop; +- entry-latency-us = <40>; +- exit-latency-us = <155>; +- min-residency-us = <780>; +- }; +- }; +- }; +- +- pmu-a55 { +- compatible = "arm,cortex-a55-pmu"; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- +- pmu-a76 { +- compatible = "arm,cortex-a76-pmu"; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- timer: timer { +- compatible = "arm,armv8-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- clock-frequency = <13000000>; +- }; +- +- soc { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "simple-bus"; +- ranges; +- +- gic: interrupt-controller@c000000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <4>; +- #redistributor-regions = <1>; +- interrupt-parent = <&gic>; +- interrupt-controller; +- reg = <0 0x0c000000 0 0x40000>, +- <0 0x0c040000 0 0x200000>; +- interrupts = ; +- +- ppi-partitions { +- ppi_cluster0: interrupt-partition-0 { +- affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; +- }; +- ppi_cluster1: interrupt-partition-1 { +- affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; +- }; +- }; +- }; +- +- pio: pinctrl@10005000 { +- compatible = "mediatek,mt8192-pinctrl"; +- reg = <0 0x10005000 0 0x1000>, +- <0 0x11c20000 0 0x1000>, +- <0 0x11d10000 0 0x1000>, +- <0 0x11d30000 0 0x1000>, +- <0 0x11d40000 0 0x1000>, +- <0 0x11e20000 0 0x1000>, +- <0 0x11e70000 0 0x1000>, +- <0 0x11ea0000 0 0x1000>, +- <0 0x11f20000 0 0x1000>, +- <0 0x11f30000 0 0x1000>, +- <0 0x1000b000 0 0x1000>; +- reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", +- "iocfg_bl", "iocfg_br", "iocfg_lm", +- "iocfg_lb", "iocfg_rt", "iocfg_lt", +- "iocfg_tl", "eint"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pio 0 0 220>; +- interrupt-controller; +- interrupts = ; +- #interrupt-cells = <2>; +- }; +- +- systimer: timer@10017000 { +- compatible = "mediatek,mt8192-timer", +- "mediatek,mt6765-timer"; +- reg = <0 0x10017000 0 0x1000>; +- interrupts = ; +- clocks = <&clk26m>; +- clock-names = "clk13m"; +- }; +- +- uart0: serial@11002000 { +- compatible = "mediatek,mt8192-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11002000 0 0x1000>; +- interrupts = ; +- clocks = <&clk26m>, <&clk26m>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- uart1: serial@11003000 { +- compatible = "mediatek,mt8192-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11003000 0 0x1000>; +- interrupts = ; +- clocks = <&clk26m>, <&clk26m>; +- clock-names = "baud", "bus"; +- status = "disabled"; +- }; +- +- spi0: spi@1100a000 { +- compatible = "mediatek,mt8192-spi", +- "mediatek,mt6765-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x1100a000 0 0x1000>; +- interrupts = ; +- clocks = <&clk26m>, +- <&clk26m>, +- <&clk26m>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- spi1: spi@11010000 { +- compatible = "mediatek,mt8192-spi", +- "mediatek,mt6765-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x11010000 0 0x1000>; +- interrupts = ; +- clocks = <&clk26m>, +- <&clk26m>, +- <&clk26m>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- spi2: spi@11012000 { +- compatible = "mediatek,mt8192-spi", +- "mediatek,mt6765-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x11012000 0 0x1000>; +- interrupts = ; +- clocks = <&clk26m>, +- <&clk26m>, +- <&clk26m>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- spi3: spi@11013000 { +- compatible = "mediatek,mt8192-spi", +- "mediatek,mt6765-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x11013000 0 0x1000>; +- interrupts = ; +- clocks = <&clk26m>, +- <&clk26m>, +- <&clk26m>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- spi4: spi@11018000 { +- compatible = "mediatek,mt8192-spi", +- "mediatek,mt6765-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x11018000 0 0x1000>; +- interrupts = ; +- clocks = <&clk26m>, +- <&clk26m>, +- <&clk26m>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- spi5: spi@11019000 { +- compatible = "mediatek,mt8192-spi", +- "mediatek,mt6765-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x11019000 0 0x1000>; +- interrupts = ; +- clocks = <&clk26m>, +- <&clk26m>, +- <&clk26m>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- spi6: spi@1101d000 { +- compatible = "mediatek,mt8192-spi", +- "mediatek,mt6765-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x1101d000 0 0x1000>; +- interrupts = ; +- clocks = <&clk26m>, +- <&clk26m>, +- <&clk26m>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- spi7: spi@1101e000 { +- compatible = "mediatek,mt8192-spi", +- "mediatek,mt6765-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x1101e000 0 0x1000>; +- interrupts = ; +- clocks = <&clk26m>, +- <&clk26m>, +- <&clk26m>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- nor_flash: spi@11234000 { +- compatible = "mediatek,mt8192-nor"; +- reg = <0 0x11234000 0 0xe0>; +- interrupts = ; +- clocks = <&clk26m>, +- <&clk26m>, +- <&clk26m>; +- clock-names = "spi", "sf", "axi"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disable"; +- }; +- +- i2c3: i2c3@11cb0000 { +- compatible = "mediatek,mt8192-i2c"; +- reg = <0 0x11cb0000 0 0x1000>, +- <0 0x10217300 0 0x80>; +- interrupts = ; +- clocks = <&clk26m>, <&clk26m>; +- clock-names = "main", "dma"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c7: i2c7@11d00000 { +- compatible = "mediatek,mt8192-i2c"; +- reg = <0 0x11d00000 0 0x1000>, +- <0 0x10217600 0 0x180>; +- interrupts = ; +- clocks = <&clk26m>, <&clk26m>; +- clock-names = "main", "dma"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c8: i2c8@11d01000 { +- compatible = "mediatek,mt8192-i2c"; +- reg = <0 0x11d01000 0 0x1000>, +- <0 0x10217780 0 0x180>; +- interrupts = ; +- clocks = <&clk26m>, <&clk26m>; +- clock-names = "main", "dma"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c9: i2c9@11d02000 { +- compatible = "mediatek,mt8192-i2c"; +- reg = <0 0x11d02000 0 0x1000>, +- <0 0x10217900 0 0x180>; +- interrupts = ; +- clocks = <&clk26m>, <&clk26m>; +- clock-names = "main", "dma"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c1@11d20000 { +- compatible = "mediatek,mt8192-i2c"; +- reg = <0 0x11d20000 0 0x1000>, +- <0 0x10217100 0 0x80>; +- interrupts = ; +- clocks = <&clk26m>, <&clk26m>; +- clock-names = "main", "dma"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c2@11d21000 { +- compatible = "mediatek,mt8192-i2c"; +- reg = <0 0x11d21000 0 0x1000>, +- <0 0x10217180 0 0x180>; +- interrupts = ; +- clocks = <&clk26m>, <&clk26m>; +- clock-names = "main", "dma"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c4@11d22000 { +- compatible = "mediatek,mt8192-i2c"; +- reg = <0 0x11d22000 0 0x1000>, +- <0 0x10217380 0 0x180>; +- interrupts = ; +- clocks = <&clk26m>, <&clk26m>; +- clock-names = "main", "dma"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c5: i2c5@11e00000 { +- compatible = "mediatek,mt8192-i2c"; +- reg = <0 0x11e00000 0 0x1000>, +- <0 0x10217500 0 0x80>; +- interrupts = ; +- clocks = <&clk26m>, <&clk26m>; +- clock-names = "main", "dma"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c0: i2c0@11f00000 { +- compatible = "mediatek,mt8192-i2c"; +- reg = <0 0x11f00000 0 0x1000>, +- <0 0x10217080 0 0x80>; +- interrupts = ; +- clocks = <&clk26m>, <&clk26m>; +- clock-names = "main", "dma"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c6: i2c6@11f01000 { +- compatible = "mediatek,mt8192-i2c"; +- reg = <0 0x11f01000 0 0x1000>, +- <0 0x10217580 0 0x80>; +- interrupts = ; +- clocks = <&clk26m>, <&clk26m>; +- clock-names = "main", "dma"; +- clock-div = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8516-pinfunc.h b/scripts/dtc/include-prefixes/arm64/mediatek/mt8516-pinfunc.h +deleted file mode 100644 +index 73339bb48f0d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8516-pinfunc.h ++++ /dev/null +@@ -1,663 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2019 MediaTek Inc. +- */ +-#ifndef __DTS_MT8516_PINFUNC_H +-#define __DTS_MT8516_PINFUNC_H +- +-#include +- +-#define MT8516_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +-#define MT8516_PIN_0_EINT0__FUNC_PWM_B (MTK_PIN_NO(0) | 1) +-#define MT8516_PIN_0_EINT0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3) +-#define MT8516_PIN_0_EINT0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4) +-#define MT8516_PIN_0_EINT0__FUNC_SQICS (MTK_PIN_NO(0) | 6) +-#define MT8516_PIN_0_EINT0__FUNC_DBG_MON_A_6 (MTK_PIN_NO(0) | 7) +- +-#define MT8516_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +-#define MT8516_PIN_1_EINT1__FUNC_PWM_C (MTK_PIN_NO(1) | 1) +-#define MT8516_PIN_1_EINT1__FUNC_I2S2_DI (MTK_PIN_NO(1) | 3) +-#define MT8516_PIN_1_EINT1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4) +-#define MT8516_PIN_1_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(1) | 5) +-#define MT8516_PIN_1_EINT1__FUNC_SQISO (MTK_PIN_NO(1) | 6) +-#define MT8516_PIN_1_EINT1__FUNC_DBG_MON_A_7 (MTK_PIN_NO(1) | 7) +- +-#define MT8516_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +-#define MT8516_PIN_2_EINT2__FUNC_CLKM0 (MTK_PIN_NO(2) | 1) +-#define MT8516_PIN_2_EINT2__FUNC_I2S2_LRCK (MTK_PIN_NO(2) | 3) +-#define MT8516_PIN_2_EINT2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4) +-#define MT8516_PIN_2_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(2) | 5) +-#define MT8516_PIN_2_EINT2__FUNC_SQISI (MTK_PIN_NO(2) | 6) +-#define MT8516_PIN_2_EINT2__FUNC_DBG_MON_A_8 (MTK_PIN_NO(2) | 7) +- +-#define MT8516_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +-#define MT8516_PIN_3_EINT3__FUNC_CLKM1 (MTK_PIN_NO(3) | 1) +-#define MT8516_PIN_3_EINT3__FUNC_SPI_MI (MTK_PIN_NO(3) | 3) +-#define MT8516_PIN_3_EINT3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4) +-#define MT8516_PIN_3_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(3) | 5) +-#define MT8516_PIN_3_EINT3__FUNC_SQIWP (MTK_PIN_NO(3) | 6) +-#define MT8516_PIN_3_EINT3__FUNC_DBG_MON_A_9 (MTK_PIN_NO(3) | 7) +- +-#define MT8516_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +-#define MT8516_PIN_4_EINT4__FUNC_CLKM2 (MTK_PIN_NO(4) | 1) +-#define MT8516_PIN_4_EINT4__FUNC_SPI_MO (MTK_PIN_NO(4) | 3) +-#define MT8516_PIN_4_EINT4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4) +-#define MT8516_PIN_4_EINT4__FUNC_CONN_MCU_TCK (MTK_PIN_NO(4) | 5) +-#define MT8516_PIN_4_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(4) | 6) +-#define MT8516_PIN_4_EINT4__FUNC_DBG_MON_A_10 (MTK_PIN_NO(4) | 7) +- +-#define MT8516_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +-#define MT8516_PIN_5_EINT5__FUNC_UCTS2 (MTK_PIN_NO(5) | 1) +-#define MT8516_PIN_5_EINT5__FUNC_SPI_CSB (MTK_PIN_NO(5) | 3) +-#define MT8516_PIN_5_EINT5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4) +-#define MT8516_PIN_5_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(5) | 5) +-#define MT8516_PIN_5_EINT5__FUNC_CONN_TEST_CK (MTK_PIN_NO(5) | 6) +-#define MT8516_PIN_5_EINT5__FUNC_DBG_MON_A_11 (MTK_PIN_NO(5) | 7) +- +-#define MT8516_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +-#define MT8516_PIN_6_EINT6__FUNC_URTS2 (MTK_PIN_NO(6) | 1) +-#define MT8516_PIN_6_EINT6__FUNC_SPI_CLK (MTK_PIN_NO(6) | 3) +-#define MT8516_PIN_6_EINT6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4) +-#define MT8516_PIN_6_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(6) | 5) +-#define MT8516_PIN_6_EINT6__FUNC_DBG_MON_A_12 (MTK_PIN_NO(6) | 7) +- +-#define MT8516_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +-#define MT8516_PIN_7_EINT7__FUNC_SQIRST (MTK_PIN_NO(7) | 1) +-#define MT8516_PIN_7_EINT7__FUNC_SDA1_0 (MTK_PIN_NO(7) | 3) +-#define MT8516_PIN_7_EINT7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4) +-#define MT8516_PIN_7_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(7) | 5) +-#define MT8516_PIN_7_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(7) | 6) +-#define MT8516_PIN_7_EINT7__FUNC_DBG_MON_A_13 (MTK_PIN_NO(7) | 7) +- +-#define MT8516_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +-#define MT8516_PIN_8_EINT8__FUNC_SQICK (MTK_PIN_NO(8) | 1) +-#define MT8516_PIN_8_EINT8__FUNC_CLKM3 (MTK_PIN_NO(8) | 2) +-#define MT8516_PIN_8_EINT8__FUNC_SCL1_0 (MTK_PIN_NO(8) | 3) +-#define MT8516_PIN_8_EINT8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4) +-#define MT8516_PIN_8_EINT8__FUNC_ANT_SEL0 (MTK_PIN_NO(8) | 5) +-#define MT8516_PIN_8_EINT8__FUNC_DBG_MON_A_14 (MTK_PIN_NO(8) | 7) +- +-#define MT8516_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +-#define MT8516_PIN_9_EINT9__FUNC_CLKM4 (MTK_PIN_NO(9) | 1) +-#define MT8516_PIN_9_EINT9__FUNC_SDA2_0 (MTK_PIN_NO(9) | 2) +-#define MT8516_PIN_9_EINT9__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3) +-#define MT8516_PIN_9_EINT9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4) +-#define MT8516_PIN_9_EINT9__FUNC_ANT_SEL1 (MTK_PIN_NO(9) | 5) +-#define MT8516_PIN_9_EINT9__FUNC_DBG_MON_A_15 (MTK_PIN_NO(9) | 7) +- +-#define MT8516_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +-#define MT8516_PIN_10_EINT10__FUNC_CLKM5 (MTK_PIN_NO(10) | 1) +-#define MT8516_PIN_10_EINT10__FUNC_SCL2_0 (MTK_PIN_NO(10) | 2) +-#define MT8516_PIN_10_EINT10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 3) +-#define MT8516_PIN_10_EINT10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4) +-#define MT8516_PIN_10_EINT10__FUNC_ANT_SEL2 (MTK_PIN_NO(10) | 5) +-#define MT8516_PIN_10_EINT10__FUNC_DBG_MON_A_16 (MTK_PIN_NO(10) | 7) +- +-#define MT8516_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +-#define MT8516_PIN_11_EINT11__FUNC_CLKM4 (MTK_PIN_NO(11) | 1) +-#define MT8516_PIN_11_EINT11__FUNC_PWM_C (MTK_PIN_NO(11) | 2) +-#define MT8516_PIN_11_EINT11__FUNC_CONN_TEST_CK (MTK_PIN_NO(11) | 3) +-#define MT8516_PIN_11_EINT11__FUNC_ANT_SEL3 (MTK_PIN_NO(11) | 4) +-#define MT8516_PIN_11_EINT11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 6) +-#define MT8516_PIN_11_EINT11__FUNC_DBG_MON_A_17 (MTK_PIN_NO(11) | 7) +- +-#define MT8516_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +-#define MT8516_PIN_12_EINT12__FUNC_CLKM5 (MTK_PIN_NO(12) | 1) +-#define MT8516_PIN_12_EINT12__FUNC_PWM_A (MTK_PIN_NO(12) | 2) +-#define MT8516_PIN_12_EINT12__FUNC_SPDIF_OUT (MTK_PIN_NO(12) | 3) +-#define MT8516_PIN_12_EINT12__FUNC_ANT_SEL4 (MTK_PIN_NO(12) | 4) +-#define MT8516_PIN_12_EINT12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 6) +-#define MT8516_PIN_12_EINT12__FUNC_DBG_MON_A_18 (MTK_PIN_NO(12) | 7) +- +-#define MT8516_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +-#define MT8516_PIN_13_EINT13__FUNC_TSF_IN (MTK_PIN_NO(13) | 3) +-#define MT8516_PIN_13_EINT13__FUNC_ANT_SEL5 (MTK_PIN_NO(13) | 4) +-#define MT8516_PIN_13_EINT13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 6) +-#define MT8516_PIN_13_EINT13__FUNC_DBG_MON_A_19 (MTK_PIN_NO(13) | 7) +- +-#define MT8516_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +-#define MT8516_PIN_14_EINT14__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(14) | 2) +-#define MT8516_PIN_14_EINT14__FUNC_TDM_RX_MCK (MTK_PIN_NO(14) | 3) +-#define MT8516_PIN_14_EINT14__FUNC_ANT_SEL1 (MTK_PIN_NO(14) | 4) +-#define MT8516_PIN_14_EINT14__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(14) | 5) +-#define MT8516_PIN_14_EINT14__FUNC_NCLE (MTK_PIN_NO(14) | 6) +-#define MT8516_PIN_14_EINT14__FUNC_DBG_MON_B_8 (MTK_PIN_NO(14) | 7) +- +-#define MT8516_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +-#define MT8516_PIN_15_EINT15__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(15) | 2) +-#define MT8516_PIN_15_EINT15__FUNC_TDM_RX_BCK (MTK_PIN_NO(15) | 3) +-#define MT8516_PIN_15_EINT15__FUNC_ANT_SEL2 (MTK_PIN_NO(15) | 4) +-#define MT8516_PIN_15_EINT15__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(15) | 5) +-#define MT8516_PIN_15_EINT15__FUNC_NCEB1 (MTK_PIN_NO(15) | 6) +-#define MT8516_PIN_15_EINT15__FUNC_DBG_MON_B_9 (MTK_PIN_NO(15) | 7) +- +-#define MT8516_PIN_16_EINT16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +-#define MT8516_PIN_16_EINT16__FUNC_I2S_8CH_BCK (MTK_PIN_NO(16) | 2) +-#define MT8516_PIN_16_EINT16__FUNC_TDM_RX_LRCK (MTK_PIN_NO(16) | 3) +-#define MT8516_PIN_16_EINT16__FUNC_ANT_SEL3 (MTK_PIN_NO(16) | 4) +-#define MT8516_PIN_16_EINT16__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(16) | 5) +-#define MT8516_PIN_16_EINT16__FUNC_NCEB0 (MTK_PIN_NO(16) | 6) +-#define MT8516_PIN_16_EINT16__FUNC_DBG_MON_B_10 (MTK_PIN_NO(16) | 7) +- +-#define MT8516_PIN_17_EINT17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +-#define MT8516_PIN_17_EINT17__FUNC_I2S_8CH_MCK (MTK_PIN_NO(17) | 2) +-#define MT8516_PIN_17_EINT17__FUNC_TDM_RX_DI (MTK_PIN_NO(17) | 3) +-#define MT8516_PIN_17_EINT17__FUNC_IDDIG (MTK_PIN_NO(17) | 4) +-#define MT8516_PIN_17_EINT17__FUNC_ANT_SEL4 (MTK_PIN_NO(17) | 5) +-#define MT8516_PIN_17_EINT17__FUNC_NREB (MTK_PIN_NO(17) | 6) +-#define MT8516_PIN_17_EINT17__FUNC_DBG_MON_B_11 (MTK_PIN_NO(17) | 7) +- +-#define MT8516_PIN_18_EINT18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +-#define MT8516_PIN_18_EINT18__FUNC_USB_DRVVBUS (MTK_PIN_NO(18) | 2) +-#define MT8516_PIN_18_EINT18__FUNC_I2S3_LRCK (MTK_PIN_NO(18) | 3) +-#define MT8516_PIN_18_EINT18__FUNC_CLKM1 (MTK_PIN_NO(18) | 4) +-#define MT8516_PIN_18_EINT18__FUNC_ANT_SEL3 (MTK_PIN_NO(18) | 5) +-#define MT8516_PIN_18_EINT18__FUNC_I2S2_BCK (MTK_PIN_NO(18) | 6) +-#define MT8516_PIN_18_EINT18__FUNC_DBG_MON_A_20 (MTK_PIN_NO(18) | 7) +- +-#define MT8516_PIN_19_EINT19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +-#define MT8516_PIN_19_EINT19__FUNC_UCTS1 (MTK_PIN_NO(19) | 1) +-#define MT8516_PIN_19_EINT19__FUNC_IDDIG (MTK_PIN_NO(19) | 2) +-#define MT8516_PIN_19_EINT19__FUNC_I2S3_BCK (MTK_PIN_NO(19) | 3) +-#define MT8516_PIN_19_EINT19__FUNC_CLKM2 (MTK_PIN_NO(19) | 4) +-#define MT8516_PIN_19_EINT19__FUNC_ANT_SEL4 (MTK_PIN_NO(19) | 5) +-#define MT8516_PIN_19_EINT19__FUNC_I2S2_DI (MTK_PIN_NO(19) | 6) +-#define MT8516_PIN_19_EINT19__FUNC_DBG_MON_A_21 (MTK_PIN_NO(19) | 7) +- +-#define MT8516_PIN_20_EINT20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +-#define MT8516_PIN_20_EINT20__FUNC_URTS1 (MTK_PIN_NO(20) | 1) +-#define MT8516_PIN_20_EINT20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 3) +-#define MT8516_PIN_20_EINT20__FUNC_CLKM3 (MTK_PIN_NO(20) | 4) +-#define MT8516_PIN_20_EINT20__FUNC_ANT_SEL5 (MTK_PIN_NO(20) | 5) +-#define MT8516_PIN_20_EINT20__FUNC_I2S2_LRCK (MTK_PIN_NO(20) | 6) +-#define MT8516_PIN_20_EINT20__FUNC_DBG_MON_A_22 (MTK_PIN_NO(20) | 7) +- +-#define MT8516_PIN_21_EINT21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +-#define MT8516_PIN_21_EINT21__FUNC_NRNB (MTK_PIN_NO(21) | 1) +-#define MT8516_PIN_21_EINT21__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 2) +-#define MT8516_PIN_21_EINT21__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(21) | 3) +-#define MT8516_PIN_21_EINT21__FUNC_DBG_MON_B_31 (MTK_PIN_NO(21) | 7) +- +-#define MT8516_PIN_22_EINT22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +-#define MT8516_PIN_22_EINT22__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(22) | 2) +-#define MT8516_PIN_22_EINT22__FUNC_TSF_IN (MTK_PIN_NO(22) | 3) +-#define MT8516_PIN_22_EINT22__FUNC_USB_DRVVBUS (MTK_PIN_NO(22) | 4) +-#define MT8516_PIN_22_EINT22__FUNC_SPDIF_OUT (MTK_PIN_NO(22) | 5) +-#define MT8516_PIN_22_EINT22__FUNC_NRE_C (MTK_PIN_NO(22) | 6) +-#define MT8516_PIN_22_EINT22__FUNC_DBG_MON_B_12 (MTK_PIN_NO(22) | 7) +- +-#define MT8516_PIN_23_EINT23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +-#define MT8516_PIN_23_EINT23__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(23) | 2) +-#define MT8516_PIN_23_EINT23__FUNC_CLKM0 (MTK_PIN_NO(23) | 3) +-#define MT8516_PIN_23_EINT23__FUNC_IR (MTK_PIN_NO(23) | 4) +-#define MT8516_PIN_23_EINT23__FUNC_SPDIF_IN (MTK_PIN_NO(23) | 5) +-#define MT8516_PIN_23_EINT23__FUNC_NDQS_C (MTK_PIN_NO(23) | 6) +-#define MT8516_PIN_23_EINT23__FUNC_DBG_MON_B_13 (MTK_PIN_NO(23) | 7) +- +-#define MT8516_PIN_24_EINT24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +-#define MT8516_PIN_24_EINT24__FUNC_ANT_SEL1 (MTK_PIN_NO(24) | 3) +-#define MT8516_PIN_24_EINT24__FUNC_UCTS2 (MTK_PIN_NO(24) | 4) +-#define MT8516_PIN_24_EINT24__FUNC_PWM_A (MTK_PIN_NO(24) | 5) +-#define MT8516_PIN_24_EINT24__FUNC_I2S0_MCK (MTK_PIN_NO(24) | 6) +-#define MT8516_PIN_24_EINT24__FUNC_DBG_MON_A_0 (MTK_PIN_NO(24) | 7) +- +-#define MT8516_PIN_25_EINT25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +-#define MT8516_PIN_25_EINT25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 3) +-#define MT8516_PIN_25_EINT25__FUNC_URTS2 (MTK_PIN_NO(25) | 4) +-#define MT8516_PIN_25_EINT25__FUNC_PWM_B (MTK_PIN_NO(25) | 5) +-#define MT8516_PIN_25_EINT25__FUNC_I2S_8CH_MCK (MTK_PIN_NO(25) | 6) +-#define MT8516_PIN_25_EINT25__FUNC_DBG_MON_A_1 (MTK_PIN_NO(25) | 7) +- +-#define MT8516_PIN_26_PWRAP_SPI0_MI__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +-#define MT8516_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(26) | 1) +-#define MT8516_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(26) | 2) +- +-#define MT8516_PIN_27_PWRAP_SPI0_MO__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +-#define MT8516_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(27) | 1) +-#define MT8516_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(27) | 2) +- +-#define MT8516_PIN_28_PWRAP_INT__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +-#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S0_MCK (MTK_PIN_NO(28) | 1) +-#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S_8CH_MCK (MTK_PIN_NO(28) | 4) +-#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S2_MCK (MTK_PIN_NO(28) | 5) +-#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S3_MCK (MTK_PIN_NO(28) | 6) +- +-#define MT8516_PIN_29_PWRAP_SPI0_CK__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +-#define MT8516_PIN_29_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(29) | 1) +- +-#define MT8516_PIN_30_PWRAP_SPI0_CSN__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +-#define MT8516_PIN_30_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(30) | 1) +- +-#define MT8516_PIN_31_RTC32K_CK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +-#define MT8516_PIN_31_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(31) | 1) +- +-#define MT8516_PIN_32_WATCHDOG__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +-#define MT8516_PIN_32_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(32) | 1) +- +-#define MT8516_PIN_33_SRCLKENA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +-#define MT8516_PIN_33_SRCLKENA__FUNC_SRCLKENA0 (MTK_PIN_NO(33) | 1) +- +-#define MT8516_PIN_34_URXD2__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +-#define MT8516_PIN_34_URXD2__FUNC_URXD2 (MTK_PIN_NO(34) | 1) +-#define MT8516_PIN_34_URXD2__FUNC_UTXD2 (MTK_PIN_NO(34) | 3) +-#define MT8516_PIN_34_URXD2__FUNC_DBG_SCL (MTK_PIN_NO(34) | 4) +-#define MT8516_PIN_34_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(34) | 6) +-#define MT8516_PIN_34_URXD2__FUNC_DBG_MON_B_0 (MTK_PIN_NO(34) | 7) +- +-#define MT8516_PIN_35_UTXD2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +-#define MT8516_PIN_35_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(35) | 1) +-#define MT8516_PIN_35_UTXD2__FUNC_URXD2 (MTK_PIN_NO(35) | 3) +-#define MT8516_PIN_35_UTXD2__FUNC_DBG_SDA (MTK_PIN_NO(35) | 4) +-#define MT8516_PIN_35_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(35) | 6) +-#define MT8516_PIN_35_UTXD2__FUNC_DBG_MON_B_1 (MTK_PIN_NO(35) | 7) +- +-#define MT8516_PIN_36_MRG_CLK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +-#define MT8516_PIN_36_MRG_CLK__FUNC_MRG_CLK (MTK_PIN_NO(36) | 1) +-#define MT8516_PIN_36_MRG_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(36) | 3) +-#define MT8516_PIN_36_MRG_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(36) | 4) +-#define MT8516_PIN_36_MRG_CLK__FUNC_PCM0_CLK (MTK_PIN_NO(36) | 5) +-#define MT8516_PIN_36_MRG_CLK__FUNC_IR (MTK_PIN_NO(36) | 6) +-#define MT8516_PIN_36_MRG_CLK__FUNC_DBG_MON_A_2 (MTK_PIN_NO(36) | 7) +- +-#define MT8516_PIN_37_MRG_SYNC__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +-#define MT8516_PIN_37_MRG_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(37) | 1) +-#define MT8516_PIN_37_MRG_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(37) | 3) +-#define MT8516_PIN_37_MRG_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(37) | 4) +-#define MT8516_PIN_37_MRG_SYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(37) | 5) +-#define MT8516_PIN_37_MRG_SYNC__FUNC_EXT_COL (MTK_PIN_NO(37) | 6) +-#define MT8516_PIN_37_MRG_SYNC__FUNC_DBG_MON_A_3 (MTK_PIN_NO(37) | 7) +- +-#define MT8516_PIN_38_MRG_DI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +-#define MT8516_PIN_38_MRG_DI__FUNC_MRG_DI (MTK_PIN_NO(38) | 1) +-#define MT8516_PIN_38_MRG_DI__FUNC_I2S0_DI (MTK_PIN_NO(38) | 3) +-#define MT8516_PIN_38_MRG_DI__FUNC_I2S3_DO (MTK_PIN_NO(38) | 4) +-#define MT8516_PIN_38_MRG_DI__FUNC_PCM0_DI (MTK_PIN_NO(38) | 5) +-#define MT8516_PIN_38_MRG_DI__FUNC_EXT_MDIO (MTK_PIN_NO(38) | 6) +-#define MT8516_PIN_38_MRG_DI__FUNC_DBG_MON_A_4 (MTK_PIN_NO(38) | 7) +- +-#define MT8516_PIN_39_MRG_DO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +-#define MT8516_PIN_39_MRG_DO__FUNC_MRG_DO (MTK_PIN_NO(39) | 1) +-#define MT8516_PIN_39_MRG_DO__FUNC_I2S0_MCK (MTK_PIN_NO(39) | 3) +-#define MT8516_PIN_39_MRG_DO__FUNC_I2S3_MCK (MTK_PIN_NO(39) | 4) +-#define MT8516_PIN_39_MRG_DO__FUNC_PCM0_DO (MTK_PIN_NO(39) | 5) +-#define MT8516_PIN_39_MRG_DO__FUNC_EXT_MDC (MTK_PIN_NO(39) | 6) +-#define MT8516_PIN_39_MRG_DO__FUNC_DBG_MON_A_5 (MTK_PIN_NO(39) | 7) +- +-#define MT8516_PIN_40_KPROW0__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +-#define MT8516_PIN_40_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(40) | 1) +-#define MT8516_PIN_40_KPROW0__FUNC_DBG_MON_B_4 (MTK_PIN_NO(40) | 7) +- +-#define MT8516_PIN_41_KPROW1__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +-#define MT8516_PIN_41_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(41) | 1) +-#define MT8516_PIN_41_KPROW1__FUNC_IDDIG (MTK_PIN_NO(41) | 2) +-#define MT8516_PIN_41_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 3) +-#define MT8516_PIN_41_KPROW1__FUNC_DBG_MON_B_5 (MTK_PIN_NO(41) | 7) +- +-#define MT8516_PIN_42_KPCOL0__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +-#define MT8516_PIN_42_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(42) | 1) +-#define MT8516_PIN_42_KPCOL0__FUNC_DBG_MON_B_6 (MTK_PIN_NO(42) | 7) +- +-#define MT8516_PIN_43_KPCOL1__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +-#define MT8516_PIN_43_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(43) | 1) +-#define MT8516_PIN_43_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(43) | 2) +-#define MT8516_PIN_43_KPCOL1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(43) | 3) +-#define MT8516_PIN_43_KPCOL1__FUNC_TSF_IN (MTK_PIN_NO(43) | 4) +-#define MT8516_PIN_43_KPCOL1__FUNC_DBG_MON_B_7 (MTK_PIN_NO(43) | 7) +- +-#define MT8516_PIN_44_JTMS__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +-#define MT8516_PIN_44_JTMS__FUNC_JTMS (MTK_PIN_NO(44) | 1) +-#define MT8516_PIN_44_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(44) | 2) +-#define MT8516_PIN_44_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(44) | 3) +-#define MT8516_PIN_44_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(44) | 5) +-#define MT8516_PIN_44_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(44) | 6) +- +-#define MT8516_PIN_45_JTCK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +-#define MT8516_PIN_45_JTCK__FUNC_JTCK (MTK_PIN_NO(45) | 1) +-#define MT8516_PIN_45_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(45) | 2) +-#define MT8516_PIN_45_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(45) | 3) +- +-#define MT8516_PIN_46_JTDI__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +-#define MT8516_PIN_46_JTDI__FUNC_JTDI (MTK_PIN_NO(46) | 1) +-#define MT8516_PIN_46_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(46) | 2) +- +-#define MT8516_PIN_47_JTDO__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +-#define MT8516_PIN_47_JTDO__FUNC_JTDO (MTK_PIN_NO(47) | 1) +-#define MT8516_PIN_47_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(47) | 2) +- +-#define MT8516_PIN_48_SPI_CS__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +-#define MT8516_PIN_48_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(48) | 1) +-#define MT8516_PIN_48_SPI_CS__FUNC_I2S0_DI (MTK_PIN_NO(48) | 3) +-#define MT8516_PIN_48_SPI_CS__FUNC_I2S2_BCK (MTK_PIN_NO(48) | 4) +-#define MT8516_PIN_48_SPI_CS__FUNC_DBG_MON_A_23 (MTK_PIN_NO(48) | 7) +- +-#define MT8516_PIN_49_SPI_CK__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +-#define MT8516_PIN_49_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(49) | 1) +-#define MT8516_PIN_49_SPI_CK__FUNC_I2S0_LRCK (MTK_PIN_NO(49) | 3) +-#define MT8516_PIN_49_SPI_CK__FUNC_I2S2_DI (MTK_PIN_NO(49) | 4) +-#define MT8516_PIN_49_SPI_CK__FUNC_DBG_MON_A_24 (MTK_PIN_NO(49) | 7) +- +-#define MT8516_PIN_50_SPI_MI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +-#define MT8516_PIN_50_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(50) | 1) +-#define MT8516_PIN_50_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(50) | 2) +-#define MT8516_PIN_50_SPI_MI__FUNC_I2S0_BCK (MTK_PIN_NO(50) | 3) +-#define MT8516_PIN_50_SPI_MI__FUNC_I2S2_LRCK (MTK_PIN_NO(50) | 4) +-#define MT8516_PIN_50_SPI_MI__FUNC_DBG_MON_A_25 (MTK_PIN_NO(50) | 7) +- +-#define MT8516_PIN_51_SPI_MO__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +-#define MT8516_PIN_51_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(51) | 1) +-#define MT8516_PIN_51_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(51) | 2) +-#define MT8516_PIN_51_SPI_MO__FUNC_I2S0_MCK (MTK_PIN_NO(51) | 3) +-#define MT8516_PIN_51_SPI_MO__FUNC_I2S2_MCK (MTK_PIN_NO(51) | 4) +-#define MT8516_PIN_51_SPI_MO__FUNC_DBG_MON_A_26 (MTK_PIN_NO(51) | 7) +- +-#define MT8516_PIN_52_SDA1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +-#define MT8516_PIN_52_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(52) | 1) +- +-#define MT8516_PIN_53_SCL1__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +-#define MT8516_PIN_53_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(53) | 1) +- +-#define MT8516_PIN_54_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +-#define MT8516_PIN_54_GPIO54__FUNC_PWM_B (MTK_PIN_NO(54) | 2) +-#define MT8516_PIN_54_GPIO54__FUNC_DBG_MON_B_2 (MTK_PIN_NO(54) | 7) +- +-#define MT8516_PIN_55_I2S_DATA_IN__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +-#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(55) | 1) +-#define MT8516_PIN_55_I2S_DATA_IN__FUNC_UCTS0 (MTK_PIN_NO(55) | 2) +-#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(55) | 3) +-#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(55) | 4) +-#define MT8516_PIN_55_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(55) | 5) +-#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S2_BCK (MTK_PIN_NO(55) | 6) +-#define MT8516_PIN_55_I2S_DATA_IN__FUNC_DBG_MON_A_28 (MTK_PIN_NO(55) | 7) +- +-#define MT8516_PIN_56_I2S_LRCK__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +-#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(56) | 1) +-#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(56) | 3) +-#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(56) | 4) +-#define MT8516_PIN_56_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(56) | 5) +-#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S2_DI (MTK_PIN_NO(56) | 6) +-#define MT8516_PIN_56_I2S_LRCK__FUNC_DBG_MON_A_29 (MTK_PIN_NO(56) | 7) +- +-#define MT8516_PIN_57_I2S_BCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +-#define MT8516_PIN_57_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(57) | 1) +-#define MT8516_PIN_57_I2S_BCK__FUNC_URTS0 (MTK_PIN_NO(57) | 2) +-#define MT8516_PIN_57_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(57) | 3) +-#define MT8516_PIN_57_I2S_BCK__FUNC_I2S_8CH_BCK (MTK_PIN_NO(57) | 4) +-#define MT8516_PIN_57_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(57) | 5) +-#define MT8516_PIN_57_I2S_BCK__FUNC_I2S2_LRCK (MTK_PIN_NO(57) | 6) +-#define MT8516_PIN_57_I2S_BCK__FUNC_DBG_MON_A_30 (MTK_PIN_NO(57) | 7) +- +-#define MT8516_PIN_58_SDA0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +-#define MT8516_PIN_58_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(58) | 1) +- +-#define MT8516_PIN_59_SCL0__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +-#define MT8516_PIN_59_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(59) | 1) +- +-#define MT8516_PIN_60_SDA2__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +-#define MT8516_PIN_60_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(60) | 1) +-#define MT8516_PIN_60_SDA2__FUNC_PWM_B (MTK_PIN_NO(60) | 2) +- +-#define MT8516_PIN_61_SCL2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +-#define MT8516_PIN_61_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(61) | 1) +-#define MT8516_PIN_61_SCL2__FUNC_PWM_C (MTK_PIN_NO(61) | 2) +- +-#define MT8516_PIN_62_URXD0__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +-#define MT8516_PIN_62_URXD0__FUNC_URXD0 (MTK_PIN_NO(62) | 1) +-#define MT8516_PIN_62_URXD0__FUNC_UTXD0 (MTK_PIN_NO(62) | 2) +- +-#define MT8516_PIN_63_UTXD0__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +-#define MT8516_PIN_63_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(63) | 1) +-#define MT8516_PIN_63_UTXD0__FUNC_URXD0 (MTK_PIN_NO(63) | 2) +- +-#define MT8516_PIN_64_URXD1__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +-#define MT8516_PIN_64_URXD1__FUNC_URXD1 (MTK_PIN_NO(64) | 1) +-#define MT8516_PIN_64_URXD1__FUNC_UTXD1 (MTK_PIN_NO(64) | 2) +-#define MT8516_PIN_64_URXD1__FUNC_DBG_MON_A_27 (MTK_PIN_NO(64) | 7) +- +-#define MT8516_PIN_65_UTXD1__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +-#define MT8516_PIN_65_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(65) | 1) +-#define MT8516_PIN_65_UTXD1__FUNC_URXD1 (MTK_PIN_NO(65) | 2) +-#define MT8516_PIN_65_UTXD1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(65) | 7) +- +-#define MT8516_PIN_68_MSDC2_CMD__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +-#define MT8516_PIN_68_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(68) | 1) +-#define MT8516_PIN_68_MSDC2_CMD__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(68) | 2) +-#define MT8516_PIN_68_MSDC2_CMD__FUNC_SDA1_0 (MTK_PIN_NO(68) | 3) +-#define MT8516_PIN_68_MSDC2_CMD__FUNC_USB_SDA (MTK_PIN_NO(68) | 5) +-#define MT8516_PIN_68_MSDC2_CMD__FUNC_I2S3_BCK (MTK_PIN_NO(68) | 6) +-#define MT8516_PIN_68_MSDC2_CMD__FUNC_DBG_MON_B_15 (MTK_PIN_NO(68) | 7) +- +-#define MT8516_PIN_69_MSDC2_CLK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +-#define MT8516_PIN_69_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(69) | 1) +-#define MT8516_PIN_69_MSDC2_CLK__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(69) | 2) +-#define MT8516_PIN_69_MSDC2_CLK__FUNC_SCL1_0 (MTK_PIN_NO(69) | 3) +-#define MT8516_PIN_69_MSDC2_CLK__FUNC_USB_SCL (MTK_PIN_NO(69) | 5) +-#define MT8516_PIN_69_MSDC2_CLK__FUNC_I2S3_LRCK (MTK_PIN_NO(69) | 6) +-#define MT8516_PIN_69_MSDC2_CLK__FUNC_DBG_MON_B_16 (MTK_PIN_NO(69) | 7) +- +-#define MT8516_PIN_70_MSDC2_DAT0__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +-#define MT8516_PIN_70_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(70) | 1) +-#define MT8516_PIN_70_MSDC2_DAT0__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(70) | 2) +-#define MT8516_PIN_70_MSDC2_DAT0__FUNC_UTXD0 (MTK_PIN_NO(70) | 5) +-#define MT8516_PIN_70_MSDC2_DAT0__FUNC_I2S3_DO (MTK_PIN_NO(70) | 6) +-#define MT8516_PIN_70_MSDC2_DAT0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(70) | 7) +- +-#define MT8516_PIN_71_MSDC2_DAT1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +-#define MT8516_PIN_71_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(71) | 1) +-#define MT8516_PIN_71_MSDC2_DAT1__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(71) | 2) +-#define MT8516_PIN_71_MSDC2_DAT1__FUNC_PWM_A (MTK_PIN_NO(71) | 3) +-#define MT8516_PIN_71_MSDC2_DAT1__FUNC_I2S3_MCK (MTK_PIN_NO(71) | 4) +-#define MT8516_PIN_71_MSDC2_DAT1__FUNC_URXD0 (MTK_PIN_NO(71) | 5) +-#define MT8516_PIN_71_MSDC2_DAT1__FUNC_PWM_B (MTK_PIN_NO(71) | 6) +-#define MT8516_PIN_71_MSDC2_DAT1__FUNC_DBG_MON_B_18 (MTK_PIN_NO(71) | 7) +- +-#define MT8516_PIN_72_MSDC2_DAT2__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +-#define MT8516_PIN_72_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(72) | 1) +-#define MT8516_PIN_72_MSDC2_DAT2__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(72) | 2) +-#define MT8516_PIN_72_MSDC2_DAT2__FUNC_SDA2_0 (MTK_PIN_NO(72) | 3) +-#define MT8516_PIN_72_MSDC2_DAT2__FUNC_UTXD1 (MTK_PIN_NO(72) | 5) +-#define MT8516_PIN_72_MSDC2_DAT2__FUNC_PWM_C (MTK_PIN_NO(72) | 6) +-#define MT8516_PIN_72_MSDC2_DAT2__FUNC_DBG_MON_B_19 (MTK_PIN_NO(72) | 7) +- +-#define MT8516_PIN_73_MSDC2_DAT3__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +-#define MT8516_PIN_73_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(73) | 1) +-#define MT8516_PIN_73_MSDC2_DAT3__FUNC_I2S_8CH_BCK (MTK_PIN_NO(73) | 2) +-#define MT8516_PIN_73_MSDC2_DAT3__FUNC_SCL2_0 (MTK_PIN_NO(73) | 3) +-#define MT8516_PIN_73_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(73) | 4) +-#define MT8516_PIN_73_MSDC2_DAT3__FUNC_URXD1 (MTK_PIN_NO(73) | 5) +-#define MT8516_PIN_73_MSDC2_DAT3__FUNC_PWM_A (MTK_PIN_NO(73) | 6) +-#define MT8516_PIN_73_MSDC2_DAT3__FUNC_DBG_MON_B_20 (MTK_PIN_NO(73) | 7) +- +-#define MT8516_PIN_74_TDN3__FUNC_GPI74 (MTK_PIN_NO(74) | 0) +-#define MT8516_PIN_74_TDN3__FUNC_TDN3 (MTK_PIN_NO(74) | 1) +- +-#define MT8516_PIN_75_TDP3__FUNC_GPI75 (MTK_PIN_NO(75) | 0) +-#define MT8516_PIN_75_TDP3__FUNC_TDP3 (MTK_PIN_NO(75) | 1) +- +-#define MT8516_PIN_76_TDN2__FUNC_GPI76 (MTK_PIN_NO(76) | 0) +-#define MT8516_PIN_76_TDN2__FUNC_TDN2 (MTK_PIN_NO(76) | 1) +- +-#define MT8516_PIN_77_TDP2__FUNC_GPI77 (MTK_PIN_NO(77) | 0) +-#define MT8516_PIN_77_TDP2__FUNC_TDP2 (MTK_PIN_NO(77) | 1) +- +-#define MT8516_PIN_78_TCN__FUNC_GPI78 (MTK_PIN_NO(78) | 0) +-#define MT8516_PIN_78_TCN__FUNC_TCN (MTK_PIN_NO(78) | 1) +- +-#define MT8516_PIN_79_TCP__FUNC_GPI79 (MTK_PIN_NO(79) | 0) +-#define MT8516_PIN_79_TCP__FUNC_TCP (MTK_PIN_NO(79) | 1) +- +-#define MT8516_PIN_80_TDN1__FUNC_GPI80 (MTK_PIN_NO(80) | 0) +-#define MT8516_PIN_80_TDN1__FUNC_TDN1 (MTK_PIN_NO(80) | 1) +- +-#define MT8516_PIN_81_TDP1__FUNC_GPI81 (MTK_PIN_NO(81) | 0) +-#define MT8516_PIN_81_TDP1__FUNC_TDP1 (MTK_PIN_NO(81) | 1) +- +-#define MT8516_PIN_82_TDN0__FUNC_GPI82 (MTK_PIN_NO(82) | 0) +-#define MT8516_PIN_82_TDN0__FUNC_TDN0 (MTK_PIN_NO(82) | 1) +- +-#define MT8516_PIN_83_TDP0__FUNC_GPI83 (MTK_PIN_NO(83) | 0) +-#define MT8516_PIN_83_TDP0__FUNC_TDP0 (MTK_PIN_NO(83) | 1) +- +-#define MT8516_PIN_84_RDN0__FUNC_GPI84 (MTK_PIN_NO(84) | 0) +-#define MT8516_PIN_84_RDN0__FUNC_RDN0 (MTK_PIN_NO(84) | 1) +- +-#define MT8516_PIN_85_RDP0__FUNC_GPI85 (MTK_PIN_NO(85) | 0) +-#define MT8516_PIN_85_RDP0__FUNC_RDP0 (MTK_PIN_NO(85) | 1) +- +-#define MT8516_PIN_86_RDN1__FUNC_GPI86 (MTK_PIN_NO(86) | 0) +-#define MT8516_PIN_86_RDN1__FUNC_RDN1 (MTK_PIN_NO(86) | 1) +- +-#define MT8516_PIN_87_RDP1__FUNC_GPI87 (MTK_PIN_NO(87) | 0) +-#define MT8516_PIN_87_RDP1__FUNC_RDP1 (MTK_PIN_NO(87) | 1) +- +-#define MT8516_PIN_88_RCN__FUNC_GPI88 (MTK_PIN_NO(88) | 0) +-#define MT8516_PIN_88_RCN__FUNC_RCN (MTK_PIN_NO(88) | 1) +- +-#define MT8516_PIN_89_RCP__FUNC_GPI89 (MTK_PIN_NO(89) | 0) +-#define MT8516_PIN_89_RCP__FUNC_RCP (MTK_PIN_NO(89) | 1) +- +-#define MT8516_PIN_90_RDN2__FUNC_GPI90 (MTK_PIN_NO(90) | 0) +-#define MT8516_PIN_90_RDN2__FUNC_RDN2 (MTK_PIN_NO(90) | 1) +-#define MT8516_PIN_90_RDN2__FUNC_CMDAT8 (MTK_PIN_NO(90) | 2) +- +-#define MT8516_PIN_91_RDP2__FUNC_GPI91 (MTK_PIN_NO(91) | 0) +-#define MT8516_PIN_91_RDP2__FUNC_RDP2 (MTK_PIN_NO(91) | 1) +-#define MT8516_PIN_91_RDP2__FUNC_CMDAT9 (MTK_PIN_NO(91) | 2) +- +-#define MT8516_PIN_92_RDN3__FUNC_GPI92 (MTK_PIN_NO(92) | 0) +-#define MT8516_PIN_92_RDN3__FUNC_RDN3 (MTK_PIN_NO(92) | 1) +-#define MT8516_PIN_92_RDN3__FUNC_CMDAT4 (MTK_PIN_NO(92) | 2) +- +-#define MT8516_PIN_93_RDP3__FUNC_GPI93 (MTK_PIN_NO(93) | 0) +-#define MT8516_PIN_93_RDP3__FUNC_RDP3 (MTK_PIN_NO(93) | 1) +-#define MT8516_PIN_93_RDP3__FUNC_CMDAT5 (MTK_PIN_NO(93) | 2) +- +-#define MT8516_PIN_94_RCN_A__FUNC_GPI94 (MTK_PIN_NO(94) | 0) +-#define MT8516_PIN_94_RCN_A__FUNC_RCN_A (MTK_PIN_NO(94) | 1) +-#define MT8516_PIN_94_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(94) | 2) +- +-#define MT8516_PIN_95_RCP_A__FUNC_GPI95 (MTK_PIN_NO(95) | 0) +-#define MT8516_PIN_95_RCP_A__FUNC_RCP_A (MTK_PIN_NO(95) | 1) +-#define MT8516_PIN_95_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(95) | 2) +- +-#define MT8516_PIN_96_RDN1_A__FUNC_GPI96 (MTK_PIN_NO(96) | 0) +-#define MT8516_PIN_96_RDN1_A__FUNC_RDN1_A (MTK_PIN_NO(96) | 1) +-#define MT8516_PIN_96_RDN1_A__FUNC_CMDAT2 (MTK_PIN_NO(96) | 2) +-#define MT8516_PIN_96_RDN1_A__FUNC_CMCSD2 (MTK_PIN_NO(96) | 3) +- +-#define MT8516_PIN_97_RDP1_A__FUNC_GPI97 (MTK_PIN_NO(97) | 0) +-#define MT8516_PIN_97_RDP1_A__FUNC_RDP1_A (MTK_PIN_NO(97) | 1) +-#define MT8516_PIN_97_RDP1_A__FUNC_CMDAT3 (MTK_PIN_NO(97) | 2) +-#define MT8516_PIN_97_RDP1_A__FUNC_CMCSD3 (MTK_PIN_NO(97) | 3) +- +-#define MT8516_PIN_98_RDN0_A__FUNC_GPI98 (MTK_PIN_NO(98) | 0) +-#define MT8516_PIN_98_RDN0_A__FUNC_RDN0_A (MTK_PIN_NO(98) | 1) +-#define MT8516_PIN_98_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(98) | 2) +- +-#define MT8516_PIN_99_RDP0_A__FUNC_GPI99 (MTK_PIN_NO(99) | 0) +-#define MT8516_PIN_99_RDP0_A__FUNC_RDP0_A (MTK_PIN_NO(99) | 1) +-#define MT8516_PIN_99_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(99) | 2) +- +-#define MT8516_PIN_100_CMDAT0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +-#define MT8516_PIN_100_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(100) | 1) +-#define MT8516_PIN_100_CMDAT0__FUNC_CMCSD0 (MTK_PIN_NO(100) | 2) +-#define MT8516_PIN_100_CMDAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(100) | 3) +-#define MT8516_PIN_100_CMDAT0__FUNC_TDM_RX_MCK (MTK_PIN_NO(100) | 5) +-#define MT8516_PIN_100_CMDAT0__FUNC_DBG_MON_B_21 (MTK_PIN_NO(100) | 7) +- +-#define MT8516_PIN_101_CMDAT1__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +-#define MT8516_PIN_101_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(101) | 1) +-#define MT8516_PIN_101_CMDAT1__FUNC_CMCSD1 (MTK_PIN_NO(101) | 2) +-#define MT8516_PIN_101_CMDAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(101) | 3) +-#define MT8516_PIN_101_CMDAT1__FUNC_CMFLASH (MTK_PIN_NO(101) | 4) +-#define MT8516_PIN_101_CMDAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(101) | 5) +-#define MT8516_PIN_101_CMDAT1__FUNC_DBG_MON_B_22 (MTK_PIN_NO(101) | 7) +- +-#define MT8516_PIN_102_CMMCLK__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +-#define MT8516_PIN_102_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(102) | 1) +-#define MT8516_PIN_102_CMMCLK__FUNC_ANT_SEL4 (MTK_PIN_NO(102) | 3) +-#define MT8516_PIN_102_CMMCLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(102) | 5) +-#define MT8516_PIN_102_CMMCLK__FUNC_DBG_MON_B_23 (MTK_PIN_NO(102) | 7) +- +-#define MT8516_PIN_103_CMPCLK__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +-#define MT8516_PIN_103_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(103) | 1) +-#define MT8516_PIN_103_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(103) | 2) +-#define MT8516_PIN_103_CMPCLK__FUNC_ANT_SEL5 (MTK_PIN_NO(103) | 3) +-#define MT8516_PIN_103_CMPCLK__FUNC_TDM_RX_DI (MTK_PIN_NO(103) | 5) +-#define MT8516_PIN_103_CMPCLK__FUNC_DBG_MON_B_24 (MTK_PIN_NO(103) | 7) +- +-#define MT8516_PIN_104_MSDC1_CMD__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +-#define MT8516_PIN_104_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(104) | 1) +-#define MT8516_PIN_104_MSDC1_CMD__FUNC_SQICS (MTK_PIN_NO(104) | 4) +-#define MT8516_PIN_104_MSDC1_CMD__FUNC_DBG_MON_B_25 (MTK_PIN_NO(104) | 7) +- +-#define MT8516_PIN_105_MSDC1_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +-#define MT8516_PIN_105_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(105) | 1) +-#define MT8516_PIN_105_MSDC1_CLK__FUNC_SQISO (MTK_PIN_NO(105) | 4) +-#define MT8516_PIN_105_MSDC1_CLK__FUNC_DBG_MON_B_26 (MTK_PIN_NO(105) | 7) +- +-#define MT8516_PIN_106_MSDC1_DAT0__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +-#define MT8516_PIN_106_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(106) | 1) +-#define MT8516_PIN_106_MSDC1_DAT0__FUNC_SQISI (MTK_PIN_NO(106) | 4) +-#define MT8516_PIN_106_MSDC1_DAT0__FUNC_DBG_MON_B_27 (MTK_PIN_NO(106) | 7) +- +-#define MT8516_PIN_107_MSDC1_DAT1__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +-#define MT8516_PIN_107_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(107) | 1) +-#define MT8516_PIN_107_MSDC1_DAT1__FUNC_SQIWP (MTK_PIN_NO(107) | 4) +-#define MT8516_PIN_107_MSDC1_DAT1__FUNC_DBG_MON_B_28 (MTK_PIN_NO(107) | 7) +- +-#define MT8516_PIN_108_MSDC1_DAT2__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +-#define MT8516_PIN_108_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(108) | 1) +-#define MT8516_PIN_108_MSDC1_DAT2__FUNC_SQIRST (MTK_PIN_NO(108) | 4) +-#define MT8516_PIN_108_MSDC1_DAT2__FUNC_DBG_MON_B_29 (MTK_PIN_NO(108) | 7) +- +-#define MT8516_PIN_109_MSDC1_DAT3__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +-#define MT8516_PIN_109_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(109) | 1) +-#define MT8516_PIN_109_MSDC1_DAT3__FUNC_SQICK (MTK_PIN_NO(109) | 4) +-#define MT8516_PIN_109_MSDC1_DAT3__FUNC_DBG_MON_B_30 (MTK_PIN_NO(109) | 7) +- +-#define MT8516_PIN_110_MSDC0_DAT7__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +-#define MT8516_PIN_110_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(110) | 1) +-#define MT8516_PIN_110_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(110) | 4) +- +-#define MT8516_PIN_111_MSDC0_DAT6__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +-#define MT8516_PIN_111_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(111) | 1) +-#define MT8516_PIN_111_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(111) | 4) +- +-#define MT8516_PIN_112_MSDC0_DAT5__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +-#define MT8516_PIN_112_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(112) | 1) +-#define MT8516_PIN_112_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(112) | 4) +- +-#define MT8516_PIN_113_MSDC0_DAT4__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +-#define MT8516_PIN_113_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(113) | 1) +-#define MT8516_PIN_113_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(113) | 4) +- +-#define MT8516_PIN_114_MSDC0_RSTB__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +-#define MT8516_PIN_114_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(114) | 1) +-#define MT8516_PIN_114_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(114) | 4) +- +-#define MT8516_PIN_115_MSDC0_CMD__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +-#define MT8516_PIN_115_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(115) | 1) +-#define MT8516_PIN_115_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(115) | 4) +- +-#define MT8516_PIN_116_MSDC0_CLK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +-#define MT8516_PIN_116_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(116) | 1) +-#define MT8516_PIN_116_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(116) | 4) +- +-#define MT8516_PIN_117_MSDC0_DAT3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +-#define MT8516_PIN_117_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(117) | 1) +-#define MT8516_PIN_117_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(117) | 4) +- +-#define MT8516_PIN_118_MSDC0_DAT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +-#define MT8516_PIN_118_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(118) | 1) +-#define MT8516_PIN_118_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(118) | 4) +- +-#define MT8516_PIN_119_MSDC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +-#define MT8516_PIN_119_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(119) | 1) +-#define MT8516_PIN_119_MSDC0_DAT1__FUNC_NLD8 (MTK_PIN_NO(119) | 4) +- +-#define MT8516_PIN_120_MSDC0_DAT0__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +-#define MT8516_PIN_120_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(120) | 1) +-#define MT8516_PIN_120_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(120) | 4) +-#define MT8516_PIN_120_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(120) | 5) +- +-#endif /* __DTS_MT8516_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8516-pumpkin.dts b/scripts/dtc/include-prefixes/arm64/mediatek/mt8516-pumpkin.dts +deleted file mode 100644 +index cce642c53812..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8516-pumpkin.dts ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019 BayLibre, SAS. +- * Author: Fabien Parent +- */ +- +-/dts-v1/; +- +-#include "mt8516.dtsi" +-#include "pumpkin-common.dtsi" +- +-/ { +- model = "Pumpkin MT8516"; +- compatible = "mediatek,mt8516"; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0 0x40000000 0 0x40000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/mt8516.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/mt8516.dtsi +deleted file mode 100644 +index bbe5a1419eff..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/mt8516.dtsi ++++ /dev/null +@@ -1,543 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019 MediaTek Inc. +- * Copyright (c) 2019 BayLibre, SAS. +- * Author: Fabien Parent +- */ +- +-#include +-#include +-#include +-#include +- +-#include "mt8516-pinfunc.h" +- +-/ { +- compatible = "mediatek,mt8516"; +- interrupt-parent = <&sysirq>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cluster0_opp: opp-table-0 { +- compatible = "operating-points-v2"; +- opp-shared; +- opp-598000000 { +- opp-hz = /bits/ 64 <598000000>; +- opp-microvolt = <1150000>; +- }; +- opp-747500000 { +- opp-hz = /bits/ 64 <747500000>; +- opp-microvolt = <1150000>; +- }; +- opp-1040000000 { +- opp-hz = /bits/ 64 <1040000000>; +- opp-microvolt = <1200000>; +- }; +- opp-1196000000 { +- opp-hz = /bits/ 64 <1196000000>; +- opp-microvolt = <1250000>; +- }; +- opp-1300000000 { +- opp-hz = /bits/ 64 <1300000000>; +- opp-microvolt = <1300000>; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x0>; +- enable-method = "psci"; +- cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, +- <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; +- clocks = <&infracfg CLK_IFR_MUX1_SEL>, +- <&topckgen CLK_TOP_MAINPLL_D2>; +- clock-names = "cpu", "intermediate"; +- operating-points-v2 = <&cluster0_opp>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x1>; +- enable-method = "psci"; +- cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, +- <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; +- clocks = <&infracfg CLK_IFR_MUX1_SEL>, +- <&topckgen CLK_TOP_MAINPLL_D2>; +- clock-names = "cpu", "intermediate"; +- operating-points-v2 = <&cluster0_opp>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x2>; +- enable-method = "psci"; +- cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, +- <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; +- clocks = <&infracfg CLK_IFR_MUX1_SEL>, +- <&topckgen CLK_TOP_MAINPLL_D2>; +- clock-names = "cpu", "intermediate"; +- operating-points-v2 = <&cluster0_opp>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x3>; +- enable-method = "psci"; +- cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, +- <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; +- clocks = <&infracfg CLK_IFR_MUX1_SEL>, +- <&topckgen CLK_TOP_MAINPLL_D2>; +- clock-names = "cpu", "intermediate", "armpll"; +- operating-points-v2 = <&cluster0_opp>; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP_0_0: cpu-sleep-0-0 { +- compatible = "arm,idle-state"; +- entry-latency-us = <600>; +- exit-latency-us = <600>; +- min-residency-us = <1200>; +- arm,psci-suspend-param = <0x0010000>; +- }; +- +- CLUSTER_SLEEP_0: cluster-sleep-0 { +- compatible = "arm,idle-state"; +- entry-latency-us = <800>; +- exit-latency-us = <1000>; +- min-residency-us = <2000>; +- arm,psci-suspend-param = <0x2010000>; +- }; +- }; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- clk26m: clk26m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- clock-output-names = "clk26m"; +- }; +- +- clk32k: clk32k { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32000>; +- clock-output-names = "clk32k"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ +- bl31_secmon_reserved: secmon@43000000 { +- no-map; +- reg = <0 0x43000000 0 0x20000>; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- soc { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "simple-bus"; +- ranges; +- +- topckgen: topckgen@10000000 { +- compatible = "mediatek,mt8516-topckgen", "syscon"; +- reg = <0 0x10000000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- infracfg: infracfg@10001000 { +- compatible = "mediatek,mt8516-infracfg", "syscon"; +- reg = <0 0x10001000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- pericfg: pericfg@10003050 { +- compatible = "mediatek,mt8516-pericfg", "syscon"; +- reg = <0 0x10003050 0 0x1000>; +- }; +- +- apmixedsys: apmixedsys@10018000 { +- compatible = "mediatek,mt8516-apmixedsys", "syscon"; +- reg = <0 0x10018000 0 0x710>; +- #clock-cells = <1>; +- }; +- +- toprgu: toprgu@10007000 { +- compatible = "mediatek,mt8516-wdt", +- "mediatek,mt6589-wdt"; +- reg = <0 0x10007000 0 0x1000>; +- interrupts = ; +- #reset-cells = <1>; +- }; +- +- timer: timer@10008000 { +- compatible = "mediatek,mt8516-timer", +- "mediatek,mt6577-timer"; +- reg = <0 0x10008000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_CLK26M_D2>, +- <&topckgen CLK_TOP_APXGPT>; +- clock-names = "clk13m", "bus"; +- }; +- +- syscfg_pctl: syscfg-pctl@10005000 { +- compatible = "syscon"; +- reg = <0 0x10005000 0 0x1000>; +- }; +- +- pio: pinctrl@1000b000 { +- compatible = "mediatek,mt8516-pinctrl"; +- reg = <0 0x1000b000 0 0x1000>; +- mediatek,pctl-regmap = <&syscfg_pctl>; +- pins-are-numbered; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- +- efuse: efuse@10009000 { +- compatible = "mediatek,mt8516-efuse", "mediatek,efuse"; +- reg = <0 0x10009000 0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- pwrap: pwrap@1000f000 { +- compatible = "mediatek,mt8516-pwrap"; +- reg = <0 0x1000f000 0 0x1000>; +- reg-names = "pwrap"; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_PMICWRAP_26M>, +- <&topckgen CLK_TOP_PMICWRAP_AP>; +- clock-names = "spi", "wrap"; +- }; +- +- sysirq: interrupt-controller@10200620 { +- compatible = "mediatek,mt8516-sysirq", +- "mediatek,mt6577-sysirq"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- reg = <0 0x10200620 0 0x20>; +- }; +- +- gic: interrupt-controller@10310000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- interrupt-controller; +- reg = <0 0x10310000 0 0x1000>, +- <0 0x10320000 0 0x1000>, +- <0 0x10340000 0 0x2000>, +- <0 0x10360000 0 0x2000>; +- interrupts = ; +- }; +- +- apdma: dma-controller@11000480 { +- compatible = "mediatek,mt8516-uart-dma", +- "mediatek,mt6577-uart-dma"; +- reg = <0 0x11000480 0 0x80>, +- <0 0x11000500 0 0x80>, +- <0 0x11000580 0 0x80>, +- <0 0x11000600 0 0x80>, +- <0 0x11000980 0 0x80>, +- <0 0x11000a00 0 0x80>; +- interrupts = , +- , +- , +- , +- , +- ; +- dma-requests = <6>; +- clocks = <&topckgen CLK_TOP_APDMA>; +- clock-names = "apdma"; +- #dma-cells = <1>; +- }; +- +- uart0: serial@11005000 { +- compatible = "mediatek,mt8516-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11005000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_UART0_SEL>, +- <&topckgen CLK_TOP_UART0>; +- clock-names = "baud", "bus"; +- dmas = <&apdma 0 +- &apdma 1>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- uart1: serial@11006000 { +- compatible = "mediatek,mt8516-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11006000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_UART1_SEL>, +- <&topckgen CLK_TOP_UART1>; +- clock-names = "baud", "bus"; +- dmas = <&apdma 2 +- &apdma 3>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- uart2: serial@11007000 { +- compatible = "mediatek,mt8516-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11007000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_UART2_SEL>, +- <&topckgen CLK_TOP_UART2>; +- clock-names = "baud", "bus"; +- dmas = <&apdma 4 +- &apdma 5>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- i2c0: i2c@11009000 { +- compatible = "mediatek,mt8516-i2c", +- "mediatek,mt2712-i2c"; +- reg = <0 0x11009000 0 0x90>, +- <0 0x11000180 0 0x80>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, +- <&infracfg CLK_IFR_I2C0_SEL>, +- <&topckgen CLK_TOP_I2C0>, +- <&topckgen CLK_TOP_APDMA>; +- clock-names = "main-source", +- "main-sel", +- "main", +- "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@1100a000 { +- compatible = "mediatek,mt8516-i2c", +- "mediatek,mt2712-i2c"; +- reg = <0 0x1100a000 0 0x90>, +- <0 0x11000200 0 0x80>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, +- <&infracfg CLK_IFR_I2C1_SEL>, +- <&topckgen CLK_TOP_I2C1>, +- <&topckgen CLK_TOP_APDMA>; +- clock-names = "main-source", +- "main-sel", +- "main", +- "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@1100b000 { +- compatible = "mediatek,mt8516-i2c", +- "mediatek,mt2712-i2c"; +- reg = <0 0x1100b000 0 0x90>, +- <0 0x11000280 0 0x80>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, +- <&infracfg CLK_IFR_I2C2_SEL>, +- <&topckgen CLK_TOP_I2C2>, +- <&topckgen CLK_TOP_APDMA>; +- clock-names = "main-source", +- "main-sel", +- "main", +- "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi: spi@1100c000 { +- compatible = "mediatek,mt8516-spi", +- "mediatek,mt2712-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x1100c000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_UNIVPLL_D12>, +- <&topckgen CLK_TOP_SPI_SEL>, +- <&topckgen CLK_TOP_SPI>; +- clock-names = "parent-clk", "sel-clk", "spi-clk"; +- status = "disabled"; +- }; +- +- mmc0: mmc@11120000 { +- compatible = "mediatek,mt8516-mmc"; +- reg = <0 0x11120000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_MSDC0>, +- <&topckgen CLK_TOP_AHB_INFRA_SEL>, +- <&topckgen CLK_TOP_MSDC0_INFRA>; +- clock-names = "source", "hclk", "source_cg"; +- status = "disabled"; +- }; +- +- mmc1: mmc@11130000 { +- compatible = "mediatek,mt8516-mmc"; +- reg = <0 0x11130000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_MSDC1>, +- <&topckgen CLK_TOP_AHB_INFRA_SEL>, +- <&topckgen CLK_TOP_MSDC1_INFRA>; +- clock-names = "source", "hclk", "source_cg"; +- status = "disabled"; +- }; +- +- mmc2: mmc@11170000 { +- compatible = "mediatek,mt8516-mmc"; +- reg = <0 0x11170000 0 0x1000>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_MSDC2>, +- <&topckgen CLK_TOP_RG_MSDC2>, +- <&topckgen CLK_TOP_MSDC2_INFRA>; +- clock-names = "source", "hclk", "source_cg"; +- status = "disabled"; +- }; +- +- ethernet: ethernet@11180000 { +- compatible = "mediatek,mt8516-eth"; +- reg = <0 0x11180000 0 0x1000>; +- mediatek,pericfg = <&pericfg>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_RG_ETH>, +- <&topckgen CLK_TOP_66M_ETH>, +- <&topckgen CLK_TOP_133M_ETH>; +- clock-names = "core", "reg", "trans"; +- status = "disabled"; +- }; +- +- rng: rng@1020c000 { +- compatible = "mediatek,mt8516-rng", +- "mediatek,mt7623-rng"; +- reg = <0 0x1020c000 0 0x100>; +- clocks = <&topckgen CLK_TOP_TRNG>; +- clock-names = "rng"; +- }; +- +- pwm: pwm@11008000 { +- compatible = "mediatek,mt8516-pwm"; +- reg = <0 0x11008000 0 0x1000>; +- #pwm-cells = <2>; +- interrupts = ; +- clocks = <&topckgen CLK_TOP_PWM>, +- <&topckgen CLK_TOP_PWM_B>, +- <&topckgen CLK_TOP_PWM1_FB>, +- <&topckgen CLK_TOP_PWM2_FB>, +- <&topckgen CLK_TOP_PWM3_FB>, +- <&topckgen CLK_TOP_PWM4_FB>, +- <&topckgen CLK_TOP_PWM5_FB>; +- clock-names = "top", "main", "pwm1", "pwm2", "pwm3", +- "pwm4", "pwm5"; +- }; +- +- usb0: usb@11100000 { +- compatible = "mediatek,mt8516-musb", "mediatek,mtk-musb"; +- reg = <0 0x11100000 0 0x1000>; +- interrupts = ; +- interrupt-names = "mc"; +- phys = <&usb0_port PHY_TYPE_USB2>; +- clocks = <&topckgen CLK_TOP_USB>, +- <&topckgen CLK_TOP_USBIF>, +- <&topckgen CLK_TOP_USB_1P>; +- clock-names = "main","mcu","univpll"; +- status = "disabled"; +- }; +- +- usb1: usb@11190000 { +- compatible = "mediatek,mt8516-musb", "mediatek,mtk-musb"; +- reg = <0 0x11190000 0 0x1000>; +- interrupts = ; +- interrupt-names = "mc"; +- phys = <&usb1_port PHY_TYPE_USB2>; +- clocks = <&topckgen CLK_TOP_USB>, +- <&topckgen CLK_TOP_USBIF>, +- <&topckgen CLK_TOP_USB_1P>; +- clock-names = "main","mcu","univpll"; +- dr_mode = "host"; +- status = "disabled"; +- }; +- +- usb_phy: t-phy@11110000 { +- compatible = "mediatek,mt8516-tphy", +- "mediatek,generic-tphy-v1"; +- reg = <0 0x11110000 0 0x800>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "disabled"; +- +- usb0_port: usb-phy@11110800 { +- reg = <0 0x11110800 0 0x100>; +- clocks = <&topckgen CLK_TOP_USB_PHY48M>; +- clock-names = "ref"; +- #phy-cells = <1>; +- }; +- +- usb1_port: usb-phy@11110900 { +- reg = <0 0x11110900 0 0x100>; +- clocks = <&topckgen CLK_TOP_USB_PHY48M>; +- clock-names = "ref"; +- #phy-cells = <1>; +- }; +- }; +- +- auxadc: adc@11003000 { +- compatible = "mediatek,mt8516-auxadc", +- "mediatek,mt8173-auxadc"; +- reg = <0 0x11003000 0 0x1000>; +- clocks = <&topckgen CLK_TOP_AUX_ADC>; +- clock-names = "main"; +- #io-channel-cells = <1>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/mediatek/pumpkin-common.dtsi b/scripts/dtc/include-prefixes/arm64/mediatek/pumpkin-common.dtsi +deleted file mode 100644 +index fcddec14738d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/mediatek/pumpkin-common.dtsi ++++ /dev/null +@@ -1,256 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019 BayLibre, SAS. +- * Author: Fabien Parent +- */ +- +-#include +- +-/ { +- aliases { +- serial0 = &uart0; +- ethernet0 = ðernet; +- }; +- +- chosen { +- stdout-path = "serial0:921600n8"; +- }; +- +- firmware { +- optee: optee@4fd00000 { +- compatible = "linaro,optee-tz"; +- method = "smc"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- input-name = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_default>; +- +- volume-up { +- gpios = <&pio 42 GPIO_ACTIVE_LOW>; +- label = "volume_up"; +- linux,code = <115>; +- wakeup-source; +- debounce-interval = <15>; +- }; +- +- volume-down { +- gpios = <&pio 43 GPIO_ACTIVE_LOW>; +- label = "volume_down"; +- linux,code = <114>; +- wakeup-source; +- debounce-interval = <15>; +- }; +- }; +-}; +- +-&i2c0 { +- clock-div = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins_a>; +- status = "okay"; +- +- tca6416: gpio@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- reset-gpios = <&pio 65 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tca6416_pins>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- eint20-mux-sel0-hog { +- gpio-hog; +- gpios = <0 0>; +- input; +- line-name = "eint20_mux_sel0"; +- }; +- +- expcon-mux-sel1-hog { +- gpio-hog; +- gpios = <1 0>; +- input; +- line-name = "expcon_mux_sel1"; +- }; +- +- mrg-di-mux-sel2-hog { +- gpio-hog; +- gpios = <2 0>; +- input; +- line-name = "mrg_di_mux_sel2"; +- }; +- +- sd-sdio-mux-sel3-hog { +- gpio-hog; +- gpios = <3 0>; +- input; +- line-name = "sd_sdio_mux_sel3"; +- }; +- +- sd-sdio-mux-ctrl7-hog { +- gpio-hog; +- gpios = <7 0>; +- output-low; +- line-name = "sd_sdio_mux_ctrl7"; +- }; +- +- hw-id0-hog { +- gpio-hog; +- gpios = <8 0>; +- input; +- line-name = "hw_id0"; +- }; +- +- hw-id1-hog { +- gpio-hog; +- gpios = <9 0>; +- input; +- line-name = "hw_id1"; +- }; +- +- hw-id2-hog { +- gpio-hog; +- gpios = <10 0>; +- input; +- line-name = "hw_id2"; +- }; +- +- fg-int-n-hog { +- gpio-hog; +- gpios = <11 0>; +- input; +- line-name = "fg_int_n"; +- }; +- +- usba-pwr-en-hog { +- gpio-hog; +- gpios = <12 0>; +- output-high; +- line-name = "usba_pwr_en"; +- }; +- +- wifi-3v3-pg-hog { +- gpio-hog; +- gpios = <13 0>; +- input; +- line-name = "wifi_3v3_pg"; +- }; +- +- cam-rst-hog { +- gpio-hog; +- gpios = <14 0>; +- output-low; +- line-name = "cam_rst"; +- }; +- +- cam-pwdn-hog { +- gpio-hog; +- gpios = <15 0>; +- output-low; +- line-name = "cam_pwdn"; +- }; +- }; +-}; +- +-&i2c2 { +- clock-div = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins_a>; +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-ðernet { +- pinctrl-names = "default"; +- pinctrl-0 = <ðernet_pins_default>; +- phy-handle = <ð_phy>; +- phy-mode = "rmii"; +- mac-address = [00 00 00 00 00 00]; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- eth_phy: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +-}; +- +-&usb0 { +- status = "okay"; +- dr_mode = "peripheral"; +- usb-role-switch; +- +- usb_con: connector { +- compatible = "usb-c-connector"; +- label = "USB-C"; +- }; +-}; +- +-&usb_phy { +- status = "okay"; +-}; +- +-&pio { +- gpio_keys_default: gpiodefault { +- pins_cmd_dat { +- pinmux = , +- ; +- bias-pull-up; +- input-enable; +- }; +- }; +- +- i2c0_pins_a: i2c0@0 { +- pins1 { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- i2c2_pins_a: i2c2@0 { +- pins1 { +- pinmux = , +- ; +- bias-disable; +- }; +- }; +- +- tca6416_pins: pinmux_tca6416_pins { +- gpio_mux_rst_n_pin { +- pinmux = ; +- output-high; +- }; +- +- gpio_mux_int_n_pin { +- pinmux = ; +- input-enable; +- bias-pull-up; +- }; +- }; +- +- ethernet_pins_default: ethernet { +- pins_ethernet { +- pinmux = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/microchip/Makefile b/scripts/dtc/include-prefixes/arm64/microchip/Makefile +deleted file mode 100644 +index c6e0313eea0f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/microchip/Makefile ++++ /dev/null +@@ -1,4 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb +-dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb +-dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/microchip/sparx5.dtsi b/scripts/dtc/include-prefixes/arm64/microchip/sparx5.dtsi +deleted file mode 100644 +index 787ebcec121d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/microchip/sparx5.dtsi ++++ /dev/null +@@ -1,481 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "microchip,sparx5"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <1>; +- +- aliases { +- spi0 = &spi0; +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- }; +- }; +- cpu0: cpu@0 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- next-level-cache = <&L2_0>; +- }; +- cpu1: cpu@1 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- next-level-cache = <&L2_0>; +- }; +- L2_0: l2-cache0 { +- compatible = "cache"; +- }; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = ; +- interrupt-affinity = <&cpu0>, <&cpu1>; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- lcpll_clk: lcpll-clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <2500000000>; +- }; +- +- clks: clock-controller@61110000c { +- compatible = "microchip,sparx5-dpll"; +- #clock-cells = <1>; +- clocks = <&lcpll_clk>; +- reg = <0x6 0x1110000c 0x24>; +- }; +- +- ahb_clk: ahb-clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <250000000>; +- }; +- +- sys_clk: sys-clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <625000000>; +- }; +- +- axi: axi@600000000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- +- gic: interrupt-controller@600300000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-controller; +- reg = <0x6 0x00300000 0x10000>, /* GIC Dist */ +- <0x6 0x00340000 0xc0000>, /* GICR */ +- <0x6 0x00200000 0x2000>, /* GICC */ +- <0x6 0x00210000 0x2000>, /* GICV */ +- <0x6 0x00220000 0x2000>; /* GICH */ +- interrupts = ; +- }; +- +- cpu_ctrl: syscon@600000000 { +- compatible = "microchip,sparx5-cpu-syscon", "syscon", +- "simple-mfd"; +- reg = <0x6 0x00000000 0xd0>; +- mux: mux-controller { +- compatible = "mmio-mux"; +- #mux-control-cells = <0>; +- /* +- * SI_OWNER and SI2_OWNER in GENERAL_CTRL +- * SPI: value 9 - (SIMC,SIBM) = 0b1001 +- * SPI2: value 6 - (SIBM,SIMC) = 0b0110 +- */ +- mux-reg-masks = <0x88 0xf0>; +- }; +- }; +- +- reset: reset-controller@611010008 { +- compatible = "microchip,sparx5-switch-reset"; +- reg = <0x6 0x11010008 0x4>; +- reg-names = "gcb"; +- #reset-cells = <1>; +- cpu-syscon = <&cpu_ctrl>; +- }; +- +- uart0: serial@600100000 { +- pinctrl-0 = <&uart_pins>; +- pinctrl-names = "default"; +- compatible = "ns16550a"; +- reg = <0x6 0x00100000 0x20>; +- clocks = <&ahb_clk>; +- reg-io-width = <4>; +- reg-shift = <2>; +- interrupts = ; +- +- status = "disabled"; +- }; +- +- uart1: serial@600102000 { +- pinctrl-0 = <&uart2_pins>; +- pinctrl-names = "default"; +- compatible = "ns16550a"; +- reg = <0x6 0x00102000 0x20>; +- clocks = <&ahb_clk>; +- reg-io-width = <4>; +- reg-shift = <2>; +- interrupts = ; +- +- status = "disabled"; +- }; +- +- spi0: spi@600104000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "microchip,sparx5-spi"; +- reg = <0x6 0x00104000 0x40>; +- num-cs = <16>; +- reg-io-width = <4>; +- reg-shift = <2>; +- clocks = <&ahb_clk>; +- interrupts = ; +- status = "disabled"; +- }; +- +- timer1: timer@600105000 { +- compatible = "snps,dw-apb-timer"; +- reg = <0x6 0x00105000 0x1000>; +- clocks = <&ahb_clk>; +- clock-names = "timer"; +- interrupts = ; +- }; +- +- sdhci0: mmc@600800000 { +- compatible = "microchip,dw-sparx5-sdhci"; +- status = "disabled"; +- reg = <0x6 0x00800000 0x1000>; +- pinctrl-0 = <&emmc_pins>; +- pinctrl-names = "default"; +- clocks = <&clks CLK_ID_AUX1>; +- clock-names = "core"; +- assigned-clocks = <&clks CLK_ID_AUX1>; +- assigned-clock-rates = <800000000>; +- interrupts = ; +- bus-width = <8>; +- }; +- +- gpio: pinctrl@6110101e0 { +- compatible = "microchip,sparx5-pinctrl"; +- reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&gpio 0 0 64>; +- interrupt-controller; +- interrupts = ; +- #interrupt-cells = <2>; +- +- cs1_pins: cs1-pins { +- pins = "GPIO_16"; +- function = "si"; +- }; +- +- cs2_pins: cs2-pins { +- pins = "GPIO_17"; +- function = "si"; +- }; +- +- cs3_pins: cs3-pins { +- pins = "GPIO_18"; +- function = "si"; +- }; +- +- si2_pins: si2-pins { +- pins = "GPIO_39", "GPIO_40", "GPIO_41"; +- function = "si2"; +- }; +- +- sgpio0_pins: sgpio-pins { +- pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; +- function = "sg0"; +- }; +- +- sgpio1_pins: sgpio1-pins { +- pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13"; +- function = "sg1"; +- }; +- +- sgpio2_pins: sgpio2-pins { +- pins = "GPIO_30", "GPIO_31", "GPIO_32", +- "GPIO_33"; +- function = "sg2"; +- }; +- +- uart_pins: uart-pins { +- pins = "GPIO_10", "GPIO_11"; +- function = "uart"; +- }; +- +- uart2_pins: uart2-pins { +- pins = "GPIO_26", "GPIO_27"; +- function = "uart2"; +- }; +- +- i2c_pins: i2c-pins { +- pins = "GPIO_14", "GPIO_15"; +- function = "twi"; +- }; +- +- i2c2_pins: i2c2-pins { +- pins = "GPIO_28", "GPIO_29"; +- function = "twi2"; +- }; +- +- emmc_pins: emmc-pins { +- pins = "GPIO_34", "GPIO_35", "GPIO_36", +- "GPIO_37", "GPIO_38", "GPIO_39", +- "GPIO_40", "GPIO_41", "GPIO_42", +- "GPIO_43", "GPIO_44", "GPIO_45", +- "GPIO_46", "GPIO_47"; +- function = "emmc"; +- }; +- +- miim1_pins: miim1-pins { +- pins = "GPIO_56", "GPIO_57"; +- function = "miim"; +- }; +- +- miim2_pins: miim2-pins { +- pins = "GPIO_58", "GPIO_59"; +- function = "miim"; +- }; +- +- miim3_pins: miim3-pins { +- pins = "GPIO_52", "GPIO_53"; +- function = "miim"; +- }; +- }; +- +- sgpio0: gpio@61101036c { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "microchip,sparx5-sgpio"; +- status = "disabled"; +- clocks = <&sys_clk>; +- pinctrl-0 = <&sgpio0_pins>; +- pinctrl-names = "default"; +- resets = <&reset 0>; +- reset-names = "switch"; +- reg = <0x6 0x1101036c 0x100>; +- sgpio_in0: gpio@0 { +- compatible = "microchip,sparx5-sgpio-bank"; +- reg = <0>; +- gpio-controller; +- #gpio-cells = <3>; +- ngpios = <96>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- sgpio_out0: gpio@1 { +- compatible = "microchip,sparx5-sgpio-bank"; +- reg = <1>; +- gpio-controller; +- #gpio-cells = <3>; +- ngpios = <96>; +- }; +- }; +- +- sgpio1: gpio@611010484 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "microchip,sparx5-sgpio"; +- status = "disabled"; +- clocks = <&sys_clk>; +- pinctrl-0 = <&sgpio1_pins>; +- pinctrl-names = "default"; +- resets = <&reset 0>; +- reset-names = "switch"; +- reg = <0x6 0x11010484 0x100>; +- sgpio_in1: gpio@0 { +- compatible = "microchip,sparx5-sgpio-bank"; +- reg = <0>; +- gpio-controller; +- #gpio-cells = <3>; +- ngpios = <96>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- sgpio_out1: gpio@1 { +- compatible = "microchip,sparx5-sgpio-bank"; +- reg = <1>; +- gpio-controller; +- #gpio-cells = <3>; +- ngpios = <96>; +- }; +- }; +- +- sgpio2: gpio@61101059c { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "microchip,sparx5-sgpio"; +- status = "disabled"; +- clocks = <&sys_clk>; +- pinctrl-0 = <&sgpio2_pins>; +- pinctrl-names = "default"; +- resets = <&reset 0>; +- reset-names = "switch"; +- reg = <0x6 0x1101059c 0x100>; +- sgpio_in2: gpio@0 { +- reg = <0>; +- compatible = "microchip,sparx5-sgpio-bank"; +- gpio-controller; +- #gpio-cells = <3>; +- ngpios = <96>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- sgpio_out2: gpio@1 { +- compatible = "microchip,sparx5-sgpio-bank"; +- reg = <1>; +- gpio-controller; +- #gpio-cells = <3>; +- ngpios = <96>; +- }; +- }; +- +- i2c0: i2c@600101000 { +- compatible = "snps,designware-i2c"; +- status = "disabled"; +- pinctrl-0 = <&i2c_pins>; +- pinctrl-names = "default"; +- reg = <0x6 0x00101000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- i2c-sda-hold-time-ns = <300>; +- clock-frequency = <100000>; +- clocks = <&ahb_clk>; +- }; +- +- i2c1: i2c@600103000 { +- compatible = "snps,designware-i2c"; +- status = "disabled"; +- pinctrl-0 = <&i2c2_pins>; +- pinctrl-names = "default"; +- reg = <0x6 0x00103000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- i2c-sda-hold-time-ns = <300>; +- clock-frequency = <100000>; +- clocks = <&ahb_clk>; +- }; +- +- tmon0: tmon@610508110 { +- compatible = "microchip,sparx5-temp"; +- reg = <0x6 0x10508110 0xc>; +- #thermal-sensor-cells = <0>; +- clocks = <&ahb_clk>; +- }; +- +- mdio0: mdio@6110102b0 { +- compatible = "mscc,ocelot-miim"; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x6 0x110102b0 0x24>; +- }; +- +- mdio1: mdio@6110102d4 { +- compatible = "mscc,ocelot-miim"; +- status = "disabled"; +- pinctrl-0 = <&miim1_pins>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x6 0x110102d4 0x24>; +- }; +- +- mdio2: mdio@6110102f8 { +- compatible = "mscc,ocelot-miim"; +- status = "disabled"; +- pinctrl-0 = <&miim2_pins>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x6 0x110102d4 0x24>; +- }; +- +- mdio3: mdio@61101031c { +- compatible = "mscc,ocelot-miim"; +- status = "disabled"; +- pinctrl-0 = <&miim3_pins>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x6 0x1101031c 0x24>; +- }; +- +- serdes: serdes@10808000 { +- compatible = "microchip,sparx5-serdes"; +- #phy-cells = <1>; +- clocks = <&sys_clk>; +- reg = <0x6 0x10808000 0x5d0000>; +- }; +- +- switch: switch@0x600000000 { +- compatible = "microchip,sparx5-switch"; +- reg = <0x6 0 0x401000>, +- <0x6 0x10004000 0x7fc000>, +- <0x6 0x11010000 0xaf0000>; +- reg-names = "cpu", "dev", "gcb"; +- interrupt-names = "xtr", "fdma"; +- interrupts = , +- ; +- resets = <&reset 0>; +- reset-names = "switch"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/microchip/sparx5_nand.dtsi b/scripts/dtc/include-prefixes/arm64/microchip/sparx5_nand.dtsi +deleted file mode 100644 +index 03f107e427d7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/microchip/sparx5_nand.dtsi ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. +- */ +- +-&gpio { +- cs14_pins: cs14-pins { +- pins = "GPIO_44"; +- function = "si"; +- }; +-}; +- +-&spi0 { +- pinctrl-0 = <&si2_pins>; +- pinctrl-names = "default"; +- spi@e { +- compatible = "spi-mux"; +- mux-controls = <&mux>; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <14>; /* CS14 */ +- spi-flash@6 { +- compatible = "spi-nand"; +- pinctrl-0 = <&cs14_pins>; +- pinctrl-names = "default"; +- reg = <0x6>; /* SPI2 */ +- spi-max-frequency = <42000000>; +- rx-sample-delay-ns = <7>; /* Tune for speed */ +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb125.dts b/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb125.dts +deleted file mode 100644 +index 9baa085d7861..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb125.dts ++++ /dev/null +@@ -1,79 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. +- */ +- +-/dts-v1/; +-#include "sparx5_pcb_common.dtsi" +- +-/ { +- model = "Sparx5 PCB125 Reference Board"; +- compatible = "microchip,sparx5-pcb125", "microchip,sparx5"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x10000000>; +- }; +-}; +- +-&gpio { +- emmc_pins: emmc-pins { +- /* NB: No "GPIO_35", "GPIO_36", "GPIO_37" +- * (N/A: CARD_nDETECT, CARD_WP, CARD_LED) +- */ +- pins = "GPIO_34", "GPIO_38", "GPIO_39", +- "GPIO_40", "GPIO_41", "GPIO_42", +- "GPIO_43", "GPIO_44", "GPIO_45", +- "GPIO_46", "GPIO_47"; +- drive-strength = <3>; +- function = "emmc"; +- }; +-}; +- +-&sdhci0 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- pinctrl-0 = <&emmc_pins>; +- max-frequency = <8000000>; +- microchip,clock-delay = <10>; +-}; +- +-&spi0 { +- status = "okay"; +- spi@0 { +- compatible = "spi-mux"; +- mux-controls = <&mux>; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; /* CS0 */ +- spi-flash@9 { +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <8000000>; +- reg = <0x9>; /* SPI */ +- }; +- }; +- spi@1 { +- compatible = "spi-mux"; +- mux-controls = <&mux 0>; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; /* CS1 */ +- spi-flash@9 { +- compatible = "spi-nand"; +- pinctrl-0 = <&cs1_pins>; +- pinctrl-names = "default"; +- spi-max-frequency = <8000000>; +- reg = <0x9>; /* SPI */ +- }; +- }; +-}; +- +-&sgpio0 { +- status = "okay"; +- microchip,sgpio-port-ranges = <0 23>; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb134.dts b/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb134.dts +deleted file mode 100644 +index 45ca1af7e850..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb134.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. +- */ +- +-/dts-v1/; +-#include "sparx5_pcb134_board.dtsi" +-#include "sparx5_nand.dtsi" +- +-/ { +- model = "Sparx5 PCB134 Reference Board (NAND)"; +- compatible = "microchip,sparx5-pcb134", "microchip,sparx5"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x10000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb134_board.dtsi b/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb134_board.dtsi +deleted file mode 100644 +index 33faf1f3264f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb134_board.dtsi ++++ /dev/null +@@ -1,907 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. +- */ +- +-/dts-v1/; +-#include "sparx5_pcb_common.dtsi" +- +-/{ +- gpio-restart { +- compatible = "gpio-restart"; +- gpios = <&gpio 37 GPIO_ACTIVE_LOW>; +- priority = <200>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led@0 { +- label = "twr0:green"; +- gpios = <&sgpio_out0 8 0 GPIO_ACTIVE_LOW>; +- }; +- led@1 { +- label = "twr0:yellow"; +- gpios = <&sgpio_out0 8 1 GPIO_ACTIVE_LOW>; +- }; +- led@2 { +- label = "twr1:green"; +- gpios = <&sgpio_out0 9 0 GPIO_ACTIVE_LOW>; +- }; +- led@3 { +- label = "twr1:yellow"; +- gpios = <&sgpio_out0 9 1 GPIO_ACTIVE_LOW>; +- }; +- led@4 { +- label = "twr2:green"; +- gpios = <&sgpio_out0 10 0 GPIO_ACTIVE_LOW>; +- }; +- led@5 { +- label = "twr2:yellow"; +- gpios = <&sgpio_out0 10 1 GPIO_ACTIVE_LOW>; +- }; +- led@6 { +- label = "twr3:green"; +- gpios = <&sgpio_out0 11 0 GPIO_ACTIVE_LOW>; +- }; +- led@7 { +- label = "twr3:yellow"; +- gpios = <&sgpio_out0 11 1 GPIO_ACTIVE_LOW>; +- }; +- led@8 { +- label = "eth12:green"; +- gpios = <&sgpio_out0 12 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@9 { +- label = "eth12:yellow"; +- gpios = <&sgpio_out0 12 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@10 { +- label = "eth13:green"; +- gpios = <&sgpio_out0 13 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@11 { +- label = "eth13:yellow"; +- gpios = <&sgpio_out0 13 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@12 { +- label = "eth14:green"; +- gpios = <&sgpio_out0 14 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@13 { +- label = "eth14:yellow"; +- gpios = <&sgpio_out0 14 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@14 { +- label = "eth15:green"; +- gpios = <&sgpio_out0 15 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@15 { +- label = "eth15:yellow"; +- gpios = <&sgpio_out0 15 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@16 { +- label = "eth48:green"; +- gpios = <&sgpio_out1 16 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@17 { +- label = "eth48:yellow"; +- gpios = <&sgpio_out1 16 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@18 { +- label = "eth49:green"; +- gpios = <&sgpio_out1 17 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@19 { +- label = "eth49:yellow"; +- gpios = <&sgpio_out1 17 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@20 { +- label = "eth50:green"; +- gpios = <&sgpio_out1 18 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@21 { +- label = "eth50:yellow"; +- gpios = <&sgpio_out1 18 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@22 { +- label = "eth51:green"; +- gpios = <&sgpio_out1 19 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@23 { +- label = "eth51:yellow"; +- gpios = <&sgpio_out1 19 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@24 { +- label = "eth52:green"; +- gpios = <&sgpio_out1 20 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@25 { +- label = "eth52:yellow"; +- gpios = <&sgpio_out1 20 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@26 { +- label = "eth53:green"; +- gpios = <&sgpio_out1 21 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@27 { +- label = "eth53:yellow"; +- gpios = <&sgpio_out1 21 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@28 { +- label = "eth54:green"; +- gpios = <&sgpio_out1 22 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@29 { +- label = "eth54:yellow"; +- gpios = <&sgpio_out1 22 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@30 { +- label = "eth55:green"; +- gpios = <&sgpio_out1 23 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@31 { +- label = "eth55:yellow"; +- gpios = <&sgpio_out1 23 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@32 { +- label = "eth56:green"; +- gpios = <&sgpio_out1 24 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@33 { +- label = "eth56:yellow"; +- gpios = <&sgpio_out1 24 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@34 { +- label = "eth57:green"; +- gpios = <&sgpio_out1 25 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@35 { +- label = "eth57:yellow"; +- gpios = <&sgpio_out1 25 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@36 { +- label = "eth58:green"; +- gpios = <&sgpio_out1 26 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@37 { +- label = "eth58:yellow"; +- gpios = <&sgpio_out1 26 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@38 { +- label = "eth59:green"; +- gpios = <&sgpio_out1 27 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@39 { +- label = "eth59:yellow"; +- gpios = <&sgpio_out1 27 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@40 { +- label = "eth60:green"; +- gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@41 { +- label = "eth60:yellow"; +- gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@42 { +- label = "eth61:green"; +- gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@43 { +- label = "eth61:yellow"; +- gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@44 { +- label = "eth62:green"; +- gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@45 { +- label = "eth62:yellow"; +- gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@46 { +- label = "eth63:green"; +- gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- led@47 { +- label = "eth63:yellow"; +- gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +-}; +- +-&sgpio0 { +- status = "okay"; +- microchip,sgpio-port-ranges = <8 15>; +- gpio@0 { +- ngpios = <64>; +- }; +- gpio@1 { +- ngpios = <64>; +- }; +-}; +- +-&sgpio1 { +- status = "okay"; +- microchip,sgpio-port-ranges = <24 31>; +- gpio@0 { +- ngpios = <64>; +- }; +- gpio@1 { +- ngpios = <64>; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- spi-flash@0 { +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <8000000>; +- reg = <0>; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- spi@0 { +- compatible = "spi-mux"; +- mux-controls = <&mux>; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; /* CS0 */ +- spi-flash@9 { +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <8000000>; +- reg = <0x9>; /* SPI */ +- }; +- }; +-}; +- +-&sgpio0 { +- status = "okay"; +- microchip,sgpio-port-ranges = <8 15>; +- gpio@0 { +- ngpios = <64>; +- }; +- gpio@1 { +- ngpios = <64>; +- }; +-}; +- +-&sgpio1 { +- status = "okay"; +- microchip,sgpio-port-ranges = <24 31>; +- gpio@0 { +- ngpios = <64>; +- }; +- gpio@1 { +- ngpios = <64>; +- }; +-}; +- +-&sgpio2 { +- status = "okay"; +- microchip,sgpio-port-ranges = <0 0>, <11 31>; +-}; +- +-&gpio { +- i2cmux_pins_i: i2cmux-pins-i { +- pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19", +- "GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35", +- "GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57"; +- function = "twi_scl_m"; +- output-low; +- }; +- i2cmux_0: i2cmux-0 { +- pins = "GPIO_16"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_1: i2cmux-1 { +- pins = "GPIO_17"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_2: i2cmux-2 { +- pins = "GPIO_18"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_3: i2cmux-3 { +- pins = "GPIO_19"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_4: i2cmux-4 { +- pins = "GPIO_20"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_5: i2cmux-5 { +- pins = "GPIO_22"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_6: i2cmux-6 { +- pins = "GPIO_36"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_7: i2cmux-7 { +- pins = "GPIO_35"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_8: i2cmux-8 { +- pins = "GPIO_50"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_9: i2cmux-9 { +- pins = "GPIO_51"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_10: i2cmux-10 { +- pins = "GPIO_56"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_11: i2cmux-11 { +- pins = "GPIO_57"; +- function = "twi_scl_m"; +- output-high; +- }; +-}; +- +-&axi { +- i2c0_imux: i2c0-imux@0 { +- compatible = "i2c-mux-pinctrl"; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-parent = <&i2c0>; +- }; +- i2c0_emux: i2c0-emux@0 { +- compatible = "i2c-mux-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-parent = <&i2c0>; +- }; +-}; +- +-&i2c0_imux { +- pinctrl-names = +- "i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4", +- "i2c_sfp5", "i2c_sfp6", "i2c_sfp7", "i2c_sfp8", +- "i2c_sfp9", "i2c_sfp10", "i2c_sfp11", "i2c_sfp12", "idle"; +- pinctrl-0 = <&i2cmux_0>; +- pinctrl-1 = <&i2cmux_1>; +- pinctrl-2 = <&i2cmux_2>; +- pinctrl-3 = <&i2cmux_3>; +- pinctrl-4 = <&i2cmux_4>; +- pinctrl-5 = <&i2cmux_5>; +- pinctrl-6 = <&i2cmux_6>; +- pinctrl-7 = <&i2cmux_7>; +- pinctrl-8 = <&i2cmux_8>; +- pinctrl-9 = <&i2cmux_9>; +- pinctrl-10 = <&i2cmux_10>; +- pinctrl-11 = <&i2cmux_11>; +- pinctrl-12 = <&i2cmux_pins_i>; +- i2c_sfp1: i2c_sfp1 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp2: i2c_sfp2 { +- reg = <0x1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp3: i2c_sfp3 { +- reg = <0x2>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp4: i2c_sfp4 { +- reg = <0x3>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp5: i2c_sfp5 { +- reg = <0x4>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp6: i2c_sfp6 { +- reg = <0x5>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp7: i2c_sfp7 { +- reg = <0x6>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp8: i2c_sfp8 { +- reg = <0x7>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp9: i2c_sfp9 { +- reg = <0x8>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp10: i2c_sfp10 { +- reg = <0x9>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp11: i2c_sfp11 { +- reg = <0xa>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp12: i2c_sfp12 { +- reg = <0xb>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +- +-&i2c0_emux { +- mux-gpios = <&gpio 55 GPIO_ACTIVE_HIGH +- &gpio 60 GPIO_ACTIVE_HIGH +- &gpio 61 GPIO_ACTIVE_HIGH +- &gpio 54 GPIO_ACTIVE_HIGH>; +- idle-state = <0x8>; +- i2c_sfp13: i2c_sfp13 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp14: i2c_sfp14 { +- reg = <0x1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp15: i2c_sfp15 { +- reg = <0x2>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp16: i2c_sfp16 { +- reg = <0x3>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp17: i2c_sfp17 { +- reg = <0x4>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp18: i2c_sfp18 { +- reg = <0x5>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp19: i2c_sfp19 { +- reg = <0x6>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp20: i2c_sfp20 { +- reg = <0x7>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +- +-&mdio3 { +- status = "ok"; +- phy64: ethernet-phy@64 { +- reg = <28>; +- }; +-}; +- +-&axi { +- sfp_eth12: sfp-eth12 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp1>; +- tx-disable-gpios = <&sgpio_out2 11 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 11 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 11 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 12 0 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth13: sfp-eth13 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp2>; +- tx-disable-gpios = <&sgpio_out2 12 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 12 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 12 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 13 0 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth14: sfp-eth14 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp3>; +- tx-disable-gpios = <&sgpio_out2 13 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 13 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 13 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 14 0 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth15: sfp-eth15 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp4>; +- tx-disable-gpios = <&sgpio_out2 14 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 14 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 14 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 15 0 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth48: sfp-eth48 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp5>; +- tx-disable-gpios = <&sgpio_out2 15 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 15 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 15 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 16 0 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth49: sfp-eth49 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp6>; +- tx-disable-gpios = <&sgpio_out2 16 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 16 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 16 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 17 0 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth50: sfp-eth50 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp7>; +- tx-disable-gpios = <&sgpio_out2 17 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 17 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 17 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 18 0 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth51: sfp-eth51 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp8>; +- tx-disable-gpios = <&sgpio_out2 18 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 18 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 18 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 19 0 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth52: sfp-eth52 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp9>; +- tx-disable-gpios = <&sgpio_out2 19 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 19 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 19 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 20 0 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth53: sfp-eth53 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp10>; +- tx-disable-gpios = <&sgpio_out2 20 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 20 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 20 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 21 0 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth54: sfp-eth54 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp11>; +- tx-disable-gpios = <&sgpio_out2 21 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 21 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 21 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 22 0 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth55: sfp-eth55 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp12>; +- tx-disable-gpios = <&sgpio_out2 22 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 22 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 22 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 23 0 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth56: sfp-eth56 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp13>; +- tx-disable-gpios = <&sgpio_out2 23 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 23 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 23 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 24 0 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth57: sfp-eth57 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp14>; +- tx-disable-gpios = <&sgpio_out2 24 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 24 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 24 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 25 0 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth58: sfp-eth58 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp15>; +- tx-disable-gpios = <&sgpio_out2 25 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 25 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 25 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 26 0 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth59: sfp-eth59 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp16>; +- tx-disable-gpios = <&sgpio_out2 26 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 26 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 26 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 27 0 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth60: sfp-eth60 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp17>; +- tx-disable-gpios = <&sgpio_out2 27 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 27 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 27 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth61: sfp-eth61 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp18>; +- tx-disable-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth62: sfp-eth62 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp19>; +- tx-disable-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth63: sfp-eth63 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp20>; +- tx-disable-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_LOW>; +- los-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&switch { +- ethernet-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* 10G SFPs */ +- port12: port@12 { +- reg = <12>; +- microchip,bandwidth = <10000>; +- phys = <&serdes 13>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth12>; +- microchip,sd-sgpio = <301>; +- managed = "in-band-status"; +- }; +- port13: port@13 { +- reg = <13>; +- /* Example: CU SFP, 1G speed */ +- microchip,bandwidth = <10000>; +- phys = <&serdes 14>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth13>; +- microchip,sd-sgpio = <305>; +- managed = "in-band-status"; +- }; +- port14: port@14 { +- reg = <14>; +- microchip,bandwidth = <10000>; +- phys = <&serdes 15>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth14>; +- microchip,sd-sgpio = <309>; +- managed = "in-band-status"; +- }; +- port15: port@15 { +- reg = <15>; +- microchip,bandwidth = <10000>; +- phys = <&serdes 16>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth15>; +- microchip,sd-sgpio = <313>; +- managed = "in-band-status"; +- }; +- port48: port@48 { +- reg = <48>; +- microchip,bandwidth = <10000>; +- phys = <&serdes 17>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth48>; +- microchip,sd-sgpio = <317>; +- managed = "in-band-status"; +- }; +- port49: port@49 { +- reg = <49>; +- microchip,bandwidth = <10000>; +- phys = <&serdes 18>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth49>; +- microchip,sd-sgpio = <321>; +- managed = "in-band-status"; +- }; +- port50: port@50 { +- reg = <50>; +- microchip,bandwidth = <10000>; +- phys = <&serdes 19>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth50>; +- microchip,sd-sgpio = <325>; +- managed = "in-band-status"; +- }; +- port51: port@51 { +- reg = <51>; +- microchip,bandwidth = <10000>; +- phys = <&serdes 20>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth51>; +- microchip,sd-sgpio = <329>; +- managed = "in-band-status"; +- }; +- port52: port@52 { +- reg = <52>; +- microchip,bandwidth = <10000>; +- phys = <&serdes 21>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth52>; +- microchip,sd-sgpio = <333>; +- managed = "in-band-status"; +- }; +- port53: port@53 { +- reg = <53>; +- microchip,bandwidth = <10000>; +- phys = <&serdes 22>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth53>; +- microchip,sd-sgpio = <337>; +- managed = "in-band-status"; +- }; +- port54: port@54 { +- reg = <54>; +- microchip,bandwidth = <10000>; +- phys = <&serdes 23>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth54>; +- microchip,sd-sgpio = <341>; +- managed = "in-band-status"; +- }; +- port55: port@55 { +- reg = <55>; +- microchip,bandwidth = <10000>; +- phys = <&serdes 24>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth55>; +- microchip,sd-sgpio = <345>; +- managed = "in-band-status"; +- }; +- /* 25G SFPs */ +- port56: port@56 { +- reg = <56>; +- microchip,bandwidth = <10000>; +- phys = <&serdes 25>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth56>; +- microchip,sd-sgpio = <349>; +- managed = "in-band-status"; +- }; +- port57: port@57 { +- reg = <57>; +- microchip,bandwidth = <10000>; +- phys = <&serdes 26>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth57>; +- microchip,sd-sgpio = <353>; +- managed = "in-band-status"; +- }; +- port58: port@58 { +- reg = <58>; +- microchip,bandwidth = <10000>; +- phys = <&serdes 27>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth58>; +- microchip,sd-sgpio = <357>; +- managed = "in-band-status"; +- }; +- port59: port@59 { +- reg = <59>; +- microchip,bandwidth = <10000>; +- phys = <&serdes 28>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth59>; +- microchip,sd-sgpio = <361>; +- managed = "in-band-status"; +- }; +- port60: port@60 { +- reg = <60>; +- microchip,bandwidth = <10000>; +- phys = <&serdes 29>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth60>; +- microchip,sd-sgpio = <365>; +- managed = "in-band-status"; +- }; +- port61: port@61 { +- reg = <61>; +- microchip,bandwidth = <10000>; +- phys = <&serdes 30>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth61>; +- microchip,sd-sgpio = <369>; +- managed = "in-band-status"; +- }; +- port62: port@62 { +- reg = <62>; +- microchip,bandwidth = <10000>; +- phys = <&serdes 31>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth62>; +- microchip,sd-sgpio = <373>; +- managed = "in-band-status"; +- }; +- port63: port@63 { +- reg = <63>; +- microchip,bandwidth = <10000>; +- phys = <&serdes 32>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth63>; +- microchip,sd-sgpio = <377>; +- managed = "in-band-status"; +- }; +- /* Finally the Management interface */ +- port64: port@64 { +- reg = <64>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 0>; +- phy-handle = <&phy64>; +- phy-mode = "sgmii"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb134_emmc.dts b/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb134_emmc.dts +deleted file mode 100644 +index bbb9852c1f15..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb134_emmc.dts ++++ /dev/null +@@ -1,40 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. +- */ +- +-/dts-v1/; +-#include "sparx5_pcb134_board.dtsi" +- +-/ { +- model = "Sparx5 PCB134 Reference Board (eMMC enabled)"; +- compatible = "microchip,sparx5-pcb134", "microchip,sparx5"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x10000000>; +- }; +-}; +- +-&gpio { +- emmc_pins: emmc-pins { +- /* NB: No "GPIO_35", "GPIO_36", "GPIO_37" +- * (N/A: CARD_nDETECT, CARD_WP, CARD_LED) +- */ +- pins = "GPIO_34", "GPIO_38", "GPIO_39", +- "GPIO_40", "GPIO_41", "GPIO_42", +- "GPIO_43", "GPIO_44", "GPIO_45", +- "GPIO_46", "GPIO_47"; +- drive-strength = <3>; +- function = "emmc"; +- }; +-}; +- +-&sdhci0 { +- status = "okay"; +- pinctrl-0 = <&emmc_pins>; +- non-removable; +- max-frequency = <52000000>; +- bus-width = <8>; +- microchip,clock-delay = <10>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb135.dts b/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb135.dts +deleted file mode 100644 +index 647cdb38b113..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb135.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. +- */ +- +-/dts-v1/; +-#include "sparx5_pcb135_board.dtsi" +-#include "sparx5_nand.dtsi" +- +-/ { +- model = "Sparx5 PCB135 Reference Board (NAND)"; +- compatible = "microchip,sparx5-pcb135", "microchip,sparx5"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x10000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb135_board.dtsi b/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb135_board.dtsi +deleted file mode 100644 +index ef96e6d8c6b3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb135_board.dtsi ++++ /dev/null +@@ -1,752 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. +- */ +- +-/dts-v1/; +-#include "sparx5_pcb_common.dtsi" +- +-/{ +- gpio-restart { +- compatible = "gpio-restart"; +- gpios = <&gpio 37 GPIO_ACTIVE_LOW>; +- priority = <200>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led@0 { +- label = "eth60:yellow"; +- gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- led@1 { +- label = "eth60:green"; +- gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- led@2 { +- label = "eth61:yellow"; +- gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- led@3 { +- label = "eth61:green"; +- gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- led@4 { +- label = "eth62:yellow"; +- gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- led@5 { +- label = "eth62:green"; +- gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- led@6 { +- label = "eth63:yellow"; +- gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- led@7 { +- label = "eth63:green"; +- gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +-}; +- +-&gpio { +- i2cmux_pins_i: i2cmux-pins-i { +- pins = "GPIO_35", "GPIO_36", +- "GPIO_50", "GPIO_51"; +- function = "twi_scl_m"; +- output-low; +- }; +- i2cmux_s29: i2cmux-0 { +- pins = "GPIO_35"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_s30: i2cmux-1 { +- pins = "GPIO_36"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_s31: i2cmux-2 { +- pins = "GPIO_50"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_s32: i2cmux-3 { +- pins = "GPIO_51"; +- function = "twi_scl_m"; +- output-high; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- spi-flash@0 { +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <8000000>; +- reg = <0>; +- }; +-}; +- +-&spi0 { +- status = "okay"; +- spi@0 { +- compatible = "spi-mux"; +- mux-controls = <&mux>; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; /* CS0 */ +- spi-flash@9 { +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <8000000>; +- reg = <0x9>; /* SPI */ +- }; +- }; +-}; +- +-&sgpio1 { +- status = "okay"; +- microchip,sgpio-port-ranges = <24 31>; +- gpio@0 { +- ngpios = <64>; +- }; +- gpio@1 { +- ngpios = <64>; +- }; +-}; +- +-&sgpio2 { +- status = "okay"; +- microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>; +-}; +- +-&axi { +- i2c0_imux: i2c0-imux@0 { +- compatible = "i2c-mux-pinctrl"; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-parent = <&i2c0>; +- }; +-}; +- +-&i2c0_imux { +- pinctrl-names = +- "i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4", +- "idle"; +- pinctrl-0 = <&i2cmux_s29>; +- pinctrl-1 = <&i2cmux_s30>; +- pinctrl-2 = <&i2cmux_s31>; +- pinctrl-3 = <&i2cmux_s32>; +- pinctrl-4 = <&i2cmux_pins_i>; +- i2c_sfp1: i2c_sfp1 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp2: i2c_sfp2 { +- reg = <0x1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp3: i2c_sfp3 { +- reg = <0x2>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c_sfp4: i2c_sfp4 { +- reg = <0x3>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +- +-&axi { +- sfp_eth60: sfp-eth60 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp1>; +- tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>; +- rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>; +- los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth61: sfp-eth61 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp2>; +- tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>; +- rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>; +- los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth62: sfp-eth62 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp3>; +- tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>; +- rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>; +- los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>; +- }; +- sfp_eth63: sfp-eth63 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c_sfp4>; +- tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>; +- rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>; +- los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>; +- mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>; +- tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&mdio0 { +- status = "ok"; +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +- phy2: ethernet-phy@2 { +- reg = <2>; +- }; +- phy3: ethernet-phy@3 { +- reg = <3>; +- }; +- phy4: ethernet-phy@4 { +- reg = <4>; +- }; +- phy5: ethernet-phy@5 { +- reg = <5>; +- }; +- phy6: ethernet-phy@6 { +- reg = <6>; +- }; +- phy7: ethernet-phy@7 { +- reg = <7>; +- }; +- phy8: ethernet-phy@8 { +- reg = <8>; +- }; +- phy9: ethernet-phy@9 { +- reg = <9>; +- }; +- phy10: ethernet-phy@10 { +- reg = <10>; +- }; +- phy11: ethernet-phy@11 { +- reg = <11>; +- }; +- phy12: ethernet-phy@12 { +- reg = <12>; +- }; +- phy13: ethernet-phy@13 { +- reg = <13>; +- }; +- phy14: ethernet-phy@14 { +- reg = <14>; +- }; +- phy15: ethernet-phy@15 { +- reg = <15>; +- }; +- phy16: ethernet-phy@16 { +- reg = <16>; +- }; +- phy17: ethernet-phy@17 { +- reg = <17>; +- }; +- phy18: ethernet-phy@18 { +- reg = <18>; +- }; +- phy19: ethernet-phy@19 { +- reg = <19>; +- }; +- phy20: ethernet-phy@20 { +- reg = <20>; +- }; +- phy21: ethernet-phy@21 { +- reg = <21>; +- }; +- phy22: ethernet-phy@22 { +- reg = <22>; +- }; +- phy23: ethernet-phy@23 { +- reg = <23>; +- }; +-}; +- +-&mdio1 { +- status = "ok"; +- phy24: ethernet-phy@24 { +- reg = <0>; +- }; +- phy25: ethernet-phy@25 { +- reg = <1>; +- }; +- phy26: ethernet-phy@26 { +- reg = <2>; +- }; +- phy27: ethernet-phy@27 { +- reg = <3>; +- }; +- phy28: ethernet-phy@28 { +- reg = <4>; +- }; +- phy29: ethernet-phy@29 { +- reg = <5>; +- }; +- phy30: ethernet-phy@30 { +- reg = <6>; +- }; +- phy31: ethernet-phy@31 { +- reg = <7>; +- }; +- phy32: ethernet-phy@32 { +- reg = <8>; +- }; +- phy33: ethernet-phy@33 { +- reg = <9>; +- }; +- phy34: ethernet-phy@34 { +- reg = <10>; +- }; +- phy35: ethernet-phy@35 { +- reg = <11>; +- }; +- phy36: ethernet-phy@36 { +- reg = <12>; +- }; +- phy37: ethernet-phy@37 { +- reg = <13>; +- }; +- phy38: ethernet-phy@38 { +- reg = <14>; +- }; +- phy39: ethernet-phy@39 { +- reg = <15>; +- }; +- phy40: ethernet-phy@40 { +- reg = <16>; +- }; +- phy41: ethernet-phy@41 { +- reg = <17>; +- }; +- phy42: ethernet-phy@42 { +- reg = <18>; +- }; +- phy43: ethernet-phy@43 { +- reg = <19>; +- }; +- phy44: ethernet-phy@44 { +- reg = <20>; +- }; +- phy45: ethernet-phy@45 { +- reg = <21>; +- }; +- phy46: ethernet-phy@46 { +- reg = <22>; +- }; +- phy47: ethernet-phy@47 { +- reg = <23>; +- }; +-}; +- +-&mdio3 { +- status = "ok"; +- phy64: ethernet-phy@64 { +- reg = <28>; +- }; +-}; +- +-&switch { +- ethernet-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port0: port@0 { +- reg = <0>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 13>; +- phy-handle = <&phy0>; +- phy-mode = "qsgmii"; +- }; +- port1: port@1 { +- reg = <1>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 13>; +- phy-handle = <&phy1>; +- phy-mode = "qsgmii"; +- }; +- port2: port@2 { +- reg = <2>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 13>; +- phy-handle = <&phy2>; +- phy-mode = "qsgmii"; +- }; +- port3: port@3 { +- reg = <3>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 13>; +- phy-handle = <&phy3>; +- phy-mode = "qsgmii"; +- }; +- port4: port@4 { +- reg = <4>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 14>; +- phy-handle = <&phy4>; +- phy-mode = "qsgmii"; +- }; +- port5: port@5 { +- reg = <5>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 14>; +- phy-handle = <&phy5>; +- phy-mode = "qsgmii"; +- }; +- port6: port@6 { +- reg = <6>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 14>; +- phy-handle = <&phy6>; +- phy-mode = "qsgmii"; +- }; +- port7: port@7 { +- reg = <7>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 14>; +- phy-handle = <&phy7>; +- phy-mode = "qsgmii"; +- }; +- port8: port@8 { +- reg = <8>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 15>; +- phy-handle = <&phy8>; +- phy-mode = "qsgmii"; +- }; +- port9: port@9 { +- reg = <9>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 15>; +- phy-handle = <&phy9>; +- phy-mode = "qsgmii"; +- }; +- port10: port@10 { +- reg = <10>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 15>; +- phy-handle = <&phy10>; +- phy-mode = "qsgmii"; +- }; +- port11: port@11 { +- reg = <11>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 15>; +- phy-handle = <&phy11>; +- phy-mode = "qsgmii"; +- }; +- port12: port@12 { +- reg = <12>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 16>; +- phy-handle = <&phy12>; +- phy-mode = "qsgmii"; +- }; +- port13: port@13 { +- reg = <13>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 16>; +- phy-handle = <&phy13>; +- phy-mode = "qsgmii"; +- }; +- port14: port@14 { +- reg = <14>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 16>; +- phy-handle = <&phy14>; +- phy-mode = "qsgmii"; +- }; +- port15: port@15 { +- reg = <15>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 16>; +- phy-handle = <&phy15>; +- phy-mode = "qsgmii"; +- }; +- port16: port@16 { +- reg = <16>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 17>; +- phy-handle = <&phy16>; +- phy-mode = "qsgmii"; +- }; +- port17: port@17 { +- reg = <17>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 17>; +- phy-handle = <&phy17>; +- phy-mode = "qsgmii"; +- }; +- port18: port@18 { +- reg = <18>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 17>; +- phy-handle = <&phy18>; +- phy-mode = "qsgmii"; +- }; +- port19: port@19 { +- reg = <19>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 17>; +- phy-handle = <&phy19>; +- phy-mode = "qsgmii"; +- }; +- port20: port@20 { +- reg = <20>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 18>; +- phy-handle = <&phy20>; +- phy-mode = "qsgmii"; +- }; +- port21: port@21 { +- reg = <21>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 18>; +- phy-handle = <&phy21>; +- phy-mode = "qsgmii"; +- }; +- port22: port@22 { +- reg = <22>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 18>; +- phy-handle = <&phy22>; +- phy-mode = "qsgmii"; +- }; +- port23: port@23 { +- reg = <23>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 18>; +- phy-handle = <&phy23>; +- phy-mode = "qsgmii"; +- }; +- port24: port@24 { +- reg = <24>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 19>; +- phy-handle = <&phy24>; +- phy-mode = "qsgmii"; +- }; +- port25: port@25 { +- reg = <25>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 19>; +- phy-handle = <&phy25>; +- phy-mode = "qsgmii"; +- }; +- port26: port@26 { +- reg = <26>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 19>; +- phy-handle = <&phy26>; +- phy-mode = "qsgmii"; +- }; +- port27: port@27 { +- reg = <27>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 19>; +- phy-handle = <&phy27>; +- phy-mode = "qsgmii"; +- }; +- port28: port@28 { +- reg = <28>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 20>; +- phy-handle = <&phy28>; +- phy-mode = "qsgmii"; +- }; +- port29: port@29 { +- reg = <29>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 20>; +- phy-handle = <&phy29>; +- phy-mode = "qsgmii"; +- }; +- port30: port@30 { +- reg = <30>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 20>; +- phy-handle = <&phy30>; +- phy-mode = "qsgmii"; +- }; +- port31: port@31 { +- reg = <31>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 20>; +- phy-handle = <&phy31>; +- phy-mode = "qsgmii"; +- }; +- port32: port@32 { +- reg = <32>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 21>; +- phy-handle = <&phy32>; +- phy-mode = "qsgmii"; +- }; +- port33: port@33 { +- reg = <33>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 21>; +- phy-handle = <&phy33>; +- phy-mode = "qsgmii"; +- }; +- port34: port@34 { +- reg = <34>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 21>; +- phy-handle = <&phy34>; +- phy-mode = "qsgmii"; +- }; +- port35: port@35 { +- reg = <35>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 21>; +- phy-handle = <&phy35>; +- phy-mode = "qsgmii"; +- }; +- port36: port@36 { +- reg = <36>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 22>; +- phy-handle = <&phy36>; +- phy-mode = "qsgmii"; +- }; +- port37: port@37 { +- reg = <37>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 22>; +- phy-handle = <&phy37>; +- phy-mode = "qsgmii"; +- }; +- port38: port@38 { +- reg = <38>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 22>; +- phy-handle = <&phy38>; +- phy-mode = "qsgmii"; +- }; +- port39: port@39 { +- reg = <39>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 22>; +- phy-handle = <&phy39>; +- phy-mode = "qsgmii"; +- }; +- port40: port@40 { +- reg = <40>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 23>; +- phy-handle = <&phy40>; +- phy-mode = "qsgmii"; +- }; +- port41: port@41 { +- reg = <41>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 23>; +- phy-handle = <&phy41>; +- phy-mode = "qsgmii"; +- }; +- port42: port@42 { +- reg = <42>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 23>; +- phy-handle = <&phy42>; +- phy-mode = "qsgmii"; +- }; +- port43: port@43 { +- reg = <43>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 23>; +- phy-handle = <&phy43>; +- phy-mode = "qsgmii"; +- }; +- port44: port@44 { +- reg = <44>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 24>; +- phy-handle = <&phy44>; +- phy-mode = "qsgmii"; +- }; +- port45: port@45 { +- reg = <45>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 24>; +- phy-handle = <&phy45>; +- phy-mode = "qsgmii"; +- }; +- port46: port@46 { +- reg = <46>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 24>; +- phy-handle = <&phy46>; +- phy-mode = "qsgmii"; +- }; +- port47: port@47 { +- reg = <47>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 24>; +- phy-handle = <&phy47>; +- phy-mode = "qsgmii"; +- }; +- /* Then the 25G interfaces */ +- port60: port@60 { +- reg = <60>; +- microchip,bandwidth = <25000>; +- phys = <&serdes 29>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth60>; +- managed = "in-band-status"; +- }; +- port61: port@61 { +- reg = <61>; +- microchip,bandwidth = <25000>; +- phys = <&serdes 30>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth61>; +- managed = "in-band-status"; +- }; +- port62: port@62 { +- reg = <62>; +- microchip,bandwidth = <25000>; +- phys = <&serdes 31>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth62>; +- managed = "in-band-status"; +- }; +- port63: port@63 { +- reg = <63>; +- microchip,bandwidth = <25000>; +- phys = <&serdes 32>; +- phy-mode = "10gbase-r"; +- sfp = <&sfp_eth63>; +- managed = "in-band-status"; +- }; +- /* Finally the Management interface */ +- port64: port@64 { +- reg = <64>; +- microchip,bandwidth = <1000>; +- phys = <&serdes 0>; +- phy-handle = <&phy64>; +- phy-mode = "sgmii"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb135_emmc.dts b/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb135_emmc.dts +deleted file mode 100644 +index f82266fe2ad4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb135_emmc.dts ++++ /dev/null +@@ -1,40 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. +- */ +- +-/dts-v1/; +-#include "sparx5_pcb135_board.dtsi" +- +-/ { +- model = "Sparx5 PCB135 Reference Board (eMMC enabled)"; +- compatible = "microchip,sparx5-pcb135", "microchip,sparx5"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x10000000>; +- }; +-}; +- +-&gpio { +- emmc_pins: emmc-pins { +- /* NB: No "GPIO_35", "GPIO_36", "GPIO_37" +- * (N/A: CARD_nDETECT, CARD_WP, CARD_LED) +- */ +- pins = "GPIO_34", "GPIO_38", "GPIO_39", +- "GPIO_40", "GPIO_41", "GPIO_42", +- "GPIO_43", "GPIO_44", "GPIO_45", +- "GPIO_46", "GPIO_47"; +- drive-strength = <3>; +- function = "emmc"; +- }; +-}; +- +-&sdhci0 { +- status = "okay"; +- pinctrl-0 = <&emmc_pins>; +- non-removable; +- max-frequency = <52000000>; +- bus-width = <8>; +- microchip,clock-delay = <10>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb_common.dtsi b/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb_common.dtsi +deleted file mode 100644 +index 9d1a082de3e2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/microchip/sparx5_pcb_common.dtsi ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. +- */ +- +-/dts-v1/; +-#include "sparx5.dtsi" +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/Makefile b/scripts/dtc/include-prefixes/arm64/nvidia/Makefile +deleted file mode 100644 +index c80f7dc2935e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/Makefile ++++ /dev/null +@@ -1,14 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb +-dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb +-dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb +-dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb +-dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p3450-0000.dtb +-dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb +-dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2894-0050-a08.dtb +-dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb +-dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p3509-0000+p3636-0001.dtb +-dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb +-dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb +-dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0001.dtb +-dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra132-norrin.dts b/scripts/dtc/include-prefixes/arm64/nvidia/tegra132-norrin.dts +deleted file mode 100644 +index 6e5f8465669e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra132-norrin.dts ++++ /dev/null +@@ -1,1197 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include "tegra132.dtsi" +- +-/ { +- model = "NVIDIA Tegra132 Norrin"; +- compatible = "nvidia,norrin", "nvidia,tegra132", "nvidia,tegra124"; +- +- aliases { +- rtc0 = "/i2c@7000d000/as3722@40"; +- rtc1 = "/rtc@7000e000"; +- serial0 = &uarta; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0x80000000>; +- }; +- +- host1x@50000000 { +- hdmi@54280000 { +- status = "disabled"; +- +- vdd-supply = <&vdd_3v3_hdmi>; +- pll-supply = <&vdd_hdmi_pll>; +- hdmi-supply = <&vdd_5v0_hdmi>; +- +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = +- <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; +- }; +- +- sor@54540000 { +- status = "okay"; +- +- avdd-io-hdmi-dp-supply = <&vdd_3v3_hdmi>; +- vdd-hdmi-dp-pll-supply = <&vdd_hdmi_pll>; +- +- nvidia,dpaux = <&dpaux>; +- nvidia,panel = <&panel>; +- }; +- +- dpaux: dpaux@545c0000 { +- vdd-supply = <&vdd_3v3_panel>; +- status = "okay"; +- }; +- }; +- +- gpu@57000000 { +- status = "okay"; +- +- vdd-supply = <&vdd_gpu>; +- }; +- +- pinmux@70000868 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinmux_default>; +- +- pinmux_default: pinmux@0 { +- dap_mclk1_pw4 { +- nvidia,pins = "dap_mclk1_pw4"; +- nvidia,function = "extperiph1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_din_pa4 { +- nvidia,pins = "dap2_din_pa4"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap2_dout_pa5 { +- nvidia,pins = "dap2_dout_pa5", +- "dap2_fs_pa2", +- "dap2_sclk_pa3"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dap3_dout_pp2 { +- nvidia,pins = "dap3_dout_pp2"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- dvfs_pwm_px0 { +- nvidia,pins = "dvfs_pwm_px0", +- "dvfs_clk_px2"; +- nvidia,function = "cldvfs"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_clk_py0 { +- nvidia,pins = "ulpi_clk_py0", +- "ulpi_nxt_py2", +- "ulpi_stp_py3"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ulpi_dir_py1 { +- nvidia,pins = "ulpi_dir_py1"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cam_i2c_scl_pbb1 { +- nvidia,pins = "cam_i2c_scl_pbb1", +- "cam_i2c_sda_pbb2"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- gen2_i2c_scl_pt5 { +- nvidia,pins = "gen2_i2c_scl_pt5", +- "gen2_i2c_sda_pt6"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- pj7 { +- nvidia,pins = "pj7"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- spdif_in_pk6 { +- nvidia,pins = "spdif_in_pk6"; +- nvidia,function = "spdif"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk7 { +- nvidia,pins = "pk7"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg4 { +- nvidia,pins = "pg4", +- "pg5", +- "pg6", +- "pi3"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pg7 { +- nvidia,pins = "pg7"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph1 { +- nvidia,pins = "ph1"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pk0 { +- nvidia,pins = "pk0", +- "kb_row15_ps7", +- "clk_32k_out_pa0"; +- nvidia,function = "soc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_clk_pz0 { +- nvidia,pins = "sdmmc1_clk_pz0"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc1_cmd_pz1 { +- nvidia,pins = "sdmmc1_cmd_pz1", +- "sdmmc1_dat0_py7", +- "sdmmc1_dat1_py6", +- "sdmmc1_dat2_py5", +- "sdmmc1_dat3_py4"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_clk_pa6 { +- nvidia,pins = "sdmmc3_clk_pa6"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc3_cmd_pa7 { +- nvidia,pins = "sdmmc3_cmd_pa7", +- "sdmmc3_dat0_pb7", +- "sdmmc3_dat1_pb6", +- "sdmmc3_dat2_pb5", +- "sdmmc3_dat3_pb4", +- "kb_col4_pq4", +- "sdmmc3_clk_lb_out_pee4", +- "sdmmc3_clk_lb_in_pee5", +- "sdmmc3_cd_n_pv2"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_clk_pcc4 { +- nvidia,pins = "sdmmc4_clk_pcc4"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sdmmc4_cmd_pt7 { +- nvidia,pins = "sdmmc4_cmd_pt7", +- "sdmmc4_dat0_paa0", +- "sdmmc4_dat1_paa1", +- "sdmmc4_dat2_paa2", +- "sdmmc4_dat3_paa3", +- "sdmmc4_dat4_paa4", +- "sdmmc4_dat5_paa5", +- "sdmmc4_dat6_paa6", +- "sdmmc4_dat7_paa7"; +- nvidia,function = "sdmmc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- mic_det_l { +- nvidia,pins = "kb_row7_pr7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row10_ps2 { +- nvidia,pins = "kb_row10_ps2"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_row9_ps1 { +- nvidia,pins = "kb_row9_ps1"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pwr_i2c_scl_pz6 { +- nvidia,pins = "pwr_i2c_scl_pz6", +- "pwr_i2c_sda_pz7"; +- nvidia,function = "i2cpwr"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- jtag_rtck { +- nvidia,pins = "jtag_rtck"; +- nvidia,function = "rtck"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk_32k_in { +- nvidia,pins = "clk_32k_in"; +- nvidia,function = "clk"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- core_pwr_req { +- nvidia,pins = "core_pwr_req"; +- nvidia,function = "pwron"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- cpu_pwr_req { +- nvidia,pins = "cpu_pwr_req"; +- nvidia,function = "cpu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- kb_col0_ap { +- nvidia,pins = "kb_col0_pq0"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- en_vdd_sd { +- nvidia,pins = "kb_row0_pr0"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lid_open { +- nvidia,pins = "kb_row4_pr4"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- pwr_int_n { +- nvidia,pins = "pwr_int_n"; +- nvidia,function = "pmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- reset_out_n { +- nvidia,pins = "reset_out_n"; +- nvidia,function = "reset_out_n"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- clk3_out_pee0 { +- nvidia,pins = "clk3_out_pee0"; +- nvidia,function = "extperiph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- gen1_i2c_scl_pc4 { +- nvidia,pins = "gen1_i2c_scl_pc4", +- "gen1_i2c_sda_pc5"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- hdmi_cec_pee3 { +- nvidia,pins = "hdmi_cec_pee3"; +- nvidia,function = "cec"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- hdmi_int_pn7 { +- nvidia,pins = "hdmi_int_pn7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ddc_scl_pv4 { +- nvidia,pins = "ddc_scl_pv4", +- "ddc_sda_pv5"; +- nvidia,function = "i2c4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,rcv-sel = ; +- }; +- usb_vbus_en0_pn4 { +- nvidia,pins = "usb_vbus_en0_pn4", +- "usb_vbus_en1_pn5", +- "usb_vbus_en2_pff1"; +- nvidia,function = "usb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,lock = ; +- nvidia,open-drain = ; +- }; +- drive_sdio1 { +- nvidia,pins = "drive_sdio1"; +- nvidia,high-speed-mode = ; +- nvidia,schmitt = ; +- nvidia,pull-down-strength = <36>; +- nvidia,pull-up-strength = <20>; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- }; +- drive_sdio3 { +- nvidia,pins = "drive_sdio3"; +- nvidia,high-speed-mode = ; +- nvidia,schmitt = ; +- nvidia,pull-down-strength = <22>; +- nvidia,pull-up-strength = <36>; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- }; +- drive_gma { +- nvidia,pins = "drive_gma"; +- nvidia,high-speed-mode = ; +- nvidia,schmitt = ; +- nvidia,pull-down-strength = <2>; +- nvidia,pull-up-strength = <1>; +- nvidia,slew-rate-rising = ; +- nvidia,slew-rate-falling = ; +- nvidia,drive-type = <1>; +- }; +- ac_ok { +- nvidia,pins = "pj0"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- codec_irq_l { +- nvidia,pins = "ph4"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- lcd_bl_en { +- nvidia,pins = "ph2"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- touch_irq_l { +- nvidia,pins = "gpio_w3_aud_pw3"; +- nvidia,function = "spi6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- tpm_davint_l { +- nvidia,pins = "ph6"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ts_irq_l { +- nvidia,pins = "pk2"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ts_reset_l { +- nvidia,pins = "pk4"; +- nvidia,function = "gmi"; +- nvidia,pull = <1>; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ts_shdn_l { +- nvidia,pins = "pk1"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- ph7 { +- nvidia,pins = "ph7"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- sensor_irq_l { +- nvidia,pins = "pi6"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- wifi_en { +- nvidia,pins = "gpio_x7_aud_px7"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- chromeos_write_protect { +- nvidia,pins = "kb_row1_pr1"; +- nvidia,function = "rsvd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- hp_det_l { +- nvidia,pins = "pi7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- soc_warm_reset_l { +- nvidia,pins = "pi5"; +- nvidia,function = "gmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- }; +- }; +- }; +- +- serial@70006000 { +- status = "okay"; +- }; +- +- pwm: pwm@7000a000 { +- status = "okay"; +- }; +- +- /* HDMI DDC */ +- hdmi_ddc: i2c@7000c700 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- as3722: pmic@40 { +- compatible = "ams,as3722"; +- reg = <0x40>; +- interrupts = ; +- +- ams,system-power-controller; +- +- #interrupt-cells = <2>; +- interrupt-controller; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&as3722_default>; +- +- as3722_default: pinmux@0 { +- gpio0 { +- pins = "gpio0"; +- function = "gpio"; +- bias-pull-down; +- }; +- +- gpio1 { +- pins = "gpio1"; +- function = "gpio"; +- bias-pull-up; +- }; +- +- gpio2_4_7 { +- pins = "gpio2", "gpio4", "gpio7"; +- function = "gpio"; +- bias-pull-up; +- }; +- +- gpio3 { +- pins = "gpio3"; +- function = "gpio"; +- bias-high-impedance; +- }; +- +- gpio5 { +- pins = "gpio5"; +- function = "clk32k-out"; +- bias-pull-down; +- }; +- +- gpio6 { +- pins = "gpio6"; +- function = "clk32k-out"; +- bias-pull-down; +- }; +- }; +- +- regulators { +- vsup-sd2-supply = <&vdd_5v0_sys>; +- vsup-sd3-supply = <&vdd_5v0_sys>; +- vsup-sd4-supply = <&vdd_5v0_sys>; +- vsup-sd5-supply = <&vdd_5v0_sys>; +- vin-ldo0-supply = <&vdd_1v35_lp0>; +- vin-ldo1-6-supply = <&vdd_3v3_sys>; +- vin-ldo2-5-7-supply = <&vddio_1v8>; +- vin-ldo3-4-supply = <&vdd_3v3_sys>; +- vin-ldo9-10-supply = <&vdd_5v0_sys>; +- vin-ldo11-supply = <&vdd_3v3_run>; +- +- sd0 { +- regulator-name = "+VDD_CPU_AP"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-max-microamp = <3500000>; +- regulator-always-on; +- regulator-boot-on; +- ams,ext-control = <2>; +- }; +- +- sd1 { +- regulator-name = "+VDD_CORE"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-max-microamp = <4000000>; +- regulator-always-on; +- regulator-boot-on; +- ams,ext-control = <1>; +- }; +- +- vdd_1v35_lp0: sd2 { +- regulator-name = "+1.35V_LP0(sd2)"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- sd3 { +- regulator-name = "+1.35V_LP0(sd3)"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v05_run: sd4 { +- regulator-name = "+1.05V_RUN"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- vddio_1v8: sd5 { +- regulator-name = "+1.8V_VDDIO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_gpu: sd6 { +- regulator-name = "+VDD_GPU_AP"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1200000>; +- regulator-min-microamp = <3500000>; +- regulator-max-microamp = <3500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- avdd_1v05_run: ldo0 { +- regulator-name = "+1.05_RUN_AVDD"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-always-on; +- regulator-boot-on; +- ams,ext-control = <1>; +- }; +- +- ldo1 { +- regulator-name = "+1.8V_RUN_CAM"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo2 { +- regulator-name = "+1.2V_GEN_AVDD"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo3 { +- regulator-name = "+1.00V_LP0_VDD_RTC"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- ams,enable-tracking; +- }; +- +- vdd_run_cam: ldo4 { +- regulator-name = "+2.8V_RUN_CAM"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo5 { +- regulator-name = "+1.2V_RUN_CAM_FRONT"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- vddio_sdmmc3: ldo6 { +- regulator-name = "+VDDIO_SDMMC3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo7 { +- regulator-name = "+1.05V_RUN_CAM_REAR"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- ldo9 { +- regulator-name = "+2.8V_RUN_TOUCH"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo10 { +- regulator-name = "+2.8V_RUN_CAM_AF"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- ldo11 { +- regulator-name = "+1.8V_RUN_VPP_FUSE"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- }; +- }; +- }; +- +- spi@7000d400 { +- status = "okay"; +- +- ec: cros-ec@0 { +- compatible = "google,cros-ec-spi"; +- spi-max-frequency = <3000000>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- reg = <0>; +- +- google,cros-ec-spi-msg-delay = <2000>; +- +- i2c_20: i2c-tunnel { +- compatible = "google,cros-ec-i2c-tunnel"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- google,remote-bus = <0>; +- +- charger: bq24735 { +- compatible = "ti,bq24735"; +- reg = <0x9>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- ti,ac-detect-gpios = <&gpio +- TEGRA_GPIO(J, 0) +- GPIO_ACTIVE_HIGH>; +- }; +- +- battery: smart-battery { +- compatible = "sbs,sbs-battery"; +- reg = <0xb>; +- sbs,i2c-retry-count = <2>; +- sbs,poll-retry-count = <10>; +- /* power-supplies = <&charger>; */ +- }; +- }; +- +- keyboard-controller { +- compatible = "google,cros-ec-keyb"; +- keypad,num-rows = <8>; +- keypad,num-columns = <13>; +- google,needs-ghost-filter; +- linux,keymap = +- ; +- }; +- }; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <0>; +- #wake-cells = <3>; +- nvidia,cpu-pwr-good-time = <500>; +- nvidia,cpu-pwr-off-time = <300>; +- nvidia,core-pwr-good-time = <641 3845>; +- nvidia,core-pwr-off-time = <61036>; +- nvidia,core-power-req-active-high; +- nvidia,sys-clock-req-active-high; +- nvidia,reset-gpio = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; +- }; +- +- usb@70090000 { +- phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ +- <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ +- <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ +- phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; +- +- avddio-pex-supply = <&vdd_1v05_run>; +- dvddio-pex-supply = <&vdd_1v05_run>; +- avdd-usb-supply = <&vdd_3v3_lp0>; +- hvdd-usb-ss-supply = <&vdd_3v3_lp0>; +- +- status = "okay"; +- }; +- +- padctl@7009f000 { +- avdd-pll-utmip-supply = <&vddio_1v8>; +- avdd-pll-erefe-supply = <&avdd_1v05_run>; +- avdd-pex-pll-supply = <&vdd_1v05_run>; +- hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; +- +- pads { +- usb2 { +- status = "okay"; +- +- lanes { +- usb2-0 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- +- usb2-1 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- +- usb2-2 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- }; +- }; +- +- pcie { +- status = "okay"; +- +- lanes { +- pcie-0 { +- nvidia,function = "usb3-ss"; +- status = "okay"; +- }; +- +- pcie-1 { +- nvidia,function = "usb3-ss"; +- status = "okay"; +- }; +- }; +- }; +- }; +- +- ports { +- usb2-0 { +- status = "okay"; +- mode = "otg"; +- +- vbus-supply = <&vdd_usb1_vbus>; +- }; +- +- usb2-1 { +- status = "okay"; +- mode = "host"; +- +- vbus-supply = <&vdd_run_cam>; +- }; +- +- usb2-2 { +- status = "okay"; +- mode = "host"; +- +- vbus-supply = <&vdd_usb3_vbus>; +- }; +- +- usb3-0 { +- nvidia,usb2-companion = <0>; +- status = "okay"; +- }; +- +- usb3-1 { +- nvidia,usb2-companion = <2>; +- status = "okay"; +- }; +- }; +- }; +- +- /* WIFI/BT module */ +- mmc@700b0000 { +- status = "disabled"; +- }; +- +- /* external SD/MMC */ +- mmc@700b0400 { +- cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; +- power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; +- wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; +- status = "okay"; +- bus-width = <4>; +- vqmmc-supply = <&vddio_sdmmc3>; +- }; +- +- /* EMMC 4.51 */ +- mmc@700b0600 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- +- enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; +- power-supply = <&vdd_led>; +- pwms = <&pwm 1 1000000>; +- +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- +- backlight-boot-off; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- lid { +- label = "Lid"; +- gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; +- linux,input-type = <5>; +- linux,code = <0>; +- debounce-interval = <1>; +- wakeup-source; +- }; +- +- power { +- label = "Power"; +- gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-source; +- }; +- }; +- +- panel: panel { +- compatible = "innolux,n116bge"; +- power-supply = <&vdd_3v3_panel>; +- backlight = <&backlight>; +- ddc-i2c-bus = <&dpaux>; +- }; +- +- vdd_mux: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "+VDD_MUX"; +- regulator-min-microvolt = <19000000>; +- regulator-max-microvolt = <19000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_5v0_sys: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "+5V_SYS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_mux>; +- }; +- +- vdd_3v3_sys: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "+3.3V_SYS"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_mux>; +- }; +- +- vdd_3v3_run: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "+3.3V_RUN"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&as3722 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_3v3_sys>; +- }; +- +- vdd_3v3_hdmi: regulator@4 { +- compatible = "regulator-fixed"; +- regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vdd_3v3_run>; +- }; +- +- vdd_led: regulator@5 { +- compatible = "regulator-fixed"; +- regulator-name = "+VDD_LED"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_mux>; +- }; +- +- vdd_usb1_vbus: regulator@6 { +- compatible = "regulator-fixed"; +- regulator-name = "+5V_USB_HS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- gpio-open-drain; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_usb3_vbus: regulator@7 { +- compatible = "regulator-fixed"; +- regulator-name = "+5V_USB_SS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- gpio-open-drain; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_3v3_panel: regulator@8 { +- compatible = "regulator-fixed"; +- regulator-name = "+3.3V_PANEL"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&as3722 4 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_3v3_sys>; +- }; +- +- vdd_hdmi_pll: regulator@9 { +- compatible = "regulator-fixed"; +- regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; +- vin-supply = <&vdd_1v05_run>; +- }; +- +- vdd_5v0_hdmi: regulator@10 { +- compatible = "regulator-fixed"; +- regulator-name = "+5V_HDMI_CON"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_5v0_ts: regulator@11 { +- compatible = "regulator-fixed"; +- regulator-name = "+5V_VDD_TS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vdd_3v3_lp0: regulator@12 { +- compatible = "regulator-fixed"; +- regulator-name = "+3.3V_LP0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- /* +- * TODO: find a way to wire this up with the USB EHCI +- * controllers so that it can be enabled on demand. +- */ +- regulator-always-on; +- gpio = <&as3722 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_3v3_sys>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra132.dtsi b/scripts/dtc/include-prefixes/arm64/nvidia/tegra132.dtsi +deleted file mode 100644 +index b0bcda8cc51f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra132.dtsi ++++ /dev/null +@@ -1,1253 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "nvidia,tegra132", "nvidia,tegra124"; +- interrupt-parent = <&lic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- pcie@1003000 { +- compatible = "nvidia,tegra124-pcie"; +- device_type = "pci"; +- reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ +- <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ +- <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ +- reg-names = "pads", "afi", "cs"; +- interrupts = , /* controller interrupt */ +- ; /* MSI interrupt */ +- interrupt-names = "intr", "msi"; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; +- +- bus-range = <0x00 0xff>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ +- <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ +- <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ +- <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ +- <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ +- +- clocks = <&tegra_car TEGRA124_CLK_PCIE>, +- <&tegra_car TEGRA124_CLK_AFI>, +- <&tegra_car TEGRA124_CLK_PLL_E>, +- <&tegra_car TEGRA124_CLK_CML0>; +- clock-names = "pex", "afi", "pll_e", "cml"; +- resets = <&tegra_car 70>, +- <&tegra_car 72>, +- <&tegra_car 74>; +- reset-names = "pex", "afi", "pcie_x"; +- status = "disabled"; +- +- pci@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; +- reg = <0x000800 0 0 0 0>; +- bus-range = <0x00 0xff>; +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- ranges; +- +- nvidia,num-lanes = <2>; +- }; +- +- pci@2,0 { +- device_type = "pci"; +- assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; +- reg = <0x001000 0 0 0 0>; +- bus-range = <0x00 0xff>; +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- ranges; +- +- nvidia,num-lanes = <1>; +- }; +- }; +- +- host1x@50000000 { +- compatible = "nvidia,tegra132-host1x", +- "nvidia,tegra124-host1x"; +- reg = <0x0 0x50000000 0x0 0x00034000>; +- interrupts = , /* syncpt */ +- ; /* general */ +- interrupt-names = "syncpt", "host1x"; +- clocks = <&tegra_car TEGRA124_CLK_HOST1X>; +- clock-names = "host1x"; +- resets = <&tegra_car 28>; +- reset-names = "host1x"; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; +- +- dc@54200000 { +- compatible = "nvidia,tegra124-dc"; +- reg = <0x0 0x54200000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_DISP1>; +- clock-names = "dc"; +- resets = <&tegra_car 27>; +- reset-names = "dc"; +- +- iommus = <&mc TEGRA_SWGROUP_DC>; +- +- nvidia,head = <0>; +- }; +- +- dc@54240000 { +- compatible = "nvidia,tegra124-dc"; +- reg = <0x0 0x54240000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_DISP2>; +- clock-names = "dc"; +- resets = <&tegra_car 26>; +- reset-names = "dc"; +- +- iommus = <&mc TEGRA_SWGROUP_DCB>; +- +- nvidia,head = <1>; +- }; +- +- hdmi@54280000 { +- compatible = "nvidia,tegra124-hdmi"; +- reg = <0x0 0x54280000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_HDMI>, +- <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; +- clock-names = "hdmi", "parent"; +- resets = <&tegra_car 51>; +- reset-names = "hdmi"; +- status = "disabled"; +- }; +- +- sor@54540000 { +- compatible = "nvidia,tegra124-sor"; +- reg = <0x0 0x54540000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_SOR0>, +- <&tegra_car TEGRA124_CLK_SOR0_OUT>, +- <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, +- <&tegra_car TEGRA124_CLK_PLL_DP>, +- <&tegra_car TEGRA124_CLK_CLK_M>; +- clock-names = "sor", "out", "parent", "dp", "safe"; +- resets = <&tegra_car 182>; +- reset-names = "sor"; +- status = "disabled"; +- }; +- +- dpaux: dpaux@545c0000 { +- compatible = "nvidia,tegra124-dpaux"; +- reg = <0x0 0x545c0000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_DPAUX>, +- <&tegra_car TEGRA124_CLK_PLL_DP>; +- clock-names = "dpaux", "parent"; +- resets = <&tegra_car 181>; +- reset-names = "dpaux"; +- status = "disabled"; +- +- i2c-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- }; +- +- gic: interrupt-controller@50041000 { +- compatible = "arm,cortex-a15-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x0 0x50041000 0x0 0x1000>, +- <0x0 0x50042000 0x0 0x2000>, +- <0x0 0x50044000 0x0 0x2000>, +- <0x0 0x50046000 0x0 0x2000>; +- interrupts = ; +- interrupt-parent = <&gic>; +- }; +- +- gpu@57000000 { +- compatible = "nvidia,gk20a"; +- reg = <0x0 0x57000000 0x0 0x01000000>, +- <0x0 0x58000000 0x0 0x01000000>; +- interrupts = , +- ; +- interrupt-names = "stall", "nonstall"; +- clocks = <&tegra_car TEGRA124_CLK_GPU>, +- <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; +- clock-names = "gpu", "pwr"; +- resets = <&tegra_car 184>; +- reset-names = "gpu"; +- status = "disabled"; +- }; +- +- lic: interrupt-controller@60004000 { +- compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; +- reg = <0x0 0x60004000 0x0 0x100>, +- <0x0 0x60004100 0x0 0x100>, +- <0x0 0x60004200 0x0 0x100>, +- <0x0 0x60004300 0x0 0x100>, +- <0x0 0x60004400 0x0 0x100>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- }; +- +- timer@60005000 { +- compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; +- reg = <0x0 0x60005000 0x0 0x400>; +- interrupts = , +- , +- , +- , +- , +- ; +- clocks = <&tegra_car TEGRA124_CLK_TIMER>; +- clock-names = "timer"; +- }; +- +- tegra_car: clock@60006000 { +- compatible = "nvidia,tegra132-car"; +- reg = <0x0 0x60006000 0x0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- nvidia,external-memory-controller = <&emc>; +- }; +- +- flow-controller@60007000 { +- compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl"; +- reg = <0x0 0x60007000 0x0 0x1000>; +- }; +- +- actmon@6000c800 { +- compatible = "nvidia,tegra124-actmon"; +- reg = <0x0 0x6000c800 0x0 0x400>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_ACTMON>, +- <&tegra_car TEGRA124_CLK_EMC>; +- clock-names = "actmon", "emc"; +- resets = <&tegra_car 119>; +- reset-names = "actmon"; +- }; +- +- gpio: gpio@6000d000 { +- compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; +- reg = <0x0 0x6000d000 0x0 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- #gpio-cells = <2>; +- gpio-controller; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- apbdma: dma@60020000 { +- compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; +- reg = <0x0 0x60020000 0x0 0x1400>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&tegra_car TEGRA124_CLK_APBDMA>; +- clock-names = "dma"; +- resets = <&tegra_car 34>; +- reset-names = "dma"; +- #dma-cells = <1>; +- }; +- +- apbmisc@70000800 { +- compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; +- reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ +- <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ +- }; +- +- pinmux: pinmux@70000868 { +- compatible = "nvidia,tegra124-pinmux"; +- reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ +- <0x0 0x70003000 0x0 0x434>, /* Mux registers */ +- <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ +- }; +- +- /* +- * There are two serial driver i.e. 8250 based simple serial +- * driver and APB DMA based serial driver for higher baudrate +- * and performance. To enable the 8250 based driver, the compatible +- * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable +- * the APB DMA based serial driver, the compatible is +- * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". +- */ +- uarta: serial@70006000 { +- compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; +- reg = <0x0 0x70006000 0x0 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_UARTA>; +- clock-names = "serial"; +- resets = <&tegra_car 6>; +- reset-names = "serial"; +- dmas = <&apbdma 8>, <&apbdma 8>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uartb: serial@70006040 { +- compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; +- reg = <0x0 0x70006040 0x0 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_UARTB>; +- clock-names = "serial"; +- resets = <&tegra_car 7>; +- reset-names = "serial"; +- dmas = <&apbdma 9>, <&apbdma 9>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uartc: serial@70006200 { +- compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; +- reg = <0x0 0x70006200 0x0 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_UARTC>; +- clock-names = "serial"; +- resets = <&tegra_car 55>; +- reset-names = "serial"; +- dmas = <&apbdma 10>, <&apbdma 10>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uartd: serial@70006300 { +- compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; +- reg = <0x0 0x70006300 0x0 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_UARTD>; +- clock-names = "serial"; +- resets = <&tegra_car 65>; +- reset-names = "serial"; +- dmas = <&apbdma 19>, <&apbdma 19>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- pwm: pwm@7000a000 { +- compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; +- reg = <0x0 0x7000a000 0x0 0x100>; +- #pwm-cells = <2>; +- clocks = <&tegra_car TEGRA124_CLK_PWM>; +- clock-names = "pwm"; +- resets = <&tegra_car 17>; +- reset-names = "pwm"; +- status = "disabled"; +- }; +- +- i2c@7000c000 { +- compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; +- reg = <0x0 0x7000c000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_I2C1>; +- clock-names = "div-clk"; +- resets = <&tegra_car 12>; +- reset-names = "i2c"; +- dmas = <&apbdma 21>, <&apbdma 21>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000c400 { +- compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; +- reg = <0x0 0x7000c400 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_I2C2>; +- clock-names = "div-clk"; +- resets = <&tegra_car 54>; +- reset-names = "i2c"; +- dmas = <&apbdma 22>, <&apbdma 22>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000c500 { +- compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; +- reg = <0x0 0x7000c500 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_I2C3>; +- clock-names = "div-clk"; +- resets = <&tegra_car 67>; +- reset-names = "i2c"; +- dmas = <&apbdma 23>, <&apbdma 23>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000c700 { +- compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; +- reg = <0x0 0x7000c700 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_I2C4>; +- clock-names = "div-clk"; +- resets = <&tegra_car 103>; +- reset-names = "i2c"; +- dmas = <&apbdma 26>, <&apbdma 26>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000d000 { +- compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; +- reg = <0x0 0x7000d000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_I2C5>; +- clock-names = "div-clk"; +- resets = <&tegra_car 47>; +- reset-names = "i2c"; +- dmas = <&apbdma 24>, <&apbdma 24>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000d100 { +- compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; +- reg = <0x0 0x7000d100 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_I2C6>; +- clock-names = "div-clk"; +- resets = <&tegra_car 166>; +- reset-names = "i2c"; +- dmas = <&apbdma 30>, <&apbdma 30>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000d400 { +- compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; +- reg = <0x0 0x7000d400 0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_SBC1>; +- clock-names = "spi"; +- resets = <&tegra_car 41>; +- reset-names = "spi"; +- dmas = <&apbdma 15>, <&apbdma 15>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000d600 { +- compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; +- reg = <0x0 0x7000d600 0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_SBC2>; +- clock-names = "spi"; +- resets = <&tegra_car 44>; +- reset-names = "spi"; +- dmas = <&apbdma 16>, <&apbdma 16>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000d800 { +- compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; +- reg = <0x0 0x7000d800 0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_SBC3>; +- clock-names = "spi"; +- resets = <&tegra_car 46>; +- reset-names = "spi"; +- dmas = <&apbdma 17>, <&apbdma 17>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000da00 { +- compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; +- reg = <0x0 0x7000da00 0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_SBC4>; +- clock-names = "spi"; +- resets = <&tegra_car 68>; +- reset-names = "spi"; +- dmas = <&apbdma 18>, <&apbdma 18>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000dc00 { +- compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; +- reg = <0x0 0x7000dc00 0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_SBC5>; +- clock-names = "spi"; +- resets = <&tegra_car 104>; +- reset-names = "spi"; +- dmas = <&apbdma 27>, <&apbdma 27>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000de00 { +- compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; +- reg = <0x0 0x7000de00 0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA124_CLK_SBC6>; +- clock-names = "spi"; +- resets = <&tegra_car 105>; +- reset-names = "spi"; +- dmas = <&apbdma 28>, <&apbdma 28>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- rtc@7000e000 { +- compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; +- reg = <0x0 0x7000e000 0x0 0x100>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_RTC>; +- clock-names = "rtc"; +- }; +- +- tegra_pmc: pmc@7000e400 { +- compatible = "nvidia,tegra124-pmc"; +- reg = <0x0 0x7000e400 0x0 0x400>; +- clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; +- clock-names = "pclk", "clk32k_in"; +- #clock-cells = <1>; +- }; +- +- fuse@7000f800 { +- compatible = "nvidia,tegra124-efuse"; +- reg = <0x0 0x7000f800 0x0 0x400>; +- clocks = <&tegra_car TEGRA124_CLK_FUSE>; +- clock-names = "fuse"; +- resets = <&tegra_car 39>; +- reset-names = "fuse"; +- }; +- +- mc: memory-controller@70019000 { +- compatible = "nvidia,tegra132-mc"; +- reg = <0x0 0x70019000 0x0 0x1000>; +- clocks = <&tegra_car TEGRA124_CLK_MC>; +- clock-names = "mc"; +- +- interrupts = ; +- +- #iommu-cells = <1>; +- }; +- +- emc: external-memory-controller@7001b000 { +- compatible = "nvidia,tegra132-emc"; +- reg = <0x0 0x7001b000 0x0 0x1000>; +- clocks = <&tegra_car TEGRA124_CLK_EMC>; +- clock-names = "emc"; +- +- nvidia,memory-controller = <&mc>; +- }; +- +- sata@70020000 { +- compatible = "nvidia,tegra124-ahci"; +- reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ +- <0x0 0x70020000 0x0 0x7000>; /* SATA */ +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_SATA>, +- <&tegra_car TEGRA124_CLK_SATA_OOB>, +- <&tegra_car TEGRA124_CLK_CML1>, +- <&tegra_car TEGRA124_CLK_PLL_E>; +- clock-names = "sata", "sata-oob", "cml1", "pll_e"; +- resets = <&tegra_car 124>, +- <&tegra_car 129>, +- <&tegra_car 123>; +- reset-names = "sata", "sata-cold", "sata-oob"; +- status = "disabled"; +- }; +- +- hda@70030000 { +- compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda", +- "nvidia,tegra30-hda"; +- reg = <0x0 0x70030000 0x0 0x10000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_HDA>, +- <&tegra_car TEGRA124_CLK_HDA2HDMI>, +- <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; +- clock-names = "hda", "hda2hdmi", "hda2codec_2x"; +- resets = <&tegra_car 125>, /* hda */ +- <&tegra_car 128>, /* hda2hdmi */ +- <&tegra_car 111>; /* hda2codec_2x */ +- reset-names = "hda", "hda2hdmi", "hda2codec_2x"; +- status = "disabled"; +- }; +- +- usb@70090000 { +- compatible = "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"; +- reg = <0x0 0x70090000 0x0 0x8000>, +- <0x0 0x70098000 0x0 0x1000>, +- <0x0 0x70099000 0x0 0x1000>; +- reg-names = "hcd", "fpci", "ipfs"; +- +- interrupts = , +- ; +- +- clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, +- <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, +- <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, +- <&tegra_car TEGRA124_CLK_XUSB_SS>, +- <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, +- <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, +- <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, +- <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, +- <&tegra_car TEGRA124_CLK_PLL_U_480M>, +- <&tegra_car TEGRA124_CLK_CLK_M>, +- <&tegra_car TEGRA124_CLK_PLL_E>; +- clock-names = "xusb_host", "xusb_host_src", +- "xusb_falcon_src", "xusb_ss", +- "xusb_ss_src", "xusb_ss_div2", +- "xusb_hs_src", "xusb_fs_src", +- "pll_u_480m", "clk_m", "pll_e"; +- resets = <&tegra_car 89>, <&tegra_car 156>, +- <&tegra_car 143>; +- reset-names = "xusb_host", "xusb_ss", "xusb_src"; +- +- nvidia,xusb-padctl = <&padctl>; +- +- status = "disabled"; +- }; +- +- padctl: padctl@7009f000 { +- compatible = "nvidia,tegra132-xusb-padctl", +- "nvidia,tegra124-xusb-padctl"; +- reg = <0x0 0x7009f000 0x0 0x1000>; +- resets = <&tegra_car 142>; +- reset-names = "padctl"; +- +- pads { +- usb2 { +- status = "disabled"; +- +- lanes { +- usb2-0 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- usb2-1 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- usb2-2 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- ulpi { +- status = "disabled"; +- +- lanes { +- ulpi-0 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- hsic { +- status = "disabled"; +- +- lanes { +- hsic-0 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- hsic-1 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- pcie { +- status = "disabled"; +- +- lanes { +- pcie-0 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- pcie-1 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- pcie-2 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- pcie-3 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- pcie-4 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- sata { +- status = "disabled"; +- +- lanes { +- sata-0 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- }; +- }; +- +- ports { +- usb2-0 { +- status = "disabled"; +- }; +- +- usb2-1 { +- status = "disabled"; +- }; +- +- usb2-2 { +- status = "disabled"; +- }; +- +- hsic-0 { +- status = "disabled"; +- }; +- +- hsic-1 { +- status = "disabled"; +- }; +- +- usb3-0 { +- status = "disabled"; +- }; +- +- usb3-1 { +- status = "disabled"; +- }; +- }; +- }; +- +- mmc@700b0000 { +- compatible = "nvidia,tegra124-sdhci"; +- reg = <0x0 0x700b0000 0x0 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; +- clock-names = "sdhci"; +- resets = <&tegra_car 14>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- mmc@700b0200 { +- compatible = "nvidia,tegra124-sdhci"; +- reg = <0x0 0x700b0200 0x0 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; +- clock-names = "sdhci"; +- resets = <&tegra_car 9>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- mmc@700b0400 { +- compatible = "nvidia,tegra124-sdhci"; +- reg = <0x0 0x700b0400 0x0 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; +- clock-names = "sdhci"; +- resets = <&tegra_car 69>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- mmc@700b0600 { +- compatible = "nvidia,tegra124-sdhci"; +- reg = <0x0 0x700b0600 0x0 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; +- clock-names = "sdhci"; +- resets = <&tegra_car 15>; +- reset-names = "sdhci"; +- status = "disabled"; +- }; +- +- soctherm: thermal-sensor@700e2000 { +- compatible = "nvidia,tegra132-soctherm"; +- reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */ +- <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ +- reg-names = "soctherm-reg", "ccroc-reg"; +- interrupts = , +- ; +- interrupt-names = "thermal", "edp"; +- clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, +- <&tegra_car TEGRA124_CLK_SOC_THERM>; +- clock-names = "tsensor", "soctherm"; +- resets = <&tegra_car 78>; +- reset-names = "soctherm"; +- #thermal-sensor-cells = <1>; +- +- throttle-cfgs { +- throttle_heavy: heavy { +- nvidia,priority = <100>; +- nvidia,cpu-throt-level = ; +- +- #cooling-cells = <2>; +- }; +- }; +- }; +- +- thermal-zones { +- cpu { +- polling-delay-passive = <1000>; +- polling-delay = <0>; +- +- thermal-sensors = +- <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; +- +- trips { +- cpu_shutdown_trip { +- temperature = <105000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- +- cpu_throttle_trip: throttle-trip { +- temperature = <102000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_throttle_trip>; +- cooling-device = <&throttle_heavy 1 1>; +- }; +- }; +- }; +- mem { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = +- <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; +- +- trips { +- mem_shutdown_trip { +- temperature = <101000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- mem_throttle_trip { +- temperature = <99000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- +- cooling-maps { +- /* +- * There are currently no cooling maps, +- * because there are no cooling devices. +- */ +- }; +- }; +- gpu { +- polling-delay-passive = <1000>; +- polling-delay = <0>; +- +- thermal-sensors = +- <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; +- +- trips { +- gpu_shutdown_trip { +- temperature = <101000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- +- gpu_throttle_trip: throttle-trip { +- temperature = <99000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&gpu_throttle_trip>; +- cooling-device = <&throttle_heavy 1 1>; +- }; +- }; +- }; +- pllx { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = +- <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; +- +- trips { +- pllx_shutdown_trip { +- temperature = <105000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- pllx_throttle_trip { +- temperature = <99000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- +- cooling-maps { +- /* +- * There are currently no cooling maps, +- * because there are no cooling devices. +- */ +- }; +- }; +- }; +- +- ahub@70300000 { +- compatible = "nvidia,tegra124-ahub"; +- reg = <0x0 0x70300000 0x0 0x200>, +- <0x0 0x70300800 0x0 0x800>, +- <0x0 0x70300200 0x0 0x600>; +- interrupts = ; +- clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, +- <&tegra_car TEGRA124_CLK_APBIF>; +- clock-names = "d_audio", "apbif"; +- resets = <&tegra_car 106>, /* d_audio */ +- <&tegra_car 107>, /* apbif */ +- <&tegra_car 30>, /* i2s0 */ +- <&tegra_car 11>, /* i2s1 */ +- <&tegra_car 18>, /* i2s2 */ +- <&tegra_car 101>, /* i2s3 */ +- <&tegra_car 102>, /* i2s4 */ +- <&tegra_car 108>, /* dam0 */ +- <&tegra_car 109>, /* dam1 */ +- <&tegra_car 110>, /* dam2 */ +- <&tegra_car 10>, /* spdif */ +- <&tegra_car 153>, /* amx */ +- <&tegra_car 185>, /* amx1 */ +- <&tegra_car 154>, /* adx */ +- <&tegra_car 180>, /* adx1 */ +- <&tegra_car 186>, /* afc0 */ +- <&tegra_car 187>, /* afc1 */ +- <&tegra_car 188>, /* afc2 */ +- <&tegra_car 189>, /* afc3 */ +- <&tegra_car 190>, /* afc4 */ +- <&tegra_car 191>; /* afc5 */ +- reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", +- "i2s3", "i2s4", "dam0", "dam1", "dam2", +- "spdif", "amx", "amx1", "adx", "adx1", +- "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; +- dmas = <&apbdma 1>, <&apbdma 1>, +- <&apbdma 2>, <&apbdma 2>, +- <&apbdma 3>, <&apbdma 3>, +- <&apbdma 4>, <&apbdma 4>, +- <&apbdma 6>, <&apbdma 6>, +- <&apbdma 7>, <&apbdma 7>, +- <&apbdma 12>, <&apbdma 12>, +- <&apbdma 13>, <&apbdma 13>, +- <&apbdma 14>, <&apbdma 14>, +- <&apbdma 29>, <&apbdma 29>; +- dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", +- "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", +- "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", +- "rx9", "tx9"; +- ranges; +- #address-cells = <2>; +- #size-cells = <2>; +- +- tegra_i2s0: i2s@70301000 { +- compatible = "nvidia,tegra124-i2s"; +- reg = <0x0 0x70301000 0x0 0x100>; +- nvidia,ahub-cif-ids = <4 4>; +- clocks = <&tegra_car TEGRA124_CLK_I2S0>; +- clock-names = "i2s"; +- resets = <&tegra_car 30>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- +- tegra_i2s1: i2s@70301100 { +- compatible = "nvidia,tegra124-i2s"; +- reg = <0x0 0x70301100 0x0 0x100>; +- nvidia,ahub-cif-ids = <5 5>; +- clocks = <&tegra_car TEGRA124_CLK_I2S1>; +- clock-names = "i2s"; +- resets = <&tegra_car 11>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- +- tegra_i2s2: i2s@70301200 { +- compatible = "nvidia,tegra124-i2s"; +- reg = <0x0 0x70301200 0x0 0x100>; +- nvidia,ahub-cif-ids = <6 6>; +- clocks = <&tegra_car TEGRA124_CLK_I2S2>; +- clock-names = "i2s"; +- resets = <&tegra_car 18>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- +- tegra_i2s3: i2s@70301300 { +- compatible = "nvidia,tegra124-i2s"; +- reg = <0x0 0x70301300 0x0 0x100>; +- nvidia,ahub-cif-ids = <7 7>; +- clocks = <&tegra_car TEGRA124_CLK_I2S3>; +- clock-names = "i2s"; +- resets = <&tegra_car 101>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- +- tegra_i2s4: i2s@70301400 { +- compatible = "nvidia,tegra124-i2s"; +- reg = <0x0 0x70301400 0x0 0x100>; +- nvidia,ahub-cif-ids = <8 8>; +- clocks = <&tegra_car TEGRA124_CLK_I2S4>; +- clock-names = "i2s"; +- resets = <&tegra_car 102>; +- reset-names = "i2s"; +- status = "disabled"; +- }; +- }; +- +- usb@7d000000 { +- compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; +- reg = <0x0 0x7d000000 0x0 0x4000>; +- interrupts = ; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA124_CLK_USBD>; +- clock-names = "usb"; +- resets = <&tegra_car 22>; +- reset-names = "usb"; +- nvidia,phy = <&phy1>; +- status = "disabled"; +- }; +- +- phy1: usb-phy@7d000000 { +- compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; +- reg = <0x0 0x7d000000 0x0 0x4000>, +- <0x0 0x7d000000 0x0 0x4000>; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA124_CLK_USBD>, +- <&tegra_car TEGRA124_CLK_PLL_U>, +- <&tegra_car TEGRA124_CLK_USBD>; +- clock-names = "reg", "pll_u", "utmi-pads"; +- resets = <&tegra_car 22>, <&tegra_car 22>; +- reset-names = "usb", "utmi-pads"; +- #phy-cells = <0>; +- nvidia,hssync-start-delay = <0>; +- nvidia,idle-wait-delay = <17>; +- nvidia,elastic-limit = <16>; +- nvidia,term-range-adj = <6>; +- nvidia,xcvr-setup = <9>; +- nvidia,xcvr-lsfslew = <0>; +- nvidia,xcvr-lsrslew = <3>; +- nvidia,hssquelch-level = <2>; +- nvidia,hsdiscon-level = <5>; +- nvidia,xcvr-hsslew = <12>; +- nvidia,has-utmi-pad-registers; +- status = "disabled"; +- }; +- +- usb@7d004000 { +- compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; +- reg = <0x0 0x7d004000 0x0 0x4000>; +- interrupts = ; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA124_CLK_USB2>; +- clock-names = "usb"; +- resets = <&tegra_car 58>; +- reset-names = "usb"; +- nvidia,phy = <&phy2>; +- status = "disabled"; +- }; +- +- phy2: usb-phy@7d004000 { +- compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; +- reg = <0x0 0x7d004000 0x0 0x4000>, +- <0x0 0x7d000000 0x0 0x4000>; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA124_CLK_USB2>, +- <&tegra_car TEGRA124_CLK_PLL_U>, +- <&tegra_car TEGRA124_CLK_USBD>; +- clock-names = "reg", "pll_u", "utmi-pads"; +- resets = <&tegra_car 58>, <&tegra_car 22>; +- reset-names = "usb", "utmi-pads"; +- #phy-cells = <0>; +- nvidia,hssync-start-delay = <0>; +- nvidia,idle-wait-delay = <17>; +- nvidia,elastic-limit = <16>; +- nvidia,term-range-adj = <6>; +- nvidia,xcvr-setup = <9>; +- nvidia,xcvr-lsfslew = <0>; +- nvidia,xcvr-lsrslew = <3>; +- nvidia,hssquelch-level = <2>; +- nvidia,hsdiscon-level = <5>; +- nvidia,xcvr-hsslew = <12>; +- status = "disabled"; +- }; +- +- usb@7d008000 { +- compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; +- reg = <0x0 0x7d008000 0x0 0x4000>; +- interrupts = ; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA124_CLK_USB3>; +- clock-names = "usb"; +- resets = <&tegra_car 59>; +- reset-names = "usb"; +- nvidia,phy = <&phy3>; +- status = "disabled"; +- }; +- +- phy3: usb-phy@7d008000 { +- compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; +- reg = <0x0 0x7d008000 0x0 0x4000>, +- <0x0 0x7d000000 0x0 0x4000>; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA124_CLK_USB3>, +- <&tegra_car TEGRA124_CLK_PLL_U>, +- <&tegra_car TEGRA124_CLK_USBD>; +- clock-names = "reg", "pll_u", "utmi-pads"; +- resets = <&tegra_car 59>, <&tegra_car 22>; +- reset-names = "usb", "utmi-pads"; +- #phy-cells = <0>; +- nvidia,hssync-start-delay = <0>; +- nvidia,idle-wait-delay = <17>; +- nvidia,elastic-limit = <16>; +- nvidia,term-range-adj = <6>; +- nvidia,xcvr-setup = <9>; +- nvidia,xcvr-lsfslew = <0>; +- nvidia,xcvr-lsrslew = <3>; +- nvidia,hssquelch-level = <2>; +- nvidia,hsdiscon-level = <5>; +- nvidia,xcvr-hsslew = <12>; +- status = "disabled"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "nvidia,tegra132-denver"; +- reg = <0>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "nvidia,tegra132-denver"; +- reg = <1>; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = , +- , +- , +- ; +- interrupt-parent = <&gic>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra186-p2771-0000.dts b/scripts/dtc/include-prefixes/arm64/nvidia/tegra186-p2771-0000.dts +deleted file mode 100644 +index 74c1a5df3fdb..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra186-p2771-0000.dts ++++ /dev/null +@@ -1,1114 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +- +-#include "tegra186-p3310.dtsi" +- +-/ { +- model = "NVIDIA Jetson TX2 Developer Kit"; +- compatible = "nvidia,p2771-0000", "nvidia,tegra186"; +- +- aconnect@2900000 { +- status = "okay"; +- +- dma-controller@2930000 { +- status = "okay"; +- }; +- +- interrupt-controller@2a40000 { +- status = "okay"; +- }; +- +- ahub@2900800 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0x0>; +- +- xbar_admaif0_ep: endpoint { +- remote-endpoint = <&admaif0_ep>; +- }; +- }; +- +- port@1 { +- reg = <0x1>; +- +- xbar_admaif1_ep: endpoint { +- remote-endpoint = <&admaif1_ep>; +- }; +- }; +- +- port@2 { +- reg = <0x2>; +- +- xbar_admaif2_ep: endpoint { +- remote-endpoint = <&admaif2_ep>; +- }; +- }; +- +- port@3 { +- reg = <0x3>; +- +- xbar_admaif3_ep: endpoint { +- remote-endpoint = <&admaif3_ep>; +- }; +- }; +- +- port@4 { +- reg = <0x4>; +- +- xbar_admaif4_ep: endpoint { +- remote-endpoint = <&admaif4_ep>; +- }; +- }; +- +- port@5 { +- reg = <0x5>; +- +- xbar_admaif5_ep: endpoint { +- remote-endpoint = <&admaif5_ep>; +- }; +- }; +- +- port@6 { +- reg = <0x6>; +- +- xbar_admaif6_ep: endpoint { +- remote-endpoint = <&admaif6_ep>; +- }; +- }; +- +- port@7 { +- reg = <0x7>; +- +- xbar_admaif7_ep: endpoint { +- remote-endpoint = <&admaif7_ep>; +- }; +- }; +- +- port@8 { +- reg = <0x8>; +- +- xbar_admaif8_ep: endpoint { +- remote-endpoint = <&admaif8_ep>; +- }; +- }; +- +- port@9 { +- reg = <0x9>; +- +- xbar_admaif9_ep: endpoint { +- remote-endpoint = <&admaif9_ep>; +- }; +- }; +- +- port@a { +- reg = <0xa>; +- +- xbar_admaif10_ep: endpoint { +- remote-endpoint = <&admaif10_ep>; +- }; +- }; +- +- port@b { +- reg = <0xb>; +- +- xbar_admaif11_ep: endpoint { +- remote-endpoint = <&admaif11_ep>; +- }; +- }; +- +- port@c { +- reg = <0xc>; +- +- xbar_admaif12_ep: endpoint { +- remote-endpoint = <&admaif12_ep>; +- }; +- }; +- +- port@d { +- reg = <0xd>; +- +- xbar_admaif13_ep: endpoint { +- remote-endpoint = <&admaif13_ep>; +- }; +- }; +- +- port@e { +- reg = <0xe>; +- +- xbar_admaif14_ep: endpoint { +- remote-endpoint = <&admaif14_ep>; +- }; +- }; +- +- port@f { +- reg = <0xf>; +- +- xbar_admaif15_ep: endpoint { +- remote-endpoint = <&admaif15_ep>; +- }; +- }; +- +- port@10 { +- reg = <0x10>; +- +- xbar_admaif16_ep: endpoint { +- remote-endpoint = <&admaif16_ep>; +- }; +- }; +- +- port@11 { +- reg = <0x11>; +- +- xbar_admaif17_ep: endpoint { +- remote-endpoint = <&admaif17_ep>; +- }; +- }; +- +- port@12 { +- reg = <0x12>; +- +- xbar_admaif18_ep: endpoint { +- remote-endpoint = <&admaif18_ep>; +- }; +- }; +- +- port@13 { +- reg = <0x13>; +- +- xbar_admaif19_ep: endpoint { +- remote-endpoint = <&admaif19_ep>; +- }; +- }; +- +- xbar_i2s1_port: port@14 { +- reg = <0x14>; +- +- xbar_i2s1_ep: endpoint { +- remote-endpoint = <&i2s1_cif_ep>; +- }; +- }; +- +- xbar_i2s2_port: port@15 { +- reg = <0x15>; +- +- xbar_i2s2_ep: endpoint { +- remote-endpoint = <&i2s2_cif_ep>; +- }; +- }; +- +- xbar_i2s3_port: port@16 { +- reg = <0x16>; +- +- xbar_i2s3_ep: endpoint { +- remote-endpoint = <&i2s3_cif_ep>; +- }; +- }; +- +- xbar_i2s4_port: port@17 { +- reg = <0x17>; +- +- xbar_i2s4_ep: endpoint { +- remote-endpoint = <&i2s4_cif_ep>; +- }; +- }; +- +- xbar_i2s5_port: port@18 { +- reg = <0x18>; +- +- xbar_i2s5_ep: endpoint { +- remote-endpoint = <&i2s5_cif_ep>; +- }; +- }; +- +- xbar_i2s6_port: port@19 { +- reg = <0x19>; +- +- xbar_i2s6_ep: endpoint { +- remote-endpoint = <&i2s6_cif_ep>; +- }; +- }; +- +- xbar_dmic1_port: port@1a { +- reg = <0x1a>; +- +- xbar_dmic1_ep: endpoint { +- remote-endpoint = <&dmic1_cif_ep>; +- }; +- }; +- +- xbar_dmic2_port: port@1b { +- reg = <0x1b>; +- +- xbar_dmic2_ep: endpoint { +- remote-endpoint = <&dmic2_cif_ep>; +- }; +- }; +- +- xbar_dmic3_port: port@1c { +- reg = <0x1c>; +- +- xbar_dmic3_ep: endpoint { +- remote-endpoint = <&dmic3_cif_ep>; +- }; +- }; +- +- xbar_dspk1_port: port@1e { +- reg = <0x1e>; +- +- xbar_dspk1_ep: endpoint { +- remote-endpoint = <&dspk1_cif_ep>; +- }; +- }; +- +- xbar_dspk2_port: port@1f { +- reg = <0x1f>; +- +- xbar_dspk2_ep: endpoint { +- remote-endpoint = <&dspk2_cif_ep>; +- }; +- }; +- }; +- +- admaif@290f000 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- admaif0_port: port@0 { +- reg = <0x0>; +- +- admaif0_ep: endpoint { +- remote-endpoint = <&xbar_admaif0_ep>; +- }; +- }; +- +- admaif1_port: port@1 { +- reg = <0x1>; +- +- admaif1_ep: endpoint { +- remote-endpoint = <&xbar_admaif1_ep>; +- }; +- }; +- +- admaif2_port: port@2 { +- reg = <0x2>; +- +- admaif2_ep: endpoint { +- remote-endpoint = <&xbar_admaif2_ep>; +- }; +- }; +- +- admaif3_port: port@3 { +- reg = <0x3>; +- +- admaif3_ep: endpoint { +- remote-endpoint = <&xbar_admaif3_ep>; +- }; +- }; +- +- admaif4_port: port@4 { +- reg = <0x4>; +- +- admaif4_ep: endpoint { +- remote-endpoint = <&xbar_admaif4_ep>; +- }; +- }; +- +- admaif5_port: port@5 { +- reg = <0x5>; +- +- admaif5_ep: endpoint { +- remote-endpoint = <&xbar_admaif5_ep>; +- }; +- }; +- +- admaif6_port: port@6 { +- reg = <0x6>; +- +- admaif6_ep: endpoint { +- remote-endpoint = <&xbar_admaif6_ep>; +- }; +- }; +- +- admaif7_port: port@7 { +- reg = <0x7>; +- +- admaif7_ep: endpoint { +- remote-endpoint = <&xbar_admaif7_ep>; +- }; +- }; +- +- admaif8_port: port@8 { +- reg = <0x8>; +- +- admaif8_ep: endpoint { +- remote-endpoint = <&xbar_admaif8_ep>; +- }; +- }; +- +- admaif9_port: port@9 { +- reg = <0x9>; +- +- admaif9_ep: endpoint { +- remote-endpoint = <&xbar_admaif9_ep>; +- }; +- }; +- +- admaif10_port: port@a { +- reg = <0xa>; +- +- admaif10_ep: endpoint { +- remote-endpoint = <&xbar_admaif10_ep>; +- }; +- }; +- +- admaif11_port: port@b { +- reg = <0xb>; +- +- admaif11_ep: endpoint { +- remote-endpoint = <&xbar_admaif11_ep>; +- }; +- }; +- +- admaif12_port: port@c { +- reg = <0xc>; +- +- admaif12_ep: endpoint { +- remote-endpoint = <&xbar_admaif12_ep>; +- }; +- }; +- +- admaif13_port: port@d { +- reg = <0xd>; +- +- admaif13_ep: endpoint { +- remote-endpoint = <&xbar_admaif13_ep>; +- }; +- }; +- +- admaif14_port: port@e { +- reg = <0xe>; +- +- admaif14_ep: endpoint { +- remote-endpoint = <&xbar_admaif14_ep>; +- }; +- }; +- +- admaif15_port: port@f { +- reg = <0xf>; +- +- admaif15_ep: endpoint { +- remote-endpoint = <&xbar_admaif15_ep>; +- }; +- }; +- +- admaif16_port: port@10 { +- reg = <0x10>; +- +- admaif16_ep: endpoint { +- remote-endpoint = <&xbar_admaif16_ep>; +- }; +- }; +- +- admaif17_port: port@11 { +- reg = <0x11>; +- +- admaif17_ep: endpoint { +- remote-endpoint = <&xbar_admaif17_ep>; +- }; +- }; +- +- admaif18_port: port@12 { +- reg = <0x12>; +- +- admaif18_ep: endpoint { +- remote-endpoint = <&xbar_admaif18_ep>; +- }; +- }; +- +- admaif19_port: port@13 { +- reg = <0x13>; +- +- admaif19_ep: endpoint { +- remote-endpoint = <&xbar_admaif19_ep>; +- }; +- }; +- }; +- }; +- +- i2s@2901000 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- i2s1_cif_ep: endpoint { +- remote-endpoint = <&xbar_i2s1_ep>; +- }; +- }; +- +- i2s1_port: port@1 { +- reg = <1>; +- +- i2s1_dap_ep: endpoint { +- dai-format = "i2s"; +- /* Placeholder for external Codec */ +- }; +- }; +- }; +- }; +- +- i2s@2901100 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- i2s2_cif_ep: endpoint { +- remote-endpoint = <&xbar_i2s2_ep>; +- }; +- }; +- +- i2s2_port: port@1 { +- reg = <1>; +- +- i2s2_dap_ep: endpoint { +- dai-format = "i2s"; +- /* Placeholder for external Codec */ +- }; +- }; +- }; +- }; +- +- i2s@2901200 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- i2s3_cif_ep: endpoint { +- remote-endpoint = <&xbar_i2s3_ep>; +- }; +- }; +- +- i2s3_port: port@1 { +- reg = <1>; +- +- i2s3_dap_ep: endpoint { +- dai-format = "i2s"; +- /* Placeholder for external Codec */ +- }; +- }; +- }; +- }; +- +- i2s@2901300 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- i2s4_cif_ep: endpoint { +- remote-endpoint = <&xbar_i2s4_ep>; +- }; +- }; +- +- i2s4_port: port@1 { +- reg = <1>; +- +- i2s4_dap_ep: endpoint { +- dai-format = "i2s"; +- /* Placeholder for external Codec */ +- }; +- }; +- }; +- }; +- +- i2s@2901400 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- i2s5_cif_ep: endpoint { +- remote-endpoint = <&xbar_i2s5_ep>; +- }; +- }; +- +- i2s5_port: port@1 { +- reg = <1>; +- +- i2s5_dap_ep: endpoint { +- dai-format = "i2s"; +- /* Placeholder for external Codec */ +- }; +- }; +- }; +- }; +- +- i2s@2901500 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- i2s6_cif_ep: endpoint { +- remote-endpoint = <&xbar_i2s6_ep>; +- }; +- }; +- +- i2s6_port: port@1 { +- reg = <1>; +- +- i2s6_dap_ep: endpoint { +- dai-format = "i2s"; +- /* Placeholder for external Codec */ +- }; +- }; +- }; +- }; +- +- dmic@2904000 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- dmic1_cif_ep: endpoint { +- remote-endpoint = <&xbar_dmic1_ep>; +- }; +- }; +- +- dmic1_port: port@1 { +- reg = <1>; +- +- dmic1_dap_ep: endpoint { +- /* Place holder for external Codec */ +- }; +- }; +- }; +- }; +- +- dmic@2904100 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- dmic2_cif_ep: endpoint { +- remote-endpoint = <&xbar_dmic2_ep>; +- }; +- }; +- +- dmic2_port: port@1 { +- reg = <1>; +- +- dmic2_dap_ep: endpoint { +- /* Place holder for external Codec */ +- }; +- }; +- }; +- }; +- +- dmic@2904200 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- dmic3_cif_ep: endpoint { +- remote-endpoint = <&xbar_dmic3_ep>; +- }; +- }; +- +- dmic3_port: port@1 { +- reg = <1>; +- +- dmic3_dap_ep: endpoint { +- /* Place holder for external Codec */ +- }; +- }; +- }; +- }; +- +- dspk@2905000 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- dspk1_cif_ep: endpoint { +- remote-endpoint = <&xbar_dspk1_ep>; +- }; +- }; +- +- dspk1_port: port@1 { +- reg = <1>; +- +- dspk1_dap_ep: endpoint { +- /* Place holder for external Codec */ +- }; +- }; +- }; +- }; +- +- dspk@2905100 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- dspk2_cif_ep: endpoint { +- remote-endpoint = <&xbar_dspk2_ep>; +- }; +- }; +- +- dspk2_port: port@1 { +- reg = <1>; +- +- dspk2_dap_ep: endpoint { +- /* Place holder for external Codec */ +- }; +- }; +- }; +- }; +- }; +- }; +- +- i2c@3160000 { +- power-monitor@42 { +- compatible = "ti,ina3221"; +- reg = <0x42>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@0 { +- reg = <0x0>; +- label = "VDD_MUX"; +- shunt-resistor-micro-ohms = <20000>; +- }; +- +- channel@1 { +- reg = <0x1>; +- label = "VDD_5V0_IO_SYS"; +- shunt-resistor-micro-ohms = <5000>; +- }; +- +- channel@2 { +- reg = <0x2>; +- label = "VDD_3V3_SYS"; +- shunt-resistor-micro-ohms = <10000>; +- }; +- }; +- +- power-monitor@43 { +- compatible = "ti,ina3221"; +- reg = <0x43>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@0 { +- reg = <0x0>; +- label = "VDD_3V3_IO_SLP"; +- shunt-resistor-micro-ohms = <10000>; +- }; +- +- channel@1 { +- reg = <0x1>; +- label = "VDD_1V8_IO"; +- shunt-resistor-micro-ohms = <10000>; +- }; +- +- channel@2 { +- reg = <0x2>; +- label = "VDD_M2_IN"; +- shunt-resistor-micro-ohms = <10000>; +- }; +- }; +- +- exp1: gpio@74 { +- compatible = "ti,tca9539"; +- reg = <0x74>; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- vcc-supply = <&vdd_3v3_sys>; +- }; +- +- exp2: gpio@77 { +- compatible = "ti,tca9539"; +- reg = <0x77>; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- vcc-supply = <&vdd_1v8>; +- }; +- }; +- +- /* SDMMC1 (SD/MMC) */ +- mmc@3400000 { +- status = "okay"; +- +- vmmc-supply = <&vdd_sd>; +- }; +- +- hda@3510000 { +- nvidia,model = "NVIDIA Jetson TX2 HDA"; +- status = "okay"; +- }; +- +- padctl@3520000 { +- status = "okay"; +- +- avdd-pll-erefeut-supply = <&vdd_1v8_pll>; +- avdd-usb-supply = <&vdd_3v3_sys>; +- vclamp-usb-supply = <&vdd_1v8>; +- vddio-hsic-supply = <&gnd>; +- +- pads { +- usb2 { +- status = "okay"; +- +- lanes { +- micro_b: usb2-0 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- +- usb2-1 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- +- usb2-2 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- }; +- }; +- +- usb3 { +- status = "okay"; +- +- lanes { +- usb3-0 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- +- usb3-1 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- +- usb3-2 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- }; +- }; +- }; +- +- ports { +- usb2-0 { +- status = "okay"; +- mode = "otg"; +- vbus-supply = <&vdd_usb0>; +- usb-role-switch; +- +- connector { +- compatible = "gpio-usb-b-connector", +- "usb-b-connector"; +- label = "micro-USB"; +- type = "micro"; +- vbus-gpios = <&gpio +- TEGRA186_MAIN_GPIO(X, 7) +- GPIO_ACTIVE_LOW>; +- id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- usb2-1 { +- status = "okay"; +- mode = "host"; +- +- vbus-supply = <&vdd_usb1>; +- }; +- +- usb3-0 { +- nvidia,usb2-companion = <1>; +- vbus-supply = <&vdd_usb1>; +- status = "okay"; +- }; +- }; +- }; +- +- usb@3530000 { +- status = "okay"; +- +- phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>, +- <&{/padctl@3520000/pads/usb2/lanes/usb2-1}>, +- <&{/padctl@3520000/pads/usb3/lanes/usb3-0}>; +- phy-names = "usb2-0", "usb2-1", "usb3-0"; +- }; +- +- usb@3550000 { +- status = "okay"; +- +- phys = <µ_b>; +- phy-names = "usb2-0"; +- }; +- +- i2c@c250000 { +- /* carrier board ID EEPROM */ +- eeprom@57 { +- compatible = "atmel,24c02"; +- reg = <0x57>; +- +- label = "system"; +- vcc-supply = <&vdd_1v8>; +- address-width = <8>; +- pagesize = <8>; +- size = <256>; +- read-only; +- }; +- }; +- +- pcie@10003000 { +- status = "okay"; +- +- dvdd-pex-supply = <&vdd_pex>; +- hvdd-pex-pll-supply = <&vdd_1v8>; +- hvdd-pex-supply = <&vdd_1v8>; +- vddio-pexctl-aud-supply = <&vdd_1v8>; +- +- pci@1,0 { +- nvidia,num-lanes = <4>; +- status = "okay"; +- }; +- +- pci@2,0 { +- nvidia,num-lanes = <0>; +- status = "disabled"; +- }; +- +- pci@3,0 { +- nvidia,num-lanes = <1>; +- status = "disabled"; +- }; +- }; +- +- host1x@13e00000 { +- status = "okay"; +- +- dpaux@15040000 { +- status = "okay"; +- }; +- +- display-hub@15200000 { +- status = "okay"; +- }; +- +- dsi@15300000 { +- status = "disabled"; +- }; +- +- /* DP on E3320 */ +- sor@15540000 { +- status = "okay"; +- +- avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>; +- vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>; +- +- nvidia,dpaux = <&dpaux>; +- }; +- +- sor@15580000 { +- status = "okay"; +- +- avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>; +- vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>; +- hdmi-supply = <&vdd_hdmi>; +- +- nvidia,ddc-i2c-bus = <&ddc>; +- nvidia,hpd-gpio = <&gpio TEGRA186_MAIN_GPIO(P, 1) +- GPIO_ACTIVE_LOW>; +- }; +- +- dpaux@155c0000 { +- status = "okay"; +- }; +- }; +- +- sata@3507000 { +- status = "okay"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "Power"; +- gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0) +- GPIO_ACTIVE_LOW>; +- linux,input-type = ; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-event-action = ; +- wakeup-source; +- }; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) +- GPIO_ACTIVE_LOW>; +- linux,input-type = ; +- linux,code = ; +- debounce-interval = <10>; +- }; +- +- volume-down { +- label = "Volume Down"; +- gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) +- GPIO_ACTIVE_LOW>; +- linux,input-type = ; +- linux,code = ; +- debounce-interval = <10>; +- }; +- }; +- +- vdd_sd: regulator@100 { +- compatible = "regulator-fixed"; +- regulator-name = "SD_CARD_SW_PWR"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio TEGRA186_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- vin-supply = <&vdd_3v3_sys>; +- }; +- +- vdd_hdmi: regulator@101 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_HDMI_5V0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- gpio = <&exp1 14 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_usb0: regulator@102 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_USB0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- gpio = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_usb1: regulator@103 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_USB1"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- gpio = <&gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- sound { +- compatible = "nvidia,tegra186-audio-graph-card"; +- status = "okay"; +- +- dais = /* FE */ +- <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, +- <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, +- <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, +- <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, +- <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, +- /* Router */ +- <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>, +- <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_i2s6_port>, +- <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic3_port>, +- <&xbar_dspk1_port>, <&xbar_dspk2_port>, +- /* I/O */ +- <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>, +- <&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>, +- <&dmic3_port>, <&dspk1_port>, <&dspk2_port>; +- +- label = "NVIDIA Jetson TX2 APE"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra186-p3310.dtsi b/scripts/dtc/include-prefixes/arm64/nvidia/tegra186-p3310.dtsi +deleted file mode 100644 +index fcd71bfc6707..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra186-p3310.dtsi ++++ /dev/null +@@ -1,425 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "tegra186.dtsi" +- +-#include +- +-/ { +- model = "NVIDIA Jetson TX2"; +- compatible = "nvidia,p3310", "nvidia,tegra186"; +- +- aliases { +- ethernet0 = "/ethernet@2490000"; +- i2c0 = "/bpmp/i2c"; +- i2c1 = "/i2c@3160000"; +- i2c2 = "/i2c@c240000"; +- i2c3 = "/i2c@3180000"; +- i2c4 = "/i2c@3190000"; +- i2c5 = "/i2c@31c0000"; +- i2c6 = "/i2c@c250000"; +- i2c7 = "/i2c@31e0000"; +- mmc0 = "/mmc@3460000"; +- mmc1 = "/mmc@3400000"; +- serial0 = &uarta; +- }; +- +- chosen { +- bootargs = "earlycon console=ttyS0,115200n8 fw_devlink=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x2 0x00000000>; +- }; +- +- ethernet@2490000 { +- status = "okay"; +- +- phy-reset-gpios = <&gpio TEGRA186_MAIN_GPIO(M, 4) +- GPIO_ACTIVE_LOW>; +- phy-handle = <&phy>; +- phy-mode = "rgmii"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy: phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0x0>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- +- #phy-cells = <0>; +- }; +- }; +- }; +- +- memory-controller@2c00000 { +- status = "okay"; +- }; +- +- serial@3100000 { +- status = "okay"; +- }; +- +- i2c@3160000 { +- status = "okay"; +- +- power-monitor@40 { +- compatible = "ti,ina3221"; +- reg = <0x40>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@0 { +- reg = <0x0>; +- label = "VDD_SYS_GPU"; +- shunt-resistor-micro-ohms = <10000>; +- }; +- +- channel@1 { +- reg = <0x1>; +- label = "VDD_SYS_SOC"; +- shunt-resistor-micro-ohms = <10000>; +- }; +- +- channel@2 { +- reg = <0x2>; +- label = "VDD_3V8_WIFI"; +- shunt-resistor-micro-ohms = <10000>; +- }; +- }; +- +- power-monitor@41 { +- compatible = "ti,ina3221"; +- reg = <0x41>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@0 { +- reg = <0x0>; +- label = "VDD_IN"; +- shunt-resistor-micro-ohms = <5000>; +- }; +- +- channel@1 { +- reg = <0x1>; +- label = "VDD_SYS_CPU"; +- shunt-resistor-micro-ohms = <10000>; +- }; +- +- channel@2 { +- reg = <0x2>; +- label = "VDD_5V0_DDR"; +- shunt-resistor-micro-ohms = <10000>; +- }; +- }; +- }; +- +- i2c@3180000 { +- status = "okay"; +- }; +- +- ddc: i2c@3190000 { +- status = "okay"; +- }; +- +- i2c@31c0000 { +- status = "okay"; +- }; +- +- i2c@31e0000 { +- status = "okay"; +- }; +- +- /* SDMMC1 (SD/MMC) */ +- mmc@3400000 { +- cd-gpios = <&gpio TEGRA186_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio TEGRA186_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>; +- +- vqmmc-supply = <&vddio_sdmmc1>; +- }; +- +- /* SDMMC3 (SDIO) */ +- mmc@3440000 { +- status = "okay"; +- }; +- +- /* SDMMC4 (eMMC) */ +- mmc@3460000 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- +- vqmmc-supply = <&vdd_1v8_ap>; +- vmmc-supply = <&vdd_3v3_sys>; +- }; +- +- hsp@3c00000 { +- status = "okay"; +- }; +- +- i2c@c240000 { +- status = "okay"; +- }; +- +- i2c@c250000 { +- status = "okay"; +- +- /* module ID EEPROM */ +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- +- label = "module"; +- vcc-supply = <&vdd_1v8>; +- address-width = <8>; +- pagesize = <8>; +- size = <256>; +- read-only; +- }; +- }; +- +- rtc@c2a0000 { +- status = "okay"; +- }; +- +- pmc@c360000 { +- nvidia,invert-interrupt; +- }; +- +- cpus { +- cpu@0 { +- enable-method = "psci"; +- }; +- +- cpu@1 { +- enable-method = "psci"; +- }; +- +- cpu@2 { +- enable-method = "psci"; +- }; +- +- cpu@3 { +- enable-method = "psci"; +- }; +- +- cpu@4 { +- enable-method = "psci"; +- }; +- +- cpu@5 { +- enable-method = "psci"; +- }; +- }; +- +- bpmp { +- i2c { +- status = "okay"; +- +- pmic: pmic@3c { +- compatible = "maxim,max77620"; +- reg = <0x3c>; +- +- interrupt-parent = <&pmc>; +- interrupts = <24 IRQ_TYPE_LEVEL_LOW>; +- #interrupt-cells = <2>; +- interrupt-controller; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&max77620_default>; +- +- max77620_default: pinmux { +- gpio0 { +- pins = "gpio0"; +- function = "gpio"; +- }; +- +- gpio1 { +- pins = "gpio1"; +- function = "fps-out"; +- maxim,active-fps-source = ; +- }; +- +- gpio2 { +- pins = "gpio2"; +- function = "fps-out"; +- maxim,active-fps-source = ; +- }; +- +- gpio3 { +- pins = "gpio3"; +- function = "fps-out"; +- maxim,active-fps-source = ; +- }; +- +- gpio4 { +- pins = "gpio4"; +- function = "32k-out1"; +- drive-push-pull = <1>; +- }; +- +- gpio5 { +- pins = "gpio5"; +- function = "gpio"; +- drive-push-pull = <0>; +- }; +- +- gpio6 { +- pins = "gpio6"; +- function = "gpio"; +- drive-push-pull = <1>; +- }; +- +- gpio7 { +- pins = "gpio7"; +- function = "gpio"; +- drive-push-pull = <0>; +- }; +- }; +- +- fps { +- fps0 { +- maxim,fps-event-source = ; +- maxim,shutdown-fps-time-period-us = <640>; +- }; +- +- fps1 { +- maxim,fps-event-source = ; +- maxim,shutdown-fps-time-period-us = <640>; +- }; +- +- fps2 { +- maxim,fps-event-source = ; +- maxim,shutdown-fps-time-period-us = <640>; +- }; +- }; +- +- regulators { +- in-sd0-supply = <&vdd_5v0_sys>; +- in-sd1-supply = <&vdd_5v0_sys>; +- in-sd2-supply = <&vdd_5v0_sys>; +- in-sd3-supply = <&vdd_5v0_sys>; +- +- in-ldo0-1-supply = <&vdd_5v0_sys>; +- in-ldo2-supply = <&vdd_5v0_sys>; +- in-ldo3-5-supply = <&vdd_5v0_sys>; +- in-ldo4-6-supply = <&vdd_1v8>; +- in-ldo7-8-supply = <&avdd_dsi_csi>; +- +- sd0 { +- regulator-name = "VDD_DDR_1V1_PMIC"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- avdd_dsi_csi: sd1 { +- regulator-name = "AVDD_DSI_CSI_1V2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- vdd_1v8: sd2 { +- regulator-name = "VDD_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vdd_3v3_sys: sd3 { +- regulator-name = "VDD_3V3_SYS"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vdd_1v8_pll: ldo0 { +- regulator-name = "VDD_1V8_AP_PLL"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo2 { +- regulator-name = "VDDIO_3V3_AOHV"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vddio_sdmmc1: ldo3 { +- regulator-name = "VDDIO_SDMMC1_AP"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo4 { +- regulator-name = "VDD_RTC"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- vddio_sdmmc3: ldo5 { +- regulator-name = "VDDIO_SDMMC3_AP"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- vdd_hdmi_1v05: ldo7 { +- regulator-name = "VDD_HDMI_1V05"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- vdd_pex: ldo8 { +- regulator-name = "VDD_PEX_1V05"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- }; +- }; +- }; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- status = "okay"; +- method = "smc"; +- }; +- +- gnd: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "GND"; +- regulator-min-microvolt = <0>; +- regulator-max-microvolt = <0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_5v0_sys: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_5V0_SYS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v8_ap: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_1V8_AP"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- vin-supply = <&vdd_1v8>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra186-p3509-0000+p3636-0001.dts b/scripts/dtc/include-prefixes/arm64/nvidia/tegra186-p3509-0000+p3636-0001.dts +deleted file mode 100644 +index 936b106e73db..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra186-p3509-0000+p3636-0001.dts ++++ /dev/null +@@ -1,718 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +-#include +- +-#include "tegra186.dtsi" +- +-/ { +- model = "NVIDIA Jetson TX2 NX Developer Kit"; +- compatible = "nvidia,p3509-0000+p3636-0001", "nvidia,tegra186"; +- +- aliases { +- ethernet0 = "/ethernet@2490000"; +- i2c0 = "/bpmp/i2c"; +- i2c1 = "/i2c@3160000"; +- i2c2 = "/i2c@c240000"; +- i2c3 = "/i2c@3180000"; +- i2c4 = "/i2c@3190000"; +- i2c5 = "/i2c@31c0000"; +- i2c6 = "/i2c@c250000"; +- i2c7 = "/i2c@31e0000"; +- mmc0 = "/mmc@3460000"; +- serial0 = &uarta; +- }; +- +- chosen { +- bootargs = "earlycon console=ttyS0,115200n8"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0x70000000>; +- }; +- +- ethernet@2490000 { +- status = "okay"; +- +- phy-reset-gpios = <&gpio_aon TEGRA186_AON_GPIO(AA, 6) GPIO_ACTIVE_LOW>; +- phy-handle = <&phy>; +- phy-mode = "rgmii-id"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy: phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0x0>; +- interrupt-parent = <&gpio_aon>; +- interrupts = ; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- memory-controller@2c00000 { +- status = "okay"; +- }; +- +- timer@3010000 { +- status = "okay"; +- }; +- +- serial@3100000 { +- status = "okay"; +- }; +- +- i2c@3160000 { +- status = "okay"; +- }; +- +- i2c@3180000 { +- status = "okay"; +- +- power-monitor@40 { +- compatible = "ti,ina3221"; +- reg = <0x40>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@0 { +- reg = <0>; +- label = "VDD_IN"; +- shunt-resistor-micro-ohms = <5>; +- }; +- +- channel@1 { +- reg = <1>; +- label = "VDD_CPU_GPU"; +- shunt-resistor-micro-ohms = <5>; +- }; +- +- channel@2 { +- reg = <2>; +- label = "VDD_SOC"; +- shunt-resistor-micro-ohms = <>; +- }; +- }; +- }; +- +- ddc: i2c@3190000 { +- status = "okay"; +- }; +- +- i2c@31c0000 { +- status = "okay"; +- }; +- +- i2c@31e0000 { +- status = "okay"; +- }; +- +- /* SDMMC4 (eMMC) */ +- mmc@3460000 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- +- vqmmc-supply = <&vdd_1v8_ap>; +- vmmc-supply = <&vdd_3v3_sys>; +- }; +- +- hda@3510000 { +- nvidia,model = "jetson-tx2-hda"; +- status = "okay"; +- }; +- +- padctl@3520000 { +- status = "okay"; +- +- avdd-pll-erefeut-supply = <&vdd_1v8_pll>; +- avdd-usb-supply = <&vdd_3v3_sys>; +- vclamp-usb-supply = <&vdd_1v8>; +- vddio-hsic-supply = <&gnd>; +- +- pads { +- usb2 { +- status = "okay"; +- +- lanes { +- micro_b: usb2-0 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- +- usb2-1 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- +- usb2-2 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- }; +- }; +- +- usb3 { +- status = "okay"; +- +- lanes { +- usb3-1 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- }; +- }; +- }; +- +- ports { +- usb2-0 { +- status = "okay"; +- mode = "otg"; +- vbus-supply = <&vdd_5v0_sys>; +- usb-role-switch; +- +- connector { +- compatible = "gpio-usb-b-connector", +- "usb-b-connector"; +- label = "micro-USB"; +- type = "micro"; +- vbus-gpios = <&gpio +- TEGRA186_MAIN_GPIO(L, 4) +- GPIO_ACTIVE_LOW>; +- id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- usb2-1 { +- status = "okay"; +- mode = "host"; +- +- vbus-supply = <&vdd_5v0_sys>; +- }; +- +- usb2-2 { +- status = "okay"; +- mode = "host"; +- +- vbus-supply = <&vdd_5v0_sys>; +- }; +- +- usb3-1 { +- nvidia,usb2-companion = <1>; +- vbus-supply = <&vdd_5v0_sys>; +- status = "okay"; +- }; +- }; +- }; +- +- usb@3530000 { +- status = "okay"; +- +- phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>, +- <&{/padctl@3520000/pads/usb2/lanes/usb2-1}>, +- <&{/padctl@3520000/pads/usb2/lanes/usb2-2}>, +- <&{/padctl@3520000/pads/usb3/lanes/usb3-1}>; +- phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-1"; +- }; +- +- usb@3550000 { +- status = "okay"; +- +- phys = <µ_b>; +- phy-names = "usb2-0"; +- }; +- +- hsp@3c00000 { +- status = "okay"; +- }; +- +- i2c@c240000 { +- status = "okay"; +- }; +- +- i2c@c250000 { +- status = "okay"; +- +- /* module ID EEPROM */ +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- +- label = "module"; +- vcc-supply = <&vdd_1v8>; +- address-width = <8>; +- pagesize = <8>; +- size = <256>; +- read-only; +- }; +- +- /* carrier board ID EEPROM */ +- eeprom@57 { +- compatible = "atmel,24c02"; +- reg = <0x57>; +- +- label = "system"; +- vcc-supply = <&vdd_1v8>; +- address-width = <8>; +- pagesize = <8>; +- size = <256>; +- read-only; +- }; +- }; +- +- rtc@c2a0000 { +- status = "okay"; +- }; +- +- pwm@c340000 { +- status = "okay"; +- }; +- +- pmc@c360000 { +- nvidia,invert-interrupt; +- }; +- +- pcie@10003000 { +- status = "okay"; +- +- dvdd-pex-supply = <&vdd_pex>; +- hvdd-pex-pll-supply = <&vdd_1v8>; +- hvdd-pex-supply = <&vdd_1v8>; +- vddio-pexctl-aud-supply = <&vdd_1v8>; +- +- pci@1,0 { +- nvidia,num-lanes = <2>; +- status = "okay"; +- }; +- +- pci@2,0 { +- nvidia,num-lanes = <1>; +- status = "disabled"; +- }; +- +- pci@3,0 { +- nvidia,num-lanes = <1>; +- status = "okay"; +- }; +- }; +- +- host1x@13e00000 { +- status = "okay"; +- +- dpaux@15040000 { +- status = "okay"; +- }; +- +- display-hub@15200000 { +- status = "okay"; +- }; +- +- dsi@15300000 { +- status = "disabled"; +- }; +- +- /* DP */ +- sor@15540000 { +- status = "okay"; +- +- avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>; +- vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>; +- +- nvidia,dpaux = <&dpaux>; +- }; +- +- /* HDMI */ +- sor@15580000 { +- status = "okay"; +- +- avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>; +- vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>; +- hdmi-supply = <&vdd_hdmi>; +- +- nvidia,ddc-i2c-bus = <&ddc>; +- nvidia,hpd-gpio = <&gpio TEGRA186_MAIN_GPIO(P, 1) +- GPIO_ACTIVE_LOW>; +- }; +- +- dpaux@155c0000 { +- status = "okay"; +- }; +- }; +- +- gpu@17000000 { +- status = "okay"; +- }; +- +- fan: fan { +- compatible = "pwm-fan"; +- pwms = <&pwm4 0 45334>; +- +- cooling-levels = <0 64 128 255>; +- #cooling-cells = <2>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "Power"; +- gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0) +- GPIO_ACTIVE_LOW>; +- linux,input-type = ; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-event-action = ; +- wakeup-source; +- }; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) +- GPIO_ACTIVE_LOW>; +- linux,input-type = ; +- linux,code = ; +- debounce-interval = <10>; +- }; +- +- volume-down { +- label = "Volume Down"; +- gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) +- GPIO_ACTIVE_LOW>; +- linux,input-type = ; +- linux,code = ; +- debounce-interval = <10>; +- }; +- }; +- +- cpus { +- cpu@0 { +- enable-method = "psci"; +- }; +- +- cpu@1 { +- enable-method = "psci"; +- }; +- +- cpu@2 { +- enable-method = "psci"; +- }; +- +- cpu@3 { +- enable-method = "psci"; +- }; +- +- cpu@4 { +- enable-method = "psci"; +- }; +- +- cpu@5 { +- enable-method = "psci"; +- }; +- }; +- +- bpmp { +- i2c { +- status = "okay"; +- +- pmic: pmic@3c { +- compatible = "maxim,max77620"; +- reg = <0x3c>; +- +- interrupt-parent = <&pmc>; +- interrupts = <24 IRQ_TYPE_LEVEL_LOW>; +- #interrupt-cells = <2>; +- interrupt-controller; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&max77620_default>; +- +- max77620_default: pinmux { +- gpio0 { +- pins = "gpio0"; +- function = "gpio"; +- }; +- +- gpio1 { +- pins = "gpio1"; +- function = "fps-out"; +- maxim,active-fps-source = ; +- }; +- +- gpio2 { +- pins = "gpio2"; +- function = "fps-out"; +- maxim,active-fps-source = ; +- }; +- +- gpio3 { +- pins = "gpio3"; +- function = "fps-out"; +- maxim,active-fps-source = ; +- }; +- +- gpio4 { +- pins = "gpio4"; +- function = "32k-out1"; +- drive-push-pull = <1>; +- }; +- +- gpio5 { +- pins = "gpio5"; +- function = "gpio"; +- drive-push-pull = <0>; +- }; +- +- gpio6 { +- pins = "gpio6"; +- function = "gpio"; +- drive-push-pull = <1>; +- }; +- +- gpio7 { +- pins = "gpio7"; +- function = "gpio"; +- drive-push-pull = <1>; +- }; +- }; +- +- fps { +- fps0 { +- maxim,fps-event-source = ; +- maxim,shutdown-fps-time-period-us = <640>; +- }; +- +- fps1 { +- maxim,fps-event-source = ; +- maxim,shutdown-fps-time-period-us = <640>; +- }; +- +- fps2 { +- maxim,fps-event-source = ; +- maxim,shutdown-fps-time-period-us = <640>; +- }; +- }; +- +- regulators { +- in-sd0-supply = <&vdd_5v0_sys>; +- in-sd1-supply = <&vdd_5v0_sys>; +- in-sd2-supply = <&vdd_5v0_sys>; +- in-sd3-supply = <&vdd_5v0_sys>; +- +- in-ldo0-1-supply = <&vdd_5v0_sys>; +- in-ldo2-supply = <&vdd_5v0_sys>; +- in-ldo3-5-supply = <&vdd_5v0_sys>; +- in-ldo4-6-supply = <&vdd_1v8>; +- in-ldo7-8-supply = <&avdd_dsi_csi>; +- +- sd0 { +- regulator-name = "VDD_DDR_1V1_PMIC"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- avdd_dsi_csi: sd1 { +- regulator-name = "AVDD_DSI_CSI_1V2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- vdd_1v8: sd2 { +- regulator-name = "VDD_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vdd_3v3_sys: sd3 { +- regulator-name = "VDD_3V3_SYS"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vdd_1v8_pll: ldo0 { +- regulator-name = "VDD_1V8_AP_PLL"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- ldo2 { +- regulator-name = "VDDIO_3V3_AOHV"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vddio_sdmmc1: ldo3 { +- regulator-name = "VDDIO_SDMMC1_AP"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo4 { +- regulator-name = "VDD_RTC"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- vddio_sdmmc3: ldo5 { +- regulator-name = "VDDIO_SDMMC3_AP"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- vdd_hdmi_1v05: ldo7 { +- regulator-name = "VDD_HDMI_1V05"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- vdd_pex: ldo8 { +- regulator-name = "VDD_PEX_1V05"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- }; +- }; +- }; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- status = "okay"; +- method = "smc"; +- }; +- +- gnd: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "GND"; +- regulator-min-microvolt = <0>; +- regulator-max-microvolt = <0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_5v0_sys: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_5V0_SYS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v8_ap: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_1V8_AP"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- vin-supply = <&vdd_1v8>; +- }; +- +- vdd_hdmi: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_5V0_HDMI_CON"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- thermal-zones { +- cpu { +- polling-delay = <0>; +- polling-delay-passive = <500>; +- status = "okay"; +- +- trips { +- cpu_trip_critical: critical { +- temperature = <96500>; +- hysteresis = <0>; +- type = "critical"; +- }; +- +- cpu_trip_hot: hot { +- temperature = <79000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- cpu_trip_active: active { +- temperature = <62000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- cpu_trip_passive: passive { +- temperature = <45000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- }; +- +- cooling-maps { +- cpu-critical { +- cooling-device = <&fan 3 3>; +- trip = <&cpu_trip_critical>; +- }; +- +- cpu-hot { +- cooling-device = <&fan 2 2>; +- trip = <&cpu_trip_hot>; +- }; +- +- cpu-active { +- cooling-device = <&fan 1 1>; +- trip = <&cpu_trip_active>; +- }; +- +- cpu-passive { +- cooling-device = <&fan 0 0>; +- trip = <&cpu_trip_passive>; +- }; +- }; +- }; +- +- gpu { +- polling-delay = <0>; +- polling-delay-passive = <500>; +- status = "okay"; +- +- trips { +- gpu_alert0: critical { +- temperature = <99000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- aux { +- polling-delay = <0>; +- polling-delay-passive = <500>; +- status = "okay"; +- +- trips { +- aux_alert0: critical { +- temperature = <90000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra186.dtsi b/scripts/dtc/include-prefixes/arm64/nvidia/tegra186.dtsi +deleted file mode 100644 +index 062e87e89331..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra186.dtsi ++++ /dev/null +@@ -1,1906 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "nvidia,tegra186"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- misc@100000 { +- compatible = "nvidia,tegra186-misc"; +- reg = <0x0 0x00100000 0x0 0xf000>, +- <0x0 0x0010f000 0x0 0x1000>; +- }; +- +- gpio: gpio@2200000 { +- compatible = "nvidia,tegra186-gpio"; +- reg-names = "security", "gpio"; +- reg = <0x0 0x2200000 0x0 0x10000>, +- <0x0 0x2210000 0x0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- ; +- #interrupt-cells = <2>; +- interrupt-controller; +- #gpio-cells = <2>; +- gpio-controller; +- }; +- +- ethernet@2490000 { +- compatible = "nvidia,tegra186-eqos", +- "snps,dwc-qos-ethernet-4.10"; +- reg = <0x0 0x02490000 0x0 0x10000>; +- interrupts = , /* common */ +- , /* power */ +- , /* rx0 */ +- , /* tx0 */ +- , /* rx1 */ +- , /* tx1 */ +- , /* rx2 */ +- , /* tx2 */ +- , /* rx3 */ +- ; /* tx3 */ +- clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, +- <&bpmp TEGRA186_CLK_EQOS_AXI>, +- <&bpmp TEGRA186_CLK_EQOS_RX>, +- <&bpmp TEGRA186_CLK_EQOS_TX>, +- <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; +- clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; +- resets = <&bpmp TEGRA186_RESET_EQOS>; +- reset-names = "eqos"; +- interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA186_SID_EQOS>; +- status = "disabled"; +- +- snps,write-requests = <1>; +- snps,read-requests = <3>; +- snps,burst-map = <0x7>; +- snps,txpbl = <32>; +- snps,rxpbl = <8>; +- }; +- +- aconnect@2900000 { +- compatible = "nvidia,tegra186-aconnect", +- "nvidia,tegra210-aconnect"; +- clocks = <&bpmp TEGRA186_CLK_APE>, +- <&bpmp TEGRA186_CLK_APB2APE>; +- clock-names = "ape", "apb2ape"; +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x02900000 0x0 0x02900000 0x200000>; +- status = "disabled"; +- +- adma: dma-controller@2930000 { +- compatible = "nvidia,tegra186-adma"; +- reg = <0x02930000 0x20000>; +- interrupt-parent = <&agic>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- #dma-cells = <1>; +- clocks = <&bpmp TEGRA186_CLK_AHUB>; +- clock-names = "d_audio"; +- status = "disabled"; +- }; +- +- agic: interrupt-controller@2a40000 { +- compatible = "nvidia,tegra186-agic", +- "nvidia,tegra210-agic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x02a41000 0x1000>, +- <0x02a42000 0x2000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_APE>; +- clock-names = "clk"; +- status = "disabled"; +- }; +- +- tegra_ahub: ahub@2900800 { +- compatible = "nvidia,tegra186-ahub"; +- reg = <0x02900800 0x800>; +- clocks = <&bpmp TEGRA186_CLK_AHUB>; +- clock-names = "ahub"; +- assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; +- assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x02900800 0x02900800 0x11800>; +- status = "disabled"; +- +- tegra_admaif: admaif@290f000 { +- compatible = "nvidia,tegra186-admaif"; +- reg = <0x0290f000 0x1000>; +- dmas = <&adma 1>, <&adma 1>, +- <&adma 2>, <&adma 2>, +- <&adma 3>, <&adma 3>, +- <&adma 4>, <&adma 4>, +- <&adma 5>, <&adma 5>, +- <&adma 6>, <&adma 6>, +- <&adma 7>, <&adma 7>, +- <&adma 8>, <&adma 8>, +- <&adma 9>, <&adma 9>, +- <&adma 10>, <&adma 10>, +- <&adma 11>, <&adma 11>, +- <&adma 12>, <&adma 12>, +- <&adma 13>, <&adma 13>, +- <&adma 14>, <&adma 14>, +- <&adma 15>, <&adma 15>, +- <&adma 16>, <&adma 16>, +- <&adma 17>, <&adma 17>, +- <&adma 18>, <&adma 18>, +- <&adma 19>, <&adma 19>, +- <&adma 20>, <&adma 20>; +- dma-names = "rx1", "tx1", +- "rx2", "tx2", +- "rx3", "tx3", +- "rx4", "tx4", +- "rx5", "tx5", +- "rx6", "tx6", +- "rx7", "tx7", +- "rx8", "tx8", +- "rx9", "tx9", +- "rx10", "tx10", +- "rx11", "tx11", +- "rx12", "tx12", +- "rx13", "tx13", +- "rx14", "tx14", +- "rx15", "tx15", +- "rx16", "tx16", +- "rx17", "tx17", +- "rx18", "tx18", +- "rx19", "tx19", +- "rx20", "tx20"; +- status = "disabled"; +- }; +- +- tegra_i2s1: i2s@2901000 { +- compatible = "nvidia,tegra186-i2s", +- "nvidia,tegra210-i2s"; +- reg = <0x2901000 0x100>; +- clocks = <&bpmp TEGRA186_CLK_I2S1>, +- <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; +- clock-names = "i2s", "sync_input"; +- assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; +- assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <1536000>; +- sound-name-prefix = "I2S1"; +- status = "disabled"; +- }; +- +- tegra_i2s2: i2s@2901100 { +- compatible = "nvidia,tegra186-i2s", +- "nvidia,tegra210-i2s"; +- reg = <0x2901100 0x100>; +- clocks = <&bpmp TEGRA186_CLK_I2S2>, +- <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; +- clock-names = "i2s", "sync_input"; +- assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; +- assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <1536000>; +- sound-name-prefix = "I2S2"; +- status = "disabled"; +- }; +- +- tegra_i2s3: i2s@2901200 { +- compatible = "nvidia,tegra186-i2s", +- "nvidia,tegra210-i2s"; +- reg = <0x2901200 0x100>; +- clocks = <&bpmp TEGRA186_CLK_I2S3>, +- <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; +- clock-names = "i2s", "sync_input"; +- assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; +- assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <1536000>; +- sound-name-prefix = "I2S3"; +- status = "disabled"; +- }; +- +- tegra_i2s4: i2s@2901300 { +- compatible = "nvidia,tegra186-i2s", +- "nvidia,tegra210-i2s"; +- reg = <0x2901300 0x100>; +- clocks = <&bpmp TEGRA186_CLK_I2S4>, +- <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; +- clock-names = "i2s", "sync_input"; +- assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; +- assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <1536000>; +- sound-name-prefix = "I2S4"; +- status = "disabled"; +- }; +- +- tegra_i2s5: i2s@2901400 { +- compatible = "nvidia,tegra186-i2s", +- "nvidia,tegra210-i2s"; +- reg = <0x2901400 0x100>; +- clocks = <&bpmp TEGRA186_CLK_I2S5>, +- <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; +- clock-names = "i2s", "sync_input"; +- assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; +- assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <1536000>; +- sound-name-prefix = "I2S5"; +- status = "disabled"; +- }; +- +- tegra_i2s6: i2s@2901500 { +- compatible = "nvidia,tegra186-i2s", +- "nvidia,tegra210-i2s"; +- reg = <0x2901500 0x100>; +- clocks = <&bpmp TEGRA186_CLK_I2S6>, +- <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; +- clock-names = "i2s", "sync_input"; +- assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; +- assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <1536000>; +- sound-name-prefix = "I2S6"; +- status = "disabled"; +- }; +- +- tegra_dmic1: dmic@2904000 { +- compatible = "nvidia,tegra210-dmic"; +- reg = <0x2904000 0x100>; +- clocks = <&bpmp TEGRA186_CLK_DMIC1>; +- clock-names = "dmic"; +- assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; +- assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <3072000>; +- sound-name-prefix = "DMIC1"; +- status = "disabled"; +- }; +- +- tegra_dmic2: dmic@2904100 { +- compatible = "nvidia,tegra210-dmic"; +- reg = <0x2904100 0x100>; +- clocks = <&bpmp TEGRA186_CLK_DMIC2>; +- clock-names = "dmic"; +- assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; +- assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <3072000>; +- sound-name-prefix = "DMIC2"; +- status = "disabled"; +- }; +- +- tegra_dmic3: dmic@2904200 { +- compatible = "nvidia,tegra210-dmic"; +- reg = <0x2904200 0x100>; +- clocks = <&bpmp TEGRA186_CLK_DMIC3>; +- clock-names = "dmic"; +- assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; +- assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <3072000>; +- sound-name-prefix = "DMIC3"; +- status = "disabled"; +- }; +- +- tegra_dmic4: dmic@2904300 { +- compatible = "nvidia,tegra210-dmic"; +- reg = <0x2904300 0x100>; +- clocks = <&bpmp TEGRA186_CLK_DMIC4>; +- clock-names = "dmic"; +- assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; +- assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <3072000>; +- sound-name-prefix = "DMIC4"; +- status = "disabled"; +- }; +- +- tegra_dspk1: dspk@2905000 { +- compatible = "nvidia,tegra186-dspk"; +- reg = <0x2905000 0x100>; +- clocks = <&bpmp TEGRA186_CLK_DSPK1>; +- clock-names = "dspk"; +- assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; +- assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <12288000>; +- sound-name-prefix = "DSPK1"; +- status = "disabled"; +- }; +- +- tegra_dspk2: dspk@2905100 { +- compatible = "nvidia,tegra186-dspk"; +- reg = <0x2905100 0x100>; +- clocks = <&bpmp TEGRA186_CLK_DSPK2>; +- clock-names = "dspk"; +- assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; +- assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <12288000>; +- sound-name-prefix = "DSPK2"; +- status = "disabled"; +- }; +- }; +- }; +- +- mc: memory-controller@2c00000 { +- compatible = "nvidia,tegra186-mc"; +- reg = <0x0 0x02c00000 0x0 0xb0000>; +- interrupts = ; +- status = "disabled"; +- +- #interconnect-cells = <1>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; +- +- /* +- * Memory clients have access to all 40 bits that the memory +- * controller can address. +- */ +- dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; +- +- emc: external-memory-controller@2c60000 { +- compatible = "nvidia,tegra186-emc"; +- reg = <0x0 0x02c60000 0x0 0x50000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_EMC>; +- clock-names = "emc"; +- +- #interconnect-cells = <0>; +- +- nvidia,bpmp = <&bpmp>; +- }; +- }; +- +- uarta: serial@3100000 { +- compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; +- reg = <0x0 0x03100000 0x0 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_UARTA>; +- clock-names = "serial"; +- resets = <&bpmp TEGRA186_RESET_UARTA>; +- reset-names = "serial"; +- status = "disabled"; +- }; +- +- uartb: serial@3110000 { +- compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; +- reg = <0x0 0x03110000 0x0 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_UARTB>; +- clock-names = "serial"; +- resets = <&bpmp TEGRA186_RESET_UARTB>; +- reset-names = "serial"; +- status = "disabled"; +- }; +- +- uartd: serial@3130000 { +- compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; +- reg = <0x0 0x03130000 0x0 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_UARTD>; +- clock-names = "serial"; +- resets = <&bpmp TEGRA186_RESET_UARTD>; +- reset-names = "serial"; +- status = "disabled"; +- }; +- +- uarte: serial@3140000 { +- compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; +- reg = <0x0 0x03140000 0x0 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_UARTE>; +- clock-names = "serial"; +- resets = <&bpmp TEGRA186_RESET_UARTE>; +- reset-names = "serial"; +- status = "disabled"; +- }; +- +- uartf: serial@3150000 { +- compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; +- reg = <0x0 0x03150000 0x0 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_UARTF>; +- clock-names = "serial"; +- resets = <&bpmp TEGRA186_RESET_UARTF>; +- reset-names = "serial"; +- status = "disabled"; +- }; +- +- gen1_i2c: i2c@3160000 { +- compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; +- reg = <0x0 0x03160000 0x0 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&bpmp TEGRA186_CLK_I2C1>; +- clock-names = "div-clk"; +- resets = <&bpmp TEGRA186_RESET_I2C1>; +- reset-names = "i2c"; +- status = "disabled"; +- }; +- +- cam_i2c: i2c@3180000 { +- compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; +- reg = <0x0 0x03180000 0x0 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&bpmp TEGRA186_CLK_I2C3>; +- clock-names = "div-clk"; +- resets = <&bpmp TEGRA186_RESET_I2C3>; +- reset-names = "i2c"; +- status = "disabled"; +- }; +- +- /* shares pads with dpaux1 */ +- dp_aux_ch1_i2c: i2c@3190000 { +- compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; +- reg = <0x0 0x03190000 0x0 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&bpmp TEGRA186_CLK_I2C4>; +- clock-names = "div-clk"; +- resets = <&bpmp TEGRA186_RESET_I2C4>; +- reset-names = "i2c"; +- pinctrl-names = "default", "idle"; +- pinctrl-0 = <&state_dpaux1_i2c>; +- pinctrl-1 = <&state_dpaux1_off>; +- status = "disabled"; +- }; +- +- /* controlled by BPMP, should not be enabled */ +- pwr_i2c: i2c@31a0000 { +- compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; +- reg = <0x0 0x031a0000 0x0 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&bpmp TEGRA186_CLK_I2C5>; +- clock-names = "div-clk"; +- resets = <&bpmp TEGRA186_RESET_I2C5>; +- reset-names = "i2c"; +- status = "disabled"; +- }; +- +- /* shares pads with dpaux0 */ +- dp_aux_ch0_i2c: i2c@31b0000 { +- compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; +- reg = <0x0 0x031b0000 0x0 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&bpmp TEGRA186_CLK_I2C6>; +- clock-names = "div-clk"; +- resets = <&bpmp TEGRA186_RESET_I2C6>; +- reset-names = "i2c"; +- pinctrl-names = "default", "idle"; +- pinctrl-0 = <&state_dpaux_i2c>; +- pinctrl-1 = <&state_dpaux_off>; +- status = "disabled"; +- }; +- +- gen7_i2c: i2c@31c0000 { +- compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; +- reg = <0x0 0x031c0000 0x0 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&bpmp TEGRA186_CLK_I2C7>; +- clock-names = "div-clk"; +- resets = <&bpmp TEGRA186_RESET_I2C7>; +- reset-names = "i2c"; +- status = "disabled"; +- }; +- +- gen9_i2c: i2c@31e0000 { +- compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; +- reg = <0x0 0x031e0000 0x0 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&bpmp TEGRA186_CLK_I2C9>; +- clock-names = "div-clk"; +- resets = <&bpmp TEGRA186_RESET_I2C9>; +- reset-names = "i2c"; +- status = "disabled"; +- }; +- +- pwm1: pwm@3280000 { +- compatible = "nvidia,tegra186-pwm"; +- reg = <0x0 0x3280000 0x0 0x10000>; +- clocks = <&bpmp TEGRA186_CLK_PWM1>; +- clock-names = "pwm"; +- resets = <&bpmp TEGRA186_RESET_PWM1>; +- reset-names = "pwm"; +- status = "disabled"; +- #pwm-cells = <2>; +- }; +- +- pwm2: pwm@3290000 { +- compatible = "nvidia,tegra186-pwm"; +- reg = <0x0 0x3290000 0x0 0x10000>; +- clocks = <&bpmp TEGRA186_CLK_PWM2>; +- clock-names = "pwm"; +- resets = <&bpmp TEGRA186_RESET_PWM2>; +- reset-names = "pwm"; +- status = "disabled"; +- #pwm-cells = <2>; +- }; +- +- pwm3: pwm@32a0000 { +- compatible = "nvidia,tegra186-pwm"; +- reg = <0x0 0x32a0000 0x0 0x10000>; +- clocks = <&bpmp TEGRA186_CLK_PWM3>; +- clock-names = "pwm"; +- resets = <&bpmp TEGRA186_RESET_PWM3>; +- reset-names = "pwm"; +- status = "disabled"; +- #pwm-cells = <2>; +- }; +- +- pwm5: pwm@32c0000 { +- compatible = "nvidia,tegra186-pwm"; +- reg = <0x0 0x32c0000 0x0 0x10000>; +- clocks = <&bpmp TEGRA186_CLK_PWM5>; +- clock-names = "pwm"; +- resets = <&bpmp TEGRA186_RESET_PWM5>; +- reset-names = "pwm"; +- status = "disabled"; +- #pwm-cells = <2>; +- }; +- +- pwm6: pwm@32d0000 { +- compatible = "nvidia,tegra186-pwm"; +- reg = <0x0 0x32d0000 0x0 0x10000>; +- clocks = <&bpmp TEGRA186_CLK_PWM6>; +- clock-names = "pwm"; +- resets = <&bpmp TEGRA186_RESET_PWM6>; +- reset-names = "pwm"; +- status = "disabled"; +- #pwm-cells = <2>; +- }; +- +- pwm7: pwm@32e0000 { +- compatible = "nvidia,tegra186-pwm"; +- reg = <0x0 0x32e0000 0x0 0x10000>; +- clocks = <&bpmp TEGRA186_CLK_PWM7>; +- clock-names = "pwm"; +- resets = <&bpmp TEGRA186_RESET_PWM7>; +- reset-names = "pwm"; +- status = "disabled"; +- #pwm-cells = <2>; +- }; +- +- pwm8: pwm@32f0000 { +- compatible = "nvidia,tegra186-pwm"; +- reg = <0x0 0x32f0000 0x0 0x10000>; +- clocks = <&bpmp TEGRA186_CLK_PWM8>; +- clock-names = "pwm"; +- resets = <&bpmp TEGRA186_RESET_PWM8>; +- reset-names = "pwm"; +- status = "disabled"; +- #pwm-cells = <2>; +- }; +- +- sdmmc1: mmc@3400000 { +- compatible = "nvidia,tegra186-sdhci"; +- reg = <0x0 0x03400000 0x0 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_SDMMC1>, +- <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; +- clock-names = "sdhci", "tmclk"; +- resets = <&bpmp TEGRA186_RESET_SDMMC1>; +- reset-names = "sdhci"; +- interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA186_SID_SDMMC1>; +- pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; +- pinctrl-0 = <&sdmmc1_3v3>; +- pinctrl-1 = <&sdmmc1_1v8>; +- nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; +- nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; +- nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; +- nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; +- nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; +- nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; +- nvidia,default-tap = <0x5>; +- nvidia,default-trim = <0xb>; +- assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, +- <&bpmp TEGRA186_CLK_PLLP_OUT0>; +- assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; +- status = "disabled"; +- }; +- +- sdmmc2: mmc@3420000 { +- compatible = "nvidia,tegra186-sdhci"; +- reg = <0x0 0x03420000 0x0 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_SDMMC2>, +- <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; +- clock-names = "sdhci", "tmclk"; +- resets = <&bpmp TEGRA186_RESET_SDMMC2>; +- reset-names = "sdhci"; +- interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA186_SID_SDMMC2>; +- pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; +- pinctrl-0 = <&sdmmc2_3v3>; +- pinctrl-1 = <&sdmmc2_1v8>; +- nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; +- nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; +- nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; +- nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; +- nvidia,default-tap = <0x5>; +- nvidia,default-trim = <0xb>; +- status = "disabled"; +- }; +- +- sdmmc3: mmc@3440000 { +- compatible = "nvidia,tegra186-sdhci"; +- reg = <0x0 0x03440000 0x0 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_SDMMC3>, +- <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; +- clock-names = "sdhci", "tmclk"; +- resets = <&bpmp TEGRA186_RESET_SDMMC3>; +- reset-names = "sdhci"; +- interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA186_SID_SDMMC3>; +- pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; +- pinctrl-0 = <&sdmmc3_3v3>; +- pinctrl-1 = <&sdmmc3_1v8>; +- nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; +- nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; +- nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; +- nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; +- nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; +- nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; +- nvidia,default-tap = <0x5>; +- nvidia,default-trim = <0xb>; +- status = "disabled"; +- }; +- +- sdmmc4: mmc@3460000 { +- compatible = "nvidia,tegra186-sdhci"; +- reg = <0x0 0x03460000 0x0 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_SDMMC4>, +- <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; +- clock-names = "sdhci", "tmclk"; +- assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, +- <&bpmp TEGRA186_CLK_PLLC4_VCO>; +- assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; +- resets = <&bpmp TEGRA186_RESET_SDMMC4>; +- reset-names = "sdhci"; +- interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA186_SID_SDMMC4>; +- nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; +- nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; +- nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; +- nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; +- nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; +- nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; +- nvidia,default-tap = <0x9>; +- nvidia,default-trim = <0x5>; +- nvidia,dqs-trim = <63>; +- mmc-hs400-1_8v; +- supports-cqe; +- status = "disabled"; +- }; +- +- hda@3510000 { +- compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; +- reg = <0x0 0x03510000 0x0 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_HDA>, +- <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, +- <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; +- clock-names = "hda", "hda2hdmi", "hda2codec_2x"; +- resets = <&bpmp TEGRA186_RESET_HDA>, +- <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, +- <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; +- reset-names = "hda", "hda2hdmi", "hda2codec_2x"; +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; +- interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA186_SID_HDA>; +- status = "disabled"; +- }; +- +- padctl: padctl@3520000 { +- compatible = "nvidia,tegra186-xusb-padctl"; +- reg = <0x0 0x03520000 0x0 0x1000>, +- <0x0 0x03540000 0x0 0x1000>; +- reg-names = "padctl", "ao"; +- interrupts = ; +- +- resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; +- reset-names = "padctl"; +- +- status = "disabled"; +- +- pads { +- usb2 { +- clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; +- clock-names = "trk"; +- status = "disabled"; +- +- lanes { +- usb2-0 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- usb2-1 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- usb2-2 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- hsic { +- clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; +- clock-names = "trk"; +- status = "disabled"; +- +- lanes { +- hsic-0 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- usb3 { +- status = "disabled"; +- +- lanes { +- usb3-0 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- usb3-1 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- usb3-2 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- }; +- }; +- +- ports { +- usb2-0 { +- status = "disabled"; +- }; +- +- usb2-1 { +- status = "disabled"; +- }; +- +- usb2-2 { +- status = "disabled"; +- }; +- +- hsic-0 { +- status = "disabled"; +- }; +- +- usb3-0 { +- status = "disabled"; +- }; +- +- usb3-1 { +- status = "disabled"; +- }; +- +- usb3-2 { +- status = "disabled"; +- }; +- }; +- }; +- +- usb@3530000 { +- compatible = "nvidia,tegra186-xusb"; +- reg = <0x0 0x03530000 0x0 0x8000>, +- <0x0 0x03538000 0x0 0x1000>; +- reg-names = "hcd", "fpci"; +- interrupts = , +- ; +- clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, +- <&bpmp TEGRA186_CLK_XUSB_FALCON>, +- <&bpmp TEGRA186_CLK_XUSB_SS>, +- <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, +- <&bpmp TEGRA186_CLK_CLK_M>, +- <&bpmp TEGRA186_CLK_XUSB_FS>, +- <&bpmp TEGRA186_CLK_PLLU>, +- <&bpmp TEGRA186_CLK_CLK_M>, +- <&bpmp TEGRA186_CLK_PLLE>; +- clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", +- "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", +- "pll_u_480m", "clk_m", "pll_e"; +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, +- <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; +- power-domain-names = "xusb_host", "xusb_ss"; +- interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA186_SID_XUSB_HOST>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- nvidia,xusb-padctl = <&padctl>; +- }; +- +- usb@3550000 { +- compatible = "nvidia,tegra186-xudc"; +- reg = <0x0 0x03550000 0x0 0x8000>, +- <0x0 0x03558000 0x0 0x1000>; +- reg-names = "base", "fpci"; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, +- <&bpmp TEGRA186_CLK_XUSB_SS>, +- <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, +- <&bpmp TEGRA186_CLK_XUSB_FS>; +- clock-names = "dev", "ss", "ss_src", "fs_src"; +- interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA186_SID_XUSB_DEV>; +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, +- <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; +- power-domain-names = "dev", "ss"; +- nvidia,xusb-padctl = <&padctl>; +- status = "disabled"; +- }; +- +- fuse@3820000 { +- compatible = "nvidia,tegra186-efuse"; +- reg = <0x0 0x03820000 0x0 0x10000>; +- clocks = <&bpmp TEGRA186_CLK_FUSE>; +- clock-names = "fuse"; +- }; +- +- gic: interrupt-controller@3881000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x0 0x03881000 0x0 0x1000>, +- <0x0 0x03882000 0x0 0x2000>, +- <0x0 0x03884000 0x0 0x2000>, +- <0x0 0x03886000 0x0 0x2000>; +- interrupts = ; +- interrupt-parent = <&gic>; +- }; +- +- cec@3960000 { +- compatible = "nvidia,tegra186-cec"; +- reg = <0x0 0x03960000 0x0 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_CEC>; +- clock-names = "cec"; +- status = "disabled"; +- }; +- +- hsp_top0: hsp@3c00000 { +- compatible = "nvidia,tegra186-hsp"; +- reg = <0x0 0x03c00000 0x0 0xa0000>; +- interrupts = ; +- interrupt-names = "doorbell"; +- #mbox-cells = <2>; +- status = "disabled"; +- }; +- +- gen2_i2c: i2c@c240000 { +- compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; +- reg = <0x0 0x0c240000 0x0 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&bpmp TEGRA186_CLK_I2C2>; +- clock-names = "div-clk"; +- resets = <&bpmp TEGRA186_RESET_I2C2>; +- reset-names = "i2c"; +- status = "disabled"; +- }; +- +- gen8_i2c: i2c@c250000 { +- compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; +- reg = <0x0 0x0c250000 0x0 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&bpmp TEGRA186_CLK_I2C8>; +- clock-names = "div-clk"; +- resets = <&bpmp TEGRA186_RESET_I2C8>; +- reset-names = "i2c"; +- status = "disabled"; +- }; +- +- uartc: serial@c280000 { +- compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; +- reg = <0x0 0x0c280000 0x0 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_UARTC>; +- clock-names = "serial"; +- resets = <&bpmp TEGRA186_RESET_UARTC>; +- reset-names = "serial"; +- status = "disabled"; +- }; +- +- uartg: serial@c290000 { +- compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; +- reg = <0x0 0x0c290000 0x0 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_UARTG>; +- clock-names = "serial"; +- resets = <&bpmp TEGRA186_RESET_UARTG>; +- reset-names = "serial"; +- status = "disabled"; +- }; +- +- rtc: rtc@c2a0000 { +- compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; +- reg = <0 0x0c2a0000 0 0x10000>; +- interrupt-parent = <&pmc>; +- interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&bpmp TEGRA186_CLK_CLK_32K>; +- clock-names = "rtc"; +- status = "disabled"; +- }; +- +- gpio_aon: gpio@c2f0000 { +- compatible = "nvidia,tegra186-gpio-aon"; +- reg-names = "security", "gpio"; +- reg = <0x0 0xc2f0000 0x0 0x1000>, +- <0x0 0xc2f1000 0x0 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pwm4: pwm@c340000 { +- compatible = "nvidia,tegra186-pwm"; +- reg = <0x0 0xc340000 0x0 0x10000>; +- clocks = <&bpmp TEGRA186_CLK_PWM4>; +- clock-names = "pwm"; +- resets = <&bpmp TEGRA186_RESET_PWM4>; +- reset-names = "pwm"; +- status = "disabled"; +- #pwm-cells = <2>; +- }; +- +- pmc: pmc@c360000 { +- compatible = "nvidia,tegra186-pmc"; +- reg = <0 0x0c360000 0 0x10000>, +- <0 0x0c370000 0 0x10000>, +- <0 0x0c380000 0 0x10000>, +- <0 0x0c390000 0 0x10000>; +- reg-names = "pmc", "wake", "aotag", "scratch"; +- +- #interrupt-cells = <2>; +- interrupt-controller; +- +- sdmmc1_3v3: sdmmc1-3v3 { +- pins = "sdmmc1-hv"; +- power-source = ; +- }; +- +- sdmmc1_1v8: sdmmc1-1v8 { +- pins = "sdmmc1-hv"; +- power-source = ; +- }; +- +- sdmmc2_3v3: sdmmc2-3v3 { +- pins = "sdmmc2-hv"; +- power-source = ; +- }; +- +- sdmmc2_1v8: sdmmc2-1v8 { +- pins = "sdmmc2-hv"; +- power-source = ; +- }; +- +- sdmmc3_3v3: sdmmc3-3v3 { +- pins = "sdmmc3-hv"; +- power-source = ; +- }; +- +- sdmmc3_1v8: sdmmc3-1v8 { +- pins = "sdmmc3-hv"; +- power-source = ; +- }; +- }; +- +- ccplex@e000000 { +- compatible = "nvidia,tegra186-ccplex-cluster"; +- reg = <0x0 0x0e000000 0x0 0x400000>; +- +- nvidia,bpmp = <&bpmp>; +- }; +- +- pcie@10003000 { +- compatible = "nvidia,tegra186-pcie"; +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; +- device_type = "pci"; +- reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ +- <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ +- <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ +- reg-names = "pads", "afi", "cs"; +- +- interrupts = , /* controller interrupt */ +- ; /* MSI interrupt */ +- interrupt-names = "intr", "msi"; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; +- +- bus-range = <0x00 0xff>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ +- <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ +- <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ +- <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ +- <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ +- <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ +- +- clocks = <&bpmp TEGRA186_CLK_PCIE>, +- <&bpmp TEGRA186_CLK_AFI>, +- <&bpmp TEGRA186_CLK_PLLE>; +- clock-names = "pex", "afi", "pll_e"; +- +- resets = <&bpmp TEGRA186_RESET_PCIE>, +- <&bpmp TEGRA186_RESET_AFI>, +- <&bpmp TEGRA186_RESET_PCIEXCLK>; +- reset-names = "pex", "afi", "pcie_x"; +- +- interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; +- interconnect-names = "dma-mem", "write"; +- +- iommus = <&smmu TEGRA186_SID_AFI>; +- iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; +- iommu-map-mask = <0x0>; +- +- status = "disabled"; +- +- pci@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; +- reg = <0x000800 0 0 0 0>; +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- ranges; +- +- nvidia,num-lanes = <2>; +- }; +- +- pci@2,0 { +- device_type = "pci"; +- assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; +- reg = <0x001000 0 0 0 0>; +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- ranges; +- +- nvidia,num-lanes = <1>; +- }; +- +- pci@3,0 { +- device_type = "pci"; +- assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; +- reg = <0x001800 0 0 0 0>; +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- ranges; +- +- nvidia,num-lanes = <1>; +- }; +- }; +- +- smmu: iommu@12000000 { +- compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; +- reg = <0 0x12000000 0 0x800000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- stream-match-mask = <0x7f80>; +- #global-interrupts = <1>; +- #iommu-cells = <1>; +- +- nvidia,memory-controller = <&mc>; +- }; +- +- host1x@13e00000 { +- compatible = "nvidia,tegra186-host1x"; +- reg = <0x0 0x13e00000 0x0 0x10000>, +- <0x0 0x13e10000 0x0 0x10000>; +- reg-names = "hypervisor", "vm"; +- interrupts = , +- ; +- interrupt-names = "syncpt", "host1x"; +- clocks = <&bpmp TEGRA186_CLK_HOST1X>; +- clock-names = "host1x"; +- resets = <&bpmp TEGRA186_RESET_HOST1X>; +- reset-names = "host1x"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0x15000000 0x0 0x15000000 0x01000000>; +- +- interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; +- interconnect-names = "dma-mem"; +- +- iommus = <&smmu TEGRA186_SID_HOST1X>; +- +- dpaux1: dpaux@15040000 { +- compatible = "nvidia,tegra186-dpaux"; +- reg = <0x15040000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_DPAUX1>, +- <&bpmp TEGRA186_CLK_PLLDP>; +- clock-names = "dpaux", "parent"; +- resets = <&bpmp TEGRA186_RESET_DPAUX1>; +- reset-names = "dpaux"; +- status = "disabled"; +- +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; +- +- state_dpaux1_aux: pinmux-aux { +- groups = "dpaux-io"; +- function = "aux"; +- }; +- +- state_dpaux1_i2c: pinmux-i2c { +- groups = "dpaux-io"; +- function = "i2c"; +- }; +- +- state_dpaux1_off: pinmux-off { +- groups = "dpaux-io"; +- function = "off"; +- }; +- +- i2c-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- display-hub@15200000 { +- compatible = "nvidia,tegra186-display"; +- reg = <0x15200000 0x00040000>; +- resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, +- <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, +- <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, +- <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, +- <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, +- <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, +- <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; +- reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", +- "wgrp3", "wgrp4", "wgrp5"; +- clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, +- <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, +- <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; +- clock-names = "disp", "dsc", "hub"; +- status = "disabled"; +- +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0x15200000 0x15200000 0x40000>; +- +- display@15200000 { +- compatible = "nvidia,tegra186-dc"; +- reg = <0x15200000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; +- clock-names = "dc"; +- resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; +- reset-names = "dc"; +- +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; +- interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; +- interconnect-names = "dma-mem", "read-1"; +- iommus = <&smmu TEGRA186_SID_NVDISPLAY>; +- +- nvidia,outputs = <&dsia &dsib &sor0 &sor1>; +- nvidia,head = <0>; +- }; +- +- display@15210000 { +- compatible = "nvidia,tegra186-dc"; +- reg = <0x15210000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; +- clock-names = "dc"; +- resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; +- reset-names = "dc"; +- +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; +- interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; +- interconnect-names = "dma-mem", "read-1"; +- iommus = <&smmu TEGRA186_SID_NVDISPLAY>; +- +- nvidia,outputs = <&dsia &dsib &sor0 &sor1>; +- nvidia,head = <1>; +- }; +- +- display@15220000 { +- compatible = "nvidia,tegra186-dc"; +- reg = <0x15220000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; +- clock-names = "dc"; +- resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; +- reset-names = "dc"; +- +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; +- interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; +- interconnect-names = "dma-mem", "read-1"; +- iommus = <&smmu TEGRA186_SID_NVDISPLAY>; +- +- nvidia,outputs = <&sor0 &sor1>; +- nvidia,head = <2>; +- }; +- }; +- +- dsia: dsi@15300000 { +- compatible = "nvidia,tegra186-dsi"; +- reg = <0x15300000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_DSI>, +- <&bpmp TEGRA186_CLK_DSIA_LP>, +- <&bpmp TEGRA186_CLK_PLLD>; +- clock-names = "dsi", "lp", "parent"; +- resets = <&bpmp TEGRA186_RESET_DSI>; +- reset-names = "dsi"; +- status = "disabled"; +- +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; +- }; +- +- vic@15340000 { +- compatible = "nvidia,tegra186-vic"; +- reg = <0x15340000 0x40000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_VIC>; +- clock-names = "vic"; +- resets = <&bpmp TEGRA186_RESET_VIC>; +- reset-names = "vic"; +- +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; +- interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA186_SID_VIC>; +- }; +- +- dsib: dsi@15400000 { +- compatible = "nvidia,tegra186-dsi"; +- reg = <0x15400000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_DSIB>, +- <&bpmp TEGRA186_CLK_DSIB_LP>, +- <&bpmp TEGRA186_CLK_PLLD>; +- clock-names = "dsi", "lp", "parent"; +- resets = <&bpmp TEGRA186_RESET_DSIB>; +- reset-names = "dsi"; +- status = "disabled"; +- +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; +- }; +- +- sor0: sor@15540000 { +- compatible = "nvidia,tegra186-sor"; +- reg = <0x15540000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_SOR0>, +- <&bpmp TEGRA186_CLK_SOR0_OUT>, +- <&bpmp TEGRA186_CLK_PLLD2>, +- <&bpmp TEGRA186_CLK_PLLDP>, +- <&bpmp TEGRA186_CLK_SOR_SAFE>, +- <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; +- clock-names = "sor", "out", "parent", "dp", "safe", +- "pad"; +- resets = <&bpmp TEGRA186_RESET_SOR0>; +- reset-names = "sor"; +- pinctrl-0 = <&state_dpaux_aux>; +- pinctrl-1 = <&state_dpaux_i2c>; +- pinctrl-2 = <&state_dpaux_off>; +- pinctrl-names = "aux", "i2c", "off"; +- status = "disabled"; +- +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; +- nvidia,interface = <0>; +- }; +- +- sor1: sor@15580000 { +- compatible = "nvidia,tegra186-sor"; +- reg = <0x15580000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_SOR1>, +- <&bpmp TEGRA186_CLK_SOR1_OUT>, +- <&bpmp TEGRA186_CLK_PLLD3>, +- <&bpmp TEGRA186_CLK_PLLDP>, +- <&bpmp TEGRA186_CLK_SOR_SAFE>, +- <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; +- clock-names = "sor", "out", "parent", "dp", "safe", +- "pad"; +- resets = <&bpmp TEGRA186_RESET_SOR1>; +- reset-names = "sor"; +- pinctrl-0 = <&state_dpaux1_aux>; +- pinctrl-1 = <&state_dpaux1_i2c>; +- pinctrl-2 = <&state_dpaux1_off>; +- pinctrl-names = "aux", "i2c", "off"; +- status = "disabled"; +- +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; +- nvidia,interface = <1>; +- }; +- +- dpaux: dpaux@155c0000 { +- compatible = "nvidia,tegra186-dpaux"; +- reg = <0x155c0000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_DPAUX>, +- <&bpmp TEGRA186_CLK_PLLDP>; +- clock-names = "dpaux", "parent"; +- resets = <&bpmp TEGRA186_RESET_DPAUX>; +- reset-names = "dpaux"; +- status = "disabled"; +- +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; +- +- state_dpaux_aux: pinmux-aux { +- groups = "dpaux-io"; +- function = "aux"; +- }; +- +- state_dpaux_i2c: pinmux-i2c { +- groups = "dpaux-io"; +- function = "i2c"; +- }; +- +- state_dpaux_off: pinmux-off { +- groups = "dpaux-io"; +- function = "off"; +- }; +- +- i2c-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- padctl@15880000 { +- compatible = "nvidia,tegra186-dsi-padctl"; +- reg = <0x15880000 0x10000>; +- resets = <&bpmp TEGRA186_RESET_DSI>; +- reset-names = "dsi"; +- status = "disabled"; +- }; +- +- dsic: dsi@15900000 { +- compatible = "nvidia,tegra186-dsi"; +- reg = <0x15900000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_DSIC>, +- <&bpmp TEGRA186_CLK_DSIC_LP>, +- <&bpmp TEGRA186_CLK_PLLD>; +- clock-names = "dsi", "lp", "parent"; +- resets = <&bpmp TEGRA186_RESET_DSIC>; +- reset-names = "dsi"; +- status = "disabled"; +- +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; +- }; +- +- dsid: dsi@15940000 { +- compatible = "nvidia,tegra186-dsi"; +- reg = <0x15940000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA186_CLK_DSID>, +- <&bpmp TEGRA186_CLK_DSID_LP>, +- <&bpmp TEGRA186_CLK_PLLD>; +- clock-names = "dsi", "lp", "parent"; +- resets = <&bpmp TEGRA186_RESET_DSID>; +- reset-names = "dsi"; +- status = "disabled"; +- +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; +- }; +- }; +- +- gpu@17000000 { +- compatible = "nvidia,gp10b"; +- reg = <0x0 0x17000000 0x0 0x1000000>, +- <0x0 0x18000000 0x0 0x1000000>; +- interrupts = , +- ; +- interrupt-names = "stall", "nonstall"; +- +- clocks = <&bpmp TEGRA186_CLK_GPCCLK>, +- <&bpmp TEGRA186_CLK_GPU>; +- clock-names = "gpu", "pwr"; +- resets = <&bpmp TEGRA186_RESET_GPU>; +- reset-names = "gpu"; +- status = "disabled"; +- +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; +- interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; +- interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; +- }; +- +- sram@30000000 { +- compatible = "nvidia,tegra186-sysram", "mmio-sram"; +- reg = <0x0 0x30000000 0x0 0x50000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x30000000 0x50000>; +- +- cpu_bpmp_tx: sram@4e000 { +- reg = <0x4e000 0x1000>; +- label = "cpu-bpmp-tx"; +- pool; +- }; +- +- cpu_bpmp_rx: sram@4f000 { +- reg = <0x4f000 0x1000>; +- label = "cpu-bpmp-rx"; +- pool; +- }; +- }; +- +- sata@3507000 { +- compatible = "nvidia,tegra186-ahci"; +- reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ +- <0x0 0x03500000 0x0 0x00007000>, /* SATA */ +- <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ +- interrupts = ; +- +- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; +- interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA186_SID_SATA>; +- +- clocks = <&bpmp TEGRA186_CLK_SATA>, +- <&bpmp TEGRA186_CLK_SATA_OOB>; +- clock-names = "sata", "sata-oob"; +- assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, +- <&bpmp TEGRA186_CLK_SATA_OOB>; +- assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, +- <&bpmp TEGRA186_CLK_PLLP>; +- assigned-clock-rates = <102000000>, +- <204000000>; +- resets = <&bpmp TEGRA186_RESET_SATA>, +- <&bpmp TEGRA186_RESET_SATACOLD>; +- reset-names = "sata", "sata-cold"; +- status = "disabled"; +- }; +- +- bpmp: bpmp { +- compatible = "nvidia,tegra186-bpmp"; +- interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, +- <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; +- interconnect-names = "read", "write", "dma-mem", "dma-write"; +- iommus = <&smmu TEGRA186_SID_BPMP>; +- mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB +- TEGRA_HSP_DB_MASTER_BPMP>; +- shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- +- bpmp_i2c: i2c { +- compatible = "nvidia,tegra186-bpmp-i2c"; +- nvidia,bpmp-bus-id = <5>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- bpmp_thermal: thermal { +- compatible = "nvidia,tegra186-bpmp-thermal"; +- #thermal-sensor-cells = <1>; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- denver_0: cpu@0 { +- compatible = "nvidia,tegra186-denver"; +- device_type = "cpu"; +- i-cache-size = <0x20000>; +- i-cache-line-size = <64>; +- i-cache-sets = <512>; +- d-cache-size = <0x10000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&L2_DENVER>; +- reg = <0x000>; +- }; +- +- denver_1: cpu@1 { +- compatible = "nvidia,tegra186-denver"; +- device_type = "cpu"; +- i-cache-size = <0x20000>; +- i-cache-line-size = <64>; +- i-cache-sets = <512>; +- d-cache-size = <0x10000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&L2_DENVER>; +- reg = <0x001>; +- }; +- +- ca57_0: cpu@2 { +- compatible = "arm,cortex-a57"; +- device_type = "cpu"; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&L2_A57>; +- reg = <0x100>; +- }; +- +- ca57_1: cpu@3 { +- compatible = "arm,cortex-a57"; +- device_type = "cpu"; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&L2_A57>; +- reg = <0x101>; +- }; +- +- ca57_2: cpu@4 { +- compatible = "arm,cortex-a57"; +- device_type = "cpu"; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&L2_A57>; +- reg = <0x102>; +- }; +- +- ca57_3: cpu@5 { +- compatible = "arm,cortex-a57"; +- device_type = "cpu"; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&L2_A57>; +- reg = <0x103>; +- }; +- +- L2_DENVER: l2-cache0 { +- compatible = "cache"; +- cache-unified; +- cache-level = <2>; +- cache-size = <0x200000>; +- cache-line-size = <64>; +- cache-sets = <2048>; +- }; +- +- L2_A57: l2-cache1 { +- compatible = "cache"; +- cache-unified; +- cache-level = <2>; +- cache-size = <0x200000>; +- cache-line-size = <64>; +- cache-sets = <2048>; +- }; +- }; +- +- pmu_denver { +- compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3"; +- interrupts = , +- ; +- interrupt-affinity = <&denver_0 &denver_1>; +- }; +- +- pmu_a57 { +- compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; +- }; +- +- sound { +- status = "disabled"; +- +- clocks = <&bpmp TEGRA186_CLK_PLLA>, +- <&bpmp TEGRA186_CLK_PLL_A_OUT0>; +- clock-names = "pll_a", "plla_out0"; +- assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, +- <&bpmp TEGRA186_CLK_PLL_A_OUT0>, +- <&bpmp TEGRA186_CLK_AUD_MCLK>; +- assigned-clock-parents = <0>, +- <&bpmp TEGRA186_CLK_PLLA>, +- <&bpmp TEGRA186_CLK_PLL_A_OUT0>; +- /* +- * PLLA supports dynamic ramp. Below initial rate is chosen +- * for this to work and oscillate between base rates required +- * for 8x and 11.025x sample rate streams. +- */ +- assigned-clock-rates = <258000000>; +- +- iommus = <&smmu TEGRA186_SID_APE>; +- }; +- +- thermal-zones { +- a57 { +- polling-delay = <0>; +- polling-delay-passive = <1000>; +- +- thermal-sensors = +- <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; +- +- trips { +- critical { +- temperature = <101000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- }; +- }; +- +- denver { +- polling-delay = <0>; +- polling-delay-passive = <1000>; +- +- thermal-sensors = +- <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; +- +- trips { +- critical { +- temperature = <101000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- }; +- }; +- +- gpu { +- polling-delay = <0>; +- polling-delay-passive = <1000>; +- +- thermal-sensors = +- <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; +- +- trips { +- critical { +- temperature = <101000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- }; +- }; +- +- pll { +- polling-delay = <0>; +- polling-delay-passive = <1000>; +- +- thermal-sensors = +- <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; +- +- trips { +- critical { +- temperature = <101000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- }; +- }; +- +- always_on { +- polling-delay = <0>; +- polling-delay-passive = <1000>; +- +- thermal-sensors = +- <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; +- +- trips { +- critical { +- temperature = <101000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- interrupt-parent = <&gic>; +- always-on; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p2888.dtsi b/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p2888.dtsi +deleted file mode 100644 +index c4058ee36fec..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p2888.dtsi ++++ /dev/null +@@ -1,365 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "tegra194.dtsi" +- +-#include +- +-/ { +- model = "NVIDIA Jetson AGX Xavier"; +- compatible = "nvidia,p2888", "nvidia,tegra194"; +- +- aliases { +- ethernet0 = "/bus@0/ethernet@2490000"; +- i2c0 = "/bpmp/i2c"; +- i2c1 = "/bus@0/i2c@3160000"; +- i2c2 = "/bus@0/i2c@c240000"; +- i2c3 = "/bus@0/i2c@3180000"; +- i2c4 = "/bus@0/i2c@3190000"; +- i2c5 = "/bus@0/i2c@31c0000"; +- i2c6 = "/bus@0/i2c@c250000"; +- i2c7 = "/bus@0/i2c@31e0000"; +- mmc0 = "/bus@0/mmc@3460000"; +- mmc1 = "/bus@0/mmc@3400000"; +- serial0 = &tcu; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = "serial0:115200n8"; +- }; +- +- bus@0 { +- ethernet@2490000 { +- status = "okay"; +- +- phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>; +- phy-handle = <&phy>; +- phy-mode = "rgmii-id"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy: phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0x0>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- memory-controller@2c00000 { +- status = "okay"; +- }; +- +- serial@3110000 { +- status = "okay"; +- }; +- +- i2c@3160000 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- +- label = "module"; +- vcc-supply = <&vdd_1v8ls>; +- address-width = <8>; +- pagesize = <8>; +- size = <256>; +- read-only; +- }; +- }; +- +- /* SDMMC1 (SD/MMC) */ +- mmc@3400000 { +- cd-gpios = <&gpio TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_LOW>; +- }; +- +- /* SDMMC4 (eMMC) */ +- mmc@3460000 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- +- vqmmc-supply = <&vdd_1v8ls>; +- vmmc-supply = <&vdd_emmc_3v3>; +- }; +- +- padctl@3520000 { +- avdd-usb-supply = <&vdd_usb_3v3>; +- vclamp-usb-supply = <&vdd_1v8ao>; +- +- ports { +- usb2-0 { +- vbus-supply = <&vdd_5v0_sys>; +- }; +- +- usb2-1 { +- vbus-supply = <&vdd_5v0_sys>; +- }; +- +- usb2-3 { +- vbus-supply = <&vdd_5v_sata>; +- }; +- +- usb3-0 { +- vbus-supply = <&vdd_5v0_sys>; +- }; +- +- usb3-2 { +- vbus-supply = <&vdd_5v0_sys>; +- }; +- +- usb3-3 { +- vbus-supply = <&vdd_5v0_sys>; +- }; +- }; +- }; +- +- rtc@c2a0000 { +- status = "okay"; +- }; +- +- pmc@c360000 { +- nvidia,invert-interrupt; +- }; +- }; +- +- bpmp { +- i2c { +- status = "okay"; +- +- pmic: pmic@3c { +- compatible = "maxim,max20024"; +- reg = <0x3c>; +- +- interrupt-parent = <&pmc>; +- interrupts = <24 IRQ_TYPE_LEVEL_LOW>; +- #interrupt-cells = <2>; +- interrupt-controller; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&max20024_default>; +- +- max20024_default: pinmux { +- gpio0 { +- pins = "gpio0"; +- function = "gpio"; +- }; +- +- gpio1 { +- pins = "gpio1"; +- function = "fps-out"; +- maxim,active-fps-source = ; +- }; +- +- gpio2 { +- pins = "gpio2"; +- function = "fps-out"; +- maxim,active-fps-source = ; +- }; +- +- gpio3 { +- pins = "gpio3"; +- function = "fps-out"; +- maxim,active-fps-source = ; +- }; +- +- gpio4 { +- pins = "gpio4"; +- function = "32k-out1"; +- drive-push-pull = <1>; +- }; +- +- gpio6 { +- pins = "gpio6"; +- function = "gpio"; +- drive-push-pull = <1>; +- }; +- +- gpio7 { +- pins = "gpio7"; +- function = "gpio"; +- drive-push-pull = <0>; +- }; +- }; +- +- fps { +- fps0 { +- maxim,fps-event-source = ; +- maxim,shutdown-fps-time-period-us = <640>; +- }; +- +- fps1 { +- maxim,fps-event-source = ; +- maxim,shutdown-fps-time-period-us = <640>; +- maxim,device-state-on-disabled-event = ; +- }; +- +- fps2 { +- maxim,fps-event-source = ; +- maxim,shutdown-fps-time-period-us = <640>; +- }; +- }; +- +- regulators { +- in-sd0-supply = <&vdd_5v0_sys>; +- in-sd1-supply = <&vdd_5v0_sys>; +- in-sd2-supply = <&vdd_5v0_sys>; +- in-sd3-supply = <&vdd_5v0_sys>; +- in-sd4-supply = <&vdd_5v0_sys>; +- +- in-ldo0-1-supply = <&vdd_5v0_sys>; +- in-ldo2-supply = <&vdd_5v0_sys>; +- in-ldo3-5-supply = <&vdd_5v0_sys>; +- in-ldo4-6-supply = <&vdd_5v0_sys>; +- in-ldo7-8-supply = <&vdd_1v8ls>; +- +- vdd_1v0: sd0 { +- regulator-name = "VDDIO_SYS_1V0"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v8hs: sd1 { +- regulator-name = "VDDIO_SYS_1V8HS"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v8ls: sd2 { +- regulator-name = "VDDIO_SYS_1V8LS"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v8ao: sd3 { +- regulator-name = "VDDIO_AO_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- sd4 { +- regulator-name = "VDD_DDR_1V1"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo0 { +- regulator-name = "VDD_RTC"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo2 { +- regulator-name = "VDDIO_AO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_emmc_3v3: ldo3 { +- regulator-name = "VDD_EMMC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vdd_usb_3v3: ldo5 { +- regulator-name = "VDD_USB_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo6 { +- regulator-name = "VDD_SDIO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo7 { +- regulator-name = "AVDD_CSI_1V2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- }; +- }; +- +- temperature-sensor@4c { +- compatible = "ti,tmp451"; +- reg = <0x4c>; +- +- interrupt-parent = <&gpio>; +- interrupts = ; +- vcc-supply = <&vdd_1v8ls>; +- +- #thermal-sensor-cells = <1>; +- }; +- }; +- }; +- +- vdd_5v0_sys: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "VIN_SYS_5V0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_hdmi: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_5V0_HDMI_CON"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA194_MAIN_GPIO(A, 3) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vdd_3v3_pcie: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "PEX_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; +- regulator-boot-on; +- enable-active-high; +- }; +- +- vdd_12v_pcie: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_12V"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_HIGH>; +- regulator-boot-on; +- }; +- +- vdd_5v_sata: regulator@4 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_5V_SATA"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 1) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p2972-0000.dts b/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p2972-0000.dts +deleted file mode 100644 +index 96bd01cadb18..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p2972-0000.dts ++++ /dev/null +@@ -1,941 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +- +-#include "tegra194-p2888.dtsi" +- +-/ { +- model = "NVIDIA Jetson AGX Xavier Developer Kit"; +- compatible = "nvidia,p2972-0000", "nvidia,tegra194"; +- +- bus@0 { +- aconnect@2900000 { +- status = "okay"; +- +- dma-controller@2930000 { +- status = "okay"; +- }; +- +- interrupt-controller@2a40000 { +- status = "okay"; +- }; +- +- ahub@2900800 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0x0>; +- +- xbar_admaif0_ep: endpoint { +- remote-endpoint = <&admaif0_ep>; +- }; +- }; +- +- port@1 { +- reg = <0x1>; +- +- xbar_admaif1_ep: endpoint { +- remote-endpoint = <&admaif1_ep>; +- }; +- }; +- +- port@2 { +- reg = <0x2>; +- +- xbar_admaif2_ep: endpoint { +- remote-endpoint = <&admaif2_ep>; +- }; +- }; +- +- port@3 { +- reg = <0x3>; +- +- xbar_admaif3_ep: endpoint { +- remote-endpoint = <&admaif3_ep>; +- }; +- }; +- +- port@4 { +- reg = <0x4>; +- +- xbar_admaif4_ep: endpoint { +- remote-endpoint = <&admaif4_ep>; +- }; +- }; +- +- port@5 { +- reg = <0x5>; +- +- xbar_admaif5_ep: endpoint { +- remote-endpoint = <&admaif5_ep>; +- }; +- }; +- +- port@6 { +- reg = <0x6>; +- +- xbar_admaif6_ep: endpoint { +- remote-endpoint = <&admaif6_ep>; +- }; +- }; +- +- port@7 { +- reg = <0x7>; +- +- xbar_admaif7_ep: endpoint { +- remote-endpoint = <&admaif7_ep>; +- }; +- }; +- +- port@8 { +- reg = <0x8>; +- +- xbar_admaif8_ep: endpoint { +- remote-endpoint = <&admaif8_ep>; +- }; +- }; +- +- port@9 { +- reg = <0x9>; +- +- xbar_admaif9_ep: endpoint { +- remote-endpoint = <&admaif9_ep>; +- }; +- }; +- +- port@a { +- reg = <0xa>; +- +- xbar_admaif10_ep: endpoint { +- remote-endpoint = <&admaif10_ep>; +- }; +- }; +- +- port@b { +- reg = <0xb>; +- +- xbar_admaif11_ep: endpoint { +- remote-endpoint = <&admaif11_ep>; +- }; +- }; +- +- port@c { +- reg = <0xc>; +- +- xbar_admaif12_ep: endpoint { +- remote-endpoint = <&admaif12_ep>; +- }; +- }; +- +- port@d { +- reg = <0xd>; +- +- xbar_admaif13_ep: endpoint { +- remote-endpoint = <&admaif13_ep>; +- }; +- }; +- +- port@e { +- reg = <0xe>; +- +- xbar_admaif14_ep: endpoint { +- remote-endpoint = <&admaif14_ep>; +- }; +- }; +- +- port@f { +- reg = <0xf>; +- +- xbar_admaif15_ep: endpoint { +- remote-endpoint = <&admaif15_ep>; +- }; +- }; +- +- port@10 { +- reg = <0x10>; +- +- xbar_admaif16_ep: endpoint { +- remote-endpoint = <&admaif16_ep>; +- }; +- }; +- +- port@11 { +- reg = <0x11>; +- +- xbar_admaif17_ep: endpoint { +- remote-endpoint = <&admaif17_ep>; +- }; +- }; +- +- port@12 { +- reg = <0x12>; +- +- xbar_admaif18_ep: endpoint { +- remote-endpoint = <&admaif18_ep>; +- }; +- }; +- +- port@13 { +- reg = <0x13>; +- +- xbar_admaif19_ep: endpoint { +- remote-endpoint = <&admaif19_ep>; +- }; +- }; +- +- xbar_i2s1_port: port@14 { +- reg = <0x14>; +- +- xbar_i2s1_ep: endpoint { +- remote-endpoint = <&i2s1_cif_ep>; +- }; +- }; +- +- xbar_i2s2_port: port@15 { +- reg = <0x15>; +- +- xbar_i2s2_ep: endpoint { +- remote-endpoint = <&i2s2_cif_ep>; +- }; +- }; +- +- xbar_i2s4_port: port@17 { +- reg = <0x17>; +- +- xbar_i2s4_ep: endpoint { +- remote-endpoint = <&i2s4_cif_ep>; +- }; +- }; +- +- xbar_i2s6_port: port@19 { +- reg = <0x19>; +- +- xbar_i2s6_ep: endpoint { +- remote-endpoint = <&i2s6_cif_ep>; +- }; +- }; +- +- xbar_dmic3_port: port@1c { +- reg = <0x1c>; +- +- xbar_dmic3_ep: endpoint { +- remote-endpoint = <&dmic3_cif_ep>; +- }; +- }; +- }; +- +- admaif@290f000 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- admaif0_port: port@0 { +- reg = <0x0>; +- +- admaif0_ep: endpoint { +- remote-endpoint = <&xbar_admaif0_ep>; +- }; +- }; +- +- admaif1_port: port@1 { +- reg = <0x1>; +- +- admaif1_ep: endpoint { +- remote-endpoint = <&xbar_admaif1_ep>; +- }; +- }; +- +- admaif2_port: port@2 { +- reg = <0x2>; +- +- admaif2_ep: endpoint { +- remote-endpoint = <&xbar_admaif2_ep>; +- }; +- }; +- +- admaif3_port: port@3 { +- reg = <0x3>; +- +- admaif3_ep: endpoint { +- remote-endpoint = <&xbar_admaif3_ep>; +- }; +- }; +- +- admaif4_port: port@4 { +- reg = <0x4>; +- +- admaif4_ep: endpoint { +- remote-endpoint = <&xbar_admaif4_ep>; +- }; +- }; +- +- admaif5_port: port@5 { +- reg = <0x5>; +- +- admaif5_ep: endpoint { +- remote-endpoint = <&xbar_admaif5_ep>; +- }; +- }; +- +- admaif6_port: port@6 { +- reg = <0x6>; +- +- admaif6_ep: endpoint { +- remote-endpoint = <&xbar_admaif6_ep>; +- }; +- }; +- +- admaif7_port: port@7 { +- reg = <0x7>; +- +- admaif7_ep: endpoint { +- remote-endpoint = <&xbar_admaif7_ep>; +- }; +- }; +- +- admaif8_port: port@8 { +- reg = <0x8>; +- +- admaif8_ep: endpoint { +- remote-endpoint = <&xbar_admaif8_ep>; +- }; +- }; +- +- admaif9_port: port@9 { +- reg = <0x9>; +- +- admaif9_ep: endpoint { +- remote-endpoint = <&xbar_admaif9_ep>; +- }; +- }; +- +- admaif10_port: port@a { +- reg = <0xa>; +- +- admaif10_ep: endpoint { +- remote-endpoint = <&xbar_admaif10_ep>; +- }; +- }; +- +- admaif11_port: port@b { +- reg = <0xb>; +- +- admaif11_ep: endpoint { +- remote-endpoint = <&xbar_admaif11_ep>; +- }; +- }; +- +- admaif12_port: port@c { +- reg = <0xc>; +- +- admaif12_ep: endpoint { +- remote-endpoint = <&xbar_admaif12_ep>; +- }; +- }; +- +- admaif13_port: port@d { +- reg = <0xd>; +- +- admaif13_ep: endpoint { +- remote-endpoint = <&xbar_admaif13_ep>; +- }; +- }; +- +- admaif14_port: port@e { +- reg = <0xe>; +- +- admaif14_ep: endpoint { +- remote-endpoint = <&xbar_admaif14_ep>; +- }; +- }; +- +- admaif15_port: port@f { +- reg = <0xf>; +- +- admaif15_ep: endpoint { +- remote-endpoint = <&xbar_admaif15_ep>; +- }; +- }; +- +- admaif16_port: port@10 { +- reg = <0x10>; +- +- admaif16_ep: endpoint { +- remote-endpoint = <&xbar_admaif16_ep>; +- }; +- }; +- +- admaif17_port: port@11 { +- reg = <0x11>; +- +- admaif17_ep: endpoint { +- remote-endpoint = <&xbar_admaif17_ep>; +- }; +- }; +- +- admaif18_port: port@12 { +- reg = <0x12>; +- +- admaif18_ep: endpoint { +- remote-endpoint = <&xbar_admaif18_ep>; +- }; +- }; +- +- admaif19_port: port@13 { +- reg = <0x13>; +- +- admaif19_ep: endpoint { +- remote-endpoint = <&xbar_admaif19_ep>; +- }; +- }; +- }; +- }; +- +- i2s@2901000 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- i2s1_cif_ep: endpoint { +- remote-endpoint = <&xbar_i2s1_ep>; +- }; +- }; +- +- i2s1_port: port@1 { +- reg = <1>; +- +- i2s1_dap_ep: endpoint { +- dai-format = "i2s"; +- remote-endpoint = <&rt5658_ep>; +- }; +- }; +- }; +- }; +- +- i2s@2901100 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- i2s2_cif_ep: endpoint { +- remote-endpoint = <&xbar_i2s2_ep>; +- }; +- }; +- +- i2s2_port: port@1 { +- reg = <1>; +- +- i2s2_dap_ep: endpoint { +- dai-format = "i2s"; +- /* Place holder for external Codec */ +- }; +- }; +- }; +- }; +- +- i2s@2901300 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- i2s4_cif_ep: endpoint { +- remote-endpoint = <&xbar_i2s4_ep>; +- }; +- }; +- +- i2s4_port: port@1 { +- reg = <1>; +- +- i2s4_dap_ep: endpoint { +- dai-format = "i2s"; +- /* Place holder for external Codec */ +- }; +- }; +- }; +- }; +- +- i2s@2901500 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- i2s6_cif_ep: endpoint { +- remote-endpoint = <&xbar_i2s6_ep>; +- }; +- }; +- +- i2s6_port: port@1 { +- reg = <1>; +- +- i2s6_dap_ep: endpoint@0 { +- dai-format = "i2s"; +- /* Place holder for external Codec */ +- }; +- }; +- }; +- }; +- +- dmic@2904200 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- dmic3_cif_ep: endpoint { +- remote-endpoint = <&xbar_dmic3_ep>; +- }; +- }; +- +- dmic3_port: port@1 { +- reg = <1>; +- +- dmic3_dap_ep: endpoint { +- /* Place holder for external Codec */ +- }; +- }; +- }; +- }; +- }; +- }; +- +- i2c@3160000 { +- eeprom@56 { +- compatible = "atmel,24c02"; +- reg = <0x56>; +- +- label = "system"; +- vcc-supply = <&vdd_1v8ls>; +- address-width = <8>; +- pagesize = <8>; +- size = <256>; +- read-only; +- }; +- }; +- +- ddc: i2c@31c0000 { +- status = "okay"; +- }; +- +- /* SDMMC1 (SD/MMC) */ +- mmc@3400000 { +- status = "okay"; +- }; +- +- hda@3510000 { +- nvidia,model = "NVIDIA Jetson AGX Xavier HDA"; +- status = "okay"; +- }; +- +- padctl@3520000 { +- status = "okay"; +- +- pads { +- usb2 { +- lanes { +- usb2-0 { +- status = "okay"; +- }; +- +- usb2-1 { +- status = "okay"; +- }; +- +- usb2-3 { +- status = "okay"; +- }; +- }; +- }; +- +- usb3 { +- lanes { +- usb3-0 { +- status = "okay"; +- }; +- +- usb3-2 { +- status = "okay"; +- }; +- +- usb3-3 { +- status = "okay"; +- }; +- }; +- }; +- }; +- +- ports { +- usb2-0 { +- mode = "host"; +- status = "okay"; +- }; +- +- usb2-1 { +- mode = "host"; +- status = "okay"; +- }; +- +- usb2-3 { +- mode = "host"; +- status = "okay"; +- }; +- +- usb3-0 { +- nvidia,usb2-companion = <1>; +- status = "okay"; +- }; +- +- usb3-2 { +- nvidia,usb2-companion = <0>; +- status = "okay"; +- }; +- +- usb3-3 { +- nvidia,usb2-companion = <3>; +- maximum-speed = "super-speed"; +- status = "okay"; +- }; +- }; +- }; +- +- usb@3610000 { +- status = "okay"; +- +- phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, +- <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, +- <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>, +- <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>, +- <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>, +- <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-3}>; +- phy-names = "usb2-0", "usb2-1", "usb2-3", "usb3-0", "usb3-2", "usb3-3"; +- }; +- +- i2c@c250000 { +- status = "okay"; +- +- rt5658: audio-codec@1a { +- status = "okay"; +- +- compatible = "realtek,rt5658"; +- reg = <0x1a>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_AUD_MCLK>; +- clock-names = "mclk"; +- realtek,jd-src = <2>; +- sound-name-prefix = "CVB-RT"; +- +- port { +- rt5658_ep: endpoint { +- remote-endpoint = <&i2s1_dap_ep>; +- mclk-fs = <256>; +- }; +- }; +- }; +- }; +- +- pwm@c340000 { +- status = "okay"; +- }; +- +- host1x@13e00000 { +- display-hub@15200000 { +- status = "okay"; +- }; +- +- dpaux@155c0000 { +- status = "okay"; +- }; +- +- dpaux@155d0000 { +- status = "okay"; +- }; +- +- dpaux@155e0000 { +- status = "okay"; +- }; +- +- /* DP0 */ +- sor@15b00000 { +- status = "okay"; +- +- avdd-io-hdmi-dp-supply = <&vdd_1v0>; +- vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>; +- +- nvidia,dpaux = <&dpaux0>; +- }; +- +- /* DP1 */ +- sor@15b40000 { +- status = "okay"; +- +- avdd-io-hdmi-dp-supply = <&vdd_1v0>; +- vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>; +- +- nvidia,dpaux = <&dpaux1>; +- }; +- +- /* HDMI */ +- sor@15b80000 { +- status = "okay"; +- +- avdd-io-hdmi-dp-supply = <&vdd_1v0>; +- vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>; +- hdmi-supply = <&vdd_hdmi>; +- +- nvidia,ddc-i2c-bus = <&ddc>; +- nvidia,hpd-gpio = <&gpio TEGRA194_MAIN_GPIO(M, 2) +- GPIO_ACTIVE_LOW>; +- }; +- }; +- }; +- +- pcie@14100000 { +- status = "okay"; +- +- vddio-pex-ctl-supply = <&vdd_1v8ao>; +- +- phys = <&p2u_hsio_0>; +- phy-names = "p2u-0"; +- }; +- +- pcie@14140000 { +- status = "okay"; +- +- vddio-pex-ctl-supply = <&vdd_1v8ao>; +- +- phys = <&p2u_hsio_7>; +- phy-names = "p2u-0"; +- }; +- +- pcie@14180000 { +- status = "okay"; +- +- vddio-pex-ctl-supply = <&vdd_1v8ao>; +- +- phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, +- <&p2u_hsio_5>; +- phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; +- }; +- +- pcie@141a0000 { +- status = "okay"; +- +- vddio-pex-ctl-supply = <&vdd_1v8ao>; +- vpcie3v3-supply = <&vdd_3v3_pcie>; +- vpcie12v-supply = <&vdd_12v_pcie>; +- +- phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, +- <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, +- <&p2u_nvhs_6>, <&p2u_nvhs_7>; +- +- phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", +- "p2u-5", "p2u-6", "p2u-7"; +- }; +- +- pcie_ep@141a0000 { +- status = "disabled"; +- +- vddio-pex-ctl-supply = <&vdd_1v8ao>; +- +- reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; +- +- nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) +- GPIO_ACTIVE_HIGH>; +- +- phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, +- <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, +- <&p2u_nvhs_6>, <&p2u_nvhs_7>; +- +- phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", +- "p2u-5", "p2u-6", "p2u-7"; +- }; +- +- fan: fan { +- compatible = "pwm-fan"; +- pwms = <&pwm4 0 45334>; +- +- cooling-levels = <0 64 128 255>; +- #cooling-cells = <2>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- force-recovery { +- label = "Force Recovery"; +- gpios = <&gpio TEGRA194_MAIN_GPIO(G, 0) +- GPIO_ACTIVE_LOW>; +- linux,input-type = ; +- linux,code = ; +- debounce-interval = <10>; +- }; +- +- power { +- label = "Power"; +- gpios = <&gpio_aon TEGRA194_AON_GPIO(EE, 4) +- GPIO_ACTIVE_LOW>; +- linux,input-type = ; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-event-action = ; +- wakeup-source; +- }; +- }; +- +- sound { +- compatible = "nvidia,tegra186-audio-graph-card"; +- status = "okay"; +- +- dais = /* ADMAIF (FE) Ports */ +- <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, +- <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, +- <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, +- <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, +- <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, +- /* XBAR Ports */ +- <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s4_port>, +- <&xbar_i2s6_port>, <&xbar_dmic3_port>, +- /* BE I/O Ports */ +- <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>, +- <&dmic3_port>; +- +- label = "NVIDIA Jetson AGX Xavier APE"; +- +- widgets = +- "Microphone", "CVB-RT MIC Jack", +- "Microphone", "CVB-RT MIC", +- "Headphone", "CVB-RT HP Jack", +- "Speaker", "CVB-RT SPK"; +- +- routing = +- /* I2S1 <-> RT5658 */ +- "CVB-RT AIF1 Playback", "I2S1 DAP-Playback", +- "I2S1 DAP-Capture", "CVB-RT AIF1 Capture", +- /* RT5658 Codec controls */ +- "CVB-RT HP Jack", "CVB-RT HPO L Playback", +- "CVB-RT HP Jack", "CVB-RT HPO R Playback", +- "CVB-RT IN1P", "CVB-RT MIC Jack", +- "CVB-RT IN2P", "CVB-RT MIC Jack", +- "CVB-RT SPK", "CVB-RT SPO Playback", +- "CVB-RT DMIC L1", "CVB-RT MIC", +- "CVB-RT DMIC L2", "CVB-RT MIC", +- "CVB-RT DMIC R1", "CVB-RT MIC", +- "CVB-RT DMIC R2", "CVB-RT MIC"; +- }; +- +- thermal-zones { +- cpu { +- polling-delay = <0>; +- polling-delay-passive = <500>; +- status = "okay"; +- +- trips { +- cpu_trip_critical: critical { +- temperature = <96500>; +- hysteresis = <0>; +- type = "critical"; +- }; +- +- cpu_trip_hot: hot { +- temperature = <70000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- cpu_trip_active: active { +- temperature = <50000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- cpu_trip_passive: passive { +- temperature = <30000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- }; +- +- cooling-maps { +- cpu-critical { +- cooling-device = <&fan 3 3>; +- trip = <&cpu_trip_critical>; +- }; +- +- cpu-hot { +- cooling-device = <&fan 2 2>; +- trip = <&cpu_trip_hot>; +- }; +- +- cpu-active { +- cooling-device = <&fan 1 1>; +- trip = <&cpu_trip_active>; +- }; +- +- cpu-passive { +- cooling-device = <&fan 0 0>; +- trip = <&cpu_trip_passive>; +- }; +- }; +- }; +- +- gpu { +- polling-delay = <0>; +- polling-delay-passive = <500>; +- status = "okay"; +- +- trips { +- gpu_alert0: critical { +- temperature = <99000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- aux { +- polling-delay = <0>; +- polling-delay-passive = <500>; +- status = "okay"; +- +- trips { +- aux_alert0: critical { +- temperature = <90000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p3509-0000+p3668-0000.dts b/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p3509-0000+p3668-0000.dts +deleted file mode 100644 +index 1c3874b677c0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p3509-0000+p3668-0000.dts ++++ /dev/null +@@ -1,10 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "tegra194-p3668-0000.dtsi" +-#include "tegra194-p3509-0000.dtsi" +- +-/ { +- model = "NVIDIA Jetson Xavier NX Developer Kit (SD-card)"; +- compatible = "nvidia,p3509-0000+p3668-0000", "nvidia,tegra194"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p3509-0000+p3668-0001.dts b/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p3509-0000+p3668-0001.dts +deleted file mode 100644 +index 238fd98e8e45..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p3509-0000+p3668-0001.dts ++++ /dev/null +@@ -1,10 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "tegra194-p3668-0001.dtsi" +-#include "tegra194-p3509-0000.dtsi" +- +-/ { +- model = "NVIDIA Jetson Xavier NX Developer Kit (eMMC)"; +- compatible = "nvidia,p3509-0000+p3668-0001", "nvidia,tegra194"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p3509-0000.dtsi b/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p3509-0000.dtsi +deleted file mode 100644 +index 836a7e0a4267..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p3509-0000.dtsi ++++ /dev/null +@@ -1,944 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include +-#include +- +-/ { +- bus@0 { +- aconnect@2900000 { +- status = "okay"; +- +- dma-controller@2930000 { +- status = "okay"; +- }; +- +- interrupt-controller@2a40000 { +- status = "okay"; +- }; +- +- ahub@2900800 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0x0>; +- +- xbar_admaif0_ep: endpoint { +- remote-endpoint = <&admaif0_ep>; +- }; +- }; +- +- port@1 { +- reg = <0x1>; +- +- xbar_admaif1_ep: endpoint { +- remote-endpoint = <&admaif1_ep>; +- }; +- }; +- +- port@2 { +- reg = <0x2>; +- +- xbar_admaif2_ep: endpoint { +- remote-endpoint = <&admaif2_ep>; +- }; +- }; +- +- port@3 { +- reg = <0x3>; +- +- xbar_admaif3_ep: endpoint { +- remote-endpoint = <&admaif3_ep>; +- }; +- }; +- +- port@4 { +- reg = <0x4>; +- +- xbar_admaif4_ep: endpoint { +- remote-endpoint = <&admaif4_ep>; +- }; +- }; +- +- port@5 { +- reg = <0x5>; +- +- xbar_admaif5_ep: endpoint { +- remote-endpoint = <&admaif5_ep>; +- }; +- }; +- +- port@6 { +- reg = <0x6>; +- +- xbar_admaif6_ep: endpoint { +- remote-endpoint = <&admaif6_ep>; +- }; +- }; +- +- port@7 { +- reg = <0x7>; +- +- xbar_admaif7_ep: endpoint { +- remote-endpoint = <&admaif7_ep>; +- }; +- }; +- +- port@8 { +- reg = <0x8>; +- +- xbar_admaif8_ep: endpoint { +- remote-endpoint = <&admaif8_ep>; +- }; +- }; +- +- port@9 { +- reg = <0x9>; +- +- xbar_admaif9_ep: endpoint { +- remote-endpoint = <&admaif9_ep>; +- }; +- }; +- +- port@a { +- reg = <0xa>; +- +- xbar_admaif10_ep: endpoint { +- remote-endpoint = <&admaif10_ep>; +- }; +- }; +- +- port@b { +- reg = <0xb>; +- +- xbar_admaif11_ep: endpoint { +- remote-endpoint = <&admaif11_ep>; +- }; +- }; +- +- port@c { +- reg = <0xc>; +- +- xbar_admaif12_ep: endpoint { +- remote-endpoint = <&admaif12_ep>; +- }; +- }; +- +- port@d { +- reg = <0xd>; +- +- xbar_admaif13_ep: endpoint { +- remote-endpoint = <&admaif13_ep>; +- }; +- }; +- +- port@e { +- reg = <0xe>; +- +- xbar_admaif14_ep: endpoint { +- remote-endpoint = <&admaif14_ep>; +- }; +- }; +- +- port@f { +- reg = <0xf>; +- +- xbar_admaif15_ep: endpoint { +- remote-endpoint = <&admaif15_ep>; +- }; +- }; +- +- port@10 { +- reg = <0x10>; +- +- xbar_admaif16_ep: endpoint { +- remote-endpoint = <&admaif16_ep>; +- }; +- }; +- +- port@11 { +- reg = <0x11>; +- +- xbar_admaif17_ep: endpoint { +- remote-endpoint = <&admaif17_ep>; +- }; +- }; +- +- port@12 { +- reg = <0x12>; +- +- xbar_admaif18_ep: endpoint { +- remote-endpoint = <&admaif18_ep>; +- }; +- }; +- +- port@13 { +- reg = <0x13>; +- +- xbar_admaif19_ep: endpoint { +- remote-endpoint = <&admaif19_ep>; +- }; +- }; +- +- xbar_i2s3_port: port@16 { +- reg = <0x16>; +- +- xbar_i2s3_ep: endpoint { +- remote-endpoint = <&i2s3_cif_ep>; +- }; +- }; +- +- xbar_i2s5_port: port@18 { +- reg = <0x18>; +- +- xbar_i2s5_ep: endpoint { +- remote-endpoint = <&i2s5_cif_ep>; +- }; +- }; +- +- xbar_dmic1_port: port@1a { +- reg = <0x1a>; +- +- xbar_dmic1_ep: endpoint { +- remote-endpoint = <&dmic1_cif_ep>; +- }; +- }; +- +- xbar_dmic2_port: port@1b { +- reg = <0x1b>; +- +- xbar_dmic2_ep: endpoint { +- remote-endpoint = <&dmic2_cif_ep>; +- }; +- }; +- +- xbar_dmic4_port: port@1d { +- reg = <0x1d>; +- +- xbar_dmic4_ep: endpoint { +- remote-endpoint = <&dmic4_cif_ep>; +- }; +- }; +- +- xbar_dspk1_port: port@1e { +- reg = <0x1e>; +- +- xbar_dspk1_ep: endpoint { +- remote-endpoint = <&dspk1_cif_ep>; +- }; +- }; +- +- xbar_dspk2_port: port@1f { +- reg = <0x1f>; +- +- xbar_dspk2_ep: endpoint { +- remote-endpoint = <&dspk2_cif_ep>; +- }; +- }; +- }; +- +- admaif@290f000 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- admaif0_port: port@0 { +- reg = <0x0>; +- +- admaif0_ep: endpoint { +- remote-endpoint = <&xbar_admaif0_ep>; +- }; +- }; +- +- admaif1_port: port@1 { +- reg = <0x1>; +- +- admaif1_ep: endpoint { +- remote-endpoint = <&xbar_admaif1_ep>; +- }; +- }; +- +- admaif2_port: port@2 { +- reg = <0x2>; +- +- admaif2_ep: endpoint { +- remote-endpoint = <&xbar_admaif2_ep>; +- }; +- }; +- +- admaif3_port: port@3 { +- reg = <0x3>; +- +- admaif3_ep: endpoint { +- remote-endpoint = <&xbar_admaif3_ep>; +- }; +- }; +- +- admaif4_port: port@4 { +- reg = <0x4>; +- +- admaif4_ep: endpoint { +- remote-endpoint = <&xbar_admaif4_ep>; +- }; +- }; +- +- admaif5_port: port@5 { +- reg = <0x5>; +- +- admaif5_ep: endpoint { +- remote-endpoint = <&xbar_admaif5_ep>; +- }; +- }; +- +- admaif6_port: port@6 { +- reg = <0x6>; +- +- admaif6_ep: endpoint { +- remote-endpoint = <&xbar_admaif6_ep>; +- }; +- }; +- +- admaif7_port: port@7 { +- reg = <0x7>; +- +- admaif7_ep: endpoint { +- remote-endpoint = <&xbar_admaif7_ep>; +- }; +- }; +- +- admaif8_port: port@8 { +- reg = <0x8>; +- +- admaif8_ep: endpoint { +- remote-endpoint = <&xbar_admaif8_ep>; +- }; +- }; +- +- admaif9_port: port@9 { +- reg = <0x9>; +- +- admaif9_ep: endpoint { +- remote-endpoint = <&xbar_admaif9_ep>; +- }; +- }; +- +- admaif10_port: port@a { +- reg = <0xa>; +- +- admaif10_ep: endpoint { +- remote-endpoint = <&xbar_admaif10_ep>; +- }; +- }; +- +- admaif11_port: port@b { +- reg = <0xb>; +- +- admaif11_ep: endpoint { +- remote-endpoint = <&xbar_admaif11_ep>; +- }; +- }; +- +- admaif12_port: port@c { +- reg = <0xc>; +- +- admaif12_ep: endpoint { +- remote-endpoint = <&xbar_admaif12_ep>; +- }; +- }; +- +- admaif13_port: port@d { +- reg = <0xd>; +- +- admaif13_ep: endpoint { +- remote-endpoint = <&xbar_admaif13_ep>; +- }; +- }; +- +- admaif14_port: port@e { +- reg = <0xe>; +- +- admaif14_ep: endpoint { +- remote-endpoint = <&xbar_admaif14_ep>; +- }; +- }; +- +- admaif15_port: port@f { +- reg = <0xf>; +- +- admaif15_ep: endpoint { +- remote-endpoint = <&xbar_admaif15_ep>; +- }; +- }; +- +- admaif16_port: port@10 { +- reg = <0x10>; +- +- admaif16_ep: endpoint { +- remote-endpoint = <&xbar_admaif16_ep>; +- }; +- }; +- +- admaif17_port: port@11 { +- reg = <0x11>; +- +- admaif17_ep: endpoint { +- remote-endpoint = <&xbar_admaif17_ep>; +- }; +- }; +- +- admaif18_port: port@12 { +- reg = <0x12>; +- +- admaif18_ep: endpoint { +- remote-endpoint = <&xbar_admaif18_ep>; +- }; +- }; +- +- admaif19_port: port@13 { +- reg = <0x13>; +- +- admaif19_ep: endpoint { +- remote-endpoint = <&xbar_admaif19_ep>; +- }; +- }; +- }; +- }; +- +- i2s@2901200 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- i2s3_cif_ep: endpoint { +- remote-endpoint = <&xbar_i2s3_ep>; +- }; +- }; +- +- i2s3_port: port@1 { +- reg = <1>; +- +- i2s3_dap_ep: endpoint { +- dai-format = "i2s"; +- /* Place holder for external Codec */ +- }; +- }; +- }; +- }; +- +- i2s@2901400 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- i2s5_cif_ep: endpoint { +- remote-endpoint = <&xbar_i2s5_ep>; +- }; +- }; +- +- i2s5_port: port@1 { +- reg = <1>; +- +- i2s5_dap_ep: endpoint@0 { +- dai-format = "i2s"; +- /* Place holder for external Codec */ +- }; +- }; +- }; +- }; +- +- dmic@2904000 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- dmic1_cif_ep: endpoint { +- remote-endpoint = <&xbar_dmic1_ep>; +- }; +- }; +- +- dmic1_port: port@1 { +- reg = <1>; +- +- dmic1_dap_ep: endpoint { +- /* Place holder for external Codec */ +- }; +- }; +- }; +- }; +- +- dmic@2904100 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- dmic2_cif_ep: endpoint { +- remote-endpoint = <&xbar_dmic2_ep>; +- }; +- }; +- +- dmic2_port: port@1 { +- reg = <1>; +- +- dmic2_dap_ep: endpoint { +- /* Place holder for external Codec */ +- }; +- }; +- }; +- }; +- +- dmic@2904300 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- dmic4_cif_ep: endpoint { +- remote-endpoint = <&xbar_dmic4_ep>; +- }; +- }; +- +- dmic4_port: port@1 { +- reg = <1>; +- +- dmic4_dap_ep: endpoint { +- /* Place holder for external Codec */ +- }; +- }; +- }; +- }; +- +- dspk@2905000 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- dspk1_cif_ep: endpoint { +- remote-endpoint = <&xbar_dspk1_ep>; +- }; +- }; +- +- dspk1_port: port@1 { +- reg = <1>; +- +- dspk1_dap_ep: endpoint { +- /* Place holder for external Codec */ +- }; +- }; +- }; +- }; +- +- dspk@2905100 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- dspk2_cif_ep: endpoint { +- remote-endpoint = <&xbar_dspk2_ep>; +- }; +- }; +- +- dspk2_port: port@1 { +- reg = <1>; +- +- dspk2_dap_ep: endpoint { +- /* Place holder for external Codec */ +- }; +- }; +- }; +- }; +- }; +- }; +- +- ddc: i2c@3190000 { +- status = "okay"; +- }; +- +- i2c@3160000 { +- eeprom@57 { +- compatible = "atmel,24c02"; +- reg = <0x57>; +- +- label = "system"; +- vcc-supply = <&vdd_1v8>; +- address-width = <8>; +- pagesize = <8>; +- size = <256>; +- read-only; +- }; +- }; +- +- hda@3510000 { +- nvidia,model = "NVIDIA Jetson Xavier NX HDA"; +- status = "okay"; +- }; +- +- padctl@3520000 { +- status = "okay"; +- +- pads { +- usb2 { +- lanes { +- usb2-1 { +- status = "okay"; +- }; +- +- usb2-2 { +- status = "okay"; +- }; +- }; +- }; +- +- usb3 { +- lanes { +- usb3-2 { +- status = "okay"; +- }; +- }; +- }; +- }; +- +- ports { +- usb2-1 { +- mode = "host"; +- status = "okay"; +- }; +- +- usb2-2 { +- mode = "host"; +- vbus-supply = <&vdd_5v0_sys>; +- status = "okay"; +- }; +- +- usb3-2 { +- nvidia,usb2-companion = <1>; +- vbus-supply = <&vdd_5v0_sys>; +- status = "okay"; +- }; +- }; +- }; +- +- usb@3610000 { +- status = "okay"; +- +- phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, +- <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>, +- <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>; +- phy-names = "usb2-1", "usb2-2", "usb3-2"; +- }; +- +- spi@3270000 { +- status = "okay"; +- +- flash@0 { +- compatible = "spi-nor"; +- reg = <0>; +- spi-max-frequency = <102000000>; +- spi-tx-bus-width = <4>; +- spi-rx-bus-width = <4>; +- }; +- }; +- +- pwm@32d0000 { +- status = "okay"; +- }; +- +- host1x@13e00000 { +- display-hub@15200000 { +- status = "okay"; +- }; +- +- dpaux@155c0000 { +- status = "okay"; +- }; +- +- dpaux@155d0000 { +- status = "okay"; +- }; +- +- /* DP0 */ +- sor@15b00000 { +- status = "okay"; +- +- avdd-io-hdmi-dp-supply = <&vdd_1v0>; +- vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>; +- +- nvidia,dpaux = <&dpaux0>; +- }; +- +- /* HDMI */ +- sor@15b40000 { +- status = "okay"; +- +- avdd-io-hdmi-dp-supply = <&vdd_1v0>; +- vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>; +- hdmi-supply = <&vdd_hdmi>; +- +- nvidia,ddc-i2c-bus = <&ddc>; +- nvidia,hpd-gpio = <&gpio TEGRA194_MAIN_GPIO(M, 1) +- GPIO_ACTIVE_LOW>; +- }; +- }; +- }; +- +- pcie@14160000 { +- status = "okay"; +- +- vddio-pex-ctl-supply = <&vdd_1v8ao>; +- +- phys = <&p2u_hsio_11>; +- phy-names = "p2u-0"; +- }; +- +- pcie@141a0000 { +- status = "okay"; +- +- vddio-pex-ctl-supply = <&vdd_1v8ao>; +- +- phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, +- <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, +- <&p2u_nvhs_6>, <&p2u_nvhs_7>; +- +- phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", +- "p2u-5", "p2u-6", "p2u-7"; +- }; +- +- pcie_ep@141a0000 { +- status = "disabled"; +- +- vddio-pex-ctl-supply = <&vdd_1v8ao>; +- +- reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; +- +- nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) +- GPIO_ACTIVE_HIGH>; +- +- phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, +- <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, +- <&p2u_nvhs_6>, <&p2u_nvhs_7>; +- +- phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", +- "p2u-5", "p2u-6", "p2u-7"; +- }; +- +- fan: fan { +- compatible = "pwm-fan"; +- pwms = <&pwm6 0 45334>; +- +- cooling-levels = <0 64 128 255>; +- #cooling-cells = <2>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- force-recovery { +- label = "Force Recovery"; +- gpios = <&gpio TEGRA194_MAIN_GPIO(G, 0) +- GPIO_ACTIVE_LOW>; +- linux,input-type = ; +- linux,code = ; +- debounce-interval = <10>; +- }; +- +- power { +- label = "Power"; +- gpios = <&gpio_aon TEGRA194_AON_GPIO(EE, 4) +- GPIO_ACTIVE_LOW>; +- linux,input-type = ; +- linux,code = ; +- debounce-interval = <10>; +- wakeup-event-action = ; +- wakeup-source; +- }; +- }; +- +- vdd_5v0_sys: regulator@100 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_5V_SYS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_3v3_sys: regulator@101 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_3V3_SYS"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_3v3_ao: regulator@102 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_3V3_AO"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v8: regulator@103 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_hdmi: regulator@104 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_5V0_HDMI_CON"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- sound { +- compatible = "nvidia,tegra186-audio-graph-card"; +- status = "okay"; +- +- dais = /* ADMAIF (FE) Ports */ +- <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, +- <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, +- <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, +- <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, +- <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, +- /* XBAR Ports */ +- <&xbar_i2s3_port>, <&xbar_i2s5_port>, +- <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic4_port>, +- <&xbar_dspk1_port>, <&xbar_dspk2_port>, +- /* BE I/O Ports */ +- <&i2s3_port>, <&i2s5_port>, +- <&dmic1_port>, <&dmic2_port>, <&dmic4_port>, +- <&dspk1_port>, <&dspk2_port>; +- +- label = "NVIDIA Jetson Xavier NX APE"; +- }; +- +- thermal-zones { +- cpu { +- polling-delay = <0>; +- polling-delay-passive = <500>; +- status = "okay"; +- +- trips { +- cpu_trip_critical: critical { +- temperature = <96500>; +- hysteresis = <0>; +- type = "critical"; +- }; +- +- cpu_trip_hot: hot { +- temperature = <70000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- cpu_trip_active: active { +- temperature = <50000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- cpu_trip_passive: passive { +- temperature = <30000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- }; +- +- cooling-maps { +- cpu-critical { +- cooling-device = <&fan 3 3>; +- trip = <&cpu_trip_critical>; +- }; +- +- cpu-hot { +- cooling-device = <&fan 2 2>; +- trip = <&cpu_trip_hot>; +- }; +- +- cpu-active { +- cooling-device = <&fan 1 1>; +- trip = <&cpu_trip_active>; +- }; +- +- cpu-passive { +- cooling-device = <&fan 0 0>; +- trip = <&cpu_trip_passive>; +- }; +- }; +- }; +- +- gpu { +- polling-delay = <0>; +- polling-delay-passive = <500>; +- status = "okay"; +- +- trips { +- gpu_alert0: critical { +- temperature = <99000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- aux { +- polling-delay = <0>; +- polling-delay-passive = <500>; +- status = "okay"; +- +- trips { +- aux_alert0: critical { +- temperature = <90000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p3668-0000.dtsi b/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p3668-0000.dtsi +deleted file mode 100644 +index 14da4206ea66..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p3668-0000.dtsi ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "tegra194-p3668.dtsi" +- +-/ { +- model = "NVIDIA Jetson Xavier NX (SD-card)"; +- compatible = "nvidia,p3668-0000", "nvidia,tegra194"; +- +- aliases { +- mmc0 = "/bus@0/mmc@3400000"; +- }; +- +- bus@0 { +- /* SDMMC1 (SD/MMC) */ +- mmc@3400000 { +- status = "okay"; +- bus-width = <4>; +- cd-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>; +- disable-wp; +- vmmc-supply = <&vdd_3v3_sd>; +- }; +- }; +- +- vdd_3v3_sd: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_3V3_SD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio TEGRA194_MAIN_GPIO(G, 2) GPIO_ACTIVE_HIGH>; +- regulator-boot-on; +- enable-active-high; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p3668-0001.dtsi b/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p3668-0001.dtsi +deleted file mode 100644 +index f5a9ebbfb12f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p3668-0001.dtsi ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "tegra194-p3668.dtsi" +- +-/ { +- model = "NVIDIA Jetson Xavier NX (eMMC)"; +- compatible = "nvidia,p3668-0001", "nvidia,tegra194"; +- +- aliases { +- mmc0 = "/bus@0/mmc@3460000"; +- }; +- +- bus@0 { +- /* SDMMC4 (eMMC) */ +- mmc@3460000 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- +- vqmmc-supply = <&vdd_1v8ls>; +- vmmc-supply = <&vdd_emmc_3v3>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p3668.dtsi b/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p3668.dtsi +deleted file mode 100644 +index f16b0aa8a374..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra194-p3668.dtsi ++++ /dev/null +@@ -1,283 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "tegra194.dtsi" +- +-#include +- +-/ { +- aliases { +- ethernet0 = "/bus@0/ethernet@2490000"; +- i2c0 = "/bpmp/i2c"; +- i2c1 = "/bus@0/i2c@3160000"; +- i2c2 = "/bus@0/i2c@c240000"; +- i2c3 = "/bus@0/i2c@3180000"; +- i2c4 = "/bus@0/i2c@3190000"; +- i2c5 = "/bus@0/i2c@31c0000"; +- i2c6 = "/bus@0/i2c@c250000"; +- i2c7 = "/bus@0/i2c@31e0000"; +- rtc0 = "/bpmp/i2c/pmic@3c"; +- rtc1 = "/bus@0/rtc@c2a0000"; +- serial0 = &tcu; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8"; +- stdout-path = "serial0:115200n8"; +- }; +- +- bus@0 { +- ethernet@2490000 { +- status = "okay"; +- +- phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(R, 1) GPIO_ACTIVE_LOW>; +- phy-handle = <&phy>; +- phy-mode = "rgmii-id"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy: phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0x0>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- memory-controller@2c00000 { +- status = "okay"; +- }; +- +- serial@3100000 { +- status = "okay"; +- }; +- +- i2c@3160000 { +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- +- label = "module"; +- vcc-supply = <&vdd_1v8ls>; +- address-width = <8>; +- pagesize = <8>; +- size = <256>; +- read-only; +- }; +- }; +- +- padctl@3520000 { +- avdd-usb-supply = <&vdd_usb_3v3>; +- vclamp-usb-supply = <&vdd_1v8ao>; +- +- ports { +- usb2-1 { +- vbus-supply = <&vdd_5v0_sys>; +- }; +- +- usb2-3 { +- vbus-supply = <&vdd_5v0_sys>; +- }; +- +- usb3-0 { +- vbus-supply = <&vdd_5v0_sys>; +- }; +- +- usb3-3 { +- vbus-supply = <&vdd_5v0_sys>; +- }; +- }; +- }; +- +- rtc@c2a0000 { +- status = "okay"; +- }; +- +- pmc@c360000 { +- nvidia,invert-interrupt; +- }; +- }; +- +- bpmp { +- i2c { +- status = "okay"; +- +- pmic: pmic@3c { +- compatible = "maxim,max20024"; +- reg = <0x3c>; +- +- interrupt-parent = <&pmc>; +- interrupts = <24 IRQ_TYPE_LEVEL_LOW>; +- #interrupt-cells = <2>; +- interrupt-controller; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&max20024_default>; +- +- max20024_default: pinmux { +- gpio0 { +- pins = "gpio0"; +- function = "gpio"; +- }; +- +- gpio1 { +- pins = "gpio1"; +- function = "fps-out"; +- maxim,active-fps-source = ; +- }; +- +- gpio2 { +- pins = "gpio2"; +- function = "fps-out"; +- maxim,active-fps-source = ; +- }; +- +- gpio3 { +- pins = "gpio3"; +- function = "fps-out"; +- maxim,active-fps-source = ; +- }; +- +- gpio4 { +- pins = "gpio4"; +- function = "32k-out1"; +- drive-push-pull = <1>; +- }; +- +- gpio6 { +- pins = "gpio6"; +- function = "gpio"; +- drive-push-pull = <1>; +- }; +- +- gpio7 { +- pins = "gpio7"; +- function = "gpio"; +- drive-push-pull = <0>; +- }; +- }; +- +- fps { +- fps0 { +- maxim,fps-event-source = ; +- maxim,shutdown-fps-time-period-us = <640>; +- }; +- +- fps1 { +- maxim,fps-event-source = ; +- maxim,shutdown-fps-time-period-us = <640>; +- maxim,device-state-on-disabled-event = ; +- }; +- +- fps2 { +- maxim,fps-event-source = ; +- maxim,shutdown-fps-time-period-us = <640>; +- }; +- }; +- +- regulators { +- in-sd0-supply = <&vdd_5v0_sys>; +- in-sd1-supply = <&vdd_5v0_sys>; +- in-sd2-supply = <&vdd_5v0_sys>; +- in-sd3-supply = <&vdd_5v0_sys>; +- in-sd4-supply = <&vdd_5v0_sys>; +- +- in-ldo0-1-supply = <&vdd_5v0_sys>; +- in-ldo2-supply = <&vdd_5v0_sys>; +- in-ldo3-5-supply = <&vdd_5v0_sys>; +- in-ldo4-6-supply = <&vdd_5v0_sys>; +- in-ldo7-8-supply = <&vdd_1v8ls>; +- +- vdd_1v0: sd0 { +- regulator-name = "VDDIO_SYS_1V0"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v8hs: sd1 { +- regulator-name = "VDDIO_SYS_1V8HS"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v8ls: sd2 { +- regulator-name = "VDDIO_SYS_1V8LS"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_1v8ao: sd3 { +- regulator-name = "VDDIO_AO_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- sd4 { +- regulator-name = "VDD_DDR_1V1"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo0 { +- regulator-name = "VDD_RTC"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo2 { +- regulator-name = "VDDIO_AO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_emmc_3v3: ldo3 { +- regulator-name = "VDD_EMMC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vdd_usb_3v3: ldo5 { +- regulator-name = "VDD_USB_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- ldo6 { +- regulator-name = "VDD_SDIO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- ldo7 { +- regulator-name = "AVDD_CSI_1V2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra194.dtsi b/scripts/dtc/include-prefixes/arm64/nvidia/tegra194.dtsi +deleted file mode 100644 +index 510d2974470c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra194.dtsi ++++ /dev/null +@@ -1,2592 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "nvidia,tegra194"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- /* control backbone */ +- bus@0 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x0 0x40000000>; +- +- misc@100000 { +- compatible = "nvidia,tegra194-misc"; +- reg = <0x00100000 0xf000>, +- <0x0010f000 0x1000>; +- }; +- +- gpio: gpio@2200000 { +- compatible = "nvidia,tegra194-gpio"; +- reg-names = "security", "gpio"; +- reg = <0x2200000 0x10000>, +- <0x2210000 0x10000>; +- interrupts = , +- , +- , +- , +- , +- ; +- #interrupt-cells = <2>; +- interrupt-controller; +- #gpio-cells = <2>; +- gpio-controller; +- }; +- +- ethernet@2490000 { +- compatible = "nvidia,tegra194-eqos", +- "nvidia,tegra186-eqos", +- "snps,dwc-qos-ethernet-4.10"; +- reg = <0x02490000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, +- <&bpmp TEGRA194_CLK_EQOS_AXI>, +- <&bpmp TEGRA194_CLK_EQOS_RX>, +- <&bpmp TEGRA194_CLK_EQOS_TX>, +- <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; +- clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; +- resets = <&bpmp TEGRA194_RESET_EQOS>; +- reset-names = "eqos"; +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA194_SID_EQOS>; +- status = "disabled"; +- +- snps,write-requests = <1>; +- snps,read-requests = <3>; +- snps,burst-map = <0x7>; +- snps,txpbl = <16>; +- snps,rxpbl = <8>; +- }; +- +- aconnect@2900000 { +- compatible = "nvidia,tegra194-aconnect", +- "nvidia,tegra210-aconnect"; +- clocks = <&bpmp TEGRA194_CLK_APE>, +- <&bpmp TEGRA194_CLK_APB2APE>; +- clock-names = "ape", "apb2ape"; +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x02900000 0x02900000 0x200000>; +- status = "disabled"; +- +- adma: dma-controller@2930000 { +- compatible = "nvidia,tegra194-adma", +- "nvidia,tegra186-adma"; +- reg = <0x02930000 0x20000>; +- interrupt-parent = <&agic>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- #dma-cells = <1>; +- clocks = <&bpmp TEGRA194_CLK_AHUB>; +- clock-names = "d_audio"; +- status = "disabled"; +- }; +- +- agic: interrupt-controller@2a40000 { +- compatible = "nvidia,tegra194-agic", +- "nvidia,tegra210-agic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x02a41000 0x1000>, +- <0x02a42000 0x2000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_APE>; +- clock-names = "clk"; +- status = "disabled"; +- }; +- +- tegra_ahub: ahub@2900800 { +- compatible = "nvidia,tegra194-ahub", +- "nvidia,tegra186-ahub"; +- reg = <0x02900800 0x800>; +- clocks = <&bpmp TEGRA194_CLK_AHUB>; +- clock-names = "ahub"; +- assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; +- assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x02900800 0x02900800 0x11800>; +- status = "disabled"; +- +- tegra_admaif: admaif@290f000 { +- compatible = "nvidia,tegra194-admaif", +- "nvidia,tegra186-admaif"; +- reg = <0x0290f000 0x1000>; +- dmas = <&adma 1>, <&adma 1>, +- <&adma 2>, <&adma 2>, +- <&adma 3>, <&adma 3>, +- <&adma 4>, <&adma 4>, +- <&adma 5>, <&adma 5>, +- <&adma 6>, <&adma 6>, +- <&adma 7>, <&adma 7>, +- <&adma 8>, <&adma 8>, +- <&adma 9>, <&adma 9>, +- <&adma 10>, <&adma 10>, +- <&adma 11>, <&adma 11>, +- <&adma 12>, <&adma 12>, +- <&adma 13>, <&adma 13>, +- <&adma 14>, <&adma 14>, +- <&adma 15>, <&adma 15>, +- <&adma 16>, <&adma 16>, +- <&adma 17>, <&adma 17>, +- <&adma 18>, <&adma 18>, +- <&adma 19>, <&adma 19>, +- <&adma 20>, <&adma 20>; +- dma-names = "rx1", "tx1", +- "rx2", "tx2", +- "rx3", "tx3", +- "rx4", "tx4", +- "rx5", "tx5", +- "rx6", "tx6", +- "rx7", "tx7", +- "rx8", "tx8", +- "rx9", "tx9", +- "rx10", "tx10", +- "rx11", "tx11", +- "rx12", "tx12", +- "rx13", "tx13", +- "rx14", "tx14", +- "rx15", "tx15", +- "rx16", "tx16", +- "rx17", "tx17", +- "rx18", "tx18", +- "rx19", "tx19", +- "rx20", "tx20"; +- status = "disabled"; +- }; +- +- tegra_i2s1: i2s@2901000 { +- compatible = "nvidia,tegra194-i2s", +- "nvidia,tegra210-i2s"; +- reg = <0x2901000 0x100>; +- clocks = <&bpmp TEGRA194_CLK_I2S1>, +- <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; +- clock-names = "i2s", "sync_input"; +- assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; +- assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; +- assigned-clock-rates = <1536000>; +- sound-name-prefix = "I2S1"; +- status = "disabled"; +- }; +- +- tegra_i2s2: i2s@2901100 { +- compatible = "nvidia,tegra194-i2s", +- "nvidia,tegra210-i2s"; +- reg = <0x2901100 0x100>; +- clocks = <&bpmp TEGRA194_CLK_I2S2>, +- <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; +- clock-names = "i2s", "sync_input"; +- assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; +- assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; +- assigned-clock-rates = <1536000>; +- sound-name-prefix = "I2S2"; +- status = "disabled"; +- }; +- +- tegra_i2s3: i2s@2901200 { +- compatible = "nvidia,tegra194-i2s", +- "nvidia,tegra210-i2s"; +- reg = <0x2901200 0x100>; +- clocks = <&bpmp TEGRA194_CLK_I2S3>, +- <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; +- clock-names = "i2s", "sync_input"; +- assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; +- assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; +- assigned-clock-rates = <1536000>; +- sound-name-prefix = "I2S3"; +- status = "disabled"; +- }; +- +- tegra_i2s4: i2s@2901300 { +- compatible = "nvidia,tegra194-i2s", +- "nvidia,tegra210-i2s"; +- reg = <0x2901300 0x100>; +- clocks = <&bpmp TEGRA194_CLK_I2S4>, +- <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; +- clock-names = "i2s", "sync_input"; +- assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; +- assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; +- assigned-clock-rates = <1536000>; +- sound-name-prefix = "I2S4"; +- status = "disabled"; +- }; +- +- tegra_i2s5: i2s@2901400 { +- compatible = "nvidia,tegra194-i2s", +- "nvidia,tegra210-i2s"; +- reg = <0x2901400 0x100>; +- clocks = <&bpmp TEGRA194_CLK_I2S5>, +- <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; +- clock-names = "i2s", "sync_input"; +- assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; +- assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; +- assigned-clock-rates = <1536000>; +- sound-name-prefix = "I2S5"; +- status = "disabled"; +- }; +- +- tegra_i2s6: i2s@2901500 { +- compatible = "nvidia,tegra194-i2s", +- "nvidia,tegra210-i2s"; +- reg = <0x2901500 0x100>; +- clocks = <&bpmp TEGRA194_CLK_I2S6>, +- <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; +- clock-names = "i2s", "sync_input"; +- assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; +- assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; +- assigned-clock-rates = <1536000>; +- sound-name-prefix = "I2S6"; +- status = "disabled"; +- }; +- +- tegra_dmic1: dmic@2904000 { +- compatible = "nvidia,tegra194-dmic", +- "nvidia,tegra210-dmic"; +- reg = <0x2904000 0x100>; +- clocks = <&bpmp TEGRA194_CLK_DMIC1>; +- clock-names = "dmic"; +- assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; +- assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; +- assigned-clock-rates = <3072000>; +- sound-name-prefix = "DMIC1"; +- status = "disabled"; +- }; +- +- tegra_dmic2: dmic@2904100 { +- compatible = "nvidia,tegra194-dmic", +- "nvidia,tegra210-dmic"; +- reg = <0x2904100 0x100>; +- clocks = <&bpmp TEGRA194_CLK_DMIC2>; +- clock-names = "dmic"; +- assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; +- assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; +- assigned-clock-rates = <3072000>; +- sound-name-prefix = "DMIC2"; +- status = "disabled"; +- }; +- +- tegra_dmic3: dmic@2904200 { +- compatible = "nvidia,tegra194-dmic", +- "nvidia,tegra210-dmic"; +- reg = <0x2904200 0x100>; +- clocks = <&bpmp TEGRA194_CLK_DMIC3>; +- clock-names = "dmic"; +- assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; +- assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; +- assigned-clock-rates = <3072000>; +- sound-name-prefix = "DMIC3"; +- status = "disabled"; +- }; +- +- tegra_dmic4: dmic@2904300 { +- compatible = "nvidia,tegra194-dmic", +- "nvidia,tegra210-dmic"; +- reg = <0x2904300 0x100>; +- clocks = <&bpmp TEGRA194_CLK_DMIC4>; +- clock-names = "dmic"; +- assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; +- assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; +- assigned-clock-rates = <3072000>; +- sound-name-prefix = "DMIC4"; +- status = "disabled"; +- }; +- +- tegra_dspk1: dspk@2905000 { +- compatible = "nvidia,tegra194-dspk", +- "nvidia,tegra186-dspk"; +- reg = <0x2905000 0x100>; +- clocks = <&bpmp TEGRA194_CLK_DSPK1>; +- clock-names = "dspk"; +- assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; +- assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; +- assigned-clock-rates = <12288000>; +- sound-name-prefix = "DSPK1"; +- status = "disabled"; +- }; +- +- tegra_dspk2: dspk@2905100 { +- compatible = "nvidia,tegra194-dspk", +- "nvidia,tegra186-dspk"; +- reg = <0x2905100 0x100>; +- clocks = <&bpmp TEGRA194_CLK_DSPK2>; +- clock-names = "dspk"; +- assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; +- assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; +- assigned-clock-rates = <12288000>; +- sound-name-prefix = "DSPK2"; +- status = "disabled"; +- }; +- }; +- }; +- +- pinmux: pinmux@2430000 { +- compatible = "nvidia,tegra194-pinmux"; +- reg = <0x2430000 0x17000>, +- <0xc300000 0x4000>; +- +- status = "okay"; +- +- pex_rst_c5_out_state: pex_rst_c5_out { +- pex_rst { +- nvidia,pins = "pex_l5_rst_n_pgg1"; +- nvidia,schmitt = ; +- nvidia,lpdr = ; +- nvidia,enable-input = ; +- nvidia,io-hv = ; +- nvidia,tristate = ; +- nvidia,pull = ; +- }; +- }; +- +- clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { +- clkreq { +- nvidia,pins = "pex_l5_clkreq_n_pgg0"; +- nvidia,schmitt = ; +- nvidia,lpdr = ; +- nvidia,enable-input = ; +- nvidia,io-hv = ; +- nvidia,tristate = ; +- nvidia,pull = ; +- }; +- }; +- }; +- +- mc: memory-controller@2c00000 { +- compatible = "nvidia,tegra194-mc"; +- reg = <0x02c00000 0x100000>, +- <0x02b80000 0x040000>, +- <0x01700000 0x100000>; +- interrupts = ; +- #interconnect-cells = <1>; +- status = "disabled"; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, +- <0x02b80000 0x0 0x02b80000 0x0 0x040000>, +- <0x02c00000 0x0 0x02c00000 0x0 0x100000>; +- +- /* +- * Bit 39 of addresses passing through the memory +- * controller selects the XBAR format used when memory +- * is accessed. This is used to transparently access +- * memory in the XBAR format used by the discrete GPU +- * (bit 39 set) or Tegra (bit 39 clear). +- * +- * As a consequence, the operating system must ensure +- * that bit 39 is never used implicitly, for example +- * via an I/O virtual address mapping of an IOMMU. If +- * devices require access to the XBAR switch, their +- * drivers must set this bit explicitly. +- * +- * Limit the DMA range for memory clients to [38:0]. +- */ +- dma-ranges = <0x0 0x0 0x0 0x80 0x0>; +- +- emc: external-memory-controller@2c60000 { +- compatible = "nvidia,tegra194-emc"; +- reg = <0x0 0x02c60000 0x0 0x90000>, +- <0x0 0x01780000 0x0 0x80000>; +- clocks = <&bpmp TEGRA194_CLK_EMC>; +- clock-names = "emc"; +- +- #interconnect-cells = <0>; +- +- nvidia,bpmp = <&bpmp>; +- }; +- }; +- +- uarta: serial@3100000 { +- compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; +- reg = <0x03100000 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_UARTA>; +- clock-names = "serial"; +- resets = <&bpmp TEGRA194_RESET_UARTA>; +- reset-names = "serial"; +- status = "disabled"; +- }; +- +- uartb: serial@3110000 { +- compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; +- reg = <0x03110000 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_UARTB>; +- clock-names = "serial"; +- resets = <&bpmp TEGRA194_RESET_UARTB>; +- reset-names = "serial"; +- status = "disabled"; +- }; +- +- uartd: serial@3130000 { +- compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; +- reg = <0x03130000 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_UARTD>; +- clock-names = "serial"; +- resets = <&bpmp TEGRA194_RESET_UARTD>; +- reset-names = "serial"; +- status = "disabled"; +- }; +- +- uarte: serial@3140000 { +- compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; +- reg = <0x03140000 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_UARTE>; +- clock-names = "serial"; +- resets = <&bpmp TEGRA194_RESET_UARTE>; +- reset-names = "serial"; +- status = "disabled"; +- }; +- +- uartf: serial@3150000 { +- compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; +- reg = <0x03150000 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_UARTF>; +- clock-names = "serial"; +- resets = <&bpmp TEGRA194_RESET_UARTF>; +- reset-names = "serial"; +- status = "disabled"; +- }; +- +- gen1_i2c: i2c@3160000 { +- compatible = "nvidia,tegra194-i2c"; +- reg = <0x03160000 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&bpmp TEGRA194_CLK_I2C1>; +- clock-names = "div-clk"; +- resets = <&bpmp TEGRA194_RESET_I2C1>; +- reset-names = "i2c"; +- status = "disabled"; +- }; +- +- uarth: serial@3170000 { +- compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; +- reg = <0x03170000 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_UARTH>; +- clock-names = "serial"; +- resets = <&bpmp TEGRA194_RESET_UARTH>; +- reset-names = "serial"; +- status = "disabled"; +- }; +- +- cam_i2c: i2c@3180000 { +- compatible = "nvidia,tegra194-i2c"; +- reg = <0x03180000 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&bpmp TEGRA194_CLK_I2C3>; +- clock-names = "div-clk"; +- resets = <&bpmp TEGRA194_RESET_I2C3>; +- reset-names = "i2c"; +- status = "disabled"; +- }; +- +- /* shares pads with dpaux1 */ +- dp_aux_ch1_i2c: i2c@3190000 { +- compatible = "nvidia,tegra194-i2c"; +- reg = <0x03190000 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&bpmp TEGRA194_CLK_I2C4>; +- clock-names = "div-clk"; +- resets = <&bpmp TEGRA194_RESET_I2C4>; +- reset-names = "i2c"; +- pinctrl-0 = <&state_dpaux1_i2c>; +- pinctrl-1 = <&state_dpaux1_off>; +- pinctrl-names = "default", "idle"; +- status = "disabled"; +- }; +- +- /* shares pads with dpaux0 */ +- dp_aux_ch0_i2c: i2c@31b0000 { +- compatible = "nvidia,tegra194-i2c"; +- reg = <0x031b0000 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&bpmp TEGRA194_CLK_I2C6>; +- clock-names = "div-clk"; +- resets = <&bpmp TEGRA194_RESET_I2C6>; +- reset-names = "i2c"; +- pinctrl-0 = <&state_dpaux0_i2c>; +- pinctrl-1 = <&state_dpaux0_off>; +- pinctrl-names = "default", "idle"; +- status = "disabled"; +- }; +- +- /* shares pads with dpaux2 */ +- dp_aux_ch2_i2c: i2c@31c0000 { +- compatible = "nvidia,tegra194-i2c"; +- reg = <0x031c0000 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&bpmp TEGRA194_CLK_I2C7>; +- clock-names = "div-clk"; +- resets = <&bpmp TEGRA194_RESET_I2C7>; +- reset-names = "i2c"; +- pinctrl-0 = <&state_dpaux2_i2c>; +- pinctrl-1 = <&state_dpaux2_off>; +- pinctrl-names = "default", "idle"; +- status = "disabled"; +- }; +- +- /* shares pads with dpaux3 */ +- dp_aux_ch3_i2c: i2c@31e0000 { +- compatible = "nvidia,tegra194-i2c"; +- reg = <0x031e0000 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&bpmp TEGRA194_CLK_I2C9>; +- clock-names = "div-clk"; +- resets = <&bpmp TEGRA194_RESET_I2C9>; +- reset-names = "i2c"; +- pinctrl-0 = <&state_dpaux3_i2c>; +- pinctrl-1 = <&state_dpaux3_off>; +- pinctrl-names = "default", "idle"; +- status = "disabled"; +- }; +- +- spi@3270000 { +- compatible = "nvidia,tegra194-qspi"; +- reg = <0x3270000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&bpmp TEGRA194_CLK_QSPI0>, +- <&bpmp TEGRA194_CLK_QSPI0_PM>; +- clock-names = "qspi", "qspi_out"; +- resets = <&bpmp TEGRA194_RESET_QSPI0>; +- reset-names = "qspi"; +- status = "disabled"; +- }; +- +- spi@3300000 { +- compatible = "nvidia,tegra194-qspi"; +- reg = <0x3300000 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&bpmp TEGRA194_CLK_QSPI1>, +- <&bpmp TEGRA194_CLK_QSPI1_PM>; +- clock-names = "qspi", "qspi_out"; +- resets = <&bpmp TEGRA194_RESET_QSPI1>; +- reset-names = "qspi"; +- status = "disabled"; +- }; +- +- pwm1: pwm@3280000 { +- compatible = "nvidia,tegra194-pwm", +- "nvidia,tegra186-pwm"; +- reg = <0x3280000 0x10000>; +- clocks = <&bpmp TEGRA194_CLK_PWM1>; +- clock-names = "pwm"; +- resets = <&bpmp TEGRA194_RESET_PWM1>; +- reset-names = "pwm"; +- status = "disabled"; +- #pwm-cells = <2>; +- }; +- +- pwm2: pwm@3290000 { +- compatible = "nvidia,tegra194-pwm", +- "nvidia,tegra186-pwm"; +- reg = <0x3290000 0x10000>; +- clocks = <&bpmp TEGRA194_CLK_PWM2>; +- clock-names = "pwm"; +- resets = <&bpmp TEGRA194_RESET_PWM2>; +- reset-names = "pwm"; +- status = "disabled"; +- #pwm-cells = <2>; +- }; +- +- pwm3: pwm@32a0000 { +- compatible = "nvidia,tegra194-pwm", +- "nvidia,tegra186-pwm"; +- reg = <0x32a0000 0x10000>; +- clocks = <&bpmp TEGRA194_CLK_PWM3>; +- clock-names = "pwm"; +- resets = <&bpmp TEGRA194_RESET_PWM3>; +- reset-names = "pwm"; +- status = "disabled"; +- #pwm-cells = <2>; +- }; +- +- pwm5: pwm@32c0000 { +- compatible = "nvidia,tegra194-pwm", +- "nvidia,tegra186-pwm"; +- reg = <0x32c0000 0x10000>; +- clocks = <&bpmp TEGRA194_CLK_PWM5>; +- clock-names = "pwm"; +- resets = <&bpmp TEGRA194_RESET_PWM5>; +- reset-names = "pwm"; +- status = "disabled"; +- #pwm-cells = <2>; +- }; +- +- pwm6: pwm@32d0000 { +- compatible = "nvidia,tegra194-pwm", +- "nvidia,tegra186-pwm"; +- reg = <0x32d0000 0x10000>; +- clocks = <&bpmp TEGRA194_CLK_PWM6>; +- clock-names = "pwm"; +- resets = <&bpmp TEGRA194_RESET_PWM6>; +- reset-names = "pwm"; +- status = "disabled"; +- #pwm-cells = <2>; +- }; +- +- pwm7: pwm@32e0000 { +- compatible = "nvidia,tegra194-pwm", +- "nvidia,tegra186-pwm"; +- reg = <0x32e0000 0x10000>; +- clocks = <&bpmp TEGRA194_CLK_PWM7>; +- clock-names = "pwm"; +- resets = <&bpmp TEGRA194_RESET_PWM7>; +- reset-names = "pwm"; +- status = "disabled"; +- #pwm-cells = <2>; +- }; +- +- pwm8: pwm@32f0000 { +- compatible = "nvidia,tegra194-pwm", +- "nvidia,tegra186-pwm"; +- reg = <0x32f0000 0x10000>; +- clocks = <&bpmp TEGRA194_CLK_PWM8>; +- clock-names = "pwm"; +- resets = <&bpmp TEGRA194_RESET_PWM8>; +- reset-names = "pwm"; +- status = "disabled"; +- #pwm-cells = <2>; +- }; +- +- sdmmc1: mmc@3400000 { +- compatible = "nvidia,tegra194-sdhci"; +- reg = <0x03400000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_SDMMC1>, +- <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; +- clock-names = "sdhci", "tmclk"; +- resets = <&bpmp TEGRA194_RESET_SDMMC1>; +- reset-names = "sdhci"; +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA194_SID_SDMMC1>; +- nvidia,pad-autocal-pull-up-offset-3v3-timeout = +- <0x07>; +- nvidia,pad-autocal-pull-down-offset-3v3-timeout = +- <0x07>; +- nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; +- nvidia,pad-autocal-pull-down-offset-1v8-timeout = +- <0x07>; +- nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; +- nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; +- nvidia,default-tap = <0x9>; +- nvidia,default-trim = <0x5>; +- status = "disabled"; +- }; +- +- sdmmc3: mmc@3440000 { +- compatible = "nvidia,tegra194-sdhci"; +- reg = <0x03440000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_SDMMC3>, +- <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; +- clock-names = "sdhci", "tmclk"; +- resets = <&bpmp TEGRA194_RESET_SDMMC3>; +- reset-names = "sdhci"; +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA194_SID_SDMMC3>; +- nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; +- nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; +- nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; +- nvidia,pad-autocal-pull-down-offset-3v3-timeout = +- <0x07>; +- nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; +- nvidia,pad-autocal-pull-down-offset-1v8-timeout = +- <0x07>; +- nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; +- nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; +- nvidia,default-tap = <0x9>; +- nvidia,default-trim = <0x5>; +- status = "disabled"; +- }; +- +- sdmmc4: mmc@3460000 { +- compatible = "nvidia,tegra194-sdhci"; +- reg = <0x03460000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_SDMMC4>, +- <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; +- clock-names = "sdhci", "tmclk"; +- assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, +- <&bpmp TEGRA194_CLK_PLLC4>; +- assigned-clock-parents = +- <&bpmp TEGRA194_CLK_PLLC4>; +- resets = <&bpmp TEGRA194_RESET_SDMMC4>; +- reset-names = "sdhci"; +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA194_SID_SDMMC4>; +- nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; +- nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; +- nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; +- nvidia,pad-autocal-pull-down-offset-1v8-timeout = +- <0x0a>; +- nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; +- nvidia,pad-autocal-pull-down-offset-3v3-timeout = +- <0x0a>; +- nvidia,default-tap = <0x8>; +- nvidia,default-trim = <0x14>; +- nvidia,dqs-trim = <40>; +- supports-cqe; +- status = "disabled"; +- }; +- +- hda@3510000 { +- compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; +- reg = <0x3510000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_HDA>, +- <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, +- <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; +- clock-names = "hda", "hda2hdmi", "hda2codec_2x"; +- resets = <&bpmp TEGRA194_RESET_HDA>, +- <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; +- reset-names = "hda", "hda2hdmi"; +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA194_SID_HDA>; +- status = "disabled"; +- }; +- +- xusb_padctl: padctl@3520000 { +- compatible = "nvidia,tegra194-xusb-padctl"; +- reg = <0x03520000 0x1000>, +- <0x03540000 0x1000>; +- reg-names = "padctl", "ao"; +- interrupts = ; +- +- resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; +- reset-names = "padctl"; +- +- status = "disabled"; +- +- pads { +- usb2 { +- clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; +- clock-names = "trk"; +- +- lanes { +- usb2-0 { +- nvidia,function = "xusb"; +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- usb2-1 { +- nvidia,function = "xusb"; +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- usb2-2 { +- nvidia,function = "xusb"; +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- usb2-3 { +- nvidia,function = "xusb"; +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- usb3 { +- lanes { +- usb3-0 { +- nvidia,function = "xusb"; +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- usb3-1 { +- nvidia,function = "xusb"; +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- usb3-2 { +- nvidia,function = "xusb"; +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- usb3-3 { +- nvidia,function = "xusb"; +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- }; +- }; +- +- ports { +- usb2-0 { +- status = "disabled"; +- }; +- +- usb2-1 { +- status = "disabled"; +- }; +- +- usb2-2 { +- status = "disabled"; +- }; +- +- usb2-3 { +- status = "disabled"; +- }; +- +- usb3-0 { +- status = "disabled"; +- }; +- +- usb3-1 { +- status = "disabled"; +- }; +- +- usb3-2 { +- status = "disabled"; +- }; +- +- usb3-3 { +- status = "disabled"; +- }; +- }; +- }; +- +- usb@3550000 { +- compatible = "nvidia,tegra194-xudc"; +- reg = <0x03550000 0x8000>, +- <0x03558000 0x1000>; +- reg-names = "base", "fpci"; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, +- <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, +- <&bpmp TEGRA194_CLK_XUSB_SS>, +- <&bpmp TEGRA194_CLK_XUSB_FS>; +- clock-names = "dev", "ss", "ss_src", "fs_src"; +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA194_SID_XUSB_DEV>; +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, +- <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; +- power-domain-names = "dev", "ss"; +- nvidia,xusb-padctl = <&xusb_padctl>; +- status = "disabled"; +- }; +- +- usb@3610000 { +- compatible = "nvidia,tegra194-xusb"; +- reg = <0x03610000 0x40000>, +- <0x03600000 0x10000>; +- reg-names = "hcd", "fpci"; +- +- interrupts = , +- ; +- +- clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, +- <&bpmp TEGRA194_CLK_XUSB_FALCON>, +- <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, +- <&bpmp TEGRA194_CLK_XUSB_SS>, +- <&bpmp TEGRA194_CLK_CLK_M>, +- <&bpmp TEGRA194_CLK_XUSB_FS>, +- <&bpmp TEGRA194_CLK_UTMIPLL>, +- <&bpmp TEGRA194_CLK_CLK_M>, +- <&bpmp TEGRA194_CLK_PLLE>; +- clock-names = "xusb_host", "xusb_falcon_src", +- "xusb_ss", "xusb_ss_src", "xusb_hs_src", +- "xusb_fs_src", "pll_u_480m", "clk_m", +- "pll_e"; +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA194_SID_XUSB_HOST>; +- +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, +- <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; +- power-domain-names = "xusb_host", "xusb_ss"; +- +- nvidia,xusb-padctl = <&xusb_padctl>; +- status = "disabled"; +- }; +- +- fuse@3820000 { +- compatible = "nvidia,tegra194-efuse"; +- reg = <0x03820000 0x10000>; +- clocks = <&bpmp TEGRA194_CLK_FUSE>; +- clock-names = "fuse"; +- }; +- +- gic: interrupt-controller@3881000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x03881000 0x1000>, +- <0x03882000 0x2000>, +- <0x03884000 0x2000>, +- <0x03886000 0x2000>; +- interrupts = ; +- interrupt-parent = <&gic>; +- }; +- +- cec@3960000 { +- compatible = "nvidia,tegra194-cec"; +- reg = <0x03960000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_CEC>; +- clock-names = "cec"; +- status = "disabled"; +- }; +- +- hsp_top0: hsp@3c00000 { +- compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; +- reg = <0x03c00000 0xa0000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "doorbell", "shared0", "shared1", "shared2", +- "shared3", "shared4", "shared5", "shared6", +- "shared7"; +- #mbox-cells = <2>; +- }; +- +- p2u_hsio_0: phy@3e10000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03e10000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- p2u_hsio_1: phy@3e20000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03e20000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- p2u_hsio_2: phy@3e30000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03e30000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- p2u_hsio_3: phy@3e40000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03e40000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- p2u_hsio_4: phy@3e50000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03e50000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- p2u_hsio_5: phy@3e60000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03e60000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- p2u_hsio_6: phy@3e70000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03e70000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- p2u_hsio_7: phy@3e80000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03e80000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- p2u_hsio_8: phy@3e90000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03e90000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- p2u_hsio_9: phy@3ea0000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03ea0000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- p2u_nvhs_0: phy@3eb0000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03eb0000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- p2u_nvhs_1: phy@3ec0000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03ec0000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- p2u_nvhs_2: phy@3ed0000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03ed0000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- p2u_nvhs_3: phy@3ee0000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03ee0000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- p2u_nvhs_4: phy@3ef0000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03ef0000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- p2u_nvhs_5: phy@3f00000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03f00000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- p2u_nvhs_6: phy@3f10000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03f10000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- p2u_nvhs_7: phy@3f20000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03f20000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- p2u_hsio_10: phy@3f30000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03f30000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- p2u_hsio_11: phy@3f40000 { +- compatible = "nvidia,tegra194-p2u"; +- reg = <0x03f40000 0x10000>; +- reg-names = "ctl"; +- +- #phy-cells = <0>; +- }; +- +- hsp_aon: hsp@c150000 { +- compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; +- reg = <0x0c150000 0x90000>; +- interrupts = , +- , +- , +- ; +- /* +- * Shared interrupt 0 is routed only to AON/SPE, so +- * we only have 4 shared interrupts for the CCPLEX. +- */ +- interrupt-names = "shared1", "shared2", "shared3", "shared4"; +- #mbox-cells = <2>; +- }; +- +- gen2_i2c: i2c@c240000 { +- compatible = "nvidia,tegra194-i2c"; +- reg = <0x0c240000 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&bpmp TEGRA194_CLK_I2C2>; +- clock-names = "div-clk"; +- resets = <&bpmp TEGRA194_RESET_I2C2>; +- reset-names = "i2c"; +- status = "disabled"; +- }; +- +- gen8_i2c: i2c@c250000 { +- compatible = "nvidia,tegra194-i2c"; +- reg = <0x0c250000 0x10000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&bpmp TEGRA194_CLK_I2C8>; +- clock-names = "div-clk"; +- resets = <&bpmp TEGRA194_RESET_I2C8>; +- reset-names = "i2c"; +- status = "disabled"; +- }; +- +- uartc: serial@c280000 { +- compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; +- reg = <0x0c280000 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_UARTC>; +- clock-names = "serial"; +- resets = <&bpmp TEGRA194_RESET_UARTC>; +- reset-names = "serial"; +- status = "disabled"; +- }; +- +- uartg: serial@c290000 { +- compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; +- reg = <0x0c290000 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_UARTG>; +- clock-names = "serial"; +- resets = <&bpmp TEGRA194_RESET_UARTG>; +- reset-names = "serial"; +- status = "disabled"; +- }; +- +- rtc: rtc@c2a0000 { +- compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; +- reg = <0x0c2a0000 0x10000>; +- interrupt-parent = <&pmc>; +- interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&bpmp TEGRA194_CLK_CLK_32K>; +- clock-names = "rtc"; +- status = "disabled"; +- }; +- +- gpio_aon: gpio@c2f0000 { +- compatible = "nvidia,tegra194-gpio-aon"; +- reg-names = "security", "gpio"; +- reg = <0xc2f0000 0x1000>, +- <0xc2f1000 0x1000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pwm4: pwm@c340000 { +- compatible = "nvidia,tegra194-pwm", +- "nvidia,tegra186-pwm"; +- reg = <0xc340000 0x10000>; +- clocks = <&bpmp TEGRA194_CLK_PWM4>; +- clock-names = "pwm"; +- resets = <&bpmp TEGRA194_RESET_PWM4>; +- reset-names = "pwm"; +- status = "disabled"; +- #pwm-cells = <2>; +- }; +- +- pmc: pmc@c360000 { +- compatible = "nvidia,tegra194-pmc"; +- reg = <0x0c360000 0x10000>, +- <0x0c370000 0x10000>, +- <0x0c380000 0x10000>, +- <0x0c390000 0x10000>, +- <0x0c3a0000 0x10000>; +- reg-names = "pmc", "wake", "aotag", "scratch", "misc"; +- +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- smmu: iommu@12000000 { +- compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; +- reg = <0x12000000 0x800000>, +- <0x11000000 0x800000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- stream-match-mask = <0x7f80>; +- #global-interrupts = <2>; +- #iommu-cells = <1>; +- +- nvidia,memory-controller = <&mc>; +- status = "okay"; +- }; +- +- host1x@13e00000 { +- compatible = "nvidia,tegra194-host1x"; +- reg = <0x13e00000 0x10000>, +- <0x13e10000 0x10000>; +- reg-names = "hypervisor", "vm"; +- interrupts = , +- ; +- interrupt-names = "syncpt", "host1x"; +- clocks = <&bpmp TEGRA194_CLK_HOST1X>; +- clock-names = "host1x"; +- resets = <&bpmp TEGRA194_RESET_HOST1X>; +- reset-names = "host1x"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0x15000000 0x15000000 0x01000000>; +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; +- interconnect-names = "dma-mem"; +- iommus = <&smmu TEGRA194_SID_HOST1X>; +- +- display-hub@15200000 { +- compatible = "nvidia,tegra194-display"; +- reg = <0x15200000 0x00040000>; +- resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, +- <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, +- <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, +- <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, +- <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, +- <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, +- <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; +- reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", +- "wgrp3", "wgrp4", "wgrp5"; +- clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, +- <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; +- clock-names = "disp", "hub"; +- status = "disabled"; +- +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0x15200000 0x15200000 0x40000>; +- +- display@15200000 { +- compatible = "nvidia,tegra194-dc"; +- reg = <0x15200000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; +- clock-names = "dc"; +- resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; +- reset-names = "dc"; +- +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; +- interconnect-names = "dma-mem", "read-1"; +- +- nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; +- nvidia,head = <0>; +- }; +- +- display@15210000 { +- compatible = "nvidia,tegra194-dc"; +- reg = <0x15210000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; +- clock-names = "dc"; +- resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; +- reset-names = "dc"; +- +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; +- interconnect-names = "dma-mem", "read-1"; +- +- nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; +- nvidia,head = <1>; +- }; +- +- display@15220000 { +- compatible = "nvidia,tegra194-dc"; +- reg = <0x15220000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; +- clock-names = "dc"; +- resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; +- reset-names = "dc"; +- +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; +- interconnect-names = "dma-mem", "read-1"; +- +- nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; +- nvidia,head = <2>; +- }; +- +- display@15230000 { +- compatible = "nvidia,tegra194-dc"; +- reg = <0x15230000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; +- clock-names = "dc"; +- resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; +- reset-names = "dc"; +- +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; +- interconnect-names = "dma-mem", "read-1"; +- +- nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; +- nvidia,head = <3>; +- }; +- }; +- +- vic@15340000 { +- compatible = "nvidia,tegra194-vic"; +- reg = <0x15340000 0x00040000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_VIC>; +- clock-names = "vic"; +- resets = <&bpmp TEGRA194_RESET_VIC>; +- reset-names = "vic"; +- +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA194_SID_VIC>; +- }; +- +- dpaux0: dpaux@155c0000 { +- compatible = "nvidia,tegra194-dpaux"; +- reg = <0x155c0000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_DPAUX>, +- <&bpmp TEGRA194_CLK_PLLDP>; +- clock-names = "dpaux", "parent"; +- resets = <&bpmp TEGRA194_RESET_DPAUX>; +- reset-names = "dpaux"; +- status = "disabled"; +- +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; +- +- state_dpaux0_aux: pinmux-aux { +- groups = "dpaux-io"; +- function = "aux"; +- }; +- +- state_dpaux0_i2c: pinmux-i2c { +- groups = "dpaux-io"; +- function = "i2c"; +- }; +- +- state_dpaux0_off: pinmux-off { +- groups = "dpaux-io"; +- function = "off"; +- }; +- +- i2c-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- dpaux1: dpaux@155d0000 { +- compatible = "nvidia,tegra194-dpaux"; +- reg = <0x155d0000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_DPAUX1>, +- <&bpmp TEGRA194_CLK_PLLDP>; +- clock-names = "dpaux", "parent"; +- resets = <&bpmp TEGRA194_RESET_DPAUX1>; +- reset-names = "dpaux"; +- status = "disabled"; +- +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; +- +- state_dpaux1_aux: pinmux-aux { +- groups = "dpaux-io"; +- function = "aux"; +- }; +- +- state_dpaux1_i2c: pinmux-i2c { +- groups = "dpaux-io"; +- function = "i2c"; +- }; +- +- state_dpaux1_off: pinmux-off { +- groups = "dpaux-io"; +- function = "off"; +- }; +- +- i2c-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- dpaux2: dpaux@155e0000 { +- compatible = "nvidia,tegra194-dpaux"; +- reg = <0x155e0000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_DPAUX2>, +- <&bpmp TEGRA194_CLK_PLLDP>; +- clock-names = "dpaux", "parent"; +- resets = <&bpmp TEGRA194_RESET_DPAUX2>; +- reset-names = "dpaux"; +- status = "disabled"; +- +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; +- +- state_dpaux2_aux: pinmux-aux { +- groups = "dpaux-io"; +- function = "aux"; +- }; +- +- state_dpaux2_i2c: pinmux-i2c { +- groups = "dpaux-io"; +- function = "i2c"; +- }; +- +- state_dpaux2_off: pinmux-off { +- groups = "dpaux-io"; +- function = "off"; +- }; +- +- i2c-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- dpaux3: dpaux@155f0000 { +- compatible = "nvidia,tegra194-dpaux"; +- reg = <0x155f0000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_DPAUX3>, +- <&bpmp TEGRA194_CLK_PLLDP>; +- clock-names = "dpaux", "parent"; +- resets = <&bpmp TEGRA194_RESET_DPAUX3>; +- reset-names = "dpaux"; +- status = "disabled"; +- +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; +- +- state_dpaux3_aux: pinmux-aux { +- groups = "dpaux-io"; +- function = "aux"; +- }; +- +- state_dpaux3_i2c: pinmux-i2c { +- groups = "dpaux-io"; +- function = "i2c"; +- }; +- +- state_dpaux3_off: pinmux-off { +- groups = "dpaux-io"; +- function = "off"; +- }; +- +- i2c-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- sor0: sor@15b00000 { +- compatible = "nvidia,tegra194-sor"; +- reg = <0x15b00000 0x40000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, +- <&bpmp TEGRA194_CLK_SOR0_OUT>, +- <&bpmp TEGRA194_CLK_PLLD>, +- <&bpmp TEGRA194_CLK_PLLDP>, +- <&bpmp TEGRA194_CLK_SOR_SAFE>, +- <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; +- clock-names = "sor", "out", "parent", "dp", "safe", +- "pad"; +- resets = <&bpmp TEGRA194_RESET_SOR0>; +- reset-names = "sor"; +- pinctrl-0 = <&state_dpaux0_aux>; +- pinctrl-1 = <&state_dpaux0_i2c>; +- pinctrl-2 = <&state_dpaux0_off>; +- pinctrl-names = "aux", "i2c", "off"; +- status = "disabled"; +- +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; +- nvidia,interface = <0>; +- }; +- +- sor1: sor@15b40000 { +- compatible = "nvidia,tegra194-sor"; +- reg = <0x15b40000 0x40000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, +- <&bpmp TEGRA194_CLK_SOR1_OUT>, +- <&bpmp TEGRA194_CLK_PLLD2>, +- <&bpmp TEGRA194_CLK_PLLDP>, +- <&bpmp TEGRA194_CLK_SOR_SAFE>, +- <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; +- clock-names = "sor", "out", "parent", "dp", "safe", +- "pad"; +- resets = <&bpmp TEGRA194_RESET_SOR1>; +- reset-names = "sor"; +- pinctrl-0 = <&state_dpaux1_aux>; +- pinctrl-1 = <&state_dpaux1_i2c>; +- pinctrl-2 = <&state_dpaux1_off>; +- pinctrl-names = "aux", "i2c", "off"; +- status = "disabled"; +- +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; +- nvidia,interface = <1>; +- }; +- +- sor2: sor@15b80000 { +- compatible = "nvidia,tegra194-sor"; +- reg = <0x15b80000 0x40000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, +- <&bpmp TEGRA194_CLK_SOR2_OUT>, +- <&bpmp TEGRA194_CLK_PLLD3>, +- <&bpmp TEGRA194_CLK_PLLDP>, +- <&bpmp TEGRA194_CLK_SOR_SAFE>, +- <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; +- clock-names = "sor", "out", "parent", "dp", "safe", +- "pad"; +- resets = <&bpmp TEGRA194_RESET_SOR2>; +- reset-names = "sor"; +- pinctrl-0 = <&state_dpaux2_aux>; +- pinctrl-1 = <&state_dpaux2_i2c>; +- pinctrl-2 = <&state_dpaux2_off>; +- pinctrl-names = "aux", "i2c", "off"; +- status = "disabled"; +- +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; +- nvidia,interface = <2>; +- }; +- +- sor3: sor@15bc0000 { +- compatible = "nvidia,tegra194-sor"; +- reg = <0x15bc0000 0x40000>; +- interrupts = ; +- clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, +- <&bpmp TEGRA194_CLK_SOR3_OUT>, +- <&bpmp TEGRA194_CLK_PLLD4>, +- <&bpmp TEGRA194_CLK_PLLDP>, +- <&bpmp TEGRA194_CLK_SOR_SAFE>, +- <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; +- clock-names = "sor", "out", "parent", "dp", "safe", +- "pad"; +- resets = <&bpmp TEGRA194_RESET_SOR3>; +- reset-names = "sor"; +- pinctrl-0 = <&state_dpaux3_aux>; +- pinctrl-1 = <&state_dpaux3_i2c>; +- pinctrl-2 = <&state_dpaux3_off>; +- pinctrl-names = "aux", "i2c", "off"; +- status = "disabled"; +- +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; +- nvidia,interface = <3>; +- }; +- }; +- +- gpu@17000000 { +- compatible = "nvidia,gv11b"; +- reg = <0x17000000 0x1000000>, +- <0x18000000 0x1000000>; +- interrupts = , +- ; +- interrupt-names = "stall", "nonstall"; +- clocks = <&bpmp TEGRA194_CLK_GPCCLK>, +- <&bpmp TEGRA194_CLK_GPU_PWR>, +- <&bpmp TEGRA194_CLK_FUSE>; +- clock-names = "gpu", "pwr", "fuse"; +- resets = <&bpmp TEGRA194_RESET_GPU>; +- reset-names = "gpu"; +- dma-coherent; +- +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; +- interconnect-names = "dma-mem", "read-0-hp", "write-0", +- "read-1", "read-1-hp", "write-1", +- "read-2", "read-2-hp", "write-2", +- "read-3", "read-3-hp", "write-3"; +- }; +- }; +- +- pcie@14100000 { +- compatible = "nvidia,tegra194-pcie"; +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; +- reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ +- <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ +- <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ +- <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ +- reg-names = "appl", "config", "atu_dma", "dbi"; +- +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- num-lanes = <1>; +- num-viewport = <8>; +- linux,pci-domain = <1>; +- +- clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; +- clock-names = "core"; +- +- resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, +- <&bpmp TEGRA194_RESET_PEX0_CORE_1>; +- reset-names = "apb", "core"; +- +- interrupts = , /* controller interrupt */ +- ; /* MSI interrupt */ +- interrupt-names = "intr", "msi"; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; +- +- nvidia,bpmp = <&bpmp 1>; +- +- nvidia,aspm-cmrt-us = <60>; +- nvidia,aspm-pwr-on-t-us = <20>; +- nvidia,aspm-l0s-entrance-latency-us = <3>; +- +- bus-range = <0x0 0xff>; +- +- ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ +- <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ +- <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ +- +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA194_SID_PCIE1>; +- iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; +- iommu-map-mask = <0x0>; +- dma-coherent; +- }; +- +- pcie@14120000 { +- compatible = "nvidia,tegra194-pcie"; +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; +- reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ +- <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ +- <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ +- <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ +- reg-names = "appl", "config", "atu_dma", "dbi"; +- +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- num-lanes = <1>; +- num-viewport = <8>; +- linux,pci-domain = <2>; +- +- clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; +- clock-names = "core"; +- +- resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, +- <&bpmp TEGRA194_RESET_PEX0_CORE_2>; +- reset-names = "apb", "core"; +- +- interrupts = , /* controller interrupt */ +- ; /* MSI interrupt */ +- interrupt-names = "intr", "msi"; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; +- +- nvidia,bpmp = <&bpmp 2>; +- +- nvidia,aspm-cmrt-us = <60>; +- nvidia,aspm-pwr-on-t-us = <20>; +- nvidia,aspm-l0s-entrance-latency-us = <3>; +- +- bus-range = <0x0 0xff>; +- +- ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ +- <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ +- <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ +- +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA194_SID_PCIE2>; +- iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; +- iommu-map-mask = <0x0>; +- dma-coherent; +- }; +- +- pcie@14140000 { +- compatible = "nvidia,tegra194-pcie"; +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; +- reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ +- <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ +- <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ +- <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ +- reg-names = "appl", "config", "atu_dma", "dbi"; +- +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- num-lanes = <1>; +- num-viewport = <8>; +- linux,pci-domain = <3>; +- +- clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; +- clock-names = "core"; +- +- resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, +- <&bpmp TEGRA194_RESET_PEX0_CORE_3>; +- reset-names = "apb", "core"; +- +- interrupts = , /* controller interrupt */ +- ; /* MSI interrupt */ +- interrupt-names = "intr", "msi"; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; +- +- nvidia,bpmp = <&bpmp 3>; +- +- nvidia,aspm-cmrt-us = <60>; +- nvidia,aspm-pwr-on-t-us = <20>; +- nvidia,aspm-l0s-entrance-latency-us = <3>; +- +- bus-range = <0x0 0xff>; +- +- ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ +- <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ +- <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ +- +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA194_SID_PCIE3>; +- iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; +- iommu-map-mask = <0x0>; +- dma-coherent; +- }; +- +- pcie@14160000 { +- compatible = "nvidia,tegra194-pcie"; +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; +- reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ +- <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ +- <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ +- <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ +- reg-names = "appl", "config", "atu_dma", "dbi"; +- +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- num-lanes = <4>; +- num-viewport = <8>; +- linux,pci-domain = <4>; +- +- clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; +- clock-names = "core"; +- +- resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, +- <&bpmp TEGRA194_RESET_PEX0_CORE_4>; +- reset-names = "apb", "core"; +- +- interrupts = , /* controller interrupt */ +- ; /* MSI interrupt */ +- interrupt-names = "intr", "msi"; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; +- +- nvidia,bpmp = <&bpmp 4>; +- +- nvidia,aspm-cmrt-us = <60>; +- nvidia,aspm-pwr-on-t-us = <20>; +- nvidia,aspm-l0s-entrance-latency-us = <3>; +- +- bus-range = <0x0 0xff>; +- +- ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ +- <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ +- <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ +- +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA194_SID_PCIE4>; +- iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; +- iommu-map-mask = <0x0>; +- dma-coherent; +- }; +- +- pcie@14180000 { +- compatible = "nvidia,tegra194-pcie"; +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; +- reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ +- <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ +- <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ +- <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ +- reg-names = "appl", "config", "atu_dma", "dbi"; +- +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- num-lanes = <8>; +- num-viewport = <8>; +- linux,pci-domain = <0>; +- +- clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; +- clock-names = "core"; +- +- resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, +- <&bpmp TEGRA194_RESET_PEX0_CORE_0>; +- reset-names = "apb", "core"; +- +- interrupts = , /* controller interrupt */ +- ; /* MSI interrupt */ +- interrupt-names = "intr", "msi"; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; +- +- nvidia,bpmp = <&bpmp 0>; +- +- nvidia,aspm-cmrt-us = <60>; +- nvidia,aspm-pwr-on-t-us = <20>; +- nvidia,aspm-l0s-entrance-latency-us = <3>; +- +- bus-range = <0x0 0xff>; +- +- ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ +- <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ +- <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ +- +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA194_SID_PCIE0>; +- iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; +- iommu-map-mask = <0x0>; +- dma-coherent; +- }; +- +- pcie@141a0000 { +- compatible = "nvidia,tegra194-pcie"; +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; +- reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ +- <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ +- <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ +- <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ +- reg-names = "appl", "config", "atu_dma", "dbi"; +- +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- num-lanes = <8>; +- num-viewport = <8>; +- linux,pci-domain = <5>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; +- +- clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, +- <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; +- clock-names = "core", "core_m"; +- +- resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, +- <&bpmp TEGRA194_RESET_PEX1_CORE_5>; +- reset-names = "apb", "core"; +- +- interrupts = , /* controller interrupt */ +- ; /* MSI interrupt */ +- interrupt-names = "intr", "msi"; +- +- nvidia,bpmp = <&bpmp 5>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; +- +- nvidia,aspm-cmrt-us = <60>; +- nvidia,aspm-pwr-on-t-us = <20>; +- nvidia,aspm-l0s-entrance-latency-us = <3>; +- +- bus-range = <0x0 0xff>; +- +- ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ +- <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ +- <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ +- +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA194_SID_PCIE5>; +- iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; +- iommu-map-mask = <0x0>; +- dma-coherent; +- }; +- +- pcie_ep@14160000 { +- compatible = "nvidia,tegra194-pcie-ep"; +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; +- reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ +- <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ +- <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ +- <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ +- reg-names = "appl", "atu_dma", "dbi", "addr_space"; +- +- status = "disabled"; +- +- num-lanes = <4>; +- num-ib-windows = <2>; +- num-ob-windows = <8>; +- +- clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; +- clock-names = "core"; +- +- resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, +- <&bpmp TEGRA194_RESET_PEX0_CORE_4>; +- reset-names = "apb", "core"; +- +- interrupts = ; /* controller interrupt */ +- interrupt-names = "intr"; +- +- nvidia,bpmp = <&bpmp 4>; +- +- nvidia,aspm-cmrt-us = <60>; +- nvidia,aspm-pwr-on-t-us = <20>; +- nvidia,aspm-l0s-entrance-latency-us = <3>; +- +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA194_SID_PCIE4>; +- iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; +- iommu-map-mask = <0x0>; +- dma-coherent; +- }; +- +- pcie_ep@14180000 { +- compatible = "nvidia,tegra194-pcie-ep"; +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; +- reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ +- <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ +- <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ +- <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ +- reg-names = "appl", "atu_dma", "dbi", "addr_space"; +- +- status = "disabled"; +- +- num-lanes = <8>; +- num-ib-windows = <2>; +- num-ob-windows = <8>; +- +- clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; +- clock-names = "core"; +- +- resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, +- <&bpmp TEGRA194_RESET_PEX0_CORE_0>; +- reset-names = "apb", "core"; +- +- interrupts = ; /* controller interrupt */ +- interrupt-names = "intr"; +- +- nvidia,bpmp = <&bpmp 0>; +- +- nvidia,aspm-cmrt-us = <60>; +- nvidia,aspm-pwr-on-t-us = <20>; +- nvidia,aspm-l0s-entrance-latency-us = <3>; +- +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA194_SID_PCIE0>; +- iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; +- iommu-map-mask = <0x0>; +- dma-coherent; +- }; +- +- pcie_ep@141a0000 { +- compatible = "nvidia,tegra194-pcie-ep"; +- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; +- reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ +- <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ +- <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ +- <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ +- reg-names = "appl", "atu_dma", "dbi", "addr_space"; +- +- status = "disabled"; +- +- num-lanes = <8>; +- num-ib-windows = <2>; +- num-ob-windows = <8>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&clkreq_c5_bi_dir_state>; +- +- clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; +- clock-names = "core"; +- +- resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, +- <&bpmp TEGRA194_RESET_PEX1_CORE_5>; +- reset-names = "apb", "core"; +- +- interrupts = ; /* controller interrupt */ +- interrupt-names = "intr"; +- +- nvidia,bpmp = <&bpmp 5>; +- +- nvidia,aspm-cmrt-us = <60>; +- nvidia,aspm-pwr-on-t-us = <20>; +- nvidia,aspm-l0s-entrance-latency-us = <3>; +- +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA194_SID_PCIE5>; +- iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; +- iommu-map-mask = <0x0>; +- dma-coherent; +- }; +- +- sram@40000000 { +- compatible = "nvidia,tegra194-sysram", "mmio-sram"; +- reg = <0x0 0x40000000 0x0 0x50000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x40000000 0x50000>; +- +- cpu_bpmp_tx: sram@4e000 { +- reg = <0x4e000 0x1000>; +- label = "cpu-bpmp-tx"; +- pool; +- }; +- +- cpu_bpmp_rx: sram@4f000 { +- reg = <0x4f000 0x1000>; +- label = "cpu-bpmp-rx"; +- pool; +- }; +- }; +- +- bpmp: bpmp { +- compatible = "nvidia,tegra186-bpmp"; +- mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB +- TEGRA_HSP_DB_MASTER_BPMP>; +- shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; +- interconnect-names = "read", "write", "dma-mem", "dma-write"; +- iommus = <&smmu TEGRA194_SID_BPMP>; +- +- bpmp_i2c: i2c { +- compatible = "nvidia,tegra186-bpmp-i2c"; +- nvidia,bpmp-bus-id = <5>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- bpmp_thermal: thermal { +- compatible = "nvidia,tegra186-bpmp-thermal"; +- #thermal-sensor-cells = <1>; +- }; +- }; +- +- cpus { +- compatible = "nvidia,tegra194-ccplex"; +- nvidia,bpmp = <&bpmp>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0_0: cpu@0 { +- compatible = "nvidia,tegra194-carmel"; +- device_type = "cpu"; +- reg = <0x000>; +- enable-method = "psci"; +- i-cache-size = <131072>; +- i-cache-line-size = <64>; +- i-cache-sets = <512>; +- d-cache-size = <65536>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2c_0>; +- }; +- +- cpu0_1: cpu@1 { +- compatible = "nvidia,tegra194-carmel"; +- device_type = "cpu"; +- reg = <0x001>; +- enable-method = "psci"; +- i-cache-size = <131072>; +- i-cache-line-size = <64>; +- i-cache-sets = <512>; +- d-cache-size = <65536>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2c_0>; +- }; +- +- cpu1_0: cpu@100 { +- compatible = "nvidia,tegra194-carmel"; +- device_type = "cpu"; +- reg = <0x100>; +- enable-method = "psci"; +- i-cache-size = <131072>; +- i-cache-line-size = <64>; +- i-cache-sets = <512>; +- d-cache-size = <65536>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2c_1>; +- }; +- +- cpu1_1: cpu@101 { +- compatible = "nvidia,tegra194-carmel"; +- device_type = "cpu"; +- reg = <0x101>; +- enable-method = "psci"; +- i-cache-size = <131072>; +- i-cache-line-size = <64>; +- i-cache-sets = <512>; +- d-cache-size = <65536>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2c_1>; +- }; +- +- cpu2_0: cpu@200 { +- compatible = "nvidia,tegra194-carmel"; +- device_type = "cpu"; +- reg = <0x200>; +- enable-method = "psci"; +- i-cache-size = <131072>; +- i-cache-line-size = <64>; +- i-cache-sets = <512>; +- d-cache-size = <65536>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2c_2>; +- }; +- +- cpu2_1: cpu@201 { +- compatible = "nvidia,tegra194-carmel"; +- device_type = "cpu"; +- reg = <0x201>; +- enable-method = "psci"; +- i-cache-size = <131072>; +- i-cache-line-size = <64>; +- i-cache-sets = <512>; +- d-cache-size = <65536>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2c_2>; +- }; +- +- cpu3_0: cpu@300 { +- compatible = "nvidia,tegra194-carmel"; +- device_type = "cpu"; +- reg = <0x300>; +- enable-method = "psci"; +- i-cache-size = <131072>; +- i-cache-line-size = <64>; +- i-cache-sets = <512>; +- d-cache-size = <65536>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2c_3>; +- }; +- +- cpu3_1: cpu@301 { +- compatible = "nvidia,tegra194-carmel"; +- device_type = "cpu"; +- reg = <0x301>; +- enable-method = "psci"; +- i-cache-size = <131072>; +- i-cache-line-size = <64>; +- i-cache-sets = <512>; +- d-cache-size = <65536>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2c_3>; +- }; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0_0>; +- }; +- +- core1 { +- cpu = <&cpu0_1>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&cpu1_0>; +- }; +- +- core1 { +- cpu = <&cpu1_1>; +- }; +- }; +- +- cluster2 { +- core0 { +- cpu = <&cpu2_0>; +- }; +- +- core1 { +- cpu = <&cpu2_1>; +- }; +- }; +- +- cluster3 { +- core0 { +- cpu = <&cpu3_0>; +- }; +- +- core1 { +- cpu = <&cpu3_1>; +- }; +- }; +- }; +- +- l2c_0: l2-cache0 { +- cache-size = <2097152>; +- cache-line-size = <64>; +- cache-sets = <2048>; +- next-level-cache = <&l3c>; +- }; +- +- l2c_1: l2-cache1 { +- cache-size = <2097152>; +- cache-line-size = <64>; +- cache-sets = <2048>; +- next-level-cache = <&l3c>; +- }; +- +- l2c_2: l2-cache2 { +- cache-size = <2097152>; +- cache-line-size = <64>; +- cache-sets = <2048>; +- next-level-cache = <&l3c>; +- }; +- +- l2c_3: l2-cache3 { +- cache-size = <2097152>; +- cache-line-size = <64>; +- cache-sets = <2048>; +- next-level-cache = <&l3c>; +- }; +- +- l3c: l3-cache { +- cache-size = <4194304>; +- cache-line-size = <64>; +- cache-sets = <4096>; +- }; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 +- &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- status = "okay"; +- method = "smc"; +- }; +- +- sound { +- status = "disabled"; +- +- clocks = <&bpmp TEGRA194_CLK_PLLA>, +- <&bpmp TEGRA194_CLK_PLLA_OUT0>; +- clock-names = "pll_a", "plla_out0"; +- assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, +- <&bpmp TEGRA194_CLK_PLLA_OUT0>, +- <&bpmp TEGRA194_CLK_AUD_MCLK>; +- assigned-clock-parents = <0>, +- <&bpmp TEGRA194_CLK_PLLA>, +- <&bpmp TEGRA194_CLK_PLLA_OUT0>; +- /* +- * PLLA supports dynamic ramp. Below initial rate is chosen +- * for this to work and oscillate between base rates required +- * for 8x and 11.025x sample rate streams. +- */ +- assigned-clock-rates = <258000000>; +- +- interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, +- <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; +- interconnect-names = "dma-mem", "write"; +- iommus = <&smmu TEGRA194_SID_APE>; +- }; +- +- tcu: tcu { +- compatible = "nvidia,tegra194-tcu"; +- mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, +- <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; +- mbox-names = "rx", "tx"; +- }; +- +- thermal-zones { +- cpu { +- thermal-sensors = <&{/bpmp/thermal} +- TEGRA194_BPMP_THERMAL_ZONE_CPU>; +- status = "disabled"; +- }; +- +- gpu { +- thermal-sensors = <&{/bpmp/thermal} +- TEGRA194_BPMP_THERMAL_ZONE_GPU>; +- status = "disabled"; +- }; +- +- aux { +- thermal-sensors = <&{/bpmp/thermal} +- TEGRA194_BPMP_THERMAL_ZONE_AUX>; +- status = "disabled"; +- }; +- +- pllx { +- thermal-sensors = <&{/bpmp/thermal} +- TEGRA194_BPMP_THERMAL_ZONE_PLLX>; +- status = "disabled"; +- }; +- +- ao { +- thermal-sensors = <&{/bpmp/thermal} +- TEGRA194_BPMP_THERMAL_ZONE_AO>; +- status = "disabled"; +- }; +- +- tj { +- thermal-sensors = <&{/bpmp/thermal} +- TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; +- status = "disabled"; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- interrupt-parent = <&gic>; +- always-on; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2180.dtsi b/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2180.dtsi +deleted file mode 100644 +index 6077d572d828..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2180.dtsi ++++ /dev/null +@@ -1,350 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +- +-#include "tegra210.dtsi" +- +-/ { +- model = "NVIDIA Jetson TX1"; +- compatible = "nvidia,p2180", "nvidia,tegra210"; +- +- aliases { +- rtc0 = "/i2c@7000d000/pmic@3c"; +- rtc1 = "/rtc@7000e000"; +- serial0 = &uarta; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x1 0x0>; +- }; +- +- gpu@57000000 { +- vdd-supply = <&vdd_gpu>; +- }; +- +- /* debug port */ +- serial@70006000 { +- status = "okay"; +- }; +- +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- pmic: pmic@3c { +- compatible = "maxim,max77620"; +- reg = <0x3c>; +- interrupt-parent = <&tegra_pmc>; +- interrupts = <51 IRQ_TYPE_LEVEL_LOW>; +- +- #interrupt-cells = <2>; +- interrupt-controller; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&max77620_default>; +- +- max77620_default: pinmux { +- gpio0 { +- pins = "gpio0"; +- function = "gpio"; +- }; +- +- gpio1 { +- pins = "gpio1"; +- function = "fps-out"; +- drive-push-pull = <1>; +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <7>; +- maxim,active-fps-power-down-slot = <0>; +- }; +- +- gpio2_3 { +- pins = "gpio2", "gpio3"; +- function = "fps-out"; +- drive-open-drain = <1>; +- maxim,active-fps-source = ; +- }; +- +- gpio4 { +- pins = "gpio4"; +- function = "32k-out1"; +- }; +- +- gpio5_6_7 { +- pins = "gpio5", "gpio6", "gpio7"; +- function = "gpio"; +- drive-push-pull = <1>; +- }; +- }; +- +- fps { +- fps0 { +- maxim,fps-event-source = ; +- maxim,suspend-fps-time-period-us = <1280>; +- }; +- +- fps1 { +- maxim,fps-event-source = ; +- maxim,suspend-fps-time-period-us = <1280>; +- }; +- +- fps2 { +- maxim,fps-event-source = ; +- }; +- }; +- +- regulators { +- in-ldo0-1-supply = <&vdd_pre>; +- in-ldo7-8-supply = <&vdd_pre>; +- in-sd3-supply = <&vdd_5v0_sys>; +- +- vdd_soc: sd0 { +- regulator-name = "VDD_SOC"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-enable-ramp-delay = <146>; +- regulator-ramp-delay = <27500>; +- +- maxim,active-fps-source = ; +- }; +- +- vdd_ddr: sd1 { +- regulator-name = "VDD_DDR_1V1_PMIC"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-enable-ramp-delay = <130>; +- regulator-ramp-delay = <27500>; +- +- maxim,active-fps-source = ; +- }; +- +- vdd_pre: sd2 { +- regulator-name = "VDD_PRE_REG_1V35"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- +- regulator-enable-ramp-delay = <176>; +- regulator-ramp-delay = <27500>; +- +- maxim,active-fps-source = ; +- }; +- +- vdd_1v8: sd3 { +- regulator-name = "VDD_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-enable-ramp-delay = <242>; +- regulator-ramp-delay = <27500>; +- +- maxim,active-fps-source = ; +- }; +- +- vdd_sys_1v2: ldo0 { +- regulator-name = "AVDD_SYS_1V2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-enable-ramp-delay = <26>; +- regulator-ramp-delay = <100000>; +- +- maxim,active-fps-source = ; +- }; +- +- vdd_pex_1v05: ldo1 { +- regulator-name = "VDD_PEX_1V05"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- +- regulator-enable-ramp-delay = <22>; +- regulator-ramp-delay = <100000>; +- +- maxim,active-fps-source = ; +- }; +- +- vddio_sdmmc: ldo2 { +- regulator-name = "VDDIO_SDMMC"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-enable-ramp-delay = <62>; +- regulator-ramp-delay = <100000>; +- +- maxim,active-fps-source = ; +- }; +- +- vdd_cam_hv: ldo3 { +- regulator-name = "VDD_CAM_HV"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- +- regulator-enable-ramp-delay = <50>; +- regulator-ramp-delay = <100000>; +- +- maxim,active-fps-source = ; +- }; +- +- vdd_rtc: ldo4 { +- regulator-name = "VDD_RTC"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <850000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-enable-ramp-delay = <22>; +- regulator-ramp-delay = <100000>; +- +- maxim,active-fps-source = ; +- }; +- +- vdd_ts_hv: ldo5 { +- regulator-name = "VDD_TS_HV"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-enable-ramp-delay = <62>; +- regulator-ramp-delay = <100000>; +- +- maxim,active-fps-source = ; +- }; +- +- vdd_ts: ldo6 { +- regulator-name = "VDD_TS_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-enable-ramp-delay = <36>; +- regulator-ramp-delay = <100000>; +- +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <7>; +- maxim,active-fps-power-down-slot = <0>; +- }; +- +- avdd_1v05_pll: ldo7 { +- regulator-name = "AVDD_1V05_PLL"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-enable-ramp-delay = <24>; +- regulator-ramp-delay = <100000>; +- +- maxim,active-fps-source = ; +- }; +- +- avdd_1v05: ldo8 { +- regulator-name = "AVDD_SATA_HDMI_DP_1V05"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- +- regulator-enable-ramp-delay = <22>; +- regulator-ramp-delay = <100000>; +- +- maxim,active-fps-source = ; +- }; +- }; +- }; +- }; +- +- i2c@7000c500 { +- status = "okay"; +- +- /* module ID EEPROM */ +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- +- label = "module"; +- vcc-supply = <&vdd_1v8>; +- address-width = <8>; +- pagesize = <8>; +- size = <256>; +- read-only; +- }; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <0>; +- nvidia,cpu-pwr-good-time = <0>; +- nvidia,cpu-pwr-off-time = <0>; +- nvidia,core-pwr-good-time = <4587 3876>; +- nvidia,core-pwr-off-time = <39065>; +- nvidia,core-power-req-active-high; +- nvidia,sys-clock-req-active-high; +- }; +- +- /* eMMC */ +- mmc@700b0600 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- vqmmc-supply = <&vdd_1v8>; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- cpus { +- cpu@0 { +- enable-method = "psci"; +- }; +- +- cpu@1 { +- enable-method = "psci"; +- }; +- +- cpu@2 { +- enable-method = "psci"; +- }; +- +- cpu@3 { +- enable-method = "psci"; +- }; +- +- idle-states { +- cpu-sleep { +- status = "okay"; +- }; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- vdd_gpu: regulator@100 { +- compatible = "pwm-regulator"; +- pwms = <&pwm 1 8000>; +- regulator-name = "VDD_GPU"; +- regulator-min-microvolt = <710000>; +- regulator-max-microvolt = <1320000>; +- enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; +- regulator-ramp-delay = <80>; +- regulator-enable-ramp-delay = <2000>; +- regulator-settling-time-us = <160>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2371-0000.dts b/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2371-0000.dts +deleted file mode 100644 +index 21c6d3749bc6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2371-0000.dts ++++ /dev/null +@@ -1,10 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "tegra210-p2530.dtsi" +-#include "tegra210-p2595.dtsi" +- +-/ { +- model = "NVIDIA Tegra210 P2371 (P2530/P2595) reference design"; +- compatible = "nvidia,p2371-0000", "nvidia,tegra210"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2371-2180.dts b/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2371-2180.dts +deleted file mode 100644 +index 7d3e3634743e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2371-2180.dts ++++ /dev/null +@@ -1,429 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "tegra210-p2180.dtsi" +-#include "tegra210-p2597.dtsi" +- +-/ { +- model = "NVIDIA Jetson TX1 Developer Kit"; +- compatible = "nvidia,p2371-2180", "nvidia,tegra210"; +- +- pcie@1003000 { +- status = "okay"; +- +- avdd-pll-uerefe-supply = <&avdd_1v05_pll>; +- hvddio-pex-supply = <&vdd_1v8>; +- dvddio-pex-supply = <&vdd_pex_1v05>; +- dvdd-pex-pll-supply = <&vdd_pex_1v05>; +- hvdd-pex-pll-e-supply = <&vdd_1v8>; +- vddio-pex-ctl-supply = <&vdd_1v8>; +- +- pci@1,0 { +- phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; +- phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; +- status = "okay"; +- }; +- +- pci@2,0 { +- phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; +- phy-names = "pcie-0"; +- status = "okay"; +- }; +- }; +- +- host1x@50000000 { +- dsi@54300000 { +- status = "okay"; +- +- avdd-dsi-csi-supply = <&vdd_dsi_csi>; +- +- panel@0 { +- compatible = "auo,b080uan01"; +- reg = <0>; +- +- enable-gpios = <&gpio TEGRA_GPIO(V, 2) +- GPIO_ACTIVE_HIGH>; +- power-supply = <&vdd_5v0_io>; +- backlight = <&backlight>; +- }; +- }; +- }; +- +- i2c@7000c400 { +- backlight: backlight@2c { +- compatible = "ti,lp8557"; +- reg = <0x2c>; +- power-supply = <&vdd_3v3_sys>; +- +- dev-ctrl = /bits/ 8 <0x80>; +- init-brt = /bits/ 8 <0xff>; +- +- pwm-period = <29334>; +- +- pwms = <&pwm 0 29334>; +- pwm-names = "lp8557"; +- +- /* 3 LED string */ +- rom_14h { +- rom-addr = /bits/ 8 <0x14>; +- rom-val = /bits/ 8 <0x87>; +- }; +- +- /* boost frequency 1 MHz */ +- rom_13h { +- rom-addr = /bits/ 8 <0x13>; +- rom-val = /bits/ 8 <0x01>; +- }; +- }; +- }; +- +- i2c@7000c500 { +- /* carrier board ID EEPROM */ +- eeprom@57 { +- compatible = "atmel,24c02"; +- reg = <0x57>; +- +- label = "system"; +- vcc-supply = <&vdd_1v8>; +- address-width = <8>; +- pagesize = <8>; +- size = <256>; +- read-only; +- }; +- }; +- +- clock@70110000 { +- status = "okay"; +- +- nvidia,cf = <6>; +- nvidia,ci = <0>; +- nvidia,cg = <2>; +- nvidia,droop-ctrl = <0x00000f00>; +- nvidia,force-mode = <1>; +- nvidia,sample-rate = <25000>; +- +- nvidia,pwm-min-microvolts = <708000>; +- nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ +- nvidia,pwm-to-pmic; +- nvidia,pwm-tristate-microvolts = <1000000>; +- nvidia,pwm-voltage-step-microvolts = <19200>; +- +- pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; +- pinctrl-0 = <&dvfs_pwm_active_state>; +- pinctrl-1 = <&dvfs_pwm_inactive_state>; +- }; +- +- aconnect@702c0000 { +- status = "okay"; +- +- dma-controller@702e2000 { +- status = "okay"; +- }; +- +- interrupt-controller@702f9000 { +- status = "okay"; +- }; +- +- ahub@702d0800 { +- status = "okay"; +- +- admaif@702d0000 { +- status = "okay"; +- }; +- +- i2s@702d1000 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- i2s1_cif_ep: endpoint { +- remote-endpoint = <&xbar_i2s1_ep>; +- }; +- }; +- +- i2s1_port: port@1 { +- reg = <1>; +- +- i2s1_dap_ep: endpoint { +- dai-format = "i2s"; +- /* Placeholder for external Codec */ +- }; +- }; +- }; +- }; +- +- i2s@702d1100 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- i2s2_cif_ep: endpoint { +- remote-endpoint = <&xbar_i2s2_ep>; +- }; +- }; +- +- i2s2_port: port@1 { +- reg = <1>; +- +- i2s2_dap_ep: endpoint { +- dai-format = "i2s"; +- /* Placeholder for external Codec */ +- }; +- }; +- }; +- }; +- +- i2s@702d1200 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- i2s3_cif_ep: endpoint { +- remote-endpoint = <&xbar_i2s3_ep>; +- }; +- }; +- +- i2s3_port: port@1 { +- reg = <1>; +- +- i2s3_dap_ep: endpoint { +- dai-format = "i2s"; +- /* Placeholder for external Codec */ +- }; +- }; +- }; +- }; +- +- i2s@702d1300 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- i2s4_cif_ep: endpoint { +- remote-endpoint = <&xbar_i2s4_ep>; +- }; +- }; +- +- i2s4_port: port@1 { +- reg = <1>; +- +- i2s4_dap_ep: endpoint { +- dai-format = "i2s"; +- /* Placeholder for external Codec */ +- }; +- }; +- }; +- }; +- +- i2s@702d1400 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- i2s5_cif_ep: endpoint { +- remote-endpoint = <&xbar_i2s5_ep>; +- }; +- }; +- +- i2s5_port: port@1 { +- reg = <1>; +- +- i2s5_dap_ep: endpoint { +- dai-format = "i2s"; +- /* Placeholder for external Codec */ +- }; +- }; +- }; +- }; +- +- dmic@702d4000 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- dmic1_cif_ep: endpoint { +- remote-endpoint = <&xbar_dmic1_ep>; +- }; +- }; +- +- dmic1_port: port@1 { +- reg = <1>; +- +- dmic1_dap_ep: endpoint { +- /* Placeholder for external Codec */ +- }; +- }; +- }; +- }; +- +- dmic@702d4100 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- dmic2_cif_ep: endpoint { +- remote-endpoint = <&xbar_dmic2_ep>; +- }; +- }; +- +- dmic2_port: port@1 { +- reg = <1>; +- +- dmic2_dap_ep: endpoint { +- /* Placeholder for external Codec */ +- }; +- }; +- }; +- }; +- +- dmic@702d4200 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- dmic3_cif_ep: endpoint { +- remote-endpoint = <&xbar_dmic3_ep>; +- }; +- }; +- +- dmic3_port: port@1 { +- reg = <1>; +- +- dmic3_dap_ep: endpoint { +- /* Placeholder for external Codec */ +- }; +- }; +- }; +- }; +- +- ports { +- xbar_i2s1_port: port@a { +- reg = <0xa>; +- +- xbar_i2s1_ep: endpoint { +- remote-endpoint = <&i2s1_cif_ep>; +- }; +- }; +- +- xbar_i2s2_port: port@b { +- reg = <0xb>; +- +- xbar_i2s2_ep: endpoint { +- remote-endpoint = <&i2s2_cif_ep>; +- }; +- }; +- +- xbar_i2s3_port: port@c { +- reg = <0xc>; +- +- xbar_i2s3_ep: endpoint { +- remote-endpoint = <&i2s3_cif_ep>; +- }; +- }; +- +- xbar_i2s4_port: port@d { +- reg = <0xd>; +- +- xbar_i2s4_ep: endpoint { +- remote-endpoint = <&i2s4_cif_ep>; +- }; +- }; +- +- xbar_i2s5_port: port@e { +- reg = <0xe>; +- +- xbar_i2s5_ep: endpoint { +- remote-endpoint = <&i2s5_cif_ep>; +- }; +- }; +- +- xbar_dmic1_port: port@f { +- reg = <0xf>; +- +- xbar_dmic1_ep: endpoint { +- remote-endpoint = <&dmic1_cif_ep>; +- }; +- }; +- +- xbar_dmic2_port: port@10 { +- reg = <0x10>; +- +- xbar_dmic2_ep: endpoint { +- remote-endpoint = <&dmic2_cif_ep>; +- }; +- }; +- +- xbar_dmic3_port: port@11 { +- reg = <0x11>; +- +- xbar_dmic3_ep: endpoint { +- remote-endpoint = <&dmic3_cif_ep>; +- }; +- }; +- }; +- }; +- }; +- +- sound { +- compatible = "nvidia,tegra210-audio-graph-card"; +- status = "okay"; +- +- dais = /* FE */ +- <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, +- <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, +- <&admaif7_port>, <&admaif8_port>, <&admaif9_port>, +- <&admaif10_port>, +- /* Router */ +- <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>, +- <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_dmic1_port>, +- <&xbar_dmic2_port>, <&xbar_dmic3_port>, +- /* I/O DAP Ports */ +- <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>, +- <&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>; +- +- label = "NVIDIA Jetson TX1 APE"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2530.dtsi b/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2530.dtsi +deleted file mode 100644 +index 58aa0518965e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2530.dtsi ++++ /dev/null +@@ -1,71 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include "tegra210.dtsi" +- +-/ { +- model = "NVIDIA Tegra210 P2530 main board"; +- compatible = "nvidia,p2530", "nvidia,tegra210"; +- +- aliases { +- rtc1 = "/rtc@7000e000"; +- serial0 = &uarta; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0xc0000000>; +- }; +- +- /* debug port */ +- serial@70006000 { +- status = "okay"; +- }; +- +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <400000>; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- }; +- +- /* eMMC */ +- mmc@700b0600 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- cpus { +- cpu@0 { +- enable-method = "psci"; +- }; +- +- cpu@1 { +- enable-method = "psci"; +- }; +- +- cpu@2 { +- enable-method = "psci"; +- }; +- +- cpu@3 { +- enable-method = "psci"; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2571.dts b/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2571.dts +deleted file mode 100644 +index e2a347e57215..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2571.dts ++++ /dev/null +@@ -1,1303 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include "tegra210-p2530.dtsi" +- +-/ { +- model = "NVIDIA Tegra210 P2571 reference design"; +- compatible = "nvidia,p2571", "nvidia,tegra210"; +- +- pinmux: pinmux@700008d4 { +- pinctrl-names = "boot"; +- pinctrl-0 = <&state_boot>; +- +- state_boot: pinmux { +- pex_l0_rst_n_pa0 { +- nvidia,pins = "pex_l0_rst_n_pa0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_l0_clkreq_n_pa1 { +- nvidia,pins = "pex_l0_clkreq_n_pa1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_wake_n_pa2 { +- nvidia,pins = "pex_wake_n_pa2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_l1_rst_n_pa3 { +- nvidia,pins = "pex_l1_rst_n_pa3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_l1_clkreq_n_pa4 { +- nvidia,pins = "pex_l1_clkreq_n_pa4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- sata_led_active_pa5 { +- nvidia,pins = "sata_led_active_pa5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pa6 { +- nvidia,pins = "pa6"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_fs_pb0 { +- nvidia,pins = "dap1_fs_pb0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_din_pb1 { +- nvidia,pins = "dap1_din_pb1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_dout_pb2 { +- nvidia,pins = "dap1_dout_pb2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_sclk_pb3 { +- nvidia,pins = "dap1_sclk_pb3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_mosi_pb4 { +- nvidia,pins = "spi2_mosi_pb4"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_miso_pb5 { +- nvidia,pins = "spi2_miso_pb5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_sck_pb6 { +- nvidia,pins = "spi2_sck_pb6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_cs0_pb7 { +- nvidia,pins = "spi2_cs0_pb7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_mosi_pc0 { +- nvidia,pins = "spi1_mosi_pc0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_miso_pc1 { +- nvidia,pins = "spi1_miso_pc1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_sck_pc2 { +- nvidia,pins = "spi1_sck_pc2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_cs0_pc3 { +- nvidia,pins = "spi1_cs0_pc3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_cs1_pc4 { +- nvidia,pins = "spi1_cs1_pc4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_sck_pc5 { +- nvidia,pins = "spi4_sck_pc5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_cs0_pc6 { +- nvidia,pins = "spi4_cs0_pc6"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_mosi_pc7 { +- nvidia,pins = "spi4_mosi_pc7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_miso_pd0 { +- nvidia,pins = "spi4_miso_pd0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_tx_pd1 { +- nvidia,pins = "uart3_tx_pd1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_rx_pd2 { +- nvidia,pins = "uart3_rx_pd2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_rts_pd3 { +- nvidia,pins = "uart3_rts_pd3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_cts_pd4 { +- nvidia,pins = "uart3_cts_pd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic1_clk_pe0 { +- nvidia,pins = "dmic1_clk_pe0"; +- nvidia,function = "i2s3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic1_dat_pe1 { +- nvidia,pins = "dmic1_dat_pe1"; +- nvidia,function = "i2s3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic2_clk_pe2 { +- nvidia,pins = "dmic2_clk_pe2"; +- nvidia,function = "i2s3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic2_dat_pe3 { +- nvidia,pins = "dmic2_dat_pe3"; +- nvidia,function = "i2s3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic3_clk_pe4 { +- nvidia,pins = "dmic3_clk_pe4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic3_dat_pe5 { +- nvidia,pins = "dmic3_dat_pe5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pe6 { +- nvidia,pins = "pe6"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pe7 { +- nvidia,pins = "pe7"; +- nvidia,function = "pwm3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen3_i2c_scl_pf0 { +- nvidia,pins = "gen3_i2c_scl_pf0"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen3_i2c_sda_pf1 { +- nvidia,pins = "gen3_i2c_sda_pf1"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- uart2_tx_pg0 { +- nvidia,pins = "uart2_tx_pg0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart2_rx_pg1 { +- nvidia,pins = "uart2_rx_pg1"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart2_rts_pg2 { +- nvidia,pins = "uart2_rts_pg2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart2_cts_pg3 { +- nvidia,pins = "uart2_cts_pg3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- wifi_en_ph0 { +- nvidia,pins = "wifi_en_ph0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- wifi_rst_ph1 { +- nvidia,pins = "wifi_rst_ph1"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- wifi_wake_ap_ph2 { +- nvidia,pins = "wifi_wake_ap_ph2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ap_wake_bt_ph3 { +- nvidia,pins = "ap_wake_bt_ph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- bt_rst_ph4 { +- nvidia,pins = "bt_rst_ph4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- bt_wake_ap_ph5 { +- nvidia,pins = "bt_wake_ap_ph5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ph6 { +- nvidia,pins = "ph6"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ap_wake_nfc_ph7 { +- nvidia,pins = "ap_wake_nfc_ph7"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- nfc_en_pi0 { +- nvidia,pins = "nfc_en_pi0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- nfc_int_pi1 { +- nvidia,pins = "nfc_int_pi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gps_en_pi2 { +- nvidia,pins = "gps_en_pi2"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gps_rst_pi3 { +- nvidia,pins = "gps_rst_pi3"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_tx_pi4 { +- nvidia,pins = "uart4_tx_pi4"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_rx_pi5 { +- nvidia,pins = "uart4_rx_pi5"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_rts_pi6 { +- nvidia,pins = "uart4_rts_pi6"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_cts_pi7 { +- nvidia,pins = "uart4_cts_pi7"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen1_i2c_sda_pj0 { +- nvidia,pins = "gen1_i2c_sda_pj0"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen1_i2c_scl_pj1 { +- nvidia,pins = "gen1_i2c_scl_pj1"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen2_i2c_scl_pj2 { +- nvidia,pins = "gen2_i2c_scl_pj2"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen2_i2c_sda_pj3 { +- nvidia,pins = "gen2_i2c_sda_pj3"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- dap4_fs_pj4 { +- nvidia,pins = "dap4_fs_pj4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap4_din_pj5 { +- nvidia,pins = "dap4_din_pj5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap4_dout_pj6 { +- nvidia,pins = "dap4_dout_pj6"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap4_sclk_pj7 { +- nvidia,pins = "dap4_sclk_pj7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk0 { +- nvidia,pins = "pk0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk1 { +- nvidia,pins = "pk1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk2 { +- nvidia,pins = "pk2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk3 { +- nvidia,pins = "pk3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk4 { +- nvidia,pins = "pk4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk5 { +- nvidia,pins = "pk5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk6 { +- nvidia,pins = "pk6"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk7 { +- nvidia,pins = "pk7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pl0 { +- nvidia,pins = "pl0"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pl1 { +- nvidia,pins = "pl1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_clk_pm0 { +- nvidia,pins = "sdmmc1_clk_pm0"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_cmd_pm1 { +- nvidia,pins = "sdmmc1_cmd_pm1"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat3_pm2 { +- nvidia,pins = "sdmmc1_dat3_pm2"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat2_pm3 { +- nvidia,pins = "sdmmc1_dat2_pm3"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat1_pm4 { +- nvidia,pins = "sdmmc1_dat1_pm4"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat0_pm5 { +- nvidia,pins = "sdmmc1_dat0_pm5"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_clk_pp0 { +- nvidia,pins = "sdmmc3_clk_pp0"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_cmd_pp1 { +- nvidia,pins = "sdmmc3_cmd_pp1"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat3_pp2 { +- nvidia,pins = "sdmmc3_dat3_pp2"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat2_pp3 { +- nvidia,pins = "sdmmc3_dat2_pp3"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat1_pp4 { +- nvidia,pins = "sdmmc3_dat1_pp4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat0_pp5 { +- nvidia,pins = "sdmmc3_dat0_pp5"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam1_mclk_ps0 { +- nvidia,pins = "cam1_mclk_ps0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam2_mclk_ps1 { +- nvidia,pins = "cam2_mclk_ps1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_i2c_scl_ps2 { +- nvidia,pins = "cam_i2c_scl_ps2"; +- nvidia,function = "i2cvi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- cam_i2c_sda_ps3 { +- nvidia,pins = "cam_i2c_sda_ps3"; +- nvidia,function = "i2cvi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- cam_rst_ps4 { +- nvidia,pins = "cam_rst_ps4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_af_en_ps5 { +- nvidia,pins = "cam_af_en_ps5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_flash_en_ps6 { +- nvidia,pins = "cam_flash_en_ps6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam1_pwdn_ps7 { +- nvidia,pins = "cam1_pwdn_ps7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam2_pwdn_pt0 { +- nvidia,pins = "cam2_pwdn_pt0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam1_strobe_pt1 { +- nvidia,pins = "cam1_strobe_pt1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_tx_pu0 { +- nvidia,pins = "uart1_tx_pu0"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_rx_pu1 { +- nvidia,pins = "uart1_rx_pu1"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_rts_pu2 { +- nvidia,pins = "uart1_rts_pu2"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_cts_pu3 { +- nvidia,pins = "uart1_cts_pu3"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_bl_pwm_pv0 { +- nvidia,pins = "lcd_bl_pwm_pv0"; +- nvidia,function = "pwm0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_bl_en_pv1 { +- nvidia,pins = "lcd_bl_en_pv1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_rst_pv2 { +- nvidia,pins = "lcd_rst_pv2"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_gpio1_pv3 { +- nvidia,pins = "lcd_gpio1_pv3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_gpio2_pv4 { +- nvidia,pins = "lcd_gpio2_pv4"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ap_ready_pv5 { +- nvidia,pins = "ap_ready_pv5"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- touch_rst_pv6 { +- nvidia,pins = "touch_rst_pv6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- touch_clk_pv7 { +- nvidia,pins = "touch_clk_pv7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- modem_wake_ap_px0 { +- nvidia,pins = "modem_wake_ap_px0"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- touch_int_px1 { +- nvidia,pins = "touch_int_px1"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- motion_int_px2 { +- nvidia,pins = "motion_int_px2"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- als_prox_int_px3 { +- nvidia,pins = "als_prox_int_px3"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- temp_alert_px4 { +- nvidia,pins = "temp_alert_px4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_power_on_px5 { +- nvidia,pins = "button_power_on_px5"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_vol_up_px6 { +- nvidia,pins = "button_vol_up_px6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_vol_down_px7 { +- nvidia,pins = "button_vol_down_px7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_slide_sw_py0 { +- nvidia,pins = "button_slide_sw_py0"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_home_py1 { +- nvidia,pins = "button_home_py1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_te_py2 { +- nvidia,pins = "lcd_te_py2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pwr_i2c_scl_py3 { +- nvidia,pins = "pwr_i2c_scl_py3"; +- nvidia,function = "i2cpmu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pwr_i2c_sda_py4 { +- nvidia,pins = "pwr_i2c_sda_py4"; +- nvidia,function = "i2cpmu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- clk_32k_out_py5 { +- nvidia,pins = "clk_32k_out_py5"; +- nvidia,function = "soc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz0 { +- nvidia,pins = "pz0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz1 { +- nvidia,pins = "pz1"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz2 { +- nvidia,pins = "pz2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz3 { +- nvidia,pins = "pz3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz4 { +- nvidia,pins = "pz4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz5 { +- nvidia,pins = "pz5"; +- nvidia,function = "soc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_fs_paa0 { +- nvidia,pins = "dap2_fs_paa0"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_sclk_paa1 { +- nvidia,pins = "dap2_sclk_paa1"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_din_paa2 { +- nvidia,pins = "dap2_din_paa2"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_dout_paa3 { +- nvidia,pins = "dap2_dout_paa3"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- aud_mclk_pbb0 { +- nvidia,pins = "aud_mclk_pbb0"; +- nvidia,function = "aud"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dvfs_pwm_pbb1 { +- nvidia,pins = "dvfs_pwm_pbb1"; +- nvidia,function = "cldvfs"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dvfs_clk_pbb2 { +- nvidia,pins = "dvfs_clk_pbb2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gpio_x1_aud_pbb3 { +- nvidia,pins = "gpio_x1_aud_pbb3"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gpio_x3_aud_pbb4 { +- nvidia,pins = "gpio_x3_aud_pbb4"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- hdmi_cec_pcc0 { +- nvidia,pins = "hdmi_cec_pcc0"; +- nvidia,function = "cec"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- hdmi_int_dp_hpd_pcc1 { +- nvidia,pins = "hdmi_int_dp_hpd_pcc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- spdif_out_pcc2 { +- nvidia,pins = "spdif_out_pcc2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spdif_in_pcc3 { +- nvidia,pins = "spdif_in_pcc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- usb_vbus_en0_pcc4 { +- nvidia,pins = "usb_vbus_en0_pcc4"; +- nvidia,function = "usb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- usb_vbus_en1_pcc5 { +- nvidia,pins = "usb_vbus_en1_pcc5"; +- nvidia,function = "usb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- dp_hpd0_pcc6 { +- nvidia,pins = "dp_hpd0_pcc6"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pcc7 { +- nvidia,pins = "pcc7"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- spi2_cs1_pdd0 { +- nvidia,pins = "spi2_cs1_pdd0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_sck_pee0 { +- nvidia,pins = "qspi_sck_pee0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_cs_n_pee1 { +- nvidia,pins = "qspi_cs_n_pee1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io0_pee2 { +- nvidia,pins = "qspi_io0_pee2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io1_pee3 { +- nvidia,pins = "qspi_io1_pee3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io2_pee4 { +- nvidia,pins = "qspi_io2_pee4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io3_pee5 { +- nvidia,pins = "qspi_io3_pee5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- core_pwr_req { +- nvidia,pins = "core_pwr_req"; +- nvidia,function = "core"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cpu_pwr_req { +- nvidia,pins = "cpu_pwr_req"; +- nvidia,function = "cpu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pwr_int_n { +- nvidia,pins = "pwr_int_n"; +- nvidia,function = "pmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- clk_32k_in { +- nvidia,pins = "clk_32k_in"; +- nvidia,function = "clk"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- jtag_rtck { +- nvidia,pins = "jtag_rtck"; +- nvidia,function = "jtag"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- clk_req { +- nvidia,pins = "clk_req"; +- nvidia,function = "sys"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- shutdown { +- nvidia,pins = "shutdown"; +- nvidia,function = "shutdown"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2595.dtsi b/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2595.dtsi +deleted file mode 100644 +index 6ae292da7294..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2595.dtsi ++++ /dev/null +@@ -1,1273 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- model = "NVIDIA Tegra210 P2595 I/O board"; +- compatible = "nvidia,p2595", "nvidia,tegra210"; +- +- pinmux: pinmux@700008d4 { +- pinctrl-names = "boot"; +- pinctrl-0 = <&state_boot>; +- +- state_boot: pinmux { +- pex_l0_rst_n_pa0 { +- nvidia,pins = "pex_l0_rst_n_pa0"; +- nvidia,function = "pe0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_l0_clkreq_n_pa1 { +- nvidia,pins = "pex_l0_clkreq_n_pa1"; +- nvidia,function = "pe0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_wake_n_pa2 { +- nvidia,pins = "pex_wake_n_pa2"; +- nvidia,function = "pe"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_l1_rst_n_pa3 { +- nvidia,pins = "pex_l1_rst_n_pa3"; +- nvidia,function = "pe1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_l1_clkreq_n_pa4 { +- nvidia,pins = "pex_l1_clkreq_n_pa4"; +- nvidia,function = "pe1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- sata_led_active_pa5 { +- nvidia,pins = "sata_led_active_pa5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pa6 { +- nvidia,pins = "pa6"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_fs_pb0 { +- nvidia,pins = "dap1_fs_pb0"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_din_pb1 { +- nvidia,pins = "dap1_din_pb1"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_dout_pb2 { +- nvidia,pins = "dap1_dout_pb2"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_sclk_pb3 { +- nvidia,pins = "dap1_sclk_pb3"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_mosi_pb4 { +- nvidia,pins = "spi2_mosi_pb4"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_miso_pb5 { +- nvidia,pins = "spi2_miso_pb5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_sck_pb6 { +- nvidia,pins = "spi2_sck_pb6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_cs0_pb7 { +- nvidia,pins = "spi2_cs0_pb7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_mosi_pc0 { +- nvidia,pins = "spi1_mosi_pc0"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_miso_pc1 { +- nvidia,pins = "spi1_miso_pc1"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_sck_pc2 { +- nvidia,pins = "spi1_sck_pc2"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_cs0_pc3 { +- nvidia,pins = "spi1_cs0_pc3"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_cs1_pc4 { +- nvidia,pins = "spi1_cs1_pc4"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_sck_pc5 { +- nvidia,pins = "spi4_sck_pc5"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_cs0_pc6 { +- nvidia,pins = "spi4_cs0_pc6"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_mosi_pc7 { +- nvidia,pins = "spi4_mosi_pc7"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_miso_pd0 { +- nvidia,pins = "spi4_miso_pd0"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_tx_pd1 { +- nvidia,pins = "uart3_tx_pd1"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_rx_pd2 { +- nvidia,pins = "uart3_rx_pd2"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_rts_pd3 { +- nvidia,pins = "uart3_rts_pd3"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_cts_pd4 { +- nvidia,pins = "uart3_cts_pd4"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic1_clk_pe0 { +- nvidia,pins = "dmic1_clk_pe0"; +- nvidia,function = "dmic1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic1_dat_pe1 { +- nvidia,pins = "dmic1_dat_pe1"; +- nvidia,function = "dmic1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic2_clk_pe2 { +- nvidia,pins = "dmic2_clk_pe2"; +- nvidia,function = "dmic2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic2_dat_pe3 { +- nvidia,pins = "dmic2_dat_pe3"; +- nvidia,function = "dmic2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic3_clk_pe4 { +- nvidia,pins = "dmic3_clk_pe4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic3_dat_pe5 { +- nvidia,pins = "dmic3_dat_pe5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pe6 { +- nvidia,pins = "pe6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pe7 { +- nvidia,pins = "pe7"; +- nvidia,function = "pwm3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen3_i2c_scl_pf0 { +- nvidia,pins = "gen3_i2c_scl_pf0"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen3_i2c_sda_pf1 { +- nvidia,pins = "gen3_i2c_sda_pf1"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- uart2_tx_pg0 { +- nvidia,pins = "uart2_tx_pg0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart2_rx_pg1 { +- nvidia,pins = "uart2_rx_pg1"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart2_rts_pg2 { +- nvidia,pins = "uart2_rts_pg2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart2_cts_pg3 { +- nvidia,pins = "uart2_cts_pg3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- wifi_en_ph0 { +- nvidia,pins = "wifi_en_ph0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- wifi_rst_ph1 { +- nvidia,pins = "wifi_rst_ph1"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- wifi_wake_ap_ph2 { +- nvidia,pins = "wifi_wake_ap_ph2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ap_wake_bt_ph3 { +- nvidia,pins = "ap_wake_bt_ph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- bt_rst_ph4 { +- nvidia,pins = "bt_rst_ph4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- bt_wake_ap_ph5 { +- nvidia,pins = "bt_wake_ap_ph5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ph6 { +- nvidia,pins = "ph6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ap_wake_nfc_ph7 { +- nvidia,pins = "ap_wake_nfc_ph7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- nfc_en_pi0 { +- nvidia,pins = "nfc_en_pi0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- nfc_int_pi1 { +- nvidia,pins = "nfc_int_pi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gps_en_pi2 { +- nvidia,pins = "gps_en_pi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gps_rst_pi3 { +- nvidia,pins = "gps_rst_pi3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_tx_pi4 { +- nvidia,pins = "uart4_tx_pi4"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_rx_pi5 { +- nvidia,pins = "uart4_rx_pi5"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_rts_pi6 { +- nvidia,pins = "uart4_rts_pi6"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_cts_pi7 { +- nvidia,pins = "uart4_cts_pi7"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen1_i2c_sda_pj0 { +- nvidia,pins = "gen1_i2c_sda_pj0"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen1_i2c_scl_pj1 { +- nvidia,pins = "gen1_i2c_scl_pj1"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen2_i2c_scl_pj2 { +- nvidia,pins = "gen2_i2c_scl_pj2"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen2_i2c_sda_pj3 { +- nvidia,pins = "gen2_i2c_sda_pj3"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- dap4_fs_pj4 { +- nvidia,pins = "dap4_fs_pj4"; +- nvidia,function = "i2s4b"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap4_din_pj5 { +- nvidia,pins = "dap4_din_pj5"; +- nvidia,function = "i2s4b"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap4_dout_pj6 { +- nvidia,pins = "dap4_dout_pj6"; +- nvidia,function = "i2s4b"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap4_sclk_pj7 { +- nvidia,pins = "dap4_sclk_pj7"; +- nvidia,function = "i2s4b"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk0 { +- nvidia,pins = "pk0"; +- nvidia,function = "i2s5b"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk1 { +- nvidia,pins = "pk1"; +- nvidia,function = "i2s5b"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk2 { +- nvidia,pins = "pk2"; +- nvidia,function = "i2s5b"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk3 { +- nvidia,pins = "pk3"; +- nvidia,function = "i2s5b"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk4 { +- nvidia,pins = "pk4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk5 { +- nvidia,pins = "pk5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk6 { +- nvidia,pins = "pk6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk7 { +- nvidia,pins = "pk7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pl0 { +- nvidia,pins = "pl0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pl1 { +- nvidia,pins = "pl1"; +- nvidia,function = "soc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_clk_pm0 { +- nvidia,pins = "sdmmc1_clk_pm0"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_cmd_pm1 { +- nvidia,pins = "sdmmc1_cmd_pm1"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat3_pm2 { +- nvidia,pins = "sdmmc1_dat3_pm2"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat2_pm3 { +- nvidia,pins = "sdmmc1_dat2_pm3"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat1_pm4 { +- nvidia,pins = "sdmmc1_dat1_pm4"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat0_pm5 { +- nvidia,pins = "sdmmc1_dat0_pm5"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_clk_pp0 { +- nvidia,pins = "sdmmc3_clk_pp0"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_cmd_pp1 { +- nvidia,pins = "sdmmc3_cmd_pp1"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat3_pp2 { +- nvidia,pins = "sdmmc3_dat3_pp2"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat2_pp3 { +- nvidia,pins = "sdmmc3_dat2_pp3"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat1_pp4 { +- nvidia,pins = "sdmmc3_dat1_pp4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat0_pp5 { +- nvidia,pins = "sdmmc3_dat0_pp5"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam1_mclk_ps0 { +- nvidia,pins = "cam1_mclk_ps0"; +- nvidia,function = "extperiph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam2_mclk_ps1 { +- nvidia,pins = "cam2_mclk_ps1"; +- nvidia,function = "extperiph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_i2c_scl_ps2 { +- nvidia,pins = "cam_i2c_scl_ps2"; +- nvidia,function = "i2cvi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- cam_i2c_sda_ps3 { +- nvidia,pins = "cam_i2c_sda_ps3"; +- nvidia,function = "i2cvi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- cam_rst_ps4 { +- nvidia,pins = "cam_rst_ps4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_af_en_ps5 { +- nvidia,pins = "cam_af_en_ps5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_flash_en_ps6 { +- nvidia,pins = "cam_flash_en_ps6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam1_pwdn_ps7 { +- nvidia,pins = "cam1_pwdn_ps7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam2_pwdn_pt0 { +- nvidia,pins = "cam2_pwdn_pt0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam1_strobe_pt1 { +- nvidia,pins = "cam1_strobe_pt1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_tx_pu0 { +- nvidia,pins = "uart1_tx_pu0"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_rx_pu1 { +- nvidia,pins = "uart1_rx_pu1"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_rts_pu2 { +- nvidia,pins = "uart1_rts_pu2"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_cts_pu3 { +- nvidia,pins = "uart1_cts_pu3"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_bl_pwm_pv0 { +- nvidia,pins = "lcd_bl_pwm_pv0"; +- nvidia,function = "pwm0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_bl_en_pv1 { +- nvidia,pins = "lcd_bl_en_pv1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_rst_pv2 { +- nvidia,pins = "lcd_rst_pv2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_gpio1_pv3 { +- nvidia,pins = "lcd_gpio1_pv3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_gpio2_pv4 { +- nvidia,pins = "lcd_gpio2_pv4"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ap_ready_pv5 { +- nvidia,pins = "ap_ready_pv5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- touch_rst_pv6 { +- nvidia,pins = "touch_rst_pv6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- touch_clk_pv7 { +- nvidia,pins = "touch_clk_pv7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- modem_wake_ap_px0 { +- nvidia,pins = "modem_wake_ap_px0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- touch_int_px1 { +- nvidia,pins = "touch_int_px1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- motion_int_px2 { +- nvidia,pins = "motion_int_px2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- als_prox_int_px3 { +- nvidia,pins = "als_prox_int_px3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- temp_alert_px4 { +- nvidia,pins = "temp_alert_px4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_power_on_px5 { +- nvidia,pins = "button_power_on_px5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_vol_up_px6 { +- nvidia,pins = "button_vol_up_px6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_vol_down_px7 { +- nvidia,pins = "button_vol_down_px7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_slide_sw_py0 { +- nvidia,pins = "button_slide_sw_py0"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_home_py1 { +- nvidia,pins = "button_home_py1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_te_py2 { +- nvidia,pins = "lcd_te_py2"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pwr_i2c_scl_py3 { +- nvidia,pins = "pwr_i2c_scl_py3"; +- nvidia,function = "i2cpmu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pwr_i2c_sda_py4 { +- nvidia,pins = "pwr_i2c_sda_py4"; +- nvidia,function = "i2cpmu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- clk_32k_out_py5 { +- nvidia,pins = "clk_32k_out_py5"; +- nvidia,function = "soc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz0 { +- nvidia,pins = "pz0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz1 { +- nvidia,pins = "pz1"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz2 { +- nvidia,pins = "pz2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz3 { +- nvidia,pins = "pz3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz4 { +- nvidia,pins = "pz4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz5 { +- nvidia,pins = "pz5"; +- nvidia,function = "soc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_fs_paa0 { +- nvidia,pins = "dap2_fs_paa0"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_sclk_paa1 { +- nvidia,pins = "dap2_sclk_paa1"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_din_paa2 { +- nvidia,pins = "dap2_din_paa2"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_dout_paa3 { +- nvidia,pins = "dap2_dout_paa3"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- aud_mclk_pbb0 { +- nvidia,pins = "aud_mclk_pbb0"; +- nvidia,function = "aud"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dvfs_pwm_pbb1 { +- nvidia,pins = "dvfs_pwm_pbb1"; +- nvidia,function = "cldvfs"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dvfs_clk_pbb2 { +- nvidia,pins = "dvfs_clk_pbb2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gpio_x1_aud_pbb3 { +- nvidia,pins = "gpio_x1_aud_pbb3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gpio_x3_aud_pbb4 { +- nvidia,pins = "gpio_x3_aud_pbb4"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- hdmi_cec_pcc0 { +- nvidia,pins = "hdmi_cec_pcc0"; +- nvidia,function = "cec"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- hdmi_int_dp_hpd_pcc1 { +- nvidia,pins = "hdmi_int_dp_hpd_pcc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- spdif_out_pcc2 { +- nvidia,pins = "spdif_out_pcc2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spdif_in_pcc3 { +- nvidia,pins = "spdif_in_pcc3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- usb_vbus_en0_pcc4 { +- nvidia,pins = "usb_vbus_en0_pcc4"; +- nvidia,function = "usb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- usb_vbus_en1_pcc5 { +- nvidia,pins = "usb_vbus_en1_pcc5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- dp_hpd0_pcc6 { +- nvidia,pins = "dp_hpd0_pcc6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pcc7 { +- nvidia,pins = "pcc7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- spi2_cs1_pdd0 { +- nvidia,pins = "spi2_cs1_pdd0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_sck_pee0 { +- nvidia,pins = "qspi_sck_pee0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_cs_n_pee1 { +- nvidia,pins = "qspi_cs_n_pee1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io0_pee2 { +- nvidia,pins = "qspi_io0_pee2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io1_pee3 { +- nvidia,pins = "qspi_io1_pee3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io2_pee4 { +- nvidia,pins = "qspi_io2_pee4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io3_pee5 { +- nvidia,pins = "qspi_io3_pee5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- core_pwr_req { +- nvidia,pins = "core_pwr_req"; +- nvidia,function = "core"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cpu_pwr_req { +- nvidia,pins = "cpu_pwr_req"; +- nvidia,function = "cpu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pwr_int_n { +- nvidia,pins = "pwr_int_n"; +- nvidia,function = "pmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- clk_32k_in { +- nvidia,pins = "clk_32k_in"; +- nvidia,function = "clk"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- jtag_rtck { +- nvidia,pins = "jtag_rtck"; +- nvidia,function = "jtag"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- clk_req { +- nvidia,pins = "clk_req"; +- nvidia,function = "sys"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- shutdown { +- nvidia,pins = "shutdown"; +- nvidia,function = "shutdown"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2597.dtsi b/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2597.dtsi +deleted file mode 100644 +index d8409c1b4380..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2597.dtsi ++++ /dev/null +@@ -1,1715 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +- +-/ { +- model = "NVIDIA Tegra210 P2597 I/O board"; +- compatible = "nvidia,p2597", "nvidia,tegra210"; +- +- aliases { +- ethernet = "/usb@70090000/ethernet@1"; +- }; +- +- host1x@50000000 { +- dpaux@54040000 { +- status = "okay"; +- }; +- +- vi@54080000 { +- status = "okay"; +- +- avdd-dsi-csi-supply = <&vdd_dsi_csi>; +- +- csi@838 { +- status = "okay"; +- }; +- }; +- +- sor@54580000 { +- status = "okay"; +- +- avdd-io-hdmi-dp-supply = <&avdd_1v05>; +- vdd-hdmi-dp-pll-supply = <&vdd_1v8>; +- hdmi-supply = <&vdd_hdmi>; +- +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) +- GPIO_ACTIVE_LOW>; +- }; +- }; +- +- pinmux: pinmux@700008d4 { +- pinctrl-names = "boot"; +- pinctrl-0 = <&state_boot>; +- +- state_boot: pinmux { +- pex_l0_rst_n_pa0 { +- nvidia,pins = "pex_l0_rst_n_pa0"; +- nvidia,function = "pe0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_l0_clkreq_n_pa1 { +- nvidia,pins = "pex_l0_clkreq_n_pa1"; +- nvidia,function = "pe0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_wake_n_pa2 { +- nvidia,pins = "pex_wake_n_pa2"; +- nvidia,function = "pe"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_l1_rst_n_pa3 { +- nvidia,pins = "pex_l1_rst_n_pa3"; +- nvidia,function = "pe1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_l1_clkreq_n_pa4 { +- nvidia,pins = "pex_l1_clkreq_n_pa4"; +- nvidia,function = "pe1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- sata_led_active_pa5 { +- nvidia,pins = "sata_led_active_pa5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pa6 { +- nvidia,pins = "pa6"; +- nvidia,function = "sata"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_fs_pb0 { +- nvidia,pins = "dap1_fs_pb0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_din_pb1 { +- nvidia,pins = "dap1_din_pb1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_dout_pb2 { +- nvidia,pins = "dap1_dout_pb2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_sclk_pb3 { +- nvidia,pins = "dap1_sclk_pb3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_mosi_pb4 { +- nvidia,pins = "spi2_mosi_pb4"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_miso_pb5 { +- nvidia,pins = "spi2_miso_pb5"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_sck_pb6 { +- nvidia,pins = "spi2_sck_pb6"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_cs0_pb7 { +- nvidia,pins = "spi2_cs0_pb7"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_mosi_pc0 { +- nvidia,pins = "spi1_mosi_pc0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_miso_pc1 { +- nvidia,pins = "spi1_miso_pc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_sck_pc2 { +- nvidia,pins = "spi1_sck_pc2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_cs0_pc3 { +- nvidia,pins = "spi1_cs0_pc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_cs1_pc4 { +- nvidia,pins = "spi1_cs1_pc4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_sck_pc5 { +- nvidia,pins = "spi4_sck_pc5"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_cs0_pc6 { +- nvidia,pins = "spi4_cs0_pc6"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_mosi_pc7 { +- nvidia,pins = "spi4_mosi_pc7"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_miso_pd0 { +- nvidia,pins = "spi4_miso_pd0"; +- nvidia,function = "spi4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_tx_pd1 { +- nvidia,pins = "uart3_tx_pd1"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_rx_pd2 { +- nvidia,pins = "uart3_rx_pd2"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_rts_pd3 { +- nvidia,pins = "uart3_rts_pd3"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_cts_pd4 { +- nvidia,pins = "uart3_cts_pd4"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic1_clk_pe0 { +- nvidia,pins = "dmic1_clk_pe0"; +- nvidia,function = "i2s3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic1_dat_pe1 { +- nvidia,pins = "dmic1_dat_pe1"; +- nvidia,function = "i2s3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic2_clk_pe2 { +- nvidia,pins = "dmic2_clk_pe2"; +- nvidia,function = "i2s3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic2_dat_pe3 { +- nvidia,pins = "dmic2_dat_pe3"; +- nvidia,function = "i2s3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic3_clk_pe4 { +- nvidia,pins = "dmic3_clk_pe4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic3_dat_pe5 { +- nvidia,pins = "dmic3_dat_pe5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pe6 { +- nvidia,pins = "pe6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pe7 { +- nvidia,pins = "pe7"; +- nvidia,function = "pwm3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen3_i2c_scl_pf0 { +- nvidia,pins = "gen3_i2c_scl_pf0"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen3_i2c_sda_pf1 { +- nvidia,pins = "gen3_i2c_sda_pf1"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- uart2_tx_pg0 { +- nvidia,pins = "uart2_tx_pg0"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart2_rx_pg1 { +- nvidia,pins = "uart2_rx_pg1"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart2_rts_pg2 { +- nvidia,pins = "uart2_rts_pg2"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart2_cts_pg3 { +- nvidia,pins = "uart2_cts_pg3"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- wifi_en_ph0 { +- nvidia,pins = "wifi_en_ph0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- wifi_rst_ph1 { +- nvidia,pins = "wifi_rst_ph1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- wifi_wake_ap_ph2 { +- nvidia,pins = "wifi_wake_ap_ph2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ap_wake_bt_ph3 { +- nvidia,pins = "ap_wake_bt_ph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- bt_rst_ph4 { +- nvidia,pins = "bt_rst_ph4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- bt_wake_ap_ph5 { +- nvidia,pins = "bt_wake_ap_ph5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ph6 { +- nvidia,pins = "ph6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ap_wake_nfc_ph7 { +- nvidia,pins = "ap_wake_nfc_ph7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- nfc_en_pi0 { +- nvidia,pins = "nfc_en_pi0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- nfc_int_pi1 { +- nvidia,pins = "nfc_int_pi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gps_en_pi2 { +- nvidia,pins = "gps_en_pi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gps_rst_pi3 { +- nvidia,pins = "gps_rst_pi3"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_tx_pi4 { +- nvidia,pins = "uart4_tx_pi4"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_rx_pi5 { +- nvidia,pins = "uart4_rx_pi5"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_rts_pi6 { +- nvidia,pins = "uart4_rts_pi6"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_cts_pi7 { +- nvidia,pins = "uart4_cts_pi7"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen1_i2c_sda_pj0 { +- nvidia,pins = "gen1_i2c_sda_pj0"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen1_i2c_scl_pj1 { +- nvidia,pins = "gen1_i2c_scl_pj1"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen2_i2c_scl_pj2 { +- nvidia,pins = "gen2_i2c_scl_pj2"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen2_i2c_sda_pj3 { +- nvidia,pins = "gen2_i2c_sda_pj3"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- dap4_fs_pj4 { +- nvidia,pins = "dap4_fs_pj4"; +- nvidia,function = "i2s4b"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap4_din_pj5 { +- nvidia,pins = "dap4_din_pj5"; +- nvidia,function = "i2s4b"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap4_dout_pj6 { +- nvidia,pins = "dap4_dout_pj6"; +- nvidia,function = "i2s4b"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap4_sclk_pj7 { +- nvidia,pins = "dap4_sclk_pj7"; +- nvidia,function = "i2s4b"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk0 { +- nvidia,pins = "pk0"; +- nvidia,function = "i2s5b"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk1 { +- nvidia,pins = "pk1"; +- nvidia,function = "i2s5b"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk2 { +- nvidia,pins = "pk2"; +- nvidia,function = "i2s5b"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk3 { +- nvidia,pins = "pk3"; +- nvidia,function = "i2s5b"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk4 { +- nvidia,pins = "pk4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk5 { +- nvidia,pins = "pk5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk6 { +- nvidia,pins = "pk6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk7 { +- nvidia,pins = "pk7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pl0 { +- nvidia,pins = "pl0"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pl1 { +- nvidia,pins = "pl1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_clk_pm0 { +- nvidia,pins = "sdmmc1_clk_pm0"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_cmd_pm1 { +- nvidia,pins = "sdmmc1_cmd_pm1"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat3_pm2 { +- nvidia,pins = "sdmmc1_dat3_pm2"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat2_pm3 { +- nvidia,pins = "sdmmc1_dat2_pm3"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat1_pm4 { +- nvidia,pins = "sdmmc1_dat1_pm4"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat0_pm5 { +- nvidia,pins = "sdmmc1_dat0_pm5"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_clk_pp0 { +- nvidia,pins = "sdmmc3_clk_pp0"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_cmd_pp1 { +- nvidia,pins = "sdmmc3_cmd_pp1"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat3_pp2 { +- nvidia,pins = "sdmmc3_dat3_pp2"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat2_pp3 { +- nvidia,pins = "sdmmc3_dat2_pp3"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat1_pp4 { +- nvidia,pins = "sdmmc3_dat1_pp4"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat0_pp5 { +- nvidia,pins = "sdmmc3_dat0_pp5"; +- nvidia,function = "sdmmc3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam1_mclk_ps0 { +- nvidia,pins = "cam1_mclk_ps0"; +- nvidia,function = "extperiph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam2_mclk_ps1 { +- nvidia,pins = "cam2_mclk_ps1"; +- nvidia,function = "extperiph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_i2c_scl_ps2 { +- nvidia,pins = "cam_i2c_scl_ps2"; +- nvidia,function = "i2cvi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- cam_i2c_sda_ps3 { +- nvidia,pins = "cam_i2c_sda_ps3"; +- nvidia,function = "i2cvi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- cam_rst_ps4 { +- nvidia,pins = "cam_rst_ps4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_af_en_ps5 { +- nvidia,pins = "cam_af_en_ps5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_flash_en_ps6 { +- nvidia,pins = "cam_flash_en_ps6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam1_pwdn_ps7 { +- nvidia,pins = "cam1_pwdn_ps7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam2_pwdn_pt0 { +- nvidia,pins = "cam2_pwdn_pt0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam1_strobe_pt1 { +- nvidia,pins = "cam1_strobe_pt1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_tx_pu0 { +- nvidia,pins = "uart1_tx_pu0"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_rx_pu1 { +- nvidia,pins = "uart1_rx_pu1"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_rts_pu2 { +- nvidia,pins = "uart1_rts_pu2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_cts_pu3 { +- nvidia,pins = "uart1_cts_pu3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_bl_pwm_pv0 { +- nvidia,pins = "lcd_bl_pwm_pv0"; +- nvidia,function = "pwm0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_bl_en_pv1 { +- nvidia,pins = "lcd_bl_en_pv1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_rst_pv2 { +- nvidia,pins = "lcd_rst_pv2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_gpio1_pv3 { +- nvidia,pins = "lcd_gpio1_pv3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_gpio2_pv4 { +- nvidia,pins = "lcd_gpio2_pv4"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ap_ready_pv5 { +- nvidia,pins = "ap_ready_pv5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- touch_rst_pv6 { +- nvidia,pins = "touch_rst_pv6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- touch_clk_pv7 { +- nvidia,pins = "touch_clk_pv7"; +- nvidia,function = "touch"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- modem_wake_ap_px0 { +- nvidia,pins = "modem_wake_ap_px0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- touch_int_px1 { +- nvidia,pins = "touch_int_px1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- motion_int_px2 { +- nvidia,pins = "motion_int_px2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- als_prox_int_px3 { +- nvidia,pins = "als_prox_int_px3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- temp_alert_px4 { +- nvidia,pins = "temp_alert_px4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_power_on_px5 { +- nvidia,pins = "button_power_on_px5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_vol_up_px6 { +- nvidia,pins = "button_vol_up_px6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_vol_down_px7 { +- nvidia,pins = "button_vol_down_px7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_slide_sw_py0 { +- nvidia,pins = "button_slide_sw_py0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_home_py1 { +- nvidia,pins = "button_home_py1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_te_py2 { +- nvidia,pins = "lcd_te_py2"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pwr_i2c_scl_py3 { +- nvidia,pins = "pwr_i2c_scl_py3"; +- nvidia,function = "i2cpmu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pwr_i2c_sda_py4 { +- nvidia,pins = "pwr_i2c_sda_py4"; +- nvidia,function = "i2cpmu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- clk_32k_out_py5 { +- nvidia,pins = "clk_32k_out_py5"; +- nvidia,function = "soc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz0 { +- nvidia,pins = "pz0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz1 { +- nvidia,pins = "pz1"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz2 { +- nvidia,pins = "pz2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz3 { +- nvidia,pins = "pz3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz4 { +- nvidia,pins = "pz4"; +- nvidia,function = "sdmmc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz5 { +- nvidia,pins = "pz5"; +- nvidia,function = "soc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_fs_paa0 { +- nvidia,pins = "dap2_fs_paa0"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_sclk_paa1 { +- nvidia,pins = "dap2_sclk_paa1"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_din_paa2 { +- nvidia,pins = "dap2_din_paa2"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_dout_paa3 { +- nvidia,pins = "dap2_dout_paa3"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- aud_mclk_pbb0 { +- nvidia,pins = "aud_mclk_pbb0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dvfs_pwm_pbb1 { +- nvidia,pins = "dvfs_pwm_pbb1"; +- nvidia,function = "cldvfs"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dvfs_clk_pbb2 { +- nvidia,pins = "dvfs_clk_pbb2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gpio_x1_aud_pbb3 { +- nvidia,pins = "gpio_x1_aud_pbb3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gpio_x3_aud_pbb4 { +- nvidia,pins = "gpio_x3_aud_pbb4"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- hdmi_cec_pcc0 { +- nvidia,pins = "hdmi_cec_pcc0"; +- nvidia,function = "cec"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- hdmi_int_dp_hpd_pcc1 { +- nvidia,pins = "hdmi_int_dp_hpd_pcc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- spdif_out_pcc2 { +- nvidia,pins = "spdif_out_pcc2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spdif_in_pcc3 { +- nvidia,pins = "spdif_in_pcc3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- usb_vbus_en0_pcc4 { +- nvidia,pins = "usb_vbus_en0_pcc4"; +- nvidia,function = "usb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- usb_vbus_en1_pcc5 { +- nvidia,pins = "usb_vbus_en1_pcc5"; +- nvidia,function = "usb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- dp_hpd0_pcc6 { +- nvidia,pins = "dp_hpd0_pcc6"; +- nvidia,function = "dp"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pcc7 { +- nvidia,pins = "pcc7"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- spi2_cs1_pdd0 { +- nvidia,pins = "spi2_cs1_pdd0"; +- nvidia,function = "spi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_sck_pee0 { +- nvidia,pins = "qspi_sck_pee0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_cs_n_pee1 { +- nvidia,pins = "qspi_cs_n_pee1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io0_pee2 { +- nvidia,pins = "qspi_io0_pee2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io1_pee3 { +- nvidia,pins = "qspi_io1_pee3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io2_pee4 { +- nvidia,pins = "qspi_io2_pee4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io3_pee5 { +- nvidia,pins = "qspi_io3_pee5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- core_pwr_req { +- nvidia,pins = "core_pwr_req"; +- nvidia,function = "core"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cpu_pwr_req { +- nvidia,pins = "cpu_pwr_req"; +- nvidia,function = "cpu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pwr_int_n { +- nvidia,pins = "pwr_int_n"; +- nvidia,function = "pmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- clk_32k_in { +- nvidia,pins = "clk_32k_in"; +- nvidia,function = "clk"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- jtag_rtck { +- nvidia,pins = "jtag_rtck"; +- nvidia,function = "jtag"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- clk_req { +- nvidia,pins = "clk_req"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- shutdown { +- nvidia,pins = "shutdown"; +- nvidia,function = "shutdown"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- }; +- +- dvfs_pwm_active_state: dvfs_pwm_active { +- dvfs_pwm_pbb1 { +- nvidia,pins = "dvfs_pwm_pbb1"; +- nvidia,tristate = ; +- }; +- }; +- +- dvfs_pwm_inactive_state: dvfs_pwm_inactive { +- dvfs_pwm_pbb1 { +- nvidia,pins = "dvfs_pwm_pbb1"; +- nvidia,tristate = ; +- }; +- }; +- }; +- +- pwm@7000a000 { +- status = "okay"; +- }; +- +- i2c@7000c400 { +- status = "okay"; +- clock-frequency = <100000>; +- +- exp1: gpio@74 { +- compatible = "ti,tca9539"; +- reg = <0x74>; +- +- #gpio-cells = <2>; +- gpio-controller; +- }; +- +- exp2: gpio@77 { +- compatible = "ti,tca9539"; +- reg = <0x77>; +- +- #gpio-cells = <2>; +- gpio-controller; +- }; +- }; +- +- /* HDMI DDC */ +- hdmi_ddc: i2c@7000c700 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- sata@70020000 { +- status = "okay"; +- phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; +- }; +- +- hda@70030000 { +- nvidia,model = "NVIDIA Jetson TX1 HDA"; +- status = "okay"; +- }; +- +- usb@70090000 { +- phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, +- <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, +- <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, +- <&{/padctl@7009f000/pads/usb2/lanes/usb2-3}>, +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>, +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>; +- phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0", +- "usb3-1"; +- dvddio-pex-supply = <&vdd_pex_1v05>; +- hvddio-pex-supply = <&vdd_1v8>; +- avdd-usb-supply = <&vdd_3v3_sys>; +- /* XXX what are these? */ +- avdd-pll-utmip-supply = <&vdd_1v8>; +- avdd-pll-uerefe-supply = <&vdd_pex_1v05>; +- dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>; +- hvdd-usb-ss-pll-e-supply = <&vdd_1v8>; +- +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethernet@1 { +- reg = <1>; +- }; +- }; +- +- padctl@7009f000 { +- status = "okay"; +- +- avdd-pll-utmip-supply = <&vdd_1v8>; +- avdd-pll-uerefe-supply = <&avdd_1v05_pll>; +- dvdd-pex-pll-supply = <&vdd_pex_1v05>; +- hvdd-pex-pll-e-supply = <&vdd_1v8>; +- +- pads { +- usb2 { +- status = "okay"; +- +- lanes { +- micro_b: usb2-0 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- +- usb2-1 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- +- usb2-2 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- +- usb2-3 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- }; +- }; +- +- pcie { +- status = "okay"; +- +- lanes { +- pcie-0 { +- nvidia,function = "pcie-x1"; +- status = "okay"; +- }; +- +- pcie-1 { +- nvidia,function = "pcie-x4"; +- status = "okay"; +- }; +- +- pcie-2 { +- nvidia,function = "pcie-x4"; +- status = "okay"; +- }; +- +- pcie-3 { +- nvidia,function = "pcie-x4"; +- status = "okay"; +- }; +- +- pcie-4 { +- nvidia,function = "pcie-x4"; +- status = "okay"; +- }; +- +- pcie-5 { +- nvidia,function = "usb3-ss"; +- status = "okay"; +- }; +- +- pcie-6 { +- nvidia,function = "usb3-ss"; +- status = "okay"; +- }; +- }; +- }; +- +- sata { +- status = "okay"; +- +- lanes { +- sata-0 { +- nvidia,function = "sata"; +- status = "okay"; +- }; +- }; +- }; +- }; +- +- ports { +- usb2-0 { +- status = "okay"; +- vbus-supply = <&vdd_usb_vbus_otg>; +- usb-role-switch; +- mode = "otg"; +- +- connector { +- compatible = "gpio-usb-b-connector", +- "usb-b-connector"; +- label = "micro-USB"; +- type = "micro"; +- vbus-gpios = <&gpio TEGRA_GPIO(Z, 0) +- GPIO_ACTIVE_LOW>; +- id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- usb2-1 { +- status = "okay"; +- vbus-supply = <&vdd_5v0_rtl>; +- mode = "host"; +- }; +- +- usb2-2 { +- status = "okay"; +- vbus-supply = <&vdd_usb_vbus>; +- mode = "host"; +- }; +- +- usb2-3 { +- status = "okay"; +- mode = "host"; +- }; +- +- usb3-0 { +- nvidia,usb2-companion = <1>; +- status = "okay"; +- }; +- +- usb3-1 { +- nvidia,usb2-companion = <2>; +- status = "okay"; +- }; +- }; +- }; +- +- /* MMC/SD */ +- mmc@700b0000 { +- status = "okay"; +- bus-width = <4>; +- +- cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; +- +- vqmmc-supply = <&vddio_sdmmc>; +- vmmc-supply = <&vdd_3v3_sd>; +- }; +- +- usb@700d0000 { +- status = "okay"; +- phys = <µ_b>; +- phy-names = "usb2-0"; +- avddio-usb-supply = <&vdd_3v3_sys>; +- hvdd-usb-supply = <&vdd_1v8>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- label = "gpio-keys"; +- +- power { +- label = "Power"; +- gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- +- volume_down { +- label = "Volume Down"; +- gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- volume_up { +- label = "Volume Up"; +- gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- vdd_sys_mux: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_SYS_MUX"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_5v0_sys: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_5V0_SYS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_sys_mux>; +- }; +- +- vdd_3v3_sys: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_3V3_SYS"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_sys_mux>; +- +- regulator-enable-ramp-delay = <160>; +- regulator-disable-ramp-delay = <10000>; +- }; +- +- vdd_5v0_io: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_5V0_IO_SYS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_3v3_sd: regulator@4 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_3V3_SD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_3v3_sys>; +- +- regulator-enable-ramp-delay = <472>; +- regulator-disable-ramp-delay = <4880>; +- }; +- +- vdd_dsi_csi: regulator@5 { +- compatible = "regulator-fixed"; +- regulator-name = "AVDD_DSI_CSI_1V2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- vin-supply = <&vdd_sys_1v2>; +- }; +- +- vdd_3v3_dis: regulator@6 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_DIS_3V3_LCD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_3v3_sys>; +- }; +- +- vdd_1v8_dis: regulator@7 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_LCD_1V8_DIS"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- gpio = <&exp1 14 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_1v8>; +- }; +- +- vdd_5v0_rtl: regulator@8 { +- compatible = "regulator-fixed"; +- regulator-name = "RTL_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_usb_vbus: regulator@9 { +- compatible = "regulator-fixed"; +- regulator-name = "USB_VBUS_EN1"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_hdmi: regulator@10 { +- compatible = "regulator-fixed"; +- regulator-name = "VDD_HDMI_5V0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&exp1 12 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_cam_1v2: regulator@11 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-cam-1v2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- gpio = <&exp2 10 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_3v3_sys>; +- }; +- +- vdd_cam_2v8: regulator@12 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-cam-2v8"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- gpio = <&exp1 13 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_3v3_sys>; +- }; +- +- vdd_cam_1v8: regulator@13 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-cam-1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&exp2 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_3v3_sys>; +- }; +- +- vdd_usb_vbus_otg: regulator@14 { +- compatible = "regulator-fixed"; +- regulator-name = "USB_VBUS_EN0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <&vdd_5v0_sys>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2894-0050-a08.dts b/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2894-0050-a08.dts +deleted file mode 100644 +index 7ffb351b5882..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2894-0050-a08.dts ++++ /dev/null +@@ -1,9 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "tegra210-p2894.dtsi" +- +-/ { +- model = "NVIDIA Shield TV"; +- compatible = "nvidia,p2894-0050-a08", "nvidia,darcy", "nvidia,tegra210"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2894.dtsi b/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2894.dtsi +deleted file mode 100644 +index 41beab626d95..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2894.dtsi ++++ /dev/null +@@ -1,1832 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include +-#include +-#include +-#include +-#include "tegra210.dtsi" +- +-/ { +- aliases { +- serial0 = &uarta; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0xc0000000>; +- }; +- +- pinmux: pinmux@700008d4 { +- status = "okay"; +- pinctrl-names = "boot"; +- pinctrl-0 = <&state_boot>; +- +- state_boot: pinmux { +- pex_l0_rst_n_pa0 { +- nvidia,pins = "pex_l0_rst_n_pa0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_l0_clkreq_n_pa1 { +- nvidia,pins = "pex_l0_clkreq_n_pa1"; +- nvidia,function = "pe0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_wake_n_pa2 { +- nvidia,pins = "pex_wake_n_pa2"; +- nvidia,function = "pe"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_l1_rst_n_pa3 { +- nvidia,pins = "pex_l1_rst_n_pa3"; +- nvidia,function = "pe1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_l1_clkreq_n_pa4 { +- nvidia,pins = "pex_l1_clkreq_n_pa4"; +- nvidia,function = "pe1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- sata_led_active_pa5 { +- nvidia,pins = "sata_led_active_pa5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pa6 { +- nvidia,pins = "pa6"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_fs_pb0 { +- nvidia,pins = "dap1_fs_pb0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_din_pb1 { +- nvidia,pins = "dap1_din_pb1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_dout_pb2 { +- nvidia,pins = "dap1_dout_pb2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_sclk_pb3 { +- nvidia,pins = "dap1_sclk_pb3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_mosi_pb4 { +- nvidia,pins = "spi2_mosi_pb4"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_miso_pb5 { +- nvidia,pins = "spi2_miso_pb5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_sck_pb6 { +- nvidia,pins = "spi2_sck_pb6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_cs0_pb7 { +- nvidia,pins = "spi2_cs0_pb7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_mosi_pc0 { +- nvidia,pins = "spi1_mosi_pc0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_miso_pc1 { +- nvidia,pins = "spi1_miso_pc1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_sck_pc2 { +- nvidia,pins = "spi1_sck_pc2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_cs0_pc3 { +- nvidia,pins = "spi1_cs0_pc3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_cs1_pc4 { +- nvidia,pins = "spi1_cs1_pc4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_sck_pc5 { +- nvidia,pins = "spi4_sck_pc5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_cs0_pc6 { +- nvidia,pins = "spi4_cs0_pc6"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_mosi_pc7 { +- nvidia,pins = "spi4_mosi_pc7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_miso_pd0 { +- nvidia,pins = "spi4_miso_pd0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_tx_pd1 { +- nvidia,pins = "uart3_tx_pd1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_rx_pd2 { +- nvidia,pins = "uart3_rx_pd2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_rts_pd3 { +- nvidia,pins = "uart3_rts_pd3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_cts_pd4 { +- nvidia,pins = "uart3_cts_pd4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic1_clk_pe0 { +- nvidia,pins = "dmic1_clk_pe0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic1_dat_pe1 { +- nvidia,pins = "dmic1_dat_pe1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic2_clk_pe2 { +- nvidia,pins = "dmic2_clk_pe2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic2_dat_pe3 { +- nvidia,pins = "dmic2_dat_pe3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic3_clk_pe4 { +- nvidia,pins = "dmic3_clk_pe4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic3_dat_pe5 { +- nvidia,pins = "dmic3_dat_pe5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pe6 { +- nvidia,pins = "pe6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pe7 { +- nvidia,pins = "pe7"; +- nvidia,function = "pwm3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen3_i2c_scl_pf0 { +- nvidia,pins = "gen3_i2c_scl_pf0"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen3_i2c_sda_pf1 { +- nvidia,pins = "gen3_i2c_sda_pf1"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- uart2_tx_pg0 { +- nvidia,pins = "uart2_tx_pg0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart2_rx_pg1 { +- nvidia,pins = "uart2_rx_pg1"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart2_rts_pg2 { +- nvidia,pins = "uart2_rts_pg2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart2_cts_pg3 { +- nvidia,pins = "uart2_cts_pg3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- wifi_en_ph0 { +- nvidia,pins = "wifi_en_ph0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- wifi_rst_ph1 { +- nvidia,pins = "wifi_rst_ph1"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- wifi_wake_ap_ph2 { +- nvidia,pins = "wifi_wake_ap_ph2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ap_wake_bt_ph3 { +- nvidia,pins = "ap_wake_bt_ph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- bt_rst_ph4 { +- nvidia,pins = "bt_rst_ph4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- bt_wake_ap_ph5 { +- nvidia,pins = "bt_wake_ap_ph5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ph6 { +- nvidia,pins = "ph6"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ap_wake_nfc_ph7 { +- nvidia,pins = "ap_wake_nfc_ph7"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- nfc_en_pi0 { +- nvidia,pins = "nfc_en_pi0"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- nfc_int_pi1 { +- nvidia,pins = "nfc_int_pi1"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gps_en_pi2 { +- nvidia,pins = "gps_en_pi2"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gps_rst_pi3 { +- nvidia,pins = "gps_rst_pi3"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_tx_pi4 { +- nvidia,pins = "uart4_tx_pi4"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_rx_pi5 { +- nvidia,pins = "uart4_rx_pi5"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_rts_pi6 { +- nvidia,pins = "uart4_rts_pi6"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_cts_pi7 { +- nvidia,pins = "uart4_cts_pi7"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen1_i2c_sda_pj0 { +- nvidia,pins = "gen1_i2c_sda_pj0"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen1_i2c_scl_pj1 { +- nvidia,pins = "gen1_i2c_scl_pj1"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen2_i2c_scl_pj2 { +- nvidia,pins = "gen2_i2c_scl_pj2"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen2_i2c_sda_pj3 { +- nvidia,pins = "gen2_i2c_sda_pj3"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- dap4_fs_pj4 { +- nvidia,pins = "dap4_fs_pj4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap4_din_pj5 { +- nvidia,pins = "dap4_din_pj5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap4_dout_pj6 { +- nvidia,pins = "dap4_dout_pj6"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap4_sclk_pj7 { +- nvidia,pins = "dap4_sclk_pj7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk0 { +- nvidia,pins = "pk0"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk1 { +- nvidia,pins = "pk1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk2 { +- nvidia,pins = "pk2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk3 { +- nvidia,pins = "pk3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk4 { +- nvidia,pins = "pk4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk5 { +- nvidia,pins = "pk5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk6 { +- nvidia,pins = "pk6"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk7 { +- nvidia,pins = "pk7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pl0 { +- nvidia,pins = "pl0"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pl1 { +- nvidia,pins = "pl1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_clk_pm0 { +- nvidia,pins = "sdmmc1_clk_pm0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_cmd_pm1 { +- nvidia,pins = "sdmmc1_cmd_pm1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat3_pm2 { +- nvidia,pins = "sdmmc1_dat3_pm2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat2_pm3 { +- nvidia,pins = "sdmmc1_dat2_pm3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat1_pm4 { +- nvidia,pins = "sdmmc1_dat1_pm4"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat0_pm5 { +- nvidia,pins = "sdmmc1_dat0_pm5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_clk_pp0 { +- nvidia,pins = "sdmmc3_clk_pp0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_cmd_pp1 { +- nvidia,pins = "sdmmc3_cmd_pp1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat3_pp2 { +- nvidia,pins = "sdmmc3_dat3_pp2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat2_pp3 { +- nvidia,pins = "sdmmc3_dat2_pp3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat1_pp4 { +- nvidia,pins = "sdmmc3_dat1_pp4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat0_pp5 { +- nvidia,pins = "sdmmc3_dat0_pp5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam1_mclk_ps0 { +- nvidia,pins = "cam1_mclk_ps0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam2_mclk_ps1 { +- nvidia,pins = "cam2_mclk_ps1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_i2c_scl_ps2 { +- nvidia,pins = "cam_i2c_scl_ps2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- cam_i2c_sda_ps3 { +- nvidia,pins = "cam_i2c_sda_ps3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- cam_rst_ps4 { +- nvidia,pins = "cam_rst_ps4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_af_en_ps5 { +- nvidia,pins = "cam_af_en_ps5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_flash_en_ps6 { +- nvidia,pins = "cam_flash_en_ps6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam1_pwdn_ps7 { +- nvidia,pins = "cam1_pwdn_ps7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam2_pwdn_pt0 { +- nvidia,pins = "cam2_pwdn_pt0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam1_strobe_pt1 { +- nvidia,pins = "cam1_strobe_pt1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_tx_pu0 { +- nvidia,pins = "uart1_tx_pu0"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_rx_pu1 { +- nvidia,pins = "uart1_rx_pu1"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_rts_pu2 { +- nvidia,pins = "uart1_rts_pu2"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_cts_pu3 { +- nvidia,pins = "uart1_cts_pu3"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_bl_pwm_pv0 { +- nvidia,pins = "lcd_bl_pwm_pv0"; +- nvidia,function = "pwm0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_bl_en_pv1 { +- nvidia,pins = "lcd_bl_en_pv1"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_rst_pv2 { +- nvidia,pins = "lcd_rst_pv2"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_gpio1_pv3 { +- nvidia,pins = "lcd_gpio1_pv3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_gpio2_pv4 { +- nvidia,pins = "lcd_gpio2_pv4"; +- nvidia,function = "pwm1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ap_ready_pv5 { +- nvidia,pins = "ap_ready_pv5"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- touch_rst_pv6 { +- nvidia,pins = "touch_rst_pv6"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- touch_clk_pv7 { +- nvidia,pins = "touch_clk_pv7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- modem_wake_ap_px0 { +- nvidia,pins = "modem_wake_ap_px0"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- touch_int_px1 { +- nvidia,pins = "touch_int_px1"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- motion_int_px2 { +- nvidia,pins = "motion_int_px2"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- als_prox_int_px3 { +- nvidia,pins = "als_prox_int_px3"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- temp_alert_px4 { +- nvidia,pins = "temp_alert_px4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_power_on_px5 { +- nvidia,pins = "button_power_on_px5"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_vol_up_px6 { +- nvidia,pins = "button_vol_up_px6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_vol_down_px7 { +- nvidia,pins = "button_vol_down_px7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_slide_sw_py0 { +- nvidia,pins = "button_slide_sw_py0"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_home_py1 { +- nvidia,pins = "button_home_py1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_te_py2 { +- nvidia,pins = "lcd_te_py2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pwr_i2c_scl_py3 { +- nvidia,pins = "pwr_i2c_scl_py3"; +- nvidia,function = "i2cpmu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pwr_i2c_sda_py4 { +- nvidia,pins = "pwr_i2c_sda_py4"; +- nvidia,function = "i2cpmu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- clk_32k_out_py5 { +- nvidia,pins = "clk_32k_out_py5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz0 { +- nvidia,pins = "pz0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz1 { +- nvidia,pins = "pz1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz2 { +- nvidia,pins = "pz2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz3 { +- nvidia,pins = "pz3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz4 { +- nvidia,pins = "pz4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz5 { +- nvidia,pins = "pz5"; +- nvidia,function = "soc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_fs_paa0 { +- nvidia,pins = "dap2_fs_paa0"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_sclk_paa1 { +- nvidia,pins = "dap2_sclk_paa1"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_din_paa2 { +- nvidia,pins = "dap2_din_paa2"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_dout_paa3 { +- nvidia,pins = "dap2_dout_paa3"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- aud_mclk_pbb0 { +- nvidia,pins = "aud_mclk_pbb0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dvfs_pwm_pbb1 { +- nvidia,pins = "dvfs_pwm_pbb1"; +- nvidia,function = "cldvfs"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dvfs_clk_pbb2 { +- nvidia,pins = "dvfs_clk_pbb2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gpio_x1_aud_pbb3 { +- nvidia,pins = "gpio_x1_aud_pbb3"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gpio_x3_aud_pbb4 { +- nvidia,pins = "gpio_x3_aud_pbb4"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- hdmi_cec_pcc0 { +- nvidia,pins = "hdmi_cec_pcc0"; +- nvidia,function = "cec"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- hdmi_int_dp_hpd_pcc1 { +- nvidia,pins = "hdmi_int_dp_hpd_pcc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- spdif_out_pcc2 { +- nvidia,pins = "spdif_out_pcc2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spdif_in_pcc3 { +- nvidia,pins = "spdif_in_pcc3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- usb_vbus_en0_pcc4 { +- nvidia,pins = "usb_vbus_en0_pcc4"; +- nvidia,function = "usb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- usb_vbus_en1_pcc5 { +- nvidia,pins = "usb_vbus_en1_pcc5"; +- nvidia,function = "usb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- dp_hpd0_pcc6 { +- nvidia,pins = "dp_hpd0_pcc6"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pcc7 { +- nvidia,pins = "pcc7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- spi2_cs1_pdd0 { +- nvidia,pins = "spi2_cs1_pdd0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_sck_pee0 { +- nvidia,pins = "qspi_sck_pee0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_cs_n_pee1 { +- nvidia,pins = "qspi_cs_n_pee1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io0_pee2 { +- nvidia,pins = "qspi_io0_pee2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io1_pee3 { +- nvidia,pins = "qspi_io1_pee3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io2_pee4 { +- nvidia,pins = "qspi_io2_pee4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io3_pee5 { +- nvidia,pins = "qspi_io3_pee5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- core_pwr_req { +- nvidia,pins = "core_pwr_req"; +- nvidia,function = "core"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cpu_pwr_req { +- nvidia,pins = "cpu_pwr_req"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pwr_int_n { +- nvidia,pins = "pwr_int_n"; +- nvidia,function = "pmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- clk_32k_in { +- nvidia,pins = "clk_32k_in"; +- nvidia,function = "clk"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- jtag_rtck { +- nvidia,pins = "jtag_rtck"; +- nvidia,function = "jtag"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- clk_req { +- nvidia,pins = "clk_req"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- shutdown { +- nvidia,pins = "shutdown"; +- nvidia,function = "shutdown"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- }; +- }; +- +- serial@70006000 { +- status = "okay"; +- }; +- +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- pmic: pmic@3c { +- compatible = "maxim,max77620"; +- reg = <0x3c>; +- interrupts = ; +- +- #interrupt-cells = <2>; +- interrupt-controller; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&max77620_default>; +- +- max77620_default: pinmux@0 { +- gpio0 { +- pins = "gpio0"; +- function = "gpio"; +- }; +- +- gpio1 { +- pins = "gpio1"; +- function = "fps-out"; +- drive-push-pull = <1>; +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <7>; +- maxim,active-fps-power-down-slot = <0>; +- }; +- +- gpio2 { +- pins = "gpio2"; +- function = "fps-out"; +- drive-open-drain = <1>; +- maxim,active-fps-source = ; +- }; +- +- gpio3 { +- pins = "gpio3"; +- function = "fps-out"; +- drive-open-drain = <1>; +- maxim,active-fps-source = ; +- }; +- +- gpio4 { +- pins = "gpio4"; +- function = "32k-out1"; +- }; +- +- gpio5_6_7 { +- pins = "gpio5", "gpio6", "gpio7"; +- function = "gpio"; +- drive-push-pull = <1>; +- }; +- }; +- +- gpio@0 { +- gpio-hog; +- output-high; +- gpios = <2 GPIO_ACTIVE_HIGH>, +- <7 GPIO_ACTIVE_HIGH>; +- }; +- +- fps { +- #address-cells = <1>; +- #size-cells = <0>; +- +- fps0 { +- reg = <0>; +- maxim,fps-event-source = ; +- }; +- +- fps1 { +- reg = <1>; +- maxim,fps-event-source = ; +- maxim,device-state-on-disabled-event = ; +- }; +- +- fps2 { +- reg = <2>; +- maxim,fps-event-source = ; +- }; +- }; +- +- regulators { +- in-ldo0-1-supply = <&max77620_sd2>; +- in-ldo7-8-supply = <&max77620_sd2>; +- +- max77620_sd0: sd0 { +- regulator-name = "vdd-core"; +- regulator-enable-ramp-delay = <146>; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1400000>; +- regulator-ramp-delay = <27500>; +- regulator-always-on; +- regulator-boot-on; +- +- maxim,active-fps-power-up-slot = <0>; +- maxim,active-fps-source = ; +- }; +- +- max77620_sd1: sd1 { +- regulator-name = "vddio-ddr"; +- regulator-enable-ramp-delay = <130>; +- regulator-ramp-delay = <27500>; +- regulator-always-on; +- regulator-boot-on; +- +- maxim,active-fps-source = ; +- }; +- +- max77620_sd2: sd2 { +- regulator-name = "vdd-pre-reg"; +- regulator-enable-ramp-delay = <176>; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-ramp-delay = <27500>; +- regulator-always-on; +- regulator-boot-on; +- +- maxim,active-fps-source = ; +- maxim,suspend-fps-source = ; +- }; +- +- max77620_sd3: sd3 { +- regulator-name = "vdd-1v8"; +- regulator-enable-ramp-delay = <242>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-ramp-delay = <27500>; +- regulator-always-on; +- regulator-boot-on; +- +- maxim,active-fps-source = ; +- }; +- +- max77620_ldo0: ldo0 { +- regulator-name = "avdd-sys"; +- regulator-enable-ramp-delay = <26>; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-ramp-delay = <100000>; +- regulator-boot-on; +- +- maxim,active-fps-source = ; +- }; +- +- max77620_ldo1: ldo1 { +- regulator-name = "vdd-pex"; +- regulator-enable-ramp-delay = <22>; +- regulator-min-microvolt = <1075000>; +- regulator-max-microvolt = <1075000>; +- regulator-ramp-delay = <100000>; +- regulator-always-on; +- +- maxim,active-fps-source = ; +- }; +- +- max77620_ldo2: ldo2 { +- regulator-name = "vddio-sdmmc3"; +- regulator-enable-ramp-delay = <62>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-ramp-delay = <100000>; +- +- maxim,active-fps-source = ; +- }; +- +- max77620_ldo3: ldo3 { +- regulator-name = "vdd-3v3-eth"; +- regulator-enable-ramp-delay = <50>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-ramp-delay = <100000>; +- regulator-always-on; +- regulator-boot-on; +- +- maxim,active-fps-source = ; +- }; +- +- max77620_ldo4: ldo4 { +- regulator-name = "vdd-rtc"; +- regulator-enable-ramp-delay = <22>; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <850000>; +- regulator-ramp-delay = <100000>; +- regulator-always-on; +- regulator-boot-on; +- +- maxim,active-fps-source = ; +- }; +- +- max77620_ldo5: ldo5 { +- regulator-name = "avdd-ts-hv"; +- regulator-enable-ramp-delay = <62>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-ramp-delay = <100000>; +- +- maxim,active-fps-source = ; +- }; +- +- max77620_ldo6: ldo6 { +- regulator-name = "vdd-ts"; +- regulator-enable-ramp-delay = <36>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-ramp-delay = <100000>; +- regulator-boot-on; +- +- maxim,active-fps-source = ; +- }; +- +- max77620_ldo7: ldo7 { +- regulator-name = "vdd-gen-pll-edp"; +- regulator-enable-ramp-delay = <24>; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-ramp-delay = <100000>; +- regulator-always-on; +- regulator-boot-on; +- +- maxim,active-fps-source = ; +- maxim,suspend-fps-source = ; +- }; +- +- max77620_ldo8: ldo8 { +- regulator-name = "vdd-hdmi-dp"; +- regulator-enable-ramp-delay = <22>; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-ramp-delay = <100000>; +- regulator-always-on; +- regulator-boot-on; +- +- maxim,active-fps-source = ; +- }; +- }; +- }; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <0>; +- nvidia,cpu-pwr-good-time = <0>; +- nvidia,cpu-pwr-off-time = <0>; +- nvidia,core-pwr-good-time = <4587 3876>; +- nvidia,core-pwr-off-time = <39065>; +- nvidia,core-power-req-active-high; +- nvidia,sys-clock-req-active-high; +- status = "okay"; +- }; +- +- mmc@700b0600 { +- bus-width = <8>; +- non-removable; +- status = "okay"; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- status = "okay"; +- +- power { +- debounce-interval = <30>; +- gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; +- label = "Power"; +- linux,code = ; +- wakeup-event-action = ; +- wakeup-source; +- }; +- }; +- +- cpus { +- cpu@0 { +- enable-method = "psci"; +- }; +- +- cpu@1 { +- enable-method = "psci"; +- }; +- +- cpu@2 { +- enable-method = "psci"; +- }; +- +- cpu@3 { +- enable-method = "psci"; +- }; +- +- idle-states { +- cpu-sleep { +- status = "okay"; +- }; +- }; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- battery_reg: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-ac-bat"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- vdd_3v3: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-3v3"; +- regulator-enable-ramp-delay = <160>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- +- gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- max77620_gpio7: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "max77620-gpio7"; +- regulator-enable-ramp-delay = <240>; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- vin-supply = <&max77620_ldo0>; +- regulator-always-on; +- regulator-boot-on; +- +- gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- lcd_bl_en: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "lcd-bl-en"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- +- gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- en_vdd_sd: regulator@4 { +- compatible = "regulator-fixed"; +- regulator-name = "en-vdd-sd"; +- regulator-enable-ramp-delay = <472>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vdd_3v3>; +- +- gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- en_vdd_cam: regulator@5 { +- compatible = "regulator-fixed"; +- regulator-name = "en-vdd-cam"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- gpio = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vdd_sys_boost: regulator@6 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-sys-boost"; +- regulator-enable-ramp-delay = <3090>; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- +- gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vdd_hdmi: regulator@7 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-hdmi"; +- regulator-enable-ramp-delay = <468>; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vdd_sys_boost>; +- regulator-boot-on; +- +- gpio = <&gpio TEGRA_GPIO(CC, 7) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- en_vdd_cpu_fixed: regulator@8 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-cpu-fixed"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- vdd_aux_3v3: regulator@9 { +- compatible = "regulator-fixed"; +- regulator-name = "aux-3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vdd_snsr_pm: regulator@10 { +- compatible = "regulator-fixed"; +- regulator-name = "snsr_pm"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- enable-active-high; +- }; +- +- vdd_usb_5v0: regulator@11 { +- compatible = "regulator-fixed"; +- status = "disabled"; +- regulator-name = "vdd-usb-5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vdd_3v3>; +- +- enable-active-high; +- }; +- +- vdd_cdc_1v2_aud: regulator@101 { +- compatible = "regulator-fixed"; +- status = "disabled"; +- regulator-name = "vdd_cdc_1v2_aud"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- startup-delay-us = <250000>; +- +- enable-active-high; +- }; +- +- vdd_disp_3v0: regulator@12 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-disp-3v0"; +- regulator-enable-ramp-delay = <232>; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- +- gpio = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vdd_fan: regulator@13 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-fan"; +- regulator-enable-ramp-delay = <284>; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- gpio = <&gpio TEGRA_GPIO(E, 4) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- usb_vbus1: regulator@14 { +- compatible = "regulator-fixed"; +- regulator-name = "usb-vbus1"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- gpio-open-drain; +- }; +- +- usb_vbus2: regulator@15 { +- compatible = "regulator-fixed"; +- regulator-name = "usb-vbus2"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- gpio-open-drain; +- }; +- +- vdd_3v3_eth: regulator@16 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-3v3-eth-a02"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- +- gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- gpio-open-drain; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p3450-0000.dts b/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p3450-0000.dts +deleted file mode 100644 +index 7dbb13f20de7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p3450-0000.dts ++++ /dev/null +@@ -1,1048 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +-#include +- +-#include "tegra210.dtsi" +- +-/ { +- model = "NVIDIA Jetson Nano Developer Kit"; +- compatible = "nvidia,p3450-0000", "nvidia,tegra210"; +- +- aliases { +- ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0"; +- rtc0 = "/i2c@7000d000/pmic@3c"; +- rtc1 = "/rtc@7000e000"; +- serial0 = &uarta; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x1 0x0>; +- }; +- +- pcie@1003000 { +- status = "okay"; +- +- avdd-pll-uerefe-supply = <&vdd_pex_1v05>; +- hvddio-pex-supply = <&vdd_1v8>; +- dvddio-pex-supply = <&vdd_pex_1v05>; +- dvdd-pex-pll-supply = <&vdd_pex_1v05>; +- hvdd-pex-pll-e-supply = <&vdd_1v8>; +- vddio-pex-ctl-supply = <&vdd_1v8>; +- +- pci@1,0 { +- phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>, +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; +- phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; +- nvidia,num-lanes = <4>; +- status = "okay"; +- }; +- +- pci@2,0 { +- phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; +- phy-names = "pcie-0"; +- status = "okay"; +- +- ethernet@0,0 { +- reg = <0x000000 0 0 0 0>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- }; +- }; +- +- host1x@50000000 { +- dpaux@54040000 { +- status = "okay"; +- }; +- +- vi@54080000 { +- status = "okay"; +- +- avdd-dsi-csi-supply = <&vdd_sys_1v2>; +- +- csi@838 { +- status = "okay"; +- }; +- }; +- +- sor@54540000 { +- status = "okay"; +- +- avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>; +- vdd-hdmi-dp-pll-supply = <&vdd_1v8>; +- +- nvidia,xbar-cfg = <2 1 0 3 4>; +- nvidia,dpaux = <&dpaux>; +- }; +- +- sor@54580000 { +- status = "okay"; +- +- avdd-io-hdmi-dp-supply = <&avdd_1v05>; +- vdd-hdmi-dp-pll-supply = <&vdd_1v8>; +- hdmi-supply = <&vdd_hdmi>; +- +- nvidia,ddc-i2c-bus = <&hdmi_ddc>; +- nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) +- GPIO_ACTIVE_LOW>; +- nvidia,xbar-cfg = <0 1 2 3 4>; +- }; +- +- dpaux@545c0000 { +- status = "okay"; +- }; +- +- i2c@546c0000 { +- status = "okay"; +- }; +- }; +- +- gpu@57000000 { +- vdd-supply = <&vdd_gpu>; +- status = "okay"; +- }; +- +- pinmux@700008d4 { +- dvfs_pwm_active_state: dvfs_pwm_active { +- dvfs_pwm_pbb1 { +- nvidia,pins = "dvfs_pwm_pbb1"; +- nvidia,tristate = ; +- }; +- }; +- +- dvfs_pwm_inactive_state: dvfs_pwm_inactive { +- dvfs_pwm_pbb1 { +- nvidia,pins = "dvfs_pwm_pbb1"; +- nvidia,tristate = ; +- }; +- }; +- }; +- +- /* debug port */ +- serial@70006000 { +- status = "okay"; +- }; +- +- pwm@7000a000 { +- status = "okay"; +- }; +- +- i2c@7000c500 { +- status = "okay"; +- clock-frequency = <100000>; +- +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- +- label = "module"; +- vcc-supply = <&vdd_1v8>; +- address-width = <8>; +- pagesize = <8>; +- size = <256>; +- read-only; +- }; +- +- eeprom@57 { +- compatible = "atmel,24c02"; +- reg = <0x57>; +- +- label = "system"; +- vcc-supply = <&vdd_1v8>; +- address-width = <8>; +- pagesize = <8>; +- size = <256>; +- read-only; +- }; +- }; +- +- hdmi_ddc: i2c@7000c700 { +- status = "okay"; +- clock-frequency = <100000>; +- }; +- +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <400000>; +- +- pmic: pmic@3c { +- compatible = "maxim,max77620"; +- reg = <0x3c>; +- interrupt-parent = <&tegra_pmc>; +- interrupts = <51 IRQ_TYPE_LEVEL_LOW>; +- +- #interrupt-cells = <2>; +- interrupt-controller; +- +- #gpio-cells = <2>; +- gpio-controller; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&max77620_default>; +- +- max77620_default: pinmux { +- gpio0 { +- pins = "gpio0"; +- function = "gpio"; +- }; +- +- gpio1 { +- pins = "gpio1"; +- function = "fps-out"; +- drive-push-pull = <1>; +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <0>; +- maxim,active-fps-power-down-slot = <7>; +- }; +- +- gpio2 { +- pins = "gpio2"; +- function = "fps-out"; +- drive-open-drain = <1>; +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <0>; +- maxim,active-fps-power-down-slot = <7>; +- }; +- +- gpio3 { +- pins = "gpio3"; +- function = "fps-out"; +- drive-open-drain = <1>; +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <4>; +- maxim,active-fps-power-down-slot = <3>; +- }; +- +- gpio4 { +- pins = "gpio4"; +- function = "32k-out1"; +- }; +- +- gpio5_6_7 { +- pins = "gpio5", "gpio6", "gpio7"; +- function = "gpio"; +- drive-push-pull = <1>; +- }; +- }; +- +- fps { +- fps0 { +- maxim,fps-event-source = ; +- maxim,suspend-fps-time-period-us = <5120>; +- }; +- +- fps1 { +- maxim,fps-event-source = ; +- maxim,suspend-fps-time-period-us = <5120>; +- }; +- +- fps2 { +- maxim,fps-event-source = ; +- }; +- }; +- +- regulators { +- in-ldo0-1-supply = <&vdd_pre>; +- in-ldo2-supply = <&vdd_3v3_sys>; +- in-ldo3-5-supply = <&vdd_1v8>; +- in-ldo4-6-supply = <&vdd_5v0_sys>; +- in-ldo7-8-supply = <&vdd_pre>; +- in-sd0-supply = <&vdd_5v0_sys>; +- in-sd1-supply = <&vdd_5v0_sys>; +- in-sd2-supply = <&vdd_5v0_sys>; +- in-sd3-supply = <&vdd_5v0_sys>; +- +- vdd_soc: sd0 { +- regulator-name = "VDD_SOC"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1170000>; +- regulator-enable-ramp-delay = <146>; +- regulator-disable-ramp-delay = <4080>; +- regulator-ramp-delay = <27500>; +- regulator-ramp-delay-scale = <300>; +- regulator-always-on; +- regulator-boot-on; +- +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <1>; +- maxim,active-fps-power-down-slot = <6>; +- }; +- +- vdd_ddr: sd1 { +- regulator-name = "VDD_DDR_1V1_PMIC"; +- regulator-min-microvolt = <1150000>; +- regulator-max-microvolt = <1150000>; +- regulator-enable-ramp-delay = <176>; +- regulator-disable-ramp-delay = <145800>; +- regulator-ramp-delay = <27500>; +- regulator-ramp-delay-scale = <300>; +- regulator-always-on; +- regulator-boot-on; +- +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <5>; +- maxim,active-fps-power-down-slot = <2>; +- }; +- +- vdd_pre: sd2 { +- regulator-name = "VDD_PRE_REG_1V35"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-enable-ramp-delay = <176>; +- regulator-disable-ramp-delay = <32000>; +- regulator-ramp-delay = <27500>; +- regulator-ramp-delay-scale = <350>; +- regulator-always-on; +- regulator-boot-on; +- +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <2>; +- maxim,active-fps-power-down-slot = <5>; +- }; +- +- vdd_1v8: sd3 { +- regulator-name = "VDD_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <242>; +- regulator-disable-ramp-delay = <118000>; +- regulator-ramp-delay = <27500>; +- regulator-ramp-delay-scale = <360>; +- regulator-always-on; +- regulator-boot-on; +- +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <3>; +- maxim,active-fps-power-down-slot = <4>; +- }; +- +- vdd_sys_1v2: ldo0 { +- regulator-name = "AVDD_SYS_1V2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-enable-ramp-delay = <26>; +- regulator-disable-ramp-delay = <626>; +- regulator-ramp-delay = <100000>; +- regulator-ramp-delay-scale = <200>; +- regulator-always-on; +- regulator-boot-on; +- +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <0>; +- maxim,active-fps-power-down-slot = <7>; +- }; +- +- vdd_pex_1v05: ldo1 { +- regulator-name = "VDD_PEX_1V05"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-enable-ramp-delay = <22>; +- regulator-disable-ramp-delay = <650>; +- regulator-ramp-delay = <100000>; +- regulator-ramp-delay-scale = <200>; +- +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <0>; +- maxim,active-fps-power-down-slot = <7>; +- }; +- +- vddio_sdmmc: ldo2 { +- regulator-name = "VDDIO_SDMMC"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <62>; +- regulator-disable-ramp-delay = <650>; +- regulator-ramp-delay = <100000>; +- regulator-ramp-delay-scale = <200>; +- +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <0>; +- maxim,active-fps-power-down-slot = <7>; +- }; +- +- ldo3 { +- status = "disabled"; +- }; +- +- vdd_rtc: ldo4 { +- regulator-name = "VDD_RTC"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1100000>; +- regulator-enable-ramp-delay = <22>; +- regulator-disable-ramp-delay = <610>; +- regulator-ramp-delay = <100000>; +- regulator-ramp-delay-scale = <200>; +- regulator-disable-active-discharge; +- regulator-always-on; +- regulator-boot-on; +- +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <1>; +- maxim,active-fps-power-down-slot = <6>; +- }; +- +- ldo5 { +- status = "disabled"; +- }; +- +- ldo6 { +- status = "disabled"; +- }; +- +- avdd_1v05_pll: ldo7 { +- regulator-name = "AVDD_1V05_PLL"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-enable-ramp-delay = <24>; +- regulator-disable-ramp-delay = <2768>; +- regulator-ramp-delay = <100000>; +- regulator-ramp-delay-scale = <200>; +- +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <3>; +- maxim,active-fps-power-down-slot = <4>; +- }; +- +- avdd_1v05: ldo8 { +- regulator-name = "AVDD_SATA_HDMI_DP_1V05"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-enable-ramp-delay = <22>; +- regulator-disable-ramp-delay = <1160>; +- regulator-ramp-delay = <100000>; +- regulator-ramp-delay-scale = <200>; +- +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <6>; +- maxim,active-fps-power-down-slot = <1>; +- }; +- }; +- }; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <0>; +- nvidia,cpu-pwr-good-time = <0>; +- nvidia,cpu-pwr-off-time = <0>; +- nvidia,core-pwr-good-time = <4587 3876>; +- nvidia,core-pwr-off-time = <39065>; +- nvidia,core-power-req-active-high; +- nvidia,sys-clock-req-active-high; +- }; +- +- hda@70030000 { +- nvidia,model = "NVIDIA Jetson Nano HDA"; +- +- status = "okay"; +- }; +- +- usb@70090000 { +- phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, +- <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, +- <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>; +- phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; +- +- avdd-usb-supply = <&vdd_3v3_sys>; +- dvddio-pex-supply = <&vdd_pex_1v05>; +- hvddio-pex-supply = <&vdd_1v8>; +- /* these really belong to the XUSB pad controller */ +- avdd-pll-utmip-supply = <&vdd_1v8>; +- avdd-pll-uerefe-supply = <&vdd_pex_1v05>; +- dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>; +- hvdd-usb-ss-pll-e-supply = <&vdd_1v8>; +- +- status = "okay"; +- }; +- +- padctl@7009f000 { +- status = "okay"; +- +- avdd-pll-utmip-supply = <&vdd_1v8>; +- avdd-pll-uerefe-supply = <&vdd_pex_1v05>; +- dvdd-pex-pll-supply = <&vdd_pex_1v05>; +- hvdd-pex-pll-e-supply = <&vdd_1v8>; +- +- pads { +- usb2 { +- status = "okay"; +- +- lanes { +- micro_b: usb2-0 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- +- usb2-1 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- +- usb2-2 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- }; +- }; +- +- pcie { +- status = "okay"; +- +- lanes { +- pcie-0 { +- nvidia,function = "pcie-x1"; +- status = "okay"; +- }; +- +- pcie-1 { +- nvidia,function = "pcie-x4"; +- status = "okay"; +- }; +- +- pcie-2 { +- nvidia,function = "pcie-x4"; +- status = "okay"; +- }; +- +- pcie-3 { +- nvidia,function = "pcie-x4"; +- status = "okay"; +- }; +- +- pcie-4 { +- nvidia,function = "pcie-x4"; +- status = "okay"; +- }; +- +- pcie-5 { +- nvidia,function = "usb3-ss"; +- status = "okay"; +- }; +- +- pcie-6 { +- nvidia,function = "usb3-ss"; +- status = "okay"; +- }; +- }; +- }; +- }; +- +- ports { +- usb2-0 { +- status = "okay"; +- mode = "peripheral"; +- usb-role-switch; +- +- vbus-supply = <&vdd_5v0_usb>; +- +- connector { +- compatible = "gpio-usb-b-connector", +- "usb-b-connector"; +- label = "micro-USB"; +- type = "micro"; +- vbus-gpios = <&gpio TEGRA_GPIO(CC, 4) +- GPIO_ACTIVE_LOW>; +- }; +- }; +- +- usb2-1 { +- status = "okay"; +- mode = "host"; +- }; +- +- usb2-2 { +- status = "okay"; +- mode = "host"; +- }; +- +- usb3-0 { +- status = "okay"; +- nvidia,usb2-companion = <1>; +- vbus-supply = <&vdd_hub_3v3>; +- }; +- }; +- }; +- +- mmc@700b0000 { +- status = "okay"; +- bus-width = <4>; +- +- cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; +- disable-wp; +- +- vqmmc-supply = <&vddio_sdmmc>; +- vmmc-supply = <&vdd_3v3_sd>; +- }; +- +- mmc@700b0400 { +- status = "okay"; +- bus-width = <4>; +- +- vqmmc-supply = <&vdd_1v8>; +- vmmc-supply = <&vdd_3v3_sys>; +- +- non-removable; +- cap-sdio-irq; +- keep-power-in-suspend; +- wakeup-source; +- }; +- +- usb@700d0000 { +- status = "okay"; +- phys = <µ_b>; +- phy-names = "usb2-0"; +- avddio-usb-supply = <&vdd_3v3_sys>; +- hvdd-usb-supply = <&vdd_1v8>; +- }; +- +- clock@70110000 { +- status = "okay"; +- +- nvidia,cf = <6>; +- nvidia,ci = <0>; +- nvidia,cg = <2>; +- nvidia,droop-ctrl = <0x00000f00>; +- nvidia,force-mode = <1>; +- nvidia,sample-rate = <25000>; +- +- nvidia,pwm-min-microvolts = <708000>; +- nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ +- nvidia,pwm-to-pmic; +- nvidia,pwm-tristate-microvolts = <1000000>; +- nvidia,pwm-voltage-step-microvolts = <19200>; +- +- pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; +- pinctrl-0 = <&dvfs_pwm_active_state>; +- pinctrl-1 = <&dvfs_pwm_inactive_state>; +- }; +- +- aconnect@702c0000 { +- status = "okay"; +- +- dma-controller@702e2000 { +- status = "okay"; +- }; +- +- interrupt-controller@702f9000 { +- status = "okay"; +- }; +- +- ahub@702d0800 { +- status = "okay"; +- +- admaif@702d0000 { +- status = "okay"; +- }; +- +- i2s@702d1200 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- i2s3_cif_ep: endpoint { +- remote-endpoint = <&xbar_i2s3_ep>; +- }; +- }; +- +- i2s3_port: port@1 { +- reg = <1>; +- +- i2s3_dap_ep: endpoint { +- dai-format = "i2s"; +- /* Placeholder for external Codec */ +- }; +- }; +- }; +- }; +- +- i2s@702d1300 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- i2s4_cif_ep: endpoint { +- remote-endpoint = <&xbar_i2s4_ep>; +- }; +- }; +- +- i2s4_port: port@1 { +- reg = <1>; +- +- i2s4_dap_ep: endpoint@0 { +- dai-format = "i2s"; +- /* Placeholder for external Codec */ +- }; +- }; +- }; +- }; +- +- dmic@702d4000 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- dmic1_cif_ep: endpoint@0 { +- remote-endpoint = <&xbar_dmic1_ep>; +- }; +- }; +- +- dmic1_port: port@1 { +- reg = <1>; +- +- dmic1_dap_ep: endpoint@0 { +- /* Placeholder for external Codec */ +- }; +- }; +- }; +- }; +- +- dmic@702d4100 { +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- dmic2_cif_ep: endpoint@0 { +- remote-endpoint = <&xbar_dmic2_ep>; +- }; +- }; +- +- dmic2_port: port@1 { +- reg = <1>; +- +- dmic2_dap_ep: endpoint@0 { +- /* Placeholder for external Codec */ +- }; +- }; +- }; +- }; +- +- ports { +- xbar_i2s3_port: port@c { +- reg = <0xc>; +- +- xbar_i2s3_ep: endpoint { +- remote-endpoint = <&i2s3_cif_ep>; +- }; +- }; +- +- xbar_i2s4_port: port@d { +- reg = <0xd>; +- +- xbar_i2s4_ep: endpoint { +- remote-endpoint = <&i2s4_cif_ep>; +- }; +- }; +- +- xbar_dmic1_port: port@f { +- reg = <0xf>; +- +- xbar_dmic1_ep: endpoint { +- remote-endpoint = <&dmic1_cif_ep>; +- }; +- }; +- +- xbar_dmic2_port: port@10 { +- reg = <0x10>; +- +- xbar_dmic2_ep: endpoint { +- remote-endpoint = <&dmic2_cif_ep>; +- }; +- }; +- }; +- }; +- }; +- +- spi@70410000 { +- status = "okay"; +- +- flash@0 { +- compatible = "spi-nor"; +- reg = <0>; +- spi-max-frequency = <104000000>; +- spi-tx-bus-width = <2>; +- spi-rx-bus-width = <2>; +- }; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- cpus { +- cpu@0 { +- enable-method = "psci"; +- }; +- +- cpu@1 { +- enable-method = "psci"; +- }; +- +- cpu@2 { +- enable-method = "psci"; +- }; +- +- cpu@3 { +- enable-method = "psci"; +- }; +- +- idle-states { +- cpu-sleep { +- status = "okay"; +- }; +- }; +- }; +- +- fan: fan { +- compatible = "pwm-fan"; +- pwms = <&pwm 3 45334>; +- +- cooling-levels = <0 64 128 255>; +- #cooling-cells = <2>; +- }; +- +- thermal-zones { +- cpu { +- trips { +- cpu_trip_critical: critical { +- temperature = <96500>; +- hysteresis = <0>; +- type = "critical"; +- }; +- +- cpu_trip_hot: hot { +- temperature = <70000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- cpu_trip_active: active { +- temperature = <50000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- cpu_trip_passive: passive { +- temperature = <30000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- }; +- +- cooling-maps { +- cpu-critical { +- cooling-device = <&fan 3 3>; +- trip = <&cpu_trip_critical>; +- }; +- +- cpu-hot { +- cooling-device = <&fan 2 2>; +- trip = <&cpu_trip_hot>; +- }; +- +- cpu-active { +- cooling-device = <&fan 1 1>; +- trip = <&cpu_trip_active>; +- }; +- +- cpu-passive { +- cooling-device = <&fan 0 0>; +- trip = <&cpu_trip_passive>; +- }; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "Power"; +- gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; +- linux,input-type = ; +- linux,code = ; +- debounce-interval = <30>; +- wakeup-event-action = ; +- wakeup-source; +- }; +- +- force-recovery { +- label = "Force Recovery"; +- gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; +- linux,input-type = ; +- linux,code = ; +- debounce-interval = <30>; +- }; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- vdd_5v0_sys: regulator@0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "VDD_5V0_SYS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_3v3_sys: regulator@1 { +- compatible = "regulator-fixed"; +- +- regulator-name = "VDD_3V3_SYS"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <240>; +- regulator-disable-ramp-delay = <11340>; +- regulator-always-on; +- regulator-boot-on; +- +- gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_3v3_sd: regulator@2 { +- compatible = "regulator-fixed"; +- +- regulator-name = "VDD_3V3_SD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- vin-supply = <&vdd_3v3_sys>; +- }; +- +- vdd_hdmi: regulator@3 { +- compatible = "regulator-fixed"; +- +- regulator-name = "VDD_HDMI_5V0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_hub_3v3: regulator@4 { +- compatible = "regulator-fixed"; +- +- regulator-name = "VDD_HUB_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_cpu: regulator@5 { +- compatible = "regulator-fixed"; +- +- regulator-name = "VDD_CPU"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- +- gpio = <&pmic 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- vdd_gpu: regulator@6 { +- compatible = "pwm-regulator"; +- pwms = <&pwm 1 8000>; +- +- regulator-name = "VDD_GPU"; +- regulator-min-microvolt = <710000>; +- regulator-max-microvolt = <1320000>; +- regulator-ramp-delay = <80>; +- regulator-enable-ramp-delay = <2000>; +- regulator-settling-time-us = <160>; +- +- enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- avdd_io_edp_1v05: regulator@7 { +- compatible = "regulator-fixed"; +- +- regulator-name = "AVDD_IO_EDP_1V05"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- +- gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- vin-supply = <&avdd_1v05_pll>; +- }; +- +- vdd_5v0_usb: regulator@8 { +- compatible = "regulator-fixed"; +- +- regulator-name = "VDD_5V_USB"; +- regulator-min-microvolt = <50000000>; +- regulator-max-microvolt = <50000000>; +- +- vin-supply = <&vdd_5v0_sys>; +- }; +- +- sound { +- compatible = "nvidia,tegra210-audio-graph-card"; +- status = "okay"; +- +- dais = /* FE */ +- <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, +- <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, +- <&admaif7_port>, <&admaif8_port>, <&admaif9_port>, +- <&admaif10_port>, +- /* Router */ +- <&xbar_i2s3_port>, <&xbar_i2s4_port>, +- <&xbar_dmic1_port>, <&xbar_dmic2_port>, +- /* I/O DAP Ports */ +- <&i2s3_port>, <&i2s4_port>, +- <&dmic1_port>, <&dmic2_port>; +- +- label = "NVIDIA Jetson Nano APE"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-smaug.dts b/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-smaug.dts +deleted file mode 100644 +index 131c064d6991..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-smaug.dts ++++ /dev/null +@@ -1,1879 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +-#include +- +-#include "tegra210.dtsi" +- +-/ { +- model = "Google Pixel C"; +- compatible = "google,smaug-rev8", "google,smaug-rev7", +- "google,smaug-rev6", "google,smaug-rev5", +- "google,smaug-rev4", "google,smaug-rev3", +- "google,smaug-rev2", "google,smaug-rev1", +- "google,smaug", "nvidia,tegra210"; +- +- aliases { +- serial0 = &uarta; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0xc0000000>; +- }; +- +- host1x@50000000 { +- dpaux: dpaux@545c0000 { +- status = "okay"; +- }; +- }; +- +- pinmux: pinmux@700008d4 { +- pinctrl-names = "boot"; +- pinctrl-0 = <&state_boot>; +- +- state_boot: pinmux { +- pex_l0_rst_n_pa0 { +- nvidia,pins = "pex_l0_rst_n_pa0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_l0_clkreq_n_pa1 { +- nvidia,pins = "pex_l0_clkreq_n_pa1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_wake_n_pa2 { +- nvidia,pins = "pex_wake_n_pa2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_l1_rst_n_pa3 { +- nvidia,pins = "pex_l1_rst_n_pa3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pex_l1_clkreq_n_pa4 { +- nvidia,pins = "pex_l1_clkreq_n_pa4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- sata_led_active_pa5 { +- nvidia,pins = "sata_led_active_pa5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pa6 { +- nvidia,pins = "pa6"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_fs_pb0 { +- nvidia,pins = "dap1_fs_pb0"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_din_pb1 { +- nvidia,pins = "dap1_din_pb1"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_dout_pb2 { +- nvidia,pins = "dap1_dout_pb2"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap1_sclk_pb3 { +- nvidia,pins = "dap1_sclk_pb3"; +- nvidia,function = "i2s1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_mosi_pb4 { +- nvidia,pins = "spi2_mosi_pb4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_miso_pb5 { +- nvidia,pins = "spi2_miso_pb5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_sck_pb6 { +- nvidia,pins = "spi2_sck_pb6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi2_cs0_pb7 { +- nvidia,pins = "spi2_cs0_pb7"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_mosi_pc0 { +- nvidia,pins = "spi1_mosi_pc0"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_miso_pc1 { +- nvidia,pins = "spi1_miso_pc1"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_sck_pc2 { +- nvidia,pins = "spi1_sck_pc2"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_cs0_pc3 { +- nvidia,pins = "spi1_cs0_pc3"; +- nvidia,function = "spi1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi1_cs1_pc4 { +- nvidia,pins = "spi1_cs1_pc4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_sck_pc5 { +- nvidia,pins = "spi4_sck_pc5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_cs0_pc6 { +- nvidia,pins = "spi4_cs0_pc6"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_mosi_pc7 { +- nvidia,pins = "spi4_mosi_pc7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spi4_miso_pd0 { +- nvidia,pins = "spi4_miso_pd0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_tx_pd1 { +- nvidia,pins = "uart3_tx_pd1"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_rx_pd2 { +- nvidia,pins = "uart3_rx_pd2"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_rts_pd3 { +- nvidia,pins = "uart3_rts_pd3"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart3_cts_pd4 { +- nvidia,pins = "uart3_cts_pd4"; +- nvidia,function = "uartc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic1_clk_pe0 { +- nvidia,pins = "dmic1_clk_pe0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic1_dat_pe1 { +- nvidia,pins = "dmic1_dat_pe1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic2_clk_pe2 { +- nvidia,pins = "dmic2_clk_pe2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic2_dat_pe3 { +- nvidia,pins = "dmic2_dat_pe3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic3_clk_pe4 { +- nvidia,pins = "dmic3_clk_pe4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dmic3_dat_pe5 { +- nvidia,pins = "dmic3_dat_pe5"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pe6 { +- nvidia,pins = "pe6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pe7 { +- nvidia,pins = "pe7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen3_i2c_scl_pf0 { +- nvidia,pins = "gen3_i2c_scl_pf0"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen3_i2c_sda_pf1 { +- nvidia,pins = "gen3_i2c_sda_pf1"; +- nvidia,function = "i2c3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- uart2_tx_pg0 { +- nvidia,pins = "uart2_tx_pg0"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart2_rx_pg1 { +- nvidia,pins = "uart2_rx_pg1"; +- nvidia,function = "uartb"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart2_rts_pg2 { +- nvidia,pins = "uart2_rts_pg2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart2_cts_pg3 { +- nvidia,pins = "uart2_cts_pg3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- wifi_en_ph0 { +- nvidia,pins = "wifi_en_ph0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- wifi_rst_ph1 { +- nvidia,pins = "wifi_rst_ph1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- wifi_wake_ap_ph2 { +- nvidia,pins = "wifi_wake_ap_ph2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ap_wake_bt_ph3 { +- nvidia,pins = "ap_wake_bt_ph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- bt_rst_ph4 { +- nvidia,pins = "bt_rst_ph4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- bt_wake_ap_ph5 { +- nvidia,pins = "bt_wake_ap_ph5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ph6 { +- nvidia,pins = "ph6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ap_wake_nfc_ph7 { +- nvidia,pins = "ap_wake_nfc_ph7"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- nfc_en_pi0 { +- nvidia,pins = "nfc_en_pi0"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- nfc_int_pi1 { +- nvidia,pins = "nfc_int_pi1"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gps_en_pi2 { +- nvidia,pins = "gps_en_pi2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gps_rst_pi3 { +- nvidia,pins = "gps_rst_pi3"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_tx_pi4 { +- nvidia,pins = "uart4_tx_pi4"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_rx_pi5 { +- nvidia,pins = "uart4_rx_pi5"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_rts_pi6 { +- nvidia,pins = "uart4_rts_pi6"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart4_cts_pi7 { +- nvidia,pins = "uart4_cts_pi7"; +- nvidia,function = "uartd"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gen1_i2c_sda_pj0 { +- nvidia,pins = "gen1_i2c_sda_pj0"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen1_i2c_scl_pj1 { +- nvidia,pins = "gen1_i2c_scl_pj1"; +- nvidia,function = "i2c1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen2_i2c_scl_pj2 { +- nvidia,pins = "gen2_i2c_scl_pj2"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- gen2_i2c_sda_pj3 { +- nvidia,pins = "gen2_i2c_sda_pj3"; +- nvidia,function = "i2c2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- dap4_fs_pj4 { +- nvidia,pins = "dap4_fs_pj4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap4_din_pj5 { +- nvidia,pins = "dap4_din_pj5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap4_dout_pj6 { +- nvidia,pins = "dap4_dout_pj6"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap4_sclk_pj7 { +- nvidia,pins = "dap4_sclk_pj7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk0 { +- nvidia,pins = "pk0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk1 { +- nvidia,pins = "pk1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk2 { +- nvidia,pins = "pk2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk3 { +- nvidia,pins = "pk3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk4 { +- nvidia,pins = "pk4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk5 { +- nvidia,pins = "pk5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk6 { +- nvidia,pins = "pk6"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pk7 { +- nvidia,pins = "pk7"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pl0 { +- nvidia,pins = "pl0"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pl1 { +- nvidia,pins = "pl1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_clk_pm0 { +- nvidia,pins = "sdmmc1_clk_pm0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_cmd_pm1 { +- nvidia,pins = "sdmmc1_cmd_pm1"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat3_pm2 { +- nvidia,pins = "sdmmc1_dat3_pm2"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat2_pm3 { +- nvidia,pins = "sdmmc1_dat2_pm3"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat1_pm4 { +- nvidia,pins = "sdmmc1_dat1_pm4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc1_dat0_pm5 { +- nvidia,pins = "sdmmc1_dat0_pm5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_clk_pp0 { +- nvidia,pins = "sdmmc3_clk_pp0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_cmd_pp1 { +- nvidia,pins = "sdmmc3_cmd_pp1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat3_pp2 { +- nvidia,pins = "sdmmc3_dat3_pp2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat2_pp3 { +- nvidia,pins = "sdmmc3_dat2_pp3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat1_pp4 { +- nvidia,pins = "sdmmc3_dat1_pp4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- sdmmc3_dat0_pp5 { +- nvidia,pins = "sdmmc3_dat0_pp5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam1_mclk_ps0 { +- nvidia,pins = "cam1_mclk_ps0"; +- nvidia,function = "extperiph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam2_mclk_ps1 { +- nvidia,pins = "cam2_mclk_ps1"; +- nvidia,function = "extperiph3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_i2c_scl_ps2 { +- nvidia,pins = "cam_i2c_scl_ps2"; +- nvidia,function = "i2cvi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- cam_i2c_sda_ps3 { +- nvidia,pins = "cam_i2c_sda_ps3"; +- nvidia,function = "i2cvi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- cam_rst_ps4 { +- nvidia,pins = "cam_rst_ps4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_af_en_ps5 { +- nvidia,pins = "cam_af_en_ps5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam_flash_en_ps6 { +- nvidia,pins = "cam_flash_en_ps6"; +- nvidia,function = "rsvd2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam1_pwdn_ps7 { +- nvidia,pins = "cam1_pwdn_ps7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam2_pwdn_pt0 { +- nvidia,pins = "cam2_pwdn_pt0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cam1_strobe_pt1 { +- nvidia,pins = "cam1_strobe_pt1"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_tx_pu0 { +- nvidia,pins = "uart1_tx_pu0"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_rx_pu1 { +- nvidia,pins = "uart1_rx_pu1"; +- nvidia,function = "uarta"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_rts_pu2 { +- nvidia,pins = "uart1_rts_pu2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- uart1_cts_pu3 { +- nvidia,pins = "uart1_cts_pu3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_bl_pwm_pv0 { +- nvidia,pins = "lcd_bl_pwm_pv0"; +- nvidia,function = "rsvd3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_bl_en_pv1 { +- nvidia,pins = "lcd_bl_en_pv1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_rst_pv2 { +- nvidia,pins = "lcd_rst_pv2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_gpio1_pv3 { +- nvidia,pins = "lcd_gpio1_pv3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_gpio2_pv4 { +- nvidia,pins = "lcd_gpio2_pv4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- ap_ready_pv5 { +- nvidia,pins = "ap_ready_pv5"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- touch_rst_pv6 { +- nvidia,pins = "touch_rst_pv6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- touch_clk_pv7 { +- nvidia,pins = "touch_clk_pv7"; +- nvidia,function = "touch"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- modem_wake_ap_px0 { +- nvidia,pins = "modem_wake_ap_px0"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- touch_int_px1 { +- nvidia,pins = "touch_int_px1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- motion_int_px2 { +- nvidia,pins = "motion_int_px2"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- als_prox_int_px3 { +- nvidia,pins = "als_prox_int_px3"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- temp_alert_px4 { +- nvidia,pins = "temp_alert_px4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_power_on_px5 { +- nvidia,pins = "button_power_on_px5"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_vol_up_px6 { +- nvidia,pins = "button_vol_up_px6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_vol_down_px7 { +- nvidia,pins = "button_vol_down_px7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_slide_sw_py0 { +- nvidia,pins = "button_slide_sw_py0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- button_home_py1 { +- nvidia,pins = "button_home_py1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- lcd_te_py2 { +- nvidia,pins = "lcd_te_py2"; +- nvidia,function = "displaya"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pwr_i2c_scl_py3 { +- nvidia,pins = "pwr_i2c_scl_py3"; +- nvidia,function = "i2cpmu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- pwr_i2c_sda_py4 { +- nvidia,pins = "pwr_i2c_sda_py4"; +- nvidia,function = "i2cpmu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- clk_32k_out_py5 { +- nvidia,pins = "clk_32k_out_py5"; +- nvidia,function = "soc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz0 { +- nvidia,pins = "pz0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz1 { +- nvidia,pins = "pz1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz2 { +- nvidia,pins = "pz2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz3 { +- nvidia,pins = "pz3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz4 { +- nvidia,pins = "pz4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pz5 { +- nvidia,pins = "pz5"; +- nvidia,function = "soc"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_fs_paa0 { +- nvidia,pins = "dap2_fs_paa0"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_sclk_paa1 { +- nvidia,pins = "dap2_sclk_paa1"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_din_paa2 { +- nvidia,pins = "dap2_din_paa2"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dap2_dout_paa3 { +- nvidia,pins = "dap2_dout_paa3"; +- nvidia,function = "i2s2"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- aud_mclk_pbb0 { +- nvidia,pins = "aud_mclk_pbb0"; +- nvidia,function = "aud"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dvfs_pwm_pbb1 { +- nvidia,pins = "dvfs_pwm_pbb1"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- dvfs_clk_pbb2 { +- nvidia,pins = "dvfs_clk_pbb2"; +- nvidia,function = "rsvd0"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gpio_x1_aud_pbb3 { +- nvidia,pins = "gpio_x1_aud_pbb3"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- gpio_x3_aud_pbb4 { +- nvidia,pins = "gpio_x3_aud_pbb4"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- hdmi_cec_pcc0 { +- nvidia,pins = "hdmi_cec_pcc0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- hdmi_int_dp_hpd_pcc1 { +- nvidia,pins = "hdmi_int_dp_hpd_pcc1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- spdif_out_pcc2 { +- nvidia,pins = "spdif_out_pcc2"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- spdif_in_pcc3 { +- nvidia,pins = "spdif_in_pcc3"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- usb_vbus_en0_pcc4 { +- nvidia,pins = "usb_vbus_en0_pcc4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- usb_vbus_en1_pcc5 { +- nvidia,pins = "usb_vbus_en1_pcc5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- dp_hpd0_pcc6 { +- nvidia,pins = "dp_hpd0_pcc6"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pcc7 { +- nvidia,pins = "pcc7"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- nvidia,io-hv = ; +- }; +- spi2_cs1_pdd0 { +- nvidia,pins = "spi2_cs1_pdd0"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_sck_pee0 { +- nvidia,pins = "qspi_sck_pee0"; +- nvidia,function = "qspi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_cs_n_pee1 { +- nvidia,pins = "qspi_cs_n_pee1"; +- nvidia,function = "qspi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io0_pee2 { +- nvidia,pins = "qspi_io0_pee2"; +- nvidia,function = "qspi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io1_pee3 { +- nvidia,pins = "qspi_io1_pee3"; +- nvidia,function = "qspi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io2_pee4 { +- nvidia,pins = "qspi_io2_pee4"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- qspi_io3_pee5 { +- nvidia,pins = "qspi_io3_pee5"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- core_pwr_req { +- nvidia,pins = "core_pwr_req"; +- nvidia,function = "core"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- cpu_pwr_req { +- nvidia,pins = "cpu_pwr_req"; +- nvidia,function = "cpu"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- pwr_int_n { +- nvidia,pins = "pwr_int_n"; +- nvidia,function = "pmi"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- clk_32k_in { +- nvidia,pins = "clk_32k_in"; +- nvidia,function = "clk"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- jtag_rtck { +- nvidia,pins = "jtag_rtck"; +- nvidia,function = "jtag"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- clk_req { +- nvidia,pins = "clk_req"; +- nvidia,function = "rsvd1"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- shutdown { +- nvidia,pins = "shutdown"; +- nvidia,function = "shutdown"; +- nvidia,pull = ; +- nvidia,tristate = ; +- nvidia,enable-input = ; +- nvidia,open-drain = ; +- }; +- }; +- }; +- +- serial@70006000 { +- status = "okay"; +- }; +- +- i2c@7000c400 { +- status = "okay"; +- clock-frequency = <1000000>; +- +- ec@1e { +- compatible = "google,cros-ec-i2c"; +- reg = <0x1e>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- wakeup-source; +- +- ec_i2c_0: i2c-tunnel { +- compatible = "google,cros-ec-i2c-tunnel"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- google,remote-bus = <0>; +- +- battery: bq27742@55 { +- compatible = "ti,bq27742"; +- reg = <0x55>; +- }; +- }; +- }; +- }; +- +- i2c@7000d000 { +- status = "okay"; +- clock-frequency = <1000000>; +- +- max77621_cpu: max77621@1b { +- compatible = "maxim,max77621"; +- reg = <0x1b>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1231250>; +- regulator-name = "PPVAR_CPU"; +- regulator-ramp-delay = <12500>; +- maxim,dvs-default-state = <1>; +- maxim,enable-active-discharge; +- maxim,enable-bias-control; +- maxim,enable-etr; +- maxim,enable-gpio = <&pmic 5 0>; +- maxim,externally-enable; +- }; +- +- pmic: pmic@3c { +- compatible = "maxim,max77620"; +- reg = <0x3c>; +- interrupts = ; +- +- #interrupt-cells = <2>; +- interrupt-controller; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&max77620_default>; +- +- max77620_default: pinmux { +- gpio0_1_2_7 { +- pins = "gpio0", "gpio1", "gpio2", "gpio7"; +- function = "gpio"; +- }; +- +- /* +- * GPIO3 is used to en_pp3300, and it is part of power +- * sequence, So it must be sequenced up (automatically +- * set by OTP) and down properly. +- */ +- gpio3 { +- pins = "gpio3"; +- function = "fps-out"; +- drive-open-drain = <1>; +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <4>; +- maxim,active-fps-power-down-slot = <2>; +- }; +- +- gpio5_6 { +- pins = "gpio5", "gpio6"; +- function = "gpio"; +- drive-push-pull = <1>; +- }; +- +- gpio4 { +- pins = "gpio4"; +- function = "32k-out1"; +- }; +- }; +- +- fps { +- fps0 { +- maxim,shutdown-fps-time-period-us = <5120>; +- maxim,fps-event-source = ; +- }; +- +- fps1 { +- maxim,shutdown-fps-time-period-us = <5120>; +- maxim,fps-event-source = ; +- maxim,device-state-on-disabled-event = ; +- }; +- +- fps2 { +- maxim,fps-event-source = ; +- }; +- }; +- +- regulators { +- in-ldo0-1-supply = <&pp1350>; +- in-ldo2-supply = <&pp3300>; +- in-ldo3-5-supply = <&pp3300>; +- in-ldo7-8-supply = <&pp1350>; +- +- ppvar_soc: sd0 { +- regulator-name = "PPVAR_SOC"; +- regulator-min-microvolt = <825000>; +- regulator-max-microvolt = <1125000>; +- regulator-always-on; +- regulator-boot-on; +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <1>; +- maxim,active-fps-power-down-slot = <7>; +- }; +- +- pp1100_sd1: sd1 { +- regulator-name = "PP1100"; +- regulator-min-microvolt = <1125000>; +- regulator-max-microvolt = <1125000>; +- regulator-always-on; +- regulator-boot-on; +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <5>; +- maxim,active-fps-power-down-slot = <1>; +- }; +- +- pp1350: sd2 { +- regulator-name = "PP1350"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <2>; +- maxim,active-fps-power-down-slot = <5>; +- }; +- +- pp1800: sd3 { +- regulator-name = "PP1800"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <3>; +- maxim,active-fps-power-down-slot = <3>; +- }; +- +- pp1200_avdd: ldo0 { +- regulator-name = "PP1200_AVDD"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-enable-ramp-delay = <26>; +- regulator-ramp-delay = <100000>; +- regulator-boot-on; +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <0>; +- maxim,active-fps-power-down-slot = <7>; +- }; +- +- pp1200_rcam: ldo1 { +- regulator-name = "PP1200_RCAM"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-enable-ramp-delay = <22>; +- regulator-ramp-delay = <100000>; +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <0>; +- maxim,active-fps-power-down-slot = <7>; +- }; +- +- pp_ldo2: ldo2 { +- regulator-name = "PP_LDO2"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <62>; +- regulator-ramp-delay = <11000>; +- regulator-always-on; +- regulator-boot-on; +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <0>; +- maxim,active-fps-power-down-slot = <7>; +- }; +- +- pp2800l_rcam: ldo3 { +- regulator-name = "PP2800L_RCAM"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-enable-ramp-delay = <50>; +- regulator-ramp-delay = <100000>; +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <0>; +- maxim,active-fps-power-down-slot = <7>; +- }; +- +- pp100_soc_rtc: ldo4 { +- regulator-name = "PP1100_SOC_RTC"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <850000>; +- regulator-enable-ramp-delay = <22>; +- regulator-ramp-delay = <100000>; +- regulator-always-on; /* Check this */ +- regulator-boot-on; +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <1>; +- maxim,active-fps-power-down-slot = <7>; +- }; +- +- pp2800l_fcam: ldo5 { +- regulator-name = "PP2800L_FCAM"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-enable-ramp-delay = <62>; +- regulator-ramp-delay = <100000>; +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <0>; +- maxim,active-fps-power-down-slot = <7>; +- }; +- +- ldo6 { +- /* Unused. */ +- regulator-name = "PP_LDO6"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <36>; +- regulator-ramp-delay = <100000>; +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <0>; +- maxim,active-fps-power-down-slot = <7>; +- }; +- +- pp1050_avdd: ldo7 { +- regulator-name = "PP1050_AVDD"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-enable-ramp-delay = <24>; +- regulator-ramp-delay = <100000>; +- regulator-always-on; +- regulator-boot-on; +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <3>; +- maxim,active-fps-power-down-slot = <4>; +- }; +- +- avddio_1v05: ldo8 { +- regulator-name = "AVDDIO_1V05"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-enable-ramp-delay = <22>; +- regulator-ramp-delay = <100000>; +- regulator-boot-on; +- maxim,active-fps-source = ; +- maxim,active-fps-power-up-slot = <0>; +- maxim,active-fps-power-down-slot = <7>; +- }; +- }; +- }; +- }; +- +- i2c@7000d100 { +- status = "okay"; +- clock-frequency = <400000>; +- +- nau8825@1a { +- compatible = "nuvoton,nau8825"; +- reg = <0x1a>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_2>; +- clock-names = "mclk"; +- +- nuvoton,jkdet-enable; +- nuvoton,jkdet-polarity = ; +- nuvoton,vref-impedance = <2>; +- nuvoton,micbias-voltage = <6>; +- nuvoton,sar-threshold-num = <4>; +- nuvoton,sar-threshold = <0xc 0x1e 0x38 0x60>; +- nuvoton,sar-hysteresis = <1>; +- nuvoton,sar-voltage = <0>; +- nuvoton,sar-compare-time = <0>; +- nuvoton,sar-sampling-time = <0>; +- nuvoton,short-key-debounce = <2>; +- nuvoton,jack-insert-debounce = <7>; +- nuvoton,jack-eject-debounce = <7>; +- status = "okay"; +- }; +- +- audio-codec@2d { +- compatible = "realtek,rt5677"; +- reg = <0x2d>; +- interrupt-parent = <&gpio>; +- interrupts = ; +- realtek,reset-gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_LOW>; +- gpio-controller; +- #gpio-cells = <2>; +- status = "okay"; +- }; +- }; +- +- pmc@7000e400 { +- nvidia,invert-interrupt; +- nvidia,suspend-mode = <0>; +- nvidia,cpu-pwr-good-time = <0>; +- nvidia,cpu-pwr-off-time = <0>; +- nvidia,core-pwr-good-time = <12000 6000>; +- nvidia,core-pwr-off-time = <39053>; +- nvidia,core-power-req-active-high; +- nvidia,sys-clock-req-active-high; +- status = "okay"; +- }; +- +- usb@70090000 { +- phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, +- <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>; +- phy-names = "usb2-0", "usb3-0"; +- +- dvddio-pex-supply = <&avddio_1v05>; +- hvddio-pex-supply = <&pp1800>; +- avdd-usb-supply = <&pp3300>; +- avdd-pll-utmip-supply = <&pp1800>; +- avdd-pll-uerefe-supply = <&pp1050_avdd>; +- dvdd-pex-pll-supply = <&avddio_1v05>; +- hvdd-pex-pll-e-supply = <&pp1800>; +- +- status = "okay"; +- }; +- +- padctl@7009f000 { +- status = "okay"; +- +- avdd-pll-utmip-supply = <&pp1800>; +- avdd-pll-uerefe-supply = <&pp1050_avdd>; +- dvdd-pex-pll-supply = <&avddio_1v05>; +- hvdd-pex-pll-e-supply = <&pp1800>; +- +- pads { +- usb2 { +- status = "okay"; +- +- lanes { +- usb2-0 { +- nvidia,function = "xusb"; +- status = "okay"; +- }; +- }; +- }; +- +- pcie { +- status = "okay"; +- +- lanes { +- pcie-6 { +- nvidia,function = "usb3-ss"; +- status = "okay"; +- }; +- }; +- }; +- }; +- +- ports { +- usb2-0 { +- status = "okay"; +- vbus-supply = <&usbc_vbus>; +- mode = "otg"; +- }; +- +- usb3-0 { +- nvidia,usb2-companion = <0>; +- status = "okay"; +- }; +- }; +- }; +- +- mmc@700b0600 { +- bus-width = <8>; +- non-removable; +- status = "okay"; +- }; +- +- clock@70110000 { +- status = "okay"; +- nvidia,cf = <6>; +- nvidia,ci = <0>; +- nvidia,cg = <2>; +- nvidia,droop-ctrl = <0x00000f00>; +- nvidia,force-mode = <1>; +- nvidia,i2c-fs-rate = <400000>; +- nvidia,sample-rate = <12500>; +- vdd-cpu-supply = <&max77621_cpu>; +- }; +- +- aconnect@702c0000 { +- status = "okay"; +- +- dma-controller@702e2000 { +- status = "okay"; +- }; +- +- interrupt-controller@702f9000 { +- status = "okay"; +- }; +- }; +- +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- +- cpus { +- cpu@0 { +- enable-method = "psci"; +- }; +- +- cpu@1 { +- enable-method = "psci"; +- }; +- +- cpu@2 { +- enable-method = "psci"; +- }; +- +- cpu@3 { +- enable-method = "psci"; +- }; +- +- idle-states { +- cpu-sleep { +- arm,psci-suspend-param = <0x00010007>; +- status = "okay"; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "Power"; +- gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <30>; +- wakeup-source; +- }; +- +- lid { +- label = "Lid"; +- gpios = <&gpio TEGRA_GPIO(B, 4) GPIO_ACTIVE_LOW>; +- linux,input-type = ; +- linux,code = ; +- wakeup-source; +- }; +- +- tablet_mode { +- label = "Tablet Mode"; +- gpios = <&gpio TEGRA_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; +- linux,input-type = ; +- linux,code = ; +- wakeup-source; +- }; +- +- volume_down { +- label = "Volume Down"; +- gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- volume_up { +- label = "Volume Up"; +- gpios = <&gpio TEGRA_GPIO(M, 4) GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- max98357a { +- compatible = "maxim,max98357a"; +- status = "okay"; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- ppvar_sys: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "PPVAR_SYS"; +- regulator-min-microvolt = <4400000>; +- regulator-max-microvolt = <4400000>; +- regulator-always-on; +- }; +- +- pplcd_vdd: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "PPLCD_VDD"; +- regulator-min-microvolt = <4400000>; +- regulator-max-microvolt = <4400000>; +- gpio = <&gpio TEGRA_GPIO(V, 4) 0>; +- enable-active-high; +- regulator-boot-on; +- }; +- +- pp3000_always: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "PP3000_ALWAYS"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- }; +- +- pp3300: regulator@3 { +- compatible = "regulator-fixed"; +- regulator-name = "PP3300"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- enable-active-high; +- }; +- +- pp5000: regulator@4 { +- compatible = "regulator-fixed"; +- regulator-name = "PP5000"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- pp1800_lcdio: regulator@5 { +- compatible = "regulator-fixed"; +- regulator-name = "PP1800_LCDIO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio TEGRA_GPIO(V, 3) 0>; +- enable-active-high; +- regulator-boot-on; +- }; +- +- pp1800_cam: regulator@6 { +- compatible = "regulator-fixed"; +- regulator-name = "PP1800_CAM"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio TEGRA_GPIO(K, 3) 0>; +- enable-active-high; +- }; +- +- usbc_vbus: regulator@7 { +- compatible = "regulator-fixed"; +- regulator-name = "USBC_VBUS"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210.dtsi b/scripts/dtc/include-prefixes/arm64/nvidia/tegra210.dtsi +deleted file mode 100644 +index 26b3f98a211c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra210.dtsi ++++ /dev/null +@@ -1,2054 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "nvidia,tegra210"; +- interrupt-parent = <&lic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- pcie@1003000 { +- compatible = "nvidia,tegra210-pcie"; +- device_type = "pci"; +- reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ +- <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ +- <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ +- reg-names = "pads", "afi", "cs"; +- interrupts = , /* controller interrupt */ +- ; /* MSI interrupt */ +- interrupt-names = "intr", "msi"; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; +- +- bus-range = <0x00 0xff>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ +- <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ +- <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ +- <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ +- <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ +- +- clocks = <&tegra_car TEGRA210_CLK_PCIE>, +- <&tegra_car TEGRA210_CLK_AFI>, +- <&tegra_car TEGRA210_CLK_PLL_E>, +- <&tegra_car TEGRA210_CLK_CML0>; +- clock-names = "pex", "afi", "pll_e", "cml"; +- resets = <&tegra_car 70>, +- <&tegra_car 72>, +- <&tegra_car 74>; +- reset-names = "pex", "afi", "pcie_x"; +- +- pinctrl-names = "default", "idle"; +- pinctrl-0 = <&pex_dpd_disable>; +- pinctrl-1 = <&pex_dpd_enable>; +- +- status = "disabled"; +- +- pci@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; +- reg = <0x000800 0 0 0 0>; +- bus-range = <0x00 0xff>; +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- ranges; +- +- nvidia,num-lanes = <4>; +- }; +- +- pci@2,0 { +- device_type = "pci"; +- assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; +- reg = <0x001000 0 0 0 0>; +- bus-range = <0x00 0xff>; +- status = "disabled"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- ranges; +- +- nvidia,num-lanes = <1>; +- }; +- }; +- +- host1x@50000000 { +- compatible = "nvidia,tegra210-host1x"; +- reg = <0x0 0x50000000 0x0 0x00034000>; +- interrupts = , /* syncpt */ +- ; /* general */ +- interrupt-names = "syncpt", "host1x"; +- clocks = <&tegra_car TEGRA210_CLK_HOST1X>; +- clock-names = "host1x"; +- resets = <&tegra_car 28>; +- reset-names = "host1x"; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; +- +- iommus = <&mc TEGRA_SWGROUP_HC>; +- +- dpaux1: dpaux@54040000 { +- compatible = "nvidia,tegra210-dpaux"; +- reg = <0x0 0x54040000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, +- <&tegra_car TEGRA210_CLK_PLL_DP>; +- clock-names = "dpaux", "parent"; +- resets = <&tegra_car 207>; +- reset-names = "dpaux"; +- power-domains = <&pd_sor>; +- status = "disabled"; +- +- state_dpaux1_aux: pinmux-aux { +- groups = "dpaux-io"; +- function = "aux"; +- }; +- +- state_dpaux1_i2c: pinmux-i2c { +- groups = "dpaux-io"; +- function = "i2c"; +- }; +- +- state_dpaux1_off: pinmux-off { +- groups = "dpaux-io"; +- function = "off"; +- }; +- +- i2c-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- vi@54080000 { +- compatible = "nvidia,tegra210-vi"; +- reg = <0x0 0x54080000 0x0 0x700>; +- interrupts = ; +- status = "disabled"; +- assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; +- assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; +- +- clocks = <&tegra_car TEGRA210_CLK_VI>; +- power-domains = <&pd_venc>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0x0 0x0 0x54080000 0x2000>; +- +- csi@838 { +- compatible = "nvidia,tegra210-csi"; +- reg = <0x838 0x1300>; +- status = "disabled"; +- assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, +- <&tegra_car TEGRA210_CLK_CILCD>, +- <&tegra_car TEGRA210_CLK_CILE>, +- <&tegra_car TEGRA210_CLK_CSI_TPG>; +- assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, +- <&tegra_car TEGRA210_CLK_PLL_P>, +- <&tegra_car TEGRA210_CLK_PLL_P>; +- assigned-clock-rates = <102000000>, +- <102000000>, +- <102000000>, +- <972000000>; +- +- clocks = <&tegra_car TEGRA210_CLK_CSI>, +- <&tegra_car TEGRA210_CLK_CILAB>, +- <&tegra_car TEGRA210_CLK_CILCD>, +- <&tegra_car TEGRA210_CLK_CILE>, +- <&tegra_car TEGRA210_CLK_CSI_TPG>; +- clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; +- power-domains = <&pd_sor>; +- }; +- }; +- +- tsec@54100000 { +- compatible = "nvidia,tegra210-tsec"; +- reg = <0x0 0x54100000 0x0 0x00040000>; +- }; +- +- dc@54200000 { +- compatible = "nvidia,tegra210-dc"; +- reg = <0x0 0x54200000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_DISP1>; +- clock-names = "dc"; +- resets = <&tegra_car 27>; +- reset-names = "dc"; +- +- iommus = <&mc TEGRA_SWGROUP_DC>; +- +- nvidia,outputs = <&dsia &dsib &sor0 &sor1>; +- nvidia,head = <0>; +- }; +- +- dc@54240000 { +- compatible = "nvidia,tegra210-dc"; +- reg = <0x0 0x54240000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_DISP2>; +- clock-names = "dc"; +- resets = <&tegra_car 26>; +- reset-names = "dc"; +- +- iommus = <&mc TEGRA_SWGROUP_DCB>; +- +- nvidia,outputs = <&dsia &dsib &sor0 &sor1>; +- nvidia,head = <1>; +- }; +- +- dsia: dsi@54300000 { +- compatible = "nvidia,tegra210-dsi"; +- reg = <0x0 0x54300000 0x0 0x00040000>; +- clocks = <&tegra_car TEGRA210_CLK_DSIA>, +- <&tegra_car TEGRA210_CLK_DSIALP>, +- <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; +- clock-names = "dsi", "lp", "parent"; +- resets = <&tegra_car 48>; +- reset-names = "dsi"; +- power-domains = <&pd_sor>; +- nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ +- +- status = "disabled"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- vic@54340000 { +- compatible = "nvidia,tegra210-vic"; +- reg = <0x0 0x54340000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_VIC03>; +- clock-names = "vic"; +- resets = <&tegra_car 178>; +- reset-names = "vic"; +- +- iommus = <&mc TEGRA_SWGROUP_VIC>; +- power-domains = <&pd_vic>; +- }; +- +- nvjpg@54380000 { +- compatible = "nvidia,tegra210-nvjpg"; +- reg = <0x0 0x54380000 0x0 0x00040000>; +- status = "disabled"; +- }; +- +- dsib: dsi@54400000 { +- compatible = "nvidia,tegra210-dsi"; +- reg = <0x0 0x54400000 0x0 0x00040000>; +- clocks = <&tegra_car TEGRA210_CLK_DSIB>, +- <&tegra_car TEGRA210_CLK_DSIBLP>, +- <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; +- clock-names = "dsi", "lp", "parent"; +- resets = <&tegra_car 82>; +- reset-names = "dsi"; +- power-domains = <&pd_sor>; +- nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ +- +- status = "disabled"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- nvdec@54480000 { +- compatible = "nvidia,tegra210-nvdec"; +- reg = <0x0 0x54480000 0x0 0x00040000>; +- status = "disabled"; +- }; +- +- nvenc@544c0000 { +- compatible = "nvidia,tegra210-nvenc"; +- reg = <0x0 0x544c0000 0x0 0x00040000>; +- status = "disabled"; +- }; +- +- tsec@54500000 { +- compatible = "nvidia,tegra210-tsec"; +- reg = <0x0 0x54500000 0x0 0x00040000>; +- status = "disabled"; +- }; +- +- sor0: sor@54540000 { +- compatible = "nvidia,tegra210-sor"; +- reg = <0x0 0x54540000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_SOR0>, +- <&tegra_car TEGRA210_CLK_SOR0_OUT>, +- <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, +- <&tegra_car TEGRA210_CLK_PLL_DP>, +- <&tegra_car TEGRA210_CLK_SOR_SAFE>; +- clock-names = "sor", "out", "parent", "dp", "safe"; +- resets = <&tegra_car 182>; +- reset-names = "sor"; +- pinctrl-0 = <&state_dpaux_aux>; +- pinctrl-1 = <&state_dpaux_i2c>; +- pinctrl-2 = <&state_dpaux_off>; +- pinctrl-names = "aux", "i2c", "off"; +- power-domains = <&pd_sor>; +- status = "disabled"; +- }; +- +- sor1: sor@54580000 { +- compatible = "nvidia,tegra210-sor1"; +- reg = <0x0 0x54580000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_SOR1>, +- <&tegra_car TEGRA210_CLK_SOR1_OUT>, +- <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, +- <&tegra_car TEGRA210_CLK_PLL_DP>, +- <&tegra_car TEGRA210_CLK_SOR_SAFE>; +- clock-names = "sor", "out", "parent", "dp", "safe"; +- resets = <&tegra_car 183>; +- reset-names = "sor"; +- pinctrl-0 = <&state_dpaux1_aux>; +- pinctrl-1 = <&state_dpaux1_i2c>; +- pinctrl-2 = <&state_dpaux1_off>; +- pinctrl-names = "aux", "i2c", "off"; +- power-domains = <&pd_sor>; +- status = "disabled"; +- }; +- +- dpaux: dpaux@545c0000 { +- compatible = "nvidia,tegra210-dpaux"; +- reg = <0x0 0x545c0000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_DPAUX>, +- <&tegra_car TEGRA210_CLK_PLL_DP>; +- clock-names = "dpaux", "parent"; +- resets = <&tegra_car 181>; +- reset-names = "dpaux"; +- power-domains = <&pd_sor>; +- status = "disabled"; +- +- state_dpaux_aux: pinmux-aux { +- groups = "dpaux-io"; +- function = "aux"; +- }; +- +- state_dpaux_i2c: pinmux-i2c { +- groups = "dpaux-io"; +- function = "i2c"; +- }; +- +- state_dpaux_off: pinmux-off { +- groups = "dpaux-io"; +- function = "off"; +- }; +- +- i2c-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- isp@54600000 { +- compatible = "nvidia,tegra210-isp"; +- reg = <0x0 0x54600000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_ISPA>; +- resets = <&tegra_car 23>; +- reset-names = "isp"; +- status = "disabled"; +- }; +- +- isp@54680000 { +- compatible = "nvidia,tegra210-isp"; +- reg = <0x0 0x54680000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_ISPB>; +- resets = <&tegra_car 3>; +- reset-names = "isp"; +- status = "disabled"; +- }; +- +- i2c@546c0000 { +- compatible = "nvidia,tegra210-i2c-vi"; +- reg = <0x0 0x546c0000 0x0 0x00040000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, +- <&tegra_car TEGRA210_CLK_I2CSLOW>; +- clock-names = "div-clk", "slow"; +- resets = <&tegra_car 208>; +- reset-names = "i2c"; +- power-domains = <&pd_venc>; +- status = "disabled"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- gic: interrupt-controller@50041000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x0 0x50041000 0x0 0x1000>, +- <0x0 0x50042000 0x0 0x2000>, +- <0x0 0x50044000 0x0 0x2000>, +- <0x0 0x50046000 0x0 0x2000>; +- interrupts = ; +- interrupt-parent = <&gic>; +- }; +- +- gpu@57000000 { +- compatible = "nvidia,gm20b"; +- reg = <0x0 0x57000000 0x0 0x01000000>, +- <0x0 0x58000000 0x0 0x01000000>; +- interrupts = , +- ; +- interrupt-names = "stall", "nonstall"; +- clocks = <&tegra_car TEGRA210_CLK_GPU>, +- <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, +- <&tegra_car TEGRA210_CLK_PLL_G_REF>; +- clock-names = "gpu", "pwr", "ref"; +- resets = <&tegra_car 184>; +- reset-names = "gpu"; +- +- iommus = <&mc TEGRA_SWGROUP_GPU>; +- +- status = "disabled"; +- }; +- +- lic: interrupt-controller@60004000 { +- compatible = "nvidia,tegra210-ictlr"; +- reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ +- <0x0 0x60004100 0x0 0x40>, /* secondary controller */ +- <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ +- <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ +- <0x0 0x60004400 0x0 0x40>, /* quinary controller */ +- <0x0 0x60004500 0x0 0x40>; /* senary controller */ +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- }; +- +- timer@60005000 { +- compatible = "nvidia,tegra210-timer"; +- reg = <0x0 0x60005000 0x0 0x400>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&tegra_car TEGRA210_CLK_TIMER>; +- clock-names = "timer"; +- }; +- +- tegra_car: clock@60006000 { +- compatible = "nvidia,tegra210-car"; +- reg = <0x0 0x60006000 0x0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- flow-controller@60007000 { +- compatible = "nvidia,tegra210-flowctrl"; +- reg = <0x0 0x60007000 0x0 0x1000>; +- }; +- +- gpio: gpio@6000d000 { +- compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; +- reg = <0x0 0x6000d000 0x0 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- #gpio-cells = <2>; +- gpio-controller; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- apbdma: dma@60020000 { +- compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; +- reg = <0x0 0x60020000 0x0 0x1400>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&tegra_car TEGRA210_CLK_APBDMA>; +- clock-names = "dma"; +- resets = <&tegra_car 34>; +- reset-names = "dma"; +- #dma-cells = <1>; +- }; +- +- apbmisc@70000800 { +- compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; +- reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ +- <0x0 0x70000008 0x0 0x04>; /* Strapping options */ +- }; +- +- pinmux: pinmux@700008d4 { +- compatible = "nvidia,tegra210-pinmux"; +- reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ +- <0x0 0x70003000 0x0 0x294>; /* Mux registers */ +- sdmmc1_3v3_drv: sdmmc1-3v3-drv { +- sdmmc1 { +- nvidia,pins = "drive_sdmmc1"; +- nvidia,pull-down-strength = <0x8>; +- nvidia,pull-up-strength = <0x8>; +- }; +- }; +- sdmmc1_1v8_drv: sdmmc1-1v8-drv { +- sdmmc1 { +- nvidia,pins = "drive_sdmmc1"; +- nvidia,pull-down-strength = <0x4>; +- nvidia,pull-up-strength = <0x3>; +- }; +- }; +- sdmmc2_1v8_drv: sdmmc2-1v8-drv { +- sdmmc2 { +- nvidia,pins = "drive_sdmmc2"; +- nvidia,pull-down-strength = <0x10>; +- nvidia,pull-up-strength = <0x10>; +- }; +- }; +- sdmmc3_3v3_drv: sdmmc3-3v3-drv { +- sdmmc3 { +- nvidia,pins = "drive_sdmmc3"; +- nvidia,pull-down-strength = <0x8>; +- nvidia,pull-up-strength = <0x8>; +- }; +- }; +- sdmmc3_1v8_drv: sdmmc3-1v8-drv { +- sdmmc3 { +- nvidia,pins = "drive_sdmmc3"; +- nvidia,pull-down-strength = <0x4>; +- nvidia,pull-up-strength = <0x3>; +- }; +- }; +- sdmmc4_1v8_drv: sdmmc4-1v8-drv { +- sdmmc4 { +- nvidia,pins = "drive_sdmmc4"; +- nvidia,pull-down-strength = <0x10>; +- nvidia,pull-up-strength = <0x10>; +- }; +- }; +- }; +- +- /* +- * There are two serial driver i.e. 8250 based simple serial +- * driver and APB DMA based serial driver for higher baudrate +- * and performance. To enable the 8250 based driver, the compatible +- * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable +- * the APB DMA based serial driver, the compatible is +- * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". +- */ +- uarta: serial@70006000 { +- compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; +- reg = <0x0 0x70006000 0x0 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_UARTA>; +- clock-names = "serial"; +- resets = <&tegra_car 6>; +- reset-names = "serial"; +- dmas = <&apbdma 8>, <&apbdma 8>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uartb: serial@70006040 { +- compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; +- reg = <0x0 0x70006040 0x0 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_UARTB>; +- clock-names = "serial"; +- resets = <&tegra_car 7>; +- reset-names = "serial"; +- dmas = <&apbdma 9>, <&apbdma 9>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uartc: serial@70006200 { +- compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; +- reg = <0x0 0x70006200 0x0 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_UARTC>; +- clock-names = "serial"; +- resets = <&tegra_car 55>; +- reset-names = "serial"; +- dmas = <&apbdma 10>, <&apbdma 10>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- uartd: serial@70006300 { +- compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; +- reg = <0x0 0x70006300 0x0 0x40>; +- reg-shift = <2>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_UARTD>; +- clock-names = "serial"; +- resets = <&tegra_car 65>; +- reset-names = "serial"; +- dmas = <&apbdma 19>, <&apbdma 19>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- pwm: pwm@7000a000 { +- compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; +- reg = <0x0 0x7000a000 0x0 0x100>; +- #pwm-cells = <2>; +- clocks = <&tegra_car TEGRA210_CLK_PWM>; +- clock-names = "pwm"; +- resets = <&tegra_car 17>; +- reset-names = "pwm"; +- status = "disabled"; +- }; +- +- i2c@7000c000 { +- compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; +- reg = <0x0 0x7000c000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA210_CLK_I2C1>; +- clock-names = "div-clk"; +- resets = <&tegra_car 12>; +- reset-names = "i2c"; +- dmas = <&apbdma 21>, <&apbdma 21>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000c400 { +- compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; +- reg = <0x0 0x7000c400 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA210_CLK_I2C2>; +- clock-names = "div-clk"; +- resets = <&tegra_car 54>; +- reset-names = "i2c"; +- dmas = <&apbdma 22>, <&apbdma 22>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000c500 { +- compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; +- reg = <0x0 0x7000c500 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA210_CLK_I2C3>; +- clock-names = "div-clk"; +- resets = <&tegra_car 67>; +- reset-names = "i2c"; +- dmas = <&apbdma 23>, <&apbdma 23>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000c700 { +- compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; +- reg = <0x0 0x7000c700 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA210_CLK_I2C4>; +- clock-names = "div-clk"; +- resets = <&tegra_car 103>; +- reset-names = "i2c"; +- dmas = <&apbdma 26>, <&apbdma 26>; +- dma-names = "rx", "tx"; +- pinctrl-0 = <&state_dpaux1_i2c>; +- pinctrl-1 = <&state_dpaux1_off>; +- pinctrl-names = "default", "idle"; +- status = "disabled"; +- }; +- +- i2c@7000d000 { +- compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; +- reg = <0x0 0x7000d000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA210_CLK_I2C5>; +- clock-names = "div-clk"; +- resets = <&tegra_car 47>; +- reset-names = "i2c"; +- dmas = <&apbdma 24>, <&apbdma 24>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c@7000d100 { +- compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; +- reg = <0x0 0x7000d100 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA210_CLK_I2C6>; +- clock-names = "div-clk"; +- resets = <&tegra_car 166>; +- reset-names = "i2c"; +- dmas = <&apbdma 30>, <&apbdma 30>; +- dma-names = "rx", "tx"; +- pinctrl-0 = <&state_dpaux_i2c>; +- pinctrl-1 = <&state_dpaux_off>; +- pinctrl-names = "default", "idle"; +- status = "disabled"; +- }; +- +- spi@7000d400 { +- compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; +- reg = <0x0 0x7000d400 0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA210_CLK_SBC1>; +- clock-names = "spi"; +- resets = <&tegra_car 41>; +- reset-names = "spi"; +- dmas = <&apbdma 15>, <&apbdma 15>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000d600 { +- compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; +- reg = <0x0 0x7000d600 0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA210_CLK_SBC2>; +- clock-names = "spi"; +- resets = <&tegra_car 44>; +- reset-names = "spi"; +- dmas = <&apbdma 16>, <&apbdma 16>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000d800 { +- compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; +- reg = <0x0 0x7000d800 0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA210_CLK_SBC3>; +- clock-names = "spi"; +- resets = <&tegra_car 46>; +- reset-names = "spi"; +- dmas = <&apbdma 17>, <&apbdma 17>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi@7000da00 { +- compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; +- reg = <0x0 0x7000da00 0x0 0x200>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA210_CLK_SBC4>; +- clock-names = "spi"; +- resets = <&tegra_car 68>; +- reset-names = "spi"; +- dmas = <&apbdma 18>, <&apbdma 18>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- rtc@7000e000 { +- compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; +- reg = <0x0 0x7000e000 0x0 0x100>; +- interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&tegra_pmc>; +- clocks = <&tegra_car TEGRA210_CLK_RTC>; +- clock-names = "rtc"; +- }; +- +- tegra_pmc: pmc@7000e400 { +- compatible = "nvidia,tegra210-pmc"; +- reg = <0x0 0x7000e400 0x0 0x400>; +- clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; +- clock-names = "pclk", "clk32k_in"; +- #clock-cells = <1>; +- #interrupt-cells = <2>; +- interrupt-controller; +- +- powergates { +- pd_audio: aud { +- clocks = <&tegra_car TEGRA210_CLK_APE>, +- <&tegra_car TEGRA210_CLK_APB2APE>; +- resets = <&tegra_car 198>; +- #power-domain-cells = <0>; +- }; +- +- pd_sor: sor { +- clocks = <&tegra_car TEGRA210_CLK_SOR0>, +- <&tegra_car TEGRA210_CLK_SOR1>, +- <&tegra_car TEGRA210_CLK_CILAB>, +- <&tegra_car TEGRA210_CLK_CILCD>, +- <&tegra_car TEGRA210_CLK_CILE>, +- <&tegra_car TEGRA210_CLK_DSIA>, +- <&tegra_car TEGRA210_CLK_DSIB>, +- <&tegra_car TEGRA210_CLK_DPAUX>, +- <&tegra_car TEGRA210_CLK_DPAUX1>, +- <&tegra_car TEGRA210_CLK_MIPI_CAL>; +- resets = <&tegra_car TEGRA210_CLK_SOR0>, +- <&tegra_car TEGRA210_CLK_SOR1>, +- <&tegra_car TEGRA210_CLK_DSIA>, +- <&tegra_car TEGRA210_CLK_DSIB>, +- <&tegra_car TEGRA210_CLK_DPAUX>, +- <&tegra_car TEGRA210_CLK_DPAUX1>, +- <&tegra_car TEGRA210_CLK_MIPI_CAL>; +- #power-domain-cells = <0>; +- }; +- +- pd_xusbss: xusba { +- clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; +- resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; +- #power-domain-cells = <0>; +- }; +- +- pd_xusbdev: xusbb { +- clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; +- resets = <&tegra_car 95>; +- #power-domain-cells = <0>; +- }; +- +- pd_xusbhost: xusbc { +- clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; +- resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; +- #power-domain-cells = <0>; +- }; +- +- pd_vic: vic { +- clocks = <&tegra_car TEGRA210_CLK_VIC03>; +- clock-names = "vic"; +- resets = <&tegra_car 178>; +- reset-names = "vic"; +- #power-domain-cells = <0>; +- }; +- +- pd_venc: venc { +- clocks = <&tegra_car TEGRA210_CLK_VI>, +- <&tegra_car TEGRA210_CLK_CSI>; +- resets = <&mc TEGRA210_MC_RESET_VI>, +- <&tegra_car 20>, +- <&tegra_car 52>; +- #power-domain-cells = <0>; +- }; +- }; +- +- sdmmc1_3v3: sdmmc1-3v3 { +- pins = "sdmmc1"; +- power-source = ; +- }; +- +- sdmmc1_1v8: sdmmc1-1v8 { +- pins = "sdmmc1"; +- power-source = ; +- }; +- +- sdmmc3_3v3: sdmmc3-3v3 { +- pins = "sdmmc3"; +- power-source = ; +- }; +- +- sdmmc3_1v8: sdmmc3-1v8 { +- pins = "sdmmc3"; +- power-source = ; +- }; +- +- pex_dpd_disable: pex_en { +- pex-dpd-disable { +- pins = "pex-bias", "pex-clk1", "pex-clk2"; +- low-power-disable; +- }; +- }; +- +- pex_dpd_enable: pex_dis { +- pex-dpd-enable { +- pins = "pex-bias", "pex-clk1", "pex-clk2"; +- low-power-enable; +- }; +- }; +- }; +- +- fuse@7000f800 { +- compatible = "nvidia,tegra210-efuse"; +- reg = <0x0 0x7000f800 0x0 0x400>; +- clocks = <&tegra_car TEGRA210_CLK_FUSE>; +- clock-names = "fuse"; +- resets = <&tegra_car 39>; +- reset-names = "fuse"; +- }; +- +- mc: memory-controller@70019000 { +- compatible = "nvidia,tegra210-mc"; +- reg = <0x0 0x70019000 0x0 0x1000>; +- clocks = <&tegra_car TEGRA210_CLK_MC>; +- clock-names = "mc"; +- +- interrupts = ; +- +- #iommu-cells = <1>; +- #reset-cells = <1>; +- }; +- +- emc: external-memory-controller@7001b000 { +- compatible = "nvidia,tegra210-emc"; +- reg = <0x0 0x7001b000 0x0 0x1000>, +- <0x0 0x7001e000 0x0 0x1000>, +- <0x0 0x7001f000 0x0 0x1000>; +- clocks = <&tegra_car TEGRA210_CLK_EMC>; +- clock-names = "emc"; +- interrupts = ; +- nvidia,memory-controller = <&mc>; +- #cooling-cells = <2>; +- }; +- +- sata@70020000 { +- compatible = "nvidia,tegra210-ahci"; +- reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ +- <0x0 0x70020000 0x0 0x7000>, /* SATA */ +- <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_SATA>, +- <&tegra_car TEGRA210_CLK_SATA_OOB>; +- clock-names = "sata", "sata-oob"; +- resets = <&tegra_car 124>, +- <&tegra_car 129>, +- <&tegra_car 123>; +- reset-names = "sata", "sata-cold", "sata-oob"; +- status = "disabled"; +- }; +- +- hda@70030000 { +- compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; +- reg = <0x0 0x70030000 0x0 0x10000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_HDA>, +- <&tegra_car TEGRA210_CLK_HDA2HDMI>, +- <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; +- clock-names = "hda", "hda2hdmi", "hda2codec_2x"; +- resets = <&tegra_car 125>, /* hda */ +- <&tegra_car 128>, /* hda2hdmi */ +- <&tegra_car 111>; /* hda2codec_2x */ +- reset-names = "hda", "hda2hdmi", "hda2codec_2x"; +- power-domains = <&pd_sor>; +- status = "disabled"; +- }; +- +- usb@70090000 { +- compatible = "nvidia,tegra210-xusb"; +- reg = <0x0 0x70090000 0x0 0x8000>, +- <0x0 0x70098000 0x0 0x1000>, +- <0x0 0x70099000 0x0 0x1000>; +- reg-names = "hcd", "fpci", "ipfs"; +- +- interrupts = , +- ; +- +- clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, +- <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, +- <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, +- <&tegra_car TEGRA210_CLK_XUSB_SS>, +- <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, +- <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, +- <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, +- <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, +- <&tegra_car TEGRA210_CLK_PLL_U_480M>, +- <&tegra_car TEGRA210_CLK_CLK_M>, +- <&tegra_car TEGRA210_CLK_PLL_E>; +- clock-names = "xusb_host", "xusb_host_src", +- "xusb_falcon_src", "xusb_ss", +- "xusb_ss_src", "xusb_ss_div2", +- "xusb_hs_src", "xusb_fs_src", +- "pll_u_480m", "clk_m", "pll_e"; +- resets = <&tegra_car 89>, <&tegra_car 156>, +- <&tegra_car 143>; +- reset-names = "xusb_host", "xusb_ss", "xusb_src"; +- power-domains = <&pd_xusbhost>, <&pd_xusbss>; +- power-domain-names = "xusb_host", "xusb_ss"; +- +- nvidia,xusb-padctl = <&padctl>; +- +- status = "disabled"; +- }; +- +- padctl: padctl@7009f000 { +- compatible = "nvidia,tegra210-xusb-padctl"; +- reg = <0x0 0x7009f000 0x0 0x1000>; +- interrupts = ; +- resets = <&tegra_car 142>; +- reset-names = "padctl"; +- nvidia,pmc = <&tegra_pmc>; +- +- status = "disabled"; +- +- pads { +- usb2 { +- clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; +- clock-names = "trk"; +- status = "disabled"; +- +- lanes { +- usb2-0 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- usb2-1 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- usb2-2 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- usb2-3 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- hsic { +- clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; +- clock-names = "trk"; +- status = "disabled"; +- +- lanes { +- hsic-0 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- hsic-1 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- pcie { +- clocks = <&tegra_car TEGRA210_CLK_PLL_E>; +- clock-names = "pll"; +- resets = <&tegra_car 205>; +- reset-names = "phy"; +- status = "disabled"; +- +- lanes { +- pcie-0 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- pcie-1 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- pcie-2 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- pcie-3 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- pcie-4 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- pcie-5 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- +- pcie-6 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- sata { +- clocks = <&tegra_car TEGRA210_CLK_PLL_E>; +- clock-names = "pll"; +- resets = <&tegra_car 204>; +- reset-names = "phy"; +- status = "disabled"; +- +- lanes { +- sata-0 { +- status = "disabled"; +- #phy-cells = <0>; +- }; +- }; +- }; +- }; +- +- ports { +- usb2-0 { +- status = "disabled"; +- }; +- +- usb2-1 { +- status = "disabled"; +- }; +- +- usb2-2 { +- status = "disabled"; +- }; +- +- usb2-3 { +- status = "disabled"; +- }; +- +- hsic-0 { +- status = "disabled"; +- }; +- +- usb3-0 { +- status = "disabled"; +- }; +- +- usb3-1 { +- status = "disabled"; +- }; +- +- usb3-2 { +- status = "disabled"; +- }; +- +- usb3-3 { +- status = "disabled"; +- }; +- }; +- }; +- +- mmc@700b0000 { +- compatible = "nvidia,tegra210-sdhci"; +- reg = <0x0 0x700b0000 0x0 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, +- <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; +- clock-names = "sdhci", "tmclk"; +- resets = <&tegra_car 14>; +- reset-names = "sdhci"; +- pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", +- "sdmmc-3v3-drv", "sdmmc-1v8-drv"; +- pinctrl-0 = <&sdmmc1_3v3>; +- pinctrl-1 = <&sdmmc1_1v8>; +- pinctrl-2 = <&sdmmc1_3v3_drv>; +- pinctrl-3 = <&sdmmc1_1v8_drv>; +- nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; +- nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; +- nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; +- nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; +- nvidia,default-tap = <0x2>; +- nvidia,default-trim = <0x4>; +- assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, +- <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, +- <&tegra_car TEGRA210_CLK_PLL_C4>; +- assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; +- assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; +- status = "disabled"; +- }; +- +- mmc@700b0200 { +- compatible = "nvidia,tegra210-sdhci"; +- reg = <0x0 0x700b0200 0x0 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_SDMMC2>, +- <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; +- clock-names = "sdhci", "tmclk"; +- resets = <&tegra_car 9>; +- reset-names = "sdhci"; +- pinctrl-names = "sdmmc-1v8-drv"; +- pinctrl-0 = <&sdmmc2_1v8_drv>; +- nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; +- nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; +- nvidia,default-tap = <0x8>; +- nvidia,default-trim = <0x0>; +- status = "disabled"; +- }; +- +- mmc@700b0400 { +- compatible = "nvidia,tegra210-sdhci"; +- reg = <0x0 0x700b0400 0x0 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_SDMMC3>, +- <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; +- clock-names = "sdhci", "tmclk"; +- resets = <&tegra_car 69>; +- reset-names = "sdhci"; +- pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", +- "sdmmc-3v3-drv", "sdmmc-1v8-drv"; +- pinctrl-0 = <&sdmmc3_3v3>; +- pinctrl-1 = <&sdmmc3_1v8>; +- pinctrl-2 = <&sdmmc3_3v3_drv>; +- pinctrl-3 = <&sdmmc3_1v8_drv>; +- nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; +- nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; +- nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; +- nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; +- nvidia,default-tap = <0x3>; +- nvidia,default-trim = <0x3>; +- status = "disabled"; +- }; +- +- mmc@700b0600 { +- compatible = "nvidia,tegra210-sdhci"; +- reg = <0x0 0x700b0600 0x0 0x200>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, +- <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; +- clock-names = "sdhci", "tmclk"; +- resets = <&tegra_car 15>; +- reset-names = "sdhci"; +- pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; +- pinctrl-0 = <&sdmmc4_1v8_drv>; +- pinctrl-1 = <&sdmmc4_1v8_drv>; +- nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; +- nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; +- nvidia,default-tap = <0x8>; +- nvidia,default-trim = <0x0>; +- assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, +- <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; +- assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; +- nvidia,dqs-trim = <40>; +- mmc-hs400-1_8v; +- status = "disabled"; +- }; +- +- usb@700d0000 { +- compatible = "nvidia,tegra210-xudc"; +- reg = <0x0 0x700d0000 0x0 0x8000>, +- <0x0 0x700d8000 0x0 0x1000>, +- <0x0 0x700d9000 0x0 0x1000>; +- reg-names = "base", "fpci", "ipfs"; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, +- <&tegra_car TEGRA210_CLK_XUSB_SS>, +- <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, +- <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, +- <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; +- clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; +- power-domains = <&pd_xusbdev>, <&pd_xusbss>; +- power-domain-names = "dev", "ss"; +- nvidia,xusb-padctl = <&padctl>; +- status = "disabled"; +- }; +- +- soctherm: thermal-sensor@700e2000 { +- compatible = "nvidia,tegra210-soctherm"; +- reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ +- <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ +- reg-names = "soctherm-reg", "car-reg"; +- interrupts = , +- ; +- interrupt-names = "thermal", "edp"; +- clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, +- <&tegra_car TEGRA210_CLK_SOC_THERM>; +- clock-names = "tsensor", "soctherm"; +- resets = <&tegra_car 78>; +- reset-names = "soctherm"; +- #thermal-sensor-cells = <1>; +- +- throttle-cfgs { +- throttle_heavy: heavy { +- nvidia,priority = <100>; +- nvidia,cpu-throt-percent = <85>; +- nvidia,gpu-throt-level = ; +- +- #cooling-cells = <2>; +- }; +- }; +- }; +- +- mipi: mipi@700e3000 { +- compatible = "nvidia,tegra210-mipi"; +- reg = <0x0 0x700e3000 0x0 0x100>; +- clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; +- clock-names = "mipi-cal"; +- power-domains = <&pd_sor>; +- #nvidia,mipi-calibrate-cells = <1>; +- }; +- +- dfll: clock@70110000 { +- compatible = "nvidia,tegra210-dfll"; +- reg = <0 0x70110000 0 0x100>, /* DFLL control */ +- <0 0x70110000 0 0x100>, /* I2C output control */ +- <0 0x70110100 0 0x100>, /* Integrated I2C controller */ +- <0 0x70110200 0 0x100>; /* Look-up table RAM */ +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, +- <&tegra_car TEGRA210_CLK_DFLL_REF>, +- <&tegra_car TEGRA210_CLK_I2C5>; +- clock-names = "soc", "ref", "i2c"; +- resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; +- reset-names = "dvco"; +- #clock-cells = <0>; +- clock-output-names = "dfllCPU_out"; +- status = "disabled"; +- }; +- +- aconnect@702c0000 { +- compatible = "nvidia,tegra210-aconnect"; +- clocks = <&tegra_car TEGRA210_CLK_APE>, +- <&tegra_car TEGRA210_CLK_APB2APE>; +- clock-names = "ape", "apb2ape"; +- power-domains = <&pd_audio>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; +- status = "disabled"; +- +- adma: dma-controller@702e2000 { +- compatible = "nvidia,tegra210-adma"; +- reg = <0x702e2000 0x2000>; +- interrupt-parent = <&agic>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- #dma-cells = <1>; +- clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; +- clock-names = "d_audio"; +- status = "disabled"; +- }; +- +- agic: interrupt-controller@702f9000 { +- compatible = "nvidia,tegra210-agic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x702f9000 0x1000>, +- <0x702fa000 0x2000>; +- interrupts = ; +- clocks = <&tegra_car TEGRA210_CLK_APE>; +- clock-names = "clk"; +- status = "disabled"; +- }; +- +- tegra_ahub: ahub@702d0800 { +- compatible = "nvidia,tegra210-ahub"; +- reg = <0x702d0800 0x800>; +- clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; +- clock-names = "ahub"; +- assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; +- assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x702d0000 0x702d0000 0x0000e400>; +- status = "disabled"; +- +- tegra_admaif: admaif@702d0000 { +- compatible = "nvidia,tegra210-admaif"; +- reg = <0x702d0000 0x800>; +- dmas = <&adma 1>, <&adma 1>, +- <&adma 2>, <&adma 2>, +- <&adma 3>, <&adma 3>, +- <&adma 4>, <&adma 4>, +- <&adma 5>, <&adma 5>, +- <&adma 6>, <&adma 6>, +- <&adma 7>, <&adma 7>, +- <&adma 8>, <&adma 8>, +- <&adma 9>, <&adma 9>, +- <&adma 10>, <&adma 10>; +- dma-names = "rx1", "tx1", +- "rx2", "tx2", +- "rx3", "tx3", +- "rx4", "tx4", +- "rx5", "tx5", +- "rx6", "tx6", +- "rx7", "tx7", +- "rx8", "tx8", +- "rx9", "tx9", +- "rx10", "tx10"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- admaif1_port: port@0 { +- reg = <0>; +- +- admaif1_ep: endpoint { +- remote-endpoint = <&xbar_admaif1_ep>; +- }; +- }; +- +- admaif2_port: port@1 { +- reg = <1>; +- +- admaif2_ep: endpoint { +- remote-endpoint = <&xbar_admaif2_ep>; +- }; +- }; +- +- admaif3_port: port@2 { +- reg = <2>; +- +- admaif3_ep: endpoint { +- remote-endpoint = <&xbar_admaif3_ep>; +- }; +- }; +- +- admaif4_port: port@3 { +- reg = <3>; +- +- admaif4_ep: endpoint { +- remote-endpoint = <&xbar_admaif4_ep>; +- }; +- }; +- +- admaif5_port: port@4 { +- reg = <4>; +- +- admaif5_ep: endpoint { +- remote-endpoint = <&xbar_admaif5_ep>; +- }; +- }; +- +- admaif6_port: port@5 { +- reg = <5>; +- +- admaif6_ep: endpoint { +- remote-endpoint = <&xbar_admaif6_ep>; +- }; +- }; +- +- admaif7_port: port@6 { +- reg = <6>; +- +- admaif7_ep: endpoint { +- remote-endpoint = <&xbar_admaif7_ep>; +- }; +- }; +- +- admaif8_port: port@7 { +- reg = <7>; +- +- admaif8_ep: endpoint { +- remote-endpoint = <&xbar_admaif8_ep>; +- }; +- }; +- +- admaif9_port: port@8 { +- reg = <8>; +- +- admaif9_ep: endpoint { +- remote-endpoint = <&xbar_admaif9_ep>; +- }; +- }; +- +- admaif10_port: port@9 { +- reg = <9>; +- +- admaif10_ep: endpoint { +- remote-endpoint = <&xbar_admaif10_ep>; +- }; +- }; +- }; +- }; +- +- tegra_i2s1: i2s@702d1000 { +- compatible = "nvidia,tegra210-i2s"; +- reg = <0x702d1000 0x100>; +- clocks = <&tegra_car TEGRA210_CLK_I2S0>, +- <&tegra_car TEGRA210_CLK_I2S0_SYNC>; +- clock-names = "i2s", "sync_input"; +- assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; +- assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <1536000>; +- sound-name-prefix = "I2S1"; +- status = "disabled"; +- }; +- +- tegra_i2s2: i2s@702d1100 { +- compatible = "nvidia,tegra210-i2s"; +- reg = <0x702d1100 0x100>; +- clocks = <&tegra_car TEGRA210_CLK_I2S1>, +- <&tegra_car TEGRA210_CLK_I2S1_SYNC>; +- clock-names = "i2s", "sync_input"; +- assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>; +- assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <1536000>; +- sound-name-prefix = "I2S2"; +- status = "disabled"; +- }; +- +- tegra_i2s3: i2s@702d1200 { +- compatible = "nvidia,tegra210-i2s"; +- reg = <0x702d1200 0x100>; +- clocks = <&tegra_car TEGRA210_CLK_I2S2>, +- <&tegra_car TEGRA210_CLK_I2S2_SYNC>; +- clock-names = "i2s", "sync_input"; +- assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>; +- assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <1536000>; +- sound-name-prefix = "I2S3"; +- status = "disabled"; +- }; +- +- tegra_i2s4: i2s@702d1300 { +- compatible = "nvidia,tegra210-i2s"; +- reg = <0x702d1300 0x100>; +- clocks = <&tegra_car TEGRA210_CLK_I2S3>, +- <&tegra_car TEGRA210_CLK_I2S3_SYNC>; +- clock-names = "i2s", "sync_input"; +- assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>; +- assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <1536000>; +- sound-name-prefix = "I2S4"; +- status = "disabled"; +- }; +- +- tegra_i2s5: i2s@702d1400 { +- compatible = "nvidia,tegra210-i2s"; +- reg = <0x702d1400 0x100>; +- clocks = <&tegra_car TEGRA210_CLK_I2S4>, +- <&tegra_car TEGRA210_CLK_I2S4_SYNC>; +- clock-names = "i2s", "sync_input"; +- assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>; +- assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <1536000>; +- sound-name-prefix = "I2S5"; +- status = "disabled"; +- }; +- +- tegra_dmic1: dmic@702d4000 { +- compatible = "nvidia,tegra210-dmic"; +- reg = <0x702d4000 0x100>; +- clocks = <&tegra_car TEGRA210_CLK_DMIC1>; +- clock-names = "dmic"; +- assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; +- assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <3072000>; +- sound-name-prefix = "DMIC1"; +- status = "disabled"; +- }; +- +- tegra_dmic2: dmic@702d4100 { +- compatible = "nvidia,tegra210-dmic"; +- reg = <0x702d4100 0x100>; +- clocks = <&tegra_car TEGRA210_CLK_DMIC2>; +- clock-names = "dmic"; +- assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; +- assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <3072000>; +- sound-name-prefix = "DMIC2"; +- status = "disabled"; +- }; +- +- tegra_dmic3: dmic@702d4200 { +- compatible = "nvidia,tegra210-dmic"; +- reg = <0x702d4200 0x100>; +- clocks = <&tegra_car TEGRA210_CLK_DMIC3>; +- clock-names = "dmic"; +- assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; +- assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <3072000>; +- sound-name-prefix = "DMIC3"; +- status = "disabled"; +- }; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0x0>; +- +- xbar_admaif1_ep: endpoint { +- remote-endpoint = <&admaif1_ep>; +- }; +- }; +- +- port@1 { +- reg = <0x1>; +- +- xbar_admaif2_ep: endpoint { +- remote-endpoint = <&admaif2_ep>; +- }; +- }; +- +- port@2 { +- reg = <0x2>; +- +- xbar_admaif3_ep: endpoint { +- remote-endpoint = <&admaif3_ep>; +- }; +- }; +- +- port@3 { +- reg = <0x3>; +- +- xbar_admaif4_ep: endpoint { +- remote-endpoint = <&admaif4_ep>; +- }; +- }; +- +- port@4 { +- reg = <0x4>; +- xbar_admaif5_ep: endpoint { +- remote-endpoint = <&admaif5_ep>; +- }; +- }; +- port@5 { +- reg = <0x5>; +- +- xbar_admaif6_ep: endpoint { +- remote-endpoint = <&admaif6_ep>; +- }; +- }; +- +- port@6 { +- reg = <0x6>; +- +- xbar_admaif7_ep: endpoint { +- remote-endpoint = <&admaif7_ep>; +- }; +- }; +- +- port@7 { +- reg = <0x7>; +- +- xbar_admaif8_ep: endpoint { +- remote-endpoint = <&admaif8_ep>; +- }; +- }; +- +- port@8 { +- reg = <0x8>; +- +- xbar_admaif9_ep: endpoint { +- remote-endpoint = <&admaif9_ep>; +- }; +- }; +- +- port@9 { +- reg = <0x9>; +- +- xbar_admaif10_ep: endpoint { +- remote-endpoint = <&admaif10_ep>; +- }; +- }; +- }; +- }; +- }; +- +- spi@70410000 { +- compatible = "nvidia,tegra210-qspi"; +- reg = <0x0 0x70410000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&tegra_car TEGRA210_CLK_QSPI>, +- <&tegra_car TEGRA210_CLK_QSPI_PM>; +- clock-names = "qspi", "qspi_out"; +- resets = <&tegra_car 211>; +- reset-names = "qspi"; +- dmas = <&apbdma 5>, <&apbdma 5>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- usb@7d000000 { +- compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; +- reg = <0x0 0x7d000000 0x0 0x4000>; +- interrupts = ; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA210_CLK_USBD>; +- clock-names = "usb"; +- resets = <&tegra_car 22>; +- reset-names = "usb"; +- nvidia,phy = <&phy1>; +- status = "disabled"; +- }; +- +- phy1: usb-phy@7d000000 { +- compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; +- reg = <0x0 0x7d000000 0x0 0x4000>, +- <0x0 0x7d000000 0x0 0x4000>; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA210_CLK_USBD>, +- <&tegra_car TEGRA210_CLK_PLL_U>, +- <&tegra_car TEGRA210_CLK_USBD>; +- clock-names = "reg", "pll_u", "utmi-pads"; +- resets = <&tegra_car 22>, <&tegra_car 22>; +- reset-names = "usb", "utmi-pads"; +- nvidia,hssync-start-delay = <0>; +- nvidia,idle-wait-delay = <17>; +- nvidia,elastic-limit = <16>; +- nvidia,term-range-adj = <6>; +- nvidia,xcvr-setup = <9>; +- nvidia,xcvr-lsfslew = <0>; +- nvidia,xcvr-lsrslew = <3>; +- nvidia,hssquelch-level = <2>; +- nvidia,hsdiscon-level = <5>; +- nvidia,xcvr-hsslew = <12>; +- nvidia,has-utmi-pad-registers; +- status = "disabled"; +- }; +- +- usb@7d004000 { +- compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; +- reg = <0x0 0x7d004000 0x0 0x4000>; +- interrupts = ; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA210_CLK_USB2>; +- clock-names = "usb"; +- resets = <&tegra_car 58>; +- reset-names = "usb"; +- nvidia,phy = <&phy2>; +- status = "disabled"; +- }; +- +- phy2: usb-phy@7d004000 { +- compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; +- reg = <0x0 0x7d004000 0x0 0x4000>, +- <0x0 0x7d000000 0x0 0x4000>; +- phy_type = "utmi"; +- clocks = <&tegra_car TEGRA210_CLK_USB2>, +- <&tegra_car TEGRA210_CLK_PLL_U>, +- <&tegra_car TEGRA210_CLK_USBD>; +- clock-names = "reg", "pll_u", "utmi-pads"; +- resets = <&tegra_car 58>, <&tegra_car 22>; +- reset-names = "usb", "utmi-pads"; +- nvidia,hssync-start-delay = <0>; +- nvidia,idle-wait-delay = <17>; +- nvidia,elastic-limit = <16>; +- nvidia,term-range-adj = <6>; +- nvidia,xcvr-setup = <9>; +- nvidia,xcvr-lsfslew = <0>; +- nvidia,xcvr-lsrslew = <3>; +- nvidia,hssquelch-level = <2>; +- nvidia,hsdiscon-level = <5>; +- nvidia,xcvr-hsslew = <12>; +- status = "disabled"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0>; +- clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, +- <&tegra_car TEGRA210_CLK_PLL_X>, +- <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, +- <&dfll>; +- clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; +- clock-latency = <300000>; +- cpu-idle-states = <&CPU_SLEEP>; +- next-level-cache = <&L2>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <1>; +- cpu-idle-states = <&CPU_SLEEP>; +- next-level-cache = <&L2>; +- }; +- +- cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <2>; +- cpu-idle-states = <&CPU_SLEEP>; +- next-level-cache = <&L2>; +- }; +- +- cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <3>; +- cpu-idle-states = <&CPU_SLEEP>; +- next-level-cache = <&L2>; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP: cpu-sleep { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x40000007>; +- entry-latency-us = <100>; +- exit-latency-us = <30>; +- min-residency-us = <1000>; +- wakeup-latency-us = <130>; +- idle-state-name = "cpu-sleep"; +- status = "disabled"; +- }; +- }; +- +- L2: l2-cache { +- compatible = "cache"; +- }; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} +- &{/cpus/cpu@2} &{/cpus/cpu@3}>; +- }; +- +- sound { +- status = "disabled"; +- +- clocks = <&tegra_car TEGRA210_CLK_PLL_A>, +- <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; +- clock-names = "pll_a", "plla_out0"; +- +- assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>, +- <&tegra_car TEGRA210_CLK_PLL_A_OUT0>, +- <&tegra_car TEGRA210_CLK_EXTERN1>; +- assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; +- assigned-clock-rates = <368640000>, <49152000>, <12288000>; +- }; +- +- thermal-zones { +- cpu { +- polling-delay-passive = <1000>; +- polling-delay = <0>; +- +- thermal-sensors = +- <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; +- +- trips { +- cpu-shutdown-trip { +- temperature = <102500>; +- hysteresis = <0>; +- type = "critical"; +- }; +- +- cpu_throttle_trip: throttle-trip { +- temperature = <98500>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_throttle_trip>; +- cooling-device = <&throttle_heavy 1 1>; +- }; +- }; +- }; +- +- mem { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = +- <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; +- +- trips { +- dram_nominal: mem-nominal-trip { +- temperature = <50000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- +- dram_throttle: mem-throttle-trip { +- temperature = <70000>; +- hysteresis = <1000>; +- type = "active"; +- }; +- +- mem-hot-trip { +- temperature = <100000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- +- mem-shutdown-trip { +- temperature = <103000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- dram-passive { +- cooling-device = <&emc 0 0>; +- trip = <&dram_nominal>; +- }; +- +- dram-active { +- cooling-device = <&emc 1 1>; +- trip = <&dram_throttle>; +- }; +- }; +- }; +- +- gpu { +- polling-delay-passive = <1000>; +- polling-delay = <0>; +- +- thermal-sensors = +- <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; +- +- trips { +- gpu-shutdown-trip { +- temperature = <103000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- +- gpu_throttle_trip: throttle-trip { +- temperature = <100000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&gpu_throttle_trip>; +- cooling-device = <&throttle_heavy 1 1>; +- }; +- }; +- }; +- +- pllx { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = +- <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; +- +- trips { +- pllx-shutdown-trip { +- temperature = <103000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- +- pllx-throttle-trip { +- temperature = <100000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- +- cooling-maps { +- /* +- * There are currently no cooling maps, +- * because there are no cooling devices. +- */ +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- interrupt-parent = <&gic>; +- arm,no-tick-in-suspend; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra234-sim-vdk.dts b/scripts/dtc/include-prefixes/arm64/nvidia/tegra234-sim-vdk.dts +deleted file mode 100644 +index b5d9a5526272..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra234-sim-vdk.dts ++++ /dev/null +@@ -1,40 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "tegra234.dtsi" +- +-/ { +- model = "NVIDIA Tegra234 VDK"; +- compatible = "nvidia,tegra234-vdk", "nvidia,tegra234"; +- +- aliases { +- mmc3 = "/bus@0/mmc@3460000"; +- serial0 = &uarta; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x03100000"; +- stdout-path = "serial0:115200n8"; +- }; +- +- bus@0 { +- serial@3100000 { +- status = "okay"; +- }; +- +- mmc@3460000 { +- status = "okay"; +- bus-width = <8>; +- non-removable; +- only-1-8-v; +- }; +- +- rtc@c2a0000 { +- status = "okay"; +- }; +- +- pmc@c360000 { +- nvidia,invert-interrupt; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/nvidia/tegra234.dtsi b/scripts/dtc/include-prefixes/arm64/nvidia/tegra234.dtsi +deleted file mode 100644 +index f0efb3a62804..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/nvidia/tegra234.dtsi ++++ /dev/null +@@ -1,189 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "nvidia,tegra234"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- bus@0 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0x0 0x0 0x0 0x40000000>; +- +- misc@100000 { +- compatible = "nvidia,tegra234-misc"; +- reg = <0x00100000 0xf000>, +- <0x0010f000 0x1000>; +- status = "okay"; +- }; +- +- uarta: serial@3100000 { +- compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; +- reg = <0x03100000 0x10000>; +- interrupts = ; +- clocks = <&bpmp TEGRA234_CLK_UARTA>; +- clock-names = "serial"; +- resets = <&bpmp TEGRA234_RESET_UARTA>; +- reset-names = "serial"; +- status = "disabled"; +- }; +- +- mmc@3460000 { +- compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; +- reg = <0x03460000 0x20000>; +- interrupts = ; +- clocks = <&bpmp TEGRA234_CLK_SDMMC4>; +- clock-names = "sdhci"; +- resets = <&bpmp TEGRA234_RESET_SDMMC4>; +- reset-names = "sdhci"; +- dma-coherent; +- status = "disabled"; +- }; +- +- fuse@3810000 { +- compatible = "nvidia,tegra234-efuse"; +- reg = <0x03810000 0x10000>; +- clocks = <&bpmp TEGRA234_CLK_FUSE>; +- clock-names = "fuse"; +- }; +- +- hsp_top0: hsp@3c00000 { +- compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; +- reg = <0x03c00000 0xa0000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "doorbell", "shared0", "shared1", "shared2", +- "shared3", "shared4", "shared5", "shared6", +- "shared7"; +- #mbox-cells = <2>; +- }; +- +- hsp_aon: hsp@c150000 { +- compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; +- reg = <0x0c150000 0x90000>; +- interrupts = , +- , +- , +- ; +- /* +- * Shared interrupt 0 is routed only to AON/SPE, so +- * we only have 4 shared interrupts for the CCPLEX. +- */ +- interrupt-names = "shared1", "shared2", "shared3", "shared4"; +- #mbox-cells = <2>; +- }; +- +- rtc@c2a0000 { +- compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; +- reg = <0x0c2a0000 0x10000>; +- interrupt-parent = <&pmc>; +- interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; +- +- pmc: pmc@c360000 { +- compatible = "nvidia,tegra234-pmc"; +- reg = <0x0c360000 0x10000>, +- <0x0c370000 0x10000>, +- <0x0c380000 0x10000>, +- <0x0c390000 0x10000>, +- <0x0c3a0000 0x10000>; +- reg-names = "pmc", "wake", "aotag", "scratch", "misc"; +- +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- gic: interrupt-controller@f400000 { +- compatible = "arm,gic-v3"; +- reg = <0x0f400000 0x010000>, /* GICD */ +- <0x0f440000 0x200000>; /* GICR */ +- interrupt-parent = <&gic>; +- interrupts = ; +- +- #redistributor-regions = <1>; +- #interrupt-cells = <3>; +- interrupt-controller; +- }; +- }; +- +- sysram@40000000 { +- compatible = "nvidia,tegra234-sysram", "mmio-sram"; +- reg = <0x0 0x40000000 0x0 0x50000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x40000000 0x50000>; +- +- cpu_bpmp_tx: shmem@4e000 { +- reg = <0x4e000 0x1000>; +- label = "cpu-bpmp-tx"; +- pool; +- }; +- +- cpu_bpmp_rx: shmem@4f000 { +- reg = <0x4f000 0x1000>; +- label = "cpu-bpmp-rx"; +- pool; +- }; +- }; +- +- bpmp: bpmp { +- compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; +- mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB +- TEGRA_HSP_DB_MASTER_BPMP>; +- shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- +- bpmp_i2c: i2c { +- compatible = "nvidia,tegra186-bpmp-i2c"; +- nvidia,bpmp-bus-id = <5>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- reg = <0x000>; +- +- enable-method = "psci"; +- }; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- status = "okay"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- interrupt-parent = <&gic>; +- always-on; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/Makefile b/scripts/dtc/include-prefixes/arm64/qcom/Makefile +deleted file mode 100644 +index 70516508be56..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/Makefile ++++ /dev/null +@@ -1,97 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb +-dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb +-dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb +-dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb +-dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb +-dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb +-dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb +-dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-octagon-talkman.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8994-msft-lumia-octagon-cityman.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-ivy.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-karin.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-satsuki.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-sumire.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-suzuran.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8996-pmi8996-sony-xperia-tone-dora.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8996-pmi8996-sony-xperia-tone-kagura.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8996-pmi8996-sony-xperia-tone-keyaki.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-dora.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-kagura.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-keyaki.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8998-oneplus-cheeseburger.dtb +-dtb-$(CONFIG_ARCH_QCOM) += msm8998-oneplus-dumpling.dtb +-dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb +-dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb +-dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3-lte.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-lte.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-kb.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-lte.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r4.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1-lte.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2-lte.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-enchilada.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-bahamut.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-griffin.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb +-dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/apq8016-sbc.dts b/scripts/dtc/include-prefixes/arm64/qcom/apq8016-sbc.dts +deleted file mode 100644 +index f3c0dbfd0a23..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/apq8016-sbc.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2015, The Linux Foundation. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "apq8016-sbc.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. APQ 8016 SBC"; +- compatible = "qcom,apq8016-sbc", "qcom,apq8016"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/apq8016-sbc.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/apq8016-sbc.dtsi +deleted file mode 100644 +index f8d8f3e3664e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/apq8016-sbc.dtsi ++++ /dev/null +@@ -1,826 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2015, The Linux Foundation. All rights reserved. +- */ +- +-#include "msm8916-pm8916.dtsi" +-#include +-#include +-#include +-#include +-#include +- +-/ { +- aliases { +- serial0 = &blsp1_uart2; +- serial1 = &blsp1_uart1; +- usid0 = &pm8916_0; +- i2c0 = &blsp_i2c2; +- i2c1 = &blsp_i2c6; +- i2c3 = &blsp_i2c4; +- spi0 = &blsp_spi5; +- spi1 = &blsp_spi3; +- }; +- +- chosen { +- stdout-path = "serial0"; +- }; +- +- camera_vdddo_1v8: camera-vdddo-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "camera_vdddo"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- camera_vdda_2v8: camera-vdda-2v8 { +- compatible = "regulator-fixed"; +- regulator-name = "camera_vdda"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- camera_vddd_1v5: camera-vddd-1v5 { +- compatible = "regulator-fixed"; +- regulator-name = "camera_vddd"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- +- reserved-memory { +- ramoops@bff00000 { +- compatible = "ramoops"; +- reg = <0x0 0xbff00000 0x0 0x100000>; +- +- record-size = <0x20000>; +- console-size = <0x20000>; +- ftrace-size = <0x20000>; +- }; +- }; +- +- usb2513 { +- compatible = "smsc,usb3503"; +- reset-gpios = <&pm8916_gpios 3 GPIO_ACTIVE_LOW>; +- initial-mode = <1>; +- }; +- +- usb_id: usb-id { +- compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_id_default>; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con: endpoint { +- remote-endpoint = <&adv7533_out>; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- autorepeat; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&msm_key_volp_n_default>; +- +- button@0 { +- label = "Volume Up"; +- linux,code = ; +- gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds { +- pinctrl-names = "default"; +- pinctrl-0 = <&msmgpio_leds>, +- <&pm8916_gpios_leds>, +- <&pm8916_mpps_leds>; +- +- compatible = "gpio-leds"; +- +- led@1 { +- label = "apq8016-sbc:green:user1"; +- gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- +- led@2 { +- label = "apq8016-sbc:green:user2"; +- gpios = <&msmgpio 120 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- +- led@3 { +- label = "apq8016-sbc:green:user3"; +- gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc1"; +- default-state = "off"; +- }; +- +- led@4 { +- label = "apq8016-sbc:green:user4"; +- gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "none"; +- panic-indicator; +- default-state = "off"; +- }; +- +- led@5 { +- label = "apq8016-sbc:yellow:wlan"; +- gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "phy0tx"; +- default-state = "off"; +- }; +- +- led@6 { +- label = "apq8016-sbc:blue:bt"; +- gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "bluetooth-power"; +- default-state = "off"; +- }; +- }; +-}; +- +-&blsp_dma { +- status = "okay"; +-}; +- +-&blsp_i2c2 { +- /* On Low speed expansion */ +- status = "okay"; +- label = "LS-I2C0"; +-}; +- +-&blsp_i2c4 { +- /* On High speed expansion */ +- status = "okay"; +- label = "HS-I2C2"; +- +- adv_bridge: bridge@39 { +- status = "okay"; +- +- compatible = "adi,adv7533"; +- reg = <0x39>; +- +- interrupt-parent = <&msmgpio>; +- interrupts = <31 IRQ_TYPE_EDGE_FALLING>; +- +- adi,dsi-lanes = <4>; +- clocks = <&rpmcc RPM_SMD_BB_CLK2>; +- clock-names = "cec"; +- +- pd-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; +- +- avdd-supply = <&pm8916_l6>; +- v1p2-supply = <&pm8916_l6>; +- v3p3-supply = <&pm8916_l17>; +- +- pinctrl-names = "default","sleep"; +- pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>; +- pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>; +- #sound-dai-cells = <1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7533_in: endpoint { +- remote-endpoint = <&dsi0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- adv7533_out: endpoint { +- remote-endpoint = <&hdmi_con>; +- }; +- }; +- }; +- }; +-}; +- +-&blsp_i2c6 { +- /* On Low speed expansion */ +- status = "okay"; +- label = "LS-I2C1"; +-}; +- +-&blsp_spi3 { +- /* On High speed expansion */ +- status = "okay"; +- label = "HS-SPI1"; +-}; +- +-&blsp_spi5 { +- /* On Low speed expansion */ +- status = "okay"; +- label = "LS-SPI0"; +-}; +- +-&blsp1_uart1 { +- status = "okay"; +- label = "LS-UART0"; +-}; +- +-&blsp1_uart2 { +- status = "okay"; +- label = "LS-UART1"; +-}; +- +-&camss { +- status = "okay"; +- ports { +- port@0 { +- reg = <0>; +- csiphy0_ep: endpoint { +- clock-lanes = <1>; +- data-lanes = <0 2>; +- remote-endpoint = <&ov5640_ep>; +- status = "okay"; +- }; +- }; +- }; +-}; +- +-&cci { +- status = "okay"; +-}; +- +-&cci_i2c0 { +- camera_rear@3b { +- compatible = "ovti,ov5640"; +- reg = <0x3b>; +- +- enable-gpios = <&msmgpio 34 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&camera_rear_default>; +- +- clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; +- clock-names = "xclk"; +- clock-frequency = <23880000>; +- +- vdddo-supply = <&camera_vdddo_1v8>; +- vdda-supply = <&camera_vdda_2v8>; +- vddd-supply = <&camera_vddd_1v5>; +- +- /* No camera mezzanine by default */ +- status = "disabled"; +- +- port { +- ov5640_ep: endpoint { +- clock-lanes = <1>; +- data-lanes = <0 2>; +- remote-endpoint = <&csiphy0_ep>; +- }; +- }; +- }; +-}; +- +-&dsi0_out { +- data-lanes = <0 1 2 3>; +- remote-endpoint = <&adv7533_in>; +-}; +- +-&lpass { +- status = "okay"; +-}; +- +-&mdss { +- status = "okay"; +-}; +- +-&pm8916_resin { +- status = "okay"; +- linux,code = ; +-}; +- +-&pronto { +- status = "okay"; +-}; +- +-&sdhc_1 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; +- pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +-}; +- +-&sdhc_2 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; +- pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; +- +- cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; +-}; +- +-&sound { +- status = "okay"; +- +- pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>; +- pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>; +- pinctrl-names = "default", "sleep"; +- qcom,model = "DB410c"; +- qcom,audio-routing = +- "AMIC2", "MIC BIAS Internal2", +- "AMIC3", "MIC BIAS External1"; +- +- external-dai-link@0 { +- link-name = "ADV7533"; +- cpu { +- sound-dai = <&lpass MI2S_QUATERNARY>; +- }; +- codec { +- sound-dai = <&adv_bridge 0>; +- }; +- }; +- +- internal-codec-playback-dai-link@0 { +- link-name = "WCD"; +- cpu { +- sound-dai = <&lpass MI2S_PRIMARY>; +- }; +- codec { +- sound-dai = <&lpass_codec 0>, <&wcd_codec 0>; +- }; +- }; +- +- internal-codec-capture-dai-link@0 { +- link-name = "WCD-Capture"; +- cpu { +- sound-dai = <&lpass MI2S_TERTIARY>; +- }; +- codec { +- sound-dai = <&lpass_codec 1>, <&wcd_codec 1>; +- }; +- }; +-}; +- +-&usb { +- status = "okay"; +- extcon = <&usb_id>, <&usb_id>; +- +- pinctrl-names = "default", "device"; +- pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>; +- pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>; +-}; +- +-&usb_hs_phy { +- extcon = <&usb_id>; +-}; +- +-&wcd_codec { +- clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; +- clock-names = "mclk"; +- qcom,mbhc-vthreshold-low = <75 150 237 450 500>; +- qcom,mbhc-vthreshold-high = <75 150 237 450 500>; +-}; +- +-/* Enable CoreSight */ +-&cti0 { status = "okay"; }; +-&cti1 { status = "okay"; }; +-&cti12 { status = "okay"; }; +-&cti13 { status = "okay"; }; +-&cti14 { status = "okay"; }; +-&cti15 { status = "okay"; }; +-&debug0 { status = "okay"; }; +-&debug1 { status = "okay"; }; +-&debug2 { status = "okay"; }; +-&debug3 { status = "okay"; }; +-&etf { status = "okay"; }; +-&etm0 { status = "okay"; }; +-&etm1 { status = "okay"; }; +-&etm2 { status = "okay"; }; +-&etm3 { status = "okay"; }; +-&etr { status = "okay"; }; +-&funnel0 { status = "okay"; }; +-&funnel1 { status = "okay"; }; +-&replicator { status = "okay"; }; +-&stm { status = "okay"; }; +-&tpiu { status = "okay"; }; +- +-&smd_rpm_regulators { +- vdd_l1_l2_l3-supply = <&pm8916_s3>; +- vdd_l4_l5_l6-supply = <&pm8916_s4>; +- vdd_l7-supply = <&pm8916_s4>; +- +- s3 { +- regulator-min-microvolt = <375000>; +- regulator-max-microvolt = <1562000>; +- }; +- +- s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-always-on; +- regulator-boot-on; +- }; +- +- l1 { +- regulator-min-microvolt = <375000>; +- regulator-max-microvolt = <1525000>; +- }; +- +- l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- l4 { +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <3337000>; +- }; +- +- l5 { +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <3337000>; +- }; +- +- l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l7 { +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <3337000>; +- }; +- +- l8 { +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <3337000>; +- }; +- +- l9 { +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <3337000>; +- }; +- +- l10 { +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <3337000>; +- }; +- +- l11 { +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <3337000>; +- regulator-allow-set-load; +- regulator-system-load = <200000>; +- }; +- +- l12 { +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <3337000>; +- }; +- +- l13 { +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <3337000>; +- }; +- +- l14 { +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <3337000>; +- }; +- +- /** +- * 1.8v required on LS expansion +- * for mezzanine boards +- */ +- l15 { +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <3337000>; +- regulator-always-on; +- }; +- +- l16 { +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <3337000>; +- }; +- +- l17 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l18 { +- regulator-min-microvolt = <1750000>; +- regulator-max-microvolt = <3337000>; +- }; +-}; +- +-/* +- * 2mA drive strength is not enough when connecting multiple +- * I2C devices with different pull up resistors. +- */ +-&i2c2_default { +- drive-strength = <16>; +-}; +- +-&i2c4_default { +- drive-strength = <16>; +-}; +- +-&i2c6_default { +- drive-strength = <16>; +-}; +- +-/* +- * GPIO name legend: proper name = the GPIO line is used as GPIO +- * NC = not connected (pin out but not routed from the chip to +- * anything the board) +- * "[PER]" = pin is muxed for [peripheral] (not GPIO) +- * LSEC = Low Speed External Connector +- * HSEC = High Speed External Connector +- * +- * Line names are taken from the schematic "DragonBoard410c" +- * dated monday, august 31, 2015. Page 5 in particular. +- * +- * For the lines routed to the external connectors the +- * lines are named after the 96Boards CE Specification 1.0, +- * Appendix "Expansion Connector Signal Description". +- * +- * When the 96Board naming of a line and the schematic name of +- * the same line are in conflict, the 96Board specification +- * takes precedence, which means that the external UART on the +- * LSEC is named UART0 while the schematic and SoC names this +- * UART3. This is only for the informational lines i.e. "[FOO]", +- * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only +- * ones actually used for GPIO. +- */ +- +-&msmgpio { +- gpio-line-names = +- "[UART0_TX]", /* GPIO_0, LSEC pin 5 */ +- "[UART0_RX]", /* GPIO_1, LSEC pin 7 */ +- "[UART0_CTS_N]", /* GPIO_2, LSEC pin 3 */ +- "[UART0_RTS_N]", /* GPIO_3, LSEC pin 9 */ +- "[UART1_TX]", /* GPIO_4, LSEC pin 11 */ +- "[UART1_RX]", /* GPIO_5, LSEC pin 13 */ +- "[I2C0_SDA]", /* GPIO_8, LSEC pin 17 */ +- "[I2C0_SCL]", /* GPIO_7, LSEC pin 15 */ +- "[SPI1_DOUT]", /* SPI1_MOSI, HSEC pin 1 */ +- "[SPI1_DIN]", /* SPI1_MISO, HSEC pin 11 */ +- "[SPI1_CS]", /* SPI1_CS_N, HSEC pin 7 */ +- "[SPI1_SCLK]", /* SPI1_CLK, HSEC pin 9 */ +- "GPIO-B", /* LS_EXP_GPIO_B, LSEC pin 24 */ +- "GPIO-C", /* LS_EXP_GPIO_C, LSEC pin 25 */ +- "[I2C3_SDA]", /* HSEC pin 38 */ +- "[I2C3_SCL]", /* HSEC pin 36 */ +- "[SPI0_MOSI]", /* LSEC pin 14 */ +- "[SPI0_MISO]", /* LSEC pin 10 */ +- "[SPI0_CS_N]", /* LSEC pin 12 */ +- "[SPI0_CLK]", /* LSEC pin 8 */ +- "HDMI_HPD_N", /* GPIO 20 */ +- "USR_LED_1_CTRL", +- "[I2C1_SDA]", /* GPIO_22, LSEC pin 21 */ +- "[I2C1_SCL]", /* GPIO_23, LSEC pin 19 */ +- "GPIO-G", /* LS_EXP_GPIO_G, LSEC pin 29 */ +- "GPIO-H", /* LS_EXP_GPIO_H, LSEC pin 30 */ +- "[CSI0_MCLK]", /* HSEC pin 15 */ +- "[CSI1_MCLK]", /* HSEC pin 17 */ +- "GPIO-K", /* LS_EXP_GPIO_K, LSEC pin 33 */ +- "[I2C2_SDA]", /* HSEC pin 34 */ +- "[I2C2_SCL]", /* HSEC pin 32 */ +- "DSI2HDMI_INT_N", +- "DSI_SW_SEL_APQ", +- "GPIO-L", /* LS_EXP_GPIO_L, LSEC pin 34 */ +- "GPIO-J", /* LS_EXP_GPIO_J, LSEC pin 32 */ +- "GPIO-I", /* LS_EXP_GPIO_I, LSEC pin 31 */ +- "GPIO-A", /* LS_EXP_GPIO_A, LSEC pin 23 */ +- "FORCED_USB_BOOT", +- "SD_CARD_DET_N", +- "[WCSS_BT_SSBI]", +- "[WCSS_WLAN_DATA_2]", /* GPIO 40 */ +- "[WCSS_WLAN_DATA_1]", +- "[WCSS_WLAN_DATA_0]", +- "[WCSS_WLAN_SET]", +- "[WCSS_WLAN_CLK]", +- "[WCSS_FM_SSBI]", +- "[WCSS_FM_SDI]", +- "[WCSS_BT_DAT_CTL]", +- "[WCSS_BT_DAT_STB]", +- "NC", +- "NC", /* GPIO 50 */ +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", /* GPIO 60 */ +- "NC", +- "NC", +- "[CDC_PDM0_CLK]", +- "[CDC_PDM0_SYNC]", +- "[CDC_PDM0_TX0]", +- "[CDC_PDM0_RX0]", +- "[CDC_PDM0_RX1]", +- "[CDC_PDM0_RX2]", +- "GPIO-D", /* LS_EXP_GPIO_D, LSEC pin 26 */ +- "NC", /* GPIO 70 */ +- "NC", +- "NC", +- "NC", +- "NC", /* GPIO 74 */ +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "BOOT_CONFIG_0", /* GPIO 80 */ +- "BOOT_CONFIG_1", +- "BOOT_CONFIG_2", +- "BOOT_CONFIG_3", +- "NC", +- "NC", +- "BOOT_CONFIG_5", +- "NC", +- "NC", +- "NC", +- "NC", /* GPIO 90 */ +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", /* GPIO 100 */ +- "NC", +- "NC", +- "NC", +- "SSBI_GPS", +- "NC", +- "NC", +- "KEY_VOLP_N", +- "NC", +- "NC", +- "[LS_EXP_MI2S_WS]", /* GPIO 110 */ +- "NC", +- "NC", +- "[LS_EXP_MI2S_SCK]", +- "[LS_EXP_MI2S_DATA0]", +- "GPIO-E", /* LS_EXP_GPIO_E, LSEC pin 27 */ +- "NC", +- "[DSI2HDMI_MI2S_WS]", +- "[DSI2HDMI_MI2S_SCK]", +- "[DSI2HDMI_MI2S_DATA0]", +- "USR_LED_2_CTRL", /* GPIO 120 */ +- "SB_HS_ID"; +- +- msmgpio_leds: msmgpio-leds { +- pins = "gpio21", "gpio120"; +- function = "gpio"; +- +- output-low; +- }; +- +- usb_id_default: usb-id-default { +- pins = "gpio121"; +- function = "gpio"; +- +- drive-strength = <8>; +- input-enable; +- bias-pull-up; +- }; +- +- adv7533_int_active: adv533-int-active { +- pins = "gpio31"; +- function = "gpio"; +- +- drive-strength = <16>; +- bias-disable; +- }; +- +- adv7533_int_suspend: adv7533-int-suspend { +- pins = "gpio31"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- adv7533_switch_active: adv7533-switch-active { +- pins = "gpio32"; +- function = "gpio"; +- +- drive-strength = <16>; +- bias-disable; +- }; +- +- adv7533_switch_suspend: adv7533-switch-suspend { +- pins = "gpio32"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- msm_key_volp_n_default: msm-key-volp-n-default { +- pins = "gpio107"; +- function = "gpio"; +- +- drive-strength = <8>; +- input-enable; +- bias-pull-up; +- }; +-}; +- +-&pm8916_gpios { +- gpio-line-names = +- "USR_LED_3_CTRL", +- "USR_LED_4_CTRL", +- "USB_HUB_RESET_N_PM", +- "USB_SW_SEL_PM"; +- +- usb_hub_reset_pm: usb-hub-reset-pm { +- pins = "gpio3"; +- function = PMIC_GPIO_FUNC_NORMAL; +- +- input-disable; +- output-high; +- }; +- +- usb_hub_reset_pm_device: usb-hub-reset-pm-device { +- pins = "gpio3"; +- function = PMIC_GPIO_FUNC_NORMAL; +- +- output-low; +- }; +- +- usb_sw_sel_pm: usb-sw-sel-pm { +- pins = "gpio4"; +- function = PMIC_GPIO_FUNC_NORMAL; +- +- power-source = ; +- input-disable; +- output-high; +- }; +- +- usb_sw_sel_pm_device: usb-sw-sel-pm-device { +- pins = "gpio4"; +- function = PMIC_GPIO_FUNC_NORMAL; +- +- power-source = ; +- input-disable; +- output-low; +- }; +- +- pm8916_gpios_leds: pm8916-gpios-leds { +- pins = "gpio1", "gpio2"; +- function = PMIC_GPIO_FUNC_NORMAL; +- +- output-low; +- }; +-}; +- +-&pm8916_mpps { +- gpio-line-names = +- "VDD_PX_BIAS", +- "WLAN_LED_CTRL", +- "BT_LED_CTRL", +- "GPIO-F"; /* LS_EXP_GPIO_F, LSEC pin 28 */ +- +- pinctrl-names = "default"; +- pinctrl-0 = <&ls_exp_gpio_f>; +- +- ls_exp_gpio_f: pm8916-mpp4 { +- pins = "mpp4"; +- function = "digital"; +- +- output-low; +- power-source = ; // 1.8V +- }; +- +- pm8916_mpps_leds: pm8916-mpps-leds { +- pins = "mpp2", "mpp3"; +- function = "digital"; +- +- output-low; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/apq8094-sony-xperia-kitakami-karin_windy.dts b/scripts/dtc/include-prefixes/arm64/qcom/apq8094-sony-xperia-kitakami-karin_windy.dts +deleted file mode 100644 +index a8dffc8c64ea..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/apq8094-sony-xperia-kitakami-karin_windy.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Konrad Dybcio +- */ +- +-/dts-v1/; +- +-/* As the names may imply, there is quite a bunch of duplication there. */ +-#include "msm8994-sony-xperia-kitakami-karin.dts" +- +-/ { +- model = "Sony Xperia Z4 Tablet (Wi-Fi)"; +- compatible = "sony,karin_windy", "qcom,apq8094"; +- +- /* +- * This model uses the APQ variant of MSM8994 (APQ8094). +- * The v1/v2/v2.1 story (from kitakami.dtsi) also applies here. +- */ +- qcom,msm-id = <253 0x20000>, <253 0x20001>; +-}; +- +-/delete-node/ &pm8994_l1; +-/delete-node/ &pm8994_l19; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/apq8096-db820c.dts b/scripts/dtc/include-prefixes/arm64/qcom/apq8096-db820c.dts +deleted file mode 100644 +index 757afa27424d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/apq8096-db820c.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "apq8096-db820c.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. DB820c"; +- compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/apq8096-db820c.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/apq8096-db820c.dtsi +deleted file mode 100644 +index 51e17094d7b1..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/apq8096-db820c.dtsi ++++ /dev/null +@@ -1,1105 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. +- */ +- +-#include "msm8996.dtsi" +-#include "pm8994.dtsi" +-#include "pmi8994.dtsi" +-#include +-#include +-#include +-#include +-#include +- +-/* +- * GPIO name legend: proper name = the GPIO line is used as GPIO +- * NC = not connected (pin out but not routed from the chip to +- * anything the board) +- * "[PER]" = pin is muxed for [peripheral] (not GPIO) +- * LSEC = Low Speed External Connector +- * P HSEC = Primary High Speed External Connector +- * S HSEC = Secondary High Speed External Connector +- * J14 = Camera Connector +- * TP = Test Points +- * +- * Line names are taken from the schematic "DragonBoard 820c", +- * drawing no: LM25-P2751-1 +- * +- * For the lines routed to the external connectors the +- * lines are named after the 96Boards CE Specification 1.0, +- * Appendix "Expansion Connector Signal Description". +- * +- * When the 96Board naming of a line and the schematic name of +- * the same line are in conflict, the 96Board specification +- * takes precedence, which means that the external UART on the +- * LSEC is named UART0 while the schematic and SoC names this +- * UART3. This is only for the informational lines i.e. "[FOO]", +- * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only +- * ones actually used for GPIO. +- */ +- +-/ { +- aliases { +- serial0 = &blsp2_uart2; +- serial1 = &blsp2_uart3; +- serial2 = &blsp1_uart2; +- i2c0 = &blsp1_i2c3; +- i2c1 = &blsp2_i2c1; +- i2c2 = &blsp2_i2c1; +- spi0 = &blsp1_spi1; +- spi1 = &blsp2_spi6; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- clocks { +- compatible = "simple-bus"; +- divclk4: divclk4 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "divclk4"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&divclk4_pin_a>; +- }; +- +- div1_mclk: divclk1 { +- compatible = "gpio-gate-clock"; +- pinctrl-0 = <&audio_mclk>; +- pinctrl-names = "default"; +- clocks = <&rpmcc RPM_SMD_DIV_CLK1>; +- #clock-cells = <0>; +- enable-gpios = <&pm8994_gpios 15 0>; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- autorepeat; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&volume_up_gpio>; +- +- button@0 { +- label = "Volume Up"; +- linux,code = ; +- gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- usb2_id: usb2-id { +- compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb2_vbus_det_gpio>; +- }; +- +- usb3_id: usb3-id { +- compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb3_vbus_det_gpio>; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- }; +- +- wlan_en: wlan-en-1-8v { +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_en_gpios>; +- compatible = "regulator-fixed"; +- regulator-name = "wlan-en-regulator"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- gpio = <&pm8994_gpios 8 0>; +- +- /* WLAN card specific delay */ +- startup-delay-us = <70000>; +- enable-active-high; +- }; +-}; +- +-&blsp1_i2c3 { +- /* On Low speed expansion */ +- label = "LS-I2C0"; +- status = "okay"; +-}; +- +-&blsp1_spi1 { +- /* On Low speed expansion */ +- label = "LS-SPI0"; +- status = "okay"; +-}; +- +-&blsp1_uart2 { +- label = "BT-UART"; +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp1_uart2_default>; +- pinctrl-1 = <&blsp1_uart2_sleep>; +- +- bluetooth { +- compatible = "qcom,qca6174-bt"; +- +- /* bt_disable_n gpio */ +- enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>; +- +- clocks = <&divclk4>; +- }; +-}; +- +-&adsp_pil { +- status = "okay"; +-}; +- +-&blsp2_i2c1 { +- /* On High speed expansion */ +- label = "HS-I2C2"; +- status = "okay"; +-}; +- +-&blsp2_i2c1 { +- /* On Low speed expansion */ +- label = "LS-I2C1"; +- status = "okay"; +-}; +- +-&blsp2_spi6 { +- /* On High speed expansion */ +- label = "HS-SPI1"; +- status = "okay"; +-}; +- +-&blsp2_uart2 { +- label = "LS-UART1"; +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp2_uart2_2pins_default>; +- pinctrl-1 = <&blsp2_uart2_2pins_sleep>; +-}; +- +-&blsp2_uart3 { +- label = "LS-UART0"; +- status = "disabled"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp2_uart3_4pins_default>; +- pinctrl-1 = <&blsp2_uart3_4pins_sleep>; +-}; +- +-&camss { +- vdda-supply = <&vreg_l2a_1p25>; +-}; +- +-&gpu { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>; +- pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>; +- +- core-vdda-supply = <&vreg_l12a_1p8>; +- core-vcc-supply = <&vreg_s4a_1p8>; +-}; +- +-&hdmi_phy { +- status = "okay"; +- +- vddio-supply = <&vreg_l12a_1p8>; +- vcca-supply = <&vreg_l28a_0p925>; +- #phy-cells = <0>; +-}; +- +-&hsusb_phy1 { +- status = "okay"; +- +- vdda-pll-supply = <&vreg_l12a_1p8>; +- vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; +-}; +- +-&hsusb_phy2 { +- status = "okay"; +- +- vdda-pll-supply = <&vreg_l12a_1p8>; +- vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; +-}; +- +-&mdp { +- status = "okay"; +-}; +- +-&mdss { +- status = "okay"; +-}; +- +-&mmcc { +- vdd-gfx-supply = <&vdd_gfx>; +-}; +- +-&pm8994_resin { +- status = "okay"; +- linux,code = ; +-}; +- +-&tlmm { +- gpio-line-names = +- "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */ +- "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */ +- "[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC pin 12 */ +- "[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC pin 8 */ +- "[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC pin 11 */ +- "[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC pin 13 */ +- "[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC pin 21 */ +- "[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC pin 19 */ +- "GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 */ +- "TP93", /* GPIO_9 */ +- "GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 */ +- "[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */ +- "NC", /* GPIO_12 */ +- "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC pin 15 */ +- "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */ +- "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC pin 17 */ +- "TP99", /* GPIO_16 */ +- "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC pin 34 */ +- "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC pin 32 */ +- "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */ +- "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */ +- "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */ +- "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */ +- "GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */ +- "GPIO-D", /* GPIO_24, LSEC pin 26 */ +- "GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */ +- "GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 32 */ +- "BLSP6_I2C_SDA", /* GPIO_27 */ +- "BLSP6_I2C_SCL", /* GPIO_28 */ +- "GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 */ +- "GPIO30", /* GPIO_30, S HSEC pin 4 */ +- "HDMI_CEC", /* GPIO_31 */ +- "HDMI_DDC_CLOCK", /* GPIO_32 */ +- "HDMI_DDC_DATA", /* GPIO_33 */ +- "HDMI_HOT_PLUG_DETECT", /* GPIO_34 */ +- "PCIE0_RST_N", /* GPIO_35 */ +- "PCIE0_CLKREQ_N", /* GPIO_36 */ +- "PCIE0_WAKE", /* GPIO_37 */ +- "SD_CARD_DET_N", /* GPIO_38 */ +- "TSIF1_SYNC", /* GPIO_39, S HSEC pin 48 */ +- "W_DISABLE_N", /* GPIO_40 */ +- "[BLSP9_UART_TX]", /* GPIO_41 */ +- "[BLSP9_UART_RX]", /* GPIO_42 */ +- "[BLSP2_UART_CTS_N]", /* GPIO_43 */ +- "[BLSP2_UART_RFR_N]", /* GPIO_44 */ +- "[BLSP3_UART_TX]", /* GPIO_45 */ +- "[BLSP3_UART_RX]", /* GPIO_46 */ +- "[I2C0_SDA]", /* GPIO_47, LS_I2C0_SDA, LSEC pin 17 */ +- "[I2C0_SCL]", /* GPIO_48, LS_I2C0_SCL, LSEC pin 15 */ +- "[UART0_TxD]", /* GPIO_49, BLSP9_UART_TX, LSEC pin 5 */ +- "[UART0_RxD]", /* GPIO_50, BLSP9_UART_RX, LSEC pin 7 */ +- "[UART0_CTS]", /* GPIO_51, BLSP9_UART_CTS_N, LSEC pin 3 */ +- "[UART0_RTS]", /* GPIO_52, BLSP9_UART_RFR_N, LSEC pin 9 */ +- "[CODEC_INT1_N]", /* GPIO_53 */ +- "[CODEC_INT2_N]", /* GPIO_54 */ +- "[BLSP7_I2C_SDA]", /* GPIO_55 */ +- "[BLSP7_I2C_SCL]", /* GPIO_56 */ +- "MI2S_MCLK", /* GPIO_57, S HSEC pin 3 */ +- "[PCM_CLK]", /* GPIO_58, QUA_MI2S_SCK, LSEC pin 18 */ +- "[PCM_FS]", /* GPIO_59, QUA_MI2S_WS, LSEC pin 16 */ +- "[PCM_DO]", /* GPIO_60, QUA_MI2S_DATA0, LSEC pin 20 */ +- "[PCM_DI]", /* GPIO_61, QUA_MI2S_DATA1, LSEC pin 22 */ +- "GPIO-E", /* GPIO_62, LSEC pin 27 */ +- "TP87", /* GPIO_63 */ +- "[CODEC_RST_N]", /* GPIO_64 */ +- "[PCM1_CLK]", /* GPIO_65 */ +- "[PCM1_SYNC]", /* GPIO_66 */ +- "[PCM1_DIN]", /* GPIO_67 */ +- "[PCM1_DOUT]", /* GPIO_68 */ +- "AUDIO_REF_CLK", /* GPIO_69 */ +- "SLIMBUS_CLK", /* GPIO_70 */ +- "SLIMBUS_DATA0", /* GPIO_71 */ +- "SLIMBUS_DATA1", /* GPIO_72 */ +- "NC", /* GPIO_73 */ +- "NC", /* GPIO_74 */ +- "NC", /* GPIO_75 */ +- "NC", /* GPIO_76 */ +- "TP94", /* GPIO_77 */ +- "NC", /* GPIO_78 */ +- "TP95", /* GPIO_79 */ +- "GPIO-A", /* GPIO_80, MEMS_RESET_N, LSEC pin 23 */ +- "TP88", /* GPIO_81 */ +- "TP89", /* GPIO_82 */ +- "TP90", /* GPIO_83 */ +- "TP91", /* GPIO_84 */ +- "[SD_DAT0]", /* GPIO_85, BLSP12_SPI_MOSI, P HSEC pin 1 */ +- "[SD_CMD]", /* GPIO_86, BLSP12_SPI_MISO, P HSEC pin 11 */ +- "[SD_DAT3]", /* GPIO_87, BLSP12_SPI_CS_N, P HSEC pin 7 */ +- "[SD_SCLK]", /* GPIO_88, BLSP12_SPI_CLK, P HSEC pin 9 */ +- "TSIF1_CLK", /* GPIO_89, S HSEC pin 42 */ +- "TSIF1_EN", /* GPIO_90, S HSEC pin 46 */ +- "TSIF1_DATA", /* GPIO_91, S HSEC pin 44 */ +- "NC", /* GPIO_92 */ +- "TSIF2_CLK", /* GPIO_93, S HSEC pin 52 */ +- "TSIF2_EN", /* GPIO_94, S HSEC pin 56 */ +- "TSIF2_DATA", /* GPIO_95, S HSEC pin 54 */ +- "TSIF2_SYNC", /* GPIO_96, S HSEC pin 58 */ +- "NC", /* GPIO_97 */ +- "CAM1_STANDBY_N", /* GPIO_98 */ +- "NC", /* GPIO_99 */ +- "NC", /* GPIO_100 */ +- "[LCD1_RESET_N]", /* GPIO_101, S HSEC pin 51 */ +- "BOOT_CONFIG1", /* GPIO_102 */ +- "USB_HUB_RESET", /* GPIO_103 */ +- "CAM1_RST_N", /* GPIO_104 */ +- "NC", /* GPIO_105 */ +- "NC", /* GPIO_106 */ +- "NC", /* GPIO_107 */ +- "NC", /* GPIO_108 */ +- "NC", /* GPIO_109 */ +- "NC", /* GPIO_110 */ +- "NC", /* GPIO_111 */ +- "NC", /* GPIO_112 */ +- "PMI8994_BUA", /* GPIO_113 */ +- "PCIE2_RST_N", /* GPIO_114 */ +- "PCIE2_CLKREQ_N", /* GPIO_115 */ +- "PCIE2_WAKE", /* GPIO_116 */ +- "SSC_IRQ_0", /* GPIO_117 */ +- "SSC_IRQ_1", /* GPIO_118 */ +- "SSC_IRQ_2", /* GPIO_119 */ +- "NC", /* GPIO_120 */ +- "GPIO121", /* GPIO_121, S HSEC pin 2 */ +- "NC", /* GPIO_122 */ +- "SSC_IRQ_6", /* GPIO_123 */ +- "SSC_IRQ_7", /* GPIO_124 */ +- "GPIO-C", /* GPIO_125, TS_INT0, LSEC pin 25 */ +- "BOOT_CONFIG5", /* GPIO_126 */ +- "NC", /* GPIO_127 */ +- "NC", /* GPIO_128 */ +- "BOOT_CONFIG7", /* GPIO_129 */ +- "PCIE1_RST_N", /* GPIO_130 */ +- "PCIE1_CLKREQ_N", /* GPIO_131 */ +- "PCIE1_WAKE", /* GPIO_132 */ +- "GPIO-L", /* GPIO_133, CAM2_STANDBY_N, LSEC pin 34 */ +- "NC", /* GPIO_134 */ +- "NC", /* GPIO_135 */ +- "BOOT_CONFIG8", /* GPIO_136 */ +- "NC", /* GPIO_137 */ +- "NC", /* GPIO_138 */ +- "GPS_SSBI2", /* GPIO_139 */ +- "GPS_SSBI1", /* GPIO_140 */ +- "NC", /* GPIO_141 */ +- "NC", /* GPIO_142 */ +- "NC", /* GPIO_143 */ +- "BOOT_CONFIG6", /* GPIO_144 */ +- "NC", /* GPIO_145 */ +- "NC", /* GPIO_146 */ +- "NC", /* GPIO_147 */ +- "NC", /* GPIO_148 */ +- "NC"; /* GPIO_149 */ +- +- sdc2_cd_on: sdc2_cd_on { +- mux { +- pins = "gpio38"; +- function = "gpio"; +- }; +- +- config { +- pins = "gpio38"; +- bias-pull-up; /* pull up */ +- drive-strength = <16>; /* 16 MA */ +- }; +- }; +- +- sdc2_cd_off: sdc2_cd_off { +- mux { +- pins = "gpio38"; +- function = "gpio"; +- }; +- +- config { +- pins = "gpio38"; +- bias-pull-up; /* pull up */ +- drive-strength = <2>; /* 2 MA */ +- }; +- }; +- +- blsp1_uart2_default: blsp1_uart2_default { +- mux { +- pins = "gpio41", "gpio42", "gpio43", "gpio44"; +- function = "blsp_uart2"; +- }; +- +- config { +- pins = "gpio41", "gpio42", "gpio43", "gpio44"; +- drive-strength = <16>; +- bias-disable; +- }; +- }; +- +- blsp1_uart2_sleep: blsp1_uart2_sleep { +- mux { +- pins = "gpio41", "gpio42", "gpio43", "gpio44"; +- function = "gpio"; +- }; +- +- config { +- pins = "gpio41", "gpio42", "gpio43", "gpio44"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- hdmi_hpd_active: hdmi_hpd_active { +- mux { +- pins = "gpio34"; +- function = "hdmi_hot"; +- }; +- +- config { +- pins = "gpio34"; +- bias-pull-down; +- drive-strength = <16>; +- }; +- }; +- +- hdmi_hpd_suspend: hdmi_hpd_suspend { +- mux { +- pins = "gpio34"; +- function = "hdmi_hot"; +- }; +- +- config { +- pins = "gpio34"; +- bias-pull-down; +- drive-strength = <2>; +- }; +- }; +- +- hdmi_ddc_active: hdmi_ddc_active { +- mux { +- pins = "gpio32", "gpio33"; +- function = "hdmi_ddc"; +- }; +- +- config { +- pins = "gpio32", "gpio33"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- }; +- +- hdmi_ddc_suspend: hdmi_ddc_suspend { +- mux { +- pins = "gpio32", "gpio33"; +- function = "hdmi_ddc"; +- }; +- +- config { +- pins = "gpio32", "gpio33"; +- drive-strength = <2>; +- bias-pull-down; +- }; +- }; +-}; +- +-&pcie0 { +- status = "okay"; +- perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>; +- vddpe-3v3-supply = <&wlan_en>; +- vdda-supply = <&vreg_l28a_0p925>; +-}; +- +-&pcie1 { +- status = "okay"; +- perst-gpio = <&tlmm 130 GPIO_ACTIVE_LOW>; +- vdda-supply = <&vreg_l28a_0p925>; +-}; +- +-&pcie2 { +- status = "okay"; +- perst-gpio = <&tlmm 114 GPIO_ACTIVE_LOW>; +- vdda-supply = <&vreg_l28a_0p925>; +-}; +- +-&pcie_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l28a_0p925>; +- vdda-pll-supply = <&vreg_l12a_1p8>; +-}; +- +-&pm8994_gpios { +- gpio-line-names = +- "NC", +- "KEY_VOLP_N", +- "NC", +- "BL1_PWM", +- "GPIO-F", /* BL0_PWM, LSEC pin 28 */ +- "BL1_EN", +- "NC", +- "WLAN_EN", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "DIVCLK1", +- "DIVCLK2", +- "DIVCLK3", +- "DIVCLK4", +- "BT_EN", +- "PMIC_SLB", +- "PMIC_BUA", +- "USB_VBUS_DET"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>; +- +- ls_exp_gpio_f: pm8994_gpio5 { +- pinconf { +- pins = "gpio5"; +- output-low; +- power-source = <2>; // PM8994_GPIO_S4, 1.8V +- }; +- }; +- +- bt_en_gpios: bt_en_gpios { +- pinconf { +- pins = "gpio19"; +- function = PMIC_GPIO_FUNC_NORMAL; +- output-low; +- power-source = ; // 1.8V +- qcom,drive-strength = ; +- bias-pull-down; +- }; +- }; +- +- wlan_en_gpios: wlan_en_gpios { +- pinconf { +- pins = "gpio8"; +- function = PMIC_GPIO_FUNC_NORMAL; +- output-low; +- power-source = ; // 1.8V +- qcom,drive-strength = ; +- bias-pull-down; +- }; +- }; +- +- audio_mclk: clk_div1 { +- pinconf { +- pins = "gpio15"; +- function = "func1"; +- power-source = ; // 1.8V +- }; +- }; +- +- volume_up_gpio: pm8996_gpio2 { +- pinconf { +- pins = "gpio2"; +- function = "normal"; +- input-enable; +- drive-push-pull; +- bias-pull-up; +- qcom,drive-strength = ; +- power-source = ; // 1.8V +- }; +- }; +- +- divclk4_pin_a: divclk4 { +- pinconf { +- pins = "gpio18"; +- function = PMIC_GPIO_FUNC_FUNC2; +- +- bias-disable; +- power-source = ; +- }; +- }; +- +- usb3_vbus_det_gpio: pm8996_gpio22 { +- pinconf { +- pins = "gpio22"; +- function = PMIC_GPIO_FUNC_NORMAL; +- input-enable; +- bias-pull-down; +- qcom,drive-strength = ; +- power-source = ; // 1.8V +- }; +- }; +-}; +- +-&pm8994_mpps { +- gpio-line-names = +- "VDDPX_BIAS", +- "WIFI_LED", +- "NC", +- "BT_LED", +- "PM_MPP05", +- "PM_MPP06", +- "PM_MPP07", +- "NC"; +-}; +- +-&pm8994_spmi_regulators { +- qcom,saw-reg = <&saw3>; +- s9 { +- qcom,saw-slave; +- }; +- s10 { +- qcom,saw-slave; +- }; +- s11 { +- qcom,saw-leader; +- regulator-always-on; +- regulator-min-microvolt = <980000>; +- regulator-max-microvolt = <980000>; +- }; +-}; +- +-&pmi8994_gpios { +- gpio-line-names = +- "NC", +- "SPKR_AMP_EN1", +- "SPKR_AMP_EN2", +- "TP61", +- "NC", +- "USB2_VBUS_DET", +- "NC", +- "NC", +- "NC", +- "NC"; +- +- usb2_vbus_det_gpio: pmi8996_gpio6 { +- pinconf { +- pins = "gpio6"; +- function = PMIC_GPIO_FUNC_NORMAL; +- input-enable; +- bias-pull-down; +- qcom,drive-strength = ; +- power-source = ; // 1.8V +- }; +- }; +-}; +- +-&pmi8994_spmi_regulators { +- vdd_gfx: s2@1700 { +- reg = <0x1700 0x100>; +- regulator-name = "VDD_GFX"; +- regulator-min-microvolt = <980000>; +- regulator-max-microvolt = <980000>; +- }; +-}; +- +-&rpm_requests { +- pm8994-regulators { +- compatible = "qcom,rpm-pm8994-regulators"; +- +- vdd_s1-supply = <&vph_pwr>; +- vdd_s2-supply = <&vph_pwr>; +- vdd_s3-supply = <&vph_pwr>; +- vdd_s4-supply = <&vph_pwr>; +- vdd_s5-supply = <&vph_pwr>; +- vdd_s6-supply = <&vph_pwr>; +- vdd_s7-supply = <&vph_pwr>; +- vdd_s8-supply = <&vph_pwr>; +- vdd_s9-supply = <&vph_pwr>; +- vdd_s10-supply = <&vph_pwr>; +- vdd_s11-supply = <&vph_pwr>; +- vdd_s12-supply = <&vph_pwr>; +- vdd_l1-supply = <&vreg_s1b_1p025>; +- vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>; +- vdd_l3_l11-supply = <&vreg_s3a_1p3>; +- vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>; +- vdd_l5_l7-supply = <&vreg_s5a_2p15>; +- vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>; +- vdd_l8_l16_l30-supply = <&vph_pwr>; +- vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>; +- vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>; +- vdd_l14_l15-supply = <&vreg_s5a_2p15>; +- vdd_l17_l29-supply = <&vph_pwr_bbyp>; +- vdd_l20_l21-supply = <&vph_pwr_bbyp>; +- vdd_l25-supply = <&vreg_s3a_1p3>; +- vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; +- +- vreg_s3a_1p3: s3 { +- regulator-name = "vreg_s3a_1p3"; +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- }; +- +- /** +- * 1.8v required on LS expansion +- * for mezzanine boards +- */ +- vreg_s4a_1p8: s4 { +- regulator-name = "vreg_s4a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- vreg_s5a_2p15: s5 { +- regulator-name = "vreg_s5a_2p15"; +- regulator-min-microvolt = <2150000>; +- regulator-max-microvolt = <2150000>; +- }; +- vreg_s7a_1p0: s7 { +- regulator-name = "vreg_s7a_1p0"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- }; +- +- vreg_l1a_1p0: l1 { +- regulator-name = "vreg_l1a_1p0"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- vreg_l2a_1p25: l2 { +- regulator-name = "vreg_l2a_1p25"; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- }; +- vreg_l3a_0p875: l3 { +- regulator-name = "vreg_l3a_0p875"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <850000>; +- }; +- vreg_l4a_1p225: l4 { +- regulator-name = "vreg_l4a_1p225"; +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- vreg_l6a_1p2: l6 { +- regulator-name = "vreg_l6a_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- vreg_l8a_1p8: l8 { +- regulator-name = "vreg_l8a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l9a_1p8: l9 { +- regulator-name = "vreg_l9a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l10a_1p8: l10 { +- regulator-name = "vreg_l10a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l11a_1p15: l11 { +- regulator-name = "vreg_l11a_1p15"; +- regulator-min-microvolt = <1150000>; +- regulator-max-microvolt = <1150000>; +- }; +- vreg_l12a_1p8: l12 { +- regulator-name = "vreg_l12a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l13a_2p95: l13 { +- regulator-name = "vreg_l13a_2p95"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- vreg_l14a_1p8: l14 { +- regulator-name = "vreg_l14a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l15a_1p8: l15 { +- regulator-name = "vreg_l15a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l16a_2p7: l16 { +- regulator-name = "vreg_l16a_2p7"; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- vreg_l17a_2p8: l17 { +- regulator-name = "vreg_l17a_2p8"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- }; +- vreg_l18a_2p85: l18 { +- regulator-name = "vreg_l18a_2p85"; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2900000>; +- }; +- vreg_l19a_2p8: l19 { +- regulator-name = "vreg_l19a_2p8"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- vreg_l20a_2p95: l20 { +- regulator-name = "vreg_l20a_2p95"; +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- regulator-allow-set-load; +- }; +- vreg_l21a_2p95: l21 { +- regulator-name = "vreg_l21a_2p95"; +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- regulator-allow-set-load; +- regulator-system-load = <200000>; +- }; +- vreg_l22a_3p0: l22 { +- regulator-name = "vreg_l22a_3p0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- vreg_l23a_2p8: l23 { +- regulator-name = "vreg_l23a_2p8"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- vreg_l24a_3p075: l24 { +- regulator-name = "vreg_l24a_3p075"; +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- }; +- vreg_l25a_1p2: l25 { +- regulator-name = "vreg_l25a_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-allow-set-load; +- }; +- vreg_l26a_0p8: l27 { +- regulator-name = "vreg_l26a_0p8"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- vreg_l28a_0p925: l28 { +- regulator-name = "vreg_l28a_0p925"; +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <925000>; +- regulator-allow-set-load; +- }; +- vreg_l29a_2p8: l29 { +- regulator-name = "vreg_l29a_2p8"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- vreg_l30a_1p8: l30 { +- regulator-name = "vreg_l30a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l32a_1p8: l32 { +- regulator-name = "vreg_l32a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vreg_lvs1a_1p8: lvs1 { +- regulator-name = "vreg_lvs1a_1p8"; +- }; +- +- vreg_lvs2a_1p8: lvs2 { +- regulator-name = "vreg_lvs2a_1p8"; +- }; +- }; +- +- pmi8994-regulators { +- compatible = "qcom,rpm-pmi8994-regulators"; +- +- vdd_s1-supply = <&vph_pwr>; +- vdd_s2-supply = <&vph_pwr>; +- vdd_s3-supply = <&vph_pwr>; +- vdd_bst_byp-supply = <&vph_pwr>; +- +- vph_pwr_bbyp: boost-bypass { +- regulator-name = "vph_pwr_bbyp"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vreg_s1b_1p025: s1 { +- regulator-name = "vreg_s1b_1p025"; +- regulator-min-microvolt = <1025000>; +- regulator-max-microvolt = <1025000>; +- }; +- }; +-}; +- +-&sdhc2 { +- /* External SD card */ +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc2_state_on &sdc2_cd_on>; +- pinctrl-1 = <&sdc2_state_off &sdc2_cd_off>; +- cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; +- vmmc-supply = <&vreg_l21a_2p95>; +- vqmmc-supply = <&vreg_l13a_2p95>; +- status = "okay"; +-}; +- +-&q6asmdai { +- dai@0 { +- reg = <0>; +- }; +- +- dai@1 { +- reg = <1>; +- }; +- +- dai@2 { +- reg = <2>; +- }; +-}; +- +-&sound { +- compatible = "qcom,apq8096-sndcard"; +- model = "DB820c"; +- audio-routing = "RX_BIAS", "MCLK", +- "MM_DL1", "MultiMedia1 Playback", +- "MM_DL2", "MultiMedia2 Playback", +- "MultiMedia3 Capture", "MM_UL3"; +- +- mm1-dai-link { +- link-name = "MultiMedia1"; +- cpu { +- sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; +- }; +- }; +- +- mm2-dai-link { +- link-name = "MultiMedia2"; +- cpu { +- sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; +- }; +- }; +- +- mm3-dai-link { +- link-name = "MultiMedia3"; +- cpu { +- sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; +- }; +- }; +- +- hdmi-dai-link { +- link-name = "HDMI"; +- cpu { +- sound-dai = <&q6afedai HDMI_RX>; +- }; +- +- platform { +- sound-dai = <&q6routing>; +- }; +- +- codec { +- sound-dai = <&hdmi 0>; +- }; +- }; +- +- slim-dai-link { +- link-name = "SLIM Playback"; +- cpu { +- sound-dai = <&q6afedai SLIMBUS_6_RX>; +- }; +- +- platform { +- sound-dai = <&q6routing>; +- }; +- +- codec { +- sound-dai = <&wcd9335 6>; +- }; +- }; +- +- slimcap-dai-link { +- link-name = "SLIM Capture"; +- cpu { +- sound-dai = <&q6afedai SLIMBUS_0_TX>; +- }; +- +- platform { +- sound-dai = <&q6routing>; +- }; +- +- codec { +- sound-dai = <&wcd9335 1>; +- }; +- }; +-}; +- +-&ufsphy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l28a_0p925>; +- vdda-pll-supply = <&vreg_l12a_1p8>; +- vddp-ref-clk-supply = <&vreg_l25a_1p2>; +-}; +- +-&ufshc { +- status = "okay"; +- +- vcc-supply = <&vreg_l20a_2p95>; +- vccq-supply = <&vreg_l25a_1p2>; +- vccq2-supply = <&vreg_s4a_1p8>; +- +- vcc-max-microamp = <600000>; +- vccq-max-microamp = <450000>; +- vccq2-max-microamp = <450000>; +-}; +- +-&usb2 { +- status = "okay"; +- extcon = <&usb2_id>; +- +- dwc3@7600000 { +- extcon = <&usb2_id>; +- dr_mode = "otg"; +- maximum-speed = "high-speed"; +- }; +-}; +- +-&usb3 { +- status = "okay"; +- extcon = <&usb3_id>; +- +- dwc3@6a00000 { +- extcon = <&usb3_id>; +- dr_mode = "otg"; +- }; +-}; +- +-&usb3phy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l28a_0p925>; +- vdda-pll-supply = <&vreg_l12a_1p8>; +- +-}; +- +-&venus { +- status = "okay"; +-}; +- +-&wcd9335 { +- clock-names = "mclk", "slimbus"; +- clocks = <&div1_mclk>, +- <&rpmcc RPM_SMD_BB_CLK1>; +- +- vdd-buck-supply = <&vreg_s4a_1p8>; +- vdd-buck-sido-supply = <&vreg_s4a_1p8>; +- vdd-tx-supply = <&vreg_s4a_1p8>; +- vdd-rx-supply = <&vreg_s4a_1p8>; +- vdd-io-supply = <&vreg_s4a_1p8>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/apq8096-ifc6640.dts b/scripts/dtc/include-prefixes/arm64/qcom/apq8096-ifc6640.dts +deleted file mode 100644 +index a57c60070cdc..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/apq8096-ifc6640.dts ++++ /dev/null +@@ -1,405 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +- +-/dts-v1/; +- +-#include "msm8996.dtsi" +-#include "pm8994.dtsi" +-#include "pmi8994.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "Inforce 6640 Single Board Computer"; +- compatible = "inforce,ifc6640", "qcom,apq8096-sbc", "qcom,apq8096"; +- +- qcom,msm-id = <291 0x00030001>; +- qcom,board-id = <0x00010018 0>; +- +- aliases { +- serial0 = &blsp2_uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- v1p05: v1p05-regulator { +- compatible = "regulator-fixed"; +- reglator-name = "v1p05"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- +- vin-supply = <&v5p0>; +- }; +- +- v12_poe: v12-poe-regulator { +- compatible = "regulator-fixed"; +- reglator-name = "v12_poe"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- v3p3: v3p3-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "v3p3"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- vin-supply = <&v12_poe>; +- }; +- +- v5p0: v5p0-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "v5p0"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- vin-supply = <&v12_poe>; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-min-microvolt = <3800000>; +- regulator-max-microvolt = <3800000>; +- }; +-}; +- +-&blsp2_uart2 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp2_uart2_2pins_default>; +- pinctrl-1 = <&blsp2_uart2_2pins_sleep>; +-}; +- +-&gpu { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_phy { +- status = "okay"; +-}; +- +-&mdss { +- status = "okay"; +-}; +- +-&tlmm { +- sdc2_pins_default: sdc2-pins-default { +- clk { +- pins = "sdc2_clk"; +- bias-disable; +- drive-strength = <16>; +- }; +- +- cmd { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- data { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- cd { +- pins = "gpio38"; +- function = "gpio"; +- +- bias-pull-up; +- drive-strength = <16>; +- }; +- }; +- +- sdc2_pins_sleep: sdc2-pins-sleep { +- clk { +- pins = "sdc2_clk"; +- bias-disable; +- drive-strength = <2>; +- }; +- +- cmd { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- data { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- cd { +- pins = "gpio38"; +- function = "gpio"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +-}; +- +-&rpm_requests { +- pm8994-regulators { +- compatible = "qcom,rpm-pm8994-regulators"; +- +- vdd_s1-supply = <&vph_pwr>; +- vdd_s2-supply = <&vph_pwr>; +- vdd_s3-supply = <&vph_pwr>; +- vdd_s4-supply = <&vph_pwr>; +- vdd_s5-supply = <&vph_pwr>; +- vdd_s6-supply = <&vph_pwr>; +- vdd_s7-supply = <&vph_pwr>; +- vdd_s8-supply = <&vph_pwr>; +- vdd_s9-supply = <&vph_pwr>; +- vdd_s10-supply = <&vph_pwr>; +- vdd_s11-supply = <&vph_pwr>; +- vdd_s12-supply = <&vph_pwr>; +- vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>; +- vdd_l3_l11-supply = <&vreg_s3a_1p3>; +- vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>; +- vdd_l5_l7-supply = <&vreg_s5a_2p15>; +- vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>; +- vdd_l8_l16_l30-supply = <&vph_pwr>; +- vdd_l25-supply = <&vreg_s3a_1p3>; +- vdd_lvs1_2-supply = <&vreg_s4a_1p8>; +- +- vreg_s3a_1p3: s3 { +- regulator-name = "vreg_s3a_1p3"; +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- }; +- +- vreg_s4a_1p8: s4 { +- regulator-name = "vreg_s4a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- vreg_s5a_2p15: s5 { +- regulator-name = "vreg_s5a_2p15"; +- regulator-min-microvolt = <2150000>; +- regulator-max-microvolt = <2150000>; +- }; +- vreg_s7a_1p0: s7 { +- regulator-name = "vreg_s7a_1p0"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- }; +- +- vreg_l1a_1p0: l1 { +- regulator-name = "vreg_l1a_1p0"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- vreg_l2a_1p25: l2 { +- regulator-name = "vreg_l2a_1p25"; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- }; +- vreg_l3a_0p875: l3 { +- regulator-name = "vreg_l3a_0p875"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <850000>; +- }; +- vreg_l4a_1p225: l4 { +- regulator-name = "vreg_l4a_1p225"; +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- vreg_l6a_1p2: l6 { +- regulator-name = "vreg_l6a_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- vreg_l8a_1p8: l8 { +- regulator-name = "vreg_l8a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l9a_1p8: l9 { +- regulator-name = "vreg_l9a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l10a_1p8: l10 { +- regulator-name = "vreg_l10a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l11a_1p15: l11 { +- regulator-name = "vreg_l11a_1p15"; +- regulator-min-microvolt = <1150000>; +- regulator-max-microvolt = <1150000>; +- }; +- vreg_l12a_1p8: l12 { +- regulator-name = "vreg_l12a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l13a_2p95: l13 { +- regulator-name = "vreg_l13a_2p95"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- vreg_l14a_1p8: l14 { +- regulator-name = "vreg_l14a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l15a_1p8: l15 { +- regulator-name = "vreg_l15a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l16a_2p7: l16 { +- regulator-name = "vreg_l16a_2p7"; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- vreg_l17a_2p8: l17 { +- regulator-name = "vreg_l17a_2p8"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- }; +- vreg_l18a_2p85: l18 { +- regulator-name = "vreg_l18a_2p85"; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2900000>; +- }; +- vreg_l19a_2p8: l19 { +- regulator-name = "vreg_l19a_2p8"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- vreg_l20a_2p95: l20 { +- regulator-name = "vreg_l20a_2p95"; +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- regulator-allow-set-load; +- }; +- vreg_l21a_2p95: l21 { +- regulator-name = "vreg_l21a_2p95"; +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- }; +- vreg_l22a_3p0: l22 { +- regulator-name = "vreg_l22a_3p0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- vreg_l23a_2p8: l23 { +- regulator-name = "vreg_l23a_2p8"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- vreg_l24a_3p075: l24 { +- regulator-name = "vreg_l24a_3p075"; +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- }; +- vreg_l25a_1p2: l25 { +- regulator-name = "vreg_l25a_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-allow-set-load; +- }; +- vreg_l26a_0p8: l27 { +- regulator-name = "vreg_l26a_0p8"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- vreg_l28a_0p925: l28 { +- regulator-name = "vreg_l28a_0p925"; +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <925000>; +- regulator-allow-set-load; +- }; +- vreg_l29a_2p8: l29 { +- regulator-name = "vreg_l29a_2p8"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- vreg_l30a_1p8: l30 { +- regulator-name = "vreg_l30a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l32a_1p8: l32 { +- regulator-name = "vreg_l32a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vreg_lvs1a_1p8: lvs1 { +- regulator-name = "vreg_lvs1a_1p8"; +- }; +- +- vreg_lvs2a_1p8: lvs2 { +- regulator-name = "vreg_lvs2a_1p8"; +- }; +- }; +-}; +- +-&sdhc2 { +- status = "okay"; +- +- bus-width = <4>; +- +- cd-gpios = <&tlmm 38 0x1>; +- +- vmmc-supply = <&vreg_l21a_2p95>; +- vqmmc-supply = <&vreg_l13a_2p95>; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc2_pins_default>; +- pinctrl-1 = <&sdc2_pins_sleep>; +-}; +- +-&ufshc { +- status = "okay"; +- +- vcc-supply = <&vreg_l20a_2p95>; +- vccq-supply = <&vreg_l25a_1p2>; +- vccq2-supply = <&vreg_s4a_1p8>; +- +- vcc-max-microamp = <600000>; +- vccq-max-microamp = <450000>; +- vccq2-max-microamp = <450000>; +-}; +- +-&ufsphy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l28a_0p925>; +- vdda-pll-supply = <&vreg_l12a_1p8>; +- +- vdda-phy-max-microamp = <18380>; +- vdda-pll-max-microamp = <9440>; +-}; +- +-&venus { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/ipq6018-cp01-c1.dts b/scripts/dtc/include-prefixes/arm64/qcom/ipq6018-cp01-c1.dts +deleted file mode 100644 +index 5aec18308712..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/ipq6018-cp01-c1.dts ++++ /dev/null +@@ -1,88 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * IPQ6018 CP01 board device tree source +- * +- * Copyright (c) 2019, The Linux Foundation. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "ipq6018.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1"; +- compatible = "qcom,ipq6018-cp01", "qcom,ipq6018"; +- +- aliases { +- serial0 = &blsp1_uart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- bootargs-append = " swiotlb=1"; +- }; +-}; +- +-&blsp1_uart3 { +- pinctrl-0 = <&serial_3_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&i2c_1 { +- pinctrl-0 = <&i2c_1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&spi_0 { +- cs-select = <0>; +- status = "okay"; +- +- m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- compatible = "n25q128a11"; +- spi-max-frequency = <50000000>; +- }; +-}; +- +-&tlmm { +- i2c_1_pins: i2c-1-pins { +- pins = "gpio42", "gpio43"; +- function = "blsp2_i2c"; +- drive-strength = <8>; +- }; +- +- spi_0_pins: spi-0-pins { +- pins = "gpio38", "gpio39", "gpio40", "gpio41"; +- function = "blsp0_spi"; +- drive-strength = <8>; +- bias-pull-down; +- }; +-}; +- +-&qpic_bam { +- status = "okay"; +-}; +- +-&qpic_nand { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- nand-bus-width = <8>; +- }; +-}; +- +-&qusb_phy_1 { +- status = "ok"; +-}; +- +-&usb2 { +- status = "ok"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/ipq6018.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/ipq6018.dtsi +deleted file mode 100644 +index ce4c2b4a5fc0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/ipq6018.dtsi ++++ /dev/null +@@ -1,721 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * IPQ6018 SoC device tree source +- * +- * Copyright (c) 2019, The Linux Foundation. All rights reserved. +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&intc>; +- +- clocks { +- sleep_clk: sleep-clk { +- compatible = "fixed-clock"; +- clock-frequency = <32000>; +- #clock-cells = <0>; +- }; +- +- xo: xo { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- #clock-cells = <0>; +- }; +- }; +- +- cpus: cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- CPU0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0>; +- enable-method = "psci"; +- next-level-cache = <&L2_0>; +- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; +- clock-names = "cpu"; +- operating-points-v2 = <&cpu_opp_table>; +- cpu-supply = <&ipq6018_s2>; +- }; +- +- CPU1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x1>; +- next-level-cache = <&L2_0>; +- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; +- clock-names = "cpu"; +- operating-points-v2 = <&cpu_opp_table>; +- cpu-supply = <&ipq6018_s2>; +- }; +- +- CPU2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x2>; +- next-level-cache = <&L2_0>; +- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; +- clock-names = "cpu"; +- operating-points-v2 = <&cpu_opp_table>; +- cpu-supply = <&ipq6018_s2>; +- }; +- +- CPU3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x3>; +- next-level-cache = <&L2_0>; +- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; +- clock-names = "cpu"; +- operating-points-v2 = <&cpu_opp_table>; +- cpu-supply = <&ipq6018_s2>; +- }; +- +- L2_0: l2-cache { +- compatible = "cache"; +- cache-level = <0x2>; +- }; +- }; +- +- cpu_opp_table: cpu_opp_table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-864000000 { +- opp-hz = /bits/ 64 <864000000>; +- opp-microvolt = <725000>; +- clock-latency-ns = <200000>; +- }; +- opp-1056000000 { +- opp-hz = /bits/ 64 <1056000000>; +- opp-microvolt = <787500>; +- clock-latency-ns = <200000>; +- }; +- opp-1320000000 { +- opp-hz = /bits/ 64 <1320000000>; +- opp-microvolt = <862500>; +- clock-latency-ns = <200000>; +- }; +- opp-1440000000 { +- opp-hz = /bits/ 64 <1440000000>; +- opp-microvolt = <925000>; +- clock-latency-ns = <200000>; +- }; +- opp-1608000000 { +- opp-hz = /bits/ 64 <1608000000>; +- opp-microvolt = <987500>; +- clock-latency-ns = <200000>; +- }; +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <1062500>; +- clock-latency-ns = <200000>; +- }; +- }; +- +- firmware { +- scm { +- compatible = "qcom,scm"; +- }; +- }; +- +- tcsr_mutex: hwlock { +- compatible = "qcom,tcsr-mutex"; +- syscon = <&tcsr_mutex_regs 0 0x80>; +- #hwlock-cells = <1>; +- }; +- +- pmuv8: pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = ; +- }; +- +- psci: psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rpm_msg_ram: memory@60000 { +- reg = <0x0 0x60000 0x0 0x6000>; +- no-map; +- }; +- +- tz: memory@4a600000 { +- reg = <0x0 0x4a600000 0x0 0x00400000>; +- no-map; +- }; +- +- smem_region: memory@4aa00000 { +- reg = <0x0 0x4aa00000 0x0 0x00100000>; +- no-map; +- }; +- +- q6_region: memory@4ab00000 { +- reg = <0x0 0x4ab00000 0x0 0x05500000>; +- no-map; +- }; +- }; +- +- smem { +- compatible = "qcom,smem"; +- memory-region = <&smem_region>; +- hwlocks = <&tcsr_mutex 0>; +- }; +- +- soc: soc { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0 0 0 0 0x0 0xffffffff>; +- dma-ranges; +- compatible = "simple-bus"; +- +- prng: qrng@e1000 { +- compatible = "qcom,prng-ee"; +- reg = <0x0 0xe3000 0x0 0x1000>; +- clocks = <&gcc GCC_PRNG_AHB_CLK>; +- clock-names = "core"; +- }; +- +- cryptobam: dma-controller@704000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0x0 0x00704000 0x0 0x20000>; +- interrupts = ; +- clocks = <&gcc GCC_CRYPTO_AHB_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <1>; +- qcom,controlled-remotely; +- qcom,config-pipe-trust-reg = <0>; +- }; +- +- crypto: crypto@73a000 { +- compatible = "qcom,crypto-v5.1"; +- reg = <0x0 0x0073a000 0x0 0x6000>; +- clocks = <&gcc GCC_CRYPTO_AHB_CLK>, +- <&gcc GCC_CRYPTO_AXI_CLK>, +- <&gcc GCC_CRYPTO_CLK>; +- clock-names = "iface", "bus", "core"; +- dmas = <&cryptobam 2>, <&cryptobam 3>; +- dma-names = "rx", "tx"; +- }; +- +- tlmm: pinctrl@1000000 { +- compatible = "qcom,ipq6018-pinctrl"; +- reg = <0x0 0x01000000 0x0 0x300000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&tlmm 0 0 80>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- serial_3_pins: serial3-pinmux { +- pins = "gpio44", "gpio45"; +- function = "blsp2_uart"; +- drive-strength = <8>; +- bias-pull-down; +- }; +- +- qpic_pins: qpic-pins { +- pins = "gpio1", "gpio3", "gpio4", +- "gpio5", "gpio6", "gpio7", +- "gpio8", "gpio10", "gpio11", +- "gpio12", "gpio13", "gpio14", +- "gpio15", "gpio17"; +- function = "qpic_pad"; +- drive-strength = <8>; +- bias-disable; +- }; +- }; +- +- gcc: gcc@1800000 { +- compatible = "qcom,gcc-ipq6018"; +- reg = <0x0 0x01800000 0x0 0x80000>; +- clocks = <&xo>, <&sleep_clk>; +- clock-names = "xo", "sleep_clk"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- tcsr_mutex_regs: syscon@1905000 { +- compatible = "syscon"; +- reg = <0x0 0x01905000 0x0 0x8000>; +- }; +- +- tcsr: syscon@1937000 { +- compatible = "syscon"; +- reg = <0x0 0x01937000 0x0 0x21000>; +- }; +- +- blsp_dma: dma-controller@7884000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0x0 0x07884000 0x0 0x2b000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- }; +- +- blsp1_uart3: serial@78b1000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x0 0x078b1000 0x0 0x200>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- spi_0: spi@78b5000 { +- compatible = "qcom,spi-qup-v2.2.1"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x078b5000 0x0 0x600>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp_dma 12>, <&blsp_dma 13>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- spi_1: spi@78b6000 { +- compatible = "qcom,spi-qup-v2.2.1"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x078b6000 0x0 0x600>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp_dma 14>, <&blsp_dma 15>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- i2c_0: i2c@78b6000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x078b6000 0x0 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- clock-frequency = <400000>; +- dmas = <&blsp_dma 15>, <&blsp_dma 14>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */ +- compatible = "qcom,i2c-qup-v2.2.1"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x078b7000 0x0 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- clock-frequency = <400000>; +- dmas = <&blsp_dma 17>, <&blsp_dma 16>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- qpic_bam: dma-controller@7984000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0x0 0x07984000 0x0 0x1a000>; +- interrupts = ; +- clocks = <&gcc GCC_QPIC_CLK>, +- <&gcc GCC_QPIC_AHB_CLK>; +- clock-names = "iface_clk", "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- status = "disabled"; +- }; +- +- qpic_nand: nand@79b0000 { +- compatible = "qcom,ipq6018-nand"; +- reg = <0x0 0x079b0000 0x0 0x10000>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&gcc GCC_QPIC_CLK>, +- <&gcc GCC_QPIC_AHB_CLK>; +- clock-names = "core", "aon"; +- +- dmas = <&qpic_bam 0>, +- <&qpic_bam 1>, +- <&qpic_bam 2>; +- dma-names = "tx", "rx", "cmd"; +- pinctrl-0 = <&qpic_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- intc: interrupt-controller@b000000 { +- compatible = "qcom,msm-qgic2"; +- interrupt-controller; +- #interrupt-cells = <0x3>; +- reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ +- <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ +- <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ +- <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ +- interrupts = ; +- }; +- +- pcie_phy: phy@84000 { +- compatible = "qcom,ipq6018-qmp-pcie-phy"; +- reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */ +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clocks = <&gcc GCC_PCIE0_AUX_CLK>, +- <&gcc GCC_PCIE0_AHB_CLK>; +- clock-names = "aux", "cfg_ahb"; +- +- resets = <&gcc GCC_PCIE0_PHY_BCR>, +- <&gcc GCC_PCIE0PHY_PHY_BCR>; +- reset-names = "phy", +- "common"; +- +- pcie_phy0: lane@84200 { +- reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */ +- <0x0 0x84400 0x0 0x200>, /* Serdes Rx */ +- <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */ +- #phy-cells = <0>; +- +- clocks = <&gcc GCC_PCIE0_PIPE_CLK>; +- clock-names = "pipe0"; +- clock-output-names = "gcc_pcie0_pipe_clk_src"; +- #clock-cells = <0>; +- }; +- }; +- +- pcie0: pci@20000000 { +- compatible = "qcom,pcie-ipq6018"; +- reg = <0x0 0x20000000 0x0 0xf1d>, +- <0x0 0x20000f20 0x0 0xa8>, +- <0x0 0x20001000 0x0 0x1000>, +- <0x0 0x80000 0x0 0x4000>, +- <0x0 0x20100000 0x0 0x1000>; +- reg-names = "dbi", "elbi", "atu", "parf", "config"; +- +- device_type = "pci"; +- linux,pci-domain = <0>; +- bus-range = <0x00 0xff>; +- num-lanes = <1>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- phys = <&pcie_phy0>; +- phy-names = "pciephy"; +- +- ranges = <0x81000000 0 0x20200000 0 0x20200000 +- 0 0x10000>, /* downstream I/O */ +- <0x82000000 0 0x20220000 0 0x20220000 +- 0 0xfde0000>; /* non-prefetchable memory */ +- +- interrupts = ; +- interrupt-names = "msi"; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc 0 75 +- IRQ_TYPE_LEVEL_HIGH>, /* int_a */ +- <0 0 0 2 &intc 0 78 +- IRQ_TYPE_LEVEL_HIGH>, /* int_b */ +- <0 0 0 3 &intc 0 79 +- IRQ_TYPE_LEVEL_HIGH>, /* int_c */ +- <0 0 0 4 &intc 0 83 +- IRQ_TYPE_LEVEL_HIGH>; /* int_d */ +- +- clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, +- <&gcc GCC_PCIE0_AXI_M_CLK>, +- <&gcc GCC_PCIE0_AXI_S_CLK>, +- <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, +- <&gcc PCIE0_RCHNG_CLK>; +- clock-names = "iface", +- "axi_m", +- "axi_s", +- "axi_bridge", +- "rchng"; +- +- resets = <&gcc GCC_PCIE0_PIPE_ARES>, +- <&gcc GCC_PCIE0_SLEEP_ARES>, +- <&gcc GCC_PCIE0_CORE_STICKY_ARES>, +- <&gcc GCC_PCIE0_AXI_MASTER_ARES>, +- <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, +- <&gcc GCC_PCIE0_AHB_ARES>, +- <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, +- <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; +- reset-names = "pipe", +- "sleep", +- "sticky", +- "axi_m", +- "axi_s", +- "ahb", +- "axi_m_sticky", +- "axi_s_sticky"; +- +- status = "disabled"; +- }; +- +- watchdog@b017000 { +- compatible = "qcom,kpss-wdt"; +- interrupts = ; +- reg = <0x0 0x0b017000 0x0 0x40>; +- clocks = <&sleep_clk>; +- timeout-sec = <10>; +- }; +- +- apcs_glb: mailbox@b111000 { +- compatible = "qcom,ipq6018-apcs-apps-global"; +- reg = <0x0 0x0b111000 0x0 0x1000>; +- #clock-cells = <1>; +- clocks = <&a53pll>, <&xo>; +- clock-names = "pll", "xo"; +- #mbox-cells = <1>; +- }; +- +- a53pll: clock@b116000 { +- compatible = "qcom,ipq6018-a53pll"; +- reg = <0x0 0x0b116000 0x0 0x40>; +- #clock-cells = <0>; +- clocks = <&xo>; +- clock-names = "xo"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- timer@b120000 { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- compatible = "arm,armv7-timer-mem"; +- reg = <0x0 0x0b120000 0x0 0x1000>; +- clock-frequency = <19200000>; +- +- frame@b120000 { +- frame-number = <0>; +- interrupts = , +- ; +- reg = <0x0 0x0b121000 0x0 0x1000>, +- <0x0 0x0b122000 0x0 0x1000>; +- }; +- +- frame@b123000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0x0 0xb123000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@b124000 { +- frame-number = <2>; +- interrupts = ; +- reg = <0x0 0x0b124000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@b125000 { +- frame-number = <3>; +- interrupts = ; +- reg = <0x0 0x0b125000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@b126000 { +- frame-number = <4>; +- interrupts = ; +- reg = <0x0 0x0b126000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@b127000 { +- frame-number = <5>; +- interrupts = ; +- reg = <0x0 0x0b127000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@b128000 { +- frame-number = <6>; +- interrupts = ; +- reg = <0x0 0x0b128000 0x0 0x1000>; +- status = "disabled"; +- }; +- }; +- +- q6v5_wcss: remoteproc@cd00000 { +- compatible = "qcom,ipq6018-wcss-pil"; +- reg = <0x0 0x0cd00000 0x0 0x4040>, +- <0x0 0x004ab000 0x0 0x20>; +- reg-names = "qdsp6", +- "rmb"; +- interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, +- <&wcss_smp2p_in 0 0>, +- <&wcss_smp2p_in 1 0>, +- <&wcss_smp2p_in 2 0>, +- <&wcss_smp2p_in 3 0>; +- interrupt-names = "wdog", +- "fatal", +- "ready", +- "handover", +- "stop-ack"; +- +- resets = <&gcc GCC_WCSSAON_RESET>, +- <&gcc GCC_WCSS_BCR>, +- <&gcc GCC_WCSS_Q6_BCR>; +- +- reset-names = "wcss_aon_reset", +- "wcss_reset", +- "wcss_q6_reset"; +- +- clocks = <&gcc GCC_PRNG_AHB_CLK>; +- clock-names = "prng"; +- +- qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>; +- +- qcom,smem-states = <&wcss_smp2p_out 0>, +- <&wcss_smp2p_out 1>; +- qcom,smem-state-names = "shutdown", +- "stop"; +- +- memory-region = <&q6_region>; +- +- glink-edge { +- interrupts = ; +- qcom,remote-pid = <1>; +- mboxes = <&apcs_glb 8>; +- +- qrtr_requests { +- qcom,glink-channels = "IPCRTR"; +- }; +- }; +- }; +- +- qusb_phy_1: qusb@59000 { +- compatible = "qcom,ipq6018-qusb2-phy"; +- reg = <0x0 0x059000 0x0 0x180>; +- #phy-cells = <0>; +- +- clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, +- <&xo>; +- clock-names = "cfg_ahb", "ref"; +- +- resets = <&gcc GCC_QUSB2_1_PHY_BCR>; +- status = "disabled"; +- }; +- +- usb2: usb2@7000000 { +- compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; +- reg = <0x0 0x070F8800 0x0 0x400>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- clocks = <&gcc GCC_USB1_MASTER_CLK>, +- <&gcc GCC_USB1_SLEEP_CLK>, +- <&gcc GCC_USB1_MOCK_UTMI_CLK>; +- clock-names = "master", +- "sleep", +- "mock_utmi"; +- +- assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, +- <&gcc GCC_USB1_MOCK_UTMI_CLK>; +- assigned-clock-rates = <133330000>, +- <24000000>; +- resets = <&gcc GCC_USB1_BCR>; +- status = "disabled"; +- +- dwc_1: usb@7000000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0x7000000 0x0 0xcd00>; +- interrupts = ; +- phys = <&qusb_phy_1>; +- phy-names = "usb2-phy"; +- tx-fifo-resize; +- snps,is-utmi-l1-suspend; +- snps,hird-threshold = /bits/ 8 <0x0>; +- snps,dis_u2_susphy_quirk; +- snps,dis_u3_susphy_quirk; +- dr_mode = "host"; +- }; +- }; +- +- }; +- +- wcss: wcss-smp2p { +- compatible = "qcom,smp2p"; +- qcom,smem = <435>, <428>; +- +- interrupt-parent = <&intc>; +- interrupts = ; +- +- mboxes = <&apcs_glb 9>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <1>; +- +- wcss_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- wcss_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- rpm-glink { +- compatible = "qcom,glink-rpm"; +- interrupts = ; +- qcom,rpm-msg-ram = <&rpm_msg_ram>; +- mboxes = <&apcs_glb 0>; +- +- rpm_requests: glink-channel { +- compatible = "qcom,rpm-ipq6018"; +- qcom,glink-channels = "rpm_requests"; +- +- regulators { +- compatible = "qcom,rpm-mp5496-regulators"; +- +- ipq6018_s2: s2 { +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1062500>; +- regulator-always-on; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/ipq8074-hk01.dts b/scripts/dtc/include-prefixes/arm64/qcom/ipq8074-hk01.dts +deleted file mode 100644 +index cc08dc4eb56a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/ipq8074-hk01.dts ++++ /dev/null +@@ -1,112 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/dts-v1/; +-/* Copyright (c) 2017, The Linux Foundation. All rights reserved. +- */ +-#include "ipq8074.dtsi" +- +-/ { +- #address-cells = <0x2>; +- #size-cells = <0x2>; +- model = "Qualcomm Technologies, Inc. IPQ8074-HK01"; +- compatible = "qcom,ipq8074-hk01", "qcom,ipq8074"; +- interrupt-parent = <&intc>; +- +- aliases { +- serial0 = &blsp1_uart5; +- serial1 = &blsp1_uart3; +- }; +- +- chosen { +- stdout-path = "serial0"; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x0 0x40000000 0x0 0x20000000>; +- }; +-}; +- +-&blsp1_i2c2 { +- status = "okay"; +-}; +- +-&blsp1_spi1 { +- status = "okay"; +- +- m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- }; +-}; +- +-&blsp1_uart3 { +- status = "okay"; +-}; +- +-&blsp1_uart5 { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +- perst-gpio = <&tlmm 61 0x1>; +-}; +- +-&pcie1 { +- status = "okay"; +- perst-gpio = <&tlmm 58 0x1>; +-}; +- +-&pcie_phy0 { +- status = "okay"; +-}; +- +-&pcie_phy1 { +- status = "okay"; +-}; +- +-&qpic_bam { +- status = "okay"; +-}; +- +-&qpic_nand { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- nand-bus-width = <8>; +- }; +-}; +- +-&sdhc_1 { +- status = "okay"; +-}; +- +-&qusb_phy_0 { +- status = "okay"; +-}; +- +-&qusb_phy_1 { +- status = "okay"; +-}; +- +-&ssphy_0 { +- status = "okay"; +-}; +- +-&ssphy_1 { +- status = "okay"; +-}; +- +-&usb_0 { +- status = "okay"; +-}; +- +-&usb_1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/ipq8074-hk10-c1.dts b/scripts/dtc/include-prefixes/arm64/qcom/ipq8074-hk10-c1.dts +deleted file mode 100644 +index 2bfcf42aeabc..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/ipq8074-hk10-c1.dts ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* Copyright (c) 2020 The Linux Foundation. All rights reserved. +- */ +-/dts-v1/; +- +-#include "ipq8074-hk10.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. IPQ8074/AP-HK10-C1"; +- compatible = "qcom,ipq8074-hk10-c1", "qcom,ipq8074"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/ipq8074-hk10-c2.dts b/scripts/dtc/include-prefixes/arm64/qcom/ipq8074-hk10-c2.dts +deleted file mode 100644 +index 7da39f1d979b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/ipq8074-hk10-c2.dts ++++ /dev/null +@@ -1,10 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/dts-v1/; +-/* Copyright (c) 2020 The Linux Foundation. All rights reserved. +- */ +-#include "ipq8074-hk10.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. IPQ8074/AP-HK10-C2"; +- compatible = "qcom,ipq8074-hk10-c2", "qcom,ipq8074"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/ipq8074-hk10.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/ipq8074-hk10.dtsi +deleted file mode 100644 +index 07e670829676..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/ipq8074-hk10.dtsi ++++ /dev/null +@@ -1,76 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +-/dts-v1/; +- +-#include "ipq8074.dtsi" +- +-/ { +- #address-cells = <0x2>; +- #size-cells = <0x2>; +- +- interrupt-parent = <&intc>; +- +- aliases { +- serial0 = &blsp1_uart5; +- }; +- +- chosen { +- stdout-path = "serial0"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x40000000 0x0 0x20000000>; +- }; +-}; +- +-&blsp1_spi1 { +- status = "ok"; +- +- m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- }; +-}; +- +-&blsp1_uart5 { +- status = "ok"; +-}; +- +-&pcie0 { +- status = "ok"; +- perst-gpio = <&tlmm 58 0x1>; +-}; +- +-&pcie1 { +- status = "ok"; +- perst-gpio = <&tlmm 61 0x1>; +-}; +- +-&pcie_phy0 { +- status = "ok"; +-}; +- +-&pcie_phy1 { +- status = "ok"; +-}; +- +-&qpic_bam { +- status = "ok"; +-}; +- +-&qpic_nand { +- status = "ok"; +- +- nand@0 { +- reg = <0>; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- nand-bus-width = <8>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/ipq8074.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/ipq8074.dtsi +deleted file mode 100644 +index 97f99663c132..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/ipq8074.dtsi ++++ /dev/null +@@ -1,745 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2017, The Linux Foundation. All rights reserved. +- */ +- +-#include +-#include +- +-/ { +- model = "Qualcomm Technologies, Inc. IPQ8074"; +- compatible = "qcom,ipq8074"; +- +- clocks { +- sleep_clk: sleep_clk { +- compatible = "fixed-clock"; +- clock-frequency = <32000>; +- #clock-cells = <0>; +- }; +- +- xo: xo { +- compatible = "fixed-clock"; +- clock-frequency = <19200000>; +- #clock-cells = <0>; +- }; +- }; +- +- cpus { +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- +- CPU0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0>; +- next-level-cache = <&L2_0>; +- enable-method = "psci"; +- }; +- +- CPU1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x1>; +- next-level-cache = <&L2_0>; +- }; +- +- CPU2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x2>; +- next-level-cache = <&L2_0>; +- }; +- +- CPU3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x3>; +- next-level-cache = <&L2_0>; +- }; +- +- L2_0: l2-cache { +- compatible = "cache"; +- cache-level = <0x2>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- firmware { +- scm { +- compatible = "qcom,scm-ipq8074", "qcom,scm"; +- }; +- }; +- +- soc: soc { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- ranges = <0 0 0 0xffffffff>; +- compatible = "simple-bus"; +- +- ssphy_1: phy@58000 { +- compatible = "qcom,ipq8074-qmp-usb3-phy"; +- reg = <0x00058000 0x1c4>; +- #clock-cells = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clocks = <&gcc GCC_USB1_AUX_CLK>, +- <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, +- <&xo>; +- clock-names = "aux", "cfg_ahb", "ref"; +- +- resets = <&gcc GCC_USB1_PHY_BCR>, +- <&gcc GCC_USB3PHY_1_PHY_BCR>; +- reset-names = "phy","common"; +- status = "disabled"; +- +- usb1_ssphy: lane@58200 { +- reg = <0x00058200 0x130>, /* Tx */ +- <0x00058400 0x200>, /* Rx */ +- <0x00058800 0x1f8>, /* PCS */ +- <0x00058600 0x044>; /* PCS misc*/ +- #phy-cells = <0>; +- clocks = <&gcc GCC_USB1_PIPE_CLK>; +- clock-names = "pipe0"; +- clock-output-names = "gcc_usb1_pipe_clk_src"; +- }; +- }; +- +- qusb_phy_1: phy@59000 { +- compatible = "qcom,ipq8074-qusb2-phy"; +- reg = <0x00059000 0x180>; +- #phy-cells = <0>; +- +- clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, +- <&xo>; +- clock-names = "cfg_ahb", "ref"; +- +- resets = <&gcc GCC_QUSB2_1_PHY_BCR>; +- status = "disabled"; +- }; +- +- ssphy_0: phy@78000 { +- compatible = "qcom,ipq8074-qmp-usb3-phy"; +- reg = <0x00078000 0x1c4>; +- #clock-cells = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clocks = <&gcc GCC_USB0_AUX_CLK>, +- <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, +- <&xo>; +- clock-names = "aux", "cfg_ahb", "ref"; +- +- resets = <&gcc GCC_USB0_PHY_BCR>, +- <&gcc GCC_USB3PHY_0_PHY_BCR>; +- reset-names = "phy","common"; +- status = "disabled"; +- +- usb0_ssphy: lane@78200 { +- reg = <0x00078200 0x130>, /* Tx */ +- <0x00078400 0x200>, /* Rx */ +- <0x00078800 0x1f8>, /* PCS */ +- <0x00078600 0x044>; /* PCS misc*/ +- #phy-cells = <0>; +- clocks = <&gcc GCC_USB0_PIPE_CLK>; +- clock-names = "pipe0"; +- clock-output-names = "gcc_usb0_pipe_clk_src"; +- }; +- }; +- +- qusb_phy_0: phy@79000 { +- compatible = "qcom,ipq8074-qusb2-phy"; +- reg = <0x00079000 0x180>; +- #phy-cells = <0>; +- +- clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, +- <&xo>; +- clock-names = "cfg_ahb", "ref"; +- +- resets = <&gcc GCC_QUSB2_0_PHY_BCR>; +- status = "disabled"; +- }; +- +- pcie_phy0: phy@86000 { +- compatible = "qcom,ipq8074-qmp-pcie-phy"; +- reg = <0x00086000 0x1000>; +- #phy-cells = <0>; +- clocks = <&gcc GCC_PCIE0_PIPE_CLK>; +- clock-names = "pipe_clk"; +- clock-output-names = "pcie20_phy0_pipe_clk"; +- +- resets = <&gcc GCC_PCIE0_PHY_BCR>, +- <&gcc GCC_PCIE0PHY_PHY_BCR>; +- reset-names = "phy", +- "common"; +- status = "disabled"; +- }; +- +- pcie_phy1: phy@8e000 { +- compatible = "qcom,ipq8074-qmp-pcie-phy"; +- reg = <0x0008e000 0x1000>; +- #phy-cells = <0>; +- clocks = <&gcc GCC_PCIE1_PIPE_CLK>; +- clock-names = "pipe_clk"; +- clock-output-names = "pcie20_phy1_pipe_clk"; +- +- resets = <&gcc GCC_PCIE1_PHY_BCR>, +- <&gcc GCC_PCIE1PHY_PHY_BCR>; +- reset-names = "phy", +- "common"; +- status = "disabled"; +- }; +- +- prng: rng@e3000 { +- compatible = "qcom,prng-ee"; +- reg = <0x000e3000 0x1000>; +- clocks = <&gcc GCC_PRNG_AHB_CLK>; +- clock-names = "core"; +- status = "disabled"; +- }; +- +- cryptobam: dma@704000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0x00704000 0x20000>; +- interrupts = ; +- clocks = <&gcc GCC_CRYPTO_AHB_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <1>; +- qcom,controlled-remotely; +- status = "disabled"; +- }; +- +- crypto: crypto@73a000 { +- compatible = "qcom,crypto-v5.1"; +- reg = <0x0073a000 0x6000>; +- clocks = <&gcc GCC_CRYPTO_AHB_CLK>, +- <&gcc GCC_CRYPTO_AXI_CLK>, +- <&gcc GCC_CRYPTO_CLK>; +- clock-names = "iface", "bus", "core"; +- dmas = <&cryptobam 2>, <&cryptobam 3>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- tlmm: pinctrl@1000000 { +- compatible = "qcom,ipq8074-pinctrl"; +- reg = <0x01000000 0x300000>; +- interrupts = ; +- gpio-controller; +- gpio-ranges = <&tlmm 0 0 70>; +- #gpio-cells = <0x2>; +- interrupt-controller; +- #interrupt-cells = <0x2>; +- +- serial_4_pins: serial4-pinmux { +- pins = "gpio23", "gpio24"; +- function = "blsp4_uart1"; +- drive-strength = <8>; +- bias-disable; +- }; +- +- i2c_0_pins: i2c-0-pinmux { +- pins = "gpio42", "gpio43"; +- function = "blsp1_i2c"; +- drive-strength = <8>; +- bias-disable; +- }; +- +- spi_0_pins: spi-0-pins { +- pins = "gpio38", "gpio39", "gpio40", "gpio41"; +- function = "blsp0_spi"; +- drive-strength = <8>; +- bias-disable; +- }; +- +- hsuart_pins: hsuart-pins { +- pins = "gpio46", "gpio47", "gpio48", "gpio49"; +- function = "blsp2_uart"; +- drive-strength = <8>; +- bias-disable; +- }; +- +- qpic_pins: qpic-pins { +- pins = "gpio1", "gpio3", "gpio4", +- "gpio5", "gpio6", "gpio7", +- "gpio8", "gpio10", "gpio11", +- "gpio12", "gpio13", "gpio14", +- "gpio15", "gpio16", "gpio17"; +- function = "qpic"; +- drive-strength = <8>; +- bias-disable; +- }; +- }; +- +- gcc: gcc@1800000 { +- compatible = "qcom,gcc-ipq8074"; +- reg = <0x01800000 0x80000>; +- #clock-cells = <0x1>; +- #reset-cells = <0x1>; +- }; +- +- sdhc_1: sdhci@7824900 { +- compatible = "qcom,sdhci-msm-v4"; +- reg = <0x7824900 0x500>, <0x7824000 0x800>; +- reg-names = "hc_mem", "core_mem"; +- +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- +- clocks = <&xo>, +- <&gcc GCC_SDCC1_AHB_CLK>, +- <&gcc GCC_SDCC1_APPS_CLK>; +- clock-names = "xo", "iface", "core"; +- max-frequency = <384000000>; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- bus-width = <8>; +- +- status = "disabled"; +- }; +- +- blsp_dma: dma-controller@7884000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0x07884000 0x2b000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- }; +- +- blsp1_uart1: serial@78af000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x078af000 0x200>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- blsp1_uart3: serial@78b1000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x078b1000 0x200>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp_dma 4>, +- <&blsp_dma 5>; +- dma-names = "tx", "rx"; +- pinctrl-0 = <&hsuart_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- blsp1_uart5: serial@78b3000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x078b3000 0x200>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- pinctrl-0 = <&serial_4_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- blsp1_spi1: spi@78b5000 { +- compatible = "qcom,spi-qup-v2.2.1"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x078b5000 0x600>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp_dma 12>, <&blsp_dma 13>; +- dma-names = "tx", "rx"; +- pinctrl-0 = <&spi_0_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- blsp1_i2c2: i2c@78b6000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x078b6000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- clock-frequency = <400000>; +- dmas = <&blsp_dma 15>, <&blsp_dma 14>; +- dma-names = "rx", "tx"; +- pinctrl-0 = <&i2c_0_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- blsp1_i2c3: i2c@78b7000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x078b7000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- clock-frequency = <100000>; +- dmas = <&blsp_dma 17>, <&blsp_dma 16>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- blsp1_i2c6: i2c@78ba000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x078ba000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- clock-frequency = <100000>; +- dmas = <&blsp_dma 23>, <&blsp_dma 22>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- qpic_bam: dma-controller@7984000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0x07984000 0x1a000>; +- interrupts = ; +- clocks = <&gcc GCC_QPIC_AHB_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- status = "disabled"; +- }; +- +- qpic_nand: nand@79b0000 { +- compatible = "qcom,ipq8074-nand"; +- reg = <0x079b0000 0x10000>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&gcc GCC_QPIC_CLK>, +- <&gcc GCC_QPIC_AHB_CLK>; +- clock-names = "core", "aon"; +- +- dmas = <&qpic_bam 0>, +- <&qpic_bam 1>, +- <&qpic_bam 2>; +- dma-names = "tx", "rx", "cmd"; +- pinctrl-0 = <&qpic_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- usb_0: usb@8af8800 { +- compatible = "qcom,dwc3"; +- reg = <0x08af8800 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, +- <&gcc GCC_USB0_MASTER_CLK>, +- <&gcc GCC_USB0_SLEEP_CLK>, +- <&gcc GCC_USB0_MOCK_UTMI_CLK>; +- clock-names = "sys_noc_axi", +- "master", +- "sleep", +- "mock_utmi"; +- +- assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, +- <&gcc GCC_USB0_MASTER_CLK>, +- <&gcc GCC_USB0_MOCK_UTMI_CLK>; +- assigned-clock-rates = <133330000>, +- <133330000>, +- <19200000>; +- +- resets = <&gcc GCC_USB0_BCR>; +- status = "disabled"; +- +- dwc_0: dwc3@8a00000 { +- compatible = "snps,dwc3"; +- reg = <0x8a00000 0xcd00>; +- interrupts = ; +- phys = <&qusb_phy_0>, <&usb0_ssphy>; +- phy-names = "usb2-phy", "usb3-phy"; +- snps,is-utmi-l1-suspend; +- snps,hird-threshold = /bits/ 8 <0x0>; +- snps,dis_u2_susphy_quirk; +- snps,dis_u3_susphy_quirk; +- dr_mode = "host"; +- }; +- }; +- +- usb_1: usb@8cf8800 { +- compatible = "qcom,dwc3"; +- reg = <0x08cf8800 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, +- <&gcc GCC_USB1_MASTER_CLK>, +- <&gcc GCC_USB1_SLEEP_CLK>, +- <&gcc GCC_USB1_MOCK_UTMI_CLK>; +- clock-names = "sys_noc_axi", +- "master", +- "sleep", +- "mock_utmi"; +- +- assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, +- <&gcc GCC_USB1_MASTER_CLK>, +- <&gcc GCC_USB1_MOCK_UTMI_CLK>; +- assigned-clock-rates = <133330000>, +- <133330000>, +- <19200000>; +- +- resets = <&gcc GCC_USB1_BCR>; +- status = "disabled"; +- +- dwc_1: dwc3@8c00000 { +- compatible = "snps,dwc3"; +- reg = <0x8c00000 0xcd00>; +- interrupts = ; +- phys = <&qusb_phy_1>, <&usb1_ssphy>; +- phy-names = "usb2-phy", "usb3-phy"; +- snps,is-utmi-l1-suspend; +- snps,hird-threshold = /bits/ 8 <0x0>; +- snps,dis_u2_susphy_quirk; +- snps,dis_u3_susphy_quirk; +- dr_mode = "host"; +- }; +- }; +- +- intc: interrupt-controller@b000000 { +- compatible = "qcom,msm-qgic2"; +- interrupt-controller; +- #interrupt-cells = <0x3>; +- reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- watchdog: watchdog@b017000 { +- compatible = "qcom,kpss-wdt"; +- reg = <0xb017000 0x1000>; +- interrupts = ; +- clocks = <&sleep_clk>; +- timeout-sec = <30>; +- }; +- +- timer@b120000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "arm,armv7-timer-mem"; +- reg = <0x0b120000 0x1000>; +- clock-frequency = <19200000>; +- +- frame@b120000 { +- frame-number = <0>; +- interrupts = , +- ; +- reg = <0x0b121000 0x1000>, +- <0x0b122000 0x1000>; +- }; +- +- frame@b123000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0x0b123000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b124000 { +- frame-number = <2>; +- interrupts = ; +- reg = <0x0b124000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b125000 { +- frame-number = <3>; +- interrupts = ; +- reg = <0x0b125000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b126000 { +- frame-number = <4>; +- interrupts = ; +- reg = <0x0b126000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b127000 { +- frame-number = <5>; +- interrupts = ; +- reg = <0x0b127000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b128000 { +- frame-number = <6>; +- interrupts = ; +- reg = <0x0b128000 0x1000>; +- status = "disabled"; +- }; +- }; +- +- pcie1: pci@10000000 { +- compatible = "qcom,pcie-ipq8074"; +- reg = <0x10000000 0xf1d>, +- <0x10000f20 0xa8>, +- <0x00088000 0x2000>, +- <0x10100000 0x1000>; +- reg-names = "dbi", "elbi", "parf", "config"; +- device_type = "pci"; +- linux,pci-domain = <1>; +- bus-range = <0x00 0xff>; +- num-lanes = <1>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- phys = <&pcie_phy1>; +- phy-names = "pciephy"; +- +- ranges = <0x81000000 0 0x10200000 0x10200000 +- 0 0x100000 /* downstream I/O */ +- 0x82000000 0 0x10300000 0x10300000 +- 0 0xd00000>; /* non-prefetchable memory */ +- +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc 0 142 +- IRQ_TYPE_LEVEL_HIGH>, /* int_a */ +- <0 0 0 2 &intc 0 143 +- IRQ_TYPE_LEVEL_HIGH>, /* int_b */ +- <0 0 0 3 &intc 0 144 +- IRQ_TYPE_LEVEL_HIGH>, /* int_c */ +- <0 0 0 4 &intc 0 145 +- IRQ_TYPE_LEVEL_HIGH>; /* int_d */ +- +- clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, +- <&gcc GCC_PCIE1_AXI_M_CLK>, +- <&gcc GCC_PCIE1_AXI_S_CLK>, +- <&gcc GCC_PCIE1_AHB_CLK>, +- <&gcc GCC_PCIE1_AUX_CLK>; +- clock-names = "iface", +- "axi_m", +- "axi_s", +- "ahb", +- "aux"; +- resets = <&gcc GCC_PCIE1_PIPE_ARES>, +- <&gcc GCC_PCIE1_SLEEP_ARES>, +- <&gcc GCC_PCIE1_CORE_STICKY_ARES>, +- <&gcc GCC_PCIE1_AXI_MASTER_ARES>, +- <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, +- <&gcc GCC_PCIE1_AHB_ARES>, +- <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; +- reset-names = "pipe", +- "sleep", +- "sticky", +- "axi_m", +- "axi_s", +- "ahb", +- "axi_m_sticky"; +- status = "disabled"; +- }; +- +- pcie0: pci@20000000 { +- compatible = "qcom,pcie-ipq8074"; +- reg = <0x20000000 0xf1d>, +- <0x20000f20 0xa8>, +- <0x00080000 0x2000>, +- <0x20100000 0x1000>; +- reg-names = "dbi", "elbi", "parf", "config"; +- device_type = "pci"; +- linux,pci-domain = <0>; +- bus-range = <0x00 0xff>; +- num-lanes = <1>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- phys = <&pcie_phy0>; +- phy-names = "pciephy"; +- +- ranges = <0x81000000 0 0x20200000 0x20200000 +- 0 0x100000 /* downstream I/O */ +- 0x82000000 0 0x20300000 0x20300000 +- 0 0xd00000>; /* non-prefetchable memory */ +- +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc 0 75 +- IRQ_TYPE_LEVEL_HIGH>, /* int_a */ +- <0 0 0 2 &intc 0 78 +- IRQ_TYPE_LEVEL_HIGH>, /* int_b */ +- <0 0 0 3 &intc 0 79 +- IRQ_TYPE_LEVEL_HIGH>, /* int_c */ +- <0 0 0 4 &intc 0 83 +- IRQ_TYPE_LEVEL_HIGH>; /* int_d */ +- +- clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, +- <&gcc GCC_PCIE0_AXI_M_CLK>, +- <&gcc GCC_PCIE0_AXI_S_CLK>, +- <&gcc GCC_PCIE0_AHB_CLK>, +- <&gcc GCC_PCIE0_AUX_CLK>; +- +- clock-names = "iface", +- "axi_m", +- "axi_s", +- "ahb", +- "aux"; +- resets = <&gcc GCC_PCIE0_PIPE_ARES>, +- <&gcc GCC_PCIE0_SLEEP_ARES>, +- <&gcc GCC_PCIE0_CORE_STICKY_ARES>, +- <&gcc GCC_PCIE0_AXI_MASTER_ARES>, +- <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, +- <&gcc GCC_PCIE0_AHB_ARES>, +- <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; +- reset-names = "pipe", +- "sleep", +- "sticky", +- "axi_m", +- "axi_s", +- "ahb", +- "axi_m_sticky"; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-alcatel-idol347.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8916-alcatel-idol347.dts +deleted file mode 100644 +index 670bd1bebd73..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-alcatel-idol347.dts ++++ /dev/null +@@ -1,317 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +- +-/dts-v1/; +- +-#include "msm8916-pm8916.dtsi" +-#include +-#include +- +-/ { +- model = "Alcatel OneTouch Idol 3 (4.7)"; +- compatible = "alcatel,idol347", "qcom,msm8916"; +- +- aliases { +- serial0 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_default>; +- +- label = "GPIO Buttons"; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- usb_id: usb-id { +- compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&msmgpio 69 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_id_default>; +- }; +-}; +- +-&blsp1_uart2 { +- status = "okay"; +-}; +- +-&blsp_i2c4 { +- status = "okay"; +- +- touchscreen@26 { +- compatible = "mstar,msg2638"; +- reg = <0x26>; +- interrupt-parent = <&msmgpio>; +- interrupts = <13 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&msmgpio 100 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ts_int_reset_default>; +- vdd-supply = <&pm8916_l17>; +- vddio-supply = <&pm8916_l5>; +- touchscreen-size-x = <2048>; +- touchscreen-size-y = <2048>; +- }; +-}; +- +-&blsp_i2c5 { +- status = "okay"; +- +- magnetometer@c { +- compatible = "asahi-kasei,ak09911"; +- reg = <0x0c>; +- vdd-supply = <&pm8916_l17>; +- vid-supply = <&pm8916_l6>; +- reset-gpios = <&msmgpio 8 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mag_reset_default>; +- mount-matrix = "0", "1", "0", +- "-1", "0", "0", +- "0", "0", "1"; +- }; +- +- accelerometer@f { +- compatible = "kionix,kxtj21009"; +- reg = <0x0f>; +- vdd-supply = <&pm8916_l17>; +- vddio-supply = <&pm8916_l6>; +- interrupt-parent = <&msmgpio>; +- interrupts = <31 IRQ_TYPE_EDGE_RISING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&accel_int_default>; +- mount-matrix = "-1", "0", "0", +- "0", "1", "0", +- "0", "0", "-1"; +- }; +- +- proximity@48 { +- compatible = "sensortek,stk3310"; +- reg = <0x48>; +- interrupt-parent = <&msmgpio>; +- interrupts = <12 IRQ_TYPE_EDGE_FALLING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&proximity_int_default>; +- }; +- +- gyroscope@68 { +- compatible = "bosch,bmg160"; +- reg = <0x68>; +- vdd-supply = <&pm8916_l17>; +- vddio-supply = <&pm8916_l6>; +- interrupt-parent = <&msmgpio>; +- interrupts = <97 IRQ_TYPE_EDGE_RISING>, +- <98 IRQ_TYPE_EDGE_RISING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gyro_int_default>; +- }; +-}; +- +-&pm8916_resin { +- status = "okay"; +- linux,code = ; +-}; +- +-&pm8916_vib { +- status = "okay"; +-}; +- +-&pronto { +- status = "okay"; +-}; +- +-&sdhc_1 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; +- pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +-}; +- +-&sdhc_2 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; +- pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; +- +- cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; +-}; +- +-&usb { +- status = "okay"; +- extcon = <&usb_id>, <&usb_id>; +-}; +- +-&usb_hs_phy { +- extcon = <&usb_id>; +-}; +- +-&smd_rpm_regulators { +- vdd_l1_l2_l3-supply = <&pm8916_s3>; +- vdd_l4_l5_l6-supply = <&pm8916_s4>; +- vdd_l7-supply = <&pm8916_s4>; +- +- s3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1300000>; +- }; +- +- s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2100000>; +- }; +- +- l1 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- l4 { +- regulator-min-microvolt = <2050000>; +- regulator-max-microvolt = <2050000>; +- }; +- +- l5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l8 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2900000>; +- }; +- +- l9 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l10 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- l11 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- regulator-allow-set-load; +- regulator-system-load = <200000>; +- }; +- +- l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- l13 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- }; +- +- l14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l16 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l17 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- l18 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +-}; +- +-&msmgpio { +- accel_int_default: accel-int-default { +- pins = "gpio31"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- gpio_keys_default: gpio-keys-default { +- pins = "gpio107"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- gyro_int_default: gyro-int-default { +- pins = "gpio97", "gpio98"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- mag_reset_default: mag-reset-default { +- pins = "gpio8"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- proximity_int_default: proximity-int-default { +- pins = "gpio12"; +- function = "gpio"; +- +- drive-strength = <6>; +- bias-pull-up; +- }; +- +- ts_int_reset_default: ts-int-reset-default { +- pins = "gpio13", "gpio100"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- usb_id_default: usb-id-default { +- pins = "gpio69"; +- function = "gpio"; +- +- drive-strength = <8>; +- bias-pull-up; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-asus-z00l.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8916-asus-z00l.dts +deleted file mode 100644 +index cee451e59385..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-asus-z00l.dts ++++ /dev/null +@@ -1,195 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +- +-/dts-v1/; +- +-#include "msm8916-pm8916.dtsi" +-#include +- +-/ { +- model = "Asus Zenfone 2 Laser"; +- compatible = "asus,z00l", "qcom,msm8916"; +- +- aliases { +- serial0 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_default>; +- +- label = "GPIO Buttons"; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <15>; +- }; +- +- volume-down { +- label = "Volume Down"; +- gpios = <&msmgpio 117 GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <15>; +- }; +- }; +- +- usb_id: usb-id { +- compatible = "linux,extcon-usb-gpio"; +- id-gpios = <&msmgpio 110 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_id_default>; +- }; +-}; +- +-&blsp1_uart2 { +- status = "okay"; +-}; +- +-&pronto { +- status = "okay"; +-}; +- +-&sdhc_1 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; +- pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +-}; +- +-&usb { +- status = "okay"; +- extcon = <&usb_id>, <&usb_id>; +-}; +- +-&usb_hs_phy { +- extcon = <&usb_id>; +-}; +- +-&smd_rpm_regulators { +- vdd_l1_l2_l3-supply = <&pm8916_s3>; +- vdd_l4_l5_l6-supply = <&pm8916_s4>; +- vdd_l7-supply = <&pm8916_s4>; +- +- s3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1300000>; +- }; +- +- s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2100000>; +- }; +- +- l1 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- l4 { +- regulator-min-microvolt = <2050000>; +- regulator-max-microvolt = <2050000>; +- }; +- +- l5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l8 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2900000>; +- }; +- +- l9 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l10 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- l11 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- regulator-allow-set-load; +- regulator-system-load = <200000>; +- }; +- +- l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- l13 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- }; +- +- l14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l16 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l17 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- l18 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +-}; +- +-&msmgpio { +- gpio_keys_default: gpio-keys-default { +- pins = "gpio107", "gpio117"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- usb_id_default: usb-id-default { +- pins = "gpio110"; +- function = "gpio"; +- +- drive-strength = <8>; +- bias-pull-up; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-huawei-g7.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8916-huawei-g7.dts +deleted file mode 100644 +index e0075b574190..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-huawei-g7.dts ++++ /dev/null +@@ -1,454 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-// Copyright (C) 2021 Stephan Gerhold +- +-/dts-v1/; +- +-#include "msm8916-pm8916.dtsi" +-#include +-#include +-#include +-#include +- +-/* +- * Note: The original firmware from Huawei can only boot 32-bit kernels. +- * To boot arm64 kernels it is necessary to flash 64-bit TZ/HYP firmware +- * with EDL, e.g. taken from the DragonBoard 410c. This works because Huawei +- * forgot to set up (firmware) secure boot for some reason. +- * +- * Also note that Huawei no longer provides bootloader unlock codes. +- * This can be bypassed by patching the bootloader from a custom HYP firmware, +- * making it think the bootloader is unlocked. +- * +- * See: https://wiki.postmarketos.org/wiki/Huawei_Ascend_G7_(huawei-g7) +- */ +- +-/ { +- model = "Huawei Ascend G7"; +- compatible = "huawei,g7", "qcom,msm8916"; +- +- aliases { +- serial0 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_default>; +- +- label = "GPIO Buttons"; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_leds_default>; +- +- led-0 { +- gpios = <&msmgpio 8 GPIO_ACTIVE_HIGH>; +- color = ; +- default-state = "off"; +- function = LED_FUNCTION_INDICATOR; +- }; +- +- led-1 { +- gpios = <&msmgpio 9 GPIO_ACTIVE_HIGH>; +- color = ; +- default-state = "off"; +- function = LED_FUNCTION_INDICATOR; +- }; +- +- led-2 { +- gpios = <&msmgpio 10 GPIO_ACTIVE_HIGH>; +- color = ; +- default-state = "off"; +- function = LED_FUNCTION_INDICATOR; +- }; +- }; +- +- usb_id: usb-id { +- compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&msmgpio 117 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_id_default>; +- }; +-}; +- +-&blsp_i2c2 { +- status = "okay"; +- +- magnetometer@c { +- compatible = "asahi-kasei,ak09911"; +- reg = <0x0c>; +- +- vdd-supply = <&pm8916_l17>; +- vid-supply = <&pm8916_l6>; +- +- reset-gpios = <&msmgpio 36 GPIO_ACTIVE_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&mag_reset_default>; +- }; +- +- accelerometer@1e { +- compatible = "kionix,kx023-1025"; +- reg = <0x1e>; +- +- interrupt-parent = <&msmgpio>; +- interrupts = <115 IRQ_TYPE_EDGE_RISING>; +- +- vdd-supply = <&pm8916_l17>; +- vddio-supply = <&pm8916_l6>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&accel_irq_default>; +- +- mount-matrix = "-1", "0", "0", +- "0", "1", "0", +- "0", "0", "1"; +- }; +- +- proximity@39 { +- compatible = "avago,apds9930"; +- reg = <0x39>; +- +- interrupt-parent = <&msmgpio>; +- interrupts = <113 IRQ_TYPE_EDGE_FALLING>; +- +- vdd-supply = <&pm8916_l17>; +- vddio-supply = <&pm8916_l6>; +- +- led-max-microamp = <100000>; +- amstaos,proximity-diodes = <1>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&prox_irq_default>; +- }; +- +- regulator@3e { +- compatible = "ti,tps65132"; +- reg = <0x3e>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <®_lcd_en_default>; +- +- reg_lcd_pos: outp { +- regulator-name = "outp"; +- regulator-min-microvolt = <5400000>; +- regulator-max-microvolt = <5400000>; +- enable-gpios = <&msmgpio 97 GPIO_ACTIVE_HIGH>; +- regulator-active-discharge = <1>; +- }; +- +- reg_lcd_neg: outn { +- regulator-name = "outn"; +- regulator-min-microvolt = <5400000>; +- regulator-max-microvolt = <5400000>; +- enable-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; +- regulator-active-discharge = <1>; +- }; +- }; +-}; +- +-&blsp_i2c5 { +- status = "okay"; +- +- rmi4@70 { +- compatible = "syna,rmi4-i2c"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- interrupt-parent = <&msmgpio>; +- interrupts = <13 IRQ_TYPE_EDGE_FALLING>; +- +- vdd-supply = <&pm8916_l17>; +- vio-supply = <&pm8916_l16>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&ts_irq_default>; +- +- syna,startup-delay-ms = <100>; +- +- rmi4-f01@1 { +- reg = <0x1>; +- syna,nosleep-mode = <1>; /* Allow sleeping */ +- }; +- +- rmi4-f11@11 { +- reg = <0x11>; +- syna,sensor-type = <1>; /* Touchscreen */ +- }; +- }; +-}; +- +-&blsp_i2c6 { +- status = "okay"; +- +- nfc@28 { +- compatible = "nxp,pn547", "nxp,nxp-nci-i2c"; +- reg = <0x28>; +- +- interrupt-parent = <&msmgpio>; +- interrupts = <21 IRQ_TYPE_EDGE_RISING>; +- +- enable-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>; +- firmware-gpios = <&msmgpio 2 GPIO_ACTIVE_HIGH>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&nfc_default>; +- }; +-}; +- +-&blsp1_uart2 { +- status = "okay"; +-}; +- +-&pm8916_resin { +- status = "okay"; +- linux,code = ; +-}; +- +-&pm8916_vib { +- status = "okay"; +-}; +- +-&pronto { +- status = "okay"; +-}; +- +-&sdhc_1 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; +- pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +-}; +- +-&sdhc_2 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdhc2_cd_default>; +- pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdhc2_cd_default>; +- +- /* +- * The Huawei device tree sets cd-gpios = <&msmgpio 38 GPIO_ACTIVE_HIGH>. +- * However, gpio38 does not change its state when inserting/removing the +- * SD card, it's just low all the time. The Huawei kernel seems to use +- * polling for SD card detection instead. +- * +- * However, looking closer at the GPIO debug output it turns out that +- * gpio56 switches its state when inserting/removing the SD card. +- * It behaves just like gpio38 normally does. Usually GPIO56 is used as +- * "UIM2_PRESENT", i.e. to check if a second SIM card is inserted. +- * Maybe Huawei decided to replace the second SIM card slot with the +- * SD card slot and forgot to re-route to gpio38. +- */ +- cd-gpios = <&msmgpio 56 GPIO_ACTIVE_LOW>; +-}; +- +-&usb { +- status = "okay"; +- extcon = <&usb_id>, <&usb_id>; +-}; +- +-&usb_hs_phy { +- extcon = <&usb_id>; +-}; +- +-&smd_rpm_regulators { +- vdd_l1_l2_l3-supply = <&pm8916_s3>; +- vdd_l4_l5_l6-supply = <&pm8916_s4>; +- vdd_l7-supply = <&pm8916_s4>; +- +- s3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1300000>; +- }; +- +- s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2100000>; +- }; +- +- l1 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- l4 { +- regulator-min-microvolt = <2050000>; +- regulator-max-microvolt = <2050000>; +- }; +- +- l5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l8 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- l9 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l10 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- l11 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- regulator-allow-set-load; +- regulator-system-load = <200000>; +- }; +- +- l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- l13 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- }; +- +- l14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l16 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l17 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- l18 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +-}; +- +-&msmgpio { +- accel_irq_default: accel-irq-default { +- pins = "gpio115"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- gpio_keys_default: gpio-keys-default { +- pins = "gpio107"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- gpio_leds_default: gpio-leds-default { +- pins = "gpio8", "gpio9", "gpio10"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- nfc_default: nfc-default { +- pins = "gpio2", "gpio20", "gpio21"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- mag_reset_default: mag-reset-default { +- pins = "gpio36"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- prox_irq_default: prox-irq-default { +- pins = "gpio113"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- reg_lcd_en_default: reg-lcd-en-default { +- pins = "gpio32", "gpio97"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- sdhc2_cd_default: sdhc2-cd-default { +- pins = "gpio56"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- ts_irq_default: ts-irq-default { +- pins = "gpio13"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- usb_id_default: usb-id-default { +- pins = "gpio117"; +- function = "gpio"; +- +- drive-strength = <8>; +- bias-pull-up; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-longcheer-l8150.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8916-longcheer-l8150.dts +deleted file mode 100644 +index 1e893c0b6fbc..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-longcheer-l8150.dts ++++ /dev/null +@@ -1,385 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +- +-/dts-v1/; +- +-#include "msm8916-pm8916.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "Longcheer L8150"; +- compatible = "longcheer,l8150", "qcom,msm8916-v1-qrd/9-v1", "qcom,msm8916"; +- +- aliases { +- serial0 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0"; +- }; +- +- reserved-memory { +- // wcnss.mdt is not relocatable, so it must be loaded at 0x8b600000 +- /delete-node/ wcnss@89300000; +- +- wcnss_mem: wcnss@8b600000 { +- reg = <0x0 0x8b600000 0x0 0x600000>; +- no-map; +- }; +- }; +- +- // FIXME: Use extcon device provided by charger driver when available +- usb_vbus: usb-vbus { +- compatible = "linux,extcon-usb-gpio"; +- vbus-gpio = <&msmgpio 62 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_vbus_default>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_default>; +- +- label = "GPIO Buttons"; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- reg_ctp: regulator-ctp { +- compatible = "regulator-fixed"; +- regulator-name = "ctp"; +- +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- +- gpio = <&msmgpio 17 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&ctp_pwr_en_default>; +- }; +- +- flash-led-controller { +- compatible = "sgmicro,sgm3140"; +- flash-gpios = <&msmgpio 31 GPIO_ACTIVE_HIGH>; +- enable-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&camera_flash_default>; +- +- flash_led: led { +- function = LED_FUNCTION_FLASH; +- color = ; +- flash-max-timeout-us = <250000>; +- }; +- }; +-}; +- +-&blsp_i2c1 { +- status = "okay"; +- +- led-controller@45 { +- compatible = "awinic,aw2013"; +- reg = <0x45>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- vcc-supply = <&pm8916_l17>; +- +- led@0 { +- reg = <0>; +- led-max-microamp = <5000>; +- function = LED_FUNCTION_INDICATOR; +- color = ; +- }; +- +- led@1 { +- reg = <1>; +- led-max-microamp = <5000>; +- function = LED_FUNCTION_INDICATOR; +- color = ; +- }; +- +- led@2 { +- reg = <2>; +- led-max-microamp = <5000>; +- function = LED_FUNCTION_INDICATOR; +- color = ; +- }; +- }; +-}; +- +-&blsp_i2c2 { +- status = "okay"; +- +- accelerometer@10 { +- compatible = "bosch,bmc150_accel"; +- reg = <0x10>; +- +- vdd-supply = <&pm8916_l17>; +- vddio-supply = <&pm8916_l6>; +- +- mount-matrix = "0", "1", "0", +- "-1", "0", "0", +- "0", "0", "1"; +- }; +- +- magnetometer@12 { +- compatible = "bosch,bmc150_magn"; +- reg = <0x12>; +- +- vdd-supply = <&pm8916_l17>; +- vddio-supply = <&pm8916_l6>; +- }; +- +- gyroscope@68 { +- compatible = "bosch,bmg160"; +- reg = <0x68>; +- +- interrupt-parent = <&msmgpio>; +- interrupts = <23 IRQ_TYPE_EDGE_RISING>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gyro_int_default>; +- +- vdd-supply = <&pm8916_l17>; +- vddio-supply = <&pm8916_l6>; +- }; +-}; +- +-&blsp_i2c5 { +- status = "okay"; +- +- rmi4@20 { +- compatible = "syna,rmi4-i2c"; +- reg = <0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- interrupt-parent = <&msmgpio>; +- interrupts = <13 IRQ_TYPE_EDGE_FALLING>; +- +- vdd-supply = <®_ctp>; +- vio-supply = <&pm8916_l6>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&tp_int_default>; +- +- syna,startup-delay-ms = <10>; +- +- rmi4-f01@1 { +- reg = <0x1>; +- syna,nosleep-mode = <1>; // Allow sleeping +- }; +- +- rmi4-f12@12 { +- reg = <0x12>; +- syna,sensor-type = <1>; // Touchscreen +- }; +- }; +-}; +- +-&blsp1_uart2 { +- status = "okay"; +-}; +- +-&pm8916_resin { +- status = "okay"; +- linux,code = ; +-}; +- +-&pm8916_vib { +- status = "okay"; +-}; +- +-&pronto { +- status = "okay"; +-}; +- +-&sdhc_1 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; +- pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +-}; +- +-&sdhc_2 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; +- pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; +- +- non-removable; +-}; +- +-&usb { +- status = "okay"; +- dr_mode = "peripheral"; +- extcon = <&usb_vbus>; +-}; +- +-&usb_hs_phy { +- extcon = <&usb_vbus>; +-}; +- +-&smd_rpm_regulators { +- vdd_l1_l2_l3-supply = <&pm8916_s3>; +- vdd_l4_l5_l6-supply = <&pm8916_s4>; +- vdd_l7-supply = <&pm8916_s4>; +- +- s3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1300000>; +- }; +- +- s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2100000>; +- }; +- +- l1 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- l4 { +- regulator-min-microvolt = <2050000>; +- regulator-max-microvolt = <2050000>; +- }; +- +- l5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l8 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2900000>; +- }; +- +- l9 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l10 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- l11 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- regulator-allow-set-load; +- regulator-system-load = <200000>; +- }; +- +- l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- l13 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- }; +- +- l14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l16 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l17 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- l18 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +-}; +- +-&msmgpio { +- camera_flash_default: camera-flash-default { +- pins = "gpio31", "gpio32"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- ctp_pwr_en_default: ctp-pwr-en-default { +- pins = "gpio17"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- gpio_keys_default: gpio-keys-default { +- pins = "gpio107"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- gyro_int_default: gyro-int-default { +- pins = "gpio23"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- tp_int_default: tp-int-default { +- pins = "gpio13"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- usb_vbus_default: usb-vbus-default { +- pins = "gpio62"; +- function = "gpio"; +- +- bias-pull-up; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-longcheer-l8910.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8916-longcheer-l8910.dts +deleted file mode 100644 +index 27845189ac2b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-longcheer-l8910.dts ++++ /dev/null +@@ -1,267 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +- +-/dts-v1/; +- +-#include "msm8916-pm8916.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "BQ Aquaris X5 (Longcheer L8910)"; +- compatible = "longcheer,l8910", "qcom,msm8916"; +- +- aliases { +- serial0 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_default>; +- +- label = "GPIO Buttons"; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- gpios = <&msmgpio 17 GPIO_ACTIVE_HIGH>; +- color = ; +- default-state = "off"; +- function = LED_FUNCTION_KBD_BACKLIGHT; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&button_backlight_default>; +- }; +- }; +- +- usb_id: usb-id { +- compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&msmgpio 110 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_id_default>; +- }; +-}; +- +-&blsp_i2c3 { +- status = "okay"; +- +- magnetometer@d { +- compatible = "asahi-kasei,ak09911"; +- reg = <0x0d>; +- +- vdd-supply = <&pm8916_l17>; +- vid-supply = <&pm8916_l6>; +- +- reset-gpios = <&msmgpio 111 GPIO_ACTIVE_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&mag_reset_default>; +- }; +- +- imu@68 { +- compatible = "bosch,bmi160"; +- reg = <0x68>; +- +- vdd-supply = <&pm8916_l17>; +- vddio-supply = <&pm8916_l6>; +- +- mount-matrix = "0", "1", "0", +- "-1", "0", "0", +- "0", "0", "1"; +- }; +-}; +- +-&blsp1_uart2 { +- status = "okay"; +-}; +- +-&pm8916_resin { +- status = "okay"; +- linux,code = ; +-}; +- +-&pm8916_vib { +- status = "okay"; +-}; +- +-&pronto { +- status = "okay"; +-}; +- +-&sdhc_1 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; +- pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +-}; +- +-&sdhc_2 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; +- pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; +- +- cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; +-}; +- +-&usb { +- status = "okay"; +- extcon = <&usb_id>, <&usb_id>; +-}; +- +-&usb_hs_phy { +- extcon = <&usb_id>; +-}; +- +-&smd_rpm_regulators { +- vdd_l1_l2_l3-supply = <&pm8916_s3>; +- vdd_l4_l5_l6-supply = <&pm8916_s4>; +- vdd_l7-supply = <&pm8916_s4>; +- +- s3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1300000>; +- }; +- +- s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2100000>; +- }; +- +- l1 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- l4 { +- regulator-min-microvolt = <2050000>; +- regulator-max-microvolt = <2050000>; +- }; +- +- l5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l8 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2900000>; +- }; +- +- l9 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l10 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- l11 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- regulator-allow-set-load; +- regulator-system-load = <200000>; +- }; +- +- l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- l13 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- }; +- +- l14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l16 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l17 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- l18 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +-}; +- +-&msmgpio { +- button_backlight_default: button-backlight-default { +- pins = "gpio17"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- gpio_keys_default: gpio-keys-default { +- pins = "gpio107"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- mag_reset_default: mag-reset-default { +- pins = "gpio111"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- usb_id_default: usb-id-default { +- pins = "gpio110"; +- function = "gpio"; +- +- drive-strength = <8>; +- bias-pull-up; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-mtp.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8916-mtp.dts +deleted file mode 100644 +index d66c15538785..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-mtp.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "msm8916-mtp.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. MSM 8916 MTP"; +- compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp/1", "qcom,msm8916"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-mtp.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/msm8916-mtp.dtsi +deleted file mode 100644 +index 1bd05046cdeb..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-mtp.dtsi ++++ /dev/null +@@ -1,21 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. +- */ +- +-#include "msm8916-pm8916.dtsi" +- +-/ { +- aliases { +- serial0 = &blsp1_uart2; +- usid0 = &pm8916_0; +- }; +- +- chosen { +- stdout-path = "serial0"; +- }; +-}; +- +-&blsp1_uart2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-pins.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/msm8916-pins.dtsi +deleted file mode 100644 +index 7dedb91b9930..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-pins.dtsi ++++ /dev/null +@@ -1,578 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. +- */ +- +-&msmgpio { +- +- blsp1_uart1_default: blsp1-uart1-default { +- // TX, RX, CTS_N, RTS_N +- pins = "gpio0", "gpio1", "gpio2", "gpio3"; +- function = "blsp_uart1"; +- +- drive-strength = <16>; +- bias-disable; +- }; +- +- blsp1_uart1_sleep: blsp1-uart1-sleep { +- pins = "gpio0", "gpio1", "gpio2", "gpio3"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- blsp1_uart2_default: blsp1-uart2-default { +- pins = "gpio4", "gpio5"; +- function = "blsp_uart2"; +- +- drive-strength = <16>; +- bias-disable; +- }; +- +- blsp1_uart2_sleep: blsp1-uart2-sleep { +- pins = "gpio4", "gpio5"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- spi1_default: spi1-default { +- pins = "gpio0", "gpio1", "gpio3"; +- function = "blsp_spi1"; +- +- drive-strength = <12>; +- bias-disable; +- +- cs { +- pins = "gpio2"; +- function = "gpio"; +- +- drive-strength = <16>; +- bias-disable; +- output-high; +- }; +- }; +- +- spi1_sleep: spi1-sleep { +- pins = "gpio0", "gpio1", "gpio2", "gpio3"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- spi2_default: spi2-default { +- pins = "gpio4", "gpio5", "gpio7"; +- function = "blsp_spi2"; +- +- drive-strength = <12>; +- bias-disable; +- +- cs { +- pins = "gpio6"; +- function = "gpio"; +- +- drive-strength = <16>; +- bias-disable; +- output-high; +- }; +- }; +- +- spi2_sleep: spi2-sleep { +- pins = "gpio4", "gpio5", "gpio6", "gpio7"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- spi3_default: spi3-default { +- pins = "gpio8", "gpio9", "gpio11"; +- function = "blsp_spi3"; +- +- drive-strength = <12>; +- bias-disable; +- +- cs { +- pins = "gpio10"; +- function = "gpio"; +- +- drive-strength = <16>; +- bias-disable; +- output-high; +- }; +- }; +- +- spi3_sleep: spi3-sleep { +- pins = "gpio8", "gpio9", "gpio10", "gpio11"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- spi4_default: spi4-default { +- pins = "gpio12", "gpio13", "gpio15"; +- function = "blsp_spi4"; +- +- drive-strength = <12>; +- bias-disable; +- +- cs { +- pins = "gpio14"; +- function = "gpio"; +- +- drive-strength = <16>; +- bias-disable; +- output-high; +- }; +- }; +- +- spi4_sleep: spi4-sleep { +- pins = "gpio12", "gpio13", "gpio14", "gpio15"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- spi5_default: spi5-default { +- pins = "gpio16", "gpio17", "gpio19"; +- function = "blsp_spi5"; +- +- drive-strength = <12>; +- bias-disable; +- +- cs { +- pins = "gpio18"; +- function = "gpio"; +- +- drive-strength = <16>; +- bias-disable; +- output-high; +- }; +- }; +- +- spi5_sleep: spi5-sleep { +- pins = "gpio16", "gpio17", "gpio18", "gpio19"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- spi6_default: spi6-default { +- pins = "gpio20", "gpio21", "gpio23"; +- function = "blsp_spi6"; +- +- drive-strength = <12>; +- bias-disable; +- +- cs { +- pins = "gpio22"; +- function = "gpio"; +- +- drive-strength = <16>; +- bias-disable; +- output-high; +- }; +- }; +- +- spi6_sleep: spi6-sleep { +- pins = "gpio20", "gpio21", "gpio22", "gpio23"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- i2c1_default: i2c1-default { +- pins = "gpio2", "gpio3"; +- function = "blsp_i2c1"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c1_sleep: i2c1-sleep { +- pins = "gpio2", "gpio3"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c2_default: i2c2-default { +- pins = "gpio6", "gpio7"; +- function = "blsp_i2c2"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c2_sleep: i2c2-sleep { +- pins = "gpio6", "gpio7"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c3_default: i2c3-default { +- pins = "gpio10", "gpio11"; +- function = "blsp_i2c3"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c3_sleep: i2c3-sleep { +- pins = "gpio10", "gpio11"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c4_default: i2c4-default { +- pins = "gpio14", "gpio15"; +- function = "blsp_i2c4"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c4_sleep: i2c4-sleep { +- pins = "gpio14", "gpio15"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c5_default: i2c5-default { +- pins = "gpio18", "gpio19"; +- function = "blsp_i2c5"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c5_sleep: i2c5-sleep { +- pins = "gpio18", "gpio19"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c6_default: i2c6-default { +- pins = "gpio22", "gpio23"; +- function = "blsp_i2c6"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c6_sleep: i2c6-sleep { +- pins = "gpio22", "gpio23"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- pmx-sdc1-clk { +- sdc1_clk_on: clk-on { +- pins = "sdc1_clk"; +- +- bias-disable; +- drive-strength = <16>; +- }; +- sdc1_clk_off: clk-off { +- pins = "sdc1_clk"; +- +- bias-disable; +- drive-strength = <2>; +- }; +- }; +- +- pmx-sdc1-cmd { +- sdc1_cmd_on: cmd-on { +- pins = "sdc1_cmd"; +- +- bias-pull-up; +- drive-strength = <10>; +- }; +- sdc1_cmd_off: cmd-off { +- pins = "sdc1_cmd"; +- +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +- +- pmx-sdc1-data { +- sdc1_data_on: data-on { +- pins = "sdc1_data"; +- +- bias-pull-up; +- drive-strength = <10>; +- }; +- sdc1_data_off: data-off { +- pins = "sdc1_data"; +- +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +- +- pmx-sdc2-clk { +- sdc2_clk_on: clk-on { +- pins = "sdc2_clk"; +- +- bias-disable; +- drive-strength = <16>; +- }; +- sdc2_clk_off: clk-off { +- pins = "sdc2_clk"; +- +- bias-disable; +- drive-strength = <2>; +- }; +- }; +- +- pmx-sdc2-cmd { +- sdc2_cmd_on: cmd-on { +- pins = "sdc2_cmd"; +- +- bias-pull-up; +- drive-strength = <10>; +- }; +- sdc2_cmd_off: cmd-off { +- pins = "sdc2_cmd"; +- +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +- +- pmx-sdc2-data { +- sdc2_data_on: data-on { +- pins = "sdc2_data"; +- +- bias-pull-up; +- drive-strength = <10>; +- }; +- sdc2_data_off: data-off { +- pins = "sdc2_data"; +- +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +- +- pmx-sdc2-cd-pin { +- sdc2_cd_on: cd-on { +- pins = "gpio38"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-up; +- }; +- sdc2_cd_off: cd-off { +- pins = "gpio38"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- cdc-pdm-lines { +- cdc_pdm_lines_act: pdm-lines-on { +- pins = "gpio63", "gpio64", "gpio65", "gpio66", +- "gpio67", "gpio68"; +- function = "cdc_pdm0"; +- +- drive-strength = <8>; +- bias-disable; +- }; +- cdc_pdm_lines_sus: pdm-lines-off { +- pins = "gpio63", "gpio64", "gpio65", "gpio66", +- "gpio67", "gpio68"; +- function = "cdc_pdm0"; +- +- drive-strength = <2>; +- bias-pull-down; +- }; +- }; +- +- ext-pri-tlmm-lines { +- ext_pri_tlmm_lines_act: ext-pa-on { +- pins = "gpio113", "gpio114", "gpio115", "gpio116"; +- function = "pri_mi2s"; +- +- drive-strength = <8>; +- bias-disable; +- }; +- ext_pri_tlmm_lines_sus: ext-pa-off { +- pins = "gpio113", "gpio114", "gpio115", "gpio116"; +- function = "pri_mi2s"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- ext-pri-ws-line { +- ext_pri_ws_act: ext-pa-on { +- pins = "gpio110"; +- function = "pri_mi2s_ws"; +- +- drive-strength = <8>; +- bias-disable; +- }; +- ext_pri_ws_sus: ext-pa-off { +- pins = "gpio110"; +- function = "pri_mi2s_ws"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- ext-mclk-tlmm-lines { +- ext_mclk_tlmm_lines_act: mclk-lines-on { +- pins = "gpio116"; +- function = "pri_mi2s"; +- +- drive-strength = <8>; +- bias-disable; +- }; +- ext_mclk_tlmm_lines_sus: mclk-lines-off { +- pins = "gpio116"; +- function = "pri_mi2s"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- /* secondary Mi2S */ +- ext-sec-tlmm-lines { +- ext_sec_tlmm_lines_act: tlmm-lines-on { +- pins = "gpio112", "gpio117", "gpio118", "gpio119"; +- function = "sec_mi2s"; +- +- drive-strength = <8>; +- bias-disable; +- }; +- ext_sec_tlmm_lines_sus: tlmm-lines-off { +- pins = "gpio112", "gpio117", "gpio118", "gpio119"; +- function = "sec_mi2s"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- cdc-dmic-lines { +- cdc_dmic_lines_act: dmic-lines-on { +- clk { +- pins = "gpio0"; +- function = "dmic0_clk"; +- +- drive-strength = <8>; +- }; +- data { +- pins = "gpio1"; +- function = "dmic0_data"; +- +- drive-strength = <8>; +- }; +- }; +- cdc_dmic_lines_sus: dmic-lines-off { +- clk { +- pins = "gpio0"; +- function = "dmic0_clk"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- data { +- pins = "gpio1"; +- function = "dmic0_data"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- }; +- +- wcnss_pin_a: wcnss-active { +- pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; +- function = "wcss_wlan"; +- +- drive-strength = <6>; +- bias-pull-up; +- }; +- +- cci0_default: cci0-default { +- pins = "gpio29", "gpio30"; +- function = "cci_i2c"; +- +- drive-strength = <16>; +- bias-disable; +- }; +- +- camera_front_default: camera-front-default { +- pwdn { +- pins = "gpio33"; +- function = "gpio"; +- +- drive-strength = <16>; +- bias-disable; +- }; +- rst { +- pins = "gpio28"; +- function = "gpio"; +- +- drive-strength = <16>; +- bias-disable; +- }; +- mclk1 { +- pins = "gpio27"; +- function = "cam_mclk1"; +- +- drive-strength = <16>; +- bias-disable; +- }; +- }; +- +- camera_rear_default: camera-rear-default { +- pwdn { +- pins = "gpio34"; +- function = "gpio"; +- +- drive-strength = <16>; +- bias-disable; +- }; +- rst { +- pins = "gpio35"; +- function = "gpio"; +- +- drive-strength = <16>; +- bias-disable; +- }; +- mclk0 { +- pins = "gpio26"; +- function = "cam_mclk0"; +- +- drive-strength = <16>; +- bias-disable; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-pm8916.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/msm8916-pm8916.dtsi +deleted file mode 100644 +index 539823b2c36e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-pm8916.dtsi ++++ /dev/null +@@ -1,76 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +- +-#include "msm8916.dtsi" +-#include "pm8916.dtsi" +- +-&camss { +- vdda-supply = <&pm8916_l2>; +-}; +- +-&dsi0 { +- vdda-supply = <&pm8916_l2>; +- vddio-supply = <&pm8916_l6>; +-}; +- +-&dsi_phy0 { +- vddio-supply = <&pm8916_l6>; +-}; +- +-&mpss { +- pll-supply = <&pm8916_l7>; +-}; +- +-&pronto { +- vddpx-supply = <&pm8916_l7>; +- +- iris { +- vddxo-supply = <&pm8916_l7>; +- vddrfa-supply = <&pm8916_s3>; +- vddpa-supply = <&pm8916_l9>; +- vdddig-supply = <&pm8916_l5>; +- }; +-}; +- +-&sdhc_1 { +- vmmc-supply = <&pm8916_l8>; +- vqmmc-supply = <&pm8916_l5>; +-}; +- +-&sdhc_2 { +- vmmc-supply = <&pm8916_l11>; +- vqmmc-supply = <&pm8916_l12>; +-}; +- +-&usb_hs_phy { +- v1p8-supply = <&pm8916_l7>; +- v3p3-supply = <&pm8916_l13>; +-}; +- +-&rpm_requests { +- smd_rpm_regulators: pm8916-regulators { +- compatible = "qcom,rpm-pm8916-regulators"; +- +- /* pm8916_s1 is managed by rpmpd (MSM8916_VDDCX) */ +- pm8916_s3: s3 {}; +- pm8916_s4: s4 {}; +- +- pm8916_l1: l1 {}; +- pm8916_l2: l2 {}; +- /* pm8916_l3 is managed by rpmpd (MSM8916_VDDMX) */ +- pm8916_l4: l4 {}; +- pm8916_l5: l5 {}; +- pm8916_l6: l6 {}; +- pm8916_l7: l7 {}; +- pm8916_l8: l8 {}; +- pm8916_l9: l9 {}; +- pm8916_l10: l10 {}; +- pm8916_l11: l11 {}; +- pm8916_l12: l12 {}; +- pm8916_l13: l13 {}; +- pm8916_l14: l14 {}; +- pm8916_l15: l15 {}; +- pm8916_l16: l16 {}; +- pm8916_l17: l17 {}; +- pm8916_l18: l18 {}; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-samsung-a2015-common.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/msm8916-samsung-a2015-common.dtsi +deleted file mode 100644 +index 9b4b7de7cec2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-samsung-a2015-common.dtsi ++++ /dev/null +@@ -1,474 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +- +-#include "msm8916-pm8916.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- aliases { +- serial0 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0"; +- }; +- +- reserved-memory { +- /* Additional memory used by Samsung firmware modifications */ +- tz-apps@85500000 { +- reg = <0x0 0x85500000 0x0 0xb00000>; +- no-map; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_default>; +- +- label = "GPIO Buttons"; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- home { +- label = "Home"; +- gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- gpio-hall-sensor { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_hall_sensor_default>; +- +- label = "GPIO Hall Effect Sensor"; +- +- hall-sensor { +- label = "Hall Effect Sensor"; +- gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; +- linux,input-type = ; +- linux,code = ; +- linux,can-disable; +- }; +- }; +- +- reg_vdd_tsp: regulator-vdd-tsp { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_tsp"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&tsp_en_default>; +- }; +- +- i2c-muic { +- compatible = "i2c-gpio"; +- sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&muic_i2c_default>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- muic: extcon@25 { +- compatible = "siliconmitus,sm5502-muic"; +- +- reg = <0x25>; +- interrupt-parent = <&msmgpio>; +- interrupts = <12 IRQ_TYPE_EDGE_FALLING>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&muic_int_default>; +- }; +- }; +- +- i2c-tkey { +- compatible = "i2c-gpio"; +- sda-gpios = <&msmgpio 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&msmgpio 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&tkey_i2c_default>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- touchkey: touchkey@20 { +- /* Note: Actually an ABOV MCU that implements same interface */ +- compatible = "coreriver,tc360-touchkey"; +- reg = <0x20>; +- +- interrupt-parent = <&msmgpio>; +- interrupts = <98 IRQ_TYPE_EDGE_FALLING>; +- +- /* vcc/vdd-supply are board-specific */ +- vddio-supply = <&pm8916_l6>; +- +- linux,keycodes = ; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&tkey_default>; +- }; +- }; +- +- i2c-nfc { +- compatible = "i2c-gpio"; +- sda-gpios = <&msmgpio 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&msmgpio 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&nfc_i2c_default>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- nfc@27 { +- compatible = "samsung,s3fwrn5-i2c"; +- reg = <0x27>; +- +- interrupt-parent = <&msmgpio>; +- interrupts = <21 IRQ_TYPE_EDGE_RISING>; +- +- en-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>; +- wake-gpios = <&msmgpio 49 GPIO_ACTIVE_HIGH>; +- +- clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&nfc_default &nfc_clk_req>; +- }; +- }; +-}; +- +-&blsp_i2c2 { +- status = "okay"; +- +- accelerometer: accelerometer@10 { +- compatible = "bosch,bmc150_accel"; +- reg = <0x10>; +- interrupt-parent = <&msmgpio>; +- interrupts = <115 IRQ_TYPE_EDGE_RISING>; +- +- vdd-supply = <&pm8916_l17>; +- vddio-supply = <&pm8916_l5>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&accel_int_default>; +- }; +- +- magnetometer@12 { +- compatible = "bosch,bmc150_magn"; +- reg = <0x12>; +- +- vdd-supply = <&pm8916_l17>; +- vddio-supply = <&pm8916_l5>; +- }; +-}; +- +-&blsp_i2c4 { +- status = "okay"; +- +- battery@35 { +- compatible = "richtek,rt5033-battery"; +- reg = <0x35>; +- interrupt-parent = <&msmgpio>; +- interrupts = <121 IRQ_TYPE_EDGE_BOTH>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&fg_alert_default>; +- }; +-}; +- +-&blsp1_uart2 { +- status = "okay"; +-}; +- +-&dsi0 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&mdss_default>; +- pinctrl-1 = <&mdss_sleep>; +-}; +- +-&mdss { +- status = "okay"; +-}; +- +-&pm8916_resin { +- status = "okay"; +- linux,code = ; +-}; +- +-&pronto { +- status = "okay"; +-}; +- +-&sdhc_1 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; +- pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +-}; +- +-&sdhc_2 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; +- pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; +- +- cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; +-}; +- +-&usb { +- status = "okay"; +- extcon = <&muic>, <&muic>; +-}; +- +-&usb_hs_phy { +- extcon = <&muic>; +-}; +- +-&smd_rpm_regulators { +- vdd_l1_l2_l3-supply = <&pm8916_s3>; +- vdd_l4_l5_l6-supply = <&pm8916_s4>; +- vdd_l7-supply = <&pm8916_s4>; +- +- s3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1300000>; +- }; +- +- s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2100000>; +- }; +- +- l1 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- l4 { +- regulator-min-microvolt = <2050000>; +- regulator-max-microvolt = <2050000>; +- }; +- +- l5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l8 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2900000>; +- }; +- +- l9 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l10 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- l11 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- regulator-allow-set-load; +- regulator-system-load = <200000>; +- }; +- +- l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- l13 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- }; +- +- l14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l16 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l17 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- l18 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +-}; +- +-&msmgpio { +- accel_int_default: accel-int-default { +- pins = "gpio115"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- fg_alert_default: fg-alert-default { +- pins = "gpio121"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- gpio_keys_default: gpio-keys-default { +- pins = "gpio107", "gpio109"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- gpio_hall_sensor_default: gpio-hall-sensor-default { +- pins = "gpio52"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- mdss { +- mdss_default: mdss-default { +- pins = "gpio25"; +- function = "gpio"; +- +- drive-strength = <8>; +- bias-disable; +- }; +- mdss_sleep: mdss-sleep { +- pins = "gpio25"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-down; +- }; +- }; +- +- muic_i2c_default: muic-i2c-default { +- pins = "gpio105", "gpio106"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- muic_int_default: muic-int-default { +- pins = "gpio12"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- nfc_default: nfc-default { +- pins = "gpio20", "gpio49"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- +- irq { +- pins = "gpio21"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-down; +- }; +- }; +- +- nfc_i2c_default: nfc-i2c-default { +- pins = "gpio0", "gpio1"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- tkey_default: tkey-default { +- pins = "gpio98"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- tkey_i2c_default: tkey-i2c-default { +- pins = "gpio16", "gpio17"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- tsp_en_default: tsp-en-default { +- pins = "gpio73"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +-}; +- +-&pm8916_gpios { +- nfc_clk_req: nfc-clk-req { +- pins = "gpio2"; +- function = "func1"; +- +- input-enable; +- bias-disable; +- power-source = ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-samsung-a3u-eur.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8916-samsung-a3u-eur.dts +deleted file mode 100644 +index 6cc2eaeb1d33..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-samsung-a3u-eur.dts ++++ /dev/null +@@ -1,138 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +- +-/dts-v1/; +- +-#include "msm8916-samsung-a2015-common.dtsi" +- +-/ { +- model = "Samsung Galaxy A3U (EUR)"; +- compatible = "samsung,a3u-eur", "qcom,msm8916"; +- +- reg_panel_vdd3: regulator-panel-vdd3 { +- compatible = "regulator-fixed"; +- regulator-name = "panel_vdd3"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- gpio = <&msmgpio 9 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&panel_vdd3_default>; +- }; +- +- reg_touch_key: regulator-touch-key { +- compatible = "regulator-fixed"; +- regulator-name = "touch_key"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- +- gpio = <&msmgpio 86 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&tkey_en_default>; +- }; +- +- reg_key_led: regulator-key-led { +- compatible = "regulator-fixed"; +- regulator-name = "key_led"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&msmgpio 60 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&tkey_led_en_default>; +- }; +-}; +- +-&touchkey { +- vcc-supply = <®_touch_key>; +- vdd-supply = <®_key_led>; +-}; +- +-&accelerometer { +- mount-matrix = "0", "1", "0", +- "1", "0", "0", +- "0", "0", "1"; +-}; +- +-&blsp_i2c5 { +- status = "okay"; +- +- touchscreen@20 { +- compatible = "zinitix,bt541"; +- +- reg = <0x20>; +- interrupt-parent = <&msmgpio>; +- interrupts = <13 IRQ_TYPE_EDGE_FALLING>; +- +- touchscreen-size-x = <540>; +- touchscreen-size-y = <960>; +- +- vdd-supply = <®_vdd_tsp>; +- vddo-supply = <&pm8916_l6>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&ts_int_default>; +- }; +-}; +- +-&dsi0 { +- panel@0 { +- reg = <0>; +- +- compatible = "samsung,s6e88a0-ams452ef01"; +- +- vdd3-supply = <®_panel_vdd3>; +- vci-supply = <&pm8916_l17>; +- reset-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&dsi0_out>; +- }; +- }; +- }; +-}; +- +-&dsi0_out { +- data-lanes = <0 1>; +- remote-endpoint = <&panel_in>; +-}; +- +-&msmgpio { +- panel_vdd3_default: panel-vdd3-default { +- pins = "gpio9"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- tkey_en_default: tkey-en-default { +- pins = "gpio86"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- tkey_led_en_default: tkey-led-en-default { +- pins = "gpio60"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- ts_int_default: ts-int-default { +- pins = "gpio13"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-samsung-a5u-eur.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8916-samsung-a5u-eur.dts +deleted file mode 100644 +index c2eff5aebf85..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-samsung-a5u-eur.dts ++++ /dev/null +@@ -1,79 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +- +-/dts-v1/; +- +-#include "msm8916-samsung-a2015-common.dtsi" +- +-/ { +- model = "Samsung Galaxy A5U (EUR)"; +- compatible = "samsung,a5u-eur", "qcom,msm8916"; +- +- reg_touch_key: regulator-touch-key { +- compatible = "regulator-fixed"; +- regulator-name = "touch_key"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&msmgpio 97 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&tkey_en_default>; +- }; +-}; +- +-&accelerometer { +- mount-matrix = "-1", "0", "0", +- "0", "1", "0", +- "0", "0", "1"; +-}; +- +-&blsp_i2c5 { +- status = "okay"; +- +- touchscreen@48 { +- compatible = "melfas,mms345l"; +- +- reg = <0x48>; +- interrupt-parent = <&msmgpio>; +- interrupts = <13 IRQ_TYPE_EDGE_FALLING>; +- +- touchscreen-size-x = <720>; +- touchscreen-size-y = <1280>; +- +- avdd-supply = <®_vdd_tsp>; +- vdd-supply = <&pm8916_l6>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&ts_int_default>; +- }; +-}; +- +-&pronto { +- iris { +- compatible = "qcom,wcn3660b"; +- }; +-}; +- +-&touchkey { +- vcc-supply = <®_touch_key>; +- vdd-supply = <®_touch_key>; +-}; +- +-&msmgpio { +- tkey_en_default: tkey-en-default { +- pins = "gpio97"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- ts_int_default: ts-int-default { +- pins = "gpio13"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-wingtech-wt88047.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8916-wingtech-wt88047.dts +deleted file mode 100644 +index 4e20cc0008f7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8916-wingtech-wt88047.dts ++++ /dev/null +@@ -1,313 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-// Copyright (C) 2020 Stephan Gerhold +- +-/dts-v1/; +- +-#include "msm8916-pm8916.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "Xiaomi Redmi 2 (Wingtech WT88047)"; +- compatible = "wingtech,wt88047", "qcom,msm8916"; +- +- aliases { +- serial0 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&gpio_keys_default>; +- +- label = "GPIO Buttons"; +- +- volume-up { +- label = "Volume Up"; +- gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- usb_id: usb-id { +- compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&msmgpio 110 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_id_default>; +- }; +-}; +- +-&blsp_i2c2 { +- status = "okay"; +- +- imu@68 { +- compatible = "invensense,mpu6880"; +- reg = <0x68>; +- +- interrupt-parent = <&msmgpio>; +- interrupts = <115 IRQ_TYPE_EDGE_RISING>; +- +- vdd-supply = <&pm8916_l17>; +- vddio-supply = <&pm8916_l6>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&imu_default>; +- +- mount-matrix = "1", "0", "0", +- "0", "-1", "0", +- "0", "0", "1"; +- }; +-}; +- +-&blsp_i2c5 { +- status = "okay"; +- +- touchscreen@38 { +- /* Likely some other model but works just fine with this one */ +- compatible = "edt,edt-ft5506"; +- reg = <0x38>; +- +- interrupt-parent = <&msmgpio>; +- interrupts = <13 IRQ_TYPE_EDGE_FALLING>; +- +- reset-gpios = <&msmgpio 12 GPIO_ACTIVE_LOW>; +- +- vcc-supply = <&pm8916_l17>; +- iovcc-supply = <&pm8916_l6>; +- +- touchscreen-size-x = <720>; +- touchscreen-size-y = <1280>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&touchscreen_default>; +- }; +-}; +- +-&blsp_i2c6 { +- status = "okay"; +- +- led-controller@45 { +- compatible = "awinic,aw2013"; +- reg = <0x45>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- vcc-supply = <&pm8916_l16>; +- +- led@0 { +- reg = <0>; +- led-max-microamp = <15000>; +- function = LED_FUNCTION_INDICATOR; +- color = ; +- }; +- +- led@1 { +- reg = <1>; +- led-max-microamp = <15000>; +- function = LED_FUNCTION_INDICATOR; +- color = ; +- }; +- +- led@2 { +- reg = <2>; +- led-max-microamp = <15000>; +- function = LED_FUNCTION_INDICATOR; +- color = ; +- }; +- }; +-}; +- +-&blsp1_uart2 { +- status = "okay"; +-}; +- +-&pm8916_resin { +- status = "okay"; +- linux,code = ; +-}; +- +-&pm8916_vib { +- status = "okay"; +-}; +- +-&pronto { +- status = "okay"; +-}; +- +-&sdhc_1 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; +- pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +-}; +- +-&sdhc_2 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; +- pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; +- +- non-removable; +-}; +- +-&usb { +- status = "okay"; +- extcon = <&usb_id>, <&usb_id>; +-}; +- +-&usb_hs_phy { +- extcon = <&usb_id>; +-}; +- +-&smd_rpm_regulators { +- vdd_l1_l2_l3-supply = <&pm8916_s3>; +- vdd_l4_l5_l6-supply = <&pm8916_s4>; +- vdd_l7-supply = <&pm8916_s4>; +- +- s3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1300000>; +- }; +- +- s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2100000>; +- }; +- +- l1 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- l4 { +- regulator-min-microvolt = <2050000>; +- regulator-max-microvolt = <2050000>; +- }; +- +- l5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- l8 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2900000>; +- }; +- +- l9 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l10 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- l11 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- regulator-allow-set-load; +- regulator-system-load = <200000>; +- }; +- +- l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- l13 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- }; +- +- l14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l16 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- l17 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- l18 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +-}; +- +-&msmgpio { +- gpio_keys_default: gpio-keys-default { +- pins = "gpio107"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- imu_default: imu-default { +- pins = "gpio115"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- touchscreen_default: touchscreen-default { +- pins = "gpio13"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-up; +- +- reset { +- pins = "gpio12"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- usb_id_default: usb-id-default { +- pins = "gpio110"; +- function = "gpio"; +- +- drive-strength = <8>; +- bias-pull-up; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8916.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/msm8916.dtsi +deleted file mode 100644 +index 8b2724272464..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8916.dtsi ++++ /dev/null +@@ -1,2004 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&intc>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- mmc0 = &sdhc_1; /* SDC1 eMMC slot */ +- mmc1 = &sdhc_2; /* SDC2 SD card slot */ +- }; +- +- chosen { }; +- +- memory@80000000 { +- device_type = "memory"; +- /* We expect the bootloader to fill in the reg */ +- reg = <0 0x80000000 0 0>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- tz-apps@86000000 { +- reg = <0x0 0x86000000 0x0 0x300000>; +- no-map; +- }; +- +- smem_mem: smem_region@86300000 { +- reg = <0x0 0x86300000 0x0 0x100000>; +- no-map; +- }; +- +- hypervisor@86400000 { +- reg = <0x0 0x86400000 0x0 0x100000>; +- no-map; +- }; +- +- tz@86500000 { +- reg = <0x0 0x86500000 0x0 0x180000>; +- no-map; +- }; +- +- reserved@86680000 { +- reg = <0x0 0x86680000 0x0 0x80000>; +- no-map; +- }; +- +- rmtfs@86700000 { +- compatible = "qcom,rmtfs-mem"; +- reg = <0x0 0x86700000 0x0 0xe0000>; +- no-map; +- +- qcom,client-id = <1>; +- }; +- +- rfsa@867e0000 { +- reg = <0x0 0x867e0000 0x0 0x20000>; +- no-map; +- }; +- +- mpss_mem: mpss@86800000 { +- reg = <0x0 0x86800000 0x0 0x2b00000>; +- no-map; +- }; +- +- wcnss_mem: wcnss@89300000 { +- reg = <0x0 0x89300000 0x0 0x600000>; +- no-map; +- }; +- +- venus_mem: venus@89900000 { +- reg = <0x0 0x89900000 0x0 0x600000>; +- no-map; +- }; +- +- mba_mem: mba@8ea00000 { +- no-map; +- reg = <0 0x8ea00000 0 0x100000>; +- }; +- }; +- +- clocks { +- xo_board: xo-board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <19200000>; +- }; +- +- sleep_clk: sleep-clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- CPU0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0>; +- next-level-cache = <&L2_0>; +- enable-method = "psci"; +- clocks = <&apcs>; +- operating-points-v2 = <&cpu_opp_table>; +- #cooling-cells = <2>; +- power-domains = <&CPU_PD0>; +- power-domain-names = "psci"; +- }; +- +- CPU1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x1>; +- next-level-cache = <&L2_0>; +- enable-method = "psci"; +- clocks = <&apcs>; +- operating-points-v2 = <&cpu_opp_table>; +- #cooling-cells = <2>; +- power-domains = <&CPU_PD1>; +- power-domain-names = "psci"; +- }; +- +- CPU2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x2>; +- next-level-cache = <&L2_0>; +- enable-method = "psci"; +- clocks = <&apcs>; +- operating-points-v2 = <&cpu_opp_table>; +- #cooling-cells = <2>; +- power-domains = <&CPU_PD2>; +- power-domain-names = "psci"; +- }; +- +- CPU3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x3>; +- next-level-cache = <&L2_0>; +- enable-method = "psci"; +- clocks = <&apcs>; +- operating-points-v2 = <&cpu_opp_table>; +- #cooling-cells = <2>; +- power-domains = <&CPU_PD3>; +- power-domain-names = "psci"; +- }; +- +- L2_0: l2-cache { +- compatible = "cache"; +- cache-level = <2>; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP_0: cpu-sleep-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "standalone-power-collapse"; +- arm,psci-suspend-param = <0x40000002>; +- entry-latency-us = <130>; +- exit-latency-us = <150>; +- min-residency-us = <2000>; +- local-timer-stop; +- }; +- }; +- +- domain-idle-states { +- +- CLUSTER_RET: cluster-retention { +- compatible = "domain-idle-state"; +- arm,psci-suspend-param = <0x41000012>; +- entry-latency-us = <500>; +- exit-latency-us = <500>; +- min-residency-us = <2000>; +- }; +- +- CLUSTER_PWRDN: cluster-gdhs { +- compatible = "domain-idle-state"; +- arm,psci-suspend-param = <0x41000032>; +- entry-latency-us = <2000>; +- exit-latency-us = <2000>; +- min-residency-us = <6000>; +- }; +- }; +- }; +- +- cpu_opp_table: cpu-opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- }; +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- }; +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- }; +- opp-998400000 { +- opp-hz = /bits/ 64 <998400000>; +- }; +- }; +- +- firmware { +- scm: scm { +- compatible = "qcom,scm-msm8916", "qcom,scm"; +- clocks = <&gcc GCC_CRYPTO_CLK>, +- <&gcc GCC_CRYPTO_AXI_CLK>, +- <&gcc GCC_CRYPTO_AHB_CLK>; +- clock-names = "core", "bus", "iface"; +- #reset-cells = <1>; +- +- qcom,dload-mode = <&tcsr 0x6100>; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- +- CPU_PD0: power-domain-cpu0 { +- #power-domain-cells = <0>; +- power-domains = <&CLUSTER_PD>; +- domain-idle-states = <&CPU_SLEEP_0>; +- }; +- +- CPU_PD1: power-domain-cpu1 { +- #power-domain-cells = <0>; +- power-domains = <&CLUSTER_PD>; +- domain-idle-states = <&CPU_SLEEP_0>; +- }; +- +- CPU_PD2: power-domain-cpu2 { +- #power-domain-cells = <0>; +- power-domains = <&CLUSTER_PD>; +- domain-idle-states = <&CPU_SLEEP_0>; +- }; +- +- CPU_PD3: power-domain-cpu3 { +- #power-domain-cells = <0>; +- power-domains = <&CLUSTER_PD>; +- domain-idle-states = <&CPU_SLEEP_0>; +- }; +- +- CLUSTER_PD: power-domain-cluster { +- #power-domain-cells = <0>; +- domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; +- }; +- }; +- +- smd { +- compatible = "qcom,smd"; +- +- rpm { +- interrupts = ; +- qcom,ipc = <&apcs 8 0>; +- qcom,smd-edge = <15>; +- +- rpm_requests: rpm-requests { +- compatible = "qcom,rpm-msm8916"; +- qcom,smd-channels = "rpm_requests"; +- +- rpmcc: clock-controller { +- compatible = "qcom,rpmcc-msm8916"; +- #clock-cells = <1>; +- }; +- +- rpmpd: power-controller { +- compatible = "qcom,msm8916-rpmpd"; +- #power-domain-cells = <1>; +- operating-points-v2 = <&rpmpd_opp_table>; +- +- rpmpd_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- rpmpd_opp_ret: opp1 { +- opp-level = <1>; +- }; +- rpmpd_opp_svs_krait: opp2 { +- opp-level = <2>; +- }; +- rpmpd_opp_svs_soc: opp3 { +- opp-level = <3>; +- }; +- rpmpd_opp_nom: opp4 { +- opp-level = <4>; +- }; +- rpmpd_opp_turbo: opp5 { +- opp-level = <5>; +- }; +- rpmpd_opp_super_turbo: opp6 { +- opp-level = <6>; +- }; +- }; +- }; +- }; +- }; +- }; +- +- smem { +- compatible = "qcom,smem"; +- +- memory-region = <&smem_mem>; +- qcom,rpm-msg-ram = <&rpm_msg_ram>; +- +- hwlocks = <&tcsr_mutex 3>; +- }; +- +- smp2p-hexagon { +- compatible = "qcom,smp2p"; +- qcom,smem = <435>, <428>; +- +- interrupts = ; +- +- qcom,ipc = <&apcs 8 14>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <1>; +- +- hexagon_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- +- #qcom,smem-state-cells = <1>; +- }; +- +- hexagon_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-wcnss { +- compatible = "qcom,smp2p"; +- qcom,smem = <451>, <431>; +- +- interrupts = ; +- +- qcom,ipc = <&apcs 8 18>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <4>; +- +- wcnss_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- +- #qcom,smem-state-cells = <1>; +- }; +- +- wcnss_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smsm { +- compatible = "qcom,smsm"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- qcom,ipc-1 = <&apcs 8 13>; +- qcom,ipc-3 = <&apcs 8 19>; +- +- apps_smsm: apps@0 { +- reg = <0>; +- +- #qcom,smem-state-cells = <1>; +- }; +- +- hexagon_smsm: hexagon@1 { +- reg = <1>; +- interrupts = ; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- wcnss_smsm: wcnss@6 { +- reg = <6>; +- interrupts = ; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- soc: soc { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0 0xffffffff>; +- compatible = "simple-bus"; +- +- rng@22000 { +- compatible = "qcom,prng"; +- reg = <0x00022000 0x200>; +- clocks = <&gcc GCC_PRNG_AHB_CLK>; +- clock-names = "core"; +- }; +- +- restart@4ab000 { +- compatible = "qcom,pshold"; +- reg = <0x004ab000 0x4>; +- }; +- +- qfprom: qfprom@5c000 { +- compatible = "qcom,qfprom"; +- reg = <0x0005c000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- tsens_caldata: caldata@d0 { +- reg = <0xd0 0x8>; +- }; +- tsens_calsel: calsel@ec { +- reg = <0xec 0x4>; +- }; +- }; +- +- rpm_msg_ram: sram@60000 { +- compatible = "qcom,rpm-msg-ram"; +- reg = <0x00060000 0x8000>; +- }; +- +- bimc: interconnect@400000 { +- compatible = "qcom,msm8916-bimc"; +- reg = <0x00400000 0x62000>; +- #interconnect-cells = <1>; +- clock-names = "bus", "bus_a"; +- clocks = <&rpmcc RPM_SMD_BIMC_CLK>, +- <&rpmcc RPM_SMD_BIMC_A_CLK>; +- }; +- +- tsens: thermal-sensor@4a9000 { +- compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; +- reg = <0x004a9000 0x1000>, /* TM */ +- <0x004a8000 0x1000>; /* SROT */ +- nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; +- nvmem-cell-names = "calib", "calib_sel"; +- #qcom,sensors = <5>; +- interrupts = ; +- interrupt-names = "uplow"; +- #thermal-sensor-cells = <1>; +- }; +- +- pcnoc: interconnect@500000 { +- compatible = "qcom,msm8916-pcnoc"; +- reg = <0x00500000 0x11000>; +- #interconnect-cells = <1>; +- clock-names = "bus", "bus_a"; +- clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, +- <&rpmcc RPM_SMD_PCNOC_A_CLK>; +- }; +- +- snoc: interconnect@580000 { +- compatible = "qcom,msm8916-snoc"; +- reg = <0x00580000 0x14000>; +- #interconnect-cells = <1>; +- clock-names = "bus", "bus_a"; +- clocks = <&rpmcc RPM_SMD_SNOC_CLK>, +- <&rpmcc RPM_SMD_SNOC_A_CLK>; +- }; +- +- stm: stm@802000 { +- compatible = "arm,coresight-stm", "arm,primecell"; +- reg = <0x00802000 0x1000>, +- <0x09280000 0x180000>; +- reg-names = "stm-base", "stm-stimulus-base"; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- status = "disabled"; +- +- out-ports { +- port { +- stm_out: endpoint { +- remote-endpoint = <&funnel0_in7>; +- }; +- }; +- }; +- }; +- +- /* System CTIs */ +- /* CTI 0 - TMC connections */ +- cti0: cti@810000 { +- compatible = "arm,coresight-cti", "arm,primecell"; +- reg = <0x00810000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- +- status = "disabled"; +- }; +- +- /* CTI 1 - TPIU connections */ +- cti1: cti@811000 { +- compatible = "arm,coresight-cti", "arm,primecell"; +- reg = <0x00811000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- +- status = "disabled"; +- }; +- +- /* CTIs 2-11 - no information - not instantiated */ +- +- tpiu: tpiu@820000 { +- compatible = "arm,coresight-tpiu", "arm,primecell"; +- reg = <0x00820000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- status = "disabled"; +- +- in-ports { +- port { +- tpiu_in: endpoint { +- remote-endpoint = <&replicator_out1>; +- }; +- }; +- }; +- }; +- +- funnel0: funnel@821000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0x00821000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- status = "disabled"; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* +- * Not described input ports: +- * 0 - connected to Resource and Power Manger CPU ETM +- * 1 - not-connected +- * 2 - connected to Modem CPU ETM +- * 3 - not-connected +- * 5 - not-connected +- * 6 - connected trought funnel to Wireless CPU ETM +- * 7 - connected to STM component +- */ +- +- port@4 { +- reg = <4>; +- funnel0_in4: endpoint { +- remote-endpoint = <&funnel1_out>; +- }; +- }; +- +- port@7 { +- reg = <7>; +- funnel0_in7: endpoint { +- remote-endpoint = <&stm_out>; +- }; +- }; +- }; +- +- out-ports { +- port { +- funnel0_out: endpoint { +- remote-endpoint = <&etf_in>; +- }; +- }; +- }; +- }; +- +- replicator: replicator@824000 { +- compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; +- reg = <0x00824000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- status = "disabled"; +- +- out-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- replicator_out0: endpoint { +- remote-endpoint = <&etr_in>; +- }; +- }; +- port@1 { +- reg = <1>; +- replicator_out1: endpoint { +- remote-endpoint = <&tpiu_in>; +- }; +- }; +- }; +- +- in-ports { +- port { +- replicator_in: endpoint { +- remote-endpoint = <&etf_out>; +- }; +- }; +- }; +- }; +- +- etf: etf@825000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0x00825000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- status = "disabled"; +- +- in-ports { +- port { +- etf_in: endpoint { +- remote-endpoint = <&funnel0_out>; +- }; +- }; +- }; +- +- out-ports { +- port { +- etf_out: endpoint { +- remote-endpoint = <&replicator_in>; +- }; +- }; +- }; +- }; +- +- etr: etr@826000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0x00826000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- status = "disabled"; +- +- in-ports { +- port { +- etr_in: endpoint { +- remote-endpoint = <&replicator_out0>; +- }; +- }; +- }; +- }; +- +- funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */ +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0x00841000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- status = "disabled"; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- funnel1_in0: endpoint { +- remote-endpoint = <&etm0_out>; +- }; +- }; +- port@1 { +- reg = <1>; +- funnel1_in1: endpoint { +- remote-endpoint = <&etm1_out>; +- }; +- }; +- port@2 { +- reg = <2>; +- funnel1_in2: endpoint { +- remote-endpoint = <&etm2_out>; +- }; +- }; +- port@3 { +- reg = <3>; +- funnel1_in3: endpoint { +- remote-endpoint = <&etm3_out>; +- }; +- }; +- }; +- +- out-ports { +- port { +- funnel1_out: endpoint { +- remote-endpoint = <&funnel0_in4>; +- }; +- }; +- }; +- }; +- +- debug0: debug@850000 { +- compatible = "arm,coresight-cpu-debug", "arm,primecell"; +- reg = <0x00850000 0x1000>; +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- cpu = <&CPU0>; +- status = "disabled"; +- }; +- +- debug1: debug@852000 { +- compatible = "arm,coresight-cpu-debug", "arm,primecell"; +- reg = <0x00852000 0x1000>; +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- cpu = <&CPU1>; +- status = "disabled"; +- }; +- +- debug2: debug@854000 { +- compatible = "arm,coresight-cpu-debug", "arm,primecell"; +- reg = <0x00854000 0x1000>; +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- cpu = <&CPU2>; +- status = "disabled"; +- }; +- +- debug3: debug@856000 { +- compatible = "arm,coresight-cpu-debug", "arm,primecell"; +- reg = <0x00856000 0x1000>; +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- cpu = <&CPU3>; +- status = "disabled"; +- }; +- +- /* Core CTIs; CTIs 12-15 */ +- /* CTI - CPU-0 */ +- cti12: cti@858000 { +- compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", +- "arm,primecell"; +- reg = <0x00858000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- +- cpu = <&CPU0>; +- arm,cs-dev-assoc = <&etm0>; +- +- status = "disabled"; +- }; +- +- /* CTI - CPU-1 */ +- cti13: cti@859000 { +- compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", +- "arm,primecell"; +- reg = <0x00859000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- +- cpu = <&CPU1>; +- arm,cs-dev-assoc = <&etm1>; +- +- status = "disabled"; +- }; +- +- /* CTI - CPU-2 */ +- cti14: cti@85a000 { +- compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", +- "arm,primecell"; +- reg = <0x0085a000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- +- cpu = <&CPU2>; +- arm,cs-dev-assoc = <&etm2>; +- +- status = "disabled"; +- }; +- +- /* CTI - CPU-3 */ +- cti15: cti@85b000 { +- compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", +- "arm,primecell"; +- reg = <0x0085b000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- +- cpu = <&CPU3>; +- arm,cs-dev-assoc = <&etm3>; +- +- status = "disabled"; +- }; +- +- etm0: etm@85c000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0x0085c000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- arm,coresight-loses-context-with-cpu; +- +- cpu = <&CPU0>; +- +- status = "disabled"; +- +- out-ports { +- port { +- etm0_out: endpoint { +- remote-endpoint = <&funnel1_in0>; +- }; +- }; +- }; +- }; +- +- etm1: etm@85d000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0x0085d000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- arm,coresight-loses-context-with-cpu; +- +- cpu = <&CPU1>; +- +- status = "disabled"; +- +- out-ports { +- port { +- etm1_out: endpoint { +- remote-endpoint = <&funnel1_in1>; +- }; +- }; +- }; +- }; +- +- etm2: etm@85e000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0x0085e000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- arm,coresight-loses-context-with-cpu; +- +- cpu = <&CPU2>; +- +- status = "disabled"; +- +- out-ports { +- port { +- etm2_out: endpoint { +- remote-endpoint = <&funnel1_in2>; +- }; +- }; +- }; +- }; +- +- etm3: etm@85f000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0x0085f000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- arm,coresight-loses-context-with-cpu; +- +- cpu = <&CPU3>; +- +- status = "disabled"; +- +- out-ports { +- port { +- etm3_out: endpoint { +- remote-endpoint = <&funnel1_in3>; +- }; +- }; +- }; +- }; +- +- msmgpio: pinctrl@1000000 { +- compatible = "qcom,msm8916-pinctrl"; +- reg = <0x01000000 0x300000>; +- interrupts = ; +- gpio-controller; +- gpio-ranges = <&msmgpio 0 0 122>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gcc: clock-controller@1800000 { +- compatible = "qcom,gcc-msm8916"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- reg = <0x01800000 0x80000>; +- }; +- +- tcsr_mutex: hwlock@1905000 { +- compatible = "qcom,tcsr-mutex"; +- reg = <0x01905000 0x20000>; +- #hwlock-cells = <1>; +- }; +- +- tcsr: syscon@1937000 { +- compatible = "qcom,tcsr-msm8916", "syscon"; +- reg = <0x01937000 0x30000>; +- }; +- +- mdss: mdss@1a00000 { +- status = "disabled"; +- compatible = "qcom,mdss"; +- reg = <0x01a00000 0x1000>, +- <0x01ac8000 0x3000>; +- reg-names = "mdss_phys", "vbif_phys"; +- +- power-domains = <&gcc MDSS_GDSC>; +- +- clocks = <&gcc GCC_MDSS_AHB_CLK>, +- <&gcc GCC_MDSS_AXI_CLK>, +- <&gcc GCC_MDSS_VSYNC_CLK>; +- clock-names = "iface", +- "bus", +- "vsync"; +- +- interrupts = ; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- mdp: mdp@1a01000 { +- compatible = "qcom,mdp5"; +- reg = <0x01a01000 0x89000>; +- reg-names = "mdp_phys"; +- +- interrupt-parent = <&mdss>; +- interrupts = <0>; +- +- clocks = <&gcc GCC_MDSS_AHB_CLK>, +- <&gcc GCC_MDSS_AXI_CLK>, +- <&gcc GCC_MDSS_MDP_CLK>, +- <&gcc GCC_MDSS_VSYNC_CLK>; +- clock-names = "iface", +- "bus", +- "core", +- "vsync"; +- +- iommus = <&apps_iommu 4>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- mdp5_intf1_out: endpoint { +- remote-endpoint = <&dsi0_in>; +- }; +- }; +- }; +- }; +- +- dsi0: dsi@1a98000 { +- compatible = "qcom,mdss-dsi-ctrl"; +- reg = <0x01a98000 0x25c>; +- reg-names = "dsi_ctrl"; +- +- interrupt-parent = <&mdss>; +- interrupts = <4>; +- +- assigned-clocks = <&gcc BYTE0_CLK_SRC>, +- <&gcc PCLK0_CLK_SRC>; +- assigned-clock-parents = <&dsi_phy0 0>, +- <&dsi_phy0 1>; +- +- clocks = <&gcc GCC_MDSS_MDP_CLK>, +- <&gcc GCC_MDSS_AHB_CLK>, +- <&gcc GCC_MDSS_AXI_CLK>, +- <&gcc GCC_MDSS_BYTE0_CLK>, +- <&gcc GCC_MDSS_PCLK0_CLK>, +- <&gcc GCC_MDSS_ESC0_CLK>; +- clock-names = "mdp_core", +- "iface", +- "bus", +- "byte", +- "pixel", +- "core"; +- phys = <&dsi_phy0>; +- phy-names = "dsi-phy"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dsi0_in: endpoint { +- remote-endpoint = <&mdp5_intf1_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- dsi0_out: endpoint { +- }; +- }; +- }; +- }; +- +- dsi_phy0: dsi-phy@1a98300 { +- compatible = "qcom,dsi-phy-28nm-lp"; +- reg = <0x01a98300 0xd4>, +- <0x01a98500 0x280>, +- <0x01a98780 0x30>; +- reg-names = "dsi_pll", +- "dsi_phy", +- "dsi_phy_regulator"; +- +- #clock-cells = <1>; +- #phy-cells = <0>; +- +- clocks = <&gcc GCC_MDSS_AHB_CLK>, +- <&xo_board>; +- clock-names = "iface", "ref"; +- }; +- }; +- +- camss: camss@1b00000 { +- compatible = "qcom,msm8916-camss"; +- reg = <0x01b0ac00 0x200>, +- <0x01b00030 0x4>, +- <0x01b0b000 0x200>, +- <0x01b00038 0x4>, +- <0x01b08000 0x100>, +- <0x01b08400 0x100>, +- <0x01b0a000 0x500>, +- <0x01b00020 0x10>, +- <0x01b10000 0x1000>; +- reg-names = "csiphy0", +- "csiphy0_clk_mux", +- "csiphy1", +- "csiphy1_clk_mux", +- "csid0", +- "csid1", +- "ispif", +- "csi_clk_mux", +- "vfe0"; +- interrupts = , +- , +- , +- , +- , +- ; +- interrupt-names = "csiphy0", +- "csiphy1", +- "csid0", +- "csid1", +- "ispif", +- "vfe0"; +- power-domains = <&gcc VFE_GDSC>; +- clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, +- <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, +- <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, +- <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, +- <&gcc GCC_CAMSS_CSI0_AHB_CLK>, +- <&gcc GCC_CAMSS_CSI0_CLK>, +- <&gcc GCC_CAMSS_CSI0PHY_CLK>, +- <&gcc GCC_CAMSS_CSI0PIX_CLK>, +- <&gcc GCC_CAMSS_CSI0RDI_CLK>, +- <&gcc GCC_CAMSS_CSI1_AHB_CLK>, +- <&gcc GCC_CAMSS_CSI1_CLK>, +- <&gcc GCC_CAMSS_CSI1PHY_CLK>, +- <&gcc GCC_CAMSS_CSI1PIX_CLK>, +- <&gcc GCC_CAMSS_CSI1RDI_CLK>, +- <&gcc GCC_CAMSS_AHB_CLK>, +- <&gcc GCC_CAMSS_VFE0_CLK>, +- <&gcc GCC_CAMSS_CSI_VFE0_CLK>, +- <&gcc GCC_CAMSS_VFE_AHB_CLK>, +- <&gcc GCC_CAMSS_VFE_AXI_CLK>; +- clock-names = "top_ahb", +- "ispif_ahb", +- "csiphy0_timer", +- "csiphy1_timer", +- "csi0_ahb", +- "csi0", +- "csi0_phy", +- "csi0_pix", +- "csi0_rdi", +- "csi1_ahb", +- "csi1", +- "csi1_phy", +- "csi1_pix", +- "csi1_rdi", +- "ahb", +- "vfe0", +- "csi_vfe0", +- "vfe_ahb", +- "vfe_axi"; +- iommus = <&apps_iommu 3>; +- status = "disabled"; +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- cci: cci@1b0c000 { +- compatible = "qcom,msm8916-cci"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x01b0c000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, +- <&gcc GCC_CAMSS_CCI_AHB_CLK>, +- <&gcc GCC_CAMSS_CCI_CLK>, +- <&gcc GCC_CAMSS_AHB_CLK>; +- clock-names = "camss_top_ahb", "cci_ahb", +- "cci", "camss_ahb"; +- assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, +- <&gcc GCC_CAMSS_CCI_CLK>; +- assigned-clock-rates = <80000000>, <19200000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cci0_default>; +- status = "disabled"; +- +- cci_i2c0: i2c-bus@0 { +- reg = <0>; +- clock-frequency = <400000>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- gpu@1c00000 { +- compatible = "qcom,adreno-306.0", "qcom,adreno"; +- reg = <0x01c00000 0x20000>; +- reg-names = "kgsl_3d0_reg_memory"; +- interrupts = ; +- interrupt-names = "kgsl_3d0_irq"; +- clock-names = +- "core", +- "iface", +- "mem", +- "mem_iface", +- "alt_mem_iface", +- "gfx3d"; +- clocks = +- <&gcc GCC_OXILI_GFX3D_CLK>, +- <&gcc GCC_OXILI_AHB_CLK>, +- <&gcc GCC_OXILI_GMEM_CLK>, +- <&gcc GCC_BIMC_GFX_CLK>, +- <&gcc GCC_BIMC_GPU_CLK>, +- <&gcc GFX3D_CLK_SRC>; +- power-domains = <&gcc OXILI_GDSC>; +- operating-points-v2 = <&gpu_opp_table>; +- iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; +- +- gpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- }; +- opp-19200000 { +- opp-hz = /bits/ 64 <19200000>; +- }; +- }; +- }; +- +- venus: video-codec@1d00000 { +- compatible = "qcom,msm8916-venus"; +- reg = <0x01d00000 0xff000>; +- interrupts = ; +- power-domains = <&gcc VENUS_GDSC>; +- clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, +- <&gcc GCC_VENUS0_AHB_CLK>, +- <&gcc GCC_VENUS0_AXI_CLK>; +- clock-names = "core", "iface", "bus"; +- iommus = <&apps_iommu 5>; +- memory-region = <&venus_mem>; +- status = "okay"; +- +- video-decoder { +- compatible = "venus-decoder"; +- }; +- +- video-encoder { +- compatible = "venus-encoder"; +- }; +- }; +- +- apps_iommu: iommu@1ef0000 { +- #address-cells = <1>; +- #size-cells = <1>; +- #iommu-cells = <1>; +- compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; +- ranges = <0 0x01e20000 0x40000>; +- reg = <0x01ef0000 0x3000>; +- clocks = <&gcc GCC_SMMU_CFG_CLK>, +- <&gcc GCC_APSS_TCU_CLK>; +- clock-names = "iface", "bus"; +- qcom,iommu-secure-id = <17>; +- +- // vfe: +- iommu-ctx@3000 { +- compatible = "qcom,msm-iommu-v1-sec"; +- reg = <0x3000 0x1000>; +- interrupts = ; +- }; +- +- // mdp_0: +- iommu-ctx@4000 { +- compatible = "qcom,msm-iommu-v1-ns"; +- reg = <0x4000 0x1000>; +- interrupts = ; +- }; +- +- // venus_ns: +- iommu-ctx@5000 { +- compatible = "qcom,msm-iommu-v1-sec"; +- reg = <0x5000 0x1000>; +- interrupts = ; +- }; +- }; +- +- gpu_iommu: iommu@1f08000 { +- #address-cells = <1>; +- #size-cells = <1>; +- #iommu-cells = <1>; +- compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; +- ranges = <0 0x01f08000 0x10000>; +- clocks = <&gcc GCC_SMMU_CFG_CLK>, +- <&gcc GCC_GFX_TCU_CLK>; +- clock-names = "iface", "bus"; +- qcom,iommu-secure-id = <18>; +- +- // gfx3d_user: +- iommu-ctx@1000 { +- compatible = "qcom,msm-iommu-v1-ns"; +- reg = <0x1000 0x1000>; +- interrupts = ; +- }; +- +- // gfx3d_priv: +- iommu-ctx@2000 { +- compatible = "qcom,msm-iommu-v1-ns"; +- reg = <0x2000 0x1000>; +- interrupts = ; +- }; +- }; +- +- spmi_bus: spmi@200f000 { +- compatible = "qcom,spmi-pmic-arb"; +- reg = <0x0200f000 0x001000>, +- <0x02400000 0x400000>, +- <0x02c00000 0x400000>, +- <0x03800000 0x200000>, +- <0x0200a000 0x002100>; +- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; +- interrupt-names = "periph_irq"; +- interrupts = ; +- qcom,ee = <0>; +- qcom,channel = <0>; +- #address-cells = <2>; +- #size-cells = <0>; +- interrupt-controller; +- #interrupt-cells = <4>; +- }; +- +- mpss: remoteproc@4080000 { +- compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil"; +- reg = <0x04080000 0x100>, +- <0x04020000 0x040>; +- +- reg-names = "qdsp6", "rmb"; +- +- interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, +- <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack"; +- +- power-domains = <&rpmpd MSM8916_VDDCX>, +- <&rpmpd MSM8916_VDDMX>; +- power-domain-names = "cx", "mx"; +- +- clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, +- <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, +- <&gcc GCC_BOOT_ROM_AHB_CLK>, +- <&xo_board>; +- clock-names = "iface", "bus", "mem", "xo"; +- +- qcom,smem-states = <&hexagon_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- resets = <&scm 0>; +- reset-names = "mss_restart"; +- +- qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; +- +- status = "disabled"; +- +- mba { +- memory-region = <&mba_mem>; +- }; +- +- mpss { +- memory-region = <&mpss_mem>; +- }; +- +- smd-edge { +- interrupts = ; +- +- qcom,smd-edge = <0>; +- qcom,ipc = <&apcs 8 12>; +- qcom,remote-pid = <1>; +- +- label = "hexagon"; +- +- fastrpc { +- compatible = "qcom,fastrpc"; +- qcom,smd-channels = "fastrpcsmd-apps-dsp"; +- label = "adsp"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- cb@1 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <1>; +- }; +- }; +- }; +- }; +- +- sound: sound@7702000 { +- status = "disabled"; +- compatible = "qcom,apq8016-sbc-sndcard"; +- reg = <0x07702000 0x4>, <0x07702004 0x4>; +- reg-names = "mic-iomux", "spkr-iomux"; +- }; +- +- lpass: audio-controller@7708000 { +- status = "disabled"; +- compatible = "qcom,lpass-cpu-apq8016"; +- +- /* +- * Note: Unlike the name would suggest, the SEC_I2S_CLK +- * is actually only used by Tertiary MI2S while +- * Primary/Secondary MI2S both use the PRI_I2S_CLK. +- */ +- clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, +- <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, +- <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, +- <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, +- <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, +- <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, +- <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; +- +- clock-names = "ahbix-clk", +- "pcnoc-mport-clk", +- "pcnoc-sway-clk", +- "mi2s-bit-clk0", +- "mi2s-bit-clk1", +- "mi2s-bit-clk2", +- "mi2s-bit-clk3"; +- #sound-dai-cells = <1>; +- +- interrupts = ; +- interrupt-names = "lpass-irq-lpaif"; +- reg = <0x07708000 0x10000>; +- reg-names = "lpass-lpaif"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- lpass_codec: audio-codec@771c000 { +- compatible = "qcom,msm8916-wcd-digital-codec"; +- reg = <0x0771c000 0x400>; +- clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, +- <&gcc GCC_CODEC_DIGCODEC_CLK>; +- clock-names = "ahbix-clk", "mclk"; +- #sound-dai-cells = <1>; +- }; +- +- sdhc_1: sdhci@7824000 { +- compatible = "qcom,sdhci-msm-v4"; +- reg = <0x07824900 0x11c>, <0x07824000 0x800>; +- reg-names = "hc_mem", "core_mem"; +- +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- clocks = <&gcc GCC_SDCC1_APPS_CLK>, +- <&gcc GCC_SDCC1_AHB_CLK>, +- <&xo_board>; +- clock-names = "core", "iface", "xo"; +- mmc-ddr-1_8v; +- bus-width = <8>; +- non-removable; +- status = "disabled"; +- }; +- +- sdhc_2: sdhci@7864000 { +- compatible = "qcom,sdhci-msm-v4"; +- reg = <0x07864900 0x11c>, <0x07864000 0x800>; +- reg-names = "hc_mem", "core_mem"; +- +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- clocks = <&gcc GCC_SDCC2_APPS_CLK>, +- <&gcc GCC_SDCC2_AHB_CLK>, +- <&xo_board>; +- clock-names = "core", "iface", "xo"; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- blsp_dma: dma-controller@7884000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0x07884000 0x23000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- status = "disabled"; +- }; +- +- blsp1_uart1: serial@78af000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x078af000 0x200>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp_dma 1>, <&blsp_dma 0>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp1_uart1_default>; +- pinctrl-1 = <&blsp1_uart1_sleep>; +- status = "disabled"; +- }; +- +- blsp1_uart2: serial@78b0000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x078b0000 0x200>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp_dma 3>, <&blsp_dma 2>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp1_uart2_default>; +- pinctrl-1 = <&blsp1_uart2_sleep>; +- status = "disabled"; +- }; +- +- blsp_i2c1: i2c@78b5000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x078b5000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c1_default>; +- pinctrl-1 = <&i2c1_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp_spi1: spi@78b5000 { +- compatible = "qcom,spi-qup-v2.2.1"; +- reg = <0x078b5000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp_dma 5>, <&blsp_dma 4>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&spi1_default>; +- pinctrl-1 = <&spi1_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp_i2c2: i2c@78b6000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x078b6000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c2_default>; +- pinctrl-1 = <&i2c2_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp_spi2: spi@78b6000 { +- compatible = "qcom,spi-qup-v2.2.1"; +- reg = <0x078b6000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp_dma 7>, <&blsp_dma 6>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&spi2_default>; +- pinctrl-1 = <&spi2_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp_i2c3: i2c@78b7000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x078b7000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c3_default>; +- pinctrl-1 = <&i2c3_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp_spi3: spi@78b7000 { +- compatible = "qcom,spi-qup-v2.2.1"; +- reg = <0x078b7000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp_dma 9>, <&blsp_dma 8>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&spi3_default>; +- pinctrl-1 = <&spi3_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp_i2c4: i2c@78b8000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x078b8000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c4_default>; +- pinctrl-1 = <&i2c4_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp_spi4: spi@78b8000 { +- compatible = "qcom,spi-qup-v2.2.1"; +- reg = <0x078b8000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp_dma 11>, <&blsp_dma 10>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&spi4_default>; +- pinctrl-1 = <&spi4_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp_i2c5: i2c@78b9000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x078b9000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c5_default>; +- pinctrl-1 = <&i2c5_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp_spi5: spi@78b9000 { +- compatible = "qcom,spi-qup-v2.2.1"; +- reg = <0x078b9000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp_dma 13>, <&blsp_dma 12>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&spi5_default>; +- pinctrl-1 = <&spi5_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp_i2c6: i2c@78ba000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x078ba000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c6_default>; +- pinctrl-1 = <&i2c6_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp_spi6: spi@78ba000 { +- compatible = "qcom,spi-qup-v2.2.1"; +- reg = <0x078ba000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp_dma 15>, <&blsp_dma 14>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&spi6_default>; +- pinctrl-1 = <&spi6_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- usb: usb@78d9000 { +- compatible = "qcom,ci-hdrc"; +- reg = <0x078d9000 0x200>, +- <0x078d9200 0x200>; +- interrupts = , +- ; +- clocks = <&gcc GCC_USB_HS_AHB_CLK>, +- <&gcc GCC_USB_HS_SYSTEM_CLK>; +- clock-names = "iface", "core"; +- assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; +- assigned-clock-rates = <80000000>; +- resets = <&gcc GCC_USB_HS_BCR>; +- reset-names = "core"; +- phy_type = "ulpi"; +- dr_mode = "otg"; +- hnp-disable; +- srp-disable; +- adp-disable; +- ahb-burst-config = <0>; +- phy-names = "usb-phy"; +- phys = <&usb_hs_phy>; +- status = "disabled"; +- #reset-cells = <1>; +- +- ulpi { +- usb_hs_phy: phy { +- compatible = "qcom,usb-hs-phy-msm8916", +- "qcom,usb-hs-phy"; +- #phy-cells = <0>; +- clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; +- clock-names = "ref", "sleep"; +- resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; +- reset-names = "phy", "por"; +- qcom,init-seq = /bits/ 8 <0x0 0x44 +- 0x1 0x6b 0x2 0x24 0x3 0x13>; +- }; +- }; +- }; +- +- pronto: remoteproc@a21b000 { +- compatible = "qcom,pronto-v2-pil", "qcom,pronto"; +- reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; +- reg-names = "ccu", "dxe", "pmu"; +- +- memory-region = <&wcnss_mem>; +- +- interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, +- <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; +- +- power-domains = <&rpmpd MSM8916_VDDCX>, +- <&rpmpd MSM8916_VDDMX>; +- power-domain-names = "cx", "mx"; +- +- qcom,state = <&wcnss_smp2p_out 0>; +- qcom,state-names = "stop"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&wcnss_pin_a>; +- +- status = "disabled"; +- +- iris { +- compatible = "qcom,wcn3620"; +- +- clocks = <&rpmcc RPM_SMD_RF_CLK2>; +- clock-names = "xo"; +- }; +- +- smd-edge { +- interrupts = ; +- +- qcom,ipc = <&apcs 8 17>; +- qcom,smd-edge = <6>; +- qcom,remote-pid = <4>; +- +- label = "pronto"; +- +- wcnss { +- compatible = "qcom,wcnss"; +- qcom,smd-channels = "WCNSS_CTRL"; +- +- qcom,mmio = <&pronto>; +- +- bt { +- compatible = "qcom,wcnss-bt"; +- }; +- +- wifi { +- compatible = "qcom,wcnss-wlan"; +- +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- +- qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; +- qcom,smem-state-names = "tx-enable", "tx-rings-empty"; +- }; +- }; +- }; +- }; +- +- intc: interrupt-controller@b000000 { +- compatible = "qcom,msm-qgic2"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, +- <0x0b001000 0x1000>, <0x0b004000 0x2000>; +- interrupts = ; +- }; +- +- apcs: mailbox@b011000 { +- compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; +- reg = <0x0b011000 0x1000>; +- #mbox-cells = <1>; +- clocks = <&a53pll>, <&gcc GPLL0_VOTE>; +- clock-names = "pll", "aux"; +- #clock-cells = <0>; +- }; +- +- a53pll: clock@b016000 { +- compatible = "qcom,msm8916-a53pll"; +- reg = <0x0b016000 0x40>; +- #clock-cells = <0>; +- }; +- +- timer@b020000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "arm,armv7-timer-mem"; +- reg = <0x0b020000 0x1000>; +- clock-frequency = <19200000>; +- +- frame@b021000 { +- frame-number = <0>; +- interrupts = , +- ; +- reg = <0x0b021000 0x1000>, +- <0x0b022000 0x1000>; +- }; +- +- frame@b023000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0x0b023000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b024000 { +- frame-number = <2>; +- interrupts = ; +- reg = <0x0b024000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b025000 { +- frame-number = <3>; +- interrupts = ; +- reg = <0x0b025000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b026000 { +- frame-number = <4>; +- interrupts = ; +- reg = <0x0b026000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b027000 { +- frame-number = <5>; +- interrupts = ; +- reg = <0x0b027000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b028000 { +- frame-number = <6>; +- interrupts = ; +- reg = <0x0b028000 0x1000>; +- status = "disabled"; +- }; +- }; +- }; +- +- thermal-zones { +- cpu0-1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 5>; +- +- trips { +- cpu0_1_alert0: trip-point0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu0_1_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu0_1_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu2-3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 4>; +- +- trips { +- cpu2_3_alert0: trip-point0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu2_3_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu2_3_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- gpu-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 2>; +- +- trips { +- gpu_alert0: trip-point0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- gpu_crit: gpu_crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- camera-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 1>; +- +- trips { +- cam_alert0: trip-point0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- modem-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 0>; +- +- trips { +- modem_alert0: trip-point0 { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +-}; +- +-#include "msm8916-pins.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8992-bullhead-rev-101.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8992-bullhead-rev-101.dts +deleted file mode 100644 +index 1ccca83292ac..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8992-bullhead-rev-101.dts ++++ /dev/null +@@ -1,302 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* Copyright (c) 2015, LGE Inc. All rights reserved. +- * Copyright (c) 2016, The Linux Foundation. All rights reserved. +- * Copyright (c) 2021, Petr Vorel +- */ +- +-/dts-v1/; +- +-#include "msm8992.dtsi" +-#include "pm8994.dtsi" +-#include "pmi8994.dtsi" +- +-/* cont_splash_mem has different memory mapping */ +-/delete-node/ &cont_splash_mem; +- +-/ { +- model = "LG Nexus 5X"; +- compatible = "lg,bullhead", "qcom,msm8992"; +- /* required for bootloader to select correct board */ +- qcom,msm-id = <251 0>, <252 0>; +- qcom,board-id = <0xb64 0>; +- qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; +- +- /* Bullhead firmware doesn't support PSCI */ +- /delete-node/ psci; +- +- aliases { +- serial0 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ramoops@1ff00000 { +- compatible = "ramoops"; +- reg = <0x0 0x1ff00000 0x0 0x40000>; +- console-size = <0x10000>; +- record-size = <0x10000>; +- ftrace-size = <0x10000>; +- pmsg-size = <0x20000>; +- }; +- +- cont_splash_mem: memory@3400000 { +- reg = <0 0x03400000 0 0x1200000>; +- no-map; +- }; +- }; +-}; +- +-&blsp1_uart2 { +- status = "okay"; +-}; +- +-&rpm_requests { +- pm8994_regulators: pm8994-regulators { +- compatible = "qcom,rpm-pm8994-regulators"; +- +- vdd_l1-supply = <&pm8994_s1>; +- vdd_l2_26_28-supply = <&pm8994_s3>; +- vdd_l3_11-supply = <&pm8994_s3>; +- vdd_l4_27_31-supply = <&pm8994_s3>; +- vdd_l5_7-supply = <&pm8994_s3>; +- vdd_l6_12_32-supply = <&pm8994_s5>; +- vdd_l8_16_30-supply = <&vph_pwr>; +- vdd_l9_10_18_22-supply = <&vph_pwr>; +- vdd_l13_19_23_24-supply = <&vph_pwr>; +- vdd_l14_15-supply = <&pm8994_s5>; +- vdd_l17_29-supply = <&vph_pwr>; +- vdd_l20_21-supply = <&vph_pwr>; +- vdd_l25-supply = <&pm8994_s5>; +- vdd_lvs1_2 = <&pm8994_s4>; +- +- /* S1, S2, S6 and S12 are managed by RPMPD */ +- +- pm8994_s1: s1 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- }; +- +- pm8994_s2: s2 { +- /* TODO */ +- }; +- +- pm8994_s3: s3 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- }; +- +- pm8994_s4: s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-allow-set-load; +- regulator-system-load = <325000>; +- }; +- +- pm8994_s5: s5 { +- regulator-min-microvolt = <2150000>; +- regulator-max-microvolt = <2150000>; +- }; +- +- pm8994_s7: s7 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- /* S8, S9, S10 and S11 - SPMI-managed VDD_APC */ +- +- pm8994_l1: l1 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- pm8994_l2: l2 { +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- }; +- +- pm8994_l3: l3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- pm8994_l4: l4 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- /* L5 is inaccessible from RPM */ +- +- pm8994_l6: l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- /* L7 is inaccessible from RPM */ +- +- pm8994_l8: l8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l9: l9 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l10: l10 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l11: l11 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- pm8994_l12: l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l13: l13 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- pm8994_l14: l14 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- pm8994_l15: l15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l16: l16 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- pm8994_l17: l17 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- pm8994_l18: l18 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- pm8994_l19: l19 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l20: l20 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-allow-set-load; +- regulator-system-load = <570000>; +- }; +- +- pm8994_l21: l21 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- pm8994_l22: l22 { +- regulator-min-microvolt = <3100000>; +- regulator-max-microvolt = <3100000>; +- }; +- +- pm8994_l23: l23 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- pm8994_l24: l24 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3150000>; +- }; +- +- pm8994_l25: l25 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l26: l26 { +- /* TODO: value from downstream +- regulator-min-microvolt = <987500>; +- fails to apply */ +- }; +- +- pm8994_l27: l27 { +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- pm8994_l28: l28 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- pm8994_l29: l29 { +- /* TODO: Unsupported voltage range. +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- qcom,init-voltage = <2800000>; +- */ +- }; +- +- pm8994_l30: l30 { +- /* TODO: get this verified +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- qcom,init-voltage = <1800000>; +- */ +- }; +- +- pm8994_l31: l31 { +- regulator-min-microvolt = <1262500>; +- regulator-max-microvolt = <1262500>; +- }; +- +- pm8994_l32: l32 { +- /* TODO: get this verified +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- qcom,init-voltage = <1800000>; +- */ +- }; +- }; +- +- pmi8994_regulators: pmi8994-regulators { +- compatible = "qcom,rpm-pmi8994-regulators"; +- +- vdd_s1-supply = <&vph_pwr>; +- vdd_bst_byp-supply = <&vph_pwr>; +- +- pmi8994_s1: s1 {}; +- +- /* S2 & S3 - VDD_GFX */ +- +- pmi8994_bby: boost-bypass {}; +- }; +-}; +- +-&sdhc1 { +- status = "okay"; +- +- mmc-hs400-1_8v; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8992-msft-lumia-octagon-talkman.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8992-msft-lumia-octagon-talkman.dts +deleted file mode 100644 +index 5322b9ce5839..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8992-msft-lumia-octagon-talkman.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Konrad Dybcio +- * Copyright (c) 2020, Gustave Monce +- */ +- +-/dts-v1/; +- +-#include "msm8992.dtsi" +-#include "msm8994-msft-lumia-octagon.dtsi" +- +-/ { +- model = "Microsoft Lumia 950"; +- compatible = "microsoft,talkman", "qcom,msm8992"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8992-xiaomi-libra.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8992-xiaomi-libra.dts +deleted file mode 100644 +index 357d55496e75..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8992-xiaomi-libra.dts ++++ /dev/null +@@ -1,364 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Konrad Dybcio +- */ +- +-/dts-v1/; +- +-#include "msm8992.dtsi" +-#include "pm8994.dtsi" +-#include "pmi8994.dtsi" +-#include +-#include +- +-/ { +- model = "Xiaomi Mi 4C"; +- compatible = "xiaomi,libra", "qcom,msm8992"; +- /* required for bootloader to select correct board */ +- qcom,msm-id = <251 0 252 0>; +- qcom,pmic-id = <65545 65546 0 0>; +- qcom,board-id = <12 0>; +- +- /* This enables graphical output via bootloader-enabled display */ +- chosen { +- bootargs = "earlycon=tty0 console=tty0"; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- framebuffer0: framebuffer@3404000 { +- status= "okay"; +- compatible = "simple-framebuffer"; +- reg = <0 0x3404000 0 (1080 * 1920 * 3)>; +- width = <1080>; +- height = <1920>; +- stride = <(1080 * 3)>; +- format = "r8g8b8"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- input-name = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- autorepeat; +- +- button@0 { +- label = "Volume Up"; +- gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- wakeup-source; +- debounce-interval = <15>; +- }; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- /* This is for getting crash logs using Android downstream kernels */ +- ramoops@dfc00000 { +- compatible = "ramoops"; +- reg = <0x0 0xdfc00000 0x0 0x40000>; +- console-size = <0x10000>; +- record-size = <0x10000>; +- ftrace-size = <0x10000>; +- pmsg-size = <0x20000>; +- }; +- +- modem_region: modem_region@9000000 { +- reg = <0x0 0x9000000 0x0 0x5a00000>; +- no-map; +- }; +- +- tzapp: modem_region@ea00000 { +- reg = <0x0 0xea00000 0x0 0x1900000>; +- no-map; +- }; +- }; +-}; +- +-&blsp1_i2c2 { +- status = "okay"; +- +- /* Atmel or Synaptics touchscreen */ +-}; +- +-&blsp1_i2c5 { +- status = "okay"; +- +- /* ST lsm6db0 gyro/accelerometer */ +-}; +- +-&blsp1_i2c6 { +- status = "okay"; +- +- /* +- * NXP NCI NFC, +- * TI USB320 Type-C controller, +- * Pericom 30216a USB (de)mux switch +- */ +-}; +- +-&blsp2_i2c1 { +- status = "okay"; +- +- /* cm36686 proximity and ambient light sensor */ +-}; +- +-&blsp2_i2c5 { +- status = "okay"; +- +- /* Silabs si4705 FM transmitter */ +-}; +- +-&blsp2_uart2 { +- status = "okay"; +-}; +- +-&peripheral_region { +- reg = <0x0 0x7400000 0x0 0x1c00000>; +- no-map; +-}; +- +-&rpm_requests { +- pm8994-regulators { +- compatible = "qcom,rpm-pm8994-regulators"; +- +- vdd_l1-supply = <&pm8994_s7>; +- vdd_l2_26_28-supply = <&pm8994_s3>; +- vdd_l3_11-supply = <&pm8994_s3>; +- vdd_l4_27_31-supply = <&pm8994_s3>; +- vdd_l5_7-supply = <&pm8994_s3>; +- vdd_l6_12_32-supply = <&pm8994_s5>; +- vdd_l8_16_30-supply = <&vph_pwr>; +- vdd_l9_10_18_22-supply = <&vph_pwr>; +- vdd_l13_19_23_24-supply = <&vph_pwr>; +- vdd_l14_15-supply = <&pm8994_s5>; +- vdd_l17_29-supply = <&vph_pwr>; +- vdd_l20_21-supply = <&vph_pwr>; +- vdd_l25-supply = <&pm8994_s5>; +- vdd_lvs1_2 = <&pm8994_s4>; +- +- /* S1, S2, S6 and S12 are managed by RPMPD */ +- +- pm8994_s3: s3 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- }; +- +- pm8994_s4: s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-allow-set-load; +- regulator-always-on; +- regulator-system-load = <325000>; +- }; +- +- pm8994_s5: s5 { +- regulator-min-microvolt = <2150000>; +- regulator-max-microvolt = <2150000>; +- }; +- +- pm8994_s7: s7 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- /* S8, S9, S10 and S11 - SPMI-managed VDD_APC */ +- +- pm8994_l1: l1 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- pm8994_l2: l2 { +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- }; +- +- pm8994_l3: l3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- pm8994_l4: l4 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- /* L5 is inaccessible from RPM */ +- +- pm8994_l6: l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- /* L7 is inaccessible from RPM */ +- +- pm8994_l8: l8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l9: l9 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l10: l10 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l11: l11 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- pm8994_l12: l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l13: l13 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- pm8994_l14: l14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l15: l15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l16: l16 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- pm8994_l17: l17 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- pm8994_l18: l18 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- }; +- +- pm8994_l19: l19 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- pm8994_l20: l20 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-allow-set-load; +- regulator-system-load = <570000>; +- }; +- +- pm8994_l21: l21 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- regulator-always-on; +- }; +- +- pm8994_l22: l22 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- pm8994_l23: l23 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- pm8994_l24: l24 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3150000>; +- }; +- +- pm8994_l25: l25 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- pm8994_l26: l26 { +- regulator-min-microvolt = <987500>; +- regulator-max-microvolt = <987500>; +- +- }; +- +- pm8994_l27: l27 { +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- pm8994_l28: l28 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- pm8994_l29: l29 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- pm8994_l30: l30 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l31: l31 { +- regulator-min-microvolt = <1262500>; +- regulator-max-microvolt = <1262500>; +- }; +- +- pm8994_l32: l32 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_lvs1: lvs1 {}; +- pm8994_lvs2: lvs2 {}; +- }; +- +- pmi8994_regulators: pmi8994-regulators { +- compatible = "qcom,rpm-pmi8994-regulators"; +- vdd_s1-supply = <&vph_pwr>; +- vdd_bst_byp-supply = <&vph_pwr>; +- +- pmi8994_s1: s1 { +- regulator-min-microvolt = <1025000>; +- regulator-max-microvolt = <1025000>; +- }; +- +- /* S2 & S3 - VDD_GFX */ +- +- pmi8994_bby: boost-bypass { +- regulator-min-microvolt = <3150000>; +- regulator-max-microvolt = <3600000>; +- }; +- }; +-}; +- +-&sdhc1 { +- status = "okay"; +- +- mmc-hs400-1_8v; +- vmmc-supply = <&pm8994_l20>; +- vqmmc-supply = <&pm8994_s4>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8992.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/msm8992.dtsi +deleted file mode 100644 +index 58fe58cc7703..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8992.dtsi ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. +- */ +- +-#include "msm8994.dtsi" +- +-/* 8992 only features 2 A57 cores. */ +-/delete-node/ &CPU6; +-/delete-node/ &CPU7; +-/delete-node/ &cpu6_map; +-/delete-node/ &cpu7_map; +- +-&rpmcc { +- compatible = "qcom,rpmcc-msm8992"; +-}; +- +-&tcsr_mutex { +- compatible = "qcom,sfpb-mutex"; +-}; +- +-&timer { +- interrupts = , +- , +- , +- ; +-}; +- +-&tlmm { +- compatible = "qcom,msm8992-pinctrl"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8994-angler-rev-101.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8994-angler-rev-101.dts +deleted file mode 100644 +index c096b7758aa0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8994-angler-rev-101.dts ++++ /dev/null +@@ -1,42 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* Copyright (c) 2015, Huawei Inc. All rights reserved. +- * Copyright (c) 2016, The Linux Foundation. All rights reserved. +- * Copyright (c) 2021, Petr Vorel +- */ +- +-/dts-v1/; +- +-#include "msm8994.dtsi" +- +-/* Angler's firmware does not report where the memory is allocated */ +-/delete-node/ &cont_splash_mem; +- +-/ { +- model = "Huawei Nexus 6P"; +- compatible = "huawei,angler", "qcom,msm8994"; +- /* required for bootloader to select correct board */ +- qcom,msm-id = <207 0x20000>; +- qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; +- qcom,board-id = <8026 0>; +- +- aliases { +- serial0 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- soc { +- serial@f991e000 { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp1_uart2_default>; +- pinctrl-1 = <&blsp1_uart2_sleep>; +- }; +- }; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <85 4>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8994-msft-lumia-octagon-cityman.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8994-msft-lumia-octagon-cityman.dts +deleted file mode 100644 +index d0aaf5750c21..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8994-msft-lumia-octagon-cityman.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Konrad Dybcio +- * Copyright (c) 2020, Gustave Monce +- */ +- +-/dts-v1/; +- +-#include "msm8994.dtsi" +-#include "msm8994-msft-lumia-octagon.dtsi" +- +-/ { +- model = "Microsoft Lumia 950 XL"; +- compatible = "microsoft,cityman", "qcom,msm8994"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8994-msft-lumia-octagon.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/msm8994-msft-lumia-octagon.dtsi +deleted file mode 100644 +index 3a3790a52a2c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8994-msft-lumia-octagon.dtsi ++++ /dev/null +@@ -1,909 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Common Board Device Tree for +- * Microsoft Mobile MSM8994 Octagon Platforms +- * +- * Copyright (c) 2020, Konrad Dybcio +- * Copyright (c) 2020, Gustave Monce +- */ +- +-#include "pm8994.dtsi" +-#include "pmi8994.dtsi" +-#include +-#include +-#include +- +-/* +- * Delete all generic (msm8994.dtsi) reserved +- * memory mappings which are different in this device. +- */ +-/delete-node/ &adsp_mem; +-/delete-node/ &audio_mem; +-/delete-node/ &cont_splash_mem; +-/delete-node/ &mba_mem; +-/delete-node/ &mpss_mem; +-/delete-node/ &peripheral_region; +-/delete-node/ &rmtfs_mem; +-/delete-node/ &smem_mem; +- +-/ { +- /* +- * Most Lumia 950/XL users use GRUB to load their kernels, +- * hence there is no need for msm-id and friends. +- */ +- +- /* +- * This enables graphical output via bootloader-enabled display. +- * acpi=no is required due to WP platforms having ACPI support, but +- * only for Windows-based OSes. +- */ +- chosen { +- bootargs = "earlycon=efifb console=efifb acpi=no"; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- }; +- +- clocks { +- compatible = "simple-bus"; +- +- divclk4: divclk4 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- +- clock-frequency = <32768>; +- clock-output-names = "divclk4"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&divclk4_pin_a>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- input-name = "gpio-keys"; +- autorepeat; +- +- volupkey { +- label = "Volume Up"; +- gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- wakeup-source; +- debounce-interval = <15>; +- }; +- +- camsnapkey { +- label = "Camera Snapshot"; +- gpios = <&pm8994_gpios 4 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- wakeup-source; +- debounce-interval = <15>; +- }; +- +- camfocuskey { +- label = "Camera Focus"; +- gpios = <&pm8994_gpios 5 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- wakeup-source; +- debounce-interval = <15>; +- }; +- }; +- +- gpio-hall-sensor { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&hall_front_default &hall_back_default>; +- +- label = "GPIO Hall Effect Sensor"; +- +- hall-front-sensor { +- label = "Hall Effect Front Sensor"; +- gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; +- linux,input-type = ; +- linux,code = ; +- linux,can-disable; +- }; +- +- hall-back-sensor { +- label = "Hall Effect Back Sensor"; +- gpios = <&tlmm 75 GPIO_ACTIVE_HIGH>; +- linux,input-type = ; +- linux,code = ; +- linux,can-disable; +- }; +- }; +- +- reserved-memory { +- /* +- * This device being a WP platform has a very different +- * memory layout than other Android based devices. +- * This memory layout is directly copied from the original +- * device UEFI firmware, and adapted based on observations +- * using JTAG for the Qualcomm Peripheral Image regions. +- */ +- +- uefi_mem: memory@200000 { +- reg = <0 0x200000 0 0x100000>; +- no-map; +- }; +- +- mppark_mem: memory@300000 { +- reg = <0 0x300000 0 0x80000>; +- no-map; +- }; +- +- fbpt_mem: memory@380000 { +- reg = <0 0x380000 0 0x1000>; +- no-map; +- }; +- +- dbg2_mem: memory@381000 { +- reg = <0 0x381000 0 0x4000>; +- no-map; +- }; +- +- capsule_mem: memory@385000 { +- reg = <0 0x385000 0 0x1000>; +- no-map; +- }; +- +- tpmctrl_mem: memory@386000 { +- reg = <0 0x386000 0 0x3000>; +- no-map; +- }; +- +- uefiinfo_mem: memory@389000 { +- reg = <0 0x389000 0 0x1000>; +- no-map; +- }; +- +- reset_mem: memory@389000 { +- reg = <0 0x389000 0 0x1000>; +- no-map; +- }; +- +- resuncached_mem: memory@38e000 { +- reg = <0 0x38e000 0 0x72000>; +- no-map; +- }; +- +- disp_mem: memory@400000 { +- reg = <0 0x400000 0 0x800000>; +- no-map; +- }; +- +- uefistack_mem: memory@c00000 { +- reg = <0 0xc00000 0 0x40000>; +- no-map; +- }; +- +- cpuvect_mem: memory@c40000 { +- reg = <0 0xc40000 0 0x10000>; +- no-map; +- }; +- +- rescached_mem: memory@400000 { +- reg = <0 0xc50000 0 0xb0000>; +- no-map; +- }; +- +- tzapps_mem: memory@6500000 { +- reg = <0 0x6500000 0 0x500000>; +- no-map; +- }; +- +- smem_mem: memory@6a00000 { +- reg = <0 0x6a00000 0 0x200000>; +- no-map; +- }; +- +- hyp_mem: memory@6c00000 { +- reg = <0 0x6c00000 0 0x100000>; +- no-map; +- }; +- +- tz_mem: memory@6d00000 { +- reg = <0 0x6d00000 0 0x160000>; +- no-map; +- }; +- +- rfsa_adsp_mem: memory@6e60000 { +- reg = <0 0x6e60000 0 0x10000>; +- no-map; +- }; +- +- rfsa_mpss_mem: memory@6e70000 { +- compatible = "qcom,rmtfs-mem"; +- reg = <0 0x6e70000 0 0x10000>; +- no-map; +- +- qcom,client-id = <1>; +- }; +- +- /* +- * Value obtained from the device original ACPI DSDT table +- * MPSS_EFS / SBL +- */ +- mba_mem: memory@6e80000 { +- reg = <0 0x6e80000 0 0x180000>; +- no-map; +- }; +- +- /* +- * Peripheral Image loader region begin! +- * The region reserved for pil is 0x7000000-0xef00000 +- */ +- +- mpss_mem: memory@7000000 { +- reg = <0 0x7000000 0 0x5a00000>; +- no-map; +- }; +- +- adsp_mem: memory@ca00000 { +- reg = <0 0xca00000 0 0x1800000>; +- no-map; +- }; +- +- venus_mem: memory@e200000 { +- reg = <0 0xe200000 0 0x500000>; +- no-map; +- }; +- +- pil_metadata_mem: memory@e700000 { +- reg = <0 0xe700000 0 0x4000>; +- no-map; +- }; +- +- memory@e704000 { +- reg = <0 0xe704000 0 0x7fc000>; +- no-map; +- }; +- /* Peripheral Image loader region end */ +- +- cnss_mem: memory@ef00000 { +- reg = <0 0xef00000 0 0x300000>; +- no-map; +- }; +- }; +-}; +- +-&blsp1_i2c1 { +- status = "okay"; +- +- rmi4-i2c-dev@4b { +- compatible = "syna,rmi4-i2c"; +- reg = <0x4b>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <77 IRQ_TYPE_EDGE_FALLING>; +- +- rmi4-f01@1 { +- reg = <0x01>; +- syna,nosleep-mode = <1>; +- }; +- +- rmi4-f12@12 { +- reg = <0x12>; +- syna,sensor-type = <1>; +- syna,clip-x-low = <0>; +- syna,clip-x-high = <1440>; +- syna,clip-y-low = <0>; +- syna,clip-y-high = <2560>; +- }; +- }; +-}; +- +-&blsp1_i2c2 { +- status = "okay"; +- +- /* +- * This device uses the Texas Instruments TAS2553, however the TAS2552 driver +- * seems to work here. In the future a proper driver might need to +- * be written for this device. +- */ +- tas2553: tas2553@40 { +- compatible = "ti,tas2552"; +- reg = <0x40>; +- +- vbat-supply = <&vph_pwr>; +- iovdd-supply = <&vreg_s4a_1p8>; +- avdd-supply = <&vreg_s4a_1p8>; +- +- enable-gpio = <&pm8994_gpios 12 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&blsp1_i2c5 { +- status = "okay"; +- +- ak09912: magnetometer@c { +- compatible = "asahi-kasei,ak09912"; +- reg = <0xc>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <26 IRQ_TYPE_EDGE_RISING>; +- +- vdd-supply = <&vreg_l18a_2p85>; +- vid-supply = <&vreg_lvs2a_1p8>; +- }; +- +- zpa2326: barometer@5c { +- compatible = "murata,zpa2326"; +- reg = <0x5c>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <74 IRQ_TYPE_EDGE_RISING>; +- +- vdd-supply = <&vreg_lvs2a_1p8>; +- }; +- +- mpu6050: accelerometer@68 { +- compatible = "invensense,mpu6500"; +- reg = <0x68>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <64 IRQ_TYPE_EDGE_RISING>; +- +- vdd-supply = <&vreg_lvs2a_1p8>; +- vddio-supply = <&vreg_lvs2a_1p8>; +- }; +-}; +- +-&blsp1_i2c6 { +- status = "okay"; +- +- pn547: pn547@28 { +- compatible = "nxp,pn544-i2c"; +- +- reg = <0x28>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <29 IRQ_TYPE_EDGE_RISING>; +- +- enable-gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>; +- firmware-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&blsp1_uart2 { +- status = "okay"; +-}; +- +-&blsp2_i2c1 { +- status = "okay"; +- +- sideinteraction: ad7147_captouch@2c { +- compatible = "ad,ad7147_captouch"; +- reg = <0x2c>; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&grip_default>; +- pinctrl-1 = <&grip_sleep>; +- +- interrupts = <&tlmm 96 IRQ_TYPE_EDGE_FALLING>; +- +- button_num = <8>; +- touchpad_num = <0>; +- wheel_num = <0>; +- slider_num = <0>; +- +- vcc-supply = <&vreg_l18a_2p85>; +- }; +- +- /* +- * The QPDS-T900/QPDS-T930 is a customized part built for Nokia +- * by Avago. It is very similar to the Avago APDS-9930 with some +- * minor differences. In the future a proper driver might need to +- * be written for this device. For now this works fine. +- */ +- qpdst900: qpdst900@39 { +- compatible = "avago,apds9930"; +- reg = <0x39>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <40 IRQ_TYPE_EDGE_FALLING>; +- }; +-}; +- +-&blsp2_i2c5 { +- status = "okay"; +- +- fm_radio: si4705@11 { +- compatible = "silabs,si470x"; +- reg = <0x11>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <9 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&tlmm 93 GPIO_ACTIVE_HIGH>; +- }; +- +- vreg_lpddr_1p1: fan53526a@6c { +- compatible = "fcs,fan53526"; +- reg = <0x6c>; +- +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- vin-supply = <&vph_pwr>; +- fcs,suspend-voltage-selector = <1>; +- regulator-always-on; /* Turning off DDR power doesn't sound good. */ +- }; +- +- /* ANX7816 HDMI bridge (needs MDSS HDMI) */ +-}; +- +-&blsp2_spi4 { +- status = "okay"; +- +- /* +- * This device is a Lattice UC120 USB-C PD PHY. +- * It is actually a Lattice iCE40 FPGA pre-programmed by +- * the device firmware with a specific bitstream +- * enabling USB Type C PHY functionality. +- * Communication is done via a proprietary protocol over SPI. +- * +- * TODO: Once a proper driver is available, replace this. +- */ +- uc120: ice5lp2k@0 { +- compatible = "lattice,ice40-fpga-mgr"; +- reg = <0>; +- spi-max-frequency = <5000000>; +- cdone-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&pmi8994_gpios 4 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&blsp2_uart2 { +- status = "okay"; +- +- qca6174_bt: bluetooth { +- compatible = "qcom,qca6174-bt"; +- +- enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>; +- clocks = <&divclk4>; +- }; +-}; +- +-&pm8994_gpios { +- bt_en_gpios: bt_en_gpios { +- pinconf { +- pins = "gpio19"; +- function = PMIC_GPIO_FUNC_NORMAL; +- output-low; +- power-source = ; +- qcom,drive-strength = ; +- bias-pull-down; +- }; +- }; +- +- divclk4_pin_a: divclk4 { +- pinconf { +- pins = "gpio18"; +- function = PMIC_GPIO_FUNC_FUNC2; +- power-source = ; +- bias-disable; +- }; +- }; +-}; +- +-&pm8994_pon { +- pwrkey { +- compatible = "qcom,pm8941-pwrkey"; +- interrupts = <0 8 0 IRQ_TYPE_EDGE_BOTH>; +- debounce = <15625>; +- linux,code = ; +- }; +- +- volwnkey { +- compatible = "qcom,pm8941-resin"; +- interrupts = <0 8 1 IRQ_TYPE_EDGE_BOTH>; +- debounce = <15625>; +- linux,code = ; +- }; +-}; +- +-&pmi8994_gpios { +- pinctrl-0 = <&hd3ss460_pol &hd3ss460_amsel &hd3ss460_en>; +- pinctrl-names = "default"; +- +- /* +- * This device uses a TI HD3SS460 Type-C MUX +- * As this device has no driver currently, +- * the configuration for USB Face Up is set-up here. +- * +- * TODO: remove once a driver is available +- * TODO: add VBUS GPIO 5 +- */ +- hd3ss460_pol: pol_low { +- pins = "gpio8"; +- drive-strength = <3>; +- bias-pull-down; +- }; +- +- hd3ss460_amsel: amsel_high { +- pins = "gpio9"; +- drive-strength = <1>; +- bias-pull-up; +- }; +- +- hd3ss460_en: en_high { +- pins = "gpio10"; +- drive-strength = <1>; +- bias-pull-up; +- }; +-}; +- +-&pmi8994_spmi_regulators { +- vdd_gfx: s2@1700 { +- reg = <0x1700 0x100>; +- regulator-min-microvolt = <980000>; +- regulator-max-microvolt = <980000>; +- }; +-}; +- +-&rpm_requests { +- /* These values were taken from the original firmware ACPI tables */ +- pm8994_regulators: pm8994-regulators { +- compatible = "qcom,rpm-pm8994-regulators"; +- +- vdd_s1-supply = <&vph_pwr>; +- vdd_s2-supply = <&vph_pwr>; +- vdd_s3-supply = <&vph_pwr>; +- vdd_s4-supply = <&vph_pwr>; +- vdd_s5-supply = <&vph_pwr>; +- vdd_s6-supply = <&vph_pwr>; +- vdd_s7-supply = <&vph_pwr>; +- vdd_s8-supply = <&vph_pwr>; +- vdd_s9-supply = <&vph_pwr>; +- vdd_s10-supply = <&vph_pwr>; +- vdd_s11-supply = <&vph_pwr>; +- vdd_s12-supply = <&vph_pwr>; +- vdd_l1-supply = <&vreg_s1b_1p0>; +- vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>; +- vdd_l3_l11-supply = <&vreg_s3a_1p3>; +- vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>; +- vdd_l5_l7-supply = <&vreg_s5a_2p15>; +- vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>; +- vdd_l8_l16_l30-supply = <&vph_pwr>; +- vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>; +- vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>; +- vdd_l14_l15-supply = <&vreg_s5a_2p15>; +- vdd_l17_l29-supply = <&vph_pwr_bbyp>; +- vdd_l20_l21-supply = <&vph_pwr_bbyp>; +- vdd_l25-supply = <&vreg_s5a_2p15>; +- vdd_lvs1_2-supply = <&vreg_s4a_1p8>; +- +- /* S1, S2, S6 and S12 are managed by RPMPD */ +- +- vreg_s3a_1p3: s3 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- regulator-allow-set-load; +- regulator-system-load = <300000>; +- }; +- +- vreg_s4a_1p8: s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-allow-set-load; +- regulator-always-on; +- regulator-system-load = <325000>; +- }; +- +- vreg_s5a_2p15: s5 { +- regulator-min-microvolt = <2150000>; +- regulator-max-microvolt = <2150000>; +- regulator-allow-set-load; +- regulator-system-load = <325000>; +- }; +- +- vreg_s7a_1p0: s7 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- /* +- * S8 - SPMI-managed VDD_APC0 +- * S9, S10 and S11 (the main one) - SPMI-managed VDD_APC1 +- */ +- +- vreg_l1a_1p0: l1 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- vreg_l2a_1p25: l2 { +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- regulator-allow-set-load; +- regulator-system-load = <4160>; +- }; +- +- vreg_l3a_1p2: l3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-allow-set-load; +- regulator-system-load = <80000>; +- }; +- +- vreg_l4a_1p225: l4 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- /* L5 is inaccessible from RPM */ +- +- vreg_l6a_1p8: l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-allow-set-load; +- regulator-system-load = <1000>; +- }; +- +- /* L7 is inaccessible from RPM */ +- +- vreg_l8a_1p8: l8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vreg_l9a_1p8: l9 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vreg_l10a_1p8: l10 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vreg_l11a_1p2: l11 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-allow-set-load; +- regulator-system-load = <35000>; +- }; +- +- vreg_l12a_1p8: l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-allow-set-load; +- regulator-system-load = <50000>; +- }; +- +- vreg_l13a_2p95: l13 { +- regulator-min-microvolt = <1850000>; +- regulator-max-microvolt = <2950000>; +- regulator-always-on; +- regulator-allow-set-load; +- regulator-system-load = <22000>; +- }; +- +- vreg_l14a_1p8: l14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-allow-set-load; +- regulator-system-load = <52000>; +- }; +- +- vreg_l15a_1p8: l15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vreg_l16a_2p7: l16 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- vreg_l17a_2p7: l17 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- regulator-allow-set-load; +- regulator-system-load = <300000>; +- }; +- +- vreg_l18a_2p85: l18 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- regulator-allow-set-load; +- regulator-system-load = <600000>; +- }; +- +- vreg_l19a_3p3: l19 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-allow-set-load; +- regulator-system-load = <500000>; +- }; +- +- vreg_l20a_2p95: l20 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-allow-set-load; +- regulator-system-load = <570000>; +- }; +- +- vreg_l21a_2p95: l21 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- regulator-always-on; +- regulator-allow-set-load; +- regulator-system-load = <800000>; +- }; +- +- vreg_l22a_3p0: l22 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-allow-set-load; +- regulator-system-load = <150000>; +- }; +- +- vreg_l23a_2p8: l23 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- regulator-allow-set-load; +- regulator-system-load = <80000>; +- }; +- +- vreg_l24a_3p075: l24 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3150000>; +- regulator-allow-set-load; +- regulator-system-load = <5800>; +- }; +- +- vreg_l25a_1p1: l25 { +- regulator-min-microvolt = <1150000>; +- regulator-max-microvolt = <1150000>; +- regulator-always-on; +- regulator-allow-set-load; +- regulator-system-load = <80000>; +- }; +- +- vreg_l26a_1p0: l26 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- vreg_l27a_1p05: l27 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-allow-set-load; +- regulator-system-load = <500000>; +- }; +- +- vreg_l28a_1p0: l28 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-allow-set-load; +- regulator-system-load = <26000>; +- }; +- +- vreg_l29a_2p8: l29 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- regulator-allow-set-load; +- regulator-system-load = <80000>; +- }; +- +- vreg_l30a_1p8: l30 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-allow-set-load; +- regulator-system-load = <2500>; +- }; +- +- vreg_l31a_1p2: l31 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- regulator-allow-set-load; +- regulator-system-load = <600000>; +- }; +- +- vreg_l32a_1p8: l32 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vreg_lvs1a_1p8: lvs1 { }; +- +- vreg_lvs2a_1p8: lvs2 { }; +- }; +- +- pmi8994_regulators: pmi8994-regulators { +- compatible = "qcom,rpm-pmi8994-regulators"; +- +- vdd_s1-supply = <&vph_pwr>; +- vdd_bst_byp-supply = <&vph_pwr>; +- +- vreg_s1b_1p0: s1 { +- regulator-min-microvolt = <1025000>; +- regulator-max-microvolt = <1025000>; +- }; +- +- /* S2 & S3 - VDD_GFX */ +- +- vph_pwr_bbyp: boost-bypass { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +-}; +- +-&sdhc1 { +- status = "okay"; +- +- /* +- * This device is shipped with HS400 capabable eMMCs +- * However various brands have been used in various product batches, +- * including a Samsung eMMC (BGND3R) which features a quirk with HS400. +- * Set the speed to HS200 as a safety measure. +- */ +- mmc-hs200-1_8v; +-}; +- +-&sdhc2 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; +- pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; +- +- vmmc-supply = <&vreg_l21a_2p95>; +- vqmmc-supply = <&vreg_l13a_2p95>; +- +- cd-gpios = <&pm8994_gpios 8 GPIO_ACTIVE_LOW>; +-}; +- +-&tlmm { +- grip_default: grip-default { +- pins = "gpio39"; +- function = "gpio"; +- drive-strength = <6>; +- bias-pull-down; +- }; +- +- grip_sleep: grip-sleep { +- pins = "gpio39"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- hall_front_default: hall-front-default { +- pins = "gpio42"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- hall_back_default: hall-back-default { +- pins = "gpio75"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8994-sony-xperia-kitakami-ivy.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8994-sony-xperia-kitakami-ivy.dts +deleted file mode 100644 +index b5e90c85aaf6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8994-sony-xperia-kitakami-ivy.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Konrad Dybcio +- */ +- +-/dts-v1/; +- +-#include "msm8994-sony-xperia-kitakami.dtsi" +- +-/ { +- model = "Sony Xperia Z3+/Z4"; +- compatible = "sony,ivy-row", "qcom,msm8994"; +-}; +- +-&pm8994_l3 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +-}; +- +-&pm8994_l17 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +-}; +- +-/delete-node/ &pm8994_l19; +-/delete-node/ &pm8994_l32; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8994-sony-xperia-kitakami-karin.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8994-sony-xperia-kitakami-karin.dts +deleted file mode 100644 +index a1d1a075941a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8994-sony-xperia-kitakami-karin.dts ++++ /dev/null +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Konrad Dybcio +- */ +- +-/dts-v1/; +- +-#include "msm8994-sony-xperia-kitakami.dtsi" +- +-/ { +- model = "Sony Xperia Z4 Tablet (LTE)"; +- compatible = "sony,karin-row", "qcom,msm8994"; +-}; +- +-&blsp2_i2c5 { +- /* +- * TI LP8557 backlight driver @ 2c +- * AD AD7146 touch controller @ 2f +- * sii8620 HDMI/MHL bridge @ 72 (kitakami-common) +- */ +-}; +- +-&pm8994_l3 { +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +-}; +- +-&pm8994_l17 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +-}; +- +-&pm8994_l22 { +- regulator-min-microvolt = <3100000>; +- regulator-max-microvolt = <3100000>; +-}; +- +-&pm8994_l25 { +- regulator-min-microvolt = <1037500>; +- regulator-max-microvolt = <1037500>; +-}; +- +-/delete-node/ &pm8994_l32; +-/* Z4 tablets use a different touchscreen. */ +-/delete-node/ &touchscreen; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8994-sony-xperia-kitakami-satsuki.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8994-sony-xperia-kitakami-satsuki.dts +deleted file mode 100644 +index 1385956a69f3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8994-sony-xperia-kitakami-satsuki.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Konrad Dybcio +- */ +- +-/dts-v1/; +- +-#include "msm8994-sony-xperia-kitakami.dtsi" +- +-/ { +- model = "Sony Xperia Z5 Premium"; +- compatible = "sony,satsuki-row", "qcom,msm8994"; +-}; +- +-&pm8994_l14 { +- regulator-min-microvolt = <1850000>; +- regulator-max-microvolt = <1850000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8994-sony-xperia-kitakami-sumire.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8994-sony-xperia-kitakami-sumire.dts +deleted file mode 100644 +index d3ba9867a369..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8994-sony-xperia-kitakami-sumire.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Konrad Dybcio +- */ +- +-/dts-v1/; +- +-#include "msm8994-sony-xperia-kitakami.dtsi" +- +-/ { +- model = "Sony Xperia Z5"; +- compatible = "sony,sumire-row", "qcom,msm8994"; +-}; +- +-/delete-node/ &pm8994_l19; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8994-sony-xperia-kitakami-suzuran.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8994-sony-xperia-kitakami-suzuran.dts +deleted file mode 100644 +index f129479bbf95..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8994-sony-xperia-kitakami-suzuran.dts ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Konrad Dybcio +- */ +- +-/dts-v1/; +- +-#include "msm8994-sony-xperia-kitakami.dtsi" +- +-/ { +- model = "Sony Xperia Z5 Compact"; +- compatible = "sony,suzuran-row", "qcom,msm8994"; +-}; +- +-&pm8994_l14 { +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +-}; +- +-/delete-node/ &pm8994_l19; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8994-sony-xperia-kitakami.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/msm8994-sony-xperia-kitakami.dtsi +deleted file mode 100644 +index 48de66bf19c4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8994-sony-xperia-kitakami.dtsi ++++ /dev/null +@@ -1,497 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Konrad Dybcio +- */ +- +-#include "msm8994.dtsi" +-#include "pm8994.dtsi" +-#include "pmi8994.dtsi" +-#include +-#include +- +-/ { +- /* required for bootloader to select correct board */ +- +- /* +- * We support MSM8994 v2 (0x20000) and v2.1 (0x20001). +- * The V1 chip (0x0 and 0x10000) is significantly different +- * and requires driver-side changes (including CPR, be warned!!). +- * Besides that, it's very rare. +- */ +- qcom,msm-id = <207 0x20000>, <207 0x20001>; +- /* We only use pm8994+pmi8994. */ +- qcom,pmic-id = <0x10009 0x1000a 0x00 0x00>; +- /* This property is shared across all kitakami devices. */ +- qcom,board-id = <8 0>; +- +- /* Kitakami firmware doesn't support PSCI */ +- /delete-node/ psci; +- +- gpio_keys { +- compatible = "gpio-keys"; +- input-name = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- autorepeat; +- +- button@0 { +- label = "Volume Down"; +- gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- wakeup-source; +- debounce-interval = <15>; +- }; +- +- button@1 { +- label = "Volume Up"; +- gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- wakeup-source; +- debounce-interval = <15>; +- }; +- +- button@2 { +- label = "Camera Snapshot"; +- gpios = <&pm8994_gpios 4 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- wakeup-source; +- debounce-interval = <15>; +- }; +- +- button@3 { +- label = "Camera Focus"; +- gpios = <&pm8994_gpios 5 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- wakeup-source; +- debounce-interval = <15>; +- }; +- }; +- +- reserved-memory { +- /* This is for getting crash logs using Android downstream kernels */ +- ramoops@1fe00000 { +- compatible = "ramoops"; +- reg = <0 0x1fe00000 0 0x200000>; +- console-size = <0x100000>; +- record-size = <0x10000>; +- ftrace-size = <0x10000>; +- pmsg-size = <0x80000>; +- }; +- +- fb_region: fb_region@40000000 { +- reg = <0 0x40000000 0 0x1000000>; +- no-map; +- }; +- +- tzapp: memory@c7800000 { +- reg = <0 0xc7800000 0 0x1900000>; +- no-map; +- }; +- }; +-}; +- +-&blsp1_spi1 { +- status = "okay"; +- +- /* FPC fingerprint reader */ +-}; +- +-/* I2C1 is disabled on this board */ +- +-&blsp1_i2c2 { +- status = "okay"; +- clock-frequency = <355000>; +- +- /* NXP PN547 NFC */ +-}; +- +-&blsp1_i2c4 { +- status = "okay"; +- clock-frequency = <355000>; +- +- /* Empty but active */ +-}; +- +-&blsp1_i2c6 { +- status = "okay"; +- clock-frequency = <355000>; +- +- touchscreen: rmi4-i2c-dev@2c { +- compatible = "syna,rmi4-i2c"; +- reg = <0x2c>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <42 IRQ_TYPE_EDGE_FALLING>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&ts_int_active &ts_reset_active>; +- +- vdd-supply = <&pm8994_l22>; +- vio-supply = <&pm8994_s4>; +- +- syna,reset-delay-ms = <220>; +- syna,startup-delay-ms = <220>; +- +- rmi4-f01@1 { +- reg = <0x01>; +- syna,nosleep-mode = <1>; +- }; +- +- rmi4-f11@11 { +- reg = <0x11>; +- syna,sensor-type = <1>; +- }; +- }; +-}; +- +-&blsp1_uart2 { +- status = "okay"; +-}; +- +-&blsp2_i2c5 { +- status = "okay"; +- clock-frequency = <355000>; +- +- /* sii8620 HDMI/MHL bridge */ +-}; +- +-&blsp2_uart2 { +- status = "okay"; +-}; +- +-/* +- * Kitakami bootloader only turns cont_splash on when it detects +- * specific downstream MDSS/backlight nodes in the active DTB. +- * One way to use that framebuffer is to load a secondary instance of +- * LK with the downstream DTB appended and then, only from there, load +- * mainline Linux. +- */ +-&cont_splash_mem { +- reg = <0 0x3401000 0 0x2200000>; +-}; +- +-&pmi8994_spmi_regulators { +- /* +- * Yeah, this one *is* managed by RPMPD, but also needs +- * to be hacked up as a-o due to the GPU device only accepting a single +- * power domain.. which still isn't enough and forces us to bind +- * OXILI_CX and OXILI_GX together! +- */ +- vdd_gfx: s2@1700 { +- reg = <0x1700 0x100>; +- regulator-name = "VDD_GFX"; +- regulator-min-microvolt = <980000>; +- regulator-max-microvolt = <980000>; +- +- /* hack until we rig up the gpu consumer */ +- regulator-always-on; +- }; +-}; +- +-&rpm_requests { +- pm8994_regulators: pm8994-regulators { +- compatible = "qcom,rpm-pm8994-regulators"; +- +- vdd_s1-supply = <&vph_pwr>; +- vdd_s2-supply = <&vph_pwr>; +- vdd_s3-supply = <&vph_pwr>; +- vdd_s4-supply = <&vph_pwr>; +- vdd_s5-supply = <&vph_pwr>; +- vdd_s6-supply = <&vph_pwr>; +- vdd_s7-supply = <&vph_pwr>; +- vdd_s8-supply = <&vph_pwr>; +- vdd_s9-supply = <&vph_pwr>; +- vdd_s10-supply = <&vph_pwr>; +- vdd_s11-supply = <&vph_pwr>; +- vdd_s12-supply = <&vph_pwr>; +- vdd_l1-supply = <&pmi8994_s1>; +- vdd_l2_l26_l28-supply = <&pm8994_s3>; +- vdd_l3_l11-supply = <&pm8994_s3>; +- vdd_l4_l27_l31-supply = <&pm8994_s3>; +- vdd_l5_l7-supply = <&pm8994_s5>; +- vdd_l6_l12_l32-supply = <&pm8994_s5>; +- vdd_l8_l16_l30-supply = <&vph_pwr>; +- vdd_l9_l10_l18_l22-supply = <&pmi8994_bby>; +- vdd_l13_l19_l23_l24-supply = <&pmi8994_bby>; +- vdd_l14_l15-supply = <&pm8994_s5>; +- vdd_l17_l29-supply = <&pmi8994_bby>; +- vdd_l20_l21-supply = <&pmi8994_bby>; +- vdd_l25-supply = <&pm8994_s3>; +- vdd_lvs1_lvs2-supply = <&pm8994_s4>; +- +- /* S1, S2, S6 and S12 are managed by RPMPD */ +- +- pm8994_s3: s3 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- }; +- +- pm8994_s4: s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-allow-set-load; +- regulator-always-on; +- regulator-system-load = <325000>; +- }; +- +- pm8994_s5: s5 { +- regulator-min-microvolt = <2150000>; +- regulator-max-microvolt = <2150000>; +- }; +- +- pm8994_s7: s7 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- /* +- * S8 - SPMI-managed VDD_APC0 +- * S9, S10 and S11 (the main one) - SPMI-managed VDD_APC1 +- */ +- +- pm8994_l1: l1 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- pm8994_l2: l2 { +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- regulator-allow-set-load; +- regulator-system-load = <10000>; +- }; +- +- pm8994_l3: l3 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- pm8994_l4: l4 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- /* L5 is inaccessible from RPM */ +- +- pm8994_l6: l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- /* L7 is inaccessible from RPM */ +- +- pm8994_l8: l8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l9: l9 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l10: l10 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l11: l11 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- pm8994_l12: l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-allow-set-load; +- regulator-system-load = <10000>; +- }; +- +- pm8994_l13: l13 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- pm8994_l14: l14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-allow-set-load; +- regulator-system-load = <10000>; +- }; +- +- pm8994_l15: l15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l16: l16 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- pm8994_l17: l17 { +- regulator-min-microvolt = <2200000>; +- regulator-max-microvolt = <2200000>; +- }; +- +- pm8994_l18: l18 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- regulator-always-on; +- }; +- +- pm8994_l19: l19 { +- regulator-min-microvolt = <2850000>; +- regulator-max-microvolt = <2850000>; +- }; +- +- pm8994_l20: l20 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-allow-set-load; +- regulator-system-load = <570000>; +- }; +- +- pm8994_l21: l21 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- regulator-always-on; +- regulator-allow-set-load; +- regulator-system-load = <800000>; +- }; +- +- pm8994_l22: l22 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- pm8994_l23: l23 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- }; +- +- pm8994_l24: l24 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3150000>; +- }; +- +- pm8994_l25: l25 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- pm8994_l26: l26 { +- regulator-min-microvolt = <987500>; +- regulator-max-microvolt = <987500>; +- }; +- +- pm8994_l27: l27 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- pm8994_l28: l28 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-allow-set-load; +- regulator-system-load = <10000>; +- }; +- +- pm8994_l29: l29 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- pm8994_l30: l30 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l31: l31 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-allow-set-load; +- regulator-system-load = <10000>; +- }; +- +- pm8994_l32: l32 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_lvs1: lvs1 {}; +- pm8994_lvs2: lvs2 {}; +- }; +- +- pmi8994_regulators: pmi8994-regulators { +- compatible = "qcom,rpm-pmi8994-regulators"; +- +- vdd_s1-supply = <&vph_pwr>; +- vdd_bst_byp-supply = <&vph_pwr>; +- +- pmi8994_s1: s1 { +- regulator-min-microvolt = <1025000>; +- regulator-max-microvolt = <1025000>; +- }; +- +- /* S2 & S3 - VDD_GFX */ +- +- pmi8994_bby: boost-bypass { +- regulator-min-microvolt = <3150000>; +- regulator-max-microvolt = <3600000>; +- }; +- }; +-}; +- +-&sdhc1 { +- /* +- * There is an issue with the eMMC causing permanent +- * damage to the card if a quirk isn't addressed. +- * Until it's fixed, disable the MMC so as not to brick +- * devices. +- */ +- status = "disabled"; +- +- /* +- * Downstream pushes 2.95V to the sdhci device, +- * but upstream driver REALLY wants to make vmmc 1.8v +- * cause of the hs400-1_8v mode. MMC works fine without +- * that regulator, so let's not use it for now. +- * vqmmc is also disabled cause driver stll complains. +- * +- * vmmc-supply = <&pm8994_l20>; +- * vqmmc-supply = <&pm8994_s4>; +- */ +-}; +- +-&sdhc2 { +- status = "okay"; +- +- cd-gpios = <&tlmm 100 0>; +- vmmc-supply = <&pm8994_l21>; +- vqmmc-supply = <&pm8994_l13>; +-}; +- +-&tlmm { +- ts_int_active: ts-int-active { +- pins = "gpio42"; +- drive-strength = <2>; +- bias-disable; +- input-enable; +- }; +- +- ts_reset_active: ts-reset-active { +- pins = "gpio109"; +- drive-strength = <2>; +- bias-disable; +- output-low; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8994.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/msm8994.dtsi +deleted file mode 100644 +index 5a9a5ed0565f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8994.dtsi ++++ /dev/null +@@ -1,1032 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. +- */ +- +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&intc>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- chosen { }; +- +- clocks { +- xo_board: xo-board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <19200000>; +- clock-output-names = "xo_board"; +- }; +- +- sleep_clk: sleep-clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "sleep_clk"; +- }; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- CPU0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- next-level-cache = <&L2_0>; +- L2_0: l2-cache { +- compatible = "cache"; +- cache-level = <2>; +- }; +- }; +- +- CPU1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- next-level-cache = <&L2_0>; +- }; +- +- CPU2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- next-level-cache = <&L2_0>; +- }; +- +- CPU3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- next-level-cache = <&L2_0>; +- }; +- +- CPU4: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- next-level-cache = <&L2_1>; +- L2_1: l2-cache { +- compatible = "cache"; +- cache-level = <2>; +- }; +- }; +- +- CPU5: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x0 0x101>; +- enable-method = "psci"; +- next-level-cache = <&L2_1>; +- }; +- +- CPU6: cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x0 0x101>; +- enable-method = "psci"; +- next-level-cache = <&L2_1>; +- }; +- +- CPU7: cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57"; +- reg = <0x0 0x101>; +- enable-method = "psci"; +- next-level-cache = <&L2_1>; +- }; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&CPU0>; +- }; +- +- core1 { +- cpu = <&CPU1>; +- }; +- +- core2 { +- cpu = <&CPU2>; +- }; +- +- core3 { +- cpu = <&CPU3>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&CPU4>; +- }; +- +- core1 { +- cpu = <&CPU5>; +- }; +- +- cpu6_map: core2 { +- cpu = <&CPU6>; +- }; +- +- cpu7_map: core3 { +- cpu = <&CPU7>; +- }; +- }; +- }; +- }; +- +- firmware { +- scm { +- compatible = "qcom,scm-msm8994", "qcom,scm"; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- /* We expect the bootloader to fill in the reg */ +- reg = <0 0x80000000 0 0>; +- }; +- +- tcsr_mutex: hwlock { +- compatible = "qcom,tcsr-mutex"; +- syscon = <&tcsr_mutex_regs 0 0x80>; +- #hwlock-cells = <1>; +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "hvc"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- dfps_data_mem: dfps_data_mem@3400000 { +- reg = <0 0x03400000 0 0x1000>; +- no-map; +- }; +- +- cont_splash_mem: memory@3800000 { +- reg = <0 0x03800000 0 0x2400000>; +- no-map; +- }; +- +- smem_mem: smem_region@6a00000 { +- reg = <0 0x06a00000 0 0x200000>; +- no-map; +- }; +- +- mpss_mem: memory@7000000 { +- reg = <0 0x07000000 0 0x5a00000>; +- no-map; +- }; +- +- peripheral_region: memory@ca00000 { +- reg = <0 0x0ca00000 0 0x1f00000>; +- no-map; +- }; +- +- rmtfs_mem: memory@c6400000 { +- compatible = "qcom,rmtfs-mem"; +- reg = <0 0xc6400000 0 0x180000>; +- no-map; +- +- qcom,client-id = <1>; +- }; +- +- mba_mem: memory@c6700000 { +- reg = <0 0xc6700000 0 0x100000>; +- no-map; +- }; +- +- audio_mem: memory@c7000000 { +- reg = <0 0xc7000000 0 0x800000>; +- no-map; +- }; +- +- adsp_mem: memory@c9400000 { +- reg = <0 0xc9400000 0 0x3f00000>; +- no-map; +- }; +- }; +- +- smd { +- compatible = "qcom,smd"; +- rpm { +- interrupts = ; +- qcom,ipc = <&apcs 8 0>; +- qcom,smd-edge = <15>; +- qcom,local-pid = <0>; +- qcom,remote-pid = <6>; +- +- rpm_requests: rpm-requests { +- compatible = "qcom,rpm-msm8994"; +- qcom,smd-channels = "rpm_requests"; +- +- rpmcc: rpmcc { +- compatible = "qcom,rpmcc-msm8994"; +- #clock-cells = <1>; +- }; +- +- rpmpd: power-controller { +- compatible = "qcom,msm8994-rpmpd"; +- #power-domain-cells = <1>; +- operating-points-v2 = <&rpmpd_opp_table>; +- +- rpmpd_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- rpmpd_opp_ret: opp1 { +- opp-level = <1>; +- }; +- rpmpd_opp_svs_krait: opp2 { +- opp-level = <2>; +- }; +- rpmpd_opp_svs_soc: opp3 { +- opp-level = <3>; +- }; +- rpmpd_opp_nom: opp4 { +- opp-level = <4>; +- }; +- rpmpd_opp_turbo: opp5 { +- opp-level = <5>; +- }; +- rpmpd_opp_super_turbo: opp6 { +- opp-level = <6>; +- }; +- }; +- }; +- }; +- }; +- }; +- +- smem { +- compatible = "qcom,smem"; +- memory-region = <&smem_mem>; +- qcom,rpm-msg-ram = <&rpm_msg_ram>; +- hwlocks = <&tcsr_mutex 3>; +- }; +- +- smp2p-lpass { +- compatible = "qcom,smp2p"; +- qcom,smem = <443>, <429>; +- +- interrupts = ; +- +- qcom,ipc = <&apcs 8 10>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <2>; +- +- adsp_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- adsp_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-modem { +- compatible = "qcom,smp2p"; +- qcom,smem = <435>, <428>; +- +- interrupt-parent = <&intc>; +- interrupts = ; +- +- qcom,ipc = <&apcs 8 14>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <1>; +- +- modem_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- modem_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- soc: soc { +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0 0xffffffff>; +- compatible = "simple-bus"; +- +- intc: interrupt-controller@f9000000 { +- compatible = "qcom,msm-qgic2"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0xf9000000 0x1000>, +- <0xf9002000 0x1000>; +- }; +- +- apcs: mailbox@f900d000 { +- compatible = "qcom,msm8994-apcs-kpss-global", "syscon"; +- reg = <0xf900d000 0x2000>; +- #mbox-cells = <1>; +- }; +- +- timer@f9020000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "arm,armv7-timer-mem"; +- reg = <0xf9020000 0x1000>; +- +- frame@f9021000 { +- frame-number = <0>; +- interrupts = , +- ; +- reg = <0xf9021000 0x1000>, +- <0xf9022000 0x1000>; +- }; +- +- frame@f9023000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0xf9023000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9024000 { +- frame-number = <2>; +- interrupts = ; +- reg = <0xf9024000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9025000 { +- frame-number = <3>; +- interrupts = ; +- reg = <0xf9025000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9026000 { +- frame-number = <4>; +- interrupts = ; +- reg = <0xf9026000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9027000 { +- frame-number = <5>; +- interrupts = ; +- reg = <0xf9027000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f9028000 { +- frame-number = <6>; +- interrupts = ; +- reg = <0xf9028000 0x1000>; +- status = "disabled"; +- }; +- }; +- +- usb3: usb@f92f8800 { +- compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; +- reg = <0xf92f8800 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clocks = <&gcc GCC_USB30_MASTER_CLK>, +- <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, +- <&gcc GCC_USB30_SLEEP_CLK>, +- <&gcc GCC_USB30_MOCK_UTMI_CLK>; +- clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo"; +- +- assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_MASTER_CLK>; +- assigned-clock-rates = <19200000>, <120000000>; +- +- power-domains = <&gcc USB30_GDSC>; +- qcom,select-utmi-as-pipe-clk; +- +- usb@f9200000 { +- compatible = "snps,dwc3"; +- reg = <0xf9200000 0xcc00>; +- interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; +- snps,dis_u2_susphy_quirk; +- snps,dis_enblslpm_quirk; +- maximum-speed = "high-speed"; +- dr_mode = "peripheral"; +- }; +- }; +- +- sdhc1: sdhci@f9824900 { +- compatible = "qcom,sdhci-msm-v4"; +- reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; +- reg-names = "hc_mem", "core_mem"; +- +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- +- clocks = <&gcc GCC_SDCC1_APPS_CLK>, +- <&gcc GCC_SDCC1_AHB_CLK>, +- <&xo_board>; +- clock-names = "core", "iface", "xo"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; +- pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; +- +- bus-width = <8>; +- non-removable; +- status = "disabled"; +- }; +- +- sdhc2: sdhci@f98a4900 { +- compatible = "qcom,sdhci-msm-v4"; +- reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; +- reg-names = "hc_mem", "core_mem"; +- +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- +- clocks = <&gcc GCC_SDCC2_APPS_CLK>, +- <&gcc GCC_SDCC2_AHB_CLK>, +- <&xo_board>; +- clock-names = "core", "iface", "xo"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; +- pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; +- +- cd-gpios = <&tlmm 100 0>; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- blsp1_dma: dma-controller@f9904000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0xf9904000 0x19000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- qcom,controlled-remotely; +- num-channels = <18>; +- qcom,num-ees = <4>; +- }; +- +- blsp1_uart2: serial@f991e000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0xf991e000 0x1000>; +- interrupts = ; +- clock-names = "core", "iface"; +- clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp1_uart2_default>; +- pinctrl-1 = <&blsp1_uart2_sleep>; +- status = "disabled"; +- }; +- +- blsp1_i2c1: i2c@f9923000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0xf9923000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- clock-frequency = <400000>; +- dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c1_default>; +- pinctrl-1 = <&i2c1_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp1_spi1: spi@f9923000 { +- compatible = "qcom,spi-qup-v2.2.1"; +- reg = <0xf9923000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- spi-max-frequency = <19200000>; +- dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp1_spi1_default>; +- pinctrl-1 = <&blsp1_spi1_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp1_i2c2: i2c@f9924000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0xf9924000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- clock-frequency = <400000>; +- dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c2_default>; +- pinctrl-1 = <&i2c2_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- /* I2C3 doesn't exist */ +- +- blsp1_i2c4: i2c@f9926000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0xf9926000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- clock-frequency = <400000>; +- dmas = <&blsp1_dma 18>, <&blsp1_dma 19>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c4_default>; +- pinctrl-1 = <&i2c4_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp1_i2c5: i2c@f9927000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0xf9927000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- clock-frequency = <400000>; +- dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c5_default>; +- pinctrl-1 = <&i2c5_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp1_i2c6: i2c@f9928000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0xf9928000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- clock-frequency = <400000>; +- dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c6_default>; +- pinctrl-1 = <&i2c6_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp2_dma: dma-controller@f9944000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0xf9944000 0x19000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- qcom,controlled-remotely; +- num-channels = <18>; +- qcom,num-ees = <4>; +- }; +- +- blsp2_uart2: serial@f995e000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0xf995e000 0x1000>; +- interrupts = ; +- clock-names = "core", "iface"; +- clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, +- <&gcc GCC_BLSP2_AHB_CLK>; +- dmas = <&blsp2_dma 2>, <&blsp2_dma 3>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp2_uart2_default>; +- pinctrl-1 = <&blsp2_uart2_sleep>; +- status = "disabled"; +- }; +- +- blsp2_i2c1: i2c@f9963000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0xf9963000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_AHB_CLK>, +- <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- clock-frequency = <400000>; +- dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c7_default>; +- pinctrl-1 = <&i2c7_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp2_spi4: spi@f9966000 { +- compatible = "qcom,spi-qup-v2.2.1"; +- reg = <0xf9966000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, +- <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- spi-max-frequency = <19200000>; +- dmas = <&blsp2_dma 18>, <&blsp2_dma 19>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp2_spi10_default>; +- pinctrl-1 = <&blsp2_spi10_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp2_i2c5: i2c@f9967000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0xf9967000 0x500>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_AHB_CLK>, +- <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- clock-frequency = <355000>; +- dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c11_default>; +- pinctrl-1 = <&i2c11_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- gcc: clock-controller@fc400000 { +- compatible = "qcom,gcc-msm8994"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- reg = <0xfc400000 0x2000>; +- }; +- +- rpm_msg_ram: sram@fc428000 { +- compatible = "qcom,rpm-msg-ram"; +- reg = <0xfc428000 0x4000>; +- }; +- +- restart@fc4ab000 { +- compatible = "qcom,pshold"; +- reg = <0xfc4ab000 0x4>; +- }; +- +- spmi_bus: spmi@fc4c0000 { +- compatible = "qcom,spmi-pmic-arb"; +- reg = <0xfc4cf000 0x1000>, +- <0xfc4cb000 0x1000>, +- <0xfc4ca000 0x1000>; +- reg-names = "core", "intr", "cnfg"; +- interrupt-names = "periph_irq"; +- interrupts = ; +- qcom,ee = <0>; +- qcom,channel = <0>; +- #address-cells = <2>; +- #size-cells = <0>; +- interrupt-controller; +- #interrupt-cells = <4>; +- }; +- +- tcsr_mutex_regs: syscon@fd484000 { +- compatible = "syscon"; +- reg = <0xfd484000 0x2000>; +- }; +- +- tlmm: pinctrl@fd510000 { +- compatible = "qcom,msm8994-pinctrl"; +- reg = <0xfd510000 0x4000>; +- interrupts = ; +- gpio-controller; +- gpio-ranges = <&tlmm 0 0 146>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- blsp1_uart2_default: blsp1-uart2-default { +- function = "blsp_uart2"; +- pins = "gpio4", "gpio5"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- blsp1_uart2_sleep: blsp1-uart2-sleep { +- function = "gpio"; +- pins = "gpio4", "gpio5"; +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- blsp2_uart2_default: blsp2-uart2-default { +- function = "blsp_uart8"; +- pins = "gpio45", "gpio46", +- "gpio47", "gpio48"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- blsp2_uart2_sleep: blsp2-uart2-sleep { +- function = "gpio"; +- pins = "gpio45", "gpio46", +- "gpio47", "gpio48"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c1_default: i2c1-default { +- function = "blsp_i2c1"; +- pins = "gpio2", "gpio3"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c1_sleep: i2c1-sleep { +- function = "gpio"; +- pins = "gpio2", "gpio3"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c2_default: i2c2-default { +- function = "blsp_i2c2"; +- pins = "gpio6", "gpio7"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c2_sleep: i2c2-sleep { +- function = "gpio"; +- pins = "gpio6", "gpio7"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c4_default: i2c4-default { +- function = "blsp_i2c4"; +- pins = "gpio19", "gpio20"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c4_sleep: i2c4-sleep { +- function = "gpio"; +- pins = "gpio19", "gpio20"; +- drive-strength = <2>; +- bias-pull-down; +- input-enable; +- }; +- +- i2c5_default: i2c5-default { +- function = "blsp_i2c5"; +- pins = "gpio23", "gpio24"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c5_sleep: i2c5-sleep { +- function = "gpio"; +- pins = "gpio23", "gpio24"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c6_default: i2c6-default { +- function = "blsp_i2c6"; +- pins = "gpio28", "gpio27"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c6_sleep: i2c6-sleep { +- function = "gpio"; +- pins = "gpio28", "gpio27"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c7_default: i2c7-default { +- function = "blsp_i2c7"; +- pins = "gpio44", "gpio43"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c7_sleep: i2c7-sleep { +- function = "gpio"; +- pins = "gpio44", "gpio43"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- blsp2_spi10_default: blsp2-spi10-default { +- default { +- function = "blsp_spi10"; +- pins = "gpio53", "gpio54", "gpio55"; +- drive-strength = <10>; +- bias-pull-down; +- }; +- cs { +- function = "gpio"; +- pins = "gpio55"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- blsp2_spi10_sleep: blsp2-spi10-sleep { +- pins = "gpio53", "gpio54", "gpio55"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c11_default: i2c11-default { +- function = "blsp_i2c11"; +- pins = "gpio83", "gpio84"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c11_sleep: i2c11-sleep { +- function = "gpio"; +- pins = "gpio83", "gpio84"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- blsp1_spi1_default: blsp1-spi1-default { +- default { +- function = "blsp_spi1"; +- pins = "gpio0", "gpio1", "gpio3"; +- drive-strength = <10>; +- bias-pull-down; +- }; +- cs { +- function = "gpio"; +- pins = "gpio8"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- blsp1_spi1_sleep: blsp1-spi1-sleep { +- pins = "gpio0", "gpio1", "gpio3"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- sdc1_clk_on: clk-on { +- pins = "sdc1_clk"; +- bias-disable; +- drive-strength = <16>; +- }; +- +- sdc1_clk_off: clk-off { +- pins = "sdc1_clk"; +- bias-disable; +- drive-strength = <2>; +- }; +- +- sdc1_cmd_on: cmd-on { +- pins = "sdc1_cmd"; +- bias-pull-up; +- drive-strength = <8>; +- }; +- +- sdc1_cmd_off: cmd-off { +- pins = "sdc1_cmd"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- sdc1_data_on: data-on { +- pins = "sdc1_data"; +- bias-pull-up; +- drive-strength = <8>; +- }; +- +- sdc1_data_off: data-off { +- pins = "sdc1_data"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- sdc1_rclk_on: rclk-on { +- pins = "sdc1_rclk"; +- bias-pull-down; +- }; +- +- sdc1_rclk_off: rclk-off { +- pins = "sdc1_rclk"; +- bias-pull-down; +- }; +- +- sdc2_clk_on: sdc2-clk-on { +- pins = "sdc2_clk"; +- bias-disable; +- drive-strength = <10>; +- }; +- +- sdc2_clk_off: sdc2-clk-off { +- pins = "sdc2_clk"; +- bias-disable; +- drive-strength = <2>; +- }; +- +- sdc2_cmd_on: sdc2-cmd-on { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- sdc2_cmd_off: sdc2-cmd-off { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- sdc2_data_on: sdc2-data-on { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- sdc2_data_off: sdc2-data-off { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +- }; +- +- timer: timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- +- regulator-min-microvolt = <3600000>; +- regulator-max-microvolt = <3600000>; +- +- regulator-always-on; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-mtp.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8996-mtp.dts +deleted file mode 100644 +index 45ed594c1b9c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-mtp.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "msm8996-mtp.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. MSM 8996 MTP"; +- compatible = "qcom,msm8996-mtp"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-mtp.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/msm8996-mtp.dtsi +deleted file mode 100644 +index ac43a91f1104..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-mtp.dtsi ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. +- */ +- +-#include "msm8996.dtsi" +- +-/ { +- aliases { +- serial0 = &blsp2_uart2; +- }; +- +- chosen { +- stdout-path = "serial0"; +- }; +- +- soc { +- serial@75b0000 { +- status = "okay"; +- }; +- }; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_phy { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dts +deleted file mode 100644 +index b018693600a5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dts ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Konrad Dybcio +- */ +- +-#include "msm8996-sony-xperia-tone-dora.dts" +-#include "pmi8996.dtsi" +- +-/ { +- model = "Sony Xperia X Performance (PMI8996)"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dts +deleted file mode 100644 +index 842ea3cf557e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dts ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Konrad Dybcio +- */ +- +-#include "msm8996-sony-xperia-tone-kagura.dts" +-#include "pmi8996.dtsi" +- +-/ { +- model = "Sony Xperia XZ (PMI8996)"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dts +deleted file mode 100644 +index b3f9062da4b0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dts ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Konrad Dybcio +- */ +- +-#include "msm8996-sony-xperia-tone-keyaki.dts" +-#include "pmi8996.dtsi" +- +-/ { +- model = "Sony Xperia XZs (PMI8996)"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-sony-xperia-tone-dora.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8996-sony-xperia-tone-dora.dts +deleted file mode 100644 +index b4cca54dcb68..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-sony-xperia-tone-dora.dts ++++ /dev/null +@@ -1,27 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, AngeloGioacchino Del Regno +- * +- * Copyright (c) 2021, Konrad Dybcio +- */ +- +-/dts-v1/; +- +-#include "msm8996-sony-xperia-tone.dtsi" +- +-/ { +- model = "Sony Xperia X Performance"; +- compatible = "sony,dora-row", "qcom,msm8996"; +-}; +- +-/delete-node/ &tof_sensor; +-/delete-node/ &pm8994_l11; +-/delete-node/ &pm8994_l14; +- +-&usb_detect { +- pins = "gpio24"; +-}; +- +-&usb3_id { +- id-gpio = <&tlmm 24 GPIO_ACTIVE_LOW>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-sony-xperia-tone-kagura.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8996-sony-xperia-tone-kagura.dts +deleted file mode 100644 +index be6ea855fcce..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-sony-xperia-tone-kagura.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, AngeloGioacchino Del Regno +- * +- * Copyright (c) 2021, Konrad Dybcio +- */ +- +-/dts-v1/; +- +-#include "msm8996-sony-xperia-tone.dtsi" +- +-/ { +- model = "Sony Xperia XZ"; +- compatible = "sony,kagura-row", "qcom,msm8996"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-sony-xperia-tone-keyaki.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8996-sony-xperia-tone-keyaki.dts +deleted file mode 100644 +index 1eee7d0fc178..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-sony-xperia-tone-keyaki.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, AngeloGioacchino Del Regno +- * +- * Copyright (c) 2021, Konrad Dybcio +- */ +- +-/dts-v1/; +- +-#include "msm8996-sony-xperia-tone.dtsi" +- +-/ { +- model = "Sony Xperia XZs"; +- compatible = "sony,keyaki-row", "qcom,msm8996"; +-}; +- +-&pm8994_l19 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +-}; +- +-&pm8994_l30 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-pull-down; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-sony-xperia-tone.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/msm8996-sony-xperia-tone.dtsi +deleted file mode 100644 +index 507396c4d23b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-sony-xperia-tone.dtsi ++++ /dev/null +@@ -1,956 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, AngeloGioacchino Del Regno +- * +- * Copyright (c) 2021, Konrad Dybcio +- */ +- +-#include "msm8996.dtsi" +-#include "pm8994.dtsi" +-#include "pmi8994.dtsi" +-#include +-#include +-#include +-#include +- +-/delete-node/ &slpi_region; +-/delete-node/ &venus_region; +-/delete-node/ &zap_shader_region; +- +-/ { +- qcom,msm-id = <246 0x30001>; /* MSM8996 V3.1 (Final) */ +- qcom,pmic-id = <0x20009 0x2000a 0 0>; /* PM8994 + PMI8994 */ +- qcom,board-id = <8 0>; +- +- chosen { +- /* +- * Due to an unknown-for-a-few-years regression, +- * SDHCI only works on MSM8996 in PIO (lame) mode. +- */ +- bootargs = "sdhci.debug_quirks=0x40 sdhci.debug_quirks2=0x4 maxcpus=2"; +- }; +- +- reserved-memory { +- ramoops@a7f00000 { +- compatible = "ramoops"; +- reg = <0 0xa7f00000 0 0x100000>; +- record-size = <0x20000>; +- console-size = <0x40000>; +- ftrace-size = <0x20000>; +- pmsg-size = <0x20000>; +- ecc-size = <16>; +- }; +- +- cont_splash_mem: memory@83401000 { +- reg = <0 0x83401000 0 0x23ff000>; +- no-map; +- }; +- +- zap_shader_region: gpu@90400000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x90400000 0x0 0x2000>; +- no-map; +- }; +- +- slpi_region: memory@90500000 { +- reg = <0 0x90500000 0 0xa00000>; +- no-map; +- }; +- +- venus_region: memory@90f00000 { +- reg = <0 0x90f00000 0 0x500000>; +- no-map; +- }; +- }; +- +- panel_tvdd: tvdd-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "panel_tvdd"; +- gpio = <&tlmm 50 GPIO_ACTIVE_LOW>; +- pinctrl-0 = <&tp_vddio_en>; +- pinctrl-names = "default"; +- }; +- +- usb3_id: usb3-id { +- compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&tlmm 25 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_detect>; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- regulator-name = "vph_pwr"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- wlan_en: wlan-en-1-8v { +- compatible = "regulator-fixed"; +- regulator-name = "wlan-en-regulator"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&wl_reg_on>; +- +- /* WLAN card specific delay */ +- startup-delay-us = <70000>; +- enable-active-high; +- }; +-}; +- +-&blsp1_i2c3 { +- status = "okay"; +- clock-frequency = <355000>; +- +- tof_sensor: vl53l0x@29 { +- compatible = "st,vl53l0x"; +- reg = <0x29>; +- }; +-}; +- +-&blsp1_uart2 { +- status = "okay"; +-}; +- +-&blsp2_i2c5 { +- status = "okay"; +- clock-frequency = <355000>; +- +- /* FUSB301 USB-C controller */ +-}; +- +-&blsp2_i2c6 { +- status = "okay"; +- clock-frequency = <355000>; +- +- synaptics@2c { +- compatible = "syna,rmi4-i2c"; +- reg = <0x2c>; +- interrupt-parent = <&tlmm>; +- interrupts = <125 IRQ_TYPE_EDGE_FALLING>; +- vdd-supply = <&panel_tvdd>; +- +- syna,reset-delay-ms = <220>; +- syna,startup-delay-ms = <220>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rmi4-f01@1 { +- reg = <0x1>; +- syna,nosleep-mode = <1>; +- }; +- +- rmi4-f11@11 { +- reg = <0x11>; +- syna,sensor-type = <1>; +- }; +- }; +-}; +- +-&blsp2_uart2 { +- status = "okay"; +-}; +- +-&camera0_mclk { +- drive-strength = <2>; +- output-low; +-}; +- +-&camera0_pwdn { +- drive-strength = <2>; +- output-low; +-}; +- +-&camera0_rst { +- pins = "gpio30"; +- drive-strength = <2>; +- output-low; +-}; +- +-&camera2_mclk { +- drive-strength = <2>; +- output-low; +-}; +- +-&camera2_rst { +- drive-strength = <2>; +- output-low; +-}; +- +-&hsusb_phy1 { +- status = "okay"; +- +- vdda-pll-supply = <&pm8994_l12>; +- vdda-phy-dpdm-supply = <&pm8994_l24>; +-}; +- +-&mmcc { +- vdd-gfx-supply = <&vdd_gfx>; +-}; +- +-&pcie0 { +- status = "okay"; +- perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>; +- wake-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; +- vddpe-3v3-supply = <&wlan_en>; +- vdda-supply = <&pm8994_l28>; +-}; +- +-&pcie_phy { +- status = "okay"; +- +- vdda-phy-supply = <&pm8994_l28>; +- vdda-pll-supply = <&pm8994_l12>; +-}; +- +-&pm8994_gpios { +- pinctrl-names = "default"; +- pinctrl-0 = <&pm8994_gpios_defaults>; +- gpio-line-names = +- "NC", +- "VOL_DOWN_N", +- "VOL_UP_N", +- "SNAPSHOT_N", +- "FOCUS_N", +- "NC", +- "NFC_VEN", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "EAR_EN", +- "NC", +- "PM_DIVCLK1", +- "PMI_CLK", +- "NC", +- "WL_SLEEP_CLK", +- "NC", +- "PMIC_SPON", +- "UIM_BATT_ALARM", +- "PMK_SLEEP_CLK"; +- +- /* +- * We don't yet know for sure which GPIOs are of our interest, but what +- * we do know is that if a vendor sets the pins to a non-default state, there's +- * probably a reason for it, and just to be on the safe side, we follow suit. +- */ +- pm8994_gpios_defaults: pm8994-gpios-default-state { +- pm8994-gpio1-nc { +- pins = "gpio1"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- bias-high-impedance; +- }; +- +- vol-down-n { +- pins = "gpio2"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- input-enable; +- bias-pull-up; +- qcom,drive-strength = ; +- power-source = ; +- }; +- +- vol-up-n { +- pins = "gpio3"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- input-enable; +- bias-pull-up; +- power-source = ; +- }; +- +- camera-snapshot-n { +- pins = "gpio4"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- input-enable; +- bias-pull-up; +- qcom,drive-strength = ; +- power-source = ; +- }; +- +- camera-focus-n { +- pins = "gpio5"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- input-enable; +- bias-pull-up; +- qcom,drive-strength = ; +- power-source = ; +- }; +- +- pm8994-gpio6-nc { +- pins = "gpio6"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- bias-high-impedance; +- power-source = ; +- }; +- +- nfc-download { +- pins = "gpio7"; +- function = PMIC_GPIO_FUNC_NORMAL; +- output-low; +- drive-push-pull; +- bias-disable; +- qcom,drive-strength = ; +- power-source = ; +- }; +- +- pm8994-gpio8-nc { +- pins = "gpio8"; +- function = PMIC_GPIO_FUNC_NORMAL; +- output-low; +- drive-push-pull; +- bias-high-impedance; +- qcom,drive-strength = ; +- power-source = ; +- }; +- +- pm8994-gpio9-nc { +- pins = "gpio9"; +- function = PMIC_GPIO_FUNC_NORMAL; +- output-high; +- drive-push-pull; +- bias-high-impedance; +- qcom,drive-strength = ; +- power-source = ; +- }; +- +- nfc-clock { +- pins = "gpio10"; +- function = PMIC_GPIO_FUNC_NORMAL; +- input-enable; +- drive-push-pull; +- bias-pull-down; +- qcom,drive-strength = ; +- power-source = ; +- }; +- +- pm8994-gpio11-nc { +- pins = "gpio11"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- bias-high-impedance; +- power-source = ; +- }; +- +- pm8994-gpio12-nc { +- pins = "gpio12"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- bias-high-impedance; +- power-source = ; +- }; +- +- ear-enable { +- pins = "gpio13"; +- function = PMIC_GPIO_FUNC_NORMAL; +- output-high; +- drive-push-pull; +- bias-disable; +- qcom,drive-strength = ; +- power-source = ; +- }; +- +- pm8994-gpio14-nc { +- pins = "gpio14"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- input-enable; +- bias-high-impedance; +- qcom,drive-strength = ; +- power-source = ; +- }; +- +- pm-divclk1-gpio { +- pins = "gpio15"; +- function = "func1"; +- output-high; +- drive-push-pull; +- bias-high-impedance; +- qcom,drive-strength = ; +- power-source = ; +- }; +- +- pmi-clk-gpio { +- pins = "gpio16"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- }; +- +- pm8994-gpio17-nc { +- pins = "gpio17"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- bias-high-impedance; +- power-source = ; +- }; +- +- rome-sleep { +- pins = "gpio18"; +- function = PMIC_GPIO_FUNC_FUNC2; +- output-low; +- drive-push-pull; +- bias-disable; +- qcom,drive-strength = ; +- power-source = ; +- }; +- +- pm8994-gpio19-nc { +- pins = "gpio19"; +- function = PMIC_GPIO_FUNC_NORMAL; +- output-low; +- drive-push-pull; +- bias-high-impedance; +- qcom,drive-strength = ; +- power-source = ; +- }; +- +- pm8994-gpio22-nc { +- pins = "gpio22"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- bias-high-impedance; +- power-source = ; +- }; +- }; +-}; +- +-&pm8994_mpps { +- pinctrl-names = "default"; +- pinctrl-0 = <&pm8994_mpps_defaults>; +- +- gpio-line-names = +- "SDC_UIM_VBIAS", +- "LCD_ID_ADC", +- "VREF_DACX", +- "NC", +- "FLASH_THERM", +- "NC", +- "NC", +- "RF_ID"; +- +- pm8994_mpps_defaults: pm8994-mpps-default-state { +- lcd-id_adc-mpp { +- pins = "mpp2"; +- function = "analog"; +- input-enable; +- qcom,amux-route = ; +- }; +- +- pm-mpp4-nc { +- pins = "mpp4"; +- function = "digital"; +- bias-high-impedance; +- power-source = ; +- }; +- +- flash-therm-mpp { +- pins = "mpp5"; +- function = "analog"; +- input-enable; +- qcom,amux-route = ; +- }; +- +- mpp6-nc { +- pins = "mpp6"; +- function = "digital"; +- bias-high-impedance; +- }; +- +- rf-id-mpp { +- pins = "mpp8"; +- function = "analog"; +- input-enable; +- qcom,amux-route = ; +- }; +- }; +-}; +- +-&pm8994_resin { +- status = "okay"; +- linux,code = ; +-}; +- +-&pmi8994_gpios { +- pinctrl-names = "default"; +- pinctrl-0 = <&pmi8994_gpios_defaults>; +- +- gpio-line-names = +- "VIB_LDO_EN", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "NC", +- "USB_SWITCH_SEL", +- "NC"; +- +- pmi8994_gpios_defaults: pmi8994-gpios-default-state { +- vib-ldo-en-gpio { +- pins = "gpio1"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- output-low; +- bias-disable; +- power-source = ; +- }; +- +- pmi-gpio2-nc { +- pins = "gpio2"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- input-enable; +- bias-high-impedance; +- qcom,drive-strength = ; +- power-source = ; +- }; +- +- pmi-gpio3-nc { +- pins = "gpio3"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- input-enable; +- bias-high-impedance; +- qcom,drive-strength = ; +- power-source = ; +- }; +- +- pmi-gpio4-nc { +- pins = "gpio4"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- output-high; +- qcom,drive-strength = ; +- power-source = ; +- }; +- +- pmi-gpio5-nc { +- pins = "gpio5"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- output-high; +- qcom,drive-strength = ; +- power-source = ; +- }; +- +- pmi-gpio6-nc { +- pins = "gpio6"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- output-high; +- qcom,drive-strength = ; +- power-source = ; +- }; +- +- pmi-gpio7-nc { +- pins = "gpio7"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- output-high; +- qcom,drive-strength = ; +- power-source = ; +- }; +- +- pmi-gpio8-nc { +- pins = "gpio8"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- output-high; +- qcom,drive-strength = ; +- power-source = ; +- }; +- +- usb-switch-sel { +- pins = "gpio9"; +- function = PMIC_GPIO_FUNC_NORMAL; +- drive-push-pull; +- }; +- +- pmi-gpio10-nc { +- pins = "gpio10"; +- function = PMIC_GPIO_FUNC_NORMAL; +- output-low; +- drive-push-pull; +- bias-disable; +- qcom,drive-strength = ; +- power-source = ; +- }; +- }; +-}; +- +-&pmi8994_spmi_regulators { +- qcom,saw-reg = <&saw3>; +- +- vdd_gfx: +- pmi8994_s2: s2 { +- /* Pinned to a high value for now to avoid random crashes. */ +- regulator-min-microvolt = <1015000>; +- regulator-max-microvolt = <1015000>; +- regulator-name = "vdd_gfx"; +- regulator-always-on; +- }; +- +- pmi8994_s9: s9 { +- qcom,saw-slave; +- }; +- +- pmi8994_s10: s10 { +- qcom,saw-slave; +- }; +- +- pmi8994_s11: s11 { +- qcom,saw-leader; +- regulator-always-on; +- regulator-min-microvolt = <470000>; +- regulator-max-microvolt = <1140000>; +- }; +-}; +- +-&pmi8994_wled { +- status = "okay"; +- default-brightness = <512>; +-}; +- +-&rpm_requests { +- pm8994-regulators { +- compatible = "qcom,rpm-pm8994-regulators"; +- +- vdd_s1-supply = <&vph_pwr>; +- vdd_s2-supply = <&vph_pwr>; +- vdd_s3-supply = <&vph_pwr>; +- vdd_s4-supply = <&vph_pwr>; +- vdd_s5-supply = <&vph_pwr>; +- vdd_s6-supply = <&vph_pwr>; +- vdd_s7-supply = <&vph_pwr>; +- vdd_s8-supply = <&vph_pwr>; +- vdd_s9-supply = <&vph_pwr>; +- vdd_s10-supply = <&vph_pwr>; +- vdd_s11-supply = <&vph_pwr>; +- vdd_s12-supply = <&vph_pwr>; +- vdd_l1-supply = <&pm8994_s3>; +- vdd_l2_l26_l28-supply = <&pm8994_s3>; +- vdd_l3_l11-supply = <&pm8994_s3>; +- vdd_l4_l27_l31-supply = <&pm8994_s3>; +- vdd_l5_l7-supply = <&pm8994_s5>; +- vdd_l6_l12_l32-supply = <&pm8994_s5>; +- vdd_l8_l16_l30-supply = <&vph_pwr>; +- vdd_l14_l15-supply = <&pm8994_s5>; +- vdd_l20_l21-supply = <&pm8994_s5>; +- vdd_l25-supply = <&pm8994_s3>; +- vdd_lvs1_2-supply = <&pm8994_s4>; +- +- pm8994_s3: s3 { +- regulator-min-microvolt = <1300000>; +- regulator-max-microvolt = <1300000>; +- }; +- +- pm8994_s4: s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-system-load = <325000>; +- regulator-always-on; +- }; +- +- pm8994_s5: s5 { +- regulator-min-microvolt = <2150000>; +- regulator-max-microvolt = <2150000>; +- }; +- +- pm8994_s7: s7 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- }; +- +- pm8994_l1: l1 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- pm8994_l2: l2 { +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- }; +- +- pm8994_l3: l3 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- pm8994_l4: l4 { +- regulator-min-microvolt = <1225000>; +- regulator-max-microvolt = <1225000>; +- }; +- +- /* L6 and L7 seem unused. */ +- +- pm8994_l8: l8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l9: l9 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l10: l10 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l11: l11 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- pm8994_l12: l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-allow-set-load; +- }; +- +- pm8994_l13: l13 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- regulator-system-load = <22000>; +- regulator-allow-set-load; +- }; +- +- pm8994_l14: l14 { +- regulator-min-microvolt = <1700000>; +- regulator-max-microvolt = <1900000>; +- }; +- +- pm8994_l15: l15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l16: l16 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- pm8994_l17: l17 { +- regulator-min-microvolt = <2200000>; +- regulator-max-microvolt = <2500000>; +- }; +- +- pm8994_l18: l18 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- pm8994_l19: l19 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- pm8994_l20: l20 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- regulator-system-load = <570000>; +- regulator-allow-set-load; +- }; +- +- pm8994_l21: l21 { +- regulator-min-microvolt = <2950000>; +- regulator-max-microvolt = <2950000>; +- regulator-system-load = <800000>; +- regulator-allow-set-load; +- }; +- +- pm8994_l22: l22 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- pm8994_l23: l23 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- pm8994_l24: l24 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3075000>; +- regulator-allow-set-load; +- }; +- +- pm8994_l25: l25 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-allow-set-load; +- }; +- +- pm8994_l27: l27 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- pm8994_l28: l28 { +- regulator-min-microvolt = <925000>; +- regulator-max-microvolt = <925000>; +- regulator-allow-set-load; +- }; +- +- pm8994_l29: l29 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- }; +- +- pm8994_l30: l30 { }; +- +- pm8994_l32: l32 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- }; +-}; +- +-&sdhc1 { +- /* eMMC doesn't seem to cooperate even in PIO mode.. */ +- status = "disabled"; +- +- vmmc-supply = <&pm8994_l20>; +- vqmmc-supply = <&pm8994_s4>; +- mmc-hs400-1_8v; +- mmc-hs200-1_8v; +-}; +- +-&sdhc2 { +- status = "okay"; +- +- cd-gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>; +- vmmc-supply = <&pm8994_l21>; +- vqmmc-supply = <&pm8994_l13>; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <0 4>; +- pinctrl-0 = <&sw_service_gpio>; +- pinctrl-names = "default"; +- +- disp_reset_n_gpio: disp-reset-n { +- pins = "gpio8"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- mdp_vsync_p_gpio: mdp-vsync-p { +- pins = "gpio10"; +- function = "mdp_vsync"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- sw_service_gpio: sw-service-gpio { +- pins = "gpio16"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- usb_detect: usb-detect { +- pins = "gpio25"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- output-high; +- }; +- +- uim_detect_en: uim-detect-en { +- pins = "gpio29"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- output-high; +- }; +- +- tray_det_pin: tray-det { +- pins = "gpio40"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- tp_vddio_en: tp-vddio-en { +- pins = "gpio50"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- output-high; +- }; +- +- lcd_vddio_en: lcd-vddio-en { +- pins = "gpio51"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- output-low; +- }; +- +- wl_host_wake: wl-host-wake { +- pins = "gpio79"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-down; +- input-high; +- }; +- +- wl_reg_on: wl-reg-on { +- pins = "gpio84"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- output-low; +- }; +- +- ts_reset_n: ts-rst-n { +- pins = "gpio89"; +- function = "gpio"; +- drive-strength = <2>; +- }; +- +- touch_int_n: touch-int-n { +- pins = "gpio125"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- touch_int_sleep: touch-int-sleep { +- pins = "gpio125"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-down; +- }; +-}; +- +-/* +- * For reasons that are currently unknown (but probably related to fusb301), USB takes about +- * 6 minutes to wake up (nothing interesting in kernel logs), but then it works as it should. +- */ +-&usb3 { +- status = "okay"; +- qcom,select-utmi-as-pipe-clk; +-}; +- +-&usb3_dwc3 { +- extcon = <&usb3_id>; +- dr_mode = "peripheral"; +- phys = <&hsusb_phy1>; +- phy-names = "usb2-phy"; +- snps,hird-threshold = /bits/ 8 <0>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-v3.0.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/msm8996-v3.0.dtsi +deleted file mode 100644 +index 5728583af41e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8996-v3.0.dtsi ++++ /dev/null +@@ -1,63 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Konrad Dybcio +- */ +- +-#include "msm8996.dtsi" +- +-/ { +- qcom,msm-id = <246 0x30000>; +-}; +- +- /* +- * This revision seems to have differ GPU CPR +- * parameters, GPU frequencies and some differences +- * when it comes to voltage delivery to.. once again +- * the GPU. Funnily enough, it's simpler to make it an +- * overlay on top of 3.1 (the final one) than vice versa. +- * The differences will show here as more and more +- * features get enabled upstream. +- */ +- +-gpu_opp_table_3_0: gpu-opp-table-30 { +- compatible = "operating-points-v2"; +- +- opp-624000000 { +- opp-hz = /bits/ 64 <624000000>; +- opp-level = <7>; +- }; +- +- opp-560000000 { +- opp-hz = /bits/ 64 <560000000>; +- opp-level = <6>; +- }; +- +- opp-510000000 { +- opp-hz = /bits/ 64 <510000000>; +- opp-level = <5>; +- }; +- +- opp-401800000 { +- opp-hz = /bits/ 64 <401800000>; +- opp-level = <4>; +- }; +- +- opp-315000000 { +- opp-hz = /bits/ 64 <315000000>; +- opp-level = <3>; +- }; +- +- opp-214000000 { +- opp-hz = /bits/ 64 <214000000>; +- opp-level = <3>; +- }; +- +- opp-133000000 { +- opp-hz = /bits/ 64 <133000000>; +- opp-level = <3>; +- }; +-}; +- +-&gpu { +- operating-points-v2 = <&gpu_opp_table_3_0>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8996.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/msm8996.dtsi +deleted file mode 100644 +index 6077c3601951..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8996.dtsi ++++ /dev/null +@@ -1,3373 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&intc>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- chosen { }; +- +- clocks { +- xo_board: xo-board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <19200000>; +- clock-output-names = "xo_board"; +- }; +- +- sleep_clk: sleep-clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32764>; +- clock-output-names = "sleep_clk"; +- }; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- CPU0: cpu@0 { +- device_type = "cpu"; +- compatible = "qcom,kryo"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- capacity-dmips-mhz = <1024>; +- clocks = <&kryocc 0>; +- operating-points-v2 = <&cluster0_opp>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_0>; +- L2_0: l2-cache { +- compatible = "cache"; +- cache-level = <2>; +- }; +- }; +- +- CPU1: cpu@1 { +- device_type = "cpu"; +- compatible = "qcom,kryo"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- capacity-dmips-mhz = <1024>; +- clocks = <&kryocc 0>; +- operating-points-v2 = <&cluster0_opp>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_0>; +- }; +- +- CPU2: cpu@100 { +- device_type = "cpu"; +- compatible = "qcom,kryo"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- capacity-dmips-mhz = <1024>; +- clocks = <&kryocc 1>; +- operating-points-v2 = <&cluster1_opp>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_1>; +- L2_1: l2-cache { +- compatible = "cache"; +- cache-level = <2>; +- }; +- }; +- +- CPU3: cpu@101 { +- device_type = "cpu"; +- compatible = "qcom,kryo"; +- reg = <0x0 0x101>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- capacity-dmips-mhz = <1024>; +- clocks = <&kryocc 1>; +- operating-points-v2 = <&cluster1_opp>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_1>; +- }; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&CPU0>; +- }; +- +- core1 { +- cpu = <&CPU1>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&CPU2>; +- }; +- +- core1 { +- cpu = <&CPU3>; +- }; +- }; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP_0: cpu-sleep-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "standalone-power-collapse"; +- arm,psci-suspend-param = <0x00000004>; +- entry-latency-us = <130>; +- exit-latency-us = <80>; +- min-residency-us = <300>; +- }; +- }; +- }; +- +- cluster0_opp: opp_table0 { +- compatible = "operating-points-v2-kryo-cpu"; +- nvmem-cells = <&speedbin_efuse>; +- opp-shared; +- +- /* Nominal fmax for now */ +- opp-307200000 { +- opp-hz = /bits/ 64 <307200000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-422400000 { +- opp-hz = /bits/ 64 <422400000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-480000000 { +- opp-hz = /bits/ 64 <480000000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-556800000 { +- opp-hz = /bits/ 64 <556800000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-652800000 { +- opp-hz = /bits/ 64 <652800000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-729600000 { +- opp-hz = /bits/ 64 <729600000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-844800000 { +- opp-hz = /bits/ 64 <844800000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-960000000 { +- opp-hz = /bits/ 64 <960000000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1036800000 { +- opp-hz = /bits/ 64 <1036800000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1113600000 { +- opp-hz = /bits/ 64 <1113600000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1190400000 { +- opp-hz = /bits/ 64 <1190400000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1228800000 { +- opp-hz = /bits/ 64 <1228800000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1324800000 { +- opp-hz = /bits/ 64 <1324800000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1401600000 { +- opp-hz = /bits/ 64 <1401600000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1478400000 { +- opp-hz = /bits/ 64 <1478400000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1593600000 { +- opp-hz = /bits/ 64 <1593600000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- }; +- +- cluster1_opp: opp_table1 { +- compatible = "operating-points-v2-kryo-cpu"; +- nvmem-cells = <&speedbin_efuse>; +- opp-shared; +- +- /* Nominal fmax for now */ +- opp-307200000 { +- opp-hz = /bits/ 64 <307200000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-403200000 { +- opp-hz = /bits/ 64 <403200000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-480000000 { +- opp-hz = /bits/ 64 <480000000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-556800000 { +- opp-hz = /bits/ 64 <556800000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-652800000 { +- opp-hz = /bits/ 64 <652800000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-729600000 { +- opp-hz = /bits/ 64 <729600000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-806400000 { +- opp-hz = /bits/ 64 <806400000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-883200000 { +- opp-hz = /bits/ 64 <883200000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-940800000 { +- opp-hz = /bits/ 64 <940800000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1036800000 { +- opp-hz = /bits/ 64 <1036800000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1113600000 { +- opp-hz = /bits/ 64 <1113600000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1190400000 { +- opp-hz = /bits/ 64 <1190400000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1248000000 { +- opp-hz = /bits/ 64 <1248000000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1324800000 { +- opp-hz = /bits/ 64 <1324800000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1401600000 { +- opp-hz = /bits/ 64 <1401600000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1478400000 { +- opp-hz = /bits/ 64 <1478400000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1555200000 { +- opp-hz = /bits/ 64 <1555200000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1632000000 { +- opp-hz = /bits/ 64 <1632000000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1708800000 { +- opp-hz = /bits/ 64 <1708800000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1785600000 { +- opp-hz = /bits/ 64 <1785600000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1824000000 { +- opp-hz = /bits/ 64 <1824000000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1920000000 { +- opp-hz = /bits/ 64 <1920000000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-1996800000 { +- opp-hz = /bits/ 64 <1996800000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-2073600000 { +- opp-hz = /bits/ 64 <2073600000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- opp-2150400000 { +- opp-hz = /bits/ 64 <2150400000>; +- opp-supported-hw = <0x77>; +- clock-latency-ns = <200000>; +- }; +- }; +- +- firmware { +- scm { +- compatible = "qcom,scm-msm8996"; +- qcom,dload-mode = <&tcsr 0x13000>; +- }; +- }; +- +- tcsr_mutex: hwlock { +- compatible = "qcom,tcsr-mutex"; +- syscon = <&tcsr_mutex_regs 0 0x1000>; +- #hwlock-cells = <1>; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- /* We expect the bootloader to fill in the reg */ +- reg = <0x0 0x80000000 0x0 0x0>; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- mba_region: mba@91500000 { +- reg = <0x0 0x91500000 0x0 0x200000>; +- no-map; +- }; +- +- slpi_region: slpi@90b00000 { +- reg = <0x0 0x90b00000 0x0 0xa00000>; +- no-map; +- }; +- +- venus_region: venus@90400000 { +- reg = <0x0 0x90400000 0x0 0x700000>; +- no-map; +- }; +- +- adsp_region: adsp@8ea00000 { +- reg = <0x0 0x8ea00000 0x0 0x1a00000>; +- no-map; +- }; +- +- mpss_region: mpss@88800000 { +- reg = <0x0 0x88800000 0x0 0x6200000>; +- no-map; +- }; +- +- smem_mem: smem-mem@86000000 { +- reg = <0x0 0x86000000 0x0 0x200000>; +- no-map; +- }; +- +- memory@85800000 { +- reg = <0x0 0x85800000 0x0 0x800000>; +- no-map; +- }; +- +- memory@86200000 { +- reg = <0x0 0x86200000 0x0 0x2600000>; +- no-map; +- }; +- +- rmtfs@86700000 { +- compatible = "qcom,rmtfs-mem"; +- +- size = <0x0 0x200000>; +- alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; +- no-map; +- +- qcom,client-id = <1>; +- qcom,vmid = <15>; +- }; +- +- zap_shader_region: gpu@8f200000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0x90b00000 0x0 0xa00000>; +- no-map; +- }; +- }; +- +- rpm-glink { +- compatible = "qcom,glink-rpm"; +- +- interrupts = ; +- +- qcom,rpm-msg-ram = <&rpm_msg_ram>; +- +- mboxes = <&apcs_glb 0>; +- +- rpm_requests: rpm-requests { +- compatible = "qcom,rpm-msm8996"; +- qcom,glink-channels = "rpm_requests"; +- +- rpmcc: qcom,rpmcc { +- compatible = "qcom,rpmcc-msm8996"; +- #clock-cells = <1>; +- }; +- +- rpmpd: power-controller { +- compatible = "qcom,msm8996-rpmpd"; +- #power-domain-cells = <1>; +- operating-points-v2 = <&rpmpd_opp_table>; +- +- rpmpd_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- rpmpd_opp1: opp1 { +- opp-level = <1>; +- }; +- +- rpmpd_opp2: opp2 { +- opp-level = <2>; +- }; +- +- rpmpd_opp3: opp3 { +- opp-level = <3>; +- }; +- +- rpmpd_opp4: opp4 { +- opp-level = <4>; +- }; +- +- rpmpd_opp5: opp5 { +- opp-level = <5>; +- }; +- +- rpmpd_opp6: opp6 { +- opp-level = <6>; +- }; +- }; +- }; +- }; +- }; +- +- smem { +- compatible = "qcom,smem"; +- memory-region = <&smem_mem>; +- hwlocks = <&tcsr_mutex 3>; +- }; +- +- smp2p-adsp { +- compatible = "qcom,smp2p"; +- qcom,smem = <443>, <429>; +- +- interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; +- +- mboxes = <&apcs_glb 10>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <2>; +- +- smp2p_adsp_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- smp2p_adsp_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-modem { +- compatible = "qcom,smp2p"; +- qcom,smem = <435>, <428>; +- +- interrupts = ; +- +- mboxes = <&apcs_glb 14>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <1>; +- +- modem_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- modem_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-slpi { +- compatible = "qcom,smp2p"; +- qcom,smem = <481>, <430>; +- +- interrupts = ; +- +- mboxes = <&apcs_glb 26>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <3>; +- +- smp2p_slpi_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- smp2p_slpi_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- }; +- +- soc: soc { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0 0xffffffff>; +- compatible = "simple-bus"; +- +- pcie_phy: phy@34000 { +- compatible = "qcom,msm8996-qmp-pcie-phy"; +- reg = <0x00034000 0x488>; +- #clock-cells = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, +- <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, +- <&gcc GCC_PCIE_CLKREF_CLK>; +- clock-names = "aux", "cfg_ahb", "ref"; +- +- resets = <&gcc GCC_PCIE_PHY_BCR>, +- <&gcc GCC_PCIE_PHY_COM_BCR>, +- <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; +- reset-names = "phy", "common", "cfg"; +- status = "disabled"; +- +- pciephy_0: lane@35000 { +- reg = <0x00035000 0x130>, +- <0x00035200 0x200>, +- <0x00035400 0x1dc>; +- #phy-cells = <0>; +- +- clock-output-names = "pcie_0_pipe_clk_src"; +- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; +- clock-names = "pipe0"; +- resets = <&gcc GCC_PCIE_0_PHY_BCR>; +- reset-names = "lane0"; +- }; +- +- pciephy_1: lane@36000 { +- reg = <0x00036000 0x130>, +- <0x00036200 0x200>, +- <0x00036400 0x1dc>; +- #phy-cells = <0>; +- +- clock-output-names = "pcie_1_pipe_clk_src"; +- clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; +- clock-names = "pipe1"; +- resets = <&gcc GCC_PCIE_1_PHY_BCR>; +- reset-names = "lane1"; +- }; +- +- pciephy_2: lane@37000 { +- reg = <0x00037000 0x130>, +- <0x00037200 0x200>, +- <0x00037400 0x1dc>; +- #phy-cells = <0>; +- +- clock-output-names = "pcie_2_pipe_clk_src"; +- clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; +- clock-names = "pipe2"; +- resets = <&gcc GCC_PCIE_2_PHY_BCR>; +- reset-names = "lane2"; +- }; +- }; +- +- rpm_msg_ram: sram@68000 { +- compatible = "qcom,rpm-msg-ram"; +- reg = <0x00068000 0x6000>; +- }; +- +- qfprom@74000 { +- compatible = "qcom,qfprom"; +- reg = <0x00074000 0x8ff>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- qusb2p_hstx_trim: hstx_trim@24e { +- reg = <0x24e 0x2>; +- bits = <5 4>; +- }; +- +- qusb2s_hstx_trim: hstx_trim@24f { +- reg = <0x24f 0x1>; +- bits = <1 4>; +- }; +- +- speedbin_efuse: speedbin@133 { +- reg = <0x133 0x1>; +- bits = <5 3>; +- }; +- }; +- +- rng: rng@83000 { +- compatible = "qcom,prng-ee"; +- reg = <0x00083000 0x1000>; +- clocks = <&gcc GCC_PRNG_AHB_CLK>; +- clock-names = "core"; +- }; +- +- gcc: clock-controller@300000 { +- compatible = "qcom,gcc-msm8996"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- reg = <0x00300000 0x90000>; +- +- clocks = <&rpmcc RPM_SMD_LN_BB_CLK>; +- clock-names = "cxo2"; +- }; +- +- tsens0: thermal-sensor@4a9000 { +- compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; +- reg = <0x004a9000 0x1000>, /* TM */ +- <0x004a8000 0x1000>; /* SROT */ +- #qcom,sensors = <13>; +- interrupts = , +- ; +- interrupt-names = "uplow", "critical"; +- #thermal-sensor-cells = <1>; +- }; +- +- tsens1: thermal-sensor@4ad000 { +- compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; +- reg = <0x004ad000 0x1000>, /* TM */ +- <0x004ac000 0x1000>; /* SROT */ +- #qcom,sensors = <8>; +- interrupts = , +- ; +- interrupt-names = "uplow", "critical"; +- #thermal-sensor-cells = <1>; +- }; +- +- tcsr_mutex_regs: syscon@740000 { +- compatible = "syscon"; +- reg = <0x00740000 0x40000>; +- }; +- +- tcsr: syscon@7a0000 { +- compatible = "qcom,tcsr-msm8996", "syscon"; +- reg = <0x007a0000 0x18000>; +- }; +- +- mmcc: clock-controller@8c0000 { +- compatible = "qcom,mmcc-msm8996"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- reg = <0x008c0000 0x40000>; +- assigned-clocks = <&mmcc MMPLL9_PLL>, +- <&mmcc MMPLL1_PLL>, +- <&mmcc MMPLL3_PLL>, +- <&mmcc MMPLL4_PLL>, +- <&mmcc MMPLL5_PLL>; +- assigned-clock-rates = <624000000>, +- <810000000>, +- <980000000>, +- <960000000>, +- <825000000>; +- }; +- +- mdss: mdss@900000 { +- compatible = "qcom,mdss"; +- +- reg = <0x00900000 0x1000>, +- <0x009b0000 0x1040>, +- <0x009b8000 0x1040>; +- reg-names = "mdss_phys", +- "vbif_phys", +- "vbif_nrt_phys"; +- +- power-domains = <&mmcc MDSS_GDSC>; +- interrupts = ; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- clocks = <&mmcc MDSS_AHB_CLK>; +- clock-names = "iface"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- status = "disabled"; +- +- mdp: mdp@901000 { +- compatible = "qcom,mdp5"; +- reg = <0x00901000 0x90000>; +- reg-names = "mdp_phys"; +- +- interrupt-parent = <&mdss>; +- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; +- +- clocks = <&mmcc MDSS_AHB_CLK>, +- <&mmcc MDSS_AXI_CLK>, +- <&mmcc MDSS_MDP_CLK>, +- <&mmcc SMMU_MDP_AXI_CLK>, +- <&mmcc MDSS_VSYNC_CLK>; +- clock-names = "iface", +- "bus", +- "core", +- "iommu", +- "vsync"; +- +- iommus = <&mdp_smmu 0>; +- +- assigned-clocks = <&mmcc MDSS_MDP_CLK>, +- <&mmcc MDSS_VSYNC_CLK>; +- assigned-clock-rates = <300000000>, +- <19200000>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- mdp5_intf3_out: endpoint { +- remote-endpoint = <&hdmi_in>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- mdp5_intf1_out: endpoint { +- remote-endpoint = <&dsi0_in>; +- }; +- }; +- }; +- }; +- +- dsi0: dsi@994000 { +- compatible = "qcom,mdss-dsi-ctrl"; +- reg = <0x00994000 0x400>; +- reg-names = "dsi_ctrl"; +- +- interrupt-parent = <&mdss>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +- +- clocks = <&mmcc MDSS_MDP_CLK>, +- <&mmcc MDSS_BYTE0_CLK>, +- <&mmcc MDSS_AHB_CLK>, +- <&mmcc MDSS_AXI_CLK>, +- <&mmcc MMSS_MISC_AHB_CLK>, +- <&mmcc MDSS_PCLK0_CLK>, +- <&mmcc MDSS_ESC0_CLK>; +- clock-names = "mdp_core", +- "byte", +- "iface", +- "bus", +- "core_mmss", +- "pixel", +- "core"; +- +- phys = <&dsi0_phy>; +- phy-names = "dsi"; +- status = "disabled"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dsi0_in: endpoint { +- remote-endpoint = <&mdp5_intf1_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- dsi0_out: endpoint { +- }; +- }; +- }; +- }; +- +- dsi0_phy: dsi-phy@994400 { +- compatible = "qcom,dsi-phy-14nm"; +- reg = <0x00994400 0x100>, +- <0x00994500 0x300>, +- <0x00994800 0x188>; +- reg-names = "dsi_phy", +- "dsi_phy_lane", +- "dsi_pll"; +- +- #clock-cells = <1>; +- #phy-cells = <0>; +- +- clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; +- clock-names = "iface", "ref"; +- status = "disabled"; +- }; +- +- hdmi: hdmi-tx@9a0000 { +- compatible = "qcom,hdmi-tx-8996"; +- reg = <0x009a0000 0x50c>, +- <0x00070000 0x6158>, +- <0x009e0000 0xfff>; +- reg-names = "core_physical", +- "qfprom_physical", +- "hdcp_physical"; +- +- interrupt-parent = <&mdss>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; +- +- clocks = <&mmcc MDSS_MDP_CLK>, +- <&mmcc MDSS_AHB_CLK>, +- <&mmcc MDSS_HDMI_CLK>, +- <&mmcc MDSS_HDMI_AHB_CLK>, +- <&mmcc MDSS_EXTPCLK_CLK>; +- clock-names = +- "mdp_core", +- "iface", +- "core", +- "alt_iface", +- "extp"; +- +- phys = <&hdmi_phy>; +- phy-names = "hdmi_phy"; +- #sound-dai-cells = <1>; +- +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- hdmi_in: endpoint { +- remote-endpoint = <&mdp5_intf3_out>; +- }; +- }; +- }; +- }; +- +- hdmi_phy: hdmi-phy@9a0600 { +- #phy-cells = <0>; +- compatible = "qcom,hdmi-phy-8996"; +- reg = <0x009a0600 0x1c4>, +- <0x009a0a00 0x124>, +- <0x009a0c00 0x124>, +- <0x009a0e00 0x124>, +- <0x009a1000 0x124>, +- <0x009a1200 0x0c8>; +- reg-names = "hdmi_pll", +- "hdmi_tx_l0", +- "hdmi_tx_l1", +- "hdmi_tx_l2", +- "hdmi_tx_l3", +- "hdmi_phy"; +- +- clocks = <&mmcc MDSS_AHB_CLK>, +- <&gcc GCC_HDMI_CLKREF_CLK>; +- clock-names = "iface", +- "ref"; +- +- status = "disabled"; +- }; +- }; +- +- gpu: gpu@b00000 { +- compatible = "qcom,adreno-530.2", "qcom,adreno"; +- #stream-id-cells = <16>; +- +- reg = <0x00b00000 0x3f000>; +- reg-names = "kgsl_3d0_reg_memory"; +- +- interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; +- +- clocks = <&mmcc GPU_GX_GFX3D_CLK>, +- <&mmcc GPU_AHB_CLK>, +- <&mmcc GPU_GX_RBBMTIMER_CLK>, +- <&gcc GCC_BIMC_GFX_CLK>, +- <&gcc GCC_MMSS_BIMC_GFX_CLK>; +- +- clock-names = "core", +- "iface", +- "rbbmtimer", +- "mem", +- "mem_iface"; +- +- power-domains = <&mmcc GPU_GX_GDSC>; +- iommus = <&adreno_smmu 0>; +- +- nvmem-cells = <&speedbin_efuse>; +- nvmem-cell-names = "speed_bin"; +- +- operating-points-v2 = <&gpu_opp_table>; +- +- status = "disabled"; +- +- #cooling-cells = <2>; +- +- gpu_opp_table: opp-table { +- compatible ="operating-points-v2"; +- +- /* +- * 624Mhz and 560Mhz are only available on speed +- * bin (1 << 0). All the rest are available on +- * all bins of the hardware +- */ +- opp-624000000 { +- opp-hz = /bits/ 64 <624000000>; +- opp-supported-hw = <0x01>; +- }; +- opp-560000000 { +- opp-hz = /bits/ 64 <560000000>; +- opp-supported-hw = <0x01>; +- }; +- opp-510000000 { +- opp-hz = /bits/ 64 <510000000>; +- opp-supported-hw = <0xFF>; +- }; +- opp-401800000 { +- opp-hz = /bits/ 64 <401800000>; +- opp-supported-hw = <0xFF>; +- }; +- opp-315000000 { +- opp-hz = /bits/ 64 <315000000>; +- opp-supported-hw = <0xFF>; +- }; +- opp-214000000 { +- opp-hz = /bits/ 64 <214000000>; +- opp-supported-hw = <0xFF>; +- }; +- opp-133000000 { +- opp-hz = /bits/ 64 <133000000>; +- opp-supported-hw = <0xFF>; +- }; +- }; +- +- zap-shader { +- memory-region = <&zap_shader_region>; +- }; +- }; +- +- tlmm: pinctrl@1010000 { +- compatible = "qcom,msm8996-pinctrl"; +- reg = <0x01010000 0x300000>; +- interrupts = ; +- gpio-controller; +- gpio-ranges = <&tlmm 0 0 150>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- blsp1_spi1_default: blsp1-spi1-default { +- spi { +- pins = "gpio0", "gpio1", "gpio3"; +- function = "blsp_spi1"; +- drive-strength = <12>; +- bias-disable; +- }; +- +- cs { +- pins = "gpio2"; +- function = "gpio"; +- drive-strength = <16>; +- bias-disable; +- output-high; +- }; +- }; +- +- blsp1_spi1_sleep: blsp1-spi1-sleep { +- pins = "gpio0", "gpio1", "gpio2", "gpio3"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- blsp2_uart2_2pins_default: blsp2-uart1-2pins { +- pins = "gpio4", "gpio5"; +- function = "blsp_uart8"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep { +- pins = "gpio4", "gpio5"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- blsp2_i2c2_default: blsp2-i2c2 { +- pins = "gpio6", "gpio7"; +- function = "blsp_i2c8"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- blsp2_i2c2_sleep: blsp2-i2c2-sleep { +- pins = "gpio6", "gpio7"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- cci0_default: cci0-default { +- pins = "gpio17", "gpio18"; +- function = "cci_i2c"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- camera0_state_on: +- camera_rear_default: camera-rear-default { +- camera0_mclk: mclk0 { +- pins = "gpio13"; +- function = "cam_mclk"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- camera0_rst: rst { +- pins = "gpio25"; +- function = "gpio"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- camera0_pwdn: pwdn { +- pins = "gpio26"; +- function = "gpio"; +- drive-strength = <16>; +- bias-disable; +- }; +- }; +- +- cci1_default: cci1-default { +- pins = "gpio19", "gpio20"; +- function = "cci_i2c"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- camera1_state_on: +- camera_board_default: camera-board-default { +- mclk1 { +- pins = "gpio14"; +- function = "cam_mclk"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- pwdn { +- pins = "gpio98"; +- function = "gpio"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- rst { +- pins = "gpio104"; +- function = "gpio"; +- drive-strength = <16>; +- bias-disable; +- }; +- }; +- +- camera2_state_on: +- camera_front_default: camera-front-default { +- camera2_mclk: mclk2 { +- pins = "gpio15"; +- function = "cam_mclk"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- camera2_rst: rst { +- pins = "gpio23"; +- function = "gpio"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- pwdn { +- pins = "gpio133"; +- function = "gpio"; +- drive-strength = <16>; +- bias-disable; +- }; +- }; +- +- pcie0_state_on: pcie0-state-on { +- perst { +- pins = "gpio35"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- clkreq { +- pins = "gpio36"; +- function = "pci_e0"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- wake { +- pins = "gpio37"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- }; +- +- pcie0_state_off: pcie0-state-off { +- perst { +- pins = "gpio35"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- clkreq { +- pins = "gpio36"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- wake { +- pins = "gpio37"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- blsp1_i2c3_default: blsp1-i2c2-default { +- pins = "gpio47", "gpio48"; +- function = "blsp_i2c3"; +- drive-strength = <16>; +- bias-disable = <0>; +- }; +- +- blsp1_i2c3_sleep: blsp1-i2c2-sleep { +- pins = "gpio47", "gpio48"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable = <0>; +- }; +- +- blsp2_uart3_4pins_default: blsp2-uart2-4pins { +- pins = "gpio49", "gpio50", "gpio51", "gpio52"; +- function = "blsp_uart9"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep { +- pins = "gpio49", "gpio50", "gpio51", "gpio52"; +- function = "blsp_uart9"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- wcd_intr_default: wcd-intr-default{ +- pins = "gpio54"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-down; +- input-enable; +- }; +- +- blsp2_i2c1_default: blsp2-i2c1 { +- pins = "gpio55", "gpio56"; +- function = "blsp_i2c7"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- blsp2_i2c1_sleep: blsp2-i2c0-sleep { +- pins = "gpio55", "gpio56"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- blsp2_i2c5_default: blsp2-i2c5 { +- pins = "gpio60", "gpio61"; +- function = "blsp_i2c11"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- /* Sleep state for BLSP2_I2C5 is missing.. */ +- +- cdc_reset_active: cdc-reset-active { +- pins = "gpio64"; +- function = "gpio"; +- drive-strength = <16>; +- bias-pull-down; +- output-high; +- }; +- +- cdc_reset_sleep: cdc-reset-sleep { +- pins = "gpio64"; +- function = "gpio"; +- drive-strength = <16>; +- bias-disable; +- output-low; +- }; +- +- blsp2_spi6_default: blsp2-spi5-default { +- spi { +- pins = "gpio85", "gpio86", "gpio88"; +- function = "blsp_spi12"; +- drive-strength = <12>; +- bias-disable; +- }; +- +- cs { +- pins = "gpio87"; +- function = "gpio"; +- drive-strength = <16>; +- bias-disable; +- output-high; +- }; +- }; +- +- blsp2_spi6_sleep: blsp2-spi5-sleep { +- pins = "gpio85", "gpio86", "gpio87", "gpio88"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- blsp2_i2c6_default: blsp2-i2c6 { +- pins = "gpio87", "gpio88"; +- function = "blsp_i2c12"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- blsp2_i2c6_sleep: blsp2-i2c6-sleep { +- pins = "gpio87", "gpio88"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- pcie1_state_on: pcie1-state-on { +- perst { +- pins = "gpio130"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- clkreq { +- pins = "gpio131"; +- function = "pci_e1"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- wake { +- pins = "gpio132"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-down; +- }; +- }; +- +- pcie1_state_off: pcie1-state-off { +- /* Perst is missing? */ +- clkreq { +- pins = "gpio131"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- wake { +- pins = "gpio132"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- pcie2_state_on: pcie2-state-on { +- perst { +- pins = "gpio114"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- clkreq { +- pins = "gpio115"; +- function = "pci_e2"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- wake { +- pins = "gpio116"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-down; +- }; +- }; +- +- pcie2_state_off: pcie2-state-off { +- /* Perst is missing? */ +- clkreq { +- pins = "gpio115"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- wake { +- pins = "gpio116"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- sdc1_state_on: sdc1-state-on { +- clk { +- pins = "sdc1_clk"; +- bias-disable; +- drive-strength = <16>; +- }; +- +- cmd { +- pins = "sdc1_cmd"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- data { +- pins = "sdc1_data"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- rclk { +- pins = "sdc1_rclk"; +- bias-pull-down; +- }; +- }; +- +- sdc1_state_off: sdc1-state-off { +- clk { +- pins = "sdc1_clk"; +- bias-disable; +- drive-strength = <2>; +- }; +- +- cmd { +- pins = "sdc1_cmd"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- data { +- pins = "sdc1_data"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- rclk { +- pins = "sdc1_rclk"; +- bias-pull-down; +- }; +- }; +- +- sdc2_state_on: sdc2-clk-on { +- clk { +- pins = "sdc2_clk"; +- bias-disable; +- drive-strength = <16>; +- }; +- +- cmd { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- data { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- }; +- +- sdc2_state_off: sdc2-clk-off { +- clk { +- pins = "sdc2_clk"; +- bias-disable; +- drive-strength = <2>; +- }; +- +- cmd { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- data { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +- }; +- +- spmi_bus: qcom,spmi@400f000 { +- compatible = "qcom,spmi-pmic-arb"; +- reg = <0x0400f000 0x1000>, +- <0x04400000 0x800000>, +- <0x04c00000 0x800000>, +- <0x05800000 0x200000>, +- <0x0400a000 0x002100>; +- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; +- interrupt-names = "periph_irq"; +- interrupts = ; +- qcom,ee = <0>; +- qcom,channel = <0>; +- #address-cells = <2>; +- #size-cells = <0>; +- interrupt-controller; +- #interrupt-cells = <4>; +- }; +- +- agnoc@0 { +- power-domains = <&gcc AGGRE0_NOC_GDSC>; +- compatible = "simple-pm-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- pcie0: pcie@600000 { +- compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; +- status = "disabled"; +- power-domains = <&gcc PCIE0_GDSC>; +- bus-range = <0x00 0xff>; +- num-lanes = <1>; +- +- reg = <0x00600000 0x2000>, +- <0x0c000000 0xf1d>, +- <0x0c000f20 0xa8>, +- <0x0c100000 0x100000>; +- reg-names = "parf", "dbi", "elbi","config"; +- +- phys = <&pciephy_0>; +- phy-names = "pciephy"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, +- <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; +- +- device_type = "pci"; +- +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ +- <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ +- <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ +- <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&pcie0_state_on>; +- pinctrl-1 = <&pcie0_state_off>; +- +- linux,pci-domain = <0>; +- +- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, +- <&gcc GCC_PCIE_0_AUX_CLK>, +- <&gcc GCC_PCIE_0_CFG_AHB_CLK>, +- <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, +- <&gcc GCC_PCIE_0_SLV_AXI_CLK>; +- +- clock-names = "pipe", +- "aux", +- "cfg", +- "bus_master", +- "bus_slave"; +- +- }; +- +- pcie1: pcie@608000 { +- compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; +- power-domains = <&gcc PCIE1_GDSC>; +- bus-range = <0x00 0xff>; +- num-lanes = <1>; +- +- status = "disabled"; +- +- reg = <0x00608000 0x2000>, +- <0x0d000000 0xf1d>, +- <0x0d000f20 0xa8>, +- <0x0d100000 0x100000>; +- +- reg-names = "parf", "dbi", "elbi","config"; +- +- phys = <&pciephy_1>; +- phy-names = "pciephy"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, +- <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; +- +- device_type = "pci"; +- +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ +- <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ +- <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ +- <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&pcie1_state_on>; +- pinctrl-1 = <&pcie1_state_off>; +- +- linux,pci-domain = <1>; +- +- clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, +- <&gcc GCC_PCIE_1_AUX_CLK>, +- <&gcc GCC_PCIE_1_CFG_AHB_CLK>, +- <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, +- <&gcc GCC_PCIE_1_SLV_AXI_CLK>; +- +- clock-names = "pipe", +- "aux", +- "cfg", +- "bus_master", +- "bus_slave"; +- }; +- +- pcie2: pcie@610000 { +- compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; +- power-domains = <&gcc PCIE2_GDSC>; +- bus-range = <0x00 0xff>; +- num-lanes = <1>; +- status = "disabled"; +- reg = <0x00610000 0x2000>, +- <0x0e000000 0xf1d>, +- <0x0e000f20 0xa8>, +- <0x0e100000 0x100000>; +- +- reg-names = "parf", "dbi", "elbi","config"; +- +- phys = <&pciephy_2>; +- phy-names = "pciephy"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, +- <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; +- +- device_type = "pci"; +- +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ +- <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ +- <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ +- <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&pcie2_state_on>; +- pinctrl-1 = <&pcie2_state_off>; +- +- linux,pci-domain = <2>; +- clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, +- <&gcc GCC_PCIE_2_AUX_CLK>, +- <&gcc GCC_PCIE_2_CFG_AHB_CLK>, +- <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, +- <&gcc GCC_PCIE_2_SLV_AXI_CLK>; +- +- clock-names = "pipe", +- "aux", +- "cfg", +- "bus_master", +- "bus_slave"; +- }; +- }; +- +- ufshc: ufshc@624000 { +- compatible = "qcom,ufshc"; +- reg = <0x00624000 0x2500>; +- interrupts = ; +- +- phys = <&ufsphy_lane>; +- phy-names = "ufsphy"; +- +- power-domains = <&gcc UFS_GDSC>; +- +- clock-names = +- "core_clk_src", +- "core_clk", +- "bus_clk", +- "bus_aggr_clk", +- "iface_clk", +- "core_clk_unipro_src", +- "core_clk_unipro", +- "core_clk_ice", +- "ref_clk", +- "tx_lane0_sync_clk", +- "rx_lane0_sync_clk"; +- clocks = +- <&gcc UFS_AXI_CLK_SRC>, +- <&gcc GCC_UFS_AXI_CLK>, +- <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, +- <&gcc GCC_AGGRE2_UFS_AXI_CLK>, +- <&gcc GCC_UFS_AHB_CLK>, +- <&gcc UFS_ICE_CORE_CLK_SRC>, +- <&gcc GCC_UFS_UNIPRO_CORE_CLK>, +- <&gcc GCC_UFS_ICE_CORE_CLK>, +- <&rpmcc RPM_SMD_LN_BB_CLK>, +- <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, +- <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; +- freq-table-hz = +- <100000000 200000000>, +- <0 0>, +- <0 0>, +- <0 0>, +- <0 0>, +- <150000000 300000000>, +- <0 0>, +- <0 0>, +- <0 0>, +- <0 0>, +- <0 0>; +- +- lanes-per-direction = <1>; +- #reset-cells = <1>; +- status = "disabled"; +- +- ufs_variant { +- compatible = "qcom,ufs_variant"; +- }; +- }; +- +- ufsphy: phy@627000 { +- compatible = "qcom,msm8996-qmp-ufs-phy"; +- reg = <0x00627000 0x1c4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clocks = <&gcc GCC_UFS_CLKREF_CLK>; +- clock-names = "ref"; +- +- resets = <&ufshc 0>; +- reset-names = "ufsphy"; +- status = "disabled"; +- +- ufsphy_lane: lanes@627400 { +- reg = <0x627400 0x12c>, +- <0x627600 0x200>, +- <0x627c00 0x1b4>; +- #phy-cells = <0>; +- }; +- }; +- +- camss: camss@a00000 { +- compatible = "qcom,msm8996-camss"; +- reg = <0x00a34000 0x1000>, +- <0x00a00030 0x4>, +- <0x00a35000 0x1000>, +- <0x00a00038 0x4>, +- <0x00a36000 0x1000>, +- <0x00a00040 0x4>, +- <0x00a30000 0x100>, +- <0x00a30400 0x100>, +- <0x00a30800 0x100>, +- <0x00a30c00 0x100>, +- <0x00a31000 0x500>, +- <0x00a00020 0x10>, +- <0x00a10000 0x1000>, +- <0x00a14000 0x1000>; +- reg-names = "csiphy0", +- "csiphy0_clk_mux", +- "csiphy1", +- "csiphy1_clk_mux", +- "csiphy2", +- "csiphy2_clk_mux", +- "csid0", +- "csid1", +- "csid2", +- "csid3", +- "ispif", +- "csi_clk_mux", +- "vfe0", +- "vfe1"; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "csiphy0", +- "csiphy1", +- "csiphy2", +- "csid0", +- "csid1", +- "csid2", +- "csid3", +- "ispif", +- "vfe0", +- "vfe1"; +- power-domains = <&mmcc VFE0_GDSC>, +- <&mmcc VFE1_GDSC>; +- clocks = <&mmcc CAMSS_TOP_AHB_CLK>, +- <&mmcc CAMSS_ISPIF_AHB_CLK>, +- <&mmcc CAMSS_CSI0PHYTIMER_CLK>, +- <&mmcc CAMSS_CSI1PHYTIMER_CLK>, +- <&mmcc CAMSS_CSI2PHYTIMER_CLK>, +- <&mmcc CAMSS_CSI0_AHB_CLK>, +- <&mmcc CAMSS_CSI0_CLK>, +- <&mmcc CAMSS_CSI0PHY_CLK>, +- <&mmcc CAMSS_CSI0PIX_CLK>, +- <&mmcc CAMSS_CSI0RDI_CLK>, +- <&mmcc CAMSS_CSI1_AHB_CLK>, +- <&mmcc CAMSS_CSI1_CLK>, +- <&mmcc CAMSS_CSI1PHY_CLK>, +- <&mmcc CAMSS_CSI1PIX_CLK>, +- <&mmcc CAMSS_CSI1RDI_CLK>, +- <&mmcc CAMSS_CSI2_AHB_CLK>, +- <&mmcc CAMSS_CSI2_CLK>, +- <&mmcc CAMSS_CSI2PHY_CLK>, +- <&mmcc CAMSS_CSI2PIX_CLK>, +- <&mmcc CAMSS_CSI2RDI_CLK>, +- <&mmcc CAMSS_CSI3_AHB_CLK>, +- <&mmcc CAMSS_CSI3_CLK>, +- <&mmcc CAMSS_CSI3PHY_CLK>, +- <&mmcc CAMSS_CSI3PIX_CLK>, +- <&mmcc CAMSS_CSI3RDI_CLK>, +- <&mmcc CAMSS_AHB_CLK>, +- <&mmcc CAMSS_VFE0_CLK>, +- <&mmcc CAMSS_CSI_VFE0_CLK>, +- <&mmcc CAMSS_VFE0_AHB_CLK>, +- <&mmcc CAMSS_VFE0_STREAM_CLK>, +- <&mmcc CAMSS_VFE1_CLK>, +- <&mmcc CAMSS_CSI_VFE1_CLK>, +- <&mmcc CAMSS_VFE1_AHB_CLK>, +- <&mmcc CAMSS_VFE1_STREAM_CLK>, +- <&mmcc CAMSS_VFE_AHB_CLK>, +- <&mmcc CAMSS_VFE_AXI_CLK>; +- clock-names = "top_ahb", +- "ispif_ahb", +- "csiphy0_timer", +- "csiphy1_timer", +- "csiphy2_timer", +- "csi0_ahb", +- "csi0", +- "csi0_phy", +- "csi0_pix", +- "csi0_rdi", +- "csi1_ahb", +- "csi1", +- "csi1_phy", +- "csi1_pix", +- "csi1_rdi", +- "csi2_ahb", +- "csi2", +- "csi2_phy", +- "csi2_pix", +- "csi2_rdi", +- "csi3_ahb", +- "csi3", +- "csi3_phy", +- "csi3_pix", +- "csi3_rdi", +- "ahb", +- "vfe0", +- "csi_vfe0", +- "vfe0_ahb", +- "vfe0_stream", +- "vfe1", +- "csi_vfe1", +- "vfe1_ahb", +- "vfe1_stream", +- "vfe_ahb", +- "vfe_axi"; +- iommus = <&vfe_smmu 0>, +- <&vfe_smmu 1>, +- <&vfe_smmu 2>, +- <&vfe_smmu 3>; +- status = "disabled"; +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- cci: cci@a0c000 { +- compatible = "qcom,msm8996-cci"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xa0c000 0x1000>; +- interrupts = ; +- power-domains = <&mmcc CAMSS_GDSC>; +- clocks = <&mmcc CAMSS_TOP_AHB_CLK>, +- <&mmcc CAMSS_CCI_AHB_CLK>, +- <&mmcc CAMSS_CCI_CLK>, +- <&mmcc CAMSS_AHB_CLK>; +- clock-names = "camss_top_ahb", +- "cci_ahb", +- "cci", +- "camss_ahb"; +- assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, +- <&mmcc CAMSS_CCI_CLK>; +- assigned-clock-rates = <80000000>, <37500000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cci0_default &cci1_default>; +- status = "disabled"; +- +- cci_i2c0: i2c-bus@0 { +- reg = <0>; +- clock-frequency = <400000>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- cci_i2c1: i2c-bus@1 { +- reg = <1>; +- clock-frequency = <400000>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- adreno_smmu: iommu@b40000 { +- compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; +- reg = <0x00b40000 0x10000>; +- +- #global-interrupts = <1>; +- interrupts = , +- , +- ; +- #iommu-cells = <1>; +- +- clocks = <&mmcc GPU_AHB_CLK>, +- <&gcc GCC_MMSS_BIMC_GFX_CLK>; +- clock-names = "iface", "bus"; +- +- power-domains = <&mmcc GPU_GDSC>; +- }; +- +- venus: video-codec@c00000 { +- compatible = "qcom,msm8996-venus"; +- reg = <0x00c00000 0xff000>; +- interrupts = ; +- power-domains = <&mmcc VENUS_GDSC>; +- clocks = <&mmcc VIDEO_CORE_CLK>, +- <&mmcc VIDEO_AHB_CLK>, +- <&mmcc VIDEO_AXI_CLK>, +- <&mmcc VIDEO_MAXI_CLK>; +- clock-names = "core", "iface", "bus", "mbus"; +- iommus = <&venus_smmu 0x00>, +- <&venus_smmu 0x01>, +- <&venus_smmu 0x0a>, +- <&venus_smmu 0x07>, +- <&venus_smmu 0x0e>, +- <&venus_smmu 0x0f>, +- <&venus_smmu 0x08>, +- <&venus_smmu 0x09>, +- <&venus_smmu 0x0b>, +- <&venus_smmu 0x0c>, +- <&venus_smmu 0x0d>, +- <&venus_smmu 0x10>, +- <&venus_smmu 0x11>, +- <&venus_smmu 0x21>, +- <&venus_smmu 0x28>, +- <&venus_smmu 0x29>, +- <&venus_smmu 0x2b>, +- <&venus_smmu 0x2c>, +- <&venus_smmu 0x2d>, +- <&venus_smmu 0x31>; +- memory-region = <&venus_region>; +- status = "disabled"; +- +- video-decoder { +- compatible = "venus-decoder"; +- clocks = <&mmcc VIDEO_SUBCORE0_CLK>; +- clock-names = "core"; +- power-domains = <&mmcc VENUS_CORE0_GDSC>; +- }; +- +- video-encoder { +- compatible = "venus-encoder"; +- clocks = <&mmcc VIDEO_SUBCORE1_CLK>; +- clock-names = "core"; +- power-domains = <&mmcc VENUS_CORE1_GDSC>; +- }; +- }; +- +- mdp_smmu: iommu@d00000 { +- compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; +- reg = <0x00d00000 0x10000>; +- +- #global-interrupts = <1>; +- interrupts = , +- , +- ; +- #iommu-cells = <1>; +- clocks = <&mmcc SMMU_MDP_AHB_CLK>, +- <&mmcc SMMU_MDP_AXI_CLK>; +- clock-names = "iface", "bus"; +- +- power-domains = <&mmcc MDSS_GDSC>; +- }; +- +- venus_smmu: iommu@d40000 { +- compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; +- reg = <0x00d40000 0x20000>; +- #global-interrupts = <1>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; +- clocks = <&mmcc SMMU_VIDEO_AHB_CLK>, +- <&mmcc SMMU_VIDEO_AXI_CLK>; +- clock-names = "iface", "bus"; +- #iommu-cells = <1>; +- status = "okay"; +- }; +- +- vfe_smmu: iommu@da0000 { +- compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; +- reg = <0x00da0000 0x10000>; +- +- #global-interrupts = <1>; +- interrupts = , +- , +- ; +- power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; +- clocks = <&mmcc SMMU_VFE_AHB_CLK>, +- <&mmcc SMMU_VFE_AXI_CLK>; +- clock-names = "iface", +- "bus"; +- #iommu-cells = <1>; +- }; +- +- lpass_q6_smmu: iommu@1600000 { +- compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; +- reg = <0x01600000 0x20000>; +- #iommu-cells = <1>; +- power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; +- +- #global-interrupts = <1>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- +- clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>, +- <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; +- clock-names = "iface", "bus"; +- }; +- +- stm@3002000 { +- compatible = "arm,coresight-stm", "arm,primecell"; +- reg = <0x3002000 0x1000>, +- <0x8280000 0x180000>; +- reg-names = "stm-base", "stm-stimulus-base"; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- out-ports { +- port { +- stm_out: endpoint { +- remote-endpoint = +- <&funnel0_in>; +- }; +- }; +- }; +- }; +- +- tpiu@3020000 { +- compatible = "arm,coresight-tpiu", "arm,primecell"; +- reg = <0x3020000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- in-ports { +- port { +- tpiu_in: endpoint { +- remote-endpoint = +- <&replicator_out1>; +- }; +- }; +- }; +- }; +- +- funnel@3021000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0x3021000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@7 { +- reg = <7>; +- funnel0_in: endpoint { +- remote-endpoint = +- <&stm_out>; +- }; +- }; +- }; +- +- out-ports { +- port { +- funnel0_out: endpoint { +- remote-endpoint = +- <&merge_funnel_in0>; +- }; +- }; +- }; +- }; +- +- funnel@3022000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0x3022000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@6 { +- reg = <6>; +- funnel1_in: endpoint { +- remote-endpoint = +- <&apss_merge_funnel_out>; +- }; +- }; +- }; +- +- out-ports { +- port { +- funnel1_out: endpoint { +- remote-endpoint = +- <&merge_funnel_in1>; +- }; +- }; +- }; +- }; +- +- funnel@3023000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0x3023000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- +- out-ports { +- port { +- funnel2_out: endpoint { +- remote-endpoint = +- <&merge_funnel_in2>; +- }; +- }; +- }; +- }; +- +- funnel@3025000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0x3025000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- merge_funnel_in0: endpoint { +- remote-endpoint = +- <&funnel0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- merge_funnel_in1: endpoint { +- remote-endpoint = +- <&funnel1_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- merge_funnel_in2: endpoint { +- remote-endpoint = +- <&funnel2_out>; +- }; +- }; +- }; +- +- out-ports { +- port { +- merge_funnel_out: endpoint { +- remote-endpoint = +- <&etf_in>; +- }; +- }; +- }; +- }; +- +- replicator@3026000 { +- compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; +- reg = <0x3026000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- in-ports { +- port { +- replicator_in: endpoint { +- remote-endpoint = +- <&etf_out>; +- }; +- }; +- }; +- +- out-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- replicator_out0: endpoint { +- remote-endpoint = +- <&etr_in>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- replicator_out1: endpoint { +- remote-endpoint = +- <&tpiu_in>; +- }; +- }; +- }; +- }; +- +- etf@3027000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0x3027000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- in-ports { +- port { +- etf_in: endpoint { +- remote-endpoint = +- <&merge_funnel_out>; +- }; +- }; +- }; +- +- out-ports { +- port { +- etf_out: endpoint { +- remote-endpoint = +- <&replicator_in>; +- }; +- }; +- }; +- }; +- +- etr@3028000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0x3028000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- arm,scatter-gather; +- +- in-ports { +- port { +- etr_in: endpoint { +- remote-endpoint = +- <&replicator_out0>; +- }; +- }; +- }; +- }; +- +- debug@3810000 { +- compatible = "arm,coresight-cpu-debug", "arm,primecell"; +- reg = <0x3810000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- +- cpu = <&CPU0>; +- }; +- +- etm@3840000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0x3840000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- cpu = <&CPU0>; +- +- out-ports { +- port { +- etm0_out: endpoint { +- remote-endpoint = +- <&apss_funnel0_in0>; +- }; +- }; +- }; +- }; +- +- debug@3910000 { +- compatible = "arm,coresight-cpu-debug", "arm,primecell"; +- reg = <0x3910000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- +- cpu = <&CPU1>; +- }; +- +- etm@3940000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0x3940000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- cpu = <&CPU1>; +- +- out-ports { +- port { +- etm1_out: endpoint { +- remote-endpoint = +- <&apss_funnel0_in1>; +- }; +- }; +- }; +- }; +- +- funnel@39b0000 { /* APSS Funnel 0 */ +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0x39b0000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- apss_funnel0_in0: endpoint { +- remote-endpoint = <&etm0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- apss_funnel0_in1: endpoint { +- remote-endpoint = <&etm1_out>; +- }; +- }; +- }; +- +- out-ports { +- port { +- apss_funnel0_out: endpoint { +- remote-endpoint = +- <&apss_merge_funnel_in0>; +- }; +- }; +- }; +- }; +- +- debug@3a10000 { +- compatible = "arm,coresight-cpu-debug", "arm,primecell"; +- reg = <0x3a10000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- +- cpu = <&CPU2>; +- }; +- +- etm@3a40000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0x3a40000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- cpu = <&CPU2>; +- +- out-ports { +- port { +- etm2_out: endpoint { +- remote-endpoint = +- <&apss_funnel1_in0>; +- }; +- }; +- }; +- }; +- +- debug@3b10000 { +- compatible = "arm,coresight-cpu-debug", "arm,primecell"; +- reg = <0x3b10000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>; +- clock-names = "apb_pclk"; +- +- cpu = <&CPU3>; +- }; +- +- etm@3b40000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0x3b40000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- cpu = <&CPU3>; +- +- out-ports { +- port { +- etm3_out: endpoint { +- remote-endpoint = +- <&apss_funnel1_in1>; +- }; +- }; +- }; +- }; +- +- funnel@3bb0000 { /* APSS Funnel 1 */ +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0x3bb0000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- apss_funnel1_in0: endpoint { +- remote-endpoint = <&etm2_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- apss_funnel1_in1: endpoint { +- remote-endpoint = <&etm3_out>; +- }; +- }; +- }; +- +- out-ports { +- port { +- apss_funnel1_out: endpoint { +- remote-endpoint = +- <&apss_merge_funnel_in1>; +- }; +- }; +- }; +- }; +- +- funnel@3bc0000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0x3bc0000 0x1000>; +- +- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- apss_merge_funnel_in0: endpoint { +- remote-endpoint = +- <&apss_funnel0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- apss_merge_funnel_in1: endpoint { +- remote-endpoint = +- <&apss_funnel1_out>; +- }; +- }; +- }; +- +- out-ports { +- port { +- apss_merge_funnel_out: endpoint { +- remote-endpoint = +- <&funnel1_in>; +- }; +- }; +- }; +- }; +- +- kryocc: clock-controller@6400000 { +- compatible = "qcom,msm8996-apcc"; +- reg = <0x06400000 0x90000>; +- +- clock-names = "xo"; +- clocks = <&xo_board>; +- +- #clock-cells = <1>; +- }; +- +- usb3: usb@6af8800 { +- compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; +- reg = <0x06af8800 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- interrupts = , +- ; +- interrupt-names = "hs_phy_irq", "ss_phy_irq"; +- +- clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, +- <&gcc GCC_USB30_MASTER_CLK>, +- <&gcc GCC_AGGRE2_USB3_AXI_CLK>, +- <&gcc GCC_USB30_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_SLEEP_CLK>, +- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; +- +- assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_MASTER_CLK>; +- assigned-clock-rates = <19200000>, <120000000>; +- +- power-domains = <&gcc USB30_GDSC>; +- status = "disabled"; +- +- usb3_dwc3: dwc3@6a00000 { +- compatible = "snps,dwc3"; +- reg = <0x06a00000 0xcc00>; +- interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; +- phys = <&hsusb_phy1>, <&ssusb_phy_0>; +- phy-names = "usb2-phy", "usb3-phy"; +- snps,dis_u2_susphy_quirk; +- snps,dis_enblslpm_quirk; +- }; +- }; +- +- usb3phy: phy@7410000 { +- compatible = "qcom,msm8996-qmp-usb3-phy"; +- reg = <0x07410000 0x1c4>; +- #clock-cells = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, +- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, +- <&gcc GCC_USB3_CLKREF_CLK>; +- clock-names = "aux", "cfg_ahb", "ref"; +- +- resets = <&gcc GCC_USB3_PHY_BCR>, +- <&gcc GCC_USB3PHY_PHY_BCR>; +- reset-names = "phy", "common"; +- status = "disabled"; +- +- ssusb_phy_0: lane@7410200 { +- reg = <0x07410200 0x200>, +- <0x07410400 0x130>, +- <0x07410600 0x1a8>; +- #phy-cells = <0>; +- +- clock-output-names = "usb3_phy_pipe_clk_src"; +- clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; +- clock-names = "pipe0"; +- }; +- }; +- +- hsusb_phy1: phy@7411000 { +- compatible = "qcom,msm8996-qusb2-phy"; +- reg = <0x07411000 0x180>; +- #phy-cells = <0>; +- +- clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, +- <&gcc GCC_RX1_USB2_CLKREF_CLK>; +- clock-names = "cfg_ahb", "ref"; +- +- resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; +- nvmem-cells = <&qusb2p_hstx_trim>; +- status = "disabled"; +- }; +- +- hsusb_phy2: phy@7412000 { +- compatible = "qcom,msm8996-qusb2-phy"; +- reg = <0x07412000 0x180>; +- #phy-cells = <0>; +- +- clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, +- <&gcc GCC_RX2_USB2_CLKREF_CLK>; +- clock-names = "cfg_ahb", "ref"; +- +- resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; +- nvmem-cells = <&qusb2s_hstx_trim>; +- status = "disabled"; +- }; +- +- sdhc1: sdhci@7464900 { +- compatible = "qcom,sdhci-msm-v4"; +- reg = <0x07464900 0x11c>, <0x07464000 0x800>; +- reg-names = "hc_mem", "core_mem"; +- +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- +- clock-names = "iface", "core", "xo"; +- clocks = <&gcc GCC_SDCC1_AHB_CLK>, +- <&gcc GCC_SDCC1_APPS_CLK>, +- <&xo_board>; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc1_state_on>; +- pinctrl-1 = <&sdc1_state_off>; +- +- bus-width = <8>; +- non-removable; +- status = "disabled"; +- }; +- +- sdhc2: sdhci@74a4900 { +- compatible = "qcom,sdhci-msm-v4"; +- reg = <0x074a4900 0x314>, <0x074a4000 0x800>; +- reg-names = "hc_mem", "core_mem"; +- +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- +- clock-names = "iface", "core", "xo"; +- clocks = <&gcc GCC_SDCC2_AHB_CLK>, +- <&gcc GCC_SDCC2_APPS_CLK>, +- <&xo_board>; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc2_state_on>; +- pinctrl-1 = <&sdc2_state_off>; +- +- bus-width = <4>; +- status = "disabled"; +- }; +- +- blsp1_dma: dma@7544000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0x07544000 0x2b000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "bam_clk"; +- qcom,controlled-remotely; +- #dma-cells = <1>; +- qcom,ee = <0>; +- }; +- +- blsp1_uart2: serial@7570000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x07570000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- blsp1_spi1: spi@7575000 { +- compatible = "qcom,spi-qup-v2.2.1"; +- reg = <0x07575000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp1_spi1_default>; +- pinctrl-1 = <&blsp1_spi1_sleep>; +- dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp1_i2c3: i2c@7577000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x07577000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp1_i2c3_default>; +- pinctrl-1 = <&blsp1_i2c3_sleep>; +- dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp2_dma: dma@7584000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0x07584000 0x2b000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "bam_clk"; +- qcom,controlled-remotely; +- #dma-cells = <1>; +- qcom,ee = <0>; +- }; +- +- blsp2_uart2: serial@75b0000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x075b0000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, +- <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- blsp2_uart3: serial@75b1000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x075b1000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, +- <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- blsp2_i2c1: i2c@75b5000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x075b5000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_AHB_CLK>, +- <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp2_i2c1_default>; +- pinctrl-1 = <&blsp2_i2c1_sleep>; +- dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp2_i2c2: i2c@75b6000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x075b6000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_AHB_CLK>, +- <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp2_i2c2_default>; +- pinctrl-1 = <&blsp2_i2c2_sleep>; +- dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp2_i2c5: i2c@75b9000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x75b9000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_AHB_CLK>, +- <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp2_i2c5_default>; +- dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp2_i2c6: i2c@75ba000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x75ba000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_AHB_CLK>, +- <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp2_i2c6_default>; +- pinctrl-1 = <&blsp2_i2c6_sleep>; +- dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp2_spi6: spi@75ba000{ +- compatible = "qcom,spi-qup-v2.2.1"; +- reg = <0x075ba000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, +- <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp2_spi6_default>; +- pinctrl-1 = <&blsp2_spi6_sleep>; +- dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- usb2: usb@76f8800 { +- compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; +- reg = <0x076f8800 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, +- <&gcc GCC_USB20_MASTER_CLK>, +- <&gcc GCC_USB20_MOCK_UTMI_CLK>, +- <&gcc GCC_USB20_SLEEP_CLK>, +- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; +- +- assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, +- <&gcc GCC_USB20_MASTER_CLK>; +- assigned-clock-rates = <19200000>, <60000000>; +- +- power-domains = <&gcc USB30_GDSC>; +- qcom,select-utmi-as-pipe-clk; +- status = "disabled"; +- +- dwc3@7600000 { +- compatible = "snps,dwc3"; +- reg = <0x07600000 0xcc00>; +- interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; +- phys = <&hsusb_phy2>; +- phy-names = "usb2-phy"; +- maximum-speed = "high-speed"; +- snps,dis_u2_susphy_quirk; +- snps,dis_enblslpm_quirk; +- }; +- }; +- +- slimbam: dma-controller@9184000 { +- compatible = "qcom,bam-v1.7.0"; +- qcom,controlled-remotely; +- reg = <0x09184000 0x32000>; +- num-channels = <31>; +- interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; +- #dma-cells = <1>; +- qcom,ee = <1>; +- qcom,num-ees = <2>; +- }; +- +- slim_msm: slim@91c0000 { +- compatible = "qcom,slim-ngd-v1.5.0"; +- reg = <0x091c0000 0x2C000>; +- reg-names = "ctrl"; +- interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; +- dmas = <&slimbam 3>, <&slimbam 4>, +- <&slimbam 5>, <&slimbam 6>; +- dma-names = "rx", "tx", "tx2", "rx2"; +- #address-cells = <1>; +- #size-cells = <0>; +- ngd@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- tasha_ifd: tas-ifd { +- compatible = "slim217,1a0"; +- reg = <0 0>; +- }; +- +- wcd9335: codec@1{ +- pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; +- pinctrl-names = "default"; +- +- compatible = "slim217,1a0"; +- reg = <1 0>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, +- <53 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "intr1", "intr2"; +- interrupt-controller; +- #interrupt-cells = <1>; +- reset-gpios = <&tlmm 64 0>; +- +- slim-ifc-dev = <&tasha_ifd>; +- +- #sound-dai-cells = <1>; +- }; +- }; +- }; +- +- adsp_pil: remoteproc@9300000 { +- compatible = "qcom,msm8996-adsp-pil"; +- reg = <0x09300000 0x80000>; +- +- interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack"; +- +- clocks = <&xo_board>; +- clock-names = "xo"; +- +- memory-region = <&adsp_region>; +- +- qcom,smem-states = <&smp2p_adsp_out 0>; +- qcom,smem-state-names = "stop"; +- +- power-domains = <&rpmpd MSM8996_VDDCX>; +- power-domain-names = "cx"; +- +- status = "disabled"; +- +- smd-edge { +- interrupts = ; +- +- label = "lpass"; +- mboxes = <&apcs_glb 8>; +- qcom,smd-edge = <1>; +- qcom,remote-pid = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- apr { +- power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; +- compatible = "qcom,apr-v2"; +- qcom,smd-channels = "apr_audio_svc"; +- qcom,apr-domain = ; +- #address-cells = <1>; +- #size-cells = <0>; +- +- q6core { +- reg = ; +- compatible = "qcom,q6core"; +- }; +- +- q6afe: q6afe { +- compatible = "qcom,q6afe"; +- reg = ; +- q6afedai: dais { +- compatible = "qcom,q6afe-dais"; +- #address-cells = <1>; +- #size-cells = <0>; +- #sound-dai-cells = <1>; +- hdmi@1 { +- reg = <1>; +- }; +- }; +- }; +- +- q6asm: q6asm { +- compatible = "qcom,q6asm"; +- reg = ; +- q6asmdai: dais { +- compatible = "qcom,q6asm-dais"; +- #address-cells = <1>; +- #size-cells = <0>; +- #sound-dai-cells = <1>; +- iommus = <&lpass_q6_smmu 1>; +- }; +- }; +- +- q6adm: q6adm { +- compatible = "qcom,q6adm"; +- reg = ; +- q6routing: routing { +- compatible = "qcom,q6adm-routing"; +- #sound-dai-cells = <0>; +- }; +- }; +- }; +- +- }; +- }; +- +- apcs_glb: mailbox@9820000 { +- compatible = "qcom,msm8996-apcs-hmss-global"; +- reg = <0x09820000 0x1000>; +- +- #mbox-cells = <1>; +- }; +- +- timer@9840000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "arm,armv7-timer-mem"; +- reg = <0x09840000 0x1000>; +- clock-frequency = <19200000>; +- +- frame@9850000 { +- frame-number = <0>; +- interrupts = , +- ; +- reg = <0x09850000 0x1000>, +- <0x09860000 0x1000>; +- }; +- +- frame@9870000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0x09870000 0x1000>; +- status = "disabled"; +- }; +- +- frame@9880000 { +- frame-number = <2>; +- interrupts = ; +- reg = <0x09880000 0x1000>; +- status = "disabled"; +- }; +- +- frame@9890000 { +- frame-number = <3>; +- interrupts = ; +- reg = <0x09890000 0x1000>; +- status = "disabled"; +- }; +- +- frame@98a0000 { +- frame-number = <4>; +- interrupts = ; +- reg = <0x098a0000 0x1000>; +- status = "disabled"; +- }; +- +- frame@98b0000 { +- frame-number = <5>; +- interrupts = ; +- reg = <0x098b0000 0x1000>; +- status = "disabled"; +- }; +- +- frame@98c0000 { +- frame-number = <6>; +- interrupts = ; +- reg = <0x098c0000 0x1000>; +- status = "disabled"; +- }; +- }; +- +- saw3: syscon@9a10000 { +- compatible = "syscon"; +- reg = <0x09a10000 0x1000>; +- }; +- +- intc: interrupt-controller@9bc0000 { +- compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; +- #interrupt-cells = <3>; +- interrupt-controller; +- #redistributor-regions = <1>; +- redistributor-stride = <0x0 0x40000>; +- reg = <0x09bc0000 0x10000>, +- <0x09c00000 0x100000>; +- interrupts = ; +- }; +- }; +- +- sound: sound { +- }; +- +- thermal-zones { +- cpu0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 3>; +- +- trips { +- cpu0_alert0: trip-point0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu0_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 5>; +- +- trips { +- cpu1_alert0: trip-point0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu1_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 8>; +- +- trips { +- cpu2_alert0: trip-point0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu2_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 10>; +- +- trips { +- cpu3_alert0: trip-point0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu3_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- gpu-thermal-top { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 6>; +- +- trips { +- gpu1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&gpu1_alert0>; +- cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- gpu-thermal-bottom { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 7>; +- +- trips { +- gpu2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&gpu2_alert0>; +- cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- m4m-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 1>; +- +- trips { +- m4m_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- l3-or-venus-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 2>; +- +- trips { +- l3_or_venus_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- cluster0-l2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 7>; +- +- trips { +- cluster0_l2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- cluster1-l2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 12>; +- +- trips { +- cluster1_l2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- camera-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 1>; +- +- trips { +- camera_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- q6-dsp-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 2>; +- +- trips { +- q6_dsp_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- mem-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 3>; +- +- trips { +- mem_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- modemtx-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 4>; +- +- trips { +- modemtx_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8998-asus-novago-tp370ql.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8998-asus-novago-tp370ql.dts +deleted file mode 100644 +index db5821be1e2f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8998-asus-novago-tp370ql.dts ++++ /dev/null +@@ -1,47 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* Copyright (c) 2019, Jeffrey Hugo. All rights reserved. */ +- +-/dts-v1/; +- +-#include "msm8998-clamshell.dtsi" +- +-/ { +- model = "Asus NovaGo TP370QL"; +- compatible = "asus,novago-tp370ql", "qcom,msm8998"; +-}; +- +-&blsp1_i2c6 { +- status = "okay"; +- +- touchpad@15 { +- compatible = "hid-over-i2c"; +- interrupt-parent = <&tlmm>; +- interrupts = <0x7b IRQ_TYPE_LEVEL_LOW>; +- reg = <0x15>; +- hid-descr-addr = <0x0001>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&touchpad>; +- }; +- +- keyboard@3a { +- compatible = "hid-over-i2c"; +- interrupt-parent = <&tlmm>; +- interrupts = <0x25 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x3a>; +- hid-descr-addr = <0x0001>; +- }; +-}; +- +-&sdhc2 { +- cd-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; +-}; +- +-&tlmm { +- touchpad: touchpad { +- config { +- pins = "gpio123"; +- bias-pull-up; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8998-clamshell.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/msm8998-clamshell.dtsi +deleted file mode 100644 +index 125d7923d713..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8998-clamshell.dtsi ++++ /dev/null +@@ -1,363 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* Copyright (c) 2019, Jeffrey Hugo. All rights reserved. */ +- +-/* +- * Common include for MSM8998 clamshell devices, ie the Lenovo Miix 630, +- * Asus NovaGo TP370QL, and HP Envy x2. All three devices are basically the +- * same, with differences in peripherals. +- */ +- +-#include "msm8998.dtsi" +-#include "pm8998.dtsi" +-#include "pm8005.dtsi" +- +-/ { +- chosen { +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&blsp1_uart3 { +- status = "okay"; +- +- bluetooth { +- compatible = "qcom,wcn3990-bt"; +- +- vddio-supply = <&vreg_s4a_1p8>; +- vddxo-supply = <&vreg_l7a_1p8>; +- vddrf-supply = <&vreg_l17a_1p3>; +- vddch0-supply = <&vreg_l25a_3p3>; +- max-speed = <3200000>; +- }; +-}; +- +-/* +- * The laptop FW does not appear to support the retention state as it is +- * not advertised as enabled in ACPI, and enabling it in DT can cause boot +- * hangs. +- */ +-&CPU0 { +- cpu-idle-states = <&LITTLE_CPU_SLEEP_1>; +-}; +- +-&CPU1 { +- cpu-idle-states = <&LITTLE_CPU_SLEEP_1>; +-}; +- +-&CPU2 { +- cpu-idle-states = <&LITTLE_CPU_SLEEP_1>; +-}; +- +-&CPU3 { +- cpu-idle-states = <&LITTLE_CPU_SLEEP_1>; +-}; +- +-&CPU4 { +- cpu-idle-states = <&BIG_CPU_SLEEP_1>; +-}; +- +-&CPU5 { +- cpu-idle-states = <&BIG_CPU_SLEEP_1>; +-}; +- +-&CPU6 { +- cpu-idle-states = <&BIG_CPU_SLEEP_1>; +-}; +- +-&CPU7 { +- cpu-idle-states = <&BIG_CPU_SLEEP_1>; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie_phy { +- status = "okay"; +-}; +- +-&pm8005_lsid1 { +- pm8005-regulators { +- compatible = "qcom,pm8005-regulators"; +- +- vdd_s1-supply = <&vph_pwr>; +- +- pm8005_s1: s1 { /* VDD_GFX supply */ +- regulator-min-microvolt = <524000>; +- regulator-max-microvolt = <1100000>; +- regulator-enable-ramp-delay = <500>; +- +- /* hack until we rig up the gpu consumer */ +- regulator-always-on; +- }; +- }; +-}; +- +-&qusb2phy { +- status = "okay"; +- +- vdda-pll-supply = <&vreg_l12a_1p8>; +- vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; +-}; +- +-&rpm_requests { +- pm8998-regulators { +- compatible = "qcom,rpm-pm8998-regulators"; +- +- vdd_s1-supply = <&vph_pwr>; +- vdd_s2-supply = <&vph_pwr>; +- vdd_s3-supply = <&vph_pwr>; +- vdd_s4-supply = <&vph_pwr>; +- vdd_s5-supply = <&vph_pwr>; +- vdd_s6-supply = <&vph_pwr>; +- vdd_s7-supply = <&vph_pwr>; +- vdd_s8-supply = <&vph_pwr>; +- vdd_s9-supply = <&vph_pwr>; +- vdd_s10-supply = <&vph_pwr>; +- vdd_s11-supply = <&vph_pwr>; +- vdd_s12-supply = <&vph_pwr>; +- vdd_s13-supply = <&vph_pwr>; +- vdd_l1_l27-supply = <&vreg_s7a_1p025>; +- vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>; +- vdd_l3_l11-supply = <&vreg_s7a_1p025>; +- vdd_l4_l5-supply = <&vreg_s7a_1p025>; +- vdd_l6-supply = <&vreg_s5a_2p04>; +- vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>; +- vdd_l9-supply = <&vph_pwr>; +- vdd_l10_l23_l25-supply = <&vph_pwr>; +- vdd_l13_l19_l21-supply = <&vph_pwr>; +- vdd_l16_l28-supply = <&vph_pwr>; +- vdd_l18_l22-supply = <&vph_pwr>; +- vdd_l20_l24-supply = <&vph_pwr>; +- vdd_l26-supply = <&vreg_s3a_1p35>; +- vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; +- +- vreg_s3a_1p35: s3 { +- regulator-min-microvolt = <1352000>; +- regulator-max-microvolt = <1352000>; +- }; +- vreg_s4a_1p8: s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-allow-set-load; +- }; +- vreg_s5a_2p04: s5 { +- regulator-min-microvolt = <1904000>; +- regulator-max-microvolt = <2040000>; +- }; +- vreg_s7a_1p025: s7 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1028000>; +- }; +- vreg_l1a_0p875: l1 { +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-allow-set-load; +- }; +- vreg_l2a_1p2: l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-allow-set-load; +- }; +- vreg_l3a_1p0: l3 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- vreg_l5a_0p8: l5 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- }; +- vreg_l6a_1p8: l6 { +- regulator-min-microvolt = <1808000>; +- regulator-max-microvolt = <1808000>; +- }; +- vreg_l7a_1p8: l7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-allow-set-load; +- }; +- vreg_l8a_1p2: l8 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- vreg_l9a_1p8: l9 { +- regulator-min-microvolt = <1808000>; +- regulator-max-microvolt = <2960000>; +- }; +- vreg_l10a_1p8: l10 { +- regulator-min-microvolt = <1808000>; +- regulator-max-microvolt = <2960000>; +- }; +- vreg_l11a_1p0: l11 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- vreg_l12a_1p8: l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l13a_2p95: l13 { +- regulator-min-microvolt = <1808000>; +- regulator-max-microvolt = <2960000>; +- }; +- vreg_l14a_1p88: l14 { +- regulator-min-microvolt = <1880000>; +- regulator-max-microvolt = <1880000>; +- }; +- vreg_l15a_1p8: l15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l16a_2p7: l16 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2704000>; +- }; +- vreg_l17a_1p3: l17 { +- regulator-min-microvolt = <1304000>; +- regulator-max-microvolt = <1304000>; +- regulator-allow-set-load; +- }; +- vreg_l18a_2p7: l18 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2704000>; +- }; +- vreg_l19a_3p0: l19 { +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3008000>; +- }; +- vreg_l20a_2p95: l20 { +- regulator-min-microvolt = <2960000>; +- regulator-max-microvolt = <2960000>; +- regulator-allow-set-load; +- }; +- vreg_l21a_2p95: l21 { +- regulator-min-microvolt = <2960000>; +- regulator-max-microvolt = <2960000>; +- regulator-allow-set-load; +- regulator-system-load = <800000>; +- }; +- vreg_l22a_2p85: l22 { +- regulator-min-microvolt = <2864000>; +- regulator-max-microvolt = <2864000>; +- }; +- vreg_l23a_3p3: l23 { +- regulator-min-microvolt = <3312000>; +- regulator-max-microvolt = <3312000>; +- }; +- vreg_l24a_3p075: l24 { +- regulator-min-microvolt = <3088000>; +- regulator-max-microvolt = <3088000>; +- }; +- vreg_l25a_3p3: l25 { +- regulator-min-microvolt = <3104000>; +- regulator-max-microvolt = <3312000>; +- regulator-allow-set-load; +- }; +- vreg_l26a_1p2: l26 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- vreg_l28_3p0: l28 { +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3008000>; +- }; +- +- vreg_lvs1a_1p8: lvs1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vreg_lvs2a_1p8: lvs2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- }; +-}; +- +-&remoteproc_mss { +- status = "okay"; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <0 4>, <81 4>; +- +- touchpad: touchpad { +- config { +- pins = "gpio123"; +- bias-pull-up; /* pull up */ +- }; +- }; +-}; +- +-&sdhc2 { +- status = "okay"; +- +- vmmc-supply = <&vreg_l21a_2p95>; +- vqmmc-supply = <&vreg_l13a_2p95>; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; +- pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; +-}; +- +-&ufshc { +- status = "okay"; +-}; +- +-&ufsphy { +- status = "okay"; +-}; +- +-&usb3 { +- status = "okay"; +-}; +- +-&usb3_dwc3 { +- dr_mode = "host"; /* Force to host until we have Type-C hooked up */ +-}; +- +-&usb3phy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l1a_0p875>; +- vdda-pll-supply = <&vreg_l2a_1p2>; +-}; +- +-&wifi { +- status = "okay"; +- +- vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; +- vdd-1.8-xo-supply = <&vreg_l7a_1p8>; +- vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; +- vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; +-}; +- +-/* PINCTRL - board-specific pinctrl */ +-&blsp1_uart3_on { +- rx { +- /delete-property/ bias-disable; +- /* +- * Configure a pull-up on 45 (RX). This is needed to +- * avoid garbage data when the TX pin of the Bluetooth +- * module is in tri-state (module powered off or not +- * driving the signal yet). +- */ +- bias-pull-up; +- }; +- +- cts { +- /delete-property/ bias-disable; +- /* +- * Configure a pull-down on 47 (CTS) to match the pull +- * of the Bluetooth module. +- */ +- bias-pull-down; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8998-hp-envy-x2.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8998-hp-envy-x2.dts +deleted file mode 100644 +index 24073127091f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8998-hp-envy-x2.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* Copyright (c) 2019, Jeffrey Hugo. All rights reserved. */ +- +-/dts-v1/; +- +-#include "msm8998-clamshell.dtsi" +- +-/ { +- model = "HP Envy x2"; +- compatible = "hp,envy-x2", "qcom,msm8998"; +-}; +- +-&blsp1_i2c6 { +- status = "okay"; +- +- keyboard@3a { +- compatible = "hid-over-i2c"; +- interrupt-parent = <&tlmm>; +- interrupts = <0x79 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x3a>; +- hid-descr-addr = <0x0001>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&touchpad>; +- }; +-}; +- +-&sdhc2 { +- cd-gpios = <&tlmm 95 GPIO_ACTIVE_LOW>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8998-lenovo-miix-630.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8998-lenovo-miix-630.dts +deleted file mode 100644 +index 89492ed5196c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8998-lenovo-miix-630.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* Copyright (c) 2019, Jeffrey Hugo. All rights reserved. */ +- +-/dts-v1/; +- +-#include "msm8998-clamshell.dtsi" +- +-/ { +- model = "Lenovo Miix 630"; +- compatible = "lenovo,miix-630", "qcom,msm8998"; +-}; +- +-&blsp1_i2c6 { +- status = "okay"; +- +- keyboard@3a { +- compatible = "hid-over-i2c"; +- interrupt-parent = <&tlmm>; +- interrupts = <0x79 IRQ_TYPE_LEVEL_LOW>; +- reg = <0x3a>; +- hid-descr-addr = <0x0001>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&touchpad>; +- }; +-}; +- +-&remoteproc_mss { +- firmware-name = "qcom/LENOVO/81F1/qcdsp1v28998.mbn", +- "qcom/LENOVO/81F1/qcdsp28998.mbn"; +-}; +- +-&sdhc2 { +- cd-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8998-mtp.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8998-mtp.dts +deleted file mode 100644 +index 66540d2ca13b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8998-mtp.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ +- +-/dts-v1/; +- +-#include "msm8998-mtp.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. MSM8998 v1 MTP"; +- compatible = "qcom,msm8998-mtp"; +- +- qcom,board-id = <8 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8998-mtp.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/msm8998-mtp.dtsi +deleted file mode 100644 +index a1d15eab8553..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8998-mtp.dtsi ++++ /dev/null +@@ -1,425 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ +- +-#include "msm8998.dtsi" +-#include "pm8998.dtsi" +-#include "pmi8998.dtsi" +-#include "pm8005.dtsi" +- +-/ { +- aliases { +- serial0 = &blsp2_uart1; +- serial1 = &blsp1_uart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&blsp1_uart3 { +- status = "okay"; +- +- bluetooth { +- compatible = "qcom,wcn3990-bt"; +- +- vddio-supply = <&vreg_s4a_1p8>; +- vddxo-supply = <&vreg_l7a_1p8>; +- vddrf-supply = <&vreg_l17a_1p3>; +- vddch0-supply = <&vreg_l25a_3p3>; +- max-speed = <3200000>; +- }; +-}; +- +-&blsp2_uart1 { +- status = "okay"; +-}; +- +-&etf { +- status = "okay"; +-}; +- +-&etm1 { +- status = "okay"; +-}; +- +-&etm2 { +- status = "okay"; +-}; +- +-&etm3 { +- status = "okay"; +-}; +- +-&etm4 { +- status = "okay"; +-}; +- +-&etm5 { +- status = "okay"; +-}; +- +-&etm6 { +- status = "okay"; +-}; +- +-&etm7 { +- status = "okay"; +-}; +- +-&etm8 { +- status = "okay"; +-}; +- +-&etr { +- status = "okay"; +-}; +- +-&funnel1 { +- status = "okay"; +-}; +- +-&funnel2 { +- status = "okay"; +-}; +- +-&funnel3 { +- status = "okay"; +-}; +- +-&funnel4 { +- // FIXME: Figure out why clock late_initcall crashes the board with +- // this enabled. +- // status = "okay"; +-}; +- +-&funnel5 { +- // FIXME: Figure out why clock late_initcall crashes the board with +- // this enabled. +- // status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie_phy { +- status = "okay"; +-}; +- +-&pm8005_lsid1 { +- pm8005-regulators { +- compatible = "qcom,pm8005-regulators"; +- +- vdd_s1-supply = <&vph_pwr>; +- +- pm8005_s1: s1 { /* VDD_GFX supply */ +- regulator-min-microvolt = <524000>; +- regulator-max-microvolt = <1100000>; +- regulator-enable-ramp-delay = <500>; +- +- /* hack until we rig up the gpu consumer */ +- regulator-always-on; +- }; +- }; +-}; +- +-&qusb2phy { +- status = "okay"; +- +- vdda-pll-supply = <&vreg_l12a_1p8>; +- vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; +-}; +- +-&replicator1 { +- status = "okay"; +-}; +- +-&rpm_requests { +- pm8998-regulators { +- compatible = "qcom,rpm-pm8998-regulators"; +- +- vdd_s1-supply = <&vph_pwr>; +- vdd_s2-supply = <&vph_pwr>; +- vdd_s3-supply = <&vph_pwr>; +- vdd_s4-supply = <&vph_pwr>; +- vdd_s5-supply = <&vph_pwr>; +- vdd_s6-supply = <&vph_pwr>; +- vdd_s7-supply = <&vph_pwr>; +- vdd_s8-supply = <&vph_pwr>; +- vdd_s9-supply = <&vph_pwr>; +- vdd_s10-supply = <&vph_pwr>; +- vdd_s11-supply = <&vph_pwr>; +- vdd_s12-supply = <&vph_pwr>; +- vdd_s13-supply = <&vph_pwr>; +- vdd_l1_l27-supply = <&vreg_s7a_1p025>; +- vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>; +- vdd_l3_l11-supply = <&vreg_s7a_1p025>; +- vdd_l4_l5-supply = <&vreg_s7a_1p025>; +- vdd_l6-supply = <&vreg_s5a_2p04>; +- vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>; +- vdd_l9-supply = <&vreg_bob>; +- vdd_l10_l23_l25-supply = <&vreg_bob>; +- vdd_l13_l19_l21-supply = <&vreg_bob>; +- vdd_l16_l28-supply = <&vreg_bob>; +- vdd_l18_l22-supply = <&vreg_bob>; +- vdd_l20_l24-supply = <&vreg_bob>; +- vdd_l26-supply = <&vreg_s3a_1p35>; +- vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; +- +- vreg_s3a_1p35: s3 { +- regulator-min-microvolt = <1352000>; +- regulator-max-microvolt = <1352000>; +- }; +- vreg_s4a_1p8: s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-allow-set-load; +- }; +- vreg_s5a_2p04: s5 { +- regulator-min-microvolt = <1904000>; +- regulator-max-microvolt = <2040000>; +- }; +- vreg_s7a_1p025: s7 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1028000>; +- }; +- vreg_l1a_0p875: l1 { +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- }; +- vreg_l2a_1p2: l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- vreg_l3a_1p0: l3 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- vreg_l5a_0p8: l5 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- }; +- vreg_l6a_1p8: l6 { +- regulator-min-microvolt = <1808000>; +- regulator-max-microvolt = <1808000>; +- }; +- vreg_l7a_1p8: l7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l8a_1p2: l8 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- vreg_l9a_1p8: l9 { +- regulator-min-microvolt = <1808000>; +- regulator-max-microvolt = <2960000>; +- }; +- vreg_l10a_1p8: l10 { +- regulator-min-microvolt = <1808000>; +- regulator-max-microvolt = <2960000>; +- }; +- vreg_l11a_1p0: l11 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- vreg_l12a_1p8: l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l13a_2p95: l13 { +- regulator-min-microvolt = <1808000>; +- regulator-max-microvolt = <2960000>; +- }; +- vreg_l14a_1p88: l14 { +- regulator-min-microvolt = <1880000>; +- regulator-max-microvolt = <1880000>; +- }; +- vreg_l15a_1p8: l15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l16a_2p7: l16 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2704000>; +- }; +- vreg_l17a_1p3: l17 { +- regulator-min-microvolt = <1304000>; +- regulator-max-microvolt = <1304000>; +- }; +- vreg_l18a_2p7: l18 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2704000>; +- }; +- vreg_l19a_3p0: l19 { +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3008000>; +- }; +- vreg_l20a_2p95: l20 { +- regulator-min-microvolt = <2960000>; +- regulator-max-microvolt = <2960000>; +- regulator-allow-set-load; +- }; +- vreg_l21a_2p95: l21 { +- regulator-min-microvolt = <2960000>; +- regulator-max-microvolt = <2960000>; +- regulator-allow-set-load; +- regulator-system-load = <800000>; +- }; +- vreg_l22a_2p85: l22 { +- regulator-min-microvolt = <2864000>; +- regulator-max-microvolt = <2864000>; +- }; +- vreg_l23a_3p3: l23 { +- regulator-min-microvolt = <3312000>; +- regulator-max-microvolt = <3312000>; +- }; +- vreg_l24a_3p075: l24 { +- regulator-min-microvolt = <3088000>; +- regulator-max-microvolt = <3088000>; +- }; +- vreg_l25a_3p3: l25 { +- regulator-min-microvolt = <3104000>; +- regulator-max-microvolt = <3312000>; +- }; +- vreg_l26a_1p2: l26 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-allow-set-load; +- }; +- vreg_l28_3p0: l28 { +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3008000>; +- }; +- +- vreg_lvs1a_1p8: lvs1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vreg_lvs2a_1p8: lvs2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- }; +- +- pmi8998-regulators { +- compatible = "qcom,rpm-pmi8998-regulators"; +- +- vdd_bob-supply = <&vph_pwr>; +- +- vreg_bob: bob { +- regulator-min-microvolt = <3312000>; +- regulator-max-microvolt = <3600000>; +- }; +- }; +-}; +- +-&remoteproc_adsp { +- status = "okay"; +-}; +- +-&remoteproc_mss { +- status = "okay"; +-}; +- +-&remoteproc_slpi { +- status = "okay"; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <0 4>, <81 4>; +-}; +- +-&sdhc2 { +- status = "okay"; +- cd-gpios = <&tlmm 95 GPIO_ACTIVE_LOW>; +- +- vmmc-supply = <&vreg_l21a_2p95>; +- vqmmc-supply = <&vreg_l13a_2p95>; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; +- pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; +-}; +- +-&stm { +- status = "okay"; +-}; +- +-&ufshc { +- status = "okay"; +- vcc-supply = <&vreg_l20a_2p95>; +- vccq-supply = <&vreg_l26a_1p2>; +- vccq2-supply = <&vreg_s4a_1p8>; +- vcc-max-microamp = <750000>; +- vccq-max-microamp = <560000>; +- vccq2-max-microamp = <750000>; +-}; +- +-&ufsphy { +- status = "okay"; +- vdda-phy-supply = <&vreg_l1a_0p875>; +- vdda-pll-supply = <&vreg_l2a_1p2>; +- vddp-ref-clk-supply = <&vreg_l26a_1p2>; +- vdda-phy-max-microamp = <51400>; +- vdda-pll-max-microamp = <14600>; +- vddp-ref-clk-max-microamp = <100>; +- vddp-ref-clk-always-on; +-}; +- +-&usb3 { +- status = "okay"; +-}; +- +-&usb3_dwc3 { +- dr_mode = "host"; /* Force to host until we have Type-C hooked up */ +-}; +- +-&usb3phy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l1a_0p875>; +- vdda-pll-supply = <&vreg_l2a_1p2>; +-}; +- +-&wifi { +- status = "okay"; +- +- vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; +- vdd-1.8-xo-supply = <&vreg_l7a_1p8>; +- vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; +- vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; +-}; +- +-/* PINCTRL - board-specific pinctrl */ +-&blsp1_uart3_on { +- rx { +- /delete-property/ bias-disable; +- /* +- * Configure a pull-up on 45 (RX). This is needed to +- * avoid garbage data when the TX pin of the Bluetooth +- * module is in tri-state (module powered off or not +- * driving the signal yet). +- */ +- bias-pull-up; +- }; +- +- cts { +- /delete-property/ bias-disable; +- /* +- * Configure a pull-down on 47 (CTS) to match the pull +- * of the Bluetooth module. +- */ +- bias-pull-down; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8998-oneplus-cheeseburger.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8998-oneplus-cheeseburger.dts +deleted file mode 100644 +index 66b9297588ab..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8998-oneplus-cheeseburger.dts ++++ /dev/null +@@ -1,42 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * OnePlus 5 (cheeseburger) device tree +- * +- * Copyright (c) 2021, Jami Kettunen +- */ +- +-#include +-#include "msm8998-oneplus-common.dtsi" +- +-/ { +- model = "OnePlus 5"; +- compatible = "oneplus,cheeseburger", "qcom,msm8998"; +- /* Required for bootloader to select correct board */ +- qcom,board-id = <8 0 16859 23>; +- +- /* Capacitive keypad button backlight */ +- leds { +- compatible = "gpio-leds"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&button_backlight_default>; +- +- button-backlight { +- gpios = <&pmi8998_gpio 5 GPIO_ACTIVE_HIGH>; +- color = ; +- function = LED_FUNCTION_KBD_BACKLIGHT; +- default-state = "off"; +- }; +- }; +-}; +- +-&pmi8998_gpio { +- button_backlight_default: button-backlight-default { +- pinconf { +- pins = "gpio5"; +- function = "normal"; +- bias-pull-down; +- qcom,drive-strength = ; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8998-oneplus-common.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/msm8998-oneplus-common.dtsi +deleted file mode 100644 +index 0f5c7828a901..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8998-oneplus-common.dtsi ++++ /dev/null +@@ -1,514 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * OnePlus 5(T) (cheeseburger / dumpling) common device tree source based on msm8998-mtp.dtsi +- * +- * Copyright (c) 2021, Jami Kettunen +- * Copyright (c) 2016, The Linux Foundation. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "msm8998.dtsi" +-#include "pm8998.dtsi" +-#include "pmi8998.dtsi" +-#include "pm8005.dtsi" +- +-/ { +- /* Required for bootloader to select correct board */ +- qcom,msm-id = <292 0x20001>; /* 8998 v2.1 */ +- +- chosen { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- /* Use display framebuffer setup by the UEFI XBL bootloader for simplefb */ +- framebuffer0: framebuffer@9d400000 { +- compatible = "simple-framebuffer"; +- reg = <0x0 0x9d400000 0x0 0x2400000>; +- width = <1080>; +- height = <1920>; +- stride = <(1080 * 4)>; +- format = "a8r8g8b8"; +- }; +- }; +- +- reserved-memory { +- /* Bootloader display framebuffer region */ +- cont_splash_mem: memory@9d400000 { +- reg = <0x0 0x9d400000 0x0 0x2400000>; +- no-map; +- }; +- +- /* For getting crash logs using Android downstream kernels */ +- ramoops@ac000000 { +- compatible = "ramoops"; +- reg = <0x0 0xac000000 0x0 0x200000>; +- console-size = <0x80000>; +- pmsg-size = <0x40000>; +- record-size = <0x8000>; +- ftrace-size = <0x20000>; +- }; +- +- /* +- * The following memory regions on downstream are "dynamically allocated" +- * but given the same addresses every time. Hard code them as these addresses +- * are where the OnePlus signed firmware expects them to be. +- */ +- ipa_fws_region: ipa@f6800000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0xf6800000 0x0 0x5000>; +- no-map; +- }; +- zap_shader_region: gpu@f6900000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0xf6900000 0x0 0x2000>; +- no-map; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- label = "Volume buttons"; +- autorepeat; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&vol_keys_default>; +- +- vol-down { +- label = "Volume down"; +- gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <15>; +- wakeup-source; +- }; +- +- vol-up { +- label = "Volume up"; +- gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <15>; +- wakeup-source; +- }; +- }; +- +- gpio-hall-sensor { +- compatible = "gpio-keys"; +- label = "Hall effect sensor"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&hall_sensor_default>; +- +- hall-sensor { +- label = "Hall Effect Sensor"; +- gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; +- linux,input-type = ; +- linux,code = ; +- linux,can-disable; +- wakeup-source; +- }; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-/* +- * OnePlus' ADSP firmware requires 30 MiB in total, so increase the adsp_mem +- * region by 4 MiB to account for this while relocating the other now +- * conflicting memory nodes accordingly. +- */ +-&adsp_mem { +- reg = <0x0 0x8b200000 0x0 0x1e00000>; +-}; +-&mpss_mem { +- reg = <0x0 0x8d000000 0x0 0x7000000>; +-}; +-&venus_mem { +- reg = <0x0 0x94000000 0x0 0x500000>; +-}; +-&mba_mem { +- reg = <0x0 0x94500000 0x0 0x200000>; +-}; +-&slpi_mem { +- reg = <0x0 0x94700000 0x0 0xf00000>; +-}; +-&ipa_fw_mem { +- reg = <0x0 0x95600000 0x0 0x10000>; +-}; +-&ipa_gsi_mem { +- reg = <0x0 0x95610000 0x0 0x5000>; +-}; +-&gpu_mem { +- reg = <0x0 0x95615000 0x0 0x100000>; +-}; +-&wlan_msa_mem { +- reg = <0x0 0x95715000 0x0 0x100000>; +-}; +- +-&blsp1_i2c5 { +- status = "okay"; +- +- touchscreen@20 { +- compatible = "syna,rmi4-i2c"; +- reg = <0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <125 IRQ_TYPE_EDGE_FALLING>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&ts_int_active &ts_reset_active>; +- +- vdd-supply = <&vreg_l28_3p0>; +- vio-supply = <&vreg_l6a_1p8>; +- +- syna,reset-delay-ms = <20>; +- syna,startup-delay-ms = <20>; +- +- rmi4-f01@1 { +- reg = <0x01>; +- syna,nosleep-mode = <1>; +- }; +- +- rmi4_f12: rmi4-f12@12 { +- reg = <0x12>; +- syna,rezero-wait-ms = <20>; +- syna,sensor-type = <1>; +- touchscreen-x-mm = <68>; +- touchscreen-y-mm = <122>; +- }; +- }; +-}; +- +-&blsp1_uart3 { +- status = "okay"; +- +- bluetooth { +- compatible = "qcom,wcn3990-bt"; +- +- vddio-supply = <&vreg_s4a_1p8>; +- vddxo-supply = <&vreg_l7a_1p8>; +- vddrf-supply = <&vreg_l17a_1p3>; +- vddch0-supply = <&vreg_l25a_3p3>; +- max-speed = <3200000>; +- }; +-}; +- +-&blsp1_uart3_on { +- rx { +- /delete-property/ bias-disable; +- /* +- * Configure a pull-up on 46 (RX). This is needed to +- * avoid garbage data when the TX pin of the Bluetooth +- * module is in tri-state (module powered off or not +- * driving the signal yet). +- */ +- bias-pull-up; +- }; +- +- cts { +- /delete-property/ bias-disable; +- /* +- * Configure a pull-down on 47 (CTS) to match the pull +- * of the Bluetooth module. +- */ +- bias-pull-down; +- }; +-}; +- +-&blsp2_uart1 { +- status = "okay"; +-}; +- +-&pm8005_lsid1 { +- pm8005-regulators { +- compatible = "qcom,pm8005-regulators"; +- +- vdd_s1-supply = <&vph_pwr>; +- +- pm8005_s1: s1 { /* VDD_GFX supply */ +- regulator-min-microvolt = <524000>; +- regulator-max-microvolt = <1100000>; +- regulator-enable-ramp-delay = <500>; +- +- /* hack until we rig up the gpu consumer */ +- regulator-always-on; +- }; +- }; +-}; +- +-&pm8998_gpio { +- vol_keys_default: vol-keys-default { +- pinconf { +- pins = "gpio5", "gpio6"; +- function = "normal"; +- bias-pull-up; +- input-enable; +- qcom,drive-strength = ; +- }; +- }; +-}; +- +-&qusb2phy { +- status = "okay"; +- +- vdda-pll-supply = <&vreg_l12a_1p8>; +- vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; +-}; +- +-&rpm_requests { +- pm8998-regulators { +- compatible = "qcom,rpm-pm8998-regulators"; +- +- vdd_s1-supply = <&vph_pwr>; +- vdd_s2-supply = <&vph_pwr>; +- vdd_s3-supply = <&vph_pwr>; +- vdd_s4-supply = <&vph_pwr>; +- vdd_s5-supply = <&vph_pwr>; +- vdd_s6-supply = <&vph_pwr>; +- vdd_s7-supply = <&vph_pwr>; +- vdd_s8-supply = <&vph_pwr>; +- vdd_s9-supply = <&vph_pwr>; +- vdd_s10-supply = <&vph_pwr>; +- vdd_s11-supply = <&vph_pwr>; +- vdd_s12-supply = <&vph_pwr>; +- vdd_s13-supply = <&vph_pwr>; +- vdd_l1_l27-supply = <&vreg_s7a_1p025>; +- vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>; +- vdd_l3_l11-supply = <&vreg_s7a_1p025>; +- vdd_l4_l5-supply = <&vreg_s7a_1p025>; +- vdd_l6-supply = <&vreg_s5a_2p04>; +- vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>; +- vdd_l9-supply = <&vreg_bob>; +- vdd_l10_l23_l25-supply = <&vreg_bob>; +- vdd_l13_l19_l21-supply = <&vreg_bob>; +- vdd_l16_l28-supply = <&vreg_bob>; +- vdd_l18_l22-supply = <&vreg_bob>; +- vdd_l20_l24-supply = <&vreg_bob>; +- vdd_l26-supply = <&vreg_s3a_1p35>; +- vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; +- +- vreg_s3a_1p35: s3 { +- regulator-min-microvolt = <1352000>; +- regulator-max-microvolt = <1352000>; +- }; +- vreg_s4a_1p8: s4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-allow-set-load; +- }; +- vreg_s5a_2p04: s5 { +- regulator-min-microvolt = <1904000>; +- regulator-max-microvolt = <2040000>; +- }; +- vreg_s7a_1p025: s7 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1028000>; +- }; +- vreg_l1a_0p875: l1 { +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- }; +- vreg_l2a_1p2: l2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- vreg_l3a_1p0: l3 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- vreg_l5a_0p8: l5 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- }; +- vreg_l6a_1p8: l6 { +- regulator-min-microvolt = <1808000>; +- regulator-max-microvolt = <1808000>; +- }; +- vreg_l7a_1p8: l7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l8a_1p2: l8 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- vreg_l9a_1p8: l9 { +- regulator-min-microvolt = <1808000>; +- regulator-max-microvolt = <2960000>; +- }; +- vreg_l10a_1p8: l10 { +- regulator-min-microvolt = <1808000>; +- regulator-max-microvolt = <2960000>; +- }; +- vreg_l11a_1p0: l11 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- }; +- vreg_l12a_1p8: l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l13a_2p95: l13 { +- regulator-min-microvolt = <1808000>; +- regulator-max-microvolt = <2960000>; +- }; +- vreg_l14a_1p88: l14 { +- regulator-min-microvolt = <1880000>; +- regulator-max-microvolt = <1880000>; +- }; +- vreg_l15a_1p8: l15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- vreg_l16a_2p7: l16 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2704000>; +- }; +- vreg_l17a_1p3: l17 { +- regulator-min-microvolt = <1304000>; +- regulator-max-microvolt = <1304000>; +- }; +- vreg_l18a_2p7: l18 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2704000>; +- }; +- vreg_l19a_3p0: l19 { +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3008000>; +- }; +- vreg_l20a_2p95: l20 { +- regulator-min-microvolt = <2960000>; +- regulator-max-microvolt = <2960000>; +- regulator-allow-set-load; +- }; +- vreg_l21a_2p95: l21 { +- regulator-min-microvolt = <2960000>; +- regulator-max-microvolt = <2960000>; +- regulator-allow-set-load; +- regulator-system-load = <800000>; +- }; +- vreg_l22a_2p85: l22 { +- regulator-min-microvolt = <2864000>; +- regulator-max-microvolt = <2864000>; +- }; +- vreg_l23a_3p3: l23 { +- regulator-min-microvolt = <3312000>; +- regulator-max-microvolt = <3312000>; +- }; +- vreg_l24a_3p075: l24 { +- regulator-min-microvolt = <3088000>; +- regulator-max-microvolt = <3088000>; +- }; +- vreg_l25a_3p3: l25 { +- regulator-min-microvolt = <3104000>; +- regulator-max-microvolt = <3312000>; +- }; +- vreg_l26a_1p2: l26 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-allow-set-load; +- }; +- vreg_l28_3p0: l28 { +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3008000>; +- }; +- vreg_lvs1a_1p8: lvs1 { }; +- vreg_lvs2a_1p8: lvs2 { }; +- }; +- +- pmi8998-regulators { +- compatible = "qcom,rpm-pmi8998-regulators"; +- +- vdd_bob-supply = <&vph_pwr>; +- +- vreg_bob: bob { +- regulator-min-microvolt = <3312000>; +- regulator-max-microvolt = <3600000>; +- }; +- }; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <0 4>, <81 4>; +- +- hall_sensor_default: hall-sensor-default { +- pins = "gpio124"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- input-enable; +- }; +- +- ts_int_active: ts-int-active { +- pins = "gpio125"; +- function = "gpio"; +- drive-strength = <8>; +- bias-pull-up; +- }; +- +- ts_reset_active: ts-reset-active { +- pins = "gpio89"; +- function = "gpio"; +- drive-strength = <8>; +- bias-pull-up; +- }; +-}; +- +-&ufshc { +- status = "okay"; +- +- vcc-supply = <&vreg_l20a_2p95>; +- vccq-supply = <&vreg_l26a_1p2>; +- vccq2-supply = <&vreg_s4a_1p8>; +- vcc-max-microamp = <750000>; +- vccq-max-microamp = <560000>; +- vccq2-max-microamp = <750000>; +-}; +- +-&ufsphy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l1a_0p875>; +- vdda-pll-supply = <&vreg_l2a_1p2>; +- vddp-ref-clk-supply = <&vreg_l26a_1p2>; +- vdda-phy-max-microamp = <51400>; +- vdda-pll-max-microamp = <14600>; +- vddp-ref-clk-max-microamp = <100>; +- vddp-ref-clk-always-on; +-}; +- +-&usb3 { +- status = "okay"; +- +- /* Disable USB3 clock requirement as the device only supports USB2 */ +- qcom,select-utmi-as-pipe-clk; +-}; +- +-&usb3_dwc3 { +- /* Drop the unused USB 3 PHY */ +- phys = <&qusb2phy>; +- phy-names = "usb2-phy"; +- +- /* Fastest mode for USB 2 */ +- maximum-speed = "high-speed"; +- +- /* Force to peripheral until we can switch modes */ +- dr_mode = "peripheral"; +-}; +- +-&wifi { +- /* Leave disabled until MSS is functional */ +- vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; +- vdd-1.8-xo-supply = <&vreg_l7a_1p8>; +- vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; +- vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8998-oneplus-dumpling.dts b/scripts/dtc/include-prefixes/arm64/qcom/msm8998-oneplus-dumpling.dts +deleted file mode 100644 +index 544b9b0ae44b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8998-oneplus-dumpling.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * OnePlus 5T (dumpling) device tree +- * +- * Copyright (c) 2021, Jami Kettunen +- */ +- +-#include "msm8998-oneplus-common.dtsi" +- +-/ { +- model = "OnePlus 5T"; +- compatible = "oneplus,dumpling", "qcom,msm8998"; +- /* Required for bootloader to select correct board */ +- qcom,board-id = <8 0 17801 43>; +-}; +- +-/* Update the screen height values from 1920 to 2160 on the 5T */ +-&framebuffer0 { +- height = <2160>; +-}; +- +-/* Adjust digitizer area height to match the 5T's taller panel */ +-&rmi4_f12 { +- touchscreen-y-mm = <137>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/msm8998.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/msm8998.dtsi +deleted file mode 100644 +index 228339f81c32..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/msm8998.dtsi ++++ /dev/null +@@ -1,2475 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&intc>; +- +- qcom,msm-id = <292 0x0>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- chosen { }; +- +- memory@80000000 { +- device_type = "memory"; +- /* We expect the bootloader to fill in the reg */ +- reg = <0x0 0x80000000 0x0 0x0>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- hyp_mem: memory@85800000 { +- reg = <0x0 0x85800000 0x0 0x600000>; +- no-map; +- }; +- +- xbl_mem: memory@85e00000 { +- reg = <0x0 0x85e00000 0x0 0x100000>; +- no-map; +- }; +- +- smem_mem: smem-mem@86000000 { +- reg = <0x0 0x86000000 0x0 0x200000>; +- no-map; +- }; +- +- tz_mem: memory@86200000 { +- reg = <0x0 0x86200000 0x0 0x2d00000>; +- no-map; +- }; +- +- rmtfs_mem: memory@88f00000 { +- compatible = "qcom,rmtfs-mem"; +- reg = <0x0 0x88f00000 0x0 0x200000>; +- no-map; +- +- qcom,client-id = <1>; +- qcom,vmid = <15>; +- }; +- +- spss_mem: memory@8ab00000 { +- reg = <0x0 0x8ab00000 0x0 0x700000>; +- no-map; +- }; +- +- adsp_mem: memory@8b200000 { +- reg = <0x0 0x8b200000 0x0 0x1a00000>; +- no-map; +- }; +- +- mpss_mem: memory@8cc00000 { +- reg = <0x0 0x8cc00000 0x0 0x7000000>; +- no-map; +- }; +- +- venus_mem: memory@93c00000 { +- reg = <0x0 0x93c00000 0x0 0x500000>; +- no-map; +- }; +- +- mba_mem: memory@94100000 { +- reg = <0x0 0x94100000 0x0 0x200000>; +- no-map; +- }; +- +- slpi_mem: memory@94300000 { +- reg = <0x0 0x94300000 0x0 0xf00000>; +- no-map; +- }; +- +- ipa_fw_mem: memory@95200000 { +- reg = <0x0 0x95200000 0x0 0x10000>; +- no-map; +- }; +- +- ipa_gsi_mem: memory@95210000 { +- reg = <0x0 0x95210000 0x0 0x5000>; +- no-map; +- }; +- +- gpu_mem: memory@95600000 { +- reg = <0x0 0x95600000 0x0 0x100000>; +- no-map; +- }; +- +- wlan_msa_mem: memory@95700000 { +- reg = <0x0 0x95700000 0x0 0x100000>; +- no-map; +- }; +- }; +- +- clocks { +- xo: xo-board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <19200000>; +- clock-output-names = "xo_board"; +- }; +- +- sleep_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32764>; +- }; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- CPU0: cpu@0 { +- device_type = "cpu"; +- compatible = "qcom,kryo280"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; +- next-level-cache = <&L2_0>; +- L2_0: l2-cache { +- compatible = "arm,arch-cache"; +- cache-level = <2>; +- }; +- L1_I_0: l1-icache { +- compatible = "arm,arch-cache"; +- }; +- L1_D_0: l1-dcache { +- compatible = "arm,arch-cache"; +- }; +- }; +- +- CPU1: cpu@1 { +- device_type = "cpu"; +- compatible = "qcom,kryo280"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; +- next-level-cache = <&L2_0>; +- L1_I_1: l1-icache { +- compatible = "arm,arch-cache"; +- }; +- L1_D_1: l1-dcache { +- compatible = "arm,arch-cache"; +- }; +- }; +- +- CPU2: cpu@2 { +- device_type = "cpu"; +- compatible = "qcom,kryo280"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; +- next-level-cache = <&L2_0>; +- L1_I_2: l1-icache { +- compatible = "arm,arch-cache"; +- }; +- L1_D_2: l1-dcache { +- compatible = "arm,arch-cache"; +- }; +- }; +- +- CPU3: cpu@3 { +- device_type = "cpu"; +- compatible = "qcom,kryo280"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; +- next-level-cache = <&L2_0>; +- L1_I_3: l1-icache { +- compatible = "arm,arch-cache"; +- }; +- L1_D_3: l1-dcache { +- compatible = "arm,arch-cache"; +- }; +- }; +- +- CPU4: cpu@100 { +- device_type = "cpu"; +- compatible = "qcom,kryo280"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1536>; +- cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; +- next-level-cache = <&L2_1>; +- L2_1: l2-cache { +- compatible = "arm,arch-cache"; +- cache-level = <2>; +- }; +- L1_I_100: l1-icache { +- compatible = "arm,arch-cache"; +- }; +- L1_D_100: l1-dcache { +- compatible = "arm,arch-cache"; +- }; +- }; +- +- CPU5: cpu@101 { +- device_type = "cpu"; +- compatible = "qcom,kryo280"; +- reg = <0x0 0x101>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1536>; +- cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; +- next-level-cache = <&L2_1>; +- L1_I_101: l1-icache { +- compatible = "arm,arch-cache"; +- }; +- L1_D_101: l1-dcache { +- compatible = "arm,arch-cache"; +- }; +- }; +- +- CPU6: cpu@102 { +- device_type = "cpu"; +- compatible = "qcom,kryo280"; +- reg = <0x0 0x102>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1536>; +- cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; +- next-level-cache = <&L2_1>; +- L1_I_102: l1-icache { +- compatible = "arm,arch-cache"; +- }; +- L1_D_102: l1-dcache { +- compatible = "arm,arch-cache"; +- }; +- }; +- +- CPU7: cpu@103 { +- device_type = "cpu"; +- compatible = "qcom,kryo280"; +- reg = <0x0 0x103>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1536>; +- cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; +- next-level-cache = <&L2_1>; +- L1_I_103: l1-icache { +- compatible = "arm,arch-cache"; +- }; +- L1_D_103: l1-dcache { +- compatible = "arm,arch-cache"; +- }; +- }; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&CPU0>; +- }; +- +- core1 { +- cpu = <&CPU1>; +- }; +- +- core2 { +- cpu = <&CPU2>; +- }; +- +- core3 { +- cpu = <&CPU3>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&CPU4>; +- }; +- +- core1 { +- cpu = <&CPU5>; +- }; +- +- core2 { +- cpu = <&CPU6>; +- }; +- +- core3 { +- cpu = <&CPU7>; +- }; +- }; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "little-retention"; +- /* CPU Retention (C2D), L2 Active */ +- arm,psci-suspend-param = <0x00000002>; +- entry-latency-us = <81>; +- exit-latency-us = <86>; +- min-residency-us = <504>; +- }; +- +- LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { +- compatible = "arm,idle-state"; +- idle-state-name = "little-power-collapse"; +- /* CPU + L2 Power Collapse (C3, D4) */ +- arm,psci-suspend-param = <0x40000003>; +- entry-latency-us = <814>; +- exit-latency-us = <4562>; +- min-residency-us = <9183>; +- local-timer-stop; +- }; +- +- BIG_CPU_SLEEP_0: cpu-sleep-1-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "big-retention"; +- /* CPU Retention (C2D), L2 Active */ +- arm,psci-suspend-param = <0x00000002>; +- entry-latency-us = <79>; +- exit-latency-us = <82>; +- min-residency-us = <1302>; +- }; +- +- BIG_CPU_SLEEP_1: cpu-sleep-1-1 { +- compatible = "arm,idle-state"; +- idle-state-name = "big-power-collapse"; +- /* CPU + L2 Power Collapse (C3, D4) */ +- arm,psci-suspend-param = <0x40000003>; +- entry-latency-us = <724>; +- exit-latency-us = <2027>; +- min-residency-us = <9419>; +- local-timer-stop; +- }; +- }; +- }; +- +- firmware { +- scm { +- compatible = "qcom,scm-msm8998", "qcom,scm"; +- }; +- }; +- +- tcsr_mutex: hwlock { +- compatible = "qcom,tcsr-mutex"; +- syscon = <&tcsr_mutex_regs 0 0x1000>; +- #hwlock-cells = <1>; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- rpm-glink { +- compatible = "qcom,glink-rpm"; +- +- interrupts = ; +- qcom,rpm-msg-ram = <&rpm_msg_ram>; +- mboxes = <&apcs_glb 0>; +- +- rpm_requests: rpm-requests { +- compatible = "qcom,rpm-msm8998"; +- qcom,glink-channels = "rpm_requests"; +- +- rpmcc: clock-controller { +- compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; +- #clock-cells = <1>; +- }; +- +- rpmpd: power-controller { +- compatible = "qcom,msm8998-rpmpd"; +- #power-domain-cells = <1>; +- operating-points-v2 = <&rpmpd_opp_table>; +- +- rpmpd_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- rpmpd_opp_ret: opp1 { +- opp-level = ; +- }; +- +- rpmpd_opp_ret_plus: opp2 { +- opp-level = ; +- }; +- +- rpmpd_opp_min_svs: opp3 { +- opp-level = ; +- }; +- +- rpmpd_opp_low_svs: opp4 { +- opp-level = ; +- }; +- +- rpmpd_opp_svs: opp5 { +- opp-level = ; +- }; +- +- rpmpd_opp_svs_plus: opp6 { +- opp-level = ; +- }; +- +- rpmpd_opp_nom: opp7 { +- opp-level = ; +- }; +- +- rpmpd_opp_nom_plus: opp8 { +- opp-level = ; +- }; +- +- rpmpd_opp_turbo: opp9 { +- opp-level = ; +- }; +- +- rpmpd_opp_turbo_plus: opp10 { +- opp-level = ; +- }; +- }; +- }; +- }; +- }; +- +- smem { +- compatible = "qcom,smem"; +- memory-region = <&smem_mem>; +- hwlocks = <&tcsr_mutex 3>; +- }; +- +- smp2p-lpass { +- compatible = "qcom,smp2p"; +- qcom,smem = <443>, <429>; +- +- interrupts = ; +- +- mboxes = <&apcs_glb 10>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <2>; +- +- adsp_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- adsp_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-mpss { +- compatible = "qcom,smp2p"; +- qcom,smem = <435>, <428>; +- interrupts = ; +- mboxes = <&apcs_glb 14>; +- qcom,local-pid = <0>; +- qcom,remote-pid = <1>; +- +- modem_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- modem_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-slpi { +- compatible = "qcom,smp2p"; +- qcom,smem = <481>, <430>; +- interrupts = ; +- mboxes = <&apcs_glb 26>; +- qcom,local-pid = <0>; +- qcom,remote-pid = <3>; +- +- slpi_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- slpi_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- thermal-zones { +- cpu0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 1>; +- +- trips { +- cpu0_alert0: trip-point0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu0_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 2>; +- +- trips { +- cpu1_alert0: trip-point0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu1_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 3>; +- +- trips { +- cpu2_alert0: trip-point0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu2_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 4>; +- +- trips { +- cpu3_alert0: trip-point0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu3_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu4-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 7>; +- +- trips { +- cpu4_alert0: trip-point0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu4_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu5-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 8>; +- +- trips { +- cpu5_alert0: trip-point0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu5_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu6-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 9>; +- +- trips { +- cpu6_alert0: trip-point0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu6_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu7-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 10>; +- +- trips { +- cpu7_alert0: trip-point0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu7_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- gpu-thermal-bottom { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 12>; +- +- trips { +- gpu1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- gpu-thermal-top { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 13>; +- +- trips { +- gpu2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- clust0-mhm-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 5>; +- +- trips { +- cluster0_mhm_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- clust1-mhm-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 6>; +- +- trips { +- cluster1_mhm_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- cluster1-l2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 11>; +- +- trips { +- cluster1_l2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- modem-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 1>; +- +- trips { +- modem_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- mem-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 2>; +- +- trips { +- mem_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- wlan-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 3>; +- +- trips { +- wlan_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- q6-dsp-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 4>; +- +- trips { +- q6_dsp_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- camera-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 5>; +- +- trips { +- camera_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- multimedia-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 6>; +- +- trips { +- multimedia_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- soc: soc { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0 0xffffffff>; +- compatible = "simple-bus"; +- +- gcc: clock-controller@100000 { +- compatible = "qcom,gcc-msm8998"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- reg = <0x00100000 0xb0000>; +- }; +- +- rpm_msg_ram: sram@778000 { +- compatible = "qcom,rpm-msg-ram"; +- reg = <0x00778000 0x7000>; +- }; +- +- qfprom: qfprom@780000 { +- compatible = "qcom,qfprom"; +- reg = <0x00780000 0x621c>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- qusb2_hstx_trim: hstx-trim@423a { +- reg = <0x423a 0x1>; +- bits = <0 4>; +- }; +- }; +- +- tsens0: thermal@10ab000 { +- compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; +- reg = <0x010ab000 0x1000>, /* TM */ +- <0x010aa000 0x1000>; /* SROT */ +- #qcom,sensors = <14>; +- interrupts = , +- ; +- interrupt-names = "uplow", "critical"; +- #thermal-sensor-cells = <1>; +- }; +- +- tsens1: thermal@10ae000 { +- compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; +- reg = <0x010ae000 0x1000>, /* TM */ +- <0x010ad000 0x1000>; /* SROT */ +- #qcom,sensors = <8>; +- interrupts = , +- ; +- interrupt-names = "uplow", "critical"; +- #thermal-sensor-cells = <1>; +- }; +- +- anoc1_smmu: iommu@1680000 { +- compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; +- reg = <0x01680000 0x10000>; +- #iommu-cells = <1>; +- +- #global-interrupts = <0>; +- interrupts = +- , +- , +- , +- , +- , +- ; +- }; +- +- anoc2_smmu: iommu@16c0000 { +- compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; +- reg = <0x016c0000 0x40000>; +- #iommu-cells = <1>; +- +- #global-interrupts = <0>; +- interrupts = +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- }; +- +- pcie0: pci@1c00000 { +- compatible = "qcom,pcie-msm8996"; +- reg = <0x01c00000 0x2000>, +- <0x1b000000 0xf1d>, +- <0x1b000f20 0xa8>, +- <0x1b100000 0x100000>; +- reg-names = "parf", "dbi", "elbi", "config"; +- device_type = "pci"; +- linux,pci-domain = <0>; +- bus-range = <0x00 0xff>; +- #address-cells = <3>; +- #size-cells = <2>; +- num-lanes = <1>; +- phys = <&pciephy>; +- phy-names = "pciephy"; +- status = "disabled"; +- +- ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, +- <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; +- +- #interrupt-cells = <1>; +- interrupts = ; +- interrupt-names = "msi"; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>, +- <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>; +- +- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, +- <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, +- <&gcc GCC_PCIE_0_SLV_AXI_CLK>, +- <&gcc GCC_PCIE_0_CFG_AHB_CLK>, +- <&gcc GCC_PCIE_0_AUX_CLK>; +- clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux"; +- +- power-domains = <&gcc PCIE_0_GDSC>; +- iommu-map = <0x100 &anoc1_smmu 0x1480 1>; +- perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; +- }; +- +- pcie_phy: phy@1c06000 { +- compatible = "qcom,msm8998-qmp-pcie-phy"; +- reg = <0x01c06000 0x18c>; +- #address-cells = <1>; +- #size-cells = <1>; +- status = "disabled"; +- ranges; +- +- clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, +- <&gcc GCC_PCIE_0_CFG_AHB_CLK>, +- <&gcc GCC_PCIE_CLKREF_CLK>; +- clock-names = "aux", "cfg_ahb", "ref"; +- +- resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; +- reset-names = "phy", "common"; +- +- vdda-phy-supply = <&vreg_l1a_0p875>; +- vdda-pll-supply = <&vreg_l2a_1p2>; +- +- pciephy: lane@1c06800 { +- reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; +- #phy-cells = <0>; +- +- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; +- clock-names = "pipe0"; +- clock-output-names = "pcie_0_pipe_clk_src"; +- #clock-cells = <0>; +- }; +- }; +- +- ufshc: ufshc@1da4000 { +- compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; +- reg = <0x01da4000 0x2500>; +- interrupts = ; +- phys = <&ufsphy_lanes>; +- phy-names = "ufsphy"; +- lanes-per-direction = <2>; +- power-domains = <&gcc UFS_GDSC>; +- status = "disabled"; +- #reset-cells = <1>; +- +- clock-names = +- "core_clk", +- "bus_aggr_clk", +- "iface_clk", +- "core_clk_unipro", +- "ref_clk", +- "tx_lane0_sync_clk", +- "rx_lane0_sync_clk", +- "rx_lane1_sync_clk"; +- clocks = +- <&gcc GCC_UFS_AXI_CLK>, +- <&gcc GCC_AGGRE1_UFS_AXI_CLK>, +- <&gcc GCC_UFS_AHB_CLK>, +- <&gcc GCC_UFS_UNIPRO_CORE_CLK>, +- <&rpmcc RPM_SMD_LN_BB_CLK1>, +- <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, +- <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, +- <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; +- freq-table-hz = +- <50000000 200000000>, +- <0 0>, +- <0 0>, +- <37500000 150000000>, +- <0 0>, +- <0 0>, +- <0 0>, +- <0 0>; +- +- resets = <&gcc GCC_UFS_BCR>; +- reset-names = "rst"; +- }; +- +- ufsphy: phy@1da7000 { +- compatible = "qcom,msm8998-qmp-ufs-phy"; +- reg = <0x01da7000 0x18c>; +- #address-cells = <1>; +- #size-cells = <1>; +- status = "disabled"; +- ranges; +- +- clock-names = +- "ref", +- "ref_aux"; +- clocks = +- <&gcc GCC_UFS_CLKREF_CLK>, +- <&gcc GCC_UFS_PHY_AUX_CLK>; +- +- reset-names = "ufsphy"; +- resets = <&ufshc 0>; +- +- ufsphy_lanes: lanes@1da7400 { +- reg = <0x01da7400 0x128>, +- <0x01da7600 0x1fc>, +- <0x01da7c00 0x1dc>, +- <0x01da7800 0x128>, +- <0x01da7a00 0x1fc>; +- #phy-cells = <0>; +- }; +- }; +- +- tcsr_mutex_regs: syscon@1f40000 { +- compatible = "syscon"; +- reg = <0x01f40000 0x40000>; +- }; +- +- tlmm: pinctrl@3400000 { +- compatible = "qcom,msm8998-pinctrl"; +- reg = <0x03400000 0xc00000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <0x2>; +- interrupt-controller; +- #interrupt-cells = <0x2>; +- +- sdc2_clk_on: sdc2_clk_on { +- config { +- pins = "sdc2_clk"; +- bias-disable; +- drive-strength = <16>; +- }; +- }; +- +- sdc2_clk_off: sdc2_clk_off { +- config { +- pins = "sdc2_clk"; +- bias-disable; +- drive-strength = <2>; +- }; +- }; +- +- sdc2_cmd_on: sdc2_cmd_on { +- config { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- }; +- +- sdc2_cmd_off: sdc2_cmd_off { +- config { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +- +- sdc2_data_on: sdc2_data_on { +- config { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- }; +- +- sdc2_data_off: sdc2_data_off { +- config { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +- +- sdc2_cd_on: sdc2_cd_on { +- mux { +- pins = "gpio95"; +- function = "gpio"; +- }; +- +- config { +- pins = "gpio95"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +- +- sdc2_cd_off: sdc2_cd_off { +- mux { +- pins = "gpio95"; +- function = "gpio"; +- }; +- +- config { +- pins = "gpio95"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +- +- blsp1_uart3_on: blsp1_uart3_on { +- tx { +- pins = "gpio45"; +- function = "blsp_uart3_a"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- rx { +- pins = "gpio46"; +- function = "blsp_uart3_a"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- cts { +- pins = "gpio47"; +- function = "blsp_uart3_a"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- rfr { +- pins = "gpio48"; +- function = "blsp_uart3_a"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- blsp1_i2c1_default: blsp1-i2c1-default { +- pins = "gpio2", "gpio3"; +- function = "blsp_i2c1"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- blsp1_i2c1_sleep: blsp1-i2c1-sleep { +- pins = "gpio2", "gpio3"; +- function = "blsp_i2c1"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- blsp1_i2c2_default: blsp1-i2c2-default { +- pins = "gpio32", "gpio33"; +- function = "blsp_i2c2"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- blsp1_i2c2_sleep: blsp1-i2c2-sleep { +- pins = "gpio32", "gpio33"; +- function = "blsp_i2c2"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- blsp1_i2c3_default: blsp1-i2c3-default { +- pins = "gpio47", "gpio48"; +- function = "blsp_i2c3"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- blsp1_i2c3_sleep: blsp1-i2c3-sleep { +- pins = "gpio47", "gpio48"; +- function = "blsp_i2c3"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- blsp1_i2c4_default: blsp1-i2c4-default { +- pins = "gpio10", "gpio11"; +- function = "blsp_i2c4"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- blsp1_i2c4_sleep: blsp1-i2c4-sleep { +- pins = "gpio10", "gpio11"; +- function = "blsp_i2c4"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- blsp1_i2c5_default: blsp1-i2c5-default { +- pins = "gpio87", "gpio88"; +- function = "blsp_i2c5"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- blsp1_i2c5_sleep: blsp1-i2c5-sleep { +- pins = "gpio87", "gpio88"; +- function = "blsp_i2c5"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- blsp1_i2c6_default: blsp1-i2c6-default { +- pins = "gpio43", "gpio44"; +- function = "blsp_i2c6"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- blsp1_i2c6_sleep: blsp1-i2c6-sleep { +- pins = "gpio43", "gpio44"; +- function = "blsp_i2c6"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ +- blsp2_i2c1_default: blsp2-i2c1-default { +- pins = "gpio55", "gpio56"; +- function = "blsp_i2c7"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- blsp2_i2c1_sleep: blsp2-i2c1-sleep { +- pins = "gpio55", "gpio56"; +- function = "blsp_i2c7"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- blsp2_i2c2_default: blsp2-i2c2-default { +- pins = "gpio6", "gpio7"; +- function = "blsp_i2c8"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- blsp2_i2c2_sleep: blsp2-i2c2-sleep { +- pins = "gpio6", "gpio7"; +- function = "blsp_i2c8"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- blsp2_i2c3_default: blsp2-i2c3-default { +- pins = "gpio51", "gpio52"; +- function = "blsp_i2c9"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- blsp2_i2c3_sleep: blsp2-i2c3-sleep { +- pins = "gpio51", "gpio52"; +- function = "blsp_i2c9"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- blsp2_i2c4_default: blsp2-i2c4-default { +- pins = "gpio67", "gpio68"; +- function = "blsp_i2c10"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- blsp2_i2c4_sleep: blsp2-i2c4-sleep { +- pins = "gpio67", "gpio68"; +- function = "blsp_i2c10"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- blsp2_i2c5_default: blsp2-i2c5-default { +- pins = "gpio60", "gpio61"; +- function = "blsp_i2c11"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- blsp2_i2c5_sleep: blsp2-i2c5-sleep { +- pins = "gpio60", "gpio61"; +- function = "blsp_i2c11"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- blsp2_i2c6_default: blsp2-i2c6-default { +- pins = "gpio83", "gpio84"; +- function = "blsp_i2c12"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- blsp2_i2c6_sleep: blsp2-i2c6-sleep { +- pins = "gpio83", "gpio84"; +- function = "blsp_i2c12"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- }; +- +- remoteproc_mss: remoteproc@4080000 { +- compatible = "qcom,msm8998-mss-pil"; +- reg = <0x04080000 0x100>, <0x04180000 0x20>; +- reg-names = "qdsp6", "rmb"; +- +- interrupts-extended = +- <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack", +- "shutdown-ack"; +- +- clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, +- <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, +- <&gcc GCC_BOOT_ROM_AHB_CLK>, +- <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, +- <&gcc GCC_MSS_SNOC_AXI_CLK>, +- <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, +- <&rpmcc RPM_SMD_QDSS_CLK>, +- <&rpmcc RPM_SMD_XO_CLK_SRC>; +- clock-names = "iface", "bus", "mem", "gpll0_mss", +- "snoc_axi", "mnoc_axi", "qdss", "xo"; +- +- qcom,smem-states = <&modem_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- resets = <&gcc GCC_MSS_RESTART>; +- reset-names = "mss_restart"; +- +- qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; +- +- power-domains = <&rpmpd MSM8998_VDDCX>, +- <&rpmpd MSM8998_VDDMX>; +- power-domain-names = "cx", "mx"; +- +- status = "disabled"; +- +- mba { +- memory-region = <&mba_mem>; +- }; +- +- mpss { +- memory-region = <&mpss_mem>; +- }; +- +- glink-edge { +- interrupts = ; +- label = "modem"; +- qcom,remote-pid = <1>; +- mboxes = <&apcs_glb 15>; +- }; +- }; +- +- gpucc: clock-controller@5065000 { +- compatible = "qcom,msm8998-gpucc"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- reg = <0x05065000 0x9000>; +- +- clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, +- <&gcc GPLL0_OUT_MAIN>; +- clock-names = "xo", +- "gpll0"; +- }; +- +- remoteproc_slpi: remoteproc@5800000 { +- compatible = "qcom,msm8998-slpi-pas"; +- reg = <0x05800000 0x4040>; +- +- interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>, +- <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack"; +- +- px-supply = <&vreg_lvs2a_1p8>; +- +- clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, +- <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; +- clock-names = "xo", "aggre2"; +- +- memory-region = <&slpi_mem>; +- +- qcom,smem-states = <&slpi_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- power-domains = <&rpmpd MSM8998_SSCCX>; +- power-domain-names = "ssc_cx"; +- +- status = "disabled"; +- +- glink-edge { +- interrupts = ; +- label = "dsps"; +- qcom,remote-pid = <3>; +- mboxes = <&apcs_glb 27>; +- }; +- }; +- +- stm: stm@6002000 { +- compatible = "arm,coresight-stm", "arm,primecell"; +- reg = <0x06002000 0x1000>, +- <0x16280000 0x180000>; +- reg-names = "stm-base", "stm-data-base"; +- status = "disabled"; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- out-ports { +- port { +- stm_out: endpoint { +- remote-endpoint = <&funnel0_in7>; +- }; +- }; +- }; +- }; +- +- funnel1: funnel@6041000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0x06041000 0x1000>; +- status = "disabled"; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- out-ports { +- port { +- funnel0_out: endpoint { +- remote-endpoint = +- <&merge_funnel_in0>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@7 { +- reg = <7>; +- funnel0_in7: endpoint { +- remote-endpoint = <&stm_out>; +- }; +- }; +- }; +- }; +- +- funnel2: funnel@6042000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0x06042000 0x1000>; +- status = "disabled"; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- out-ports { +- port { +- funnel1_out: endpoint { +- remote-endpoint = +- <&merge_funnel_in1>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@6 { +- reg = <6>; +- funnel1_in6: endpoint { +- remote-endpoint = +- <&apss_merge_funnel_out>; +- }; +- }; +- }; +- }; +- +- funnel3: funnel@6045000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0x06045000 0x1000>; +- status = "disabled"; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- out-ports { +- port { +- merge_funnel_out: endpoint { +- remote-endpoint = +- <&etf_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- merge_funnel_in0: endpoint { +- remote-endpoint = +- <&funnel0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- merge_funnel_in1: endpoint { +- remote-endpoint = +- <&funnel1_out>; +- }; +- }; +- }; +- }; +- +- replicator1: replicator@6046000 { +- compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; +- reg = <0x06046000 0x1000>; +- status = "disabled"; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- out-ports { +- port { +- replicator_out: endpoint { +- remote-endpoint = <&etr_in>; +- }; +- }; +- }; +- +- in-ports { +- port { +- replicator_in: endpoint { +- remote-endpoint = <&etf_out>; +- }; +- }; +- }; +- }; +- +- etf: etf@6047000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0x06047000 0x1000>; +- status = "disabled"; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- out-ports { +- port { +- etf_out: endpoint { +- remote-endpoint = +- <&replicator_in>; +- }; +- }; +- }; +- +- in-ports { +- port { +- etf_in: endpoint { +- remote-endpoint = +- <&merge_funnel_out>; +- }; +- }; +- }; +- }; +- +- etr: etr@6048000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0x06048000 0x1000>; +- status = "disabled"; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- arm,scatter-gather; +- +- in-ports { +- port { +- etr_in: endpoint { +- remote-endpoint = +- <&replicator_out>; +- }; +- }; +- }; +- }; +- +- etm1: etm@7840000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0x07840000 0x1000>; +- status = "disabled"; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- cpu = <&CPU0>; +- +- out-ports { +- port { +- etm0_out: endpoint { +- remote-endpoint = +- <&apss_funnel_in0>; +- }; +- }; +- }; +- }; +- +- etm2: etm@7940000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0x07940000 0x1000>; +- status = "disabled"; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- cpu = <&CPU1>; +- +- out-ports { +- port { +- etm1_out: endpoint { +- remote-endpoint = +- <&apss_funnel_in1>; +- }; +- }; +- }; +- }; +- +- etm3: etm@7a40000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0x07a40000 0x1000>; +- status = "disabled"; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- cpu = <&CPU2>; +- +- out-ports { +- port { +- etm2_out: endpoint { +- remote-endpoint = +- <&apss_funnel_in2>; +- }; +- }; +- }; +- }; +- +- etm4: etm@7b40000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0x07b40000 0x1000>; +- status = "disabled"; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- cpu = <&CPU3>; +- +- out-ports { +- port { +- etm3_out: endpoint { +- remote-endpoint = +- <&apss_funnel_in3>; +- }; +- }; +- }; +- }; +- +- funnel4: funnel@7b60000 { /* APSS Funnel */ +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0x07b60000 0x1000>; +- status = "disabled"; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- out-ports { +- port { +- apss_funnel_out: endpoint { +- remote-endpoint = +- <&apss_merge_funnel_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- apss_funnel_in0: endpoint { +- remote-endpoint = +- <&etm0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- apss_funnel_in1: endpoint { +- remote-endpoint = +- <&etm1_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- apss_funnel_in2: endpoint { +- remote-endpoint = +- <&etm2_out>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- apss_funnel_in3: endpoint { +- remote-endpoint = +- <&etm3_out>; +- }; +- }; +- +- port@4 { +- reg = <4>; +- apss_funnel_in4: endpoint { +- remote-endpoint = +- <&etm4_out>; +- }; +- }; +- +- port@5 { +- reg = <5>; +- apss_funnel_in5: endpoint { +- remote-endpoint = +- <&etm5_out>; +- }; +- }; +- +- port@6 { +- reg = <6>; +- apss_funnel_in6: endpoint { +- remote-endpoint = +- <&etm6_out>; +- }; +- }; +- +- port@7 { +- reg = <7>; +- apss_funnel_in7: endpoint { +- remote-endpoint = +- <&etm7_out>; +- }; +- }; +- }; +- }; +- +- funnel5: funnel@7b70000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0x07b70000 0x1000>; +- status = "disabled"; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- out-ports { +- port { +- apss_merge_funnel_out: endpoint { +- remote-endpoint = +- <&funnel1_in6>; +- }; +- }; +- }; +- +- in-ports { +- port { +- apss_merge_funnel_in: endpoint { +- remote-endpoint = +- <&apss_funnel_out>; +- }; +- }; +- }; +- }; +- +- etm5: etm@7c40000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0x07c40000 0x1000>; +- status = "disabled"; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- cpu = <&CPU4>; +- +- port{ +- etm4_out: endpoint { +- remote-endpoint = <&apss_funnel_in4>; +- }; +- }; +- }; +- +- etm6: etm@7d40000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0x07d40000 0x1000>; +- status = "disabled"; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- cpu = <&CPU5>; +- +- port{ +- etm5_out: endpoint { +- remote-endpoint = <&apss_funnel_in5>; +- }; +- }; +- }; +- +- etm7: etm@7e40000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0x07e40000 0x1000>; +- status = "disabled"; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- cpu = <&CPU6>; +- +- port{ +- etm6_out: endpoint { +- remote-endpoint = <&apss_funnel_in6>; +- }; +- }; +- }; +- +- etm8: etm@7f40000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0x07f40000 0x1000>; +- status = "disabled"; +- +- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +- clock-names = "apb_pclk", "atclk"; +- +- cpu = <&CPU7>; +- +- port{ +- etm7_out: endpoint { +- remote-endpoint = <&apss_funnel_in7>; +- }; +- }; +- }; +- +- spmi_bus: spmi@800f000 { +- compatible = "qcom,spmi-pmic-arb"; +- reg = <0x0800f000 0x1000>, +- <0x08400000 0x1000000>, +- <0x09400000 0x1000000>, +- <0x0a400000 0x220000>, +- <0x0800a000 0x3000>; +- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; +- interrupt-names = "periph_irq"; +- interrupts = ; +- qcom,ee = <0>; +- qcom,channel = <0>; +- #address-cells = <2>; +- #size-cells = <0>; +- interrupt-controller; +- #interrupt-cells = <4>; +- cell-index = <0>; +- }; +- +- usb3: usb@a8f8800 { +- compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; +- reg = <0x0a8f8800 0x400>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, +- <&gcc GCC_USB30_MASTER_CLK>, +- <&gcc GCC_AGGRE1_USB3_AXI_CLK>, +- <&gcc GCC_USB30_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_SLEEP_CLK>; +- clock-names = "cfg_noc", "core", "iface", "mock_utmi", +- "sleep"; +- +- assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_MASTER_CLK>; +- assigned-clock-rates = <19200000>, <120000000>; +- +- interrupts = , +- ; +- interrupt-names = "hs_phy_irq", "ss_phy_irq"; +- +- power-domains = <&gcc USB_30_GDSC>; +- +- resets = <&gcc GCC_USB_30_BCR>; +- +- usb3_dwc3: dwc3@a800000 { +- compatible = "snps,dwc3"; +- reg = <0x0a800000 0xcd00>; +- interrupts = ; +- snps,dis_u2_susphy_quirk; +- snps,dis_enblslpm_quirk; +- phys = <&qusb2phy>, <&usb1_ssphy>; +- phy-names = "usb2-phy", "usb3-phy"; +- snps,has-lpm-erratum; +- snps,hird-threshold = /bits/ 8 <0x10>; +- }; +- }; +- +- usb3phy: phy@c010000 { +- compatible = "qcom,msm8998-qmp-usb3-phy"; +- reg = <0x0c010000 0x18c>; +- status = "disabled"; +- #clock-cells = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, +- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, +- <&gcc GCC_USB3_CLKREF_CLK>; +- clock-names = "aux", "cfg_ahb", "ref"; +- +- resets = <&gcc GCC_USB3_PHY_BCR>, +- <&gcc GCC_USB3PHY_PHY_BCR>; +- reset-names = "phy", "common"; +- +- usb1_ssphy: lane@c010200 { +- reg = <0xc010200 0x128>, +- <0xc010400 0x200>, +- <0xc010c00 0x20c>, +- <0xc010600 0x128>, +- <0xc010800 0x200>; +- #phy-cells = <0>; +- clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; +- clock-names = "pipe0"; +- clock-output-names = "usb3_phy_pipe_clk_src"; +- }; +- }; +- +- qusb2phy: phy@c012000 { +- compatible = "qcom,msm8998-qusb2-phy"; +- reg = <0x0c012000 0x2a8>; +- status = "disabled"; +- #phy-cells = <0>; +- +- clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, +- <&gcc GCC_RX1_USB2_CLKREF_CLK>; +- clock-names = "cfg_ahb", "ref"; +- +- resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; +- +- nvmem-cells = <&qusb2_hstx_trim>; +- }; +- +- sdhc2: sdhci@c0a4900 { +- compatible = "qcom,sdhci-msm-v4"; +- reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; +- reg-names = "hc_mem", "core_mem"; +- +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- +- clock-names = "iface", "core", "xo"; +- clocks = <&gcc GCC_SDCC2_AHB_CLK>, +- <&gcc GCC_SDCC2_APPS_CLK>, +- <&xo>; +- bus-width = <4>; +- status = "disabled"; +- }; +- +- blsp1_dma: dma-controller@c144000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0x0c144000 0x25000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- qcom,controlled-remotely; +- num-channels = <18>; +- qcom,num-ees = <4>; +- }; +- +- blsp1_uart3: serial@c171000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x0c171000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp1_uart3_on>; +- status = "disabled"; +- }; +- +- blsp1_i2c1: i2c@c175000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c175000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp1_i2c1_default>; +- pinctrl-1 = <&blsp1_i2c1_sleep>; +- clock-frequency = <400000>; +- +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- blsp1_i2c2: i2c@c176000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c176000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp1_i2c2_default>; +- pinctrl-1 = <&blsp1_i2c2_sleep>; +- clock-frequency = <400000>; +- +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- blsp1_i2c3: i2c@c177000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c177000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp1_i2c3_default>; +- pinctrl-1 = <&blsp1_i2c3_sleep>; +- clock-frequency = <400000>; +- +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- blsp1_i2c4: i2c@c178000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c178000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp1_i2c4_default>; +- pinctrl-1 = <&blsp1_i2c4_sleep>; +- clock-frequency = <400000>; +- +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- blsp1_i2c5: i2c@c179000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c179000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp1_i2c5_default>; +- pinctrl-1 = <&blsp1_i2c5_sleep>; +- clock-frequency = <400000>; +- +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- blsp1_i2c6: i2c@c17a000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c17a000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp1_i2c6_default>; +- pinctrl-1 = <&blsp1_i2c6_sleep>; +- clock-frequency = <400000>; +- +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- blsp2_dma: dma@c184000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0x0c184000 0x25000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- qcom,controlled-remotely; +- num-channels = <18>; +- qcom,num-ees = <4>; +- }; +- +- blsp2_uart1: serial@c1b0000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x0c1b0000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, +- <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- status = "disabled"; +- }; +- +- blsp2_i2c1: i2c@c1b5000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c1b5000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, +- <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp2_i2c1_default>; +- pinctrl-1 = <&blsp2_i2c1_sleep>; +- clock-frequency = <400000>; +- +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- blsp2_i2c2: i2c@c1b6000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c1b6000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, +- <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp2_i2c2_default>; +- pinctrl-1 = <&blsp2_i2c2_sleep>; +- clock-frequency = <400000>; +- +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- blsp2_i2c3: i2c@c1b7000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c1b7000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, +- <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp2_i2c3_default>; +- pinctrl-1 = <&blsp2_i2c3_sleep>; +- clock-frequency = <400000>; +- +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- blsp2_i2c4: i2c@c1b8000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c1b8000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, +- <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp2_i2c4_default>; +- pinctrl-1 = <&blsp2_i2c4_sleep>; +- clock-frequency = <400000>; +- +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- blsp2_i2c5: i2c@c1b9000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c1b9000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, +- <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp2_i2c5_default>; +- pinctrl-1 = <&blsp2_i2c5_sleep>; +- clock-frequency = <400000>; +- +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- blsp2_i2c6: i2c@c1ba000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c1ba000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, +- <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp2_i2c6_default>; +- pinctrl-1 = <&blsp2_i2c6_sleep>; +- clock-frequency = <400000>; +- +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- remoteproc_adsp: remoteproc@17300000 { +- compatible = "qcom,msm8998-adsp-pas"; +- reg = <0x17300000 0x4040>; +- +- interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack"; +- +- clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; +- clock-names = "xo"; +- +- memory-region = <&adsp_mem>; +- +- qcom,smem-states = <&adsp_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- power-domains = <&rpmpd MSM8998_VDDCX>; +- power-domain-names = "cx"; +- +- status = "disabled"; +- +- glink-edge { +- interrupts = ; +- label = "lpass"; +- qcom,remote-pid = <2>; +- mboxes = <&apcs_glb 9>; +- }; +- }; +- +- apcs_glb: mailbox@17911000 { +- compatible = "qcom,msm8998-apcs-hmss-global"; +- reg = <0x17911000 0x1000>; +- +- #mbox-cells = <1>; +- }; +- +- timer@17920000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "arm,armv7-timer-mem"; +- reg = <0x17920000 0x1000>; +- +- frame@17921000 { +- frame-number = <0>; +- interrupts = , +- ; +- reg = <0x17921000 0x1000>, +- <0x17922000 0x1000>; +- }; +- +- frame@17923000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0x17923000 0x1000>; +- status = "disabled"; +- }; +- +- frame@17924000 { +- frame-number = <2>; +- interrupts = ; +- reg = <0x17924000 0x1000>; +- status = "disabled"; +- }; +- +- frame@17925000 { +- frame-number = <3>; +- interrupts = ; +- reg = <0x17925000 0x1000>; +- status = "disabled"; +- }; +- +- frame@17926000 { +- frame-number = <4>; +- interrupts = ; +- reg = <0x17926000 0x1000>; +- status = "disabled"; +- }; +- +- frame@17927000 { +- frame-number = <5>; +- interrupts = ; +- reg = <0x17927000 0x1000>; +- status = "disabled"; +- }; +- +- frame@17928000 { +- frame-number = <6>; +- interrupts = ; +- reg = <0x17928000 0x1000>; +- status = "disabled"; +- }; +- }; +- +- intc: interrupt-controller@17a00000 { +- compatible = "arm,gic-v3"; +- reg = <0x17a00000 0x10000>, /* GICD */ +- <0x17b00000 0x100000>; /* GICR * 8 */ +- #interrupt-cells = <3>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- interrupt-controller; +- #redistributor-regions = <1>; +- redistributor-stride = <0x0 0x20000>; +- interrupts = ; +- }; +- +- wifi: wifi@18800000 { +- compatible = "qcom,wcn3990-wifi"; +- status = "disabled"; +- reg = <0x18800000 0x800000>; +- reg-names = "membase"; +- memory-region = <&wlan_msa_mem>; +- clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>; +- clock-names = "cxo_ref_clk_pin"; +- interrupts = +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- iommus = <&anoc2_smmu 0x1900>, +- <&anoc2_smmu 0x1901>; +- qcom,snoc-host-cap-8bit-quirk; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pm6150.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pm6150.dtsi +deleted file mode 100644 +index 8a4972e6a24c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pm6150.dtsi ++++ /dev/null +@@ -1,106 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-// Copyright (c) 2019, The Linux Foundation. All rights reserved. +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- thermal-zones { +- pm6150_thermal: pm6150-thermal { +- polling-delay-passive = <100>; +- polling-delay = <0>; +- thermal-sensors = <&pm6150_temp>; +- +- trips { +- pm6150_trip0: trip0 { +- temperature = <95000>; +- hysteresis = <0>; +- type = "passive"; +- }; +- +- pm6150_crit: crit { +- temperature = <115000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +- +-&spmi_bus { +- pm6150_lsid0: pmic@0 { +- compatible = "qcom,pm6150", "qcom,spmi-pmic"; +- reg = <0x0 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm6150_pon: pon@800 { +- compatible = "qcom,pm8998-pon"; +- reg = <0x800>; +- mode-bootloader = <0x2>; +- mode-recovery = <0x1>; +- +- pm6150_pwrkey: pwrkey { +- compatible = "qcom,pm8941-pwrkey"; +- interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; +- debounce = <15625>; +- bias-pull-up; +- linux,code = ; +- }; +- }; +- +- pm6150_temp: temp-alarm@2400 { +- compatible = "qcom,spmi-temp-alarm"; +- reg = <0x2400>; +- interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; +- io-channels = <&pm6150_adc ADC5_DIE_TEMP>; +- io-channel-names = "thermal"; +- #thermal-sensor-cells = <0>; +- }; +- +- pm6150_adc: adc@3100 { +- compatible = "qcom,spmi-adc5"; +- reg = <0x3100>; +- interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; +- #address-cells = <1>; +- #size-cells = <0>; +- #io-channel-cells = <1>; +- +- adc-chan@6 { +- reg = ; +- label = "die_temp"; +- }; +- }; +- +- pm6150_adc_tm: adc-tm@3500 { +- compatible = "qcom,spmi-adc-tm5"; +- reg = <0x3500>; +- interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; +- #thermal-sensor-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pm6150_gpio: gpios@c000 { +- compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio"; +- reg = <0xc000>; +- gpio-controller; +- gpio-ranges = <&pm6150_gpio 0 0 10>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- pm6150_lsid1: pmic@1 { +- compatible = "qcom,pm6150", "qcom,spmi-pmic"; +- reg = <0x1 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pm6150l.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pm6150l.dtsi +deleted file mode 100644 +index b49860cd1387..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pm6150l.dtsi ++++ /dev/null +@@ -1,55 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-// Copyright (c) 2019, The Linux Foundation. All rights reserved. +- +-#include +-#include +- +-&spmi_bus { +- pm6150l_lsid4: pmic@4 { +- compatible = "qcom,pm6150l", "qcom,spmi-pmic"; +- reg = <0x4 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm6150l_adc: adc@3100 { +- compatible = "qcom,spmi-adc5"; +- reg = <0x3100>; +- interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; +- #address-cells = <1>; +- #size-cells = <0>; +- #io-channel-cells = <1>; +- +- adc-chan@6 { +- reg = ; +- label = "die_temp"; +- }; +- }; +- +- pm6150l_adc_tm: adc-tm@3500 { +- compatible = "qcom,spmi-adc-tm5"; +- reg = <0x3500>; +- interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>; +- #thermal-sensor-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pm6150l_gpio: gpios@c000 { +- compatible = "qcom,pm6150l-gpio", "qcom,spmi-gpio"; +- reg = <0xc000>; +- gpio-controller; +- gpio-ranges = <&pm6150l_gpio 0 0 12>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- pm6150l_lsid5: pmic@5 { +- compatible = "qcom,pm6150l", "qcom,spmi-pmic"; +- reg = <0x5 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pm660.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pm660.dtsi +deleted file mode 100644 +index e847d7209afc..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pm660.dtsi ++++ /dev/null +@@ -1,183 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Konrad Dybcio +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- thermal-zones { +- pm660 { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&pm660_temp>; +- +- trips { +- pm660_alert0: pm660-alert0 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- pm660_crit: pm660-crit { +- temperature = <125000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +- +-&spmi_bus { +- +- pmic@0 { +- compatible = "qcom,pm660", "qcom,spmi-pmic"; +- reg = <0x0 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtc@6000 { +- compatible = "qcom,pm8941-rtc"; +- reg = <0x6000>, <0x6100>; +- reg-names = "rtc", "alarm"; +- interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; +- }; +- +- pon: pon@800 { +- compatible = "qcom,pm8916-pon"; +- +- reg = <0x800>; +- +- pwrkey { +- compatible = "qcom,pm8941-pwrkey"; +- interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; +- debounce = <15625>; +- bias-pull-up; +- linux,code = ; +- }; +- +- }; +- +- pm660_temp: temp-alarm@2400 { +- compatible = "qcom,spmi-temp-alarm"; +- reg = <0x2400>; +- interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; +- io-channels = <&pm660_adc ADC5_DIE_TEMP>; +- io-channel-names = "thermal"; +- #thermal-sensor-cells = <0>; +- }; +- +- pm660_adc: adc@3100 { +- compatible = "qcom,spmi-adc-rev2"; +- reg = <0x3100>; +- interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; +- #address-cells = <1>; +- #size-cells = <0>; +- #io-channel-cells = <1>; +- +- ref_gnd: ref_gnd@0 { +- reg = ; +- qcom,decimation = <1024>; +- qcom,pre-scaling = <1 1>; +- }; +- +- vref_1p25: vref_1p25@1 { +- reg = ; +- qcom,decimation = <1024>; +- qcom,pre-scaling = <1 1>; +- }; +- +- die_temp: die_temp@6 { +- reg = ; +- qcom,decimation = <1024>; +- qcom,pre-scaling = <1 1>; +- }; +- +- xo_therm: xo_therm@4c { +- reg = ; +- qcom,pre-scaling = <1 1>; +- qcom,decimation = <1024>; +- qcom,hw-settle-time = <200>; +- qcom,ratiometric; +- }; +- +- msm_therm: msm_therm@4d { +- reg = ; +- qcom,pre-scaling = <1 1>; +- qcom,decimation = <1024>; +- qcom,hw-settle-time = <200>; +- qcom,ratiometric; +- }; +- +- emmc_therm: emmc_therm@4e { +- reg = ; +- qcom,pre-scaling = <1 1>; +- qcom,decimation = <1024>; +- qcom,hw-settle-time = <200>; +- qcom,ratiometric; +- }; +- +- pa_therm0: thermistor0@4f { +- reg = ; +- qcom,pre-scaling = <1 1>; +- qcom,decimation = <1024>; +- qcom,hw-settle-time = <200>; +- qcom,ratiometric; +- }; +- +- pa_therm1: thermistor1@50 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- qcom,decimation = <1024>; +- qcom,hw-settle-time = <200>; +- qcom,ratiometric; +- }; +- +- quiet_therm: quiet_therm@51 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- qcom,decimation = <1024>; +- qcom,hw-settle-time = <200>; +- qcom,ratiometric; +- }; +- +- vadc_vph_pwr: vph_pwr@83 { +- reg = ; +- qcom,decimation = <1024>; +- qcom,pre-scaling = <1 3>; +- }; +- +- vcoin: vcoin@83 { +- reg = ; +- qcom,decimation = <1024>; +- qcom,pre-scaling = <1 3>; +- }; +- }; +- +- pm660_gpios: gpios@c000 { +- compatible = "qcom,pm660-gpio"; +- reg = <0xc000>; +- gpio-controller; +- gpio-ranges = <&pm660_gpios 0 0 13>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- pmic@1 { +- compatible = "qcom,pm660", "qcom,spmi-pmic"; +- reg = <0x1 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm660_spmi_regulators: pm660-regulators { +- compatible = "qcom,pm660-regulators"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pm660l.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pm660l.dtsi +deleted file mode 100644 +index 05086cbe573b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pm660l.dtsi ++++ /dev/null +@@ -1,90 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Konrad Dybcio +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- thermal-zones { +- pm660l { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&pm660l_temp>; +- +- trips { +- pm660l_alert0: pm660l-alert0 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- pm660l_crit: pm660l-crit { +- temperature = <125000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +- +-&spmi_bus { +- +- pmic@2 { +- compatible = "qcom,pm660l", "qcom,spmi-pmic"; +- reg = <0x2 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm660l_temp: temp-alarm@2400 { +- compatible = "qcom,spmi-temp-alarm"; +- reg = <0x2400>; +- interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; +- #thermal-sensor-cells = <0>; +- }; +- +- pm660l_gpios: gpios@c000 { +- compatible = "qcom,pm660l-gpio", "qcom,spmi-gpio"; +- reg = <0xc000>; +- gpio-controller; +- gpio-ranges = <&pm660l_gpios 0 0 12>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- pmic@3 { +- compatible = "qcom,pm660l", "qcom,spmi-pmic"; +- reg = <0x3 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm660l_wled: leds@d800 { +- compatible = "qcom,pm660l-wled"; +- reg = <0xd800 0xd900>; +- interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "ovp"; +- label = "backlight"; +- +- qcom,switching-freq = <800>; +- qcom,ovp-millivolt = <29600>; +- qcom,current-boost-limit = <970>; +- qcom,current-limit-microamp = <20000>; +- qcom,num-strings = <2>; +- qcom,enabled-strings = <0 1>; +- +- status = "disabled"; +- }; +- +- pm660l_spmi_regulators: pm660l-regulators { +- compatible = "qcom,pm660l-regulators"; +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pm7325.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pm7325.dtsi +deleted file mode 100644 +index e7f64a9ddc9c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pm7325.dtsi ++++ /dev/null +@@ -1,53 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-// Copyright (c) 2021, The Linux Foundation. All rights reserved. +- +-#include +-#include +- +-&spmi_bus { +- pm7325: pmic@1 { +- compatible = "qcom,pm7325", "qcom,spmi-pmic"; +- reg = <0x1 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm7325_temp_alarm: temp-alarm@a00 { +- compatible = "qcom,spmi-temp-alarm"; +- reg = <0xa00>; +- interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; +- #thermal-sensor-cells = <0>; +- }; +- +- pm7325_gpios: gpios@8800 { +- compatible = "qcom,pm7325-gpio", "qcom,spmi-gpio"; +- reg = <0x8800>; +- gpio-controller; +- gpio-ranges = <&pm7325_gpios 0 0 10>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +-}; +- +-&thermal_zones { +- pm7325_thermal: pm7325-thermal { +- polling-delay-passive = <100>; +- polling-delay = <0>; +- thermal-sensors = <&pm7325_temp_alarm>; +- +- trips { +- pm7325_trip0: trip0 { +- temperature = <95000>; +- hysteresis = <0>; +- type = "passive"; +- }; +- +- pm7325_crit: pm7325-crit { +- temperature = <115000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pm8004.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pm8004.dtsi +deleted file mode 100644 +index 532b79acf0e8..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pm8004.dtsi ++++ /dev/null +@@ -1,24 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +- +-&spmi_bus { +- +- pm8004_lsid4: pmic@4 { +- compatible = "qcom,pm8004", "qcom,spmi-pmic"; +- reg = <0x4 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- pm8004_lsid5: pmic@5 { +- compatible = "qcom,pm8004", "qcom,spmi-pmic"; +- reg = <0x5 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm8004_spmi_regulators: regulators { +- compatible = "qcom,pm8004-regulators"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pm8005.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pm8005.dtsi +deleted file mode 100644 +index 3f97607d8baa..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pm8005.dtsi ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* Copyright 2018 Google LLC. */ +- +-#include +-#include +- +-&spmi_bus { +- pm8005_lsid0: pmic@4 { +- compatible = "qcom,pm8005", "qcom,spmi-pmic"; +- reg = <0x4 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm8005_gpio: gpios@c000 { +- compatible = "qcom,pm8005-gpio", "qcom,spmi-gpio"; +- reg = <0xc000>; +- gpio-controller; +- gpio-ranges = <&pm8005_gpio 0 0 4>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- }; +- +- pm8005_lsid1: pmic@5 { +- compatible = "qcom,pm8005", "qcom,spmi-pmic"; +- reg = <0x5 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pm8009.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pm8009.dtsi +deleted file mode 100644 +index b126d7e7e4fb..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pm8009.dtsi ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. +- * Copyright (c) 2020, Linaro Limited +- */ +- +-#include +- +-&spmi_bus { +- pmic@a { +- compatible = "qcom,pm8009", "qcom,spmi-pmic"; +- reg = <0xa SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm8009_pon: pon@800 { +- compatible = "qcom,pm8916-pon"; +- reg = <0x0800>; +- }; +- +- pm8009_gpios: gpio@c000 { +- compatible = "qcom,pm8005-gpio"; +- reg = <0xc000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- pmic@b { +- compatible = "qcom,pm8009", "qcom,spmi-pmic"; +- reg = <0xb SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pm8150.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pm8150.dtsi +deleted file mode 100644 +index 0df76f7b1cc1..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pm8150.dtsi ++++ /dev/null +@@ -1,145 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. +- * Copyright (c) 2019, Linaro Limited +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- thermal-zones { +- pm8150-thermal { +- polling-delay-passive = <100>; +- polling-delay = <0>; +- +- thermal-sensors = <&pm8150_temp>; +- +- trips { +- trip0 { +- temperature = <95000>; +- hysteresis = <0>; +- type = "passive"; +- }; +- +- trip1 { +- temperature = <115000>; +- hysteresis = <0>; +- type = "hot"; +- }; +- +- trip2 { +- temperature = <145000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +- +-&spmi_bus { +- pm8150_0: pmic@0 { +- compatible = "qcom,pm8150", "qcom,spmi-pmic"; +- reg = <0x0 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pon: power-on@800 { +- compatible = "qcom,pm8998-pon"; +- reg = <0x0800>; +- mode-bootloader = <0x2>; +- mode-recovery = <0x1>; +- +- pon_pwrkey: pwrkey { +- compatible = "qcom,pm8941-pwrkey"; +- interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>; +- debounce = <15625>; +- bias-pull-up; +- linux,code = ; +- +- status = "disabled"; +- }; +- +- pon_resin: resin { +- compatible = "qcom,pm8941-resin"; +- interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; +- debounce = <15625>; +- bias-pull-up; +- +- status = "disabled"; +- }; +- }; +- +- pm8150_temp: temp-alarm@2400 { +- compatible = "qcom,spmi-temp-alarm"; +- reg = <0x2400>; +- interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; +- io-channels = <&pm8150_adc ADC5_DIE_TEMP>; +- io-channel-names = "thermal"; +- #thermal-sensor-cells = <0>; +- }; +- +- pm8150_adc: adc@3100 { +- compatible = "qcom,spmi-adc5"; +- reg = <0x3100>; +- #address-cells = <1>; +- #size-cells = <0>; +- #io-channel-cells = <1>; +- interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; +- +- ref-gnd@0 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "ref_gnd"; +- }; +- +- vref-1p25@1 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "vref_1p25"; +- }; +- +- die-temp@6 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "die_temp"; +- }; +- }; +- +- pm8150_adc_tm: adc-tm@3500 { +- compatible = "qcom,spmi-adc-tm5"; +- reg = <0x3500>; +- interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; +- #thermal-sensor-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- rtc@6000 { +- compatible = "qcom,pm8941-rtc"; +- reg = <0x6000>; +- reg-names = "rtc", "alarm"; +- interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; +- }; +- +- pm8150_gpios: gpio@c000 { +- compatible = "qcom,pm8150-gpio"; +- reg = <0xc000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- pmic@1 { +- compatible = "qcom,pm8150", "qcom,spmi-pmic"; +- reg = <0x1 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pm8150b.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pm8150b.dtsi +deleted file mode 100644 +index 058cc5107c75..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pm8150b.dtsi ++++ /dev/null +@@ -1,130 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. +- * Copyright (c) 2019, Linaro Limited +- */ +- +-#include +-#include +-#include +- +-/ { +- thermal-zones { +- pm8150b-thermal { +- polling-delay-passive = <100>; +- polling-delay = <0>; +- +- thermal-sensors = <&pm8150b_temp>; +- +- trips { +- trip0 { +- temperature = <95000>; +- hysteresis = <0>; +- type = "passive"; +- }; +- +- trip1 { +- temperature = <115000>; +- hysteresis = <0>; +- type = "hot"; +- }; +- +- trip2 { +- temperature = <145000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +- +-&spmi_bus { +- pmic@2 { +- compatible = "qcom,pm8150b", "qcom,spmi-pmic"; +- reg = <0x2 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- power-on@800 { +- compatible = "qcom,pm8916-pon"; +- reg = <0x0800>; +- +- status = "disabled"; +- }; +- +- pm8150b_vbus: dcdc@1100 { +- compatible = "qcom,pm8150b-vbus-reg"; +- status = "disabled"; +- reg = <0x1100>; +- }; +- +- pm8150b_temp: temp-alarm@2400 { +- compatible = "qcom,spmi-temp-alarm"; +- reg = <0x2400>; +- interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; +- io-channels = <&pm8150b_adc ADC5_DIE_TEMP>; +- io-channel-names = "thermal"; +- #thermal-sensor-cells = <0>; +- }; +- +- pm8150b_adc: adc@3100 { +- compatible = "qcom,spmi-adc5"; +- reg = <0x3100>; +- #address-cells = <1>; +- #size-cells = <0>; +- #io-channel-cells = <1>; +- interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; +- +- ref-gnd@0 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "ref_gnd"; +- }; +- +- vref-1p25@1 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "vref_1p25"; +- }; +- +- die-temp@6 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "die_temp"; +- }; +- +- chg-temp@9 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "chg_temp"; +- }; +- }; +- +- pm8150b_adc_tm: adc-tm@3500 { +- compatible = "qcom,spmi-adc-tm5"; +- reg = <0x3500>; +- interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; +- #thermal-sensor-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pm8150b_gpios: gpio@c000 { +- compatible = "qcom,pm8150b-gpio"; +- reg = <0xc000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- pmic@3 { +- compatible = "qcom,pm8150b", "qcom,spmi-pmic"; +- reg = <0x3 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pm8150l.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pm8150l.dtsi +deleted file mode 100644 +index 52f094a2b713..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pm8150l.dtsi ++++ /dev/null +@@ -1,118 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. +- * Copyright (c) 2019, Linaro Limited +- */ +- +-#include +-#include +-#include +- +-/ { +- thermal-zones { +- pm8150l-thermal { +- polling-delay-passive = <100>; +- polling-delay = <0>; +- +- thermal-sensors = <&pm8150l_temp>; +- +- trips { +- trip0 { +- temperature = <95000>; +- hysteresis = <0>; +- type = "passive"; +- }; +- +- trip1 { +- temperature = <115000>; +- hysteresis = <0>; +- type = "hot"; +- }; +- +- trip2 { +- temperature = <145000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +- +-&spmi_bus { +- pmic@4 { +- compatible = "qcom,pm8150l", "qcom,spmi-pmic"; +- reg = <0x4 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- power-on@800 { +- compatible = "qcom,pm8916-pon"; +- reg = <0x0800>; +- +- status = "disabled"; +- }; +- +- pm8150l_temp: temp-alarm@2400 { +- compatible = "qcom,spmi-temp-alarm"; +- reg = <0x2400>; +- interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; +- io-channels = <&pm8150l_adc ADC5_DIE_TEMP>; +- io-channel-names = "thermal"; +- #thermal-sensor-cells = <0>; +- }; +- +- pm8150l_adc: adc@3100 { +- compatible = "qcom,spmi-adc5"; +- reg = <0x3100>; +- #address-cells = <1>; +- #size-cells = <0>; +- #io-channel-cells = <1>; +- interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; +- +- ref-gnd@0 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "ref_gnd"; +- }; +- +- vref-1p25@1 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "vref_1p25"; +- }; +- +- die-temp@6 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "die_temp"; +- }; +- }; +- +- pm8150l_adc_tm: adc-tm@3500 { +- compatible = "qcom,spmi-adc-tm5"; +- reg = <0x3500>; +- interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>; +- #thermal-sensor-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pm8150l_gpios: gpio@c000 { +- compatible = "qcom,pm8150l-gpio"; +- reg = <0xc000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- pmic@5 { +- compatible = "qcom,pm8150l", "qcom,spmi-pmic"; +- reg = <0x5 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pm8350.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pm8350.dtsi +deleted file mode 100644 +index 308f9ca7c744..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pm8350.dtsi ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Linaro Limited +- */ +- +-#include +-#include +- +-&spmi_bus { +- pm8350: pmic@1 { +- compatible = "qcom,pm8350", "qcom,spmi-pmic"; +- reg = <0x1 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm8350_gpios: gpio@8800 { +- compatible = "qcom,pm8350-gpio"; +- reg = <0x8800>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pm8350b.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pm8350b.dtsi +deleted file mode 100644 +index b23bb1d49a4d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pm8350b.dtsi ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Linaro Limited +- */ +- +-#include +-#include +- +-&spmi_bus { +- pm8350b: pmic@3 { +- compatible = "qcom,pm8350b", "qcom,spmi-pmic"; +- reg = <0x3 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm8350b_gpios: gpio@8800 { +- compatible = "qcom,pm8350b-gpio"; +- reg = <0x8800>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pm8350c.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pm8350c.dtsi +deleted file mode 100644 +index e1b75ae0a823..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pm8350c.dtsi ++++ /dev/null +@@ -1,55 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Linaro Limited +- */ +- +-#include +-#include +- +-&spmi_bus { +- pm8350c: pmic@2 { +- compatible = "qcom,pm8350c", "qcom,spmi-pmic"; +- reg = <0x2 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm8350c_temp_alarm: temp-alarm@a00 { +- compatible = "qcom,spmi-temp-alarm"; +- reg = <0xa00>; +- interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; +- #thermal-sensor-cells = <0>; +- }; +- +- pm8350c_gpios: gpio@8800 { +- compatible = "qcom,pm8350c-gpio", "qcom,spmi-gpio"; +- reg = <0x8800>; +- gpio-controller; +- gpio-ranges = <&pm8350c_gpios 0 0 9>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +-}; +- +-&thermal_zones { +- pm8350c_thermal: pm8350c-thermal { +- polling-delay-passive = <100>; +- polling-delay = <0>; +- thermal-sensors = <&pm8350c_temp_alarm>; +- +- trips { +- pm8350c_trip0: trip0 { +- temperature = <95000>; +- hysteresis = <0>; +- type = "passive"; +- }; +- +- pm8350c_crit: pm8350c-crit { +- temperature = <115000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pm8916.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pm8916.dtsi +deleted file mode 100644 +index 42180f1b5dbb..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pm8916.dtsi ++++ /dev/null +@@ -1,168 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +-#include +-#include +- +-&spmi_bus { +- +- pm8916_0: pmic@0 { +- compatible = "qcom,pm8916", "qcom,spmi-pmic"; +- reg = <0x0 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pon@800 { +- compatible = "qcom,pm8916-pon"; +- reg = <0x800>; +- mode-bootloader = <0x2>; +- mode-recovery = <0x1>; +- +- pwrkey { +- compatible = "qcom,pm8941-pwrkey"; +- interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; +- debounce = <15625>; +- bias-pull-up; +- linux,code = ; +- }; +- +- pm8916_resin: resin { +- compatible = "qcom,pm8941-resin"; +- interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; +- debounce = <15625>; +- bias-pull-up; +- status = "disabled"; +- }; +- +- watchdog { +- compatible = "qcom,pm8916-wdt"; +- interrupts = <0x0 0x8 6 IRQ_TYPE_EDGE_RISING>; +- timeout-sec = <60>; +- }; +- }; +- +- pm8916_temp: temp-alarm@2400 { +- compatible = "qcom,spmi-temp-alarm"; +- reg = <0x2400>; +- interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; +- io-channels = <&pm8916_vadc VADC_DIE_TEMP>; +- io-channel-names = "thermal"; +- #thermal-sensor-cells = <0>; +- }; +- +- pm8916_vadc: adc@3100 { +- compatible = "qcom,spmi-vadc"; +- reg = <0x3100>; +- interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; +- #address-cells = <1>; +- #size-cells = <0>; +- #io-channel-cells = <1>; +- +- adc-chan@0 { +- reg = ; +- qcom,pre-scaling = <1 10>; +- }; +- adc-chan@7 { +- reg = ; +- qcom,pre-scaling = <1 3>; +- }; +- adc-chan@8 { +- reg = ; +- }; +- adc-chan@9 { +- reg = ; +- }; +- adc-chan@a { +- reg = ; +- }; +- adc-chan@e { +- reg = ; +- }; +- adc-chan@f { +- reg = ; +- }; +- }; +- +- rtc@6000 { +- compatible = "qcom,pm8941-rtc"; +- reg = <0x6000>; +- interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; +- }; +- +- pm8916_mpps: mpps@a000 { +- compatible = "qcom,pm8916-mpp"; +- reg = <0xa000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, +- <0 0xa1 0 IRQ_TYPE_NONE>, +- <0 0xa2 0 IRQ_TYPE_NONE>, +- <0 0xa3 0 IRQ_TYPE_NONE>; +- }; +- +- pm8916_gpios: gpios@c000 { +- compatible = "qcom,pm8916-gpio"; +- reg = <0xc000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, +- <0 0xc1 0 IRQ_TYPE_NONE>, +- <0 0xc2 0 IRQ_TYPE_NONE>, +- <0 0xc3 0 IRQ_TYPE_NONE>; +- }; +- }; +- +- pm8916_1: pmic@1 { +- compatible = "qcom,pm8916", "qcom,spmi-pmic"; +- reg = <0x1 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm8916_vib: vibrator@c000 { +- compatible = "qcom,pm8916-vib"; +- reg = <0xc000>; +- status = "disabled"; +- }; +- +- wcd_codec: audio-codec@f000 { +- compatible = "qcom,pm8916-wcd-analog-codec"; +- reg = <0xf000>; +- reg-names = "pmic-codec-core"; +- clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; +- clock-names = "mclk"; +- interrupt-parent = <&spmi_bus>; +- interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>, +- <0x1 0xf0 0x1 IRQ_TYPE_NONE>, +- <0x1 0xf0 0x2 IRQ_TYPE_NONE>, +- <0x1 0xf0 0x3 IRQ_TYPE_NONE>, +- <0x1 0xf0 0x4 IRQ_TYPE_NONE>, +- <0x1 0xf0 0x5 IRQ_TYPE_NONE>, +- <0x1 0xf0 0x6 IRQ_TYPE_NONE>, +- <0x1 0xf0 0x7 IRQ_TYPE_NONE>, +- <0x1 0xf1 0x0 IRQ_TYPE_NONE>, +- <0x1 0xf1 0x1 IRQ_TYPE_NONE>, +- <0x1 0xf1 0x2 IRQ_TYPE_NONE>, +- <0x1 0xf1 0x3 IRQ_TYPE_NONE>, +- <0x1 0xf1 0x4 IRQ_TYPE_NONE>, +- <0x1 0xf1 0x5 IRQ_TYPE_NONE>; +- interrupt-names = "cdc_spk_cnp_int", +- "cdc_spk_clip_int", +- "cdc_spk_ocp_int", +- "mbhc_ins_rem_det1", +- "mbhc_but_rel_det", +- "mbhc_but_press_det", +- "mbhc_ins_rem_det", +- "mbhc_switch_int", +- "cdc_ear_ocp_int", +- "cdc_hphr_ocp_int", +- "cdc_hphl_ocp_det", +- "cdc_ear_cnp_int", +- "cdc_hphr_cnp_int", +- "cdc_hphl_cnp_int"; +- vdd-cdc-io-supply = <&pm8916_l5>; +- vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>; +- vdd-micbias-supply = <&pm8916_l13>; +- #sound-dai-cells = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pm8994.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pm8994.dtsi +deleted file mode 100644 +index ad19016df047..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pm8994.dtsi ++++ /dev/null +@@ -1,147 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +-#include +-#include +- +-/ { +- thermal-zones { +- pm8994-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&pm8994_temp>; +- +- trips { +- pm8994_alert0: pm8994-alert0 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- pm8994_crit: pm8994-crit { +- temperature = <125000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +- +-&spmi_bus { +- +- pmic@0 { +- compatible = "qcom,pm8994", "qcom,spmi-pmic"; +- reg = <0x0 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtc@6000 { +- compatible = "qcom,pm8941-rtc"; +- reg = <0x6000>, <0x6100>; +- reg-names = "rtc", "alarm"; +- interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; +- }; +- +- pm8994_pon: pon@800 { +- compatible = "qcom,pm8916-pon"; +- reg = <0x800>; +- mode-bootloader = <0x2>; +- mode-recovery = <0x1>; +- +- pwrkey { +- compatible = "qcom,pm8941-pwrkey"; +- interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; +- debounce = <15625>; +- bias-pull-up; +- linux,code = ; +- }; +- +- pm8994_resin: resin { +- compatible = "qcom,pm8941-resin"; +- interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; +- debounce = <15625>; +- bias-pull-up; +- status = "disabled"; +- }; +- }; +- +- pm8994_temp: temp-alarm@2400 { +- compatible = "qcom,spmi-temp-alarm"; +- reg = <0x2400>; +- interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; +- io-channels = <&pm8994_vadc VADC_DIE_TEMP>; +- io-channel-names = "thermal"; +- #thermal-sensor-cells = <0>; +- }; +- +- pm8994_vadc: adc@3100 { +- compatible = "qcom,spmi-vadc"; +- reg = <0x3100>; +- interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; +- #address-cells = <1>; +- #size-cells = <0>; +- #io-channel-cells = <1>; +- +- adc-chan@7 { +- reg = ; +- qcom,pre-scaling = <1 3>; +- label = "vph_pwr"; +- }; +- adc-chan@8 { +- reg = ; +- label = "die_temp"; +- }; +- adc-chan@9 { +- reg = ; +- label = "ref_625mv"; +- }; +- adc-chan@a { +- reg = ; +- label = "ref_1250mv"; +- }; +- adc-chan@e { +- reg = ; +- }; +- adc-chan@f { +- reg = ; +- }; +- }; +- +- pm8994_gpios: gpios@c000 { +- compatible = "qcom,pm8994-gpio", "qcom,spmi-gpio"; +- reg = <0xc000>; +- gpio-controller; +- gpio-ranges = <&pm8994_gpios 0 0 22>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pm8994_mpps: mpps@a000 { +- compatible = "qcom,pm8994-mpp"; +- reg = <0xa000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, +- <0 0xa1 0 IRQ_TYPE_NONE>, +- <0 0xa2 0 IRQ_TYPE_NONE>, +- <0 0xa3 0 IRQ_TYPE_NONE>, +- <0 0xa4 0 IRQ_TYPE_NONE>, +- <0 0xa5 0 IRQ_TYPE_NONE>, +- <0 0xa6 0 IRQ_TYPE_NONE>, +- <0 0xa7 0 IRQ_TYPE_NONE>; +- }; +- }; +- +- pmic@1 { +- compatible = "qcom,pm8994", "qcom,spmi-pmic"; +- reg = <0x1 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm8994_spmi_regulators: regulators { +- compatible = "qcom,pm8994-regulators"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pm8998.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pm8998.dtsi +deleted file mode 100644 +index 6f5bb6b37ec2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pm8998.dtsi ++++ /dev/null +@@ -1,112 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* Copyright 2018 Google LLC. */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- thermal-zones { +- pm8998-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&pm8998_temp>; +- +- trips { +- pm8998_alert0: pm8998-alert0 { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- pm8998_crit: pm8998-crit { +- temperature = <125000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +- +-&spmi_bus { +- pm8998_lsid0: pmic@0 { +- compatible = "qcom,pm8998", "qcom,spmi-pmic"; +- reg = <0x0 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pm8998_pon: pon@800 { +- compatible = "qcom,pm8998-pon"; +- +- reg = <0x800>; +- mode-bootloader = <0x2>; +- mode-recovery = <0x1>; +- +- pm8998_pwrkey: pwrkey { +- compatible = "qcom,pm8941-pwrkey"; +- interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; +- debounce = <15625>; +- bias-pull-up; +- linux,code = ; +- }; +- }; +- +- pm8998_temp: temp-alarm@2400 { +- compatible = "qcom,spmi-temp-alarm"; +- reg = <0x2400>; +- interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; +- io-channels = <&pm8998_adc ADC5_DIE_TEMP>; +- io-channel-names = "thermal"; +- #thermal-sensor-cells = <0>; +- }; +- +- pm8998_coincell: coincell@2800 { +- compatible = "qcom,pm8941-coincell"; +- reg = <0x2800>; +- +- status = "disabled"; +- }; +- +- pm8998_adc: adc@3100 { +- compatible = "qcom,spmi-adc-rev2"; +- reg = <0x3100>; +- interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; +- #address-cells = <1>; +- #size-cells = <0>; +- #io-channel-cells = <1>; +- +- adc-chan@6 { +- reg = ; +- label = "die_temp"; +- }; +- }; +- +- rtc@6000 { +- compatible = "qcom,pm8941-rtc"; +- reg = <0x6000>, <0x6100>; +- reg-names = "rtc", "alarm"; +- interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; +- }; +- +- pm8998_gpio: gpios@c000 { +- compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio"; +- reg = <0xc000>; +- gpio-controller; +- gpio-ranges = <&pm8998_gpio 0 0 26>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- }; +- +- pm8998_lsid1: pmic@1 { +- compatible = "qcom,pm8998", "qcom,spmi-pmic"; +- reg = <0x1 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pmi8994.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pmi8994.dtsi +deleted file mode 100644 +index a06ea9adae81..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pmi8994.dtsi ++++ /dev/null +@@ -1,49 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +- +-&spmi_bus { +- +- pmic@2 { +- compatible = "qcom,pmi8994", "qcom,spmi-pmic"; +- reg = <0x2 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pmi8994_gpios: gpios@c000 { +- compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio"; +- reg = <0xc000>; +- gpio-controller; +- gpio-ranges = <&pmi8994_gpios 0 0 10>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- pmic@3 { +- compatible = "qcom,pmi8994", "qcom,spmi-pmic"; +- reg = <0x3 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pmi8994_spmi_regulators: regulators { +- compatible = "qcom,pmi8994-regulators"; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- pmi8994_wled: wled@d800 { +- compatible = "qcom,pmi8994-wled"; +- reg = <0xd800 0xd900>; +- interrupts = <3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "short"; +- qcom,num-strings = <3>; +- /* Yes, all four strings *have to* be defined or things won't work. */ +- qcom,enabled-strings = <0 1 2 3>; +- qcom,cabc; +- qcom,external-pfet; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pmi8996.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pmi8996.dtsi +deleted file mode 100644 +index 31b47209e261..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pmi8996.dtsi ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2021, Konrad Dybcio +- */ +- +- /* +- * PMI8996 is a slight modification of PMI8994 with +- * some notable changes, like being the first PMIC +- * whose the bootloader has to check to continue booting +- * and a change to a LABIBB parameter. +- */ +- +-/ { +- qcom,pmic-id = <0x20009 0x10013 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pmi8998.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pmi8998.dtsi +deleted file mode 100644 +index d230c510d4b7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pmi8998.dtsi ++++ /dev/null +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +- +-&spmi_bus { +- pmi8998_lsid0: pmic@2 { +- compatible = "qcom,pmi8998", "qcom,spmi-pmic"; +- reg = <0x2 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pmi8998_gpio: gpios@c000 { +- compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio"; +- reg = <0xc000>; +- gpio-controller; +- gpio-ranges = <&pmi8998_gpio 0 0 14>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- pmi8998_lsid1: pmic@3 { +- compatible = "qcom,pmi8998", "qcom,spmi-pmic"; +- reg = <0x3 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- labibb { +- compatible = "qcom,pmi8998-lab-ibb"; +- +- ibb: ibb { +- interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>, +- <0x3 0xdc 0x0 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "sc-err", "ocp"; +- }; +- +- lab: lab { +- interrupts = <0x3 0xde 0x1 IRQ_TYPE_EDGE_RISING>, +- <0x3 0xde 0x0 IRQ_TYPE_LEVEL_LOW>; +- interrupt-names = "sc-err", "ocp"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pmk8350.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pmk8350.dtsi +deleted file mode 100644 +index 04fc2632a0b2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pmk8350.dtsi ++++ /dev/null +@@ -1,74 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Linaro Limited +- */ +- +-#include +-#include +-#include +-#include +- +-&spmi_bus { +- pmk8350: pmic@0 { +- compatible = "qcom,pmk8350", "qcom,spmi-pmic"; +- reg = <0x0 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pmk8350_pon: pon@1300 { +- compatible = "qcom,pm8998-pon"; +- reg = <0x1300>; +- +- pwrkey { +- compatible = "qcom,pmk8350-pwrkey"; +- interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; +- linux,code = ; +- }; +- +- resin { +- compatible = "qcom,pmk8350-resin"; +- interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; +- linux,code = ; +- }; +- }; +- +- pmk8350_vadc: adc@3100 { +- compatible = "qcom,spmi-adc7"; +- reg = <0x3100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "eoc-int-en-set"; +- #io-channel-cells = <1>; +- io-channel-ranges; +- }; +- +- pmk8350_adc_tm: adc-tm@3400 { +- compatible = "qcom,adc-tm7"; +- reg = <0x3400>; +- interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "threshold"; +- #address-cells = <1>; +- #size-cells = <0>; +- #thermal-sensor-cells = <1>; +- status = "disabled"; +- }; +- +- pmk8350_rtc: rtc@6100 { +- compatible = "qcom,pmk8350-rtc"; +- reg = <0x6100>, <0x6200>; +- reg-names = "rtc", "alarm"; +- interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; +- }; +- +- pmk8350_gpios: gpio@b000 { +- compatible = "qcom,pmk8350-gpio", "qcom,spmi-gpio"; +- reg = <0xb000>; +- gpio-controller; +- gpio-ranges = <&pmk8350_gpios 0 0 4>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pmm8155au_1.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pmm8155au_1.dtsi +deleted file mode 100644 +index 7072e5a2e73f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pmm8155au_1.dtsi ++++ /dev/null +@@ -1,135 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Linaro Limited +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- thermal-zones { +- pmm8155au-1-thermal { +- polling-delay-passive = <100>; +- polling-delay = <0>; +- +- thermal-sensors = <&pmm8155au_1_temp>; +- +- trips { +- trip0 { +- temperature = <95000>; +- hysteresis = <0>; +- type = "passive"; +- }; +- +- trip1 { +- temperature = <115000>; +- hysteresis = <0>; +- type = "hot"; +- }; +- +- trip2 { +- temperature = <145000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +- +-&spmi_bus { +- pmic@0 { +- compatible = "qcom,pmm8155au", "qcom,spmi-pmic"; +- reg = <0x0 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pon: power-on@800 { +- compatible = "qcom,pm8916-pon"; +- reg = <0x0800>; +- pwrkey { +- compatible = "qcom,pm8941-pwrkey"; +- interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>; +- debounce = <15625>; +- bias-pull-up; +- linux,code = ; +- +- status = "disabled"; +- }; +- }; +- +- pmm8155au_1_temp: temp-alarm@2400 { +- compatible = "qcom,spmi-temp-alarm"; +- reg = <0x2400>; +- interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; +- io-channels = <&pmm8155au_1_adc ADC5_DIE_TEMP>; +- io-channel-names = "thermal"; +- #thermal-sensor-cells = <0>; +- }; +- +- pmm8155au_1_adc: adc@3100 { +- compatible = "qcom,spmi-adc5"; +- reg = <0x3100>; +- #address-cells = <1>; +- #size-cells = <0>; +- #io-channel-cells = <1>; +- interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; +- +- ref-gnd@0 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "ref_gnd"; +- }; +- +- vref-1p25@1 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "vref_1p25"; +- }; +- +- die-temp@6 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "die_temp"; +- }; +- }; +- +- pmm8155au_1_adc_tm: adc-tm@3500 { +- compatible = "qcom,spmi-adc-tm5"; +- reg = <0x3500>; +- interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; +- #thermal-sensor-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pmm8155au_1_rtc: rtc@6000 { +- compatible = "qcom,pm8941-rtc"; +- reg = <0x6000>; +- reg-names = "rtc", "alarm"; +- interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; +- +- status = "disabled"; +- }; +- +- pmm8155au_1_gpios: gpio@c000 { +- compatible = "qcom,pmm8155au-gpio"; +- reg = <0xc000>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmm8155au_1_gpios 0 0 10>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- pmic@1 { +- compatible = "qcom,pmm8155au", "qcom,spmi-pmic"; +- reg = <0x1 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pmm8155au_2.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pmm8155au_2.dtsi +deleted file mode 100644 +index 72075964fbb9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pmm8155au_2.dtsi ++++ /dev/null +@@ -1,108 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Linaro Limited +- */ +- +-#include +-#include +-#include +- +-/ { +- thermal-zones { +- pmm8155au-2-thermal { +- polling-delay-passive = <100>; +- polling-delay = <0>; +- +- thermal-sensors = <&pmm8155au_2_temp>; +- +- trips { +- trip0 { +- temperature = <95000>; +- hysteresis = <0>; +- type = "passive"; +- }; +- +- trip1 { +- temperature = <115000>; +- hysteresis = <0>; +- type = "hot"; +- }; +- +- trip2 { +- temperature = <145000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +- +-&spmi_bus { +- pmic@4 { +- compatible = "qcom,pmm8155au", "qcom,spmi-pmic"; +- reg = <0x4 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- power-on@800 { +- compatible = "qcom,pm8916-pon"; +- reg = <0x0800>; +- +- status = "disabled"; +- }; +- +- pmm8155au_2_temp: temp-alarm@2400 { +- compatible = "qcom,spmi-temp-alarm"; +- reg = <0x2400>; +- interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; +- io-channels = <&pmm8155au_2_adc ADC5_DIE_TEMP>; +- io-channel-names = "thermal"; +- #thermal-sensor-cells = <0>; +- }; +- +- pmm8155au_2_adc: adc@3100 { +- compatible = "qcom,spmi-adc5"; +- reg = <0x3100>; +- #address-cells = <1>; +- #size-cells = <0>; +- #io-channel-cells = <1>; +- interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; +- +- ref-gnd@0 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "ref_gnd"; +- }; +- +- vref-1p25@1 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "vref_1p25"; +- }; +- +- die-temp@6 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- label = "die_temp"; +- }; +- }; +- +- pmm8155au_2_gpios: gpio@c000 { +- compatible = "qcom,pmm8155au-gpio"; +- reg = <0xc000>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pmm8155au_2_gpios 0 0 10>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- pmic@5 { +- compatible = "qcom,pmm8155au", "qcom,spmi-pmic"; +- reg = <0x5 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pmr735a.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pmr735a.dtsi +deleted file mode 100644 +index b4b6ba24f845..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pmr735a.dtsi ++++ /dev/null +@@ -1,55 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Linaro Limited +- */ +- +-#include +-#include +- +-&spmi_bus { +- pmr735a: pmic@4 { +- compatible = "qcom,pmr735a", "qcom,spmi-pmic"; +- reg = <0x4 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pmr735a_temp_alarm: temp-alarm@a00 { +- compatible = "qcom,spmi-temp-alarm"; +- reg = <0xa00>; +- interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; +- #thermal-sensor-cells = <0>; +- }; +- +- pmr735a_gpios: gpio@8800 { +- compatible = "qcom,pmr735a-gpio", "qcom,spmi-gpio"; +- reg = <0x8800>; +- gpio-controller; +- gpio-ranges = <&pmr735a_gpios 0 0 4>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +-}; +- +-&thermal_zones { +- pmr735a_thermal: pmr735a-thermal { +- polling-delay-passive = <100>; +- polling-delay = <0>; +- thermal-sensors = <&pmr735a_temp_alarm>; +- +- trips { +- pmr735a_trip0: trip0 { +- temperature = <95000>; +- hysteresis = <0>; +- type = "passive"; +- }; +- +- pmr735a_crit: pmr735a-crit { +- temperature = <115000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pmr735b.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pmr735b.dtsi +deleted file mode 100644 +index 1144086280f5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pmr735b.dtsi ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Linaro Limited +- */ +- +-#include +-#include +- +-&spmi_bus { +- pmr735b: pmic@5 { +- compatible = "qcom,pmr735b", "qcom,spmi-pmic"; +- reg = <0x5 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pmr735b_gpios: gpio@8800 { +- compatible = "qcom,pmr735b-gpio"; +- reg = <0x8800>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/pms405.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/pms405.dtsi +deleted file mode 100644 +index 172be177fc8f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/pms405.dtsi ++++ /dev/null +@@ -1,149 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2018, Linaro Limited +- +-#include +-#include +-#include +-#include +- +-/ { +- thermal-zones { +- pms405-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&pms405_temp>; +- +- trips { +- pms405_alert0: pms405-alert0 { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- pms405_crit: pms405-crit { +- temperature = <125000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +- +-&spmi_bus { +- pms405_0: pms405@0 { +- compatible = "qcom,spmi-pmic"; +- reg = <0x0 SPMI_USID>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pms405_gpios: gpio@c000 { +- compatible = "qcom,pms405-gpio"; +- reg = <0xc000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, +- <0 0xc1 0 IRQ_TYPE_NONE>, +- <0 0xc2 0 IRQ_TYPE_NONE>, +- <0 0xc3 0 IRQ_TYPE_NONE>, +- <0 0xc4 0 IRQ_TYPE_NONE>, +- <0 0xc5 0 IRQ_TYPE_NONE>, +- <0 0xc6 0 IRQ_TYPE_NONE>, +- <0 0xc7 0 IRQ_TYPE_NONE>, +- <0 0xc8 0 IRQ_TYPE_NONE>, +- <0 0xc9 0 IRQ_TYPE_NONE>, +- <0 0xca 0 IRQ_TYPE_NONE>, +- <0 0xcb 0 IRQ_TYPE_NONE>; +- }; +- +- pon@800 { +- compatible = "qcom,pms405-pon"; +- reg = <0x0800>; +- mode-bootloader = <0x2>; +- mode-recovery = <0x1>; +- +- pwrkey { +- compatible = "qcom,pm8941-pwrkey"; +- interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; +- debounce = <15625>; +- bias-pull-up; +- linux,code = ; +- }; +- }; +- +- pms405_temp: temp-alarm@2400 { +- compatible = "qcom,spmi-temp-alarm"; +- reg = <0x2400>; +- interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; +- io-channels = <&pms405_adc ADC5_DIE_TEMP>; +- io-channel-names = "thermal"; +- #thermal-sensor-cells = <0>; +- }; +- +- pms405_adc: adc@3100 { +- compatible = "qcom,pms405-adc", "qcom,spmi-adc-rev2"; +- reg = <0x3100>; +- interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; +- #address-cells = <1>; +- #size-cells = <0>; +- #io-channel-cells = <1>; +- +- ref_gnd@0 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- }; +- +- vref_1p25@1 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- }; +- +- pon_1: vph_pwr@131 { +- reg = ; +- qcom,pre-scaling = <1 3>; +- }; +- +- die_temp@6 { +- reg = ; +- qcom,pre-scaling = <1 1>; +- }; +- +- pa_therm1: thermistor1@77 { +- reg = ; +- qcom,ratiometric; +- qcom,hw-settle-time = <200>; +- qcom,pre-scaling = <1 1>; +- }; +- +- pa_therm3: thermistor3@79 { +- reg = ; +- qcom,ratiometric; +- qcom,hw-settle-time = <200>; +- qcom,pre-scaling = <1 1>; +- }; +- +- xo_therm: xo_temp@76 { +- reg = ; +- qcom,ratiometric; +- qcom,hw-settle-time = <200>; +- qcom,pre-scaling = <1 1>; +- }; +- }; +- +- rtc@6000 { +- compatible = "qcom,pm8941-rtc"; +- reg = <0x6000>; +- reg-names = "rtc", "alarm"; +- interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; +- }; +- }; +- +- pms405_1: pms405@1 { +- compatible = "qcom,spmi-pmic"; +- reg = <0x1 SPMI_USID>; +- +- pms405_spmi_regulators: regulators { +- compatible = "qcom,pms405-regulators"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/qcs404-evb-1000.dts b/scripts/dtc/include-prefixes/arm64/qcom/qcs404-evb-1000.dts +deleted file mode 100644 +index 937eb4555ffe..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/qcs404-evb-1000.dts ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2018, Linaro Limited +- +-/dts-v1/; +- +-#include "qcs404-evb.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. QCS404 EVB 1000"; +- compatible = "qcom,qcs404-evb-1000", "qcom,qcs404-evb", +- "qcom,qcs404"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/qcs404-evb-4000.dts b/scripts/dtc/include-prefixes/arm64/qcom/qcs404-evb-4000.dts +deleted file mode 100644 +index 08d5d51221cf..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/qcs404-evb-4000.dts ++++ /dev/null +@@ -1,94 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2018, Linaro Limited +- +-/dts-v1/; +- +-#include +-#include "qcs404-evb.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. QCS404 EVB 4000"; +- compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb", +- "qcom,qcs404"; +-}; +- +-ðernet { +- status = "okay"; +- +- snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 10000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <ðernet_defaults>; +- +- phy-handle = <&phy1>; +- phy-mode = "rgmii"; +- mdio { +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- compatible = "snps,dwmac-mdio"; +- phy1: phy@4 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- device_type = "ethernet-phy"; +- reg = <0x4>; +- }; +- }; +-}; +- +-&tlmm { +- ethernet_defaults: ethernet-defaults { +- int { +- pins = "gpio61"; +- function = "rgmii_int"; +- bias-disable; +- drive-strength = <2>; +- }; +- mdc { +- pins = "gpio76"; +- function = "rgmii_mdc"; +- bias-pull-up; +- }; +- mdio { +- pins = "gpio75"; +- function = "rgmii_mdio"; +- bias-pull-up; +- }; +- tx { +- pins = "gpio67", "gpio66", "gpio65", "gpio64"; +- function = "rgmii_tx"; +- bias-pull-up; +- drive-strength = <16>; +- }; +- rx { +- pins = "gpio73", "gpio72", "gpio71", "gpio70"; +- function = "rgmii_rx"; +- bias-disable; +- drive-strength = <2>; +- }; +- tx-ctl { +- pins = "gpio68"; +- function = "rgmii_ctl"; +- bias-pull-up; +- drive-strength = <16>; +- }; +- rx-ctl { +- pins = "gpio74"; +- function = "rgmii_ctl"; +- bias-disable; +- drive-strength = <2>; +- }; +- tx-ck { +- pins = "gpio63"; +- function = "rgmii_ck"; +- bias-pull-up; +- drive-strength = <16>; +- }; +- rx-ck { +- pins = "gpio69"; +- function = "rgmii_ck"; +- bias-disable; +- drive-strength = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/qcs404-evb.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/qcs404-evb.dtsi +deleted file mode 100644 +index a80c578484ba..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/qcs404-evb.dtsi ++++ /dev/null +@@ -1,395 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2018, Linaro Limited +- +-#include +-#include "qcs404.dtsi" +-#include "pms405.dtsi" +-#include +-#include +- +-/ { +- aliases { +- serial0 = &blsp1_uart2; +- serial1 = &blsp1_uart3; +- }; +- +- chosen { +- stdout-path = "serial0"; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_ch0_3p3: +- vdd_esmps3_3p3: vdd-esmps3-3p3-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "eSMPS3_3P3"; +- +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- usb3_vbus_reg: regulator-usb3-vbus { +- compatible = "regulator-fixed"; +- regulator-name = "VBUS_BOOST_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_vbus_boost_pin>; +- vin-supply = <&vph_pwr>; +- enable-active-high; +- +- /* TODO: Drop this when introducing role switching */ +- regulator-always-on; +- }; +-}; +- +-&blsp1_uart3 { +- status = "okay"; +- +- bluetooth { +- compatible = "qcom,wcn3990-bt"; +- vddio-supply = <&vreg_l6_1p8>; +- vddxo-supply = <&vreg_l5_1p8>; +- vddrf-supply = <&vreg_l1_1p3>; +- vddch0-supply = <&vdd_ch0_3p3>; +- +- local-bd-address = [ 02 00 00 00 5a ad ]; +- +- max-speed = <3200000>; +- }; +-}; +- +-&blsp1_dma { +- qcom,controlled-remotely; +-}; +- +-&blsp2_dma { +- qcom,controlled-remotely; +-}; +- +-&gcc { +- protected-clocks = , +- , +- , +- , +- <141>, /* GCC_WCSS_Q6_AHB_CLK */ +- <142>; /* GCC_WCSS_Q6_AXIM_CLK */ +-}; +- +-&pms405_spmi_regulators { +- vdd_s3-supply = <&vph_pwr>; +- +- pms405_s3: s3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vdd_apc"; +- regulator-initial-mode = <1>; +- regulator-min-microvolt = <1048000>; +- regulator-max-microvolt = <1384000>; +- }; +-}; +- +-&pcie { +- status = "okay"; +- +- perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&perst_state>; +-}; +- +-&pcie_phy { +- status = "okay"; +- +- vdda-vp-supply = <&vreg_l3_1p05>; +- vdda-vph-supply = <&vreg_l5_1p8>; +-}; +- +-&remoteproc_adsp { +- status = "okay"; +-}; +- +-&remoteproc_cdsp { +- status = "okay"; +-}; +- +-&remoteproc_wcss { +- status = "okay"; +-}; +- +-&rpm_requests { +- pms405-regulators { +- compatible = "qcom,rpm-pms405-regulators"; +- +- vdd_s1-supply = <&vph_pwr>; +- vdd_s2-supply = <&vph_pwr>; +- vdd_s3-supply = <&vph_pwr>; +- vdd_s4-supply = <&vph_pwr>; +- vdd_s5-supply = <&vph_pwr>; +- vdd_l1_l2-supply = <&vreg_s5_1p35>; +- vdd_l3_l8-supply = <&vreg_s5_1p35>; +- vdd_l4-supply = <&vreg_s5_1p35>; +- vdd_l5_l6-supply = <&vreg_s4_1p8>; +- vdd_l7-supply = <&vph_pwr>; +- vdd_l9-supply = <&vreg_s5_1p35>; +- vdd_l10_l11_l12_l13-supply = <&vph_pwr>; +- +- vreg_s4_1p8: s4 { +- regulator-min-microvolt = <1728000>; +- regulator-max-microvolt = <1920000>; +- }; +- +- vreg_s5_1p35: s5 { +- regulator-min-microvolt = <1352000>; +- regulator-max-microvolt = <1352000>; +- }; +- +- vreg_l1_1p3: l1 { +- regulator-min-microvolt = <1240000>; +- regulator-max-microvolt = <1352000>; +- }; +- +- vreg_l2_1p275: l2 { +- regulator-min-microvolt = <1048000>; +- regulator-max-microvolt = <1280000>; +- }; +- +- vreg_l3_1p05: l3 { +- regulator-min-microvolt = <1048000>; +- regulator-max-microvolt = <1160000>; +- }; +- +- vreg_l4_1p2: l4 { +- regulator-min-microvolt = <1144000>; +- regulator-max-microvolt = <1256000>; +- }; +- +- vreg_l5_1p8: l5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vreg_l6_1p8: l6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vreg_l7_1p8: l7 { +- regulator-min-microvolt = <1616000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- vreg_l8_1p2: l8 { +- regulator-min-microvolt = <1136000>; +- regulator-max-microvolt = <1352000>; +- }; +- +- vreg_l10_3p3: l10 { +- regulator-min-microvolt = <2936000>; +- regulator-max-microvolt = <3088000>; +- }; +- +- vreg_l11_sdc2: l11 { +- regulator-min-microvolt = <2696000>; +- regulator-max-microvolt = <3304000>; +- }; +- +- vreg_l12_3p3: l12 { +- regulator-min-microvolt = <3050000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vreg_l13_3p3: l13 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +-}; +- +-&sdcc1 { +- status = "okay"; +- +- supports-cqe; +- mmc-ddr-1_8v; +- mmc-hs400-1_8v; +- bus-width = <8>; +- non-removable; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc1_on>; +- pinctrl-1 = <&sdc1_off>; +-}; +- +-&tlmm { +- perst_state: perst { +- pins = "gpio43"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- output-low; +- }; +- +- sdc1_on: sdc1-on { +- clk { +- pins = "sdc1_clk"; +- bias-disable; +- drive-strength = <16>; +- }; +- +- cmd { +- pins = "sdc1_cmd"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- data { +- pins = "sdc1_data"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- rclk { +- pins = "sdc1_rclk"; +- bias-pull-down; +- }; +- }; +- +- sdc1_off: sdc1-off { +- clk { +- pins = "sdc1_clk"; +- bias-disable; +- drive-strength = <2>; +- }; +- +- cmd { +- pins = "sdc1_cmd"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- data { +- pins = "sdc1_data"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- rclk { +- pins = "sdc1_rclk"; +- bias-pull-down; +- }; +- }; +- +- usb3_id_pin: usb3-id-pin { +- pinmux { +- pins = "gpio116"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio116"; +- drive-strength = <2>; +- bias-pull-up; +- input-enable; +- }; +- }; +-}; +- +-&pms405_gpios { +- usb_vbus_boost_pin: usb-vbus-boost-pin { +- pinconf { +- pins = "gpio3"; +- function = PMIC_GPIO_FUNC_NORMAL; +- output-low; +- power-source = <1>; +- }; +- }; +- usb3_vbus_pin: usb3-vbus-pin { +- pinconf { +- pins = "gpio12"; +- function = PMIC_GPIO_FUNC_NORMAL; +- input-enable; +- bias-pull-down; +- power-source = <1>; +- }; +- }; +-}; +- +-&usb2 { +- status = "okay"; +-}; +- +-&usb2_phy_sec { +- vdd-supply = <&vreg_l4_1p2>; +- vdda1p8-supply = <&vreg_l5_1p8>; +- vdda3p3-supply = <&vreg_l12_3p3>; +- status = "okay"; +-}; +- +-&usb3 { +- status = "okay"; +- +- dwc3@7580000 { +- dr_mode = "host"; +- }; +-}; +- +-&usb2_phy_prim { +- vdd-supply = <&vreg_l4_1p2>; +- vdda1p8-supply = <&vreg_l5_1p8>; +- vdda3p3-supply = <&vreg_l12_3p3>; +- status = "okay"; +-}; +- +-&usb3_phy { +- vdd-supply = <&vreg_l3_1p05>; +- vdda1p8-supply = <&vreg_l5_1p8>; +- status = "okay"; +-}; +- +-&wifi { +- status = "okay"; +- vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>; +- vdd-1.8-xo-supply = <&vreg_l5_1p8>; +- vdd-1.3-rfa-supply = <&vreg_l1_1p3>; +-}; +- +-/* PINCTRL - additions to nodes defined in qcs404.dtsi */ +- +-&blsp1_uart2_default { +- rx { +- drive-strength = <2>; +- bias-disable; +- }; +- +- tx { +- drive-strength = <2>; +- bias-disable; +- }; +-}; +- +-&blsp1_uart3_default { +- cts { +- pins = "gpio84"; +- bias-disable; +- }; +- +- rts-tx { +- pins = "gpio85", "gpio82"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- rx { +- pins = "gpio83"; +- bias-pull-up; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/qcs404.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/qcs404.dtsi +deleted file mode 100644 +index ca5be1647980..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/qcs404.dtsi ++++ /dev/null +@@ -1,1642 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-// Copyright (c) 2018, Linaro Limited +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&intc>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- chosen { }; +- +- clocks { +- xo_board: xo-board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <19200000>; +- }; +- +- sleep_clk: sleep-clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- CPU0: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x100>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- next-level-cache = <&L2_0>; +- #cooling-cells = <2>; +- clocks = <&apcs_glb>; +- operating-points-v2 = <&cpu_opp_table>; +- power-domains = <&cpr>; +- power-domain-names = "cpr"; +- }; +- +- CPU1: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x101>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- next-level-cache = <&L2_0>; +- #cooling-cells = <2>; +- clocks = <&apcs_glb>; +- operating-points-v2 = <&cpu_opp_table>; +- power-domains = <&cpr>; +- power-domain-names = "cpr"; +- }; +- +- CPU2: cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x102>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- next-level-cache = <&L2_0>; +- #cooling-cells = <2>; +- clocks = <&apcs_glb>; +- operating-points-v2 = <&cpu_opp_table>; +- power-domains = <&cpr>; +- power-domain-names = "cpr"; +- }; +- +- CPU3: cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x103>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- next-level-cache = <&L2_0>; +- #cooling-cells = <2>; +- clocks = <&apcs_glb>; +- operating-points-v2 = <&cpu_opp_table>; +- power-domains = <&cpr>; +- power-domain-names = "cpr"; +- }; +- +- L2_0: l2-cache { +- compatible = "cache"; +- cache-level = <2>; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP_0: cpu-sleep-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "standalone-power-collapse"; +- arm,psci-suspend-param = <0x40000003>; +- entry-latency-us = <125>; +- exit-latency-us = <180>; +- min-residency-us = <595>; +- local-timer-stop; +- }; +- }; +- }; +- +- cpu_opp_table: cpu-opp-table { +- compatible = "operating-points-v2-kryo-cpu"; +- opp-shared; +- +- opp-1094400000 { +- opp-hz = /bits/ 64 <1094400000>; +- required-opps = <&cpr_opp1>; +- }; +- opp-1248000000 { +- opp-hz = /bits/ 64 <1248000000>; +- required-opps = <&cpr_opp2>; +- }; +- opp-1401600000 { +- opp-hz = /bits/ 64 <1401600000>; +- required-opps = <&cpr_opp3>; +- }; +- }; +- +- cpr_opp_table: cpr-opp-table { +- compatible = "operating-points-v2-qcom-level"; +- +- cpr_opp1: opp1 { +- opp-level = <1>; +- qcom,opp-fuse-level = <1>; +- }; +- cpr_opp2: opp2 { +- opp-level = <2>; +- qcom,opp-fuse-level = <2>; +- }; +- cpr_opp3: opp3 { +- opp-level = <3>; +- qcom,opp-fuse-level = <3>; +- }; +- }; +- +- firmware { +- scm: scm { +- compatible = "qcom,scm-qcs404", "qcom,scm"; +- #reset-cells = <1>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- /* We expect the bootloader to fill in the size */ +- reg = <0 0x80000000 0 0>; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- tz_apps_mem: memory@85900000 { +- reg = <0 0x85900000 0 0x500000>; +- no-map; +- }; +- +- xbl_mem: memory@85e00000 { +- reg = <0 0x85e00000 0 0x100000>; +- no-map; +- }; +- +- smem_region: memory@85f00000 { +- reg = <0 0x85f00000 0 0x200000>; +- no-map; +- }; +- +- tz_mem: memory@86100000 { +- reg = <0 0x86100000 0 0x300000>; +- no-map; +- }; +- +- wlan_fw_mem: memory@86400000 { +- reg = <0 0x86400000 0 0x1100000>; +- no-map; +- }; +- +- adsp_fw_mem: memory@87500000 { +- reg = <0 0x87500000 0 0x1a00000>; +- no-map; +- }; +- +- cdsp_fw_mem: memory@88f00000 { +- reg = <0 0x88f00000 0 0x600000>; +- no-map; +- }; +- +- wlan_msa_mem: memory@89500000 { +- reg = <0 0x89500000 0 0x100000>; +- no-map; +- }; +- +- uefi_mem: memory@9f800000 { +- reg = <0 0x9f800000 0 0x800000>; +- no-map; +- }; +- }; +- +- rpm-glink { +- compatible = "qcom,glink-rpm"; +- +- interrupts = ; +- qcom,rpm-msg-ram = <&rpm_msg_ram>; +- mboxes = <&apcs_glb 0>; +- +- rpm_requests: glink-channel { +- compatible = "qcom,rpm-qcs404"; +- qcom,glink-channels = "rpm_requests"; +- +- rpmcc: clock-controller { +- compatible = "qcom,rpmcc-qcs404"; +- #clock-cells = <1>; +- }; +- +- rpmpd: power-controller { +- compatible = "qcom,qcs404-rpmpd"; +- #power-domain-cells = <1>; +- operating-points-v2 = <&rpmpd_opp_table>; +- +- rpmpd_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- rpmpd_opp_ret: opp1 { +- opp-level = <16>; +- }; +- +- rpmpd_opp_ret_plus: opp2 { +- opp-level = <32>; +- }; +- +- rpmpd_opp_min_svs: opp3 { +- opp-level = <48>; +- }; +- +- rpmpd_opp_low_svs: opp4 { +- opp-level = <64>; +- }; +- +- rpmpd_opp_svs: opp5 { +- opp-level = <128>; +- }; +- +- rpmpd_opp_svs_plus: opp6 { +- opp-level = <192>; +- }; +- +- rpmpd_opp_nom: opp7 { +- opp-level = <256>; +- }; +- +- rpmpd_opp_nom_plus: opp8 { +- opp-level = <320>; +- }; +- +- rpmpd_opp_turbo: opp9 { +- opp-level = <384>; +- }; +- +- rpmpd_opp_turbo_no_cpr: opp10 { +- opp-level = <416>; +- }; +- +- rpmpd_opp_turbo_plus: opp11 { +- opp-level = <512>; +- }; +- }; +- }; +- }; +- }; +- +- smem { +- compatible = "qcom,smem"; +- +- memory-region = <&smem_region>; +- qcom,rpm-msg-ram = <&rpm_msg_ram>; +- +- hwlocks = <&tcsr_mutex 3>; +- }; +- +- tcsr_mutex: hwlock { +- compatible = "qcom,tcsr-mutex"; +- syscon = <&tcsr_mutex_regs 0 0x1000>; +- #hwlock-cells = <1>; +- }; +- +- soc: soc@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0 0xffffffff>; +- compatible = "simple-bus"; +- +- turingcc: clock-controller@800000 { +- compatible = "qcom,qcs404-turingcc"; +- reg = <0x00800000 0x30000>; +- clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; +- +- #clock-cells = <1>; +- #reset-cells = <1>; +- +- status = "disabled"; +- }; +- +- rpm_msg_ram: sram@60000 { +- compatible = "qcom,rpm-msg-ram"; +- reg = <0x00060000 0x6000>; +- }; +- +- usb3_phy: phy@78000 { +- compatible = "qcom,usb-ss-28nm-phy"; +- reg = <0x00078000 0x400>; +- #phy-cells = <0>; +- clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, +- <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, +- <&gcc GCC_USB3_PHY_PIPE_CLK>; +- clock-names = "ref", "ahb", "pipe"; +- resets = <&gcc GCC_USB3_PHY_BCR>, +- <&gcc GCC_USB3PHY_PHY_BCR>; +- reset-names = "com", "phy"; +- status = "disabled"; +- }; +- +- usb2_phy_prim: phy@7a000 { +- compatible = "qcom,usb-hs-28nm-femtophy"; +- reg = <0x0007a000 0x200>; +- #phy-cells = <0>; +- clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, +- <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, +- <&gcc GCC_USB2A_PHY_SLEEP_CLK>; +- clock-names = "ref", "ahb", "sleep"; +- resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, +- <&gcc GCC_USB2A_PHY_BCR>; +- reset-names = "phy", "por"; +- status = "disabled"; +- }; +- +- usb2_phy_sec: phy@7c000 { +- compatible = "qcom,usb-hs-28nm-femtophy"; +- reg = <0x0007c000 0x200>; +- #phy-cells = <0>; +- clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, +- <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, +- <&gcc GCC_USB2A_PHY_SLEEP_CLK>; +- clock-names = "ref", "ahb", "sleep"; +- resets = <&gcc GCC_QUSB2_PHY_BCR>, +- <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; +- reset-names = "phy", "por"; +- status = "disabled"; +- }; +- +- qfprom: qfprom@a4000 { +- compatible = "qcom,qfprom"; +- reg = <0x000a4000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- tsens_caldata: caldata@d0 { +- reg = <0x1f8 0x14>; +- }; +- cpr_efuse_speedbin: speedbin@13c { +- reg = <0x13c 0x4>; +- bits = <2 3>; +- }; +- cpr_efuse_quot_offset1: qoffset1@231 { +- reg = <0x231 0x4>; +- bits = <4 7>; +- }; +- cpr_efuse_quot_offset2: qoffset2@232 { +- reg = <0x232 0x4>; +- bits = <3 7>; +- }; +- cpr_efuse_quot_offset3: qoffset3@233 { +- reg = <0x233 0x4>; +- bits = <2 7>; +- }; +- cpr_efuse_init_voltage1: ivoltage1@229 { +- reg = <0x229 0x4>; +- bits = <4 6>; +- }; +- cpr_efuse_init_voltage2: ivoltage2@22a { +- reg = <0x22a 0x4>; +- bits = <2 6>; +- }; +- cpr_efuse_init_voltage3: ivoltage3@22b { +- reg = <0x22b 0x4>; +- bits = <0 6>; +- }; +- cpr_efuse_quot1: quot1@22b { +- reg = <0x22b 0x4>; +- bits = <6 12>; +- }; +- cpr_efuse_quot2: quot2@22d { +- reg = <0x22d 0x4>; +- bits = <2 12>; +- }; +- cpr_efuse_quot3: quot3@230 { +- reg = <0x230 0x4>; +- bits = <0 12>; +- }; +- cpr_efuse_ring1: ring1@228 { +- reg = <0x228 0x4>; +- bits = <0 3>; +- }; +- cpr_efuse_ring2: ring2@228 { +- reg = <0x228 0x4>; +- bits = <4 3>; +- }; +- cpr_efuse_ring3: ring3@229 { +- reg = <0x229 0x4>; +- bits = <0 3>; +- }; +- cpr_efuse_revision: revision@218 { +- reg = <0x218 0x4>; +- bits = <3 3>; +- }; +- }; +- +- rng: rng@e3000 { +- compatible = "qcom,prng-ee"; +- reg = <0x000e3000 0x1000>; +- clocks = <&gcc GCC_PRNG_AHB_CLK>; +- clock-names = "core"; +- }; +- +- bimc: interconnect@400000 { +- reg = <0x00400000 0x80000>; +- compatible = "qcom,qcs404-bimc"; +- #interconnect-cells = <1>; +- clock-names = "bus", "bus_a"; +- clocks = <&rpmcc RPM_SMD_BIMC_CLK>, +- <&rpmcc RPM_SMD_BIMC_A_CLK>; +- }; +- +- tsens: thermal-sensor@4a9000 { +- compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; +- reg = <0x004a9000 0x1000>, /* TM */ +- <0x004a8000 0x1000>; /* SROT */ +- nvmem-cells = <&tsens_caldata>; +- nvmem-cell-names = "calib"; +- #qcom,sensors = <10>; +- interrupts = ; +- interrupt-names = "uplow"; +- #thermal-sensor-cells = <1>; +- }; +- +- pcnoc: interconnect@500000 { +- reg = <0x00500000 0x15080>; +- compatible = "qcom,qcs404-pcnoc"; +- #interconnect-cells = <1>; +- clock-names = "bus", "bus_a"; +- clocks = <&rpmcc RPM_SMD_PNOC_CLK>, +- <&rpmcc RPM_SMD_PNOC_A_CLK>; +- }; +- +- snoc: interconnect@580000 { +- reg = <0x00580000 0x23080>; +- compatible = "qcom,qcs404-snoc"; +- #interconnect-cells = <1>; +- clock-names = "bus", "bus_a"; +- clocks = <&rpmcc RPM_SMD_SNOC_CLK>, +- <&rpmcc RPM_SMD_SNOC_A_CLK>; +- }; +- +- remoteproc_cdsp: remoteproc@b00000 { +- compatible = "qcom,qcs404-cdsp-pas"; +- reg = <0x00b00000 0x4040>; +- +- interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, +- <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack"; +- +- clocks = <&xo_board>, +- <&gcc GCC_CDSP_CFG_AHB_CLK>, +- <&gcc GCC_CDSP_TBU_CLK>, +- <&gcc GCC_BIMC_CDSP_CLK>, +- <&turingcc TURING_WRAPPER_AON_CLK>, +- <&turingcc TURING_Q6SS_AHBS_AON_CLK>, +- <&turingcc TURING_Q6SS_AHBM_AON_CLK>, +- <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; +- clock-names = "xo", +- "sway", +- "tbu", +- "bimc", +- "ahb_aon", +- "q6ss_slave", +- "q6ss_master", +- "q6_axim"; +- +- resets = <&gcc GCC_CDSP_RESTART>; +- reset-names = "restart"; +- +- qcom,halt-regs = <&tcsr 0x19004>; +- +- memory-region = <&cdsp_fw_mem>; +- +- qcom,smem-states = <&cdsp_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- status = "disabled"; +- +- glink-edge { +- interrupts = ; +- +- qcom,remote-pid = <5>; +- mboxes = <&apcs_glb 12>; +- +- label = "cdsp"; +- }; +- }; +- +- usb3: usb@7678800 { +- compatible = "qcom,dwc3"; +- reg = <0x07678800 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- clocks = <&gcc GCC_USB30_MASTER_CLK>, +- <&gcc GCC_SYS_NOC_USB3_CLK>, +- <&gcc GCC_USB30_SLEEP_CLK>, +- <&gcc GCC_USB30_MOCK_UTMI_CLK>; +- clock-names = "core", "iface", "sleep", "mock_utmi"; +- assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_MASTER_CLK>; +- assigned-clock-rates = <19200000>, <200000000>; +- status = "disabled"; +- +- dwc3@7580000 { +- compatible = "snps,dwc3"; +- reg = <0x07580000 0xcd00>; +- interrupts = ; +- phys = <&usb2_phy_sec>, <&usb3_phy>; +- phy-names = "usb2-phy", "usb3-phy"; +- snps,has-lpm-erratum; +- snps,hird-threshold = /bits/ 8 <0x10>; +- snps,usb3_lpm_capable; +- dr_mode = "otg"; +- }; +- }; +- +- usb2: usb@79b8800 { +- compatible = "qcom,dwc3"; +- reg = <0x079b8800 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, +- <&gcc GCC_PCNOC_USB2_CLK>, +- <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, +- <&gcc GCC_USB20_MOCK_UTMI_CLK>; +- clock-names = "core", "iface", "sleep", "mock_utmi"; +- assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, +- <&gcc GCC_USB_HS_SYSTEM_CLK>; +- assigned-clock-rates = <19200000>, <133333333>; +- status = "disabled"; +- +- dwc3@78c0000 { +- compatible = "snps,dwc3"; +- reg = <0x078c0000 0xcc00>; +- interrupts = ; +- phys = <&usb2_phy_prim>; +- phy-names = "usb2-phy"; +- snps,has-lpm-erratum; +- snps,hird-threshold = /bits/ 8 <0x10>; +- snps,usb3_lpm_capable; +- dr_mode = "peripheral"; +- }; +- }; +- +- tlmm: pinctrl@1000000 { +- compatible = "qcom,qcs404-pinctrl"; +- reg = <0x01000000 0x200000>, +- <0x01300000 0x200000>, +- <0x07b00000 0x200000>; +- reg-names = "south", "north", "east"; +- interrupts = ; +- gpio-ranges = <&tlmm 0 0 120>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- blsp1_i2c0_default: blsp1-i2c0-default { +- pins = "gpio32", "gpio33"; +- function = "blsp_i2c0"; +- }; +- +- blsp1_i2c1_default: blsp1-i2c1-default { +- pins = "gpio24", "gpio25"; +- function = "blsp_i2c1"; +- }; +- +- blsp1_i2c2_default: blsp1-i2c2-default { +- sda { +- pins = "gpio19"; +- function = "blsp_i2c_sda_a2"; +- }; +- +- scl { +- pins = "gpio20"; +- function = "blsp_i2c_scl_a2"; +- }; +- }; +- +- blsp1_i2c3_default: blsp1-i2c3-default { +- pins = "gpio84", "gpio85"; +- function = "blsp_i2c3"; +- }; +- +- blsp1_i2c4_default: blsp1-i2c4-default { +- pins = "gpio117", "gpio118"; +- function = "blsp_i2c4"; +- }; +- +- blsp1_uart0_default: blsp1-uart0-default { +- pins = "gpio30", "gpio31", "gpio32", "gpio33"; +- function = "blsp_uart0"; +- }; +- +- blsp1_uart1_default: blsp1-uart1-default { +- pins = "gpio22", "gpio23"; +- function = "blsp_uart1"; +- }; +- +- blsp1_uart2_default: blsp1-uart2-default { +- rx { +- pins = "gpio18"; +- function = "blsp_uart_rx_a2"; +- }; +- +- tx { +- pins = "gpio17"; +- function = "blsp_uart_tx_a2"; +- }; +- }; +- +- blsp1_uart3_default: blsp1-uart3-default { +- pins = "gpio82", "gpio83", "gpio84", "gpio85"; +- function = "blsp_uart3"; +- }; +- +- blsp2_i2c0_default: blsp2-i2c0-default { +- pins = "gpio28", "gpio29"; +- function = "blsp_i2c5"; +- }; +- +- blsp1_spi0_default: blsp1-spi0-default { +- pins = "gpio30", "gpio31", "gpio32", "gpio33"; +- function = "blsp_spi0"; +- }; +- +- blsp1_spi1_default: blsp1-spi1-default { +- pins = "gpio22", "gpio23", "gpio24", "gpio25"; +- function = "blsp_spi1"; +- }; +- +- blsp1_spi2_default: blsp1-spi2-default { +- pins = "gpio17", "gpio18", "gpio19", "gpio20"; +- function = "blsp_spi2"; +- }; +- +- blsp1_spi3_default: blsp1-spi3-default { +- pins = "gpio82", "gpio83", "gpio84", "gpio85"; +- function = "blsp_spi3"; +- }; +- +- blsp1_spi4_default: blsp1-spi4-default { +- pins = "gpio37", "gpio38", "gpio117", "gpio118"; +- function = "blsp_spi4"; +- }; +- +- blsp2_spi0_default: blsp2-spi0-default { +- pins = "gpio26", "gpio27", "gpio28", "gpio29"; +- function = "blsp_spi5"; +- }; +- +- blsp2_uart0_default: blsp2-uart0-default { +- pins = "gpio26", "gpio27", "gpio28", "gpio29"; +- function = "blsp_uart5"; +- }; +- }; +- +- gcc: clock-controller@1800000 { +- compatible = "qcom,gcc-qcs404"; +- reg = <0x01800000 0x80000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- +- assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; +- assigned-clock-rates = <19200000>; +- }; +- +- tcsr_mutex_regs: syscon@1905000 { +- compatible = "syscon"; +- reg = <0x01905000 0x20000>; +- }; +- +- tcsr: syscon@1937000 { +- compatible = "syscon"; +- reg = <0x01937000 0x25000>; +- }; +- +- spmi_bus: spmi@200f000 { +- compatible = "qcom,spmi-pmic-arb"; +- reg = <0x0200f000 0x001000>, +- <0x02400000 0x800000>, +- <0x02c00000 0x800000>, +- <0x03800000 0x200000>, +- <0x0200a000 0x002100>; +- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; +- interrupt-names = "periph_irq"; +- interrupts = ; +- qcom,ee = <0>; +- qcom,channel = <0>; +- #address-cells = <2>; +- #size-cells = <0>; +- interrupt-controller; +- #interrupt-cells = <4>; +- }; +- +- remoteproc_wcss: remoteproc@7400000 { +- compatible = "qcom,qcs404-wcss-pas"; +- reg = <0x07400000 0x4040>; +- +- interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, +- <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack"; +- +- clocks = <&xo_board>; +- clock-names = "xo"; +- +- memory-region = <&wlan_fw_mem>; +- +- qcom,smem-states = <&wcss_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- status = "disabled"; +- +- glink-edge { +- interrupts = ; +- +- qcom,remote-pid = <1>; +- mboxes = <&apcs_glb 16>; +- +- label = "wcss"; +- }; +- }; +- +- pcie_phy: phy@7786000 { +- compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; +- reg = <0x07786000 0xb8>; +- +- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; +- resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, +- <&gcc 21>; +- reset-names = "phy", "pipe"; +- +- clock-output-names = "pcie_0_pipe_clk"; +- #phy-cells = <0>; +- +- status = "disabled"; +- }; +- +- sdcc1: sdcc@7804000 { +- compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; +- reg = <0x07804000 0x1000>, <0x7805000 0x1000>; +- reg-names = "hc", "cqhci"; +- +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- +- clocks = <&gcc GCC_SDCC1_APPS_CLK>, +- <&gcc GCC_SDCC1_AHB_CLK>, +- <&xo_board>; +- clock-names = "core", "iface", "xo"; +- +- status = "disabled"; +- }; +- +- blsp1_dma: dma-controller@7884000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0x07884000 0x25000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- status = "okay"; +- }; +- +- blsp1_uart0: serial@78af000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x078af000 0x200>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp1_dma 1>, <&blsp1_dma 0>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp1_uart0_default>; +- status = "disabled"; +- }; +- +- blsp1_uart1: serial@78b0000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x078b0000 0x200>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp1_dma 3>, <&blsp1_dma 2>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp1_uart1_default>; +- status = "disabled"; +- }; +- +- blsp1_uart2: serial@78b1000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x078b1000 0x200>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp1_dma 5>, <&blsp1_dma 4>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp1_uart2_default>; +- status = "okay"; +- }; +- +- ethernet: ethernet@7a80000 { +- compatible = "qcom,qcs404-ethqos"; +- reg = <0x07a80000 0x10000>, +- <0x07a96000 0x100>; +- reg-names = "stmmaceth", "rgmii"; +- clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; +- clocks = <&gcc GCC_ETH_AXI_CLK>, +- <&gcc GCC_ETH_SLAVE_AHB_CLK>, +- <&gcc GCC_ETH_PTP_CLK>, +- <&gcc GCC_ETH_RGMII_CLK>; +- interrupts = , +- ; +- interrupt-names = "macirq", "eth_lpi"; +- +- snps,tso; +- rx-fifo-depth = <4096>; +- tx-fifo-depth = <4096>; +- +- status = "disabled"; +- }; +- +- wifi: wifi@a000000 { +- compatible = "qcom,wcn3990-wifi"; +- reg = <0xa000000 0x800000>; +- reg-names = "membase"; +- memory-region = <&wlan_msa_mem>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- status = "disabled"; +- }; +- +- blsp1_uart3: serial@78b2000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x078b2000 0x200>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp1_dma 7>, <&blsp1_dma 6>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp1_uart3_default>; +- status = "disabled"; +- }; +- +- blsp1_i2c0: i2c@78b5000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x078b5000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp1_i2c0_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp1_spi0: spi@78b5000 { +- compatible = "qcom,spi-qup-v2.2.1"; +- reg = <0x078b5000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp1_spi0_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp1_i2c1: i2c@78b6000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x078b6000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp1_i2c1_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp1_spi1: spi@78b6000 { +- compatible = "qcom,spi-qup-v2.2.1"; +- reg = <0x078b6000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp1_spi1_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp1_i2c2: i2c@78b7000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x078b7000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp1_i2c2_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp1_spi2: spi@78b7000 { +- compatible = "qcom,spi-qup-v2.2.1"; +- reg = <0x078b7000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp1_spi2_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp1_i2c3: i2c@78b8000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x078b8000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp1_i2c3_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp1_spi3: spi@78b8000 { +- compatible = "qcom,spi-qup-v2.2.1"; +- reg = <0x078b8000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp1_spi3_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp1_i2c4: i2c@78b9000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x078b9000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp1_i2c4_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp1_spi4: spi@78b9000 { +- compatible = "qcom,spi-qup-v2.2.1"; +- reg = <0x078b9000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp1_spi4_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp2_dma: dma-controller@7ac4000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0x07ac4000 0x17000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- status = "disabled"; +- }; +- +- blsp2_uart0: serial@7aef000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x07aef000 0x200>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp2_dma 1>, <&blsp2_dma 0>; +- dma-names = "rx", "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp2_uart0_default>; +- status = "disabled"; +- }; +- +- blsp2_i2c0: i2c@7af5000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x07af5000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_AHB_CLK>, +- <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp2_i2c0_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp2_spi0: spi@7af5000 { +- compatible = "qcom,spi-qup-v2.2.1"; +- reg = <0x07af5000 0x600>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_AHB_CLK>, +- <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>; +- clock-names = "iface", "core"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp2_spi0_default>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- imem@8600000 { +- compatible = "simple-mfd"; +- reg = <0x08600000 0x1000>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0 0x08600000 0x1000>; +- +- pil-reloc@94c { +- compatible = "qcom,pil-reloc-info"; +- reg = <0x94c 0xc8>; +- }; +- }; +- +- intc: interrupt-controller@b000000 { +- compatible = "qcom,msm-qgic2"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x0b000000 0x1000>, +- <0x0b002000 0x1000>; +- }; +- +- apcs_glb: mailbox@b011000 { +- compatible = "qcom,qcs404-apcs-apps-global", "syscon"; +- reg = <0x0b011000 0x1000>; +- #mbox-cells = <1>; +- clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; +- clock-names = "pll", "aux"; +- #clock-cells = <0>; +- }; +- +- apcs_hfpll: clock-controller@b016000 { +- compatible = "qcom,hfpll"; +- reg = <0x0b016000 0x30>; +- #clock-cells = <0>; +- clock-output-names = "apcs_hfpll"; +- clocks = <&xo_board>; +- clock-names = "xo"; +- }; +- +- watchdog@b017000 { +- compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; +- reg = <0x0b017000 0x1000>; +- clocks = <&sleep_clk>; +- }; +- +- cpr: power-controller@b018000 { +- compatible = "qcom,qcs404-cpr", "qcom,cpr"; +- reg = <0x0b018000 0x1000>; +- interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; +- clocks = <&xo_board>; +- clock-names = "ref"; +- vdd-apc-supply = <&pms405_s3>; +- #power-domain-cells = <0>; +- operating-points-v2 = <&cpr_opp_table>; +- acc-syscon = <&tcsr>; +- +- nvmem-cells = <&cpr_efuse_quot_offset1>, +- <&cpr_efuse_quot_offset2>, +- <&cpr_efuse_quot_offset3>, +- <&cpr_efuse_init_voltage1>, +- <&cpr_efuse_init_voltage2>, +- <&cpr_efuse_init_voltage3>, +- <&cpr_efuse_quot1>, +- <&cpr_efuse_quot2>, +- <&cpr_efuse_quot3>, +- <&cpr_efuse_ring1>, +- <&cpr_efuse_ring2>, +- <&cpr_efuse_ring3>, +- <&cpr_efuse_revision>; +- nvmem-cell-names = "cpr_quotient_offset1", +- "cpr_quotient_offset2", +- "cpr_quotient_offset3", +- "cpr_init_voltage1", +- "cpr_init_voltage2", +- "cpr_init_voltage3", +- "cpr_quotient1", +- "cpr_quotient2", +- "cpr_quotient3", +- "cpr_ring_osc1", +- "cpr_ring_osc2", +- "cpr_ring_osc3", +- "cpr_fuse_revision"; +- }; +- +- timer@b120000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "arm,armv7-timer-mem"; +- reg = <0x0b120000 0x1000>; +- clock-frequency = <19200000>; +- +- frame@b121000 { +- frame-number = <0>; +- interrupts = , +- ; +- reg = <0x0b121000 0x1000>, +- <0x0b122000 0x1000>; +- }; +- +- frame@b123000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0x0b123000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b124000 { +- frame-number = <2>; +- interrupts = ; +- reg = <0x0b124000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b125000 { +- frame-number = <3>; +- interrupts = ; +- reg = <0x0b125000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b126000 { +- frame-number = <4>; +- interrupts = ; +- reg = <0x0b126000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b127000 { +- frame-number = <5>; +- interrupts = ; +- reg = <0xb127000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b128000 { +- frame-number = <6>; +- interrupts = ; +- reg = <0x0b128000 0x1000>; +- status = "disabled"; +- }; +- }; +- +- remoteproc_adsp: remoteproc@c700000 { +- compatible = "qcom,qcs404-adsp-pas"; +- reg = <0x0c700000 0x4040>; +- +- interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack"; +- +- clocks = <&xo_board>; +- clock-names = "xo"; +- +- memory-region = <&adsp_fw_mem>; +- +- qcom,smem-states = <&adsp_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- status = "disabled"; +- +- glink-edge { +- interrupts = ; +- +- qcom,remote-pid = <2>; +- mboxes = <&apcs_glb 8>; +- +- label = "adsp"; +- }; +- }; +- +- pcie: pci@10000000 { +- compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; +- reg = <0x10000000 0xf1d>, +- <0x10000f20 0xa8>, +- <0x07780000 0x2000>, +- <0x10001000 0x2000>; +- reg-names = "dbi", "elbi", "parf", "config"; +- device_type = "pci"; +- linux,pci-domain = <0>; +- bus-range = <0x00 0xff>; +- num-lanes = <1>; +- #address-cells = <3>; +- #size-cells = <2>; +- +- ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */ +- <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ +- +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ +- <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ +- <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ +- <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ +- clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, +- <&gcc GCC_PCIE_0_AUX_CLK>, +- <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, +- <&gcc GCC_PCIE_0_SLV_AXI_CLK>; +- clock-names = "iface", "aux", "master_bus", "slave_bus"; +- +- resets = <&gcc 18>, +- <&gcc 17>, +- <&gcc 15>, +- <&gcc 19>, +- <&gcc GCC_PCIE_0_BCR>, +- <&gcc 16>; +- reset-names = "axi_m", +- "axi_s", +- "axi_m_sticky", +- "pipe_sticky", +- "pwr", +- "ahb"; +- +- phys = <&pcie_phy>; +- phy-names = "pciephy"; +- +- status = "disabled"; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- smp2p-adsp { +- compatible = "qcom,smp2p"; +- qcom,smem = <443>, <429>; +- interrupts = ; +- mboxes = <&apcs_glb 10>; +- qcom,local-pid = <0>; +- qcom,remote-pid = <2>; +- +- adsp_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- adsp_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-cdsp { +- compatible = "qcom,smp2p"; +- qcom,smem = <94>, <432>; +- interrupts = ; +- mboxes = <&apcs_glb 14>; +- qcom,local-pid = <0>; +- qcom,remote-pid = <5>; +- +- cdsp_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- cdsp_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-wcss { +- compatible = "qcom,smp2p"; +- qcom,smem = <435>, <428>; +- interrupts = ; +- mboxes = <&apcs_glb 18>; +- qcom,local-pid = <0>; +- qcom,remote-pid = <1>; +- +- wcss_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- wcss_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- thermal-zones { +- aoss-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 0>; +- +- trips { +- aoss_alert0: trip-point0 { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- q6-hvx-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 1>; +- +- trips { +- q6_hvx_alert0: trip-point0 { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- lpass-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 2>; +- +- trips { +- lpass_alert0: trip-point0 { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- wlan-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 3>; +- +- trips { +- wlan_alert0: trip-point0 { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- cluster-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 4>; +- +- trips { +- cluster_alert0: trip-point0 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- cluster_alert1: trip-point1 { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cluster_crit: cluster_crit { +- temperature = <120000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- cooling-maps { +- map0 { +- trip = <&cluster_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 5>; +- +- trips { +- cpu0_alert0: trip-point0 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- cpu0_alert1: trip-point1 { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu0_crit: cpu_crit { +- temperature = <120000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- cooling-maps { +- map0 { +- trip = <&cpu0_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 6>; +- +- trips { +- cpu1_alert0: trip-point0 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- cpu1_alert1: trip-point1 { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu1_crit: cpu_crit { +- temperature = <120000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- cooling-maps { +- map0 { +- trip = <&cpu1_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 7>; +- +- trips { +- cpu2_alert0: trip-point0 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- cpu2_alert1: trip-point1 { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu2_crit: cpu_crit { +- temperature = <120000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- cooling-maps { +- map0 { +- trip = <&cpu2_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 8>; +- +- trips { +- cpu3_alert0: trip-point0 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- cpu3_alert1: trip-point1 { +- temperature = <105000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu3_crit: cpu_crit { +- temperature = <120000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- cooling-maps { +- map0 { +- trip = <&cpu3_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- gpu-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 9>; +- +- trips { +- gpu_alert0: trip-point0 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/qrb5165-rb5.dts b/scripts/dtc/include-prefixes/arm64/qcom/qrb5165-rb5.dts +deleted file mode 100644 +index 28d5b5528516..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/qrb5165-rb5.dts ++++ /dev/null +@@ -1,1296 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Linaro Ltd. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include "sm8250.dtsi" +-#include "pm8150.dtsi" +-#include "pm8150b.dtsi" +-#include "pm8150l.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. Robotics RB5"; +- compatible = "qcom,qrb5165-rb5", "qcom,sm8250"; +- +- aliases { +- serial0 = &uart12; +- sdhc2 = &sdhc_2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- /* Fixed crystal oscillator dedicated to MCP2518FD */ +- clk40M: can_clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <40000000>; +- }; +- +- dc12v: dc12v-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "DC12V"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con: endpoint { +- remote-endpoint = <<9611_out>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- user4 { +- label = "green:user4"; +- gpios = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "panic-indicator"; +- default-state = "off"; +- }; +- +- wlan { +- label = "yellow:wlan"; +- gpios = <&pm8150_gpios 9 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "phy0tx"; +- default-state = "off"; +- }; +- +- bt { +- label = "blue:bt"; +- gpios = <&pm8150_gpios 7 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "bluetooth-power"; +- default-state = "off"; +- }; +- +- }; +- +- lt9611_1v2: lt9611-vdd12-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "LT9611_1V2"; +- +- vin-supply = <&vdc_3v3>; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- lt9611_3v3: lt9611-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "LT9611_3V3"; +- +- vin-supply = <&vdc_3v3>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- thermal-zones { +- conn-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&pm8150b_adc_tm 0>; +- +- trips { +- active-config0 { +- temperature = <125000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- pm8150l-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&pm8150l_adc_tm 1>; +- +- trips { +- active-config0 { +- temperature = <50000>; +- hysteresis = <4000>; +- type = "passive"; +- }; +- }; +- }; +- +- skin-msm-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&pm8150l_adc_tm 0>; +- +- trips { +- active-config0 { +- temperature = <50000>; +- hysteresis = <4000>; +- type = "passive"; +- }; +- }; +- }; +- +- wifi-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&pm8150_adc_tm 1>; +- +- trips { +- active-config0 { +- temperature = <52000>; +- hysteresis = <4000>; +- type = "passive"; +- }; +- }; +- }; +- +- xo-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&pm8150_adc_tm 0>; +- +- trips { +- active-config0 { +- temperature = <50000>; +- hysteresis = <4000>; +- type = "passive"; +- }; +- }; +- }; +- }; +- +- vbat: vbat-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "VBAT"; +- vin-supply = <&vreg_l11c_3p3>; +- regulator-min-microvolt = <4200000>; +- regulator-max-microvolt = <4200000>; +- regulator-always-on; +- }; +- +- vbat_som: vbat-som-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "VBAT_SOM"; +- vin-supply = <&dc12v>; +- regulator-min-microvolt = <4200000>; +- regulator-max-microvolt = <4200000>; +- regulator-always-on; +- }; +- +- vdc_3v3: vdc-3v3-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "VDC_3V3"; +- vin-supply = <&vreg_l11c_3p3>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdc_5v: vdc-5v-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "VDC_5V"; +- +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- vin-supply = <&vreg_l11c_3p3>; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- regulator-always-on; +- }; +- +- vreg_s4a_1p8: vreg-s4a-1p8 { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_s4a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +-}; +- +-&adsp { +- status = "okay"; +- firmware-name = "qcom/sm8250/adsp.mbn"; +-}; +- +-&apps_rsc { +- pm8009-rpmh-regulators { +- compatible = "qcom,pm8009-1-rpmh-regulators"; +- qcom,pmic-id = "f"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-l2-supply = <&vreg_s8c_1p3>; +- vdd-l5-l6-supply = <&vreg_bob>; +- vdd-l7-supply = <&vreg_s4a_1p8>; +- +- vreg_s2f_0p95: smps2 { +- regulator-name = "vreg_s2f_0p95"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <952000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l1f_1p1: ldo1 { +- regulator-name = "vreg_l1f_1p1"; +- regulator-min-microvolt = <1104000>; +- regulator-max-microvolt = <1104000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l2f_1p2: ldo2 { +- regulator-name = "vreg_l2f_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6f_2p8: ldo6 { +- regulator-name = "vreg_l6f_2p8"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7f_1p8: ldo7 { +- regulator-name = "vreg_l7f_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- }; +- +- pm8150-rpmh-regulators { +- compatible = "qcom,pm8150-rpmh-regulators"; +- qcom,pmic-id = "a"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- vdd-s9-supply = <&vph_pwr>; +- vdd-s10-supply = <&vph_pwr>; +- vdd-l2-l10-supply = <&vreg_bob>; +- vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p95>; +- vdd-l6-l9-supply = <&vreg_s8c_1p3>; +- vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; +- vdd-l13-l16-l17-supply = <&vreg_bob>; +- +- vreg_l2a_3p1: ldo2 { +- regulator-name = "vreg_l2a_3p1"; +- regulator-min-microvolt = <3072000>; +- regulator-max-microvolt = <3072000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3a_0p9: ldo3 { +- regulator-name = "vreg_l3a_0p9"; +- regulator-min-microvolt = <928000>; +- regulator-max-microvolt = <932000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5a_0p88: ldo5 { +- regulator-name = "vreg_l5a_0p88"; +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6a_1p2: ldo6 { +- regulator-name = "vreg_l6a_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7a_1p7: ldo7 { +- regulator-name = "vreg_l7a_1p7"; +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l9a_1p2: ldo9 { +- regulator-name = "vreg_l9a_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10a_1p8: ldo10 { +- regulator-name = "vreg_l10a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l12a_1p8: ldo12 { +- regulator-name = "vreg_l12a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l13a_ts_3p0: ldo13 { +- regulator-name = "vreg_l13a_ts_3p0"; +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l14a_1p8: ldo14 { +- regulator-name = "vreg_l14a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1880000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l15a_1p8: ldo15 { +- regulator-name = "vreg_l15a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l16a_2p7: ldo16 { +- regulator-name = "vreg_l16a_2p7"; +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l17a_3p0: ldo17 { +- regulator-name = "vreg_l17a_3p0"; +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l18a_0p92: ldo18 { +- regulator-name = "vreg_l18a_0p92"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <912000>; +- regulator-initial-mode = ; +- }; +- +- vreg_s5a_1p9: smps5 { +- regulator-name = "vreg_s5a_1p9"; +- regulator-min-microvolt = <1904000>; +- regulator-max-microvolt = <2000000>; +- regulator-initial-mode = ; +- }; +- +- vreg_s6a_0p95: smps6 { +- regulator-name = "vreg_s6a_0p95"; +- regulator-min-microvolt = <920000>; +- regulator-max-microvolt = <1128000>; +- regulator-initial-mode = ; +- }; +- }; +- +- pm8150l-rpmh-regulators { +- compatible = "qcom,pm8150l-rpmh-regulators"; +- qcom,pmic-id = "c"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- vdd-l1-l8-supply = <&vreg_s4a_1p8>; +- vdd-l2-l3-supply = <&vreg_s8c_1p3>; +- vdd-l4-l5-l6-supply = <&vreg_bob>; +- vdd-l7-l11-supply = <&vreg_bob>; +- vdd-l9-l10-supply = <&vreg_bob>; +- vdd-bob-supply = <&vph_pwr>; +- +- vreg_bob: bob { +- regulator-name = "vreg_bob"; +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <4000000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l1c_1p8: ldo1 { +- regulator-name = "vreg_l1c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l2c_1p2: ldo2 { +- regulator-name = "vreg_l2c_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3c_0p8: ldo3 { +- regulator-name = "vreg_l3c_0p8"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l4c_1p7: ldo4 { +- regulator-name = "vreg_l4c_1p7"; +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5c_1p8: ldo5 { +- regulator-name = "vreg_l5c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6c_2p96: ldo6 { +- regulator-name = "vreg_l6c_2p96"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7c_cam_vcm0_2p85: ldo7 { +- regulator-name = "vreg_l7c_cam_vcm0_2p85"; +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <3104000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l8c_1p8: ldo8 { +- regulator-name = "vreg_l8c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l9c_2p96: ldo9 { +- regulator-name = "vreg_l9c_2p96"; +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10c_3p0: ldo10 { +- regulator-name = "vreg_l10c_3p0"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l11c_3p3: ldo11 { +- regulator-name = "vreg_l11c_3p3"; +- regulator-min-microvolt = <3296000>; +- regulator-max-microvolt = <3296000>; +- regulator-initial-mode = ; +- regulator-always-on; +- }; +- +- vreg_s8c_1p3: smps8 { +- regulator-name = "vreg_s8c_1p3"; +- regulator-min-microvolt = <1352000>; +- regulator-max-microvolt = <1352000>; +- regulator-initial-mode = ; +- }; +- }; +-}; +- +-&cdsp { +- status = "okay"; +- firmware-name = "qcom/sm8250/cdsp.mbn"; +-}; +- +-&dsi0 { +- status = "okay"; +- vdda-supply = <&vreg_l9a_1p2>; +- +-#if 0 +- qcom,dual-dsi-mode; +- qcom,master-dsi; +-#endif +- +- ports { +- port@1 { +- endpoint { +- remote-endpoint = <<9611_a>; +- data-lanes = <0 1 2 3>; +- }; +- }; +- }; +-}; +- +-&dsi0_phy { +- status = "okay"; +- vdds-supply = <&vreg_l5a_0p88>; +-}; +- +-&gmu { +- status = "okay"; +-}; +- +-&gpu { +- status = "okay"; +- +- zap-shader { +- memory-region = <&gpu_mem>; +- firmware-name = "qcom/sm8250/a650_zap.mbn"; +- }; +-}; +- +-/* LS-I2C0 */ +-&i2c4 { +- status = "okay"; +-}; +- +-&i2c5 { +- status = "okay"; +- clock-frequency = <400000>; +- +- lt9611_codec: hdmi-bridge@2b { +- compatible = "lontium,lt9611uxc"; +- reg = <0x2b>; +- #sound-dai-cells = <1>; +- +- interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_FALLING>; +- +- reset-gpios = <&pm8150l_gpios 5 GPIO_ACTIVE_HIGH>; +- +- vdd-supply = <<9611_1v2>; +- vcc-supply = <<9611_3v3>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- lt9611_a: endpoint { +- remote-endpoint = <&dsi0_out>; +- }; +- }; +- +-#if 0 +- port@1 { +- reg = <1>; +- +- lt9611_b: endpoint { +- remote-endpoint = <&dsi1_out>; +- }; +- }; +-#endif +- +- port@2 { +- reg = <2>; +- +- lt9611_out: endpoint { +- remote-endpoint = <&hdmi_con>; +- }; +- }; +- +- }; +- }; +-}; +- +-/* LS-I2C1 */ +-&i2c15 { +- status = "okay"; +-}; +- +-&mdss { +- status = "okay"; +-}; +- +-&mdss_mdp { +- status = "okay"; +-}; +- +-&pm8150_adc { +- xo-therm@4c { +- reg = ; +- qcom,ratiometric; +- qcom,hw-settle-time = <200>; +- }; +- +- wifi-therm@4e { +- reg = ; +- qcom,ratiometric; +- qcom,hw-settle-time = <200>; +- }; +-}; +- +-&pm8150_adc_tm { +- status = "okay"; +- +- xo-therm@0 { +- reg = <0>; +- io-channels = <&pm8150_adc ADC5_XO_THERM_100K_PU>; +- qcom,ratiometric; +- qcom,hw-settle-time-us = <200>; +- }; +- +- wifi-therm@1 { +- reg = <1>; +- io-channels = <&pm8150_adc ADC5_AMUX_THM2_100K_PU>; +- qcom,ratiometric; +- qcom,hw-settle-time-us = <200>; +- }; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie0_phy { +- status = "okay"; +- vdda-phy-supply = <&vreg_l5a_0p88>; +- vdda-pll-supply = <&vreg_l9a_1p2>; +-}; +- +-&pcie1 { +- status = "okay"; +-}; +- +-&pcie1_phy { +- status = "okay"; +- vdda-phy-supply = <&vreg_l5a_0p88>; +- vdda-pll-supply = <&vreg_l9a_1p2>; +-}; +- +-&pcie2 { +- status = "okay"; +-}; +- +-&pcie2_phy { +- status = "okay"; +- vdda-phy-supply = <&vreg_l5a_0p88>; +- vdda-pll-supply = <&vreg_l9a_1p2>; +-}; +- +-&pm8150_gpios { +- gpio-reserved-ranges = <1 1>, <3 2>, <7 1>; +- gpio-line-names = +- "NC", +- "OPTION2", +- "PM_GPIO-F", +- "PM_SLP_CLK_IN", +- "OPTION1", +- "VOL_UP_N", +- "PM8250_GPIO7", /* Blue LED */ +- "SP_ARI_PWR_ALARM", +- "GPIO_9_P", /* Yellow LED */ +- "GPIO_10_P"; /* Green LED */ +-}; +- +-&pm8150b_adc { +- conn-therm@4f { +- reg = ; +- qcom,ratiometric; +- qcom,hw-settle-time = <200>; +- }; +-}; +- +-&pm8150b_adc_tm { +- status = "okay"; +- +- conn-therm@0 { +- reg = <0>; +- io-channels = <&pm8150b_adc ADC5_AMUX_THM3_100K_PU>; +- qcom,ratiometric; +- qcom,hw-settle-time-us = <200>; +- }; +-}; +- +-&pm8150b_gpios { +- gpio-line-names = +- "NC", +- "NC", +- "NC", +- "NC", +- "HAP_BOOST_EN", /* SOM */ +- "SMB_STAT", /* SOM */ +- "NC", +- "NC", +- "SDM_FORCE_USB_BOOT", +- "NC", +- "NC", +- "NC"; +-}; +- +-&pm8150l_adc { +- skin-msm-therm@4e { +- reg = ; +- qcom,ratiometric; +- qcom,hw-settle-time = <200>; +- }; +- +- pm8150l-therm@4f { +- reg = ; +- qcom,ratiometric; +- qcom,hw-settle-time = <200>; +- }; +-}; +- +-&pm8150l_adc_tm { +- status = "okay"; +- +- skin-msm-therm@0 { +- reg = <0>; +- io-channels = <&pm8150l_adc ADC5_AMUX_THM2_100K_PU>; +- qcom,ratiometric; +- qcom,hw-settle-time-us = <200>; +- }; +- +- pm8150l-therm@1 { +- reg = <1>; +- io-channels = <&pm8150l_adc ADC5_AMUX_THM3_100K_PU>; +- qcom,ratiometric; +- qcom,hw-settle-time-us = <200>; +- }; +-}; +- +-&pm8150l_gpios { +- gpio-line-names = +- "NC", +- "PM3003A_EN", +- "NC", +- "NC", +- "PM_GPIO5", /* HDMI RST_N */ +- "PM_GPIO-A", /* PWM */ +- "PM_GPIO7", +- "NC", +- "NC", +- "PM_GPIO-B", +- "NC", +- "PM3003A_MODE"; +- +- lt9611_rst_pin: lt9611-rst-pin { +- pins = "gpio5"; +- function = "normal"; +- +- output-high; +- input-disable; +- power-source = <0>; +- }; +-}; +- +-&pon_pwrkey { +- status = "okay"; +-}; +- +-&pon_resin { +- status = "okay"; +- +- linux,code = ; +-}; +- +-&qupv3_id_0 { +- status = "okay"; +-}; +- +-&qupv3_id_1 { +- status = "okay"; +-}; +- +-&qupv3_id_2 { +- status = "okay"; +-}; +- +-&q6afedai { +- qi2s@16 { +- reg = <16>; +- qcom,sd-lines = <0 1 2 3>; +- }; +-}; +- +-/* TERT I2S Uses 1 I2S SD Lines for audio on LT9611 HDMI Bridge */ +-&q6afedai { +- qi2s@20 { +- reg = <20>; +- qcom,sd-lines = <0>; +- }; +-}; +- +-&q6asmdai { +- dai@0 { +- reg = <0>; +- }; +- +- dai@1 { +- reg = <1>; +- }; +- +- dai@2 { +- reg = <2>; +- }; +-}; +- +-&sdhc_2 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; +- vmmc-supply = <&vreg_l9c_2p96>; +- vqmmc-supply = <&vreg_l6c_2p96>; +- cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- no-sdio; +- no-emmc; +-}; +- +-&sound { +- compatible = "qcom,qrb5165-rb5-sndcard"; +- pinctrl-0 = <&tert_mi2s_active>; +- pinctrl-names = "default"; +- model = "Qualcomm-RB5-WSA8815-Speakers-DMIC0"; +- audio-routing = +- "SpkrLeft IN", "WSA_SPK1 OUT", +- "SpkrRight IN", "WSA_SPK2 OUT", +- "VA DMIC0", "vdd-micb", +- "VA DMIC1", "vdd-micb", +- "MM_DL1", "MultiMedia1 Playback", +- "MM_DL2", "MultiMedia2 Playback", +- "MultiMedia3 Capture", "MM_UL3"; +- +- mm1-dai-link { +- link-name = "MultiMedia1"; +- cpu { +- sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; +- }; +- }; +- +- mm2-dai-link { +- link-name = "MultiMedia2"; +- cpu { +- sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; +- }; +- }; +- +- mm3-dai-link { +- link-name = "MultiMedia3"; +- cpu { +- sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; +- }; +- }; +- +- hdmi-dai-link { +- link-name = "HDMI Playback"; +- cpu { +- sound-dai = <&q6afedai TERTIARY_MI2S_RX>; +- }; +- +- platform { +- sound-dai = <&q6routing>; +- }; +- +- codec { +- sound-dai = <<9611_codec 0>; +- }; +- }; +- +- dma-dai-link { +- link-name = "WSA Playback"; +- cpu { +- sound-dai = <&q6afedai WSA_CODEC_DMA_RX_0>; +- }; +- +- platform { +- sound-dai = <&q6routing>; +- }; +- +- codec { +- sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&wsamacro 0>; +- }; +- }; +- +- va-dai-link { +- link-name = "VA Capture"; +- cpu { +- sound-dai = <&q6afedai VA_CODEC_DMA_TX_0>; +- }; +- +- platform { +- sound-dai = <&q6routing>; +- }; +- +- codec { +- sound-dai = <&vamacro 0>; +- }; +- }; +-}; +- +-/* CAN */ +-&spi0 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs_gpio>; +- cs-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; +- +- can@0 { +- compatible = "microchip,mcp2518fd"; +- reg = <0>; +- clocks = <&clk40M>; +- interrupts-extended = <&tlmm 15 IRQ_TYPE_LEVEL_LOW>; +- spi-max-frequency = <10000000>; +- vdd-supply = <&vdc_5v>; +- xceiver-supply = <&vdc_5v>; +- }; +-}; +- +-&swr0 { +- left_spkr: wsa8810-left{ +- compatible = "sdw10217211000"; +- reg = <0 3>; +- powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>; +- #thermal-sensor-cells = <0>; +- sound-name-prefix = "SpkrLeft"; +- #sound-dai-cells = <0>; +- }; +- +- right_spkr: wsa8810-right{ +- compatible = "sdw10217211000"; +- reg = <0 4>; +- powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>; +- #thermal-sensor-cells = <0>; +- sound-name-prefix = "SpkrRight"; +- #sound-dai-cells = <0>; +- }; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <40 4>; +- gpio-line-names = +- "GPIO-MM", +- "GPIO-NN", +- "GPIO-OO", +- "GPIO-PP", +- "GPIO-A", +- "GPIO-C", +- "GPIO-E", +- "GPIO-D", +- "I2C0-SDA", +- "I2C0-SCL", +- "GPIO-TT", /* GPIO_10 */ +- "NC", +- "GPIO_12_I2C_SDA", +- "GPIO_13_I2C_SCL", +- "GPIO-X", +- "GPIO_15_RGMII_INT", +- "HST_BT_UART_CTS", +- "HST_BT_UART_RFR", +- "HST_BT_UART_TX", +- "HST_BT_UART_RX", +- "HST_WLAN_EN", /* GPIO_20 */ +- "HST_BT_EN", +- "GPIO-AAA", +- "GPIO-BBB", +- "GPIO-CCC", +- "GPIO-Z", +- "GPIO-DDD", +- "GPIO-BB", +- "GPIO_28_CAN_SPI_MISO", +- "GPIO_29_CAN_SPI_MOSI", +- "GPIO_30_CAN_SPI_CLK", /* GPIO_30 */ +- "GPIO_31_CAN_SPI_CS", +- "GPIO-UU", +- "NC", +- "UART1_TXD_SOM", +- "UART1_RXD_SOM", +- "UART0_CTS", +- "UART0_RTS", +- "UART0_TXD", +- "UART0_RXD", +- "SPI1_MISO", /* GPIO_40 */ +- "SPI1_MOSI", +- "SPI1_CLK", +- "SPI1_CS", +- "I2C1_SDA", +- "I2C1_SCL", +- "GPIO-F", +- "GPIO-JJ", +- "Board_ID1", +- "Board_ID2", +- "NC", /* GPIO_50 */ +- "NC", +- "SPI0_MISO", +- "SPI0_MOSI", +- "SPI0_SCLK", +- "SPI0_CS", +- "GPIO-QQ", +- "GPIO-RR", +- "USB2LAN_RESET", +- "USB2LAN_EXTWAKE", +- "NC", /* GPIO_60 */ +- "NC", +- "NC", +- "LT9611_INT", +- "GPIO-AA", +- "USB_CC_DIR", +- "GPIO-G", +- "GPIO-LL", +- "USB_DP_HPD_1P8", +- "NC", +- "NC", /* GPIO_70 */ +- "SD_CMD", +- "SD_DAT3", +- "SD_SCLK", +- "SD_DAT2", +- "SD_DAT1", +- "SD_DAT0", /* BOOT_CFG3 */ +- "SD_UFS_CARD_DET_N", +- "GPIO-II", +- "PCIE0_RST_N", +- "PCIE0_CLK_REQ_N", /* GPIO_80 */ +- "PCIE0_WAKE_N", +- "GPIO-CC", +- "GPIO-DD", +- "GPIO-EE", +- "GPIO-FF", +- "GPIO-GG", +- "GPIO-HH", +- "GPIO-VV", +- "GPIO-WW", +- "NC", /* GPIO_90 */ +- "NC", +- "GPIO-K", +- "GPIO-I", +- "CSI0_MCLK", +- "CSI1_MCLK", +- "CSI2_MCLK", +- "CSI3_MCLK", +- "GPIO-AA", /* CSI4_MCLK */ +- "GPIO-BB", /* CSI5_MCLK */ +- "GPIO-KK", /* GPIO_100 */ +- "CCI_I2C_SDA0", +- "CCI_I2C_SCL0", +- "CCI_I2C_SDA1", +- "CCI_I2C_SCL1", +- "CCI_I2C_SDA2", +- "CCI_I2C_SCL2", +- "CCI_I2C_SDA3", +- "CCI_I2C_SCL3", +- "GPIO-L", +- "NC", /* GPIO_110 */ +- "NC", +- "ACCEL_INT", +- "GYRO_INT", +- "GPIO-J", +- "GPIO-YY", +- "GPIO-H", +- "GPIO-ZZ", +- "NC", +- "NC", +- "NC", /* GPIO_120 */ +- "NC", +- "MAG_INT", +- "MAG_DRDY_INT", +- "HST_SW_CTRL", +- "GPIO-M", +- "GPIO-N", +- "GPIO-O", +- "GPIO-P", +- "PS_INT", +- "WSA1_EN", /* GPIO_130 */ +- "USB_HUB_RESET", +- "SDM_FORCE_USB_BOOT", +- "I2S1_CLK_HDMI", +- "I2S1_DATA0_HDMI", +- "I2S1_WS_HDMI", +- "GPIO-B", +- "GPIO_137", /* To LT9611_I2S_MCLK_3V3 */ +- "PCM_CLK", +- "PCM_DI", +- "PCM_DO", /* GPIO_140 */ +- "PCM_FS", +- "HST_SLIM_CLK", +- "HST_SLIM_DATA", +- "GPIO-U", +- "GPIO-Y", +- "GPIO-R", +- "GPIO-Q", +- "GPIO-S", +- "GPIO-T", +- "GPIO-V", /* GPIO_150 */ +- "GPIO-W", +- "DMIC_CLK1", +- "DMIC_DATA1", +- "DMIC_CLK2", +- "DMIC_DATA2", +- "WSA_SWR_CLK", +- "WSA_SWR_DATA", +- "DMIC_CLK3", +- "DMIC_DATA3", +- "I2C4_SDA", /* GPIO_160 */ +- "I2C4_SCL", +- "SPI3_CS1", +- "SPI3_CS2", +- "SPI2_MISO_LS3", +- "SPI2_MOSI_LS3", +- "SPI2_CLK_LS3", +- "SPI2_ACCEL_CS_LS3", +- "SPI2_CS1", +- "NC", +- "GPIO-SS", /* GPIO_170 */ +- "GPIO-XX", +- "SPI3_MISO", +- "SPI3_MOSI", +- "SPI3_CLK", +- "SPI3_CS", +- "HST_BLE_SNS_UART_TX", +- "HST_BLE_SNS_UART_RX", +- "HST_WLAN_UART_TX", +- "HST_WLAN_UART_RX"; +- +- lt9611_irq_pin: lt9611-irq { +- pins = "gpio63"; +- function = "gpio"; +- bias-disable; +- }; +- +- sdc2_default_state: sdc2-default { +- clk { +- pins = "sdc2_clk"; +- bias-disable; +- drive-strength = <16>; +- }; +- +- cmd { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- data { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- }; +- +- sdc2_card_det_n: sd-card-det-n { +- pins = "gpio77"; +- function = "gpio"; +- bias-pull-up; +- }; +-}; +- +-&uart12 { +- status = "okay"; +-}; +- +-&ufs_mem_hc { +- status = "okay"; +- +- vcc-supply = <&vreg_l17a_3p0>; +- vcc-max-microamp = <800000>; +- vccq-supply = <&vreg_l6a_1p2>; +- vccq-max-microamp = <800000>; +- vccq2-supply = <&vreg_s4a_1p8>; +- vccq2-max-microamp = <800000>; +-}; +- +-&ufs_mem_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l5a_0p88>; +- vdda-max-microamp = <89900>; +- vdda-pll-supply = <&vreg_l9a_1p2>; +- vdda-pll-max-microamp = <18800>; +-}; +- +-&usb_1 { +- status = "okay"; +-}; +- +-&usb_1_dwc3 { +- dr_mode = "peripheral"; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- +- vdda-pll-supply = <&vreg_l5a_0p88>; +- vdda33-supply = <&vreg_l2a_3p1>; +- vdda18-supply = <&vreg_l12a_1p8>; +-}; +- +-&usb_1_qmpphy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l9a_1p2>; +- vdda-pll-supply = <&vreg_l18a_0p92>; +-}; +- +-&usb_2 { +- status = "okay"; +-}; +- +-&usb_2_dwc3 { +- dr_mode = "host"; +-}; +- +-&usb_2_hsphy { +- status = "okay"; +- +- vdda-pll-supply = <&vreg_l5a_0p88>; +- vdda33-supply = <&vreg_l2a_3p1>; +- vdda18-supply = <&vreg_l12a_1p8>; +-}; +- +-&usb_2_qmpphy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l9a_1p2>; +- vdda-pll-supply = <&vreg_l18a_0p92>; +-}; +- +-&vamacro { +- pinctrl-0 = <&dmic01_active>; +- pinctrl-names = "default"; +- vdd-micb-supply = <&vreg_s4a_1p8>; +- qcom,dmic-sample-rate = <600000>; +-}; +- +-&venus { +- status = "okay"; +-}; +- +-/* PINCTRL - additions to nodes defined in sm8250.dtsi */ +-&qup_spi0_cs_gpio { +- drive-strength = <6>; +- bias-disable; +-}; +- +-&qup_spi0_data_clk { +- drive-strength = <6>; +- bias-disable; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sa8155p-adp.dts b/scripts/dtc/include-prefixes/arm64/qcom/sa8155p-adp.dts +deleted file mode 100644 +index 5ae2ddc65f7e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sa8155p-adp.dts ++++ /dev/null +@@ -1,402 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Linaro Limited +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "sm8150.dtsi" +-#include "pmm8155au_1.dtsi" +-#include "pmm8155au_2.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. SA8155P ADP"; +- compatible = "qcom,sa8155p-adp", "qcom,sa8155p"; +- +- aliases { +- serial0 = &uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- vreg_3p3: vreg_3p3_regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_3p3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- /* +- * S4A is always on and not controllable through RPMh. +- * So model it as a fixed regulator. +- */ +- vreg_s4a_1p8: smps4 { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_s4a_1p8"; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-always-on; +- regulator-boot-on; +- regulator-allow-set-load; +- +- vin-supply = <&vreg_3p3>; +- }; +-}; +- +-&apps_rsc { +- pmm8155au-1-rpmh-regulators { +- compatible = "qcom,pmm8155au-rpmh-regulators"; +- qcom,pmic-id = "a"; +- +- vdd-s1-supply = <&vreg_3p3>; +- vdd-s2-supply = <&vreg_3p3>; +- vdd-s3-supply = <&vreg_3p3>; +- vdd-s4-supply = <&vreg_3p3>; +- vdd-s5-supply = <&vreg_3p3>; +- vdd-s6-supply = <&vreg_3p3>; +- vdd-s7-supply = <&vreg_3p3>; +- vdd-s8-supply = <&vreg_3p3>; +- vdd-s9-supply = <&vreg_3p3>; +- vdd-s10-supply = <&vreg_3p3>; +- +- vdd-l1-l8-l11-supply = <&vreg_s6a_0p92>; +- vdd-l2-l10-supply = <&vreg_3p3>; +- vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p92>; +- vdd-l6-l9-supply = <&vreg_s6a_0p92>; +- vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; +- vdd-l13-l16-l17-supply = <&vreg_3p3>; +- +- vreg_s5a_2p04: smps5 { +- regulator-name = "vreg_s5a_2p04"; +- regulator-min-microvolt = <1904000>; +- regulator-max-microvolt = <2000000>; +- }; +- +- vreg_s6a_0p92: smps6 { +- regulator-name = "vreg_s6a_0p92"; +- regulator-min-microvolt = <920000>; +- regulator-max-microvolt = <1128000>; +- }; +- +- vreg_l1a_0p752: ldo1 { +- regulator-name = "vreg_l1a_0p752"; +- regulator-min-microvolt = <752000>; +- regulator-max-microvolt = <752000>; +- regulator-initial-mode = ; +- }; +- +- vdda_usb_hs_3p1: +- vreg_l2a_3p072: ldo2 { +- regulator-name = "vreg_l2a_3p072"; +- regulator-min-microvolt = <3072000>; +- regulator-max-microvolt = <3072000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3a_0p8: ldo3 { +- regulator-name = "vreg_l3a_0p8"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vdd_usb_hs_core: +- vdda_usb_ss_dp_core_1: +- vreg_l5a_0p88: ldo5 { +- regulator-name = "vreg_l5a_0p88"; +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-initial-mode = ; +- regulator-allow-set-load; +- }; +- +- vreg_l7a_1p8: ldo7 { +- regulator-name = "vreg_l7a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10a_2p96: ldo10 { +- regulator-name = "vreg_l10a_2p96"; +- regulator-min-microvolt = <2504000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- regulator-allow-set-load; +- }; +- +- vreg_l11a_0p8: ldo11 { +- regulator-name = "vreg_l11a_0p8"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vdda_usb_hs_1p8: +- vreg_l12a_1p8: ldo12 { +- regulator-name = "vreg_l12a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l13a_2p7: ldo13 { +- regulator-name = "vreg_l13a_2p7"; +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2704000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l15a_1p7: ldo15 { +- regulator-name = "vreg_l15a_1p7"; +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <1704000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l16a_2p7: ldo16 { +- regulator-name = "vreg_l16a_2p7"; +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l17a_2p96: ldo17 { +- regulator-name = "vreg_l17a_2p96"; +- regulator-min-microvolt = <2504000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- }; +- +- pmm8155au-2-rpmh-regulators { +- compatible = "qcom,pmm8155au-rpmh-regulators"; +- qcom,pmic-id = "c"; +- +- vdd-s1-supply = <&vreg_3p3>; +- vdd-s2-supply = <&vreg_3p3>; +- vdd-s3-supply = <&vreg_3p3>; +- vdd-s4-supply = <&vreg_3p3>; +- vdd-s5-supply = <&vreg_3p3>; +- vdd-s6-supply = <&vreg_3p3>; +- vdd-s7-supply = <&vreg_3p3>; +- vdd-s8-supply = <&vreg_3p3>; +- vdd-s9-supply = <&vreg_3p3>; +- vdd-s10-supply = <&vreg_3p3>; +- +- vdd-l1-l8-l11-supply = <&vreg_s4c_1p352>; +- vdd-l2-l10-supply = <&vreg_3p3>; +- vdd-l3-l4-l5-l18-supply = <&vreg_s4c_1p352>; +- vdd-l6-l9-supply = <&vreg_s6c_1p128>; +- vdd-l7-l12-l14-l15-supply = <&vreg_s5c_2p04>; +- vdd-l13-l16-l17-supply = <&vreg_3p3>; +- +- vreg_s4c_1p352: smps4 { +- regulator-name = "vreg_s4c_1p352"; +- regulator-min-microvolt = <1352000>; +- regulator-max-microvolt = <1352000>; +- }; +- +- vreg_s5c_2p04: smps5 { +- regulator-name = "vreg_s5c_2p04"; +- regulator-min-microvolt = <1904000>; +- regulator-max-microvolt = <2000000>; +- }; +- +- vreg_s6c_1p128: smps6 { +- regulator-name = "vreg_s6c_1p128"; +- regulator-min-microvolt = <1128000>; +- regulator-max-microvolt = <1128000>; +- }; +- +- vreg_l1c_1p304: ldo1 { +- regulator-name = "vreg_l1c_1p304"; +- regulator-min-microvolt = <1304000>; +- regulator-max-microvolt = <1304000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l2c_1p808: ldo2 { +- regulator-name = "vreg_l2c_1p808"; +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5c_1p2: ldo5 { +- regulator-name = "vreg_l5c_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- regulator-allow-set-load; +- }; +- +- vreg_l7c_1p8: ldo7 { +- regulator-name = "vreg_l7c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l8c_1p2: ldo8 { +- regulator-name = "vreg_l8c_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- regulator-allow-set-load; +- }; +- +- vreg_l10c_3p3: ldo10 { +- regulator-name = "vreg_l10c_3p3"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l11c_0p8: ldo11 { +- regulator-name = "vreg_l11c_0p8"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l12c_1p808: ldo12 { +- regulator-name = "vreg_l12c_1p808"; +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l13c_2p96: ldo13 { +- regulator-name = "vreg_l13c_2p96"; +- regulator-min-microvolt = <2504000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l15c_1p9: ldo15 { +- regulator-name = "vreg_l15c_1p9"; +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l16c_3p008: ldo16 { +- regulator-name = "vreg_l16c_3p008"; +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l18c_0p88: ldo18 { +- regulator-name = "vreg_l18c_0p88"; +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-initial-mode = ; +- }; +- }; +-}; +- +-&qupv3_id_1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&ufs_mem_hc { +- status = "okay"; +- +- reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; +- +- vcc-supply = <&vreg_l10a_2p96>; +- vcc-max-microamp = <750000>; +- vccq-supply = <&vreg_l5c_1p2>; +- vccq-max-microamp = <700000>; +- vccq2-supply = <&vreg_s4a_1p8>; +- vccq2-max-microamp = <750000>; +-}; +- +-&ufs_mem_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l8c_1p2>; +- vdda-max-microamp = <87100>; +- vdda-pll-supply = <&vreg_l5a_0p88>; +- vdda-pll-max-microamp = <18300>; +-}; +- +-&usb_1 { +- status = "okay"; +-}; +- +-&usb_1_dwc3 { +- dr_mode = "host"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&usb2phy_ac_en1_default>; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- vdda-pll-supply = <&vdd_usb_hs_core>; +- vdda33-supply = <&vdda_usb_hs_3p1>; +- vdda18-supply = <&vdda_usb_hs_1p8>; +-}; +- +-&usb_1_qmpphy { +- status = "disabled"; +-}; +- +-&usb_2 { +- status = "okay"; +-}; +- +-&usb_2_dwc3 { +- dr_mode = "host"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&usb2phy_ac_en2_default>; +-}; +- +-&usb_2_hsphy { +- status = "okay"; +- vdda-pll-supply = <&vdd_usb_hs_core>; +- vdda33-supply = <&vdda_usb_hs_3p1>; +- vdda18-supply = <&vdda_usb_hs_1p8>; +-}; +- +-&usb_2_qmpphy { +- status = "okay"; +- vdda-phy-supply = <&vreg_l8c_1p2>; +- vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <0 4>; +- +- usb2phy_ac_en1_default: usb2phy_ac_en1_default { +- mux { +- pins = "gpio113"; +- function = "usb2phy_ac"; +- bias-disable; +- drive-strength = <2>; +- }; +- }; +- +- usb2phy_ac_en2_default: usb2phy_ac_en2_default { +- mux { +- pins = "gpio123"; +- function = "usb2phy_ac"; +- bias-disable; +- drive-strength = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-idp.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-idp.dts +deleted file mode 100644 +index acdb36f4479f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-idp.dts ++++ /dev/null +@@ -1,768 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * SC7180 IDP board device tree source +- * +- * Copyright (c) 2019, The Linux Foundation. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include "sc7180.dtsi" +-#include "pm6150.dtsi" +-#include "pm6150l.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. SC7180 IDP"; +- compatible = "qcom,sc7180-idp", "qcom,sc7180"; +- +- aliases { +- bluetooth0 = &bluetooth; +- hsuart0 = &uart3; +- serial0 = &uart8; +- wifi0 = &wifi; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-/* +- * Reserved memory changes +- * +- * Delete all unused memory nodes and define the peripheral memory regions +- * required by the board dts. +- * +- */ +- +-/delete-node/ &hyp_mem; +-/delete-node/ &xbl_mem; +-/delete-node/ &aop_mem; +-/delete-node/ &sec_apps_mem; +-/delete-node/ &tz_mem; +- +-/* Increase the size from 2MB to 8MB */ +-&rmtfs_mem { +- reg = <0x0 0x94600000 0x0 0x800000>; +-}; +- +-/ { +- reserved-memory { +- atf_mem: memory@80b00000 { +- reg = <0x0 0x80b00000 0x0 0x100000>; +- no-map; +- }; +- +- mpss_mem: memory@86000000 { +- reg = <0x0 0x86000000 0x0 0x8c00000>; +- no-map; +- }; +- +- camera_mem: memory@8ec00000 { +- reg = <0x0 0x8ec00000 0x0 0x500000>; +- no-map; +- }; +- +- venus_mem: memory@8f600000 { +- reg = <0 0x8f600000 0 0x500000>; +- no-map; +- }; +- +- wlan_mem: memory@94100000 { +- reg = <0x0 0x94100000 0x0 0x200000>; +- no-map; +- }; +- +- mba_mem: memory@94400000 { +- reg = <0x0 0x94400000 0x0 0x200000>; +- no-map; +- }; +- }; +-}; +- +-&apps_rsc { +- pm6150-rpmh-regulators { +- compatible = "qcom,pm6150-rpmh-regulators"; +- qcom,pmic-id = "a"; +- +- vreg_s1a_1p1: smps1 { +- regulator-min-microvolt = <1128000>; +- regulator-max-microvolt = <1128000>; +- }; +- +- vreg_s4a_1p0: smps4 { +- regulator-min-microvolt = <824000>; +- regulator-max-microvolt = <1120000>; +- }; +- +- vreg_s5a_2p0: smps5 { +- regulator-min-microvolt = <1744000>; +- regulator-max-microvolt = <2040000>; +- }; +- +- vreg_l1a_1p2: ldo1 { +- regulator-min-microvolt = <1178000>; +- regulator-max-microvolt = <1256000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l2a_1p0: ldo2 { +- regulator-min-microvolt = <944000>; +- regulator-max-microvolt = <1056000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3a_1p0: ldo3 { +- regulator-min-microvolt = <968000>; +- regulator-max-microvolt = <1064000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l4a_0p8: ldo4 { +- regulator-min-microvolt = <824000>; +- regulator-max-microvolt = <928000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5a_2p7: ldo5 { +- regulator-min-microvolt = <2496000>; +- regulator-max-microvolt = <3000000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6a_0p6: ldo6 { +- regulator-min-microvolt = <568000>; +- regulator-max-microvolt = <648000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l9a_0p6: ldo9 { +- regulator-min-microvolt = <488000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10a_1p8: ldo10 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1832000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l11a_1p8: ldo11 { +- regulator-min-microvolt = <1696000>; +- regulator-max-microvolt = <1904000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l12a_1p8: ldo12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l13a_1p8: ldo13 { +- regulator-min-microvolt = <1696000>; +- regulator-max-microvolt = <1904000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l14a_1p8: ldo14 { +- regulator-min-microvolt = <1728000>; +- regulator-max-microvolt = <1832000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l15a_1p8: ldo15 { +- regulator-min-microvolt = <1696000>; +- regulator-max-microvolt = <1904000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l16a_2p7: ldo16 { +- regulator-min-microvolt = <2496000>; +- regulator-max-microvolt = <3304000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l17a_3p0: ldo17 { +- regulator-min-microvolt = <2920000>; +- regulator-max-microvolt = <3232000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l18a_2p8: ldo18 { +- regulator-min-microvolt = <2496000>; +- regulator-max-microvolt = <3304000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l19a_2p9: ldo19 { +- regulator-min-microvolt = <2960000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- }; +- +- pm6150l-rpmh-regulators { +- compatible = "qcom,pm6150l-rpmh-regulators"; +- qcom,pmic-id = "c"; +- +- vreg_s8c_1p3: smps8 { +- regulator-min-microvolt = <1120000>; +- regulator-max-microvolt = <1408000>; +- }; +- +- vreg_l1c_1p8: ldo1 { +- regulator-min-microvolt = <1616000>; +- regulator-max-microvolt = <1984000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l2c_1p3: ldo2 { +- regulator-min-microvolt = <1168000>; +- regulator-max-microvolt = <1304000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3c_1p2: ldo3 { +- regulator-min-microvolt = <1144000>; +- regulator-max-microvolt = <1304000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l4c_1p8: ldo4 { +- regulator-min-microvolt = <1648000>; +- regulator-max-microvolt = <3304000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5c_1p8: ldo5 { +- regulator-min-microvolt = <1648000>; +- regulator-max-microvolt = <3304000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6c_2p9: ldo6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7c_3p0: ldo7 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l8c_1p8: ldo8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1904000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l9c_2p9: ldo9 { +- regulator-min-microvolt = <2960000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10c_3p3: ldo10 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3400000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l11c_3p3: ldo11 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3400000>; +- regulator-initial-mode = ; +- }; +- +- vreg_bob: bob { +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3960000>; +- regulator-initial-mode = ; +- }; +- }; +-}; +- +-&dsi0 { +- status = "okay"; +- +- vdda-supply = <&vreg_l3c_1p2>; +- +- panel@0 { +- compatible = "visionox,rm69299-1080p-display"; +- reg = <0>; +- +- vdda-supply = <&vreg_l8c_1p8>; +- vdd3p3-supply = <&vreg_l18a_2p8>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&disp_pins>; +- +- reset-gpios = <&pm6150l_gpio 3 GPIO_ACTIVE_HIGH>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- panel0_in: endpoint { +- remote-endpoint = <&dsi0_out>; +- }; +- }; +- }; +- }; +- +- ports { +- port@1 { +- endpoint { +- remote-endpoint = <&panel0_in>; +- data-lanes = <0 1 2 3>; +- }; +- }; +- }; +-}; +- +-&dsi_phy { +- status = "okay"; +-}; +- +-&mdp { +- status = "okay"; +-}; +- +-&mdss { +- status = "okay"; +-}; +- +-&qfprom { +- vcc-supply = <&vreg_l11a_1p8>; +-}; +- +-&qspi { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <25000000>; +- spi-tx-bus-width = <2>; +- spi-rx-bus-width = <2>; +- }; +-}; +- +-&qupv3_id_0 { +- status = "okay"; +-}; +- +-&qupv3_id_1 { +- status = "okay"; +-}; +- +-&remoteproc_mpss { +- status = "okay"; +- compatible = "qcom,sc7180-mss-pil"; +- iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>; +- memory-region = <&mba_mem &mpss_mem>; +-}; +- +-&sdhc_1 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc1_on>; +- pinctrl-1 = <&sdc1_off>; +- vmmc-supply = <&vreg_l19a_2p9>; +- vqmmc-supply = <&vreg_l12a_1p8>; +-}; +- +-&sdhc_2 { +- status = "okay"; +- +- pinctrl-names = "default","sleep"; +- pinctrl-0 = <&sdc2_on>; +- pinctrl-1 = <&sdc2_off>; +- vmmc-supply = <&vreg_l9c_2p9>; +- vqmmc-supply = <&vreg_l6c_2p9>; +- +- cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>; +-}; +- +-&uart3 { +- status = "okay"; +- +- /delete-property/interrupts; +- interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, +- <&tlmm 41 IRQ_TYPE_EDGE_FALLING>; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-1 = <&qup_uart3_sleep>; +- +- bluetooth: wcn3990-bt { +- compatible = "qcom,wcn3990-bt"; +- vddio-supply = <&vreg_l10a_1p8>; +- vddxo-supply = <&vreg_l1c_1p8>; +- vddrf-supply = <&vreg_l2c_1p3>; +- vddch0-supply = <&vreg_l10c_3p3>; +- max-speed = <3200000>; +- }; +-}; +- +-&uart8 { +- status = "okay"; +-}; +- +-&usb_1 { +- status = "okay"; +-}; +- +-&usb_1_dwc3 { +- dr_mode = "host"; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- vdd-supply = <&vreg_l4a_0p8>; +- vdda-pll-supply = <&vreg_l11a_1p8>; +- vdda-phy-dpdm-supply = <&vreg_l17a_3p0>; +- qcom,imp-res-offset-value = <8>; +- qcom,preemphasis-level = ; +- qcom,preemphasis-width = ; +- qcom,bias-ctrl-value = <0x22>; +- qcom,charge-ctrl-value = <3>; +- qcom,hsdisc-trim-value = <0>; +-}; +- +-&usb_1_qmpphy { +- status = "okay"; +- vdda-phy-supply = <&vreg_l3c_1p2>; +- vdda-pll-supply = <&vreg_l4a_0p8>; +-}; +- +-&venus { +- video-firmware { +- iommus = <&apps_smmu 0x0c42 0x0>; +- }; +-}; +- +-&wifi { +- status = "okay"; +- vdd-0.8-cx-mx-supply = <&vreg_l9a_0p6>; +- vdd-1.8-xo-supply = <&vreg_l1c_1p8>; +- vdd-1.3-rfa-supply = <&vreg_l2c_1p3>; +- vdd-3.3-ch0-supply = <&vreg_l10c_3p3>; +- vdd-3.3-ch1-supply = <&vreg_l11c_3p3>; +- wifi-firmware { +- iommus = <&apps_smmu 0xc2 0x1>; +- }; +-}; +- +-/* PINCTRL - additions to nodes defined in sc7180.dtsi */ +- +-&pm6150l_gpio { +- disp_pins: disp-pins { +- pinconf { +- pins = "gpio3"; +- function = PMIC_GPIO_FUNC_FUNC1; +- qcom,drive-strength = ; +- power-source = <0>; +- bias-disable; +- output-low; +- }; +- }; +-}; +- +-&qspi_clk { +- pinconf { +- pins = "gpio63"; +- bias-disable; +- }; +-}; +- +-&qspi_cs0 { +- pinconf { +- pins = "gpio68"; +- bias-disable; +- }; +-}; +- +-&qspi_data01 { +- pinconf { +- pins = "gpio64", "gpio65"; +- +- /* High-Z when no transfers; nice to park the lines */ +- bias-pull-up; +- }; +-}; +- +-&qup_i2c2_default { +- pinconf { +- pins = "gpio15", "gpio16"; +- drive-strength = <2>; +- +- /* Has external pullup */ +- bias-disable; +- }; +-}; +- +-&qup_i2c4_default { +- pinconf { +- pins = "gpio115", "gpio116"; +- drive-strength = <2>; +- +- /* Has external pullup */ +- bias-disable; +- }; +-}; +- +-&qup_i2c7_default { +- pinconf { +- pins = "gpio6", "gpio7"; +- drive-strength = <2>; +- +- /* Has external pullup */ +- bias-disable; +- }; +-}; +- +-&qup_i2c9_default { +- pinconf { +- pins = "gpio46", "gpio47"; +- drive-strength = <2>; +- +- /* Has external pullup */ +- bias-disable; +- }; +-}; +- +-&qup_uart3_default { +- pinconf-cts { +- /* +- * Configure a pull-down on CTS to match the pull of +- * the Bluetooth module. +- */ +- pins = "gpio38"; +- bias-pull-down; +- }; +- +- pinconf-rts { +- /* We'll drive RTS, so no pull */ +- pins = "gpio39"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- pinconf-tx { +- /* We'll drive TX, so no pull */ +- pins = "gpio40"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- pinconf-rx { +- /* +- * Configure a pull-up on RX. This is needed to avoid +- * garbage data when the TX pin of the Bluetooth module is +- * in tri-state (module powered off or not driving the +- * signal yet). +- */ +- pins = "gpio41"; +- bias-pull-up; +- }; +-}; +- +-&qup_uart8_default { +- pinconf-tx { +- pins = "gpio44"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- pinconf-rx { +- pins = "gpio45"; +- drive-strength = <2>; +- bias-pull-up; +- }; +-}; +- +-&qup_spi0_default { +- pinconf { +- pins = "gpio34", "gpio35", "gpio36", "gpio37"; +- drive-strength = <2>; +- bias-disable; +- }; +-}; +- +-&qup_spi6_default { +- pinconf { +- pins = "gpio59", "gpio60", "gpio61", "gpio62"; +- drive-strength = <2>; +- bias-disable; +- }; +-}; +- +-&qup_spi10_default { +- pinconf { +- pins = "gpio86", "gpio87", "gpio88", "gpio89"; +- drive-strength = <2>; +- bias-disable; +- }; +-}; +- +-&tlmm { +- qup_uart3_sleep: qup-uart3-sleep { +- pinmux { +- pins = "gpio38", "gpio39", +- "gpio40", "gpio41"; +- function = "gpio"; +- }; +- +- pinconf-cts { +- /* +- * Configure a pull-down on CTS to match the pull of +- * the Bluetooth module. +- */ +- pins = "gpio38"; +- bias-pull-down; +- }; +- +- pinconf-rts { +- /* +- * Configure pull-down on RTS. As RTS is active low +- * signal, pull it low to indicate the BT SoC that it +- * can wakeup the system anytime from suspend state by +- * pulling RX low (by sending wakeup bytes). +- */ +- pins = "gpio39"; +- bias-pull-down; +- }; +- +- pinconf-tx { +- /* +- * Configure pull-up on TX when it isn't actively driven +- * to prevent BT SoC from receiving garbage during sleep. +- */ +- pins = "gpio40"; +- bias-pull-up; +- }; +- +- pinconf-rx { +- /* +- * Configure a pull-up on RX. This is needed to avoid +- * garbage data when the TX pin of the Bluetooth module +- * is floating which may cause spurious wakeups. +- */ +- pins = "gpio41"; +- bias-pull-up; +- }; +- }; +- +- sdc1_on: sdc1-on { +- pinconf-clk { +- pins = "sdc1_clk"; +- bias-disable; +- drive-strength = <16>; +- }; +- +- pinconf-cmd { +- pins = "sdc1_cmd"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- pinconf-data { +- pins = "sdc1_data"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- pinconf-rclk { +- pins = "sdc1_rclk"; +- bias-pull-down; +- }; +- }; +- +- sdc1_off: sdc1-off { +- pinconf-clk { +- pins = "sdc1_clk"; +- bias-disable; +- drive-strength = <2>; +- }; +- +- pinconf-cmd { +- pins = "sdc1_cmd"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- pinconf-data { +- pins = "sdc1_data"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- pinconf-rclk { +- pins = "sdc1_rclk"; +- bias-pull-down; +- }; +- }; +- +- sdc2_on: sdc2-on { +- pinconf-clk { +- pins = "sdc2_clk"; +- bias-disable; +- drive-strength = <16>; +- }; +- +- pinconf-cmd { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- pinconf-data { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- pinconf-sd-cd { +- pins = "gpio69"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +- +- sdc2_off: sdc2-off { +- pinconf-clk { +- pins = "sdc2_clk"; +- bias-disable; +- drive-strength = <2>; +- }; +- +- pinconf-cmd { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- pinconf-data { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- pinconf-sd-cd { +- pins = "gpio69"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-lite.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-lite.dtsi +deleted file mode 100644 +index d8ed1d7b4ec7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-lite.dtsi ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * SC7180 lite device tree source +- * +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-&cpu6_opp10 { +- opp-peak-kBps = <7216000 22425600>; +-}; +- +-&cpu6_opp11 { +- opp-peak-kBps = <7216000 22425600>; +-}; +- +-&cpu6_opp12 { +- opp-peak-kBps = <8532000 23347200>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-coachz-r1-lte.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-coachz-r1-lte.dts +deleted file mode 100644 +index 82dc00cc7fb9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-coachz-r1-lte.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google CoachZ board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-#include "sc7180-trogdor-coachz-r1.dts" +-#include "sc7180-trogdor-lte-sku.dtsi" +- +-/ { +- model = "Google CoachZ (rev1 - 2) with LTE"; +- compatible = "google,coachz-rev1-sku0", "google,coachz-rev2-sku0", "qcom,sc7180"; +-}; +- +-&cros_ec_proximity { +- label = "proximity-wifi-lte"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-coachz-r1.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-coachz-r1.dts +deleted file mode 100644 +index 21b516e0694a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-coachz-r1.dts ++++ /dev/null +@@ -1,159 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google CoachZ board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-/dts-v1/; +- +-#include "sc7180-trogdor-coachz.dtsi" +- +-/ { +- model = "Google CoachZ (rev1 - 2)"; +- compatible = "google,coachz-rev1", "google,coachz-rev2", "qcom,sc7180"; +-}; +- +-/* +- * CoachZ rev1 is stuffed with a 47k NTC as charger thermistor which currently +- * is not supported by the PM6150 ADC driver. Disable the charger thermal zone +- * to avoid using bogus temperature values. +- */ +-&charger_thermal { +- status = "disabled"; +-}; +- +-/* +- * CoachZ rev1 is stuffed with a 47k NTC as thermistor for skin temperature, +- * which currently is not supported by the PM6150 ADC driver. Disable the +- * skin temperature thermal zone to avoid using bogus temperature values. +- */ +-&skin_temp_thermal { +- status = "disabled"; +-}; +- +-&tlmm { +- gpio-line-names = "HUB_RST_L", +- "AP_RAM_ID0", +- "AP_SKU_ID2", +- "AP_RAM_ID1", +- "FP_TO_AP_IRQ_L", +- "AP_RAM_ID2", +- "UF_CAM_EN", +- "WF_CAM_EN", +- "TS_RESET_L", +- "TS_INT_L", +- "FPMCU_BOOT0", +- "EDP_BRIJ_IRQ", +- "AP_EDP_BKLTEN", +- "UF_CAM_MCLK", +- "WF_CAM_CLK", +- "EDP_BRIJ_I2C_SDA", +- "EDP_BRIJ_I2C_SCL", +- "UF_CAM_SDA", +- "UF_CAM_SCL", +- "WF_CAM_SDA", +- "WF_CAM_SCL", +- "WLC_IRQ", +- "FP_RST_L", +- "AMP_EN", +- "WLC_NRST", +- "AP_SAR_SENSOR_SDA", +- "AP_SAR_SENSOR_SCL", +- "", +- "", +- "WF_CAM_RST_L", +- "UF_CAM_RST_L", +- "AP_BRD_ID2", +- "BRIJ_SUSPEND", +- "AP_BRD_ID0", +- "AP_H1_SPI_MISO", +- "AP_H1_SPI_MOSI", +- "AP_H1_SPI_CLK", +- "AP_H1_SPI_CS_L", +- "", +- "", +- "", +- "", +- "H1_AP_INT_ODL", +- "", +- "UART_AP_TX_DBG_RX", +- "UART_DBG_TX_AP_RX", +- "", +- "", +- "FORCED_USB_BOOT", +- "AMP_BCLK", +- "AMP_LRCLK", +- "AMP_DIN", +- "EN_PP3300_DX_EDP", +- "HP_BCLK", +- "HP_LRCLK", +- "HP_DOUT", +- "HP_DIN", +- "HP_MCLK", +- "AP_SKU_ID0", +- "AP_EC_SPI_MISO", +- "AP_EC_SPI_MOSI", +- "AP_EC_SPI_CLK", +- "AP_EC_SPI_CS_L", +- "AP_SPI_CLK", +- "AP_SPI_MOSI", +- "AP_SPI_MISO", +- /* +- * AP_FLASH_WP_L is crossystem ABI. Schematics +- * call it BIOS_FLASH_WP_L. +- */ +- "AP_FLASH_WP_L", +- "", +- "AP_SPI_CS0_L", +- "SD_CD_ODL", +- "", +- "", +- "", +- "", +- "FPMCU_SEL", +- "UIM2_DATA", +- "UIM2_CLK", +- "UIM2_RST", +- "UIM2_PRESENT_L", +- "UIM1_DATA", +- "UIM1_CLK", +- "UIM1_RST", +- "", +- "DMIC_CLK_EN", +- "HUB_EN", +- "", +- "AP_SPI_FP_MISO", +- "AP_SPI_FP_MOSI", +- "AP_SPI_FP_CLK", +- "AP_SPI_FP_CS_L", +- "AP_SKU_ID1", +- "AP_RST_REQ", +- "", +- "AP_BRD_ID1", +- "AP_EC_INT_L", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "EDP_BRIJ_EN", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "AP_TS_PEN_I2C_SDA", +- "AP_TS_PEN_I2C_SCL", +- "DP_HOT_PLUG_DET", +- "EC_IN_RW_ODL"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-coachz-r3-lte.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-coachz-r3-lte.dts +deleted file mode 100644 +index d23409034e8c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-coachz-r3-lte.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google CoachZ board device tree source +- * +- * Copyright 2021 Google LLC. +- */ +- +-#include "sc7180-trogdor-coachz-r3.dts" +-#include "sc7180-trogdor-lte-sku.dtsi" +- +-/ { +- model = "Google CoachZ (rev3+) with LTE"; +- compatible = "google,coachz-sku0", "qcom,sc7180"; +-}; +- +-&cros_ec_proximity { +- label = "proximity-wifi-lte"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-coachz-r3.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-coachz-r3.dts +deleted file mode 100644 +index a02d2d57c78c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-coachz-r3.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google CoachZ board device tree source +- * +- * Copyright 2021 Google LLC. +- */ +- +-/dts-v1/; +- +-#include "sc7180-trogdor-coachz.dtsi" +- +-/ { +- model = "Google CoachZ (rev3+)"; +- compatible = "google,coachz", "qcom,sc7180"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-coachz.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-coachz.dtsi +deleted file mode 100644 +index 81098aa9687b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-coachz.dtsi ++++ /dev/null +@@ -1,330 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google CoachZ board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-#include "sc7180.dtsi" +- +-ap_ec_spi: &spi6 {}; +-ap_h1_spi: &spi0 {}; +- +-#include "sc7180-trogdor.dtsi" +- +-/* Deleted nodes from trogdor.dtsi */ +- +-/delete-node/ &alc5682; +-/delete-node/ &pp3300_codec; +- +-/ { +- /* BOARD-SPECIFIC TOP LEVEL NODES */ +- +- adau7002: audio-codec-1 { +- compatible = "adi,adau7002"; +- IOVDD-supply = <&pp1800_l15a>; +- wakeup-delay-ms = <80>; +- #sound-dai-cells = <0>; +- }; +- +- thermal-zones { +- skin_temp_thermal: skin-temp-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&pm6150_adc_tm 1>; +- sustainable-power = <965>; +- +- trips { +- skin_temp_alert0: trip-point0 { +- temperature = <42000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- +- skin_temp_alert1: trip-point1 { +- temperature = <45000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- +- skin-temp-crit { +- temperature = <60000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&skin_temp_alert0>; +- cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- +- map1 { +- trip = <&skin_temp_alert1>; +- cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +-}; +- +-&ap_spi_fp { +- status = "okay"; +-}; +- +-&backlight { +- pwms = <&cros_ec_pwm 0>; +-}; +- +-&camcc { +- status = "okay"; +-}; +- +-&cros_ec { +- cros_ec_proximity: proximity { +- compatible = "google,cros-ec-mkbp-proximity"; +- label = "proximity-wifi"; +- }; +-}; +- +-ap_ts_pen_1v8: &i2c4 { +- status = "okay"; +- clock-frequency = <400000>; +- +- ap_ts: touchscreen@5d { +- compatible = "goodix,gt7375p"; +- reg = <0x5d>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <9 IRQ_TYPE_LEVEL_LOW>; +- +- reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; +- +- vdd-supply = <&pp3300_ts>; +- }; +-}; +- +-&i2c7 { +- status = "disabled"; +-}; +- +-&i2c9 { +- status = "disabled"; +-}; +- +-&panel { +- compatible = "boe,nv110wtm-n61"; +-}; +- +-&pm6150_adc { +- skin-temp-thermistor@4e { +- reg = ; +- qcom,ratiometric; +- qcom,hw-settle-time = <200>; +- }; +-}; +- +-&pm6150_adc_tm { +- status = "okay"; +- +- skin-temp-thermistor@1 { +- reg = <1>; +- io-channels = <&pm6150_adc ADC5_AMUX_THM2_100K_PU>; +- qcom,ratiometric; +- qcom,hw-settle-time-us = <200>; +- }; +-}; +- +-&pp3300_dx_edp { +- gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; +-}; +- +-&sdhc_2 { +- status = "okay"; +-}; +- +-&sn65dsi86_out { +- data-lanes = <0 1 2 3>; +-}; +- +-&sound { +- compatible = "google,sc7180-coachz"; +- model = "sc7180-adau7002-max98357a"; +- audio-routing = "PDM_DAT", "DMIC"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&dmic_clk_en>; +-}; +- +-&sound_multimedia0_codec { +- sound-dai = <&adau7002>; +-}; +- +-/* PINCTRL - modifications to sc7180-trogdor.dtsi */ +- +-&en_pp3300_dx_edp { +- pinmux { +- pins = "gpio67"; +- }; +- +- pinconf { +- pins = "gpio67"; +- }; +-}; +- +-&ts_reset_l { +- pinconf { +- /* +- * We want reset state by default and it will be up to the +- * driver to disable this when it's ready. +- */ +- output-low; +- }; +-}; +- +-/* PINCTRL - board-specific pinctrl */ +- +-&tlmm { +- gpio-line-names = "HUB_RST_L", +- "AP_RAM_ID0", +- "AP_SKU_ID2", +- "AP_RAM_ID1", +- "FP_TO_AP_IRQ_L", +- "AP_RAM_ID2", +- "UF_CAM_EN", +- "WF_CAM_EN", +- "TS_RESET_L", +- "TS_INT_L", +- "FPMCU_BOOT0", +- "EDP_BRIJ_IRQ", +- "AP_EDP_BKLTEN", +- "UF_CAM_MCLK", +- "WF_CAM_CLK", +- "EDP_BRIJ_I2C_SDA", +- "EDP_BRIJ_I2C_SCL", +- "UF_CAM_SDA", +- "UF_CAM_SCL", +- "WF_CAM_SDA", +- "WF_CAM_SCL", +- "WLC_IRQ", +- "FP_RST_L", +- "AMP_EN", +- "WLC_NRST", +- "AP_SAR_SENSOR_SDA", +- "AP_SAR_SENSOR_SCL", +- "", +- "", +- "WF_CAM_RST_L", +- "UF_CAM_RST_L", +- "AP_BRD_ID2", +- "BRIJ_SUSPEND", +- "AP_BRD_ID0", +- "AP_H1_SPI_MISO", +- "AP_H1_SPI_MOSI", +- "AP_H1_SPI_CLK", +- "AP_H1_SPI_CS_L", +- "", +- "", +- "", +- "", +- "H1_AP_INT_ODL", +- "", +- "UART_AP_TX_DBG_RX", +- "UART_DBG_TX_AP_RX", +- "", +- "", +- "FORCED_USB_BOOT", +- "AMP_BCLK", +- "AMP_LRCLK", +- "AMP_DIN", +- "", +- "HP_BCLK", +- "HP_LRCLK", +- "HP_DOUT", +- "HP_DIN", +- "HP_MCLK", +- "AP_SKU_ID0", +- "AP_EC_SPI_MISO", +- "AP_EC_SPI_MOSI", +- "AP_EC_SPI_CLK", +- "AP_EC_SPI_CS_L", +- "AP_SPI_CLK", +- "AP_SPI_MOSI", +- "AP_SPI_MISO", +- /* +- * AP_FLASH_WP_L is crossystem ABI. Schematics +- * call it BIOS_FLASH_WP_L. +- */ +- "AP_FLASH_WP_L", +- "EN_PP3300_DX_EDP", +- "AP_SPI_CS0_L", +- "SD_CD_ODL", +- "", +- "", +- "", +- "", +- "EN_FP_RAILS", +- "UIM2_DATA", +- "UIM2_CLK", +- "UIM2_RST", +- "UIM2_PRESENT_L", +- "UIM1_DATA", +- "UIM1_CLK", +- "UIM1_RST", +- "", +- "", +- "HUB_EN", +- "", +- "AP_SPI_FP_MISO", +- "AP_SPI_FP_MOSI", +- "AP_SPI_FP_CLK", +- "AP_SPI_FP_CS_L", +- "AP_SKU_ID1", +- "AP_RST_REQ", +- "", +- "AP_BRD_ID1", +- "AP_EC_INT_L", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "EDP_BRIJ_EN", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "AP_TS_PEN_I2C_SDA", +- "AP_TS_PEN_I2C_SCL", +- "DP_HOT_PLUG_DET", +- "EC_IN_RW_ODL"; +- +- dmic_clk_en: dmic_clk_en { +- pinmux { +- pins = "gpio83"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio83"; +- drive-strength = <8>; +- bias-pull-up; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts +deleted file mode 100644 +index 6ebde0828550..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Lazor Limozeen board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-#include "sc7180-trogdor-lazor-limozeen-nots.dts" +- +-/ { +- model = "Google Lazor Limozeen without Touchscreen (rev4)"; +- compatible = "google,lazor-rev4-sku5", "qcom,sc7180"; +-}; +- +-/* +- * rev4-sku5 was built with a different trackpad. +- */ +-/delete-node/&trackpad; +-&ap_tp_i2c { +- trackpad: trackpad@2c { +- compatible = "hid-over-i2c"; +- reg = <0x2c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tp_int_odl>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <58 IRQ_TYPE_EDGE_FALLING>; +- +- vcc-supply = <&pp3300_fp_tp>; +- hid-descr-addr = <0x20>; +- +- wakeup-source; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-limozeen-nots.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-limozeen-nots.dts +deleted file mode 100644 +index 0456c7e05d00..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-limozeen-nots.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Lazor Limozeen board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-/dts-v1/; +- +-#include "sc7180-trogdor-lazor.dtsi" +-#include "sc7180-trogdor-lte-sku.dtsi" +- +-/ { +- model = "Google Lazor Limozeen without Touchscreen"; +- compatible = "google,lazor-sku6", "google,lazor-sku5", "qcom,sc7180"; +-}; +- +-/delete-node/&ap_ts; +- +-&panel { +- compatible = "innolux,n116bca-ea1", "innolux,n116bge"; +-}; +- +-&sdhc_2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-limozeen.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-limozeen.dts +deleted file mode 100644 +index e6ad6dae4e60..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-limozeen.dts ++++ /dev/null +@@ -1,42 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Lazor Limozeen board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-/dts-v1/; +- +-#include "sc7180-trogdor-lazor.dtsi" +-#include "sc7180-trogdor-lte-sku.dtsi" +- +-/ { +- model = "Google Lazor Limozeen"; +- compatible = "google,lazor-sku4", "qcom,sc7180"; +-}; +- +-/delete-node/&ap_ts; +- +-&ap_ts_pen_1v8 { +- ap_ts: touchscreen@10 { +- compatible = "elan,ekth3500"; +- reg = <0x10>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <9 IRQ_TYPE_LEVEL_LOW>; +- +- vcc33-supply = <&pp3300_ts>; +- +- reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&panel { +- compatible = "auo,b116xa01"; +-}; +- +-&sdhc_2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r0.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r0.dts +deleted file mode 100644 +index 30e3e769d2b4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r0.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Lazor board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-/dts-v1/; +- +-#include "sc7180-trogdor-lazor.dtsi" +- +-/ { +- model = "Google Lazor (rev0)"; +- compatible = "google,lazor-rev0", "qcom,sc7180"; +-}; +- +-&pp3300_hub { +- /* pp3300_l7c is used to power the USB hub */ +- /delete-property/regulator-always-on; +- /delete-property/regulator-boot-on; +-}; +- +-&pp3300_l7c { +- regulator-always-on; +- regulator-boot-on; +-}; +- +-&sn65dsi86_out { +- /* +- * Lane 0 was incorrectly mapped on the cable, but we've now decided +- * that the cable is canon and in -rev1+ we'll make a board change +- * that means we no longer need the swizzle. +- */ +- lane-polarities = <1 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r1-kb.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r1-kb.dts +deleted file mode 100644 +index 919bfaea6189..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r1-kb.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Lazor board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-#include "sc7180-trogdor-lazor-r1.dts" +- +-/ { +- model = "Google Lazor (rev1 - 2) with KB Backlight"; +- compatible = "google,lazor-rev1-sku2", "google,lazor-rev2-sku2", "qcom,sc7180"; +-}; +- +-&keyboard_backlight { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r1-lte.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r1-lte.dts +deleted file mode 100644 +index e16ba7b01f25..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r1-lte.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Lazor board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-#include "sc7180-trogdor-lazor-r1.dts" +-#include "sc7180-trogdor-lte-sku.dtsi" +- +-/ { +- model = "Google Lazor (rev1 - 2) with LTE"; +- compatible = "google,lazor-rev1-sku0", "google,lazor-rev2-sku0", "qcom,sc7180"; +-}; +- +-&ap_sar_sensor { +- status = "okay"; +-}; +- +-&ap_sar_sensor_i2c { +- status = "okay"; +-}; +- +-&keyboard_backlight { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r1.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r1.dts +deleted file mode 100644 +index c2ef06367baf..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r1.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Lazor board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-/dts-v1/; +- +-#include "sc7180-trogdor-lazor.dtsi" +- +-/ { +- model = "Google Lazor (rev1 - 2)"; +- compatible = "google,lazor-rev1", "google,lazor-rev2", "qcom,sc7180"; +-}; +- +-&pp3300_hub { +- /* pp3300_l7c is used to power the USB hub */ +- /delete-property/regulator-always-on; +- /delete-property/regulator-boot-on; +-}; +- +-&pp3300_l7c { +- regulator-always-on; +- regulator-boot-on; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r3-kb.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r3-kb.dts +deleted file mode 100644 +index dcb41afdc82a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r3-kb.dts ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Lazor board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-/dts-v1/; +- +-#include "sc7180-trogdor-lazor.dtsi" +-#include "sc7180-lite.dtsi" +- +-/ { +- model = "Google Lazor (rev3+) with KB Backlight"; +- compatible = "google,lazor-sku2", "qcom,sc7180"; +-}; +- +-&keyboard_backlight { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r3-lte.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r3-lte.dts +deleted file mode 100644 +index be44900602d7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r3-lte.dts ++++ /dev/null +@@ -1,28 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Lazor board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-/dts-v1/; +- +-#include "sc7180-trogdor-lazor.dtsi" +-#include "sc7180-trogdor-lte-sku.dtsi" +- +-/ { +- model = "Google Lazor (rev3+) with LTE"; +- compatible = "google,lazor-sku0", "qcom,sc7180"; +-}; +- +-&ap_sar_sensor { +- status = "okay"; +-}; +- +-&ap_sar_sensor_i2c { +- status = "okay"; +-}; +- +-&keyboard_backlight { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r3.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r3.dts +deleted file mode 100644 +index b474df47cd70..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor-r3.dts ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Lazor board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-/dts-v1/; +- +-#include "sc7180-trogdor-lazor.dtsi" +-#include "sc7180-lite.dtsi" +- +-/ { +- model = "Google Lazor (rev3+)"; +- compatible = "google,lazor", "qcom,sc7180"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor.dtsi +deleted file mode 100644 +index 00535aaa43c9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lazor.dtsi ++++ /dev/null +@@ -1,211 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Lazor board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-#include "sc7180.dtsi" +- +-ap_ec_spi: &spi6 {}; +-ap_h1_spi: &spi0 {}; +- +-#include "sc7180-trogdor.dtsi" +- +-&ap_sar_sensor { +- semtech,cs0-ground; +- semtech,combined-sensors = <3>; +- semtech,resolution = "fine"; +- semtech,startup-sensor = <0>; +- semtech,proxraw-strength = <8>; +- semtech,avg-pos-strength = <64>; +-}; +- +-/* +- * Lazor is stuffed with a 47k NTC as charger thermistor which currently is +- * not supported by the PM6150 ADC driver. Disable the charger thermal zone +- * to avoid using bogus temperature values. +- */ +-&charger_thermal { +- status = "disabled"; +-}; +- +-ap_ts_pen_1v8: &i2c4 { +- status = "okay"; +- clock-frequency = <400000>; +- +- ap_ts: touchscreen@10 { +- compatible = "hid-over-i2c"; +- reg = <0x10>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <9 IRQ_TYPE_LEVEL_LOW>; +- +- post-power-on-delay-ms = <20>; +- hid-descr-addr = <0x0001>; +- +- vdd-supply = <&pp3300_ts>; +- }; +-}; +- +-&panel { +- compatible = "boe,nv133fhm-n62"; +-}; +- +-&trackpad { +- interrupts = <58 IRQ_TYPE_EDGE_FALLING>; +-}; +- +-&wifi { +- qcom,ath10k-calibration-variant = "GO_LAZOR"; +-}; +- +-/* PINCTRL - modifications to sc7180-trogdor.dtsi */ +- +-&trackpad_int_1v8_odl { +- pinmux { +- pins = "gpio58"; +- }; +- +- pinconf { +- pins = "gpio58"; +- }; +-}; +- +-&ts_reset_l { +- pinconf { +- /* This pin is not connected on -rev0, pull up to park. */ +- /delete-property/bias-disable; +- bias-pull-up; +- }; +-}; +- +-/* PINCTRL - board-specific pinctrl */ +- +-&tlmm { +- gpio-line-names = "ESIM_MISO", +- "ESIM_MOSI", +- "ESIM_CLK", +- "ESIM_CS_L", +- "", +- "", +- "AP_TP_I2C_SDA", +- "AP_TP_I2C_SCL", +- "TS_RESET_L", +- "TS_INT_L", +- "", +- "EDP_BRIJ_IRQ", +- "AP_EDP_BKLTEN", +- "AP_RAM_ID2", +- "", +- "EDP_BRIJ_I2C_SDA", +- "EDP_BRIJ_I2C_SCL", +- "HUB_RST_L", +- "", +- "AP_RAM_ID1", +- "AP_SKU_ID2", +- "", +- "", +- "AMP_EN", +- "P_SENSOR_INT_L", +- "AP_SAR_SENSOR_SDA", +- "AP_SAR_SENSOR_SCL", +- "", +- "HP_IRQ", +- "AP_RAM_ID0", +- "EN_PP3300_DX_EDP", +- "AP_BRD_ID2", +- "BRIJ_SUSPEND", +- "AP_BRD_ID0", +- "AP_H1_SPI_MISO", +- "AP_H1_SPI_MOSI", +- "AP_H1_SPI_CLK", +- "AP_H1_SPI_CS_L", +- "", +- "", +- "", +- "", +- "H1_AP_INT_ODL", +- "", +- "UART_AP_TX_DBG_RX", +- "UART_DBG_TX_AP_RX", +- "HP_I2C_SDA", +- "HP_I2C_SCL", +- "FORCED_USB_BOOT", +- "", +- "", +- "AMP_DIN", +- "", +- "HP_BCLK", +- "HP_LRCLK", +- "HP_DOUT", +- "HP_DIN", +- "HP_MCLK", +- "TRACKPAD_INT_1V8_ODL", +- "AP_EC_SPI_MISO", +- "AP_EC_SPI_MOSI", +- "AP_EC_SPI_CLK", +- "AP_EC_SPI_CS_L", +- "AP_SPI_CLK", +- "AP_SPI_MOSI", +- "AP_SPI_MISO", +- /* +- * AP_FLASH_WP_L is crossystem ABI. Schematics +- * call it BIOS_FLASH_WP_L. +- */ +- "AP_FLASH_WP_L", +- "DBG_SPI_HOLD_L", +- "AP_SPI_CS0_L", +- "", +- "", +- "", +- "", +- "", +- "", +- "UIM2_DATA", +- "UIM2_CLK", +- "UIM2_RST", +- "UIM2_PRESENT", +- "UIM1_DATA", +- "UIM1_CLK", +- "UIM1_RST", +- "", +- "EN_PP3300_CODEC", +- "EN_PP3300_HUB", +- "", +- "", +- "", +- "", +- "", +- "AP_SKU_ID1", +- "AP_RST_REQ", +- "", +- "AP_BRD_ID1", +- "AP_EC_INT_L", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "EDP_BRIJ_EN", +- "AP_SKU_ID0", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "AP_TS_PEN_I2C_SDA", +- "AP_TS_PEN_I2C_SCL", +- "DP_HOT_PLUG_DET", +- "EC_IN_RW_ODL"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lte-sku.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lte-sku.dtsi +deleted file mode 100644 +index 469aad4e5948..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-lte-sku.dtsi ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Trogdor dts fragment for LTE SKUs +- * +- * Copyright 2020 Google LLC. +- */ +- +-&ap_sar_sensor { +- label = "proximity-wifi-lte"; +-}; +- +-&mpss_mem { +- reg = <0x0 0x86000000 0x0 0x8c00000>; +-}; +- +-&remoteproc_mpss { +- firmware-name = "qcom/sc7180-trogdor/modem/mba.mbn", +- "qcom/sc7180-trogdor/modem/qdsp6sw.mbn"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom-r1-lte.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom-r1-lte.dts +deleted file mode 100644 +index 0202f03eafe6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom-r1-lte.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Pompom board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-#include "sc7180-trogdor-pompom-r1.dts" +-#include "sc7180-trogdor-lte-sku.dtsi" +- +-/ { +- model = "Google Pompom (rev1) with LTE"; +- compatible = "google,pompom-rev1-sku0", "qcom,sc7180"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom-r1.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom-r1.dts +deleted file mode 100644 +index e122a6b481ff..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom-r1.dts ++++ /dev/null +@@ -1,38 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Pompom board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-/dts-v1/; +- +-#include "sc7180-trogdor-pompom.dtsi" +- +-/delete-node/ &keyboard_controller; +-#include +- +-/ { +- model = "Google Pompom (rev1)"; +- compatible = "google,pompom-rev1", "qcom,sc7180"; +-}; +- +-/* +- * Pompom rev1 is stuffed with a 47k NTC as charger thermistor which currently +- * is not supported by the PM6150 ADC driver. Disable the charger thermal zone +- * to avoid using bogus temperature values. +- */ +-&charger_thermal { +- status = "disabled"; +-}; +- +-&pp3300_hub { +- /* pp3300_l7c is used to power the USB hub */ +- /delete-property/regulator-always-on; +- /delete-property/regulator-boot-on; +-}; +- +-&pp3300_l7c { +- regulator-always-on; +- regulator-boot-on; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom-r2-lte.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom-r2-lte.dts +deleted file mode 100644 +index 00e187c08eb9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom-r2-lte.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Pompom board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-#include "sc7180-trogdor-pompom-r2.dts" +-#include "sc7180-trogdor-lte-sku.dtsi" +- +-/ { +- model = "Google Pompom (rev2) with LTE"; +- compatible = "google,pompom-rev2-sku0", "qcom,sc7180"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom-r2.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom-r2.dts +deleted file mode 100644 +index 4f32e6733f4c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom-r2.dts ++++ /dev/null +@@ -1,24 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Pompom board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-/dts-v1/; +- +-#include "sc7180-trogdor-pompom.dtsi" +- +-/ { +- model = "Google Pompom (rev2)"; +- compatible = "google,pompom-rev2", "qcom,sc7180"; +-}; +- +-/* +- * Pompom rev2 is stuffed with a 47k NTC as charger thermistor which currently +- * is not supported by the PM6150 ADC driver. Disable the charger thermal zone +- * to avoid using bogus temperature values. +- */ +-&charger_thermal { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom-r3-lte.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom-r3-lte.dts +deleted file mode 100644 +index e90b73c353bb..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom-r3-lte.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Pompom board device tree source +- * +- * Copyright 2021 Google LLC. +- */ +- +-#include "sc7180-trogdor-pompom-r3.dts" +-#include "sc7180-trogdor-lte-sku.dtsi" +- +-/ { +- model = "Google Pompom (rev3+) with LTE"; +- compatible = "google,pompom-sku0", "qcom,sc7180"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom-r3.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom-r3.dts +deleted file mode 100644 +index f8aac63a53ef..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom-r3.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Pompom board device tree source +- * +- * Copyright 2021 Google LLC. +- */ +- +-/dts-v1/; +- +-#include "sc7180-trogdor-pompom.dtsi" +- +-/ { +- model = "Google Pompom (rev3+)"; +- compatible = "google,pompom", "qcom,sc7180"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom.dtsi +deleted file mode 100644 +index b7b5264888b7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-pompom.dtsi ++++ /dev/null +@@ -1,324 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Pompom board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-#include "sc7180.dtsi" +- +-ap_ec_spi: &spi6 {}; +-ap_h1_spi: &spi0 {}; +- +-#include "sc7180-trogdor.dtsi" +- +-/ { +- thermal-zones { +- 5v-choke-thermal { +- polling-delay-passive = <0>; +- polling-delay = <250>; +- +- thermal-sensors = <&pm6150_adc_tm 1>; +- +- trips { +- 5v-choke-crit { +- temperature = <125000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +- +-&alc5682 { +- realtek,dmic-clk-driving-high = "true"; +-}; +- +-&cpu6_alert0 { +- temperature = <60000>; +-}; +- +-&cpu6_alert1 { +- temperature = <65000>; +-}; +- +-&cpu6_thermal { +- sustainable-power = <1124>; +-}; +- +-&cpu7_alert0 { +- temperature = <60000>; +-}; +- +-&cpu7_alert1 { +- temperature = <65000>; +-}; +- +-&cpu7_thermal { +- sustainable-power = <1124>; +-}; +- +-&cpu8_alert0 { +- temperature = <60000>; +-}; +- +-&cpu8_alert1 { +- temperature = <65000>; +-}; +- +-&cpu8_thermal { +- sustainable-power = <1124>; +-}; +- +-&cpu9_alert0 { +- temperature = <60000>; +-}; +- +-&cpu9_alert1 { +- temperature = <65000>; +-}; +- +-&cpu9_thermal { +- sustainable-power = <1124>; +-}; +- +-&gpio_keys { +- status = "okay"; +-}; +- +-ap_ts_pen_1v8: &i2c4 { +- status = "okay"; +- clock-frequency = <400000>; +- +- ap_ts: touchscreen@10 { +- compatible = "hid-over-i2c"; +- reg = <0x10>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <9 IRQ_TYPE_LEVEL_LOW>; +- +- post-power-on-delay-ms = <20>; +- hid-descr-addr = <0x0001>; +- +- vdd-supply = <&pp3300_ts>; +- }; +-}; +- +-&keyboard_controller { +- function-row-physmap = < +- MATRIX_KEY(0x00, 0x02, 0) /* T1 */ +- MATRIX_KEY(0x03, 0x02, 0) /* T2 */ +- MATRIX_KEY(0x02, 0x02, 0) /* T3 */ +- MATRIX_KEY(0x01, 0x02, 0) /* T4 */ +- MATRIX_KEY(0x03, 0x04, 0) /* T5 */ +- MATRIX_KEY(0x02, 0x04, 0) /* T6 */ +- MATRIX_KEY(0x01, 0x04, 0) /* T7 */ +- MATRIX_KEY(0x02, 0x09, 0) /* T8 */ +- MATRIX_KEY(0x01, 0x09, 0) /* T9 */ +- MATRIX_KEY(0x00, 0x04, 0) /* T10 */ +- >; +- linux,keymap = < +- MATRIX_KEY(0x00, 0x02, KEY_BACK) +- MATRIX_KEY(0x03, 0x02, KEY_REFRESH) +- MATRIX_KEY(0x02, 0x02, KEY_ZOOM) +- MATRIX_KEY(0x01, 0x02, KEY_SCALE) +- MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) +- MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) +- MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) +- MATRIX_KEY(0x02, 0x09, KEY_MUTE) +- MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) +- MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) +- +- CROS_STD_MAIN_KEYMAP +- >; +-}; +- +-&panel { +- compatible = "kingdisplay,kd116n21-30nv-a010"; +-}; +- +-&pen_insert { +- /* Insert = high, eject = low */ +- gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; +-}; +- +-&pm6150_adc { +- 5v-choke-thermistor@4e { +- reg = ; +- qcom,ratiometric; +- qcom,hw-settle-time = <200>; +- }; +-}; +- +-&pm6150_adc_tm { +- status = "okay"; +- +- 5v-choke-thermistor@1 { +- reg = <1>; +- io-channels = <&pm6150_adc ADC5_AMUX_THM2_100K_PU>; +- qcom,ratiometric; +- qcom,hw-settle-time-us = <200>; +- }; +-}; +- +-&sdhc_2 { +- status = "okay"; +-}; +- +-&sound { +- model = "sc7180-rt5682-max98357a-2mic"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dmic_sel>; +- dmic-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>; +-}; +- +-&usb_c1 { +- status = "disabled"; +-}; +- +-&wifi { +- qcom,ath10k-calibration-variant = "GO_POMPOM"; +-}; +- +-/* PINCTRL - board-specific pinctrl */ +- +-&tlmm { +- gpio-line-names = "TP_INT_ODL", +- "AP_RAM_ID0", +- "AP_SKU_ID2", +- "AP_RAM_ID1", +- "", +- "AP_RAM_ID2", +- "AP_TP_I2C_SDA", +- "AP_TP_I2C_SCL", +- "TS_RESET_L", +- "TS_INT_L", +- "", +- "EDP_BRIJ_IRQ", +- "AP_EDP_BKLTEN", +- "", +- "", +- "EDP_BRIJ_I2C_SDA", +- "EDP_BRIJ_I2C_SCL", +- "HUB_RST_L", +- "", +- "", +- "", +- "", +- "", +- "AMP_EN", +- "P_SENSOR_INT_L", +- "AP_SAR_SENSOR_SDA", +- "AP_SAR_SENSOR_SCL", +- "", +- "HP_IRQ", +- "", +- "EN_PP3300_DX_EDP", +- "AP_BRD_ID2", +- "BRIJ_SUSPEND", +- "AP_BRD_ID0", +- "AP_H1_SPI_MISO", +- "AP_H1_SPI_MOSI", +- "AP_H1_SPI_CLK", +- "AP_H1_SPI_CS_L", +- "", +- "", +- "", +- "", +- "H1_AP_INT_ODL", +- "", +- "UART_AP_TX_DBG_RX", +- "UART_DBG_TX_AP_RX", +- "HP_I2C_SDA", +- "HP_I2C_SCL", +- "FORCED_USB_BOOT", +- "AMP_BCLK", +- "AMP_LRCLK", +- "AMP_DIN", +- "PEN_PDCT_L", +- "HP_BCLK", +- "HP_LRCLK", +- "HP_DOUT", +- "HP_DIN", +- "HP_MCLK", +- "AP_SKU_ID0", +- "AP_EC_SPI_MISO", +- "AP_EC_SPI_MOSI", +- "AP_EC_SPI_CLK", +- "AP_EC_SPI_CS_L", +- "AP_SPI_CLK", +- "AP_SPI_MOSI", +- "AP_SPI_MISO", +- /* +- * AP_FLASH_WP_L is crossystem ABI. Schematics +- * call it BIOS_FLASH_WP_L. +- */ +- "AP_FLASH_WP_L", +- "", +- "AP_SPI_CS0_L", +- "SD_CD_ODL", +- "", +- "", +- "", +- "", +- "", +- "UIM2_DATA", +- "UIM2_CLK", +- "UIM2_RST", +- "UIM2_PRESENT", +- "UIM1_DATA", +- "UIM1_CLK", +- "UIM1_RST", +- "", +- "EN_PP3300_CODEC", +- "EN_PP3300_HUB", +- "", +- "DMIC_SEL", +- "", +- "", +- "", +- "AP_SKU_ID1", +- "AP_RST_REQ", +- "", +- "AP_BRD_ID1", +- "AP_EC_INT_R_L", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "EDP_BRIJ_EN", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "AP_TS_PEN_I2C_SDA", +- "AP_TS_PEN_I2C_SCL", +- "DP_HOT_PLUG_DET", +- "EC_IN_RW_ODL"; +- +- dmic_sel: dmic-sel { +- pinmux { +- pins = "gpio86"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio86"; +- bias-pull-down; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-r1-lte.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-r1-lte.dts +deleted file mode 100644 +index 1123c02bd539..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-r1-lte.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Trogdor board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-#include "sc7180-trogdor-r1.dts" +-#include "sc7180-trogdor-lte-sku.dtsi" +- +-/ { +- model = "Google Trogdor (rev1+) with LTE"; +- compatible = "google,trogdor-sku0", "qcom,sc7180"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-r1.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-r1.dts +deleted file mode 100644 +index 2b522f9e0d8f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-r1.dts ++++ /dev/null +@@ -1,202 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Trogdor board device tree source +- * +- * Copyright 2020 Google LLC. +- */ +- +-/dts-v1/; +- +-#include "sc7180.dtsi" +- +-ap_ec_spi: &spi6 {}; +-ap_h1_spi: &spi0 {}; +- +-#include "sc7180-trogdor.dtsi" +- +-/ { +- model = "Google Trogdor (rev1+)"; +- compatible = "google,trogdor", "qcom,sc7180"; +-}; +- +-ap_ts_pen_1v8: &i2c4 { +- status = "okay"; +- clock-frequency = <400000>; +- +- ap_ts: touchscreen@10 { +- compatible = "elan,ekth3500"; +- reg = <0x10>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <9 IRQ_TYPE_LEVEL_LOW>; +- +- vcc33-supply = <&pp3300_ts>; +- +- reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&panel { +- compatible = "auo,b116xa01"; +-}; +- +-&pp3300_hub { +- /* pp3300_l7c is used to power the USB hub */ +- /delete-property/regulator-always-on; +- /delete-property/regulator-boot-on; +-}; +- +-&pp3300_l7c { +- regulator-always-on; +- regulator-boot-on; +-}; +- +-&sdhc_2 { +- status = "okay"; +-}; +- +-&trackpad { +- interrupts = <58 IRQ_TYPE_EDGE_FALLING>; +-}; +- +-/* PINCTRL - modifications to sc7180-trogdor.dtsi */ +- +-&trackpad_int_1v8_odl { +- pinmux { +- pins = "gpio58"; +- }; +- +- pinconf { +- pins = "gpio58"; +- }; +-}; +- +-/* PINCTRL - board-specific pinctrl */ +- +-&tlmm { +- gpio-line-names = "ESIM_MISO", +- "ESIM_MOSI", +- "ESIM_CLK", +- "ESIM_CS_L", +- "FP_TO_AP_IRQ_L", +- "FP_RST_L", +- "AP_TP_I2C_SDA", +- "AP_TP_I2C_SCL", +- "TS_RESET_L", +- "TS_INT_L", +- "FPMCU_BOOT0", +- "EDP_BRIJ_IRQ", +- "AP_EDP_BKLTEN", +- "", +- "", +- "EDP_BRIJ_I2C_SDA", +- "EDP_BRIJ_I2C_SCL", +- "HUB_RST_L", +- "PEN_RST_ODL", +- "AP_RAM_ID1", +- "AP_RAM_ID2", +- "PEN_IRQ_L", +- "FPMCU_SEL", +- "AMP_EN", +- "P_SENSOR_INT_L", +- "AP_SAR_SENSOR_SDA", +- "AP_SAR_SENSOR_SCL", +- "", +- "HP_IRQ", +- "AP_RAM_ID0", +- "EN_PP3300_DX_EDP", +- "AP_BRD_ID2", +- "BRIJ_SUSPEND", +- "AP_BRD_ID0", +- "AP_H1_SPI_MISO", +- "AP_H1_SPI_MOSI", +- "AP_H1_SPI_CLK", +- "AP_H1_SPI_CS_L", +- "", +- "", +- "", +- "", +- "H1_AP_INT_ODL", +- "", +- "UART_AP_TX_DBG_RX", +- "UART_DBG_TX_AP_RX", +- "HP_I2C_SDA", +- "HP_I2C_SCL", +- "FORCED_USB_BOOT", +- "", +- "", +- "AMP_DIN", +- "PEN_PDCT_L", +- "HP_BCLK", +- "HP_LRCLK", +- "HP_DOUT", +- "HP_DIN", +- "HP_MCLK", +- "TRACKPAD_INT_1V8_ODL", +- "AP_EC_SPI_MISO", +- "AP_EC_SPI_MOSI", +- "AP_EC_SPI_CLK", +- "AP_EC_SPI_CS_L", +- "AP_SPI_CLK", +- "AP_SPI_MOSI", +- "AP_SPI_MISO", +- /* +- * AP_FLASH_WP_L is crossystem ABI. Schematics +- * call it BIOS_FLASH_WP_L. +- */ +- "AP_FLASH_WP_L", +- "DBG_SPI_HOLD_L", +- "AP_SPI_CS0_L", +- "SD_CD_ODL", +- "", +- "", +- "", +- "", +- "", +- "UIM2_DATA", +- "UIM2_CLK", +- "UIM2_RST", +- "UIM2_PRESENT", +- "UIM1_DATA", +- "UIM1_CLK", +- "UIM1_RST", +- "", +- "EN_PP3300_CODEC", +- "EN_PP3300_HUB", +- "", +- "AP_SPI_FP_MISO", +- "AP_SPI_FP_MOSI", +- "AP_SPI_FP_CLK", +- "AP_SPI_FP_CS_L", +- "AP_SKU_ID1", +- "AP_RST_REQ", +- "", +- "AP_BRD_ID1", +- "AP_EC_INT_L", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "EDP_BRIJ_EN", +- "AP_SKU_ID0", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "AP_TS_PEN_I2C_SDA", +- "AP_TS_PEN_I2C_SCL", +- "DP_HOT_PLUG_DET", +- "EC_IN_RW_ODL"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor.dtsi +deleted file mode 100644 +index 70c88c37de32..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor.dtsi ++++ /dev/null +@@ -1,1617 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Trogdor device tree source (common between revisions) +- * +- * Copyright 2019 Google LLC. +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/* PMICs depend on spmi_bus label and so must come after SoC */ +-#include "pm6150.dtsi" +-#include "pm6150l.dtsi" +- +-/ { +- thermal-zones { +- charger_thermal: charger-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&pm6150_adc_tm 0>; +- +- trips { +- charger-crit { +- temperature = <125000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- }; +-}; +- +-/* +- * Reserved memory changes +- * +- * Delete all unused memory nodes and define the peripheral memory regions +- * required by the board dts. +- */ +- +-/delete-node/ &hyp_mem; +-/delete-node/ &xbl_mem; +-/delete-node/ &aop_mem; +-/delete-node/ &sec_apps_mem; +-/delete-node/ &tz_mem; +- +-/* Increase the size from 2MB to 8MB */ +-&rmtfs_mem { +- reg = <0x0 0x94600000 0x0 0x800000>; +-}; +- +-/ { +- reserved-memory { +- atf_mem: memory@80b00000 { +- reg = <0x0 0x80b00000 0x0 0x100000>; +- no-map; +- }; +- +- mpss_mem: memory@86000000 { +- reg = <0x0 0x86000000 0x0 0x2000000>; +- no-map; +- }; +- +- venus_mem: memory@8f600000 { +- reg = <0 0x8f600000 0 0x500000>; +- no-map; +- }; +- +- wlan_mem: memory@94100000 { +- reg = <0x0 0x94100000 0x0 0x200000>; +- no-map; +- }; +- +- mba_mem: memory@94400000 { +- reg = <0x0 0x94400000 0x0 0x200000>; +- no-map; +- }; +- }; +- +- aliases { +- bluetooth0 = &bluetooth; +- hsuart0 = &uart3; +- serial0 = &uart8; +- wifi0 = &wifi; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- /* FIXED REGULATORS - parents above children */ +- +- /* This is the top level supply and variable voltage */ +- ppvar_sys: ppvar-sys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "ppvar_sys"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* This divides ppvar_sys by 2, so voltage is variable */ +- src_vph_pwr: src-vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "src_vph_pwr"; +- +- /* EC turns on with switchcap_on; always on for AP */ +- regulator-always-on; +- regulator-boot-on; +- +- vin-supply = <&ppvar_sys>; +- }; +- +- pp5000_a: pp5000-a-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "pp5000_a"; +- +- /* EC turns on with en_pp5000_a; always on for AP */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- vin-supply = <&ppvar_sys>; +- }; +- +- pp3300_a: pp3300-a-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "pp3300_a"; +- +- /* EC turns on with en_pp3300_a; always on for AP */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- /* +- * Actually should be pp3300 but that's practically an alias for +- * pp3300_a so we use pp3300's vin-supply here to avoid one more +- * node. +- */ +- vin-supply = <&ppvar_sys>; +- }; +- +- pp3300_audio: +- pp3300_codec: pp3300-codec-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "pp3300_codec"; +- +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&tlmm 83 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&en_pp3300_codec>; +- +- vin-supply = <&pp3300_a>; +- }; +- +- pp3300_dx_edp: +- pp3300_ts: pp3300-dx-edp-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "pp3300_dx_edp"; +- +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&tlmm 30 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&en_pp3300_dx_edp>; +- +- vin-supply = <&pp3300_a>; +- }; +- +- pp3300_fp_tp: pp3300-fp-tp-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "pp3300_fp_tp"; +- +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- /* AP turns on with PP1800_VIO_OUT; always on for AP */ +- regulator-always-on; +- regulator-boot-on; +- +- vin-supply = <&pp3300_a>; +- }; +- +- pp3300_hub: pp3300-hub { +- compatible = "regulator-fixed"; +- regulator-name = "pp3300_hub"; +- +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&en_pp3300_hub>; +- +- regulator-always-on; +- regulator-boot-on; +- +- vin-supply = <&pp3300_a>; +- }; +- +- /* BOARD-SPECIFIC TOP LEVEL NODES */ +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- +- /* The panels don't seem to like anything below ~ 5% */ +- brightness-levels = < +- 196 256 324 400 484 576 676 784 900 1024 1156 1296 +- 1444 1600 1764 1936 2116 2304 2500 2704 2916 3136 +- 3364 3600 3844 4096 +- >; +- num-interpolated-steps = <64>; +- default-brightness-level = <951>; +- +- pwms = <&cros_ec_pwm 1>; +- enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; +- power-supply = <&ppvar_sys>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ap_edp_bklten>; +- }; +- +- gpio_keys: gpio-keys { +- compatible = "gpio-keys"; +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pen_pdct_l>; +- +- pen_insert: pen-insert { +- label = "Pen Insert"; +- +- /* Insert = low, eject = high */ +- gpios = <&tlmm 52 GPIO_ACTIVE_LOW>; +- linux,code = ; +- linux,input-type = ; +- wakeup-event-action = ; +- wakeup-source; +- }; +- }; +- +- max98360a: audio-codec-0 { +- compatible = "maxim,max98360a"; +- pinctrl-names = "default"; +- pinctrl-0 = <&_en>; +- sdmode-gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>; +- #sound-dai-cells = <0>; +- }; +- +- pwmleds { +- compatible = "pwm-leds"; +- keyboard_backlight: keyboard-backlight { +- status = "disabled"; +- label = "cros_ec::kbd_backlight"; +- pwms = <&cros_ec_pwm 0>; +- max-brightness = <1023>; +- }; +- }; +- +- sound: sound { +- compatible = "google,sc7180-trogdor"; +- model = "sc7180-rt5682-max98357a-1mic"; +- +- audio-routing = +- "Headphone Jack", "HPOL", +- "Headphone Jack", "HPOR"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- dai-link@0 { +- link-name = "MultiMedia0"; +- reg = ; +- cpu { +- sound-dai = <&lpass_cpu MI2S_PRIMARY>; +- }; +- +- sound_multimedia0_codec: codec { +- sound-dai = <&alc5682 0 /* aif1 */>; +- }; +- }; +- +- dai-link@1 { +- link-name = "MultiMedia1"; +- reg = ; +- cpu { +- sound-dai = <&lpass_cpu MI2S_SECONDARY>; +- }; +- +- sound_multimedia1_codec: codec { +- sound-dai = <&max98360a>; +- }; +- }; +- +- dai-link@5 { +- link-name = "MultiMedia2"; +- reg = ; +- cpu { +- sound-dai = <&lpass_cpu LPASS_DP_RX>; +- }; +- +- codec { +- sound-dai = <&mdss_dp>; +- }; +- }; +- }; +-}; +- +-&qfprom { +- vcc-supply = <&pp1800_l11a>; +-}; +- +-&qspi { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- +- spi-max-frequency = <37500000>; +- spi-tx-bus-width = <2>; +- spi-rx-bus-width = <2>; +- }; +-}; +- +-&apps_rsc { +- pm6150-rpmh-regulators { +- compatible = "qcom,pm6150-rpmh-regulators"; +- qcom,pmic-id = "a"; +- +- vddpx_1: +- vdd2: +- pp1125_s1a: smps1 { +- regulator-min-microvolt = <1128000>; +- regulator-max-microvolt = <1128000>; +- }; +- +- vdd_qlink_lv: +- vdd_qlink_lv_ck: +- vdd_qusb_hs0_core: +- vdd_ufs1_core: +- vdda_mipi_csi0_0p9: +- vdda_mipi_csi1_0p9: +- vdda_mipi_csi2_0p9: +- vdda_mipi_csi3_0p9: +- vdda_mipi_dsi0_pll: +- vdda_pll_cc_ebi01: +- vdda_qrefs_0p9: +- vdda_usb_ss_dp_core: +- pp900_l4a: ldo4 { +- regulator-min-microvolt = <824000>; +- regulator-max-microvolt = <928000>; +- regulator-initial-mode = ; +- }; +- +- vdd_cx_wlan: +- pp800_l9a: ldo9 { +- regulator-min-microvolt = <488000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vdd1: +- vddpx_3: +- vddpx_7: +- vio_in: +- pp1800_l10a: ldo10 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vdd_qfprom: +- vdda_apc1_cs_1p8: +- vdda_qrefs_1p8: +- vdda_qusb_hs0_1p8: +- vddpx_11: +- vreg_bb_clk: +- pp1800_l11a: ldo11 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- mcp_vccq: +- pp1800_l12a_r: ldo12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- /* +- * On trogdor this needs to match l10a since we use it to +- * give power to things like SPI flash which communicate back +- * on lines powered by l10a. Thus we force to 1.8V. +- */ +- pp1800_l13a: ldo13 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- pp1800_prox: +- pp1800_l14a: ldo14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- pp1800_alc5682: +- pp1800_l15a: ldo15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vdda_qusb_hs0_3p1: +- vdd_pdphy: +- pp3100_l17a: ldo17 { +- regulator-min-microvolt = <2920000>; +- regulator-max-microvolt = <3232000>; +- regulator-initial-mode = ; +- }; +- +- pp1800_pen: +- pp1800_l18a: ldo18 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- mcp_vcc: +- pp2850_l19a: ldo19 { +- regulator-min-microvolt = <2960000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- }; +- +- pm6150l-rpmh-regulators { +- compatible = "qcom,pm6150l-rpmh-regulators"; +- qcom,pmic-id = "c"; +- +- pp1300_s8c: smps8 { +- regulator-min-microvolt = <1120000>; +- regulator-max-microvolt = <1408000>; +- }; +- +- pp1800_l1c: ldo1 { +- regulator-min-microvolt = <1616000>; +- regulator-max-microvolt = <1984000>; +- regulator-initial-mode = ; +- }; +- +- vdd_wcss_adc_dac: +- pp1300_l2c: ldo2 { +- regulator-min-microvolt = <1168000>; +- regulator-max-microvolt = <1304000>; +- regulator-initial-mode = ; +- }; +- +- pp1200_brij: +- vdd_ufs1_1p2: +- vdda_csi0_1p25: +- vdda_csi1_1p25: +- vdda_csi2_1p25: +- vdda_csi3_1p25: +- vdda_hv_ebi0: +- vdda_mipi_dsi0_1p2: +- vdda_usb_ss_dp_1p2: +- vddpx_10: +- pp1200_l3c: ldo3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_2: +- ppvar_l6c: ldo6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2952000>; +- regulator-initial-mode = ; +- }; +- +- pp3300_l7c: ldo7 { +- regulator-min-microvolt = <3304000>; +- regulator-max-microvolt = <3304000>; +- regulator-initial-mode = ; +- }; +- +- pp1800_brij_vccio: +- pp1800_edp_vpll: +- pp1800_l8c: ldo8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- pp2950_l9c: ldo9 { +- regulator-min-microvolt = <2952000>; +- regulator-max-microvolt = <2952000>; +- regulator-initial-mode = ; +- }; +- +- pp3300_l10c: ldo10 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3400000>; +- regulator-initial-mode = ; +- }; +- +- pp3300_l11c: ldo11 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3400000>; +- regulator-initial-mode = ; +- }; +- +- src_vreg_bob: bob { +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3960000>; +- regulator-initial-mode = ; +- }; +- }; +-}; +- +-&ap_ec_spi { +- status = "okay"; +- cros_ec: ec@0 { +- compatible = "google,cros-ec-spi"; +- reg = <0>; +- interrupt-parent = <&tlmm>; +- interrupts = <94 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ap_ec_int_l>; +- spi-max-frequency = <3000000>; +- +- cros_ec_pwm: ec-pwm { +- compatible = "google,cros-ec-pwm"; +- #pwm-cells = <1>; +- }; +- +- i2c_tunnel: i2c-tunnel { +- compatible = "google,cros-ec-i2c-tunnel"; +- google,remote-bus = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- typec { +- compatible = "google,cros-ec-typec"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- usb_c0: connector@0 { +- compatible = "usb-c-connector"; +- reg = <0>; +- label = "left"; +- power-role = "dual"; +- data-role = "host"; +- try-power-role = "source"; +- }; +- +- usb_c1: connector@1 { +- compatible = "usb-c-connector"; +- reg = <1>; +- label = "right"; +- power-role = "dual"; +- data-role = "host"; +- try-power-role = "source"; +- }; +- }; +- }; +-}; +- +-&ap_h1_spi { +- status = "okay"; +- cr50: tpm@0 { +- compatible = "google,cr50"; +- reg = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&h1_ap_int_odl>; +- spi-max-frequency = <800000>; +- interrupt-parent = <&tlmm>; +- interrupts = <42 IRQ_TYPE_EDGE_RISING>; +- }; +-}; +- +-&camcc { +- status = "disabled"; +-}; +- +-&dsi0 { +- status = "okay"; +- vdda-supply = <&vdda_mipi_dsi0_1p2>; +- +- ports { +- port@1 { +- endpoint { +- remote-endpoint = <&sn65dsi86_in>; +- data-lanes = <0 1 2 3>; +- }; +- }; +- }; +-}; +- +-&dsi_phy { +- status = "okay"; +- vdds-supply = <&vdda_mipi_dsi0_pll>; +-}; +- +-edp_brij_i2c: &i2c2 { +- status = "okay"; +- clock-frequency = <400000>; +- +- sn65dsi86_bridge: bridge@2d { +- compatible = "ti,sn65dsi86"; +- reg = <0x2d>; +- pinctrl-names = "default"; +- pinctrl-0 = <&edp_brij_en>, <&edp_brij_irq>; +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; +- +- enable-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; +- +- vpll-supply = <&pp1800_edp_vpll>; +- vccio-supply = <&pp1800_brij_vccio>; +- vcca-supply = <&pp1200_brij>; +- vcc-supply = <&pp1200_brij>; +- +- clocks = <&rpmhcc RPMH_LN_BB_CLK3>; +- clock-names = "refclk"; +- +- no-hpd; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- sn65dsi86_in: endpoint { +- remote-endpoint = <&dsi0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- sn65dsi86_out: endpoint { +- data-lanes = <0 1>; +- remote-endpoint = <&panel_in_edp>; +- }; +- }; +- }; +- +- aux-bus { +- panel: panel { +- /* Compatible will be filled in per-board */ +- power-supply = <&pp3300_dx_edp>; +- backlight = <&backlight>; +- hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>; +- +- port { +- panel_in_edp: endpoint { +- remote-endpoint = <&sn65dsi86_out>; +- }; +- }; +- }; +- }; +- }; +-}; +- +-ap_sar_sensor_i2c: &i2c5 { +- clock-frequency = <400000>; +- +- ap_sar_sensor: proximity@28 { +- compatible = "semtech,sx9310"; +- reg = <0x28>; +- #io-channel-cells = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&p_sensor_int_l>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <24 IRQ_TYPE_LEVEL_LOW>; +- +- vdd-supply = <&pp3300_a>; +- svdd-supply = <&pp1800_prox>; +- +- status = "disabled"; +- label = "proximity-wifi"; +- }; +-}; +- +-ap_tp_i2c: &i2c7 { +- status = "okay"; +- clock-frequency = <400000>; +- +- trackpad: trackpad@15 { +- compatible = "elan,ekth3000"; +- reg = <0x15>; +- pinctrl-names = "default"; +- pinctrl-0 = <&tp_int_odl>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <0 IRQ_TYPE_EDGE_FALLING>; +- +- vcc-supply = <&pp3300_fp_tp>; +- +- wakeup-source; +- }; +-}; +- +-hp_i2c: &i2c9 { +- status = "okay"; +- clock-frequency = <400000>; +- +- alc5682: codec@1a { +- compatible = "realtek,rt5682i"; +- reg = <0x1a>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hp_irq>; +- +- #sound-dai-cells = <1>; +- +- interrupt-parent = <&tlmm>; +- /* +- * This will get ignored because the interrupt type +- * is set in rt5682.c. +- */ +- interrupts = <28 IRQ_TYPE_EDGE_BOTH>; +- +- AVDD-supply = <&pp1800_alc5682>; +- MICVDD-supply = <&pp3300_codec>; +- VBAT-supply = <&pp3300_audio>; +- +- realtek,dmic1-data-pin = <1>; +- realtek,dmic1-clk-pin = <1>; +- realtek,jd-src = <1>; +- }; +-}; +- +-&ipa { +- status = "okay"; +- +- /* +- * Trogdor doesn't have QHEE (Qualcomm's EL2 blob), so the +- * modem needs to cover certain init steps (GSI init), and +- * the AP needs to wait for it. +- */ +- modem-init; +-}; +- +-&lpass_cpu { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sec_mi2s_active>, <&pri_mi2s_active>, <&pri_mi2s_mclk_active>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- mi2s@0 { +- reg = ; +- qcom,playback-sd-lines = <1>; +- qcom,capture-sd-lines = <0>; +- }; +- +- secondary_mi2s: mi2s@1 { +- reg = ; +- qcom,playback-sd-lines = <0>; +- }; +- +- hdmi@5 { +- reg = ; +- }; +-}; +- +-&mdp { +- status = "okay"; +-}; +- +-&mdss { +- status = "okay"; +-}; +- +-&mdss_dp { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&dp_hot_plug_det>; +- data-lanes = <0 1>; +- vdda-1p2-supply = <&vdda_usb_ss_dp_1p2>; +- vdda-0p9-supply = <&vdda_usb_ss_dp_core>; +-}; +- +-&pm6150_adc { +- charger-thermistor@4f { +- reg = ; +- qcom,ratiometric; +- qcom,hw-settle-time = <200>; +- }; +-}; +- +-&pm6150_adc_tm { +- status = "okay"; +- +- charger-thermistor@0 { +- reg = <0>; +- io-channels = <&pm6150_adc ADC5_AMUX_THM3_100K_PU>; +- qcom,ratiometric; +- qcom,hw-settle-time-us = <200>; +- }; +-}; +- +-&pm6150_pon { +- status = "disabled"; +-}; +- +-&qupv3_id_0 { +- status = "okay"; +-}; +- +-&qupv3_id_1 { +- status = "okay"; +-}; +- +-&remoteproc_mpss { +- status = "okay"; +- compatible = "qcom,sc7180-mss-pil"; +- iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>; +- memory-region = <&mba_mem &mpss_mem>; +- +- /* This gets overridden for SKUs with LTE support. */ +- firmware-name = "qcom/sc7180-trogdor/modem-nolte/mba.mbn", +- "qcom/sc7180-trogdor/modem-nolte/qdsp6sw.mbn"; +-}; +- +-&sdhc_1 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc1_on>; +- pinctrl-1 = <&sdc1_off>; +- vmmc-supply = <&mcp_vcc>; +- vqmmc-supply = <&mcp_vccq>; +-}; +- +-&sdhc_2 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc2_on>; +- pinctrl-1 = <&sdc2_off>; +- vmmc-supply = <&pp2950_l9c>; +- vqmmc-supply = <&ppvar_l6c>; +- +- cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>; +-}; +- +-&spi0 { +- pinctrl-0 = <&qup_spi0_cs_gpio_init_high>, <&qup_spi0_cs_gpio>; +- cs-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; +-}; +- +-&spi6 { +- pinctrl-0 = <&qup_spi6_cs_gpio_init_high>, <&qup_spi6_cs_gpio>; +- cs-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; +-}; +- +-ap_spi_fp: &spi10 { +- pinctrl-0 = <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>; +- cs-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; +- +- cros_ec_fp: ec@0 { +- compatible = "google,cros-ec-spi"; +- reg = <0>; +- interrupt-parent = <&tlmm>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&fp_to_ap_irq_l>; +- spi-max-frequency = <3000000>; +- }; +-}; +- +-#include +-#include +- +-&uart3 { +- status = "okay"; +- +- /delete-property/interrupts; +- interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, +- <&tlmm 41 IRQ_TYPE_EDGE_FALLING>; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-1 = <&qup_uart3_sleep>; +- +- bluetooth: bluetooth { +- compatible = "qcom,wcn3991-bt"; +- vddio-supply = <&pp1800_l10a>; +- vddxo-supply = <&pp1800_l1c>; +- vddrf-supply = <&pp1300_l2c>; +- vddch0-supply = <&pp3300_l10c>; +- max-speed = <3200000>; +- }; +-}; +- +-&uart8 { +- status = "okay"; +-}; +- +-&usb_1 { +- status = "okay"; +-}; +- +-&usb_1_dwc3 { +- dr_mode = "host"; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- vdd-supply = <&vdd_qusb_hs0_core>; +- vdda-pll-supply = <&vdda_qusb_hs0_1p8>; +- vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; +- qcom,imp-res-offset-value = <8>; +- qcom,preemphasis-level = ; +- qcom,preemphasis-width = ; +- qcom,bias-ctrl-value = <0x22>; +- qcom,charge-ctrl-value = <3>; +- qcom,hsdisc-trim-value = <0>; +-}; +- +-&usb_1_qmpphy { +- status = "okay"; +- vdda-phy-supply = <&vdda_usb_ss_dp_1p2>; +- vdda-pll-supply = <&vdda_usb_ss_dp_core>; +-}; +- +-&venus { +- video-firmware { +- iommus = <&apps_smmu 0x0c42 0x0>; +- }; +-}; +- +-&wifi { +- status = "okay"; +- vdd-0.8-cx-mx-supply = <&vdd_cx_wlan>; +- vdd-1.8-xo-supply = <&pp1800_l1c>; +- vdd-1.3-rfa-supply = <&pp1300_l2c>; +- vdd-3.3-ch0-supply = <&pp3300_l10c>; +- vdd-3.3-ch1-supply = <&pp3300_l11c>; +- +- wifi-firmware { +- iommus = <&apps_smmu 0xc2 0x1>; +- }; +-}; +- +-/* PINCTRL - additions to nodes defined in sc7180.dtsi */ +- +-&dp_hot_plug_det { +- pinconf { +- pins = "gpio117"; +- bias-disable; +- }; +-}; +- +-&pri_mi2s_active { +- pinconf { +- pins = "gpio53", "gpio54", "gpio55", "gpio56"; +- drive-strength = <2>; +- bias-pull-down; +- }; +-}; +- +-&pri_mi2s_mclk_active { +- pinconf { +- pins = "gpio57"; +- drive-strength = <2>; +- bias-pull-down; +- }; +-}; +- +-&qspi_cs0 { +- pinconf { +- pins = "gpio68"; +- bias-disable; +- }; +-}; +- +-&qspi_clk { +- pinconf { +- pins = "gpio63"; +- drive-strength = <8>; +- bias-disable; +- }; +-}; +- +-&qspi_data01 { +- pinconf { +- pins = "gpio64", "gpio65"; +- +- /* High-Z when no transfers; nice to park the lines */ +- bias-pull-up; +- }; +-}; +- +-&qup_i2c2_default { +- pinconf { +- pins = "gpio15", "gpio16"; +- drive-strength = <2>; +- +- /* Has external pullup */ +- bias-disable; +- }; +-}; +- +-&qup_i2c4_default { +- pinconf { +- pins = "gpio115", "gpio116"; +- drive-strength = <2>; +- +- /* Has external pullup */ +- bias-disable; +- }; +-}; +- +-&qup_i2c5_default { +- pinconf { +- pins = "gpio25", "gpio26"; +- drive-strength = <2>; +- +- /* Has external pullup */ +- bias-disable; +- }; +-}; +- +-&qup_i2c7_default { +- pinconf { +- pins = "gpio6", "gpio7"; +- drive-strength = <2>; +- +- /* Has external pullup */ +- bias-disable; +- }; +-}; +- +-&qup_i2c9_default { +- pinconf { +- pins = "gpio46", "gpio47"; +- drive-strength = <2>; +- +- /* Has external pullup */ +- bias-disable; +- }; +-}; +- +-&qup_spi0_cs_gpio { +- pinconf { +- pins = "gpio34", "gpio35", "gpio36", "gpio37"; +- drive-strength = <2>; +- bias-disable; +- }; +-}; +- +-&qup_spi6_cs_gpio { +- pinconf { +- pins = "gpio59", "gpio60", "gpio61", "gpio62"; +- drive-strength = <2>; +- bias-disable; +- }; +-}; +- +-&qup_spi10_cs_gpio { +- pinconf { +- pins = "gpio86", "gpio87", "gpio88", "gpio89"; +- drive-strength = <2>; +- bias-disable; +- }; +-}; +- +-&qup_uart3_default { +- pinconf-cts { +- /* +- * Configure a pull-down on CTS to match the pull of +- * the Bluetooth module. +- */ +- pins = "gpio38"; +- bias-pull-down; +- }; +- +- pinconf-rts-tx { +- /* We'll drive RTS and TX, so no pull */ +- pins = "gpio39", "gpio40"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- pinconf-rx { +- /* +- * Configure a pull-up on RX. This is needed to avoid +- * garbage data when the TX pin of the Bluetooth module is +- * in tri-state (module powered off or not driving the +- * signal yet). +- */ +- pins = "gpio41"; +- bias-pull-up; +- }; +-}; +- +-&qup_uart8_default { +- pinconf-tx { +- pins = "gpio44"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- pinconf-rx { +- pins = "gpio45"; +- drive-strength = <2>; +- bias-pull-up; +- }; +-}; +- +-&sec_mi2s_active { +- pinconf { +- pins = "gpio49", "gpio50", "gpio51"; +- drive-strength = <2>; +- bias-pull-down; +- }; +-}; +- +-/* PINCTRL - board-specific pinctrl */ +- +-&pm6150_gpio { +- status = "disabled"; /* No GPIOs are connected */ +-}; +- +-&pm6150l_gpio { +- gpio-line-names = "AP_SUSPEND", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- ""; +-}; +- +-&tlmm { +- /* +- * pinctrl settings for pins that have no real owners. +- */ +- pinctrl-names = "default"; +- pinctrl-0 = <&bios_flash_wp_l>, <&ap_suspend_l_neuter>; +- +- amp_en: amp-en { +- pinmux { +- pins = "gpio23"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio23"; +- bias-pull-down; +- }; +- }; +- +- ap_ec_int_l: ap-ec-int-l { +- pinmux { +- pins = "gpio94"; +- function = "gpio"; +- input-enable; +- }; +- +- pinconf { +- pins = "gpio94"; +- bias-pull-up; +- }; +- }; +- +- ap_edp_bklten: ap-edp-bklten { +- pinmux { +- pins = "gpio12"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio12"; +- drive-strength = <2>; +- bias-disable; +- +- /* Force backlight to be disabled to match state at boot. */ +- output-low; +- }; +- }; +- +- ap_suspend_l_neuter: ap-suspend-l-neuter { +- pinmux { +- pins = "gpio27"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio27"; +- bias-disable; +- }; +- }; +- +- bios_flash_wp_l: bios-flash-wp-l { +- pinmux { +- pins = "gpio66"; +- function = "gpio"; +- input-enable; +- }; +- +- pinconf { +- pins = "gpio66"; +- bias-disable; +- }; +- }; +- +- edp_brij_en: edp-brij-en { +- pinmux { +- pins = "gpio104"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio104"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- edp_brij_irq: edp-brij-irq { +- pinmux { +- pins = "gpio11"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio11"; +- drive-strength = <2>; +- bias-pull-down; +- }; +- }; +- +- en_pp3300_codec: en-pp3300-codec { +- pinmux { +- pins = "gpio83"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio83"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- en_pp3300_dx_edp: en-pp3300-dx-edp { +- pinmux { +- pins = "gpio30"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio30"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- en_pp3300_hub: en-pp3300-hub { +- pinmux { +- pins = "gpio84"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio84"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- fp_to_ap_irq_l: fp-to-ap-irq-l { +- pinmux { +- pins = "gpio4"; +- function = "gpio"; +- input-enable; +- }; +- +- pinconf { +- pins = "gpio4"; +- +- /* Has external pullup */ +- bias-disable; +- }; +- }; +- +- h1_ap_int_odl: h1-ap-int-odl { +- pinmux { +- pins = "gpio42"; +- function = "gpio"; +- input-enable; +- }; +- +- pinconf { +- pins = "gpio42"; +- bias-pull-up; +- }; +- }; +- +- hp_irq: hp-irq { +- pinmux { +- pins = "gpio28"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio28"; +- bias-pull-up; +- }; +- }; +- +- pen_irq_l: pen-irq-l { +- pinmux { +- pins = "gpio21"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio21"; +- +- /* Has external pullup */ +- bias-disable; +- }; +- }; +- +- pen_pdct_l: pen-pdct-l { +- pinmux { +- pins = "gpio52"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio52"; +- +- /* Has external pullup */ +- bias-disable; +- }; +- }; +- +- pen_rst_odl: pen-rst-odl { +- pinmux { +- pins = "gpio18"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio18"; +- bias-disable; +- drive-strength = <2>; +- +- /* +- * The pen driver doesn't currently support +- * driving this reset line. By specifying +- * output-high here we're relying on the fact +- * that this pin has a default pulldown at boot +- * (which makes sure the pen was in reset if it +- * was powered) and then we set it high here to +- * take it out of reset. Better would be if the +- * pen driver could control this and we could +- * remove "output-high" here. +- */ +- output-high; /* TODO: Remove this? */ +- }; +- }; +- +- p_sensor_int_l: p-sensor-int-l { +- pinmux { +- pins = "gpio24"; +- function = "gpio"; +- input-enable; +- }; +- +- pinconf { +- pins = "gpio24"; +- /* Has external pullup */ +- bias-disable; +- }; +- }; +- +- qup_spi0_cs_gpio_init_high: qup-spi0-cs-gpio-init-high { +- pinconf { +- pins = "gpio37"; +- output-high; +- }; +- }; +- +- qup_spi6_cs_gpio_init_high: qup-spi6-cs-gpio-init-high { +- pinconf { +- pins = "gpio62"; +- output-high; +- }; +- }; +- +- qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high { +- pinconf { +- pins = "gpio89"; +- output-high; +- }; +- }; +- +- qup_uart3_sleep: qup-uart3-sleep { +- pinmux { +- pins = "gpio38", "gpio39", +- "gpio40", "gpio41"; +- function = "gpio"; +- }; +- +- pinconf-cts { +- /* +- * Configure a pull-down on CTS to match the pull of +- * the Bluetooth module. +- */ +- pins = "gpio38"; +- bias-pull-down; +- }; +- +- pinconf-rts { +- /* +- * Configure pull-down on RTS. As RTS is active low +- * signal, pull it low to indicate the BT SoC that it +- * can wakeup the system anytime from suspend state by +- * pulling RX low (by sending wakeup bytes). +- */ +- pins = "gpio39"; +- bias-pull-down; +- }; +- +- pinconf-tx { +- /* +- * Configure pull-up on TX when it isn't actively driven +- * to prevent BT SoC from receiving garbage during sleep. +- */ +- pins = "gpio40"; +- bias-pull-up; +- }; +- +- pinconf-rx { +- /* +- * Configure a pull-up on RX. This is needed to avoid +- * garbage data when the TX pin of the Bluetooth module +- * is floating which may cause spurious wakeups. +- */ +- pins = "gpio41"; +- bias-pull-up; +- }; +- }; +- +- /* Named trackpad_int_1v8_odl on earlier revision schematics */ +- trackpad_int_1v8_odl: +- tp_int_odl: tp-int-odl { +- pinmux { +- pins = "gpio0"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio0"; +- +- /* Has external pullup */ +- bias-disable; +- }; +- }; +- +- ts_int_l: ts-int-l { +- pinmux { +- pins = "gpio9"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio9"; +- bias-pull-up; +- }; +- }; +- +- ts_reset_l: ts-reset-l { +- pinmux { +- pins = "gpio8"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio8"; +- bias-disable; +- drive-strength = <2>; +- }; +- }; +- +- sdc1_on: sdc1-on { +- pinconf-clk { +- pins = "sdc1_clk"; +- bias-disable; +- drive-strength = <16>; +- }; +- +- pinconf-cmd { +- pins = "sdc1_cmd"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- pinconf-data { +- pins = "sdc1_data"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- pinconf-rclk { +- pins = "sdc1_rclk"; +- bias-pull-down; +- }; +- }; +- +- sdc1_off: sdc1-off { +- pinconf-clk { +- pins = "sdc1_clk"; +- bias-disable; +- drive-strength = <2>; +- }; +- +- pinconf-cmd { +- pins = "sdc1_cmd"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- pinconf-data { +- pins = "sdc1_data"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- pinconf-rclk { +- pins = "sdc1_rclk"; +- bias-pull-down; +- }; +- }; +- +- sdc2_on: sdc2-on { +- pinconf-clk { +- pins = "sdc2_clk"; +- bias-disable; +- drive-strength = <16>; +- }; +- +- pinconf-cmd { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- pinconf-data { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- pinconf-sd-cd { +- pins = "gpio69"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +- +- sdc2_off: sdc2-off { +- pinconf-clk { +- pins = "sdc2_clk"; +- bias-disable; +- drive-strength = <2>; +- }; +- +- pinconf-cmd { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- pinconf-data { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- pinconf-sd-cd { +- pins = "gpio69"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7180.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sc7180.dtsi +deleted file mode 100644 +index 495c15deacb7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7180.dtsi ++++ /dev/null +@@ -1,4407 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * SC7180 SoC device tree source +- * +- * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&intc>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- chosen { }; +- +- aliases { +- mmc1 = &sdhc_1; +- mmc2 = &sdhc_2; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c7; +- i2c8 = &i2c8; +- i2c9 = &i2c9; +- i2c10 = &i2c10; +- i2c11 = &i2c11; +- spi0 = &spi0; +- spi1 = &spi1; +- spi3 = &spi3; +- spi5 = &spi5; +- spi6 = &spi6; +- spi8 = &spi8; +- spi10 = &spi10; +- spi11 = &spi11; +- }; +- +- clocks { +- xo_board: xo-board { +- compatible = "fixed-clock"; +- clock-frequency = <38400000>; +- #clock-cells = <0>; +- }; +- +- sleep_clk: sleep-clk { +- compatible = "fixed-clock"; +- clock-frequency = <32764>; +- #clock-cells = <0>; +- }; +- }; +- +- reserved_memory: reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- hyp_mem: memory@80000000 { +- reg = <0x0 0x80000000 0x0 0x600000>; +- no-map; +- }; +- +- xbl_mem: memory@80600000 { +- reg = <0x0 0x80600000 0x0 0x200000>; +- no-map; +- }; +- +- aop_mem: memory@80800000 { +- reg = <0x0 0x80800000 0x0 0x20000>; +- no-map; +- }; +- +- aop_cmd_db_mem: memory@80820000 { +- reg = <0x0 0x80820000 0x0 0x20000>; +- compatible = "qcom,cmd-db"; +- no-map; +- }; +- +- sec_apps_mem: memory@808ff000 { +- reg = <0x0 0x808ff000 0x0 0x1000>; +- no-map; +- }; +- +- smem_mem: memory@80900000 { +- reg = <0x0 0x80900000 0x0 0x200000>; +- no-map; +- }; +- +- tz_mem: memory@80b00000 { +- reg = <0x0 0x80b00000 0x0 0x3900000>; +- no-map; +- }; +- +- ipa_fw_mem: memory@8b700000 { +- reg = <0 0x8b700000 0 0x10000>; +- no-map; +- }; +- +- rmtfs_mem: memory@94600000 { +- compatible = "qcom,rmtfs-mem"; +- reg = <0x0 0x94600000 0x0 0x200000>; +- no-map; +- +- qcom,client-id = <1>; +- qcom,vmid = <15>; +- }; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- CPU0: cpu@0 { +- device_type = "cpu"; +- compatible = "qcom,kryo468"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- cpu-idle-states = <&LITTLE_CPU_SLEEP_0 +- &LITTLE_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <415>; +- dynamic-power-coefficient = <137>; +- operating-points-v2 = <&cpu0_opp_table>; +- interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- next-level-cache = <&L2_0>; +- #cooling-cells = <2>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- L2_0: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- L3_0: l3-cache { +- compatible = "cache"; +- }; +- }; +- }; +- +- CPU1: cpu@100 { +- device_type = "cpu"; +- compatible = "qcom,kryo468"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- cpu-idle-states = <&LITTLE_CPU_SLEEP_0 +- &LITTLE_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <415>; +- dynamic-power-coefficient = <137>; +- next-level-cache = <&L2_100>; +- operating-points-v2 = <&cpu0_opp_table>; +- interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- #cooling-cells = <2>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- L2_100: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU2: cpu@200 { +- device_type = "cpu"; +- compatible = "qcom,kryo468"; +- reg = <0x0 0x200>; +- enable-method = "psci"; +- cpu-idle-states = <&LITTLE_CPU_SLEEP_0 +- &LITTLE_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <415>; +- dynamic-power-coefficient = <137>; +- next-level-cache = <&L2_200>; +- operating-points-v2 = <&cpu0_opp_table>; +- interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- #cooling-cells = <2>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- L2_200: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU3: cpu@300 { +- device_type = "cpu"; +- compatible = "qcom,kryo468"; +- reg = <0x0 0x300>; +- enable-method = "psci"; +- cpu-idle-states = <&LITTLE_CPU_SLEEP_0 +- &LITTLE_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <415>; +- dynamic-power-coefficient = <137>; +- next-level-cache = <&L2_300>; +- operating-points-v2 = <&cpu0_opp_table>; +- interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- #cooling-cells = <2>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- L2_300: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU4: cpu@400 { +- device_type = "cpu"; +- compatible = "qcom,kryo468"; +- reg = <0x0 0x400>; +- enable-method = "psci"; +- cpu-idle-states = <&LITTLE_CPU_SLEEP_0 +- &LITTLE_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <415>; +- dynamic-power-coefficient = <137>; +- next-level-cache = <&L2_400>; +- operating-points-v2 = <&cpu0_opp_table>; +- interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- #cooling-cells = <2>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- L2_400: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU5: cpu@500 { +- device_type = "cpu"; +- compatible = "qcom,kryo468"; +- reg = <0x0 0x500>; +- enable-method = "psci"; +- cpu-idle-states = <&LITTLE_CPU_SLEEP_0 +- &LITTLE_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <415>; +- dynamic-power-coefficient = <137>; +- next-level-cache = <&L2_500>; +- operating-points-v2 = <&cpu0_opp_table>; +- interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- #cooling-cells = <2>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- L2_500: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU6: cpu@600 { +- device_type = "cpu"; +- compatible = "qcom,kryo468"; +- reg = <0x0 0x600>; +- enable-method = "psci"; +- cpu-idle-states = <&BIG_CPU_SLEEP_0 +- &BIG_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <480>; +- next-level-cache = <&L2_600>; +- operating-points-v2 = <&cpu6_opp_table>; +- interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- #cooling-cells = <2>; +- qcom,freq-domain = <&cpufreq_hw 1>; +- L2_600: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU7: cpu@700 { +- device_type = "cpu"; +- compatible = "qcom,kryo468"; +- reg = <0x0 0x700>; +- enable-method = "psci"; +- cpu-idle-states = <&BIG_CPU_SLEEP_0 +- &BIG_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <480>; +- next-level-cache = <&L2_700>; +- operating-points-v2 = <&cpu6_opp_table>; +- interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- #cooling-cells = <2>; +- qcom,freq-domain = <&cpufreq_hw 1>; +- L2_700: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&CPU0>; +- }; +- +- core1 { +- cpu = <&CPU1>; +- }; +- +- core2 { +- cpu = <&CPU2>; +- }; +- +- core3 { +- cpu = <&CPU3>; +- }; +- +- core4 { +- cpu = <&CPU4>; +- }; +- +- core5 { +- cpu = <&CPU5>; +- }; +- +- core6 { +- cpu = <&CPU6>; +- }; +- +- core7 { +- cpu = <&CPU7>; +- }; +- }; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "little-power-down"; +- arm,psci-suspend-param = <0x40000003>; +- entry-latency-us = <549>; +- exit-latency-us = <901>; +- min-residency-us = <1774>; +- local-timer-stop; +- }; +- +- LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { +- compatible = "arm,idle-state"; +- idle-state-name = "little-rail-power-down"; +- arm,psci-suspend-param = <0x40000004>; +- entry-latency-us = <702>; +- exit-latency-us = <915>; +- min-residency-us = <4001>; +- local-timer-stop; +- }; +- +- BIG_CPU_SLEEP_0: cpu-sleep-1-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "big-power-down"; +- arm,psci-suspend-param = <0x40000003>; +- entry-latency-us = <523>; +- exit-latency-us = <1244>; +- min-residency-us = <2207>; +- local-timer-stop; +- }; +- +- BIG_CPU_SLEEP_1: cpu-sleep-1-1 { +- compatible = "arm,idle-state"; +- idle-state-name = "big-rail-power-down"; +- arm,psci-suspend-param = <0x40000004>; +- entry-latency-us = <526>; +- exit-latency-us = <1854>; +- min-residency-us = <5555>; +- local-timer-stop; +- }; +- +- CLUSTER_SLEEP_0: cluster-sleep-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "cluster-power-down"; +- arm,psci-suspend-param = <0x40003444>; +- entry-latency-us = <3263>; +- exit-latency-us = <6562>; +- min-residency-us = <9926>; +- local-timer-stop; +- }; +- }; +- }; +- +- cpu0_opp_table: cpu0_opp_table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- cpu0_opp1: opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-peak-kBps = <1200000 4800000>; +- }; +- +- cpu0_opp2: opp-576000000 { +- opp-hz = /bits/ 64 <576000000>; +- opp-peak-kBps = <1200000 4800000>; +- }; +- +- cpu0_opp3: opp-768000000 { +- opp-hz = /bits/ 64 <768000000>; +- opp-peak-kBps = <1200000 4800000>; +- }; +- +- cpu0_opp4: opp-1017600000 { +- opp-hz = /bits/ 64 <1017600000>; +- opp-peak-kBps = <1804000 8908800>; +- }; +- +- cpu0_opp5: opp-1248000000 { +- opp-hz = /bits/ 64 <1248000000>; +- opp-peak-kBps = <2188000 12902400>; +- }; +- +- cpu0_opp6: opp-1324800000 { +- opp-hz = /bits/ 64 <1324800000>; +- opp-peak-kBps = <2188000 12902400>; +- }; +- +- cpu0_opp7: opp-1516800000 { +- opp-hz = /bits/ 64 <1516800000>; +- opp-peak-kBps = <3072000 15052800>; +- }; +- +- cpu0_opp8: opp-1612800000 { +- opp-hz = /bits/ 64 <1612800000>; +- opp-peak-kBps = <3072000 15052800>; +- }; +- +- cpu0_opp9: opp-1708800000 { +- opp-hz = /bits/ 64 <1708800000>; +- opp-peak-kBps = <3072000 15052800>; +- }; +- +- cpu0_opp10: opp-1804800000 { +- opp-hz = /bits/ 64 <1804800000>; +- opp-peak-kBps = <4068000 22425600>; +- }; +- }; +- +- cpu6_opp_table: cpu6_opp_table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- cpu6_opp1: opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-peak-kBps = <2188000 8908800>; +- }; +- +- cpu6_opp2: opp-652800000 { +- opp-hz = /bits/ 64 <652800000>; +- opp-peak-kBps = <2188000 8908800>; +- }; +- +- cpu6_opp3: opp-825600000 { +- opp-hz = /bits/ 64 <825600000>; +- opp-peak-kBps = <2188000 8908800>; +- }; +- +- cpu6_opp4: opp-979200000 { +- opp-hz = /bits/ 64 <979200000>; +- opp-peak-kBps = <2188000 8908800>; +- }; +- +- cpu6_opp5: opp-1113600000 { +- opp-hz = /bits/ 64 <1113600000>; +- opp-peak-kBps = <2188000 8908800>; +- }; +- +- cpu6_opp6: opp-1267200000 { +- opp-hz = /bits/ 64 <1267200000>; +- opp-peak-kBps = <4068000 12902400>; +- }; +- +- cpu6_opp7: opp-1555200000 { +- opp-hz = /bits/ 64 <1555200000>; +- opp-peak-kBps = <4068000 15052800>; +- }; +- +- cpu6_opp8: opp-1708800000 { +- opp-hz = /bits/ 64 <1708800000>; +- opp-peak-kBps = <6220000 19353600>; +- }; +- +- cpu6_opp9: opp-1843200000 { +- opp-hz = /bits/ 64 <1843200000>; +- opp-peak-kBps = <6220000 19353600>; +- }; +- +- cpu6_opp10: opp-1900800000 { +- opp-hz = /bits/ 64 <1900800000>; +- opp-peak-kBps = <6220000 22425600>; +- }; +- +- cpu6_opp11: opp-1996800000 { +- opp-hz = /bits/ 64 <1996800000>; +- opp-peak-kBps = <6220000 22425600>; +- }; +- +- cpu6_opp12: opp-2112000000 { +- opp-hz = /bits/ 64 <2112000000>; +- opp-peak-kBps = <6220000 22425600>; +- }; +- +- cpu6_opp13: opp-2208000000 { +- opp-hz = /bits/ 64 <2208000000>; +- opp-peak-kBps = <7216000 22425600>; +- }; +- +- cpu6_opp14: opp-2323200000 { +- opp-hz = /bits/ 64 <2323200000>; +- opp-peak-kBps = <7216000 22425600>; +- }; +- +- cpu6_opp15: opp-2400000000 { +- opp-hz = /bits/ 64 <2400000000>; +- opp-peak-kBps = <8532000 23347200>; +- }; +- +- cpu6_opp16: opp-2553600000 { +- opp-hz = /bits/ 64 <2553600000>; +- opp-peak-kBps = <8532000 23347200>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- /* We expect the bootloader to fill in the size */ +- reg = <0 0x80000000 0 0>; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = ; +- }; +- +- firmware { +- scm { +- compatible = "qcom,scm-sc7180", "qcom,scm"; +- }; +- }; +- +- tcsr_mutex: hwlock { +- compatible = "qcom,tcsr-mutex"; +- syscon = <&tcsr_mutex_regs 0 0x1000>; +- #hwlock-cells = <1>; +- }; +- +- smem { +- compatible = "qcom,smem"; +- memory-region = <&smem_mem>; +- hwlocks = <&tcsr_mutex 3>; +- }; +- +- smp2p-cdsp { +- compatible = "qcom,smp2p"; +- qcom,smem = <94>, <432>; +- +- interrupts = ; +- +- mboxes = <&apss_shared 6>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <5>; +- +- cdsp_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- cdsp_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-lpass { +- compatible = "qcom,smp2p"; +- qcom,smem = <443>, <429>; +- +- interrupts = ; +- +- mboxes = <&apss_shared 10>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <2>; +- +- adsp_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- adsp_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-mpss { +- compatible = "qcom,smp2p"; +- qcom,smem = <435>, <428>; +- interrupts = ; +- mboxes = <&apss_shared 14>; +- qcom,local-pid = <0>; +- qcom,remote-pid = <1>; +- +- modem_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- modem_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- ipa_smp2p_out: ipa-ap-to-modem { +- qcom,entry-name = "ipa"; +- #qcom,smem-state-cells = <1>; +- }; +- +- ipa_smp2p_in: ipa-modem-to-ap { +- qcom,entry-name = "ipa"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- soc: soc@0 { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0 0 0 0 0x10 0>; +- dma-ranges = <0 0 0 0 0x10 0>; +- compatible = "simple-bus"; +- +- gcc: clock-controller@100000 { +- compatible = "qcom,gcc-sc7180"; +- reg = <0 0x00100000 0 0x1f0000>; +- clocks = <&rpmhcc RPMH_CXO_CLK>, +- <&rpmhcc RPMH_CXO_CLK_A>, +- <&sleep_clk>; +- clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- }; +- +- qfprom: efuse@784000 { +- compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; +- reg = <0 0x00784000 0 0x7a0>, +- <0 0x00780000 0 0x7a0>, +- <0 0x00782000 0 0x100>, +- <0 0x00786000 0 0x1fff>; +- +- clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; +- clock-names = "core"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- qusb2p_hstx_trim: hstx-trim-primary@25b { +- reg = <0x25b 0x1>; +- bits = <1 3>; +- }; +- +- gpu_speed_bin: gpu_speed_bin@1d2 { +- reg = <0x1d2 0x2>; +- bits = <5 8>; +- }; +- }; +- +- sdhc_1: sdhci@7c4000 { +- compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; +- reg = <0 0x7c4000 0 0x1000>, +- <0 0x07c5000 0 0x1000>; +- reg-names = "hc", "cqhci"; +- +- iommus = <&apps_smmu 0x60 0x0>; +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- +- clocks = <&gcc GCC_SDCC1_APPS_CLK>, +- <&gcc GCC_SDCC1_AHB_CLK>, +- <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "core", "iface", "xo"; +- interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; +- interconnect-names = "sdhc-ddr","cpu-sdhc"; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&sdhc1_opp_table>; +- +- bus-width = <8>; +- non-removable; +- supports-cqe; +- +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- +- status = "disabled"; +- +- sdhc1_opp_table: sdhc1-opp-table { +- compatible = "operating-points-v2"; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- opp-peak-kBps = <1800000 600000>; +- opp-avg-kBps = <100000 0>; +- }; +- +- opp-384000000 { +- opp-hz = /bits/ 64 <384000000>; +- required-opps = <&rpmhpd_opp_nom>; +- opp-peak-kBps = <5400000 1600000>; +- opp-avg-kBps = <390000 0>; +- }; +- }; +- }; +- +- qup_opp_table: qup-opp-table { +- compatible = "operating-points-v2"; +- +- opp-75000000 { +- opp-hz = /bits/ 64 <75000000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- }; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- required-opps = <&rpmhpd_opp_svs>; +- }; +- +- opp-128000000 { +- opp-hz = /bits/ 64 <128000000>; +- required-opps = <&rpmhpd_opp_nom>; +- }; +- }; +- +- qupv3_id_0: geniqup@8c0000 { +- compatible = "qcom,geni-se-qup"; +- reg = <0 0x008c0000 0 0x6000>; +- clock-names = "m-ahb", "s-ahb"; +- clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, +- <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- iommus = <&apps_smmu 0x43 0x0>; +- status = "disabled"; +- +- i2c0: i2c@880000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00880000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c0_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, +- <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", +- "qup-memory"; +- power-domains = <&rpmhpd SC7180_CX>; +- required-opps = <&rpmhpd_opp_low_svs>; +- status = "disabled"; +- }; +- +- spi0: spi@880000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00880000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi0_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart0: serial@880000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00880000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart0_default>; +- interrupts = ; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c1: i2c@884000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00884000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c1_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, +- <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", +- "qup-memory"; +- power-domains = <&rpmhpd SC7180_CX>; +- required-opps = <&rpmhpd_opp_low_svs>; +- status = "disabled"; +- }; +- +- spi1: spi@884000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00884000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi1_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart1: serial@884000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00884000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart1_default>; +- interrupts = ; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c2: i2c@888000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00888000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c2_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, +- <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", +- "qup-memory"; +- power-domains = <&rpmhpd SC7180_CX>; +- required-opps = <&rpmhpd_opp_low_svs>; +- status = "disabled"; +- }; +- +- uart2: serial@888000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00888000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart2_default>; +- interrupts = ; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c3: i2c@88c000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x0088c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c3_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, +- <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", +- "qup-memory"; +- power-domains = <&rpmhpd SC7180_CX>; +- required-opps = <&rpmhpd_opp_low_svs>; +- status = "disabled"; +- }; +- +- spi3: spi@88c000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x0088c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi3_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart3: serial@88c000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x0088c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart3_default>; +- interrupts = ; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c4: i2c@890000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00890000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c4_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, +- <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", +- "qup-memory"; +- power-domains = <&rpmhpd SC7180_CX>; +- required-opps = <&rpmhpd_opp_low_svs>; +- status = "disabled"; +- }; +- +- uart4: serial@890000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00890000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart4_default>; +- interrupts = ; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c5: i2c@894000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00894000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c5_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, +- <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", +- "qup-memory"; +- power-domains = <&rpmhpd SC7180_CX>; +- required-opps = <&rpmhpd_opp_low_svs>; +- status = "disabled"; +- }; +- +- spi5: spi@894000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00894000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi5_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart5: serial@894000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00894000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart5_default>; +- interrupts = ; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- }; +- +- qupv3_id_1: geniqup@ac0000 { +- compatible = "qcom,geni-se-qup"; +- reg = <0 0x00ac0000 0 0x6000>; +- clock-names = "m-ahb", "s-ahb"; +- clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, +- <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- iommus = <&apps_smmu 0x4c3 0x0>; +- status = "disabled"; +- +- i2c6: i2c@a80000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a80000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c6_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, +- <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", +- "qup-memory"; +- power-domains = <&rpmhpd SC7180_CX>; +- required-opps = <&rpmhpd_opp_low_svs>; +- status = "disabled"; +- }; +- +- spi6: spi@a80000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00a80000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi6_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart6: serial@a80000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00a80000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart6_default>; +- interrupts = ; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c7: i2c@a84000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a84000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c7_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, +- <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", +- "qup-memory"; +- power-domains = <&rpmhpd SC7180_CX>; +- required-opps = <&rpmhpd_opp_low_svs>; +- status = "disabled"; +- }; +- +- uart7: serial@a84000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00a84000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart7_default>; +- interrupts = ; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c8: i2c@a88000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a88000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c8_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, +- <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", +- "qup-memory"; +- power-domains = <&rpmhpd SC7180_CX>; +- required-opps = <&rpmhpd_opp_low_svs>; +- status = "disabled"; +- }; +- +- spi8: spi@a88000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00a88000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi8_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart8: serial@a88000 { +- compatible = "qcom,geni-debug-uart"; +- reg = <0 0x00a88000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart8_default>; +- interrupts = ; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c9: i2c@a8c000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a8c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c9_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, +- <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", +- "qup-memory"; +- power-domains = <&rpmhpd SC7180_CX>; +- required-opps = <&rpmhpd_opp_low_svs>; +- status = "disabled"; +- }; +- +- uart9: serial@a8c000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00a8c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart9_default>; +- interrupts = ; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c10: i2c@a90000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a90000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c10_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, +- <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", +- "qup-memory"; +- power-domains = <&rpmhpd SC7180_CX>; +- required-opps = <&rpmhpd_opp_low_svs>; +- status = "disabled"; +- }; +- +- spi10: spi@a90000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00a90000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi10_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart10: serial@a90000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00a90000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart10_default>; +- interrupts = ; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c11: i2c@a94000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a94000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c11_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, +- <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", +- "qup-memory"; +- power-domains = <&rpmhpd SC7180_CX>; +- required-opps = <&rpmhpd_opp_low_svs>; +- status = "disabled"; +- }; +- +- spi11: spi@a94000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00a94000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi11_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart11: serial@a94000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00a94000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart11_default>; +- interrupts = ; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- }; +- +- config_noc: interconnect@1500000 { +- compatible = "qcom,sc7180-config-noc"; +- reg = <0 0x01500000 0 0x28000>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- system_noc: interconnect@1620000 { +- compatible = "qcom,sc7180-system-noc"; +- reg = <0 0x01620000 0 0x17080>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- mc_virt: interconnect@1638000 { +- compatible = "qcom,sc7180-mc-virt"; +- reg = <0 0x01638000 0 0x1000>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- qup_virt: interconnect@1650000 { +- compatible = "qcom,sc7180-qup-virt"; +- reg = <0 0x01650000 0 0x1000>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- aggre1_noc: interconnect@16e0000 { +- compatible = "qcom,sc7180-aggre1-noc"; +- reg = <0 0x016e0000 0 0x15080>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- aggre2_noc: interconnect@1705000 { +- compatible = "qcom,sc7180-aggre2-noc"; +- reg = <0 0x01705000 0 0x9000>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- compute_noc: interconnect@170e000 { +- compatible = "qcom,sc7180-compute-noc"; +- reg = <0 0x0170e000 0 0x6000>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- mmss_noc: interconnect@1740000 { +- compatible = "qcom,sc7180-mmss-noc"; +- reg = <0 0x01740000 0 0x1c100>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- ipa_virt: interconnect@1e00000 { +- compatible = "qcom,sc7180-ipa-virt"; +- reg = <0 0x01e00000 0 0x1000>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- ipa: ipa@1e40000 { +- compatible = "qcom,sc7180-ipa"; +- +- iommus = <&apps_smmu 0x440 0x0>, +- <&apps_smmu 0x442 0x0>; +- reg = <0 0x1e40000 0 0x7000>, +- <0 0x1e47000 0 0x2000>, +- <0 0x1e04000 0 0x2c000>; +- reg-names = "ipa-reg", +- "ipa-shared", +- "gsi"; +- +- interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, +- <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, +- <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "ipa", +- "gsi", +- "ipa-clock-query", +- "ipa-setup-ready"; +- +- clocks = <&rpmhcc RPMH_IPA_CLK>; +- clock-names = "core"; +- +- interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, +- <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; +- interconnect-names = "memory", +- "imem", +- "config"; +- +- qcom,smem-states = <&ipa_smp2p_out 0>, +- <&ipa_smp2p_out 1>; +- qcom,smem-state-names = "ipa-clock-enabled-valid", +- "ipa-clock-enabled"; +- +- status = "disabled"; +- }; +- +- tcsr_mutex_regs: syscon@1f40000 { +- compatible = "syscon"; +- reg = <0 0x01f40000 0 0x40000>; +- }; +- +- tcsr_regs: syscon@1fc0000 { +- compatible = "syscon"; +- reg = <0 0x01fc0000 0 0x40000>; +- }; +- +- tlmm: pinctrl@3500000 { +- compatible = "qcom,sc7180-pinctrl"; +- reg = <0 0x03500000 0 0x300000>, +- <0 0x03900000 0 0x300000>, +- <0 0x03d00000 0 0x300000>; +- reg-names = "west", "north", "south"; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&tlmm 0 0 120>; +- wakeup-parent = <&pdc>; +- +- dp_hot_plug_det: dp-hot-plug-det { +- pinmux { +- pins = "gpio117"; +- function = "dp_hot"; +- }; +- }; +- +- qspi_clk: qspi-clk { +- pinmux { +- pins = "gpio63"; +- function = "qspi_clk"; +- }; +- }; +- +- qspi_cs0: qspi-cs0 { +- pinmux { +- pins = "gpio68"; +- function = "qspi_cs"; +- }; +- }; +- +- qspi_cs1: qspi-cs1 { +- pinmux { +- pins = "gpio72"; +- function = "qspi_cs"; +- }; +- }; +- +- qspi_data01: qspi-data01 { +- pinmux-data { +- pins = "gpio64", "gpio65"; +- function = "qspi_data"; +- }; +- }; +- +- qspi_data12: qspi-data12 { +- pinmux-data { +- pins = "gpio66", "gpio67"; +- function = "qspi_data"; +- }; +- }; +- +- qup_i2c0_default: qup-i2c0-default { +- pinmux { +- pins = "gpio34", "gpio35"; +- function = "qup00"; +- }; +- }; +- +- qup_i2c1_default: qup-i2c1-default { +- pinmux { +- pins = "gpio0", "gpio1"; +- function = "qup01"; +- }; +- }; +- +- qup_i2c2_default: qup-i2c2-default { +- pinmux { +- pins = "gpio15", "gpio16"; +- function = "qup02_i2c"; +- }; +- }; +- +- qup_i2c3_default: qup-i2c3-default { +- pinmux { +- pins = "gpio38", "gpio39"; +- function = "qup03"; +- }; +- }; +- +- qup_i2c4_default: qup-i2c4-default { +- pinmux { +- pins = "gpio115", "gpio116"; +- function = "qup04_i2c"; +- }; +- }; +- +- qup_i2c5_default: qup-i2c5-default { +- pinmux { +- pins = "gpio25", "gpio26"; +- function = "qup05"; +- }; +- }; +- +- qup_i2c6_default: qup-i2c6-default { +- pinmux { +- pins = "gpio59", "gpio60"; +- function = "qup10"; +- }; +- }; +- +- qup_i2c7_default: qup-i2c7-default { +- pinmux { +- pins = "gpio6", "gpio7"; +- function = "qup11_i2c"; +- }; +- }; +- +- qup_i2c8_default: qup-i2c8-default { +- pinmux { +- pins = "gpio42", "gpio43"; +- function = "qup12"; +- }; +- }; +- +- qup_i2c9_default: qup-i2c9-default { +- pinmux { +- pins = "gpio46", "gpio47"; +- function = "qup13_i2c"; +- }; +- }; +- +- qup_i2c10_default: qup-i2c10-default { +- pinmux { +- pins = "gpio86", "gpio87"; +- function = "qup14"; +- }; +- }; +- +- qup_i2c11_default: qup-i2c11-default { +- pinmux { +- pins = "gpio53", "gpio54"; +- function = "qup15"; +- }; +- }; +- +- qup_spi0_default: qup-spi0-default { +- pinmux { +- pins = "gpio34", "gpio35", +- "gpio36", "gpio37"; +- function = "qup00"; +- }; +- }; +- +- qup_spi0_cs_gpio: qup-spi0-cs-gpio { +- pinmux { +- pins = "gpio34", "gpio35", +- "gpio36"; +- function = "qup00"; +- }; +- +- pinmux-cs { +- pins = "gpio37"; +- function = "gpio"; +- }; +- }; +- +- qup_spi1_default: qup-spi1-default { +- pinmux { +- pins = "gpio0", "gpio1", +- "gpio2", "gpio3"; +- function = "qup01"; +- }; +- }; +- +- qup_spi1_cs_gpio: qup-spi1-cs-gpio { +- pinmux { +- pins = "gpio0", "gpio1", +- "gpio2"; +- function = "qup01"; +- }; +- +- pinmux-cs { +- pins = "gpio3"; +- function = "gpio"; +- }; +- }; +- +- qup_spi3_default: qup-spi3-default { +- pinmux { +- pins = "gpio38", "gpio39", +- "gpio40", "gpio41"; +- function = "qup03"; +- }; +- }; +- +- qup_spi3_cs_gpio: qup-spi3-cs-gpio { +- pinmux { +- pins = "gpio38", "gpio39", +- "gpio40"; +- function = "qup03"; +- }; +- +- pinmux-cs { +- pins = "gpio41"; +- function = "gpio"; +- }; +- }; +- +- qup_spi5_default: qup-spi5-default { +- pinmux { +- pins = "gpio25", "gpio26", +- "gpio27", "gpio28"; +- function = "qup05"; +- }; +- }; +- +- qup_spi5_cs_gpio: qup-spi5-cs-gpio { +- pinmux { +- pins = "gpio25", "gpio26", +- "gpio27"; +- function = "qup05"; +- }; +- +- pinmux-cs { +- pins = "gpio28"; +- function = "gpio"; +- }; +- }; +- +- qup_spi6_default: qup-spi6-default { +- pinmux { +- pins = "gpio59", "gpio60", +- "gpio61", "gpio62"; +- function = "qup10"; +- }; +- }; +- +- qup_spi6_cs_gpio: qup-spi6-cs-gpio { +- pinmux { +- pins = "gpio59", "gpio60", +- "gpio61"; +- function = "qup10"; +- }; +- +- pinmux-cs { +- pins = "gpio62"; +- function = "gpio"; +- }; +- }; +- +- qup_spi8_default: qup-spi8-default { +- pinmux { +- pins = "gpio42", "gpio43", +- "gpio44", "gpio45"; +- function = "qup12"; +- }; +- }; +- +- qup_spi8_cs_gpio: qup-spi8-cs-gpio { +- pinmux { +- pins = "gpio42", "gpio43", +- "gpio44"; +- function = "qup12"; +- }; +- +- pinmux-cs { +- pins = "gpio45"; +- function = "gpio"; +- }; +- }; +- +- qup_spi10_default: qup-spi10-default { +- pinmux { +- pins = "gpio86", "gpio87", +- "gpio88", "gpio89"; +- function = "qup14"; +- }; +- }; +- +- qup_spi10_cs_gpio: qup-spi10-cs-gpio { +- pinmux { +- pins = "gpio86", "gpio87", +- "gpio88"; +- function = "qup14"; +- }; +- +- pinmux-cs { +- pins = "gpio89"; +- function = "gpio"; +- }; +- }; +- +- qup_spi11_default: qup-spi11-default { +- pinmux { +- pins = "gpio53", "gpio54", +- "gpio55", "gpio56"; +- function = "qup15"; +- }; +- }; +- +- qup_spi11_cs_gpio: qup-spi11-cs-gpio { +- pinmux { +- pins = "gpio53", "gpio54", +- "gpio55"; +- function = "qup15"; +- }; +- +- pinmux-cs { +- pins = "gpio56"; +- function = "gpio"; +- }; +- }; +- +- qup_uart0_default: qup-uart0-default { +- pinmux { +- pins = "gpio34", "gpio35", +- "gpio36", "gpio37"; +- function = "qup00"; +- }; +- }; +- +- qup_uart1_default: qup-uart1-default { +- pinmux { +- pins = "gpio0", "gpio1", +- "gpio2", "gpio3"; +- function = "qup01"; +- }; +- }; +- +- qup_uart2_default: qup-uart2-default { +- pinmux { +- pins = "gpio15", "gpio16"; +- function = "qup02_uart"; +- }; +- }; +- +- qup_uart3_default: qup-uart3-default { +- pinmux { +- pins = "gpio38", "gpio39", +- "gpio40", "gpio41"; +- function = "qup03"; +- }; +- }; +- +- qup_uart4_default: qup-uart4-default { +- pinmux { +- pins = "gpio115", "gpio116"; +- function = "qup04_uart"; +- }; +- }; +- +- qup_uart5_default: qup-uart5-default { +- pinmux { +- pins = "gpio25", "gpio26", +- "gpio27", "gpio28"; +- function = "qup05"; +- }; +- }; +- +- qup_uart6_default: qup-uart6-default { +- pinmux { +- pins = "gpio59", "gpio60", +- "gpio61", "gpio62"; +- function = "qup10"; +- }; +- }; +- +- qup_uart7_default: qup-uart7-default { +- pinmux { +- pins = "gpio6", "gpio7"; +- function = "qup11_uart"; +- }; +- }; +- +- qup_uart8_default: qup-uart8-default { +- pinmux { +- pins = "gpio44", "gpio45"; +- function = "qup12"; +- }; +- }; +- +- qup_uart9_default: qup-uart9-default { +- pinmux { +- pins = "gpio46", "gpio47"; +- function = "qup13_uart"; +- }; +- }; +- +- qup_uart10_default: qup-uart10-default { +- pinmux { +- pins = "gpio86", "gpio87", +- "gpio88", "gpio89"; +- function = "qup14"; +- }; +- }; +- +- qup_uart11_default: qup-uart11-default { +- pinmux { +- pins = "gpio53", "gpio54", +- "gpio55", "gpio56"; +- function = "qup15"; +- }; +- }; +- +- sec_mi2s_active: sec-mi2s-active { +- pinmux { +- pins = "gpio49", "gpio50", "gpio51"; +- function = "mi2s_1"; +- }; +- }; +- +- pri_mi2s_active: pri-mi2s-active { +- pinmux { +- pins = "gpio53", "gpio54", "gpio55", "gpio56"; +- function = "mi2s_0"; +- }; +- }; +- +- pri_mi2s_mclk_active: pri-mi2s-mclk-active { +- pinmux { +- pins = "gpio57"; +- function = "lpass_ext"; +- }; +- }; +- }; +- +- remoteproc_mpss: remoteproc@4080000 { +- compatible = "qcom,sc7180-mpss-pas"; +- reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; +- reg-names = "qdsp6", "rmb"; +- +- interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", "handover", +- "stop-ack", "shutdown-ack"; +- +- clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, +- <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, +- <&gcc GCC_MSS_NAV_AXI_CLK>, +- <&gcc GCC_MSS_SNOC_AXI_CLK>, +- <&gcc GCC_MSS_MFAB_AXIS_CLK>, +- <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "iface", "bus", "nav", "snoc_axi", +- "mnoc_axi", "xo"; +- +- power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, +- <&rpmhpd SC7180_CX>, +- <&rpmhpd SC7180_MX>, +- <&rpmhpd SC7180_MSS>; +- power-domain-names = "load_state", "cx", "mx", "mss"; +- +- memory-region = <&mpss_mem>; +- +- qcom,smem-states = <&modem_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- resets = <&aoss_reset AOSS_CC_MSS_RESTART>, +- <&pdc_reset PDC_MODEM_SYNC_RESET>; +- reset-names = "mss_restart", "pdc_reset"; +- +- qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; +- qcom,spare-regs = <&tcsr_regs 0xb3e4>; +- +- status = "disabled"; +- +- glink-edge { +- interrupts = ; +- label = "modem"; +- qcom,remote-pid = <1>; +- mboxes = <&apss_shared 12>; +- }; +- }; +- +- gpu: gpu@5000000 { +- compatible = "qcom,adreno-618.0", "qcom,adreno"; +- #stream-id-cells = <16>; +- reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, +- <0 0x05061000 0 0x800>; +- reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; +- interrupts = ; +- iommus = <&adreno_smmu 0>; +- operating-points-v2 = <&gpu_opp_table>; +- qcom,gmu = <&gmu>; +- +- #cooling-cells = <2>; +- +- nvmem-cells = <&gpu_speed_bin>; +- nvmem-cell-names = "speed_bin"; +- +- interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; +- interconnect-names = "gfx-mem"; +- +- gpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-825000000 { +- opp-hz = /bits/ 64 <825000000>; +- opp-level = ; +- opp-peak-kBps = <8532000>; +- opp-supported-hw = <0x04>; +- }; +- +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-level = ; +- opp-peak-kBps = <8532000>; +- opp-supported-hw = <0x07>; +- }; +- +- opp-650000000 { +- opp-hz = /bits/ 64 <650000000>; +- opp-level = ; +- opp-peak-kBps = <7216000>; +- opp-supported-hw = <0x07>; +- }; +- +- opp-565000000 { +- opp-hz = /bits/ 64 <565000000>; +- opp-level = ; +- opp-peak-kBps = <5412000>; +- opp-supported-hw = <0x07>; +- }; +- +- opp-430000000 { +- opp-hz = /bits/ 64 <430000000>; +- opp-level = ; +- opp-peak-kBps = <5412000>; +- opp-supported-hw = <0x07>; +- }; +- +- opp-355000000 { +- opp-hz = /bits/ 64 <355000000>; +- opp-level = ; +- opp-peak-kBps = <3072000>; +- opp-supported-hw = <0x07>; +- }; +- +- opp-267000000 { +- opp-hz = /bits/ 64 <267000000>; +- opp-level = ; +- opp-peak-kBps = <3072000>; +- opp-supported-hw = <0x07>; +- }; +- +- opp-180000000 { +- opp-hz = /bits/ 64 <180000000>; +- opp-level = ; +- opp-peak-kBps = <1804000>; +- opp-supported-hw = <0x07>; +- }; +- }; +- }; +- +- adreno_smmu: iommu@5040000 { +- compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; +- reg = <0 0x05040000 0 0x10000>; +- #iommu-cells = <1>; +- #global-interrupts = <2>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- +- clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, +- <&gcc GCC_GPU_CFG_AHB_CLK>; +- clock-names = "bus", "iface"; +- +- power-domains = <&gpucc CX_GDSC>; +- }; +- +- gmu: gmu@506a000 { +- compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; +- reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, +- <0 0x0b490000 0 0x10000>; +- reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; +- interrupts = , +- ; +- interrupt-names = "hfi", "gmu"; +- clocks = <&gpucc GPU_CC_CX_GMU_CLK>, +- <&gpucc GPU_CC_CXO_CLK>, +- <&gcc GCC_DDRSS_GPU_AXI_CLK>, +- <&gcc GCC_GPU_MEMNOC_GFX_CLK>; +- clock-names = "gmu", "cxo", "axi", "memnoc"; +- power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; +- power-domain-names = "cx", "gx"; +- iommus = <&adreno_smmu 5>; +- operating-points-v2 = <&gmu_opp_table>; +- +- gmu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- opp-level = ; +- }; +- }; +- }; +- +- gpucc: clock-controller@5090000 { +- compatible = "qcom,sc7180-gpucc"; +- reg = <0 0x05090000 0 0x9000>; +- clocks = <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_GPU_GPLL0_CLK_SRC>, +- <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; +- clock-names = "bi_tcxo", +- "gcc_gpu_gpll0_clk_src", +- "gcc_gpu_gpll0_div_clk_src"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- }; +- +- stm@6002000 { +- compatible = "arm,coresight-stm", "arm,primecell"; +- reg = <0 0x06002000 0 0x1000>, +- <0 0x16280000 0 0x180000>; +- reg-names = "stm-base", "stm-stimulus-base"; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- stm_out: endpoint { +- remote-endpoint = <&funnel0_in7>; +- }; +- }; +- }; +- }; +- +- funnel@6041000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x06041000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- funnel0_out: endpoint { +- remote-endpoint = <&merge_funnel_in0>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@7 { +- reg = <7>; +- funnel0_in7: endpoint { +- remote-endpoint = <&stm_out>; +- }; +- }; +- }; +- }; +- +- funnel@6042000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x06042000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- funnel1_out: endpoint { +- remote-endpoint = <&merge_funnel_in1>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@4 { +- reg = <4>; +- funnel1_in4: endpoint { +- remote-endpoint = <&apss_merge_funnel_out>; +- }; +- }; +- }; +- }; +- +- funnel@6045000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x06045000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- merge_funnel_out: endpoint { +- remote-endpoint = <&swao_funnel_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- merge_funnel_in0: endpoint { +- remote-endpoint = <&funnel0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- merge_funnel_in1: endpoint { +- remote-endpoint = <&funnel1_out>; +- }; +- }; +- }; +- }; +- +- replicator@6046000 { +- compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; +- reg = <0 0x06046000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- replicator_out: endpoint { +- remote-endpoint = <&etr_in>; +- }; +- }; +- }; +- +- in-ports { +- port { +- replicator_in: endpoint { +- remote-endpoint = <&swao_replicator_out>; +- }; +- }; +- }; +- }; +- +- etr@6048000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0x06048000 0 0x1000>; +- iommus = <&apps_smmu 0x04a0 0x20>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,scatter-gather; +- +- in-ports { +- port { +- etr_in: endpoint { +- remote-endpoint = <&replicator_out>; +- }; +- }; +- }; +- }; +- +- funnel@6b04000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x06b04000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- swao_funnel_out: endpoint { +- remote-endpoint = <&etf_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@7 { +- reg = <7>; +- swao_funnel_in: endpoint { +- remote-endpoint = <&merge_funnel_out>; +- }; +- }; +- }; +- }; +- +- etf@6b05000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0x06b05000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etf_out: endpoint { +- remote-endpoint = <&swao_replicator_in>; +- }; +- }; +- }; +- +- in-ports { +- port { +- etf_in: endpoint { +- remote-endpoint = <&swao_funnel_out>; +- }; +- }; +- }; +- }; +- +- replicator@6b06000 { +- compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; +- reg = <0 0x06b06000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- qcom,replicator-loses-context; +- +- out-ports { +- port { +- swao_replicator_out: endpoint { +- remote-endpoint = <&replicator_in>; +- }; +- }; +- }; +- +- in-ports { +- port { +- swao_replicator_in: endpoint { +- remote-endpoint = <&etf_out>; +- }; +- }; +- }; +- }; +- +- etm@7040000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07040000 0 0x1000>; +- +- cpu = <&CPU0>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm0_out: endpoint { +- remote-endpoint = <&apss_funnel_in0>; +- }; +- }; +- }; +- }; +- +- etm@7140000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07140000 0 0x1000>; +- +- cpu = <&CPU1>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm1_out: endpoint { +- remote-endpoint = <&apss_funnel_in1>; +- }; +- }; +- }; +- }; +- +- etm@7240000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07240000 0 0x1000>; +- +- cpu = <&CPU2>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm2_out: endpoint { +- remote-endpoint = <&apss_funnel_in2>; +- }; +- }; +- }; +- }; +- +- etm@7340000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07340000 0 0x1000>; +- +- cpu = <&CPU3>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm3_out: endpoint { +- remote-endpoint = <&apss_funnel_in3>; +- }; +- }; +- }; +- }; +- +- etm@7440000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07440000 0 0x1000>; +- +- cpu = <&CPU4>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm4_out: endpoint { +- remote-endpoint = <&apss_funnel_in4>; +- }; +- }; +- }; +- }; +- +- etm@7540000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07540000 0 0x1000>; +- +- cpu = <&CPU5>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm5_out: endpoint { +- remote-endpoint = <&apss_funnel_in5>; +- }; +- }; +- }; +- }; +- +- etm@7640000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07640000 0 0x1000>; +- +- cpu = <&CPU6>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm6_out: endpoint { +- remote-endpoint = <&apss_funnel_in6>; +- }; +- }; +- }; +- }; +- +- etm@7740000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07740000 0 0x1000>; +- +- cpu = <&CPU7>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm7_out: endpoint { +- remote-endpoint = <&apss_funnel_in7>; +- }; +- }; +- }; +- }; +- +- funnel@7800000 { /* APSS Funnel */ +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x07800000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- apss_funnel_out: endpoint { +- remote-endpoint = <&apss_merge_funnel_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- apss_funnel_in0: endpoint { +- remote-endpoint = <&etm0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- apss_funnel_in1: endpoint { +- remote-endpoint = <&etm1_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- apss_funnel_in2: endpoint { +- remote-endpoint = <&etm2_out>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- apss_funnel_in3: endpoint { +- remote-endpoint = <&etm3_out>; +- }; +- }; +- +- port@4 { +- reg = <4>; +- apss_funnel_in4: endpoint { +- remote-endpoint = <&etm4_out>; +- }; +- }; +- +- port@5 { +- reg = <5>; +- apss_funnel_in5: endpoint { +- remote-endpoint = <&etm5_out>; +- }; +- }; +- +- port@6 { +- reg = <6>; +- apss_funnel_in6: endpoint { +- remote-endpoint = <&etm6_out>; +- }; +- }; +- +- port@7 { +- reg = <7>; +- apss_funnel_in7: endpoint { +- remote-endpoint = <&etm7_out>; +- }; +- }; +- }; +- }; +- +- funnel@7810000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x07810000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- apss_merge_funnel_out: endpoint { +- remote-endpoint = <&funnel1_in4>; +- }; +- }; +- }; +- +- in-ports { +- port { +- apss_merge_funnel_in: endpoint { +- remote-endpoint = <&apss_funnel_out>; +- }; +- }; +- }; +- }; +- +- sdhc_2: sdhci@8804000 { +- compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; +- reg = <0 0x08804000 0 0x1000>; +- +- iommus = <&apps_smmu 0x80 0>; +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- +- clocks = <&gcc GCC_SDCC2_APPS_CLK>, +- <&gcc GCC_SDCC2_AHB_CLK>, +- <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "core", "iface", "xo"; +- +- interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; +- interconnect-names = "sdhc-ddr","cpu-sdhc"; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&sdhc2_opp_table>; +- +- bus-width = <4>; +- +- status = "disabled"; +- +- sdhc2_opp_table: sdhc2-opp-table { +- compatible = "operating-points-v2"; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- opp-peak-kBps = <1800000 600000>; +- opp-avg-kBps = <100000 0>; +- }; +- +- opp-202000000 { +- opp-hz = /bits/ 64 <202000000>; +- required-opps = <&rpmhpd_opp_nom>; +- opp-peak-kBps = <5400000 1600000>; +- opp-avg-kBps = <200000 0>; +- }; +- }; +- }; +- +- qspi_opp_table: qspi-opp-table { +- compatible = "operating-points-v2"; +- +- opp-75000000 { +- opp-hz = /bits/ 64 <75000000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- }; +- +- opp-150000000 { +- opp-hz = /bits/ 64 <150000000>; +- required-opps = <&rpmhpd_opp_svs>; +- }; +- +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- required-opps = <&rpmhpd_opp_nom>; +- }; +- }; +- +- qspi: spi@88dc000 { +- compatible = "qcom,qspi-v1"; +- reg = <0 0x088dc000 0 0x600>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, +- <&gcc GCC_QSPI_CORE_CLK>; +- clock-names = "iface", "core"; +- interconnects = <&gem_noc MASTER_APPSS_PROC 0 +- &config_noc SLAVE_QSPI_0 0>; +- interconnect-names = "qspi-config"; +- power-domains = <&rpmhpd SC7180_CX>; +- operating-points-v2 = <&qspi_opp_table>; +- status = "disabled"; +- }; +- +- usb_1_hsphy: phy@88e3000 { +- compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; +- reg = <0 0x088e3000 0 0x400>; +- status = "disabled"; +- #phy-cells = <0>; +- clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, +- <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "cfg_ahb", "ref"; +- resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; +- +- nvmem-cells = <&qusb2p_hstx_trim>; +- }; +- +- usb_1_qmpphy: phy-wrapper@88e9000 { +- compatible = "qcom,sc7180-qmp-usb3-dp-phy"; +- reg = <0 0x088e9000 0 0x18c>, +- <0 0x088e8000 0 0x3c>, +- <0 0x088ea000 0 0x18c>; +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, +- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, +- <&gcc GCC_USB3_PRIM_CLKREF_CLK>, +- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; +- clock-names = "aux", "cfg_ahb", "ref", "com_aux"; +- +- resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, +- <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; +- reset-names = "phy", "common"; +- +- usb_1_ssphy: usb3-phy@88e9200 { +- reg = <0 0x088e9200 0 0x128>, +- <0 0x088e9400 0 0x200>, +- <0 0x088e9c00 0 0x218>, +- <0 0x088e9600 0 0x128>, +- <0 0x088e9800 0 0x200>, +- <0 0x088e9a00 0 0x18>; +- #clock-cells = <0>; +- #phy-cells = <0>; +- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; +- clock-names = "pipe0"; +- clock-output-names = "usb3_phy_pipe_clk_src"; +- }; +- +- dp_phy: dp-phy@88ea200 { +- reg = <0 0x088ea200 0 0x200>, +- <0 0x088ea400 0 0x200>, +- <0 0x088eaa00 0 0x200>, +- <0 0x088ea600 0 0x200>, +- <0 0x088ea800 0 0x200>; +- #clock-cells = <1>; +- #phy-cells = <0>; +- }; +- }; +- +- dc_noc: interconnect@9160000 { +- compatible = "qcom,sc7180-dc-noc"; +- reg = <0 0x09160000 0 0x03200>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- system-cache-controller@9200000 { +- compatible = "qcom,sc7180-llcc"; +- reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; +- reg-names = "llcc_base", "llcc_broadcast_base"; +- interrupts = ; +- }; +- +- gem_noc: interconnect@9680000 { +- compatible = "qcom,sc7180-gem-noc"; +- reg = <0 0x09680000 0 0x3e200>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- npu_noc: interconnect@9990000 { +- compatible = "qcom,sc7180-npu-noc"; +- reg = <0 0x09990000 0 0x1600>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- usb_1: usb@a6f8800 { +- compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; +- reg = <0 0x0a6f8800 0 0x400>; +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- dma-ranges; +- +- clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, +- <&gcc GCC_USB30_PRIM_MASTER_CLK>, +- <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, +- <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_PRIM_SLEEP_CLK>; +- clock-names = "cfg_noc", "core", "iface", "mock_utmi", +- "sleep"; +- +- assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_PRIM_MASTER_CLK>; +- assigned-clock-rates = <19200000>, <150000000>; +- +- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, +- <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, +- <&pdc 8 IRQ_TYPE_LEVEL_HIGH>, +- <&pdc 9 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "hs_phy_irq", "ss_phy_irq", +- "dm_hs_phy_irq", "dp_hs_phy_irq"; +- +- power-domains = <&gcc USB30_PRIM_GDSC>; +- +- resets = <&gcc GCC_USB30_PRIM_BCR>; +- +- interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; +- interconnect-names = "usb-ddr", "apps-usb"; +- +- usb_1_dwc3: dwc3@a600000 { +- compatible = "snps,dwc3"; +- reg = <0 0x0a600000 0 0xe000>; +- interrupts = ; +- iommus = <&apps_smmu 0x540 0>; +- snps,dis_u2_susphy_quirk; +- snps,dis_enblslpm_quirk; +- phys = <&usb_1_hsphy>, <&usb_1_ssphy>; +- phy-names = "usb2-phy", "usb3-phy"; +- maximum-speed = "super-speed"; +- }; +- }; +- +- venus: video-codec@aa00000 { +- compatible = "qcom,sc7180-venus"; +- reg = <0 0x0aa00000 0 0xff000>; +- interrupts = ; +- power-domains = <&videocc VENUS_GDSC>, +- <&videocc VCODEC0_GDSC>, +- <&rpmhpd SC7180_CX>; +- power-domain-names = "venus", "vcodec0", "cx"; +- operating-points-v2 = <&venus_opp_table>; +- clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, +- <&videocc VIDEO_CC_VENUS_AHB_CLK>, +- <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, +- <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, +- <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; +- clock-names = "core", "iface", "bus", +- "vcodec0_core", "vcodec0_bus"; +- iommus = <&apps_smmu 0x0c00 0x60>; +- memory-region = <&venus_mem>; +- interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; +- interconnect-names = "video-mem", "cpu-cfg"; +- +- video-decoder { +- compatible = "venus-decoder"; +- }; +- +- video-encoder { +- compatible = "venus-encoder"; +- }; +- +- venus_opp_table: venus-opp-table { +- compatible = "operating-points-v2"; +- +- opp-150000000 { +- opp-hz = /bits/ 64 <150000000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- }; +- +- opp-270000000 { +- opp-hz = /bits/ 64 <270000000>; +- required-opps = <&rpmhpd_opp_svs>; +- }; +- +- opp-340000000 { +- opp-hz = /bits/ 64 <340000000>; +- required-opps = <&rpmhpd_opp_svs_l1>; +- }; +- +- opp-434000000 { +- opp-hz = /bits/ 64 <434000000>; +- required-opps = <&rpmhpd_opp_nom>; +- }; +- +- opp-500000097 { +- opp-hz = /bits/ 64 <500000097>; +- required-opps = <&rpmhpd_opp_turbo>; +- }; +- }; +- }; +- +- videocc: clock-controller@ab00000 { +- compatible = "qcom,sc7180-videocc"; +- reg = <0 0x0ab00000 0 0x10000>; +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "bi_tcxo"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- }; +- +- camnoc_virt: interconnect@ac00000 { +- compatible = "qcom,sc7180-camnoc-virt"; +- reg = <0 0x0ac00000 0 0x1000>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- camcc: clock-controller@ad00000 { +- compatible = "qcom,sc7180-camcc"; +- reg = <0 0x0ad00000 0 0x10000>; +- clocks = <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_CAMERA_AHB_CLK>, +- <&gcc GCC_CAMERA_XO_CLK>; +- clock-names = "bi_tcxo", "iface", "xo"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- }; +- +- mdss: mdss@ae00000 { +- compatible = "qcom,sc7180-mdss"; +- reg = <0 0x0ae00000 0 0x1000>; +- reg-names = "mdss"; +- +- power-domains = <&dispcc MDSS_GDSC>; +- +- clocks = <&gcc GCC_DISP_AHB_CLK>, +- <&dispcc DISP_CC_MDSS_AHB_CLK>, +- <&dispcc DISP_CC_MDSS_MDP_CLK>; +- clock-names = "iface", "ahb", "core"; +- +- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; +- assigned-clock-rates = <300000000>; +- +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; +- interconnect-names = "mdp0-mem"; +- +- iommus = <&apps_smmu 0x800 0x2>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- status = "disabled"; +- +- mdp: mdp@ae01000 { +- compatible = "qcom,sc7180-dpu"; +- reg = <0 0x0ae01000 0 0x8f000>, +- <0 0x0aeb0000 0 0x2008>; +- reg-names = "mdp", "vbif"; +- +- clocks = <&gcc GCC_DISP_HF_AXI_CLK>, +- <&dispcc DISP_CC_MDSS_AHB_CLK>, +- <&dispcc DISP_CC_MDSS_ROT_CLK>, +- <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, +- <&dispcc DISP_CC_MDSS_MDP_CLK>, +- <&dispcc DISP_CC_MDSS_VSYNC_CLK>; +- clock-names = "bus", "iface", "rot", "lut", "core", +- "vsync"; +- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, +- <&dispcc DISP_CC_MDSS_VSYNC_CLK>, +- <&dispcc DISP_CC_MDSS_ROT_CLK>, +- <&dispcc DISP_CC_MDSS_AHB_CLK>; +- assigned-clock-rates = <300000000>, +- <19200000>, +- <19200000>, +- <19200000>; +- operating-points-v2 = <&mdp_opp_table>; +- power-domains = <&rpmhpd SC7180_CX>; +- +- interrupt-parent = <&mdss>; +- interrupts = <0>; +- +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dpu_intf1_out: endpoint { +- remote-endpoint = <&dsi0_in>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- dpu_intf0_out: endpoint { +- remote-endpoint = <&dp_in>; +- }; +- }; +- }; +- +- mdp_opp_table: mdp-opp-table { +- compatible = "operating-points-v2"; +- +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- }; +- +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- required-opps = <&rpmhpd_opp_svs>; +- }; +- +- opp-345000000 { +- opp-hz = /bits/ 64 <345000000>; +- required-opps = <&rpmhpd_opp_svs_l1>; +- }; +- +- opp-460000000 { +- opp-hz = /bits/ 64 <460000000>; +- required-opps = <&rpmhpd_opp_nom>; +- }; +- }; +- +- }; +- +- dsi0: dsi@ae94000 { +- compatible = "qcom,mdss-dsi-ctrl"; +- reg = <0 0x0ae94000 0 0x400>; +- reg-names = "dsi_ctrl"; +- +- interrupt-parent = <&mdss>; +- interrupts = <4>; +- +- clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, +- <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, +- <&dispcc DISP_CC_MDSS_PCLK0_CLK>, +- <&dispcc DISP_CC_MDSS_ESC0_CLK>, +- <&dispcc DISP_CC_MDSS_AHB_CLK>, +- <&gcc GCC_DISP_HF_AXI_CLK>; +- clock-names = "byte", +- "byte_intf", +- "pixel", +- "core", +- "iface", +- "bus"; +- +- assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; +- assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; +- +- operating-points-v2 = <&dsi_opp_table>; +- power-domains = <&rpmhpd SC7180_CX>; +- +- phys = <&dsi_phy>; +- phy-names = "dsi"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dsi0_in: endpoint { +- remote-endpoint = <&dpu_intf1_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- dsi0_out: endpoint { +- }; +- }; +- }; +- +- dsi_opp_table: dsi-opp-table { +- compatible = "operating-points-v2"; +- +- opp-187500000 { +- opp-hz = /bits/ 64 <187500000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- }; +- +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- required-opps = <&rpmhpd_opp_svs>; +- }; +- +- opp-358000000 { +- opp-hz = /bits/ 64 <358000000>; +- required-opps = <&rpmhpd_opp_svs_l1>; +- }; +- }; +- }; +- +- dsi_phy: dsi-phy@ae94400 { +- compatible = "qcom,dsi-phy-10nm"; +- reg = <0 0x0ae94400 0 0x200>, +- <0 0x0ae94600 0 0x280>, +- <0 0x0ae94a00 0 0x1e0>; +- reg-names = "dsi_phy", +- "dsi_phy_lane", +- "dsi_pll"; +- +- #clock-cells = <1>; +- #phy-cells = <0>; +- +- clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, +- <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "iface", "ref"; +- +- status = "disabled"; +- }; +- +- mdss_dp: displayport-controller@ae90000 { +- compatible = "qcom,sc7180-dp"; +- status = "disabled"; +- +- reg = <0 0x0ae90000 0 0x1400>; +- +- interrupt-parent = <&mdss>; +- interrupts = <12>; +- +- clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, +- <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, +- <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, +- <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, +- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; +- clock-names = "core_iface", "core_aux", "ctrl_link", +- "ctrl_link_iface", "stream_pixel"; +- #clock-cells = <1>; +- assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, +- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; +- assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; +- phys = <&dp_phy>; +- phy-names = "dp"; +- +- operating-points-v2 = <&dp_opp_table>; +- power-domains = <&rpmhpd SC7180_CX>; +- +- #sound-dai-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- dp_in: endpoint { +- remote-endpoint = <&dpu_intf0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- dp_out: endpoint { }; +- }; +- }; +- +- dp_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-160000000 { +- opp-hz = /bits/ 64 <160000000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- }; +- +- opp-270000000 { +- opp-hz = /bits/ 64 <270000000>; +- required-opps = <&rpmhpd_opp_svs>; +- }; +- +- opp-540000000 { +- opp-hz = /bits/ 64 <540000000>; +- required-opps = <&rpmhpd_opp_svs_l1>; +- }; +- +- opp-810000000 { +- opp-hz = /bits/ 64 <810000000>; +- required-opps = <&rpmhpd_opp_nom>; +- }; +- }; +- }; +- }; +- +- dispcc: clock-controller@af00000 { +- compatible = "qcom,sc7180-dispcc"; +- reg = <0 0x0af00000 0 0x200000>; +- clocks = <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_DISP_GPLL0_CLK_SRC>, +- <&dsi_phy 0>, +- <&dsi_phy 1>, +- <&dp_phy 0>, +- <&dp_phy 1>; +- clock-names = "bi_tcxo", +- "gcc_disp_gpll0_clk_src", +- "dsi0_phy_pll_out_byteclk", +- "dsi0_phy_pll_out_dsiclk", +- "dp_phy_pll_link_clk", +- "dp_phy_pll_vco_div_clk"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- }; +- +- pdc: interrupt-controller@b220000 { +- compatible = "qcom,sc7180-pdc", "qcom,pdc"; +- reg = <0 0x0b220000 0 0x30000>; +- qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; +- #interrupt-cells = <2>; +- interrupt-parent = <&intc>; +- interrupt-controller; +- }; +- +- pdc_reset: reset-controller@b2e0000 { +- compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; +- reg = <0 0x0b2e0000 0 0x20000>; +- #reset-cells = <1>; +- }; +- +- tsens0: thermal-sensor@c263000 { +- compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; +- reg = <0 0x0c263000 0 0x1ff>, /* TM */ +- <0 0x0c222000 0 0x1ff>; /* SROT */ +- #qcom,sensors = <15>; +- interrupts = , +- ; +- interrupt-names = "uplow","critical"; +- #thermal-sensor-cells = <1>; +- }; +- +- tsens1: thermal-sensor@c265000 { +- compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; +- reg = <0 0x0c265000 0 0x1ff>, /* TM */ +- <0 0x0c223000 0 0x1ff>; /* SROT */ +- #qcom,sensors = <10>; +- interrupts = , +- ; +- interrupt-names = "uplow","critical"; +- #thermal-sensor-cells = <1>; +- }; +- +- aoss_reset: reset-controller@c2a0000 { +- compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; +- reg = <0 0x0c2a0000 0 0x31000>; +- #reset-cells = <1>; +- }; +- +- aoss_qmp: power-controller@c300000 { +- compatible = "qcom,sc7180-aoss-qmp"; +- reg = <0 0x0c300000 0 0x100000>; +- interrupts = ; +- mboxes = <&apss_shared 0>; +- +- #clock-cells = <0>; +- #power-domain-cells = <1>; +- }; +- +- spmi_bus: spmi@c440000 { +- compatible = "qcom,spmi-pmic-arb"; +- reg = <0 0x0c440000 0 0x1100>, +- <0 0x0c600000 0 0x2000000>, +- <0 0x0e600000 0 0x100000>, +- <0 0x0e700000 0 0xa0000>, +- <0 0x0c40a000 0 0x26000>; +- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; +- interrupt-names = "periph_irq"; +- interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; +- qcom,ee = <0>; +- qcom,channel = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-controller; +- #interrupt-cells = <4>; +- cell-index = <0>; +- }; +- +- apps_smmu: iommu@15000000 { +- compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; +- reg = <0 0x15000000 0 0x100000>; +- #iommu-cells = <2>; +- #global-interrupts = <1>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- }; +- +- intc: interrupt-controller@17a00000 { +- compatible = "arm,gic-v3"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0 0x17a00000 0 0x10000>, /* GICD */ +- <0 0x17a60000 0 0x100000>; /* GICR * 8 */ +- interrupts = ; +- +- msi-controller@17a40000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0 0x17a40000 0 0x20000>; +- status = "disabled"; +- }; +- }; +- +- apss_shared: mailbox@17c00000 { +- compatible = "qcom,sc7180-apss-shared"; +- reg = <0 0x17c00000 0 0x10000>; +- #mbox-cells = <1>; +- }; +- +- watchdog@17c10000 { +- compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; +- reg = <0 0x17c10000 0 0x1000>; +- clocks = <&sleep_clk>; +- interrupts = ; +- }; +- +- timer@17c20000{ +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- compatible = "arm,armv7-timer-mem"; +- reg = <0 0x17c20000 0 0x1000>; +- +- frame@17c21000 { +- frame-number = <0>; +- interrupts = , +- ; +- reg = <0 0x17c21000 0 0x1000>, +- <0 0x17c22000 0 0x1000>; +- }; +- +- frame@17c23000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0 0x17c23000 0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c25000 { +- frame-number = <2>; +- interrupts = ; +- reg = <0 0x17c25000 0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c27000 { +- frame-number = <3>; +- interrupts = ; +- reg = <0 0x17c27000 0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c29000 { +- frame-number = <4>; +- interrupts = ; +- reg = <0 0x17c29000 0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c2b000 { +- frame-number = <5>; +- interrupts = ; +- reg = <0 0x17c2b000 0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c2d000 { +- frame-number = <6>; +- interrupts = ; +- reg = <0 0x17c2d000 0 0x1000>; +- status = "disabled"; +- }; +- }; +- +- apps_rsc: rsc@18200000 { +- compatible = "qcom,rpmh-rsc"; +- reg = <0 0x18200000 0 0x10000>, +- <0 0x18210000 0 0x10000>, +- <0 0x18220000 0 0x10000>; +- reg-names = "drv-0", "drv-1", "drv-2"; +- interrupts = , +- , +- ; +- qcom,tcs-offset = <0xd00>; +- qcom,drv-id = <2>; +- qcom,tcs-config = , +- , +- , +- ; +- +- rpmhcc: clock-controller { +- compatible = "qcom,sc7180-rpmh-clk"; +- clocks = <&xo_board>; +- clock-names = "xo"; +- #clock-cells = <1>; +- }; +- +- rpmhpd: power-controller { +- compatible = "qcom,sc7180-rpmhpd"; +- #power-domain-cells = <1>; +- operating-points-v2 = <&rpmhpd_opp_table>; +- +- rpmhpd_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- rpmhpd_opp_ret: opp1 { +- opp-level = ; +- }; +- +- rpmhpd_opp_min_svs: opp2 { +- opp-level = ; +- }; +- +- rpmhpd_opp_low_svs: opp3 { +- opp-level = ; +- }; +- +- rpmhpd_opp_svs: opp4 { +- opp-level = ; +- }; +- +- rpmhpd_opp_svs_l1: opp5 { +- opp-level = ; +- }; +- +- rpmhpd_opp_svs_l2: opp6 { +- opp-level = <224>; +- }; +- +- rpmhpd_opp_nom: opp7 { +- opp-level = ; +- }; +- +- rpmhpd_opp_nom_l1: opp8 { +- opp-level = ; +- }; +- +- rpmhpd_opp_nom_l2: opp9 { +- opp-level = ; +- }; +- +- rpmhpd_opp_turbo: opp10 { +- opp-level = ; +- }; +- +- rpmhpd_opp_turbo_l1: opp11 { +- opp-level = ; +- }; +- }; +- }; +- +- apps_bcm_voter: bcm_voter { +- compatible = "qcom,bcm-voter"; +- }; +- }; +- +- osm_l3: interconnect@18321000 { +- compatible = "qcom,sc7180-osm-l3"; +- reg = <0 0x18321000 0 0x1400>; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; +- clock-names = "xo", "alternate"; +- +- #interconnect-cells = <1>; +- }; +- +- cpufreq_hw: cpufreq@18323000 { +- compatible = "qcom,cpufreq-hw"; +- reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; +- reg-names = "freq-domain0", "freq-domain1"; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; +- clock-names = "xo", "alternate"; +- +- #freq-domain-cells = <1>; +- }; +- +- wifi: wifi@18800000 { +- compatible = "qcom,wcn3990-wifi"; +- reg = <0 0x18800000 0 0x800000>; +- reg-names = "membase"; +- iommus = <&apps_smmu 0xc0 0x1>; +- interrupts = +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- memory-region = <&wlan_mem>; +- qcom,msa-fixed-perm; +- status = "disabled"; +- }; +- +- lpasscc: clock-controller@62d00000 { +- compatible = "qcom,sc7180-lpasscorecc"; +- reg = <0 0x62d00000 0 0x50000>, +- <0 0x62780000 0 0x30000>; +- reg-names = "lpass_core_cc", "lpass_audio_cc"; +- clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, +- <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "iface", "bi_tcxo"; +- power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; +- #clock-cells = <1>; +- #power-domain-cells = <1>; +- }; +- +- lpass_cpu: lpass@62d87000 { +- compatible = "qcom,sc7180-lpass-cpu"; +- +- reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; +- reg-names = "lpass-hdmiif", "lpass-lpaif"; +- +- iommus = <&apps_smmu 0x1020 0>, +- <&apps_smmu 0x1021 0>, +- <&apps_smmu 0x1032 0>; +- +- power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; +- +- status = "disabled"; +- +- clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, +- <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, +- <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, +- <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, +- <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, +- <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; +- +- clock-names = "pcnoc-sway-clk", "audio-core", +- "mclk0", "pcnoc-mport-clk", +- "mi2s-bit-clk0", "mi2s-bit-clk1"; +- +- +- #sound-dai-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- interrupts = , +- ; +- interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi"; +- }; +- +- lpass_hm: clock-controller@63000000 { +- compatible = "qcom,sc7180-lpasshm"; +- reg = <0 0x63000000 0 0x28>; +- clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, +- <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "iface", "bi_tcxo"; +- #clock-cells = <1>; +- #power-domain-cells = <1>; +- }; +- }; +- +- thermal-zones { +- cpu0_thermal: cpu0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 1>; +- sustainable-power = <1052>; +- +- trips { +- cpu0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu0_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu0_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu0_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu0_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu1_thermal: cpu1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 2>; +- sustainable-power = <1052>; +- +- trips { +- cpu1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu1_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu1_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu1_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu1_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu2_thermal: cpu2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 3>; +- sustainable-power = <1052>; +- +- trips { +- cpu2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu2_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu2_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu2_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu2_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu3_thermal: cpu3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 4>; +- sustainable-power = <1052>; +- +- trips { +- cpu3_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu3_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu3_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu3_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu3_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu4_thermal: cpu4-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 5>; +- sustainable-power = <1052>; +- +- trips { +- cpu4_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu4_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu4_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu4_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu4_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu5_thermal: cpu5-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 6>; +- sustainable-power = <1052>; +- +- trips { +- cpu5_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu5_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu5_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu5_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu5_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu6_thermal: cpu6-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 9>; +- sustainable-power = <1425>; +- +- trips { +- cpu6_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu6_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu6_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu6_alert0>; +- cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu6_alert1>; +- cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu7_thermal: cpu7-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 10>; +- sustainable-power = <1425>; +- +- trips { +- cpu7_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu7_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu7_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu7_alert0>; +- cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu7_alert1>; +- cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu8_thermal: cpu8-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 11>; +- sustainable-power = <1425>; +- +- trips { +- cpu8_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu8_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu8_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu8_alert0>; +- cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu8_alert1>; +- cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu9_thermal: cpu9-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 12>; +- sustainable-power = <1425>; +- +- trips { +- cpu9_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu9_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu9_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu9_alert0>; +- cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu9_alert1>; +- cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- aoss0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 0>; +- +- trips { +- aoss0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- aoss0_crit: aoss0_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpuss0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 7>; +- +- trips { +- cpuss0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- cpuss0_crit: cluster0_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpuss1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 8>; +- +- trips { +- cpuss1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- cpuss1_crit: cluster0_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- gpuss0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 13>; +- +- trips { +- gpuss0_alert0: trip-point0 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- gpuss0_crit: gpuss0_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&gpuss0_alert0>; +- cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- gpuss1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 14>; +- +- trips { +- gpuss1_alert0: trip-point0 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- gpuss1_crit: gpuss1_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&gpuss1_alert0>; +- cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- aoss1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 0>; +- +- trips { +- aoss1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- aoss1_crit: aoss1_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cwlan-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 1>; +- +- trips { +- cwlan_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- cwlan_crit: cwlan_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- audio-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 2>; +- +- trips { +- audio_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- audio_crit: audio_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- ddr-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 3>; +- +- trips { +- ddr_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- ddr_crit: ddr_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- q6-hvx-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 4>; +- +- trips { +- q6_hvx_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- q6_hvx_crit: q6_hvx_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- camera-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 5>; +- +- trips { +- camera_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- camera_crit: camera_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- mdm-core-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 6>; +- +- trips { +- mdm_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- mdm_crit: mdm_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- mdm-dsp-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 7>; +- +- trips { +- mdm_dsp_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- mdm_dsp_crit: mdm_dsp_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- npu-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 8>; +- +- trips { +- npu_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- npu_crit: npu_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- video-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 9>; +- +- trips { +- video_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- video_crit: video_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7280-idp.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7280-idp.dts +deleted file mode 100644 +index 64fc22aff33d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7280-idp.dts ++++ /dev/null +@@ -1,70 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * sc7280 IDP board device tree source +- * +- * Copyright (c) 2021, The Linux Foundation. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include +-#include "sc7280-idp.dtsi" +-#include "pmr735a.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. sc7280 IDP SKU1 platform"; +- compatible = "qcom,sc7280-idp", "google,senor", "qcom,sc7280"; +- +- aliases { +- serial0 = &uart5; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&apps_rsc { +- pmr735a-regulators { +- compatible = "qcom,pmr735a-rpmh-regulators"; +- qcom,pmic-id = "e"; +- +- vreg_l2e_1p2: ldo2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- }; +- +- vreg_l3e_0p9: ldo3 { +- regulator-min-microvolt = <912000>; +- regulator-max-microvolt = <1020000>; +- }; +- +- vreg_l4e_1p7: ldo4 { +- regulator-min-microvolt = <1776000>; +- regulator-max-microvolt = <1890000>; +- }; +- +- vreg_l5e_0p8: ldo5 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- }; +- +- vreg_l6e_0p8: ldo6 { +- regulator-min-microvolt = <480000>; +- regulator-max-microvolt = <904000>; +- }; +- }; +-}; +- +-&ipa { +- status = "okay"; +- modem-init; +-}; +- +-&pmk8350_vadc { +- pmr735a_die_temp { +- reg = ; +- label = "pmr735a_die_temp"; +- qcom,pre-scaling = <1 1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7280-idp.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sc7280-idp.dtsi +deleted file mode 100644 +index 371a2a9dcf7a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7280-idp.dtsi ++++ /dev/null +@@ -1,341 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * sc7280 IDP board device tree source (common between SKU1 and SKU2) +- * +- * Copyright (c) 2021, The Linux Foundation. All rights reserved. +- */ +- +-#include +-#include +-#include "sc7280.dtsi" +-#include "pm7325.dtsi" +-#include "pm8350c.dtsi" +-#include "pmk8350.dtsi" +- +-&apps_rsc { +- pm7325-regulators { +- compatible = "qcom,pm7325-rpmh-regulators"; +- qcom,pmic-id = "b"; +- +- vreg_s1b_1p8: smps1 { +- regulator-min-microvolt = <1856000>; +- regulator-max-microvolt = <2040000>; +- }; +- +- vreg_s7b_0p9: smps7 { +- regulator-min-microvolt = <535000>; +- regulator-max-microvolt = <1120000>; +- }; +- +- vreg_s8b_1p2: smps8 { +- regulator-min-microvolt = <1256000>; +- regulator-max-microvolt = <1500000>; +- }; +- +- vreg_l1b_0p8: ldo1 { +- regulator-min-microvolt = <825000>; +- regulator-max-microvolt = <925000>; +- }; +- +- vreg_l2b_3p0: ldo2 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3544000>; +- }; +- +- vreg_l6b_1p2: ldo6 { +- regulator-min-microvolt = <1140000>; +- regulator-max-microvolt = <1260000>; +- }; +- +- vreg_l7b_2p9: ldo7 { +- regulator-min-microvolt = <2960000>; +- regulator-max-microvolt = <2960000>; +- }; +- +- vreg_l8b_0p9: ldo8 { +- regulator-min-microvolt = <870000>; +- regulator-max-microvolt = <970000>; +- }; +- +- vreg_l9b_1p2: ldo9 { +- regulator-min-microvolt = <1080000>; +- regulator-max-microvolt = <1304000>; +- }; +- +- vreg_l11b_1p7: ldo11 { +- regulator-min-microvolt = <1504000>; +- regulator-max-microvolt = <2000000>; +- }; +- +- vreg_l12b_0p8: ldo12 { +- regulator-min-microvolt = <751000>; +- regulator-max-microvolt = <824000>; +- }; +- +- vreg_l13b_0p8: ldo13 { +- regulator-min-microvolt = <530000>; +- regulator-max-microvolt = <824000>; +- }; +- +- vreg_l14b_1p2: ldo14 { +- regulator-min-microvolt = <1080000>; +- regulator-max-microvolt = <1304000>; +- }; +- +- vreg_l15b_0p8: ldo15 { +- regulator-min-microvolt = <765000>; +- regulator-max-microvolt = <1020000>; +- }; +- +- vreg_l16b_1p2: ldo16 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1300000>; +- }; +- +- vreg_l17b_1p8: ldo17 { +- regulator-min-microvolt = <1700000>; +- regulator-max-microvolt = <1900000>; +- }; +- +- vreg_l18b_1p8: ldo18 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2000000>; +- }; +- +- vreg_l19b_1p8: ldo19 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- }; +- +- pm8350c-regulators { +- compatible = "qcom,pm8350c-rpmh-regulators"; +- qcom,pmic-id = "c"; +- +- vreg_s1c_2p2: smps1 { +- regulator-min-microvolt = <2190000>; +- regulator-max-microvolt = <2210000>; +- }; +- +- vreg_s9c_1p0: smps9 { +- regulator-min-microvolt = <1010000>; +- regulator-max-microvolt = <1170000>; +- }; +- +- vreg_l1c_1p8: ldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1980000>; +- }; +- +- vreg_l2c_1p8: ldo2 { +- regulator-min-microvolt = <1620000>; +- regulator-max-microvolt = <1980000>; +- }; +- +- vreg_l3c_3p0: ldo3 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <3540000>; +- }; +- +- vreg_l4c_1p8: ldo4 { +- regulator-min-microvolt = <1620000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vreg_l5c_1p8: ldo5 { +- regulator-min-microvolt = <1620000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vreg_l6c_2p9: ldo6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2950000>; +- }; +- +- vreg_l7c_3p0: ldo7 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3544000>; +- }; +- +- vreg_l8c_1p8: ldo8 { +- regulator-min-microvolt = <1620000>; +- regulator-max-microvolt = <2000000>; +- }; +- +- vreg_l9c_2p9: ldo9 { +- regulator-min-microvolt = <2960000>; +- regulator-max-microvolt = <2960000>; +- }; +- +- vreg_l10c_0p8: ldo10 { +- regulator-min-microvolt = <720000>; +- regulator-max-microvolt = <1050000>; +- }; +- +- vreg_l11c_2p8: ldo11 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <3544000>; +- }; +- +- vreg_l12c_1p8: ldo12 { +- regulator-min-microvolt = <1650000>; +- regulator-max-microvolt = <2000000>; +- }; +- +- vreg_l13c_3p0: ldo13 { +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <3544000>; +- }; +- +- vreg_bob: bob { +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3960000>; +- }; +- }; +-}; +- +-&ipa { +- status = "okay"; +- modem-init; +-}; +- +-&pmk8350_vadc { +- pmk8350_die_temp { +- reg = ; +- label = "pmk8350_die_temp"; +- qcom,pre-scaling = <1 1>; +- }; +-}; +- +-&qupv3_id_0 { +- status = "okay"; +-}; +- +-&sdhc_1 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc1_on>; +- pinctrl-1 = <&sdc1_off>; +- +- non-removable; +- no-sd; +- no-sdio; +- +- vmmc-supply = <&vreg_l7b_2p9>; +- vqmmc-supply = <&vreg_l19b_1p8>; +-}; +- +-&sdhc_2 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc2_on>; +- pinctrl-1 = <&sdc2_off>; +- +- vmmc-supply = <&vreg_l9c_2p9>; +- vqmmc-supply = <&vreg_l6c_2p9>; +- +- cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&usb_1 { +- status = "okay"; +-}; +- +-&usb_1_dwc3 { +- dr_mode = "host"; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- +- vdda-pll-supply = <&vreg_l10c_0p8>; +- vdda33-supply = <&vreg_l2b_3p0>; +- vdda18-supply = <&vreg_l1c_1p8>; +-}; +- +-&usb_1_qmpphy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l6b_1p2>; +- vdda-pll-supply = <&vreg_l1b_0p8>; +-}; +- +-&usb_2 { +- status = "okay"; +-}; +- +-&usb_2_dwc3 { +- dr_mode = "peripheral"; +-}; +- +-&usb_2_hsphy { +- status = "okay"; +- +- vdda-pll-supply = <&vreg_l10c_0p8>; +- vdda33-supply = <&vreg_l2b_3p0>; +- vdda18-supply = <&vreg_l1c_1p8>; +-}; +- +-/* PINCTRL - additions to nodes defined in sc7280.dtsi */ +- +-&qup_uart5_default { +- tx { +- pins = "gpio46"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- rx { +- pins = "gpio47"; +- drive-strength = <2>; +- bias-pull-up; +- }; +-}; +- +-&sdc1_on { +- clk { +- bias-disable; +- drive-strength = <16>; +- }; +- +- cmd { +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- data { +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- rclk { +- bias-pull-down; +- }; +-}; +- +-&sdc2_on { +- clk { +- bias-disable; +- drive-strength = <16>; +- }; +- +- cmd { +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- data { +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- sd-cd { +- bias-pull-up; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7280-idp2.dts b/scripts/dtc/include-prefixes/arm64/qcom/sc7280-idp2.dts +deleted file mode 100644 +index 1fc2addc8ab6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7280-idp2.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * sc7280 IDP2 board device tree source +- * +- * Copyright (c) 2021, The Linux Foundation. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "sc7280-idp.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. sc7280 IDP SKU2 platform"; +- compatible = "qcom,sc7280-idp2", "google,piglin", "qcom,sc7280"; +- +- aliases { +- serial0 = &uart5; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sc7280.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sc7280.dtsi +deleted file mode 100644 +index 692973c4f434..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sc7280.dtsi ++++ /dev/null +@@ -1,2708 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * sc7280 SoC device tree source +- * +- * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&intc>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- chosen { }; +- +- aliases { +- mmc1 = &sdhc_1; +- mmc2 = &sdhc_2; +- }; +- +- clocks { +- xo_board: xo-board { +- compatible = "fixed-clock"; +- clock-frequency = <76800000>; +- #clock-cells = <0>; +- }; +- +- sleep_clk: sleep-clk { +- compatible = "fixed-clock"; +- clock-frequency = <32000>; +- #clock-cells = <0>; +- }; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- aop_mem: memory@80800000 { +- reg = <0x0 0x80800000 0x0 0x60000>; +- no-map; +- }; +- +- aop_cmd_db_mem: memory@80860000 { +- reg = <0x0 0x80860000 0x0 0x20000>; +- compatible = "qcom,cmd-db"; +- no-map; +- }; +- +- smem_mem: memory@80900000 { +- reg = <0x0 0x80900000 0x0 0x200000>; +- no-map; +- }; +- +- cpucp_mem: memory@80b00000 { +- no-map; +- reg = <0x0 0x80b00000 0x0 0x100000>; +- }; +- +- ipa_fw_mem: memory@8b700000 { +- reg = <0 0x8b700000 0 0x10000>; +- no-map; +- }; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- CPU0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,kryo"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- cpu-idle-states = <&LITTLE_CPU_SLEEP_0 +- &LITTLE_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- next-level-cache = <&L2_0>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- #cooling-cells = <2>; +- L2_0: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- L3_0: l3-cache { +- compatible = "cache"; +- }; +- }; +- }; +- +- CPU1: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,kryo"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- cpu-idle-states = <&LITTLE_CPU_SLEEP_0 +- &LITTLE_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- next-level-cache = <&L2_100>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- #cooling-cells = <2>; +- L2_100: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU2: cpu@200 { +- device_type = "cpu"; +- compatible = "arm,kryo"; +- reg = <0x0 0x200>; +- enable-method = "psci"; +- cpu-idle-states = <&LITTLE_CPU_SLEEP_0 +- &LITTLE_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- next-level-cache = <&L2_200>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- #cooling-cells = <2>; +- L2_200: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU3: cpu@300 { +- device_type = "cpu"; +- compatible = "arm,kryo"; +- reg = <0x0 0x300>; +- enable-method = "psci"; +- cpu-idle-states = <&LITTLE_CPU_SLEEP_0 +- &LITTLE_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- next-level-cache = <&L2_300>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- #cooling-cells = <2>; +- L2_300: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU4: cpu@400 { +- device_type = "cpu"; +- compatible = "arm,kryo"; +- reg = <0x0 0x400>; +- enable-method = "psci"; +- cpu-idle-states = <&BIG_CPU_SLEEP_0 +- &BIG_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- next-level-cache = <&L2_400>; +- qcom,freq-domain = <&cpufreq_hw 1>; +- #cooling-cells = <2>; +- L2_400: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU5: cpu@500 { +- device_type = "cpu"; +- compatible = "arm,kryo"; +- reg = <0x0 0x500>; +- enable-method = "psci"; +- cpu-idle-states = <&BIG_CPU_SLEEP_0 +- &BIG_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- next-level-cache = <&L2_500>; +- qcom,freq-domain = <&cpufreq_hw 1>; +- #cooling-cells = <2>; +- L2_500: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU6: cpu@600 { +- device_type = "cpu"; +- compatible = "arm,kryo"; +- reg = <0x0 0x600>; +- enable-method = "psci"; +- cpu-idle-states = <&BIG_CPU_SLEEP_0 +- &BIG_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- next-level-cache = <&L2_600>; +- qcom,freq-domain = <&cpufreq_hw 1>; +- #cooling-cells = <2>; +- L2_600: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU7: cpu@700 { +- device_type = "cpu"; +- compatible = "arm,kryo"; +- reg = <0x0 0x700>; +- enable-method = "psci"; +- cpu-idle-states = <&BIG_CPU_SLEEP_0 +- &BIG_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- next-level-cache = <&L2_700>; +- qcom,freq-domain = <&cpufreq_hw 2>; +- #cooling-cells = <2>; +- L2_700: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "little-power-down"; +- arm,psci-suspend-param = <0x40000003>; +- entry-latency-us = <549>; +- exit-latency-us = <901>; +- min-residency-us = <1774>; +- local-timer-stop; +- }; +- +- LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { +- compatible = "arm,idle-state"; +- idle-state-name = "little-rail-power-down"; +- arm,psci-suspend-param = <0x40000004>; +- entry-latency-us = <702>; +- exit-latency-us = <915>; +- min-residency-us = <4001>; +- local-timer-stop; +- }; +- +- BIG_CPU_SLEEP_0: cpu-sleep-1-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "big-power-down"; +- arm,psci-suspend-param = <0x40000003>; +- entry-latency-us = <523>; +- exit-latency-us = <1244>; +- min-residency-us = <2207>; +- local-timer-stop; +- }; +- +- BIG_CPU_SLEEP_1: cpu-sleep-1-1 { +- compatible = "arm,idle-state"; +- idle-state-name = "big-rail-power-down"; +- arm,psci-suspend-param = <0x40000004>; +- entry-latency-us = <526>; +- exit-latency-us = <1854>; +- min-residency-us = <5555>; +- local-timer-stop; +- }; +- +- CLUSTER_SLEEP_0: cluster-sleep-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "cluster-power-down"; +- arm,psci-suspend-param = <0x40003444>; +- entry-latency-us = <3263>; +- exit-latency-us = <6562>; +- min-residency-us = <9926>; +- local-timer-stop; +- }; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- /* We expect the bootloader to fill in the size */ +- reg = <0 0x80000000 0 0>; +- }; +- +- firmware { +- scm { +- compatible = "qcom,scm-sc7280", "qcom,scm"; +- }; +- }; +- +- clk_virt: interconnect { +- compatible = "qcom,sc7280-clk-virt"; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- smem { +- compatible = "qcom,smem"; +- memory-region = <&smem_mem>; +- hwlocks = <&tcsr_mutex 3>; +- }; +- +- smp2p-adsp { +- compatible = "qcom,smp2p"; +- qcom,smem = <443>, <429>; +- interrupts-extended = <&ipcc IPCC_CLIENT_LPASS +- IPCC_MPROC_SIGNAL_SMP2P +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_LPASS +- IPCC_MPROC_SIGNAL_SMP2P>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <2>; +- +- adsp_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- adsp_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-cdsp { +- compatible = "qcom,smp2p"; +- qcom,smem = <94>, <432>; +- interrupts-extended = <&ipcc IPCC_CLIENT_CDSP +- IPCC_MPROC_SIGNAL_SMP2P +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_CDSP +- IPCC_MPROC_SIGNAL_SMP2P>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <5>; +- +- cdsp_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- cdsp_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-mpss { +- compatible = "qcom,smp2p"; +- qcom,smem = <435>, <428>; +- interrupts-extended = <&ipcc IPCC_CLIENT_MPSS +- IPCC_MPROC_SIGNAL_SMP2P +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_MPSS +- IPCC_MPROC_SIGNAL_SMP2P>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <1>; +- +- modem_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- modem_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- ipa_smp2p_out: ipa-ap-to-modem { +- qcom,entry-name = "ipa"; +- #qcom,smem-state-cells = <1>; +- }; +- +- ipa_smp2p_in: ipa-modem-to-ap { +- qcom,entry-name = "ipa"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-wpss { +- compatible = "qcom,smp2p"; +- qcom,smem = <617>, <616>; +- interrupts-extended = <&ipcc IPCC_CLIENT_WPSS +- IPCC_MPROC_SIGNAL_SMP2P +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_WPSS +- IPCC_MPROC_SIGNAL_SMP2P>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <13>; +- +- wpss_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- wpss_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- soc: soc@0 { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0 0 0 0 0x10 0>; +- dma-ranges = <0 0 0 0 0x10 0>; +- compatible = "simple-bus"; +- +- gcc: clock-controller@100000 { +- compatible = "qcom,gcc-sc7280"; +- reg = <0 0x00100000 0 0x1f0000>; +- clocks = <&rpmhcc RPMH_CXO_CLK>, +- <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, +- <0>, <0>, <0>, <0>, <0>, <0>; +- clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", +- "pcie_0_pipe_clk", "pcie_1_pipe_clk", +- "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", +- "ufs_phy_tx_symbol_0_clk", +- "usb3_phy_wrapper_gcc_usb30_pipe_clk"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- }; +- +- ipcc: mailbox@408000 { +- compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; +- reg = <0 0x00408000 0 0x1000>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- #mbox-cells = <2>; +- }; +- +- qfprom: efuse@784000 { +- compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; +- reg = <0 0x00784000 0 0xa20>, +- <0 0x00780000 0 0xa20>, +- <0 0x00782000 0 0x120>, +- <0 0x00786000 0 0x1fff>; +- clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; +- clock-names = "core"; +- power-domains = <&rpmhpd SC7280_MX>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- sdhc_1: sdhci@7c4000 { +- compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; +- status = "disabled"; +- +- reg = <0 0x007c4000 0 0x1000>, +- <0 0x007c5000 0 0x1000>; +- reg-names = "hc", "cqhci"; +- +- iommus = <&apps_smmu 0xc0 0x0>; +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- +- clocks = <&gcc GCC_SDCC1_APPS_CLK>, +- <&gcc GCC_SDCC1_AHB_CLK>, +- <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "core", "iface", "xo"; +- interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; +- interconnect-names = "sdhc-ddr","cpu-sdhc"; +- power-domains = <&rpmhpd SC7280_CX>; +- operating-points-v2 = <&sdhc1_opp_table>; +- +- bus-width = <8>; +- supports-cqe; +- +- qcom,dll-config = <0x0007642c>; +- qcom,ddr-config = <0x80040868>; +- +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- +- sdhc1_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- opp-peak-kBps = <1800000 400000>; +- opp-avg-kBps = <100000 0>; +- }; +- +- opp-384000000 { +- opp-hz = /bits/ 64 <384000000>; +- required-opps = <&rpmhpd_opp_nom>; +- opp-peak-kBps = <5400000 1600000>; +- opp-avg-kBps = <390000 0>; +- }; +- }; +- +- }; +- +- qupv3_id_0: geniqup@9c0000 { +- compatible = "qcom,geni-se-qup"; +- reg = <0 0x009c0000 0 0x2000>; +- clock-names = "m-ahb", "s-ahb"; +- clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, +- <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "disabled"; +- +- uart5: serial@994000 { +- compatible = "qcom,geni-debug-uart"; +- reg = <0 0x00994000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart5_default>; +- interrupts = ; +- status = "disabled"; +- }; +- }; +- +- cnoc2: interconnect@1500000 { +- reg = <0 0x01500000 0 0x1000>; +- compatible = "qcom,sc7280-cnoc2"; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- cnoc3: interconnect@1502000 { +- reg = <0 0x01502000 0 0x1000>; +- compatible = "qcom,sc7280-cnoc3"; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- mc_virt: interconnect@1580000 { +- reg = <0 0x01580000 0 0x4>; +- compatible = "qcom,sc7280-mc-virt"; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- system_noc: interconnect@1680000 { +- reg = <0 0x01680000 0 0x15480>; +- compatible = "qcom,sc7280-system-noc"; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- aggre1_noc: interconnect@16e0000 { +- compatible = "qcom,sc7280-aggre1-noc"; +- reg = <0 0x016e0000 0 0x1c080>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- aggre2_noc: interconnect@1700000 { +- reg = <0 0x01700000 0 0x2b080>; +- compatible = "qcom,sc7280-aggre2-noc"; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- mmss_noc: interconnect@1740000 { +- reg = <0 0x01740000 0 0x1e080>; +- compatible = "qcom,sc7280-mmss-noc"; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- ipa: ipa@1e40000 { +- compatible = "qcom,sc7280-ipa"; +- +- iommus = <&apps_smmu 0x480 0x0>, +- <&apps_smmu 0x482 0x0>; +- reg = <0 0x1e40000 0 0x8000>, +- <0 0x1e50000 0 0x4ad0>, +- <0 0x1e04000 0 0x23000>; +- reg-names = "ipa-reg", +- "ipa-shared", +- "gsi"; +- +- interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>, +- <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, +- <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "ipa", +- "gsi", +- "ipa-clock-query", +- "ipa-setup-ready"; +- +- clocks = <&rpmhcc RPMH_IPA_CLK>; +- clock-names = "core"; +- +- interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; +- interconnect-names = "memory", +- "config"; +- +- qcom,smem-states = <&ipa_smp2p_out 0>, +- <&ipa_smp2p_out 1>; +- qcom,smem-state-names = "ipa-clock-enabled-valid", +- "ipa-clock-enabled"; +- +- status = "disabled"; +- }; +- +- tcsr_mutex: hwlock@1f40000 { +- compatible = "qcom,tcsr-mutex", "syscon"; +- reg = <0 0x01f40000 0 0x40000>; +- #hwlock-cells = <1>; +- }; +- +- lpasscc: lpasscc@3000000 { +- compatible = "qcom,sc7280-lpasscc"; +- reg = <0 0x03000000 0 0x40>, +- <0 0x03c04000 0 0x4>, +- <0 0x03389000 0 0x24>; +- reg-names = "qdsp6ss", "top_cc", "cc"; +- clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; +- clock-names = "iface"; +- #clock-cells = <1>; +- }; +- +- lpass_ag_noc: interconnect@3c40000 { +- reg = <0 0x03c40000 0 0xf080>; +- compatible = "qcom,sc7280-lpass-ag-noc"; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- gpucc: clock-controller@3d90000 { +- compatible = "qcom,sc7280-gpucc"; +- reg = <0 0x03d90000 0 0x9000>; +- clocks = <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_GPU_GPLL0_CLK_SRC>, +- <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; +- clock-names = "bi_tcxo", +- "gcc_gpu_gpll0_clk_src", +- "gcc_gpu_gpll0_div_clk_src"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- }; +- +- stm@6002000 { +- compatible = "arm,coresight-stm", "arm,primecell"; +- reg = <0 0x06002000 0 0x1000>, +- <0 0x16280000 0 0x180000>; +- reg-names = "stm-base", "stm-stimulus-base"; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- stm_out: endpoint { +- remote-endpoint = <&funnel0_in7>; +- }; +- }; +- }; +- }; +- +- funnel@6041000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x06041000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- funnel0_out: endpoint { +- remote-endpoint = <&merge_funnel_in0>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@7 { +- reg = <7>; +- funnel0_in7: endpoint { +- remote-endpoint = <&stm_out>; +- }; +- }; +- }; +- }; +- +- funnel@6042000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x06042000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- funnel1_out: endpoint { +- remote-endpoint = <&merge_funnel_in1>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@4 { +- reg = <4>; +- funnel1_in4: endpoint { +- remote-endpoint = <&apss_merge_funnel_out>; +- }; +- }; +- }; +- }; +- +- funnel@6045000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x06045000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- merge_funnel_out: endpoint { +- remote-endpoint = <&swao_funnel_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- merge_funnel_in0: endpoint { +- remote-endpoint = <&funnel0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- merge_funnel_in1: endpoint { +- remote-endpoint = <&funnel1_out>; +- }; +- }; +- }; +- }; +- +- replicator@6046000 { +- compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; +- reg = <0 0x06046000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- replicator_out: endpoint { +- remote-endpoint = <&etr_in>; +- }; +- }; +- }; +- +- in-ports { +- port { +- replicator_in: endpoint { +- remote-endpoint = <&swao_replicator_out>; +- }; +- }; +- }; +- }; +- +- etr@6048000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0x06048000 0 0x1000>; +- iommus = <&apps_smmu 0x04c0 0>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,scatter-gather; +- +- in-ports { +- port { +- etr_in: endpoint { +- remote-endpoint = <&replicator_out>; +- }; +- }; +- }; +- }; +- +- funnel@6b04000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x06b04000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- swao_funnel_out: endpoint { +- remote-endpoint = <&etf_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@7 { +- reg = <7>; +- swao_funnel_in: endpoint { +- remote-endpoint = <&merge_funnel_out>; +- }; +- }; +- }; +- }; +- +- etf@6b05000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0x06b05000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etf_out: endpoint { +- remote-endpoint = <&swao_replicator_in>; +- }; +- }; +- }; +- +- in-ports { +- port { +- etf_in: endpoint { +- remote-endpoint = <&swao_funnel_out>; +- }; +- }; +- }; +- }; +- +- replicator@6b06000 { +- compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; +- reg = <0 0x06b06000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- qcom,replicator-loses-context; +- +- out-ports { +- port { +- swao_replicator_out: endpoint { +- remote-endpoint = <&replicator_in>; +- }; +- }; +- }; +- +- in-ports { +- port { +- swao_replicator_in: endpoint { +- remote-endpoint = <&etf_out>; +- }; +- }; +- }; +- }; +- +- etm@7040000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07040000 0 0x1000>; +- +- cpu = <&CPU0>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm0_out: endpoint { +- remote-endpoint = <&apss_funnel_in0>; +- }; +- }; +- }; +- }; +- +- etm@7140000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07140000 0 0x1000>; +- +- cpu = <&CPU1>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm1_out: endpoint { +- remote-endpoint = <&apss_funnel_in1>; +- }; +- }; +- }; +- }; +- +- etm@7240000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07240000 0 0x1000>; +- +- cpu = <&CPU2>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm2_out: endpoint { +- remote-endpoint = <&apss_funnel_in2>; +- }; +- }; +- }; +- }; +- +- etm@7340000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07340000 0 0x1000>; +- +- cpu = <&CPU3>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm3_out: endpoint { +- remote-endpoint = <&apss_funnel_in3>; +- }; +- }; +- }; +- }; +- +- etm@7440000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07440000 0 0x1000>; +- +- cpu = <&CPU4>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm4_out: endpoint { +- remote-endpoint = <&apss_funnel_in4>; +- }; +- }; +- }; +- }; +- +- etm@7540000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07540000 0 0x1000>; +- +- cpu = <&CPU5>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm5_out: endpoint { +- remote-endpoint = <&apss_funnel_in5>; +- }; +- }; +- }; +- }; +- +- etm@7640000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07640000 0 0x1000>; +- +- cpu = <&CPU6>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm6_out: endpoint { +- remote-endpoint = <&apss_funnel_in6>; +- }; +- }; +- }; +- }; +- +- etm@7740000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07740000 0 0x1000>; +- +- cpu = <&CPU7>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm7_out: endpoint { +- remote-endpoint = <&apss_funnel_in7>; +- }; +- }; +- }; +- }; +- +- funnel@7800000 { /* APSS Funnel */ +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x07800000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- apss_funnel_out: endpoint { +- remote-endpoint = <&apss_merge_funnel_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- apss_funnel_in0: endpoint { +- remote-endpoint = <&etm0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- apss_funnel_in1: endpoint { +- remote-endpoint = <&etm1_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- apss_funnel_in2: endpoint { +- remote-endpoint = <&etm2_out>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- apss_funnel_in3: endpoint { +- remote-endpoint = <&etm3_out>; +- }; +- }; +- +- port@4 { +- reg = <4>; +- apss_funnel_in4: endpoint { +- remote-endpoint = <&etm4_out>; +- }; +- }; +- +- port@5 { +- reg = <5>; +- apss_funnel_in5: endpoint { +- remote-endpoint = <&etm5_out>; +- }; +- }; +- +- port@6 { +- reg = <6>; +- apss_funnel_in6: endpoint { +- remote-endpoint = <&etm6_out>; +- }; +- }; +- +- port@7 { +- reg = <7>; +- apss_funnel_in7: endpoint { +- remote-endpoint = <&etm7_out>; +- }; +- }; +- }; +- }; +- +- funnel@7810000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x07810000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- apss_merge_funnel_out: endpoint { +- remote-endpoint = <&funnel1_in4>; +- }; +- }; +- }; +- +- in-ports { +- port { +- apss_merge_funnel_in: endpoint { +- remote-endpoint = <&apss_funnel_out>; +- }; +- }; +- }; +- }; +- +- sdhc_2: sdhci@8804000 { +- compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; +- status = "disabled"; +- +- reg = <0 0x08804000 0 0x1000>; +- +- iommus = <&apps_smmu 0x100 0x0>; +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- +- clocks = <&gcc GCC_SDCC2_APPS_CLK>, +- <&gcc GCC_SDCC2_AHB_CLK>, +- <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "core", "iface", "xo"; +- interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; +- interconnect-names = "sdhc-ddr","cpu-sdhc"; +- power-domains = <&rpmhpd SC7280_CX>; +- operating-points-v2 = <&sdhc2_opp_table>; +- +- bus-width = <4>; +- +- qcom,dll-config = <0x0007642c>; +- +- sdhc2_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- opp-peak-kBps = <1800000 400000>; +- opp-avg-kBps = <100000 0>; +- }; +- +- opp-202000000 { +- opp-hz = /bits/ 64 <202000000>; +- required-opps = <&rpmhpd_opp_nom>; +- opp-peak-kBps = <5400000 1600000>; +- opp-avg-kBps = <200000 0>; +- }; +- }; +- +- }; +- +- usb_1_hsphy: phy@88e3000 { +- compatible = "qcom,sc7280-usb-hs-phy", +- "qcom,usb-snps-hs-7nm-phy"; +- reg = <0 0x088e3000 0 0x400>; +- status = "disabled"; +- #phy-cells = <0>; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "ref"; +- +- resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; +- }; +- +- usb_2_hsphy: phy@88e4000 { +- compatible = "qcom,sc7280-usb-hs-phy", +- "qcom,usb-snps-hs-7nm-phy"; +- reg = <0 0x088e4000 0 0x400>; +- status = "disabled"; +- #phy-cells = <0>; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "ref"; +- +- resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; +- }; +- +- usb_1_qmpphy: phy-wrapper@88e9000 { +- compatible = "qcom,sc7280-qmp-usb3-dp-phy", +- "qcom,sm8250-qmp-usb3-dp-phy"; +- reg = <0 0x088e9000 0 0x200>, +- <0 0x088e8000 0 0x40>, +- <0 0x088ea000 0 0x200>; +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, +- <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; +- clock-names = "aux", "ref_clk_src", "com_aux"; +- +- resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, +- <&gcc GCC_USB3_PHY_PRIM_BCR>; +- reset-names = "phy", "common"; +- +- usb_1_ssphy: usb3-phy@88e9200 { +- reg = <0 0x088e9200 0 0x200>, +- <0 0x088e9400 0 0x200>, +- <0 0x088e9c00 0 0x400>, +- <0 0x088e9600 0 0x200>, +- <0 0x088e9800 0 0x200>, +- <0 0x088e9a00 0 0x100>; +- #clock-cells = <0>; +- #phy-cells = <0>; +- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; +- clock-names = "pipe0"; +- clock-output-names = "usb3_phy_pipe_clk_src"; +- }; +- +- dp_phy: dp-phy@88ea200 { +- reg = <0 0x088ea200 0 0x200>, +- <0 0x088ea400 0 0x200>, +- <0 0x088eaa00 0 0x200>, +- <0 0x088ea600 0 0x200>, +- <0 0x088ea800 0 0x200>; +- #phy-cells = <0>; +- #clock-cells = <1>; +- }; +- }; +- +- usb_2: usb@8cf8800 { +- compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; +- reg = <0 0x08cf8800 0 0x400>; +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- dma-ranges; +- +- clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, +- <&gcc GCC_USB30_SEC_MASTER_CLK>, +- <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, +- <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_SEC_SLEEP_CLK>; +- clock-names = "cfg_noc", "core", "iface","mock_utmi", +- "sleep"; +- +- assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_SEC_MASTER_CLK>; +- assigned-clock-rates = <19200000>, <200000000>; +- +- interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, +- <&pdc 13 IRQ_TYPE_EDGE_RISING>, +- <&pdc 12 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "hs_phy_irq", +- "dm_hs_phy_irq", "dp_hs_phy_irq"; +- +- power-domains = <&gcc GCC_USB30_SEC_GDSC>; +- +- resets = <&gcc GCC_USB30_SEC_BCR>; +- +- interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; +- interconnect-names = "usb-ddr", "apps-usb"; +- +- usb_2_dwc3: usb@8c00000 { +- compatible = "snps,dwc3"; +- reg = <0 0x08c00000 0 0xe000>; +- interrupts = ; +- iommus = <&apps_smmu 0xa0 0x0>; +- snps,dis_u2_susphy_quirk; +- snps,dis_enblslpm_quirk; +- phys = <&usb_2_hsphy>; +- phy-names = "usb2-phy"; +- maximum-speed = "high-speed"; +- }; +- }; +- +- dc_noc: interconnect@90e0000 { +- reg = <0 0x090e0000 0 0x5080>; +- compatible = "qcom,sc7280-dc-noc"; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- gem_noc: interconnect@9100000 { +- reg = <0 0x9100000 0 0xe2200>; +- compatible = "qcom,sc7280-gem-noc"; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- system-cache-controller@9200000 { +- compatible = "qcom,sc7280-llcc"; +- reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; +- reg-names = "llcc_base", "llcc_broadcast_base"; +- interrupts = ; +- }; +- +- nsp_noc: interconnect@a0c0000 { +- reg = <0 0x0a0c0000 0 0x10000>; +- compatible = "qcom,sc7280-nsp-noc"; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- usb_1: usb@a6f8800 { +- compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; +- reg = <0 0x0a6f8800 0 0x400>; +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- dma-ranges; +- +- clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, +- <&gcc GCC_USB30_PRIM_MASTER_CLK>, +- <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, +- <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_PRIM_SLEEP_CLK>; +- clock-names = "cfg_noc", "core", "iface", "mock_utmi", +- "sleep"; +- +- assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_PRIM_MASTER_CLK>; +- assigned-clock-rates = <19200000>, <200000000>; +- +- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, +- <&pdc 14 IRQ_TYPE_EDGE_BOTH>, +- <&pdc 15 IRQ_TYPE_EDGE_BOTH>, +- <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", +- "dm_hs_phy_irq", "ss_phy_irq"; +- +- power-domains = <&gcc GCC_USB30_PRIM_GDSC>; +- +- resets = <&gcc GCC_USB30_PRIM_BCR>; +- +- interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, +- <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; +- interconnect-names = "usb-ddr", "apps-usb"; +- +- usb_1_dwc3: usb@a600000 { +- compatible = "snps,dwc3"; +- reg = <0 0x0a600000 0 0xe000>; +- interrupts = ; +- iommus = <&apps_smmu 0xe0 0x0>; +- snps,dis_u2_susphy_quirk; +- snps,dis_enblslpm_quirk; +- phys = <&usb_1_hsphy>, <&usb_1_ssphy>; +- phy-names = "usb2-phy", "usb3-phy"; +- maximum-speed = "super-speed"; +- }; +- }; +- +- videocc: clock-controller@aaf0000 { +- compatible = "qcom,sc7280-videocc"; +- reg = <0 0xaaf0000 0 0x10000>; +- clocks = <&rpmhcc RPMH_CXO_CLK>, +- <&rpmhcc RPMH_CXO_CLK_A>; +- clock-names = "bi_tcxo", "bi_tcxo_ao"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- }; +- +- dispcc: clock-controller@af00000 { +- compatible = "qcom,sc7280-dispcc"; +- reg = <0 0xaf00000 0 0x20000>; +- clocks = <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_DISP_GPLL0_CLK_SRC>, +- <0>, <0>, <0>, <0>, <0>, <0>; +- clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", +- "dsi0_phy_pll_out_byteclk", +- "dsi0_phy_pll_out_dsiclk", +- "dp_phy_pll_link_clk", +- "dp_phy_pll_vco_div_clk", +- "edp_phy_pll_link_clk", +- "edp_phy_pll_vco_div_clk"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- }; +- +- pdc: interrupt-controller@b220000 { +- compatible = "qcom,sc7280-pdc", "qcom,pdc"; +- reg = <0 0x0b220000 0 0x30000>; +- qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, +- <55 306 4>, <59 312 3>, <62 374 2>, +- <64 434 2>, <66 438 3>, <69 86 1>, +- <70 520 54>, <124 609 31>, <155 63 1>, +- <156 716 12>; +- #interrupt-cells = <2>; +- interrupt-parent = <&intc>; +- interrupt-controller; +- }; +- +- pdc_reset: reset-controller@b5e0000 { +- compatible = "qcom,sc7280-pdc-global"; +- reg = <0 0x0b5e0000 0 0x20000>; +- #reset-cells = <1>; +- }; +- +- tsens0: thermal-sensor@c263000 { +- compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; +- reg = <0 0x0c263000 0 0x1ff>, /* TM */ +- <0 0x0c222000 0 0x1ff>; /* SROT */ +- #qcom,sensors = <15>; +- interrupts = , +- ; +- interrupt-names = "uplow","critical"; +- #thermal-sensor-cells = <1>; +- }; +- +- tsens1: thermal-sensor@c265000 { +- compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; +- reg = <0 0x0c265000 0 0x1ff>, /* TM */ +- <0 0x0c223000 0 0x1ff>; /* SROT */ +- #qcom,sensors = <12>; +- interrupts = , +- ; +- interrupt-names = "uplow","critical"; +- #thermal-sensor-cells = <1>; +- }; +- +- aoss_reset: reset-controller@c2a0000 { +- compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; +- reg = <0 0x0c2a0000 0 0x31000>; +- #reset-cells = <1>; +- }; +- +- aoss_qmp: power-controller@c300000 { +- compatible = "qcom,sc7280-aoss-qmp"; +- reg = <0 0x0c300000 0 0x100000>; +- interrupts-extended = <&ipcc IPCC_CLIENT_AOP +- IPCC_MPROC_SIGNAL_GLINK_QMP +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_AOP +- IPCC_MPROC_SIGNAL_GLINK_QMP>; +- +- #clock-cells = <0>; +- #power-domain-cells = <1>; +- }; +- +- spmi_bus: spmi@c440000 { +- compatible = "qcom,spmi-pmic-arb"; +- reg = <0 0x0c440000 0 0x1100>, +- <0 0x0c600000 0 0x2000000>, +- <0 0x0e600000 0 0x100000>, +- <0 0x0e700000 0 0xa0000>, +- <0 0x0c40a000 0 0x26000>; +- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; +- interrupt-names = "periph_irq"; +- interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; +- qcom,ee = <0>; +- qcom,channel = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-controller; +- #interrupt-cells = <4>; +- }; +- +- tlmm: pinctrl@f100000 { +- compatible = "qcom,sc7280-pinctrl"; +- reg = <0 0x0f100000 0 0x300000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&tlmm 0 0 175>; +- wakeup-parent = <&pdc>; +- +- qup_uart5_default: qup-uart5-default { +- pins = "gpio46", "gpio47"; +- function = "qup13"; +- }; +- +- sdc1_on: sdc1-on { +- clk { +- pins = "sdc1_clk"; +- }; +- +- cmd { +- pins = "sdc1_cmd"; +- }; +- +- data { +- pins = "sdc1_data"; +- }; +- +- rclk { +- pins = "sdc1_rclk"; +- }; +- }; +- +- sdc1_off: sdc1-off { +- clk { +- pins = "sdc1_clk"; +- drive-strength = <2>; +- bias-bus-hold; +- }; +- +- cmd { +- pins = "sdc1_cmd"; +- drive-strength = <2>; +- bias-bus-hold; +- }; +- +- data { +- pins = "sdc1_data"; +- drive-strength = <2>; +- bias-bus-hold; +- }; +- +- rclk { +- pins = "sdc1_rclk"; +- bias-bus-hold; +- }; +- }; +- +- sdc2_on: sdc2-on { +- clk { +- pins = "sdc2_clk"; +- }; +- +- cmd { +- pins = "sdc2_cmd"; +- }; +- +- data { +- pins = "sdc2_data"; +- }; +- +- sd-cd { +- pins = "gpio91"; +- }; +- }; +- +- sdc2_off: sdc2-off { +- clk { +- pins = "sdc2_clk"; +- drive-strength = <2>; +- bias-bus-hold; +- }; +- +- cmd { +- pins ="sdc2_cmd"; +- drive-strength = <2>; +- bias-bus-hold; +- }; +- +- data { +- pins ="sdc2_data"; +- drive-strength = <2>; +- bias-bus-hold; +- }; +- }; +- }; +- +- apps_smmu: iommu@15000000 { +- compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; +- reg = <0 0x15000000 0 0x100000>; +- #iommu-cells = <2>; +- #global-interrupts = <1>; +- dma-coherent; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- }; +- +- intc: interrupt-controller@17a00000 { +- compatible = "arm,gic-v3"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0 0x17a00000 0 0x10000>, /* GICD */ +- <0 0x17a60000 0 0x100000>; /* GICR * 8 */ +- interrupts = ; +- +- gic-its@17a40000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0 0x17a40000 0 0x20000>; +- status = "disabled"; +- }; +- }; +- +- watchdog@17c10000 { +- compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; +- reg = <0 0x17c10000 0 0x1000>; +- clocks = <&sleep_clk>; +- interrupts = ; +- }; +- +- timer@17c20000 { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- compatible = "arm,armv7-timer-mem"; +- reg = <0 0x17c20000 0 0x1000>; +- +- frame@17c21000 { +- frame-number = <0>; +- interrupts = , +- ; +- reg = <0 0x17c21000 0 0x1000>, +- <0 0x17c22000 0 0x1000>; +- }; +- +- frame@17c23000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0 0x17c23000 0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c25000 { +- frame-number = <2>; +- interrupts = ; +- reg = <0 0x17c25000 0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c27000 { +- frame-number = <3>; +- interrupts = ; +- reg = <0 0x17c27000 0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c29000 { +- frame-number = <4>; +- interrupts = ; +- reg = <0 0x17c29000 0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c2b000 { +- frame-number = <5>; +- interrupts = ; +- reg = <0 0x17c2b000 0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c2d000 { +- frame-number = <6>; +- interrupts = ; +- reg = <0 0x17c2d000 0 0x1000>; +- status = "disabled"; +- }; +- }; +- +- apps_rsc: rsc@18200000 { +- compatible = "qcom,rpmh-rsc"; +- reg = <0 0x18200000 0 0x10000>, +- <0 0x18210000 0 0x10000>, +- <0 0x18220000 0 0x10000>; +- reg-names = "drv-0", "drv-1", "drv-2"; +- interrupts = , +- , +- ; +- qcom,tcs-offset = <0xd00>; +- qcom,drv-id = <2>; +- qcom,tcs-config = , +- , +- , +- ; +- +- apps_bcm_voter: bcm-voter { +- compatible = "qcom,bcm-voter"; +- }; +- +- rpmhpd: power-controller { +- compatible = "qcom,sc7280-rpmhpd"; +- #power-domain-cells = <1>; +- operating-points-v2 = <&rpmhpd_opp_table>; +- +- rpmhpd_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- rpmhpd_opp_ret: opp1 { +- opp-level = ; +- }; +- +- rpmhpd_opp_low_svs: opp2 { +- opp-level = ; +- }; +- +- rpmhpd_opp_svs: opp3 { +- opp-level = ; +- }; +- +- rpmhpd_opp_svs_l1: opp4 { +- opp-level = ; +- }; +- +- rpmhpd_opp_svs_l2: opp5 { +- opp-level = ; +- }; +- +- rpmhpd_opp_nom: opp6 { +- opp-level = ; +- }; +- +- rpmhpd_opp_nom_l1: opp7 { +- opp-level = ; +- }; +- +- rpmhpd_opp_turbo: opp8 { +- opp-level = ; +- }; +- +- rpmhpd_opp_turbo_l1: opp9 { +- opp-level = ; +- }; +- }; +- }; +- +- rpmhcc: clock-controller { +- compatible = "qcom,sc7280-rpmh-clk"; +- clocks = <&xo_board>; +- clock-names = "xo"; +- #clock-cells = <1>; +- }; +- }; +- +- cpufreq_hw: cpufreq@18591000 { +- compatible = "qcom,cpufreq-epss"; +- reg = <0 0x18591000 0 0x1000>, +- <0 0x18592000 0 0x1000>, +- <0 0x18593000 0 0x1000>; +- clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; +- clock-names = "xo", "alternate"; +- #freq-domain-cells = <1>; +- }; +- }; +- +- thermal_zones: thermal-zones { +- cpu0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 1>; +- +- trips { +- cpu0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu0_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu0_crit: cpu-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu0_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu0_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 2>; +- +- trips { +- cpu1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu1_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu1_crit: cpu-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu1_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu1_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 3>; +- +- trips { +- cpu2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu2_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu2_crit: cpu-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu2_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu2_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 4>; +- +- trips { +- cpu3_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu3_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu3_crit: cpu-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu3_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu3_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu4-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 7>; +- +- trips { +- cpu4_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu4_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu4_crit: cpu-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu4_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu4_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu5-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 8>; +- +- trips { +- cpu5_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu5_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu5_crit: cpu-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu5_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu5_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu6-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 9>; +- +- trips { +- cpu6_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu6_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu6_crit: cpu-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu6_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu6_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu7-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 10>; +- +- trips { +- cpu7_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu7_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu7_crit: cpu-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu7_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu7_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu8-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 11>; +- +- trips { +- cpu8_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu8_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu8_crit: cpu-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu8_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu8_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu9-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 12>; +- +- trips { +- cpu9_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu9_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu9_crit: cpu-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu9_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu9_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu10-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 13>; +- +- trips { +- cpu10_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu10_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu10_crit: cpu-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu10_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu10_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu11-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 14>; +- +- trips { +- cpu11_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu11_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu11_crit: cpu-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu11_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu11_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- aoss0-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 0>; +- +- trips { +- aoss0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- aoss0_crit: aoss0-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- aoss1-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 0>; +- +- trips { +- aoss1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- aoss1_crit: aoss1-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- cpuss0-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 5>; +- +- trips { +- cpuss0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- cpuss0_crit: cluster0-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- cpuss1-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens0 6>; +- +- trips { +- cpuss1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- cpuss1_crit: cluster0-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- gpuss0-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 1>; +- +- trips { +- gpuss0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- gpuss0_crit: gpuss0-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- gpuss1-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 2>; +- +- trips { +- gpuss1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- gpuss1_crit: gpuss1-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- nspss0-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 3>; +- +- trips { +- nspss0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- nspss0_crit: nspss0-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- nspss1-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 4>; +- +- trips { +- nspss1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- nspss1_crit: nspss1-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- video-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 5>; +- +- trips { +- video_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- video_crit: video-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- ddr-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 6>; +- +- trips { +- ddr_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- ddr_crit: ddr-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- mdmss0-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 7>; +- +- trips { +- mdmss0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- mdmss0_crit: mdmss0-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- mdmss1-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 8>; +- +- trips { +- mdmss1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- mdmss1_crit: mdmss1-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- mdmss2-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 9>; +- +- trips { +- mdmss2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- mdmss2_crit: mdmss2-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- mdmss3-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 10>; +- +- trips { +- mdmss3_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- mdmss3_crit: mdmss3-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- +- camera0-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- +- thermal-sensors = <&tsens1 11>; +- +- trips { +- camera0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- camera0_crit: camera0-crit { +- temperature = <110000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm630-sony-xperia-ganges-kirin.dts b/scripts/dtc/include-prefixes/arm64/qcom/sdm630-sony-xperia-ganges-kirin.dts +deleted file mode 100644 +index a4e1fb8ca52d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm630-sony-xperia-ganges-kirin.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Martin Botka +- */ +- +-/dts-v1/; +- +-#include "sdm630.dtsi" +-#include "sdm630-sony-xperia-nile.dtsi" +- +-/ { +- model = "Sony Xperia 10"; +- compatible = "sony,kirin-row", "qcom,sdm630"; +- +- chosen { +- framebuffer@9d400000 { +- reg = <0 0x9d400000 0 (2520 * 1080 * 4)>; +- height = <2520>; +- }; +- }; +-}; +- +-/* Ganges devices feature a Novatek touchscreen instead. */ +-/delete-node/ &touchscreen; +-/delete-node/ &vreg_l18a_1v8; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm630-sony-xperia-nile-discovery.dts b/scripts/dtc/include-prefixes/arm64/qcom/sdm630-sony-xperia-nile-discovery.dts +deleted file mode 100644 +index c574e430ba67..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm630-sony-xperia-nile-discovery.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Konrad Dybcio +- */ +- +-/dts-v1/; +- +-#include "sdm630.dtsi" +-#include "sdm630-sony-xperia-nile.dtsi" +- +-/ { +- model = "Sony Xperia XA2 Ultra"; +- compatible = "sony,discovery-row", "qcom,sdm630"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm630-sony-xperia-nile-pioneer.dts b/scripts/dtc/include-prefixes/arm64/qcom/sdm630-sony-xperia-nile-pioneer.dts +deleted file mode 100644 +index a93ff3ab1b6d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm630-sony-xperia-nile-pioneer.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Konrad Dybcio +- */ +- +-/dts-v1/; +- +-#include "sdm630.dtsi" +-#include "sdm630-sony-xperia-nile.dtsi" +- +-/ { +- model = "Sony Xperia XA2"; +- compatible = "sony,pioneer-row", "qcom,sdm630"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm630-sony-xperia-nile-voyager.dts b/scripts/dtc/include-prefixes/arm64/qcom/sdm630-sony-xperia-nile-voyager.dts +deleted file mode 100644 +index 59a679c205e0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm630-sony-xperia-nile-voyager.dts ++++ /dev/null +@@ -1,21 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Konrad Dybcio +- */ +- +-/dts-v1/; +- +-#include "sdm630.dtsi" +-#include "sdm630-sony-xperia-nile.dtsi" +- +-/ { +- model = "Sony Xperia XA2 Plus"; +- compatible = "sony,voyager-row", "qcom,sdm630"; +- +- chosen { +- framebuffer@9d400000 { +- reg = <0 0x9d400000 0 (2160 * 1080 * 4)>; +- height = <2160>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm630-sony-xperia-nile.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sdm630-sony-xperia-nile.dtsi +deleted file mode 100644 +index 849900e8b80e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm630-sony-xperia-nile.dtsi ++++ /dev/null +@@ -1,617 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Konrad Dybcio +- * Copyright (c) 2020, AngeloGioacchino Del Regno +- * +- */ +- +-#include "pm660.dtsi" +-#include "pm660l.dtsi" +-#include +-#include +-#include +- +-/ { +- /* required for bootloader to select correct board */ +- qcom,msm-id = <318 0>; +- qcom,board-id = <8 1>; +- qcom,pmic-id = <0x1001b 0x101011a 0x00 0x00 0x1001b 0x201011a 0x00 0x00>; +- +- /* This part enables graphical output via bootloader-enabled display */ +- chosen { +- bootargs = "earlycon=tty0 console=tty0"; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- stdout-path = "framebuffer0"; +- +- framebuffer0: framebuffer@9d400000 { +- compatible = "simple-framebuffer"; +- reg = <0 0x9d400000 0 (1920 * 1080 * 4)>; +- width = <1080>; +- height = <1920>; +- stride = <(1080 * 4)>; +- format = "a8r8g8b8"; +- status= "okay"; +- }; +- }; +- +- board_vbat: vbat-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "VBAT"; +- +- regulator-min-microvolt = <4000000>; +- regulator-max-microvolt = <4000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- +- regulator-always-on; +- regulator-boot-on; +- }; +- +- cam_vdig_imx300_219_vreg: cam_vdig_imx300_219_vreg { +- compatible = "regulator-fixed"; +- regulator-name = "cam_vdig_imx300_219_vreg"; +- startup-delay-us = <0>; +- enable-active-high; +- gpio = <&tlmm 52 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cam_vdig_default>; +- }; +- +- cam_vana_front_vreg: cam_vana_front_vreg { +- compatible = "regulator-fixed"; +- regulator-name = "cam_vana_front_vreg"; +- startup-delay-us = <0>; +- enable-active-high; +- gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&imx219_vana_default>; +- }; +- +- cam_vana_rear_vreg: cam_vana_rear_vreg { +- compatible = "regulator-fixed"; +- regulator-name = "cam_vana_rear_vreg"; +- startup-delay-us = <0>; +- enable-active-high; +- gpio = <&tlmm 50 GPIO_ACTIVE_HIGH>; +- regulator-always-on; +- pinctrl-names = "default"; +- pinctrl-0 = <&imx300_vana_default>; +- }; +- +- gpio_keys { +- status = "okay"; +- compatible = "gpio-keys"; +- input-name = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- camera_focus { +- label = "Camera Focus"; +- gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- debounce-interval = <15>; +- }; +- +- camera_snapshot { +- label = "Camera Snapshot"; +- gpios = <&tlmm 113 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- debounce-interval = <15>; +- }; +- +- vol_down { +- label = "Volume Down"; +- gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- gpio-key,wakeup; +- debounce-interval = <15>; +- }; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ramoops@ffc00000 { +- compatible = "ramoops"; +- reg = <0x0 0xffc00000 0x0 0x100000>; +- record-size = <0x10000>; +- console-size = <0x60000>; +- ftrace-size = <0x10000>; +- pmsg-size = <0x20000>; +- ecc-size = <16>; +- status = "okay"; +- }; +- +- debug_region@ffb00000 { +- reg = <0x00 0xffb00000 0x00 0x100000>; +- no-map; +- }; +- +- removed_region@85800000 { +- reg = <0x00 0x85800000 0x00 0x3700000>; +- no-map; +- }; +- }; +- +- /* +- * Until we hook up type-c detection, we +- * have to stick with this. But it works. +- */ +- extcon_usb: extcon-usb { +- compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&adsp_pil { +- firmware-name = "adsp.mdt"; +-}; +- +-&blsp_i2c1 { +- status = "okay"; +- +- touchscreen: synaptics-rmi4-i2c@70 { +- compatible = "syna,rmi4-i2c"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts-extended = <&tlmm 45 0x2008>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&ts_int_active &ts_lcd_id_active>; +- +- syna,reset-delay-ms = <200>; +- syna,startup-delay-ms = <220>; +- +- rmi4-f01@1 { +- reg = <0x01>; +- syna,nosleep-mode = <1>; +- }; +- +- rmi4-f11@11 { +- reg = <0x11>; +- syna,sensor-type = <1>; +- }; +- }; +-}; +- +-&blsp_i2c2 { +- status = "okay"; +- +- /* SMB1351 charger */ +-}; +- +-/* I2C3, 4, 5, 7 and 8 are disabled on this board. */ +- +-&blsp_i2c6 { +- status = "okay"; +- +- /* NXP NFC */ +-}; +- +-&blsp1_uart2 { +- status = "okay"; +- +- /* MSM serial console */ +-}; +- +-&blsp2_uart1 { +- status = "okay"; +- +- /* HCI Bluetooth */ +-}; +- +-&pon { +- volup { +- compatible = "qcom,pm8941-resin"; +- interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; +- debounce = <15625>; +- bias-pull-up; +- linux,code = ; +- }; +-}; +- +-&qusb2phy { +- status = "okay"; +- +- vdd-supply = <&vreg_l1b_0p925>; +- vdda-pll-supply = <&vreg_l10a_1p8>; +- vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; +-}; +- +-&rpm_requests { +- pm660l-regulators { +- compatible = "qcom,rpm-pm660l-regulators"; +- +- vdd_s1-supply = <&vph_pwr>; +- vdd_s2-supply = <&vph_pwr>; +- vdd_s3_s4-supply = <&vph_pwr>; +- vdd_s5-supply = <&vph_pwr>; +- vdd_s6-supply = <&vph_pwr>; +- +- vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>; +- vdd_l2-supply = <&vreg_bob>; +- vdd_l3_l5_l7_l8-supply = <&vreg_bob>; +- vdd_l4_l6-supply = <&vreg_bob>; +- vdd_bob-supply = <&vph_pwr>; +- +- vreg_s1b_1p125: s1 { +- regulator-min-microvolt = <1125000>; +- regulator-max-microvolt = <1125000>; +- regulator-enable-ramp-delay = <200>; +- regulator-ramp-delay = <0>; +- }; +- +- vreg_s2b_1p05: s2 { +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-enable-ramp-delay = <200>; +- regulator-ramp-delay = <0>; +- }; +- +- /* +- * At least on Nile's configuration, S3B/S4B (VDD_CX) and +- * S5B (VDD_MX) are managed only through RPM Power Domains. +- * Trying to set a voltage on the main supply will create +- * havoc and freeze the SoC. +- * In any case, reference voltages for these regulators are: +- * S3B/S4B: 0.870V +- * S5B: 0.915V +- */ +- +- /* LDOs */ +- vreg_l1b_0p925: l1 { +- regulator-min-microvolt = <920000>; +- regulator-max-microvolt = <928000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- regulator-allow-set-load; +- }; +- +- vreg_l2b_2p95: l2 { +- /* +- * This regulator supports 1.648 - 3.104V on this board +- * but we set a max voltage of anything less than 2.7V +- * to satisfy a condition in sdhci.c that will disable +- * 3.3V SDHCI signaling, which happens to be not really +- * supported on the Xperia Nile/Ganges platform. +- */ +- regulator-min-microvolt = <1648000>; +- regulator-max-microvolt = <2696000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- regulator-allow-set-load; +- }; +- +- vreg_l3b_3p0: l3 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- regulator-min-microamp = <200>; +- regulator-max-microamp = <600000>; +- regulator-system-load = <100000>; +- regulator-allow-set-load; +- }; +- +- vreg_l4b_29p5: l4 { +- regulator-min-microvolt = <2944000>; +- regulator-max-microvolt = <2952000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- +- regulator-min-microamp = <200>; +- regulator-max-microamp = <600000>; +- regulator-system-load = <570000>; +- regulator-allow-set-load; +- }; +- +- /* +- * Downstream specifies a range of 1721-3600mV, +- * but the only assigned consumers are SDHCI2 VMMC +- * and Coresight QPDI that both request pinned 2.95V. +- * Tighten the range to 1.8-3.328 (closest to 3.3) to +- * make the mmc driver happy. +- */ +- vreg_l5b_29p5: l5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3328000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- regulator-allow-set-load; +- regulator-system-load = <800000>; +- }; +- +- vreg_l6b_3p3: l6 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <3312000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- }; +- +- vreg_l7b_3p125: l7 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <3128000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- }; +- +- vreg_l8b_3p3: l8 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <3400000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- }; +- +- /* L9B (870mV) is currently unused */ +- /* L10B (915mV) is currently unused */ +- +- vreg_bob: bob { +- regulator-min-microvolt = <3304000>; +- regulator-max-microvolt = <3624000>; +- regulator-enable-ramp-delay = <500>; +- regulator-ramp-delay = <0>; +- }; +- }; +- +- pm660-regulators { +- compatible = "qcom,rpm-pm660-regulators"; +- +- vdd_s1-supply = <&vph_pwr>; +- vdd_s2-supply = <&vph_pwr>; +- vdd_s3-supply = <&vph_pwr>; +- vdd_s4-supply = <&vph_pwr>; +- vdd_s5-supply = <&vph_pwr>; +- vdd_s6-supply = <&vph_pwr>; +- +- vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>; +- vdd_l2_l3-supply = <&vreg_s2b_1p05>; +- vdd_l5-supply = <&vreg_s2b_1p05>; +- vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>; +- vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>; +- +- /* +- * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed +- * by the Core Power Reduction hardened (CPRh) and the +- * Operating State Manager (OSM) HW automatically. +- */ +- +- vreg_s4a_2p04: s4 { +- regulator-min-microvolt = <2040000>; +- regulator-max-microvolt = <2040000>; +- regulator-enable-ramp-delay = <200>; +- regulator-ramp-delay = <0>; +- regulator-always-on; +- }; +- +- vreg_s5a_1p35: s5 { +- regulator-min-microvolt = <1224000>; +- regulator-max-microvolt = <1350000>; +- regulator-enable-ramp-delay = <200>; +- regulator-ramp-delay = <0>; +- }; +- +- vreg_s6a_0p87: s6 { +- regulator-min-microvolt = <504000>; +- regulator-max-microvolt = <992000>; +- regulator-enable-ramp-delay = <150>; +- regulator-ramp-delay = <0>; +- }; +- +- /* LDOs */ +- vreg_l1a_1p225: l1 { +- regulator-min-microvolt = <1226000>; +- regulator-max-microvolt = <1250000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- regulator-allow-set-load; +- }; +- +- vreg_l2a_1p0: l2 { +- regulator-min-microvolt = <944000>; +- regulator-max-microvolt = <1008000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- }; +- +- vreg_l3a_1p0: l3 { +- regulator-min-microvolt = <944000>; +- regulator-max-microvolt = <1008000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- }; +- +- vreg_l5a_0p848: l5 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <952000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- }; +- +- vreg_l6a_1p3: l6 { +- regulator-min-microvolt = <1304000>; +- regulator-max-microvolt = <1368000>; +- regulator-allow-set-load; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- }; +- +- vreg_l7a_1p2: l7 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- }; +- +- vreg_l8a_1p8: l8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- regulator-system-load = <325000>; +- regulator-allow-set-load; +- }; +- +- vreg_l9a_1p8: l9 { +- regulator-min-microvolt = <1804000>; +- regulator-max-microvolt = <1896000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- regulator-allow-set-load; +- }; +- +- vreg_l10a_1p8: l10 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1944000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- regulator-allow-set-load; +- }; +- +- vreg_l11a_1p8: l11 { +- regulator-min-microvolt = <1784000>; +- regulator-max-microvolt = <1944000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- }; +- +- vreg_l12a_1p8: l12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1944000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- }; +- +- /* This gives power to the LPDDR4: never turn it off! */ +- vreg_l13a_1p8: l13 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1944000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vreg_l14a_1p8: l14 { +- regulator-min-microvolt = <1710000>; +- regulator-max-microvolt = <1904000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- }; +- +- vreg_l15a_1p8: l15 { +- regulator-min-microvolt = <1648000>; +- regulator-max-microvolt = <2952000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- }; +- +- /* L16A (2.70V) is unused */ +- +- vreg_l17a_1p8: l17 { +- regulator-min-microvolt = <1648000>; +- regulator-max-microvolt = <2952000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- }; +- +- vreg_l18a_1v8: l18 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <10>; +- regulator-min-microamp = <200>; +- regulator-max-microamp = <50000>; +- regulator-system-load = <10000>; +- regulator-allow-set-load; +- }; +- +- vreg_l19a_3p3: l19 { +- regulator-min-microvolt = <3312000>; +- regulator-max-microvolt = <3400000>; +- regulator-enable-ramp-delay = <250>; +- regulator-ramp-delay = <0>; +- regulator-allow-set-load; +- }; +- }; +-}; +- +-&sdhc_1 { +- status = "okay"; +- supports-cqe; +- +- /* SoMC Nile platform's eMMC doesn't support HS200 mode */ +- mmc-ddr-1_8v; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- +- vmmc-supply = <&vreg_l4b_29p5>; +- vqmmc-supply = <&vreg_l8a_1p8>; +-}; +- +-&sdhc_2 { +- status = "okay"; +- +- vmmc-supply = <&vreg_l5b_29p5>; +- vqmmc-supply = <&vreg_l2b_2p95>; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <8 4>; +- +- ts_int_active: ts-int-active { +- pins = "gpio45"; +- drive-strength = <8>; +- bias-pull-up; +- }; +- +- ts_lcd_id_active: ts-lcd-id-active { +- pins = "gpio56"; +- drive-strength = <8>; +- bias-disable; +- }; +- +- imx300_vana_default: imx300-vana-default { +- pins = "gpio50"; +- function = "gpio"; +- bias-disable; +- drive-strength = <2>; +- }; +- +- imx219_vana_default: imx219-vana-default { +- pins = "gpio51"; +- function = "gpio"; +- bias-disable; +- drive-strength = <2>; +- }; +- +- cam_vdig_default: cam-vdig-default { +- pins = "gpio52"; +- function = "gpio"; +- bias-disable; +- drive-strength = <2>; +- }; +-}; +- +-&usb3 { +- status = "okay"; +-}; +- +-&usb3_dwc3 { +- dr_mode = "peripheral"; +- extcon = <&extcon_usb>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm630.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sdm630.dtsi +deleted file mode 100644 +index a8724fd60645..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm630.dtsi ++++ /dev/null +@@ -1,2430 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Konrad Dybcio +- * Copyright (c) 2020, AngeloGioacchino Del Regno +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&intc>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- chosen { }; +- +- clocks { +- xo_board: xo-board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <19200000>; +- clock-output-names = "xo_board"; +- }; +- +- sleep_clk: sleep-clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32764>; +- clock-output-names = "sleep_clk"; +- }; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- CPU0: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- cpu-idle-states = <&PERF_CPU_SLEEP_0 +- &PERF_CPU_SLEEP_1 +- &PERF_CLUSTER_SLEEP_0 +- &PERF_CLUSTER_SLEEP_1 +- &PERF_CLUSTER_SLEEP_2>; +- capacity-dmips-mhz = <1126>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_1>; +- L2_1: l2-cache { +- compatible = "cache"; +- cache-level = <2>; +- }; +- }; +- +- CPU1: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x101>; +- enable-method = "psci"; +- cpu-idle-states = <&PERF_CPU_SLEEP_0 +- &PERF_CPU_SLEEP_1 +- &PERF_CLUSTER_SLEEP_0 +- &PERF_CLUSTER_SLEEP_1 +- &PERF_CLUSTER_SLEEP_2>; +- capacity-dmips-mhz = <1126>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_1>; +- }; +- +- CPU2: cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x102>; +- enable-method = "psci"; +- cpu-idle-states = <&PERF_CPU_SLEEP_0 +- &PERF_CPU_SLEEP_1 +- &PERF_CLUSTER_SLEEP_0 +- &PERF_CLUSTER_SLEEP_1 +- &PERF_CLUSTER_SLEEP_2>; +- capacity-dmips-mhz = <1126>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_1>; +- }; +- +- CPU3: cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x103>; +- enable-method = "psci"; +- cpu-idle-states = <&PERF_CPU_SLEEP_0 +- &PERF_CPU_SLEEP_1 +- &PERF_CLUSTER_SLEEP_0 +- &PERF_CLUSTER_SLEEP_1 +- &PERF_CLUSTER_SLEEP_2>; +- capacity-dmips-mhz = <1126>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_1>; +- }; +- +- CPU4: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- cpu-idle-states = <&PWR_CPU_SLEEP_0 +- &PWR_CPU_SLEEP_1 +- &PWR_CLUSTER_SLEEP_0 +- &PWR_CLUSTER_SLEEP_1 +- &PWR_CLUSTER_SLEEP_2>; +- capacity-dmips-mhz = <1024>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_0>; +- L2_0: l2-cache { +- compatible = "cache"; +- cache-level = <2>; +- }; +- }; +- +- CPU5: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- cpu-idle-states = <&PWR_CPU_SLEEP_0 +- &PWR_CPU_SLEEP_1 +- &PWR_CLUSTER_SLEEP_0 +- &PWR_CLUSTER_SLEEP_1 +- &PWR_CLUSTER_SLEEP_2>; +- capacity-dmips-mhz = <1024>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_0>; +- }; +- +- CPU6: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- cpu-idle-states = <&PWR_CPU_SLEEP_0 +- &PWR_CPU_SLEEP_1 +- &PWR_CLUSTER_SLEEP_0 +- &PWR_CLUSTER_SLEEP_1 +- &PWR_CLUSTER_SLEEP_2>; +- capacity-dmips-mhz = <1024>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_0>; +- }; +- +- CPU7: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- cpu-idle-states = <&PWR_CPU_SLEEP_0 +- &PWR_CPU_SLEEP_1 +- &PWR_CLUSTER_SLEEP_0 +- &PWR_CLUSTER_SLEEP_1 +- &PWR_CLUSTER_SLEEP_2>; +- capacity-dmips-mhz = <1024>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_0>; +- }; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&CPU4>; +- }; +- +- core1 { +- cpu = <&CPU5>; +- }; +- +- core2 { +- cpu = <&CPU6>; +- }; +- +- core3 { +- cpu = <&CPU7>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&CPU0>; +- }; +- +- core1 { +- cpu = <&CPU1>; +- }; +- +- core2 { +- cpu = <&CPU2>; +- }; +- +- core3 { +- cpu = <&CPU3>; +- }; +- }; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- PWR_CPU_SLEEP_0: cpu-sleep-0-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "pwr-retention"; +- arm,psci-suspend-param = <0x40000002>; +- entry-latency-us = <338>; +- exit-latency-us = <423>; +- min-residency-us = <200>; +- }; +- +- PWR_CPU_SLEEP_1: cpu-sleep-0-1 { +- compatible = "arm,idle-state"; +- idle-state-name = "pwr-power-collapse"; +- arm,psci-suspend-param = <0x40000003>; +- entry-latency-us = <515>; +- exit-latency-us = <1821>; +- min-residency-us = <1000>; +- local-timer-stop; +- }; +- +- PERF_CPU_SLEEP_0: cpu-sleep-1-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "perf-retention"; +- arm,psci-suspend-param = <0x40000002>; +- entry-latency-us = <154>; +- exit-latency-us = <87>; +- min-residency-us = <200>; +- }; +- +- PERF_CPU_SLEEP_1: cpu-sleep-1-1 { +- compatible = "arm,idle-state"; +- idle-state-name = "perf-power-collapse"; +- arm,psci-suspend-param = <0x40000003>; +- entry-latency-us = <262>; +- exit-latency-us = <301>; +- min-residency-us = <1000>; +- local-timer-stop; +- }; +- +- PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "pwr-cluster-dynamic-retention"; +- arm,psci-suspend-param = <0x400000F2>; +- entry-latency-us = <284>; +- exit-latency-us = <384>; +- min-residency-us = <9987>; +- local-timer-stop; +- }; +- +- PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { +- compatible = "arm,idle-state"; +- idle-state-name = "pwr-cluster-retention"; +- arm,psci-suspend-param = <0x400000F3>; +- entry-latency-us = <338>; +- exit-latency-us = <423>; +- min-residency-us = <9987>; +- local-timer-stop; +- }; +- +- PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { +- compatible = "arm,idle-state"; +- idle-state-name = "pwr-cluster-retention"; +- arm,psci-suspend-param = <0x400000F4>; +- entry-latency-us = <515>; +- exit-latency-us = <1821>; +- min-residency-us = <9987>; +- local-timer-stop; +- }; +- +- PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "perf-cluster-dynamic-retention"; +- arm,psci-suspend-param = <0x400000F2>; +- entry-latency-us = <272>; +- exit-latency-us = <329>; +- min-residency-us = <9987>; +- local-timer-stop; +- }; +- +- PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { +- compatible = "arm,idle-state"; +- idle-state-name = "perf-cluster-retention"; +- arm,psci-suspend-param = <0x400000F3>; +- entry-latency-us = <332>; +- exit-latency-us = <368>; +- min-residency-us = <9987>; +- local-timer-stop; +- }; +- +- PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { +- compatible = "arm,idle-state"; +- idle-state-name = "perf-cluster-retention"; +- arm,psci-suspend-param = <0x400000F4>; +- entry-latency-us = <545>; +- exit-latency-us = <1609>; +- min-residency-us = <9987>; +- local-timer-stop; +- }; +- }; +- }; +- +- firmware { +- scm { +- compatible = "qcom,scm-msm8998", "qcom,scm"; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- /* We expect the bootloader to fill in the reg */ +- reg = <0x0 0x80000000 0x0 0x0>; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- wlan_msa_guard: wlan-msa-guard@85600000 { +- reg = <0x0 0x85600000 0x0 0x100000>; +- no-map; +- }; +- +- wlan_msa_mem: wlan-msa-mem@85700000 { +- reg = <0x0 0x85700000 0x0 0x100000>; +- no-map; +- }; +- +- qhee_code: qhee-code@85800000 { +- reg = <0x0 0x85800000 0x0 0x600000>; +- no-map; +- }; +- +- rmtfs_mem: memory@85e00000 { +- compatible = "qcom,rmtfs-mem"; +- reg = <0x0 0x85e00000 0x0 0x200000>; +- no-map; +- +- qcom,client-id = <1>; +- qcom,vmid = <15>; +- }; +- +- smem_region: smem-mem@86000000 { +- reg = <0 0x86000000 0 0x200000>; +- no-map; +- }; +- +- tz_mem: memory@86200000 { +- reg = <0x0 0x86200000 0x0 0x3300000>; +- no-map; +- }; +- +- mpss_region: mpss@8ac00000 { +- reg = <0x0 0x8ac00000 0x0 0x7e00000>; +- no-map; +- }; +- +- adsp_region: adsp@92a00000 { +- reg = <0x0 0x92a00000 0x0 0x1e00000>; +- no-map; +- }; +- +- mba_region: mba@94800000 { +- reg = <0x0 0x94800000 0x0 0x200000>; +- no-map; +- }; +- +- buffer_mem: tzbuffer@94a00000 { +- reg = <0x0 0x94a00000 0x0 0x100000>; +- no-map; +- }; +- +- venus_region: venus@9f800000 { +- reg = <0x0 0x9f800000 0x0 0x800000>; +- no-map; +- }; +- +- adsp_mem: adsp-region@f6000000 { +- reg = <0x0 0xf6000000 0x0 0x800000>; +- no-map; +- }; +- +- qseecom_mem: qseecom-region@f6800000 { +- reg = <0x0 0xf6800000 0x0 0x1400000>; +- no-map; +- }; +- +- zap_shader_region: gpu@fed00000 { +- compatible = "shared-dma-pool"; +- reg = <0x0 0xfed00000 0x0 0xa00000>; +- no-map; +- }; +- }; +- +- rpm-glink { +- compatible = "qcom,glink-rpm"; +- +- interrupts = ; +- qcom,rpm-msg-ram = <&rpm_msg_ram>; +- mboxes = <&apcs_glb 0>; +- +- rpm_requests: rpm-requests { +- compatible = "qcom,rpm-sdm660"; +- qcom,glink-channels = "rpm_requests"; +- +- rpmcc: clock-controller { +- compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; +- #clock-cells = <1>; +- }; +- +- rpmpd: power-controller { +- compatible = "qcom,sdm660-rpmpd"; +- #power-domain-cells = <1>; +- operating-points-v2 = <&rpmpd_opp_table>; +- +- rpmpd_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- rpmpd_opp_ret: opp1 { +- opp-level = ; +- }; +- +- rpmpd_opp_ret_plus: opp2 { +- opp-level = ; +- }; +- +- rpmpd_opp_min_svs: opp3 { +- opp-level = ; +- }; +- +- rpmpd_opp_low_svs: opp4 { +- opp-level = ; +- }; +- +- rpmpd_opp_svs: opp5 { +- opp-level = ; +- }; +- +- rpmpd_opp_svs_plus: opp6 { +- opp-level = ; +- }; +- +- rpmpd_opp_nom: opp7 { +- opp-level = ; +- }; +- +- rpmpd_opp_nom_plus: opp8 { +- opp-level = ; +- }; +- +- rpmpd_opp_turbo: opp9 { +- opp-level = ; +- }; +- }; +- }; +- }; +- }; +- +- smem: smem { +- compatible = "qcom,smem"; +- memory-region = <&smem_region>; +- hwlocks = <&tcsr_mutex 3>; +- }; +- +- smp2p-adsp { +- compatible = "qcom,smp2p"; +- qcom,smem = <443>, <429>; +- interrupts = ; +- mboxes = <&apcs_glb 10>; +- qcom,local-pid = <0>; +- qcom,remote-pid = <2>; +- +- adsp_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- adsp_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-mpss { +- compatible = "qcom,smp2p"; +- qcom,smem = <435>, <428>; +- interrupts = ; +- mboxes = <&apcs_glb 14>; +- qcom,local-pid = <0>; +- qcom,remote-pid = <1>; +- +- modem_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- modem_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0 0xffffffff>; +- compatible = "simple-bus"; +- +- gcc: clock-controller@100000 { +- compatible = "qcom,gcc-sdm630"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- reg = <0x00100000 0x94000>; +- +- clock-names = "xo", "sleep_clk"; +- clocks = <&xo_board>, +- <&sleep_clk>; +- }; +- +- rpm_msg_ram: sram@778000 { +- compatible = "qcom,rpm-msg-ram"; +- reg = <0x00778000 0x7000>; +- }; +- +- qfprom: qfprom@780000 { +- compatible = "qcom,qfprom"; +- reg = <0x00780000 0x621c>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- qusb2_hstx_trim: hstx-trim@240 { +- reg = <0x240 0x1>; +- bits = <25 3>; +- }; +- +- gpu_speed_bin: gpu-speed-bin@41a0 { +- reg = <0x41a0 0x1>; +- bits = <21 7>; +- }; +- }; +- +- rng: rng@793000 { +- compatible = "qcom,prng-ee"; +- reg = <0x00793000 0x1000>; +- clocks = <&gcc GCC_PRNG_AHB_CLK>; +- clock-names = "core"; +- }; +- +- bimc: interconnect@1008000 { +- compatible = "qcom,sdm660-bimc"; +- reg = <0x01008000 0x78000>; +- #interconnect-cells = <1>; +- clock-names = "bus", "bus_a"; +- clocks = <&rpmcc RPM_SMD_BIMC_CLK>, +- <&rpmcc RPM_SMD_BIMC_A_CLK>; +- }; +- +- restart@10ac000 { +- compatible = "qcom,pshold"; +- reg = <0x010ac000 0x4>; +- }; +- +- cnoc: interconnect@1500000 { +- compatible = "qcom,sdm660-cnoc"; +- reg = <0x01500000 0x10000>; +- #interconnect-cells = <1>; +- clock-names = "bus", "bus_a"; +- clocks = <&rpmcc RPM_SMD_CNOC_CLK>, +- <&rpmcc RPM_SMD_CNOC_A_CLK>; +- }; +- +- snoc: interconnect@1626000 { +- compatible = "qcom,sdm660-snoc"; +- reg = <0x01626000 0x7090>; +- #interconnect-cells = <1>; +- clock-names = "bus", "bus_a"; +- clocks = <&rpmcc RPM_SMD_SNOC_CLK>, +- <&rpmcc RPM_SMD_SNOC_A_CLK>; +- }; +- +- anoc2_smmu: iommu@16c0000 { +- compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; +- reg = <0x016c0000 0x40000>; +- +- assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; +- assigned-clock-rates = <1000>; +- clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; +- clock-names = "bus"; +- #global-interrupts = <2>; +- #iommu-cells = <1>; +- +- interrupts = +- , +- , +- +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- +- status = "disabled"; +- }; +- +- a2noc: interconnect@1704000 { +- compatible = "qcom,sdm660-a2noc"; +- reg = <0x01704000 0xc100>; +- #interconnect-cells = <1>; +- clock-names = "bus", +- "bus_a", +- "ipa", +- "ufs_axi", +- "aggre2_ufs_axi", +- "aggre2_usb3_axi", +- "cfg_noc_usb2_axi"; +- clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, +- <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, +- <&rpmcc RPM_SMD_IPA_CLK>, +- <&gcc GCC_UFS_AXI_CLK>, +- <&gcc GCC_AGGRE2_UFS_AXI_CLK>, +- <&gcc GCC_AGGRE2_USB3_AXI_CLK>, +- <&gcc GCC_CFG_NOC_USB2_AXI_CLK>; +- }; +- +- mnoc: interconnect@1745000 { +- compatible = "qcom,sdm660-mnoc"; +- reg = <0x01745000 0xA010>; +- #interconnect-cells = <1>; +- clock-names = "bus", "bus_a", "iface"; +- clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, +- <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>, +- <&mmcc AHB_CLK_SRC>; +- }; +- +- tsens: thermal-sensor@10ae000 { +- compatible = "qcom,sdm630-tsens", "qcom,tsens-v2"; +- reg = <0x010ae000 0x1000>, /* TM */ +- <0x010ad000 0x1000>; /* SROT */ +- #qcom,sensors = <12>; +- interrupts = , +- ; +- interrupt-names = "uplow", "critical"; +- #thermal-sensor-cells = <1>; +- }; +- +- tcsr_mutex_regs: syscon@1f40000 { +- compatible = "syscon"; +- reg = <0x01f40000 0x40000>; +- }; +- +- tlmm: pinctrl@3100000 { +- compatible = "qcom,sdm630-pinctrl"; +- reg = <0x03100000 0x400000>, +- <0x03500000 0x400000>, +- <0x03900000 0x400000>; +- reg-names = "south", "center", "north"; +- interrupts = ; +- gpio-controller; +- gpio-ranges = <&tlmm 0 0 114>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- blsp1_uart1_default: blsp1-uart1-default { +- pins = "gpio0", "gpio1", "gpio2", "gpio3"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- blsp1_uart1_sleep: blsp1-uart1-sleep { +- pins = "gpio0", "gpio1", "gpio2", "gpio3"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- blsp1_uart2_default: blsp1-uart2-default { +- pins = "gpio4", "gpio5"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- blsp2_uart1_default: blsp2-uart1-active { +- tx-rts { +- pins = "gpio16", "gpio19"; +- function = "blsp_uart5"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- rx { +- /* +- * Avoid garbage data while BT module +- * is powered off or not driving signal +- */ +- pins = "gpio17"; +- function = "blsp_uart5"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- cts { +- /* Match the pull of the BT module */ +- pins = "gpio18"; +- function = "blsp_uart5"; +- drive-strength = <2>; +- bias-pull-down; +- }; +- }; +- +- blsp2_uart1_sleep: blsp2-uart1-sleep { +- tx { +- pins = "gpio16"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- rx-cts-rts { +- pins = "gpio17", "gpio18", "gpio19"; +- function = "gpio"; +- drive-strength = <2>; +- bias-no-pull; +- }; +- }; +- +- i2c1_default: i2c1-default { +- pins = "gpio2", "gpio3"; +- function = "blsp_i2c1"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c1_sleep: i2c1-sleep { +- pins = "gpio2", "gpio3"; +- function = "blsp_i2c1"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- i2c2_default: i2c2-default { +- pins = "gpio6", "gpio7"; +- function = "blsp_i2c2"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c2_sleep: i2c2-sleep { +- pins = "gpio6", "gpio7"; +- function = "blsp_i2c2"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- i2c3_default: i2c3-default { +- pins = "gpio10", "gpio11"; +- function = "blsp_i2c3"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c3_sleep: i2c3-sleep { +- pins = "gpio10", "gpio11"; +- function = "blsp_i2c3"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- i2c4_default: i2c4-default { +- pins = "gpio14", "gpio15"; +- function = "blsp_i2c4"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c4_sleep: i2c4-sleep { +- pins = "gpio14", "gpio15"; +- function = "blsp_i2c4"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- i2c5_default: i2c5-default { +- pins = "gpio18", "gpio19"; +- function = "blsp_i2c5"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c5_sleep: i2c5-sleep { +- pins = "gpio18", "gpio19"; +- function = "blsp_i2c5"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- i2c6_default: i2c6-default { +- pins = "gpio22", "gpio23"; +- function = "blsp_i2c6"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c6_sleep: i2c6-sleep { +- pins = "gpio22", "gpio23"; +- function = "blsp_i2c6"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- i2c7_default: i2c7-default { +- pins = "gpio26", "gpio27"; +- function = "blsp_i2c7"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c7_sleep: i2c7-sleep { +- pins = "gpio26", "gpio27"; +- function = "blsp_i2c7"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- i2c8_default: i2c8-default { +- pins = "gpio30", "gpio31"; +- function = "blsp_i2c8"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c8_sleep: i2c8-sleep { +- pins = "gpio30", "gpio31"; +- function = "blsp_i2c8"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- cci0_default: cci0_default { +- pinmux { +- pins = "gpio36","gpio37"; +- function = "cci_i2c"; +- }; +- +- pinconf { +- pins = "gpio36","gpio37"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +- +- cci1_default: cci1_default { +- pinmux { +- pins = "gpio38","gpio39"; +- function = "cci_i2c"; +- }; +- +- pinconf { +- pins = "gpio38","gpio39"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +- +- sdc1_state_on: sdc1-on { +- clk { +- pins = "sdc1_clk"; +- bias-disable; +- drive-strength = <16>; +- }; +- +- cmd { +- pins = "sdc1_cmd"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- data { +- pins = "sdc1_data"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- rclk { +- pins = "sdc1_rclk"; +- bias-pull-down; +- }; +- }; +- +- sdc1_state_off: sdc1-off { +- clk { +- pins = "sdc1_clk"; +- bias-disable; +- drive-strength = <2>; +- }; +- +- cmd { +- pins = "sdc1_cmd"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- data { +- pins = "sdc1_data"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- rclk { +- pins = "sdc1_rclk"; +- bias-pull-down; +- }; +- }; +- +- sdc2_state_on: sdc2-on { +- clk { +- pins = "sdc2_clk"; +- bias-disable; +- drive-strength = <16>; +- }; +- +- cmd { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- data { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- sd-cd { +- pins = "gpio54"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +- +- sdc2_state_off: sdc2-off { +- clk { +- pins = "sdc2_clk"; +- bias-disable; +- drive-strength = <2>; +- }; +- +- cmd { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- data { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- sd-cd { +- pins = "gpio54"; +- bias-disable; +- drive-strength = <2>; +- }; +- }; +- }; +- +- adreno_gpu: gpu@5000000 { +- compatible = "qcom,adreno-508.0", "qcom,adreno"; +- #stream-id-cells = <16>; +- +- reg = <0x05000000 0x40000>; +- reg-names = "kgsl_3d0_reg_memory"; +- +- interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; +- +- clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, +- <&gpucc GPUCC_RBBMTIMER_CLK>, +- <&gcc GCC_BIMC_GFX_CLK>, +- <&gcc GCC_GPU_BIMC_GFX_CLK>, +- <&gpucc GPUCC_RBCPR_CLK>, +- <&gpucc GPUCC_GFX3D_CLK>; +- +- clock-names = "iface", +- "rbbmtimer", +- "mem", +- "mem_iface", +- "rbcpr", +- "core"; +- +- power-domains = <&rpmpd SDM660_VDDMX>; +- iommus = <&kgsl_smmu 0>; +- +- nvmem-cells = <&gpu_speed_bin>; +- nvmem-cell-names = "speed_bin"; +- +- interconnects = <&gnoc 1 &bimc 5>; +- interconnect-names = "gfx-mem"; +- +- operating-points-v2 = <&gpu_sdm630_opp_table>; +- +- gpu_sdm630_opp_table: opp-table { +- compatible = "operating-points-v2"; +- opp-775000000 { +- opp-hz = /bits/ 64 <775000000>; +- opp-level = ; +- opp-peak-kBps = <5412000>; +- opp-supported-hw = <0xA2>; +- }; +- opp-647000000 { +- opp-hz = /bits/ 64 <647000000>; +- opp-level = ; +- opp-peak-kBps = <4068000>; +- opp-supported-hw = <0xFF>; +- }; +- opp-588000000 { +- opp-hz = /bits/ 64 <588000000>; +- opp-level = ; +- opp-peak-kBps = <3072000>; +- opp-supported-hw = <0xFF>; +- }; +- opp-465000000 { +- opp-hz = /bits/ 64 <465000000>; +- opp-level = ; +- opp-peak-kBps = <2724000>; +- opp-supported-hw = <0xFF>; +- }; +- opp-370000000 { +- opp-hz = /bits/ 64 <370000000>; +- opp-level = ; +- opp-peak-kBps = <2188000>; +- opp-supported-hw = <0xFF>; +- }; +- opp-240000000 { +- opp-hz = /bits/ 64 <240000000>; +- opp-level = ; +- opp-peak-kBps = <1648000>; +- opp-supported-hw = <0xFF>; +- }; +- opp-160000000 { +- opp-hz = /bits/ 64 <160000000>; +- opp-level = ; +- opp-peak-kBps = <1200000>; +- opp-supported-hw = <0xFF>; +- }; +- }; +- }; +- +- kgsl_smmu: iommu@5040000 { +- compatible = "qcom,sdm630-smmu-v2", +- "qcom,adreno-smmu", "qcom,smmu-v2"; +- reg = <0x05040000 0x10000>; +- +- /* +- * GX GDSC parent is CX. We need to bring up CX for SMMU +- * but we need both up for Adreno. On the other hand, we +- * need to manage the GX rpmpd domain in the adreno driver. +- * Enable CX/GX GDSCs here so that we can manage just the GX +- * RPM Power Domain in the Adreno driver. +- */ +- power-domains = <&gpucc GPU_GX_GDSC>; +- clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, +- <&gcc GCC_BIMC_GFX_CLK>, +- <&gcc GCC_GPU_BIMC_GFX_CLK>; +- clock-names = "iface", "mem", "mem_iface"; +- #global-interrupts = <2>; +- #iommu-cells = <1>; +- +- interrupts = +- , +- , +- +- , +- , +- , +- , +- , +- , +- , +- ; +- +- status = "disabled"; +- }; +- +- gpucc: clock-controller@5065000 { +- compatible = "qcom,gpucc-sdm630"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- reg = <0x05065000 0x9038>; +- +- clocks = <&xo_board>, +- <&gcc GCC_GPU_GPLL0_CLK>, +- <&gcc GCC_GPU_GPLL0_DIV_CLK>; +- clock-names = "xo", +- "gcc_gpu_gpll0_clk", +- "gcc_gpu_gpll0_div_clk"; +- status = "disabled"; +- }; +- +- lpass_smmu: iommu@5100000 { +- compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; +- reg = <0x05100000 0x40000>; +- #iommu-cells = <1>; +- +- #global-interrupts = <2>; +- interrupts = +- , +- , +- +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- +- status = "disabled"; +- }; +- +- spmi_bus: spmi@800f000 { +- compatible = "qcom,spmi-pmic-arb"; +- reg = <0x0800f000 0x1000>, +- <0x08400000 0x1000000>, +- <0x09400000 0x1000000>, +- <0x0a400000 0x220000>, +- <0x0800a000 0x3000>; +- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; +- interrupt-names = "periph_irq"; +- interrupts = ; +- qcom,ee = <0>; +- qcom,channel = <0>; +- #address-cells = <2>; +- #size-cells = <0>; +- interrupt-controller; +- #interrupt-cells = <4>; +- cell-index = <0>; +- }; +- +- usb3: usb@a8f8800 { +- compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; +- reg = <0x0a8f8800 0x400>; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, +- <&gcc GCC_USB30_MASTER_CLK>, +- <&gcc GCC_AGGRE2_USB3_AXI_CLK>, +- <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, +- <&gcc GCC_USB30_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_SLEEP_CLK>; +- clock-names = "cfg_noc", "core", "iface", "bus", +- "mock_utmi", "sleep"; +- +- assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_MASTER_CLK>, +- <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; +- assigned-clock-rates = <19200000>, <120000000>, +- <19200000>; +- +- interrupts = , +- ; +- interrupt-names = "hs_phy_irq", "ss_phy_irq"; +- +- power-domains = <&gcc USB_30_GDSC>; +- qcom,select-utmi-as-pipe-clk; +- +- resets = <&gcc GCC_USB_30_BCR>; +- +- usb3_dwc3: usb@a800000 { +- compatible = "snps,dwc3"; +- reg = <0x0a800000 0xc8d0>; +- interrupts = ; +- snps,dis_u2_susphy_quirk; +- snps,dis_enblslpm_quirk; +- +- /* +- * SDM630 technically supports USB3 but I +- * haven't seen any devices making use of it. +- */ +- maximum-speed = "high-speed"; +- phys = <&qusb2phy>; +- phy-names = "usb2-phy"; +- snps,hird-threshold = /bits/ 8 <0>; +- }; +- }; +- +- qusb2phy: phy@c012000 { +- compatible = "qcom,sdm660-qusb2-phy"; +- reg = <0x0c012000 0x180>; +- #phy-cells = <0>; +- +- clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, +- <&gcc GCC_RX1_USB2_CLKREF_CLK>; +- clock-names = "cfg_ahb", "ref"; +- +- resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; +- nvmem-cells = <&qusb2_hstx_trim>; +- status = "disabled"; +- }; +- +- sdhc_2: sdhci@c084000 { +- compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; +- reg = <0x0c084000 0x1000>; +- reg-names = "hc"; +- +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- +- bus-width = <4>; +- clocks = <&gcc GCC_SDCC2_APPS_CLK>, +- <&gcc GCC_SDCC2_AHB_CLK>, +- <&xo_board>; +- clock-names = "core", "iface", "xo"; +- +- interconnects = <&a2noc 3 &a2noc 10>, +- <&gnoc 0 &cnoc 28>; +- operating-points-v2 = <&sdhc2_opp_table>; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc2_state_on>; +- pinctrl-1 = <&sdc2_state_off>; +- power-domains = <&rpmpd SDM660_VDDCX>; +- +- status = "disabled"; +- +- sdhc2_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-50000000 { +- opp-hz = /bits/ 64 <50000000>; +- required-opps = <&rpmpd_opp_low_svs>; +- opp-peak-kBps = <200000 140000>; +- opp-avg-kBps = <130718 133320>; +- }; +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- required-opps = <&rpmpd_opp_svs>; +- opp-peak-kBps = <250000 160000>; +- opp-avg-kBps = <196078 150000>; +- }; +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- required-opps = <&rpmpd_opp_nom>; +- opp-peak-kBps = <4096000 4096000>; +- opp-avg-kBps = <1338562 1338562>; +- }; +- }; +- }; +- +- sdhc_1: sdhci@c0c4000 { +- compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; +- reg = <0x0c0c4000 0x1000>, +- <0x0c0c5000 0x1000>, +- <0x0c0c8000 0x8000>; +- reg-names = "hc", "cqhci", "ice"; +- +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- +- clocks = <&gcc GCC_SDCC1_APPS_CLK>, +- <&gcc GCC_SDCC1_AHB_CLK>, +- <&xo_board>, +- <&gcc GCC_SDCC1_ICE_CORE_CLK>; +- clock-names = "core", "iface", "xo", "ice"; +- +- interconnects = <&a2noc 2 &a2noc 10>, +- <&gnoc 0 &cnoc 27>; +- interconnect-names = "sdhc1-ddr", "cpu-sdhc1"; +- operating-points-v2 = <&sdhc1_opp_table>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc1_state_on>; +- pinctrl-1 = <&sdc1_state_off>; +- power-domains = <&rpmpd SDM660_VDDCX>; +- +- bus-width = <8>; +- non-removable; +- +- status = "disabled"; +- +- sdhc1_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-50000000 { +- opp-hz = /bits/ 64 <50000000>; +- required-opps = <&rpmpd_opp_low_svs>; +- opp-peak-kBps = <200000 140000>; +- opp-avg-kBps = <130718 133320>; +- }; +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- required-opps = <&rpmpd_opp_svs>; +- opp-peak-kBps = <250000 160000>; +- opp-avg-kBps = <196078 150000>; +- }; +- opp-384000000 { +- opp-hz = /bits/ 64 <384000000>; +- required-opps = <&rpmpd_opp_nom>; +- opp-peak-kBps = <4096000 4096000>; +- opp-avg-kBps = <1338562 1338562>; +- }; +- }; +- }; +- +- mmcc: clock-controller@c8c0000 { +- compatible = "qcom,mmcc-sdm630"; +- reg = <0x0c8c0000 0x40000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- clock-names = "xo", +- "sleep_clk", +- "gpll0", +- "gpll0_div", +- "dsi0pll", +- "dsi0pllbyte", +- "dsi1pll", +- "dsi1pllbyte", +- "dp_link_2x_clk_divsel_five", +- "dp_vco_divided_clk_src_mux"; +- clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, +- <&sleep_clk>, +- <&gcc GCC_MMSS_GPLL0_CLK>, +- <&gcc GCC_MMSS_GPLL0_DIV_CLK>, +- <&dsi0_phy 1>, +- <&dsi0_phy 0>, +- <0>, +- <0>, +- <0>, +- <0>; +- }; +- +- dsi_opp_table: dsi-opp-table { +- compatible = "operating-points-v2"; +- +- opp-131250000 { +- opp-hz = /bits/ 64 <131250000>; +- required-opps = <&rpmpd_opp_svs>; +- }; +- +- opp-210000000 { +- opp-hz = /bits/ 64 <210000000>; +- required-opps = <&rpmpd_opp_svs_plus>; +- }; +- +- opp-262500000 { +- opp-hz = /bits/ 64 <262500000>; +- required-opps = <&rpmpd_opp_nom>; +- }; +- }; +- +- mdss: mdss@c900000 { +- compatible = "qcom,mdss"; +- reg = <0x0c900000 0x1000>, +- <0x0c9b0000 0x1040>; +- reg-names = "mdss_phys", "vbif_phys"; +- +- power-domains = <&mmcc MDSS_GDSC>; +- +- clocks = <&mmcc MDSS_AHB_CLK>, +- <&mmcc MDSS_AXI_CLK>, +- <&mmcc MDSS_VSYNC_CLK>, +- <&mmcc MDSS_MDP_CLK>; +- clock-names = "iface", +- "bus", +- "vsync", +- "core"; +- +- interrupts = ; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- status = "disabled"; +- +- mdp: mdp@c901000 { +- compatible = "qcom,mdp5"; +- reg = <0x0c901000 0x89000>; +- reg-names = "mdp_phys"; +- +- interrupt-parent = <&mdss>; +- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; +- +- assigned-clocks = <&mmcc MDSS_MDP_CLK>, +- <&mmcc MDSS_VSYNC_CLK>; +- assigned-clock-rates = <300000000>, +- <19200000>; +- clocks = <&mmcc MDSS_AHB_CLK>, +- <&mmcc MDSS_AXI_CLK>, +- <&mmcc MDSS_MDP_CLK>, +- <&mmcc MDSS_VSYNC_CLK>; +- clock-names = "iface", +- "bus", +- "core", +- "vsync"; +- +- interconnects = <&mnoc 2 &bimc 5>, +- <&mnoc 3 &bimc 5>, +- <&gnoc 0 &mnoc 17>; +- interconnect-names = "mdp0-mem", +- "mdp1-mem", +- "rotator-mem"; +- iommus = <&mmss_smmu 0>; +- operating-points-v2 = <&mdp_opp_table>; +- power-domains = <&rpmpd SDM660_VDDCX>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- mdp5_intf1_out: endpoint { +- remote-endpoint = <&dsi0_in>; +- }; +- }; +- }; +- +- mdp_opp_table: mdp-opp { +- compatible = "operating-points-v2"; +- +- opp-150000000 { +- opp-hz = /bits/ 64 <150000000>; +- opp-peak-kBps = <320000 320000 76800>; +- required-opps = <&rpmpd_opp_low_svs>; +- }; +- opp-275000000 { +- opp-hz = /bits/ 64 <275000000>; +- opp-peak-kBps = <6400000 6400000 160000>; +- required-opps = <&rpmpd_opp_svs>; +- }; +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-peak-kBps = <6400000 6400000 190000>; +- required-opps = <&rpmpd_opp_svs_plus>; +- }; +- opp-330000000 { +- opp-hz = /bits/ 64 <330000000>; +- opp-peak-kBps = <6400000 6400000 240000>; +- required-opps = <&rpmpd_opp_nom>; +- }; +- opp-412500000 { +- opp-hz = /bits/ 64 <412500000>; +- opp-peak-kBps = <6400000 6400000 320000>; +- required-opps = <&rpmpd_opp_turbo>; +- }; +- }; +- }; +- +- dsi0: dsi@c994000 { +- compatible = "qcom,mdss-dsi-ctrl"; +- reg = <0x0c994000 0x400>; +- reg-names = "dsi_ctrl"; +- +- operating-points-v2 = <&dsi_opp_table>; +- power-domains = <&rpmpd SDM660_VDDCX>; +- +- interrupt-parent = <&mdss>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +- +- assigned-clocks = <&mmcc BYTE0_CLK_SRC>, +- <&mmcc PCLK0_CLK_SRC>; +- assigned-clock-parents = <&dsi0_phy 0>, +- <&dsi0_phy 1>; +- +- clocks = <&mmcc MDSS_MDP_CLK>, +- <&mmcc MDSS_BYTE0_CLK>, +- <&mmcc MDSS_BYTE0_INTF_CLK>, +- <&mmcc MNOC_AHB_CLK>, +- <&mmcc MDSS_AHB_CLK>, +- <&mmcc MDSS_AXI_CLK>, +- <&mmcc MISC_AHB_CLK>, +- <&mmcc MDSS_PCLK0_CLK>, +- <&mmcc MDSS_ESC0_CLK>; +- clock-names = "mdp_core", +- "byte", +- "byte_intf", +- "mnoc", +- "iface", +- "bus", +- "core_mmss", +- "pixel", +- "core"; +- +- phys = <&dsi0_phy>; +- phy-names = "dsi"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dsi0_in: endpoint { +- remote-endpoint = <&mdp5_intf1_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- dsi0_out: endpoint { +- }; +- }; +- }; +- }; +- +- dsi0_phy: dsi-phy@c994400 { +- compatible = "qcom,dsi-phy-14nm-660"; +- reg = <0x0c994400 0x100>, +- <0x0c994500 0x300>, +- <0x0c994800 0x188>; +- reg-names = "dsi_phy", +- "dsi_phy_lane", +- "dsi_pll"; +- +- #clock-cells = <1>; +- #phy-cells = <0>; +- +- clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; +- clock-names = "iface", "ref"; +- }; +- }; +- +- blsp1_dma: dma-controller@c144000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0x0c144000 0x1f000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- qcom,controlled-remotely; +- num-channels = <18>; +- qcom,num-ees = <4>; +- }; +- +- blsp1_uart1: serial@c16f000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x0c16f000 0x200>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp1_uart1_default>; +- pinctrl-1 = <&blsp1_uart1_sleep>; +- status = "disabled"; +- }; +- +- blsp1_uart2: serial@c170000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x0c170000 0x1000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blsp1_uart2_default>; +- status = "disabled"; +- }; +- +- blsp_i2c1: i2c@c175000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c175000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- clock-frequency = <400000>; +- dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; +- dma-names = "tx", "rx"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c1_default>; +- pinctrl-1 = <&i2c1_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp_i2c2: i2c@c176000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c176000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- clock-frequency = <400000>; +- dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; +- dma-names = "tx", "rx"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c2_default>; +- pinctrl-1 = <&i2c2_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp_i2c3: i2c@c177000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c177000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- clock-frequency = <400000>; +- dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; +- dma-names = "tx", "rx"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c3_default>; +- pinctrl-1 = <&i2c3_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp_i2c4: i2c@c178000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c178000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- clock-frequency = <400000>; +- dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; +- dma-names = "tx", "rx"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c4_default>; +- pinctrl-1 = <&i2c4_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp2_dma: dma-controller@c184000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0x0c184000 0x1f000>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- qcom,controlled-remotely; +- num-channels = <18>; +- qcom,num-ees = <4>; +- }; +- +- blsp2_uart1: serial@c1af000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x0c1af000 0x200>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, +- <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&blsp2_uart1_default>; +- pinctrl-1 = <&blsp2_uart1_sleep>; +- status = "disabled"; +- }; +- +- blsp_i2c5: i2c@c1b5000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c1b5000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, +- <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- clock-frequency = <400000>; +- dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; +- dma-names = "tx", "rx"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c5_default>; +- pinctrl-1 = <&i2c5_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp_i2c6: i2c@c1b6000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c1b6000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, +- <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- clock-frequency = <400000>; +- dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; +- dma-names = "tx", "rx"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c6_default>; +- pinctrl-1 = <&i2c6_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp_i2c7: i2c@c1b7000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c1b7000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, +- <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- clock-frequency = <400000>; +- dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; +- dma-names = "tx", "rx"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c7_default>; +- pinctrl-1 = <&i2c7_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- blsp_i2c8: i2c@c1b8000 { +- compatible = "qcom,i2c-qup-v2.2.1"; +- reg = <0x0c1b8000 0x600>; +- interrupts = ; +- +- clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, +- <&gcc GCC_BLSP2_AHB_CLK>; +- clock-names = "core", "iface"; +- clock-frequency = <400000>; +- dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; +- dma-names = "tx", "rx"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c8_default>; +- pinctrl-1 = <&i2c8_sleep>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- imem@146bf000 { +- compatible = "simple-mfd"; +- reg = <0x146bf000 0x1000>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0 0x146bf000 0x1000>; +- +- pil-reloc@94c { +- compatible = "qcom,pil-reloc-info"; +- reg = <0x94c 0xc8>; +- }; +- }; +- +- camss: camss@ca00000 { +- compatible = "qcom,sdm660-camss"; +- reg = <0x0c824000 0x1000>, +- <0x0ca00120 0x4>, +- <0x0c825000 0x1000>, +- <0x0ca00124 0x4>, +- <0x0c826000 0x1000>, +- <0x0ca00128 0x4>, +- <0x0ca30000 0x100>, +- <0x0ca30400 0x100>, +- <0x0ca30800 0x100>, +- <0x0ca30c00 0x100>, +- <0x0ca31000 0x500>, +- <0x0ca00020 0x10>, +- <0x0ca10000 0x1000>, +- <0x0ca14000 0x1000>; +- reg-names = "csiphy0", +- "csiphy0_clk_mux", +- "csiphy1", +- "csiphy1_clk_mux", +- "csiphy2", +- "csiphy2_clk_mux", +- "csid0", +- "csid1", +- "csid2", +- "csid3", +- "ispif", +- "csi_clk_mux", +- "vfe0", +- "vfe1"; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "csiphy0", +- "csiphy1", +- "csiphy2", +- "csid0", +- "csid1", +- "csid2", +- "csid3", +- "ispif", +- "vfe0", +- "vfe1"; +- clocks = <&mmcc CAMSS_TOP_AHB_CLK>, +- <&mmcc THROTTLE_CAMSS_AXI_CLK>, +- <&mmcc CAMSS_ISPIF_AHB_CLK>, +- <&mmcc CAMSS_CSI0PHYTIMER_CLK>, +- <&mmcc CAMSS_CSI1PHYTIMER_CLK>, +- <&mmcc CAMSS_CSI2PHYTIMER_CLK>, +- <&mmcc CAMSS_CSI0_AHB_CLK>, +- <&mmcc CAMSS_CSI0_CLK>, +- <&mmcc CAMSS_CPHY_CSID0_CLK>, +- <&mmcc CAMSS_CSI0PIX_CLK>, +- <&mmcc CAMSS_CSI0RDI_CLK>, +- <&mmcc CAMSS_CSI1_AHB_CLK>, +- <&mmcc CAMSS_CSI1_CLK>, +- <&mmcc CAMSS_CPHY_CSID1_CLK>, +- <&mmcc CAMSS_CSI1PIX_CLK>, +- <&mmcc CAMSS_CSI1RDI_CLK>, +- <&mmcc CAMSS_CSI2_AHB_CLK>, +- <&mmcc CAMSS_CSI2_CLK>, +- <&mmcc CAMSS_CPHY_CSID2_CLK>, +- <&mmcc CAMSS_CSI2PIX_CLK>, +- <&mmcc CAMSS_CSI2RDI_CLK>, +- <&mmcc CAMSS_CSI3_AHB_CLK>, +- <&mmcc CAMSS_CSI3_CLK>, +- <&mmcc CAMSS_CPHY_CSID3_CLK>, +- <&mmcc CAMSS_CSI3PIX_CLK>, +- <&mmcc CAMSS_CSI3RDI_CLK>, +- <&mmcc CAMSS_AHB_CLK>, +- <&mmcc CAMSS_VFE0_CLK>, +- <&mmcc CAMSS_CSI_VFE0_CLK>, +- <&mmcc CAMSS_VFE0_AHB_CLK>, +- <&mmcc CAMSS_VFE0_STREAM_CLK>, +- <&mmcc CAMSS_VFE1_CLK>, +- <&mmcc CAMSS_CSI_VFE1_CLK>, +- <&mmcc CAMSS_VFE1_AHB_CLK>, +- <&mmcc CAMSS_VFE1_STREAM_CLK>, +- <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, +- <&mmcc CAMSS_VFE_VBIF_AXI_CLK>, +- <&mmcc CSIPHY_AHB2CRIF_CLK>, +- <&mmcc CAMSS_CPHY_CSID0_CLK>, +- <&mmcc CAMSS_CPHY_CSID1_CLK>, +- <&mmcc CAMSS_CPHY_CSID2_CLK>, +- <&mmcc CAMSS_CPHY_CSID3_CLK>; +- clock-names = "top_ahb", +- "throttle_axi", +- "ispif_ahb", +- "csiphy0_timer", +- "csiphy1_timer", +- "csiphy2_timer", +- "csi0_ahb", +- "csi0", +- "csi0_phy", +- "csi0_pix", +- "csi0_rdi", +- "csi1_ahb", +- "csi1", +- "csi1_phy", +- "csi1_pix", +- "csi1_rdi", +- "csi2_ahb", +- "csi2", +- "csi2_phy", +- "csi2_pix", +- "csi2_rdi", +- "csi3_ahb", +- "csi3", +- "csi3_phy", +- "csi3_pix", +- "csi3_rdi", +- "ahb", +- "vfe0", +- "csi_vfe0", +- "vfe0_ahb", +- "vfe0_stream", +- "vfe1", +- "csi_vfe1", +- "vfe1_ahb", +- "vfe1_stream", +- "vfe_ahb", +- "vfe_axi", +- "csiphy_ahb2crif", +- "cphy_csid0", +- "cphy_csid1", +- "cphy_csid2", +- "cphy_csid3"; +- interconnects = <&mnoc 5 &bimc 5>; +- interconnect-names = "vfe-mem"; +- iommus = <&mmss_smmu 0xc00>, +- <&mmss_smmu 0xc01>, +- <&mmss_smmu 0xc02>, +- <&mmss_smmu 0xc03>; +- power-domains = <&mmcc CAMSS_VFE0_GDSC>, +- <&mmcc CAMSS_VFE1_GDSC>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- cci: cci@ca0c000 { +- compatible = "qcom,msm8996-cci"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0ca0c000 0x1000>; +- interrupts = ; +- +- assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, +- <&mmcc CAMSS_CCI_CLK>; +- assigned-clock-rates = <80800000>, <37500000>; +- clocks = <&mmcc CAMSS_TOP_AHB_CLK>, +- <&mmcc CAMSS_CCI_AHB_CLK>, +- <&mmcc CAMSS_CCI_CLK>, +- <&mmcc CAMSS_AHB_CLK>; +- clock-names = "camss_top_ahb", +- "cci_ahb", +- "cci", +- "camss_ahb"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&cci0_default &cci1_default>; +- power-domains = <&mmcc CAMSS_TOP_GDSC>; +- status = "disabled"; +- +- cci_i2c0: i2c-bus@0 { +- reg = <0>; +- clock-frequency = <400000>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- cci_i2c1: i2c-bus@1 { +- reg = <1>; +- clock-frequency = <400000>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- mmss_smmu: iommu@cd00000 { +- compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; +- reg = <0x0cd00000 0x40000>; +- +- clocks = <&mmcc MNOC_AHB_CLK>, +- <&mmcc BIMC_SMMU_AHB_CLK>, +- <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, +- <&mmcc BIMC_SMMU_AXI_CLK>; +- clock-names = "iface-mm", "iface-smmu", +- "bus-mm", "bus-smmu"; +- #global-interrupts = <2>; +- #iommu-cells = <1>; +- +- interrupts = +- , +- , +- +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- +- status = "disabled"; +- }; +- +- adsp_pil: remoteproc@15700000 { +- compatible = "qcom,sdm660-adsp-pas"; +- reg = <0x15700000 0x4040>; +- +- interrupts-extended = +- <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack"; +- +- clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; +- clock-names = "xo"; +- +- memory-region = <&adsp_region>; +- power-domains = <&rpmpd SDM660_VDDCX>; +- power-domain-names = "cx"; +- +- qcom,smem-states = <&adsp_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- glink-edge { +- interrupts = ; +- +- label = "lpass"; +- mboxes = <&apcs_glb 9>; +- qcom,remote-pid = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- apr { +- compatible = "qcom,apr-v2"; +- qcom,glink-channels = "apr_audio_svc"; +- qcom,apr-domain = ; +- #address-cells = <1>; +- #size-cells = <0>; +- +- q6core { +- reg = ; +- compatible = "qcom,q6core"; +- }; +- +- q6afe: apr-service@4 { +- compatible = "qcom,q6afe"; +- reg = ; +- q6afedai: dais { +- compatible = "qcom,q6afe-dais"; +- #address-cells = <1>; +- #size-cells = <0>; +- #sound-dai-cells = <1>; +- }; +- }; +- +- q6asm: apr-service@7 { +- compatible = "qcom,q6asm"; +- reg = ; +- q6asmdai: dais { +- compatible = "qcom,q6asm-dais"; +- #address-cells = <1>; +- #size-cells = <0>; +- #sound-dai-cells = <1>; +- iommus = <&lpass_smmu 1>; +- }; +- }; +- +- q6adm: apr-service@8 { +- compatible = "qcom,q6adm"; +- reg = ; +- q6routing: routing { +- compatible = "qcom,q6adm-routing"; +- #sound-dai-cells = <0>; +- }; +- }; +- }; +- }; +- }; +- +- gnoc: interconnect@17900000 { +- compatible = "qcom,sdm660-gnoc"; +- reg = <0x17900000 0xe000>; +- #interconnect-cells = <1>; +- /* +- * This one apparently features no clocks, +- * so let's not mess with the driver needlessly +- */ +- clock-names = "bus", "bus_a"; +- clocks = <&xo_board>, <&xo_board>; +- }; +- +- apcs_glb: mailbox@17911000 { +- compatible = "qcom,sdm660-apcs-hmss-global"; +- reg = <0x17911000 0x1000>; +- +- #mbox-cells = <1>; +- }; +- +- timer@17920000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "arm,armv7-timer-mem"; +- reg = <0x17920000 0x1000>; +- clock-frequency = <19200000>; +- +- frame@17921000 { +- frame-number = <0>; +- interrupts = <0 8 0x4>, +- <0 7 0x4>; +- reg = <0x17921000 0x1000>, +- <0x17922000 0x1000>; +- }; +- +- frame@17923000 { +- frame-number = <1>; +- interrupts = <0 9 0x4>; +- reg = <0x17923000 0x1000>; +- status = "disabled"; +- }; +- +- frame@17924000 { +- frame-number = <2>; +- interrupts = <0 10 0x4>; +- reg = <0x17924000 0x1000>; +- status = "disabled"; +- }; +- +- frame@17925000 { +- frame-number = <3>; +- interrupts = <0 11 0x4>; +- reg = <0x17925000 0x1000>; +- status = "disabled"; +- }; +- +- frame@17926000 { +- frame-number = <4>; +- interrupts = <0 12 0x4>; +- reg = <0x17926000 0x1000>; +- status = "disabled"; +- }; +- +- frame@17927000 { +- frame-number = <5>; +- interrupts = <0 13 0x4>; +- reg = <0x17927000 0x1000>; +- status = "disabled"; +- }; +- +- frame@17928000 { +- frame-number = <6>; +- interrupts = <0 14 0x4>; +- reg = <0x17928000 0x1000>; +- status = "disabled"; +- }; +- }; +- +- intc: interrupt-controller@17a00000 { +- compatible = "arm,gic-v3"; +- reg = <0x17a00000 0x10000>, /* GICD */ +- <0x17b00000 0x100000>; /* GICR * 8 */ +- #interrupt-cells = <3>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- interrupt-controller; +- #redistributor-regions = <1>; +- redistributor-stride = <0x0 0x20000>; +- interrupts = ; +- }; +- }; +- +- tcsr_mutex: hwlock { +- compatible = "qcom,tcsr-mutex"; +- syscon = <&tcsr_mutex_regs 0 0x1000>; +- #hwlock-cells = <1>; +- }; +- +- sound: sound { +- }; +- +- thermal-zones { +- aoss-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 0>; +- +- trips { +- aoss_alert0: trip-point0 { +- temperature = <105000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- }; +- +- cpuss0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 1>; +- +- trips { +- cpuss0_alert0: trip-point0 { +- temperature = <125000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- }; +- +- cpuss1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 2>; +- +- trips { +- cpuss1_alert0: trip-point0 { +- temperature = <125000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- }; +- +- cpu0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 3>; +- +- trips { +- cpu0_alert0: trip-point0 { +- temperature = <70000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- +- cpu0_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 4>; +- +- trips { +- cpu1_alert0: trip-point0 { +- temperature = <70000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- +- cpu1_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 5>; +- +- trips { +- cpu2_alert0: trip-point0 { +- temperature = <70000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- +- cpu2_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- cpu3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 6>; +- +- trips { +- cpu3_alert0: trip-point0 { +- temperature = <70000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- +- cpu3_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- /* +- * According to what downstream DTS says, +- * the entire power efficient cluster has +- * only a single thermal sensor. +- */ +- +- pwr-cluster-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 7>; +- +- trips { +- pwr_cluster_alert0: trip-point0 { +- temperature = <70000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- +- pwr_cluster_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- gpu-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens 8>; +- +- trips { +- gpu_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm636-sony-xperia-ganges-mermaid.dts b/scripts/dtc/include-prefixes/arm64/qcom/sdm636-sony-xperia-ganges-mermaid.dts +deleted file mode 100644 +index bba1c2bce213..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm636-sony-xperia-ganges-mermaid.dts ++++ /dev/null +@@ -1,24 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Martin Botka +- */ +- +-/dts-v1/; +- +-#include "sdm630-sony-xperia-ganges-kirin.dts" +-#include "sdm636.dtsi" +- +-/ { +- model = "Sony Xperia 10 Plus"; +- compatible = "sony,mermaid-row", "qcom,sdm636"; +- +- /* SDM636 v1 */ +- qcom,msm-id = <345 0>; +- qcom,pmic-id = <0x1001b 0x101011a 0x00 0x00 0x1001b 0x201011a 0x00 0x00 0x1001b 0x102001a 0x00 0x00>; +-}; +- +-&sdc2_state_on { +- pinconf-clk { +- drive-strength = <14>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm636.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sdm636.dtsi +deleted file mode 100644 +index ae15d81fa3f9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm636.dtsi ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, AngeloGioacchino Del Regno +- * Copyright (c) 2020, Konrad Dybcio +- * Copyright (c) 2020, Martin Botka +- */ +- +-#include "sdm660.dtsi" +- +-/* +- * According to the downstream DTS, +- * 636 is basically a 660 except for +- * different CPU frequencies, Adreno +- * 509 instead of 512 and lack of +- * turing IP. These differences will +- * be addressed when the aforementioned +- * peripherals will be enabled upstream. +- */ +- +-&adreno_gpu { +- compatible = "qcom,adreno-509.0", "qcom,adreno"; +- /* Adreno 509 shares the frequency table with 512 */ +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm660-xiaomi-lavender.dts b/scripts/dtc/include-prefixes/arm64/qcom/sdm660-xiaomi-lavender.dts +deleted file mode 100644 +index 3e677fb7cfea..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm660-xiaomi-lavender.dts ++++ /dev/null +@@ -1,44 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2020, Alexey Minnekhanov +- */ +- +-/dts-v1/; +- +-#include "sdm660.dtsi" +- +-/ { +- model = "Xiaomi Redmi Note 7"; +- compatible = "xiaomi,lavender", "qcom,sdm660"; +- +- aliases { +- serial0 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ramoops@a0000000 { +- compatible = "ramoops"; +- reg = <0x0 0xa0000000 0x0 0x400000>; +- console-size = <0x20000>; +- record-size = <0x20000>; +- ftrace-size = <0x0>; +- pmsg-size = <0x20000>; +- }; +- }; +-}; +- +-&blsp1_uart2 { +- status = "okay"; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <8 4>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm660.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sdm660.dtsi +deleted file mode 100644 +index eccf6fde16b4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm660.dtsi ++++ /dev/null +@@ -1,251 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2018, Craig Tatlor. +- * Copyright (c) 2020, Alexey Minnekhanov +- * Copyright (c) 2020, AngeloGioacchino Del Regno +- * Copyright (c) 2020, Konrad Dybcio +- * Copyright (c) 2020, Martin Botka +- */ +- +-#include "sdm630.dtsi" +- +-&adreno_gpu { +- compatible = "qcom,adreno-512.0", "qcom,adreno"; +- operating-points-v2 = <&gpu_sdm660_opp_table>; +- +- gpu_sdm660_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- /* +- * 775MHz is only available on the highest speed bin +- * Though it cannot be used for now due to interconnect +- * framework not supporting multiple frequencies +- * at the same opp-level +- +- opp-750000000 { +- opp-hz = /bits/ 64 <750000000>; +- opp-level = ; +- opp-peak-kBps = <5412000>; +- opp-supported-hw = <0xCHECKME>; +- }; +- +- * These OPPs are correct, but we are lacking support for the +- * GPU regulator. Hence, disable them for now to prevent the +- * platform from hanging on high graphics loads. +- +- opp-700000000 { +- opp-hz = /bits/ 64 <700000000>; +- opp-level = ; +- opp-peak-kBps = <5184000>; +- opp-supported-hw = <0xFF>; +- }; +- +- opp-647000000 { +- opp-hz = /bits/ 64 <647000000>; +- opp-level = ; +- opp-peak-kBps = <4068000>; +- opp-supported-hw = <0xFF>; +- }; +- +- opp-588000000 { +- opp-hz = /bits/ 64 <588000000>; +- opp-level = ; +- opp-peak-kBps = <3072000>; +- opp-supported-hw = <0xFF>; +- }; +- +- opp-465000000 { +- opp-hz = /bits/ 64 <465000000>; +- opp-level = ; +- opp-peak-kBps = <2724000>; +- opp-supported-hw = <0xFF>; +- }; +- +- opp-370000000 { +- opp-hz = /bits/ 64 <370000000>; +- opp-level = ; +- opp-peak-kBps = <2188000>; +- opp-supported-hw = <0xFF>; +- }; +- */ +- +- opp-266000000 { +- opp-hz = /bits/ 64 <266000000>; +- opp-level = ; +- opp-peak-kBps = <1648000>; +- opp-supported-hw = <0xFF>; +- }; +- +- opp-160000000 { +- opp-hz = /bits/ 64 <160000000>; +- opp-level = ; +- opp-peak-kBps = <1200000>; +- opp-supported-hw = <0xFF>; +- }; +- }; +-}; +- +-&CPU0 { +- compatible = "qcom,kryo260"; +- capacity-dmips-mhz = <1024>; +- /delete-property/ operating-points-v2; +-}; +- +-&CPU1 { +- compatible = "qcom,kryo260"; +- capacity-dmips-mhz = <1024>; +- /delete-property/ operating-points-v2; +-}; +- +-&CPU2 { +- compatible = "qcom,kryo260"; +- capacity-dmips-mhz = <1024>; +- /delete-property/ operating-points-v2; +-}; +- +-&CPU3 { +- compatible = "qcom,kryo260"; +- capacity-dmips-mhz = <1024>; +- /delete-property/ operating-points-v2; +-}; +- +-&CPU4 { +- compatible = "qcom,kryo260"; +- capacity-dmips-mhz = <640>; +- /delete-property/ operating-points-v2; +-}; +- +-&CPU5 { +- compatible = "qcom,kryo260"; +- capacity-dmips-mhz = <640>; +- /delete-property/ operating-points-v2; +-}; +- +-&CPU6 { +- compatible = "qcom,kryo260"; +- capacity-dmips-mhz = <640>; +- /delete-property/ operating-points-v2; +-}; +- +-&CPU7 { +- compatible = "qcom,kryo260"; +- capacity-dmips-mhz = <640>; +- /delete-property/ operating-points-v2; +-}; +- +-&gcc { +- compatible = "qcom,gcc-sdm660"; +-}; +- +-&gpucc { +- compatible = "qcom,gpucc-sdm660"; +-}; +- +-&mdp { +- ports { +- port@1 { +- reg = <1>; +- mdp5_intf2_out: endpoint { +- remote-endpoint = <&dsi1_in>; +- }; +- }; +- }; +-}; +- +-&mdss { +- dsi1: dsi@c996000 { +- compatible = "qcom,mdss-dsi-ctrl"; +- reg = <0x0c996000 0x400>; +- reg-names = "dsi_ctrl"; +- +- /* DSI1 shares the OPP table with DSI0 */ +- operating-points-v2 = <&dsi_opp_table>; +- power-domains = <&rpmpd SDM660_VDDCX>; +- +- interrupt-parent = <&mdss>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; +- +- assigned-clocks = <&mmcc BYTE1_CLK_SRC>, +- <&mmcc PCLK1_CLK_SRC>; +- assigned-clock-parents = <&dsi1_phy 0>, +- <&dsi1_phy 1>; +- +- clocks = <&mmcc MDSS_MDP_CLK>, +- <&mmcc MDSS_BYTE1_CLK>, +- <&mmcc MDSS_BYTE1_INTF_CLK>, +- <&mmcc MNOC_AHB_CLK>, +- <&mmcc MDSS_AHB_CLK>, +- <&mmcc MDSS_AXI_CLK>, +- <&mmcc MISC_AHB_CLK>, +- <&mmcc MDSS_PCLK1_CLK>, +- <&mmcc MDSS_ESC1_CLK>; +- clock-names = "mdp_core", +- "byte", +- "byte_intf", +- "mnoc", +- "iface", +- "bus", +- "core_mmss", +- "pixel", +- "core"; +- +- phys = <&dsi1_phy>; +- phy-names = "dsi"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dsi1_in: endpoint { +- remote-endpoint = <&mdp5_intf2_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- dsi1_out: endpoint { +- }; +- }; +- }; +- }; +- +- dsi1_phy: dsi-phy@c996400 { +- compatible = "qcom,dsi-phy-14nm-660"; +- reg = <0x0c996400 0x100>, +- <0x0c996500 0x300>, +- <0x0c996800 0x188>; +- reg-names = "dsi_phy", +- "dsi_phy_lane", +- "dsi_pll"; +- +- #clock-cells = <1>; +- #phy-cells = <0>; +- +- clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; +- clock-names = "iface", "ref"; +- }; +-}; +- +-&mmcc { +- compatible = "qcom,mmcc-sdm660"; +- clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, +- <&sleep_clk>, +- <&gcc GCC_MMSS_GPLL0_CLK>, +- <&gcc GCC_MMSS_GPLL0_DIV_CLK>, +- <&dsi0_phy 1>, +- <&dsi0_phy 0>, +- <&dsi1_phy 1>, +- <&dsi1_phy 0>, +- <0>, +- <0>; +-}; +- +-&tlmm { +- compatible = "qcom,sdm660-pinctrl"; +-}; +- +-&tsens { +- #qcom,sensors = <14>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-cheza-r1.dts b/scripts/dtc/include-prefixes/arm64/qcom/sdm845-cheza-r1.dts +deleted file mode 100644 +index bd7c25bb8d35..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-cheza-r1.dts ++++ /dev/null +@@ -1,238 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Cheza board device tree source +- * +- * Copyright 2018 Google LLC. +- */ +- +-/dts-v1/; +- +-#include "sdm845-cheza.dtsi" +- +-/ { +- model = "Google Cheza (rev1)"; +- compatible = "google,cheza-rev1", "qcom,sdm845"; +- +- /* +- * FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children +- */ +- +- /* +- * NOTE: Technically pp3500_a is not the exact same signal as +- * pp3500_a_vbob (there's a load switch between them and the EC can +- * control pp3500_a via "en_pp3300_a"), but from the AP's point of +- * view they are the same. +- */ +- pp3500_a: +- pp3500_a_vbob: pp3500-a-vbob-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_bob"; +- +- /* +- * Comes on automatically when pp5000_ldo comes on, which +- * comes on automatically when ppvar_sys comes on +- */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3500000>; +- regulator-max-microvolt = <3500000>; +- +- vin-supply = <&ppvar_sys>; +- }; +- +- pp3300_dx_edp: pp3300-dx-edp-regulator { +- /* Yes, it's really 3.5 despite the name of the signal */ +- regulator-min-microvolt = <3500000>; +- regulator-max-microvolt = <3500000>; +- +- vin-supply = <&pp3500_a>; +- }; +-}; +- +-/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */ +- +-/* +- * L19 and L28 technically go to 3.3V, but most boards have old AOP firmware +- * that limits them to 3.0, and trying to run at 3.3V with that old firmware +- * prevents the system from booting. +- */ +-&src_pp3000_l19a { +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3008000>; +-}; +- +-&src_pp3300_l22a { +- /delete-property/regulator-boot-on; +- /delete-property/regulator-always-on; +-}; +- +-&src_pp3300_l28a { +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3008000>; +-}; +- +-&src_vreg_bob { +- regulator-min-microvolt = <3500000>; +- regulator-max-microvolt = <3500000>; +- vin-supply = <&pp3500_a_vbob>; +-}; +- +-/* +- * NON-REGULATOR OVERRIDES +- * (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label +- */ +- +-/* PINCTRL - board-specific pinctrl */ +- +-&tlmm { +- gpio-line-names = "AP_SPI_FP_MISO", +- "AP_SPI_FP_MOSI", +- "AP_SPI_FP_CLK", +- "AP_SPI_FP_CS_L", +- "UART_AP_TX_DBG_RX", +- "UART_DBG_TX_AP_RX", +- "", +- "FP_RST_L", +- "FCAM_EN", +- "", +- "EDP_BRIJ_IRQ", +- "EC_IN_RW_ODL", +- "", +- "RCAM_MCLK", +- "FCAM_MCLK", +- "", +- "RCAM_EN", +- "CCI0_SDA", +- "CCI0_SCL", +- "CCI1_SDA", +- "CCI1_SCL", +- "FCAM_RST_L", +- "", +- "PEN_RST_L", +- "PEN_IRQ_L", +- "", +- "RCAM_VSYNC", +- "ESIM_MISO", +- "ESIM_MOSI", +- "ESIM_CLK", +- "ESIM_CS_L", +- "AP_PEN_1V8_SDA", +- "AP_PEN_1V8_SCL", +- "AP_TS_I2C_SDA", +- "AP_TS_I2C_SCL", +- "RCAM_RST_L", +- "", +- "AP_EDP_BKLTEN", +- "AP_BRD_ID1", +- "BOOT_CONFIG_4", +- "AMP_IRQ_L", +- "EDP_BRIJ_I2C_SDA", +- "EDP_BRIJ_I2C_SCL", +- "EN_PP3300_DX_EDP", +- "SD_CD_ODL", +- "BT_UART_RTS", +- "BT_UART_CTS", +- "BT_UART_RXD", +- "BT_UART_TXD", +- "AMP_I2C_SDA", +- "AMP_I2C_SCL", +- "AP_BRD_ID3", +- "", +- "AP_EC_SPI_CLK", +- "AP_EC_SPI_CS_L", +- "AP_EC_SPI_MISO", +- "AP_EC_SPI_MOSI", +- "FORCED_USB_BOOT", +- "AMP_BCLK", +- "AMP_LRCLK", +- "AMP_DOUT", +- "AMP_DIN", +- "AP_BRD_ID2", +- "PEN_PDCT_L", +- "HP_MCLK", +- "HP_BCLK", +- "HP_LRCLK", +- "HP_DOUT", +- "HP_DIN", +- "", +- "", +- "", +- "", +- "BT_SLIMBUS_DATA", +- "BT_SLIMBUS_CLK", +- "AMP_RESET_L", +- "", +- "FCAM_VSYNC", +- "", +- "AP_SKU_ID1", +- "EC_WOV_BCLK", +- "EC_WOV_LRCLK", +- "EC_WOV_DOUT", +- "", +- "", +- "AP_H1_SPI_MISO", +- "AP_H1_SPI_MOSI", +- "AP_H1_SPI_CLK", +- "AP_H1_SPI_CS_L", +- "", +- "AP_SPI_CS0_L", +- "AP_SPI_MOSI", +- "AP_SPI_MISO", +- "", +- "", +- "AP_SPI_CLK", +- "", +- "RFFE6_CLK", +- "RFFE6_DATA", +- "BOOT_CONFIG_1", +- "BOOT_CONFIG_2", +- "BOOT_CONFIG_0", +- "EDP_BRIJ_EN", +- "", +- "USB_HS_TX_EN", +- "UIM2_DATA", +- "UIM2_CLK", +- "UIM2_RST", +- "UIM2_PRESENT", +- "UIM1_DATA", +- "UIM1_CLK", +- "UIM1_RST", +- "", +- "AP_SKU_ID2", +- "SDM_GRFC_8", +- "SDM_GRFC_9", +- "AP_RST_REQ", +- "HP_IRQ", +- "TS_RESET_L", +- "PEN_EJECT_ODL", +- "HUB_RST_L", +- "FP_TO_AP_IRQ", +- "AP_EC_INT_L", +- "", +- "", +- "TS_INT_L", +- "AP_SUSPEND_L", +- "SDM_GRFC_3", +- "", +- "H1_AP_INT_ODL", +- "QLINK_REQ", +- "QLINK_EN", +- "SDM_GRFC_2", +- "BOOT_CONFIG_3", +- "WMSS_RESET_L", +- "SDM_GRFC_0", +- "SDM_GRFC_1", +- "RFFE3_DATA", +- "RFFE3_CLK", +- "RFFE4_DATA", +- "RFFE4_CLK", +- "RFFE5_DATA", +- "RFFE5_CLK", +- "GNSS_EN", +- "WCI2_LTE_COEX_RXD", +- "WCI2_LTE_COEX_TXD", +- "AP_RAM_ID1", +- "AP_RAM_ID2", +- "RFFE1_DATA", +- "RFFE1_CLK"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-cheza-r2.dts b/scripts/dtc/include-prefixes/arm64/qcom/sdm845-cheza-r2.dts +deleted file mode 100644 +index 2b7230594ecb..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-cheza-r2.dts ++++ /dev/null +@@ -1,238 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Cheza board device tree source +- * +- * Copyright 2018 Google LLC. +- */ +- +-/dts-v1/; +- +-#include "sdm845-cheza.dtsi" +- +-/ { +- model = "Google Cheza (rev2)"; +- compatible = "google,cheza-rev2", "qcom,sdm845"; +- +- /* +- * FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children +- */ +- +- /* +- * NOTE: Technically pp3500_a is not the exact same signal as +- * pp3500_a_vbob (there's a load switch between them and the EC can +- * control pp3500_a via "en_pp3300_a"), but from the AP's point of +- * view they are the same. +- */ +- pp3500_a: +- pp3500_a_vbob: pp3500-a-vbob-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_bob"; +- +- /* +- * Comes on automatically when pp5000_ldo comes on, which +- * comes on automatically when ppvar_sys comes on +- */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3500000>; +- regulator-max-microvolt = <3500000>; +- +- vin-supply = <&ppvar_sys>; +- }; +- +- pp3300_dx_edp: pp3300-dx-edp-regulator { +- /* Yes, it's really 3.5 despite the name of the signal */ +- regulator-min-microvolt = <3500000>; +- regulator-max-microvolt = <3500000>; +- +- vin-supply = <&pp3500_a>; +- }; +-}; +- +-/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */ +- +-/* +- * L19 and L28 technically go to 3.3V, but most boards have old AOP firmware +- * that limits them to 3.0, and trying to run at 3.3V with that old firmware +- * prevents the system from booting. +- */ +-&src_pp3000_l19a { +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3008000>; +-}; +- +-&src_pp3300_l22a { +- /delete-property/regulator-boot-on; +- /delete-property/regulator-always-on; +-}; +- +-&src_pp3300_l28a { +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3008000>; +-}; +- +-&src_vreg_bob { +- regulator-min-microvolt = <3500000>; +- regulator-max-microvolt = <3500000>; +- vin-supply = <&pp3500_a_vbob>; +-}; +- +-/* +- * NON-REGULATOR OVERRIDES +- * (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label +- */ +- +-/* PINCTRL - board-specific pinctrl */ +- +-&tlmm { +- gpio-line-names = "AP_SPI_FP_MISO", +- "AP_SPI_FP_MOSI", +- "AP_SPI_FP_CLK", +- "AP_SPI_FP_CS_L", +- "UART_AP_TX_DBG_RX", +- "UART_DBG_TX_AP_RX", +- "BRIJ_SUSPEND", +- "FP_RST_L", +- "FCAM_EN", +- "", +- "EDP_BRIJ_IRQ", +- "EC_IN_RW_ODL", +- "", +- "RCAM_MCLK", +- "FCAM_MCLK", +- "", +- "RCAM_EN", +- "CCI0_SDA", +- "CCI0_SCL", +- "CCI1_SDA", +- "CCI1_SCL", +- "FCAM_RST_L", +- "FPMCU_BOOT0", +- "PEN_RST_L", +- "PEN_IRQ_L", +- "FPMCU_SEL_OD", +- "RCAM_VSYNC", +- "ESIM_MISO", +- "ESIM_MOSI", +- "ESIM_CLK", +- "ESIM_CS_L", +- "AP_PEN_1V8_SDA", +- "AP_PEN_1V8_SCL", +- "AP_TS_I2C_SDA", +- "AP_TS_I2C_SCL", +- "RCAM_RST_L", +- "", +- "AP_EDP_BKLTEN", +- "AP_BRD_ID1", +- "BOOT_CONFIG_4", +- "AMP_IRQ_L", +- "EDP_BRIJ_I2C_SDA", +- "EDP_BRIJ_I2C_SCL", +- "EN_PP3300_DX_EDP", +- "SD_CD_ODL", +- "BT_UART_RTS", +- "BT_UART_CTS", +- "BT_UART_RXD", +- "BT_UART_TXD", +- "AMP_I2C_SDA", +- "AMP_I2C_SCL", +- "AP_BRD_ID3", +- "", +- "AP_EC_SPI_CLK", +- "AP_EC_SPI_CS_L", +- "AP_EC_SPI_MISO", +- "AP_EC_SPI_MOSI", +- "FORCED_USB_BOOT", +- "AMP_BCLK", +- "AMP_LRCLK", +- "AMP_DOUT", +- "AMP_DIN", +- "AP_BRD_ID2", +- "PEN_PDCT_L", +- "HP_MCLK", +- "HP_BCLK", +- "HP_LRCLK", +- "HP_DOUT", +- "HP_DIN", +- "", +- "", +- "", +- "", +- "BT_SLIMBUS_DATA", +- "BT_SLIMBUS_CLK", +- "AMP_RESET_L", +- "", +- "FCAM_VSYNC", +- "", +- "AP_SKU_ID1", +- "EC_WOV_BCLK", +- "EC_WOV_LRCLK", +- "EC_WOV_DOUT", +- "", +- "", +- "AP_H1_SPI_MISO", +- "AP_H1_SPI_MOSI", +- "AP_H1_SPI_CLK", +- "AP_H1_SPI_CS_L", +- "", +- "AP_SPI_CS0_L", +- "AP_SPI_MOSI", +- "AP_SPI_MISO", +- "", +- "", +- "AP_SPI_CLK", +- "", +- "RFFE6_CLK", +- "RFFE6_DATA", +- "BOOT_CONFIG_1", +- "BOOT_CONFIG_2", +- "BOOT_CONFIG_0", +- "EDP_BRIJ_EN", +- "", +- "USB_HS_TX_EN", +- "UIM2_DATA", +- "UIM2_CLK", +- "UIM2_RST", +- "UIM2_PRESENT", +- "UIM1_DATA", +- "UIM1_CLK", +- "UIM1_RST", +- "", +- "AP_SKU_ID2", +- "SDM_GRFC_8", +- "SDM_GRFC_9", +- "AP_RST_REQ", +- "HP_IRQ", +- "TS_RESET_L", +- "PEN_EJECT_ODL", +- "HUB_RST_L", +- "FP_TO_AP_IRQ", +- "AP_EC_INT_L", +- "", +- "", +- "TS_INT_L", +- "AP_SUSPEND_L", +- "SDM_GRFC_3", +- "", +- "H1_AP_INT_ODL", +- "QLINK_REQ", +- "QLINK_EN", +- "SDM_GRFC_2", +- "BOOT_CONFIG_3", +- "WMSS_RESET_L", +- "SDM_GRFC_0", +- "SDM_GRFC_1", +- "RFFE3_DATA", +- "RFFE3_CLK", +- "RFFE4_DATA", +- "RFFE4_CLK", +- "RFFE5_DATA", +- "RFFE5_CLK", +- "GNSS_EN", +- "WCI2_LTE_COEX_RXD", +- "WCI2_LTE_COEX_TXD", +- "AP_RAM_ID1", +- "AP_RAM_ID2", +- "RFFE1_DATA", +- "RFFE1_CLK"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-cheza-r3.dts b/scripts/dtc/include-prefixes/arm64/qcom/sdm845-cheza-r3.dts +deleted file mode 100644 +index 1ba67be08f81..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-cheza-r3.dts ++++ /dev/null +@@ -1,174 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Cheza board device tree source +- * +- * Copyright 2018 Google LLC. +- */ +- +-/dts-v1/; +- +-#include "sdm845-cheza.dtsi" +- +-/ { +- model = "Google Cheza (rev3+)"; +- compatible = "google,cheza", "qcom,sdm845"; +-}; +- +-/* PINCTRL - board-specific pinctrl */ +- +-&tlmm { +- gpio-line-names = "AP_SPI_FP_MISO", +- "AP_SPI_FP_MOSI", +- "AP_SPI_FP_CLK", +- "AP_SPI_FP_CS_L", +- "UART_AP_TX_DBG_RX", +- "UART_DBG_TX_AP_RX", +- "BRIJ_SUSPEND", +- "FP_RST_L", +- "FCAM_EN", +- "", +- "EDP_BRIJ_IRQ", +- "EC_IN_RW_ODL", +- "", +- "RCAM_MCLK", +- "FCAM_MCLK", +- "", +- "RCAM_EN", +- "CCI0_SDA", +- "CCI0_SCL", +- "CCI1_SDA", +- "CCI1_SCL", +- "FCAM_RST_L", +- "FPMCU_BOOT0", +- "PEN_RST_L", +- "PEN_IRQ_L", +- "FPMCU_SEL_OD", +- "RCAM_VSYNC", +- "ESIM_MISO", +- "ESIM_MOSI", +- "ESIM_CLK", +- "ESIM_CS_L", +- "AP_PEN_1V8_SDA", +- "AP_PEN_1V8_SCL", +- "AP_TS_I2C_SDA", +- "AP_TS_I2C_SCL", +- "RCAM_RST_L", +- "", +- "AP_EDP_BKLTEN", +- "AP_BRD_ID0", +- "BOOT_CONFIG_4", +- "AMP_IRQ_L", +- "EDP_BRIJ_I2C_SDA", +- "EDP_BRIJ_I2C_SCL", +- "EN_PP3300_DX_EDP", +- "SD_CD_ODL", +- "BT_UART_RTS", +- "BT_UART_CTS", +- "BT_UART_RXD", +- "BT_UART_TXD", +- "AMP_I2C_SDA", +- "AMP_I2C_SCL", +- "AP_BRD_ID2", +- "", +- "AP_EC_SPI_CLK", +- "AP_EC_SPI_CS_L", +- "AP_EC_SPI_MISO", +- "AP_EC_SPI_MOSI", +- "FORCED_USB_BOOT", +- "AMP_BCLK", +- "AMP_LRCLK", +- "AMP_DOUT", +- "AMP_DIN", +- "AP_BRD_ID1", +- "PEN_PDCT_L", +- "HP_MCLK", +- "HP_BCLK", +- "HP_LRCLK", +- "HP_DOUT", +- "HP_DIN", +- "", +- "", +- "", +- "", +- "BT_SLIMBUS_DATA", +- "BT_SLIMBUS_CLK", +- "AMP_RESET_L", +- "", +- "FCAM_VSYNC", +- "", +- "AP_SKU_ID0", +- "EC_WOV_BCLK", +- "EC_WOV_LRCLK", +- "EC_WOV_DOUT", +- "", +- "", +- "AP_H1_SPI_MISO", +- "AP_H1_SPI_MOSI", +- "AP_H1_SPI_CLK", +- "AP_H1_SPI_CS_L", +- "", +- "AP_SPI_CS0_L", +- "AP_SPI_MOSI", +- "AP_SPI_MISO", +- "", +- "", +- "AP_SPI_CLK", +- "", +- "RFFE6_CLK", +- "RFFE6_DATA", +- "BOOT_CONFIG_1", +- "BOOT_CONFIG_2", +- "BOOT_CONFIG_0", +- "EDP_BRIJ_EN", +- "", +- "USB_HS_TX_EN", +- "UIM2_DATA", +- "UIM2_CLK", +- "UIM2_RST", +- "UIM2_PRESENT", +- "UIM1_DATA", +- "UIM1_CLK", +- "UIM1_RST", +- "", +- "AP_SKU_ID1", +- "SDM_GRFC_8", +- "SDM_GRFC_9", +- "AP_RST_REQ", +- "HP_IRQ", +- "TS_RESET_L", +- "PEN_EJECT_ODL", +- "HUB_RST_L", +- "FP_TO_AP_IRQ", +- "AP_EC_INT_L", +- "", +- "", +- "TS_INT_L", +- "AP_SUSPEND_L", +- "SDM_GRFC_3", +- /* +- * AP_FLASH_WP_L is crossystem ABI. Rev3 schematics +- * call it BIOS_FLASH_WP_R_L. +- */ +- "AP_FLASH_WP_L", +- "H1_AP_INT_ODL", +- "QLINK_REQ", +- "QLINK_EN", +- "SDM_GRFC_2", +- "BOOT_CONFIG_3", +- "WMSS_RESET_L", +- "SDM_GRFC_0", +- "SDM_GRFC_1", +- "RFFE3_DATA", +- "RFFE3_CLK", +- "RFFE4_DATA", +- "RFFE4_CLK", +- "RFFE5_DATA", +- "RFFE5_CLK", +- "GNSS_EN", +- "WCI2_LTE_COEX_RXD", +- "WCI2_LTE_COEX_TXD", +- "AP_RAM_ID0", +- "AP_RAM_ID1", +- "RFFE1_DATA", +- "RFFE1_CLK"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-cheza.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sdm845-cheza.dtsi +deleted file mode 100644 +index dfd1b42c07fd..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-cheza.dtsi ++++ /dev/null +@@ -1,1323 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Cheza device tree source (common between revisions) +- * +- * Copyright 2018 Google LLC. +- */ +- +-#include +-#include +-#include +-#include "sdm845.dtsi" +- +-/* PMICs depend on spmi_bus label and so must come after SoC */ +-#include "pm8005.dtsi" +-#include "pm8998.dtsi" +- +-/ { +- aliases { +- bluetooth0 = &bluetooth; +- hsuart0 = &uart6; +- serial0 = &uart9; +- wifi0 = &wifi; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&cros_ec_pwm 0>; +- enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; +- power-supply = <&ppvar_sys>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ap_edp_bklten>; +- }; +- +- /* FIXED REGULATORS - parents above children */ +- +- /* This is the top level supply and variable voltage */ +- ppvar_sys: ppvar-sys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "ppvar_sys"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* This divides ppvar_sys by 2, so voltage is variable */ +- src_vph_pwr: src-vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "src_vph_pwr"; +- +- /* EC turns on with switchcap_on_l; always on for AP */ +- regulator-always-on; +- regulator-boot-on; +- +- vin-supply = <&ppvar_sys>; +- }; +- +- pp5000_a: pp5000-a-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "pp5000_a"; +- +- /* EC turns on with en_pp5000_a; always on for AP */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- vin-supply = <&ppvar_sys>; +- }; +- +- src_vreg_bob: src-vreg-bob-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "src_vreg_bob"; +- +- /* EC turns on with vbob_en; always on for AP */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3600000>; +- regulator-max-microvolt = <3600000>; +- +- vin-supply = <&ppvar_sys>; +- }; +- +- pp3300_dx_edp: pp3300-dx-edp-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "pp3300_dx_edp"; +- +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&en_pp3300_dx_edp>; +- }; +- +- /* +- * Apparently RPMh does not provide support for PM8998 S4 because it +- * is always-on; model it as a fixed regulator. +- */ +- src_pp1800_s4a: pm8998-smps4 { +- compatible = "regulator-fixed"; +- regulator-name = "src_pp1800_s4a"; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-always-on; +- regulator-boot-on; +- +- vin-supply = <&src_vph_pwr>; +- }; +- +- /* BOARD-SPECIFIC TOP LEVEL NODES */ +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pen_eject_odl>; +- +- pen-insert { +- label = "Pen Insert"; +- /* Insert = low, eject = high */ +- gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; +- linux,code = ; +- linux,input-type = ; +- wakeup-source; +- }; +- }; +- +- panel: panel { +- compatible ="innolux,p120zdg-bf1"; +- power-supply = <&pp3300_dx_edp>; +- backlight = <&backlight>; +- no-hpd; +- +- ports { +- panel_in: port { +- panel_in_edp: endpoint { +- remote-endpoint = <&sn65dsi86_out>; +- }; +- }; +- }; +- }; +-}; +- +-/* +- * Reserved memory changes +- * +- * Putting this all together (out of order with the rest of the file) to keep +- * all modifications to the memory map (from sdm845.dtsi) in one place. +- */ +- +-/* +- * Our mpss_region is 8MB bigger than the default one and that conflicts +- * with venus_mem and cdsp_mem. +- * +- * For venus_mem we'll delete and re-create at a different address. +- * +- * cdsp_mem isn't used on cheza right now so we won't bother re-creating it; but +- * that also means we need to delete cdsp_pas. +- */ +-/delete-node/ &venus_mem; +-/delete-node/ &cdsp_mem; +-/delete-node/ &cdsp_pas; +-/delete-node/ &gpu_mem; +- +-/* Increase the size from 120 MB to 128 MB */ +-&mpss_region { +- reg = <0 0x8e000000 0 0x8000000>; +-}; +- +-/* Increase the size from 2MB to 8MB */ +-&rmtfs_mem { +- reg = <0 0x88f00000 0 0x800000>; +-}; +- +-/ { +- reserved-memory { +- venus_mem: memory@96000000 { +- reg = <0 0x96000000 0 0x500000>; +- no-map; +- }; +- }; +-}; +- +-&qspi { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- +- /* +- * In theory chip supports up to 104 MHz and controller up +- * to 80 MHz, but above 25 MHz wasn't reliable so we'll use +- * that for now. b:117440651 +- */ +- spi-max-frequency = <25000000>; +- spi-tx-bus-width = <2>; +- spi-rx-bus-width = <2>; +- }; +-}; +- +- +-&apps_rsc { +- pm8998-rpmh-regulators { +- compatible = "qcom,pm8998-rpmh-regulators"; +- qcom,pmic-id = "a"; +- +- vdd-s1-supply = <&src_vph_pwr>; +- vdd-s2-supply = <&src_vph_pwr>; +- vdd-s3-supply = <&src_vph_pwr>; +- vdd-s4-supply = <&src_vph_pwr>; +- vdd-s5-supply = <&src_vph_pwr>; +- vdd-s6-supply = <&src_vph_pwr>; +- vdd-s7-supply = <&src_vph_pwr>; +- vdd-s8-supply = <&src_vph_pwr>; +- vdd-s9-supply = <&src_vph_pwr>; +- vdd-s10-supply = <&src_vph_pwr>; +- vdd-s11-supply = <&src_vph_pwr>; +- vdd-s12-supply = <&src_vph_pwr>; +- vdd-s13-supply = <&src_vph_pwr>; +- vdd-l1-l27-supply = <&src_pp1025_s7a>; +- vdd-l2-l8-l17-supply = <&src_pp1350_s3a>; +- vdd-l3-l11-supply = <&src_pp1025_s7a>; +- vdd-l4-l5-supply = <&src_pp1025_s7a>; +- vdd-l6-supply = <&src_vph_pwr>; +- vdd-l7-l12-l14-l15-supply = <&src_pp2040_s5a>; +- vdd-l9-supply = <&src_pp2040_s5a>; +- vdd-l10-l23-l25-supply = <&src_vreg_bob>; +- vdd-l13-l19-l21-supply = <&src_vreg_bob>; +- vdd-l16-l28-supply = <&src_vreg_bob>; +- vdd-l18-l22-supply = <&src_vreg_bob>; +- vdd-l20-l24-supply = <&src_vreg_bob>; +- vdd-l26-supply = <&src_pp1350_s3a>; +- vin-lvs-1-2-supply = <&src_pp1800_s4a>; +- +- src_pp1125_s2a: smps2 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- src_pp1350_s3a: smps3 { +- regulator-min-microvolt = <1352000>; +- regulator-max-microvolt = <1352000>; +- }; +- +- src_pp2040_s5a: smps5 { +- regulator-min-microvolt = <1904000>; +- regulator-max-microvolt = <2040000>; +- }; +- +- src_pp1025_s7a: smps7 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1028000>; +- }; +- +- vdd_qusb_hs0: +- vdda_hp_pcie_core: +- vdda_mipi_csi0_0p9: +- vdda_mipi_csi1_0p9: +- vdda_mipi_csi2_0p9: +- vdda_mipi_dsi0_pll: +- vdda_mipi_dsi1_pll: +- vdda_qlink_lv: +- vdda_qlink_lv_ck: +- vdda_qrefs_0p875: +- vdda_pcie_core: +- vdda_pll_cc_ebi01: +- vdda_pll_cc_ebi23: +- vdda_sp_sensor: +- vdda_ufs1_core: +- vdda_ufs2_core: +- vdda_usb1_ss_core: +- vdda_usb2_ss_core: +- src_pp875_l1a: ldo1 { +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_10: +- src_pp1200_l2a: ldo2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- +- /* TODO: why??? */ +- regulator-always-on; +- }; +- +- pp1000_l3a_sdr845: ldo3 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-initial-mode = ; +- }; +- +- vdd_wcss_cx: +- vdd_wcss_mx: +- vdda_wcss_pll: +- src_pp800_l5a: ldo5 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_13: +- src_pp1800_l6a: ldo6 { +- regulator-min-microvolt = <1856000>; +- regulator-max-microvolt = <1856000>; +- regulator-initial-mode = ; +- }; +- +- pp1800_l7a_wcn3990: ldo7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- src_pp1200_l8a: ldo8 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1248000>; +- regulator-initial-mode = ; +- }; +- +- pp1800_dx_pen: +- src_pp1800_l9a: ldo9 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- src_pp1800_l10a: ldo10 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- pp1000_l11a_sdr845: ldo11 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1048000>; +- regulator-initial-mode = ; +- }; +- +- vdd_qfprom: +- vdd_qfprom_sp: +- vdda_apc1_cs_1p8: +- vdda_gfx_cs_1p8: +- vdda_qrefs_1p8: +- vdda_qusb_hs0_1p8: +- vddpx_11: +- src_pp1800_l12a: ldo12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_2: +- src_pp2950_l13a: ldo13 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- src_pp1800_l14a: ldo14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- src_pp1800_l15a: ldo15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- pp2700_l16a: ldo16 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2704000>; +- regulator-initial-mode = ; +- }; +- +- src_pp1300_l17a: ldo17 { +- regulator-min-microvolt = <1304000>; +- regulator-max-microvolt = <1304000>; +- regulator-initial-mode = ; +- }; +- +- pp2700_l18a: ldo18 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- /* +- * NOTE: this rail should have been called +- * src_pp3300_l19a in the schematic +- */ +- src_pp3000_l19a: ldo19 { +- regulator-min-microvolt = <3304000>; +- regulator-max-microvolt = <3304000>; +- +- regulator-initial-mode = ; +- }; +- +- src_pp2950_l20a: ldo20 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- src_pp2950_l21a: ldo21 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- pp3300_hub: +- src_pp3300_l22a: ldo22 { +- regulator-min-microvolt = <3304000>; +- regulator-max-microvolt = <3304000>; +- regulator-initial-mode = ; +- /* +- * HACK: Should add a usb hub node and driver +- * to turn this on and off at suspend/resume time +- */ +- regulator-boot-on; +- regulator-always-on; +- }; +- +- pp3300_l23a_ch1_wcn3990: ldo23 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- +- vdda_qusb_hs0_3p1: +- src_pp3075_l24a: ldo24 { +- regulator-min-microvolt = <3088000>; +- regulator-max-microvolt = <3088000>; +- regulator-initial-mode = ; +- }; +- +- pp3300_l25a_ch0_wcn3990: ldo25 { +- regulator-min-microvolt = <3304000>; +- regulator-max-microvolt = <3304000>; +- regulator-initial-mode = ; +- }; +- +- pp1200_hub: +- vdda_hp_pcie_1p2: +- vdda_hv_ebi0: +- vdda_hv_ebi1: +- vdda_hv_ebi2: +- vdda_hv_ebi3: +- vdda_mipi_csi_1p25: +- vdda_mipi_dsi0_1p2: +- vdda_mipi_dsi1_1p2: +- vdda_pcie_1p2: +- vdda_ufs1_1p2: +- vdda_ufs2_1p2: +- vdda_usb1_ss_1p2: +- vdda_usb2_ss_1p2: +- src_pp1200_l26a: ldo26 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- pp3300_dx_pen: +- src_pp3300_l28a: ldo28 { +- regulator-min-microvolt = <3304000>; +- regulator-max-microvolt = <3304000>; +- regulator-initial-mode = ; +- }; +- +- src_pp1800_lvs1: lvs1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- src_pp1800_lvs2: lvs2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- }; +- +- pm8005-rpmh-regulators { +- compatible = "qcom,pm8005-rpmh-regulators"; +- qcom,pmic-id = "c"; +- +- vdd-s1-supply = <&src_vph_pwr>; +- vdd-s2-supply = <&src_vph_pwr>; +- vdd-s3-supply = <&src_vph_pwr>; +- vdd-s4-supply = <&src_vph_pwr>; +- +- src_pp600_s3c: smps3 { +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <600000>; +- }; +- }; +-}; +- +-&dsi0 { +- status = "okay"; +- vdda-supply = <&vdda_mipi_dsi0_1p2>; +- +- ports { +- port@1 { +- endpoint { +- remote-endpoint = <&sn65dsi86_in>; +- data-lanes = <0 1 2 3>; +- }; +- }; +- }; +-}; +- +-&dsi0_phy { +- status = "okay"; +- vdds-supply = <&vdda_mipi_dsi0_pll>; +-}; +- +-edp_brij_i2c: &i2c3 { +- status = "okay"; +- clock-frequency = <400000>; +- +- sn65dsi86_bridge: bridge@2d { +- compatible = "ti,sn65dsi86"; +- reg = <0x2d>; +- pinctrl-names = "default"; +- pinctrl-0 = <&edp_brij_en &edp_brij_irq>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; +- +- enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; +- +- vpll-supply = <&src_pp1800_s4a>; +- vccio-supply = <&src_pp1800_s4a>; +- vcca-supply = <&src_pp1200_l2a>; +- vcc-supply = <&src_pp1200_l2a>; +- +- clocks = <&rpmhcc RPMH_LN_BB_CLK2>; +- clock-names = "refclk"; +- +- no-hpd; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- sn65dsi86_in: endpoint { +- remote-endpoint = <&dsi0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- sn65dsi86_out: endpoint { +- remote-endpoint = <&panel_in_edp>; +- }; +- }; +- }; +- }; +-}; +- +-ap_pen_1v8: &i2c11 { +- status = "okay"; +- clock-frequency = <400000>; +- +- digitizer@9 { +- compatible = "wacom,w9013", "hid-over-i2c"; +- reg = <0x9>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>; +- +- vdd-supply = <&pp3300_dx_pen>; +- vddl-supply = <&pp1800_dx_pen>; +- post-power-on-delay-ms = <100>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <24 IRQ_TYPE_LEVEL_LOW>; +- +- hid-descr-addr = <0x1>; +- }; +-}; +- +-amp_i2c: &i2c12 { +- status = "okay"; +- clock-frequency = <400000>; +-}; +- +-ap_ts_i2c: &i2c14 { +- status = "okay"; +- clock-frequency = <400000>; +- +- touchscreen@10 { +- compatible = "elan,ekth3500"; +- reg = <0x10>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ts_int_l &ts_reset_l>; +- +- interrupt-parent = <&tlmm>; +- interrupts = <125 IRQ_TYPE_LEVEL_LOW>; +- +- vcc33-supply = <&src_pp3300_l28a>; +- +- reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&ipa { +- status = "okay"; +- modem-init; +-}; +- +-&lpasscc { +- status = "okay"; +-}; +- +-&mdss { +- status = "okay"; +-}; +- +-&mdss_mdp { +- status = "okay"; +-}; +- +-/* +- * Cheza fw does not properly program the GPU aperture to allow the +- * GPU to update the SMMU pagetables for context switches. Work +- * around this by dropping the "qcom,adreno-smmu" compat string. +- */ +-&adreno_smmu { +- compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; +-}; +- +-&mss_pil { +- iommus = <&apps_smmu 0x781 0x0>, +- <&apps_smmu 0x724 0x3>; +-}; +- +-&pm8998_pwrkey { +- status = "disabled"; +-}; +- +-&qupv3_id_0 { +- status = "okay"; +- iommus = <&apps_smmu 0x0 0x3>; +-}; +- +-&qupv3_id_1 { +- status = "okay"; +- iommus = <&apps_smmu 0x6c0 0x3>; +-}; +- +-&sdhc_2 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_cd_odl>; +- +- vmmc-supply = <&src_pp2950_l21a>; +- vqmmc-supply = <&vddpx_2>; +- +- cd-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; +-}; +- +-&spi0 { +- status = "okay"; +-}; +- +-&spi5 { +- status = "okay"; +- +- tpm@0 { +- compatible = "google,cr50"; +- reg = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&h1_ap_int_odl>; +- spi-max-frequency = <800000>; +- interrupt-parent = <&tlmm>; +- interrupts = <129 IRQ_TYPE_EDGE_RISING>; +- }; +-}; +- +-&spi10 { +- status = "okay"; +- +- cros_ec: ec@0 { +- compatible = "google,cros-ec-spi"; +- reg = <0>; +- interrupt-parent = <&tlmm>; +- interrupts = <122 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ec_ap_int_l>; +- spi-max-frequency = <3000000>; +- +- cros_ec_pwm: ec-pwm { +- compatible = "google,cros-ec-pwm"; +- #pwm-cells = <1>; +- }; +- +- i2c_tunnel: i2c-tunnel { +- compatible = "google,cros-ec-i2c-tunnel"; +- google,remote-bus = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +-}; +- +-#include +-#include +- +-&uart6 { +- status = "okay"; +- +- bluetooth: wcn3990-bt { +- compatible = "qcom,wcn3990-bt"; +- vddio-supply = <&src_pp1800_s4a>; +- vddxo-supply = <&pp1800_l7a_wcn3990>; +- vddrf-supply = <&src_pp1300_l17a>; +- vddch0-supply = <&pp3300_l25a_ch0_wcn3990>; +- max-speed = <3200000>; +- }; +-}; +- +-&uart9 { +- status = "okay"; +-}; +- +-&ufs_mem_hc { +- status = "okay"; +- +- reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; +- +- vcc-supply = <&src_pp2950_l20a>; +- vcc-max-microamp = <600000>; +-}; +- +-&ufs_mem_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vdda_ufs1_core>; +- vdda-pll-supply = <&vdda_ufs1_1p2>; +-}; +- +-&usb_1 { +- status = "okay"; +- +- /* We'll use this as USB 2.0 only */ +- qcom,select-utmi-as-pipe-clk; +-}; +- +-&usb_1_dwc3 { +- /* +- * The hardware design intends this port to be hooked up in peripheral +- * mode, so we'll hardcode it here. Some details: +- * - SDM845 expects only a single Type C connector so it has only one +- * native Type C port but cheza has two Type C connectors. +- * - The only source of DP is the single native Type C port. +- * - On cheza we want to be able to hook DP up to _either_ of the +- * two Type C connectors and want to be able to achieve 4 lanes of DP. +- * - When you configure a Type C port for 4 lanes of DP you lose USB3. +- * - In order to make everything work, the native Type C port is always +- * configured as 4-lanes DP so it's always available. +- * - The extra USB3 port on SDM845 goes to a USB 3 hub which is then +- * sent to the two Type C connectors. +- * - The extra USB2 lines from the native Type C port are always +- * setup as "peripheral" so that we can mux them over to one connector +- * or the other if someone needs the connector configured as a gadget +- * (but they only get USB2 speeds). +- * +- * All the hardware muxes would allow us to hook things up in different +- * ways to some potential benefit for static configurations (you could +- * achieve extra USB2 bandwidth by using two different ports for the +- * two connectors or possibly even get USB3 peripheral mode), but in +- * each case you end up forcing to disconnect/reconnect an in-use +- * USB session in some cases depending on what you hotplug into the +- * other connector. Thus hardcoding this as peripheral makes sense. +- */ +- dr_mode = "peripheral"; +- +- /* +- * We always need the high speed pins as 4-lanes DP in case someone +- * hotplugs a DP peripheral. Thus limit this port to a max of high +- * speed. +- */ +- maximum-speed = "high-speed"; +- +- /* +- * We don't need the usb3-phy since we run in highspeed mode always, so +- * re-define these properties removing the superspeed USB PHY reference. +- */ +- phys = <&usb_1_hsphy>; +- phy-names = "usb2-phy"; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- +- vdd-supply = <&vdda_usb1_ss_core>; +- vdda-pll-supply = <&vdda_qusb_hs0_1p8>; +- vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; +- +- qcom,imp-res-offset-value = <8>; +- qcom,hstx-trim-value = ; +- qcom,preemphasis-level = ; +- qcom,preemphasis-width = ; +-}; +- +-&usb_2 { +- status = "okay"; +-}; +- +-&usb_2_dwc3 { +- /* We have this hooked up to a hub and we always use in host mode */ +- dr_mode = "host"; +-}; +- +-&usb_2_hsphy { +- status = "okay"; +- +- vdd-supply = <&vdda_usb2_ss_core>; +- vdda-pll-supply = <&vdda_qusb_hs0_1p8>; +- vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; +- +- qcom,imp-res-offset-value = <8>; +- qcom,hstx-trim-value = ; +-}; +- +-&usb_2_qmpphy { +- status = "okay"; +- +- vdda-phy-supply = <&vdda_usb2_ss_1p2>; +- vdda-pll-supply = <&vdda_usb2_ss_core>; +-}; +- +-&wifi { +- status = "okay"; +- +- vdd-0.8-cx-mx-supply = <&src_pp800_l5a >; +- vdd-1.8-xo-supply = <&pp1800_l7a_wcn3990>; +- vdd-1.3-rfa-supply = <&src_pp1300_l17a>; +- vdd-3.3-ch0-supply = <&pp3300_l25a_ch0_wcn3990>; +-}; +- +-/* PINCTRL - additions to nodes defined in sdm845.dtsi */ +- +-&qspi_cs0 { +- pinconf { +- pins = "gpio90"; +- bias-disable; +- }; +-}; +- +-&qspi_clk { +- pinconf { +- pins = "gpio95"; +- bias-disable; +- }; +-}; +- +-&qspi_data01 { +- pinconf { +- pins = "gpio91", "gpio92"; +- +- /* High-Z when no transfers; nice to park the lines */ +- bias-pull-up; +- }; +-}; +- +-&qup_i2c3_default { +- pinconf { +- pins = "gpio41", "gpio42"; +- drive-strength = <2>; +- +- /* Has external pullup */ +- bias-disable; +- }; +-}; +- +-&qup_i2c11_default { +- pinconf { +- pins = "gpio31", "gpio32"; +- drive-strength = <2>; +- +- /* Has external pullup */ +- bias-disable; +- }; +-}; +- +-&qup_i2c12_default { +- pinconf { +- pins = "gpio49", "gpio50"; +- drive-strength = <2>; +- +- /* Has external pullup */ +- bias-disable; +- }; +-}; +- +-&qup_i2c14_default { +- pinconf { +- pins = "gpio33", "gpio34"; +- drive-strength = <2>; +- +- /* Has external pullup */ +- bias-disable; +- }; +-}; +- +-&qup_spi0_default { +- pinconf { +- pins = "gpio0", "gpio1", "gpio2", "gpio3"; +- drive-strength = <2>; +- bias-disable; +- }; +-}; +- +-&qup_spi5_default { +- pinconf { +- pins = "gpio85", "gpio86", "gpio87", "gpio88"; +- drive-strength = <2>; +- bias-disable; +- }; +-}; +- +-&qup_spi10_default { +- pinconf { +- pins = "gpio53", "gpio54", "gpio55", "gpio56"; +- drive-strength = <2>; +- bias-disable; +- }; +-}; +- +-&qup_uart6_default { +- /* Change pinmux to all 4 pins since CTS and RTS are connected */ +- pinmux { +- pins = "gpio45", "gpio46", +- "gpio47", "gpio48"; +- }; +- +- pinconf-cts { +- /* +- * Configure a pull-down on 45 (CTS) to match the pull of +- * the Bluetooth module. +- */ +- pins = "gpio45"; +- bias-pull-down; +- }; +- +- pinconf-rts-tx { +- /* We'll drive 46 (RTS) and 47 (TX), so no pull */ +- pins = "gpio46", "gpio47"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- pinconf-rx { +- /* +- * Configure a pull-up on 48 (RX). This is needed to avoid +- * garbage data when the TX pin of the Bluetooth module is +- * in tri-state (module powered off or not driving the +- * signal yet). +- */ +- pins = "gpio48"; +- bias-pull-up; +- }; +-}; +- +-&qup_uart9_default { +- pinconf-tx { +- pins = "gpio4"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- pinconf-rx { +- pins = "gpio5"; +- drive-strength = <2>; +- bias-pull-up; +- }; +-}; +- +-/* PINCTRL - board-specific pinctrl */ +-&pm8005_gpio { +- gpio-line-names = "", +- "", +- "SLB", +- ""; +-}; +- +-&pm8998_adc { +- adc-chan@4d { +- reg = ; +- label = "sdm_temp"; +- }; +- +- adc-chan@4e { +- reg = ; +- label = "quiet_temp"; +- }; +- +- adc-chan@4f { +- reg = ; +- label = "lte_temp_1"; +- }; +- +- adc-chan@50 { +- reg = ; +- label = "lte_temp_2"; +- }; +- +- adc-chan@51 { +- reg = ; +- label = "charger_temp"; +- }; +-}; +- +-&pm8998_gpio { +- gpio-line-names = "", +- "", +- "SW_CTRL", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "", +- "CFG_OPT1", +- "WCSS_PWR_REQ", +- "", +- "CFG_OPT2", +- "SLB"; +-}; +- +-&tlmm { +- /* +- * pinctrl settings for pins that have no real owners. +- */ +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&bios_flash_wp_r_l>, +- <&ap_suspend_l_deassert>; +- +- pinctrl-1 = <&bios_flash_wp_r_l>, +- <&ap_suspend_l_assert>; +- +- /* +- * Hogs prevent usermode from changing the value. A GPIO can be both +- * here and in the pinctrl section. +- */ +- ap-suspend-l-hog { +- gpio-hog; +- gpios = <126 GPIO_ACTIVE_LOW>; +- output-low; +- }; +- +- ap_edp_bklten: ap-edp-bklten { +- pinmux { +- pins = "gpio37"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio37"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- bios_flash_wp_r_l: bios-flash-wp-r-l { +- pinmux { +- pins = "gpio128"; +- function = "gpio"; +- input-enable; +- }; +- +- pinconf { +- pins = "gpio128"; +- bias-disable; +- }; +- }; +- +- ec_ap_int_l: ec-ap-int-l { +- pinmux { +- pins = "gpio122"; +- function = "gpio"; +- input-enable; +- }; +- +- pinconf { +- pins = "gpio122"; +- bias-pull-up; +- }; +- }; +- +- edp_brij_en: edp-brij-en { +- pinmux { +- pins = "gpio102"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio102"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- edp_brij_irq: edp-brij-irq { +- pinmux { +- pins = "gpio10"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio10"; +- drive-strength = <2>; +- bias-pull-down; +- }; +- }; +- +- en_pp3300_dx_edp: en-pp3300-dx-edp { +- pinmux { +- pins = "gpio43"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio43"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- h1_ap_int_odl: h1-ap-int-odl { +- pinmux { +- pins = "gpio129"; +- function = "gpio"; +- input-enable; +- }; +- +- pinconf { +- pins = "gpio129"; +- bias-pull-up; +- }; +- }; +- +- pen_eject_odl: pen-eject-odl { +- pinmux { +- pins = "gpio119"; +- function = "gpio"; +- bias-pull-up; +- }; +- }; +- +- pen_irq_l: pen-irq-l { +- pinmux { +- pins = "gpio24"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio24"; +- +- /* Has external pullup */ +- bias-disable; +- }; +- }; +- +- pen_pdct_l: pen-pdct-l { +- pinmux { +- pins = "gpio63"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio63"; +- +- /* Has external pullup */ +- bias-disable; +- }; +- }; +- +- pen_rst_l: pen-rst-l { +- pinmux { +- pins = "gpio23"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio23"; +- bias-disable; +- drive-strength = <2>; +- +- /* +- * The pen driver doesn't currently support +- * driving this reset line. By specifying +- * output-high here we're relying on the fact +- * that this pin has a default pulldown at boot +- * (which makes sure the pen was in reset if it +- * was powered) and then we set it high here to +- * take it out of reset. Better would be if the +- * pen driver could control this and we could +- * remove "output-high" here. +- */ +- output-high; +- }; +- }; +- +- sdc2_clk: sdc2-clk { +- pinconf { +- pins = "sdc2_clk"; +- bias-disable; +- +- /* +- * It seems that mmc_test reports errors if drive +- * strength is not 16. +- */ +- drive-strength = <16>; +- }; +- }; +- +- sdc2_cmd: sdc2-cmd { +- pinconf { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <16>; +- }; +- }; +- +- sdc2_data: sdc2-data { +- pinconf { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <16>; +- }; +- }; +- +- sd_cd_odl: sd-cd-odl { +- pinmux { +- pins = "gpio44"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio44"; +- bias-pull-up; +- }; +- }; +- +- ts_int_l: ts-int-l { +- pinmux { +- pins = "gpio125"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio125"; +- bias-pull-up; +- }; +- }; +- +- ts_reset_l: ts-reset-l { +- pinmux { +- pins = "gpio118"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio118"; +- bias-disable; +- drive-strength = <2>; +- }; +- }; +- +- ap_suspend_l_assert: ap_suspend_l_assert { +- config { +- pins = "gpio126"; +- function = "gpio"; +- bias-no-pull; +- drive-strength = <2>; +- output-low; +- }; +- }; +- +- ap_suspend_l_deassert: ap_suspend_l_deassert { +- config { +- pins = "gpio126"; +- function = "gpio"; +- bias-no-pull; +- drive-strength = <2>; +- output-high; +- }; +- }; +-}; +- +-&venus { +- video-firmware { +- iommus = <&apps_smmu 0x10b2 0x0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-db845c.dts b/scripts/dtc/include-prefixes/arm64/qcom/sdm845-db845c.dts +deleted file mode 100644 +index 2d5533dd4ec2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-db845c.dts ++++ /dev/null +@@ -1,1214 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019, Linaro Ltd. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include +-#include +-#include "sdm845.dtsi" +-#include "pm8998.dtsi" +-#include "pmi8998.dtsi" +- +-/ { +- model = "Thundercomm Dragonboard 845c"; +- compatible = "thundercomm,db845c", "qcom,sdm845"; +- +- aliases { +- serial0 = &uart9; +- hsuart0 = &uart6; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- dc12v: dc12v-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "DC12V"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- autorepeat; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&vol_up_pin_a>; +- +- vol-up { +- label = "Volume Up"; +- linux,code = ; +- gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- user4 { +- label = "green:user4"; +- gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "panic-indicator"; +- default-state = "off"; +- }; +- +- wlan { +- label = "yellow:wlan"; +- gpios = <&pm8998_gpio 9 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "phy0tx"; +- default-state = "off"; +- }; +- +- bt { +- label = "blue:bt"; +- gpios = <&pm8998_gpio 5 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "bluetooth-power"; +- default-state = "off"; +- }; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con: endpoint { +- remote-endpoint = <<9611_out>; +- }; +- }; +- }; +- +- lt9611_1v8: lt9611-vdd18-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "LT9611_1V8"; +- +- vin-supply = <&vdc_5v>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- lt9611_3v3: lt9611-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "LT9611_3V3"; +- +- vin-supply = <&vdc_3v3>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- // TODO: make it possible to drive same GPIO from two clients +- // gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; +- // enable-active-high; +- }; +- +- pcie0_1p05v: pcie-0-1p05v-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "PCIE0_1.05V"; +- +- vin-supply = <&vbat>; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- +- // TODO: make it possible to drive same GPIO from two clients +- // gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>; +- // enable-active-high; +- }; +- +- cam0_dvdd_1v2: reg_cam0_dvdd_1v2 { +- compatible = "regulator-fixed"; +- regulator-name = "CAM0_DVDD_1V2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- enable-active-high; +- gpio = <&pm8998_gpio 12 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cam0_dvdd_1v2_en_default>; +- vin-supply = <&vbat>; +- }; +- +- cam0_avdd_2v8: reg_cam0_avdd_2v8 { +- compatible = "regulator-fixed"; +- regulator-name = "CAM0_AVDD_2V8"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- enable-active-high; +- gpio = <&pm8998_gpio 10 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cam0_avdd_2v8_en_default>; +- vin-supply = <&vbat>; +- }; +- +- /* This regulator is enabled when the VREG_LVS1A_1P8 trace is enabled */ +- cam3_avdd_2v8: reg_cam3_avdd_2v8 { +- compatible = "regulator-fixed"; +- regulator-name = "CAM3_AVDD_2V8"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- vin-supply = <&vbat>; +- }; +- +- pcie0_3p3v_dual: vldo-3v3-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "VLDO_3V3"; +- +- vin-supply = <&vbat>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pwren_state>; +- }; +- +- v5p0_hdmiout: v5p0-hdmiout-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "V5P0_HDMIOUT"; +- +- vin-supply = <&vdc_5v>; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <500000>; +- +- // TODO: make it possible to drive same GPIO from two clients +- // gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; +- // enable-active-high; +- }; +- +- vbat: vbat-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "VBAT"; +- +- vin-supply = <&dc12v>; +- regulator-min-microvolt = <4200000>; +- regulator-max-microvolt = <4200000>; +- regulator-always-on; +- }; +- +- vbat_som: vbat-som-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "VBAT_SOM"; +- +- vin-supply = <&dc12v>; +- regulator-min-microvolt = <4200000>; +- regulator-max-microvolt = <4200000>; +- regulator-always-on; +- }; +- +- vdc_3v3: vdc-3v3-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "VDC_3V3"; +- vin-supply = <&dc12v>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdc_5v: vdc-5v-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "VDC_5V"; +- +- vin-supply = <&dc12v>; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <500000>; +- regulator-always-on; +- }; +- +- vreg_s4a_1p8: vreg-s4a-1p8 { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_s4a_1p8"; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- +- vin-supply = <&vbat_som>; +- }; +-}; +- +-&adsp_pas { +- status = "okay"; +- +- firmware-name = "qcom/sdm845/adsp.mbn"; +-}; +- +-&apps_rsc { +- pm8998-rpmh-regulators { +- compatible = "qcom,pm8998-rpmh-regulators"; +- qcom,pmic-id = "a"; +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- vdd-s9-supply = <&vph_pwr>; +- vdd-s10-supply = <&vph_pwr>; +- vdd-s11-supply = <&vph_pwr>; +- vdd-s12-supply = <&vph_pwr>; +- vdd-s13-supply = <&vph_pwr>; +- vdd-l1-l27-supply = <&vreg_s7a_1p025>; +- vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; +- vdd-l3-l11-supply = <&vreg_s7a_1p025>; +- vdd-l4-l5-supply = <&vreg_s7a_1p025>; +- vdd-l6-supply = <&vph_pwr>; +- vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; +- vdd-l9-supply = <&vreg_bob>; +- vdd-l10-l23-l25-supply = <&vreg_bob>; +- vdd-l13-l19-l21-supply = <&vreg_bob>; +- vdd-l16-l28-supply = <&vreg_bob>; +- vdd-l18-l22-supply = <&vreg_bob>; +- vdd-l20-l24-supply = <&vreg_bob>; +- vdd-l26-supply = <&vreg_s3a_1p35>; +- vin-lvs-1-2-supply = <&vreg_s4a_1p8>; +- +- vreg_s3a_1p35: smps3 { +- regulator-min-microvolt = <1352000>; +- regulator-max-microvolt = <1352000>; +- }; +- +- vreg_s5a_2p04: smps5 { +- regulator-min-microvolt = <1904000>; +- regulator-max-microvolt = <2040000>; +- }; +- +- vreg_s7a_1p025: smps7 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1028000>; +- }; +- +- vreg_l1a_0p875: ldo1 { +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5a_0p8: ldo5 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l12a_1p8: ldo12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7a_1p8: ldo7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l13a_2p95: ldo13 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l17a_1p3: ldo17 { +- regulator-min-microvolt = <1304000>; +- regulator-max-microvolt = <1304000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l20a_2p95: ldo20 { +- regulator-min-microvolt = <2960000>; +- regulator-max-microvolt = <2968000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l21a_2p95: ldo21 { +- regulator-min-microvolt = <2960000>; +- regulator-max-microvolt = <2968000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l24a_3p075: ldo24 { +- regulator-min-microvolt = <3088000>; +- regulator-max-microvolt = <3088000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l25a_3p3: ldo25 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l26a_1p2: ldo26 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_lvs1a_1p8: lvs1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vreg_lvs2a_1p8: lvs2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- }; +- +- pmi8998-rpmh-regulators { +- compatible = "qcom,pmi8998-rpmh-regulators"; +- qcom,pmic-id = "b"; +- +- vdd-bob-supply = <&vph_pwr>; +- +- vreg_bob: bob { +- regulator-min-microvolt = <3312000>; +- regulator-max-microvolt = <3600000>; +- regulator-initial-mode = ; +- regulator-allow-bypass; +- }; +- }; +-}; +- +-&cdsp_pas { +- status = "okay"; +- firmware-name = "qcom/sdm845/cdsp.mbn"; +-}; +- +-&dsi0 { +- status = "okay"; +- vdda-supply = <&vreg_l26a_1p2>; +- +- ports { +- port@1 { +- endpoint { +- remote-endpoint = <<9611_a>; +- data-lanes = <0 1 2 3>; +- }; +- }; +- }; +-}; +- +-&dsi0_phy { +- status = "okay"; +- vdds-supply = <&vreg_l1a_0p875>; +-}; +- +-&gcc { +- protected-clocks = , +- , +- , +- , +- ; +-}; +- +-&gpu { +- zap-shader { +- memory-region = <&gpu_mem>; +- firmware-name = "qcom/sdm845/a630_zap.mbn"; +- }; +-}; +- +-&i2c10 { +- status = "okay"; +- clock-frequency = <400000>; +- +- lt9611_codec: hdmi-bridge@3b { +- compatible = "lontium,lt9611"; +- reg = <0x3b>; +- #sound-dai-cells = <1>; +- +- interrupts-extended = <&tlmm 84 IRQ_TYPE_EDGE_FALLING>; +- +- reset-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>; +- +- vdd-supply = <<9611_1v8>; +- vcc-supply = <<9611_3v3>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <<9611_irq_pin>, <&dsi_sw_sel>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- lt9611_a: endpoint { +- remote-endpoint = <&dsi0_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- +- lt9611_out: endpoint { +- remote-endpoint = <&hdmi_con>; +- }; +- }; +- }; +- }; +-}; +- +-&i2c11 { +- /* On Low speed expansion */ +- label = "LS-I2C1"; +- status = "okay"; +-}; +- +-&i2c14 { +- /* On Low speed expansion */ +- label = "LS-I2C0"; +- status = "okay"; +-}; +- +-&mdss { +- status = "okay"; +-}; +- +-&mdss_mdp { +- status = "okay"; +-}; +- +-&mss_pil { +- status = "okay"; +- firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn"; +-}; +- +-&pcie0 { +- status = "okay"; +- perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>; +- enable-gpio = <&tlmm 134 GPIO_ACTIVE_HIGH>; +- +- vddpe-3v3-supply = <&pcie0_3p3v_dual>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_default_state>; +-}; +- +-&pcie0_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l1a_0p875>; +- vdda-pll-supply = <&vreg_l26a_1p2>; +-}; +- +-&pcie1 { +- status = "okay"; +- perst-gpio = <&tlmm 102 GPIO_ACTIVE_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie1_default_state>; +-}; +- +-&pcie1_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l1a_0p875>; +- vdda-pll-supply = <&vreg_l26a_1p2>; +-}; +- +-&pm8998_gpio { +- gpio-line-names = +- "NC", +- "NC", +- "WLAN_SW_CTRL", +- "NC", +- "PM_GPIO5_BLUE_BT_LED", +- "VOL_UP_N", +- "NC", +- "ADC_IN1", +- "PM_GPIO9_YEL_WIFI_LED", +- "CAM0_AVDD_EN", +- "NC", +- "CAM0_DVDD_EN", +- "PM_GPIO13_GREEN_U4_LED", +- "DIV_CLK2", +- "NC", +- "NC", +- "NC", +- "SMB_STAT", +- "NC", +- "NC", +- "ADC_IN2", +- "OPTION1", +- "WCSS_PWR_REQ", +- "PM845_GPIO24", +- "OPTION2", +- "PM845_SLB"; +- +- cam0_dvdd_1v2_en_default: cam0-dvdd-1v2-en { +- pins = "gpio12"; +- function = "normal"; +- +- bias-pull-up; +- drive-push-pull; +- qcom,drive-strength = ; +- }; +- +- cam0_avdd_2v8_en_default: cam0-avdd-2v8-en { +- pins = "gpio10"; +- function = "normal"; +- +- bias-pull-up; +- drive-push-pull; +- qcom,drive-strength = ; +- }; +- +- vol_up_pin_a: vol-up-active { +- pins = "gpio6"; +- function = "normal"; +- input-enable; +- bias-pull-up; +- qcom,drive-strength = ; +- }; +-}; +- +-&pm8998_pon { +- resin { +- compatible = "qcom,pm8941-resin"; +- interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; +- debounce = <15625>; +- bias-pull-up; +- linux,code = ; +- }; +-}; +- +-/* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */ +-&q6afedai { +- qi2s@22 { +- reg = <22>; +- qcom,sd-lines = <0 1 2 3>; +- }; +-}; +- +-&q6asmdai { +- dai@0 { +- reg = <0>; +- }; +- +- dai@1 { +- reg = <1>; +- }; +- +- dai@2 { +- reg = <2>; +- }; +- +- dai@3 { +- reg = <3>; +- direction = <2>; +- is-compress-dai; +- }; +-}; +- +-&qupv3_id_0 { +- status = "okay"; +-}; +- +-&qupv3_id_1 { +- status = "okay"; +-}; +- +-&sdhc_2 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; +- +- vmmc-supply = <&vreg_l21a_2p95>; +- vqmmc-supply = <&vreg_l13a_2p95>; +- +- bus-width = <4>; +- cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; +-}; +- +-&sound { +- compatible = "qcom,db845c-sndcard"; +- pinctrl-0 = <&quat_mi2s_active +- &quat_mi2s_sd0_active +- &quat_mi2s_sd1_active +- &quat_mi2s_sd2_active +- &quat_mi2s_sd3_active>; +- pinctrl-names = "default"; +- model = "DB845c"; +- audio-routing = +- "RX_BIAS", "MCLK", +- "AMIC1", "MIC BIAS1", +- "AMIC2", "MIC BIAS2", +- "DMIC0", "MIC BIAS1", +- "DMIC1", "MIC BIAS1", +- "DMIC2", "MIC BIAS3", +- "DMIC3", "MIC BIAS3", +- "SpkrLeft IN", "SPK1 OUT", +- "SpkrRight IN", "SPK2 OUT", +- "MM_DL1", "MultiMedia1 Playback", +- "MM_DL2", "MultiMedia2 Playback", +- "MM_DL4", "MultiMedia4 Playback", +- "MultiMedia3 Capture", "MM_UL3"; +- +- mm1-dai-link { +- link-name = "MultiMedia1"; +- cpu { +- sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; +- }; +- }; +- +- mm2-dai-link { +- link-name = "MultiMedia2"; +- cpu { +- sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; +- }; +- }; +- +- mm3-dai-link { +- link-name = "MultiMedia3"; +- cpu { +- sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; +- }; +- }; +- +- mm4-dai-link { +- link-name = "MultiMedia4"; +- cpu { +- sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA4>; +- }; +- }; +- +- hdmi-dai-link { +- link-name = "HDMI Playback"; +- cpu { +- sound-dai = <&q6afedai QUATERNARY_MI2S_RX>; +- }; +- +- platform { +- sound-dai = <&q6routing>; +- }; +- +- codec { +- sound-dai = <<9611_codec 0>; +- }; +- }; +- +- slim-dai-link { +- link-name = "SLIM Playback"; +- cpu { +- sound-dai = <&q6afedai SLIMBUS_0_RX>; +- }; +- +- platform { +- sound-dai = <&q6routing>; +- }; +- +- codec { +- sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; +- }; +- }; +- +- slimcap-dai-link { +- link-name = "SLIM Capture"; +- cpu { +- sound-dai = <&q6afedai SLIMBUS_0_TX>; +- }; +- +- platform { +- sound-dai = <&q6routing>; +- }; +- +- codec { +- sound-dai = <&wcd9340 1>; +- }; +- }; +-}; +- +-&spi2 { +- /* On Low speed expansion */ +- label = "LS-SPI0"; +- status = "okay"; +-}; +- +-&tlmm { +- cam0_default: cam0_default { +- rst { +- pins = "gpio9"; +- function = "gpio"; +- +- drive-strength = <16>; +- bias-disable; +- }; +- +- mclk0 { +- pins = "gpio13"; +- function = "cam_mclk"; +- +- drive-strength = <16>; +- bias-disable; +- }; +- }; +- +- cam3_default: cam3_default { +- rst { +- function = "gpio"; +- pins = "gpio21"; +- +- drive-strength = <16>; +- bias-disable; +- }; +- +- mclk3 { +- function = "cam_mclk"; +- pins = "gpio16"; +- +- drive-strength = <16>; +- bias-disable; +- }; +- }; +- +- dsi_sw_sel: dsi-sw-sel { +- pins = "gpio120"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- output-high; +- }; +- +- lt9611_irq_pin: lt9611-irq { +- pins = "gpio84"; +- function = "gpio"; +- bias-disable; +- }; +- +- pcie0_default_state: pcie0-default { +- clkreq { +- pins = "gpio36"; +- function = "pci_e0"; +- bias-pull-up; +- }; +- +- reset-n { +- pins = "gpio35"; +- function = "gpio"; +- +- drive-strength = <2>; +- output-low; +- bias-pull-down; +- }; +- +- wake-n { +- pins = "gpio37"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-up; +- }; +- }; +- +- pcie0_pwren_state: pcie0-pwren { +- pins = "gpio90"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-disable; +- }; +- +- pcie1_default_state: pcie1-default { +- perst-n { +- pins = "gpio102"; +- function = "gpio"; +- +- drive-strength = <16>; +- bias-disable; +- }; +- +- clkreq { +- pins = "gpio103"; +- function = "pci_e1"; +- bias-pull-up; +- }; +- +- wake-n { +- pins = "gpio11"; +- function = "gpio"; +- +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- reset-n { +- pins = "gpio75"; +- function = "gpio"; +- +- drive-strength = <16>; +- bias-pull-up; +- output-high; +- }; +- }; +- +- sdc2_default_state: sdc2-default { +- clk { +- pins = "sdc2_clk"; +- bias-disable; +- +- /* +- * It seems that mmc_test reports errors if drive +- * strength is not 16 on clk, cmd, and data pins. +- */ +- drive-strength = <16>; +- }; +- +- cmd { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- data { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- }; +- +- sdc2_card_det_n: sd-card-det-n { +- pins = "gpio126"; +- function = "gpio"; +- bias-pull-up; +- }; +- +- wcd_intr_default: wcd_intr_default { +- pins = <54>; +- function = "gpio"; +- +- input-enable; +- bias-pull-down; +- drive-strength = <2>; +- }; +-}; +- +-&uart3 { +- label = "LS-UART0"; +- status = "disabled"; +-}; +- +-&uart6 { +- status = "okay"; +- +- bluetooth { +- compatible = "qcom,wcn3990-bt"; +- +- vddio-supply = <&vreg_s4a_1p8>; +- vddxo-supply = <&vreg_l7a_1p8>; +- vddrf-supply = <&vreg_l17a_1p3>; +- vddch0-supply = <&vreg_l25a_3p3>; +- max-speed = <3200000>; +- }; +-}; +- +-&uart9 { +- label = "LS-UART1"; +- status = "okay"; +-}; +- +-&usb_1 { +- status = "okay"; +-}; +- +-&usb_1_dwc3 { +- dr_mode = "peripheral"; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- +- vdd-supply = <&vreg_l1a_0p875>; +- vdda-pll-supply = <&vreg_l12a_1p8>; +- vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; +- +- qcom,imp-res-offset-value = <8>; +- qcom,hstx-trim-value = ; +- qcom,preemphasis-level = ; +- qcom,preemphasis-width = ; +-}; +- +-&usb_1_qmpphy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l26a_1p2>; +- vdda-pll-supply = <&vreg_l1a_0p875>; +-}; +- +-&usb_2 { +- status = "okay"; +-}; +- +-&usb_2_dwc3 { +- dr_mode = "host"; +-}; +- +-&usb_2_hsphy { +- status = "okay"; +- +- vdd-supply = <&vreg_l1a_0p875>; +- vdda-pll-supply = <&vreg_l12a_1p8>; +- vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; +- +- qcom,imp-res-offset-value = <8>; +- qcom,hstx-trim-value = ; +-}; +- +-&usb_2_qmpphy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l26a_1p2>; +- vdda-pll-supply = <&vreg_l1a_0p875>; +-}; +- +-&ufs_mem_hc { +- status = "okay"; +- +- reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; +- +- vcc-supply = <&vreg_l20a_2p95>; +- vcc-max-microamp = <800000>; +-}; +- +-&ufs_mem_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l1a_0p875>; +- vdda-pll-supply = <&vreg_l26a_1p2>; +-}; +- +-&wcd9340{ +- pinctrl-0 = <&wcd_intr_default>; +- pinctrl-names = "default"; +- clock-names = "extclk"; +- clocks = <&rpmhcc RPMH_LN_BB_CLK2>; +- reset-gpios = <&tlmm 64 0>; +- vdd-buck-supply = <&vreg_s4a_1p8>; +- vdd-buck-sido-supply = <&vreg_s4a_1p8>; +- vdd-tx-supply = <&vreg_s4a_1p8>; +- vdd-rx-supply = <&vreg_s4a_1p8>; +- vdd-io-supply = <&vreg_s4a_1p8>; +- +- swm: swm@c85 { +- left_spkr: wsa8810-left{ +- compatible = "sdw10217201000"; +- reg = <0 1>; +- powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; +- #thermal-sensor-cells = <0>; +- sound-name-prefix = "SpkrLeft"; +- #sound-dai-cells = <0>; +- }; +- +- right_spkr: wsa8810-right{ +- compatible = "sdw10217201000"; +- powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; +- reg = <0 2>; +- #thermal-sensor-cells = <0>; +- sound-name-prefix = "SpkrRight"; +- #sound-dai-cells = <0>; +- }; +- }; +-}; +- +-&wifi { +- status = "okay"; +- +- vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; +- vdd-1.8-xo-supply = <&vreg_l7a_1p8>; +- vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; +- vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; +- +- qcom,snoc-host-cap-8bit-quirk; +-}; +- +-/* PINCTRL - additions to nodes defined in sdm845.dtsi */ +-&qup_spi2_default { +- drive-strength = <16>; +-}; +- +-&qup_uart3_default{ +- pinmux { +- pins = "gpio41", "gpio42", "gpio43", "gpio44"; +- function = "qup3"; +- }; +-}; +- +-&qup_i2c10_default { +- pinconf { +- pins = "gpio55", "gpio56"; +- drive-strength = <2>; +- bias-disable; +- }; +-}; +- +-&qup_uart6_default { +- pinmux { +- pins = "gpio45", "gpio46", "gpio47", "gpio48"; +- function = "qup6"; +- }; +- +- cts { +- pins = "gpio45"; +- bias-disable; +- }; +- +- rts-tx { +- pins = "gpio46", "gpio47"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- rx { +- pins = "gpio48"; +- bias-pull-up; +- }; +-}; +- +-&qup_uart9_default { +- pinconf-tx { +- pins = "gpio4"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- pinconf-rx { +- pins = "gpio5"; +- drive-strength = <2>; +- bias-pull-up; +- }; +-}; +- +-&pm8998_gpio { +- +-}; +- +-&cci { +- status = "okay"; +-}; +- +-&camss { +- vdda-supply = <&vreg_l1a_0p875>; +- +- status = "ok"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- csiphy0_ep: endpoint { +- clock-lanes = <7>; +- data-lanes = <0 1 2 3>; +- remote-endpoint = <&ov8856_ep>; +- }; +- }; +- }; +-}; +- +-&cci_i2c0 { +- camera@10 { +- compatible = "ovti,ov8856"; +- reg = <0x10>; +- +- // CAM0_RST_N +- reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cam0_default>; +- gpios = <&tlmm 13 0>, +- <&tlmm 9 GPIO_ACTIVE_LOW>; +- +- clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; +- clock-names = "xvclk"; +- clock-frequency = <19200000>; +- +- /* The &vreg_s4a_1p8 trace is powered on as a, +- * so it is represented by a fixed regulator. +- * +- * The 2.8V vdda-supply and 1.2V vddd-supply regulators +- * both have to be enabled through the power management +- * gpios. +- */ +- power-domains = <&clock_camcc TITAN_TOP_GDSC>; +- +- dovdd-supply = <&vreg_lvs1a_1p8>; +- avdd-supply = <&cam0_avdd_2v8>; +- dvdd-supply = <&cam0_dvdd_1v2>; +- +- status = "ok"; +- +- port { +- ov8856_ep: endpoint { +- clock-lanes = <1>; +- link-frequencies = /bits/ 64 +- <360000000 180000000>; +- data-lanes = <1 2 3 4>; +- remote-endpoint = <&csiphy0_ep>; +- }; +- }; +- }; +-}; +- +-&cci_i2c1 { +- camera@60 { +- compatible = "ovti,ov7251"; +- +- // I2C address as per ov7251.txt linux documentation +- reg = <0x60>; +- +- // CAM3_RST_N +- enable-gpios = <&tlmm 21 0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cam3_default>; +- gpios = <&tlmm 16 0>, +- <&tlmm 21 0>; +- +- clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; +- clock-names = "xclk"; +- clock-frequency = <24000000>; +- +- /* The &vreg_s4a_1p8 trace always powered on. +- * +- * The 2.8V vdda-supply regulator is enabled when the +- * vreg_s4a_1p8 trace is pulled high. +- * It too is represented by a fixed regulator. +- * +- * No 1.2V vddd-supply regulator is used. +- */ +- power-domains = <&clock_camcc TITAN_TOP_GDSC>; +- +- vdddo-supply = <&vreg_lvs1a_1p8>; +- vdda-supply = <&cam3_avdd_2v8>; +- +- status = "disable"; +- +- port { +- ov7251_ep: endpoint { +- clock-lanes = <1>; +- data-lanes = <0 1>; +-// remote-endpoint = <&csiphy3_ep>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-mtp.dts b/scripts/dtc/include-prefixes/arm64/qcom/sdm845-mtp.dts +deleted file mode 100644 +index 52dd7a858231..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-mtp.dts ++++ /dev/null +@@ -1,644 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * SDM845 MTP board device tree source +- * +- * Copyright (c) 2018, The Linux Foundation. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "sdm845.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. SDM845 MTP"; +- compatible = "qcom,sdm845-mtp", "qcom,sdm845"; +- +- aliases { +- serial0 = &uart9; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- }; +- +- /* +- * Apparently RPMh does not provide support for PM8998 S4 because it +- * is always-on; model it as a fixed regulator. +- */ +- vreg_s4a_1p8: pm8998-smps4 { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_s4a_1p8"; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-always-on; +- regulator-boot-on; +- +- vin-supply = <&vph_pwr>; +- }; +-}; +- +-&adsp_pas { +- status = "okay"; +- firmware-name = "qcom/sdm845/adsp.mdt"; +-}; +- +-&apps_rsc { +- pm8998-rpmh-regulators { +- compatible = "qcom,pm8998-rpmh-regulators"; +- qcom,pmic-id = "a"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- vdd-s9-supply = <&vph_pwr>; +- vdd-s10-supply = <&vph_pwr>; +- vdd-s11-supply = <&vph_pwr>; +- vdd-s12-supply = <&vph_pwr>; +- vdd-s13-supply = <&vph_pwr>; +- vdd-l1-l27-supply = <&vreg_s7a_1p025>; +- vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; +- vdd-l3-l11-supply = <&vreg_s7a_1p025>; +- vdd-l4-l5-supply = <&vreg_s7a_1p025>; +- vdd-l6-supply = <&vph_pwr>; +- vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; +- vdd-l9-supply = <&vreg_bob>; +- vdd-l10-l23-l25-supply = <&vreg_bob>; +- vdd-l13-l19-l21-supply = <&vreg_bob>; +- vdd-l16-l28-supply = <&vreg_bob>; +- vdd-l18-l22-supply = <&vreg_bob>; +- vdd-l20-l24-supply = <&vreg_bob>; +- vdd-l26-supply = <&vreg_s3a_1p35>; +- vin-lvs-1-2-supply = <&vreg_s4a_1p8>; +- +- vreg_s2a_1p125: smps2 { +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- }; +- +- vreg_s3a_1p35: smps3 { +- regulator-min-microvolt = <1352000>; +- regulator-max-microvolt = <1352000>; +- }; +- +- vreg_s5a_2p04: smps5 { +- regulator-min-microvolt = <1904000>; +- regulator-max-microvolt = <2040000>; +- }; +- +- vreg_s7a_1p025: smps7 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1028000>; +- }; +- +- vdd_qusb_hs0: +- vdda_hp_pcie_core: +- vdda_mipi_csi0_0p9: +- vdda_mipi_csi1_0p9: +- vdda_mipi_csi2_0p9: +- vdda_mipi_dsi0_pll: +- vdda_mipi_dsi1_pll: +- vdda_qlink_lv: +- vdda_qlink_lv_ck: +- vdda_qrefs_0p875: +- vdda_pcie_core: +- vdda_pll_cc_ebi01: +- vdda_pll_cc_ebi23: +- vdda_sp_sensor: +- vdda_ufs1_core: +- vdda_ufs2_core: +- vdda_usb1_ss_core: +- vdda_usb2_ss_core: +- vreg_l1a_0p875: ldo1 { +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_10: +- vreg_l2a_1p2: ldo2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- regulator-always-on; +- }; +- +- vreg_l3a_1p0: ldo3 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-initial-mode = ; +- }; +- +- vdd_wcss_cx: +- vdd_wcss_mx: +- vdda_wcss_pll: +- vreg_l5a_0p8: ldo5 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_13: +- vreg_l6a_1p8: ldo6 { +- regulator-min-microvolt = <1856000>; +- regulator-max-microvolt = <1856000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7a_1p8: ldo7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l8a_1p2: ldo8 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1248000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l9a_1p8: ldo9 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10a_1p8: ldo10 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l11a_1p0: ldo11 { +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1048000>; +- regulator-initial-mode = ; +- }; +- +- vdd_qfprom: +- vdd_qfprom_sp: +- vdda_apc1_cs_1p8: +- vdda_gfx_cs_1p8: +- vdda_qrefs_1p8: +- vdda_qusb_hs0_1p8: +- vddpx_11: +- vreg_l12a_1p8: ldo12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_2: +- vreg_l13a_2p95: ldo13 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l14a_1p88: ldo14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l15a_1p8: ldo15 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l16a_2p7: ldo16 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2704000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l17a_1p3: ldo17 { +- regulator-min-microvolt = <1304000>; +- regulator-max-microvolt = <1304000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l18a_2p7: ldo18 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l19a_3p0: ldo19 { +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <3104000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l20a_2p95: ldo20 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l21a_2p95: ldo21 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l22a_2p85: ldo22 { +- regulator-min-microvolt = <2864000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l23a_3p3: ldo23 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- +- vdda_qusb_hs0_3p1: +- vreg_l24a_3p075: ldo24 { +- regulator-min-microvolt = <3088000>; +- regulator-max-microvolt = <3088000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l25a_3p3: ldo25 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- +- vdda_hp_pcie_1p2: +- vdda_hv_ebi0: +- vdda_hv_ebi1: +- vdda_hv_ebi2: +- vdda_hv_ebi3: +- vdda_mipi_csi_1p25: +- vdda_mipi_dsi0_1p2: +- vdda_mipi_dsi1_1p2: +- vdda_pcie_1p2: +- vdda_ufs1_1p2: +- vdda_ufs2_1p2: +- vdda_usb1_ss_1p2: +- vdda_usb2_ss_1p2: +- vreg_l26a_1p2: ldo26 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l28a_3p0: ldo28 { +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- +- vreg_lvs1a_1p8: lvs1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vreg_lvs2a_1p8: lvs2 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- }; +- +- pmi8998-rpmh-regulators { +- compatible = "qcom,pmi8998-rpmh-regulators"; +- qcom,pmic-id = "b"; +- +- vdd-bob-supply = <&vph_pwr>; +- +- vreg_bob: bob { +- regulator-min-microvolt = <3312000>; +- regulator-max-microvolt = <3600000>; +- regulator-initial-mode = ; +- regulator-allow-bypass; +- }; +- }; +- +- pm8005-rpmh-regulators { +- compatible = "qcom,pm8005-rpmh-regulators"; +- qcom,pmic-id = "c"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- +- vreg_s3c_0p6: smps3 { +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <600000>; +- }; +- }; +-}; +- +-&cdsp_pas { +- status = "okay"; +- firmware-name = "qcom/sdm845/cdsp.mdt"; +-}; +- +-&dsi0 { +- status = "okay"; +- vdda-supply = <&vdda_mipi_dsi0_1p2>; +- +- qcom,dual-dsi-mode; +- qcom,master-dsi; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports { +- port@1 { +- endpoint { +- remote-endpoint = <&truly_in_0>; +- data-lanes = <0 1 2 3>; +- }; +- }; +- }; +- +- panel@0 { +- compatible = "truly,nt35597-2K-display"; +- reg = <0>; +- vdda-supply = <&vreg_l14a_1p88>; +- +- reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; +- mode-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- truly_in_0: endpoint { +- remote-endpoint = <&dsi0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- truly_in_1: endpoint { +- remote-endpoint = <&dsi1_out>; +- }; +- }; +- }; +- }; +-}; +- +-&dsi0_phy { +- status = "okay"; +- vdds-supply = <&vdda_mipi_dsi0_pll>; +-}; +- +-&dsi1 { +- status = "okay"; +- vdda-supply = <&vdda_mipi_dsi1_1p2>; +- +- qcom,dual-dsi-mode; +- +- /* DSI1 is slave, so use DSI0 clocks */ +- assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; +- +- ports { +- port@1 { +- endpoint { +- remote-endpoint = <&truly_in_1>; +- data-lanes = <0 1 2 3>; +- }; +- }; +- }; +-}; +- +-&dsi1_phy { +- status = "okay"; +- vdds-supply = <&vdda_mipi_dsi1_pll>; +-}; +- +-&gcc { +- protected-clocks = , +- , +- , +- , +- ; +-}; +- +-&gpu { +- zap-shader { +- memory-region = <&gpu_mem>; +- firmware-name = "qcom/sdm845/a630_zap.mbn"; +- }; +-}; +- +-&i2c10 { +- status = "okay"; +- clock-frequency = <400000>; +-}; +- +-&ipa { +- status = "okay"; +- memory-region = <&ipa_fw_mem>; +-}; +- +-&mdss { +- status = "okay"; +-}; +- +-&mdss_mdp { +- status = "okay"; +-}; +- +-&mss_pil { +- status = "okay"; +- firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn"; +-}; +- +-&qupv3_id_1 { +- status = "okay"; +-}; +- +-&sdhc_2 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_card_det_n>; +- +- vmmc-supply = <&vreg_l21a_2p95>; +- vqmmc-supply = <&vddpx_2>; +- +- cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; +-}; +- +-&uart9 { +- status = "okay"; +-}; +- +-&ufs_mem_hc { +- status = "okay"; +- +- reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; +- +- vcc-supply = <&vreg_l20a_2p95>; +- vcc-max-microamp = <600000>; +-}; +- +-&ufs_mem_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vdda_ufs1_core>; +- vdda-pll-supply = <&vdda_ufs1_1p2>; +-}; +- +-&usb_1 { +- status = "okay"; +-}; +- +-&usb_1_dwc3 { +- /* Until we have Type C hooked up we'll force this as peripheral. */ +- dr_mode = "peripheral"; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- +- vdd-supply = <&vdda_usb1_ss_core>; +- vdda-pll-supply = <&vdda_qusb_hs0_1p8>; +- vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; +- +- qcom,imp-res-offset-value = <8>; +- qcom,hstx-trim-value = ; +- qcom,preemphasis-level = ; +- qcom,preemphasis-width = ; +-}; +- +-&usb_1_qmpphy { +- status = "okay"; +- +- vdda-phy-supply = <&vdda_usb1_ss_1p2>; +- vdda-pll-supply = <&vdda_usb1_ss_core>; +-}; +- +-&usb_2 { +- status = "okay"; +-}; +- +-&usb_2_dwc3 { +- /* +- * Though the USB block on SDM845 can support host, there's no vbus +- * signal for this port on MTP. Thus (unless you have a non-compliant +- * hub that works without vbus) the only sensible thing is to force +- * peripheral mode. +- */ +- dr_mode = "peripheral"; +-}; +- +-&usb_2_hsphy { +- status = "okay"; +- +- vdd-supply = <&vdda_usb2_ss_core>; +- vdda-pll-supply = <&vdda_qusb_hs0_1p8>; +- vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; +- +- qcom,imp-res-offset-value = <8>; +- qcom,hstx-trim-value = ; +-}; +- +-&usb_2_qmpphy { +- status = "okay"; +- +- vdda-phy-supply = <&vdda_usb2_ss_1p2>; +- vdda-pll-supply = <&vdda_usb2_ss_core>; +-}; +- +-&wifi { +- status = "okay"; +- vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; +- vdd-1.8-xo-supply = <&vreg_l7a_1p8>; +- vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; +- vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; +-}; +- +-/* PINCTRL - additions to nodes defined in sdm845.dtsi */ +- +-&qup_i2c10_default { +- pinconf { +- pins = "gpio55", "gpio56"; +- drive-strength = <2>; +- bias-disable; +- }; +-}; +- +-&qup_uart9_default { +- pinconf-tx { +- pins = "gpio4"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- pinconf-rx { +- pins = "gpio5"; +- drive-strength = <2>; +- bias-pull-up; +- }; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <0 4>, <81 4>; +- +- sdc2_clk: sdc2-clk { +- pinconf { +- pins = "sdc2_clk"; +- bias-disable; +- +- /* +- * It seems that mmc_test reports errors if drive +- * strength is not 16 on clk, cmd, and data pins. +- */ +- drive-strength = <16>; +- }; +- }; +- +- sdc2_cmd: sdc2-cmd { +- pinconf { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <16>; +- }; +- }; +- +- sdc2_data: sdc2-data { +- pinconf { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <16>; +- }; +- }; +- +- sd_card_det_n: sd-card-det-n { +- pinmux { +- pins = "gpio126"; +- function = "gpio"; +- }; +- +- pinconf { +- pins = "gpio126"; +- bias-pull-up; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-oneplus-common.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sdm845-oneplus-common.dtsi +deleted file mode 100644 +index d4355522374a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-oneplus-common.dtsi ++++ /dev/null +@@ -1,652 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * SDM845 OnePlus 6(T) (enchilada / fajita) common device tree source +- * +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +- +-#include "sdm845.dtsi" +-#include "pm8998.dtsi" +-#include "pmi8998.dtsi" +- +-/delete-node/ &rmtfs_mem; +- +-/ { +- aliases { +- serial0 = &uart9; +- hsuart0 = &uart6; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- label = "Volume keys"; +- autorepeat; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&volume_down_gpio &volume_up_gpio>; +- +- vol-down { +- label = "Volume down"; +- linux,code = ; +- gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; +- debounce-interval = <15>; +- }; +- +- vol-up { +- label = "Volume up"; +- linux,code = ; +- gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; +- debounce-interval = <15>; +- }; +- }; +- +- reserved-memory { +- /* The rmtfs_mem needs to be guarded due to "XPU limitations" +- * it is otherwise possible for an allocation adjacent to the +- * rmtfs_mem region to trigger an XPU violation, causing a crash. +- */ +- rmtfs_lower_guard: memory@f5b00000 { +- no-map; +- reg = <0 0xf5b00000 0 0x1000>; +- }; +- /* +- * The rmtfs memory region in downstream is 'dynamically allocated' +- * but given the same address every time. Hard code it as this address is +- * where the modem firmware expects it to be. +- */ +- rmtfs_mem: memory@f5b01000 { +- compatible = "qcom,rmtfs-mem"; +- reg = <0 0xf5b01000 0 0x200000>; +- no-map; +- +- qcom,client-id = <1>; +- qcom,vmid = <15>; +- }; +- rmtfs_upper_guard: memory@f5d01000 { +- no-map; +- reg = <0 0xf5d01000 0 0x1000>; +- }; +- +- /* +- * It seems like reserving the old rmtfs_mem region is also needed to prevent +- * random crashes which are most likely modem related, more testing needed. +- */ +- removed_region: memory@88f00000 { +- no-map; +- reg = <0 0x88f00000 0 0x1c00000>; +- }; +- +- ramoops: ramoops@ac300000 { +- compatible = "ramoops"; +- reg = <0 0xac300000 0 0x400000>; +- record-size = <0x40000>; +- console-size = <0x40000>; +- ftrace-size = <0x40000>; +- pmsg-size = <0x200000>; +- devinfo-size = <0x1000>; +- ecc-size = <16>; +- }; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- }; +- +- /* +- * Apparently RPMh does not provide support for PM8998 S4 because it +- * is always-on; model it as a fixed regulator. +- */ +- vreg_s4a_1p8: pm8998-smps4 { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_s4a_1p8"; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-always-on; +- regulator-boot-on; +- +- vin-supply = <&vph_pwr>; +- }; +- +- /* +- * The touchscreen regulator seems to be controlled somehow by a gpio. +- * Model it as a fixed regulator and keep it on. Without schematics we +- * don't know how this is actually wired up... +- */ +- ts_1p8_supply: ts-1p8-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "ts_1p8_supply"; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- gpio = <&tlmm 88 0>; +- enable-active-high; +- regulator-boot-on; +- }; +-}; +- +-&adsp_pas { +- status = "okay"; +- firmware-name = "qcom/sdm845/oneplus6/adsp.mbn"; +-}; +- +-&apps_rsc { +- pm8998-rpmh-regulators { +- compatible = "qcom,pm8998-rpmh-regulators"; +- qcom,pmic-id = "a"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- vdd-s9-supply = <&vph_pwr>; +- vdd-s10-supply = <&vph_pwr>; +- vdd-s11-supply = <&vph_pwr>; +- vdd-s12-supply = <&vph_pwr>; +- vdd-s13-supply = <&vph_pwr>; +- vdd-l1-l27-supply = <&vreg_s7a_1p025>; +- vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; +- vdd-l3-l11-supply = <&vreg_s7a_1p025>; +- vdd-l4-l5-supply = <&vreg_s7a_1p025>; +- vdd-l6-supply = <&vph_pwr>; +- vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; +- vdd-l9-supply = <&vreg_bob>; +- vdd-l10-l23-l25-supply = <&vreg_bob>; +- vdd-l13-l19-l21-supply = <&vreg_bob>; +- vdd-l16-l28-supply = <&vreg_bob>; +- vdd-l18-l22-supply = <&vreg_bob>; +- vdd-l20-l24-supply = <&vreg_bob>; +- vdd-l26-supply = <&vreg_s3a_1p35>; +- vin-lvs-1-2-supply = <&vreg_s4a_1p8>; +- +- vreg_s3a_1p35: smps3 { +- regulator-min-microvolt = <1352000>; +- regulator-max-microvolt = <1352000>; +- }; +- +- vreg_s5a_2p04: smps5 { +- regulator-min-microvolt = <1904000>; +- regulator-max-microvolt = <2040000>; +- }; +- +- vreg_s7a_1p025: smps7 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1028000>; +- }; +- +- vdda_mipi_dsi0_pll: +- vdda_qlink_lv: +- vdda_ufs1_core: +- vdda_usb1_ss_core: +- vreg_l1a_0p875: ldo1 { +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l2a_1p2: ldo2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- regulator-always-on; +- }; +- +- vreg_l5a_0p8: ldo5 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7a_1p8: ldo7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vdda_qusb_hs0_1p8: +- vreg_l12a_1p8: ldo12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l14a_1p88: ldo14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- regulator-always-on; +- }; +- +- vreg_l17a_1p3: ldo17 { +- regulator-min-microvolt = <1304000>; +- regulator-max-microvolt = <1304000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l20a_2p95: ldo20 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vdda_qusb_hs0_3p1: +- vreg_l24a_3p075: ldo24 { +- regulator-min-microvolt = <3088000>; +- regulator-max-microvolt = <3088000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l25a_3p3: ldo25 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- +- vdda_mipi_dsi0_1p2: +- vdda_ufs1_1p2: +- vreg_l26a_1p2: ldo26 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l28a_3p0: ldo28 { +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- }; +- +- pmi8998-rpmh-regulators { +- compatible = "qcom,pmi8998-rpmh-regulators"; +- qcom,pmic-id = "b"; +- +- vdd-bob-supply = <&vph_pwr>; +- +- vreg_bob: bob { +- regulator-min-microvolt = <3312000>; +- regulator-max-microvolt = <3600000>; +- regulator-initial-mode = ; +- regulator-allow-bypass; +- }; +- }; +- +- pm8005-rpmh-regulators { +- compatible = "qcom,pm8005-rpmh-regulators"; +- qcom,pmic-id = "c"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- +- vreg_s3c_0p6: smps3 { +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <600000>; +- }; +- }; +-}; +- +-&cdsp_pas { +- status = "okay"; +- firmware-name = "qcom/sdm845/oneplus6/cdsp.mbn"; +-}; +- +-&dsi0 { +- status = "okay"; +- vdda-supply = <&vdda_mipi_dsi0_1p2>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* +- * Both devices use different panels but all other properties +- * are common. Compatible line is declared in device dts. +- */ +- display_panel: panel@0 { +- status = "disabled"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- vddio-supply = <&vreg_l14a_1p88>; +- +- reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_esd_pin>; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&dsi0_out>; +- }; +- }; +- }; +-}; +- +-&dsi0_out { +- remote-endpoint = <&panel_in>; +- data-lanes = <0 1 2 3>; +-}; +- +-&dsi0_phy { +- status = "okay"; +- vdds-supply = <&vdda_mipi_dsi0_pll>; +-}; +- +-&gcc { +- protected-clocks = , +- , +- , +- , +- ; +-}; +- +-&gpu { +- zap-shader { +- memory-region = <&gpu_mem>; +- firmware-name = "qcom/sdm845/oneplus6/a630_zap.mbn"; +- }; +-}; +- +-&i2c12 { +- status = "okay"; +- clock-frequency = <400000>; +- +- synaptics-rmi4-i2c@20 { +- compatible = "syna,rmi4-i2c"; +- reg = <0x20>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&ts_default_pins>; +- +- vdd-supply = <&vreg_l28a_3p0>; +- vio-supply = <&ts_1p8_supply>; +- +- syna,reset-delay-ms = <200>; +- syna,startup-delay-ms = <200>; +- +- rmi4-f01@1 { +- reg = <0x01>; +- syna,nosleep-mode = <1>; +- }; +- +- rmi4_f12: rmi4-f12@12 { +- reg = <0x12>; +- touchscreen-x-mm = <68>; +- touchscreen-y-mm = <144>; +- syna,sensor-type = <1>; +- syna,rezero-wait-ms = <200>; +- }; +- }; +-}; +- +-&ipa { +- status = "okay"; +- +- memory-region = <&ipa_fw_mem>; +- firmware-name = "qcom/sdm845/oneplus6/ipa_fws.mbn"; +-}; +- +-&mdss { +- status = "okay"; +-}; +- +-&mdss_mdp { +- status = "okay"; +-}; +- +-/* Modem/wifi*/ +-&mss_pil { +- status = "okay"; +- firmware-name = "qcom/sdm845/oneplus6/mba.mbn", "qcom/sdm845/oneplus6/modem.mbn"; +-}; +- +-&pm8998_gpio { +- volume_down_gpio: pm8998_gpio5 { +- pinconf { +- pins = "gpio5"; +- function = "normal"; +- input-enable; +- bias-pull-up; +- qcom,drive-strength = <0>; +- }; +- }; +- +- volume_up_gpio: pm8998_gpio6 { +- pinconf { +- pins = "gpio6"; +- function = "normal"; +- input-enable; +- bias-pull-up; +- qcom,drive-strength = <0>; +- }; +- }; +-}; +- +-&qupv3_id_1 { +- status = "okay"; +-}; +- +-&qupv3_id_0 { +- status = "okay"; +-}; +- +-&qup_i2c12_default { +- mux { +- pins = "gpio49", "gpio50"; +- function = "qup12"; +- drive-strength = <2>; +- bias-disable; +- }; +-}; +- +-&qup_i2c10_default { +- pinconf { +- pins = "gpio55", "gpio56"; +- drive-strength = <2>; +- bias-disable; +- }; +-}; +- +-&qup_uart9_default { +- pinconf-tx { +- pins = "gpio4"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- pinconf-rx { +- pins = "gpio5"; +- drive-strength = <2>; +- bias-pull-up; +- }; +-}; +- +-/* +- * Prevent garbage data on bluetooth UART lines +- */ +-&qup_uart6_default { +- pinmux { +- pins = "gpio45", "gpio46", "gpio47", "gpio48"; +- function = "qup6"; +- }; +- +- cts { +- pins = "gpio45"; +- bias-pull-down; +- }; +- +- rts-tx { +- pins = "gpio46", "gpio47"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- rx { +- pins = "gpio48"; +- bias-pull-up; +- }; +-}; +- +-&uart6 { +- status = "okay"; +- +- bluetooth { +- compatible = "qcom,wcn3990-bt"; +- +- /* +- * This path is relative to the qca/ +- * subdir under lib/firmware. +- */ +- firmware-name = "oneplus6/crnv21.bin"; +- +- vddio-supply = <&vreg_s4a_1p8>; +- vddxo-supply = <&vreg_l7a_1p8>; +- vddrf-supply = <&vreg_l17a_1p3>; +- vddch0-supply = <&vreg_l25a_3p3>; +- max-speed = <3200000>; +- }; +-}; +- +-&uart9 { +- label = "LS-UART1"; +- status = "okay"; +-}; +- +-&ufs_mem_hc { +- status = "okay"; +- +- reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; +- +- vcc-supply = <&vreg_l20a_2p95>; +- vcc-max-microamp = <600000>; +-}; +- +-&ufs_mem_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vdda_ufs1_core>; +- vdda-pll-supply = <&vdda_ufs1_1p2>; +-}; +- +-&usb_1 { +- status = "okay"; +- +- /* +- * disable USB3 clock requirement as the device only supports +- * USB2. +- */ +- qcom,select-utmi-as-pipe-clk; +-}; +- +-&usb_1_dwc3 { +- /* +- * We don't have the capability to switch modes yet. +- */ +- dr_mode = "peripheral"; +- +- /* fastest mode for USB 2 */ +- maximum-speed = "high-speed"; +- +- /* Remove USB3 phy as it's unused on this device. */ +- phys = <&usb_1_hsphy>; +- phy-names = "usb2-phy"; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- +- vdd-supply = <&vdda_usb1_ss_core>; +- vdda-pll-supply = <&vdda_qusb_hs0_1p8>; +- vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; +- +- qcom,imp-res-offset-value = <8>; +- qcom,hstx-trim-value = ; +- qcom,preemphasis-level = ; +- qcom,preemphasis-width = ; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <0 4>, <81 4>; +- +- tri_state_key_default: tri_state_key_default { +- mux { +- pins = "gpio40", "gpio42", "gpio26"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- ts_default_pins: ts-int { +- mux { +- pins = "gpio99", "gpio125"; +- function = "gpio"; +- drive-strength = <16>; +- bias-pull-up; +- }; +- }; +- +- panel_reset_pins: panel-reset { +- mux { +- pins = "gpio6", "gpio25", "gpio26"; +- function = "gpio"; +- drive-strength = <8>; +- bias-disable = <0>; +- }; +- }; +- +- panel_te_pin: panel-te { +- mux { +- pins = "gpio10"; +- function = "mdp_vsync"; +- drive-strength = <2>; +- bias-disable; +- input-enable; +- }; +- }; +- +- panel_esd_pin: panel-esd { +- mux { +- pins = "gpio30"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-down; +- input-enable; +- }; +- }; +-}; +- +-&wifi { +- status = "okay"; +- vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; +- vdd-1.8-xo-supply = <&vreg_l7a_1p8>; +- vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; +- vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; +- +- qcom,snoc-host-cap-8bit-quirk; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-oneplus-enchilada.dts b/scripts/dtc/include-prefixes/arm64/qcom/sdm845-oneplus-enchilada.dts +deleted file mode 100644 +index 72842c887617..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-oneplus-enchilada.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * SDM845 OnePlus 6 (enchilada) device tree. +- * +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-#include "sdm845-oneplus-common.dtsi" +- +-/ { +- model = "OnePlus 6"; +- compatible = "oneplus,enchilada", "qcom,sdm845"; +-}; +- +-&display_panel { +- status = "okay"; +- +- compatible = "samsung,sofef00"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-oneplus-fajita.dts b/scripts/dtc/include-prefixes/arm64/qcom/sdm845-oneplus-fajita.dts +deleted file mode 100644 +index 969b36dc9e2c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-oneplus-fajita.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * SDM845 OnePlus 6T (fajita) device tree. +- * +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-#include "sdm845-oneplus-common.dtsi" +- +-/ { +- model = "OnePlus 6T"; +- compatible = "oneplus,fajita", "qcom,sdm845"; +-}; +- +-&display_panel { +- status = "okay"; +- +- compatible = "samsung,s6e3fc2x01"; +-}; +- +-&rmi4_f12 { +- touchscreen-y-mm = <148>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-xiaomi-beryllium.dts b/scripts/dtc/include-prefixes/arm64/qcom/sdm845-xiaomi-beryllium.dts +deleted file mode 100644 +index c60c8c640e17..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm845-xiaomi-beryllium.dts ++++ /dev/null +@@ -1,565 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include +-#include +-#include "sdm845.dtsi" +-#include "pm8998.dtsi" +-#include "pmi8998.dtsi" +- +-/* +- * Delete following upstream (sdm845.dtsi) reserved +- * memory mappings which are different in this device. +- */ +-/delete-node/ &tz_mem; +-/delete-node/ &adsp_mem; +-/delete-node/ &wlan_msa_mem; +-/delete-node/ &mpss_region; +-/delete-node/ &venus_mem; +-/delete-node/ &cdsp_mem; +-/delete-node/ &mba_region; +-/delete-node/ &slpi_mem; +-/delete-node/ &spss_mem; +-/delete-node/ &rmtfs_mem; +- +-/ { +- model = "Xiaomi Pocophone F1"; +- compatible = "xiaomi,beryllium", "qcom,sdm845"; +- +- /* required for bootloader to select correct board */ +- qcom,board-id = <69 0>; +- qcom,msm-id = <321 0x20001>; +- +- aliases { +- hsuart0 = &uart6; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&vol_up_pin_a>; +- +- vol-up { +- label = "Volume Up"; +- linux,code = ; +- gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- /* Reserved memory changes from downstream */ +- reserved-memory { +- tz_mem: memory@86200000 { +- reg = <0 0x86200000 0 0x4900000>; +- no-map; +- }; +- +- adsp_mem: memory@8c500000 { +- reg = <0 0x8c500000 0 0x1e00000>; +- no-map; +- }; +- +- wlan_msa_mem: memory@8e300000 { +- reg = <0 0x8e300000 0 0x100000>; +- no-map; +- }; +- +- mpss_region: memory@8e400000 { +- reg = <0 0x8e400000 0 0x7800000>; +- no-map; +- }; +- +- venus_mem: memory@95c00000 { +- reg = <0 0x95c00000 0 0x500000>; +- no-map; +- }; +- +- cdsp_mem: memory@96100000 { +- reg = <0 0x96100000 0 0x800000>; +- no-map; +- }; +- +- mba_region: memory@96900000 { +- reg = <0 0x96900000 0 0x200000>; +- no-map; +- }; +- +- slpi_mem: memory@96b00000 { +- reg = <0 0x96b00000 0 0x1400000>; +- no-map; +- }; +- +- spss_mem: memory@97f00000 { +- reg = <0 0x97f00000 0 0x100000>; +- no-map; +- }; +- +- rmtfs_mem: memory@f6301000 { +- compatible = "qcom,rmtfs-mem"; +- reg = <0 0xf6301000 0 0x200000>; +- no-map; +- +- qcom,client-id = <1>; +- qcom,vmid = <15>; +- }; +- }; +- +- vreg_s4a_1p8: vreg-s4a-1p8 { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_s4a_1p8"; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +-}; +- +-&adsp_pas { +- status = "okay"; +- firmware-name = "qcom/sdm845/adsp.mdt"; +-}; +- +-&apps_rsc { +- pm8998-rpmh-regulators { +- compatible = "qcom,pm8998-rpmh-regulators"; +- qcom,pmic-id = "a"; +- +- vreg_l1a_0p875: ldo1 { +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5a_0p8: ldo5 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7a_1p8: ldo7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l12a_1p8: ldo12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l13a_2p95: ldo13 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l14a_1p8: ldo14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vreg_l17a_1p3: ldo17 { +- regulator-min-microvolt = <1304000>; +- regulator-max-microvolt = <1304000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l20a_2p95: ldo20 { +- regulator-min-microvolt = <2960000>; +- regulator-max-microvolt = <2968000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l21a_2p95: ldo21 { +- regulator-min-microvolt = <2960000>; +- regulator-max-microvolt = <2968000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l24a_3p075: ldo24 { +- regulator-min-microvolt = <3088000>; +- regulator-max-microvolt = <3088000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l25a_3p3: ldo25 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l26a_1p2: ldo26 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- regulator-boot-on; +- }; +- }; +-}; +- +-&cdsp_pas { +- status = "okay"; +- firmware-name = "qcom/sdm845/cdsp.mdt"; +-}; +- +-&dsi0 { +- status = "okay"; +- vdda-supply = <&vreg_l26a_1p2>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- panel@0 { +- compatible = "tianma,fhd-video"; +- reg = <0>; +- vddi0-supply = <&vreg_l14a_1p8>; +- vddpos-supply = <&lab>; +- vddneg-supply = <&ibb>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; +- +- port { +- tianma_nt36672a_in_0: endpoint { +- remote-endpoint = <&dsi0_out>; +- }; +- }; +- }; +-}; +- +-&dsi0_out { +- remote-endpoint = <&tianma_nt36672a_in_0>; +- data-lanes = <0 1 2 3>; +-}; +- +-&dsi0_phy { +- status = "okay"; +- vdds-supply = <&vreg_l1a_0p875>; +-}; +- +-&gcc { +- protected-clocks = , +- , +- , +- , +- ; +-}; +- +-&gpu { +- zap-shader { +- memory-region = <&gpu_mem>; +- firmware-name = "qcom/sdm845/a630_zap.mbn"; +- }; +-}; +- +-&ibb { +- regulator-min-microvolt = <4600000>; +- regulator-max-microvolt = <6000000>; +- regulator-over-current-protection; +- regulator-pull-down; +- regulator-soft-start; +- qcom,discharge-resistor-kohms = <300>; +-}; +- +-&lab { +- regulator-min-microvolt = <4600000>; +- regulator-max-microvolt = <6000000>; +- regulator-over-current-protection; +- regulator-pull-down; +- regulator-soft-start; +-}; +- +-&mdss { +- status = "okay"; +-}; +- +-&mdss_mdp { +- status = "okay"; +-}; +- +-&mss_pil { +- status = "okay"; +- firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mdt"; +-}; +- +-&pm8998_gpio { +- vol_up_pin_a: vol-up-active { +- pins = "gpio6"; +- function = "normal"; +- input-enable; +- bias-pull-up; +- qcom,drive-strength = ; +- }; +-}; +- +-&pm8998_pon { +- resin { +- compatible = "qcom,pm8941-resin"; +- interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; +- debounce = <15625>; +- bias-pull-up; +- linux,code = ; +- }; +-}; +- +-/* QUAT I2S Uses 1 I2S SD Line for audio on TAS2559/60 amplifiers */ +-&q6afedai { +- qi2s@22 { +- reg = <22>; +- qcom,sd-lines = <0>; +- }; +-}; +- +-&q6asmdai { +- dai@0 { +- reg = <0>; +- }; +- +- dai@1 { +- reg = <1>; +- }; +- +- dai@2 { +- reg = <2>; +- }; +-}; +- +-&qupv3_id_0 { +- status = "okay"; +-}; +- +-&sdhc_2 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; +- +- vmmc-supply = <&vreg_l21a_2p95>; +- vqmmc-supply = <&vreg_l13a_2p95>; +- +- bus-width = <4>; +- cd-gpios = <&tlmm 126 GPIO_ACTIVE_HIGH>; +-}; +- +-&sound { +- compatible = "qcom,db845c-sndcard"; +- pinctrl-0 = <&quat_mi2s_active +- &quat_mi2s_sd0_active>; +- pinctrl-names = "default"; +- model = "Xiaomi Poco F1"; +- audio-routing = +- "RX_BIAS", "MCLK", +- "AMIC1", "MIC BIAS1", +- "AMIC2", "MIC BIAS2", +- "AMIC3", "MIC BIAS3"; +- +- mm1-dai-link { +- link-name = "MultiMedia1"; +- cpu { +- sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; +- }; +- }; +- +- mm2-dai-link { +- link-name = "MultiMedia2"; +- cpu { +- sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; +- }; +- }; +- +- mm3-dai-link { +- link-name = "MultiMedia3"; +- cpu { +- sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; +- }; +- }; +- +- slim-dai-link { +- link-name = "SLIM Playback"; +- cpu { +- sound-dai = <&q6afedai SLIMBUS_0_RX>; +- }; +- +- platform { +- sound-dai = <&q6routing>; +- }; +- +- codec { +- sound-dai = <&wcd9340 0>; +- }; +- }; +- +- slimcap-dai-link { +- link-name = "SLIM Capture"; +- cpu { +- sound-dai = <&q6afedai SLIMBUS_0_TX>; +- }; +- +- platform { +- sound-dai = <&q6routing>; +- }; +- +- codec { +- sound-dai = <&wcd9340 1>; +- }; +- }; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <0 4>, <81 4>; +- +- sdc2_default_state: sdc2-default { +- clk { +- pins = "sdc2_clk"; +- bias-disable; +- drive-strength = <16>; +- }; +- +- cmd { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- data { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- }; +- +- sdc2_card_det_n: sd-card-det-n { +- pins = "gpio126"; +- function = "gpio"; +- bias-pull-up; +- }; +- +- wcd_intr_default: wcd_intr_default { +- pins = <54>; +- function = "gpio"; +- +- input-enable; +- bias-pull-down; +- drive-strength = <2>; +- }; +-}; +- +-&uart6 { +- status = "okay"; +- +- bluetooth { +- compatible = "qcom,wcn3990-bt"; +- +- vddio-supply = <&vreg_s4a_1p8>; +- vddxo-supply = <&vreg_l7a_1p8>; +- vddrf-supply = <&vreg_l17a_1p3>; +- vddch0-supply = <&vreg_l25a_3p3>; +- max-speed = <3200000>; +- }; +-}; +- +-&ufs_mem_hc { +- status = "okay"; +- +- reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; +- +- vcc-supply = <&vreg_l20a_2p95>; +- vcc-max-microamp = <800000>; +-}; +- +-&ufs_mem_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l1a_0p875>; +- vdda-pll-supply = <&vreg_l26a_1p2>; +-}; +- +-&usb_1 { +- status = "okay"; +-}; +- +-&usb_1_dwc3 { +- dr_mode = "peripheral"; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- +- vdd-supply = <&vreg_l1a_0p875>; +- vdda-pll-supply = <&vreg_l12a_1p8>; +- vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; +- +- qcom,imp-res-offset-value = <8>; +- qcom,hstx-trim-value = ; +- qcom,preemphasis-level = ; +- qcom,preemphasis-width = ; +-}; +- +-&usb_1_qmpphy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l26a_1p2>; +- vdda-pll-supply = <&vreg_l1a_0p875>; +-}; +- +-&wcd9340{ +- pinctrl-0 = <&wcd_intr_default>; +- pinctrl-names = "default"; +- clock-names = "extclk"; +- clocks = <&rpmhcc RPMH_LN_BB_CLK2>; +- reset-gpios = <&tlmm 64 0>; +- vdd-buck-supply = <&vreg_s4a_1p8>; +- vdd-buck-sido-supply = <&vreg_s4a_1p8>; +- vdd-tx-supply = <&vreg_s4a_1p8>; +- vdd-rx-supply = <&vreg_s4a_1p8>; +- vdd-io-supply = <&vreg_s4a_1p8>; +- qcom,micbias1-microvolt = <2700000>; +- qcom,micbias2-microvolt = <1800000>; +- qcom,micbias3-microvolt = <2700000>; +- qcom,micbias4-microvolt = <2700000>; +-}; +- +-&wifi { +- status = "okay"; +- +- vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; +- vdd-1.8-xo-supply = <&vreg_l7a_1p8>; +- vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; +- vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; +-}; +- +-/* PINCTRL - additions to nodes defined in sdm845.dtsi */ +- +-&qup_uart6_default { +- pinmux { +- pins = "gpio45", "gpio46", "gpio47", "gpio48"; +- function = "qup6"; +- }; +- +- cts { +- pins = "gpio45"; +- bias-disable; +- }; +- +- rts-tx { +- pins = "gpio46", "gpio47"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- rx { +- pins = "gpio48"; +- bias-pull-up; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm845.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sdm845.dtsi +deleted file mode 100644 +index 519ca9a705b4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm845.dtsi ++++ /dev/null +@@ -1,5509 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * SDM845 SoC device tree source +- * +- * Copyright (c) 2018, The Linux Foundation. All rights reserved. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&intc>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c7; +- i2c8 = &i2c8; +- i2c9 = &i2c9; +- i2c10 = &i2c10; +- i2c11 = &i2c11; +- i2c12 = &i2c12; +- i2c13 = &i2c13; +- i2c14 = &i2c14; +- i2c15 = &i2c15; +- spi0 = &spi0; +- spi1 = &spi1; +- spi2 = &spi2; +- spi3 = &spi3; +- spi4 = &spi4; +- spi5 = &spi5; +- spi6 = &spi6; +- spi7 = &spi7; +- spi8 = &spi8; +- spi9 = &spi9; +- spi10 = &spi10; +- spi11 = &spi11; +- spi12 = &spi12; +- spi13 = &spi13; +- spi14 = &spi14; +- spi15 = &spi15; +- }; +- +- chosen { }; +- +- memory@80000000 { +- device_type = "memory"; +- /* We expect the bootloader to fill in the size */ +- reg = <0 0x80000000 0 0>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- hyp_mem: memory@85700000 { +- reg = <0 0x85700000 0 0x600000>; +- no-map; +- }; +- +- xbl_mem: memory@85e00000 { +- reg = <0 0x85e00000 0 0x100000>; +- no-map; +- }; +- +- aop_mem: memory@85fc0000 { +- reg = <0 0x85fc0000 0 0x20000>; +- no-map; +- }; +- +- aop_cmd_db_mem: memory@85fe0000 { +- compatible = "qcom,cmd-db"; +- reg = <0x0 0x85fe0000 0 0x20000>; +- no-map; +- }; +- +- smem_mem: memory@86000000 { +- reg = <0x0 0x86000000 0 0x200000>; +- no-map; +- }; +- +- tz_mem: memory@86200000 { +- reg = <0 0x86200000 0 0x2d00000>; +- no-map; +- }; +- +- rmtfs_mem: memory@88f00000 { +- compatible = "qcom,rmtfs-mem"; +- reg = <0 0x88f00000 0 0x200000>; +- no-map; +- +- qcom,client-id = <1>; +- qcom,vmid = <15>; +- }; +- +- qseecom_mem: memory@8ab00000 { +- reg = <0 0x8ab00000 0 0x1400000>; +- no-map; +- }; +- +- camera_mem: memory@8bf00000 { +- reg = <0 0x8bf00000 0 0x500000>; +- no-map; +- }; +- +- ipa_fw_mem: memory@8c400000 { +- reg = <0 0x8c400000 0 0x10000>; +- no-map; +- }; +- +- ipa_gsi_mem: memory@8c410000 { +- reg = <0 0x8c410000 0 0x5000>; +- no-map; +- }; +- +- gpu_mem: memory@8c415000 { +- reg = <0 0x8c415000 0 0x2000>; +- no-map; +- }; +- +- adsp_mem: memory@8c500000 { +- reg = <0 0x8c500000 0 0x1a00000>; +- no-map; +- }; +- +- wlan_msa_mem: memory@8df00000 { +- reg = <0 0x8df00000 0 0x100000>; +- no-map; +- }; +- +- mpss_region: memory@8e000000 { +- reg = <0 0x8e000000 0 0x7800000>; +- no-map; +- }; +- +- venus_mem: memory@95800000 { +- reg = <0 0x95800000 0 0x500000>; +- no-map; +- }; +- +- cdsp_mem: memory@95d00000 { +- reg = <0 0x95d00000 0 0x800000>; +- no-map; +- }; +- +- mba_region: memory@96500000 { +- reg = <0 0x96500000 0 0x200000>; +- no-map; +- }; +- +- slpi_mem: memory@96700000 { +- reg = <0 0x96700000 0 0x1400000>; +- no-map; +- }; +- +- spss_mem: memory@97b00000 { +- reg = <0 0x97b00000 0 0x100000>; +- no-map; +- }; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- CPU0: cpu@0 { +- device_type = "cpu"; +- compatible = "qcom,kryo385"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- cpu-idle-states = <&LITTLE_CPU_SLEEP_0 +- &LITTLE_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <607>; +- dynamic-power-coefficient = <100>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- operating-points-v2 = <&cpu0_opp_table>; +- interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_0>; +- L2_0: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- L3_0: l3-cache { +- compatible = "cache"; +- }; +- }; +- }; +- +- CPU1: cpu@100 { +- device_type = "cpu"; +- compatible = "qcom,kryo385"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- cpu-idle-states = <&LITTLE_CPU_SLEEP_0 +- &LITTLE_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <607>; +- dynamic-power-coefficient = <100>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- operating-points-v2 = <&cpu0_opp_table>; +- interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_100>; +- L2_100: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU2: cpu@200 { +- device_type = "cpu"; +- compatible = "qcom,kryo385"; +- reg = <0x0 0x200>; +- enable-method = "psci"; +- cpu-idle-states = <&LITTLE_CPU_SLEEP_0 +- &LITTLE_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <607>; +- dynamic-power-coefficient = <100>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- operating-points-v2 = <&cpu0_opp_table>; +- interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_200>; +- L2_200: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU3: cpu@300 { +- device_type = "cpu"; +- compatible = "qcom,kryo385"; +- reg = <0x0 0x300>; +- enable-method = "psci"; +- cpu-idle-states = <&LITTLE_CPU_SLEEP_0 +- &LITTLE_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- capacity-dmips-mhz = <607>; +- dynamic-power-coefficient = <100>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- operating-points-v2 = <&cpu0_opp_table>; +- interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_300>; +- L2_300: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU4: cpu@400 { +- device_type = "cpu"; +- compatible = "qcom,kryo385"; +- reg = <0x0 0x400>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- cpu-idle-states = <&BIG_CPU_SLEEP_0 +- &BIG_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- dynamic-power-coefficient = <396>; +- qcom,freq-domain = <&cpufreq_hw 1>; +- operating-points-v2 = <&cpu4_opp_table>; +- interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_400>; +- L2_400: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU5: cpu@500 { +- device_type = "cpu"; +- compatible = "qcom,kryo385"; +- reg = <0x0 0x500>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- cpu-idle-states = <&BIG_CPU_SLEEP_0 +- &BIG_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- dynamic-power-coefficient = <396>; +- qcom,freq-domain = <&cpufreq_hw 1>; +- operating-points-v2 = <&cpu4_opp_table>; +- interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_500>; +- L2_500: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU6: cpu@600 { +- device_type = "cpu"; +- compatible = "qcom,kryo385"; +- reg = <0x0 0x600>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- cpu-idle-states = <&BIG_CPU_SLEEP_0 +- &BIG_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- dynamic-power-coefficient = <396>; +- qcom,freq-domain = <&cpufreq_hw 1>; +- operating-points-v2 = <&cpu4_opp_table>; +- interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_600>; +- L2_600: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU7: cpu@700 { +- device_type = "cpu"; +- compatible = "qcom,kryo385"; +- reg = <0x0 0x700>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- cpu-idle-states = <&BIG_CPU_SLEEP_0 +- &BIG_CPU_SLEEP_1 +- &CLUSTER_SLEEP_0>; +- dynamic-power-coefficient = <396>; +- qcom,freq-domain = <&cpufreq_hw 1>; +- operating-points-v2 = <&cpu4_opp_table>; +- interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- #cooling-cells = <2>; +- next-level-cache = <&L2_700>; +- L2_700: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&CPU0>; +- }; +- +- core1 { +- cpu = <&CPU1>; +- }; +- +- core2 { +- cpu = <&CPU2>; +- }; +- +- core3 { +- cpu = <&CPU3>; +- }; +- +- core4 { +- cpu = <&CPU4>; +- }; +- +- core5 { +- cpu = <&CPU5>; +- }; +- +- core6 { +- cpu = <&CPU6>; +- }; +- +- core7 { +- cpu = <&CPU7>; +- }; +- }; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "little-power-down"; +- arm,psci-suspend-param = <0x40000003>; +- entry-latency-us = <350>; +- exit-latency-us = <461>; +- min-residency-us = <1890>; +- local-timer-stop; +- }; +- +- LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { +- compatible = "arm,idle-state"; +- idle-state-name = "little-rail-power-down"; +- arm,psci-suspend-param = <0x40000004>; +- entry-latency-us = <360>; +- exit-latency-us = <531>; +- min-residency-us = <3934>; +- local-timer-stop; +- }; +- +- BIG_CPU_SLEEP_0: cpu-sleep-1-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "big-power-down"; +- arm,psci-suspend-param = <0x40000003>; +- entry-latency-us = <264>; +- exit-latency-us = <621>; +- min-residency-us = <952>; +- local-timer-stop; +- }; +- +- BIG_CPU_SLEEP_1: cpu-sleep-1-1 { +- compatible = "arm,idle-state"; +- idle-state-name = "big-rail-power-down"; +- arm,psci-suspend-param = <0x40000004>; +- entry-latency-us = <702>; +- exit-latency-us = <1061>; +- min-residency-us = <4488>; +- local-timer-stop; +- }; +- +- CLUSTER_SLEEP_0: cluster-sleep-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "cluster-power-down"; +- arm,psci-suspend-param = <0x400000F4>; +- entry-latency-us = <3263>; +- exit-latency-us = <6562>; +- min-residency-us = <9987>; +- local-timer-stop; +- }; +- }; +- }; +- +- cpu0_opp_table: cpu0_opp_table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- cpu0_opp1: opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-peak-kBps = <800000 4800000>; +- }; +- +- cpu0_opp2: opp-403200000 { +- opp-hz = /bits/ 64 <403200000>; +- opp-peak-kBps = <800000 4800000>; +- }; +- +- cpu0_opp3: opp-480000000 { +- opp-hz = /bits/ 64 <480000000>; +- opp-peak-kBps = <800000 6451200>; +- }; +- +- cpu0_opp4: opp-576000000 { +- opp-hz = /bits/ 64 <576000000>; +- opp-peak-kBps = <800000 6451200>; +- }; +- +- cpu0_opp5: opp-652800000 { +- opp-hz = /bits/ 64 <652800000>; +- opp-peak-kBps = <800000 7680000>; +- }; +- +- cpu0_opp6: opp-748800000 { +- opp-hz = /bits/ 64 <748800000>; +- opp-peak-kBps = <1804000 9216000>; +- }; +- +- cpu0_opp7: opp-825600000 { +- opp-hz = /bits/ 64 <825600000>; +- opp-peak-kBps = <1804000 9216000>; +- }; +- +- cpu0_opp8: opp-902400000 { +- opp-hz = /bits/ 64 <902400000>; +- opp-peak-kBps = <1804000 10444800>; +- }; +- +- cpu0_opp9: opp-979200000 { +- opp-hz = /bits/ 64 <979200000>; +- opp-peak-kBps = <1804000 11980800>; +- }; +- +- cpu0_opp10: opp-1056000000 { +- opp-hz = /bits/ 64 <1056000000>; +- opp-peak-kBps = <1804000 11980800>; +- }; +- +- cpu0_opp11: opp-1132800000 { +- opp-hz = /bits/ 64 <1132800000>; +- opp-peak-kBps = <2188000 13516800>; +- }; +- +- cpu0_opp12: opp-1228800000 { +- opp-hz = /bits/ 64 <1228800000>; +- opp-peak-kBps = <2188000 15052800>; +- }; +- +- cpu0_opp13: opp-1324800000 { +- opp-hz = /bits/ 64 <1324800000>; +- opp-peak-kBps = <2188000 16588800>; +- }; +- +- cpu0_opp14: opp-1420800000 { +- opp-hz = /bits/ 64 <1420800000>; +- opp-peak-kBps = <3072000 18124800>; +- }; +- +- cpu0_opp15: opp-1516800000 { +- opp-hz = /bits/ 64 <1516800000>; +- opp-peak-kBps = <3072000 19353600>; +- }; +- +- cpu0_opp16: opp-1612800000 { +- opp-hz = /bits/ 64 <1612800000>; +- opp-peak-kBps = <4068000 19353600>; +- }; +- +- cpu0_opp17: opp-1689600000 { +- opp-hz = /bits/ 64 <1689600000>; +- opp-peak-kBps = <4068000 20889600>; +- }; +- +- cpu0_opp18: opp-1766400000 { +- opp-hz = /bits/ 64 <1766400000>; +- opp-peak-kBps = <4068000 22425600>; +- }; +- }; +- +- cpu4_opp_table: cpu4_opp_table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- cpu4_opp1: opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-peak-kBps = <800000 4800000>; +- }; +- +- cpu4_opp2: opp-403200000 { +- opp-hz = /bits/ 64 <403200000>; +- opp-peak-kBps = <800000 4800000>; +- }; +- +- cpu4_opp3: opp-480000000 { +- opp-hz = /bits/ 64 <480000000>; +- opp-peak-kBps = <1804000 4800000>; +- }; +- +- cpu4_opp4: opp-576000000 { +- opp-hz = /bits/ 64 <576000000>; +- opp-peak-kBps = <1804000 4800000>; +- }; +- +- cpu4_opp5: opp-652800000 { +- opp-hz = /bits/ 64 <652800000>; +- opp-peak-kBps = <1804000 4800000>; +- }; +- +- cpu4_opp6: opp-748800000 { +- opp-hz = /bits/ 64 <748800000>; +- opp-peak-kBps = <1804000 4800000>; +- }; +- +- cpu4_opp7: opp-825600000 { +- opp-hz = /bits/ 64 <825600000>; +- opp-peak-kBps = <2188000 9216000>; +- }; +- +- cpu4_opp8: opp-902400000 { +- opp-hz = /bits/ 64 <902400000>; +- opp-peak-kBps = <2188000 9216000>; +- }; +- +- cpu4_opp9: opp-979200000 { +- opp-hz = /bits/ 64 <979200000>; +- opp-peak-kBps = <2188000 9216000>; +- }; +- +- cpu4_opp10: opp-1056000000 { +- opp-hz = /bits/ 64 <1056000000>; +- opp-peak-kBps = <3072000 9216000>; +- }; +- +- cpu4_opp11: opp-1132800000 { +- opp-hz = /bits/ 64 <1132800000>; +- opp-peak-kBps = <3072000 11980800>; +- }; +- +- cpu4_opp12: opp-1209600000 { +- opp-hz = /bits/ 64 <1209600000>; +- opp-peak-kBps = <4068000 11980800>; +- }; +- +- cpu4_opp13: opp-1286400000 { +- opp-hz = /bits/ 64 <1286400000>; +- opp-peak-kBps = <4068000 11980800>; +- }; +- +- cpu4_opp14: opp-1363200000 { +- opp-hz = /bits/ 64 <1363200000>; +- opp-peak-kBps = <4068000 15052800>; +- }; +- +- cpu4_opp15: opp-1459200000 { +- opp-hz = /bits/ 64 <1459200000>; +- opp-peak-kBps = <4068000 15052800>; +- }; +- +- cpu4_opp16: opp-1536000000 { +- opp-hz = /bits/ 64 <1536000000>; +- opp-peak-kBps = <5412000 15052800>; +- }; +- +- cpu4_opp17: opp-1612800000 { +- opp-hz = /bits/ 64 <1612800000>; +- opp-peak-kBps = <5412000 15052800>; +- }; +- +- cpu4_opp18: opp-1689600000 { +- opp-hz = /bits/ 64 <1689600000>; +- opp-peak-kBps = <5412000 19353600>; +- }; +- +- cpu4_opp19: opp-1766400000 { +- opp-hz = /bits/ 64 <1766400000>; +- opp-peak-kBps = <6220000 19353600>; +- }; +- +- cpu4_opp20: opp-1843200000 { +- opp-hz = /bits/ 64 <1843200000>; +- opp-peak-kBps = <6220000 19353600>; +- }; +- +- cpu4_opp21: opp-1920000000 { +- opp-hz = /bits/ 64 <1920000000>; +- opp-peak-kBps = <7216000 19353600>; +- }; +- +- cpu4_opp22: opp-1996800000 { +- opp-hz = /bits/ 64 <1996800000>; +- opp-peak-kBps = <7216000 20889600>; +- }; +- +- cpu4_opp23: opp-2092800000 { +- opp-hz = /bits/ 64 <2092800000>; +- opp-peak-kBps = <7216000 20889600>; +- }; +- +- cpu4_opp24: opp-2169600000 { +- opp-hz = /bits/ 64 <2169600000>; +- opp-peak-kBps = <7216000 20889600>; +- }; +- +- cpu4_opp25: opp-2246400000 { +- opp-hz = /bits/ 64 <2246400000>; +- opp-peak-kBps = <7216000 20889600>; +- }; +- +- cpu4_opp26: opp-2323200000 { +- opp-hz = /bits/ 64 <2323200000>; +- opp-peak-kBps = <7216000 20889600>; +- }; +- +- cpu4_opp27: opp-2400000000 { +- opp-hz = /bits/ 64 <2400000000>; +- opp-peak-kBps = <7216000 22425600>; +- }; +- +- cpu4_opp28: opp-2476800000 { +- opp-hz = /bits/ 64 <2476800000>; +- opp-peak-kBps = <7216000 22425600>; +- }; +- +- cpu4_opp29: opp-2553600000 { +- opp-hz = /bits/ 64 <2553600000>; +- opp-peak-kBps = <7216000 22425600>; +- }; +- +- cpu4_opp30: opp-2649600000 { +- opp-hz = /bits/ 64 <2649600000>; +- opp-peak-kBps = <7216000 22425600>; +- }; +- +- cpu4_opp31: opp-2745600000 { +- opp-hz = /bits/ 64 <2745600000>; +- opp-peak-kBps = <7216000 25497600>; +- }; +- +- cpu4_opp32: opp-2803200000 { +- opp-hz = /bits/ 64 <2803200000>; +- opp-peak-kBps = <7216000 25497600>; +- }; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = ; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- clocks { +- xo_board: xo-board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <38400000>; +- clock-output-names = "xo_board"; +- }; +- +- sleep_clk: sleep-clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32764>; +- }; +- }; +- +- firmware { +- scm { +- compatible = "qcom,scm-sdm845", "qcom,scm"; +- }; +- }; +- +- adsp_pas: remoteproc-adsp { +- compatible = "qcom,sdm845-adsp-pas"; +- +- interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack"; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "xo"; +- +- memory-region = <&adsp_mem>; +- +- qcom,smem-states = <&adsp_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- status = "disabled"; +- +- glink-edge { +- interrupts = ; +- label = "lpass"; +- qcom,remote-pid = <2>; +- mboxes = <&apss_shared 8>; +- +- apr { +- compatible = "qcom,apr-v2"; +- qcom,glink-channels = "apr_audio_svc"; +- qcom,apr-domain = ; +- #address-cells = <1>; +- #size-cells = <0>; +- qcom,intents = <512 20>; +- +- apr-service@3 { +- reg = ; +- compatible = "qcom,q6core"; +- qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; +- }; +- +- q6afe: apr-service@4 { +- compatible = "qcom,q6afe"; +- reg = ; +- qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; +- q6afedai: dais { +- compatible = "qcom,q6afe-dais"; +- #address-cells = <1>; +- #size-cells = <0>; +- #sound-dai-cells = <1>; +- }; +- }; +- +- q6asm: apr-service@7 { +- compatible = "qcom,q6asm"; +- reg = ; +- qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; +- q6asmdai: dais { +- compatible = "qcom,q6asm-dais"; +- #address-cells = <1>; +- #size-cells = <0>; +- #sound-dai-cells = <1>; +- iommus = <&apps_smmu 0x1821 0x0>; +- }; +- }; +- +- q6adm: apr-service@8 { +- compatible = "qcom,q6adm"; +- reg = ; +- qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; +- q6routing: routing { +- compatible = "qcom,q6adm-routing"; +- #sound-dai-cells = <0>; +- }; +- }; +- }; +- +- fastrpc { +- compatible = "qcom,fastrpc"; +- qcom,glink-channels = "fastrpcglink-apps-dsp"; +- label = "adsp"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- compute-cb@3 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <3>; +- iommus = <&apps_smmu 0x1823 0x0>; +- }; +- +- compute-cb@4 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <4>; +- iommus = <&apps_smmu 0x1824 0x0>; +- }; +- }; +- }; +- }; +- +- cdsp_pas: remoteproc-cdsp { +- compatible = "qcom,sdm845-cdsp-pas"; +- +- interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, +- <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack"; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "xo"; +- +- memory-region = <&cdsp_mem>; +- +- qcom,smem-states = <&cdsp_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- status = "disabled"; +- +- glink-edge { +- interrupts = ; +- label = "turing"; +- qcom,remote-pid = <5>; +- mboxes = <&apss_shared 4>; +- fastrpc { +- compatible = "qcom,fastrpc"; +- qcom,glink-channels = "fastrpcglink-apps-dsp"; +- label = "cdsp"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- compute-cb@1 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <1>; +- iommus = <&apps_smmu 0x1401 0x30>; +- }; +- +- compute-cb@2 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <2>; +- iommus = <&apps_smmu 0x1402 0x30>; +- }; +- +- compute-cb@3 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <3>; +- iommus = <&apps_smmu 0x1403 0x30>; +- }; +- +- compute-cb@4 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <4>; +- iommus = <&apps_smmu 0x1404 0x30>; +- }; +- +- compute-cb@5 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <5>; +- iommus = <&apps_smmu 0x1405 0x30>; +- }; +- +- compute-cb@6 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <6>; +- iommus = <&apps_smmu 0x1406 0x30>; +- }; +- +- compute-cb@7 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <7>; +- iommus = <&apps_smmu 0x1407 0x30>; +- }; +- +- compute-cb@8 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <8>; +- iommus = <&apps_smmu 0x1408 0x30>; +- }; +- }; +- }; +- }; +- +- tcsr_mutex: hwlock { +- compatible = "qcom,tcsr-mutex"; +- syscon = <&tcsr_mutex_regs 0 0x1000>; +- #hwlock-cells = <1>; +- }; +- +- smem { +- compatible = "qcom,smem"; +- memory-region = <&smem_mem>; +- hwlocks = <&tcsr_mutex 3>; +- }; +- +- smp2p-cdsp { +- compatible = "qcom,smp2p"; +- qcom,smem = <94>, <432>; +- +- interrupts = ; +- +- mboxes = <&apss_shared 6>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <5>; +- +- cdsp_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- cdsp_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-lpass { +- compatible = "qcom,smp2p"; +- qcom,smem = <443>, <429>; +- +- interrupts = ; +- +- mboxes = <&apss_shared 10>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <2>; +- +- adsp_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- adsp_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-mpss { +- compatible = "qcom,smp2p"; +- qcom,smem = <435>, <428>; +- interrupts = ; +- mboxes = <&apss_shared 14>; +- qcom,local-pid = <0>; +- qcom,remote-pid = <1>; +- +- modem_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- modem_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- ipa_smp2p_out: ipa-ap-to-modem { +- qcom,entry-name = "ipa"; +- #qcom,smem-state-cells = <1>; +- }; +- +- ipa_smp2p_in: ipa-modem-to-ap { +- qcom,entry-name = "ipa"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-slpi { +- compatible = "qcom,smp2p"; +- qcom,smem = <481>, <430>; +- interrupts = ; +- mboxes = <&apss_shared 26>; +- qcom,local-pid = <0>; +- qcom,remote-pid = <3>; +- +- slpi_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- slpi_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- soc: soc@0 { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0 0 0 0 0x10 0>; +- dma-ranges = <0 0 0 0 0x10 0>; +- compatible = "simple-bus"; +- +- gcc: clock-controller@100000 { +- compatible = "qcom,gcc-sdm845"; +- reg = <0 0x00100000 0 0x1f0000>; +- clocks = <&rpmhcc RPMH_CXO_CLK>, +- <&rpmhcc RPMH_CXO_CLK_A>, +- <&sleep_clk>, +- <&pcie0_lane>, +- <&pcie1_lane>; +- clock-names = "bi_tcxo", +- "bi_tcxo_ao", +- "sleep_clk", +- "pcie_0_pipe_clk", +- "pcie_1_pipe_clk"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- }; +- +- qfprom@784000 { +- compatible = "qcom,qfprom"; +- reg = <0 0x00784000 0 0x8ff>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- qusb2p_hstx_trim: hstx-trim-primary@1eb { +- reg = <0x1eb 0x1>; +- bits = <1 4>; +- }; +- +- qusb2s_hstx_trim: hstx-trim-secondary@1eb { +- reg = <0x1eb 0x2>; +- bits = <6 4>; +- }; +- }; +- +- rng: rng@793000 { +- compatible = "qcom,prng-ee"; +- reg = <0 0x00793000 0 0x1000>; +- clocks = <&gcc GCC_PRNG_AHB_CLK>; +- clock-names = "core"; +- }; +- +- qup_opp_table: qup-opp-table { +- compatible = "operating-points-v2"; +- +- opp-50000000 { +- opp-hz = /bits/ 64 <50000000>; +- required-opps = <&rpmhpd_opp_min_svs>; +- }; +- +- opp-75000000 { +- opp-hz = /bits/ 64 <75000000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- }; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- required-opps = <&rpmhpd_opp_svs>; +- }; +- +- opp-128000000 { +- opp-hz = /bits/ 64 <128000000>; +- required-opps = <&rpmhpd_opp_nom>; +- }; +- }; +- +- qupv3_id_0: geniqup@8c0000 { +- compatible = "qcom,geni-se-qup"; +- reg = <0 0x008c0000 0 0x6000>; +- clock-names = "m-ahb", "s-ahb"; +- clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, +- <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; +- iommus = <&apps_smmu 0x3 0x0>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; +- interconnect-names = "qup-core"; +- status = "disabled"; +- +- i2c0: i2c@880000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00880000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c0_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, +- <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", "qup-memory"; +- status = "disabled"; +- }; +- +- spi0: spi@880000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00880000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi0_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart0: serial@880000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00880000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart0_default>; +- interrupts = ; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c1: i2c@884000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00884000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c1_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, +- <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", "qup-memory"; +- status = "disabled"; +- }; +- +- spi1: spi@884000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00884000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi1_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart1: serial@884000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00884000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart1_default>; +- interrupts = ; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c2: i2c@888000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00888000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c2_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, +- <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", "qup-memory"; +- status = "disabled"; +- }; +- +- spi2: spi@888000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00888000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi2_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart2: serial@888000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00888000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart2_default>; +- interrupts = ; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c3: i2c@88c000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x0088c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c3_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, +- <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", "qup-memory"; +- status = "disabled"; +- }; +- +- spi3: spi@88c000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x0088c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi3_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart3: serial@88c000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x0088c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart3_default>; +- interrupts = ; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c4: i2c@890000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00890000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c4_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, +- <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", "qup-memory"; +- status = "disabled"; +- }; +- +- spi4: spi@890000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00890000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi4_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart4: serial@890000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00890000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart4_default>; +- interrupts = ; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c5: i2c@894000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00894000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c5_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, +- <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", "qup-memory"; +- status = "disabled"; +- }; +- +- spi5: spi@894000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00894000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi5_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart5: serial@894000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00894000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart5_default>; +- interrupts = ; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c6: i2c@898000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00898000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c6_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, +- <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", "qup-memory"; +- status = "disabled"; +- }; +- +- spi6: spi@898000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00898000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi6_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart6: serial@898000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00898000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart6_default>; +- interrupts = ; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c7: i2c@89c000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x0089c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c7_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- status = "disabled"; +- }; +- +- spi7: spi@89c000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x0089c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi7_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart7: serial@89c000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x0089c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart7_default>; +- interrupts = ; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- }; +- +- qupv3_id_1: geniqup@ac0000 { +- compatible = "qcom,geni-se-qup"; +- reg = <0 0x00ac0000 0 0x6000>; +- clock-names = "m-ahb", "s-ahb"; +- clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, +- <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; +- iommus = <&apps_smmu 0x6c3 0x0>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; +- interconnect-names = "qup-core"; +- status = "disabled"; +- +- i2c8: i2c@a80000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a80000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c8_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, +- <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", "qup-memory"; +- status = "disabled"; +- }; +- +- spi8: spi@a80000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00a80000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi8_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart8: serial@a80000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00a80000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart8_default>; +- interrupts = ; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c9: i2c@a84000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a84000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c9_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, +- <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", "qup-memory"; +- status = "disabled"; +- }; +- +- spi9: spi@a84000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00a84000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi9_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart9: serial@a84000 { +- compatible = "qcom,geni-debug-uart"; +- reg = <0 0x00a84000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart9_default>; +- interrupts = ; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c10: i2c@a88000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a88000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c10_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, +- <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", "qup-memory"; +- status = "disabled"; +- }; +- +- spi10: spi@a88000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00a88000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi10_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart10: serial@a88000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00a88000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart10_default>; +- interrupts = ; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c11: i2c@a8c000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a8c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c11_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, +- <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", "qup-memory"; +- status = "disabled"; +- }; +- +- spi11: spi@a8c000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00a8c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi11_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart11: serial@a8c000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00a8c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart11_default>; +- interrupts = ; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c12: i2c@a90000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a90000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c12_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, +- <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", "qup-memory"; +- status = "disabled"; +- }; +- +- spi12: spi@a90000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00a90000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi12_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart12: serial@a90000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00a90000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart12_default>; +- interrupts = ; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c13: i2c@a94000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a94000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c13_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, +- <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", "qup-memory"; +- status = "disabled"; +- }; +- +- spi13: spi@a94000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00a94000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi13_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart13: serial@a94000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00a94000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart13_default>; +- interrupts = ; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c14: i2c@a98000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a98000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c14_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, +- <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", "qup-memory"; +- status = "disabled"; +- }; +- +- spi14: spi@a98000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00a98000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi14_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart14: serial@a98000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00a98000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart14_default>; +- interrupts = ; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- i2c15: i2c@a9c000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a9c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c15_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- status = "disabled"; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, +- <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; +- interconnect-names = "qup-core", "qup-config", "qup-memory"; +- }; +- +- spi15: spi@a9c000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00a9c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi15_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- +- uart15: serial@a9c000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00a9c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart15_default>; +- interrupts = ; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qup_opp_table>; +- interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; +- interconnect-names = "qup-core", "qup-config"; +- status = "disabled"; +- }; +- }; +- +- system-cache-controller@1100000 { +- compatible = "qcom,sdm845-llcc"; +- reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; +- reg-names = "llcc_base", "llcc_broadcast_base"; +- interrupts = ; +- }; +- +- pcie0: pci@1c00000 { +- compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; +- reg = <0 0x01c00000 0 0x2000>, +- <0 0x60000000 0 0xf1d>, +- <0 0x60000f20 0 0xa8>, +- <0 0x60100000 0 0x100000>; +- reg-names = "parf", "dbi", "elbi", "config"; +- device_type = "pci"; +- linux,pci-domain = <0>; +- bus-range = <0x00 0xff>; +- num-lanes = <1>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, +- <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>; +- +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ +- <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ +- <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ +- <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ +- +- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, +- <&gcc GCC_PCIE_0_AUX_CLK>, +- <&gcc GCC_PCIE_0_CFG_AHB_CLK>, +- <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, +- <&gcc GCC_PCIE_0_SLV_AXI_CLK>, +- <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, +- <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; +- clock-names = "pipe", +- "aux", +- "cfg", +- "bus_master", +- "bus_slave", +- "slave_q2a", +- "tbu"; +- +- iommus = <&apps_smmu 0x1c10 0xf>; +- iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, +- <0x100 &apps_smmu 0x1c11 0x1>, +- <0x200 &apps_smmu 0x1c12 0x1>, +- <0x300 &apps_smmu 0x1c13 0x1>, +- <0x400 &apps_smmu 0x1c14 0x1>, +- <0x500 &apps_smmu 0x1c15 0x1>, +- <0x600 &apps_smmu 0x1c16 0x1>, +- <0x700 &apps_smmu 0x1c17 0x1>, +- <0x800 &apps_smmu 0x1c18 0x1>, +- <0x900 &apps_smmu 0x1c19 0x1>, +- <0xa00 &apps_smmu 0x1c1a 0x1>, +- <0xb00 &apps_smmu 0x1c1b 0x1>, +- <0xc00 &apps_smmu 0x1c1c 0x1>, +- <0xd00 &apps_smmu 0x1c1d 0x1>, +- <0xe00 &apps_smmu 0x1c1e 0x1>, +- <0xf00 &apps_smmu 0x1c1f 0x1>; +- +- resets = <&gcc GCC_PCIE_0_BCR>; +- reset-names = "pci"; +- +- power-domains = <&gcc PCIE_0_GDSC>; +- +- phys = <&pcie0_lane>; +- phy-names = "pciephy"; +- +- status = "disabled"; +- }; +- +- pcie0_phy: phy@1c06000 { +- compatible = "qcom,sdm845-qmp-pcie-phy"; +- reg = <0 0x01c06000 0 0x18c>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, +- <&gcc GCC_PCIE_0_CFG_AHB_CLK>, +- <&gcc GCC_PCIE_0_CLKREF_CLK>, +- <&gcc GCC_PCIE_PHY_REFGEN_CLK>; +- clock-names = "aux", "cfg_ahb", "ref", "refgen"; +- +- resets = <&gcc GCC_PCIE_0_PHY_BCR>; +- reset-names = "phy"; +- +- assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; +- assigned-clock-rates = <100000000>; +- +- status = "disabled"; +- +- pcie0_lane: lanes@1c06200 { +- reg = <0 0x01c06200 0 0x128>, +- <0 0x01c06400 0 0x1fc>, +- <0 0x01c06800 0 0x218>, +- <0 0x01c06600 0 0x70>; +- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; +- clock-names = "pipe0"; +- +- #clock-cells = <0>; +- #phy-cells = <0>; +- clock-output-names = "pcie_0_pipe_clk"; +- }; +- }; +- +- pcie1: pci@1c08000 { +- compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; +- reg = <0 0x01c08000 0 0x2000>, +- <0 0x40000000 0 0xf1d>, +- <0 0x40000f20 0 0xa8>, +- <0 0x40100000 0 0x100000>; +- reg-names = "parf", "dbi", "elbi", "config"; +- device_type = "pci"; +- linux,pci-domain = <1>; +- bus-range = <0x00 0xff>; +- num-lanes = <1>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, +- <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; +- +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ +- <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ +- <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ +- <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ +- +- clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, +- <&gcc GCC_PCIE_1_AUX_CLK>, +- <&gcc GCC_PCIE_1_CFG_AHB_CLK>, +- <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, +- <&gcc GCC_PCIE_1_SLV_AXI_CLK>, +- <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, +- <&gcc GCC_PCIE_1_CLKREF_CLK>, +- <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; +- clock-names = "pipe", +- "aux", +- "cfg", +- "bus_master", +- "bus_slave", +- "slave_q2a", +- "ref", +- "tbu"; +- +- assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; +- assigned-clock-rates = <19200000>; +- +- iommus = <&apps_smmu 0x1c00 0xf>; +- iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, +- <0x100 &apps_smmu 0x1c01 0x1>, +- <0x200 &apps_smmu 0x1c02 0x1>, +- <0x300 &apps_smmu 0x1c03 0x1>, +- <0x400 &apps_smmu 0x1c04 0x1>, +- <0x500 &apps_smmu 0x1c05 0x1>, +- <0x600 &apps_smmu 0x1c06 0x1>, +- <0x700 &apps_smmu 0x1c07 0x1>, +- <0x800 &apps_smmu 0x1c08 0x1>, +- <0x900 &apps_smmu 0x1c09 0x1>, +- <0xa00 &apps_smmu 0x1c0a 0x1>, +- <0xb00 &apps_smmu 0x1c0b 0x1>, +- <0xc00 &apps_smmu 0x1c0c 0x1>, +- <0xd00 &apps_smmu 0x1c0d 0x1>, +- <0xe00 &apps_smmu 0x1c0e 0x1>, +- <0xf00 &apps_smmu 0x1c0f 0x1>; +- +- resets = <&gcc GCC_PCIE_1_BCR>; +- reset-names = "pci"; +- +- power-domains = <&gcc PCIE_1_GDSC>; +- +- phys = <&pcie1_lane>; +- phy-names = "pciephy"; +- +- status = "disabled"; +- }; +- +- pcie1_phy: phy@1c0a000 { +- compatible = "qcom,sdm845-qhp-pcie-phy"; +- reg = <0 0x01c0a000 0 0x800>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, +- <&gcc GCC_PCIE_1_CFG_AHB_CLK>, +- <&gcc GCC_PCIE_1_CLKREF_CLK>, +- <&gcc GCC_PCIE_PHY_REFGEN_CLK>; +- clock-names = "aux", "cfg_ahb", "ref", "refgen"; +- +- resets = <&gcc GCC_PCIE_1_PHY_BCR>; +- reset-names = "phy"; +- +- assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; +- assigned-clock-rates = <100000000>; +- +- status = "disabled"; +- +- pcie1_lane: lanes@1c06200 { +- reg = <0 0x01c0a800 0 0x800>, +- <0 0x01c0a800 0 0x800>, +- <0 0x01c0b800 0 0x400>; +- clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; +- clock-names = "pipe0"; +- +- #clock-cells = <0>; +- #phy-cells = <0>; +- clock-output-names = "pcie_1_pipe_clk"; +- }; +- }; +- +- mem_noc: interconnect@1380000 { +- compatible = "qcom,sdm845-mem-noc"; +- reg = <0 0x01380000 0 0x27200>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- dc_noc: interconnect@14e0000 { +- compatible = "qcom,sdm845-dc-noc"; +- reg = <0 0x014e0000 0 0x400>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- config_noc: interconnect@1500000 { +- compatible = "qcom,sdm845-config-noc"; +- reg = <0 0x01500000 0 0x5080>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- system_noc: interconnect@1620000 { +- compatible = "qcom,sdm845-system-noc"; +- reg = <0 0x01620000 0 0x18080>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- aggre1_noc: interconnect@16e0000 { +- compatible = "qcom,sdm845-aggre1-noc"; +- reg = <0 0x016e0000 0 0x15080>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- aggre2_noc: interconnect@1700000 { +- compatible = "qcom,sdm845-aggre2-noc"; +- reg = <0 0x01700000 0 0x1f300>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- mmss_noc: interconnect@1740000 { +- compatible = "qcom,sdm845-mmss-noc"; +- reg = <0 0x01740000 0 0x1c100>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- ufs_mem_hc: ufshc@1d84000 { +- compatible = "qcom,sdm845-ufshc", "qcom,ufshc", +- "jedec,ufs-2.0"; +- reg = <0 0x01d84000 0 0x2500>, +- <0 0x01d90000 0 0x8000>; +- reg-names = "std", "ice"; +- interrupts = ; +- phys = <&ufs_mem_phy_lanes>; +- phy-names = "ufsphy"; +- lanes-per-direction = <2>; +- power-domains = <&gcc UFS_PHY_GDSC>; +- #reset-cells = <1>; +- resets = <&gcc GCC_UFS_PHY_BCR>; +- reset-names = "rst"; +- +- iommus = <&apps_smmu 0x100 0xf>; +- +- clock-names = +- "core_clk", +- "bus_aggr_clk", +- "iface_clk", +- "core_clk_unipro", +- "ref_clk", +- "tx_lane0_sync_clk", +- "rx_lane0_sync_clk", +- "rx_lane1_sync_clk", +- "ice_core_clk"; +- clocks = +- <&gcc GCC_UFS_PHY_AXI_CLK>, +- <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, +- <&gcc GCC_UFS_PHY_AHB_CLK>, +- <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, +- <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, +- <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, +- <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, +- <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; +- freq-table-hz = +- <50000000 200000000>, +- <0 0>, +- <0 0>, +- <37500000 150000000>, +- <0 0>, +- <0 0>, +- <0 0>, +- <0 0>, +- <0 300000000>; +- +- status = "disabled"; +- }; +- +- ufs_mem_phy: phy@1d87000 { +- compatible = "qcom,sdm845-qmp-ufs-phy"; +- reg = <0 0x01d87000 0 0x18c>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- clock-names = "ref", +- "ref_aux"; +- clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, +- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; +- +- resets = <&ufs_mem_hc 0>; +- reset-names = "ufsphy"; +- status = "disabled"; +- +- ufs_mem_phy_lanes: lanes@1d87400 { +- reg = <0 0x01d87400 0 0x108>, +- <0 0x01d87600 0 0x1e0>, +- <0 0x01d87c00 0 0x1dc>, +- <0 0x01d87800 0 0x108>, +- <0 0x01d87a00 0 0x1e0>; +- #phy-cells = <0>; +- }; +- }; +- +- cryptobam: dma@1dc4000 { +- compatible = "qcom,bam-v1.7.0"; +- reg = <0 0x01dc4000 0 0x24000>; +- interrupts = ; +- clocks = <&rpmhcc RPMH_CE_CLK>; +- clock-names = "bam_clk"; +- #dma-cells = <1>; +- qcom,ee = <0>; +- qcom,controlled-remotely; +- iommus = <&apps_smmu 0x704 0x1>, +- <&apps_smmu 0x706 0x1>, +- <&apps_smmu 0x714 0x1>, +- <&apps_smmu 0x716 0x1>; +- }; +- +- crypto: crypto@1dfa000 { +- compatible = "qcom,crypto-v5.4"; +- reg = <0 0x01dfa000 0 0x6000>; +- clocks = <&gcc GCC_CE1_AHB_CLK>, +- <&gcc GCC_CE1_AXI_CLK>, +- <&rpmhcc RPMH_CE_CLK>; +- clock-names = "iface", "bus", "core"; +- dmas = <&cryptobam 6>, <&cryptobam 7>; +- dma-names = "rx", "tx"; +- iommus = <&apps_smmu 0x704 0x1>, +- <&apps_smmu 0x706 0x1>, +- <&apps_smmu 0x714 0x1>, +- <&apps_smmu 0x716 0x1>; +- }; +- +- ipa: ipa@1e40000 { +- compatible = "qcom,sdm845-ipa"; +- +- iommus = <&apps_smmu 0x720 0x0>, +- <&apps_smmu 0x722 0x0>; +- reg = <0 0x1e40000 0 0x7000>, +- <0 0x1e47000 0 0x2000>, +- <0 0x1e04000 0 0x2c000>; +- reg-names = "ipa-reg", +- "ipa-shared", +- "gsi"; +- +- interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, +- <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, +- <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "ipa", +- "gsi", +- "ipa-clock-query", +- "ipa-setup-ready"; +- +- clocks = <&rpmhcc RPMH_IPA_CLK>; +- clock-names = "core"; +- +- interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, +- <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; +- interconnect-names = "memory", +- "imem", +- "config"; +- +- qcom,smem-states = <&ipa_smp2p_out 0>, +- <&ipa_smp2p_out 1>; +- qcom,smem-state-names = "ipa-clock-enabled-valid", +- "ipa-clock-enabled"; +- +- status = "disabled"; +- }; +- +- tcsr_mutex_regs: syscon@1f40000 { +- compatible = "syscon"; +- reg = <0 0x01f40000 0 0x40000>; +- }; +- +- tlmm: pinctrl@3400000 { +- compatible = "qcom,sdm845-pinctrl"; +- reg = <0 0x03400000 0 0xc00000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&tlmm 0 0 151>; +- wakeup-parent = <&pdc_intc>; +- +- cci0_default: cci0-default { +- /* SDA, SCL */ +- pins = "gpio17", "gpio18"; +- function = "cci_i2c"; +- +- bias-pull-up; +- drive-strength = <2>; /* 2 mA */ +- }; +- +- cci0_sleep: cci0-sleep { +- /* SDA, SCL */ +- pins = "gpio17", "gpio18"; +- function = "cci_i2c"; +- +- drive-strength = <2>; /* 2 mA */ +- bias-pull-down; +- }; +- +- cci1_default: cci1-default { +- /* SDA, SCL */ +- pins = "gpio19", "gpio20"; +- function = "cci_i2c"; +- +- bias-pull-up; +- drive-strength = <2>; /* 2 mA */ +- }; +- +- cci1_sleep: cci1-sleep { +- /* SDA, SCL */ +- pins = "gpio19", "gpio20"; +- function = "cci_i2c"; +- +- drive-strength = <2>; /* 2 mA */ +- bias-pull-down; +- }; +- +- qspi_clk: qspi-clk { +- pinmux { +- pins = "gpio95"; +- function = "qspi_clk"; +- }; +- }; +- +- qspi_cs0: qspi-cs0 { +- pinmux { +- pins = "gpio90"; +- function = "qspi_cs"; +- }; +- }; +- +- qspi_cs1: qspi-cs1 { +- pinmux { +- pins = "gpio89"; +- function = "qspi_cs"; +- }; +- }; +- +- qspi_data01: qspi-data01 { +- pinmux-data { +- pins = "gpio91", "gpio92"; +- function = "qspi_data"; +- }; +- }; +- +- qspi_data12: qspi-data12 { +- pinmux-data { +- pins = "gpio93", "gpio94"; +- function = "qspi_data"; +- }; +- }; +- +- qup_i2c0_default: qup-i2c0-default { +- pinmux { +- pins = "gpio0", "gpio1"; +- function = "qup0"; +- }; +- }; +- +- qup_i2c1_default: qup-i2c1-default { +- pinmux { +- pins = "gpio17", "gpio18"; +- function = "qup1"; +- }; +- }; +- +- qup_i2c2_default: qup-i2c2-default { +- pinmux { +- pins = "gpio27", "gpio28"; +- function = "qup2"; +- }; +- }; +- +- qup_i2c3_default: qup-i2c3-default { +- pinmux { +- pins = "gpio41", "gpio42"; +- function = "qup3"; +- }; +- }; +- +- qup_i2c4_default: qup-i2c4-default { +- pinmux { +- pins = "gpio89", "gpio90"; +- function = "qup4"; +- }; +- }; +- +- qup_i2c5_default: qup-i2c5-default { +- pinmux { +- pins = "gpio85", "gpio86"; +- function = "qup5"; +- }; +- }; +- +- qup_i2c6_default: qup-i2c6-default { +- pinmux { +- pins = "gpio45", "gpio46"; +- function = "qup6"; +- }; +- }; +- +- qup_i2c7_default: qup-i2c7-default { +- pinmux { +- pins = "gpio93", "gpio94"; +- function = "qup7"; +- }; +- }; +- +- qup_i2c8_default: qup-i2c8-default { +- pinmux { +- pins = "gpio65", "gpio66"; +- function = "qup8"; +- }; +- }; +- +- qup_i2c9_default: qup-i2c9-default { +- pinmux { +- pins = "gpio6", "gpio7"; +- function = "qup9"; +- }; +- }; +- +- qup_i2c10_default: qup-i2c10-default { +- pinmux { +- pins = "gpio55", "gpio56"; +- function = "qup10"; +- }; +- }; +- +- qup_i2c11_default: qup-i2c11-default { +- pinmux { +- pins = "gpio31", "gpio32"; +- function = "qup11"; +- }; +- }; +- +- qup_i2c12_default: qup-i2c12-default { +- pinmux { +- pins = "gpio49", "gpio50"; +- function = "qup12"; +- }; +- }; +- +- qup_i2c13_default: qup-i2c13-default { +- pinmux { +- pins = "gpio105", "gpio106"; +- function = "qup13"; +- }; +- }; +- +- qup_i2c14_default: qup-i2c14-default { +- pinmux { +- pins = "gpio33", "gpio34"; +- function = "qup14"; +- }; +- }; +- +- qup_i2c15_default: qup-i2c15-default { +- pinmux { +- pins = "gpio81", "gpio82"; +- function = "qup15"; +- }; +- }; +- +- qup_spi0_default: qup-spi0-default { +- pinmux { +- pins = "gpio0", "gpio1", +- "gpio2", "gpio3"; +- function = "qup0"; +- }; +- }; +- +- qup_spi1_default: qup-spi1-default { +- pinmux { +- pins = "gpio17", "gpio18", +- "gpio19", "gpio20"; +- function = "qup1"; +- }; +- }; +- +- qup_spi2_default: qup-spi2-default { +- pinmux { +- pins = "gpio27", "gpio28", +- "gpio29", "gpio30"; +- function = "qup2"; +- }; +- }; +- +- qup_spi3_default: qup-spi3-default { +- pinmux { +- pins = "gpio41", "gpio42", +- "gpio43", "gpio44"; +- function = "qup3"; +- }; +- }; +- +- qup_spi4_default: qup-spi4-default { +- pinmux { +- pins = "gpio89", "gpio90", +- "gpio91", "gpio92"; +- function = "qup4"; +- }; +- }; +- +- qup_spi5_default: qup-spi5-default { +- pinmux { +- pins = "gpio85", "gpio86", +- "gpio87", "gpio88"; +- function = "qup5"; +- }; +- }; +- +- qup_spi6_default: qup-spi6-default { +- pinmux { +- pins = "gpio45", "gpio46", +- "gpio47", "gpio48"; +- function = "qup6"; +- }; +- }; +- +- qup_spi7_default: qup-spi7-default { +- pinmux { +- pins = "gpio93", "gpio94", +- "gpio95", "gpio96"; +- function = "qup7"; +- }; +- }; +- +- qup_spi8_default: qup-spi8-default { +- pinmux { +- pins = "gpio65", "gpio66", +- "gpio67", "gpio68"; +- function = "qup8"; +- }; +- }; +- +- qup_spi9_default: qup-spi9-default { +- pinmux { +- pins = "gpio6", "gpio7", +- "gpio4", "gpio5"; +- function = "qup9"; +- }; +- }; +- +- qup_spi10_default: qup-spi10-default { +- pinmux { +- pins = "gpio55", "gpio56", +- "gpio53", "gpio54"; +- function = "qup10"; +- }; +- }; +- +- qup_spi11_default: qup-spi11-default { +- pinmux { +- pins = "gpio31", "gpio32", +- "gpio33", "gpio34"; +- function = "qup11"; +- }; +- }; +- +- qup_spi12_default: qup-spi12-default { +- pinmux { +- pins = "gpio49", "gpio50", +- "gpio51", "gpio52"; +- function = "qup12"; +- }; +- }; +- +- qup_spi13_default: qup-spi13-default { +- pinmux { +- pins = "gpio105", "gpio106", +- "gpio107", "gpio108"; +- function = "qup13"; +- }; +- }; +- +- qup_spi14_default: qup-spi14-default { +- pinmux { +- pins = "gpio33", "gpio34", +- "gpio31", "gpio32"; +- function = "qup14"; +- }; +- }; +- +- qup_spi15_default: qup-spi15-default { +- pinmux { +- pins = "gpio81", "gpio82", +- "gpio83", "gpio84"; +- function = "qup15"; +- }; +- }; +- +- qup_uart0_default: qup-uart0-default { +- pinmux { +- pins = "gpio2", "gpio3"; +- function = "qup0"; +- }; +- }; +- +- qup_uart1_default: qup-uart1-default { +- pinmux { +- pins = "gpio19", "gpio20"; +- function = "qup1"; +- }; +- }; +- +- qup_uart2_default: qup-uart2-default { +- pinmux { +- pins = "gpio29", "gpio30"; +- function = "qup2"; +- }; +- }; +- +- qup_uart3_default: qup-uart3-default { +- pinmux { +- pins = "gpio43", "gpio44"; +- function = "qup3"; +- }; +- }; +- +- qup_uart4_default: qup-uart4-default { +- pinmux { +- pins = "gpio91", "gpio92"; +- function = "qup4"; +- }; +- }; +- +- qup_uart5_default: qup-uart5-default { +- pinmux { +- pins = "gpio87", "gpio88"; +- function = "qup5"; +- }; +- }; +- +- qup_uart6_default: qup-uart6-default { +- pinmux { +- pins = "gpio47", "gpio48"; +- function = "qup6"; +- }; +- }; +- +- qup_uart7_default: qup-uart7-default { +- pinmux { +- pins = "gpio95", "gpio96"; +- function = "qup7"; +- }; +- }; +- +- qup_uart8_default: qup-uart8-default { +- pinmux { +- pins = "gpio67", "gpio68"; +- function = "qup8"; +- }; +- }; +- +- qup_uart9_default: qup-uart9-default { +- pinmux { +- pins = "gpio4", "gpio5"; +- function = "qup9"; +- }; +- }; +- +- qup_uart10_default: qup-uart10-default { +- pinmux { +- pins = "gpio53", "gpio54"; +- function = "qup10"; +- }; +- }; +- +- qup_uart11_default: qup-uart11-default { +- pinmux { +- pins = "gpio33", "gpio34"; +- function = "qup11"; +- }; +- }; +- +- qup_uart12_default: qup-uart12-default { +- pinmux { +- pins = "gpio51", "gpio52"; +- function = "qup12"; +- }; +- }; +- +- qup_uart13_default: qup-uart13-default { +- pinmux { +- pins = "gpio107", "gpio108"; +- function = "qup13"; +- }; +- }; +- +- qup_uart14_default: qup-uart14-default { +- pinmux { +- pins = "gpio31", "gpio32"; +- function = "qup14"; +- }; +- }; +- +- qup_uart15_default: qup-uart15-default { +- pinmux { +- pins = "gpio83", "gpio84"; +- function = "qup15"; +- }; +- }; +- +- quat_mi2s_sleep: quat_mi2s_sleep { +- mux { +- pins = "gpio58", "gpio59"; +- function = "gpio"; +- }; +- +- config { +- pins = "gpio58", "gpio59"; +- drive-strength = <2>; +- bias-pull-down; +- input-enable; +- }; +- }; +- +- quat_mi2s_active: quat_mi2s_active { +- mux { +- pins = "gpio58", "gpio59"; +- function = "qua_mi2s"; +- }; +- +- config { +- pins = "gpio58", "gpio59"; +- drive-strength = <8>; +- bias-disable; +- output-high; +- }; +- }; +- +- quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { +- mux { +- pins = "gpio60"; +- function = "gpio"; +- }; +- +- config { +- pins = "gpio60"; +- drive-strength = <2>; +- bias-pull-down; +- input-enable; +- }; +- }; +- +- quat_mi2s_sd0_active: quat_mi2s_sd0_active { +- mux { +- pins = "gpio60"; +- function = "qua_mi2s"; +- }; +- +- config { +- pins = "gpio60"; +- drive-strength = <8>; +- bias-disable; +- }; +- }; +- +- quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { +- mux { +- pins = "gpio61"; +- function = "gpio"; +- }; +- +- config { +- pins = "gpio61"; +- drive-strength = <2>; +- bias-pull-down; +- input-enable; +- }; +- }; +- +- quat_mi2s_sd1_active: quat_mi2s_sd1_active { +- mux { +- pins = "gpio61"; +- function = "qua_mi2s"; +- }; +- +- config { +- pins = "gpio61"; +- drive-strength = <8>; +- bias-disable; +- }; +- }; +- +- quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { +- mux { +- pins = "gpio62"; +- function = "gpio"; +- }; +- +- config { +- pins = "gpio62"; +- drive-strength = <2>; +- bias-pull-down; +- input-enable; +- }; +- }; +- +- quat_mi2s_sd2_active: quat_mi2s_sd2_active { +- mux { +- pins = "gpio62"; +- function = "qua_mi2s"; +- }; +- +- config { +- pins = "gpio62"; +- drive-strength = <8>; +- bias-disable; +- }; +- }; +- +- quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { +- mux { +- pins = "gpio63"; +- function = "gpio"; +- }; +- +- config { +- pins = "gpio63"; +- drive-strength = <2>; +- bias-pull-down; +- input-enable; +- }; +- }; +- +- quat_mi2s_sd3_active: quat_mi2s_sd3_active { +- mux { +- pins = "gpio63"; +- function = "qua_mi2s"; +- }; +- +- config { +- pins = "gpio63"; +- drive-strength = <8>; +- bias-disable; +- }; +- }; +- }; +- +- mss_pil: remoteproc@4080000 { +- compatible = "qcom,sdm845-mss-pil"; +- reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; +- reg-names = "qdsp6", "rmb"; +- +- interrupts-extended = +- <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack", +- "shutdown-ack"; +- +- clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, +- <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, +- <&gcc GCC_BOOT_ROM_AHB_CLK>, +- <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, +- <&gcc GCC_MSS_SNOC_AXI_CLK>, +- <&gcc GCC_MSS_MFAB_AXIS_CLK>, +- <&gcc GCC_PRNG_AHB_CLK>, +- <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "iface", "bus", "mem", "gpll0_mss", +- "snoc_axi", "mnoc_axi", "prng", "xo"; +- +- qcom,smem-states = <&modem_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- resets = <&aoss_reset AOSS_CC_MSS_RESTART>, +- <&pdc_reset PDC_MODEM_SYNC_RESET>; +- reset-names = "mss_restart", "pdc_reset"; +- +- qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; +- +- power-domains = <&aoss_qmp 2>, +- <&rpmhpd SDM845_CX>, +- <&rpmhpd SDM845_MX>, +- <&rpmhpd SDM845_MSS>; +- power-domain-names = "load_state", "cx", "mx", "mss"; +- +- mba { +- memory-region = <&mba_region>; +- }; +- +- mpss { +- memory-region = <&mpss_region>; +- }; +- +- glink-edge { +- interrupts = ; +- label = "modem"; +- qcom,remote-pid = <1>; +- mboxes = <&apss_shared 12>; +- }; +- }; +- +- gpucc: clock-controller@5090000 { +- compatible = "qcom,sdm845-gpucc"; +- reg = <0 0x05090000 0 0x9000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- clocks = <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_GPU_GPLL0_CLK_SRC>, +- <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; +- clock-names = "bi_tcxo", +- "gcc_gpu_gpll0_clk_src", +- "gcc_gpu_gpll0_div_clk_src"; +- }; +- +- stm@6002000 { +- compatible = "arm,coresight-stm", "arm,primecell"; +- reg = <0 0x06002000 0 0x1000>, +- <0 0x16280000 0 0x180000>; +- reg-names = "stm-base", "stm-stimulus-base"; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- stm_out: endpoint { +- remote-endpoint = +- <&funnel0_in7>; +- }; +- }; +- }; +- }; +- +- funnel@6041000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x06041000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- funnel0_out: endpoint { +- remote-endpoint = +- <&merge_funnel_in0>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@7 { +- reg = <7>; +- funnel0_in7: endpoint { +- remote-endpoint = <&stm_out>; +- }; +- }; +- }; +- }; +- +- funnel@6043000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x06043000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- funnel2_out: endpoint { +- remote-endpoint = +- <&merge_funnel_in2>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@5 { +- reg = <5>; +- funnel2_in5: endpoint { +- remote-endpoint = +- <&apss_merge_funnel_out>; +- }; +- }; +- }; +- }; +- +- funnel@6045000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x06045000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- merge_funnel_out: endpoint { +- remote-endpoint = <&etf_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- merge_funnel_in0: endpoint { +- remote-endpoint = +- <&funnel0_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- merge_funnel_in2: endpoint { +- remote-endpoint = +- <&funnel2_out>; +- }; +- }; +- }; +- }; +- +- replicator@6046000 { +- compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; +- reg = <0 0x06046000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- replicator_out: endpoint { +- remote-endpoint = <&etr_in>; +- }; +- }; +- }; +- +- in-ports { +- port { +- replicator_in: endpoint { +- remote-endpoint = <&etf_out>; +- }; +- }; +- }; +- }; +- +- etf@6047000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0x06047000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etf_out: endpoint { +- remote-endpoint = +- <&replicator_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <1>; +- etf_in: endpoint { +- remote-endpoint = +- <&merge_funnel_out>; +- }; +- }; +- }; +- }; +- +- etr@6048000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0x06048000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,scatter-gather; +- +- in-ports { +- port { +- etr_in: endpoint { +- remote-endpoint = +- <&replicator_out>; +- }; +- }; +- }; +- }; +- +- etm@7040000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07040000 0 0x1000>; +- +- cpu = <&CPU0>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- +- out-ports { +- port { +- etm0_out: endpoint { +- remote-endpoint = +- <&apss_funnel_in0>; +- }; +- }; +- }; +- }; +- +- etm@7140000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07140000 0 0x1000>; +- +- cpu = <&CPU1>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- +- out-ports { +- port { +- etm1_out: endpoint { +- remote-endpoint = +- <&apss_funnel_in1>; +- }; +- }; +- }; +- }; +- +- etm@7240000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07240000 0 0x1000>; +- +- cpu = <&CPU2>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- +- out-ports { +- port { +- etm2_out: endpoint { +- remote-endpoint = +- <&apss_funnel_in2>; +- }; +- }; +- }; +- }; +- +- etm@7340000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07340000 0 0x1000>; +- +- cpu = <&CPU3>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- +- out-ports { +- port { +- etm3_out: endpoint { +- remote-endpoint = +- <&apss_funnel_in3>; +- }; +- }; +- }; +- }; +- +- etm@7440000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07440000 0 0x1000>; +- +- cpu = <&CPU4>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- +- out-ports { +- port { +- etm4_out: endpoint { +- remote-endpoint = +- <&apss_funnel_in4>; +- }; +- }; +- }; +- }; +- +- etm@7540000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07540000 0 0x1000>; +- +- cpu = <&CPU5>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- +- out-ports { +- port { +- etm5_out: endpoint { +- remote-endpoint = +- <&apss_funnel_in5>; +- }; +- }; +- }; +- }; +- +- etm@7640000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07640000 0 0x1000>; +- +- cpu = <&CPU6>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- +- out-ports { +- port { +- etm6_out: endpoint { +- remote-endpoint = +- <&apss_funnel_in6>; +- }; +- }; +- }; +- }; +- +- etm@7740000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07740000 0 0x1000>; +- +- cpu = <&CPU7>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- +- out-ports { +- port { +- etm7_out: endpoint { +- remote-endpoint = +- <&apss_funnel_in7>; +- }; +- }; +- }; +- }; +- +- funnel@7800000 { /* APSS Funnel */ +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x07800000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- apss_funnel_out: endpoint { +- remote-endpoint = +- <&apss_merge_funnel_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- apss_funnel_in0: endpoint { +- remote-endpoint = +- <&etm0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- apss_funnel_in1: endpoint { +- remote-endpoint = +- <&etm1_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- apss_funnel_in2: endpoint { +- remote-endpoint = +- <&etm2_out>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- apss_funnel_in3: endpoint { +- remote-endpoint = +- <&etm3_out>; +- }; +- }; +- +- port@4 { +- reg = <4>; +- apss_funnel_in4: endpoint { +- remote-endpoint = +- <&etm4_out>; +- }; +- }; +- +- port@5 { +- reg = <5>; +- apss_funnel_in5: endpoint { +- remote-endpoint = +- <&etm5_out>; +- }; +- }; +- +- port@6 { +- reg = <6>; +- apss_funnel_in6: endpoint { +- remote-endpoint = +- <&etm6_out>; +- }; +- }; +- +- port@7 { +- reg = <7>; +- apss_funnel_in7: endpoint { +- remote-endpoint = +- <&etm7_out>; +- }; +- }; +- }; +- }; +- +- funnel@7810000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x07810000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- apss_merge_funnel_out: endpoint { +- remote-endpoint = +- <&funnel2_in5>; +- }; +- }; +- }; +- +- in-ports { +- port { +- apss_merge_funnel_in: endpoint { +- remote-endpoint = +- <&apss_funnel_out>; +- }; +- }; +- }; +- }; +- +- sdhc_2: sdhci@8804000 { +- compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; +- reg = <0 0x08804000 0 0x1000>; +- +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- +- clocks = <&gcc GCC_SDCC2_AHB_CLK>, +- <&gcc GCC_SDCC2_APPS_CLK>; +- clock-names = "iface", "core"; +- iommus = <&apps_smmu 0xa0 0xf>; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&sdhc2_opp_table>; +- +- status = "disabled"; +- +- sdhc2_opp_table: sdhc2-opp-table { +- compatible = "operating-points-v2"; +- +- opp-9600000 { +- opp-hz = /bits/ 64 <9600000>; +- required-opps = <&rpmhpd_opp_min_svs>; +- }; +- +- opp-19200000 { +- opp-hz = /bits/ 64 <19200000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- }; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- required-opps = <&rpmhpd_opp_svs>; +- }; +- +- opp-201500000 { +- opp-hz = /bits/ 64 <201500000>; +- required-opps = <&rpmhpd_opp_svs_l1>; +- }; +- }; +- }; +- +- qspi_opp_table: qspi-opp-table { +- compatible = "operating-points-v2"; +- +- opp-19200000 { +- opp-hz = /bits/ 64 <19200000>; +- required-opps = <&rpmhpd_opp_min_svs>; +- }; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- }; +- +- opp-150000000 { +- opp-hz = /bits/ 64 <150000000>; +- required-opps = <&rpmhpd_opp_svs>; +- }; +- +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- required-opps = <&rpmhpd_opp_nom>; +- }; +- }; +- +- qspi: spi@88df000 { +- compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; +- reg = <0 0x088df000 0 0x600>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, +- <&gcc GCC_QSPI_CORE_CLK>; +- clock-names = "iface", "core"; +- power-domains = <&rpmhpd SDM845_CX>; +- operating-points-v2 = <&qspi_opp_table>; +- status = "disabled"; +- }; +- +- slim: slim@171c0000 { +- compatible = "qcom,slim-ngd-v2.1.0"; +- reg = <0 0x171c0000 0 0x2c000>; +- interrupts = ; +- +- qcom,apps-ch-pipes = <0x780000>; +- qcom,ea-pc = <0x270>; +- status = "okay"; +- dmas = <&slimbam 3>, <&slimbam 4>, +- <&slimbam 5>, <&slimbam 6>; +- dma-names = "rx", "tx", "tx2", "rx2"; +- +- iommus = <&apps_smmu 0x1806 0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ngd@1 { +- reg = <1>; +- #address-cells = <2>; +- #size-cells = <0>; +- +- wcd9340_ifd: ifd@0{ +- compatible = "slim217,250"; +- reg = <0 0>; +- }; +- +- wcd9340: codec@1{ +- compatible = "slim217,250"; +- reg = <1 0>; +- slim-ifc-dev = <&wcd9340_ifd>; +- +- #sound-dai-cells = <1>; +- +- interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-controller; +- #interrupt-cells = <1>; +- +- #clock-cells = <0>; +- clock-frequency = <9600000>; +- clock-output-names = "mclk"; +- qcom,micbias1-millivolt = <1800>; +- qcom,micbias2-millivolt = <1800>; +- qcom,micbias3-millivolt = <1800>; +- qcom,micbias4-millivolt = <1800>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- wcdgpio: gpio-controller@42 { +- compatible = "qcom,wcd9340-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- reg = <0x42 0x2>; +- }; +- +- swm: swm@c85 { +- compatible = "qcom,soundwire-v1.3.0"; +- reg = <0xc85 0x40>; +- interrupts-extended = <&wcd9340 20>; +- +- qcom,dout-ports = <6>; +- qcom,din-ports = <2>; +- qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; +- qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; +- qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; +- +- #sound-dai-cells = <1>; +- clocks = <&wcd9340>; +- clock-names = "iface"; +- #address-cells = <2>; +- #size-cells = <0>; +- +- +- }; +- }; +- }; +- }; +- +- sound: sound { +- }; +- +- usb_1_hsphy: phy@88e2000 { +- compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; +- reg = <0 0x088e2000 0 0x400>; +- status = "disabled"; +- #phy-cells = <0>; +- +- clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, +- <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "cfg_ahb", "ref"; +- +- resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; +- +- nvmem-cells = <&qusb2p_hstx_trim>; +- }; +- +- usb_2_hsphy: phy@88e3000 { +- compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; +- reg = <0 0x088e3000 0 0x400>; +- status = "disabled"; +- #phy-cells = <0>; +- +- clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, +- <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "cfg_ahb", "ref"; +- +- resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; +- +- nvmem-cells = <&qusb2s_hstx_trim>; +- }; +- +- usb_1_qmpphy: phy@88e9000 { +- compatible = "qcom,sdm845-qmp-usb3-phy"; +- reg = <0 0x088e9000 0 0x18c>, +- <0 0x088e8000 0 0x10>; +- reg-names = "reg-base", "dp_com"; +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, +- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, +- <&gcc GCC_USB3_PRIM_CLKREF_CLK>, +- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; +- clock-names = "aux", "cfg_ahb", "ref", "com_aux"; +- +- resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, +- <&gcc GCC_USB3_PHY_PRIM_BCR>; +- reset-names = "phy", "common"; +- +- usb_1_ssphy: lanes@88e9200 { +- reg = <0 0x088e9200 0 0x128>, +- <0 0x088e9400 0 0x200>, +- <0 0x088e9c00 0 0x218>, +- <0 0x088e9600 0 0x128>, +- <0 0x088e9800 0 0x200>, +- <0 0x088e9a00 0 0x100>; +- #clock-cells = <0>; +- #phy-cells = <0>; +- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; +- clock-names = "pipe0"; +- clock-output-names = "usb3_phy_pipe_clk_src"; +- }; +- }; +- +- usb_2_qmpphy: phy@88eb000 { +- compatible = "qcom,sdm845-qmp-usb3-uni-phy"; +- reg = <0 0x088eb000 0 0x18c>; +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, +- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, +- <&gcc GCC_USB3_SEC_CLKREF_CLK>, +- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; +- clock-names = "aux", "cfg_ahb", "ref", "com_aux"; +- +- resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, +- <&gcc GCC_USB3_PHY_SEC_BCR>; +- reset-names = "phy", "common"; +- +- usb_2_ssphy: lane@88eb200 { +- reg = <0 0x088eb200 0 0x128>, +- <0 0x088eb400 0 0x1fc>, +- <0 0x088eb800 0 0x218>, +- <0 0x088eb600 0 0x70>; +- #clock-cells = <0>; +- #phy-cells = <0>; +- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; +- clock-names = "pipe0"; +- clock-output-names = "usb3_uni_phy_pipe_clk_src"; +- }; +- }; +- +- usb_1: usb@a6f8800 { +- compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; +- reg = <0 0x0a6f8800 0 0x400>; +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- dma-ranges; +- +- clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, +- <&gcc GCC_USB30_PRIM_MASTER_CLK>, +- <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, +- <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_PRIM_SLEEP_CLK>; +- clock-names = "cfg_noc", "core", "iface", "mock_utmi", +- "sleep"; +- +- assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_PRIM_MASTER_CLK>; +- assigned-clock-rates = <19200000>, <150000000>; +- +- interrupts = , +- , +- , +- ; +- interrupt-names = "hs_phy_irq", "ss_phy_irq", +- "dm_hs_phy_irq", "dp_hs_phy_irq"; +- +- power-domains = <&gcc USB30_PRIM_GDSC>; +- +- resets = <&gcc GCC_USB30_PRIM_BCR>; +- +- interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; +- interconnect-names = "usb-ddr", "apps-usb"; +- +- usb_1_dwc3: dwc3@a600000 { +- compatible = "snps,dwc3"; +- reg = <0 0x0a600000 0 0xcd00>; +- interrupts = ; +- iommus = <&apps_smmu 0x740 0>; +- snps,dis_u2_susphy_quirk; +- snps,dis_enblslpm_quirk; +- phys = <&usb_1_hsphy>, <&usb_1_ssphy>; +- phy-names = "usb2-phy", "usb3-phy"; +- }; +- }; +- +- usb_2: usb@a8f8800 { +- compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; +- reg = <0 0x0a8f8800 0 0x400>; +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- dma-ranges; +- +- clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, +- <&gcc GCC_USB30_SEC_MASTER_CLK>, +- <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, +- <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_SEC_SLEEP_CLK>; +- clock-names = "cfg_noc", "core", "iface", "mock_utmi", +- "sleep"; +- +- assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_SEC_MASTER_CLK>; +- assigned-clock-rates = <19200000>, <150000000>; +- +- interrupts = , +- , +- , +- ; +- interrupt-names = "hs_phy_irq", "ss_phy_irq", +- "dm_hs_phy_irq", "dp_hs_phy_irq"; +- +- power-domains = <&gcc USB30_SEC_GDSC>; +- +- resets = <&gcc GCC_USB30_SEC_BCR>; +- +- interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; +- interconnect-names = "usb-ddr", "apps-usb"; +- +- usb_2_dwc3: dwc3@a800000 { +- compatible = "snps,dwc3"; +- reg = <0 0x0a800000 0 0xcd00>; +- interrupts = ; +- iommus = <&apps_smmu 0x760 0>; +- snps,dis_u2_susphy_quirk; +- snps,dis_enblslpm_quirk; +- phys = <&usb_2_hsphy>, <&usb_2_ssphy>; +- phy-names = "usb2-phy", "usb3-phy"; +- }; +- }; +- +- venus: video-codec@aa00000 { +- compatible = "qcom,sdm845-venus-v2"; +- reg = <0 0x0aa00000 0 0xff000>; +- interrupts = ; +- power-domains = <&videocc VENUS_GDSC>, +- <&videocc VCODEC0_GDSC>, +- <&videocc VCODEC1_GDSC>, +- <&rpmhpd SDM845_CX>; +- power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; +- operating-points-v2 = <&venus_opp_table>; +- clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, +- <&videocc VIDEO_CC_VENUS_AHB_CLK>, +- <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, +- <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, +- <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, +- <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, +- <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; +- clock-names = "core", "iface", "bus", +- "vcodec0_core", "vcodec0_bus", +- "vcodec1_core", "vcodec1_bus"; +- iommus = <&apps_smmu 0x10a0 0x8>, +- <&apps_smmu 0x10b0 0x0>; +- memory-region = <&venus_mem>; +- interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, +- <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; +- interconnect-names = "video-mem", "cpu-cfg"; +- +- video-core0 { +- compatible = "venus-decoder"; +- }; +- +- video-core1 { +- compatible = "venus-encoder"; +- }; +- +- venus_opp_table: venus-opp-table { +- compatible = "operating-points-v2"; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- required-opps = <&rpmhpd_opp_min_svs>; +- }; +- +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- }; +- +- opp-320000000 { +- opp-hz = /bits/ 64 <320000000>; +- required-opps = <&rpmhpd_opp_svs>; +- }; +- +- opp-380000000 { +- opp-hz = /bits/ 64 <380000000>; +- required-opps = <&rpmhpd_opp_svs_l1>; +- }; +- +- opp-444000000 { +- opp-hz = /bits/ 64 <444000000>; +- required-opps = <&rpmhpd_opp_nom>; +- }; +- +- opp-533000097 { +- opp-hz = /bits/ 64 <533000097>; +- required-opps = <&rpmhpd_opp_turbo>; +- }; +- }; +- }; +- +- videocc: clock-controller@ab00000 { +- compatible = "qcom,sdm845-videocc"; +- reg = <0 0x0ab00000 0 0x10000>; +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "bi_tcxo"; +- #clock-cells = <1>; +- #power-domain-cells = <1>; +- #reset-cells = <1>; +- }; +- +- camss: camss@a00000 { +- compatible = "qcom,sdm845-camss"; +- +- reg = <0 0xacb3000 0 0x1000>, +- <0 0xacba000 0 0x1000>, +- <0 0xacc8000 0 0x1000>, +- <0 0xac65000 0 0x1000>, +- <0 0xac66000 0 0x1000>, +- <0 0xac67000 0 0x1000>, +- <0 0xac68000 0 0x1000>, +- <0 0xacaf000 0 0x4000>, +- <0 0xacb6000 0 0x4000>, +- <0 0xacc4000 0 0x4000>; +- reg-names = "csid0", +- "csid1", +- "csid2", +- "csiphy0", +- "csiphy1", +- "csiphy2", +- "csiphy3", +- "vfe0", +- "vfe1", +- "vfe_lite"; +- +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "csid0", +- "csid1", +- "csid2", +- "csiphy0", +- "csiphy1", +- "csiphy2", +- "csiphy3", +- "vfe0", +- "vfe1", +- "vfe_lite"; +- +- power-domains = <&clock_camcc IFE_0_GDSC>, +- <&clock_camcc IFE_1_GDSC>, +- <&clock_camcc TITAN_TOP_GDSC>; +- +- clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, +- <&clock_camcc CAM_CC_CPAS_AHB_CLK>, +- <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, +- <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, +- <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, +- <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, +- <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, +- <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, +- <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, +- <&clock_camcc CAM_CC_CSIPHY0_CLK>, +- <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, +- <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, +- <&clock_camcc CAM_CC_CSIPHY1_CLK>, +- <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, +- <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, +- <&clock_camcc CAM_CC_CSIPHY2_CLK>, +- <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, +- <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, +- <&clock_camcc CAM_CC_CSIPHY3_CLK>, +- <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, +- <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, +- <&gcc GCC_CAMERA_AHB_CLK>, +- <&gcc GCC_CAMERA_AXI_CLK>, +- <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, +- <&clock_camcc CAM_CC_SOC_AHB_CLK>, +- <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, +- <&clock_camcc CAM_CC_IFE_0_CLK>, +- <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, +- <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, +- <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, +- <&clock_camcc CAM_CC_IFE_1_CLK>, +- <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, +- <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, +- <&clock_camcc CAM_CC_IFE_LITE_CLK>, +- <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, +- <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; +- clock-names = "camnoc_axi", +- "cpas_ahb", +- "cphy_rx_src", +- "csi0", +- "csi0_src", +- "csi1", +- "csi1_src", +- "csi2", +- "csi2_src", +- "csiphy0", +- "csiphy0_timer", +- "csiphy0_timer_src", +- "csiphy1", +- "csiphy1_timer", +- "csiphy1_timer_src", +- "csiphy2", +- "csiphy2_timer", +- "csiphy2_timer_src", +- "csiphy3", +- "csiphy3_timer", +- "csiphy3_timer_src", +- "gcc_camera_ahb", +- "gcc_camera_axi", +- "slow_ahb_src", +- "soc_ahb", +- "vfe0_axi", +- "vfe0", +- "vfe0_cphy_rx", +- "vfe0_src", +- "vfe1_axi", +- "vfe1", +- "vfe1_cphy_rx", +- "vfe1_src", +- "vfe_lite", +- "vfe_lite_cphy_rx", +- "vfe_lite_src"; +- +- iommus = <&apps_smmu 0x0808 0x0>, +- <&apps_smmu 0x0810 0x8>, +- <&apps_smmu 0x0c08 0x0>, +- <&apps_smmu 0x0c10 0x8>; +- +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- cci: cci@ac4a000 { +- compatible = "qcom,sdm845-cci"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <0 0x0ac4a000 0 0x4000>; +- interrupts = ; +- power-domains = <&clock_camcc TITAN_TOP_GDSC>; +- +- clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, +- <&clock_camcc CAM_CC_SOC_AHB_CLK>, +- <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, +- <&clock_camcc CAM_CC_CPAS_AHB_CLK>, +- <&clock_camcc CAM_CC_CCI_CLK>, +- <&clock_camcc CAM_CC_CCI_CLK_SRC>; +- clock-names = "camnoc_axi", +- "soc_ahb", +- "slow_ahb_src", +- "cpas_ahb", +- "cci", +- "cci_src"; +- +- assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, +- <&clock_camcc CAM_CC_CCI_CLK>; +- assigned-clock-rates = <80000000>, <37500000>; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&cci0_default &cci1_default>; +- pinctrl-1 = <&cci0_sleep &cci1_sleep>; +- +- status = "disabled"; +- +- cci_i2c0: i2c-bus@0 { +- reg = <0>; +- clock-frequency = <1000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- cci_i2c1: i2c-bus@1 { +- reg = <1>; +- clock-frequency = <1000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- clock_camcc: clock-controller@ad00000 { +- compatible = "qcom,sdm845-camcc"; +- reg = <0 0x0ad00000 0 0x10000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- }; +- +- dsi_opp_table: dsi-opp-table { +- compatible = "operating-points-v2"; +- +- opp-19200000 { +- opp-hz = /bits/ 64 <19200000>; +- required-opps = <&rpmhpd_opp_min_svs>; +- }; +- +- opp-180000000 { +- opp-hz = /bits/ 64 <180000000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- }; +- +- opp-275000000 { +- opp-hz = /bits/ 64 <275000000>; +- required-opps = <&rpmhpd_opp_svs>; +- }; +- +- opp-328580000 { +- opp-hz = /bits/ 64 <328580000>; +- required-opps = <&rpmhpd_opp_svs_l1>; +- }; +- +- opp-358000000 { +- opp-hz = /bits/ 64 <358000000>; +- required-opps = <&rpmhpd_opp_nom>; +- }; +- }; +- +- mdss: mdss@ae00000 { +- compatible = "qcom,sdm845-mdss"; +- reg = <0 0x0ae00000 0 0x1000>; +- reg-names = "mdss"; +- +- power-domains = <&dispcc MDSS_GDSC>; +- +- clocks = <&gcc GCC_DISP_AHB_CLK>, +- <&dispcc DISP_CC_MDSS_MDP_CLK>; +- clock-names = "iface", "core"; +- +- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; +- assigned-clock-rates = <300000000>; +- +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, +- <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; +- interconnect-names = "mdp0-mem", "mdp1-mem"; +- +- iommus = <&apps_smmu 0x880 0x8>, +- <&apps_smmu 0xc80 0x8>; +- +- status = "disabled"; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- mdss_mdp: mdp@ae01000 { +- compatible = "qcom,sdm845-dpu"; +- reg = <0 0x0ae01000 0 0x8f000>, +- <0 0x0aeb0000 0 0x2008>; +- reg-names = "mdp", "vbif"; +- +- clocks = <&gcc GCC_DISP_AXI_CLK>, +- <&dispcc DISP_CC_MDSS_AHB_CLK>, +- <&dispcc DISP_CC_MDSS_AXI_CLK>, +- <&dispcc DISP_CC_MDSS_MDP_CLK>, +- <&dispcc DISP_CC_MDSS_VSYNC_CLK>; +- clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; +- +- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, +- <&dispcc DISP_CC_MDSS_VSYNC_CLK>; +- assigned-clock-rates = <300000000>, +- <19200000>; +- operating-points-v2 = <&mdp_opp_table>; +- power-domains = <&rpmhpd SDM845_CX>; +- +- interrupt-parent = <&mdss>; +- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; +- +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dpu_intf1_out: endpoint { +- remote-endpoint = <&dsi0_in>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- dpu_intf2_out: endpoint { +- remote-endpoint = <&dsi1_in>; +- }; +- }; +- }; +- +- mdp_opp_table: mdp-opp-table { +- compatible = "operating-points-v2"; +- +- opp-19200000 { +- opp-hz = /bits/ 64 <19200000>; +- required-opps = <&rpmhpd_opp_min_svs>; +- }; +- +- opp-171428571 { +- opp-hz = /bits/ 64 <171428571>; +- required-opps = <&rpmhpd_opp_low_svs>; +- }; +- +- opp-344000000 { +- opp-hz = /bits/ 64 <344000000>; +- required-opps = <&rpmhpd_opp_svs_l1>; +- }; +- +- opp-430000000 { +- opp-hz = /bits/ 64 <430000000>; +- required-opps = <&rpmhpd_opp_nom>; +- }; +- }; +- }; +- +- dsi0: dsi@ae94000 { +- compatible = "qcom,mdss-dsi-ctrl"; +- reg = <0 0x0ae94000 0 0x400>; +- reg-names = "dsi_ctrl"; +- +- interrupt-parent = <&mdss>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +- +- clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, +- <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, +- <&dispcc DISP_CC_MDSS_PCLK0_CLK>, +- <&dispcc DISP_CC_MDSS_ESC0_CLK>, +- <&dispcc DISP_CC_MDSS_AHB_CLK>, +- <&dispcc DISP_CC_MDSS_AXI_CLK>; +- clock-names = "byte", +- "byte_intf", +- "pixel", +- "core", +- "iface", +- "bus"; +- assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; +- assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; +- +- operating-points-v2 = <&dsi_opp_table>; +- power-domains = <&rpmhpd SDM845_CX>; +- +- phys = <&dsi0_phy>; +- phy-names = "dsi"; +- +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dsi0_in: endpoint { +- remote-endpoint = <&dpu_intf1_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- dsi0_out: endpoint { +- }; +- }; +- }; +- }; +- +- dsi0_phy: dsi-phy@ae94400 { +- compatible = "qcom,dsi-phy-10nm"; +- reg = <0 0x0ae94400 0 0x200>, +- <0 0x0ae94600 0 0x280>, +- <0 0x0ae94a00 0 0x1e0>; +- reg-names = "dsi_phy", +- "dsi_phy_lane", +- "dsi_pll"; +- +- #clock-cells = <1>; +- #phy-cells = <0>; +- +- clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, +- <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "iface", "ref"; +- +- status = "disabled"; +- }; +- +- dsi1: dsi@ae96000 { +- compatible = "qcom,mdss-dsi-ctrl"; +- reg = <0 0x0ae96000 0 0x400>; +- reg-names = "dsi_ctrl"; +- +- interrupt-parent = <&mdss>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; +- +- clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, +- <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, +- <&dispcc DISP_CC_MDSS_PCLK1_CLK>, +- <&dispcc DISP_CC_MDSS_ESC1_CLK>, +- <&dispcc DISP_CC_MDSS_AHB_CLK>, +- <&dispcc DISP_CC_MDSS_AXI_CLK>; +- clock-names = "byte", +- "byte_intf", +- "pixel", +- "core", +- "iface", +- "bus"; +- assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; +- assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; +- +- operating-points-v2 = <&dsi_opp_table>; +- power-domains = <&rpmhpd SDM845_CX>; +- +- phys = <&dsi1_phy>; +- phy-names = "dsi"; +- +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dsi1_in: endpoint { +- remote-endpoint = <&dpu_intf2_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- dsi1_out: endpoint { +- }; +- }; +- }; +- }; +- +- dsi1_phy: dsi-phy@ae96400 { +- compatible = "qcom,dsi-phy-10nm"; +- reg = <0 0x0ae96400 0 0x200>, +- <0 0x0ae96600 0 0x280>, +- <0 0x0ae96a00 0 0x10e>; +- reg-names = "dsi_phy", +- "dsi_phy_lane", +- "dsi_pll"; +- +- #clock-cells = <1>; +- #phy-cells = <0>; +- +- clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, +- <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "iface", "ref"; +- +- status = "disabled"; +- }; +- }; +- +- gpu: gpu@5000000 { +- compatible = "qcom,adreno-630.2", "qcom,adreno"; +- #stream-id-cells = <16>; +- +- reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; +- reg-names = "kgsl_3d0_reg_memory", "cx_mem"; +- +- /* +- * Look ma, no clocks! The GPU clocks and power are +- * controlled entirely by the GMU +- */ +- +- interrupts = ; +- +- iommus = <&adreno_smmu 0>; +- +- operating-points-v2 = <&gpu_opp_table>; +- +- qcom,gmu = <&gmu>; +- +- interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; +- interconnect-names = "gfx-mem"; +- +- gpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-710000000 { +- opp-hz = /bits/ 64 <710000000>; +- opp-level = ; +- opp-peak-kBps = <7216000>; +- }; +- +- opp-675000000 { +- opp-hz = /bits/ 64 <675000000>; +- opp-level = ; +- opp-peak-kBps = <7216000>; +- }; +- +- opp-596000000 { +- opp-hz = /bits/ 64 <596000000>; +- opp-level = ; +- opp-peak-kBps = <6220000>; +- }; +- +- opp-520000000 { +- opp-hz = /bits/ 64 <520000000>; +- opp-level = ; +- opp-peak-kBps = <6220000>; +- }; +- +- opp-414000000 { +- opp-hz = /bits/ 64 <414000000>; +- opp-level = ; +- opp-peak-kBps = <4068000>; +- }; +- +- opp-342000000 { +- opp-hz = /bits/ 64 <342000000>; +- opp-level = ; +- opp-peak-kBps = <2724000>; +- }; +- +- opp-257000000 { +- opp-hz = /bits/ 64 <257000000>; +- opp-level = ; +- opp-peak-kBps = <1648000>; +- }; +- }; +- }; +- +- adreno_smmu: iommu@5040000 { +- compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; +- reg = <0 0x5040000 0 0x10000>; +- #iommu-cells = <1>; +- #global-interrupts = <2>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, +- <&gcc GCC_GPU_CFG_AHB_CLK>; +- clock-names = "bus", "iface"; +- +- power-domains = <&gpucc GPU_CX_GDSC>; +- }; +- +- gmu: gmu@506a000 { +- compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; +- +- reg = <0 0x506a000 0 0x30000>, +- <0 0xb280000 0 0x10000>, +- <0 0xb480000 0 0x10000>; +- reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; +- +- interrupts = , +- ; +- interrupt-names = "hfi", "gmu"; +- +- clocks = <&gpucc GPU_CC_CX_GMU_CLK>, +- <&gpucc GPU_CC_CXO_CLK>, +- <&gcc GCC_DDRSS_GPU_AXI_CLK>, +- <&gcc GCC_GPU_MEMNOC_GFX_CLK>; +- clock-names = "gmu", "cxo", "axi", "memnoc"; +- +- power-domains = <&gpucc GPU_CX_GDSC>, +- <&gpucc GPU_GX_GDSC>; +- power-domain-names = "cx", "gx"; +- +- iommus = <&adreno_smmu 5>; +- +- operating-points-v2 = <&gmu_opp_table>; +- +- gmu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-level = ; +- }; +- +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- opp-level = ; +- }; +- }; +- }; +- +- dispcc: clock-controller@af00000 { +- compatible = "qcom,sdm845-dispcc"; +- reg = <0 0x0af00000 0 0x10000>; +- clocks = <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_DISP_GPLL0_CLK_SRC>, +- <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, +- <&dsi0_phy 0>, +- <&dsi0_phy 1>, +- <&dsi1_phy 0>, +- <&dsi1_phy 1>, +- <0>, +- <0>; +- clock-names = "bi_tcxo", +- "gcc_disp_gpll0_clk_src", +- "gcc_disp_gpll0_div_clk_src", +- "dsi0_phy_pll_out_byteclk", +- "dsi0_phy_pll_out_dsiclk", +- "dsi1_phy_pll_out_byteclk", +- "dsi1_phy_pll_out_dsiclk", +- "dp_link_clk_divsel_ten", +- "dp_vco_divided_clk_src_mux"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- }; +- +- pdc_intc: interrupt-controller@b220000 { +- compatible = "qcom,sdm845-pdc", "qcom,pdc"; +- reg = <0 0x0b220000 0 0x30000>; +- qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; +- #interrupt-cells = <2>; +- interrupt-parent = <&intc>; +- interrupt-controller; +- }; +- +- pdc_reset: reset-controller@b2e0000 { +- compatible = "qcom,sdm845-pdc-global"; +- reg = <0 0x0b2e0000 0 0x20000>; +- #reset-cells = <1>; +- }; +- +- tsens0: thermal-sensor@c263000 { +- compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; +- reg = <0 0x0c263000 0 0x1ff>, /* TM */ +- <0 0x0c222000 0 0x1ff>; /* SROT */ +- #qcom,sensors = <13>; +- interrupts = , +- ; +- interrupt-names = "uplow", "critical"; +- #thermal-sensor-cells = <1>; +- }; +- +- tsens1: thermal-sensor@c265000 { +- compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; +- reg = <0 0x0c265000 0 0x1ff>, /* TM */ +- <0 0x0c223000 0 0x1ff>; /* SROT */ +- #qcom,sensors = <8>; +- interrupts = , +- ; +- interrupt-names = "uplow", "critical"; +- #thermal-sensor-cells = <1>; +- }; +- +- aoss_reset: reset-controller@c2a0000 { +- compatible = "qcom,sdm845-aoss-cc"; +- reg = <0 0x0c2a0000 0 0x31000>; +- #reset-cells = <1>; +- }; +- +- aoss_qmp: power-controller@c300000 { +- compatible = "qcom,sdm845-aoss-qmp"; +- reg = <0 0x0c300000 0 0x100000>; +- interrupts = ; +- mboxes = <&apss_shared 0>; +- +- #clock-cells = <0>; +- #power-domain-cells = <1>; +- +- cx_cdev: cx { +- #cooling-cells = <2>; +- }; +- +- ebi_cdev: ebi { +- #cooling-cells = <2>; +- }; +- }; +- +- spmi_bus: spmi@c440000 { +- compatible = "qcom,spmi-pmic-arb"; +- reg = <0 0x0c440000 0 0x1100>, +- <0 0x0c600000 0 0x2000000>, +- <0 0x0e600000 0 0x100000>, +- <0 0x0e700000 0 0xa0000>, +- <0 0x0c40a000 0 0x26000>; +- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; +- interrupt-names = "periph_irq"; +- interrupts = ; +- qcom,ee = <0>; +- qcom,channel = <0>; +- #address-cells = <2>; +- #size-cells = <0>; +- interrupt-controller; +- #interrupt-cells = <4>; +- cell-index = <0>; +- }; +- +- imem@146bf000 { +- compatible = "simple-mfd"; +- reg = <0 0x146bf000 0 0x1000>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0 0 0x146bf000 0x1000>; +- +- pil-reloc@94c { +- compatible = "qcom,pil-reloc-info"; +- reg = <0x94c 0xc8>; +- }; +- }; +- +- apps_smmu: iommu@15000000 { +- compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; +- reg = <0 0x15000000 0 0x80000>; +- #iommu-cells = <2>; +- #global-interrupts = <1>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- }; +- +- lpasscc: clock-controller@17014000 { +- compatible = "qcom,sdm845-lpasscc"; +- reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; +- reg-names = "cc", "qdsp6ss"; +- #clock-cells = <1>; +- status = "disabled"; +- }; +- +- gladiator_noc: interconnect@17900000 { +- compatible = "qcom,sdm845-gladiator-noc"; +- reg = <0 0x17900000 0 0xd080>; +- #interconnect-cells = <2>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- watchdog@17980000 { +- compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; +- reg = <0 0x17980000 0 0x1000>; +- clocks = <&sleep_clk>; +- interrupts = ; +- }; +- +- apss_shared: mailbox@17990000 { +- compatible = "qcom,sdm845-apss-shared"; +- reg = <0 0x17990000 0 0x1000>; +- #mbox-cells = <1>; +- }; +- +- apps_rsc: rsc@179c0000 { +- label = "apps_rsc"; +- compatible = "qcom,rpmh-rsc"; +- reg = <0 0x179c0000 0 0x10000>, +- <0 0x179d0000 0 0x10000>, +- <0 0x179e0000 0 0x10000>; +- reg-names = "drv-0", "drv-1", "drv-2"; +- interrupts = , +- , +- ; +- qcom,tcs-offset = <0xd00>; +- qcom,drv-id = <2>; +- qcom,tcs-config = , +- , +- , +- ; +- +- apps_bcm_voter: bcm-voter { +- compatible = "qcom,bcm-voter"; +- }; +- +- rpmhcc: clock-controller { +- compatible = "qcom,sdm845-rpmh-clk"; +- #clock-cells = <1>; +- clock-names = "xo"; +- clocks = <&xo_board>; +- }; +- +- rpmhpd: power-controller { +- compatible = "qcom,sdm845-rpmhpd"; +- #power-domain-cells = <1>; +- operating-points-v2 = <&rpmhpd_opp_table>; +- +- rpmhpd_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- rpmhpd_opp_ret: opp1 { +- opp-level = ; +- }; +- +- rpmhpd_opp_min_svs: opp2 { +- opp-level = ; +- }; +- +- rpmhpd_opp_low_svs: opp3 { +- opp-level = ; +- }; +- +- rpmhpd_opp_svs: opp4 { +- opp-level = ; +- }; +- +- rpmhpd_opp_svs_l1: opp5 { +- opp-level = ; +- }; +- +- rpmhpd_opp_nom: opp6 { +- opp-level = ; +- }; +- +- rpmhpd_opp_nom_l1: opp7 { +- opp-level = ; +- }; +- +- rpmhpd_opp_nom_l2: opp8 { +- opp-level = ; +- }; +- +- rpmhpd_opp_turbo: opp9 { +- opp-level = ; +- }; +- +- rpmhpd_opp_turbo_l1: opp10 { +- opp-level = ; +- }; +- }; +- }; +- }; +- +- intc: interrupt-controller@17a00000 { +- compatible = "arm,gic-v3"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0 0x17a00000 0 0x10000>, /* GICD */ +- <0 0x17a60000 0 0x100000>; /* GICR * 8 */ +- interrupts = ; +- +- msi-controller@17a40000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0 0x17a40000 0 0x20000>; +- status = "disabled"; +- }; +- }; +- +- slimbam: dma-controller@17184000 { +- compatible = "qcom,bam-v1.7.0"; +- qcom,controlled-remotely; +- reg = <0 0x17184000 0 0x2a000>; +- num-channels = <31>; +- interrupts = ; +- #dma-cells = <1>; +- qcom,ee = <1>; +- qcom,num-ees = <2>; +- iommus = <&apps_smmu 0x1806 0x0>; +- }; +- +- timer@17c90000 { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- compatible = "arm,armv7-timer-mem"; +- reg = <0 0x17c90000 0 0x1000>; +- +- frame@17ca0000 { +- frame-number = <0>; +- interrupts = , +- ; +- reg = <0 0x17ca0000 0 0x1000>, +- <0 0x17cb0000 0 0x1000>; +- }; +- +- frame@17cc0000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0 0x17cc0000 0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17cd0000 { +- frame-number = <2>; +- interrupts = ; +- reg = <0 0x17cd0000 0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17ce0000 { +- frame-number = <3>; +- interrupts = ; +- reg = <0 0x17ce0000 0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17cf0000 { +- frame-number = <4>; +- interrupts = ; +- reg = <0 0x17cf0000 0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17d00000 { +- frame-number = <5>; +- interrupts = ; +- reg = <0 0x17d00000 0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17d10000 { +- frame-number = <6>; +- interrupts = ; +- reg = <0 0x17d10000 0 0x1000>; +- status = "disabled"; +- }; +- }; +- +- osm_l3: interconnect@17d41000 { +- compatible = "qcom,sdm845-osm-l3"; +- reg = <0 0x17d41000 0 0x1400>; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; +- clock-names = "xo", "alternate"; +- +- #interconnect-cells = <1>; +- }; +- +- cpufreq_hw: cpufreq@17d43000 { +- compatible = "qcom,cpufreq-hw"; +- reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; +- reg-names = "freq-domain0", "freq-domain1"; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; +- clock-names = "xo", "alternate"; +- +- #freq-domain-cells = <1>; +- }; +- +- wifi: wifi@18800000 { +- compatible = "qcom,wcn3990-wifi"; +- status = "disabled"; +- reg = <0 0x18800000 0 0x800000>; +- reg-names = "membase"; +- memory-region = <&wlan_msa_mem>; +- clock-names = "cxo_ref_clk_pin"; +- clocks = <&rpmhcc RPMH_RF_CLK2>; +- interrupts = +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- iommus = <&apps_smmu 0x0040 0x1>; +- }; +- }; +- +- thermal-zones { +- cpu0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 1>; +- +- trips { +- cpu0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu0_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu0_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu0_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu0_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 2>; +- +- trips { +- cpu1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu1_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu1_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu1_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu1_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 3>; +- +- trips { +- cpu2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu2_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu2_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu2_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu2_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 4>; +- +- trips { +- cpu3_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu3_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu3_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu3_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu3_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu4-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 7>; +- +- trips { +- cpu4_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu4_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu4_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu4_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu4_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu5-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 8>; +- +- trips { +- cpu5_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu5_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu5_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu5_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu5_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu6-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 9>; +- +- trips { +- cpu6_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu6_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu6_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu6_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu6_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu7-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 10>; +- +- trips { +- cpu7_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu7_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu7_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu7_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu7_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- aoss0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 0>; +- +- trips { +- aoss0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- cluster0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 5>; +- +- trips { +- cluster0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- cluster0_crit: cluster0_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cluster1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 6>; +- +- trips { +- cluster1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- cluster1_crit: cluster1_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- gpu-thermal-top { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 11>; +- +- trips { +- gpu1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- gpu-thermal-bottom { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 12>; +- +- trips { +- gpu2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- aoss1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 0>; +- +- trips { +- aoss1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- q6-modem-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 1>; +- +- trips { +- q6_modem_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- mem-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 2>; +- +- trips { +- mem_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- wlan-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 3>; +- +- trips { +- wlan_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- q6-hvx-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 4>; +- +- trips { +- q6_hvx_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- camera-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 5>; +- +- trips { +- camera_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- video-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 6>; +- +- trips { +- video_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- modem-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 7>; +- +- trips { +- modem_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm850-lenovo-yoga-c630.dts b/scripts/dtc/include-prefixes/arm64/qcom/sdm850-lenovo-yoga-c630.dts +deleted file mode 100644 +index 617a634ac905..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm850-lenovo-yoga-c630.dts ++++ /dev/null +@@ -1,795 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Lenovo Yoga C630 +- * +- * Copyright (c) 2019, Linaro Ltd. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include "sdm850.dtsi" +-#include "pm8998.dtsi" +- +-/* +- * Update following upstream (sdm845.dtsi) reserved +- * memory mappings for firmware loading to succeed +- * and enable the IPA device. +- */ +-/delete-node/ &ipa_fw_mem; +-/delete-node/ &ipa_gsi_mem; +-/delete-node/ &gpu_mem; +-/delete-node/ &adsp_mem; +-/delete-node/ &wlan_msa_mem; +- +-/ { +- model = "Lenovo Yoga C630"; +- compatible = "lenovo,yoga-c630", "qcom,sdm845"; +- +- aliases { +- hsuart0 = &uart6; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&lid_pin_active>, <&mode_pin_active>; +- +- lid { +- gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>; +- linux,input-type = ; +- linux,code = ; +- wakeup-source; +- wakeup-event-action = ; +- }; +- +- mode { +- gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; +- linux,input-type = ; +- linux,code = ; +- }; +- }; +- +- panel { +- compatible = "boe,nv133fhm-n61"; +- no-hpd; +- +- ports { +- port { +- panel_in_edp: endpoint { +- remote-endpoint = <&sn65dsi86_out>; +- }; +- }; +- }; +- }; +- +- /* Reserved memory changes for IPA */ +- reserved-memory { +- wlan_msa_mem: memory@8c400000 { +- reg = <0 0x8c400000 0 0x100000>; +- no-map; +- }; +- +- gpu_mem: memory@8c515000 { +- reg = <0 0x8c515000 0 0x2000>; +- no-map; +- }; +- +- ipa_fw_mem: memory@8c517000 { +- reg = <0 0x8c517000 0 0x5a000>; +- no-map; +- }; +- +- adsp_mem: memory@8c600000 { +- reg = <0 0x8c600000 0 0x1a00000>; +- no-map; +- }; +- }; +- +- sn65dsi86_refclk: sn65dsi86-refclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- +- clock-frequency = <19200000>; +- }; +-}; +- +-&adsp_pas { +- firmware-name = "qcom/LENOVO/81JL/qcadsp850.mbn"; +- status = "okay"; +-}; +- +-&apps_rsc { +- pm8998-rpmh-regulators { +- compatible = "qcom,pm8998-rpmh-regulators"; +- qcom,pmic-id = "a"; +- +- vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; +- vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; +- +- vreg_s2a_1p125: smps2 { +- }; +- +- vreg_s3a_1p35: smps3 { +- regulator-min-microvolt = <1352000>; +- regulator-max-microvolt = <1352000>; +- regulator-initial-mode = ; +- }; +- +- vreg_s4a_1p8: smps4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_s5a_2p04: smps5 { +- regulator-min-microvolt = <2040000>; +- regulator-max-microvolt = <2040000>; +- regulator-initial-mode = ; +- }; +- +- vreg_s7a_1p025: smps7 { +- }; +- +- vdd_qusb_hs0: +- vdda_hp_pcie_core: +- vdda_mipi_csi0_0p9: +- vdda_mipi_csi1_0p9: +- vdda_mipi_csi2_0p9: +- vdda_mipi_dsi0_pll: +- vdda_mipi_dsi1_pll: +- vdda_qlink_lv: +- vdda_qlink_lv_ck: +- vdda_qrefs_0p875: +- vdda_pcie_core: +- vdda_pll_cc_ebi01: +- vdda_pll_cc_ebi23: +- vdda_sp_sensor: +- vdda_ufs1_core: +- vdda_ufs2_core: +- vdda_usb1_ss_core: +- vdda_usb2_ss_core: +- vreg_l1a_0p875: ldo1 { +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_10: +- vreg_l2a_1p2: ldo2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- regulator-always-on; +- }; +- +- vreg_l3a_1p0: ldo3 { +- }; +- +- vdd_wcss_cx: +- vdd_wcss_mx: +- vdda_wcss_pll: +- vreg_l5a_0p8: ldo5 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_13: +- vreg_l6a_1p8: ldo6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7a_1p8: ldo7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l8a_1p2: ldo8 { +- }; +- +- vreg_l9a_1p8: ldo9 { +- }; +- +- vreg_l10a_1p8: ldo10 { +- }; +- +- vreg_l11a_1p0: ldo11 { +- }; +- +- vdd_qfprom: +- vdd_qfprom_sp: +- vdda_apc1_cs_1p8: +- vdda_gfx_cs_1p8: +- vdda_qrefs_1p8: +- vdda_qusb_hs0_1p8: +- vddpx_11: +- vreg_l12a_1p8: ldo12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_2: +- vreg_l13a_2p95: ldo13 { +- }; +- +- vreg_l14a_1p88: ldo14 { +- regulator-min-microvolt = <1880000>; +- regulator-max-microvolt = <1880000>; +- regulator-initial-mode = ; +- regulator-always-on; +- }; +- +- vreg_l15a_1p8: ldo15 { +- }; +- +- vreg_l16a_2p7: ldo16 { +- }; +- +- vreg_l17a_1p3: ldo17 { +- regulator-min-microvolt = <1304000>; +- regulator-max-microvolt = <1304000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l18a_2p7: ldo18 { +- }; +- +- vreg_l19a_3p0: ldo19 { +- regulator-min-microvolt = <3100000>; +- regulator-max-microvolt = <3108000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l20a_2p95: ldo20 { +- regulator-min-microvolt = <2960000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l21a_2p95: ldo21 { +- }; +- +- vreg_l22a_2p85: ldo22 { +- }; +- +- vreg_l23a_3p3: ldo23 { +- }; +- +- vdda_qusb_hs0_3p1: +- vreg_l24a_3p075: ldo24 { +- regulator-min-microvolt = <3075000>; +- regulator-max-microvolt = <3083000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l25a_3p3: ldo25 { +- regulator-min-microvolt = <3104000>; +- regulator-max-microvolt = <3112000>; +- regulator-initial-mode = ; +- }; +- +- vdda_hp_pcie_1p2: +- vdda_hv_ebi0: +- vdda_hv_ebi1: +- vdda_hv_ebi2: +- vdda_hv_ebi3: +- vdda_mipi_csi_1p25: +- vdda_mipi_dsi0_1p2: +- vdda_mipi_dsi1_1p2: +- vdda_pcie_1p2: +- vdda_ufs1_1p2: +- vdda_ufs2_1p2: +- vdda_usb1_ss_1p2: +- vdda_usb2_ss_1p2: +- vreg_l26a_1p2: ldo26 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1208000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l28a_3p0: ldo28 { +- }; +- +- vreg_lvs1a_1p8: lvs1 { +- }; +- +- vreg_lvs2a_1p8: lvs2 { +- }; +- }; +-}; +- +-&cdsp_pas { +- firmware-name = "qcom/LENOVO/81JL/qccdsp850.mbn"; +- status = "okay"; +-}; +- +-&dsi0 { +- status = "okay"; +- vdda-supply = <&vreg_l26a_1p2>; +- +- ports { +- port@1 { +- endpoint { +- remote-endpoint = <&sn65dsi86_in_a>; +- data-lanes = <0 1 2 3>; +- }; +- }; +- }; +-}; +- +-&dsi0_phy { +- status = "okay"; +- vdds-supply = <&vreg_l1a_0p875>; +-}; +- +-&gcc { +- protected-clocks = , +- , +- , +- , +- ; +-}; +- +-&gpu { +- zap-shader { +- memory-region = <&gpu_mem>; +- firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +-}; +- +-&i2c3 { +- status = "okay"; +- clock-frequency = <400000>; +- /* Overwrite pinctrl-0 from sdm845.dtsi */ +- pinctrl-0 = <&qup_i2c3_default &i2c3_hid_active>; +- +- tsel: hid@15 { +- compatible = "hid-over-i2c"; +- reg = <0x15>; +- hid-descr-addr = <0x1>; +- +- interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- tsc2: hid@2c { +- compatible = "hid-over-i2c"; +- reg = <0x2c>; +- hid-descr-addr = <0x20>; +- +- interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_HIGH>; +- }; +-}; +- +-&i2c5 { +- status = "okay"; +- clock-frequency = <400000>; +- +- tsc1: hid@10 { +- compatible = "hid-over-i2c"; +- reg = <0x10>; +- hid-descr-addr = <0x1>; +- +- interrupts-extended = <&tlmm 125 IRQ_TYPE_LEVEL_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_hid_active>; +- }; +-}; +- +-&i2c10 { +- status = "okay"; +- clock-frequency = <400000>; +- +- sn65dsi86: bridge@2c { +- compatible = "ti,sn65dsi86"; +- reg = <0x2c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sn65dsi86_pin_active>; +- +- enable-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; +- +- vpll-supply = <&vreg_l14a_1p88>; +- vccio-supply = <&vreg_l14a_1p88>; +- +- clocks = <&sn65dsi86_refclk>; +- clock-names = "refclk"; +- +- no-hpd; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- sn65dsi86_in_a: endpoint { +- remote-endpoint = <&dsi0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- sn65dsi86_out: endpoint { +- remote-endpoint = <&panel_in_edp>; +- }; +- }; +- }; +- }; +-}; +- +-&i2c11 { +- status = "okay"; +- clock-frequency = <400000>; +- +- ecsh: hid@5c { +- compatible = "hid-over-i2c"; +- reg = <0x5c>; +- hid-descr-addr = <0x1>; +- +- interrupts-extended = <&tlmm 92 IRQ_TYPE_LEVEL_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c11_hid_active>; +- }; +-}; +- +-&ipa { +- status = "okay"; +- memory-region = <&ipa_fw_mem>; +-}; +- +-&mdss { +- status = "okay"; +-}; +- +-&mdss_mdp { +- status = "okay"; +-}; +- +-&mss_pil { +- firmware-name = "qcom/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/LENOVO/81JL/qcdsp2850.mbn"; +-}; +- +-&qup_i2c10_default { +- pinconf { +- pins = "gpio55", "gpio56"; +- drive-strength = <2>; +- bias-disable; +- }; +-}; +- +-&qup_i2c12_default { +- drive-strength = <2>; +- bias-disable; +-}; +- +-&qup_uart6_default { +- pinmux { +- pins = "gpio45", "gpio46", "gpio47", "gpio48"; +- function = "qup6"; +- }; +- +- cts { +- pins = "gpio45"; +- bias-pull-down; +- }; +- +- rts-tx { +- pins = "gpio46", "gpio47"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- rx { +- pins = "gpio48"; +- bias-pull-up; +- }; +-}; +- +-&qupv3_id_0 { +- status = "okay"; +-}; +- +-&qupv3_id_1 { +- status = "okay"; +-}; +- +-&q6asmdai { +- dai@0 { +- reg = <0>; +- }; +- +- dai@1 { +- reg = <1>; +- }; +- +- dai@2 { +- reg = <2>; +- }; +-}; +- +-&sound { +- compatible = "qcom,db845c-sndcard"; +- model = "Lenovo-YOGA-C630-13Q50"; +- +- audio-routing = +- "RX_BIAS", "MCLK", +- "AMIC2", "MIC BIAS2", +- "SpkrLeft IN", "SPK1 OUT", +- "SpkrRight IN", "SPK2 OUT", +- "MM_DL1", "MultiMedia1 Playback", +- "MM_DL3", "MultiMedia3 Playback", +- "MultiMedia2 Capture", "MM_UL2"; +- +- mm1-dai-link { +- link-name = "MultiMedia1"; +- cpu { +- sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; +- }; +- }; +- +- mm2-dai-link { +- link-name = "MultiMedia2"; +- cpu { +- sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; +- }; +- }; +- +- mm3-dai-link { +- link-name = "MultiMedia3"; +- cpu { +- sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; +- }; +- }; +- +- slim-dai-link { +- link-name = "SLIM Playback"; +- cpu { +- sound-dai = <&q6afedai SLIMBUS_0_RX>; +- }; +- +- platform { +- sound-dai = <&q6routing>; +- }; +- +- codec { +- sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; +- }; +- }; +- +- slimcap-dai-link { +- link-name = "SLIM Capture"; +- cpu { +- sound-dai = <&q6afedai SLIMBUS_0_TX>; +- }; +- +- platform { +- sound-dai = <&q6routing>; +- }; +- +- codec { +- sound-dai = <&wcd9340 1>; +- }; +- }; +- +- slim-wcd-dai-link { +- link-name = "SLIM WCD Playback"; +- cpu { +- sound-dai = <&q6afedai SLIMBUS_1_RX>; +- }; +- +- platform { +- sound-dai = <&q6routing>; +- }; +- +- codec { +- sound-dai = <&wcd9340 2>; +- }; +- }; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <0 4>, <81 4>; +- +- sn65dsi86_pin_active: sn65dsi86-enable { +- pins = "gpio96"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- i2c3_hid_active: i2c2-hid-active { +- pins = "gpio37"; +- function = "gpio"; +- +- input-enable; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- i2c5_hid_active: i2c5-hid-active { +- pins = "gpio125"; +- function = "gpio"; +- +- input-enable; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- i2c11_hid_active: i2c11-hid-active { +- pins = "gpio92"; +- function = "gpio"; +- +- input-enable; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- wcd_intr_default: wcd_intr_default { +- pins = "gpio54"; +- function = "gpio"; +- +- input-enable; +- bias-pull-down; +- drive-strength = <2>; +- }; +- +- lid_pin_active: lid-pin { +- pins = "gpio124"; +- function = "gpio"; +- +- input-enable; +- bias-disable; +- }; +- +- mode_pin_active: mode-pin { +- pins = "gpio95"; +- function = "gpio"; +- +- input-enable; +- bias-disable; +- }; +-}; +- +-&uart6 { +- status = "okay"; +- +- bluetooth { +- compatible = "qcom,wcn3990-bt"; +- +- vddio-supply = <&vreg_s4a_1p8>; +- vddxo-supply = <&vreg_l7a_1p8>; +- vddrf-supply = <&vreg_l17a_1p3>; +- vddch0-supply = <&vreg_l25a_3p3>; +- max-speed = <3200000>; +- }; +-}; +- +-&ufs_mem_hc { +- status = "okay"; +- +- reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; +- +- vcc-supply = <&vreg_l20a_2p95>; +- vcc-max-microamp = <600000>; +-}; +- +-&ufs_mem_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vdda_ufs1_core>; +- vdda-pll-supply = <&vdda_ufs1_1p2>; +-}; +- +-&usb_1 { +- status = "okay"; +-}; +- +-&usb_1_dwc3 { +- dr_mode = "host"; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- +- vdd-supply = <&vdda_usb1_ss_core>; +- vdda-pll-supply = <&vdda_qusb_hs0_1p8>; +- vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; +- +- qcom,imp-res-offset-value = <8>; +- qcom,hstx-trim-value = ; +- qcom,preemphasis-level = ; +- qcom,preemphasis-width = ; +-}; +- +-&usb_1_qmpphy { +- status = "okay"; +- +- vdda-phy-supply = <&vdda_usb1_ss_1p2>; +- vdda-pll-supply = <&vdda_usb1_ss_core>; +-}; +- +-&usb_2 { +- status = "okay"; +-}; +- +-&usb_2_dwc3 { +- dr_mode = "host"; +-}; +- +-&usb_2_hsphy { +- status = "okay"; +- +- vdd-supply = <&vdda_usb2_ss_core>; +- vdda-pll-supply = <&vdda_qusb_hs0_1p8>; +- vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; +- +- qcom,imp-res-offset-value = <8>; +- qcom,hstx-trim-value = ; +-}; +- +-&usb_2_qmpphy { +- status = "okay"; +- +- vdda-phy-supply = <&vdda_usb2_ss_1p2>; +- vdda-pll-supply = <&vdda_usb2_ss_core>; +-}; +- +-&wcd9340{ +- pinctrl-0 = <&wcd_intr_default>; +- pinctrl-names = "default"; +- clock-names = "extclk"; +- clocks = <&rpmhcc RPMH_LN_BB_CLK2>; +- reset-gpios = <&tlmm 64 0>; +- vdd-buck-supply = <&vreg_s4a_1p8>; +- vdd-buck-sido-supply = <&vreg_s4a_1p8>; +- vdd-tx-supply = <&vreg_s4a_1p8>; +- vdd-rx-supply = <&vreg_s4a_1p8>; +- vdd-io-supply = <&vreg_s4a_1p8>; +- +- swm: swm@c85 { +- left_spkr: wsa8810-left{ +- compatible = "sdw10217211000"; +- reg = <0 3>; +- powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; +- #thermal-sensor-cells = <0>; +- sound-name-prefix = "SpkrLeft"; +- #sound-dai-cells = <0>; +- }; +- +- right_spkr: wsa8810-right{ +- compatible = "sdw10217211000"; +- powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>; +- reg = <0 4>; +- #thermal-sensor-cells = <0>; +- sound-name-prefix = "SpkrRight"; +- #sound-dai-cells = <0>; +- }; +- }; +-}; +- +-&wifi { +- status = "okay"; +- +- vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; +- vdd-1.8-xo-supply = <&vreg_l7a_1p8>; +- vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; +- vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; +- +- qcom,snoc-host-cap-8bit-quirk; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sdm850.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sdm850.dtsi +deleted file mode 100644 +index b1c2cf566c7a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sdm850.dtsi ++++ /dev/null +@@ -1,21 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * SDM850 SoC device tree source +- * +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-#include "sdm845.dtsi" +- +-&cpu4_opp_table { +- cpu4_opp33: opp-2841600000 { +- opp-hz = /bits/ 64 <2841600000>; +- opp-peak-kBps = <7216000 25497600>; +- }; +- +- cpu4_opp34: opp-2956800000 { +- opp-hz = /bits/ 64 <2956800000>; +- opp-peak-kBps = <7216000 25497600>; +- turbo-mode; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sm6125-sony-xperia-seine-pdx201.dts b/scripts/dtc/include-prefixes/arm64/qcom/sm6125-sony-xperia-seine-pdx201.dts +deleted file mode 100644 +index 58b6b2742d3f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sm6125-sony-xperia-seine-pdx201.dts ++++ /dev/null +@@ -1,139 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Martin Botka +- */ +- +-/dts-v1/; +- +-#include "sm6125.dtsi" +-#include +-#include +-#include +- +-/ { +- /* required for bootloader to select correct board */ +- qcom,msm-id = <394 0x10000>; /* sm6125 v1 */ +- qcom,board-id = <34 0>; +- +- model = "Sony Xperia 10 II"; +- compatible = "sony,pdx201", "qcom,sm6125"; +- +- chosen { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- framebuffer0: framebuffer@5c000000 { +- compatible = "simple-framebuffer"; +- reg = <0 0x5c000000 0 (2520 * 1080 * 4)>; +- width = <1080>; +- height = <2520>; +- stride = <(1080 * 4)>; +- format = "a8r8g8b8"; +- }; +- }; +- +- extcon_usb: extcon-usb { +- compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; +- }; +- +- gpio-keys { +- status = "okay"; +- compatible = "gpio-keys"; +- input-name = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- autorepeat; +- +- vol-dn { +- label = "Volume Down"; +- gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- linux,code = ; +- gpio-key,wakeup; +- debounce-interval = <15>; +- }; +- }; +- +- reserved_memory { +- #address-cells = <2>; +- #size-cells = <2>; +- debug_mem: memory@ffb00000 { +- reg = <0x0 0xffb00000 0x0 0xc0000>; +- no-map; +- }; +- +- last_log_mem: memory@ffbc0000 { +- reg = <0x0 0xffbc0000 0x0 0x80000>; +- no-map; +- }; +- +- pstore_mem: ramoops@ffc00000 { +- compatible = "ramoops"; +- reg = <0x0 0xffc40000 0x0 0xc0000>; +- record-size = <0x1000>; +- console-size = <0x40000>; +- msg-size = <0x20000 0x20000>; +- }; +- +- cmdline_mem: memory@ffd00000 { +- reg = <0x0 0xffd40000 0x0 0x1000>; +- no-map; +- }; +- }; +-}; +- +-&hsusb_phy1 { +- status = "okay"; +-}; +- +-&sdc2_state_off { +- sd-cd { +- pins = "gpio98"; +- bias-disable; +- drive-strength = <2>; +- }; +-}; +- +-&sdhc_1 { +- status = "okay"; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <22 2>, <28 6>; +- +- sdc2_state_on: sdc2-on { +- clk { +- pins = "sdc2_clk"; +- bias-disable; +- drive-strength = <16>; +- }; +- +- cmd { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- data { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- sd-cd { +- pins = "gpio98"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +-}; +- +-&usb3 { +- status = "okay"; +-}; +- +-&usb3_dwc3 { +- extcon = <&extcon_usb>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sm6125.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sm6125.dtsi +deleted file mode 100644 +index 9f476e3d0720..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sm6125.dtsi ++++ /dev/null +@@ -1,566 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Martin Botka +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&intc>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- chosen { }; +- +- clocks { +- xo_board: xo-board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <19200000>; +- clock-output-names = "xo_board"; +- }; +- +- sleep_clk: sleep-clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32000>; +- clock-output-names = "sleep_clk"; +- }; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- CPU0: cpu@0 { +- device_type = "cpu"; +- compatible = "qcom,kryo260"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- next-level-cache = <&L2_0>; +- L2_0: l2-cache { +- compatible = "cache"; +- }; +- }; +- +- CPU1: cpu@1 { +- device_type = "cpu"; +- compatible = "qcom,kryo260"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- next-level-cache = <&L2_0>; +- }; +- +- CPU2: cpu@2 { +- device_type = "cpu"; +- compatible = "qcom,kryo260"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- next-level-cache = <&L2_0>; +- }; +- +- CPU3: cpu@3 { +- device_type = "cpu"; +- compatible = "qcom,kryo260"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- next-level-cache = <&L2_0>; +- }; +- +- CPU4: cpu@100 { +- device_type = "cpu"; +- compatible = "qcom,kryo260"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1638>; +- next-level-cache = <&L2_1>; +- L2_1: l2-cache { +- compatible = "cache"; +- }; +- }; +- +- CPU5: cpu@101 { +- device_type = "cpu"; +- compatible = "qcom,kryo260"; +- reg = <0x0 0x101>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1638>; +- next-level-cache = <&L2_1>; +- }; +- +- CPU6: cpu@102 { +- device_type = "cpu"; +- compatible = "qcom,kryo260"; +- reg = <0x0 0x102>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1638>; +- next-level-cache = <&L2_1>; +- }; +- +- CPU7: cpu@103 { +- device_type = "cpu"; +- compatible = "qcom,kryo260"; +- reg = <0x0 0x103>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1638>; +- next-level-cache = <&L2_1>; +- }; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&CPU0>; +- }; +- +- core1 { +- cpu = <&CPU1>; +- }; +- +- core2 { +- cpu = <&CPU2>; +- }; +- +- core3 { +- cpu = <&CPU3>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&CPU4>; +- }; +- +- core1 { +- cpu = <&CPU5>; +- }; +- +- core2 { +- cpu = <&CPU6>; +- }; +- +- core3 { +- cpu = <&CPU7>; +- }; +- }; +- }; +- }; +- +- firmware { +- scm: scm { +- compatible = "qcom,scm-sm6125", "qcom,scm"; +- #reset-cells = <1>; +- }; +- }; +- +- memory@40000000 { +- /* We expect the bootloader to fill in the size */ +- reg = <0x0 0x40000000 0x0 0x0>; +- device_type = "memory"; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- reserved_memory: reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- hyp_mem: memory@45700000 { +- reg = <0x0 0x45700000 0x0 0x600000>; +- no-map; +- }; +- +- xbl_aop_mem: memory@45e00000 { +- reg = <0x0 0x45e00000 0x0 0x140000>; +- no-map; +- }; +- +- sec_apps_mem: memory@45fff000 { +- reg = <0x0 0x45fff000 0x0 0x1000>; +- no-map; +- }; +- +- smem_mem: memory@46000000 { +- reg = <0x0 0x46000000 0x0 0x200000>; +- no-map; +- }; +- +- reserved_mem1: memory@46200000 { +- reg = <0x0 0x46200000 0x0 0x2d00000>; +- no-map; +- }; +- +- camera_mem: memory@4ab00000 { +- reg = <0x0 0x4ab00000 0x0 0x500000>; +- no-map; +- }; +- +- modem_mem: memory@4b000000 { +- reg = <0x0 0x4b000000 0x0 0x7e00000>; +- no-map; +- }; +- +- venus_mem: memory@52e00000 { +- reg = <0x0 0x52e00000 0x0 0x500000>; +- no-map; +- }; +- +- wlan_msa_mem: memory@53300000 { +- reg = <0x0 0x53300000 0x0 0x200000>; +- no-map; +- }; +- +- cdsp_mem: memory@53500000 { +- reg = <0x0 0x53500000 0x0 0x1e00000>; +- no-map; +- }; +- +- adsp_pil_mem: memory@55300000 { +- reg = <0x0 0x55300000 0x0 0x1e00000>; +- no-map; +- }; +- +- ipa_fw_mem: memory@57100000 { +- reg = <0x0 0x57100000 0x0 0x10000>; +- no-map; +- }; +- +- ipa_gsi_mem: memory@57110000 { +- reg = <0x0 0x57110000 0x0 0x5000>; +- no-map; +- }; +- +- gpu_mem: memory@57115000 { +- reg = <0x0 0x57115000 0x0 0x2000>; +- no-map; +- }; +- +- cont_splash_mem: memory@5c000000 { +- reg = <0x0 0x5c000000 0x0 0x00f00000>; +- no-map; +- }; +- +- dfps_data_mem: memory@5cf00000 { +- reg = <0x0 0x5cf00000 0x0 0x0100000>; +- no-map; +- }; +- +- cdsp_sec_mem: memory@5f800000 { +- reg = <0x0 0x5f800000 0x0 0x1e00000>; +- no-map; +- }; +- +- qseecom_mem: memory@5e400000 { +- reg = <0x0 0x5e400000 0x0 0x1400000>; +- no-map; +- }; +- +- sdsp_mem: memory@f3000000 { +- reg = <0x0 0xf3000000 0x0 0x400000>; +- no-map; +- }; +- +- adsp_mem: memory@f3400000 { +- reg = <0x0 0xf3400000 0x0 0x800000>; +- no-map; +- }; +- +- qseecom_ta_mem: memory@13fc00000 { +- reg = <0x1 0x3fc00000 0x0 0x400000>; +- no-map; +- }; +- }; +- +- rpm-glink { +- compatible = "qcom,glink-rpm"; +- +- interrupts = ; +- qcom,rpm-msg-ram = <&rpm_msg_ram>; +- mboxes = <&apcs_glb 0>; +- +- rpm_requests: rpm-requests { +- compatible = "qcom,rpm-sm6125"; +- qcom,glink-channels = "rpm_requests"; +- +- rpmcc: clock-controller { +- compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc"; +- #clock-cells = <1>; +- }; +- }; +- }; +- +- smem: smem { +- compatible = "qcom,smem"; +- memory-region = <&smem_mem>; +- hwlocks = <&tcsr_mutex 3>; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00 0x00 0x00 0xffffffff>; +- compatible = "simple-bus"; +- +- tcsr_mutex: hwlock@340000 { +- compatible = "qcom,tcsr-mutex"; +- reg = <0x00340000 0x20000>; +- #hwlock-cells = <1>; +- }; +- +- tlmm: pinctrl@500000 { +- compatible = "qcom,sm6125-tlmm"; +- reg = <0x00500000 0x400000>, +- <0x00900000 0x400000>, +- <0x00d00000 0x400000>; +- reg-names = "west", "south", "east"; +- interrupts = ; +- gpio-controller; +- gpio-ranges = <&tlmm 0 0 134>; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- sdc2_state_off: sdc2-off { +- clk { +- pins = "sdc2_clk"; +- bias-disable; +- drive-strength = <2>; +- }; +- +- cmd { +- pins = "sdc2_cmd"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- data { +- pins = "sdc2_data"; +- bias-pull-up; +- drive-strength = <2>; +- }; +- }; +- }; +- +- gcc: clock-controller@1400000 { +- compatible = "qcom,gcc-sm6125"; +- reg = <0x01400000 0x1f0000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- clock-names = "bi_tcxo", "sleep_clk"; +- clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; +- }; +- +- hsusb_phy1: phy@1613000 { +- compatible = "qcom,msm8996-qusb2-phy"; +- reg = <0x01613000 0x180>; +- #phy-cells = <0>; +- +- clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, +- <&gcc GCC_AHB2PHY_USB_CLK>; +- clock-names = "ref", "cfg_ahb"; +- +- resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; +- status = "disabled"; +- }; +- +- rpm_msg_ram: sram@45f0000 { +- compatible = "qcom,rpm-msg-ram"; +- reg = <0x045f0000 0x7000>; +- }; +- +- sdhc_1: sdhci@4744000 { +- compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; +- reg = <0x04744000 0x1000>, <0x04745000 0x1000>; +- reg-names = "hc", "core"; +- +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- +- clocks = <&gcc GCC_SDCC1_AHB_CLK>, +- <&gcc GCC_SDCC1_APPS_CLK>, +- <&xo_board>; +- clock-names = "iface", "core", "xo"; +- bus-width = <8>; +- non-removable; +- status = "disabled"; +- }; +- +- sdhc_2: sdhci@4784000 { +- compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; +- reg = <0x04784000 0x1000>; +- reg-names = "hc"; +- +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- +- clocks = <&gcc GCC_SDCC2_AHB_CLK>, +- <&gcc GCC_SDCC2_APPS_CLK>, +- <&xo_board>; +- clock-names = "iface", "core", "xo"; +- +- pinctrl-0 = <&sdc2_state_on>; +- pinctrl-1 = <&sdc2_state_off>; +- pinctrl-names = "default", "sleep"; +- +- bus-width = <4>; +- status = "disabled"; +- }; +- +- usb3: usb@4ef8800 { +- compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; +- reg = <0x04ef8800 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, +- <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, +- <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, +- <&gcc GCC_USB3_PRIM_CLKREF_CLK>, +- <&gcc GCC_USB30_PRIM_SLEEP_CLK>, +- <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; +- +- assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_PRIM_MASTER_CLK>; +- assigned-clock-rates = <19200000>, <66666667>; +- +- power-domains = <&gcc USB30_PRIM_GDSC>; +- qcom,select-utmi-as-pipe-clk; +- status = "disabled"; +- +- usb3_dwc3: usb@4e00000 { +- compatible = "snps,dwc3"; +- reg = <0x04e00000 0xcd00>; +- interrupts = ; +- phys = <&hsusb_phy1>; +- phy-names = "usb2-phy"; +- snps,dis_u2_susphy_quirk; +- snps,dis_enblslpm_quirk; +- maximum-speed = "high-speed"; +- dr_mode = "peripheral"; +- }; +- }; +- +- spmi_bus: spmi@1c40000 { +- compatible = "qcom,spmi-pmic-arb"; +- reg = <0x01c40000 0x1100>, +- <0x01e00000 0x2000000>, +- <0x03e00000 0x100000>, +- <0x03f00000 0xa0000>, +- <0x01c0a000 0x26000>; +- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; +- interrupt-names = "periph_irq"; +- interrupts = ; +- qcom,ee = <0>; +- qcom,channel = <0>; +- #address-cells = <2>; +- #size-cells = <0>; +- interrupt-controller; +- #interrupt-cells = <4>; +- cell-index = <0>; +- }; +- +- apcs_glb: mailbox@f111000 { +- compatible = "qcom,sm6125-apcs-hmss-global"; +- reg = <0x0f111000 0x1000>; +- +- #mbox-cells = <1>; +- }; +- +- timer@f120000 { +- compatible = "arm,armv7-timer-mem"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- reg = <0x0f120000 0x1000>; +- clock-frequency = <19200000>; +- +- frame@0f121000 { +- frame-number = <0>; +- interrupts = , +- ; +- reg = <0x0f121000 0x1000>, +- <0x0f122000 0x1000>; +- }; +- +- frame@0f123000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0x0f123000 0x1000>; +- status = "disabled"; +- }; +- +- frame@0f124000 { +- frame-number = <2>; +- interrupts = ; +- reg = <0x0f124000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f125000 { +- frame-number = <3>; +- interrupts = ; +- reg = <0x0f125000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f126000 { +- frame-number = <4>; +- interrupts = ; +- reg = <0x0f126000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f127000 { +- frame-number = <5>; +- interrupts = ; +- reg = <0x0f127000 0x1000>; +- status = "disabled"; +- }; +- +- frame@f128000 { +- frame-number = <6>; +- interrupts = ; +- reg = <0x0f128000 0x1000>; +- status = "disabled"; +- }; +- }; +- +- intc: interrupt-controller@f200000 { +- compatible = "arm,gic-v3"; +- reg = <0x0f200000 0x20000>, +- <0x0f300000 0x100000>; +- #interrupt-cells = <3>; +- interrupt-controller; +- interrupts = ; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = ; +- clock-frequency = <19200000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sm8150-hdk.dts b/scripts/dtc/include-prefixes/arm64/qcom/sm8150-hdk.dts +deleted file mode 100644 +index 335aa0753fc0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sm8150-hdk.dts ++++ /dev/null +@@ -1,467 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "sm8150.dtsi" +-#include "pm8150.dtsi" +-#include "pm8150b.dtsi" +-#include "pm8150l.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. SM8150 HDK"; +- compatible = "qcom,sm8150-hdk", "qcom,sm8150"; +- +- aliases { +- serial0 = &uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- }; +- +- vreg_s4a_1p8: pm8150-s4 { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_s4a_1p8"; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-always-on; +- regulator-boot-on; +- +- vin-supply = <&vph_pwr>; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- vol-up { +- label = "Volume Up"; +- linux,code = ; +- gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&apps_rsc { +- pm8150-rpmh-regulators { +- compatible = "qcom,pm8150-rpmh-regulators"; +- qcom,pmic-id = "a"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- vdd-s9-supply = <&vph_pwr>; +- vdd-s10-supply = <&vph_pwr>; +- +- vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; +- vdd-l2-l10-supply = <&vreg_bob>; +- vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>; +- vdd-l6-l9-supply = <&vreg_s8c_1p3>; +- vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>; +- vdd-l13-l16-l17-supply = <&vreg_bob>; +- +- vreg_s5a_2p0: smps5 { +- regulator-min-microvolt = <1904000>; +- regulator-max-microvolt = <2000000>; +- }; +- +- vreg_s6a_0p9: smps6 { +- regulator-min-microvolt = <920000>; +- regulator-max-microvolt = <1128000>; +- }; +- +- vdda_wcss_pll: +- vreg_l1a_0p75: ldo1 { +- regulator-min-microvolt = <752000>; +- regulator-max-microvolt = <752000>; +- regulator-initial-mode = ; +- }; +- +- vdd_pdphy: +- vdda_usb_hs_3p1: +- vreg_l2a_3p1: ldo2 { +- regulator-min-microvolt = <3072000>; +- regulator-max-microvolt = <3072000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3a_0p8: ldo3 { +- regulator-min-microvolt = <480000>; +- regulator-max-microvolt = <932000>; +- regulator-initial-mode = ; +- }; +- +- vdd_usb_hs_core: +- vdda_csi_0_0p9: +- vdda_csi_1_0p9: +- vdda_csi_2_0p9: +- vdda_csi_3_0p9: +- vdda_dsi_0_0p9: +- vdda_dsi_1_0p9: +- vdda_dsi_0_pll_0p9: +- vdda_dsi_1_pll_0p9: +- vdda_pcie_1ln_core: +- vdda_pcie_2ln_core: +- vdda_pll_hv_cc_ebi01: +- vdda_pll_hv_cc_ebi23: +- vdda_qrefs_0p875_5: +- vdda_sp_sensor: +- vdda_ufs_2ln_core_1: +- vdda_ufs_2ln_core_2: +- vdda_usb_ss_dp_core_1: +- vdda_usb_ss_dp_core_2: +- vdda_qlink_lv: +- vdda_qlink_lv_ck: +- vreg_l5a_0p875: ldo5 { +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6a_1p2: ldo6 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7a_1p8: ldo7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_10: +- vreg_l9a_1p2: ldo9 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10a_2p5: ldo10 { +- regulator-min-microvolt = <2504000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l11a_0p8: ldo11 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vdd_qfprom: +- vdd_qfprom_sp: +- vdda_apc_cs_1p8: +- vdda_gfx_cs_1p8: +- vdda_usb_hs_1p8: +- vdda_qrefs_vref_1p8: +- vddpx_10_a: +- vreg_l12a_1p8: ldo12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l13a_2p7: ldo13 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2704000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l14a_1p8: ldo14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1880000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l15a_1p7: ldo15 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <1704000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l16a_2p7: ldo16 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l17a_3p0: ldo17 { +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- }; +- +- pm8150l-rpmh-regulators { +- compatible = "qcom,pm8150l-rpmh-regulators"; +- qcom,pmic-id = "c"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- +- vdd-l1-l8-supply = <&vreg_s4a_1p8>; +- vdd-l2-l3-supply = <&vreg_s8c_1p3>; +- vdd-l4-l5-l6-supply = <&vreg_bob>; +- vdd-l7-l11-supply = <&vreg_bob>; +- vdd-l9-l10-supply = <&vreg_bob>; +- +- vdd-bob-supply = <&vph_pwr>; +- vdd-flash-supply = <&vreg_bob>; +- vdd-rgb-supply = <&vreg_bob>; +- +- vreg_bob: bob { +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <4000000>; +- regulator-initial-mode = ; +- regulator-allow-bypass; +- }; +- +- vreg_s8c_1p3: smps8 { +- regulator-min-microvolt = <1352000>; +- regulator-max-microvolt = <1352000>; +- }; +- +- vreg_l1c_1p8: ldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vdda_wcss_adcdac_1: +- vdda_wcss_adcdac_22: +- vreg_l2c_1p3: ldo2 { +- regulator-min-microvolt = <1304000>; +- regulator-max-microvolt = <1304000>; +- regulator-initial-mode = ; +- }; +- +- vdda_hv_ebi0: +- vdda_hv_ebi1: +- vdda_hv_ebi2: +- vdda_hv_ebi3: +- vdda_hv_refgen0: +- vdda_qlink_hv_ck: +- vreg_l3c_1p2: ldo3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_5: +- vreg_l4c_1p8: ldo4 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_6: +- vreg_l5c_1p8: ldo5 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_2: +- vreg_l6c_2p9: ldo6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7c_3p0: ldo7 { +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <3104000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l8c_1p8: ldo8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l9c_2p9: ldo9 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10c_3p3: ldo10 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l11c_3p3: ldo11 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- }; +- +- pm8009-rpmh-regulators { +- compatible = "qcom,pm8009-rpmh-regulators"; +- qcom,pmic-id = "f"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vreg_bob>; +- +- vdd-l2-supply = <&vreg_s8c_1p3>; +- vdd-l5-l6-supply = <&vreg_bob>; +- +- vreg_l2f_1p2: ldo2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5f_2p85: ldo5 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6f_2p85: ldo6 { +- regulator-initial-mode = ; +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <2856000>; +- }; +- }; +-}; +- +-&gmu { +- status = "okay"; +-}; +- +-&gpu { +- status = "okay"; +-}; +- +-&pon_pwrkey { +- status = "okay"; +-}; +- +-&pon_resin { +- status = "okay"; +- +- linux,code = ; +-}; +- +-&qupv3_id_1 { +- status = "okay"; +-}; +- +-&remoteproc_adsp { +- status = "okay"; +- +- firmware-name = "qcom/sm8150/adsp.mbn"; +-}; +- +-&remoteproc_cdsp { +- status = "okay"; +- +- firmware-name = "qcom/sm8150/cdsp.mbn"; +-}; +- +-&remoteproc_slpi { +- status = "okay"; +- +- firmware-name = "qcom/sm8150/slpi.mbn"; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <0 4>, <126 4>; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&ufs_mem_hc { +- status = "okay"; +- +- reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; +- +- vcc-supply = <&vreg_l10a_2p5>; +- vcc-max-microamp = <750000>; +- vccq-supply = <&vreg_l9a_1p2>; +- vccq-max-microamp = <700000>; +- vccq2-supply = <&vreg_s4a_1p8>; +- vccq2-max-microamp = <750000>; +-}; +- +-&ufs_mem_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vdda_ufs_2ln_core_1>; +- vdda-max-microamp = <90200>; +- vdda-pll-supply = <&vreg_l3c_1p2>; +- vdda-pll-max-microamp = <19000>; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- vdda-pll-supply = <&vdd_usb_hs_core>; +- vdda33-supply = <&vdda_usb_hs_3p1>; +- vdda18-supply = <&vdda_usb_hs_1p8>; +-}; +- +-&usb_2_hsphy { +- status = "okay"; +- vdda-pll-supply = <&vdd_usb_hs_core>; +- vdda33-supply = <&vdda_usb_hs_3p1>; +- vdda18-supply = <&vdda_usb_hs_1p8>; +-}; +- +-&usb_1_qmpphy { +- status = "okay"; +- vdda-phy-supply = <&vreg_l3c_1p2>; +- vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; +-}; +- +-&usb_2_qmpphy { +- status = "okay"; +- vdda-phy-supply = <&vreg_l3c_1p2>; +- vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; +-}; +- +-&usb_1 { +- status = "okay"; +-}; +- +-&usb_2 { +- status = "okay"; +-}; +- +-&usb_1_dwc3 { +- dr_mode = "peripheral"; +-}; +- +-&usb_2_dwc3 { +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sm8150-microsoft-surface-duo.dts b/scripts/dtc/include-prefixes/arm64/qcom/sm8150-microsoft-surface-duo.dts +deleted file mode 100644 +index 736da9af44e0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sm8150-microsoft-surface-duo.dts ++++ /dev/null +@@ -1,543 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (C) 2021, Microsoft Corporation +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "sm8150.dtsi" +-#include "pm8150.dtsi" +-#include "pm8150b.dtsi" +-#include "pm8150l.dtsi" +- +-/ { +- model = "Microsoft Surface Duo"; +- compatible = "microsoft,surface-duo", "qcom,sm8150"; +- +- aliases { +- serial0 = &uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- }; +- +- /* +- * Apparently RPMh does not provide support for PM8150 S4 because it +- * is always-on; model it as a fixed regulator. +- */ +- vreg_s4a_1p8: pm8150-s4 { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_s4a_1p8"; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-always-on; +- regulator-boot-on; +- +- vin-supply = <&vph_pwr>; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- vol_up { +- label = "Volume Up"; +- gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +-}; +- +-&apps_rsc { +- pm8150-rpmh-regulators { +- compatible = "qcom,pm8150-rpmh-regulators"; +- qcom,pmic-id = "a"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- vdd-s9-supply = <&vph_pwr>; +- vdd-s10-supply = <&vph_pwr>; +- +- vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; +- vdd-l2-l10-supply = <&vreg_bob>; +- vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>; +- vdd-l6-l9-supply = <&vreg_s8c_1p3>; +- vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>; +- vdd-l13-l16-l17-supply = <&vreg_bob>; +- +- vreg_s5a_2p0: smps5 { +- regulator-min-microvolt = <1904000>; +- regulator-max-microvolt = <2000000>; +- }; +- +- vreg_s6a_0p9: smps6 { +- regulator-min-microvolt = <920000>; +- regulator-max-microvolt = <1128000>; +- }; +- +- vdda_wcss_pll: +- vreg_l1a_0p75: ldo1 { +- regulator-min-microvolt = <752000>; +- regulator-max-microvolt = <752000>; +- regulator-initial-mode = ; +- }; +- +- vdd_pdphy: +- vdda_usb_hs_3p1: +- vreg_l2a_3p1: ldo2 { +- regulator-min-microvolt = <3072000>; +- regulator-max-microvolt = <3072000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3a_0p8: ldo3 { +- regulator-min-microvolt = <480000>; +- regulator-max-microvolt = <932000>; +- regulator-initial-mode = ; +- }; +- +- vdd_usb_hs_core: +- vdda_csi_0_0p9: +- vdda_csi_1_0p9: +- vdda_csi_2_0p9: +- vdda_csi_3_0p9: +- vdda_dsi_0_0p9: +- vdda_dsi_1_0p9: +- vdda_dsi_0_pll_0p9: +- vdda_dsi_1_pll_0p9: +- vdda_pcie_1ln_core: +- vdda_pcie_2ln_core: +- vdda_pll_hv_cc_ebi01: +- vdda_pll_hv_cc_ebi23: +- vdda_qrefs_0p875_5: +- vdda_sp_sensor: +- vdda_ufs_2ln_core_1: +- vdda_ufs_2ln_core_2: +- vdda_usb_ss_dp_core_1: +- vdda_usb_ss_dp_core_2: +- vdda_qlink_lv: +- vdda_qlink_lv_ck: +- vreg_l5a_0p875: ldo5 { +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6a_1p2: ldo6 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7a_1p8: ldo7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_10: +- vreg_l9a_1p2: ldo9 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10a_2p5: ldo10 { +- regulator-min-microvolt = <2504000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l11a_0p8: ldo11 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vdd_qfprom: +- vdd_qfprom_sp: +- vdda_apc_cs_1p8: +- vdda_gfx_cs_1p8: +- vdda_usb_hs_1p8: +- vdda_qrefs_vref_1p8: +- vddpx_10_a: +- vreg_l12a_1p8: ldo12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l13a_2p7: ldo13 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2704000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l14a_1p8: ldo14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1880000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l15a_1p7: ldo15 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <1704000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l16a_2p7: ldo16 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l17a_3p0: ldo17 { +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- }; +- +- pm8150l-rpmh-regulators { +- compatible = "qcom,pm8150l-rpmh-regulators"; +- qcom,pmic-id = "c"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- +- vdd-l1-l8-supply = <&vreg_s4a_1p8>; +- vdd-l2-l3-supply = <&vreg_s8c_1p3>; +- vdd-l4-l5-l6-supply = <&vreg_bob>; +- vdd-l7-l11-supply = <&vreg_bob>; +- vdd-l9-l10-supply = <&vreg_bob>; +- +- vdd-bob-supply = <&vph_pwr>; +- vdd-flash-supply = <&vreg_bob>; +- vdd-rgb-supply = <&vreg_bob>; +- +- vreg_bob: bob { +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <4000000>; +- regulator-initial-mode = ; +- regulator-allow-bypass; +- }; +- +- vreg_s8c_1p3: smps8 { +- regulator-min-microvolt = <1352000>; +- regulator-max-microvolt = <1352000>; +- }; +- +- vreg_l1c_1p8: ldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vdda_wcss_adcdac_1: +- vdda_wcss_adcdac_22: +- vreg_l2c_1p3: ldo2 { +- regulator-min-microvolt = <1304000>; +- regulator-max-microvolt = <1304000>; +- regulator-initial-mode = ; +- }; +- +- vdda_hv_ebi0: +- vdda_hv_ebi1: +- vdda_hv_ebi2: +- vdda_hv_ebi3: +- vdda_hv_refgen0: +- vdda_qlink_hv_ck: +- vreg_l3c_1p2: ldo3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_5: +- vreg_l4c_1p8: ldo4 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_6: +- vreg_l5c_1p8: ldo5 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_2: +- vreg_l6c_2p9: ldo6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7c_3p0: ldo7 { +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <3104000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l8c_1p8: ldo8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l9c_2p9: ldo9 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10c_3p3: ldo10 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l11c_3p3: ldo11 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- }; +- +- pm8009-rpmh-regulators { +- compatible = "qcom,pm8009-rpmh-regulators"; +- qcom,pmic-id = "f"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vreg_bob>; +- +- vdd-l2-supply = <&vreg_s8c_1p3>; +- vdd-l5-l6-supply = <&vreg_bob>; +- +- vreg_l2f_1p2: ldo2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5f_2p85: ldo5 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6f_2p85: ldo6 { +- regulator-initial-mode = ; +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <2856000>; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- bq27742@55 { +- compatible = "ti,bq27742"; +- reg = <0x55>; +- }; +- +- da7280@4a { +- compatible = "dlg,da7280"; +- reg = <0x4a>; +- interrupts-extended = <&tlmm 42 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "da7280_default"; +- pinctrl-0 = <&da7280_intr_default>; +- +- dlg,actuator-type = "LRA"; +- dlg,dlg,const-op-mode = <1>; +- dlg,dlg,periodic-op-mode = <1>; +- dlg,nom-microvolt = <2000000>; +- dlg,abs-max-microvolt = <2000000>; +- dlg,imax-microamp = <129000>; +- dlg,resonant-freq-hz = <180>; +- dlg,impd-micro-ohms = <14300000>; +- dlg,freq-track-enable; +- dlg,bemf-sens-enable; +- dlg,mem-array = < +- 0x06 0x08 0x10 0x11 0x12 0x13 0x14 0x15 0x1c 0x2a +- 0x33 0x3c 0x42 0x4b 0x4c 0x4e 0x17 0x19 0x27 0x29 +- 0x17 0x19 0x03 0x84 0x5e 0x04 0x08 0x84 0x5d 0x01 +- 0x84 0x5e 0x02 0x00 0xa4 0x5d 0x03 0x84 0x5e 0x06 +- 0x08 0x84 0x5d 0x05 0x84 0x5d 0x06 0x84 0x5e 0x08 +- 0x84 0x5e 0x05 0x8c 0x5e 0x24 0x84 0x5f 0x10 0x84 +- 0x5e 0x05 0x84 0x5e 0x08 0x84 0x5f 0x01 0x8c 0x5e +- 0x04 0x84 0x5e 0x08 0x84 0x5f 0x11 0x19 0x88 0x00 +- 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 +- 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 +- >; +- }; +- +- /* SMB1381 @ 0x44 */ +- /* MAX34417 @ 0x1c */ +-}; +- +-&i2c4 { +- status = "okay"; +- clock-frequency = <400000>; +- +- /* SMB1355 @ 0x0c */ +- /* SMB1390 @ 0x10 */ +-}; +- +-&i2c17 { +- status = "okay"; +- clock-frequency = <400000>; +- +- bq27742@55 { +- compatible = "ti,bq27742"; +- reg = <0x55>; +- }; +-}; +- +-&i2c19 { +- status = "okay"; +- clock-frequency = <400000>; +- +- /* MAX34417 @ 0x12 */ +- /* MAX34417 @ 0x1a */ +- /* MAX34417 @ 0x1e */ +-}; +- +-&pon { +- pwrkey { +- status = "okay"; +- }; +- +- resin { +- compatible = "qcom,pm8941-resin"; +- interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; +- debounce = <15625>; +- bias-pull-up; +- linux,code = ; +- }; +-}; +- +-&qupv3_id_0 { +- status = "okay"; +-}; +- +-&qupv3_id_1 { +- status = "okay"; +-}; +- +-&qupv3_id_2 { +- status = "okay"; +-}; +- +-&remoteproc_adsp { +- status = "okay"; +- firmware-name = "qcom/sm8150/microsoft/adsp.mdt"; +-}; +- +-&remoteproc_cdsp { +- status = "okay"; +- firmware-name = "qcom/sm8150/microsoft/cdsp.mdt"; +-}; +- +-&remoteproc_mpss { +- status = "okay"; +- firmware-name = "qcom/sm8150/microsoft/modem.mdt"; +-}; +- +-&remoteproc_slpi { +- status = "okay"; +- firmware-name = "qcom/sm8150/microsoft/slpi.mdt"; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <126 4>; +- +- da7280_intr_default: da7280-intr-default { +- pins = "gpio42"; +- function = "gpio"; +- bias-pull-up; +- input-enable; +- }; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&ufs_mem_hc { +- status = "okay"; +- +- reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; +- +- vcc-supply = <&vreg_l10a_2p5>; +- vcc-max-microamp = <750000>; +- vccq-supply = <&vreg_l9a_1p2>; +- vccq-max-microamp = <700000>; +- vccq2-supply = <&vreg_s4a_1p8>; +- vccq2-max-microamp = <750000>; +-}; +- +-&ufs_mem_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vdda_ufs_2ln_core_1>; +- vdda-max-microamp = <90200>; +- vdda-pll-supply = <&vreg_l3c_1p2>; +- vdda-pll-max-microamp = <19000>; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- vdda-pll-supply = <&vdd_usb_hs_core>; +- vdda33-supply = <&vdda_usb_hs_3p1>; +- vdda18-supply = <&vdda_usb_hs_1p8>; +-}; +- +-&usb_1_qmpphy { +- status = "okay"; +- vdda-phy-supply = <&vreg_l3c_1p2>; +- vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; +-}; +- +-&usb_1 { +- status = "okay"; +-}; +- +-&usb_1_dwc3 { +- dr_mode = "peripheral"; +-}; +- +-&wifi { +- status = "okay"; +- +- vdd-0.8-cx-mx-supply = <&vdda_wcss_pll>; +- vdd-1.8-xo-supply = <&vreg_l7a_1p8>; +- vdd-1.3-rfa-supply = <&vdda_wcss_adcdac_1>; +- vdd-3.3-ch0-supply = <&vreg_l11c_3p3>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sm8150-mtp.dts b/scripts/dtc/include-prefixes/arm64/qcom/sm8150-mtp.dts +deleted file mode 100644 +index b484371a6044..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sm8150-mtp.dts ++++ /dev/null +@@ -1,452 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. +- * Copyright (c) 2019, Linaro Limited +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "sm8150.dtsi" +-#include "pm8150.dtsi" +-#include "pm8150b.dtsi" +-#include "pm8150l.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. SM8150 MTP"; +- compatible = "qcom,sm8150-mtp", "qcom,sm8150"; +- +- aliases { +- serial0 = &uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- }; +- +- /* +- * Apparently RPMh does not provide support for PM8150 S4 because it +- * is always-on; model it as a fixed regulator. +- */ +- vreg_s4a_1p8: pm8150-s4 { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_s4a_1p8"; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-always-on; +- regulator-boot-on; +- +- vin-supply = <&vph_pwr>; +- }; +-}; +- +-&apps_rsc { +- pm8150-rpmh-regulators { +- compatible = "qcom,pm8150-rpmh-regulators"; +- qcom,pmic-id = "a"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- vdd-s9-supply = <&vph_pwr>; +- vdd-s10-supply = <&vph_pwr>; +- +- vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; +- vdd-l2-l10-supply = <&vreg_bob>; +- vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>; +- vdd-l6-l9-supply = <&vreg_s8c_1p3>; +- vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>; +- vdd-l13-l16-l17-supply = <&vreg_bob>; +- +- vreg_s5a_2p0: smps5 { +- regulator-min-microvolt = <1904000>; +- regulator-max-microvolt = <2000000>; +- }; +- +- vreg_s6a_0p9: smps6 { +- regulator-min-microvolt = <920000>; +- regulator-max-microvolt = <1128000>; +- }; +- +- vdda_wcss_pll: +- vreg_l1a_0p75: ldo1 { +- regulator-min-microvolt = <752000>; +- regulator-max-microvolt = <752000>; +- regulator-initial-mode = ; +- }; +- +- vdd_pdphy: +- vdda_usb_hs_3p1: +- vreg_l2a_3p1: ldo2 { +- regulator-min-microvolt = <3072000>; +- regulator-max-microvolt = <3072000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3a_0p8: ldo3 { +- regulator-min-microvolt = <480000>; +- regulator-max-microvolt = <932000>; +- regulator-initial-mode = ; +- }; +- +- vdd_usb_hs_core: +- vdda_csi_0_0p9: +- vdda_csi_1_0p9: +- vdda_csi_2_0p9: +- vdda_csi_3_0p9: +- vdda_dsi_0_0p9: +- vdda_dsi_1_0p9: +- vdda_dsi_0_pll_0p9: +- vdda_dsi_1_pll_0p9: +- vdda_pcie_1ln_core: +- vdda_pcie_2ln_core: +- vdda_pll_hv_cc_ebi01: +- vdda_pll_hv_cc_ebi23: +- vdda_qrefs_0p875_5: +- vdda_sp_sensor: +- vdda_ufs_2ln_core_1: +- vdda_ufs_2ln_core_2: +- vdda_usb_ss_dp_core_1: +- vdda_usb_ss_dp_core_2: +- vdda_qlink_lv: +- vdda_qlink_lv_ck: +- vreg_l5a_0p875: ldo5 { +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6a_1p2: ldo6 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7a_1p8: ldo7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_10: +- vreg_l9a_1p2: ldo9 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10a_2p5: ldo10 { +- regulator-min-microvolt = <2504000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l11a_0p8: ldo11 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vdd_qfprom: +- vdd_qfprom_sp: +- vdda_apc_cs_1p8: +- vdda_gfx_cs_1p8: +- vdda_usb_hs_1p8: +- vdda_qrefs_vref_1p8: +- vddpx_10_a: +- vreg_l12a_1p8: ldo12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l13a_2p7: ldo13 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2704000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l14a_1p8: ldo14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1880000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l15a_1p7: ldo15 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <1704000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l16a_2p7: ldo16 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l17a_3p0: ldo17 { +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- }; +- +- pm8150l-rpmh-regulators { +- compatible = "qcom,pm8150l-rpmh-regulators"; +- qcom,pmic-id = "c"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- +- vdd-l1-l8-supply = <&vreg_s4a_1p8>; +- vdd-l2-l3-supply = <&vreg_s8c_1p3>; +- vdd-l4-l5-l6-supply = <&vreg_bob>; +- vdd-l7-l11-supply = <&vreg_bob>; +- vdd-l9-l10-supply = <&vreg_bob>; +- +- vdd-bob-supply = <&vph_pwr>; +- vdd-flash-supply = <&vreg_bob>; +- vdd-rgb-supply = <&vreg_bob>; +- +- vreg_bob: bob { +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <4000000>; +- regulator-initial-mode = ; +- regulator-allow-bypass; +- }; +- +- vreg_s8c_1p3: smps8 { +- regulator-min-microvolt = <1352000>; +- regulator-max-microvolt = <1352000>; +- }; +- +- vreg_l1c_1p8: ldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vdda_wcss_adcdac_1: +- vdda_wcss_adcdac_22: +- vreg_l2c_1p3: ldo2 { +- regulator-min-microvolt = <1304000>; +- regulator-max-microvolt = <1304000>; +- regulator-initial-mode = ; +- }; +- +- vdda_hv_ebi0: +- vdda_hv_ebi1: +- vdda_hv_ebi2: +- vdda_hv_ebi3: +- vdda_hv_refgen0: +- vdda_qlink_hv_ck: +- vreg_l3c_1p2: ldo3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_5: +- vreg_l4c_1p8: ldo4 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_6: +- vreg_l5c_1p8: ldo5 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- vddpx_2: +- vreg_l6c_2p9: ldo6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7c_3p0: ldo7 { +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <3104000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l8c_1p8: ldo8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l9c_2p9: ldo9 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10c_3p3: ldo10 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l11c_3p3: ldo11 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- }; +- +- pm8009-rpmh-regulators { +- compatible = "qcom,pm8009-rpmh-regulators"; +- qcom,pmic-id = "f"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vreg_bob>; +- +- vdd-l2-supply = <&vreg_s8c_1p3>; +- vdd-l5-l6-supply = <&vreg_bob>; +- +- vreg_l2f_1p2: ldo2 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5f_2p85: ldo5 { +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6f_2p85: ldo6 { +- regulator-initial-mode = ; +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <2856000>; +- }; +- }; +-}; +- +-&gmu { +- status = "okay"; +-}; +- +-&gpu { +- status = "okay"; +-}; +- +-&pon_pwrkey { +- status = "okay"; +-}; +- +-&pon_resin { +- status = "okay"; +- +- linux,code = ; +-}; +- +-&qupv3_id_1 { +- status = "okay"; +-}; +- +-&remoteproc_adsp { +- status = "okay"; +- firmware-name = "qcom/sm8150/adsp.mdt"; +-}; +- +-&remoteproc_cdsp { +- status = "okay"; +- firmware-name = "qcom/sm8150/cdsp.mdt"; +-}; +- +-&remoteproc_mpss { +- status = "okay"; +- firmware-name = "qcom/sm8150/modem.mdt"; +-}; +- +-&remoteproc_slpi { +- status = "okay"; +- firmware-name = "qcom/sm8150/slpi.mdt"; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <0 4>, <126 4>; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&ufs_mem_hc { +- status = "okay"; +- +- reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; +- +- vcc-supply = <&vreg_l10a_2p5>; +- vcc-max-microamp = <750000>; +- vccq-supply = <&vreg_l9a_1p2>; +- vccq-max-microamp = <700000>; +- vccq2-supply = <&vreg_s4a_1p8>; +- vccq2-max-microamp = <750000>; +-}; +- +-&ufs_mem_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vdda_ufs_2ln_core_1>; +- vdda-max-microamp = <90200>; +- vdda-pll-supply = <&vreg_l3c_1p2>; +- vdda-pll-max-microamp = <19000>; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- vdda-pll-supply = <&vdd_usb_hs_core>; +- vdda33-supply = <&vdda_usb_hs_3p1>; +- vdda18-supply = <&vdda_usb_hs_1p8>; +-}; +- +-&usb_1_qmpphy { +- status = "okay"; +- vdda-phy-supply = <&vreg_l3c_1p2>; +- vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; +-}; +- +-&usb_1 { +- status = "okay"; +-}; +- +-&usb_1_dwc3 { +- dr_mode = "peripheral"; +-}; +- +-&wifi { +- status = "okay"; +- +- vdd-0.8-cx-mx-supply = <&vdda_wcss_pll>; +- vdd-1.8-xo-supply = <&vreg_l7a_1p8>; +- vdd-1.3-rfa-supply = <&vdda_wcss_adcdac_1>; +- vdd-3.3-ch0-supply = <&vreg_l11c_3p3>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sm8150-sony-xperia-kumano-bahamut.dts b/scripts/dtc/include-prefixes/arm64/qcom/sm8150-sony-xperia-kumano-bahamut.dts +deleted file mode 100644 +index 3b55fdda767a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sm8150-sony-xperia-kumano-bahamut.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Konrad Dybcio +- */ +- +-/dts-v1/; +- +-#include "sm8150-sony-xperia-kumano.dtsi" +- +-/ { +- model = "Sony Xperia 5"; +- compatible = "sony,bahamut-generic", "qcom,sm8150"; +-}; +- +-&framebuffer { +- width = <1080>; +- height = <2520>; +- stride = <(1080 * 4)>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sm8150-sony-xperia-kumano-griffin.dts b/scripts/dtc/include-prefixes/arm64/qcom/sm8150-sony-xperia-kumano-griffin.dts +deleted file mode 100644 +index 6f490ec284bd..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sm8150-sony-xperia-kumano-griffin.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Konrad Dybcio +- */ +- +-/dts-v1/; +- +-#include "sm8150-sony-xperia-kumano.dtsi" +- +-/ { +- model = "Sony Xperia 1"; +- compatible = "sony,griffin-generic", "qcom,sm8150"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sm8150-sony-xperia-kumano.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sm8150-sony-xperia-kumano.dtsi +deleted file mode 100644 +index 014fe3a31548..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sm8150-sony-xperia-kumano.dtsi ++++ /dev/null +@@ -1,452 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Konrad Dybcio +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "sm8150.dtsi" +-#include "pm8150.dtsi" +-#include "pm8150b.dtsi" +-#include "pm8150l.dtsi" +- +-/delete-node/ &cdsp_mem; +-/delete-node/ &gpu_mem; +-/delete-node/ &ipa_fw_mem; +-/delete-node/ &ipa_gsi_mem; +-/delete-node/ &mpss_mem; +-/delete-node/ &slpi_mem; +-/delete-node/ &spss_mem; +-/delete-node/ &venus_mem; +- +-/ { +- qcom,msm-id = <339 0x20000>; /* SM8150 v2 */ +- qcom,board-id = <8 0>; +- +- chosen { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- framebuffer: framebuffer@9c000000 { +- compatible = "simple-framebuffer"; +- reg = <0 0x9c000000 0 0x2300000>; +- width = <1644>; +- height = <3840>; +- stride = <(1644 * 4)>; +- format = "a8r8g8b8"; +- /* +- * That's (going to be) a lot of clocks, but it's necessary due +- * to unused clk cleanup & no panel driver yet (& no dispcc either).. +- */ +- clocks = <&gcc GCC_DISP_HF_AXI_CLK>, +- <&gcc GCC_DISP_SF_AXI_CLK>; +- }; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- }; +- +- /* +- * Apparently RPMh does not provide support for PM8150 S4 because it +- * is always-on; model it as a fixed regulator. +- */ +- vreg_s4a_1p8: pm8150-s4 { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_s4a_1p8"; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-always-on; +- regulator-boot-on; +- +- vin-supply = <&vph_pwr>; +- }; +- +- reserved-memory { +- mpss_mem: memory@8dc00000 { +- reg = <0x0 0x8dc00000 0x0 0x9600000>; +- no-map; +- }; +- +- venus_mem: memory@97200000 { +- reg = <0x0 0x97200000 0x0 0x500000>; +- no-map; +- }; +- +- slpi_mem: memory@97700000 { +- reg = <0x0 0x97700000 0x0 0x1400000>; +- no-map; +- }; +- +- ipa_fw_mem: memory@98b00000 { +- reg = <0x0 0x98b00000 0x0 0x10000>; +- no-map; +- }; +- +- ipa_gsi_mem: memory@98b10000 { +- reg = <0x0 0x98b10000 0x0 0x5000>; +- no-map; +- }; +- +- gpu_mem: memory@98b15000 { +- reg = <0x0 0x98b15000 0x0 0x2000>; +- no-map; +- }; +- +- spss_mem: memory@98c00000 { +- reg = <0x0 0x98c00000 0x0 0x100000>; +- no-map; +- }; +- +- cdsp_mem: memory@98d00000 { +- reg = <0x0 0x98d00000 0x0 0x1400000>; +- no-map; +- }; +- +- cont_splash_mem: memory@9c000000 { +- reg = <0x0 0x9c000000 0x0 0x2400000>; +- no-map; +- }; +- +- cdsp_sec_mem: memory@a4c00000 { +- reg = <0x0 0xa4c00000 0x0 0x3c00000>; +- no-map; +- }; +- +- ramoops@ffc00000 { +- compatible = "ramoops"; +- reg = <0x0 0xffc00000 0x0 0x100000>; +- record-size = <0x1000>; +- console-size = <0x40000>; +- msg-size = <0x20000 0x20000>; +- ecc-size = <16>; +- no-map; +- }; +- }; +-}; +- +-&adsp_mem { +- reg = <0x0 0x8be00000 0x0 0x1e00000>; +-}; +- +-&apps_rsc { +- pm8150-rpmh-regulators { +- compatible = "qcom,pm8150-rpmh-regulators"; +- qcom,pmic-id = "a"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- vdd-s9-supply = <&vph_pwr>; +- vdd-s10-supply = <&vph_pwr>; +- +- vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; +- vdd-l2-l10-supply = <&vreg_bob>; +- vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>; +- vdd-l6-l9-supply = <&vreg_s8c_1p3>; +- vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; +- vdd-l13-l16-l17-supply = <&vreg_bob>; +- +- vreg_s2a_0p6: smps2 { +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <600000>; +- regulator-initial-mode = ; +- }; +- +- vreg_s5a_1p9: smps5 { +- regulator-min-microvolt = <1904000>; +- regulator-max-microvolt = <2040000>; +- regulator-initial-mode = ; +- }; +- +- vreg_s6a_0p9: smps6 { +- regulator-min-microvolt = <920000>; +- regulator-max-microvolt = <1128000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l1a_0p75: ldo1 { +- regulator-min-microvolt = <752000>; +- regulator-max-microvolt = <752000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l2a_3p1: ldo2 { +- regulator-min-microvolt = <3072000>; +- regulator-max-microvolt = <3072000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3a_0p8: ldo3 { +- regulator-min-microvolt = <480000>; +- regulator-max-microvolt = <932000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5a_0p875: ldo5 { +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6a_1p2: ldo6 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7a_1p8: ldo7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l9a_1p2: ldo9 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10a_2p5: ldo10 { +- regulator-min-microvolt = <2504000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l11a_0p8: ldo11 { +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l12a_1p8: ldo12 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- /* L13 is unused. */ +- +- vreg_l14a_1p8: ldo14 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l15a_1p7: ldo15 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <1704000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l16a_2p7: ldo16 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l17a_3p0: ldo17 { +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l18a_0p8: ldo18 { +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <912000>; +- regulator-initial-mode = ; +- }; +- }; +- +- pm8150l-rpmh-regulators { +- compatible = "qcom,pm8150l-rpmh-regulators"; +- qcom,pmic-id = "c"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- +- vdd-l1-l8-supply = <&vreg_s4a_1p8>; +- vdd-l2-l3-supply = <&vreg_s8c_1p3>; +- vdd-l4-l5-l6-supply = <&vreg_bob>; +- vdd-l7-l11-supply = <&vreg_bob>; +- vdd-l9-l10-supply = <&vreg_bob>; +- +- vdd-bob-supply = <&vph_pwr>; +- vdd-flash-supply = <&vreg_bob>; +- vdd-rgb-supply = <&vreg_bob>; +- +- vreg_bob: bob { +- regulator-min-microvolt = <3350000>; +- regulator-max-microvolt = <4000000>; +- regulator-initial-mode = ; +- regulator-allow-bypass; +- }; +- +- vreg_s1c_1p1: smps1 { +- regulator-min-microvolt = <1128000>; +- regulator-max-microvolt = <1128000>; +- regulator-initial-mode = ; +- }; +- +- vreg_s8c_1p3: smps8 { +- regulator-min-microvolt = <1352000>; +- regulator-max-microvolt = <1352000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l1c_1p8: ldo1 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l2c_1p3: ldo2 { +- regulator-min-microvolt = <1304000>; +- regulator-max-microvolt = <1304000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3c_1p2: ldo3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l4c_1p8: ldo4 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5c_1p8: ldo5 { +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6c_2p9: ldo6 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- regulator-allow-set-load; +- }; +- +- vreg_l7c_3p0: ldo7 { +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <3104000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l8c_1p8: ldo8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l9c_2p9: ldo9 { +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- regulator-allow-set-load; +- }; +- +- vreg_l10c_3p3: ldo10 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l11c_3p3: ldo11 { +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- }; +- +- /* PM8009 is not present on these boards, even if downstream sources suggest so. */ +-}; +- +-&i2c4 { +- status = "okay"; +- +- /* Qcom SMB1355 @ c */ +- /* Qcom SMB1390 @ 10 */ +- /* NXP PN553 NFC @ 28 */ +- /* Qcom FSA4480 USB-C audio switch @ 43 */ +-}; +- +-&i2c7 { +- status = "okay"; +- +- /* AMS TCS3490 RGB+IR color sensor @ 72 */ +-}; +- +-&i2c10 { +- status = "okay"; +- +- /* Samsung touchscreen @ 48 */ +-}; +- +-&pon_pwrkey { +- status = "okay"; +-}; +- +-&qupv3_id_0 { +- status = "okay"; +-}; +- +-&qupv3_id_1 { +- status = "okay"; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <126 4>; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */ +-&ufs_mem_hc { status = "disabled"; }; +-&ufs_mem_phy { status = "disabled"; }; +- +-&usb_1 { +- status = "okay"; +-}; +- +-&usb_1_dwc3 { +- dr_mode = "peripheral"; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- vdda-pll-supply = <&vreg_l5a_0p875>; +- vdda33-supply = <&vreg_l2a_3p1>; +- vdda18-supply = <&vreg_l12a_1p8>; +-}; +- +-&usb_1_qmpphy { +- status = "okay"; +- vdda-phy-supply = <&vreg_l3c_1p2>; +- vdda-pll-supply = <&vreg_l18a_0p8>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sm8150.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sm8150.dtsi +deleted file mode 100644 +index ef0232c2cf45..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sm8150.dtsi ++++ /dev/null +@@ -1,4341 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. +- * Copyright (c) 2019, Linaro Limited +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&intc>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- chosen { }; +- +- clocks { +- xo_board: xo-board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <38400000>; +- clock-output-names = "xo_board"; +- }; +- +- sleep_clk: sleep-clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32764>; +- clock-output-names = "sleep_clk"; +- }; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- CPU0: cpu@0 { +- device_type = "cpu"; +- compatible = "qcom,kryo485"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- capacity-dmips-mhz = <488>; +- dynamic-power-coefficient = <232>; +- next-level-cache = <&L2_0>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- operating-points-v2 = <&cpu0_opp_table>; +- interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- power-domains = <&CPU_PD0>; +- power-domain-names = "psci"; +- #cooling-cells = <2>; +- L2_0: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- L3_0: l3-cache { +- compatible = "cache"; +- }; +- }; +- }; +- +- CPU1: cpu@100 { +- device_type = "cpu"; +- compatible = "qcom,kryo485"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- capacity-dmips-mhz = <488>; +- dynamic-power-coefficient = <232>; +- next-level-cache = <&L2_100>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- operating-points-v2 = <&cpu0_opp_table>; +- interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- power-domains = <&CPU_PD1>; +- power-domain-names = "psci"; +- #cooling-cells = <2>; +- L2_100: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- +- }; +- +- CPU2: cpu@200 { +- device_type = "cpu"; +- compatible = "qcom,kryo485"; +- reg = <0x0 0x200>; +- enable-method = "psci"; +- capacity-dmips-mhz = <488>; +- dynamic-power-coefficient = <232>; +- next-level-cache = <&L2_200>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- operating-points-v2 = <&cpu0_opp_table>; +- interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- power-domains = <&CPU_PD2>; +- power-domain-names = "psci"; +- #cooling-cells = <2>; +- L2_200: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU3: cpu@300 { +- device_type = "cpu"; +- compatible = "qcom,kryo485"; +- reg = <0x0 0x300>; +- enable-method = "psci"; +- capacity-dmips-mhz = <488>; +- dynamic-power-coefficient = <232>; +- next-level-cache = <&L2_300>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- operating-points-v2 = <&cpu0_opp_table>; +- interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- power-domains = <&CPU_PD3>; +- power-domain-names = "psci"; +- #cooling-cells = <2>; +- L2_300: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU4: cpu@400 { +- device_type = "cpu"; +- compatible = "qcom,kryo485"; +- reg = <0x0 0x400>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <369>; +- next-level-cache = <&L2_400>; +- qcom,freq-domain = <&cpufreq_hw 1>; +- operating-points-v2 = <&cpu4_opp_table>; +- interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- power-domains = <&CPU_PD4>; +- power-domain-names = "psci"; +- #cooling-cells = <2>; +- L2_400: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU5: cpu@500 { +- device_type = "cpu"; +- compatible = "qcom,kryo485"; +- reg = <0x0 0x500>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <369>; +- next-level-cache = <&L2_500>; +- qcom,freq-domain = <&cpufreq_hw 1>; +- operating-points-v2 = <&cpu4_opp_table>; +- interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- power-domains = <&CPU_PD5>; +- power-domain-names = "psci"; +- #cooling-cells = <2>; +- L2_500: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU6: cpu@600 { +- device_type = "cpu"; +- compatible = "qcom,kryo485"; +- reg = <0x0 0x600>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <369>; +- next-level-cache = <&L2_600>; +- qcom,freq-domain = <&cpufreq_hw 1>; +- operating-points-v2 = <&cpu4_opp_table>; +- interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- power-domains = <&CPU_PD6>; +- power-domain-names = "psci"; +- #cooling-cells = <2>; +- L2_600: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU7: cpu@700 { +- device_type = "cpu"; +- compatible = "qcom,kryo485"; +- reg = <0x0 0x700>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <421>; +- next-level-cache = <&L2_700>; +- qcom,freq-domain = <&cpufreq_hw 2>; +- operating-points-v2 = <&cpu7_opp_table>; +- interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, +- <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; +- power-domains = <&CPU_PD7>; +- power-domain-names = "psci"; +- #cooling-cells = <2>; +- L2_700: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&CPU0>; +- }; +- +- core1 { +- cpu = <&CPU1>; +- }; +- +- core2 { +- cpu = <&CPU2>; +- }; +- +- core3 { +- cpu = <&CPU3>; +- }; +- +- core4 { +- cpu = <&CPU4>; +- }; +- +- core5 { +- cpu = <&CPU5>; +- }; +- +- core6 { +- cpu = <&CPU6>; +- }; +- +- core7 { +- cpu = <&CPU7>; +- }; +- }; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "little-rail-power-collapse"; +- arm,psci-suspend-param = <0x40000004>; +- entry-latency-us = <355>; +- exit-latency-us = <909>; +- min-residency-us = <3934>; +- local-timer-stop; +- }; +- +- BIG_CPU_SLEEP_0: cpu-sleep-1-0 { +- compatible = "arm,idle-state"; +- idle-state-name = "big-rail-power-collapse"; +- arm,psci-suspend-param = <0x40000004>; +- entry-latency-us = <241>; +- exit-latency-us = <1461>; +- min-residency-us = <4488>; +- local-timer-stop; +- }; +- }; +- +- domain-idle-states { +- CLUSTER_SLEEP_0: cluster-sleep-0 { +- compatible = "domain-idle-state"; +- idle-state-name = "cluster-power-collapse"; +- arm,psci-suspend-param = <0x4100c244>; +- entry-latency-us = <3263>; +- exit-latency-us = <6562>; +- min-residency-us = <9987>; +- local-timer-stop; +- }; +- }; +- }; +- +- cpu0_opp_table: cpu0_opp_table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- cpu0_opp1: opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-peak-kBps = <800000 9600000>; +- }; +- +- cpu0_opp2: opp-403200000 { +- opp-hz = /bits/ 64 <403200000>; +- opp-peak-kBps = <800000 9600000>; +- }; +- +- cpu0_opp3: opp-499200000 { +- opp-hz = /bits/ 64 <499200000>; +- opp-peak-kBps = <800000 12902400>; +- }; +- +- cpu0_opp4: opp-576000000 { +- opp-hz = /bits/ 64 <576000000>; +- opp-peak-kBps = <800000 12902400>; +- }; +- +- cpu0_opp5: opp-672000000 { +- opp-hz = /bits/ 64 <672000000>; +- opp-peak-kBps = <800000 15974400>; +- }; +- +- cpu0_opp6: opp-768000000 { +- opp-hz = /bits/ 64 <768000000>; +- opp-peak-kBps = <1804000 19660800>; +- }; +- +- cpu0_opp7: opp-844800000 { +- opp-hz = /bits/ 64 <844800000>; +- opp-peak-kBps = <1804000 19660800>; +- }; +- +- cpu0_opp8: opp-940800000 { +- opp-hz = /bits/ 64 <940800000>; +- opp-peak-kBps = <1804000 22732800>; +- }; +- +- cpu0_opp9: opp-1036800000 { +- opp-hz = /bits/ 64 <1036800000>; +- opp-peak-kBps = <1804000 22732800>; +- }; +- +- cpu0_opp10: opp-1113600000 { +- opp-hz = /bits/ 64 <1113600000>; +- opp-peak-kBps = <2188000 25804800>; +- }; +- +- cpu0_opp11: opp-1209600000 { +- opp-hz = /bits/ 64 <1209600000>; +- opp-peak-kBps = <2188000 31948800>; +- }; +- +- cpu0_opp12: opp-1305600000 { +- opp-hz = /bits/ 64 <1305600000>; +- opp-peak-kBps = <3072000 31948800>; +- }; +- +- cpu0_opp13: opp-1382400000 { +- opp-hz = /bits/ 64 <1382400000>; +- opp-peak-kBps = <3072000 31948800>; +- }; +- +- cpu0_opp14: opp-1478400000 { +- opp-hz = /bits/ 64 <1478400000>; +- opp-peak-kBps = <3072000 31948800>; +- }; +- +- cpu0_opp15: opp-1555200000 { +- opp-hz = /bits/ 64 <1555200000>; +- opp-peak-kBps = <3072000 40550400>; +- }; +- +- cpu0_opp16: opp-1632000000 { +- opp-hz = /bits/ 64 <1632000000>; +- opp-peak-kBps = <3072000 40550400>; +- }; +- +- cpu0_opp17: opp-1708800000 { +- opp-hz = /bits/ 64 <1708800000>; +- opp-peak-kBps = <3072000 43008000>; +- }; +- +- cpu0_opp18: opp-1785600000 { +- opp-hz = /bits/ 64 <1785600000>; +- opp-peak-kBps = <3072000 43008000>; +- }; +- }; +- +- cpu4_opp_table: cpu4_opp_table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- cpu4_opp1: opp-710400000 { +- opp-hz = /bits/ 64 <710400000>; +- opp-peak-kBps = <1804000 15974400>; +- }; +- +- cpu4_opp2: opp-825600000 { +- opp-hz = /bits/ 64 <825600000>; +- opp-peak-kBps = <2188000 19660800>; +- }; +- +- cpu4_opp3: opp-940800000 { +- opp-hz = /bits/ 64 <940800000>; +- opp-peak-kBps = <2188000 22732800>; +- }; +- +- cpu4_opp4: opp-1056000000 { +- opp-hz = /bits/ 64 <1056000000>; +- opp-peak-kBps = <3072000 25804800>; +- }; +- +- cpu4_opp5: opp-1171200000 { +- opp-hz = /bits/ 64 <1171200000>; +- opp-peak-kBps = <3072000 31948800>; +- }; +- +- cpu4_opp6: opp-1286400000 { +- opp-hz = /bits/ 64 <1286400000>; +- opp-peak-kBps = <4068000 31948800>; +- }; +- +- cpu4_opp7: opp-1401600000 { +- opp-hz = /bits/ 64 <1401600000>; +- opp-peak-kBps = <4068000 31948800>; +- }; +- +- cpu4_opp8: opp-1497600000 { +- opp-hz = /bits/ 64 <1497600000>; +- opp-peak-kBps = <4068000 40550400>; +- }; +- +- cpu4_opp9: opp-1612800000 { +- opp-hz = /bits/ 64 <1612800000>; +- opp-peak-kBps = <4068000 40550400>; +- }; +- +- cpu4_opp10: opp-1708800000 { +- opp-hz = /bits/ 64 <1708800000>; +- opp-peak-kBps = <4068000 43008000>; +- }; +- +- cpu4_opp11: opp-1804800000 { +- opp-hz = /bits/ 64 <1804800000>; +- opp-peak-kBps = <6220000 43008000>; +- }; +- +- cpu4_opp12: opp-1920000000 { +- opp-hz = /bits/ 64 <1920000000>; +- opp-peak-kBps = <6220000 49152000>; +- }; +- +- cpu4_opp13: opp-2016000000 { +- opp-hz = /bits/ 64 <2016000000>; +- opp-peak-kBps = <7216000 49152000>; +- }; +- +- cpu4_opp14: opp-2131200000 { +- opp-hz = /bits/ 64 <2131200000>; +- opp-peak-kBps = <8368000 49152000>; +- }; +- +- cpu4_opp15: opp-2227200000 { +- opp-hz = /bits/ 64 <2227200000>; +- opp-peak-kBps = <8368000 51609600>; +- }; +- +- cpu4_opp16: opp-2323200000 { +- opp-hz = /bits/ 64 <2323200000>; +- opp-peak-kBps = <8368000 51609600>; +- }; +- +- cpu4_opp17: opp-2419200000 { +- opp-hz = /bits/ 64 <2419200000>; +- opp-peak-kBps = <8368000 51609600>; +- }; +- }; +- +- cpu7_opp_table: cpu7_opp_table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- cpu7_opp1: opp-825600000 { +- opp-hz = /bits/ 64 <825600000>; +- opp-peak-kBps = <2188000 19660800>; +- }; +- +- cpu7_opp2: opp-940800000 { +- opp-hz = /bits/ 64 <940800000>; +- opp-peak-kBps = <2188000 22732800>; +- }; +- +- cpu7_opp3: opp-1056000000 { +- opp-hz = /bits/ 64 <1056000000>; +- opp-peak-kBps = <3072000 25804800>; +- }; +- +- cpu7_opp4: opp-1171200000 { +- opp-hz = /bits/ 64 <1171200000>; +- opp-peak-kBps = <3072000 31948800>; +- }; +- +- cpu7_opp5: opp-1286400000 { +- opp-hz = /bits/ 64 <1286400000>; +- opp-peak-kBps = <4068000 31948800>; +- }; +- +- cpu7_opp6: opp-1401600000 { +- opp-hz = /bits/ 64 <1401600000>; +- opp-peak-kBps = <4068000 31948800>; +- }; +- +- cpu7_opp7: opp-1497600000 { +- opp-hz = /bits/ 64 <1497600000>; +- opp-peak-kBps = <4068000 40550400>; +- }; +- +- cpu7_opp8: opp-1612800000 { +- opp-hz = /bits/ 64 <1612800000>; +- opp-peak-kBps = <4068000 40550400>; +- }; +- +- cpu7_opp9: opp-1708800000 { +- opp-hz = /bits/ 64 <1708800000>; +- opp-peak-kBps = <4068000 43008000>; +- }; +- +- cpu7_opp10: opp-1804800000 { +- opp-hz = /bits/ 64 <1804800000>; +- opp-peak-kBps = <6220000 43008000>; +- }; +- +- cpu7_opp11: opp-1920000000 { +- opp-hz = /bits/ 64 <1920000000>; +- opp-peak-kBps = <6220000 49152000>; +- }; +- +- cpu7_opp12: opp-2016000000 { +- opp-hz = /bits/ 64 <2016000000>; +- opp-peak-kBps = <7216000 49152000>; +- }; +- +- cpu7_opp13: opp-2131200000 { +- opp-hz = /bits/ 64 <2131200000>; +- opp-peak-kBps = <8368000 49152000>; +- }; +- +- cpu7_opp14: opp-2227200000 { +- opp-hz = /bits/ 64 <2227200000>; +- opp-peak-kBps = <8368000 51609600>; +- }; +- +- cpu7_opp15: opp-2323200000 { +- opp-hz = /bits/ 64 <2323200000>; +- opp-peak-kBps = <8368000 51609600>; +- }; +- +- cpu7_opp16: opp-2419200000 { +- opp-hz = /bits/ 64 <2419200000>; +- opp-peak-kBps = <8368000 51609600>; +- }; +- +- cpu7_opp17: opp-2534400000 { +- opp-hz = /bits/ 64 <2534400000>; +- opp-peak-kBps = <8368000 51609600>; +- }; +- +- cpu7_opp18: opp-2649600000 { +- opp-hz = /bits/ 64 <2649600000>; +- opp-peak-kBps = <8368000 51609600>; +- }; +- +- cpu7_opp19: opp-2745600000 { +- opp-hz = /bits/ 64 <2745600000>; +- opp-peak-kBps = <8368000 51609600>; +- }; +- +- cpu7_opp20: opp-2841600000 { +- opp-hz = /bits/ 64 <2841600000>; +- opp-peak-kBps = <8368000 51609600>; +- }; +- }; +- +- firmware { +- scm: scm { +- compatible = "qcom,scm-sm8150", "qcom,scm"; +- #reset-cells = <1>; +- }; +- }; +- +- tcsr_mutex: hwlock { +- compatible = "qcom,tcsr-mutex"; +- syscon = <&tcsr_mutex_regs 0 0x1000>; +- #hwlock-cells = <1>; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- /* We expect the bootloader to fill in the size */ +- reg = <0x0 0x80000000 0x0 0x0>; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- +- CPU_PD0: cpu0 { +- #power-domain-cells = <0>; +- power-domains = <&CLUSTER_PD>; +- domain-idle-states = <&LITTLE_CPU_SLEEP_0>; +- }; +- +- CPU_PD1: cpu1 { +- #power-domain-cells = <0>; +- power-domains = <&CLUSTER_PD>; +- domain-idle-states = <&LITTLE_CPU_SLEEP_0>; +- }; +- +- CPU_PD2: cpu2 { +- #power-domain-cells = <0>; +- power-domains = <&CLUSTER_PD>; +- domain-idle-states = <&LITTLE_CPU_SLEEP_0>; +- }; +- +- CPU_PD3: cpu3 { +- #power-domain-cells = <0>; +- power-domains = <&CLUSTER_PD>; +- domain-idle-states = <&LITTLE_CPU_SLEEP_0>; +- }; +- +- CPU_PD4: cpu4 { +- #power-domain-cells = <0>; +- power-domains = <&CLUSTER_PD>; +- domain-idle-states = <&BIG_CPU_SLEEP_0>; +- }; +- +- CPU_PD5: cpu5 { +- #power-domain-cells = <0>; +- power-domains = <&CLUSTER_PD>; +- domain-idle-states = <&BIG_CPU_SLEEP_0>; +- }; +- +- CPU_PD6: cpu6 { +- #power-domain-cells = <0>; +- power-domains = <&CLUSTER_PD>; +- domain-idle-states = <&BIG_CPU_SLEEP_0>; +- }; +- +- CPU_PD7: cpu7 { +- #power-domain-cells = <0>; +- power-domains = <&CLUSTER_PD>; +- domain-idle-states = <&BIG_CPU_SLEEP_0>; +- }; +- +- CLUSTER_PD: cpu-cluster0 { +- #power-domain-cells = <0>; +- domain-idle-states = <&CLUSTER_SLEEP_0>; +- }; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- hyp_mem: memory@85700000 { +- reg = <0x0 0x85700000 0x0 0x600000>; +- no-map; +- }; +- +- xbl_mem: memory@85d00000 { +- reg = <0x0 0x85d00000 0x0 0x140000>; +- no-map; +- }; +- +- aop_mem: memory@85f00000 { +- reg = <0x0 0x85f00000 0x0 0x20000>; +- no-map; +- }; +- +- aop_cmd_db: memory@85f20000 { +- compatible = "qcom,cmd-db"; +- reg = <0x0 0x85f20000 0x0 0x20000>; +- no-map; +- }; +- +- smem_mem: memory@86000000 { +- reg = <0x0 0x86000000 0x0 0x200000>; +- no-map; +- }; +- +- tz_mem: memory@86200000 { +- reg = <0x0 0x86200000 0x0 0x3900000>; +- no-map; +- }; +- +- rmtfs_mem: memory@89b00000 { +- compatible = "qcom,rmtfs-mem"; +- reg = <0x0 0x89b00000 0x0 0x200000>; +- no-map; +- +- qcom,client-id = <1>; +- qcom,vmid = <15>; +- }; +- +- camera_mem: memory@8b700000 { +- reg = <0x0 0x8b700000 0x0 0x500000>; +- no-map; +- }; +- +- wlan_mem: memory@8bc00000 { +- reg = <0x0 0x8bc00000 0x0 0x180000>; +- no-map; +- }; +- +- npu_mem: memory@8bd80000 { +- reg = <0x0 0x8bd80000 0x0 0x80000>; +- no-map; +- }; +- +- adsp_mem: memory@8be00000 { +- reg = <0x0 0x8be00000 0x0 0x1a00000>; +- no-map; +- }; +- +- mpss_mem: memory@8d800000 { +- reg = <0x0 0x8d800000 0x0 0x9600000>; +- no-map; +- }; +- +- venus_mem: memory@96e00000 { +- reg = <0x0 0x96e00000 0x0 0x500000>; +- no-map; +- }; +- +- slpi_mem: memory@97300000 { +- reg = <0x0 0x97300000 0x0 0x1400000>; +- no-map; +- }; +- +- ipa_fw_mem: memory@98700000 { +- reg = <0x0 0x98700000 0x0 0x10000>; +- no-map; +- }; +- +- ipa_gsi_mem: memory@98710000 { +- reg = <0x0 0x98710000 0x0 0x5000>; +- no-map; +- }; +- +- gpu_mem: memory@98715000 { +- reg = <0x0 0x98715000 0x0 0x2000>; +- no-map; +- }; +- +- spss_mem: memory@98800000 { +- reg = <0x0 0x98800000 0x0 0x100000>; +- no-map; +- }; +- +- cdsp_mem: memory@98900000 { +- reg = <0x0 0x98900000 0x0 0x1400000>; +- no-map; +- }; +- +- qseecom_mem: memory@9e400000 { +- reg = <0x0 0x9e400000 0x0 0x1400000>; +- no-map; +- }; +- }; +- +- smem { +- compatible = "qcom,smem"; +- memory-region = <&smem_mem>; +- hwlocks = <&tcsr_mutex 3>; +- }; +- +- smp2p-cdsp { +- compatible = "qcom,smp2p"; +- qcom,smem = <94>, <432>; +- +- interrupts = ; +- +- mboxes = <&apss_shared 6>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <5>; +- +- cdsp_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- cdsp_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-lpass { +- compatible = "qcom,smp2p"; +- qcom,smem = <443>, <429>; +- +- interrupts = ; +- +- mboxes = <&apss_shared 10>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <2>; +- +- adsp_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- adsp_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-mpss { +- compatible = "qcom,smp2p"; +- qcom,smem = <435>, <428>; +- +- interrupts = ; +- +- mboxes = <&apss_shared 14>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <1>; +- +- modem_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- modem_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-slpi { +- compatible = "qcom,smp2p"; +- qcom,smem = <481>, <430>; +- +- interrupts = ; +- +- mboxes = <&apss_shared 26>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <3>; +- +- slpi_smp2p_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- slpi_smp2p_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- soc: soc@0 { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0 0 0 0 0x10 0>; +- dma-ranges = <0 0 0 0 0x10 0>; +- compatible = "simple-bus"; +- +- gcc: clock-controller@100000 { +- compatible = "qcom,gcc-sm8150"; +- reg = <0x0 0x00100000 0x0 0x1f0000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- clock-names = "bi_tcxo", +- "sleep_clk"; +- clocks = <&rpmhcc RPMH_CXO_CLK>, +- <&sleep_clk>; +- }; +- +- gpi_dma0: dma-controller@800000 { +- compatible = "qcom,sm8150-gpi-dma"; +- reg = <0 0x800000 0 0x60000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- dma-channels = <13>; +- dma-channel-mask = <0xfa>; +- iommus = <&apps_smmu 0x00d6 0x0>; +- #dma-cells = <3>; +- status = "disabled"; +- }; +- +- qupv3_id_0: geniqup@8c0000 { +- compatible = "qcom,geni-se-qup"; +- reg = <0x0 0x008c0000 0x0 0x6000>; +- clock-names = "m-ahb", "s-ahb"; +- clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, +- <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; +- iommus = <&apps_smmu 0xc3 0x0>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "disabled"; +- +- i2c0: i2c@880000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00880000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c0_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi0: spi@880000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x880000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi0_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@884000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00884000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c1_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi1: spi@884000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x884000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi1_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@888000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00888000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c2_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi2: spi@888000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x888000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi2_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@88c000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x0088c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c3_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi3: spi@88c000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x88c000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi3_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@890000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00890000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c4_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi4: spi@890000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x890000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi4_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c5: i2c@894000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00894000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c5_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi5: spi@894000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x894000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi5_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c6: i2c@898000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00898000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c6_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi6: spi@898000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x898000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi6_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c7: i2c@89c000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x0089c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c7_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi7: spi@89c000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x89c000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi7_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- gpi_dma1: dma-controller@a00000 { +- compatible = "qcom,sm8150-gpi-dma"; +- reg = <0 0xa00000 0 0x60000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- dma-channels = <13>; +- dma-channel-mask = <0xfa>; +- iommus = <&apps_smmu 0x0616 0x0>; +- #dma-cells = <3>; +- status = "disabled"; +- }; +- +- qupv3_id_1: geniqup@ac0000 { +- compatible = "qcom,geni-se-qup"; +- reg = <0x0 0x00ac0000 0x0 0x6000>; +- clock-names = "m-ahb", "s-ahb"; +- clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, +- <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; +- iommus = <&apps_smmu 0x603 0x0>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "disabled"; +- +- i2c8: i2c@a80000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a80000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c8_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi8: spi@a80000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0xa80000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi8_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c9: i2c@a84000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a84000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c9_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi9: spi@a84000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0xa84000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi9_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c10: i2c@a88000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a88000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c10_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi10: spi@a88000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0xa88000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi10_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c11: i2c@a8c000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a8c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c11_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi11: spi@a8c000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0xa8c000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi11_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- uart2: serial@a90000 { +- compatible = "qcom,geni-debug-uart"; +- reg = <0x0 0x00a90000 0x0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; +- interrupts = ; +- status = "disabled"; +- }; +- +- i2c12: i2c@a90000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a90000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c12_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi12: spi@a90000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0xa90000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi12_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c16: i2c@94000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x0094000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c16_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi16: spi@a94000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0xa94000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi16_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- gpi_dma2: dma-controller@c00000 { +- compatible = "qcom,sm8150-gpi-dma"; +- reg = <0 0xc00000 0 0x60000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- dma-channels = <13>; +- dma-channel-mask = <0xfa>; +- iommus = <&apps_smmu 0x07b6 0x0>; +- #dma-cells = <3>; +- status = "disabled"; +- }; +- +- qupv3_id_2: geniqup@cc0000 { +- compatible = "qcom,geni-se-qup"; +- reg = <0x0 0x00cc0000 0x0 0x6000>; +- +- clock-names = "m-ahb", "s-ahb"; +- clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, +- <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; +- iommus = <&apps_smmu 0x7a3 0x0>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "disabled"; +- +- i2c17: i2c@c80000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00c80000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c17_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi17: spi@c80000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0xc80000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi17_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c18: i2c@c84000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00c84000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c18_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi18: spi@c84000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0xc84000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi18_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c19: i2c@c88000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00c88000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c19_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi19: spi@c88000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0xc88000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi19_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c13: i2c@c8c000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00c8c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c13_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi13: spi@c8c000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0xc8c000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi13_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c14: i2c@c90000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00c90000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c14_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi14: spi@c90000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0xc90000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi14_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c15: i2c@c94000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00c94000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c15_default>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi15: spi@c94000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0xc94000 0 0x4000>; +- reg-names = "se"; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_spi15_default>; +- interrupts = ; +- spi-max-frequency = <50000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- config_noc: interconnect@1500000 { +- compatible = "qcom,sm8150-config-noc"; +- reg = <0 0x01500000 0 0x7400>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- system_noc: interconnect@1620000 { +- compatible = "qcom,sm8150-system-noc"; +- reg = <0 0x01620000 0 0x19400>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- mc_virt: interconnect@163a000 { +- compatible = "qcom,sm8150-mc-virt"; +- reg = <0 0x0163a000 0 0x1000>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- aggre1_noc: interconnect@16e0000 { +- compatible = "qcom,sm8150-aggre1-noc"; +- reg = <0 0x016e0000 0 0xd080>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- aggre2_noc: interconnect@1700000 { +- compatible = "qcom,sm8150-aggre2-noc"; +- reg = <0 0x01700000 0 0x20000>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- compute_noc: interconnect@1720000 { +- compatible = "qcom,sm8150-compute-noc"; +- reg = <0 0x01720000 0 0x7000>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- mmss_noc: interconnect@1740000 { +- compatible = "qcom,sm8150-mmss-noc"; +- reg = <0 0x01740000 0 0x1c100>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- system-cache-controller@9200000 { +- compatible = "qcom,sm8150-llcc"; +- reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; +- reg-names = "llcc_base", "llcc_broadcast_base"; +- interrupts = ; +- }; +- +- ufs_mem_hc: ufshc@1d84000 { +- compatible = "qcom,sm8150-ufshc", "qcom,ufshc", +- "jedec,ufs-2.0"; +- reg = <0 0x01d84000 0 0x2500>, +- <0 0x01d90000 0 0x8000>; +- reg-names = "std", "ice"; +- interrupts = ; +- phys = <&ufs_mem_phy_lanes>; +- phy-names = "ufsphy"; +- lanes-per-direction = <2>; +- #reset-cells = <1>; +- resets = <&gcc GCC_UFS_PHY_BCR>; +- reset-names = "rst"; +- +- iommus = <&apps_smmu 0x300 0>; +- +- clock-names = +- "core_clk", +- "bus_aggr_clk", +- "iface_clk", +- "core_clk_unipro", +- "ref_clk", +- "tx_lane0_sync_clk", +- "rx_lane0_sync_clk", +- "rx_lane1_sync_clk", +- "ice_core_clk"; +- clocks = +- <&gcc GCC_UFS_PHY_AXI_CLK>, +- <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, +- <&gcc GCC_UFS_PHY_AHB_CLK>, +- <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, +- <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, +- <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, +- <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, +- <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; +- freq-table-hz = +- <37500000 300000000>, +- <0 0>, +- <0 0>, +- <37500000 300000000>, +- <0 0>, +- <0 0>, +- <0 0>, +- <0 0>, +- <0 300000000>; +- +- status = "disabled"; +- }; +- +- ufs_mem_phy: phy@1d87000 { +- compatible = "qcom,sm8150-qmp-ufs-phy"; +- reg = <0 0x01d87000 0 0x1c0>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- clock-names = "ref", +- "ref_aux"; +- clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, +- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; +- +- resets = <&ufs_mem_hc 0>; +- reset-names = "ufsphy"; +- status = "disabled"; +- +- ufs_mem_phy_lanes: lanes@1d87400 { +- reg = <0 0x01d87400 0 0x108>, +- <0 0x01d87600 0 0x1e0>, +- <0 0x01d87c00 0 0x1dc>, +- <0 0x01d87800 0 0x108>, +- <0 0x01d87a00 0 0x1e0>; +- #phy-cells = <0>; +- }; +- }; +- +- ipa_virt: interconnect@1e00000 { +- compatible = "qcom,sm8150-ipa-virt"; +- reg = <0 0x01e00000 0 0x1000>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- tcsr_mutex_regs: syscon@1f40000 { +- compatible = "syscon"; +- reg = <0x0 0x01f40000 0x0 0x40000>; +- }; +- +- remoteproc_slpi: remoteproc@2400000 { +- compatible = "qcom,sm8150-slpi-pas"; +- reg = <0x0 0x02400000 0x0 0x4040>; +- +- interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, +- <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack"; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "xo"; +- +- power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, +- <&rpmhpd 3>, +- <&rpmhpd 2>; +- power-domain-names = "load_state", "lcx", "lmx"; +- +- memory-region = <&slpi_mem>; +- +- qcom,smem-states = <&slpi_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- status = "disabled"; +- +- glink-edge { +- interrupts = ; +- label = "dsps"; +- qcom,remote-pid = <3>; +- mboxes = <&apss_shared 24>; +- }; +- }; +- +- gpu: gpu@2c00000 { +- /* +- * note: the amd,imageon compatible makes it possible +- * to use the drm/msm driver without the display node, +- * make sure to remove it when display node is added +- */ +- compatible = "qcom,adreno-640.1", +- "qcom,adreno", +- "amd,imageon"; +- #stream-id-cells = <16>; +- +- reg = <0 0x02c00000 0 0x40000>; +- reg-names = "kgsl_3d0_reg_memory"; +- +- interrupts = ; +- +- iommus = <&adreno_smmu 0 0x401>; +- +- operating-points-v2 = <&gpu_opp_table>; +- +- qcom,gmu = <&gmu>; +- +- status = "disabled"; +- +- zap-shader { +- memory-region = <&gpu_mem>; +- }; +- +- /* note: downstream checks gpu binning for 675 Mhz */ +- gpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-675000000 { +- opp-hz = /bits/ 64 <675000000>; +- opp-level = ; +- }; +- +- opp-585000000 { +- opp-hz = /bits/ 64 <585000000>; +- opp-level = ; +- }; +- +- opp-499200000 { +- opp-hz = /bits/ 64 <499200000>; +- opp-level = ; +- }; +- +- opp-427000000 { +- opp-hz = /bits/ 64 <427000000>; +- opp-level = ; +- }; +- +- opp-345000000 { +- opp-hz = /bits/ 64 <345000000>; +- opp-level = ; +- }; +- +- opp-257000000 { +- opp-hz = /bits/ 64 <257000000>; +- opp-level = ; +- }; +- }; +- }; +- +- gmu: gmu@2c6a000 { +- compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; +- +- reg = <0 0x02c6a000 0 0x30000>, +- <0 0x0b290000 0 0x10000>, +- <0 0x0b490000 0 0x10000>; +- reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; +- +- interrupts = , +- ; +- interrupt-names = "hfi", "gmu"; +- +- clocks = <&gpucc GPU_CC_AHB_CLK>, +- <&gpucc GPU_CC_CX_GMU_CLK>, +- <&gpucc GPU_CC_CXO_CLK>, +- <&gcc GCC_DDRSS_GPU_AXI_CLK>, +- <&gcc GCC_GPU_MEMNOC_GFX_CLK>; +- clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; +- +- power-domains = <&gpucc GPU_CX_GDSC>, +- <&gpucc GPU_GX_GDSC>; +- power-domain-names = "cx", "gx"; +- +- iommus = <&adreno_smmu 5 0x400>; +- +- operating-points-v2 = <&gmu_opp_table>; +- +- status = "disabled"; +- +- gmu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- opp-level = ; +- }; +- }; +- }; +- +- gpucc: clock-controller@2c90000 { +- compatible = "qcom,sm8150-gpucc"; +- reg = <0 0x02c90000 0 0x9000>; +- clocks = <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_GPU_GPLL0_CLK_SRC>, +- <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; +- clock-names = "bi_tcxo", +- "gcc_gpu_gpll0_clk_src", +- "gcc_gpu_gpll0_div_clk_src"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- }; +- +- adreno_smmu: iommu@2ca0000 { +- compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; +- reg = <0 0x02ca0000 0 0x10000>; +- #iommu-cells = <2>; +- #global-interrupts = <1>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&gpucc GPU_CC_AHB_CLK>, +- <&gcc GCC_GPU_MEMNOC_GFX_CLK>, +- <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; +- clock-names = "ahb", "bus", "iface"; +- +- power-domains = <&gpucc GPU_CX_GDSC>; +- }; +- +- tlmm: pinctrl@3100000 { +- compatible = "qcom,sm8150-pinctrl"; +- reg = <0x0 0x03100000 0x0 0x300000>, +- <0x0 0x03500000 0x0 0x300000>, +- <0x0 0x03900000 0x0 0x300000>, +- <0x0 0x03D00000 0x0 0x300000>; +- reg-names = "west", "east", "north", "south"; +- interrupts = ; +- gpio-ranges = <&tlmm 0 0 176>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- qup_i2c0_default: qup-i2c0-default { +- mux { +- pins = "gpio0", "gpio1"; +- function = "qup0"; +- }; +- +- config { +- pins = "gpio0", "gpio1"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi0_default: qup-spi0-default { +- pins = "gpio0", "gpio1", "gpio2", "gpio3"; +- function = "qup0"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- qup_i2c1_default: qup-i2c1-default { +- mux { +- pins = "gpio114", "gpio115"; +- function = "qup1"; +- }; +- +- config { +- pins = "gpio114", "gpio115"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi1_default: qup-spi1-default { +- pins = "gpio114", "gpio115", "gpio116", "gpio117"; +- function = "qup1"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- qup_i2c2_default: qup-i2c2-default { +- mux { +- pins = "gpio126", "gpio127"; +- function = "qup2"; +- }; +- +- config { +- pins = "gpio126", "gpio127"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi2_default: qup-spi2-default { +- pins = "gpio126", "gpio127", "gpio128", "gpio129"; +- function = "qup2"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- qup_i2c3_default: qup-i2c3-default { +- mux { +- pins = "gpio144", "gpio145"; +- function = "qup3"; +- }; +- +- config { +- pins = "gpio144", "gpio145"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi3_default: qup-spi3-default { +- pins = "gpio144", "gpio145", "gpio146", "gpio147"; +- function = "qup3"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- qup_i2c4_default: qup-i2c4-default { +- mux { +- pins = "gpio51", "gpio52"; +- function = "qup4"; +- }; +- +- config { +- pins = "gpio51", "gpio52"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi4_default: qup-spi4-default { +- pins = "gpio51", "gpio52", "gpio53", "gpio54"; +- function = "qup4"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- qup_i2c5_default: qup-i2c5-default { +- mux { +- pins = "gpio121", "gpio122"; +- function = "qup5"; +- }; +- +- config { +- pins = "gpio121", "gpio122"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi5_default: qup-spi5-default { +- pins = "gpio119", "gpio120", "gpio121", "gpio122"; +- function = "qup5"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- qup_i2c6_default: qup-i2c6-default { +- mux { +- pins = "gpio6", "gpio7"; +- function = "qup6"; +- }; +- +- config { +- pins = "gpio6", "gpio7"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi6_default: qup-spi6_default { +- pins = "gpio4", "gpio5", "gpio6", "gpio7"; +- function = "qup6"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- qup_i2c7_default: qup-i2c7-default { +- mux { +- pins = "gpio98", "gpio99"; +- function = "qup7"; +- }; +- +- config { +- pins = "gpio98", "gpio99"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi7_default: qup-spi7_default { +- pins = "gpio98", "gpio99", "gpio100", "gpio101"; +- function = "qup7"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- qup_i2c8_default: qup-i2c8-default { +- mux { +- pins = "gpio88", "gpio89"; +- function = "qup8"; +- }; +- +- config { +- pins = "gpio88", "gpio89"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi8_default: qup-spi8-default { +- pins = "gpio88", "gpio89", "gpio90", "gpio91"; +- function = "qup8"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- qup_i2c9_default: qup-i2c9-default { +- mux { +- pins = "gpio39", "gpio40"; +- function = "qup9"; +- }; +- +- config { +- pins = "gpio39", "gpio40"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi9_default: qup-spi9-default { +- pins = "gpio39", "gpio40", "gpio41", "gpio42"; +- function = "qup9"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- qup_i2c10_default: qup-i2c10-default { +- mux { +- pins = "gpio9", "gpio10"; +- function = "qup10"; +- }; +- +- config { +- pins = "gpio9", "gpio10"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi10_default: qup-spi10-default { +- pins = "gpio9", "gpio10", "gpio11", "gpio12"; +- function = "qup10"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- qup_i2c11_default: qup-i2c11-default { +- mux { +- pins = "gpio94", "gpio95"; +- function = "qup11"; +- }; +- +- config { +- pins = "gpio94", "gpio95"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi11_default: qup-spi11-default { +- pins = "gpio92", "gpio93", "gpio94", "gpio95"; +- function = "qup11"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- qup_i2c12_default: qup-i2c12-default { +- mux { +- pins = "gpio83", "gpio84"; +- function = "qup12"; +- }; +- +- config { +- pins = "gpio83", "gpio84"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi12_default: qup-spi12-default { +- pins = "gpio83", "gpio84", "gpio85", "gpio86"; +- function = "qup12"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- qup_i2c13_default: qup-i2c13-default { +- mux { +- pins = "gpio43", "gpio44"; +- function = "qup13"; +- }; +- +- config { +- pins = "gpio43", "gpio44"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi13_default: qup-spi13-default { +- pins = "gpio43", "gpio44", "gpio45", "gpio46"; +- function = "qup13"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- qup_i2c14_default: qup-i2c14-default { +- mux { +- pins = "gpio47", "gpio48"; +- function = "qup14"; +- }; +- +- config { +- pins = "gpio47", "gpio48"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi14_default: qup-spi14-default { +- pins = "gpio47", "gpio48", "gpio49", "gpio50"; +- function = "qup14"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- qup_i2c15_default: qup-i2c15-default { +- mux { +- pins = "gpio27", "gpio28"; +- function = "qup15"; +- }; +- +- config { +- pins = "gpio27", "gpio28"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi15_default: qup-spi15-default { +- pins = "gpio27", "gpio28", "gpio29", "gpio30"; +- function = "qup15"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- qup_i2c16_default: qup-i2c16-default { +- mux { +- pins = "gpio86", "gpio85"; +- function = "qup16"; +- }; +- +- config { +- pins = "gpio86", "gpio85"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi16_default: qup-spi16-default { +- pins = "gpio83", "gpio84", "gpio85", "gpio86"; +- function = "qup16"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- qup_i2c17_default: qup-i2c17-default { +- mux { +- pins = "gpio55", "gpio56"; +- function = "qup17"; +- }; +- +- config { +- pins = "gpio55", "gpio56"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi17_default: qup-spi17-default { +- pins = "gpio55", "gpio56", "gpio57", "gpio58"; +- function = "qup17"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- qup_i2c18_default: qup-i2c18-default { +- mux { +- pins = "gpio23", "gpio24"; +- function = "qup18"; +- }; +- +- config { +- pins = "gpio23", "gpio24"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi18_default: qup-spi18-default { +- pins = "gpio23", "gpio24", "gpio25", "gpio26"; +- function = "qup18"; +- drive-strength = <6>; +- bias-disable; +- }; +- +- qup_i2c19_default: qup-i2c19-default { +- mux { +- pins = "gpio57", "gpio58"; +- function = "qup19"; +- }; +- +- config { +- pins = "gpio57", "gpio58"; +- drive-strength = <0x02>; +- bias-disable; +- }; +- }; +- +- qup_spi19_default: qup-spi19-default { +- pins = "gpio55", "gpio56", "gpio57", "gpio58"; +- function = "qup19"; +- drive-strength = <6>; +- bias-disable; +- }; +- }; +- +- remoteproc_mpss: remoteproc@4080000 { +- compatible = "qcom,sm8150-mpss-pas"; +- reg = <0x0 0x04080000 0x0 0x4040>; +- +- interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, +- <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", "handover", +- "stop-ack", "shutdown-ack"; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "xo"; +- +- power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, +- <&rpmhpd 7>, +- <&rpmhpd 0>; +- power-domain-names = "load_state", "cx", "mss"; +- +- memory-region = <&mpss_mem>; +- +- qcom,smem-states = <&modem_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- status = "disabled"; +- +- glink-edge { +- interrupts = ; +- label = "modem"; +- qcom,remote-pid = <1>; +- mboxes = <&apss_shared 12>; +- }; +- }; +- +- stm@6002000 { +- compatible = "arm,coresight-stm", "arm,primecell"; +- reg = <0 0x06002000 0 0x1000>, +- <0 0x16280000 0 0x180000>; +- reg-names = "stm-base", "stm-stimulus-base"; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- stm_out: endpoint { +- remote-endpoint = <&funnel0_in7>; +- }; +- }; +- }; +- }; +- +- funnel@6041000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x06041000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- funnel0_out: endpoint { +- remote-endpoint = <&merge_funnel_in0>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@7 { +- reg = <7>; +- funnel0_in7: endpoint { +- remote-endpoint = <&stm_out>; +- }; +- }; +- }; +- }; +- +- funnel@6042000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x06042000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- funnel1_out: endpoint { +- remote-endpoint = <&merge_funnel_in1>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@4 { +- reg = <4>; +- funnel1_in4: endpoint { +- remote-endpoint = <&swao_replicator_out>; +- }; +- }; +- }; +- }; +- +- funnel@6043000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x06043000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- funnel2_out: endpoint { +- remote-endpoint = <&merge_funnel_in2>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@2 { +- reg = <2>; +- funnel2_in2: endpoint { +- remote-endpoint = <&apss_merge_funnel_out>; +- }; +- }; +- }; +- }; +- +- funnel@6045000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x06045000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- merge_funnel_out: endpoint { +- remote-endpoint = <&etf_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- merge_funnel_in0: endpoint { +- remote-endpoint = <&funnel0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- merge_funnel_in1: endpoint { +- remote-endpoint = <&funnel1_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- merge_funnel_in2: endpoint { +- remote-endpoint = <&funnel2_out>; +- }; +- }; +- }; +- }; +- +- replicator@6046000 { +- compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; +- reg = <0 0x06046000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- replicator_out0: endpoint { +- remote-endpoint = <&etr_in>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- replicator_out1: endpoint { +- remote-endpoint = <&replicator1_in>; +- }; +- }; +- }; +- +- in-ports { +- port { +- replicator_in0: endpoint { +- remote-endpoint = <&etf_out>; +- }; +- }; +- }; +- }; +- +- etf@6047000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0x06047000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etf_out: endpoint { +- remote-endpoint = <&replicator_in0>; +- }; +- }; +- }; +- +- in-ports { +- port { +- etf_in: endpoint { +- remote-endpoint = <&merge_funnel_out>; +- }; +- }; +- }; +- }; +- +- etr@6048000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0x06048000 0 0x1000>; +- iommus = <&apps_smmu 0x05e0 0x0>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,scatter-gather; +- +- in-ports { +- port { +- etr_in: endpoint { +- remote-endpoint = <&replicator_out0>; +- }; +- }; +- }; +- }; +- +- replicator@604a000 { +- compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; +- reg = <0 0x0604a000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <1>; +- replicator1_out: endpoint { +- remote-endpoint = <&swao_funnel_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <1>; +- replicator1_in: endpoint { +- remote-endpoint = <&replicator_out1>; +- }; +- }; +- }; +- }; +- +- funnel@6b08000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x06b08000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- swao_funnel_out: endpoint { +- remote-endpoint = <&swao_etf_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@6 { +- reg = <6>; +- swao_funnel_in: endpoint { +- remote-endpoint = <&replicator1_out>; +- }; +- }; +- }; +- }; +- +- etf@6b09000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0x06b09000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- swao_etf_out: endpoint { +- remote-endpoint = <&swao_replicator_in>; +- }; +- }; +- }; +- +- in-ports { +- port { +- swao_etf_in: endpoint { +- remote-endpoint = <&swao_funnel_out>; +- }; +- }; +- }; +- }; +- +- replicator@6b0a000 { +- compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; +- reg = <0 0x06b0a000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- qcom,replicator-loses-context; +- +- out-ports { +- port { +- swao_replicator_out: endpoint { +- remote-endpoint = <&funnel1_in4>; +- }; +- }; +- }; +- +- in-ports { +- port { +- swao_replicator_in: endpoint { +- remote-endpoint = <&swao_etf_out>; +- }; +- }; +- }; +- }; +- +- etm@7040000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07040000 0 0x1000>; +- +- cpu = <&CPU0>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm0_out: endpoint { +- remote-endpoint = <&apss_funnel_in0>; +- }; +- }; +- }; +- }; +- +- etm@7140000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07140000 0 0x1000>; +- +- cpu = <&CPU1>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm1_out: endpoint { +- remote-endpoint = <&apss_funnel_in1>; +- }; +- }; +- }; +- }; +- +- etm@7240000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07240000 0 0x1000>; +- +- cpu = <&CPU2>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm2_out: endpoint { +- remote-endpoint = <&apss_funnel_in2>; +- }; +- }; +- }; +- }; +- +- etm@7340000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07340000 0 0x1000>; +- +- cpu = <&CPU3>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm3_out: endpoint { +- remote-endpoint = <&apss_funnel_in3>; +- }; +- }; +- }; +- }; +- +- etm@7440000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07440000 0 0x1000>; +- +- cpu = <&CPU4>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm4_out: endpoint { +- remote-endpoint = <&apss_funnel_in4>; +- }; +- }; +- }; +- }; +- +- etm@7540000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07540000 0 0x1000>; +- +- cpu = <&CPU5>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm5_out: endpoint { +- remote-endpoint = <&apss_funnel_in5>; +- }; +- }; +- }; +- }; +- +- etm@7640000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07640000 0 0x1000>; +- +- cpu = <&CPU6>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm6_out: endpoint { +- remote-endpoint = <&apss_funnel_in6>; +- }; +- }; +- }; +- }; +- +- etm@7740000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x07740000 0 0x1000>; +- +- cpu = <&CPU7>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- arm,coresight-loses-context-with-cpu; +- qcom,skip-power-up; +- +- out-ports { +- port { +- etm7_out: endpoint { +- remote-endpoint = <&apss_funnel_in7>; +- }; +- }; +- }; +- }; +- +- funnel@7800000 { /* APSS Funnel */ +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x07800000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- apss_funnel_out: endpoint { +- remote-endpoint = <&apss_merge_funnel_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- apss_funnel_in0: endpoint { +- remote-endpoint = <&etm0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- apss_funnel_in1: endpoint { +- remote-endpoint = <&etm1_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- apss_funnel_in2: endpoint { +- remote-endpoint = <&etm2_out>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- apss_funnel_in3: endpoint { +- remote-endpoint = <&etm3_out>; +- }; +- }; +- +- port@4 { +- reg = <4>; +- apss_funnel_in4: endpoint { +- remote-endpoint = <&etm4_out>; +- }; +- }; +- +- port@5 { +- reg = <5>; +- apss_funnel_in5: endpoint { +- remote-endpoint = <&etm5_out>; +- }; +- }; +- +- port@6 { +- reg = <6>; +- apss_funnel_in6: endpoint { +- remote-endpoint = <&etm6_out>; +- }; +- }; +- +- port@7 { +- reg = <7>; +- apss_funnel_in7: endpoint { +- remote-endpoint = <&etm7_out>; +- }; +- }; +- }; +- }; +- +- funnel@7810000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x07810000 0 0x1000>; +- +- clocks = <&aoss_qmp>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- apss_merge_funnel_out: endpoint { +- remote-endpoint = <&funnel2_in2>; +- }; +- }; +- }; +- +- in-ports { +- port { +- apss_merge_funnel_in: endpoint { +- remote-endpoint = <&apss_funnel_out>; +- }; +- }; +- }; +- }; +- +- remoteproc_cdsp: remoteproc@8300000 { +- compatible = "qcom,sm8150-cdsp-pas"; +- reg = <0x0 0x08300000 0x0 0x4040>; +- +- interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, +- <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack"; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "xo"; +- +- power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, +- <&rpmhpd 7>; +- power-domain-names = "load_state", "cx"; +- +- memory-region = <&cdsp_mem>; +- +- qcom,smem-states = <&cdsp_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- status = "disabled"; +- +- glink-edge { +- interrupts = ; +- label = "cdsp"; +- qcom,remote-pid = <5>; +- mboxes = <&apss_shared 4>; +- }; +- }; +- +- usb_1_hsphy: phy@88e2000 { +- compatible = "qcom,sm8150-usb-hs-phy", +- "qcom,usb-snps-hs-7nm-phy"; +- reg = <0 0x088e2000 0 0x400>; +- status = "disabled"; +- #phy-cells = <0>; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "ref"; +- +- resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; +- }; +- +- usb_2_hsphy: phy@88e3000 { +- compatible = "qcom,sm8150-usb-hs-phy", +- "qcom,usb-snps-hs-7nm-phy"; +- reg = <0 0x088e3000 0 0x400>; +- status = "disabled"; +- #phy-cells = <0>; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "ref"; +- +- resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; +- }; +- +- usb_1_qmpphy: phy@88e9000 { +- compatible = "qcom,sm8150-qmp-usb3-phy"; +- reg = <0 0x088e9000 0 0x18c>, +- <0 0x088e8000 0 0x10>; +- reg-names = "reg-base", "dp_com"; +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, +- <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_USB3_PRIM_CLKREF_CLK>, +- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; +- clock-names = "aux", "ref_clk_src", "ref", "com_aux"; +- +- resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, +- <&gcc GCC_USB3_PHY_PRIM_BCR>; +- reset-names = "phy", "common"; +- +- usb_1_ssphy: lanes@88e9200 { +- reg = <0 0x088e9200 0 0x200>, +- <0 0x088e9400 0 0x200>, +- <0 0x088e9c00 0 0x218>, +- <0 0x088e9600 0 0x200>, +- <0 0x088e9800 0 0x200>, +- <0 0x088e9a00 0 0x100>; +- #clock-cells = <0>; +- #phy-cells = <0>; +- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; +- clock-names = "pipe0"; +- clock-output-names = "usb3_phy_pipe_clk_src"; +- }; +- }; +- +- usb_2_qmpphy: phy@88eb000 { +- compatible = "qcom,sm8150-qmp-usb3-uni-phy"; +- reg = <0 0x088eb000 0 0x200>; +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, +- <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_USB3_SEC_CLKREF_CLK>, +- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; +- clock-names = "aux", "ref_clk_src", "ref", "com_aux"; +- +- resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, +- <&gcc GCC_USB3_PHY_SEC_BCR>; +- reset-names = "phy", "common"; +- +- usb_2_ssphy: lane@88eb200 { +- reg = <0 0x088eb200 0 0x200>, +- <0 0x088eb400 0 0x200>, +- <0 0x088eb800 0 0x800>, +- <0 0x088eb600 0 0x200>; +- #clock-cells = <0>; +- #phy-cells = <0>; +- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; +- clock-names = "pipe0"; +- clock-output-names = "usb3_uni_phy_pipe_clk_src"; +- }; +- }; +- +- dc_noc: interconnect@9160000 { +- compatible = "qcom,sm8150-dc-noc"; +- reg = <0 0x09160000 0 0x3200>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- gem_noc: interconnect@9680000 { +- compatible = "qcom,sm8150-gem-noc"; +- reg = <0 0x09680000 0 0x3e200>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- usb_1: usb@a6f8800 { +- compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; +- reg = <0 0x0a6f8800 0 0x400>; +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- dma-ranges; +- +- clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, +- <&gcc GCC_USB30_PRIM_MASTER_CLK>, +- <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, +- <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_PRIM_SLEEP_CLK>, +- <&gcc GCC_USB3_SEC_CLKREF_CLK>; +- clock-names = "cfg_noc", "core", "iface", "mock_utmi", +- "sleep", "xo"; +- +- assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_PRIM_MASTER_CLK>; +- assigned-clock-rates = <19200000>, <200000000>; +- +- interrupts = , +- , +- , +- ; +- interrupt-names = "hs_phy_irq", "ss_phy_irq", +- "dm_hs_phy_irq", "dp_hs_phy_irq"; +- +- power-domains = <&gcc USB30_PRIM_GDSC>; +- +- resets = <&gcc GCC_USB30_PRIM_BCR>; +- +- usb_1_dwc3: dwc3@a600000 { +- compatible = "snps,dwc3"; +- reg = <0 0x0a600000 0 0xcd00>; +- interrupts = ; +- iommus = <&apps_smmu 0x140 0>; +- snps,dis_u2_susphy_quirk; +- snps,dis_enblslpm_quirk; +- phys = <&usb_1_hsphy>, <&usb_1_ssphy>; +- phy-names = "usb2-phy", "usb3-phy"; +- }; +- }; +- +- usb_2: usb@a8f8800 { +- compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; +- reg = <0 0x0a8f8800 0 0x400>; +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- dma-ranges; +- +- clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, +- <&gcc GCC_USB30_SEC_MASTER_CLK>, +- <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, +- <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_SEC_SLEEP_CLK>, +- <&gcc GCC_USB3_SEC_CLKREF_CLK>; +- clock-names = "cfg_noc", "core", "iface", "mock_utmi", +- "sleep", "xo"; +- +- assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_SEC_MASTER_CLK>; +- assigned-clock-rates = <19200000>, <200000000>; +- +- interrupts = , +- , +- , +- ; +- interrupt-names = "hs_phy_irq", "ss_phy_irq", +- "dm_hs_phy_irq", "dp_hs_phy_irq"; +- +- power-domains = <&gcc USB30_SEC_GDSC>; +- +- resets = <&gcc GCC_USB30_SEC_BCR>; +- +- usb_2_dwc3: usb@a800000 { +- compatible = "snps,dwc3"; +- reg = <0 0x0a800000 0 0xcd00>; +- interrupts = ; +- iommus = <&apps_smmu 0x160 0>; +- snps,dis_u2_susphy_quirk; +- snps,dis_enblslpm_quirk; +- phys = <&usb_2_hsphy>, <&usb_2_ssphy>; +- phy-names = "usb2-phy", "usb3-phy"; +- }; +- }; +- +- camnoc_virt: interconnect@ac00000 { +- compatible = "qcom,sm8150-camnoc-virt"; +- reg = <0 0x0ac00000 0 0x1000>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- aoss_qmp: power-controller@c300000 { +- compatible = "qcom,sm8150-aoss-qmp"; +- reg = <0x0 0x0c300000 0x0 0x100000>; +- interrupts = ; +- mboxes = <&apss_shared 0>; +- +- #clock-cells = <0>; +- #power-domain-cells = <1>; +- }; +- +- tsens0: thermal-sensor@c263000 { +- compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; +- reg = <0 0x0c263000 0 0x1ff>, /* TM */ +- <0 0x0c222000 0 0x1ff>; /* SROT */ +- #qcom,sensors = <16>; +- interrupts = , +- ; +- interrupt-names = "uplow", "critical"; +- #thermal-sensor-cells = <1>; +- }; +- +- tsens1: thermal-sensor@c265000 { +- compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; +- reg = <0 0x0c265000 0 0x1ff>, /* TM */ +- <0 0x0c223000 0 0x1ff>; /* SROT */ +- #qcom,sensors = <8>; +- interrupts = , +- ; +- interrupt-names = "uplow", "critical"; +- #thermal-sensor-cells = <1>; +- }; +- +- spmi_bus: spmi@c440000 { +- compatible = "qcom,spmi-pmic-arb"; +- reg = <0x0 0x0c440000 0x0 0x0001100>, +- <0x0 0x0c600000 0x0 0x2000000>, +- <0x0 0x0e600000 0x0 0x0100000>, +- <0x0 0x0e700000 0x0 0x00a0000>, +- <0x0 0x0c40a000 0x0 0x0026000>; +- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; +- interrupt-names = "periph_irq"; +- interrupts = ; +- qcom,ee = <0>; +- qcom,channel = <0>; +- #address-cells = <2>; +- #size-cells = <0>; +- interrupt-controller; +- #interrupt-cells = <4>; +- cell-index = <0>; +- }; +- +- apps_smmu: iommu@15000000 { +- compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; +- reg = <0 0x15000000 0 0x100000>; +- #iommu-cells = <2>; +- #global-interrupts = <1>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- }; +- +- remoteproc_adsp: remoteproc@17300000 { +- compatible = "qcom,sm8150-adsp-pas"; +- reg = <0x0 0x17300000 0x0 0x4040>; +- +- interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, +- <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack"; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "xo"; +- +- power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, +- <&rpmhpd 7>; +- power-domain-names = "load_state", "cx"; +- +- memory-region = <&adsp_mem>; +- +- qcom,smem-states = <&adsp_smp2p_out 0>; +- qcom,smem-state-names = "stop"; +- +- status = "disabled"; +- +- glink-edge { +- interrupts = ; +- label = "lpass"; +- qcom,remote-pid = <2>; +- mboxes = <&apss_shared 8>; +- }; +- }; +- +- intc: interrupt-controller@17a00000 { +- compatible = "arm,gic-v3"; +- interrupt-controller; +- #interrupt-cells = <3>; +- reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ +- <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ +- interrupts = ; +- }; +- +- apss_shared: mailbox@17c00000 { +- compatible = "qcom,sm8150-apss-shared"; +- reg = <0x0 0x17c00000 0x0 0x1000>; +- #mbox-cells = <1>; +- }; +- +- watchdog@17c10000 { +- compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; +- reg = <0 0x17c10000 0 0x1000>; +- clocks = <&sleep_clk>; +- interrupts = ; +- }; +- +- timer@17c20000 { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- compatible = "arm,armv7-timer-mem"; +- reg = <0x0 0x17c20000 0x0 0x1000>; +- clock-frequency = <19200000>; +- +- frame@17c21000{ +- frame-number = <0>; +- interrupts = , +- ; +- reg = <0x0 0x17c21000 0x0 0x1000>, +- <0x0 0x17c22000 0x0 0x1000>; +- }; +- +- frame@17c23000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0x0 0x17c23000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c25000 { +- frame-number = <2>; +- interrupts = ; +- reg = <0x0 0x17c25000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c27000 { +- frame-number = <3>; +- interrupts = ; +- reg = <0x0 0x17c26000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c29000 { +- frame-number = <4>; +- interrupts = ; +- reg = <0x0 0x17c29000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c2b000 { +- frame-number = <5>; +- interrupts = ; +- reg = <0x0 0x17c2b000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c2d000 { +- frame-number = <6>; +- interrupts = ; +- reg = <0x0 0x17c2d000 0x0 0x1000>; +- status = "disabled"; +- }; +- }; +- +- apps_rsc: rsc@18200000 { +- label = "apps_rsc"; +- compatible = "qcom,rpmh-rsc"; +- reg = <0x0 0x18200000 0x0 0x10000>, +- <0x0 0x18210000 0x0 0x10000>, +- <0x0 0x18220000 0x0 0x10000>; +- reg-names = "drv-0", "drv-1", "drv-2"; +- interrupts = , +- , +- ; +- qcom,tcs-offset = <0xd00>; +- qcom,drv-id = <2>; +- qcom,tcs-config = , +- , +- , +- ; +- +- rpmhcc: clock-controller { +- compatible = "qcom,sm8150-rpmh-clk"; +- #clock-cells = <1>; +- clock-names = "xo"; +- clocks = <&xo_board>; +- }; +- +- rpmhpd: power-controller { +- compatible = "qcom,sm8150-rpmhpd"; +- #power-domain-cells = <1>; +- operating-points-v2 = <&rpmhpd_opp_table>; +- +- rpmhpd_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- rpmhpd_opp_ret: opp1 { +- opp-level = ; +- }; +- +- rpmhpd_opp_min_svs: opp2 { +- opp-level = ; +- }; +- +- rpmhpd_opp_low_svs: opp3 { +- opp-level = ; +- }; +- +- rpmhpd_opp_svs: opp4 { +- opp-level = ; +- }; +- +- rpmhpd_opp_svs_l1: opp5 { +- opp-level = ; +- }; +- +- rpmhpd_opp_svs_l2: opp6 { +- opp-level = <224>; +- }; +- +- rpmhpd_opp_nom: opp7 { +- opp-level = ; +- }; +- +- rpmhpd_opp_nom_l1: opp8 { +- opp-level = ; +- }; +- +- rpmhpd_opp_nom_l2: opp9 { +- opp-level = ; +- }; +- +- rpmhpd_opp_turbo: opp10 { +- opp-level = ; +- }; +- +- rpmhpd_opp_turbo_l1: opp11 { +- opp-level = ; +- }; +- }; +- }; +- +- apps_bcm_voter: bcm_voter { +- compatible = "qcom,bcm-voter"; +- }; +- }; +- +- osm_l3: interconnect@18321000 { +- compatible = "qcom,sm8150-osm-l3"; +- reg = <0 0x18321000 0 0x1400>; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; +- clock-names = "xo", "alternate"; +- +- #interconnect-cells = <1>; +- }; +- +- cpufreq_hw: cpufreq@18323000 { +- compatible = "qcom,cpufreq-hw"; +- reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, +- <0 0x18327800 0 0x1400>; +- reg-names = "freq-domain0", "freq-domain1", +- "freq-domain2"; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; +- clock-names = "xo", "alternate"; +- +- #freq-domain-cells = <1>; +- }; +- +- wifi: wifi@18800000 { +- compatible = "qcom,wcn3990-wifi"; +- reg = <0 0x18800000 0 0x800000>; +- reg-names = "membase"; +- memory-region = <&wlan_mem>; +- clock-names = "cxo_ref_clk_pin", "qdss"; +- clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- iommus = <&apps_smmu 0x0640 0x1>; +- status = "disabled"; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- thermal-zones { +- cpu0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 1>; +- +- trips { +- cpu0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu0_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu0_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu0_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu0_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 2>; +- +- trips { +- cpu1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu1_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu1_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu1_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu1_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 3>; +- +- trips { +- cpu2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu2_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu2_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu2_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu2_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 4>; +- +- trips { +- cpu3_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu3_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu3_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu3_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu3_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu4-top-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 7>; +- +- trips { +- cpu4_top_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu4_top_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu4_top_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu4_top_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu4_top_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu5-top-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 8>; +- +- trips { +- cpu5_top_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu5_top_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu5_top_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu5_top_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu5_top_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu6-top-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 9>; +- +- trips { +- cpu6_top_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu6_top_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu6_top_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu6_top_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu6_top_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu7-top-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 10>; +- +- trips { +- cpu7_top_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu7_top_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu7_top_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu7_top_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu7_top_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu4-bottom-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 11>; +- +- trips { +- cpu4_bottom_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu4_bottom_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu4_bottom_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu4_bottom_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu4_bottom_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu5-bottom-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 12>; +- +- trips { +- cpu5_bottom_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu5_bottom_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu5_bottom_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu5_bottom_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu5_bottom_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu6-bottom-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 13>; +- +- trips { +- cpu6_bottom_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu6_bottom_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu6_bottom_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu6_bottom_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu6_bottom_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu7-bottom-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 14>; +- +- trips { +- cpu7_bottom_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu7_bottom_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu7_bottom_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu7_bottom_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu7_bottom_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- aoss0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 0>; +- +- trips { +- aoss0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- cluster0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 5>; +- +- trips { +- cluster0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- cluster0_crit: cluster0_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cluster1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 6>; +- +- trips { +- cluster1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- cluster1_crit: cluster1_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- gpu-thermal-top { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 15>; +- +- trips { +- gpu1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- aoss1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 0>; +- +- trips { +- aoss1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- wlan-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 1>; +- +- trips { +- wlan_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- video-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 2>; +- +- trips { +- video_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- mem-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 3>; +- +- trips { +- mem_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- q6-hvx-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 4>; +- +- trips { +- q6_hvx_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- camera-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 5>; +- +- trips { +- camera_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- compute-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 6>; +- +- trips { +- compute_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- modem-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 7>; +- +- trips { +- modem_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- npu-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 8>; +- +- trips { +- npu_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- modem-vec-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 9>; +- +- trips { +- modem_vec_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- modem-scl-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 10>; +- +- trips { +- modem_scl_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- gpu-thermal-bottom { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 11>; +- +- trips { +- gpu2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sm8250-hdk.dts b/scripts/dtc/include-prefixes/arm64/qcom/sm8250-hdk.dts +deleted file mode 100644 +index 47742816ac2f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sm8250-hdk.dts ++++ /dev/null +@@ -1,461 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include +-#include "sm8250.dtsi" +-#include "pm8150.dtsi" +-#include "pm8150b.dtsi" +-#include "pm8150l.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. SM8250 HDK"; +- compatible = "qcom,sm8250-hdk", "qcom,sm8250"; +- +- aliases { +- serial0 = &uart12; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- }; +- +- vreg_s4a_1p8: pm8150-s4 { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_s4a_1p8"; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-always-on; +- regulator-boot-on; +- +- vin-supply = <&vph_pwr>; +- }; +- +- vreg_s6c_0p88: smpc6-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_s6c_0p88"; +- +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-always-on; +- vin-supply = <&vph_pwr>; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- vol-up { +- label = "Volume Up"; +- linux,code = ; +- gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&apps_rsc { +- pm8150-rpmh-regulators { +- compatible = "qcom,pm8150-rpmh-regulators"; +- qcom,pmic-id = "a"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- vdd-s9-supply = <&vph_pwr>; +- vdd-s10-supply = <&vph_pwr>; +- vdd-l1-l8-l11-supply = <&vreg_s6c_0p88>; +- vdd-l2-l10-supply = <&vreg_bob>; +- vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p95>; +- vdd-l6-l9-supply = <&vreg_s8c_1p3>; +- vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; +- vdd-l13-l16-l17-supply = <&vreg_bob>; +- +- vreg_s5a_1p9: smps5 { +- regulator-name = "vreg_s5a_1p9"; +- regulator-min-microvolt = <1824000>; +- regulator-max-microvolt = <2000000>; +- regulator-initial-mode = ; +- }; +- +- vreg_s6a_0p95: smps6 { +- regulator-name = "vreg_s6a_0p95"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1128000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l2a_3p1: ldo2 { +- regulator-name = "vreg_l2a_3p1"; +- regulator-min-microvolt = <3072000>; +- regulator-max-microvolt = <3072000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3a_0p9: ldo3 { +- regulator-name = "vreg_l3a_0p9"; +- regulator-min-microvolt = <928000>; +- regulator-max-microvolt = <932000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5a_0p88: ldo5 { +- regulator-name = "vreg_l5a_0p88"; +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6a_1p2: ldo6 { +- regulator-name = "vreg_l6a_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7a_1p7: ldo7 { +- regulator-name = "vreg_l7a_1p7"; +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l9a_1p2: ldo9 { +- regulator-name = "vreg_l9a_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10a_1p8: ldo10 { +- regulator-name = "vreg_l10a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l12a_1p8: ldo12 { +- regulator-name = "vreg_l12a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l13a_ts_3p0: ldo13 { +- regulator-name = "vreg_l13a_ts_3p0"; +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l14a_1p8: ldo14 { +- regulator-name = "vreg_l14a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1880000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l15a_1p8: ldo15 { +- regulator-name = "vreg_l15a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l16a_3p3: ldo16 { +- regulator-name = "vreg_l16a_3p3"; +- regulator-min-microvolt = <3024000>; +- regulator-max-microvolt = <3304000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l17a_2p96: ldo17 { +- regulator-name = "vreg_l17a_2p96"; +- regulator-min-microvolt = <2496000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l18a_0p92: ldo18 { +- regulator-name = "vreg_l18a_0p92"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <920000>; +- regulator-initial-mode = ; +- }; +- }; +- +- pm8150l-rpmh-regulators { +- compatible = "qcom,pm8150l-rpmh-regulators"; +- qcom,pmic-id = "c"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- vdd-l1-l8-supply = <&vreg_s4a_1p8>; +- vdd-l2-l3-supply = <&vreg_s8c_1p3>; +- vdd-l4-l5-l6-supply = <&vreg_bob>; +- vdd-l7-l11-supply = <&vreg_bob>; +- vdd-l9-l10-supply = <&vreg_bob>; +- vdd-bob-supply = <&vph_pwr>; +- +- vreg_bob: bob { +- regulator-name = "vreg_bob"; +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_s8c_1p3: smps8 { +- regulator-name = "vreg_s8c_1p3"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1400000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l1c_1p8: ldo1 { +- regulator-name = "vreg_l1c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l2c_1p2: ldo2 { +- regulator-name = "vreg_l2c_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1304000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3c_0p8: ldo3 { +- regulator-name = "vreg_l3c_0p8"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l4c_1p8: ldo4 { +- regulator-name = "vreg_l4c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5c_1p8: ldo5 { +- regulator-name = "vreg_l5c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6c_2p96: ldo6 { +- regulator-name = "vreg_l6c_2p96"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7c_cam_vcm0_2p85: ldo7 { +- regulator-name = "vreg_l7c_cam_vcm0_2p85"; +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <3104000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l8c_1p8: ldo8 { +- regulator-name = "vreg_l8c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l9c_2p96: ldo9 { +- regulator-name = "vreg_l9c_2p96"; +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10c_3p0: ldo10 { +- regulator-name = "vreg_l10c_3p0"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l11c_3p3: ldo11 { +- regulator-name = "vreg_l11c_3p3"; +- regulator-min-microvolt = <3104000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- }; +- +- pm8009-rpmh-regulators { +- compatible = "qcom,pm8009-rpmh-regulators"; +- qcom,pmic-id = "f"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vreg_bob>; +- vdd-l2-supply = <&vreg_s8c_1p3>; +- vdd-l5-l6-supply = <&vreg_bob>; +- vdd-l7-supply = <&vreg_s4a_1p8>; +- +- vreg_l1f_cam_dvdd1_1p1: ldo1 { +- regulator-name = "vreg_l1f_cam_dvdd1_1p1"; +- regulator-min-microvolt = <1104000>; +- regulator-max-microvolt = <1104000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l2f_cam_dvdd0_1p2: ldo2 { +- regulator-name = "vreg_l2f_cam_dvdd0_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3f_cam_dvdd2_1p05: ldo3 { +- regulator-name = "vreg_l3f_cam_dvdd2_1p05"; +- regulator-min-microvolt = <1056000>; +- regulator-max-microvolt = <1056000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5f_cam_avdd0_2p85: ldo5 { +- regulator-name = "vreg_l5f_cam_avdd0_2p85"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <3000000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6f_cam_avdd1_2p8: ldo6 { +- regulator-name = "vreg_l6f_cam_avdd1_2p8"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <3000000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7f_1p8: ldo7 { +- regulator-name = "vreg_l7f_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- }; +-}; +- +-&gmu { +- status = "okay"; +-}; +- +-&gpu { +- status = "okay"; +-}; +- +-&pon_pwrkey { +- status = "okay"; +-}; +- +-&pon_resin { +- status = "okay"; +- +- linux,code = ; +-}; +- +-&qupv3_id_1 { +- status = "okay"; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <28 4>, <40 4>; +-}; +- +-&uart12 { +- status = "okay"; +-}; +- +-&ufs_mem_hc { +- status = "okay"; +- +- vcc-supply = <&vreg_l17a_2p96>; +- vcc-max-microamp = <800000>; +- vccq-supply = <&vreg_l6a_1p2>; +- vccq-max-microamp = <800000>; +- vccq2-supply = <&vreg_s4a_1p8>; +- vccq2-max-microamp = <800000>; +-}; +- +-&ufs_mem_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l5a_0p88>; +- vdda-max-microamp = <89900>; +- vdda-pll-supply = <&vreg_l9a_1p2>; +- vdda-pll-max-microamp = <18800>; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- vdda-pll-supply = <&vreg_l5a_0p88>; +- vdda33-supply = <&vreg_l2a_3p1>; +- vdda18-supply = <&vreg_l12a_1p8>; +-}; +- +-&usb_2_hsphy { +- status = "okay"; +- vdda-pll-supply = <&vreg_l5a_0p88>; +- vdda33-supply = <&vreg_l2a_3p1>; +- vdda18-supply = <&vreg_l12a_1p8>; +-}; +- +-&usb_1_qmpphy { +- status = "okay"; +- vdda-phy-supply = <&vreg_l9a_1p2>; +- vdda-pll-supply = <&vreg_l18a_0p92>; +-}; +- +-&usb_2_qmpphy { +- status = "okay"; +- vdda-phy-supply = <&vreg_l9a_1p2>; +- vdda-pll-supply = <&vreg_l18a_0p92>; +-}; +- +-&usb_1 { +- status = "okay"; +-}; +- +-&usb_2 { +- status = "okay"; +-}; +- +-&usb_1_dwc3 { +- dr_mode = "peripheral"; +-}; +- +-&usb_2_dwc3 { +- dr_mode = "host"; +-}; +- +-&venus { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sm8250-mtp.dts b/scripts/dtc/include-prefixes/arm64/qcom/sm8250-mtp.dts +deleted file mode 100644 +index 062b944be91d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sm8250-mtp.dts ++++ /dev/null +@@ -1,703 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include +-#include "sm8250.dtsi" +-#include "pm8150.dtsi" +-#include "pm8150b.dtsi" +-#include "pm8150l.dtsi" +-#include "pm8009.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. SM8250 MTP"; +- compatible = "qcom,sm8250-mtp", "qcom,sm8250"; +- +- aliases { +- serial0 = &uart12; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- thermal-zones { +- camera-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&pm8150l_adc_tm 0>; +- +- trips { +- active-config0 { +- temperature = <125000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- }; +- }; +- +- conn-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&pm8150b_adc_tm 0>; +- +- trips { +- active-config0 { +- temperature = <125000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- }; +- }; +- +- mmw-pa1-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&pm8150_adc_tm 2>; +- +- trips { +- active-config0 { +- temperature = <125000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- }; +- }; +- +- mmw-pa2-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&pm8150l_adc_tm 2>; +- +- trips { +- active-config0 { +- temperature = <125000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- }; +- }; +- +- skin-msm-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&pm8150l_adc_tm 1>; +- +- trips { +- active-config0 { +- temperature = <125000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- }; +- }; +- +- skin-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&pm8150_adc_tm 1>; +- +- trips { +- active-config0 { +- temperature = <125000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- }; +- }; +- +- xo-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; +- thermal-sensors = <&pm8150_adc_tm 0>; +- +- trips { +- active-config0 { +- temperature = <125000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- }; +- }; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- }; +- +- vreg_s4a_1p8: pm8150-s4 { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_s4a_1p8"; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-always-on; +- regulator-boot-on; +- +- vin-supply = <&vph_pwr>; +- }; +- +- vreg_s6c_0p88: smpc6-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_s6c_0p88"; +- +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-always-on; +- vin-supply = <&vph_pwr>; +- }; +-}; +- +-&adsp { +- status = "okay"; +- firmware-name = "qcom/sm8250/adsp.mbn"; +-}; +- +-&apps_rsc { +- pm8150-rpmh-regulators { +- compatible = "qcom,pm8150-rpmh-regulators"; +- qcom,pmic-id = "a"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- vdd-s9-supply = <&vph_pwr>; +- vdd-s10-supply = <&vph_pwr>; +- vdd-l1-l8-l11-supply = <&vreg_s6c_0p88>; +- vdd-l2-l10-supply = <&vreg_bob>; +- vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p95>; +- vdd-l6-l9-supply = <&vreg_s8c_1p3>; +- vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; +- vdd-l13-l16-l17-supply = <&vreg_bob>; +- +- vreg_s5a_1p9: smps5 { +- regulator-name = "vreg_s5a_1p9"; +- regulator-min-microvolt = <1904000>; +- regulator-max-microvolt = <2000000>; +- regulator-initial-mode = ; +- }; +- +- vreg_s6a_0p95: smps6 { +- regulator-name = "vreg_s6a_0p95"; +- regulator-min-microvolt = <920000>; +- regulator-max-microvolt = <1128000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l2a_3p1: ldo2 { +- regulator-name = "vreg_l2a_3p1"; +- regulator-min-microvolt = <3072000>; +- regulator-max-microvolt = <3072000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3a_0p9: ldo3 { +- regulator-name = "vreg_l3a_0p9"; +- regulator-min-microvolt = <928000>; +- regulator-max-microvolt = <932000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5a_0p875: ldo5 { +- regulator-name = "vreg_l5a_0p875"; +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6a_1p2: ldo6 { +- regulator-name = "vreg_l6a_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7a_1p7: ldo7 { +- regulator-name = "vreg_l7a_1p7"; +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l9a_1p2: ldo9 { +- regulator-name = "vreg_l9a_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10a_1p8: ldo10 { +- regulator-name = "vreg_l10a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l12a_1p8: ldo12 { +- regulator-name = "vreg_l12a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l13a_ts_3p0: ldo13 { +- regulator-name = "vreg_l13a_ts_3p0"; +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l14a_1p8: ldo14 { +- regulator-name = "vreg_l14a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1880000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l15a_11ad_io_1p8: ldo15 { +- regulator-name = "vreg_l15a_11ad_io_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l16a_2p7: ldo16 { +- regulator-name = "vreg_l16a_2p7"; +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l17a_3p0: ldo17 { +- regulator-name = "vreg_l17a_3p0"; +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l18a_0p9: ldo18 { +- regulator-name = "vreg_l18a_0p9"; +- regulator-min-microvolt = <912000>; +- regulator-max-microvolt = <912000>; +- regulator-initial-mode = ; +- }; +- }; +- +- pm8150l-rpmh-regulators { +- compatible = "qcom,pm8150l-rpmh-regulators"; +- qcom,pmic-id = "c"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- vdd-l1-l8-supply = <&vreg_s4a_1p8>; +- vdd-l2-l3-supply = <&vreg_s8c_1p3>; +- vdd-l4-l5-l6-supply = <&vreg_bob>; +- vdd-l7-l11-supply = <&vreg_bob>; +- vdd-l9-l10-supply = <&vreg_bob>; +- vdd-bob-supply = <&vph_pwr>; +- +- vreg_bob: bob { +- regulator-name = "vreg_bob"; +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <4000000>; +- regulator-initial-mode = ; +- }; +- +- vreg_s8c_1p3: smps8 { +- regulator-name = "vreg_s8c_1p3"; +- regulator-min-microvolt = <1352000>; +- regulator-max-microvolt = <1352000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l1c_1p8: ldo1 { +- regulator-name = "vreg_l1c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l2c_1p2: ldo2 { +- regulator-name = "vreg_l2c_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3c_0p92: ldo3 { +- regulator-name = "vreg_l3c_0p92"; +- regulator-min-microvolt = <920000>; +- regulator-max-microvolt = <920000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l4c_1p7: ldo4 { +- regulator-name = "vreg_l4c_1p7"; +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5c_1p8: ldo5 { +- regulator-name = "vreg_l5c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2928000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6c_2p9: ldo6 { +- regulator-name = "vreg_l6c_2p9"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7c_cam_vcm0_2p85: ldo7 { +- regulator-name = "vreg_l7c_cam_vcm0_2p85"; +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <3104000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l8c_1p8: ldo8 { +- regulator-name = "vreg_l8c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l9c_2p9: ldo9 { +- regulator-name = "vreg_l9c_2p9"; +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10c_3p0: ldo10 { +- regulator-name = "vreg_l10c_3p0"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l11c_3p3: ldo11 { +- regulator-name = "vreg_l11c_3p3"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3312000>; +- regulator-initial-mode = ; +- }; +- }; +- +- pm8009-rpmh-regulators { +- compatible = "qcom,pm8009-rpmh-regulators"; +- qcom,pmic-id = "f"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vreg_bob>; +- vdd-l2-supply = <&vreg_s8c_1p3>; +- vdd-l5-l6-supply = <&vreg_bob>; +- vdd-l7-supply = <&vreg_s4a_1p8>; +- +- vreg_l1f_cam_dvdd1_1p1: ldo1 { +- regulator-name = "vreg_l1f_cam_dvdd1_1p1"; +- regulator-min-microvolt = <1104000>; +- regulator-max-microvolt = <1104000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l2f_cam_dvdd0_1p2: ldo2 { +- regulator-name = "vreg_l2f_cam_dvdd0_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3f_cam_dvdd2_1p05: ldo3 { +- regulator-name = "vreg_l3f_cam_dvdd2_1p05"; +- regulator-min-microvolt = <1056000>; +- regulator-max-microvolt = <1056000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5f_cam_avdd0_2p85: ldo5 { +- regulator-name = "vreg_l5f_cam_avdd0_2p85"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6f_cam_avdd1_2p85: ldo6 { +- regulator-name = "vreg_l6f_cam_avdd1_2p85"; +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <2856000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7f_1p8: ldo7 { +- regulator-name = "vreg_l7f_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- }; +-}; +- +-&cdsp { +- status = "okay"; +- firmware-name = "qcom/sm8250/cdsp.mbn"; +-}; +- +-&gmu { +- status = "okay"; +-}; +- +-&gpu { +- status = "okay"; +- +- zap-shader { +- memory-region = <&gpu_mem>; +- firmware-name = "qcom/sm8250/a650_zap.mbn"; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <1000000>; +- +- /* NQ NFC chip @28 */ +-}; +- +-&i2c13 { +- status = "okay"; +- +- /* st,stmfts @ 49 */ +-}; +- +-&i2c15 { +- status = "okay"; +- +- /* smb1390 @ 10 */ +- /* rtc6226 @ 64 */ +-}; +- +-&pm8150_adc { +- xo-therm@4c { +- reg = ; +- qcom,ratiometric; +- qcom,hw-settle-time = <200>; +- }; +- +- skin-therm@4d { +- reg = ; +- qcom,ratiometric; +- qcom,hw-settle-time = <200>; +- }; +- +- pa-therm1@4e { +- reg = ; +- qcom,ratiometric; +- qcom,hw-settle-time = <200>; +- }; +-}; +- +-&pm8150_adc_tm { +- status = "okay"; +- +- xo-therm@0 { +- reg = <0>; +- io-channels = <&pm8150_adc ADC5_XO_THERM_100K_PU>; +- qcom,ratiometric; +- qcom,hw-settle-time-us = <200>; +- }; +- +- skin-therm@1 { +- reg = <1>; +- io-channels = <&pm8150_adc ADC5_AMUX_THM1_100K_PU>; +- qcom,ratiometric; +- qcom,hw-settle-time-us = <200>; +- }; +- +- pa-therm1@2 { +- reg = <2>; +- io-channels = <&pm8150_adc ADC5_AMUX_THM2_100K_PU>; +- qcom,ratiometric; +- qcom,hw-settle-time-us = <200>; +- }; +-}; +- +-&pm8150b_adc { +- conn-therm@4f { +- reg = ; +- qcom,ratiometric; +- qcom,hw-settle-time = <200>; +- }; +-}; +- +-&pm8150b_adc_tm { +- status = "okay"; +- +- conn-therm@0 { +- reg = <0>; +- io-channels = <&pm8150b_adc ADC5_AMUX_THM3_100K_PU>; +- qcom,ratiometric; +- qcom,hw-settle-time-us = <200>; +- }; +-}; +- +-&pm8150l_adc_tm { +- status = "okay"; +- +- camera-flash-therm@0 { +- reg = <0>; +- io-channels = <&pm8150l_adc ADC5_AMUX_THM1_100K_PU>; +- qcom,ratiometric; +- qcom,hw-settle-time-us = <200>; +- }; +- +- skin-msm-therm@1 { +- reg = <1>; +- io-channels = <&pm8150l_adc ADC5_AMUX_THM2_100K_PU>; +- qcom,ratiometric; +- qcom,hw-settle-time-us = <200>; +- }; +- +- pa-therm2@2 { +- reg = <2>; +- io-channels = <&pm8150l_adc ADC5_AMUX_THM3_100K_PU>; +- qcom,ratiometric; +- qcom,hw-settle-time-us = <200>; +- }; +-}; +- +-&pm8150l_adc { +- camera-flash-therm@4d { +- reg = ; +- qcom,ratiometric; +- qcom,hw-settle-time = <200>; +- }; +- +- skin-msm-therm@4e { +- reg = ; +- qcom,ratiometric; +- qcom,hw-settle-time = <200>; +- }; +- +- pa-therm2@4f { +- reg = ; +- qcom,ratiometric; +- qcom,hw-settle-time = <200>; +- }; +-}; +- +-&qupv3_id_0 { +- status = "okay"; +-}; +- +-&qupv3_id_1 { +- status = "okay"; +-}; +- +-&qupv3_id_2 { +- status = "okay"; +-}; +- +-&slpi { +- status = "okay"; +- firmware-name = "qcom/sm8250/slpi.mbn"; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <28 4>, <40 4>; +-}; +- +-&uart12 { +- status = "okay"; +-}; +- +-&ufs_mem_hc { +- status = "okay"; +- +- vcc-supply = <&vreg_l17a_3p0>; +- vcc-max-microamp = <750000>; +- vccq-supply = <&vreg_l6a_1p2>; +- vccq-max-microamp = <700000>; +- vccq2-supply = <&vreg_s4a_1p8>; +- vccq2-max-microamp = <750000>; +-}; +- +-&ufs_mem_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l5a_0p875>; +- vdda-max-microamp = <90200>; +- vdda-pll-supply = <&vreg_l9a_1p2>; +- vdda-pll-max-microamp = <19000>; +-}; +- +-&usb_1 { +- status = "okay"; +-}; +- +-&usb_1_dwc3 { +- dr_mode = "host"; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- +- vdda-pll-supply = <&vreg_l5a_0p875>; +- vdda18-supply = <&vreg_l12a_1p8>; +- vdda33-supply = <&vreg_l2a_3p1>; +-}; +- +-&usb_1_qmpphy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l9a_1p2>; +- vdda-pll-supply = <&vreg_l18a_0p9>; +-}; +- +-&usb_2 { +- status = "okay"; +-}; +- +-&usb_2_dwc3 { +- dr_mode = "host"; +-}; +- +-&usb_2_hsphy { +- status = "okay"; +- +- vdda-pll-supply = <&vreg_l5a_0p875>; +- vdda18-supply = <&vreg_l12a_1p8>; +- vdda33-supply = <&vreg_l2a_3p1>; +-}; +- +-&usb_2_qmpphy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l9a_1p2>; +- vdda-pll-supply = <&vreg_l18a_0p9>; +-}; +- +-&venus { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sm8250-sony-xperia-edo-pdx203.dts b/scripts/dtc/include-prefixes/arm64/qcom/sm8250-sony-xperia-edo-pdx203.dts +deleted file mode 100644 +index 79afeb07f4a2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sm8250-sony-xperia-edo-pdx203.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Konrad Dybcio +- */ +- +-/dts-v1/; +- +-#include "sm8250-sony-xperia-edo.dtsi" +- +-/ { +- model = "Sony Xperia 1 II"; +- compatible = "sony,pdx203-generic", "qcom,sm8250"; +-}; +- +-/delete-node/ &vreg_l7f_1p8; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sm8250-sony-xperia-edo-pdx206.dts b/scripts/dtc/include-prefixes/arm64/qcom/sm8250-sony-xperia-edo-pdx206.dts +deleted file mode 100644 +index 16c96e838534..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sm8250-sony-xperia-edo-pdx206.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Konrad Dybcio +- */ +- +-/dts-v1/; +- +-#include "sm8250-sony-xperia-edo.dtsi" +- +-/ { +- model = "Sony Xperia 5 II"; +- compatible = "sony,pdx206-generic", "qcom,sm8250"; +-}; +- +-&framebuffer { +- width = <1080>; +- height = <2520>; +- stride = <(1080 * 4)>; +-}; +- +-&gpio_keys { +- g-assist-key { +- label = "Google Assistant Key"; +- linux,code = ; +- gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; +- debounce-interval = <15>; +- linux,can-disable; +- gpio-key,wakeup; +- }; +-}; +- +-&vreg_l2f_1p3 { +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sm8250-sony-xperia-edo.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sm8250-sony-xperia-edo.dtsi +deleted file mode 100644 +index d63f7a9bc4e9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sm8250-sony-xperia-edo.dtsi ++++ /dev/null +@@ -1,636 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2021, Konrad Dybcio +- */ +- +-#include +-#include "sm8250.dtsi" +-#include "pm8150.dtsi" +-#include "pm8150b.dtsi" +-#include "pm8150l.dtsi" +-#include "pm8009.dtsi" +- +-/delete-node/ &adsp_mem; +-/delete-node/ &spss_mem; +-/delete-node/ &cdsp_secure_heap; +- +-/ { +- qcom,msm-id = <356 0x20001>; /* SM8250 v2.1 */ +- qcom,board-id = <0x10008 0>; +- +- chosen { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- framebuffer: framebuffer@9c000000 { +- compatible = "simple-framebuffer"; +- reg = <0 0x9c000000 0 0x2300000>; +- width = <1644>; +- height = <3840>; +- stride = <(1644 * 4)>; +- format = "a8r8g8b8"; +- /* +- * That's a lot of clocks, but it's necessary due +- * to unused clk cleanup & no panel driver yet.. +- */ +- clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, +- <&gcc GCC_DISP_HF_AXI_CLK>, +- <&gcc GCC_DISP_SF_AXI_CLK>, +- <&dispcc DISP_CC_MDSS_VSYNC_CLK>, +- <&dispcc DISP_CC_MDSS_MDP_CLK>, +- <&dispcc DISP_CC_MDSS_BYTE0_CLK>, +- <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, +- <&dispcc DISP_CC_MDSS_PCLK0_CLK>, +- <&dispcc DISP_CC_MDSS_ESC0_CLK>; +- power-domains = <&dispcc MDSS_GDSC>; +- }; +- }; +- +- gpio_keys: gpio-keys { +- compatible = "gpio-keys"; +- +- /* +- * Camera focus (light press) and camera snapshot (full press) +- * seem not to work properly.. Adding the former one stalls the CPU +- * and the latter kills the volume down key for whatever reason. In any +- * case, they are both on &pm8150b_gpios: camera focus(2), camera snapshot(1). +- */ +- +- vol-down { +- label = "Volume Down"; +- linux,code = ; +- gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>; +- debounce-interval = <15>; +- linux,can-disable; +- gpio-key,wakeup; +- }; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- }; +- +- /* S6c is really ebi.lvl but it's there for supply map completeness sake. */ +- vreg_s6c_0p88: smpc6-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vreg_s6c_0p88"; +- +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-always-on; +- vin-supply = <&vph_pwr>; +- }; +- +- reserved-memory { +- adsp_mem: memory@8a100000 { +- reg = <0x0 0x8a100000 0x0 0x2500000>; +- no-map; +- }; +- +- spss_mem: memory@8c600000 { +- reg = <0x0 0x8c600000 0x0 0x100000>; +- no-map; +- }; +- +- cdsp_secure_heap: memory@8c700000 { +- reg = <0x0 0x8c700000 0x0 0x4600000>; +- no-map; +- }; +- +- cont_splash_mem: memory@9c000000 { +- reg = <0x0 0x9c000000 0x0 0x2300000>; +- no-map; +- }; +- +- ramoops@ffc00000 { +- compatible = "ramoops"; +- reg = <0x0 0xffc00000 0x0 0x100000>; +- record-size = <0x1000>; +- console-size = <0x40000>; +- msg-size = <0x20000 0x20000>; +- ecc-size = <16>; +- no-map; +- }; +- }; +-}; +- +-&adsp { +- status = "okay"; +-}; +- +-&apps_rsc { +- pm8150-rpmh-regulators { +- compatible = "qcom,pm8150-rpmh-regulators"; +- qcom,pmic-id = "a"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- vdd-s9-supply = <&vph_pwr>; +- vdd-s10-supply = <&vph_pwr>; +- vdd-l1-l8-l11-supply = <&vreg_s6c_0p88>; +- vdd-l2-l10-supply = <&vreg_bob>; +- vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p6>; +- vdd-l6-l9-supply = <&vreg_s8c_1p2>; +- vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; +- vdd-l13-l16-l17-supply = <&vreg_bob>; +- +- /* (S1+S2+S3) - cx.lvl (ARC) */ +- +- vreg_s4a_1p8: smps4 { +- regulator-name = "vreg_s4a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1920000>; +- regulator-initial-mode = ; +- }; +- +- vreg_s5a_1p9: smps5 { +- regulator-name = "vreg_s5a_1p9"; +- regulator-min-microvolt = <1824000>; +- regulator-max-microvolt = <2040000>; +- regulator-initial-mode = ; +- }; +- +- vreg_s6a_0p6: smps6 { +- regulator-name = "vreg_s6a_0p6"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1128000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l2a_3p1: ldo2 { +- regulator-name = "vreg_l2a_3p1"; +- regulator-min-microvolt = <3072000>; +- regulator-max-microvolt = <3072000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3a_0p9: ldo3 { +- regulator-name = "vreg_l3a_0p9"; +- regulator-min-microvolt = <928000>; +- regulator-max-microvolt = <932000>; +- regulator-initial-mode = ; +- }; +- +- /* L4 - lmx.lvl (ARC) */ +- +- vreg_l5a_0p88: ldo5 { +- regulator-name = "vreg_l5a_0p88"; +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <880000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6a_1p2: ldo6 { +- regulator-name = "vreg_l6a_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- /* L7 is unused. */ +- +- vreg_l9a_1p2: ldo9 { +- regulator-name = "vreg_l9a_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- /* L10 is unused, L11 - lcx.lvl (ARC) */ +- +- vreg_l12a_1p8: ldo12 { +- regulator-name = "vreg_l12a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- /* L13 is unused. */ +- +- vreg_l14a_1p8: ldo14 { +- regulator-name = "vreg_l14a_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1880000>; +- regulator-initial-mode = ; +- }; +- +- /* L15 & L16 are unused. */ +- +- vreg_l17a_3p0: ldo17 { +- regulator-name = "vreg_l17a_3p0"; +- regulator-min-microvolt = <2496000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l18a_0p9: ldo18 { +- regulator-name = "vreg_l18a_0p9"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <920000>; +- regulator-initial-mode = ; +- }; +- }; +- +- /* +- * Remaining regulators that are not yet supported: +- * OLEDB: 4925000-8100000 +- * ab: 4600000-6100000 +- * ibb: 800000-5400000 +- */ +- pm8150l-rpmh-regulators { +- compatible = "qcom,pm8150l-rpmh-regulators"; +- qcom,pmic-id = "c"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- vdd-l1-l8-supply = <&vreg_s4a_1p8>; +- vdd-l2-l3-supply = <&vreg_s8c_1p2>; +- vdd-l4-l5-l6-supply = <&vreg_bob>; +- vdd-l7-l11-supply = <&vreg_bob>; +- vdd-l9-l10-supply = <&vreg_bob>; +- vdd-bob-supply = <&vph_pwr>; +- +- vreg_bob: bob { +- regulator-name = "vreg_bob"; +- regulator-min-microvolt = <3350000>; +- regulator-max-microvolt = <3960000>; +- regulator-initial-mode = ; +- }; +- +- /* +- * S1-S6 are ARCs: +- * (S1+S2) - gfx.lvl, +- * S3 - mx.lvl, +- * (S4+S5) - mmcx.lvl, +- * S6 - ebi.lvl +- */ +- +- vreg_s7c_0p35: smps7 { +- regulator-name = "vreg_s7c_0p35"; +- regulator-min-microvolt = <348000>; +- regulator-max-microvolt = <1000000>; +- regulator-initial-mode = ; +- }; +- +- vreg_s8c_1p2: smps8 { +- regulator-name = "vreg_s8c_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1400000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l1c_1p8: ldo1 { +- regulator-name = "vreg_l1c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- /* L2-4 are unused. */ +- +- vreg_l5c_1p8: ldo5 { +- regulator-name = "vreg_l5c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6c_2p9: ldo6 { +- regulator-name = "vreg_l6c_2p9"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- regulator-allow-set-load; +- }; +- +- vreg_l7c_2p85: ldo7 { +- regulator-name = "vreg_l7c_2p85"; +- regulator-min-microvolt = <2856000>; +- regulator-max-microvolt = <3104000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l8c_1p8: ldo8 { +- regulator-name = "vreg_l8c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l9c_2p9: ldo9 { +- regulator-name = "vreg_l9c_2p9"; +- regulator-min-microvolt = <2704000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- regulator-allow-set-load; +- }; +- +- vreg_l10c_3p3: ldo10 { +- regulator-name = "vreg_l10c_3p3"; +- regulator-min-microvolt = <3296000>; +- regulator-max-microvolt = <3296000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l11c_3p0: ldo11 { +- regulator-name = "vreg_l11c_3p0"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-initial-mode = ; +- }; +- }; +- +- pm8009-rpmh-regulators { +- compatible = "qcom,pm8009-rpmh-regulators"; +- qcom,pmic-id = "f"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vreg_bob>; +- vdd-l2-supply = <&vreg_s8c_1p2>; +- vdd-l5-l6-supply = <&vreg_bob>; +- vdd-l7-supply = <&vreg_s4a_1p8>; +- +- vreg_s1f_1p2: smps1 { +- regulator-name = "vreg_s1f_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_s2f_0p5: smps2 { +- regulator-name = "vreg_s2f_0p5"; +- regulator-min-microvolt = <512000>; +- regulator-max-microvolt = <1100000>; +- regulator-initial-mode = ; +- }; +- +- /* L1 is unused. */ +- +- vreg_l2f_1p3: ldo2 { +- regulator-name = "vreg_l2f_1p3"; +- regulator-min-microvolt = <1304000>; +- regulator-max-microvolt = <1304000>; +- regulator-initial-mode = ; +- }; +- +- /* L3 & L4 are unused. */ +- +- vreg_l5f_2p8: ldo5 { +- regulator-name = "vreg_l5f_2p85"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6f_2p8: ldo6 { +- regulator-name = "vreg_l6f_2p8"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7f_1p8: ldo7 { +- regulator-name = "vreg_l7f_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- }; +-}; +- +-&cdsp { +- status = "okay"; +-}; +- +-&gpi_dma0 { +- status = "okay"; +-}; +- +-&gpi_dma1 { +- status = "okay"; +-}; +- +-&gpi_dma2 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- /* NXP PN553 NFC @ 28 */ +-}; +- +-&i2c2 { +- status = "okay"; +- clock-frequency = <1000000>; +- +- /* Dual Cirrus Logic CS35L41 amps @ 40, 41 */ +-}; +- +-&i2c5 { +- status = "okay"; +- clock-frequency = <400000>; +- +- /* Dialog SLG51000 CMIC @ 75 */ +-}; +- +-&i2c9 { +- status = "okay"; +- clock-frequency = <400000>; +- +- /* AMS TCS3490 RGB+IR color sensor @ 72 */ +-}; +- +-&i2c13 { +- status = "okay"; +- clock-frequency = <400000>; +- +- touchscreen@48 { +- compatible = "samsung,s6sy761"; +- reg = <0x48>; +- interrupt-parent = <&tlmm>; +- interrupts = <39 0x2008>; +- /* It's "vddio" downstream but it works anyway! */ +- vdd-supply = <&vreg_l1c_1p8>; +- avdd-supply = <&vreg_l10c_3p3>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&ts_int_default>; +- }; +-}; +- +-&i2c15 { +- status = "okay"; +- clock-frequency = <400000>; +- +- /* Qcom SMB1390 @ 10 */ +- /* Silicon Labs SI4704 FM Radio Receiver @ 11 */ +- /* Qcom SMB1390_slave @ 18 */ +- /* HALO HL6111R Qi charger @ 25 */ +- /* Richwave RTC6226 FM Radio Receiver @ 64 */ +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie0_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l5a_0p88>; +- vdda-pll-supply = <&vreg_l9a_1p2>; +-}; +- +-&pcie2 { +- status = "okay"; +- +- pinctrl-0 = <&pcie2_default_state &mdm2ap_default &ap2mdm_default>; +-}; +- +-&pcie2_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l5a_0p88>; +- vdda-pll-supply = <&vreg_l9a_1p2>; +-}; +- +-&pon_pwrkey { +- status = "okay"; +-}; +- +-&pon_resin { +- status = "okay"; +- +- linux,code = ; +-}; +- +-&qupv3_id_0 { +- status = "okay"; +-}; +- +-&qupv3_id_1 { +- status = "okay"; +-}; +- +-&qupv3_id_2 { +- status = "okay"; +-}; +- +-&sdhc_2 { +- status = "okay"; +- +- cd-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; +- pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>; +- vmmc-supply = <&vreg_l9c_2p9>; +- vqmmc-supply = <&vreg_l6c_2p9>; +- bus-width = <4>; +- no-sdio; +- no-emmc; +-}; +- +-&slpi { +- status = "okay"; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <40 4>, <52 4>; +- +- sdc2_default_state: sdc2-default { +- clk { +- pins = "sdc2_clk"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- cmd { +- pins = "sdc2_cmd"; +- drive-strength = <16>; +- bias-pull-up; +- }; +- +- data { +- pins = "sdc2_data"; +- drive-strength = <16>; +- bias-pull-up; +- }; +- }; +- +- mdm2ap_default: mdm2ap-default { +- pins = "gpio1", "gpio3"; +- function = "gpio"; +- drive-strength = <8>; +- bias-disable; +- }; +- +- ts_int_default: ts-int-default { +- pins = "gpio39"; +- function = "gpio"; +- drive-strength = <2>; +- bias-disabled; +- input-enable; +- }; +- +- ap2mdm_default: ap2mdm-default { +- pins = "gpio56", "gpio57"; +- function = "gpio"; +- drive-strength = <16>; +- bias-disable; +- }; +- +- sdc2_card_det_n: sd-card-det-n { +- pins = "gpio77"; +- function = "gpio"; +- bias-pull-up; +- drive-strength = <2>; +- }; +-}; +- +-&uart12 { +- status = "okay"; +-}; +- +-/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */ +-&ufs_mem_hc { status = "disabled"; }; +-&ufs_mem_phy { status = "disabled"; }; +- +-&usb_1 { +- status = "okay"; +-}; +- +-&usb_1_dwc3 { +- dr_mode = "peripheral"; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- +- vdda-pll-supply = <&vreg_l5a_0p88>; +- vdda18-supply = <&vreg_l12a_1p8>; +- vdda33-supply = <&vreg_l2a_3p1>; +-}; +- +-&usb_1_qmpphy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l9a_1p2>; +- vdda-pll-supply = <&vreg_l18a_0p9>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sm8250.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sm8250.dtsi +deleted file mode 100644 +index d12e4cbfc852..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sm8250.dtsi ++++ /dev/null +@@ -1,4855 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&intc>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c7; +- i2c8 = &i2c8; +- i2c9 = &i2c9; +- i2c10 = &i2c10; +- i2c11 = &i2c11; +- i2c12 = &i2c12; +- i2c13 = &i2c13; +- i2c14 = &i2c14; +- i2c15 = &i2c15; +- i2c16 = &i2c16; +- i2c17 = &i2c17; +- i2c18 = &i2c18; +- i2c19 = &i2c19; +- spi0 = &spi0; +- spi1 = &spi1; +- spi2 = &spi2; +- spi3 = &spi3; +- spi4 = &spi4; +- spi5 = &spi5; +- spi6 = &spi6; +- spi7 = &spi7; +- spi8 = &spi8; +- spi9 = &spi9; +- spi10 = &spi10; +- spi11 = &spi11; +- spi12 = &spi12; +- spi13 = &spi13; +- spi14 = &spi14; +- spi15 = &spi15; +- spi16 = &spi16; +- spi17 = &spi17; +- spi18 = &spi18; +- spi19 = &spi19; +- }; +- +- chosen { }; +- +- clocks { +- xo_board: xo-board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <38400000>; +- clock-output-names = "xo_board"; +- }; +- +- sleep_clk: sleep-clk { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- #clock-cells = <0>; +- }; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- CPU0: cpu@0 { +- device_type = "cpu"; +- compatible = "qcom,kryo485"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- capacity-dmips-mhz = <448>; +- dynamic-power-coefficient = <205>; +- next-level-cache = <&L2_0>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- #cooling-cells = <2>; +- L2_0: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- L3_0: l3-cache { +- compatible = "cache"; +- }; +- }; +- }; +- +- CPU1: cpu@100 { +- device_type = "cpu"; +- compatible = "qcom,kryo485"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- capacity-dmips-mhz = <448>; +- dynamic-power-coefficient = <205>; +- next-level-cache = <&L2_100>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- #cooling-cells = <2>; +- L2_100: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU2: cpu@200 { +- device_type = "cpu"; +- compatible = "qcom,kryo485"; +- reg = <0x0 0x200>; +- enable-method = "psci"; +- capacity-dmips-mhz = <448>; +- dynamic-power-coefficient = <205>; +- next-level-cache = <&L2_200>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- #cooling-cells = <2>; +- L2_200: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU3: cpu@300 { +- device_type = "cpu"; +- compatible = "qcom,kryo485"; +- reg = <0x0 0x300>; +- enable-method = "psci"; +- capacity-dmips-mhz = <448>; +- dynamic-power-coefficient = <205>; +- next-level-cache = <&L2_300>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- #cooling-cells = <2>; +- L2_300: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU4: cpu@400 { +- device_type = "cpu"; +- compatible = "qcom,kryo485"; +- reg = <0x0 0x400>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <379>; +- next-level-cache = <&L2_400>; +- qcom,freq-domain = <&cpufreq_hw 1>; +- #cooling-cells = <2>; +- L2_400: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU5: cpu@500 { +- device_type = "cpu"; +- compatible = "qcom,kryo485"; +- reg = <0x0 0x500>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <379>; +- next-level-cache = <&L2_500>; +- qcom,freq-domain = <&cpufreq_hw 1>; +- #cooling-cells = <2>; +- L2_500: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- +- }; +- +- CPU6: cpu@600 { +- device_type = "cpu"; +- compatible = "qcom,kryo485"; +- reg = <0x0 0x600>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <379>; +- next-level-cache = <&L2_600>; +- qcom,freq-domain = <&cpufreq_hw 1>; +- #cooling-cells = <2>; +- L2_600: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU7: cpu@700 { +- device_type = "cpu"; +- compatible = "qcom,kryo485"; +- reg = <0x0 0x700>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- dynamic-power-coefficient = <444>; +- next-level-cache = <&L2_700>; +- qcom,freq-domain = <&cpufreq_hw 2>; +- #cooling-cells = <2>; +- L2_700: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&CPU0>; +- }; +- +- core1 { +- cpu = <&CPU1>; +- }; +- +- core2 { +- cpu = <&CPU2>; +- }; +- +- core3 { +- cpu = <&CPU3>; +- }; +- +- core4 { +- cpu = <&CPU4>; +- }; +- +- core5 { +- cpu = <&CPU5>; +- }; +- +- core6 { +- cpu = <&CPU6>; +- }; +- +- core7 { +- cpu = <&CPU7>; +- }; +- }; +- }; +- }; +- +- firmware { +- scm: scm { +- compatible = "qcom,scm"; +- #reset-cells = <1>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- /* We expect the bootloader to fill in the size */ +- reg = <0x0 0x80000000 0x0 0x0>; +- }; +- +- mmcx_reg: mmcx-reg { +- compatible = "regulator-fixed-domain"; +- power-domains = <&rpmhpd SM8250_MMCX>; +- required-opps = <&rpmhpd_opp_low_svs>; +- regulator-name = "MMCX"; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- hyp_mem: memory@80000000 { +- reg = <0x0 0x80000000 0x0 0x600000>; +- no-map; +- }; +- +- xbl_aop_mem: memory@80700000 { +- reg = <0x0 0x80700000 0x0 0x160000>; +- no-map; +- }; +- +- cmd_db: memory@80860000 { +- compatible = "qcom,cmd-db"; +- reg = <0x0 0x80860000 0x0 0x20000>; +- no-map; +- }; +- +- smem_mem: memory@80900000 { +- reg = <0x0 0x80900000 0x0 0x200000>; +- no-map; +- }; +- +- removed_mem: memory@80b00000 { +- reg = <0x0 0x80b00000 0x0 0x5300000>; +- no-map; +- }; +- +- camera_mem: memory@86200000 { +- reg = <0x0 0x86200000 0x0 0x500000>; +- no-map; +- }; +- +- wlan_mem: memory@86700000 { +- reg = <0x0 0x86700000 0x0 0x100000>; +- no-map; +- }; +- +- ipa_fw_mem: memory@86800000 { +- reg = <0x0 0x86800000 0x0 0x10000>; +- no-map; +- }; +- +- ipa_gsi_mem: memory@86810000 { +- reg = <0x0 0x86810000 0x0 0xa000>; +- no-map; +- }; +- +- gpu_mem: memory@8681a000 { +- reg = <0x0 0x8681a000 0x0 0x2000>; +- no-map; +- }; +- +- npu_mem: memory@86900000 { +- reg = <0x0 0x86900000 0x0 0x500000>; +- no-map; +- }; +- +- video_mem: memory@86e00000 { +- reg = <0x0 0x86e00000 0x0 0x500000>; +- no-map; +- }; +- +- cvp_mem: memory@87300000 { +- reg = <0x0 0x87300000 0x0 0x500000>; +- no-map; +- }; +- +- cdsp_mem: memory@87800000 { +- reg = <0x0 0x87800000 0x0 0x1400000>; +- no-map; +- }; +- +- slpi_mem: memory@88c00000 { +- reg = <0x0 0x88c00000 0x0 0x1500000>; +- no-map; +- }; +- +- adsp_mem: memory@8a100000 { +- reg = <0x0 0x8a100000 0x0 0x1d00000>; +- no-map; +- }; +- +- spss_mem: memory@8be00000 { +- reg = <0x0 0x8be00000 0x0 0x100000>; +- no-map; +- }; +- +- cdsp_secure_heap: memory@8bf00000 { +- reg = <0x0 0x8bf00000 0x0 0x4600000>; +- no-map; +- }; +- }; +- +- smem { +- compatible = "qcom,smem"; +- memory-region = <&smem_mem>; +- hwlocks = <&tcsr_mutex 3>; +- }; +- +- smp2p-adsp { +- compatible = "qcom,smp2p"; +- qcom,smem = <443>, <429>; +- interrupts-extended = <&ipcc IPCC_CLIENT_LPASS +- IPCC_MPROC_SIGNAL_SMP2P +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_LPASS +- IPCC_MPROC_SIGNAL_SMP2P>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <2>; +- +- smp2p_adsp_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- smp2p_adsp_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-cdsp { +- compatible = "qcom,smp2p"; +- qcom,smem = <94>, <432>; +- interrupts-extended = <&ipcc IPCC_CLIENT_CDSP +- IPCC_MPROC_SIGNAL_SMP2P +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_CDSP +- IPCC_MPROC_SIGNAL_SMP2P>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <5>; +- +- smp2p_cdsp_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- smp2p_cdsp_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-slpi { +- compatible = "qcom,smp2p"; +- qcom,smem = <481>, <430>; +- interrupts-extended = <&ipcc IPCC_CLIENT_SLPI +- IPCC_MPROC_SIGNAL_SMP2P +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_SLPI +- IPCC_MPROC_SIGNAL_SMP2P>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <3>; +- +- smp2p_slpi_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- smp2p_slpi_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- soc: soc@0 { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0 0 0 0 0x10 0>; +- dma-ranges = <0 0 0 0 0x10 0>; +- compatible = "simple-bus"; +- +- gcc: clock-controller@100000 { +- compatible = "qcom,gcc-sm8250"; +- reg = <0x0 0x00100000 0x0 0x1f0000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- clock-names = "bi_tcxo", +- "bi_tcxo_ao", +- "sleep_clk"; +- clocks = <&rpmhcc RPMH_CXO_CLK>, +- <&rpmhcc RPMH_CXO_CLK_A>, +- <&sleep_clk>; +- }; +- +- ipcc: mailbox@408000 { +- compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; +- reg = <0 0x00408000 0 0x1000>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- #mbox-cells = <2>; +- }; +- +- rng: rng@793000 { +- compatible = "qcom,prng-ee"; +- reg = <0 0x00793000 0 0x1000>; +- clocks = <&gcc GCC_PRNG_AHB_CLK>; +- clock-names = "core"; +- }; +- +- qup_opp_table: qup-opp-table { +- compatible = "operating-points-v2"; +- +- opp-50000000 { +- opp-hz = /bits/ 64 <50000000>; +- required-opps = <&rpmhpd_opp_min_svs>; +- }; +- +- opp-75000000 { +- opp-hz = /bits/ 64 <75000000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- }; +- +- opp-120000000 { +- opp-hz = /bits/ 64 <120000000>; +- required-opps = <&rpmhpd_opp_svs>; +- }; +- }; +- +- gpi_dma2: dma-controller@800000 { +- compatible = "qcom,sm8250-gpi-dma"; +- reg = <0 0x00800000 0 0x70000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- dma-channels = <10>; +- dma-channel-mask = <0x3f>; +- iommus = <&apps_smmu 0x76 0x0>; +- #dma-cells = <3>; +- status = "disabled"; +- }; +- +- qupv3_id_2: geniqup@8c0000 { +- compatible = "qcom,geni-se-qup"; +- reg = <0x0 0x008c0000 0x0 0x6000>; +- clock-names = "m-ahb", "s-ahb"; +- clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, +- <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; +- #address-cells = <2>; +- #size-cells = <2>; +- iommus = <&apps_smmu 0x63 0x0>; +- ranges; +- status = "disabled"; +- +- i2c14: i2c@880000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00880000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c14_default>; +- interrupts = ; +- dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, +- <&gpi_dma2 1 0 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi14: spi@880000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00880000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; +- interrupts = ; +- dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, +- <&gpi_dma2 1 0 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c15: i2c@884000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00884000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c15_default>; +- interrupts = ; +- dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, +- <&gpi_dma2 1 1 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi15: spi@884000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00884000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; +- interrupts = ; +- dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, +- <&gpi_dma2 1 1 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c16: i2c@888000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00888000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c16_default>; +- interrupts = ; +- dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, +- <&gpi_dma2 1 2 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi16: spi@888000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00888000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; +- interrupts = ; +- dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, +- <&gpi_dma2 1 2 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c17: i2c@88c000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x0088c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c17_default>; +- interrupts = ; +- dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, +- <&gpi_dma2 1 3 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi17: spi@88c000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x0088c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; +- interrupts = ; +- dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, +- <&gpi_dma2 1 3 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- uart17: serial@88c000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x0088c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart17_default>; +- interrupts = ; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- status = "disabled"; +- }; +- +- i2c18: i2c@890000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00890000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c18_default>; +- interrupts = ; +- dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, +- <&gpi_dma2 1 4 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi18: spi@890000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00890000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; +- interrupts = ; +- dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, +- <&gpi_dma2 1 4 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- uart18: serial@890000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00890000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart18_default>; +- interrupts = ; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- status = "disabled"; +- }; +- +- i2c19: i2c@894000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00894000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c19_default>; +- interrupts = ; +- dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, +- <&gpi_dma2 1 5 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi19: spi@894000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00894000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; +- interrupts = ; +- dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, +- <&gpi_dma2 1 5 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- gpi_dma0: dma-controller@900000 { +- compatible = "qcom,sm8250-gpi-dma"; +- reg = <0 0x00900000 0 0x70000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- dma-channels = <15>; +- dma-channel-mask = <0x7ff>; +- iommus = <&apps_smmu 0x5b6 0x0>; +- #dma-cells = <3>; +- status = "disabled"; +- }; +- +- qupv3_id_0: geniqup@9c0000 { +- compatible = "qcom,geni-se-qup"; +- reg = <0x0 0x009c0000 0x0 0x6000>; +- clock-names = "m-ahb", "s-ahb"; +- clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, +- <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; +- #address-cells = <2>; +- #size-cells = <2>; +- iommus = <&apps_smmu 0x5a3 0x0>; +- ranges; +- status = "disabled"; +- +- i2c0: i2c@980000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00980000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c0_default>; +- interrupts = ; +- dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, +- <&gpi_dma0 1 0 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi0: spi@980000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00980000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; +- interrupts = ; +- dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, +- <&gpi_dma0 1 0 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@984000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00984000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c1_default>; +- interrupts = ; +- dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, +- <&gpi_dma0 1 1 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi1: spi@984000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00984000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; +- interrupts = ; +- dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, +- <&gpi_dma0 1 1 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@988000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00988000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c2_default>; +- interrupts = ; +- dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, +- <&gpi_dma0 1 2 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi2: spi@988000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00988000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; +- interrupts = ; +- dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, +- <&gpi_dma0 1 2 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- uart2: serial@988000 { +- compatible = "qcom,geni-debug-uart"; +- reg = <0 0x00988000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart2_default>; +- interrupts = ; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- status = "disabled"; +- }; +- +- i2c3: i2c@98c000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x0098c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c3_default>; +- interrupts = ; +- dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, +- <&gpi_dma0 1 3 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi3: spi@98c000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x0098c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; +- interrupts = ; +- dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, +- <&gpi_dma0 1 3 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@990000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00990000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c4_default>; +- interrupts = ; +- dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, +- <&gpi_dma0 1 4 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi4: spi@990000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00990000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; +- interrupts = ; +- dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, +- <&gpi_dma0 1 4 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c5: i2c@994000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00994000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c5_default>; +- interrupts = ; +- dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, +- <&gpi_dma0 1 5 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi5: spi@994000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00994000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; +- interrupts = ; +- dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, +- <&gpi_dma0 1 5 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c6: i2c@998000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00998000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c6_default>; +- interrupts = ; +- dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, +- <&gpi_dma0 1 6 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi6: spi@998000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00998000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; +- interrupts = ; +- dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, +- <&gpi_dma0 1 6 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- uart6: serial@998000 { +- compatible = "qcom,geni-uart"; +- reg = <0 0x00998000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart6_default>; +- interrupts = ; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- status = "disabled"; +- }; +- +- i2c7: i2c@99c000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x0099c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c7_default>; +- interrupts = ; +- dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, +- <&gpi_dma0 1 7 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi7: spi@99c000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x0099c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; +- interrupts = ; +- dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, +- <&gpi_dma0 1 7 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- gpi_dma1: dma-controller@a00000 { +- compatible = "qcom,sm8250-gpi-dma"; +- reg = <0 0x00a00000 0 0x70000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- dma-channels = <10>; +- dma-channel-mask = <0x3f>; +- iommus = <&apps_smmu 0x56 0x0>; +- #dma-cells = <3>; +- status = "disabled"; +- }; +- +- qupv3_id_1: geniqup@ac0000 { +- compatible = "qcom,geni-se-qup"; +- reg = <0x0 0x00ac0000 0x0 0x6000>; +- clock-names = "m-ahb", "s-ahb"; +- clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, +- <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; +- #address-cells = <2>; +- #size-cells = <2>; +- iommus = <&apps_smmu 0x43 0x0>; +- ranges; +- status = "disabled"; +- +- i2c8: i2c@a80000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a80000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c8_default>; +- interrupts = ; +- dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, +- <&gpi_dma1 1 0 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi8: spi@a80000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00a80000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; +- interrupts = ; +- dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, +- <&gpi_dma1 1 0 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c9: i2c@a84000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a84000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c9_default>; +- interrupts = ; +- dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, +- <&gpi_dma1 1 1 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi9: spi@a84000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00a84000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; +- interrupts = ; +- dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, +- <&gpi_dma1 1 1 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c10: i2c@a88000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a88000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c10_default>; +- interrupts = ; +- dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, +- <&gpi_dma1 1 2 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi10: spi@a88000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00a88000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; +- interrupts = ; +- dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, +- <&gpi_dma1 1 2 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c11: i2c@a8c000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a8c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c11_default>; +- interrupts = ; +- dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, +- <&gpi_dma1 1 3 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi11: spi@a8c000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00a8c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; +- interrupts = ; +- dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, +- <&gpi_dma1 1 3 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c12: i2c@a90000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a90000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c12_default>; +- interrupts = ; +- dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, +- <&gpi_dma1 1 4 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi12: spi@a90000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00a90000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; +- interrupts = ; +- dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, +- <&gpi_dma1 1 4 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- uart12: serial@a90000 { +- compatible = "qcom,geni-debug-uart"; +- reg = <0x0 0x00a90000 0x0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart12_default>; +- interrupts = ; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- status = "disabled"; +- }; +- +- i2c13: i2c@a94000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a94000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c13_default>; +- interrupts = ; +- dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, +- <&gpi_dma1 1 5 QCOM_GPI_I2C>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi13: spi@a94000 { +- compatible = "qcom,geni-spi"; +- reg = <0 0x00a94000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; +- interrupts = ; +- dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, +- <&gpi_dma1 1 5 QCOM_GPI_SPI>; +- dma-names = "tx", "rx"; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&qup_opp_table>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- config_noc: interconnect@1500000 { +- compatible = "qcom,sm8250-config-noc"; +- reg = <0 0x01500000 0 0xa580>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- system_noc: interconnect@1620000 { +- compatible = "qcom,sm8250-system-noc"; +- reg = <0 0x01620000 0 0x1c200>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- mc_virt: interconnect@163d000 { +- compatible = "qcom,sm8250-mc-virt"; +- reg = <0 0x0163d000 0 0x1000>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- aggre1_noc: interconnect@16e0000 { +- compatible = "qcom,sm8250-aggre1-noc"; +- reg = <0 0x016e0000 0 0x1f180>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- aggre2_noc: interconnect@1700000 { +- compatible = "qcom,sm8250-aggre2-noc"; +- reg = <0 0x01700000 0 0x33000>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- compute_noc: interconnect@1733000 { +- compatible = "qcom,sm8250-compute-noc"; +- reg = <0 0x01733000 0 0xa180>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- mmss_noc: interconnect@1740000 { +- compatible = "qcom,sm8250-mmss-noc"; +- reg = <0 0x01740000 0 0x1f080>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- pcie0: pci@1c00000 { +- compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; +- reg = <0 0x01c00000 0 0x3000>, +- <0 0x60000000 0 0xf1d>, +- <0 0x60000f20 0 0xa8>, +- <0 0x60001000 0 0x1000>, +- <0 0x60100000 0 0x100000>; +- reg-names = "parf", "dbi", "elbi", "atu", "config"; +- device_type = "pci"; +- linux,pci-domain = <0>; +- bus-range = <0x00 0xff>; +- num-lanes = <1>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, +- <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; +- +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ +- <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ +- <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ +- <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ +- +- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, +- <&gcc GCC_PCIE_0_AUX_CLK>, +- <&gcc GCC_PCIE_0_CFG_AHB_CLK>, +- <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, +- <&gcc GCC_PCIE_0_SLV_AXI_CLK>, +- <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, +- <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, +- <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; +- clock-names = "pipe", +- "aux", +- "cfg", +- "bus_master", +- "bus_slave", +- "slave_q2a", +- "tbu", +- "ddrss_sf_tbu"; +- +- iommus = <&apps_smmu 0x1c00 0x7f>; +- iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, +- <0x100 &apps_smmu 0x1c01 0x1>; +- +- resets = <&gcc GCC_PCIE_0_BCR>; +- reset-names = "pci"; +- +- power-domains = <&gcc PCIE_0_GDSC>; +- +- phys = <&pcie0_lane>; +- phy-names = "pciephy"; +- +- perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; +- enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_default_state>; +- +- status = "disabled"; +- }; +- +- pcie0_phy: phy@1c06000 { +- compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; +- reg = <0 0x01c06000 0 0x1c0>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, +- <&gcc GCC_PCIE_0_CFG_AHB_CLK>, +- <&gcc GCC_PCIE_WIFI_CLKREF_EN>, +- <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; +- clock-names = "aux", "cfg_ahb", "ref", "refgen"; +- +- resets = <&gcc GCC_PCIE_0_PHY_BCR>; +- reset-names = "phy"; +- +- assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; +- assigned-clock-rates = <100000000>; +- +- status = "disabled"; +- +- pcie0_lane: lanes@1c06200 { +- reg = <0 0x1c06200 0 0x170>, /* tx */ +- <0 0x1c06400 0 0x200>, /* rx */ +- <0 0x1c06800 0 0x1f0>, /* pcs */ +- <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ +- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; +- clock-names = "pipe0"; +- +- #phy-cells = <0>; +- clock-output-names = "pcie_0_pipe_clk"; +- }; +- }; +- +- pcie1: pci@1c08000 { +- compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; +- reg = <0 0x01c08000 0 0x3000>, +- <0 0x40000000 0 0xf1d>, +- <0 0x40000f20 0 0xa8>, +- <0 0x40001000 0 0x1000>, +- <0 0x40100000 0 0x100000>; +- reg-names = "parf", "dbi", "elbi", "atu", "config"; +- device_type = "pci"; +- linux,pci-domain = <1>; +- bus-range = <0x00 0xff>; +- num-lanes = <2>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, +- <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; +- +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ +- <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ +- <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ +- <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ +- +- clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, +- <&gcc GCC_PCIE_1_AUX_CLK>, +- <&gcc GCC_PCIE_1_CFG_AHB_CLK>, +- <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, +- <&gcc GCC_PCIE_1_SLV_AXI_CLK>, +- <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, +- <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, +- <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, +- <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; +- clock-names = "pipe", +- "aux", +- "cfg", +- "bus_master", +- "bus_slave", +- "slave_q2a", +- "ref", +- "tbu", +- "ddrss_sf_tbu"; +- +- assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; +- assigned-clock-rates = <19200000>; +- +- iommus = <&apps_smmu 0x1c80 0x7f>; +- iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, +- <0x100 &apps_smmu 0x1c81 0x1>; +- +- resets = <&gcc GCC_PCIE_1_BCR>; +- reset-names = "pci"; +- +- power-domains = <&gcc PCIE_1_GDSC>; +- +- phys = <&pcie1_lane>; +- phy-names = "pciephy"; +- +- perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>; +- enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie1_default_state>; +- +- status = "disabled"; +- }; +- +- pcie1_phy: phy@1c0e000 { +- compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; +- reg = <0 0x01c0e000 0 0x1c0>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, +- <&gcc GCC_PCIE_1_CFG_AHB_CLK>, +- <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, +- <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; +- clock-names = "aux", "cfg_ahb", "ref", "refgen"; +- +- resets = <&gcc GCC_PCIE_1_PHY_BCR>; +- reset-names = "phy"; +- +- assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; +- assigned-clock-rates = <100000000>; +- +- status = "disabled"; +- +- pcie1_lane: lanes@1c0e200 { +- reg = <0 0x1c0e200 0 0x170>, /* tx0 */ +- <0 0x1c0e400 0 0x200>, /* rx0 */ +- <0 0x1c0ea00 0 0x1f0>, /* pcs */ +- <0 0x1c0e600 0 0x170>, /* tx1 */ +- <0 0x1c0e800 0 0x200>, /* rx1 */ +- <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ +- clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; +- clock-names = "pipe0"; +- +- #phy-cells = <0>; +- clock-output-names = "pcie_1_pipe_clk"; +- }; +- }; +- +- pcie2: pci@1c10000 { +- compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; +- reg = <0 0x01c10000 0 0x3000>, +- <0 0x64000000 0 0xf1d>, +- <0 0x64000f20 0 0xa8>, +- <0 0x64001000 0 0x1000>, +- <0 0x64100000 0 0x100000>; +- reg-names = "parf", "dbi", "elbi", "atu", "config"; +- device_type = "pci"; +- linux,pci-domain = <2>; +- bus-range = <0x00 0xff>; +- num-lanes = <2>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, +- <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; +- +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ +- <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ +- <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ +- <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ +- +- clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, +- <&gcc GCC_PCIE_2_AUX_CLK>, +- <&gcc GCC_PCIE_2_CFG_AHB_CLK>, +- <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, +- <&gcc GCC_PCIE_2_SLV_AXI_CLK>, +- <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, +- <&gcc GCC_PCIE_MDM_CLKREF_EN>, +- <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, +- <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; +- clock-names = "pipe", +- "aux", +- "cfg", +- "bus_master", +- "bus_slave", +- "slave_q2a", +- "ref", +- "tbu", +- "ddrss_sf_tbu"; +- +- assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; +- assigned-clock-rates = <19200000>; +- +- iommus = <&apps_smmu 0x1d00 0x7f>; +- iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, +- <0x100 &apps_smmu 0x1d01 0x1>; +- +- resets = <&gcc GCC_PCIE_2_BCR>; +- reset-names = "pci"; +- +- power-domains = <&gcc PCIE_2_GDSC>; +- +- phys = <&pcie2_lane>; +- phy-names = "pciephy"; +- +- perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>; +- enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_default_state>; +- +- status = "disabled"; +- }; +- +- pcie2_phy: phy@1c16000 { +- compatible = "qcom,sm8250-qmp-modem-pcie-phy"; +- reg = <0 0x1c16000 0 0x1c0>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, +- <&gcc GCC_PCIE_2_CFG_AHB_CLK>, +- <&gcc GCC_PCIE_MDM_CLKREF_EN>, +- <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; +- clock-names = "aux", "cfg_ahb", "ref", "refgen"; +- +- resets = <&gcc GCC_PCIE_2_PHY_BCR>; +- reset-names = "phy"; +- +- assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; +- assigned-clock-rates = <100000000>; +- +- status = "disabled"; +- +- pcie2_lane: lanes@1c16200 { +- reg = <0 0x1c16200 0 0x170>, /* tx0 */ +- <0 0x1c16400 0 0x200>, /* rx0 */ +- <0 0x1c16a00 0 0x1f0>, /* pcs */ +- <0 0x1c16600 0 0x170>, /* tx1 */ +- <0 0x1c16800 0 0x200>, /* rx1 */ +- <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ +- clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; +- clock-names = "pipe0"; +- +- #phy-cells = <0>; +- clock-output-names = "pcie_2_pipe_clk"; +- }; +- }; +- +- ufs_mem_hc: ufshc@1d84000 { +- compatible = "qcom,sm8250-ufshc", "qcom,ufshc", +- "jedec,ufs-2.0"; +- reg = <0 0x01d84000 0 0x3000>; +- interrupts = ; +- phys = <&ufs_mem_phy_lanes>; +- phy-names = "ufsphy"; +- lanes-per-direction = <2>; +- #reset-cells = <1>; +- resets = <&gcc GCC_UFS_PHY_BCR>; +- reset-names = "rst"; +- +- power-domains = <&gcc UFS_PHY_GDSC>; +- +- iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; +- +- clock-names = +- "core_clk", +- "bus_aggr_clk", +- "iface_clk", +- "core_clk_unipro", +- "ref_clk", +- "tx_lane0_sync_clk", +- "rx_lane0_sync_clk", +- "rx_lane1_sync_clk"; +- clocks = +- <&gcc GCC_UFS_PHY_AXI_CLK>, +- <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, +- <&gcc GCC_UFS_PHY_AHB_CLK>, +- <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, +- <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, +- <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, +- <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; +- freq-table-hz = +- <37500000 300000000>, +- <0 0>, +- <0 0>, +- <37500000 300000000>, +- <0 0>, +- <0 0>, +- <0 0>, +- <0 0>; +- +- status = "disabled"; +- }; +- +- ufs_mem_phy: phy@1d87000 { +- compatible = "qcom,sm8250-qmp-ufs-phy"; +- reg = <0 0x01d87000 0 0x1c0>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- clock-names = "ref", +- "ref_aux"; +- clocks = <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; +- +- resets = <&ufs_mem_hc 0>; +- reset-names = "ufsphy"; +- status = "disabled"; +- +- ufs_mem_phy_lanes: lanes@1d87400 { +- reg = <0 0x01d87400 0 0x108>, +- <0 0x01d87600 0 0x1e0>, +- <0 0x01d87c00 0 0x1dc>, +- <0 0x01d87800 0 0x108>, +- <0 0x01d87a00 0 0x1e0>; +- #phy-cells = <0>; +- }; +- }; +- +- ipa_virt: interconnect@1e00000 { +- compatible = "qcom,sm8250-ipa-virt"; +- reg = <0 0x01e00000 0 0x1000>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- tcsr_mutex: hwlock@1f40000 { +- compatible = "qcom,tcsr-mutex"; +- reg = <0x0 0x01f40000 0x0 0x40000>; +- #hwlock-cells = <1>; +- }; +- +- wsamacro: codec@3240000 { +- compatible = "qcom,sm8250-lpass-wsa-macro"; +- reg = <0 0x03240000 0 0x1000>; +- clocks = <&audiocc 1>, +- <&audiocc 0>, +- <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, +- <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, +- <&aoncc 0>, +- <&vamacro>; +- +- clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; +- +- #clock-cells = <0>; +- clock-frequency = <9600000>; +- clock-output-names = "mclk"; +- #sound-dai-cells = <1>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&wsa_swr_active>; +- }; +- +- swr0: soundwire-controller@3250000 { +- reg = <0 0x03250000 0 0x2000>; +- compatible = "qcom,soundwire-v1.5.1"; +- interrupts = ; +- clocks = <&wsamacro>; +- clock-names = "iface"; +- +- qcom,din-ports = <2>; +- qcom,dout-ports = <6>; +- +- qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; +- qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; +- qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; +- qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; +- +- #sound-dai-cells = <1>; +- #address-cells = <2>; +- #size-cells = <0>; +- }; +- +- audiocc: clock-controller@3300000 { +- compatible = "qcom,sm8250-lpass-audiocc"; +- reg = <0 0x03300000 0 0x30000>; +- #clock-cells = <1>; +- clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, +- <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, +- <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; +- clock-names = "core", "audio", "bus"; +- }; +- +- vamacro: codec@3370000 { +- compatible = "qcom,sm8250-lpass-va-macro"; +- reg = <0 0x03370000 0 0x1000>; +- clocks = <&aoncc 0>, +- <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, +- <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; +- +- clock-names = "mclk", "macro", "dcodec"; +- +- #clock-cells = <0>; +- clock-frequency = <9600000>; +- clock-output-names = "fsgen"; +- #sound-dai-cells = <1>; +- }; +- +- aoncc: clock-controller@3380000 { +- compatible = "qcom,sm8250-lpass-aoncc"; +- reg = <0 0x03380000 0 0x40000>; +- #clock-cells = <1>; +- clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, +- <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, +- <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; +- clock-names = "core", "audio", "bus"; +- }; +- +- lpass_tlmm: pinctrl@33c0000{ +- compatible = "qcom,sm8250-lpass-lpi-pinctrl"; +- reg = <0 0x033c0000 0x0 0x20000>, +- <0 0x03550000 0x0 0x10000>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&lpass_tlmm 0 0 14>; +- +- clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, +- <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; +- clock-names = "core", "audio"; +- +- wsa_swr_active: wsa-swr-active-pins { +- clk { +- pins = "gpio10"; +- function = "wsa_swr_clk"; +- drive-strength = <2>; +- slew-rate = <1>; +- bias-disable; +- }; +- +- data { +- pins = "gpio11"; +- function = "wsa_swr_data"; +- drive-strength = <2>; +- slew-rate = <1>; +- bias-bus-hold; +- +- }; +- }; +- +- wsa_swr_sleep: wsa-swr-sleep-pins { +- clk { +- pins = "gpio10"; +- function = "wsa_swr_clk"; +- drive-strength = <2>; +- input-enable; +- bias-pull-down; +- }; +- +- data { +- pins = "gpio11"; +- function = "wsa_swr_data"; +- drive-strength = <2>; +- input-enable; +- bias-pull-down; +- +- }; +- }; +- +- dmic01_active: dmic01-active-pins { +- clk { +- pins = "gpio6"; +- function = "dmic1_clk"; +- drive-strength = <8>; +- output-high; +- }; +- data { +- pins = "gpio7"; +- function = "dmic1_data"; +- drive-strength = <8>; +- input-enable; +- }; +- }; +- +- dmic01_sleep: dmic01-sleep-pins { +- clk { +- pins = "gpio6"; +- function = "dmic1_clk"; +- drive-strength = <2>; +- bias-disable; +- output-low; +- }; +- +- data { +- pins = "gpio7"; +- function = "dmic1_data"; +- drive-strength = <2>; +- pull-down; +- input-enable; +- }; +- }; +- }; +- +- gpu: gpu@3d00000 { +- compatible = "qcom,adreno-650.2", +- "qcom,adreno"; +- #stream-id-cells = <16>; +- +- reg = <0 0x03d00000 0 0x40000>; +- reg-names = "kgsl_3d0_reg_memory"; +- +- interrupts = ; +- +- iommus = <&adreno_smmu 0 0x401>; +- +- operating-points-v2 = <&gpu_opp_table>; +- +- qcom,gmu = <&gmu>; +- +- status = "disabled"; +- +- zap-shader { +- memory-region = <&gpu_mem>; +- }; +- +- /* note: downstream checks gpu binning for 670 Mhz */ +- gpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-670000000 { +- opp-hz = /bits/ 64 <670000000>; +- opp-level = ; +- }; +- +- opp-587000000 { +- opp-hz = /bits/ 64 <587000000>; +- opp-level = ; +- }; +- +- opp-525000000 { +- opp-hz = /bits/ 64 <525000000>; +- opp-level = ; +- }; +- +- opp-490000000 { +- opp-hz = /bits/ 64 <490000000>; +- opp-level = ; +- }; +- +- opp-441600000 { +- opp-hz = /bits/ 64 <441600000>; +- opp-level = ; +- }; +- +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-level = ; +- }; +- +- opp-305000000 { +- opp-hz = /bits/ 64 <305000000>; +- opp-level = ; +- }; +- }; +- }; +- +- gmu: gmu@3d6a000 { +- compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; +- +- reg = <0 0x03d6a000 0 0x30000>, +- <0 0x3de0000 0 0x10000>, +- <0 0xb290000 0 0x10000>, +- <0 0xb490000 0 0x10000>; +- reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; +- +- interrupts = , +- ; +- interrupt-names = "hfi", "gmu"; +- +- clocks = <&gpucc GPU_CC_AHB_CLK>, +- <&gpucc GPU_CC_CX_GMU_CLK>, +- <&gpucc GPU_CC_CXO_CLK>, +- <&gcc GCC_DDRSS_GPU_AXI_CLK>, +- <&gcc GCC_GPU_MEMNOC_GFX_CLK>; +- clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; +- +- power-domains = <&gpucc GPU_CX_GDSC>, +- <&gpucc GPU_GX_GDSC>; +- power-domain-names = "cx", "gx"; +- +- iommus = <&adreno_smmu 5 0x400>; +- +- operating-points-v2 = <&gmu_opp_table>; +- +- status = "disabled"; +- +- gmu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- opp-level = ; +- }; +- }; +- }; +- +- gpucc: clock-controller@3d90000 { +- compatible = "qcom,sm8250-gpucc"; +- reg = <0 0x03d90000 0 0x9000>; +- clocks = <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_GPU_GPLL0_CLK_SRC>, +- <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; +- clock-names = "bi_tcxo", +- "gcc_gpu_gpll0_clk_src", +- "gcc_gpu_gpll0_div_clk_src"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- }; +- +- adreno_smmu: iommu@3da0000 { +- compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; +- reg = <0 0x03da0000 0 0x10000>; +- #iommu-cells = <2>; +- #global-interrupts = <2>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&gpucc GPU_CC_AHB_CLK>, +- <&gcc GCC_GPU_MEMNOC_GFX_CLK>, +- <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; +- clock-names = "ahb", "bus", "iface"; +- +- power-domains = <&gpucc GPU_CX_GDSC>; +- }; +- +- slpi: remoteproc@5c00000 { +- compatible = "qcom,sm8250-slpi-pas"; +- reg = <0 0x05c00000 0 0x4000>; +- +- interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, +- <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack"; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "xo"; +- +- power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, +- <&rpmhpd SM8250_LCX>, +- <&rpmhpd SM8250_LMX>; +- power-domain-names = "load_state", "lcx", "lmx"; +- +- memory-region = <&slpi_mem>; +- +- qcom,smem-states = <&smp2p_slpi_out 0>; +- qcom,smem-state-names = "stop"; +- +- status = "disabled"; +- +- glink-edge { +- interrupts-extended = <&ipcc IPCC_CLIENT_SLPI +- IPCC_MPROC_SIGNAL_GLINK_QMP +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_SLPI +- IPCC_MPROC_SIGNAL_GLINK_QMP>; +- +- label = "slpi"; +- qcom,remote-pid = <3>; +- +- fastrpc { +- compatible = "qcom,fastrpc"; +- qcom,glink-channels = "fastrpcglink-apps-dsp"; +- label = "sdsp"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- compute-cb@1 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <1>; +- iommus = <&apps_smmu 0x0541 0x0>; +- }; +- +- compute-cb@2 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <2>; +- iommus = <&apps_smmu 0x0542 0x0>; +- }; +- +- compute-cb@3 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <3>; +- iommus = <&apps_smmu 0x0543 0x0>; +- /* note: shared-cb = <4> in downstream */ +- }; +- }; +- }; +- }; +- +- cdsp: remoteproc@8300000 { +- compatible = "qcom,sm8250-cdsp-pas"; +- reg = <0 0x08300000 0 0x10000>; +- +- interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, +- <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack"; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "xo"; +- +- power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, +- <&rpmhpd SM8250_CX>; +- power-domain-names = "load_state", "cx"; +- +- memory-region = <&cdsp_mem>; +- +- qcom,smem-states = <&smp2p_cdsp_out 0>; +- qcom,smem-state-names = "stop"; +- +- status = "disabled"; +- +- glink-edge { +- interrupts-extended = <&ipcc IPCC_CLIENT_CDSP +- IPCC_MPROC_SIGNAL_GLINK_QMP +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_CDSP +- IPCC_MPROC_SIGNAL_GLINK_QMP>; +- +- label = "cdsp"; +- qcom,remote-pid = <5>; +- +- fastrpc { +- compatible = "qcom,fastrpc"; +- qcom,glink-channels = "fastrpcglink-apps-dsp"; +- label = "cdsp"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- compute-cb@1 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <1>; +- iommus = <&apps_smmu 0x1001 0x0460>; +- }; +- +- compute-cb@2 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <2>; +- iommus = <&apps_smmu 0x1002 0x0460>; +- }; +- +- compute-cb@3 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <3>; +- iommus = <&apps_smmu 0x1003 0x0460>; +- }; +- +- compute-cb@4 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <4>; +- iommus = <&apps_smmu 0x1004 0x0460>; +- }; +- +- compute-cb@5 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <5>; +- iommus = <&apps_smmu 0x1005 0x0460>; +- }; +- +- compute-cb@6 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <6>; +- iommus = <&apps_smmu 0x1006 0x0460>; +- }; +- +- compute-cb@7 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <7>; +- iommus = <&apps_smmu 0x1007 0x0460>; +- }; +- +- compute-cb@8 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <8>; +- iommus = <&apps_smmu 0x1008 0x0460>; +- }; +- +- /* note: secure cb9 in downstream */ +- }; +- }; +- }; +- +- sound: sound { +- }; +- +- usb_1_hsphy: phy@88e3000 { +- compatible = "qcom,sm8250-usb-hs-phy", +- "qcom,usb-snps-hs-7nm-phy"; +- reg = <0 0x088e3000 0 0x400>; +- status = "disabled"; +- #phy-cells = <0>; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "ref"; +- +- resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; +- }; +- +- usb_2_hsphy: phy@88e4000 { +- compatible = "qcom,sm8250-usb-hs-phy", +- "qcom,usb-snps-hs-7nm-phy"; +- reg = <0 0x088e4000 0 0x400>; +- status = "disabled"; +- #phy-cells = <0>; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "ref"; +- +- resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; +- }; +- +- usb_1_qmpphy: phy@88e9000 { +- compatible = "qcom,sm8250-qmp-usb3-dp-phy"; +- reg = <0 0x088e9000 0 0x200>, +- <0 0x088e8000 0 0x40>, +- <0 0x088ea000 0 0x200>; +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, +- <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; +- clock-names = "aux", "ref_clk_src", "com_aux"; +- +- resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, +- <&gcc GCC_USB3_PHY_PRIM_BCR>; +- reset-names = "phy", "common"; +- +- usb_1_ssphy: usb3-phy@88e9200 { +- reg = <0 0x088e9200 0 0x200>, +- <0 0x088e9400 0 0x200>, +- <0 0x088e9c00 0 0x400>, +- <0 0x088e9600 0 0x200>, +- <0 0x088e9800 0 0x200>, +- <0 0x088e9a00 0 0x100>; +- #clock-cells = <0>; +- #phy-cells = <0>; +- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; +- clock-names = "pipe0"; +- clock-output-names = "usb3_phy_pipe_clk_src"; +- }; +- +- dp_phy: dp-phy@88ea200 { +- reg = <0 0x088ea200 0 0x200>, +- <0 0x088ea400 0 0x200>, +- <0 0x088eac00 0 0x400>, +- <0 0x088ea600 0 0x200>, +- <0 0x088ea800 0 0x200>, +- <0 0x088eaa00 0 0x100>; +- #phy-cells = <0>; +- #clock-cells = <1>; +- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; +- clock-names = "pipe0"; +- clock-output-names = "usb3_phy_pipe_clk_src"; +- }; +- }; +- +- usb_2_qmpphy: phy@88eb000 { +- compatible = "qcom,sm8250-qmp-usb3-uni-phy"; +- reg = <0 0x088eb000 0 0x200>; +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, +- <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_USB3_SEC_CLKREF_EN>, +- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; +- clock-names = "aux", "ref_clk_src", "ref", "com_aux"; +- +- resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, +- <&gcc GCC_USB3_PHY_SEC_BCR>; +- reset-names = "phy", "common"; +- +- usb_2_ssphy: lanes@88eb200 { +- reg = <0 0x088eb200 0 0x200>, +- <0 0x088eb400 0 0x200>, +- <0 0x088eb800 0 0x800>; +- #clock-cells = <0>; +- #phy-cells = <0>; +- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; +- clock-names = "pipe0"; +- clock-output-names = "usb3_uni_phy_pipe_clk_src"; +- }; +- }; +- +- sdhc_2: sdhci@8804000 { +- compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; +- reg = <0 0x08804000 0 0x1000>; +- +- interrupts = , +- ; +- interrupt-names = "hc_irq", "pwr_irq"; +- +- clocks = <&gcc GCC_SDCC2_AHB_CLK>, +- <&gcc GCC_SDCC2_APPS_CLK>, +- <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "iface", "core", "xo"; +- iommus = <&apps_smmu 0x4a0 0x0>; +- qcom,dll-config = <0x0007642c>; +- qcom,ddr-config = <0x80040868>; +- power-domains = <&rpmhpd SM8250_CX>; +- operating-points-v2 = <&sdhc2_opp_table>; +- +- status = "disabled"; +- +- sdhc2_opp_table: sdhc2-opp-table { +- compatible = "operating-points-v2"; +- +- opp-19200000 { +- opp-hz = /bits/ 64 <19200000>; +- required-opps = <&rpmhpd_opp_min_svs>; +- }; +- +- opp-50000000 { +- opp-hz = /bits/ 64 <50000000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- }; +- +- opp-100000000 { +- opp-hz = /bits/ 64 <100000000>; +- required-opps = <&rpmhpd_opp_svs>; +- }; +- +- opp-202000000 { +- opp-hz = /bits/ 64 <202000000>; +- required-opps = <&rpmhpd_opp_svs_l1>; +- }; +- }; +- }; +- +- dc_noc: interconnect@90c0000 { +- compatible = "qcom,sm8250-dc-noc"; +- reg = <0 0x090c0000 0 0x4200>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- gem_noc: interconnect@9100000 { +- compatible = "qcom,sm8250-gem-noc"; +- reg = <0 0x09100000 0 0xb4000>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- npu_noc: interconnect@9990000 { +- compatible = "qcom,sm8250-npu-noc"; +- reg = <0 0x09990000 0 0x1600>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- usb_1: usb@a6f8800 { +- compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; +- reg = <0 0x0a6f8800 0 0x400>; +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- dma-ranges; +- +- clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, +- <&gcc GCC_USB30_PRIM_MASTER_CLK>, +- <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, +- <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_PRIM_SLEEP_CLK>, +- <&gcc GCC_USB3_SEC_CLKREF_EN>; +- clock-names = "cfg_noc", "core", "iface", "mock_utmi", +- "sleep", "xo"; +- +- assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_PRIM_MASTER_CLK>; +- assigned-clock-rates = <19200000>, <200000000>; +- +- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, +- <&pdc 14 IRQ_TYPE_EDGE_BOTH>, +- <&pdc 15 IRQ_TYPE_EDGE_BOTH>, +- <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", +- "dm_hs_phy_irq", "ss_phy_irq"; +- +- power-domains = <&gcc USB30_PRIM_GDSC>; +- +- resets = <&gcc GCC_USB30_PRIM_BCR>; +- +- usb_1_dwc3: usb@a600000 { +- compatible = "snps,dwc3"; +- reg = <0 0x0a600000 0 0xcd00>; +- interrupts = ; +- iommus = <&apps_smmu 0x0 0x0>; +- snps,dis_u2_susphy_quirk; +- snps,dis_enblslpm_quirk; +- phys = <&usb_1_hsphy>, <&usb_1_ssphy>; +- phy-names = "usb2-phy", "usb3-phy"; +- }; +- }; +- +- system-cache-controller@9200000 { +- compatible = "qcom,sm8250-llcc"; +- reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; +- reg-names = "llcc_base", "llcc_broadcast_base"; +- }; +- +- usb_2: usb@a8f8800 { +- compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; +- reg = <0 0x0a8f8800 0 0x400>; +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- dma-ranges; +- +- clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, +- <&gcc GCC_USB30_SEC_MASTER_CLK>, +- <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, +- <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_SEC_SLEEP_CLK>, +- <&gcc GCC_USB3_SEC_CLKREF_EN>; +- clock-names = "cfg_noc", "core", "iface", "mock_utmi", +- "sleep", "xo"; +- +- assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_SEC_MASTER_CLK>; +- assigned-clock-rates = <19200000>, <200000000>; +- +- interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, +- <&pdc 12 IRQ_TYPE_EDGE_BOTH>, +- <&pdc 13 IRQ_TYPE_EDGE_BOTH>, +- <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", +- "dm_hs_phy_irq", "ss_phy_irq"; +- +- power-domains = <&gcc USB30_SEC_GDSC>; +- +- resets = <&gcc GCC_USB30_SEC_BCR>; +- +- usb_2_dwc3: usb@a800000 { +- compatible = "snps,dwc3"; +- reg = <0 0x0a800000 0 0xcd00>; +- interrupts = ; +- iommus = <&apps_smmu 0x20 0>; +- snps,dis_u2_susphy_quirk; +- snps,dis_enblslpm_quirk; +- phys = <&usb_2_hsphy>, <&usb_2_ssphy>; +- phy-names = "usb2-phy", "usb3-phy"; +- }; +- }; +- +- venus: video-codec@aa00000 { +- compatible = "qcom,sm8250-venus"; +- reg = <0 0x0aa00000 0 0x100000>; +- interrupts = ; +- power-domains = <&videocc MVS0C_GDSC>, +- <&videocc MVS0_GDSC>, +- <&rpmhpd SM8250_MX>; +- power-domain-names = "venus", "vcodec0", "mx"; +- operating-points-v2 = <&venus_opp_table>; +- +- clocks = <&gcc GCC_VIDEO_AXI0_CLK>, +- <&videocc VIDEO_CC_MVS0C_CLK>, +- <&videocc VIDEO_CC_MVS0_CLK>; +- clock-names = "iface", "core", "vcodec0_core"; +- +- interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, +- <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; +- interconnect-names = "cpu-cfg", "video-mem"; +- +- iommus = <&apps_smmu 0x2100 0x0400>; +- memory-region = <&video_mem>; +- +- resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, +- <&videocc VIDEO_CC_MVS0C_CLK_ARES>; +- reset-names = "bus", "core"; +- +- status = "disabled"; +- +- video-decoder { +- compatible = "venus-decoder"; +- }; +- +- video-encoder { +- compatible = "venus-encoder"; +- }; +- +- venus_opp_table: venus-opp-table { +- compatible = "operating-points-v2"; +- +- opp-720000000 { +- opp-hz = /bits/ 64 <720000000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- }; +- +- opp-1014000000 { +- opp-hz = /bits/ 64 <1014000000>; +- required-opps = <&rpmhpd_opp_svs>; +- }; +- +- opp-1098000000 { +- opp-hz = /bits/ 64 <1098000000>; +- required-opps = <&rpmhpd_opp_svs_l1>; +- }; +- +- opp-1332000000 { +- opp-hz = /bits/ 64 <1332000000>; +- required-opps = <&rpmhpd_opp_nom>; +- }; +- }; +- }; +- +- videocc: clock-controller@abf0000 { +- compatible = "qcom,sm8250-videocc"; +- reg = <0 0x0abf0000 0 0x10000>; +- clocks = <&gcc GCC_VIDEO_AHB_CLK>, +- <&rpmhcc RPMH_CXO_CLK>, +- <&rpmhcc RPMH_CXO_CLK_A>; +- mmcx-supply = <&mmcx_reg>; +- clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- }; +- +- mdss: mdss@ae00000 { +- compatible = "qcom,sm8250-mdss"; +- reg = <0 0x0ae00000 0 0x1000>; +- reg-names = "mdss"; +- +- interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, +- <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; +- interconnect-names = "mdp0-mem", "mdp1-mem"; +- +- power-domains = <&dispcc MDSS_GDSC>; +- +- clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, +- <&gcc GCC_DISP_HF_AXI_CLK>, +- <&gcc GCC_DISP_SF_AXI_CLK>, +- <&dispcc DISP_CC_MDSS_MDP_CLK>; +- clock-names = "iface", "bus", "nrt_bus", "core"; +- +- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; +- assigned-clock-rates = <460000000>; +- +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- +- iommus = <&apps_smmu 0x820 0x402>; +- +- status = "disabled"; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- mdss_mdp: mdp@ae01000 { +- compatible = "qcom,sm8250-dpu"; +- reg = <0 0x0ae01000 0 0x8f000>, +- <0 0x0aeb0000 0 0x2008>; +- reg-names = "mdp", "vbif"; +- +- clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, +- <&gcc GCC_DISP_HF_AXI_CLK>, +- <&dispcc DISP_CC_MDSS_MDP_CLK>, +- <&dispcc DISP_CC_MDSS_VSYNC_CLK>; +- clock-names = "iface", "bus", "core", "vsync"; +- +- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, +- <&dispcc DISP_CC_MDSS_VSYNC_CLK>; +- assigned-clock-rates = <460000000>, +- <19200000>; +- +- operating-points-v2 = <&mdp_opp_table>; +- power-domains = <&rpmhpd SM8250_MMCX>; +- +- interrupt-parent = <&mdss>; +- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dpu_intf1_out: endpoint { +- remote-endpoint = <&dsi0_in>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- dpu_intf2_out: endpoint { +- remote-endpoint = <&dsi1_in>; +- }; +- }; +- }; +- +- mdp_opp_table: mdp-opp-table { +- compatible = "operating-points-v2"; +- +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- }; +- +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- required-opps = <&rpmhpd_opp_svs>; +- }; +- +- opp-345000000 { +- opp-hz = /bits/ 64 <345000000>; +- required-opps = <&rpmhpd_opp_svs_l1>; +- }; +- +- opp-460000000 { +- opp-hz = /bits/ 64 <460000000>; +- required-opps = <&rpmhpd_opp_nom>; +- }; +- }; +- }; +- +- dsi0: dsi@ae94000 { +- compatible = "qcom,mdss-dsi-ctrl"; +- reg = <0 0x0ae94000 0 0x400>; +- reg-names = "dsi_ctrl"; +- +- interrupt-parent = <&mdss>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +- +- clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, +- <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, +- <&dispcc DISP_CC_MDSS_PCLK0_CLK>, +- <&dispcc DISP_CC_MDSS_ESC0_CLK>, +- <&dispcc DISP_CC_MDSS_AHB_CLK>, +- <&gcc GCC_DISP_HF_AXI_CLK>; +- clock-names = "byte", +- "byte_intf", +- "pixel", +- "core", +- "iface", +- "bus"; +- +- assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; +- assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; +- +- operating-points-v2 = <&dsi_opp_table>; +- power-domains = <&rpmhpd SM8250_MMCX>; +- +- phys = <&dsi0_phy>; +- phy-names = "dsi"; +- +- status = "disabled"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dsi0_in: endpoint { +- remote-endpoint = <&dpu_intf1_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- dsi0_out: endpoint { +- }; +- }; +- }; +- }; +- +- dsi0_phy: dsi-phy@ae94400 { +- compatible = "qcom,dsi-phy-7nm"; +- reg = <0 0x0ae94400 0 0x200>, +- <0 0x0ae94600 0 0x280>, +- <0 0x0ae94900 0 0x260>; +- reg-names = "dsi_phy", +- "dsi_phy_lane", +- "dsi_pll"; +- +- #clock-cells = <1>; +- #phy-cells = <0>; +- +- clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, +- <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "iface", "ref"; +- +- status = "disabled"; +- }; +- +- dsi1: dsi@ae96000 { +- compatible = "qcom,mdss-dsi-ctrl"; +- reg = <0 0x0ae96000 0 0x400>; +- reg-names = "dsi_ctrl"; +- +- interrupt-parent = <&mdss>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; +- +- clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, +- <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, +- <&dispcc DISP_CC_MDSS_PCLK1_CLK>, +- <&dispcc DISP_CC_MDSS_ESC1_CLK>, +- <&dispcc DISP_CC_MDSS_AHB_CLK>, +- <&gcc GCC_DISP_HF_AXI_CLK>; +- clock-names = "byte", +- "byte_intf", +- "pixel", +- "core", +- "iface", +- "bus"; +- +- assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; +- assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; +- +- operating-points-v2 = <&dsi_opp_table>; +- power-domains = <&rpmhpd SM8250_MMCX>; +- +- phys = <&dsi1_phy>; +- phy-names = "dsi"; +- +- status = "disabled"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dsi1_in: endpoint { +- remote-endpoint = <&dpu_intf2_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- dsi1_out: endpoint { +- }; +- }; +- }; +- }; +- +- dsi1_phy: dsi-phy@ae96400 { +- compatible = "qcom,dsi-phy-7nm"; +- reg = <0 0x0ae96400 0 0x200>, +- <0 0x0ae96600 0 0x280>, +- <0 0x0ae96900 0 0x260>; +- reg-names = "dsi_phy", +- "dsi_phy_lane", +- "dsi_pll"; +- +- #clock-cells = <1>; +- #phy-cells = <0>; +- +- clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, +- <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "iface", "ref"; +- +- status = "disabled"; +- +- dsi_opp_table: dsi-opp-table { +- compatible = "operating-points-v2"; +- +- opp-187500000 { +- opp-hz = /bits/ 64 <187500000>; +- required-opps = <&rpmhpd_opp_low_svs>; +- }; +- +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- required-opps = <&rpmhpd_opp_svs>; +- }; +- +- opp-358000000 { +- opp-hz = /bits/ 64 <358000000>; +- required-opps = <&rpmhpd_opp_svs_l1>; +- }; +- }; +- }; +- }; +- +- dispcc: clock-controller@af00000 { +- compatible = "qcom,sm8250-dispcc"; +- reg = <0 0x0af00000 0 0x10000>; +- mmcx-supply = <&mmcx_reg>; +- clocks = <&rpmhcc RPMH_CXO_CLK>, +- <&dsi0_phy 0>, +- <&dsi0_phy 1>, +- <&dsi1_phy 0>, +- <&dsi1_phy 1>, +- <&dp_phy 0>, +- <&dp_phy 1>; +- clock-names = "bi_tcxo", +- "dsi0_phy_pll_out_byteclk", +- "dsi0_phy_pll_out_dsiclk", +- "dsi1_phy_pll_out_byteclk", +- "dsi1_phy_pll_out_dsiclk", +- "dp_phy_pll_link_clk", +- "dp_phy_pll_vco_div_clk"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- }; +- +- pdc: interrupt-controller@b220000 { +- compatible = "qcom,sm8250-pdc", "qcom,pdc"; +- reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; +- qcom,pdc-ranges = <0 480 94>, <94 609 31>, +- <125 63 1>, <126 716 12>; +- #interrupt-cells = <2>; +- interrupt-parent = <&intc>; +- interrupt-controller; +- }; +- +- tsens0: thermal-sensor@c263000 { +- compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; +- reg = <0 0x0c263000 0 0x1ff>, /* TM */ +- <0 0x0c222000 0 0x1ff>; /* SROT */ +- #qcom,sensors = <16>; +- interrupts = , +- ; +- interrupt-names = "uplow", "critical"; +- #thermal-sensor-cells = <1>; +- }; +- +- tsens1: thermal-sensor@c265000 { +- compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; +- reg = <0 0x0c265000 0 0x1ff>, /* TM */ +- <0 0x0c223000 0 0x1ff>; /* SROT */ +- #qcom,sensors = <9>; +- interrupts = , +- ; +- interrupt-names = "uplow", "critical"; +- #thermal-sensor-cells = <1>; +- }; +- +- aoss_qmp: power-controller@c300000 { +- compatible = "qcom,sm8250-aoss-qmp"; +- reg = <0 0x0c300000 0 0x100000>; +- interrupts-extended = <&ipcc IPCC_CLIENT_AOP +- IPCC_MPROC_SIGNAL_GLINK_QMP +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_AOP +- IPCC_MPROC_SIGNAL_GLINK_QMP>; +- +- #clock-cells = <0>; +- #power-domain-cells = <1>; +- }; +- +- spmi_bus: spmi@c440000 { +- compatible = "qcom,spmi-pmic-arb"; +- reg = <0x0 0x0c440000 0x0 0x0001100>, +- <0x0 0x0c600000 0x0 0x2000000>, +- <0x0 0x0e600000 0x0 0x0100000>, +- <0x0 0x0e700000 0x0 0x00a0000>, +- <0x0 0x0c40a000 0x0 0x0026000>; +- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; +- interrupt-names = "periph_irq"; +- interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; +- qcom,ee = <0>; +- qcom,channel = <0>; +- #address-cells = <2>; +- #size-cells = <0>; +- interrupt-controller; +- #interrupt-cells = <4>; +- }; +- +- tlmm: pinctrl@f100000 { +- compatible = "qcom,sm8250-pinctrl"; +- reg = <0 0x0f100000 0 0x300000>, +- <0 0x0f500000 0 0x300000>, +- <0 0x0f900000 0 0x300000>; +- reg-names = "west", "south", "north"; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&tlmm 0 0 181>; +- wakeup-parent = <&pdc>; +- +- pri_mi2s_active: pri-mi2s-active { +- sclk { +- pins = "gpio138"; +- function = "mi2s0_sck"; +- drive-strength = <8>; +- bias-disable; +- }; +- +- ws { +- pins = "gpio141"; +- function = "mi2s0_ws"; +- drive-strength = <8>; +- output-high; +- }; +- +- data0 { +- pins = "gpio139"; +- function = "mi2s0_data0"; +- drive-strength = <8>; +- bias-disable; +- output-high; +- }; +- +- data1 { +- pins = "gpio140"; +- function = "mi2s0_data1"; +- drive-strength = <8>; +- output-high; +- }; +- }; +- +- qup_i2c0_default: qup-i2c0-default { +- mux { +- pins = "gpio28", "gpio29"; +- function = "qup0"; +- }; +- +- config { +- pins = "gpio28", "gpio29"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_i2c1_default: qup-i2c1-default { +- pinmux { +- pins = "gpio4", "gpio5"; +- function = "qup1"; +- }; +- +- config { +- pins = "gpio4", "gpio5"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_i2c2_default: qup-i2c2-default { +- mux { +- pins = "gpio115", "gpio116"; +- function = "qup2"; +- }; +- +- config { +- pins = "gpio115", "gpio116"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_i2c3_default: qup-i2c3-default { +- mux { +- pins = "gpio119", "gpio120"; +- function = "qup3"; +- }; +- +- config { +- pins = "gpio119", "gpio120"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_i2c4_default: qup-i2c4-default { +- mux { +- pins = "gpio8", "gpio9"; +- function = "qup4"; +- }; +- +- config { +- pins = "gpio8", "gpio9"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_i2c5_default: qup-i2c5-default { +- mux { +- pins = "gpio12", "gpio13"; +- function = "qup5"; +- }; +- +- config { +- pins = "gpio12", "gpio13"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_i2c6_default: qup-i2c6-default { +- mux { +- pins = "gpio16", "gpio17"; +- function = "qup6"; +- }; +- +- config { +- pins = "gpio16", "gpio17"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_i2c7_default: qup-i2c7-default { +- mux { +- pins = "gpio20", "gpio21"; +- function = "qup7"; +- }; +- +- config { +- pins = "gpio20", "gpio21"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_i2c8_default: qup-i2c8-default { +- mux { +- pins = "gpio24", "gpio25"; +- function = "qup8"; +- }; +- +- config { +- pins = "gpio24", "gpio25"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_i2c9_default: qup-i2c9-default { +- mux { +- pins = "gpio125", "gpio126"; +- function = "qup9"; +- }; +- +- config { +- pins = "gpio125", "gpio126"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_i2c10_default: qup-i2c10-default { +- mux { +- pins = "gpio129", "gpio130"; +- function = "qup10"; +- }; +- +- config { +- pins = "gpio129", "gpio130"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_i2c11_default: qup-i2c11-default { +- mux { +- pins = "gpio60", "gpio61"; +- function = "qup11"; +- }; +- +- config { +- pins = "gpio60", "gpio61"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_i2c12_default: qup-i2c12-default { +- mux { +- pins = "gpio32", "gpio33"; +- function = "qup12"; +- }; +- +- config { +- pins = "gpio32", "gpio33"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_i2c13_default: qup-i2c13-default { +- mux { +- pins = "gpio36", "gpio37"; +- function = "qup13"; +- }; +- +- config { +- pins = "gpio36", "gpio37"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_i2c14_default: qup-i2c14-default { +- mux { +- pins = "gpio40", "gpio41"; +- function = "qup14"; +- }; +- +- config { +- pins = "gpio40", "gpio41"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_i2c15_default: qup-i2c15-default { +- mux { +- pins = "gpio44", "gpio45"; +- function = "qup15"; +- }; +- +- config { +- pins = "gpio44", "gpio45"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_i2c16_default: qup-i2c16-default { +- mux { +- pins = "gpio48", "gpio49"; +- function = "qup16"; +- }; +- +- config { +- pins = "gpio48", "gpio49"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_i2c17_default: qup-i2c17-default { +- mux { +- pins = "gpio52", "gpio53"; +- function = "qup17"; +- }; +- +- config { +- pins = "gpio52", "gpio53"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_i2c18_default: qup-i2c18-default { +- mux { +- pins = "gpio56", "gpio57"; +- function = "qup18"; +- }; +- +- config { +- pins = "gpio56", "gpio57"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_i2c19_default: qup-i2c19-default { +- mux { +- pins = "gpio0", "gpio1"; +- function = "qup19"; +- }; +- +- config { +- pins = "gpio0", "gpio1"; +- drive-strength = <2>; +- bias-disable; +- }; +- }; +- +- qup_spi0_cs: qup-spi0-cs { +- pins = "gpio31"; +- function = "qup0"; +- }; +- +- qup_spi0_cs_gpio: qup-spi0-cs-gpio { +- pins = "gpio31"; +- function = "gpio"; +- }; +- +- qup_spi0_data_clk: qup-spi0-data-clk { +- pins = "gpio28", "gpio29", +- "gpio30"; +- function = "qup0"; +- }; +- +- qup_spi1_cs: qup-spi1-cs { +- pins = "gpio7"; +- function = "qup1"; +- }; +- +- qup_spi1_cs_gpio: qup-spi1-cs-gpio { +- pins = "gpio7"; +- function = "gpio"; +- }; +- +- qup_spi1_data_clk: qup-spi1-data-clk { +- pins = "gpio4", "gpio5", +- "gpio6"; +- function = "qup1"; +- }; +- +- qup_spi2_cs: qup-spi2-cs { +- pins = "gpio118"; +- function = "qup2"; +- }; +- +- qup_spi2_cs_gpio: qup-spi2-cs-gpio { +- pins = "gpio118"; +- function = "gpio"; +- }; +- +- qup_spi2_data_clk: qup-spi2-data-clk { +- pins = "gpio115", "gpio116", +- "gpio117"; +- function = "qup2"; +- }; +- +- qup_spi3_cs: qup-spi3-cs { +- pins = "gpio122"; +- function = "qup3"; +- }; +- +- qup_spi3_cs_gpio: qup-spi3-cs-gpio { +- pins = "gpio122"; +- function = "gpio"; +- }; +- +- qup_spi3_data_clk: qup-spi3-data-clk { +- pins = "gpio119", "gpio120", +- "gpio121"; +- function = "qup3"; +- }; +- +- qup_spi4_cs: qup-spi4-cs { +- pins = "gpio11"; +- function = "qup4"; +- }; +- +- qup_spi4_cs_gpio: qup-spi4-cs-gpio { +- pins = "gpio11"; +- function = "gpio"; +- }; +- +- qup_spi4_data_clk: qup-spi4-data-clk { +- pins = "gpio8", "gpio9", +- "gpio10"; +- function = "qup4"; +- }; +- +- qup_spi5_cs: qup-spi5-cs { +- pins = "gpio15"; +- function = "qup5"; +- }; +- +- qup_spi5_cs_gpio: qup-spi5-cs-gpio { +- pins = "gpio15"; +- function = "gpio"; +- }; +- +- qup_spi5_data_clk: qup-spi5-data-clk { +- pins = "gpio12", "gpio13", +- "gpio14"; +- function = "qup5"; +- }; +- +- qup_spi6_cs: qup-spi6-cs { +- pins = "gpio19"; +- function = "qup6"; +- }; +- +- qup_spi6_cs_gpio: qup-spi6-cs-gpio { +- pins = "gpio19"; +- function = "gpio"; +- }; +- +- qup_spi6_data_clk: qup-spi6-data-clk { +- pins = "gpio16", "gpio17", +- "gpio18"; +- function = "qup6"; +- }; +- +- qup_spi7_cs: qup-spi7-cs { +- pins = "gpio23"; +- function = "qup7"; +- }; +- +- qup_spi7_cs_gpio: qup-spi7-cs-gpio { +- pins = "gpio23"; +- function = "gpio"; +- }; +- +- qup_spi7_data_clk: qup-spi7-data-clk { +- pins = "gpio20", "gpio21", +- "gpio22"; +- function = "qup7"; +- }; +- +- qup_spi8_cs: qup-spi8-cs { +- pins = "gpio27"; +- function = "qup8"; +- }; +- +- qup_spi8_cs_gpio: qup-spi8-cs-gpio { +- pins = "gpio27"; +- function = "gpio"; +- }; +- +- qup_spi8_data_clk: qup-spi8-data-clk { +- pins = "gpio24", "gpio25", +- "gpio26"; +- function = "qup8"; +- }; +- +- qup_spi9_cs: qup-spi9-cs { +- pins = "gpio128"; +- function = "qup9"; +- }; +- +- qup_spi9_cs_gpio: qup-spi9-cs-gpio { +- pins = "gpio128"; +- function = "gpio"; +- }; +- +- qup_spi9_data_clk: qup-spi9-data-clk { +- pins = "gpio125", "gpio126", +- "gpio127"; +- function = "qup9"; +- }; +- +- qup_spi10_cs: qup-spi10-cs { +- pins = "gpio132"; +- function = "qup10"; +- }; +- +- qup_spi10_cs_gpio: qup-spi10-cs-gpio { +- pins = "gpio132"; +- function = "gpio"; +- }; +- +- qup_spi10_data_clk: qup-spi10-data-clk { +- pins = "gpio129", "gpio130", +- "gpio131"; +- function = "qup10"; +- }; +- +- qup_spi11_cs: qup-spi11-cs { +- pins = "gpio63"; +- function = "qup11"; +- }; +- +- qup_spi11_cs_gpio: qup-spi11-cs-gpio { +- pins = "gpio63"; +- function = "gpio"; +- }; +- +- qup_spi11_data_clk: qup-spi11-data-clk { +- pins = "gpio60", "gpio61", +- "gpio62"; +- function = "qup11"; +- }; +- +- qup_spi12_cs: qup-spi12-cs { +- pins = "gpio35"; +- function = "qup12"; +- }; +- +- qup_spi12_cs_gpio: qup-spi12-cs-gpio { +- pins = "gpio35"; +- function = "gpio"; +- }; +- +- qup_spi12_data_clk: qup-spi12-data-clk { +- pins = "gpio32", "gpio33", +- "gpio34"; +- function = "qup12"; +- }; +- +- qup_spi13_cs: qup-spi13-cs { +- pins = "gpio39"; +- function = "qup13"; +- }; +- +- qup_spi13_cs_gpio: qup-spi13-cs-gpio { +- pins = "gpio39"; +- function = "gpio"; +- }; +- +- qup_spi13_data_clk: qup-spi13-data-clk { +- pins = "gpio36", "gpio37", +- "gpio38"; +- function = "qup13"; +- }; +- +- qup_spi14_cs: qup-spi14-cs { +- pins = "gpio43"; +- function = "qup14"; +- }; +- +- qup_spi14_cs_gpio: qup-spi14-cs-gpio { +- pins = "gpio43"; +- function = "gpio"; +- }; +- +- qup_spi14_data_clk: qup-spi14-data-clk { +- pins = "gpio40", "gpio41", +- "gpio42"; +- function = "qup14"; +- }; +- +- qup_spi15_cs: qup-spi15-cs { +- pins = "gpio47"; +- function = "qup15"; +- }; +- +- qup_spi15_cs_gpio: qup-spi15-cs-gpio { +- pins = "gpio47"; +- function = "gpio"; +- }; +- +- qup_spi15_data_clk: qup-spi15-data-clk { +- pins = "gpio44", "gpio45", +- "gpio46"; +- function = "qup15"; +- }; +- +- qup_spi16_cs: qup-spi16-cs { +- pins = "gpio51"; +- function = "qup16"; +- }; +- +- qup_spi16_cs_gpio: qup-spi16-cs-gpio { +- pins = "gpio51"; +- function = "gpio"; +- }; +- +- qup_spi16_data_clk: qup-spi16-data-clk { +- pins = "gpio48", "gpio49", +- "gpio50"; +- function = "qup16"; +- }; +- +- qup_spi17_cs: qup-spi17-cs { +- pins = "gpio55"; +- function = "qup17"; +- }; +- +- qup_spi17_cs_gpio: qup-spi17-cs-gpio { +- pins = "gpio55"; +- function = "gpio"; +- }; +- +- qup_spi17_data_clk: qup-spi17-data-clk { +- pins = "gpio52", "gpio53", +- "gpio54"; +- function = "qup17"; +- }; +- +- qup_spi18_cs: qup-spi18-cs { +- pins = "gpio59"; +- function = "qup18"; +- }; +- +- qup_spi18_cs_gpio: qup-spi18-cs-gpio { +- pins = "gpio59"; +- function = "gpio"; +- }; +- +- qup_spi18_data_clk: qup-spi18-data-clk { +- pins = "gpio56", "gpio57", +- "gpio58"; +- function = "qup18"; +- }; +- +- qup_spi19_cs: qup-spi19-cs { +- pins = "gpio3"; +- function = "qup19"; +- }; +- +- qup_spi19_cs_gpio: qup-spi19-cs-gpio { +- pins = "gpio3"; +- function = "gpio"; +- }; +- +- qup_spi19_data_clk: qup-spi19-data-clk { +- pins = "gpio0", "gpio1", +- "gpio2"; +- function = "qup19"; +- }; +- +- qup_uart2_default: qup-uart2-default { +- mux { +- pins = "gpio117", "gpio118"; +- function = "qup2"; +- }; +- }; +- +- qup_uart6_default: qup-uart6-default { +- mux { +- pins = "gpio16", "gpio17", +- "gpio18", "gpio19"; +- function = "qup6"; +- }; +- }; +- +- qup_uart12_default: qup-uart12-default { +- mux { +- pins = "gpio34", "gpio35"; +- function = "qup12"; +- }; +- }; +- +- qup_uart17_default: qup-uart17-default { +- mux { +- pins = "gpio52", "gpio53", +- "gpio54", "gpio55"; +- function = "qup17"; +- }; +- }; +- +- qup_uart18_default: qup-uart18-default { +- mux { +- pins = "gpio58", "gpio59"; +- function = "qup18"; +- }; +- }; +- +- tert_mi2s_active: tert-mi2s-active { +- sck { +- pins = "gpio133"; +- function = "mi2s2_sck"; +- drive-strength = <8>; +- bias-disable; +- }; +- +- data0 { +- pins = "gpio134"; +- function = "mi2s2_data0"; +- drive-strength = <8>; +- bias-disable; +- output-high; +- }; +- +- ws { +- pins = "gpio135"; +- function = "mi2s2_ws"; +- drive-strength = <8>; +- output-high; +- }; +- }; +- +- sdc2_sleep_state: sdc2-sleep { +- clk { +- pins = "sdc2_clk"; +- drive-strength = <2>; +- bias-disable; +- }; +- +- cmd { +- pins = "sdc2_cmd"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- data { +- pins = "sdc2_data"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- }; +- +- pcie0_default_state: pcie0-default { +- perst { +- pins = "gpio79"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- clkreq { +- pins = "gpio80"; +- function = "pci_e0"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- wake { +- pins = "gpio81"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- }; +- +- pcie1_default_state: pcie1-default { +- perst { +- pins = "gpio82"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- clkreq { +- pins = "gpio83"; +- function = "pci_e1"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- wake { +- pins = "gpio84"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- }; +- +- pcie2_default_state: pcie2-default { +- perst { +- pins = "gpio85"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-down; +- }; +- +- clkreq { +- pins = "gpio86"; +- function = "pci_e2"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- +- wake { +- pins = "gpio87"; +- function = "gpio"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- }; +- }; +- +- apps_smmu: iommu@15000000 { +- compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; +- reg = <0 0x15000000 0 0x100000>; +- #iommu-cells = <2>; +- #global-interrupts = <2>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- }; +- +- adsp: remoteproc@17300000 { +- compatible = "qcom,sm8250-adsp-pas"; +- reg = <0 0x17300000 0 0x100>; +- +- interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, +- <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack"; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "xo"; +- +- power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, +- <&rpmhpd SM8250_LCX>, +- <&rpmhpd SM8250_LMX>; +- power-domain-names = "load_state", "lcx", "lmx"; +- +- memory-region = <&adsp_mem>; +- +- qcom,smem-states = <&smp2p_adsp_out 0>; +- qcom,smem-state-names = "stop"; +- +- status = "disabled"; +- +- glink-edge { +- interrupts-extended = <&ipcc IPCC_CLIENT_LPASS +- IPCC_MPROC_SIGNAL_GLINK_QMP +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_LPASS +- IPCC_MPROC_SIGNAL_GLINK_QMP>; +- +- label = "lpass"; +- qcom,remote-pid = <2>; +- +- apr { +- compatible = "qcom,apr-v2"; +- qcom,glink-channels = "apr_audio_svc"; +- qcom,apr-domain = ; +- #address-cells = <1>; +- #size-cells = <0>; +- +- apr-service@3 { +- reg = ; +- compatible = "qcom,q6core"; +- qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; +- }; +- +- q6afe: apr-service@4 { +- compatible = "qcom,q6afe"; +- reg = ; +- qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; +- q6afedai: dais { +- compatible = "qcom,q6afe-dais"; +- #address-cells = <1>; +- #size-cells = <0>; +- #sound-dai-cells = <1>; +- }; +- +- q6afecc: cc { +- compatible = "qcom,q6afe-clocks"; +- #clock-cells = <2>; +- }; +- }; +- +- q6asm: apr-service@7 { +- compatible = "qcom,q6asm"; +- reg = ; +- qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; +- q6asmdai: dais { +- compatible = "qcom,q6asm-dais"; +- #address-cells = <1>; +- #size-cells = <0>; +- #sound-dai-cells = <1>; +- iommus = <&apps_smmu 0x1801 0x0>; +- }; +- }; +- +- q6adm: apr-service@8 { +- compatible = "qcom,q6adm"; +- reg = ; +- qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; +- q6routing: routing { +- compatible = "qcom,q6adm-routing"; +- #sound-dai-cells = <0>; +- }; +- }; +- }; +- +- fastrpc { +- compatible = "qcom,fastrpc"; +- qcom,glink-channels = "fastrpcglink-apps-dsp"; +- label = "adsp"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- compute-cb@3 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <3>; +- iommus = <&apps_smmu 0x1803 0x0>; +- }; +- +- compute-cb@4 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <4>; +- iommus = <&apps_smmu 0x1804 0x0>; +- }; +- +- compute-cb@5 { +- compatible = "qcom,fastrpc-compute-cb"; +- reg = <5>; +- iommus = <&apps_smmu 0x1805 0x0>; +- }; +- }; +- }; +- }; +- +- intc: interrupt-controller@17a00000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ +- <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ +- interrupts = ; +- }; +- +- watchdog@17c10000 { +- compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; +- reg = <0 0x17c10000 0 0x1000>; +- clocks = <&sleep_clk>; +- interrupts = ; +- }; +- +- timer@17c20000 { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- compatible = "arm,armv7-timer-mem"; +- reg = <0x0 0x17c20000 0x0 0x1000>; +- clock-frequency = <19200000>; +- +- frame@17c21000 { +- frame-number = <0>; +- interrupts = , +- ; +- reg = <0x0 0x17c21000 0x0 0x1000>, +- <0x0 0x17c22000 0x0 0x1000>; +- }; +- +- frame@17c23000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0x0 0x17c23000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c25000 { +- frame-number = <2>; +- interrupts = ; +- reg = <0x0 0x17c25000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c27000 { +- frame-number = <3>; +- interrupts = ; +- reg = <0x0 0x17c27000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c29000 { +- frame-number = <4>; +- interrupts = ; +- reg = <0x0 0x17c29000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c2b000 { +- frame-number = <5>; +- interrupts = ; +- reg = <0x0 0x17c2b000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c2d000 { +- frame-number = <6>; +- interrupts = ; +- reg = <0x0 0x17c2d000 0x0 0x1000>; +- status = "disabled"; +- }; +- }; +- +- apps_rsc: rsc@18200000 { +- label = "apps_rsc"; +- compatible = "qcom,rpmh-rsc"; +- reg = <0x0 0x18200000 0x0 0x10000>, +- <0x0 0x18210000 0x0 0x10000>, +- <0x0 0x18220000 0x0 0x10000>; +- reg-names = "drv-0", "drv-1", "drv-2"; +- interrupts = , +- , +- ; +- qcom,tcs-offset = <0xd00>; +- qcom,drv-id = <2>; +- qcom,tcs-config = , , +- , ; +- +- rpmhcc: clock-controller { +- compatible = "qcom,sm8250-rpmh-clk"; +- #clock-cells = <1>; +- clock-names = "xo"; +- clocks = <&xo_board>; +- }; +- +- rpmhpd: power-controller { +- compatible = "qcom,sm8250-rpmhpd"; +- #power-domain-cells = <1>; +- operating-points-v2 = <&rpmhpd_opp_table>; +- +- rpmhpd_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- rpmhpd_opp_ret: opp1 { +- opp-level = ; +- }; +- +- rpmhpd_opp_min_svs: opp2 { +- opp-level = ; +- }; +- +- rpmhpd_opp_low_svs: opp3 { +- opp-level = ; +- }; +- +- rpmhpd_opp_svs: opp4 { +- opp-level = ; +- }; +- +- rpmhpd_opp_svs_l1: opp5 { +- opp-level = ; +- }; +- +- rpmhpd_opp_nom: opp6 { +- opp-level = ; +- }; +- +- rpmhpd_opp_nom_l1: opp7 { +- opp-level = ; +- }; +- +- rpmhpd_opp_nom_l2: opp8 { +- opp-level = ; +- }; +- +- rpmhpd_opp_turbo: opp9 { +- opp-level = ; +- }; +- +- rpmhpd_opp_turbo_l1: opp10 { +- opp-level = ; +- }; +- }; +- }; +- +- apps_bcm_voter: bcm_voter { +- compatible = "qcom,bcm-voter"; +- }; +- }; +- +- epss_l3: interconnect@18590000 { +- compatible = "qcom,sm8250-epss-l3"; +- reg = <0 0x18590000 0 0x1000>; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; +- clock-names = "xo", "alternate"; +- +- #interconnect-cells = <1>; +- }; +- +- cpufreq_hw: cpufreq@18591000 { +- compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; +- reg = <0 0x18591000 0 0x1000>, +- <0 0x18592000 0 0x1000>, +- <0 0x18593000 0 0x1000>; +- reg-names = "freq-domain0", "freq-domain1", +- "freq-domain2"; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; +- clock-names = "xo", "alternate"; +- +- #freq-domain-cells = <1>; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- thermal-zones { +- cpu0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 1>; +- +- trips { +- cpu0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu0_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu0_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu0_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu0_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 2>; +- +- trips { +- cpu1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu1_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu1_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu1_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu1_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 3>; +- +- trips { +- cpu2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu2_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu2_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu2_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu2_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 4>; +- +- trips { +- cpu3_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu3_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu3_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu3_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu3_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu4-top-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 7>; +- +- trips { +- cpu4_top_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu4_top_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu4_top_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu4_top_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu4_top_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu5-top-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 8>; +- +- trips { +- cpu5_top_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu5_top_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu5_top_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu5_top_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu5_top_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu6-top-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 9>; +- +- trips { +- cpu6_top_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu6_top_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu6_top_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu6_top_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu6_top_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu7-top-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 10>; +- +- trips { +- cpu7_top_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu7_top_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu7_top_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu7_top_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu7_top_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu4-bottom-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 11>; +- +- trips { +- cpu4_bottom_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu4_bottom_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu4_bottom_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu4_bottom_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu4_bottom_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu5-bottom-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 12>; +- +- trips { +- cpu5_bottom_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu5_bottom_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu5_bottom_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu5_bottom_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu5_bottom_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu6-bottom-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 13>; +- +- trips { +- cpu6_bottom_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu6_bottom_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu6_bottom_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu6_bottom_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu6_bottom_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu7-bottom-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 14>; +- +- trips { +- cpu7_bottom_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu7_bottom_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu7_bottom_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu7_bottom_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu7_bottom_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- aoss0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 0>; +- +- trips { +- aoss0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- cluster0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 5>; +- +- trips { +- cluster0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- cluster0_crit: cluster0_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cluster1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 6>; +- +- trips { +- cluster1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- cluster1_crit: cluster1_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- gpu-thermal-top { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 15>; +- +- trips { +- gpu1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- aoss1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 0>; +- +- trips { +- aoss1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- wlan-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 1>; +- +- trips { +- wlan_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- video-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 2>; +- +- trips { +- video_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- mem-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 3>; +- +- trips { +- mem_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- q6-hvx-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 4>; +- +- trips { +- q6_hvx_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- camera-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 5>; +- +- trips { +- camera_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- compute-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 6>; +- +- trips { +- compute_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- npu-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 7>; +- +- trips { +- npu_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- gpu-thermal-bottom { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 8>; +- +- trips { +- gpu2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sm8350-hdk.dts b/scripts/dtc/include-prefixes/arm64/qcom/sm8350-hdk.dts +deleted file mode 100644 +index 56093e260ddf..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sm8350-hdk.dts ++++ /dev/null +@@ -1,319 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020-2021, Linaro Limited +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "sm8350.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. SM8350 HDK"; +- compatible = "qcom,sm8350-hdk", "qcom,sm8350"; +- +- aliases { +- serial0 = &uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&adsp { +- status = "okay"; +- firmware-name = "qcom/sm8350/adsp.mbn"; +-}; +- +-&apps_rsc { +- pm8350-rpmh-regulators { +- compatible = "qcom,pm8350-rpmh-regulators"; +- qcom,pmic-id = "b"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- vdd-s9-supply = <&vph_pwr>; +- vdd-s10-supply = <&vph_pwr>; +- vdd-s11-supply = <&vph_pwr>; +- vdd-s12-supply = <&vph_pwr>; +- +- vdd-l1-l4-supply = <&vreg_s11b_0p95>; +- vdd-l2-l7-supply = <&vreg_bob>; +- vdd-l3-l5-supply = <&vreg_bob>; +- vdd-l6-l9-l10-supply = <&vreg_s11b_0p95>; +- +- vreg_s10b_1p8: smps10 { +- regulator-name = "vreg_s10b_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_s11b_0p95: smps11 { +- regulator-name = "vreg_s11b_0p95"; +- regulator-min-microvolt = <952000>; +- regulator-max-microvolt = <952000>; +- regulator-initial-mode = ; +- }; +- +- vreg_s12b_1p25: smps12 { +- regulator-name = "vreg_s12b_1p25"; +- regulator-min-microvolt = <1256000>; +- regulator-max-microvolt = <1256000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l1b_0p88: ldo1 { +- regulator-name = "vreg_l1b_0p88"; +- regulator-min-microvolt = <912000>; +- regulator-max-microvolt = <920000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l2b_3p07: ldo2 { +- regulator-name = "vreg_l2b_3p07"; +- regulator-min-microvolt = <3072000>; +- regulator-max-microvolt = <3072000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3b_0p9: ldo3 { +- regulator-name = "vreg_l3b_0p9"; +- regulator-min-microvolt = <904000>; +- regulator-max-microvolt = <904000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5b_0p88: ldo5 { +- regulator-name = "vreg_l5b_0p88"; +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <888000>; +- regulator-initial-mode = ; +- regulator-allow-set-load; +- }; +- +- vreg_l6b_1p2: ldo6 { +- regulator-name = "vreg_l6b_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1208000>; +- regulator-initial-mode = ; +- regulator-allow-set-load; +- }; +- +- vreg_l7b_2p96: ldo7 { +- regulator-name = "vreg_l7b_2p96"; +- regulator-min-microvolt = <2504000>; +- regulator-max-microvolt = <2504000>; +- regulator-initial-mode = ; +- regulator-allow-set-load; +- }; +- +- vreg_l9b_1p2: ldo9 { +- regulator-name = "vreg_l9b_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- regulator-allow-set-load; +- }; +- }; +- +- pm8350c-rpmh-regulators { +- compatible = "qcom,pm8350c-rpmh-regulators"; +- qcom,pmic-id = "c"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- vdd-s9-supply = <&vph_pwr>; +- vdd-s10-supply = <&vph_pwr>; +- +- vdd-l1-l12-supply = <&vreg_s1c_1p86>; +- vdd-l2-l8-supply = <&vreg_s1c_1p86>; +- vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; +- vdd-l6-l9-l11-supply = <&vreg_bob>; +- vdd-l10-supply = <&vreg_s12b_1p25>; +- +- vdd-bob-supply = <&vph_pwr>; +- +- vreg_s1c_1p86: smps1 { +- regulator-name = "vreg_s1c_1p86"; +- regulator-min-microvolt = <1856000>; +- regulator-max-microvolt = <1880000>; +- regulator-initial-mode = ; +- }; +- +- vreg_bob: bob { +- regulator-name = "vreg_bob"; +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l1c_1p8: ldo1 { +- regulator-name = "vreg_l1c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l2c_1p8: ldo2 { +- regulator-name = "vreg_l2c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6c_1p8: ldo6 { +- regulator-name = "vreg_l6c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l9c_2p96: ldo9 { +- regulator-name = "vreg_l9c_2p96"; +- regulator-min-microvolt = <2960000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10c_1p2: ldo10 { +- regulator-name = "vreg_l10c_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- }; +-}; +- +-&cdsp { +- status = "okay"; +- firmware-name = "qcom/sm8350/cdsp.mbn"; +-}; +- +-&mpss { +- status = "okay"; +- firmware-name = "qcom/sm8350/modem.mbn"; +-}; +- +-&qupv3_id_0 { +- status = "okay"; +-}; +- +-&slpi { +- status = "okay"; +- firmware-name = "qcom/sm8350/slpi.mbn"; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <52 8>; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&ufs_mem_hc { +- status = "okay"; +- +- reset-gpios = <&tlmm 203 GPIO_ACTIVE_LOW>; +- +- vcc-supply = <&vreg_l7b_2p96>; +- vcc-max-microamp = <800000>; +- vccq-supply = <&vreg_l9b_1p2>; +- vccq-max-microamp = <900000>; +-}; +- +-&ufs_mem_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l5b_0p88>; +- vdda-max-microamp = <91600>; +- vdda-pll-supply = <&vreg_l6b_1p2>; +- vdda-pll-max-microamp = <19000>; +-}; +- +-&usb_1 { +- status = "okay"; +-}; +- +-&usb_1_dwc3 { +- /* TODO: Define USB-C connector properly */ +- dr_mode = "peripheral"; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- +- vdda-pll-supply = <&vreg_l5b_0p88>; +- vdda18-supply = <&vreg_l1c_1p8>; +- vdda33-supply = <&vreg_l2b_3p07>; +-}; +- +-&usb_1_qmpphy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l6b_1p2>; +- vdda-pll-supply = <&vreg_l1b_0p88>; +-}; +- +-&usb_2 { +- status = "okay"; +-}; +- +-&usb_2_dwc3 { +- dr_mode = "host"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_hub_enabled_state>; +-}; +- +-&usb_2_hsphy { +- status = "okay"; +- +- vdda-pll-supply = <&vreg_l5b_0p88>; +- vdda18-supply = <&vreg_l1c_1p8>; +- vdda33-supply = <&vreg_l2b_3p07>; +-}; +- +-&usb_2_qmpphy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l6b_1p2>; +- vdda-pll-supply = <&vreg_l5b_0p88>; +-}; +- +-/* PINCTRL - additions to nodes defined in sm8350.dtsi */ +- +-&tlmm { +- usb_hub_enabled_state: usb-hub-enabled-state { +- pins = "gpio42"; +- function = "gpio"; +- +- drive-strength = <2>; +- output-low; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sm8350-mtp.dts b/scripts/dtc/include-prefixes/arm64/qcom/sm8350-mtp.dts +deleted file mode 100644 +index bd95009c1875..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sm8350-mtp.dts ++++ /dev/null +@@ -1,372 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Linaro Limited +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "sm8350.dtsi" +-#include "pm8350.dtsi" +-#include "pm8350b.dtsi" +-#include "pm8350c.dtsi" +-#include "pmk8350.dtsi" +-#include "pmr735a.dtsi" +-#include "pmr735b.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. sm8350 MTP"; +- compatible = "qcom,sm8350-mtp", "qcom,sm8350"; +- +- aliases { +- serial0 = &uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- vph_pwr: vph-pwr-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vph_pwr"; +- regulator-min-microvolt = <3700000>; +- regulator-max-microvolt = <3700000>; +- +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&adsp { +- status = "okay"; +- firmware-name = "qcom/sm8350/adsp.mbn"; +-}; +- +-&apps_rsc { +- pm8350-rpmh-regulators { +- compatible = "qcom,pm8350-rpmh-regulators"; +- qcom,pmic-id = "b"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- vdd-s9-supply = <&vph_pwr>; +- vdd-s10-supply = <&vph_pwr>; +- vdd-s11-supply = <&vph_pwr>; +- vdd-s12-supply = <&vph_pwr>; +- +- vdd-l1-l4-supply = <&vreg_s11b_0p95>; +- vdd-l2-l7-supply = <&vreg_bob>; +- vdd-l3-l5-supply = <&vreg_bob>; +- vdd-l6-l9-l10-supply = <&vreg_s11b_0p95>; +- vdd-l8-supply = <&vreg_s2c_0p8>; +- +- vreg_s10b_1p8: smps10 { +- regulator-name = "vreg_s10b_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- vreg_s11b_0p95: smps11 { +- regulator-name = "vreg_s11b_0p95"; +- regulator-min-microvolt = <752000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- vreg_s12b_1p25: smps12 { +- regulator-name = "vreg_s12b_1p25"; +- regulator-min-microvolt = <1224000>; +- regulator-max-microvolt = <1360000>; +- }; +- +- vreg_l1b_0p88: ldo1 { +- regulator-name = "vreg_l1b_0p88"; +- regulator-min-microvolt = <912000>; +- regulator-max-microvolt = <920000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l2b_3p07: ldo2 { +- regulator-name = "vreg_l2b_3p07"; +- regulator-min-microvolt = <3072000>; +- regulator-max-microvolt = <3072000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3b_0p9: ldo3 { +- regulator-name = "vreg_l3b_0p9"; +- regulator-min-microvolt = <904000>; +- regulator-max-microvolt = <904000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5b_0p88: ldo5 { +- regulator-name = "vreg_l3b_0p9"; +- regulator-min-microvolt = <880000>; +- regulator-max-microvolt = <888000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6b_1p2: ldo6 { +- regulator-name = "vreg_l6b_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1208000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7b_2p96: ldo7 { +- regulator-name = "vreg_l7b_2p96"; +- regulator-min-microvolt = <2400000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l9b_1p2: ldo9 { +- regulator-name = "vreg_l9b_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- }; +- +- pm8350c-rpmh-regulators { +- compatible = "qcom,pm8350c-rpmh-regulators"; +- qcom,pmic-id = "c"; +- +- vdd-s1-supply = <&vph_pwr>; +- vdd-s2-supply = <&vph_pwr>; +- vdd-s3-supply = <&vph_pwr>; +- vdd-s4-supply = <&vph_pwr>; +- vdd-s5-supply = <&vph_pwr>; +- vdd-s6-supply = <&vph_pwr>; +- vdd-s7-supply = <&vph_pwr>; +- vdd-s8-supply = <&vph_pwr>; +- vdd-s9-supply = <&vph_pwr>; +- vdd-s10-supply = <&vph_pwr>; +- +- vdd-l1-l12-supply = <&vreg_s1c_1p86>; +- vdd-l2-l8-supply = <&vreg_s1c_1p86>; +- vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; +- vdd-l6-l9-l11-supply = <&vreg_bob>; +- vdd-l10-supply = <&vreg_s12b_1p25>; +- +- vdd-bob-supply = <&vph_pwr>; +- +- vreg_s1c_1p86: smps1 { +- regulator-name = "vreg_s1c_1p86"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1952000>; +- }; +- +- vreg_s2c_0p8: smps2 { +- regulator-name = "vreg_s2c_0p8"; +- regulator-min-microvolt = <640000>; +- regulator-max-microvolt = <1000000>; +- }; +- +- vreg_s10c_1p05: smps10 { +- regulator-name = "vreg_s10c_1p05"; +- regulator-min-microvolt = <1048000>; +- regulator-max-microvolt = <1128000>; +- }; +- +- vreg_bob: bob { +- regulator-name = "vreg_bob"; +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l1c_1p8: ldo1 { +- regulator-name = "vreg_l1c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l2c_1p8: ldo2 { +- regulator-name = "vreg_l2c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l3c_3p0: ldo3 { +- regulator-name = "vreg_l3c_3p0"; +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l4c_uim1: ldo4 { +- regulator-name = "vreg_l4c_uim1"; +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <3000000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l5c_uim2: ldo5 { +- regulator-name = "vreg_l5c_uim2"; +- regulator-min-microvolt = <1704000>; +- regulator-max-microvolt = <3000000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l6c_1p8: ldo6 { +- regulator-name = "vreg_l6c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2960000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l7c_3p0: ldo7 { +- regulator-name = "vreg_l7c_3p0"; +- regulator-min-microvolt = <3008000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l8c_1p8: ldo8 { +- regulator-name = "vreg_l8c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l9c_2p96: ldo9 { +- regulator-name = "vreg_l9c_2p96"; +- regulator-min-microvolt = <2960000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l10c_1p2: ldo10 { +- regulator-name = "vreg_l10c_1p2"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l11c_2p96: ldo11 { +- regulator-name = "vreg_l11c_2p96"; +- regulator-min-microvolt = <2400000>; +- regulator-max-microvolt = <3008000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l12c_1p8: ldo12 { +- regulator-name = "vreg_l12c_1p8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2000000>; +- regulator-initial-mode = ; +- }; +- +- vreg_l13c_3p0: ldo13 { +- regulator-name = "vreg_l13c_3p0"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-initial-mode = ; +- }; +- }; +-}; +- +-&cdsp { +- status = "okay"; +- firmware-name = "qcom/sm8350/cdsp.mbn"; +-}; +- +-&mpss { +- status = "okay"; +- firmware-name = "qcom/sm8350/modem.mbn"; +-}; +- +-&qupv3_id_0 { +- status = "okay"; +-}; +- +-&slpi { +- status = "okay"; +- firmware-name = "qcom/sm8350/slpi.mbn"; +-}; +- +-&tlmm { +- gpio-reserved-ranges = <52 8>; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&ufs_mem_hc { +- status = "okay"; +- +- reset-gpios = <&tlmm 203 GPIO_ACTIVE_LOW>; +- +- vcc-supply = <&vreg_l7b_2p96>; +- vcc-max-microamp = <800000>; +- vccq-supply = <&vreg_l9b_1p2>; +- vccq-max-microamp = <900000>; +-}; +- +-&ufs_mem_phy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l5b_0p88>; +- vdda-max-microamp = <91600>; +- vdda-pll-supply = <&vreg_l6b_1p2>; +- vdda-pll-max-microamp = <19000>; +-}; +- +-&usb_1 { +- status = "okay"; +-}; +- +-&usb_1_dwc3 { +- dr_mode = "peripheral"; +-}; +- +-&usb_1_hsphy { +- status = "okay"; +- +- vdda-pll-supply = <&vreg_l5b_0p88>; +- vdda18-supply = <&vreg_l1c_1p8>; +- vdda33-supply = <&vreg_l2b_3p07>; +-}; +- +-&usb_1_qmpphy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l6b_1p2>; +- vdda-pll-supply = <&vreg_l1b_0p88>; +-}; +- +-&usb_2 { +- status = "okay"; +-}; +- +-&usb_2_hsphy { +- status = "okay"; +- +- vdda-pll-supply = <&vreg_l5b_0p88>; +- vdda18-supply = <&vreg_l1c_1p8>; +- vdda33-supply = <&vreg_l2b_3p07>; +-}; +- +-&usb_2_qmpphy { +- status = "okay"; +- +- vdda-phy-supply = <&vreg_l6b_1p2>; +- vdda-pll-supply = <&vreg_l5b_0p88>; +-}; +- +-&ipa { +- status = "okay"; +- +- memory-region = <&pil_ipa_fw_mem>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/qcom/sm8350.dtsi b/scripts/dtc/include-prefixes/arm64/qcom/sm8350.dtsi +deleted file mode 100644 +index a8886adaaf37..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/qcom/sm8350.dtsi ++++ /dev/null +@@ -1,2251 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* +- * Copyright (c) 2020, Linaro Limited +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- interrupt-parent = <&intc>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- chosen { }; +- +- clocks { +- xo_board: xo-board { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <38400000>; +- clock-output-names = "xo_board"; +- }; +- +- sleep_clk: sleep-clk { +- compatible = "fixed-clock"; +- clock-frequency = <32000>; +- #clock-cells = <0>; +- }; +- +- ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 { +- compatible = "fixed-clock"; +- clock-frequency = <1000>; +- #clock-cells = <0>; +- }; +- +- ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 { +- compatible = "fixed-clock"; +- clock-frequency = <1000>; +- #clock-cells = <0>; +- }; +- +- ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 { +- compatible = "fixed-clock"; +- clock-frequency = <1000>; +- #clock-cells = <0>; +- }; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- CPU0: cpu@0 { +- device_type = "cpu"; +- compatible = "qcom,kryo685"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- next-level-cache = <&L2_0>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- #cooling-cells = <2>; +- L2_0: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- L3_0: l3-cache { +- compatible = "cache"; +- }; +- }; +- }; +- +- CPU1: cpu@100 { +- device_type = "cpu"; +- compatible = "qcom,kryo685"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- next-level-cache = <&L2_100>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- #cooling-cells = <2>; +- L2_100: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU2: cpu@200 { +- device_type = "cpu"; +- compatible = "qcom,kryo685"; +- reg = <0x0 0x200>; +- enable-method = "psci"; +- next-level-cache = <&L2_200>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- #cooling-cells = <2>; +- L2_200: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU3: cpu@300 { +- device_type = "cpu"; +- compatible = "qcom,kryo685"; +- reg = <0x0 0x300>; +- enable-method = "psci"; +- next-level-cache = <&L2_300>; +- qcom,freq-domain = <&cpufreq_hw 0>; +- #cooling-cells = <2>; +- L2_300: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU4: cpu@400 { +- device_type = "cpu"; +- compatible = "qcom,kryo685"; +- reg = <0x0 0x400>; +- enable-method = "psci"; +- next-level-cache = <&L2_400>; +- qcom,freq-domain = <&cpufreq_hw 1>; +- #cooling-cells = <2>; +- L2_400: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU5: cpu@500 { +- device_type = "cpu"; +- compatible = "qcom,kryo685"; +- reg = <0x0 0x500>; +- enable-method = "psci"; +- next-level-cache = <&L2_500>; +- qcom,freq-domain = <&cpufreq_hw 1>; +- #cooling-cells = <2>; +- L2_500: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- +- }; +- +- CPU6: cpu@600 { +- device_type = "cpu"; +- compatible = "qcom,kryo685"; +- reg = <0x0 0x600>; +- enable-method = "psci"; +- next-level-cache = <&L2_600>; +- qcom,freq-domain = <&cpufreq_hw 1>; +- #cooling-cells = <2>; +- L2_600: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- +- CPU7: cpu@700 { +- device_type = "cpu"; +- compatible = "qcom,kryo685"; +- reg = <0x0 0x700>; +- enable-method = "psci"; +- next-level-cache = <&L2_700>; +- qcom,freq-domain = <&cpufreq_hw 2>; +- #cooling-cells = <2>; +- L2_700: l2-cache { +- compatible = "cache"; +- next-level-cache = <&L3_0>; +- }; +- }; +- }; +- +- firmware { +- scm: scm { +- compatible = "qcom,scm-sm8350", "qcom,scm"; +- #reset-cells = <1>; +- }; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- /* We expect the bootloader to fill in the size */ +- reg = <0x0 0x80000000 0x0 0x0>; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- reserved_memory: reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- hyp_mem: memory@80000000 { +- reg = <0x0 0x80000000 0x0 0x600000>; +- no-map; +- }; +- +- xbl_aop_mem: memory@80700000 { +- no-map; +- reg = <0x0 0x80700000 0x0 0x160000>; +- }; +- +- cmd_db: memory@80860000 { +- compatible = "qcom,cmd-db"; +- reg = <0x0 0x80860000 0x0 0x20000>; +- no-map; +- }; +- +- reserved_xbl_uefi_log: memory@80880000 { +- reg = <0x0 0x80880000 0x0 0x14000>; +- no-map; +- }; +- +- smem_mem: memory@80900000 { +- reg = <0x0 0x80900000 0x0 0x200000>; +- no-map; +- }; +- +- cpucp_fw_mem: memory@80b00000 { +- reg = <0x0 0x80b00000 0x0 0x100000>; +- no-map; +- }; +- +- cdsp_secure_heap: memory@80c00000 { +- reg = <0x0 0x80c00000 0x0 0x4600000>; +- no-map; +- }; +- +- pil_camera_mem: mmeory@85200000 { +- reg = <0x0 0x85200000 0x0 0x500000>; +- no-map; +- }; +- +- pil_video_mem: memory@85700000 { +- reg = <0x0 0x85700000 0x0 0x500000>; +- no-map; +- }; +- +- pil_cvp_mem: memory@85c00000 { +- reg = <0x0 0x85c00000 0x0 0x500000>; +- no-map; +- }; +- +- pil_adsp_mem: memory@86100000 { +- reg = <0x0 0x86100000 0x0 0x2100000>; +- no-map; +- }; +- +- pil_slpi_mem: memory@88200000 { +- reg = <0x0 0x88200000 0x0 0x1500000>; +- no-map; +- }; +- +- pil_cdsp_mem: memory@89700000 { +- reg = <0x0 0x89700000 0x0 0x1e00000>; +- no-map; +- }; +- +- pil_ipa_fw_mem: memory@8b500000 { +- reg = <0x0 0x8b500000 0x0 0x10000>; +- no-map; +- }; +- +- pil_ipa_gsi_mem: memory@8b510000 { +- reg = <0x0 0x8b510000 0x0 0xa000>; +- no-map; +- }; +- +- pil_gpu_mem: memory@8b51a000 { +- reg = <0x0 0x8b51a000 0x0 0x2000>; +- no-map; +- }; +- +- pil_spss_mem: memory@8b600000 { +- reg = <0x0 0x8b600000 0x0 0x100000>; +- no-map; +- }; +- +- pil_modem_mem: memory@8b800000 { +- reg = <0x0 0x8b800000 0x0 0x10000000>; +- no-map; +- }; +- +- rmtfs_mem: memory@9b800000 { +- compatible = "qcom,rmtfs-mem"; +- reg = <0x0 0x9b800000 0x0 0x280000>; +- no-map; +- +- qcom,client-id = <1>; +- qcom,vmid = <15>; +- }; +- +- hyp_reserved_mem: memory@d0000000 { +- reg = <0x0 0xd0000000 0x0 0x800000>; +- no-map; +- }; +- +- pil_trustedvm_mem: memory@d0800000 { +- reg = <0x0 0xd0800000 0x0 0x76f7000>; +- no-map; +- }; +- +- qrtr_shbuf: memory@d7ef7000 { +- reg = <0x0 0xd7ef7000 0x0 0x9000>; +- no-map; +- }; +- +- chan0_shbuf: memory@d7f00000 { +- reg = <0x0 0xd7f00000 0x0 0x80000>; +- no-map; +- }; +- +- chan1_shbuf: memory@d7f80000 { +- reg = <0x0 0xd7f80000 0x0 0x80000>; +- no-map; +- }; +- +- removed_mem: memory@d8800000 { +- reg = <0x0 0xd8800000 0x0 0x6800000>; +- no-map; +- }; +- }; +- +- smem: qcom,smem { +- compatible = "qcom,smem"; +- memory-region = <&smem_mem>; +- hwlocks = <&tcsr_mutex 3>; +- }; +- +- smp2p-adsp { +- compatible = "qcom,smp2p"; +- qcom,smem = <443>, <429>; +- interrupts-extended = <&ipcc IPCC_CLIENT_LPASS +- IPCC_MPROC_SIGNAL_SMP2P +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_LPASS +- IPCC_MPROC_SIGNAL_SMP2P>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <2>; +- +- smp2p_adsp_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- smp2p_adsp_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-cdsp { +- compatible = "qcom,smp2p"; +- qcom,smem = <94>, <432>; +- interrupts-extended = <&ipcc IPCC_CLIENT_CDSP +- IPCC_MPROC_SIGNAL_SMP2P +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_CDSP +- IPCC_MPROC_SIGNAL_SMP2P>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <5>; +- +- smp2p_cdsp_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- smp2p_cdsp_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-modem { +- compatible = "qcom,smp2p"; +- qcom,smem = <435>, <428>; +- interrupts-extended = <&ipcc IPCC_CLIENT_MPSS +- IPCC_MPROC_SIGNAL_SMP2P +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_MPSS +- IPCC_MPROC_SIGNAL_SMP2P>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <1>; +- +- smp2p_modem_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- smp2p_modem_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- ipa_smp2p_out: ipa-ap-to-modem { +- qcom,entry-name = "ipa"; +- #qcom,smem-state-cells = <1>; +- }; +- +- ipa_smp2p_in: ipa-modem-to-ap { +- qcom,entry-name = "ipa"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- smp2p-slpi { +- compatible = "qcom,smp2p"; +- qcom,smem = <481>, <430>; +- interrupts-extended = <&ipcc IPCC_CLIENT_SLPI +- IPCC_MPROC_SIGNAL_SMP2P +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_SLPI +- IPCC_MPROC_SIGNAL_SMP2P>; +- +- qcom,local-pid = <0>; +- qcom,remote-pid = <3>; +- +- smp2p_slpi_out: master-kernel { +- qcom,entry-name = "master-kernel"; +- #qcom,smem-state-cells = <1>; +- }; +- +- smp2p_slpi_in: slave-kernel { +- qcom,entry-name = "slave-kernel"; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +- +- soc: soc@0 { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0 0 0 0 0x10 0>; +- dma-ranges = <0 0 0 0 0x10 0>; +- compatible = "simple-bus"; +- +- gcc: clock-controller@100000 { +- compatible = "qcom,gcc-sm8350"; +- reg = <0x0 0x00100000 0x0 0x1f0000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- #power-domain-cells = <1>; +- clock-names = "bi_tcxo", +- "sleep_clk", +- "pcie_0_pipe_clk", +- "pcie_1_pipe_clk", +- "ufs_card_rx_symbol_0_clk", +- "ufs_card_rx_symbol_1_clk", +- "ufs_card_tx_symbol_0_clk", +- "ufs_phy_rx_symbol_0_clk", +- "ufs_phy_rx_symbol_1_clk", +- "ufs_phy_tx_symbol_0_clk", +- "usb3_phy_wrapper_gcc_usb30_pipe_clk", +- "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; +- clocks = <&rpmhcc RPMH_CXO_CLK>, +- <&sleep_clk>, +- <0>, +- <0>, +- <0>, +- <0>, +- <0>, +- <&ufs_phy_rx_symbol_0_clk>, +- <&ufs_phy_rx_symbol_1_clk>, +- <&ufs_phy_tx_symbol_0_clk>, +- <0>, +- <0>; +- }; +- +- ipcc: mailbox@408000 { +- compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; +- reg = <0 0x00408000 0 0x1000>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- #mbox-cells = <2>; +- }; +- +- qupv3_id_0: geniqup@9c0000 { +- compatible = "qcom,geni-se-qup"; +- reg = <0x0 0x009c0000 0x0 0x6000>; +- clock-names = "m-ahb", "s-ahb"; +- clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, +- <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "disabled"; +- +- uart2: serial@98c000 { +- compatible = "qcom,geni-debug-uart"; +- reg = <0 0x0098c000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_uart3_default_state>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- qupv3_id_1: geniqup@ac0000 { +- compatible = "qcom,geni-se-qup"; +- reg = <0x0 0x00ac0000 0x0 0x6000>; +- clock-names = "m-ahb", "s-ahb"; +- clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, +- <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "disabled"; +- +- i2c13: i2c@a94000 { +- compatible = "qcom,geni-i2c"; +- reg = <0 0x00a94000 0 0x4000>; +- clock-names = "se"; +- clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; +- pinctrl-names = "default"; +- pinctrl-0 = <&qup_i2c13_default_state>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- apps_smmu: iommu@15000000 { +- compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; +- reg = <0 0x15000000 0 0x100000>; +- #iommu-cells = <2>; +- #global-interrupts = <2>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- }; +- +- config_noc: interconnect@1500000 { +- compatible = "qcom,sm8350-config-noc"; +- reg = <0 0x01500000 0 0xa580>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- mc_virt: interconnect@1580000 { +- compatible = "qcom,sm8350-mc-virt"; +- reg = <0 0x01580000 0 0x1000>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- system_noc: interconnect@1680000 { +- compatible = "qcom,sm8350-system-noc"; +- reg = <0 0x01680000 0 0x1c200>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- aggre1_noc: interconnect@16e0000 { +- compatible = "qcom,sm8350-aggre1-noc"; +- reg = <0 0x016e0000 0 0x1f180>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- aggre2_noc: interconnect@1700000 { +- compatible = "qcom,sm8350-aggre2-noc"; +- reg = <0 0x01700000 0 0x33000>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- mmss_noc: interconnect@1740000 { +- compatible = "qcom,sm8350-mmss-noc"; +- reg = <0 0x01740000 0 0x1f080>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- lpass_ag_noc: interconnect@3c40000 { +- compatible = "qcom,sm8350-lpass-ag-noc"; +- reg = <0 0x03c40000 0 0xf080>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- compute_noc: interconnect@a0c0000{ +- compatible = "qcom,sm8350-compute-noc"; +- reg = <0 0x0a0c0000 0 0xa180>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- ipa: ipa@1e40000 { +- compatible = "qcom,sm8350-ipa"; +- +- iommus = <&apps_smmu 0x5c0 0x0>, +- <&apps_smmu 0x5c2 0x0>; +- reg = <0 0x1e40000 0 0x8000>, +- <0 0x1e50000 0 0x4b20>, +- <0 0x1e04000 0 0x23000>; +- reg-names = "ipa-reg", +- "ipa-shared", +- "gsi"; +- +- interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, +- <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, +- <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, +- <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "ipa", +- "gsi", +- "ipa-clock-query", +- "ipa-setup-ready"; +- +- clocks = <&rpmhcc RPMH_IPA_CLK>; +- clock-names = "core"; +- +- interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, +- <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; +- interconnect-names = "memory", +- "config"; +- +- qcom,smem-states = <&ipa_smp2p_out 0>, +- <&ipa_smp2p_out 1>; +- qcom,smem-state-names = "ipa-clock-enabled-valid", +- "ipa-clock-enabled"; +- +- status = "disabled"; +- }; +- +- tcsr_mutex: hwlock@1f40000 { +- compatible = "qcom,tcsr-mutex"; +- reg = <0x0 0x01f40000 0x0 0x40000>; +- #hwlock-cells = <1>; +- }; +- +- mpss: remoteproc@4080000 { +- compatible = "qcom,sm8350-mpss-pas"; +- reg = <0x0 0x04080000 0x0 0x4040>; +- +- interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, +- <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", "handover", +- "stop-ack", "shutdown-ack"; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "xo"; +- +- power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, +- <&rpmhpd 0>, +- <&rpmhpd 12>; +- power-domain-names = "load_state", "cx", "mss"; +- +- interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; +- +- memory-region = <&pil_modem_mem>; +- +- qcom,smem-states = <&smp2p_modem_out 0>; +- qcom,smem-state-names = "stop"; +- +- status = "disabled"; +- +- glink-edge { +- interrupts-extended = <&ipcc IPCC_CLIENT_MPSS +- IPCC_MPROC_SIGNAL_GLINK_QMP +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_MPSS +- IPCC_MPROC_SIGNAL_GLINK_QMP>; +- interrupts = ; +- label = "modem"; +- qcom,remote-pid = <1>; +- }; +- }; +- +- pdc: interrupt-controller@b220000 { +- compatible = "qcom,sm8350-pdc", "qcom,pdc"; +- reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; +- qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, +- <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, +- <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, +- <156 716 12>; +- #interrupt-cells = <2>; +- interrupt-parent = <&intc>; +- interrupt-controller; +- }; +- +- tsens0: thermal-sensor@c263000 { +- compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; +- reg = <0 0x0c263000 0 0x1ff>, /* TM */ +- <0 0x0c222000 0 0x8>; /* SROT */ +- #qcom,sensors = <15>; +- interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, +- <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "uplow", "critical"; +- #thermal-sensor-cells = <1>; +- }; +- +- tsens1: thermal-sensor@c265000 { +- compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; +- reg = <0 0x0c265000 0 0x1ff>, /* TM */ +- <0 0x0c223000 0 0x8>; /* SROT */ +- #qcom,sensors = <14>; +- interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, +- <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "uplow", "critical"; +- #thermal-sensor-cells = <1>; +- }; +- +- aoss_qmp: power-controller@c300000 { +- compatible = "qcom,sm8350-aoss-qmp"; +- reg = <0 0x0c300000 0 0x100000>; +- interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; +- +- #clock-cells = <0>; +- #power-domain-cells = <1>; +- }; +- +- spmi_bus: spmi@c440000 { +- compatible = "qcom,spmi-pmic-arb"; +- reg = <0x0 0xc440000 0x0 0x1100>, +- <0x0 0xc600000 0x0 0x2000000>, +- <0x0 0xe600000 0x0 0x100000>, +- <0x0 0xe700000 0x0 0xa0000>, +- <0x0 0xc40a000 0x0 0x26000>; +- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; +- interrupt-names = "periph_irq"; +- interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; +- qcom,ee = <0>; +- qcom,channel = <0>; +- #address-cells = <2>; +- #size-cells = <0>; +- interrupt-controller; +- #interrupt-cells = <4>; +- }; +- +- tlmm: pinctrl@f100000 { +- compatible = "qcom,sm8350-tlmm"; +- reg = <0 0x0f100000 0 0x300000>; +- interrupts = ; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&tlmm 0 0 204>; +- wakeup-parent = <&pdc>; +- +- qup_uart3_default_state: qup-uart3-default-state { +- rx { +- pins = "gpio18"; +- function = "qup3"; +- }; +- tx { +- pins = "gpio19"; +- function = "qup3"; +- }; +- }; +- +- qup_i2c13_default_state: qup-i2c13-default-state { +- mux { +- pins = "gpio0", "gpio1"; +- function = "qup13"; +- }; +- +- config { +- pins = "gpio0", "gpio1"; +- drive-strength = <2>; +- bias-pull-up; +- }; +- }; +- }; +- +- rng: rng@10d3000 { +- compatible = "qcom,prng-ee"; +- reg = <0 0x010d3000 0 0x1000>; +- clocks = <&rpmhcc RPMH_HWKM_CLK>; +- clock-names = "core"; +- }; +- +- intc: interrupt-controller@17a00000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ +- <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ +- interrupts = ; +- }; +- +- timer@17c20000 { +- compatible = "arm,armv7-timer-mem"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- reg = <0x0 0x17c20000 0x0 0x1000>; +- clock-frequency = <19200000>; +- +- frame@17c21000 { +- frame-number = <0>; +- interrupts = , +- ; +- reg = <0x0 0x17c21000 0x0 0x1000>, +- <0x0 0x17c22000 0x0 0x1000>; +- }; +- +- frame@17c23000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0x0 0x17c23000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c25000 { +- frame-number = <2>; +- interrupts = ; +- reg = <0x0 0x17c25000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c27000 { +- frame-number = <3>; +- interrupts = ; +- reg = <0x0 0x17c27000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c29000 { +- frame-number = <4>; +- interrupts = ; +- reg = <0x0 0x17c29000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c2b000 { +- frame-number = <5>; +- interrupts = ; +- reg = <0x0 0x17c2b000 0x0 0x1000>; +- status = "disabled"; +- }; +- +- frame@17c2d000 { +- frame-number = <6>; +- interrupts = ; +- reg = <0x0 0x17c2d000 0x0 0x1000>; +- status = "disabled"; +- }; +- }; +- +- apps_rsc: rsc@18200000 { +- label = "apps_rsc"; +- compatible = "qcom,rpmh-rsc"; +- reg = <0x0 0x18200000 0x0 0x10000>, +- <0x0 0x18210000 0x0 0x10000>, +- <0x0 0x18220000 0x0 0x10000>; +- reg-names = "drv-0", "drv-1", "drv-2"; +- interrupts = , +- , +- ; +- qcom,tcs-offset = <0xd00>; +- qcom,drv-id = <2>; +- qcom,tcs-config = , , +- , ; +- +- rpmhcc: clock-controller { +- compatible = "qcom,sm8350-rpmh-clk"; +- #clock-cells = <1>; +- clock-names = "xo"; +- clocks = <&xo_board>; +- }; +- +- rpmhpd: power-controller { +- compatible = "qcom,sm8350-rpmhpd"; +- #power-domain-cells = <1>; +- operating-points-v2 = <&rpmhpd_opp_table>; +- +- rpmhpd_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- rpmhpd_opp_ret: opp1 { +- opp-level = ; +- }; +- +- rpmhpd_opp_min_svs: opp2 { +- opp-level = ; +- }; +- +- rpmhpd_opp_low_svs: opp3 { +- opp-level = ; +- }; +- +- rpmhpd_opp_svs: opp4 { +- opp-level = ; +- }; +- +- rpmhpd_opp_svs_l1: opp5 { +- opp-level = ; +- }; +- +- rpmhpd_opp_nom: opp6 { +- opp-level = ; +- }; +- +- rpmhpd_opp_nom_l1: opp7 { +- opp-level = ; +- }; +- +- rpmhpd_opp_nom_l2: opp8 { +- opp-level = ; +- }; +- +- rpmhpd_opp_turbo: opp9 { +- opp-level = ; +- }; +- +- rpmhpd_opp_turbo_l1: opp10 { +- opp-level = ; +- }; +- }; +- }; +- +- apps_bcm_voter: bcm_voter { +- compatible = "qcom,bcm-voter"; +- }; +- }; +- +- cpufreq_hw: cpufreq@18591000 { +- compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; +- reg = <0 0x18591000 0 0x1000>, +- <0 0x18592000 0 0x1000>, +- <0 0x18593000 0 0x1000>; +- reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; +- clock-names = "xo", "alternate"; +- +- #freq-domain-cells = <1>; +- }; +- +- ufs_mem_hc: ufshc@1d84000 { +- compatible = "qcom,sm8350-ufshc", "qcom,ufshc", +- "jedec,ufs-2.0"; +- reg = <0 0x01d84000 0 0x3000>; +- interrupts = ; +- phys = <&ufs_mem_phy_lanes>; +- phy-names = "ufsphy"; +- lanes-per-direction = <2>; +- #reset-cells = <1>; +- resets = <&gcc GCC_UFS_PHY_BCR>; +- reset-names = "rst"; +- +- power-domains = <&gcc UFS_PHY_GDSC>; +- +- iommus = <&apps_smmu 0xe0 0x0>; +- +- clock-names = +- "ref_clk", +- "core_clk", +- "bus_aggr_clk", +- "iface_clk", +- "core_clk_unipro", +- "ref_clk", +- "tx_lane0_sync_clk", +- "rx_lane0_sync_clk", +- "rx_lane1_sync_clk"; +- clocks = +- <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_UFS_PHY_AXI_CLK>, +- <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, +- <&gcc GCC_UFS_PHY_AHB_CLK>, +- <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, +- <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, +- <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, +- <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; +- freq-table-hz = +- <75000000 300000000>, +- <75000000 300000000>, +- <0 0>, +- <0 0>, +- <75000000 300000000>, +- <0 0>, +- <0 0>, +- <0 0>, +- <0 0>; +- status = "disabled"; +- }; +- +- ufs_mem_phy: phy@1d87000 { +- compatible = "qcom,sm8350-qmp-ufs-phy"; +- reg = <0 0x01d87000 0 0xe10>; +- #address-cells = <2>; +- #size-cells = <2>; +- #clock-cells = <1>; +- ranges; +- clock-names = "ref", +- "ref_aux"; +- clocks = <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; +- +- resets = <&ufs_mem_hc 0>; +- reset-names = "ufsphy"; +- status = "disabled"; +- +- ufs_mem_phy_lanes: lanes@1d87400 { +- reg = <0 0x01d87400 0 0x108>, +- <0 0x01d87600 0 0x1e0>, +- <0 0x01d87c00 0 0x1dc>, +- <0 0x01d87800 0 0x108>, +- <0 0x01d87a00 0 0x1e0>; +- #phy-cells = <0>; +- #clock-cells = <0>; +- }; +- }; +- +- slpi: remoteproc@5c00000 { +- compatible = "qcom,sm8350-slpi-pas"; +- reg = <0 0x05c00000 0 0x4000>; +- +- interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, +- <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack"; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "xo"; +- +- power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, +- <&rpmhpd 4>, +- <&rpmhpd 5>; +- power-domain-names = "load_state", "lcx", "lmx"; +- +- memory-region = <&pil_slpi_mem>; +- +- qcom,smem-states = <&smp2p_slpi_out 0>; +- qcom,smem-state-names = "stop"; +- +- status = "disabled"; +- +- glink-edge { +- interrupts-extended = <&ipcc IPCC_CLIENT_SLPI +- IPCC_MPROC_SIGNAL_GLINK_QMP +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_SLPI +- IPCC_MPROC_SIGNAL_GLINK_QMP>; +- +- label = "slpi"; +- qcom,remote-pid = <3>; +- +- }; +- }; +- +- cdsp: remoteproc@98900000 { +- compatible = "qcom,sm8350-cdsp-pas"; +- reg = <0 0x098900000 0 0x1400000>; +- +- interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, +- <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack"; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "xo"; +- +- power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, +- <&rpmhpd 0>, +- <&rpmhpd 10>; +- power-domain-names = "load_state", "cx", "mxc"; +- +- interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; +- +- memory-region = <&pil_cdsp_mem>; +- +- qcom,smem-states = <&smp2p_cdsp_out 0>; +- qcom,smem-state-names = "stop"; +- +- status = "disabled"; +- +- glink-edge { +- interrupts-extended = <&ipcc IPCC_CLIENT_CDSP +- IPCC_MPROC_SIGNAL_GLINK_QMP +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_CDSP +- IPCC_MPROC_SIGNAL_GLINK_QMP>; +- +- label = "cdsp"; +- qcom,remote-pid = <5>; +- }; +- }; +- +- usb_1_hsphy: phy@88e3000 { +- compatible = "qcom,sm8350-usb-hs-phy", +- "qcom,usb-snps-hs-7nm-phy"; +- reg = <0 0x088e3000 0 0x400>; +- status = "disabled"; +- #phy-cells = <0>; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "ref"; +- +- resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; +- }; +- +- usb_2_hsphy: phy@88e4000 { +- compatible = "qcom,sm8250-usb-hs-phy", +- "qcom,usb-snps-hs-7nm-phy"; +- reg = <0 0x088e4000 0 0x400>; +- status = "disabled"; +- #phy-cells = <0>; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "ref"; +- +- resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; +- }; +- +- usb_1_qmpphy: phy-wrapper@88e9000 { +- compatible = "qcom,sm8350-qmp-usb3-phy"; +- reg = <0 0x088e9000 0 0x200>, +- <0 0x088e8000 0 0x20>; +- reg-names = "reg-base", "dp_com"; +- status = "disabled"; +- #clock-cells = <1>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, +- <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; +- clock-names = "aux", "ref_clk_src", "com_aux"; +- +- resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, +- <&gcc GCC_USB3_PHY_PRIM_BCR>; +- reset-names = "phy", "common"; +- +- usb_1_ssphy: phy@88e9200 { +- reg = <0 0x088e9200 0 0x200>, +- <0 0x088e9400 0 0x200>, +- <0 0x088e9c00 0 0x400>, +- <0 0x088e9600 0 0x200>, +- <0 0x088e9800 0 0x200>, +- <0 0x088e9a00 0 0x100>; +- #phy-cells = <0>; +- #clock-cells = <1>; +- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; +- clock-names = "pipe0"; +- clock-output-names = "usb3_phy_pipe_clk_src"; +- }; +- }; +- +- usb_2_qmpphy: phy-wrapper@88eb000 { +- compatible = "qcom,sm8350-qmp-usb3-uni-phy"; +- reg = <0 0x088eb000 0 0x200>; +- status = "disabled"; +- #clock-cells = <1>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, +- <&rpmhcc RPMH_CXO_CLK>, +- <&gcc GCC_USB3_SEC_CLKREF_EN>, +- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; +- clock-names = "aux", "ref_clk_src", "ref", "com_aux"; +- +- resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, +- <&gcc GCC_USB3_PHY_SEC_BCR>; +- reset-names = "phy", "common"; +- +- usb_2_ssphy: phy@88ebe00 { +- reg = <0 0x088ebe00 0 0x200>, +- <0 0x088ec000 0 0x200>, +- <0 0x088eb200 0 0x1100>; +- #phy-cells = <0>; +- #clock-cells = <1>; +- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; +- clock-names = "pipe0"; +- clock-output-names = "usb3_uni_phy_pipe_clk_src"; +- }; +- }; +- +- dc_noc: interconnect@90c0000 { +- compatible = "qcom,sm8350-dc-noc"; +- reg = <0 0x090c0000 0 0x4200>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- gem_noc: interconnect@9100000 { +- compatible = "qcom,sm8350-gem-noc"; +- reg = <0 0x09100000 0 0xb4000>; +- #interconnect-cells = <1>; +- qcom,bcm-voters = <&apps_bcm_voter>; +- }; +- +- usb_1: usb@a6f8800 { +- compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; +- reg = <0 0x0a6f8800 0 0x400>; +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, +- <&gcc GCC_USB30_PRIM_MASTER_CLK>, +- <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, +- <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_PRIM_SLEEP_CLK>; +- clock-names = "cfg_noc", "core", "iface", "mock_utmi", +- "sleep"; +- +- assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_PRIM_MASTER_CLK>; +- assigned-clock-rates = <19200000>, <200000000>; +- +- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, +- <&pdc 14 IRQ_TYPE_EDGE_BOTH>, +- <&pdc 15 IRQ_TYPE_EDGE_BOTH>, +- <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", +- "dm_hs_phy_irq", "ss_phy_irq"; +- +- power-domains = <&gcc USB30_PRIM_GDSC>; +- +- resets = <&gcc GCC_USB30_PRIM_BCR>; +- +- usb_1_dwc3: usb@a600000 { +- compatible = "snps,dwc3"; +- reg = <0 0x0a600000 0 0xcd00>; +- interrupts = ; +- iommus = <&apps_smmu 0x0 0x0>; +- snps,dis_u2_susphy_quirk; +- snps,dis_enblslpm_quirk; +- phys = <&usb_1_hsphy>, <&usb_1_ssphy>; +- phy-names = "usb2-phy", "usb3-phy"; +- }; +- }; +- +- usb_2: usb@a8f8800 { +- compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; +- reg = <0 0x0a8f8800 0 0x400>; +- status = "disabled"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, +- <&gcc GCC_USB30_SEC_MASTER_CLK>, +- <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, +- <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_SEC_SLEEP_CLK>, +- <&gcc GCC_USB3_SEC_CLKREF_EN>; +- clock-names = "cfg_noc", "core", "iface", "mock_utmi", +- "sleep", "xo"; +- +- assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, +- <&gcc GCC_USB30_SEC_MASTER_CLK>; +- assigned-clock-rates = <19200000>, <200000000>; +- +- interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, +- <&pdc 12 IRQ_TYPE_EDGE_BOTH>, +- <&pdc 13 IRQ_TYPE_EDGE_BOTH>, +- <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", +- "dm_hs_phy_irq", "ss_phy_irq"; +- +- power-domains = <&gcc USB30_SEC_GDSC>; +- +- resets = <&gcc GCC_USB30_SEC_BCR>; +- +- usb_2_dwc3: usb@a800000 { +- compatible = "snps,dwc3"; +- reg = <0 0x0a800000 0 0xcd00>; +- interrupts = ; +- iommus = <&apps_smmu 0x20 0x0>; +- snps,dis_u2_susphy_quirk; +- snps,dis_enblslpm_quirk; +- phys = <&usb_2_hsphy>, <&usb_2_ssphy>; +- phy-names = "usb2-phy", "usb3-phy"; +- }; +- }; +- +- adsp: remoteproc@17300000 { +- compatible = "qcom,sm8350-adsp-pas"; +- reg = <0 0x17300000 0 0x100>; +- +- interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, +- <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, +- <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; +- interrupt-names = "wdog", "fatal", "ready", +- "handover", "stop-ack"; +- +- clocks = <&rpmhcc RPMH_CXO_CLK>; +- clock-names = "xo"; +- +- power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, +- <&rpmhpd 4>, +- <&rpmhpd 5>; +- power-domain-names = "load_state", "lcx", "lmx"; +- +- memory-region = <&pil_adsp_mem>; +- +- qcom,smem-states = <&smp2p_adsp_out 0>; +- qcom,smem-state-names = "stop"; +- +- status = "disabled"; +- +- glink-edge { +- interrupts-extended = <&ipcc IPCC_CLIENT_LPASS +- IPCC_MPROC_SIGNAL_GLINK_QMP +- IRQ_TYPE_EDGE_RISING>; +- mboxes = <&ipcc IPCC_CLIENT_LPASS +- IPCC_MPROC_SIGNAL_GLINK_QMP>; +- +- label = "lpass"; +- qcom,remote-pid = <2>; +- }; +- }; +- }; +- +- thermal_zones: thermal-zones { +- cpu0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 1>; +- +- trips { +- cpu0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu0_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu0_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu0_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu0_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 2>; +- +- trips { +- cpu1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu1_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu1_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu1_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu1_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 3>; +- +- trips { +- cpu2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu2_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu2_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu2_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu2_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 4>; +- +- trips { +- cpu3_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu3_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu3_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu3_alert0>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu3_alert1>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu4-top-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 7>; +- +- trips { +- cpu4_top_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu4_top_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu4_top_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu4_top_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu4_top_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu5-top-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 8>; +- +- trips { +- cpu5_top_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu5_top_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu5_top_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu5_top_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu5_top_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu6-top-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 9>; +- +- trips { +- cpu6_top_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu6_top_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu6_top_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu6_top_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu6_top_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu7-top-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 10>; +- +- trips { +- cpu7_top_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu7_top_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu7_top_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu7_top_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu7_top_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu4-bottom-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 11>; +- +- trips { +- cpu4_bottom_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu4_bottom_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu4_bottom_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu4_bottom_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu4_bottom_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu5-bottom-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 12>; +- +- trips { +- cpu5_bottom_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu5_bottom_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu5_bottom_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu5_bottom_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu5_bottom_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu6-bottom-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 13>; +- +- trips { +- cpu6_bottom_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu6_bottom_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu6_bottom_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu6_bottom_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu6_bottom_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- cpu7-bottom-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 14>; +- +- trips { +- cpu7_bottom_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu7_bottom_alert1: trip-point1 { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- cpu7_bottom_crit: cpu_crit { +- temperature = <110000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu7_bottom_alert0>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu7_bottom_alert1>; +- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- aoss0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 0>; +- +- trips { +- aoss0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- cluster0-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 5>; +- +- trips { +- cluster0_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- cluster0_crit: cluster0_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- cluster1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens0 6>; +- +- trips { +- cluster1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- cluster1_crit: cluster1_crit { +- temperature = <110000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- +- aoss1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 0>; +- +- trips { +- aoss1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- gpu-thermal-top { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 1>; +- +- trips { +- gpu1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- }; +- +- gpu-thermal-bottom { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 2>; +- +- trips { +- gpu2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- }; +- +- nspss1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 3>; +- +- trips { +- nspss1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- }; +- +- nspss2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 4>; +- +- trips { +- nspss2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- }; +- +- nspss3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 5>; +- +- trips { +- nspss3_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <1000>; +- type = "hot"; +- }; +- }; +- }; +- +- video-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 6>; +- +- trips { +- video_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- mem-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 7>; +- +- trips { +- mem_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- modem1-thermal-top { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 8>; +- +- trips { +- modem1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- modem2-thermal-top { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 9>; +- +- trips { +- modem2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- modem3-thermal-top { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 10>; +- +- trips { +- modem3_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- modem4-thermal-top { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 11>; +- +- trips { +- modem4_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- camera-thermal-top { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 12>; +- +- trips { +- camera1_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- +- cam-thermal-bottom { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsens1 13>; +- +- trips { +- camera2_alert0: trip-point0 { +- temperature = <90000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/realtek/Makefile b/scripts/dtc/include-prefixes/arm64/realtek/Makefile +deleted file mode 100644 +index ef8d8fcbaa05..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/realtek/Makefile ++++ /dev/null +@@ -1,15 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0-only +- +-dtb-$(CONFIG_ARCH_REALTEK) += rtd1293-ds418j.dtb +- +-dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-mele-v9.dtb +-dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb +-dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-xnano-x5.dtb +-dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb +- +-dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb +- +-dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-bpi-m4.dtb +-dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-lionskin.dtb +- +-dtb-$(CONFIG_ARCH_REALTEK) += rtd1619-mjolnir.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/realtek/rtd1293-ds418j.dts b/scripts/dtc/include-prefixes/arm64/realtek/rtd1293-ds418j.dts +deleted file mode 100644 +index b2e44c6c2d22..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/realtek/rtd1293-ds418j.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +-/* +- * Copyright (c) 2017-2019 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "rtd1293.dtsi" +- +-/ { +- compatible = "synology,ds418j", "realtek,rtd1293"; +- model = "Synology DiskStation DS418j"; +- +- memory@1f000 { +- device_type = "memory"; +- reg = <0x1f000 0x3ffe1000>; /* boot ROM to 1 GiB */ +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/realtek/rtd1293.dtsi b/scripts/dtc/include-prefixes/arm64/realtek/rtd1293.dtsi +deleted file mode 100644 +index 2d92b56ac94d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/realtek/rtd1293.dtsi ++++ /dev/null +@@ -1,55 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +-/* +- * Realtek RTD1293 SoC +- * +- * Copyright (c) 2017-2019 Andreas Färber +- */ +- +-#include "rtd129x.dtsi" +- +-/ { +- compatible = "realtek,rtd1293"; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- next-level-cache = <&l2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- next-level-cache = <&l2>; +- }; +- +- l2: l2-cache { +- compatible = "cache"; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +-}; +- +-&arm_pmu { +- interrupt-affinity = <&cpu0>, <&cpu1>; +-}; +- +-&gic { +- interrupts = ; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/realtek/rtd1295-mele-v9.dts b/scripts/dtc/include-prefixes/arm64/realtek/rtd1295-mele-v9.dts +deleted file mode 100644 +index cf4a57c012a8..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/realtek/rtd1295-mele-v9.dts ++++ /dev/null +@@ -1,31 +0,0 @@ +-/* +- * Copyright (c) 2017-2019 Andreas Färber +- * +- * SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- */ +- +-/dts-v1/; +- +-#include "rtd1295.dtsi" +- +-/ { +- compatible = "mele,v9", "realtek,rtd1295"; +- model = "MeLE V9"; +- +- memory@1f000 { +- device_type = "memory"; +- reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */ +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/realtek/rtd1295-probox2-ava.dts b/scripts/dtc/include-prefixes/arm64/realtek/rtd1295-probox2-ava.dts +deleted file mode 100644 +index 14161c3f304d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/realtek/rtd1295-probox2-ava.dts ++++ /dev/null +@@ -1,31 +0,0 @@ +-/* +- * Copyright (c) 2017-2019 Andreas Färber +- * +- * SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- */ +- +-/dts-v1/; +- +-#include "rtd1295.dtsi" +- +-/ { +- compatible = "probox2,ava", "realtek,rtd1295"; +- model = "PROBOX2 AVA"; +- +- memory@1f000 { +- device_type = "memory"; +- reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */ +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/realtek/rtd1295-xnano-x5.dts b/scripts/dtc/include-prefixes/arm64/realtek/rtd1295-xnano-x5.dts +deleted file mode 100644 +index d7878ff942e6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/realtek/rtd1295-xnano-x5.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +-/* +- * Copyright (c) 2017-2019 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "rtd1295.dtsi" +- +-/ { +- compatible = "xnano,x5", "realtek,rtd1295"; +- model = "Xnano X5"; +- +- memory@1f000 { +- device_type = "memory"; +- reg = <0x1f000 0x3ffe1000>; /* boot ROM to 1 GiB or 2 GiB */ +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/realtek/rtd1295-zidoo-x9s.dts b/scripts/dtc/include-prefixes/arm64/realtek/rtd1295-zidoo-x9s.dts +deleted file mode 100644 +index 4beb37bb9522..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/realtek/rtd1295-zidoo-x9s.dts ++++ /dev/null +@@ -1,35 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +-/* +- * Copyright (c) 2016-2017 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "rtd1295.dtsi" +- +-/ { +- compatible = "zidoo,x9s", "realtek,rtd1295"; +- model = "Zidoo X9S"; +- +- memory@1f000 { +- device_type = "memory"; +- reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */ +- }; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/realtek/rtd1295.dtsi b/scripts/dtc/include-prefixes/arm64/realtek/rtd1295.dtsi +deleted file mode 100644 +index 1402abe80ea1..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/realtek/rtd1295.dtsi ++++ /dev/null +@@ -1,65 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +-/* +- * Realtek RTD1295 SoC +- * +- * Copyright (c) 2016-2019 Andreas Färber +- */ +- +-#include "rtd129x.dtsi" +- +-/ { +- compatible = "realtek,rtd1295"; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- next-level-cache = <&l2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- next-level-cache = <&l2>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x2>; +- next-level-cache = <&l2>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x3>; +- next-level-cache = <&l2>; +- }; +- +- l2: l2-cache { +- compatible = "cache"; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +-}; +- +-&arm_pmu { +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/realtek/rtd1296-ds418.dts b/scripts/dtc/include-prefixes/arm64/realtek/rtd1296-ds418.dts +deleted file mode 100644 +index cc706d13da8b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/realtek/rtd1296-ds418.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +-/* +- * Copyright (c) 2017-2019 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "rtd1296.dtsi" +- +-/ { +- compatible = "synology,ds418", "realtek,rtd1296"; +- model = "Synology DiskStation DS418"; +- +- memory@1f000 { +- device_type = "memory"; +- reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */ +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/realtek/rtd1296.dtsi b/scripts/dtc/include-prefixes/arm64/realtek/rtd1296.dtsi +deleted file mode 100644 +index fb864a139c97..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/realtek/rtd1296.dtsi ++++ /dev/null +@@ -1,65 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +-/* +- * Realtek RTD1296 SoC +- * +- * Copyright (c) 2017-2019 Andreas Färber +- */ +- +-#include "rtd129x.dtsi" +- +-/ { +- compatible = "realtek,rtd1296"; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- next-level-cache = <&l2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- next-level-cache = <&l2>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x2>; +- next-level-cache = <&l2>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x3>; +- next-level-cache = <&l2>; +- }; +- +- l2: l2-cache { +- compatible = "cache"; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +-}; +- +-&arm_pmu { +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/realtek/rtd129x.dtsi b/scripts/dtc/include-prefixes/arm64/realtek/rtd129x.dtsi +deleted file mode 100644 +index 39aefe66a794..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/realtek/rtd129x.dtsi ++++ /dev/null +@@ -1,195 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +-/* +- * Realtek RTD1293/RTD1295/RTD1296 SoC +- * +- * Copyright (c) 2016-2019 Andreas Färber +- */ +- +-/memreserve/ 0x0000000000000000 0x000000000001f000; +-/memreserve/ 0x000000000001f000 0x00000000000e1000; +-/memreserve/ 0x0000000001b00000 0x00000000004be000; +- +-#include +-#include +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- rpc_comm: rpc@1f000 { +- reg = <0x1f000 0x1000>; +- }; +- +- rpc_ringbuf: rpc@1ffe000 { +- reg = <0x1ffe000 0x4000>; +- }; +- +- tee: tee@10100000 { +- reg = <0x10100000 0xf00000>; +- no-map; +- }; +- }; +- +- arm_pmu: arm-pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = ; +- }; +- +- osc27M: osc { +- compatible = "fixed-clock"; +- clock-frequency = <27000000>; +- #clock-cells = <0>; +- clock-output-names = "osc27M"; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */ +- /* Exclude up to 2 GiB of RAM */ +- <0x80000000 0x80000000 0x80000000>; +- +- rbus: bus@98000000 { +- compatible = "simple-bus"; +- reg = <0x98000000 0x200000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x98000000 0x200000>; +- +- crt: syscon@0 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x0 0x1800>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1800>; +- }; +- +- iso: syscon@7000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x7000 0x1000>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x7000 0x1000>; +- }; +- +- sb2: syscon@1a000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x1a000 0x1000>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1a000 0x1000>; +- }; +- +- misc: syscon@1b000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x1b000 0x1000>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1b000 0x1000>; +- }; +- +- scpu_wrapper: syscon@1d000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x1d000 0x2000>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1d000 0x2000>; +- }; +- }; +- +- gic: interrupt-controller@ff011000 { +- compatible = "arm,gic-400"; +- reg = <0xff011000 0x1000>, +- <0xff012000 0x2000>, +- <0xff014000 0x2000>, +- <0xff016000 0x2000>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- }; +-}; +- +-&crt { +- reset1: reset-controller@0 { +- compatible = "snps,dw-low-reset"; +- reg = <0x0 0x4>; +- #reset-cells = <1>; +- }; +- +- reset2: reset-controller@4 { +- compatible = "snps,dw-low-reset"; +- reg = <0x4 0x4>; +- #reset-cells = <1>; +- }; +- +- reset3: reset-controller@8 { +- compatible = "snps,dw-low-reset"; +- reg = <0x8 0x4>; +- #reset-cells = <1>; +- }; +- +- reset4: reset-controller@50 { +- compatible = "snps,dw-low-reset"; +- reg = <0x50 0x4>; +- #reset-cells = <1>; +- }; +-}; +- +-&iso { +- iso_reset: reset-controller@88 { +- compatible = "snps,dw-low-reset"; +- reg = <0x88 0x4>; +- #reset-cells = <1>; +- }; +- +- wdt: watchdog@680 { +- compatible = "realtek,rtd1295-watchdog"; +- reg = <0x680 0x100>; +- clocks = <&osc27M>; +- }; +- +- uart0: serial@800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x800 0x400>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <27000000>; +- resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; +- status = "disabled"; +- }; +-}; +- +-&misc { +- uart1: serial@200 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x200 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <432000000>; +- resets = <&reset2 RTD1295_RSTN_UR1>; +- status = "disabled"; +- }; +- +- uart2: serial@400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x400 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <432000000>; +- resets = <&reset2 RTD1295_RSTN_UR2>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/realtek/rtd1395-bpi-m4.dts b/scripts/dtc/include-prefixes/arm64/realtek/rtd1395-bpi-m4.dts +deleted file mode 100644 +index 9891967d1315..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/realtek/rtd1395-bpi-m4.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +-/* +- * Copyright (c) 2019 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "rtd1395.dtsi" +- +-/ { +- compatible = "bananapi,bpi-m4", "realtek,rtd1395"; +- model = "Banana Pi BPI-M4"; +- +- memory@2f000 { +- device_type = "memory"; +- reg = <0x2f000 0x3ffd1000>; /* boot ROM to 1 GiB or 2 GiB */ +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/realtek/rtd1395-lionskin.dts b/scripts/dtc/include-prefixes/arm64/realtek/rtd1395-lionskin.dts +deleted file mode 100644 +index 83f9b536cdea..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/realtek/rtd1395-lionskin.dts ++++ /dev/null +@@ -1,36 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +-/* +- * Copyright (c) 2019 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "rtd1395.dtsi" +- +-/ { +- compatible = "realtek,lion-skin", "realtek,rtd1395"; +- model = "Realtek Lion Skin EVB"; +- +- memory@2f000 { +- device_type = "memory"; +- reg = <0x2f000 0x3ffd1000>; /* boot ROM to 1 GiB or 2 GiB */ +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-/* debug console (J1) */ +-&uart0 { +- status = "okay"; +-}; +- +-/* M.2 slot (CON1) */ +-&uart1 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/realtek/rtd1395.dtsi b/scripts/dtc/include-prefixes/arm64/realtek/rtd1395.dtsi +deleted file mode 100644 +index 05c9216a87ee..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/realtek/rtd1395.dtsi ++++ /dev/null +@@ -1,65 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +-/* +- * Realtek RTD1395 SoC +- * +- * Copyright (c) 2019 Andreas Färber +- */ +- +-#include "rtd139x.dtsi" +- +-/ { +- compatible = "realtek,rtd1395"; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- next-level-cache = <&l2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- next-level-cache = <&l2>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x2>; +- next-level-cache = <&l2>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x3>; +- next-level-cache = <&l2>; +- }; +- +- l2: l2-cache { +- compatible = "cache"; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +-}; +- +-&arm_pmu { +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/realtek/rtd139x.dtsi b/scripts/dtc/include-prefixes/arm64/realtek/rtd139x.dtsi +deleted file mode 100644 +index a3c10ceeb586..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/realtek/rtd139x.dtsi ++++ /dev/null +@@ -1,193 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +-/* +- * Realtek RTD1395 SoC family +- * +- * Copyright (c) 2019 Andreas Färber +- */ +- +-/memreserve/ 0x0000000000000000 0x000000000002f000; +-/memreserve/ 0x000000000002f000 0x00000000000d1000; +- +-#include +-#include +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- rpc_comm: rpc@2f000 { +- reg = <0x2f000 0x1000>; +- }; +- +- rpc_ringbuf: rpc@1ffe000 { +- reg = <0x1ffe000 0x4000>; +- }; +- +- tee: tee@10100000 { +- reg = <0x10100000 0xf00000>; +- no-map; +- }; +- }; +- +- arm_pmu: arm-pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = ; +- }; +- +- osc27M: osc { +- compatible = "fixed-clock"; +- clock-frequency = <27000000>; +- #clock-cells = <0>; +- clock-output-names = "osc27M"; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */ +- <0x98000000 0x98000000 0x68000000>; +- +- rbus: bus@98000000 { +- compatible = "simple-bus"; +- reg = <0x98000000 0x200000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x98000000 0x200000>; +- +- crt: syscon@0 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x0 0x1000>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1000>; +- }; +- +- iso: syscon@7000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x7000 0x1000>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x7000 0x1000>; +- }; +- +- sb2: syscon@1a000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x1a000 0x1000>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1a000 0x1000>; +- }; +- +- misc: syscon@1b000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x1b000 0x1000>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1b000 0x1000>; +- }; +- +- scpu_wrapper: syscon@1d000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x1d000 0x2000>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1d000 0x2000>; +- }; +- }; +- +- gic: interrupt-controller@ff011000 { +- compatible = "arm,gic-400"; +- reg = <0xff011000 0x1000>, +- <0xff012000 0x2000>, +- <0xff014000 0x2000>, +- <0xff016000 0x2000>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- }; +-}; +- +-&crt { +- reset1: reset-controller@0 { +- compatible = "snps,dw-low-reset"; +- reg = <0x0 0x4>; +- #reset-cells = <1>; +- }; +- +- reset2: reset-controller@4 { +- compatible = "snps,dw-low-reset"; +- reg = <0x4 0x4>; +- #reset-cells = <1>; +- }; +- +- reset3: reset-controller@8 { +- compatible = "snps,dw-low-reset"; +- reg = <0x8 0x4>; +- #reset-cells = <1>; +- }; +- +- reset4: reset-controller@50 { +- compatible = "snps,dw-low-reset"; +- reg = <0x50 0x4>; +- #reset-cells = <1>; +- }; +-}; +- +-&iso { +- iso_reset: reset-controller@88 { +- compatible = "snps,dw-low-reset"; +- reg = <0x88 0x4>; +- #reset-cells = <1>; +- }; +- +- wdt: watchdog@680 { +- compatible = "realtek,rtd1295-watchdog"; +- reg = <0x680 0x100>; +- clocks = <&osc27M>; +- }; +- +- uart0: serial@800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x800 0x400>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <27000000>; +- resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; +- status = "disabled"; +- }; +-}; +- +-&misc { +- uart1: serial@200 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x200 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <432000000>; +- resets = <&reset2 RTD1295_RSTN_UR1>; +- status = "disabled"; +- }; +- +- uart2: serial@400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x400 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <432000000>; +- resets = <&reset2 RTD1295_RSTN_UR2>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/realtek/rtd1619-mjolnir.dts b/scripts/dtc/include-prefixes/arm64/realtek/rtd1619-mjolnir.dts +deleted file mode 100644 +index 90ed6681468f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/realtek/rtd1619-mjolnir.dts ++++ /dev/null +@@ -1,44 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +-/* +- * Copyright (c) 2019 Realtek Semiconductor Corp. +- * Copyright (c) 2019 Andreas Färber +- */ +- +-/dts-v1/; +- +-#include "rtd1619.dtsi" +- +-/ { +- compatible = "realtek,mjolnir", "realtek,rtd1619"; +- model = "Realtek Mjolnir EVB"; +- +- memory@2e000 { +- device_type = "memory"; +- reg = <0x2e000 0x7ffd2000>; /* boot ROM to 2 GiB */ +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- }; +-}; +- +-/* debug console (J1) */ +-&uart0 { +- status = "okay"; +-}; +- +-/* M.2 slot (CON4) */ +-&uart1 { +- status = "disabled"; +-}; +- +-/* GPIO connector (T1) */ +-&uart2 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/realtek/rtd1619.dtsi b/scripts/dtc/include-prefixes/arm64/realtek/rtd1619.dtsi +deleted file mode 100644 +index e52bf708b04e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/realtek/rtd1619.dtsi ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +-/* +- * Realtek RTD1619 SoC +- * +- * Copyright (c) 2019 Realtek Semiconductor Corp. +- */ +- +-#include "rtd16xx.dtsi" +- +-/ { +- compatible = "realtek,rtd1619"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/realtek/rtd16xx.dtsi b/scripts/dtc/include-prefixes/arm64/realtek/rtd16xx.dtsi +deleted file mode 100644 +index afba5f04c8ec..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/realtek/rtd16xx.dtsi ++++ /dev/null +@@ -1,229 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +-/* +- * Realtek RTD16xx SoC family +- * +- * Copyright (c) 2019 Realtek Semiconductor Corp. +- * Copyright (c) 2019 Andreas Färber +- */ +- +-#include +-#include +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- rpc_comm: rpc@2f000 { +- reg = <0x2f000 0x1000>; +- }; +- +- rpc_ringbuf: rpc@1ffe000 { +- reg = <0x1ffe000 0x4000>; +- }; +- +- tee: tee@10100000 { +- reg = <0x10100000 0xf00000>; +- no-map; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- }; +- +- cpu1: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x100>; +- enable-method = "psci"; +- next-level-cache = <&l3>; +- }; +- +- cpu2: cpu@200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x200>; +- enable-method = "psci"; +- next-level-cache = <&l3>; +- }; +- +- cpu3: cpu@300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x300>; +- enable-method = "psci"; +- next-level-cache = <&l3>; +- }; +- +- cpu4: cpu@400 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x400>; +- enable-method = "psci"; +- next-level-cache = <&l3>; +- }; +- +- cpu5: cpu@500 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x500>; +- enable-method = "psci"; +- next-level-cache = <&l3>; +- }; +- +- l2: l2-cache { +- compatible = "cache"; +- next-level-cache = <&l3>; +- +- }; +- +- l3: l3-cache { +- compatible = "cache"; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- arm_pmu: pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, +- <&cpu3>, <&cpu4>, <&cpu5>; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- osc27M: osc { +- compatible = "fixed-clock"; +- clock-frequency = <27000000>; +- clock-output-names = "osc27M"; +- #clock-cells = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x0002e000>, /* boot ROM */ +- <0x98000000 0x98000000 0x68000000>; +- +- rbus: bus@98000000 { +- compatible = "simple-bus"; +- reg = <0x98000000 0x200000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x98000000 0x200000>; +- +- crt: syscon@0 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x0 0x1000>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x1000>; +- }; +- +- iso: syscon@7000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x7000 0x1000>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x7000 0x1000>; +- }; +- +- sb2: syscon@1a000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x1a000 0x1000>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1a000 0x1000>; +- }; +- +- misc: syscon@1b000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x1b000 0x1000>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1b000 0x1000>; +- }; +- +- scpu_wrapper: syscon@1d000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x1d000 0x1000>; +- reg-io-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1d000 0x1000>; +- }; +- }; +- +- gic: interrupt-controller@ff100000 { +- compatible = "arm,gic-v3"; +- reg = <0xff100000 0x10000>, +- <0xff140000 0xc0000>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- }; +-}; +- +-&iso { +- uart0: serial0@800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x800 0x400>; +- reg-shift = <2>; +- reg-io-width = <4>; +- interrupts = ; +- clock-frequency = <27000000>; +- status = "disabled"; +- }; +-}; +- +-&misc { +- uart1: serial1@200 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x200 0x400>; +- reg-shift = <2>; +- reg-io-width = <4>; +- interrupts = ; +- clock-frequency = <432000000>; +- status = "disabled"; +- }; +- +- uart2: serial2@400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x400 0x400>; +- reg-shift = <2>; +- reg-io-width = <4>; +- interrupts = ; +- clock-frequency = <432000000>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/Makefile b/scripts/dtc/include-prefixes/arm64/renesas/Makefile +deleted file mode 100644 +index 15a53b513966..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/Makefile ++++ /dev/null +@@ -1,74 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-beacon-rzg2m-kit.dtb +-dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb +-dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb +-dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-idk-1110wr.dtb +-dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-mipi-2.1.dtb +-dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2.dtb +-dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex.dtb +-dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb +- +-dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-beacon-rzg2n-kit.dtb +-dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb +-dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb +-dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb +-dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-mipi-2.1.dtb +-dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2.dtb +-dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex.dtb +-dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dtb +- +-dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb +-dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874.dtb +-dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-idk-2121wr.dtb +-dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-mipi-2.1.dtb +- +-dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-beacon-rzg2h-kit.dtb +-dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb +-dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex.dtb +-dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-idk-1110wr.dtb +-dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-mipi-2.1.dtb +- +-dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-salvator-x.dtb +-dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb +-dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb-kf.dtb +- +-dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-x.dtb +-dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-xs.dtb +-dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-ulcb.dtb +-dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-ulcb-kf.dtb +- +-dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-x.dtb +-dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-xs.dtb +-dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb.dtb +-dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb-kf.dtb +- +-dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-salvator-xs.dtb +-dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-ulcb.dtb +-dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-ulcb-kf.dtb +- +-dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb +-dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-xs.dtb +-dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb.dtb +-dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb-kf.dtb +- +-dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb +-dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-v3msk.dtb +- +-dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb +-dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-v3hsk.dtb +- +-dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb +- +-dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb +- +-dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb +- +-dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb +-dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb.dtb +-dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb-kf.dtb +- +-dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-salvator-xs.dtb +-dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb.dtb +-dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb +- +-dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/aistarvision-mipi-adapter-2.1.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/aistarvision-mipi-adapter-2.1.dtsi +deleted file mode 100644 +index 7ce986f0a06f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/aistarvision-mipi-adapter-2.1.dtsi ++++ /dev/null +@@ -1,96 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the AISTARVISION MIPI Adapter V2.1 +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-/ { +- ov5645_vdddo_1v8: 1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "camera_vdddo"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- ov5645_vdda_2v8: 2p8v { +- compatible = "regulator-fixed"; +- regulator-name = "camera_vdda"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- ov5645_vddd_1v5: 1p5v { +- compatible = "regulator-fixed"; +- regulator-name = "camera_vddd"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- +- imx219_vana_2v8: 2p8v { +- compatible = "regulator-fixed"; +- regulator-name = "camera_vana"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- +- imx219_vdig_1v8: 1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "camera_vdig"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- +- imx219_vddl_1v2: 1p2v { +- compatible = "regulator-fixed"; +- regulator-name = "camera_vddl"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- osc25250_clk: osc25250_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- }; +-}; +- +-&MIPI_OV5645_PARENT_I2C { +- ov5645: ov5645@3c { +- compatible = "ovti,ov5645"; +- reg = <0x3c>; +- clock-names = "xclk"; +- clocks = <&osc25250_clk>; +- clock-frequency = <24000000>; +- vdddo-supply = <&ov5645_vdddo_1v8>; +- vdda-supply = <&ov5645_vdda_2v8>; +- vddd-supply = <&ov5645_vddd_1v5>; +- +- port { +- ov5645_ep: endpoint { +- }; +- }; +- }; +-}; +- +-&MIPI_IMX219_PARENT_I2C { +- imx219: imx219@10 { +- compatible = "sony,imx219"; +- reg = <0x10>; +- clocks = <&osc25250_clk>; +- VANA-supply = <&imx219_vana_2v8>; +- VDIG-supply = <&imx219_vdig_1v8>; +- VDDL-supply = <&imx219_vddl_1v2>; +- +- port { +- imx219_ep: endpoint { +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/beacon-renesom-baseboard.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/beacon-renesom-baseboard.dtsi +deleted file mode 100644 +index 2692cc64bff6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/beacon-renesom-baseboard.dtsi ++++ /dev/null +@@ -1,796 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2020, Compass Electronics Group, LLC +- */ +- +-#include +-#include +-#include +- +-/ { +- backlight_lvds: backlight-lvds { +- compatible = "pwm-backlight"; +- power-supply = <®_lcd>; +- enable-gpios = <&gpio_exp1 3 GPIO_ACTIVE_HIGH>; +- pwms = <&pwm2 0 25000>; +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +- +- backlight_dpi: backlight-dpi { +- compatible = "pwm-backlight"; +- power-supply = <®_lcd>; +- enable-gpios = <&gpio_exp1 7 GPIO_ACTIVE_LOW>; +- pwms = <&pwm0 0 25000>; +- brightness-levels = <0 25 33 50 63 75 88 100>; +- default-brightness-level = <6>; +- }; +- +- hdmi0-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi0_con: endpoint { +- remote-endpoint = <&rcar_dw_hdmi0_out>; +- }; +- }; +- }; +- +- keys { +- compatible = "gpio-keys"; +- +- key-1 { /* S19 */ +- gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "Up"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-2 { /*S20 */ +- gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "Left"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-3 { /* S21 */ +- gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "Down"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-4 { /* S22 */ +- gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "Right"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-5 { /* S23 */ +- gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "Center"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&led_pins>; +- pinctrl-names = "default"; +- +- led0 { +- gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; +- label = "LED0"; +- linux,default-trigger = "heartbeat"; +- }; +- led1 { +- gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; +- label = "LED1"; +- }; +- led2 { +- gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; +- label = "LED2"; +- }; +- led3 { +- gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; +- label = "LED3"; +- }; +- }; +- +- lvds { +- compatible = "panel-lvds"; +- power-supply = <®_lcd_reset>; +- width-mm = <223>; +- height-mm = <125>; +- backlight = <&backlight_lvds>; +- data-mapping = "vesa-24"; +- +- panel-timing { +- /* 800x480@60Hz */ +- clock-frequency = <30000000>; +- hactive = <800>; +- vactive = <480>; +- hsync-len = <48>; +- hfront-porch = <40>; +- hback-porch = <40>; +- vfront-porch = <13>; +- vback-porch = <29>; +- vsync-len = <1>; +- hsync-active = <1>; +- vsync-active = <3>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- }; +- +- rgb { +- /* Different LCD with compatible timings */ +- compatible = "rocktech,rk070er9427"; +- backlight = <&backlight_dpi>; +- enable-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; +- power-supply = <®_lcd>; +- port { +- rgb_panel: endpoint { +- remote-endpoint = <&du_out_rgb>; +- }; +- }; +- }; +- +- reg_audio: regulator_audio { +- compatible = "regulator-fixed"; +- regulator-name = "audio-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio_exp4 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_lcd: regulator-lcd { +- compatible = "regulator-fixed"; +- regulator-name = "lcd_panel_pwr"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio_exp1 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_lcd_reset: regulator-lcd-reset { +- compatible = "regulator-fixed"; +- regulator-name = "nLCD_RESET"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- gpio = <&gpio5 3 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- vin-supply = <®_lcd>; +- }; +- +- reg_cam0: regulator_camera { +- compatible = "regulator-fixed"; +- regulator-name = "reg_cam0"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio_exp2 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- reg_cam1: regulator_camera { +- compatible = "regulator-fixed"; +- regulator-name = "reg_cam1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- gpio = <&gpio_exp2 5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- startup-delay-us = <100000>; +- }; +- +- sound_card { +- compatible = "audio-graph-card"; +- label = "rcar-sound"; +- dais = <&rsnd_port0>, <&rsnd_port1>; +- widgets = "Microphone", "Mic Jack", +- "Line", "Line In Jack", +- "Headphone", "Headphone Jack"; +- mic-det-gpio = <&gpio0 2 GPIO_ACTIVE_LOW>; +- routing = "Headphone Jack", "HPOUTL", +- "Headphone Jack", "HPOUTR", +- "IN3R", "MICBIAS", +- "Mic Jack", "IN3R"; +- }; +- +- vccq_sdhi0: regulator-vccq-sdhi0 { +- compatible = "regulator-gpio"; +- regulator-name = "SDHI0 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- /* External DU dot clocks */ +- x302_clk: x302-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <33000000>; +- }; +- +- x304_clk: x304-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- connector { +- compatible = "usb-c-connector"; +- label = "USB-C"; +- data-role = "dual"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- hs_ep: endpoint { +- remote-endpoint = <&usb3_hs_ep>; +- }; +- }; +- port@1 { +- reg = <1>; +- ss_ep: endpoint { +- remote-endpoint = <&hd3ss3220_in_ep>; +- }; +- }; +- }; +- }; +-}; +- +-&audio_clk_b { +- clock-frequency = <22579200>; +-}; +- +-&can0 { +- pinctrl-0 = <&can0_pins>; +- pinctrl-names = "default"; +- renesas,can-clock-select = <0x0>; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-0 = <&can1_pins>; +- pinctrl-names = "default"; +- renesas,can-clock-select = <0x0>; +- status = "okay"; +-}; +- +-&du_out_rgb { +- remote-endpoint = <&rgb_panel>; +-}; +- +-&ehci0 { +- dr_mode = "otg"; +- status = "okay"; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>; +-}; +- +-&ehci1 { +- status = "okay"; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>; +-}; +- +-&hdmi0 { +- status = "okay"; +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- dw_hdmi0_in: endpoint { +- remote-endpoint = <&du_out_hdmi0>; +- }; +- }; +- port@1 { +- reg = <1>; +- rcar_dw_hdmi0_out: endpoint { +- remote-endpoint = <&hdmi0_con>; +- }; +- }; +- port@2 { +- reg = <2>; +- dw_hdmi0_snd_in: endpoint { +- remote-endpoint = <&rsnd_endpoint1>; +- }; +- }; +- }; +-}; +- +-&hscif1 { +- pinctrl-0 = <&hscif1_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&hsusb { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +- clock-frequency = <400000>; +- pinctrl-0 = <&i2c2_pins>; +- pinctrl-names = "default"; +- +- gpio_exp2: gpio@21 { +- compatible = "onnn,pca9654"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpio_exp3: gpio@22 { +- compatible = "onnn,pca9654"; +- reg = <0x22>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpio_exp4: gpio@23 { +- compatible = "onnn,pca9654"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- versaclock6_bb: clock-controller@6a { +- compatible = "idt,5p49v6965"; +- reg = <0x6a>; +- #clock-cells = <1>; +- clocks = <&x304_clk>; +- clock-names = "xin"; +- +- assigned-clocks = <&versaclock6_bb 1>, +- <&versaclock6_bb 2>, +- <&versaclock6_bb 3>, +- <&versaclock6_bb 4>; +- assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24576000>; +- +- OUT1 { +- idt,mode = ; +- idt,voltage-microvolt = <1800000>; +- idt,slew-percent = <100>; +- }; +- +- OUT2 { +- idt,mode = ; +- idt,voltage-microvolt = <1800000>; +- idt,slew-percent = <100>; +- }; +- +- OUT3 { +- idt,mode = ; +- idt,voltage-microvolt = <3300000>; +- idt,slew-percent = <100>; +- }; +- +- OUT4 { +- idt,mode = ; +- idt,voltage-microvolt = <3300000>; +- idt,slew-percent = <100>; +- }; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <400000>; +- +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +-}; +- +-&i2c5 { +- status = "okay"; +- clock-frequency = <400000>; +- pinctrl-0 = <&i2c5_pins>; +- pinctrl-names = "default"; +- +- codec: wm8962@1a { +- compatible = "wlf,wm8962"; +- reg = <0x1a>; +- clocks = <&versaclock6_bb 3>; +- DCVDD-supply = <®_audio>; +- DBVDD-supply = <®_audio>; +- AVDD-supply = <®_audio>; +- CPVDD-supply = <®_audio>; +- MICVDD-supply = <®_audio>; +- PLLVDD-supply = <®_audio>; +- SPKVDD1-supply = <®_audio>; +- SPKVDD2-supply = <®_audio>; +- gpio-cfg = < +- 0x0000 /* 0:Default */ +- 0x0000 /* 1:Default */ +- 0x0000 /* 2:Default */ +- 0x0000 /* 3:Default */ +- 0x0000 /* 4:Default */ +- 0x0000 /* 5:Default */ +- >; +- port { +- wm8962_endpoint: endpoint { +- remote-endpoint = <&rsnd_endpoint0>; +- }; +- }; +- }; +- +- /* 0 - lcd_reset */ +- /* 1 - lcd_pwr */ +- /* 2 - lcd_select */ +- /* 3 - backlight-enable */ +- /* 4 - Touch_shdwn */ +- /* 5 - LCD_H_pol */ +- /* 6 - lcd_V_pol */ +- gpio_exp1: gpio@20 { +- compatible = "onnn,pca9654"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- touchscreen@26 { +- compatible = "ilitek,ili2117"; +- reg = <0x26>; +- interrupt-parent = <&gpio5>; +- interrupts = <9 IRQ_TYPE_EDGE_RISING>; +- wakeup-source; +- }; +- +- hd3ss3220@47 { +- compatible = "ti,hd3ss3220"; +- reg = <0x47>; +- interrupt-parent = <&gpio6>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- hd3ss3220_in_ep: endpoint { +- remote-endpoint = <&ss_ep>; +- }; +- }; +- port@1 { +- reg = <1>; +- hd3ss3220_out_ep: endpoint { +- remote-endpoint = <&usb3_role_switch>; +- }; +- }; +- }; +- }; +-}; +- +-&lvds0 { +- status = "okay"; +- +- ports { +- port@1 { +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in>; +- }; +- }; +- }; +-}; +- +-&msiof1 { +- pinctrl-0 = <&msiof1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- cs-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; +-}; +- +-&ohci0 { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&pciec0 { +- status = "okay"; +-}; +- +-&pciec1 { +- status = "okay"; +-}; +- +-&pcie_bus_clk { +- clock-frequency = <100000000>; +-}; +- +-&pfc { +- can0_pins: can0 { +- groups = "can0_data_a"; +- function = "can0"; +- }; +- +- can1_pins: can1 { +- groups = "can1_data"; +- function = "can1"; +- }; +- +- du_pins: du { +- groups = "du_rgb888", "du_sync", "du_clk_out_1", "du_disp"; +- function = "du"; +- }; +- +- i2c2_pins: i2c2 { +- groups = "i2c2_a"; +- function = "i2c2"; +- }; +- +- i2c5_pins: i2c5 { +- groups = "i2c5"; +- function = "i2c5"; +- }; +- +- led_pins: leds { +- /* GP_0_4 , AVS1, AVS2, GP_7_3 */ +- pins = "GP_0_4", "GP_7_0", "GP_7_1", "GP_7_3"; +- bias-pull-down; +- }; +- +- msiof1_pins: msiof1 { +- groups = "msiof1_clk_g", "msiof1_rxd_g", "msiof1_txd_g"; +- function = "msiof1"; +- }; +- +- pwm0_pins: pwm0 { +- groups = "pwm0"; +- function = "pwm0"; +- }; +- +- pwm2_pins: pwm2 { +- groups = "pwm2_a"; +- function = "pwm2"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <3300>; +- }; +- +- sdhi0_pins_uhs: sd0_uhs { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <1800>; +- }; +- +- sound_pins: sound { +- groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; +- function = "ssi"; +- }; +- +- sound_clk_pins: sound_clk { +- groups = "audio_clk_a_a", "audio_clk_b_a"; +- function = "audio_clk"; +- }; +- +- usb0_pins: usb0 { +- mux { +- groups = "usb0"; +- function = "usb0"; +- }; +- }; +- +- usb1_pins: usb1 { +- mux { +- groups = "usb1"; +- function = "usb1"; +- }; +- }; +- +- usb30_pins: usb30 { +- mux { +- groups = "usb30"; +- function = "usb30"; +- }; +- }; +-}; +- +-&pwm0 { +- pinctrl-0 = <&pwm0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-0 = <&pwm2_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&rcar_sound { +- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; +- pinctrl-names = "default"; +- +- /* Single DAI */ +- #sound-dai-cells = <0>; +- +- /* audio_clkout0/1/2/3 */ +- #clock-cells = <1>; +- clock-frequency = <11289600>; +- +- status = "okay"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- rsnd_port0: port@0 { +- reg = <0>; +- rsnd_endpoint0: endpoint { +- remote-endpoint = <&wm8962_endpoint>; +- +- dai-format = "i2s"; +- bitclock-master = <&rsnd_endpoint0>; +- frame-master = <&rsnd_endpoint0>; +- +- playback = <&ssi1>, <&dvc1>, <&src1>; +- capture = <&ssi0>; +- }; +- }; +- rsnd_port1: port@1 { +- reg = <0x01>; +- rsnd_endpoint1: endpoint { +- remote-endpoint = <&dw_hdmi0_snd_in>; +- +- dai-format = "i2s"; +- bitclock-master = <&rsnd_endpoint1>; +- frame-master = <&rsnd_endpoint1>; +- +- playback = <&ssi2>; +- }; +- }; +- }; +-}; +- +-&rwdt { +- status = "okay"; +- timeout-sec = <60>; +-}; +- +-&scif0 { +- pinctrl-0 = <&scif0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&scif5 { +- pinctrl-0 = <&scif5_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&scif_clk { +- clock-frequency = <14745600>; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-1 = <&sdhi0_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <&vccq_sdhi0>; +- cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- status = "okay"; +-}; +- +-&ssi1 { +- shared-pin; +-}; +- +-&tmu0 { +- status = "okay"; +-}; +- +-&tmu1 { +- status = "okay"; +-}; +- +-&tmu2 { +- status = "okay"; +-}; +- +-&tmu3 { +- status = "okay"; +-}; +- +-&tmu4 { +- status = "okay"; +-}; +- +-&usb2_phy0 { +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&usb2_phy1 { +- pinctrl-0 = <&usb1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&usb3_peri0 { +- companion = <&xhci0>; +- status = "okay"; +- usb-role-switch; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- usb3_hs_ep: endpoint { +- remote-endpoint = <&hs_ep>; +- }; +- }; +- port@1 { +- reg = <1>; +- usb3_role_switch: endpoint { +- remote-endpoint = <&hd3ss3220_out_ep>; +- }; +- }; +- }; +-}; +- +-&usb3_phy0 { +- status = "okay"; +-}; +- +-&vin0 { +- status = "okay"; +-}; +-&vin1 { +- status = "okay"; +-}; +-&vin2 { +- status = "okay"; +-}; +-&vin3 { +- status = "okay"; +-}; +-&vin4 { +- status = "okay"; +-}; +-&vin5 { +- status = "okay"; +-}; +-&vin6 { +- status = "okay"; +-}; +-&vin7 { +- status = "okay"; +-}; +- +-&xhci0 +-{ +- pinctrl-0 = <&usb30_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/beacon-renesom-som.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/beacon-renesom-som.dtsi +deleted file mode 100644 +index 937d17a426b6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/beacon-renesom-som.dtsi ++++ /dev/null +@@ -1,333 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2020, Compass Electronics Group, LLC +- */ +- +-#include +-#include +- +-/ { +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x78000000>; +- }; +- +- osc_32k: osc_32k { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "osc_32k"; +- }; +- +- reg_1p8v: regulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator1 { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- wlan_pwrseq: wlan_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pca9654 1 GPIO_ACTIVE_LOW>; +- clocks = <&osc_32k>; +- clock-names = "ext_clock"; +- post-power-on-delay-ms = <80>; +- }; +-}; +- +-&avb { +- pinctrl-0 = <&avb_pins>; +- pinctrl-names = "default"; +- phy-mode = "rgmii-rxid"; +- phy-handle = <&phy0>; +- rx-internal-delay-ps = <1800>; +- tx-internal-delay-ps = <2000>; +- clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>; +- clock-names = "fck", "refclk"; +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- interrupt-parent = <&gpio2>; +- interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&extal_clk { +- clock-frequency = <16666666>; +-}; +- +-&extalr_clk { +- clock-frequency = <32768>; +-}; +- +-&gpio6 { +- usb_hub_reset { +- gpio-hog; +- gpios = <10 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "usb-hub-reset"; +- }; +-}; +- +-&hscif0 { +- pinctrl-0 = <&hscif0_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- shutdown-gpios = <&pca9654 2 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; +- device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>; +- clocks = <&osc_32k>; +- clock-names = "extclk"; +- max-speed = <4000000>; +- }; +-}; +- +-&hscif2 { +- status = "okay"; +- pinctrl-0 = <&hscif2_pins>; +- pinctrl-names = "default"; +-}; +- +-&i2c4 { +- status = "okay"; +- clock-frequency = <100000>; +- +- pca9654: gpio@20 { +- compatible = "onnn,pca9654"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-line-names = +- "i2c4_20_0", +- "wl_reg_on", +- "bt_reg_on", +- "i2c4_20_3", +- "i2c4_20_4", +- "bt_dev_wake", +- "i2c4_20_6", +- "i2c4_20_7"; +- }; +- +- pca9654_lte: gpio@21 { +- compatible = "onnn,pca9654"; +- reg = <0x21>; +- interrupt-parent = <&gpio5>; +- interrupts = <25 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-line-names = +- "i2c4_21_0", +- "zoe_pwr_on", +- "zoe_extint", +- "zoe_reset_n", +- "sara_reset", +- "i2c4_21_5", +- "sara_pwr_off", +- "sara_networking_status"; +- }; +- +- eeprom@50 { +- compatible = "microchip,24c64", "atmel,24c64"; +- pagesize = <32>; +- read-only; /* Manufacturing EEPROM programmed at factory */ +- reg = <0x50>; +- }; +- +- rtc@51 { +- compatible = "nxp,pcf85263"; +- reg = <0x51>; +- }; +- +- versaclock5: versaclock_som@6a { +- compatible = "idt,5p49v6965"; +- reg = <0x6a>; +- #clock-cells = <1>; +- clocks = <&x304_clk>; +- clock-names = "xin"; +- /* du_dotclkin0, du_dotclkin2, usb_extal, avb_txcrefclk */ +- assigned-clocks = <&versaclock5 1>, +- <&versaclock5 2>, +- <&versaclock5 3>, +- <&versaclock5 4>; +- +- assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>; +- +- OUT1 { +- idt,mode = ; +- idt,voltage-microvolt = <1800000>; +- idt,slew-percent = <100>; +- }; +- +- OUT2 { +- idt,mode = ; +- idt,voltage-microvolt = <1800000>; +- idt,slew-percent = <100>; +- }; +- +- OUT3 { +- idt,mode = ; +- idt,voltage-microvolt = <1800000>; +- idt,slew-percent = <100>; +- }; +- +- OUT4 { +- idt,mode = ; +- idt,voltage-microvolt = <3300000>; +- idt,slew-percent = <100>; +- }; +- }; +-}; +- +-&pfc { +- pinctrl-0 = <&scif_clk_pins>; +- pinctrl-names = "default"; +- +- avb_pins: avb { +- mux { +- groups = "avb_link", "avb_mdio", "avb_mii"; +- function = "avb"; +- }; +- +- pins_mdio { +- groups = "avb_mdio"; +- drive-strength = <24>; +- }; +- +- pins_mii_tx { +- pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", +- "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; +- drive-strength = <12>; +- }; +- }; +- +- scif2_pins: scif2 { +- groups = "scif2_data_a"; +- function = "scif2"; +- }; +- +- hscif0_pins: hscif0 { +- groups = "hscif0_data", "hscif0_ctrl"; +- function = "hscif0"; +- }; +- +- hscif1_pins: hscif1 { +- groups = "hscif1_data_a", "hscif1_ctrl_a"; +- function = "hscif1"; +- }; +- +- hscif2_pins: hscif2 { +- groups = "hscif2_data_a"; +- function = "hscif2"; +- }; +- +- scif0_pins: scif0 { +- groups = "scif0_data"; +- function = "scif0"; +- }; +- +- scif5_pins: scif5 { +- groups = "scif5_data_a"; +- function = "scif5"; +- }; +- +- scif_clk_pins: scif_clk { +- groups = "scif_clk_a"; +- function = "scif_clk"; +- }; +- +- i2c0_pins: i2c0 { +- groups = "i2c0"; +- function = "i2c0"; +- }; +- +- sdhi2_pins: sd2 { +- groups = "sdhi2_data4", "sdhi2_ctrl"; +- function = "sdhi2"; +- power-source = <1800>; +- }; +- +- sdhi3_pins: sd3 { +- groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; +- function = "sdhi3"; +- power-source = <1800>; +- }; +-}; +- +-&scif_clk { +- clock-frequency = <14745600>; +-}; +- +-&scif2 { +- pinctrl-0 = <&scif2_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&sdhi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhi2_pins>; +- bus-width = <4>; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_1p8v>; +- non-removable; +- cap-power-off-card; +- pm-ignore-notify; +- keep-power-in-suspend; +- mmc-pwrseq = <&wlan_pwrseq>; +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- brcmf: bcrmf@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&gpio1>; +- interrupts = <27 IRQ_TYPE_LEVEL_LOW>; +- interrupt-names = "host-wake"; +- }; +-}; +- +-&sdhi3 { +- pinctrl-0 = <&sdhi3_pins>; +- pinctrl-1 = <&sdhi3_pins>; +- pinctrl-names = "default", "state_uhs"; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_1p8v>; +- bus-width = <8>; +- mmc-hs200-1_8v; +- no-sd; +- no-sdio; +- non-removable; +- fixed-emmc-driver-type = <1>; +- status = "okay"; +-}; +- +-&usb2_clksel { +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, +- <&versaclock5 3>, <&usb3s0_clk>; +- status = "okay"; +-}; +- +-&usb3s0_clk { +- clock-frequency = <100000000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/cat875.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/cat875.dtsi +deleted file mode 100644 +index 20f8adc635e7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/cat875.dtsi ++++ /dev/null +@@ -1,65 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Silicon Linux sub board for CAT874 (CAT875) +- * +- * Copyright (C) 2019 Renesas Electronics Corp. +- */ +- +-/ { +- model = "Silicon Linux sub board for CAT874 (CAT875)"; +- +- aliases { +- ethernet0 = &avb; +- }; +-}; +- +-&avb { +- pinctrl-0 = <&avb_pins>; +- pinctrl-names = "default"; +- renesas,no-ether-link; +- phy-handle = <&phy0>; +- phy-mode = "rgmii-id"; +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- interrupt-parent = <&gpio2>; +- interrupts = <21 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&can0 { +- pinctrl-0 = <&can0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-0 = <&can1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&pciec0 { +- status = "okay"; +-}; +- +-&pfc { +- avb_pins: avb { +- mux { +- groups = "avb_mii"; +- function = "avb"; +- }; +- }; +- +- can0_pins: can0 { +- groups = "can0_data"; +- function = "can0"; +- }; +- +- can1_pins: can1 { +- groups = "can1_data"; +- function = "can1"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/hihope-common.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/hihope-common.dtsi +deleted file mode 100644 +index 0c7e6f790590..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/hihope-common.dtsi ++++ /dev/null +@@ -1,382 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and +- * HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts +- * +- * Copyright (C) 2019 Renesas Electronics Corp. +- */ +- +-#include +- +-/ { +- aliases { +- serial0 = &scif2; +- serial1 = &hscif0; +- mmc0 = &sdhi3; +- mmc1 = &sdhi0; +- mmc2 = &sdhi2; +- }; +- +- chosen { +- bootargs = "ignore_loglevel"; +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi0-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi0_con: endpoint { +- remote-endpoint = <&rcar_dw_hdmi0_out>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led1 { +- gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; +- }; +- +- led2 { +- gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; +- }; +- +- led3 { +- gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; +- }; +- +- led4 { +- gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- reg_1p8v: regulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator1 { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sound_card: sound { +- compatible = "audio-graph-card"; +- +- label = "rcar-sound"; +- +- dais = <&rsnd_port>; +- }; +- +- vbus0_usb2: regulator-vbus0-usb2 { +- compatible = "regulator-fixed"; +- +- regulator-name = "USB20_VBUS0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhi0: regulator-vccq-sdhi0 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI0 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- x302_clk: x302-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <33000000>; +- }; +- +- x304_clk: x304-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +-}; +- +-&audio_clk_a { +- clock-frequency = <22579200>; +-}; +- +-&du { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&extal_clk { +- clock-frequency = <16666666>; +-}; +- +-&extalr_clk { +- clock-frequency = <32768>; +-}; +- +-&gpio6 { +- usb1-reset { +- gpio-hog; +- gpios = <10 GPIO_ACTIVE_LOW>; +- output-low; +- line-name = "usb1-reset"; +- }; +-}; +- +-&hdmi0 { +- status = "okay"; +- +- ports { +- port@1 { +- reg = <1>; +- rcar_dw_hdmi0_out: endpoint { +- remote-endpoint = <&hdmi0_con>; +- }; +- }; +- port@2 { +- reg = <2>; +- dw_hdmi0_snd_in: endpoint { +- remote-endpoint = <&rsnd_endpoint>; +- }; +- }; +- }; +-}; +- +-&hscif0 { +- pinctrl-0 = <&hscif0_pins>; +- pinctrl-names = "default"; +- +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&hsusb { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&i2c4 { +- clock-frequency = <400000>; +- status = "okay"; +- +- versaclock5: clock-generator@6a { +- compatible = "idt,5p49v5923"; +- reg = <0x6a>; +- #clock-cells = <1>; +- clocks = <&x304_clk>; +- clock-names = "xin"; +- }; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&pcie_bus_clk { +- clock-frequency = <100000000>; +-}; +- +-&pfc { +- pinctrl-0 = <&scif_clk_pins>; +- pinctrl-names = "default"; +- +- hscif0_pins: hscif0 { +- groups = "hscif0_data", "hscif0_ctrl"; +- function = "hscif0"; +- }; +- +- scif2_pins: scif2 { +- groups = "scif2_data_a"; +- function = "scif2"; +- }; +- +- scif_clk_pins: scif_clk { +- groups = "scif_clk_a"; +- function = "scif_clk"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <3300>; +- }; +- +- sdhi0_pins_uhs: sd0_uhs { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <1800>; +- }; +- +- sdhi2_pins: sd2 { +- groups = "sdhi2_data4", "sdhi2_ctrl"; +- function = "sdhi2"; +- power-source = <1800>; +- }; +- +- sdhi3_pins: sd3 { +- groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; +- function = "sdhi3"; +- power-source = <1800>; +- }; +- +- usb0_pins: usb0 { +- groups = "usb0"; +- function = "usb0"; +- }; +- +- usb1_pins: usb1 { +- mux { +- groups = "usb1"; +- function = "usb1"; +- }; +- +- ovc { +- pins = "GP_6_27"; +- bias-pull-up; +- }; +- }; +- +- usb30_pins: usb30 { +- groups = "usb30"; +- function = "usb30"; +- }; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&scif2 { +- pinctrl-0 = <&scif2_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scif_clk { +- clock-frequency = <14745600>; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-1 = <&sdhi0_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <&vccq_sdhi0>; +- cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- status = "okay"; +-}; +- +-&sdhi2 { +- status = "okay"; +- pinctrl-0 = <&sdhi2_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <&wlan_en_reg>; +- bus-width = <4>; +- non-removable; +- cap-power-off-card; +- keep-power-in-suspend; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1837"; +- reg = <2>; +- interrupt-parent = <&gpio2>; +- interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; +- }; +-}; +- +-&sdhi3 { +- pinctrl-0 = <&sdhi3_pins>; +- pinctrl-1 = <&sdhi3_pins>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_1p8v>; +- bus-width = <8>; +- mmc-hs200-1_8v; +- no-sd; +- no-sdio; +- non-removable; +- fixed-emmc-driver-type = <1>; +- status = "okay"; +-}; +- +-&usb_extal_clk { +- clock-frequency = <50000000>; +-}; +- +-&usb2_phy0 { +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +- +- vbus-supply = <&vbus0_usb2>; +- status = "okay"; +-}; +- +-&usb2_phy1 { +- pinctrl-0 = <&usb1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&usb3_peri0 { +- phys = <&usb3_phy0>; +- phy-names = "usb"; +- +- companion = <&xhci0>; +- +- status = "okay"; +-}; +- +-&usb3_phy0 { +- status = "okay"; +-}; +- +-&usb3s0_clk { +- clock-frequency = <100000000>; +-}; +- +-&xhci0 { +- pinctrl-0 = <&usb30_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/hihope-rev2.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/hihope-rev2.dtsi +deleted file mode 100644 +index 8e2db1d6ca81..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/hihope-rev2.dtsi ++++ /dev/null +@@ -1,86 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2[MN] main board Rev.2.0 common +- * parts +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-#include +-#include "hihope-common.dtsi" +- +-/ { +- leds { +- compatible = "gpio-leds"; +- +- bt_active_led { +- label = "blue:bt"; +- gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "hci0-power"; +- default-state = "off"; +- }; +- +- wlan_active_led { +- label = "yellow:wlan"; +- gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "phy0tx"; +- default-state = "off"; +- }; +- }; +- +- wlan_en_reg: regulator-wlan_en { +- compatible = "regulator-fixed"; +- regulator-name = "wlan-en-regulator"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- startup-delay-us = <70000>; +- +- gpio = <&gpio_expander 1 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&hscif0 { +- bluetooth { +- compatible = "ti,wl1837-st"; +- enable-gpios = <&gpio_expander 2 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&i2c4 { +- gpio_expander: gpio@20 { +- compatible = "onnn,pca9654"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&pfc { +- sound_clk_pins: sound_clk { +- groups = "audio_clk_a_a"; +- function = "audio_clk"; +- }; +-}; +- +-&rcar_sound { +- pinctrl-0 = <&sound_clk_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- /* Single DAI */ +- #sound-dai-cells = <0>; +- +- rsnd_port: port { +- rsnd_endpoint: endpoint { +- remote-endpoint = <&dw_hdmi0_snd_in>; +- +- dai-format = "i2s"; +- bitclock-master = <&rsnd_endpoint>; +- frame-master = <&rsnd_endpoint>; +- +- playback = <&ssi2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/hihope-rev4.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/hihope-rev4.dtsi +deleted file mode 100644 +index 7fc0339a3ac9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/hihope-rev4.dtsi ++++ /dev/null +@@ -1,128 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and +- * HiHope RZ/G2[MN] Rev.3.0/4.0 main board common parts +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-#include +-#include "hihope-common.dtsi" +- +-/ { +- audio_clkout: audio-clkout { +- /* +- * This is same as <&rcar_sound 0> +- * but needed to avoid cs2000/rcar_sound probe dead-lock +- */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <12288000>; +- }; +- +- wlan_en_reg: regulator-wlan_en { +- compatible = "regulator-fixed"; +- regulator-name = "wlan-en-regulator"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- startup-delay-us = <70000>; +- +- gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- x1801_clk: x1801-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +-}; +- +-&hscif0 { +- bluetooth { +- compatible = "ti,wl1837-st"; +- enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&i2c2 { +- pinctrl-0 = <&i2c2_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- cs2000: clk_multiplier@4f { +- #clock-cells = <0>; +- compatible = "cirrus,cs2000-cp"; +- reg = <0x4f>; +- clocks = <&audio_clkout>, <&x1801_clk>; +- clock-names = "clk_in", "ref_clk"; +- +- assigned-clocks = <&cs2000>; +- assigned-clock-rates = <24576000>; /* 1/1 divide */ +- }; +-}; +- +-&pfc { +- i2c2_pins: i2c2 { +- groups = "i2c2_a"; +- function = "i2c2"; +- }; +- +- sound_clk_pins: sound_clk { +- groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clkout_a"; +- function = "audio_clk"; +- }; +- +- sound_pins: sound { +- groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; +- function = "ssi"; +- }; +-}; +- +-&rcar_sound { +- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- /* Single DAI */ +- #sound-dai-cells = <0>; +- +- /* audio_clkout0/1/2/3 */ +- #clock-cells = <1>; +- clock-frequency = <12288000 11289600>; +- +- /* +- * Update to +- * Switch SW2404 should be at position 1 so that clock from +- * CS2000 is connected to AUDIO_CLKB_A +- */ +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&cs2000>, +- <&audio_clk_c>, +- <&cpg CPG_CORE CPG_AUDIO_CLK_I>; +- +- rsnd_port: port { +- rsnd_endpoint: endpoint { +- remote-endpoint = <&dw_hdmi0_snd_in>; +- +- dai-format = "i2s"; +- bitclock-master = <&rsnd_endpoint>; +- frame-master = <&rsnd_endpoint>; +- +- playback = <&ssi2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi +deleted file mode 100644 +index 3771144a2ce4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi ++++ /dev/null +@@ -1,107 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2[HMN] MIPI common parts +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-#define MIPI_OV5645_PARENT_I2C i2c2 +-#define MIPI_IMX219_PARENT_I2C i2c3 +-#include "aistarvision-mipi-adapter-2.1.dtsi" +- +-&csi20 { +- status = "okay"; +- +- ports { +- port@0 { +- csi20_in: endpoint { +- clock-lanes = <0>; +- data-lanes = <1 2>; +- remote-endpoint = <&ov5645_ep>; +- }; +- }; +- }; +-}; +- +-&csi40 { +- status = "okay"; +- +- ports { +- port@0 { +- csi40_in: endpoint { +- clock-lanes = <0>; +- data-lanes = <1 2>; +- remote-endpoint = <&imx219_ep>; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- pinctrl-0 = <&i2c3_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&imx219 { +- port { +- imx219_ep: endpoint { +- clock-lanes = <0>; +- data-lanes = <1 2>; +- link-frequencies = /bits/ 64 <456000000>; +- remote-endpoint = <&csi40_in>; +- }; +- }; +-}; +- +-&ov5645 { +- enable-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; +- +- port { +- ov5645_ep: endpoint { +- clock-lanes = <0>; +- data-lanes = <1 2>; +- remote-endpoint = <&csi20_in>; +- }; +- }; +-}; +- +-&pfc { +- i2c3_pins: i2c3 { +- groups = "i2c3"; +- function = "i2c3"; +- }; +-}; +- +-&vin0 { +- status = "okay"; +-}; +- +-&vin1 { +- status = "okay"; +-}; +- +-&vin2 { +- status = "okay"; +-}; +- +-&vin3 { +- status = "okay"; +-}; +- +-&vin4 { +- status = "okay"; +-}; +- +-&vin5 { +- status = "okay"; +-}; +- +-&vin6 { +- status = "okay"; +-}; +- +-&vin7 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/hihope-rzg2-ex-lvds.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/hihope-rzg2-ex-lvds.dtsi +deleted file mode 100644 +index 40c5e8d6d841..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/hihope-rzg2-ex-lvds.dtsi ++++ /dev/null +@@ -1,52 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the RZ/G2[MN] HiHope sub board LVDS common parts +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-/ { +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm0 0 50000>; +- +- brightness-levels = <0 2 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- }; +-}; +- +-&gpio1 { +- /* +- * When GP1_20 is LOW LVDS0 is connected to the LVDS connector +- * When GP1_20 is HIGH LVDS0 is connected to the LT8918L +- */ +- lvds-connector-en-gpio { +- gpio-hog; +- gpios = <20 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "lvds-connector-en-gpio"; +- }; +-}; +- +-&lvds0 { +- ports { +- port@1 { +- lvds_connector: endpoint { +- }; +- }; +- }; +-}; +- +-&pfc { +- pwm0_pins: pwm0 { +- groups = "pwm0"; +- function = "pwm0"; +- }; +-}; +- +-&pwm0 { +- pinctrl-0 = <&pwm0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/hihope-rzg2-ex.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/hihope-rzg2-ex.dtsi +deleted file mode 100644 +index dde3a07bc417..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/hihope-rzg2-ex.dtsi ++++ /dev/null +@@ -1,93 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the RZ/G2[HMN] HiHope sub board common parts +- * +- * Copyright (C) 2019 Renesas Electronics Corp. +- */ +- +-/ { +- aliases { +- ethernet0 = &avb; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- }; +-}; +- +-&avb { +- pinctrl-0 = <&avb_pins>; +- pinctrl-names = "default"; +- phy-handle = <&phy0>; +- tx-internal-delay-ps = <2000>; +- rx-internal-delay-ps = <1800>; +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- interrupt-parent = <&gpio2>; +- interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&can0 { +- pinctrl-0 = <&can0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-0 = <&can1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&pciec0 { +- status = "okay"; +-}; +- +-&pfc { +- pinctrl-0 = <&scif_clk_pins>; +- pinctrl-names = "default"; +- +- avb_pins: avb { +- mux { +- groups = "avb_link", "avb_mdio", "avb_mii"; +- function = "avb"; +- }; +- +- pins_mdio { +- groups = "avb_mdio"; +- drive-strength = <24>; +- }; +- +- pins_mii_tx { +- pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", +- "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; +- drive-strength = <12>; +- }; +- }; +- +- can0_pins: can0 { +- groups = "can0_data_a"; +- function = "can0"; +- }; +- +- can1_pins: can1 { +- groups = "can1_data"; +- function = "can1"; +- }; +- +- pwm0_pins: pwm0 { +- groups = "pwm0"; +- function = "pwm0"; +- }; +-}; +- +-&pwm0 { +- pinctrl-0 = <&pwm0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-beacon-rzg2m-kit.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-beacon-rzg2m-kit.dts +deleted file mode 100644 +index 3cf2e076940f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-beacon-rzg2m-kit.dts ++++ /dev/null +@@ -1,73 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2020, Compass Electronics Group, LLC +- */ +- +-/dts-v1/; +- +-#include "r8a774a1.dtsi" +-#include "beacon-renesom-som.dtsi" +-#include "beacon-renesom-baseboard.dtsi" +- +-/ { +- model = "Beacon EmbeddedWorks RZ/G2M Development Kit"; +- compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1"; +- +- aliases { +- serial0 = &scif2; +- serial1 = &hscif0; +- serial2 = &hscif1; +- serial3 = &scif0; +- serial4 = &hscif2; +- serial5 = &scif5; +- ethernet0 = &avb; +- mmc0 = &sdhi3; +- mmc1 = &sdhi0; +- mmc2 = &sdhi2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@600000000 { +- device_type = "memory"; +- reg = <0x6 0x00000000 0x0 0x80000000>; +- }; +-}; +- +-&du { +- pinctrl-0 = <&du_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>, +- <&versaclock5 1>, +- <&x302_clk>, +- <&versaclock5 2>; +- clock-names = "du.0", "du.1", "du.2", +- "dclkin.0", "dclkin.1", "dclkin.2"; +-}; +- +-/* Reference versaclock instead of audio_clk_a */ +-&rcar_sound { +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&versaclock6_bb 4>, <&audio_clk_b>, +- <&audio_clk_c>, +- <&cpg CPG_CORE R8A774A1_CLK_S0D4>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts +deleted file mode 100644 +index 06c04c59cc78..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 sub board connected +- * to an Advantech IDK-1110WR 10.1" LVDS panel +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-#include "r8a774a1-hihope-rzg2m-ex.dts" +-#include "hihope-rzg2-ex-lvds.dtsi" +-#include "rzg2-advantech-idk-1110wr-panel.dtsi" +- +-&lvds0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts +deleted file mode 100644 +index 5c91e0d7e67b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts ++++ /dev/null +@@ -1,29 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2M board +- * connected with aistarvision-mipi-v2-adapter board +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a774a1-hihope-rzg2m-ex.dts" +-#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi" +- +-/ { +- model = "HopeRun HiHope RZ/G2M with sub board connected with aistarvision-mipi-v2-adapter board"; +- compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1"; +-}; +- +-/* +- * On RZ/G2M SoC LSI V1.3 CSI40 supports only 4 lane mode. +- * HiHope RZ/G2M Rev.4.0 board is based on LSI V1.3 so disable csi40 and +- * imx219 as the imx219 endpoint driver supports only 2 lane mode. +- */ +-&csi40 { +- status = "disabled"; +-}; +- +-&imx219 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m-ex.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m-ex.dts +deleted file mode 100644 +index a5ca86196a7b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m-ex.dts ++++ /dev/null +@@ -1,21 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 connected to +- * sub board +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-#include "r8a774a1-hihope-rzg2m.dts" +-#include "hihope-rzg2-ex.dtsi" +- +-/ { +- model = "HopeRun HiHope RZ/G2M with sub board"; +- compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m", +- "renesas,r8a774a1"; +-}; +- +-/* SW43 should be OFF, if in ON state SATA port will be activated */ +-&pciec1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dts +deleted file mode 100644 +index c0e9d8ca4a8c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2M Rev.2.0 sub board connected to an +- * Advantech IDK-1110WR 10.1" LVDS panel +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-#include "r8a774a1-hihope-rzg2m-rev2-ex.dts" +-#include "hihope-rzg2-ex-lvds.dtsi" +-#include "rzg2-advantech-idk-1110wr-panel.dtsi" +- +-&lvds0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m-rev2-ex.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m-rev2-ex.dts +deleted file mode 100644 +index 2221cf6aed21..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m-rev2-ex.dts ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2M Rev.2.0 connected to sub board +- * +- * Copyright (C) 2019 Renesas Electronics Corp. +- */ +- +-#include "r8a774a1-hihope-rzg2m-rev2.dts" +-#include "hihope-rzg2-ex.dtsi" +- +-/ { +- model = "HopeRun HiHope RZ/G2M (Rev.2.0) with sub board"; +- compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m", +- "renesas,r8a774a1"; +-}; +- +-/* SW43 should be OFF, if in ON state SATA port will be activated */ +-&pciec1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m-rev2.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m-rev2.dts +deleted file mode 100644 +index bb18f6ee2048..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m-rev2.dts ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2M Rev.2.0 main board +- * +- * Copyright (C) 2019 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a774a1.dtsi" +-#include "hihope-rev2.dtsi" +- +-/ { +- model = "HopeRun HiHope RZ/G2M main board (Rev.2.0) based on r8a774a1"; +- compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x78000000>; +- }; +- +- memory@600000000 { +- device_type = "memory"; +- reg = <0x6 0x00000000 0x0 0x80000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>, +- <&versaclock5 1>, +- <&x302_clk>, +- <&versaclock5 2>; +- clock-names = "du.0", "du.1", "du.2", +- "dclkin.0", "dclkin.1", "dclkin.2"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m.dts +deleted file mode 100644 +index 25ae255de0f2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1-hihope-rzg2m.dts ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 main board +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a774a1.dtsi" +-#include "hihope-rev4.dtsi" +- +-/ { +- model = "HopeRun HiHope RZ/G2M main board based on r8a774a1"; +- compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x78000000>; +- }; +- +- memory@600000000 { +- device_type = "memory"; +- reg = <0x6 0x00000000 0x0 0x80000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>, +- <&versaclock5 1>, +- <&x302_clk>, +- <&versaclock5 2>; +- clock-names = "du.0", "du.1", "du.2", +- "dclkin.0", "dclkin.1", "dclkin.2"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1.dtsi +deleted file mode 100644 +index e70aa5a08740..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774a1.dtsi ++++ /dev/null +@@ -1,2871 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the r8a774a1 SoC +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +- +-#include +-#include +-#include +-#include +- +-#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4 +- +-/ { +- compatible = "renesas,r8a774a1"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &iic_pmic; +- }; +- +- /* +- * The external audio clocks are configured as 0 Hz fixed frequency +- * clocks by default. +- * Boards that provide audio clocks should override them. +- */ +- audio_clk_a: audio_clk_a { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_b: audio_clk_b { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_c: audio_clk_c { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* External CAN clock - to be overridden by boards that provide it */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- cluster0_opp: opp_table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1500000000 { +- opp-hz = /bits/ 64 <1500000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- opp-suspend; +- }; +- }; +- +- cluster1_opp: opp_table1 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&a57_0>; +- }; +- core1 { +- cpu = <&a57_1>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&a53_0>; +- }; +- core1 { +- cpu = <&a53_1>; +- }; +- core2 { +- cpu = <&a53_2>; +- }; +- core3 { +- cpu = <&a53_3>; +- }; +- }; +- }; +- +- a57_0: cpu@0 { +- compatible = "arm,cortex-a57"; +- reg = <0x0>; +- device_type = "cpu"; +- power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; +- next-level-cache = <&L2_CA57>; +- enable-method = "psci"; +- dynamic-power-coefficient = <854>; +- clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; +- operating-points-v2 = <&cluster0_opp>; +- capacity-dmips-mhz = <1024>; +- #cooling-cells = <2>; +- }; +- +- a57_1: cpu@1 { +- compatible = "arm,cortex-a57"; +- reg = <0x1>; +- device_type = "cpu"; +- power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; +- next-level-cache = <&L2_CA57>; +- enable-method = "psci"; +- clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; +- operating-points-v2 = <&cluster0_opp>; +- capacity-dmips-mhz = <1024>; +- #cooling-cells = <2>; +- }; +- +- a53_0: cpu@100 { +- compatible = "arm,cortex-a53"; +- reg = <0x100>; +- device_type = "cpu"; +- power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- #cooling-cells = <2>; +- dynamic-power-coefficient = <277>; +- clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <560>; +- }; +- +- a53_1: cpu@101 { +- compatible = "arm,cortex-a53"; +- reg = <0x101>; +- device_type = "cpu"; +- power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <560>; +- }; +- +- a53_2: cpu@102 { +- compatible = "arm,cortex-a53"; +- reg = <0x102>; +- device_type = "cpu"; +- power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <560>; +- }; +- +- a53_3: cpu@103 { +- compatible = "arm,cortex-a53"; +- reg = <0x103>; +- device_type = "cpu"; +- power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <560>; +- }; +- +- L2_CA57: cache-controller-0 { +- compatible = "cache"; +- power-domains = <&sysc R8A774A1_PD_CA57_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- +- L2_CA53: cache-controller-1 { +- compatible = "cache"; +- power-domains = <&sysc R8A774A1_PD_CA53_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- }; +- +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- extalr_clk: extalr { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- /* External PCIe clock - can be overridden by the board */ +- pcie_bus_clk: pcie_bus { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- pmu_a53 { +- compatible = "arm,cortex-a53-pmu"; +- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; +- }; +- +- pmu_a57 { +- compatible = "arm,cortex-a57-pmu"; +- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&a57_0>, <&a57_1>; +- }; +- +- psci { +- compatible = "arm,psci-1.0", "arm,psci-0.2"; +- method = "smc"; +- }; +- +- /* External SCIF clock - to be overridden by boards that provide it */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a774a1-wdt", +- "renesas,rcar-gen3-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a774a1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 16>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a774a1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 29>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a774a1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 15>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a774a1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 16>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a774a1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 18>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a774a1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- gpio6: gpio@e6055400 { +- compatible = "renesas,gpio-r8a774a1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055400 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 192 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 906>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 906>; +- }; +- +- gpio7: gpio@e6055800 { +- compatible = "renesas,gpio-r8a774a1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055800 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 224 4>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 905>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 905>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a774a1"; +- reg = <0 0xe6060000 0 0x50c>; +- }; +- +- cmt0: timer@e60f0000 { +- compatible = "renesas,r8a774a1-cmt0", +- "renesas,rcar-gen3-cmt0"; +- reg = <0 0xe60f0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 303>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 303>; +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a774a1-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 302>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 302>; +- status = "disabled"; +- }; +- +- cmt2: timer@e6140000 { +- compatible = "renesas,r8a774a1-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6140000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 301>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 301>; +- status = "disabled"; +- }; +- +- cmt3: timer@e6148000 { +- compatible = "renesas,r8a774a1-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6148000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 300>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 300>; +- status = "disabled"; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a774a1-cpg-mssr"; +- reg = <0 0xe6150000 0 0x0bb0>; +- clocks = <&extal_clk>, <&extalr_clk>; +- clock-names = "extal", "extalr"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a774a1-rst"; +- reg = <0 0xe6160000 0 0x018c>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a774a1-sysc"; +- reg = <0 0xe6180000 0 0x0400>; +- #power-domain-cells = <1>; +- }; +- +- tsc: thermal@e6198000 { +- compatible = "renesas,r8a774a1-thermal"; +- reg = <0 0xe6198000 0 0x100>, +- <0 0xe61a0000 0 0x100>, +- <0 0xe61a8000 0 0x100>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 522>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 522>; +- #thermal-sensor-cells = <1>; +- }; +- +- intc_ex: interrupt-controller@e61c0000 { +- compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- tmu0: timer@e61e0000 { +- compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; +- reg = <0 0xe61e0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 125>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 125>; +- status = "disabled"; +- }; +- +- tmu1: timer@e6fc0000 { +- compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; +- reg = <0 0xe6fc0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- status = "disabled"; +- }; +- +- tmu2: timer@e6fd0000 { +- compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; +- reg = <0 0xe6fd0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 123>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 123>; +- status = "disabled"; +- }; +- +- tmu3: timer@e6fe0000 { +- compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; +- reg = <0 0xe6fe0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 122>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 122>; +- status = "disabled"; +- }; +- +- tmu4: timer@ffc00000 { +- compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; +- reg = <0 0xffc00000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 121>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 121>; +- status = "disabled"; +- }; +- +- i2c0: i2c@e6500000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774a1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6500000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- dmas = <&dmac1 0x91>, <&dmac1 0x90>, +- <&dmac2 0x91>, <&dmac2 0x90>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6508000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774a1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- dmas = <&dmac1 0x93>, <&dmac1 0x92>, +- <&dmac2 0x93>, <&dmac2 0x92>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6510000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774a1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6510000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- dmas = <&dmac1 0x95>, <&dmac1 0x94>, +- <&dmac2 0x95>, <&dmac2 0x94>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e66d0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774a1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- dmas = <&dmac0 0x97>, <&dmac0 0x96>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e66d8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774a1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 927>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 927>; +- dmas = <&dmac0 0x99>, <&dmac0 0x98>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c5: i2c@e66e0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774a1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 919>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 919>; +- dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c6: i2c@e66e8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774a1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 918>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 918>; +- dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- iic_pmic: i2c@e60b0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a774a1", +- "renesas,rcar-gen3-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe60b0000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 926>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 926>; +- dmas = <&dmac0 0x11>, <&dmac0 0x10>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- hscif0: serial@e6540000 { +- compatible = "renesas,hscif-r8a774a1", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6540000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 520>, +- <&cpg CPG_CORE R8A774A1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x31>, <&dmac1 0x30>, +- <&dmac2 0x31>, <&dmac2 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 520>; +- status = "disabled"; +- }; +- +- hscif1: serial@e6550000 { +- compatible = "renesas,hscif-r8a774a1", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6550000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 519>, +- <&cpg CPG_CORE R8A774A1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x33>, <&dmac1 0x32>, +- <&dmac2 0x33>, <&dmac2 0x32>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 519>; +- status = "disabled"; +- }; +- +- hscif2: serial@e6560000 { +- compatible = "renesas,hscif-r8a774a1", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6560000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 518>, +- <&cpg CPG_CORE R8A774A1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x35>, <&dmac1 0x34>, +- <&dmac2 0x35>, <&dmac2 0x34>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 518>; +- status = "disabled"; +- }; +- +- hscif3: serial@e66a0000 { +- compatible = "renesas,hscif-r8a774a1", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66a0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 517>, +- <&cpg CPG_CORE R8A774A1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x37>, <&dmac0 0x36>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 517>; +- status = "disabled"; +- }; +- +- hscif4: serial@e66b0000 { +- compatible = "renesas,hscif-r8a774a1", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66b0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 516>, +- <&cpg CPG_CORE R8A774A1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x39>, <&dmac0 0x38>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 516>; +- status = "disabled"; +- }; +- +- hsusb: usb@e6590000 { +- compatible = "renesas,usbhs-r8a774a1", +- "renesas,rcar-gen3-usbhs"; +- reg = <0 0xe6590000 0 0x200>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; +- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, +- <&usb_dmac1 0>, <&usb_dmac1 1>; +- dma-names = "ch0", "ch1", "ch2", "ch3"; +- renesas,buswait = <11>; +- phys = <&usb2_phy0 3>; +- phy-names = "usb"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 704>, <&cpg 703>; +- status = "disabled"; +- }; +- +- usb2_clksel: clock-controller@e6590630 { +- compatible = "renesas,r8a774a1-rcar-usb2-clock-sel", +- "renesas,rcar-gen3-usb2-clock-sel"; +- reg = <0 0xe6590630 0 0x02>; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, +- <&usb_extal_clk>, <&usb3s0_clk>; +- clock-names = "ehci_ohci", "hs-usb-if", +- "usb_extal", "usb_xtal"; +- #clock-cells = <0>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- reset-names = "ehci_ohci", "hs-usb-if"; +- status = "disabled"; +- }; +- +- usb_dmac0: dma-controller@e65a0000 { +- compatible = "renesas,r8a774a1-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65a0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 330>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 330>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac1: dma-controller@e65b0000 { +- compatible = "renesas,r8a774a1-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65b0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 331>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 331>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb3_phy0: usb-phy@e65ee000 { +- compatible = "renesas,r8a774a1-usb3-phy", +- "renesas,rcar-gen3-usb3-phy"; +- reg = <0 0xe65ee000 0 0x90>; +- clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, +- <&usb_extal_clk>; +- clock-names = "usb3-if", "usb3s_clk", "usb_extal"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a774a1", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, +- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, +- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, +- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, +- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, +- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, +- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, +- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; +- }; +- +- dmac1: dma-controller@e7300000 { +- compatible = "renesas,dmac-r8a774a1", +- "renesas,rcar-dmac"; +- reg = <0 0xe7300000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, +- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, +- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, +- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, +- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, +- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, +- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, +- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; +- }; +- +- dmac2: dma-controller@e7310000 { +- compatible = "renesas,dmac-r8a774a1", +- "renesas,rcar-dmac"; +- reg = <0 0xe7310000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 217>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 217>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, +- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, +- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, +- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, +- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, +- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, +- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, +- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; +- }; +- +- ipmmu_ds0: iommu@e6740000 { +- compatible = "renesas,ipmmu-r8a774a1"; +- reg = <0 0xe6740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 0>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_ds1: iommu@e7740000 { +- compatible = "renesas,ipmmu-r8a774a1"; +- reg = <0 0xe7740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 1>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_hc: iommu@e6570000 { +- compatible = "renesas,ipmmu-r8a774a1"; +- reg = <0 0xe6570000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 2>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mm: iommu@e67b0000 { +- compatible = "renesas,ipmmu-r8a774a1"; +- reg = <0 0xe67b0000 0 0x1000>; +- interrupts = , +- ; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mp: iommu@ec670000 { +- compatible = "renesas,ipmmu-r8a774a1"; +- reg = <0 0xec670000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 4>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_pv0: iommu@fd800000 { +- compatible = "renesas,ipmmu-r8a774a1"; +- reg = <0 0xfd800000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 5>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_pv1: iommu@fd950000 { +- compatible = "renesas,ipmmu-r8a774a1"; +- reg = <0 0xfd950000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 6>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vc0: iommu@fe6b0000 { +- compatible = "renesas,ipmmu-r8a774a1"; +- reg = <0 0xfe6b0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 8>; +- power-domains = <&sysc R8A774A1_PD_A3VC>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vi0: iommu@febd0000 { +- compatible = "renesas,ipmmu-r8a774a1"; +- reg = <0 0xfebd0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 9>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a774a1", +- "renesas,etheravb-rcar-gen3"; +- reg = <0 0xe6800000 0 0x800>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15", +- "ch16", "ch17", "ch18", "ch19", +- "ch20", "ch21", "ch22", "ch23", +- "ch24"; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- phy-mode = "rgmii"; +- rx-internal-delay-ps = <0>; +- tx-internal-delay-ps = <0>; +- iommus = <&ipmmu_ds0 16>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- can0: can@e6c30000 { +- compatible = "renesas,can-r8a774a1", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c30000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>, +- <&cpg CPG_CORE R8A774A1_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- status = "disabled"; +- }; +- +- can1: can@e6c38000 { +- compatible = "renesas,can-r8a774a1", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c38000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>, +- <&cpg CPG_CORE R8A774A1_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- status = "disabled"; +- }; +- +- canfd: can@e66c0000 { +- compatible = "renesas,r8a774a1-canfd", +- "renesas,rcar-gen3-canfd"; +- reg = <0 0xe66c0000 0 0x8000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 914>, +- <&cpg CPG_CORE R8A774A1_CLK_CANFD>, +- <&can_clk>; +- clock-names = "fck", "canfd", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 914>; +- status = "disabled"; +- +- channel0 { +- status = "disabled"; +- }; +- +- channel1 { +- status = "disabled"; +- }; +- }; +- +- pwm0: pwm@e6e30000 { +- compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; +- reg = <0 0xe6e30000 0 0x8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm1: pwm@e6e31000 { +- compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; +- reg = <0 0xe6e31000 0 0x8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm2: pwm@e6e32000 { +- compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; +- reg = <0 0xe6e32000 0 0x8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm3: pwm@e6e33000 { +- compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; +- reg = <0 0xe6e33000 0 0x8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm4: pwm@e6e34000 { +- compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; +- reg = <0 0xe6e34000 0 0x8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm5: pwm@e6e35000 { +- compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; +- reg = <0 0xe6e35000 0 0x8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm6: pwm@e6e36000 { +- compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; +- reg = <0 0xe6e36000 0 0x8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a774a1", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e60000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>, +- <&cpg CPG_CORE R8A774A1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x51>, <&dmac1 0x50>, +- <&dmac2 0x51>, <&dmac2 0x50>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a774a1", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e68000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>, +- <&cpg CPG_CORE R8A774A1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x53>, <&dmac1 0x52>, +- <&dmac2 0x53>, <&dmac2 0x52>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e88000 { +- compatible = "renesas,scif-r8a774a1", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e88000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 310>, +- <&cpg CPG_CORE R8A774A1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x13>, <&dmac1 0x12>, +- <&dmac2 0x13>, <&dmac2 0x12>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 310>; +- status = "disabled"; +- }; +- +- scif3: serial@e6c50000 { +- compatible = "renesas,scif-r8a774a1", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c50000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>, +- <&cpg CPG_CORE R8A774A1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x57>, <&dmac0 0x56>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scif4: serial@e6c40000 { +- compatible = "renesas,scif-r8a774a1", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c40000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>, +- <&cpg CPG_CORE R8A774A1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x59>, <&dmac0 0x58>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- scif5: serial@e6f30000 { +- compatible = "renesas,scif-r8a774a1", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6f30000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 202>, +- <&cpg CPG_CORE R8A774A1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, +- <&dmac2 0x5b>, <&dmac2 0x5a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 202>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e90000 { +- compatible = "renesas,msiof-r8a774a1", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6e90000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 211>; +- dmas = <&dmac1 0x41>, <&dmac1 0x40>, +- <&dmac2 0x41>, <&dmac2 0x40>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 211>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6ea0000 { +- compatible = "renesas,msiof-r8a774a1", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6ea0000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 210>; +- dmas = <&dmac1 0x43>, <&dmac1 0x42>, +- <&dmac2 0x43>, <&dmac2 0x42>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 210>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6c00000 { +- compatible = "renesas,msiof-r8a774a1", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c00000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 209>; +- dmas = <&dmac0 0x45>, <&dmac0 0x44>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 209>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof3: spi@e6c10000 { +- compatible = "renesas,msiof-r8a774a1", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c10000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 208>; +- dmas = <&dmac0 0x47>, <&dmac0 0x46>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 208>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a774a1"; +- reg = <0 0xe6ef0000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 811>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 811>; +- renesas,id = <0>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin0csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin0>; +- }; +- vin0csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin0>; +- }; +- }; +- }; +- }; +- +- vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a774a1"; +- reg = <0 0xe6ef1000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 810>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 810>; +- renesas,id = <1>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin1csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin1>; +- }; +- vin1csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin1>; +- }; +- }; +- }; +- }; +- +- vin2: video@e6ef2000 { +- compatible = "renesas,vin-r8a774a1"; +- reg = <0 0xe6ef2000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 809>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 809>; +- renesas,id = <2>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin2csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin2>; +- }; +- vin2csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin2>; +- }; +- }; +- }; +- }; +- +- vin3: video@e6ef3000 { +- compatible = "renesas,vin-r8a774a1"; +- reg = <0 0xe6ef3000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 808>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 808>; +- renesas,id = <3>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin3csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin3>; +- }; +- vin3csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin3>; +- }; +- }; +- }; +- }; +- +- vin4: video@e6ef4000 { +- compatible = "renesas,vin-r8a774a1"; +- reg = <0 0xe6ef4000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 807>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 807>; +- renesas,id = <4>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin4csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin4>; +- }; +- vin4csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin4>; +- }; +- }; +- }; +- }; +- +- vin5: video@e6ef5000 { +- compatible = "renesas,vin-r8a774a1"; +- reg = <0 0xe6ef5000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 806>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 806>; +- renesas,id = <5>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin5csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin5>; +- }; +- vin5csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin5>; +- }; +- }; +- }; +- }; +- +- vin6: video@e6ef6000 { +- compatible = "renesas,vin-r8a774a1"; +- reg = <0 0xe6ef6000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 805>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 805>; +- renesas,id = <6>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin6csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin6>; +- }; +- vin6csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin6>; +- }; +- }; +- }; +- }; +- +- vin7: video@e6ef7000 { +- compatible = "renesas,vin-r8a774a1"; +- reg = <0 0xe6ef7000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 804>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 804>; +- renesas,id = <7>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin7csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin7>; +- }; +- vin7csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin7>; +- }; +- }; +- }; +- }; +- +- rcar_sound: sound@ec500000 { +- /* +- * #sound-dai-cells is required +- * +- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; +- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; +- */ +- /* +- * #clock-cells is required for audio_clkout0/1/2/3 +- * +- * clkout : #clock-cells = <0>; <&rcar_sound>; +- * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; +- */ +- compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; +- reg = <0 0xec500000 0 0x1000>, /* SCU */ +- <0 0xec5a0000 0 0x100>, /* ADG */ +- <0 0xec540000 0 0x1000>, /* SSIU */ +- <0 0xec541000 0 0x280>, /* SSI */ +- <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ +- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; +- +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&audio_clk_b>, +- <&audio_clk_c>, +- <&cpg CPG_CORE R8A774A1_CLK_S0D4>; +- clock-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0", +- "src.9", "src.8", "src.7", "src.6", +- "src.5", "src.4", "src.3", "src.2", +- "src.1", "src.0", +- "mix.1", "mix.0", +- "ctu.1", "ctu.0", +- "dvc.0", "dvc.1", +- "clk_a", "clk_b", "clk_c", "clk_i"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 1005>, +- <&cpg 1006>, <&cpg 1007>, +- <&cpg 1008>, <&cpg 1009>, +- <&cpg 1010>, <&cpg 1011>, +- <&cpg 1012>, <&cpg 1013>, +- <&cpg 1014>, <&cpg 1015>; +- reset-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0"; +- status = "disabled"; +- +- rcar_sound,ctu { +- ctu00: ctu-0 { }; +- ctu01: ctu-1 { }; +- ctu02: ctu-2 { }; +- ctu03: ctu-3 { }; +- ctu10: ctu-4 { }; +- ctu11: ctu-5 { }; +- ctu12: ctu-6 { }; +- ctu13: ctu-7 { }; +- }; +- +- rcar_sound,dvc { +- dvc0: dvc-0 { +- dmas = <&audma1 0xbc>; +- dma-names = "tx"; +- }; +- dvc1: dvc-1 { +- dmas = <&audma1 0xbe>; +- dma-names = "tx"; +- }; +- }; +- +- rcar_sound,mix { +- mix0: mix-0 { }; +- mix1: mix-1 { }; +- }; +- +- rcar_sound,src { +- src0: src-0 { +- interrupts = ; +- dmas = <&audma0 0x85>, <&audma1 0x9a>; +- dma-names = "rx", "tx"; +- }; +- src1: src-1 { +- interrupts = ; +- dmas = <&audma0 0x87>, <&audma1 0x9c>; +- dma-names = "rx", "tx"; +- }; +- src2: src-2 { +- interrupts = ; +- dmas = <&audma0 0x89>, <&audma1 0x9e>; +- dma-names = "rx", "tx"; +- }; +- src3: src-3 { +- interrupts = ; +- dmas = <&audma0 0x8b>, <&audma1 0xa0>; +- dma-names = "rx", "tx"; +- }; +- src4: src-4 { +- interrupts = ; +- dmas = <&audma0 0x8d>, <&audma1 0xb0>; +- dma-names = "rx", "tx"; +- }; +- src5: src-5 { +- interrupts = ; +- dmas = <&audma0 0x8f>, <&audma1 0xb2>; +- dma-names = "rx", "tx"; +- }; +- src6: src-6 { +- interrupts = ; +- dmas = <&audma0 0x91>, <&audma1 0xb4>; +- dma-names = "rx", "tx"; +- }; +- src7: src-7 { +- interrupts = ; +- dmas = <&audma0 0x93>, <&audma1 0xb6>; +- dma-names = "rx", "tx"; +- }; +- src8: src-8 { +- interrupts = ; +- dmas = <&audma0 0x95>, <&audma1 0xb8>; +- dma-names = "rx", "tx"; +- }; +- src9: src-9 { +- interrupts = ; +- dmas = <&audma0 0x97>, <&audma1 0xba>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssi { +- ssi0: ssi-0 { +- interrupts = ; +- dmas = <&audma0 0x01>, <&audma1 0x02>; +- dma-names = "rx", "tx"; +- }; +- ssi1: ssi-1 { +- interrupts = ; +- dmas = <&audma0 0x03>, <&audma1 0x04>; +- dma-names = "rx", "tx"; +- }; +- ssi2: ssi-2 { +- interrupts = ; +- dmas = <&audma0 0x05>, <&audma1 0x06>; +- dma-names = "rx", "tx"; +- }; +- ssi3: ssi-3 { +- interrupts = ; +- dmas = <&audma0 0x07>, <&audma1 0x08>; +- dma-names = "rx", "tx"; +- }; +- ssi4: ssi-4 { +- interrupts = ; +- dmas = <&audma0 0x09>, <&audma1 0x0a>; +- dma-names = "rx", "tx"; +- }; +- ssi5: ssi-5 { +- interrupts = ; +- dmas = <&audma0 0x0b>, <&audma1 0x0c>; +- dma-names = "rx", "tx"; +- }; +- ssi6: ssi-6 { +- interrupts = ; +- dmas = <&audma0 0x0d>, <&audma1 0x0e>; +- dma-names = "rx", "tx"; +- }; +- ssi7: ssi-7 { +- interrupts = ; +- dmas = <&audma0 0x0f>, <&audma1 0x10>; +- dma-names = "rx", "tx"; +- }; +- ssi8: ssi-8 { +- interrupts = ; +- dmas = <&audma0 0x11>, <&audma1 0x12>; +- dma-names = "rx", "tx"; +- }; +- ssi9: ssi-9 { +- interrupts = ; +- dmas = <&audma0 0x13>, <&audma1 0x14>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssiu { +- ssiu00: ssiu-0 { +- dmas = <&audma0 0x15>, <&audma1 0x16>; +- dma-names = "rx", "tx"; +- }; +- ssiu01: ssiu-1 { +- dmas = <&audma0 0x35>, <&audma1 0x36>; +- dma-names = "rx", "tx"; +- }; +- ssiu02: ssiu-2 { +- dmas = <&audma0 0x37>, <&audma1 0x38>; +- dma-names = "rx", "tx"; +- }; +- ssiu03: ssiu-3 { +- dmas = <&audma0 0x47>, <&audma1 0x48>; +- dma-names = "rx", "tx"; +- }; +- ssiu04: ssiu-4 { +- dmas = <&audma0 0x3F>, <&audma1 0x40>; +- dma-names = "rx", "tx"; +- }; +- ssiu05: ssiu-5 { +- dmas = <&audma0 0x43>, <&audma1 0x44>; +- dma-names = "rx", "tx"; +- }; +- ssiu06: ssiu-6 { +- dmas = <&audma0 0x4F>, <&audma1 0x50>; +- dma-names = "rx", "tx"; +- }; +- ssiu07: ssiu-7 { +- dmas = <&audma0 0x53>, <&audma1 0x54>; +- dma-names = "rx", "tx"; +- }; +- ssiu10: ssiu-8 { +- dmas = <&audma0 0x49>, <&audma1 0x4a>; +- dma-names = "rx", "tx"; +- }; +- ssiu11: ssiu-9 { +- dmas = <&audma0 0x4B>, <&audma1 0x4C>; +- dma-names = "rx", "tx"; +- }; +- ssiu12: ssiu-10 { +- dmas = <&audma0 0x57>, <&audma1 0x58>; +- dma-names = "rx", "tx"; +- }; +- ssiu13: ssiu-11 { +- dmas = <&audma0 0x59>, <&audma1 0x5A>; +- dma-names = "rx", "tx"; +- }; +- ssiu14: ssiu-12 { +- dmas = <&audma0 0x5F>, <&audma1 0x60>; +- dma-names = "rx", "tx"; +- }; +- ssiu15: ssiu-13 { +- dmas = <&audma0 0xC3>, <&audma1 0xC4>; +- dma-names = "rx", "tx"; +- }; +- ssiu16: ssiu-14 { +- dmas = <&audma0 0xC7>, <&audma1 0xC8>; +- dma-names = "rx", "tx"; +- }; +- ssiu17: ssiu-15 { +- dmas = <&audma0 0xCB>, <&audma1 0xCC>; +- dma-names = "rx", "tx"; +- }; +- ssiu20: ssiu-16 { +- dmas = <&audma0 0x63>, <&audma1 0x64>; +- dma-names = "rx", "tx"; +- }; +- ssiu21: ssiu-17 { +- dmas = <&audma0 0x67>, <&audma1 0x68>; +- dma-names = "rx", "tx"; +- }; +- ssiu22: ssiu-18 { +- dmas = <&audma0 0x6B>, <&audma1 0x6C>; +- dma-names = "rx", "tx"; +- }; +- ssiu23: ssiu-19 { +- dmas = <&audma0 0x6D>, <&audma1 0x6E>; +- dma-names = "rx", "tx"; +- }; +- ssiu24: ssiu-20 { +- dmas = <&audma0 0xCF>, <&audma1 0xCE>; +- dma-names = "rx", "tx"; +- }; +- ssiu25: ssiu-21 { +- dmas = <&audma0 0xEB>, <&audma1 0xEC>; +- dma-names = "rx", "tx"; +- }; +- ssiu26: ssiu-22 { +- dmas = <&audma0 0xED>, <&audma1 0xEE>; +- dma-names = "rx", "tx"; +- }; +- ssiu27: ssiu-23 { +- dmas = <&audma0 0xEF>, <&audma1 0xF0>; +- dma-names = "rx", "tx"; +- }; +- ssiu30: ssiu-24 { +- dmas = <&audma0 0x6f>, <&audma1 0x70>; +- dma-names = "rx", "tx"; +- }; +- ssiu31: ssiu-25 { +- dmas = <&audma0 0x21>, <&audma1 0x22>; +- dma-names = "rx", "tx"; +- }; +- ssiu32: ssiu-26 { +- dmas = <&audma0 0x23>, <&audma1 0x24>; +- dma-names = "rx", "tx"; +- }; +- ssiu33: ssiu-27 { +- dmas = <&audma0 0x25>, <&audma1 0x26>; +- dma-names = "rx", "tx"; +- }; +- ssiu34: ssiu-28 { +- dmas = <&audma0 0x27>, <&audma1 0x28>; +- dma-names = "rx", "tx"; +- }; +- ssiu35: ssiu-29 { +- dmas = <&audma0 0x29>, <&audma1 0x2A>; +- dma-names = "rx", "tx"; +- }; +- ssiu36: ssiu-30 { +- dmas = <&audma0 0x2B>, <&audma1 0x2C>; +- dma-names = "rx", "tx"; +- }; +- ssiu37: ssiu-31 { +- dmas = <&audma0 0x2D>, <&audma1 0x2E>; +- dma-names = "rx", "tx"; +- }; +- ssiu40: ssiu-32 { +- dmas = <&audma0 0x71>, <&audma1 0x72>; +- dma-names = "rx", "tx"; +- }; +- ssiu41: ssiu-33 { +- dmas = <&audma0 0x17>, <&audma1 0x18>; +- dma-names = "rx", "tx"; +- }; +- ssiu42: ssiu-34 { +- dmas = <&audma0 0x19>, <&audma1 0x1A>; +- dma-names = "rx", "tx"; +- }; +- ssiu43: ssiu-35 { +- dmas = <&audma0 0x1B>, <&audma1 0x1C>; +- dma-names = "rx", "tx"; +- }; +- ssiu44: ssiu-36 { +- dmas = <&audma0 0x1D>, <&audma1 0x1E>; +- dma-names = "rx", "tx"; +- }; +- ssiu45: ssiu-37 { +- dmas = <&audma0 0x1F>, <&audma1 0x20>; +- dma-names = "rx", "tx"; +- }; +- ssiu46: ssiu-38 { +- dmas = <&audma0 0x31>, <&audma1 0x32>; +- dma-names = "rx", "tx"; +- }; +- ssiu47: ssiu-39 { +- dmas = <&audma0 0x33>, <&audma1 0x34>; +- dma-names = "rx", "tx"; +- }; +- ssiu50: ssiu-40 { +- dmas = <&audma0 0x73>, <&audma1 0x74>; +- dma-names = "rx", "tx"; +- }; +- ssiu60: ssiu-41 { +- dmas = <&audma0 0x75>, <&audma1 0x76>; +- dma-names = "rx", "tx"; +- }; +- ssiu70: ssiu-42 { +- dmas = <&audma0 0x79>, <&audma1 0x7a>; +- dma-names = "rx", "tx"; +- }; +- ssiu80: ssiu-43 { +- dmas = <&audma0 0x7b>, <&audma1 0x7c>; +- dma-names = "rx", "tx"; +- }; +- ssiu90: ssiu-44 { +- dmas = <&audma0 0x7d>, <&audma1 0x7e>; +- dma-names = "rx", "tx"; +- }; +- ssiu91: ssiu-45 { +- dmas = <&audma0 0x7F>, <&audma1 0x80>; +- dma-names = "rx", "tx"; +- }; +- ssiu92: ssiu-46 { +- dmas = <&audma0 0x81>, <&audma1 0x82>; +- dma-names = "rx", "tx"; +- }; +- ssiu93: ssiu-47 { +- dmas = <&audma0 0x83>, <&audma1 0x84>; +- dma-names = "rx", "tx"; +- }; +- ssiu94: ssiu-48 { +- dmas = <&audma0 0xA3>, <&audma1 0xA4>; +- dma-names = "rx", "tx"; +- }; +- ssiu95: ssiu-49 { +- dmas = <&audma0 0xA5>, <&audma1 0xA6>; +- dma-names = "rx", "tx"; +- }; +- ssiu96: ssiu-50 { +- dmas = <&audma0 0xA7>, <&audma1 0xA8>; +- dma-names = "rx", "tx"; +- }; +- ssiu97: ssiu-51 { +- dmas = <&audma0 0xA9>, <&audma1 0xAA>; +- dma-names = "rx", "tx"; +- }; +- }; +- }; +- +- audma0: dma-controller@ec700000 { +- compatible = "renesas,dmac-r8a774a1", +- "renesas,rcar-dmac"; +- reg = <0 0xec700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 502>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 502>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, +- <&ipmmu_mp 2>, <&ipmmu_mp 3>, +- <&ipmmu_mp 4>, <&ipmmu_mp 5>, +- <&ipmmu_mp 6>, <&ipmmu_mp 7>, +- <&ipmmu_mp 8>, <&ipmmu_mp 9>, +- <&ipmmu_mp 10>, <&ipmmu_mp 11>, +- <&ipmmu_mp 12>, <&ipmmu_mp 13>, +- <&ipmmu_mp 14>, <&ipmmu_mp 15>; +- }; +- +- audma1: dma-controller@ec720000 { +- compatible = "renesas,dmac-r8a774a1", +- "renesas,rcar-dmac"; +- reg = <0 0xec720000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 501>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 501>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, +- <&ipmmu_mp 18>, <&ipmmu_mp 19>, +- <&ipmmu_mp 20>, <&ipmmu_mp 21>, +- <&ipmmu_mp 22>, <&ipmmu_mp 23>, +- <&ipmmu_mp 24>, <&ipmmu_mp 25>, +- <&ipmmu_mp 26>, <&ipmmu_mp 27>, +- <&ipmmu_mp 28>, <&ipmmu_mp 29>, +- <&ipmmu_mp 30>, <&ipmmu_mp 31>; +- }; +- +- xhci0: usb@ee000000 { +- compatible = "renesas,xhci-r8a774a1", +- "renesas,rcar-gen3-xhci"; +- reg = <0 0xee000000 0 0xc00>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- status = "disabled"; +- }; +- +- usb3_peri0: usb@ee020000 { +- compatible = "renesas,r8a774a1-usb3-peri", +- "renesas,rcar-gen3-usb3-peri"; +- reg = <0 0xee020000 0 0x400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- status = "disabled"; +- }; +- +- ohci0: usb@ee080000 { +- compatible = "generic-ohci"; +- reg = <0 0xee080000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- ohci1: usb@ee0a0000 { +- compatible = "generic-ohci"; +- reg = <0 0xee0a0000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 702>; +- phys = <&usb2_phy1 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- status = "disabled"; +- }; +- +- ehci0: usb@ee080100 { +- compatible = "generic-ehci"; +- reg = <0 0xee080100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 2>; +- phy-names = "usb"; +- companion = <&ohci0>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- ehci1: usb@ee0a0100 { +- compatible = "generic-ehci"; +- reg = <0 0xee0a0100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 702>; +- phys = <&usb2_phy1 2>; +- phy-names = "usb"; +- companion = <&ohci1>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- status = "disabled"; +- }; +- +- usb2_phy0: usb-phy@ee080200 { +- compatible = "renesas,usb2-phy-r8a774a1", +- "renesas,rcar-gen3-usb2-phy"; +- reg = <0 0xee080200 0 0x700>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- usb2_phy1: usb-phy@ee0a0200 { +- compatible = "renesas,usb2-phy-r8a774a1", +- "renesas,rcar-gen3-usb2-phy"; +- reg = <0 0xee0a0200 0 0x700>; +- clocks = <&cpg CPG_MOD 702>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a774a1", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee100000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ee120000 { +- compatible = "renesas,sdhi-r8a774a1", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee120000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 313>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 313>; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a774a1", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee140000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 312>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 312>; +- status = "disabled"; +- }; +- +- sdhi3: mmc@ee160000 { +- compatible = "renesas,sdhi-r8a774a1", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee160000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 311>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 311>; +- status = "disabled"; +- }; +- +- rpc: spi@ee200000 { +- compatible = "renesas,r8a774a1-rpc-if", +- "renesas,rcar-gen3-rpc-if"; +- reg = <0 0xee200000 0 0x200>, +- <0 0x08000000 0 0x4000000>, +- <0 0xee208000 0 0x100>; +- reg-names = "regs", "dirmap", "wbuf"; +- interrupts = ; +- clocks = <&cpg CPG_MOD 917>; +- clock-names = "rpc"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 917>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1010000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x0 0xf1010000 0 0x1000>, +- <0x0 0xf1020000 0 0x20000>, +- <0x0 0xf1040000 0 0x20000>, +- <0x0 0xf1060000 0 0x20000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- pciec0: pcie@fe000000 { +- compatible = "renesas,pcie-r8a774a1", +- "renesas,pcie-rcar-gen3"; +- reg = <0 0xfe000000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, +- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, +- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, +- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 319>; +- status = "disabled"; +- }; +- +- pciec1: pcie@ee800000 { +- compatible = "renesas,pcie-r8a774a1", +- "renesas,pcie-rcar-gen3"; +- reg = <0 0xee800000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, +- <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, +- <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, +- <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 318>; +- status = "disabled"; +- }; +- +- pciec0_ep: pcie-ep@fe000000 { +- compatible = "renesas,r8a774a1-pcie-ep", +- "renesas,rcar-gen3-pcie-ep"; +- reg = <0x0 0xfe000000 0 0x80000>, +- <0x0 0xfe100000 0 0x100000>, +- <0x0 0xfe200000 0 0x200000>, +- <0x0 0x30000000 0 0x8000000>, +- <0x0 0x38000000 0 0x8000000>; +- reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 319>; +- clock-names = "pcie"; +- resets = <&cpg 319>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pciec1_ep: pcie-ep@ee800000 { +- compatible = "renesas,r8a774a1-pcie-ep", +- "renesas,rcar-gen3-pcie-ep"; +- reg = <0x0 0xee800000 0 0x80000>, +- <0x0 0xee900000 0 0x100000>, +- <0x0 0xeea00000 0 0x200000>, +- <0x0 0xc0000000 0 0x8000000>, +- <0x0 0xc8000000 0 0x8000000>; +- reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 318>; +- clock-names = "pcie"; +- resets = <&cpg 318>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- fdp1@fe940000 { +- compatible = "renesas,fdp1"; +- reg = <0 0xfe940000 0 0x2400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 119>; +- power-domains = <&sysc R8A774A1_PD_A3VC>; +- resets = <&cpg 119>; +- renesas,fcp = <&fcpf0>; +- }; +- +- fcpf0: fcp@fe950000 { +- compatible = "renesas,fcpf"; +- reg = <0 0xfe950000 0 0x200>; +- clocks = <&cpg CPG_MOD 615>; +- power-domains = <&sysc R8A774A1_PD_A3VC>; +- resets = <&cpg 615>; +- }; +- +- fcpvb0: fcp@fe96f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe96f000 0 0x200>; +- clocks = <&cpg CPG_MOD 607>; +- power-domains = <&sysc R8A774A1_PD_A3VC>; +- resets = <&cpg 607>; +- }; +- +- fcpvd0: fcp@fea27000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea27000 0 0x200>; +- clocks = <&cpg CPG_MOD 603>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 603>; +- iommus = <&ipmmu_vi0 8>; +- }; +- +- fcpvd1: fcp@fea2f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea2f000 0 0x200>; +- clocks = <&cpg CPG_MOD 602>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 602>; +- iommus = <&ipmmu_vi0 9>; +- }; +- +- fcpvd2: fcp@fea37000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea37000 0 0x200>; +- clocks = <&cpg CPG_MOD 601>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 601>; +- iommus = <&ipmmu_vi0 10>; +- }; +- +- fcpvi0: fcp@fe9af000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe9af000 0 0x200>; +- clocks = <&cpg CPG_MOD 611>; +- power-domains = <&sysc R8A774A1_PD_A3VC>; +- resets = <&cpg 611>; +- iommus = <&ipmmu_vc0 19>; +- }; +- +- vspb: vsp@fe960000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe960000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 626>; +- power-domains = <&sysc R8A774A1_PD_A3VC>; +- resets = <&cpg 626>; +- +- renesas,fcp = <&fcpvb0>; +- }; +- +- vspd0: vsp@fea20000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea20000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 623>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 623>; +- +- renesas,fcp = <&fcpvd0>; +- }; +- +- vspd1: vsp@fea28000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea28000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 622>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 622>; +- +- renesas,fcp = <&fcpvd1>; +- }; +- +- vspd2: vsp@fea30000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea30000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 621>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 621>; +- +- renesas,fcp = <&fcpvd2>; +- }; +- +- vspi0: vsp@fe9a0000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe9a0000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 631>; +- power-domains = <&sysc R8A774A1_PD_A3VC>; +- resets = <&cpg 631>; +- +- renesas,fcp = <&fcpvi0>; +- }; +- +- csi20: csi2@fea80000 { +- compatible = "renesas,r8a774a1-csi2"; +- reg = <0 0xfea80000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 714>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 714>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi20vin0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin0csi20>; +- }; +- csi20vin1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin1csi20>; +- }; +- csi20vin2: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&vin2csi20>; +- }; +- csi20vin3: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&vin3csi20>; +- }; +- csi20vin4: endpoint@4 { +- reg = <4>; +- remote-endpoint = <&vin4csi20>; +- }; +- csi20vin5: endpoint@5 { +- reg = <5>; +- remote-endpoint = <&vin5csi20>; +- }; +- csi20vin6: endpoint@6 { +- reg = <6>; +- remote-endpoint = <&vin6csi20>; +- }; +- csi20vin7: endpoint@7 { +- reg = <7>; +- remote-endpoint = <&vin7csi20>; +- }; +- }; +- }; +- }; +- +- csi40: csi2@feaa0000 { +- compatible = "renesas,r8a774a1-csi2"; +- reg = <0 0xfeaa0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi40vin0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin0csi40>; +- }; +- csi40vin1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin1csi40>; +- }; +- csi40vin2: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&vin2csi40>; +- }; +- csi40vin3: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&vin3csi40>; +- }; +- csi40vin4: endpoint@4 { +- reg = <4>; +- remote-endpoint = <&vin4csi40>; +- }; +- csi40vin5: endpoint@5 { +- reg = <5>; +- remote-endpoint = <&vin5csi40>; +- }; +- csi40vin6: endpoint@6 { +- reg = <6>; +- remote-endpoint = <&vin6csi40>; +- }; +- csi40vin7: endpoint@7 { +- reg = <7>; +- remote-endpoint = <&vin7csi40>; +- }; +- }; +- +- }; +- }; +- +- hdmi0: hdmi@fead0000 { +- compatible = "renesas,r8a774a1-hdmi", +- "renesas,rcar-gen3-hdmi"; +- reg = <0 0xfead0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 729>, +- <&cpg CPG_CORE R8A774A1_CLK_HDMI>; +- clock-names = "iahb", "isfr"; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 729>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- dw_hdmi0_in: endpoint { +- remote-endpoint = <&du_out_hdmi0>; +- }; +- }; +- port@1 { +- reg = <1>; +- }; +- port@2 { +- /* HDMI sound */ +- reg = <2>; +- }; +- }; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a774a1"; +- reg = <0 0xfeb00000 0 0x70000>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>; +- clock-names = "du.0", "du.1", "du.2"; +- resets = <&cpg 724>, <&cpg 722>; +- reset-names = "du.0", "du.2"; +- status = "disabled"; +- +- renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb: endpoint { +- }; +- }; +- port@1 { +- reg = <1>; +- du_out_hdmi0: endpoint { +- remote-endpoint = <&dw_hdmi0_in>; +- }; +- }; +- port@2 { +- reg = <2>; +- du_out_lvds0: endpoint { +- remote-endpoint = <&lvds0_in>; +- }; +- }; +- }; +- }; +- +- lvds0: lvds@feb90000 { +- compatible = "renesas,r8a774a1-lvds"; +- reg = <0 0xfeb90000 0 0x14>; +- clocks = <&cpg CPG_MOD 727>; +- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; +- resets = <&cpg 727>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds0_in: endpoint { +- remote-endpoint = <&du_out_lvds0>; +- }; +- }; +- port@1 { +- reg = <1>; +- lvds0_out: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@fff00044 { +- compatible = "renesas,prr"; +- reg = <0 0xfff00044 0 4>; +- }; +- }; +- +- thermal-zones { +- sensor1_thermal: sensor1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 0>; +- sustainable-power = <3874>; +- +- trips { +- sensor1_crit: sensor1-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- sensor2_thermal: sensor2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 1>; +- sustainable-power = <3874>; +- +- trips { +- sensor2_crit: sensor2-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- sensor3_thermal: sensor3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 2>; +- sustainable-power = <3874>; +- +- cooling-maps { +- map0 { +- trip = <&target>; +- cooling-device = <&a57_0 0 2>; +- contribution = <1024>; +- }; +- map1 { +- trip = <&target>; +- cooling-device = <&a53_0 0 2>; +- contribution = <1024>; +- }; +- }; +- trips { +- target: trip-point1 { +- temperature = <100000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- +- sensor3_crit: sensor3-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; +- }; +- +- /* External USB clocks - can be overridden by the board */ +- usb3s0_clk: usb3s0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- usb_extal_clk: usb_extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-beacon-rzg2n-kit.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-beacon-rzg2n-kit.dts +deleted file mode 100644 +index 3c0d59def8ee..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-beacon-rzg2n-kit.dts ++++ /dev/null +@@ -1,69 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2020, Compass Electronics Group, LLC +- */ +- +-/dts-v1/; +- +-#include "r8a774b1.dtsi" +-#include "beacon-renesom-som.dtsi" +-#include "beacon-renesom-baseboard.dtsi" +- +-/ { +- model = "Beacon Embedded Works RZ/G2N Development Kit"; +- compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1"; +- +- aliases { +- serial0 = &scif2; +- serial1 = &hscif0; +- serial2 = &hscif1; +- serial3 = &scif0; +- serial4 = &hscif2; +- serial5 = &scif5; +- serial6 = &scif4; +- ethernet0 = &avb; +- mmc0 = &sdhi3; +- mmc1 = &sdhi0; +- mmc2 = &sdhi2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&du { +- pinctrl-0 = <&du_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 721>, +- <&versaclock5 1>, +- <&x302_clk>, +- <&versaclock5 2>; +- clock-names = "du.0", "du.1", "du.3", +- "dclkin.0", "dclkin.1", "dclkin.3"; +-}; +- +-/* Reference versaclock instead of audio_clk_a */ +-&rcar_sound { +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&versaclock6_bb 4>, <&audio_clk_b>, +- <&audio_clk_c>, +- <&cpg CPG_CORE R8A774B1_CLK_S0D4>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n-ex-idk-1110wr.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n-ex-idk-1110wr.dts +deleted file mode 100644 +index 4b5154f029a5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n-ex-idk-1110wr.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 with sub board connected +- * to an Advantech IDK-1110WR 10.1" LVDS panel +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-#include "r8a774b1-hihope-rzg2n-ex.dts" +-#include "hihope-rzg2-ex-lvds.dtsi" +-#include "rzg2-advantech-idk-1110wr-panel.dtsi" +- +-&lvds0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts +deleted file mode 100644 +index ce8e3bcc7dc9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2N board +- * connected with aistarvision-mipi-v2-adapter board +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a774b1-hihope-rzg2n-ex.dts" +-#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi" +- +-/ { +- model = "HopeRun HiHope RZ/G2N with sub board connected with aistarvision-mipi-v2-adapter board"; +- compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n-ex.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n-ex.dts +deleted file mode 100644 +index 60d7c8adea02..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n-ex.dts ++++ /dev/null +@@ -1,21 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 connected to +- * sub board +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-#include "r8a774b1-hihope-rzg2n.dts" +-#include "hihope-rzg2-ex.dtsi" +- +-/ { +- model = "HopeRun HiHope RZ/G2N with sub board"; +- compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n", +- "renesas,r8a774b1"; +-}; +- +-/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */ +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dts +deleted file mode 100644 +index e730b3b25dbe..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2N Rev.2.0 with sub board connected +- * to an Advantech IDK-1110WR 10.1" LVDS panel +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-#include "r8a774b1-hihope-rzg2n-rev2-ex.dts" +-#include "hihope-rzg2-ex-lvds.dtsi" +-#include "rzg2-advantech-idk-1110wr-panel.dtsi" +- +-&lvds0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n-rev2-ex.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n-rev2-ex.dts +deleted file mode 100644 +index 2e5e1de04049..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n-rev2-ex.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2N Rev.2.0 connected to sub board +- * +- * Copyright (C) 2019 Renesas Electronics Corp. +- */ +- +-#include "r8a774b1-hihope-rzg2n-rev2.dts" +-#include "hihope-rzg2-ex.dtsi" +- +-/ { +- model = "HopeRun HiHope RZ/G2N (Rev.2.0) with sub board"; +- compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n", +- "renesas,r8a774b1"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n-rev2.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n-rev2.dts +deleted file mode 100644 +index c69ca5cf6f77..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n-rev2.dts ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2N Rev.2.0 main board +- * +- * Copyright (C) 2019 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a774b1.dtsi" +-#include "hihope-rev2.dtsi" +- +-/ { +- model = "HopeRun HiHope RZ/G2N main board (Rev.2.0) based on r8a774b1"; +- compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x78000000>; +- }; +- +- memory@480000000 { +- device_type = "memory"; +- reg = <0x4 0x80000000 0x0 0x80000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 721>, +- <&versaclock5 1>, +- <&x302_clk>, +- <&versaclock5 2>; +- clock-names = "du.0", "du.1", "du.3", +- "dclkin.0", "dclkin.1", "dclkin.3"; +-}; +- +-&sdhi3 { +- mmc-hs400-1_8v; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n.dts +deleted file mode 100644 +index f1883cbd1a82..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1-hihope-rzg2n.dts ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2N main board Rev.3.0/4.0 +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a774b1.dtsi" +-#include "hihope-rev4.dtsi" +- +-/ { +- model = "HopeRun HiHope RZ/G2N main board based on r8a774b1"; +- compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x78000000>; +- }; +- +- memory@480000000 { +- device_type = "memory"; +- reg = <0x4 0x80000000 0x0 0x80000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 721>, +- <&versaclock5 1>, +- <&x302_clk>, +- <&versaclock5 2>; +- clock-names = "du.0", "du.1", "du.3", +- "dclkin.0", "dclkin.1", "dclkin.3"; +-}; +- +-&sdhi3 { +- mmc-hs400-1_8v; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1.dtsi +deleted file mode 100644 +index 6c5694fa6690..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774b1.dtsi ++++ /dev/null +@@ -1,2711 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the r8a774b1 SoC +- * +- * Copyright (C) 2019 Renesas Electronics Corp. +- */ +- +-#include +-#include +-#include +-#include +- +-#define CPG_AUDIO_CLK_I R8A774B1_CLK_S0D4 +- +-/ { +- compatible = "renesas,r8a774b1"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- /* +- * The external audio clocks are configured as 0 Hz fixed frequency +- * clocks by default. +- * Boards that provide audio clocks should override them. +- */ +- audio_clk_a: audio_clk_a { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_b: audio_clk_b { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_c: audio_clk_c { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* External CAN clock - to be overridden by boards that provide it */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- cluster0_opp: opp_table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <830000>; +- clock-latency-ns = <300000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <830000>; +- clock-latency-ns = <300000>; +- }; +- opp-1500000000 { +- opp-hz = /bits/ 64 <1500000000>; +- opp-microvolt = <830000>; +- clock-latency-ns = <300000>; +- opp-suspend; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- a57_0: cpu@0 { +- compatible = "arm,cortex-a57"; +- reg = <0x0>; +- device_type = "cpu"; +- power-domains = <&sysc R8A774B1_PD_CA57_CPU0>; +- next-level-cache = <&L2_CA57>; +- enable-method = "psci"; +- #cooling-cells = <2>; +- dynamic-power-coefficient = <854>; +- clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; +- operating-points-v2 = <&cluster0_opp>; +- }; +- +- a57_1: cpu@1 { +- compatible = "arm,cortex-a57"; +- reg = <0x1>; +- device_type = "cpu"; +- power-domains = <&sysc R8A774B1_PD_CA57_CPU1>; +- next-level-cache = <&L2_CA57>; +- enable-method = "psci"; +- clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; +- operating-points-v2 = <&cluster0_opp>; +- }; +- +- L2_CA57: cache-controller-0 { +- compatible = "cache"; +- power-domains = <&sysc R8A774B1_PD_CA57_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- }; +- +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- extalr_clk: extalr { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- /* External PCIe clock - can be overridden by the board */ +- pcie_bus_clk: pcie_bus { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- pmu_a57 { +- compatible = "arm,cortex-a57-pmu"; +- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&a57_0>, <&a57_1>; +- }; +- +- psci { +- compatible = "arm,psci-1.0", "arm,psci-0.2"; +- method = "smc"; +- }; +- +- /* External SCIF clock - to be overridden by boards that provide it */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a774b1-wdt", +- "renesas,rcar-gen3-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a774b1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 16>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a774b1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 29>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a774b1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 15>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a774b1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 16>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a774b1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 18>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a774b1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- gpio6: gpio@e6055400 { +- compatible = "renesas,gpio-r8a774b1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055400 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 192 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 906>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 906>; +- }; +- +- gpio7: gpio@e6055800 { +- compatible = "renesas,gpio-r8a774b1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055800 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 224 4>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 905>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 905>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a774b1"; +- reg = <0 0xe6060000 0 0x50c>; +- }; +- +- cmt0: timer@e60f0000 { +- compatible = "renesas,r8a774b1-cmt0", +- "renesas,rcar-gen3-cmt0"; +- reg = <0 0xe60f0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 303>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 303>; +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a774b1-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 302>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 302>; +- status = "disabled"; +- }; +- +- cmt2: timer@e6140000 { +- compatible = "renesas,r8a774b1-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6140000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 301>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 301>; +- status = "disabled"; +- }; +- +- cmt3: timer@e6148000 { +- compatible = "renesas,r8a774b1-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6148000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 300>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 300>; +- status = "disabled"; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a774b1-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>, <&extalr_clk>; +- clock-names = "extal", "extalr"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a774b1-rst"; +- reg = <0 0xe6160000 0 0x0200>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a774b1-sysc"; +- reg = <0 0xe6180000 0 0x0400>; +- #power-domain-cells = <1>; +- }; +- +- tsc: thermal@e6198000 { +- compatible = "renesas,r8a774b1-thermal"; +- reg = <0 0xe6198000 0 0x100>, +- <0 0xe61a0000 0 0x100>, +- <0 0xe61a8000 0 0x100>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 522>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 522>; +- #thermal-sensor-cells = <1>; +- }; +- +- intc_ex: interrupt-controller@e61c0000 { +- compatible = "renesas,intc-ex-r8a774b1", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- tmu0: timer@e61e0000 { +- compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; +- reg = <0 0xe61e0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 125>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 125>; +- status = "disabled"; +- }; +- +- tmu1: timer@e6fc0000 { +- compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; +- reg = <0 0xe6fc0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- status = "disabled"; +- }; +- +- tmu2: timer@e6fd0000 { +- compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; +- reg = <0 0xe6fd0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 123>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 123>; +- status = "disabled"; +- }; +- +- tmu3: timer@e6fe0000 { +- compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; +- reg = <0 0xe6fe0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 122>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 122>; +- status = "disabled"; +- }; +- +- tmu4: timer@ffc00000 { +- compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; +- reg = <0 0xffc00000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 121>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 121>; +- status = "disabled"; +- }; +- +- i2c0: i2c@e6500000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774b1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6500000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- dmas = <&dmac1 0x91>, <&dmac1 0x90>, +- <&dmac2 0x91>, <&dmac2 0x90>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6508000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774b1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- dmas = <&dmac1 0x93>, <&dmac1 0x92>, +- <&dmac2 0x93>, <&dmac2 0x92>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6510000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774b1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6510000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- dmas = <&dmac1 0x95>, <&dmac1 0x94>, +- <&dmac2 0x95>, <&dmac2 0x94>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e66d0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774b1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- dmas = <&dmac0 0x97>, <&dmac0 0x96>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e66d8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774b1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 927>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 927>; +- dmas = <&dmac0 0x99>, <&dmac0 0x98>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c5: i2c@e66e0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774b1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 919>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 919>; +- dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c6: i2c@e66e8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774b1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 918>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 918>; +- dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- iic_pmic: i2c@e60b0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a774b1", +- "renesas,rcar-gen3-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe60b0000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 926>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 926>; +- dmas = <&dmac0 0x11>, <&dmac0 0x10>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- hscif0: serial@e6540000 { +- compatible = "renesas,hscif-r8a774b1", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6540000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 520>, +- <&cpg CPG_CORE R8A774B1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x31>, <&dmac1 0x30>, +- <&dmac2 0x31>, <&dmac2 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 520>; +- status = "disabled"; +- }; +- +- hscif1: serial@e6550000 { +- compatible = "renesas,hscif-r8a774b1", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6550000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 519>, +- <&cpg CPG_CORE R8A774B1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x33>, <&dmac1 0x32>, +- <&dmac2 0x33>, <&dmac2 0x32>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 519>; +- status = "disabled"; +- }; +- +- hscif2: serial@e6560000 { +- compatible = "renesas,hscif-r8a774b1", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6560000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 518>, +- <&cpg CPG_CORE R8A774B1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x35>, <&dmac1 0x34>, +- <&dmac2 0x35>, <&dmac2 0x34>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 518>; +- status = "disabled"; +- }; +- +- hscif3: serial@e66a0000 { +- compatible = "renesas,hscif-r8a774b1", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66a0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 517>, +- <&cpg CPG_CORE R8A774B1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x37>, <&dmac0 0x36>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 517>; +- status = "disabled"; +- }; +- +- hscif4: serial@e66b0000 { +- compatible = "renesas,hscif-r8a774b1", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66b0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 516>, +- <&cpg CPG_CORE R8A774B1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x39>, <&dmac0 0x38>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 516>; +- status = "disabled"; +- }; +- +- hsusb: usb@e6590000 { +- compatible = "renesas,usbhs-r8a774b1", +- "renesas,rcar-gen3-usbhs"; +- reg = <0 0xe6590000 0 0x200>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; +- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, +- <&usb_dmac1 0>, <&usb_dmac1 1>; +- dma-names = "ch0", "ch1", "ch2", "ch3"; +- renesas,buswait = <11>; +- phys = <&usb2_phy0 3>; +- phy-names = "usb"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 704>, <&cpg 703>; +- status = "disabled"; +- }; +- +- usb2_clksel: clock-controller@e6590630 { +- compatible = "renesas,r8a774b1-rcar-usb2-clock-sel", +- "renesas,rcar-gen3-usb2-clock-sel"; +- reg = <0 0xe6590630 0 0x02>; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, +- <&usb_extal_clk>, <&usb3s0_clk>; +- clock-names = "ehci_ohci", "hs-usb-if", +- "usb_extal", "usb_xtal"; +- #clock-cells = <0>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- reset-names = "ehci_ohci", "hs-usb-if"; +- status = "disabled"; +- }; +- +- usb_dmac0: dma-controller@e65a0000 { +- compatible = "renesas,r8a774b1-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65a0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 330>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 330>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac1: dma-controller@e65b0000 { +- compatible = "renesas,r8a774b1-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65b0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 331>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 331>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb3_phy0: usb-phy@e65ee000 { +- compatible = "renesas,r8a774b1-usb3-phy", +- "renesas,rcar-gen3-usb3-phy"; +- reg = <0 0xe65ee000 0 0x90>; +- clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, +- <&usb_extal_clk>; +- clock-names = "usb3-if", "usb3s_clk", "usb_extal"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a774b1", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, +- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, +- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, +- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, +- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, +- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, +- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, +- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; +- }; +- +- dmac1: dma-controller@e7300000 { +- compatible = "renesas,dmac-r8a774b1", +- "renesas,rcar-dmac"; +- reg = <0 0xe7300000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, +- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, +- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, +- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, +- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, +- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, +- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, +- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; +- }; +- +- dmac2: dma-controller@e7310000 { +- compatible = "renesas,dmac-r8a774b1", +- "renesas,rcar-dmac"; +- reg = <0 0xe7310000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 217>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 217>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, +- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, +- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, +- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, +- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, +- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, +- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, +- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; +- }; +- +- ipmmu_ds0: iommu@e6740000 { +- compatible = "renesas,ipmmu-r8a774b1"; +- reg = <0 0xe6740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 0>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_ds1: iommu@e7740000 { +- compatible = "renesas,ipmmu-r8a774b1"; +- reg = <0 0xe7740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 1>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_hc: iommu@e6570000 { +- compatible = "renesas,ipmmu-r8a774b1"; +- reg = <0 0xe6570000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 2>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mm: iommu@e67b0000 { +- compatible = "renesas,ipmmu-r8a774b1"; +- reg = <0 0xe67b0000 0 0x1000>; +- interrupts = , +- ; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mp: iommu@ec670000 { +- compatible = "renesas,ipmmu-r8a774b1"; +- reg = <0 0xec670000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 4>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_pv0: iommu@fd800000 { +- compatible = "renesas,ipmmu-r8a774b1"; +- reg = <0 0xfd800000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 6>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vc0: iommu@fe6b0000 { +- compatible = "renesas,ipmmu-r8a774b1"; +- reg = <0 0xfe6b0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 12>; +- power-domains = <&sysc R8A774B1_PD_A3VC>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vi0: iommu@febd0000 { +- compatible = "renesas,ipmmu-r8a774b1"; +- reg = <0 0xfebd0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 14>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vp0: iommu@fe990000 { +- compatible = "renesas,ipmmu-r8a774b1"; +- reg = <0 0xfe990000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 16>; +- power-domains = <&sysc R8A774B1_PD_A3VP>; +- #iommu-cells = <1>; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a774b1", +- "renesas,etheravb-rcar-gen3"; +- reg = <0 0xe6800000 0 0x800>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15", +- "ch16", "ch17", "ch18", "ch19", +- "ch20", "ch21", "ch22", "ch23", +- "ch24"; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- phy-mode = "rgmii"; +- rx-internal-delay-ps = <0>; +- tx-internal-delay-ps = <0>; +- iommus = <&ipmmu_ds0 16>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- can0: can@e6c30000 { +- compatible = "renesas,can-r8a774b1", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c30000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>, +- <&cpg CPG_CORE R8A774B1_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- status = "disabled"; +- }; +- +- can1: can@e6c38000 { +- compatible = "renesas,can-r8a774b1", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c38000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>, +- <&cpg CPG_CORE R8A774B1_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- status = "disabled"; +- }; +- +- canfd: can@e66c0000 { +- compatible = "renesas,r8a774b1-canfd", +- "renesas,rcar-gen3-canfd"; +- reg = <0 0xe66c0000 0 0x8000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 914>, +- <&cpg CPG_CORE R8A774B1_CLK_CANFD>, +- <&can_clk>; +- clock-names = "fck", "canfd", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 914>; +- status = "disabled"; +- +- channel0 { +- status = "disabled"; +- }; +- +- channel1 { +- status = "disabled"; +- }; +- }; +- +- pwm0: pwm@e6e30000 { +- compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; +- reg = <0 0xe6e30000 0 0x8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm1: pwm@e6e31000 { +- compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; +- reg = <0 0xe6e31000 0 0x8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm2: pwm@e6e32000 { +- compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; +- reg = <0 0xe6e32000 0 0x8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm3: pwm@e6e33000 { +- compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; +- reg = <0 0xe6e33000 0 0x8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm4: pwm@e6e34000 { +- compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; +- reg = <0 0xe6e34000 0 0x8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm5: pwm@e6e35000 { +- compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; +- reg = <0 0xe6e35000 0 0x8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm6: pwm@e6e36000 { +- compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; +- reg = <0 0xe6e36000 0 0x8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a774b1", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e60000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>, +- <&cpg CPG_CORE R8A774B1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x51>, <&dmac1 0x50>, +- <&dmac2 0x51>, <&dmac2 0x50>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a774b1", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e68000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>, +- <&cpg CPG_CORE R8A774B1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x53>, <&dmac1 0x52>, +- <&dmac2 0x53>, <&dmac2 0x52>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e88000 { +- compatible = "renesas,scif-r8a774b1", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e88000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 310>, +- <&cpg CPG_CORE R8A774B1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x13>, <&dmac1 0x12>, +- <&dmac2 0x13>, <&dmac2 0x12>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 310>; +- status = "disabled"; +- }; +- +- scif3: serial@e6c50000 { +- compatible = "renesas,scif-r8a774b1", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c50000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>, +- <&cpg CPG_CORE R8A774B1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x57>, <&dmac0 0x56>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scif4: serial@e6c40000 { +- compatible = "renesas,scif-r8a774b1", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c40000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>, +- <&cpg CPG_CORE R8A774B1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x59>, <&dmac0 0x58>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- scif5: serial@e6f30000 { +- compatible = "renesas,scif-r8a774b1", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6f30000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 202>, +- <&cpg CPG_CORE R8A774B1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, +- <&dmac2 0x5b>, <&dmac2 0x5a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 202>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e90000 { +- compatible = "renesas,msiof-r8a774b1", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6e90000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 211>; +- dmas = <&dmac1 0x41>, <&dmac1 0x40>, +- <&dmac2 0x41>, <&dmac2 0x40>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 211>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6ea0000 { +- compatible = "renesas,msiof-r8a774b1", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6ea0000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 210>; +- dmas = <&dmac1 0x43>, <&dmac1 0x42>, +- <&dmac2 0x43>, <&dmac2 0x42>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 210>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6c00000 { +- compatible = "renesas,msiof-r8a774b1", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c00000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 209>; +- dmas = <&dmac0 0x45>, <&dmac0 0x44>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 209>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof3: spi@e6c10000 { +- compatible = "renesas,msiof-r8a774b1", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c10000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 208>; +- dmas = <&dmac0 0x47>, <&dmac0 0x46>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 208>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a774b1"; +- reg = <0 0xe6ef0000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 811>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 811>; +- renesas,id = <0>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin0csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin0>; +- }; +- vin0csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin0>; +- }; +- }; +- }; +- }; +- +- vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a774b1"; +- reg = <0 0xe6ef1000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 810>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 810>; +- renesas,id = <1>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin1csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin1>; +- }; +- vin1csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin1>; +- }; +- }; +- }; +- }; +- +- vin2: video@e6ef2000 { +- compatible = "renesas,vin-r8a774b1"; +- reg = <0 0xe6ef2000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 809>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 809>; +- renesas,id = <2>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin2csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin2>; +- }; +- vin2csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin2>; +- }; +- }; +- }; +- }; +- +- vin3: video@e6ef3000 { +- compatible = "renesas,vin-r8a774b1"; +- reg = <0 0xe6ef3000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 808>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 808>; +- renesas,id = <3>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin3csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin3>; +- }; +- vin3csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin3>; +- }; +- }; +- }; +- }; +- +- vin4: video@e6ef4000 { +- compatible = "renesas,vin-r8a774b1"; +- reg = <0 0xe6ef4000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 807>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 807>; +- renesas,id = <4>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin4csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin4>; +- }; +- vin4csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin4>; +- }; +- }; +- }; +- }; +- +- vin5: video@e6ef5000 { +- compatible = "renesas,vin-r8a774b1"; +- reg = <0 0xe6ef5000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 806>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 806>; +- renesas,id = <5>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin5csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin5>; +- }; +- vin5csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin5>; +- }; +- }; +- }; +- }; +- +- vin6: video@e6ef6000 { +- compatible = "renesas,vin-r8a774b1"; +- reg = <0 0xe6ef6000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 805>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 805>; +- renesas,id = <6>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin6csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin6>; +- }; +- vin6csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin6>; +- }; +- }; +- }; +- }; +- +- vin7: video@e6ef7000 { +- compatible = "renesas,vin-r8a774b1"; +- reg = <0 0xe6ef7000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 804>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 804>; +- renesas,id = <7>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin7csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin7>; +- }; +- vin7csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin7>; +- }; +- }; +- }; +- }; +- +- rcar_sound: sound@ec500000 { +- /* +- * #sound-dai-cells is required +- * +- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; +- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; +- */ +- /* +- * #clock-cells is required for audio_clkout0/1/2/3 +- * +- * clkout : #clock-cells = <0>; <&rcar_sound>; +- * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; +- */ +- compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3"; +- reg = <0 0xec500000 0 0x1000>, /* SCU */ +- <0 0xec5a0000 0 0x100>, /* ADG */ +- <0 0xec540000 0 0x1000>, /* SSIU */ +- <0 0xec541000 0 0x280>, /* SSI */ +- <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ +- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; +- +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&audio_clk_b>, +- <&audio_clk_c>, +- <&cpg CPG_CORE R8A774B1_CLK_S0D4>; +- clock-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0", +- "src.9", "src.8", "src.7", "src.6", +- "src.5", "src.4", "src.3", "src.2", +- "src.1", "src.0", +- "mix.1", "mix.0", +- "ctu.1", "ctu.0", +- "dvc.0", "dvc.1", +- "clk_a", "clk_b", "clk_c", "clk_i"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 1005>, +- <&cpg 1006>, <&cpg 1007>, +- <&cpg 1008>, <&cpg 1009>, +- <&cpg 1010>, <&cpg 1011>, +- <&cpg 1012>, <&cpg 1013>, +- <&cpg 1014>, <&cpg 1015>; +- reset-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0"; +- status = "disabled"; +- +- rcar_sound,ctu { +- ctu00: ctu-0 { }; +- ctu01: ctu-1 { }; +- ctu02: ctu-2 { }; +- ctu03: ctu-3 { }; +- ctu10: ctu-4 { }; +- ctu11: ctu-5 { }; +- ctu12: ctu-6 { }; +- ctu13: ctu-7 { }; +- }; +- +- rcar_sound,dvc { +- dvc0: dvc-0 { +- dmas = <&audma1 0xbc>; +- dma-names = "tx"; +- }; +- dvc1: dvc-1 { +- dmas = <&audma1 0xbe>; +- dma-names = "tx"; +- }; +- }; +- +- rcar_sound,mix { +- mix0: mix-0 { }; +- mix1: mix-1 { }; +- }; +- +- rcar_sound,src { +- src0: src-0 { +- interrupts = ; +- dmas = <&audma0 0x85>, <&audma1 0x9a>; +- dma-names = "rx", "tx"; +- }; +- src1: src-1 { +- interrupts = ; +- dmas = <&audma0 0x87>, <&audma1 0x9c>; +- dma-names = "rx", "tx"; +- }; +- src2: src-2 { +- interrupts = ; +- dmas = <&audma0 0x89>, <&audma1 0x9e>; +- dma-names = "rx", "tx"; +- }; +- src3: src-3 { +- interrupts = ; +- dmas = <&audma0 0x8b>, <&audma1 0xa0>; +- dma-names = "rx", "tx"; +- }; +- src4: src-4 { +- interrupts = ; +- dmas = <&audma0 0x8d>, <&audma1 0xb0>; +- dma-names = "rx", "tx"; +- }; +- src5: src-5 { +- interrupts = ; +- dmas = <&audma0 0x8f>, <&audma1 0xb2>; +- dma-names = "rx", "tx"; +- }; +- src6: src-6 { +- interrupts = ; +- dmas = <&audma0 0x91>, <&audma1 0xb4>; +- dma-names = "rx", "tx"; +- }; +- src7: src-7 { +- interrupts = ; +- dmas = <&audma0 0x93>, <&audma1 0xb6>; +- dma-names = "rx", "tx"; +- }; +- src8: src-8 { +- interrupts = ; +- dmas = <&audma0 0x95>, <&audma1 0xb8>; +- dma-names = "rx", "tx"; +- }; +- src9: src-9 { +- interrupts = ; +- dmas = <&audma0 0x97>, <&audma1 0xba>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssi { +- ssi0: ssi-0 { +- interrupts = ; +- dmas = <&audma0 0x01>, <&audma1 0x02>; +- dma-names = "rx", "tx"; +- }; +- ssi1: ssi-1 { +- interrupts = ; +- dmas = <&audma0 0x03>, <&audma1 0x04>; +- dma-names = "rx", "tx"; +- }; +- ssi2: ssi-2 { +- interrupts = ; +- dmas = <&audma0 0x05>, <&audma1 0x06>; +- dma-names = "rx", "tx"; +- }; +- ssi3: ssi-3 { +- interrupts = ; +- dmas = <&audma0 0x07>, <&audma1 0x08>; +- dma-names = "rx", "tx"; +- }; +- ssi4: ssi-4 { +- interrupts = ; +- dmas = <&audma0 0x09>, <&audma1 0x0a>; +- dma-names = "rx", "tx"; +- }; +- ssi5: ssi-5 { +- interrupts = ; +- dmas = <&audma0 0x0b>, <&audma1 0x0c>; +- dma-names = "rx", "tx"; +- }; +- ssi6: ssi-6 { +- interrupts = ; +- dmas = <&audma0 0x0d>, <&audma1 0x0e>; +- dma-names = "rx", "tx"; +- }; +- ssi7: ssi-7 { +- interrupts = ; +- dmas = <&audma0 0x0f>, <&audma1 0x10>; +- dma-names = "rx", "tx"; +- }; +- ssi8: ssi-8 { +- interrupts = ; +- dmas = <&audma0 0x11>, <&audma1 0x12>; +- dma-names = "rx", "tx"; +- }; +- ssi9: ssi-9 { +- interrupts = ; +- dmas = <&audma0 0x13>, <&audma1 0x14>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssiu { +- ssiu00: ssiu-0 { +- dmas = <&audma0 0x15>, <&audma1 0x16>; +- dma-names = "rx", "tx"; +- }; +- ssiu01: ssiu-1 { +- dmas = <&audma0 0x35>, <&audma1 0x36>; +- dma-names = "rx", "tx"; +- }; +- ssiu02: ssiu-2 { +- dmas = <&audma0 0x37>, <&audma1 0x38>; +- dma-names = "rx", "tx"; +- }; +- ssiu03: ssiu-3 { +- dmas = <&audma0 0x47>, <&audma1 0x48>; +- dma-names = "rx", "tx"; +- }; +- ssiu04: ssiu-4 { +- dmas = <&audma0 0x3F>, <&audma1 0x40>; +- dma-names = "rx", "tx"; +- }; +- ssiu05: ssiu-5 { +- dmas = <&audma0 0x43>, <&audma1 0x44>; +- dma-names = "rx", "tx"; +- }; +- ssiu06: ssiu-6 { +- dmas = <&audma0 0x4F>, <&audma1 0x50>; +- dma-names = "rx", "tx"; +- }; +- ssiu07: ssiu-7 { +- dmas = <&audma0 0x53>, <&audma1 0x54>; +- dma-names = "rx", "tx"; +- }; +- ssiu10: ssiu-8 { +- dmas = <&audma0 0x49>, <&audma1 0x4a>; +- dma-names = "rx", "tx"; +- }; +- ssiu11: ssiu-9 { +- dmas = <&audma0 0x4B>, <&audma1 0x4C>; +- dma-names = "rx", "tx"; +- }; +- ssiu12: ssiu-10 { +- dmas = <&audma0 0x57>, <&audma1 0x58>; +- dma-names = "rx", "tx"; +- }; +- ssiu13: ssiu-11 { +- dmas = <&audma0 0x59>, <&audma1 0x5A>; +- dma-names = "rx", "tx"; +- }; +- ssiu14: ssiu-12 { +- dmas = <&audma0 0x5F>, <&audma1 0x60>; +- dma-names = "rx", "tx"; +- }; +- ssiu15: ssiu-13 { +- dmas = <&audma0 0xC3>, <&audma1 0xC4>; +- dma-names = "rx", "tx"; +- }; +- ssiu16: ssiu-14 { +- dmas = <&audma0 0xC7>, <&audma1 0xC8>; +- dma-names = "rx", "tx"; +- }; +- ssiu17: ssiu-15 { +- dmas = <&audma0 0xCB>, <&audma1 0xCC>; +- dma-names = "rx", "tx"; +- }; +- ssiu20: ssiu-16 { +- dmas = <&audma0 0x63>, <&audma1 0x64>; +- dma-names = "rx", "tx"; +- }; +- ssiu21: ssiu-17 { +- dmas = <&audma0 0x67>, <&audma1 0x68>; +- dma-names = "rx", "tx"; +- }; +- ssiu22: ssiu-18 { +- dmas = <&audma0 0x6B>, <&audma1 0x6C>; +- dma-names = "rx", "tx"; +- }; +- ssiu23: ssiu-19 { +- dmas = <&audma0 0x6D>, <&audma1 0x6E>; +- dma-names = "rx", "tx"; +- }; +- ssiu24: ssiu-20 { +- dmas = <&audma0 0xCF>, <&audma1 0xCE>; +- dma-names = "rx", "tx"; +- }; +- ssiu25: ssiu-21 { +- dmas = <&audma0 0xEB>, <&audma1 0xEC>; +- dma-names = "rx", "tx"; +- }; +- ssiu26: ssiu-22 { +- dmas = <&audma0 0xED>, <&audma1 0xEE>; +- dma-names = "rx", "tx"; +- }; +- ssiu27: ssiu-23 { +- dmas = <&audma0 0xEF>, <&audma1 0xF0>; +- dma-names = "rx", "tx"; +- }; +- ssiu30: ssiu-24 { +- dmas = <&audma0 0x6f>, <&audma1 0x70>; +- dma-names = "rx", "tx"; +- }; +- ssiu31: ssiu-25 { +- dmas = <&audma0 0x21>, <&audma1 0x22>; +- dma-names = "rx", "tx"; +- }; +- ssiu32: ssiu-26 { +- dmas = <&audma0 0x23>, <&audma1 0x24>; +- dma-names = "rx", "tx"; +- }; +- ssiu33: ssiu-27 { +- dmas = <&audma0 0x25>, <&audma1 0x26>; +- dma-names = "rx", "tx"; +- }; +- ssiu34: ssiu-28 { +- dmas = <&audma0 0x27>, <&audma1 0x28>; +- dma-names = "rx", "tx"; +- }; +- ssiu35: ssiu-29 { +- dmas = <&audma0 0x29>, <&audma1 0x2A>; +- dma-names = "rx", "tx"; +- }; +- ssiu36: ssiu-30 { +- dmas = <&audma0 0x2B>, <&audma1 0x2C>; +- dma-names = "rx", "tx"; +- }; +- ssiu37: ssiu-31 { +- dmas = <&audma0 0x2D>, <&audma1 0x2E>; +- dma-names = "rx", "tx"; +- }; +- ssiu40: ssiu-32 { +- dmas = <&audma0 0x71>, <&audma1 0x72>; +- dma-names = "rx", "tx"; +- }; +- ssiu41: ssiu-33 { +- dmas = <&audma0 0x17>, <&audma1 0x18>; +- dma-names = "rx", "tx"; +- }; +- ssiu42: ssiu-34 { +- dmas = <&audma0 0x19>, <&audma1 0x1A>; +- dma-names = "rx", "tx"; +- }; +- ssiu43: ssiu-35 { +- dmas = <&audma0 0x1B>, <&audma1 0x1C>; +- dma-names = "rx", "tx"; +- }; +- ssiu44: ssiu-36 { +- dmas = <&audma0 0x1D>, <&audma1 0x1E>; +- dma-names = "rx", "tx"; +- }; +- ssiu45: ssiu-37 { +- dmas = <&audma0 0x1F>, <&audma1 0x20>; +- dma-names = "rx", "tx"; +- }; +- ssiu46: ssiu-38 { +- dmas = <&audma0 0x31>, <&audma1 0x32>; +- dma-names = "rx", "tx"; +- }; +- ssiu47: ssiu-39 { +- dmas = <&audma0 0x33>, <&audma1 0x34>; +- dma-names = "rx", "tx"; +- }; +- ssiu50: ssiu-40 { +- dmas = <&audma0 0x73>, <&audma1 0x74>; +- dma-names = "rx", "tx"; +- }; +- ssiu60: ssiu-41 { +- dmas = <&audma0 0x75>, <&audma1 0x76>; +- dma-names = "rx", "tx"; +- }; +- ssiu70: ssiu-42 { +- dmas = <&audma0 0x79>, <&audma1 0x7a>; +- dma-names = "rx", "tx"; +- }; +- ssiu80: ssiu-43 { +- dmas = <&audma0 0x7b>, <&audma1 0x7c>; +- dma-names = "rx", "tx"; +- }; +- ssiu90: ssiu-44 { +- dmas = <&audma0 0x7d>, <&audma1 0x7e>; +- dma-names = "rx", "tx"; +- }; +- ssiu91: ssiu-45 { +- dmas = <&audma0 0x7F>, <&audma1 0x80>; +- dma-names = "rx", "tx"; +- }; +- ssiu92: ssiu-46 { +- dmas = <&audma0 0x81>, <&audma1 0x82>; +- dma-names = "rx", "tx"; +- }; +- ssiu93: ssiu-47 { +- dmas = <&audma0 0x83>, <&audma1 0x84>; +- dma-names = "rx", "tx"; +- }; +- ssiu94: ssiu-48 { +- dmas = <&audma0 0xA3>, <&audma1 0xA4>; +- dma-names = "rx", "tx"; +- }; +- ssiu95: ssiu-49 { +- dmas = <&audma0 0xA5>, <&audma1 0xA6>; +- dma-names = "rx", "tx"; +- }; +- ssiu96: ssiu-50 { +- dmas = <&audma0 0xA7>, <&audma1 0xA8>; +- dma-names = "rx", "tx"; +- }; +- ssiu97: ssiu-51 { +- dmas = <&audma0 0xA9>, <&audma1 0xAA>; +- dma-names = "rx", "tx"; +- }; +- }; +- }; +- +- audma0: dma-controller@ec700000 { +- compatible = "renesas,dmac-r8a774b1", +- "renesas,rcar-dmac"; +- reg = <0 0xec700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 502>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 502>; +- #dma-cells = <1>; +- dma-channels = <16>; +- }; +- +- audma1: dma-controller@ec720000 { +- compatible = "renesas,dmac-r8a774b1", +- "renesas,rcar-dmac"; +- reg = <0 0xec720000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 501>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 501>; +- #dma-cells = <1>; +- dma-channels = <16>; +- }; +- +- xhci0: usb@ee000000 { +- compatible = "renesas,xhci-r8a774b1", +- "renesas,rcar-gen3-xhci"; +- reg = <0 0xee000000 0 0xc00>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- status = "disabled"; +- }; +- +- usb3_peri0: usb@ee020000 { +- compatible = "renesas,r8a774b1-usb3-peri", +- "renesas,rcar-gen3-usb3-peri"; +- reg = <0 0xee020000 0 0x400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- status = "disabled"; +- }; +- +- ohci0: usb@ee080000 { +- compatible = "generic-ohci"; +- reg = <0 0xee080000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- ohci1: usb@ee0a0000 { +- compatible = "generic-ohci"; +- reg = <0 0xee0a0000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 702>; +- phys = <&usb2_phy1 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- status = "disabled"; +- }; +- +- ehci0: usb@ee080100 { +- compatible = "generic-ehci"; +- reg = <0 0xee080100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 2>; +- phy-names = "usb"; +- companion = <&ohci0>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- ehci1: usb@ee0a0100 { +- compatible = "generic-ehci"; +- reg = <0 0xee0a0100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 702>; +- phys = <&usb2_phy1 2>; +- phy-names = "usb"; +- companion = <&ohci1>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- status = "disabled"; +- }; +- +- usb2_phy0: usb-phy@ee080200 { +- compatible = "renesas,usb2-phy-r8a774b1", +- "renesas,rcar-gen3-usb2-phy"; +- reg = <0 0xee080200 0 0x700>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- usb2_phy1: usb-phy@ee0a0200 { +- compatible = "renesas,usb2-phy-r8a774b1", +- "renesas,rcar-gen3-usb2-phy"; +- reg = <0 0xee0a0200 0 0x700>; +- clocks = <&cpg CPG_MOD 702>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a774b1", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee100000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ee120000 { +- compatible = "renesas,sdhi-r8a774b1", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee120000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 313>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 313>; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a774b1", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee140000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 312>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 312>; +- status = "disabled"; +- }; +- +- sdhi3: mmc@ee160000 { +- compatible = "renesas,sdhi-r8a774b1", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee160000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 311>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 311>; +- status = "disabled"; +- }; +- +- rpc: spi@ee200000 { +- compatible = "renesas,r8a774b1-rpc-if", +- "renesas,rcar-gen3-rpc-if"; +- reg = <0 0xee200000 0 0x200>, +- <0 0x08000000 0 0x4000000>, +- <0 0xee208000 0 0x100>; +- reg-names = "regs", "dirmap", "wbuf"; +- interrupts = ; +- clocks = <&cpg CPG_MOD 917>; +- clock-names = "rpc"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 917>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- sata: sata@ee300000 { +- compatible = "renesas,sata-r8a774b1", +- "renesas,rcar-gen3-sata"; +- reg = <0 0xee300000 0 0x200000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 815>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 815>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1010000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x0 0xf1010000 0 0x1000>, +- <0x0 0xf1020000 0 0x20000>, +- <0x0 0xf1040000 0 0x20000>, +- <0x0 0xf1060000 0 0x20000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- pciec0: pcie@fe000000 { +- compatible = "renesas,pcie-r8a774b1", +- "renesas,pcie-rcar-gen3"; +- reg = <0 0xfe000000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, +- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, +- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, +- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 319>; +- status = "disabled"; +- }; +- +- pciec1: pcie@ee800000 { +- compatible = "renesas,pcie-r8a774b1", +- "renesas,pcie-rcar-gen3"; +- reg = <0 0xee800000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, +- <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, +- <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, +- <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 318>; +- status = "disabled"; +- }; +- +- pciec0_ep: pcie-ep@fe000000 { +- compatible = "renesas,r8a774b1-pcie-ep", +- "renesas,rcar-gen3-pcie-ep"; +- reg = <0x0 0xfe000000 0 0x80000>, +- <0x0 0xfe100000 0 0x100000>, +- <0x0 0xfe200000 0 0x200000>, +- <0x0 0x30000000 0 0x8000000>, +- <0x0 0x38000000 0 0x8000000>; +- reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 319>; +- clock-names = "pcie"; +- resets = <&cpg 319>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pciec1_ep: pcie-ep@ee800000 { +- compatible = "renesas,r8a774b1-pcie-ep", +- "renesas,rcar-gen3-pcie-ep"; +- reg = <0x0 0xee800000 0 0x80000>, +- <0x0 0xee900000 0 0x100000>, +- <0x0 0xeea00000 0 0x200000>, +- <0x0 0xc0000000 0 0x8000000>, +- <0x0 0xc8000000 0 0x8000000>; +- reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 318>; +- clock-names = "pcie"; +- resets = <&cpg 318>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- fdp1@fe940000 { +- compatible = "renesas,fdp1"; +- reg = <0 0xfe940000 0 0x2400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 119>; +- power-domains = <&sysc R8A774B1_PD_A3VP>; +- resets = <&cpg 119>; +- renesas,fcp = <&fcpf0>; +- }; +- +- fcpf0: fcp@fe950000 { +- compatible = "renesas,fcpf"; +- reg = <0 0xfe950000 0 0x200>; +- clocks = <&cpg CPG_MOD 615>; +- power-domains = <&sysc R8A774B1_PD_A3VP>; +- resets = <&cpg 615>; +- }; +- +- vspb: vsp@fe960000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe960000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 626>; +- power-domains = <&sysc R8A774B1_PD_A3VP>; +- resets = <&cpg 626>; +- +- renesas,fcp = <&fcpvb0>; +- }; +- +- vspi0: vsp@fe9a0000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe9a0000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 631>; +- power-domains = <&sysc R8A774B1_PD_A3VP>; +- resets = <&cpg 631>; +- +- renesas,fcp = <&fcpvi0>; +- }; +- +- vspd0: vsp@fea20000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea20000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 623>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 623>; +- +- renesas,fcp = <&fcpvd0>; +- }; +- +- vspd1: vsp@fea28000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea28000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 622>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 622>; +- +- renesas,fcp = <&fcpvd1>; +- }; +- +- fcpvb0: fcp@fe96f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe96f000 0 0x200>; +- clocks = <&cpg CPG_MOD 607>; +- power-domains = <&sysc R8A774B1_PD_A3VP>; +- resets = <&cpg 607>; +- }; +- +- fcpvd0: fcp@fea27000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea27000 0 0x200>; +- clocks = <&cpg CPG_MOD 603>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 603>; +- }; +- +- fcpvd1: fcp@fea2f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea2f000 0 0x200>; +- clocks = <&cpg CPG_MOD 602>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 602>; +- }; +- +- fcpvi0: fcp@fe9af000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe9af000 0 0x200>; +- clocks = <&cpg CPG_MOD 611>; +- power-domains = <&sysc R8A774B1_PD_A3VP>; +- resets = <&cpg 611>; +- }; +- +- csi20: csi2@fea80000 { +- compatible = "renesas,r8a774b1-csi2"; +- reg = <0 0xfea80000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 714>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 714>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi20vin0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin0csi20>; +- }; +- csi20vin1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin1csi20>; +- }; +- csi20vin2: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&vin2csi20>; +- }; +- csi20vin3: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&vin3csi20>; +- }; +- csi20vin4: endpoint@4 { +- reg = <4>; +- remote-endpoint = <&vin4csi20>; +- }; +- csi20vin5: endpoint@5 { +- reg = <5>; +- remote-endpoint = <&vin5csi20>; +- }; +- csi20vin6: endpoint@6 { +- reg = <6>; +- remote-endpoint = <&vin6csi20>; +- }; +- csi20vin7: endpoint@7 { +- reg = <7>; +- remote-endpoint = <&vin7csi20>; +- }; +- }; +- }; +- }; +- +- csi40: csi2@feaa0000 { +- compatible = "renesas,r8a774b1-csi2"; +- reg = <0 0xfeaa0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi40vin0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin0csi40>; +- }; +- csi40vin1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin1csi40>; +- }; +- csi40vin2: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&vin2csi40>; +- }; +- csi40vin3: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&vin3csi40>; +- }; +- csi40vin4: endpoint@4 { +- reg = <4>; +- remote-endpoint = <&vin4csi40>; +- }; +- csi40vin5: endpoint@5 { +- reg = <5>; +- remote-endpoint = <&vin5csi40>; +- }; +- csi40vin6: endpoint@6 { +- reg = <6>; +- remote-endpoint = <&vin6csi40>; +- }; +- csi40vin7: endpoint@7 { +- reg = <7>; +- remote-endpoint = <&vin7csi40>; +- }; +- }; +- }; +- }; +- +- hdmi0: hdmi@fead0000 { +- compatible = "renesas,r8a774b1-hdmi", +- "renesas,rcar-gen3-hdmi"; +- reg = <0 0xfead0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 729>, +- <&cpg CPG_CORE R8A774B1_CLK_HDMI>; +- clock-names = "iahb", "isfr"; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 729>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dw_hdmi0_in: endpoint { +- remote-endpoint = <&du_out_hdmi0>; +- }; +- }; +- port@1 { +- reg = <1>; +- }; +- port@2 { +- /* HDMI sound */ +- reg = <2>; +- }; +- }; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a774b1"; +- reg = <0 0xfeb00000 0 0x80000>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 721>; +- clock-names = "du.0", "du.1", "du.3"; +- resets = <&cpg 724>, <&cpg 722>; +- reset-names = "du.0", "du.3"; +- status = "disabled"; +- +- renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb: endpoint { +- }; +- }; +- port@1 { +- reg = <1>; +- du_out_hdmi0: endpoint { +- remote-endpoint = <&dw_hdmi0_in>; +- }; +- }; +- port@2 { +- reg = <2>; +- du_out_lvds0: endpoint { +- remote-endpoint = <&lvds0_in>; +- }; +- }; +- }; +- }; +- +- lvds0: lvds@feb90000 { +- compatible = "renesas,r8a774b1-lvds"; +- reg = <0 0xfeb90000 0 0x14>; +- clocks = <&cpg CPG_MOD 727>; +- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; +- resets = <&cpg 727>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds0_in: endpoint { +- remote-endpoint = <&du_out_lvds0>; +- }; +- }; +- port@1 { +- reg = <1>; +- lvds0_out: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@fff00044 { +- compatible = "renesas,prr"; +- reg = <0 0xfff00044 0 4>; +- }; +- }; +- +- thermal-zones { +- sensor1_thermal: sensor1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 0>; +- sustainable-power = <2439>; +- +- trips { +- sensor1_crit: sensor1-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- sensor2_thermal: sensor2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 1>; +- sustainable-power = <2439>; +- +- trips { +- sensor2_crit: sensor2-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- sensor3_thermal: sensor3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 2>; +- sustainable-power = <2439>; +- +- cooling-maps { +- map0 { +- trip = <&target>; +- cooling-device = <&a57_0 0 2>; +- contribution = <1024>; +- }; +- }; +- trips { +- target: trip-point1 { +- temperature = <100000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- +- sensor3_crit: sensor3-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +- }; +- +- /* External USB clocks - can be overridden by the board */ +- usb3s0_clk: usb3s0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- usb_extal_clk: usb_extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774c0-cat874.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774c0-cat874.dts +deleted file mode 100644 +index 4e72e4f2bab0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774c0-cat874.dts ++++ /dev/null +@@ -1,455 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874) +- * +- * Copyright (C) 2019 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a774c0.dtsi" +-#include +-#include +- +-/ { +- model = "Silicon Linux RZ/G2E 96board platform (CAT874)"; +- compatible = "si-linux,cat874", "renesas,r8a774c0"; +- +- aliases { +- serial0 = &scif2; +- serial1 = &hscif2; +- mmc0 = &sdhi0; +- mmc1 = &sdhi3; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_out: endpoint { +- remote-endpoint = <&tda19988_out>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led0 { +- gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; +- label = "LED0"; +- }; +- +- led1 { +- gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; +- label = "LED1"; +- }; +- +- led2 { +- gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; +- label = "LED2"; +- }; +- +- led3 { +- gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; +- label = "LED3"; +- }; +- }; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x78000000>; +- }; +- +- reg_12p0v: regulator-12p0v { +- compatible = "regulator-fixed"; +- regulator-name = "D12.0V"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sound: sound { +- compatible = "simple-audio-card"; +- +- simple-audio-card,name = "CAT874 HDMI sound"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,bitclock-master = <&sndcpu>; +- simple-audio-card,frame-master = <&sndcpu>; +- +- sndcodec: simple-audio-card,codec { +- sound-dai = <&tda19988>; +- }; +- +- sndcpu: simple-audio-card,cpu { +- sound-dai = <&rcar_sound>; +- }; +- }; +- +- vcc_sdhi0: regulator-vcc-sdhi0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI0 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vccq_sdhi0: regulator-vccq-sdhi0 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI0 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- wlan_en_reg: fixedregulator { +- compatible = "regulator-fixed"; +- regulator-name = "wlan-en-regulator"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- startup-delay-us = <70000>; +- +- gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- x13_clk: x13 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <74250000>; +- }; +- +- connector { +- compatible = "usb-c-connector"; +- label = "USB-C"; +- data-role = "dual"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- hs_ep: endpoint { +- remote-endpoint = <&usb3_hs_ep>; +- }; +- }; +- port@1 { +- reg = <1>; +- ss_ep: endpoint { +- remote-endpoint = <&hd3ss3220_in_ep>; +- }; +- }; +- }; +- }; +-}; +- +-&audio_clk_a { +- clock-frequency = <22579200>; +-}; +- +-&du { +- pinctrl-0 = <&du_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&x13_clk>; +- clock-names = "du.0", "du.1", "dclkin.0"; +- +- ports { +- port@0 { +- endpoint { +- remote-endpoint = <&tda19988_in>; +- }; +- }; +- }; +-}; +- +-&ehci0 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&extal_clk { +- clock-frequency = <48000000>; +-}; +- +-&hscif2 { +- pinctrl-0 = <&hscif2_pins>; +- pinctrl-names = "default"; +- +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "ti,wl1837-st"; +- enable-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <100000>; +- +- hd3ss3220@47 { +- compatible = "ti,hd3ss3220"; +- reg = <0x47>; +- interrupt-parent = <&gpio6>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- hd3ss3220_in_ep: endpoint { +- remote-endpoint = <&ss_ep>; +- }; +- }; +- port@1 { +- reg = <1>; +- hd3ss3220_out_ep: endpoint { +- remote-endpoint = <&usb3_role_switch>; +- }; +- }; +- }; +- }; +- +- tda19988: tda19988@70 { +- compatible = "nxp,tda998x"; +- reg = <0x70>; +- interrupt-parent = <&gpio1>; +- interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +- +- video-ports = <0x234501>; +- +- #sound-dai-cells = <0>; +- audio-ports = ; +- clocks = <&rcar_sound 1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- tda19988_in: endpoint { +- remote-endpoint = <&du_out_rgb>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- tda19988_out: endpoint { +- remote-endpoint = <&hdmi_con_out>; +- }; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- pinctrl-0 = <&i2c1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- rtc@32 { +- compatible = "epson,rx8571"; +- reg = <0x32>; +- }; +-}; +- +-&lvds0 { +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>; +- clock-names = "fck", "dclkin.0", "extal"; +-}; +- +-&ohci0 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&pcie_bus_clk { +- clock-frequency = <100000000>; +-}; +- +-&pciec0 { +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; +-}; +- +-&pfc { +- du_pins: du { +- groups = "du_rgb888", "du_clk_out_0", "du_sync", "du_disp", +- "du_clk_in_0"; +- function = "du"; +- }; +- +- hscif2_pins: hscif2 { +- groups = "hscif2_data_a", "hscif2_ctrl_a"; +- function = "hscif2"; +- }; +- +- i2c1_pins: i2c1 { +- groups = "i2c1_b"; +- function = "i2c1"; +- }; +- +- scif2_pins: scif2 { +- groups = "scif2_data_a"; +- function = "scif2"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <3300>; +- }; +- +- sdhi0_pins_uhs: sd0_uhs { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <1800>; +- }; +- +- sdhi3_pins: sd3 { +- groups = "sdhi3_data4", "sdhi3_ctrl"; +- function = "sdhi3"; +- power-source = <1800>; +- }; +- +- sound_clk_pins: sound_clk { +- groups = "audio_clkout1_a"; +- function = "audio_clk"; +- }; +- +- sound_pins: sound { +- groups = "ssi01239_ctrl", "ssi0_data"; +- function = "ssi"; +- }; +- +- usb30_pins: usb30 { +- groups = "usb30", "usb30_id"; +- function = "usb30"; +- }; +-}; +- +-&rcar_sound { +- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; +- pinctrl-names = "default"; +- +- /* Single DAI */ +- #sound-dai-cells = <0>; +- +- /* audio_clkout0/1/2/3 */ +- #clock-cells = <1>; +- clock-frequency = <11289600>; +- +- status = "okay"; +- +- rcar_sound,dai { +- dai0 { +- playback = <&ssi0>, <&src0>, <&dvc0>; +- }; +- }; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&scif2 { +- pinctrl-0 = <&scif2_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-1 = <&sdhi0_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <&vcc_sdhi0>; +- vqmmc-supply = <&vccq_sdhi0>; +- cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- status = "okay"; +-}; +- +-&sdhi3 { +- status = "okay"; +- pinctrl-0 = <&sdhi3_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <&wlan_en_reg>; +- bus-width = <4>; +- non-removable; +- cap-power-off-card; +- keep-power-in-suspend; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1837"; +- reg = <2>; +- interrupt-parent = <&gpio1>; +- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; +- }; +-}; +- +-&usb2_phy0 { +- renesas,no-otg-pins; +- status = "okay"; +-}; +- +-&usb3_peri0 { +- companion = <&xhci0>; +- status = "okay"; +- usb-role-switch; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- usb3_hs_ep: endpoint { +- remote-endpoint = <&hs_ep>; +- }; +- }; +- port@1 { +- reg = <1>; +- usb3_role_switch: endpoint { +- remote-endpoint = <&hd3ss3220_out_ep>; +- }; +- }; +- }; +-}; +- +-&xhci0 { +- pinctrl-0 = <&usb30_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774c0-ek874-idk-2121wr.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774c0-ek874-idk-2121wr.dts +deleted file mode 100644 +index a7b27d09f6c2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774c0-ek874-idk-2121wr.dts ++++ /dev/null +@@ -1,116 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874), +- * connected to an Advantech IDK-2121WR 21.5" LVDS panel +- * +- * Copyright (C) 2019 Renesas Electronics Corp. +- */ +- +-#include "r8a774c0-ek874.dts" +- +-/ { +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm5 0 50000>; +- +- brightness-levels = <0 4 8 16 32 64 128 255>; +- default-brightness-level = <6>; +- +- power-supply = <®_12p0v>; +- enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; +- }; +- +- panel-lvds { +- compatible = "advantech,idk-2121wr", "panel-lvds"; +- +- width-mm = <476>; +- height-mm = <268>; +- +- data-mapping = "vesa-24"; +- +- panel-timing { +- clock-frequency = <148500000>; +- hactive = <1920>; +- vactive = <1080>; +- hsync-len = <44>; +- hfront-porch = <88>; +- hback-porch = <148>; +- vfront-porch = <4>; +- vback-porch = <36>; +- vsync-len = <5>; +- }; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dual-lvds-odd-pixels; +- panel_in0: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- dual-lvds-even-pixels; +- panel_in1: endpoint { +- remote-endpoint = <&lvds1_out>; +- }; +- }; +- }; +- }; +-}; +- +-&gpio0 { +- /* +- * When GP0_17 is low LVDS[01] are connected to the LVDS connector +- * When GP0_17 is high LVDS[01] are connected to the LT8918L +- */ +- lvds-connector-en-gpio{ +- gpio-hog; +- gpios = <17 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "lvds-connector-en-gpio"; +- }; +-}; +- +-&lvds0 { +- ports { +- port@1 { +- lvds0_out: endpoint { +- remote-endpoint = <&panel_in0>; +- }; +- }; +- }; +-}; +- +-&lvds1 { +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>; +- clock-names = "fck", "dclkin.0", "extal"; +- +- ports { +- port@1 { +- lvds1_out: endpoint { +- remote-endpoint = <&panel_in1>; +- }; +- }; +- }; +-}; +- +-&pfc { +- pwm5_pins: pwm5 { +- groups = "pwm5_a"; +- function = "pwm5"; +- }; +-}; +- +-&pwm5 { +- pinctrl-0 = <&pwm5_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774c0-ek874-mipi-2.1.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774c0-ek874-mipi-2.1.dts +deleted file mode 100644 +index 2e3d1981cac4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774c0-ek874-mipi-2.1.dts ++++ /dev/null +@@ -1,73 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874) +- * connected with aistarvision-mipi-v2-adapter board +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a774c0-ek874.dts" +-#define MIPI_OV5645_PARENT_I2C i2c3 +-#define MIPI_IMX219_PARENT_I2C i2c3 +-#include "aistarvision-mipi-adapter-2.1.dtsi" +- +-/ { +- model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875) with aistarvision-mipi-v2-adapter board"; +- compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&vin4 { +- status = "okay"; +-}; +- +-&vin5 { +- status = "okay"; +-}; +- +-&csi40 { +- status = "okay"; +- +- ports { +- port@0 { +- csi40_in: endpoint { +- clock-lanes = <0>; +- data-lanes = <1 2>; +- remote-endpoint = <&ov5645_ep>; +- }; +- }; +- }; +-}; +- +-&ov5645 { +- enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; +- reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; +- +- port { +- ov5645_ep: endpoint { +- clock-lanes = <0>; +- data-lanes = <1 2>; +- remote-endpoint = <&csi40_in>; +- }; +- }; +-}; +- +-&imx219 { +- port { +- imx219_ep: endpoint { +- clock-lanes = <0>; +- data-lanes = <1 2>; +- link-frequencies = /bits/ 64 <456000000>; +- /* uncomment remote-endpoint property to tie imx219 to +- * CSI2 also make sure remote-endpoint for ov5645 camera +- * is commented and remote endpoint phandle in csi40_in +- * is imx219_ep +- */ +- /* remote-endpoint = <&csi40_in>; */ +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774c0-ek874.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774c0-ek874.dts +deleted file mode 100644 +index e7b6619ab224..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774c0-ek874.dts ++++ /dev/null +@@ -1,14 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874) +- * +- * Copyright (C) 2019 Renesas Electronics Corp. +- */ +- +-#include "r8a774c0-cat874.dts" +-#include "cat875.dtsi" +- +-/ { +- model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875)"; +- compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774c0.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r8a774c0.dtsi +deleted file mode 100644 +index d597772c4c37..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774c0.dtsi ++++ /dev/null +@@ -1,2003 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the RZ/G2E (R8A774C0) SoC +- * +- * Copyright (C) 2018-2019 Renesas Electronics Corp. +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r8a774c0"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- /* +- * The external audio clocks are configured as 0 Hz fixed frequency +- * clocks by default. +- * Boards that provide audio clocks should override them. +- */ +- audio_clk_a: audio_clk_a { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_b: audio_clk_b { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_c: audio_clk_c { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* External CAN clock - to be overridden by boards that provide it */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- cluster1_opp: opp_table10 { +- compatible = "operating-points-v2"; +- opp-shared; +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- opp-suspend; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- a53_0: cpu@0 { +- compatible = "arm,cortex-a53"; +- reg = <0>; +- device_type = "cpu"; +- #cooling-cells = <2>; +- power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- dynamic-power-coefficient = <277>; +- clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- }; +- +- a53_1: cpu@1 { +- compatible = "arm,cortex-a53"; +- reg = <1>; +- device_type = "cpu"; +- power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- }; +- +- L2_CA53: cache-controller-0 { +- compatible = "cache"; +- power-domains = <&sysc R8A774C0_PD_CA53_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- }; +- +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- /* External PCIe clock - can be overridden by the board */ +- pcie_bus_clk: pcie_bus { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- pmu_a53 { +- compatible = "arm,cortex-a53-pmu"; +- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&a53_0>, <&a53_1>; +- }; +- +- psci { +- compatible = "arm,psci-1.0", "arm,psci-0.2"; +- method = "smc"; +- }; +- +- /* External SCIF clock - to be overridden by boards that provide it */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- soc: soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a774c0-wdt", +- "renesas,rcar-gen3-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a774c0", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 18>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a774c0", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 23>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a774c0", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a774c0", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 16>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a774c0", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 11>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a774c0", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 20>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- gpio6: gpio@e6055400 { +- compatible = "renesas,gpio-r8a774c0", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055400 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 192 18>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 906>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 906>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a774c0"; +- reg = <0 0xe6060000 0 0x508>; +- }; +- +- cmt0: timer@e60f0000 { +- compatible = "renesas,r8a774c0-cmt0", +- "renesas,rcar-gen3-cmt0"; +- reg = <0 0xe60f0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 303>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 303>; +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a774c0-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 302>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 302>; +- status = "disabled"; +- }; +- +- cmt2: timer@e6140000 { +- compatible = "renesas,r8a774c0-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6140000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 301>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 301>; +- status = "disabled"; +- }; +- +- cmt3: timer@e6148000 { +- compatible = "renesas,r8a774c0-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6148000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 300>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 300>; +- status = "disabled"; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a774c0-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>; +- clock-names = "extal"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a774c0-rst"; +- reg = <0 0xe6160000 0 0x0200>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a774c0-sysc"; +- reg = <0 0xe6180000 0 0x0400>; +- #power-domain-cells = <1>; +- }; +- +- thermal: thermal@e6190000 { +- compatible = "renesas,thermal-r8a774c0"; +- reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 522>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 522>; +- #thermal-sensor-cells = <0>; +- }; +- +- intc_ex: interrupt-controller@e61c0000 { +- compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- tmu0: timer@e61e0000 { +- compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; +- reg = <0 0xe61e0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 125>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 125>; +- status = "disabled"; +- }; +- +- tmu1: timer@e6fc0000 { +- compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; +- reg = <0 0xe6fc0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- status = "disabled"; +- }; +- +- tmu2: timer@e6fd0000 { +- compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; +- reg = <0 0xe6fd0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 123>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 123>; +- status = "disabled"; +- }; +- +- tmu3: timer@e6fe0000 { +- compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; +- reg = <0 0xe6fe0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 122>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 122>; +- status = "disabled"; +- }; +- +- tmu4: timer@ffc00000 { +- compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; +- reg = <0 0xffc00000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 121>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 121>; +- status = "disabled"; +- }; +- +- i2c0: i2c@e6500000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774c0", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6500000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- dmas = <&dmac1 0x91>, <&dmac1 0x90>, +- <&dmac2 0x91>, <&dmac2 0x90>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6508000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774c0", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- dmas = <&dmac1 0x93>, <&dmac1 0x92>, +- <&dmac2 0x93>, <&dmac2 0x92>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6510000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774c0", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6510000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- dmas = <&dmac1 0x95>, <&dmac1 0x94>, +- <&dmac2 0x95>, <&dmac2 0x94>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e66d0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774c0", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- dmas = <&dmac0 0x97>, <&dmac0 0x96>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e66d8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774c0", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 927>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 927>; +- dmas = <&dmac0 0x99>, <&dmac0 0x98>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c5: i2c@e66e0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774c0", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 919>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 919>; +- dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c6: i2c@e66e8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774c0", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 918>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 918>; +- dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c7: i2c@e6690000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774c0", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6690000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1003>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 1003>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- iic_pmic: i2c@e60b0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a774c0", +- "renesas,rcar-gen3-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe60b0000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 926>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 926>; +- dmas = <&dmac0 0x11>, <&dmac0 0x10>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- hscif0: serial@e6540000 { +- compatible = "renesas,hscif-r8a774c0", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6540000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 520>, +- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x31>, <&dmac1 0x30>, +- <&dmac2 0x31>, <&dmac2 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 520>; +- status = "disabled"; +- }; +- +- hscif1: serial@e6550000 { +- compatible = "renesas,hscif-r8a774c0", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6550000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 519>, +- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x33>, <&dmac1 0x32>, +- <&dmac2 0x33>, <&dmac2 0x32>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 519>; +- status = "disabled"; +- }; +- +- hscif2: serial@e6560000 { +- compatible = "renesas,hscif-r8a774c0", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6560000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 518>, +- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x35>, <&dmac1 0x34>, +- <&dmac2 0x35>, <&dmac2 0x34>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 518>; +- status = "disabled"; +- }; +- +- hscif3: serial@e66a0000 { +- compatible = "renesas,hscif-r8a774c0", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66a0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 517>, +- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x37>, <&dmac0 0x36>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 517>; +- status = "disabled"; +- }; +- +- hscif4: serial@e66b0000 { +- compatible = "renesas,hscif-r8a774c0", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66b0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 516>, +- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x39>, <&dmac0 0x38>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 516>; +- status = "disabled"; +- }; +- +- hsusb: usb@e6590000 { +- compatible = "renesas,usbhs-r8a774c0", +- "renesas,rcar-gen3-usbhs"; +- reg = <0 0xe6590000 0 0x200>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; +- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, +- <&usb_dmac1 0>, <&usb_dmac1 1>; +- dma-names = "ch0", "ch1", "ch2", "ch3"; +- renesas,buswait = <11>; +- phys = <&usb2_phy0 3>; +- phy-names = "usb"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 704>, <&cpg 703>; +- status = "disabled"; +- }; +- +- usb_dmac0: dma-controller@e65a0000 { +- compatible = "renesas,r8a774c0-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65a0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 330>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 330>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac1: dma-controller@e65b0000 { +- compatible = "renesas,r8a774c0-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65b0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 331>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 331>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a774c0", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, +- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, +- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, +- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, +- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, +- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, +- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, +- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; +- }; +- +- dmac1: dma-controller@e7300000 { +- compatible = "renesas,dmac-r8a774c0", +- "renesas,rcar-dmac"; +- reg = <0 0xe7300000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, +- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, +- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, +- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, +- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, +- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, +- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, +- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; +- }; +- +- dmac2: dma-controller@e7310000 { +- compatible = "renesas,dmac-r8a774c0", +- "renesas,rcar-dmac"; +- reg = <0 0xe7310000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 217>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 217>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, +- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, +- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, +- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, +- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, +- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, +- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, +- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; +- }; +- +- ipmmu_ds0: iommu@e6740000 { +- compatible = "renesas,ipmmu-r8a774c0"; +- reg = <0 0xe6740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 0>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_ds1: iommu@e7740000 { +- compatible = "renesas,ipmmu-r8a774c0"; +- reg = <0 0xe7740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 1>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_hc: iommu@e6570000 { +- compatible = "renesas,ipmmu-r8a774c0"; +- reg = <0 0xe6570000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 2>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mm: iommu@e67b0000 { +- compatible = "renesas,ipmmu-r8a774c0"; +- reg = <0 0xe67b0000 0 0x1000>; +- interrupts = , +- ; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mp: iommu@ec670000 { +- compatible = "renesas,ipmmu-r8a774c0"; +- reg = <0 0xec670000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 4>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_pv0: iommu@fd800000 { +- compatible = "renesas,ipmmu-r8a774c0"; +- reg = <0 0xfd800000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 6>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vc0: iommu@fe6b0000 { +- compatible = "renesas,ipmmu-r8a774c0"; +- reg = <0 0xfe6b0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 12>; +- power-domains = <&sysc R8A774C0_PD_A3VC>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vi0: iommu@febd0000 { +- compatible = "renesas,ipmmu-r8a774c0"; +- reg = <0 0xfebd0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 14>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vp0: iommu@fe990000 { +- compatible = "renesas,ipmmu-r8a774c0"; +- reg = <0 0xfe990000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 16>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a774c0", +- "renesas,etheravb-rcar-gen3"; +- reg = <0 0xe6800000 0 0x800>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15", +- "ch16", "ch17", "ch18", "ch19", +- "ch20", "ch21", "ch22", "ch23", +- "ch24"; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- phy-mode = "rgmii"; +- rx-internal-delay-ps = <0>; +- iommus = <&ipmmu_ds0 16>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- can0: can@e6c30000 { +- compatible = "renesas,can-r8a774c0", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c30000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>, +- <&cpg CPG_CORE R8A774C0_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- status = "disabled"; +- }; +- +- can1: can@e6c38000 { +- compatible = "renesas,can-r8a774c0", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c38000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>, +- <&cpg CPG_CORE R8A774C0_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- status = "disabled"; +- }; +- +- canfd: can@e66c0000 { +- compatible = "renesas,r8a774c0-canfd", +- "renesas,rcar-gen3-canfd"; +- reg = <0 0xe66c0000 0 0x8000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 914>, +- <&cpg CPG_CORE R8A774C0_CLK_CANFD>, +- <&can_clk>; +- clock-names = "fck", "canfd", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 914>; +- status = "disabled"; +- +- channel0 { +- status = "disabled"; +- }; +- +- channel1 { +- status = "disabled"; +- }; +- }; +- +- pwm0: pwm@e6e30000 { +- compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; +- reg = <0 0xe6e30000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm1: pwm@e6e31000 { +- compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; +- reg = <0 0xe6e31000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm2: pwm@e6e32000 { +- compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; +- reg = <0 0xe6e32000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm3: pwm@e6e33000 { +- compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; +- reg = <0 0xe6e33000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm4: pwm@e6e34000 { +- compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; +- reg = <0 0xe6e34000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm5: pwm@e6e35000 { +- compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; +- reg = <0 0xe6e35000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm6: pwm@e6e36000 { +- compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; +- reg = <0 0xe6e36000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a774c0", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e60000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>, +- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x51>, <&dmac1 0x50>, +- <&dmac2 0x51>, <&dmac2 0x50>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a774c0", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e68000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>, +- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x53>, <&dmac1 0x52>, +- <&dmac2 0x53>, <&dmac2 0x52>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e88000 { +- compatible = "renesas,scif-r8a774c0", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e88000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 310>, +- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x13>, <&dmac1 0x12>, +- <&dmac2 0x13>, <&dmac2 0x12>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 310>; +- status = "disabled"; +- }; +- +- scif3: serial@e6c50000 { +- compatible = "renesas,scif-r8a774c0", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c50000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>, +- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x57>, <&dmac0 0x56>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scif4: serial@e6c40000 { +- compatible = "renesas,scif-r8a774c0", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c40000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>, +- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x59>, <&dmac0 0x58>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- scif5: serial@e6f30000 { +- compatible = "renesas,scif-r8a774c0", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6f30000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 202>, +- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 202>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e90000 { +- compatible = "renesas,msiof-r8a774c0", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6e90000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 211>; +- dmas = <&dmac1 0x41>, <&dmac1 0x40>, +- <&dmac2 0x41>, <&dmac2 0x40>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 211>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6ea0000 { +- compatible = "renesas,msiof-r8a774c0", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6ea0000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 210>; +- dmas = <&dmac0 0x43>, <&dmac0 0x42>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 210>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6c00000 { +- compatible = "renesas,msiof-r8a774c0", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c00000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 209>; +- dmas = <&dmac0 0x45>, <&dmac0 0x44>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 209>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof3: spi@e6c10000 { +- compatible = "renesas,msiof-r8a774c0", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c10000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 208>; +- dmas = <&dmac0 0x47>, <&dmac0 0x46>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 208>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- vin4: video@e6ef4000 { +- compatible = "renesas,vin-r8a774c0"; +- reg = <0 0xe6ef4000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 807>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 807>; +- renesas,id = <4>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin4csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint= <&csi40vin4>; +- }; +- }; +- }; +- }; +- +- vin5: video@e6ef5000 { +- compatible = "renesas,vin-r8a774c0"; +- reg = <0 0xe6ef5000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 806>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 806>; +- renesas,id = <5>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin5csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint= <&csi40vin5>; +- }; +- }; +- }; +- }; +- +- rcar_sound: sound@ec500000 { +- /* +- * #sound-dai-cells is required +- * +- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; +- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; +- */ +- /* +- * #clock-cells is required for audio_clkout0/1/2/3 +- * +- * clkout : #clock-cells = <0>; <&rcar_sound>; +- * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; +- */ +- compatible = "renesas,rcar_sound-r8a774c0", +- "renesas,rcar_sound-gen3"; +- reg = <0 0xec500000 0 0x1000>, /* SCU */ +- <0 0xec5a0000 0 0x100>, /* ADG */ +- <0 0xec540000 0 0x1000>, /* SSIU */ +- <0 0xec541000 0 0x280>, /* SSI */ +- <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ +- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; +- +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&audio_clk_b>, +- <&audio_clk_c>, +- <&cpg CPG_CORE R8A774C0_CLK_ZA2>; +- clock-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0", +- "src.9", "src.8", "src.7", "src.6", +- "src.5", "src.4", "src.3", "src.2", +- "src.1", "src.0", +- "mix.1", "mix.0", +- "ctu.1", "ctu.0", +- "dvc.0", "dvc.1", +- "clk_a", "clk_b", "clk_c", "clk_i"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 1005>, +- <&cpg 1006>, <&cpg 1007>, +- <&cpg 1008>, <&cpg 1009>, +- <&cpg 1010>, <&cpg 1011>, +- <&cpg 1012>, <&cpg 1013>, +- <&cpg 1014>, <&cpg 1015>; +- reset-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0"; +- status = "disabled"; +- +- rcar_sound,ctu { +- ctu00: ctu-0 { }; +- ctu01: ctu-1 { }; +- ctu02: ctu-2 { }; +- ctu03: ctu-3 { }; +- ctu10: ctu-4 { }; +- ctu11: ctu-5 { }; +- ctu12: ctu-6 { }; +- ctu13: ctu-7 { }; +- }; +- +- rcar_sound,dvc { +- dvc0: dvc-0 { +- dmas = <&audma0 0xbc>; +- dma-names = "tx"; +- }; +- dvc1: dvc-1 { +- dmas = <&audma0 0xbe>; +- dma-names = "tx"; +- }; +- }; +- +- rcar_sound,mix { +- mix0: mix-0 { }; +- mix1: mix-1 { }; +- }; +- +- rcar_sound,src { +- src0: src-0 { +- interrupts = ; +- dmas = <&audma0 0x85>, <&audma0 0x9a>; +- dma-names = "rx", "tx"; +- }; +- src1: src-1 { +- interrupts = ; +- dmas = <&audma0 0x87>, <&audma0 0x9c>; +- dma-names = "rx", "tx"; +- }; +- src2: src-2 { +- interrupts = ; +- dmas = <&audma0 0x89>, <&audma0 0x9e>; +- dma-names = "rx", "tx"; +- }; +- src3: src-3 { +- interrupts = ; +- dmas = <&audma0 0x8b>, <&audma0 0xa0>; +- dma-names = "rx", "tx"; +- }; +- src4: src-4 { +- interrupts = ; +- dmas = <&audma0 0x8d>, <&audma0 0xb0>; +- dma-names = "rx", "tx"; +- }; +- src5: src-5 { +- interrupts = ; +- dmas = <&audma0 0x8f>, <&audma0 0xb2>; +- dma-names = "rx", "tx"; +- }; +- src6: src-6 { +- interrupts = ; +- dmas = <&audma0 0x91>, <&audma0 0xb4>; +- dma-names = "rx", "tx"; +- }; +- src7: src-7 { +- interrupts = ; +- dmas = <&audma0 0x93>, <&audma0 0xb6>; +- dma-names = "rx", "tx"; +- }; +- src8: src-8 { +- interrupts = ; +- dmas = <&audma0 0x95>, <&audma0 0xb8>; +- dma-names = "rx", "tx"; +- }; +- src9: src-9 { +- interrupts = ; +- dmas = <&audma0 0x97>, <&audma0 0xba>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssi { +- ssi0: ssi-0 { +- interrupts = ; +- dmas = <&audma0 0x01>, <&audma0 0x02>, +- <&audma0 0x15>, <&audma0 0x16>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi1: ssi-1 { +- interrupts = ; +- dmas = <&audma0 0x03>, <&audma0 0x04>, +- <&audma0 0x49>, <&audma0 0x4a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi2: ssi-2 { +- interrupts = ; +- dmas = <&audma0 0x05>, <&audma0 0x06>, +- <&audma0 0x63>, <&audma0 0x64>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi3: ssi-3 { +- interrupts = ; +- dmas = <&audma0 0x07>, <&audma0 0x08>, +- <&audma0 0x6f>, <&audma0 0x70>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi4: ssi-4 { +- interrupts = ; +- dmas = <&audma0 0x09>, <&audma0 0x0a>, +- <&audma0 0x71>, <&audma0 0x72>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi5: ssi-5 { +- interrupts = ; +- dmas = <&audma0 0x0b>, <&audma0 0x0c>, +- <&audma0 0x73>, <&audma0 0x74>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi6: ssi-6 { +- interrupts = ; +- dmas = <&audma0 0x0d>, <&audma0 0x0e>, +- <&audma0 0x75>, <&audma0 0x76>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi7: ssi-7 { +- interrupts = ; +- dmas = <&audma0 0x0f>, <&audma0 0x10>, +- <&audma0 0x79>, <&audma0 0x7a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi8: ssi-8 { +- interrupts = ; +- dmas = <&audma0 0x11>, <&audma0 0x12>, +- <&audma0 0x7b>, <&audma0 0x7c>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi9: ssi-9 { +- interrupts = ; +- dmas = <&audma0 0x13>, <&audma0 0x14>, +- <&audma0 0x7d>, <&audma0 0x7e>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- }; +- }; +- +- audma0: dma-controller@ec700000 { +- compatible = "renesas,dmac-r8a774c0", +- "renesas,rcar-dmac"; +- reg = <0 0xec700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 502>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 502>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, +- <&ipmmu_mp 2>, <&ipmmu_mp 3>, +- <&ipmmu_mp 4>, <&ipmmu_mp 5>, +- <&ipmmu_mp 6>, <&ipmmu_mp 7>, +- <&ipmmu_mp 8>, <&ipmmu_mp 9>, +- <&ipmmu_mp 10>, <&ipmmu_mp 11>, +- <&ipmmu_mp 12>, <&ipmmu_mp 13>, +- <&ipmmu_mp 14>, <&ipmmu_mp 15>; +- }; +- +- xhci0: usb@ee000000 { +- compatible = "renesas,xhci-r8a774c0", +- "renesas,rcar-gen3-xhci"; +- reg = <0 0xee000000 0 0xc00>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- status = "disabled"; +- }; +- +- usb3_peri0: usb@ee020000 { +- compatible = "renesas,r8a774c0-usb3-peri", +- "renesas,rcar-gen3-usb3-peri"; +- reg = <0 0xee020000 0 0x400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- status = "disabled"; +- }; +- +- ohci0: usb@ee080000 { +- compatible = "generic-ohci"; +- reg = <0 0xee080000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- ehci0: usb@ee080100 { +- compatible = "generic-ehci"; +- reg = <0 0xee080100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 2>; +- phy-names = "usb"; +- companion = <&ohci0>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- usb2_phy0: usb-phy@ee080200 { +- compatible = "renesas,usb2-phy-r8a774c0", +- "renesas,rcar-gen3-usb2-phy"; +- reg = <0 0xee080200 0 0x700>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a774c0", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee100000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ee120000 { +- compatible = "renesas,sdhi-r8a774c0", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee120000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 313>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 313>; +- status = "disabled"; +- }; +- +- sdhi3: mmc@ee160000 { +- compatible = "renesas,sdhi-r8a774c0", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee160000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 311>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 311>; +- status = "disabled"; +- }; +- +- rpc: spi@ee200000 { +- compatible = "renesas,r8a774c0-rpc-if", +- "renesas,rcar-gen3-rpc-if"; +- reg = <0 0xee200000 0 0x200>, +- <0 0x08000000 0 0x4000000>, +- <0 0xee208000 0 0x100>; +- reg-names = "regs", "dirmap", "wbuf"; +- interrupts = ; +- clocks = <&cpg CPG_MOD 917>; +- clock-names = "rpc"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 917>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1010000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x0 0xf1010000 0 0x1000>, +- <0x0 0xf1020000 0 0x20000>, +- <0x0 0xf1040000 0 0x20000>, +- <0x0 0xf1060000 0 0x20000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- pciec0: pcie@fe000000 { +- compatible = "renesas,pcie-r8a774c0", +- "renesas,pcie-rcar-gen3"; +- reg = <0 0xfe000000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, +- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, +- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, +- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 319>; +- status = "disabled"; +- }; +- +- pciec0_ep: pcie-ep@fe000000 { +- compatible = "renesas,r8a774c0-pcie-ep", +- "renesas,rcar-gen3-pcie-ep"; +- reg = <0x0 0xfe000000 0 0x80000>, +- <0x0 0xfe100000 0 0x100000>, +- <0x0 0xfe200000 0 0x200000>, +- <0x0 0x30000000 0 0x8000000>, +- <0x0 0x38000000 0 0x8000000>; +- reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 319>; +- clock-names = "pcie"; +- resets = <&cpg 319>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- vspb0: vsp@fe960000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe960000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 626>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 626>; +- renesas,fcp = <&fcpvb0>; +- }; +- +- vspd0: vsp@fea20000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea20000 0 0x7000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 623>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 623>; +- renesas,fcp = <&fcpvd0>; +- }; +- +- vspd1: vsp@fea28000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea28000 0 0x7000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 622>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 622>; +- renesas,fcp = <&fcpvd1>; +- }; +- +- vspi0: vsp@fe9a0000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe9a0000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 631>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 631>; +- renesas,fcp = <&fcpvi0>; +- }; +- +- fcpvb0: fcp@fe96f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe96f000 0 0x200>; +- clocks = <&cpg CPG_MOD 607>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 607>; +- iommus = <&ipmmu_vp0 5>; +- }; +- +- fcpvd0: fcp@fea27000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea27000 0 0x200>; +- clocks = <&cpg CPG_MOD 603>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 603>; +- iommus = <&ipmmu_vi0 8>; +- }; +- +- fcpvd1: fcp@fea2f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea2f000 0 0x200>; +- clocks = <&cpg CPG_MOD 602>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 602>; +- iommus = <&ipmmu_vi0 9>; +- }; +- +- fcpvi0: fcp@fe9af000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe9af000 0 0x200>; +- clocks = <&cpg CPG_MOD 611>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 611>; +- iommus = <&ipmmu_vp0 8>; +- }; +- +- csi40: csi2@feaa0000 { +- compatible = "renesas,r8a774c0-csi2"; +- reg = <0 0xfeaa0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi40vin4: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin4csi40>; +- }; +- csi40vin5: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin5csi40>; +- }; +- }; +- }; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a774c0"; +- reg = <0 0xfeb00000 0 0x40000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; +- clock-names = "du.0", "du.1"; +- resets = <&cpg 724>; +- reset-names = "du.0"; +- renesas,vsps = <&vspd0 0>, <&vspd1 0>; +- +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb: endpoint { +- }; +- }; +- +- port@1 { +- reg = <1>; +- du_out_lvds0: endpoint { +- remote-endpoint = <&lvds0_in>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- du_out_lvds1: endpoint { +- remote-endpoint = <&lvds1_in>; +- }; +- }; +- }; +- }; +- +- lvds0: lvds-encoder@feb90000 { +- compatible = "renesas,r8a774c0-lvds"; +- reg = <0 0xfeb90000 0 0x20>; +- clocks = <&cpg CPG_MOD 727>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 727>; +- status = "disabled"; +- +- renesas,companion = <&lvds1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds0_in: endpoint { +- remote-endpoint = <&du_out_lvds0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- lvds0_out: endpoint { +- }; +- }; +- }; +- }; +- +- lvds1: lvds-encoder@feb90100 { +- compatible = "renesas,r8a774c0-lvds"; +- reg = <0 0xfeb90100 0 0x20>; +- clocks = <&cpg CPG_MOD 727>; +- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; +- resets = <&cpg 726>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds1_in: endpoint { +- remote-endpoint = <&du_out_lvds1>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- lvds1_out: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@fff00044 { +- compatible = "renesas,prr"; +- reg = <0 0xfff00044 0 4>; +- }; +- }; +- +- thermal-zones { +- cpu-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- thermal-sensors = <&thermal 0>; +- sustainable-power = <717>; +- +- cooling-maps { +- map0 { +- trip = <&target>; +- cooling-device = <&a53_0 0 2>; +- contribution = <1024>; +- }; +- }; +- +- trips { +- sensor1_crit: sensor1-crit { +- temperature = <120000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- +- target: trip-point1 { +- temperature = <100000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +- }; +- +- /* External USB clocks - can be overridden by the board */ +- usb3s0_clk: usb3s0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- usb_extal_clk: usb_extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774e1-beacon-rzg2h-kit.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774e1-beacon-rzg2h-kit.dts +deleted file mode 100644 +index 7b6649a3ded0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774e1-beacon-rzg2h-kit.dts ++++ /dev/null +@@ -1,74 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright 2020, Compass Electronics Group, LLC +- */ +- +-/dts-v1/; +- +-#include "r8a774e1.dtsi" +-#include "beacon-renesom-som.dtsi" +-#include "beacon-renesom-baseboard.dtsi" +- +-/ { +- model = "Beacon Embedded Works RZ/G2H Development Kit"; +- compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1"; +- +- aliases { +- serial0 = &scif2; +- serial1 = &hscif0; +- serial2 = &hscif1; +- serial3 = &scif0; +- serial4 = &hscif2; +- serial5 = &scif5; +- serial6 = &scif4; +- ethernet0 = &avb; +- mmc0 = &sdhi3; +- mmc1 = &sdhi0; +- mmc2 = &sdhi2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@500000000 { +- device_type = "memory"; +- reg = <0x5 0x00000000 0x0 0x80000000>; +- }; +-}; +- +-&du { +- pinctrl-0 = <&du_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 721>, +- <&versaclock5 1>, +- <&x302_clk>, +- <&versaclock5 2>; +- clock-names = "du.0", "du.1", "du.3", +- "dclkin.0", "dclkin.1", "dclkin.3"; +-}; +- +-/* Reference versaclock instead of audio_clk_a */ +-&rcar_sound { +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&versaclock6_bb 4>, <&audio_clk_b>, +- <&audio_clk_c>, +- <&cpg CPG_CORE R8A774E1_CLK_S0D4>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts +deleted file mode 100644 +index 3b7339127bc0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2H sub board connected +- * to an Advantech IDK-1110WR 10.1" LVDS panel +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-#include "r8a774e1-hihope-rzg2h-ex.dts" +-#include "hihope-rzg2-ex-lvds.dtsi" +-#include "rzg2-advantech-idk-1110wr-panel.dtsi" +- +-&lvds0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts +deleted file mode 100644 +index 46adb6efb5e6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2H board +- * connected with aistarvision-mipi-v2-adapter board +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a774e1-hihope-rzg2h-ex.dts" +-#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi" +- +-/ { +- model = "HopeRun HiHope RZ/G2H with sub board connected with aistarvision-mipi-v2-adapter board"; +- compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774e1-hihope-rzg2h-ex.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774e1-hihope-rzg2h-ex.dts +deleted file mode 100644 +index 812995939841..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774e1-hihope-rzg2h-ex.dts ++++ /dev/null +@@ -1,20 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2H sub board +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-#include "r8a774e1-hihope-rzg2h.dts" +-#include "hihope-rzg2-ex.dtsi" +- +-/ { +- model = "HopeRun HiHope RZ/G2H with sub board"; +- compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h", +- "renesas,r8a774e1"; +-}; +- +-/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */ +-&sata { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774e1-hihope-rzg2h.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a774e1-hihope-rzg2h.dts +deleted file mode 100644 +index 9525d5ed6fce..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774e1-hihope-rzg2h.dts ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the HiHope RZ/G2H main board +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a774e1.dtsi" +-#include "hihope-rev4.dtsi" +- +-/ { +- model = "HopeRun HiHope RZ/G2H main board based on r8a774e1"; +- compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x78000000>; +- }; +- +- memory@500000000 { +- device_type = "memory"; +- reg = <0x5 0x00000000 0x0 0x80000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 721>, +- <&versaclock5 1>, +- <&x302_clk>, +- <&versaclock5 2>; +- clock-names = "du.0", "du.1", "du.3", +- "dclkin.0", "dclkin.1", "dclkin.3"; +-}; +- +-&sdhi3 { +- mmc-hs400-1_8v; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a774e1.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r8a774e1.dtsi +deleted file mode 100644 +index 62209ab6deb9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a774e1.dtsi ++++ /dev/null +@@ -1,2993 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the r8a774e1 SoC +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-#include +-#include +-#include +-#include +- +-#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4 +- +-/ { +- compatible = "renesas,r8a774e1"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- /* +- * The external audio clocks are configured as 0 Hz fixed frequency +- * clocks by default. +- * Boards that provide audio clocks should override them. +- */ +- audio_clk_a: audio_clk_a { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_b: audio_clk_b { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_c: audio_clk_c { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* External CAN clock - to be overridden by boards that provide it */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- cluster0_opp: opp_table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1500000000 { +- opp-hz = /bits/ 64 <1500000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- opp-suspend; +- }; +- }; +- +- cluster1_opp: opp_table1 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&a57_0>; +- }; +- core1 { +- cpu = <&a57_1>; +- }; +- core2 { +- cpu = <&a57_2>; +- }; +- core3 { +- cpu = <&a57_3>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&a53_0>; +- }; +- core1 { +- cpu = <&a53_1>; +- }; +- core2 { +- cpu = <&a53_2>; +- }; +- core3 { +- cpu = <&a53_3>; +- }; +- }; +- }; +- +- a57_0: cpu@0 { +- compatible = "arm,cortex-a57"; +- reg = <0x0>; +- device_type = "cpu"; +- power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; +- next-level-cache = <&L2_CA57>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- dynamic-power-coefficient = <854>; +- clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; +- operating-points-v2 = <&cluster0_opp>; +- capacity-dmips-mhz = <1024>; +- #cooling-cells = <2>; +- }; +- +- a57_1: cpu@1 { +- compatible = "arm,cortex-a57"; +- reg = <0x1>; +- device_type = "cpu"; +- power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; +- next-level-cache = <&L2_CA57>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; +- operating-points-v2 = <&cluster0_opp>; +- capacity-dmips-mhz = <1024>; +- #cooling-cells = <2>; +- }; +- +- a57_2: cpu@2 { +- compatible = "arm,cortex-a57"; +- reg = <0x2>; +- device_type = "cpu"; +- power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; +- next-level-cache = <&L2_CA57>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; +- operating-points-v2 = <&cluster0_opp>; +- capacity-dmips-mhz = <1024>; +- #cooling-cells = <2>; +- }; +- +- a57_3: cpu@3 { +- compatible = "arm,cortex-a57"; +- reg = <0x3>; +- device_type = "cpu"; +- power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; +- next-level-cache = <&L2_CA57>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; +- operating-points-v2 = <&cluster0_opp>; +- capacity-dmips-mhz = <1024>; +- #cooling-cells = <2>; +- }; +- +- a53_0: cpu@100 { +- compatible = "arm,cortex-a53"; +- reg = <0x100>; +- device_type = "cpu"; +- power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_1>; +- #cooling-cells = <2>; +- dynamic-power-coefficient = <277>; +- clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <535>; +- }; +- +- a53_1: cpu@101 { +- compatible = "arm,cortex-a53"; +- reg = <0x101>; +- device_type = "cpu"; +- power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_1>; +- clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <535>; +- }; +- +- a53_2: cpu@102 { +- compatible = "arm,cortex-a53"; +- reg = <0x102>; +- device_type = "cpu"; +- power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_1>; +- clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <535>; +- }; +- +- a53_3: cpu@103 { +- compatible = "arm,cortex-a53"; +- reg = <0x103>; +- device_type = "cpu"; +- power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_1>; +- clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <535>; +- }; +- +- L2_CA57: cache-controller-0 { +- compatible = "cache"; +- power-domains = <&sysc R8A774E1_PD_CA57_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- +- L2_CA53: cache-controller-1 { +- compatible = "cache"; +- power-domains = <&sysc R8A774E1_PD_CA53_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP_0: cpu-sleep-0 { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x0010000>; +- local-timer-stop; +- entry-latency-us = <400>; +- exit-latency-us = <500>; +- min-residency-us = <4000>; +- }; +- +- CPU_SLEEP_1: cpu-sleep-1 { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x0010000>; +- local-timer-stop; +- entry-latency-us = <700>; +- exit-latency-us = <700>; +- min-residency-us = <5000>; +- }; +- }; +- }; +- +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- extalr_clk: extalr { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- /* External PCIe clock - can be overridden by the board */ +- pcie_bus_clk: pcie_bus { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- pmu_a53 { +- compatible = "arm,cortex-a53-pmu"; +- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; +- }; +- +- pmu_a57 { +- compatible = "arm,cortex-a57-pmu"; +- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>; +- }; +- +- psci { +- compatible = "arm,psci-1.0", "arm,psci-0.2"; +- method = "smc"; +- }; +- +- /* External SCIF clock - to be overridden by boards that provide it */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a774e1-wdt", +- "renesas,rcar-gen3-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a774e1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 16>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a774e1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 29>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a774e1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 15>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a774e1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 16>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a774e1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 18>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a774e1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- gpio6: gpio@e6055400 { +- compatible = "renesas,gpio-r8a774e1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055400 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 192 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 906>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 906>; +- }; +- +- gpio7: gpio@e6055800 { +- compatible = "renesas,gpio-r8a774e1", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055800 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 224 4>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 905>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 905>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a774e1"; +- reg = <0 0xe6060000 0 0x50c>; +- }; +- +- cmt0: timer@e60f0000 { +- compatible = "renesas,r8a774e1-cmt0", +- "renesas,rcar-gen3-cmt0"; +- reg = <0 0xe60f0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 303>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 303>; +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a774e1-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 302>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 302>; +- status = "disabled"; +- }; +- +- cmt2: timer@e6140000 { +- compatible = "renesas,r8a774e1-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6140000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 301>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 301>; +- status = "disabled"; +- }; +- +- cmt3: timer@e6148000 { +- compatible = "renesas,r8a774e1-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6148000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 300>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 300>; +- status = "disabled"; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a774e1-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>, <&extalr_clk>; +- clock-names = "extal", "extalr"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a774e1-rst"; +- reg = <0 0xe6160000 0 0x0200>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a774e1-sysc"; +- reg = <0 0xe6180000 0 0x0400>; +- #power-domain-cells = <1>; +- }; +- +- tsc: thermal@e6198000 { +- compatible = "renesas,r8a774e1-thermal"; +- reg = <0 0xe6198000 0 0x100>, +- <0 0xe61a0000 0 0x100>, +- <0 0xe61a8000 0 0x100>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 522>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 522>; +- #thermal-sensor-cells = <1>; +- }; +- +- intc_ex: interrupt-controller@e61c0000 { +- compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- tmu0: timer@e61e0000 { +- compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; +- reg = <0 0xe61e0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 125>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 125>; +- status = "disabled"; +- }; +- +- tmu1: timer@e6fc0000 { +- compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; +- reg = <0 0xe6fc0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- status = "disabled"; +- }; +- +- tmu2: timer@e6fd0000 { +- compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; +- reg = <0 0xe6fd0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 123>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 123>; +- status = "disabled"; +- }; +- +- tmu3: timer@e6fe0000 { +- compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; +- reg = <0 0xe6fe0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 122>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 122>; +- status = "disabled"; +- }; +- +- tmu4: timer@ffc00000 { +- compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; +- reg = <0 0xffc00000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 121>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 121>; +- status = "disabled"; +- }; +- +- i2c0: i2c@e6500000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774e1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6500000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- dmas = <&dmac1 0x91>, <&dmac1 0x90>, +- <&dmac2 0x91>, <&dmac2 0x90>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6508000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774e1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- dmas = <&dmac1 0x93>, <&dmac1 0x92>, +- <&dmac2 0x93>, <&dmac2 0x92>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6510000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774e1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6510000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- dmas = <&dmac1 0x95>, <&dmac1 0x94>, +- <&dmac2 0x95>, <&dmac2 0x94>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e66d0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774e1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- dmas = <&dmac0 0x97>, <&dmac0 0x96>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e66d8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774e1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 927>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 927>; +- dmas = <&dmac0 0x99>, <&dmac0 0x98>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c5: i2c@e66e0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774e1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 919>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 919>; +- dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c6: i2c@e66e8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a774e1", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 918>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 918>; +- dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c_dvfs: i2c@e60b0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a774e1", +- "renesas,rcar-gen3-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe60b0000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 926>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 926>; +- dmas = <&dmac0 0x11>, <&dmac0 0x10>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- hscif0: serial@e6540000 { +- compatible = "renesas,hscif-r8a774e1", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6540000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 520>, +- <&cpg CPG_CORE R8A774E1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x31>, <&dmac1 0x30>, +- <&dmac2 0x31>, <&dmac2 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 520>; +- status = "disabled"; +- }; +- +- hscif1: serial@e6550000 { +- compatible = "renesas,hscif-r8a774e1", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6550000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 519>, +- <&cpg CPG_CORE R8A774E1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x33>, <&dmac1 0x32>, +- <&dmac2 0x33>, <&dmac2 0x32>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 519>; +- status = "disabled"; +- }; +- +- hscif2: serial@e6560000 { +- compatible = "renesas,hscif-r8a774e1", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6560000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 518>, +- <&cpg CPG_CORE R8A774E1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x35>, <&dmac1 0x34>, +- <&dmac2 0x35>, <&dmac2 0x34>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 518>; +- status = "disabled"; +- }; +- +- hscif3: serial@e66a0000 { +- compatible = "renesas,hscif-r8a774e1", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66a0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 517>, +- <&cpg CPG_CORE R8A774E1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x37>, <&dmac0 0x36>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 517>; +- status = "disabled"; +- }; +- +- hscif4: serial@e66b0000 { +- compatible = "renesas,hscif-r8a774e1", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66b0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 516>, +- <&cpg CPG_CORE R8A774E1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x39>, <&dmac0 0x38>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 516>; +- status = "disabled"; +- }; +- +- hsusb: usb@e6590000 { +- compatible = "renesas,usbhs-r8a774e1", +- "renesas,rcar-gen3-usbhs"; +- reg = <0 0xe6590000 0 0x200>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; +- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, +- <&usb_dmac1 0>, <&usb_dmac1 1>; +- dma-names = "ch0", "ch1", "ch2", "ch3"; +- renesas,buswait = <11>; +- phys = <&usb2_phy0 3>; +- phy-names = "usb"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 704>, <&cpg 703>; +- status = "disabled"; +- }; +- +- usb2_clksel: clock-controller@e6590630 { +- compatible = "renesas,r8a774e1-rcar-usb2-clock-sel", +- "renesas,rcar-gen3-usb2-clock-sel"; +- reg = <0 0xe6590630 0 0x02>; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, +- <&usb_extal_clk>, <&usb3s0_clk>; +- clock-names = "ehci_ohci", "hs-usb-if", +- "usb_extal", "usb_xtal"; +- #clock-cells = <0>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- reset-names = "ehci_ohci", "hs-usb-if"; +- status = "disabled"; +- }; +- +- usb_dmac0: dma-controller@e65a0000 { +- compatible = "renesas,r8a774e1-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65a0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 330>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 330>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac1: dma-controller@e65b0000 { +- compatible = "renesas,r8a774e1-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65b0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 331>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 331>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb3_phy0: usb-phy@e65ee000 { +- compatible = "renesas,r8a774e1-usb3-phy", +- "renesas,rcar-gen3-usb3-phy"; +- reg = <0 0xe65ee000 0 0x90>; +- clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, +- <&usb_extal_clk>; +- clock-names = "usb3-if", "usb3s_clk", "usb_extal"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a774e1", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, +- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, +- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, +- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, +- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, +- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, +- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, +- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; +- }; +- +- dmac1: dma-controller@e7300000 { +- compatible = "renesas,dmac-r8a774e1", +- "renesas,rcar-dmac"; +- reg = <0 0xe7300000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, +- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, +- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, +- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, +- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, +- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, +- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, +- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; +- }; +- +- dmac2: dma-controller@e7310000 { +- compatible = "renesas,dmac-r8a774e1", +- "renesas,rcar-dmac"; +- reg = <0 0xe7310000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 217>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 217>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, +- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, +- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, +- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, +- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, +- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, +- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, +- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; +- }; +- +- ipmmu_ds0: iommu@e6740000 { +- compatible = "renesas,ipmmu-r8a774e1"; +- reg = <0 0xe6740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 0>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_ds1: iommu@e7740000 { +- compatible = "renesas,ipmmu-r8a774e1"; +- reg = <0 0xe7740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 1>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_hc: iommu@e6570000 { +- compatible = "renesas,ipmmu-r8a774e1"; +- reg = <0 0xe6570000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 2>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mm: iommu@e67b0000 { +- compatible = "renesas,ipmmu-r8a774e1"; +- reg = <0 0xe67b0000 0 0x1000>; +- interrupts = , +- ; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mp0: iommu@ec670000 { +- compatible = "renesas,ipmmu-r8a774e1"; +- reg = <0 0xec670000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 4>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_pv0: iommu@fd800000 { +- compatible = "renesas,ipmmu-r8a774e1"; +- reg = <0 0xfd800000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 6>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_pv1: iommu@fd950000 { +- compatible = "renesas,ipmmu-r8a774e1"; +- reg = <0 0xfd950000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 7>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_pv2: iommu@fd960000 { +- compatible = "renesas,ipmmu-r8a774e1"; +- reg = <0 0xfd960000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 8>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_pv3: iommu@fd970000 { +- compatible = "renesas,ipmmu-r8a774e1"; +- reg = <0 0xfd970000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 9>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vc0: iommu@fe6b0000 { +- compatible = "renesas,ipmmu-r8a774e1"; +- reg = <0 0xfe6b0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 12>; +- power-domains = <&sysc R8A774E1_PD_A3VC>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vc1: iommu@fe6f0000 { +- compatible = "renesas,ipmmu-r8a774e1"; +- reg = <0 0xfe6f0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 13>; +- power-domains = <&sysc R8A774E1_PD_A3VC>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vi0: iommu@febd0000 { +- compatible = "renesas,ipmmu-r8a774e1"; +- reg = <0 0xfebd0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 14>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vi1: iommu@febe0000 { +- compatible = "renesas,ipmmu-r8a774e1"; +- reg = <0 0xfebe0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 15>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vp0: iommu@fe990000 { +- compatible = "renesas,ipmmu-r8a774e1"; +- reg = <0 0xfe990000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 16>; +- power-domains = <&sysc R8A774E1_PD_A3VP>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vp1: iommu@fe980000 { +- compatible = "renesas,ipmmu-r8a774e1"; +- reg = <0 0xfe980000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 17>; +- power-domains = <&sysc R8A774E1_PD_A3VP>; +- #iommu-cells = <1>; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a774e1", +- "renesas,etheravb-rcar-gen3"; +- reg = <0 0xe6800000 0 0x800>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15", +- "ch16", "ch17", "ch18", "ch19", +- "ch20", "ch21", "ch22", "ch23", +- "ch24"; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- phy-mode = "rgmii"; +- rx-internal-delay-ps = <0>; +- tx-internal-delay-ps = <0>; +- iommus = <&ipmmu_ds0 16>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- can0: can@e6c30000 { +- compatible = "renesas,can-r8a774e1", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c30000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>, +- <&cpg CPG_CORE R8A774E1_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- status = "disabled"; +- }; +- +- can1: can@e6c38000 { +- compatible = "renesas,can-r8a774e1", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c38000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>, +- <&cpg CPG_CORE R8A774E1_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- status = "disabled"; +- }; +- +- canfd: can@e66c0000 { +- compatible = "renesas,r8a774e1-canfd", +- "renesas,rcar-gen3-canfd"; +- reg = <0 0xe66c0000 0 0x8000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 914>, +- <&cpg CPG_CORE R8A774E1_CLK_CANFD>, +- <&can_clk>; +- clock-names = "fck", "canfd", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 914>; +- status = "disabled"; +- +- channel0 { +- status = "disabled"; +- }; +- +- channel1 { +- status = "disabled"; +- }; +- }; +- +- pwm0: pwm@e6e30000 { +- compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; +- reg = <0 0xe6e30000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm1: pwm@e6e31000 { +- compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; +- reg = <0 0xe6e31000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm2: pwm@e6e32000 { +- compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; +- reg = <0 0xe6e32000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm3: pwm@e6e33000 { +- compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; +- reg = <0 0xe6e33000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm4: pwm@e6e34000 { +- compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; +- reg = <0 0xe6e34000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm5: pwm@e6e35000 { +- compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; +- reg = <0 0xe6e35000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm6: pwm@e6e36000 { +- compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; +- reg = <0 0xe6e36000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a774e1", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e60000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>, +- <&cpg CPG_CORE R8A774E1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x51>, <&dmac1 0x50>, +- <&dmac2 0x51>, <&dmac2 0x50>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a774e1", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e68000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>, +- <&cpg CPG_CORE R8A774E1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x53>, <&dmac1 0x52>, +- <&dmac2 0x53>, <&dmac2 0x52>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e88000 { +- compatible = "renesas,scif-r8a774e1", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e88000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 310>, +- <&cpg CPG_CORE R8A774E1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x13>, <&dmac1 0x12>, +- <&dmac2 0x13>, <&dmac2 0x12>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 310>; +- status = "disabled"; +- }; +- +- scif3: serial@e6c50000 { +- compatible = "renesas,scif-r8a774e1", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c50000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>, +- <&cpg CPG_CORE R8A774E1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x57>, <&dmac0 0x56>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scif4: serial@e6c40000 { +- compatible = "renesas,scif-r8a774e1", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c40000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>, +- <&cpg CPG_CORE R8A774E1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x59>, <&dmac0 0x58>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- scif5: serial@e6f30000 { +- compatible = "renesas,scif-r8a774e1", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6f30000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 202>, +- <&cpg CPG_CORE R8A774E1_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, +- <&dmac2 0x5b>, <&dmac2 0x5a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 202>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e90000 { +- compatible = "renesas,msiof-r8a774e1", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6e90000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 211>; +- dmas = <&dmac1 0x41>, <&dmac1 0x40>, +- <&dmac2 0x41>, <&dmac2 0x40>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 211>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6ea0000 { +- compatible = "renesas,msiof-r8a774e1", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6ea0000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 210>; +- dmas = <&dmac1 0x43>, <&dmac1 0x42>, +- <&dmac2 0x43>, <&dmac2 0x42>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 210>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6c00000 { +- compatible = "renesas,msiof-r8a774e1", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c00000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 209>; +- dmas = <&dmac0 0x45>, <&dmac0 0x44>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 209>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof3: spi@e6c10000 { +- compatible = "renesas,msiof-r8a774e1", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c10000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 208>; +- dmas = <&dmac0 0x47>, <&dmac0 0x46>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 208>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a774e1"; +- reg = <0 0xe6ef0000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 811>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 811>; +- renesas,id = <0>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin0csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin0>; +- }; +- vin0csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin0>; +- }; +- }; +- }; +- }; +- +- vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a774e1"; +- reg = <0 0xe6ef1000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 810>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 810>; +- renesas,id = <1>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin1csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin1>; +- }; +- vin1csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin1>; +- }; +- }; +- }; +- }; +- +- vin2: video@e6ef2000 { +- compatible = "renesas,vin-r8a774e1"; +- reg = <0 0xe6ef2000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 809>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 809>; +- renesas,id = <2>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin2csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin2>; +- }; +- vin2csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin2>; +- }; +- }; +- }; +- }; +- +- vin3: video@e6ef3000 { +- compatible = "renesas,vin-r8a774e1"; +- reg = <0 0xe6ef3000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 808>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 808>; +- renesas,id = <3>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin3csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin3>; +- }; +- vin3csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin3>; +- }; +- }; +- }; +- }; +- +- vin4: video@e6ef4000 { +- compatible = "renesas,vin-r8a774e1"; +- reg = <0 0xe6ef4000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 807>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 807>; +- renesas,id = <4>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin4csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin4>; +- }; +- }; +- }; +- }; +- +- vin5: video@e6ef5000 { +- compatible = "renesas,vin-r8a774e1"; +- reg = <0 0xe6ef5000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 806>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 806>; +- renesas,id = <5>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin5csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin5>; +- }; +- }; +- }; +- }; +- +- vin6: video@e6ef6000 { +- compatible = "renesas,vin-r8a774e1"; +- reg = <0 0xe6ef6000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 805>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 805>; +- renesas,id = <6>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin6csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin6>; +- }; +- }; +- }; +- }; +- +- vin7: video@e6ef7000 { +- compatible = "renesas,vin-r8a774e1"; +- reg = <0 0xe6ef7000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 804>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 804>; +- renesas,id = <7>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin7csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin7>; +- }; +- }; +- }; +- }; +- +- rcar_sound: sound@ec500000 { +- /* +- * #sound-dai-cells is required +- * +- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; +- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; +- */ +- /* +- * #clock-cells is required for audio_clkout0/1/2/3 +- * +- * clkout : #clock-cells = <0>; <&rcar_sound>; +- * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; +- */ +- compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3"; +- reg = <0 0xec500000 0 0x1000>, /* SCU */ +- <0 0xec5a0000 0 0x100>, /* ADG */ +- <0 0xec540000 0 0x1000>, /* SSIU */ +- <0 0xec541000 0 0x280>, /* SSI */ +- <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ +- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; +- +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&audio_clk_b>, +- <&audio_clk_c>, +- <&cpg CPG_CORE R8A774E1_CLK_S0D4>; +- clock-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0", +- "src.9", "src.8", "src.7", "src.6", +- "src.5", "src.4", "src.3", "src.2", +- "src.1", "src.0", +- "mix.1", "mix.0", +- "ctu.1", "ctu.0", +- "dvc.0", "dvc.1", +- "clk_a", "clk_b", "clk_c", "clk_i"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 1005>, +- <&cpg 1006>, <&cpg 1007>, +- <&cpg 1008>, <&cpg 1009>, +- <&cpg 1010>, <&cpg 1011>, +- <&cpg 1012>, <&cpg 1013>, +- <&cpg 1014>, <&cpg 1015>; +- reset-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0"; +- status = "disabled"; +- +- rcar_sound,dvc { +- dvc0: dvc-0 { +- dmas = <&audma1 0xbc>; +- dma-names = "tx"; +- }; +- dvc1: dvc-1 { +- dmas = <&audma1 0xbe>; +- dma-names = "tx"; +- }; +- }; +- +- rcar_sound,mix { +- mix0: mix-0 { }; +- mix1: mix-1 { }; +- }; +- +- rcar_sound,ctu { +- ctu00: ctu-0 { }; +- ctu01: ctu-1 { }; +- ctu02: ctu-2 { }; +- ctu03: ctu-3 { }; +- ctu10: ctu-4 { }; +- ctu11: ctu-5 { }; +- ctu12: ctu-6 { }; +- ctu13: ctu-7 { }; +- }; +- +- rcar_sound,src { +- src0: src-0 { +- interrupts = ; +- dmas = <&audma0 0x85>, <&audma1 0x9a>; +- dma-names = "rx", "tx"; +- }; +- src1: src-1 { +- interrupts = ; +- dmas = <&audma0 0x87>, <&audma1 0x9c>; +- dma-names = "rx", "tx"; +- }; +- src2: src-2 { +- interrupts = ; +- dmas = <&audma0 0x89>, <&audma1 0x9e>; +- dma-names = "rx", "tx"; +- }; +- src3: src-3 { +- interrupts = ; +- dmas = <&audma0 0x8b>, <&audma1 0xa0>; +- dma-names = "rx", "tx"; +- }; +- src4: src-4 { +- interrupts = ; +- dmas = <&audma0 0x8d>, <&audma1 0xb0>; +- dma-names = "rx", "tx"; +- }; +- src5: src-5 { +- interrupts = ; +- dmas = <&audma0 0x8f>, <&audma1 0xb2>; +- dma-names = "rx", "tx"; +- }; +- src6: src-6 { +- interrupts = ; +- dmas = <&audma0 0x91>, <&audma1 0xb4>; +- dma-names = "rx", "tx"; +- }; +- src7: src-7 { +- interrupts = ; +- dmas = <&audma0 0x93>, <&audma1 0xb6>; +- dma-names = "rx", "tx"; +- }; +- src8: src-8 { +- interrupts = ; +- dmas = <&audma0 0x95>, <&audma1 0xb8>; +- dma-names = "rx", "tx"; +- }; +- src9: src-9 { +- interrupts = ; +- dmas = <&audma0 0x97>, <&audma1 0xba>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssiu { +- ssiu00: ssiu-0 { +- dmas = <&audma0 0x15>, <&audma1 0x16>; +- dma-names = "rx", "tx"; +- }; +- ssiu01: ssiu-1 { +- dmas = <&audma0 0x35>, <&audma1 0x36>; +- dma-names = "rx", "tx"; +- }; +- ssiu02: ssiu-2 { +- dmas = <&audma0 0x37>, <&audma1 0x38>; +- dma-names = "rx", "tx"; +- }; +- ssiu03: ssiu-3 { +- dmas = <&audma0 0x47>, <&audma1 0x48>; +- dma-names = "rx", "tx"; +- }; +- ssiu04: ssiu-4 { +- dmas = <&audma0 0x3F>, <&audma1 0x40>; +- dma-names = "rx", "tx"; +- }; +- ssiu05: ssiu-5 { +- dmas = <&audma0 0x43>, <&audma1 0x44>; +- dma-names = "rx", "tx"; +- }; +- ssiu06: ssiu-6 { +- dmas = <&audma0 0x4F>, <&audma1 0x50>; +- dma-names = "rx", "tx"; +- }; +- ssiu07: ssiu-7 { +- dmas = <&audma0 0x53>, <&audma1 0x54>; +- dma-names = "rx", "tx"; +- }; +- ssiu10: ssiu-8 { +- dmas = <&audma0 0x49>, <&audma1 0x4a>; +- dma-names = "rx", "tx"; +- }; +- ssiu11: ssiu-9 { +- dmas = <&audma0 0x4B>, <&audma1 0x4C>; +- dma-names = "rx", "tx"; +- }; +- ssiu12: ssiu-10 { +- dmas = <&audma0 0x57>, <&audma1 0x58>; +- dma-names = "rx", "tx"; +- }; +- ssiu13: ssiu-11 { +- dmas = <&audma0 0x59>, <&audma1 0x5A>; +- dma-names = "rx", "tx"; +- }; +- ssiu14: ssiu-12 { +- dmas = <&audma0 0x5F>, <&audma1 0x60>; +- dma-names = "rx", "tx"; +- }; +- ssiu15: ssiu-13 { +- dmas = <&audma0 0xC3>, <&audma1 0xC4>; +- dma-names = "rx", "tx"; +- }; +- ssiu16: ssiu-14 { +- dmas = <&audma0 0xC7>, <&audma1 0xC8>; +- dma-names = "rx", "tx"; +- }; +- ssiu17: ssiu-15 { +- dmas = <&audma0 0xCB>, <&audma1 0xCC>; +- dma-names = "rx", "tx"; +- }; +- ssiu20: ssiu-16 { +- dmas = <&audma0 0x63>, <&audma1 0x64>; +- dma-names = "rx", "tx"; +- }; +- ssiu21: ssiu-17 { +- dmas = <&audma0 0x67>, <&audma1 0x68>; +- dma-names = "rx", "tx"; +- }; +- ssiu22: ssiu-18 { +- dmas = <&audma0 0x6B>, <&audma1 0x6C>; +- dma-names = "rx", "tx"; +- }; +- ssiu23: ssiu-19 { +- dmas = <&audma0 0x6D>, <&audma1 0x6E>; +- dma-names = "rx", "tx"; +- }; +- ssiu24: ssiu-20 { +- dmas = <&audma0 0xCF>, <&audma1 0xCE>; +- dma-names = "rx", "tx"; +- }; +- ssiu25: ssiu-21 { +- dmas = <&audma0 0xEB>, <&audma1 0xEC>; +- dma-names = "rx", "tx"; +- }; +- ssiu26: ssiu-22 { +- dmas = <&audma0 0xED>, <&audma1 0xEE>; +- dma-names = "rx", "tx"; +- }; +- ssiu27: ssiu-23 { +- dmas = <&audma0 0xEF>, <&audma1 0xF0>; +- dma-names = "rx", "tx"; +- }; +- ssiu30: ssiu-24 { +- dmas = <&audma0 0x6f>, <&audma1 0x70>; +- dma-names = "rx", "tx"; +- }; +- ssiu31: ssiu-25 { +- dmas = <&audma0 0x21>, <&audma1 0x22>; +- dma-names = "rx", "tx"; +- }; +- ssiu32: ssiu-26 { +- dmas = <&audma0 0x23>, <&audma1 0x24>; +- dma-names = "rx", "tx"; +- }; +- ssiu33: ssiu-27 { +- dmas = <&audma0 0x25>, <&audma1 0x26>; +- dma-names = "rx", "tx"; +- }; +- ssiu34: ssiu-28 { +- dmas = <&audma0 0x27>, <&audma1 0x28>; +- dma-names = "rx", "tx"; +- }; +- ssiu35: ssiu-29 { +- dmas = <&audma0 0x29>, <&audma1 0x2A>; +- dma-names = "rx", "tx"; +- }; +- ssiu36: ssiu-30 { +- dmas = <&audma0 0x2B>, <&audma1 0x2C>; +- dma-names = "rx", "tx"; +- }; +- ssiu37: ssiu-31 { +- dmas = <&audma0 0x2D>, <&audma1 0x2E>; +- dma-names = "rx", "tx"; +- }; +- ssiu40: ssiu-32 { +- dmas = <&audma0 0x71>, <&audma1 0x72>; +- dma-names = "rx", "tx"; +- }; +- ssiu41: ssiu-33 { +- dmas = <&audma0 0x17>, <&audma1 0x18>; +- dma-names = "rx", "tx"; +- }; +- ssiu42: ssiu-34 { +- dmas = <&audma0 0x19>, <&audma1 0x1A>; +- dma-names = "rx", "tx"; +- }; +- ssiu43: ssiu-35 { +- dmas = <&audma0 0x1B>, <&audma1 0x1C>; +- dma-names = "rx", "tx"; +- }; +- ssiu44: ssiu-36 { +- dmas = <&audma0 0x1D>, <&audma1 0x1E>; +- dma-names = "rx", "tx"; +- }; +- ssiu45: ssiu-37 { +- dmas = <&audma0 0x1F>, <&audma1 0x20>; +- dma-names = "rx", "tx"; +- }; +- ssiu46: ssiu-38 { +- dmas = <&audma0 0x31>, <&audma1 0x32>; +- dma-names = "rx", "tx"; +- }; +- ssiu47: ssiu-39 { +- dmas = <&audma0 0x33>, <&audma1 0x34>; +- dma-names = "rx", "tx"; +- }; +- ssiu50: ssiu-40 { +- dmas = <&audma0 0x73>, <&audma1 0x74>; +- dma-names = "rx", "tx"; +- }; +- ssiu60: ssiu-41 { +- dmas = <&audma0 0x75>, <&audma1 0x76>; +- dma-names = "rx", "tx"; +- }; +- ssiu70: ssiu-42 { +- dmas = <&audma0 0x79>, <&audma1 0x7a>; +- dma-names = "rx", "tx"; +- }; +- ssiu80: ssiu-43 { +- dmas = <&audma0 0x7b>, <&audma1 0x7c>; +- dma-names = "rx", "tx"; +- }; +- ssiu90: ssiu-44 { +- dmas = <&audma0 0x7d>, <&audma1 0x7e>; +- dma-names = "rx", "tx"; +- }; +- ssiu91: ssiu-45 { +- dmas = <&audma0 0x7F>, <&audma1 0x80>; +- dma-names = "rx", "tx"; +- }; +- ssiu92: ssiu-46 { +- dmas = <&audma0 0x81>, <&audma1 0x82>; +- dma-names = "rx", "tx"; +- }; +- ssiu93: ssiu-47 { +- dmas = <&audma0 0x83>, <&audma1 0x84>; +- dma-names = "rx", "tx"; +- }; +- ssiu94: ssiu-48 { +- dmas = <&audma0 0xA3>, <&audma1 0xA4>; +- dma-names = "rx", "tx"; +- }; +- ssiu95: ssiu-49 { +- dmas = <&audma0 0xA5>, <&audma1 0xA6>; +- dma-names = "rx", "tx"; +- }; +- ssiu96: ssiu-50 { +- dmas = <&audma0 0xA7>, <&audma1 0xA8>; +- dma-names = "rx", "tx"; +- }; +- ssiu97: ssiu-51 { +- dmas = <&audma0 0xA9>, <&audma1 0xAA>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssi { +- ssi0: ssi-0 { +- interrupts = ; +- dmas = <&audma0 0x01>, <&audma1 0x02>; +- dma-names = "rx", "tx"; +- }; +- ssi1: ssi-1 { +- interrupts = ; +- dmas = <&audma0 0x03>, <&audma1 0x04>; +- dma-names = "rx", "tx"; +- }; +- ssi2: ssi-2 { +- interrupts = ; +- dmas = <&audma0 0x05>, <&audma1 0x06>; +- dma-names = "rx", "tx"; +- }; +- ssi3: ssi-3 { +- interrupts = ; +- dmas = <&audma0 0x07>, <&audma1 0x08>; +- dma-names = "rx", "tx"; +- }; +- ssi4: ssi-4 { +- interrupts = ; +- dmas = <&audma0 0x09>, <&audma1 0x0a>; +- dma-names = "rx", "tx"; +- }; +- ssi5: ssi-5 { +- interrupts = ; +- dmas = <&audma0 0x0b>, <&audma1 0x0c>; +- dma-names = "rx", "tx"; +- }; +- ssi6: ssi-6 { +- interrupts = ; +- dmas = <&audma0 0x0d>, <&audma1 0x0e>; +- dma-names = "rx", "tx"; +- }; +- ssi7: ssi-7 { +- interrupts = ; +- dmas = <&audma0 0x0f>, <&audma1 0x10>; +- dma-names = "rx", "tx"; +- }; +- ssi8: ssi-8 { +- interrupts = ; +- dmas = <&audma0 0x11>, <&audma1 0x12>; +- dma-names = "rx", "tx"; +- }; +- ssi9: ssi-9 { +- interrupts = ; +- dmas = <&audma0 0x13>, <&audma1 0x14>; +- dma-names = "rx", "tx"; +- }; +- }; +- }; +- +- audma0: dma-controller@ec700000 { +- compatible = "renesas,dmac-r8a774e1", +- "renesas,rcar-dmac"; +- reg = <0 0xec700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 502>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 502>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, +- <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, +- <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, +- <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, +- <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, +- <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, +- <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, +- <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; +- }; +- +- audma1: dma-controller@ec720000 { +- compatible = "renesas,dmac-r8a774e1", +- "renesas,rcar-dmac"; +- reg = <0 0xec720000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 501>; +- clock-names = "fck"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 501>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, +- <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, +- <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, +- <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, +- <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, +- <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, +- <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, +- <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; +- }; +- +- xhci0: usb@ee000000 { +- compatible = "renesas,xhci-r8a774e1", +- "renesas,rcar-gen3-xhci"; +- reg = <0 0xee000000 0 0xc00>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- status = "disabled"; +- }; +- +- usb3_peri0: usb@ee020000 { +- compatible = "renesas,r8a774e1-usb3-peri", +- "renesas,rcar-gen3-usb3-peri"; +- reg = <0 0xee020000 0 0x400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- status = "disabled"; +- }; +- +- ohci0: usb@ee080000 { +- compatible = "generic-ohci"; +- reg = <0 0xee080000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- ohci1: usb@ee0a0000 { +- compatible = "generic-ohci"; +- reg = <0 0xee0a0000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 702>; +- phys = <&usb2_phy1 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- status = "disabled"; +- }; +- +- ehci0: usb@ee080100 { +- compatible = "generic-ehci"; +- reg = <0 0xee080100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 2>; +- phy-names = "usb"; +- companion = <&ohci0>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- ehci1: usb@ee0a0100 { +- compatible = "generic-ehci"; +- reg = <0 0xee0a0100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 702>; +- phys = <&usb2_phy1 2>; +- phy-names = "usb"; +- companion = <&ohci1>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- status = "disabled"; +- }; +- +- usb2_phy0: usb-phy@ee080200 { +- compatible = "renesas,usb2-phy-r8a774e1", +- "renesas,rcar-gen3-usb2-phy"; +- reg = <0 0xee080200 0 0x700>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- usb2_phy1: usb-phy@ee0a0200 { +- compatible = "renesas,usb2-phy-r8a774e1", +- "renesas,rcar-gen3-usb2-phy"; +- reg = <0 0xee0a0200 0 0x700>; +- clocks = <&cpg CPG_MOD 702>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a774e1", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee100000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- iommus = <&ipmmu_ds1 32>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ee120000 { +- compatible = "renesas,sdhi-r8a774e1", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee120000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 313>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 313>; +- iommus = <&ipmmu_ds1 33>; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a774e1", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee140000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 312>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 312>; +- iommus = <&ipmmu_ds1 34>; +- status = "disabled"; +- }; +- +- sdhi3: mmc@ee160000 { +- compatible = "renesas,sdhi-r8a774e1", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee160000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 311>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 311>; +- iommus = <&ipmmu_ds1 35>; +- status = "disabled"; +- }; +- +- rpc: spi@ee200000 { +- compatible = "renesas,r8a774e1-rpc-if", +- "renesas,rcar-gen3-rpc-if"; +- reg = <0 0xee200000 0 0x200>, +- <0 0x08000000 0 0x4000000>, +- <0 0xee208000 0 0x100>; +- reg-names = "regs", "dirmap", "wbuf"; +- interrupts = ; +- clocks = <&cpg CPG_MOD 917>; +- clock-names = "rpc"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 917>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- sata: sata@ee300000 { +- compatible = "renesas,sata-r8a774e1", +- "renesas,rcar-gen3-sata"; +- reg = <0 0xee300000 0 0x200000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 815>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 815>; +- iommus = <&ipmmu_hc 2>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1010000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x0 0xf1010000 0 0x1000>, +- <0x0 0xf1020000 0 0x20000>, +- <0x0 0xf1040000 0 0x20000>, +- <0x0 0xf1060000 0 0x20000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- pciec0: pcie@fe000000 { +- compatible = "renesas,pcie-r8a774e1", +- "renesas,pcie-rcar-gen3"; +- reg = <0 0xfe000000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, +- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, +- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, +- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 319>; +- status = "disabled"; +- }; +- +- pciec1: pcie@ee800000 { +- compatible = "renesas,pcie-r8a774e1", +- "renesas,pcie-rcar-gen3"; +- reg = <0 0xee800000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, +- <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, +- <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, +- <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 318>; +- status = "disabled"; +- }; +- +- pciec0_ep: pcie-ep@fe000000 { +- compatible = "renesas,r8a774e1-pcie-ep", +- "renesas,rcar-gen3-pcie-ep"; +- reg = <0x0 0xfe000000 0 0x80000>, +- <0x0 0xfe100000 0 0x100000>, +- <0x0 0xfe200000 0 0x200000>, +- <0x0 0x30000000 0 0x8000000>, +- <0x0 0x38000000 0 0x8000000>; +- reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 319>; +- clock-names = "pcie"; +- resets = <&cpg 319>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pciec1_ep: pcie-ep@ee800000 { +- compatible = "renesas,r8a774e1-pcie-ep", +- "renesas,rcar-gen3-pcie-ep"; +- reg = <0x0 0xee800000 0 0x80000>, +- <0x0 0xee900000 0 0x100000>, +- <0x0 0xeea00000 0 0x200000>, +- <0x0 0xc0000000 0 0x8000000>, +- <0x0 0xc8000000 0 0x8000000>; +- reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 318>; +- clock-names = "pcie"; +- resets = <&cpg 318>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- vspbc: vsp@fe920000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe920000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 624>; +- power-domains = <&sysc R8A774E1_PD_A3VP>; +- resets = <&cpg 624>; +- +- renesas,fcp = <&fcpvb1>; +- }; +- +- vspbd: vsp@fe960000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe960000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 626>; +- power-domains = <&sysc R8A774E1_PD_A3VP>; +- resets = <&cpg 626>; +- +- renesas,fcp = <&fcpvb0>; +- }; +- +- vspd0: vsp@fea20000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea20000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 623>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 623>; +- +- renesas,fcp = <&fcpvd0>; +- }; +- +- vspd1: vsp@fea28000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea28000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 622>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 622>; +- +- renesas,fcp = <&fcpvd1>; +- }; +- +- vspi0: vsp@fe9a0000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe9a0000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 631>; +- power-domains = <&sysc R8A774E1_PD_A3VP>; +- resets = <&cpg 631>; +- +- renesas,fcp = <&fcpvi0>; +- }; +- +- vspi1: vsp@fe9b0000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe9b0000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 630>; +- power-domains = <&sysc R8A774E1_PD_A3VP>; +- resets = <&cpg 630>; +- +- renesas,fcp = <&fcpvi1>; +- }; +- +- fdp1@fe940000 { +- compatible = "renesas,fdp1"; +- reg = <0 0xfe940000 0 0x2400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 119>; +- power-domains = <&sysc R8A774E1_PD_A3VP>; +- resets = <&cpg 119>; +- renesas,fcp = <&fcpf0>; +- }; +- +- fdp1@fe944000 { +- compatible = "renesas,fdp1"; +- reg = <0 0xfe944000 0 0x2400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 118>; +- power-domains = <&sysc R8A774E1_PD_A3VP>; +- resets = <&cpg 118>; +- renesas,fcp = <&fcpf1>; +- }; +- +- fcpf0: fcp@fe950000 { +- compatible = "renesas,fcpf"; +- reg = <0 0xfe950000 0 0x200>; +- clocks = <&cpg CPG_MOD 615>; +- power-domains = <&sysc R8A774E1_PD_A3VP>; +- resets = <&cpg 615>; +- }; +- +- fcpf1: fcp@fe951000 { +- compatible = "renesas,fcpf"; +- reg = <0 0xfe951000 0 0x200>; +- clocks = <&cpg CPG_MOD 614>; +- power-domains = <&sysc R8A774E1_PD_A3VP>; +- resets = <&cpg 614>; +- }; +- +- fcpvb0: fcp@fe96f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe96f000 0 0x200>; +- clocks = <&cpg CPG_MOD 607>; +- power-domains = <&sysc R8A774E1_PD_A3VP>; +- resets = <&cpg 607>; +- }; +- +- fcpvb1: fcp@fe92f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe92f000 0 0x200>; +- clocks = <&cpg CPG_MOD 606>; +- power-domains = <&sysc R8A774E1_PD_A3VP>; +- resets = <&cpg 606>; +- }; +- +- fcpvi0: fcp@fe9af000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe9af000 0 0x200>; +- clocks = <&cpg CPG_MOD 611>; +- power-domains = <&sysc R8A774E1_PD_A3VP>; +- resets = <&cpg 611>; +- }; +- +- fcpvi1: fcp@fe9bf000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe9bf000 0 0x200>; +- clocks = <&cpg CPG_MOD 610>; +- power-domains = <&sysc R8A774E1_PD_A3VP>; +- resets = <&cpg 610>; +- }; +- +- fcpvd0: fcp@fea27000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea27000 0 0x200>; +- clocks = <&cpg CPG_MOD 603>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 603>; +- }; +- +- fcpvd1: fcp@fea2f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea2f000 0 0x200>; +- clocks = <&cpg CPG_MOD 602>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 602>; +- }; +- +- csi20: csi2@fea80000 { +- compatible = "renesas,r8a774e1-csi2"; +- reg = <0 0xfea80000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 714>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 714>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi20vin0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin0csi20>; +- }; +- csi20vin1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin1csi20>; +- }; +- csi20vin2: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&vin2csi20>; +- }; +- csi20vin3: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&vin3csi20>; +- }; +- csi20vin4: endpoint@4 { +- reg = <4>; +- remote-endpoint = <&vin4csi20>; +- }; +- csi20vin5: endpoint@5 { +- reg = <5>; +- remote-endpoint = <&vin5csi20>; +- }; +- csi20vin6: endpoint@6 { +- reg = <6>; +- remote-endpoint = <&vin6csi20>; +- }; +- csi20vin7: endpoint@7 { +- reg = <7>; +- remote-endpoint = <&vin7csi20>; +- }; +- }; +- }; +- }; +- +- csi40: csi2@feaa0000 { +- compatible = "renesas,r8a774e1-csi2"; +- reg = <0 0xfeaa0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi40vin0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin0csi40>; +- }; +- csi40vin1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin1csi40>; +- }; +- csi40vin2: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&vin2csi40>; +- }; +- csi40vin3: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&vin3csi40>; +- }; +- }; +- }; +- }; +- +- hdmi0: hdmi@fead0000 { +- compatible = "renesas,r8a774e1-hdmi", +- "renesas,rcar-gen3-hdmi"; +- reg = <0 0xfead0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 729>, +- <&cpg CPG_CORE R8A774E1_CLK_HDMI>; +- clock-names = "iahb", "isfr"; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 729>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- dw_hdmi0_in: endpoint { +- remote-endpoint = <&du_out_hdmi0>; +- }; +- }; +- port@1 { +- reg = <1>; +- }; +- port@2 { +- /* HDMI sound */ +- reg = <2>; +- }; +- }; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a774e1"; +- reg = <0 0xfeb00000 0 0x80000>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 721>; +- clock-names = "du.0", "du.1", "du.3"; +- resets = <&cpg 724>, <&cpg 722>; +- reset-names = "du.0", "du.3"; +- status = "disabled"; +- +- renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb: endpoint { +- }; +- }; +- port@1 { +- reg = <1>; +- du_out_hdmi0: endpoint { +- remote-endpoint = <&dw_hdmi0_in>; +- }; +- }; +- port@2 { +- reg = <2>; +- du_out_lvds0: endpoint { +- remote-endpoint = <&lvds0_in>; +- }; +- }; +- }; +- }; +- +- lvds0: lvds@feb90000 { +- compatible = "renesas,r8a774e1-lvds"; +- reg = <0 0xfeb90000 0 0x14>; +- clocks = <&cpg CPG_MOD 727>; +- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; +- resets = <&cpg 727>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds0_in: endpoint { +- remote-endpoint = <&du_out_lvds0>; +- }; +- }; +- port@1 { +- reg = <1>; +- lvds0_out: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@fff00044 { +- compatible = "renesas,prr"; +- reg = <0 0xfff00044 0 4>; +- }; +- }; +- +- thermal-zones { +- sensor1_thermal: sensor1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 0>; +- sustainable-power = <6313>; +- +- trips { +- sensor1_crit: sensor1-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- sensor2_thermal: sensor2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 1>; +- sustainable-power = <6313>; +- +- trips { +- sensor2_crit: sensor2-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- sensor3_thermal: sensor3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 2>; +- sustainable-power = <6313>; +- +- trips { +- target: trip-point1 { +- temperature = <100000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- +- sensor3_crit: sensor3-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&target>; +- cooling-device = <&a57_0 0 2>; +- contribution = <1024>; +- }; +- +- map1 { +- trip = <&target>; +- cooling-device = <&a53_0 0 2>; +- contribution = <1024>; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; +- }; +- +- /* External USB clocks - can be overridden by the board */ +- usb3s0_clk: usb3s0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- usb_extal_clk: usb_extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77950-salvator-x.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77950-salvator-x.dts +deleted file mode 100644 +index c6ca61a8ed40..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77950-salvator-x.dts ++++ /dev/null +@@ -1,49 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Salvator-X board with R-Car H3 ES1.x +- * +- * Copyright (C) 2015 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a77950.dtsi" +-#include "salvator-x.dtsi" +- +-/ { +- model = "Renesas Salvator-X board based on r8a77950"; +- compatible = "renesas,salvator-x", "renesas,r8a7795"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x38000000>; +- }; +- +- memory@500000000 { +- device_type = "memory"; +- reg = <0x5 0x00000000 0x0 0x40000000>; +- }; +- +- memory@600000000 { +- device_type = "memory"; +- reg = <0x6 0x00000000 0x0 0x40000000>; +- }; +- +- memory@700000000 { +- device_type = "memory"; +- reg = <0x7 0x00000000 0x0 0x40000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>, +- <&cpg CPG_MOD 721>, +- <&versaclock5 1>, +- <&x21_clk>, +- <&x22_clk>, +- <&versaclock5 2>; +- clock-names = "du.0", "du.1", "du.2", "du.3", +- "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77950-ulcb-kf.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77950-ulcb-kf.dts +deleted file mode 100644 +index 85f008ef63de..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77950-ulcb-kf.dts ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the H3ULCB Kingfisher board with R-Car H3 ES1.x +- * +- * Copyright (C) 2017 Renesas Electronics Corp. +- * Copyright (C) 2017 Cogent Embedded, Inc. +- */ +- +-#include "r8a77950-ulcb.dts" +-#include "ulcb-kf.dtsi" +- +-/ { +- model = "Renesas H3ULCB Kingfisher board based on r8a77950"; +- compatible = "shimafuji,kingfisher", "renesas,h3ulcb", +- "renesas,r8a7795"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77950-ulcb.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77950-ulcb.dts +deleted file mode 100644 +index 5340579931e3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77950-ulcb.dts ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board with R-Car H3 ES1.x +- * +- * Copyright (C) 2016 Renesas Electronics Corp. +- * Copyright (C) 2016 Cogent Embedded, Inc. +- */ +- +-/dts-v1/; +-#include "r8a77950.dtsi" +-#include "ulcb.dtsi" +- +-/ { +- model = "Renesas H3ULCB board based on r8a77950"; +- compatible = "renesas,h3ulcb", "renesas,r8a7795"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x38000000>; +- }; +- +- memory@500000000 { +- device_type = "memory"; +- reg = <0x5 0x00000000 0x0 0x40000000>; +- }; +- +- memory@600000000 { +- device_type = "memory"; +- reg = <0x6 0x00000000 0x0 0x40000000>; +- }; +- +- memory@700000000 { +- device_type = "memory"; +- reg = <0x7 0x00000000 0x0 0x40000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77950.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r8a77950.dtsi +deleted file mode 100644 +index 57eb88177e92..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77950.dtsi ++++ /dev/null +@@ -1,330 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Car H3 (R8A77950) SoC +- * +- * Copyright (C) 2015 Renesas Electronics Corp. +- */ +- +-#include "r8a77951.dtsi" +- +-#undef SOC_HAS_USB2_CH3 +- +-&audma0 { +- iommus = <&ipmmu_mp1 0>, <&ipmmu_mp1 1>, +- <&ipmmu_mp1 2>, <&ipmmu_mp1 3>, +- <&ipmmu_mp1 4>, <&ipmmu_mp1 5>, +- <&ipmmu_mp1 6>, <&ipmmu_mp1 7>, +- <&ipmmu_mp1 8>, <&ipmmu_mp1 9>, +- <&ipmmu_mp1 10>, <&ipmmu_mp1 11>, +- <&ipmmu_mp1 12>, <&ipmmu_mp1 13>, +- <&ipmmu_mp1 14>, <&ipmmu_mp1 15>; +-}; +- +-&audma1 { +- iommus = <&ipmmu_mp1 16>, <&ipmmu_mp1 17>, +- <&ipmmu_mp1 18>, <&ipmmu_mp1 19>, +- <&ipmmu_mp1 20>, <&ipmmu_mp1 21>, +- <&ipmmu_mp1 22>, <&ipmmu_mp1 23>, +- <&ipmmu_mp1 24>, <&ipmmu_mp1 25>, +- <&ipmmu_mp1 26>, <&ipmmu_mp1 27>, +- <&ipmmu_mp1 28>, <&ipmmu_mp1 29>, +- <&ipmmu_mp1 30>, <&ipmmu_mp1 31>; +-}; +- +-&cluster0_opp { +- /delete-node/ opp-1600000000; +- /delete-node/ opp-1700000000; +-}; +- +-&du { +- renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>; +-}; +- +-&fcpvb1 { +- iommus = <&ipmmu_vp0 7>; +-}; +- +-&fcpf1 { +- iommus = <&ipmmu_vp0 1>; +-}; +- +-&fcpvi1 { +- iommus = <&ipmmu_vp0 9>; +-}; +- +-&fcpvd2 { +- iommus = <&ipmmu_vi0 10>; +-}; +- +-&gpio1 { +- gpio-ranges = <&pfc 0 32 28>; +-}; +- +-&ipmmu_vi0 { +- renesas,ipmmu-main = <&ipmmu_mm 11>; +-}; +- +-&ipmmu_vp0 { +- renesas,ipmmu-main = <&ipmmu_mm 12>; +-}; +- +-&ipmmu_vc0 { +- renesas,ipmmu-main = <&ipmmu_mm 9>; +-}; +- +-&ipmmu_vc1 { +- renesas,ipmmu-main = <&ipmmu_mm 10>; +-}; +- +-&ipmmu_rt { +- renesas,ipmmu-main = <&ipmmu_mm 7>; +-}; +- +-&soc { +- /delete-node/ dma-controller@e6460000; +- /delete-node/ dma-controller@e6470000; +- +- ipmmu_mp1: iommu@ec680000 { +- compatible = "renesas,ipmmu-r8a7795"; +- reg = <0 0xec680000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 5>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_sy: iommu@e7730000 { +- compatible = "renesas,ipmmu-r8a7795"; +- reg = <0 0xe7730000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 8>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- /delete-node/ iommu@fd950000; +- /delete-node/ iommu@fd960000; +- /delete-node/ iommu@fd970000; +- /delete-node/ iommu@febe0000; +- /delete-node/ iommu@fe980000; +- +- xhci1: usb@ee040000 { +- compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; +- reg = <0 0xee040000 0 0xc00>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 327>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 327>; +- status = "disabled"; +- }; +- +- /delete-node/ usb@e659c000; +- /delete-node/ usb@ee0e0000; +- /delete-node/ usb@ee0e0100; +- +- /delete-node/ usb-phy@ee0e0200; +- +- fdp1@fe948000 { +- compatible = "renesas,fdp1"; +- reg = <0 0xfe948000 0 0x2400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 117>; +- power-domains = <&sysc R8A7795_PD_A3VP>; +- resets = <&cpg 117>; +- renesas,fcp = <&fcpf2>; +- }; +- +- fcpf2: fcp@fe952000 { +- compatible = "renesas,fcpf"; +- reg = <0 0xfe952000 0 0x200>; +- clocks = <&cpg CPG_MOD 613>; +- power-domains = <&sysc R8A7795_PD_A3VP>; +- resets = <&cpg 613>; +- iommus = <&ipmmu_vp0 2>; +- }; +- +- fcpvd3: fcp@fea3f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea3f000 0 0x200>; +- clocks = <&cpg CPG_MOD 600>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 600>; +- iommus = <&ipmmu_vi0 11>; +- }; +- +- fcpvi2: fcp@fe9cf000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe9cf000 0 0x200>; +- clocks = <&cpg CPG_MOD 609>; +- power-domains = <&sysc R8A7795_PD_A3VP>; +- resets = <&cpg 609>; +- iommus = <&ipmmu_vp0 10>; +- }; +- +- vspd3: vsp@fea38000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea38000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 620>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 620>; +- +- renesas,fcp = <&fcpvd3>; +- }; +- +- vspi2: vsp@fe9c0000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe9c0000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 629>; +- power-domains = <&sysc R8A7795_PD_A3VP>; +- resets = <&cpg 629>; +- +- renesas,fcp = <&fcpvi2>; +- }; +- +- csi21: csi2@fea90000 { +- compatible = "renesas,r8a7795-csi2"; +- reg = <0 0xfea90000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 713>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 713>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi21vin0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin0csi21>; +- }; +- csi21vin1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin1csi21>; +- }; +- csi21vin2: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&vin2csi21>; +- }; +- csi21vin3: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&vin3csi21>; +- }; +- csi21vin4: endpoint@4 { +- reg = <4>; +- remote-endpoint = <&vin4csi21>; +- }; +- csi21vin5: endpoint@5 { +- reg = <5>; +- remote-endpoint = <&vin5csi21>; +- }; +- csi21vin6: endpoint@6 { +- reg = <6>; +- remote-endpoint = <&vin6csi21>; +- }; +- csi21vin7: endpoint@7 { +- reg = <7>; +- remote-endpoint = <&vin7csi21>; +- }; +- }; +- }; +- }; +-}; +- +-&vin0 { +- ports { +- port@1 { +- vin0csi21: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&csi21vin0>; +- }; +- }; +- }; +-}; +- +-&vin1 { +- ports { +- port@1 { +- vin1csi21: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&csi21vin1>; +- }; +- }; +- }; +-}; +- +-&vin2 { +- ports { +- port@1 { +- vin2csi21: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&csi21vin2>; +- }; +- }; +- }; +-}; +- +-&vin3 { +- ports { +- port@1 { +- vin3csi21: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&csi21vin3>; +- }; +- }; +- }; +-}; +- +-&vin4 { +- ports { +- port@1 { +- vin4csi21: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&csi21vin4>; +- }; +- }; +- }; +-}; +- +-&vin5 { +- ports { +- port@1 { +- vin5csi21: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&csi21vin5>; +- }; +- }; +- }; +-}; +- +-&vin6 { +- ports { +- port@1 { +- vin6csi21: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&csi21vin6>; +- }; +- }; +- }; +-}; +- +-&vin7 { +- ports { +- port@1 { +- vin7csi21: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&csi21vin7>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77951-salvator-x.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77951-salvator-x.dts +deleted file mode 100644 +index d8e655ba81bd..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77951-salvator-x.dts ++++ /dev/null +@@ -1,49 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Salvator-X board with R-Car H3 ES2.0 +- * +- * Copyright (C) 2015 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a77951.dtsi" +-#include "salvator-x.dtsi" +- +-/ { +- model = "Renesas Salvator-X board based on r8a77951"; +- compatible = "renesas,salvator-x", "renesas,r8a7795"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x38000000>; +- }; +- +- memory@500000000 { +- device_type = "memory"; +- reg = <0x5 0x00000000 0x0 0x40000000>; +- }; +- +- memory@600000000 { +- device_type = "memory"; +- reg = <0x6 0x00000000 0x0 0x40000000>; +- }; +- +- memory@700000000 { +- device_type = "memory"; +- reg = <0x7 0x00000000 0x0 0x40000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>, +- <&cpg CPG_MOD 721>, +- <&versaclock5 1>, +- <&x21_clk>, +- <&x22_clk>, +- <&versaclock5 2>; +- clock-names = "du.0", "du.1", "du.2", "du.3", +- "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77951-salvator-xs.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77951-salvator-xs.dts +deleted file mode 100644 +index 7f9fa842f01e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77951-salvator-xs.dts ++++ /dev/null +@@ -1,49 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Salvator-X 2nd version board with R-Car H3 ES2.0+ +- * +- * Copyright (C) 2015-2017 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a77951.dtsi" +-#include "salvator-xs.dtsi" +- +-/ { +- model = "Renesas Salvator-X 2nd version board based on r8a77951"; +- compatible = "renesas,salvator-xs", "renesas,r8a7795"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x38000000>; +- }; +- +- memory@500000000 { +- device_type = "memory"; +- reg = <0x5 0x00000000 0x0 0x40000000>; +- }; +- +- memory@600000000 { +- device_type = "memory"; +- reg = <0x6 0x00000000 0x0 0x40000000>; +- }; +- +- memory@700000000 { +- device_type = "memory"; +- reg = <0x7 0x00000000 0x0 0x40000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>, +- <&cpg CPG_MOD 721>, +- <&versaclock6 1>, +- <&x21_clk>, +- <&x22_clk>, +- <&versaclock6 2>; +- clock-names = "du.0", "du.1", "du.2", "du.3", +- "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77951-ulcb-kf.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77951-ulcb-kf.dts +deleted file mode 100644 +index 2e58a27aa276..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77951-ulcb-kf.dts ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the H3ULCB Kingfisher board with R-Car H3 ES2.0+ +- * +- * Copyright (C) 2017 Renesas Electronics Corp. +- * Copyright (C) 2017 Cogent Embedded, Inc. +- */ +- +-#include "r8a77951-ulcb.dts" +-#include "ulcb-kf.dtsi" +- +-/ { +- model = "Renesas H3ULCB Kingfisher board based on r8a77951"; +- compatible = "shimafuji,kingfisher", "renesas,h3ulcb", +- "renesas,r8a7795"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77951-ulcb.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77951-ulcb.dts +deleted file mode 100644 +index 06d4e948eb0f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77951-ulcb.dts ++++ /dev/null +@@ -1,50 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board with R-Car H3 ES2.0+ +- * +- * Copyright (C) 2016 Renesas Electronics Corp. +- * Copyright (C) 2016 Cogent Embedded, Inc. +- */ +- +-/dts-v1/; +-#include "r8a77951.dtsi" +-#include "ulcb.dtsi" +- +-/ { +- model = "Renesas H3ULCB board based on r8a77951"; +- compatible = "renesas,h3ulcb", "renesas,r8a7795"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x38000000>; +- }; +- +- memory@500000000 { +- device_type = "memory"; +- reg = <0x5 0x00000000 0x0 0x40000000>; +- }; +- +- memory@600000000 { +- device_type = "memory"; +- reg = <0x6 0x00000000 0x0 0x40000000>; +- }; +- +- memory@700000000 { +- device_type = "memory"; +- reg = <0x7 0x00000000 0x0 0x40000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>, +- <&cpg CPG_MOD 721>, +- <&versaclock5 1>, +- <&versaclock5 3>, +- <&versaclock5 4>, +- <&versaclock5 2>; +- clock-names = "du.0", "du.1", "du.2", "du.3", +- "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77951.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r8a77951.dtsi +deleted file mode 100644 +index 193d81be40fc..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77951.dtsi ++++ /dev/null +@@ -1,3463 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Car H3 (R8A77951) SoC +- * +- * Copyright (C) 2015 Renesas Electronics Corp. +- */ +- +-#include +-#include +-#include +- +-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 +- +-#define SOC_HAS_HDMI1 +-#define SOC_HAS_SATA +-#define SOC_HAS_USB2_CH2 +-#define SOC_HAS_USB2_CH3 +- +-/ { +- compatible = "renesas,r8a7795"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c_dvfs; +- }; +- +- /* +- * The external audio clocks are configured as 0 Hz fixed frequency +- * clocks by default. +- * Boards that provide audio clocks should override them. +- */ +- audio_clk_a: audio_clk_a { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_b: audio_clk_b { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_c: audio_clk_c { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* External CAN clock - to be overridden by boards that provide it */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- cluster0_opp: opp_table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <830000>; +- clock-latency-ns = <300000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <830000>; +- clock-latency-ns = <300000>; +- }; +- opp-1500000000 { +- opp-hz = /bits/ 64 <1500000000>; +- opp-microvolt = <830000>; +- clock-latency-ns = <300000>; +- opp-suspend; +- }; +- opp-1600000000 { +- opp-hz = /bits/ 64 <1600000000>; +- opp-microvolt = <900000>; +- clock-latency-ns = <300000>; +- turbo-mode; +- }; +- opp-1700000000 { +- opp-hz = /bits/ 64 <1700000000>; +- opp-microvolt = <960000>; +- clock-latency-ns = <300000>; +- turbo-mode; +- }; +- }; +- +- cluster1_opp: opp_table1 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&a57_0>; +- }; +- core1 { +- cpu = <&a57_1>; +- }; +- core2 { +- cpu = <&a57_2>; +- }; +- core3 { +- cpu = <&a57_3>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&a53_0>; +- }; +- core1 { +- cpu = <&a53_1>; +- }; +- core2 { +- cpu = <&a53_2>; +- }; +- core3 { +- cpu = <&a53_3>; +- }; +- }; +- }; +- +- a57_0: cpu@0 { +- compatible = "arm,cortex-a57"; +- reg = <0x0>; +- device_type = "cpu"; +- power-domains = <&sysc R8A7795_PD_CA57_CPU0>; +- next-level-cache = <&L2_CA57>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- dynamic-power-coefficient = <854>; +- clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; +- operating-points-v2 = <&cluster0_opp>; +- capacity-dmips-mhz = <1024>; +- #cooling-cells = <2>; +- }; +- +- a57_1: cpu@1 { +- compatible = "arm,cortex-a57"; +- reg = <0x1>; +- device_type = "cpu"; +- power-domains = <&sysc R8A7795_PD_CA57_CPU1>; +- next-level-cache = <&L2_CA57>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; +- operating-points-v2 = <&cluster0_opp>; +- capacity-dmips-mhz = <1024>; +- #cooling-cells = <2>; +- }; +- +- a57_2: cpu@2 { +- compatible = "arm,cortex-a57"; +- reg = <0x2>; +- device_type = "cpu"; +- power-domains = <&sysc R8A7795_PD_CA57_CPU2>; +- next-level-cache = <&L2_CA57>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; +- operating-points-v2 = <&cluster0_opp>; +- capacity-dmips-mhz = <1024>; +- #cooling-cells = <2>; +- }; +- +- a57_3: cpu@3 { +- compatible = "arm,cortex-a57"; +- reg = <0x3>; +- device_type = "cpu"; +- power-domains = <&sysc R8A7795_PD_CA57_CPU3>; +- next-level-cache = <&L2_CA57>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; +- operating-points-v2 = <&cluster0_opp>; +- capacity-dmips-mhz = <1024>; +- #cooling-cells = <2>; +- }; +- +- a53_0: cpu@100 { +- compatible = "arm,cortex-a53"; +- reg = <0x100>; +- device_type = "cpu"; +- power-domains = <&sysc R8A7795_PD_CA53_CPU0>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_1>; +- #cooling-cells = <2>; +- dynamic-power-coefficient = <277>; +- clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <535>; +- }; +- +- a53_1: cpu@101 { +- compatible = "arm,cortex-a53"; +- reg = <0x101>; +- device_type = "cpu"; +- power-domains = <&sysc R8A7795_PD_CA53_CPU1>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_1>; +- clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <535>; +- }; +- +- a53_2: cpu@102 { +- compatible = "arm,cortex-a53"; +- reg = <0x102>; +- device_type = "cpu"; +- power-domains = <&sysc R8A7795_PD_CA53_CPU2>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_1>; +- clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <535>; +- }; +- +- a53_3: cpu@103 { +- compatible = "arm,cortex-a53"; +- reg = <0x103>; +- device_type = "cpu"; +- power-domains = <&sysc R8A7795_PD_CA53_CPU3>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_1>; +- clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <535>; +- }; +- +- L2_CA57: cache-controller-0 { +- compatible = "cache"; +- power-domains = <&sysc R8A7795_PD_CA57_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- +- L2_CA53: cache-controller-1 { +- compatible = "cache"; +- power-domains = <&sysc R8A7795_PD_CA53_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP_0: cpu-sleep-0 { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x0010000>; +- local-timer-stop; +- entry-latency-us = <400>; +- exit-latency-us = <500>; +- min-residency-us = <4000>; +- }; +- +- CPU_SLEEP_1: cpu-sleep-1 { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x0010000>; +- local-timer-stop; +- entry-latency-us = <700>; +- exit-latency-us = <700>; +- min-residency-us = <5000>; +- }; +- }; +- }; +- +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- extalr_clk: extalr { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- /* External PCIe clock - can be overridden by the board */ +- pcie_bus_clk: pcie_bus { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- pmu_a53 { +- compatible = "arm,cortex-a53-pmu"; +- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&a53_0>, +- <&a53_1>, +- <&a53_2>, +- <&a53_3>; +- }; +- +- pmu_a57 { +- compatible = "arm,cortex-a57-pmu"; +- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&a57_0>, +- <&a57_1>, +- <&a57_2>, +- <&a57_3>; +- }; +- +- psci { +- compatible = "arm,psci-1.0", "arm,psci-0.2"; +- method = "smc"; +- }; +- +- /* External SCIF clock - to be overridden by boards that provide it */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- soc: soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a7795", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 16>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a7795", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 29>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a7795", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 15>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a7795", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 16>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a7795", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 18>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a7795", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- gpio6: gpio@e6055400 { +- compatible = "renesas,gpio-r8a7795", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055400 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 192 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 906>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 906>; +- }; +- +- gpio7: gpio@e6055800 { +- compatible = "renesas,gpio-r8a7795", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055800 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 224 4>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 905>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 905>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a7795"; +- reg = <0 0xe6060000 0 0x50c>; +- }; +- +- cmt0: timer@e60f0000 { +- compatible = "renesas,r8a7795-cmt0", +- "renesas,rcar-gen3-cmt0"; +- reg = <0 0xe60f0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 303>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 303>; +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a7795-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 302>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 302>; +- status = "disabled"; +- }; +- +- cmt2: timer@e6140000 { +- compatible = "renesas,r8a7795-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6140000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 301>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 301>; +- status = "disabled"; +- }; +- +- cmt3: timer@e6148000 { +- compatible = "renesas,r8a7795-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6148000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 300>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 300>; +- status = "disabled"; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a7795-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>, <&extalr_clk>; +- clock-names = "extal", "extalr"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a7795-rst"; +- reg = <0 0xe6160000 0 0x0200>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a7795-sysc"; +- reg = <0 0xe6180000 0 0x0400>; +- #power-domain-cells = <1>; +- }; +- +- tsc: thermal@e6198000 { +- compatible = "renesas,r8a7795-thermal"; +- reg = <0 0xe6198000 0 0x100>, +- <0 0xe61a0000 0 0x100>, +- <0 0xe61a8000 0 0x100>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 522>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 522>; +- #thermal-sensor-cells = <1>; +- }; +- +- intc_ex: interrupt-controller@e61c0000 { +- compatible = "renesas,intc-ex-r8a7795", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- tmu0: timer@e61e0000 { +- compatible = "renesas,tmu-r8a7795", "renesas,tmu"; +- reg = <0 0xe61e0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 125>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 125>; +- status = "disabled"; +- }; +- +- tmu1: timer@e6fc0000 { +- compatible = "renesas,tmu-r8a7795", "renesas,tmu"; +- reg = <0 0xe6fc0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- status = "disabled"; +- }; +- +- tmu2: timer@e6fd0000 { +- compatible = "renesas,tmu-r8a7795", "renesas,tmu"; +- reg = <0 0xe6fd0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 123>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 123>; +- status = "disabled"; +- }; +- +- tmu3: timer@e6fe0000 { +- compatible = "renesas,tmu-r8a7795", "renesas,tmu"; +- reg = <0 0xe6fe0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 122>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 122>; +- status = "disabled"; +- }; +- +- tmu4: timer@ffc00000 { +- compatible = "renesas,tmu-r8a7795", "renesas,tmu"; +- reg = <0 0xffc00000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 121>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 121>; +- status = "disabled"; +- }; +- +- i2c0: i2c@e6500000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7795", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6500000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- dmas = <&dmac1 0x91>, <&dmac1 0x90>, +- <&dmac2 0x91>, <&dmac2 0x90>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6508000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7795", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- dmas = <&dmac1 0x93>, <&dmac1 0x92>, +- <&dmac2 0x93>, <&dmac2 0x92>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6510000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7795", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6510000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- dmas = <&dmac1 0x95>, <&dmac1 0x94>, +- <&dmac2 0x95>, <&dmac2 0x94>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e66d0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7795", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- dmas = <&dmac0 0x97>, <&dmac0 0x96>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e66d8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7795", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 927>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 927>; +- dmas = <&dmac0 0x99>, <&dmac0 0x98>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c5: i2c@e66e0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7795", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 919>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 919>; +- dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c6: i2c@e66e8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7795", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 918>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 918>; +- dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c_dvfs: i2c@e60b0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7795", +- "renesas,rcar-gen3-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe60b0000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 926>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 926>; +- dmas = <&dmac0 0x11>, <&dmac0 0x10>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- hscif0: serial@e6540000 { +- compatible = "renesas,hscif-r8a7795", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6540000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 520>, +- <&cpg CPG_CORE R8A7795_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x31>, <&dmac1 0x30>, +- <&dmac2 0x31>, <&dmac2 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 520>; +- status = "disabled"; +- }; +- +- hscif1: serial@e6550000 { +- compatible = "renesas,hscif-r8a7795", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6550000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 519>, +- <&cpg CPG_CORE R8A7795_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x33>, <&dmac1 0x32>, +- <&dmac2 0x33>, <&dmac2 0x32>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 519>; +- status = "disabled"; +- }; +- +- hscif2: serial@e6560000 { +- compatible = "renesas,hscif-r8a7795", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6560000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 518>, +- <&cpg CPG_CORE R8A7795_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x35>, <&dmac1 0x34>, +- <&dmac2 0x35>, <&dmac2 0x34>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 518>; +- status = "disabled"; +- }; +- +- hscif3: serial@e66a0000 { +- compatible = "renesas,hscif-r8a7795", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66a0000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 517>, +- <&cpg CPG_CORE R8A7795_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x37>, <&dmac0 0x36>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 517>; +- status = "disabled"; +- }; +- +- hscif4: serial@e66b0000 { +- compatible = "renesas,hscif-r8a7795", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66b0000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 516>, +- <&cpg CPG_CORE R8A7795_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x39>, <&dmac0 0x38>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 516>; +- status = "disabled"; +- }; +- +- hsusb: usb@e6590000 { +- compatible = "renesas,usbhs-r8a7795", +- "renesas,rcar-gen3-usbhs"; +- reg = <0 0xe6590000 0 0x200>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; +- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, +- <&usb_dmac1 0>, <&usb_dmac1 1>; +- dma-names = "ch0", "ch1", "ch2", "ch3"; +- renesas,buswait = <11>; +- phys = <&usb2_phy0 3>; +- phy-names = "usb"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 704>, <&cpg 703>; +- status = "disabled"; +- }; +- +- hsusb3: usb@e659c000 { +- compatible = "renesas,usbhs-r8a7795", +- "renesas,rcar-gen3-usbhs"; +- reg = <0 0xe659c000 0 0x200>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 705>, <&cpg CPG_MOD 700>; +- dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, +- <&usb_dmac3 0>, <&usb_dmac3 1>; +- dma-names = "ch0", "ch1", "ch2", "ch3"; +- renesas,buswait = <11>; +- phys = <&usb2_phy3 3>; +- phy-names = "usb"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 705>, <&cpg 700>; +- status = "disabled"; +- }; +- +- usb_dmac0: dma-controller@e65a0000 { +- compatible = "renesas,r8a7795-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65a0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 330>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 330>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac1: dma-controller@e65b0000 { +- compatible = "renesas,r8a7795-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65b0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 331>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 331>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac2: dma-controller@e6460000 { +- compatible = "renesas,r8a7795-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe6460000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 326>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 326>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac3: dma-controller@e6470000 { +- compatible = "renesas,r8a7795-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe6470000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 329>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 329>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb3_phy0: usb-phy@e65ee000 { +- compatible = "renesas,r8a7795-usb3-phy", +- "renesas,rcar-gen3-usb3-phy"; +- reg = <0 0xe65ee000 0 0x90>; +- clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, +- <&usb_extal_clk>; +- clock-names = "usb3-if", "usb3s_clk", "usb_extal"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- arm_cc630p: crypto@e6601000 { +- compatible = "arm,cryptocell-630p-ree"; +- interrupts = ; +- reg = <0x0 0xe6601000 0 0x1000>; +- clocks = <&cpg CPG_MOD 229>; +- resets = <&cpg 229>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a7795", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, +- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, +- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, +- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, +- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, +- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, +- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, +- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; +- }; +- +- dmac1: dma-controller@e7300000 { +- compatible = "renesas,dmac-r8a7795", +- "renesas,rcar-dmac"; +- reg = <0 0xe7300000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, +- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, +- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, +- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, +- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, +- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, +- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, +- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; +- }; +- +- dmac2: dma-controller@e7310000 { +- compatible = "renesas,dmac-r8a7795", +- "renesas,rcar-dmac"; +- reg = <0 0xe7310000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 217>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 217>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, +- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, +- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, +- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, +- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, +- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, +- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, +- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; +- }; +- +- ipmmu_ds0: iommu@e6740000 { +- compatible = "renesas,ipmmu-r8a7795"; +- reg = <0 0xe6740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 0>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_ds1: iommu@e7740000 { +- compatible = "renesas,ipmmu-r8a7795"; +- reg = <0 0xe7740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 1>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_hc: iommu@e6570000 { +- compatible = "renesas,ipmmu-r8a7795"; +- reg = <0 0xe6570000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 2>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_ir: iommu@ff8b0000 { +- compatible = "renesas,ipmmu-r8a7795"; +- reg = <0 0xff8b0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 3>; +- power-domains = <&sysc R8A7795_PD_A3IR>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mm: iommu@e67b0000 { +- compatible = "renesas,ipmmu-r8a7795"; +- reg = <0 0xe67b0000 0 0x1000>; +- interrupts = , +- ; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mp0: iommu@ec670000 { +- compatible = "renesas,ipmmu-r8a7795"; +- reg = <0 0xec670000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 4>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_pv0: iommu@fd800000 { +- compatible = "renesas,ipmmu-r8a7795"; +- reg = <0 0xfd800000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 6>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_pv1: iommu@fd950000 { +- compatible = "renesas,ipmmu-r8a7795"; +- reg = <0 0xfd950000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 7>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_pv2: iommu@fd960000 { +- compatible = "renesas,ipmmu-r8a7795"; +- reg = <0 0xfd960000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 8>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_pv3: iommu@fd970000 { +- compatible = "renesas,ipmmu-r8a7795"; +- reg = <0 0xfd970000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 9>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_rt: iommu@ffc80000 { +- compatible = "renesas,ipmmu-r8a7795"; +- reg = <0 0xffc80000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 10>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vc0: iommu@fe6b0000 { +- compatible = "renesas,ipmmu-r8a7795"; +- reg = <0 0xfe6b0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 12>; +- power-domains = <&sysc R8A7795_PD_A3VC>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vc1: iommu@fe6f0000 { +- compatible = "renesas,ipmmu-r8a7795"; +- reg = <0 0xfe6f0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 13>; +- power-domains = <&sysc R8A7795_PD_A3VC>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vi0: iommu@febd0000 { +- compatible = "renesas,ipmmu-r8a7795"; +- reg = <0 0xfebd0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 14>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vi1: iommu@febe0000 { +- compatible = "renesas,ipmmu-r8a7795"; +- reg = <0 0xfebe0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 15>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vp0: iommu@fe990000 { +- compatible = "renesas,ipmmu-r8a7795"; +- reg = <0 0xfe990000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 16>; +- power-domains = <&sysc R8A7795_PD_A3VP>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vp1: iommu@fe980000 { +- compatible = "renesas,ipmmu-r8a7795"; +- reg = <0 0xfe980000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 17>; +- power-domains = <&sysc R8A7795_PD_A3VP>; +- #iommu-cells = <1>; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a7795", +- "renesas,etheravb-rcar-gen3"; +- reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15", +- "ch16", "ch17", "ch18", "ch19", +- "ch20", "ch21", "ch22", "ch23", +- "ch24"; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- phy-mode = "rgmii"; +- rx-internal-delay-ps = <0>; +- tx-internal-delay-ps = <0>; +- iommus = <&ipmmu_ds0 16>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- can0: can@e6c30000 { +- compatible = "renesas,can-r8a7795", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c30000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>, +- <&cpg CPG_CORE R8A7795_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- status = "disabled"; +- }; +- +- can1: can@e6c38000 { +- compatible = "renesas,can-r8a7795", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c38000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>, +- <&cpg CPG_CORE R8A7795_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- status = "disabled"; +- }; +- +- canfd: can@e66c0000 { +- compatible = "renesas,r8a7795-canfd", +- "renesas,rcar-gen3-canfd"; +- reg = <0 0xe66c0000 0 0x8000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 914>, +- <&cpg CPG_CORE R8A7795_CLK_CANFD>, +- <&can_clk>; +- clock-names = "fck", "canfd", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 914>; +- status = "disabled"; +- +- channel0 { +- status = "disabled"; +- }; +- +- channel1 { +- status = "disabled"; +- }; +- }; +- +- pwm0: pwm@e6e30000 { +- compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; +- reg = <0 0xe6e30000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm1: pwm@e6e31000 { +- compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; +- reg = <0 0xe6e31000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm2: pwm@e6e32000 { +- compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; +- reg = <0 0xe6e32000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm3: pwm@e6e33000 { +- compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; +- reg = <0 0xe6e33000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm4: pwm@e6e34000 { +- compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; +- reg = <0 0xe6e34000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm5: pwm@e6e35000 { +- compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; +- reg = <0 0xe6e35000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm6: pwm@e6e36000 { +- compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; +- reg = <0 0xe6e36000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a7795", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e60000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>, +- <&cpg CPG_CORE R8A7795_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x51>, <&dmac1 0x50>, +- <&dmac2 0x51>, <&dmac2 0x50>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a7795", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e68000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>, +- <&cpg CPG_CORE R8A7795_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x53>, <&dmac1 0x52>, +- <&dmac2 0x53>, <&dmac2 0x52>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e88000 { +- compatible = "renesas,scif-r8a7795", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e88000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 310>, +- <&cpg CPG_CORE R8A7795_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x13>, <&dmac1 0x12>, +- <&dmac2 0x13>, <&dmac2 0x12>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 310>; +- status = "disabled"; +- }; +- +- scif3: serial@e6c50000 { +- compatible = "renesas,scif-r8a7795", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c50000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>, +- <&cpg CPG_CORE R8A7795_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x57>, <&dmac0 0x56>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scif4: serial@e6c40000 { +- compatible = "renesas,scif-r8a7795", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c40000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>, +- <&cpg CPG_CORE R8A7795_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x59>, <&dmac0 0x58>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- scif5: serial@e6f30000 { +- compatible = "renesas,scif-r8a7795", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6f30000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 202>, +- <&cpg CPG_CORE R8A7795_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, +- <&dmac2 0x5b>, <&dmac2 0x5a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 202>; +- status = "disabled"; +- }; +- +- tpu: pwm@e6e80000 { +- compatible = "renesas,tpu-r8a7795", "renesas,tpu"; +- reg = <0 0xe6e80000 0 0x148>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 304>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 304>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e90000 { +- compatible = "renesas,msiof-r8a7795", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6e90000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 211>; +- dmas = <&dmac1 0x41>, <&dmac1 0x40>, +- <&dmac2 0x41>, <&dmac2 0x40>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 211>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6ea0000 { +- compatible = "renesas,msiof-r8a7795", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6ea0000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 210>; +- dmas = <&dmac1 0x43>, <&dmac1 0x42>, +- <&dmac2 0x43>, <&dmac2 0x42>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 210>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6c00000 { +- compatible = "renesas,msiof-r8a7795", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c00000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 209>; +- dmas = <&dmac0 0x45>, <&dmac0 0x44>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 209>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof3: spi@e6c10000 { +- compatible = "renesas,msiof-r8a7795", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c10000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 208>; +- dmas = <&dmac0 0x47>, <&dmac0 0x46>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 208>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a7795"; +- reg = <0 0xe6ef0000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 811>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 811>; +- renesas,id = <0>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin0csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin0>; +- }; +- vin0csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin0>; +- }; +- }; +- }; +- }; +- +- vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a7795"; +- reg = <0 0xe6ef1000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 810>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 810>; +- renesas,id = <1>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin1csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin1>; +- }; +- vin1csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin1>; +- }; +- }; +- }; +- }; +- +- vin2: video@e6ef2000 { +- compatible = "renesas,vin-r8a7795"; +- reg = <0 0xe6ef2000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 809>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 809>; +- renesas,id = <2>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin2csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin2>; +- }; +- vin2csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin2>; +- }; +- }; +- }; +- }; +- +- vin3: video@e6ef3000 { +- compatible = "renesas,vin-r8a7795"; +- reg = <0 0xe6ef3000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 808>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 808>; +- renesas,id = <3>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin3csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin3>; +- }; +- vin3csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin3>; +- }; +- }; +- }; +- }; +- +- vin4: video@e6ef4000 { +- compatible = "renesas,vin-r8a7795"; +- reg = <0 0xe6ef4000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 807>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 807>; +- renesas,id = <4>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin4csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin4>; +- }; +- vin4csi41: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&csi41vin4>; +- }; +- }; +- }; +- }; +- +- vin5: video@e6ef5000 { +- compatible = "renesas,vin-r8a7795"; +- reg = <0 0xe6ef5000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 806>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 806>; +- renesas,id = <5>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin5csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin5>; +- }; +- vin5csi41: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&csi41vin5>; +- }; +- }; +- }; +- }; +- +- vin6: video@e6ef6000 { +- compatible = "renesas,vin-r8a7795"; +- reg = <0 0xe6ef6000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 805>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 805>; +- renesas,id = <6>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin6csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin6>; +- }; +- vin6csi41: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&csi41vin6>; +- }; +- }; +- }; +- }; +- +- vin7: video@e6ef7000 { +- compatible = "renesas,vin-r8a7795"; +- reg = <0 0xe6ef7000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 804>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 804>; +- renesas,id = <7>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin7csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin7>; +- }; +- vin7csi41: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&csi41vin7>; +- }; +- }; +- }; +- }; +- +- drif00: rif@e6f40000 { +- compatible = "renesas,r8a7795-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f40000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 515>; +- clock-names = "fck"; +- dmas = <&dmac1 0x20>, <&dmac2 0x20>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 515>; +- renesas,bonding = <&drif01>; +- status = "disabled"; +- }; +- +- drif01: rif@e6f50000 { +- compatible = "renesas,r8a7795-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f50000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 514>; +- clock-names = "fck"; +- dmas = <&dmac1 0x22>, <&dmac2 0x22>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 514>; +- renesas,bonding = <&drif00>; +- status = "disabled"; +- }; +- +- drif10: rif@e6f60000 { +- compatible = "renesas,r8a7795-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f60000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 513>; +- clock-names = "fck"; +- dmas = <&dmac1 0x24>, <&dmac2 0x24>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 513>; +- renesas,bonding = <&drif11>; +- status = "disabled"; +- }; +- +- drif11: rif@e6f70000 { +- compatible = "renesas,r8a7795-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f70000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 512>; +- clock-names = "fck"; +- dmas = <&dmac1 0x26>, <&dmac2 0x26>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 512>; +- renesas,bonding = <&drif10>; +- status = "disabled"; +- }; +- +- drif20: rif@e6f80000 { +- compatible = "renesas,r8a7795-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f80000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 511>; +- clock-names = "fck"; +- dmas = <&dmac1 0x28>, <&dmac2 0x28>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 511>; +- renesas,bonding = <&drif21>; +- status = "disabled"; +- }; +- +- drif21: rif@e6f90000 { +- compatible = "renesas,r8a7795-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f90000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 510>; +- clock-names = "fck"; +- dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 510>; +- renesas,bonding = <&drif20>; +- status = "disabled"; +- }; +- +- drif30: rif@e6fa0000 { +- compatible = "renesas,r8a7795-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6fa0000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 509>; +- clock-names = "fck"; +- dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 509>; +- renesas,bonding = <&drif31>; +- status = "disabled"; +- }; +- +- drif31: rif@e6fb0000 { +- compatible = "renesas,r8a7795-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6fb0000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 508>; +- clock-names = "fck"; +- dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 508>; +- renesas,bonding = <&drif30>; +- status = "disabled"; +- }; +- +- rcar_sound: sound@ec500000 { +- /* +- * #sound-dai-cells is required +- * +- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; +- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; +- */ +- /* +- * #clock-cells is required for audio_clkout0/1/2/3 +- * +- * clkout : #clock-cells = <0>; <&rcar_sound>; +- * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; +- */ +- compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; +- reg = <0 0xec500000 0 0x1000>, /* SCU */ +- <0 0xec5a0000 0 0x100>, /* ADG */ +- <0 0xec540000 0 0x1000>, /* SSIU */ +- <0 0xec541000 0 0x280>, /* SSI */ +- <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ +- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; +- +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&audio_clk_b>, +- <&audio_clk_c>, +- <&cpg CPG_CORE R8A7795_CLK_S0D4>; +- clock-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0", +- "src.9", "src.8", "src.7", "src.6", +- "src.5", "src.4", "src.3", "src.2", +- "src.1", "src.0", +- "mix.1", "mix.0", +- "ctu.1", "ctu.0", +- "dvc.0", "dvc.1", +- "clk_a", "clk_b", "clk_c", "clk_i"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 1005>, +- <&cpg 1006>, <&cpg 1007>, +- <&cpg 1008>, <&cpg 1009>, +- <&cpg 1010>, <&cpg 1011>, +- <&cpg 1012>, <&cpg 1013>, +- <&cpg 1014>, <&cpg 1015>; +- reset-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0"; +- status = "disabled"; +- +- rcar_sound,dvc { +- dvc0: dvc-0 { +- dmas = <&audma1 0xbc>; +- dma-names = "tx"; +- }; +- dvc1: dvc-1 { +- dmas = <&audma1 0xbe>; +- dma-names = "tx"; +- }; +- }; +- +- rcar_sound,mix { +- mix0: mix-0 { }; +- mix1: mix-1 { }; +- }; +- +- rcar_sound,ctu { +- ctu00: ctu-0 { }; +- ctu01: ctu-1 { }; +- ctu02: ctu-2 { }; +- ctu03: ctu-3 { }; +- ctu10: ctu-4 { }; +- ctu11: ctu-5 { }; +- ctu12: ctu-6 { }; +- ctu13: ctu-7 { }; +- }; +- +- rcar_sound,src { +- src0: src-0 { +- interrupts = ; +- dmas = <&audma0 0x85>, <&audma1 0x9a>; +- dma-names = "rx", "tx"; +- }; +- src1: src-1 { +- interrupts = ; +- dmas = <&audma0 0x87>, <&audma1 0x9c>; +- dma-names = "rx", "tx"; +- }; +- src2: src-2 { +- interrupts = ; +- dmas = <&audma0 0x89>, <&audma1 0x9e>; +- dma-names = "rx", "tx"; +- }; +- src3: src-3 { +- interrupts = ; +- dmas = <&audma0 0x8b>, <&audma1 0xa0>; +- dma-names = "rx", "tx"; +- }; +- src4: src-4 { +- interrupts = ; +- dmas = <&audma0 0x8d>, <&audma1 0xb0>; +- dma-names = "rx", "tx"; +- }; +- src5: src-5 { +- interrupts = ; +- dmas = <&audma0 0x8f>, <&audma1 0xb2>; +- dma-names = "rx", "tx"; +- }; +- src6: src-6 { +- interrupts = ; +- dmas = <&audma0 0x91>, <&audma1 0xb4>; +- dma-names = "rx", "tx"; +- }; +- src7: src-7 { +- interrupts = ; +- dmas = <&audma0 0x93>, <&audma1 0xb6>; +- dma-names = "rx", "tx"; +- }; +- src8: src-8 { +- interrupts = ; +- dmas = <&audma0 0x95>, <&audma1 0xb8>; +- dma-names = "rx", "tx"; +- }; +- src9: src-9 { +- interrupts = ; +- dmas = <&audma0 0x97>, <&audma1 0xba>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssiu { +- ssiu00: ssiu-0 { +- dmas = <&audma0 0x15>, <&audma1 0x16>; +- dma-names = "rx", "tx"; +- }; +- ssiu01: ssiu-1 { +- dmas = <&audma0 0x35>, <&audma1 0x36>; +- dma-names = "rx", "tx"; +- }; +- ssiu02: ssiu-2 { +- dmas = <&audma0 0x37>, <&audma1 0x38>; +- dma-names = "rx", "tx"; +- }; +- ssiu03: ssiu-3 { +- dmas = <&audma0 0x47>, <&audma1 0x48>; +- dma-names = "rx", "tx"; +- }; +- ssiu04: ssiu-4 { +- dmas = <&audma0 0x3F>, <&audma1 0x40>; +- dma-names = "rx", "tx"; +- }; +- ssiu05: ssiu-5 { +- dmas = <&audma0 0x43>, <&audma1 0x44>; +- dma-names = "rx", "tx"; +- }; +- ssiu06: ssiu-6 { +- dmas = <&audma0 0x4F>, <&audma1 0x50>; +- dma-names = "rx", "tx"; +- }; +- ssiu07: ssiu-7 { +- dmas = <&audma0 0x53>, <&audma1 0x54>; +- dma-names = "rx", "tx"; +- }; +- ssiu10: ssiu-8 { +- dmas = <&audma0 0x49>, <&audma1 0x4a>; +- dma-names = "rx", "tx"; +- }; +- ssiu11: ssiu-9 { +- dmas = <&audma0 0x4B>, <&audma1 0x4C>; +- dma-names = "rx", "tx"; +- }; +- ssiu12: ssiu-10 { +- dmas = <&audma0 0x57>, <&audma1 0x58>; +- dma-names = "rx", "tx"; +- }; +- ssiu13: ssiu-11 { +- dmas = <&audma0 0x59>, <&audma1 0x5A>; +- dma-names = "rx", "tx"; +- }; +- ssiu14: ssiu-12 { +- dmas = <&audma0 0x5F>, <&audma1 0x60>; +- dma-names = "rx", "tx"; +- }; +- ssiu15: ssiu-13 { +- dmas = <&audma0 0xC3>, <&audma1 0xC4>; +- dma-names = "rx", "tx"; +- }; +- ssiu16: ssiu-14 { +- dmas = <&audma0 0xC7>, <&audma1 0xC8>; +- dma-names = "rx", "tx"; +- }; +- ssiu17: ssiu-15 { +- dmas = <&audma0 0xCB>, <&audma1 0xCC>; +- dma-names = "rx", "tx"; +- }; +- ssiu20: ssiu-16 { +- dmas = <&audma0 0x63>, <&audma1 0x64>; +- dma-names = "rx", "tx"; +- }; +- ssiu21: ssiu-17 { +- dmas = <&audma0 0x67>, <&audma1 0x68>; +- dma-names = "rx", "tx"; +- }; +- ssiu22: ssiu-18 { +- dmas = <&audma0 0x6B>, <&audma1 0x6C>; +- dma-names = "rx", "tx"; +- }; +- ssiu23: ssiu-19 { +- dmas = <&audma0 0x6D>, <&audma1 0x6E>; +- dma-names = "rx", "tx"; +- }; +- ssiu24: ssiu-20 { +- dmas = <&audma0 0xCF>, <&audma1 0xCE>; +- dma-names = "rx", "tx"; +- }; +- ssiu25: ssiu-21 { +- dmas = <&audma0 0xEB>, <&audma1 0xEC>; +- dma-names = "rx", "tx"; +- }; +- ssiu26: ssiu-22 { +- dmas = <&audma0 0xED>, <&audma1 0xEE>; +- dma-names = "rx", "tx"; +- }; +- ssiu27: ssiu-23 { +- dmas = <&audma0 0xEF>, <&audma1 0xF0>; +- dma-names = "rx", "tx"; +- }; +- ssiu30: ssiu-24 { +- dmas = <&audma0 0x6f>, <&audma1 0x70>; +- dma-names = "rx", "tx"; +- }; +- ssiu31: ssiu-25 { +- dmas = <&audma0 0x21>, <&audma1 0x22>; +- dma-names = "rx", "tx"; +- }; +- ssiu32: ssiu-26 { +- dmas = <&audma0 0x23>, <&audma1 0x24>; +- dma-names = "rx", "tx"; +- }; +- ssiu33: ssiu-27 { +- dmas = <&audma0 0x25>, <&audma1 0x26>; +- dma-names = "rx", "tx"; +- }; +- ssiu34: ssiu-28 { +- dmas = <&audma0 0x27>, <&audma1 0x28>; +- dma-names = "rx", "tx"; +- }; +- ssiu35: ssiu-29 { +- dmas = <&audma0 0x29>, <&audma1 0x2A>; +- dma-names = "rx", "tx"; +- }; +- ssiu36: ssiu-30 { +- dmas = <&audma0 0x2B>, <&audma1 0x2C>; +- dma-names = "rx", "tx"; +- }; +- ssiu37: ssiu-31 { +- dmas = <&audma0 0x2D>, <&audma1 0x2E>; +- dma-names = "rx", "tx"; +- }; +- ssiu40: ssiu-32 { +- dmas = <&audma0 0x71>, <&audma1 0x72>; +- dma-names = "rx", "tx"; +- }; +- ssiu41: ssiu-33 { +- dmas = <&audma0 0x17>, <&audma1 0x18>; +- dma-names = "rx", "tx"; +- }; +- ssiu42: ssiu-34 { +- dmas = <&audma0 0x19>, <&audma1 0x1A>; +- dma-names = "rx", "tx"; +- }; +- ssiu43: ssiu-35 { +- dmas = <&audma0 0x1B>, <&audma1 0x1C>; +- dma-names = "rx", "tx"; +- }; +- ssiu44: ssiu-36 { +- dmas = <&audma0 0x1D>, <&audma1 0x1E>; +- dma-names = "rx", "tx"; +- }; +- ssiu45: ssiu-37 { +- dmas = <&audma0 0x1F>, <&audma1 0x20>; +- dma-names = "rx", "tx"; +- }; +- ssiu46: ssiu-38 { +- dmas = <&audma0 0x31>, <&audma1 0x32>; +- dma-names = "rx", "tx"; +- }; +- ssiu47: ssiu-39 { +- dmas = <&audma0 0x33>, <&audma1 0x34>; +- dma-names = "rx", "tx"; +- }; +- ssiu50: ssiu-40 { +- dmas = <&audma0 0x73>, <&audma1 0x74>; +- dma-names = "rx", "tx"; +- }; +- ssiu60: ssiu-41 { +- dmas = <&audma0 0x75>, <&audma1 0x76>; +- dma-names = "rx", "tx"; +- }; +- ssiu70: ssiu-42 { +- dmas = <&audma0 0x79>, <&audma1 0x7a>; +- dma-names = "rx", "tx"; +- }; +- ssiu80: ssiu-43 { +- dmas = <&audma0 0x7b>, <&audma1 0x7c>; +- dma-names = "rx", "tx"; +- }; +- ssiu90: ssiu-44 { +- dmas = <&audma0 0x7d>, <&audma1 0x7e>; +- dma-names = "rx", "tx"; +- }; +- ssiu91: ssiu-45 { +- dmas = <&audma0 0x7F>, <&audma1 0x80>; +- dma-names = "rx", "tx"; +- }; +- ssiu92: ssiu-46 { +- dmas = <&audma0 0x81>, <&audma1 0x82>; +- dma-names = "rx", "tx"; +- }; +- ssiu93: ssiu-47 { +- dmas = <&audma0 0x83>, <&audma1 0x84>; +- dma-names = "rx", "tx"; +- }; +- ssiu94: ssiu-48 { +- dmas = <&audma0 0xA3>, <&audma1 0xA4>; +- dma-names = "rx", "tx"; +- }; +- ssiu95: ssiu-49 { +- dmas = <&audma0 0xA5>, <&audma1 0xA6>; +- dma-names = "rx", "tx"; +- }; +- ssiu96: ssiu-50 { +- dmas = <&audma0 0xA7>, <&audma1 0xA8>; +- dma-names = "rx", "tx"; +- }; +- ssiu97: ssiu-51 { +- dmas = <&audma0 0xA9>, <&audma1 0xAA>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssi { +- ssi0: ssi-0 { +- interrupts = ; +- dmas = <&audma0 0x01>, <&audma1 0x02>; +- dma-names = "rx", "tx"; +- }; +- ssi1: ssi-1 { +- interrupts = ; +- dmas = <&audma0 0x03>, <&audma1 0x04>; +- dma-names = "rx", "tx"; +- }; +- ssi2: ssi-2 { +- interrupts = ; +- dmas = <&audma0 0x05>, <&audma1 0x06>; +- dma-names = "rx", "tx"; +- }; +- ssi3: ssi-3 { +- interrupts = ; +- dmas = <&audma0 0x07>, <&audma1 0x08>; +- dma-names = "rx", "tx"; +- }; +- ssi4: ssi-4 { +- interrupts = ; +- dmas = <&audma0 0x09>, <&audma1 0x0a>; +- dma-names = "rx", "tx"; +- }; +- ssi5: ssi-5 { +- interrupts = ; +- dmas = <&audma0 0x0b>, <&audma1 0x0c>; +- dma-names = "rx", "tx"; +- }; +- ssi6: ssi-6 { +- interrupts = ; +- dmas = <&audma0 0x0d>, <&audma1 0x0e>; +- dma-names = "rx", "tx"; +- }; +- ssi7: ssi-7 { +- interrupts = ; +- dmas = <&audma0 0x0f>, <&audma1 0x10>; +- dma-names = "rx", "tx"; +- }; +- ssi8: ssi-8 { +- interrupts = ; +- dmas = <&audma0 0x11>, <&audma1 0x12>; +- dma-names = "rx", "tx"; +- }; +- ssi9: ssi-9 { +- interrupts = ; +- dmas = <&audma0 0x13>, <&audma1 0x14>; +- dma-names = "rx", "tx"; +- }; +- }; +- }; +- +- audma0: dma-controller@ec700000 { +- compatible = "renesas,dmac-r8a7795", +- "renesas,rcar-dmac"; +- reg = <0 0xec700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 502>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 502>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, +- <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, +- <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, +- <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, +- <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, +- <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, +- <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, +- <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; +- }; +- +- audma1: dma-controller@ec720000 { +- compatible = "renesas,dmac-r8a7795", +- "renesas,rcar-dmac"; +- reg = <0 0xec720000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 501>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 501>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, +- <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, +- <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, +- <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, +- <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, +- <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, +- <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, +- <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; +- }; +- +- xhci0: usb@ee000000 { +- compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; +- reg = <0 0xee000000 0 0xc00>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- status = "disabled"; +- }; +- +- usb3_peri0: usb@ee020000 { +- compatible = "renesas,r8a7795-usb3-peri", +- "renesas,rcar-gen3-usb3-peri"; +- reg = <0 0xee020000 0 0x400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- status = "disabled"; +- }; +- +- ohci0: usb@ee080000 { +- compatible = "generic-ohci"; +- reg = <0 0xee080000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- ohci1: usb@ee0a0000 { +- compatible = "generic-ohci"; +- reg = <0 0xee0a0000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 702>; +- phys = <&usb2_phy1 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- status = "disabled"; +- }; +- +- ohci2: usb@ee0c0000 { +- compatible = "generic-ohci"; +- reg = <0 0xee0c0000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 701>; +- phys = <&usb2_phy2 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 701>; +- status = "disabled"; +- }; +- +- ohci3: usb@ee0e0000 { +- compatible = "generic-ohci"; +- reg = <0 0xee0e0000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; +- phys = <&usb2_phy3 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 700>, <&cpg 705>; +- status = "disabled"; +- }; +- +- ehci0: usb@ee080100 { +- compatible = "generic-ehci"; +- reg = <0 0xee080100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 2>; +- phy-names = "usb"; +- companion = <&ohci0>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- ehci1: usb@ee0a0100 { +- compatible = "generic-ehci"; +- reg = <0 0xee0a0100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 702>; +- phys = <&usb2_phy1 2>; +- phy-names = "usb"; +- companion = <&ohci1>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- status = "disabled"; +- }; +- +- ehci2: usb@ee0c0100 { +- compatible = "generic-ehci"; +- reg = <0 0xee0c0100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 701>; +- phys = <&usb2_phy2 2>; +- phy-names = "usb"; +- companion = <&ohci2>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 701>; +- status = "disabled"; +- }; +- +- ehci3: usb@ee0e0100 { +- compatible = "generic-ehci"; +- reg = <0 0xee0e0100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; +- phys = <&usb2_phy3 2>; +- phy-names = "usb"; +- companion = <&ohci3>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 700>, <&cpg 705>; +- status = "disabled"; +- }; +- +- usb2_phy0: usb-phy@ee080200 { +- compatible = "renesas,usb2-phy-r8a7795", +- "renesas,rcar-gen3-usb2-phy"; +- reg = <0 0xee080200 0 0x700>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- usb2_phy1: usb-phy@ee0a0200 { +- compatible = "renesas,usb2-phy-r8a7795", +- "renesas,rcar-gen3-usb2-phy"; +- reg = <0 0xee0a0200 0 0x700>; +- clocks = <&cpg CPG_MOD 702>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- usb2_phy2: usb-phy@ee0c0200 { +- compatible = "renesas,usb2-phy-r8a7795", +- "renesas,rcar-gen3-usb2-phy"; +- reg = <0 0xee0c0200 0 0x700>; +- clocks = <&cpg CPG_MOD 701>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 701>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- usb2_phy3: usb-phy@ee0e0200 { +- compatible = "renesas,usb2-phy-r8a7795", +- "renesas,rcar-gen3-usb2-phy"; +- reg = <0 0xee0e0200 0 0x700>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 700>, <&cpg 705>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a7795", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee100000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- iommus = <&ipmmu_ds1 32>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ee120000 { +- compatible = "renesas,sdhi-r8a7795", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee120000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 313>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 313>; +- iommus = <&ipmmu_ds1 33>; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a7795", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee140000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 312>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 312>; +- iommus = <&ipmmu_ds1 34>; +- status = "disabled"; +- }; +- +- sdhi3: mmc@ee160000 { +- compatible = "renesas,sdhi-r8a7795", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee160000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 311>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 311>; +- iommus = <&ipmmu_ds1 35>; +- status = "disabled"; +- }; +- +- sata: sata@ee300000 { +- compatible = "renesas,sata-r8a7795", +- "renesas,rcar-gen3-sata"; +- reg = <0 0xee300000 0 0x200000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 815>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 815>; +- status = "disabled"; +- iommus = <&ipmmu_hc 2>; +- }; +- +- gic: interrupt-controller@f1010000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x0 0xf1010000 0 0x1000>, +- <0x0 0xf1020000 0 0x20000>, +- <0x0 0xf1040000 0 0x20000>, +- <0x0 0xf1060000 0 0x20000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- pciec0: pcie@fe000000 { +- compatible = "renesas,pcie-r8a7795", +- "renesas,pcie-rcar-gen3"; +- reg = <0 0xfe000000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, +- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, +- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, +- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 319>; +- status = "disabled"; +- }; +- +- pciec1: pcie@ee800000 { +- compatible = "renesas,pcie-r8a7795", +- "renesas,pcie-rcar-gen3"; +- reg = <0 0xee800000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, +- <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, +- <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, +- <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 318>; +- status = "disabled"; +- }; +- +- pciec0_ep: pcie-ep@fe000000 { +- compatible = "renesas,r8a7795-pcie-ep", +- "renesas,rcar-gen3-pcie-ep"; +- reg = <0x0 0xfe000000 0 0x80000>, +- <0x0 0xfe100000 0 0x100000>, +- <0x0 0xfe200000 0 0x200000>, +- <0x0 0x30000000 0 0x8000000>, +- <0x0 0x38000000 0 0x8000000>; +- reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 319>; +- clock-names = "pcie"; +- resets = <&cpg 319>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pciec1_ep: pcie-ep@ee800000 { +- compatible = "renesas,r8a7795-pcie-ep", +- "renesas,rcar-gen3-pcie-ep"; +- reg = <0x0 0xee800000 0 0x80000>, +- <0x0 0xee900000 0 0x100000>, +- <0x0 0xeea00000 0 0x200000>, +- <0x0 0xc0000000 0 0x8000000>, +- <0x0 0xc8000000 0 0x8000000>; +- reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 318>; +- clock-names = "pcie"; +- resets = <&cpg 318>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- imr-lx4@fe860000 { +- compatible = "renesas,r8a7795-imr-lx4", +- "renesas,imr-lx4"; +- reg = <0 0xfe860000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 823>; +- power-domains = <&sysc R8A7795_PD_A3VC>; +- resets = <&cpg 823>; +- }; +- +- imr-lx4@fe870000 { +- compatible = "renesas,r8a7795-imr-lx4", +- "renesas,imr-lx4"; +- reg = <0 0xfe870000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 822>; +- power-domains = <&sysc R8A7795_PD_A3VC>; +- resets = <&cpg 822>; +- }; +- +- imr-lx4@fe880000 { +- compatible = "renesas,r8a7795-imr-lx4", +- "renesas,imr-lx4"; +- reg = <0 0xfe880000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 821>; +- power-domains = <&sysc R8A7795_PD_A3VC>; +- resets = <&cpg 821>; +- }; +- +- imr-lx4@fe890000 { +- compatible = "renesas,r8a7795-imr-lx4", +- "renesas,imr-lx4"; +- reg = <0 0xfe890000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 820>; +- power-domains = <&sysc R8A7795_PD_A3VC>; +- resets = <&cpg 820>; +- }; +- +- vspbc: vsp@fe920000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe920000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 624>; +- power-domains = <&sysc R8A7795_PD_A3VP>; +- resets = <&cpg 624>; +- +- renesas,fcp = <&fcpvb1>; +- }; +- +- vspbd: vsp@fe960000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe960000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 626>; +- power-domains = <&sysc R8A7795_PD_A3VP>; +- resets = <&cpg 626>; +- +- renesas,fcp = <&fcpvb0>; +- }; +- +- vspd0: vsp@fea20000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea20000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 623>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 623>; +- +- renesas,fcp = <&fcpvd0>; +- }; +- +- vspd1: vsp@fea28000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea28000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 622>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 622>; +- +- renesas,fcp = <&fcpvd1>; +- }; +- +- vspd2: vsp@fea30000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea30000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 621>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 621>; +- +- renesas,fcp = <&fcpvd2>; +- }; +- +- vspi0: vsp@fe9a0000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe9a0000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 631>; +- power-domains = <&sysc R8A7795_PD_A3VP>; +- resets = <&cpg 631>; +- +- renesas,fcp = <&fcpvi0>; +- }; +- +- vspi1: vsp@fe9b0000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe9b0000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 630>; +- power-domains = <&sysc R8A7795_PD_A3VP>; +- resets = <&cpg 630>; +- +- renesas,fcp = <&fcpvi1>; +- }; +- +- fdp1@fe940000 { +- compatible = "renesas,fdp1"; +- reg = <0 0xfe940000 0 0x2400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 119>; +- power-domains = <&sysc R8A7795_PD_A3VP>; +- resets = <&cpg 119>; +- renesas,fcp = <&fcpf0>; +- }; +- +- fdp1@fe944000 { +- compatible = "renesas,fdp1"; +- reg = <0 0xfe944000 0 0x2400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 118>; +- power-domains = <&sysc R8A7795_PD_A3VP>; +- resets = <&cpg 118>; +- renesas,fcp = <&fcpf1>; +- }; +- +- fcpf0: fcp@fe950000 { +- compatible = "renesas,fcpf"; +- reg = <0 0xfe950000 0 0x200>; +- clocks = <&cpg CPG_MOD 615>; +- power-domains = <&sysc R8A7795_PD_A3VP>; +- resets = <&cpg 615>; +- iommus = <&ipmmu_vp0 0>; +- }; +- +- fcpf1: fcp@fe951000 { +- compatible = "renesas,fcpf"; +- reg = <0 0xfe951000 0 0x200>; +- clocks = <&cpg CPG_MOD 614>; +- power-domains = <&sysc R8A7795_PD_A3VP>; +- resets = <&cpg 614>; +- iommus = <&ipmmu_vp1 1>; +- }; +- +- fcpvb0: fcp@fe96f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe96f000 0 0x200>; +- clocks = <&cpg CPG_MOD 607>; +- power-domains = <&sysc R8A7795_PD_A3VP>; +- resets = <&cpg 607>; +- iommus = <&ipmmu_vp0 5>; +- }; +- +- fcpvb1: fcp@fe92f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe92f000 0 0x200>; +- clocks = <&cpg CPG_MOD 606>; +- power-domains = <&sysc R8A7795_PD_A3VP>; +- resets = <&cpg 606>; +- iommus = <&ipmmu_vp1 7>; +- }; +- +- fcpvi0: fcp@fe9af000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe9af000 0 0x200>; +- clocks = <&cpg CPG_MOD 611>; +- power-domains = <&sysc R8A7795_PD_A3VP>; +- resets = <&cpg 611>; +- iommus = <&ipmmu_vp0 8>; +- }; +- +- fcpvi1: fcp@fe9bf000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe9bf000 0 0x200>; +- clocks = <&cpg CPG_MOD 610>; +- power-domains = <&sysc R8A7795_PD_A3VP>; +- resets = <&cpg 610>; +- iommus = <&ipmmu_vp1 9>; +- }; +- +- fcpvd0: fcp@fea27000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea27000 0 0x200>; +- clocks = <&cpg CPG_MOD 603>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 603>; +- iommus = <&ipmmu_vi0 8>; +- }; +- +- fcpvd1: fcp@fea2f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea2f000 0 0x200>; +- clocks = <&cpg CPG_MOD 602>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 602>; +- iommus = <&ipmmu_vi0 9>; +- }; +- +- fcpvd2: fcp@fea37000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea37000 0 0x200>; +- clocks = <&cpg CPG_MOD 601>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 601>; +- iommus = <&ipmmu_vi1 10>; +- }; +- +- cmm0: cmm@fea40000 { +- compatible = "renesas,r8a7795-cmm", +- "renesas,rcar-gen3-cmm"; +- reg = <0 0xfea40000 0 0x1000>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- clocks = <&cpg CPG_MOD 711>; +- resets = <&cpg 711>; +- }; +- +- cmm1: cmm@fea50000 { +- compatible = "renesas,r8a7795-cmm", +- "renesas,rcar-gen3-cmm"; +- reg = <0 0xfea50000 0 0x1000>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- clocks = <&cpg CPG_MOD 710>; +- resets = <&cpg 710>; +- }; +- +- cmm2: cmm@fea60000 { +- compatible = "renesas,r8a7795-cmm", +- "renesas,rcar-gen3-cmm"; +- reg = <0 0xfea60000 0 0x1000>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- clocks = <&cpg CPG_MOD 709>; +- resets = <&cpg 709>; +- }; +- +- cmm3: cmm@fea70000 { +- compatible = "renesas,r8a7795-cmm", +- "renesas,rcar-gen3-cmm"; +- reg = <0 0xfea70000 0 0x1000>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- clocks = <&cpg CPG_MOD 708>; +- resets = <&cpg 708>; +- }; +- +- csi20: csi2@fea80000 { +- compatible = "renesas,r8a7795-csi2"; +- reg = <0 0xfea80000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 714>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 714>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi20vin0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin0csi20>; +- }; +- csi20vin1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin1csi20>; +- }; +- csi20vin2: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&vin2csi20>; +- }; +- csi20vin3: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&vin3csi20>; +- }; +- csi20vin4: endpoint@4 { +- reg = <4>; +- remote-endpoint = <&vin4csi20>; +- }; +- csi20vin5: endpoint@5 { +- reg = <5>; +- remote-endpoint = <&vin5csi20>; +- }; +- csi20vin6: endpoint@6 { +- reg = <6>; +- remote-endpoint = <&vin6csi20>; +- }; +- csi20vin7: endpoint@7 { +- reg = <7>; +- remote-endpoint = <&vin7csi20>; +- }; +- }; +- }; +- }; +- +- csi40: csi2@feaa0000 { +- compatible = "renesas,r8a7795-csi2"; +- reg = <0 0xfeaa0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi40vin0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin0csi40>; +- }; +- csi40vin1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin1csi40>; +- }; +- csi40vin2: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&vin2csi40>; +- }; +- csi40vin3: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&vin3csi40>; +- }; +- }; +- }; +- }; +- +- csi41: csi2@feab0000 { +- compatible = "renesas,r8a7795-csi2"; +- reg = <0 0xfeab0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 715>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 715>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi41vin4: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin4csi41>; +- }; +- csi41vin5: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin5csi41>; +- }; +- csi41vin6: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&vin6csi41>; +- }; +- csi41vin7: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&vin7csi41>; +- }; +- }; +- }; +- }; +- +- hdmi0: hdmi@fead0000 { +- compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; +- reg = <0 0xfead0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; +- clock-names = "iahb", "isfr"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 729>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- dw_hdmi0_in: endpoint { +- remote-endpoint = <&du_out_hdmi0>; +- }; +- }; +- port@1 { +- reg = <1>; +- }; +- port@2 { +- /* HDMI sound */ +- reg = <2>; +- }; +- }; +- }; +- +- hdmi1: hdmi@feae0000 { +- compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; +- reg = <0 0xfeae0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 728>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; +- clock-names = "iahb", "isfr"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 728>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- dw_hdmi1_in: endpoint { +- remote-endpoint = <&du_out_hdmi1>; +- }; +- }; +- port@1 { +- reg = <1>; +- }; +- port@2 { +- /* HDMI sound */ +- reg = <2>; +- }; +- }; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a7795"; +- reg = <0 0xfeb00000 0 0x80000>; +- interrupts = , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>; +- clock-names = "du.0", "du.1", "du.2", "du.3"; +- resets = <&cpg 724>, <&cpg 722>; +- reset-names = "du.0", "du.2"; +- +- renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; +- renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, +- <&vspd0 1>; +- +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb: endpoint { +- }; +- }; +- port@1 { +- reg = <1>; +- du_out_hdmi0: endpoint { +- remote-endpoint = <&dw_hdmi0_in>; +- }; +- }; +- port@2 { +- reg = <2>; +- du_out_hdmi1: endpoint { +- remote-endpoint = <&dw_hdmi1_in>; +- }; +- }; +- port@3 { +- reg = <3>; +- du_out_lvds0: endpoint { +- remote-endpoint = <&lvds0_in>; +- }; +- }; +- }; +- }; +- +- lvds0: lvds@feb90000 { +- compatible = "renesas,r8a7795-lvds"; +- reg = <0 0xfeb90000 0 0x14>; +- clocks = <&cpg CPG_MOD 727>; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- resets = <&cpg 727>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds0_in: endpoint { +- remote-endpoint = <&du_out_lvds0>; +- }; +- }; +- port@1 { +- reg = <1>; +- lvds0_out: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@fff00044 { +- compatible = "renesas,prr"; +- reg = <0 0xfff00044 0 4>; +- }; +- }; +- +- thermal-zones { +- sensor1_thermal: sensor1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 0>; +- sustainable-power = <6313>; +- +- trips { +- sensor1_crit: sensor1-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- sensor2_thermal: sensor2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 1>; +- sustainable-power = <6313>; +- +- trips { +- sensor2_crit: sensor2-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- sensor3_thermal: sensor3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 2>; +- +- trips { +- target: trip-point1 { +- temperature = <100000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- +- sensor3_crit: sensor3-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&target>; +- cooling-device = <&a57_0 2 4>; +- contribution = <1024>; +- }; +- +- map1 { +- trip = <&target>; +- cooling-device = <&a53_0 0 2>; +- contribution = <1024>; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; +- }; +- +- /* External USB clocks - can be overridden by the board */ +- usb3s0_clk: usb3s0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- usb_extal_clk: usb_extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77960-salvator-x.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77960-salvator-x.dts +deleted file mode 100644 +index d5543f26c472..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77960-salvator-x.dts ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Salvator-X board with R-Car M3-W +- * +- * Copyright (C) 2016 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a77960.dtsi" +-#include "salvator-x.dtsi" +- +-/ { +- model = "Renesas Salvator-X board based on r8a77960"; +- compatible = "renesas,salvator-x", "renesas,r8a7796"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x78000000>; +- }; +- +- memory@600000000 { +- device_type = "memory"; +- reg = <0x6 0x00000000 0x0 0x80000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>, +- <&versaclock5 1>, +- <&x21_clk>, +- <&versaclock5 2>; +- clock-names = "du.0", "du.1", "du.2", +- "dclkin.0", "dclkin.1", "dclkin.2"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77960-salvator-xs.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77960-salvator-xs.dts +deleted file mode 100644 +index 9ebb47b6bf2d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77960-salvator-xs.dts ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-W +- * +- * Copyright (C) 2015-2017 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a77960.dtsi" +-#include "salvator-xs.dtsi" +- +-/ { +- model = "Renesas Salvator-X 2nd version board based on r8a77960"; +- compatible = "renesas,salvator-xs", "renesas,r8a7796"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x78000000>; +- }; +- +- memory@600000000 { +- device_type = "memory"; +- reg = <0x6 0x00000000 0x0 0x80000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>, +- <&versaclock6 1>, +- <&x21_clk>, +- <&versaclock6 2>; +- clock-names = "du.0", "du.1", "du.2", +- "dclkin.0", "dclkin.1", "dclkin.2"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77960-ulcb-kf.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77960-ulcb-kf.dts +deleted file mode 100644 +index 02d61360692c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77960-ulcb-kf.dts ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the M3ULCB Kingfisher board with R-Car M3-W +- * +- * Copyright (C) 2017 Renesas Electronics Corp. +- * Copyright (C) 2017 Cogent Embedded, Inc. +- */ +- +-#include "r8a77960-ulcb.dts" +-#include "ulcb-kf.dtsi" +- +-/ { +- model = "Renesas M3ULCB Kingfisher board based on r8a77960"; +- compatible = "shimafuji,kingfisher", "renesas,m3ulcb", +- "renesas,r8a7796"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77960-ulcb.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77960-ulcb.dts +deleted file mode 100644 +index 4bfeb1df0488..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77960-ulcb.dts ++++ /dev/null +@@ -1,38 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board with R-Car M3-W +- * +- * Copyright (C) 2016 Renesas Electronics Corp. +- * Copyright (C) 2016 Cogent Embedded, Inc. +- */ +- +-/dts-v1/; +-#include "r8a77960.dtsi" +-#include "ulcb.dtsi" +- +-/ { +- model = "Renesas M3ULCB board based on r8a77960"; +- compatible = "renesas,m3ulcb", "renesas,r8a7796"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x38000000>; +- }; +- +- memory@600000000 { +- device_type = "memory"; +- reg = <0x6 0x00000000 0x0 0x40000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>, +- <&versaclock5 1>, +- <&versaclock5 3>, +- <&versaclock5 2>; +- clock-names = "du.0", "du.1", "du.2", +- "dclkin.0", "dclkin.1", "dclkin.2"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77960.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r8a77960.dtsi +deleted file mode 100644 +index b526e4f0ee6a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77960.dtsi ++++ /dev/null +@@ -1,3059 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Car M3-W (R8A77960) SoC +- * +- * Copyright (C) 2016-2017 Renesas Electronics Corp. +- */ +- +-#include +-#include +-#include +- +-#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4 +- +-/ { +- compatible = "renesas,r8a7796"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c_dvfs; +- }; +- +- /* +- * The external audio clocks are configured as 0 Hz fixed frequency +- * clocks by default. +- * Boards that provide audio clocks should override them. +- */ +- audio_clk_a: audio_clk_a { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_b: audio_clk_b { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_c: audio_clk_c { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* External CAN clock - to be overridden by boards that provide it */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- cluster0_opp: opp_table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <830000>; +- clock-latency-ns = <300000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <830000>; +- clock-latency-ns = <300000>; +- }; +- opp-1500000000 { +- opp-hz = /bits/ 64 <1500000000>; +- opp-microvolt = <830000>; +- clock-latency-ns = <300000>; +- opp-suspend; +- }; +- opp-1600000000 { +- opp-hz = /bits/ 64 <1600000000>; +- opp-microvolt = <900000>; +- clock-latency-ns = <300000>; +- turbo-mode; +- }; +- opp-1700000000 { +- opp-hz = /bits/ 64 <1700000000>; +- opp-microvolt = <900000>; +- clock-latency-ns = <300000>; +- turbo-mode; +- }; +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <960000>; +- clock-latency-ns = <300000>; +- turbo-mode; +- }; +- }; +- +- cluster1_opp: opp_table1 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1300000000 { +- opp-hz = /bits/ 64 <1300000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- turbo-mode; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&a57_0>; +- }; +- core1 { +- cpu = <&a57_1>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&a53_0>; +- }; +- core1 { +- cpu = <&a53_1>; +- }; +- core2 { +- cpu = <&a53_2>; +- }; +- core3 { +- cpu = <&a53_3>; +- }; +- }; +- }; +- +- a57_0: cpu@0 { +- compatible = "arm,cortex-a57"; +- reg = <0x0>; +- device_type = "cpu"; +- power-domains = <&sysc R8A7796_PD_CA57_CPU0>; +- next-level-cache = <&L2_CA57>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- dynamic-power-coefficient = <854>; +- clocks = <&cpg CPG_CORE R8A7796_CLK_Z>; +- operating-points-v2 = <&cluster0_opp>; +- capacity-dmips-mhz = <1024>; +- #cooling-cells = <2>; +- }; +- +- a57_1: cpu@1 { +- compatible = "arm,cortex-a57"; +- reg = <0x1>; +- device_type = "cpu"; +- power-domains = <&sysc R8A7796_PD_CA57_CPU1>; +- next-level-cache = <&L2_CA57>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- clocks = <&cpg CPG_CORE R8A7796_CLK_Z>; +- operating-points-v2 = <&cluster0_opp>; +- capacity-dmips-mhz = <1024>; +- #cooling-cells = <2>; +- }; +- +- a53_0: cpu@100 { +- compatible = "arm,cortex-a53"; +- reg = <0x100>; +- device_type = "cpu"; +- power-domains = <&sysc R8A7796_PD_CA53_CPU0>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_1>; +- #cooling-cells = <2>; +- dynamic-power-coefficient = <277>; +- clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <535>; +- }; +- +- a53_1: cpu@101 { +- compatible = "arm,cortex-a53"; +- reg = <0x101>; +- device_type = "cpu"; +- power-domains = <&sysc R8A7796_PD_CA53_CPU1>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_1>; +- clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <535>; +- }; +- +- a53_2: cpu@102 { +- compatible = "arm,cortex-a53"; +- reg = <0x102>; +- device_type = "cpu"; +- power-domains = <&sysc R8A7796_PD_CA53_CPU2>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_1>; +- clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <535>; +- }; +- +- a53_3: cpu@103 { +- compatible = "arm,cortex-a53"; +- reg = <0x103>; +- device_type = "cpu"; +- power-domains = <&sysc R8A7796_PD_CA53_CPU3>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_1>; +- clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <535>; +- }; +- +- L2_CA57: cache-controller-0 { +- compatible = "cache"; +- power-domains = <&sysc R8A7796_PD_CA57_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- +- L2_CA53: cache-controller-1 { +- compatible = "cache"; +- power-domains = <&sysc R8A7796_PD_CA53_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP_0: cpu-sleep-0 { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x0010000>; +- local-timer-stop; +- entry-latency-us = <400>; +- exit-latency-us = <500>; +- min-residency-us = <4000>; +- }; +- +- CPU_SLEEP_1: cpu-sleep-1 { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x0010000>; +- local-timer-stop; +- entry-latency-us = <700>; +- exit-latency-us = <700>; +- min-residency-us = <5000>; +- }; +- }; +- }; +- +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- extalr_clk: extalr { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- /* External PCIe clock - can be overridden by the board */ +- pcie_bus_clk: pcie_bus { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- pmu_a53 { +- compatible = "arm,cortex-a53-pmu"; +- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; +- }; +- +- pmu_a57 { +- compatible = "arm,cortex-a57-pmu"; +- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&a57_0>, <&a57_1>; +- }; +- +- psci { +- compatible = "arm,psci-1.0", "arm,psci-0.2"; +- method = "smc"; +- }; +- +- /* External SCIF clock - to be overridden by boards that provide it */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a7796-wdt", +- "renesas,rcar-gen3-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a7796", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 16>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a7796", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 29>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a7796", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 15>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a7796", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 16>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a7796", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 18>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a7796", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- gpio6: gpio@e6055400 { +- compatible = "renesas,gpio-r8a7796", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055400 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 192 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 906>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 906>; +- }; +- +- gpio7: gpio@e6055800 { +- compatible = "renesas,gpio-r8a7796", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055800 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 224 4>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 905>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 905>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a7796"; +- reg = <0 0xe6060000 0 0x50c>; +- }; +- +- cmt0: timer@e60f0000 { +- compatible = "renesas,r8a7796-cmt0", +- "renesas,rcar-gen3-cmt0"; +- reg = <0 0xe60f0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 303>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 303>; +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a7796-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 302>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 302>; +- status = "disabled"; +- }; +- +- cmt2: timer@e6140000 { +- compatible = "renesas,r8a7796-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6140000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 301>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 301>; +- status = "disabled"; +- }; +- +- cmt3: timer@e6148000 { +- compatible = "renesas,r8a7796-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6148000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 300>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 300>; +- status = "disabled"; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a7796-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>, <&extalr_clk>; +- clock-names = "extal", "extalr"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a7796-rst"; +- reg = <0 0xe6160000 0 0x0200>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a7796-sysc"; +- reg = <0 0xe6180000 0 0x0400>; +- #power-domain-cells = <1>; +- }; +- +- tsc: thermal@e6198000 { +- compatible = "renesas,r8a7796-thermal"; +- reg = <0 0xe6198000 0 0x100>, +- <0 0xe61a0000 0 0x100>, +- <0 0xe61a8000 0 0x100>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 522>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 522>; +- #thermal-sensor-cells = <1>; +- }; +- +- intc_ex: interrupt-controller@e61c0000 { +- compatible = "renesas,intc-ex-r8a7796", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- tmu0: timer@e61e0000 { +- compatible = "renesas,tmu-r8a7796", "renesas,tmu"; +- reg = <0 0xe61e0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 125>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 125>; +- status = "disabled"; +- }; +- +- tmu1: timer@e6fc0000 { +- compatible = "renesas,tmu-r8a7796", "renesas,tmu"; +- reg = <0 0xe6fc0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- status = "disabled"; +- }; +- +- tmu2: timer@e6fd0000 { +- compatible = "renesas,tmu-r8a7796", "renesas,tmu"; +- reg = <0 0xe6fd0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 123>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 123>; +- status = "disabled"; +- }; +- +- tmu3: timer@e6fe0000 { +- compatible = "renesas,tmu-r8a7796", "renesas,tmu"; +- reg = <0 0xe6fe0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 122>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 122>; +- status = "disabled"; +- }; +- +- tmu4: timer@ffc00000 { +- compatible = "renesas,tmu-r8a7796", "renesas,tmu"; +- reg = <0 0xffc00000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 121>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 121>; +- status = "disabled"; +- }; +- +- i2c0: i2c@e6500000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7796", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6500000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- dmas = <&dmac1 0x91>, <&dmac1 0x90>, +- <&dmac2 0x91>, <&dmac2 0x90>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6508000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7796", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- dmas = <&dmac1 0x93>, <&dmac1 0x92>, +- <&dmac2 0x93>, <&dmac2 0x92>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6510000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7796", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6510000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- dmas = <&dmac1 0x95>, <&dmac1 0x94>, +- <&dmac2 0x95>, <&dmac2 0x94>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e66d0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7796", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- dmas = <&dmac0 0x97>, <&dmac0 0x96>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e66d8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7796", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 927>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 927>; +- dmas = <&dmac0 0x99>, <&dmac0 0x98>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c5: i2c@e66e0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7796", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 919>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 919>; +- dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c6: i2c@e66e8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a7796", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 918>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 918>; +- dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c_dvfs: i2c@e60b0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a7796", +- "renesas,rcar-gen3-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe60b0000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 926>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 926>; +- dmas = <&dmac0 0x11>, <&dmac0 0x10>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- hscif0: serial@e6540000 { +- compatible = "renesas,hscif-r8a7796", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6540000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 520>, +- <&cpg CPG_CORE R8A7796_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x31>, <&dmac1 0x30>, +- <&dmac2 0x31>, <&dmac2 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 520>; +- status = "disabled"; +- }; +- +- hscif1: serial@e6550000 { +- compatible = "renesas,hscif-r8a7796", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6550000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 519>, +- <&cpg CPG_CORE R8A7796_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x33>, <&dmac1 0x32>, +- <&dmac2 0x33>, <&dmac2 0x32>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 519>; +- status = "disabled"; +- }; +- +- hscif2: serial@e6560000 { +- compatible = "renesas,hscif-r8a7796", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6560000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 518>, +- <&cpg CPG_CORE R8A7796_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x35>, <&dmac1 0x34>, +- <&dmac2 0x35>, <&dmac2 0x34>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 518>; +- status = "disabled"; +- }; +- +- hscif3: serial@e66a0000 { +- compatible = "renesas,hscif-r8a7796", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66a0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 517>, +- <&cpg CPG_CORE R8A7796_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x37>, <&dmac0 0x36>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 517>; +- status = "disabled"; +- }; +- +- hscif4: serial@e66b0000 { +- compatible = "renesas,hscif-r8a7796", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66b0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 516>, +- <&cpg CPG_CORE R8A7796_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x39>, <&dmac0 0x38>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 516>; +- status = "disabled"; +- }; +- +- hsusb: usb@e6590000 { +- compatible = "renesas,usbhs-r8a7796", +- "renesas,rcar-gen3-usbhs"; +- reg = <0 0xe6590000 0 0x200>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; +- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, +- <&usb_dmac1 0>, <&usb_dmac1 1>; +- dma-names = "ch0", "ch1", "ch2", "ch3"; +- renesas,buswait = <11>; +- phys = <&usb2_phy0 3>; +- phy-names = "usb"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 704>, <&cpg 703>; +- status = "disabled"; +- }; +- +- usb_dmac0: dma-controller@e65a0000 { +- compatible = "renesas,r8a7796-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65a0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 330>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 330>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac1: dma-controller@e65b0000 { +- compatible = "renesas,r8a7796-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65b0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 331>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 331>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb3_phy0: usb-phy@e65ee000 { +- compatible = "renesas,r8a7796-usb3-phy", +- "renesas,rcar-gen3-usb3-phy"; +- reg = <0 0xe65ee000 0 0x90>; +- clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, +- <&usb_extal_clk>; +- clock-names = "usb3-if", "usb3s_clk", "usb_extal"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- arm_cc630p: crypto@e6601000 { +- compatible = "arm,cryptocell-630p-ree"; +- interrupts = ; +- reg = <0x0 0xe6601000 0 0x1000>; +- clocks = <&cpg CPG_MOD 229>; +- resets = <&cpg 229>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a7796", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, +- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, +- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, +- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, +- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, +- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, +- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, +- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; +- }; +- +- dmac1: dma-controller@e7300000 { +- compatible = "renesas,dmac-r8a7796", +- "renesas,rcar-dmac"; +- reg = <0 0xe7300000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, +- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, +- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, +- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, +- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, +- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, +- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, +- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; +- }; +- +- dmac2: dma-controller@e7310000 { +- compatible = "renesas,dmac-r8a7796", +- "renesas,rcar-dmac"; +- reg = <0 0xe7310000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 217>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 217>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, +- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, +- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, +- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, +- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, +- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, +- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, +- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; +- }; +- +- ipmmu_ds0: iommu@e6740000 { +- compatible = "renesas,ipmmu-r8a7796"; +- reg = <0 0xe6740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 0>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_ds1: iommu@e7740000 { +- compatible = "renesas,ipmmu-r8a7796"; +- reg = <0 0xe7740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 1>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_hc: iommu@e6570000 { +- compatible = "renesas,ipmmu-r8a7796"; +- reg = <0 0xe6570000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 2>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_ir: iommu@ff8b0000 { +- compatible = "renesas,ipmmu-r8a7796"; +- reg = <0 0xff8b0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 3>; +- power-domains = <&sysc R8A7796_PD_A3IR>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mm: iommu@e67b0000 { +- compatible = "renesas,ipmmu-r8a7796"; +- reg = <0 0xe67b0000 0 0x1000>; +- interrupts = , +- ; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mp: iommu@ec670000 { +- compatible = "renesas,ipmmu-r8a7796"; +- reg = <0 0xec670000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 4>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_pv0: iommu@fd800000 { +- compatible = "renesas,ipmmu-r8a7796"; +- reg = <0 0xfd800000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 5>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_pv1: iommu@fd950000 { +- compatible = "renesas,ipmmu-r8a7796"; +- reg = <0 0xfd950000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 6>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_rt: iommu@ffc80000 { +- compatible = "renesas,ipmmu-r8a7796"; +- reg = <0 0xffc80000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 7>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vc0: iommu@fe6b0000 { +- compatible = "renesas,ipmmu-r8a7796"; +- reg = <0 0xfe6b0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 8>; +- power-domains = <&sysc R8A7796_PD_A3VC>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vi0: iommu@febd0000 { +- compatible = "renesas,ipmmu-r8a7796"; +- reg = <0 0xfebd0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 9>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a7796", +- "renesas,etheravb-rcar-gen3"; +- reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15", +- "ch16", "ch17", "ch18", "ch19", +- "ch20", "ch21", "ch22", "ch23", +- "ch24"; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- phy-mode = "rgmii"; +- rx-internal-delay-ps = <0>; +- tx-internal-delay-ps = <0>; +- iommus = <&ipmmu_ds0 16>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- can0: can@e6c30000 { +- compatible = "renesas,can-r8a7796", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c30000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>, +- <&cpg CPG_CORE R8A7796_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- status = "disabled"; +- }; +- +- can1: can@e6c38000 { +- compatible = "renesas,can-r8a7796", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c38000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>, +- <&cpg CPG_CORE R8A7796_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- status = "disabled"; +- }; +- +- canfd: can@e66c0000 { +- compatible = "renesas,r8a7796-canfd", +- "renesas,rcar-gen3-canfd"; +- reg = <0 0xe66c0000 0 0x8000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 914>, +- <&cpg CPG_CORE R8A7796_CLK_CANFD>, +- <&can_clk>; +- clock-names = "fck", "canfd", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 914>; +- status = "disabled"; +- +- channel0 { +- status = "disabled"; +- }; +- +- channel1 { +- status = "disabled"; +- }; +- }; +- +- pwm0: pwm@e6e30000 { +- compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; +- reg = <0 0xe6e30000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm1: pwm@e6e31000 { +- compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; +- reg = <0 0xe6e31000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm2: pwm@e6e32000 { +- compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; +- reg = <0 0xe6e32000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm3: pwm@e6e33000 { +- compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; +- reg = <0 0xe6e33000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm4: pwm@e6e34000 { +- compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; +- reg = <0 0xe6e34000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm5: pwm@e6e35000 { +- compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; +- reg = <0 0xe6e35000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm6: pwm@e6e36000 { +- compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; +- reg = <0 0xe6e36000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a7796", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e60000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>, +- <&cpg CPG_CORE R8A7796_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x51>, <&dmac1 0x50>, +- <&dmac2 0x51>, <&dmac2 0x50>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a7796", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e68000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>, +- <&cpg CPG_CORE R8A7796_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x53>, <&dmac1 0x52>, +- <&dmac2 0x53>, <&dmac2 0x52>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e88000 { +- compatible = "renesas,scif-r8a7796", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e88000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 310>, +- <&cpg CPG_CORE R8A7796_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x13>, <&dmac1 0x12>, +- <&dmac2 0x13>, <&dmac2 0x12>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 310>; +- status = "disabled"; +- }; +- +- scif3: serial@e6c50000 { +- compatible = "renesas,scif-r8a7796", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c50000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>, +- <&cpg CPG_CORE R8A7796_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x57>, <&dmac0 0x56>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scif4: serial@e6c40000 { +- compatible = "renesas,scif-r8a7796", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c40000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>, +- <&cpg CPG_CORE R8A7796_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x59>, <&dmac0 0x58>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- scif5: serial@e6f30000 { +- compatible = "renesas,scif-r8a7796", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6f30000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 202>, +- <&cpg CPG_CORE R8A7796_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, +- <&dmac2 0x5b>, <&dmac2 0x5a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 202>; +- status = "disabled"; +- }; +- +- tpu: pwm@e6e80000 { +- compatible = "renesas,tpu-r8a7796", "renesas,tpu"; +- reg = <0 0xe6e80000 0 0x148>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 304>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 304>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e90000 { +- compatible = "renesas,msiof-r8a7796", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6e90000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 211>; +- dmas = <&dmac1 0x41>, <&dmac1 0x40>, +- <&dmac2 0x41>, <&dmac2 0x40>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 211>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6ea0000 { +- compatible = "renesas,msiof-r8a7796", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6ea0000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 210>; +- dmas = <&dmac1 0x43>, <&dmac1 0x42>, +- <&dmac2 0x43>, <&dmac2 0x42>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 210>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6c00000 { +- compatible = "renesas,msiof-r8a7796", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c00000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 209>; +- dmas = <&dmac0 0x45>, <&dmac0 0x44>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 209>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof3: spi@e6c10000 { +- compatible = "renesas,msiof-r8a7796", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c10000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 208>; +- dmas = <&dmac0 0x47>, <&dmac0 0x46>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 208>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a7796"; +- reg = <0 0xe6ef0000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 811>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 811>; +- renesas,id = <0>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin0csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin0>; +- }; +- vin0csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin0>; +- }; +- }; +- }; +- }; +- +- vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a7796"; +- reg = <0 0xe6ef1000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 810>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 810>; +- renesas,id = <1>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin1csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin1>; +- }; +- vin1csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin1>; +- }; +- }; +- }; +- }; +- +- vin2: video@e6ef2000 { +- compatible = "renesas,vin-r8a7796"; +- reg = <0 0xe6ef2000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 809>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 809>; +- renesas,id = <2>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin2csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin2>; +- }; +- vin2csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin2>; +- }; +- }; +- }; +- }; +- +- vin3: video@e6ef3000 { +- compatible = "renesas,vin-r8a7796"; +- reg = <0 0xe6ef3000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 808>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 808>; +- renesas,id = <3>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin3csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin3>; +- }; +- vin3csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin3>; +- }; +- }; +- }; +- }; +- +- vin4: video@e6ef4000 { +- compatible = "renesas,vin-r8a7796"; +- reg = <0 0xe6ef4000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 807>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 807>; +- renesas,id = <4>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin4csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin4>; +- }; +- vin4csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin4>; +- }; +- }; +- }; +- }; +- +- vin5: video@e6ef5000 { +- compatible = "renesas,vin-r8a7796"; +- reg = <0 0xe6ef5000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 806>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 806>; +- renesas,id = <5>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin5csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin5>; +- }; +- vin5csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin5>; +- }; +- }; +- }; +- }; +- +- vin6: video@e6ef6000 { +- compatible = "renesas,vin-r8a7796"; +- reg = <0 0xe6ef6000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 805>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 805>; +- renesas,id = <6>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin6csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin6>; +- }; +- vin6csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin6>; +- }; +- }; +- }; +- }; +- +- vin7: video@e6ef7000 { +- compatible = "renesas,vin-r8a7796"; +- reg = <0 0xe6ef7000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 804>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 804>; +- renesas,id = <7>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin7csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin7>; +- }; +- vin7csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin7>; +- }; +- }; +- }; +- }; +- +- drif00: rif@e6f40000 { +- compatible = "renesas,r8a7796-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f40000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 515>; +- clock-names = "fck"; +- dmas = <&dmac1 0x20>, <&dmac2 0x20>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 515>; +- renesas,bonding = <&drif01>; +- status = "disabled"; +- }; +- +- drif01: rif@e6f50000 { +- compatible = "renesas,r8a7796-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f50000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 514>; +- clock-names = "fck"; +- dmas = <&dmac1 0x22>, <&dmac2 0x22>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 514>; +- renesas,bonding = <&drif00>; +- status = "disabled"; +- }; +- +- drif10: rif@e6f60000 { +- compatible = "renesas,r8a7796-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f60000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 513>; +- clock-names = "fck"; +- dmas = <&dmac1 0x24>, <&dmac2 0x24>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 513>; +- renesas,bonding = <&drif11>; +- status = "disabled"; +- }; +- +- drif11: rif@e6f70000 { +- compatible = "renesas,r8a7796-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f70000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 512>; +- clock-names = "fck"; +- dmas = <&dmac1 0x26>, <&dmac2 0x26>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 512>; +- renesas,bonding = <&drif10>; +- status = "disabled"; +- }; +- +- drif20: rif@e6f80000 { +- compatible = "renesas,r8a7796-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f80000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 511>; +- clock-names = "fck"; +- dmas = <&dmac1 0x28>, <&dmac2 0x28>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 511>; +- renesas,bonding = <&drif21>; +- status = "disabled"; +- }; +- +- drif21: rif@e6f90000 { +- compatible = "renesas,r8a7796-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f90000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 510>; +- clock-names = "fck"; +- dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 510>; +- renesas,bonding = <&drif20>; +- status = "disabled"; +- }; +- +- drif30: rif@e6fa0000 { +- compatible = "renesas,r8a7796-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6fa0000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 509>; +- clock-names = "fck"; +- dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 509>; +- renesas,bonding = <&drif31>; +- status = "disabled"; +- }; +- +- drif31: rif@e6fb0000 { +- compatible = "renesas,r8a7796-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6fb0000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 508>; +- clock-names = "fck"; +- dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 508>; +- renesas,bonding = <&drif30>; +- status = "disabled"; +- }; +- +- rcar_sound: sound@ec500000 { +- /* +- * #sound-dai-cells is required +- * +- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; +- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; +- */ +- /* +- * #clock-cells is required for audio_clkout0/1/2/3 +- * +- * clkout : #clock-cells = <0>; <&rcar_sound>; +- * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; +- */ +- compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3"; +- reg = <0 0xec500000 0 0x1000>, /* SCU */ +- <0 0xec5a0000 0 0x100>, /* ADG */ +- <0 0xec540000 0 0x1000>, /* SSIU */ +- <0 0xec541000 0 0x280>, /* SSI */ +- <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ +- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; +- +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&audio_clk_b>, +- <&audio_clk_c>, +- <&cpg CPG_CORE R8A7796_CLK_S0D4>; +- clock-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0", +- "src.9", "src.8", "src.7", "src.6", +- "src.5", "src.4", "src.3", "src.2", +- "src.1", "src.0", +- "mix.1", "mix.0", +- "ctu.1", "ctu.0", +- "dvc.0", "dvc.1", +- "clk_a", "clk_b", "clk_c", "clk_i"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 1005>, +- <&cpg 1006>, <&cpg 1007>, +- <&cpg 1008>, <&cpg 1009>, +- <&cpg 1010>, <&cpg 1011>, +- <&cpg 1012>, <&cpg 1013>, +- <&cpg 1014>, <&cpg 1015>; +- reset-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0"; +- status = "disabled"; +- +- rcar_sound,ctu { +- ctu00: ctu-0 { }; +- ctu01: ctu-1 { }; +- ctu02: ctu-2 { }; +- ctu03: ctu-3 { }; +- ctu10: ctu-4 { }; +- ctu11: ctu-5 { }; +- ctu12: ctu-6 { }; +- ctu13: ctu-7 { }; +- }; +- +- rcar_sound,dvc { +- dvc0: dvc-0 { +- dmas = <&audma1 0xbc>; +- dma-names = "tx"; +- }; +- dvc1: dvc-1 { +- dmas = <&audma1 0xbe>; +- dma-names = "tx"; +- }; +- }; +- +- rcar_sound,mix { +- mix0: mix-0 { }; +- mix1: mix-1 { }; +- }; +- +- rcar_sound,src { +- src0: src-0 { +- interrupts = ; +- dmas = <&audma0 0x85>, <&audma1 0x9a>; +- dma-names = "rx", "tx"; +- }; +- src1: src-1 { +- interrupts = ; +- dmas = <&audma0 0x87>, <&audma1 0x9c>; +- dma-names = "rx", "tx"; +- }; +- src2: src-2 { +- interrupts = ; +- dmas = <&audma0 0x89>, <&audma1 0x9e>; +- dma-names = "rx", "tx"; +- }; +- src3: src-3 { +- interrupts = ; +- dmas = <&audma0 0x8b>, <&audma1 0xa0>; +- dma-names = "rx", "tx"; +- }; +- src4: src-4 { +- interrupts = ; +- dmas = <&audma0 0x8d>, <&audma1 0xb0>; +- dma-names = "rx", "tx"; +- }; +- src5: src-5 { +- interrupts = ; +- dmas = <&audma0 0x8f>, <&audma1 0xb2>; +- dma-names = "rx", "tx"; +- }; +- src6: src-6 { +- interrupts = ; +- dmas = <&audma0 0x91>, <&audma1 0xb4>; +- dma-names = "rx", "tx"; +- }; +- src7: src-7 { +- interrupts = ; +- dmas = <&audma0 0x93>, <&audma1 0xb6>; +- dma-names = "rx", "tx"; +- }; +- src8: src-8 { +- interrupts = ; +- dmas = <&audma0 0x95>, <&audma1 0xb8>; +- dma-names = "rx", "tx"; +- }; +- src9: src-9 { +- interrupts = ; +- dmas = <&audma0 0x97>, <&audma1 0xba>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssi { +- ssi0: ssi-0 { +- interrupts = ; +- dmas = <&audma0 0x01>, <&audma1 0x02>; +- dma-names = "rx", "tx"; +- }; +- ssi1: ssi-1 { +- interrupts = ; +- dmas = <&audma0 0x03>, <&audma1 0x04>; +- dma-names = "rx", "tx"; +- }; +- ssi2: ssi-2 { +- interrupts = ; +- dmas = <&audma0 0x05>, <&audma1 0x06>; +- dma-names = "rx", "tx"; +- }; +- ssi3: ssi-3 { +- interrupts = ; +- dmas = <&audma0 0x07>, <&audma1 0x08>; +- dma-names = "rx", "tx"; +- }; +- ssi4: ssi-4 { +- interrupts = ; +- dmas = <&audma0 0x09>, <&audma1 0x0a>; +- dma-names = "rx", "tx"; +- }; +- ssi5: ssi-5 { +- interrupts = ; +- dmas = <&audma0 0x0b>, <&audma1 0x0c>; +- dma-names = "rx", "tx"; +- }; +- ssi6: ssi-6 { +- interrupts = ; +- dmas = <&audma0 0x0d>, <&audma1 0x0e>; +- dma-names = "rx", "tx"; +- }; +- ssi7: ssi-7 { +- interrupts = ; +- dmas = <&audma0 0x0f>, <&audma1 0x10>; +- dma-names = "rx", "tx"; +- }; +- ssi8: ssi-8 { +- interrupts = ; +- dmas = <&audma0 0x11>, <&audma1 0x12>; +- dma-names = "rx", "tx"; +- }; +- ssi9: ssi-9 { +- interrupts = ; +- dmas = <&audma0 0x13>, <&audma1 0x14>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssiu { +- ssiu00: ssiu-0 { +- dmas = <&audma0 0x15>, <&audma1 0x16>; +- dma-names = "rx", "tx"; +- }; +- ssiu01: ssiu-1 { +- dmas = <&audma0 0x35>, <&audma1 0x36>; +- dma-names = "rx", "tx"; +- }; +- ssiu02: ssiu-2 { +- dmas = <&audma0 0x37>, <&audma1 0x38>; +- dma-names = "rx", "tx"; +- }; +- ssiu03: ssiu-3 { +- dmas = <&audma0 0x47>, <&audma1 0x48>; +- dma-names = "rx", "tx"; +- }; +- ssiu04: ssiu-4 { +- dmas = <&audma0 0x3F>, <&audma1 0x40>; +- dma-names = "rx", "tx"; +- }; +- ssiu05: ssiu-5 { +- dmas = <&audma0 0x43>, <&audma1 0x44>; +- dma-names = "rx", "tx"; +- }; +- ssiu06: ssiu-6 { +- dmas = <&audma0 0x4F>, <&audma1 0x50>; +- dma-names = "rx", "tx"; +- }; +- ssiu07: ssiu-7 { +- dmas = <&audma0 0x53>, <&audma1 0x54>; +- dma-names = "rx", "tx"; +- }; +- ssiu10: ssiu-8 { +- dmas = <&audma0 0x49>, <&audma1 0x4a>; +- dma-names = "rx", "tx"; +- }; +- ssiu11: ssiu-9 { +- dmas = <&audma0 0x4B>, <&audma1 0x4C>; +- dma-names = "rx", "tx"; +- }; +- ssiu12: ssiu-10 { +- dmas = <&audma0 0x57>, <&audma1 0x58>; +- dma-names = "rx", "tx"; +- }; +- ssiu13: ssiu-11 { +- dmas = <&audma0 0x59>, <&audma1 0x5A>; +- dma-names = "rx", "tx"; +- }; +- ssiu14: ssiu-12 { +- dmas = <&audma0 0x5F>, <&audma1 0x60>; +- dma-names = "rx", "tx"; +- }; +- ssiu15: ssiu-13 { +- dmas = <&audma0 0xC3>, <&audma1 0xC4>; +- dma-names = "rx", "tx"; +- }; +- ssiu16: ssiu-14 { +- dmas = <&audma0 0xC7>, <&audma1 0xC8>; +- dma-names = "rx", "tx"; +- }; +- ssiu17: ssiu-15 { +- dmas = <&audma0 0xCB>, <&audma1 0xCC>; +- dma-names = "rx", "tx"; +- }; +- ssiu20: ssiu-16 { +- dmas = <&audma0 0x63>, <&audma1 0x64>; +- dma-names = "rx", "tx"; +- }; +- ssiu21: ssiu-17 { +- dmas = <&audma0 0x67>, <&audma1 0x68>; +- dma-names = "rx", "tx"; +- }; +- ssiu22: ssiu-18 { +- dmas = <&audma0 0x6B>, <&audma1 0x6C>; +- dma-names = "rx", "tx"; +- }; +- ssiu23: ssiu-19 { +- dmas = <&audma0 0x6D>, <&audma1 0x6E>; +- dma-names = "rx", "tx"; +- }; +- ssiu24: ssiu-20 { +- dmas = <&audma0 0xCF>, <&audma1 0xCE>; +- dma-names = "rx", "tx"; +- }; +- ssiu25: ssiu-21 { +- dmas = <&audma0 0xEB>, <&audma1 0xEC>; +- dma-names = "rx", "tx"; +- }; +- ssiu26: ssiu-22 { +- dmas = <&audma0 0xED>, <&audma1 0xEE>; +- dma-names = "rx", "tx"; +- }; +- ssiu27: ssiu-23 { +- dmas = <&audma0 0xEF>, <&audma1 0xF0>; +- dma-names = "rx", "tx"; +- }; +- ssiu30: ssiu-24 { +- dmas = <&audma0 0x6f>, <&audma1 0x70>; +- dma-names = "rx", "tx"; +- }; +- ssiu31: ssiu-25 { +- dmas = <&audma0 0x21>, <&audma1 0x22>; +- dma-names = "rx", "tx"; +- }; +- ssiu32: ssiu-26 { +- dmas = <&audma0 0x23>, <&audma1 0x24>; +- dma-names = "rx", "tx"; +- }; +- ssiu33: ssiu-27 { +- dmas = <&audma0 0x25>, <&audma1 0x26>; +- dma-names = "rx", "tx"; +- }; +- ssiu34: ssiu-28 { +- dmas = <&audma0 0x27>, <&audma1 0x28>; +- dma-names = "rx", "tx"; +- }; +- ssiu35: ssiu-29 { +- dmas = <&audma0 0x29>, <&audma1 0x2A>; +- dma-names = "rx", "tx"; +- }; +- ssiu36: ssiu-30 { +- dmas = <&audma0 0x2B>, <&audma1 0x2C>; +- dma-names = "rx", "tx"; +- }; +- ssiu37: ssiu-31 { +- dmas = <&audma0 0x2D>, <&audma1 0x2E>; +- dma-names = "rx", "tx"; +- }; +- ssiu40: ssiu-32 { +- dmas = <&audma0 0x71>, <&audma1 0x72>; +- dma-names = "rx", "tx"; +- }; +- ssiu41: ssiu-33 { +- dmas = <&audma0 0x17>, <&audma1 0x18>; +- dma-names = "rx", "tx"; +- }; +- ssiu42: ssiu-34 { +- dmas = <&audma0 0x19>, <&audma1 0x1A>; +- dma-names = "rx", "tx"; +- }; +- ssiu43: ssiu-35 { +- dmas = <&audma0 0x1B>, <&audma1 0x1C>; +- dma-names = "rx", "tx"; +- }; +- ssiu44: ssiu-36 { +- dmas = <&audma0 0x1D>, <&audma1 0x1E>; +- dma-names = "rx", "tx"; +- }; +- ssiu45: ssiu-37 { +- dmas = <&audma0 0x1F>, <&audma1 0x20>; +- dma-names = "rx", "tx"; +- }; +- ssiu46: ssiu-38 { +- dmas = <&audma0 0x31>, <&audma1 0x32>; +- dma-names = "rx", "tx"; +- }; +- ssiu47: ssiu-39 { +- dmas = <&audma0 0x33>, <&audma1 0x34>; +- dma-names = "rx", "tx"; +- }; +- ssiu50: ssiu-40 { +- dmas = <&audma0 0x73>, <&audma1 0x74>; +- dma-names = "rx", "tx"; +- }; +- ssiu60: ssiu-41 { +- dmas = <&audma0 0x75>, <&audma1 0x76>; +- dma-names = "rx", "tx"; +- }; +- ssiu70: ssiu-42 { +- dmas = <&audma0 0x79>, <&audma1 0x7a>; +- dma-names = "rx", "tx"; +- }; +- ssiu80: ssiu-43 { +- dmas = <&audma0 0x7b>, <&audma1 0x7c>; +- dma-names = "rx", "tx"; +- }; +- ssiu90: ssiu-44 { +- dmas = <&audma0 0x7d>, <&audma1 0x7e>; +- dma-names = "rx", "tx"; +- }; +- ssiu91: ssiu-45 { +- dmas = <&audma0 0x7F>, <&audma1 0x80>; +- dma-names = "rx", "tx"; +- }; +- ssiu92: ssiu-46 { +- dmas = <&audma0 0x81>, <&audma1 0x82>; +- dma-names = "rx", "tx"; +- }; +- ssiu93: ssiu-47 { +- dmas = <&audma0 0x83>, <&audma1 0x84>; +- dma-names = "rx", "tx"; +- }; +- ssiu94: ssiu-48 { +- dmas = <&audma0 0xA3>, <&audma1 0xA4>; +- dma-names = "rx", "tx"; +- }; +- ssiu95: ssiu-49 { +- dmas = <&audma0 0xA5>, <&audma1 0xA6>; +- dma-names = "rx", "tx"; +- }; +- ssiu96: ssiu-50 { +- dmas = <&audma0 0xA7>, <&audma1 0xA8>; +- dma-names = "rx", "tx"; +- }; +- ssiu97: ssiu-51 { +- dmas = <&audma0 0xA9>, <&audma1 0xAA>; +- dma-names = "rx", "tx"; +- }; +- }; +- }; +- +- audma0: dma-controller@ec700000 { +- compatible = "renesas,dmac-r8a7796", +- "renesas,rcar-dmac"; +- reg = <0 0xec700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 502>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 502>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, +- <&ipmmu_mp 2>, <&ipmmu_mp 3>, +- <&ipmmu_mp 4>, <&ipmmu_mp 5>, +- <&ipmmu_mp 6>, <&ipmmu_mp 7>, +- <&ipmmu_mp 8>, <&ipmmu_mp 9>, +- <&ipmmu_mp 10>, <&ipmmu_mp 11>, +- <&ipmmu_mp 12>, <&ipmmu_mp 13>, +- <&ipmmu_mp 14>, <&ipmmu_mp 15>; +- }; +- +- audma1: dma-controller@ec720000 { +- compatible = "renesas,dmac-r8a7796", +- "renesas,rcar-dmac"; +- reg = <0 0xec720000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 501>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 501>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, +- <&ipmmu_mp 18>, <&ipmmu_mp 19>, +- <&ipmmu_mp 20>, <&ipmmu_mp 21>, +- <&ipmmu_mp 22>, <&ipmmu_mp 23>, +- <&ipmmu_mp 24>, <&ipmmu_mp 25>, +- <&ipmmu_mp 26>, <&ipmmu_mp 27>, +- <&ipmmu_mp 28>, <&ipmmu_mp 29>, +- <&ipmmu_mp 30>, <&ipmmu_mp 31>; +- }; +- +- xhci0: usb@ee000000 { +- compatible = "renesas,xhci-r8a7796", +- "renesas,rcar-gen3-xhci"; +- reg = <0 0xee000000 0 0xc00>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- status = "disabled"; +- }; +- +- usb3_peri0: usb@ee020000 { +- compatible = "renesas,r8a7796-usb3-peri", +- "renesas,rcar-gen3-usb3-peri"; +- reg = <0 0xee020000 0 0x400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- status = "disabled"; +- }; +- +- ohci0: usb@ee080000 { +- compatible = "generic-ohci"; +- reg = <0 0xee080000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- ohci1: usb@ee0a0000 { +- compatible = "generic-ohci"; +- reg = <0 0xee0a0000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 702>; +- phys = <&usb2_phy1 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- status = "disabled"; +- }; +- +- ehci0: usb@ee080100 { +- compatible = "generic-ehci"; +- reg = <0 0xee080100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 2>; +- phy-names = "usb"; +- companion = <&ohci0>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- ehci1: usb@ee0a0100 { +- compatible = "generic-ehci"; +- reg = <0 0xee0a0100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 702>; +- phys = <&usb2_phy1 2>; +- phy-names = "usb"; +- companion = <&ohci1>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- status = "disabled"; +- }; +- +- usb2_phy0: usb-phy@ee080200 { +- compatible = "renesas,usb2-phy-r8a7796", +- "renesas,rcar-gen3-usb2-phy"; +- reg = <0 0xee080200 0 0x700>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- usb2_phy1: usb-phy@ee0a0200 { +- compatible = "renesas,usb2-phy-r8a7796", +- "renesas,rcar-gen3-usb2-phy"; +- reg = <0 0xee0a0200 0 0x700>; +- clocks = <&cpg CPG_MOD 702>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a7796", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee100000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- iommus = <&ipmmu_ds1 32>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ee120000 { +- compatible = "renesas,sdhi-r8a7796", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee120000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 313>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 313>; +- iommus = <&ipmmu_ds1 33>; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a7796", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee140000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 312>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 312>; +- iommus = <&ipmmu_ds1 34>; +- status = "disabled"; +- }; +- +- sdhi3: mmc@ee160000 { +- compatible = "renesas,sdhi-r8a7796", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee160000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 311>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 311>; +- iommus = <&ipmmu_ds1 35>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1010000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x0 0xf1010000 0 0x1000>, +- <0x0 0xf1020000 0 0x20000>, +- <0x0 0xf1040000 0 0x20000>, +- <0x0 0xf1060000 0 0x20000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- pciec0: pcie@fe000000 { +- compatible = "renesas,pcie-r8a7796", +- "renesas,pcie-rcar-gen3"; +- reg = <0 0xfe000000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, +- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, +- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, +- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 319>; +- status = "disabled"; +- }; +- +- pciec1: pcie@ee800000 { +- compatible = "renesas,pcie-r8a7796", +- "renesas,pcie-rcar-gen3"; +- reg = <0 0xee800000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, +- <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, +- <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, +- <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 318>; +- status = "disabled"; +- }; +- +- imr-lx4@fe860000 { +- compatible = "renesas,r8a7796-imr-lx4", +- "renesas,imr-lx4"; +- reg = <0 0xfe860000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 823>; +- power-domains = <&sysc R8A7796_PD_A3VC>; +- resets = <&cpg 823>; +- }; +- +- imr-lx4@fe870000 { +- compatible = "renesas,r8a7796-imr-lx4", +- "renesas,imr-lx4"; +- reg = <0 0xfe870000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 822>; +- power-domains = <&sysc R8A7796_PD_A3VC>; +- resets = <&cpg 822>; +- }; +- +- fdp1@fe940000 { +- compatible = "renesas,fdp1"; +- reg = <0 0xfe940000 0 0x2400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 119>; +- power-domains = <&sysc R8A7796_PD_A3VC>; +- resets = <&cpg 119>; +- renesas,fcp = <&fcpf0>; +- }; +- +- fcpf0: fcp@fe950000 { +- compatible = "renesas,fcpf"; +- reg = <0 0xfe950000 0 0x200>; +- clocks = <&cpg CPG_MOD 615>; +- power-domains = <&sysc R8A7796_PD_A3VC>; +- resets = <&cpg 615>; +- }; +- +- fcpvb0: fcp@fe96f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe96f000 0 0x200>; +- clocks = <&cpg CPG_MOD 607>; +- power-domains = <&sysc R8A7796_PD_A3VC>; +- resets = <&cpg 607>; +- }; +- +- fcpvi0: fcp@fe9af000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe9af000 0 0x200>; +- clocks = <&cpg CPG_MOD 611>; +- power-domains = <&sysc R8A7796_PD_A3VC>; +- resets = <&cpg 611>; +- iommus = <&ipmmu_vc0 19>; +- }; +- +- fcpvd0: fcp@fea27000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea27000 0 0x200>; +- clocks = <&cpg CPG_MOD 603>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 603>; +- iommus = <&ipmmu_vi0 8>; +- }; +- +- fcpvd1: fcp@fea2f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea2f000 0 0x200>; +- clocks = <&cpg CPG_MOD 602>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 602>; +- iommus = <&ipmmu_vi0 9>; +- }; +- +- fcpvd2: fcp@fea37000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea37000 0 0x200>; +- clocks = <&cpg CPG_MOD 601>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 601>; +- iommus = <&ipmmu_vi0 10>; +- }; +- +- vspb: vsp@fe960000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe960000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 626>; +- power-domains = <&sysc R8A7796_PD_A3VC>; +- resets = <&cpg 626>; +- +- renesas,fcp = <&fcpvb0>; +- }; +- +- vspd0: vsp@fea20000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea20000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 623>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 623>; +- +- renesas,fcp = <&fcpvd0>; +- }; +- +- vspd1: vsp@fea28000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea28000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 622>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 622>; +- +- renesas,fcp = <&fcpvd1>; +- }; +- +- vspd2: vsp@fea30000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea30000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 621>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 621>; +- +- renesas,fcp = <&fcpvd2>; +- }; +- +- vspi0: vsp@fe9a0000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe9a0000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 631>; +- power-domains = <&sysc R8A7796_PD_A3VC>; +- resets = <&cpg 631>; +- +- renesas,fcp = <&fcpvi0>; +- }; +- +- cmm0: cmm@fea40000 { +- compatible = "renesas,r8a7796-cmm", +- "renesas,rcar-gen3-cmm"; +- reg = <0 0xfea40000 0 0x1000>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- clocks = <&cpg CPG_MOD 711>; +- resets = <&cpg 711>; +- }; +- +- cmm1: cmm@fea50000 { +- compatible = "renesas,r8a7796-cmm", +- "renesas,rcar-gen3-cmm"; +- reg = <0 0xfea50000 0 0x1000>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- clocks = <&cpg CPG_MOD 710>; +- resets = <&cpg 710>; +- }; +- +- cmm2: cmm@fea60000 { +- compatible = "renesas,r8a7796-cmm", +- "renesas,rcar-gen3-cmm"; +- reg = <0 0xfea60000 0 0x1000>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- clocks = <&cpg CPG_MOD 709>; +- resets = <&cpg 709>; +- }; +- +- csi20: csi2@fea80000 { +- compatible = "renesas,r8a7796-csi2"; +- reg = <0 0xfea80000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 714>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 714>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi20vin0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin0csi20>; +- }; +- csi20vin1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin1csi20>; +- }; +- csi20vin2: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&vin2csi20>; +- }; +- csi20vin3: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&vin3csi20>; +- }; +- csi20vin4: endpoint@4 { +- reg = <4>; +- remote-endpoint = <&vin4csi20>; +- }; +- csi20vin5: endpoint@5 { +- reg = <5>; +- remote-endpoint = <&vin5csi20>; +- }; +- csi20vin6: endpoint@6 { +- reg = <6>; +- remote-endpoint = <&vin6csi20>; +- }; +- csi20vin7: endpoint@7 { +- reg = <7>; +- remote-endpoint = <&vin7csi20>; +- }; +- }; +- }; +- }; +- +- csi40: csi2@feaa0000 { +- compatible = "renesas,r8a7796-csi2"; +- reg = <0 0xfeaa0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi40vin0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin0csi40>; +- }; +- csi40vin1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin1csi40>; +- }; +- csi40vin2: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&vin2csi40>; +- }; +- csi40vin3: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&vin3csi40>; +- }; +- csi40vin4: endpoint@4 { +- reg = <4>; +- remote-endpoint = <&vin4csi40>; +- }; +- csi40vin5: endpoint@5 { +- reg = <5>; +- remote-endpoint = <&vin5csi40>; +- }; +- csi40vin6: endpoint@6 { +- reg = <6>; +- remote-endpoint = <&vin6csi40>; +- }; +- csi40vin7: endpoint@7 { +- reg = <7>; +- remote-endpoint = <&vin7csi40>; +- }; +- }; +- +- }; +- }; +- +- hdmi0: hdmi@fead0000 { +- compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi"; +- reg = <0 0xfead0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>; +- clock-names = "iahb", "isfr"; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 729>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- dw_hdmi0_in: endpoint { +- remote-endpoint = <&du_out_hdmi0>; +- }; +- }; +- port@1 { +- reg = <1>; +- }; +- port@2 { +- /* HDMI sound */ +- reg = <2>; +- }; +- }; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a7796"; +- reg = <0 0xfeb00000 0 0x70000>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>; +- clock-names = "du.0", "du.1", "du.2"; +- resets = <&cpg 724>, <&cpg 722>; +- reset-names = "du.0", "du.2"; +- +- renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>; +- renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; +- +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb: endpoint { +- }; +- }; +- port@1 { +- reg = <1>; +- du_out_hdmi0: endpoint { +- remote-endpoint = <&dw_hdmi0_in>; +- }; +- }; +- port@2 { +- reg = <2>; +- du_out_lvds0: endpoint { +- remote-endpoint = <&lvds0_in>; +- }; +- }; +- }; +- }; +- +- lvds0: lvds@feb90000 { +- compatible = "renesas,r8a7796-lvds"; +- reg = <0 0xfeb90000 0 0x14>; +- clocks = <&cpg CPG_MOD 727>; +- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- resets = <&cpg 727>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds0_in: endpoint { +- remote-endpoint = <&du_out_lvds0>; +- }; +- }; +- port@1 { +- reg = <1>; +- lvds0_out: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@fff00044 { +- compatible = "renesas,prr"; +- reg = <0 0xfff00044 0 4>; +- }; +- }; +- +- thermal-zones { +- sensor1_thermal: sensor1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 0>; +- sustainable-power = <3874>; +- +- trips { +- sensor1_crit: sensor1-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- sensor2_thermal: sensor2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 1>; +- sustainable-power = <3874>; +- +- trips { +- sensor2_crit: sensor2-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- sensor3_thermal: sensor3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 2>; +- sustainable-power = <3874>; +- +- cooling-maps { +- map0 { +- trip = <&target>; +- cooling-device = <&a57_0 2 4>; +- contribution = <1024>; +- }; +- map1 { +- trip = <&target>; +- cooling-device = <&a53_0 0 2>; +- contribution = <1024>; +- }; +- }; +- trips { +- target: trip-point1 { +- temperature = <100000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- +- sensor3_crit: sensor3-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; +- }; +- +- /* External USB clocks - can be overridden by the board */ +- usb3s0_clk: usb3s0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- usb_extal_clk: usb_extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77961-salvator-xs.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77961-salvator-xs.dts +deleted file mode 100644 +index c7f14177f7b9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77961-salvator-xs.dts ++++ /dev/null +@@ -1,42 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-W+ +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a77961.dtsi" +-#include "salvator-xs.dtsi" +- +-/ { +- model = "Renesas Salvator-X 2nd version board based on r8a77961"; +- compatible = "renesas,salvator-xs", "renesas,r8a77961"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x78000000>; +- }; +- +- memory@480000000 { +- device_type = "memory"; +- reg = <0x4 0x80000000 0x0 0x80000000>; +- }; +- +- memory@600000000 { +- device_type = "memory"; +- reg = <0x6 0x00000000 0x1 0x00000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>, +- <&versaclock6 1>, +- <&x21_clk>, +- <&versaclock6 2>; +- clock-names = "du.0", "du.1", "du.2", +- "dclkin.0", "dclkin.1", "dclkin.2"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77961-ulcb-kf.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77961-ulcb-kf.dts +deleted file mode 100644 +index d66eb27ee8c4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77961-ulcb-kf.dts ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the M3ULCB Kingfisher board with R-Car M3-W+ +- * +- * Copyright (C) 2020 Eugeniu Rosca +- */ +- +-#include "r8a77961-ulcb.dts" +-#include "ulcb-kf.dtsi" +- +-/ { +- model = "Renesas M3ULCB Kingfisher board based on r8a77961"; +- compatible = "shimafuji,kingfisher", "renesas,m3ulcb", +- "renesas,r8a77961"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77961-ulcb.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77961-ulcb.dts +deleted file mode 100644 +index 70cf926667a6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77961-ulcb.dts ++++ /dev/null +@@ -1,42 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board with R-Car M3-W+ +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a77961.dtsi" +-#include "ulcb.dtsi" +- +-/ { +- model = "Renesas M3ULCB board based on r8a77961"; +- compatible = "renesas,m3ulcb", "renesas,r8a77961"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x78000000>; +- }; +- +- memory@480000000 { +- device_type = "memory"; +- reg = <0x4 0x80000000 0x0 0x80000000>; +- }; +- +- memory@600000000 { +- device_type = "memory"; +- reg = <0x6 0x00000000 0x1 0x00000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>, +- <&versaclock5 1>, +- <&versaclock5 3>, +- <&versaclock5 2>; +- clock-names = "du.0", "du.1", "du.2", +- "dclkin.0", "dclkin.1", "dclkin.2"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77961.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r8a77961.dtsi +deleted file mode 100644 +index 21fc95397c3c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77961.dtsi ++++ /dev/null +@@ -1,2806 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC +- * +- * Copyright (C) 2016-2017 Renesas Electronics Corp. +- */ +- +-#include +-#include +-#include +- +-#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4 +- +-/ { +- compatible = "renesas,r8a77961"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- /* +- * The external audio clocks are configured as 0 Hz fixed frequency +- * clocks by default. +- * Boards that provide audio clocks should override them. +- */ +- audio_clk_a: audio_clk_a { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_b: audio_clk_b { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_c: audio_clk_c { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* External CAN clock - to be overridden by boards that provide it */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- cluster0_opp: opp_table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <830000>; +- clock-latency-ns = <300000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <830000>; +- clock-latency-ns = <300000>; +- }; +- opp-1500000000 { +- opp-hz = /bits/ 64 <1500000000>; +- opp-microvolt = <830000>; +- clock-latency-ns = <300000>; +- opp-suspend; +- }; +- opp-1600000000 { +- opp-hz = /bits/ 64 <1600000000>; +- opp-microvolt = <900000>; +- clock-latency-ns = <300000>; +- turbo-mode; +- }; +- opp-1700000000 { +- opp-hz = /bits/ 64 <1700000000>; +- opp-microvolt = <900000>; +- clock-latency-ns = <300000>; +- turbo-mode; +- }; +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <960000>; +- clock-latency-ns = <300000>; +- turbo-mode; +- }; +- }; +- +- cluster1_opp: opp_table1 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1300000000 { +- opp-hz = /bits/ 64 <1300000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- turbo-mode; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&a57_0>; +- }; +- core1 { +- cpu = <&a57_1>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&a53_0>; +- }; +- core1 { +- cpu = <&a53_1>; +- }; +- core2 { +- cpu = <&a53_2>; +- }; +- core3 { +- cpu = <&a53_3>; +- }; +- }; +- }; +- +- a57_0: cpu@0 { +- compatible = "arm,cortex-a57"; +- reg = <0x0>; +- device_type = "cpu"; +- power-domains = <&sysc R8A77961_PD_CA57_CPU0>; +- next-level-cache = <&L2_CA57>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- dynamic-power-coefficient = <854>; +- clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; +- operating-points-v2 = <&cluster0_opp>; +- capacity-dmips-mhz = <1024>; +- #cooling-cells = <2>; +- }; +- +- a57_1: cpu@1 { +- compatible = "arm,cortex-a57"; +- reg = <0x1>; +- device_type = "cpu"; +- power-domains = <&sysc R8A77961_PD_CA57_CPU1>; +- next-level-cache = <&L2_CA57>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; +- operating-points-v2 = <&cluster0_opp>; +- capacity-dmips-mhz = <1024>; +- #cooling-cells = <2>; +- }; +- +- a53_0: cpu@100 { +- compatible = "arm,cortex-a53"; +- reg = <0x100>; +- device_type = "cpu"; +- power-domains = <&sysc R8A77961_PD_CA53_CPU0>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_1>; +- #cooling-cells = <2>; +- dynamic-power-coefficient = <277>; +- clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <535>; +- }; +- +- a53_1: cpu@101 { +- compatible = "arm,cortex-a53"; +- reg = <0x101>; +- device_type = "cpu"; +- power-domains = <&sysc R8A77961_PD_CA53_CPU1>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_1>; +- clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <535>; +- }; +- +- a53_2: cpu@102 { +- compatible = "arm,cortex-a53"; +- reg = <0x102>; +- device_type = "cpu"; +- power-domains = <&sysc R8A77961_PD_CA53_CPU2>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_1>; +- clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <535>; +- }; +- +- a53_3: cpu@103 { +- compatible = "arm,cortex-a53"; +- reg = <0x103>; +- device_type = "cpu"; +- power-domains = <&sysc R8A77961_PD_CA53_CPU3>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_1>; +- clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- capacity-dmips-mhz = <535>; +- }; +- +- L2_CA57: cache-controller-0 { +- compatible = "cache"; +- power-domains = <&sysc R8A77961_PD_CA57_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- +- L2_CA53: cache-controller-1 { +- compatible = "cache"; +- power-domains = <&sysc R8A77961_PD_CA53_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP_0: cpu-sleep-0 { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x0010000>; +- local-timer-stop; +- entry-latency-us = <400>; +- exit-latency-us = <500>; +- min-residency-us = <4000>; +- }; +- +- CPU_SLEEP_1: cpu-sleep-1 { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x0010000>; +- local-timer-stop; +- entry-latency-us = <700>; +- exit-latency-us = <700>; +- min-residency-us = <5000>; +- }; +- }; +- }; +- +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- extalr_clk: extalr { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- /* External PCIe clock - can be overridden by the board */ +- pcie_bus_clk: pcie_bus { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- pmu_a53 { +- compatible = "arm,cortex-a53-pmu"; +- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; +- }; +- +- pmu_a57 { +- compatible = "arm,cortex-a57-pmu"; +- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&a57_0>, <&a57_1>; +- }; +- +- psci { +- compatible = "arm,psci-1.0", "arm,psci-0.2"; +- method = "smc"; +- }; +- +- /* External SCIF clock - to be overridden by boards that provide it */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a77961-wdt", +- "renesas,rcar-gen3-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a77961", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 16>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a77961", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 29>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a77961", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 15>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a77961", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 16>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a77961", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 18>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a77961", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- gpio6: gpio@e6055400 { +- compatible = "renesas,gpio-r8a77961", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055400 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 192 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 906>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 906>; +- }; +- +- gpio7: gpio@e6055800 { +- compatible = "renesas,gpio-r8a77961", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055800 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 224 4>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 905>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 905>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a77961"; +- reg = <0 0xe6060000 0 0x50c>; +- }; +- +- cmt0: timer@e60f0000 { +- compatible = "renesas,r8a77961-cmt0", +- "renesas,rcar-gen3-cmt0"; +- reg = <0 0xe60f0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 303>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 303>; +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a77961-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 302>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 302>; +- status = "disabled"; +- }; +- +- cmt2: timer@e6140000 { +- compatible = "renesas,r8a77961-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6140000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 301>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 301>; +- status = "disabled"; +- }; +- +- cmt3: timer@e6148000 { +- compatible = "renesas,r8a77961-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6148000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 300>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 300>; +- status = "disabled"; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a77961-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>, <&extalr_clk>; +- clock-names = "extal", "extalr"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a77961-rst"; +- reg = <0 0xe6160000 0 0x0200>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a77961-sysc"; +- reg = <0 0xe6180000 0 0x0400>; +- #power-domain-cells = <1>; +- }; +- +- tsc: thermal@e6198000 { +- compatible = "renesas,r8a77961-thermal"; +- reg = <0 0xe6198000 0 0x100>, +- <0 0xe61a0000 0 0x100>, +- <0 0xe61a8000 0 0x100>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 522>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 522>; +- #thermal-sensor-cells = <1>; +- }; +- +- intc_ex: interrupt-controller@e61c0000 { +- compatible = "renesas,intc-ex-r8a77961", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- tmu0: timer@e61e0000 { +- compatible = "renesas,tmu-r8a77961", "renesas,tmu"; +- reg = <0 0xe61e0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 125>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 125>; +- status = "disabled"; +- }; +- +- tmu1: timer@e6fc0000 { +- compatible = "renesas,tmu-r8a77961", "renesas,tmu"; +- reg = <0 0xe6fc0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- status = "disabled"; +- }; +- +- tmu2: timer@e6fd0000 { +- compatible = "renesas,tmu-r8a77961", "renesas,tmu"; +- reg = <0 0xe6fd0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 123>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 123>; +- status = "disabled"; +- }; +- +- tmu3: timer@e6fe0000 { +- compatible = "renesas,tmu-r8a77961", "renesas,tmu"; +- reg = <0 0xe6fe0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 122>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 122>; +- status = "disabled"; +- }; +- +- tmu4: timer@ffc00000 { +- compatible = "renesas,tmu-r8a77961", "renesas,tmu"; +- reg = <0 0xffc00000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 121>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 121>; +- status = "disabled"; +- }; +- +- i2c0: i2c@e6500000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77961", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6500000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- dmas = <&dmac1 0x91>, <&dmac1 0x90>, +- <&dmac2 0x91>, <&dmac2 0x90>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6508000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77961", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- dmas = <&dmac1 0x93>, <&dmac1 0x92>, +- <&dmac2 0x93>, <&dmac2 0x92>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6510000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77961", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6510000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- dmas = <&dmac1 0x95>, <&dmac1 0x94>, +- <&dmac2 0x95>, <&dmac2 0x94>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e66d0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77961", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- dmas = <&dmac0 0x97>, <&dmac0 0x96>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e66d8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77961", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 927>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 927>; +- dmas = <&dmac0 0x99>, <&dmac0 0x98>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c5: i2c@e66e0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77961", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 919>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 919>; +- dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c6: i2c@e66e8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77961", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 918>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 918>; +- dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c_dvfs: i2c@e60b0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a77961", +- "renesas,rcar-gen3-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe60b0000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 926>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 926>; +- dmas = <&dmac0 0x11>, <&dmac0 0x10>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- hscif0: serial@e6540000 { +- compatible = "renesas,hscif-r8a77961", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6540000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 520>, +- <&cpg CPG_CORE R8A77961_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x31>, <&dmac1 0x30>, +- <&dmac2 0x31>, <&dmac2 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 520>; +- status = "disabled"; +- }; +- +- hscif1: serial@e6550000 { +- compatible = "renesas,hscif-r8a77961", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6550000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 519>, +- <&cpg CPG_CORE R8A77961_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x33>, <&dmac1 0x32>, +- <&dmac2 0x33>, <&dmac2 0x32>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 519>; +- status = "disabled"; +- }; +- +- hscif2: serial@e6560000 { +- compatible = "renesas,hscif-r8a77961", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6560000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 518>, +- <&cpg CPG_CORE R8A77961_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x35>, <&dmac1 0x34>, +- <&dmac2 0x35>, <&dmac2 0x34>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 518>; +- status = "disabled"; +- }; +- +- hscif3: serial@e66a0000 { +- compatible = "renesas,hscif-r8a77961", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66a0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 517>, +- <&cpg CPG_CORE R8A77961_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x37>, <&dmac0 0x36>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 517>; +- status = "disabled"; +- }; +- +- hscif4: serial@e66b0000 { +- compatible = "renesas,hscif-r8a77961", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66b0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 516>, +- <&cpg CPG_CORE R8A77961_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x39>, <&dmac0 0x38>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 516>; +- status = "disabled"; +- }; +- +- hsusb: usb@e6590000 { +- compatible = "renesas,usbhs-r8a77961", +- "renesas,rcar-gen3-usbhs"; +- reg = <0 0xe6590000 0 0x200>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; +- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, +- <&usb_dmac1 0>, <&usb_dmac1 1>; +- dma-names = "ch0", "ch1", "ch2", "ch3"; +- renesas,buswait = <11>; +- phys = <&usb2_phy0 3>; +- phy-names = "usb"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 704>, <&cpg 703>; +- status = "disabled"; +- }; +- +- usb_dmac0: dma-controller@e65a0000 { +- compatible = "renesas,r8a77961-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65a0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 330>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 330>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac1: dma-controller@e65b0000 { +- compatible = "renesas,r8a77961-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65b0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 331>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 331>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb3_phy0: usb-phy@e65ee000 { +- compatible = "renesas,r8a77961-usb3-phy", +- "renesas,rcar-gen3-usb3-phy"; +- reg = <0 0xe65ee000 0 0x90>; +- clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, +- <&usb_extal_clk>; +- clock-names = "usb3-if", "usb3s_clk", "usb_extal"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- arm_cc630p: crypto@e6601000 { +- compatible = "arm,cryptocell-630p-ree"; +- interrupts = ; +- reg = <0x0 0xe6601000 0 0x1000>; +- clocks = <&cpg CPG_MOD 229>; +- resets = <&cpg 229>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a77961", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, +- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, +- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, +- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, +- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, +- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, +- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, +- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; +- }; +- +- dmac1: dma-controller@e7300000 { +- compatible = "renesas,dmac-r8a77961", +- "renesas,rcar-dmac"; +- reg = <0 0xe7300000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, +- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, +- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, +- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, +- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, +- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, +- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, +- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; +- }; +- +- dmac2: dma-controller@e7310000 { +- compatible = "renesas,dmac-r8a77961", +- "renesas,rcar-dmac"; +- reg = <0 0xe7310000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 217>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 217>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, +- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, +- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, +- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, +- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, +- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, +- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, +- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; +- }; +- +- ipmmu_ds0: iommu@e6740000 { +- compatible = "renesas,ipmmu-r8a77961"; +- reg = <0 0xe6740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 0>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_ds1: iommu@e7740000 { +- compatible = "renesas,ipmmu-r8a77961"; +- reg = <0 0xe7740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 1>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_hc: iommu@e6570000 { +- compatible = "renesas,ipmmu-r8a77961"; +- reg = <0 0xe6570000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 2>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_ir: iommu@ff8b0000 { +- compatible = "renesas,ipmmu-r8a77961"; +- reg = <0 0xff8b0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 3>; +- power-domains = <&sysc R8A77961_PD_A3IR>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mm: iommu@e67b0000 { +- compatible = "renesas,ipmmu-r8a77961"; +- reg = <0 0xe67b0000 0 0x1000>; +- interrupts = , +- ; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mp: iommu@ec670000 { +- compatible = "renesas,ipmmu-r8a77961"; +- reg = <0 0xec670000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 4>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_pv0: iommu@fd800000 { +- compatible = "renesas,ipmmu-r8a77961"; +- reg = <0 0xfd800000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 5>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_pv1: iommu@fd950000 { +- compatible = "renesas,ipmmu-r8a77961"; +- reg = <0 0xfd950000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 6>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_rt: iommu@ffc80000 { +- compatible = "renesas,ipmmu-r8a77961"; +- reg = <0 0xffc80000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 7>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vc0: iommu@fe6b0000 { +- compatible = "renesas,ipmmu-r8a77961"; +- reg = <0 0xfe6b0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 8>; +- power-domains = <&sysc R8A77961_PD_A3VC>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vi0: iommu@febd0000 { +- compatible = "renesas,ipmmu-r8a77961"; +- reg = <0 0xfebd0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 9>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a77961", +- "renesas,etheravb-rcar-gen3"; +- reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15", +- "ch16", "ch17", "ch18", "ch19", +- "ch20", "ch21", "ch22", "ch23", +- "ch24"; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- phy-mode = "rgmii"; +- rx-internal-delay-ps = <0>; +- tx-internal-delay-ps = <0>; +- iommus = <&ipmmu_ds0 16>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- can0: can@e6c30000 { +- compatible = "renesas,can-r8a77961", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c30000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>, +- <&cpg CPG_CORE R8A77961_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- status = "disabled"; +- }; +- +- can1: can@e6c38000 { +- compatible = "renesas,can-r8a77961", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c38000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>, +- <&cpg CPG_CORE R8A77961_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- status = "disabled"; +- }; +- +- pwm0: pwm@e6e30000 { +- compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; +- reg = <0 0xe6e30000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm1: pwm@e6e31000 { +- compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; +- reg = <0 0xe6e31000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm2: pwm@e6e32000 { +- compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; +- reg = <0 0xe6e32000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm3: pwm@e6e33000 { +- compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; +- reg = <0 0xe6e33000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm4: pwm@e6e34000 { +- compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; +- reg = <0 0xe6e34000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm5: pwm@e6e35000 { +- compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; +- reg = <0 0xe6e35000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm6: pwm@e6e36000 { +- compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; +- reg = <0 0xe6e36000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a77961", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e60000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>, +- <&cpg CPG_CORE R8A77961_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x51>, <&dmac1 0x50>, +- <&dmac2 0x51>, <&dmac2 0x50>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a77961", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e68000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>, +- <&cpg CPG_CORE R8A77961_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x53>, <&dmac1 0x52>, +- <&dmac2 0x53>, <&dmac2 0x52>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e88000 { +- compatible = "renesas,scif-r8a77961", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e88000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 310>, +- <&cpg CPG_CORE R8A77961_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x13>, <&dmac1 0x12>, +- <&dmac2 0x13>, <&dmac2 0x12>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 310>; +- status = "disabled"; +- }; +- +- scif3: serial@e6c50000 { +- compatible = "renesas,scif-r8a77961", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c50000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>, +- <&cpg CPG_CORE R8A77961_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x57>, <&dmac0 0x56>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scif4: serial@e6c40000 { +- compatible = "renesas,scif-r8a77961", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c40000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>, +- <&cpg CPG_CORE R8A77961_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x59>, <&dmac0 0x58>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- scif5: serial@e6f30000 { +- compatible = "renesas,scif-r8a77961", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6f30000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 202>, +- <&cpg CPG_CORE R8A77961_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, +- <&dmac2 0x5b>, <&dmac2 0x5a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 202>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e90000 { +- compatible = "renesas,msiof-r8a77961", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6e90000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 211>; +- dmas = <&dmac1 0x41>, <&dmac1 0x40>, +- <&dmac2 0x41>, <&dmac2 0x40>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 211>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6ea0000 { +- compatible = "renesas,msiof-r8a77961", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6ea0000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 210>; +- dmas = <&dmac1 0x43>, <&dmac1 0x42>, +- <&dmac2 0x43>, <&dmac2 0x42>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 210>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6c00000 { +- compatible = "renesas,msiof-r8a77961", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c00000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 209>; +- dmas = <&dmac0 0x45>, <&dmac0 0x44>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 209>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof3: spi@e6c10000 { +- compatible = "renesas,msiof-r8a77961", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c10000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 208>; +- dmas = <&dmac0 0x47>, <&dmac0 0x46>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 208>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a77961"; +- reg = <0 0xe6ef0000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 811>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 811>; +- renesas,id = <0>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin0csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin0>; +- }; +- vin0csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin0>; +- }; +- }; +- }; +- }; +- +- vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a77961"; +- reg = <0 0xe6ef1000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 810>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 810>; +- renesas,id = <1>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin1csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin1>; +- }; +- vin1csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin1>; +- }; +- }; +- }; +- }; +- +- vin2: video@e6ef2000 { +- compatible = "renesas,vin-r8a77961"; +- reg = <0 0xe6ef2000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 809>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 809>; +- renesas,id = <2>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin2csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin2>; +- }; +- vin2csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin2>; +- }; +- }; +- }; +- }; +- +- vin3: video@e6ef3000 { +- compatible = "renesas,vin-r8a77961"; +- reg = <0 0xe6ef3000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 808>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 808>; +- renesas,id = <3>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin3csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin3>; +- }; +- vin3csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin3>; +- }; +- }; +- }; +- }; +- +- vin4: video@e6ef4000 { +- compatible = "renesas,vin-r8a77961"; +- reg = <0 0xe6ef4000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 807>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 807>; +- renesas,id = <4>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin4csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin4>; +- }; +- vin4csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin4>; +- }; +- }; +- }; +- }; +- +- vin5: video@e6ef5000 { +- compatible = "renesas,vin-r8a77961"; +- reg = <0 0xe6ef5000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 806>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 806>; +- renesas,id = <5>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin5csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin5>; +- }; +- vin5csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin5>; +- }; +- }; +- }; +- }; +- +- vin6: video@e6ef6000 { +- compatible = "renesas,vin-r8a77961"; +- reg = <0 0xe6ef6000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 805>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 805>; +- renesas,id = <6>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin6csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin6>; +- }; +- vin6csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin6>; +- }; +- }; +- }; +- }; +- +- vin7: video@e6ef7000 { +- compatible = "renesas,vin-r8a77961"; +- reg = <0 0xe6ef7000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 804>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 804>; +- renesas,id = <7>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin7csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin7>; +- }; +- vin7csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin7>; +- }; +- }; +- }; +- }; +- +- rcar_sound: sound@ec500000 { +- /* +- * #sound-dai-cells is required +- * +- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; +- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; +- */ +- /* +- * #clock-cells is required for audio_clkout0/1/2/3 +- * +- * clkout : #clock-cells = <0>; <&rcar_sound>; +- * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; +- */ +- compatible = "renesas,rcar_sound-r8a77961", "renesas,rcar_sound-gen3"; +- reg = <0 0xec500000 0 0x1000>, /* SCU */ +- <0 0xec5a0000 0 0x100>, /* ADG */ +- <0 0xec540000 0 0x1000>, /* SSIU */ +- <0 0xec541000 0 0x280>, /* SSI */ +- <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ +- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; +- +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&audio_clk_b>, +- <&audio_clk_c>, +- <&cpg CPG_CORE R8A77961_CLK_S0D4>; +- clock-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0", +- "src.9", "src.8", "src.7", "src.6", +- "src.5", "src.4", "src.3", "src.2", +- "src.1", "src.0", +- "mix.1", "mix.0", +- "ctu.1", "ctu.0", +- "dvc.0", "dvc.1", +- "clk_a", "clk_b", "clk_c", "clk_i"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 1005>, +- <&cpg 1006>, <&cpg 1007>, +- <&cpg 1008>, <&cpg 1009>, +- <&cpg 1010>, <&cpg 1011>, +- <&cpg 1012>, <&cpg 1013>, +- <&cpg 1014>, <&cpg 1015>; +- reset-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0"; +- status = "disabled"; +- +- rcar_sound,ctu { +- ctu00: ctu-0 { }; +- ctu01: ctu-1 { }; +- ctu02: ctu-2 { }; +- ctu03: ctu-3 { }; +- ctu10: ctu-4 { }; +- ctu11: ctu-5 { }; +- ctu12: ctu-6 { }; +- ctu13: ctu-7 { }; +- }; +- +- rcar_sound,dvc { +- dvc0: dvc-0 { +- dmas = <&audma1 0xbc>; +- dma-names = "tx"; +- }; +- dvc1: dvc-1 { +- dmas = <&audma1 0xbe>; +- dma-names = "tx"; +- }; +- }; +- +- rcar_sound,mix { +- mix0: mix-0 { }; +- mix1: mix-1 { }; +- }; +- +- rcar_sound,src { +- src0: src-0 { +- interrupts = ; +- dmas = <&audma0 0x85>, <&audma1 0x9a>; +- dma-names = "rx", "tx"; +- }; +- src1: src-1 { +- interrupts = ; +- dmas = <&audma0 0x87>, <&audma1 0x9c>; +- dma-names = "rx", "tx"; +- }; +- src2: src-2 { +- interrupts = ; +- dmas = <&audma0 0x89>, <&audma1 0x9e>; +- dma-names = "rx", "tx"; +- }; +- src3: src-3 { +- interrupts = ; +- dmas = <&audma0 0x8b>, <&audma1 0xa0>; +- dma-names = "rx", "tx"; +- }; +- src4: src-4 { +- interrupts = ; +- dmas = <&audma0 0x8d>, <&audma1 0xb0>; +- dma-names = "rx", "tx"; +- }; +- src5: src-5 { +- interrupts = ; +- dmas = <&audma0 0x8f>, <&audma1 0xb2>; +- dma-names = "rx", "tx"; +- }; +- src6: src-6 { +- interrupts = ; +- dmas = <&audma0 0x91>, <&audma1 0xb4>; +- dma-names = "rx", "tx"; +- }; +- src7: src-7 { +- interrupts = ; +- dmas = <&audma0 0x93>, <&audma1 0xb6>; +- dma-names = "rx", "tx"; +- }; +- src8: src-8 { +- interrupts = ; +- dmas = <&audma0 0x95>, <&audma1 0xb8>; +- dma-names = "rx", "tx"; +- }; +- src9: src-9 { +- interrupts = ; +- dmas = <&audma0 0x97>, <&audma1 0xba>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssi { +- ssi0: ssi-0 { +- interrupts = ; +- dmas = <&audma0 0x01>, <&audma1 0x02>; +- dma-names = "rx", "tx"; +- }; +- ssi1: ssi-1 { +- interrupts = ; +- dmas = <&audma0 0x03>, <&audma1 0x04>; +- dma-names = "rx", "tx"; +- }; +- ssi2: ssi-2 { +- interrupts = ; +- dmas = <&audma0 0x05>, <&audma1 0x06>; +- dma-names = "rx", "tx"; +- }; +- ssi3: ssi-3 { +- interrupts = ; +- dmas = <&audma0 0x07>, <&audma1 0x08>; +- dma-names = "rx", "tx"; +- }; +- ssi4: ssi-4 { +- interrupts = ; +- dmas = <&audma0 0x09>, <&audma1 0x0a>; +- dma-names = "rx", "tx"; +- }; +- ssi5: ssi-5 { +- interrupts = ; +- dmas = <&audma0 0x0b>, <&audma1 0x0c>; +- dma-names = "rx", "tx"; +- }; +- ssi6: ssi-6 { +- interrupts = ; +- dmas = <&audma0 0x0d>, <&audma1 0x0e>; +- dma-names = "rx", "tx"; +- }; +- ssi7: ssi-7 { +- interrupts = ; +- dmas = <&audma0 0x0f>, <&audma1 0x10>; +- dma-names = "rx", "tx"; +- }; +- ssi8: ssi-8 { +- interrupts = ; +- dmas = <&audma0 0x11>, <&audma1 0x12>; +- dma-names = "rx", "tx"; +- }; +- ssi9: ssi-9 { +- interrupts = ; +- dmas = <&audma0 0x13>, <&audma1 0x14>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssiu { +- ssiu00: ssiu-0 { +- dmas = <&audma0 0x15>, <&audma1 0x16>; +- dma-names = "rx", "tx"; +- }; +- ssiu01: ssiu-1 { +- dmas = <&audma0 0x35>, <&audma1 0x36>; +- dma-names = "rx", "tx"; +- }; +- ssiu02: ssiu-2 { +- dmas = <&audma0 0x37>, <&audma1 0x38>; +- dma-names = "rx", "tx"; +- }; +- ssiu03: ssiu-3 { +- dmas = <&audma0 0x47>, <&audma1 0x48>; +- dma-names = "rx", "tx"; +- }; +- ssiu04: ssiu-4 { +- dmas = <&audma0 0x3F>, <&audma1 0x40>; +- dma-names = "rx", "tx"; +- }; +- ssiu05: ssiu-5 { +- dmas = <&audma0 0x43>, <&audma1 0x44>; +- dma-names = "rx", "tx"; +- }; +- ssiu06: ssiu-6 { +- dmas = <&audma0 0x4F>, <&audma1 0x50>; +- dma-names = "rx", "tx"; +- }; +- ssiu07: ssiu-7 { +- dmas = <&audma0 0x53>, <&audma1 0x54>; +- dma-names = "rx", "tx"; +- }; +- ssiu10: ssiu-8 { +- dmas = <&audma0 0x49>, <&audma1 0x4a>; +- dma-names = "rx", "tx"; +- }; +- ssiu11: ssiu-9 { +- dmas = <&audma0 0x4B>, <&audma1 0x4C>; +- dma-names = "rx", "tx"; +- }; +- ssiu12: ssiu-10 { +- dmas = <&audma0 0x57>, <&audma1 0x58>; +- dma-names = "rx", "tx"; +- }; +- ssiu13: ssiu-11 { +- dmas = <&audma0 0x59>, <&audma1 0x5A>; +- dma-names = "rx", "tx"; +- }; +- ssiu14: ssiu-12 { +- dmas = <&audma0 0x5F>, <&audma1 0x60>; +- dma-names = "rx", "tx"; +- }; +- ssiu15: ssiu-13 { +- dmas = <&audma0 0xC3>, <&audma1 0xC4>; +- dma-names = "rx", "tx"; +- }; +- ssiu16: ssiu-14 { +- dmas = <&audma0 0xC7>, <&audma1 0xC8>; +- dma-names = "rx", "tx"; +- }; +- ssiu17: ssiu-15 { +- dmas = <&audma0 0xCB>, <&audma1 0xCC>; +- dma-names = "rx", "tx"; +- }; +- ssiu20: ssiu-16 { +- dmas = <&audma0 0x63>, <&audma1 0x64>; +- dma-names = "rx", "tx"; +- }; +- ssiu21: ssiu-17 { +- dmas = <&audma0 0x67>, <&audma1 0x68>; +- dma-names = "rx", "tx"; +- }; +- ssiu22: ssiu-18 { +- dmas = <&audma0 0x6B>, <&audma1 0x6C>; +- dma-names = "rx", "tx"; +- }; +- ssiu23: ssiu-19 { +- dmas = <&audma0 0x6D>, <&audma1 0x6E>; +- dma-names = "rx", "tx"; +- }; +- ssiu24: ssiu-20 { +- dmas = <&audma0 0xCF>, <&audma1 0xCE>; +- dma-names = "rx", "tx"; +- }; +- ssiu25: ssiu-21 { +- dmas = <&audma0 0xEB>, <&audma1 0xEC>; +- dma-names = "rx", "tx"; +- }; +- ssiu26: ssiu-22 { +- dmas = <&audma0 0xED>, <&audma1 0xEE>; +- dma-names = "rx", "tx"; +- }; +- ssiu27: ssiu-23 { +- dmas = <&audma0 0xEF>, <&audma1 0xF0>; +- dma-names = "rx", "tx"; +- }; +- ssiu30: ssiu-24 { +- dmas = <&audma0 0x6f>, <&audma1 0x70>; +- dma-names = "rx", "tx"; +- }; +- ssiu31: ssiu-25 { +- dmas = <&audma0 0x21>, <&audma1 0x22>; +- dma-names = "rx", "tx"; +- }; +- ssiu32: ssiu-26 { +- dmas = <&audma0 0x23>, <&audma1 0x24>; +- dma-names = "rx", "tx"; +- }; +- ssiu33: ssiu-27 { +- dmas = <&audma0 0x25>, <&audma1 0x26>; +- dma-names = "rx", "tx"; +- }; +- ssiu34: ssiu-28 { +- dmas = <&audma0 0x27>, <&audma1 0x28>; +- dma-names = "rx", "tx"; +- }; +- ssiu35: ssiu-29 { +- dmas = <&audma0 0x29>, <&audma1 0x2A>; +- dma-names = "rx", "tx"; +- }; +- ssiu36: ssiu-30 { +- dmas = <&audma0 0x2B>, <&audma1 0x2C>; +- dma-names = "rx", "tx"; +- }; +- ssiu37: ssiu-31 { +- dmas = <&audma0 0x2D>, <&audma1 0x2E>; +- dma-names = "rx", "tx"; +- }; +- ssiu40: ssiu-32 { +- dmas = <&audma0 0x71>, <&audma1 0x72>; +- dma-names = "rx", "tx"; +- }; +- ssiu41: ssiu-33 { +- dmas = <&audma0 0x17>, <&audma1 0x18>; +- dma-names = "rx", "tx"; +- }; +- ssiu42: ssiu-34 { +- dmas = <&audma0 0x19>, <&audma1 0x1A>; +- dma-names = "rx", "tx"; +- }; +- ssiu43: ssiu-35 { +- dmas = <&audma0 0x1B>, <&audma1 0x1C>; +- dma-names = "rx", "tx"; +- }; +- ssiu44: ssiu-36 { +- dmas = <&audma0 0x1D>, <&audma1 0x1E>; +- dma-names = "rx", "tx"; +- }; +- ssiu45: ssiu-37 { +- dmas = <&audma0 0x1F>, <&audma1 0x20>; +- dma-names = "rx", "tx"; +- }; +- ssiu46: ssiu-38 { +- dmas = <&audma0 0x31>, <&audma1 0x32>; +- dma-names = "rx", "tx"; +- }; +- ssiu47: ssiu-39 { +- dmas = <&audma0 0x33>, <&audma1 0x34>; +- dma-names = "rx", "tx"; +- }; +- ssiu50: ssiu-40 { +- dmas = <&audma0 0x73>, <&audma1 0x74>; +- dma-names = "rx", "tx"; +- }; +- ssiu60: ssiu-41 { +- dmas = <&audma0 0x75>, <&audma1 0x76>; +- dma-names = "rx", "tx"; +- }; +- ssiu70: ssiu-42 { +- dmas = <&audma0 0x79>, <&audma1 0x7a>; +- dma-names = "rx", "tx"; +- }; +- ssiu80: ssiu-43 { +- dmas = <&audma0 0x7b>, <&audma1 0x7c>; +- dma-names = "rx", "tx"; +- }; +- ssiu90: ssiu-44 { +- dmas = <&audma0 0x7d>, <&audma1 0x7e>; +- dma-names = "rx", "tx"; +- }; +- ssiu91: ssiu-45 { +- dmas = <&audma0 0x7F>, <&audma1 0x80>; +- dma-names = "rx", "tx"; +- }; +- ssiu92: ssiu-46 { +- dmas = <&audma0 0x81>, <&audma1 0x82>; +- dma-names = "rx", "tx"; +- }; +- ssiu93: ssiu-47 { +- dmas = <&audma0 0x83>, <&audma1 0x84>; +- dma-names = "rx", "tx"; +- }; +- ssiu94: ssiu-48 { +- dmas = <&audma0 0xA3>, <&audma1 0xA4>; +- dma-names = "rx", "tx"; +- }; +- ssiu95: ssiu-49 { +- dmas = <&audma0 0xA5>, <&audma1 0xA6>; +- dma-names = "rx", "tx"; +- }; +- ssiu96: ssiu-50 { +- dmas = <&audma0 0xA7>, <&audma1 0xA8>; +- dma-names = "rx", "tx"; +- }; +- ssiu97: ssiu-51 { +- dmas = <&audma0 0xA9>, <&audma1 0xAA>; +- dma-names = "rx", "tx"; +- }; +- }; +- }; +- +- audma0: dma-controller@ec700000 { +- compatible = "renesas,dmac-r8a77961", +- "renesas,rcar-dmac"; +- reg = <0 0xec700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 502>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 502>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, +- <&ipmmu_mp 2>, <&ipmmu_mp 3>, +- <&ipmmu_mp 4>, <&ipmmu_mp 5>, +- <&ipmmu_mp 6>, <&ipmmu_mp 7>, +- <&ipmmu_mp 8>, <&ipmmu_mp 9>, +- <&ipmmu_mp 10>, <&ipmmu_mp 11>, +- <&ipmmu_mp 12>, <&ipmmu_mp 13>, +- <&ipmmu_mp 14>, <&ipmmu_mp 15>; +- }; +- +- audma1: dma-controller@ec720000 { +- compatible = "renesas,dmac-r8a77961", +- "renesas,rcar-dmac"; +- reg = <0 0xec720000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 501>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 501>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, +- <&ipmmu_mp 18>, <&ipmmu_mp 19>, +- <&ipmmu_mp 20>, <&ipmmu_mp 21>, +- <&ipmmu_mp 22>, <&ipmmu_mp 23>, +- <&ipmmu_mp 24>, <&ipmmu_mp 25>, +- <&ipmmu_mp 26>, <&ipmmu_mp 27>, +- <&ipmmu_mp 28>, <&ipmmu_mp 29>, +- <&ipmmu_mp 30>, <&ipmmu_mp 31>; +- }; +- +- xhci0: usb@ee000000 { +- compatible = "renesas,xhci-r8a77961", +- "renesas,rcar-gen3-xhci"; +- reg = <0 0xee000000 0 0xc00>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- status = "disabled"; +- }; +- +- usb3_peri0: usb@ee020000 { +- compatible = "renesas,r8a77961-usb3-peri", +- "renesas,rcar-gen3-usb3-peri"; +- reg = <0 0xee020000 0 0x400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- status = "disabled"; +- }; +- +- ohci0: usb@ee080000 { +- compatible = "generic-ohci"; +- reg = <0 0xee080000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- ohci1: usb@ee0a0000 { +- compatible = "generic-ohci"; +- reg = <0 0xee0a0000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 702>; +- phys = <&usb2_phy1 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- status = "disabled"; +- }; +- +- ehci0: usb@ee080100 { +- compatible = "generic-ehci"; +- reg = <0 0xee080100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 2>; +- phy-names = "usb"; +- companion = <&ohci0>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- ehci1: usb@ee0a0100 { +- compatible = "generic-ehci"; +- reg = <0 0xee0a0100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 702>; +- phys = <&usb2_phy1 2>; +- phy-names = "usb"; +- companion = <&ohci1>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- status = "disabled"; +- }; +- +- usb2_phy0: usb-phy@ee080200 { +- compatible = "renesas,usb2-phy-r8a77961", +- "renesas,rcar-gen3-usb2-phy"; +- reg = <0 0xee080200 0 0x700>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- usb2_phy1: usb-phy@ee0a0200 { +- compatible = "renesas,usb2-phy-r8a77961", +- "renesas,rcar-gen3-usb2-phy"; +- reg = <0 0xee0a0200 0 0x700>; +- clocks = <&cpg CPG_MOD 702>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a77961", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee100000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- iommus = <&ipmmu_ds1 32>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ee120000 { +- compatible = "renesas,sdhi-r8a77961", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee120000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 313>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 313>; +- iommus = <&ipmmu_ds1 33>; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a77961", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee140000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 312>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 312>; +- iommus = <&ipmmu_ds1 34>; +- status = "disabled"; +- }; +- +- sdhi3: mmc@ee160000 { +- compatible = "renesas,sdhi-r8a77961", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee160000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 311>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 311>; +- iommus = <&ipmmu_ds1 35>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1010000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x0 0xf1010000 0 0x1000>, +- <0x0 0xf1020000 0 0x20000>, +- <0x0 0xf1040000 0 0x20000>, +- <0x0 0xf1060000 0 0x20000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- pciec0: pcie@fe000000 { +- compatible = "renesas,pcie-r8a77961", +- "renesas,pcie-rcar-gen3"; +- reg = <0 0xfe000000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, +- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, +- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, +- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 319>; +- status = "disabled"; +- }; +- +- pciec1: pcie@ee800000 { +- compatible = "renesas,pcie-r8a77961", +- "renesas,pcie-rcar-gen3"; +- reg = <0 0xee800000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, +- <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, +- <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, +- <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 318>; +- status = "disabled"; +- }; +- +- fcpf0: fcp@fe950000 { +- compatible = "renesas,fcpf"; +- reg = <0 0xfe950000 0 0x200>; +- clocks = <&cpg CPG_MOD 615>; +- power-domains = <&sysc R8A77961_PD_A3VC>; +- resets = <&cpg 615>; +- }; +- +- fcpvb0: fcp@fe96f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe96f000 0 0x200>; +- clocks = <&cpg CPG_MOD 607>; +- power-domains = <&sysc R8A77961_PD_A3VC>; +- resets = <&cpg 607>; +- }; +- +- fcpvi0: fcp@fe9af000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe9af000 0 0x200>; +- clocks = <&cpg CPG_MOD 611>; +- power-domains = <&sysc R8A77961_PD_A3VC>; +- resets = <&cpg 611>; +- iommus = <&ipmmu_vc0 19>; +- }; +- +- fcpvd0: fcp@fea27000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea27000 0 0x200>; +- clocks = <&cpg CPG_MOD 603>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 603>; +- iommus = <&ipmmu_vi0 8>; +- }; +- +- fcpvd1: fcp@fea2f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea2f000 0 0x200>; +- clocks = <&cpg CPG_MOD 602>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 602>; +- iommus = <&ipmmu_vi0 9>; +- }; +- +- fcpvd2: fcp@fea37000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea37000 0 0x200>; +- clocks = <&cpg CPG_MOD 601>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 601>; +- iommus = <&ipmmu_vi0 10>; +- }; +- +- vspb: vsp@fe960000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe960000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 626>; +- power-domains = <&sysc R8A77961_PD_A3VC>; +- resets = <&cpg 626>; +- +- renesas,fcp = <&fcpvb0>; +- }; +- +- vspd0: vsp@fea20000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea20000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 623>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 623>; +- +- renesas,fcp = <&fcpvd0>; +- }; +- +- vspd1: vsp@fea28000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea28000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 622>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 622>; +- +- renesas,fcp = <&fcpvd1>; +- }; +- +- vspd2: vsp@fea30000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea30000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 621>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 621>; +- +- renesas,fcp = <&fcpvd2>; +- }; +- +- vspi0: vsp@fe9a0000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe9a0000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 631>; +- power-domains = <&sysc R8A77961_PD_A3VC>; +- resets = <&cpg 631>; +- +- renesas,fcp = <&fcpvi0>; +- }; +- +- csi20: csi2@fea80000 { +- compatible = "renesas,r8a77961-csi2"; +- reg = <0 0xfea80000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 714>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 714>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi20vin0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin0csi20>; +- }; +- csi20vin1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin1csi20>; +- }; +- csi20vin2: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&vin2csi20>; +- }; +- csi20vin3: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&vin3csi20>; +- }; +- csi20vin4: endpoint@4 { +- reg = <4>; +- remote-endpoint = <&vin4csi20>; +- }; +- csi20vin5: endpoint@5 { +- reg = <5>; +- remote-endpoint = <&vin5csi20>; +- }; +- csi20vin6: endpoint@6 { +- reg = <6>; +- remote-endpoint = <&vin6csi20>; +- }; +- csi20vin7: endpoint@7 { +- reg = <7>; +- remote-endpoint = <&vin7csi20>; +- }; +- }; +- }; +- }; +- +- csi40: csi2@feaa0000 { +- compatible = "renesas,r8a77961-csi2"; +- reg = <0 0xfeaa0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi40vin0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin0csi40>; +- }; +- csi40vin1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin1csi40>; +- }; +- csi40vin2: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&vin2csi40>; +- }; +- csi40vin3: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&vin3csi40>; +- }; +- csi40vin4: endpoint@4 { +- reg = <4>; +- remote-endpoint = <&vin4csi40>; +- }; +- csi40vin5: endpoint@5 { +- reg = <5>; +- remote-endpoint = <&vin5csi40>; +- }; +- csi40vin6: endpoint@6 { +- reg = <6>; +- remote-endpoint = <&vin6csi40>; +- }; +- csi40vin7: endpoint@7 { +- reg = <7>; +- remote-endpoint = <&vin7csi40>; +- }; +- }; +- +- }; +- }; +- +- hdmi0: hdmi@fead0000 { +- compatible = "renesas,r8a77961-hdmi", "renesas,rcar-gen3-hdmi"; +- reg = <0 0xfead0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A77961_CLK_HDMI>; +- clock-names = "iahb", "isfr"; +- power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; +- resets = <&cpg 729>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- dw_hdmi0_in: endpoint { +- remote-endpoint = <&du_out_hdmi0>; +- }; +- }; +- port@1 { +- reg = <1>; +- }; +- port@2 { +- /* HDMI sound */ +- reg = <2>; +- }; +- }; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a77961"; +- reg = <0 0xfeb00000 0 0x70000>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>; +- clock-names = "du.0", "du.1", "du.2"; +- resets = <&cpg 724>, <&cpg 722>; +- reset-names = "du.0", "du.2"; +- +- renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb: endpoint { +- }; +- }; +- port@1 { +- reg = <1>; +- du_out_hdmi0: endpoint { +- remote-endpoint = <&dw_hdmi0_in>; +- }; +- }; +- port@2 { +- reg = <2>; +- du_out_lvds0: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@fff00044 { +- compatible = "renesas,prr"; +- reg = <0 0xfff00044 0 4>; +- }; +- }; +- +- thermal-zones { +- sensor1_thermal: sensor1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 0>; +- sustainable-power = <3874>; +- +- trips { +- sensor1_crit: sensor1-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- sensor2_thermal: sensor2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 1>; +- sustainable-power = <3874>; +- +- trips { +- sensor2_crit: sensor2-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- sensor3_thermal: sensor3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 2>; +- sustainable-power = <3874>; +- +- cooling-maps { +- map0 { +- trip = <&target>; +- cooling-device = <&a57_0 2 4>; +- contribution = <1024>; +- }; +- map1 { +- trip = <&target>; +- cooling-device = <&a53_0 0 2>; +- contribution = <1024>; +- }; +- }; +- trips { +- target: trip-point1 { +- temperature = <100000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- +- sensor3_crit: sensor3-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; +- }; +- +- /* External USB clocks - can be overridden by the board */ +- usb3s0_clk: usb3s0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- usb_extal_clk: usb_extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77965-salvator-x.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77965-salvator-x.dts +deleted file mode 100644 +index f84c64ed4df7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77965-salvator-x.dts ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Salvator-X board with R-Car M3-N +- * +- * Copyright (C) 2018 Jacopo Mondi +- */ +- +-/dts-v1/; +-#include "r8a77965.dtsi" +-#include "salvator-x.dtsi" +- +-/ { +- model = "Renesas Salvator-X board based on r8a77965"; +- compatible = "renesas,salvator-x", "renesas,r8a77965"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x78000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 721>, +- <&versaclock5 1>, +- <&x21_clk>, +- <&versaclock5 2>; +- clock-names = "du.0", "du.1", "du.3", +- "dclkin.0", "dclkin.1", "dclkin.3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77965-salvator-xs.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77965-salvator-xs.dts +deleted file mode 100644 +index a1d3c8d531cf..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77965-salvator-xs.dts ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-N +- * +- * Copyright (C) 2017 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a77965.dtsi" +-#include "salvator-xs.dtsi" +- +-/ { +- model = "Renesas Salvator-X 2nd version board based on r8a77965"; +- compatible = "renesas,salvator-xs", "renesas,r8a77965"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x78000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 721>, +- <&versaclock6 1>, +- <&x21_clk>, +- <&versaclock6 2>; +- clock-names = "du.0", "du.1", "du.3", +- "dclkin.0", "dclkin.1", "dclkin.3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77965-ulcb-kf.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77965-ulcb-kf.dts +deleted file mode 100644 +index a601968c5727..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77965-ulcb-kf.dts ++++ /dev/null +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the M3NULCB Kingfisher board with R-Car M3-N +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- * Copyright (C) 2018 Cogent Embedded, Inc. +- */ +- +-#include "r8a77965-ulcb.dts" +-#include "ulcb-kf.dtsi" +- +-/ { +- model = "Renesas M3NULCB Kingfisher board based on r8a77965"; +- compatible = "shimafuji,kingfisher", "renesas,m3nulcb", +- "renesas,r8a77965"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77965-ulcb.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77965-ulcb.dts +deleted file mode 100644 +index 71704b67a20e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77965-ulcb.dts ++++ /dev/null +@@ -1,33 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board with R-Car M3-N +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- * Copyright (C) 2018 Cogent Embedded, Inc. +- */ +- +-/dts-v1/; +-#include "r8a77965.dtsi" +-#include "ulcb.dtsi" +- +-/ { +- model = "Renesas M3NULCB board based on r8a77965"; +- compatible = "renesas,m3nulcb", "renesas,r8a77965"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x78000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 721>, +- <&versaclock5 1>, +- <&versaclock5 3>, +- <&versaclock5 2>; +- clock-names = "du.0", "du.1", "du.3", +- "dclkin.0", "dclkin.1", "dclkin.3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77965.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r8a77965.dtsi +deleted file mode 100644 +index f9679a4dd85f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77965.dtsi ++++ /dev/null +@@ -1,2868 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Car M3-N (R8A77965) SoC +- * +- * Copyright (C) 2018 Jacopo Mondi +- * +- * Based on r8a7796.dtsi +- * Copyright (C) 2016 Renesas Electronics Corp. +- */ +- +-#include +-#include +-#include +- +-#define CPG_AUDIO_CLK_I R8A77965_CLK_S0D4 +- +-#define SOC_HAS_SATA +- +-/ { +- compatible = "renesas,r8a77965"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c_dvfs; +- }; +- +- /* +- * The external audio clocks are configured as 0 Hz fixed frequency +- * clocks by default. +- * Boards that provide audio clocks should override them. +- */ +- audio_clk_a: audio_clk_a { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_b: audio_clk_b { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_c: audio_clk_c { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* External CAN clock - to be overridden by boards that provide it */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- cluster0_opp: opp_table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <830000>; +- clock-latency-ns = <300000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <830000>; +- clock-latency-ns = <300000>; +- }; +- opp-1500000000 { +- opp-hz = /bits/ 64 <1500000000>; +- opp-microvolt = <830000>; +- clock-latency-ns = <300000>; +- opp-suspend; +- }; +- opp-1600000000 { +- opp-hz = /bits/ 64 <1600000000>; +- opp-microvolt = <900000>; +- clock-latency-ns = <300000>; +- turbo-mode; +- }; +- opp-1700000000 { +- opp-hz = /bits/ 64 <1700000000>; +- opp-microvolt = <900000>; +- clock-latency-ns = <300000>; +- turbo-mode; +- }; +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <960000>; +- clock-latency-ns = <300000>; +- turbo-mode; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- a57_0: cpu@0 { +- compatible = "arm,cortex-a57"; +- reg = <0x0>; +- device_type = "cpu"; +- power-domains = <&sysc R8A77965_PD_CA57_CPU0>; +- next-level-cache = <&L2_CA57>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- #cooling-cells = <2>; +- dynamic-power-coefficient = <854>; +- clocks = <&cpg CPG_CORE R8A77965_CLK_Z>; +- operating-points-v2 = <&cluster0_opp>; +- }; +- +- a57_1: cpu@1 { +- compatible = "arm,cortex-a57"; +- reg = <0x1>; +- device_type = "cpu"; +- power-domains = <&sysc R8A77965_PD_CA57_CPU1>; +- next-level-cache = <&L2_CA57>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- clocks = <&cpg CPG_CORE R8A77965_CLK_Z>; +- operating-points-v2 = <&cluster0_opp>; +- }; +- +- L2_CA57: cache-controller-0 { +- compatible = "cache"; +- power-domains = <&sysc R8A77965_PD_CA57_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP_0: cpu-sleep-0 { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x0010000>; +- local-timer-stop; +- entry-latency-us = <400>; +- exit-latency-us = <500>; +- min-residency-us = <4000>; +- }; +- }; +- }; +- +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- extalr_clk: extalr { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- /* External PCIe clock - can be overridden by the board */ +- pcie_bus_clk: pcie_bus { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- pmu_a57 { +- compatible = "arm,cortex-a57-pmu"; +- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&a57_0>, +- <&a57_1>; +- }; +- +- psci { +- compatible = "arm,psci-1.0", "arm,psci-0.2"; +- method = "smc"; +- }; +- +- /* External SCIF clock - to be overridden by boards that provide it */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a77965-wdt", +- "renesas,rcar-gen3-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a77965", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 16>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a77965", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 29>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a77965", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 15>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a77965", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 16>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a77965", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 18>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a77965", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- gpio6: gpio@e6055400 { +- compatible = "renesas,gpio-r8a77965", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055400 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 192 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 906>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 906>; +- }; +- +- gpio7: gpio@e6055800 { +- compatible = "renesas,gpio-r8a77965", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055800 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 224 4>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 905>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 905>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a77965"; +- reg = <0 0xe6060000 0 0x50c>; +- }; +- +- cmt0: timer@e60f0000 { +- compatible = "renesas,r8a77965-cmt0", +- "renesas,rcar-gen3-cmt0"; +- reg = <0 0xe60f0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 303>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 303>; +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a77965-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 302>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 302>; +- status = "disabled"; +- }; +- +- cmt2: timer@e6140000 { +- compatible = "renesas,r8a77965-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6140000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 301>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 301>; +- status = "disabled"; +- }; +- +- cmt3: timer@e6148000 { +- compatible = "renesas,r8a77965-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6148000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 300>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 300>; +- status = "disabled"; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a77965-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>, <&extalr_clk>; +- clock-names = "extal", "extalr"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a77965-rst"; +- reg = <0 0xe6160000 0 0x0200>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a77965-sysc"; +- reg = <0 0xe6180000 0 0x0400>; +- #power-domain-cells = <1>; +- }; +- +- tsc: thermal@e6198000 { +- compatible = "renesas,r8a77965-thermal"; +- reg = <0 0xe6198000 0 0x100>, +- <0 0xe61a0000 0 0x100>, +- <0 0xe61a8000 0 0x100>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 522>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 522>; +- #thermal-sensor-cells = <1>; +- }; +- +- intc_ex: interrupt-controller@e61c0000 { +- compatible = "renesas,intc-ex-r8a77965", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- tmu0: timer@e61e0000 { +- compatible = "renesas,tmu-r8a77965", "renesas,tmu"; +- reg = <0 0xe61e0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 125>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 125>; +- status = "disabled"; +- }; +- +- tmu1: timer@e6fc0000 { +- compatible = "renesas,tmu-r8a77965", "renesas,tmu"; +- reg = <0 0xe6fc0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- status = "disabled"; +- }; +- +- tmu2: timer@e6fd0000 { +- compatible = "renesas,tmu-r8a77965", "renesas,tmu"; +- reg = <0 0xe6fd0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 123>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 123>; +- status = "disabled"; +- }; +- +- tmu3: timer@e6fe0000 { +- compatible = "renesas,tmu-r8a77965", "renesas,tmu"; +- reg = <0 0xe6fe0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 122>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 122>; +- status = "disabled"; +- }; +- +- tmu4: timer@ffc00000 { +- compatible = "renesas,tmu-r8a77965", "renesas,tmu"; +- reg = <0 0xffc00000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 121>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 121>; +- status = "disabled"; +- }; +- +- i2c0: i2c@e6500000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77965", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6500000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- dmas = <&dmac1 0x91>, <&dmac1 0x90>, +- <&dmac2 0x91>, <&dmac2 0x90>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6508000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77965", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- dmas = <&dmac1 0x93>, <&dmac1 0x92>, +- <&dmac2 0x93>, <&dmac2 0x92>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6510000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77965", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6510000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- dmas = <&dmac1 0x95>, <&dmac1 0x94>, +- <&dmac2 0x95>, <&dmac2 0x94>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e66d0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77965", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- dmas = <&dmac0 0x97>, <&dmac0 0x96>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e66d8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77965", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 927>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 927>; +- dmas = <&dmac0 0x99>, <&dmac0 0x98>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c5: i2c@e66e0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77965", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 919>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 919>; +- dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c6: i2c@e66e8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77965", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 918>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 918>; +- dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c_dvfs: i2c@e60b0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a77965", +- "renesas,rcar-gen3-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe60b0000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 926>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 926>; +- dmas = <&dmac0 0x11>, <&dmac0 0x10>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- hscif0: serial@e6540000 { +- compatible = "renesas,hscif-r8a77965", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6540000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 520>, +- <&cpg CPG_CORE R8A77965_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x31>, <&dmac1 0x30>, +- <&dmac2 0x31>, <&dmac2 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 520>; +- status = "disabled"; +- }; +- +- hscif1: serial@e6550000 { +- compatible = "renesas,hscif-r8a77965", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6550000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 519>, +- <&cpg CPG_CORE R8A77965_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x33>, <&dmac1 0x32>, +- <&dmac2 0x33>, <&dmac2 0x32>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 519>; +- status = "disabled"; +- }; +- +- hscif2: serial@e6560000 { +- compatible = "renesas,hscif-r8a77965", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6560000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 518>, +- <&cpg CPG_CORE R8A77965_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x35>, <&dmac1 0x34>, +- <&dmac2 0x35>, <&dmac2 0x34>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 518>; +- status = "disabled"; +- }; +- +- hscif3: serial@e66a0000 { +- compatible = "renesas,hscif-r8a77965", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66a0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 517>, +- <&cpg CPG_CORE R8A77965_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x37>, <&dmac0 0x36>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 517>; +- status = "disabled"; +- }; +- +- hscif4: serial@e66b0000 { +- compatible = "renesas,hscif-r8a77965", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66b0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 516>, +- <&cpg CPG_CORE R8A77965_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x39>, <&dmac0 0x38>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 516>; +- status = "disabled"; +- }; +- +- hsusb: usb@e6590000 { +- compatible = "renesas,usbhs-r8a77965", +- "renesas,rcar-gen3-usbhs"; +- reg = <0 0xe6590000 0 0x200>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; +- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, +- <&usb_dmac1 0>, <&usb_dmac1 1>; +- dma-names = "ch0", "ch1", "ch2", "ch3"; +- renesas,buswait = <11>; +- phys = <&usb2_phy0 3>; +- phy-names = "usb"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 704>, <&cpg 703>; +- status = "disabled"; +- }; +- +- usb_dmac0: dma-controller@e65a0000 { +- compatible = "renesas,r8a77965-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65a0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 330>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 330>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac1: dma-controller@e65b0000 { +- compatible = "renesas,r8a77965-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65b0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 331>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 331>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb3_phy0: usb-phy@e65ee000 { +- compatible = "renesas,r8a77965-usb3-phy", +- "renesas,rcar-gen3-usb3-phy"; +- reg = <0 0xe65ee000 0 0x90>; +- clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, +- <&usb_extal_clk>; +- clock-names = "usb3-if", "usb3s_clk", "usb_extal"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- arm_cc630p: crypto@e6601000 { +- compatible = "arm,cryptocell-630p-ree"; +- interrupts = ; +- reg = <0x0 0xe6601000 0 0x1000>; +- clocks = <&cpg CPG_MOD 229>; +- resets = <&cpg 229>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a77965", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, +- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, +- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, +- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, +- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, +- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, +- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, +- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; +- }; +- +- dmac1: dma-controller@e7300000 { +- compatible = "renesas,dmac-r8a77965", +- "renesas,rcar-dmac"; +- reg = <0 0xe7300000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, +- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, +- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, +- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, +- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, +- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, +- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, +- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; +- }; +- +- dmac2: dma-controller@e7310000 { +- compatible = "renesas,dmac-r8a77965", +- "renesas,rcar-dmac"; +- reg = <0 0xe7310000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 217>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 217>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, +- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, +- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, +- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, +- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, +- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, +- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, +- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; +- }; +- +- ipmmu_ds0: iommu@e6740000 { +- compatible = "renesas,ipmmu-r8a77965"; +- reg = <0 0xe6740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 0>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_ds1: iommu@e7740000 { +- compatible = "renesas,ipmmu-r8a77965"; +- reg = <0 0xe7740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 1>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_hc: iommu@e6570000 { +- compatible = "renesas,ipmmu-r8a77965"; +- reg = <0 0xe6570000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 2>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mm: iommu@e67b0000 { +- compatible = "renesas,ipmmu-r8a77965"; +- reg = <0 0xe67b0000 0 0x1000>; +- interrupts = , +- ; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mp: iommu@ec670000 { +- compatible = "renesas,ipmmu-r8a77965"; +- reg = <0 0xec670000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 4>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_pv0: iommu@fd800000 { +- compatible = "renesas,ipmmu-r8a77965"; +- reg = <0 0xfd800000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 6>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_rt: iommu@ffc80000 { +- compatible = "renesas,ipmmu-r8a77965"; +- reg = <0 0xffc80000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 10>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vc0: iommu@fe6b0000 { +- compatible = "renesas,ipmmu-r8a77965"; +- reg = <0 0xfe6b0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 12>; +- power-domains = <&sysc R8A77965_PD_A3VC>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vi0: iommu@febd0000 { +- compatible = "renesas,ipmmu-r8a77965"; +- reg = <0 0xfebd0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 14>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vp0: iommu@fe990000 { +- compatible = "renesas,ipmmu-r8a77965"; +- reg = <0 0xfe990000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 16>; +- power-domains = <&sysc R8A77965_PD_A3VP>; +- #iommu-cells = <1>; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a77965", +- "renesas,etheravb-rcar-gen3"; +- reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15", +- "ch16", "ch17", "ch18", "ch19", +- "ch20", "ch21", "ch22", "ch23", +- "ch24"; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- phy-mode = "rgmii"; +- rx-internal-delay-ps = <0>; +- tx-internal-delay-ps = <0>; +- iommus = <&ipmmu_ds0 16>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- can0: can@e6c30000 { +- compatible = "renesas,can-r8a77965", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c30000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>, +- <&cpg CPG_CORE R8A77965_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- status = "disabled"; +- }; +- +- can1: can@e6c38000 { +- compatible = "renesas,can-r8a77965", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c38000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>, +- <&cpg CPG_CORE R8A77965_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- status = "disabled"; +- }; +- +- canfd: can@e66c0000 { +- compatible = "renesas,r8a77965-canfd", +- "renesas,rcar-gen3-canfd"; +- reg = <0 0xe66c0000 0 0x8000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 914>, +- <&cpg CPG_CORE R8A77965_CLK_CANFD>, +- <&can_clk>; +- clock-names = "fck", "canfd", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 914>; +- status = "disabled"; +- +- channel0 { +- status = "disabled"; +- }; +- +- channel1 { +- status = "disabled"; +- }; +- }; +- +- pwm0: pwm@e6e30000 { +- compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; +- reg = <0 0xe6e30000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm1: pwm@e6e31000 { +- compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; +- reg = <0 0xe6e31000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm2: pwm@e6e32000 { +- compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; +- reg = <0 0xe6e32000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm3: pwm@e6e33000 { +- compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; +- reg = <0 0xe6e33000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm4: pwm@e6e34000 { +- compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; +- reg = <0 0xe6e34000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm5: pwm@e6e35000 { +- compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; +- reg = <0 0xe6e35000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- pwm6: pwm@e6e36000 { +- compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; +- reg = <0 0xe6e36000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- resets = <&cpg 523>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a77965", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e60000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>, +- <&cpg CPG_CORE R8A77965_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x51>, <&dmac1 0x50>, +- <&dmac2 0x51>, <&dmac2 0x50>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a77965", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e68000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>, +- <&cpg CPG_CORE R8A77965_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x53>, <&dmac1 0x52>, +- <&dmac2 0x53>, <&dmac2 0x52>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e88000 { +- compatible = "renesas,scif-r8a77965", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e88000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 310>, +- <&cpg CPG_CORE R8A77965_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x13>, <&dmac1 0x12>, +- <&dmac2 0x13>, <&dmac2 0x12>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 310>; +- status = "disabled"; +- }; +- +- scif3: serial@e6c50000 { +- compatible = "renesas,scif-r8a77965", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c50000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>, +- <&cpg CPG_CORE R8A77965_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x57>, <&dmac0 0x56>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scif4: serial@e6c40000 { +- compatible = "renesas,scif-r8a77965", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c40000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>, +- <&cpg CPG_CORE R8A77965_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x59>, <&dmac0 0x58>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- scif5: serial@e6f30000 { +- compatible = "renesas,scif-r8a77965", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6f30000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 202>, +- <&cpg CPG_CORE R8A77965_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, +- <&dmac2 0x5b>, <&dmac2 0x5a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 202>; +- status = "disabled"; +- }; +- +- tpu: pwm@e6e80000 { +- compatible = "renesas,tpu-r8a77965", "renesas,tpu"; +- reg = <0 0xe6e80000 0 0x148>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 304>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 304>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e90000 { +- compatible = "renesas,msiof-r8a77965", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6e90000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 211>; +- dmas = <&dmac1 0x41>, <&dmac1 0x40>, +- <&dmac2 0x41>, <&dmac2 0x40>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 211>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6ea0000 { +- compatible = "renesas,msiof-r8a77965", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6ea0000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 210>; +- dmas = <&dmac1 0x43>, <&dmac1 0x42>, +- <&dmac2 0x43>, <&dmac2 0x42>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 210>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6c00000 { +- compatible = "renesas,msiof-r8a77965", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c00000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 209>; +- dmas = <&dmac0 0x45>, <&dmac0 0x44>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 209>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof3: spi@e6c10000 { +- compatible = "renesas,msiof-r8a77965", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c10000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 208>; +- dmas = <&dmac0 0x47>, <&dmac0 0x46>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 208>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a77965"; +- reg = <0 0xe6ef0000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 811>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 811>; +- renesas,id = <0>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin0csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin0>; +- }; +- vin0csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin0>; +- }; +- }; +- }; +- }; +- +- vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a77965"; +- reg = <0 0xe6ef1000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 810>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 810>; +- renesas,id = <1>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin1csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin1>; +- }; +- vin1csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin1>; +- }; +- }; +- }; +- }; +- +- vin2: video@e6ef2000 { +- compatible = "renesas,vin-r8a77965"; +- reg = <0 0xe6ef2000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 809>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 809>; +- renesas,id = <2>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin2csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin2>; +- }; +- vin2csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin2>; +- }; +- }; +- }; +- }; +- +- vin3: video@e6ef3000 { +- compatible = "renesas,vin-r8a77965"; +- reg = <0 0xe6ef3000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 808>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 808>; +- renesas,id = <3>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin3csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin3>; +- }; +- vin3csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin3>; +- }; +- }; +- }; +- }; +- +- vin4: video@e6ef4000 { +- compatible = "renesas,vin-r8a77965"; +- reg = <0 0xe6ef4000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 807>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 807>; +- renesas,id = <4>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin4csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin4>; +- }; +- vin4csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin4>; +- }; +- }; +- }; +- }; +- +- vin5: video@e6ef5000 { +- compatible = "renesas,vin-r8a77965"; +- reg = <0 0xe6ef5000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 806>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 806>; +- renesas,id = <5>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin5csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin5>; +- }; +- vin5csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin5>; +- }; +- }; +- }; +- }; +- +- vin6: video@e6ef6000 { +- compatible = "renesas,vin-r8a77965"; +- reg = <0 0xe6ef6000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 805>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 805>; +- renesas,id = <6>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin6csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin6>; +- }; +- vin6csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin6>; +- }; +- }; +- }; +- }; +- +- vin7: video@e6ef7000 { +- compatible = "renesas,vin-r8a77965"; +- reg = <0 0xe6ef7000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 804>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 804>; +- renesas,id = <7>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin7csi20: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&csi20vin7>; +- }; +- vin7csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin7>; +- }; +- }; +- }; +- }; +- +- drif00: rif@e6f40000 { +- compatible = "renesas,r8a77965-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f40000 0 0x84>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 515>; +- clock-names = "fck"; +- dmas = <&dmac1 0x20>, <&dmac2 0x20>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 515>; +- renesas,bonding = <&drif01>; +- status = "disabled"; +- }; +- +- drif01: rif@e6f50000 { +- compatible = "renesas,r8a77965-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f50000 0 0x84>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 514>; +- clock-names = "fck"; +- dmas = <&dmac1 0x22>, <&dmac2 0x22>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 514>; +- renesas,bonding = <&drif00>; +- status = "disabled"; +- }; +- +- drif10: rif@e6f60000 { +- compatible = "renesas,r8a77965-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f60000 0 0x84>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 513>; +- clock-names = "fck"; +- dmas = <&dmac1 0x24>, <&dmac2 0x24>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 513>; +- renesas,bonding = <&drif11>; +- status = "disabled"; +- }; +- +- drif11: rif@e6f70000 { +- compatible = "renesas,r8a77965-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f70000 0 0x84>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 512>; +- clock-names = "fck"; +- dmas = <&dmac1 0x26>, <&dmac2 0x26>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 512>; +- renesas,bonding = <&drif10>; +- status = "disabled"; +- }; +- +- drif20: rif@e6f80000 { +- compatible = "renesas,r8a77965-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f80000 0 0x84>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 511>; +- clock-names = "fck"; +- dmas = <&dmac1 0x28>, <&dmac2 0x28>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 511>; +- renesas,bonding = <&drif21>; +- status = "disabled"; +- }; +- +- drif21: rif@e6f90000 { +- compatible = "renesas,r8a77965-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f90000 0 0x84>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 510>; +- clock-names = "fck"; +- dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 510>; +- renesas,bonding = <&drif20>; +- status = "disabled"; +- }; +- +- drif30: rif@e6fa0000 { +- compatible = "renesas,r8a77965-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6fa0000 0 0x84>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 509>; +- clock-names = "fck"; +- dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 509>; +- renesas,bonding = <&drif31>; +- status = "disabled"; +- }; +- +- drif31: rif@e6fb0000 { +- compatible = "renesas,r8a77965-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6fb0000 0 0x84>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 508>; +- clock-names = "fck"; +- dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 508>; +- renesas,bonding = <&drif30>; +- status = "disabled"; +- }; +- +- rcar_sound: sound@ec500000 { +- /* +- * #sound-dai-cells is required +- * +- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; +- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; +- */ +- /* +- * #clock-cells is required for audio_clkout0/1/2/3 +- * +- * clkout : #clock-cells = <0>; <&rcar_sound>; +- * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; +- */ +- compatible = "renesas,rcar_sound-r8a77965", "renesas,rcar_sound-gen3"; +- reg = <0 0xec500000 0 0x1000>, /* SCU */ +- <0 0xec5a0000 0 0x100>, /* ADG */ +- <0 0xec540000 0 0x1000>, /* SSIU */ +- <0 0xec541000 0 0x280>, /* SSI */ +- <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ +- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; +- +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&audio_clk_b>, +- <&audio_clk_c>, +- <&cpg CPG_CORE R8A77965_CLK_S0D4>; +- clock-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0", +- "src.9", "src.8", "src.7", "src.6", +- "src.5", "src.4", "src.3", "src.2", +- "src.1", "src.0", +- "mix.1", "mix.0", +- "ctu.1", "ctu.0", +- "dvc.0", "dvc.1", +- "clk_a", "clk_b", "clk_c", "clk_i"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 1005>, +- <&cpg 1006>, <&cpg 1007>, +- <&cpg 1008>, <&cpg 1009>, +- <&cpg 1010>, <&cpg 1011>, +- <&cpg 1012>, <&cpg 1013>, +- <&cpg 1014>, <&cpg 1015>; +- reset-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0"; +- status = "disabled"; +- +- rcar_sound,dvc { +- dvc0: dvc-0 { +- dmas = <&audma1 0xbc>; +- dma-names = "tx"; +- }; +- dvc1: dvc-1 { +- dmas = <&audma1 0xbe>; +- dma-names = "tx"; +- }; +- }; +- +- rcar_sound,mix { +- mix0: mix-0 { }; +- mix1: mix-1 { }; +- }; +- +- rcar_sound,ctu { +- ctu00: ctu-0 { }; +- ctu01: ctu-1 { }; +- ctu02: ctu-2 { }; +- ctu03: ctu-3 { }; +- ctu10: ctu-4 { }; +- ctu11: ctu-5 { }; +- ctu12: ctu-6 { }; +- ctu13: ctu-7 { }; +- }; +- +- rcar_sound,src { +- src0: src-0 { +- interrupts = ; +- dmas = <&audma0 0x85>, <&audma1 0x9a>; +- dma-names = "rx", "tx"; +- }; +- src1: src-1 { +- interrupts = ; +- dmas = <&audma0 0x87>, <&audma1 0x9c>; +- dma-names = "rx", "tx"; +- }; +- src2: src-2 { +- interrupts = ; +- dmas = <&audma0 0x89>, <&audma1 0x9e>; +- dma-names = "rx", "tx"; +- }; +- src3: src-3 { +- interrupts = ; +- dmas = <&audma0 0x8b>, <&audma1 0xa0>; +- dma-names = "rx", "tx"; +- }; +- src4: src-4 { +- interrupts = ; +- dmas = <&audma0 0x8d>, <&audma1 0xb0>; +- dma-names = "rx", "tx"; +- }; +- src5: src-5 { +- interrupts = ; +- dmas = <&audma0 0x8f>, <&audma1 0xb2>; +- dma-names = "rx", "tx"; +- }; +- src6: src-6 { +- interrupts = ; +- dmas = <&audma0 0x91>, <&audma1 0xb4>; +- dma-names = "rx", "tx"; +- }; +- src7: src-7 { +- interrupts = ; +- dmas = <&audma0 0x93>, <&audma1 0xb6>; +- dma-names = "rx", "tx"; +- }; +- src8: src-8 { +- interrupts = ; +- dmas = <&audma0 0x95>, <&audma1 0xb8>; +- dma-names = "rx", "tx"; +- }; +- src9: src-9 { +- interrupts = ; +- dmas = <&audma0 0x97>, <&audma1 0xba>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssiu { +- ssiu00: ssiu-0 { +- dmas = <&audma0 0x15>, <&audma1 0x16>; +- dma-names = "rx", "tx"; +- }; +- ssiu01: ssiu-1 { +- dmas = <&audma0 0x35>, <&audma1 0x36>; +- dma-names = "rx", "tx"; +- }; +- ssiu02: ssiu-2 { +- dmas = <&audma0 0x37>, <&audma1 0x38>; +- dma-names = "rx", "tx"; +- }; +- ssiu03: ssiu-3 { +- dmas = <&audma0 0x47>, <&audma1 0x48>; +- dma-names = "rx", "tx"; +- }; +- ssiu04: ssiu-4 { +- dmas = <&audma0 0x3F>, <&audma1 0x40>; +- dma-names = "rx", "tx"; +- }; +- ssiu05: ssiu-5 { +- dmas = <&audma0 0x43>, <&audma1 0x44>; +- dma-names = "rx", "tx"; +- }; +- ssiu06: ssiu-6 { +- dmas = <&audma0 0x4F>, <&audma1 0x50>; +- dma-names = "rx", "tx"; +- }; +- ssiu07: ssiu-7 { +- dmas = <&audma0 0x53>, <&audma1 0x54>; +- dma-names = "rx", "tx"; +- }; +- ssiu10: ssiu-8 { +- dmas = <&audma0 0x49>, <&audma1 0x4a>; +- dma-names = "rx", "tx"; +- }; +- ssiu11: ssiu-9 { +- dmas = <&audma0 0x4B>, <&audma1 0x4C>; +- dma-names = "rx", "tx"; +- }; +- ssiu12: ssiu-10 { +- dmas = <&audma0 0x57>, <&audma1 0x58>; +- dma-names = "rx", "tx"; +- }; +- ssiu13: ssiu-11 { +- dmas = <&audma0 0x59>, <&audma1 0x5A>; +- dma-names = "rx", "tx"; +- }; +- ssiu14: ssiu-12 { +- dmas = <&audma0 0x5F>, <&audma1 0x60>; +- dma-names = "rx", "tx"; +- }; +- ssiu15: ssiu-13 { +- dmas = <&audma0 0xC3>, <&audma1 0xC4>; +- dma-names = "rx", "tx"; +- }; +- ssiu16: ssiu-14 { +- dmas = <&audma0 0xC7>, <&audma1 0xC8>; +- dma-names = "rx", "tx"; +- }; +- ssiu17: ssiu-15 { +- dmas = <&audma0 0xCB>, <&audma1 0xCC>; +- dma-names = "rx", "tx"; +- }; +- ssiu20: ssiu-16 { +- dmas = <&audma0 0x63>, <&audma1 0x64>; +- dma-names = "rx", "tx"; +- }; +- ssiu21: ssiu-17 { +- dmas = <&audma0 0x67>, <&audma1 0x68>; +- dma-names = "rx", "tx"; +- }; +- ssiu22: ssiu-18 { +- dmas = <&audma0 0x6B>, <&audma1 0x6C>; +- dma-names = "rx", "tx"; +- }; +- ssiu23: ssiu-19 { +- dmas = <&audma0 0x6D>, <&audma1 0x6E>; +- dma-names = "rx", "tx"; +- }; +- ssiu24: ssiu-20 { +- dmas = <&audma0 0xCF>, <&audma1 0xCE>; +- dma-names = "rx", "tx"; +- }; +- ssiu25: ssiu-21 { +- dmas = <&audma0 0xEB>, <&audma1 0xEC>; +- dma-names = "rx", "tx"; +- }; +- ssiu26: ssiu-22 { +- dmas = <&audma0 0xED>, <&audma1 0xEE>; +- dma-names = "rx", "tx"; +- }; +- ssiu27: ssiu-23 { +- dmas = <&audma0 0xEF>, <&audma1 0xF0>; +- dma-names = "rx", "tx"; +- }; +- ssiu30: ssiu-24 { +- dmas = <&audma0 0x6f>, <&audma1 0x70>; +- dma-names = "rx", "tx"; +- }; +- ssiu31: ssiu-25 { +- dmas = <&audma0 0x21>, <&audma1 0x22>; +- dma-names = "rx", "tx"; +- }; +- ssiu32: ssiu-26 { +- dmas = <&audma0 0x23>, <&audma1 0x24>; +- dma-names = "rx", "tx"; +- }; +- ssiu33: ssiu-27 { +- dmas = <&audma0 0x25>, <&audma1 0x26>; +- dma-names = "rx", "tx"; +- }; +- ssiu34: ssiu-28 { +- dmas = <&audma0 0x27>, <&audma1 0x28>; +- dma-names = "rx", "tx"; +- }; +- ssiu35: ssiu-29 { +- dmas = <&audma0 0x29>, <&audma1 0x2A>; +- dma-names = "rx", "tx"; +- }; +- ssiu36: ssiu-30 { +- dmas = <&audma0 0x2B>, <&audma1 0x2C>; +- dma-names = "rx", "tx"; +- }; +- ssiu37: ssiu-31 { +- dmas = <&audma0 0x2D>, <&audma1 0x2E>; +- dma-names = "rx", "tx"; +- }; +- ssiu40: ssiu-32 { +- dmas = <&audma0 0x71>, <&audma1 0x72>; +- dma-names = "rx", "tx"; +- }; +- ssiu41: ssiu-33 { +- dmas = <&audma0 0x17>, <&audma1 0x18>; +- dma-names = "rx", "tx"; +- }; +- ssiu42: ssiu-34 { +- dmas = <&audma0 0x19>, <&audma1 0x1A>; +- dma-names = "rx", "tx"; +- }; +- ssiu43: ssiu-35 { +- dmas = <&audma0 0x1B>, <&audma1 0x1C>; +- dma-names = "rx", "tx"; +- }; +- ssiu44: ssiu-36 { +- dmas = <&audma0 0x1D>, <&audma1 0x1E>; +- dma-names = "rx", "tx"; +- }; +- ssiu45: ssiu-37 { +- dmas = <&audma0 0x1F>, <&audma1 0x20>; +- dma-names = "rx", "tx"; +- }; +- ssiu46: ssiu-38 { +- dmas = <&audma0 0x31>, <&audma1 0x32>; +- dma-names = "rx", "tx"; +- }; +- ssiu47: ssiu-39 { +- dmas = <&audma0 0x33>, <&audma1 0x34>; +- dma-names = "rx", "tx"; +- }; +- ssiu50: ssiu-40 { +- dmas = <&audma0 0x73>, <&audma1 0x74>; +- dma-names = "rx", "tx"; +- }; +- ssiu60: ssiu-41 { +- dmas = <&audma0 0x75>, <&audma1 0x76>; +- dma-names = "rx", "tx"; +- }; +- ssiu70: ssiu-42 { +- dmas = <&audma0 0x79>, <&audma1 0x7a>; +- dma-names = "rx", "tx"; +- }; +- ssiu80: ssiu-43 { +- dmas = <&audma0 0x7b>, <&audma1 0x7c>; +- dma-names = "rx", "tx"; +- }; +- ssiu90: ssiu-44 { +- dmas = <&audma0 0x7d>, <&audma1 0x7e>; +- dma-names = "rx", "tx"; +- }; +- ssiu91: ssiu-45 { +- dmas = <&audma0 0x7F>, <&audma1 0x80>; +- dma-names = "rx", "tx"; +- }; +- ssiu92: ssiu-46 { +- dmas = <&audma0 0x81>, <&audma1 0x82>; +- dma-names = "rx", "tx"; +- }; +- ssiu93: ssiu-47 { +- dmas = <&audma0 0x83>, <&audma1 0x84>; +- dma-names = "rx", "tx"; +- }; +- ssiu94: ssiu-48 { +- dmas = <&audma0 0xA3>, <&audma1 0xA4>; +- dma-names = "rx", "tx"; +- }; +- ssiu95: ssiu-49 { +- dmas = <&audma0 0xA5>, <&audma1 0xA6>; +- dma-names = "rx", "tx"; +- }; +- ssiu96: ssiu-50 { +- dmas = <&audma0 0xA7>, <&audma1 0xA8>; +- dma-names = "rx", "tx"; +- }; +- ssiu97: ssiu-51 { +- dmas = <&audma0 0xA9>, <&audma1 0xAA>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssi { +- ssi0: ssi-0 { +- interrupts = ; +- dmas = <&audma0 0x01>, <&audma1 0x02>; +- dma-names = "rx", "tx"; +- }; +- ssi1: ssi-1 { +- interrupts = ; +- dmas = <&audma0 0x03>, <&audma1 0x04>; +- dma-names = "rx", "tx"; +- }; +- ssi2: ssi-2 { +- interrupts = ; +- dmas = <&audma0 0x05>, <&audma1 0x06>; +- dma-names = "rx", "tx"; +- }; +- ssi3: ssi-3 { +- interrupts = ; +- dmas = <&audma0 0x07>, <&audma1 0x08>; +- dma-names = "rx", "tx"; +- }; +- ssi4: ssi-4 { +- interrupts = ; +- dmas = <&audma0 0x09>, <&audma1 0x0a>; +- dma-names = "rx", "tx"; +- }; +- ssi5: ssi-5 { +- interrupts = ; +- dmas = <&audma0 0x0b>, <&audma1 0x0c>; +- dma-names = "rx", "tx"; +- }; +- ssi6: ssi-6 { +- interrupts = ; +- dmas = <&audma0 0x0d>, <&audma1 0x0e>; +- dma-names = "rx", "tx"; +- }; +- ssi7: ssi-7 { +- interrupts = ; +- dmas = <&audma0 0x0f>, <&audma1 0x10>; +- dma-names = "rx", "tx"; +- }; +- ssi8: ssi-8 { +- interrupts = ; +- dmas = <&audma0 0x11>, <&audma1 0x12>; +- dma-names = "rx", "tx"; +- }; +- ssi9: ssi-9 { +- interrupts = ; +- dmas = <&audma0 0x13>, <&audma1 0x14>; +- dma-names = "rx", "tx"; +- }; +- }; +- }; +- +- audma0: dma-controller@ec700000 { +- compatible = "renesas,dmac-r8a77965", +- "renesas,rcar-dmac"; +- reg = <0 0xec700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 502>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 502>; +- #dma-cells = <1>; +- dma-channels = <16>; +- }; +- +- audma1: dma-controller@ec720000 { +- compatible = "renesas,dmac-r8a77965", +- "renesas,rcar-dmac"; +- reg = <0 0xec720000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 501>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 501>; +- #dma-cells = <1>; +- dma-channels = <16>; +- }; +- +- xhci0: usb@ee000000 { +- compatible = "renesas,xhci-r8a77965", +- "renesas,rcar-gen3-xhci"; +- reg = <0 0xee000000 0 0xc00>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- status = "disabled"; +- }; +- +- usb3_peri0: usb@ee020000 { +- compatible = "renesas,r8a77965-usb3-peri", +- "renesas,rcar-gen3-usb3-peri"; +- reg = <0 0xee020000 0 0x400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- status = "disabled"; +- }; +- +- ohci0: usb@ee080000 { +- compatible = "generic-ohci"; +- reg = <0 0xee080000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- ohci1: usb@ee0a0000 { +- compatible = "generic-ohci"; +- reg = <0 0xee0a0000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 702>; +- phys = <&usb2_phy1 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- status = "disabled"; +- }; +- +- ehci0: usb@ee080100 { +- compatible = "generic-ehci"; +- reg = <0 0xee080100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 2>; +- phy-names = "usb"; +- companion = <&ohci0>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- ehci1: usb@ee0a0100 { +- compatible = "generic-ehci"; +- reg = <0 0xee0a0100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 702>; +- phys = <&usb2_phy1 2>; +- phy-names = "usb"; +- companion = <&ohci1>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- status = "disabled"; +- }; +- +- usb2_phy0: usb-phy@ee080200 { +- compatible = "renesas,usb2-phy-r8a77965", +- "renesas,rcar-gen3-usb2-phy"; +- reg = <0 0xee080200 0 0x700>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- usb2_phy1: usb-phy@ee0a0200 { +- compatible = "renesas,usb2-phy-r8a77965", +- "renesas,rcar-gen3-usb2-phy"; +- reg = <0 0xee0a0200 0 0x700>; +- clocks = <&cpg CPG_MOD 702>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a77965", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee100000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- iommus = <&ipmmu_ds1 32>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ee120000 { +- compatible = "renesas,sdhi-r8a77965", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee120000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 313>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 313>; +- iommus = <&ipmmu_ds1 33>; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a77965", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee140000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 312>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 312>; +- iommus = <&ipmmu_ds1 34>; +- status = "disabled"; +- }; +- +- sdhi3: mmc@ee160000 { +- compatible = "renesas,sdhi-r8a77965", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee160000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 311>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 311>; +- iommus = <&ipmmu_ds1 35>; +- status = "disabled"; +- }; +- +- sata: sata@ee300000 { +- compatible = "renesas,sata-r8a77965", +- "renesas,rcar-gen3-sata"; +- reg = <0 0xee300000 0 0x200000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 815>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 815>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1010000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x0 0xf1010000 0 0x1000>, +- <0x0 0xf1020000 0 0x20000>, +- <0x0 0xf1040000 0 0x20000>, +- <0x0 0xf1060000 0 0x20000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- pciec0: pcie@fe000000 { +- compatible = "renesas,pcie-r8a77965", +- "renesas,pcie-rcar-gen3"; +- reg = <0 0xfe000000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, +- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, +- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, +- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 319>; +- status = "disabled"; +- }; +- +- pciec1: pcie@ee800000 { +- compatible = "renesas,pcie-r8a77965", +- "renesas,pcie-rcar-gen3"; +- reg = <0 0xee800000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, +- <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, +- <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, +- <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 318>; +- status = "disabled"; +- }; +- +- fdp1@fe940000 { +- compatible = "renesas,fdp1"; +- reg = <0 0xfe940000 0 0x2400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 119>; +- power-domains = <&sysc R8A77965_PD_A3VP>; +- resets = <&cpg 119>; +- renesas,fcp = <&fcpf0>; +- }; +- +- fcpf0: fcp@fe950000 { +- compatible = "renesas,fcpf"; +- reg = <0 0xfe950000 0 0x200>; +- clocks = <&cpg CPG_MOD 615>; +- power-domains = <&sysc R8A77965_PD_A3VP>; +- resets = <&cpg 615>; +- }; +- +- vspb: vsp@fe960000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe960000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 626>; +- power-domains = <&sysc R8A77965_PD_A3VP>; +- resets = <&cpg 626>; +- +- renesas,fcp = <&fcpvb0>; +- }; +- +- vspi0: vsp@fe9a0000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe9a0000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 631>; +- power-domains = <&sysc R8A77965_PD_A3VP>; +- resets = <&cpg 631>; +- +- renesas,fcp = <&fcpvi0>; +- }; +- +- vspd0: vsp@fea20000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea20000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 623>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 623>; +- +- renesas,fcp = <&fcpvd0>; +- }; +- +- vspd1: vsp@fea28000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea28000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 622>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 622>; +- +- renesas,fcp = <&fcpvd1>; +- }; +- +- fcpvb0: fcp@fe96f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe96f000 0 0x200>; +- clocks = <&cpg CPG_MOD 607>; +- power-domains = <&sysc R8A77965_PD_A3VP>; +- resets = <&cpg 607>; +- }; +- +- fcpvd0: fcp@fea27000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea27000 0 0x200>; +- clocks = <&cpg CPG_MOD 603>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 603>; +- }; +- +- fcpvd1: fcp@fea2f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea2f000 0 0x200>; +- clocks = <&cpg CPG_MOD 602>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 602>; +- }; +- +- fcpvi0: fcp@fe9af000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe9af000 0 0x200>; +- clocks = <&cpg CPG_MOD 611>; +- power-domains = <&sysc R8A77965_PD_A3VP>; +- resets = <&cpg 611>; +- }; +- +- cmm0: cmm@fea40000 { +- compatible = "renesas,r8a77965-cmm", +- "renesas,rcar-gen3-cmm"; +- reg = <0 0xfea40000 0 0x1000>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- clocks = <&cpg CPG_MOD 711>; +- resets = <&cpg 711>; +- }; +- +- cmm1: cmm@fea50000 { +- compatible = "renesas,r8a77965-cmm", +- "renesas,rcar-gen3-cmm"; +- reg = <0 0xfea50000 0 0x1000>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- clocks = <&cpg CPG_MOD 710>; +- resets = <&cpg 710>; +- }; +- +- cmm3: cmm@fea70000 { +- compatible = "renesas,r8a77965-cmm", +- "renesas,rcar-gen3-cmm"; +- reg = <0 0xfea70000 0 0x1000>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- clocks = <&cpg CPG_MOD 708>; +- resets = <&cpg 708>; +- }; +- +- csi20: csi2@fea80000 { +- compatible = "renesas,r8a77965-csi2"; +- reg = <0 0xfea80000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 714>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 714>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi20vin0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin0csi20>; +- }; +- csi20vin1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin1csi20>; +- }; +- csi20vin2: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&vin2csi20>; +- }; +- csi20vin3: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&vin3csi20>; +- }; +- csi20vin4: endpoint@4 { +- reg = <4>; +- remote-endpoint = <&vin4csi20>; +- }; +- csi20vin5: endpoint@5 { +- reg = <5>; +- remote-endpoint = <&vin5csi20>; +- }; +- csi20vin6: endpoint@6 { +- reg = <6>; +- remote-endpoint = <&vin6csi20>; +- }; +- csi20vin7: endpoint@7 { +- reg = <7>; +- remote-endpoint = <&vin7csi20>; +- }; +- }; +- }; +- }; +- +- csi40: csi2@feaa0000 { +- compatible = "renesas,r8a77965-csi2"; +- reg = <0 0xfeaa0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi40vin0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin0csi40>; +- }; +- csi40vin1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin1csi40>; +- }; +- csi40vin2: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&vin2csi40>; +- }; +- csi40vin3: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&vin3csi40>; +- }; +- csi40vin4: endpoint@4 { +- reg = <4>; +- remote-endpoint = <&vin4csi40>; +- }; +- csi40vin5: endpoint@5 { +- reg = <5>; +- remote-endpoint = <&vin5csi40>; +- }; +- csi40vin6: endpoint@6 { +- reg = <6>; +- remote-endpoint = <&vin6csi40>; +- }; +- csi40vin7: endpoint@7 { +- reg = <7>; +- remote-endpoint = <&vin7csi40>; +- }; +- }; +- }; +- }; +- +- hdmi0: hdmi@fead0000 { +- compatible = "renesas,r8a77965-hdmi", +- "renesas,rcar-gen3-hdmi"; +- reg = <0 0xfead0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 729>, +- <&cpg CPG_CORE R8A77965_CLK_HDMI>; +- clock-names = "iahb", "isfr"; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 729>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- dw_hdmi0_in: endpoint { +- remote-endpoint = <&du_out_hdmi0>; +- }; +- }; +- port@1 { +- reg = <1>; +- }; +- }; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a77965"; +- reg = <0 0xfeb00000 0 0x80000>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 721>; +- clock-names = "du.0", "du.1", "du.3"; +- resets = <&cpg 724>, <&cpg 722>; +- reset-names = "du.0", "du.3"; +- +- renesas,cmms = <&cmm0>, <&cmm1>, <&cmm3>; +- renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; +- +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb: endpoint { +- }; +- }; +- port@1 { +- reg = <1>; +- du_out_hdmi0: endpoint { +- remote-endpoint = <&dw_hdmi0_in>; +- }; +- }; +- port@2 { +- reg = <2>; +- du_out_lvds0: endpoint { +- remote-endpoint = <&lvds0_in>; +- }; +- }; +- }; +- }; +- +- lvds0: lvds@feb90000 { +- compatible = "renesas,r8a77965-lvds"; +- reg = <0 0xfeb90000 0 0x14>; +- clocks = <&cpg CPG_MOD 727>; +- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; +- resets = <&cpg 727>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds0_in: endpoint { +- remote-endpoint = <&du_out_lvds0>; +- }; +- }; +- port@1 { +- reg = <1>; +- lvds0_out: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@fff00044 { +- compatible = "renesas,prr"; +- reg = <0 0xfff00044 0 4>; +- }; +- }; +- +- thermal-zones { +- sensor1_thermal: sensor1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 0>; +- sustainable-power = <2439>; +- +- trips { +- sensor1_crit: sensor1-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- sensor2_thermal: sensor2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 1>; +- sustainable-power = <2439>; +- +- trips { +- sensor2_crit: sensor2-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- sensor3_thermal: sensor3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 2>; +- sustainable-power = <2439>; +- +- trips { +- target: trip-point1 { +- /* miliCelsius */ +- temperature = <100000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- +- sensor3_crit: sensor3-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&target>; +- cooling-device = <&a57_0 2 4>; +- contribution = <1024>; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +- }; +- +- /* External USB clocks - can be overridden by the board */ +- usb3s0_clk: usb3s0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- usb_extal_clk: usb_extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77970-eagle.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77970-eagle.dts +deleted file mode 100644 +index d24da54f312b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77970-eagle.dts ++++ /dev/null +@@ -1,282 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Eagle board with R-Car V3M +- * +- * Copyright (C) 2016-2017 Renesas Electronics Corp. +- * Copyright (C) 2017 Cogent Embedded, Inc. +- */ +- +-/dts-v1/; +-#include "r8a77970.dtsi" +- +-/ { +- model = "Renesas Eagle board based on r8a77970"; +- compatible = "renesas,eagle", "renesas,r8a77970"; +- +- aliases { +- serial0 = &scif0; +- ethernet0 = &avb; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- d3p3: regulator-fixed { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_out: endpoint { +- remote-endpoint = <&adv7511_out>; +- }; +- }; +- }; +- +- lvds-decoder { +- compatible = "thine,thc63lvd1024"; +- +- vcc-supply = <&d3p3>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- thc63lvd1024_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- thc63lvd1024_out: endpoint { +- remote-endpoint = <&adv7511_in>; +- }; +- }; +- }; +- }; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x38000000>; +- }; +- +- x1_clk: x1-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <148500000>; +- }; +-}; +- +-&avb { +- pinctrl-0 = <&avb_pins>; +- pinctrl-names = "default"; +- +- renesas,no-ether-link; +- phy-handle = <&phy0>; +- rx-internal-delay-ps = <1800>; +- tx-internal-delay-ps = <2000>; +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- rxc-skew-ps = <1500>; +- reg = <0>; +- interrupt-parent = <&gpio1>; +- interrupts = <17 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&canfd { +- pinctrl-0 = <&canfd0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- channel0 { +- status = "okay"; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, <&x1_clk>; +- clock-names = "du.0", "dclkin.0"; +- status = "okay"; +-}; +- +-&extal_clk { +- clock-frequency = <16666666>; +-}; +- +-&extalr_clk { +- clock-frequency = <32768>; +-}; +- +-&i2c0 { +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- io_expander: gpio@20 { +- compatible = "onnn,pca9654"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- hdmi@39 { +- compatible = "adi,adv7511w"; +- reg = <0x39>; +- interrupt-parent = <&gpio1>; +- interrupts = <20 IRQ_TYPE_LEVEL_LOW>; +- +- adi,input-depth = <8>; +- adi,input-colorspace = "rgb"; +- adi,input-clock = "1x"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7511_in: endpoint { +- remote-endpoint = <&thc63lvd1024_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- adv7511_out: endpoint { +- remote-endpoint = <&hdmi_con_out>; +- }; +- }; +- }; +- }; +-}; +- +-&lvds0 { +- status = "okay"; +- +- ports { +- port@1 { +- lvds0_out: endpoint { +- remote-endpoint = <&thc63lvd1024_in>; +- }; +- }; +- }; +-}; +- +-&pfc { +- avb_pins: avb0 { +- groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; +- function = "avb0"; +- }; +- +- canfd0_pins: canfd0 { +- groups = "canfd0_data_a"; +- function = "canfd0"; +- }; +- +- i2c0_pins: i2c0 { +- groups = "i2c0"; +- function = "i2c0"; +- }; +- +- qspi0_pins: qspi0 { +- groups = "qspi0_ctrl", "qspi0_data4"; +- function = "qspi0"; +- }; +- +- scif0_pins: scif0 { +- groups = "scif0_data"; +- function = "scif0"; +- }; +-}; +- +-&rpc { +- pinctrl-0 = <&qspi0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- flash@0 { +- compatible = "spansion,s25fs512s", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- spi-rx-bus-width = <4>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- bootparam@0 { +- reg = <0x00000000 0x040000>; +- read-only; +- }; +- cr7@40000 { +- reg = <0x00040000 0x080000>; +- read-only; +- }; +- cert_header_sa3@c0000 { +- reg = <0x000c0000 0x080000>; +- read-only; +- }; +- bl2@140000 { +- reg = <0x00140000 0x040000>; +- read-only; +- }; +- cert_header_sa6@180000 { +- reg = <0x00180000 0x040000>; +- read-only; +- }; +- bl31@1c0000 { +- reg = <0x001c0000 0x460000>; +- read-only; +- }; +- uboot@640000 { +- reg = <0x00640000 0x0c0000>; +- read-only; +- }; +- uboot-env@700000 { +- reg = <0x00700000 0x040000>; +- read-only; +- }; +- dtb@740000 { +- reg = <0x00740000 0x080000>; +- }; +- kernel@7c0000 { +- reg = <0x007c0000 0x1400000>; +- }; +- user@1bc0000 { +- reg = <0x01bc0000 0x2440000>; +- }; +- }; +- }; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&scif0 { +- pinctrl-0 = <&scif0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77970-v3msk.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77970-v3msk.dts +deleted file mode 100644 +index 2426e533128c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77970-v3msk.dts ++++ /dev/null +@@ -1,294 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the V3M Starter Kit board +- * +- * Copyright (C) 2017 Renesas Electronics Corp. +- * Copyright (C) 2017 Cogent Embedded, Inc. +- */ +- +-/dts-v1/; +-#include "r8a77970.dtsi" +- +-/ { +- model = "Renesas V3M Starter Kit board"; +- compatible = "renesas,v3msk", "renesas,r8a77970"; +- +- aliases { +- serial0 = &scif0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con: endpoint { +- remote-endpoint = <&adv7511_out>; +- }; +- }; +- }; +- +- lvds-decoder { +- compatible = "thine,thc63lvd1024"; +- vcc-supply = <&vcc_d3_3v>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- thc63lvd1024_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- thc63lvd1024_out: endpoint { +- remote-endpoint = <&adv7511_in>; +- }; +- }; +- }; +- }; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x78000000>; +- }; +- +- osc5_clk: osc5-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <148500000>; +- }; +- +- vcc_d1_8v: regulator-0 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_D1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcc_d3_3v: regulator-1 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_D3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcc_vddq_vin0: regulator-2 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_VDDQ_VIN0"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&avb { +- pinctrl-0 = <&avb_pins>; +- pinctrl-names = "default"; +- +- renesas,no-ether-link; +- phy-handle = <&phy0>; +- rx-internal-delay-ps = <1800>; +- tx-internal-delay-ps = <2000>; +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- rxc-skew-ps = <1500>; +- reg = <0>; +- interrupt-parent = <&gpio1>; +- interrupts = <17 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&osc5_clk>; +- clock-names = "du.0", "dclkin.0"; +- status = "okay"; +-}; +- +-&extal_clk { +- clock-frequency = <16666666>; +-}; +- +-&extalr_clk { +- clock-frequency = <32768>; +-}; +- +-&i2c0 { +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- hdmi@39{ +- compatible = "adi,adv7511w"; +- #sound-dai-cells = <0>; +- reg = <0x39>; +- interrupt-parent = <&gpio1>; +- interrupts = <20 IRQ_TYPE_LEVEL_LOW>; +- avdd-supply = <&vcc_d1_8v>; +- dvdd-supply = <&vcc_d1_8v>; +- pvdd-supply = <&vcc_d1_8v>; +- bgvdd-supply = <&vcc_d1_8v>; +- dvdd-3v-supply = <&vcc_d3_3v>; +- +- adi,input-depth = <8>; +- adi,input-colorspace = "rgb"; +- adi,input-clock = "1x"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7511_in: endpoint { +- remote-endpoint = <&thc63lvd1024_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- adv7511_out: endpoint { +- remote-endpoint = <&hdmi_con>; +- }; +- }; +- }; +- }; +-}; +- +-&lvds0 { +- status = "okay"; +- +- ports { +- port@1 { +- lvds0_out: endpoint { +- remote-endpoint = <&thc63lvd1024_in>; +- }; +- }; +- }; +-}; +- +-&mmc0 { +- pinctrl-0 = <&mmc_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <&vcc_d3_3v>; +- vqmmc-supply = <&vcc_vddq_vin0>; +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&pfc { +- avb_pins: avb0 { +- groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; +- function = "avb0"; +- }; +- +- i2c0_pins: i2c0 { +- groups = "i2c0"; +- function = "i2c0"; +- }; +- +- mmc_pins: mmc_3_3v { +- groups = "mmc_data8", "mmc_ctrl"; +- function = "mmc"; +- power-source = <3300>; +- }; +- +- qspi0_pins: qspi0 { +- groups = "qspi0_ctrl", "qspi0_data4"; +- function = "qspi0"; +- }; +- +- scif0_pins: scif0 { +- groups = "scif0_data"; +- function = "scif0"; +- }; +-}; +- +-&rpc { +- pinctrl-0 = <&qspi0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- flash@0 { +- compatible = "spansion,s25fs512s", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- spi-rx-bus-width = <4>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- bootparam@0 { +- reg = <0x00000000 0x040000>; +- read-only; +- }; +- cr7@40000 { +- reg = <0x00040000 0x080000>; +- read-only; +- }; +- cert_header_sa3@c0000 { +- reg = <0x000c0000 0x080000>; +- read-only; +- }; +- bl2@140000 { +- reg = <0x00140000 0x040000>; +- read-only; +- }; +- cert_header_sa6@180000 { +- reg = <0x00180000 0x040000>; +- read-only; +- }; +- bl31@1c0000 { +- reg = <0x001c0000 0x460000>; +- read-only; +- }; +- uboot@640000 { +- reg = <0x00640000 0x0c0000>; +- read-only; +- }; +- uboot-env@700000 { +- reg = <0x00700000 0x040000>; +- read-only; +- }; +- dtb@740000 { +- reg = <0x00740000 0x080000>; +- }; +- kernel@7c0000 { +- reg = <0x007c0000 0x1400000>; +- }; +- user@1bc0000 { +- reg = <0x01bc0000 0x2440000>; +- }; +- }; +- }; +-}; +- +-&scif0 { +- pinctrl-0 = <&scif0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77970.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r8a77970.dtsi +deleted file mode 100644 +index 517892cf6294..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77970.dtsi ++++ /dev/null +@@ -1,1231 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Car V3M (R8A77970) SoC +- * +- * Copyright (C) 2016-2017 Renesas Electronics Corp. +- * Copyright (C) 2017 Cogent Embedded, Inc. +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r8a77970"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- }; +- +- /* External CAN clock - to be overridden by boards that provide it */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- a53_0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0>; +- clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; +- power-domains = <&sysc R8A77970_PD_CA53_CPU0>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- }; +- +- a53_1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <1>; +- clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; +- power-domains = <&sysc R8A77970_PD_CA53_CPU1>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- }; +- +- L2_CA53: cache-controller { +- compatible = "cache"; +- power-domains = <&sysc R8A77970_PD_CA53_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- }; +- +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- extalr_clk: extalr { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- pmu_a53 { +- compatible = "arm,cortex-a53-pmu"; +- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&a53_0>, <&a53_1>; +- }; +- +- psci { +- compatible = "arm,psci-1.0", "arm,psci-0.2"; +- method = "smc"; +- }; +- +- /* External SCIF clock - to be overridden by boards that provide it */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a77970-wdt", +- "renesas,rcar-gen3-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a77970", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 22>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a77970", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 28>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a77970", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 17>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a77970", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 17>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a77970", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 6>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a77970", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 15>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a77970"; +- reg = <0 0xe6060000 0 0x504>; +- }; +- +- cmt0: timer@e60f0000 { +- compatible = "renesas,r8a77970-cmt0", +- "renesas,rcar-gen3-cmt0"; +- reg = <0 0xe60f0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 303>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 303>; +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a77970-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 302>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 302>; +- status = "disabled"; +- }; +- +- cmt2: timer@e6140000 { +- compatible = "renesas,r8a77970-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6140000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 301>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 301>; +- status = "disabled"; +- }; +- +- cmt3: timer@e6148000 { +- compatible = "renesas,r8a77970-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6148000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 300>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 300>; +- status = "disabled"; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a77970-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>, <&extalr_clk>; +- clock-names = "extal", "extalr"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a77970-rst"; +- reg = <0 0xe6160000 0 0x200>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a77970-sysc"; +- reg = <0 0xe6180000 0 0x440>; +- #power-domain-cells = <1>; +- }; +- +- thermal: thermal@e6190000 { +- compatible = "renesas,thermal-r8a77970"; +- reg = <0 0xe6190000 0 0x10>, +- <0 0xe6190100 0 0x120>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 522>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 522>; +- #thermal-sensor-cells = <0>; +- }; +- +- intc_ex: interrupt-controller@e61c0000 { +- compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- tmu0: timer@e61e0000 { +- compatible = "renesas,tmu-r8a77970", "renesas,tmu"; +- reg = <0 0xe61e0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 125>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 125>; +- status = "disabled"; +- }; +- +- tmu1: timer@e6fc0000 { +- compatible = "renesas,tmu-r8a77970", "renesas,tmu"; +- reg = <0 0xe6fc0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- status = "disabled"; +- }; +- +- tmu2: timer@e6fd0000 { +- compatible = "renesas,tmu-r8a77970", "renesas,tmu"; +- reg = <0 0xe6fd0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 123>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 123>; +- status = "disabled"; +- }; +- +- tmu3: timer@e6fe0000 { +- compatible = "renesas,tmu-r8a77970", "renesas,tmu"; +- reg = <0 0xe6fe0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 122>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 122>; +- status = "disabled"; +- }; +- +- tmu4: timer@ffc00000 { +- compatible = "renesas,tmu-r8a77970", "renesas,tmu"; +- reg = <0 0xffc00000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 121>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 121>; +- status = "disabled"; +- }; +- +- i2c0: i2c@e6500000 { +- compatible = "renesas,i2c-r8a77970", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6500000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- dmas = <&dmac1 0x91>, <&dmac1 0x90>, +- <&dmac2 0x91>, <&dmac2 0x90>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6508000 { +- compatible = "renesas,i2c-r8a77970", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- dmas = <&dmac1 0x93>, <&dmac1 0x92>, +- <&dmac2 0x93>, <&dmac2 0x92>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6510000 { +- compatible = "renesas,i2c-r8a77970", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6510000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- dmas = <&dmac1 0x95>, <&dmac1 0x94>, +- <&dmac2 0x95>, <&dmac2 0x94>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e66d0000 { +- compatible = "renesas,i2c-r8a77970", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- dmas = <&dmac1 0x97>, <&dmac1 0x96>, +- <&dmac2 0x97>, <&dmac2 0x96>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e66d8000 { +- compatible = "renesas,i2c-r8a77970", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 927>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 927>; +- dmas = <&dmac1 0x99>, <&dmac1 0x98>, +- <&dmac2 0x99>, <&dmac2 0x98>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- hscif0: serial@e6540000 { +- compatible = "renesas,hscif-r8a77970", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6540000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 520>, +- <&cpg CPG_CORE R8A77970_CLK_S2D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x31>, <&dmac1 0x30>, +- <&dmac2 0x31>, <&dmac2 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 520>; +- status = "disabled"; +- }; +- +- hscif1: serial@e6550000 { +- compatible = "renesas,hscif-r8a77970", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6550000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 519>, +- <&cpg CPG_CORE R8A77970_CLK_S2D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x33>, <&dmac1 0x32>, +- <&dmac2 0x33>, <&dmac2 0x32>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 519>; +- status = "disabled"; +- }; +- +- hscif2: serial@e6560000 { +- compatible = "renesas,hscif-r8a77970", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6560000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 518>, +- <&cpg CPG_CORE R8A77970_CLK_S2D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x35>, <&dmac1 0x34>, +- <&dmac2 0x35>, <&dmac2 0x34>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 518>; +- status = "disabled"; +- }; +- +- hscif3: serial@e66a0000 { +- compatible = "renesas,hscif-r8a77970", +- "renesas,rcar-gen3-hscif", "renesas,hscif"; +- reg = <0 0xe66a0000 0 96>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 517>, +- <&cpg CPG_CORE R8A77970_CLK_S2D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x37>, <&dmac1 0x36>, +- <&dmac2 0x37>, <&dmac2 0x36>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 517>; +- status = "disabled"; +- }; +- +- canfd: can@e66c0000 { +- compatible = "renesas,r8a77970-canfd", +- "renesas,rcar-gen3-canfd"; +- reg = <0 0xe66c0000 0 0x8000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 914>, +- <&cpg CPG_CORE R8A77970_CLK_CANFD>, +- <&can_clk>; +- clock-names = "fck", "canfd", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 914>; +- status = "disabled"; +- +- channel0 { +- status = "disabled"; +- }; +- +- channel1 { +- status = "disabled"; +- }; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a77970", +- "renesas,etheravb-rcar-gen3"; +- reg = <0 0xe6800000 0 0x800>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15", +- "ch16", "ch17", "ch18", "ch19", +- "ch20", "ch21", "ch22", "ch23", +- "ch24"; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- phy-mode = "rgmii"; +- rx-internal-delay-ps = <0>; +- tx-internal-delay-ps = <0>; +- iommus = <&ipmmu_rt 3>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pwm0: pwm@e6e30000 { +- compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; +- reg = <0 0xe6e30000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- status = "disabled"; +- }; +- +- pwm1: pwm@e6e31000 { +- compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; +- reg = <0 0xe6e31000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- status = "disabled"; +- }; +- +- pwm2: pwm@e6e32000 { +- compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; +- reg = <0 0xe6e32000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- status = "disabled"; +- }; +- +- pwm3: pwm@e6e33000 { +- compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; +- reg = <0 0xe6e33000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- status = "disabled"; +- }; +- +- pwm4: pwm@e6e34000 { +- compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; +- reg = <0 0xe6e34000 0 8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a77970", +- "renesas,rcar-gen3-scif", +- "renesas,scif"; +- reg = <0 0xe6e60000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>, +- <&cpg CPG_CORE R8A77970_CLK_S2D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x51>, <&dmac1 0x50>, +- <&dmac2 0x51>, <&dmac2 0x50>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a77970", +- "renesas,rcar-gen3-scif", +- "renesas,scif"; +- reg = <0 0xe6e68000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>, +- <&cpg CPG_CORE R8A77970_CLK_S2D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x53>, <&dmac1 0x52>, +- <&dmac2 0x53>, <&dmac2 0x52>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scif3: serial@e6c50000 { +- compatible = "renesas,scif-r8a77970", +- "renesas,rcar-gen3-scif", +- "renesas,scif"; +- reg = <0 0xe6c50000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>, +- <&cpg CPG_CORE R8A77970_CLK_S2D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x57>, <&dmac1 0x56>, +- <&dmac2 0x57>, <&dmac2 0x56>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scif4: serial@e6c40000 { +- compatible = "renesas,scif-r8a77970", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c40000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>, +- <&cpg CPG_CORE R8A77970_CLK_S2D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x59>, <&dmac1 0x58>, +- <&dmac2 0x59>, <&dmac2 0x58>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- tpu: pwm@e6e80000 { +- compatible = "renesas,tpu-r8a77970", "renesas,tpu"; +- reg = <0 0xe6e80000 0 0x148>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 304>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 304>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e90000 { +- compatible = "renesas,msiof-r8a77970", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6e90000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 211>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 211>; +- dmas = <&dmac1 0x41>, <&dmac1 0x40>, +- <&dmac2 0x41>, <&dmac2 0x40>; +- dma-names = "tx", "rx", "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6ea0000 { +- compatible = "renesas,msiof-r8a77970", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6ea0000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 210>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 210>; +- dmas = <&dmac1 0x43>, <&dmac1 0x42>, +- <&dmac2 0x43>, <&dmac2 0x42>; +- dma-names = "tx", "rx", "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6c00000 { +- compatible = "renesas,msiof-r8a77970", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c00000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 209>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 209>; +- dmas = <&dmac1 0x45>, <&dmac1 0x44>, +- <&dmac2 0x45>, <&dmac2 0x44>; +- dma-names = "tx", "rx", "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof3: spi@e6c10000 { +- compatible = "renesas,msiof-r8a77970", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c10000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 208>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 208>; +- dmas = <&dmac1 0x47>, <&dmac1 0x46>, +- <&dmac2 0x47>, <&dmac2 0x46>; +- dma-names = "tx", "rx", "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a77970"; +- reg = <0 0xe6ef0000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 811>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 811>; +- renesas,id = <0>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin0csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin0>; +- }; +- }; +- }; +- }; +- +- vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a77970"; +- reg = <0 0xe6ef1000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 810>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 810>; +- renesas,id = <1>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin1csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin1>; +- }; +- }; +- }; +- }; +- +- vin2: video@e6ef2000 { +- compatible = "renesas,vin-r8a77970"; +- reg = <0 0xe6ef2000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 809>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 809>; +- renesas,id = <2>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin2csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin2>; +- }; +- }; +- }; +- }; +- +- vin3: video@e6ef3000 { +- compatible = "renesas,vin-r8a77970"; +- reg = <0 0xe6ef3000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 808>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 808>; +- renesas,id = <3>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin3csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin3>; +- }; +- }; +- }; +- }; +- +- dmac1: dma-controller@e7300000 { +- compatible = "renesas,dmac-r8a77970", +- "renesas,rcar-dmac"; +- reg = <0 0xe7300000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <8>; +- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, +- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, +- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, +- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; +- }; +- +- dmac2: dma-controller@e7310000 { +- compatible = "renesas,dmac-r8a77970", +- "renesas,rcar-dmac"; +- reg = <0 0xe7310000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7"; +- clocks = <&cpg CPG_MOD 217>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 217>; +- #dma-cells = <1>; +- dma-channels = <8>; +- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, +- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, +- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, +- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; +- }; +- +- ipmmu_ds1: iommu@e7740000 { +- compatible = "renesas,ipmmu-r8a77970"; +- reg = <0 0xe7740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 0>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_ir: iommu@ff8b0000 { +- compatible = "renesas,ipmmu-r8a77970"; +- reg = <0 0xff8b0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 3>; +- power-domains = <&sysc R8A77970_PD_A3IR>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mm: iommu@e67b0000 { +- compatible = "renesas,ipmmu-r8a77970"; +- reg = <0 0xe67b0000 0 0x1000>; +- interrupts = , +- ; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_rt: iommu@ffc80000 { +- compatible = "renesas,ipmmu-r8a77970"; +- reg = <0 0xffc80000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 7>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vi0: iommu@febd0000 { +- compatible = "renesas,ipmmu-r8a77970"; +- reg = <0 0xfebd0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 9>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- mmc0: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a77970", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee140000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- max-frequency = <200000000>; +- iommus = <&ipmmu_ds1 32>; +- status = "disabled"; +- }; +- +- rpc: spi@ee200000 { +- compatible = "renesas,r8a77970-rpc-if", +- "renesas,rcar-gen3-rpc-if"; +- reg = <0 0xee200000 0 0x200>, +- <0 0x08000000 0 0x4000000>, +- <0 0xee208000 0 0x100>; +- reg-names = "regs", "dirmap", "wbuf"; +- interrupts = ; +- clocks = <&cpg CPG_MOD 917>; +- clock-names = "rpc"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 917>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1010000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0 0xf1010000 0 0x1000>, +- <0 0xf1020000 0 0x20000>, +- <0 0xf1040000 0 0x20000>, +- <0 0xf1060000 0 0x20000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- vspd0: vsp@fea20000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea20000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 623>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 623>; +- renesas,fcp = <&fcpvd0>; +- }; +- +- fcpvd0: fcp@fea27000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea27000 0 0x200>; +- clocks = <&cpg CPG_MOD 603>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 603>; +- }; +- +- csi40: csi2@feaa0000 { +- compatible = "renesas,r8a77970-csi2"; +- reg = <0 0xfeaa0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi40vin0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin0csi40>; +- }; +- csi40vin1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin1csi40>; +- }; +- csi40vin2: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&vin2csi40>; +- }; +- csi40vin3: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&vin3csi40>; +- }; +- }; +- }; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a77970"; +- reg = <0 0xfeb00000 0 0x80000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 724>; +- clock-names = "du.0"; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 724>; +- reset-names = "du.0"; +- renesas,vsps = <&vspd0 0>; +- +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb: endpoint { +- }; +- }; +- +- port@1 { +- reg = <1>; +- du_out_lvds0: endpoint { +- remote-endpoint = <&lvds0_in>; +- }; +- }; +- }; +- }; +- +- lvds0: lvds-encoder@feb90000 { +- compatible = "renesas,r8a77970-lvds"; +- reg = <0 0xfeb90000 0 0x14>; +- clocks = <&cpg CPG_MOD 727>; +- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; +- resets = <&cpg 727>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds0_in: endpoint { +- remote-endpoint = +- <&du_out_lvds0>; +- }; +- }; +- port@1 { +- reg = <1>; +- lvds0_out: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@fff00044 { +- compatible = "renesas,prr"; +- reg = <0 0xfff00044 0 4>; +- }; +- }; +- +- thermal-zones { +- cpu-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&thermal>; +- +- cooling-maps { +- }; +- +- trips { +- cpu-crit { +- temperature = <120000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77980-condor.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77980-condor.dts +deleted file mode 100644 +index edf7f2a2f958..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77980-condor.dts ++++ /dev/null +@@ -1,353 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Condor board with R-Car V3H +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- * Copyright (C) 2018 Cogent Embedded, Inc. +- */ +- +-/dts-v1/; +-#include "r8a77980.dtsi" +- +-/ { +- model = "Renesas Condor board based on r8a77980"; +- compatible = "renesas,condor", "renesas,r8a77980"; +- +- aliases { +- serial0 = &scif0; +- ethernet0 = &gether; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- d1_8v: regulator-2 { +- compatible = "regulator-fixed"; +- regulator-name = "D1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- d3_3v: regulator-0 { +- compatible = "regulator-fixed"; +- regulator-name = "D3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con: endpoint { +- remote-endpoint = <&adv7511_out>; +- }; +- }; +- }; +- +- lvds-decoder { +- compatible = "thine,thc63lvd1024"; +- vcc-supply = <&d3_3v>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- thc63lvd1024_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- thc63lvd1024_out: endpoint { +- remote-endpoint = <&adv7511_in>; +- }; +- }; +- }; +- }; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0 0x48000000 0 0x78000000>; +- }; +- +- vddq_vin01: regulator-1 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDQ_VIN01"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- x1_clk: x1-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <148500000>; +- }; +-}; +- +-&canfd { +- pinctrl-0 = <&canfd0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- channel0 { +- status = "okay"; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&x1_clk>; +- clock-names = "du.0", "dclkin.0"; +- status = "okay"; +-}; +- +-&extal_clk { +- clock-frequency = <16666666>; +-}; +- +-&extalr_clk { +- clock-frequency = <32768>; +-}; +- +-&gether { +- pinctrl-0 = <&gether_pins>; +- pinctrl-names = "default"; +- +- phy-mode = "rgmii-id"; +- phy-handle = <&phy0>; +- renesas,no-ether-link; +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- rxc-skew-ps = <1500>; +- reg = <0>; +- interrupt-parent = <&gpio4>; +- interrupts = <23 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c0 { +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- io_expander0: gpio@20 { +- compatible = "onnn,pca9654"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- io_expander1: gpio@21 { +- compatible = "onnn,pca9654"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- hdmi@39 { +- compatible = "adi,adv7511w"; +- reg = <0x39>; +- interrupt-parent = <&gpio1>; +- interrupts = <20 IRQ_TYPE_LEVEL_LOW>; +- avdd-supply = <&d1_8v>; +- dvdd-supply = <&d1_8v>; +- pvdd-supply = <&d1_8v>; +- bgvdd-supply = <&d1_8v>; +- dvdd-3v-supply = <&d3_3v>; +- +- adi,input-depth = <8>; +- adi,input-colorspace = "rgb"; +- adi,input-clock = "1x"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7511_in: endpoint { +- remote-endpoint = <&thc63lvd1024_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- adv7511_out: endpoint { +- remote-endpoint = <&hdmi_con>; +- }; +- }; +- }; +- }; +-}; +- +-&lvds0 { +- status = "okay"; +- +- ports { +- port@1 { +- lvds0_out: endpoint { +- remote-endpoint = <&thc63lvd1024_in>; +- }; +- }; +- }; +-}; +- +-&mmc0 { +- pinctrl-0 = <&mmc_pins>; +- pinctrl-1 = <&mmc_pins>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <&d3_3v>; +- vqmmc-supply = <&vddq_vin01>; +- mmc-hs200-1_8v; +- bus-width = <8>; +- no-sd; +- no-sdio; +- non-removable; +- status = "okay"; +-}; +- +-&pciec { +- status = "okay"; +-}; +- +-&pcie_bus_clk { +- clock-frequency = <100000000>; +-}; +- +-&pcie_phy { +- status = "okay"; +-}; +- +-&pfc { +- canfd0_pins: canfd0 { +- groups = "canfd0_data_a"; +- function = "canfd0"; +- }; +- +- gether_pins: gether { +- groups = "gether_mdio_a", "gether_rgmii", +- "gether_txcrefclk", "gether_txcrefclk_mega"; +- function = "gether"; +- }; +- +- i2c0_pins: i2c0 { +- groups = "i2c0"; +- function = "i2c0"; +- }; +- +- mmc_pins: mmc { +- groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; +- function = "mmc"; +- power-source = <1800>; +- }; +- +- qspi0_pins: qspi0 { +- groups = "qspi0_ctrl", "qspi0_data4"; +- function = "qspi0"; +- }; +- +- scif0_pins: scif0 { +- groups = "scif0_data"; +- function = "scif0"; +- }; +- +- scif_clk_pins: scif_clk { +- groups = "scif_clk_b"; +- function = "scif_clk"; +- }; +-}; +- +-&rpc { +- pinctrl-0 = <&qspi0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- flash@0 { +- compatible = "spansion,s25fs512s", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- spi-rx-bus-width = <4>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- bootparam@0 { +- reg = <0x00000000 0x040000>; +- read-only; +- }; +- cr7@40000 { +- reg = <0x00040000 0x080000>; +- read-only; +- }; +- cert_header_sa3@c0000 { +- reg = <0x000c0000 0x080000>; +- read-only; +- }; +- bl2@140000 { +- reg = <0x00140000 0x040000>; +- read-only; +- }; +- cert_header_sa6@180000 { +- reg = <0x00180000 0x040000>; +- read-only; +- }; +- bl31@1c0000 { +- reg = <0x001c0000 0x460000>; +- read-only; +- }; +- uboot@640000 { +- reg = <0x00640000 0x0c0000>; +- read-only; +- }; +- uboot-env@700000 { +- reg = <0x00700000 0x040000>; +- read-only; +- }; +- dtb@740000 { +- reg = <0x00740000 0x080000>; +- }; +- kernel@7c0000 { +- reg = <0x007c0000 0x1400000>; +- }; +- user@1bc0000 { +- reg = <0x01bc0000 0x2440000>; +- }; +- }; +- }; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&scif0 { +- pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scif_clk { +- clock-frequency = <14745600>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77980-v3hsk.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77980-v3hsk.dts +deleted file mode 100644 +index 7838dcee3136..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77980-v3hsk.dts ++++ /dev/null +@@ -1,282 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the V3H Starter Kit board +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- * Copyright (C) 2018 Cogent Embedded, Inc. +- */ +- +-/dts-v1/; +-#include "r8a77980.dtsi" +- +-/ { +- model = "Renesas V3H Starter Kit board"; +- compatible = "renesas,v3hsk", "renesas,r8a77980"; +- +- aliases { +- serial0 = &scif0; +- ethernet0 = &gether; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con: endpoint { +- remote-endpoint = <&adv7511_out>; +- }; +- }; +- }; +- +- lvds-decoder { +- compatible = "thine,thc63lvd1024"; +- vcc-supply = <&vcc3v3_d5>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- thc63lvd1024_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- thc63lvd1024_out: endpoint { +- remote-endpoint = <&adv7511_in>; +- }; +- }; +- }; +- }; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0 0x48000000 0 0x78000000>; +- }; +- +- osc1_clk: osc1-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <148500000>; +- }; +- +- vcc1v8_d4: regulator-0 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC1V8_D4"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- vcc3v3_d5: regulator-1 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC3V3_D5"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&osc1_clk>; +- clock-names = "du.0", "dclkin.0"; +- status = "okay"; +-}; +- +-&extal_clk { +- clock-frequency = <16666666>; +-}; +- +-&extalr_clk { +- clock-frequency = <32768>; +-}; +- +-&gether { +- pinctrl-0 = <&gether_pins>; +- pinctrl-names = "default"; +- +- phy-mode = "rgmii"; +- phy-handle = <&phy0>; +- renesas,no-ether-link; +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- interrupt-parent = <&gpio4>; +- interrupts = <23 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&i2c0 { +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- hdmi@39 { +- compatible = "adi,adv7511w"; +- #sound-dai-cells = <0>; +- reg = <0x39>; +- interrupt-parent = <&gpio1>; +- interrupts = <20 IRQ_TYPE_LEVEL_LOW>; +- avdd-supply = <&vcc1v8_d4>; +- dvdd-supply = <&vcc1v8_d4>; +- pvdd-supply = <&vcc1v8_d4>; +- bgvdd-supply = <&vcc1v8_d4>; +- dvdd-3v-supply = <&vcc3v3_d5>; +- +- adi,input-depth = <8>; +- adi,input-colorspace = "rgb"; +- adi,input-clock = "1x"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7511_in: endpoint { +- remote-endpoint = <&thc63lvd1024_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- adv7511_out: endpoint { +- remote-endpoint = <&hdmi_con>; +- }; +- }; +- }; +- }; +-}; +- +-&lvds0 { +- status = "okay"; +- +- ports { +- port@1 { +- lvds0_out: endpoint { +- remote-endpoint = <&thc63lvd1024_in>; +- }; +- }; +- }; +-}; +- +-&pfc { +- gether_pins: gether { +- groups = "gether_mdio_a", "gether_rgmii", +- "gether_txcrefclk", "gether_txcrefclk_mega"; +- function = "gether"; +- }; +- +- i2c0_pins: i2c0 { +- groups = "i2c0"; +- function = "i2c0"; +- }; +- +- qspi0_pins: qspi0 { +- groups = "qspi0_ctrl", "qspi0_data4"; +- function = "qspi0"; +- }; +- +- scif0_pins: scif0 { +- groups = "scif0_data"; +- function = "scif0"; +- }; +- +- scif_clk_pins: scif_clk { +- groups = "scif_clk_b"; +- function = "scif_clk"; +- }; +-}; +- +-&rpc { +- pinctrl-0 = <&qspi0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- flash@0 { +- compatible = "spansion,s25fs512s", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- spi-rx-bus-width = <4>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- bootparam@0 { +- reg = <0x00000000 0x040000>; +- read-only; +- }; +- cr7@40000 { +- reg = <0x00040000 0x080000>; +- read-only; +- }; +- cert_header_sa3@c0000 { +- reg = <0x000c0000 0x080000>; +- read-only; +- }; +- bl2@140000 { +- reg = <0x00140000 0x040000>; +- read-only; +- }; +- cert_header_sa6@180000 { +- reg = <0x00180000 0x040000>; +- read-only; +- }; +- bl31@1c0000 { +- reg = <0x001c0000 0x460000>; +- read-only; +- }; +- uboot@640000 { +- reg = <0x00640000 0x0c0000>; +- read-only; +- }; +- uboot-env@700000 { +- reg = <0x00700000 0x040000>; +- read-only; +- }; +- dtb@740000 { +- reg = <0x00740000 0x080000>; +- }; +- kernel@7c0000 { +- reg = <0x007c0000 0x1400000>; +- }; +- user@1bc0000 { +- reg = <0x01bc0000 0x2440000>; +- }; +- }; +- }; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&scif0 { +- pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scif_clk { +- clock-frequency = <14745600>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77980.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r8a77980.dtsi +deleted file mode 100644 +index 21fe602bd25a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77980.dtsi ++++ /dev/null +@@ -1,1633 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Car V3H (R8A77980) SoC +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- * Copyright (C) 2018 Cogent Embedded, Inc. +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r8a77980"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- }; +- +- /* External CAN clock - to be overridden by boards that provide it */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- a53_0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0>; +- clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; +- power-domains = <&sysc R8A77980_PD_CA53_CPU0>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- }; +- +- a53_1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <1>; +- clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; +- power-domains = <&sysc R8A77980_PD_CA53_CPU1>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- }; +- +- a53_2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <2>; +- clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; +- power-domains = <&sysc R8A77980_PD_CA53_CPU2>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- }; +- +- a53_3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <3>; +- clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; +- power-domains = <&sysc R8A77980_PD_CA53_CPU3>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- }; +- +- L2_CA53: cache-controller { +- compatible = "cache"; +- power-domains = <&sysc R8A77980_PD_CA53_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- }; +- +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- extalr_clk: extalr { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- /* External PCIe clock - can be overridden by the board */ +- pcie_bus_clk: pcie_bus { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- pmu_a53 { +- compatible = "arm,cortex-a53-pmu"; +- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; +- }; +- +- psci { +- compatible = "arm,psci-1.0", "arm,psci-0.2"; +- method = "smc"; +- }; +- +- /* External SCIF clock - to be overridden by boards that provide it */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a77980-wdt", +- "renesas,rcar-gen3-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a77980", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 22>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a77980", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 28>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a77980", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 30>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a77980", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 17>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a77980", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 25>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a77980", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 15>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a77980"; +- reg = <0 0xe6060000 0 0x50c>; +- }; +- +- cmt0: timer@e60f0000 { +- compatible = "renesas,r8a77980-cmt0", +- "renesas,rcar-gen3-cmt0"; +- reg = <0 0xe60f0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 303>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 303>; +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a77980-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 302>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 302>; +- status = "disabled"; +- }; +- +- cmt2: timer@e6140000 { +- compatible = "renesas,r8a77980-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6140000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 301>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 301>; +- status = "disabled"; +- }; +- +- cmt3: timer@e6148000 { +- compatible = "renesas,r8a77980-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6148000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 300>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 300>; +- status = "disabled"; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a77980-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>, <&extalr_clk>; +- clock-names = "extal", "extalr"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a77980-rst"; +- reg = <0 0xe6160000 0 0x200>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a77980-sysc"; +- reg = <0 0xe6180000 0 0x440>; +- #power-domain-cells = <1>; +- }; +- +- tsc: thermal@e6198000 { +- compatible = "renesas,r8a77980-thermal"; +- reg = <0 0xe6198000 0 0x100>, +- <0 0xe61a0000 0 0x100>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 522>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 522>; +- #thermal-sensor-cells = <1>; +- }; +- +- intc_ex: interrupt-controller@e61c0000 { +- compatible = "renesas,intc-ex-r8a77980", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- tmu0: timer@e61e0000 { +- compatible = "renesas,tmu-r8a77980", "renesas,tmu"; +- reg = <0 0xe61e0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 125>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 125>; +- status = "disabled"; +- }; +- +- tmu1: timer@e6fc0000 { +- compatible = "renesas,tmu-r8a77980", "renesas,tmu"; +- reg = <0 0xe6fc0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- status = "disabled"; +- }; +- +- tmu2: timer@e6fd0000 { +- compatible = "renesas,tmu-r8a77980", "renesas,tmu"; +- reg = <0 0xe6fd0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 123>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 123>; +- status = "disabled"; +- }; +- +- tmu3: timer@e6fe0000 { +- compatible = "renesas,tmu-r8a77980", "renesas,tmu"; +- reg = <0 0xe6fe0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 122>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 122>; +- status = "disabled"; +- }; +- +- tmu4: timer@ffc00000 { +- compatible = "renesas,tmu-r8a77980", "renesas,tmu"; +- reg = <0 0xffc00000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 121>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 121>; +- status = "disabled"; +- }; +- +- i2c0: i2c@e6500000 { +- compatible = "renesas,i2c-r8a77980", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6500000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- dmas = <&dmac1 0x91>, <&dmac1 0x90>, +- <&dmac2 0x91>, <&dmac2 0x90>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6508000 { +- compatible = "renesas,i2c-r8a77980", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- dmas = <&dmac1 0x93>, <&dmac1 0x92>, +- <&dmac2 0x93>, <&dmac2 0x92>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6510000 { +- compatible = "renesas,i2c-r8a77980", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6510000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- dmas = <&dmac1 0x95>, <&dmac1 0x94>, +- <&dmac2 0x95>, <&dmac2 0x94>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e66d0000 { +- compatible = "renesas,i2c-r8a77980", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- i2c-scl-internal-delay-ns = <6>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e66d8000 { +- compatible = "renesas,i2c-r8a77980", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 927>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 927>; +- i2c-scl-internal-delay-ns = <6>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c5: i2c@e66e0000 { +- compatible = "renesas,i2c-r8a77980", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 919>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 919>; +- dmas = <&dmac1 0x9b>, <&dmac1 0x9a>, +- <&dmac2 0x9b>, <&dmac2 0x9a>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- hscif0: serial@e6540000 { +- compatible = "renesas,hscif-r8a77980", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6540000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 520>, +- <&cpg CPG_CORE R8A77980_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x31>, <&dmac1 0x30>, +- <&dmac2 0x31>, <&dmac2 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 520>; +- status = "disabled"; +- }; +- +- hscif1: serial@e6550000 { +- compatible = "renesas,hscif-r8a77980", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6550000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 519>, +- <&cpg CPG_CORE R8A77980_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x33>, <&dmac1 0x32>, +- <&dmac2 0x33>, <&dmac2 0x32>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 519>; +- status = "disabled"; +- }; +- +- hscif2: serial@e6560000 { +- compatible = "renesas,hscif-r8a77980", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6560000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 518>, +- <&cpg CPG_CORE R8A77980_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x35>, <&dmac1 0x34>, +- <&dmac2 0x35>, <&dmac2 0x34>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 518>; +- status = "disabled"; +- }; +- +- hscif3: serial@e66a0000 { +- compatible = "renesas,hscif-r8a77980", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66a0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 517>, +- <&cpg CPG_CORE R8A77980_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x37>, <&dmac1 0x36>, +- <&dmac2 0x37>, <&dmac2 0x36>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 517>; +- status = "disabled"; +- }; +- +- pcie_phy: pcie-phy@e65d0000 { +- compatible = "renesas,r8a77980-pcie-phy"; +- reg = <0 0xe65d0000 0 0x8000>; +- #phy-cells = <0>; +- clocks = <&cpg CPG_MOD 319>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 319>; +- status = "disabled"; +- }; +- +- canfd: can@e66c0000 { +- compatible = "renesas,r8a77980-canfd", +- "renesas,rcar-gen3-canfd"; +- reg = <0 0xe66c0000 0 0x8000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 914>, +- <&cpg CPG_CORE R8A77980_CLK_CANFD>, +- <&can_clk>; +- clock-names = "fck", "canfd", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 914>; +- status = "disabled"; +- +- channel0 { +- status = "disabled"; +- }; +- +- channel1 { +- status = "disabled"; +- }; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a77980", +- "renesas,etheravb-rcar-gen3"; +- reg = <0 0xe6800000 0 0x800>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15", +- "ch16", "ch17", "ch18", "ch19", +- "ch20", "ch21", "ch22", "ch23", +- "ch24"; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- phy-mode = "rgmii"; +- rx-internal-delay-ps = <0>; +- tx-internal-delay-ps = <2000>; +- iommus = <&ipmmu_ds1 33>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pwm0: pwm@e6e30000 { +- compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; +- reg = <0 0xe6e30000 0 0x10>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- status = "disabled"; +- }; +- +- pwm1: pwm@e6e31000 { +- compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; +- reg = <0 0xe6e31000 0 0x10>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- status = "disabled"; +- }; +- +- pwm2: pwm@e6e32000 { +- compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; +- reg = <0 0xe6e32000 0 0x10>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- status = "disabled"; +- }; +- +- pwm3: pwm@e6e33000 { +- compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; +- reg = <0 0xe6e33000 0 0x10>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- status = "disabled"; +- }; +- +- pwm4: pwm@e6e34000 { +- compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; +- reg = <0 0xe6e34000 0 0x10>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a77980", +- "renesas,rcar-gen3-scif", +- "renesas,scif"; +- reg = <0 0xe6e60000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>, +- <&cpg CPG_CORE R8A77980_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x51>, <&dmac1 0x50>, +- <&dmac2 0x51>, <&dmac2 0x50>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a77980", +- "renesas,rcar-gen3-scif", +- "renesas,scif"; +- reg = <0 0xe6e68000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>, +- <&cpg CPG_CORE R8A77980_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x53>, <&dmac1 0x52>, +- <&dmac2 0x53>, <&dmac2 0x52>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scif3: serial@e6c50000 { +- compatible = "renesas,scif-r8a77980", +- "renesas,rcar-gen3-scif", +- "renesas,scif"; +- reg = <0 0xe6c50000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>, +- <&cpg CPG_CORE R8A77980_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x57>, <&dmac1 0x56>, +- <&dmac2 0x57>, <&dmac2 0x56>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scif4: serial@e6c40000 { +- compatible = "renesas,scif-r8a77980", +- "renesas,rcar-gen3-scif", +- "renesas,scif"; +- reg = <0 0xe6c40000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>, +- <&cpg CPG_CORE R8A77980_CLK_S3D1>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x59>, <&dmac1 0x58>, +- <&dmac2 0x59>, <&dmac2 0x58>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- tpu: pwm@e6e80000 { +- compatible = "renesas,tpu-r8a77980", "renesas,tpu"; +- reg = <0 0xe6e80000 0 0x148>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 304>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 304>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e90000 { +- compatible = "renesas,msiof-r8a77980", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6e90000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 211>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 211>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6ea0000 { +- compatible = "renesas,msiof-r8a77980", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6ea0000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 210>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 210>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6c00000 { +- compatible = "renesas,msiof-r8a77980", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c00000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 209>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 209>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof3: spi@e6c10000 { +- compatible = "renesas,msiof-r8a77980", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c10000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 208>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 208>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a77980"; +- reg = <0 0xe6ef0000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 811>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 811>; +- renesas,id = <0>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin0csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin0>; +- }; +- }; +- }; +- }; +- +- vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a77980"; +- reg = <0 0xe6ef1000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 810>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- status = "disabled"; +- renesas,id = <1>; +- resets = <&cpg 810>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin1csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin1>; +- }; +- }; +- }; +- }; +- +- vin2: video@e6ef2000 { +- compatible = "renesas,vin-r8a77980"; +- reg = <0 0xe6ef2000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 809>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 809>; +- renesas,id = <2>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin2csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin2>; +- }; +- }; +- }; +- }; +- +- vin3: video@e6ef3000 { +- compatible = "renesas,vin-r8a77980"; +- reg = <0 0xe6ef3000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 808>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 808>; +- renesas,id = <3>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin3csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&csi40vin3>; +- }; +- }; +- }; +- }; +- +- vin4: video@e6ef4000 { +- compatible = "renesas,vin-r8a77980"; +- reg = <0 0xe6ef4000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 807>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 807>; +- renesas,id = <4>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin4csi41: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&csi41vin4>; +- }; +- }; +- }; +- }; +- +- vin5: video@e6ef5000 { +- compatible = "renesas,vin-r8a77980"; +- reg = <0 0xe6ef5000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 806>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 806>; +- renesas,id = <5>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin5csi41: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&csi41vin5>; +- }; +- }; +- }; +- }; +- +- vin6: video@e6ef6000 { +- compatible = "renesas,vin-r8a77980"; +- reg = <0 0xe6ef6000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 805>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 805>; +- renesas,id = <6>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin6csi41: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&csi41vin6>; +- }; +- }; +- }; +- }; +- +- vin7: video@e6ef7000 { +- compatible = "renesas,vin-r8a77980"; +- reg = <0 0xe6ef7000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 804>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 804>; +- renesas,id = <7>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin7csi41: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&csi41vin7>; +- }; +- }; +- }; +- }; +- +- vin8: video@e6ef8000 { +- compatible = "renesas,vin-r8a77980"; +- reg = <0 0xe6ef8000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 628>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 628>; +- renesas,id = <8>; +- status = "disabled"; +- }; +- +- vin9: video@e6ef9000 { +- compatible = "renesas,vin-r8a77980"; +- reg = <0 0xe6ef9000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 627>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 627>; +- renesas,id = <9>; +- status = "disabled"; +- }; +- +- vin10: video@e6efa000 { +- compatible = "renesas,vin-r8a77980"; +- reg = <0 0xe6efa000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 625>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 625>; +- renesas,id = <10>; +- status = "disabled"; +- }; +- +- vin11: video@e6efb000 { +- compatible = "renesas,vin-r8a77980"; +- reg = <0 0xe6efb000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 618>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 618>; +- renesas,id = <11>; +- status = "disabled"; +- }; +- +- vin12: video@e6efc000 { +- compatible = "renesas,vin-r8a77980"; +- reg = <0 0xe6efc000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 612>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 612>; +- renesas,id = <12>; +- status = "disabled"; +- }; +- +- vin13: video@e6efd000 { +- compatible = "renesas,vin-r8a77980"; +- reg = <0 0xe6efd000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 608>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 608>; +- renesas,id = <13>; +- status = "disabled"; +- }; +- +- vin14: video@e6efe000 { +- compatible = "renesas,vin-r8a77980"; +- reg = <0 0xe6efe000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 605>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 605>; +- renesas,id = <14>; +- status = "disabled"; +- }; +- +- vin15: video@e6eff000 { +- compatible = "renesas,vin-r8a77980"; +- reg = <0 0xe6eff000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 604>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 604>; +- renesas,id = <15>; +- status = "disabled"; +- }; +- +- dmac1: dma-controller@e7300000 { +- compatible = "renesas,dmac-r8a77980", +- "renesas,rcar-dmac"; +- reg = <0 0xe7300000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, +- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, +- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, +- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, +- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, +- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, +- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, +- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; +- }; +- +- dmac2: dma-controller@e7310000 { +- compatible = "renesas,dmac-r8a77980", +- "renesas,rcar-dmac"; +- reg = <0 0xe7310000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 217>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 217>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, +- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, +- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, +- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, +- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, +- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, +- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, +- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; +- }; +- +- gether: ethernet@e7400000 { +- compatible = "renesas,gether-r8a77980"; +- reg = <0 0xe7400000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 813>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 813>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- ipmmu_ds1: iommu@e7740000 { +- compatible = "renesas,ipmmu-r8a77980"; +- reg = <0 0xe7740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 0>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_ir: iommu@ff8b0000 { +- compatible = "renesas,ipmmu-r8a77980"; +- reg = <0 0xff8b0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 3>; +- power-domains = <&sysc R8A77980_PD_A3IR>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mm: iommu@e67b0000 { +- compatible = "renesas,ipmmu-r8a77980"; +- reg = <0 0xe67b0000 0 0x1000>; +- interrupts = , +- ; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_rt: iommu@ffc80000 { +- compatible = "renesas,ipmmu-r8a77980"; +- reg = <0 0xffc80000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 10>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vc0: iommu@fe990000 { +- compatible = "renesas,ipmmu-r8a77980"; +- reg = <0 0xfe990000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 12>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vi0: iommu@febd0000 { +- compatible = "renesas,ipmmu-r8a77980"; +- reg = <0 0xfebd0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 14>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vip0: iommu@e7b00000 { +- compatible = "renesas,ipmmu-r8a77980"; +- reg = <0 0xe7b00000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 4>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vip1: iommu@e7960000 { +- compatible = "renesas,ipmmu-r8a77980"; +- reg = <0 0xe7960000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 11>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- mmc0: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a77980", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee140000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- max-frequency = <200000000>; +- iommus = <&ipmmu_ds1 32>; +- status = "disabled"; +- }; +- +- rpc: spi@ee200000 { +- compatible = "renesas,r8a77980-rpc-if", +- "renesas,rcar-gen3-rpc-if"; +- reg = <0 0xee200000 0 0x200>, +- <0 0x08000000 0 0x4000000>, +- <0 0xee208000 0 0x100>; +- reg-names = "regs", "dirmap", "wbuf"; +- interrupts = ; +- clocks = <&cpg CPG_MOD 917>; +- clock-names = "rpc"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 917>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1010000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x0 0xf1010000 0 0x1000>, +- <0x0 0xf1020000 0 0x20000>, +- <0x0 0xf1040000 0 0x20000>, +- <0x0 0xf1060000 0 0x20000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- pciec: pcie@fe000000 { +- compatible = "renesas,pcie-r8a77980", +- "renesas,pcie-rcar-gen3"; +- reg = <0 0xfe000000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000>, +- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>, +- <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>, +- <0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>; +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 319>; +- phys = <&pcie_phy>; +- phy-names = "pcie"; +- status = "disabled"; +- }; +- +- vspd0: vsp@fea20000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea20000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 623>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 623>; +- renesas,fcp = <&fcpvd0>; +- }; +- +- fcpvd0: fcp@fea27000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea27000 0 0x200>; +- clocks = <&cpg CPG_MOD 603>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 603>; +- }; +- +- csi40: csi2@feaa0000 { +- compatible = "renesas,r8a77980-csi2"; +- reg = <0 0xfeaa0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi40vin0: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin0csi40>; +- }; +- csi40vin1: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin1csi40>; +- }; +- csi40vin2: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&vin2csi40>; +- }; +- csi40vin3: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&vin3csi40>; +- }; +- }; +- }; +- }; +- +- csi41: csi2@feab0000 { +- compatible = "renesas,r8a77980-csi2"; +- reg = <0 0xfeab0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 715>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 715>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi41vin4: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin4csi41>; +- }; +- csi41vin5: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin5csi41>; +- }; +- csi41vin6: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&vin6csi41>; +- }; +- csi41vin7: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&vin7csi41>; +- }; +- }; +- }; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a77980"; +- reg = <0 0xfeb00000 0 0x80000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 724>; +- clock-names = "du.0"; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 724>; +- reset-names = "du.0"; +- renesas,vsps = <&vspd0 0>; +- +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb: endpoint { +- }; +- }; +- +- port@1 { +- reg = <1>; +- du_out_lvds0: endpoint { +- remote-endpoint = <&lvds0_in>; +- }; +- }; +- }; +- }; +- +- lvds0: lvds-encoder@feb90000 { +- compatible = "renesas,r8a77980-lvds"; +- reg = <0 0xfeb90000 0 0x14>; +- clocks = <&cpg CPG_MOD 727>; +- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; +- resets = <&cpg 727>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds0_in: endpoint { +- remote-endpoint = +- <&du_out_lvds0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- lvds0_out: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@fff00044 { +- compatible = "renesas,prr"; +- reg = <0 0xfff00044 0 4>; +- }; +- }; +- +- thermal-zones { +- sensor1_thermal: sensor1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 0>; +- +- trips { +- sensor1-passive { +- temperature = <95000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- sensor1-critical { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- sensor2_thermal: sensor2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 1>; +- +- trips { +- sensor2-passive { +- temperature = <95000>; +- hysteresis = <1000>; +- type = "passive"; +- }; +- sensor2-critical { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | +- IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | +- IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | +- IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | +- IRQ_TYPE_LEVEL_LOW)>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77990-ebisu.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77990-ebisu.dts +deleted file mode 100644 +index 9c7146084ea1..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77990-ebisu.dts ++++ /dev/null +@@ -1,801 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Ebisu board with R-Car E3 +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a77990.dtsi" +-#include +-#include +- +-/ { +- model = "Renesas Ebisu board based on r8a77990"; +- compatible = "renesas,ebisu", "renesas,r8a77990"; +- +- aliases { +- serial0 = &scif2; +- ethernet0 = &avb; +- mmc0 = &sdhi3; +- mmc1 = &sdhi0; +- mmc2 = &sdhi1; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- audio_clkout: audio-clkout { +- /* +- * This is same as <&rcar_sound 0> +- * but needed to avoid cs2000/rcar_sound probe dead-lock +- */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <11289600>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm3 0 50000>; +- +- brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>; +- default-brightness-level = <10>; +- +- power-supply = <®_12p0v>; +- }; +- +- cvbs-in { +- compatible = "composite-video-connector"; +- label = "CVBS IN"; +- +- port { +- cvbs_con: endpoint { +- remote-endpoint = <&adv7482_ain7>; +- }; +- }; +- }; +- +- hdmi-in { +- compatible = "hdmi-connector"; +- label = "HDMI IN"; +- type = "a"; +- +- port { +- hdmi_in_con: endpoint { +- remote-endpoint = <&adv7482_hdmi>; +- }; +- }; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_out: endpoint { +- remote-endpoint = <&adv7511_out>; +- }; +- }; +- }; +- +- keys { +- compatible = "gpio-keys"; +- +- pinctrl-0 = <&keys_pins>; +- pinctrl-names = "default"; +- +- key-1 { +- gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW4-1"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-2 { +- gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW4-2"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-3 { +- gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW4-3"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-4 { +- gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW4-4"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- }; +- +- lvds-decoder { +- compatible = "thine,thc63lvd1024"; +- vcc-supply = <®_3p3v>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- thc63lvd1024_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- thc63lvd1024_out: endpoint { +- remote-endpoint = <&adv7511_in>; +- }; +- }; +- }; +- }; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x38000000>; +- }; +- +- reg_1p8v: regulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator1 { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_12p0v: regulator2 { +- compatible = "regulator-fixed"; +- regulator-name = "D12.0V"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- rsnd_ak4613: sound { +- compatible = "simple-audio-card"; +- +- simple-audio-card,name = "rsnd-ak4613"; +- simple-audio-card,format = "left_j"; +- simple-audio-card,bitclock-master = <&sndcpu>; +- simple-audio-card,frame-master = <&sndcpu>; +- +- sndcodec: simple-audio-card,codec { +- sound-dai = <&ak4613>; +- }; +- +- sndcpu: simple-audio-card,cpu { +- sound-dai = <&rcar_sound>; +- }; +- }; +- +- vbus0_usb2: regulator-vbus0-usb2 { +- compatible = "regulator-fixed"; +- +- regulator-name = "USB20_VBUS_CN"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vcc_sdhi0: regulator-vcc-sdhi0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI0 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhi0: regulator-vccq-sdhi0 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI0 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- vcc_sdhi1: regulator-vcc-sdhi1 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI1 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhi1: regulator-vccq-sdhi1 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI1 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- vga { +- compatible = "vga-connector"; +- +- port { +- vga_in: endpoint { +- remote-endpoint = <&adv7123_out>; +- }; +- }; +- }; +- +- vga-encoder { +- compatible = "adi,adv7123"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7123_in: endpoint { +- remote-endpoint = <&du_out_rgb>; +- }; +- }; +- port@1 { +- reg = <1>; +- adv7123_out: endpoint { +- remote-endpoint = <&vga_in>; +- }; +- }; +- }; +- }; +- +- x12_clk: x12 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +- +- x13_clk: x13 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <74250000>; +- }; +-}; +- +-&audio_clk_a { +- clock-frequency = <22579200>; +-}; +- +-&avb { +- pinctrl-0 = <&avb_pins>; +- pinctrl-names = "default"; +- phy-handle = <&phy0>; +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- rxc-skew-ps = <1500>; +- reg = <0>; +- interrupt-parent = <&gpio2>; +- interrupts = <21 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; +- /* +- * TX clock internal delay mode is required for reliable +- * 1Gbps communication using the KSZ9031RNX phy present on +- * the Ebisu board, however, TX clock internal delay mode +- * isn't supported on r8a77990. Thus, limit speed to +- * 100Mbps for reliable communication. +- */ +- max-speed = <100>; +- }; +-}; +- +-&canfd { +- pinctrl-0 = <&canfd0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- channel0 { +- status = "okay"; +- }; +-}; +- +-&csi40 { +- status = "okay"; +- +- ports { +- port@0 { +- csi40_in: endpoint { +- clock-lanes = <0>; +- data-lanes = <1 2>; +- remote-endpoint = <&adv7482_txa>; +- }; +- }; +- }; +-}; +- +-&du { +- pinctrl-0 = <&du_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&x13_clk>; +- clock-names = "du.0", "du.1", "dclkin.0"; +- +- ports { +- port@0 { +- endpoint { +- remote-endpoint = <&adv7123_in>; +- }; +- }; +- }; +-}; +- +-&ehci0 { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&extal_clk { +- clock-frequency = <48000000>; +-}; +- +-&hsusb { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- io_expander: gpio@20 { +- compatible = "onnn,pca9654"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&gpio2>; +- interrupts = <22 IRQ_TYPE_LEVEL_LOW>; +- }; +- +- hdmi-encoder@39 { +- compatible = "adi,adv7511w"; +- reg = <0x39>; +- interrupt-parent = <&gpio1>; +- interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +- +- adi,input-depth = <8>; +- adi,input-colorspace = "rgb"; +- adi,input-clock = "1x"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7511_in: endpoint { +- remote-endpoint = <&thc63lvd1024_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- adv7511_out: endpoint { +- remote-endpoint = <&hdmi_con_out>; +- }; +- }; +- }; +- }; +- +- video-receiver@70 { +- compatible = "adi,adv7482"; +- reg = <0x70>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- interrupt-parent = <&gpio0>; +- interrupt-names = "intrq1", "intrq2"; +- interrupts = <7 IRQ_TYPE_LEVEL_LOW>, +- <17 IRQ_TYPE_LEVEL_LOW>; +- +- port@7 { +- reg = <7>; +- +- adv7482_ain7: endpoint { +- remote-endpoint = <&cvbs_con>; +- }; +- }; +- +- port@8 { +- reg = <8>; +- +- adv7482_hdmi: endpoint { +- remote-endpoint = <&hdmi_in_con>; +- }; +- }; +- +- port@a { +- reg = <10>; +- +- adv7482_txa: endpoint { +- clock-lanes = <0>; +- data-lanes = <1 2>; +- remote-endpoint = <&csi40_in>; +- }; +- }; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +- +- ak4613: codec@10 { +- compatible = "asahi-kasei,ak4613"; +- #sound-dai-cells = <0>; +- reg = <0x10>; +- clocks = <&rcar_sound 3>; +- +- asahi-kasei,in1-single-end; +- asahi-kasei,in2-single-end; +- asahi-kasei,out1-single-end; +- asahi-kasei,out2-single-end; +- asahi-kasei,out3-single-end; +- asahi-kasei,out4-single-end; +- asahi-kasei,out5-single-end; +- asahi-kasei,out6-single-end; +- }; +- +- cs2000: clk-multiplier@4f { +- #clock-cells = <0>; +- compatible = "cirrus,cs2000-cp"; +- reg = <0x4f>; +- clocks = <&audio_clkout>, <&x12_clk>; +- clock-names = "clk_in", "ref_clk"; +- +- assigned-clocks = <&cs2000>; +- assigned-clock-rates = <24576000>; /* 1/1 divide */ +- }; +-}; +- +-&i2c_dvfs { +- status = "okay"; +- +- clock-frequency = <400000>; +- +- pmic: pmic@30 { +- pinctrl-0 = <&irq0_pins>; +- pinctrl-names = "default"; +- +- compatible = "rohm,bd9571mwv"; +- reg = <0x30>; +- interrupt-parent = <&intc_ex>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- rohm,ddr-backup-power = <0x1>; +- rohm,rstbmode-level; +- }; +- +- eeprom@50 { +- compatible = "rohm,br24t01", "atmel,24c01"; +- reg = <0x50>; +- pagesize = <8>; +- }; +-}; +- +-&lvds0 { +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 727>, +- <&x13_clk>, +- <&extal_clk>; +- clock-names = "fck", "dclkin.0", "extal"; +- +- ports { +- port@1 { +- lvds0_out: endpoint { +- remote-endpoint = <&thc63lvd1024_in>; +- }; +- }; +- }; +-}; +- +-&lvds1 { +- /* +- * Even though the LVDS1 output is not connected, the encoder must be +- * enabled to supply a pixel clock to the DU for the DPAD output when +- * LVDS0 is in use. +- */ +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 727>, +- <&x13_clk>, +- <&extal_clk>; +- clock-names = "fck", "dclkin.0", "extal"; +-}; +- +-&ohci0 { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&pcie_bus_clk { +- clock-frequency = <100000000>; +-}; +- +-&pciec0 { +- status = "okay"; +-}; +- +-&pfc { +- avb_pins: avb { +- groups = "avb_link", "avb_mii"; +- function = "avb"; +- }; +- +- canfd0_pins: canfd0 { +- groups = "canfd0_data"; +- function = "canfd0"; +- }; +- +- du_pins: du { +- groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; +- function = "du"; +- }; +- +- irq0_pins: irq0 { +- groups = "intc_ex_irq0"; +- function = "intc_ex"; +- }; +- +- keys_pins: keys { +- pins = "GP_5_10", "GP_5_11", "GP_5_12", "GP_5_13"; +- bias-pull-up; +- }; +- +- pwm3_pins: pwm3 { +- groups = "pwm3_b"; +- function = "pwm3"; +- }; +- +- pwm5_pins: pwm5 { +- groups = "pwm5_a"; +- function = "pwm5"; +- }; +- +- scif2_pins: scif2 { +- groups = "scif2_data_a"; +- function = "scif2"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <3300>; +- }; +- +- sdhi0_pins_uhs: sd0_uhs { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <1800>; +- }; +- +- sdhi1_pins: sd1 { +- groups = "sdhi1_data4", "sdhi1_ctrl"; +- function = "sdhi1"; +- power-source = <3300>; +- }; +- +- sdhi1_pins_uhs: sd1_uhs { +- groups = "sdhi1_data4", "sdhi1_ctrl"; +- function = "sdhi1"; +- power-source = <1800>; +- }; +- +- sdhi3_pins: sd3 { +- groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; +- function = "sdhi3"; +- power-source = <1800>; +- }; +- +- sound_clk_pins: sound_clk { +- groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a", +- "audio_clkout_a", "audio_clkout1_a"; +- function = "audio_clk"; +- }; +- +- sound_pins: sound { +- groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data"; +- function = "ssi"; +- }; +- +- usb0_pins: usb { +- groups = "usb0_b", "usb0_id"; +- function = "usb0"; +- }; +- +- usb30_pins: usb30 { +- groups = "usb30"; +- function = "usb30"; +- }; +-}; +- +-&pwm3 { +- pinctrl-0 = <&pwm3_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&pwm5 { +- pinctrl-0 = <&pwm5_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&rcar_sound { +- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; +- pinctrl-names = "default"; +- +- /* Single DAI */ +- #sound-dai-cells = <0>; +- +- /* audio_clkout0/1/2/3 */ +- #clock-cells = <1>; +- clock-frequency = <12288000 11289600>; +- +- status = "okay"; +- +- /* update to */ +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&cs2000>, <&audio_clk_c>, +- <&cpg CPG_CORE R8A77990_CLK_ZA2>; +- +- rcar_sound,dai { +- dai0 { +- playback = <&ssi0>, <&src0>, <&dvc0>; +- capture = <&ssi1>, <&src1>, <&dvc1>; +- }; +- }; +- +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&scif2 { +- pinctrl-0 = <&scif2_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-1 = <&sdhi0_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <&vcc_sdhi0>; +- vqmmc-supply = <&vccq_sdhi0>; +- cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; +- bus-width = <4>; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- status = "okay"; +-}; +- +-&sdhi1 { +- pinctrl-0 = <&sdhi1_pins>; +- pinctrl-1 = <&sdhi1_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <&vcc_sdhi1>; +- vqmmc-supply = <&vccq_sdhi1>; +- cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- status = "okay"; +-}; +- +-&sdhi3 { +- /* used for on-board 8bit eMMC */ +- pinctrl-0 = <&sdhi3_pins>; +- pinctrl-1 = <&sdhi3_pins>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_1p8v>; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- bus-width = <8>; +- no-sd; +- no-sdio; +- non-removable; +- full-pwr-cycle-in-suspend; +- status = "okay"; +-}; +- +-&ssi1 { +- shared-pin; +-}; +- +-&usb2_phy0 { +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +- +- vbus-supply = <&vbus0_usb2>; +- status = "okay"; +-}; +- +-&usb3_peri0 { +- companion = <&xhci0>; +- status = "okay"; +-}; +- +-&vin4 { +- status = "okay"; +-}; +- +-&vin5 { +- status = "okay"; +-}; +- +-&xhci0 { +- pinctrl-0 = <&usb30_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77990.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r8a77990.dtsi +deleted file mode 100644 +index 0ea300a8147d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77990.dtsi ++++ /dev/null +@@ -1,2139 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Car E3 (R8A77990) SoC +- * +- * Copyright (C) 2018-2019 Renesas Electronics Corp. +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r8a77990"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c7; +- }; +- +- /* +- * The external audio clocks are configured as 0 Hz fixed frequency +- * clocks by default. +- * Boards that provide audio clocks should override them. +- */ +- audio_clk_a: audio_clk_a { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_b: audio_clk_b { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_c: audio_clk_c { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* External CAN clock - to be overridden by boards that provide it */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- cluster1_opp: opp_table10 { +- compatible = "operating-points-v2"; +- opp-shared; +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <820000>; +- clock-latency-ns = <300000>; +- opp-suspend; +- }; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- a53_0: cpu@0 { +- compatible = "arm,cortex-a53"; +- reg = <0>; +- device_type = "cpu"; +- #cooling-cells = <2>; +- power-domains = <&sysc R8A77990_PD_CA53_CPU0>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- dynamic-power-coefficient = <277>; +- clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- }; +- +- a53_1: cpu@1 { +- compatible = "arm,cortex-a53"; +- reg = <1>; +- device_type = "cpu"; +- power-domains = <&sysc R8A77990_PD_CA53_CPU1>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- cpu-idle-states = <&CPU_SLEEP_0>; +- clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; +- operating-points-v2 = <&cluster1_opp>; +- }; +- +- L2_CA53: cache-controller-0 { +- compatible = "cache"; +- power-domains = <&sysc R8A77990_PD_CA53_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP_0: cpu-sleep-0 { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x0010000>; +- local-timer-stop; +- entry-latency-us = <700>; +- exit-latency-us = <700>; +- min-residency-us = <5000>; +- }; +- }; +- }; +- +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- /* External PCIe clock - can be overridden by the board */ +- pcie_bus_clk: pcie_bus { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- pmu_a53 { +- compatible = "arm,cortex-a53-pmu"; +- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, +- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-affinity = <&a53_0>, <&a53_1>; +- }; +- +- psci { +- compatible = "arm,psci-1.0", "arm,psci-0.2"; +- method = "smc"; +- }; +- +- /* External SCIF clock - to be overridden by boards that provide it */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- soc: soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a77990-wdt", +- "renesas,rcar-gen3-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a77990", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 18>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a77990", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 23>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a77990", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 26>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a77990", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 16>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a77990", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 11>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a77990", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 20>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- gpio6: gpio@e6055400 { +- compatible = "renesas,gpio-r8a77990", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055400 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 192 18>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 906>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 906>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a77990"; +- reg = <0 0xe6060000 0 0x508>; +- }; +- +- i2c_dvfs: i2c@e60b0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,iic-r8a77990", +- "renesas,rcar-gen3-iic", +- "renesas,rmobile-iic"; +- reg = <0 0xe60b0000 0 0x425>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 926>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 926>; +- dmas = <&dmac0 0x11>, <&dmac0 0x10>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- cmt0: timer@e60f0000 { +- compatible = "renesas,r8a77990-cmt0", +- "renesas,rcar-gen3-cmt0"; +- reg = <0 0xe60f0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 303>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 303>; +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a77990-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 302>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 302>; +- status = "disabled"; +- }; +- +- cmt2: timer@e6140000 { +- compatible = "renesas,r8a77990-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6140000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 301>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 301>; +- status = "disabled"; +- }; +- +- cmt3: timer@e6148000 { +- compatible = "renesas,r8a77990-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6148000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 300>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 300>; +- status = "disabled"; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a77990-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>; +- clock-names = "extal"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a77990-rst"; +- reg = <0 0xe6160000 0 0x0200>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a77990-sysc"; +- reg = <0 0xe6180000 0 0x0400>; +- #power-domain-cells = <1>; +- }; +- +- thermal: thermal@e6190000 { +- compatible = "renesas,thermal-r8a77990"; +- reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 522>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 522>; +- #thermal-sensor-cells = <0>; +- }; +- +- intc_ex: interrupt-controller@e61c0000 { +- compatible = "renesas,intc-ex-r8a77990", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- tmu0: timer@e61e0000 { +- compatible = "renesas,tmu-r8a77990", "renesas,tmu"; +- reg = <0 0xe61e0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 125>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 125>; +- status = "disabled"; +- }; +- +- tmu1: timer@e6fc0000 { +- compatible = "renesas,tmu-r8a77990", "renesas,tmu"; +- reg = <0 0xe6fc0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- status = "disabled"; +- }; +- +- tmu2: timer@e6fd0000 { +- compatible = "renesas,tmu-r8a77990", "renesas,tmu"; +- reg = <0 0xe6fd0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 123>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 123>; +- status = "disabled"; +- }; +- +- tmu3: timer@e6fe0000 { +- compatible = "renesas,tmu-r8a77990", "renesas,tmu"; +- reg = <0 0xe6fe0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 122>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 122>; +- status = "disabled"; +- }; +- +- tmu4: timer@ffc00000 { +- compatible = "renesas,tmu-r8a77990", "renesas,tmu"; +- reg = <0 0xffc00000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 121>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 121>; +- status = "disabled"; +- }; +- +- i2c0: i2c@e6500000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77990", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6500000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- dmas = <&dmac1 0x91>, <&dmac1 0x90>, +- <&dmac2 0x91>, <&dmac2 0x90>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6508000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77990", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- dmas = <&dmac1 0x93>, <&dmac1 0x92>, +- <&dmac2 0x93>, <&dmac2 0x92>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6510000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77990", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6510000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- dmas = <&dmac1 0x95>, <&dmac1 0x94>, +- <&dmac2 0x95>, <&dmac2 0x94>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e66d0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77990", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- dmas = <&dmac0 0x97>, <&dmac0 0x96>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e66d8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77990", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 927>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 927>; +- dmas = <&dmac0 0x99>, <&dmac0 0x98>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c5: i2c@e66e0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77990", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 919>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 919>; +- dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c6: i2c@e66e8000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77990", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 918>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 918>; +- dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c7: i2c@e6690000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77990", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6690000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 1003>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 1003>; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- hscif0: serial@e6540000 { +- compatible = "renesas,hscif-r8a77990", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6540000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 520>, +- <&cpg CPG_CORE R8A77990_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x31>, <&dmac1 0x30>, +- <&dmac2 0x31>, <&dmac2 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 520>; +- status = "disabled"; +- }; +- +- hscif1: serial@e6550000 { +- compatible = "renesas,hscif-r8a77990", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6550000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 519>, +- <&cpg CPG_CORE R8A77990_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x33>, <&dmac1 0x32>, +- <&dmac2 0x33>, <&dmac2 0x32>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 519>; +- status = "disabled"; +- }; +- +- hscif2: serial@e6560000 { +- compatible = "renesas,hscif-r8a77990", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6560000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 518>, +- <&cpg CPG_CORE R8A77990_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x35>, <&dmac1 0x34>, +- <&dmac2 0x35>, <&dmac2 0x34>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 518>; +- status = "disabled"; +- }; +- +- hscif3: serial@e66a0000 { +- compatible = "renesas,hscif-r8a77990", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66a0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 517>, +- <&cpg CPG_CORE R8A77990_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x37>, <&dmac0 0x36>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 517>; +- status = "disabled"; +- }; +- +- hscif4: serial@e66b0000 { +- compatible = "renesas,hscif-r8a77990", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66b0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 516>, +- <&cpg CPG_CORE R8A77990_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x39>, <&dmac0 0x38>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 516>; +- status = "disabled"; +- }; +- +- hsusb: usb@e6590000 { +- compatible = "renesas,usbhs-r8a77990", +- "renesas,rcar-gen3-usbhs"; +- reg = <0 0xe6590000 0 0x200>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; +- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, +- <&usb_dmac1 0>, <&usb_dmac1 1>; +- dma-names = "ch0", "ch1", "ch2", "ch3"; +- renesas,buswait = <11>; +- phys = <&usb2_phy0 3>; +- phy-names = "usb"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 704>, <&cpg 703>; +- status = "disabled"; +- }; +- +- usb_dmac0: dma-controller@e65a0000 { +- compatible = "renesas,r8a77990-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65a0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 330>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 330>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac1: dma-controller@e65b0000 { +- compatible = "renesas,r8a77990-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65b0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 331>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 331>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- arm_cc630p: crypto@e6601000 { +- compatible = "arm,cryptocell-630p-ree"; +- interrupts = ; +- reg = <0x0 0xe6601000 0 0x1000>; +- clocks = <&cpg CPG_MOD 229>; +- resets = <&cpg 229>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a77990", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, +- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, +- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, +- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, +- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, +- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, +- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, +- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; +- }; +- +- dmac1: dma-controller@e7300000 { +- compatible = "renesas,dmac-r8a77990", +- "renesas,rcar-dmac"; +- reg = <0 0xe7300000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, +- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, +- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, +- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, +- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, +- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, +- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, +- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; +- }; +- +- dmac2: dma-controller@e7310000 { +- compatible = "renesas,dmac-r8a77990", +- "renesas,rcar-dmac"; +- reg = <0 0xe7310000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 217>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 217>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, +- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, +- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, +- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, +- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, +- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, +- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, +- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; +- }; +- +- ipmmu_ds0: iommu@e6740000 { +- compatible = "renesas,ipmmu-r8a77990"; +- reg = <0 0xe6740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 0>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_ds1: iommu@e7740000 { +- compatible = "renesas,ipmmu-r8a77990"; +- reg = <0 0xe7740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 1>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_hc: iommu@e6570000 { +- compatible = "renesas,ipmmu-r8a77990"; +- reg = <0 0xe6570000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 2>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mm: iommu@e67b0000 { +- compatible = "renesas,ipmmu-r8a77990"; +- reg = <0 0xe67b0000 0 0x1000>; +- interrupts = , +- ; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mp: iommu@ec670000 { +- compatible = "renesas,ipmmu-r8a77990"; +- reg = <0 0xec670000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 4>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_pv0: iommu@fd800000 { +- compatible = "renesas,ipmmu-r8a77990"; +- reg = <0 0xfd800000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 6>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_rt: iommu@ffc80000 { +- compatible = "renesas,ipmmu-r8a77990"; +- reg = <0 0xffc80000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 10>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vc0: iommu@fe6b0000 { +- compatible = "renesas,ipmmu-r8a77990"; +- reg = <0 0xfe6b0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 12>; +- power-domains = <&sysc R8A77990_PD_A3VC>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vi0: iommu@febd0000 { +- compatible = "renesas,ipmmu-r8a77990"; +- reg = <0 0xfebd0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 14>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vp0: iommu@fe990000 { +- compatible = "renesas,ipmmu-r8a77990"; +- reg = <0 0xfe990000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 16>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a77990", +- "renesas,etheravb-rcar-gen3"; +- reg = <0 0xe6800000 0 0x800>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15", +- "ch16", "ch17", "ch18", "ch19", +- "ch20", "ch21", "ch22", "ch23", +- "ch24"; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- phy-mode = "rgmii"; +- rx-internal-delay-ps = <0>; +- iommus = <&ipmmu_ds0 16>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- can0: can@e6c30000 { +- compatible = "renesas,can-r8a77990", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c30000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>, +- <&cpg CPG_CORE R8A77990_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- status = "disabled"; +- }; +- +- can1: can@e6c38000 { +- compatible = "renesas,can-r8a77990", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c38000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>, +- <&cpg CPG_CORE R8A77990_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- status = "disabled"; +- }; +- +- canfd: can@e66c0000 { +- compatible = "renesas,r8a77990-canfd", +- "renesas,rcar-gen3-canfd"; +- reg = <0 0xe66c0000 0 0x8000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 914>, +- <&cpg CPG_CORE R8A77990_CLK_CANFD>, +- <&can_clk>; +- clock-names = "fck", "canfd", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 914>; +- status = "disabled"; +- +- channel0 { +- status = "disabled"; +- }; +- +- channel1 { +- status = "disabled"; +- }; +- }; +- +- pwm0: pwm@e6e30000 { +- compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; +- reg = <0 0xe6e30000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm1: pwm@e6e31000 { +- compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; +- reg = <0 0xe6e31000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm2: pwm@e6e32000 { +- compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; +- reg = <0 0xe6e32000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm3: pwm@e6e33000 { +- compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; +- reg = <0 0xe6e33000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm4: pwm@e6e34000 { +- compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; +- reg = <0 0xe6e34000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm5: pwm@e6e35000 { +- compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; +- reg = <0 0xe6e35000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- pwm6: pwm@e6e36000 { +- compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; +- reg = <0 0xe6e36000 0 0x8>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a77990", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e60000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>, +- <&cpg CPG_CORE R8A77990_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x51>, <&dmac1 0x50>, +- <&dmac2 0x51>, <&dmac2 0x50>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a77990", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e68000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>, +- <&cpg CPG_CORE R8A77990_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x53>, <&dmac1 0x52>, +- <&dmac2 0x53>, <&dmac2 0x52>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e88000 { +- compatible = "renesas,scif-r8a77990", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e88000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 310>, +- <&cpg CPG_CORE R8A77990_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x13>, <&dmac1 0x12>, +- <&dmac2 0x13>, <&dmac2 0x12>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 310>; +- status = "disabled"; +- }; +- +- scif3: serial@e6c50000 { +- compatible = "renesas,scif-r8a77990", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c50000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>, +- <&cpg CPG_CORE R8A77990_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x57>, <&dmac0 0x56>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scif4: serial@e6c40000 { +- compatible = "renesas,scif-r8a77990", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c40000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>, +- <&cpg CPG_CORE R8A77990_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x59>, <&dmac0 0x58>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- scif5: serial@e6f30000 { +- compatible = "renesas,scif-r8a77990", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6f30000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 202>, +- <&cpg CPG_CORE R8A77990_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 202>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e90000 { +- compatible = "renesas,msiof-r8a77990", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6e90000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 211>; +- dmas = <&dmac1 0x41>, <&dmac1 0x40>, +- <&dmac2 0x41>, <&dmac2 0x40>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 211>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6ea0000 { +- compatible = "renesas,msiof-r8a77990", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6ea0000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 210>; +- dmas = <&dmac0 0x43>, <&dmac0 0x42>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 210>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6c00000 { +- compatible = "renesas,msiof-r8a77990", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c00000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 209>; +- dmas = <&dmac0 0x45>, <&dmac0 0x44>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 209>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof3: spi@e6c10000 { +- compatible = "renesas,msiof-r8a77990", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c10000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 208>; +- dmas = <&dmac0 0x47>, <&dmac0 0x46>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 208>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- vin4: video@e6ef4000 { +- compatible = "renesas,vin-r8a77990"; +- reg = <0 0xe6ef4000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 807>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 807>; +- renesas,id = <4>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin4csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint= <&csi40vin4>; +- }; +- }; +- }; +- }; +- +- vin5: video@e6ef5000 { +- compatible = "renesas,vin-r8a77990"; +- reg = <0 0xe6ef5000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 806>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 806>; +- renesas,id = <5>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- vin5csi40: endpoint@2 { +- reg = <2>; +- remote-endpoint= <&csi40vin5>; +- }; +- }; +- }; +- }; +- +- drif00: rif@e6f40000 { +- compatible = "renesas,r8a77990-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f40000 0 0x84>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 515>; +- clock-names = "fck"; +- dmas = <&dmac1 0x20>, <&dmac2 0x20>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 515>; +- renesas,bonding = <&drif01>; +- status = "disabled"; +- }; +- +- drif01: rif@e6f50000 { +- compatible = "renesas,r8a77990-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f50000 0 0x84>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 514>; +- clock-names = "fck"; +- dmas = <&dmac1 0x22>, <&dmac2 0x22>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 514>; +- renesas,bonding = <&drif00>; +- status = "disabled"; +- }; +- +- drif10: rif@e6f60000 { +- compatible = "renesas,r8a77990-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f60000 0 0x84>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 513>; +- clock-names = "fck"; +- dmas = <&dmac1 0x24>, <&dmac2 0x24>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 513>; +- renesas,bonding = <&drif11>; +- status = "disabled"; +- }; +- +- drif11: rif@e6f70000 { +- compatible = "renesas,r8a77990-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f70000 0 0x84>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 512>; +- clock-names = "fck"; +- dmas = <&dmac1 0x26>, <&dmac2 0x26>; +- dma-names = "rx", "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 512>; +- renesas,bonding = <&drif10>; +- status = "disabled"; +- }; +- +- drif20: rif@e6f80000 { +- compatible = "renesas,r8a77990-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f80000 0 0x84>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 511>; +- clock-names = "fck"; +- dmas = <&dmac0 0x28>; +- dma-names = "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 511>; +- renesas,bonding = <&drif21>; +- status = "disabled"; +- }; +- +- drif21: rif@e6f90000 { +- compatible = "renesas,r8a77990-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6f90000 0 0x84>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 510>; +- clock-names = "fck"; +- dmas = <&dmac0 0x2a>; +- dma-names = "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 510>; +- renesas,bonding = <&drif20>; +- status = "disabled"; +- }; +- +- drif30: rif@e6fa0000 { +- compatible = "renesas,r8a77990-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6fa0000 0 0x84>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 509>; +- clock-names = "fck"; +- dmas = <&dmac0 0x2c>; +- dma-names = "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 509>; +- renesas,bonding = <&drif31>; +- status = "disabled"; +- }; +- +- drif31: rif@e6fb0000 { +- compatible = "renesas,r8a77990-drif", +- "renesas,rcar-gen3-drif"; +- reg = <0 0xe6fb0000 0 0x84>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 508>; +- clock-names = "fck"; +- dmas = <&dmac0 0x2e>; +- dma-names = "rx"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 508>; +- renesas,bonding = <&drif30>; +- status = "disabled"; +- }; +- +- rcar_sound: sound@ec500000 { +- /* +- * #sound-dai-cells is required +- * +- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; +- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; +- */ +- /* +- * #clock-cells is required for audio_clkout0/1/2/3 +- * +- * clkout : #clock-cells = <0>; <&rcar_sound>; +- * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; +- */ +- compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3"; +- reg = <0 0xec500000 0 0x1000>, /* SCU */ +- <0 0xec5a0000 0 0x100>, /* ADG */ +- <0 0xec540000 0 0x1000>, /* SSIU */ +- <0 0xec541000 0 0x280>, /* SSI */ +- <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ +- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; +- +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&audio_clk_b>, +- <&audio_clk_c>, +- <&cpg CPG_CORE R8A77990_CLK_ZA2>; +- clock-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0", +- "src.9", "src.8", "src.7", "src.6", +- "src.5", "src.4", "src.3", "src.2", +- "src.1", "src.0", +- "mix.1", "mix.0", +- "ctu.1", "ctu.0", +- "dvc.0", "dvc.1", +- "clk_a", "clk_b", "clk_c", "clk_i"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 1005>, +- <&cpg 1006>, <&cpg 1007>, +- <&cpg 1008>, <&cpg 1009>, +- <&cpg 1010>, <&cpg 1011>, +- <&cpg 1012>, <&cpg 1013>, +- <&cpg 1014>, <&cpg 1015>; +- reset-names = "ssi-all", +- "ssi.9", "ssi.8", "ssi.7", "ssi.6", +- "ssi.5", "ssi.4", "ssi.3", "ssi.2", +- "ssi.1", "ssi.0"; +- status = "disabled"; +- +- rcar_sound,ctu { +- ctu00: ctu-0 { }; +- ctu01: ctu-1 { }; +- ctu02: ctu-2 { }; +- ctu03: ctu-3 { }; +- ctu10: ctu-4 { }; +- ctu11: ctu-5 { }; +- ctu12: ctu-6 { }; +- ctu13: ctu-7 { }; +- }; +- +- rcar_sound,dvc { +- dvc0: dvc-0 { +- dmas = <&audma0 0xbc>; +- dma-names = "tx"; +- }; +- dvc1: dvc-1 { +- dmas = <&audma0 0xbe>; +- dma-names = "tx"; +- }; +- }; +- +- rcar_sound,mix { +- mix0: mix-0 { }; +- mix1: mix-1 { }; +- }; +- +- rcar_sound,src { +- src0: src-0 { +- interrupts = ; +- dmas = <&audma0 0x85>, <&audma0 0x9a>; +- dma-names = "rx", "tx"; +- }; +- src1: src-1 { +- interrupts = ; +- dmas = <&audma0 0x87>, <&audma0 0x9c>; +- dma-names = "rx", "tx"; +- }; +- src2: src-2 { +- interrupts = ; +- dmas = <&audma0 0x89>, <&audma0 0x9e>; +- dma-names = "rx", "tx"; +- }; +- src3: src-3 { +- interrupts = ; +- dmas = <&audma0 0x8b>, <&audma0 0xa0>; +- dma-names = "rx", "tx"; +- }; +- src4: src-4 { +- interrupts = ; +- dmas = <&audma0 0x8d>, <&audma0 0xb0>; +- dma-names = "rx", "tx"; +- }; +- src5: src-5 { +- interrupts = ; +- dmas = <&audma0 0x8f>, <&audma0 0xb2>; +- dma-names = "rx", "tx"; +- }; +- src6: src-6 { +- interrupts = ; +- dmas = <&audma0 0x91>, <&audma0 0xb4>; +- dma-names = "rx", "tx"; +- }; +- src7: src-7 { +- interrupts = ; +- dmas = <&audma0 0x93>, <&audma0 0xb6>; +- dma-names = "rx", "tx"; +- }; +- src8: src-8 { +- interrupts = ; +- dmas = <&audma0 0x95>, <&audma0 0xb8>; +- dma-names = "rx", "tx"; +- }; +- src9: src-9 { +- interrupts = ; +- dmas = <&audma0 0x97>, <&audma0 0xba>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssi { +- ssi0: ssi-0 { +- interrupts = ; +- dmas = <&audma0 0x01>, <&audma0 0x02>, +- <&audma0 0x15>, <&audma0 0x16>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi1: ssi-1 { +- interrupts = ; +- dmas = <&audma0 0x03>, <&audma0 0x04>, +- <&audma0 0x49>, <&audma0 0x4a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi2: ssi-2 { +- interrupts = ; +- dmas = <&audma0 0x05>, <&audma0 0x06>, +- <&audma0 0x63>, <&audma0 0x64>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi3: ssi-3 { +- interrupts = ; +- dmas = <&audma0 0x07>, <&audma0 0x08>, +- <&audma0 0x6f>, <&audma0 0x70>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi4: ssi-4 { +- interrupts = ; +- dmas = <&audma0 0x09>, <&audma0 0x0a>, +- <&audma0 0x71>, <&audma0 0x72>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi5: ssi-5 { +- interrupts = ; +- dmas = <&audma0 0x0b>, <&audma0 0x0c>, +- <&audma0 0x73>, <&audma0 0x74>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi6: ssi-6 { +- interrupts = ; +- dmas = <&audma0 0x0d>, <&audma0 0x0e>, +- <&audma0 0x75>, <&audma0 0x76>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi7: ssi-7 { +- interrupts = ; +- dmas = <&audma0 0x0f>, <&audma0 0x10>, +- <&audma0 0x79>, <&audma0 0x7a>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi8: ssi-8 { +- interrupts = ; +- dmas = <&audma0 0x11>, <&audma0 0x12>, +- <&audma0 0x7b>, <&audma0 0x7c>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi9: ssi-9 { +- interrupts = ; +- dmas = <&audma0 0x13>, <&audma0 0x14>, +- <&audma0 0x7d>, <&audma0 0x7e>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- }; +- }; +- +- audma0: dma-controller@ec700000 { +- compatible = "renesas,dmac-r8a77990", +- "renesas,rcar-dmac"; +- reg = <0 0xec700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 502>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 502>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, +- <&ipmmu_mp 2>, <&ipmmu_mp 3>, +- <&ipmmu_mp 4>, <&ipmmu_mp 5>, +- <&ipmmu_mp 6>, <&ipmmu_mp 7>, +- <&ipmmu_mp 8>, <&ipmmu_mp 9>, +- <&ipmmu_mp 10>, <&ipmmu_mp 11>, +- <&ipmmu_mp 12>, <&ipmmu_mp 13>, +- <&ipmmu_mp 14>, <&ipmmu_mp 15>; +- }; +- +- xhci0: usb@ee000000 { +- compatible = "renesas,xhci-r8a77990", +- "renesas,rcar-gen3-xhci"; +- reg = <0 0xee000000 0 0xc00>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- status = "disabled"; +- }; +- +- usb3_peri0: usb@ee020000 { +- compatible = "renesas,r8a77990-usb3-peri", +- "renesas,rcar-gen3-usb3-peri"; +- reg = <0 0xee020000 0 0x400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 328>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 328>; +- status = "disabled"; +- }; +- +- ohci0: usb@ee080000 { +- compatible = "generic-ohci"; +- reg = <0 0xee080000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- ehci0: usb@ee080100 { +- compatible = "generic-ehci"; +- reg = <0 0xee080100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 2>; +- phy-names = "usb"; +- companion = <&ohci0>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- usb2_phy0: usb-phy@ee080200 { +- compatible = "renesas,usb2-phy-r8a77990", +- "renesas,rcar-gen3-usb2-phy"; +- reg = <0 0xee080200 0 0x700>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- sdhi0: mmc@ee100000 { +- compatible = "renesas,sdhi-r8a77990", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee100000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 314>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 314>; +- iommus = <&ipmmu_ds1 32>; +- status = "disabled"; +- }; +- +- sdhi1: mmc@ee120000 { +- compatible = "renesas,sdhi-r8a77990", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee120000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 313>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 313>; +- iommus = <&ipmmu_ds1 33>; +- status = "disabled"; +- }; +- +- sdhi3: mmc@ee160000 { +- compatible = "renesas,sdhi-r8a77990", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee160000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 311>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 311>; +- iommus = <&ipmmu_ds1 35>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1010000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x0 0xf1010000 0 0x1000>, +- <0x0 0xf1020000 0 0x20000>, +- <0x0 0xf1040000 0 0x20000>, +- <0x0 0xf1060000 0 0x20000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- pciec0: pcie@fe000000 { +- compatible = "renesas,pcie-r8a77990", +- "renesas,pcie-rcar-gen3"; +- reg = <0 0xfe000000 0 0x80000>; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0xff>; +- device_type = "pci"; +- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, +- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, +- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, +- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; +- /* Map all possible DDR as inbound ranges */ +- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; +- interrupts = , +- , +- ; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; +- clock-names = "pcie", "pcie_bus"; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 319>; +- status = "disabled"; +- }; +- +- vspb0: vsp@fe960000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe960000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 626>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 626>; +- renesas,fcp = <&fcpvb0>; +- }; +- +- fcpvb0: fcp@fe96f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe96f000 0 0x200>; +- clocks = <&cpg CPG_MOD 607>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 607>; +- iommus = <&ipmmu_vp0 5>; +- }; +- +- vspi0: vsp@fe9a0000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe9a0000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 631>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 631>; +- renesas,fcp = <&fcpvi0>; +- }; +- +- fcpvi0: fcp@fe9af000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe9af000 0 0x200>; +- clocks = <&cpg CPG_MOD 611>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 611>; +- iommus = <&ipmmu_vp0 8>; +- }; +- +- vspd0: vsp@fea20000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea20000 0 0x7000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 623>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 623>; +- renesas,fcp = <&fcpvd0>; +- }; +- +- fcpvd0: fcp@fea27000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea27000 0 0x200>; +- clocks = <&cpg CPG_MOD 603>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 603>; +- iommus = <&ipmmu_vi0 8>; +- }; +- +- vspd1: vsp@fea28000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea28000 0 0x7000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 622>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 622>; +- renesas,fcp = <&fcpvd1>; +- }; +- +- fcpvd1: fcp@fea2f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea2f000 0 0x200>; +- clocks = <&cpg CPG_MOD 602>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 602>; +- iommus = <&ipmmu_vi0 9>; +- }; +- +- cmm0: cmm@fea40000 { +- compatible = "renesas,r8a77990-cmm", +- "renesas,rcar-gen3-cmm"; +- reg = <0 0xfea40000 0 0x1000>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- clocks = <&cpg CPG_MOD 711>; +- resets = <&cpg 711>; +- }; +- +- cmm1: cmm@fea50000 { +- compatible = "renesas,r8a77990-cmm", +- "renesas,rcar-gen3-cmm"; +- reg = <0 0xfea50000 0 0x1000>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- clocks = <&cpg CPG_MOD 710>; +- resets = <&cpg 710>; +- }; +- +- csi40: csi2@feaa0000 { +- compatible = "renesas,r8a77990-csi2"; +- reg = <0 0xfeaa0000 0 0x10000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 716>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- }; +- +- port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <1>; +- +- csi40vin4: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vin4csi40>; +- }; +- csi40vin5: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vin5csi40>; +- }; +- }; +- }; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a77990"; +- reg = <0 0xfeb00000 0 0x40000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; +- clock-names = "du.0", "du.1"; +- resets = <&cpg 724>; +- reset-names = "du.0"; +- +- renesas,cmms = <&cmm0>, <&cmm1>; +- renesas,vsps = <&vspd0 0>, <&vspd1 0>; +- +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb: endpoint { +- }; +- }; +- +- port@1 { +- reg = <1>; +- du_out_lvds0: endpoint { +- remote-endpoint = <&lvds0_in>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- du_out_lvds1: endpoint { +- remote-endpoint = <&lvds1_in>; +- }; +- }; +- }; +- }; +- +- lvds0: lvds-encoder@feb90000 { +- compatible = "renesas,r8a77990-lvds"; +- reg = <0 0xfeb90000 0 0x20>; +- clocks = <&cpg CPG_MOD 727>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 727>; +- status = "disabled"; +- +- renesas,companion = <&lvds1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds0_in: endpoint { +- remote-endpoint = <&du_out_lvds0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- lvds0_out: endpoint { +- }; +- }; +- }; +- }; +- +- lvds1: lvds-encoder@feb90100 { +- compatible = "renesas,r8a77990-lvds"; +- reg = <0 0xfeb90100 0 0x20>; +- clocks = <&cpg CPG_MOD 727>; +- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; +- resets = <&cpg 726>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds1_in: endpoint { +- remote-endpoint = <&du_out_lvds1>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- lvds1_out: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@fff00044 { +- compatible = "renesas,prr"; +- reg = <0 0xfff00044 0 4>; +- }; +- }; +- +- thermal-zones { +- cpu-thermal { +- polling-delay-passive = <250>; +- polling-delay = <0>; +- thermal-sensors = <&thermal 0>; +- sustainable-power = <717>; +- +- cooling-maps { +- map0 { +- trip = <&target>; +- cooling-device = <&a53_0 0 2>; +- contribution = <1024>; +- }; +- }; +- +- trips { +- sensor1_crit: sensor1-crit { +- temperature = <120000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- +- target: trip-point1 { +- temperature = <100000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77995-draak.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a77995-draak.dts +deleted file mode 100644 +index 1ac15aa05b82..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77995-draak.dts ++++ /dev/null +@@ -1,685 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Draak board with R-Car D3 +- * +- * Copyright (C) 2016-2018 Renesas Electronics Corp. +- * Copyright (C) 2017 Glider bvba +- */ +- +-/dts-v1/; +-#include "r8a77995.dtsi" +-#include +-#include +- +-/ { +- model = "Renesas Draak board based on r8a77995"; +- compatible = "renesas,draak", "renesas,r8a77995"; +- +- aliases { +- serial0 = &scif2; +- ethernet0 = &avb; +- }; +- +- audio_clkout: audio-clkout { +- /* +- * This is same as <&rcar_sound 0> +- * but needed to avoid cs2000/rcar_sound probe dead-lock +- */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <12288000>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 50000>; +- +- brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>; +- default-brightness-level = <10>; +- +- power-supply = <®_12p0v>; +- enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- composite-in { +- compatible = "composite-video-connector"; +- +- port { +- composite_con_in: endpoint { +- remote-endpoint = <&adv7180_in>; +- }; +- }; +- }; +- +- hdmi-in { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&adv7612_in>; +- }; +- }; +- }; +- +- hdmi-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_out: endpoint { +- remote-endpoint = <&adv7511_out>; +- }; +- }; +- }; +- +- keys { +- compatible = "gpio-keys"; +- +- pinctrl-0 = <&keys_pins>; +- pinctrl-names = "default"; +- +- key-1 { +- gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW56-1"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-2 { +- gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW56-2"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-3 { +- gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW56-3"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-4 { +- gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW56-4"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- }; +- +- lvds-decoder { +- compatible = "thine,thc63lvd1024"; +- vcc-supply = <®_3p3v>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- thc63lvd1024_in: endpoint { +- remote-endpoint = <&lvds0_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- thc63lvd1024_out: endpoint { +- remote-endpoint = <&adv7511_in>; +- }; +- }; +- }; +- }; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x18000000>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_12p0v: regulator-12p0v { +- compatible = "regulator-fixed"; +- regulator-name = "D12.0V"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sound_card: sound { +- compatible = "audio-graph-card"; +- +- dais = <&rsnd_port0 /* ak4613 */ +- /* HDMI is not yet supported */ +- >; +- }; +- +- vga { +- compatible = "vga-connector"; +- +- port { +- vga_in: endpoint { +- remote-endpoint = <&adv7123_out>; +- }; +- }; +- }; +- +- vga-encoder { +- compatible = "adi,adv7123"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7123_in: endpoint { +- remote-endpoint = <&du_out_rgb>; +- }; +- }; +- port@1 { +- reg = <1>; +- adv7123_out: endpoint { +- remote-endpoint = <&vga_in>; +- }; +- }; +- }; +- }; +- +- x12_clk: x12 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <74250000>; +- }; +- +- x19_clk: x19 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +-}; +- +-&audio_clk_b { +- /* +- * X11 is connected to VI4_FIELD/SCIF_CLK/AUDIO_CLKB, +- * and R-Car Sound uses AUDIO_CLKB. +- * Note is that schematic indicates VI4_FIELD conection only +- * not AUDIO_CLKB at SoC page. +- * And this VI4_FIELD/SCIF_CLK/AUDIO_CLKB is connected to SW60. +- * SW60 should be 1-2. +- */ +- +- clock-frequency = <22579200>; +-}; +- +-&avb { +- pinctrl-0 = <&avb0_pins>; +- pinctrl-names = "default"; +- renesas,no-ether-link; +- phy-handle = <&phy0>; +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- rxc-skew-ps = <1500>; +- reg = <0>; +- interrupt-parent = <&gpio5>; +- interrupts = <19 IRQ_TYPE_LEVEL_LOW>; +- /* +- * TX clock internal delay mode is required for reliable +- * 1Gbps communication using the KSZ9031RNX phy present on +- * the Draak board, however, TX clock internal delay mode +- * isn't supported on r8a77995. Thus, limit speed to +- * 100Mbps for reliable communication. +- */ +- max-speed = <100>; +- }; +-}; +- +-&can0 { +- pinctrl-0 = <&can0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-0 = <&can1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&du { +- pinctrl-0 = <&du_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&x12_clk>; +- clock-names = "du.0", "du.1", "dclkin.0"; +- +- ports { +- port@0 { +- endpoint { +- remote-endpoint = <&adv7123_in>; +- }; +- }; +- }; +-}; +- +-&ehci0 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&extal_clk { +- clock-frequency = <48000000>; +-}; +- +-&hsusb { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- ak4613: codec@10 { +- compatible = "asahi-kasei,ak4613"; +- #sound-dai-cells = <0>; +- reg = <0x10>; +- clocks = <&rcar_sound 0>; /* audio_clkout */ +- +- asahi-kasei,in1-single-end; +- asahi-kasei,in2-single-end; +- asahi-kasei,out1-single-end; +- asahi-kasei,out2-single-end; +- asahi-kasei,out3-single-end; +- asahi-kasei,out4-single-end; +- asahi-kasei,out5-single-end; +- asahi-kasei,out6-single-end; +- +- port { +- ak4613_endpoint: endpoint { +- remote-endpoint = <&rsnd_for_ak4613>; +- }; +- }; +- }; +- +- composite-in@20 { +- compatible = "adi,adv7180cp"; +- reg = <0x20>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7180_in: endpoint { +- remote-endpoint = <&composite_con_in>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- +- /* +- * The VIN4 video input path is shared between +- * CVBS and HDMI inputs through SW[49-53] +- * switches. +- * +- * CVBS is the default selection, link it to +- * VIN4 here. +- */ +- adv7180_out: endpoint { +- remote-endpoint = <&vin4_in>; +- }; +- }; +- }; +- +- }; +- +- hdmi-encoder@39 { +- compatible = "adi,adv7511w"; +- reg = <0x39>, <0x3f>, <0x3c>, <0x38>; +- reg-names = "main", "edid", "cec", "packet"; +- interrupt-parent = <&gpio1>; +- interrupts = <28 IRQ_TYPE_LEVEL_LOW>; +- +- adi,input-depth = <8>; +- adi,input-colorspace = "rgb"; +- adi,input-clock = "1x"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7511_in: endpoint { +- remote-endpoint = <&thc63lvd1024_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- adv7511_out: endpoint { +- remote-endpoint = <&hdmi_con_out>; +- }; +- }; +- }; +- }; +- +- hdmi-decoder@4c { +- compatible = "adi,adv7612"; +- reg = <0x4c>; +- default-input = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- adv7612_in: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- +- /* +- * The VIN4 video input path is shared between +- * CVBS and HDMI inputs through SW[49-53] +- * switches. +- * +- * CVBS is the default selection, leave HDMI +- * not connected here. +- */ +- adv7612_out: endpoint { +- pclk-sample = <0>; +- hsync-active = <0>; +- vsync-active = <0>; +- }; +- }; +- }; +- }; +- +- cs2000: clk-multiplier@4f { +- #clock-cells = <0>; +- compatible = "cirrus,cs2000-cp"; +- reg = <0x4f>; +- clocks = <&audio_clkout>, <&x19_clk>; /* audio_clkout_1, x19 */ +- clock-names = "clk_in", "ref_clk"; +- +- assigned-clocks = <&cs2000>; +- assigned-clock-rates = <24576000>; /* 1/1 divide */ +- }; +- +- eeprom@50 { +- compatible = "rohm,br24t01", "atmel,24c01"; +- reg = <0x50>; +- pagesize = <8>; +- }; +-}; +- +-&i2c1 { +- pinctrl-0 = <&i2c1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&lvds0 { +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 727>, +- <&x12_clk>, +- <&extal_clk>; +- clock-names = "fck", "dclkin.0", "extal"; +- +- ports { +- port@1 { +- lvds0_out: endpoint { +- remote-endpoint = <&thc63lvd1024_in>; +- }; +- }; +- }; +-}; +- +-&lvds1 { +- /* +- * Even though the LVDS1 output is not connected, the encoder must be +- * enabled to supply a pixel clock to the DU for the DPAD output when +- * LVDS0 is in use. +- */ +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 727>, +- <&x12_clk>, +- <&extal_clk>; +- clock-names = "fck", "dclkin.0", "extal"; +-}; +- +-&ohci0 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&pfc { +- avb0_pins: avb { +- groups = "avb0_link", "avb0_mdio", "avb0_mii"; +- function = "avb0"; +- }; +- +- can0_pins: can0 { +- groups = "can0_data_a"; +- function = "can0"; +- }; +- +- can1_pins: can1 { +- groups = "can1_data_a"; +- function = "can1"; +- }; +- +- du_pins: du { +- groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; +- function = "du"; +- }; +- +- i2c0_pins: i2c0 { +- groups = "i2c0"; +- function = "i2c0"; +- }; +- +- i2c1_pins: i2c1 { +- groups = "i2c1"; +- function = "i2c1"; +- }; +- +- keys_pins: keys { +- pins = "GP_4_12", "GP_4_13", "GP_4_14", "GP_4_15"; +- bias-pull-up; +- }; +- +- pwm0_pins: pwm0 { +- groups = "pwm0_c"; +- function = "pwm0"; +- }; +- +- pwm1_pins: pwm1 { +- groups = "pwm1_c"; +- function = "pwm1"; +- }; +- +- scif2_pins: scif2 { +- groups = "scif2_data"; +- function = "scif2"; +- }; +- +- sdhi2_pins: sd2 { +- groups = "mmc_data8", "mmc_ctrl"; +- function = "mmc"; +- power-source = <1800>; +- }; +- +- sdhi2_pins_uhs: sd2_uhs { +- groups = "mmc_data8", "mmc_ctrl"; +- function = "mmc"; +- power-source = <1800>; +- }; +- +- sound_pins: sound { +- groups = "ssi34_ctrl", "ssi3_data", "ssi4_data_a"; +- function = "ssi"; +- }; +- +- sound_clk_pins: sound-clk { +- groups = "audio_clk_a", "audio_clk_b", +- "audio_clkout", "audio_clkout1"; +- function = "audio_clk"; +- }; +- +- usb0_pins: usb0 { +- groups = "usb0"; +- function = "usb0"; +- }; +- +- vin4_pins_cvbs: vin4 { +- groups = "vin4_data8", "vin4_sync", "vin4_clk"; +- function = "vin4"; +- }; +-}; +- +-&pwm0 { +- pinctrl-0 = <&pwm0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&pwm1 { +- pinctrl-0 = <&pwm1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&rcar_sound { +- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; +- pinctrl-names = "default"; +- +- /* Single DAI */ +- #sound-dai-cells = <0>; +- +- /* audio_clkout0/1 */ +- #clock-cells = <1>; +- clock-frequency = <12288000 11289600>; +- +- status = "okay"; +- +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>, +- <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&cs2000>, <&audio_clk_b>, +- <&cpg CPG_CORE R8A77995_CLK_ZA2>; +- +- ports { +- rsnd_port0: port { +- rsnd_for_ak4613: endpoint { +- remote-endpoint = <&ak4613_endpoint>; +- dai-format = "left_j"; +- bitclock-master = <&rsnd_for_ak4613>; +- frame-master = <&rsnd_for_ak4613>; +- playback = <&ssi3>, <&src5>, <&dvc0>; +- capture = <&ssi4>, <&src6>, <&dvc1>; +- }; +- }; +- }; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&scif2 { +- pinctrl-0 = <&scif2_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&sdhi2 { +- /* used for on-board eMMC */ +- pinctrl-0 = <&sdhi2_pins>; +- pinctrl-1 = <&sdhi2_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_1p8v>; +- bus-width = <8>; +- mmc-hs200-1_8v; +- no-sd; +- no-sdio; +- non-removable; +- status = "okay"; +-}; +- +-&ssi4 { +- shared-pin; +-}; +- +-&usb2_phy0 { +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +- +- renesas,no-otg-pins; +- status = "okay"; +-}; +- +-&vin4 { +- pinctrl-0 = <&vin4_pins_cvbs>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- ports { +- port { +- vin4_in: endpoint { +- remote-endpoint = <&adv7180_out>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a77995.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r8a77995.dtsi +deleted file mode 100644 +index 16ad5fc23a67..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a77995.dtsi ++++ /dev/null +@@ -1,1448 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Car D3 (R8A77995) SoC +- * +- * Copyright (C) 2016 Renesas Electronics Corp. +- * Copyright (C) 2017 Glider bvba +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r8a77995"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- /* +- * The external audio clocks are configured as 0 Hz fixed frequency +- * clocks by default. +- * Boards that provide audio clocks should override them. +- */ +- audio_clk_a: audio_clk_a { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- audio_clk_b: audio_clk_b { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* External CAN clock - to be overridden by boards that provide it */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- a53_0: cpu@0 { +- compatible = "arm,cortex-a53"; +- reg = <0x0>; +- device_type = "cpu"; +- power-domains = <&sysc R8A77995_PD_CA53_CPU0>; +- next-level-cache = <&L2_CA53>; +- enable-method = "psci"; +- }; +- +- L2_CA53: cache-controller-1 { +- compatible = "cache"; +- power-domains = <&sysc R8A77995_PD_CA53_SCU>; +- cache-unified; +- cache-level = <2>; +- }; +- }; +- +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- pmu_a53 { +- compatible = "arm,cortex-a53-pmu"; +- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- psci { +- compatible = "arm,psci-1.0", "arm,psci-0.2"; +- method = "smc"; +- }; +- +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a77995-wdt", +- "renesas,rcar-gen3-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 402>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 402>; +- status = "disabled"; +- }; +- +- gpio0: gpio@e6050000 { +- compatible = "renesas,gpio-r8a77995", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6050000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 0 9>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 912>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- }; +- +- gpio1: gpio@e6051000 { +- compatible = "renesas,gpio-r8a77995", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6051000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 32 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 911>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- }; +- +- gpio2: gpio@e6052000 { +- compatible = "renesas,gpio-r8a77995", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6052000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 64 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 910>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- }; +- +- gpio3: gpio@e6053000 { +- compatible = "renesas,gpio-r8a77995", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6053000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 96 10>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 909>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 909>; +- }; +- +- gpio4: gpio@e6054000 { +- compatible = "renesas,gpio-r8a77995", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6054000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 128 32>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 908>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 908>; +- }; +- +- gpio5: gpio@e6055000 { +- compatible = "renesas,gpio-r8a77995", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055000 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 160 21>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- }; +- +- gpio6: gpio@e6055400 { +- compatible = "renesas,gpio-r8a77995", +- "renesas,rcar-gen3-gpio"; +- reg = <0 0xe6055400 0 0x50>; +- interrupts = ; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-ranges = <&pfc 0 192 14>; +- #interrupt-cells = <2>; +- interrupt-controller; +- clocks = <&cpg CPG_MOD 906>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 906>; +- }; +- +- pfc: pinctrl@e6060000 { +- compatible = "renesas,pfc-r8a77995"; +- reg = <0 0xe6060000 0 0x508>; +- }; +- +- cmt0: timer@e60f0000 { +- compatible = "renesas,r8a77995-cmt0", +- "renesas,rcar-gen3-cmt0"; +- reg = <0 0xe60f0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 303>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 303>; +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a77995-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 302>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 302>; +- status = "disabled"; +- }; +- +- cmt2: timer@e6140000 { +- compatible = "renesas,r8a77995-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6140000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 301>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 301>; +- status = "disabled"; +- }; +- +- cmt3: timer@e6148000 { +- compatible = "renesas,r8a77995-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6148000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 300>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 300>; +- status = "disabled"; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a77995-cpg-mssr"; +- reg = <0 0xe6150000 0 0x1000>; +- clocks = <&extal_clk>; +- clock-names = "extal"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a77995-rst"; +- reg = <0 0xe6160000 0 0x0200>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a77995-sysc"; +- reg = <0 0xe6180000 0 0x0400>; +- #power-domain-cells = <1>; +- }; +- +- thermal: thermal@e6190000 { +- compatible = "renesas,thermal-r8a77995"; +- reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 522>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 522>; +- #thermal-sensor-cells = <0>; +- }; +- +- intc_ex: interrupt-controller@e61c0000 { +- compatible = "renesas,intc-ex-r8a77995", "renesas,irqc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0 0xe61c0000 0 0x200>; +- interrupts = , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 407>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 407>; +- }; +- +- tmu0: timer@e61e0000 { +- compatible = "renesas,tmu-r8a77995", "renesas,tmu"; +- reg = <0 0xe61e0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 125>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 125>; +- status = "disabled"; +- }; +- +- tmu1: timer@e6fc0000 { +- compatible = "renesas,tmu-r8a77995", "renesas,tmu"; +- reg = <0 0xe6fc0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 124>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 124>; +- status = "disabled"; +- }; +- +- tmu2: timer@e6fd0000 { +- compatible = "renesas,tmu-r8a77995", "renesas,tmu"; +- reg = <0 0xe6fd0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 123>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 123>; +- status = "disabled"; +- }; +- +- tmu3: timer@e6fe0000 { +- compatible = "renesas,tmu-r8a77995", "renesas,tmu"; +- reg = <0 0xe6fe0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 122>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 122>; +- status = "disabled"; +- }; +- +- tmu4: timer@ffc00000 { +- compatible = "renesas,tmu-r8a77995", "renesas,tmu"; +- reg = <0 0xffc00000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 121>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 121>; +- status = "disabled"; +- }; +- +- i2c0: i2c@e6500000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77995", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6500000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 931>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 931>; +- dmas = <&dmac1 0x91>, <&dmac1 0x90>, +- <&dmac2 0x91>, <&dmac2 0x90>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6508000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77995", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 930>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 930>; +- dmas = <&dmac1 0x93>, <&dmac1 0x92>, +- <&dmac2 0x93>, <&dmac2 0x92>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6510000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77995", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6510000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 929>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 929>; +- dmas = <&dmac1 0x95>, <&dmac1 0x94>, +- <&dmac2 0x95>, <&dmac2 0x94>; +- dma-names = "tx", "rx", "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e66d0000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,i2c-r8a77995", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 928>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 928>; +- dmas = <&dmac0 0x97>, <&dmac0 0x96>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <6>; +- status = "disabled"; +- }; +- +- hscif0: serial@e6540000 { +- compatible = "renesas,hscif-r8a77995", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe6540000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 520>, +- <&cpg CPG_CORE R8A77995_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x31>, <&dmac1 0x30>, +- <&dmac2 0x31>, <&dmac2 0x30>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 520>; +- status = "disabled"; +- }; +- +- hscif3: serial@e66a0000 { +- compatible = "renesas,hscif-r8a77995", +- "renesas,rcar-gen3-hscif", +- "renesas,hscif"; +- reg = <0 0xe66a0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 517>, +- <&cpg CPG_CORE R8A77995_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x37>, <&dmac0 0x36>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 517>; +- status = "disabled"; +- }; +- +- hsusb: usb@e6590000 { +- compatible = "renesas,usbhs-r8a77995", +- "renesas,rcar-gen3-usbhs"; +- reg = <0 0xe6590000 0 0x200>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; +- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, +- <&usb_dmac1 0>, <&usb_dmac1 1>; +- dma-names = "ch0", "ch1", "ch2", "ch3"; +- renesas,buswait = <11>; +- phys = <&usb2_phy0 3>; +- phy-names = "usb"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 704>, <&cpg 703>; +- status = "disabled"; +- }; +- +- usb_dmac0: dma-controller@e65a0000 { +- compatible = "renesas,r8a77995-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65a0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 330>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 330>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- usb_dmac1: dma-controller@e65b0000 { +- compatible = "renesas,r8a77995-usb-dmac", +- "renesas,usb-dmac"; +- reg = <0 0xe65b0000 0 0x100>; +- interrupts = , +- ; +- interrupt-names = "ch0", "ch1"; +- clocks = <&cpg CPG_MOD 331>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 331>; +- #dma-cells = <1>; +- dma-channels = <2>; +- }; +- +- arm_cc630p: crypto@e6601000 { +- compatible = "arm,cryptocell-630p-ree"; +- interrupts = ; +- reg = <0x0 0xe6601000 0 0x1000>; +- clocks = <&cpg CPG_MOD 229>; +- resets = <&cpg 229>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- }; +- +- canfd: can@e66c0000 { +- compatible = "renesas,r8a77995-canfd", +- "renesas,rcar-gen3-canfd"; +- reg = <0 0xe66c0000 0 0x8000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 914>, +- <&cpg CPG_CORE R8A77995_CLK_CANFD>, +- <&can_clk>; +- clock-names = "fck", "canfd", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 914>; +- status = "disabled"; +- +- channel0 { +- status = "disabled"; +- }; +- +- channel1 { +- status = "disabled"; +- }; +- }; +- +- dmac0: dma-controller@e6700000 { +- compatible = "renesas,dmac-r8a77995", +- "renesas,rcar-dmac"; +- reg = <0 0xe6700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7"; +- clocks = <&cpg CPG_MOD 219>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 219>; +- #dma-cells = <1>; +- dma-channels = <8>; +- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, +- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, +- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, +- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>; +- }; +- +- dmac1: dma-controller@e7300000 { +- compatible = "renesas,dmac-r8a77995", +- "renesas,rcar-dmac"; +- reg = <0 0xe7300000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7"; +- clocks = <&cpg CPG_MOD 218>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 218>; +- #dma-cells = <1>; +- dma-channels = <8>; +- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, +- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, +- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, +- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; +- }; +- +- dmac2: dma-controller@e7310000 { +- compatible = "renesas,dmac-r8a77995", +- "renesas,rcar-dmac"; +- reg = <0 0xe7310000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7"; +- clocks = <&cpg CPG_MOD 217>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 217>; +- #dma-cells = <1>; +- dma-channels = <8>; +- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, +- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, +- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, +- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; +- }; +- +- ipmmu_ds0: iommu@e6740000 { +- compatible = "renesas,ipmmu-r8a77995"; +- reg = <0 0xe6740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 0>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_ds1: iommu@e7740000 { +- compatible = "renesas,ipmmu-r8a77995"; +- reg = <0 0xe7740000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 1>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_hc: iommu@e6570000 { +- compatible = "renesas,ipmmu-r8a77995"; +- reg = <0 0xe6570000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 2>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mm: iommu@e67b0000 { +- compatible = "renesas,ipmmu-r8a77995"; +- reg = <0 0xe67b0000 0 0x1000>; +- interrupts = , +- ; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_mp: iommu@ec670000 { +- compatible = "renesas,ipmmu-r8a77995"; +- reg = <0 0xec670000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 4>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_pv0: iommu@fd800000 { +- compatible = "renesas,ipmmu-r8a77995"; +- reg = <0 0xfd800000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 6>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_rt: iommu@ffc80000 { +- compatible = "renesas,ipmmu-r8a77995"; +- reg = <0 0xffc80000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 10>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vc0: iommu@fe6b0000 { +- compatible = "renesas,ipmmu-r8a77995"; +- reg = <0 0xfe6b0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 12>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vi0: iommu@febd0000 { +- compatible = "renesas,ipmmu-r8a77995"; +- reg = <0 0xfebd0000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 14>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- ipmmu_vp0: iommu@fe990000 { +- compatible = "renesas,ipmmu-r8a77995"; +- reg = <0 0xfe990000 0 0x1000>; +- renesas,ipmmu-main = <&ipmmu_mm 16>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- #iommu-cells = <1>; +- }; +- +- avb: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a77995", +- "renesas,etheravb-rcar-gen3"; +- reg = <0 0xe6800000 0 0x800>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15", +- "ch16", "ch17", "ch18", "ch19", +- "ch20", "ch21", "ch22", "ch23", +- "ch24"; +- clocks = <&cpg CPG_MOD 812>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 812>; +- phy-mode = "rgmii"; +- rx-internal-delay-ps = <1800>; +- iommus = <&ipmmu_ds0 16>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- can0: can@e6c30000 { +- compatible = "renesas,can-r8a77995", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c30000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>, +- <&cpg CPG_CORE R8A77995_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- status = "disabled"; +- }; +- +- can1: can@e6c38000 { +- compatible = "renesas,can-r8a77995", +- "renesas,rcar-gen3-can"; +- reg = <0 0xe6c38000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>, +- <&cpg CPG_CORE R8A77995_CLK_CANFD>, +- <&can_clk>; +- clock-names = "clkp1", "clkp2", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; +- assigned-clock-rates = <40000000>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- status = "disabled"; +- }; +- +- pwm0: pwm@e6e30000 { +- compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; +- reg = <0 0xe6e30000 0 0x8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- status = "disabled"; +- }; +- +- pwm1: pwm@e6e31000 { +- compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; +- reg = <0 0xe6e31000 0 0x8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- status = "disabled"; +- }; +- +- pwm2: pwm@e6e32000 { +- compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; +- reg = <0 0xe6e32000 0 0x8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- status = "disabled"; +- }; +- +- pwm3: pwm@e6e33000 { +- compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; +- reg = <0 0xe6e33000 0 0x8>; +- #pwm-cells = <2>; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a77995", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e60000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 207>, +- <&cpg CPG_CORE R8A77995_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x51>, <&dmac1 0x50>, +- <&dmac2 0x51>, <&dmac2 0x50>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 207>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a77995", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e68000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 206>, +- <&cpg CPG_CORE R8A77995_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x53>, <&dmac1 0x52>, +- <&dmac2 0x53>, <&dmac2 0x52>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 206>; +- status = "disabled"; +- }; +- +- scif2: serial@e6e88000 { +- compatible = "renesas,scif-r8a77995", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e88000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 310>, +- <&cpg CPG_CORE R8A77995_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x13>, <&dmac1 0x12>, +- <&dmac2 0x13>, <&dmac2 0x12>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 310>; +- status = "disabled"; +- }; +- +- scif3: serial@e6c50000 { +- compatible = "renesas,scif-r8a77995", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c50000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 204>, +- <&cpg CPG_CORE R8A77995_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x57>, <&dmac0 0x56>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 204>; +- status = "disabled"; +- }; +- +- scif4: serial@e6c40000 { +- compatible = "renesas,scif-r8a77995", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c40000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 203>, +- <&cpg CPG_CORE R8A77995_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac0 0x59>, <&dmac0 0x58>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 203>; +- status = "disabled"; +- }; +- +- scif5: serial@e6f30000 { +- compatible = "renesas,scif-r8a77995", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6f30000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 202>, +- <&cpg CPG_CORE R8A77995_CLK_S3D1C>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, +- <&dmac2 0x5b>, <&dmac2 0x5a>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 202>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e90000 { +- compatible = "renesas,msiof-r8a77995", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6e90000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 211>; +- dmas = <&dmac1 0x41>, <&dmac1 0x40>, +- <&dmac2 0x41>, <&dmac2 0x40>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 211>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6ea0000 { +- compatible = "renesas,msiof-r8a77995", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6ea0000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 210>; +- dmas = <&dmac1 0x43>, <&dmac1 0x42>, +- <&dmac2 0x43>, <&dmac2 0x42>; +- dma-names = "tx", "rx", "tx", "rx"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 210>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6c00000 { +- compatible = "renesas,msiof-r8a77995", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c00000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 209>; +- dmas = <&dmac0 0x45>, <&dmac0 0x44>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 209>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof3: spi@e6c10000 { +- compatible = "renesas,msiof-r8a77995", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c10000 0 0x64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 208>; +- dmas = <&dmac0 0x47>, <&dmac0 0x46>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 208>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- vin4: video@e6ef4000 { +- compatible = "renesas,vin-r8a77995"; +- reg = <0 0xe6ef4000 0 0x1000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 807>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 807>; +- renesas,id = <4>; +- status = "disabled"; +- }; +- +- rcar_sound: sound@ec500000 { +- /* +- * #sound-dai-cells is required +- * +- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; +- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; +- */ +- /* +- * #clock-cells is required for audio_clkout0/1/2/3 +- * +- * clkout : #clock-cells = <0>; <&rcar_sound>; +- * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; +- */ +- compatible = "renesas,rcar_sound-r8a77995", "renesas,rcar_sound-gen3"; +- reg = <0 0xec500000 0 0x1000>, /* SCU */ +- <0 0xec5a0000 0 0x100>, /* ADG */ +- <0 0xec540000 0 0x1000>, /* SSIU */ +- <0 0xec541000 0 0x280>, /* SSI */ +- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ +- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; +- +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>, +- <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&audio_clk_b>, +- <&cpg CPG_CORE R8A77995_CLK_ZA2>; +- clock-names = "ssi-all", +- "ssi.4", "ssi.3", +- "src.6", "src.5", +- "mix.1", "mix.0", +- "ctu.1", "ctu.0", +- "dvc.0", "dvc.1", +- "clk_a", "clk_b", "clk_i"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 1005>, +- <&cpg 1011>, <&cpg 1012>; +- reset-names = "ssi-all", +- "ssi.4", "ssi.3"; +- status = "disabled"; +- +- rcar_sound,ctu { +- ctu00: ctu-0 { }; +- ctu01: ctu-1 { }; +- ctu02: ctu-2 { }; +- ctu03: ctu-3 { }; +- ctu10: ctu-4 { }; +- ctu11: ctu-5 { }; +- ctu12: ctu-6 { }; +- ctu13: ctu-7 { }; +- }; +- +- rcar_sound,dvc { +- dvc0: dvc-0 { +- dmas = <&audma0 0xbc>; +- dma-names = "tx"; +- }; +- dvc1: dvc-1 { +- dmas = <&audma0 0xbe>; +- dma-names = "tx"; +- }; +- }; +- +- rcar_sound,mix { +- mix0: mix-0 { }; +- mix1: mix-1 { }; +- }; +- +- rcar_sound,src { +- src5: src-5 { +- interrupts = ; +- dmas = <&audma0 0x8f>, <&audma0 0xb2>; +- dma-names = "rx", "tx"; +- }; +- src6: src-6 { +- interrupts = ; +- dmas = <&audma0 0x91>, <&audma0 0xb4>; +- dma-names = "rx", "tx"; +- }; +- }; +- +- rcar_sound,ssi { +- ssi3: ssi-3 { +- interrupts = ; +- dmas = <&audma0 0x07>, <&audma0 0x08>, +- <&audma0 0x6f>, <&audma0 0x70>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- ssi4: ssi-4 { +- interrupts = ; +- dmas = <&audma0 0x09>, <&audma0 0x0a>, +- <&audma0 0x71>, <&audma0 0x72>; +- dma-names = "rx", "tx", "rxu", "txu"; +- }; +- }; +- }; +- +- audma0: dma-controller@ec700000 { +- compatible = "renesas,dmac-r8a77995", +- "renesas,rcar-dmac"; +- reg = <0 0xec700000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 502>; +- clock-names = "fck"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 502>; +- #dma-cells = <1>; +- dma-channels = <16>; +- iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, +- <&ipmmu_mp 2>, <&ipmmu_mp 3>, +- <&ipmmu_mp 4>, <&ipmmu_mp 5>, +- <&ipmmu_mp 6>, <&ipmmu_mp 7>, +- <&ipmmu_mp 8>, <&ipmmu_mp 9>, +- <&ipmmu_mp 10>, <&ipmmu_mp 11>, +- <&ipmmu_mp 12>, <&ipmmu_mp 13>, +- <&ipmmu_mp 14>, <&ipmmu_mp 15>; +- }; +- +- ohci0: usb@ee080000 { +- compatible = "generic-ohci"; +- reg = <0 0xee080000 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 1>; +- phy-names = "usb"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- ehci0: usb@ee080100 { +- compatible = "generic-ehci"; +- reg = <0 0xee080100 0 0x100>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- phys = <&usb2_phy0 2>; +- phy-names = "usb"; +- companion = <&ohci0>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- status = "disabled"; +- }; +- +- usb2_phy0: usb-phy@ee080200 { +- compatible = "renesas,usb2-phy-r8a77995", +- "renesas,rcar-gen3-usb2-phy"; +- reg = <0 0xee080200 0 0x700>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 703>, <&cpg 704>; +- #phy-cells = <1>; +- status = "disabled"; +- }; +- +- sdhi2: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a77995", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee140000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 312>; +- max-frequency = <200000000>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 312>; +- iommus = <&ipmmu_ds1 34>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1010000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x0 0xf1010000 0 0x1000>, +- <0x0 0xf1020000 0 0x20000>, +- <0x0 0xf1040000 0 0x20000>, +- <0x0 0xf1060000 0 0x20000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 408>; +- clock-names = "clk"; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 408>; +- }; +- +- vspbs: vsp@fe960000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfe960000 0 0x8000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 627>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 627>; +- renesas,fcp = <&fcpvb0>; +- }; +- +- vspd0: vsp@fea20000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea20000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 623>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 623>; +- renesas,fcp = <&fcpvd0>; +- }; +- +- vspd1: vsp@fea28000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea28000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 622>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 622>; +- renesas,fcp = <&fcpvd1>; +- }; +- +- fcpvb0: fcp@fe96f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfe96f000 0 0x200>; +- clocks = <&cpg CPG_MOD 607>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 607>; +- iommus = <&ipmmu_vp0 5>; +- }; +- +- fcpvd0: fcp@fea27000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea27000 0 0x200>; +- clocks = <&cpg CPG_MOD 603>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 603>; +- iommus = <&ipmmu_vi0 8>; +- }; +- +- fcpvd1: fcp@fea2f000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea2f000 0 0x200>; +- clocks = <&cpg CPG_MOD 602>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 602>; +- iommus = <&ipmmu_vi0 9>; +- }; +- +- cmm0: cmm@fea40000 { +- compatible = "renesas,r8a77995-cmm", +- "renesas,rcar-gen3-cmm"; +- reg = <0 0xfea40000 0 0x1000>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- clocks = <&cpg CPG_MOD 711>; +- resets = <&cpg 711>; +- }; +- +- cmm1: cmm@fea50000 { +- compatible = "renesas,r8a77995-cmm", +- "renesas,rcar-gen3-cmm"; +- reg = <0 0xfea50000 0 0x1000>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- clocks = <&cpg CPG_MOD 710>; +- resets = <&cpg 710>; +- }; +- +- du: display@feb00000 { +- compatible = "renesas,du-r8a77995"; +- reg = <0 0xfeb00000 0 0x40000>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; +- clock-names = "du.0", "du.1"; +- resets = <&cpg 724>; +- reset-names = "du.0"; +- +- renesas,cmms = <&cmm0>, <&cmm1>; +- renesas,vsps = <&vspd0 0>, <&vspd1 0>; +- +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- du_out_rgb: endpoint { +- }; +- }; +- +- port@1 { +- reg = <1>; +- du_out_lvds0: endpoint { +- remote-endpoint = <&lvds0_in>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- du_out_lvds1: endpoint { +- remote-endpoint = <&lvds1_in>; +- }; +- }; +- }; +- }; +- +- lvds0: lvds-encoder@feb90000 { +- compatible = "renesas,r8a77995-lvds"; +- reg = <0 0xfeb90000 0 0x20>; +- clocks = <&cpg CPG_MOD 727>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 727>; +- status = "disabled"; +- +- renesas,companion = <&lvds1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds0_in: endpoint { +- remote-endpoint = <&du_out_lvds0>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- lvds0_out: endpoint { +- }; +- }; +- }; +- }; +- +- lvds1: lvds-encoder@feb90100 { +- compatible = "renesas,r8a77995-lvds"; +- reg = <0 0xfeb90100 0 0x20>; +- clocks = <&cpg CPG_MOD 727>; +- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; +- resets = <&cpg 726>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- lvds1_in: endpoint { +- remote-endpoint = <&du_out_lvds1>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- lvds1_out: endpoint { +- }; +- }; +- }; +- }; +- +- prr: chipid@fff00044 { +- compatible = "renesas,prr"; +- reg = <0 0xfff00044 0 4>; +- }; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&thermal>; +- +- cooling-maps { +- }; +- +- trips { +- cpu-crit { +- temperature = <120000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a779a0-falcon-cpu.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r8a779a0-falcon-cpu.dtsi +deleted file mode 100644 +index a0a1a1da0d87..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a779a0-falcon-cpu.dtsi ++++ /dev/null +@@ -1,195 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Falcon CPU board +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-#include +-#include +- +-#include "r8a779a0.dtsi" +- +-/ { +- model = "Renesas Falcon CPU board"; +- compatible = "renesas,falcon-cpu", "renesas,r8a779a0"; +- +- aliases { +- serial0 = &scif0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-1 { +- gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; +- color = ; +- function = LED_FUNCTION_INDICATOR; +- function-enumerator = <1>; +- }; +- led-2 { +- gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; +- color = ; +- function = LED_FUNCTION_INDICATOR; +- function-enumerator = <2>; +- }; +- led-3 { +- gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; +- color = ; +- function = LED_FUNCTION_INDICATOR; +- function-enumerator = <3>; +- }; +- }; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x78000000>; +- }; +- +- memory@500000000 { +- device_type = "memory"; +- reg = <0x5 0x00000000 0x0 0x80000000>; +- }; +- +- memory@600000000 { +- device_type = "memory"; +- reg = <0x6 0x00000000 0x0 0x80000000>; +- }; +- +- memory@700000000 { +- device_type = "memory"; +- reg = <0x7 0x00000000 0x0 0x80000000>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&extal_clk { +- clock-frequency = <16666666>; +-}; +- +-&extalr_clk { +- clock-frequency = <32768>; +-}; +- +-&i2c0 { +- pinctrl-0 = <&i2c0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- clock-frequency = <400000>; +- +- eeprom@50 { +- compatible = "rohm,br24g01", "atmel,24c01"; +- label = "cpu-board"; +- reg = <0x50>; +- pagesize = <8>; +- }; +-}; +- +-&i2c1 { +- pinctrl-0 = <&i2c1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- clock-frequency = <400000>; +-}; +- +-&i2c6 { +- pinctrl-0 = <&i2c6_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- clock-frequency = <400000>; +-}; +- +-&mmc0 { +- pinctrl-0 = <&mmc_pins>; +- pinctrl-1 = <&mmc_pins>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_1p8v>; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- bus-width = <8>; +- no-sd; +- no-sdio; +- non-removable; +- full-pwr-cycle-in-suspend; +- status = "okay"; +-}; +- +-&pfc { +- pinctrl-0 = <&scif_clk_pins>; +- pinctrl-names = "default"; +- +- i2c0_pins: i2c0 { +- groups = "i2c0"; +- function = "i2c0"; +- }; +- +- i2c1_pins: i2c1 { +- groups = "i2c1"; +- function = "i2c1"; +- }; +- +- i2c6_pins: i2c6 { +- groups = "i2c6"; +- function = "i2c6"; +- }; +- +- mmc_pins: mmc { +- groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; +- function = "mmc"; +- power-source = <1800>; +- }; +- +- scif0_pins: scif0 { +- groups = "scif0_data", "scif0_ctrl"; +- function = "scif0"; +- }; +- +- scif_clk_pins: scif_clk { +- groups = "scif_clk"; +- function = "scif_clk"; +- }; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&scif0 { +- pinctrl-0 = <&scif0_pins>; +- pinctrl-names = "default"; +- +- uart-has-rtscts; +- status = "okay"; +-}; +- +-&scif_clk { +- clock-frequency = <24000000>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi +deleted file mode 100644 +index f791c76f1bcf..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi ++++ /dev/null +@@ -1,36 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Falcon CSI/DSI sub-board +- * +- * Copyright (C) 2021 Glider bv +- */ +- +-&i2c0 { +- pca9654_a: gpio@21 { +- compatible = "onnn,pca9654"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- pca9654_b: gpio@22 { +- compatible = "onnn,pca9654"; +- reg = <0x22>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- pca9654_c: gpio@23 { +- compatible = "onnn,pca9654"; +- reg = <0x23>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- eeprom@52 { +- compatible = "rohm,br24g01", "atmel,24c01"; +- label = "csi-dsi-sub-board-id"; +- reg = <0x52>; +- pagesize = <8>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a779a0-falcon-ethernet.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r8a779a0-falcon-ethernet.dtsi +deleted file mode 100644 +index e11bf9ace776..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a779a0-falcon-ethernet.dtsi ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Falcon Ethernet sub-board +- * +- * Copyright (C) 2021 Glider bv +- */ +- +-&i2c0 { +- eeprom@53 { +- compatible = "rohm,br24g01", "atmel,24c01"; +- label = "ethernet-sub-board-id"; +- reg = <0x53>; +- pagesize = <8>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a779a0-falcon.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a779a0-falcon.dts +deleted file mode 100644 +index dc671ff57ec7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a779a0-falcon.dts ++++ /dev/null +@@ -1,66 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Falcon CPU and BreakOut boards with R-Car V3U +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a779a0-falcon-cpu.dtsi" +-#include "r8a779a0-falcon-csi-dsi.dtsi" +-#include "r8a779a0-falcon-ethernet.dtsi" +- +-/ { +- model = "Renesas Falcon CPU and Breakout boards based on r8a779a0"; +- compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0"; +- +- aliases { +- ethernet0 = &avb0; +- }; +-}; +- +-&avb0 { +- pinctrl-0 = <&avb0_pins>; +- pinctrl-names = "default"; +- phy-handle = <&phy0>; +- tx-internal-delay-ps = <2000>; +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- rxc-skew-ps = <1500>; +- reg = <0>; +- interrupt-parent = <&gpio4>; +- interrupts = <16 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&i2c0 { +- eeprom@51 { +- compatible = "rohm,br24g01", "atmel,24c01"; +- label = "breakout-board"; +- reg = <0x51>; +- pagesize = <8>; +- }; +-}; +- +-&pfc { +- avb0_pins: avb0 { +- mux { +- groups = "avb0_link", "avb0_mdio", "avb0_rgmii", +- "avb0_txcrefclk"; +- function = "avb0"; +- }; +- +- pins_mdio { +- groups = "avb0_mdio"; +- drive-strength = <21>; +- }; +- +- pins_mii { +- groups = "avb0_rgmii"; +- drive-strength = <21>; +- }; +- +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a779a0.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r8a779a0.dtsi +deleted file mode 100644 +index 26899fb768a7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a779a0.dtsi ++++ /dev/null +@@ -1,1230 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Car V3U (R8A779A0) SoC +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "renesas,r8a779a0"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- a76_0: cpu@0 { +- compatible = "arm,cortex-a76"; +- reg = <0>; +- device_type = "cpu"; +- power-domains = <&sysc R8A779A0_PD_A1E0D0C0>; +- next-level-cache = <&L3_CA76_0>; +- }; +- +- L3_CA76_0: cache-controller-0 { +- compatible = "cache"; +- power-domains = <&sysc R8A779A0_PD_A2E0D0>; +- cache-unified; +- cache-level = <3>; +- }; +- }; +- +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- extalr_clk: extalr { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- pmu_a76 { +- compatible = "arm,cortex-a76-pmu"; +- interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; +- }; +- +- /* External SCIF clock - to be overridden by boards that provide it */ +- scif_clk: scif { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- soc: soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- rwdt: watchdog@e6020000 { +- compatible = "renesas,r8a779a0-wdt", +- "renesas,rcar-gen3-wdt"; +- reg = <0 0xe6020000 0 0x0c>; +- clocks = <&cpg CPG_MOD 907>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 907>; +- status = "disabled"; +- }; +- +- pfc: pin-controller@e6050000 { +- compatible = "renesas,pfc-r8a779a0"; +- reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, +- <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, +- <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, +- <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>, +- <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>; +- }; +- +- gpio0: gpio@e6058180 { +- compatible = "renesas,gpio-r8a779a0"; +- reg = <0 0xe6058180 0 0x54>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pfc 0 0 28>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio@e6050180 { +- compatible = "renesas,gpio-r8a779a0"; +- reg = <0 0xe6050180 0 0x54>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pfc 0 32 31>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@e6050980 { +- compatible = "renesas,gpio-r8a779a0"; +- reg = <0 0xe6050980 0 0x54>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 915>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 915>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pfc 0 64 25>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio@e6058980 { +- compatible = "renesas,gpio-r8a779a0"; +- reg = <0 0xe6058980 0 0x54>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 916>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 916>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pfc 0 96 17>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio4: gpio@e6060180 { +- compatible = "renesas,gpio-r8a779a0"; +- reg = <0 0xe6060180 0 0x54>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 917>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 917>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pfc 0 128 27>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio5: gpio@e6060980 { +- compatible = "renesas,gpio-r8a779a0"; +- reg = <0 0xe6060980 0 0x54>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 917>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 917>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pfc 0 160 21>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio6: gpio@e6068180 { +- compatible = "renesas,gpio-r8a779a0"; +- reg = <0 0xe6068180 0 0x54>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 918>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 918>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pfc 0 192 21>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio7: gpio@e6068980 { +- compatible = "renesas,gpio-r8a779a0"; +- reg = <0 0xe6068980 0 0x54>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 918>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 918>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pfc 0 224 21>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio8: gpio@e6069180 { +- compatible = "renesas,gpio-r8a779a0"; +- reg = <0 0xe6069180 0 0x54>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 918>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 918>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pfc 0 256 21>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio9: gpio@e6069980 { +- compatible = "renesas,gpio-r8a779a0"; +- reg = <0 0xe6069980 0 0x54>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 918>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 918>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pfc 0 288 21>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- cmt0: timer@e60f0000 { +- compatible = "renesas,r8a779a0-cmt0", +- "renesas,rcar-gen3-cmt0"; +- reg = <0 0xe60f0000 0 0x1004>; +- interrupts = , +- ; +- clocks = <&cpg CPG_MOD 910>; +- clock-names = "fck"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 910>; +- status = "disabled"; +- }; +- +- cmt1: timer@e6130000 { +- compatible = "renesas,r8a779a0-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6130000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 911>; +- clock-names = "fck"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 911>; +- status = "disabled"; +- }; +- +- cmt2: timer@e6140000 { +- compatible = "renesas,r8a779a0-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6140000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 912>; +- clock-names = "fck"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 912>; +- status = "disabled"; +- }; +- +- cmt3: timer@e6148000 { +- compatible = "renesas,r8a779a0-cmt1", +- "renesas,rcar-gen3-cmt1"; +- reg = <0 0xe6148000 0 0x1004>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cpg CPG_MOD 913>; +- clock-names = "fck"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 913>; +- status = "disabled"; +- }; +- +- cpg: clock-controller@e6150000 { +- compatible = "renesas,r8a779a0-cpg-mssr"; +- reg = <0 0xe6150000 0 0x4000>; +- clocks = <&extal_clk>, <&extalr_clk>; +- clock-names = "extal", "extalr"; +- #clock-cells = <2>; +- #power-domain-cells = <0>; +- #reset-cells = <1>; +- }; +- +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a779a0-rst"; +- reg = <0 0xe6160000 0 0x4000>; +- }; +- +- sysc: system-controller@e6180000 { +- compatible = "renesas,r8a779a0-sysc"; +- reg = <0 0xe6180000 0 0x4000>; +- #power-domain-cells = <1>; +- }; +- +- tsc: thermal@e6190000 { +- compatible = "renesas,r8a779a0-thermal"; +- reg = <0 0xe6190000 0 0x200>, +- <0 0xe6198000 0 0x200>, +- <0 0xe61a0000 0 0x200>, +- <0 0xe61a8000 0 0x200>, +- <0 0xe61b0000 0 0x200>; +- clocks = <&cpg CPG_MOD 919>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 919>; +- #thermal-sensor-cells = <1>; +- }; +- +- tmu0: timer@e61e0000 { +- compatible = "renesas,tmu-r8a779a0", "renesas,tmu"; +- reg = <0 0xe61e0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 713>; +- clock-names = "fck"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 713>; +- status = "disabled"; +- }; +- +- tmu1: timer@e6fc0000 { +- compatible = "renesas,tmu-r8a779a0", "renesas,tmu"; +- reg = <0 0xe6fc0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 714>; +- clock-names = "fck"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 714>; +- status = "disabled"; +- }; +- +- tmu2: timer@e6fd0000 { +- compatible = "renesas,tmu-r8a779a0", "renesas,tmu"; +- reg = <0 0xe6fd0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 715>; +- clock-names = "fck"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 715>; +- status = "disabled"; +- }; +- +- tmu3: timer@e6fe0000 { +- compatible = "renesas,tmu-r8a779a0", "renesas,tmu"; +- reg = <0 0xe6fe0000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 716>; +- clock-names = "fck"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 716>; +- status = "disabled"; +- }; +- +- tmu4: timer@ffc00000 { +- compatible = "renesas,tmu-r8a779a0", "renesas,tmu"; +- reg = <0 0xffc00000 0 0x30>; +- interrupts = , +- , +- ; +- clocks = <&cpg CPG_MOD 717>; +- clock-names = "fck"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 717>; +- status = "disabled"; +- }; +- +- i2c0: i2c@e6500000 { +- compatible = "renesas,i2c-r8a779a0", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6500000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 518>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 518>; +- dmas = <&dmac1 0x91>, <&dmac1 0x90>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@e6508000 { +- compatible = "renesas,i2c-r8a779a0", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6508000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 519>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 519>; +- dmas = <&dmac1 0x93>, <&dmac1 0x92>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@e6510000 { +- compatible = "renesas,i2c-r8a779a0", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe6510000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 520>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 520>; +- dmas = <&dmac1 0x95>, <&dmac1 0x94>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@e66d0000 { +- compatible = "renesas,i2c-r8a779a0", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 521>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 521>; +- dmas = <&dmac1 0x97>, <&dmac1 0x96>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@e66d8000 { +- compatible = "renesas,i2c-r8a779a0", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66d8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 522>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 522>; +- dmas = <&dmac1 0x99>, <&dmac1 0x98>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c5: i2c@e66e0000 { +- compatible = "renesas,i2c-r8a779a0", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e0000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 523>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 523>; +- dmas = <&dmac1 0x9b>, <&dmac1 0x9a>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c6: i2c@e66e8000 { +- compatible = "renesas,i2c-r8a779a0", +- "renesas,rcar-gen3-i2c"; +- reg = <0 0xe66e8000 0 0x40>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 524>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 524>; +- dmas = <&dmac1 0x9d>, <&dmac1 0x9c>; +- dma-names = "tx", "rx"; +- i2c-scl-internal-delay-ns = <110>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- hscif0: serial@e6540000 { +- compatible = "renesas,hscif-r8a779a0", +- "renesas,rcar-gen3-hscif", "renesas,hscif"; +- reg = <0 0xe6540000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 514>, +- <&cpg CPG_CORE R8A779A0_CLK_S1D2>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x31>, <&dmac1 0x30>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 514>; +- status = "disabled"; +- }; +- +- hscif1: serial@e6550000 { +- compatible = "renesas,hscif-r8a779a0", +- "renesas,rcar-gen3-hscif", "renesas,hscif"; +- reg = <0 0xe6550000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 515>, +- <&cpg CPG_CORE R8A779A0_CLK_S1D2>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x33>, <&dmac1 0x32>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 515>; +- status = "disabled"; +- }; +- +- hscif2: serial@e6560000 { +- compatible = "renesas,hscif-r8a779a0", +- "renesas,rcar-gen3-hscif", "renesas,hscif"; +- reg = <0 0xe6560000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 516>, +- <&cpg CPG_CORE R8A779A0_CLK_S1D2>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x35>, <&dmac1 0x34>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 516>; +- status = "disabled"; +- }; +- +- hscif3: serial@e66a0000 { +- compatible = "renesas,hscif-r8a779a0", +- "renesas,rcar-gen3-hscif", "renesas,hscif"; +- reg = <0 0xe66a0000 0 0x60>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 517>, +- <&cpg CPG_CORE R8A779A0_CLK_S1D2>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x37>, <&dmac1 0x36>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 517>; +- status = "disabled"; +- }; +- +- avb0: ethernet@e6800000 { +- compatible = "renesas,etheravb-r8a779a0", +- "renesas,etheravb-rcar-gen3"; +- reg = <0 0xe6800000 0 0x800>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15", +- "ch16", "ch17", "ch18", "ch19", +- "ch20", "ch21", "ch22", "ch23", +- "ch24"; +- clocks = <&cpg CPG_MOD 211>; +- clock-names = "fck"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 211>; +- phy-mode = "rgmii"; +- rx-internal-delay-ps = <0>; +- tx-internal-delay-ps = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- avb1: ethernet@e6810000 { +- compatible = "renesas,etheravb-r8a779a0", +- "renesas,etheravb-rcar-gen3"; +- reg = <0 0xe6810000 0 0x800>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15", +- "ch16", "ch17", "ch18", "ch19", +- "ch20", "ch21", "ch22", "ch23", +- "ch24"; +- clocks = <&cpg CPG_MOD 212>; +- clock-names = "fck"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 212>; +- phy-mode = "rgmii"; +- rx-internal-delay-ps = <0>; +- tx-internal-delay-ps = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- avb2: ethernet@e6820000 { +- compatible = "renesas,etheravb-r8a779a0", +- "renesas,etheravb-rcar-gen3"; +- reg = <0 0xe6820000 0 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15", +- "ch16", "ch17", "ch18", "ch19", +- "ch20", "ch21", "ch22", "ch23", +- "ch24"; +- clocks = <&cpg CPG_MOD 213>; +- clock-names = "fck"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 213>; +- phy-mode = "rgmii"; +- rx-internal-delay-ps = <0>; +- tx-internal-delay-ps = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- avb3: ethernet@e6830000 { +- compatible = "renesas,etheravb-r8a779a0", +- "renesas,etheravb-rcar-gen3"; +- reg = <0 0xe6830000 0 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15", +- "ch16", "ch17", "ch18", "ch19", +- "ch20", "ch21", "ch22", "ch23", +- "ch24"; +- clocks = <&cpg CPG_MOD 214>; +- clock-names = "fck"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 214>; +- phy-mode = "rgmii"; +- rx-internal-delay-ps = <0>; +- tx-internal-delay-ps = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- avb4: ethernet@e6840000 { +- compatible = "renesas,etheravb-r8a779a0", +- "renesas,etheravb-rcar-gen3"; +- reg = <0 0xe6840000 0 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15", +- "ch16", "ch17", "ch18", "ch19", +- "ch20", "ch21", "ch22", "ch23", +- "ch24"; +- clocks = <&cpg CPG_MOD 215>; +- clock-names = "fck"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 215>; +- phy-mode = "rgmii"; +- rx-internal-delay-ps = <0>; +- tx-internal-delay-ps = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- avb5: ethernet@e6850000 { +- compatible = "renesas,etheravb-r8a779a0", +- "renesas,etheravb-rcar-gen3"; +- reg = <0 0xe6850000 0 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15", +- "ch16", "ch17", "ch18", "ch19", +- "ch20", "ch21", "ch22", "ch23", +- "ch24"; +- clocks = <&cpg CPG_MOD 216>; +- clock-names = "fck"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 216>; +- phy-mode = "rgmii"; +- rx-internal-delay-ps = <0>; +- tx-internal-delay-ps = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- scif0: serial@e6e60000 { +- compatible = "renesas,scif-r8a779a0", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e60000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 702>, +- <&cpg CPG_CORE R8A779A0_CLK_S1D2>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x51>, <&dmac1 0x50>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 702>; +- status = "disabled"; +- }; +- +- scif1: serial@e6e68000 { +- compatible = "renesas,scif-r8a779a0", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6e68000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 703>, +- <&cpg CPG_CORE R8A779A0_CLK_S1D2>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x53>, <&dmac1 0x52>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 703>; +- status = "disabled"; +- }; +- +- scif3: serial@e6c50000 { +- compatible = "renesas,scif-r8a779a0", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c50000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 704>, +- <&cpg CPG_CORE R8A779A0_CLK_S1D2>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x57>, <&dmac1 0x56>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 704>; +- status = "disabled"; +- }; +- +- scif4: serial@e6c40000 { +- compatible = "renesas,scif-r8a779a0", +- "renesas,rcar-gen3-scif", "renesas,scif"; +- reg = <0 0xe6c40000 0 64>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 705>, +- <&cpg CPG_CORE R8A779A0_CLK_S1D2>, +- <&scif_clk>; +- clock-names = "fck", "brg_int", "scif_clk"; +- dmas = <&dmac1 0x59>, <&dmac1 0x58>; +- dma-names = "tx", "rx"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 705>; +- status = "disabled"; +- }; +- +- msiof0: spi@e6e90000 { +- compatible = "renesas,msiof-r8a779a0", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6e90000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 618>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 618>; +- dmas = <&dmac1 0x41>, <&dmac1 0x40>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof1: spi@e6ea0000 { +- compatible = "renesas,msiof-r8a779a0", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6ea0000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 619>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 619>; +- dmas = <&dmac1 0x43>, <&dmac1 0x42>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof2: spi@e6c00000 { +- compatible = "renesas,msiof-r8a779a0", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c00000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 620>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 620>; +- dmas = <&dmac1 0x45>, <&dmac1 0x44>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof3: spi@e6c10000 { +- compatible = "renesas,msiof-r8a779a0", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c10000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 621>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 621>; +- dmas = <&dmac1 0x47>, <&dmac1 0x46>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof4: spi@e6c20000 { +- compatible = "renesas,msiof-r8a779a0", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c20000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 622>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 622>; +- dmas = <&dmac1 0x49>, <&dmac1 0x48>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- msiof5: spi@e6c28000 { +- compatible = "renesas,msiof-r8a779a0", +- "renesas,rcar-gen3-msiof"; +- reg = <0 0xe6c28000 0 0x0064>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 623>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 623>; +- dmas = <&dmac1 0x4b>, <&dmac1 0x4a>; +- dma-names = "tx", "rx"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- dmac1: dma-controller@e7350000 { +- compatible = "renesas,dmac-r8a779a0"; +- reg = <0 0xe7350000 0 0x1000>, +- <0 0xe7300000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", "ch4", +- "ch5", "ch6", "ch7", "ch8", "ch9", +- "ch10", "ch11", "ch12", "ch13", +- "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 709>; +- clock-names = "fck"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 709>; +- #dma-cells = <1>; +- dma-channels = <16>; +- }; +- +- dmac2: dma-controller@e7351000 { +- compatible = "renesas,dmac-r8a779a0"; +- reg = <0 0xe7351000 0 0x1000>, +- <0 0xe7310000 0 0x10000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", "ch4", +- "ch5", "ch6", "ch7"; +- clocks = <&cpg CPG_MOD 710>; +- clock-names = "fck"; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 710>; +- #dma-cells = <1>; +- dma-channels = <8>; +- }; +- +- mmc0: mmc@ee140000 { +- compatible = "renesas,sdhi-r8a779a0", +- "renesas,rcar-gen3-sdhi"; +- reg = <0 0xee140000 0 0x2000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 706>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 706>; +- max-frequency = <200000000>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@f1000000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x0 0xf1000000 0 0x20000>, +- <0x0 0xf1060000 0 0x110000>; +- interrupts = ; +- }; +- +- fcpvd0: fcp@fea10000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea10000 0 0x200>; +- clocks = <&cpg CPG_MOD 508>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 508>; +- }; +- +- fcpvd1: fcp@fea11000 { +- compatible = "renesas,fcpv"; +- reg = <0 0xfea11000 0 0x200>; +- clocks = <&cpg CPG_MOD 509>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 509>; +- }; +- +- vspd0: vsp@fea20000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea20000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 830>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 830>; +- +- renesas,fcp = <&fcpvd0>; +- }; +- +- vspd1: vsp@fea28000 { +- compatible = "renesas,vsp2"; +- reg = <0 0xfea28000 0 0x5000>; +- interrupts = ; +- clocks = <&cpg CPG_MOD 831>; +- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; +- resets = <&cpg 831>; +- +- renesas,fcp = <&fcpvd1>; +- }; +- +- prr: chipid@fff00044 { +- compatible = "renesas,prr"; +- reg = <0 0xfff00044 0 4>; +- }; +- }; +- +- thermal-zones { +- sensor1_thermal: sensor1-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 0>; +- +- trips { +- sensor1_crit: sensor1-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- sensor2_thermal: sensor2-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 1>; +- +- trips { +- sensor2_crit: sensor2-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- sensor3_thermal: sensor3-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 2>; +- +- trips { +- sensor3_crit: sensor3-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- sensor4_thermal: sensor4-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 3>; +- +- trips { +- sensor4_crit: sensor4-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- +- sensor5_thermal: sensor5-thermal { +- polling-delay-passive = <250>; +- polling-delay = <1000>; +- thermal-sensors = <&tsc 4>; +- +- trips { +- sensor5_crit: sensor5-crit { +- temperature = <120000>; +- hysteresis = <1000>; +- type = "critical"; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a779m1-salvator-xs.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a779m1-salvator-xs.dts +deleted file mode 100644 +index 084b75b04680..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a779m1-salvator-xs.dts ++++ /dev/null +@@ -1,53 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 or MIT) +-/* +- * Device Tree Source for the Salvator-X 2nd version board with R-Car H3e-2G +- * +- * Copyright (C) 2021 Glider bv +- * +- * Based on r8a77951-salvator-xs.dts +- * Copyright (C) 2015-2017 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a779m1.dtsi" +-#include "salvator-xs.dtsi" +- +-/ { +- model = "Renesas Salvator-X 2nd version board based on r8a779m1"; +- compatible = "renesas,salvator-xs", "renesas,r8a779m1", +- "renesas,r8a7795"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x38000000>; +- }; +- +- memory@500000000 { +- device_type = "memory"; +- reg = <0x5 0x00000000 0x0 0x40000000>; +- }; +- +- memory@600000000 { +- device_type = "memory"; +- reg = <0x6 0x00000000 0x0 0x40000000>; +- }; +- +- memory@700000000 { +- device_type = "memory"; +- reg = <0x7 0x00000000 0x0 0x40000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>, +- <&cpg CPG_MOD 721>, +- <&versaclock6 1>, +- <&x21_clk>, +- <&x22_clk>, +- <&versaclock6 2>; +- clock-names = "du.0", "du.1", "du.2", "du.3", +- "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a779m1-ulcb-kf.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a779m1-ulcb-kf.dts +deleted file mode 100644 +index 0baebc5c58b0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a779m1-ulcb-kf.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 or MIT) +-/* +- * Device Tree Source for the H3ULCB Kingfisher board with R-Car H3e-2G +- * +- * Copyright (C) 2021 Glider bv +- * +- * Based on r8a77951-ulcb-kf.dts +- * Copyright (C) 2017 Renesas Electronics Corp. +- * Copyright (C) 2017 Cogent Embedded, Inc. +- */ +- +-#include "r8a779m1-ulcb.dts" +-#include "ulcb-kf.dtsi" +- +-/ { +- model = "Renesas H3ULCB Kingfisher board based on r8a779m1"; +- compatible = "shimafuji,kingfisher", "renesas,h3ulcb", +- "renesas,r8a779m1", "renesas,r8a7795"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a779m1-ulcb.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a779m1-ulcb.dts +deleted file mode 100644 +index e294b6bda28c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a779m1-ulcb.dts ++++ /dev/null +@@ -1,54 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 or MIT) +-/* +- * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) with R-Car H3e-2G +- * +- * Copyright (C) 2021 Glider bv +- * +- * Based on r8a77951-ulcb.dts +- * +- * Copyright (C) 2016 Renesas Electronics Corp. +- * Copyright (C) 2016 Cogent Embedded, Inc. +- */ +- +-/dts-v1/; +-#include "r8a779m1.dtsi" +-#include "ulcb.dtsi" +- +-/ { +- model = "Renesas H3ULCB board based on r8a779m1"; +- compatible = "renesas,h3ulcb", "renesas,r8a779m1", "renesas,r8a7795"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x38000000>; +- }; +- +- memory@500000000 { +- device_type = "memory"; +- reg = <0x5 0x00000000 0x0 0x40000000>; +- }; +- +- memory@600000000 { +- device_type = "memory"; +- reg = <0x6 0x00000000 0x0 0x40000000>; +- }; +- +- memory@700000000 { +- device_type = "memory"; +- reg = <0x7 0x00000000 0x0 0x40000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>, +- <&cpg CPG_MOD 721>, +- <&versaclock5 1>, +- <&versaclock5 3>, +- <&versaclock5 4>, +- <&versaclock5 2>; +- clock-names = "du.0", "du.1", "du.2", "du.3", +- "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a779m1.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r8a779m1.dtsi +deleted file mode 100644 +index 0e9b04469b83..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a779m1.dtsi ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 or MIT) +-/* +- * Device Tree Source for the R-Car H3e-2G (R8A779M1) SoC +- * +- * Copyright (C) 2021 Glider bv +- */ +- +-#include "r8a77951.dtsi" +- +-/ { +- compatible = "renesas,r8a779m1", "renesas,r8a7795"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a779m3-salvator-xs.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a779m3-salvator-xs.dts +deleted file mode 100644 +index 4ab26fd7233d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a779m3-salvator-xs.dts ++++ /dev/null +@@ -1,46 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 or MIT) +-/* +- * Device Tree Source for the Salvator-X 2nd version board with R-Car M3e-2G +- * +- * Copyright (C) 2021 Glider bv +- * +- * Based on r8a77961-salvator-xs.dts +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a779m3.dtsi" +-#include "salvator-xs.dtsi" +- +-/ { +- model = "Renesas Salvator-X 2nd version board based on r8a779m3"; +- compatible = "renesas,salvator-xs", "renesas,r8a779m3", +- "renesas,r8a77961"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x78000000>; +- }; +- +- memory@480000000 { +- device_type = "memory"; +- reg = <0x4 0x80000000 0x0 0x80000000>; +- }; +- +- memory@600000000 { +- device_type = "memory"; +- reg = <0x6 0x00000000 0x1 0x00000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>, +- <&versaclock6 1>, +- <&x21_clk>, +- <&versaclock6 2>; +- clock-names = "du.0", "du.1", "du.2", +- "dclkin.0", "dclkin.1", "dclkin.2"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a779m3-ulcb-kf.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a779m3-ulcb-kf.dts +deleted file mode 100644 +index 6bacee1d2ef5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a779m3-ulcb-kf.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 or MIT) +-/* +- * Device Tree Source for the M3ULCB Kingfisher board with R-Car M3e-2G +- * +- * Copyright (C) 2021 Glider bv +- * +- * Based on r8a77961-ulcb-kf.dts +- * Copyright (C) 2020 Eugeniu Rosca +- */ +- +-#include "r8a779m3-ulcb.dts" +-#include "ulcb-kf.dtsi" +- +-/ { +- model = "Renesas M3ULCB Kingfisher board based on r8a779m3"; +- compatible = "shimafuji,kingfisher", "renesas,m3ulcb", +- "renesas,r8a779m3", "renesas,r8a77961"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a779m3-ulcb.dts b/scripts/dtc/include-prefixes/arm64/renesas/r8a779m3-ulcb.dts +deleted file mode 100644 +index 8f215a0b771b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a779m3-ulcb.dts ++++ /dev/null +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 or MIT) +-/* +- * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) with R-Car M3e-2G +- * +- * Copyright (C) 2021 Glider bv +- * +- * Based on r8a77961-ulcb.dts +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r8a779m3.dtsi" +-#include "ulcb.dtsi" +- +-/ { +- model = "Renesas M3ULCB board based on r8a779m3"; +- compatible = "renesas,m3ulcb", "renesas,r8a779m3", "renesas,r8a77961"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x78000000>; +- }; +- +- memory@480000000 { +- device_type = "memory"; +- reg = <0x4 0x80000000 0x0 0x80000000>; +- }; +- +- memory@600000000 { +- device_type = "memory"; +- reg = <0x6 0x00000000 0x1 0x00000000>; +- }; +-}; +- +-&du { +- clocks = <&cpg CPG_MOD 724>, +- <&cpg CPG_MOD 723>, +- <&cpg CPG_MOD 722>, +- <&versaclock5 1>, +- <&versaclock5 3>, +- <&versaclock5 2>; +- clock-names = "du.0", "du.1", "du.2", +- "dclkin.0", "dclkin.1", "dclkin.2"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r8a779m3.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r8a779m3.dtsi +deleted file mode 100644 +index 65bb6188ccf5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r8a779m3.dtsi ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 or MIT) +-/* +- * Device Tree Source for the R-Car M3e-2G (R8A779M3) SoC +- * +- * Copyright (C) 2021 Glider bv +- */ +- +-#include "r8a77961.dtsi" +- +-/ { +- compatible = "renesas,r8a779m3", "renesas,r8a77961"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r9a07g044.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r9a07g044.dtsi +deleted file mode 100644 +index 5f3bc2898daf..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r9a07g044.dtsi ++++ /dev/null +@@ -1,316 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +-/* +- * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts +- * +- * Copyright (C) 2021 Renesas Electronics Corp. +- */ +- +-#include +-#include +- +-/ { +- compatible = "renesas,r9a07g044"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- /* External CAN clock - to be overridden by boards that provide it */ +- can_clk: can { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ +- extal_clk: extal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- /* This value must be overridden by the board */ +- clock-frequency = <0>; +- }; +- +- psci { +- compatible = "arm,psci-1.0", "arm,psci-0.2"; +- method = "smc"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- }; +- }; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a55"; +- reg = <0>; +- device_type = "cpu"; +- next-level-cache = <&L3_CA55>; +- enable-method = "psci"; +- }; +- +- cpu1: cpu@100 { +- compatible = "arm,cortex-a55"; +- reg = <0x100>; +- device_type = "cpu"; +- next-level-cache = <&L3_CA55>; +- enable-method = "psci"; +- }; +- +- L3_CA55: cache-controller-0 { +- compatible = "cache"; +- cache-unified; +- cache-size = <0x40000>; +- }; +- }; +- +- soc: soc { +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- scif0: serial@1004b800 { +- compatible = "renesas,scif-r9a07g044"; +- reg = <0 0x1004b800 0 0x400>; +- interrupts = , +- , +- , +- , +- , +- ; +- interrupt-names = "eri", "rxi", "txi", +- "bri", "dri", "tei"; +- clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>; +- clock-names = "fck"; +- power-domains = <&cpg>; +- resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>; +- status = "disabled"; +- }; +- +- canfd: can@10050000 { +- compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd"; +- reg = <0 0x10050000 0 0x8000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "g_err", "g_recc", +- "ch0_err", "ch0_rec", "ch0_trx", +- "ch1_err", "ch1_rec", "ch1_trx"; +- clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>, +- <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>, +- <&can_clk>; +- clock-names = "fck", "canfd", "can_clk"; +- assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>; +- assigned-clock-rates = <50000000>; +- resets = <&cpg R9A07G044_CANFD_RSTP_N>, +- <&cpg R9A07G044_CANFD_RSTC_N>; +- reset-names = "rstp_n", "rstc_n"; +- power-domains = <&cpg>; +- status = "disabled"; +- +- channel0 { +- status = "disabled"; +- }; +- channel1 { +- status = "disabled"; +- }; +- }; +- +- i2c0: i2c@10058000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; +- reg = <0 0x10058000 0 0x400>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "tei", "ri", "ti", "spi", "sti", +- "naki", "ali", "tmoi"; +- clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>; +- clock-frequency = <100000>; +- resets = <&cpg R9A07G044_I2C0_MRST>; +- power-domains = <&cpg>; +- status = "disabled"; +- }; +- +- i2c1: i2c@10058400 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; +- reg = <0 0x10058400 0 0x400>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "tei", "ri", "ti", "spi", "sti", +- "naki", "ali", "tmoi"; +- clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>; +- clock-frequency = <100000>; +- resets = <&cpg R9A07G044_I2C1_MRST>; +- power-domains = <&cpg>; +- status = "disabled"; +- }; +- +- i2c2: i2c@10058800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; +- reg = <0 0x10058800 0 0x400>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "tei", "ri", "ti", "spi", "sti", +- "naki", "ali", "tmoi"; +- clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>; +- clock-frequency = <100000>; +- resets = <&cpg R9A07G044_I2C2_MRST>; +- power-domains = <&cpg>; +- status = "disabled"; +- }; +- +- i2c3: i2c@10058c00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; +- reg = <0 0x10058c00 0 0x400>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "tei", "ri", "ti", "spi", "sti", +- "naki", "ali", "tmoi"; +- clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>; +- clock-frequency = <100000>; +- resets = <&cpg R9A07G044_I2C3_MRST>; +- power-domains = <&cpg>; +- status = "disabled"; +- }; +- +- adc: adc@10059000 { +- compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc"; +- reg = <0 0x10059000 0 0x400>; +- interrupts = ; +- clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>, +- <&cpg CPG_MOD R9A07G044_ADC_PCLK>; +- clock-names = "adclk", "pclk"; +- resets = <&cpg R9A07G044_ADC_PRESETN>, +- <&cpg R9A07G044_ADC_ADRST_N>; +- reset-names = "presetn", "adrst-n"; +- power-domains = <&cpg>; +- status = "disabled"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- channel@0 { +- reg = <0>; +- }; +- channel@1 { +- reg = <1>; +- }; +- channel@2 { +- reg = <2>; +- }; +- channel@3 { +- reg = <3>; +- }; +- channel@4 { +- reg = <4>; +- }; +- channel@5 { +- reg = <5>; +- }; +- channel@6 { +- reg = <6>; +- }; +- channel@7 { +- reg = <7>; +- }; +- }; +- +- cpg: clock-controller@11010000 { +- compatible = "renesas,r9a07g044-cpg"; +- reg = <0 0x11010000 0 0x10000>; +- clocks = <&extal_clk>; +- clock-names = "extal"; +- #clock-cells = <2>; +- #reset-cells = <1>; +- #power-domain-cells = <0>; +- }; +- +- sysc: system-controller@11020000 { +- compatible = "renesas,r9a07g044-sysc"; +- reg = <0 0x11020000 0 0x10000>; +- interrupts = , +- , +- , +- ; +- interrupt-names = "lpm_int", "ca55stbydone_int", +- "cm33stbyr_int", "ca55_deny"; +- status = "disabled"; +- }; +- +- pinctrl: pin-controller@11030000 { +- compatible = "renesas,r9a07g044-pinctrl"; +- reg = <0 0x11030000 0 0x10000>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 0 392>; +- clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; +- power-domains = <&cpg>; +- resets = <&cpg R9A07G044_GPIO_RSTN>, +- <&cpg R9A07G044_GPIO_PORT_RESETN>, +- <&cpg R9A07G044_GPIO_SPARE_RESETN>; +- }; +- +- gic: interrupt-controller@11900000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x0 0x11900000 0 0x40000>, +- <0x0 0x11940000 0 0x60000>; +- interrupts = ; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r9a07g044l1.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r9a07g044l1.dtsi +deleted file mode 100644 +index 9d89d4590358..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r9a07g044l1.dtsi ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +-/* +- * Device Tree Source for the RZ/G2L R9A07G044L1 SoC specific parts +- * +- * Copyright (C) 2021 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r9a07g044.dtsi" +- +-/ { +- compatible = "renesas,r9a07g044l1", "renesas,r9a07g044"; +- +- cpus { +- /delete-node/ cpu-map; +- /delete-node/ cpu@100; +- }; +- +- timer { +- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, +- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r9a07g044l2-smarc.dts b/scripts/dtc/include-prefixes/arm64/renesas/r9a07g044l2-smarc.dts +deleted file mode 100644 +index d3f72ec62f03..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r9a07g044l2-smarc.dts ++++ /dev/null +@@ -1,21 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +-/* +- * Device Tree Source for the RZ/G2L SMARC EVK board +- * +- * Copyright (C) 2021 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r9a07g044l2.dtsi" +-#include "rzg2l-smarc.dtsi" +- +-/ { +- model = "Renesas SMARC EVK based on r9a07g044l2"; +- compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044"; +- +- memory@48000000 { +- device_type = "memory"; +- /* first 128MB is reserved for secure area. */ +- reg = <0x0 0x48000000 0x0 0x78000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/r9a07g044l2.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/r9a07g044l2.dtsi +deleted file mode 100644 +index 91dc10b2cdbb..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/r9a07g044l2.dtsi ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +-/* +- * Device Tree Source for the RZ/G2L R9A07G044L2 SoC specific parts +- * +- * Copyright (C) 2021 Renesas Electronics Corp. +- */ +- +-/dts-v1/; +-#include "r9a07g044.dtsi" +- +-/ { +- compatible = "renesas,r9a07g044l2", "renesas,r9a07g044"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/rzg2-advantech-idk-1110wr-panel.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/rzg2-advantech-idk-1110wr-panel.dtsi +deleted file mode 100644 +index bcc21178ae04..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/rzg2-advantech-idk-1110wr-panel.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Advantech idk-1110wr LVDS panel connected +- * to RZ/G2 boards +- * +- * Copyright (C) 2019 Renesas Electronics Corp. +- */ +- +-/ { +- panel-lvds { +- compatible = "advantech,idk-1110wr", "panel-lvds"; +- +- width-mm = <223>; +- height-mm = <125>; +- +- data-mapping = "jeida-24"; +- +- panel-timing { +- /* 1024x600 @60Hz */ +- clock-frequency = <51200000>; +- hactive = <1024>; +- vactive = <600>; +- hsync-len = <240>; +- hfront-porch = <40>; +- hback-porch = <40>; +- vfront-porch = <15>; +- vback-porch = <10>; +- vsync-len = <10>; +- }; +- +- port { +- panel_in: endpoint { +- remote-endpoint = <&lvds_connector>; +- }; +- }; +- }; +-}; +- +-&lvds_connector { +- remote-endpoint = <&panel_in>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/rzg2l-smarc.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/rzg2l-smarc.dtsi +deleted file mode 100644 +index adcd4f50519e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/rzg2l-smarc.dtsi ++++ /dev/null +@@ -1,27 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +-/* +- * Device Tree Source for the RZ/G2L SMARC EVK common parts +- * +- * Copyright (C) 2021 Renesas Electronics Corp. +- */ +- +-#include +- +-/ { +- aliases { +- serial0 = &scif0; +- }; +- +- chosen { +- bootargs = "ignore_loglevel"; +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&extal_clk { +- clock-frequency = <24000000>; +-}; +- +-&scif0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/salvator-common.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/salvator-common.dtsi +deleted file mode 100644 +index eb1f3b82300b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/salvator-common.dtsi ++++ /dev/null +@@ -1,1049 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for common parts of Salvator-X board variants +- * +- * Copyright (C) 2015-2016 Renesas Electronics Corp. +- */ +- +-/* +- * SSI-AK4613 +- * +- * This command is required when Playback/Capture +- * +- * amixer set "DVC Out" 100% +- * amixer set "DVC In" 100% +- * +- * You can use Mute +- * +- * amixer set "DVC Out Mute" on +- * amixer set "DVC In Mute" on +- * +- * You can use Volume Ramp +- * +- * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" +- * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" +- * amixer set "DVC Out Ramp" on +- * aplay xxx.wav & +- * amixer set "DVC Out" 80% // Volume Down +- * amixer set "DVC Out" 100% // Volume Up +- */ +- +-#include +-#include +- +-/ { +- aliases { +- serial0 = &scif2; +- serial1 = &hscif1; +- ethernet0 = &avb; +- mmc0 = &sdhi2; +- mmc1 = &sdhi0; +- mmc2 = &sdhi3; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- audio_clkout: audio-clkout { +- /* +- * This is same as <&rcar_sound 0> +- * but needed to avoid cs2000/rcar_sound probe dead-lock +- */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <12288000>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 50000>; +- +- brightness-levels = <256 128 64 16 8 4 0>; +- default-brightness-level = <6>; +- +- power-supply = <®_12v>; +- enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; +- }; +- +- cvbs-in { +- compatible = "composite-video-connector"; +- label = "CVBS IN"; +- +- port { +- cvbs_con: endpoint { +- remote-endpoint = <&adv7482_ain7>; +- }; +- }; +- }; +- +- hdmi-in { +- compatible = "hdmi-connector"; +- label = "HDMI IN"; +- type = "a"; +- +- port { +- hdmi_in_con: endpoint { +- remote-endpoint = <&adv7482_hdmi>; +- }; +- }; +- }; +- +- hdmi0-out { +- compatible = "hdmi-connector"; +- label = "HDMI0 OUT"; +- type = "a"; +- +- port { +- hdmi0_con: endpoint { +- }; +- }; +- }; +- +- hdmi1-out { +- compatible = "hdmi-connector"; +- label = "HDMI1 OUT"; +- type = "a"; +- +- port { +- hdmi1_con: endpoint { +- }; +- }; +- }; +- +- keys { +- compatible = "gpio-keys"; +- +- pinctrl-0 = <&keys_pins>; +- pinctrl-names = "default"; +- +- key-1 { +- gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW4-1"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-2 { +- gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW4-2"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-3 { +- gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW4-3"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-4 { +- gpios = <&gpio5 23 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "SW4-4"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-a { +- gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "TSW0"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-b { +- gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "TSW1"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- key-c { +- gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "TSW2"; +- wakeup-source; +- debounce-interval = <20>; +- }; +- }; +- +- reg_1p8v: regulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator1 { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_12v: regulator2 { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-12V"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sound_card: sound { +- compatible = "audio-graph-card"; +- +- label = "rcar-sound"; +- +- dais = <&rsnd_port0 /* ak4613 */ +- &rsnd_port1 /* HDMI0 */ +-#ifdef SOC_HAS_HDMI1 +- &rsnd_port2 /* HDMI1 */ +-#endif +- >; +- }; +- +- vbus0_usb2: regulator-vbus0-usb2 { +- compatible = "regulator-fixed"; +- +- regulator-name = "USB20_VBUS0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vcc_sdhi0: regulator-vcc-sdhi0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI0 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhi0: regulator-vccq-sdhi0 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI0 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- vcc_sdhi3: regulator-vcc-sdhi3 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI3 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhi3: regulator-vccq-sdhi3 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI3 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- vga { +- compatible = "vga-connector"; +- +- port { +- vga_in: endpoint { +- remote-endpoint = <&adv7123_out>; +- }; +- }; +- }; +- +- vga-encoder { +- compatible = "adi,adv7123"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- adv7123_in: endpoint { +- remote-endpoint = <&du_out_rgb>; +- }; +- }; +- port@1 { +- reg = <1>; +- adv7123_out: endpoint { +- remote-endpoint = <&vga_in>; +- }; +- }; +- }; +- }; +- +- x12_clk: x12 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +- +- /* External DU dot clocks */ +- x21_clk: x21-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <33000000>; +- }; +- +- x22_clk: x22-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <33000000>; +- }; +- +- x23_clk: x23-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +-}; +- +-&a57_0 { +- cpu-supply = <&dvfs>; +-}; +- +-&audio_clk_a { +- clock-frequency = <22579200>; +-}; +- +-&avb { +- pinctrl-0 = <&avb_pins>; +- pinctrl-names = "default"; +- phy-handle = <&phy0>; +- tx-internal-delay-ps = <2000>; +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- rxc-skew-ps = <1500>; +- reg = <0>; +- interrupt-parent = <&gpio2>; +- interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&csi20 { +- status = "okay"; +- +- ports { +- port@0 { +- csi20_in: endpoint { +- clock-lanes = <0>; +- data-lanes = <1>; +- remote-endpoint = <&adv7482_txb>; +- }; +- }; +- }; +-}; +- +-&csi40 { +- status = "okay"; +- +- ports { +- port@0 { +- csi40_in: endpoint { +- clock-lanes = <0>; +- data-lanes = <1 2 3 4>; +- remote-endpoint = <&adv7482_txa>; +- }; +- }; +- }; +-}; +- +-&du { +- pinctrl-0 = <&du_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- ports { +- port@0 { +- endpoint { +- remote-endpoint = <&adv7123_in>; +- }; +- }; +- }; +-}; +- +-&ehci0 { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&extalr_clk { +- clock-frequency = <32768>; +-}; +- +-&hdmi0 { +- status = "okay"; +- +- ports { +- port@1 { +- reg = <1>; +- rcar_dw_hdmi0_out: endpoint { +- remote-endpoint = <&hdmi0_con>; +- }; +- }; +- port@2 { +- reg = <2>; +- dw_hdmi0_snd_in: endpoint { +- remote-endpoint = <&rsnd_endpoint1>; +- }; +- }; +- }; +-}; +- +-&hdmi0_con { +- remote-endpoint = <&rcar_dw_hdmi0_out>; +-}; +- +-#ifdef SOC_HAS_HDMI1 +-&hdmi1 { +- status = "okay"; +- +- ports { +- port@1 { +- reg = <1>; +- rcar_dw_hdmi1_out: endpoint { +- remote-endpoint = <&hdmi1_con>; +- }; +- }; +- port@2 { +- reg = <2>; +- dw_hdmi1_snd_in: endpoint { +- remote-endpoint = <&rsnd_endpoint2>; +- }; +- }; +- }; +-}; +- +-&hdmi1_con { +- remote-endpoint = <&rcar_dw_hdmi1_out>; +-}; +-#endif /* SOC_HAS_HDMI1 */ +- +-&hscif1 { +- pinctrl-0 = <&hscif1_pins>; +- pinctrl-names = "default"; +- +- uart-has-rtscts; +- /* Please only enable hscif1 or scif1 */ +- status = "okay"; +-}; +- +-&hsusb { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-0 = <&i2c2_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- clock-frequency = <100000>; +- +- ak4613: codec@10 { +- compatible = "asahi-kasei,ak4613"; +- #sound-dai-cells = <0>; +- reg = <0x10>; +- clocks = <&rcar_sound 3>; +- +- asahi-kasei,in1-single-end; +- asahi-kasei,in2-single-end; +- asahi-kasei,out1-single-end; +- asahi-kasei,out2-single-end; +- asahi-kasei,out3-single-end; +- asahi-kasei,out4-single-end; +- asahi-kasei,out5-single-end; +- asahi-kasei,out6-single-end; +- +- port { +- ak4613_endpoint: endpoint { +- remote-endpoint = <&rsnd_endpoint0>; +- }; +- }; +- }; +- +- cs2000: clk_multiplier@4f { +- #clock-cells = <0>; +- compatible = "cirrus,cs2000-cp"; +- reg = <0x4f>; +- clocks = <&audio_clkout>, <&x12_clk>; +- clock-names = "clk_in", "ref_clk"; +- +- assigned-clocks = <&cs2000>; +- assigned-clock-rates = <24576000>; /* 1/1 divide */ +- }; +-}; +- +-&i2c4 { +- status = "okay"; +- +- pca9654: gpio@20 { +- compatible = "onnn,pca9654"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- video-receiver@70 { +- compatible = "adi,adv7482"; +- reg = <0x70 0x71 0x72 0x73 0x74 0x75 +- 0x60 0x61 0x62 0x63 0x64 0x65>; +- reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater", +- "infoframe", "cbus", "cec", "sdp", "txa", "txb" ; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- interrupt-parent = <&gpio6>; +- interrupt-names = "intrq1", "intrq2"; +- interrupts = <30 IRQ_TYPE_LEVEL_LOW>, +- <31 IRQ_TYPE_LEVEL_LOW>; +- +- port@7 { +- reg = <7>; +- +- adv7482_ain7: endpoint { +- remote-endpoint = <&cvbs_con>; +- }; +- }; +- +- port@8 { +- reg = <8>; +- +- adv7482_hdmi: endpoint { +- remote-endpoint = <&hdmi_in_con>; +- }; +- }; +- +- port@a { +- reg = <10>; +- +- adv7482_txa: endpoint { +- clock-lanes = <0>; +- data-lanes = <1 2 3 4>; +- remote-endpoint = <&csi40_in>; +- }; +- }; +- +- port@b { +- reg = <11>; +- +- adv7482_txb: endpoint { +- clock-lanes = <0>; +- data-lanes = <1>; +- remote-endpoint = <&csi20_in>; +- }; +- }; +- }; +- +- csa_vdd: adc@7c { +- compatible = "maxim,max9611"; +- reg = <0x7c>; +- +- shunt-resistor-micro-ohms = <5000>; +- }; +- +- csa_dvfs: adc@7f { +- compatible = "maxim,max9611"; +- reg = <0x7f>; +- +- shunt-resistor-micro-ohms = <5000>; +- }; +-}; +- +-&i2c_dvfs { +- status = "okay"; +- +- clock-frequency = <400000>; +- +- pmic: pmic@30 { +- pinctrl-0 = <&irq0_pins>; +- pinctrl-names = "default"; +- +- compatible = "rohm,bd9571mwv"; +- reg = <0x30>; +- interrupt-parent = <&intc_ex>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- rohm,ddr-backup-power = <0xf>; +- rohm,rstbmode-level; +- +- regulators { +- dvfs: dvfs { +- regulator-name = "dvfs"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1030000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +- +- eeprom@50 { +- compatible = "rohm,br24t01", "atmel,24c01"; +- reg = <0x50>; +- pagesize = <8>; +- }; +-}; +- +-&ohci0 { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&pcie_bus_clk { +- clock-frequency = <100000000>; +-}; +- +-&pciec0 { +- status = "okay"; +-}; +- +-&pciec1 { +- status = "okay"; +-}; +- +-&pfc { +- pinctrl-0 = <&scif_clk_pins>; +- pinctrl-names = "default"; +- +- avb_pins: avb { +- mux { +- groups = "avb_link", "avb_mdio", "avb_mii"; +- function = "avb"; +- }; +- +- pins_mdio { +- groups = "avb_mdio"; +- drive-strength = <24>; +- }; +- +- pins_mii_tx { +- pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", +- "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; +- drive-strength = <12>; +- }; +- }; +- +- du_pins: du { +- groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0"; +- function = "du"; +- }; +- +- hscif1_pins: hscif1 { +- groups = "hscif1_data_a", "hscif1_ctrl_a"; +- function = "hscif1"; +- }; +- +- i2c2_pins: i2c2 { +- groups = "i2c2_a"; +- function = "i2c2"; +- }; +- +- irq0_pins: irq0 { +- groups = "intc_ex_irq0"; +- function = "intc_ex"; +- }; +- +- keys_pins: keys { +- pins = "GP_5_17", "GP_5_20", "GP_5_22"; +- bias-pull-up; +- }; +- +- pwm1_pins: pwm1 { +- groups = "pwm1_a"; +- function = "pwm1"; +- }; +- +- scif1_pins: scif1 { +- groups = "scif1_data_a", "scif1_ctrl"; +- function = "scif1"; +- }; +- +- scif2_pins: scif2 { +- groups = "scif2_data_a"; +- function = "scif2"; +- }; +- +- scif_clk_pins: scif_clk { +- groups = "scif_clk_a"; +- function = "scif_clk"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <3300>; +- }; +- +- sdhi0_pins_uhs: sd0_uhs { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <1800>; +- }; +- +- sdhi2_pins: sd2 { +- groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; +- function = "sdhi2"; +- power-source = <1800>; +- }; +- +- sdhi3_pins: sd3 { +- groups = "sdhi3_data4", "sdhi3_ctrl"; +- function = "sdhi3"; +- power-source = <3300>; +- }; +- +- sdhi3_pins_uhs: sd3_uhs { +- groups = "sdhi3_data4", "sdhi3_ctrl"; +- function = "sdhi3"; +- power-source = <1800>; +- }; +- +- sound_pins: sound { +- groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; +- function = "ssi"; +- }; +- +- sound_clk_pins: sound_clk { +- groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", +- "audio_clkout_a", "audio_clkout3_a"; +- function = "audio_clk"; +- }; +- +- usb0_pins: usb0 { +- groups = "usb0"; +- function = "usb0"; +- }; +- +- usb1_pins: usb1 { +- mux { +- groups = "usb1"; +- function = "usb1"; +- }; +- +- ovc { +- pins = "GP_6_27"; +- bias-pull-up; +- }; +- +- pwen { +- pins = "GP_6_26"; +- bias-pull-down; +- }; +- }; +- +- usb30_pins: usb30 { +- groups = "usb30"; +- function = "usb30"; +- }; +-}; +- +-&pwm1 { +- pinctrl-0 = <&pwm1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&rcar_sound { +- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; +- pinctrl-names = "default"; +- +- /* Single DAI */ +- #sound-dai-cells = <0>; +- +- /* audio_clkout0/1/2/3 */ +- #clock-cells = <1>; +- clock-frequency = <12288000 11289600>; +- +- status = "okay"; +- +- /* update to */ +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&cs2000>, +- <&audio_clk_c>, +- <&cpg CPG_CORE CPG_AUDIO_CLK_I>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- rsnd_port0: port@0 { +- reg = <0>; +- rsnd_endpoint0: endpoint { +- remote-endpoint = <&ak4613_endpoint>; +- +- dai-format = "left_j"; +- bitclock-master = <&rsnd_endpoint0>; +- frame-master = <&rsnd_endpoint0>; +- +- playback = <&ssi0>, <&src0>, <&dvc0>; +- capture = <&ssi1>, <&src1>, <&dvc1>; +- }; +- }; +- +- rsnd_port1: port@1 { +- reg = <1>; +- rsnd_endpoint1: endpoint { +- remote-endpoint = <&dw_hdmi0_snd_in>; +- +- dai-format = "i2s"; +- bitclock-master = <&rsnd_endpoint1>; +- frame-master = <&rsnd_endpoint1>; +- +- playback = <&ssi2>; +- }; +- }; +- +-#ifdef SOC_HAS_HDMI1 +- rsnd_port2: port@2 { +- reg = <2>; +- rsnd_endpoint2: endpoint { +- remote-endpoint = <&dw_hdmi1_snd_in>; +- +- dai-format = "i2s"; +- bitclock-master = <&rsnd_endpoint2>; +- frame-master = <&rsnd_endpoint2>; +- +- playback = <&ssi3>; +- }; +- }; +-#endif /* SOC_HAS_HDMI1 */ +- }; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-#ifdef SOC_HAS_SATA +-&sata { +- status = "okay"; +-}; +-#endif /* SOC_HAS_SATA */ +- +-&scif1 { +- pinctrl-0 = <&scif1_pins>; +- pinctrl-names = "default"; +- +- uart-has-rtscts; +- /* Please only enable hscif1 or scif1 */ +- /* status = "okay"; */ +-}; +- +-&scif2 { +- pinctrl-0 = <&scif2_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scif_clk { +- clock-frequency = <14745600>; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-1 = <&sdhi0_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <&vcc_sdhi0>; +- vqmmc-supply = <&vccq_sdhi0>; +- cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; +- bus-width = <4>; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- status = "okay"; +-}; +- +-&sdhi2 { +- /* used for on-board 8bit eMMC */ +- pinctrl-0 = <&sdhi2_pins>; +- pinctrl-1 = <&sdhi2_pins>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_1p8v>; +- bus-width = <8>; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- no-sd; +- no-sdio; +- non-removable; +- fixed-emmc-driver-type = <1>; +- full-pwr-cycle-in-suspend; +- status = "okay"; +-}; +- +-&sdhi3 { +- pinctrl-0 = <&sdhi3_pins>; +- pinctrl-1 = <&sdhi3_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <&vcc_sdhi3>; +- vqmmc-supply = <&vccq_sdhi3>; +- cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; +- wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; +- bus-width = <4>; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- status = "okay"; +-}; +- +-&ssi1 { +- shared-pin; +-}; +- +-&usb_extal_clk { +- clock-frequency = <50000000>; +-}; +- +-&usb2_phy0 { +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +- +- vbus-supply = <&vbus0_usb2>; +- status = "okay"; +-}; +- +-&usb2_phy1 { +- pinctrl-0 = <&usb1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&usb3_peri0 { +- phys = <&usb3_phy0>; +- phy-names = "usb"; +- +- companion = <&xhci0>; +- +- status = "okay"; +-}; +- +-&usb3_phy0 { +- status = "okay"; +-}; +- +-&usb3s0_clk { +- clock-frequency = <100000000>; +-}; +- +-&vin0 { +- status = "okay"; +-}; +- +-&vin1 { +- status = "okay"; +-}; +- +-&vin2 { +- status = "okay"; +-}; +- +-&vin3 { +- status = "okay"; +-}; +- +-&vin4 { +- status = "okay"; +-}; +- +-&vin5 { +- status = "okay"; +-}; +- +-&vin6 { +- status = "okay"; +-}; +- +-&vin7 { +- status = "okay"; +-}; +- +-&xhci0 { +- pinctrl-0 = <&usb30_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-#ifdef SOC_HAS_USB2_CH2 +-&ehci2 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-&pfc { +- usb2_pins: usb2 { +- groups = "usb2"; +- function = "usb2"; +- }; +-}; +- +-&usb2_phy2 { +- pinctrl-0 = <&usb2_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +-#endif /* SOC_HAS_USB2_CH2 */ +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/salvator-x.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/salvator-x.dtsi +deleted file mode 100644 +index ddee50e64632..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/salvator-x.dtsi ++++ /dev/null +@@ -1,29 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Salvator-X board +- * +- * Copyright (C) 2015-2016 Renesas Electronics Corp. +- */ +- +-#include "salvator-common.dtsi" +- +-/ { +- model = "Renesas Salvator-X board"; +- compatible = "renesas,salvator-x"; +-}; +- +-&extal_clk { +- clock-frequency = <16666666>; +-}; +- +-&i2c4 { +- clock-frequency = <400000>; +- +- versaclock5: clock-generator@6a { +- compatible = "idt,5p49v5923"; +- reg = <0x6a>; +- #clock-cells = <1>; +- clocks = <&x23_clk>; +- clock-names = "xin"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/salvator-xs.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/salvator-xs.dtsi +deleted file mode 100644 +index 08b925624e12..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/salvator-xs.dtsi ++++ /dev/null +@@ -1,85 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Salvator-X 2nd version board +- * +- * Copyright (C) 2015-2017 Renesas Electronics Corp. +- */ +- +-#include "salvator-common.dtsi" +- +-/ { +- model = "Renesas Salvator-X 2nd version board"; +- compatible = "renesas,salvator-xs"; +-}; +- +-&extal_clk { +- clock-frequency = <16640000>; +-}; +- +-&i2c4 { +- clock-frequency = <400000>; +- +- versaclock6: clock-generator@6a { +- compatible = "idt,5p49v6901"; +- reg = <0x6a>; +- #clock-cells = <1>; +- clocks = <&x23_clk>; +- clock-names = "xin"; +- }; +-}; +- +-#ifdef SOC_HAS_SATA +-&pca9654 { +- pcie-sata-switch-hog { +- gpio-hog; +- gpios = <7 GPIO_ACTIVE_HIGH>; +- output-low; /* enable SATA by default */ +- line-name = "PCIE/SATA switch"; +- }; +-}; +- +-/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */ +-#endif /* SOC_HAS_SATA */ +- +-#ifdef SOC_HAS_USB2_CH3 +-&ehci3 { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&hsusb3 { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&ohci3 { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&pfc { +- /* +- * - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins +- * (when SW31 is the default setting on Salvator-XS). +- * - If SW31 is the default setting, you cannot use USB2.0 ch3 on +- * r8a77951 with Salvator-XS. +- * Hence the SW31 setting must be changed like 2) below. +- * 1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF: +- * - Connect GP6_3[01] to ADV7842. +- * 2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON: +- * - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power). +- * - Connect GP6_{04,21} to ADV7842. +- */ +- usb2_ch3_pins: usb2_ch3 { +- groups = "usb2_ch3"; +- function = "usb2_ch3"; +- }; +-}; +- +-&usb2_phy3 { +- pinctrl-0 = <&usb2_ch3_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +-#endif /* SOC_HAS_USB2_CH3 */ +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/ulcb-kf.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/ulcb-kf.dtsi +deleted file mode 100644 +index 61bd4df09df0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/ulcb-kf.dtsi ++++ /dev/null +@@ -1,383 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the Kingfisher (ULCB extension) board +- * +- * Copyright (C) 2017 Renesas Electronics Corp. +- * Copyright (C) 2017 Cogent Embedded, Inc. +- */ +- +-/* +- * SSI-PCM3168A +- * aplay -D plughw:0,2 xxx.wav +- * arecord -D plughw:0,3 xxx.wav +- */ +- +-/ { +- aliases { +- serial1 = &hscif0; +- serial2 = &scif1; +- mmc2 = &sdhi3; +- }; +- +- clksndsel: clksndsel { +- #clock-cells = <0>; +- compatible = "gpio-mux-clock"; +- clocks = <&cs2000>, <&audio_clk_a>; /* clk8snd, clksnd */ +- select-gpios = <&gpio_exp_75 13 GPIO_ACTIVE_HIGH>; +- }; +- +- snd_3p3v: regulator-snd_3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "snd-3.3v"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- snd_vcc5v: regulator-snd_vcc5v { +- compatible = "regulator-fixed"; +- regulator-name = "snd-vcc5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- wlan_en: regulator-wlan_en { +- compatible = "regulator-fixed"; +- regulator-name = "wlan-en-regulator"; +- +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio_exp_74 4 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <70000>; +- enable-active-high; +- }; +-}; +- +-&can0 { +- pinctrl-0 = <&can0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&can1 { +- pinctrl-0 = <&can1_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&ehci0 { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&hscif0 { +- pinctrl-0 = <&hscif0_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- +- status = "okay"; +-}; +- +-&hsusb { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&i2c2 { +- i2cswitch2: i2c-switch@71 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x71>; +- reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; +- +- /* Audio_SDA, Audio_SCL */ +- i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- +- pcm3168a: audio-codec@44 { +- #sound-dai-cells = <0>; +- compatible = "ti,pcm3168a"; +- reg = <0x44>; +- clocks = <&clksndsel>; +- clock-names = "scki"; +- +- VDD1-supply = <&snd_3p3v>; +- VDD2-supply = <&snd_3p3v>; +- VCCAD1-supply = <&snd_vcc5v>; +- VCCAD2-supply = <&snd_vcc5v>; +- VCCDA1-supply = <&snd_vcc5v>; +- VCCDA2-supply = <&snd_vcc5v>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- mclk-fs = <512>; +- port@0 { +- reg = <0>; +- pcm3168a_endpoint_p: endpoint { +- remote-endpoint = <&rsnd_for_pcm3168a_play>; +- clocks = <&clksndsel>; +- }; +- }; +- port@1 { +- reg = <1>; +- pcm3168a_endpoint_c: endpoint { +- remote-endpoint = <&rsnd_for_pcm3168a_capture>; +- clocks = <&clksndsel>; +- }; +- }; +- }; +- }; +- }; +- }; +- +- /* U11 */ +- gpio_exp_74: gpio@74 { +- compatible = "ti,tca9539"; +- reg = <0x74>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- interrupt-parent = <&gpio6>; +- interrupts = <8 IRQ_TYPE_EDGE_FALLING>; +- +- audio-out-off-hog { +- gpio-hog; +- gpios = <0 GPIO_ACTIVE_HIGH>; /* P00 */ +- output-high; +- line-name = "Audio_Out_OFF"; +- }; +- +- hub-pwen-hog { +- gpio-hog; +- gpios = <6 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "HUB pwen"; +- }; +- +- hub-rst-hog { +- gpio-hog; +- gpios = <7 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "HUB rst"; +- }; +- +- otg-extlpn-hog { +- gpio-hog; +- gpios = <9 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "OTG EXTLPn"; +- }; +- +- otg-offvbusn-hog { +- gpio-hog; +- gpios = <8 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "OTG OFFVBUSn"; +- }; +- +- sd-wifi-mux-hog { +- gpio-hog; +- gpios = <5 GPIO_ACTIVE_HIGH>; +- output-low; /* Connect WL1837 */ +- line-name = "SD WiFi mux"; +- }; +- +- snd-rst-hog { +- gpio-hog; +- gpios = <15 GPIO_ACTIVE_HIGH>; /* P17 */ +- output-high; +- line-name = "SND_RST"; +- }; +- }; +- +- /* U5 */ +- gpio_exp_75: gpio@75 { +- compatible = "ti,tca9539"; +- reg = <0x75>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- interrupt-parent = <&gpio6>; +- interrupts = <4 IRQ_TYPE_EDGE_FALLING>; +- }; +-}; +- +-&i2c4 { +- i2cswitch4: i2c-switch@71 { +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x71>; +- reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; +- }; +- +- gpio_exp_76: gpio@76 { +- compatible = "ti,tca9539"; +- reg = <0x76>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- interrupt-parent = <&gpio7>; +- interrupts = <3 IRQ_TYPE_EDGE_FALLING>; +- }; +- +- gpio_exp_77: gpio@77 { +- compatible = "ti,tca9539"; +- reg = <0x77>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- interrupt-parent = <&gpio5>; +- interrupts = <9 IRQ_TYPE_EDGE_FALLING>; +- }; +-}; +- +-&ohci0 { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&pcie_bus_clk { +- clock-frequency = <100000000>; +-}; +- +-&pciec0 { +- status = "okay"; +-}; +- +-&pciec1 { +- status = "okay"; +-}; +- +-&pfc { +- can0_pins: can0 { +- groups = "can0_data_a"; +- function = "can0"; +- }; +- +- can1_pins: can1 { +- groups = "can1_data"; +- function = "can1"; +- }; +- +- hscif0_pins: hscif0 { +- groups = "hscif0_data", "hscif0_ctrl"; +- function = "hscif0"; +- }; +- +- scif1_pins: scif1 { +- groups = "scif1_data_b", "scif1_ctrl"; +- function = "scif1"; +- }; +- +- sdhi3_pins: sdhi3 { +- groups = "sdhi3_data4", "sdhi3_ctrl"; +- function = "sdhi3"; +- power-source = <3300>; +- }; +- +- sound_pcm_pins: sound-pcm { +- groups = "ssi349_ctrl", "ssi3_data", "ssi4_data"; +- function = "ssi"; +- }; +- +- usb0_pins: usb0 { +- groups = "usb0"; +- function = "usb0"; +- }; +-}; +- +-&rcar_sound { +- pinctrl-0 = <&sound_pins +- &sound_clk_pins +- &sound_pcm_pins>; +- +- ports { +- /* rsnd_port0/1 are on salvator-common */ +- rsnd_port2: port@2 { +- reg = <2>; +- rsnd_for_pcm3168a_play: endpoint { +- remote-endpoint = <&pcm3168a_endpoint_p>; +- +- dai-format = "i2s"; +- bitclock-master = <&rsnd_for_pcm3168a_play>; +- frame-master = <&rsnd_for_pcm3168a_play>; +- dai-tdm-slot-num = <8>; +- +- playback = <&ssi3>; +- }; +- }; +- rsnd_port3: port@3 { +- reg = <3>; +- rsnd_for_pcm3168a_capture: endpoint { +- remote-endpoint = <&pcm3168a_endpoint_c>; +- +- dai-format = "i2s"; +- bitclock-master = <&rsnd_for_pcm3168a_capture>; +- frame-master = <&rsnd_for_pcm3168a_capture>; +- dai-tdm-slot-num = <6>; +- +- capture = <&ssi4>; +- }; +- }; +- }; +-}; +- +-&scif1 { +- pinctrl-0 = <&scif1_pins>; +- pinctrl-names = "default"; +- uart-has-rtscts; +- +- status = "okay"; +-}; +- +-&sdhi3 { +- pinctrl-0 = <&sdhi3_pins>; +- pinctrl-names = "default"; +- +- vmmc-supply = <&wlan_en>; +- vqmmc-supply = <&wlan_en>; +- bus-width = <4>; +- no-1-8-v; +- non-removable; +- cap-power-off-card; +- keep-power-in-suspend; +- max-frequency = <26000000>; +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wlcore@2 { +- compatible = "ti,wl1837"; +- reg = <2>; +- interrupt-parent = <&gpio1>; +- interrupts = <25 IRQ_TYPE_EDGE_FALLING>; +- }; +-}; +- +-&sound_card { +- dais = <&rsnd_port0 /* ak4613 */ +- &rsnd_port1 /* HDMI0 */ +- &rsnd_port2 /* pcm3168a playback */ +- &rsnd_port3 /* pcm3168a capture */ +- >; +-}; +- +-&ssi4 { +- shared-pin; +-}; +- +-&usb2_phy0 { +- pinctrl-0 = <&usb0_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&xhci0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/renesas/ulcb.dtsi b/scripts/dtc/include-prefixes/arm64/renesas/ulcb.dtsi +deleted file mode 100644 +index 1f177af3eb9d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/renesas/ulcb.dtsi ++++ /dev/null +@@ -1,493 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for the R-Car Gen3 ULCB board +- * +- * Copyright (C) 2016 Renesas Electronics Corp. +- * Copyright (C) 2016 Cogent Embedded, Inc. +- */ +- +-/* +- * SSI-AK4613 +- * aplay -D plughw:0,0 xxx.wav +- * arecord -D plughw:0,0 xxx.wav +- * SSI-HDMI +- * aplay -D plughw:0,1 xxx.wav +- */ +- +-#include +-#include +- +-/ { +- model = "Renesas R-Car Gen3 ULCB board"; +- +- aliases { +- serial0 = &scif2; +- ethernet0 = &avb; +- mmc0 = &sdhi2; +- mmc1 = &sdhi0; +- }; +- +- chosen { +- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; +- stdout-path = "serial0:115200n8"; +- }; +- +- audio_clkout: audio-clkout { +- /* +- * This is same as <&rcar_sound 0> +- * but needed to avoid cs2000/rcar_sound probe dead-lock +- */ +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <12288000>; +- }; +- +- hdmi0-out { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi0_con: endpoint { +- }; +- }; +- }; +- +- keyboard { +- compatible = "gpio-keys"; +- +- key-1 { +- linux,code = ; +- label = "SW3"; +- wakeup-source; +- debounce-interval = <20>; +- gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led5 { +- gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; +- }; +- led6 { +- gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- reg_1p8v: regulator0 { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator1 { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- sound_card: sound { +- compatible = "audio-graph-card"; +- label = "rcar-sound"; +- +- dais = <&rsnd_port0 /* ak4613 */ +- &rsnd_port1 /* HDMI0 */ +- >; +- }; +- +- vcc_sdhi0: regulator-vcc-sdhi0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "SDHI0 Vcc"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vccq_sdhi0: regulator-vccq-sdhi0 { +- compatible = "regulator-gpio"; +- +- regulator-name = "SDHI0 VccQ"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; +- gpios-states = <1>; +- states = <3300000 1>, <1800000 0>; +- }; +- +- x12_clk: x12 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +- +- x23_clk: x23-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +-}; +- +-&a57_0 { +- cpu-supply = <&dvfs>; +-}; +- +-&audio_clk_a { +- clock-frequency = <22579200>; +-}; +- +-&avb { +- pinctrl-0 = <&avb_pins>; +- pinctrl-names = "default"; +- phy-handle = <&phy0>; +- tx-internal-delay-ps = <2000>; +- status = "okay"; +- +- phy0: ethernet-phy@0 { +- rxc-skew-ps = <1500>; +- reg = <0>; +- interrupt-parent = <&gpio2>; +- interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&du { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&extal_clk { +- clock-frequency = <16666666>; +-}; +- +-&extalr_clk { +- clock-frequency = <32768>; +-}; +- +-&hdmi0 { +- status = "okay"; +- +- ports { +- port@1 { +- reg = <1>; +- rcar_dw_hdmi0_out: endpoint { +- remote-endpoint = <&hdmi0_con>; +- }; +- }; +- port@2 { +- reg = <2>; +- dw_hdmi0_snd_in: endpoint { +- remote-endpoint = <&rsnd_for_hdmi>; +- }; +- }; +- }; +-}; +- +-&hdmi0_con { +- remote-endpoint = <&rcar_dw_hdmi0_out>; +-}; +- +-&i2c2 { +- pinctrl-0 = <&i2c2_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +- +- clock-frequency = <100000>; +- +- ak4613: codec@10 { +- compatible = "asahi-kasei,ak4613"; +- #sound-dai-cells = <0>; +- reg = <0x10>; +- clocks = <&rcar_sound 3>; +- +- asahi-kasei,in1-single-end; +- asahi-kasei,in2-single-end; +- asahi-kasei,out1-single-end; +- asahi-kasei,out2-single-end; +- asahi-kasei,out3-single-end; +- asahi-kasei,out4-single-end; +- asahi-kasei,out5-single-end; +- asahi-kasei,out6-single-end; +- +- port { +- ak4613_endpoint: endpoint { +- remote-endpoint = <&rsnd_for_ak4613>; +- }; +- }; +- }; +- +- cs2000: clk-multiplier@4f { +- #clock-cells = <0>; +- compatible = "cirrus,cs2000-cp"; +- reg = <0x4f>; +- clocks = <&audio_clkout>, <&x12_clk>; +- clock-names = "clk_in", "ref_clk"; +- +- assigned-clocks = <&cs2000>; +- assigned-clock-rates = <24576000>; /* 1/1 divide */ +- }; +-}; +- +-&i2c4 { +- status = "okay"; +- +- clock-frequency = <400000>; +- +- versaclock5: clock-generator@6a { +- compatible = "idt,5p49v5925"; +- reg = <0x6a>; +- #clock-cells = <1>; +- clocks = <&x23_clk>; +- clock-names = "xin"; +- }; +-}; +- +-&i2c_dvfs { +- status = "okay"; +- +- clock-frequency = <400000>; +- +- pmic: pmic@30 { +- pinctrl-0 = <&irq0_pins>; +- pinctrl-names = "default"; +- +- compatible = "rohm,bd9571mwv"; +- reg = <0x30>; +- interrupt-parent = <&intc_ex>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- rohm,ddr-backup-power = <0xf>; +- rohm,rstbmode-pulse; +- +- regulators { +- dvfs: dvfs { +- regulator-name = "dvfs"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1030000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&pfc { +- pinctrl-0 = <&scif_clk_pins>; +- pinctrl-names = "default"; +- +- avb_pins: avb { +- mux { +- groups = "avb_link", "avb_mdio", "avb_mii"; +- function = "avb"; +- }; +- +- pins_mdio { +- groups = "avb_mdio"; +- drive-strength = <24>; +- }; +- +- pins_mii_tx { +- pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", +- "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; +- drive-strength = <12>; +- }; +- }; +- +- i2c2_pins: i2c2 { +- groups = "i2c2_a"; +- function = "i2c2"; +- }; +- +- irq0_pins: irq0 { +- groups = "intc_ex_irq0"; +- function = "intc_ex"; +- }; +- +- scif2_pins: scif2 { +- groups = "scif2_data_a"; +- function = "scif2"; +- }; +- +- scif_clk_pins: scif_clk { +- groups = "scif_clk_a"; +- function = "scif_clk"; +- }; +- +- sdhi0_pins: sd0 { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <3300>; +- }; +- +- sdhi0_pins_uhs: sd0_uhs { +- groups = "sdhi0_data4", "sdhi0_ctrl"; +- function = "sdhi0"; +- power-source = <1800>; +- }; +- +- sdhi2_pins: sd2 { +- groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; +- function = "sdhi2"; +- power-source = <1800>; +- }; +- +- sound_pins: sound { +- groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; +- function = "ssi"; +- }; +- +- sound_clk_pins: sound-clk { +- groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", +- "audio_clkout_a", "audio_clkout3_a"; +- function = "audio_clk"; +- }; +- +- usb1_pins: usb1 { +- groups = "usb1"; +- function = "usb1"; +- }; +-}; +- +-&rcar_sound { +- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; +- pinctrl-names = "default"; +- +- /* Single DAI */ +- #sound-dai-cells = <0>; +- +- /* audio_clkout0/1/2/3 */ +- #clock-cells = <1>; +- clock-frequency = <12288000 11289600>; +- +- status = "okay"; +- +- /* update to */ +- clocks = <&cpg CPG_MOD 1005>, +- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, +- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, +- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, +- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, +- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, +- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, +- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, +- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, +- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, +- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, +- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, +- <&audio_clk_a>, <&cs2000>, +- <&audio_clk_c>, +- <&cpg CPG_CORE CPG_AUDIO_CLK_I>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- rsnd_port0: port@0 { +- reg = <0>; +- rsnd_for_ak4613: endpoint { +- remote-endpoint = <&ak4613_endpoint>; +- +- dai-format = "left_j"; +- bitclock-master = <&rsnd_for_ak4613>; +- frame-master = <&rsnd_for_ak4613>; +- +- playback = <&ssi0>, <&src0>, <&dvc0>; +- capture = <&ssi1>, <&src1>, <&dvc1>; +- }; +- }; +- rsnd_port1: port@1 { +- reg = <1>; +- rsnd_for_hdmi: endpoint { +- remote-endpoint = <&dw_hdmi0_snd_in>; +- +- dai-format = "i2s"; +- bitclock-master = <&rsnd_for_hdmi>; +- frame-master = <&rsnd_for_hdmi>; +- +- playback = <&ssi2>; +- }; +- }; +- }; +-}; +- +-&rwdt { +- timeout-sec = <60>; +- status = "okay"; +-}; +- +-&scif2 { +- pinctrl-0 = <&scif2_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +- +-&scif_clk { +- clock-frequency = <14745600>; +-}; +- +-&sdhi0 { +- pinctrl-0 = <&sdhi0_pins>; +- pinctrl-1 = <&sdhi0_pins_uhs>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <&vcc_sdhi0>; +- vqmmc-supply = <&vccq_sdhi0>; +- cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; +- bus-width = <4>; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- status = "okay"; +-}; +- +-&sdhi2 { +- /* used for on-board 8bit eMMC */ +- pinctrl-0 = <&sdhi2_pins>; +- pinctrl-1 = <&sdhi2_pins>; +- pinctrl-names = "default", "state_uhs"; +- +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_1p8v>; +- bus-width = <8>; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- no-sd; +- no-sdio; +- non-removable; +- full-pwr-cycle-in-suspend; +- status = "okay"; +-}; +- +-&ssi1 { +- shared-pin; +-}; +- +-&usb2_phy1 { +- pinctrl-0 = <&usb1_pins>; +- pinctrl-names = "default"; +- +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/Makefile b/scripts/dtc/include-prefixes/arm64/rockchip/Makefile +deleted file mode 100644 +index 7fdb41de01ec..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/Makefile ++++ /dev/null +@@ -1,54 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2-of10.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-v.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-kobol-helios64.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-leez-p710.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4b.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-v2.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-common.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-common.dtsi +deleted file mode 100644 +index 3429e124d95a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-common.dtsi ++++ /dev/null +@@ -1,129 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Engicam srl +- * Copyright (c) 2020 Amarula Solutions +- * Copyright (c) 2020 Amarula Solutions(India) +- */ +- +-/ { +- aliases { +- mmc1 = &sdmmc; +- mmc2 = &sdio; +- }; +- +- vcc5v0_sys: vcc5v0-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; /* +5V */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&xin32k>; +- clock-names = "ext_clock"; +- post-power-on-delay-ms = <80>; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_enable_h>; +- }; +- +- vcc3v3_btreg: vcc3v3-btreg { +- compatible = "regulator-gpio"; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_enable_h>; +- regulator-name = "btreg-gpio-supply"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- states = <3300000 0x0>; +- }; +- +- vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_rf_aux_mod"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- xin32k: xin32k { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "xin32k"; +- }; +-}; +- +-&sdio { +- #address-cells = <1>; +- #size-cells = <0>; +- bus-width = <4>; +- clock-frequency = <50000000>; +- cap-sdio-irq; +- cap-sd-highspeed; +- keep-power-in-suspend; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- sd-uhs-sdr104; +- status = "okay"; +- +- brcmf: wifi@1 { +- compatible = "brcm,bcm4329-fmac"; +- reg = <1>; +- }; +-}; +- +-&gmac { +- clock_in_out = "output"; +- phy-supply = <&vcc_3v3>; /* +3V3_SOM */ +- snps,reset-active-low; +- snps,reset-delays-us = <0 50000 50000>; +- snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&sdmmc { +- cap-sd-highspeed; +- card-detect-delay = <800>; +- vmmc-supply = <&vcc_3v3>; /* +3V3_SOM */ +- vqmmc-supply = <&vcc_3v3>; +- status = "okay"; +-}; +- +-&u2phy { +- status = "okay"; +- +- u2phy_host: host-port { +- status = "okay"; +- }; +- +- u2phy_otg: otg-port { +- status = "okay"; +- }; +-}; +- +-&uart2 { +- pinctrl-0 = <&uart2m1_xfer>; +- status = "okay"; +-}; +- +-&usb20_otg { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-ctouch2.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-ctouch2.dtsi +deleted file mode 100644 +index bf10a3d29fca..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-ctouch2.dtsi ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Engicam srl +- * Copyright (c) 2020 Amarula Solutions +- * Copyright (c) 2020 Amarula Solutions(India) +- */ +- +-#include "px30-engicam-common.dtsi" +- +-&pinctrl { +- bt { +- bt_enable_h: bt-enable-h { +- rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdio-pwrseq { +- wifi_enable_h: wifi-enable-h { +- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&sdio_pwrseq { +- reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; +-}; +- +-&vcc3v3_btreg { +- enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-edimm2.2.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-edimm2.2.dtsi +deleted file mode 100644 +index 449b8eb6454e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-edimm2.2.dtsi ++++ /dev/null +@@ -1,66 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Engicam srl +- * Copyright (c) 2020 Amarula Solutions(India) +- */ +- +-#include "px30-engicam-common.dtsi" +- +-/ { +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm0 0 25000 0>; +- }; +- +- panel { +- compatible = "yes-optoelectronics,ytc700tlag-05-201c"; +- backlight = <&backlight>; +- data-mapping = "vesa-24"; +- power-supply = <&vcc3v3_lcd>; +- +- port { +- panel_in_lvds: endpoint { +- remote-endpoint = <&lvds_out_panel>; +- }; +- }; +- }; +-}; +- +-&display_subsystem { +- status = "okay"; +-}; +- +-&dsi_dphy { +- status = "okay"; +-}; +- +-/* LVDS_B(secondary) */ +-&lvds { +- status = "okay"; +- +- ports { +- port@1 { +- reg = <1>; +- +- lvds_out_panel: endpoint { +- remote-endpoint = <&panel_in_lvds>; +- }; +- }; +- }; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-px30-core-ctouch2-of10.dts b/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-px30-core-ctouch2-of10.dts +deleted file mode 100644 +index 47aa30505a42..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-px30-core-ctouch2-of10.dts ++++ /dev/null +@@ -1,77 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd +- * Copyright (c) 2020 Engicam srl +- * Copyright (c) 2020 Amarula Solutions(India) +- */ +- +-/dts-v1/; +-#include "px30.dtsi" +-#include "px30-engicam-ctouch2.dtsi" +-#include "px30-engicam-px30-core.dtsi" +- +-/ { +- model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame"; +- compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core", +- "rockchip,px30"; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm0 0 25000 0>; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- panel { +- compatible = "ampire,am-1280800n3tzqw-t00h"; +- backlight = <&backlight>; +- power-supply = <&vcc3v3_lcd>; +- data-mapping = "vesa-24"; +- +- port { +- panel_in_lvds: endpoint { +- remote-endpoint = <&lvds_out_panel>; +- }; +- }; +- }; +-}; +- +-&display_subsystem { +- status = "okay"; +-}; +- +-&dsi_dphy { +- status = "okay"; +-}; +- +-&lvds { +- status = "okay"; +- +- ports { +- port@1 { +- reg = <1>; +- +- lvds_out_panel: endpoint { +- remote-endpoint = <&panel_in_lvds>; +- }; +- }; +- }; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-px30-core-ctouch2.dts b/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-px30-core-ctouch2.dts +deleted file mode 100644 +index 5a0ecb8faecf..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-px30-core-ctouch2.dts ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd +- * Copyright (c) 2020 Engicam srl +- * Copyright (c) 2020 Amarula Solutions +- * Copyright (c) 2020 Amarula Solutions(India) +- */ +- +-/dts-v1/; +-#include "px30.dtsi" +-#include "px30-engicam-ctouch2.dtsi" +-#include "px30-engicam-px30-core.dtsi" +- +-/ { +- model = "Engicam PX30.Core C.TOUCH 2.0"; +- compatible = "engicam,px30-core-ctouch2", "engicam,px30-core", +- "rockchip,px30"; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-px30-core-edimm2.2.dts b/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-px30-core-edimm2.2.dts +deleted file mode 100644 +index d759478e1c84..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-px30-core-edimm2.2.dts ++++ /dev/null +@@ -1,43 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd +- * Copyright (c) 2020 Engicam srl +- * Copyright (c) 2020 Amarula Solutions(India) +- */ +- +-/dts-v1/; +-#include "px30.dtsi" +-#include "px30-engicam-edimm2.2.dtsi" +-#include "px30-engicam-px30-core.dtsi" +- +-/ { +- model = "Engicam PX30.Core EDIMM2.2 Starter Kit"; +- compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core", +- "rockchip,px30"; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +-}; +- +-&pinctrl { +- bt { +- bt_enable_h: bt-enable-h { +- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdio-pwrseq { +- wifi_enable_h: wifi-enable-h { +- rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&sdio_pwrseq { +- reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; +-}; +- +-&vcc3v3_btreg { +- enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-px30-core.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-px30-core.dtsi +deleted file mode 100644 +index 7249871530ab..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/px30-engicam-px30-core.dtsi ++++ /dev/null +@@ -1,241 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd +- * Copyright (c) 2020 Engicam srl +- * Copyright (c) 2020 Amarula Solutons +- * Copyright (c) 2020 Amarula Solutons(India) +- */ +- +-#include +-#include +- +-/ { +- compatible = "engicam,px30-core", "rockchip,px30"; +- +- aliases { +- mmc0 = &emmc; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&emmc { +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +- non-removable; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- rk809: pmic@20 { +- compatible = "rockchip,rk809"; +- reg = <0x20>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int>; +- rockchip,system-power-controller; +- wakeup-source; +- #clock-cells = <1>; +- clock-output-names = "rk808-clkout1", "rk808-clkout2"; +- +- vcc1-supply = <&vcc5v0_sys>; +- vcc2-supply = <&vcc5v0_sys>; +- vcc3-supply = <&vcc5v0_sys>; +- vcc4-supply = <&vcc5v0_sys>; +- vcc5-supply = <&vcc3v3_sys>; +- vcc6-supply = <&vcc3v3_sys>; +- vcc7-supply = <&vcc3v3_sys>; +- vcc8-supply = <&vcc3v3_sys>; +- vcc9-supply = <&vcc5v0_sys>; +- +- regulators { +- vdd_log: DCDC_REG1 { +- regulator-name = "vdd_log"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <950000>; +- }; +- }; +- +- vdd_arm: DCDC_REG2 { +- regulator-name = "vdd_arm"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <950000>; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_3v3: DCDC_REG4 { +- regulator-name = "vcc_3v3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc3v3_sys: DCDC_REG5 { +- regulator-name = "vcc3v3_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_1v0: LDO_REG1 { +- regulator-name = "vcc_1v0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc_1v8: LDO_REG2 { +- regulator-name = "vcc_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vdd_1v0: LDO_REG3 { +- regulator-name = "vdd_1v0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc3v0_pmu: LDO_REG4 { +- regulator-name = "vcc3v0_pmu"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- +- }; +- }; +- +- vccio_sd: LDO_REG5 { +- regulator-name = "vccio_sd"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc3v3_lcd: SWITCH_REG1 { +- regulator-boot-on; +- regulator-name = "vcc3v3_lcd"; +- }; +- +- vcc5v0_host: SWITCH_REG2 { +- regulator-name = "vcc5v0_host"; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&io_domains { +- vccio1-supply = <&vcc_3v3>; +- vccio2-supply = <&vcc_3v3>; +- vccio3-supply = <&vcc_3v3>; +- vccio4-supply = <&vcc_3v3>; +- vccio5-supply = <&vcc_3v3>; +- vccio6-supply = <&vcc_1v8>; +- status = "okay"; +-}; +- +-&pinctrl { +- pmic { +- pmic_int: pmic_int { +- rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +- +-&pmu_io_domains { +- pmuio1-supply = <&vcc_3v3>; +- pmuio2-supply = <&vcc_3v3>; +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <1>; +- rockchip,hw-tshut-polarity = <1>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/px30-evb.dts b/scripts/dtc/include-prefixes/arm64/rockchip/px30-evb.dts +deleted file mode 100644 +index c1ce9c295e5b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/px30-evb.dts ++++ /dev/null +@@ -1,582 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd +- */ +- +-/dts-v1/; +-#include +-#include +-#include +-#include "px30.dtsi" +- +-/ { +- model = "Rockchip PX30 EVB"; +- compatible = "rockchip,px30-evb", "rockchip,px30"; +- +- aliases { +- mmc0 = &sdmmc; +- mmc1 = &sdio; +- mmc2 = &emmc; +- }; +- +- chosen { +- stdout-path = "serial5:115200n8"; +- }; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 2>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1800000>; +- poll-interval = <100>; +- +- esc-key { +- label = "esc"; +- linux,code = ; +- press-threshold-microvolt = <1310000>; +- }; +- +- home-key { +- label = "home"; +- linux,code = ; +- press-threshold-microvolt = <624000>; +- }; +- +- menu-key { +- label = "menu"; +- linux,code = ; +- press-threshold-microvolt = <987000>; +- }; +- +- vol-down-key { +- label = "volume down"; +- linux,code = ; +- press-threshold-microvolt = <300000>; +- }; +- +- vol-up-key { +- label = "volume up"; +- linux,code = ; +- press-threshold-microvolt = <17000>; +- }; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm1 0 25000 0>; +- power-supply = <&vcc3v3_lcd>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- pinctrl-0 = <&emmc_reset>; +- pinctrl-names = "default"; +- reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_enable_h>; +- +- /* +- * On the module itself this is one of these (depending +- * on the actual card populated): +- * - SDIO_RESET_L_WL_REG_ON +- * - PDN (power down when low) +- */ +- reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ +- }; +- +- vcc5v0_sys: vccsys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&display_subsystem { +- status = "okay"; +-}; +- +-&dsi { +- status = "okay"; +- +- ports { +- mipi_out: port@1 { +- reg = <1>; +- +- mipi_out_panel: endpoint { +- remote-endpoint = <&mipi_in_panel>; +- }; +- }; +- }; +- +- panel@0 { +- compatible = "xinpeng,xpp055c272"; +- reg = <0>; +- backlight = <&backlight>; +- iovcc-supply = <&vcc_1v8>; +- vci-supply = <&vcc3v3_lcd>; +- +- port { +- mipi_in_panel: endpoint { +- remote-endpoint = <&mipi_out_panel>; +- }; +- }; +- }; +-}; +- +-&dsi_dphy { +- status = "okay"; +-}; +- +-&emmc { +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +- non-removable; +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v0>; +- vqmmc-supply = <&vccio_flash>; +- status = "okay"; +-}; +- +-&gmac { +- clock_in_out = "output"; +- phy-supply = <&vcc_rmii>; +- snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 50000 50000>; +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&vdd_log>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- rk809: pmic@20 { +- compatible = "rockchip,rk809"; +- reg = <0x20>; +- interrupt-parent = <&gpio0>; +- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int>; +- rockchip,system-power-controller; +- wakeup-source; +- #clock-cells = <0>; +- clock-output-names = "xin32k"; +- +- vcc1-supply = <&vcc5v0_sys>; +- vcc2-supply = <&vcc5v0_sys>; +- vcc3-supply = <&vcc5v0_sys>; +- vcc4-supply = <&vcc5v0_sys>; +- vcc5-supply = <&vcc3v3_sys>; +- vcc6-supply = <&vcc3v3_sys>; +- vcc7-supply = <&vcc3v3_sys>; +- vcc8-supply = <&vcc3v3_sys>; +- vcc9-supply = <&vcc5v0_sys>; +- +- regulators { +- vdd_log: DCDC_REG1 { +- regulator-name = "vdd_log"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <950000>; +- }; +- }; +- +- vdd_arm: DCDC_REG2 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <950000>; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_3v0: vcc_rmii: DCDC_REG4 { +- regulator-name = "vcc_3v0"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc3v3_sys: DCDC_REG5 { +- regulator-name = "vcc3v3_sys"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_1v0: LDO_REG1 { +- regulator-name = "vcc_1v0"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc_1v8: vccio_flash: vccio_sdio: LDO_REG2 { +- regulator-name = "vcc_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vdd_1v0: LDO_REG3 { +- regulator-name = "vdd_1v0"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc3v0_pmu: LDO_REG4 { +- regulator-name = "vcc3v0_pmu"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vccio_sd: LDO_REG5 { +- regulator-name = "vccio_sd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_sd: LDO_REG6 { +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc2v8_dvp: LDO_REG7 { +- regulator-name = "vcc2v8_dvp"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <2800000>; +- }; +- }; +- +- vcc1v8_dvp: LDO_REG8 { +- regulator-name = "vcc1v8_dvp"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc1v5_dvp: LDO_REG9 { +- regulator-name = "vcc1v5_dvp"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <1500000>; +- }; +- }; +- +- vcc3v3_lcd: SWITCH_REG1 { +- regulator-name = "vcc3v3_lcd"; +- regulator-boot-on; +- }; +- +- vcc5v0_host: SWITCH_REG2 { +- regulator-name = "vcc5v0_host"; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- sensor@d { +- compatible = "asahi-kasei,ak8963"; +- reg = <0x0d>; +- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; +- vdd-supply = <&vcc3v0_pmu>; +- mount-matrix = "1", /* x0 */ +- "0", /* y0 */ +- "0", /* z0 */ +- "0", /* x1 */ +- "1", /* y1 */ +- "0", /* z1 */ +- "0", /* x2 */ +- "0", /* y2 */ +- "1"; /* z2 */ +- }; +- +- touchscreen@14 { +- compatible = "goodix,gt1151"; +- reg = <0x14>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- irq-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; +- reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; +- VDDIO-supply = <&vcc3v3_lcd>; +- }; +- +- sensor@4c { +- compatible = "fsl,mma7660"; +- reg = <0x4c>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- }; +-}; +- +-&i2s1_2ch { +- status = "okay"; +-}; +- +-&io_domains { +- status = "okay"; +- +- vccio1-supply = <&vccio_sdio>; +- vccio2-supply = <&vccio_sd>; +- vccio3-supply = <&vcc_3v0>; +- vccio4-supply = <&vcc3v0_pmu>; +- vccio5-supply = <&vcc_3v0>; +- vccio6-supply = <&vccio_flash>; +-}; +- +-&pinctrl { +- headphone { +- hp_det: hp-det { +- rockchip,pins = +- <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- emmc { +- emmc_reset: emmc-reset { +- rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- pmic_int: pmic_int { +- rockchip,pins = +- <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- soc_slppin_gpio: soc_slppin_gpio { +- rockchip,pins = +- <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- +- soc_slppin_slp: soc_slppin_slp { +- rockchip,pins = +- <0 RK_PA4 1 &pcfg_pull_none>; +- }; +- +- soc_slppin_rst: soc_slppin_rst { +- rockchip,pins = +- <0 RK_PA4 2 &pcfg_pull_none>; +- }; +- }; +- +- sdio-pwrseq { +- wifi_enable_h: wifi-enable-h { +- rockchip,pins = +- <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pmu_io_domains { +- status = "okay"; +- +- pmuio1-supply = <&vcc3v0_pmu>; +- pmuio2-supply = <&vcc3v0_pmu>; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vcc_1v8>; +- status = "okay"; +-}; +- +-&sdmmc { +- cap-mmc-highspeed; +- cap-sd-highspeed; +- card-detect-delay = <800>; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- vmmc-supply = <&vcc_sd>; +- vqmmc-supply = <&vccio_sd>; +- status = "okay"; +-}; +- +-&sdio { +- cap-sd-highspeed; +- keep-power-in-suspend; +- non-removable; +- mmc-pwrseq = <&sdio_pwrseq>; +- sd-uhs-sdr104; +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <1>; +- rockchip,hw-tshut-polarity = <1>; +- status = "okay"; +-}; +- +-&u2phy { +- status = "okay"; +- +- u2phy_host: host-port { +- status = "okay"; +- }; +- +- u2phy_otg: otg-port { +- status = "okay"; +- }; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_xfer &uart1_cts>; +- status = "okay"; +-}; +- +-&uart5 { +- status = "okay"; +-}; +- +-&usb20_otg { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/px30.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/px30.dtsi +deleted file mode 100644 +index 5200d0bbd9e9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/px30.dtsi ++++ /dev/null +@@ -1,2275 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "rockchip,px30"; +- +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- ethernet0 = &gmac; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- serial5 = &uart5; +- spi0 = &spi0; +- spi1 = &spi1; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- clocks = <&cru ARMCLK>; +- #cooling-cells = <2>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; +- dynamic-power-coefficient = <90>; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- clocks = <&cru ARMCLK>; +- #cooling-cells = <2>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; +- dynamic-power-coefficient = <90>; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- clocks = <&cru ARMCLK>; +- #cooling-cells = <2>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; +- dynamic-power-coefficient = <90>; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- clocks = <&cru ARMCLK>; +- #cooling-cells = <2>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; +- dynamic-power-coefficient = <90>; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP: cpu-sleep { +- compatible = "arm,idle-state"; +- local-timer-stop; +- arm,psci-suspend-param = <0x0010000>; +- entry-latency-us = <120>; +- exit-latency-us = <250>; +- min-residency-us = <900>; +- }; +- +- CLUSTER_SLEEP: cluster-sleep { +- compatible = "arm,idle-state"; +- local-timer-stop; +- arm,psci-suspend-param = <0x1010000>; +- entry-latency-us = <400>; +- exit-latency-us = <500>; +- min-residency-us = <2000>; +- }; +- }; +- }; +- +- cpu0_opp_table: cpu0-opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <950000 950000 1350000>; +- clock-latency-ns = <40000>; +- opp-suspend; +- }; +- opp-816000000 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <1050000 1050000 1350000>; +- clock-latency-ns = <40000>; +- }; +- opp-1008000000 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <1175000 1175000 1350000>; +- clock-latency-ns = <40000>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <1300000 1300000 1350000>; +- clock-latency-ns = <40000>; +- }; +- opp-1296000000 { +- opp-hz = /bits/ 64 <1296000000>; +- opp-microvolt = <1350000 1350000 1350000>; +- clock-latency-ns = <40000>; +- }; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a35-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- display_subsystem: display-subsystem { +- compatible = "rockchip,display-subsystem"; +- ports = <&vopb_out>, <&vopl_out>; +- status = "disabled"; +- }; +- +- gmac_clkin: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- clock-output-names = "gmac_clkin"; +- #clock-cells = <0>; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- thermal_zones: thermal-zones { +- soc_thermal: soc-thermal { +- polling-delay-passive = <20>; +- polling-delay = <1000>; +- sustainable-power = <750>; +- thermal-sensors = <&tsadc 0>; +- +- trips { +- threshold: trip-point-0 { +- temperature = <70000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- target: trip-point-1 { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- +- soc_crit: soc-crit { +- temperature = <115000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&target>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- contribution = <4096>; +- }; +- +- map1 { +- trip = <&target>; +- cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- contribution = <4096>; +- }; +- }; +- }; +- +- gpu_thermal: gpu-thermal { +- polling-delay-passive = <100>; /* milliseconds */ +- polling-delay = <1000>; /* milliseconds */ +- thermal-sensors = <&tsadc 1>; +- }; +- }; +- +- xin24m: xin24m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "xin24m"; +- }; +- +- pmu: power-management@ff000000 { +- compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; +- reg = <0x0 0xff000000 0x0 0x1000>; +- +- power: power-controller { +- compatible = "rockchip,px30-power-controller"; +- #power-domain-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* These power domains are grouped by VD_LOGIC */ +- power-domain@PX30_PD_USB { +- reg = ; +- clocks = <&cru HCLK_HOST>, +- <&cru HCLK_OTG>, +- <&cru SCLK_OTG_ADP>; +- pm_qos = <&qos_usb_host>, <&qos_usb_otg>; +- #power-domain-cells = <0>; +- }; +- power-domain@PX30_PD_SDCARD { +- reg = ; +- clocks = <&cru HCLK_SDMMC>, +- <&cru SCLK_SDMMC>; +- pm_qos = <&qos_sdmmc>; +- #power-domain-cells = <0>; +- }; +- power-domain@PX30_PD_GMAC { +- reg = ; +- clocks = <&cru ACLK_GMAC>, +- <&cru PCLK_GMAC>, +- <&cru SCLK_MAC_REF>, +- <&cru SCLK_GMAC_RX_TX>; +- pm_qos = <&qos_gmac>; +- #power-domain-cells = <0>; +- }; +- power-domain@PX30_PD_MMC_NAND { +- reg = ; +- clocks = <&cru HCLK_NANDC>, +- <&cru HCLK_EMMC>, +- <&cru HCLK_SDIO>, +- <&cru HCLK_SFC>, +- <&cru SCLK_EMMC>, +- <&cru SCLK_NANDC>, +- <&cru SCLK_SDIO>, +- <&cru SCLK_SFC>; +- pm_qos = <&qos_emmc>, <&qos_nand>, +- <&qos_sdio>, <&qos_sfc>; +- #power-domain-cells = <0>; +- }; +- power-domain@PX30_PD_VPU { +- reg = ; +- clocks = <&cru ACLK_VPU>, +- <&cru HCLK_VPU>, +- <&cru SCLK_CORE_VPU>; +- pm_qos = <&qos_vpu>, <&qos_vpu_r128>; +- #power-domain-cells = <0>; +- }; +- power-domain@PX30_PD_VO { +- reg = ; +- clocks = <&cru ACLK_RGA>, +- <&cru ACLK_VOPB>, +- <&cru ACLK_VOPL>, +- <&cru DCLK_VOPB>, +- <&cru DCLK_VOPL>, +- <&cru HCLK_RGA>, +- <&cru HCLK_VOPB>, +- <&cru HCLK_VOPL>, +- <&cru PCLK_MIPI_DSI>, +- <&cru SCLK_RGA_CORE>, +- <&cru SCLK_VOPB_PWM>; +- pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, +- <&qos_vop_m0>, <&qos_vop_m1>; +- #power-domain-cells = <0>; +- }; +- power-domain@PX30_PD_VI { +- reg = ; +- clocks = <&cru ACLK_CIF>, +- <&cru ACLK_ISP>, +- <&cru HCLK_CIF>, +- <&cru HCLK_ISP>, +- <&cru SCLK_ISP>; +- pm_qos = <&qos_isp_128>, <&qos_isp_rd>, +- <&qos_isp_wr>, <&qos_isp_m1>, +- <&qos_vip>; +- #power-domain-cells = <0>; +- }; +- power-domain@PX30_PD_GPU { +- reg = ; +- clocks = <&cru SCLK_GPU>; +- pm_qos = <&qos_gpu>; +- #power-domain-cells = <0>; +- }; +- }; +- }; +- +- pmugrf: syscon@ff010000 { +- compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; +- reg = <0x0 0xff010000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- pmu_io_domains: io-domains { +- compatible = "rockchip,px30-pmu-io-voltage-domain"; +- status = "disabled"; +- }; +- +- reboot-mode { +- compatible = "syscon-reboot-mode"; +- offset = <0x200>; +- mode-bootloader = ; +- mode-fastboot = ; +- mode-loader = ; +- mode-normal = ; +- mode-recovery = ; +- }; +- }; +- +- uart0: serial@ff030000 { +- compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff030000 0x0 0x100>; +- interrupts = ; +- clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac 0>, <&dmac 1>; +- dma-names = "tx", "rx"; +- reg-shift = <2>; +- reg-io-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +- status = "disabled"; +- }; +- +- i2s1_2ch: i2s@ff070000 { +- compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; +- reg = <0x0 0xff070000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; +- clock-names = "i2s_clk", "i2s_hclk"; +- dmas = <&dmac 18>, <&dmac 19>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck +- &i2s1_2ch_sdi &i2s1_2ch_sdo>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- i2s2_2ch: i2s@ff080000 { +- compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; +- reg = <0x0 0xff080000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; +- clock-names = "i2s_clk", "i2s_hclk"; +- dmas = <&dmac 20>, <&dmac 21>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck +- &i2s2_2ch_sdi &i2s2_2ch_sdo>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@ff131000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x0 0xff131000 0 0x1000>, +- <0x0 0xff132000 0 0x2000>, +- <0x0 0xff134000 0 0x2000>, +- <0x0 0xff136000 0 0x2000>; +- interrupts = ; +- }; +- +- grf: syscon@ff140000 { +- compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; +- reg = <0x0 0xff140000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- io_domains: io-domains { +- compatible = "rockchip,px30-io-voltage-domain"; +- status = "disabled"; +- }; +- +- lvds: lvds { +- compatible = "rockchip,px30-lvds"; +- phys = <&dsi_dphy>; +- phy-names = "dphy"; +- rockchip,grf = <&grf>; +- rockchip,output = "lvds"; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- lvds_vopb_in: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vopb_out_lvds>; +- }; +- +- lvds_vopl_in: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vopl_out_lvds>; +- }; +- }; +- }; +- }; +- }; +- +- uart1: serial@ff158000 { +- compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff158000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac 2>, <&dmac 3>; +- dma-names = "tx", "rx"; +- reg-shift = <2>; +- reg-io-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; +- status = "disabled"; +- }; +- +- uart2: serial@ff160000 { +- compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff160000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac 4>, <&dmac 5>; +- dma-names = "tx", "rx"; +- reg-shift = <2>; +- reg-io-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2m0_xfer>; +- status = "disabled"; +- }; +- +- uart3: serial@ff168000 { +- compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff168000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac 6>, <&dmac 7>; +- dma-names = "tx", "rx"; +- reg-shift = <2>; +- reg-io-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; +- status = "disabled"; +- }; +- +- uart4: serial@ff170000 { +- compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff170000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac 8>, <&dmac 9>; +- dma-names = "tx", "rx"; +- reg-shift = <2>; +- reg-io-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; +- status = "disabled"; +- }; +- +- uart5: serial@ff178000 { +- compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff178000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac 10>, <&dmac 11>; +- dma-names = "tx", "rx"; +- reg-shift = <2>; +- reg-io-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; +- status = "disabled"; +- }; +- +- i2c0: i2c@ff180000 { +- compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xff180000 0x0 0x1000>; +- clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_xfer>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@ff190000 { +- compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xff190000 0x0 0x1000>; +- clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_xfer>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@ff1a0000 { +- compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xff1a0000 0x0 0x1000>; +- clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_xfer>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@ff1b0000 { +- compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xff1b0000 0x0 0x1000>; +- clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_xfer>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi0: spi@ff1d0000 { +- compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xff1d0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; +- clock-names = "spiclk", "apb_pclk"; +- dmas = <&dmac 12>, <&dmac 13>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi1: spi@ff1d8000 { +- compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xff1d8000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; +- clock-names = "spiclk", "apb_pclk"; +- dmas = <&dmac 14>, <&dmac 15>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- wdt: watchdog@ff1e0000 { +- compatible = "rockchip,px30-wdt", "snps,dw-wdt"; +- reg = <0x0 0xff1e0000 0x0 0x100>; +- clocks = <&cru PCLK_WDT_NS>; +- interrupts = ; +- status = "disabled"; +- }; +- +- pwm0: pwm@ff200000 { +- compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff200000 0x0 0x10>; +- clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm1: pwm@ff200010 { +- compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff200010 0x0 0x10>; +- clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm1_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm2: pwm@ff200020 { +- compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff200020 0x0 0x10>; +- clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm2_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm3: pwm@ff200030 { +- compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff200030 0x0 0x10>; +- clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm3_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm4: pwm@ff208000 { +- compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff208000 0x0 0x10>; +- clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm4_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm5: pwm@ff208010 { +- compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff208010 0x0 0x10>; +- clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm5_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm6: pwm@ff208020 { +- compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff208020 0x0 0x10>; +- clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm6_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm7: pwm@ff208030 { +- compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff208030 0x0 0x10>; +- clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm7_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- rktimer: timer@ff210000 { +- compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; +- reg = <0x0 0xff210000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; +- clock-names = "pclk", "timer"; +- }; +- +- dmac: dma-controller@ff240000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xff240000 0x0 0x4000>; +- interrupts = , +- ; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMAC>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- }; +- +- tsadc: tsadc@ff280000 { +- compatible = "rockchip,px30-tsadc"; +- reg = <0x0 0xff280000 0x0 0x100>; +- interrupts = ; +- assigned-clocks = <&cru SCLK_TSADC>; +- assigned-clock-rates = <50000>; +- clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; +- clock-names = "tsadc", "apb_pclk"; +- resets = <&cru SRST_TSADC>; +- reset-names = "tsadc-apb"; +- rockchip,grf = <&grf>; +- rockchip,hw-tshut-temp = <120000>; +- pinctrl-names = "init", "default", "sleep"; +- pinctrl-0 = <&tsadc_otp_pin>; +- pinctrl-1 = <&tsadc_otp_out>; +- pinctrl-2 = <&tsadc_otp_pin>; +- #thermal-sensor-cells = <1>; +- status = "disabled"; +- }; +- +- saradc: saradc@ff288000 { +- compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; +- reg = <0x0 0xff288000 0x0 0x100>; +- interrupts = ; +- #io-channel-cells = <1>; +- clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; +- clock-names = "saradc", "apb_pclk"; +- resets = <&cru SRST_SARADC_P>; +- reset-names = "saradc-apb"; +- status = "disabled"; +- }; +- +- otp: nvmem@ff290000 { +- compatible = "rockchip,px30-otp"; +- reg = <0x0 0xff290000 0x0 0x4000>; +- clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, +- <&cru PCLK_OTP_PHY>; +- clock-names = "otp", "apb_pclk", "phy"; +- resets = <&cru SRST_OTP_PHY>; +- reset-names = "phy"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* Data cells */ +- cpu_id: id@7 { +- reg = <0x07 0x10>; +- }; +- cpu_leakage: cpu-leakage@17 { +- reg = <0x17 0x1>; +- }; +- performance: performance@1e { +- reg = <0x1e 0x1>; +- bits = <4 3>; +- }; +- }; +- +- cru: clock-controller@ff2b0000 { +- compatible = "rockchip,px30-cru"; +- reg = <0x0 0xff2b0000 0x0 0x1000>; +- clocks = <&xin24m>, <&pmucru PLL_GPLL>; +- clock-names = "xin24m", "gpll"; +- rockchip,grf = <&grf>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- +- assigned-clocks = <&cru PLL_NPLL>, +- <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, +- <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, +- <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; +- +- assigned-clock-rates = <1188000000>, +- <200000000>, <200000000>, +- <150000000>, <150000000>, +- <100000000>, <200000000>; +- }; +- +- pmucru: clock-controller@ff2bc000 { +- compatible = "rockchip,px30-pmucru"; +- reg = <0x0 0xff2bc000 0x0 0x1000>; +- clocks = <&xin24m>; +- clock-names = "xin24m"; +- rockchip,grf = <&grf>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- +- assigned-clocks = +- <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, +- <&pmucru SCLK_WIFI_PMU>; +- assigned-clock-rates = +- <1200000000>, <100000000>, +- <26000000>; +- }; +- +- usb2phy_grf: syscon@ff2c0000 { +- compatible = "rockchip,px30-usb2phy-grf", "syscon", +- "simple-mfd"; +- reg = <0x0 0xff2c0000 0x0 0x10000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- u2phy: usb2phy@100 { +- compatible = "rockchip,px30-usb2phy"; +- reg = <0x100 0x20>; +- clocks = <&pmucru SCLK_USBPHY_REF>; +- clock-names = "phyclk"; +- #clock-cells = <0>; +- assigned-clocks = <&cru USB480M>; +- assigned-clock-parents = <&u2phy>; +- clock-output-names = "usb480m_phy"; +- status = "disabled"; +- +- u2phy_host: host-port { +- #phy-cells = <0>; +- interrupts = ; +- interrupt-names = "linestate"; +- status = "disabled"; +- }; +- +- u2phy_otg: otg-port { +- #phy-cells = <0>; +- interrupts = , +- , +- ; +- interrupt-names = "otg-bvalid", "otg-id", +- "linestate"; +- status = "disabled"; +- }; +- }; +- }; +- +- dsi_dphy: phy@ff2e0000 { +- compatible = "rockchip,px30-dsi-dphy"; +- reg = <0x0 0xff2e0000 0x0 0x10000>; +- clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; +- clock-names = "ref", "pclk"; +- resets = <&cru SRST_MIPIDSIPHY_P>; +- reset-names = "apb"; +- #phy-cells = <0>; +- power-domains = <&power PX30_PD_VO>; +- status = "disabled"; +- }; +- +- usb20_otg: usb@ff300000 { +- compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", +- "snps,dwc2"; +- reg = <0x0 0xff300000 0x0 0x40000>; +- interrupts = ; +- clocks = <&cru HCLK_OTG>; +- clock-names = "otg"; +- dr_mode = "otg"; +- g-np-tx-fifo-size = <16>; +- g-rx-fifo-size = <280>; +- g-tx-fifo-size = <256 128 128 64 32 16>; +- phys = <&u2phy_otg>; +- phy-names = "usb2-phy"; +- power-domains = <&power PX30_PD_USB>; +- status = "disabled"; +- }; +- +- usb_host0_ehci: usb@ff340000 { +- compatible = "generic-ehci"; +- reg = <0x0 0xff340000 0x0 0x10000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST>; +- phys = <&u2phy_host>; +- phy-names = "usb"; +- power-domains = <&power PX30_PD_USB>; +- status = "disabled"; +- }; +- +- usb_host0_ohci: usb@ff350000 { +- compatible = "generic-ohci"; +- reg = <0x0 0xff350000 0x0 0x10000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST>; +- phys = <&u2phy_host>; +- phy-names = "usb"; +- power-domains = <&power PX30_PD_USB>; +- status = "disabled"; +- }; +- +- gmac: ethernet@ff360000 { +- compatible = "rockchip,px30-gmac"; +- reg = <0x0 0xff360000 0x0 0x10000>; +- interrupts = ; +- interrupt-names = "macirq"; +- clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, +- <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, +- <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, +- <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; +- clock-names = "stmmaceth", "mac_clk_rx", +- "mac_clk_tx", "clk_mac_ref", +- "clk_mac_refout", "aclk_mac", +- "pclk_mac", "clk_mac_speed"; +- rockchip,grf = <&grf>; +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; +- power-domains = <&power PX30_PD_GMAC>; +- resets = <&cru SRST_GMAC_A>; +- reset-names = "stmmaceth"; +- status = "disabled"; +- }; +- +- sdmmc: mmc@ff370000 { +- compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xff370000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, +- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- bus-width = <4>; +- fifo-depth = <0x100>; +- max-frequency = <150000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; +- power-domains = <&power PX30_PD_SDCARD>; +- status = "disabled"; +- }; +- +- sdio: mmc@ff380000 { +- compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xff380000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, +- <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- bus-width = <4>; +- fifo-depth = <0x100>; +- max-frequency = <150000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; +- power-domains = <&power PX30_PD_MMC_NAND>; +- status = "disabled"; +- }; +- +- emmc: mmc@ff390000 { +- compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xff390000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, +- <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- bus-width = <8>; +- fifo-depth = <0x100>; +- max-frequency = <150000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +- power-domains = <&power PX30_PD_MMC_NAND>; +- status = "disabled"; +- }; +- +- nfc: nand-controller@ff3b0000 { +- compatible = "rockchip,px30-nfc"; +- reg = <0x0 0xff3b0000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; +- clock-names = "ahb", "nfc"; +- assigned-clocks = <&cru SCLK_NANDC>; +- assigned-clock-rates = <150000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 +- &flash_rdn &flash_rdy &flash_wrn &flash_dqs>; +- power-domains = <&power PX30_PD_MMC_NAND>; +- status = "disabled"; +- }; +- +- gpu_opp_table: opp-table2 { +- compatible = "operating-points-v2"; +- +- opp-200000000 { +- opp-hz = /bits/ 64 <200000000>; +- opp-microvolt = <950000>; +- }; +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <975000>; +- }; +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <1050000>; +- }; +- opp-480000000 { +- opp-hz = /bits/ 64 <480000000>; +- opp-microvolt = <1125000>; +- }; +- }; +- +- gpu: gpu@ff400000 { +- compatible = "rockchip,px30-mali", "arm,mali-bifrost"; +- reg = <0x0 0xff400000 0x0 0x4000>; +- interrupts = , +- , +- ; +- interrupt-names = "job", "mmu", "gpu"; +- clocks = <&cru SCLK_GPU>; +- #cooling-cells = <2>; +- power-domains = <&power PX30_PD_GPU>; +- operating-points-v2 = <&gpu_opp_table>; +- status = "disabled"; +- }; +- +- dsi: dsi@ff450000 { +- compatible = "rockchip,px30-mipi-dsi"; +- reg = <0x0 0xff450000 0x0 0x10000>; +- interrupts = ; +- clocks = <&cru PCLK_MIPI_DSI>; +- clock-names = "pclk"; +- phys = <&dsi_dphy>; +- phy-names = "dphy"; +- power-domains = <&power PX30_PD_VO>; +- resets = <&cru SRST_MIPIDSI_HOST_P>; +- reset-names = "apb"; +- rockchip,grf = <&grf>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- dsi_in_vopb: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vopb_out_dsi>; +- }; +- +- dsi_in_vopl: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vopl_out_dsi>; +- }; +- }; +- }; +- }; +- +- vopb: vop@ff460000 { +- compatible = "rockchip,px30-vop-big"; +- reg = <0x0 0xff460000 0x0 0xefc>; +- interrupts = ; +- clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, +- <&cru HCLK_VOPB>; +- clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; +- resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; +- reset-names = "axi", "ahb", "dclk"; +- iommus = <&vopb_mmu>; +- power-domains = <&power PX30_PD_VO>; +- status = "disabled"; +- +- vopb_out: port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- vopb_out_dsi: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&dsi_in_vopb>; +- }; +- +- vopb_out_lvds: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&lvds_vopb_in>; +- }; +- }; +- }; +- +- vopb_mmu: iommu@ff460f00 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff460f00 0x0 0x100>; +- interrupts = ; +- clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; +- clock-names = "aclk", "iface"; +- power-domains = <&power PX30_PD_VO>; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- vopl: vop@ff470000 { +- compatible = "rockchip,px30-vop-lit"; +- reg = <0x0 0xff470000 0x0 0xefc>; +- interrupts = ; +- clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, +- <&cru HCLK_VOPL>; +- clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; +- resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; +- reset-names = "axi", "ahb", "dclk"; +- iommus = <&vopl_mmu>; +- power-domains = <&power PX30_PD_VO>; +- status = "disabled"; +- +- vopl_out: port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- vopl_out_dsi: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&dsi_in_vopl>; +- }; +- +- vopl_out_lvds: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&lvds_vopl_in>; +- }; +- }; +- }; +- +- vopl_mmu: iommu@ff470f00 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff470f00 0x0 0x100>; +- interrupts = ; +- clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; +- clock-names = "aclk", "iface"; +- power-domains = <&power PX30_PD_VO>; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- qos_gmac: qos@ff518000 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff518000 0x0 0x20>; +- }; +- +- qos_gpu: qos@ff520000 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff520000 0x0 0x20>; +- }; +- +- qos_sdmmc: qos@ff52c000 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff52c000 0x0 0x20>; +- }; +- +- qos_emmc: qos@ff538000 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff538000 0x0 0x20>; +- }; +- +- qos_nand: qos@ff538080 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff538080 0x0 0x20>; +- }; +- +- qos_sdio: qos@ff538100 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff538100 0x0 0x20>; +- }; +- +- qos_sfc: qos@ff538180 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff538180 0x0 0x20>; +- }; +- +- qos_usb_host: qos@ff540000 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff540000 0x0 0x20>; +- }; +- +- qos_usb_otg: qos@ff540080 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff540080 0x0 0x20>; +- }; +- +- qos_isp_128: qos@ff548000 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff548000 0x0 0x20>; +- }; +- +- qos_isp_rd: qos@ff548080 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff548080 0x0 0x20>; +- }; +- +- qos_isp_wr: qos@ff548100 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff548100 0x0 0x20>; +- }; +- +- qos_isp_m1: qos@ff548180 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff548180 0x0 0x20>; +- }; +- +- qos_vip: qos@ff548200 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff548200 0x0 0x20>; +- }; +- +- qos_rga_rd: qos@ff550000 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff550000 0x0 0x20>; +- }; +- +- qos_rga_wr: qos@ff550080 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff550080 0x0 0x20>; +- }; +- +- qos_vop_m0: qos@ff550100 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff550100 0x0 0x20>; +- }; +- +- qos_vop_m1: qos@ff550180 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff550180 0x0 0x20>; +- }; +- +- qos_vpu: qos@ff558000 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff558000 0x0 0x20>; +- }; +- +- qos_vpu_r128: qos@ff558080 { +- compatible = "rockchip,px30-qos", "syscon"; +- reg = <0x0 0xff558080 0x0 0x20>; +- }; +- +- pinctrl: pinctrl { +- compatible = "rockchip,px30-pinctrl"; +- rockchip,grf = <&grf>; +- rockchip,pmu = <&pmugrf>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gpio0: gpio0@ff040000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff040000 0x0 0x100>; +- interrupts = ; +- clocks = <&pmucru PCLK_GPIO0_PMU>; +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio1@ff250000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff250000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO1>; +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio2@ff260000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff260000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO2>; +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio3@ff270000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff270000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO3>; +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pcfg_pull_up: pcfg-pull-up { +- bias-pull-up; +- }; +- +- pcfg_pull_down: pcfg-pull-down { +- bias-pull-down; +- }; +- +- pcfg_pull_none: pcfg-pull-none { +- bias-disable; +- }; +- +- pcfg_pull_none_2ma: pcfg-pull-none-2ma { +- bias-disable; +- drive-strength = <2>; +- }; +- +- pcfg_pull_up_2ma: pcfg-pull-up-2ma { +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- pcfg_pull_up_4ma: pcfg-pull-up-4ma { +- bias-pull-up; +- drive-strength = <4>; +- }; +- +- pcfg_pull_none_4ma: pcfg-pull-none-4ma { +- bias-disable; +- drive-strength = <4>; +- }; +- +- pcfg_pull_down_4ma: pcfg-pull-down-4ma { +- bias-pull-down; +- drive-strength = <4>; +- }; +- +- pcfg_pull_none_8ma: pcfg-pull-none-8ma { +- bias-disable; +- drive-strength = <8>; +- }; +- +- pcfg_pull_up_8ma: pcfg-pull-up-8ma { +- bias-pull-up; +- drive-strength = <8>; +- }; +- +- pcfg_pull_none_12ma: pcfg-pull-none-12ma { +- bias-disable; +- drive-strength = <12>; +- }; +- +- pcfg_pull_up_12ma: pcfg-pull-up-12ma { +- bias-pull-up; +- drive-strength = <12>; +- }; +- +- pcfg_pull_none_smt: pcfg-pull-none-smt { +- bias-disable; +- input-schmitt-enable; +- }; +- +- pcfg_output_high: pcfg-output-high { +- output-high; +- }; +- +- pcfg_output_low: pcfg-output-low { +- output-low; +- }; +- +- pcfg_input_high: pcfg-input-high { +- bias-pull-up; +- input-enable; +- }; +- +- pcfg_input: pcfg-input { +- input-enable; +- }; +- +- i2c0 { +- i2c0_xfer: i2c0-xfer { +- rockchip,pins = +- <0 RK_PB0 1 &pcfg_pull_none_smt>, +- <0 RK_PB1 1 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c1 { +- i2c1_xfer: i2c1-xfer { +- rockchip,pins = +- <0 RK_PC2 1 &pcfg_pull_none_smt>, +- <0 RK_PC3 1 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c2 { +- i2c2_xfer: i2c2-xfer { +- rockchip,pins = +- <2 RK_PB7 2 &pcfg_pull_none_smt>, +- <2 RK_PC0 2 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c3 { +- i2c3_xfer: i2c3-xfer { +- rockchip,pins = +- <1 RK_PB4 4 &pcfg_pull_none_smt>, +- <1 RK_PB5 4 &pcfg_pull_none_smt>; +- }; +- }; +- +- tsadc { +- tsadc_otp_pin: tsadc-otp-pin { +- rockchip,pins = +- <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- tsadc_otp_out: tsadc-otp-out { +- rockchip,pins = +- <0 RK_PA6 1 &pcfg_pull_none>; +- }; +- }; +- +- uart0 { +- uart0_xfer: uart0-xfer { +- rockchip,pins = +- <0 RK_PB2 1 &pcfg_pull_up>, +- <0 RK_PB3 1 &pcfg_pull_up>; +- }; +- +- uart0_cts: uart0-cts { +- rockchip,pins = +- <0 RK_PB4 1 &pcfg_pull_none>; +- }; +- +- uart0_rts: uart0-rts { +- rockchip,pins = +- <0 RK_PB5 1 &pcfg_pull_none>; +- }; +- }; +- +- uart1 { +- uart1_xfer: uart1-xfer { +- rockchip,pins = +- <1 RK_PC1 1 &pcfg_pull_up>, +- <1 RK_PC0 1 &pcfg_pull_up>; +- }; +- +- uart1_cts: uart1-cts { +- rockchip,pins = +- <1 RK_PC2 1 &pcfg_pull_none>; +- }; +- +- uart1_rts: uart1-rts { +- rockchip,pins = +- <1 RK_PC3 1 &pcfg_pull_none>; +- }; +- }; +- +- uart2-m0 { +- uart2m0_xfer: uart2m0-xfer { +- rockchip,pins = +- <1 RK_PD2 2 &pcfg_pull_up>, +- <1 RK_PD3 2 &pcfg_pull_up>; +- }; +- }; +- +- uart2-m1 { +- uart2m1_xfer: uart2m1-xfer { +- rockchip,pins = +- <2 RK_PB4 2 &pcfg_pull_up>, +- <2 RK_PB6 2 &pcfg_pull_up>; +- }; +- }; +- +- uart3-m0 { +- uart3m0_xfer: uart3m0-xfer { +- rockchip,pins = +- <0 RK_PC0 2 &pcfg_pull_up>, +- <0 RK_PC1 2 &pcfg_pull_up>; +- }; +- +- uart3m0_cts: uart3m0-cts { +- rockchip,pins = +- <0 RK_PC2 2 &pcfg_pull_none>; +- }; +- +- uart3m0_rts: uart3m0-rts { +- rockchip,pins = +- <0 RK_PC3 2 &pcfg_pull_none>; +- }; +- }; +- +- uart3-m1 { +- uart3m1_xfer: uart3m1-xfer { +- rockchip,pins = +- <1 RK_PB6 2 &pcfg_pull_up>, +- <1 RK_PB7 2 &pcfg_pull_up>; +- }; +- +- uart3m1_cts: uart3m1-cts { +- rockchip,pins = +- <1 RK_PB4 2 &pcfg_pull_none>; +- }; +- +- uart3m1_rts: uart3m1-rts { +- rockchip,pins = +- <1 RK_PB5 2 &pcfg_pull_none>; +- }; +- }; +- +- uart4 { +- uart4_xfer: uart4-xfer { +- rockchip,pins = +- <1 RK_PD4 2 &pcfg_pull_up>, +- <1 RK_PD5 2 &pcfg_pull_up>; +- }; +- +- uart4_cts: uart4-cts { +- rockchip,pins = +- <1 RK_PD6 2 &pcfg_pull_none>; +- }; +- +- uart4_rts: uart4-rts { +- rockchip,pins = +- <1 RK_PD7 2 &pcfg_pull_none>; +- }; +- }; +- +- uart5 { +- uart5_xfer: uart5-xfer { +- rockchip,pins = +- <3 RK_PA2 4 &pcfg_pull_up>, +- <3 RK_PA1 4 &pcfg_pull_up>; +- }; +- +- uart5_cts: uart5-cts { +- rockchip,pins = +- <3 RK_PA3 4 &pcfg_pull_none>; +- }; +- +- uart5_rts: uart5-rts { +- rockchip,pins = +- <3 RK_PA5 4 &pcfg_pull_none>; +- }; +- }; +- +- spi0 { +- spi0_clk: spi0-clk { +- rockchip,pins = +- <1 RK_PB7 3 &pcfg_pull_up_4ma>; +- }; +- +- spi0_csn: spi0-csn { +- rockchip,pins = +- <1 RK_PB6 3 &pcfg_pull_up_4ma>; +- }; +- +- spi0_miso: spi0-miso { +- rockchip,pins = +- <1 RK_PB5 3 &pcfg_pull_up_4ma>; +- }; +- +- spi0_mosi: spi0-mosi { +- rockchip,pins = +- <1 RK_PB4 3 &pcfg_pull_up_4ma>; +- }; +- +- spi0_clk_hs: spi0-clk-hs { +- rockchip,pins = +- <1 RK_PB7 3 &pcfg_pull_up_8ma>; +- }; +- +- spi0_miso_hs: spi0-miso-hs { +- rockchip,pins = +- <1 RK_PB5 3 &pcfg_pull_up_8ma>; +- }; +- +- spi0_mosi_hs: spi0-mosi-hs { +- rockchip,pins = +- <1 RK_PB4 3 &pcfg_pull_up_8ma>; +- }; +- }; +- +- spi1 { +- spi1_clk: spi1-clk { +- rockchip,pins = +- <3 RK_PB7 4 &pcfg_pull_up_4ma>; +- }; +- +- spi1_csn0: spi1-csn0 { +- rockchip,pins = +- <3 RK_PB1 4 &pcfg_pull_up_4ma>; +- }; +- +- spi1_csn1: spi1-csn1 { +- rockchip,pins = +- <3 RK_PB2 2 &pcfg_pull_up_4ma>; +- }; +- +- spi1_miso: spi1-miso { +- rockchip,pins = +- <3 RK_PB6 4 &pcfg_pull_up_4ma>; +- }; +- +- spi1_mosi: spi1-mosi { +- rockchip,pins = +- <3 RK_PB4 4 &pcfg_pull_up_4ma>; +- }; +- +- spi1_clk_hs: spi1-clk-hs { +- rockchip,pins = +- <3 RK_PB7 4 &pcfg_pull_up_8ma>; +- }; +- +- spi1_miso_hs: spi1-miso-hs { +- rockchip,pins = +- <3 RK_PB6 4 &pcfg_pull_up_8ma>; +- }; +- +- spi1_mosi_hs: spi1-mosi-hs { +- rockchip,pins = +- <3 RK_PB4 4 &pcfg_pull_up_8ma>; +- }; +- }; +- +- pdm { +- pdm_clk0m0: pdm-clk0m0 { +- rockchip,pins = +- <3 RK_PC6 2 &pcfg_pull_none>; +- }; +- +- pdm_clk0m1: pdm-clk0m1 { +- rockchip,pins = +- <2 RK_PC6 1 &pcfg_pull_none>; +- }; +- +- pdm_clk1: pdm-clk1 { +- rockchip,pins = +- <3 RK_PC7 2 &pcfg_pull_none>; +- }; +- +- pdm_sdi0m0: pdm-sdi0m0 { +- rockchip,pins = +- <3 RK_PD3 2 &pcfg_pull_none>; +- }; +- +- pdm_sdi0m1: pdm-sdi0m1 { +- rockchip,pins = +- <2 RK_PC5 2 &pcfg_pull_none>; +- }; +- +- pdm_sdi1: pdm-sdi1 { +- rockchip,pins = +- <3 RK_PD0 2 &pcfg_pull_none>; +- }; +- +- pdm_sdi2: pdm-sdi2 { +- rockchip,pins = +- <3 RK_PD1 2 &pcfg_pull_none>; +- }; +- +- pdm_sdi3: pdm-sdi3 { +- rockchip,pins = +- <3 RK_PD2 2 &pcfg_pull_none>; +- }; +- +- pdm_clk0m0_sleep: pdm-clk0m0-sleep { +- rockchip,pins = +- <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; +- }; +- +- pdm_clk0m_sleep1: pdm-clk0m1-sleep { +- rockchip,pins = +- <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; +- }; +- +- pdm_clk1_sleep: pdm-clk1-sleep { +- rockchip,pins = +- <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; +- }; +- +- pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { +- rockchip,pins = +- <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; +- }; +- +- pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { +- rockchip,pins = +- <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; +- }; +- +- pdm_sdi1_sleep: pdm-sdi1-sleep { +- rockchip,pins = +- <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; +- }; +- +- pdm_sdi2_sleep: pdm-sdi2-sleep { +- rockchip,pins = +- <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; +- }; +- +- pdm_sdi3_sleep: pdm-sdi3-sleep { +- rockchip,pins = +- <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; +- }; +- }; +- +- i2s0 { +- i2s0_8ch_mclk: i2s0-8ch-mclk { +- rockchip,pins = +- <3 RK_PC1 2 &pcfg_pull_none>; +- }; +- +- i2s0_8ch_sclktx: i2s0-8ch-sclktx { +- rockchip,pins = +- <3 RK_PC3 2 &pcfg_pull_none>; +- }; +- +- i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { +- rockchip,pins = +- <3 RK_PB4 2 &pcfg_pull_none>; +- }; +- +- i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { +- rockchip,pins = +- <3 RK_PC2 2 &pcfg_pull_none>; +- }; +- +- i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { +- rockchip,pins = +- <3 RK_PB5 2 &pcfg_pull_none>; +- }; +- +- i2s0_8ch_sdo0: i2s0-8ch-sdo0 { +- rockchip,pins = +- <3 RK_PC4 2 &pcfg_pull_none>; +- }; +- +- i2s0_8ch_sdo1: i2s0-8ch-sdo1 { +- rockchip,pins = +- <3 RK_PC0 2 &pcfg_pull_none>; +- }; +- +- i2s0_8ch_sdo2: i2s0-8ch-sdo2 { +- rockchip,pins = +- <3 RK_PB7 2 &pcfg_pull_none>; +- }; +- +- i2s0_8ch_sdo3: i2s0-8ch-sdo3 { +- rockchip,pins = +- <3 RK_PB6 2 &pcfg_pull_none>; +- }; +- +- i2s0_8ch_sdi0: i2s0-8ch-sdi0 { +- rockchip,pins = +- <3 RK_PC5 2 &pcfg_pull_none>; +- }; +- +- i2s0_8ch_sdi1: i2s0-8ch-sdi1 { +- rockchip,pins = +- <3 RK_PB3 2 &pcfg_pull_none>; +- }; +- +- i2s0_8ch_sdi2: i2s0-8ch-sdi2 { +- rockchip,pins = +- <3 RK_PB1 2 &pcfg_pull_none>; +- }; +- +- i2s0_8ch_sdi3: i2s0-8ch-sdi3 { +- rockchip,pins = +- <3 RK_PB0 2 &pcfg_pull_none>; +- }; +- }; +- +- i2s1 { +- i2s1_2ch_mclk: i2s1-2ch-mclk { +- rockchip,pins = +- <2 RK_PC3 1 &pcfg_pull_none>; +- }; +- +- i2s1_2ch_sclk: i2s1-2ch-sclk { +- rockchip,pins = +- <2 RK_PC2 1 &pcfg_pull_none>; +- }; +- +- i2s1_2ch_lrck: i2s1-2ch-lrck { +- rockchip,pins = +- <2 RK_PC1 1 &pcfg_pull_none>; +- }; +- +- i2s1_2ch_sdi: i2s1-2ch-sdi { +- rockchip,pins = +- <2 RK_PC5 1 &pcfg_pull_none>; +- }; +- +- i2s1_2ch_sdo: i2s1-2ch-sdo { +- rockchip,pins = +- <2 RK_PC4 1 &pcfg_pull_none>; +- }; +- }; +- +- i2s2 { +- i2s2_2ch_mclk: i2s2-2ch-mclk { +- rockchip,pins = +- <3 RK_PA1 2 &pcfg_pull_none>; +- }; +- +- i2s2_2ch_sclk: i2s2-2ch-sclk { +- rockchip,pins = +- <3 RK_PA2 2 &pcfg_pull_none>; +- }; +- +- i2s2_2ch_lrck: i2s2-2ch-lrck { +- rockchip,pins = +- <3 RK_PA3 2 &pcfg_pull_none>; +- }; +- +- i2s2_2ch_sdi: i2s2-2ch-sdi { +- rockchip,pins = +- <3 RK_PA5 2 &pcfg_pull_none>; +- }; +- +- i2s2_2ch_sdo: i2s2-2ch-sdo { +- rockchip,pins = +- <3 RK_PA7 2 &pcfg_pull_none>; +- }; +- }; +- +- sdmmc { +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = +- <1 RK_PD6 1 &pcfg_pull_none_8ma>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = +- <1 RK_PD7 1 &pcfg_pull_up_8ma>; +- }; +- +- sdmmc_det: sdmmc-det { +- rockchip,pins = +- <0 RK_PA3 1 &pcfg_pull_up_8ma>; +- }; +- +- sdmmc_bus1: sdmmc-bus1 { +- rockchip,pins = +- <1 RK_PD2 1 &pcfg_pull_up_8ma>; +- }; +- +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = +- <1 RK_PD2 1 &pcfg_pull_up_8ma>, +- <1 RK_PD3 1 &pcfg_pull_up_8ma>, +- <1 RK_PD4 1 &pcfg_pull_up_8ma>, +- <1 RK_PD5 1 &pcfg_pull_up_8ma>; +- }; +- }; +- +- sdio { +- sdio_clk: sdio-clk { +- rockchip,pins = +- <1 RK_PC5 1 &pcfg_pull_none>; +- }; +- +- sdio_cmd: sdio-cmd { +- rockchip,pins = +- <1 RK_PC4 1 &pcfg_pull_up>; +- }; +- +- sdio_bus4: sdio-bus4 { +- rockchip,pins = +- <1 RK_PC6 1 &pcfg_pull_up>, +- <1 RK_PC7 1 &pcfg_pull_up>, +- <1 RK_PD0 1 &pcfg_pull_up>, +- <1 RK_PD1 1 &pcfg_pull_up>; +- }; +- }; +- +- emmc { +- emmc_clk: emmc-clk { +- rockchip,pins = +- <1 RK_PB1 2 &pcfg_pull_none_8ma>; +- }; +- +- emmc_cmd: emmc-cmd { +- rockchip,pins = +- <1 RK_PB2 2 &pcfg_pull_up_8ma>; +- }; +- +- emmc_rstnout: emmc-rstnout { +- rockchip,pins = +- <1 RK_PB3 2 &pcfg_pull_none>; +- }; +- +- emmc_bus1: emmc-bus1 { +- rockchip,pins = +- <1 RK_PA0 2 &pcfg_pull_up_8ma>; +- }; +- +- emmc_bus4: emmc-bus4 { +- rockchip,pins = +- <1 RK_PA0 2 &pcfg_pull_up_8ma>, +- <1 RK_PA1 2 &pcfg_pull_up_8ma>, +- <1 RK_PA2 2 &pcfg_pull_up_8ma>, +- <1 RK_PA3 2 &pcfg_pull_up_8ma>; +- }; +- +- emmc_bus8: emmc-bus8 { +- rockchip,pins = +- <1 RK_PA0 2 &pcfg_pull_up_8ma>, +- <1 RK_PA1 2 &pcfg_pull_up_8ma>, +- <1 RK_PA2 2 &pcfg_pull_up_8ma>, +- <1 RK_PA3 2 &pcfg_pull_up_8ma>, +- <1 RK_PA4 2 &pcfg_pull_up_8ma>, +- <1 RK_PA5 2 &pcfg_pull_up_8ma>, +- <1 RK_PA6 2 &pcfg_pull_up_8ma>, +- <1 RK_PA7 2 &pcfg_pull_up_8ma>; +- }; +- }; +- +- flash { +- flash_cs0: flash-cs0 { +- rockchip,pins = +- <1 RK_PB0 1 &pcfg_pull_none>; +- }; +- +- flash_rdy: flash-rdy { +- rockchip,pins = +- <1 RK_PB1 1 &pcfg_pull_none>; +- }; +- +- flash_dqs: flash-dqs { +- rockchip,pins = +- <1 RK_PB2 1 &pcfg_pull_none>; +- }; +- +- flash_ale: flash-ale { +- rockchip,pins = +- <1 RK_PB3 1 &pcfg_pull_none>; +- }; +- +- flash_cle: flash-cle { +- rockchip,pins = +- <1 RK_PB4 1 &pcfg_pull_none>; +- }; +- +- flash_wrn: flash-wrn { +- rockchip,pins = +- <1 RK_PB5 1 &pcfg_pull_none>; +- }; +- +- flash_csl: flash-csl { +- rockchip,pins = +- <1 RK_PB6 1 &pcfg_pull_none>; +- }; +- +- flash_rdn: flash-rdn { +- rockchip,pins = +- <1 RK_PB7 1 &pcfg_pull_none>; +- }; +- +- flash_bus8: flash-bus8 { +- rockchip,pins = +- <1 RK_PA0 1 &pcfg_pull_up_12ma>, +- <1 RK_PA1 1 &pcfg_pull_up_12ma>, +- <1 RK_PA2 1 &pcfg_pull_up_12ma>, +- <1 RK_PA3 1 &pcfg_pull_up_12ma>, +- <1 RK_PA4 1 &pcfg_pull_up_12ma>, +- <1 RK_PA5 1 &pcfg_pull_up_12ma>, +- <1 RK_PA6 1 &pcfg_pull_up_12ma>, +- <1 RK_PA7 1 &pcfg_pull_up_12ma>; +- }; +- }; +- +- lcdc { +- lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { +- rockchip,pins = +- <3 RK_PA0 1 &pcfg_pull_none_12ma>; +- }; +- +- lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { +- rockchip,pins = +- <3 RK_PA1 1 &pcfg_pull_none_12ma>; +- }; +- +- lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { +- rockchip,pins = +- <3 RK_PA2 1 &pcfg_pull_none_12ma>; +- }; +- +- lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { +- rockchip,pins = +- <3 RK_PA3 1 &pcfg_pull_none_12ma>; +- }; +- +- lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { +- rockchip,pins = +- <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ +- <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ +- <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ +- <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ +- <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ +- <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ +- <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ +- <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ +- <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ +- <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ +- <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ +- <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ +- <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ +- <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ +- <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ +- <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ +- <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ +- <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ +- <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ +- <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ +- <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ +- <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ +- <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ +- <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ +- }; +- +- lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { +- rockchip,pins = +- <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ +- <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ +- <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ +- <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ +- <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ +- <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ +- <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ +- <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ +- <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ +- <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ +- <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ +- <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ +- <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ +- <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ +- <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ +- <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ +- <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ +- <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ +- }; +- +- lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { +- rockchip,pins = +- <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ +- <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ +- <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ +- <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ +- <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ +- <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ +- <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ +- <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ +- <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ +- <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ +- <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ +- <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ +- <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ +- <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ +- <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ +- <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ +- }; +- +- lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { +- rockchip,pins = +- <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ +- <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ +- <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ +- <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ +- <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ +- <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ +- <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ +- <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ +- <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ +- <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ +- <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ +- <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ +- <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ +- <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ +- <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ +- <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ +- <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ +- }; +- +- lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { +- rockchip,pins = +- <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ +- <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ +- <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ +- <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ +- <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ +- <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ +- <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ +- <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ +- <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ +- <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ +- <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ +- }; +- +- lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { +- rockchip,pins = +- <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ +- <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ +- <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ +- <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ +- <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ +- <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ +- <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ +- <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ +- <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ +- }; +- }; +- +- pwm0 { +- pwm0_pin: pwm0-pin { +- rockchip,pins = +- <0 RK_PB7 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm1 { +- pwm1_pin: pwm1-pin { +- rockchip,pins = +- <0 RK_PC0 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm2 { +- pwm2_pin: pwm2-pin { +- rockchip,pins = +- <2 RK_PB5 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm3 { +- pwm3_pin: pwm3-pin { +- rockchip,pins = +- <0 RK_PC1 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm4 { +- pwm4_pin: pwm4-pin { +- rockchip,pins = +- <3 RK_PC2 3 &pcfg_pull_none>; +- }; +- }; +- +- pwm5 { +- pwm5_pin: pwm5-pin { +- rockchip,pins = +- <3 RK_PC3 3 &pcfg_pull_none>; +- }; +- }; +- +- pwm6 { +- pwm6_pin: pwm6-pin { +- rockchip,pins = +- <3 RK_PC4 3 &pcfg_pull_none>; +- }; +- }; +- +- pwm7 { +- pwm7_pin: pwm7-pin { +- rockchip,pins = +- <3 RK_PC5 3 &pcfg_pull_none>; +- }; +- }; +- +- gmac { +- rmii_pins: rmii-pins { +- rockchip,pins = +- <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ +- <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ +- <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ +- <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ +- <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ +- <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ +- <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ +- <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ +- <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ +- }; +- +- mac_refclk_12ma: mac-refclk-12ma { +- rockchip,pins = +- <2 RK_PB2 2 &pcfg_pull_none_12ma>; +- }; +- +- mac_refclk: mac-refclk { +- rockchip,pins = +- <2 RK_PB2 2 &pcfg_pull_none>; +- }; +- }; +- +- cif-m0 { +- cif_clkout_m0: cif-clkout-m0 { +- rockchip,pins = +- <2 RK_PB3 1 &pcfg_pull_none>; +- }; +- +- dvp_d2d9_m0: dvp-d2d9-m0 { +- rockchip,pins = +- <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ +- <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ +- <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ +- <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ +- <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ +- <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ +- <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ +- <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ +- <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ +- <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ +- <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ +- <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ +- }; +- +- dvp_d0d1_m0: dvp-d0d1-m0 { +- rockchip,pins = +- <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ +- <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ +- }; +- +- dvp_d10d11_m0:d10-d11-m0 { +- rockchip,pins = +- <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ +- <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ +- }; +- }; +- +- cif-m1 { +- cif_clkout_m1: cif-clkout-m1 { +- rockchip,pins = +- <3 RK_PD0 3 &pcfg_pull_none>; +- }; +- +- dvp_d2d9_m1: dvp-d2d9-m1 { +- rockchip,pins = +- <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ +- <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ +- <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ +- <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ +- <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ +- <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ +- <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ +- <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ +- <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ +- <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ +- <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ +- <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ +- }; +- +- dvp_d0d1_m1: dvp-d0d1-m1 { +- rockchip,pins = +- <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ +- <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ +- }; +- +- dvp_d10d11_m1:d10-d11-m1 { +- rockchip,pins = +- <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ +- <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ +- }; +- }; +- +- isp { +- isp_prelight: isp-prelight { +- rockchip,pins = +- <3 RK_PD1 4 &pcfg_pull_none>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3308-evb.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3308-evb.dts +deleted file mode 100644 +index 9b4f855ea5d4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3308-evb.dts ++++ /dev/null +@@ -1,230 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd +- * +- */ +- +-/dts-v1/; +-#include +-#include "rk3308.dtsi" +- +-/ { +- model = "Rockchip RK3308 EVB"; +- compatible = "rockchip,rk3308-evb", "rockchip,rk3308"; +- +- chosen { +- stdout-path = "serial4:1500000n8"; +- }; +- +- adc-keys0 { +- compatible = "adc-keys"; +- io-channels = <&saradc 0>; +- io-channel-names = "buttons"; +- poll-interval = <100>; +- keyup-threshold-microvolt = <1800000>; +- +- func-key { +- linux,code = ; +- label = "function"; +- press-threshold-microvolt = <18000>; +- }; +- }; +- +- adc-keys1 { +- compatible = "adc-keys"; +- io-channels = <&saradc 1>; +- io-channel-names = "buttons"; +- poll-interval = <100>; +- keyup-threshold-microvolt = <1800000>; +- +- esc-key { +- linux,code = ; +- label = "micmute"; +- press-threshold-microvolt = <1130000>; +- }; +- +- home-key { +- linux,code = ; +- label = "mode"; +- press-threshold-microvolt = <901000>; +- }; +- +- menu-key { +- linux,code = ; +- label = "play"; +- press-threshold-microvolt = <624000>; +- }; +- +- vol-down-key { +- linux,code = ; +- label = "volume down"; +- press-threshold-microvolt = <300000>; +- }; +- +- vol-up-key { +- linux,code = ; +- label = "volume up"; +- press-threshold-microvolt = <18000>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_key>; +- +- power { +- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; +- linux,code = ; +- label = "GPIO Key Power"; +- debounce-interval = <100>; +- wakeup-source; +- }; +- }; +- +- vcc12v_dcin: vcc12v-dcin { +- compatible = "regulator-fixed"; +- regulator-name = "vcc12v_dcin"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc5v0_sys: vcc5v0-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc12v_dcin>; +- }; +- +- vccio_sdio: vcc_1v8: vcc-1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_ddr: vcc-ddr { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_ddr"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc_io: vcc-io { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vccio_flash: vccio-flash { +- compatible = "regulator-fixed"; +- regulator-name = "vccio_flash"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_io>; +- }; +- +- vcc5v0_host: vcc5v0-host { +- compatible = "regulator-fixed"; +- gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_drv>; +- regulator-name = "vbus_host"; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vdd_core: vdd-core { +- compatible = "pwm-regulator"; +- pwms = <&pwm0 0 5000 1>; +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <827000>; +- regulator-max-microvolt = <1340000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-settling-time-up-us = <250>; +- pwm-supply = <&vcc5v0_sys>; +- }; +- +- vdd_log: vdd-log { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_log"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vdd_1v0: vdd-1v0 { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_1v0"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_core>; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&vcc_1v8>; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&rtc_32k>; +- +- buttons { +- pwr_key: pwr-key { +- rockchip,pins = <0 RK_PA6 0 &pcfg_pull_up>; +- }; +- }; +- +- usb { +- usb_drv: usb-drv { +- rockchip,pins = <0 RK_PC5 0 &pcfg_pull_none>; +- }; +- }; +- +- sdio-pwrseq { +- wifi_enable_h: wifi-enable-h { +- rockchip,pins = <0 RK_PA2 0 &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm0 { +- status = "okay"; +- pinctrl-0 = <&pwm0_pin_pull_down>; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_xfer>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3308-roc-cc.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3308-roc-cc.dts +deleted file mode 100644 +index ea6820902ede..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3308-roc-cc.dts ++++ /dev/null +@@ -1,191 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd +- */ +- +-/dts-v1/; +-#include "rk3308.dtsi" +- +-/ { +- model = "Firefly ROC-RK3308-CC board"; +- compatible = "firefly,roc-rk3308-cc", "rockchip,rk3308"; +- +- aliases { +- mmc0 = &sdmmc; +- mmc1 = &emmc; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- ir_rx { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ir_recv_pin>; +- }; +- +- ir_tx { +- compatible = "pwm-ir-tx"; +- pwms = <&pwm5 0 25000 0>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- power_led: led-0 { +- label = "firefly:red:power"; +- linux,default-trigger = "ir-power-click"; +- default-state = "on"; +- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; +- }; +- +- user_led: led-1 { +- label = "firefly:blue:user"; +- linux,default-trigger = "ir-user-click"; +- default-state = "off"; +- gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- typec_vcc5v: typec-vcc5v { +- compatible = "regulator-fixed"; +- regulator-name = "typec_vcc5v"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc5v0_sys: vcc5v0-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&typec_vcc5v>; +- }; +- +- vcc_io: vcc-io { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc_sdmmc: vcc-sdmmc { +- compatible = "regulator-gpio"; +- regulator-name = "vcc_sdmmc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>; +- states = <1800000 0x0>, +- <3300000 0x1>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc_sd: vcc-sd { +- compatible = "regulator-fixed"; +- gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>; +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_io>; +- }; +- +- vdd_core: vdd-core { +- compatible = "pwm-regulator"; +- pwms = <&pwm0 0 5000 1>; +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <827000>; +- regulator-max-microvolt = <1340000>; +- regulator-init-microvolt = <1015000>; +- regulator-settling-time-up-us = <250>; +- regulator-always-on; +- regulator-boot-on; +- pwm-supply = <&vcc5v0_sys>; +- }; +- +- vdd_log: vdd-log { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_log"; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_core>; +-}; +- +-&emmc { +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +- non-removable; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- status = "okay"; +- +- rtc: rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- }; +-}; +- +-&pwm5 { +- status = "okay"; +- pinctrl-names = "active"; +- pinctrl-0 = <&pwm5_pin_pull_down>; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&rtc_32k>; +- +- ir-receiver { +- ir_recv_pin: ir-recv-pin { +- rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- buttons { +- pwr_key: pwr-key { +- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +- +-&pwm0 { +- status = "okay"; +- pinctrl-0 = <&pwm0_pin_pull_down>; +-}; +- +-&sdmmc { +- cap-mmc-highspeed; +- cap-sd-highspeed; +- card-detect-delay = <300>; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- vmmc-supply = <&vcc_sd>; +- vqmmc-supply = <&vcc_sdmmc>; +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3308.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3308.dtsi +deleted file mode 100644 +index a185901aba9a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3308.dtsi ++++ /dev/null +@@ -1,1843 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd +- * +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "rockchip,rk3308"; +- +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- spi0 = &spi0; +- spi1 = &spi1; +- spi2 = &spi2; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- clocks = <&cru ARMCLK>; +- #cooling-cells = <2>; +- dynamic-power-coefficient = <90>; +- operating-points-v2 = <&cpu0_opp_table>; +- cpu-idle-states = <&CPU_SLEEP>; +- next-level-cache = <&l2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- operating-points-v2 = <&cpu0_opp_table>; +- cpu-idle-states = <&CPU_SLEEP>; +- next-level-cache = <&l2>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- operating-points-v2 = <&cpu0_opp_table>; +- cpu-idle-states = <&CPU_SLEEP>; +- next-level-cache = <&l2>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a35"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- operating-points-v2 = <&cpu0_opp_table>; +- cpu-idle-states = <&CPU_SLEEP>; +- next-level-cache = <&l2>; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP: cpu-sleep { +- compatible = "arm,idle-state"; +- local-timer-stop; +- arm,psci-suspend-param = <0x0010000>; +- entry-latency-us = <120>; +- exit-latency-us = <250>; +- min-residency-us = <900>; +- }; +- }; +- +- l2: l2-cache { +- compatible = "cache"; +- }; +- }; +- +- cpu0_opp_table: cpu0-opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-408000000 { +- opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <950000 950000 1340000>; +- clock-latency-ns = <40000>; +- opp-suspend; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <950000 950000 1340000>; +- clock-latency-ns = <40000>; +- }; +- opp-816000000 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <1025000 1025000 1340000>; +- clock-latency-ns = <40000>; +- }; +- opp-1008000000 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <1125000 1125000 1340000>; +- clock-latency-ns = <40000>; +- }; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a35-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- mac_clkin: external-mac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- clock-output-names = "mac_clkin"; +- #clock-cells = <0>; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- xin24m: xin24m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "xin24m"; +- }; +- +- grf: grf@ff000000 { +- compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; +- reg = <0x0 0xff000000 0x0 0x08000>; +- +- reboot-mode { +- compatible = "syscon-reboot-mode"; +- offset = <0x500>; +- mode-bootloader = ; +- mode-loader = ; +- mode-normal = ; +- mode-recovery = ; +- mode-fastboot = ; +- }; +- }; +- +- usb2phy_grf: syscon@ff008000 { +- compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd"; +- reg = <0x0 0xff008000 0x0 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- u2phy: usb2phy@100 { +- compatible = "rockchip,rk3308-usb2phy"; +- reg = <0x100 0x10>; +- assigned-clocks = <&cru USB480M>; +- assigned-clock-parents = <&u2phy>; +- clocks = <&cru SCLK_USBPHY_REF>; +- clock-names = "phyclk"; +- clock-output-names = "usb480m_phy"; +- #clock-cells = <0>; +- status = "disabled"; +- +- u2phy_otg: otg-port { +- interrupts = , +- , +- ; +- interrupt-names = "otg-bvalid", "otg-id", +- "linestate"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- u2phy_host: host-port { +- interrupts = ; +- interrupt-names = "linestate"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- }; +- +- detect_grf: syscon@ff00b000 { +- compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd"; +- reg = <0x0 0xff00b000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- core_grf: syscon@ff00c000 { +- compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd"; +- reg = <0x0 0xff00c000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- i2c0: i2c@ff040000 { +- compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xff040000 0x0 0x1000>; +- clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_xfer>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@ff050000 { +- compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xff050000 0x0 0x1000>; +- clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_xfer>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@ff060000 { +- compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xff060000 0x0 0x1000>; +- clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_xfer>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@ff070000 { +- compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xff070000 0x0 0x1000>; +- clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3m0_xfer>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- wdt: watchdog@ff080000 { +- compatible = "rockchip,rk3308-wdt", "snps,dw-wdt"; +- reg = <0x0 0xff080000 0x0 0x100>; +- clocks = <&cru PCLK_WDT>; +- interrupts = ; +- status = "disabled"; +- }; +- +- uart0: serial@ff0a0000 { +- compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff0a0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; +- clock-names = "baudclk", "apb_pclk"; +- reg-shift = <2>; +- reg-io-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +- status = "disabled"; +- }; +- +- uart1: serial@ff0b0000 { +- compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff0b0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; +- clock-names = "baudclk", "apb_pclk"; +- reg-shift = <2>; +- reg-io-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; +- status = "disabled"; +- }; +- +- uart2: serial@ff0c0000 { +- compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff0c0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; +- clock-names = "baudclk", "apb_pclk"; +- reg-shift = <2>; +- reg-io-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2m0_xfer>; +- status = "disabled"; +- }; +- +- uart3: serial@ff0d0000 { +- compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff0d0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; +- clock-names = "baudclk", "apb_pclk"; +- reg-shift = <2>; +- reg-io-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_xfer>; +- status = "disabled"; +- }; +- +- uart4: serial@ff0e0000 { +- compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff0e0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; +- clock-names = "baudclk", "apb_pclk"; +- reg-shift = <2>; +- reg-io-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; +- status = "disabled"; +- }; +- +- spi0: spi@ff120000 { +- compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xff120000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; +- clock-names = "spiclk", "apb_pclk"; +- dmas = <&dmac0 0>, <&dmac0 1>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>; +- status = "disabled"; +- }; +- +- spi1: spi@ff130000 { +- compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xff130000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; +- clock-names = "spiclk", "apb_pclk"; +- dmas = <&dmac0 2>, <&dmac0 3>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>; +- status = "disabled"; +- }; +- +- spi2: spi@ff140000 { +- compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xff140000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; +- clock-names = "spiclk", "apb_pclk"; +- dmas = <&dmac1 16>, <&dmac1 17>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>; +- status = "disabled"; +- }; +- +- pwm8: pwm@ff160000 { +- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff160000 0x0 0x10>; +- clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm8_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm9: pwm@ff160010 { +- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff160010 0x0 0x10>; +- clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm9_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm10: pwm@ff160020 { +- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff160020 0x0 0x10>; +- clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm10_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm11: pwm@ff160030 { +- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff160030 0x0 0x10>; +- clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm11_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm4: pwm@ff170000 { +- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff170000 0x0 0x10>; +- clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm4_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm5: pwm@ff170010 { +- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff170010 0x0 0x10>; +- clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm5_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm6: pwm@ff170020 { +- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff170020 0x0 0x10>; +- clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm6_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm7: pwm@ff170030 { +- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff170030 0x0 0x10>; +- clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm7_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm0: pwm@ff180000 { +- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff180000 0x0 0x10>; +- clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm1: pwm@ff180010 { +- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff180010 0x0 0x10>; +- clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm1_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm2: pwm@ff180020 { +- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff180020 0x0 0x10>; +- clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm2_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm3: pwm@ff180030 { +- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xff180030 0x0 0x10>; +- clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm3_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- rktimer: rktimer@ff1a0000 { +- compatible = "rockchip,rk3288-timer"; +- reg = <0x0 0xff1a0000 0x0 0x20>; +- interrupts = ; +- clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; +- clock-names = "pclk", "timer"; +- }; +- +- saradc: saradc@ff1e0000 { +- compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; +- reg = <0x0 0xff1e0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; +- clock-names = "saradc", "apb_pclk"; +- #io-channel-cells = <1>; +- resets = <&cru SRST_SARADC_P>; +- reset-names = "saradc-apb"; +- status = "disabled"; +- }; +- +- dmac0: dma-controller@ff2c0000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xff2c0000 0x0 0x4000>; +- interrupts = , +- ; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMAC0>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- }; +- +- dmac1: dma-controller@ff2d0000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xff2d0000 0x0 0x4000>; +- interrupts = , +- ; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMAC1>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- }; +- +- i2s_2ch_0: i2s@ff350000 { +- compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; +- reg = <0x0 0xff350000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>; +- clock-names = "i2s_clk", "i2s_hclk"; +- dmas = <&dmac1 8>, <&dmac1 9>; +- dma-names = "tx", "rx"; +- resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>; +- reset-names = "reset-m", "reset-h"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s_2ch_0_sclk +- &i2s_2ch_0_lrck +- &i2s_2ch_0_sdi +- &i2s_2ch_0_sdo>; +- status = "disabled"; +- }; +- +- i2s_2ch_1: i2s@ff360000 { +- compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; +- reg = <0x0 0xff360000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; +- clock-names = "i2s_clk", "i2s_hclk"; +- dmas = <&dmac1 11>; +- dma-names = "rx"; +- resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>; +- reset-names = "reset-m", "reset-h"; +- status = "disabled"; +- }; +- +- spdif_tx: spdif-tx@ff3a0000 { +- compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif"; +- reg = <0x0 0xff3a0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>; +- clock-names = "mclk", "hclk"; +- dmas = <&dmac1 13>; +- dma-names = "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spdif_out>; +- status = "disabled"; +- }; +- +- usb20_otg: usb@ff400000 { +- compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", +- "snps,dwc2"; +- reg = <0x0 0xff400000 0x0 0x40000>; +- interrupts = ; +- clocks = <&cru HCLK_OTG>; +- clock-names = "otg"; +- dr_mode = "otg"; +- g-np-tx-fifo-size = <16>; +- g-rx-fifo-size = <280>; +- g-tx-fifo-size = <256 128 128 64 32 16>; +- phys = <&u2phy_otg>; +- phy-names = "usb2-phy"; +- status = "disabled"; +- }; +- +- usb_host_ehci: usb@ff440000 { +- compatible = "generic-ehci"; +- reg = <0x0 0xff440000 0x0 0x10000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; +- phys = <&u2phy_host>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usb_host_ohci: usb@ff450000 { +- compatible = "generic-ohci"; +- reg = <0x0 0xff450000 0x0 0x10000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; +- phys = <&u2phy_host>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- sdmmc: mmc@ff480000 { +- compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xff480000 0x0 0x4000>; +- interrupts = ; +- bus-width = <4>; +- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, +- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- max-frequency = <150000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; +- status = "disabled"; +- }; +- +- emmc: mmc@ff490000 { +- compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xff490000 0x0 0x4000>; +- interrupts = ; +- bus-width = <8>; +- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, +- <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- max-frequency = <150000000>; +- status = "disabled"; +- }; +- +- sdio: mmc@ff4a0000 { +- compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xff4a0000 0x0 0x4000>; +- interrupts = ; +- bus-width = <4>; +- clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, +- <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- max-frequency = <150000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; +- status = "disabled"; +- }; +- +- nfc: nand-controller@ff4b0000 { +- compatible = "rockchip,rk3308-nfc", +- "rockchip,rv1108-nfc"; +- reg = <0x0 0xff4b0000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; +- clock-names = "ahb", "nfc"; +- assigned-clocks = <&cru SCLK_NANDC>; +- assigned-clock-rates = <150000000>; +- pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 +- &flash_rdn &flash_rdy &flash_wrn>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- gmac: ethernet@ff4e0000 { +- compatible = "rockchip,rk3308-gmac"; +- reg = <0x0 0xff4e0000 0x0 0x10000>; +- interrupts = ; +- interrupt-names = "macirq"; +- clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, +- <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>, +- <&cru SCLK_MAC>, <&cru ACLK_MAC>, +- <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>; +- clock-names = "stmmaceth", "mac_clk_rx", +- "mac_clk_tx", "clk_mac_ref", +- "clk_mac_refout", "aclk_mac", +- "pclk_mac", "clk_mac_speed"; +- phy-mode = "rmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; +- resets = <&cru SRST_MAC_A>; +- reset-names = "stmmaceth"; +- rockchip,grf = <&grf>; +- status = "disabled"; +- }; +- +- cru: clock-controller@ff500000 { +- compatible = "rockchip,rk3308-cru"; +- reg = <0x0 0xff500000 0x0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- rockchip,grf = <&grf>; +- +- assigned-clocks = <&cru SCLK_RTC32K>; +- assigned-clock-rates = <32768>; +- }; +- +- gic: interrupt-controller@ff580000 { +- compatible = "arm,gic-400"; +- reg = <0x0 0xff581000 0x0 0x1000>, +- <0x0 0xff582000 0x0 0x2000>, +- <0x0 0xff584000 0x0 0x2000>, +- <0x0 0xff586000 0x0 0x2000>; +- interrupts = ; +- #interrupt-cells = <3>; +- interrupt-controller; +- #address-cells = <0>; +- }; +- +- sram: sram@fff80000 { +- compatible = "mmio-sram"; +- reg = <0x0 0xfff80000 0x0 0x40000>; +- ranges = <0 0x0 0xfff80000 0x40000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* reserved for ddr dvfs and system suspend/resume */ +- ddr-sram@0 { +- reg = <0x0 0x8000>; +- }; +- +- /* reserved for vad audio buffer */ +- vad_sram: vad-sram@8000 { +- reg = <0x8000 0x38000>; +- }; +- }; +- +- pinctrl: pinctrl { +- compatible = "rockchip,rk3308-pinctrl"; +- rockchip,grf = <&grf>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gpio0: gpio0@ff220000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff220000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO0>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio1@ff230000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff230000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO1>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio2@ff240000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff240000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO2>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio3@ff250000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff250000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO3>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio4: gpio4@ff260000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff260000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO4>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pcfg_pull_up: pcfg-pull-up { +- bias-pull-up; +- }; +- +- pcfg_pull_down: pcfg-pull-down { +- bias-pull-down; +- }; +- +- pcfg_pull_none: pcfg-pull-none { +- bias-disable; +- }; +- +- pcfg_pull_none_2ma: pcfg-pull-none-2ma { +- bias-disable; +- drive-strength = <2>; +- }; +- +- pcfg_pull_up_2ma: pcfg-pull-up-2ma { +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- pcfg_pull_up_4ma: pcfg-pull-up-4ma { +- bias-pull-up; +- drive-strength = <4>; +- }; +- +- pcfg_pull_none_4ma: pcfg-pull-none-4ma { +- bias-disable; +- drive-strength = <4>; +- }; +- +- pcfg_pull_down_4ma: pcfg-pull-down-4ma { +- bias-pull-down; +- drive-strength = <4>; +- }; +- +- pcfg_pull_none_8ma: pcfg-pull-none-8ma { +- bias-disable; +- drive-strength = <8>; +- }; +- +- pcfg_pull_up_8ma: pcfg-pull-up-8ma { +- bias-pull-up; +- drive-strength = <8>; +- }; +- +- pcfg_pull_none_12ma: pcfg-pull-none-12ma { +- bias-disable; +- drive-strength = <12>; +- }; +- +- pcfg_pull_up_12ma: pcfg-pull-up-12ma { +- bias-pull-up; +- drive-strength = <12>; +- }; +- +- pcfg_pull_none_smt: pcfg-pull-none-smt { +- bias-disable; +- input-schmitt-enable; +- }; +- +- pcfg_output_high: pcfg-output-high { +- output-high; +- }; +- +- pcfg_output_low: pcfg-output-low { +- output-low; +- }; +- +- pcfg_input_high: pcfg-input-high { +- bias-pull-up; +- input-enable; +- }; +- +- pcfg_input: pcfg-input { +- input-enable; +- }; +- +- emmc { +- emmc_clk: emmc-clk { +- rockchip,pins = +- <3 RK_PB1 2 &pcfg_pull_none_8ma>; +- }; +- +- emmc_cmd: emmc-cmd { +- rockchip,pins = +- <3 RK_PB0 2 &pcfg_pull_up_8ma>; +- }; +- +- emmc_pwren: emmc-pwren { +- rockchip,pins = +- <3 RK_PB3 2 &pcfg_pull_none>; +- }; +- +- emmc_rstn: emmc-rstn { +- rockchip,pins = +- <3 RK_PB2 2 &pcfg_pull_none>; +- }; +- +- emmc_bus1: emmc-bus1 { +- rockchip,pins = +- <3 RK_PA0 2 &pcfg_pull_up_8ma>; +- }; +- +- emmc_bus4: emmc-bus4 { +- rockchip,pins = +- <3 RK_PA0 2 &pcfg_pull_up_8ma>, +- <3 RK_PA1 2 &pcfg_pull_up_8ma>, +- <3 RK_PA2 2 &pcfg_pull_up_8ma>, +- <3 RK_PA3 2 &pcfg_pull_up_8ma>; +- }; +- +- emmc_bus8: emmc-bus8 { +- rockchip,pins = +- <3 RK_PA0 2 &pcfg_pull_up_8ma>, +- <3 RK_PA1 2 &pcfg_pull_up_8ma>, +- <3 RK_PA2 2 &pcfg_pull_up_8ma>, +- <3 RK_PA3 2 &pcfg_pull_up_8ma>, +- <3 RK_PA4 2 &pcfg_pull_up_8ma>, +- <3 RK_PA5 2 &pcfg_pull_up_8ma>, +- <3 RK_PA6 2 &pcfg_pull_up_8ma>, +- <3 RK_PA7 2 &pcfg_pull_up_8ma>; +- }; +- }; +- +- flash { +- flash_csn0: flash-csn0 { +- rockchip,pins = +- <3 RK_PB5 1 &pcfg_pull_none>; +- }; +- +- flash_rdy: flash-rdy { +- rockchip,pins = +- <3 RK_PB4 1 &pcfg_pull_none>; +- }; +- +- flash_ale: flash-ale { +- rockchip,pins = +- <3 RK_PB3 1 &pcfg_pull_none>; +- }; +- +- flash_cle: flash-cle { +- rockchip,pins = +- <3 RK_PB1 1 &pcfg_pull_none>; +- }; +- +- flash_wrn: flash-wrn { +- rockchip,pins = +- <3 RK_PB0 1 &pcfg_pull_none>; +- }; +- +- flash_rdn: flash-rdn { +- rockchip,pins = +- <3 RK_PB2 1 &pcfg_pull_none>; +- }; +- +- flash_bus8: flash-bus8 { +- rockchip,pins = +- <3 RK_PA0 1 &pcfg_pull_up_12ma>, +- <3 RK_PA1 1 &pcfg_pull_up_12ma>, +- <3 RK_PA2 1 &pcfg_pull_up_12ma>, +- <3 RK_PA3 1 &pcfg_pull_up_12ma>, +- <3 RK_PA4 1 &pcfg_pull_up_12ma>, +- <3 RK_PA5 1 &pcfg_pull_up_12ma>, +- <3 RK_PA6 1 &pcfg_pull_up_12ma>, +- <3 RK_PA7 1 &pcfg_pull_up_12ma>; +- }; +- }; +- +- gmac { +- rmii_pins: rmii-pins { +- rockchip,pins = +- /* mac_txen */ +- <1 RK_PC1 3 &pcfg_pull_none_12ma>, +- /* mac_txd1 */ +- <1 RK_PC3 3 &pcfg_pull_none_12ma>, +- /* mac_txd0 */ +- <1 RK_PC2 3 &pcfg_pull_none_12ma>, +- /* mac_rxd0 */ +- <1 RK_PC4 3 &pcfg_pull_none>, +- /* mac_rxd1 */ +- <1 RK_PC5 3 &pcfg_pull_none>, +- /* mac_rxer */ +- <1 RK_PB7 3 &pcfg_pull_none>, +- /* mac_rxdv */ +- <1 RK_PC0 3 &pcfg_pull_none>, +- /* mac_mdio */ +- <1 RK_PB6 3 &pcfg_pull_none>, +- /* mac_mdc */ +- <1 RK_PB5 3 &pcfg_pull_none>; +- }; +- +- mac_refclk_12ma: mac-refclk-12ma { +- rockchip,pins = +- <1 RK_PB4 3 &pcfg_pull_none_12ma>; +- }; +- +- mac_refclk: mac-refclk { +- rockchip,pins = +- <1 RK_PB4 3 &pcfg_pull_none>; +- }; +- }; +- +- gmac-m1 { +- rmiim1_pins: rmiim1-pins { +- rockchip,pins = +- /* mac_txen */ +- <4 RK_PB7 2 &pcfg_pull_none_12ma>, +- /* mac_txd1 */ +- <4 RK_PA5 2 &pcfg_pull_none_12ma>, +- /* mac_txd0 */ +- <4 RK_PA4 2 &pcfg_pull_none_12ma>, +- /* mac_rxd0 */ +- <4 RK_PA2 2 &pcfg_pull_none>, +- /* mac_rxd1 */ +- <4 RK_PA3 2 &pcfg_pull_none>, +- /* mac_rxer */ +- <4 RK_PA0 2 &pcfg_pull_none>, +- /* mac_rxdv */ +- <4 RK_PA1 2 &pcfg_pull_none>, +- /* mac_mdio */ +- <4 RK_PB6 2 &pcfg_pull_none>, +- /* mac_mdc */ +- <4 RK_PB5 2 &pcfg_pull_none>; +- }; +- +- macm1_refclk_12ma: macm1-refclk-12ma { +- rockchip,pins = +- <4 RK_PB4 2 &pcfg_pull_none_12ma>; +- }; +- +- macm1_refclk: macm1-refclk { +- rockchip,pins = +- <4 RK_PB4 2 &pcfg_pull_none>; +- }; +- }; +- +- i2c0 { +- i2c0_xfer: i2c0-xfer { +- rockchip,pins = +- <1 RK_PD0 2 &pcfg_pull_none_smt>, +- <1 RK_PD1 2 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c1 { +- i2c1_xfer: i2c1-xfer { +- rockchip,pins = +- <0 RK_PB3 1 &pcfg_pull_none_smt>, +- <0 RK_PB4 1 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c2 { +- i2c2_xfer: i2c2-xfer { +- rockchip,pins = +- <2 RK_PA2 3 &pcfg_pull_none_smt>, +- <2 RK_PA3 3 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c3-m0 { +- i2c3m0_xfer: i2c3m0-xfer { +- rockchip,pins = +- <0 RK_PB7 2 &pcfg_pull_none_smt>, +- <0 RK_PC0 2 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c3-m1 { +- i2c3m1_xfer: i2c3m1-xfer { +- rockchip,pins = +- <3 RK_PB4 2 &pcfg_pull_none_smt>, +- <3 RK_PB5 2 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c3-m2 { +- i2c3m2_xfer: i2c3m2-xfer { +- rockchip,pins = +- <2 RK_PA1 3 &pcfg_pull_none_smt>, +- <2 RK_PA0 3 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2s_2ch_0 { +- i2s_2ch_0_mclk: i2s-2ch-0-mclk { +- rockchip,pins = +- <4 RK_PB4 1 &pcfg_pull_none>; +- }; +- +- i2s_2ch_0_sclk: i2s-2ch-0-sclk { +- rockchip,pins = +- <4 RK_PB5 1 &pcfg_pull_none>; +- }; +- +- i2s_2ch_0_lrck: i2s-2ch-0-lrck { +- rockchip,pins = +- <4 RK_PB6 1 &pcfg_pull_none>; +- }; +- +- i2s_2ch_0_sdo: i2s-2ch-0-sdo { +- rockchip,pins = +- <4 RK_PB7 1 &pcfg_pull_none>; +- }; +- +- i2s_2ch_0_sdi: i2s-2ch-0-sdi { +- rockchip,pins = +- <4 RK_PC0 1 &pcfg_pull_none>; +- }; +- }; +- +- i2s_8ch_0 { +- i2s_8ch_0_mclk: i2s-8ch-0-mclk { +- rockchip,pins = +- <2 RK_PA4 1 &pcfg_pull_none>; +- }; +- +- i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { +- rockchip,pins = +- <2 RK_PA5 1 &pcfg_pull_none>; +- }; +- +- i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { +- rockchip,pins = +- <2 RK_PA6 1 &pcfg_pull_none>; +- }; +- +- i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { +- rockchip,pins = +- <2 RK_PA7 1 &pcfg_pull_none>; +- }; +- +- i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { +- rockchip,pins = +- <2 RK_PB0 1 &pcfg_pull_none>; +- }; +- +- i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { +- rockchip,pins = +- <2 RK_PB1 1 &pcfg_pull_none>; +- }; +- +- i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 { +- rockchip,pins = +- <2 RK_PB2 1 &pcfg_pull_none>; +- }; +- +- i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 { +- rockchip,pins = +- <2 RK_PB3 1 &pcfg_pull_none>; +- }; +- +- i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 { +- rockchip,pins = +- <2 RK_PB4 1 &pcfg_pull_none>; +- }; +- +- i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 { +- rockchip,pins = +- <2 RK_PB5 1 &pcfg_pull_none>; +- }; +- +- i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 { +- rockchip,pins = +- <2 RK_PB6 1 &pcfg_pull_none>; +- }; +- +- i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 { +- rockchip,pins = +- <2 RK_PB7 1 &pcfg_pull_none>; +- }; +- +- i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 { +- rockchip,pins = +- <2 RK_PC0 1 &pcfg_pull_none>; +- }; +- }; +- +- i2s_8ch_1_m0 { +- i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk { +- rockchip,pins = +- <1 RK_PA2 2 &pcfg_pull_none>; +- }; +- +- i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx { +- rockchip,pins = +- <1 RK_PA3 2 &pcfg_pull_none>; +- }; +- +- i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx { +- rockchip,pins = +- <1 RK_PA4 2 &pcfg_pull_none>; +- }; +- +- i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx { +- rockchip,pins = +- <1 RK_PA5 2 &pcfg_pull_none>; +- }; +- +- i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx { +- rockchip,pins = +- <1 RK_PA6 2 &pcfg_pull_none>; +- }; +- +- i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 { +- rockchip,pins = +- <1 RK_PA7 2 &pcfg_pull_none>; +- }; +- +- i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 { +- rockchip,pins = +- <1 RK_PB0 2 &pcfg_pull_none>; +- }; +- +- i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 { +- rockchip,pins = +- <1 RK_PB1 2 &pcfg_pull_none>; +- }; +- +- i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 { +- rockchip,pins = +- <1 RK_PB2 2 &pcfg_pull_none>; +- }; +- +- i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 { +- rockchip,pins = +- <1 RK_PB3 2 &pcfg_pull_none>; +- }; +- }; +- +- i2s_8ch_1_m1 { +- i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk { +- rockchip,pins = +- <1 RK_PB4 2 &pcfg_pull_none>; +- }; +- +- i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx { +- rockchip,pins = +- <1 RK_PB5 2 &pcfg_pull_none>; +- }; +- +- i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx { +- rockchip,pins = +- <1 RK_PB6 2 &pcfg_pull_none>; +- }; +- +- i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx { +- rockchip,pins = +- <1 RK_PB7 2 &pcfg_pull_none>; +- }; +- +- i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx { +- rockchip,pins = +- <1 RK_PC0 2 &pcfg_pull_none>; +- }; +- +- i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 { +- rockchip,pins = +- <1 RK_PC1 2 &pcfg_pull_none>; +- }; +- +- i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 { +- rockchip,pins = +- <1 RK_PC2 2 &pcfg_pull_none>; +- }; +- +- i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 { +- rockchip,pins = +- <1 RK_PC3 2 &pcfg_pull_none>; +- }; +- +- i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 { +- rockchip,pins = +- <1 RK_PC4 2 &pcfg_pull_none>; +- }; +- +- i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 { +- rockchip,pins = +- <1 RK_PC5 2 &pcfg_pull_none>; +- }; +- }; +- +- pdm_m0 { +- pdm_m0_clk: pdm-m0-clk { +- rockchip,pins = +- <1 RK_PA4 3 &pcfg_pull_none>; +- }; +- +- pdm_m0_sdi0: pdm-m0-sdi0 { +- rockchip,pins = +- <1 RK_PB3 3 &pcfg_pull_none>; +- }; +- +- pdm_m0_sdi1: pdm-m0-sdi1 { +- rockchip,pins = +- <1 RK_PB2 3 &pcfg_pull_none>; +- }; +- +- pdm_m0_sdi2: pdm-m0-sdi2 { +- rockchip,pins = +- <1 RK_PB1 3 &pcfg_pull_none>; +- }; +- +- pdm_m0_sdi3: pdm-m0-sdi3 { +- rockchip,pins = +- <1 RK_PB0 3 &pcfg_pull_none>; +- }; +- }; +- +- pdm_m1 { +- pdm_m1_clk: pdm-m1-clk { +- rockchip,pins = +- <1 RK_PB6 4 &pcfg_pull_none>; +- }; +- +- pdm_m1_sdi0: pdm-m1-sdi0 { +- rockchip,pins = +- <1 RK_PC5 4 &pcfg_pull_none>; +- }; +- +- pdm_m1_sdi1: pdm-m1-sdi1 { +- rockchip,pins = +- <1 RK_PC4 4 &pcfg_pull_none>; +- }; +- +- pdm_m1_sdi2: pdm-m1-sdi2 { +- rockchip,pins = +- <1 RK_PC3 4 &pcfg_pull_none>; +- }; +- +- pdm_m1_sdi3: pdm-m1-sdi3 { +- rockchip,pins = +- <1 RK_PC2 4 &pcfg_pull_none>; +- }; +- }; +- +- pdm_m2 { +- pdm_m2_clkm: pdm-m2-clkm { +- rockchip,pins = +- <2 RK_PA4 3 &pcfg_pull_none>; +- }; +- +- pdm_m2_clk: pdm-m2-clk { +- rockchip,pins = +- <2 RK_PA6 2 &pcfg_pull_none>; +- }; +- +- pdm_m2_sdi0: pdm-m2-sdi0 { +- rockchip,pins = +- <2 RK_PB5 2 &pcfg_pull_none>; +- }; +- +- pdm_m2_sdi1: pdm-m2-sdi1 { +- rockchip,pins = +- <2 RK_PB6 2 &pcfg_pull_none>; +- }; +- +- pdm_m2_sdi2: pdm-m2-sdi2 { +- rockchip,pins = +- <2 RK_PB7 2 &pcfg_pull_none>; +- }; +- +- pdm_m2_sdi3: pdm-m2-sdi3 { +- rockchip,pins = +- <2 RK_PC0 2 &pcfg_pull_none>; +- }; +- }; +- +- pwm0 { +- pwm0_pin: pwm0-pin { +- rockchip,pins = +- <0 RK_PB5 1 &pcfg_pull_none>; +- }; +- +- pwm0_pin_pull_down: pwm0-pin-pull-down { +- rockchip,pins = +- <0 RK_PB5 1 &pcfg_pull_down>; +- }; +- }; +- +- pwm1 { +- pwm1_pin: pwm1-pin { +- rockchip,pins = +- <0 RK_PB6 1 &pcfg_pull_none>; +- }; +- +- pwm1_pin_pull_down: pwm1-pin-pull-down { +- rockchip,pins = +- <0 RK_PB6 1 &pcfg_pull_down>; +- }; +- }; +- +- pwm2 { +- pwm2_pin: pwm2-pin { +- rockchip,pins = +- <0 RK_PB7 1 &pcfg_pull_none>; +- }; +- +- pwm2_pin_pull_down: pwm2-pin-pull-down { +- rockchip,pins = +- <0 RK_PB7 1 &pcfg_pull_down>; +- }; +- }; +- +- pwm3 { +- pwm3_pin: pwm3-pin { +- rockchip,pins = +- <0 RK_PC0 1 &pcfg_pull_none>; +- }; +- +- pwm3_pin_pull_down: pwm3-pin-pull-down { +- rockchip,pins = +- <0 RK_PC0 1 &pcfg_pull_down>; +- }; +- }; +- +- pwm4 { +- pwm4_pin: pwm4-pin { +- rockchip,pins = +- <0 RK_PA1 2 &pcfg_pull_none>; +- }; +- +- pwm4_pin_pull_down: pwm4-pin-pull-down { +- rockchip,pins = +- <0 RK_PA1 2 &pcfg_pull_down>; +- }; +- }; +- +- pwm5 { +- pwm5_pin: pwm5-pin { +- rockchip,pins = +- <0 RK_PC1 2 &pcfg_pull_none>; +- }; +- +- pwm5_pin_pull_down: pwm5-pin-pull-down { +- rockchip,pins = +- <0 RK_PC1 2 &pcfg_pull_down>; +- }; +- }; +- +- pwm6 { +- pwm6_pin: pwm6-pin { +- rockchip,pins = +- <0 RK_PC2 2 &pcfg_pull_none>; +- }; +- +- pwm6_pin_pull_down: pwm6-pin-pull-down { +- rockchip,pins = +- <0 RK_PC2 2 &pcfg_pull_down>; +- }; +- }; +- +- pwm7 { +- pwm7_pin: pwm7-pin { +- rockchip,pins = +- <2 RK_PB0 2 &pcfg_pull_none>; +- }; +- +- pwm7_pin_pull_down: pwm7-pin-pull-down { +- rockchip,pins = +- <2 RK_PB0 2 &pcfg_pull_down>; +- }; +- }; +- +- pwm8 { +- pwm8_pin: pwm8-pin { +- rockchip,pins = +- <2 RK_PB2 2 &pcfg_pull_none>; +- }; +- +- pwm8_pin_pull_down: pwm8-pin-pull-down { +- rockchip,pins = +- <2 RK_PB2 2 &pcfg_pull_down>; +- }; +- }; +- +- pwm9 { +- pwm9_pin: pwm9-pin { +- rockchip,pins = +- <2 RK_PB3 2 &pcfg_pull_none>; +- }; +- +- pwm9_pin_pull_down: pwm9-pin-pull-down { +- rockchip,pins = +- <2 RK_PB3 2 &pcfg_pull_down>; +- }; +- }; +- +- pwm10 { +- pwm10_pin: pwm10-pin { +- rockchip,pins = +- <2 RK_PB4 2 &pcfg_pull_none>; +- }; +- +- pwm10_pin_pull_down: pwm10-pin-pull-down { +- rockchip,pins = +- <2 RK_PB4 2 &pcfg_pull_down>; +- }; +- }; +- +- pwm11 { +- pwm11_pin: pwm11-pin { +- rockchip,pins = +- <2 RK_PC0 4 &pcfg_pull_none>; +- }; +- +- pwm11_pin_pull_down: pwm11-pin-pull-down { +- rockchip,pins = +- <2 RK_PC0 4 &pcfg_pull_down>; +- }; +- }; +- +- rtc { +- rtc_32k: rtc-32k { +- rockchip,pins = +- <0 RK_PC3 1 &pcfg_pull_none>; +- }; +- }; +- +- sdmmc { +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = +- <4 RK_PD5 1 &pcfg_pull_none_4ma>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = +- <4 RK_PD4 1 &pcfg_pull_up_4ma>; +- }; +- +- sdmmc_det: sdmmc-det { +- rockchip,pins = +- <0 RK_PA3 1 &pcfg_pull_up_4ma>; +- }; +- +- sdmmc_pwren: sdmmc-pwren { +- rockchip,pins = +- <4 RK_PD6 1 &pcfg_pull_none_4ma>; +- }; +- +- sdmmc_bus1: sdmmc-bus1 { +- rockchip,pins = +- <4 RK_PD0 1 &pcfg_pull_up_4ma>; +- }; +- +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = +- <4 RK_PD0 1 &pcfg_pull_up_4ma>, +- <4 RK_PD1 1 &pcfg_pull_up_4ma>, +- <4 RK_PD2 1 &pcfg_pull_up_4ma>, +- <4 RK_PD3 1 &pcfg_pull_up_4ma>; +- }; +- }; +- +- sdio { +- sdio_clk: sdio-clk { +- rockchip,pins = +- <4 RK_PA5 1 &pcfg_pull_none_8ma>; +- }; +- +- sdio_cmd: sdio-cmd { +- rockchip,pins = +- <4 RK_PA4 1 &pcfg_pull_up_8ma>; +- }; +- +- sdio_pwren: sdio-pwren { +- rockchip,pins = +- <0 RK_PA2 1 &pcfg_pull_none_8ma>; +- }; +- +- sdio_wrpt: sdio-wrpt { +- rockchip,pins = +- <0 RK_PA1 1 &pcfg_pull_none_8ma>; +- }; +- +- sdio_intn: sdio-intn { +- rockchip,pins = +- <0 RK_PA0 1 &pcfg_pull_none_8ma>; +- }; +- +- sdio_bus1: sdio-bus1 { +- rockchip,pins = +- <4 RK_PA0 1 &pcfg_pull_up_8ma>; +- }; +- +- sdio_bus4: sdio-bus4 { +- rockchip,pins = +- <4 RK_PA0 1 &pcfg_pull_up_8ma>, +- <4 RK_PA1 1 &pcfg_pull_up_8ma>, +- <4 RK_PA2 1 &pcfg_pull_up_8ma>, +- <4 RK_PA3 1 &pcfg_pull_up_8ma>; +- }; +- }; +- +- spdif_in { +- spdif_in: spdif-in { +- rockchip,pins = +- <0 RK_PC2 1 &pcfg_pull_none>; +- }; +- }; +- +- spdif_out { +- spdif_out: spdif-out { +- rockchip,pins = +- <0 RK_PC1 1 &pcfg_pull_none>; +- }; +- }; +- +- spi0 { +- spi0_clk: spi0-clk { +- rockchip,pins = +- <2 RK_PA2 2 &pcfg_pull_up_4ma>; +- }; +- +- spi0_csn0: spi0-csn0 { +- rockchip,pins = +- <2 RK_PA3 2 &pcfg_pull_up_4ma>; +- }; +- +- spi0_miso: spi0-miso { +- rockchip,pins = +- <2 RK_PA0 2 &pcfg_pull_up_4ma>; +- }; +- +- spi0_mosi: spi0-mosi { +- rockchip,pins = +- <2 RK_PA1 2 &pcfg_pull_up_4ma>; +- }; +- }; +- +- spi1 { +- spi1_clk: spi1-clk { +- rockchip,pins = +- <3 RK_PB3 3 &pcfg_pull_up_4ma>; +- }; +- +- spi1_csn0: spi1-csn0 { +- rockchip,pins = +- <3 RK_PB5 3 &pcfg_pull_up_4ma>; +- }; +- +- spi1_miso: spi1-miso { +- rockchip,pins = +- <3 RK_PB2 3 &pcfg_pull_up_4ma>; +- }; +- +- spi1_mosi: spi1-mosi { +- rockchip,pins = +- <3 RK_PB4 3 &pcfg_pull_up_4ma>; +- }; +- }; +- +- spi1-m1 { +- spi1m1_miso: spi1m1-miso { +- rockchip,pins = +- <2 RK_PA4 2 &pcfg_pull_up_4ma>; +- }; +- +- spi1m1_mosi: spi1m1-mosi { +- rockchip,pins = +- <2 RK_PA5 2 &pcfg_pull_up_4ma>; +- }; +- +- spi1m1_clk: spi1m1-clk { +- rockchip,pins = +- <2 RK_PA7 2 &pcfg_pull_up_4ma>; +- }; +- +- spi1m1_csn0: spi1m1-csn0 { +- rockchip,pins = +- <2 RK_PB1 2 &pcfg_pull_up_4ma>; +- }; +- }; +- +- spi2 { +- spi2_clk: spi2-clk { +- rockchip,pins = +- <1 RK_PD0 3 &pcfg_pull_up_4ma>; +- }; +- +- spi2_csn0: spi2-csn0 { +- rockchip,pins = +- <1 RK_PD1 3 &pcfg_pull_up_4ma>; +- }; +- +- spi2_miso: spi2-miso { +- rockchip,pins = +- <1 RK_PC6 3 &pcfg_pull_up_4ma>; +- }; +- +- spi2_mosi: spi2-mosi { +- rockchip,pins = +- <1 RK_PC7 3 &pcfg_pull_up_4ma>; +- }; +- }; +- +- tsadc { +- tsadc_otp_pin: tsadc-otp-pin { +- rockchip,pins = +- <0 RK_PB2 0 &pcfg_pull_none>; +- }; +- +- tsadc_otp_out: tsadc-otp-out { +- rockchip,pins = +- <0 RK_PB2 1 &pcfg_pull_none>; +- }; +- }; +- +- uart0 { +- uart0_xfer: uart0-xfer { +- rockchip,pins = +- <2 RK_PA1 1 &pcfg_pull_up>, +- <2 RK_PA0 1 &pcfg_pull_up>; +- }; +- +- uart0_cts: uart0-cts { +- rockchip,pins = +- <2 RK_PA2 1 &pcfg_pull_none>; +- }; +- +- uart0_rts: uart0-rts { +- rockchip,pins = +- <2 RK_PA3 1 &pcfg_pull_none>; +- }; +- +- uart0_rts_pin: uart0-rts-pin { +- rockchip,pins = +- <2 RK_PA3 0 &pcfg_pull_none>; +- }; +- }; +- +- uart1 { +- uart1_xfer: uart1-xfer { +- rockchip,pins = +- <1 RK_PD1 1 &pcfg_pull_up>, +- <1 RK_PD0 1 &pcfg_pull_up>; +- }; +- +- uart1_cts: uart1-cts { +- rockchip,pins = +- <1 RK_PC6 1 &pcfg_pull_none>; +- }; +- +- uart1_rts: uart1-rts { +- rockchip,pins = +- <1 RK_PC7 1 &pcfg_pull_none>; +- }; +- }; +- +- uart2-m0 { +- uart2m0_xfer: uart2m0-xfer { +- rockchip,pins = +- <1 RK_PC7 2 &pcfg_pull_up>, +- <1 RK_PC6 2 &pcfg_pull_up>; +- }; +- }; +- +- uart2-m1 { +- uart2m1_xfer: uart2m1-xfer { +- rockchip,pins = +- <4 RK_PD3 2 &pcfg_pull_up>, +- <4 RK_PD2 2 &pcfg_pull_up>; +- }; +- }; +- +- uart3 { +- uart3_xfer: uart3-xfer { +- rockchip,pins = +- <3 RK_PB5 4 &pcfg_pull_up>, +- <3 RK_PB4 4 &pcfg_pull_up>; +- }; +- }; +- +- uart3-m1 { +- uart3m1_xfer: uart3m1-xfer { +- rockchip,pins = +- <0 RK_PC2 3 &pcfg_pull_up>, +- <0 RK_PC1 3 &pcfg_pull_up>; +- }; +- }; +- +- uart4 { +- uart4_xfer: uart4-xfer { +- rockchip,pins = +- <4 RK_PB1 1 &pcfg_pull_up>, +- <4 RK_PB0 1 &pcfg_pull_up>; +- }; +- +- uart4_cts: uart4-cts { +- rockchip,pins = +- <4 RK_PA6 1 &pcfg_pull_none>; +- }; +- +- uart4_rts: uart4-rts { +- rockchip,pins = +- <4 RK_PA7 1 &pcfg_pull_none>; +- }; +- +- uart4_rts_pin: uart4-rts-pin { +- rockchip,pins = +- <4 RK_PA7 0 &pcfg_pull_none>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3318-a95x-z2.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3318-a95x-z2.dts +deleted file mode 100644 +index 763cf9b4620e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3318-a95x-z2.dts ++++ /dev/null +@@ -1,385 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-/dts-v1/; +-#include +-#include "rk3328.dtsi" +- +-/ { +- model = "A95X Z2"; +- compatible = "zkmagic,a95x-z2", "rockchip,rk3318"; +- +- aliases { +- mmc0 = &sdmmc; +- mmc1 = &sdio; +- mmc2 = &emmc; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 0>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1800000>; +- poll-interval = <100>; +- +- recovery { +- label = "recovery"; +- linux,code = ; +- press-threshold-microvolt = <17000>; +- }; +- }; +- +- ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; +- pinctrl-0 = <&ir_int>; +- pinctrl-names = "default"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&cyx_led_pin>; +- pinctrl-names = "default"; +- +- cyx_led: led-0 { +- default-state = "on"; +- gpios = <&gpio2 RK_PC7 GPIO_ACTIVE_LOW>; +- label = "CYX_LED"; +- }; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- pinctrl-0 = <&wifi_enable_h>; +- pinctrl-names = "default"; +- reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; +- }; +- +- spdif-sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "SPDIF"; +- +- simple-audio-card,cpu { +- sound-dai = <&spdif>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&spdif_out>; +- }; +- }; +- +- spdif_out: spdif-out { +- compatible = "linux,spdif-dit"; +- #sound-dai-cells = <0>; +- }; +- +- /* Power tree */ +- vccio_1v8: vccio-1v8-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vccio_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vccio_3v3: vccio-3v3-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vccio_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vcc_otg_vbus: otg-vbus-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; +- pinctrl-0 = <&otg_vbus_drv>; +- pinctrl-names = "default"; +- regulator-name = "vcc_otg_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- }; +- +- vcc_sd: sdmmc-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; +- pinctrl-0 = <&sdmmc0m1_pin>; +- pinctrl-names = "default"; +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vccio_3v3>; +- }; +- +- vdd_arm: vdd-arm { +- compatible = "pwm-regulator"; +- pwms = <&pwm0 0 5000 1>; +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1400000>; +- regulator-settling-time-up-us = <250>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_log: vdd-log { +- compatible = "pwm-regulator"; +- pwms = <&pwm1 0 5000 1>; +- regulator-name = "vdd_log"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <1300000>; +- regulator-settling-time-up-us = <250>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&analog_sound { +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu0_opp_table { +- opp-1200000000 { +- status = "disabled"; +- }; +- +- opp-1296000000 { +- status = "disabled"; +- }; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- non-removable; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&gmac2phy { +- assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; +- assigned-clock-rate = <50000000>; +- assigned-clocks = <&cru SCLK_MAC2PHY>; +- clock_in_out = "output"; +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&vdd_log>; +-}; +- +-&hdmi { +- ddc-i2c-scl-high-time-ns = <9625>; +- ddc-i2c-scl-low-time-ns = <10000>; +- status = "okay"; +-}; +- +-&hdmiphy { +- status = "okay"; +-}; +- +-&hdmi_sound { +- status = "okay"; +-}; +- +-&i2s0 { +- status = "okay"; +-}; +- +-&i2s1 { +- status = "okay"; +-}; +- +-&io_domains { +- pmuio-supply = <&vccio_3v3>; +- vccio1-supply = <&vccio_3v3>; +- vccio2-supply = <&vccio_1v8>; +- vccio3-supply = <&vccio_3v3>; +- vccio4-supply = <&vccio_1v8>; +- vccio5-supply = <&vccio_3v3>; +- vccio6-supply = <&vccio_3v3>; +- status = "okay"; +-}; +- +-&pinctrl { +- ir { +- ir_int: ir-int { +- rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- leds { +- cyx_led_pin: cyx-led-pin { +- rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pwm0 { +- pwm0_pin_pull_up: pwm0-pin-pull-up { +- rockchip,pins = <2 RK_PA4 1 &pcfg_pull_up>; +- }; +- }; +- +- pwm1 { +- pwm1_pin_pull_up: pwm1-pin-pull-up { +- rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>; +- }; +- }; +- +- sdio-pwrseq { +- wifi_enable_h: wifi-enable-h { +- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdmmc1 { +- clk_32k_out: clk-32k-out { +- rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>; +- }; +- }; +- +- usb { +- host_vbus_drv: host-vbus-drv { +- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- otg_vbus_drv: otg-vbus-drv { +- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm0 { +- pinctrl-0 = <&pwm0_pin_pull_up>; +- pinctrl-names = "active"; +- status = "okay"; +-}; +- +-&pwm1 { +- pinctrl-0 = <&pwm1_pin_pull_up>; +- pinctrl-names = "active"; +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vccio_1v8>; +- status = "okay"; +-}; +- +-&sdio { +- bus-width = <4>; +- cap-sd-highspeed; +- cap-sdio-irq; +- keep-power-in-suspend; +- max-frequency = <125000000>; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk &clk_32k_out>; +- pinctrl-names = "default"; +- sd-uhs-sdr104; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-sd-highspeed; +- pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; +- pinctrl-names = "default"; +- vmmc-supply = <&vcc_sd>; +- status = "okay"; +-}; +- +-&spdif { +- pinctrl-0 = <&spdifm0_tx>; +- status = "okay"; +-}; +- +-&soc_crit { +- temperature = <115000>; /* millicelsius */ +-}; +- +-&target { +- temperature = <105000>; /* millicelsius */ +-}; +- +-&threshold { +- temperature = <90000>; /* millicelsius */ +-}; +- +-&tsadc { +- rockchip,hw-tshut-temp = <120000>; +- status = "okay"; +-}; +- +-&u2phy { +- status = "okay"; +-}; +- +-&u2phy_host { +- status = "okay"; +-}; +- +-&u2phy_otg { +- phy-supply = <&vcc_otg_vbus>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-0 = <&uart0_xfer &uart0_cts>; +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb20_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbdrd3 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&vop { +- status = "okay"; +-}; +- +-&vop_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3326-odroid-go2.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3326-odroid-go2.dts +deleted file mode 100644 +index 7fc674a99a6c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3326-odroid-go2.dts ++++ /dev/null +@@ -1,616 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Hardkernel Co., Ltd +- * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH +- */ +- +-/dts-v1/; +-#include +-#include +-#include +-#include "rk3326.dtsi" +- +-/ { +- model = "ODROID-GO Advance"; +- compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326"; +- +- aliases { +- mmc0 = &sdmmc; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- adc-joystick { +- compatible = "adc-joystick"; +- io-channels = <&saradc 1>, +- <&saradc 2>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- axis@0 { +- reg = <0>; +- abs-flat = <10>; +- abs-fuzz = <10>; +- abs-range = <172 772>; +- linux,code = ; +- }; +- +- axis@1 { +- reg = <1>; +- abs-flat = <10>; +- abs-fuzz = <10>; +- abs-range = <278 815>; +- linux,code = ; +- }; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- power-supply = <&vcc_bl>; +- pwms = <&pwm1 0 25000 0>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&btn_pins>; +- +- /* +- * *** ODROIDGO2-Advance Switch layout *** +- * |------------------------------------------------| +- * | sw15 sw16 | +- * |------------------------------------------------| +- * | sw1 |-------------------| sw8 | +- * | sw3 sw4 | | sw7 sw5 | +- * | sw2 | LCD Display | sw6 | +- * | | | | +- * | |-------------------| | +- * | sw9 sw10 sw11 sw12 sw13 sw14 | +- * |------------------------------------------------| +- */ +- +- sw1 { +- gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; +- label = "DPAD-UP"; +- linux,code = ; +- }; +- sw2 { +- gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; +- label = "DPAD-DOWN"; +- linux,code = ; +- }; +- sw3 { +- gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; +- label = "DPAD-LEFT"; +- linux,code = ; +- }; +- sw4 { +- gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>; +- label = "DPAD-RIGHT"; +- linux,code = ; +- }; +- sw5 { +- gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; +- label = "BTN-A"; +- linux,code = ; +- }; +- sw6 { +- gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; +- label = "BTN-B"; +- linux,code = ; +- }; +- sw7 { +- gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; +- label = "BTN-Y"; +- linux,code = ; +- }; +- sw8 { +- gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; +- label = "BTN-X"; +- linux,code = ; +- }; +- sw9 { +- gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; +- label = "F1"; +- linux,code = ; +- }; +- sw10 { +- gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>; +- label = "F2"; +- linux,code = ; +- }; +- sw11 { +- gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; +- label = "F3"; +- linux,code = ; +- }; +- sw12 { +- gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>; +- label = "F4"; +- linux,code = ; +- }; +- sw13 { +- gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>; +- label = "F5"; +- linux,code = ; +- }; +- sw14 { +- gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>; +- label = "F6"; +- linux,code = ; +- }; +- sw15 { +- gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; +- label = "TOP-LEFT"; +- linux,code = ; +- }; +- sw16 { +- gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>; +- label = "TOP-RIGHT"; +- linux,code = ; +- }; +- }; +- +- leds: gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&blue_led_pin>; +- +- blue_led: led-0 { +- label = "blue:heartbeat"; +- gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- rk817-sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "Analog"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; +- simple-audio-card,mclk-fs = <256>; +- simple-audio-card,widgets = +- "Microphone", "Mic Jack", +- "Headphone", "Headphones", +- "Speaker", "Speaker"; +- simple-audio-card,routing = +- "MICL", "Mic Jack", +- "Headphones", "HPOL", +- "Headphones", "HPOR", +- "Speaker", "SPKO"; +- +- simple-audio-card,codec { +- sound-dai = <&rk817>; +- }; +- +- simple-audio-card,cpu { +- sound-dai = <&i2s1_2ch>; +- }; +- }; +- +- vccsys: vccsys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v8_sys"; +- regulator-always-on; +- regulator-min-microvolt = <3800000>; +- regulator-max-microvolt = <3800000>; +- }; +- +- vcc_host: vcc_host { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_host"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- vin-supply = <&vccsys>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cru { +- assigned-clocks = <&cru PLL_NPLL>, +- <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, +- <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, +- <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>, +- <&cru PLL_CPLL>; +- +- assigned-clock-rates = <1188000000>, +- <200000000>, <200000000>, +- <150000000>, <150000000>, +- <100000000>, <200000000>, +- <17000000>; +-}; +- +-&display_subsystem { +- status = "okay"; +-}; +- +-&dsi { +- status = "okay"; +- +- ports { +- mipi_out: port@1 { +- reg = <1>; +- +- mipi_out_panel: endpoint { +- remote-endpoint = <&mipi_in_panel>; +- }; +- }; +- }; +- +- panel@0 { +- compatible = "elida,kd35t133"; +- reg = <0>; +- backlight = <&backlight>; +- iovcc-supply = <&vcc_lcd>; +- reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; +- rotation = <270>; +- vdd-supply = <&vcc_lcd>; +- +- port { +- mipi_in_panel: endpoint { +- remote-endpoint = <&mipi_out_panel>; +- }; +- }; +- }; +-}; +- +-&dsi_dphy { +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&vdd_logic>; +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- i2c-scl-falling-time-ns = <16>; +- i2c-scl-rising-time-ns = <280>; +- status = "okay"; +- +- rk817: pmic@20 { +- compatible = "rockchip,rk817"; +- reg = <0x20>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- clock-output-names = "rk808-clkout1", "xin32k"; +- clock-names = "mclk"; +- clocks = <&cru SCLK_I2S1_OUT>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>; +- wakeup-source; +- #clock-cells = <1>; +- #sound-dai-cells = <0>; +- +- vcc1-supply = <&vccsys>; +- vcc2-supply = <&vccsys>; +- vcc3-supply = <&vccsys>; +- vcc4-supply = <&vccsys>; +- vcc5-supply = <&vccsys>; +- vcc6-supply = <&vccsys>; +- vcc7-supply = <&vccsys>; +- +- regulators { +- vdd_logic: DCDC_REG1 { +- regulator-name = "vdd_logic"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1150000>; +- regulator-ramp-delay = <6001>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <950000>; +- }; +- }; +- +- vdd_arm: DCDC_REG2 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <950000>; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_3v3: DCDC_REG4 { +- regulator-name = "vcc_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_1v8: LDO_REG2 { +- regulator-name = "vcc_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vdd_1v0: LDO_REG3 { +- regulator-name = "vdd_1v0"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vcc3v3_pmu: LDO_REG4 { +- regulator-name = "vcc3v3_pmu"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vccio_sd: LDO_REG5 { +- regulator-name = "vccio_sd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_sd: LDO_REG6 { +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_bl: LDO_REG7 { +- regulator-name = "vcc_bl"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_lcd: LDO_REG8 { +- regulator-name = "vcc_lcd"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <2800000>; +- }; +- }; +- +- vcc_cam: LDO_REG9 { +- regulator-name = "vcc_cam"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- }; +- +- rk817_codec: codec { +- rockchip,mic-in-differential; +- }; +- }; +-}; +- +-/* EXT Header(P2): 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */ +-&i2c1 { +- clock-frequency = <400000>; +- status = "okay"; +-}; +- +-/* I2S 1 Channel Used */ +-&i2s1_2ch { +- status = "okay"; +-}; +- +-&io_domains { +- vccio1-supply = <&vcc_3v3>; +- vccio2-supply = <&vccio_sd>; +- vccio3-supply = <&vcc_3v3>; +- vccio4-supply = <&vcc_3v3>; +- vccio5-supply = <&vcc_3v3>; +- vccio6-supply = <&vcc_3v3>; +- status = "okay"; +-}; +- +-&pmu_io_domains { +- pmuio1-supply = <&vcc3v3_pmu>; +- pmuio2-supply = <&vcc3v3_pmu>; +- status = "okay"; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vcc_1v8>; +- status = "okay"; +-}; +- +-&sdmmc { +- cap-sd-highspeed; +- card-detect-delay = <200>; +- cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/ +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- vmmc-supply = <&vcc_sd>; +- vqmmc-supply = <&vccio_sd>; +- status = "okay"; +-}; +- +-&tsadc { +- status = "okay"; +-}; +- +-&u2phy { +- status = "okay"; +- +- u2phy_host: host-port { +- status = "okay"; +- }; +- +- u2phy_otg: otg-port { +- status = "disabled"; +- }; +-}; +- +-&usb20_otg { +- status = "okay"; +-}; +- +-/* EXT Header(P2): 2(RXD:GPIO1.C0),3(TXD:.C1),4(CTS:.C2),5(RTS:.C3) */ +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_xfer &uart1_cts>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2m1_xfer>; +- status = "okay"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&pinctrl { +- btns { +- btn_pins: btn-pins { +- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, +- <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, +- <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, +- <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, +- <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, +- <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, +- <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, +- <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, +- <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, +- <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, +- <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, +- <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, +- <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, +- <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, +- <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, +- <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- headphone { +- hp_det: hp-det { +- rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- leds { +- blue_led_pin: blue-led-pin { +- rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- dc_det: dc-det { +- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- pmic_int: pmic-int { +- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- soc_slppin_gpio: soc_slppin_gpio { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- +- soc_slppin_rst: soc_slppin_rst { +- rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>; +- }; +- +- soc_slppin_slp: soc_slppin_slp { +- rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3326.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3326.dtsi +deleted file mode 100644 +index 2ba6da125137..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3326.dtsi ++++ /dev/null +@@ -1,15 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd +- */ +- +-#include "px30.dtsi" +- +-&display_subsystem { +- ports = <&vopb_out>; +-}; +- +-/delete-node/ &dsi_in_vopl; +-/delete-node/ &lvds_vopl_in; +-/delete-node/ &vopl; +-/delete-node/ &vopl_mmu; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3328-a1.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3328-a1.dts +deleted file mode 100644 +index de2d3e88e27f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3328-a1.dts ++++ /dev/null +@@ -1,366 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +-// Copyright (c) 2017-2019 Arm Ltd. +- +-/dts-v1/; +-#include "rk3328.dtsi" +- +-/ { +- model = "Beelink A1"; +- compatible = "azw,beelink-a1", "rockchip,rk3328"; +- +- aliases { +- mmc0 = &sdmmc; +- mmc1 = &emmc; +- }; +- +- /* +- * UART pins, as viewed with bottom of case removed: +- * +- * Front +- * /------- +- * L / o <- Gnd +- * e / o <-- Rx +- * f / o <--- Tx +- * t / o <---- +3.3v +- * | +- */ +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- gmac_clkin: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "gmac_clkin"; +- #clock-cells = <0>; +- }; +- +- vcc_host_5v: usb3-current-switch { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb30_host_drv>; +- regulator-name = "vcc_host_5v"; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_sys: vcc-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; +- linux,rc-map-name = "rc-beelink-gs1"; +- }; +-}; +- +-&analog_sound { +- simple-audio-card,name = "Analog A/V"; +- status = "okay"; +-}; +- +-&codec { +- mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- no-sd; +- no-sdio; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +- vmmc-supply = <&vcc_io>; +- vqmmc-supply = <&vcc18_emmc>; +- status = "okay"; +-}; +- +-&gmac2io { +- assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; +- assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; +- clock_in_out = "input"; +- phy-handle = <&rtl8211f>; +- phy-mode = "rgmii"; +- phy-supply = <&vcc_io>; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmiim1_pins>; +- snps,aal; +- snps,pbl = <0x4>; +- tx_delay = <0x26>; +- rx_delay = <0x11>; +- status = "okay"; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtl8211f: ethernet-phy@0 { +- reg = <0>; +- reset-assert-us = <10000>; +- reset-deassert-us = <30000>; +- reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&gpu { +- mali-supply = <&vdd_logic>; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmiphy { +- status = "okay"; +-}; +- +-&hdmi_sound { +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <1000000>; +- i2c-scl-falling-time-ns = <5>; +- i2c-scl-rising-time-ns = <83>; +- status = "okay"; +- +- pmic@18 { +- compatible = "rockchip,rk805"; +- reg = <0x18>; +- interrupt-parent = <&gpio2>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc5-supply = <&vcc_io>; +- vcc6-supply = <&vcc_io>; +- +- regulators { +- vdd_logic: DCDC_REG1 { +- regulator-name = "vdd_logic"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vdd_arm: DCDC_REG2 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <950000>; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_io: DCDC_REG4 { +- regulator-name = "vcc_io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vdd_18: LDO_REG1 { +- regulator-name = "vdd_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc18_emmc: LDO_REG2 { +- regulator-name = "vcc_18emmc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vdd_11: LDO_REG3 { +- regulator-name = "vdd_11"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1100000>; +- }; +- }; +- }; +- }; +-}; +- +-&i2s0 { +- status = "okay"; +-}; +- +-&i2s1 { +- status = "okay"; +-}; +- +-&io_domains { +- vccio1-supply = <&vcc_io>; +- vccio2-supply = <&vcc18_emmc>; +- vccio3-supply = <&vcc_io>; +- vccio4-supply = <&vdd_18>; +- vccio5-supply = <&vcc_io>; +- vccio6-supply = <&vdd_18>; +- pmuio-supply = <&vcc_io>; +- status = "okay"; +-}; +- +-&pinctrl { +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- usb3 { +- usb30_host_drv: usb30-host-drv { +- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- wifi { +- bt_dis: bt-dis { +- rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- +- bt_wake_host: bt-wake-host { +- rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- chip_en: chip-en { +- rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- +- host_wake_bt: host-wake-bt { +- rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- +- wl_dis: wl-dis { +- rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- +- wl_wake_host: wl-wake-host { +- rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; +- vmmc-supply = <&vcc_io>; +- vqmmc-supply = <&vcc_io>; +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <0>; +- rockchip,hw-tshut-polarity = <0>; +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&u2phy { +- status = "okay"; +-}; +- +-&u2phy_host { +- status = "okay"; +-}; +- +-&u2phy_otg { +- status = "okay"; +-}; +- +-&usb20_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_dis &bt_wake_host &chip_en &host_wake_bt &wl_dis &wl_wake_host>; +- status = "okay"; +-}; +- +-&vop { +- status = "okay"; +-}; +- +-&vop_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3328-evb.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3328-evb.dts +deleted file mode 100644 +index ff6b466e0e07..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3328-evb.dts ++++ /dev/null +@@ -1,288 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd +- */ +- +-/dts-v1/; +-#include "rk3328.dtsi" +- +-/ { +- model = "Rockchip RK3328 EVB"; +- compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; +- +- aliases { +- mmc0 = &sdmmc; +- mmc1 = &sdio; +- mmc2 = &emmc; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- dc_12v: dc-12v { +- compatible = "regulator-fixed"; +- regulator-name = "dc_12v"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_enable_h>; +- +- /* +- * On the module itself this is one of these (depending +- * on the actual card populated): +- * - SDIO_RESET_L_WL_REG_ON +- * - PDN (power down when low) +- */ +- reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; +- }; +- +- vcc_sd: sdmmc-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc0m1_pin>; +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_sys: vcc-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&dc_12v>; +- }; +- +- vcc_phy: vcc-phy-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_phy"; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +- status = "okay"; +-}; +- +-&gmac2phy { +- phy-supply = <&vcc_phy>; +- clock_in_out = "output"; +- assigned-clock-rate = <50000000>; +- assigned-clocks = <&cru SCLK_MAC2PHY>; +- assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- +- rk805: pmic@18 { +- compatible = "rockchip,rk805"; +- reg = <0x18>; +- interrupt-parent = <&gpio2>; +- interrupts = <6 IRQ_TYPE_LEVEL_LOW>; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk805-clkout2"; +- gpio-controller; +- #gpio-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc5-supply = <&vcc_io>; +- vcc6-supply = <&vcc_io>; +- +- regulators { +- vdd_logic: DCDC_REG1 { +- regulator-name = "vdd_logic"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1450000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vdd_arm: DCDC_REG2 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1450000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <950000>; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_io: DCDC_REG4 { +- regulator-name = "vcc_io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_18: LDO_REG1 { +- regulator-name = "vcc_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc18_emmc: LDO_REG2 { +- regulator-name = "vcc18_emmc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vdd_10: LDO_REG3 { +- regulator-name = "vdd_10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- }; +- }; +-}; +- +-&pinctrl { +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- sdio-pwrseq { +- wifi_enable_h: wifi-enable-h { +- rockchip,pins = +- <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&sdio { +- bus-width = <4>; +- cap-sd-highspeed; +- cap-sdio-irq; +- keep-power-in-suspend; +- max-frequency = <150000000>; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- disable-wp; +- max-frequency = <150000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; +- vmmc-supply = <&vcc_sd>; +- status = "okay"; +-}; +- +-&tsadc { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&u2phy { +- status = "okay"; +-}; +- +-&u2phy_host { +- status = "okay"; +-}; +- +-&u2phy_otg { +- status = "okay"; +-}; +- +-&usb20_otg { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3328-nanopi-r2s.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3328-nanopi-r2s.dts +deleted file mode 100644 +index 3857d487ab84..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3328-nanopi-r2s.dts ++++ /dev/null +@@ -1,409 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 David Bauer +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include "rk3328.dtsi" +- +-/ { +- model = "FriendlyElec NanoPi R2S"; +- compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; +- +- aliases { +- ethernet1 = &rtl8153; +- mmc0 = &sdmmc; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- gmac_clk: gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "gmac_clkin"; +- #clock-cells = <0>; +- }; +- +- keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&reset_button_pin>; +- pinctrl-names = "default"; +- +- reset { +- label = "reset"; +- gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <50>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; +- pinctrl-names = "default"; +- +- lan_led: led-0 { +- gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; +- label = "nanopi-r2s:green:lan"; +- }; +- +- sys_led: led-1 { +- gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; +- label = "nanopi-r2s:red:sys"; +- default-state = "on"; +- }; +- +- wan_led: led-2 { +- gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; +- label = "nanopi-r2s:green:wan"; +- }; +- }; +- +- vcc_io_sdio: sdmmcio-regulator { +- compatible = "regulator-gpio"; +- enable-active-high; +- gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; +- pinctrl-0 = <&sdio_vcc_pin>; +- pinctrl-names = "default"; +- regulator-name = "vcc_io_sdio"; +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-settling-time-us = <5000>; +- regulator-type = "voltage"; +- startup-delay-us = <2000>; +- states = <1800000 0x1>, +- <3300000 0x0>; +- vin-supply = <&vcc_io_33>; +- }; +- +- vcc_sd: sdmmc-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; +- pinctrl-0 = <&sdmmc0m1_pin>; +- pinctrl-names = "default"; +- regulator-name = "vcc_sd"; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc_io_33>; +- }; +- +- vdd_5v: vdd-5v { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_5v"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- vdd_5v_lan: vdd-5v-lan { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; +- pinctrl-0 = <&lan_vdd_pin>; +- pinctrl-names = "default"; +- regulator-name = "vdd_5v_lan"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_5v>; +- }; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&display_subsystem { +- status = "disabled"; +-}; +- +-&gmac2io { +- assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; +- assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; +- clock_in_out = "input"; +- phy-handle = <&rtl8211e>; +- phy-mode = "rgmii"; +- phy-supply = <&vcc_io_33>; +- pinctrl-0 = <&rgmiim1_pins>; +- pinctrl-names = "default"; +- rx_delay = <0x18>; +- snps,aal; +- tx_delay = <0x24>; +- status = "okay"; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtl8211e: ethernet-phy@1 { +- reg = <1>; +- pinctrl-0 = <ð_phy_reset_pin>; +- pinctrl-names = "default"; +- reset-assert-us = <10000>; +- reset-deassert-us = <50000>; +- reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- rk805: pmic@18 { +- compatible = "rockchip,rk805"; +- reg = <0x18>; +- interrupt-parent = <&gpio1>; +- interrupts = <24 IRQ_TYPE_LEVEL_LOW>; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk805-clkout2"; +- gpio-controller; +- #gpio-cells = <2>; +- pinctrl-0 = <&pmic_int_l>; +- pinctrl-names = "default"; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vdd_5v>; +- vcc2-supply = <&vdd_5v>; +- vcc3-supply = <&vdd_5v>; +- vcc4-supply = <&vdd_5v>; +- vcc5-supply = <&vcc_io_33>; +- vcc6-supply = <&vdd_5v>; +- +- regulators { +- vdd_log: DCDC_REG1 { +- regulator-name = "vdd_log"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1450000>; +- regulator-ramp-delay = <12500>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vdd_arm: DCDC_REG2 { +- regulator-name = "vdd_arm"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1450000>; +- regulator-ramp-delay = <12500>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <950000>; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_io_33: DCDC_REG4 { +- regulator-name = "vcc_io_33"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_18: LDO_REG1 { +- regulator-name = "vcc_18"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc18_emmc: LDO_REG2 { +- regulator-name = "vcc18_emmc"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vdd_10: LDO_REG3 { +- regulator-name = "vdd_10"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- }; +- }; +-}; +- +-&io_domains { +- pmuio-supply = <&vcc_io_33>; +- vccio1-supply = <&vcc_io_33>; +- vccio2-supply = <&vcc18_emmc>; +- vccio3-supply = <&vcc_io_sdio>; +- vccio4-supply = <&vcc_18>; +- vccio5-supply = <&vcc_io_33>; +- vccio6-supply = <&vcc_io_33>; +- status = "okay"; +-}; +- +-&pinctrl { +- button { +- reset_button_pin: reset-button-pin { +- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- gmac2io { +- eth_phy_reset_pin: eth-phy-reset-pin { +- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- leds { +- lan_led_pin: lan-led-pin { +- rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- sys_led_pin: sys-led-pin { +- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- wan_led_pin: wan-led-pin { +- rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- lan { +- lan_vdd_pin: lan-vdd-pin { +- rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- sd { +- sdio_vcc_pin: sdio-vcc-pin { +- rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-sd-highspeed; +- disable-wp; +- pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; +- pinctrl-names = "default"; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- vmmc-supply = <&vcc_sd>; +- vqmmc-supply = <&vcc_io_sdio>; +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <0>; +- rockchip,hw-tshut-polarity = <0>; +- status = "okay"; +-}; +- +-&u2phy { +- status = "okay"; +-}; +- +-&u2phy_host { +- status = "okay"; +-}; +- +-&u2phy_otg { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb20_otg { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&usbdrd3 { +- dr_mode = "host"; +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* Second port is for USB 3.0 */ +- rtl8153: device@2 { +- compatible = "usbbda,8153"; +- reg = <2>; +- }; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3328-roc-cc.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3328-roc-cc.dts +deleted file mode 100644 +index aa22a0c22265..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3328-roc-cc.dts ++++ /dev/null +@@ -1,385 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd +- */ +- +-/dts-v1/; +-#include "rk3328.dtsi" +- +-/ { +- model = "Firefly roc-rk3328-cc"; +- compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; +- +- aliases { +- mmc0 = &sdmmc; +- mmc1 = &emmc; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- gmac_clkin: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "gmac_clkin"; +- #clock-cells = <0>; +- }; +- +- dc_12v: dc-12v { +- compatible = "regulator-fixed"; +- regulator-name = "dc_12v"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- vcc_sd: sdmmc-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc0m1_pin>; +- regulator-boot-on; +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_sdio: sdmmcio-regulator { +- compatible = "regulator-gpio"; +- gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>; +- states = <1800000 0x1>, +- <3300000 0x0>; +- regulator-name = "vcc_sdio"; +- regulator-type = "voltage"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb20_host_drv>; +- regulator-name = "vcc_host1_5v"; +- regulator-always-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_sys: vcc-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&dc_12v>; +- }; +- +- vcc_phy: vcc-phy-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_phy"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- power_led: led-0 { +- label = "firefly:blue:power"; +- linux,default-trigger = "heartbeat"; +- gpios = <&rk805 1 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- mode = <0x23>; +- }; +- +- user_led: led-1 { +- label = "firefly:yellow:user"; +- linux,default-trigger = "mmc1"; +- gpios = <&rk805 0 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- mode = <0x05>; +- }; +- }; +-}; +- +-&analog_sound { +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- max-frequency = <150000000>; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +- vmmc-supply = <&vcc_io>; +- vqmmc-supply = <&vcc18_emmc>; +- status = "okay"; +-}; +- +-&gmac2io { +- assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; +- assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; +- clock_in_out = "input"; +- phy-supply = <&vcc_phy>; +- phy-mode = "rgmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmiim1_pins>; +- snps,aal; +- snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 50000>; +- snps,rxpbl = <0x4>; +- snps,txpbl = <0x4>; +- tx_delay = <0x24>; +- rx_delay = <0x18>; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmiphy { +- status = "okay"; +-}; +- +-&hdmi_sound { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- +- rk805: pmic@18 { +- compatible = "rockchip,rk805"; +- reg = <0x18>; +- interrupt-parent = <&gpio1>; +- interrupts = <24 IRQ_TYPE_LEVEL_LOW>; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk805-clkout2"; +- gpio-controller; +- #gpio-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc5-supply = <&vcc_io>; +- vcc6-supply = <&vcc_io>; +- +- regulators { +- vdd_logic: DCDC_REG1 { +- regulator-name = "vdd_logic"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1450000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vdd_arm: DCDC_REG2 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1450000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <950000>; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_io: DCDC_REG4 { +- regulator-name = "vcc_io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_18: LDO_REG1 { +- regulator-name = "vcc_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc18_emmc: LDO_REG2 { +- regulator-name = "vcc18_emmc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vdd_10: LDO_REG3 { +- regulator-name = "vdd_10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- }; +- }; +-}; +- +-&i2s0 { +- status = "okay"; +-}; +- +-&i2s1 { +- status = "okay"; +-}; +- +-&io_domains { +- status = "okay"; +- +- vccio1-supply = <&vcc_io>; +- vccio2-supply = <&vcc18_emmc>; +- vccio3-supply = <&vcc_sdio>; +- vccio4-supply = <&vcc_18>; +- vccio5-supply = <&vcc_io>; +- vccio6-supply = <&vcc_io>; +- pmuio-supply = <&vcc_io>; +-}; +- +-&pinctrl { +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- usb2 { +- usb20_host_drv: usb20-host-drv { +- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- disable-wp; +- max-frequency = <150000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- vmmc-supply = <&vcc_sd>; +- vqmmc-supply = <&vcc_sdio>; +- status = "okay"; +-}; +- +-&tsadc { +- status = "okay"; +-}; +- +-&u2phy { +- status = "okay"; +-}; +- +-&u2phy_host { +- status = "okay"; +-}; +- +-&u2phy_otg { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb20_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbdrd3 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&vop { +- status = "okay"; +-}; +- +-&vop_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3328-rock-pi-e.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3328-rock-pi-e.dts +deleted file mode 100644 +index 018a3a5075c7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3328-rock-pi-e.dts ++++ /dev/null +@@ -1,390 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * (C) Copyright 2020 Chen-Yu Tsai +- * +- * Based on ./rk3328-rock64.dts, which is +- * +- * Copyright (c) 2017 PINE64 +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include +- +-#include "rk3328.dtsi" +- +-/ { +- model = "Radxa ROCK Pi E"; +- compatible = "radxa,rockpi-e", "rockchip,rk3328"; +- +- aliases { +- mmc0 = &sdmmc; +- mmc1 = &emmc; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 0>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1750000>; +- +- /* This button is unpopulated out of the factory. */ +- button-recovery { +- label = "Recovery"; +- linux,code = ; +- press-threshold-microvolt = <10000>; +- }; +- }; +- +- gmac_clkin: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "gmac_clkin"; +- #clock-cells = <0>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-0 = <&led_pin>; +- pinctrl-names = "default"; +- +- led-0 { +- color = ; +- gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- vcc_sd: sdmmc-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc0m1_pin>; +- regulator-name = "vcc_sd"; +- regulator-boot-on; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_host_5v: vcc-host-5v-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb30_host_drv>; +- enable-active-high; +- regulator-name = "vcc_host_5v"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_sys: vcc-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- vcc_wifi: vcc-wifi-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_en>; +- regulator-name = "vcc_wifi"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_io>; +- }; +-}; +- +-&analog_sound { +- status = "okay"; +-}; +- +-&codec { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; +- vmmc-supply = <&vcc_io>; +- vqmmc-supply = <&vcc18_emmc>; +- status = "okay"; +-}; +- +-&gmac2io { +- assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; +- assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; +- clock_in_out = "input"; +- phy-handle = <&rtl8211e>; +- phy-mode = "rgmii"; +- phy-supply = <&vcc_io>; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmiim1_pins>; +- snps,aal; +- snps,rxpbl = <0x4>; +- snps,txpbl = <0x4>; +- tx_delay = <0x26>; +- rx_delay = <0x11>; +- status = "okay"; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtl8211e: ethernet-phy@1 { +- reg = <1>; +- pinctrl-0 = <ð_phy_int_pin>, <ð_phy_reset_pin>; +- pinctrl-names = "default"; +- interrupt-parent = <&gpio1>; +- interrupts = <24 IRQ_TYPE_LEVEL_LOW>; +- reset-assert-us = <10000>; +- reset-deassert-us = <50000>; +- reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&gmac2phy { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- +- rk805: pmic@18 { +- compatible = "rockchip,rk805"; +- reg = <0x18>; +- interrupt-parent = <&gpio2>; +- interrupts = <6 IRQ_TYPE_LEVEL_LOW>; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk805-clkout2"; +- gpio-controller; +- #gpio-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc5-supply = <&vcc_io>; +- vcc6-supply = <&vcc_sys>; +- +- regulators { +- vdd_log: DCDC_REG1 { +- regulator-name = "vdd_log"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1450000>; +- regulator-ramp-delay = <12500>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vdd_arm: DCDC_REG2 { +- regulator-name = "vdd_arm"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1450000>; +- regulator-ramp-delay = <12500>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <950000>; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_io: DCDC_REG4 { +- regulator-name = "vcc_io"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_18: LDO_REG1 { +- regulator-name = "vcc_18"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc18_emmc: LDO_REG2 { +- regulator-name = "vcc18_emmc"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vdd_10: LDO_REG3 { +- regulator-name = "vdd_10"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- }; +- }; +-}; +- +-&i2s1 { +- status = "okay"; +-}; +- +-&io_domains { +- pmuio-supply = <&vcc_io>; +- vccio1-supply = <&vcc_io>; +- vccio2-supply = <&vcc18_emmc>; +- vccio3-supply = <&vcc_io>; +- vccio4-supply = <&vcc_io>; +- vccio5-supply = <&vcc_io>; +- vccio6-supply = <&vcc_io>; +- status = "okay"; +-}; +- +-&pinctrl { +- ephy { +- eth_phy_int_pin: eth-phy-int-pin { +- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- eth_phy_reset_pin: eth-phy-reset-pin { +- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- leds { +- led_pin: led-pin { +- rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- usb3 { +- usb30_host_drv: usb30-host-drv { +- rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- wifi { +- wifi_en: wifi-en { +- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-sd-highspeed; +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; +- vmmc-supply = <&vcc_sd>; +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vcc_18>; +- status = "okay"; +-}; +- +-&tsadc { +- status = "okay"; +-}; +- +-&u2phy { +- status = "okay"; +-}; +- +-&u2phy_host { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usbdrd3 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3328-rock64.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3328-rock64.dts +deleted file mode 100644 +index 1b0f7e4551ea..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3328-rock64.dts ++++ /dev/null +@@ -1,403 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 PINE64 +- */ +- +-/dts-v1/; +-#include "rk3328.dtsi" +- +-/ { +- model = "Pine64 Rock64"; +- compatible = "pine64,rock64", "rockchip,rk3328"; +- +- aliases { +- mmc0 = &sdmmc; +- mmc1 = &emmc; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- gmac_clkin: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "gmac_clkin"; +- #clock-cells = <0>; +- }; +- +- vcc_sd: sdmmc-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc0m1_pin>; +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_host_5v: vcc-host-5v-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb20_host_drv>; +- regulator-name = "vcc_host_5v"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb20_host_drv>; +- regulator-name = "vcc_host1_5v"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_sys: vcc-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; +- pinctrl-0 = <&ir_int>; +- pinctrl-names = "default"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- power_led: led-0 { +- gpios = <&rk805 1 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "mmc0"; +- }; +- +- standby_led: led-1 { +- gpios = <&rk805 0 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- spdif_sound: spdif-sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "SPDIF"; +- +- simple-audio-card,cpu { +- sound-dai = <&spdif>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&spdif_dit>; +- }; +- }; +- +- spdif_dit: spdif-dit { +- compatible = "linux,spdif-dit"; +- #sound-dai-cells = <0>; +- }; +-}; +- +-&analog_sound { +- status = "okay"; +-}; +- +-&codec { +- mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_arm>; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +- vmmc-supply = <&vcc_io>; +- vqmmc-supply = <&vcc18_emmc>; +- status = "okay"; +-}; +- +-&gmac2io { +- assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; +- assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; +- clock_in_out = "input"; +- phy-supply = <&vcc_io>; +- phy-mode = "rgmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmiim1_pins>; +- snps,force_thresh_dma_mode; +- snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 50000>; +- tx_delay = <0x24>; +- rx_delay = <0x18>; +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_sound { +- status = "okay"; +-}; +- +-&hdmiphy { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- +- rk805: pmic@18 { +- compatible = "rockchip,rk805"; +- reg = <0x18>; +- interrupt-parent = <&gpio2>; +- interrupts = <6 IRQ_TYPE_LEVEL_LOW>; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk805-clkout2"; +- gpio-controller; +- #gpio-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc5-supply = <&vcc_io>; +- vcc6-supply = <&vcc_sys>; +- +- regulators { +- vdd_logic: DCDC_REG1 { +- regulator-name = "vdd_logic"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1450000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- +- vdd_arm: DCDC_REG2 { +- regulator-name = "vdd_arm"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1450000>; +- regulator-ramp-delay = <12500>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <950000>; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_io: DCDC_REG4 { +- regulator-name = "vcc_io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_18: LDO_REG1 { +- regulator-name = "vcc_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc18_emmc: LDO_REG2 { +- regulator-name = "vcc18_emmc"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vdd_10: LDO_REG3 { +- regulator-name = "vdd_10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; +- }; +- }; +- }; +- }; +-}; +- +-&i2s0 { +- status = "okay"; +-}; +- +-&i2s1 { +- status = "okay"; +-}; +- +-&io_domains { +- status = "okay"; +- +- vccio1-supply = <&vcc_io>; +- vccio2-supply = <&vcc18_emmc>; +- vccio3-supply = <&vcc_io>; +- vccio4-supply = <&vcc_18>; +- vccio5-supply = <&vcc_io>; +- vccio6-supply = <&vcc_io>; +- pmuio-supply = <&vcc_io>; +-}; +- +-&pinctrl { +- ir { +- ir_int: ir-int { +- rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- usb2 { +- usb20_host_drv: usb20-host-drv { +- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- disable-wp; +- max-frequency = <150000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; +- vmmc-supply = <&vcc_sd>; +- status = "okay"; +-}; +- +-&spdif { +- pinctrl-0 = <&spdifm0_tx>; +- status = "okay"; +-}; +- +-&spi0 { +- status = "okay"; +- +- spiflash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- +- /* maximum speed for Rockchip SPI */ +- spi-max-frequency = <50000000>; +- }; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <0>; +- rockchip,hw-tshut-polarity = <0>; +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&u2phy { +- status = "okay"; +- +- u2phy_host: host-port { +- status = "okay"; +- }; +- +- u2phy_otg: otg-port { +- status = "okay"; +- }; +-}; +- +-&usb20_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbdrd3 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&vop { +- status = "okay"; +-}; +- +-&vop_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3328.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3328.dtsi +deleted file mode 100644 +index 3cbe83e6fb9a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3328.dtsi ++++ /dev/null +@@ -1,1912 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "rockchip,rk3328"; +- +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- ethernet0 = &gmac2io; +- ethernet1 = &gmac2phy; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- clocks = <&cru ARMCLK>; +- #cooling-cells = <2>; +- cpu-idle-states = <&CPU_SLEEP>; +- dynamic-power-coefficient = <120>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- clocks = <&cru ARMCLK>; +- #cooling-cells = <2>; +- cpu-idle-states = <&CPU_SLEEP>; +- dynamic-power-coefficient = <120>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x2>; +- clocks = <&cru ARMCLK>; +- #cooling-cells = <2>; +- cpu-idle-states = <&CPU_SLEEP>; +- dynamic-power-coefficient = <120>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x3>; +- clocks = <&cru ARMCLK>; +- #cooling-cells = <2>; +- cpu-idle-states = <&CPU_SLEEP>; +- dynamic-power-coefficient = <120>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP: cpu-sleep { +- compatible = "arm,idle-state"; +- local-timer-stop; +- arm,psci-suspend-param = <0x0010000>; +- entry-latency-us = <120>; +- exit-latency-us = <250>; +- min-residency-us = <900>; +- }; +- }; +- +- l2: l2-cache0 { +- compatible = "cache"; +- }; +- }; +- +- cpu0_opp_table: opp_table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-408000000 { +- opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <950000>; +- clock-latency-ns = <40000>; +- opp-suspend; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <950000>; +- clock-latency-ns = <40000>; +- }; +- opp-816000000 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <1000000>; +- clock-latency-ns = <40000>; +- }; +- opp-1008000000 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <1100000>; +- clock-latency-ns = <40000>; +- }; +- opp-1200000000 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <1225000>; +- clock-latency-ns = <40000>; +- }; +- opp-1296000000 { +- opp-hz = /bits/ 64 <1296000000>; +- opp-microvolt = <1300000>; +- clock-latency-ns = <40000>; +- }; +- }; +- +- analog_sound: analog-sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,mclk-fs = <256>; +- simple-audio-card,name = "Analog"; +- status = "disabled"; +- +- simple-audio-card,cpu { +- sound-dai = <&i2s1>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&codec>; +- }; +- }; +- +- arm-pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- display_subsystem: display-subsystem { +- compatible = "rockchip,display-subsystem"; +- ports = <&vop_out>; +- }; +- +- hdmi_sound: hdmi-sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,mclk-fs = <128>; +- simple-audio-card,name = "HDMI"; +- status = "disabled"; +- +- simple-audio-card,cpu { +- sound-dai = <&i2s0>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&hdmi>; +- }; +- }; +- +- psci { +- compatible = "arm,psci-1.0", "arm,psci-0.2"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- xin24m: xin24m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; +- clock-output-names = "xin24m"; +- }; +- +- i2s0: i2s@ff000000 { +- compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; +- reg = <0x0 0xff000000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; +- clock-names = "i2s_clk", "i2s_hclk"; +- dmas = <&dmac 11>, <&dmac 12>; +- dma-names = "tx", "rx"; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- i2s1: i2s@ff010000 { +- compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; +- reg = <0x0 0xff010000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; +- clock-names = "i2s_clk", "i2s_hclk"; +- dmas = <&dmac 14>, <&dmac 15>; +- dma-names = "tx", "rx"; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- i2s2: i2s@ff020000 { +- compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; +- reg = <0x0 0xff020000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; +- clock-names = "i2s_clk", "i2s_hclk"; +- dmas = <&dmac 0>, <&dmac 1>; +- dma-names = "tx", "rx"; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- spdif: spdif@ff030000 { +- compatible = "rockchip,rk3328-spdif"; +- reg = <0x0 0xff030000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; +- clock-names = "mclk", "hclk"; +- dmas = <&dmac 10>; +- dma-names = "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spdifm2_tx>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- pdm: pdm@ff040000 { +- compatible = "rockchip,pdm"; +- reg = <0x0 0xff040000 0x0 0x1000>; +- clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; +- clock-names = "pdm_clk", "pdm_hclk"; +- dmas = <&dmac 16>; +- dma-names = "rx"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&pdmm0_clk +- &pdmm0_sdi0 +- &pdmm0_sdi1 +- &pdmm0_sdi2 +- &pdmm0_sdi3>; +- pinctrl-1 = <&pdmm0_clk_sleep +- &pdmm0_sdi0_sleep +- &pdmm0_sdi1_sleep +- &pdmm0_sdi2_sleep +- &pdmm0_sdi3_sleep>; +- status = "disabled"; +- }; +- +- grf: syscon@ff100000 { +- compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; +- reg = <0x0 0xff100000 0x0 0x1000>; +- +- io_domains: io-domains { +- compatible = "rockchip,rk3328-io-voltage-domain"; +- status = "disabled"; +- }; +- +- grf_gpio: gpio { +- compatible = "rockchip,rk3328-grf-gpio"; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- power: power-controller { +- compatible = "rockchip,rk3328-power-controller"; +- #power-domain-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- power-domain@RK3328_PD_HEVC { +- reg = ; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3328_PD_VIDEO { +- reg = ; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3328_PD_VPU { +- reg = ; +- clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; +- #power-domain-cells = <0>; +- }; +- }; +- +- reboot-mode { +- compatible = "syscon-reboot-mode"; +- offset = <0x5c8>; +- mode-normal = ; +- mode-recovery = ; +- mode-bootloader = ; +- mode-loader = ; +- }; +- }; +- +- uart0: serial@ff110000 { +- compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff110000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac 2>, <&dmac 3>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart1: serial@ff120000 { +- compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff120000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac 4>, <&dmac 5>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart2: serial@ff130000 { +- compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff130000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac 6>, <&dmac 7>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2m1_xfer>; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- i2c0: i2c@ff150000 { +- compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xff150000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; +- clock-names = "i2c", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_xfer>; +- status = "disabled"; +- }; +- +- i2c1: i2c@ff160000 { +- compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xff160000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; +- clock-names = "i2c", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_xfer>; +- status = "disabled"; +- }; +- +- i2c2: i2c@ff170000 { +- compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xff170000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; +- clock-names = "i2c", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_xfer>; +- status = "disabled"; +- }; +- +- i2c3: i2c@ff180000 { +- compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xff180000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; +- clock-names = "i2c", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_xfer>; +- status = "disabled"; +- }; +- +- spi0: spi@ff190000 { +- compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xff190000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; +- clock-names = "spiclk", "apb_pclk"; +- dmas = <&dmac 8>, <&dmac 9>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; +- status = "disabled"; +- }; +- +- wdt: watchdog@ff1a0000 { +- compatible = "rockchip,rk3328-wdt", "snps,dw-wdt"; +- reg = <0x0 0xff1a0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_WDT>; +- }; +- +- pwm0: pwm@ff1b0000 { +- compatible = "rockchip,rk3328-pwm"; +- reg = <0x0 0xff1b0000 0x0 0x10>; +- clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm1: pwm@ff1b0010 { +- compatible = "rockchip,rk3328-pwm"; +- reg = <0x0 0xff1b0010 0x0 0x10>; +- clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm1_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm2: pwm@ff1b0020 { +- compatible = "rockchip,rk3328-pwm"; +- reg = <0x0 0xff1b0020 0x0 0x10>; +- clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm2_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm3: pwm@ff1b0030 { +- compatible = "rockchip,rk3328-pwm"; +- reg = <0x0 0xff1b0030 0x0 0x10>; +- interrupts = ; +- clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; +- clock-names = "pwm", "pclk"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwmir_pin>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- dmac: dma-controller@ff1f0000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xff1f0000 0x0 0x4000>; +- interrupts = , +- ; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMAC>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- }; +- +- thermal-zones { +- soc_thermal: soc-thermal { +- polling-delay-passive = <20>; +- polling-delay = <1000>; +- sustainable-power = <1000>; +- +- thermal-sensors = <&tsadc 0>; +- +- trips { +- threshold: trip-point0 { +- temperature = <70000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- target: trip-point1 { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- soc_crit: soc-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&target>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- contribution = <4096>; +- }; +- }; +- }; +- +- }; +- +- tsadc: tsadc@ff250000 { +- compatible = "rockchip,rk3328-tsadc"; +- reg = <0x0 0xff250000 0x0 0x100>; +- interrupts = ; +- assigned-clocks = <&cru SCLK_TSADC>; +- assigned-clock-rates = <50000>; +- clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; +- clock-names = "tsadc", "apb_pclk"; +- pinctrl-names = "init", "default", "sleep"; +- pinctrl-0 = <&otp_pin>; +- pinctrl-1 = <&otp_out>; +- pinctrl-2 = <&otp_pin>; +- resets = <&cru SRST_TSADC>; +- reset-names = "tsadc-apb"; +- rockchip,grf = <&grf>; +- rockchip,hw-tshut-temp = <100000>; +- #thermal-sensor-cells = <1>; +- status = "disabled"; +- }; +- +- efuse: efuse@ff260000 { +- compatible = "rockchip,rk3328-efuse"; +- reg = <0x0 0xff260000 0x0 0x50>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&cru SCLK_EFUSE>; +- clock-names = "pclk_efuse"; +- rockchip,efuse-size = <0x20>; +- +- /* Data cells */ +- efuse_id: id@7 { +- reg = <0x07 0x10>; +- }; +- cpu_leakage: cpu-leakage@17 { +- reg = <0x17 0x1>; +- }; +- logic_leakage: logic-leakage@19 { +- reg = <0x19 0x1>; +- }; +- efuse_cpu_version: cpu-version@1a { +- reg = <0x1a 0x1>; +- bits = <3 3>; +- }; +- }; +- +- saradc: adc@ff280000 { +- compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; +- reg = <0x0 0xff280000 0x0 0x100>; +- interrupts = ; +- #io-channel-cells = <1>; +- clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; +- clock-names = "saradc", "apb_pclk"; +- resets = <&cru SRST_SARADC_P>; +- reset-names = "saradc-apb"; +- status = "disabled"; +- }; +- +- gpu: gpu@ff300000 { +- compatible = "rockchip,rk3328-mali", "arm,mali-450"; +- reg = <0x0 0xff300000 0x0 0x30000>; +- interrupts = , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "gp", +- "gpmmu", +- "pp", +- "pp0", +- "ppmmu0", +- "pp1", +- "ppmmu1"; +- clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; +- clock-names = "bus", "core"; +- resets = <&cru SRST_GPU_A>; +- }; +- +- h265e_mmu: iommu@ff330200 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff330200 0 0x100>; +- interrupts = ; +- interrupt-names = "h265e_mmu"; +- clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- vepu_mmu: iommu@ff340800 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff340800 0x0 0x40>; +- interrupts = ; +- interrupt-names = "vepu_mmu"; +- clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- vpu: video-codec@ff350000 { +- compatible = "rockchip,rk3328-vpu"; +- reg = <0x0 0xff350000 0x0 0x800>; +- interrupts = ; +- interrupt-names = "vdpu"; +- clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; +- clock-names = "aclk", "hclk"; +- iommus = <&vpu_mmu>; +- power-domains = <&power RK3328_PD_VPU>; +- }; +- +- vpu_mmu: iommu@ff350800 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff350800 0x0 0x40>; +- interrupts = ; +- interrupt-names = "vpu_mmu"; +- clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- power-domains = <&power RK3328_PD_VPU>; +- }; +- +- rkvdec_mmu: iommu@ff360480 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; +- interrupts = ; +- interrupt-names = "rkvdec_mmu"; +- clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- vop: vop@ff370000 { +- compatible = "rockchip,rk3328-vop"; +- reg = <0x0 0xff370000 0x0 0x3efc>; +- interrupts = ; +- clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; +- clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; +- resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; +- reset-names = "axi", "ahb", "dclk"; +- iommus = <&vop_mmu>; +- status = "disabled"; +- +- vop_out: port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- vop_out_hdmi: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&hdmi_in_vop>; +- }; +- }; +- }; +- +- vop_mmu: iommu@ff373f00 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff373f00 0x0 0x100>; +- interrupts = ; +- interrupt-names = "vop_mmu"; +- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- hdmi: hdmi@ff3c0000 { +- compatible = "rockchip,rk3328-dw-hdmi"; +- reg = <0x0 0xff3c0000 0x0 0x20000>; +- reg-io-width = <4>; +- interrupts = , +- ; +- clocks = <&cru PCLK_HDMI>, +- <&cru SCLK_HDMI_SFC>, +- <&cru SCLK_RTC32K>; +- clock-names = "iahb", +- "isfr", +- "cec"; +- phys = <&hdmiphy>; +- phy-names = "hdmi"; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; +- rockchip,grf = <&grf>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- +- ports { +- hdmi_in: port { +- hdmi_in_vop: endpoint { +- remote-endpoint = <&vop_out_hdmi>; +- }; +- }; +- }; +- }; +- +- codec: codec@ff410000 { +- compatible = "rockchip,rk3328-codec"; +- reg = <0x0 0xff410000 0x0 0x1000>; +- clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; +- clock-names = "pclk", "mclk"; +- rockchip,grf = <&grf>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- hdmiphy: phy@ff430000 { +- compatible = "rockchip,rk3328-hdmi-phy"; +- reg = <0x0 0xff430000 0x0 0x10000>; +- interrupts = ; +- clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; +- clock-names = "sysclk", "refoclk", "refpclk"; +- clock-output-names = "hdmi_phy"; +- #clock-cells = <0>; +- nvmem-cells = <&efuse_cpu_version>; +- nvmem-cell-names = "cpu-version"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- cru: clock-controller@ff440000 { +- compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; +- reg = <0x0 0xff440000 0x0 0x1000>; +- rockchip,grf = <&grf>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- assigned-clocks = +- /* +- * CPLL should run at 1200, but that is to high for +- * the initial dividers of most of its children. +- * We need set cpll child clk div first, +- * and then set the cpll frequency. +- */ +- <&cru DCLK_LCDC>, <&cru SCLK_PDM>, +- <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, +- <&cru SCLK_UART1>, <&cru SCLK_UART2>, +- <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, +- <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, +- <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, +- <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, +- <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, +- <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, +- <&cru SCLK_SDIO>, <&cru SCLK_TSP>, +- <&cru SCLK_WIFI>, <&cru ARMCLK>, +- <&cru PLL_GPLL>, <&cru PLL_CPLL>, +- <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, +- <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, +- <&cru HCLK_PERI>, <&cru PCLK_PERI>, +- <&cru SCLK_RTC32K>; +- assigned-clock-parents = +- <&cru HDMIPHY>, <&cru PLL_APLL>, +- <&cru PLL_GPLL>, <&xin24m>, +- <&xin24m>, <&xin24m>; +- assigned-clock-rates = +- <0>, <61440000>, +- <0>, <24000000>, +- <24000000>, <24000000>, +- <15000000>, <15000000>, +- <100000000>, <100000000>, +- <100000000>, <100000000>, +- <50000000>, <100000000>, +- <100000000>, <100000000>, +- <50000000>, <50000000>, +- <50000000>, <50000000>, +- <24000000>, <600000000>, +- <491520000>, <1200000000>, +- <150000000>, <75000000>, +- <75000000>, <150000000>, +- <75000000>, <75000000>, +- <32768>; +- }; +- +- usb2phy_grf: syscon@ff450000 { +- compatible = "rockchip,rk3328-usb2phy-grf", "syscon", +- "simple-mfd"; +- reg = <0x0 0xff450000 0x0 0x10000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- u2phy: usb2phy@100 { +- compatible = "rockchip,rk3328-usb2phy"; +- reg = <0x100 0x10>; +- clocks = <&xin24m>; +- clock-names = "phyclk"; +- clock-output-names = "usb480m_phy"; +- #clock-cells = <0>; +- assigned-clocks = <&cru USB480M>; +- assigned-clock-parents = <&u2phy>; +- status = "disabled"; +- +- u2phy_otg: otg-port { +- #phy-cells = <0>; +- interrupts = , +- , +- ; +- interrupt-names = "otg-bvalid", "otg-id", +- "linestate"; +- status = "disabled"; +- }; +- +- u2phy_host: host-port { +- #phy-cells = <0>; +- interrupts = ; +- interrupt-names = "linestate"; +- status = "disabled"; +- }; +- }; +- }; +- +- sdmmc: mmc@ff500000 { +- compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xff500000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, +- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- max-frequency = <150000000>; +- status = "disabled"; +- }; +- +- sdio: mmc@ff510000 { +- compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xff510000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, +- <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- max-frequency = <150000000>; +- status = "disabled"; +- }; +- +- emmc: mmc@ff520000 { +- compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xff520000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, +- <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- max-frequency = <150000000>; +- status = "disabled"; +- }; +- +- gmac2io: ethernet@ff540000 { +- compatible = "rockchip,rk3328-gmac"; +- reg = <0x0 0xff540000 0x0 0x10000>; +- interrupts = ; +- interrupt-names = "macirq"; +- clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, +- <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, +- <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, +- <&cru PCLK_MAC2IO>; +- clock-names = "stmmaceth", "mac_clk_rx", +- "mac_clk_tx", "clk_mac_ref", +- "clk_mac_refout", "aclk_mac", +- "pclk_mac"; +- resets = <&cru SRST_GMAC2IO_A>; +- reset-names = "stmmaceth"; +- rockchip,grf = <&grf>; +- snps,txpbl = <0x4>; +- status = "disabled"; +- }; +- +- gmac2phy: ethernet@ff550000 { +- compatible = "rockchip,rk3328-gmac"; +- reg = <0x0 0xff550000 0x0 0x10000>; +- rockchip,grf = <&grf>; +- interrupts = ; +- interrupt-names = "macirq"; +- clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, +- <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, +- <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, +- <&cru SCLK_MAC2PHY_OUT>; +- clock-names = "stmmaceth", "mac_clk_rx", +- "mac_clk_tx", "clk_mac_ref", +- "aclk_mac", "pclk_mac", +- "clk_macphy"; +- resets = <&cru SRST_GMAC2PHY_A>; +- reset-names = "stmmaceth"; +- phy-mode = "rmii"; +- phy-handle = <&phy>; +- snps,txpbl = <0x4>; +- clock_in_out = "output"; +- status = "disabled"; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy: ethernet-phy@0 { +- compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- clocks = <&cru SCLK_MAC2PHY_OUT>; +- resets = <&cru SRST_MACPHY>; +- pinctrl-names = "default"; +- pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; +- phy-is-integrated; +- }; +- }; +- }; +- +- usb20_otg: usb@ff580000 { +- compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", +- "snps,dwc2"; +- reg = <0x0 0xff580000 0x0 0x40000>; +- interrupts = ; +- clocks = <&cru HCLK_OTG>; +- clock-names = "otg"; +- dr_mode = "otg"; +- g-np-tx-fifo-size = <16>; +- g-rx-fifo-size = <280>; +- g-tx-fifo-size = <256 128 128 64 32 16>; +- phys = <&u2phy_otg>; +- phy-names = "usb2-phy"; +- status = "disabled"; +- }; +- +- usb_host0_ehci: usb@ff5c0000 { +- compatible = "generic-ehci"; +- reg = <0x0 0xff5c0000 0x0 0x10000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST0>, <&u2phy>; +- phys = <&u2phy_host>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usb_host0_ohci: usb@ff5d0000 { +- compatible = "generic-ohci"; +- reg = <0x0 0xff5d0000 0x0 0x10000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST0>, <&u2phy>; +- phys = <&u2phy_host>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usbdrd3: usb@ff600000 { +- compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; +- reg = <0x0 0xff600000 0x0 0x100000>; +- interrupts = ; +- clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, +- <&cru ACLK_USB3OTG>; +- clock-names = "ref_clk", "suspend_clk", +- "bus_clk"; +- dr_mode = "otg"; +- phy_type = "utmi_wide"; +- snps,dis-del-phy-power-chg-quirk; +- snps,dis_enblslpm_quirk; +- snps,dis-tx-ipgap-linecheck-quirk; +- snps,dis-u2-freeclk-exists-quirk; +- snps,dis_u2_susphy_quirk; +- snps,dis_u3_susphy_quirk; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@ff811000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x0 0xff811000 0 0x1000>, +- <0x0 0xff812000 0 0x2000>, +- <0x0 0xff814000 0 0x2000>, +- <0x0 0xff816000 0 0x2000>; +- interrupts = ; +- }; +- +- pinctrl: pinctrl { +- compatible = "rockchip,rk3328-pinctrl"; +- rockchip,grf = <&grf>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gpio0: gpio0@ff210000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff210000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio1@ff220000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff220000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO1>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio2@ff230000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff230000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO2>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio3@ff240000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff240000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO3>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pcfg_pull_up: pcfg-pull-up { +- bias-pull-up; +- }; +- +- pcfg_pull_down: pcfg-pull-down { +- bias-pull-down; +- }; +- +- pcfg_pull_none: pcfg-pull-none { +- bias-disable; +- }; +- +- pcfg_pull_none_2ma: pcfg-pull-none-2ma { +- bias-disable; +- drive-strength = <2>; +- }; +- +- pcfg_pull_up_2ma: pcfg-pull-up-2ma { +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- pcfg_pull_up_4ma: pcfg-pull-up-4ma { +- bias-pull-up; +- drive-strength = <4>; +- }; +- +- pcfg_pull_none_4ma: pcfg-pull-none-4ma { +- bias-disable; +- drive-strength = <4>; +- }; +- +- pcfg_pull_down_4ma: pcfg-pull-down-4ma { +- bias-pull-down; +- drive-strength = <4>; +- }; +- +- pcfg_pull_none_8ma: pcfg-pull-none-8ma { +- bias-disable; +- drive-strength = <8>; +- }; +- +- pcfg_pull_up_8ma: pcfg-pull-up-8ma { +- bias-pull-up; +- drive-strength = <8>; +- }; +- +- pcfg_pull_none_12ma: pcfg-pull-none-12ma { +- bias-disable; +- drive-strength = <12>; +- }; +- +- pcfg_pull_up_12ma: pcfg-pull-up-12ma { +- bias-pull-up; +- drive-strength = <12>; +- }; +- +- pcfg_output_high: pcfg-output-high { +- output-high; +- }; +- +- pcfg_output_low: pcfg-output-low { +- output-low; +- }; +- +- pcfg_input_high: pcfg-input-high { +- bias-pull-up; +- input-enable; +- }; +- +- pcfg_input: pcfg-input { +- input-enable; +- }; +- +- i2c0 { +- i2c0_xfer: i2c0-xfer { +- rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, +- <2 RK_PD1 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c1 { +- i2c1_xfer: i2c1-xfer { +- rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, +- <2 RK_PA5 2 &pcfg_pull_none>; +- }; +- }; +- +- i2c2 { +- i2c2_xfer: i2c2-xfer { +- rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, +- <2 RK_PB6 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c3 { +- i2c3_xfer: i2c3-xfer { +- rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, +- <0 RK_PA6 2 &pcfg_pull_none>; +- }; +- i2c3_pins: i2c3-pins { +- rockchip,pins = +- <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, +- <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- hdmi_i2c { +- hdmii2c_xfer: hdmii2c-xfer { +- rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, +- <0 RK_PA6 1 &pcfg_pull_none>; +- }; +- }; +- +- pdm-0 { +- pdmm0_clk: pdmm0-clk { +- rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; +- }; +- +- pdmm0_fsync: pdmm0-fsync { +- rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; +- }; +- +- pdmm0_sdi0: pdmm0-sdi0 { +- rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; +- }; +- +- pdmm0_sdi1: pdmm0-sdi1 { +- rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; +- }; +- +- pdmm0_sdi2: pdmm0-sdi2 { +- rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; +- }; +- +- pdmm0_sdi3: pdmm0-sdi3 { +- rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; +- }; +- +- pdmm0_clk_sleep: pdmm0-clk-sleep { +- rockchip,pins = +- <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; +- }; +- +- pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { +- rockchip,pins = +- <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; +- }; +- +- pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { +- rockchip,pins = +- <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; +- }; +- +- pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { +- rockchip,pins = +- <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; +- }; +- +- pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { +- rockchip,pins = +- <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; +- }; +- +- pdmm0_fsync_sleep: pdmm0-fsync-sleep { +- rockchip,pins = +- <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; +- }; +- }; +- +- tsadc { +- otp_pin: otp-pin { +- rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- otp_out: otp-out { +- rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; +- }; +- }; +- +- uart0 { +- uart0_xfer: uart0-xfer { +- rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, +- <1 RK_PB0 1 &pcfg_pull_up>; +- }; +- +- uart0_cts: uart0-cts { +- rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; +- }; +- +- uart0_rts: uart0-rts { +- rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; +- }; +- +- uart0_rts_pin: uart0-rts-pin { +- rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- uart1 { +- uart1_xfer: uart1-xfer { +- rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, +- <3 RK_PA6 4 &pcfg_pull_up>; +- }; +- +- uart1_cts: uart1-cts { +- rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; +- }; +- +- uart1_rts: uart1-rts { +- rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; +- }; +- +- uart1_rts_pin: uart1-rts-pin { +- rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- uart2-0 { +- uart2m0_xfer: uart2m0-xfer { +- rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, +- <1 RK_PA1 2 &pcfg_pull_up>; +- }; +- }; +- +- uart2-1 { +- uart2m1_xfer: uart2m1-xfer { +- rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, +- <2 RK_PA1 1 &pcfg_pull_up>; +- }; +- }; +- +- spi0-0 { +- spi0m0_clk: spi0m0-clk { +- rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; +- }; +- +- spi0m0_cs0: spi0m0-cs0 { +- rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; +- }; +- +- spi0m0_tx: spi0m0-tx { +- rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; +- }; +- +- spi0m0_rx: spi0m0-rx { +- rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; +- }; +- +- spi0m0_cs1: spi0m0-cs1 { +- rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; +- }; +- }; +- +- spi0-1 { +- spi0m1_clk: spi0m1-clk { +- rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; +- }; +- +- spi0m1_cs0: spi0m1-cs0 { +- rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; +- }; +- +- spi0m1_tx: spi0m1-tx { +- rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; +- }; +- +- spi0m1_rx: spi0m1-rx { +- rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; +- }; +- +- spi0m1_cs1: spi0m1-cs1 { +- rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; +- }; +- }; +- +- spi0-2 { +- spi0m2_clk: spi0m2-clk { +- rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; +- }; +- +- spi0m2_cs0: spi0m2-cs0 { +- rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; +- }; +- +- spi0m2_tx: spi0m2-tx { +- rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; +- }; +- +- spi0m2_rx: spi0m2-rx { +- rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; +- }; +- }; +- +- i2s1 { +- i2s1_mclk: i2s1-mclk { +- rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; +- }; +- +- i2s1_sclk: i2s1-sclk { +- rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; +- }; +- +- i2s1_lrckrx: i2s1-lrckrx { +- rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; +- }; +- +- i2s1_lrcktx: i2s1-lrcktx { +- rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; +- }; +- +- i2s1_sdi: i2s1-sdi { +- rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; +- }; +- +- i2s1_sdo: i2s1-sdo { +- rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; +- }; +- +- i2s1_sdio1: i2s1-sdio1 { +- rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; +- }; +- +- i2s1_sdio2: i2s1-sdio2 { +- rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; +- }; +- +- i2s1_sdio3: i2s1-sdio3 { +- rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; +- }; +- +- i2s1_sleep: i2s1-sleep { +- rockchip,pins = +- <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, +- <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, +- <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, +- <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, +- <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, +- <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, +- <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, +- <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, +- <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; +- }; +- }; +- +- i2s2-0 { +- i2s2m0_mclk: i2s2m0-mclk { +- rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; +- }; +- +- i2s2m0_sclk: i2s2m0-sclk { +- rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; +- }; +- +- i2s2m0_lrckrx: i2s2m0-lrckrx { +- rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; +- }; +- +- i2s2m0_lrcktx: i2s2m0-lrcktx { +- rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; +- }; +- +- i2s2m0_sdi: i2s2m0-sdi { +- rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; +- }; +- +- i2s2m0_sdo: i2s2m0-sdo { +- rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; +- }; +- +- i2s2m0_sleep: i2s2m0-sleep { +- rockchip,pins = +- <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, +- <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, +- <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, +- <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, +- <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, +- <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; +- }; +- }; +- +- i2s2-1 { +- i2s2m1_mclk: i2s2m1-mclk { +- rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; +- }; +- +- i2s2m1_sclk: i2s2m1-sclk { +- rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; +- }; +- +- i2s2m1_lrckrx: i2sm1-lrckrx { +- rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; +- }; +- +- i2s2m1_lrcktx: i2s2m1-lrcktx { +- rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; +- }; +- +- i2s2m1_sdi: i2s2m1-sdi { +- rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; +- }; +- +- i2s2m1_sdo: i2s2m1-sdo { +- rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; +- }; +- +- i2s2m1_sleep: i2s2m1-sleep { +- rockchip,pins = +- <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, +- <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, +- <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, +- <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, +- <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; +- }; +- }; +- +- spdif-0 { +- spdifm0_tx: spdifm0-tx { +- rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; +- }; +- }; +- +- spdif-1 { +- spdifm1_tx: spdifm1-tx { +- rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; +- }; +- }; +- +- spdif-2 { +- spdifm2_tx: spdifm2-tx { +- rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; +- }; +- }; +- +- sdmmc0-0 { +- sdmmc0m0_pwren: sdmmc0m0-pwren { +- rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; +- }; +- +- sdmmc0m0_pin: sdmmc0m0-pin { +- rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; +- }; +- }; +- +- sdmmc0-1 { +- sdmmc0m1_pwren: sdmmc0m1-pwren { +- rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; +- }; +- +- sdmmc0m1_pin: sdmmc0m1-pin { +- rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; +- }; +- }; +- +- sdmmc0 { +- sdmmc0_clk: sdmmc0-clk { +- rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; +- }; +- +- sdmmc0_cmd: sdmmc0-cmd { +- rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; +- }; +- +- sdmmc0_dectn: sdmmc0-dectn { +- rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; +- }; +- +- sdmmc0_wrprt: sdmmc0-wrprt { +- rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; +- }; +- +- sdmmc0_bus1: sdmmc0-bus1 { +- rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; +- }; +- +- sdmmc0_bus4: sdmmc0-bus4 { +- rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, +- <1 RK_PA1 1 &pcfg_pull_up_8ma>, +- <1 RK_PA2 1 &pcfg_pull_up_8ma>, +- <1 RK_PA3 1 &pcfg_pull_up_8ma>; +- }; +- +- sdmmc0_pins: sdmmc0-pins { +- rockchip,pins = +- <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; +- }; +- }; +- +- sdmmc0ext { +- sdmmc0ext_clk: sdmmc0ext-clk { +- rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; +- }; +- +- sdmmc0ext_cmd: sdmmc0ext-cmd { +- rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; +- }; +- +- sdmmc0ext_wrprt: sdmmc0ext-wrprt { +- rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; +- }; +- +- sdmmc0ext_dectn: sdmmc0ext-dectn { +- rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; +- }; +- +- sdmmc0ext_bus1: sdmmc0ext-bus1 { +- rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; +- }; +- +- sdmmc0ext_bus4: sdmmc0ext-bus4 { +- rockchip,pins = +- <3 RK_PA4 3 &pcfg_pull_up_4ma>, +- <3 RK_PA5 3 &pcfg_pull_up_4ma>, +- <3 RK_PA6 3 &pcfg_pull_up_4ma>, +- <3 RK_PA7 3 &pcfg_pull_up_4ma>; +- }; +- +- sdmmc0ext_pins: sdmmc0ext-pins { +- rockchip,pins = +- <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; +- }; +- }; +- +- sdmmc1 { +- sdmmc1_clk: sdmmc1-clk { +- rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; +- }; +- +- sdmmc1_cmd: sdmmc1-cmd { +- rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; +- }; +- +- sdmmc1_pwren: sdmmc1-pwren { +- rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; +- }; +- +- sdmmc1_wrprt: sdmmc1-wrprt { +- rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; +- }; +- +- sdmmc1_dectn: sdmmc1-dectn { +- rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; +- }; +- +- sdmmc1_bus1: sdmmc1-bus1 { +- rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; +- }; +- +- sdmmc1_bus4: sdmmc1-bus4 { +- rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, +- <1 RK_PB7 1 &pcfg_pull_up_8ma>, +- <1 RK_PC0 1 &pcfg_pull_up_8ma>, +- <1 RK_PC1 1 &pcfg_pull_up_8ma>; +- }; +- +- sdmmc1_pins: sdmmc1-pins { +- rockchip,pins = +- <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, +- <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; +- }; +- }; +- +- emmc { +- emmc_clk: emmc-clk { +- rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; +- }; +- +- emmc_cmd: emmc-cmd { +- rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; +- }; +- +- emmc_pwren: emmc-pwren { +- rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; +- }; +- +- emmc_rstnout: emmc-rstnout { +- rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; +- }; +- +- emmc_bus1: emmc-bus1 { +- rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; +- }; +- +- emmc_bus4: emmc-bus4 { +- rockchip,pins = +- <0 RK_PA7 2 &pcfg_pull_up_12ma>, +- <2 RK_PD4 2 &pcfg_pull_up_12ma>, +- <2 RK_PD5 2 &pcfg_pull_up_12ma>, +- <2 RK_PD6 2 &pcfg_pull_up_12ma>; +- }; +- +- emmc_bus8: emmc-bus8 { +- rockchip,pins = +- <0 RK_PA7 2 &pcfg_pull_up_12ma>, +- <2 RK_PD4 2 &pcfg_pull_up_12ma>, +- <2 RK_PD5 2 &pcfg_pull_up_12ma>, +- <2 RK_PD6 2 &pcfg_pull_up_12ma>, +- <2 RK_PD7 2 &pcfg_pull_up_12ma>, +- <3 RK_PC0 2 &pcfg_pull_up_12ma>, +- <3 RK_PC1 2 &pcfg_pull_up_12ma>, +- <3 RK_PC2 2 &pcfg_pull_up_12ma>; +- }; +- }; +- +- pwm0 { +- pwm0_pin: pwm0-pin { +- rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm1 { +- pwm1_pin: pwm1-pin { +- rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm2 { +- pwm2_pin: pwm2-pin { +- rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; +- }; +- }; +- +- pwmir { +- pwmir_pin: pwmir-pin { +- rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; +- }; +- }; +- +- gmac-1 { +- rgmiim1_pins: rgmiim1-pins { +- rockchip,pins = +- /* mac_txclk */ +- <1 RK_PB4 2 &pcfg_pull_none_8ma>, +- /* mac_rxclk */ +- <1 RK_PB5 2 &pcfg_pull_none_4ma>, +- /* mac_mdio */ +- <1 RK_PC3 2 &pcfg_pull_none_4ma>, +- /* mac_txen */ +- <1 RK_PD1 2 &pcfg_pull_none_8ma>, +- /* mac_clk */ +- <1 RK_PC5 2 &pcfg_pull_none_4ma>, +- /* mac_rxdv */ +- <1 RK_PC6 2 &pcfg_pull_none_4ma>, +- /* mac_mdc */ +- <1 RK_PC7 2 &pcfg_pull_none_4ma>, +- /* mac_rxd1 */ +- <1 RK_PB2 2 &pcfg_pull_none_4ma>, +- /* mac_rxd0 */ +- <1 RK_PB3 2 &pcfg_pull_none_4ma>, +- /* mac_txd1 */ +- <1 RK_PB0 2 &pcfg_pull_none_8ma>, +- /* mac_txd0 */ +- <1 RK_PB1 2 &pcfg_pull_none_8ma>, +- /* mac_rxd3 */ +- <1 RK_PB6 2 &pcfg_pull_none_4ma>, +- /* mac_rxd2 */ +- <1 RK_PB7 2 &pcfg_pull_none_4ma>, +- /* mac_txd3 */ +- <1 RK_PC0 2 &pcfg_pull_none_8ma>, +- /* mac_txd2 */ +- <1 RK_PC1 2 &pcfg_pull_none_8ma>, +- +- /* mac_txclk */ +- <0 RK_PB0 1 &pcfg_pull_none_8ma>, +- /* mac_txen */ +- <0 RK_PB4 1 &pcfg_pull_none_8ma>, +- /* mac_clk */ +- <0 RK_PD0 1 &pcfg_pull_none_4ma>, +- /* mac_txd1 */ +- <0 RK_PC0 1 &pcfg_pull_none_8ma>, +- /* mac_txd0 */ +- <0 RK_PC1 1 &pcfg_pull_none_8ma>, +- /* mac_txd3 */ +- <0 RK_PC7 1 &pcfg_pull_none_8ma>, +- /* mac_txd2 */ +- <0 RK_PC6 1 &pcfg_pull_none_8ma>; +- }; +- +- rmiim1_pins: rmiim1-pins { +- rockchip,pins = +- /* mac_mdio */ +- <1 RK_PC3 2 &pcfg_pull_none_2ma>, +- /* mac_txen */ +- <1 RK_PD1 2 &pcfg_pull_none_12ma>, +- /* mac_clk */ +- <1 RK_PC5 2 &pcfg_pull_none_2ma>, +- /* mac_rxer */ +- <1 RK_PD0 2 &pcfg_pull_none_2ma>, +- /* mac_rxdv */ +- <1 RK_PC6 2 &pcfg_pull_none_2ma>, +- /* mac_mdc */ +- <1 RK_PC7 2 &pcfg_pull_none_2ma>, +- /* mac_rxd1 */ +- <1 RK_PB2 2 &pcfg_pull_none_2ma>, +- /* mac_rxd0 */ +- <1 RK_PB3 2 &pcfg_pull_none_2ma>, +- /* mac_txd1 */ +- <1 RK_PB0 2 &pcfg_pull_none_12ma>, +- /* mac_txd0 */ +- <1 RK_PB1 2 &pcfg_pull_none_12ma>, +- +- /* mac_mdio */ +- <0 RK_PB3 1 &pcfg_pull_none>, +- /* mac_txen */ +- <0 RK_PB4 1 &pcfg_pull_none>, +- /* mac_clk */ +- <0 RK_PD0 1 &pcfg_pull_none>, +- /* mac_mdc */ +- <0 RK_PC3 1 &pcfg_pull_none>, +- /* mac_txd1 */ +- <0 RK_PC0 1 &pcfg_pull_none>, +- /* mac_txd0 */ +- <0 RK_PC1 1 &pcfg_pull_none>; +- }; +- }; +- +- gmac2phy { +- fephyled_speed10: fephyled-speed10 { +- rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; +- }; +- +- fephyled_duplex: fephyled-duplex { +- rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; +- }; +- +- fephyled_rxm1: fephyled-rxm1 { +- rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; +- }; +- +- fephyled_txm1: fephyled-txm1 { +- rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; +- }; +- +- fephyled_linkm1: fephyled-linkm1 { +- rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; +- }; +- }; +- +- tsadc_pin { +- tsadc_int: tsadc-int { +- rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; +- }; +- tsadc_pin: tsadc-pin { +- rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- hdmi_pin { +- hdmi_cec: hdmi-cec { +- rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; +- }; +- +- hdmi_hpd: hdmi-hpd { +- rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; +- }; +- }; +- +- cif-0 { +- dvp_d2d9_m0:dvp-d2d9-m0 { +- rockchip,pins = +- /* cif_d0 */ +- <3 RK_PA4 2 &pcfg_pull_none>, +- /* cif_d1 */ +- <3 RK_PA5 2 &pcfg_pull_none>, +- /* cif_d2 */ +- <3 RK_PA6 2 &pcfg_pull_none>, +- /* cif_d3 */ +- <3 RK_PA7 2 &pcfg_pull_none>, +- /* cif_d4 */ +- <3 RK_PB0 2 &pcfg_pull_none>, +- /* cif_d5m0 */ +- <3 RK_PB1 2 &pcfg_pull_none>, +- /* cif_d6m0 */ +- <3 RK_PB2 2 &pcfg_pull_none>, +- /* cif_d7m0 */ +- <3 RK_PB3 2 &pcfg_pull_none>, +- /* cif_href */ +- <3 RK_PA1 2 &pcfg_pull_none>, +- /* cif_vsync */ +- <3 RK_PA0 2 &pcfg_pull_none>, +- /* cif_clkoutm0 */ +- <3 RK_PA3 2 &pcfg_pull_none>, +- /* cif_clkin */ +- <3 RK_PA2 2 &pcfg_pull_none>; +- }; +- }; +- +- cif-1 { +- dvp_d2d9_m1:dvp-d2d9-m1 { +- rockchip,pins = +- /* cif_d0 */ +- <3 RK_PA4 2 &pcfg_pull_none>, +- /* cif_d1 */ +- <3 RK_PA5 2 &pcfg_pull_none>, +- /* cif_d2 */ +- <3 RK_PA6 2 &pcfg_pull_none>, +- /* cif_d3 */ +- <3 RK_PA7 2 &pcfg_pull_none>, +- /* cif_d4 */ +- <3 RK_PB0 2 &pcfg_pull_none>, +- /* cif_d5m1 */ +- <2 RK_PC0 4 &pcfg_pull_none>, +- /* cif_d6m1 */ +- <2 RK_PC1 4 &pcfg_pull_none>, +- /* cif_d7m1 */ +- <2 RK_PC2 4 &pcfg_pull_none>, +- /* cif_href */ +- <3 RK_PA1 2 &pcfg_pull_none>, +- /* cif_vsync */ +- <3 RK_PA0 2 &pcfg_pull_none>, +- /* cif_clkoutm1 */ +- <2 RK_PB7 4 &pcfg_pull_none>, +- /* cif_clkin */ +- <3 RK_PA2 2 &pcfg_pull_none>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-evb-act8846.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-evb-act8846.dts +deleted file mode 100644 +index 160f2c7e9559..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-evb-act8846.dts ++++ /dev/null +@@ -1,139 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2015 Caesar Wang +- */ +- +-/dts-v1/; +-#include "rk3368-evb.dtsi" +- +-/ { +- model = "Rockchip RK3368 EVB with ACT8846 pmic"; +- compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- +- vdd_cpu: syr827@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_cpu"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vdd_gpu: syr828@41 { +- compatible = "silergy,syr828"; +- reg = <0x41>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_gpu"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- vin-supply = <&vcc_sys>; +- }; +- +- act8846: act8846@5a { +- compatible = "active-semi,act8846"; +- reg = <0x5a>; +- status = "okay"; +- +- vp1-supply = <&vcc_sys>; +- vp2-supply = <&vcc_sys>; +- vp3-supply = <&vcc_sys>; +- vp4-supply = <&vcc_sys>; +- inl1-supply = <&vcc_io>; +- inl2-supply = <&vcc_sys>; +- inl3-supply = <&vcc_20>; +- +- regulators { +- vcc_ddr: REG1 { +- regulator-name = "VCC_DDR"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- +- vcc_io: REG2 { +- regulator-name = "VCC_IO"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_log: REG3 { +- regulator-name = "VDD_LOG"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- +- vcc_20: REG4 { +- regulator-name = "VCC_20"; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- regulator-always-on; +- }; +- +- vccio_sd: REG5 { +- regulator-name = "VCCIO_SD"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd10_lcd: REG6 { +- regulator-name = "VDD10_LCD"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- vcca_codec: REG7 { +- regulator-name = "VCCA_CODEC"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vcca_tp: REG8 { +- regulator-name = "VCCA_TP"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vccio_pmu: REG9 { +- regulator-name = "VCCIO_PMU"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- vdd_10: REG10 { +- regulator-name = "VDD_10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- }; +- +- vcc_18: REG11 { +- regulator-name = "VCC_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcc18_lcd: REG12 { +- regulator-name = "VCC18_LCD"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-evb.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-evb.dtsi +deleted file mode 100644 +index 15d1fc541c38..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-evb.dtsi ++++ /dev/null +@@ -1,244 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2015 Caesar Wang +- */ +- +-#include +-#include +-#include "rk3368.dtsi" +- +-/ { +- aliases { +- mmc0 = &emmc; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x40000000>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- brightness-levels = < +- 0 1 2 3 4 5 6 7 +- 8 9 10 11 12 13 14 15 +- 16 17 18 19 20 21 22 23 +- 24 25 26 27 28 29 30 31 +- 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 +- 48 49 50 51 52 53 54 55 +- 56 57 58 59 60 61 62 63 +- 64 65 66 67 68 69 70 71 +- 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 +- 88 89 90 91 92 93 94 95 +- 96 97 98 99 100 101 102 103 +- 104 105 106 107 108 109 110 111 +- 112 113 114 115 116 117 118 119 +- 120 121 122 123 124 125 126 127 +- 128 129 130 131 132 133 134 135 +- 136 137 138 139 140 141 142 143 +- 144 145 146 147 148 149 150 151 +- 152 153 154 155 156 157 158 159 +- 160 161 162 163 164 165 166 167 +- 168 169 170 171 172 173 174 175 +- 176 177 178 179 180 181 182 183 +- 184 185 186 187 188 189 190 191 +- 192 193 194 195 196 197 198 199 +- 200 201 202 203 204 205 206 207 +- 208 209 210 211 212 213 214 215 +- 216 217 218 219 220 221 222 223 +- 224 225 226 227 228 229 230 231 +- 232 233 234 235 236 237 238 239 +- 240 241 242 243 244 245 246 247 +- 248 249 250 251 252 253 254 255>; +- default-brightness-level = <128>; +- enable-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bl_en>; +- pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>; +- pwm-delay-us = <10000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- pinctrl-0 = <&emmc_reset>; +- pinctrl-names = "default"; +- reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; +- }; +- +- keys: gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_key>; +- +- power { +- wakeup-source; +- gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; +- label = "GPIO Power"; +- linux,code = ; +- }; +- }; +- +- /* supplies both host and otg */ +- vcc_host: vcc-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&host_vbus_drv>; +- regulator-name = "vcc_host"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_lan: vcc-lan-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_lan"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_sys: vcc-sys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-pwrseq = <&emmc_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +- status = "okay"; +-}; +- +-&gmac { +- phy-supply = <&vcc_lan>; +- phy-mode = "rmii"; +- clock_in_out = "output"; +- snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 1000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&rmii_pins>; +- tx_delay = <0x30>; +- rx_delay = <0x10>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&pinctrl { +- pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { +- bias-disable; +- drive-strength = <8>; +- }; +- +- pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { +- bias-pull-up; +- drive-strength = <8>; +- }; +- +- backlight { +- bl_en: bl-en { +- rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- emmc { +- emmc_bus8: emmc-bus8 { +- rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PC3 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PC4 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PC5 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PC6 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PC7 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PD0 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PD1 2 &pcfg_pull_up_drv_8ma>; +- }; +- +- emmc-clk { +- rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none_drv_8ma>; +- }; +- +- emmc-cmd { +- rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up_drv_8ma>; +- }; +- +- emmc_reset: emmc-reset { +- rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- keys { +- pwr_key: pwr-key { +- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- pmic { +- pmic_int: pmic-int { +- rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- sdio { +- wifi_reg_on: wifi-reg-on { +- rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_rst: bt-rst { +- rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb { +- host_vbus_drv: host-vbus-drv { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-geekbox.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-geekbox.dts +deleted file mode 100644 +index 62aa97a0b8c9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-geekbox.dts ++++ /dev/null +@@ -1,281 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Andreas Färber +- */ +- +-/dts-v1/; +-#include "rk3368.dtsi" +-#include +- +-/ { +- model = "GeekBox"; +- compatible = "geekbuying,geekbox", "rockchip,rk3368"; +- +- aliases { +- mmc0 = &emmc; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- ext_gmac: gmac-clk { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "ext_gmac"; +- #clock-cells = <0>; +- }; +- +- ir: ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ir_int>; +- }; +- +- keys: gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_key>; +- +- power { +- gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; +- label = "GPIO Power"; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds: gpio-leds { +- compatible = "gpio-leds"; +- +- blue_led: led-0 { +- gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; +- label = "geekbox:blue:led"; +- default-state = "on"; +- }; +- +- red_led: led-1 { +- gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; +- label = "geekbox:red:led"; +- default-state = "off"; +- }; +- }; +- +- vcc_sys: vcc-sys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&emmc { +- status = "okay"; +- bus-width = <8>; +- cap-mmc-highspeed; +- clock-frequency = <150000000>; +- non-removable; +- vmmc-supply = <&vcc_io>; +- vqmmc-supply = <&vcc18_flash>; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; +-}; +- +-&gmac { +- status = "okay"; +- phy-supply = <&vcc_lan>; +- phy-mode = "rgmii"; +- clock_in_out = "input"; +- assigned-clocks = <&cru SCLK_MAC>; +- assigned-clock-parents = <&ext_gmac>; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- tx_delay = <0x30>; +- rx_delay = <0x10>; +-}; +- +-&i2c0 { +- status = "okay"; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int>, <&pmic_sleep>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- rockchip,system-power-controller; +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc6-supply = <&vcc_sys>; +- vcc7-supply = <&vcc_sys>; +- vcc8-supply = <&vcc_io>; +- vcc9-supply = <&vcc_sys>; +- vcc10-supply = <&vcc_sys>; +- vcc11-supply = <&vcc_sys>; +- vcc12-supply = <&vcc_io>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- #clock-cells = <1>; +- +- regulators { +- vdd_cpu: DCDC_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vdd_cpu"; +- }; +- +- vdd_log: DCDC_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vdd_log"; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc_ddr"; +- }; +- +- vcc_io: DCDC_REG4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc_io"; +- }; +- +- vcc18_flash: LDO_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc18_flash"; +- }; +- +- vcc33_lcd: LDO_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc33_lcd"; +- }; +- +- vdd_10: LDO_REG3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-name = "vdd_10"; +- }; +- +- vcca_18: LDO_REG4 { +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcca_18"; +- }; +- +- vccio_sd: LDO_REG5 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vccio_sd"; +- }; +- +- vdd10_lcd: LDO_REG6 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-name = "vdd10_lcd"; +- }; +- +- vcc_18: LDO_REG7 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc_18"; +- }; +- +- vcc18_lcd: LDO_REG8 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc18_lcd"; +- }; +- +- vcc_sd: SWITCH_REG1 { +- regulator-name = "vcc_sd"; +- }; +- +- vcc_lan: SWITCH_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc_lan"; +- }; +- }; +- }; +-}; +- +-&pinctrl { +- ir { +- ir_int: ir-int { +- rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- keys { +- pwr_key: pwr-key { +- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- pmic_sleep: pmic-sleep { +- rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; +- }; +- +- pmic_int: pmic-int { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +- +-&tsadc { +- status = "okay"; +- rockchip,hw-tshut-mode = <0>; /* CRU */ +- rockchip,hw-tshut-polarity = <1>; /* high */ +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-lion-haikou.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-lion-haikou.dts +deleted file mode 100644 +index cae01d35b93d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-lion-haikou.dts ++++ /dev/null +@@ -1,144 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Theobroma Systems Design und Consulting GmbH +- */ +- +-/dts-v1/; +-#include "rk3368-lion.dtsi" +- +-/ { +- model = "Theobroma Systems RK3368-uQ7 Baseboard"; +- compatible = "tsd,rk3368-lion-haikou", "rockchip,rk3368"; +- +- aliases { +- mmc1 = &sdmmc; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- i2cmux2 { +- i2c@0 { +- eeprom: eeprom@50 { +- compatible = "atmel,24c01"; +- pagesize = <8>; +- reg = <0x50>; +- }; +- }; +- }; +- +- leds { +- pinctrl-0 = <&module_led_pins>, <&sd_card_led_pin>; +- +- sd_card_led: led-3 { +- label = "sd_card_led"; +- gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- }; +- }; +- +- dc_12v: dc-12v { +- compatible = "regulator-fixed"; +- regulator-name = "dc_12v"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- vcc3v3_baseboard: vcc3v3-baseboard { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_baseboard"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&dc_12v>; +- }; +- +- vcc5v0_otg: vcc5v0-otg-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&otg_vbus_drv>; +- regulator-name = "vcc5v0_otg"; +- regulator-always-on; +- }; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- cd-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>; +- disable-wp; +- max-frequency = <25000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; +- rockchip,default-sample-phase = <90>; +- vmmc-supply = <&vcc3v3_baseboard>; +- status = "okay"; +-}; +- +-&spi2 { +- cs-gpios = <0>, <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "otg"; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +- status = "okay"; +-}; +- +-&uart1 { +- /* alternate function of GPIO5/6 */ +- status = "disabled"; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&haikou_pin_hog>; +- +- hog { +- haikou_pin_hog: haikou-pin-hog { +- rockchip,pins = +- /* LID_BTN */ +- <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, +- /* BATLOW# */ +- <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>, +- /* SLP_BTN# */ +- <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, +- /* BIOS_DISABLE# */ +- <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- leds { +- sd_card_led_pin: sd-card-led-pin { +- rockchip,pins = +- <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdmmc { +- sdmmc_cd_pin: sdmmc-cd-pin { +- rockchip,pins = +- <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb_otg { +- otg_vbus_drv: otg-vbus-drv { +- rockchip,pins = +- <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-lion.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-lion.dtsi +deleted file mode 100644 +index bcd7977fb0f8..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-lion.dtsi ++++ /dev/null +@@ -1,318 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Theobroma Systems Design und Consulting GmbH +- */ +- +-/dts-v1/; +-#include "rk3368.dtsi" +- +-/ { +- aliases { +- mmc0 = &emmc; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- ext_gmac: gmac-clk { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "ext_gmac"; +- #clock-cells = <0>; +- }; +- +- i2cmux1 { +- compatible = "i2c-mux-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-parent = <&i2c1>; +- mux-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; +- +- /* Q7_GPO_I2C */ +- i2c@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- /* Q7_SMB */ +- i2c@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- i2cmux2 { +- compatible = "i2c-mux-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-parent = <&i2c2>; +- mux-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; +- +- /* Q7_LVDS_BLC_I2C */ +- i2c@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- fan: fan@18 { +- compatible = "ti,amc6821"; +- reg = <0x18>; +- #cooling-cells = <2>; +- }; +- +- rtc_twi: rtc@6f { +- compatible = "isil,isl1208"; +- reg = <0x6f>; +- }; +- }; +- +- /* Q7_GP2_I2C */ +- i2c@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&module_led_pins>; +- +- module_led1: led-1 { +- label = "module_led1"; +- gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- panic-indicator; +- }; +- +- module_led2: led-2 { +- label = "module_led2"; +- gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- vcc_sys: vcc-sys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu_b2 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu_b3 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&emmc { +- bus-width = <8>; +- clock-frequency = <150000000>; +- mmc-hs200-1_8v; +- non-removable; +- vmmc-supply = <&vcc33_io>; +- vqmmc-supply = <&vcc18_io>; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_MAC>; +- assigned-clock-parents = <&ext_gmac>; +- clock_in_out = "input"; +- phy-supply = <&vcc33_io>; +- phy-mode = "rgmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 50000>; +- snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; +- tx_delay = <0x10>; +- rx_delay = <0x10>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- clock-output-names = "xin32k", "rk808-clkout2"; +- #clock-cells = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>, <&pmic_sleep>; +- rockchip,system-power-controller; +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc6-supply = <&vcc_sys>; +- vcc7-supply = <&vcc_sys>; +- vcc8-supply = <&vcc_sys>; +- vcc9-supply = <&vcc_sys>; +- vcc10-supply = <&vcc_sys>; +- vcc11-supply = <&vcc_sys>; +- vcc12-supply = <&vcc_sys>; +- +- regulators { +- vdd_cpu: DCDC_REG1 { +- regulator-name = "vdd_cpu"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_log: DCDC_REG2 { +- regulator-name = "vdd_log"; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc33_io: DCDC_REG4 { +- regulator-name = "vcc33_io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc33_video: LDO_REG2 { +- regulator-name = "vcc33_video"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd10_pll: LDO_REG3 { +- regulator-name = "vdd10_pll"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc18_io: LDO_REG4 { +- regulator-name = "vcc18_io"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- }; +- +- vdd10_video: LDO_REG6 { +- regulator-name = "vdd10_video"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc18_video: LDO_REG8 { +- regulator-name = "vcc18_video"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&pinctrl { +- leds { +- module_led_pins: module-led-pins { +- rockchip,pins = +- <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, +- <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- pmic_sleep: pmic-sleep { +- rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; +- }; +- }; +-}; +- +-&spi1 { +- status = "okay"; +- +- norflash: flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- }; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-orion-r68-meta.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-orion-r68-meta.dts +deleted file mode 100644 +index 3ebe15e03cf4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-orion-r68-meta.dts ++++ /dev/null +@@ -1,343 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Matthias Brugger +- */ +- +-/dts-v1/; +-#include +-#include "rk3368.dtsi" +- +-/ { +- model = "Rockchip Orion R68"; +- compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368"; +- +- aliases { +- mmc0 = &sdmmc; +- mmc1 = &emmc; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- pinctrl-0 = <&emmc_reset>; +- pinctrl-names = "default"; +- reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; +- }; +- +- ext_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- clock-output-names = "ext_gmac"; +- }; +- +- keys: gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_key>; +- +- power { +- wakeup-source; +- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; +- label = "GPIO Power"; +- linux,code = ; +- }; +- }; +- +- leds: gpio-leds { +- compatible = "gpio-leds"; +- +- red_led: led-0 { +- gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; +- label = "orion:red:led"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_ctl>; +- default-state = "on"; +- }; +- +- blue_led: led-1 { +- gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; +- label = "orion:blue:led"; +- pinctrl-names = "default"; +- pinctrl-0 = <&stby_pwren>; +- default-state = "off"; +- }; +- }; +- +- vcc_18: vcc18-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +- /* supplies both host and otg */ +- vcc_host: vcc-host-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&host_vbus_drv>; +- regulator-name = "vcc_host"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_io: vcc-io-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_lan: vcc-lan-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_lan"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_sd: vcc-sd-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sd"; +- gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_sys: vcc-sys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vccio_sd: vcc-io-sd-regulator { +- compatible = "regulator-fixed"; +- regulator-name= "vccio_sd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_io>; +- }; +- +- vccio_wl: vccio-wl-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vccio_wl"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_io>; +- }; +- +- vdd_10: vdd-10-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-pwrseq = <&emmc_pwrseq>; +- mmc-hs200-1_2v; +- mmc-hs200-1_8v; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_MAC>; +- assigned-clock-parents = <&ext_gmac>; +- clock_in_out = "input"; +- phy-supply = <&vcc_lan>; +- phy-mode = "rgmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 1000000>; +- tx_delay = <0x30>; +- rx_delay = <0x10>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- vdd_cpu: syr827@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_cpu"; +- regulator-enable-ramp-delay = <300>; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <8000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +- hym8563: hym8563@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "xin32k"; +- /* rtc_int is not connected */ +- }; +-}; +- +-&pinctrl { +- pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { +- bias-disable; +- drive-strength = <8>; +- }; +- +- pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { +- bias-pull-up; +- drive-strength = <8>; +- }; +- +- emmc { +- emmc_bus8: emmc-bus8 { +- rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PC3 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PC4 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PC5 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PC6 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PC7 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PD0 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PD1 2 &pcfg_pull_up_drv_8ma>; +- }; +- +- emmc-clk { +- rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none_drv_8ma>; +- }; +- +- emmc-cmd { +- rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up_drv_8ma>; +- }; +- +- emmc_reset: emmc-reset { +- rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- keys { +- pwr_key: pwr-key { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- leds { +- stby_pwren: stby-pwren { +- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- led_ctl: led-ctl { +- rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdmmc { +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none_drv_8ma>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up_drv_8ma>; +- }; +- +- sdmmc_cd: sdmmc-cd { +- rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up_drv_8ma>; +- }; +- +- sdmmc_bus1: sdmmc-bus1 { +- rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up_drv_8ma>; +- }; +- +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up_drv_8ma>, +- <2 RK_PA6 1 &pcfg_pull_up_drv_8ma>, +- <2 RK_PA7 1 &pcfg_pull_up_drv_8ma>, +- <2 RK_PB0 1 &pcfg_pull_up_drv_8ma>; +- }; +- }; +- +- usb { +- host_vbus_drv: host-vbus-drv { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&saradc { +- vref-supply = <&vcc_18>; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- clock-frequency = <50000000>; +- max-frequency = <50000000>; +- cap-sd-highspeed; +- card-detect-delay = <200>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +- vmmc-supply = <&vcc_sd>; +- vqmmc-supply = <&vccio_sd>; +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_xfer>; +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-px5-evb.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-px5-evb.dts +deleted file mode 100644 +index 5ccaa5f7a370..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-px5-evb.dts ++++ /dev/null +@@ -1,277 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd +- */ +- +-/dts-v1/; +-#include "rk3368.dtsi" +-#include +- +-/ { +- model = "Rockchip PX5 EVB"; +- compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368"; +- +- aliases { +- mmc0 = &sdmmc; +- mmc1 = &emmc; +- }; +- +- chosen { +- stdout-path = "serial4:115200n8"; +- }; +- +- memory@0 { +- reg = <0x0 0x0 0x0 0x40000000>; +- device_type = "memory"; +- }; +- +- keys: gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_key>; +- +- power { +- gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; +- label = "GPIO Power"; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- vcc_sys: vcc-sys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&emmc { +- status = "okay"; +- bus-width = <8>; +- cap-mmc-highspeed; +- clock-frequency = <150000000>; +- mmc-hs200-1_8v; +- no-sdio; +- no-sd; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; +- vmmc-supply = <&vcc_io>; +- vqmmc-supply = <&vcc18_flash>; +-}; +- +-&i2c0 { +- status = "okay"; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int>, <&pmic_sleep>; +- rockchip,system-power-controller; +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc6-supply = <&vcc_sys>; +- vcc7-supply = <&vcc_sys>; +- vcc8-supply = <&vcc_io>; +- vcc9-supply = <&vcc_sys>; +- vcc10-supply = <&vcc_sys>; +- vcc11-supply = <&vcc_sys>; +- vcc12-supply = <&vcc_io>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- #clock-cells = <1>; +- +- regulators { +- vdd_cpu: DCDC_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vdd_cpu"; +- }; +- +- vdd_log: DCDC_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vdd_log"; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc_ddr"; +- }; +- +- vcc_io: DCDC_REG4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc_io"; +- }; +- +- vcc18_flash: LDO_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc18_flash"; +- }; +- +- vcca_33: LDO_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcca_33"; +- }; +- +- vdd_10: LDO_REG3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-name = "vdd_10"; +- }; +- +- avdd_33: LDO_REG4 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "avdd_33"; +- }; +- +- vccio_sd: LDO_REG5 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vccio_sd"; +- }; +- +- vdd10_lcd: LDO_REG6 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-name = "vdd10_lcd"; +- }; +- +- vcc_18: LDO_REG7 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc_18"; +- }; +- +- vcc18_lcd: LDO_REG8 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc18_lcd"; +- }; +- +- vcc_sd: SWITCH_REG1 { +- regulator-name = "vcc_sd"; +- }; +- +- vcc33_lcd: SWITCH_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc33_lcd"; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- accelerometer@18 { +- compatible = "bosch,bma250"; +- reg = <0x18>; +- interrupt-parent = <&gpio2>; +- interrupts = ; +- }; +-}; +- +-&i2c2 { +- status = "okay"; +- +- gsl1680: touchscreen@40 { +- compatible = "silead,gsl1680"; +- reg = <0x40>; +- interrupt-parent = <&gpio3>; +- interrupts = ; +- power-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; +- touchscreen-size-x = <800>; +- touchscreen-size-y = <1280>; +- silead,max-fingers = <5>; +- }; +-}; +- +-&pinctrl { +- keys { +- pwr_key: pwr-key { +- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- pmic_sleep: pmic-sleep { +- rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; +- }; +- +- pmic_int: pmic-int { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +- +-&sdmmc { +- status = "okay"; +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- card-detect-delay = <200>; +- no-sdio; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_bus4>, <&sdmmc_cd>; +- rockchip,default-sample-phase = <90>; +- vmmc-supply = <&vcc_sd>; +- vqmmc-supply = <&vccio_sd>; +-}; +- +-&tsadc { +- status = "okay"; +- rockchip,hw-tshut-mode = <0>; /* CRU */ +- rockchip,hw-tshut-polarity = <1>; /* high */ +-}; +- +-&uart4 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_otg { +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-r88.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-r88.dts +deleted file mode 100644 +index 959d3cc801f2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-r88.dts ++++ /dev/null +@@ -1,338 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2015 Heiko Stuebner +- */ +- +-/dts-v1/; +-#include "rk3368.dtsi" +-#include +- +-/ { +- model = "Rockchip R88"; +- compatible = "rockchip,r88", "rockchip,rk3368"; +- +- aliases { +- mmc0 = &sdio0; +- mmc1 = &emmc; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x40000000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- pinctrl-0 = <&emmc_reset>; +- pinctrl-names = "default"; +- reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; +- }; +- +- keys: gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_key>; +- +- power { +- wakeup-source; +- gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; +- label = "GPIO Power"; +- linux,code = ; +- }; +- }; +- +- leds: gpio-leds { +- compatible = "gpio-leds"; +- +- work_led: led-0 { +- gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; +- label = "r88:green:led"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_ctl>; +- }; +- }; +- +- ir: ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ir_int>; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&hym8563>; +- clock-names = "ext_clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_rst>, <&wifi_reg_on>; +- +- reset-gpios = +- /* BT_RST_N */ +- <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>, +- +- /* WL_REG_ON */ +- <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; +- }; +- +- vcc_18: vcc18-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +- /* supplies both host and otg */ +- vcc_host: vcc-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&host_vbus_drv>; +- regulator-name = "vcc_host"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_io: vcc-io-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_lan: vcc-lan-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_lan"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_io>; +- }; +- +- vcc_sys: vcc-sys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vccio_wl: vccio-wl-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vccio_wl"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_io>; +- }; +- +- vdd_10: vdd-10-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_10"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1000000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +-}; +- +-&emmc { +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-pwrseq = <&emmc_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +- status = "okay"; +-}; +- +-&gmac { +- phy-supply = <&vcc_lan>; +- phy-mode = "rmii"; +- clock_in_out = "output"; +- snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 1000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&rmii_pins>; +- tx_delay = <0x30>; +- rx_delay = <0x10>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- vdd_cpu: syr827@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_cpu"; +- regulator-enable-ramp-delay = <300>; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <8000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +- hym8563: hym8563@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "xin32k"; +- /* rtc_int is not connected */ +- }; +-}; +- +-&io_domains { +- status = "okay"; +- +- audio-supply = <&vcc_io>; +- gpio30-supply = <&vcc_io>; +- gpio1830-supply = <&vcc_io>; +- wifi-supply = <&vccio_wl>; +-}; +- +-&sdio0 { +- assigned-clocks = <&cru SCLK_SDIO0>; +- assigned-clock-parents = <&cru PLL_CPLL>; +- bus-width = <4>; +- cap-sd-highspeed; +- cap-sdio-irq; +- keep-power-in-suspend; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; +- vmmc-supply = <&vcc_io>; +- vqmmc-supply = <&vccio_wl>; +- status = "okay"; +-}; +- +-&pinctrl { +- pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { +- bias-disable; +- drive-strength = <8>; +- }; +- +- pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { +- bias-pull-up; +- drive-strength = <8>; +- }; +- +- emmc { +- emmc_bus8: emmc-bus8 { +- rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PC3 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PC4 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PC5 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PC6 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PC7 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PD0 2 &pcfg_pull_up_drv_8ma>, +- <1 RK_PD1 2 &pcfg_pull_up_drv_8ma>; +- }; +- +- emmc-clk { +- rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none_drv_8ma>; +- }; +- +- emmc-cmd { +- rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up_drv_8ma>; +- }; +- +- emmc_reset: emmc-reset { +- rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- ir { +- ir_int: ir-int { +- rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- keys { +- pwr_key: pwr-key { +- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- leds { +- stby_pwren: stby-pwren { +- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- led_ctl: led-ctl { +- rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdio { +- wifi_reg_on: wifi-reg-on { +- rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_rst: bt-rst { +- rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb { +- host_vbus_drv: host-vbus-drv { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pmu_io_domains { +- status = "okay"; +- +- pmu-supply = <&vcc_io>; +- vop-supply = <&vcc_io>; +-}; +- +-&saradc { +- vref-supply = <&vcc_18>; +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_otg { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&wdt { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3368.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3368.dtsi +deleted file mode 100644 +index 4c64fbefb483..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3368.dtsi ++++ /dev/null +@@ -1,1218 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2015 Heiko Stuebner +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "rockchip,rk3368"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- ethernet0 = &gmac; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- spi0 = &spi0; +- spi1 = &spi1; +- spi2 = &spi2; +- }; +- +- cpus { +- #address-cells = <0x2>; +- #size-cells = <0x0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu_b0>; +- }; +- core1 { +- cpu = <&cpu_b1>; +- }; +- core2 { +- cpu = <&cpu_b2>; +- }; +- core3 { +- cpu = <&cpu_b3>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&cpu_l0>; +- }; +- core1 { +- cpu = <&cpu_l1>; +- }; +- core2 { +- cpu = <&cpu_l2>; +- }; +- core3 { +- cpu = <&cpu_l3>; +- }; +- }; +- }; +- +- cpu_l0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- +- cpu_l1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- +- cpu_l2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- +- cpu_l3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- +- cpu_b0: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- +- cpu_b1: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x101>; +- enable-method = "psci"; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- +- cpu_b2: cpu@102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x102>; +- enable-method = "psci"; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- +- cpu_b3: cpu@103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x103>; +- enable-method = "psci"; +- #cooling-cells = <2>; /* min followed by max */ +- }; +- }; +- +- arm-pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, +- <&cpu_l3>, <&cpu_b0>, <&cpu_b1>, +- <&cpu_b2>, <&cpu_b3>; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- xin24m: oscillator { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "xin24m"; +- #clock-cells = <0>; +- }; +- +- sdmmc: mmc@ff0c0000 { +- compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xff0c0000 0x0 0x4000>; +- max-frequency = <150000000>; +- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, +- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- interrupts = ; +- resets = <&cru SRST_MMC0>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- sdio0: mmc@ff0d0000 { +- compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xff0d0000 0x0 0x4000>; +- max-frequency = <150000000>; +- clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, +- <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- interrupts = ; +- resets = <&cru SRST_SDIO0>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- emmc: mmc@ff0f0000 { +- compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xff0f0000 0x0 0x4000>; +- max-frequency = <150000000>; +- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, +- <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- interrupts = ; +- resets = <&cru SRST_EMMC>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- saradc: saradc@ff100000 { +- compatible = "rockchip,saradc"; +- reg = <0x0 0xff100000 0x0 0x100>; +- interrupts = ; +- #io-channel-cells = <1>; +- clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; +- clock-names = "saradc", "apb_pclk"; +- resets = <&cru SRST_SARADC>; +- reset-names = "saradc-apb"; +- status = "disabled"; +- }; +- +- spi0: spi@ff110000 { +- compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xff110000 0x0 0x1000>; +- clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; +- clock-names = "spiclk", "apb_pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi1: spi@ff120000 { +- compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xff120000 0x0 0x1000>; +- clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; +- clock-names = "spiclk", "apb_pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi2: spi@ff130000 { +- compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xff130000 0x0 0x1000>; +- clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; +- clock-names = "spiclk", "apb_pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@ff140000 { +- compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; +- reg = <0x0 0xff140000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "i2c"; +- clocks = <&cru PCLK_I2C2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_xfer>; +- status = "disabled"; +- }; +- +- i2c3: i2c@ff150000 { +- compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; +- reg = <0x0 0xff150000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "i2c"; +- clocks = <&cru PCLK_I2C3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_xfer>; +- status = "disabled"; +- }; +- +- i2c4: i2c@ff160000 { +- compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; +- reg = <0x0 0xff160000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "i2c"; +- clocks = <&cru PCLK_I2C4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_xfer>; +- status = "disabled"; +- }; +- +- i2c5: i2c@ff170000 { +- compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; +- reg = <0x0 0xff170000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "i2c"; +- clocks = <&cru PCLK_I2C5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_xfer>; +- status = "disabled"; +- }; +- +- uart0: serial@ff180000 { +- compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff180000 0x0 0x100>; +- clock-frequency = <24000000>; +- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; +- clock-names = "baudclk", "apb_pclk"; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart1: serial@ff190000 { +- compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff190000 0x0 0x100>; +- clock-frequency = <24000000>; +- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; +- clock-names = "baudclk", "apb_pclk"; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart3: serial@ff1b0000 { +- compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff1b0000 0x0 0x100>; +- clock-frequency = <24000000>; +- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; +- clock-names = "baudclk", "apb_pclk"; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart4: serial@ff1c0000 { +- compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff1c0000 0x0 0x100>; +- clock-frequency = <24000000>; +- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; +- clock-names = "baudclk", "apb_pclk"; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- dmac_peri: dma-controller@ff250000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xff250000 0x0 0x4000>; +- interrupts = , +- ; +- #dma-cells = <1>; +- arm,pl330-broken-no-flushp; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMAC_PERI>; +- clock-names = "apb_pclk"; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <100>; /* milliseconds */ +- polling-delay = <5000>; /* milliseconds */ +- +- thermal-sensors = <&tsadc 0>; +- +- trips { +- cpu_alert0: cpu_alert0 { +- temperature = <75000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu_alert1: cpu_alert1 { +- temperature = <80000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- cpu_crit: cpu_crit { +- temperature = <95000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- cooling-device = +- <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu_alert1>; +- cooling-device = +- <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- gpu_thermal: gpu-thermal { +- polling-delay-passive = <100>; /* milliseconds */ +- polling-delay = <5000>; /* milliseconds */ +- +- thermal-sensors = <&tsadc 1>; +- +- trips { +- gpu_alert0: gpu_alert0 { +- temperature = <80000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- gpu_crit: gpu_crit { +- temperature = <115000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&gpu_alert0>; +- cooling-device = +- <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- tsadc: tsadc@ff280000 { +- compatible = "rockchip,rk3368-tsadc"; +- reg = <0x0 0xff280000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; +- clock-names = "tsadc", "apb_pclk"; +- resets = <&cru SRST_TSADC>; +- reset-names = "tsadc-apb"; +- pinctrl-names = "init", "default", "sleep"; +- pinctrl-0 = <&otp_pin>; +- pinctrl-1 = <&otp_out>; +- pinctrl-2 = <&otp_pin>; +- #thermal-sensor-cells = <1>; +- rockchip,hw-tshut-temp = <95000>; +- status = "disabled"; +- }; +- +- gmac: ethernet@ff290000 { +- compatible = "rockchip,rk3368-gmac"; +- reg = <0x0 0xff290000 0x0 0x10000>; +- interrupts = ; +- interrupt-names = "macirq"; +- rockchip,grf = <&grf>; +- clocks = <&cru SCLK_MAC>, +- <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, +- <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, +- <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; +- clock-names = "stmmaceth", +- "mac_clk_rx", "mac_clk_tx", +- "clk_mac_ref", "clk_mac_refout", +- "aclk_mac", "pclk_mac"; +- status = "disabled"; +- }; +- +- usb_host0_ehci: usb@ff500000 { +- compatible = "generic-ehci"; +- reg = <0x0 0xff500000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru HCLK_HOST0>; +- status = "disabled"; +- }; +- +- usb_otg: usb@ff580000 { +- compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", +- "snps,dwc2"; +- reg = <0x0 0xff580000 0x0 0x40000>; +- interrupts = ; +- clocks = <&cru HCLK_OTG0>; +- clock-names = "otg"; +- dr_mode = "otg"; +- g-np-tx-fifo-size = <16>; +- g-rx-fifo-size = <275>; +- g-tx-fifo-size = <256 128 128 64 64 32>; +- status = "disabled"; +- }; +- +- dmac_bus: dma-controller@ff600000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xff600000 0x0 0x4000>; +- interrupts = , +- ; +- #dma-cells = <1>; +- arm,pl330-broken-no-flushp; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMAC_BUS>; +- clock-names = "apb_pclk"; +- }; +- +- i2c0: i2c@ff650000 { +- compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; +- reg = <0x0 0xff650000 0x0 0x1000>; +- clocks = <&cru PCLK_I2C0>; +- clock-names = "i2c"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_xfer>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@ff660000 { +- compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; +- reg = <0x0 0xff660000 0x0 0x1000>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "i2c"; +- clocks = <&cru PCLK_I2C1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_xfer>; +- status = "disabled"; +- }; +- +- pwm0: pwm@ff680000 { +- compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; +- reg = <0x0 0xff680000 0x0 0x10>; +- #pwm-cells = <3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>; +- clocks = <&cru PCLK_PWM1>; +- status = "disabled"; +- }; +- +- pwm1: pwm@ff680010 { +- compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; +- reg = <0x0 0xff680010 0x0 0x10>; +- #pwm-cells = <3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm1_pin>; +- clocks = <&cru PCLK_PWM1>; +- status = "disabled"; +- }; +- +- pwm2: pwm@ff680020 { +- compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; +- reg = <0x0 0xff680020 0x0 0x10>; +- #pwm-cells = <3>; +- clocks = <&cru PCLK_PWM1>; +- status = "disabled"; +- }; +- +- pwm3: pwm@ff680030 { +- compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; +- reg = <0x0 0xff680030 0x0 0x10>; +- #pwm-cells = <3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm3_pin>; +- clocks = <&cru PCLK_PWM1>; +- status = "disabled"; +- }; +- +- uart2: serial@ff690000 { +- compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff690000 0x0 0x100>; +- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; +- clock-names = "baudclk", "apb_pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_xfer>; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- mbox: mbox@ff6b0000 { +- compatible = "rockchip,rk3368-mailbox"; +- reg = <0x0 0xff6b0000 0x0 0x1000>; +- interrupts = , +- , +- , +- ; +- clocks = <&cru PCLK_MAILBOX>; +- clock-names = "pclk_mailbox"; +- #mbox-cells = <1>; +- status = "disabled"; +- }; +- +- pmugrf: syscon@ff738000 { +- compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd"; +- reg = <0x0 0xff738000 0x0 0x1000>; +- +- pmu_io_domains: io-domains { +- compatible = "rockchip,rk3368-pmu-io-voltage-domain"; +- status = "disabled"; +- }; +- +- reboot-mode { +- compatible = "syscon-reboot-mode"; +- offset = <0x200>; +- mode-normal = ; +- mode-recovery = ; +- mode-bootloader = ; +- mode-loader = ; +- }; +- }; +- +- cru: clock-controller@ff760000 { +- compatible = "rockchip,rk3368-cru"; +- reg = <0x0 0xff760000 0x0 0x1000>; +- rockchip,grf = <&grf>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- grf: syscon@ff770000 { +- compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd"; +- reg = <0x0 0xff770000 0x0 0x1000>; +- +- io_domains: io-domains { +- compatible = "rockchip,rk3368-io-voltage-domain"; +- status = "disabled"; +- }; +- }; +- +- wdt: watchdog@ff800000 { +- compatible = "rockchip,rk3368-wdt", "snps,dw-wdt"; +- reg = <0x0 0xff800000 0x0 0x100>; +- clocks = <&cru PCLK_WDT>; +- interrupts = ; +- status = "disabled"; +- }; +- +- timer0: timer@ff810000 { +- compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; +- reg = <0x0 0xff810000 0x0 0x20>; +- interrupts = ; +- clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; +- clock-names = "pclk", "timer"; +- }; +- +- spdif: spdif@ff880000 { +- compatible = "rockchip,rk3368-spdif"; +- reg = <0x0 0xff880000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; +- clock-names = "mclk", "hclk"; +- dmas = <&dmac_bus 3>; +- dma-names = "tx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spdif_tx>; +- status = "disabled"; +- }; +- +- i2s_2ch: i2s-2ch@ff890000 { +- compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; +- reg = <0x0 0xff890000 0x0 0x1000>; +- interrupts = ; +- clock-names = "i2s_clk", "i2s_hclk"; +- clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>; +- dmas = <&dmac_bus 6>, <&dmac_bus 7>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- +- i2s_8ch: i2s-8ch@ff898000 { +- compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; +- reg = <0x0 0xff898000 0x0 0x1000>; +- interrupts = ; +- clock-names = "i2s_clk", "i2s_hclk"; +- clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>; +- dmas = <&dmac_bus 0>, <&dmac_bus 1>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s_8ch_bus>; +- status = "disabled"; +- }; +- +- iep_mmu: iommu@ff900800 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff900800 0x0 0x100>; +- interrupts = ; +- interrupt-names = "iep_mmu"; +- clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- isp_mmu: iommu@ff914000 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff914000 0x0 0x100>, +- <0x0 0xff915000 0x0 0x100>; +- interrupts = ; +- interrupt-names = "isp_mmu"; +- clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- rockchip,disable-mmu-reset; +- status = "disabled"; +- }; +- +- vop_mmu: iommu@ff930300 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff930300 0x0 0x100>; +- interrupts = ; +- interrupt-names = "vop_mmu"; +- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- hevc_mmu: iommu@ff9a0440 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff9a0440 0x0 0x40>, +- <0x0 0xff9a0480 0x0 0x40>; +- interrupts = ; +- interrupt-names = "hevc_mmu"; +- clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- vpu_mmu: iommu@ff9a0800 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff9a0800 0x0 0x100>; +- interrupts = , +- ; +- interrupt-names = "vepu_mmu", "vdpu_mmu"; +- clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- efuse256: efuse@ffb00000 { +- compatible = "rockchip,rk3368-efuse"; +- reg = <0x0 0xffb00000 0x0 0x20>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&cru PCLK_EFUSE256>; +- clock-names = "pclk_efuse"; +- +- cpu_leakage: cpu-leakage@17 { +- reg = <0x17 0x1>; +- }; +- temp_adjust: temp-adjust@1f { +- reg = <0x1f 0x1>; +- }; +- }; +- +- gic: interrupt-controller@ffb71000 { +- compatible = "arm,gic-400"; +- interrupt-controller; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- +- reg = <0x0 0xffb71000 0x0 0x1000>, +- <0x0 0xffb72000 0x0 0x2000>, +- <0x0 0xffb74000 0x0 0x2000>, +- <0x0 0xffb76000 0x0 0x2000>; +- interrupts = ; +- }; +- +- pinctrl: pinctrl { +- compatible = "rockchip,rk3368-pinctrl"; +- rockchip,grf = <&grf>; +- rockchip,pmu = <&pmugrf>; +- #address-cells = <0x2>; +- #size-cells = <0x2>; +- ranges; +- +- gpio0: gpio0@ff750000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff750000 0x0 0x100>; +- clocks = <&cru PCLK_GPIO0>; +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <0x2>; +- +- interrupt-controller; +- #interrupt-cells = <0x2>; +- }; +- +- gpio1: gpio1@ff780000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff780000 0x0 0x100>; +- clocks = <&cru PCLK_GPIO1>; +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <0x2>; +- +- interrupt-controller; +- #interrupt-cells = <0x2>; +- }; +- +- gpio2: gpio2@ff790000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff790000 0x0 0x100>; +- clocks = <&cru PCLK_GPIO2>; +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <0x2>; +- +- interrupt-controller; +- #interrupt-cells = <0x2>; +- }; +- +- gpio3: gpio3@ff7a0000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff7a0000 0x0 0x100>; +- clocks = <&cru PCLK_GPIO3>; +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <0x2>; +- +- interrupt-controller; +- #interrupt-cells = <0x2>; +- }; +- +- pcfg_pull_up: pcfg-pull-up { +- bias-pull-up; +- }; +- +- pcfg_pull_down: pcfg-pull-down { +- bias-pull-down; +- }; +- +- pcfg_pull_none: pcfg-pull-none { +- bias-disable; +- }; +- +- pcfg_pull_none_12ma: pcfg-pull-none-12ma { +- bias-disable; +- drive-strength = <12>; +- }; +- +- emmc { +- emmc_clk: emmc-clk { +- rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; +- }; +- +- emmc_cmd: emmc-cmd { +- rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>; +- }; +- +- emmc_pwr: emmc-pwr { +- rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>; +- }; +- +- emmc_bus1: emmc-bus1 { +- rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>; +- }; +- +- emmc_bus4: emmc-bus4 { +- rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, +- <1 RK_PC3 2 &pcfg_pull_up>, +- <1 RK_PC4 2 &pcfg_pull_up>, +- <1 RK_PC5 2 &pcfg_pull_up>; +- }; +- +- emmc_bus8: emmc-bus8 { +- rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, +- <1 RK_PC3 2 &pcfg_pull_up>, +- <1 RK_PC4 2 &pcfg_pull_up>, +- <1 RK_PC5 2 &pcfg_pull_up>, +- <1 RK_PC6 2 &pcfg_pull_up>, +- <1 RK_PC7 2 &pcfg_pull_up>, +- <1 RK_PD0 2 &pcfg_pull_up>, +- <1 RK_PD1 2 &pcfg_pull_up>; +- }; +- }; +- +- gmac { +- rgmii_pins: rgmii-pins { +- rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, +- <3 RK_PD0 1 &pcfg_pull_none>, +- <3 RK_PC3 1 &pcfg_pull_none>, +- <3 RK_PB0 1 &pcfg_pull_none_12ma>, +- <3 RK_PB1 1 &pcfg_pull_none_12ma>, +- <3 RK_PB2 1 &pcfg_pull_none_12ma>, +- <3 RK_PB6 1 &pcfg_pull_none_12ma>, +- <3 RK_PD4 1 &pcfg_pull_none_12ma>, +- <3 RK_PB5 1 &pcfg_pull_none_12ma>, +- <3 RK_PB7 1 &pcfg_pull_none>, +- <3 RK_PC0 1 &pcfg_pull_none>, +- <3 RK_PC1 1 &pcfg_pull_none>, +- <3 RK_PC2 1 &pcfg_pull_none>, +- <3 RK_PD1 1 &pcfg_pull_none>, +- <3 RK_PC4 1 &pcfg_pull_none>; +- }; +- +- rmii_pins: rmii-pins { +- rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, +- <3 RK_PD0 1 &pcfg_pull_none>, +- <3 RK_PC3 1 &pcfg_pull_none>, +- <3 RK_PB0 1 &pcfg_pull_none_12ma>, +- <3 RK_PB1 1 &pcfg_pull_none_12ma>, +- <3 RK_PB5 1 &pcfg_pull_none_12ma>, +- <3 RK_PB7 1 &pcfg_pull_none>, +- <3 RK_PC0 1 &pcfg_pull_none>, +- <3 RK_PC4 1 &pcfg_pull_none>, +- <3 RK_PC5 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c0 { +- i2c0_xfer: i2c0-xfer { +- rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, +- <0 RK_PA7 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c1 { +- i2c1_xfer: i2c1-xfer { +- rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>, +- <2 RK_PC6 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c2 { +- i2c2_xfer: i2c2-xfer { +- rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>, +- <3 RK_PD7 2 &pcfg_pull_none>; +- }; +- }; +- +- i2c3 { +- i2c3_xfer: i2c3-xfer { +- rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, +- <1 RK_PC1 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c4 { +- i2c4_xfer: i2c4-xfer { +- rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, +- <3 RK_PD1 2 &pcfg_pull_none>; +- }; +- }; +- +- i2c5 { +- i2c5_xfer: i2c5-xfer { +- rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>, +- <3 RK_PD3 2 &pcfg_pull_none>; +- }; +- }; +- +- i2s { +- i2s_8ch_bus: i2s-8ch-bus { +- rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, +- <2 RK_PB5 1 &pcfg_pull_none>, +- <2 RK_PB6 1 &pcfg_pull_none>, +- <2 RK_PB7 1 &pcfg_pull_none>, +- <2 RK_PC0 1 &pcfg_pull_none>, +- <2 RK_PC1 1 &pcfg_pull_none>, +- <2 RK_PC2 1 &pcfg_pull_none>, +- <2 RK_PC3 1 &pcfg_pull_none>, +- <2 RK_PC4 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm0 { +- pwm0_pin: pwm0-pin { +- rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>; +- }; +- }; +- +- pwm1 { +- pwm1_pin: pwm1-pin { +- rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>; +- }; +- }; +- +- pwm3 { +- pwm3_pin: pwm3-pin { +- rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>; +- }; +- }; +- +- sdio0 { +- sdio0_bus1: sdio0-bus1 { +- rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>; +- }; +- +- sdio0_bus4: sdio0-bus4 { +- rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>, +- <2 RK_PD5 1 &pcfg_pull_up>, +- <2 RK_PD6 1 &pcfg_pull_up>, +- <2 RK_PD7 1 &pcfg_pull_up>; +- }; +- +- sdio0_cmd: sdio0-cmd { +- rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>; +- }; +- +- sdio0_clk: sdio0-clk { +- rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; +- }; +- +- sdio0_cd: sdio0-cd { +- rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>; +- }; +- +- sdio0_wp: sdio0-wp { +- rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>; +- }; +- +- sdio0_pwr: sdio0-pwr { +- rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>; +- }; +- +- sdio0_bkpwr: sdio0-bkpwr { +- rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>; +- }; +- +- sdio0_int: sdio0-int { +- rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>; +- }; +- }; +- +- sdmmc { +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; +- }; +- +- sdmmc_cd: sdmmc-cd { +- rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; +- }; +- +- sdmmc_bus1: sdmmc-bus1 { +- rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>; +- }; +- +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>, +- <2 RK_PA6 1 &pcfg_pull_up>, +- <2 RK_PA7 1 &pcfg_pull_up>, +- <2 RK_PB0 1 &pcfg_pull_up>; +- }; +- }; +- +- spdif { +- spdif_tx: spdif-tx { +- rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; +- }; +- }; +- +- spi0 { +- spi0_clk: spi0-clk { +- rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>; +- }; +- spi0_cs0: spi0-cs0 { +- rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>; +- }; +- spi0_cs1: spi0-cs1 { +- rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>; +- }; +- spi0_tx: spi0-tx { +- rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>; +- }; +- spi0_rx: spi0-rx { +- rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>; +- }; +- }; +- +- spi1 { +- spi1_clk: spi1-clk { +- rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; +- }; +- spi1_cs0: spi1-cs0 { +- rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>; +- }; +- spi1_cs1: spi1-cs1 { +- rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>; +- }; +- spi1_rx: spi1-rx { +- rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>; +- }; +- spi1_tx: spi1-tx { +- rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>; +- }; +- }; +- +- spi2 { +- spi2_clk: spi2-clk { +- rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>; +- }; +- spi2_cs0: spi2-cs0 { +- rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; +- }; +- spi2_rx: spi2-rx { +- rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>; +- }; +- spi2_tx: spi2-tx { +- rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; +- }; +- }; +- +- tsadc { +- otp_pin: otp-pin { +- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- otp_out: otp-out { +- rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; +- }; +- }; +- +- uart0 { +- uart0_xfer: uart0-xfer { +- rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>, +- <2 RK_PD1 1 &pcfg_pull_none>; +- }; +- +- uart0_cts: uart0-cts { +- rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; +- }; +- +- uart0_rts: uart0-rts { +- rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; +- }; +- }; +- +- uart1 { +- uart1_xfer: uart1-xfer { +- rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>, +- <0 RK_PC5 3 &pcfg_pull_none>; +- }; +- +- uart1_cts: uart1-cts { +- rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>; +- }; +- +- uart1_rts: uart1-rts { +- rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>; +- }; +- }; +- +- uart2 { +- uart2_xfer: uart2-xfer { +- rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>, +- <2 RK_PA5 2 &pcfg_pull_none>; +- }; +- /* no rts / cts for uart2 */ +- }; +- +- uart3 { +- uart3_xfer: uart3-xfer { +- rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>, +- <3 RK_PD6 3 &pcfg_pull_none>; +- }; +- +- uart3_cts: uart3-cts { +- rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>; +- }; +- +- uart3_rts: uart3-rts { +- rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>; +- }; +- }; +- +- uart4 { +- uart4_xfer: uart4-xfer { +- rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>, +- <0 RK_PD2 3 &pcfg_pull_none>; +- }; +- +- uart4_cts: uart4-cts { +- rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>; +- }; +- +- uart4_rts: uart4-rts { +- rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-evb.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-evb.dts +deleted file mode 100644 +index 7b717ebec8ff..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-evb.dts ++++ /dev/null +@@ -1,484 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd +- */ +- +-/dts-v1/; +-#include +-#include "rk3399.dtsi" +- +-/ { +- model = "Rockchip RK3399 Evaluation Board"; +- compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; +- +- aliases { +- mmc0 = &sdhci; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- brightness-levels = < +- 0 1 2 3 4 5 6 7 +- 8 9 10 11 12 13 14 15 +- 16 17 18 19 20 21 22 23 +- 24 25 26 27 28 29 30 31 +- 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 +- 48 49 50 51 52 53 54 55 +- 56 57 58 59 60 61 62 63 +- 64 65 66 67 68 69 70 71 +- 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 +- 88 89 90 91 92 93 94 95 +- 96 97 98 99 100 101 102 103 +- 104 105 106 107 108 109 110 111 +- 112 113 114 115 116 117 118 119 +- 120 121 122 123 124 125 126 127 +- 128 129 130 131 132 133 134 135 +- 136 137 138 139 140 141 142 143 +- 144 145 146 147 148 149 150 151 +- 152 153 154 155 156 157 158 159 +- 160 161 162 163 164 165 166 167 +- 168 169 170 171 172 173 174 175 +- 176 177 178 179 180 181 182 183 +- 184 185 186 187 188 189 190 191 +- 192 193 194 195 196 197 198 199 +- 200 201 202 203 204 205 206 207 +- 208 209 210 211 212 213 214 215 +- 216 217 218 219 220 221 222 223 +- 224 225 226 227 228 229 230 231 +- 232 233 234 235 236 237 238 239 +- 240 241 242 243 244 245 246 247 +- 248 249 250 251 252 253 254 255>; +- default-brightness-level = <200>; +- pwms = <&pwm0 0 25000 0>; +- }; +- +- edp_panel: edp-panel { +- compatible ="lg,lp079qx1-sp0v"; +- backlight = <&backlight>; +- enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; +- power-supply = <&vcc3v3_s0>; +- +- port { +- panel_in_edp: endpoint { +- remote-endpoint = <&edp_out_panel>; +- }; +- }; +- }; +- +- clkin_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "clkin_gmac"; +- #clock-cells = <0>; +- }; +- +- vdd_center: vdd-center { +- compatible = "pwm-regulator"; +- pwms = <&pwm3 0 25000 0>; +- regulator-name = "vdd_center"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- status = "okay"; +- }; +- +- vcc3v3_sys: vcc3v3-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vcc5v0_sys: vcc5v0-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- vcc5v0_host: vcc5v0-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_host_en>; +- regulator-name = "vcc5v0_host"; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc_phy: vcc-phy-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_phy"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc_phy: vcc-phy-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_phy"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +-}; +- +-&edp { +- status = "okay"; +- force-hpd; +- +- ports { +- edp_out: port@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- edp_out_panel: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_in_edp>; +- }; +- }; +- }; +-}; +- +-&emmc_phy { +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_RMII_SRC>; +- assigned-clock-parents = <&clkin_gmac>; +- clock_in_out = "input"; +- phy-supply = <&vcc_phy>; +- phy-mode = "rgmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 50000>; +- tx_delay = <0x28>; +- rx_delay = <0x11>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio1>; +- interrupts = <21 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- #clock-cells = <1>; +- clock-output-names = "rk808-clkout1", "rk808-clkout2"; +- +- vcc1-supply = <&vcc3v3_sys>; +- vcc2-supply = <&vcc3v3_sys>; +- vcc3-supply = <&vcc3v3_sys>; +- vcc4-supply = <&vcc3v3_sys>; +- vcc6-supply = <&vcc3v3_sys>; +- vcc7-supply = <&vcc3v3_sys>; +- vcc8-supply = <&vcc3v3_sys>; +- vcc9-supply = <&vcc3v3_sys>; +- vcc10-supply = <&vcc3v3_sys>; +- vcc11-supply = <&vcc3v3_sys>; +- vcc12-supply = <&vcc3v3_sys>; +- vddio-supply = <&vcc1v8_pmu>; +- +- regulators { +- vdd_log: DCDC_REG1 { +- regulator-name = "vdd_log"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <900000>; +- }; +- }; +- +- vdd_cpu_l: DCDC_REG2 { +- regulator-name = "vdd_cpu_l"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_1v8: DCDC_REG4 { +- regulator-name = "vcc_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc1v8_dvp: LDO_REG1 { +- regulator-name = "vcc1v8_dvp"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v0_tp: LDO_REG2 { +- regulator-name = "vcc3v0_tp"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc1v8_pmu: LDO_REG3 { +- regulator-name = "vcc1v8_pmu"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc_sd: LDO_REG4 { +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcca3v0_codec: LDO_REG5 { +- regulator-name = "vcca3v0_codec"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v5: LDO_REG6 { +- regulator-name = "vcc_1v5"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1500000>; +- }; +- }; +- +- vcca1v8_codec: LDO_REG7 { +- regulator-name = "vcca1v8_codec"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_3v0: LDO_REG8 { +- regulator-name = "vcc_3v0"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc3v3_s3: SWITCH_REG1 { +- regulator-name = "vcc3v3_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc3v3_s0: SWITCH_REG2 { +- regulator-name = "vcc3v3_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +- +- vdd_cpu_b: regulator@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_cpu_b"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: regulator@41 { +- compatible = "silergy,syr828"; +- reg = <0x41>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_gpu"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&pwm3 { +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- non-removable; +- status = "okay"; +-}; +- +-&pcie_phy { +- status = "disabled"; +-}; +- +-&pcie0 { +- ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; +- num-lanes = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_clkreqn_cpm>; +- status = "disabled"; +-}; +- +-&u2phy0 { +- status = "okay"; +-}; +- +-&u2phy0_host { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +-}; +- +-&u2phy1 { +- status = "okay"; +-}; +- +-&u2phy1_host { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&pinctrl { +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = +- <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- usb2 { +- vcc5v0_host_en: vcc5v0-host-en { +- rockchip,pins = +- <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-ficus.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-ficus.dts +deleted file mode 100644 +index 1ce85a5816e4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-ficus.dts ++++ /dev/null +@@ -1,170 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Collabora Ltd. +- * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. +- * +- * Schematics available at https://dl.vamrs.com/products/ficus/docs/hw +- */ +- +-/dts-v1/; +-#include "rk3399-rock960.dtsi" +- +-/ { +- model = "96boards RK3399 Ficus"; +- compatible = "vamrs,ficus", "rockchip,rk3399"; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- clkin_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "clkin_gmac"; +- #clock-cells = <0>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&user_led1_pin>, <&user_led2_pin>, +- <&user_led3_pin>, <&user_led4_pin>, +- <&wlan_led_pin>, <&bt_led_pin>; +- +- user_led1: led-1 { +- label = "red:user1"; +- gpios = <&gpio4 25 0>; +- linux,default-trigger = "heartbeat"; +- }; +- +- user_led2: led-2 { +- label = "red:user2"; +- gpios = <&gpio4 26 0>; +- linux,default-trigger = "mmc0"; +- }; +- +- user_led3: led-3 { +- label = "red:user3"; +- gpios = <&gpio4 30 0>; +- linux,default-trigger = "mmc1"; +- }; +- +- user_led4: led-4 { +- label = "red:user4"; +- gpios = <&gpio1 0 0>; +- panic-indicator; +- linux,default-trigger = "none"; +- }; +- +- wlan_active_led: led-5 { +- label = "red:wlan"; +- gpios = <&gpio1 1 0>; +- linux,default-trigger = "phy0tx"; +- default-state = "off"; +- }; +- +- bt_active_led: led-6 { +- label = "red:bt"; +- gpios = <&gpio1 4 0>; +- linux,default-trigger = "hci0-power"; +- default-state = "off"; +- }; +- }; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_RMII_SRC>; +- assigned-clock-parents = <&clkin_gmac>; +- clock_in_out = "input"; +- phy-supply = <&vcc3v3_sys>; +- phy-mode = "rgmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 50000>; +- tx_delay = <0x28>; +- rx_delay = <0x11>; +- status = "okay"; +-}; +- +-&pcie0 { +- ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; +-}; +- +-&pinctrl { +- gmac { +- rgmii_sleep_pins: rgmii-sleep-pins { +- rockchip,pins = +- <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- }; +- +- pcie { +- pcie_drv: pcie-drv { +- rockchip,pins = +- <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb2 { +- host_vbus_drv: host-vbus-drv { +- rockchip,pins = +- <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- leds { +- user_led1_pin: user-led1-pin { +- rockchip,pins = +- <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- user_led2_pin: user-led2-pin { +- rockchip,pins = +- <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- user_led3_pin: user-led3-pin { +- rockchip,pins = +- <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- user_led4_pin: user-led4-pin { +- rockchip,pins = +- <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- wlan_led_pin: wlan-led-pin { +- rockchip,pins = +- <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_led_pin: bt-led-pin { +- rockchip,pins = +- <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&spi1 { +- /* On both Low speed and High speed expansion */ +- cs-gpios = <0>, <&gpio4 RK_PA6 0>, <&gpio4 RK_PA7 0>; +- status = "okay"; +-}; +- +-&usbdrd_dwc3_0 { +- dr_mode = "host"; +-}; +- +-&usbdrd_dwc3_1 { +- dr_mode = "host"; +-}; +- +-&vcc3v3_pcie { +- gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; +-}; +- +-&vcc5v0_host { +- gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-firefly.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-firefly.dts +deleted file mode 100644 +index c4dd2a6b4836..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-firefly.dts ++++ /dev/null +@@ -1,937 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. +- */ +- +-/dts-v1/; +-#include +-#include +-#include +-#include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" +- +-/ { +- model = "Firefly-RK3399 Board"; +- compatible = "firefly,firefly-rk3399", "rockchip,rk3399"; +- +- aliases { +- mmc0 = &sdio0; +- mmc1 = &sdmmc; +- mmc2 = &sdhci; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; +- pwms = <&pwm0 0 25000 0>; +- brightness-levels = < +- 0 1 2 3 4 5 6 7 +- 8 9 10 11 12 13 14 15 +- 16 17 18 19 20 21 22 23 +- 24 25 26 27 28 29 30 31 +- 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 +- 48 49 50 51 52 53 54 55 +- 56 57 58 59 60 61 62 63 +- 64 65 66 67 68 69 70 71 +- 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 +- 88 89 90 91 92 93 94 95 +- 96 97 98 99 100 101 102 103 +- 104 105 106 107 108 109 110 111 +- 112 113 114 115 116 117 118 119 +- 120 121 122 123 124 125 126 127 +- 128 129 130 131 132 133 134 135 +- 136 137 138 139 140 141 142 143 +- 144 145 146 147 148 149 150 151 +- 152 153 154 155 156 157 158 159 +- 160 161 162 163 164 165 166 167 +- 168 169 170 171 172 173 174 175 +- 176 177 178 179 180 181 182 183 +- 184 185 186 187 188 189 190 191 +- 192 193 194 195 196 197 198 199 +- 200 201 202 203 204 205 206 207 +- 208 209 210 211 212 213 214 215 +- 216 217 218 219 220 221 222 223 +- 224 225 226 227 228 229 230 231 +- 232 233 234 235 236 237 238 239 +- 240 241 242 243 244 245 246 247 +- 248 249 250 251 252 253 254 255>; +- default-brightness-level = <200>; +- }; +- +- clkin_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "clkin_gmac"; +- #clock-cells = <0>; +- }; +- +- dc_12v: dc-12v { +- compatible = "regulator-fixed"; +- regulator-name = "dc_12v"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwrbtn>; +- +- power { +- debounce-interval = <100>; +- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; +- label = "GPIO Key Power"; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; +- pinctrl-0 = <&ir_int>; +- pinctrl-names = "default"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&work_led_pin>, <&diy_led_pin>; +- +- work_led: led-0 { +- label = "work"; +- default-state = "on"; +- gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; +- }; +- +- diy_led: led-1 { +- label = "diy"; +- default-state = "off"; +- gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- rt5640-sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "rockchip,rt5640-codec"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,mclk-fs = <256>; +- simple-audio-card,widgets = +- "Microphone", "Mic Jack", +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "Mic Jack", "MICBIAS1", +- "IN1P", "Mic Jack", +- "Headphone Jack", "HPOL", +- "Headphone Jack", "HPOR"; +- +- simple-audio-card,cpu { +- sound-dai = <&i2s1>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&rt5640>; +- }; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&rk808 1>; +- clock-names = "ext_clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_enable_h>; +- +- /* +- * On the module itself this is one of these (depending +- * on the actual card populated): +- * - SDIO_RESET_L_WL_REG_ON +- * - PDN (power down when low) +- */ +- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; +- }; +- +- sound-dit { +- compatible = "audio-graph-card"; +- label = "SPDIF"; +- dais = <&spdif_p0>; +- }; +- +- spdif-dit { +- compatible = "linux,spdif-dit"; +- #sound-dai-cells = <0>; +- +- port { +- dit_p0_0: endpoint { +- remote-endpoint = <&spdif_p0_0>; +- }; +- }; +- }; +- +- /* switched by pmic_sleep */ +- vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc1v8_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_1v8>; +- }; +- +- vcc3v3_pcie: vcc3v3-pcie-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_pwr_en>; +- regulator-name = "vcc3v3_pcie"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&dc_12v>; +- }; +- +- vcc3v3_sys: vcc3v3-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc_sys>; +- }; +- +- /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ +- vcc5v0_host: vcc5v0-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_host_en>; +- regulator-name = "vcc5v0_host"; +- regulator-always-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc5v0_typec: vcc5v0-typec-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_typec_en>; +- regulator-name = "vcc5v0_typec"; +- regulator-always-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_sys: vcc-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&dc_12v>; +- }; +- +- vdd_log: vdd-log { +- compatible = "pwm-regulator"; +- pwms = <&pwm2 0 25000 1>; +- regulator-name = "vdd_log"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <430000>; +- regulator-max-microvolt = <1400000>; +- vin-supply = <&vcc_sys>; +- }; +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&emmc_phy { +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_RMII_SRC>; +- assigned-clock-parents = <&clkin_gmac>; +- clock_in_out = "input"; +- phy-supply = <&vcc_lan>; +- phy-mode = "rgmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 50000>; +- tx_delay = <0x28>; +- rx_delay = <0x11>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_cec>; +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- i2c-scl-rising-time-ns = <168>; +- i2c-scl-falling-time-ns = <4>; +- status = "okay"; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio1>; +- interrupts = <21 IRQ_TYPE_LEVEL_LOW>; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc6-supply = <&vcc_sys>; +- vcc7-supply = <&vcc_sys>; +- vcc8-supply = <&vcc3v3_sys>; +- vcc9-supply = <&vcc_sys>; +- vcc10-supply = <&vcc_sys>; +- vcc11-supply = <&vcc_sys>; +- vcc12-supply = <&vcc3v3_sys>; +- vddio-supply = <&vcc1v8_pmu>; +- +- regulators { +- vdd_center: DCDC_REG1 { +- regulator-name = "vdd_center"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_l: DCDC_REG2 { +- regulator-name = "vdd_cpu_l"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_1v8: DCDC_REG4 { +- regulator-name = "vcc_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc1v8_dvp: LDO_REG1 { +- regulator-name = "vcc1v8_dvp"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc2v8_dvp: LDO_REG2 { +- regulator-name = "vcc2v8_dvp"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc1v8_pmu: LDO_REG3 { +- regulator-name = "vcc1v8_pmu"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc_sdio: LDO_REG4 { +- regulator-name = "vcc_sdio"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcca3v0_codec: LDO_REG5 { +- regulator-name = "vcca3v0_codec"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v5: LDO_REG6 { +- regulator-name = "vcc_1v5"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1500000>; +- }; +- }; +- +- vcca1v8_codec: LDO_REG7 { +- regulator-name = "vcca1v8_codec"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_3v0: LDO_REG8 { +- regulator-name = "vcc_3v0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc3v3_s3: vcc_lan: SWITCH_REG1 { +- regulator-name = "vcc3v3_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v3_s0: SWITCH_REG2 { +- regulator-name = "vcc3v3_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +- +- vdd_cpu_b: regulator@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- fcs,suspend-voltage-selector = <0>; +- regulator-name = "vdd_cpu_b"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: regulator@41 { +- compatible = "silergy,syr828"; +- reg = <0x41>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_gpu"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +-}; +- +-&i2c1 { +- i2c-scl-rising-time-ns = <300>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +- +- rt5640: rt5640@1c { +- compatible = "realtek,rt5640"; +- reg = <0x1c>; +- clocks = <&cru SCLK_I2S_8CH_OUT>; +- clock-names = "mclk"; +- realtek,in1-differential; +- #sound-dai-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&rt5640_hpcon>; +- }; +-}; +- +-&i2c3 { +- i2c-scl-rising-time-ns = <450>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +-}; +- +-&i2c4 { +- i2c-scl-rising-time-ns = <600>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- +- fusb0: typec-portc@22 { +- compatible = "fcs,fusb302"; +- reg = <0x22>; +- interrupt-parent = <&gpio1>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&fusb0_int>; +- vbus-supply = <&vcc5v0_typec>; +- status = "okay"; +- +- connector { +- compatible = "usb-c-connector"; +- data-role = "host"; +- label = "USB-C"; +- op-sink-microwatt = <1000000>; +- power-role = "dual"; +- sink-pdos = +- ; +- source-pdos = +- ; +- try-power-role = "sink"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- usbc_hs: endpoint { +- remote-endpoint = +- <&u2phy0_typec_hs>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- usbc_ss: endpoint { +- remote-endpoint = +- <&tcphy0_typec_ss>; +- }; +- }; +- }; +- }; +- }; +- +- accelerometer@68 { +- compatible = "invensense,mpu6500"; +- reg = <0x68>; +- interrupt-parent = <&gpio1>; +- interrupts = ; +- }; +-}; +- +-&i2s0 { +- rockchip,playback-channels = <8>; +- rockchip,capture-channels = <8>; +- status = "okay"; +-}; +- +-&i2s1 { +- rockchip,playback-channels = <2>; +- rockchip,capture-channels = <2>; +- status = "okay"; +-}; +- +-&i2s2 { +- status = "okay"; +-}; +- +-&io_domains { +- status = "okay"; +- +- bt656-supply = <&vcc1v8_dvp>; +- audio-supply = <&vcca1v8_codec>; +- sdmmc-supply = <&vcc_sdio>; +- gpio1830-supply = <&vcc_3v0>; +-}; +- +-&pcie_phy { +- status = "okay"; +-}; +- +-&pcie0 { +- ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; +- num-lanes = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_clkreqn_cpm>; +- status = "okay"; +-}; +- +-&pmu_io_domains { +- pmu1830-supply = <&vcc_3v0>; +- status = "okay"; +-}; +- +-&pinctrl { +- buttons { +- pwrbtn: pwrbtn { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- fusb302x { +- fusb0_int: fusb0-int { +- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- ir { +- ir_int: ir-int { +- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- lcd-panel { +- lcd_panel_reset: lcd-panel-reset { +- rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- leds { +- work_led_pin: work-led-pin { +- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- diy_led_pin: diy-led-pin { +- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pcie { +- pcie_pwr_en: pcie-pwr-en { +- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- pcie_3g_drv: pcie-3g-drv { +- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- vsel1_pin: vsel1-pin { +- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- vsel2_pin: vsel2-pin { +- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- rt5640 { +- rt5640_hpcon: rt5640-hpcon { +- rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdio-pwrseq { +- wifi_enable_h: wifi-enable-h { +- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb-typec { +- vcc5v0_typec_en: vcc5v0_typec_en { +- rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- usb2 { +- vcc5v0_host_en: vcc5v0-host-en { +- rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- wifi { +- wifi_host_wake_l: wifi-host-wake-l { +- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vcca1v8_s3>; +- status = "okay"; +-}; +- +-&sdio0 { +- /* WiFi & BT combo module Ampak AP6356S */ +- bus-width = <4>; +- cap-sdio-irq; +- cap-sd-highspeed; +- keep-power-in-suspend; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; +- sd-uhs-sdr104; +- +- /* Power supply */ +- vqmmc-supply = &vcc1v8_s3; /* IO line */ +- vmmc-supply = &vcc_sdio; /* card's power */ +- +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- interrupt-names = "host-wake"; +- brcm,drive-strength = <5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_host_wake_l>; +- }; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; +- disable-wp; +- max-frequency = <150000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- non-removable; +- status = "okay"; +-}; +- +-&spdif { +- pinctrl-0 = <&spdif_bus_1>; +- status = "okay"; +- +- spdif_p0: port { +- spdif_p0_0: endpoint { +- remote-endpoint = <&dit_p0_0>; +- }; +- }; +-}; +- +-&tcphy0 { +- status = "okay"; +-}; +- +-&tcphy0_usb3 { +- port { +- tcphy0_typec_ss: endpoint { +- remote-endpoint = <&usbc_ss>; +- }; +- }; +-}; +- +-&tcphy1 { +- status = "okay"; +-}; +- +-&tsadc { +- /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-mode = <1>; +- /* tshut polarity 0:LOW 1:HIGH */ +- rockchip,hw-tshut-polarity = <1>; +- status = "okay"; +-}; +- +-&u2phy0 { +- status = "okay"; +- +- u2phy0_otg: otg-port { +- status = "okay"; +- }; +- +- u2phy0_host: host-port { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +- }; +- +- port { +- u2phy0_typec_hs: endpoint { +- remote-endpoint = <&usbc_hs>; +- }; +- }; +-}; +- +-&u2phy1 { +- status = "okay"; +- +- u2phy1_otg: otg-port { +- status = "okay"; +- }; +- +- u2phy1_host: host-port { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts>; +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&usbdrd3_0 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_0 { +- status = "okay"; +- dr_mode = "otg"; +-}; +- +-&usbdrd3_1 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_1 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru-bob.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru-bob.dts +deleted file mode 100644 +index e6c1c94c8d69..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru-bob.dts ++++ /dev/null +@@ -1,89 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Gru-Bob Rev 4+ board device tree source +- * +- * Copyright 2018 Google, Inc +- */ +- +-/dts-v1/; +-#include "rk3399-gru-chromebook.dtsi" +- +-/ { +- model = "Google Bob"; +- compatible = "google,bob-rev13", "google,bob-rev12", +- "google,bob-rev11", "google,bob-rev10", +- "google,bob-rev9", "google,bob-rev8", +- "google,bob-rev7", "google,bob-rev6", +- "google,bob-rev5", "google,bob-rev4", +- "google,bob", "google,gru", "rockchip,rk3399"; +- +- edp_panel: edp-panel { +- compatible = "boe,nv101wxmn51"; +- backlight = <&backlight>; +- power-supply = <&pp3300_disp>; +- +- port { +- panel_in_edp: endpoint { +- remote-endpoint = <&edp_out_panel>; +- }; +- }; +- }; +-}; +- +-&ap_i2c_ts { +- touchscreen: touchscreen@10 { +- compatible = "elan,ekth3500"; +- reg = <0x10>; +- interrupt-parent = <&gpio3>; +- interrupts = <13 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&touch_int_l &touch_reset_l>; +- reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&ap_i2c_tp { +- trackpad: trackpad@15 { +- compatible = "elan,ekth3000"; +- reg = <0x15>; +- interrupt-parent = <&gpio1>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&trackpad_int_l>; +- wakeup-source; +- }; +-}; +- +-&backlight { +- pwms = <&cros_ec_pwm 0>; +-}; +- +-&cpu_alert0 { +- temperature = <65000>; +-}; +- +-&cpu_alert1 { +- temperature = <70000>; +-}; +- +-&spi0 { +- status = "okay"; +- +- cr50@0 { +- compatible = "google,cr50"; +- reg = <0>; +- interrupt-parent = <&gpio0>; +- interrupts = <5 IRQ_TYPE_EDGE_RISING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&h1_int_od_l>; +- spi-max-frequency = <800000>; +- }; +-}; +- +-&pinctrl { +- tpm { +- h1_int_od_l: h1-int-od-l { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru-chromebook.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru-chromebook.dtsi +deleted file mode 100644 +index 1384dabbdf40..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru-chromebook.dtsi ++++ /dev/null +@@ -1,400 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Gru-Chromebook shared properties +- * +- * Copyright 2018 Google, Inc +- */ +- +-#include "rk3399-gru.dtsi" +- +-/ { +- pp900_ap: pp900-ap { +- compatible = "regulator-fixed"; +- regulator-name = "pp900_ap"; +- +- /* EC turns on w/ pp900_ap_en; always on for AP */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- +- vin-supply = <&ppvar_sys>; +- }; +- +- /* EC turns on w/ pp900_usb_en */ +- pp900_usb: pp900-ap { +- }; +- +- /* EC turns on w/ pp900_pcie_en */ +- pp900_pcie: pp900-ap { +- }; +- +- pp3000: pp3000 { +- compatible = "regulator-fixed"; +- regulator-name = "pp3000"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pp3000_en>; +- +- enable-active-high; +- gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; +- +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- +- vin-supply = <&ppvar_sys>; +- }; +- +- ppvar_centerlogic_pwm: ppvar-centerlogic-pwm { +- compatible = "pwm-regulator"; +- regulator-name = "ppvar_centerlogic_pwm"; +- +- pwms = <&pwm3 0 3337 0>; +- pwm-supply = <&ppvar_sys>; +- pwm-dutycycle-range = <100 0>; +- pwm-dutycycle-unit = <100>; +- +- /* EC turns on w/ ppvar_centerlogic_en; always on for AP */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <799434>; +- regulator-max-microvolt = <1049925>; +- }; +- +- ppvar_centerlogic: ppvar-centerlogic { +- compatible = "vctrl-regulator"; +- regulator-name = "ppvar_centerlogic"; +- +- regulator-min-microvolt = <799434>; +- regulator-max-microvolt = <1049925>; +- +- ctrl-supply = <&ppvar_centerlogic_pwm>; +- ctrl-voltage-range = <799434 1049925>; +- +- regulator-settling-time-up-us = <378>; +- min-slew-down-rate = <225>; +- ovp-threshold-percent = <16>; +- }; +- +- /* Schematics call this PPVAR even though it's fixed */ +- ppvar_logic: ppvar-logic { +- compatible = "regulator-fixed"; +- regulator-name = "ppvar_logic"; +- +- /* EC turns on w/ ppvar_logic_en; always on for AP */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- +- vin-supply = <&ppvar_sys>; +- }; +- +- pp1800_audio: pp1800-audio { +- compatible = "regulator-fixed"; +- regulator-name = "pp1800_audio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pp1800_audio_en>; +- +- enable-active-high; +- gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; +- +- regulator-always-on; +- regulator-boot-on; +- +- vin-supply = <&pp1800>; +- }; +- +- /* gpio is shared with pp3300_wifi_bt */ +- pp1800_pcie: pp1800-pcie { +- compatible = "regulator-fixed"; +- regulator-name = "pp1800_pcie"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_module_pd_l>; +- +- enable-active-high; +- gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; +- +- /* +- * Need to wait 1ms + ramp-up time before we can power on WiFi. +- * This has been approximated as 8ms total. +- */ +- regulator-enable-ramp-delay = <8000>; +- +- vin-supply = <&pp1800>; +- }; +- +- /* Always on; plain and simple */ +- pp3000_ap: pp3000_emmc: pp3000 { +- }; +- +- pp1500_ap_io: pp1500-ap-io { +- compatible = "regulator-fixed"; +- regulator-name = "pp1500_ap_io"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pp1500_en>; +- +- enable-active-high; +- gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; +- +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- +- vin-supply = <&pp1800>; +- }; +- +- pp3300_disp: pp3300-disp { +- compatible = "regulator-fixed"; +- regulator-name = "pp3300_disp"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pp3300_disp_en>; +- +- enable-active-high; +- gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; +- +- startup-delay-us = <2000>; +- vin-supply = <&pp3300>; +- }; +- +- /* EC turns on w/ pp3300_usb_en_l */ +- pp3300_usb: pp3300 { +- }; +- +- /* gpio is shared with pp1800_pcie and pinctrl is set there */ +- pp3300_wifi_bt: pp3300-wifi-bt { +- compatible = "regulator-fixed"; +- regulator-name = "pp3300_wifi_bt"; +- +- enable-active-high; +- gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; +- +- vin-supply = <&pp3300>; +- }; +- +- /* +- * This is a bit of a hack. The WiFi module should be reset at least +- * 1ms after its regulators have ramped up (max rampup time is ~7ms). +- * With some stretching of the imagination, we can call the 1.8V +- * regulator a supply. +- */ +- wlan_pd_n: wlan-pd-n { +- compatible = "regulator-fixed"; +- regulator-name = "wlan_pd_n"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_module_reset_l>; +- +- enable-active-high; +- gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; +- +- vin-supply = <&pp1800_pcie>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; +- power-supply = <&pp3300_disp>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bl_en>; +- pwm-delay-us = <10000>; +- }; +- +- gpio_keys: gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_host_wake_l>; +- +- wake_on_bt: wake-on-bt { +- label = "Wake-on-Bluetooth"; +- gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- }; +- }; +-}; +- +-&ppvar_bigcpu { +- min-slew-down-rate = <225>; +- ovp-threshold-percent = <16>; +-}; +- +-&ppvar_litcpu { +- min-slew-down-rate = <225>; +- ovp-threshold-percent = <16>; +-}; +- +-&ppvar_gpu { +- min-slew-down-rate = <225>; +- ovp-threshold-percent = <16>; +-}; +- +-&cdn_dp { +- extcon = <&usbc_extcon0>, <&usbc_extcon1>; +-}; +- +-&edp { +- status = "okay"; +- +- ports { +- edp_out: port@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- edp_out_panel: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_in_edp>; +- }; +- }; +- }; +-}; +- +-ap_i2c_mic: &i2c1 { +- status = "okay"; +- +- clock-frequency = <400000>; +- +- /* These are relatively safe rise/fall times */ +- i2c-scl-falling-time-ns = <50>; +- i2c-scl-rising-time-ns = <300>; +- +- headsetcodec: rt5514@57 { +- compatible = "realtek,rt5514"; +- reg = <0x57>; +- realtek,dmic-init-delay-ms = <20>; +- }; +-}; +- +-ap_i2c_tp: &i2c5 { +- status = "okay"; +- +- clock-frequency = <400000>; +- +- /* These are relatively safe rise/fall times */ +- i2c-scl-falling-time-ns = <50>; +- i2c-scl-rising-time-ns = <300>; +- +- /* +- * Note strange pullup enable. Apparently this avoids leakage but +- * still allows us to get nice 4.7K pullups for high speed i2c +- * transfers. Basically we want the pullup on whenever the ap is +- * alive, so the "en" pin just gets set to output high. +- */ +- pinctrl-0 = <&i2c5_xfer &ap_i2c_tp_pu_en>; +-}; +- +-&cros_ec { +- cros_ec_pwm: ec-pwm { +- compatible = "google,cros-ec-pwm"; +- #pwm-cells = <1>; +- }; +- +- usbc_extcon1: extcon1 { +- compatible = "google,extcon-usbc-cros-ec"; +- google,usb-port-id = <1>; +- }; +-}; +- +-&sound { +- rockchip,codec = <&max98357a &headsetcodec +- &codec &wacky_spi_audio &cdn_dp>; +-}; +- +-&spi2 { +- wacky_spi_audio: spi2@0 { +- compatible = "realtek,rt5514"; +- reg = <0>; +- interrupt-parent = <&gpio1>; +- interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mic_int>; +- /* May run faster once verified. */ +- spi-max-frequency = <10000000>; +- wakeup-source; +- }; +-}; +- +-&pci_rootport { +- mvl_wifi: wifi@0,0 { +- compatible = "pci1b4b,2b42"; +- reg = <0x83010000 0x0 0x00000000 0x0 0x00100000 +- 0x83010000 0x0 0x00100000 0x0 0x00100000>; +- interrupt-parent = <&gpio0>; +- interrupts = <8 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_host_wake_l>; +- wakeup-source; +- }; +-}; +- +-&tcphy1 { +- status = "okay"; +- extcon = <&usbc_extcon1>; +-}; +- +-&u2phy1 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&usbdrd3_1 { +- status = "okay"; +- extcon = <&usbc_extcon1>; +-}; +- +-&usbdrd_dwc3_1 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&pinctrl { +- discrete-regulators { +- pp1500_en: pp1500-en { +- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO +- &pcfg_pull_none>; +- }; +- +- pp1800_audio_en: pp1800-audio-en { +- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO +- &pcfg_pull_down>; +- }; +- +- pp3000_en: pp3000-en { +- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO +- &pcfg_pull_none>; +- }; +- +- pp3300_disp_en: pp3300-disp-en { +- rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO +- &pcfg_pull_none>; +- }; +- +- wlan_module_pd_l: wlan-module-pd-l { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO +- &pcfg_pull_down>; +- }; +- }; +-}; +- +-&wifi { +- wifi_perst_l: wifi-perst-l { +- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- wlan_host_wake_l: wlan-host-wake-l { +- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru-kevin.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru-kevin.dts +deleted file mode 100644 +index 2bbef9fcbe27..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru-kevin.dts ++++ /dev/null +@@ -1,327 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Gru-Kevin Rev 6+ board device tree source +- * +- * Copyright 2016-2017 Google, Inc +- */ +- +-/dts-v1/; +-#include "rk3399-gru-chromebook.dtsi" +-#include +- +-/* +- * Kevin-specific things +- * +- * Things in this section should use names from Kevin schematic since no +- * equivalent exists in Gru schematic. If referring to signals that exist +- * in Gru we use the Gru names, though. Confusing enough for you? +- */ +-/ { +- model = "Google Kevin"; +- compatible = "google,kevin-rev15", "google,kevin-rev14", +- "google,kevin-rev13", "google,kevin-rev12", +- "google,kevin-rev11", "google,kevin-rev10", +- "google,kevin-rev9", "google,kevin-rev8", +- "google,kevin-rev7", "google,kevin-rev6", +- "google,kevin", "google,gru", "rockchip,rk3399"; +- +- /* Power tree */ +- +- p3_3v_dig: p3-3v-dig { +- compatible = "regulator-fixed"; +- regulator-name = "p3.3v_dig"; +- pinctrl-names = "default"; +- pinctrl-0 = <&cpu3_pen_pwr_en>; +- +- enable-active-high; +- gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; +- vin-supply = <&pp3300>; +- }; +- +- edp_panel: edp-panel { +- compatible = "sharp,lq123p1jx31"; +- backlight = <&backlight>; +- power-supply = <&pp3300_disp>; +- +- panel-timing { +- clock-frequency = <266666667>; +- hactive = <2400>; +- hfront-porch = <48>; +- hback-porch = <84>; +- hsync-len = <32>; +- hsync-active = <0>; +- vactive = <1600>; +- vfront-porch = <3>; +- vback-porch = <120>; +- vsync-len = <10>; +- vsync-active = <0>; +- }; +- +- port { +- panel_in_edp: endpoint { +- remote-endpoint = <&edp_out_panel>; +- }; +- }; +- }; +- +- thermistor_ppvar_bigcpu: thermistor-ppvar-bigcpu { +- compatible = "murata,ncp15wb473"; +- pullup-uv = <1800000>; +- pullup-ohm = <25500>; +- pulldown-ohm = <0>; +- io-channels = <&saradc 2>; +- #thermal-sensor-cells = <0>; +- }; +- +- thermistor_ppvar_litcpu: thermistor-ppvar-litcpu { +- compatible = "murata,ncp15wb473"; +- pullup-uv = <1800000>; +- pullup-ohm = <25500>; +- pulldown-ohm = <0>; +- io-channels = <&saradc 3>; +- #thermal-sensor-cells = <0>; +- }; +-}; +- +-&backlight { +- pwms = <&cros_ec_pwm 1>; +-}; +- +-&gpio_keys { +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>; +- +- pen-insert { +- label = "Pen Insert"; +- /* Insert = low, eject = high */ +- gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; +- linux,code = ; +- linux,input-type = ; +- wakeup-source; +- }; +-}; +- +-&thermal_zones { +- bigcpu_reg_thermal: bigcpu-reg-thermal { +- polling-delay-passive = <100>; /* milliseconds */ +- polling-delay = <1000>; /* milliseconds */ +- thermal-sensors = <&thermistor_ppvar_bigcpu 0>; +- sustainable-power = <4000>; +- +- ppvar_bigcpu_trips: trips { +- ppvar_bigcpu_on: ppvar-bigcpu-on { +- temperature = <40000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- +- ppvar_bigcpu_alert: ppvar-bigcpu-alert { +- temperature = <50000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- +- ppvar_bigcpu_crit: ppvar-bigcpu-crit { +- temperature = <90000>; /* millicelsius */ +- hysteresis = <0>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&ppvar_bigcpu_alert>; +- cooling-device = +- <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- contribution = <4096>; +- }; +- map1 { +- trip = <&ppvar_bigcpu_alert>; +- cooling-device = +- <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- contribution = <1024>; +- }; +- }; +- }; +- +- litcpu_reg_thermal: litcpu-reg-thermal { +- polling-delay-passive = <100>; /* milliseconds */ +- polling-delay = <1000>; /* milliseconds */ +- thermal-sensors = <&thermistor_ppvar_litcpu 0>; +- sustainable-power = <4000>; +- +- ppvar_litcpu_trips: trips { +- ppvar_litcpu_on: ppvar-litcpu-on { +- temperature = <40000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- +- ppvar_litcpu_alert: ppvar-litcpu-alert { +- temperature = <50000>; /* millicelsius */ +- hysteresis = <2000>; /* millicelsius */ +- type = "passive"; +- }; +- +- ppvar_litcpu_crit: ppvar-litcpu-crit { +- temperature = <90000>; /* millicelsius */ +- hysteresis = <0>; /* millicelsius */ +- type = "critical"; +- }; +- }; +- }; +-}; +- +-ap_i2c_tpm: &i2c0 { +- status = "okay"; +- +- clock-frequency = <400000>; +- +- /* These are relatively safe rise/fall times. */ +- i2c-scl-falling-time-ns = <50>; +- i2c-scl-rising-time-ns = <300>; +- +- tpm: tpm@20 { +- compatible = "infineon,slb9645tt"; +- reg = <0x20>; +- powered-while-suspended; +- }; +-}; +- +-ap_i2c_dig: &i2c2 { +- status = "okay"; +- +- clock-frequency = <400000>; +- +- /* These are relatively safe rise/fall times. */ +- i2c-scl-falling-time-ns = <50>; +- i2c-scl-rising-time-ns = <300>; +- +- digitizer: digitizer@9 { +- /* wacom,w9013 */ +- compatible = "hid-over-i2c"; +- reg = <0x9>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cpu1_dig_irq_l &cpu1_dig_pdct_l>; +- +- vdd-supply = <&p3_3v_dig>; +- post-power-on-delay-ms = <100>; +- +- interrupt-parent = <&gpio2>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- +- hid-descr-addr = <0x1>; +- }; +-}; +- +-/* Adjustments to things in the gru baseboard */ +- +-&ap_i2c_tp { +- trackpad@4a { +- compatible = "atmel,maxtouch"; +- reg = <0x4a>; +- pinctrl-names = "default"; +- pinctrl-0 = <&trackpad_int_l>; +- interrupt-parent = <&gpio1>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- linux,gpio-keymap = ; +- wakeup-source; +- }; +-}; +- +-&ap_i2c_ts { +- touchscreen@4b { +- compatible = "atmel,maxtouch"; +- reg = <0x4b>; +- pinctrl-names = "default"; +- pinctrl-0 = <&touch_int_l>; +- interrupt-parent = <&gpio3>; +- interrupts = <13 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&ppvar_bigcpu_pwm { +- regulator-min-microvolt = <798674>; +- regulator-max-microvolt = <1302172>; +-}; +- +-&ppvar_bigcpu { +- regulator-min-microvolt = <798674>; +- regulator-max-microvolt = <1302172>; +- ctrl-voltage-range = <798674 1302172>; +-}; +- +-&ppvar_litcpu_pwm { +- regulator-min-microvolt = <799065>; +- regulator-max-microvolt = <1303738>; +-}; +- +-&ppvar_litcpu { +- regulator-min-microvolt = <799065>; +- regulator-max-microvolt = <1303738>; +- ctrl-voltage-range = <799065 1303738>; +-}; +- +-&ppvar_gpu_pwm { +- regulator-min-microvolt = <785782>; +- regulator-max-microvolt = <1217729>; +-}; +- +-&ppvar_gpu { +- regulator-min-microvolt = <785782>; +- regulator-max-microvolt = <1217729>; +- ctrl-voltage-range = <785782 1217729>; +-}; +- +-&ppvar_centerlogic_pwm { +- regulator-min-microvolt = <800069>; +- regulator-max-microvolt = <1049692>; +-}; +- +-&ppvar_centerlogic { +- regulator-min-microvolt = <800069>; +- regulator-max-microvolt = <1049692>; +- ctrl-voltage-range = <800069 1049692>; +-}; +- +-&saradc { +- status = "okay"; +- vref-supply = <&pp1800_ap_io>; +-}; +- +-&mvl_wifi { +- marvell,wakeup-pin = <14>; /* GPIO_14 on Marvell */ +-}; +- +-&pinctrl { +- digitizer { +- /* Has external pullup */ +- cpu1_dig_irq_l: cpu1-dig-irq-l { +- rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- /* Has external pullup */ +- cpu1_dig_pdct_l: cpu1-dig-pdct-l { +- rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- discrete-regulators { +- cpu3_pen_pwr_en: cpu3-pen-pwr-en { +- rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pen { +- cpu1_pen_eject: cpu1-pen-eject { +- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru-scarlet-inx.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru-scarlet-inx.dts +deleted file mode 100644 +index 2d721a974790..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru-scarlet-inx.dts ++++ /dev/null +@@ -1,33 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Gru-Scarlet Rev4+ (SKU-6/Innolux) board device tree source +- * +- * Copyright 2018 Google, Inc +- */ +- +-/dts-v1/; +- +-#include "rk3399-gru-scarlet.dtsi" +- +-/ { +- model = "Google Scarlet"; +- compatible = "google,scarlet-rev15-sku6", "google,scarlet-rev15", +- "google,scarlet-rev14-sku6", "google,scarlet-rev14", +- "google,scarlet-rev13-sku6", "google,scarlet-rev13", +- "google,scarlet-rev12-sku6", "google,scarlet-rev12", +- "google,scarlet-rev11-sku6", "google,scarlet-rev11", +- "google,scarlet-rev10-sku6", "google,scarlet-rev10", +- "google,scarlet-rev9-sku6", "google,scarlet-rev9", +- "google,scarlet-rev8-sku6", "google,scarlet-rev8", +- "google,scarlet-rev7-sku6", "google,scarlet-rev7", +- "google,scarlet-rev6-sku6", "google,scarlet-rev6", +- "google,scarlet-rev5-sku6", "google,scarlet-rev5", +- "google,scarlet-rev4-sku6", "google,scarlet-rev4", +- "google,scarlet", "google,gru", "rockchip,rk3399"; +-}; +- +-&mipi_panel { +- compatible = "innolux,p097pfg"; +- avdd-supply = <&ppvarp_lcd>; +- avee-supply = <&ppvarn_lcd>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru-scarlet-kd.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru-scarlet-kd.dts +deleted file mode 100644 +index bd7592217270..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru-scarlet-kd.dts ++++ /dev/null +@@ -1,33 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Gru-Scarlet Rev3+ (SKU-7/Kingdisplay) board device tree source +- * +- * Copyright 2018 Google, Inc +- */ +- +-/dts-v1/; +- +-#include "rk3399-gru-scarlet.dtsi" +- +-/ { +- model = "Google Scarlet"; +- compatible = "google,scarlet-rev15-sku7", "google,scarlet-rev15", +- "google,scarlet-rev14-sku7", "google,scarlet-rev14", +- "google,scarlet-rev13-sku7", "google,scarlet-rev13", +- "google,scarlet-rev12-sku7", "google,scarlet-rev12", +- "google,scarlet-rev11-sku7", "google,scarlet-rev11", +- "google,scarlet-rev10-sku7", "google,scarlet-rev10", +- "google,scarlet-rev9-sku7", "google,scarlet-rev9", +- "google,scarlet-rev8-sku7", "google,scarlet-rev8", +- "google,scarlet-rev7-sku7", "google,scarlet-rev7", +- "google,scarlet-rev6-sku7", "google,scarlet-rev6", +- "google,scarlet-rev5-sku7", "google,scarlet-rev5", +- "google,scarlet-rev4-sku7", "google,scarlet-rev4", +- "google,scarlet-rev3-sku7", "google,scarlet-rev3", +- "google,scarlet", "google,gru", "rockchip,rk3399"; +-}; +- +-&mipi_panel { +- compatible = "kingdisplay,kd097d04"; +- power-supply = <&pp3300_s0>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru-scarlet.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru-scarlet.dtsi +deleted file mode 100644 +index 5d7a9d96d163..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru-scarlet.dtsi ++++ /dev/null +@@ -1,690 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Gru-scarlet board device tree source +- * +- * Copyright 2018 Google, Inc +- */ +- +-#include "rk3399-gru.dtsi" +- +-/{ +- /* Power tree */ +- +- /* ppvar_sys children, sorted by name */ +- pp1250_s3: pp1250-s3 { +- compatible = "regulator-fixed"; +- regulator-name = "pp1250_s3"; +- +- /* EC turns on w/ pp1250_s3_en; always on for AP */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1250000>; +- regulator-max-microvolt = <1250000>; +- +- vin-supply = <&ppvar_sys>; +- }; +- +- pp1250_cam: pp1250-dvdd { +- compatible = "regulator-fixed"; +- regulator-name = "pp1250_dvdd"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pp1250_cam_en>; +- +- enable-active-high; +- gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>; +- +- /* 740us delay from gpio output high to pp1250 stable, +- * rounding up to 1ms for safety. +- */ +- startup-delay-us = <1000>; +- vin-supply = <&pp1250_s3>; +- }; +- +- pp900_s0: pp900-s0 { +- compatible = "regulator-fixed"; +- regulator-name = "pp900_s0"; +- +- /* EC turns on w/ pp900_s0_en; always on for AP */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- +- vin-supply = <&ppvar_sys>; +- }; +- +- ppvarn_lcd: ppvarn-lcd { +- compatible = "regulator-fixed"; +- regulator-name = "ppvarn_lcd"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ppvarn_lcd_en>; +- +- enable-active-high; +- gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; +- vin-supply = <&ppvar_sys>; +- }; +- +- ppvarp_lcd: ppvarp-lcd { +- compatible = "regulator-fixed"; +- regulator-name = "ppvarp_lcd"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ppvarp_lcd_en>; +- +- enable-active-high; +- gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; +- vin-supply = <&ppvar_sys>; +- }; +- +- /* pp1800 children, sorted by name */ +- pp900_s3: pp900-s3 { +- compatible = "regulator-fixed"; +- regulator-name = "pp900_s3"; +- +- /* EC turns on w/ pp900_s3_en; always on for AP */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- +- vin-supply = <&pp1800>; +- }; +- +- /* EC turns on pp1800_s3_en */ +- pp1800_s3: pp1800 { +- }; +- +- /* pp3300 children, sorted by name */ +- pp2800_cam: pp2800-avdd { +- compatible = "regulator-fixed"; +- regulator-name = "pp2800_avdd"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pp2800_cam_en>; +- +- enable-active-high; +- gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <100>; +- vin-supply = <&pp3300>; +- }; +- +- /* EC turns on pp3300_s0_en */ +- pp3300_s0: pp3300 { +- }; +- +- /* EC turns on pp3300_s3_en */ +- pp3300_s3: pp3300 { +- }; +- +- /* +- * See b/66922012 +- * +- * This is a hack to make sure the Bluetooth part of the QCA6174A +- * is reset at boot by toggling BT_EN. At boot BT_EN is first set +- * to low when the bt_3v3 regulator is registered (in disabled +- * state). The fake regulator is configured as a supply of the +- * wlan_3v3 regulator below. When wlan_3v3 is enabled early in +- * the boot process it also enables its supply regulator bt_3v3, +- * which changes BT_EN to high. +- */ +- bt_3v3: bt-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "bt_3v3"; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_en_1v8_l>; +- +- enable-active-high; +- gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; +- vin-supply = <&pp3300_s3>; +- }; +- +- wlan_3v3: wlan-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "wlan_3v3"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wlan_pd_1v8_l>; +- +- /* +- * The WL_EN pin is driven low when the regulator is +- * registered, and transitions to high when the PCIe bus +- * is powered up. +- */ +- enable-active-high; +- gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; +- +- /* +- * Require minimum 10ms from power-on (e.g., PD#) to init PCIe. +- * TODO (b/64444991): how long to assert PD#? +- */ +- regulator-enable-ramp-delay = <10000>; +- /* See bt_3v3 hack above */ +- vin-supply = <&bt_3v3>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- enable-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bl_en>; +- pwms = <&pwm1 0 1000000 0>; +- pwm-delay-us = <10000>; +- }; +- +- dmic: dmic { +- compatible = "dmic-codec"; +- dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&dmic_en>; +- wakeup-delay-ms = <250>; +- }; +- +- gpio_keys: gpio-keys { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pen_eject_odl>; +- +- pen-insert { +- label = "Pen Insert"; +- /* Insert = low, eject = high */ +- gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- linux,input-type = ; +- wakeup-source; +- }; +- }; +-}; +- +-/* pp900_s0 aliases */ +-pp900_ddrpll_ap: &pp900_s0 { +-}; +-pp900_pcie: &pp900_s0 { +-}; +-pp900_usb: &pp900_s0 { +-}; +- +-/* pp900_s3 aliases */ +-pp900_emmcpll: &pp900_s3 { +-}; +- +-/* EC turns on; alias for pp1800_s0 */ +-pp1800_pcie: &pp1800_s0 { +-}; +- +-/* On scarlet PPVAR(big_cpu, lit_cpu, gpu) need to adjust voltage ranges */ +-&ppvar_bigcpu { +- ctrl-voltage-range = <800074 1299226>; +- regulator-min-microvolt = <800074>; +- regulator-max-microvolt = <1299226>; +-}; +- +-&ppvar_bigcpu_pwm { +- /* On scarlet ppvar big cpu use pwm3 */ +- pwms = <&pwm3 0 3337 0>; +- regulator-min-microvolt = <800074>; +- regulator-max-microvolt = <1299226>; +-}; +- +-&ppvar_litcpu { +- ctrl-voltage-range = <802122 1199620>; +- regulator-min-microvolt = <802122>; +- regulator-max-microvolt = <1199620>; +-}; +- +-&ppvar_litcpu_pwm { +- regulator-min-microvolt = <802122>; +- regulator-max-microvolt = <1199620>; +-}; +- +-&ppvar_gpu { +- ctrl-voltage-range = <799600 1099600>; +- regulator-min-microvolt = <799600>; +- regulator-max-microvolt = <1099600>; +-}; +- +-&ppvar_gpu_pwm { +- regulator-min-microvolt = <799600>; +- regulator-max-microvolt = <1099600>; +-}; +- +-&ppvar_sd_card_io { +- states = <1800000 0x0>, <3300000 0x1>; +- regulator-max-microvolt = <3300000>; +-}; +- +-&pp3000_sd_slot { +- vin-supply = <&pp3300>; +-}; +- +-ap_i2c_dig: &i2c2 { +- status = "okay"; +- +- clock-frequency = <400000>; +- +- /* These are relatively safe rise/fall times. */ +- i2c-scl-falling-time-ns = <50>; +- i2c-scl-rising-time-ns = <300>; +- +- digitizer: digitizer@9 { +- compatible = "hid-over-i2c"; +- reg = <0x9>; +- interrupt-parent = <&gpio1>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- hid-descr-addr = <0x1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pen_int_odl &pen_reset_l>; +- }; +-}; +- +-&ap_i2c_ts { +- touchscreen: touchscreen@10 { +- compatible = "elan,ekth3500"; +- reg = <0x10>; +- interrupt-parent = <&gpio1>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&touch_int_l &touch_reset_l>; +- reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-camera: &i2c7 { +- status = "okay"; +- +- clock-frequency = <400000>; +- +- /* These are relatively safe rise/fall times; TODO: measure */ +- i2c-scl-falling-time-ns = <50>; +- i2c-scl-rising-time-ns = <300>; +- +- /* 24M mclk is shared between world and user cameras */ +- pinctrl-0 = <&i2c7_xfer &test_clkout1>; +- +- /* Rear-facing camera */ +- wcam: camera@36 { +- compatible = "ovti,ov5695"; +- reg = <0x36>; +- pinctrl-names = "default"; +- pinctrl-0 = <&wcam_rst>; +- +- clocks = <&cru SCLK_TESTCLKOUT1>; +- clock-names = "xvclk"; +- +- avdd-supply = <&pp2800_cam>; +- dvdd-supply = <&pp1250_cam>; +- dovdd-supply = <&pp1800_s0>; +- reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; +- +- port { +- wcam_out: endpoint { +- remote-endpoint = <&mipi_in_wcam>; +- data-lanes = <1 2>; +- }; +- }; +- }; +- +- /* Front-facing camera */ +- ucam: camera@3c { +- compatible = "ovti,ov2685"; +- reg = <0x3c>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ucam_rst>; +- +- clocks = <&cru SCLK_TESTCLKOUT1>; +- clock-names = "xvclk"; +- +- avdd-supply = <&pp2800_cam>; +- dovdd-supply = <&pp1800_s0>; +- dvdd-supply = <&pp1800_s0>; +- reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; +- +- port { +- ucam_out: endpoint { +- remote-endpoint = <&mipi_in_ucam>; +- data-lanes = <1>; +- }; +- }; +- }; +-}; +- +-&cdn_dp { +- extcon = <&usbc_extcon0>; +- phys = <&tcphy0_dp>; +-}; +- +-&cpu_alert0 { +- temperature = <66000>; +-}; +- +-&cpu_alert1 { +- temperature = <71000>; +-}; +- +-&cros_ec { +- interrupt-parent = <&gpio1>; +- interrupts = <18 IRQ_TYPE_LEVEL_LOW>; +-}; +- +-&cru { +- assigned-clocks = +- <&cru PLL_GPLL>, <&cru PLL_CPLL>, +- <&cru PLL_NPLL>, +- <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, +- <&cru PCLK_PERIHP>, +- <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, +- <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, +- <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, +- <&cru ACLK_VIO>, +- <&cru ACLK_GIC_PRE>, +- <&cru PCLK_DDR>, +- <&cru ACLK_HDCP>; +- assigned-clock-rates = +- <600000000>, <1600000000>, +- <1000000000>, +- <150000000>, <75000000>, +- <37500000>, +- <100000000>, <100000000>, +- <50000000>, <800000000>, +- <100000000>, <50000000>, +- <400000000>, +- <200000000>, +- <200000000>, +- <400000000>; +-}; +- +-&i2c_tunnel { +- google,remote-bus = <0>; +-}; +- +-&io_domains { +- bt656-supply = <&pp1800_s0>; /* APIO2_VDD; 2a 2b */ +- audio-supply = <&pp1800_s0>; /* APIO5_VDD; 3d 4a */ +- gpio1830-supply = <&pp1800_s0>; /* APIO4_VDD; 4c 4d */ +-}; +- +-&isp0 { +- status = "okay"; +- +- ports { +- port@0 { +- mipi_in_wcam: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&wcam_out>; +- data-lanes = <1 2>; +- }; +- +- mipi_in_ucam: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&ucam_out>; +- data-lanes = <1>; +- }; +- }; +- }; +-}; +- +-&isp0_mmu { +- status = "okay"; +-}; +- +-&max98357a { +- sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; +-}; +- +-&mipi_dphy_rx0 { +- status = "okay"; +-}; +- +-&mipi_dsi { +- status = "okay"; +- clock-master; +- +- ports { +- mipi_out: port@1 { +- reg = <1>; +- +- mipi_out_panel: endpoint { +- remote-endpoint = <&mipi_in_panel>; +- }; +- }; +- }; +- +- mipi_panel: panel@0 { +- /* 2 different panels are used, compatibles are in dts files */ +- reg = <0>; +- backlight = <&backlight>; +- enable-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&display_rst_l>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- mipi_in_panel: endpoint { +- remote-endpoint = <&mipi_out_panel>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- mipi1_in_panel: endpoint@1 { +- remote-endpoint = <&mipi1_out_panel>; +- }; +- }; +- }; +- }; +-}; +- +-&mipi_dsi1 { +- status = "okay"; +- +- ports { +- mipi1_out: port@1 { +- reg = <1>; +- +- mipi1_out_panel: endpoint { +- remote-endpoint = <&mipi1_in_panel>; +- }; +- }; +- }; +-}; +- +-&pcie0 { +- ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; +- +- /* PERST# asserted in S3 */ +- pcie-reset-suspend = <1>; +- +- vpcie3v3-supply = <&wlan_3v3>; +- vpcie1v8-supply = <&pp1800_pcie>; +-}; +- +-&sdmmc { +- cd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; +-}; +- +-&sound { +- rockchip,codec = <&max98357a &dmic &codec &cdn_dp>; +-}; +- +-&spi2 { +- status = "okay"; +- +- cr50@0 { +- compatible = "google,cr50"; +- reg = <0>; +- interrupt-parent = <&gpio1>; +- interrupts = <17 IRQ_TYPE_EDGE_RISING>; +- pinctrl-names = "default"; +- pinctrl-0 = <&h1_int_od_l>; +- spi-max-frequency = <800000>; +- }; +-}; +- +-&usb_host0_ohci { +- #address-cells = <1>; +- #size-cells = <0>; +- +- qca_bt: bluetooth@1 { +- compatible = "usbcf3,e300", "usb4ca,301a"; +- reg = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_host_wake_l>; +- interrupt-parent = <&gpio1>; +- interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "wakeup"; +- }; +-}; +- +-/* PINCTRL OVERRIDES */ +-&ec_ap_int_l { +- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; +-}; +- +-&ap_fw_wp { +- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; +-}; +- +-&bl_en { +- rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; +-}; +- +-&bt_host_wake_l { +- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +-}; +- +-&ec_ap_int_l { +- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; +-}; +- +-&headset_int_l { +- rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; +-}; +- +-&i2s0_8ch_bus { +- rockchip,pins = +- <3 RK_PD0 1 &pcfg_pull_none_6ma>, +- <3 RK_PD1 1 &pcfg_pull_none_6ma>, +- <3 RK_PD2 1 &pcfg_pull_none_6ma>, +- <3 RK_PD3 1 &pcfg_pull_none_6ma>, +- <3 RK_PD7 1 &pcfg_pull_none_6ma>, +- <4 RK_PA0 1 &pcfg_pull_none_6ma>; +-}; +- +-/* there is no external pull up, so need to set this pin pull up */ +-&sdmmc_cd_pin { +- rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; +-}; +- +-&sd_pwr_1800_sel { +- rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; +-}; +- +-&sdmode_en { +- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; +-}; +- +-&touch_reset_l { +- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; +-}; +- +-&touch_int_l { +- rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; +-}; +- +-&pinctrl { +- pinctrl-0 = < +- &ap_pwroff /* AP will auto-assert this when in S3 */ +- &clk_32k /* This pin is always 32k on gru boards */ +- &wlan_rf_kill_1v8_l +- >; +- +- pcfg_pull_none_6ma: pcfg-pull-none-6ma { +- bias-disable; +- drive-strength = <6>; +- }; +- +- camera { +- pp1250_cam_en: pp1250-dvdd { +- rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- pp2800_cam_en: pp2800-avdd { +- rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- ucam_rst: ucam_rst { +- rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- wcam_rst: wcam_rst { +- rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- digitizer { +- pen_int_odl: pen-int-odl { +- rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- pen_reset_l: pen-reset-l { +- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- discrete-regulators { +- display_rst_l: display-rst-l { +- rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- ppvarp_lcd_en: ppvarp-lcd-en { +- rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- ppvarn_lcd_en: ppvarn-lcd-en { +- rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- dmic { +- dmic_en: dmic-en { +- rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pen { +- pen_eject_odl: pen-eject-odl { +- rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- tpm { +- h1_int_od_l: h1-int-od-l { +- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +- +-&wifi { +- bt_en_1v8_l: bt-en-1v8-l { +- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- wlan_pd_1v8_l: wlan-pd-1v8-l { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- /* Default pull-up, but just to be clear */ +- wlan_rf_kill_1v8_l: wlan-rf-kill-1v8-l { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- wifi_perst_l: wifi-perst-l { +- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- wlan_host_wake_l: wlan-host-wake-l { +- rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru.dtsi +deleted file mode 100644 +index 2f8e11710969..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-gru.dtsi ++++ /dev/null +@@ -1,836 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Google Gru (and derivatives) board device tree source +- * +- * Copyright 2016-2017 Google, Inc +- */ +- +-#include +-#include "rk3399.dtsi" +-#include "rk3399-op1-opp.dtsi" +- +-/ { +- aliases { +- mmc0 = &sdmmc; +- mmc1 = &sdhci; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- /* +- * Power Tree +- * +- * In general an attempt is made to include all rails called out by +- * the schematic as long as those rails interact in some way with +- * the AP. AKA: +- * - Rails that only connect to the EC (or devices that the EC talks to) +- * are not included. +- * - Rails _are_ included if the rails go to the AP even if the AP +- * doesn't currently care about them / they are always on. The idea +- * here is that it makes it easier to map to the schematic or extend +- * later. +- * +- * If two rails are substantially the same from the AP's point of +- * view, though, we won't create a full fixed regulator. We'll just +- * put the child rail as an alias of the parent rail. Sometimes rails +- * look the same to the AP because one of these is true: +- * - The EC controls the enable and the EC always enables a rail as +- * long as the AP is running. +- * - The rails are actually connected to each other by a jumper and +- * the distinction is just there to add clarity/flexibility to the +- * schematic. +- */ +- +- ppvar_sys: ppvar-sys { +- compatible = "regulator-fixed"; +- regulator-name = "ppvar_sys"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- pp1200_lpddr: pp1200-lpddr { +- compatible = "regulator-fixed"; +- regulator-name = "pp1200_lpddr"; +- +- /* EC turns on w/ lpddr_pwr_en; always on for AP */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- +- vin-supply = <&ppvar_sys>; +- }; +- +- pp1800: pp1800 { +- compatible = "regulator-fixed"; +- regulator-name = "pp1800"; +- +- /* Always on when ppvar_sys shows power good */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- vin-supply = <&ppvar_sys>; +- }; +- +- pp3300: pp3300 { +- compatible = "regulator-fixed"; +- regulator-name = "pp3300"; +- +- /* Always on; plain and simple */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- vin-supply = <&ppvar_sys>; +- }; +- +- pp5000: pp5000 { +- compatible = "regulator-fixed"; +- regulator-name = "pp5000"; +- +- /* EC turns on w/ pp5000_en; always on for AP */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- vin-supply = <&ppvar_sys>; +- }; +- +- ppvar_bigcpu_pwm: ppvar-bigcpu-pwm { +- compatible = "pwm-regulator"; +- regulator-name = "ppvar_bigcpu_pwm"; +- +- pwms = <&pwm1 0 3337 0>; +- pwm-supply = <&ppvar_sys>; +- pwm-dutycycle-range = <100 0>; +- pwm-dutycycle-unit = <100>; +- +- /* EC turns on w/ ap_core_en; always on for AP */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <800107>; +- regulator-max-microvolt = <1302232>; +- }; +- +- ppvar_bigcpu: ppvar-bigcpu { +- compatible = "vctrl-regulator"; +- regulator-name = "ppvar_bigcpu"; +- +- regulator-min-microvolt = <800107>; +- regulator-max-microvolt = <1302232>; +- +- ctrl-supply = <&ppvar_bigcpu_pwm>; +- ctrl-voltage-range = <800107 1302232>; +- +- regulator-settling-time-up-us = <322>; +- }; +- +- ppvar_litcpu_pwm: ppvar-litcpu-pwm { +- compatible = "pwm-regulator"; +- regulator-name = "ppvar_litcpu_pwm"; +- +- pwms = <&pwm2 0 3337 0>; +- pwm-supply = <&ppvar_sys>; +- pwm-dutycycle-range = <100 0>; +- pwm-dutycycle-unit = <100>; +- +- /* EC turns on w/ ap_core_en; always on for AP */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <797743>; +- regulator-max-microvolt = <1307837>; +- }; +- +- ppvar_litcpu: ppvar-litcpu { +- compatible = "vctrl-regulator"; +- regulator-name = "ppvar_litcpu"; +- +- regulator-min-microvolt = <797743>; +- regulator-max-microvolt = <1307837>; +- +- ctrl-supply = <&ppvar_litcpu_pwm>; +- ctrl-voltage-range = <797743 1307837>; +- +- regulator-settling-time-up-us = <384>; +- }; +- +- ppvar_gpu_pwm: ppvar-gpu-pwm { +- compatible = "pwm-regulator"; +- regulator-name = "ppvar_gpu_pwm"; +- +- pwms = <&pwm0 0 3337 0>; +- pwm-supply = <&ppvar_sys>; +- pwm-dutycycle-range = <100 0>; +- pwm-dutycycle-unit = <100>; +- +- /* EC turns on w/ ap_core_en; always on for AP */ +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <786384>; +- regulator-max-microvolt = <1217747>; +- }; +- +- ppvar_gpu: ppvar-gpu { +- compatible = "vctrl-regulator"; +- regulator-name = "ppvar_gpu"; +- +- regulator-min-microvolt = <786384>; +- regulator-max-microvolt = <1217747>; +- +- ctrl-supply = <&ppvar_gpu_pwm>; +- ctrl-voltage-range = <786384 1217747>; +- +- regulator-settling-time-up-us = <390>; +- }; +- +- /* EC turns on w/ pp900_ddrpll_en */ +- pp900_ddrpll: pp900-ap { +- }; +- +- /* EC turns on w/ pp900_pll_en */ +- pp900_pll: pp900-ap { +- }; +- +- /* EC turns on w/ pp900_pmu_en */ +- pp900_pmu: pp900-ap { +- }; +- +- /* EC turns on w/ pp1800_s0_en_l */ +- pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 { +- }; +- +- /* EC turns on w/ pp1800_avdd_en_l */ +- pp1800_avdd: pp1800 { +- }; +- +- /* EC turns on w/ pp1800_lid_en_l */ +- pp1800_lid: pp1800_mic: pp1800 { +- }; +- +- /* EC turns on w/ lpddr_pwr_en */ +- pp1800_lpddr: pp1800 { +- }; +- +- /* EC turns on w/ pp1800_pmu_en_l */ +- pp1800_pmu: pp1800 { +- }; +- +- /* EC turns on w/ pp1800_usb_en_l */ +- pp1800_usb: pp1800 { +- }; +- +- pp3000_sd_slot: pp3000-sd-slot { +- compatible = "regulator-fixed"; +- regulator-name = "pp3000_sd_slot"; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd_slot_pwr_en>; +- +- enable-active-high; +- gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; +- +- vin-supply = <&pp3000>; +- }; +- +- /* +- * Technically, this is a small abuse of 'regulator-gpio'; this +- * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are +- * always on though, so it is sufficient to simply control the mux +- * here. +- */ +- ppvar_sd_card_io: ppvar-sd-card-io { +- compatible = "regulator-gpio"; +- regulator-name = "ppvar_sd_card_io"; +- pinctrl-names = "default"; +- pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>; +- +- enable-active-high; +- enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; +- gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; +- states = <1800000 0x1>, +- <3000000 0x0>; +- +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- }; +- +- /* EC turns on w/ pp3300_trackpad_en_l */ +- pp3300_trackpad: pp3300-trackpad { +- }; +- +- /* EC turns on w/ usb_a_en */ +- pp5000_usb_a_vbus: pp5000 { +- }; +- +- ap_rtc_clk: ap-rtc-clk { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-output-names = "xin32k"; +- #clock-cells = <0>; +- }; +- +- max98357a: max98357a { +- compatible = "maxim,max98357a"; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmode_en>; +- sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; +- sdmode-delay = <2>; +- #sound-dai-cells = <0>; +- status = "okay"; +- }; +- +- sound: sound { +- compatible = "rockchip,rk3399-gru-sound"; +- rockchip,cpu = <&i2s0 &spdif>; +- }; +-}; +- +-&cdn_dp { +- status = "okay"; +-}; +- +-/* +- * Set some suspend operating points to avoid OVP in suspend +- * +- * When we go into S3 ARM Trusted Firmware will transition our PWM regulators +- * from wherever they're at back to the "default" operating point (whatever +- * voltage we get when we set the PWM pins to "input"). +- * +- * This quick transition under light load has the possibility to trigger the +- * regulator "over voltage protection" (OVP). +- * +- * To make extra certain that we don't hit this OVP at suspend time, we'll +- * transition to a voltage that's much closer to the default (~1.0 V) so that +- * there will not be a big jump. Technically we only need to get within 200 mV +- * of the default voltage, but the speed here should be fast enough and we need +- * suspend/resume to be rock solid. +- */ +- +-&cluster0_opp { +- opp05 { +- opp-suspend; +- }; +-}; +- +-&cluster1_opp { +- opp06 { +- opp-suspend; +- }; +-}; +- +-&cpu_l0 { +- cpu-supply = <&ppvar_litcpu>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&ppvar_litcpu>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&ppvar_litcpu>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&ppvar_litcpu>; +-}; +- +-&cpu_b0 { +- cpu-supply = <&ppvar_bigcpu>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&ppvar_bigcpu>; +-}; +- +- +-&cru { +- assigned-clocks = +- <&cru PLL_GPLL>, <&cru PLL_CPLL>, +- <&cru PLL_NPLL>, +- <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, +- <&cru PCLK_PERIHP>, +- <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, +- <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, +- <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, +- <&cru ACLK_VIO>, <&cru ACLK_HDCP>, +- <&cru ACLK_GIC_PRE>, +- <&cru PCLK_DDR>; +- assigned-clock-rates = +- <600000000>, <800000000>, +- <1000000000>, +- <150000000>, <75000000>, +- <37500000>, +- <100000000>, <100000000>, +- <50000000>, <800000000>, +- <100000000>, <50000000>, +- <400000000>, <400000000>, +- <200000000>, +- <200000000>; +-}; +- +-&emmc_phy { +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&ppvar_gpu>; +- status = "okay"; +-}; +- +-ap_i2c_ts: &i2c3 { +- status = "okay"; +- +- clock-frequency = <400000>; +- +- /* These are relatively safe rise/fall times */ +- i2c-scl-falling-time-ns = <50>; +- i2c-scl-rising-time-ns = <300>; +-}; +- +-ap_i2c_audio: &i2c8 { +- status = "okay"; +- +- clock-frequency = <400000>; +- +- /* These are relatively safe rise/fall times */ +- i2c-scl-falling-time-ns = <50>; +- i2c-scl-rising-time-ns = <300>; +- +- codec: da7219@1a { +- compatible = "dlg,da7219"; +- reg = <0x1a>; +- interrupt-parent = <&gpio1>; +- interrupts = <23 IRQ_TYPE_LEVEL_LOW>; +- clocks = <&cru SCLK_I2S_8CH_OUT>; +- clock-names = "mclk"; +- dlg,micbias-lvl = <2600>; +- dlg,mic-amp-in-sel = "diff"; +- pinctrl-names = "default"; +- pinctrl-0 = <&headset_int_l>; +- VDD-supply = <&pp1800>; +- VDDMIC-supply = <&pp3300>; +- VDDIO-supply = <&pp1800>; +- +- da7219_aad { +- dlg,adc-1bit-rpt = <1>; +- dlg,btn-avg = <4>; +- dlg,btn-cfg = <50>; +- dlg,mic-det-thr = <500>; +- dlg,jack-ins-deb = <20>; +- dlg,jack-det-rate = "32ms_64ms"; +- dlg,jack-rem-deb = <1>; +- +- dlg,a-d-btn-thr = <0xa>; +- dlg,d-b-btn-thr = <0x16>; +- dlg,b-c-btn-thr = <0x21>; +- dlg,c-mic-btn-thr = <0x3E>; +- }; +- }; +-}; +- +-&i2s0 { +- status = "okay"; +-}; +- +-&io_domains { +- status = "okay"; +- +- audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */ +- bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */ +- gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */ +- sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */ +-}; +- +-&pcie0 { +- status = "okay"; +- +- ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>; +- vpcie3v3-supply = <&pp3300_wifi_bt>; +- vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */ +- vpcie0v9-supply = <&pp900_pcie>; +- +- pci_rootport: pcie@0,0 { +- reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>; +- #address-cells = <3>; +- #size-cells = <2>; +- ranges; +- }; +-}; +- +-&pcie_phy { +- status = "okay"; +-}; +- +-&pmu_io_domains { +- status = "okay"; +- +- pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */ +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&pwm3 { +- status = "okay"; +-}; +- +-&sdhci { +- /* +- * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the +- * same (or nearly the same) performance for all eMMC that are intended +- * to be used. +- */ +- assigned-clock-rates = <150000000>; +- +- bus-width = <8>; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- non-removable; +- status = "okay"; +-}; +- +-&sdmmc { +- status = "okay"; +- +- /* +- * Note: configure "sdmmc_cd" as card detect even though it's actually +- * hooked to ground. Because we specified "cd-gpios" below dw_mmc +- * should be ignoring card detect anyway. Specifying the pin as +- * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag) +- * turned on that the system will still make sure the port is +- * configured as SDMMC and not JTAG. +- */ +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_pin +- &sdmmc_bus4>; +- +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; +- disable-wp; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- vmmc-supply = <&pp3000_sd_slot>; +- vqmmc-supply = <&ppvar_sd_card_io>; +-}; +- +-&spdif { +- status = "okay"; +- +- /* +- * SPDIF is routed internally to DP; we either don't use these pins, or +- * mux them to something else. +- */ +- /delete-property/ pinctrl-0; +- /delete-property/ pinctrl-names; +-}; +- +-&spi1 { +- status = "okay"; +- +- pinctrl-names = "default", "sleep"; +- pinctrl-1 = <&spi1_sleep>; +- +- spiflash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- +- /* May run faster once verified. */ +- spi-max-frequency = <10000000>; +- }; +-}; +- +-&spi2 { +- status = "okay"; +-}; +- +-&spi5 { +- status = "okay"; +- +- cros_ec: ec@0 { +- compatible = "google,cros-ec-spi"; +- reg = <0>; +- interrupt-parent = <&gpio0>; +- interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ec_ap_int_l>; +- spi-max-frequency = <3000000>; +- +- i2c_tunnel: i2c-tunnel { +- compatible = "google,cros-ec-i2c-tunnel"; +- google,remote-bus = <4>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- usbc_extcon0: extcon0 { +- compatible = "google,extcon-usbc-cros-ec"; +- google,usb-port-id = <0>; +- }; +- }; +-}; +- +-&tsadc { +- status = "okay"; +- +- rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ +-}; +- +-&tcphy0 { +- status = "okay"; +- extcon = <&usbc_extcon0>; +-}; +- +-&u2phy0 { +- status = "okay"; +-}; +- +-&u2phy0_host { +- status = "okay"; +-}; +- +-&u2phy1_host { +- status = "okay"; +-}; +- +-&u2phy0_otg { +- status = "okay"; +-}; +- +-&u2phy1_otg { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usbdrd3_0 { +- status = "okay"; +- extcon = <&usbc_extcon0>; +-}; +- +-&usbdrd_dwc3_0 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +- +-#include +-#include +- +-&pinctrl { +- /* +- * pinctrl settings for pins that have no real owners. +- * +- * At the moment settings are identical for S0 and S3, but if we later +- * need to configure things differently for S3 we'll adjust here. +- */ +- pinctrl-names = "default"; +- pinctrl-0 = < +- &ap_pwroff /* AP will auto-assert this when in S3 */ +- &clk_32k /* This pin is always 32k on gru boards */ +- >; +- +- pcfg_output_low: pcfg-output-low { +- output-low; +- }; +- +- pcfg_output_high: pcfg-output-high { +- output-high; +- }; +- +- pcfg_pull_none_8ma: pcfg-pull-none-8ma { +- bias-disable; +- drive-strength = <8>; +- }; +- +- backlight-enable { +- bl_en: bl-en { +- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- cros-ec { +- ec_ap_int_l: ec-ap-int-l { +- rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- discrete-regulators { +- sd_io_pwr_en: sd-io-pwr-en { +- rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO +- &pcfg_pull_none>; +- }; +- +- sd_pwr_1800_sel: sd-pwr-1800-sel { +- rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO +- &pcfg_pull_none>; +- }; +- +- sd_slot_pwr_en: sd-slot-pwr-en { +- rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO +- &pcfg_pull_none>; +- }; +- }; +- +- codec { +- /* Has external pullup */ +- headset_int_l: headset-int-l { +- rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- mic_int: mic-int { +- rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- max98357a { +- sdmode_en: sdmode-en { +- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- pcie { +- pcie_clkreqn_cpm: pci-clkreqn-cpm { +- /* +- * Since our pcie doesn't support ClockPM(CPM), we want +- * to hack this as gpio, so the EP could be able to +- * de-assert it along and make ClockPM(CPM) work. +- */ +- rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdmmc { +- /* +- * We run sdmmc at max speed; bump up drive strength. +- * We also have external pulls, so disable the internal ones. +- */ +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = +- <4 RK_PB0 1 &pcfg_pull_none_8ma>, +- <4 RK_PB1 1 &pcfg_pull_none_8ma>, +- <4 RK_PB2 1 &pcfg_pull_none_8ma>, +- <4 RK_PB3 1 &pcfg_pull_none_8ma>; +- }; +- +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = +- <4 RK_PB4 1 &pcfg_pull_none_8ma>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = +- <4 RK_PB5 1 &pcfg_pull_none_8ma>; +- }; +- +- /* +- * In our case the official card detect is hooked to ground +- * to avoid getting access to JTAG just by sticking something +- * in the SD card slot (see the force_jtag bit in the TRM). +- * +- * We still configure it as card detect because it doesn't +- * hurt and dw_mmc will ignore it. We make sure to disable +- * the pull though so we don't burn needless power. +- */ +- sdmmc_cd: sdmmc-cd { +- rockchip,pins = +- <0 RK_PA7 1 &pcfg_pull_none>; +- }; +- +- /* This is where we actually hook up CD; has external pull */ +- sdmmc_cd_pin: sdmmc-cd-pin { +- rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- spi1 { +- spi1_sleep: spi1-sleep { +- /* +- * Pull down SPI1 CLK/CS/RX/TX during suspend, to +- * prevent leakage. +- */ +- rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>, +- <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>, +- <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>, +- <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- touchscreen { +- touch_int_l: touch-int-l { +- rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- touch_reset_l: touch-reset-l { +- rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- trackpad { +- ap_i2c_tp_pu_en: ap-i2c-tp-pu-en { +- rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- +- trackpad_int_l: trackpad-int-l { +- rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- wifi: wifi { +- wlan_module_reset_l: wlan-module-reset-l { +- rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_host_wake_l: bt-host-wake-l { +- /* Kevin has an external pull up, but Gru does not */ +- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- write-protect { +- ap_fw_wp: ap-fw-wp { +- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-hugsun-x99.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-hugsun-x99.dts +deleted file mode 100644 +index bee45c17e2ca..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-hugsun-x99.dts ++++ /dev/null +@@ -1,763 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/dts-v1/; +-#include +-#include +-#include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" +- +-/ { +- model = "Hugsun X99 TV BOX"; +- compatible = "hugsun,x99", "rockchip,rk3399"; +- +- aliases { +- mmc0 = &sdio0; +- mmc1 = &sdmmc; +- mmc2 = &sdhci; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- clkin_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "clkin_gmac"; +- #clock-cells = <0>; +- }; +- +- dc_5v: dc-5v { +- compatible = "regulator-fixed"; +- regulator-name = "dc_5v"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ir_rx>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&power_led_pin>; +- +- power_led: led-0 { +- label = "blue:power"; +- gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- linux,default-trigger = "default-on"; +- }; +- }; +- +- vcc_sys: vcc-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- vin-supply = <&dc_5v>; +- }; +- +- vcc_phy: vcc-phy-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_phy"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc1v8_s0: vcc1v8-s0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc1v8_s0"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcc3v3_sys: vcc3v3-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_sys"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc5v0_host: vcc5v0-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&host_vbus_drv>; +- regulator-name = "vcc5v0_host"; +- regulator-always-on; +- }; +- +- vcc5v0_typec: vcc5v0-typec-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_typec_en>; +- regulator-name = "vcc5v0_typec"; +- regulator-always-on; +- vin-supply = <&vcc5v0_usb>; +- }; +- +- vcc5v0_usb: vcc5v0-usb { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_usb"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&dc_5v>; +- }; +- +- vdd_log: vdd-log { +- compatible = "pwm-regulator"; +- pwms = <&pwm2 0 25000 1>; +- pwm-supply = <&vcc_sys>; +- regulator-name = "vdd_log"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&rk808 1>; +- clock-names = "ext_clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_reg_on_h>; +- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; +- }; +- +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&emmc_phy { +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_RMII_SRC>; +- assigned-clock-parents = <&clkin_gmac>; +- clock_in_out = "input"; +- phy-supply = <&vcc_phy>; +- phy-mode = "rgmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 50000>; +- tx_delay = <0x28>; +- rx_delay = <0x11>; +- status = "okay"; +-}; +- +-&gpu { +- status = "okay"; +- mali-supply = <&vdd_gpu>; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_cec>; +- status = "okay"; +-}; +- +-&hdmi_sound { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- i2c-scl-rising-time-ns = <180>; +- i2c-scl-falling-time-ns = <30>; +- clock-frequency = <400000>; +- +- vdd_cpu_b: syr827@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- regulator-compatible = "fan53555-reg"; +- pinctrl-0 = <&vsel1_pin>; +- regulator-name = "vdd_cpu_b"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- fcs,suspend-voltage-selector = <1>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: syr828@41 { +- compatible = "silergy,syr828"; +- reg = <0x41>; +- regulator-compatible = "fan53555-reg"; +- pinctrl-0 = <&vsel2_pin>; +- regulator-name = "vdd_gpu"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- fcs,suspend-voltage-selector = <1>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- regulator-initial-mode = <1>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio1>; +- interrupts = <21 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rtc_clko_wifi"; +- +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc6-supply = <&vcc_sys>; +- vcc7-supply = <&vcc_sys>; +- vcc8-supply = <&vcc3v3_sys>; +- vcc9-supply = <&vcc_sys>; +- vcc10-supply = <&vcc_sys>; +- vcc11-supply = <&vcc_sys>; +- vcc12-supply = <&vcc3v3_sys>; +- vddio-supply = <&vcc_1v8>; +- +- regulators { +- vdd_center: DCDC_REG1 { +- regulator-name = "vdd_center"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-ramp-delay = <6001>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_l: DCDC_REG2 { +- regulator-name = "vdd_cpu_l"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_1v8: DCDC_REG4 { +- regulator-name = "vcc_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc1v8_dvp: LDO_REG1 { +- regulator-name = "vcc1v8_dvp"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcca1v8_hdmi: LDO_REG2 { +- regulator-name = "vcca1v8_hdmi"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcca_1v8: LDO_REG3 { +- regulator-name = "vcca_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc_sd: LDO_REG4 { +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc3v0_sd: LDO_REG5 { +- regulator-name = "vcc3v0_sd"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc_1v5: LDO_REG6 { +- regulator-name = "vcc_1v5"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1500000>; +- }; +- }; +- +- vcca0v9_hdmi: LDO_REG7 { +- regulator-name = "vcca0v9_hdmi"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <900000>; +- }; +- }; +- +- vcc_3v0: LDO_REG8 { +- regulator-name = "vcc_3v0"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc3v3_s3: SWITCH_REG1 { +- regulator-name = "vcc3v3_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc3v3_s0: SWITCH_REG2 { +- regulator-name = "vcc3v3_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- i2c-scl-rising-time-ns = <300>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +-}; +- +-&i2c3 { +- i2c-scl-rising-time-ns = <450>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +-}; +- +-&i2c4 { +- i2c-scl-rising-time-ns = <600>; +- i2c-scl-falling-time-ns = <40>; +- status = "okay"; +- +- fusb0: typec-portc@22 { +- compatible = "fcs,fusb302"; +- reg = <0x22>; +- interrupt-parent = <&gpio1>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&fusb0_int>; +- vbus-supply = <&vcc5v0_typec>; +- status = "okay"; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&i2s0 { +- rockchip,playback-channels = <8>; +- rockchip,capture-channels = <8>; +- status = "okay"; +-}; +- +-&i2s1 { +- rockchip,playback-channels = <2>; +- rockchip,capture-channels = <2>; +- status = "okay"; +-}; +- +-&i2s2 { +- status = "okay"; +-}; +- +-&io_domains { +- status = "okay"; +- audio-supply = <&vcc1v8_s0>; +- bt656-supply = <&vcc1v8_s0>; +- gpio1830-supply = <&vcc_3v0>; +- sdmmc-supply = <&vcc_sd>; +-}; +- +-&pmu_io_domains { +- status = "okay"; +- pmu1830-supply = <&vcc_1v8>; +-}; +- +-&pinctrl { +- fusb30x { +- fusb0_int: fusb0-int { +- rockchip,pins = +- <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- gmac { +- rgmii_sleep_pins: rgmii-sleep-pins { +- rockchip,pins = +- <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- }; +- +- ir { +- ir_rx: ir-rx { +- rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>; +- }; +- }; +- +- leds { +- power_led_pin: power-led-pin { +- rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = +- <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- vsel1_pin: vsel1-pin { +- rockchip,pins = +- <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- vsel2_pin: vsel2-pin { +- rockchip,pins = +- <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- sdio { +- bt_host_wake_l: bt-host-wake-l { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_reg_on_h: bt-reg-on-h { +- /* external pullup to VCC1V8_PMUPLL */ +- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_wake_l: bt-wake-l { +- rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- wifi_reg_on_h: wifi-reg_on-h { +- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- wifi { +- wifi_host_wake_l: wifi-host-wake-l { +- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb-typec { +- vcc5v0_typec_en: vcc5v0_typec_en { +- rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- usb2 { +- host_vbus_drv: host-vbus-drv { +- rockchip,pins = +- <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm2 { +- status = "okay"; +- pinctrl-0 = <&pwm2_pin_pull_down>; +-}; +- +-&saradc { +- vref-supply = <&vcc1v8_s0>; +- status = "okay"; +-}; +- +-&sdmmc { +- clock-frequency = <150000000>; +- max-frequency = <150000000>; +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- disable-wp; +- vqmmc-supply = <&vcc_sd>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +- card-detect-delay = <800>; +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- non-removable; +- keep-power-in-suspend; +- status = "okay"; +-}; +- +-&sdio0 { +- bus-width = <4>; +- clock-frequency = <50000000>; +- cap-sdio-irq; +- cap-sd-highspeed; +- keep-power-in-suspend; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; +- sd-uhs-sdr104; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- brcmf: wifi@1 { +- compatible = "brcm,bcm4329-fmac"; +- reg = <1>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- interrupt-names = "host-wake"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_host_wake_l>; +- }; +-}; +- +-&spdif { +- status = "okay"; +- pinctrl-0 = <&spdif_bus_1>; +-}; +- +-&spi1 { +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- spi-max-frequency = <10000000>; +- }; +-}; +- +-&tcphy0 { +- status = "okay"; +-}; +- +-&tcphy1 { +- status = "okay"; +-}; +- +-&tsadc { +- /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-mode = <1>; +- /* tshut polarity 0:LOW 1:HIGH */ +- rockchip,hw-tshut-polarity = <1>; +- rockchip,hw-tshut-temp = <110000>; +- status = "okay"; +-}; +- +-&u2phy0 { +- status = "okay"; +- +- u2phy0_host: host-port { +- phy-supply = <&vcc5v0_typec>; +- status = "okay"; +- }; +- +- u2phy0_otg: otg-port { +- status = "okay"; +- }; +-}; +- +-&u2phy1 { +- status = "okay"; +- +- u2phy1_host: host-port { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +- }; +- +- u2phy1_otg: otg-port { +- status = "okay"; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&rk808 1>; +- clock-names = "ext_clock"; +- device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; +- max-speed = <4000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; +- vbat-supply = <&vcc3v3_sys>; +- vddio-supply = <&vcc_1v8>; +- }; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&usbdrd3_0 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_0 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&usbdrd3_1 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_1 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-khadas-edge-captain.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-khadas-edge-captain.dts +deleted file mode 100644 +index 8302e51def52..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-khadas-edge-captain.dts ++++ /dev/null +@@ -1,27 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. +- * (https://www.khadas.com) +- */ +- +-/dts-v1/; +-#include "rk3399-khadas-edge.dtsi" +- +-/ { +- model = "Khadas Edge-Captain"; +- compatible = "khadas,edge-captain", "rockchip,rk3399"; +-}; +- +-&gmac { +- status = "okay"; +-}; +- +-&pcie_phy { +- status = "okay"; +-}; +- +-&pcie0 { +- ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; +- num-lanes = <4>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-khadas-edge-v.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-khadas-edge-v.dts +deleted file mode 100644 +index f5dcb99dc349..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-khadas-edge-v.dts ++++ /dev/null +@@ -1,27 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. +- * (https://www.khadas.com) +- */ +- +-/dts-v1/; +-#include "rk3399-khadas-edge.dtsi" +- +-/ { +- model = "Khadas Edge-V"; +- compatible = "khadas,edge-v", "rockchip,rk3399"; +-}; +- +-&gmac { +- status = "okay"; +-}; +- +-&pcie_phy { +- status = "okay"; +-}; +- +-&pcie0 { +- ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; +- num-lanes = <4>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-khadas-edge.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-khadas-edge.dts +deleted file mode 100644 +index 31616e7ad89d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-khadas-edge.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. +- * (https://www.khadas.com) +- */ +- +-/dts-v1/; +-#include "rk3399-khadas-edge.dtsi" +- +-/ { +- model = "Khadas Edge"; +- compatible = "khadas,edge", "rockchip,rk3399"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-khadas-edge.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-khadas-edge.dtsi +deleted file mode 100644 +index f1fcc6b5b402..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-khadas-edge.dtsi ++++ /dev/null +@@ -1,836 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. +- * (https://www.khadas.com) +- */ +- +-/dts-v1/; +-#include +-#include +-#include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" +- +-/ { +- aliases { +- mmc0 = &sdio0; +- mmc1 = &sdmmc; +- mmc2 = &sdhci; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- clkin_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "clkin_gmac"; +- #clock-cells = <0>; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&rk808 1>; +- clock-names = "ext_clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_enable_h>; +- +- /* +- * On the module itself this is one of these (depending +- * on the actual card populated): +- * - SDIO_RESET_L_WL_REG_ON +- * - PDN (power down when low) +- */ +- reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>; +- }; +- +- /* switched by pmic_sleep */ +- vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc1v8_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_1v8>; +- }; +- +- vcc3v3_pcie: vcc3v3-pcie-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_pcie"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vsys_3v3>; +- }; +- +- /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ +- vcc5v0_host: vcc5v0-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_host_en>; +- regulator-name = "vcc5v0_host"; +- regulator-always-on; +- vin-supply = <&vsys_5v0>; +- }; +- +- vdd_log: vdd-log { +- compatible = "pwm-regulator"; +- pwms = <&pwm2 0 25000 1>; +- regulator-name = "vdd_log"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- vin-supply = <&vsys_3v3>; +- }; +- +- vsys: vsys { +- compatible = "regulator-fixed"; +- regulator-name = "vsys"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vsys_3v3: vsys-3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vsys_3v3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vsys>; +- }; +- +- vsys_5v0: vsys-5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "vsys_5v0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vsys>; +- }; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 1>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1800000>; +- poll-interval = <100>; +- +- recovery { +- label = "Recovery"; +- linux,code = ; +- press-threshold-microvolt = <18000>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwrbtn>; +- +- power { +- debounce-interval = <100>; +- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; +- label = "GPIO Key Power"; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; +- linux,rc-map-name = "rc-khadas"; +- pinctrl-names = "default"; +- pinctrl-0 = <&ir_rx>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&sys_led_pin>, <&user_led_pin>; +- +- sys_led: led-0 { +- label = "sys_led"; +- linux,default-trigger = "heartbeat"; +- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; +- }; +- +- user_led: led-1 { +- label = "user_led"; +- default-state = "off"; +- gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- fan: pwm-fan { +- compatible = "pwm-fan"; +- cooling-levels = <0 150 200 255>; +- #cooling-cells = <2>; +- fan-supply = <&vsys_5v0>; +- pwms = <&pwm0 0 40000 0>; +- }; +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_thermal { +- trips { +- cpu_warm: cpu_warm { +- temperature = <55000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- cpu_hot: cpu_hot { +- temperature = <65000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- }; +- +- cooling-maps { +- map2 { +- trip = <&cpu_warm>; +- cooling-device = <&fan THERMAL_NO_LIMIT 1>; +- }; +- +- map3 { +- trip = <&cpu_hot>; +- cooling-device = <&fan 2 THERMAL_NO_LIMIT>; +- }; +- }; +-}; +- +-&emmc_phy { +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_RMII_SRC>; +- assigned-clock-parents = <&clkin_gmac>; +- clock_in_out = "input"; +- phy-supply = <&vcc_lan>; +- phy-mode = "rgmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 50000>; +- tx_delay = <0x28>; +- rx_delay = <0x11>; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&gpu_thermal { +- trips { +- gpu_warm: gpu_warm { +- temperature = <55000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- gpu_hot: gpu_hot { +- temperature = <65000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- }; +- +- cooling-maps { +- map1 { +- trip = <&gpu_warm>; +- cooling-device = <&fan THERMAL_NO_LIMIT 1>; +- }; +- +- map2 { +- trip = <&gpu_hot>; +- cooling-device = <&fan 2 THERMAL_NO_LIMIT>; +- }; +- }; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_cec>; +- status = "okay"; +-}; +- +-&hdmi_sound { +- status = "okay"; +-}; +- +-&i2c3 { +- i2c-scl-rising-time-ns = <450>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +-}; +- +-&i2c4 { +- clock-frequency = <400000>; +- i2c-scl-rising-time-ns = <168>; +- i2c-scl-falling-time-ns = <4>; +- status = "okay"; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio1>; +- interrupts = ; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vsys_3v3>; +- vcc2-supply = <&vsys_3v3>; +- vcc3-supply = <&vsys_3v3>; +- vcc4-supply = <&vsys_3v3>; +- vcc6-supply = <&vsys_3v3>; +- vcc7-supply = <&vsys_3v3>; +- vcc8-supply = <&vsys_3v3>; +- vcc9-supply = <&vsys_3v3>; +- vcc10-supply = <&vsys_3v3>; +- vcc11-supply = <&vsys_3v3>; +- vcc12-supply = <&vsys_3v3>; +- vddio-supply = <&vcc_1v8>; +- +- regulators { +- vdd_center: DCDC_REG1 { +- regulator-name = "vdd_center"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_l: DCDC_REG2 { +- regulator-name = "vdd_cpu_l"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_1v8: DCDC_REG4 { +- regulator-name = "vcc_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc1v8_apio2: LDO_REG1 { +- regulator-name = "vcc1v8_apio2"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_vldo2: LDO_REG2 { +- regulator-name = "vcc_vldo2"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc1v8_pmupll: LDO_REG3 { +- regulator-name = "vcc1v8_pmupll"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vccio_sd: LDO_REG4 { +- regulator-name = "vccio_sd"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc_vldo5: LDO_REG5 { +- regulator-name = "vcc_vldo5"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v5: LDO_REG6 { +- regulator-name = "vcc_1v5"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1500000>; +- }; +- }; +- +- vcc1v8_codec: LDO_REG7 { +- regulator-name = "vcc1v8_codec"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_3v0: LDO_REG8 { +- regulator-name = "vcc_3v0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc3v3_s3: vcc_lan: SWITCH_REG1 { +- regulator-name = "vcc3v3_s3"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v3_s0: SWITCH_REG2 { +- regulator-name = "vcc3v3_s0"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +- +- vdd_cpu_b: regulator@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- fcs,suspend-voltage-selector = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cpu_b_sleep>; +- regulator-name = "vdd_cpu_b"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vsys_3v3>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: regulator@41 { +- compatible = "silergy,syr828"; +- reg = <0x41>; +- fcs,suspend-voltage-selector = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpu_sleep>; +- regulator-name = "vdd_gpu"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vsys_3v3>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +-}; +- +-&i2c8 { +- clock-frequency = <400000>; +- i2c-scl-rising-time-ns = <160>; +- i2c-scl-falling-time-ns = <30>; +- status = "okay"; +-}; +- +-&i2s0 { +- rockchip,playback-channels = <8>; +- rockchip,capture-channels = <8>; +- status = "okay"; +-}; +- +-&i2s1 { +- rockchip,playback-channels = <2>; +- rockchip,capture-channels = <2>; +- status = "okay"; +-}; +- +-&i2s2 { +- status = "okay"; +-}; +- +-&io_domains { +- bt656-supply = <&vcc1v8_apio2>; +- audio-supply = <&vcc1v8_codec>; +- sdmmc-supply = <&vccio_sd>; +- gpio1830-supply = <&vcc_3v0>; +- status = "okay"; +-}; +- +-&pmu_io_domains { +- pmu1830-supply = <&vcc_1v8>; +- status = "okay"; +-}; +- +-&pinctrl { +- bt { +- bt_host_wake_l: bt-host-wake-l { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_reg_on_h: bt-reg-on-h { +- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_wake_l: bt-wake-l { +- rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- buttons { +- pwrbtn: pwrbtn { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- ir { +- ir_rx: ir-rx { +- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- leds { +- sys_led_pin: sys-led-pin { +- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- user_led_pin: user-led-pin { +- rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- cpu_b_sleep: cpu-b-sleep { +- rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- gpu_sleep: gpu-sleep { +- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- sdio-pwrseq { +- wifi_enable_h: wifi-enable-h { +- rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb2 { +- vcc5v0_host_en: vcc5v0-host-en { +- rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- wifi { +- wifi_host_wake_l: wifi-host-wake-l { +- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vcca1v8_s3>; +- status = "okay"; +-}; +- +-&sdio0 { +- /* WiFi & BT combo module Ampak AP6356S */ +- bus-width = <4>; +- cap-sdio-irq; +- cap-sd-highspeed; +- keep-power-in-suspend; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; +- sd-uhs-sdr104; +- vqmmc-supply = <&vcc1v8_s3>; +- vmmc-supply = <&vccio_sd>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- interrupt-names = "host-wake"; +- brcm,drive-strength = <5>; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_host_wake_l>; +- }; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; +- disable-wp; +- max-frequency = <150000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- mmc-hs400-1_8v; +- non-removable; +- status = "okay"; +-}; +- +-&spi1 { +- status = "okay"; +- +- spiflash: flash@0 { +- compatible = "winbond,w25q128fw", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <104000000>; +- }; +-}; +- +-&tcphy0 { +- status = "okay"; +-}; +- +-&tcphy1 { +- status = "okay"; +-}; +- +-&tsadc { +- /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-mode = <1>; +- /* tshut polarity 0:LOW 1:HIGH */ +- rockchip,hw-tshut-polarity = <1>; +- status = "okay"; +-}; +- +-&u2phy0 { +- status = "okay"; +- +- u2phy0_otg: otg-port { +- status = "okay"; +- }; +- +- u2phy0_host: host-port { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +- }; +-}; +- +-&u2phy1 { +- status = "okay"; +- +- u2phy1_otg: otg-port { +- status = "okay"; +- }; +- +- u2phy1_host: host-port { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&rk808 1>; +- clock-names = "lpo"; +- device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; +- max-speed = <4000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; +- vbat-supply = <&vsys_3v3>; +- vddio-supply = <&vcc_1v8>; +- }; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&usbdrd3_0 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_0 { +- status = "okay"; +- dr_mode = "otg"; +-}; +- +-&usbdrd3_1 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_1 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-kobol-helios64.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-kobol-helios64.dts +deleted file mode 100644 +index 354f54767bad..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-kobol-helios64.dts ++++ /dev/null +@@ -1,499 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Aditya Prayoga +- */ +- +-/* +- * The Kobol Helios64 is a board designed to operate as a NAS and optionally +- * ships with an enclosing that can host five 2.5" hard disks. +- * +- * See https://wiki.kobol.io/helios64/intro/ for further details. +- */ +- +-/dts-v1/; +-#include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" +- +-/ { +- model = "Kobol Helios64"; +- compatible = "kobol,helios64", "rockchip,rk3399"; +- +- aliases { +- mmc0 = &sdmmc; +- mmc1 = &sdhci; +- }; +- +- avdd_0v9_s0: avdd-0v9-s0 { +- compatible = "regulator-fixed"; +- regulator-name = "avdd_0v9_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- vin-supply = <&vcc1v8_sys_s3>; +- }; +- +- avdd_1v8_s0: avdd-1v8-s0 { +- compatible = "regulator-fixed"; +- regulator-name = "avdd_1v8_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc3v3_sys_s3>; +- }; +- +- clkin_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "clkin_gmac"; +- #clock-cells = <0>; +- }; +- +- fan1 { +- /* fan connected to P7 */ +- compatible = "pwm-fan"; +- pwms = <&pwm0 0 40000 0>; +- cooling-levels = <0 80 170 255>; +- }; +- +- fan2 { +- /* fan connected to P6 */ +- compatible = "pwm-fan"; +- pwms = <&pwm1 0 40000 0>; +- cooling-levels = <0 80 170 255>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&sys_grn_led_on &sys_red_led_on>; +- +- led-0 { +- label = "helios64:green:status"; +- gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- led-1 { +- label = "helios64:red:fault"; +- gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; +- }; +- }; +- +- pcie_power: pcie-power { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; +- pinctrl-0 = <&pcie_pwr>; +- pinctrl-names = "default"; +- regulator-boot-on; +- regulator-name = "pcie_power"; +- startup-delay-us = <10000>; +- vin-supply = <&vcc5v0_perdev>; +- }; +- +- vcc1v8_sys_s0: vcc1v8-sys-s0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc1v8_sys_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc1v8_sys_s3>; +- }; +- +- vcc3v0_sd: vcc3v0-sd { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; +- regulator-name = "vcc3v0_sd"; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc0_pwr_h>; +- vin-supply = <&vcc3v3_sys_s3>; +- }; +- +- vcc3v3_sys_s3: vcc_lan: vcc3v3-sys-s3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_sys_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc5v0_perdev: vcc5v0-perdev { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_perdev"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc12v_dcin_bkup>; +- }; +- +- vcc5v0_sys: vcc5v0-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc12v_dcin_bkup>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc5v0_usb: vcc5v0-usb { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_usb_en>; +- regulator-name = "vcc5v0_usb"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc5v0_perdev>; +- }; +- +- vcc12v_dcin: vcc12v-dcin { +- compatible = "regulator-fixed"; +- regulator-name = "vcc12v_dcin"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- vcc12v_dcin_bkup: vcc12v-dcin-bkup { +- compatible = "regulator-fixed"; +- regulator-name = "vcc12v_dcin_bkup"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- vin-supply = <&vcc12v_dcin>; +- }; +-}; +- +-/* +- * The system doesn't run stable with cpu freq enabled, so disallow the lower +- * frequencies until this problem is properly understood and resolved. +- */ +-&cluster0_opp { +- /delete-node/ opp00; +- /delete-node/ opp01; +- /delete-node/ opp02; +- /delete-node/ opp03; +- /delete-node/ opp04; +-}; +- +-&cluster1_opp { +- /delete-node/ opp00; +- /delete-node/ opp01; +- /delete-node/ opp02; +- /delete-node/ opp03; +- /delete-node/ opp04; +- /delete-node/ opp05; +- /delete-node/ opp06; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&emmc_phy { +- status = "okay"; +-}; +- +-&gmac { +- assigned-clock-parents = <&clkin_gmac>; +- assigned-clocks = <&cru SCLK_RMII_SRC>; +- clock_in_out = "input"; +- phy-mode = "rgmii"; +- phy-supply = <&vcc_lan>; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins &gphy_reset>; +- rx_delay = <0x20>; +- tx_delay = <0x28>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 50000>; +- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- i2c-scl-rising-time-ns = <168>; +- i2c-scl-falling-time-ns = <4>; +- status = "okay"; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio0>; +- interrupts = <10 IRQ_TYPE_LEVEL_LOW>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- vcc1-supply = <&vcc5v0_sys>; +- vcc2-supply = <&vcc5v0_sys>; +- vcc3-supply = <&vcc5v0_sys>; +- vcc4-supply = <&vcc5v0_sys>; +- vcc6-supply = <&vcc5v0_sys>; +- vcc7-supply = <&vcc5v0_sys>; +- vcc8-supply = <&vcc3v3_sys_s3>; +- vcc9-supply = <&vcc5v0_sys>; +- vcc10-supply = <&vcc5v0_sys>; +- vcc11-supply = <&vcc5v0_sys>; +- vcc12-supply = <&vcc3v3_sys_s3>; +- vddio-supply = <&vcc3v0_s3>; +- wakeup-source; +- #clock-cells = <1>; +- +- regulators { +- vdd_cpu_l: DCDC_REG2 { +- regulator-name = "vdd_cpu_l"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc1v8_sys_s3: DCDC_REG4 { +- regulator-name = "vcc1v8_sys_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc_sdio_s0: LDO_REG4 { +- regulator-name = "vcc_sdio_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc3v0_s3: LDO_REG8 { +- regulator-name = "vcc3v0_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- }; +- }; +- +- vdd_cpu_b: regulator@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_cpu_b"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- i2c-scl-rising-time-ns = <160>; +- i2c-scl-falling-time-ns = <30>; +- status = "okay"; +- +- temp@4c { +- compatible = "national,lm75"; +- reg = <0x4c>; +- }; +-}; +- +-&io_domains { +- audio-supply = <&vcc1v8_sys_s0>; +- bt656-supply = <&vcc1v8_sys_s0>; +- gpio1830-supply = <&vcc3v0_s3>; +- sdmmc-supply = <&vcc_sdio_s0>; +- status = "okay"; +-}; +- +-&pcie_phy { +- status = "okay"; +-}; +- +-&pcie0 { +- num-lanes = <2>; +- status = "okay"; +- +- vpcie12v-supply = <&vcc12v_dcin>; +- vpcie3v3-supply = <&pcie_power>; +- vpcie1v8-supply = <&avdd_1v8_s0>; +- vpcie0v9-supply = <&avdd_0v9_s0>; +-}; +- +-&pinctrl { +- gmac { +- gphy_reset: gphy-reset { +- rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; +- }; +- }; +- +- leds { +- sys_grn_led_on: sys-grn-led-on { +- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- sys_red_led_on: sys-red-led-on { +- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- pcie { +- pcie_pwr: pcie-pwr { +- rockchip,pins = +- <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- power { +- vcc5v0_usb_en: vcc5v0-usb-en { +- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- vcc3v0-sd { +- sdmmc0_pwr_h: sdmmc0-pwr-h { +- rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +- +-&pmu_io_domains { +- pmu1830-supply = <&vcc3v0_s3>; +- status = "okay"; +-}; +- +-&pwm0 { +- /* pwm-fan on P7 */ +- status = "okay"; +-}; +- +-&pwm1 { +- /* pwm-fan on P6 */ +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- mmc-hs200-1_8v; +- non-removable; +- vqmmc-supply = <&vcc1v8_sys_s0>; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-sd-highspeed; +- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +- vmmc-supply = <&vcc3v0_sd>; +- vqmmc-supply = <&vcc_sdio_s0>; +- status = "okay"; +-}; +- +-&tcphy1 { +- /* phy for &usbdrd_dwc3_1 */ +- status = "okay"; +-}; +- +-&u2phy1 { +- status = "okay"; +- +- otg-port { +- /* phy for &usbdrd_dwc3_1 */ +- phy-supply = <&vcc5v0_usb>; +- status = "okay"; +- }; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usbdrd3_1 { +- status = "okay"; +- +- usb@fe900000 { +- dr_mode = "host"; +- status = "okay"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-leez-p710.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-leez-p710.dts +deleted file mode 100644 +index e890166e7fd4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-leez-p710.dts ++++ /dev/null +@@ -1,651 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Andy Yan +- */ +- +-/dts-v1/; +-#include +-#include +-#include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" +- +-/ { +- model = "Leez RK3399 P710"; +- compatible = "leez,p710", "rockchip,rk3399"; +- +- aliases { +- mmc0 = &sdio0; +- mmc1 = &sdmmc; +- mmc2 = &sdhci; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- clkin_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "clkin_gmac"; +- #clock-cells = <0>; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&rk808 1>; +- clock-names = "ext_clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_reg_on_h>; +- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; +- }; +- +- dc5v_adp: dc5v-adp { +- compatible = "regulator-fixed"; +- regulator-name = "dc5v_adapter"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- vcc3v3_lan: vcc3v3-lan { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_lan"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc3v3_sys>; +- }; +- +- vcc3v3_sys: vcc3v3-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc5v0_host0: vcc5v0_host1: vcc5v0-host { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_host"; +- regulator-boot-on; +- regulator-always-on; +- regulator-min-microvolt = <5500000>; +- regulator-max-microvolt = <5500000>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc5v0_host3: vcc5v0-host3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_host3"; +- enable-active-high; +- gpio = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_host3_en>; +- regulator-always-on; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc5v0_sys: vcc5v0-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&dc5v_adp>; +- }; +- +- vdd_log: vdd-log { +- compatible = "pwm-regulator"; +- pwms = <&pwm2 0 25000 1>; +- regulator-name = "vdd_log"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- vin-supply = <&vcc5v0_sys>; +- }; +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&emmc_phy { +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_RMII_SRC>; +- assigned-clock-parents = <&clkin_gmac>; +- clock_in_out = "input"; +- phy-supply = <&vcc3v3_lan>; +- phy-mode = "rgmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 50000>; +- tx_delay = <0x28>; +- rx_delay = <0x11>; +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c7>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_cec>; +- status = "okay"; +-}; +- +-&hdmi_sound { +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- i2c-scl-rising-time-ns = <168>; +- i2c-scl-falling-time-ns = <4>; +- status = "okay"; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio1>; +- interrupts = <21 IRQ_TYPE_LEVEL_LOW>; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vcc5v0_sys>; +- vcc2-supply = <&vcc5v0_sys>; +- vcc3-supply = <&vcc5v0_sys>; +- vcc4-supply = <&vcc5v0_sys>; +- vcc6-supply = <&vcc5v0_sys>; +- vcc7-supply = <&vcc5v0_sys>; +- vcc8-supply = <&vcc3v3_sys>; +- vcc9-supply = <&vcc5v0_sys>; +- vcc10-supply = <&vcc5v0_sys>; +- vcc11-supply = <&vcc5v0_sys>; +- vcc12-supply = <&vcc3v3_sys>; +- vddio-supply = <&vcc_1v8>; +- +- regulators { +- vdd_center: DCDC_REG1 { +- regulator-name = "vdd_center"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_l: DCDC_REG2 { +- regulator-name = "vdd_cpu_l"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_1v8: DCDC_REG4 { +- regulator-name = "vcc_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc1v8_dvp: LDO_REG1 { +- regulator-name = "vcc1v8_dvp"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc1v8_hdmi: LDO_REG2 { +- regulator-name = "vcc1v8_hdmi"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcca_1v8: LDO_REG3 { +- regulator-name = "vcca_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vccio_sd: LDO_REG4 { +- regulator-name = "vccio_sd"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcca3v0_codec: LDO_REG5 { +- regulator-name = "vcca3v0_codec"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v5: LDO_REG6 { +- regulator-name = "vcc_1v5"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1500000>; +- }; +- }; +- +- vcc0v9_hdmi: LDO_REG7 { +- regulator-name = "vcc0v9_hdmi"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_3v0: LDO_REG8 { +- regulator-name = "vcc_3v0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- }; +- }; +- +- vdd_cpu_b: regulator@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- fcs,suspend-voltage-selector = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vsel1_pin>; +- regulator-name = "vdd_cpu_b"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: regulator@41 { +- compatible = "silergy,syr828"; +- reg = <0x41>; +- fcs,suspend-voltage-selector = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vsel2_pin>; +- regulator-name = "vdd_gpu"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +-}; +- +-&i2c1 { +- i2c-scl-rising-time-ns = <300>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +-}; +- +-&i2c3 { +- i2c-scl-rising-time-ns = <450>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +-}; +- +-&i2c4 { +- i2c-scl-rising-time-ns = <600>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&i2s0 { +- rockchip,playback-channels = <8>; +- rockchip,capture-channels = <8>; +- status = "okay"; +-}; +- +-&i2s1 { +- rockchip,playback-channels = <2>; +- rockchip,capture-channels = <2>; +- status = "okay"; +-}; +- +-&i2s2 { +- status = "okay"; +-}; +- +-&io_domains { +- status = "okay"; +- +- bt656-supply = <&vcc1v8_dvp>; +- audio-supply = <&vcc_1v8>; +- sdmmc-supply = <&vccio_sd>; +- gpio1830-supply = <&vcc_3v0>; +-}; +- +-&pmu_io_domains { +- status = "okay"; +- pmu1830-supply = <&vcc_3v0>; +-}; +- +-&pinctrl { +- bt { +- bt_reg_on_h: bt-reg-on-h { +- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_host_wake_l: bt-host-wake-l { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_wake_l: bt-wake-l { +- rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- vsel1_pin: vsel1-pin { +- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- vsel2_pin: vsel2-pin { +- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- usb2 { +- vcc5v0_host3_en: vcc5v0-host3-en { +- rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- wifi { +- wifi_reg_on_h: wifi-reg-on-h { +- rockchip,pins = +- <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- wifi_host_wake_l: wifi-host-wake-l { +- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&saradc { +- status = "okay"; +- +- vref-supply = <&vcc_1v8>; +-}; +- +-&sdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- bus-width = <4>; +- clock-frequency = <50000000>; +- cap-sdio-irq; +- cap-sd-highspeed; +- keep-power-in-suspend; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; +- sd-uhs-sdr104; +- status = "okay"; +- +- brcmf: wifi@1 { +- compatible = "brcm,bcm4329-fmac"; +- reg = <1>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- interrupt-names = "host-wake"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_host_wake_l>; +- }; +-}; +- +-&sdhci { +- bus-width = <8>; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- non-removable; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; +- disable-wp; +- max-frequency = <150000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>; +- status = "okay"; +-}; +- +-&tcphy0 { +- status = "okay"; +-}; +- +-&tcphy1 { +- status = "okay"; +-}; +- +-&tsadc { +- status = "okay"; +- +- /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-mode = <1>; +- /* tshut polarity 0:LOW 1:HIGH */ +- rockchip,hw-tshut-polarity = <1>; +-}; +- +-&u2phy0 { +- status = "okay"; +- +- u2phy0_otg: otg-port { +- status = "okay"; +- }; +- +- u2phy0_host: host-port { +- phy-supply = <&vcc5v0_host0>; +- status = "okay"; +- }; +-}; +- +-&u2phy1 { +- status = "okay"; +- +- u2phy1_otg: otg-port { +- status = "okay"; +- }; +- +- u2phy1_host: host-port { +- phy-supply = <&vcc5v0_host1>; +- status = "okay"; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&rk808 1>; +- clock-names = "ext_clock"; +- device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>; +- }; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&usbdrd3_0 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_0 { +- status = "okay"; +- dr_mode = "otg"; +-}; +- +-&usbdrd3_1 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_1 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-nanopc-t4.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-nanopc-t4.dts +deleted file mode 100644 +index 452728b82e42..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-nanopc-t4.dts ++++ /dev/null +@@ -1,137 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * FriendlyElec NanoPC-T4 board device tree source +- * +- * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. +- * (http://www.friendlyarm.com) +- * +- * Copyright (c) 2018 Collabora Ltd. +- */ +- +-/dts-v1/; +-#include "rk3399-nanopi4.dtsi" +- +-/ { +- model = "FriendlyElec NanoPC-T4"; +- compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399"; +- +- vcc12v0_sys: vcc12v0-sys { +- compatible = "regulator-fixed"; +- regulator-always-on; +- regulator-boot-on; +- regulator-max-microvolt = <12000000>; +- regulator-min-microvolt = <12000000>; +- regulator-name = "vcc12v0_sys"; +- }; +- +- vcc5v0_host0: vcc5v0-host0 { +- compatible = "regulator-fixed"; +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc5v0_host0"; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 1>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1800000>; +- poll-interval = <100>; +- +- recovery { +- label = "Recovery"; +- linux,code = ; +- press-threshold-microvolt = <18000>; +- }; +- }; +- +- ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ir_rx>; +- }; +- +- fan: pwm-fan { +- compatible = "pwm-fan"; +- /* +- * With 20KHz PWM and an EVERCOOL EC4007H12SA fan, these levels +- * work out to 0, ~1200, ~3000, and 5000RPM respectively. +- */ +- cooling-levels = <0 12 18 255>; +- #cooling-cells = <2>; +- fan-supply = <&vcc12v0_sys>; +- pwms = <&pwm1 0 50000 0>; +- }; +-}; +- +-&cpu_thermal { +- trips { +- cpu_warm: cpu_warm { +- temperature = <55000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- cpu_hot: cpu_hot { +- temperature = <65000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- }; +- +- cooling-maps { +- map2 { +- trip = <&cpu_warm>; +- cooling-device = <&fan THERMAL_NO_LIMIT 1>; +- }; +- +- map3 { +- trip = <&cpu_hot>; +- cooling-device = <&fan 2 THERMAL_NO_LIMIT>; +- }; +- }; +-}; +- +-&pcie0 { +- ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; +- num-lanes = <4>; +- vpcie3v3-supply = <&vcc3v3_sys>; +-}; +- +-&pinctrl { +- ir { +- ir_rx: ir-rx { +- /* external pullup to VCC3V3_SYS, despite being 1.8V :/ */ +- rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>; +- }; +- }; +-}; +- +-&sdhci { +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +-}; +- +-&u2phy0_host { +- phy-supply = <&vcc5v0_host0>; +-}; +- +-&u2phy1_host { +- phy-supply = <&vcc5v0_host0>; +-}; +- +-&vcc5v0_sys { +- vin-supply = <&vcc12v0_sys>; +-}; +- +-&vcc3v3_sys { +- vin-supply = <&vcc12v0_sys>; +-}; +- +-&vbus_typec { +- enable-active-high; +- gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; +- vin-supply = <&vcc5v0_sys>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-nanopi-m4.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-nanopi-m4.dts +deleted file mode 100644 +index 60358ab8c7df..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-nanopi-m4.dts ++++ /dev/null +@@ -1,66 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * FriendlyElec NanoPi M4 board device tree source +- * +- * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. +- * (http://www.friendlyarm.com) +- * +- * Copyright (c) 2018 Collabora Ltd. +- * Copyright (c) 2019 Arm Ltd. +- */ +- +-/dts-v1/; +-#include "rk3399-nanopi4.dtsi" +- +-/ { +- model = "FriendlyElec NanoPi M4"; +- compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399"; +- +- vdd_5v: vdd-5v { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_5v"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc5v0_core: vcc5v0-core { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_core"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_5v>; +- }; +- +- vcc5v0_usb1: vcc5v0-usb1 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_usb1"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc5v0_usb2: vcc5v0-usb2 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_usb2"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- }; +-}; +- +-&vcc3v3_sys { +- vin-supply = <&vcc5v0_core>; +-}; +- +-&u2phy0_host { +- phy-supply = <&vcc5v0_usb1>; +-}; +- +-&u2phy1_host { +- phy-supply = <&vcc5v0_usb2>; +-}; +- +-&vbus_typec { +- regulator-always-on; +- vin-supply = <&vdd_5v>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-nanopi-m4b.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-nanopi-m4b.dts +deleted file mode 100644 +index 72182c58cc46..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-nanopi-m4b.dts ++++ /dev/null +@@ -1,52 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * FriendlyElec NanoPi M4B board device tree source +- * +- * Copyright (c) 2020 Chen-Yu Tsai +- */ +- +-/dts-v1/; +-#include "rk3399-nanopi-m4.dts" +- +-/ { +- model = "FriendlyElec NanoPi M4B"; +- compatible = "friendlyarm,nanopi-m4b", "rockchip,rk3399"; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 1>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1500000>; +- poll-interval = <100>; +- +- recovery { +- label = "Recovery"; +- linux,code = ; +- press-threshold-microvolt = <18000>; +- }; +- }; +-}; +- +-/* No USB type-C PD power manager */ +-/delete-node/ &fusb0; +- +-&i2c4 { +- status = "disabled"; +-}; +- +-&u2phy0_host { +- phy-supply = <&vcc5v0_usb2>; +-}; +- +-&u2phy0_otg { +- phy-supply = <&vbus_typec>; +-}; +- +-&u2phy1_otg { +- phy-supply = <&vcc5v0_usb1>; +-}; +- +-&vbus_typec { +- enable-active-high; +- gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-nanopi-neo4.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-nanopi-neo4.dts +deleted file mode 100644 +index 195410b089b9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-nanopi-neo4.dts ++++ /dev/null +@@ -1,50 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (C) 2019 Amarula Solutions B.V. +- * Author: Jagan Teki +- */ +- +-/dts-v1/; +- +-#include "rk3399-nanopi4.dtsi" +- +-/ { +- model = "FriendlyARM NanoPi NEO4"; +- compatible = "friendlyarm,nanopi-neo4", "rockchip,rk3399"; +- +- vdd_5v: vdd-5v { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_5v"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc5v0_core: vcc5v0-core { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_core"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_5v>; +- }; +- +- vcc5v0_usb1: vcc5v0-usb1 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_usb1"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- }; +-}; +- +-&vcc3v3_sys { +- vin-supply = <&vcc5v0_core>; +-}; +- +-&u2phy0_host { +- phy-supply = <&vcc5v0_usb1>; +-}; +- +-&vbus_typec { +- regulator-always-on; +- vin-supply = <&vdd_5v>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-nanopi-r4s.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-nanopi-r4s.dts +deleted file mode 100644 +index cef4d18b599d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-nanopi-r4s.dts ++++ /dev/null +@@ -1,133 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * FriendlyElec NanoPC-T4 board device tree source +- * +- * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. +- * (http://www.friendlyarm.com) +- * +- * Copyright (c) 2018 Collabora Ltd. +- * +- * Copyright (c) 2020 Jensen Huang +- * Copyright (c) 2020 Marty Jones +- * Copyright (c) 2021 Tianling Shen +- */ +- +-/dts-v1/; +-#include "rk3399-nanopi4.dtsi" +- +-/ { +- model = "FriendlyElec NanoPi R4S"; +- compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; +- +- /delete-node/ display-subsystem; +- +- gpio-leds { +- pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; +- +- /delete-node/ led-0; +- +- lan_led: led-lan { +- gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; +- label = "green:lan"; +- }; +- +- sys_led: led-sys { +- gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; +- label = "red:power"; +- default-state = "on"; +- }; +- +- wan_led: led-wan { +- gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; +- label = "green:wan"; +- }; +- }; +- +- gpio-keys { +- pinctrl-0 = <&reset_button_pin>; +- +- /delete-node/ power; +- +- reset { +- debounce-interval = <50>; +- gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; +- label = "reset"; +- linux,code = ; +- }; +- }; +- +- vdd_5v: vdd-5v { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_5v"; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&emmc_phy { +- status = "disabled"; +-}; +- +-&i2c4 { +- status = "disabled"; +-}; +- +-&pcie0 { +- max-link-speed = <1>; +- num-lanes = <1>; +- vpcie3v3-supply = <&vcc3v3_sys>; +-}; +- +-&pinctrl { +- gpio-leds { +- /delete-node/ status-led-pin; +- +- lan_led_pin: lan-led-pin { +- rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- sys_led_pin: sys-led-pin { +- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- wan_led_pin: wan-led-pin { +- rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- rockchip-key { +- /delete-node/ power-key; +- +- reset_button_pin: reset-button-pin { +- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +- +-&sdhci { +- status = "disabled"; +-}; +- +-&sdio0 { +- status = "disabled"; +-}; +- +-&u2phy0_host { +- phy-supply = <&vdd_5v>; +-}; +- +-&u2phy1_host { +- status = "disabled"; +-}; +- +-&uart0 { +- status = "disabled"; +-}; +- +-&usbdrd_dwc3_0 { +- dr_mode = "host"; +-}; +- +-&vcc3v3_sys { +- vin-supply = <&vcc5v0_sys>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-nanopi4.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-nanopi4.dtsi +deleted file mode 100644 +index 8c0ff6c96e03..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-nanopi4.dtsi ++++ /dev/null +@@ -1,761 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * RK3399-based FriendlyElec boards device tree source +- * +- * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd +- * +- * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. +- * (http://www.friendlyarm.com) +- * +- * Copyright (c) 2018 Collabora Ltd. +- * Copyright (c) 2019 Arm Ltd. +- */ +- +-/dts-v1/; +-#include +-#include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" +- +-/ { +- aliases { +- mmc0 = &sdio0; +- mmc1 = &sdmmc; +- mmc2 = &sdhci; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- clkin_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "clkin_gmac"; +- #clock-cells = <0>; +- }; +- +- vcc3v3_sys: vcc3v3-sys { +- compatible = "regulator-fixed"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc3v3_sys"; +- }; +- +- vcc5v0_sys: vcc5v0-sys { +- compatible = "regulator-fixed"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-name = "vcc5v0_sys"; +- vin-supply = <&vdd_5v>; +- }; +- +- /* switched by pmic_sleep */ +- vcc1v8_s3: vcc1v8-s3 { +- compatible = "regulator-fixed"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc1v8_s3"; +- vin-supply = <&vcc_1v8>; +- }; +- +- vcc3v0_sd: vcc3v0-sd { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc0_pwr_h>; +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc3v0_sd"; +- vin-supply = <&vcc3v3_sys>; +- }; +- +- /* +- * Really, this is supplied by vcc_1v8, and vcc1v8_s3 only +- * drives the enable pin, but we can't quite model that. +- */ +- vcca0v9_s3: vcca0v9-s3 { +- compatible = "regulator-fixed"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-name = "vcca0v9_s3"; +- vin-supply = <&vcc1v8_s3>; +- }; +- +- /* As above, actually supplied by vcc3v3_sys */ +- vcca1v8_s3: vcca1v8-s3 { +- compatible = "regulator-fixed"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcca1v8_s3"; +- vin-supply = <&vcc1v8_s3>; +- }; +- +- vbus_typec: vbus-typec { +- compatible = "regulator-fixed"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-name = "vbus_typec"; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- pinctrl-names = "default"; +- pinctrl-0 = <&power_key>; +- +- power { +- debounce-interval = <100>; +- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; +- label = "GPIO Key Power"; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds: gpio-leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&status_led_pin>; +- +- status_led: led-0 { +- gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; +- label = "status_led"; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&rk808 1>; +- clock-names = "ext_clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_reg_on_h>; +- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&emmc_phy { +- status = "okay"; +-}; +- +-&gmac { +- assigned-clock-parents = <&clkin_gmac>; +- assigned-clocks = <&cru SCLK_RMII_SRC>; +- clock_in_out = "input"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>; +- phy-handle = <&rtl8211e>; +- phy-mode = "rgmii"; +- phy-supply = <&vcc3v3_s3>; +- tx_delay = <0x28>; +- rx_delay = <0x11>; +- status = "okay"; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtl8211e: ethernet-phy@1 { +- reg = <1>; +- interrupt-parent = <&gpio3>; +- interrupts = ; +- reset-assert-us = <10000>; +- reset-deassert-us = <30000>; +- reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c7>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_cec>; +- status = "okay"; +-}; +- +-&hdmi_sound { +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- i2c-scl-rising-time-ns = <160>; +- i2c-scl-falling-time-ns = <30>; +- status = "okay"; +- +- vdd_cpu_b: regulator@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- fcs,suspend-voltage-selector = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cpu_b_sleep>; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vdd_cpu_b"; +- regulator-ramp-delay = <1000>; +- vin-supply = <&vcc3v3_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: regulator@41 { +- compatible = "silergy,syr828"; +- reg = <0x41>; +- fcs,suspend-voltage-selector = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpu_sleep>; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vdd_gpu"; +- regulator-ramp-delay = <1000>; +- vin-supply = <&vcc3v3_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- clock-output-names = "xin32k", "rtc_clko_wifi"; +- #clock-cells = <1>; +- interrupt-parent = <&gpio1>; +- interrupts = <21 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vcc3v3_sys>; +- vcc2-supply = <&vcc3v3_sys>; +- vcc3-supply = <&vcc3v3_sys>; +- vcc4-supply = <&vcc3v3_sys>; +- vcc6-supply = <&vcc3v3_sys>; +- vcc7-supply = <&vcc3v3_sys>; +- vcc8-supply = <&vcc3v3_sys>; +- vcc9-supply = <&vcc3v3_sys>; +- vcc10-supply = <&vcc3v3_sys>; +- vcc11-supply = <&vcc3v3_sys>; +- vcc12-supply = <&vcc3v3_sys>; +- vddio-supply = <&vcc_3v0>; +- +- regulators { +- vdd_center: DCDC_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-name = "vdd_center"; +- regulator-ramp-delay = <6001>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_l: DCDC_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-name = "vdd_cpu_l"; +- regulator-ramp-delay = <6001>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc_ddr"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_1v8: DCDC_REG4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc_1v8"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc1v8_cam: LDO_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc1v8_cam"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v0_touch: LDO_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc3v0_touch"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc1v8_pmupll: LDO_REG3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc1v8_pmupll"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc_sdio: LDO_REG4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-init-microvolt = <3000000>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc_sdio"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcca3v0_codec: LDO_REG5 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcca3v0_codec"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v5: LDO_REG6 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-name = "vcc_1v5"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1500000>; +- }; +- }; +- +- vcca1v8_codec: LDO_REG7 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcca1v8_codec"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_3v0: LDO_REG8 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-name = "vcc_3v0"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc3v3_s3: SWITCH_REG1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc3v3_s3"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v3_s0: SWITCH_REG2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vcc3v3_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <200000>; +- i2c-scl-rising-time-ns = <150>; +- i2c-scl-falling-time-ns = <30>; +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c4 { +- clock-frequency = <400000>; +- i2c-scl-rising-time-ns = <160>; +- i2c-scl-falling-time-ns = <30>; +- status = "okay"; +- +- fusb0: typec-portc@22 { +- compatible = "fcs,fusb302"; +- reg = <0x22>; +- interrupt-parent = <&gpio1>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&fusb0_int>; +- vbus-supply = <&vbus_typec>; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +-}; +- +-&i2s2 { +- status = "okay"; +-}; +- +-&io_domains { +- bt656-supply = <&vcc_1v8>; +- audio-supply = <&vcca1v8_codec>; +- sdmmc-supply = <&vcc_sdio>; +- gpio1830-supply = <&vcc_3v0>; +- status = "okay"; +-}; +- +-&pcie_phy { +- assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; +- assigned-clock-rates = <100000000>; +- assigned-clocks = <&cru SCLK_PCIEPHY_REF>; +- status = "okay"; +-}; +- +-&pcie0 { +- num-lanes = <2>; +- vpcie0v9-supply = <&vcca0v9_s3>; +- vpcie1v8-supply = <&vcca1v8_s3>; +- status = "okay"; +-}; +- +-&pinctrl { +- fusb30x { +- fusb0_int: fusb0-int { +- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- gpio-leds { +- status_led_pin: status-led-pin { +- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- gmac { +- phy_intb: phy-intb { +- rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- phy_rstb: phy-rstb { +- rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- cpu_b_sleep: cpu-b-sleep { +- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- gpu_sleep: gpu-sleep { +- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- pmic_int_l: pmic-int-l { +- rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- rockchip-key { +- power_key: power-key { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- sdio { +- bt_host_wake_l: bt-host-wake-l { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_reg_on_h: bt-reg-on-h { +- /* external pullup to VCC1V8_PMUPLL */ +- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_wake_l: bt-wake-l { +- rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- wifi_reg_on_h: wifi-reg_on-h { +- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdmmc { +- sdmmc0_det_l: sdmmc0-det-l { +- rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- sdmmc0_pwr_h: sdmmc0-pwr-h { +- rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pmu_io_domains { +- pmu1830-supply = <&vcc_3v0>; +- status = "okay"; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&pwm2 { +- pinctrl-names = "active"; +- pinctrl-0 = <&pwm2_pin_pull_down>; +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vcca1v8_s3>; +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- mmc-hs200-1_8v; +- non-removable; +- status = "okay"; +-}; +- +-&sdio0 { +- bus-width = <4>; +- cap-sd-highspeed; +- cap-sdio-irq; +- keep-power-in-suspend; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; +- sd-uhs-sdr104; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; +- sd-uhs-sdr104; +- vmmc-supply = <&vcc3v0_sd>; +- vqmmc-supply = <&vcc_sdio>; +- status = "okay"; +-}; +- +-&tcphy0 { +- status = "okay"; +-}; +- +-&tcphy1 { +- status = "okay"; +-}; +- +-&tsadc { +- /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-mode = <1>; +- /* tshut polarity 0:LOW 1:HIGH */ +- rockchip,hw-tshut-polarity = <1>; +- status = "okay"; +-}; +- +-&u2phy0 { +- status = "okay"; +-}; +- +-&u2phy0_host { +- status = "okay"; +-}; +- +-&u2phy0_otg { +- status = "okay"; +-}; +- +-&u2phy1 { +- status = "okay"; +-}; +- +-&u2phy1_host { +- status = "okay"; +-}; +- +-&u2phy1_otg { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&rk808 1>; +- clock-names = "lpo"; +- device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; +- max-speed = <4000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; +- vbat-supply = <&vcc3v3_sys>; +- vddio-supply = <&vcc_1v8>; +- }; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usbdrd3_0 { +- status = "okay"; +-}; +- +-&usbdrd3_1 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_0 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_1 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-op1-opp.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-op1-opp.dtsi +deleted file mode 100644 +index 69cc9b05baa5..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-op1-opp.dtsi ++++ /dev/null +@@ -1,141 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd +- */ +- +-/ { +- cluster0_opp: opp-table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp00 { +- opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <800000>; +- clock-latency-ns = <40000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <825000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <850000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <900000>; +- }; +- opp04 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <975000>; +- }; +- opp05 { +- opp-hz = /bits/ 64 <1416000000>; +- opp-microvolt = <1100000>; +- }; +- opp06 { +- opp-hz = /bits/ 64 <1512000000>; +- opp-microvolt = <1150000>; +- }; +- }; +- +- cluster1_opp: opp-table1 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp00 { +- opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <800000>; +- clock-latency-ns = <40000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <800000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <825000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <850000>; +- }; +- opp04 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <900000>; +- }; +- opp05 { +- opp-hz = /bits/ 64 <1416000000>; +- opp-microvolt = <975000>; +- }; +- opp06 { +- opp-hz = /bits/ 64 <1608000000>; +- opp-microvolt = <1050000>; +- }; +- opp07 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <1150000>; +- }; +- opp08 { +- opp-hz = /bits/ 64 <2016000000>; +- opp-microvolt = <1250000>; +- }; +- }; +- +- gpu_opp_table: opp-table2 { +- compatible = "operating-points-v2"; +- +- opp00 { +- opp-hz = /bits/ 64 <200000000>; +- opp-microvolt = <800000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <297000000>; +- opp-microvolt = <800000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <825000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <850000>; +- }; +- opp04 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <925000>; +- }; +- opp05 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <1075000>; +- }; +- }; +-}; +- +-&cpu_l0 { +- operating-points-v2 = <&cluster0_opp>; +-}; +- +-&cpu_l1 { +- operating-points-v2 = <&cluster0_opp>; +-}; +- +-&cpu_l2 { +- operating-points-v2 = <&cluster0_opp>; +-}; +- +-&cpu_l3 { +- operating-points-v2 = <&cluster0_opp>; +-}; +- +-&cpu_b0 { +- operating-points-v2 = <&cluster1_opp>; +-}; +- +-&cpu_b1 { +- operating-points-v2 = <&cluster1_opp>; +-}; +- +-&gpu { +- operating-points-v2 = <&gpu_opp_table>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-opp.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-opp.dtsi +deleted file mode 100644 +index da41cd81ebb7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-opp.dtsi ++++ /dev/null +@@ -1,133 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd +- */ +- +-/ { +- cluster0_opp: opp-table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp00 { +- opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <825000 825000 1250000>; +- clock-latency-ns = <40000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <825000 825000 1250000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <850000 850000 1250000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <925000 925000 1250000>; +- }; +- opp04 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <1000000 1000000 1250000>; +- }; +- opp05 { +- opp-hz = /bits/ 64 <1416000000>; +- opp-microvolt = <1125000 1125000 1250000>; +- }; +- }; +- +- cluster1_opp: opp-table1 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp00 { +- opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <825000 825000 1250000>; +- clock-latency-ns = <40000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <825000 825000 1250000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <825000 825000 1250000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <875000 875000 1250000>; +- }; +- opp04 { +- opp-hz = /bits/ 64 <1200000000>; +- opp-microvolt = <950000 950000 1250000>; +- }; +- opp05 { +- opp-hz = /bits/ 64 <1416000000>; +- opp-microvolt = <1025000 1025000 1250000>; +- }; +- opp06 { +- opp-hz = /bits/ 64 <1608000000>; +- opp-microvolt = <1100000 1100000 1250000>; +- }; +- opp07 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <1200000 1200000 1250000>; +- }; +- }; +- +- gpu_opp_table: opp-table2 { +- compatible = "operating-points-v2"; +- +- opp00 { +- opp-hz = /bits/ 64 <200000000>; +- opp-microvolt = <825000 825000 1150000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <297000000>; +- opp-microvolt = <825000 825000 1150000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <825000 825000 1150000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <875000 875000 1150000>; +- }; +- opp04 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <925000 925000 1150000>; +- }; +- opp05 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <1100000 1100000 1150000>; +- }; +- }; +-}; +- +-&cpu_l0 { +- operating-points-v2 = <&cluster0_opp>; +-}; +- +-&cpu_l1 { +- operating-points-v2 = <&cluster0_opp>; +-}; +- +-&cpu_l2 { +- operating-points-v2 = <&cluster0_opp>; +-}; +- +-&cpu_l3 { +- operating-points-v2 = <&cluster0_opp>; +-}; +- +-&cpu_b0 { +- operating-points-v2 = <&cluster1_opp>; +-}; +- +-&cpu_b1 { +- operating-points-v2 = <&cluster1_opp>; +-}; +- +-&gpu { +- operating-points-v2 = <&gpu_opp_table>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-orangepi.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-orangepi.dts +deleted file mode 100644 +index 04b54abea3cc..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-orangepi.dts ++++ /dev/null +@@ -1,894 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. +- */ +- +-/dts-v1/; +- +-#include "dt-bindings/pwm/pwm.h" +-#include "dt-bindings/input/input.h" +-#include "dt-bindings/usb/pd.h" +-#include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" +- +-/ { +- model = "Orange Pi RK3399 Board"; +- compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399"; +- +- aliases { +- mmc0 = &sdio0; +- mmc1 = &sdmmc; +- mmc2 = &sdhci; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- clkin_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "clkin_gmac"; +- #clock-cells = <0>; +- }; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 1>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1800000>; +- poll-interval = <100>; +- +- button-up { +- label = "Volume Up"; +- linux,code = ; +- press-threshold-microvolt = <100000>; +- }; +- +- button-down { +- label = "Volume Down"; +- linux,code = ; +- press-threshold-microvolt = <300000>; +- }; +- +- back { +- label = "Back"; +- linux,code = ; +- press-threshold-microvolt = <985000>; +- }; +- +- menu { +- label = "Menu"; +- linux,code = ; +- press-threshold-microvolt = <1314000>; +- }; +- }; +- +- dc_12v: dc-12v { +- compatible = "regulator-fixed"; +- regulator-name = "dc_12v"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- keys: gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- +- power { +- debounce-interval = <100>; +- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; +- label = "GPIO Power"; +- linux,code = ; +- linux,input-type = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_btn>; +- wakeup-source; +- }; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&rk808 1>; +- clock-names = "ext_clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_reg_on_h>; +- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; +- }; +- +- /* switched by pmic_sleep */ +- vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc1v8_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_1v8>; +- }; +- +- vcc3v0_sd: vcc3v0-sd { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc0_pwr_h>; +- regulator-boot-on; +- regulator-max-microvolt = <3000000>; +- regulator-min-microvolt = <3000000>; +- regulator-name = "vcc3v0_sd"; +- vin-supply = <&vcc3v3_sys>; +- }; +- +- vcc3v3_sys: vcc3v3-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc5v0_host: vcc5v0-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_host_en>; +- regulator-name = "vcc5v0_host"; +- regulator-always-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vbus_typec: vbus-typec-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_typec_en>; +- regulator-name = "vbus_typec"; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_sys: vcc-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&dc_12v>; +- }; +- +- vdd_log: vdd-log { +- compatible = "pwm-regulator"; +- pwms = <&pwm2 0 25000 1>; +- regulator-name = "vdd_log"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- vin-supply = <&vcc_sys>; +- }; +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&emmc_phy { +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_RMII_SRC>; +- assigned-clock-parents = <&clkin_gmac>; +- clock_in_out = "input"; +- phy-supply = <&vcc3v3_s3>; +- phy-mode = "rgmii"; +- phy-handle = <&rtl8211e>; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>; +- tx_delay = <0x28>; +- rx_delay = <0x11>; +- status = "okay"; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtl8211e: ethernet-phy@1 { +- reg = <1>; +- interrupt-parent = <&gpio3>; +- interrupts = ; +- reset-assert-us = <10000>; +- reset-deassert-us = <30000>; +- reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- status = "okay"; +-}; +- +-&hdmi_sound { +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- i2c-scl-rising-time-ns = <168>; +- i2c-scl-falling-time-ns = <4>; +- status = "okay"; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio1>; +- interrupts = <21 IRQ_TYPE_LEVEL_LOW>; +- #clock-cells = <1>; +- clock-output-names = "rtc_clko_soc", "rtc_clko_wifi"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vcc3v3_sys>; +- vcc2-supply = <&vcc3v3_sys>; +- vcc3-supply = <&vcc3v3_sys>; +- vcc4-supply = <&vcc3v3_sys>; +- vcc6-supply = <&vcc3v3_sys>; +- vcc7-supply = <&vcc3v3_sys>; +- vcc8-supply = <&vcc3v3_sys>; +- vcc9-supply = <&vcc3v3_sys>; +- vcc10-supply = <&vcc3v3_sys>; +- vcc11-supply = <&vcc3v3_sys>; +- vcc12-supply = <&vcc3v3_sys>; +- vddio-supply = <&vcc_3v0>; +- +- regulators { +- vdd_center: DCDC_REG1 { +- regulator-name = "vdd_center"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <6001>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_l: DCDC_REG2 { +- regulator-name = "vdd_cpu_l"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <700000>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <6001>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_1v8: DCDC_REG4 { +- regulator-name = "vcc_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc1v8_dvp: LDO_REG1 { +- regulator-name = "vcc1v8_dvp"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3400000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v0_tp: LDO_REG2 { +- regulator-name = "vcc3v0_tp"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3400000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc1v8_pmupll: LDO_REG3 { +- regulator-name = "vcc1v8_pmupll"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <2500000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc_sdio: LDO_REG4 { +- regulator-name = "vcc_sdio"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3400000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcca3v0_codec: LDO_REG5 { +- regulator-name = "vcca3v0_codec"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3400000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v5: LDO_REG6 { +- regulator-name = "vcc_1v5"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <2500000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1500000>; +- }; +- }; +- +- vcca1v8_codec: LDO_REG7 { +- regulator-name = "vcca1v8_codec"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <2500000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_3v0: LDO_REG8 { +- regulator-name = "vcc_3v0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3400000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc3v3_s3: SWITCH_REG1 { +- regulator-name = "vcc3v3_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v3_s0: SWITCH_REG2 { +- regulator-name = "vcc3v3_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +- +- vdd_cpu_b: regulator@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- fcs,suspend-voltage-selector = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&cpu_b_sleep>; +- regulator-name = "vdd_cpu_b"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc3v3_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: regulator@41 { +- compatible = "silergy,syr828"; +- reg = <0x41>; +- fcs,suspend-voltage-selector = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&gpu_sleep>; +- regulator-name = "vdd_gpu"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc3v3_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +-}; +- +-&i2c1 { +- i2c-scl-rising-time-ns = <450>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +-}; +- +-&i2c3 { +- i2c-scl-rising-time-ns = <450>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +-}; +- +-&i2c4 { +- clock-frequency = <400000>; +- i2c-scl-rising-time-ns = <450>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +- +- ak09911@c { +- compatible = "asahi-kasei,ak09911"; +- reg = <0x0c>; +- vdd-supply = <&vcc3v3_s3>; +- vid-supply = <&vcc3v3_s3>; +- }; +- +- mpu6500@68 { +- compatible = "invensense,mpu6500"; +- reg = <0x68>; +- interrupt-parent = <&gpio1>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&gsensor_int_l>; +- vddio-supply = <&vcc3v3_s3>; +- }; +- +- lsm6ds3@6a { +- compatible = "st,lsm6ds3"; +- reg = <0x6a>; +- interrupt-parent = <&gpio1>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&gyr_int_l>; +- vdd-supply = <&vcc3v3_s3>; +- vddio-supply = <&vcc3v3_s3>; +- }; +- +- cm32181@10 { +- compatible = "capella,cm32181"; +- reg = <0x10>; +- interrupt-parent = <&gpio4>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&light_int_l>; +- vdd-supply = <&vcc3v3_s3>; +- }; +- +- fusb302@22 { +- compatible = "fcs,fusb302"; +- reg = <0x22>; +- interrupt-parent = <&gpio1>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&chg_cc_int_l>; +- vbus-supply = <&vbus_typec>; +- +- typec_con: connector { +- compatible = "usb-c-connector"; +- data-role = "host"; +- label = "USB-C"; +- op-sink-microwatt = <1000000>; +- power-role = "dual"; +- sink-pdos = +- ; +- source-pdos = +- ; +- try-power-role = "sink"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- typec_hs: endpoint { +- remote-endpoint = <&u2phy0_typec_hs>; +- }; +- }; +- port@1 { +- reg = <1>; +- typec_ss: endpoint { +- remote-endpoint = <&tcphy0_typec_ss>; +- }; +- }; +- port@2 { +- reg = <2>; +- typec_dp: endpoint { +- remote-endpoint = <&tcphy0_typec_dp>; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&io_domains { +- status = "okay"; +- bt656-supply = <&vcc_3v0>; +- audio-supply = <&vcca1v8_codec>; +- sdmmc-supply = <&vcc_sdio>; +- gpio1830-supply = <&vcc_3v0>; +-}; +- +-&pmu_io_domains { +- status = "okay"; +- pmu1830-supply = <&vcc_3v0>; +-}; +- +-&pinctrl { +- buttons { +- pwr_btn: pwr-btn { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- gmac { +- phy_intb: phy-intb { +- rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- phy_rstb: phy-rstb { +- rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- cpu_b_sleep: cpu-b-sleep { +- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- gpu_sleep: gpu-sleep { +- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- pmic_int_l: pmic-int-l { +- rockchip,pins = +- <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- sd { +- sdmmc0_pwr_h: sdmmc0-pwr-h { +- rockchip,pins = +- <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb2 { +- vcc5v0_host_en: vcc5v0-host-en { +- rockchip,pins = +- <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- vcc5v0_typec_en: vcc5v0-typec-en { +- rockchip,pins = +- <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdio-pwrseq { +- wifi_reg_on_h: wifi-reg-on-h { +- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- wifi { +- wifi_host_wake_l: wifi-host-wake-l { +- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- bluetooth { +- bt_reg_on_h: bt-enable-h { +- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_host_wake_l: bt-host-wake-l { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_wake_l: bt-wake-l { +- rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- mpu6500 { +- gsensor_int_l: gsensor-int-l { +- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- lsm6ds3 { +- gyr_int_l: gyr-int-l { +- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- cm32181 { +- light_int_l: light-int-l { +- rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- fusb302 { +- chg_cc_int_l: chg-cc-int-l { +- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vcca1v8_s3>; +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- non-removable; +- status = "okay"; +-}; +- +-&sdio0 { +- bus-width = <4>; +- cap-sd-highspeed; +- cap-sdio-irq; +- clock-frequency = <50000000>; +- disable-wp; +- keep-power-in-suspend; +- max-frequency = <50000000>; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; +- sd-uhs-sdr104; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- interrupt-names = "host-wake"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_host_wake_l>; +- }; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; +- clock-frequency = <150000000>; +- disable-wp; +- max-frequency = <150000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +- vmmc-supply = <&vcc3v0_sd>; +- vqmmc-supply = <&vcc_sdio>; +- status = "okay"; +-}; +- +-&tcphy0 { +- status = "okay"; +-}; +- +-&tcphy0_dp { +- port { +- tcphy0_typec_dp: endpoint { +- remote-endpoint = <&typec_dp>; +- }; +- }; +-}; +- +-&tcphy0_usb3 { +- port { +- tcphy0_typec_ss: endpoint { +- remote-endpoint = <&typec_ss>; +- }; +- }; +-}; +- +-&tcphy1 { +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <1>; +- rockchip,hw-tshut-polarity = <1>; +- status = "okay"; +-}; +- +-&u2phy0 { +- status = "okay"; +- +- u2phy0_otg: otg-port { +- phy-supply = <&vbus_typec>; +- status = "okay"; +- }; +- +- u2phy0_host: host-port { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +- }; +- +- port { +- u2phy0_typec_hs: endpoint { +- remote-endpoint = <&typec_hs>; +- }; +- }; +-}; +- +-&u2phy1 { +- status = "okay"; +- +- u2phy1_otg: otg-port { +- status = "okay"; +- }; +- +- u2phy1_host: host-port { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&rk808 1>; +- clock-names = "lpo"; +- device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>; +- vbat-supply = <&vcc3v3_sys>; +- vddio-supply = <&vcc_1v8>; +- }; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&usbdrd3_0 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_0 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&usbdrd3_1 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_1 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-pinebook-pro.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-pinebook-pro.dts +deleted file mode 100644 +index 9e5d07f5712e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-pinebook-pro.dts ++++ /dev/null +@@ -1,1122 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. +- * Copyright (c) 2018 Akash Gajjar +- * Copyright (c) 2020 Tobias Schramm +- */ +- +-/dts-v1/; +-#include +-#include +-#include +-#include +-#include +-#include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" +- +-/ { +- model = "Pine64 Pinebook Pro"; +- compatible = "pine64,pinebook-pro", "rockchip,rk3399"; +- +- aliases { +- mmc0 = &sdio0; +- mmc1 = &sdmmc; +- mmc2 = &sdhci; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- backlight: edp-backlight { +- compatible = "pwm-backlight"; +- power-supply = <&vcc_12v>; +- pwms = <&pwm0 0 740740 0>; +- }; +- +- bat: battery { +- compatible = "simple-battery"; +- charge-full-design-microamp-hours = <9800000>; +- voltage-max-design-microvolt = <4350000>; +- voltage-min-design-microvolt = <3000000>; +- }; +- +- edp_panel: edp-panel { +- compatible = "boe,nv140fhmn49"; +- backlight = <&backlight>; +- enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&panel_en_pin>; +- power-supply = <&vcc3v3_panel>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- panel_in_edp: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&edp_out_panel>; +- }; +- }; +- }; +- }; +- +- /* +- * Use separate nodes for gpio-keys to allow for selective deactivation +- * of wakeup sources via sysfs without disabling the whole key +- */ +- gpio-key-lid { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&lidbtn_pin>; +- +- lid { +- debounce-interval = <20>; +- gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>; +- label = "Lid"; +- linux,code = ; +- linux,input-type = ; +- wakeup-event-action = ; +- wakeup-source; +- }; +- }; +- +- gpio-key-power { +- compatible = "gpio-keys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwrbtn_pin>; +- +- power { +- debounce-interval = <20>; +- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; +- label = "Power"; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_led_pin &slp_led_pin>; +- +- green_led: led-0 { +- color = ; +- default-state = "on"; +- function = LED_FUNCTION_POWER; +- gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; +- label = "green:power"; +- }; +- +- red_led: led-1 { +- color = ; +- default-state = "off"; +- function = LED_FUNCTION_STANDBY; +- gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; +- label = "red:standby"; +- panic-indicator; +- retain-state-suspended; +- }; +- }; +- +- /* Power sequence for SDIO WiFi module */ +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&rk808 1>; +- clock-names = "ext_clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_enable_h_pin>; +- post-power-on-delay-ms = <100>; +- power-off-delay-us = <500000>; +- +- /* WL_REG_ON on module */ +- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; +- }; +- +- /* Audio components */ +- es8316-sound { +- compatible = "simple-audio-card"; +- pinctrl-names = "default"; +- pinctrl-0 = <&hp_det_pin>; +- simple-audio-card,name = "rockchip,es8316-codec"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,mclk-fs = <256>; +- +- simple-audio-card,widgets = +- "Microphone", "Mic Jack", +- "Headphone", "Headphones", +- "Speaker", "Speaker"; +- simple-audio-card,routing = +- "MIC1", "Mic Jack", +- "Headphones", "HPOL", +- "Headphones", "HPOR", +- "Speaker Amplifier INL", "HPOL", +- "Speaker Amplifier INR", "HPOR", +- "Speaker", "Speaker Amplifier OUTL", +- "Speaker", "Speaker Amplifier OUTR"; +- +- simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; +- simple-audio-card,aux-devs = <&speaker_amp>; +- simple-audio-card,pin-switches = "Speaker"; +- +- simple-audio-card,cpu { +- sound-dai = <&i2s1>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&es8316>; +- }; +- }; +- +- speaker_amp: speaker-amplifier { +- compatible = "simple-audio-amplifier"; +- enable-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; +- sound-name-prefix = "Speaker Amplifier"; +- VCC-supply = <&pa_5v>; +- }; +- +- /* Power tree */ +- /* Root power source */ +- vcc_sysin: vcc-sysin { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sysin"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- /* Regulators supplied by vcc_sysin */ +- /* LCD backlight supply */ +- vcc_12v: vcc-12v { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_12v"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- vin-supply = <&vcc_sysin>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- /* Main 3.3 V supply */ +- vcc3v3_sys: wifi_bat: vcc3v3-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc_sysin>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- /* 5 V USB power supply */ +- vcc5v0_usb: pa_5v: vcc5v0-usb-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_5v_pin>; +- regulator-name = "vcc5v0_usb"; +- regulator-always-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc_sysin>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- /* RK3399 logic supply */ +- vdd_log: vdd-log { +- compatible = "pwm-regulator"; +- pwms = <&pwm2 0 25000 1>; +- regulator-name = "vdd_log"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- vin-supply = <&vcc_sysin>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- /* Regulators supplied by vcc3v3_sys */ +- /* 0.9 V supply, always on */ +- vcc_0v9: vcc-0v9 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_0v9"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- vin-supply = <&vcc3v3_sys>; +- }; +- +- /* S3 1.8 V supply, switched by vcc1v8_s3 */ +- vcca1v8_s3: vcc1v8-s3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcca1v8_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc3v3_sys>; +- }; +- +- /* micro SD card power */ +- vcc3v0_sd: vcc3v0-sd { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc0_pwr_h_pin>; +- regulator-name = "vcc3v0_sd"; +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- vin-supply = <&vcc3v3_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- /* LCD panel power, called VCC3V3_S0 in schematic */ +- vcc3v3_panel: vcc3v3-panel { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcdvcc_en_pin>; +- regulator-name = "vcc3v3_panel"; +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-enable-ramp-delay = <100000>; +- vin-supply = <&vcc3v3_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- /* M.2 adapter power, switched by vcc1v8_s3 */ +- vcc3v3_ssd: vcc3v3-ssd { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_ssd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc3v3_sys>; +- }; +- +- /* Regulators supplied by vcc5v0_usb */ +- /* USB 3 port power supply regulator */ +- vcc5v0_otg: vcc5v0-otg { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_host_en_pin>; +- regulator-name = "vcc5v0_otg"; +- regulator-always-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc5v0_usb>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- /* Regulators supplied by vcc5v0_usb */ +- /* Type C port power supply regulator */ +- vbus_5vout: vbus_typec: vbus-5vout { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_typec0_en_pin>; +- regulator-name = "vbus_5vout"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc5v0_usb>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- /* Regulators supplied by vcc_1v8 */ +- /* Primary 0.9 V LDO */ +- vcca0v9_s3: vcca0v9-s3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc0v9_s3"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc_1v8>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- mains_charger: dc-charger { +- compatible = "gpio-charger"; +- charger-type = "mains"; +- gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; +- +- /* Also triggered by USB charger */ +- pinctrl-names = "default"; +- pinctrl-0 = <&dc_det_pin>; +- }; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&edp { +- force-hpd; +- pinctrl-names = "default"; +- pinctrl-0 = <&edp_hpd>; +- status = "okay"; +- +- ports { +- edp_out: port@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- edp_out_panel: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_in_edp>; +- }; +- }; +- }; +-}; +- +-&emmc_phy { +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&hdmi_sound { +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- i2c-scl-falling-time-ns = <4>; +- i2c-scl-rising-time-ns = <168>; +- status = "okay"; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- interrupt-parent = <&gpio3>; +- interrupts = <10 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l_pin>; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vcc_sysin>; +- vcc2-supply = <&vcc_sysin>; +- vcc3-supply = <&vcc_sysin>; +- vcc4-supply = <&vcc_sysin>; +- vcc6-supply = <&vcc_sysin>; +- vcc7-supply = <&vcc_sysin>; +- vcc8-supply = <&vcc3v3_sys>; +- vcc9-supply = <&vcc_sysin>; +- vcc10-supply = <&vcc_sysin>; +- vcc11-supply = <&vcc_sysin>; +- vcc12-supply = <&vcc3v3_sys>; +- vcc13-supply = <&vcc_sysin>; +- vcc14-supply = <&vcc_sysin>; +- +- regulators { +- /* rk3399 center logic supply */ +- vdd_center: DCDC_REG1 { +- regulator-name = "vdd_center"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_l: DCDC_REG2 { +- regulator-name = "vdd_cpu_l"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_1v8: vcc_wl: DCDC_REG4 { +- regulator-name = "vcc_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- /* not used */ +- LDO_REG1 { +- }; +- +- /* not used */ +- LDO_REG2 { +- }; +- +- vcc1v8_pmupll: LDO_REG3 { +- regulator-name = "vcc1v8_pmupll"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc_sdio: LDO_REG4 { +- regulator-name = "vcc_sdio"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcca3v0_codec: LDO_REG5 { +- regulator-name = "vcca3v0_codec"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v5: LDO_REG6 { +- regulator-name = "vcc_1v5"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1500000>; +- }; +- }; +- +- vcca1v8_codec: LDO_REG7 { +- regulator-name = "vcca1v8_codec"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_3v0: LDO_REG8 { +- regulator-name = "vcc_3v0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc3v3_s3: SWITCH_REG1 { +- regulator-name = "vcc3v3_s3"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v3_s0: SWITCH_REG2 { +- regulator-name = "vcc3v3_s0"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +- +- vdd_cpu_b: regulator@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- fcs,suspend-voltage-selector = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vsel1_pin>; +- regulator-name = "vdd_cpu_b"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- vin-supply = <&vcc_1v8>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: regulator@41 { +- compatible = "silergy,syr828"; +- reg = <0x41>; +- fcs,suspend-voltage-selector = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vsel2_pin>; +- regulator-name = "vdd_gpu"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- vin-supply = <&vcc_1v8>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- i2c-scl-falling-time-ns = <4>; +- i2c-scl-rising-time-ns = <168>; +- status = "okay"; +- +- es8316: es8316@11 { +- compatible = "everest,es8316"; +- reg = <0x11>; +- clocks = <&cru SCLK_I2S_8CH_OUT>; +- clock-names = "mclk"; +- #sound-dai-cells = <0>; +- }; +-}; +- +-&i2c3 { +- i2c-scl-falling-time-ns = <15>; +- i2c-scl-rising-time-ns = <450>; +- status = "okay"; +-}; +- +-&i2c4 { +- i2c-scl-falling-time-ns = <20>; +- i2c-scl-rising-time-ns = <600>; +- status = "okay"; +- +- fusb0: fusb30x@22 { +- compatible = "fcs,fusb302"; +- reg = <0x22>; +- interrupt-parent = <&gpio1>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&fusb0_int_pin>; +- vbus-supply = <&vbus_typec>; +- +- connector { +- compatible = "usb-c-connector"; +- data-role = "host"; +- label = "USB-C"; +- op-sink-microwatt = <1000000>; +- power-role = "dual"; +- sink-pdos = +- ; +- source-pdos = +- ; +- try-power-role = "sink"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- usbc_hs: endpoint { +- remote-endpoint = +- <&u2phy0_typec_hs>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- usbc_ss: endpoint { +- remote-endpoint = +- <&tcphy0_typec_ss>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- +- usbc_dp: endpoint { +- remote-endpoint = +- <&tcphy0_typec_dp>; +- }; +- }; +- }; +- }; +- }; +- +- cw2015@62 { +- compatible = "cellwise,cw2015"; +- reg = <0x62>; +- cellwise,battery-profile = /bits/ 8 < +- 0x17 0x67 0x80 0x73 0x6E 0x6C 0x6B 0x63 +- 0x77 0x51 0x5C 0x58 0x50 0x4C 0x48 0x36 +- 0x15 0x0C 0x0C 0x19 0x5B 0x7D 0x6F 0x69 +- 0x69 0x5B 0x0C 0x29 0x20 0x40 0x52 0x59 +- 0x57 0x56 0x54 0x4F 0x3B 0x1F 0x7F 0x17 +- 0x06 0x1A 0x30 0x5A 0x85 0x93 0x96 0x2D +- 0x48 0x77 0x9C 0xB3 0x80 0x52 0x94 0xCB +- 0x2F 0x00 0x64 0xA5 0xB5 0x11 0xF0 0x11 +- >; +- cellwise,monitor-interval-ms = <5000>; +- monitored-battery = <&bat>; +- power-supplies = <&mains_charger>, <&fusb0>; +- }; +-}; +- +-&i2s1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s_8ch_mclk_pin>, <&i2s1_2ch_bus>; +- rockchip,capture-channels = <8>; +- rockchip,playback-channels = <8>; +- status = "okay"; +-}; +- +-&io_domains { +- audio-supply = <&vcc_3v0>; +- gpio1830-supply = <&vcc_3v0>; +- sdmmc-supply = <&vcc_sdio>; +- status = "okay"; +-}; +- +-&pcie_phy { +- status = "okay"; +-}; +- +-&pcie0 { +- bus-scan-delay-ms = <1000>; +- ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; +- num-lanes = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_clkreqn_cpm>; +- vpcie0v9-supply = <&vcca0v9_s3>; +- vpcie1v8-supply = <&vcca1v8_s3>; +- vpcie3v3-supply = <&vcc3v3_ssd>; +- status = "okay"; +-}; +- +-&pinctrl { +- buttons { +- pwrbtn_pin: pwrbtn-pin { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- lidbtn_pin: lidbtn-pin { +- rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- dc-charger { +- dc_det_pin: dc-det-pin { +- rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- es8316 { +- hp_det_pin: hp-det-pin { +- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- fusb302x { +- fusb0_int_pin: fusb0-int-pin { +- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- i2s1 { +- i2s_8ch_mclk_pin: i2s-8ch-mclk-pin { +- rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>; +- }; +- }; +- +- lcd-panel { +- lcdvcc_en_pin: lcdvcc-en-pin { +- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- panel_en_pin: panel-en-pin { +- rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- lcd_panel_reset_pin: lcd-panel-reset-pin { +- rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- leds { +- pwr_led_pin: pwr-led-pin { +- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- slp_led_pin: slp-led-pin { +- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- pmic_int_l_pin: pmic-int-l-pin { +- rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- vsel1_pin: vsel1-pin { +- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- vsel2_pin: vsel2-pin { +- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- sdcard { +- sdmmc0_pwr_h_pin: sdmmc0-pwr-h-pin { +- rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- }; +- +- sdio-pwrseq { +- wifi_enable_h_pin: wifi-enable-h-pin { +- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb-typec { +- vcc5v0_typec0_en_pin: vcc5v0-typec0-en-pin { +- rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- usb2 { +- pwr_5v_pin: pwr-5v-pin { +- rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- vcc5v0_host_en_pin: vcc5v0-host-en-pin { +- rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- wireless-bluetooth { +- bt_wake_pin: bt-wake-pin { +- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_host_wake_pin: bt-host-wake-pin { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_reset_pin: bt-reset-pin { +- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pmu_io_domains { +- pmu1830-supply = <&vcc_3v0>; +- status = "okay"; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vcca1v8_s3>; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; +- disable-wp; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; +- sd-uhs-sdr104; +- vmmc-supply = <&vcc3v0_sd>; +- vqmmc-supply = <&vcc_sdio>; +- status = "okay"; +-}; +- +-&sdio0 { +- bus-width = <4>; +- cap-sd-highspeed; +- cap-sdio-irq; +- keep-power-in-suspend; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; +- sd-uhs-sdr104; +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- mmc-hs200-1_8v; +- non-removable; +- status = "okay"; +-}; +- +-&spi1 { +- max-freq = <10000000>; +- status = "okay"; +- +- spiflash: flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- m25p,fast-read; +- spi-max-frequency = <10000000>; +- }; +-}; +- +-&tcphy0 { +- status = "okay"; +-}; +- +-&tcphy0_dp { +- port { +- tcphy0_typec_dp: endpoint { +- remote-endpoint = <&usbc_dp>; +- }; +- }; +-}; +- +-&tcphy0_usb3 { +- port { +- tcphy0_typec_ss: endpoint { +- remote-endpoint = <&usbc_ss>; +- }; +- }; +-}; +- +-&tcphy1 { +- status = "okay"; +-}; +- +-&tsadc { +- /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-mode = <1>; +- /* tshut polarity 0:LOW 1:HIGH */ +- rockchip,hw-tshut-polarity = <1>; +- status = "okay"; +-}; +- +-&u2phy0 { +- status = "okay"; +- +- u2phy0_otg: otg-port { +- status = "okay"; +- }; +- +- u2phy0_host: host-port { +- phy-supply = <&vcc5v0_otg>; +- status = "okay"; +- }; +- +- port { +- u2phy0_typec_hs: endpoint { +- remote-endpoint = <&usbc_hs>; +- }; +- }; +-}; +- +-&u2phy1 { +- status = "okay"; +- +- u2phy1_otg: otg-port { +- status = "okay"; +- }; +- +- u2phy1_host: host-port { +- phy-supply = <&vcc5v0_otg>; +- status = "okay"; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm4345c5"; +- clocks = <&rk808 1>; +- clock-names = "lpo"; +- device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; +- max-speed = <1500000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_host_wake_pin &bt_wake_pin &bt_reset_pin>; +- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; +- vbat-supply = <&wifi_bat>; +- vddio-supply = <&vcc_wl>; +- }; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&usbdrd3_0 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_0 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usbdrd3_1 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_1 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-puma-haikou.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-puma-haikou.dts +deleted file mode 100644 +index 3ae5d727e367..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-puma-haikou.dts ++++ /dev/null +@@ -1,276 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH +- */ +- +-/dts-v1/; +-#include "rk3399-puma.dtsi" +- +-/ { +- model = "Theobroma Systems RK3399-Q7 SoM"; +- compatible = "tsd,rk3399-puma-haikou", "rockchip,rk3399"; +- +- aliases { +- mmc1 = &sdmmc; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>; +- +- sd_card_led: led-1 { +- label = "sd_card_led"; +- gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- }; +- }; +- +- i2s0-sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,name = "Haikou,I2S-codec"; +- simple-audio-card,mclk-fs = <512>; +- +- simple-audio-card,codec { +- clocks = <&sgtl5000_clk>; +- sound-dai = <&sgtl5000>; +- }; +- +- simple-audio-card,cpu { +- bitclock-master; +- frame-master; +- sound-dai = <&i2s0>; +- }; +- }; +- +- sgtl5000_clk: sgtl5000-oscillator { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24576000>; +- }; +- +- dc_12v: dc-12v { +- compatible = "regulator-fixed"; +- regulator-name = "dc_12v"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- vcc3v3_baseboard: vcc3v3-baseboard { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_baseboard"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&dc_12v>; +- }; +- +- vcc5v0_baseboard: vcc5v0-baseboard { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_baseboard"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&dc_12v>; +- }; +- +- vcc5v0_otg: vcc5v0-otg-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&otg_vbus_drv>; +- regulator-name = "vcc5v0_otg"; +- regulator-always-on; +- }; +- +- vdda_codec: vdda-codec { +- compatible = "regulator-fixed"; +- regulator-name = "vdda_codec"; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc5v0_baseboard>; +- }; +- +- vddd_codec: vddd-codec { +- compatible = "regulator-fixed"; +- regulator-name = "vddd_codec"; +- regulator-boot-on; +- regulator-min-microvolt = <1600000>; +- regulator-max-microvolt = <1600000>; +- vin-supply = <&vcc5v0_baseboard>; +- }; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +-}; +- +-&i2c2 { +- status = "okay"; +- clock-frequency = <400000>; +-}; +- +-&i2c3 { +- i2c-scl-rising-time-ns = <450>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +- clock-frequency = <400000>; +- +- sgtl5000: codec@a { +- compatible = "fsl,sgtl5000"; +- reg = <0x0a>; +- clocks = <&sgtl5000_clk>; +- #sound-dai-cells = <0>; +- VDDA-supply = <&vdda_codec>; +- VDDIO-supply = <&vdda_codec>; +- VDDD-supply = <&vddd_codec>; +- status = "okay"; +- }; +-}; +- +-&i2c6 { +- status = "okay"; +- clock-frequency = <400000>; +-}; +- +-&pcie_phy { +- status = "okay"; +-}; +- +-&pcie0 { +- ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; +- num-lanes = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_clkreqn_cpm>; +- status = "okay"; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&haikou_pin_hog>; +- +- hog { +- haikou_pin_hog: haikou-pin-hog { +- rockchip,pins = +- /* LID_BTN */ +- <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, +- /* BATLOW# */ +- <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, +- /* SLP_BTN# */ +- <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, +- /* BIOS_DISABLE# */ +- <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- leds { +- sd_card_led_pin: sd-card-led-pin { +- rockchip,pins = +- <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb2 { +- otg_vbus_drv: otg-vbus-drv { +- rockchip,pins = +- <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; +- disable-wp; +- max-frequency = <150000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +- vmmc-supply = <&vcc3v3_baseboard>; +- status = "okay"; +-}; +- +-&spi5 { +- status = "okay"; +-}; +- +-&tcphy0 { +- status = "okay"; +-}; +- +-&u2phy0 { +- status = "okay"; +-}; +- +-&usbdrd3_0 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_0 { +- dr_mode = "otg"; +- extcon = <&extcon_usb3>; +- status = "okay"; +-}; +- +-&u2phy0_host { +- phy-supply = <&vcc5v0_otg>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-puma.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-puma.dtsi +deleted file mode 100644 +index 08fa00364b42..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-puma.dtsi ++++ /dev/null +@@ -1,507 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH +- */ +- +-#include +-#include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" +- +-/ { +- aliases { +- mmc0 = &sdhci; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&module_led_pin>; +- +- module_led: led-0 { +- label = "module_led"; +- gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- panic-indicator; +- }; +- }; +- +- extcon_usb3: extcon-usb3 { +- compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb3_id>; +- }; +- +- clkin_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "clkin_gmac"; +- #clock-cells = <0>; +- }; +- +- vcc1v2_phy: vcc1v2-phy { +- compatible = "regulator-fixed"; +- regulator-name = "vcc1v2_phy"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc3v3_sys: vcc3v3-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc5v0_host: vcc5v0-host-regulator { +- compatible = "regulator-fixed"; +- gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; +- enable-active-low; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_host_en>; +- regulator-name = "vcc5v0_host"; +- regulator-always-on; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc5v0_sys: vcc5v0-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&emmc_phy { +- status = "okay"; +- drive-impedance-ohm = <33>; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_RMII_SRC>; +- assigned-clock-parents = <&clkin_gmac>; +- clock_in_out = "input"; +- phy-supply = <&vcc1v2_phy>; +- phy-mode = "rgmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 50000>; +- tx_delay = <0x10>; +- rx_delay = <0x10>; +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- i2c-scl-rising-time-ns = <168>; +- i2c-scl-falling-time-ns = <4>; +- clock-frequency = <400000>; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio1>; +- interrupts = <22 IRQ_TYPE_LEVEL_LOW>; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vcc5v0_sys>; +- vcc2-supply = <&vcc5v0_sys>; +- vcc3-supply = <&vcc5v0_sys>; +- vcc4-supply = <&vcc5v0_sys>; +- vcc6-supply = <&vcc5v0_sys>; +- vcc7-supply = <&vcc5v0_sys>; +- vcc8-supply = <&vcc3v3_sys>; +- vcc9-supply = <&vcc5v0_sys>; +- vcc10-supply = <&vcc5v0_sys>; +- vcc11-supply = <&vcc5v0_sys>; +- vcc12-supply = <&vcc3v3_sys>; +- vddio-supply = <&vcc1v8_pmu>; +- +- regulators { +- vdd_center: DCDC_REG1 { +- regulator-name = "vdd_center"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_l: DCDC_REG2 { +- regulator-name = "vdd_cpu_l"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_1v8: DCDC_REG4 { +- regulator-name = "vcc_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc_ldo1: LDO_REG1 { +- regulator-name = "vcc_ldo1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc1v8_hdmi: LDO_REG2 { +- regulator-name = "vcc1v8_hdmi"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc1v8_pmu: LDO_REG3 { +- regulator-name = "vcc1v8_pmu"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc_sd: LDO_REG4 { +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc_ldo5: LDO_REG5 { +- regulator-name = "vcc_ldo5"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ldo6: LDO_REG6 { +- regulator-name = "vcc_ldo6"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc0v9_hdmi: LDO_REG7 { +- regulator-name = "vcc0v9_hdmi"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_efuse: LDO_REG8 { +- regulator-name = "vcc_efuse"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v3_s3: SWITCH_REG1 { +- regulator-name = "vcc3v3_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v3_s0: SWITCH_REG2 { +- regulator-name = "vcc3v3_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +- +- vdd_gpu: regulator@60 { +- compatible = "fcs,fan53555"; +- reg = <0x60>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_gpu"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1230000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +- clock-frequency = <400000>; +- +- fan: fan@18 { +- compatible = "ti,amc6821"; +- reg = <0x18>; +- #cooling-cells = <2>; +- }; +- +- rtc_twi: rtc@6f { +- compatible = "isil,isl1208"; +- reg = <0x6f>; +- }; +-}; +- +-&i2c8 { +- status = "okay"; +- clock-frequency = <400000>; +- +- vdd_cpu_b: regulator@60 { +- compatible = "fcs,fan53555"; +- reg = <0x60>; +- vin-supply = <&vcc5v0_sys>; +- regulator-name = "vdd_cpu_b"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1230000>; +- regulator-ramp-delay = <1000>; +- fcs,suspend-voltage-selector = <1>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&i2s0 { +- pinctrl-0 = <&i2s0_2ch_bus>; +- rockchip,playback-channels = <2>; +- rockchip,capture-channels = <2>; +- status = "okay"; +-}; +- +-/* +- * As Q7 does not specify neither a global nor a RX clock for I2S these +- * signals are not used. Furthermore I2S0_LRCK_RX is used as GPIO. +- * Therefore we have to redefine the i2s0_2ch_bus definition to prevent +- * conflicts. +- */ +-&i2s0_2ch_bus { +- rockchip,pins = +- <3 RK_PD0 1 &pcfg_pull_none>, +- <3 RK_PD2 1 &pcfg_pull_none>, +- <3 RK_PD3 1 &pcfg_pull_none>, +- <3 RK_PD7 1 &pcfg_pull_none>; +-}; +- +-&io_domains { +- status = "okay"; +- bt656-supply = <&vcc_1v8>; +- audio-supply = <&vcc_1v8>; +- sdmmc-supply = <&vcc_sd>; +- gpio1830-supply = <&vcc_1v8>; +-}; +- +-&pmu_io_domains { +- status = "okay"; +- pmu1830-supply = <&vcc_1v8>; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&pinctrl { +- i2c8 { +- i2c8_xfer_a: i2c8-xfer { +- rockchip,pins = +- <1 RK_PC4 1 &pcfg_pull_up>, +- <1 RK_PC5 1 &pcfg_pull_up>; +- }; +- }; +- +- leds { +- module_led_pin: module-led-pin { +- rockchip,pins = +- <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = +- <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- usb2 { +- vcc5v0_host_en: vcc5v0-host-en { +- rockchip,pins = +- <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb3 { +- usb3_id: usb3-id { +- rockchip,pins = +- <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&sdhci { +- /* +- * Signal integrity isn't great at 200MHz but 100MHz has proven stable +- * enough. +- */ +- max-frequency = <100000000>; +- +- bus-width = <8>; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- non-removable; +- status = "okay"; +-}; +- +-&sdmmc { +- vqmmc-supply = <&vcc_sd>; +-}; +- +-&spi1 { +- status = "okay"; +- +- norflash: flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- }; +-}; +- +-&tcphy1 { +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <1>; +- rockchip,hw-tshut-polarity = <1>; +- status = "okay"; +-}; +- +-&u2phy1 { +- status = "okay"; +- +- u2phy1_otg: otg-port { +- status = "okay"; +- }; +- +- u2phy1_host: host-port { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +- }; +-}; +- +-&usbdrd3_1 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_1 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-roc-pc-mezzanine.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-roc-pc-mezzanine.dts +deleted file mode 100644 +index 9447c8724b65..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-roc-pc-mezzanine.dts ++++ /dev/null +@@ -1,111 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd +- * Copyright (c) 2019 Markus Reichl +- */ +- +-/dts-v1/; +-#include "rk3399-roc-pc.dtsi" +- +-/ { +- model = "Firefly ROC-RK3399-PC Mezzanine Board"; +- compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399"; +- +- aliases { +- mmc2 = &sdio0; +- }; +- +- /* MP8009 PoE PD */ +- poe_12v: poe-12v { +- compatible = "regulator-fixed"; +- regulator-name = "poe_12v"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- vcc3v3_ngff: vcc3v3-ngff { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_ngff"; +- enable-active-high; +- gpio = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc3v3_ngff_en>; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&sys_12v>; +- }; +- +- vcc3v3_pcie: vcc3v3-pcie { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_pcie"; +- enable-active-high; +- gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc3v3_pcie_en>; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&sys_12v>; +- }; +-}; +- +-&sys_12v { +- vin-supply = <&poe_12v>; +-}; +- +-&pcie_phy { +- status = "okay"; +-}; +- +-&pcie0 { +- ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; +- num-lanes = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_perst>; +- vpcie3v3-supply = <&vcc3v3_pcie>; +- vpcie1v8-supply = <&vcc1v8_pmu>; +- vpcie0v9-supply = <&vcca_0v9>; +- status = "okay"; +-}; +- +-&pinctrl { +- ngff { +- vcc3v3_ngff_en: vcc3v3-ngff-en { +- rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pcie { +- vcc3v3_pcie_en: vcc3v3-pcie-en { +- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- pcie_perst: pcie-perst { +- rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&sdio0 { +- bus-width = <4>; +- cap-sd-highspeed; +- cap-sdio-irq; +- keep-power-in-suspend; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; +- sd-uhs-sdr104; +- vmmc-supply = <&vcc3v3_ngff>; +- vqmmc-supply = <&vcc_1v8>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-roc-pc.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-roc-pc.dts +deleted file mode 100644 +index cd4195425309..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-roc-pc.dts ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd +- */ +- +-/dts-v1/; +-#include "rk3399-roc-pc.dtsi" +- +-/ { +- model = "Firefly ROC-RK3399-PC Board"; +- compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-roc-pc.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-roc-pc.dtsi +deleted file mode 100644 +index d1aaf8e83391..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-roc-pc.dtsi ++++ /dev/null +@@ -1,843 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd +- */ +- +-/dts-v1/; +-#include +-#include +-#include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" +- +-/ { +- model = "Firefly ROC-RK3399-PC Board"; +- compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; +- +- aliases { +- mmc0 = &sdmmc; +- mmc1 = &sdhci; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm0 0 25000 0>; +- }; +- +- clkin_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "clkin_gmac"; +- #clock-cells = <0>; +- }; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 1>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1500000>; +- poll-interval = <100>; +- +- recovery { +- label = "Recovery"; +- linux,code = ; +- press-threshold-microvolt = <18000>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_key_l>; +- +- power { +- debounce-interval = <100>; +- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; +- label = "GPIO Key Power"; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&ir_int>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&work_led_pin>, <&diy_led_pin>, <&yellow_led_pin>; +- +- work_led: led-0 { +- label = "green:work"; +- gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- linux,default-trigger = "heartbeat"; +- }; +- +- diy_led: led-1 { +- label = "red:diy"; +- gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "mmc2"; +- }; +- +- yellow_led: led-2 { +- label = "yellow:yellow-led"; +- gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- linux,default-trigger = "mmc1"; +- }; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&rk808 1>; +- clock-names = "ext_clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_enable_h>; +- +- /* +- * On the module itself this is one of these (depending +- * on the actual card populated): +- * - SDIO_RESET_L_WL_REG_ON +- * - PDN (power down when low) +- */ +- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; +- }; +- +- vcc_vbus_typec0: vcc-vbus-typec0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_vbus_typec0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- sys_12v: sys-12v { +- compatible = "regulator-fixed"; +- regulator-name = "sys_12v"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&dc_12v>; +- }; +- +- /* switched by pmic_sleep */ +- vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc1v8_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_1v8>; +- }; +- +- vcc3v0_sd: vcc3v0-sd { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc3v0_sd_en>; +- regulator-name = "vcc3v0_sd"; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- vin-supply = <&vcc3v3_sys>; +- }; +- +- vcc3v3_sys: vcc3v3-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&sys_12v>; +- }; +- +- vcca_0v9: vcca-0v9 { +- compatible = "regulator-fixed"; +- regulator-name = "vcca_0v9"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- vin-supply = <&vcc3v3_sys>; +- }; +- +- /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ +- vcc5v0_host: vcc5v0-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_host_en &hub_rst>; +- regulator-name = "vcc5v0_host"; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_vbus_typec1: vcc-vbus-typec1 { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc_vbus_typec1_en>; +- regulator-name = "vcc_vbus_typec1"; +- regulator-always-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_sys: vcc-sys { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc_sys_en>; +- regulator-name = "vcc_sys"; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&sys_12v>; +- }; +- +- vdd_log: vdd-log { +- compatible = "pwm-regulator"; +- pwms = <&pwm2 0 25000 1>; +- regulator-name = "vdd_log"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <450000>; +- regulator-max-microvolt = <1400000>; +- pwm-supply = <&vcc3v3_sys>; +- }; +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&emmc_phy { +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_RMII_SRC>; +- assigned-clock-parents = <&clkin_gmac>; +- clock_in_out = "input"; +- phy-supply = <&vcc_lan>; +- phy-mode = "rgmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 50000>; +- tx_delay = <0x28>; +- rx_delay = <0x11>; +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_cec>; +- status = "okay"; +-}; +- +-&hdmi_sound { +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- i2c-scl-rising-time-ns = <168>; +- i2c-scl-falling-time-ns = <4>; +- status = "okay"; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio1>; +- interrupts = <21 IRQ_TYPE_LEVEL_LOW>; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vcc3v3_sys>; +- vcc2-supply = <&vcc3v3_sys>; +- vcc3-supply = <&vcc3v3_sys>; +- vcc4-supply = <&vcc3v3_sys>; +- vcc6-supply = <&vcc3v3_sys>; +- vcc7-supply = <&vcc3v3_sys>; +- vcc8-supply = <&vcc3v3_sys>; +- vcc9-supply = <&vcc3v3_sys>; +- vcc10-supply = <&vcc3v3_sys>; +- vcc11-supply = <&vcc3v3_sys>; +- vcc12-supply = <&vcc3v3_sys>; +- vcc13-supply = <&vcc3v3_sys>; +- vcc14-supply = <&vcc3v3_sys>; +- vddio-supply = <&vcc_3v0>; +- +- regulators { +- vdd_center: DCDC_REG1 { +- regulator-name = "vdd_center"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_l: DCDC_REG2 { +- regulator-name = "vdd_cpu_l"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_1v8: DCDC_REG4 { +- regulator-name = "vcc_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcca1v8_codec: LDO_REG1 { +- regulator-name = "vcca1v8_codec"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc1v8_hdmi: LDO_REG2 { +- regulator-name = "vcc1v8_hdmi"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc1v8_pmu: LDO_REG3 { +- regulator-name = "vcc1v8_pmu"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc_sdio: LDO_REG4 { +- regulator-name = "vcc_sdio"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcca3v0_codec: LDO_REG5 { +- regulator-name = "vcca3v0_codec"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v5: LDO_REG6 { +- regulator-name = "vcc_1v5"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1500000>; +- }; +- }; +- +- vcca0v9_hdmi: LDO_REG7 { +- regulator-name = "vcca0v9_hdmi"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_3v0: LDO_REG8 { +- regulator-name = "vcc_3v0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc3v3_s3: vcc_lan: SWITCH_REG1 { +- regulator-name = "vcc3v3_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v3_s0: SWITCH_REG2 { +- regulator-name = "vcc3v3_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +- +- vdd_cpu_b: regulator@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- fcs,suspend-voltage-selector = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vsel1_pin>; +- regulator-name = "vdd_cpu_b"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc3v3_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: regulator@41 { +- compatible = "silergy,syr828"; +- reg = <0x41>; +- fcs,suspend-voltage-selector = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vsel2_pin>; +- regulator-name = "vdd_gpu"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc3v3_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +-}; +- +-&i2c1 { +- i2c-scl-rising-time-ns = <300>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +-}; +- +-&i2c3 { +- i2c-scl-rising-time-ns = <450>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +-}; +- +-&i2c4 { +- i2c-scl-rising-time-ns = <600>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- +- fusb1: usb-typec@22 { +- compatible = "fcs,fusb302"; +- reg = <0x22>; +- interrupt-parent = <&gpio1>; +- interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&fusb1_int>; +- vbus-supply = <&vcc_vbus_typec1>; +- status = "okay"; +- }; +-}; +- +-&i2c7 { +- i2c-scl-rising-time-ns = <600>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- +- fusb0: usb-typec@22 { +- compatible = "fcs,fusb302"; +- reg = <0x22>; +- interrupt-parent = <&gpio1>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&fusb0_int>; +- vbus-supply = <&vcc_vbus_typec0>; +- status = "okay"; +- }; +- +- mp8859: regulator@66 { +- compatible = "mps,mp8859"; +- reg = <0x66>; +- dc_12v: mp8859_dcdc { +- regulator-name = "dc_12v"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_vbus_typec0>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <12000000>; +- }; +- }; +- }; +-}; +- +-&i2s0 { +- rockchip,playback-channels = <8>; +- rockchip,capture-channels = <8>; +- status = "okay"; +-}; +- +-&i2s1 { +- rockchip,playback-channels = <2>; +- rockchip,capture-channels = <2>; +- status = "okay"; +-}; +- +-&i2s2 { +- status = "okay"; +-}; +- +-&io_domains { +- audio-supply = <&vcca1v8_codec>; +- bt656-supply = <&vcc_3v0>; +- gpio1830-supply = <&vcc_3v0>; +- sdmmc-supply = <&vcc_sdio>; +- status = "okay"; +-}; +- +-&pmu_io_domains { +- pmu1830-supply = <&vcc_3v0>; +- status = "okay"; +-}; +- +-&pinctrl { +- buttons { +- pwr_key_l: pwr-key-l { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- ir { +- ir_int: ir-int { +- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- lcd-panel { +- lcd_panel_reset: lcd-panel-reset { +- rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- leds { +- diy_led_pin: diy-led-pin { +- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- work_led_pin: work-led-pin { +- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- yellow_led_pin: yellow-led-pin { +- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- vsel1_pin: vsel1-pin { +- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- vsel2_pin: vsel2-pin { +- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- sdio-pwrseq { +- wifi_enable_h: wifi-enable-h { +- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdmmc { +- vcc3v0_sd_en: vcc3v0-sd-en { +- rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- usb2 { +- vcc5v0_host_en: vcc5v0-host-en { +- rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- vcc_sys_en: vcc-sys-en { +- rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- hub_rst: hub-rst { +- rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>; +- }; +- }; +- +- usb-typec { +- vcc_vbus_typec1_en: vcc-vbus-typec1-en { +- rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- fusb30x { +- fusb0_int: fusb0-int { +- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- fusb1_int: fusb1-int { +- rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vcca1v8_s3>; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-sd-highspeed; +- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; +- disable-wp; +- max-frequency = <150000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; +- sd-uhs-sdr104; +- vmmc-supply = <&vcc3v0_sd>; +- vqmmc-supply = <&vcc_sdio>; +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- non-removable; +- status = "okay"; +-}; +- +-&spi1 { +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <10000000>; +- }; +-}; +- +-&tcphy0 { +- status = "okay"; +-}; +- +-&tcphy1 { +- status = "okay"; +-}; +- +-&tsadc { +- /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-mode = <1>; +- /* tshut polarity 0:LOW 1:HIGH */ +- rockchip,hw-tshut-polarity = <1>; +- status = "okay"; +-}; +- +-&u2phy0 { +- status = "okay"; +- +- u2phy0_otg: otg-port { +- phy-supply = <&vcc_vbus_typec0>; +- status = "okay"; +- }; +- +- u2phy0_host: host-port { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +- }; +-}; +- +-&u2phy1 { +- status = "okay"; +- +- u2phy1_otg: otg-port { +- phy-supply = <&vcc_vbus_typec1>; +- status = "okay"; +- }; +- +- u2phy1_host: host-port { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts>; +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&usbdrd3_0 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_0 { +- status = "okay"; +-}; +- +-&usbdrd3_1 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_1 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rock-pi-4.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rock-pi-4.dtsi +deleted file mode 100644 +index 100a769165ef..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rock-pi-4.dtsi ++++ /dev/null +@@ -1,706 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Akash Gajjar +- * Copyright (c) 2019 Pragnesh Patel +- */ +- +-/dts-v1/; +-#include +-#include +-#include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" +- +-/ { +- aliases { +- mmc0 = &sdmmc; +- mmc1 = &sdhci; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- clkin_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "clkin_gmac"; +- #clock-cells = <0>; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&rk808 1>; +- clock-names = "ext_clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_enable_h>; +- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; +- }; +- +- vcc12v_dcin: dc-12v { +- compatible = "regulator-fixed"; +- regulator-name = "vcc12v_dcin"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- vcc5v0_sys: vcc-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc12v_dcin>; +- }; +- +- vcc_0v9: vcc-0v9 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_0v9"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- vin-supply = <&vcc3v3_sys>; +- }; +- +- vcc3v3_pcie: vcc3v3-pcie-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_pwr_en>; +- regulator-name = "vcc3v3_pcie"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc3v3_sys: vcc3v3-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc5v0_host: vcc5v0-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_host_en>; +- regulator-name = "vcc5v0_host"; +- regulator-always-on; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc5v0_typec: vcc5v0-typec-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_typec_en>; +- regulator-name = "vcc5v0_typec"; +- regulator-always-on; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc_lan: vcc3v3-phy-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_lan"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- vdd_log: vdd-log { +- compatible = "pwm-regulator"; +- pwms = <&pwm2 0 25000 1>; +- regulator-name = "vdd_log"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- vin-supply = <&vcc5v0_sys>; +- }; +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&emmc_phy { +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_RMII_SRC>; +- assigned-clock-parents = <&clkin_gmac>; +- clock_in_out = "input"; +- phy-supply = <&vcc_lan>; +- phy-mode = "rgmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 50000>; +- tx_delay = <0x28>; +- rx_delay = <0x11>; +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_cec>; +- status = "okay"; +-}; +- +-&hdmi_sound { +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- i2c-scl-rising-time-ns = <168>; +- i2c-scl-falling-time-ns = <4>; +- status = "okay"; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio1>; +- interrupts = <21 IRQ_TYPE_LEVEL_LOW>; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vcc5v0_sys>; +- vcc2-supply = <&vcc5v0_sys>; +- vcc3-supply = <&vcc5v0_sys>; +- vcc4-supply = <&vcc5v0_sys>; +- vcc6-supply = <&vcc5v0_sys>; +- vcc7-supply = <&vcc5v0_sys>; +- vcc8-supply = <&vcc3v3_sys>; +- vcc9-supply = <&vcc5v0_sys>; +- vcc10-supply = <&vcc5v0_sys>; +- vcc11-supply = <&vcc5v0_sys>; +- vcc12-supply = <&vcc3v3_sys>; +- vddio-supply = <&vcc_1v8>; +- +- regulators { +- vdd_center: DCDC_REG1 { +- regulator-name = "vdd_center"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_l: DCDC_REG2 { +- regulator-name = "vdd_cpu_l"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_1v8: DCDC_REG4 { +- regulator-name = "vcc_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc1v8_codec: LDO_REG1 { +- regulator-name = "vcc1v8_codec"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc1v8_hdmi: LDO_REG2 { +- regulator-name = "vcc1v8_hdmi"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcca_1v8: LDO_REG3 { +- regulator-name = "vcca_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc_sdio: LDO_REG4 { +- regulator-name = "vcc_sdio"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcca3v0_codec: LDO_REG5 { +- regulator-name = "vcca3v0_codec"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v5: LDO_REG6 { +- regulator-name = "vcc_1v5"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1500000>; +- }; +- }; +- +- vcc0v9_hdmi: LDO_REG7 { +- regulator-name = "vcc0v9_hdmi"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_3v0: LDO_REG8 { +- regulator-name = "vcc_3v0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc_cam: SWITCH_REG1 { +- regulator-name = "vcc_cam"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_mipi: SWITCH_REG2 { +- regulator-name = "vcc_mipi"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +- +- vdd_cpu_b: regulator@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- fcs,suspend-voltage-selector = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vsel1_pin>; +- regulator-name = "vdd_cpu_b"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: regulator@41 { +- compatible = "silergy,syr828"; +- reg = <0x41>; +- fcs,suspend-voltage-selector = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vsel2_pin>; +- regulator-name = "vdd_gpu"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +-}; +- +-&i2c1 { +- i2c-scl-rising-time-ns = <300>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +-}; +- +-&i2c3 { +- i2c-scl-rising-time-ns = <450>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +-}; +- +-&i2c4 { +- i2c-scl-rising-time-ns = <600>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +-}; +- +-&i2s0 { +- pinctrl-0 = <&i2s0_2ch_bus>; +- rockchip,capture-channels = <2>; +- rockchip,playback-channels = <2>; +- status = "okay"; +-}; +- +-&i2s1 { +- rockchip,playback-channels = <2>; +- rockchip,capture-channels = <2>; +- status = "okay"; +-}; +- +-&i2s2 { +- status = "okay"; +-}; +- +-&io_domains { +- status = "okay"; +- +- bt656-supply = <&vcc_3v0>; +- audio-supply = <&vcc1v8_codec>; +- sdmmc-supply = <&vcc_sdio>; +- gpio1830-supply = <&vcc_3v0>; +-}; +- +-&pmu_io_domains { +- status = "okay"; +- +- pmu1830-supply = <&vcc_3v0>; +-}; +- +-&pcie_phy { +- status = "okay"; +-}; +- +-&pcie0 { +- ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; +- num-lanes = <4>; +- pinctrl-0 = <&pcie_clkreqnb_cpm>; +- pinctrl-names = "default"; +- vpcie0v9-supply = <&vcc_0v9>; +- vpcie1v8-supply = <&vcc_1v8>; +- vpcie3v3-supply = <&vcc3v3_pcie>; +- status = "okay"; +-}; +- +-&pinctrl { +- bt { +- bt_enable_h: bt-enable-h { +- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_host_wake_l: bt-host-wake-l { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_wake_l: bt-wake-l { +- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pcie { +- pcie_pwr_en: pcie-pwr-en { +- rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdio0 { +- sdio0_bus4: sdio0-bus4 { +- rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up_20ma>, +- <2 RK_PC5 1 &pcfg_pull_up_20ma>, +- <2 RK_PC6 1 &pcfg_pull_up_20ma>, +- <2 RK_PC7 1 &pcfg_pull_up_20ma>; +- }; +- +- sdio0_cmd: sdio0-cmd { +- rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up_20ma>; +- }; +- +- sdio0_clk: sdio0-clk { +- rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none_20ma>; +- }; +- }; +- +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- vsel1_pin: vsel1-pin { +- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- vsel2_pin: vsel2-pin { +- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- usb-typec { +- vcc5v0_typec_en: vcc5v0-typec-en { +- rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- usb2 { +- vcc5v0_host_en: vcc5v0-host-en { +- rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- wifi { +- wifi_enable_h: wifi-enable-h { +- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- wifi_host_wake_l: wifi-host-wake-l { +- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&saradc { +- status = "okay"; +- +- vref-supply = <&vcc_1v8>; +-}; +- +-&sdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- bus-width = <4>; +- clock-frequency = <50000000>; +- cap-sdio-irq; +- cap-sd-highspeed; +- keep-power-in-suspend; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; +- sd-uhs-sdr104; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; +- disable-wp; +- max-frequency = <150000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>; +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- non-removable; +- status = "okay"; +-}; +- +-&tcphy0 { +- status = "okay"; +-}; +- +-&tcphy1 { +- status = "okay"; +-}; +- +-&tsadc { +- status = "okay"; +- +- /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-mode = <1>; +- /* tshut polarity 0:LOW 1:HIGH */ +- rockchip,hw-tshut-polarity = <1>; +-}; +- +-&u2phy0 { +- status = "okay"; +- +- u2phy0_otg: otg-port { +- status = "okay"; +- }; +- +- u2phy0_host: host-port { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +- }; +-}; +- +-&u2phy1 { +- status = "okay"; +- +- u2phy1_otg: otg-port { +- status = "okay"; +- }; +- +- u2phy1_host: host-port { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&usbdrd3_0 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_0 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&usbdrd3_1 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_1 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rock-pi-4a.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rock-pi-4a.dts +deleted file mode 100644 +index 89f2af5e111d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rock-pi-4a.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Akash Gajjar +- * Copyright (c) 2019 Pragnesh Patel +- */ +- +-/dts-v1/; +-#include "rk3399-rock-pi-4.dtsi" +- +-/ { +- model = "Radxa ROCK Pi 4A"; +- compatible = "radxa,rockpi4a", "radxa,rockpi4", "rockchip,rk3399"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rock-pi-4b.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rock-pi-4b.dts +deleted file mode 100644 +index 6c63e617063c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rock-pi-4b.dts ++++ /dev/null +@@ -1,46 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Akash Gajjar +- * Copyright (c) 2019 Pragnesh Patel +- */ +- +-/dts-v1/; +-#include "rk3399-rock-pi-4.dtsi" +- +-/ { +- model = "Radxa ROCK Pi 4B"; +- compatible = "radxa,rockpi4b", "radxa,rockpi4", "rockchip,rk3399"; +- +- aliases { +- mmc2 = &sdio0; +- }; +-}; +- +-&sdio0 { +- status = "okay"; +- +- brcmf: wifi@1 { +- compatible = "brcm,bcm4329-fmac"; +- reg = <1>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- interrupt-names = "host-wake"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_host_wake_l>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&rk808 1>; +- clock-names = "ext_clock"; +- device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rock-pi-4c.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rock-pi-4c.dts +deleted file mode 100644 +index 99169bcd51c0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rock-pi-4c.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd +- * Copyright (c) 2019 Radxa Limited +- * Copyright (c) 2019 Amarula Solutions(India) +- */ +- +-/dts-v1/; +-#include "rk3399-rock-pi-4.dtsi" +- +-/ { +- model = "Radxa ROCK Pi 4C"; +- compatible = "radxa,rockpi4c", "radxa,rockpi4", "rockchip,rk3399"; +- +- aliases { +- mmc2 = &sdio0; +- }; +-}; +- +-&sdio0 { +- status = "okay"; +- +- brcmf: wifi@1 { +- compatible = "brcm,bcm4329-fmac"; +- reg = <1>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- interrupt-names = "host-wake"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_host_wake_l>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&rk808 1>; +- clock-names = "ext_clock"; +- device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; +- }; +-}; +- +-&vcc5v0_host { +- gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; +-}; +- +-&vcc5v0_host_en { +- rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rock960.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rock960.dts +deleted file mode 100644 +index 1a23e8f3cdf6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rock960.dts ++++ /dev/null +@@ -1,156 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Linaro Ltd. +- */ +- +-/dts-v1/; +-#include "rk3399-rock960.dtsi" +- +-/ { +- model = "96boards Rock960"; +- compatible = "vamrs,rock960", "rockchip,rk3399"; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&user_led1_pin>, <&user_led2_pin>, +- <&user_led3_pin>, <&user_led4_pin>, +- <&wlan_led_pin>, <&bt_led_pin>; +- +- user_led1: led-1 { +- label = "green:user1"; +- gpios = <&gpio4 RK_PC2 0>; +- linux,default-trigger = "heartbeat"; +- }; +- +- user_led2: led-2 { +- label = "green:user2"; +- gpios = <&gpio4 RK_PC6 0>; +- linux,default-trigger = "mmc0"; +- }; +- +- user_led3: led-3 { +- label = "green:user3"; +- gpios = <&gpio4 RK_PD0 0>; +- linux,default-trigger = "mmc1"; +- }; +- +- user_led4: led-4 { +- label = "green:user4"; +- gpios = <&gpio4 RK_PD4 0>; +- panic-indicator; +- linux,default-trigger = "none"; +- }; +- +- wlan_active_led: led-5 { +- label = "yellow:wlan"; +- gpios = <&gpio4 RK_PD5 0>; +- linux,default-trigger = "phy0tx"; +- default-state = "off"; +- }; +- +- bt_active_led: led-6 { +- label = "blue:bt"; +- gpios = <&gpio4 RK_PD6 0>; +- linux,default-trigger = "hci0-power"; +- default-state = "off"; +- }; +- }; +- +-}; +- +-&cpu_alert0 { +- temperature = <65000>; +-}; +- +-&cpu_thermal { +- sustainable-power = <1550>; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert1>; +- }; +- }; +-}; +- +-&pcie0 { +- ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; +-}; +- +-&pinctrl { +- leds { +- user_led1_pin: user-led1-pin { +- rockchip,pins = +- <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- user_led2_pin: user-led2-pin { +- rockchip,pins = +- <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- user_led3_pin: user-led3-pin { +- rockchip,pins = +- <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- user_led4_pin: user-led4-pin { +- rockchip,pins = +- <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- wlan_led_pin: wlan-led-pin { +- rockchip,pins = +- <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_led_pin: bt-led-pin { +- rockchip,pins = +- <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pcie { +- pcie_drv: pcie-drv { +- rockchip,pins = +- <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb2 { +- host_vbus_drv: host-vbus-drv { +- rockchip,pins = +- <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&spi0 { +- /* On Low speed expansion (LS-SPI0) */ +- status = "okay"; +-}; +- +-&spi4 { +- /* On High speed expansion (HS-SPI1) */ +- status = "okay"; +-}; +- +-&usbdrd_dwc3_0 { +- dr_mode = "otg"; +-}; +- +-&usbdrd_dwc3_1 { +- dr_mode = "host"; +-}; +- +-&vcc3v3_pcie { +- gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; +-}; +- +-&vcc5v0_host { +- gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rock960.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rock960.dtsi +deleted file mode 100644 +index 25dc61c26a94..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rock960.dtsi ++++ /dev/null +@@ -1,670 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Collabora Ltd. +- * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. +- * Copyright (c) 2018 Linaro Ltd. +- */ +- +-#include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" +- +-/ { +- aliases { +- mmc0 = &sdio0; +- mmc1 = &sdmmc; +- mmc2 = &sdhci; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&rk808 1>; +- clock-names = "ext_clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_enable_h>; +- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; +- }; +- +- vcc12v_dcin: vcc12v-dcin { +- compatible = "regulator-fixed"; +- regulator-name = "vcc12v_dcin"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc1v8_s0: vcc1v8-s0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc1v8_s0"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcc5v0_sys: vcc5v0-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- vin-supply = <&vcc12v_dcin>; +- }; +- +- vcc3v3_sys: vcc3v3-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_sys"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc3v3_pcie: vcc3v3-pcie-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_drv>; +- regulator-boot-on; +- regulator-name = "vcc3v3_pcie"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc3v3_sys>; +- }; +- +- vcc5v0_host: vcc5v0-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- pinctrl-names = "default"; +- pinctrl-0 = <&host_vbus_drv>; +- regulator-name = "vcc5v0_host"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc_0v9: vcc-0v9 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_0v9"; +- regulator-always-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- vin-supply = <&vcc3v3_sys>; +- }; +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&emmc_phy { +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_cec>; +- status = "okay"; +-}; +- +-&hdmi_sound { +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- i2c-scl-rising-time-ns = <168>; +- i2c-scl-falling-time-ns = <4>; +- status = "okay"; +- +- vdd_cpu_b: regulator@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_cpu_b"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- status = "okay"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: regulator@41 { +- compatible = "silergy,syr828"; +- reg = <0x41>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_gpu"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio1>; +- interrupts = <21 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- +- vcc1-supply = <&vcc5v0_sys>; +- vcc2-supply = <&vcc5v0_sys>; +- vcc3-supply = <&vcc5v0_sys>; +- vcc4-supply = <&vcc5v0_sys>; +- vcc6-supply = <&vcc5v0_sys>; +- vcc7-supply = <&vcc5v0_sys>; +- vcc8-supply = <&vcc3v3_sys>; +- vcc9-supply = <&vcc5v0_sys>; +- vcc10-supply = <&vcc5v0_sys>; +- vcc11-supply = <&vcc5v0_sys>; +- vcc12-supply = <&vcc3v3_sys>; +- vddio-supply = <&vcc_1v8>; +- +- regulators { +- vdd_center: DCDC_REG1 { +- regulator-name = "vdd_center"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_l: DCDC_REG2 { +- regulator-name = "vdd_cpu_l"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_1v8: DCDC_REG4 { +- regulator-name = "vcc_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc1v8_dvp: LDO_REG1 { +- regulator-name = "vcc1v8_dvp"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcca1v8_hdmi: LDO_REG2 { +- regulator-name = "vcca1v8_hdmi"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcca_1v8: LDO_REG3 { +- regulator-name = "vcca_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc_sd: LDO_REG4 { +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc3v0_sd: LDO_REG5 { +- regulator-name = "vcc3v0_sd"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc_1v5: LDO_REG6 { +- regulator-name = "vcc_1v5"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1500000>; +- }; +- }; +- +- vcca0v9_hdmi: LDO_REG7 { +- regulator-name = "vcca0v9_hdmi"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <900000>; +- }; +- }; +- +- vcc_3v0: LDO_REG8 { +- regulator-name = "vcc_3v0"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc3v3_s3: SWITCH_REG1 { +- regulator-name = "vcc3v3_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc3v3_s0: SWITCH_REG2 { +- regulator-name = "vcc3v3_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&i2s2 { +- status = "okay"; +-}; +- +-&io_domains { +- bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ +- audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ +- sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ +- gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ +- status = "okay"; +-}; +- +-&pcie_phy { +- status = "okay"; +-}; +- +-&pcie0 { +- num-lanes = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_clkreqn_cpm>; +- vpcie0v9-supply = <&vcc_0v9>; +- vpcie1v8-supply = <&vcca_1v8>; +- vpcie3v3-supply = <&vcc3v3_pcie>; +- status = "okay"; +-}; +- +-&pmu_io_domains { +- pmu1830-supply = <&vcc_1v8>; +- status = "okay"; +-}; +- +-&pinctrl { +- bt { +- bt_enable_h: bt-enable-h { +- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_host_wake_l: bt-host-wake-l { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_wake_l: bt-wake-l { +- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sdmmc { +- sdmmc_bus1: sdmmc-bus1 { +- rockchip,pins = +- <4 RK_PB0 1 &pcfg_pull_up_8ma>; +- }; +- +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = +- <4 RK_PB0 1 &pcfg_pull_up_8ma>, +- <4 RK_PB1 1 &pcfg_pull_up_8ma>, +- <4 RK_PB2 1 &pcfg_pull_up_8ma>, +- <4 RK_PB3 1 &pcfg_pull_up_8ma>; +- }; +- +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = +- <4 RK_PB4 1 &pcfg_pull_none_18ma>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = +- <4 RK_PB5 1 &pcfg_pull_up_8ma>; +- }; +- }; +- +- sdio0 { +- sdio0_bus4: sdio0-bus4 { +- rockchip,pins = +- <2 RK_PC4 1 &pcfg_pull_up_20ma>, +- <2 RK_PC5 1 &pcfg_pull_up_20ma>, +- <2 RK_PC6 1 &pcfg_pull_up_20ma>, +- <2 RK_PC7 1 &pcfg_pull_up_20ma>; +- }; +- +- sdio0_cmd: sdio0-cmd { +- rockchip,pins = +- <2 RK_PD0 1 &pcfg_pull_up_20ma>; +- }; +- +- sdio0_clk: sdio0-clk { +- rockchip,pins = +- <2 RK_PD1 1 &pcfg_pull_none_20ma>; +- }; +- }; +- +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = +- <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- vsel1_pin: vsel1-pin { +- rockchip,pins = +- <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- vsel2_pin: vsel2-pin { +- rockchip,pins = +- <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- sdio-pwrseq { +- wifi_enable_h: wifi-enable-h { +- rockchip,pins = +- <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- wifi { +- wifi_host_wake_l: wifi-host-wake-l { +- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&pwm3 { +- status = "okay"; +-}; +- +-&sdio0 { +- bus-width = <4>; +- clock-frequency = <50000000>; +- cap-sdio-irq; +- cap-sd-highspeed; +- keep-power-in-suspend; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; +- sd-uhs-sdr104; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- brcmf: wifi@1 { +- compatible = "brcm,bcm4329-fmac"; +- reg = <1>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- interrupt-names = "host-wake"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_host_wake_l>; +- }; +-}; +- +-&sdhci { +- bus-width = <8>; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- non-removable; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- clock-frequency = <100000000>; +- max-frequency = <100000000>; +- cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; +- disable-wp; +- sd-uhs-sdr104; +- vqmmc-supply = <&vcc_sd>; +- card-detect-delay = <800>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <1>; +- rockchip,hw-tshut-polarity = <1>; +- rockchip,hw-tshut-temp = <110000>; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&rk808 1>; +- clock-names = "ext_clock"; +- device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; +- }; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&tcphy0 { +- status = "okay"; +-}; +- +-&tcphy1 { +- status = "okay"; +-}; +- +-&u2phy0 { +- status = "okay"; +-}; +- +-&u2phy1 { +- status = "okay"; +-}; +- +-&u2phy0_host { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +-}; +- +-&u2phy1_host { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +-}; +- +-&u2phy0_otg { +- status = "okay"; +-}; +- +-&u2phy1_otg { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&usbdrd3_0 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_0 { +- status = "okay"; +-}; +- +-&usbdrd3_1 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_1 { +- status = "okay"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rockpro64-v2.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rockpro64-v2.dts +deleted file mode 100644 +index 304e3c51391c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rockpro64-v2.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. +- * Copyright (c) 2018 Akash Gajjar +- * Copyright (c) 2019 Katsuhiro Suzuki +- */ +- +-/dts-v1/; +-#include "rk3399-rockpro64.dtsi" +- +-/ { +- model = "Pine64 RockPro64 v2.0"; +- compatible = "pine64,rockpro64-v2.0", "pine64,rockpro64", "rockchip,rk3399"; +-}; +- +-&i2c1 { +- es8316: codec@10 { +- compatible = "everest,es8316"; +- reg = <0x10>; +- clocks = <&cru SCLK_I2S_8CH_OUT>; +- clock-names = "mclk"; +- #sound-dai-cells = <0>; +- +- port { +- es8316_p0_0: endpoint { +- remote-endpoint = <&i2s1_p0_0>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rockpro64.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rockpro64.dts +deleted file mode 100644 +index 4b42717800f7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rockpro64.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. +- * Copyright (c) 2018 Akash Gajjar +- * Copyright (c) 2019 Katsuhiro Suzuki +- */ +- +-/dts-v1/; +-#include "rk3399-rockpro64.dtsi" +- +-/ { +- model = "Pine64 RockPro64 v2.1"; +- compatible = "pine64,rockpro64-v2.1", "pine64,rockpro64", "rockchip,rk3399"; +-}; +- +-&i2c1 { +- es8316: codec@11 { +- compatible = "everest,es8316"; +- reg = <0x11>; +- clocks = <&cru SCLK_I2S_8CH_OUT>; +- clock-names = "mclk"; +- #sound-dai-cells = <0>; +- +- port { +- es8316_p0_0: endpoint { +- remote-endpoint = <&i2s1_p0_0>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rockpro64.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rockpro64.dtsi +deleted file mode 100644 +index 6bff8db7d33e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-rockpro64.dtsi ++++ /dev/null +@@ -1,870 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. +- * Copyright (c) 2018 Akash Gajjar +- */ +- +-#include +-#include +-#include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" +- +-/ { +- aliases { +- mmc0 = &sdio0; +- mmc1 = &sdmmc; +- mmc2 = &sdhci; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- clkin_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "clkin_gmac"; +- #clock-cells = <0>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwrbtn>; +- +- power { +- debounce-interval = <100>; +- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; +- label = "GPIO Key Power"; +- linux,code = ; +- wakeup-source; +- }; +- }; +- +- ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; +- pinctrl-0 = <&ir_int>; +- pinctrl-names = "default"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&work_led_pin>, <&diy_led_pin>; +- +- work_led: led-0 { +- label = "work"; +- default-state = "on"; +- gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; +- }; +- +- diy_led: led-1 { +- label = "diy"; +- default-state = "off"; +- gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- fan: pwm-fan { +- compatible = "pwm-fan"; +- #cooling-cells = <2>; +- fan-supply = <&vcc12v_dcin>; +- pwms = <&pwm1 0 50000 0>; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&rk808 1>; +- clock-names = "ext_clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_enable_h>; +- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; +- }; +- +- sound { +- compatible = "audio-graph-card"; +- label = "Analog"; +- dais = <&i2s1_p0>; +- }; +- +- sound-dit { +- compatible = "audio-graph-card"; +- label = "SPDIF"; +- dais = <&spdif_p0>; +- }; +- +- spdif-dit { +- compatible = "linux,spdif-dit"; +- #sound-dai-cells = <0>; +- +- port { +- dit_p0_0: endpoint { +- remote-endpoint = <&spdif_p0_0>; +- }; +- }; +- }; +- +- vcc12v_dcin: vcc12v-dcin { +- compatible = "regulator-fixed"; +- regulator-name = "vcc12v_dcin"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- /* switched by pmic_sleep */ +- vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc1v8_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_1v8>; +- }; +- +- /* micro SD card power */ +- vcc3v0_sd: vcc3v0-sd { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc0_pwr_h>; +- regulator-name = "vcc3v0_sd"; +- regulator-always-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- vin-supply = <&vcc3v3_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v3_pcie: vcc3v3-pcie-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_pwr_en>; +- regulator-name = "vcc3v3_pcie"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc12v_dcin>; +- }; +- +- vcc3v3_sys: vcc3v3-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ +- vcc5v0_host: vcc5v0-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_host_en>; +- regulator-name = "vcc5v0_host"; +- regulator-always-on; +- vin-supply = <&vcc5v0_usb>; +- }; +- +- vcc5v0_typec: vcc5v0-typec-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_typec_en>; +- regulator-name = "vcc5v0_typec"; +- regulator-always-on; +- vin-supply = <&vcc5v0_usb>; +- }; +- +- vcc5v0_sys: vcc5v0-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc12v_dcin>; +- }; +- +- vcc5v0_usb: vcc5v0-usb { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_usb"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc12v_dcin>; +- }; +- +- vdd_log: vdd-log { +- compatible = "pwm-regulator"; +- pwms = <&pwm2 0 25000 1>; +- regulator-name = "vdd_log"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1700000>; +- vin-supply = <&vcc5v0_sys>; +- }; +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&emmc_phy { +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_RMII_SRC>; +- assigned-clock-parents = <&clkin_gmac>; +- clock_in_out = "input"; +- phy-supply = <&vcc_lan>; +- phy-mode = "rgmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 50000>; +- tx_delay = <0x28>; +- rx_delay = <0x11>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_cec>; +- status = "okay"; +-}; +- +-&hdmi_sound { +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- i2c-scl-rising-time-ns = <168>; +- i2c-scl-falling-time-ns = <4>; +- status = "okay"; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio3>; +- interrupts = <10 IRQ_TYPE_LEVEL_LOW>; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vcc5v0_sys>; +- vcc2-supply = <&vcc5v0_sys>; +- vcc3-supply = <&vcc5v0_sys>; +- vcc4-supply = <&vcc5v0_sys>; +- vcc6-supply = <&vcc5v0_sys>; +- vcc7-supply = <&vcc5v0_sys>; +- vcc8-supply = <&vcc3v3_sys>; +- vcc9-supply = <&vcc5v0_sys>; +- vcc10-supply = <&vcc5v0_sys>; +- vcc11-supply = <&vcc5v0_sys>; +- vcc12-supply = <&vcc3v3_sys>; +- vddio-supply = <&vcca_1v8>; +- +- regulators { +- vdd_center: DCDC_REG1 { +- regulator-name = "vdd_center"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_l: DCDC_REG2 { +- regulator-name = "vdd_cpu_l"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_1v8: DCDC_REG4 { +- regulator-name = "vcc_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc1v8_dvp: LDO_REG1 { +- regulator-name = "vcc1v8_dvp"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v0_touch: LDO_REG2 { +- regulator-name = "vcc3v0_touch"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcca_1v8: LDO_REG3 { +- regulator-name = "vcca_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc_sdio: LDO_REG4 { +- regulator-name = "vcc_sdio"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcca3v0_codec: LDO_REG5 { +- regulator-name = "vcca3v0_codec"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v5: LDO_REG6 { +- regulator-name = "vcc_1v5"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1500000>; +- }; +- }; +- +- vcca1v8_codec: LDO_REG7 { +- regulator-name = "vcca1v8_codec"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_3v0: LDO_REG8 { +- regulator-name = "vcc_3v0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc3v3_s3: vcc_lan: SWITCH_REG1 { +- regulator-name = "vcc3v3_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v3_s0: SWITCH_REG2 { +- regulator-name = "vcc3v3_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +- +- vdd_cpu_b: regulator@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- fcs,suspend-voltage-selector = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vsel1_pin>; +- regulator-name = "vdd_cpu_b"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: regulator@41 { +- compatible = "silergy,syr828"; +- reg = <0x41>; +- fcs,suspend-voltage-selector = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vsel2_pin>; +- regulator-name = "vdd_gpu"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +-}; +- +-&i2c1 { +- i2c-scl-rising-time-ns = <300>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +-}; +- +-&i2c3 { +- i2c-scl-rising-time-ns = <450>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +-}; +- +-&i2c4 { +- i2c-scl-rising-time-ns = <600>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- +- fusb0: typec-portc@22 { +- compatible = "fcs,fusb302"; +- reg = <0x22>; +- interrupt-parent = <&gpio1>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&fusb0_int>; +- vbus-supply = <&vcc5v0_typec>; +- status = "okay"; +- }; +-}; +- +-&i2s0 { +- rockchip,playback-channels = <8>; +- rockchip,capture-channels = <8>; +- status = "okay"; +-}; +- +-&i2s1 { +- rockchip,playback-channels = <2>; +- rockchip,capture-channels = <2>; +- status = "okay"; +- +- i2s1_p0: port { +- i2s1_p0_0: endpoint { +- dai-format = "i2s"; +- mclk-fs = <256>; +- remote-endpoint = <&es8316_p0_0>; +- }; +- }; +-}; +- +-&i2s2 { +- status = "okay"; +-}; +- +-&io_domains { +- status = "okay"; +- +- bt656-supply = <&vcc1v8_dvp>; +- audio-supply = <&vcc_3v0>; +- sdmmc-supply = <&vcc_sdio>; +- gpio1830-supply = <&vcc_3v0>; +-}; +- +-&pcie0 { +- ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; +- num-lanes = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_perst>; +- vpcie12v-supply = <&vcc12v_dcin>; +- vpcie3v3-supply = <&vcc3v3_pcie>; +- status = "okay"; +-}; +- +-&pcie_phy { +- status = "okay"; +-}; +- +-&pmu_io_domains { +- pmu1830-supply = <&vcc_3v0>; +- status = "okay"; +-}; +- +-&pinctrl { +- bt { +- bt_enable_h: bt-enable-h { +- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- bt_host_wake_l: bt-host-wake-l { +- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- bt_wake_l: bt-wake-l { +- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- buttons { +- pwrbtn: pwrbtn { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- fusb302x { +- fusb0_int: fusb0-int { +- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- ir { +- ir_int: ir-int { +- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- leds { +- work_led_pin: work-led-pin { +- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- diy_led_pin: diy-led-pin { +- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pcie { +- pcie_perst: pcie-perst { +- rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- pcie_pwr_en: pcie-pwr-en { +- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- vsel1_pin: vsel1-pin { +- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- vsel2_pin: vsel2-pin { +- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- sdcard { +- sdmmc0_pwr_h: sdmmc0-pwr-h { +- rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- }; +- +- sdio-pwrseq { +- wifi_enable_h: wifi-enable-h { +- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb-typec { +- vcc5v0_typec_en: vcc5v0_typec_en { +- rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- usb2 { +- vcc5v0_host_en: vcc5v0-host-en { +- rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vcca1v8_s3>; +- status = "okay"; +-}; +- +-&sdio0 { +- bus-width = <4>; +- cap-sd-highspeed; +- cap-sdio-irq; +- disable-wp; +- keep-power-in-suspend; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; +- sd-uhs-sdr104; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-sd-highspeed; +- cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; +- disable-wp; +- max-frequency = <150000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; +- vmmc-supply = <&vcc3v0_sd>; +- vqmmc-supply = <&vcc_sdio>; +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- mmc-hs200-1_8v; +- non-removable; +- status = "okay"; +-}; +- +-&spdif { +- pinctrl-0 = <&spdif_bus_1>; +- +- spdif_p0: port { +- spdif_p0_0: endpoint { +- remote-endpoint = <&dit_p0_0>; +- }; +- }; +-}; +- +-&spi1 { +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <10000000>; +- }; +-}; +- +-&tcphy0 { +- status = "okay"; +-}; +- +-&tcphy1 { +- status = "okay"; +-}; +- +-&tsadc { +- /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-mode = <1>; +- /* tshut polarity 0:LOW 1:HIGH */ +- rockchip,hw-tshut-polarity = <1>; +- status = "okay"; +-}; +- +-&u2phy0 { +- status = "okay"; +- +- u2phy0_otg: otg-port { +- status = "okay"; +- }; +- +- u2phy0_host: host-port { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +- }; +-}; +- +-&u2phy1 { +- status = "okay"; +- +- u2phy1_otg: otg-port { +- status = "okay"; +- }; +- +- u2phy1_host: host-port { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +- status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&rk808 1>; +- clock-names = "lpo"; +- device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; +- vbat-supply = <&vcc3v3_sys>; +- vddio-supply = <&vcc_1v8>; +- }; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&usbdrd3_0 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_0 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&usbdrd3_1 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_1 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-sapphire-excavator.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-sapphire-excavator.dts +deleted file mode 100644 +index f6b2199a42bd..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-sapphire-excavator.dts ++++ /dev/null +@@ -1,238 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. +- */ +- +-/dts-v1/; +-#include "rk3399-sapphire.dtsi" +- +-/ { +- model = "Excavator-RK3399 Board"; +- compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399"; +- +- aliases { +- mmc2 = &sdio0; +- }; +- +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 1>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1800000>; +- poll-interval = <100>; +- +- button-up { +- label = "Volume Up"; +- linux,code = ; +- press-threshold-microvolt = <100000>; +- }; +- +- button-down { +- label = "Volume Down"; +- linux,code = ; +- press-threshold-microvolt = <300000>; +- }; +- +- back { +- label = "Back"; +- linux,code = ; +- press-threshold-microvolt = <985000>; +- }; +- +- menu { +- label = "Menu"; +- linux,code = ; +- press-threshold-microvolt = <1314000>; +- }; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- brightness-levels = < +- 0 1 2 3 4 5 6 7 +- 8 9 10 11 12 13 14 15 +- 16 17 18 19 20 21 22 23 +- 24 25 26 27 28 29 30 31 +- 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 +- 48 49 50 51 52 53 54 55 +- 56 57 58 59 60 61 62 63 +- 64 65 66 67 68 69 70 71 +- 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 +- 88 89 90 91 92 93 94 95 +- 96 97 98 99 100 101 102 103 +- 104 105 106 107 108 109 110 111 +- 112 113 114 115 116 117 118 119 +- 120 121 122 123 124 125 126 127 +- 128 129 130 131 132 133 134 135 +- 136 137 138 139 140 141 142 143 +- 144 145 146 147 148 149 150 151 +- 152 153 154 155 156 157 158 159 +- 160 161 162 163 164 165 166 167 +- 168 169 170 171 172 173 174 175 +- 176 177 178 179 180 181 182 183 +- 184 185 186 187 188 189 190 191 +- 192 193 194 195 196 197 198 199 +- 200 201 202 203 204 205 206 207 +- 208 209 210 211 212 213 214 215 +- 216 217 218 219 220 221 222 223 +- 224 225 226 227 228 229 230 231 +- 232 233 234 235 236 237 238 239 +- 240 241 242 243 244 245 246 247 +- 248 249 250 251 252 253 254 255>; +- default-brightness-level = <200>; +- enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; +- pwms = <&pwm0 0 25000 0>; +- status = "okay"; +- }; +- +- edp_panel: edp-panel { +- compatible ="lg,lp079qx1-sp0v"; +- backlight = <&backlight>; +- enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&lcd_panel_reset>; +- power-supply = <&vcc3v3_s0>; +- +- port { +- panel_in_edp: endpoint { +- remote-endpoint = <&edp_out_panel>; +- }; +- }; +- }; +- +- rt5651-sound { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "realtek,rt5651-codec"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,mclk-fs = <256>; +- simple-audio-card,widgets = +- "Microphone", "Mic Jack", +- "Headphone", "Headphone Jack"; +- simple-audio-card,routing = +- "Mic Jack", "MICBIAS1", +- "IN1P", "Mic Jack", +- "Headphone Jack", "HPOL", +- "Headphone Jack", "HPOR"; +- simple-audio-card,cpu { +- sound-dai = <&i2s0>; +- }; +- simple-audio-card,codec { +- sound-dai = <&rt5651>; +- }; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- clocks = <&rk808 1>; +- clock-names = "ext_clock"; +- pinctrl-names = "default"; +- pinctrl-0 = <&wifi_enable_h>; +- +- /* +- * On the module itself this is one of these (depending +- * on the actual card populated): +- * - SDIO_RESET_L_WL_REG_ON +- * - PDN (power down when low) +- */ +- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&edp { +- status = "okay"; +- +- ports { +- edp_out: port@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- edp_out_panel: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_in_edp>; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- i2c-scl-rising-time-ns = <300>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +- +- rt5651: rt5651@1a { +- compatible = "rockchip,rt5651"; +- reg = <0x1a>; +- clocks = <&cru SCLK_I2S_8CH_OUT>; +- clock-names = "mclk"; +- hp-det-gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; +- spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; +- #sound-dai-cells = <0>; +- }; +-}; +- +-&i2c4 { +- i2c-scl-rising-time-ns = <600>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- +- accelerometer@68 { +- compatible = "invensense,mpu6500"; +- reg = <0x68>; +- interrupt-parent = <&gpio1>; +- interrupts = ; +- }; +-}; +- +-&i2s0 { +- rockchip,playback-channels = <8>; +- rockchip,capture-channels = <8>; +- status = "okay"; +-}; +- +-&pcie_phy { +- status = "okay"; +-}; +- +-&pcie0 { +- ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; +- num-lanes = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_clkreqn_cpm>; +- status = "okay"; +-}; +- +-&pinctrl { +- sdio-pwrseq { +- wifi_enable_h: wifi-enable-h { +- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- lcd-panel { +- lcd_panel_reset: lcd-panel-reset { +- rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +- +-&sdio0 { +- bus-width = <4>; +- cap-sd-highspeed; +- cap-sdio-irq; +- clock-frequency = <50000000>; +- keep-power-in-suspend; +- max-frequency = <50000000>; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; +- sd-uhs-sdr104; +- status = "okay"; +-}; +- +-&spdif { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-sapphire.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-sapphire.dts +deleted file mode 100644 +index 5a58060447cf..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-sapphire.dts ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. +- */ +- +-/dts-v1/; +-#include "rk3399-sapphire.dtsi" +- +-/ { +- model = "Sapphire-RK3399 Board"; +- compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-sapphire.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-sapphire.dtsi +deleted file mode 100644 +index 46b0f97a0b1c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-sapphire.dtsi ++++ /dev/null +@@ -1,653 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. +- */ +- +-#include "dt-bindings/pwm/pwm.h" +-#include "dt-bindings/input/input.h" +-#include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" +- +-/ { +- compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399"; +- +- aliases { +- mmc0 = &sdmmc; +- mmc1 = &sdhci; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- clkin_gmac: external-gmac-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "clkin_gmac"; +- #clock-cells = <0>; +- }; +- +- dc_12v: dc-12v { +- compatible = "regulator-fixed"; +- regulator-name = "dc_12v"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- /* +- * The fan power supply comes from the baseboard. +- * For the standalone Sapphire one option is to connect a wire +- * from R90030 DNP R0805 pin2 to C90002 10uF C0805 pin1 (vcc_sys). +- */ +- fan0: gpio-fan { +- #cooling-cells = <2>; +- compatible = "gpio-fan"; +- gpio-fan,speed-map = <0 0 3000 1>; +- gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- }; +- +- keys: gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- +- power { +- debounce-interval = <100>; +- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; +- label = "GPIO Power"; +- linux,code = ; +- linux,input-type = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwr_btn>; +- wakeup-source; +- }; +- }; +- +- /* switched by pmic_sleep */ +- vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc1v8_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_1v8>; +- }; +- +- vcc3v0_sd: vcc3v0-sd { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc0_pwr_h>; +- regulator-always-on; +- regulator-max-microvolt = <3000000>; +- regulator-min-microvolt = <3000000>; +- regulator-name = "vcc3v0_sd"; +- vin-supply = <&vcc3v3_sys>; +- }; +- +- vcc3v3_sys: vcc3v3-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc5v0_host: vcc5v0-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_host_en>; +- regulator-name = "vcc5v0_host"; +- regulator-always-on; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc5v0_typec0: vcc5v0-typec0-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_typec0_en>; +- regulator-name = "vcc5v0_typec0"; +- vin-supply = <&vcc_sys>; +- }; +- +- vcc_sys: vcc-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&dc_12v>; +- }; +- +- vdd_log: vdd-log { +- compatible = "pwm-regulator"; +- pwms = <&pwm2 0 25000 1>; +- regulator-name = "vdd_log"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- vin-supply = <&vcc_sys>; +- }; +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_thermal { +- trips { +- cpu_hot: cpu_hot { +- hysteresis = <10000>; +- temperature = <55000>; +- type = "active"; +- }; +- }; +- +- cooling-maps { +- map2 { +- cooling-device = +- <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- trip = <&cpu_hot>; +- }; +- }; +-}; +- +-&emmc_phy { +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_RMII_SRC>; +- assigned-clock-parents = <&clkin_gmac>; +- clock_in_out = "input"; +- phy-supply = <&vcc_lan>; +- phy-mode = "rgmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 50000>; +- tx_delay = <0x28>; +- rx_delay = <0x11>; +- status = "okay"; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- status = "okay"; +-}; +- +-&hdmi_sound { +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- i2c-scl-rising-time-ns = <168>; +- i2c-scl-falling-time-ns = <4>; +- status = "okay"; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio1>; +- interrupts = <21 IRQ_TYPE_LEVEL_LOW>; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc6-supply = <&vcc_sys>; +- vcc7-supply = <&vcc_sys>; +- vcc8-supply = <&vcc3v3_sys>; +- vcc9-supply = <&vcc_sys>; +- vcc10-supply = <&vcc_sys>; +- vcc11-supply = <&vcc_sys>; +- vcc12-supply = <&vcc3v3_sys>; +- vddio-supply = <&vcc1v8_pmu>; +- +- regulators { +- vdd_center: DCDC_REG1 { +- regulator-name = "vdd_center"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_l: DCDC_REG2 { +- regulator-name = "vdd_cpu_l"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_1v8: DCDC_REG4 { +- regulator-name = "vcc_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc1v8_dvp: LDO_REG1 { +- regulator-name = "vcc1v8_dvp"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v0_tp: LDO_REG2 { +- regulator-name = "vcc3v0_tp"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc1v8_pmu: LDO_REG3 { +- regulator-name = "vcc1v8_pmu"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc_sdio: LDO_REG4 { +- regulator-name = "vcc_sdio"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcca3v0_codec: LDO_REG5 { +- regulator-name = "vcca3v0_codec"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v5: LDO_REG6 { +- regulator-name = "vcc_1v5"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1500000>; +- }; +- }; +- +- vcca1v8_codec: LDO_REG7 { +- regulator-name = "vcca1v8_codec"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_3v0: LDO_REG8 { +- regulator-name = "vcc_3v0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc3v3_s3: vcc_lan: SWITCH_REG1 { +- regulator-name = "vcc3v3_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v3_s0: SWITCH_REG2 { +- regulator-name = "vcc3v3_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +- +- vdd_cpu_b: regulator@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_cpu_b"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: regulator@41 { +- compatible = "silergy,syr828"; +- reg = <0x41>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_gpu"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +-}; +- +-&i2c3 { +- i2c-scl-rising-time-ns = <450>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +-}; +- +-&i2s2 { +- status = "okay"; +-}; +- +-&io_domains { +- status = "okay"; +- +- bt656-supply = <&vcc_3v0>; +- audio-supply = <&vcca1v8_codec>; +- sdmmc-supply = <&vcc_sdio>; +- gpio1830-supply = <&vcc_3v0>; +-}; +- +-&pmu_io_domains { +- pmu1830-supply = <&vcc_3v0>; +- status = "okay"; +-}; +- +-&pinctrl { +- buttons { +- pwr_btn: pwr-btn { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- fan { +- motor_pwr: motor-pwr { +- rockchip,pins = +- <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = +- <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- vsel1_pin: vsel1-pin { +- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- vsel2_pin: vsel2-pin { +- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- +- sd { +- sdmmc0_pwr_h: sdmmc0-pwr-h { +- rockchip,pins = +- <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb2 { +- vcc5v0_host_en: vcc5v0-host-en { +- rockchip,pins = +- <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- vcc5v0_typec0_en: vcc5v0-typec0-en { +- rockchip,pins = +- <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm0 { +- status = "okay"; +-}; +- +-&pwm2 { +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vcca1v8_s3>; +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- non-removable; +- status = "okay"; +-}; +- +-&sdmmc { +- broken-cd; +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- clock-frequency = <150000000>; +- disable-wp; +- max-frequency = <150000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +- vmmc-supply = <&vcc3v0_sd>; +- vqmmc-supply = <&vcc_sdio>; +- status = "okay"; +-}; +- +-&tcphy0 { +- status = "okay"; +-}; +- +-&tcphy1 { +- status = "okay"; +-}; +- +-&tsadc { +- /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-mode = <1>; +- /* tshut polarity 0:LOW 1:HIGH */ +- rockchip,hw-tshut-polarity = <1>; +- status = "okay"; +-}; +- +-&u2phy0 { +- status = "okay"; +- +- u2phy0_otg: otg-port { +- status = "okay"; +- }; +- +- u2phy0_host: host-port { +- phy-supply = <&vcc5v0_typec0>; +- status = "okay"; +- }; +-}; +- +-&u2phy1 { +- status = "okay"; +- +- u2phy1_otg: otg-port { +- status = "okay"; +- }; +- +- u2phy1_host: host-port { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts>; +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&usbdrd3_0 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_0 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&usbdrd3_1 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_1 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399.dtsi +deleted file mode 100644 +index 00f1d036dfe0..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399.dtsi ++++ /dev/null +@@ -1,2714 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "rockchip,rk3399"; +- +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- ethernet0 = &gmac; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c7; +- i2c8 = &i2c8; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu_l0>; +- }; +- core1 { +- cpu = <&cpu_l1>; +- }; +- core2 { +- cpu = <&cpu_l2>; +- }; +- core3 { +- cpu = <&cpu_l3>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&cpu_b0>; +- }; +- core1 { +- cpu = <&cpu_b1>; +- }; +- }; +- }; +- +- cpu_l0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- capacity-dmips-mhz = <485>; +- clocks = <&cru ARMCLKL>; +- #cooling-cells = <2>; /* min followed by max */ +- dynamic-power-coefficient = <100>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; +- }; +- +- cpu_l1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- capacity-dmips-mhz = <485>; +- clocks = <&cru ARMCLKL>; +- #cooling-cells = <2>; /* min followed by max */ +- dynamic-power-coefficient = <100>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; +- }; +- +- cpu_l2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- capacity-dmips-mhz = <485>; +- clocks = <&cru ARMCLKL>; +- #cooling-cells = <2>; /* min followed by max */ +- dynamic-power-coefficient = <100>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; +- }; +- +- cpu_l3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- capacity-dmips-mhz = <485>; +- clocks = <&cru ARMCLKL>; +- #cooling-cells = <2>; /* min followed by max */ +- dynamic-power-coefficient = <100>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; +- }; +- +- cpu_b0: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- clocks = <&cru ARMCLKB>; +- #cooling-cells = <2>; /* min followed by max */ +- dynamic-power-coefficient = <436>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; +- }; +- +- cpu_b1: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0x0 0x101>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- clocks = <&cru ARMCLKB>; +- #cooling-cells = <2>; /* min followed by max */ +- dynamic-power-coefficient = <436>; +- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP: cpu-sleep { +- compatible = "arm,idle-state"; +- local-timer-stop; +- arm,psci-suspend-param = <0x0010000>; +- entry-latency-us = <120>; +- exit-latency-us = <250>; +- min-residency-us = <900>; +- }; +- +- CLUSTER_SLEEP: cluster-sleep { +- compatible = "arm,idle-state"; +- local-timer-stop; +- arm,psci-suspend-param = <0x1010000>; +- entry-latency-us = <400>; +- exit-latency-us = <500>; +- min-residency-us = <2000>; +- }; +- }; +- }; +- +- display-subsystem { +- compatible = "rockchip,display-subsystem"; +- ports = <&vopl_out>, <&vopb_out>; +- }; +- +- pmu_a53 { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = ; +- }; +- +- pmu_a72 { +- compatible = "arm,cortex-a72-pmu"; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- arm,no-tick-in-suspend; +- }; +- +- xin24m: xin24m { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "xin24m"; +- #clock-cells = <0>; +- }; +- +- pcie0: pcie@f8000000 { +- compatible = "rockchip,rk3399-pcie"; +- reg = <0x0 0xf8000000 0x0 0x2000000>, +- <0x0 0xfd000000 0x0 0x1000000>; +- reg-names = "axi-base", "apb-base"; +- device_type = "pci"; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- aspm-no-l0s; +- bus-range = <0x0 0x1f>; +- clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, +- <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; +- clock-names = "aclk", "aclk-perf", +- "hclk", "pm"; +- interrupts = , +- , +- ; +- interrupt-names = "sys", "legacy", "client"; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie0_intc 0>, +- <0 0 0 2 &pcie0_intc 1>, +- <0 0 0 3 &pcie0_intc 2>, +- <0 0 0 4 &pcie0_intc 3>; +- max-link-speed = <1>; +- msi-map = <0x0 &its 0x0 0x1000>; +- phys = <&pcie_phy 0>, <&pcie_phy 1>, +- <&pcie_phy 2>, <&pcie_phy 3>; +- phy-names = "pcie-phy-0", "pcie-phy-1", +- "pcie-phy-2", "pcie-phy-3"; +- ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>, +- <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; +- resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, +- <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, +- <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, +- <&cru SRST_A_PCIE>; +- reset-names = "core", "mgmt", "mgmt-sticky", "pipe", +- "pm", "pclk", "aclk"; +- status = "disabled"; +- +- pcie0_intc: interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- }; +- }; +- +- gmac: ethernet@fe300000 { +- compatible = "rockchip,rk3399-gmac"; +- reg = <0x0 0xfe300000 0x0 0x10000>; +- interrupts = ; +- interrupt-names = "macirq"; +- clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, +- <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, +- <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, +- <&cru PCLK_GMAC>; +- clock-names = "stmmaceth", "mac_clk_rx", +- "mac_clk_tx", "clk_mac_ref", +- "clk_mac_refout", "aclk_mac", +- "pclk_mac"; +- power-domains = <&power RK3399_PD_GMAC>; +- resets = <&cru SRST_A_GMAC>; +- reset-names = "stmmaceth"; +- rockchip,grf = <&grf>; +- snps,txpbl = <0x4>; +- status = "disabled"; +- }; +- +- sdio0: mmc@fe310000 { +- compatible = "rockchip,rk3399-dw-mshc", +- "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xfe310000 0x0 0x4000>; +- interrupts = ; +- max-frequency = <150000000>; +- clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, +- <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- power-domains = <&power RK3399_PD_SDIOAUDIO>; +- resets = <&cru SRST_SDIO0>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- sdmmc: mmc@fe320000 { +- compatible = "rockchip,rk3399-dw-mshc", +- "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xfe320000 0x0 0x4000>; +- interrupts = ; +- max-frequency = <150000000>; +- assigned-clocks = <&cru HCLK_SD>; +- assigned-clock-rates = <200000000>; +- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, +- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- power-domains = <&power RK3399_PD_SD>; +- resets = <&cru SRST_SDMMC>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- sdhci: mmc@fe330000 { +- compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; +- reg = <0x0 0xfe330000 0x0 0x10000>; +- interrupts = ; +- arasan,soc-ctl-syscon = <&grf>; +- assigned-clocks = <&cru SCLK_EMMC>; +- assigned-clock-rates = <200000000>; +- clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; +- clock-names = "clk_xin", "clk_ahb"; +- clock-output-names = "emmc_cardclock"; +- #clock-cells = <0>; +- phys = <&emmc_phy>; +- phy-names = "phy_arasan"; +- power-domains = <&power RK3399_PD_EMMC>; +- disable-cqe-dcmd; +- status = "disabled"; +- }; +- +- usb_host0_ehci: usb@fe380000 { +- compatible = "generic-ehci"; +- reg = <0x0 0xfe380000 0x0 0x20000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, +- <&u2phy0>; +- phys = <&u2phy0_host>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usb_host0_ohci: usb@fe3a0000 { +- compatible = "generic-ohci"; +- reg = <0x0 0xfe3a0000 0x0 0x20000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, +- <&u2phy0>; +- phys = <&u2phy0_host>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usb_host1_ehci: usb@fe3c0000 { +- compatible = "generic-ehci"; +- reg = <0x0 0xfe3c0000 0x0 0x20000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, +- <&u2phy1>; +- phys = <&u2phy1_host>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usb_host1_ohci: usb@fe3e0000 { +- compatible = "generic-ohci"; +- reg = <0x0 0xfe3e0000 0x0 0x20000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, +- <&u2phy1>; +- phys = <&u2phy1_host>; +- phy-names = "usb"; +- status = "disabled"; +- }; +- +- usbdrd3_0: usb@fe800000 { +- compatible = "rockchip,rk3399-dwc3"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, +- <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, +- <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; +- clock-names = "ref_clk", "suspend_clk", +- "bus_clk", "aclk_usb3_rksoc_axi_perf", +- "aclk_usb3", "grf_clk"; +- resets = <&cru SRST_A_USB3_OTG0>; +- reset-names = "usb3-otg"; +- status = "disabled"; +- +- usbdrd_dwc3_0: usb@fe800000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0xfe800000 0x0 0x100000>; +- interrupts = ; +- clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, +- <&cru SCLK_USB3OTG0_SUSPEND>; +- clock-names = "ref", "bus_early", "suspend"; +- dr_mode = "otg"; +- phys = <&u2phy0_otg>, <&tcphy0_usb3>; +- phy-names = "usb2-phy", "usb3-phy"; +- phy_type = "utmi_wide"; +- snps,dis_enblslpm_quirk; +- snps,dis-u2-freeclk-exists-quirk; +- snps,dis_u2_susphy_quirk; +- snps,dis-del-phy-power-chg-quirk; +- snps,dis-tx-ipgap-linecheck-quirk; +- power-domains = <&power RK3399_PD_USB3>; +- status = "disabled"; +- }; +- }; +- +- usbdrd3_1: usb@fe900000 { +- compatible = "rockchip,rk3399-dwc3"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, +- <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, +- <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; +- clock-names = "ref_clk", "suspend_clk", +- "bus_clk", "aclk_usb3_rksoc_axi_perf", +- "aclk_usb3", "grf_clk"; +- resets = <&cru SRST_A_USB3_OTG1>; +- reset-names = "usb3-otg"; +- status = "disabled"; +- +- usbdrd_dwc3_1: usb@fe900000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0xfe900000 0x0 0x100000>; +- interrupts = ; +- clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, +- <&cru SCLK_USB3OTG1_SUSPEND>; +- clock-names = "ref", "bus_early", "suspend"; +- dr_mode = "otg"; +- phys = <&u2phy1_otg>, <&tcphy1_usb3>; +- phy-names = "usb2-phy", "usb3-phy"; +- phy_type = "utmi_wide"; +- snps,dis_enblslpm_quirk; +- snps,dis-u2-freeclk-exists-quirk; +- snps,dis_u2_susphy_quirk; +- snps,dis-del-phy-power-chg-quirk; +- snps,dis-tx-ipgap-linecheck-quirk; +- power-domains = <&power RK3399_PD_USB3>; +- status = "disabled"; +- }; +- }; +- +- cdn_dp: dp@fec00000 { +- compatible = "rockchip,rk3399-cdn-dp"; +- reg = <0x0 0xfec00000 0x0 0x100000>; +- interrupts = ; +- assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; +- assigned-clock-rates = <100000000>, <200000000>; +- clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, +- <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; +- clock-names = "core-clk", "pclk", "spdif", "grf"; +- phys = <&tcphy0_dp>, <&tcphy1_dp>; +- power-domains = <&power RK3399_PD_HDCP>; +- resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, +- <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; +- reset-names = "spdif", "dptx", "apb", "core"; +- rockchip,grf = <&grf>; +- #sound-dai-cells = <1>; +- status = "disabled"; +- +- ports { +- dp_in: port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- dp_in_vopb: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vopb_out_dp>; +- }; +- +- dp_in_vopl: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vopl_out_dp>; +- }; +- }; +- }; +- }; +- +- gic: interrupt-controller@fee00000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <4>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- interrupt-controller; +- +- reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ +- <0x0 0xfef00000 0 0xc0000>, /* GICR */ +- <0x0 0xfff00000 0 0x10000>, /* GICC */ +- <0x0 0xfff10000 0 0x10000>, /* GICH */ +- <0x0 0xfff20000 0 0x10000>; /* GICV */ +- interrupts = ; +- its: interrupt-controller@fee20000 { +- compatible = "arm,gic-v3-its"; +- msi-controller; +- #msi-cells = <1>; +- reg = <0x0 0xfee20000 0x0 0x20000>; +- }; +- +- ppi-partitions { +- ppi_cluster0: interrupt-partition-0 { +- affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; +- }; +- +- ppi_cluster1: interrupt-partition-1 { +- affinity = <&cpu_b0 &cpu_b1>; +- }; +- }; +- }; +- +- saradc: saradc@ff100000 { +- compatible = "rockchip,rk3399-saradc"; +- reg = <0x0 0xff100000 0x0 0x100>; +- interrupts = ; +- #io-channel-cells = <1>; +- clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; +- clock-names = "saradc", "apb_pclk"; +- resets = <&cru SRST_P_SARADC>; +- reset-names = "saradc-apb"; +- status = "disabled"; +- }; +- +- i2c1: i2c@ff110000 { +- compatible = "rockchip,rk3399-i2c"; +- reg = <0x0 0xff110000 0x0 0x1000>; +- assigned-clocks = <&cru SCLK_I2C1>; +- assigned-clock-rates = <200000000>; +- clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_xfer>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@ff120000 { +- compatible = "rockchip,rk3399-i2c"; +- reg = <0x0 0xff120000 0x0 0x1000>; +- assigned-clocks = <&cru SCLK_I2C2>; +- assigned-clock-rates = <200000000>; +- clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_xfer>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@ff130000 { +- compatible = "rockchip,rk3399-i2c"; +- reg = <0x0 0xff130000 0x0 0x1000>; +- assigned-clocks = <&cru SCLK_I2C3>; +- assigned-clock-rates = <200000000>; +- clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_xfer>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c5: i2c@ff140000 { +- compatible = "rockchip,rk3399-i2c"; +- reg = <0x0 0xff140000 0x0 0x1000>; +- assigned-clocks = <&cru SCLK_I2C5>; +- assigned-clock-rates = <200000000>; +- clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_xfer>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c6: i2c@ff150000 { +- compatible = "rockchip,rk3399-i2c"; +- reg = <0x0 0xff150000 0x0 0x1000>; +- assigned-clocks = <&cru SCLK_I2C6>; +- assigned-clock-rates = <200000000>; +- clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c6_xfer>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c7: i2c@ff160000 { +- compatible = "rockchip,rk3399-i2c"; +- reg = <0x0 0xff160000 0x0 0x1000>; +- assigned-clocks = <&cru SCLK_I2C7>; +- assigned-clock-rates = <200000000>; +- clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c7_xfer>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- uart0: serial@ff180000 { +- compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff180000 0x0 0x100>; +- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; +- clock-names = "baudclk", "apb_pclk"; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer>; +- status = "disabled"; +- }; +- +- uart1: serial@ff190000 { +- compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff190000 0x0 0x100>; +- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; +- clock-names = "baudclk", "apb_pclk"; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_xfer>; +- status = "disabled"; +- }; +- +- uart2: serial@ff1a0000 { +- compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff1a0000 0x0 0x100>; +- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; +- clock-names = "baudclk", "apb_pclk"; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2c_xfer>; +- status = "disabled"; +- }; +- +- uart3: serial@ff1b0000 { +- compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff1b0000 0x0 0x100>; +- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; +- clock-names = "baudclk", "apb_pclk"; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_xfer>; +- status = "disabled"; +- }; +- +- spi0: spi@ff1c0000 { +- compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xff1c0000 0x0 0x1000>; +- clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; +- clock-names = "spiclk", "apb_pclk"; +- interrupts = ; +- dmas = <&dmac_peri 10>, <&dmac_peri 11>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi1: spi@ff1d0000 { +- compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xff1d0000 0x0 0x1000>; +- clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; +- clock-names = "spiclk", "apb_pclk"; +- interrupts = ; +- dmas = <&dmac_peri 12>, <&dmac_peri 13>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi2: spi@ff1e0000 { +- compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xff1e0000 0x0 0x1000>; +- clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; +- clock-names = "spiclk", "apb_pclk"; +- interrupts = ; +- dmas = <&dmac_peri 14>, <&dmac_peri 15>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi4: spi@ff1f0000 { +- compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xff1f0000 0x0 0x1000>; +- clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; +- clock-names = "spiclk", "apb_pclk"; +- interrupts = ; +- dmas = <&dmac_peri 18>, <&dmac_peri 19>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi5: spi@ff200000 { +- compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xff200000 0x0 0x1000>; +- clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; +- clock-names = "spiclk", "apb_pclk"; +- interrupts = ; +- dmas = <&dmac_bus 8>, <&dmac_bus 9>; +- dma-names = "tx", "rx"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; +- power-domains = <&power RK3399_PD_SDIOAUDIO>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- thermal_zones: thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <100>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsadc 0>; +- +- trips { +- cpu_alert0: cpu_alert0 { +- temperature = <70000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu_alert1: cpu_alert1 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu_crit: cpu_crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert0>; +- cooling-device = +- <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu_alert1>; +- cooling-device = +- <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- +- gpu_thermal: gpu-thermal { +- polling-delay-passive = <100>; +- polling-delay = <1000>; +- +- thermal-sensors = <&tsadc 1>; +- +- trips { +- gpu_alert0: gpu_alert0 { +- temperature = <75000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- gpu_crit: gpu_crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&gpu_alert0>; +- cooling-device = +- <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- tsadc: tsadc@ff260000 { +- compatible = "rockchip,rk3399-tsadc"; +- reg = <0x0 0xff260000 0x0 0x100>; +- interrupts = ; +- assigned-clocks = <&cru SCLK_TSADC>; +- assigned-clock-rates = <750000>; +- clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; +- clock-names = "tsadc", "apb_pclk"; +- resets = <&cru SRST_TSADC>; +- reset-names = "tsadc-apb"; +- rockchip,grf = <&grf>; +- rockchip,hw-tshut-temp = <95000>; +- pinctrl-names = "init", "default", "sleep"; +- pinctrl-0 = <&otp_pin>; +- pinctrl-1 = <&otp_out>; +- pinctrl-2 = <&otp_pin>; +- #thermal-sensor-cells = <1>; +- status = "disabled"; +- }; +- +- qos_emmc: qos@ffa58000 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffa58000 0x0 0x20>; +- }; +- +- qos_gmac: qos@ffa5c000 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffa5c000 0x0 0x20>; +- }; +- +- qos_pcie: qos@ffa60080 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffa60080 0x0 0x20>; +- }; +- +- qos_usb_host0: qos@ffa60100 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffa60100 0x0 0x20>; +- }; +- +- qos_usb_host1: qos@ffa60180 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffa60180 0x0 0x20>; +- }; +- +- qos_usb_otg0: qos@ffa70000 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffa70000 0x0 0x20>; +- }; +- +- qos_usb_otg1: qos@ffa70080 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffa70080 0x0 0x20>; +- }; +- +- qos_sd: qos@ffa74000 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffa74000 0x0 0x20>; +- }; +- +- qos_sdioaudio: qos@ffa76000 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffa76000 0x0 0x20>; +- }; +- +- qos_hdcp: qos@ffa90000 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffa90000 0x0 0x20>; +- }; +- +- qos_iep: qos@ffa98000 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffa98000 0x0 0x20>; +- }; +- +- qos_isp0_m0: qos@ffaa0000 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffaa0000 0x0 0x20>; +- }; +- +- qos_isp0_m1: qos@ffaa0080 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffaa0080 0x0 0x20>; +- }; +- +- qos_isp1_m0: qos@ffaa8000 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffaa8000 0x0 0x20>; +- }; +- +- qos_isp1_m1: qos@ffaa8080 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffaa8080 0x0 0x20>; +- }; +- +- qos_rga_r: qos@ffab0000 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffab0000 0x0 0x20>; +- }; +- +- qos_rga_w: qos@ffab0080 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffab0080 0x0 0x20>; +- }; +- +- qos_video_m0: qos@ffab8000 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffab8000 0x0 0x20>; +- }; +- +- qos_video_m1_r: qos@ffac0000 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffac0000 0x0 0x20>; +- }; +- +- qos_video_m1_w: qos@ffac0080 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffac0080 0x0 0x20>; +- }; +- +- qos_vop_big_r: qos@ffac8000 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffac8000 0x0 0x20>; +- }; +- +- qos_vop_big_w: qos@ffac8080 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffac8080 0x0 0x20>; +- }; +- +- qos_vop_little: qos@ffad0000 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffad0000 0x0 0x20>; +- }; +- +- qos_perihp: qos@ffad8080 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffad8080 0x0 0x20>; +- }; +- +- qos_gpu: qos@ffae0000 { +- compatible = "rockchip,rk3399-qos", "syscon"; +- reg = <0x0 0xffae0000 0x0 0x20>; +- }; +- +- pmu: power-management@ff310000 { +- compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; +- reg = <0x0 0xff310000 0x0 0x1000>; +- +- /* +- * Note: RK3399 supports 6 voltage domains including VD_CORE_L, +- * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. +- * Some of the power domains are grouped together for every +- * voltage domain. +- * The detail contents as below. +- */ +- power: power-controller { +- compatible = "rockchip,rk3399-power-controller"; +- #power-domain-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* These power domains are grouped by VD_CENTER */ +- power-domain@RK3399_PD_IEP { +- reg = ; +- clocks = <&cru ACLK_IEP>, +- <&cru HCLK_IEP>; +- pm_qos = <&qos_iep>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3399_PD_RGA { +- reg = ; +- clocks = <&cru ACLK_RGA>, +- <&cru HCLK_RGA>; +- pm_qos = <&qos_rga_r>, +- <&qos_rga_w>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3399_PD_VCODEC { +- reg = ; +- clocks = <&cru ACLK_VCODEC>, +- <&cru HCLK_VCODEC>; +- pm_qos = <&qos_video_m0>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3399_PD_VDU { +- reg = ; +- clocks = <&cru ACLK_VDU>, +- <&cru HCLK_VDU>; +- pm_qos = <&qos_video_m1_r>, +- <&qos_video_m1_w>; +- #power-domain-cells = <0>; +- }; +- +- /* These power domains are grouped by VD_GPU */ +- power-domain@RK3399_PD_GPU { +- reg = ; +- clocks = <&cru ACLK_GPU>; +- pm_qos = <&qos_gpu>; +- #power-domain-cells = <0>; +- }; +- +- /* These power domains are grouped by VD_LOGIC */ +- power-domain@RK3399_PD_EDP { +- reg = ; +- clocks = <&cru PCLK_EDP_CTRL>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3399_PD_EMMC { +- reg = ; +- clocks = <&cru ACLK_EMMC>; +- pm_qos = <&qos_emmc>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3399_PD_GMAC { +- reg = ; +- clocks = <&cru ACLK_GMAC>, +- <&cru PCLK_GMAC>; +- pm_qos = <&qos_gmac>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3399_PD_SD { +- reg = ; +- clocks = <&cru HCLK_SDMMC>, +- <&cru SCLK_SDMMC>; +- pm_qos = <&qos_sd>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3399_PD_SDIOAUDIO { +- reg = ; +- clocks = <&cru HCLK_SDIO>; +- pm_qos = <&qos_sdioaudio>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3399_PD_TCPD0 { +- reg = ; +- clocks = <&cru SCLK_UPHY0_TCPDCORE>, +- <&cru SCLK_UPHY0_TCPDPHY_REF>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3399_PD_TCPD1 { +- reg = ; +- clocks = <&cru SCLK_UPHY1_TCPDCORE>, +- <&cru SCLK_UPHY1_TCPDPHY_REF>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3399_PD_USB3 { +- reg = ; +- clocks = <&cru ACLK_USB3>; +- pm_qos = <&qos_usb_otg0>, +- <&qos_usb_otg1>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3399_PD_VIO { +- reg = ; +- #power-domain-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- power-domain@RK3399_PD_HDCP { +- reg = ; +- clocks = <&cru ACLK_HDCP>, +- <&cru HCLK_HDCP>, +- <&cru PCLK_HDCP>; +- pm_qos = <&qos_hdcp>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3399_PD_ISP0 { +- reg = ; +- clocks = <&cru ACLK_ISP0>, +- <&cru HCLK_ISP0>; +- pm_qos = <&qos_isp0_m0>, +- <&qos_isp0_m1>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3399_PD_ISP1 { +- reg = ; +- clocks = <&cru ACLK_ISP1>, +- <&cru HCLK_ISP1>; +- pm_qos = <&qos_isp1_m0>, +- <&qos_isp1_m1>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3399_PD_VO { +- reg = ; +- #power-domain-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- power-domain@RK3399_PD_VOPB { +- reg = ; +- clocks = <&cru ACLK_VOP0>, +- <&cru HCLK_VOP0>; +- pm_qos = <&qos_vop_big_r>, +- <&qos_vop_big_w>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3399_PD_VOPL { +- reg = ; +- clocks = <&cru ACLK_VOP1>, +- <&cru HCLK_VOP1>; +- pm_qos = <&qos_vop_little>; +- #power-domain-cells = <0>; +- }; +- }; +- }; +- }; +- }; +- +- pmugrf: syscon@ff320000 { +- compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; +- reg = <0x0 0xff320000 0x0 0x1000>; +- +- pmu_io_domains: io-domains { +- compatible = "rockchip,rk3399-pmu-io-voltage-domain"; +- status = "disabled"; +- }; +- }; +- +- spi3: spi@ff350000 { +- compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xff350000 0x0 0x1000>; +- clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; +- clock-names = "spiclk", "apb_pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- uart4: serial@ff370000 { +- compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff370000 0x0 0x100>; +- clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; +- clock-names = "baudclk", "apb_pclk"; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_xfer>; +- status = "disabled"; +- }; +- +- i2c0: i2c@ff3c0000 { +- compatible = "rockchip,rk3399-i2c"; +- reg = <0x0 0xff3c0000 0x0 0x1000>; +- assigned-clocks = <&pmucru SCLK_I2C0_PMU>; +- assigned-clock-rates = <200000000>; +- clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_xfer>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@ff3d0000 { +- compatible = "rockchip,rk3399-i2c"; +- reg = <0x0 0xff3d0000 0x0 0x1000>; +- assigned-clocks = <&pmucru SCLK_I2C4_PMU>; +- assigned-clock-rates = <200000000>; +- clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_xfer>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c8: i2c@ff3e0000 { +- compatible = "rockchip,rk3399-i2c"; +- reg = <0x0 0xff3e0000 0x0 0x1000>; +- assigned-clocks = <&pmucru SCLK_I2C8_PMU>; +- assigned-clock-rates = <200000000>; +- clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c8_xfer>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pwm0: pwm@ff420000 { +- compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; +- reg = <0x0 0xff420000 0x0 0x10>; +- #pwm-cells = <3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm0_pin>; +- clocks = <&pmucru PCLK_RKPWM_PMU>; +- status = "disabled"; +- }; +- +- pwm1: pwm@ff420010 { +- compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; +- reg = <0x0 0xff420010 0x0 0x10>; +- #pwm-cells = <3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm1_pin>; +- clocks = <&pmucru PCLK_RKPWM_PMU>; +- status = "disabled"; +- }; +- +- pwm2: pwm@ff420020 { +- compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; +- reg = <0x0 0xff420020 0x0 0x10>; +- #pwm-cells = <3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm2_pin>; +- clocks = <&pmucru PCLK_RKPWM_PMU>; +- status = "disabled"; +- }; +- +- pwm3: pwm@ff420030 { +- compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; +- reg = <0x0 0xff420030 0x0 0x10>; +- #pwm-cells = <3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm3a_pin>; +- clocks = <&pmucru PCLK_RKPWM_PMU>; +- status = "disabled"; +- }; +- +- vpu: video-codec@ff650000 { +- compatible = "rockchip,rk3399-vpu"; +- reg = <0x0 0xff650000 0x0 0x800>; +- interrupts = , +- ; +- interrupt-names = "vepu", "vdpu"; +- clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; +- clock-names = "aclk", "hclk"; +- iommus = <&vpu_mmu>; +- power-domains = <&power RK3399_PD_VCODEC>; +- }; +- +- vpu_mmu: iommu@ff650800 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff650800 0x0 0x40>; +- interrupts = ; +- interrupt-names = "vpu_mmu"; +- clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- power-domains = <&power RK3399_PD_VCODEC>; +- }; +- +- vdec: video-codec@ff660000 { +- compatible = "rockchip,rk3399-vdec"; +- reg = <0x0 0xff660000 0x0 0x400>; +- interrupts = ; +- clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, +- <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; +- clock-names = "axi", "ahb", "cabac", "core"; +- iommus = <&vdec_mmu>; +- power-domains = <&power RK3399_PD_VDU>; +- }; +- +- vdec_mmu: iommu@ff660480 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; +- interrupts = ; +- interrupt-names = "vdec_mmu"; +- clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; +- clock-names = "aclk", "iface"; +- power-domains = <&power RK3399_PD_VDU>; +- #iommu-cells = <0>; +- }; +- +- iep_mmu: iommu@ff670800 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff670800 0x0 0x40>; +- interrupts = ; +- interrupt-names = "iep_mmu"; +- clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- rga: rga@ff680000 { +- compatible = "rockchip,rk3399-rga"; +- reg = <0x0 0xff680000 0x0 0x10000>; +- interrupts = ; +- clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; +- clock-names = "aclk", "hclk", "sclk"; +- resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; +- reset-names = "core", "axi", "ahb"; +- power-domains = <&power RK3399_PD_RGA>; +- }; +- +- efuse0: efuse@ff690000 { +- compatible = "rockchip,rk3399-efuse"; +- reg = <0x0 0xff690000 0x0 0x80>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&cru PCLK_EFUSE1024NS>; +- clock-names = "pclk_efuse"; +- +- /* Data cells */ +- cpu_id: cpu-id@7 { +- reg = <0x07 0x10>; +- }; +- cpub_leakage: cpu-leakage@17 { +- reg = <0x17 0x1>; +- }; +- gpu_leakage: gpu-leakage@18 { +- reg = <0x18 0x1>; +- }; +- center_leakage: center-leakage@19 { +- reg = <0x19 0x1>; +- }; +- cpul_leakage: cpu-leakage@1a { +- reg = <0x1a 0x1>; +- }; +- logic_leakage: logic-leakage@1b { +- reg = <0x1b 0x1>; +- }; +- wafer_info: wafer-info@1c { +- reg = <0x1c 0x1>; +- }; +- }; +- +- dmac_bus: dma-controller@ff6d0000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xff6d0000 0x0 0x4000>; +- interrupts = , +- ; +- #dma-cells = <1>; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMAC0_PERILP>; +- clock-names = "apb_pclk"; +- }; +- +- dmac_peri: dma-controller@ff6e0000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xff6e0000 0x0 0x4000>; +- interrupts = , +- ; +- #dma-cells = <1>; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMAC1_PERILP>; +- clock-names = "apb_pclk"; +- }; +- +- pmucru: pmu-clock-controller@ff750000 { +- compatible = "rockchip,rk3399-pmucru"; +- reg = <0x0 0xff750000 0x0 0x1000>; +- rockchip,grf = <&pmugrf>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- assigned-clocks = <&pmucru PLL_PPLL>; +- assigned-clock-rates = <676000000>; +- }; +- +- cru: clock-controller@ff760000 { +- compatible = "rockchip,rk3399-cru"; +- reg = <0x0 0xff760000 0x0 0x1000>; +- rockchip,grf = <&grf>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- assigned-clocks = +- <&cru PLL_GPLL>, <&cru PLL_CPLL>, +- <&cru PLL_NPLL>, +- <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, +- <&cru PCLK_PERIHP>, +- <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, +- <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, +- <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, +- <&cru ACLK_VIO>, <&cru ACLK_HDCP>, +- <&cru ACLK_GIC_PRE>, +- <&cru PCLK_DDR>; +- assigned-clock-rates = +- <594000000>, <800000000>, +- <1000000000>, +- <150000000>, <75000000>, +- <37500000>, +- <100000000>, <100000000>, +- <50000000>, <600000000>, +- <100000000>, <50000000>, +- <400000000>, <400000000>, +- <200000000>, +- <200000000>; +- }; +- +- grf: syscon@ff770000 { +- compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; +- reg = <0x0 0xff770000 0x0 0x10000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- io_domains: io-domains { +- compatible = "rockchip,rk3399-io-voltage-domain"; +- status = "disabled"; +- }; +- +- mipi_dphy_rx0: mipi-dphy-rx0 { +- compatible = "rockchip,rk3399-mipi-dphy-rx0"; +- clocks = <&cru SCLK_MIPIDPHY_REF>, +- <&cru SCLK_DPHY_RX0_CFG>, +- <&cru PCLK_VIO_GRF>; +- clock-names = "dphy-ref", "dphy-cfg", "grf"; +- power-domains = <&power RK3399_PD_VIO>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- u2phy0: usb2phy@e450 { +- compatible = "rockchip,rk3399-usb2phy"; +- reg = <0xe450 0x10>; +- clocks = <&cru SCLK_USB2PHY0_REF>; +- clock-names = "phyclk"; +- #clock-cells = <0>; +- clock-output-names = "clk_usbphy0_480m"; +- status = "disabled"; +- +- u2phy0_host: host-port { +- #phy-cells = <0>; +- interrupts = ; +- interrupt-names = "linestate"; +- status = "disabled"; +- }; +- +- u2phy0_otg: otg-port { +- #phy-cells = <0>; +- interrupts = , +- , +- ; +- interrupt-names = "otg-bvalid", "otg-id", +- "linestate"; +- status = "disabled"; +- }; +- }; +- +- u2phy1: usb2phy@e460 { +- compatible = "rockchip,rk3399-usb2phy"; +- reg = <0xe460 0x10>; +- clocks = <&cru SCLK_USB2PHY1_REF>; +- clock-names = "phyclk"; +- #clock-cells = <0>; +- clock-output-names = "clk_usbphy1_480m"; +- status = "disabled"; +- +- u2phy1_host: host-port { +- #phy-cells = <0>; +- interrupts = ; +- interrupt-names = "linestate"; +- status = "disabled"; +- }; +- +- u2phy1_otg: otg-port { +- #phy-cells = <0>; +- interrupts = , +- , +- ; +- interrupt-names = "otg-bvalid", "otg-id", +- "linestate"; +- status = "disabled"; +- }; +- }; +- +- emmc_phy: phy@f780 { +- compatible = "rockchip,rk3399-emmc-phy"; +- reg = <0xf780 0x24>; +- clocks = <&sdhci>; +- clock-names = "emmcclk"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- pcie_phy: pcie-phy { +- compatible = "rockchip,rk3399-pcie-phy"; +- clocks = <&cru SCLK_PCIEPHY_REF>; +- clock-names = "refclk"; +- #phy-cells = <1>; +- resets = <&cru SRST_PCIEPHY>; +- drive-impedance-ohm = <50>; +- reset-names = "phy"; +- status = "disabled"; +- }; +- }; +- +- tcphy0: phy@ff7c0000 { +- compatible = "rockchip,rk3399-typec-phy"; +- reg = <0x0 0xff7c0000 0x0 0x40000>; +- clocks = <&cru SCLK_UPHY0_TCPDCORE>, +- <&cru SCLK_UPHY0_TCPDPHY_REF>; +- clock-names = "tcpdcore", "tcpdphy-ref"; +- assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; +- assigned-clock-rates = <50000000>; +- power-domains = <&power RK3399_PD_TCPD0>; +- resets = <&cru SRST_UPHY0>, +- <&cru SRST_UPHY0_PIPE_L00>, +- <&cru SRST_P_UPHY0_TCPHY>; +- reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; +- rockchip,grf = <&grf>; +- status = "disabled"; +- +- tcphy0_dp: dp-port { +- #phy-cells = <0>; +- }; +- +- tcphy0_usb3: usb3-port { +- #phy-cells = <0>; +- }; +- }; +- +- tcphy1: phy@ff800000 { +- compatible = "rockchip,rk3399-typec-phy"; +- reg = <0x0 0xff800000 0x0 0x40000>; +- clocks = <&cru SCLK_UPHY1_TCPDCORE>, +- <&cru SCLK_UPHY1_TCPDPHY_REF>; +- clock-names = "tcpdcore", "tcpdphy-ref"; +- assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; +- assigned-clock-rates = <50000000>; +- power-domains = <&power RK3399_PD_TCPD1>; +- resets = <&cru SRST_UPHY1>, +- <&cru SRST_UPHY1_PIPE_L00>, +- <&cru SRST_P_UPHY1_TCPHY>; +- reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; +- rockchip,grf = <&grf>; +- status = "disabled"; +- +- tcphy1_dp: dp-port { +- #phy-cells = <0>; +- }; +- +- tcphy1_usb3: usb3-port { +- #phy-cells = <0>; +- }; +- }; +- +- watchdog@ff848000 { +- compatible = "rockchip,rk3399-wdt", "snps,dw-wdt"; +- reg = <0x0 0xff848000 0x0 0x100>; +- clocks = <&cru PCLK_WDT>; +- interrupts = ; +- }; +- +- rktimer: rktimer@ff850000 { +- compatible = "rockchip,rk3399-timer"; +- reg = <0x0 0xff850000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; +- clock-names = "pclk", "timer"; +- }; +- +- spdif: spdif@ff870000 { +- compatible = "rockchip,rk3399-spdif"; +- reg = <0x0 0xff870000 0x0 0x1000>; +- interrupts = ; +- dmas = <&dmac_bus 7>; +- dma-names = "tx"; +- clock-names = "mclk", "hclk"; +- clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; +- pinctrl-names = "default"; +- pinctrl-0 = <&spdif_bus>; +- power-domains = <&power RK3399_PD_SDIOAUDIO>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- i2s0: i2s@ff880000 { +- compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; +- reg = <0x0 0xff880000 0x0 0x1000>; +- rockchip,grf = <&grf>; +- interrupts = ; +- dmas = <&dmac_bus 0>, <&dmac_bus 1>; +- dma-names = "tx", "rx"; +- clock-names = "i2s_clk", "i2s_hclk"; +- clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s0_8ch_bus>; +- power-domains = <&power RK3399_PD_SDIOAUDIO>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- i2s1: i2s@ff890000 { +- compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; +- reg = <0x0 0xff890000 0x0 0x1000>; +- interrupts = ; +- dmas = <&dmac_bus 2>, <&dmac_bus 3>; +- dma-names = "tx", "rx"; +- clock-names = "i2s_clk", "i2s_hclk"; +- clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s1_2ch_bus>; +- power-domains = <&power RK3399_PD_SDIOAUDIO>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- i2s2: i2s@ff8a0000 { +- compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; +- reg = <0x0 0xff8a0000 0x0 0x1000>; +- interrupts = ; +- dmas = <&dmac_bus 4>, <&dmac_bus 5>; +- dma-names = "tx", "rx"; +- clock-names = "i2s_clk", "i2s_hclk"; +- clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; +- power-domains = <&power RK3399_PD_SDIOAUDIO>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- vopl: vop@ff8f0000 { +- compatible = "rockchip,rk3399-vop-lit"; +- reg = <0x0 0xff8f0000 0x0 0x3efc>; +- interrupts = ; +- assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; +- assigned-clock-rates = <400000000>, <100000000>; +- clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; +- clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; +- iommus = <&vopl_mmu>; +- power-domains = <&power RK3399_PD_VOPL>; +- resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; +- reset-names = "axi", "ahb", "dclk"; +- status = "disabled"; +- +- vopl_out: port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- vopl_out_mipi: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&mipi_in_vopl>; +- }; +- +- vopl_out_edp: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&edp_in_vopl>; +- }; +- +- vopl_out_hdmi: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&hdmi_in_vopl>; +- }; +- +- vopl_out_mipi1: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&mipi1_in_vopl>; +- }; +- +- vopl_out_dp: endpoint@4 { +- reg = <4>; +- remote-endpoint = <&dp_in_vopl>; +- }; +- }; +- }; +- +- vopl_mmu: iommu@ff8f3f00 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff8f3f00 0x0 0x100>; +- interrupts = ; +- interrupt-names = "vopl_mmu"; +- clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; +- clock-names = "aclk", "iface"; +- power-domains = <&power RK3399_PD_VOPL>; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- vopb: vop@ff900000 { +- compatible = "rockchip,rk3399-vop-big"; +- reg = <0x0 0xff900000 0x0 0x3efc>; +- interrupts = ; +- assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; +- assigned-clock-rates = <400000000>, <100000000>; +- clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; +- clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; +- iommus = <&vopb_mmu>; +- power-domains = <&power RK3399_PD_VOPB>; +- resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; +- reset-names = "axi", "ahb", "dclk"; +- status = "disabled"; +- +- vopb_out: port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- vopb_out_edp: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&edp_in_vopb>; +- }; +- +- vopb_out_mipi: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&mipi_in_vopb>; +- }; +- +- vopb_out_hdmi: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&hdmi_in_vopb>; +- }; +- +- vopb_out_mipi1: endpoint@3 { +- reg = <3>; +- remote-endpoint = <&mipi1_in_vopb>; +- }; +- +- vopb_out_dp: endpoint@4 { +- reg = <4>; +- remote-endpoint = <&dp_in_vopb>; +- }; +- }; +- }; +- +- vopb_mmu: iommu@ff903f00 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff903f00 0x0 0x100>; +- interrupts = ; +- interrupt-names = "vopb_mmu"; +- clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; +- clock-names = "aclk", "iface"; +- power-domains = <&power RK3399_PD_VOPB>; +- #iommu-cells = <0>; +- status = "disabled"; +- }; +- +- isp0: isp0@ff910000 { +- compatible = "rockchip,rk3399-cif-isp"; +- reg = <0x0 0xff910000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cru SCLK_ISP0>, +- <&cru ACLK_ISP0_WRAPPER>, +- <&cru HCLK_ISP0_WRAPPER>; +- clock-names = "isp", "aclk", "hclk"; +- iommus = <&isp0_mmu>; +- phys = <&mipi_dphy_rx0>; +- phy-names = "dphy"; +- power-domains = <&power RK3399_PD_ISP0>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- }; +- +- isp0_mmu: iommu@ff914000 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; +- interrupts = ; +- interrupt-names = "isp0_mmu"; +- clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- power-domains = <&power RK3399_PD_ISP0>; +- rockchip,disable-mmu-reset; +- }; +- +- isp1_mmu: iommu@ff924000 { +- compatible = "rockchip,iommu"; +- reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; +- interrupts = ; +- interrupt-names = "isp1_mmu"; +- clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- power-domains = <&power RK3399_PD_ISP1>; +- rockchip,disable-mmu-reset; +- }; +- +- hdmi_sound: hdmi-sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,mclk-fs = <256>; +- simple-audio-card,name = "hdmi-sound"; +- status = "disabled"; +- +- simple-audio-card,cpu { +- sound-dai = <&i2s2>; +- }; +- simple-audio-card,codec { +- sound-dai = <&hdmi>; +- }; +- }; +- +- hdmi: hdmi@ff940000 { +- compatible = "rockchip,rk3399-dw-hdmi"; +- reg = <0x0 0xff940000 0x0 0x20000>; +- interrupts = ; +- clocks = <&cru PCLK_HDMI_CTRL>, +- <&cru SCLK_HDMI_SFR>, +- <&cru SCLK_HDMI_CEC>, +- <&cru PCLK_VIO_GRF>, +- <&cru PLL_VPLL>; +- clock-names = "iahb", "isfr", "cec", "grf", "vpll"; +- power-domains = <&power RK3399_PD_HDCP>; +- reg-io-width = <4>; +- rockchip,grf = <&grf>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- +- ports { +- hdmi_in: port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- hdmi_in_vopb: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vopb_out_hdmi>; +- }; +- hdmi_in_vopl: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vopl_out_hdmi>; +- }; +- }; +- }; +- }; +- +- mipi_dsi: mipi@ff960000 { +- compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; +- reg = <0x0 0xff960000 0x0 0x8000>; +- interrupts = ; +- clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, +- <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; +- clock-names = "ref", "pclk", "phy_cfg", "grf"; +- power-domains = <&power RK3399_PD_VIO>; +- resets = <&cru SRST_P_MIPI_DSI0>; +- reset-names = "apb"; +- rockchip,grf = <&grf>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mipi_in: port@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- mipi_in_vopb: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vopb_out_mipi>; +- }; +- mipi_in_vopl: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vopl_out_mipi>; +- }; +- }; +- }; +- }; +- +- mipi_dsi1: mipi@ff968000 { +- compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; +- reg = <0x0 0xff968000 0x0 0x8000>; +- interrupts = ; +- clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, +- <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; +- clock-names = "ref", "pclk", "phy_cfg", "grf"; +- power-domains = <&power RK3399_PD_VIO>; +- resets = <&cru SRST_P_MIPI_DSI1>; +- reset-names = "apb"; +- rockchip,grf = <&grf>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mipi1_in: port@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- mipi1_in_vopb: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vopb_out_mipi1>; +- }; +- +- mipi1_in_vopl: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vopl_out_mipi1>; +- }; +- }; +- }; +- }; +- +- edp: edp@ff970000 { +- compatible = "rockchip,rk3399-edp"; +- reg = <0x0 0xff970000 0x0 0x8000>; +- interrupts = ; +- clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; +- clock-names = "dp", "pclk", "grf"; +- pinctrl-names = "default"; +- pinctrl-0 = <&edp_hpd>; +- power-domains = <&power RK3399_PD_EDP>; +- resets = <&cru SRST_P_EDP_CTRL>; +- reset-names = "dp"; +- rockchip,grf = <&grf>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- edp_in: port@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- edp_in_vopb: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&vopb_out_edp>; +- }; +- +- edp_in_vopl: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vopl_out_edp>; +- }; +- }; +- }; +- }; +- +- gpu: gpu@ff9a0000 { +- compatible = "rockchip,rk3399-mali", "arm,mali-t860"; +- reg = <0x0 0xff9a0000 0x0 0x10000>; +- interrupts = , +- , +- ; +- interrupt-names = "job", "mmu", "gpu"; +- clocks = <&cru ACLK_GPU>; +- #cooling-cells = <2>; +- power-domains = <&power RK3399_PD_GPU>; +- status = "disabled"; +- }; +- +- pinctrl: pinctrl { +- compatible = "rockchip,rk3399-pinctrl"; +- rockchip,grf = <&grf>; +- rockchip,pmu = <&pmugrf>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gpio0: gpio0@ff720000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff720000 0x0 0x100>; +- clocks = <&pmucru PCLK_GPIO0_PMU>; +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <0x2>; +- +- interrupt-controller; +- #interrupt-cells = <0x2>; +- }; +- +- gpio1: gpio1@ff730000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff730000 0x0 0x100>; +- clocks = <&pmucru PCLK_GPIO1_PMU>; +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <0x2>; +- +- interrupt-controller; +- #interrupt-cells = <0x2>; +- }; +- +- gpio2: gpio2@ff780000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff780000 0x0 0x100>; +- clocks = <&cru PCLK_GPIO2>; +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <0x2>; +- +- interrupt-controller; +- #interrupt-cells = <0x2>; +- }; +- +- gpio3: gpio3@ff788000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff788000 0x0 0x100>; +- clocks = <&cru PCLK_GPIO3>; +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <0x2>; +- +- interrupt-controller; +- #interrupt-cells = <0x2>; +- }; +- +- gpio4: gpio4@ff790000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xff790000 0x0 0x100>; +- clocks = <&cru PCLK_GPIO4>; +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <0x2>; +- +- interrupt-controller; +- #interrupt-cells = <0x2>; +- }; +- +- pcfg_pull_up: pcfg-pull-up { +- bias-pull-up; +- }; +- +- pcfg_pull_down: pcfg-pull-down { +- bias-pull-down; +- }; +- +- pcfg_pull_none: pcfg-pull-none { +- bias-disable; +- }; +- +- pcfg_pull_none_12ma: pcfg-pull-none-12ma { +- bias-disable; +- drive-strength = <12>; +- }; +- +- pcfg_pull_none_13ma: pcfg-pull-none-13ma { +- bias-disable; +- drive-strength = <13>; +- }; +- +- pcfg_pull_none_18ma: pcfg-pull-none-18ma { +- bias-disable; +- drive-strength = <18>; +- }; +- +- pcfg_pull_none_20ma: pcfg-pull-none-20ma { +- bias-disable; +- drive-strength = <20>; +- }; +- +- pcfg_pull_up_2ma: pcfg-pull-up-2ma { +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- pcfg_pull_up_8ma: pcfg-pull-up-8ma { +- bias-pull-up; +- drive-strength = <8>; +- }; +- +- pcfg_pull_up_18ma: pcfg-pull-up-18ma { +- bias-pull-up; +- drive-strength = <18>; +- }; +- +- pcfg_pull_up_20ma: pcfg-pull-up-20ma { +- bias-pull-up; +- drive-strength = <20>; +- }; +- +- pcfg_pull_down_4ma: pcfg-pull-down-4ma { +- bias-pull-down; +- drive-strength = <4>; +- }; +- +- pcfg_pull_down_8ma: pcfg-pull-down-8ma { +- bias-pull-down; +- drive-strength = <8>; +- }; +- +- pcfg_pull_down_12ma: pcfg-pull-down-12ma { +- bias-pull-down; +- drive-strength = <12>; +- }; +- +- pcfg_pull_down_18ma: pcfg-pull-down-18ma { +- bias-pull-down; +- drive-strength = <18>; +- }; +- +- pcfg_pull_down_20ma: pcfg-pull-down-20ma { +- bias-pull-down; +- drive-strength = <20>; +- }; +- +- pcfg_output_high: pcfg-output-high { +- output-high; +- }; +- +- pcfg_output_low: pcfg-output-low { +- output-low; +- }; +- +- clock { +- clk_32k: clk-32k { +- rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; +- }; +- }; +- +- edp { +- edp_hpd: edp-hpd { +- rockchip,pins = +- <4 RK_PC7 2 &pcfg_pull_none>; +- }; +- }; +- +- gmac { +- rgmii_pins: rgmii-pins { +- rockchip,pins = +- /* mac_txclk */ +- <3 RK_PC1 1 &pcfg_pull_none_13ma>, +- /* mac_rxclk */ +- <3 RK_PB6 1 &pcfg_pull_none>, +- /* mac_mdio */ +- <3 RK_PB5 1 &pcfg_pull_none>, +- /* mac_txen */ +- <3 RK_PB4 1 &pcfg_pull_none_13ma>, +- /* mac_clk */ +- <3 RK_PB3 1 &pcfg_pull_none>, +- /* mac_rxdv */ +- <3 RK_PB1 1 &pcfg_pull_none>, +- /* mac_mdc */ +- <3 RK_PB0 1 &pcfg_pull_none>, +- /* mac_rxd1 */ +- <3 RK_PA7 1 &pcfg_pull_none>, +- /* mac_rxd0 */ +- <3 RK_PA6 1 &pcfg_pull_none>, +- /* mac_txd1 */ +- <3 RK_PA5 1 &pcfg_pull_none_13ma>, +- /* mac_txd0 */ +- <3 RK_PA4 1 &pcfg_pull_none_13ma>, +- /* mac_rxd3 */ +- <3 RK_PA3 1 &pcfg_pull_none>, +- /* mac_rxd2 */ +- <3 RK_PA2 1 &pcfg_pull_none>, +- /* mac_txd3 */ +- <3 RK_PA1 1 &pcfg_pull_none_13ma>, +- /* mac_txd2 */ +- <3 RK_PA0 1 &pcfg_pull_none_13ma>; +- }; +- +- rmii_pins: rmii-pins { +- rockchip,pins = +- /* mac_mdio */ +- <3 RK_PB5 1 &pcfg_pull_none>, +- /* mac_txen */ +- <3 RK_PB4 1 &pcfg_pull_none_13ma>, +- /* mac_clk */ +- <3 RK_PB3 1 &pcfg_pull_none>, +- /* mac_rxer */ +- <3 RK_PB2 1 &pcfg_pull_none>, +- /* mac_rxdv */ +- <3 RK_PB1 1 &pcfg_pull_none>, +- /* mac_mdc */ +- <3 RK_PB0 1 &pcfg_pull_none>, +- /* mac_rxd1 */ +- <3 RK_PA7 1 &pcfg_pull_none>, +- /* mac_rxd0 */ +- <3 RK_PA6 1 &pcfg_pull_none>, +- /* mac_txd1 */ +- <3 RK_PA5 1 &pcfg_pull_none_13ma>, +- /* mac_txd0 */ +- <3 RK_PA4 1 &pcfg_pull_none_13ma>; +- }; +- }; +- +- i2c0 { +- i2c0_xfer: i2c0-xfer { +- rockchip,pins = +- <1 RK_PB7 2 &pcfg_pull_none>, +- <1 RK_PC0 2 &pcfg_pull_none>; +- }; +- }; +- +- i2c1 { +- i2c1_xfer: i2c1-xfer { +- rockchip,pins = +- <4 RK_PA2 1 &pcfg_pull_none>, +- <4 RK_PA1 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c2 { +- i2c2_xfer: i2c2-xfer { +- rockchip,pins = +- <2 RK_PA1 2 &pcfg_pull_none_12ma>, +- <2 RK_PA0 2 &pcfg_pull_none_12ma>; +- }; +- }; +- +- i2c3 { +- i2c3_xfer: i2c3-xfer { +- rockchip,pins = +- <4 RK_PC1 1 &pcfg_pull_none>, +- <4 RK_PC0 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c4 { +- i2c4_xfer: i2c4-xfer { +- rockchip,pins = +- <1 RK_PB4 1 &pcfg_pull_none>, +- <1 RK_PB3 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c5 { +- i2c5_xfer: i2c5-xfer { +- rockchip,pins = +- <3 RK_PB3 2 &pcfg_pull_none>, +- <3 RK_PB2 2 &pcfg_pull_none>; +- }; +- }; +- +- i2c6 { +- i2c6_xfer: i2c6-xfer { +- rockchip,pins = +- <2 RK_PB2 2 &pcfg_pull_none>, +- <2 RK_PB1 2 &pcfg_pull_none>; +- }; +- }; +- +- i2c7 { +- i2c7_xfer: i2c7-xfer { +- rockchip,pins = +- <2 RK_PB0 2 &pcfg_pull_none>, +- <2 RK_PA7 2 &pcfg_pull_none>; +- }; +- }; +- +- i2c8 { +- i2c8_xfer: i2c8-xfer { +- rockchip,pins = +- <1 RK_PC5 1 &pcfg_pull_none>, +- <1 RK_PC4 1 &pcfg_pull_none>; +- }; +- }; +- +- i2s0 { +- i2s0_2ch_bus: i2s0-2ch-bus { +- rockchip,pins = +- <3 RK_PD0 1 &pcfg_pull_none>, +- <3 RK_PD1 1 &pcfg_pull_none>, +- <3 RK_PD2 1 &pcfg_pull_none>, +- <3 RK_PD3 1 &pcfg_pull_none>, +- <3 RK_PD7 1 &pcfg_pull_none>, +- <4 RK_PA0 1 &pcfg_pull_none>; +- }; +- +- i2s0_8ch_bus: i2s0-8ch-bus { +- rockchip,pins = +- <3 RK_PD0 1 &pcfg_pull_none>, +- <3 RK_PD1 1 &pcfg_pull_none>, +- <3 RK_PD2 1 &pcfg_pull_none>, +- <3 RK_PD3 1 &pcfg_pull_none>, +- <3 RK_PD4 1 &pcfg_pull_none>, +- <3 RK_PD5 1 &pcfg_pull_none>, +- <3 RK_PD6 1 &pcfg_pull_none>, +- <3 RK_PD7 1 &pcfg_pull_none>, +- <4 RK_PA0 1 &pcfg_pull_none>; +- }; +- }; +- +- i2s1 { +- i2s1_2ch_bus: i2s1-2ch-bus { +- rockchip,pins = +- <4 RK_PA3 1 &pcfg_pull_none>, +- <4 RK_PA4 1 &pcfg_pull_none>, +- <4 RK_PA5 1 &pcfg_pull_none>, +- <4 RK_PA6 1 &pcfg_pull_none>, +- <4 RK_PA7 1 &pcfg_pull_none>; +- }; +- }; +- +- sdio0 { +- sdio0_bus1: sdio0-bus1 { +- rockchip,pins = +- <2 RK_PC4 1 &pcfg_pull_up>; +- }; +- +- sdio0_bus4: sdio0-bus4 { +- rockchip,pins = +- <2 RK_PC4 1 &pcfg_pull_up>, +- <2 RK_PC5 1 &pcfg_pull_up>, +- <2 RK_PC6 1 &pcfg_pull_up>, +- <2 RK_PC7 1 &pcfg_pull_up>; +- }; +- +- sdio0_cmd: sdio0-cmd { +- rockchip,pins = +- <2 RK_PD0 1 &pcfg_pull_up>; +- }; +- +- sdio0_clk: sdio0-clk { +- rockchip,pins = +- <2 RK_PD1 1 &pcfg_pull_none>; +- }; +- +- sdio0_cd: sdio0-cd { +- rockchip,pins = +- <2 RK_PD2 1 &pcfg_pull_up>; +- }; +- +- sdio0_pwr: sdio0-pwr { +- rockchip,pins = +- <2 RK_PD3 1 &pcfg_pull_up>; +- }; +- +- sdio0_bkpwr: sdio0-bkpwr { +- rockchip,pins = +- <2 RK_PD4 1 &pcfg_pull_up>; +- }; +- +- sdio0_wp: sdio0-wp { +- rockchip,pins = +- <0 RK_PA3 1 &pcfg_pull_up>; +- }; +- +- sdio0_int: sdio0-int { +- rockchip,pins = +- <0 RK_PA4 1 &pcfg_pull_up>; +- }; +- }; +- +- sdmmc { +- sdmmc_bus1: sdmmc-bus1 { +- rockchip,pins = +- <4 RK_PB0 1 &pcfg_pull_up>; +- }; +- +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = +- <4 RK_PB0 1 &pcfg_pull_up>, +- <4 RK_PB1 1 &pcfg_pull_up>, +- <4 RK_PB2 1 &pcfg_pull_up>, +- <4 RK_PB3 1 &pcfg_pull_up>; +- }; +- +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = +- <4 RK_PB4 1 &pcfg_pull_none>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = +- <4 RK_PB5 1 &pcfg_pull_up>; +- }; +- +- sdmmc_cd: sdmmc-cd { +- rockchip,pins = +- <0 RK_PA7 1 &pcfg_pull_up>; +- }; +- +- sdmmc_wp: sdmmc-wp { +- rockchip,pins = +- <0 RK_PB0 1 &pcfg_pull_up>; +- }; +- }; +- +- suspend { +- ap_pwroff: ap-pwroff { +- rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; +- }; +- +- ddrio_pwroff: ddrio-pwroff { +- rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; +- }; +- }; +- +- spdif { +- spdif_bus: spdif-bus { +- rockchip,pins = +- <4 RK_PC5 1 &pcfg_pull_none>; +- }; +- +- spdif_bus_1: spdif-bus-1 { +- rockchip,pins = +- <3 RK_PC0 3 &pcfg_pull_none>; +- }; +- }; +- +- spi0 { +- spi0_clk: spi0-clk { +- rockchip,pins = +- <3 RK_PA6 2 &pcfg_pull_up>; +- }; +- spi0_cs0: spi0-cs0 { +- rockchip,pins = +- <3 RK_PA7 2 &pcfg_pull_up>; +- }; +- spi0_cs1: spi0-cs1 { +- rockchip,pins = +- <3 RK_PB0 2 &pcfg_pull_up>; +- }; +- spi0_tx: spi0-tx { +- rockchip,pins = +- <3 RK_PA5 2 &pcfg_pull_up>; +- }; +- spi0_rx: spi0-rx { +- rockchip,pins = +- <3 RK_PA4 2 &pcfg_pull_up>; +- }; +- }; +- +- spi1 { +- spi1_clk: spi1-clk { +- rockchip,pins = +- <1 RK_PB1 2 &pcfg_pull_up>; +- }; +- spi1_cs0: spi1-cs0 { +- rockchip,pins = +- <1 RK_PB2 2 &pcfg_pull_up>; +- }; +- spi1_rx: spi1-rx { +- rockchip,pins = +- <1 RK_PA7 2 &pcfg_pull_up>; +- }; +- spi1_tx: spi1-tx { +- rockchip,pins = +- <1 RK_PB0 2 &pcfg_pull_up>; +- }; +- }; +- +- spi2 { +- spi2_clk: spi2-clk { +- rockchip,pins = +- <2 RK_PB3 1 &pcfg_pull_up>; +- }; +- spi2_cs0: spi2-cs0 { +- rockchip,pins = +- <2 RK_PB4 1 &pcfg_pull_up>; +- }; +- spi2_rx: spi2-rx { +- rockchip,pins = +- <2 RK_PB1 1 &pcfg_pull_up>; +- }; +- spi2_tx: spi2-tx { +- rockchip,pins = +- <2 RK_PB2 1 &pcfg_pull_up>; +- }; +- }; +- +- spi3 { +- spi3_clk: spi3-clk { +- rockchip,pins = +- <1 RK_PC1 1 &pcfg_pull_up>; +- }; +- spi3_cs0: spi3-cs0 { +- rockchip,pins = +- <1 RK_PC2 1 &pcfg_pull_up>; +- }; +- spi3_rx: spi3-rx { +- rockchip,pins = +- <1 RK_PB7 1 &pcfg_pull_up>; +- }; +- spi3_tx: spi3-tx { +- rockchip,pins = +- <1 RK_PC0 1 &pcfg_pull_up>; +- }; +- }; +- +- spi4 { +- spi4_clk: spi4-clk { +- rockchip,pins = +- <3 RK_PA2 2 &pcfg_pull_up>; +- }; +- spi4_cs0: spi4-cs0 { +- rockchip,pins = +- <3 RK_PA3 2 &pcfg_pull_up>; +- }; +- spi4_rx: spi4-rx { +- rockchip,pins = +- <3 RK_PA0 2 &pcfg_pull_up>; +- }; +- spi4_tx: spi4-tx { +- rockchip,pins = +- <3 RK_PA1 2 &pcfg_pull_up>; +- }; +- }; +- +- spi5 { +- spi5_clk: spi5-clk { +- rockchip,pins = +- <2 RK_PC6 2 &pcfg_pull_up>; +- }; +- spi5_cs0: spi5-cs0 { +- rockchip,pins = +- <2 RK_PC7 2 &pcfg_pull_up>; +- }; +- spi5_rx: spi5-rx { +- rockchip,pins = +- <2 RK_PC4 2 &pcfg_pull_up>; +- }; +- spi5_tx: spi5-tx { +- rockchip,pins = +- <2 RK_PC5 2 &pcfg_pull_up>; +- }; +- }; +- +- testclk { +- test_clkout0: test-clkout0 { +- rockchip,pins = +- <0 RK_PA0 1 &pcfg_pull_none>; +- }; +- +- test_clkout1: test-clkout1 { +- rockchip,pins = +- <2 RK_PD1 2 &pcfg_pull_none>; +- }; +- +- test_clkout2: test-clkout2 { +- rockchip,pins = +- <0 RK_PB0 3 &pcfg_pull_none>; +- }; +- }; +- +- tsadc { +- otp_pin: otp-pin { +- rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- otp_out: otp-out { +- rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; +- }; +- }; +- +- uart0 { +- uart0_xfer: uart0-xfer { +- rockchip,pins = +- <2 RK_PC0 1 &pcfg_pull_up>, +- <2 RK_PC1 1 &pcfg_pull_none>; +- }; +- +- uart0_cts: uart0-cts { +- rockchip,pins = +- <2 RK_PC2 1 &pcfg_pull_none>; +- }; +- +- uart0_rts: uart0-rts { +- rockchip,pins = +- <2 RK_PC3 1 &pcfg_pull_none>; +- }; +- }; +- +- uart1 { +- uart1_xfer: uart1-xfer { +- rockchip,pins = +- <3 RK_PB4 2 &pcfg_pull_up>, +- <3 RK_PB5 2 &pcfg_pull_none>; +- }; +- }; +- +- uart2a { +- uart2a_xfer: uart2a-xfer { +- rockchip,pins = +- <4 RK_PB0 2 &pcfg_pull_up>, +- <4 RK_PB1 2 &pcfg_pull_none>; +- }; +- }; +- +- uart2b { +- uart2b_xfer: uart2b-xfer { +- rockchip,pins = +- <4 RK_PC0 2 &pcfg_pull_up>, +- <4 RK_PC1 2 &pcfg_pull_none>; +- }; +- }; +- +- uart2c { +- uart2c_xfer: uart2c-xfer { +- rockchip,pins = +- <4 RK_PC3 1 &pcfg_pull_up>, +- <4 RK_PC4 1 &pcfg_pull_none>; +- }; +- }; +- +- uart3 { +- uart3_xfer: uart3-xfer { +- rockchip,pins = +- <3 RK_PB6 2 &pcfg_pull_up>, +- <3 RK_PB7 2 &pcfg_pull_none>; +- }; +- +- uart3_cts: uart3-cts { +- rockchip,pins = +- <3 RK_PC0 2 &pcfg_pull_none>; +- }; +- +- uart3_rts: uart3-rts { +- rockchip,pins = +- <3 RK_PC1 2 &pcfg_pull_none>; +- }; +- }; +- +- uart4 { +- uart4_xfer: uart4-xfer { +- rockchip,pins = +- <1 RK_PA7 1 &pcfg_pull_up>, +- <1 RK_PB0 1 &pcfg_pull_none>; +- }; +- }; +- +- uarthdcp { +- uarthdcp_xfer: uarthdcp-xfer { +- rockchip,pins = +- <4 RK_PC5 2 &pcfg_pull_up>, +- <4 RK_PC6 2 &pcfg_pull_none>; +- }; +- }; +- +- pwm0 { +- pwm0_pin: pwm0-pin { +- rockchip,pins = +- <4 RK_PC2 1 &pcfg_pull_none>; +- }; +- +- pwm0_pin_pull_down: pwm0-pin-pull-down { +- rockchip,pins = +- <4 RK_PC2 1 &pcfg_pull_down>; +- }; +- +- vop0_pwm_pin: vop0-pwm-pin { +- rockchip,pins = +- <4 RK_PC2 2 &pcfg_pull_none>; +- }; +- +- vop1_pwm_pin: vop1-pwm-pin { +- rockchip,pins = +- <4 RK_PC2 3 &pcfg_pull_none>; +- }; +- }; +- +- pwm1 { +- pwm1_pin: pwm1-pin { +- rockchip,pins = +- <4 RK_PC6 1 &pcfg_pull_none>; +- }; +- +- pwm1_pin_pull_down: pwm1-pin-pull-down { +- rockchip,pins = +- <4 RK_PC6 1 &pcfg_pull_down>; +- }; +- }; +- +- pwm2 { +- pwm2_pin: pwm2-pin { +- rockchip,pins = +- <1 RK_PC3 1 &pcfg_pull_none>; +- }; +- +- pwm2_pin_pull_down: pwm2-pin-pull-down { +- rockchip,pins = +- <1 RK_PC3 1 &pcfg_pull_down>; +- }; +- }; +- +- pwm3a { +- pwm3a_pin: pwm3a-pin { +- rockchip,pins = +- <0 RK_PA6 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm3b { +- pwm3b_pin: pwm3b-pin { +- rockchip,pins = +- <1 RK_PB6 1 &pcfg_pull_none>; +- }; +- }; +- +- hdmi { +- hdmi_i2c_xfer: hdmi-i2c-xfer { +- rockchip,pins = +- <4 RK_PC1 3 &pcfg_pull_none>, +- <4 RK_PC0 3 &pcfg_pull_none>; +- }; +- +- hdmi_cec: hdmi-cec { +- rockchip,pins = +- <4 RK_PC7 1 &pcfg_pull_none>; +- }; +- }; +- +- pcie { +- pcie_clkreqn_cpm: pci-clkreqn-cpm { +- rockchip,pins = +- <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- pcie_clkreqnb_cpm: pci-clkreqnb-cpm { +- rockchip,pins = +- <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399pro-rock-pi-n10.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399pro-rock-pi-n10.dts +deleted file mode 100644 +index 369de5dc0ebd..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399pro-rock-pi-n10.dts ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd +- * Copyright (c) 2019 Radxa Limited +- * Copyright (c) 2019 Amarula Solutions(India) +- */ +- +-/dts-v1/; +-#include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" +-#include +-#include "rk3399pro-vmarc-som.dtsi" +- +-/ { +- model = "Radxa ROCK Pi N10"; +- compatible = "radxa,rockpi-n10", "vamrs,rk3399pro-vmarc-som", +- "rockchip,rk3399pro"; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399pro-vmarc-som.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399pro-vmarc-som.dtsi +deleted file mode 100644 +index 01d1a75c8b4d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399pro-vmarc-som.dtsi ++++ /dev/null +@@ -1,477 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd +- * Copyright (c) 2019 Vamrs Limited +- * Copyright (c) 2019 Amarula Solutions(India) +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro"; +- +- aliases { +- mmc0 = &sdmmc; +- mmc1 = &sdhci; +- }; +- +- vcc3v3_pcie: vcc-pcie-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_pwr>; +- regulator-name = "vcc3v3_pcie"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc5v0_sys>; +- }; +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&emmc_phy { +- status = "okay"; +-}; +- +-&gmac { +- assigned-clocks = <&cru SCLK_RMII_SRC>; +- phy-supply = <&vcc_lan>; +- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; +-}; +- +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_cec>; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- i2c-scl-falling-time-ns = <30>; +- i2c-scl-rising-time-ns = <180>; +- status = "okay"; +- +- rk809: pmic@20 { +- compatible = "rockchip,rk809"; +- reg = <0x20>; +- interrupt-parent = <&gpio1>; +- interrupts = ; +- #clock-cells = <1>; +- clock-output-names = "rk808-clkout1", "rk808-clkout2"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- +- vcc1-supply = <&vcc5v0_sys>; +- vcc2-supply = <&vcc5v0_sys>; +- vcc3-supply = <&vcc5v0_sys>; +- vcc4-supply = <&vcc5v0_sys>; +- vcc5-supply = <&vcc_buck5>; +- vcc6-supply = <&vcc_buck5>; +- vcc7-supply = <&vcc5v0_sys>; +- vcc8-supply = <&vcc3v3_sys>; +- vcc9-supply = <&vcc5v0_sys>; +- +- regulators { +- vdd_log: DCDC_REG1 { +- regulator-name = "vdd_log"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-initial-mode = <0x2>; +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <900000>; +- }; +- }; +- +- vdd_cpu_l: DCDC_REG2 { +- regulator-name = "vdd_cpu_l"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- regulator-initial-mode = <0x2>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-initial-mode = <0x2>; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc3v3_sys: DCDC_REG4 { +- regulator-name = "vcc3v3_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-initial-mode = <0x2>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc_buck5: DCDC_REG5 { +- regulator-name = "vcc_buck5"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <2200000>; +- regulator-max-microvolt = <2200000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <2200000>; +- }; +- }; +- +- vcca_0v9: LDO_REG1 { +- regulator-name = "vcca_0v9"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <900000>; +- }; +- }; +- +- vcc_1v8: LDO_REG2 { +- regulator-name = "vcc_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc_0v9: LDO_REG3 { +- regulator-name = "vcc_0v9"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <900000>; +- }; +- }; +- +- vcca_1v8: LDO_REG4 { +- regulator-name = "vcca_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1850000>; +- regulator-max-microvolt = <1850000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1850000>; +- }; +- }; +- +- /* +- * As per BSP, but schematic not showing any regulator +- * pin for LD05. +- */ +- vdd1v5_dvp: LDO_REG5 { +- regulator-name = "vdd1v5_dvp"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v5: LDO_REG6 { +- regulator-name = "vcc_1v5"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vccio_3v0: LDO_REG7 { +- regulator-name = "vccio_3v0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vccio_sd: LDO_REG8 { +- regulator-name = "vccio_sd"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- /* +- * As per BSP, but schematic not showing any regulator +- * pin for LD09. +- */ +- vcc_sd: LDO_REG9 { +- regulator-name = "vcc_sd"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc5v0_usb2: SWITCH_REG1 { +- regulator-name = "vcc5v0_usb2"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <5000000>; +- }; +- }; +- +- vccio_3v3: vcc_lan: SWITCH_REG2 { +- regulator-name = "vccio_3v3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- i2c-scl-falling-time-ns = <30>; +- i2c-scl-rising-time-ns = <140>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <400000>; +- status = "okay"; +- +- hym8563: hym8563@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "hym8563"; +- pinctrl-names = "default"; +- pinctrl-0 = <&hym8563_int>; +- interrupt-parent = <&gpio4>; +- interrupts = ; +- }; +-}; +- +-&i2c3 { +- i2c-scl-rising-time-ns = <450>; +- i2c-scl-falling-time-ns = <15>; +- status = "okay"; +-}; +- +-&io_domains { +- status = "okay"; +- bt656-supply = <&vcca_1v8>; +- gpio1830-supply = <&vccio_3v0>; +- sdmmc-supply = <&vccio_sd>; +-}; +- +-&pcie_phy { +- status = "okay"; +-}; +- +-&pcie0 { +- ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; +- num-lanes = <4>; +- pinctrl-0 = <&pcie_clkreqnb_cpm>; +- pinctrl-names = "default"; +- vpcie0v9-supply = <&vcca_0v9>; /* VCC_0V9_S0 */ +- vpcie1v8-supply = <&vcca_1v8>; /* VCC_1V8_S0 */ +- vpcie3v3-supply = <&vcc3v3_pcie>; +- status = "okay"; +-}; +- +-&pinctrl { +- hym8563 { +- hym8563_int: hym8563-int { +- rockchip,pins = <4 RK_PD6 0 &pcfg_pull_up>; +- }; +- }; +- +- pcie { +- pcie_pwr: pcie-pwr { +- rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = <1 RK_PC2 0 &pcfg_pull_up>; +- }; +- }; +- +- sdio-pwrseq { +- wifi_enable_h: wifi-enable-h { +- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- vbus_host { +- usb1_en_oc: usb1-en-oc { +- rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- vbus_typec { +- usb0_en_oc: usb0-en-oc { +- rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +-}; +- +-&pmu_io_domains { +- status = "okay"; +- pmu1830-supply = <&vcc_1v8>; +-}; +- +-&sdio_pwrseq { +- /* +- * On the module itself this is one of these (depending +- * on the actual card populated): +- * - SDIO_RESET_L_WL_REG_ON +- * - PDN (power down when low) +- */ +- reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; +-}; +- +-&sdhci { +- bus-width = <8>; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- non-removable; +- status = "okay"; +-}; +- +-&sdmmc { +- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; +- max-frequency = <150000000>; +-}; +- +-&tcphy0 { +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <1>; +- rockchip,hw-tshut-polarity = <1>; +- status = "okay"; +-}; +- +-&u2phy0 { +- status = "okay"; +- +- u2phy0_otg: otg-port { +- phy-supply = <&vbus_typec>; +- status = "okay"; +- }; +- +- u2phy0_host: host-port { +- phy-supply = <&vbus_host>; +- status = "okay"; +- }; +-}; +- +- +-&u2phy1 { +- status = "okay"; +- +- u2phy1_host: host-port { +- phy-supply = <&vbus_host>; +- status = "okay"; +- }; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&usbdrd3_0 { +- status = "okay"; +-}; +- +-&usbdrd_dwc3_0 { +- status = "okay"; +-}; +- +-&vbus_host { +- enable-active-high; +- gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; /* USB1_EN_OC# */ +- pinctrl-names = "default"; +- pinctrl-0 = <&usb1_en_oc>; +-}; +- +-&vbus_typec { +- enable-active-high; +- gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; /* USB0_EN_OC# */ +- pinctrl-names = "default"; +- pinctrl-0 = <&usb0_en_oc>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399pro.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3399pro.dtsi +deleted file mode 100644 +index bb5ebf6608b9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3399pro.dtsi ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. +- +-#include "rk3399.dtsi" +- +-/ { +- compatible = "rockchip,rk3399pro"; +-}; +- +-/* Default to enabled since AP talk to NPU part over pcie */ +-&pcie_phy { +- status = "okay"; +-}; +- +-/* Default to enabled since AP talk to NPU part over pcie */ +-&pcie0 { +- ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; +- num-lanes = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie_clkreqn_cpm>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3568-evb1-v10.dts b/scripts/dtc/include-prefixes/arm64/rockchip/rk3568-evb1-v10.dts +deleted file mode 100644 +index 69786557093d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3568-evb1-v10.dts ++++ /dev/null +@@ -1,79 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2021 Rockchip Electronics Co., Ltd. +- * +- */ +- +-/dts-v1/; +-#include +-#include +-#include "rk3568.dtsi" +- +-/ { +- model = "Rockchip RK3568 EVB1 DDR4 V10 Board"; +- compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568"; +- +- chosen: chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- dc_12v: dc-12v { +- compatible = "regulator-fixed"; +- regulator-name = "dc_12v"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- vcc3v3_sys: vcc3v3-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&dc_12v>; +- }; +- +- vcc5v0_sys: vcc5v0-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&dc_12v>; +- }; +- +- vcc3v3_lcd0_n: vcc3v3-lcd0-n { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_lcd0_n"; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v3_lcd1_n: vcc3v3-lcd1-n { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_lcd1_n"; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +-}; +- +-&sdhci { +- bus-width = <8>; +- max-frequency = <200000000>; +- non-removable; +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3568-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3568-pinctrl.dtsi +deleted file mode 100644 +index a588ca95ace2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3568-pinctrl.dtsi ++++ /dev/null +@@ -1,3111 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2021 Rockchip Electronics Co., Ltd. +- */ +- +-#include +-#include "rockchip-pinconf.dtsi" +- +-/* +- * This file is auto generated by pin2dts tool, please keep these code +- * by adding changes at end of this file. +- */ +-&pinctrl { +- acodec { +- /omit-if-no-ref/ +- acodec_pins: acodec-pins { +- rockchip,pins = +- /* acodec_adc_sync */ +- <1 RK_PB1 5 &pcfg_pull_none>, +- /* acodec_adcclk */ +- <1 RK_PA1 5 &pcfg_pull_none>, +- /* acodec_adcdata */ +- <1 RK_PA0 5 &pcfg_pull_none>, +- /* acodec_dac_datal */ +- <1 RK_PA7 5 &pcfg_pull_none>, +- /* acodec_dac_datar */ +- <1 RK_PB0 5 &pcfg_pull_none>, +- /* acodec_dacclk */ +- <1 RK_PA3 5 &pcfg_pull_none>, +- /* acodec_dacsync */ +- <1 RK_PA5 5 &pcfg_pull_none>; +- }; +- }; +- +- audiopwm { +- /omit-if-no-ref/ +- audiopwm_lout: audiopwm-lout { +- rockchip,pins = +- /* audiopwm_lout */ +- <1 RK_PA0 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- audiopwm_loutn: audiopwm-loutn { +- rockchip,pins = +- /* audiopwm_loutn */ +- <1 RK_PA1 6 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- audiopwm_loutp: audiopwm-loutp { +- rockchip,pins = +- /* audiopwm_loutp */ +- <1 RK_PA0 6 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- audiopwm_rout: audiopwm-rout { +- rockchip,pins = +- /* audiopwm_rout */ +- <1 RK_PA1 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- audiopwm_routn: audiopwm-routn { +- rockchip,pins = +- /* audiopwm_routn */ +- <1 RK_PA7 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- audiopwm_routp: audiopwm-routp { +- rockchip,pins = +- /* audiopwm_routp */ +- <1 RK_PA6 4 &pcfg_pull_none>; +- }; +- }; +- +- bt656 { +- /omit-if-no-ref/ +- bt656m0_pins: bt656m0-pins { +- rockchip,pins = +- /* bt656_clkm0 */ +- <3 RK_PA0 2 &pcfg_pull_none>, +- /* bt656_d0m0 */ +- <2 RK_PD0 2 &pcfg_pull_none>, +- /* bt656_d1m0 */ +- <2 RK_PD1 2 &pcfg_pull_none>, +- /* bt656_d2m0 */ +- <2 RK_PD2 2 &pcfg_pull_none>, +- /* bt656_d3m0 */ +- <2 RK_PD3 2 &pcfg_pull_none>, +- /* bt656_d4m0 */ +- <2 RK_PD4 2 &pcfg_pull_none>, +- /* bt656_d5m0 */ +- <2 RK_PD5 2 &pcfg_pull_none>, +- /* bt656_d6m0 */ +- <2 RK_PD6 2 &pcfg_pull_none>, +- /* bt656_d7m0 */ +- <2 RK_PD7 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- bt656m1_pins: bt656m1-pins { +- rockchip,pins = +- /* bt656_clkm1 */ +- <4 RK_PB4 5 &pcfg_pull_none>, +- /* bt656_d0m1 */ +- <3 RK_PC6 5 &pcfg_pull_none>, +- /* bt656_d1m1 */ +- <3 RK_PC7 5 &pcfg_pull_none>, +- /* bt656_d2m1 */ +- <3 RK_PD0 5 &pcfg_pull_none>, +- /* bt656_d3m1 */ +- <3 RK_PD1 5 &pcfg_pull_none>, +- /* bt656_d4m1 */ +- <3 RK_PD2 5 &pcfg_pull_none>, +- /* bt656_d5m1 */ +- <3 RK_PD3 5 &pcfg_pull_none>, +- /* bt656_d6m1 */ +- <3 RK_PD4 5 &pcfg_pull_none>, +- /* bt656_d7m1 */ +- <3 RK_PD5 5 &pcfg_pull_none>; +- }; +- }; +- +- bt1120 { +- /omit-if-no-ref/ +- bt1120_pins: bt1120-pins { +- rockchip,pins = +- /* bt1120_clk */ +- <3 RK_PA6 2 &pcfg_pull_none>, +- /* bt1120_d0 */ +- <3 RK_PA1 2 &pcfg_pull_none>, +- /* bt1120_d1 */ +- <3 RK_PA2 2 &pcfg_pull_none>, +- /* bt1120_d2 */ +- <3 RK_PA3 2 &pcfg_pull_none>, +- /* bt1120_d3 */ +- <3 RK_PA4 2 &pcfg_pull_none>, +- /* bt1120_d4 */ +- <3 RK_PA5 2 &pcfg_pull_none>, +- /* bt1120_d5 */ +- <3 RK_PA7 2 &pcfg_pull_none>, +- /* bt1120_d6 */ +- <3 RK_PB0 2 &pcfg_pull_none>, +- /* bt1120_d7 */ +- <3 RK_PB1 2 &pcfg_pull_none>, +- /* bt1120_d8 */ +- <3 RK_PB2 2 &pcfg_pull_none>, +- /* bt1120_d9 */ +- <3 RK_PB3 2 &pcfg_pull_none>, +- /* bt1120_d10 */ +- <3 RK_PB4 2 &pcfg_pull_none>, +- /* bt1120_d11 */ +- <3 RK_PB5 2 &pcfg_pull_none>, +- /* bt1120_d12 */ +- <3 RK_PB6 2 &pcfg_pull_none>, +- /* bt1120_d13 */ +- <3 RK_PC1 2 &pcfg_pull_none>, +- /* bt1120_d14 */ +- <3 RK_PC2 2 &pcfg_pull_none>, +- /* bt1120_d15 */ +- <3 RK_PC3 2 &pcfg_pull_none>; +- }; +- }; +- +- cam { +- /omit-if-no-ref/ +- cam_clkout0: cam-clkout0 { +- rockchip,pins = +- /* cam_clkout0 */ +- <4 RK_PA7 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- cam_clkout1: cam-clkout1 { +- rockchip,pins = +- /* cam_clkout1 */ +- <4 RK_PB0 1 &pcfg_pull_none>; +- }; +- }; +- +- can0 { +- /omit-if-no-ref/ +- can0m0_pins: can0m0-pins { +- rockchip,pins = +- /* can0_rxm0 */ +- <0 RK_PB4 2 &pcfg_pull_none>, +- /* can0_txm0 */ +- <0 RK_PB3 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- can0m1_pins: can0m1-pins { +- rockchip,pins = +- /* can0_rxm1 */ +- <2 RK_PA2 4 &pcfg_pull_none>, +- /* can0_txm1 */ +- <2 RK_PA1 4 &pcfg_pull_none>; +- }; +- }; +- +- can1 { +- /omit-if-no-ref/ +- can1m0_pins: can1m0-pins { +- rockchip,pins = +- /* can1_rxm0 */ +- <1 RK_PA0 3 &pcfg_pull_none>, +- /* can1_txm0 */ +- <1 RK_PA1 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- can1m1_pins: can1m1-pins { +- rockchip,pins = +- /* can1_rxm1 */ +- <4 RK_PC2 3 &pcfg_pull_none>, +- /* can1_txm1 */ +- <4 RK_PC3 3 &pcfg_pull_none>; +- }; +- }; +- +- can2 { +- /omit-if-no-ref/ +- can2m0_pins: can2m0-pins { +- rockchip,pins = +- /* can2_rxm0 */ +- <4 RK_PB4 3 &pcfg_pull_none>, +- /* can2_txm0 */ +- <4 RK_PB5 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- can2m1_pins: can2m1-pins { +- rockchip,pins = +- /* can2_rxm1 */ +- <2 RK_PB1 4 &pcfg_pull_none>, +- /* can2_txm1 */ +- <2 RK_PB2 4 &pcfg_pull_none>; +- }; +- }; +- +- cif { +- /omit-if-no-ref/ +- cif_clk: cif-clk { +- rockchip,pins = +- /* cif_clkout */ +- <4 RK_PC0 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- cif_dvp_clk: cif-dvp-clk { +- rockchip,pins = +- /* cif_clkin */ +- <4 RK_PC1 1 &pcfg_pull_none>, +- /* cif_href */ +- <4 RK_PB6 1 &pcfg_pull_none>, +- /* cif_vsync */ +- <4 RK_PB7 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- cif_dvp_bus16: cif-dvp-bus16 { +- rockchip,pins = +- /* cif_d8 */ +- <3 RK_PD6 1 &pcfg_pull_none>, +- /* cif_d9 */ +- <3 RK_PD7 1 &pcfg_pull_none>, +- /* cif_d10 */ +- <4 RK_PA0 1 &pcfg_pull_none>, +- /* cif_d11 */ +- <4 RK_PA1 1 &pcfg_pull_none>, +- /* cif_d12 */ +- <4 RK_PA2 1 &pcfg_pull_none>, +- /* cif_d13 */ +- <4 RK_PA3 1 &pcfg_pull_none>, +- /* cif_d14 */ +- <4 RK_PA4 1 &pcfg_pull_none>, +- /* cif_d15 */ +- <4 RK_PA5 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- cif_dvp_bus8: cif-dvp-bus8 { +- rockchip,pins = +- /* cif_d0 */ +- <3 RK_PC6 1 &pcfg_pull_none>, +- /* cif_d1 */ +- <3 RK_PC7 1 &pcfg_pull_none>, +- /* cif_d2 */ +- <3 RK_PD0 1 &pcfg_pull_none>, +- /* cif_d3 */ +- <3 RK_PD1 1 &pcfg_pull_none>, +- /* cif_d4 */ +- <3 RK_PD2 1 &pcfg_pull_none>, +- /* cif_d5 */ +- <3 RK_PD3 1 &pcfg_pull_none>, +- /* cif_d6 */ +- <3 RK_PD4 1 &pcfg_pull_none>, +- /* cif_d7 */ +- <3 RK_PD5 1 &pcfg_pull_none>; +- }; +- }; +- +- clk32k { +- /omit-if-no-ref/ +- clk32k_in: clk32k-in { +- rockchip,pins = +- /* clk32k_in */ +- <0 RK_PB0 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- clk32k_out0: clk32k-out0 { +- rockchip,pins = +- /* clk32k_out0 */ +- <0 RK_PB0 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- clk32k_out1: clk32k-out1 { +- rockchip,pins = +- /* clk32k_out1 */ +- <2 RK_PC6 1 &pcfg_pull_none>; +- }; +- }; +- +- cpu { +- /omit-if-no-ref/ +- cpu_pins: cpu-pins { +- rockchip,pins = +- /* cpu_avs */ +- <0 RK_PB7 2 &pcfg_pull_none>; +- }; +- }; +- +- ebc { +- /omit-if-no-ref/ +- ebc_extern: ebc-extern { +- rockchip,pins = +- /* ebc_sdce1 */ +- <4 RK_PA7 2 &pcfg_pull_none>, +- /* ebc_sdce2 */ +- <4 RK_PB0 2 &pcfg_pull_none>, +- /* ebc_sdce3 */ +- <4 RK_PB1 2 &pcfg_pull_none>, +- /* ebc_sdshr */ +- <4 RK_PB5 2 &pcfg_pull_none>, +- /* ebc_vcom */ +- <4 RK_PB2 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- ebc_pins: ebc-pins { +- rockchip,pins = +- /* ebc_gdclk */ +- <4 RK_PC0 2 &pcfg_pull_none>, +- /* ebc_gdoe */ +- <4 RK_PB3 2 &pcfg_pull_none>, +- /* ebc_gdsp */ +- <4 RK_PB4 2 &pcfg_pull_none>, +- /* ebc_sdce0 */ +- <4 RK_PA6 2 &pcfg_pull_none>, +- /* ebc_sdclk */ +- <4 RK_PC1 2 &pcfg_pull_none>, +- /* ebc_sddo0 */ +- <3 RK_PC6 2 &pcfg_pull_none>, +- /* ebc_sddo1 */ +- <3 RK_PC7 2 &pcfg_pull_none>, +- /* ebc_sddo2 */ +- <3 RK_PD0 2 &pcfg_pull_none>, +- /* ebc_sddo3 */ +- <3 RK_PD1 2 &pcfg_pull_none>, +- /* ebc_sddo4 */ +- <3 RK_PD2 2 &pcfg_pull_none>, +- /* ebc_sddo5 */ +- <3 RK_PD3 2 &pcfg_pull_none>, +- /* ebc_sddo6 */ +- <3 RK_PD4 2 &pcfg_pull_none>, +- /* ebc_sddo7 */ +- <3 RK_PD5 2 &pcfg_pull_none>, +- /* ebc_sddo8 */ +- <3 RK_PD6 2 &pcfg_pull_none>, +- /* ebc_sddo9 */ +- <3 RK_PD7 2 &pcfg_pull_none>, +- /* ebc_sddo10 */ +- <4 RK_PA0 2 &pcfg_pull_none>, +- /* ebc_sddo11 */ +- <4 RK_PA1 2 &pcfg_pull_none>, +- /* ebc_sddo12 */ +- <4 RK_PA2 2 &pcfg_pull_none>, +- /* ebc_sddo13 */ +- <4 RK_PA3 2 &pcfg_pull_none>, +- /* ebc_sddo14 */ +- <4 RK_PA4 2 &pcfg_pull_none>, +- /* ebc_sddo15 */ +- <4 RK_PA5 2 &pcfg_pull_none>, +- /* ebc_sdle */ +- <4 RK_PB6 2 &pcfg_pull_none>, +- /* ebc_sdoe */ +- <4 RK_PB7 2 &pcfg_pull_none>; +- }; +- }; +- +- edpdp { +- /omit-if-no-ref/ +- edpdpm0_pins: edpdpm0-pins { +- rockchip,pins = +- /* edpdp_hpdinm0 */ +- <4 RK_PC4 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- edpdpm1_pins: edpdpm1-pins { +- rockchip,pins = +- /* edpdp_hpdinm1 */ +- <0 RK_PC2 2 &pcfg_pull_none>; +- }; +- }; +- +- emmc { +- /omit-if-no-ref/ +- emmc_rstnout: emmc-rstnout { +- rockchip,pins = +- /* emmc_rstn */ +- <1 RK_PC7 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- emmc_bus8: emmc-bus8 { +- rockchip,pins = +- /* emmc_d0 */ +- <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, +- /* emmc_d1 */ +- <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, +- /* emmc_d2 */ +- <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, +- /* emmc_d3 */ +- <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>, +- /* emmc_d4 */ +- <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>, +- /* emmc_d5 */ +- <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>, +- /* emmc_d6 */ +- <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>, +- /* emmc_d7 */ +- <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- emmc_clk: emmc-clk { +- rockchip,pins = +- /* emmc_clkout */ +- <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- emmc_cmd: emmc-cmd { +- rockchip,pins = +- /* emmc_cmd */ +- <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- emmc_datastrobe: emmc-datastrobe { +- rockchip,pins = +- /* emmc_datastrobe */ +- <1 RK_PC6 1 &pcfg_pull_none>; +- }; +- }; +- +- eth0 { +- /omit-if-no-ref/ +- eth0_pins: eth0-pins { +- rockchip,pins = +- /* eth0_refclko25m */ +- <2 RK_PC1 2 &pcfg_pull_none>; +- }; +- }; +- +- eth1 { +- /omit-if-no-ref/ +- eth1m0_pins: eth1m0-pins { +- rockchip,pins = +- /* eth1_refclko25mm0 */ +- <3 RK_PB0 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- eth1m1_pins: eth1m1-pins { +- rockchip,pins = +- /* eth1_refclko25mm1 */ +- <4 RK_PB3 3 &pcfg_pull_none>; +- }; +- }; +- +- flash { +- /omit-if-no-ref/ +- flash_pins: flash-pins { +- rockchip,pins = +- /* flash_ale */ +- <1 RK_PD0 2 &pcfg_pull_none>, +- /* flash_cle */ +- <1 RK_PC6 3 &pcfg_pull_none>, +- /* flash_cs0n */ +- <1 RK_PD3 2 &pcfg_pull_none>, +- /* flash_cs1n */ +- <1 RK_PD4 2 &pcfg_pull_none>, +- /* flash_d0 */ +- <1 RK_PB4 2 &pcfg_pull_none>, +- /* flash_d1 */ +- <1 RK_PB5 2 &pcfg_pull_none>, +- /* flash_d2 */ +- <1 RK_PB6 2 &pcfg_pull_none>, +- /* flash_d3 */ +- <1 RK_PB7 2 &pcfg_pull_none>, +- /* flash_d4 */ +- <1 RK_PC0 2 &pcfg_pull_none>, +- /* flash_d5 */ +- <1 RK_PC1 2 &pcfg_pull_none>, +- /* flash_d6 */ +- <1 RK_PC2 2 &pcfg_pull_none>, +- /* flash_d7 */ +- <1 RK_PC3 2 &pcfg_pull_none>, +- /* flash_dqs */ +- <1 RK_PC5 2 &pcfg_pull_none>, +- /* flash_rdn */ +- <1 RK_PD2 2 &pcfg_pull_none>, +- /* flash_rdy */ +- <1 RK_PD1 2 &pcfg_pull_none>, +- /* flash_volsel */ +- <0 RK_PA7 1 &pcfg_pull_none>, +- /* flash_wpn */ +- <1 RK_PC7 3 &pcfg_pull_none>, +- /* flash_wrn */ +- <1 RK_PC4 2 &pcfg_pull_none>; +- }; +- }; +- +- fspi { +- /omit-if-no-ref/ +- fspi_pins: fspi-pins { +- rockchip,pins = +- /* fspi_clk */ +- <1 RK_PD0 1 &pcfg_pull_none>, +- /* fspi_cs0n */ +- <1 RK_PD3 1 &pcfg_pull_none>, +- /* fspi_d0 */ +- <1 RK_PD1 1 &pcfg_pull_none>, +- /* fspi_d1 */ +- <1 RK_PD2 1 &pcfg_pull_none>, +- /* fspi_d2 */ +- <1 RK_PC7 2 &pcfg_pull_none>, +- /* fspi_d3 */ +- <1 RK_PD4 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- fspi_cs1: fspi-cs1 { +- rockchip,pins = +- /* fspi_cs1n */ +- <1 RK_PC6 2 &pcfg_pull_up>; +- }; +- }; +- +- gmac0 { +- /omit-if-no-ref/ +- gmac0_miim: gmac0-miim { +- rockchip,pins = +- /* gmac0_mdc */ +- <2 RK_PC3 2 &pcfg_pull_none>, +- /* gmac0_mdio */ +- <2 RK_PC4 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac0_clkinout: gmac0-clkinout { +- rockchip,pins = +- /* gmac0_mclkinout */ +- <2 RK_PC2 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac0_rx_er: gmac0-rx-er { +- rockchip,pins = +- /* gmac0_rxer */ +- <2 RK_PC5 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac0_rx_bus2: gmac0-rx-bus2 { +- rockchip,pins = +- /* gmac0_rxd0 */ +- <2 RK_PB6 1 &pcfg_pull_none>, +- /* gmac0_rxd1 */ +- <2 RK_PB7 2 &pcfg_pull_none>, +- /* gmac0_rxdvcrs */ +- <2 RK_PC0 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac0_tx_bus2: gmac0-tx-bus2 { +- rockchip,pins = +- /* gmac0_txd0 */ +- <2 RK_PB3 1 &pcfg_pull_none_drv_level_2>, +- /* gmac0_txd1 */ +- <2 RK_PB4 1 &pcfg_pull_none_drv_level_2>, +- /* gmac0_txen */ +- <2 RK_PB5 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac0_rgmii_clk: gmac0-rgmii-clk { +- rockchip,pins = +- /* gmac0_rxclk */ +- <2 RK_PA5 2 &pcfg_pull_none>, +- /* gmac0_txclk */ +- <2 RK_PB0 2 &pcfg_pull_none_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- gmac0_rgmii_bus: gmac0-rgmii-bus { +- rockchip,pins = +- /* gmac0_rxd2 */ +- <2 RK_PA3 2 &pcfg_pull_none>, +- /* gmac0_rxd3 */ +- <2 RK_PA4 2 &pcfg_pull_none>, +- /* gmac0_txd2 */ +- <2 RK_PA6 2 &pcfg_pull_none_drv_level_2>, +- /* gmac0_txd3 */ +- <2 RK_PA7 2 &pcfg_pull_none_drv_level_2>; +- }; +- }; +- +- gmac1 { +- /omit-if-no-ref/ +- gmac1m0_miim: gmac1m0-miim { +- rockchip,pins = +- /* gmac1_mdcm0 */ +- <3 RK_PC4 3 &pcfg_pull_none>, +- /* gmac1_mdiom0 */ +- <3 RK_PC5 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1m0_clkinout: gmac1m0-clkinout { +- rockchip,pins = +- /* gmac1_mclkinoutm0 */ +- <3 RK_PC0 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1m0_rx_er: gmac1m0-rx-er { +- rockchip,pins = +- /* gmac1_rxerm0 */ +- <3 RK_PB4 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1m0_rx_bus2: gmac1m0-rx-bus2 { +- rockchip,pins = +- /* gmac1_rxd0m0 */ +- <3 RK_PB1 3 &pcfg_pull_none>, +- /* gmac1_rxd1m0 */ +- <3 RK_PB2 3 &pcfg_pull_none>, +- /* gmac1_rxdvcrsm0 */ +- <3 RK_PB3 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1m0_tx_bus2: gmac1m0-tx-bus2 { +- rockchip,pins = +- /* gmac1_txd0m0 */ +- <3 RK_PB5 3 &pcfg_pull_none_drv_level_2>, +- /* gmac1_txd1m0 */ +- <3 RK_PB6 3 &pcfg_pull_none_drv_level_2>, +- /* gmac1_txenm0 */ +- <3 RK_PB7 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1m0_rgmii_clk: gmac1m0-rgmii-clk { +- rockchip,pins = +- /* gmac1_rxclkm0 */ +- <3 RK_PA7 3 &pcfg_pull_none>, +- /* gmac1_txclkm0 */ +- <3 RK_PA6 3 &pcfg_pull_none_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- gmac1m0_rgmii_bus: gmac1m0-rgmii-bus { +- rockchip,pins = +- /* gmac1_rxd2m0 */ +- <3 RK_PA4 3 &pcfg_pull_none>, +- /* gmac1_rxd3m0 */ +- <3 RK_PA5 3 &pcfg_pull_none>, +- /* gmac1_txd2m0 */ +- <3 RK_PA2 3 &pcfg_pull_none_drv_level_2>, +- /* gmac1_txd3m0 */ +- <3 RK_PA3 3 &pcfg_pull_none_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- gmac1m1_miim: gmac1m1-miim { +- rockchip,pins = +- /* gmac1_mdcm1 */ +- <4 RK_PB6 3 &pcfg_pull_none>, +- /* gmac1_mdiom1 */ +- <4 RK_PB7 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1m1_clkinout: gmac1m1-clkinout { +- rockchip,pins = +- /* gmac1_mclkinoutm1 */ +- <4 RK_PC1 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1m1_rx_er: gmac1m1-rx-er { +- rockchip,pins = +- /* gmac1_rxerm1 */ +- <4 RK_PB2 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1m1_rx_bus2: gmac1m1-rx-bus2 { +- rockchip,pins = +- /* gmac1_rxd0m1 */ +- <4 RK_PA7 3 &pcfg_pull_none>, +- /* gmac1_rxd1m1 */ +- <4 RK_PB0 3 &pcfg_pull_none>, +- /* gmac1_rxdvcrsm1 */ +- <4 RK_PB1 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1m1_tx_bus2: gmac1m1-tx-bus2 { +- rockchip,pins = +- /* gmac1_txd0m1 */ +- <4 RK_PA4 3 &pcfg_pull_none_drv_level_2>, +- /* gmac1_txd1m1 */ +- <4 RK_PA5 3 &pcfg_pull_none_drv_level_2>, +- /* gmac1_txenm1 */ +- <4 RK_PA6 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1m1_rgmii_clk: gmac1m1-rgmii-clk { +- rockchip,pins = +- /* gmac1_rxclkm1 */ +- <4 RK_PA3 3 &pcfg_pull_none>, +- /* gmac1_txclkm1 */ +- <4 RK_PA0 3 &pcfg_pull_none_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- gmac1m1_rgmii_bus: gmac1m1-rgmii-bus { +- rockchip,pins = +- /* gmac1_rxd2m1 */ +- <4 RK_PA1 3 &pcfg_pull_none>, +- /* gmac1_rxd3m1 */ +- <4 RK_PA2 3 &pcfg_pull_none>, +- /* gmac1_txd2m1 */ +- <3 RK_PD6 3 &pcfg_pull_none_drv_level_2>, +- /* gmac1_txd3m1 */ +- <3 RK_PD7 3 &pcfg_pull_none_drv_level_2>; +- }; +- }; +- +- gpu { +- /omit-if-no-ref/ +- gpu_pins: gpu-pins { +- rockchip,pins = +- /* gpu_avs */ +- <0 RK_PC0 2 &pcfg_pull_none>, +- /* gpu_pwren */ +- <0 RK_PA6 4 &pcfg_pull_none>; +- }; +- }; +- +- hdmitx { +- /omit-if-no-ref/ +- hdmitxm0_cec: hdmitxm0-cec { +- rockchip,pins = +- /* hdmitxm0_cec */ +- <4 RK_PD1 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmitxm1_cec: hdmitxm1-cec { +- rockchip,pins = +- /* hdmitxm1_cec */ +- <0 RK_PC7 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmitx_scl: hdmitx-scl { +- rockchip,pins = +- /* hdmitx_scl */ +- <4 RK_PC7 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmitx_sda: hdmitx-sda { +- rockchip,pins = +- /* hdmitx_sda */ +- <4 RK_PD0 1 &pcfg_pull_none>; +- }; +- }; +- +- i2c0 { +- /omit-if-no-ref/ +- i2c0_xfer: i2c0-xfer { +- rockchip,pins = +- /* i2c0_scl */ +- <0 RK_PB1 1 &pcfg_pull_none_smt>, +- /* i2c0_sda */ +- <0 RK_PB2 1 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c1 { +- /omit-if-no-ref/ +- i2c1_xfer: i2c1-xfer { +- rockchip,pins = +- /* i2c1_scl */ +- <0 RK_PB3 1 &pcfg_pull_none_smt>, +- /* i2c1_sda */ +- <0 RK_PB4 1 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c2 { +- /omit-if-no-ref/ +- i2c2m0_xfer: i2c2m0-xfer { +- rockchip,pins = +- /* i2c2_sclm0 */ +- <0 RK_PB5 1 &pcfg_pull_none_smt>, +- /* i2c2_sdam0 */ +- <0 RK_PB6 1 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c2m1_xfer: i2c2m1-xfer { +- rockchip,pins = +- /* i2c2_sclm1 */ +- <4 RK_PB5 1 &pcfg_pull_none_smt>, +- /* i2c2_sdam1 */ +- <4 RK_PB4 1 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c3 { +- /omit-if-no-ref/ +- i2c3m0_xfer: i2c3m0-xfer { +- rockchip,pins = +- /* i2c3_sclm0 */ +- <1 RK_PA1 1 &pcfg_pull_none_smt>, +- /* i2c3_sdam0 */ +- <1 RK_PA0 1 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c3m1_xfer: i2c3m1-xfer { +- rockchip,pins = +- /* i2c3_sclm1 */ +- <3 RK_PB5 4 &pcfg_pull_none_smt>, +- /* i2c3_sdam1 */ +- <3 RK_PB6 4 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c4 { +- /omit-if-no-ref/ +- i2c4m0_xfer: i2c4m0-xfer { +- rockchip,pins = +- /* i2c4_sclm0 */ +- <4 RK_PB3 1 &pcfg_pull_none_smt>, +- /* i2c4_sdam0 */ +- <4 RK_PB2 1 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c4m1_xfer: i2c4m1-xfer { +- rockchip,pins = +- /* i2c4_sclm1 */ +- <2 RK_PB2 2 &pcfg_pull_none_smt>, +- /* i2c4_sdam1 */ +- <2 RK_PB1 2 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c5 { +- /omit-if-no-ref/ +- i2c5m0_xfer: i2c5m0-xfer { +- rockchip,pins = +- /* i2c5_sclm0 */ +- <3 RK_PB3 4 &pcfg_pull_none_smt>, +- /* i2c5_sdam0 */ +- <3 RK_PB4 4 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c5m1_xfer: i2c5m1-xfer { +- rockchip,pins = +- /* i2c5_sclm1 */ +- <4 RK_PC7 2 &pcfg_pull_none_smt>, +- /* i2c5_sdam1 */ +- <4 RK_PD0 2 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2s1 { +- /omit-if-no-ref/ +- i2s1m0_lrckrx: i2s1m0-lrckrx { +- rockchip,pins = +- /* i2s1m0_lrckrx */ +- <1 RK_PA6 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_lrcktx: i2s1m0-lrcktx { +- rockchip,pins = +- /* i2s1m0_lrcktx */ +- <1 RK_PA5 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_mclk: i2s1m0-mclk { +- rockchip,pins = +- /* i2s1m0_mclk */ +- <1 RK_PA2 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_sclkrx: i2s1m0-sclkrx { +- rockchip,pins = +- /* i2s1m0_sclkrx */ +- <1 RK_PA4 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_sclktx: i2s1m0-sclktx { +- rockchip,pins = +- /* i2s1m0_sclktx */ +- <1 RK_PA3 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_sdi0: i2s1m0-sdi0 { +- rockchip,pins = +- /* i2s1m0_sdi0 */ +- <1 RK_PB3 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_sdi1: i2s1m0-sdi1 { +- rockchip,pins = +- /* i2s1m0_sdi1 */ +- <1 RK_PB2 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_sdi2: i2s1m0-sdi2 { +- rockchip,pins = +- /* i2s1m0_sdi2 */ +- <1 RK_PB1 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_sdi3: i2s1m0-sdi3 { +- rockchip,pins = +- /* i2s1m0_sdi3 */ +- <1 RK_PB0 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_sdo0: i2s1m0-sdo0 { +- rockchip,pins = +- /* i2s1m0_sdo0 */ +- <1 RK_PA7 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_sdo1: i2s1m0-sdo1 { +- rockchip,pins = +- /* i2s1m0_sdo1 */ +- <1 RK_PB0 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_sdo2: i2s1m0-sdo2 { +- rockchip,pins = +- /* i2s1m0_sdo2 */ +- <1 RK_PB1 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_sdo3: i2s1m0-sdo3 { +- rockchip,pins = +- /* i2s1m0_sdo3 */ +- <1 RK_PB2 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_lrckrx: i2s1m1-lrckrx { +- rockchip,pins = +- /* i2s1m1_lrckrx */ +- <4 RK_PA7 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_lrcktx: i2s1m1-lrcktx { +- rockchip,pins = +- /* i2s1m1_lrcktx */ +- <3 RK_PD0 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_mclk: i2s1m1-mclk { +- rockchip,pins = +- /* i2s1m1_mclk */ +- <3 RK_PC6 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_sclkrx: i2s1m1-sclkrx { +- rockchip,pins = +- /* i2s1m1_sclkrx */ +- <4 RK_PA6 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_sclktx: i2s1m1-sclktx { +- rockchip,pins = +- /* i2s1m1_sclktx */ +- <3 RK_PC7 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_sdi0: i2s1m1-sdi0 { +- rockchip,pins = +- /* i2s1m1_sdi0 */ +- <3 RK_PD2 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_sdi1: i2s1m1-sdi1 { +- rockchip,pins = +- /* i2s1m1_sdi1 */ +- <3 RK_PD3 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_sdi2: i2s1m1-sdi2 { +- rockchip,pins = +- /* i2s1m1_sdi2 */ +- <3 RK_PD4 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_sdi3: i2s1m1-sdi3 { +- rockchip,pins = +- /* i2s1m1_sdi3 */ +- <3 RK_PD5 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_sdo0: i2s1m1-sdo0 { +- rockchip,pins = +- /* i2s1m1_sdo0 */ +- <3 RK_PD1 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_sdo1: i2s1m1-sdo1 { +- rockchip,pins = +- /* i2s1m1_sdo1 */ +- <4 RK_PB0 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_sdo2: i2s1m1-sdo2 { +- rockchip,pins = +- /* i2s1m1_sdo2 */ +- <4 RK_PB1 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_sdo3: i2s1m1-sdo3 { +- rockchip,pins = +- /* i2s1m1_sdo3 */ +- <4 RK_PB5 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m2_lrckrx: i2s1m2-lrckrx { +- rockchip,pins = +- /* i2s1m2_lrckrx */ +- <3 RK_PC5 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m2_lrcktx: i2s1m2-lrcktx { +- rockchip,pins = +- /* i2s1m2_lrcktx */ +- <2 RK_PD2 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m2_mclk: i2s1m2-mclk { +- rockchip,pins = +- /* i2s1m2_mclk */ +- <2 RK_PD0 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m2_sclkrx: i2s1m2-sclkrx { +- rockchip,pins = +- /* i2s1m2_sclkrx */ +- <3 RK_PC3 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m2_sclktx: i2s1m2-sclktx { +- rockchip,pins = +- /* i2s1m2_sclktx */ +- <2 RK_PD1 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m2_sdi0: i2s1m2-sdi0 { +- rockchip,pins = +- /* i2s1m2_sdi0 */ +- <2 RK_PD3 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m2_sdi1: i2s1m2-sdi1 { +- rockchip,pins = +- /* i2s1m2_sdi1 */ +- <2 RK_PD4 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m2_sdi2: i2s1m2-sdi2 { +- rockchip,pins = +- /* i2s1m2_sdi2 */ +- <2 RK_PD5 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m2_sdi3: i2s1m2-sdi3 { +- rockchip,pins = +- /* i2s1m2_sdi3 */ +- <2 RK_PD6 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m2_sdo0: i2s1m2-sdo0 { +- rockchip,pins = +- /* i2s1m2_sdo0 */ +- <2 RK_PD7 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m2_sdo1: i2s1m2-sdo1 { +- rockchip,pins = +- /* i2s1m2_sdo1 */ +- <3 RK_PA0 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m2_sdo2: i2s1m2-sdo2 { +- rockchip,pins = +- /* i2s1m2_sdo2 */ +- <3 RK_PC1 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m2_sdo3: i2s1m2-sdo3 { +- rockchip,pins = +- /* i2s1m2_sdo3 */ +- <3 RK_PC2 5 &pcfg_pull_none>; +- }; +- }; +- +- i2s2 { +- /omit-if-no-ref/ +- i2s2m0_lrckrx: i2s2m0-lrckrx { +- rockchip,pins = +- /* i2s2m0_lrckrx */ +- <2 RK_PC0 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m0_lrcktx: i2s2m0-lrcktx { +- rockchip,pins = +- /* i2s2m0_lrcktx */ +- <2 RK_PC3 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m0_mclk: i2s2m0-mclk { +- rockchip,pins = +- /* i2s2m0_mclk */ +- <2 RK_PC1 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m0_sclkrx: i2s2m0-sclkrx { +- rockchip,pins = +- /* i2s2m0_sclkrx */ +- <2 RK_PB7 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m0_sclktx: i2s2m0-sclktx { +- rockchip,pins = +- /* i2s2m0_sclktx */ +- <2 RK_PC2 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m0_sdi: i2s2m0-sdi { +- rockchip,pins = +- /* i2s2m0_sdi */ +- <2 RK_PC5 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m0_sdo: i2s2m0-sdo { +- rockchip,pins = +- /* i2s2m0_sdo */ +- <2 RK_PC4 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m1_lrckrx: i2s2m1-lrckrx { +- rockchip,pins = +- /* i2s2m1_lrckrx */ +- <4 RK_PA5 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m1_lrcktx: i2s2m1-lrcktx { +- rockchip,pins = +- /* i2s2m1_lrcktx */ +- <4 RK_PA4 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m1_mclk: i2s2m1-mclk { +- rockchip,pins = +- /* i2s2m1_mclk */ +- <4 RK_PB6 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m1_sclkrx: i2s2m1-sclkrx { +- rockchip,pins = +- /* i2s2m1_sclkrx */ +- <4 RK_PC1 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m1_sclktx: i2s2m1-sclktx { +- rockchip,pins = +- /* i2s2m1_sclktx */ +- <4 RK_PB7 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m1_sdi: i2s2m1-sdi { +- rockchip,pins = +- /* i2s2m1_sdi */ +- <4 RK_PB2 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m1_sdo: i2s2m1-sdo { +- rockchip,pins = +- /* i2s2m1_sdo */ +- <4 RK_PB3 5 &pcfg_pull_none>; +- }; +- }; +- +- i2s3 { +- /omit-if-no-ref/ +- i2s3m0_lrck: i2s3m0-lrck { +- rockchip,pins = +- /* i2s3m0_lrck */ +- <3 RK_PA4 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s3m0_mclk: i2s3m0-mclk { +- rockchip,pins = +- /* i2s3m0_mclk */ +- <3 RK_PA2 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s3m0_sclk: i2s3m0-sclk { +- rockchip,pins = +- /* i2s3m0_sclk */ +- <3 RK_PA3 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s3m0_sdi: i2s3m0-sdi { +- rockchip,pins = +- /* i2s3m0_sdi */ +- <3 RK_PA6 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s3m0_sdo: i2s3m0-sdo { +- rockchip,pins = +- /* i2s3m0_sdo */ +- <3 RK_PA5 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s3m1_lrck: i2s3m1-lrck { +- rockchip,pins = +- /* i2s3m1_lrck */ +- <4 RK_PC4 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s3m1_mclk: i2s3m1-mclk { +- rockchip,pins = +- /* i2s3m1_mclk */ +- <4 RK_PC2 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s3m1_sclk: i2s3m1-sclk { +- rockchip,pins = +- /* i2s3m1_sclk */ +- <4 RK_PC3 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s3m1_sdi: i2s3m1-sdi { +- rockchip,pins = +- /* i2s3m1_sdi */ +- <4 RK_PC6 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s3m1_sdo: i2s3m1-sdo { +- rockchip,pins = +- /* i2s3m1_sdo */ +- <4 RK_PC5 5 &pcfg_pull_none>; +- }; +- }; +- +- isp { +- /omit-if-no-ref/ +- isp_pins: isp-pins { +- rockchip,pins = +- /* isp_flashtrigin */ +- <4 RK_PB4 4 &pcfg_pull_none>, +- /* isp_flashtrigout */ +- <4 RK_PA6 1 &pcfg_pull_none>, +- /* isp_prelighttrig */ +- <4 RK_PB1 1 &pcfg_pull_none>; +- }; +- }; +- +- jtag { +- /omit-if-no-ref/ +- jtag_pins: jtag-pins { +- rockchip,pins = +- /* jtag_tck */ +- <1 RK_PD7 2 &pcfg_pull_none>, +- /* jtag_tms */ +- <2 RK_PA0 2 &pcfg_pull_none>; +- }; +- }; +- +- lcdc { +- /omit-if-no-ref/ +- lcdc_ctl: lcdc-ctl { +- rockchip,pins = +- /* lcdc_clk */ +- <3 RK_PA0 1 &pcfg_pull_none>, +- /* lcdc_d0 */ +- <2 RK_PD0 1 &pcfg_pull_none>, +- /* lcdc_d1 */ +- <2 RK_PD1 1 &pcfg_pull_none>, +- /* lcdc_d2 */ +- <2 RK_PD2 1 &pcfg_pull_none>, +- /* lcdc_d3 */ +- <2 RK_PD3 1 &pcfg_pull_none>, +- /* lcdc_d4 */ +- <2 RK_PD4 1 &pcfg_pull_none>, +- /* lcdc_d5 */ +- <2 RK_PD5 1 &pcfg_pull_none>, +- /* lcdc_d6 */ +- <2 RK_PD6 1 &pcfg_pull_none>, +- /* lcdc_d7 */ +- <2 RK_PD7 1 &pcfg_pull_none>, +- /* lcdc_d8 */ +- <3 RK_PA1 1 &pcfg_pull_none>, +- /* lcdc_d9 */ +- <3 RK_PA2 1 &pcfg_pull_none>, +- /* lcdc_d10 */ +- <3 RK_PA3 1 &pcfg_pull_none>, +- /* lcdc_d11 */ +- <3 RK_PA4 1 &pcfg_pull_none>, +- /* lcdc_d12 */ +- <3 RK_PA5 1 &pcfg_pull_none>, +- /* lcdc_d13 */ +- <3 RK_PA6 1 &pcfg_pull_none>, +- /* lcdc_d14 */ +- <3 RK_PA7 1 &pcfg_pull_none>, +- /* lcdc_d15 */ +- <3 RK_PB0 1 &pcfg_pull_none>, +- /* lcdc_d16 */ +- <3 RK_PB1 1 &pcfg_pull_none>, +- /* lcdc_d17 */ +- <3 RK_PB2 1 &pcfg_pull_none>, +- /* lcdc_d18 */ +- <3 RK_PB3 1 &pcfg_pull_none>, +- /* lcdc_d19 */ +- <3 RK_PB4 1 &pcfg_pull_none>, +- /* lcdc_d20 */ +- <3 RK_PB5 1 &pcfg_pull_none>, +- /* lcdc_d21 */ +- <3 RK_PB6 1 &pcfg_pull_none>, +- /* lcdc_d22 */ +- <3 RK_PB7 1 &pcfg_pull_none>, +- /* lcdc_d23 */ +- <3 RK_PC0 1 &pcfg_pull_none>, +- /* lcdc_den */ +- <3 RK_PC3 1 &pcfg_pull_none>, +- /* lcdc_hsync */ +- <3 RK_PC1 1 &pcfg_pull_none>, +- /* lcdc_vsync */ +- <3 RK_PC2 1 &pcfg_pull_none>; +- }; +- }; +- +- mcu { +- /omit-if-no-ref/ +- mcu_pins: mcu-pins { +- rockchip,pins = +- /* mcu_jtagtck */ +- <0 RK_PB4 4 &pcfg_pull_none>, +- /* mcu_jtagtdi */ +- <0 RK_PC1 4 &pcfg_pull_none>, +- /* mcu_jtagtdo */ +- <0 RK_PB3 4 &pcfg_pull_none>, +- /* mcu_jtagtms */ +- <0 RK_PC2 4 &pcfg_pull_none>, +- /* mcu_jtagtrstn */ +- <0 RK_PC3 4 &pcfg_pull_none>; +- }; +- }; +- +- npu { +- /omit-if-no-ref/ +- npu_pins: npu-pins { +- rockchip,pins = +- /* npu_avs */ +- <0 RK_PC1 2 &pcfg_pull_none>; +- }; +- }; +- +- pcie20 { +- /omit-if-no-ref/ +- pcie20m0_pins: pcie20m0-pins { +- rockchip,pins = +- /* pcie20_clkreqnm0 */ +- <0 RK_PA5 3 &pcfg_pull_none>, +- /* pcie20_perstnm0 */ +- <0 RK_PB6 3 &pcfg_pull_none>, +- /* pcie20_wakenm0 */ +- <0 RK_PB5 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie20m1_pins: pcie20m1-pins { +- rockchip,pins = +- /* pcie20_clkreqnm1 */ +- <2 RK_PD0 4 &pcfg_pull_none>, +- /* pcie20_perstnm1 */ +- <3 RK_PC1 4 &pcfg_pull_none>, +- /* pcie20_wakenm1 */ +- <2 RK_PD1 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie20m2_pins: pcie20m2-pins { +- rockchip,pins = +- /* pcie20_clkreqnm2 */ +- <1 RK_PB0 4 &pcfg_pull_none>, +- /* pcie20_perstnm2 */ +- <1 RK_PB2 4 &pcfg_pull_none>, +- /* pcie20_wakenm2 */ +- <1 RK_PB1 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie20_buttonrstn: pcie20-buttonrstn { +- rockchip,pins = +- /* pcie20_buttonrstn */ +- <0 RK_PB4 3 &pcfg_pull_none>; +- }; +- }; +- +- pcie30x1 { +- /omit-if-no-ref/ +- pcie30x1m0_pins: pcie30x1m0-pins { +- rockchip,pins = +- /* pcie30x1_clkreqnm0 */ +- <0 RK_PA4 3 &pcfg_pull_none>, +- /* pcie30x1_perstnm0 */ +- <0 RK_PC3 3 &pcfg_pull_none>, +- /* pcie30x1_wakenm0 */ +- <0 RK_PC2 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie30x1m1_pins: pcie30x1m1-pins { +- rockchip,pins = +- /* pcie30x1_clkreqnm1 */ +- <2 RK_PD2 4 &pcfg_pull_none>, +- /* pcie30x1_perstnm1 */ +- <3 RK_PA1 4 &pcfg_pull_none>, +- /* pcie30x1_wakenm1 */ +- <2 RK_PD3 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie30x1m2_pins: pcie30x1m2-pins { +- rockchip,pins = +- /* pcie30x1_clkreqnm2 */ +- <1 RK_PA5 4 &pcfg_pull_none>, +- /* pcie30x1_perstnm2 */ +- <1 RK_PA2 4 &pcfg_pull_none>, +- /* pcie30x1_wakenm2 */ +- <1 RK_PA3 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie30x1_buttonrstn: pcie30x1-buttonrstn { +- rockchip,pins = +- /* pcie30x1_buttonrstn */ +- <0 RK_PB3 3 &pcfg_pull_none>; +- }; +- }; +- +- pcie30x2 { +- /omit-if-no-ref/ +- pcie30x2m0_pins: pcie30x2m0-pins { +- rockchip,pins = +- /* pcie30x2_clkreqnm0 */ +- <0 RK_PA6 2 &pcfg_pull_none>, +- /* pcie30x2_perstnm0 */ +- <0 RK_PC6 3 &pcfg_pull_none>, +- /* pcie30x2_wakenm0 */ +- <0 RK_PC5 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie30x2m1_pins: pcie30x2m1-pins { +- rockchip,pins = +- /* pcie30x2_clkreqnm1 */ +- <2 RK_PD4 4 &pcfg_pull_none>, +- /* pcie30x2_perstnm1 */ +- <2 RK_PD6 4 &pcfg_pull_none>, +- /* pcie30x2_wakenm1 */ +- <2 RK_PD5 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie30x2m2_pins: pcie30x2m2-pins { +- rockchip,pins = +- /* pcie30x2_clkreqnm2 */ +- <4 RK_PC2 4 &pcfg_pull_none>, +- /* pcie30x2_perstnm2 */ +- <4 RK_PC4 4 &pcfg_pull_none>, +- /* pcie30x2_wakenm2 */ +- <4 RK_PC3 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie30x2_buttonrstn: pcie30x2-buttonrstn { +- rockchip,pins = +- /* pcie30x2_buttonrstn */ +- <0 RK_PB0 3 &pcfg_pull_none>; +- }; +- }; +- +- pdm { +- /omit-if-no-ref/ +- pdmm0_clk: pdmm0-clk { +- rockchip,pins = +- /* pdm_clk0m0 */ +- <1 RK_PA6 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdmm0_clk1: pdmm0-clk1 { +- rockchip,pins = +- /* pdmm0_clk1 */ +- <1 RK_PA4 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdmm0_sdi0: pdmm0-sdi0 { +- rockchip,pins = +- /* pdmm0_sdi0 */ +- <1 RK_PB3 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdmm0_sdi1: pdmm0-sdi1 { +- rockchip,pins = +- /* pdmm0_sdi1 */ +- <1 RK_PB2 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdmm0_sdi2: pdmm0-sdi2 { +- rockchip,pins = +- /* pdmm0_sdi2 */ +- <1 RK_PB1 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdmm0_sdi3: pdmm0-sdi3 { +- rockchip,pins = +- /* pdmm0_sdi3 */ +- <1 RK_PB0 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdmm1_clk: pdmm1-clk { +- rockchip,pins = +- /* pdm_clk0m1 */ +- <3 RK_PD6 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdmm1_clk1: pdmm1-clk1 { +- rockchip,pins = +- /* pdmm1_clk1 */ +- <4 RK_PA0 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdmm1_sdi0: pdmm1-sdi0 { +- rockchip,pins = +- /* pdmm1_sdi0 */ +- <3 RK_PD7 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdmm1_sdi1: pdmm1-sdi1 { +- rockchip,pins = +- /* pdmm1_sdi1 */ +- <4 RK_PA1 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdmm1_sdi2: pdmm1-sdi2 { +- rockchip,pins = +- /* pdmm1_sdi2 */ +- <4 RK_PA2 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdmm1_sdi3: pdmm1-sdi3 { +- rockchip,pins = +- /* pdmm1_sdi3 */ +- <4 RK_PA3 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdmm2_clk1: pdmm2-clk1 { +- rockchip,pins = +- /* pdmm2_clk1 */ +- <3 RK_PC4 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdmm2_sdi0: pdmm2-sdi0 { +- rockchip,pins = +- /* pdmm2_sdi0 */ +- <3 RK_PB3 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdmm2_sdi1: pdmm2-sdi1 { +- rockchip,pins = +- /* pdmm2_sdi1 */ +- <3 RK_PB4 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdmm2_sdi2: pdmm2-sdi2 { +- rockchip,pins = +- /* pdmm2_sdi2 */ +- <3 RK_PB7 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdmm2_sdi3: pdmm2-sdi3 { +- rockchip,pins = +- /* pdmm2_sdi3 */ +- <3 RK_PC0 5 &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- /omit-if-no-ref/ +- pmic_pins: pmic-pins { +- rockchip,pins = +- /* pmic_sleep */ +- <0 RK_PA2 1 &pcfg_pull_none>; +- }; +- }; +- +- pmu { +- /omit-if-no-ref/ +- pmu_pins: pmu-pins { +- rockchip,pins = +- /* pmu_debug0 */ +- <0 RK_PA5 4 &pcfg_pull_none>, +- /* pmu_debug1 */ +- <0 RK_PA6 3 &pcfg_pull_none>, +- /* pmu_debug2 */ +- <0 RK_PC4 4 &pcfg_pull_none>, +- /* pmu_debug3 */ +- <0 RK_PC5 4 &pcfg_pull_none>, +- /* pmu_debug4 */ +- <0 RK_PC6 4 &pcfg_pull_none>, +- /* pmu_debug5 */ +- <0 RK_PC7 4 &pcfg_pull_none>; +- }; +- }; +- +- pwm0 { +- /omit-if-no-ref/ +- pwm0m0_pins: pwm0m0-pins { +- rockchip,pins = +- /* pwm0_m0 */ +- <0 RK_PB7 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm0m1_pins: pwm0m1-pins { +- rockchip,pins = +- /* pwm0_m1 */ +- <0 RK_PC7 2 &pcfg_pull_none>; +- }; +- }; +- +- pwm1 { +- /omit-if-no-ref/ +- pwm1m0_pins: pwm1m0-pins { +- rockchip,pins = +- /* pwm1_m0 */ +- <0 RK_PC0 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm1m1_pins: pwm1m1-pins { +- rockchip,pins = +- /* pwm1_m1 */ +- <0 RK_PB5 4 &pcfg_pull_none>; +- }; +- }; +- +- pwm2 { +- /omit-if-no-ref/ +- pwm2m0_pins: pwm2m0-pins { +- rockchip,pins = +- /* pwm2_m0 */ +- <0 RK_PC1 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm2m1_pins: pwm2m1-pins { +- rockchip,pins = +- /* pwm2_m1 */ +- <0 RK_PB6 4 &pcfg_pull_none>; +- }; +- }; +- +- pwm3 { +- /omit-if-no-ref/ +- pwm3_pins: pwm3-pins { +- rockchip,pins = +- /* pwm3_ir */ +- <0 RK_PC2 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm4 { +- /omit-if-no-ref/ +- pwm4_pins: pwm4-pins { +- rockchip,pins = +- /* pwm4 */ +- <0 RK_PC3 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm5 { +- /omit-if-no-ref/ +- pwm5_pins: pwm5-pins { +- rockchip,pins = +- /* pwm5 */ +- <0 RK_PC4 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm6 { +- /omit-if-no-ref/ +- pwm6_pins: pwm6-pins { +- rockchip,pins = +- /* pwm6 */ +- <0 RK_PC5 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm7 { +- /omit-if-no-ref/ +- pwm7_pins: pwm7-pins { +- rockchip,pins = +- /* pwm7_ir */ +- <0 RK_PC6 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm8 { +- /omit-if-no-ref/ +- pwm8m0_pins: pwm8m0-pins { +- rockchip,pins = +- /* pwm8_m0 */ +- <3 RK_PB1 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm8m1_pins: pwm8m1-pins { +- rockchip,pins = +- /* pwm8_m1 */ +- <1 RK_PD5 4 &pcfg_pull_none>; +- }; +- }; +- +- pwm9 { +- /omit-if-no-ref/ +- pwm9m0_pins: pwm9m0-pins { +- rockchip,pins = +- /* pwm9_m0 */ +- <3 RK_PB2 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm9m1_pins: pwm9m1-pins { +- rockchip,pins = +- /* pwm9_m1 */ +- <1 RK_PD6 4 &pcfg_pull_none>; +- }; +- }; +- +- pwm10 { +- /omit-if-no-ref/ +- pwm10m0_pins: pwm10m0-pins { +- rockchip,pins = +- /* pwm10_m0 */ +- <3 RK_PB5 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm10m1_pins: pwm10m1-pins { +- rockchip,pins = +- /* pwm10_m1 */ +- <2 RK_PA1 2 &pcfg_pull_none>; +- }; +- }; +- +- pwm11 { +- /omit-if-no-ref/ +- pwm11m0_pins: pwm11m0-pins { +- rockchip,pins = +- /* pwm11_irm0 */ +- <3 RK_PB6 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm11m1_pins: pwm11m1-pins { +- rockchip,pins = +- /* pwm11_irm1 */ +- <4 RK_PC0 3 &pcfg_pull_none>; +- }; +- }; +- +- pwm12 { +- /omit-if-no-ref/ +- pwm12m0_pins: pwm12m0-pins { +- rockchip,pins = +- /* pwm12_m0 */ +- <3 RK_PB7 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm12m1_pins: pwm12m1-pins { +- rockchip,pins = +- /* pwm12_m1 */ +- <4 RK_PC5 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm13 { +- /omit-if-no-ref/ +- pwm13m0_pins: pwm13m0-pins { +- rockchip,pins = +- /* pwm13_m0 */ +- <3 RK_PC0 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm13m1_pins: pwm13m1-pins { +- rockchip,pins = +- /* pwm13_m1 */ +- <4 RK_PC6 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm14 { +- /omit-if-no-ref/ +- pwm14m0_pins: pwm14m0-pins { +- rockchip,pins = +- /* pwm14_m0 */ +- <3 RK_PC4 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm14m1_pins: pwm14m1-pins { +- rockchip,pins = +- /* pwm14_m1 */ +- <4 RK_PC2 1 &pcfg_pull_none>; +- }; +- }; +- +- pwm15 { +- /omit-if-no-ref/ +- pwm15m0_pins: pwm15m0-pins { +- rockchip,pins = +- /* pwm15_irm0 */ +- <3 RK_PC5 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm15m1_pins: pwm15m1-pins { +- rockchip,pins = +- /* pwm15_irm1 */ +- <4 RK_PC3 1 &pcfg_pull_none>; +- }; +- }; +- +- refclk { +- /omit-if-no-ref/ +- refclk_pins: refclk-pins { +- rockchip,pins = +- /* refclk_ou */ +- <0 RK_PA0 1 &pcfg_pull_none>; +- }; +- }; +- +- sata { +- /omit-if-no-ref/ +- sata_pins: sata-pins { +- rockchip,pins = +- /* sata_cpdet */ +- <0 RK_PA4 2 &pcfg_pull_none>, +- /* sata_cppod */ +- <0 RK_PA6 1 &pcfg_pull_none>, +- /* sata_mpswitch */ +- <0 RK_PA5 2 &pcfg_pull_none>; +- }; +- }; +- +- sata0 { +- /omit-if-no-ref/ +- sata0_pins: sata0-pins { +- rockchip,pins = +- /* sata0_actled */ +- <4 RK_PC6 3 &pcfg_pull_none>; +- }; +- }; +- +- sata1 { +- /omit-if-no-ref/ +- sata1_pins: sata1-pins { +- rockchip,pins = +- /* sata1_actled */ +- <4 RK_PC5 3 &pcfg_pull_none>; +- }; +- }; +- +- sata2 { +- /omit-if-no-ref/ +- sata2_pins: sata2-pins { +- rockchip,pins = +- /* sata2_actled */ +- <4 RK_PC4 3 &pcfg_pull_none>; +- }; +- }; +- +- scr { +- /omit-if-no-ref/ +- scr_pins: scr-pins { +- rockchip,pins = +- /* scr_clk */ +- <1 RK_PA2 3 &pcfg_pull_none>, +- /* scr_det */ +- <1 RK_PA7 3 &pcfg_pull_up>, +- /* scr_io */ +- <1 RK_PA3 3 &pcfg_pull_up>, +- /* scr_rst */ +- <1 RK_PA5 3 &pcfg_pull_none>; +- }; +- }; +- +- sdmmc0 { +- /omit-if-no-ref/ +- sdmmc0_bus4: sdmmc0-bus4 { +- rockchip,pins = +- /* sdmmc0_d0 */ +- <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>, +- /* sdmmc0_d1 */ +- <1 RK_PD6 1 &pcfg_pull_up_drv_level_2>, +- /* sdmmc0_d2 */ +- <1 RK_PD7 1 &pcfg_pull_up_drv_level_2>, +- /* sdmmc0_d3 */ +- <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- sdmmc0_clk: sdmmc0-clk { +- rockchip,pins = +- /* sdmmc0_clk */ +- <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- sdmmc0_cmd: sdmmc0-cmd { +- rockchip,pins = +- /* sdmmc0_cmd */ +- <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- sdmmc0_det: sdmmc0-det { +- rockchip,pins = +- /* sdmmc0_det */ +- <0 RK_PA4 1 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- sdmmc0_pwren: sdmmc0-pwren { +- rockchip,pins = +- /* sdmmc0_pwren */ +- <0 RK_PA5 1 &pcfg_pull_none>; +- }; +- }; +- +- sdmmc1 { +- /omit-if-no-ref/ +- sdmmc1_bus4: sdmmc1-bus4 { +- rockchip,pins = +- /* sdmmc1_d0 */ +- <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>, +- /* sdmmc1_d1 */ +- <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>, +- /* sdmmc1_d2 */ +- <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>, +- /* sdmmc1_d3 */ +- <2 RK_PA6 1 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- sdmmc1_clk: sdmmc1-clk { +- rockchip,pins = +- /* sdmmc1_clk */ +- <2 RK_PB0 1 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- sdmmc1_cmd: sdmmc1-cmd { +- rockchip,pins = +- /* sdmmc1_cmd */ +- <2 RK_PA7 1 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- sdmmc1_det: sdmmc1-det { +- rockchip,pins = +- /* sdmmc1_det */ +- <2 RK_PB2 1 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- sdmmc1_pwren: sdmmc1-pwren { +- rockchip,pins = +- /* sdmmc1_pwren */ +- <2 RK_PB1 1 &pcfg_pull_none>; +- }; +- }; +- +- sdmmc2 { +- /omit-if-no-ref/ +- sdmmc2m0_bus4: sdmmc2m0-bus4 { +- rockchip,pins = +- /* sdmmc2_d0m0 */ +- <3 RK_PC6 3 &pcfg_pull_up_drv_level_2>, +- /* sdmmc2_d1m0 */ +- <3 RK_PC7 3 &pcfg_pull_up_drv_level_2>, +- /* sdmmc2_d2m0 */ +- <3 RK_PD0 3 &pcfg_pull_up_drv_level_2>, +- /* sdmmc2_d3m0 */ +- <3 RK_PD1 3 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- sdmmc2m0_clk: sdmmc2m0-clk { +- rockchip,pins = +- /* sdmmc2_clkm0 */ +- <3 RK_PD3 3 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- sdmmc2m0_cmd: sdmmc2m0-cmd { +- rockchip,pins = +- /* sdmmc2_cmdm0 */ +- <3 RK_PD2 3 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- sdmmc2m0_det: sdmmc2m0-det { +- rockchip,pins = +- /* sdmmc2_detm0 */ +- <3 RK_PD4 3 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- sdmmc2m0_pwren: sdmmc2m0-pwren { +- rockchip,pins = +- /* sdmmc2m0_pwren */ +- <3 RK_PD5 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- sdmmc2m1_bus4: sdmmc2m1-bus4 { +- rockchip,pins = +- /* sdmmc2_d0m1 */ +- <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, +- /* sdmmc2_d1m1 */ +- <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, +- /* sdmmc2_d2m1 */ +- <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>, +- /* sdmmc2_d3m1 */ +- <3 RK_PA4 5 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- sdmmc2m1_clk: sdmmc2m1-clk { +- rockchip,pins = +- /* sdmmc2_clkm1 */ +- <3 RK_PA6 5 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- sdmmc2m1_cmd: sdmmc2m1-cmd { +- rockchip,pins = +- /* sdmmc2_cmdm1 */ +- <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- sdmmc2m1_det: sdmmc2m1-det { +- rockchip,pins = +- /* sdmmc2_detm1 */ +- <3 RK_PA7 4 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- sdmmc2m1_pwren: sdmmc2m1-pwren { +- rockchip,pins = +- /* sdmmc2m1_pwren */ +- <3 RK_PB0 4 &pcfg_pull_none>; +- }; +- }; +- +- spdif { +- /omit-if-no-ref/ +- spdifm0_tx: spdifm0-tx { +- rockchip,pins = +- /* spdifm0_tx */ +- <1 RK_PA4 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spdifm1_tx: spdifm1-tx { +- rockchip,pins = +- /* spdifm1_tx */ +- <3 RK_PC5 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spdifm2_tx: spdifm2-tx { +- rockchip,pins = +- /* spdifm2_tx */ +- <4 RK_PC4 2 &pcfg_pull_none>; +- }; +- }; +- +- spi0 { +- /omit-if-no-ref/ +- spi0m0_pins: spi0m0-pins { +- rockchip,pins = +- /* spi0_clkm0 */ +- <0 RK_PB5 2 &pcfg_pull_none>, +- /* spi0_misom0 */ +- <0 RK_PC5 2 &pcfg_pull_none>, +- /* spi0_mosim0 */ +- <0 RK_PB6 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spi0m0_cs0: spi0m0-cs0 { +- rockchip,pins = +- /* spi0_cs0m0 */ +- <0 RK_PC6 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spi0m0_cs1: spi0m0-cs1 { +- rockchip,pins = +- /* spi0_cs1m0 */ +- <0 RK_PC4 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spi0m1_pins: spi0m1-pins { +- rockchip,pins = +- /* spi0_clkm1 */ +- <2 RK_PD3 3 &pcfg_pull_none>, +- /* spi0_misom1 */ +- <2 RK_PD0 3 &pcfg_pull_none>, +- /* spi0_mosim1 */ +- <2 RK_PD1 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spi0m1_cs0: spi0m1-cs0 { +- rockchip,pins = +- /* spi0_cs0m1 */ +- <2 RK_PD2 3 &pcfg_pull_none>; +- }; +- }; +- +- spi1 { +- /omit-if-no-ref/ +- spi1m0_pins: spi1m0-pins { +- rockchip,pins = +- /* spi1_clkm0 */ +- <2 RK_PB5 3 &pcfg_pull_none>, +- /* spi1_misom0 */ +- <2 RK_PB6 3 &pcfg_pull_none>, +- /* spi1_mosim0 */ +- <2 RK_PB7 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spi1m0_cs0: spi1m0-cs0 { +- rockchip,pins = +- /* spi1_cs0m0 */ +- <2 RK_PC0 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spi1m0_cs1: spi1m0-cs1 { +- rockchip,pins = +- /* spi1_cs1m0 */ +- <2 RK_PC6 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spi1m1_pins: spi1m1-pins { +- rockchip,pins = +- /* spi1_clkm1 */ +- <3 RK_PC3 3 &pcfg_pull_none>, +- /* spi1_misom1 */ +- <3 RK_PC2 3 &pcfg_pull_none>, +- /* spi1_mosim1 */ +- <3 RK_PC1 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spi1m1_cs0: spi1m1-cs0 { +- rockchip,pins = +- /* spi1_cs0m1 */ +- <3 RK_PA1 3 &pcfg_pull_none>; +- }; +- }; +- +- spi2 { +- /omit-if-no-ref/ +- spi2m0_pins: spi2m0-pins { +- rockchip,pins = +- /* spi2_clkm0 */ +- <2 RK_PC1 4 &pcfg_pull_none>, +- /* spi2_misom0 */ +- <2 RK_PC2 4 &pcfg_pull_none>, +- /* spi2_mosim0 */ +- <2 RK_PC3 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spi2m0_cs0: spi2m0-cs0 { +- rockchip,pins = +- /* spi2_cs0m0 */ +- <2 RK_PC4 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spi2m0_cs1: spi2m0-cs1 { +- rockchip,pins = +- /* spi2_cs1m0 */ +- <2 RK_PC5 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spi2m1_pins: spi2m1-pins { +- rockchip,pins = +- /* spi2_clkm1 */ +- <3 RK_PA0 3 &pcfg_pull_none>, +- /* spi2_misom1 */ +- <2 RK_PD7 3 &pcfg_pull_none>, +- /* spi2_mosim1 */ +- <2 RK_PD6 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spi2m1_cs0: spi2m1-cs0 { +- rockchip,pins = +- /* spi2_cs0m1 */ +- <2 RK_PD5 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spi2m1_cs1: spi2m1-cs1 { +- rockchip,pins = +- /* spi2_cs1m1 */ +- <2 RK_PD4 3 &pcfg_pull_none>; +- }; +- }; +- +- spi3 { +- /omit-if-no-ref/ +- spi3m0_pins: spi3m0-pins { +- rockchip,pins = +- /* spi3_clkm0 */ +- <4 RK_PB3 4 &pcfg_pull_none>, +- /* spi3_misom0 */ +- <4 RK_PB0 4 &pcfg_pull_none>, +- /* spi3_mosim0 */ +- <4 RK_PB2 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spi3m0_cs0: spi3m0-cs0 { +- rockchip,pins = +- /* spi3_cs0m0 */ +- <4 RK_PA6 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spi3m0_cs1: spi3m0-cs1 { +- rockchip,pins = +- /* spi3_cs1m0 */ +- <4 RK_PA7 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spi3m1_pins: spi3m1-pins { +- rockchip,pins = +- /* spi3_clkm1 */ +- <4 RK_PC2 2 &pcfg_pull_none>, +- /* spi3_misom1 */ +- <4 RK_PC5 2 &pcfg_pull_none>, +- /* spi3_mosim1 */ +- <4 RK_PC3 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spi3m1_cs0: spi3m1-cs0 { +- rockchip,pins = +- /* spi3_cs0m1 */ +- <4 RK_PC6 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spi3m1_cs1: spi3m1-cs1 { +- rockchip,pins = +- /* spi3_cs1m1 */ +- <4 RK_PD1 2 &pcfg_pull_none>; +- }; +- }; +- +- tsadc { +- /omit-if-no-ref/ +- tsadcm0_shut: tsadcm0-shut { +- rockchip,pins = +- /* tsadcm0_shut */ +- <0 RK_PA1 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- tsadcm1_shut: tsadcm1-shut { +- rockchip,pins = +- /* tsadcm1_shut */ +- <0 RK_PA2 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- tsadc_shutorg: tsadc-shutorg { +- rockchip,pins = +- /* tsadc_shutorg */ +- <0 RK_PA1 2 &pcfg_pull_none>; +- }; +- }; +- +- uart0 { +- /omit-if-no-ref/ +- uart0_xfer: uart0-xfer { +- rockchip,pins = +- /* uart0_rx */ +- <0 RK_PC0 3 &pcfg_pull_up>, +- /* uart0_tx */ +- <0 RK_PC1 3 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart0_ctsn: uart0-ctsn { +- rockchip,pins = +- /* uart0_ctsn */ +- <0 RK_PC7 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart0_rtsn: uart0-rtsn { +- rockchip,pins = +- /* uart0_rtsn */ +- <0 RK_PC4 3 &pcfg_pull_none>; +- }; +- }; +- +- uart1 { +- /omit-if-no-ref/ +- uart1m0_xfer: uart1m0-xfer { +- rockchip,pins = +- /* uart1_rxm0 */ +- <2 RK_PB3 2 &pcfg_pull_up>, +- /* uart1_txm0 */ +- <2 RK_PB4 2 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart1m0_ctsn: uart1m0-ctsn { +- rockchip,pins = +- /* uart1m0_ctsn */ +- <2 RK_PB6 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart1m0_rtsn: uart1m0-rtsn { +- rockchip,pins = +- /* uart1m0_rtsn */ +- <2 RK_PB5 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart1m1_xfer: uart1m1-xfer { +- rockchip,pins = +- /* uart1_rxm1 */ +- <3 RK_PD7 4 &pcfg_pull_up>, +- /* uart1_txm1 */ +- <3 RK_PD6 4 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart1m1_ctsn: uart1m1-ctsn { +- rockchip,pins = +- /* uart1m1_ctsn */ +- <4 RK_PC1 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart1m1_rtsn: uart1m1-rtsn { +- rockchip,pins = +- /* uart1m1_rtsn */ +- <4 RK_PB6 4 &pcfg_pull_none>; +- }; +- }; +- +- uart2 { +- /omit-if-no-ref/ +- uart2m0_xfer: uart2m0-xfer { +- rockchip,pins = +- /* uart2_rxm0 */ +- <0 RK_PD0 1 &pcfg_pull_up>, +- /* uart2_txm0 */ +- <0 RK_PD1 1 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart2m1_xfer: uart2m1-xfer { +- rockchip,pins = +- /* uart2_rxm1 */ +- <1 RK_PD6 2 &pcfg_pull_up>, +- /* uart2_txm1 */ +- <1 RK_PD5 2 &pcfg_pull_up>; +- }; +- }; +- +- uart3 { +- /omit-if-no-ref/ +- uart3m0_xfer: uart3m0-xfer { +- rockchip,pins = +- /* uart3_rxm0 */ +- <1 RK_PA0 2 &pcfg_pull_up>, +- /* uart3_txm0 */ +- <1 RK_PA1 2 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart3m0_ctsn: uart3m0-ctsn { +- rockchip,pins = +- /* uart3m0_ctsn */ +- <1 RK_PA3 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart3m0_rtsn: uart3m0-rtsn { +- rockchip,pins = +- /* uart3m0_rtsn */ +- <1 RK_PA2 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart3m1_xfer: uart3m1-xfer { +- rockchip,pins = +- /* uart3_rxm1 */ +- <3 RK_PC0 4 &pcfg_pull_up>, +- /* uart3_txm1 */ +- <3 RK_PB7 4 &pcfg_pull_up>; +- }; +- }; +- +- uart4 { +- /omit-if-no-ref/ +- uart4m0_xfer: uart4m0-xfer { +- rockchip,pins = +- /* uart4_rxm0 */ +- <1 RK_PA4 2 &pcfg_pull_up>, +- /* uart4_txm0 */ +- <1 RK_PA6 2 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart4m0_ctsn: uart4m0-ctsn { +- rockchip,pins = +- /* uart4m0_ctsn */ +- <1 RK_PA7 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart4m0_rtsn: uart4m0-rtsn { +- rockchip,pins = +- /* uart4m0_rtsn */ +- <1 RK_PA5 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart4m1_xfer: uart4m1-xfer { +- rockchip,pins = +- /* uart4_rxm1 */ +- <3 RK_PB1 4 &pcfg_pull_up>, +- /* uart4_txm1 */ +- <3 RK_PB2 4 &pcfg_pull_up>; +- }; +- }; +- +- uart5 { +- /omit-if-no-ref/ +- uart5m0_xfer: uart5m0-xfer { +- rockchip,pins = +- /* uart5_rxm0 */ +- <2 RK_PA1 3 &pcfg_pull_up>, +- /* uart5_txm0 */ +- <2 RK_PA2 3 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart5m0_ctsn: uart5m0-ctsn { +- rockchip,pins = +- /* uart5m0_ctsn */ +- <1 RK_PD7 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart5m0_rtsn: uart5m0-rtsn { +- rockchip,pins = +- /* uart5m0_rtsn */ +- <2 RK_PA0 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart5m1_xfer: uart5m1-xfer { +- rockchip,pins = +- /* uart5_rxm1 */ +- <3 RK_PC3 4 &pcfg_pull_up>, +- /* uart5_txm1 */ +- <3 RK_PC2 4 &pcfg_pull_up>; +- }; +- }; +- +- uart6 { +- /omit-if-no-ref/ +- uart6m0_xfer: uart6m0-xfer { +- rockchip,pins = +- /* uart6_rxm0 */ +- <2 RK_PA3 3 &pcfg_pull_up>, +- /* uart6_txm0 */ +- <2 RK_PA4 3 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart6m0_ctsn: uart6m0-ctsn { +- rockchip,pins = +- /* uart6m0_ctsn */ +- <2 RK_PC0 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart6m0_rtsn: uart6m0-rtsn { +- rockchip,pins = +- /* uart6m0_rtsn */ +- <2 RK_PB7 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart6m1_xfer: uart6m1-xfer { +- rockchip,pins = +- /* uart6_rxm1 */ +- <1 RK_PD6 3 &pcfg_pull_up>, +- /* uart6_txm1 */ +- <1 RK_PD5 3 &pcfg_pull_up>; +- }; +- }; +- +- uart7 { +- /omit-if-no-ref/ +- uart7m0_xfer: uart7m0-xfer { +- rockchip,pins = +- /* uart7_rxm0 */ +- <2 RK_PA5 3 &pcfg_pull_up>, +- /* uart7_txm0 */ +- <2 RK_PA6 3 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart7m0_ctsn: uart7m0-ctsn { +- rockchip,pins = +- /* uart7m0_ctsn */ +- <2 RK_PC2 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart7m0_rtsn: uart7m0-rtsn { +- rockchip,pins = +- /* uart7m0_rtsn */ +- <2 RK_PC1 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart7m1_xfer: uart7m1-xfer { +- rockchip,pins = +- /* uart7_rxm1 */ +- <3 RK_PC5 4 &pcfg_pull_up>, +- /* uart7_txm1 */ +- <3 RK_PC4 4 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart7m2_xfer: uart7m2-xfer { +- rockchip,pins = +- /* uart7_rxm2 */ +- <4 RK_PA3 4 &pcfg_pull_up>, +- /* uart7_txm2 */ +- <4 RK_PA2 4 &pcfg_pull_up>; +- }; +- }; +- +- uart8 { +- /omit-if-no-ref/ +- uart8m0_xfer: uart8m0-xfer { +- rockchip,pins = +- /* uart8_rxm0 */ +- <2 RK_PC6 2 &pcfg_pull_up>, +- /* uart8_txm0 */ +- <2 RK_PC5 3 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart8m0_ctsn: uart8m0-ctsn { +- rockchip,pins = +- /* uart8m0_ctsn */ +- <2 RK_PB2 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart8m0_rtsn: uart8m0-rtsn { +- rockchip,pins = +- /* uart8m0_rtsn */ +- <2 RK_PB1 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart8m1_xfer: uart8m1-xfer { +- rockchip,pins = +- /* uart8_rxm1 */ +- <3 RK_PA0 4 &pcfg_pull_up>, +- /* uart8_txm1 */ +- <2 RK_PD7 4 &pcfg_pull_up>; +- }; +- }; +- +- uart9 { +- /omit-if-no-ref/ +- uart9m0_xfer: uart9m0-xfer { +- rockchip,pins = +- /* uart9_rxm0 */ +- <2 RK_PA7 3 &pcfg_pull_up>, +- /* uart9_txm0 */ +- <2 RK_PB0 3 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart9m0_ctsn: uart9m0-ctsn { +- rockchip,pins = +- /* uart9m0_ctsn */ +- <2 RK_PC4 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart9m0_rtsn: uart9m0-rtsn { +- rockchip,pins = +- /* uart9m0_rtsn */ +- <2 RK_PC3 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart9m1_xfer: uart9m1-xfer { +- rockchip,pins = +- /* uart9_rxm1 */ +- <4 RK_PC6 4 &pcfg_pull_up>, +- /* uart9_txm1 */ +- <4 RK_PC5 4 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart9m2_xfer: uart9m2-xfer { +- rockchip,pins = +- /* uart9_rxm2 */ +- <4 RK_PA5 4 &pcfg_pull_up>, +- /* uart9_txm2 */ +- <4 RK_PA4 4 &pcfg_pull_up>; +- }; +- }; +- +- vop { +- /omit-if-no-ref/ +- vopm0_pins: vopm0-pins { +- rockchip,pins = +- /* vop_pwmm0 */ +- <0 RK_PC3 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- vopm1_pins: vopm1-pins { +- rockchip,pins = +- /* vop_pwmm1 */ +- <3 RK_PC4 2 &pcfg_pull_none>; +- }; +- }; +-}; +- +-/* +- * This part is edited handly. +- */ +-&pinctrl { +- spi0-hs { +- /omit-if-no-ref/ +- spi0m0_pins_hs: spi0m0-pins { +- rockchip,pins = +- /* spi0_clkm0 */ +- <0 RK_PB5 2 &pcfg_pull_up_drv_level_1>, +- /* spi0_misom0 */ +- <0 RK_PC5 2 &pcfg_pull_up_drv_level_1>, +- /* spi0_mosim0 */ +- <0 RK_PB6 2 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi0m0_cs0_hs: spi0m0-cs0 { +- rockchip,pins = +- /* spi0_cs0m0 */ +- <0 RK_PC6 2 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi0m0_cs1_hs: spi0m0-cs1 { +- rockchip,pins = +- /* spi0_cs1m0 */ +- <0 RK_PC4 2 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi0m1_pins_hs: spi0m1-pins { +- rockchip,pins = +- /* spi0_clkm1 */ +- <2 RK_PD3 3 &pcfg_pull_up_drv_level_1>, +- /* spi0_misom1 */ +- <2 RK_PD0 3 &pcfg_pull_up_drv_level_1>, +- /* spi0_mosim1 */ +- <2 RK_PD1 3 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi0m1_cs0_hs: spi0m1-cs0 { +- rockchip,pins = +- /* spi0_cs0m1 */ +- <2 RK_PD2 3 &pcfg_pull_up_drv_level_1>; +- }; +- }; +- +- spi1-hs { +- /omit-if-no-ref/ +- spi1m0_pins_hs: spi1m0-pins { +- rockchip,pins = +- /* spi1_clkm0 */ +- <2 RK_PB5 3 &pcfg_pull_up_drv_level_1>, +- /* spi1_misom0 */ +- <2 RK_PB6 3 &pcfg_pull_up_drv_level_1>, +- /* spi1_mosim0 */ +- <2 RK_PB7 4 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi1m0_cs0_hs: spi1m0-cs0 { +- rockchip,pins = +- /* spi1_cs0m0 */ +- <2 RK_PC0 4 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi1m0_cs1_hs: spi1m0-cs1 { +- rockchip,pins = +- /* spi1_cs1m0 */ +- <2 RK_PC6 3 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi1m1_pins_hs: spi1m1-pins { +- rockchip,pins = +- /* spi1_clkm1 */ +- <3 RK_PC3 3 &pcfg_pull_up_drv_level_1>, +- /* spi1_misom1 */ +- <3 RK_PC2 3 &pcfg_pull_up_drv_level_1>, +- /* spi1_mosim1 */ +- <3 RK_PC1 3 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi1m1_cs0_hs: spi1m1-cs0 { +- rockchip,pins = +- /* spi1_cs0m1 */ +- <3 RK_PA1 3 &pcfg_pull_up_drv_level_1>; +- }; +- }; +- +- spi2-hs { +- /omit-if-no-ref/ +- spi2m0_pins_hs: spi2m0-pins { +- rockchip,pins = +- /* spi2_clkm0 */ +- <2 RK_PC1 4 &pcfg_pull_up_drv_level_1>, +- /* spi2_misom0 */ +- <2 RK_PC2 4 &pcfg_pull_up_drv_level_1>, +- /* spi2_mosim0 */ +- <2 RK_PC3 4 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi2m0_cs0_hs: spi2m0-cs0 { +- rockchip,pins = +- /* spi2_cs0m0 */ +- <2 RK_PC4 4 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi2m0_cs1_hs: spi2m0-cs1 { +- rockchip,pins = +- /* spi2_cs1m0 */ +- <2 RK_PC5 4 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi2m1_pins_hs: spi2m1-pins { +- rockchip,pins = +- /* spi2_clkm1 */ +- <3 RK_PA0 3 &pcfg_pull_up_drv_level_1>, +- /* spi2_misom1 */ +- <2 RK_PD7 3 &pcfg_pull_up_drv_level_1>, +- /* spi2_mosim1 */ +- <2 RK_PD6 3 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi2m1_cs0_hs: spi2m1-cs0 { +- rockchip,pins = +- /* spi2_cs0m1 */ +- <2 RK_PD5 3 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi2m1_cs1_hs: spi2m1-cs1 { +- rockchip,pins = +- /* spi2_cs1m1 */ +- <2 RK_PD4 3 &pcfg_pull_up_drv_level_1>; +- }; +- }; +- +- spi3-hs { +- /omit-if-no-ref/ +- spi3m0_pins_hs: spi3m0-pins { +- rockchip,pins = +- /* spi3_clkm0 */ +- <4 RK_PB3 4 &pcfg_pull_up_drv_level_1>, +- /* spi3_misom0 */ +- <4 RK_PB0 4 &pcfg_pull_up_drv_level_1>, +- /* spi3_mosim0 */ +- <4 RK_PB2 4 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi3m0_cs0_hs: spi3m0-cs0 { +- rockchip,pins = +- /* spi3_cs0m0 */ +- <4 RK_PA6 4 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi3m0_cs1_hs: spi3m0-cs1 { +- rockchip,pins = +- /* spi3_cs1m0 */ +- <4 RK_PA7 4 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi3m1_pins_hs: spi3m1-pins { +- rockchip,pins = +- /* spi3_clkm1 */ +- <4 RK_PC2 2 &pcfg_pull_up_drv_level_1>, +- /* spi3_misom1 */ +- <4 RK_PC5 2 &pcfg_pull_up_drv_level_1>, +- /* spi3_mosim1 */ +- <4 RK_PC3 2 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi3m1_cs0_hs: spi3m1-cs0 { +- rockchip,pins = +- /* spi3_cs0m1 */ +- <4 RK_PC6 2 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi3m1_cs1_hs: spi3m1-cs1 { +- rockchip,pins = +- /* spi3_cs1m1 */ +- <4 RK_PD1 2 &pcfg_pull_up_drv_level_1>; +- }; +- }; +- +- gmac-txd-level3 { +- /omit-if-no-ref/ +- gmac0_tx_bus2_level3: gmac0-tx-bus2-level3 { +- rockchip,pins = +- /* gmac0_txd0 */ +- <2 RK_PB3 1 &pcfg_pull_none_drv_level_3>, +- /* gmac0_txd1 */ +- <2 RK_PB4 1 &pcfg_pull_none_drv_level_3>, +- /* gmac0_txen */ +- <2 RK_PB5 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac0_rgmii_bus_level3: gmac0-rgmii-bus-level3 { +- rockchip,pins = +- /* gmac0_rxd2 */ +- <2 RK_PA3 2 &pcfg_pull_none>, +- /* gmac0_rxd3 */ +- <2 RK_PA4 2 &pcfg_pull_none>, +- /* gmac0_txd2 */ +- <2 RK_PA6 2 &pcfg_pull_none_drv_level_3>, +- /* gmac0_txd3 */ +- <2 RK_PA7 2 &pcfg_pull_none_drv_level_3>; +- }; +- +- /omit-if-no-ref/ +- gmac1m0_tx_bus2_level3: gmac1m0-tx-bus2-level3 { +- rockchip,pins = +- /* gmac1_txd0m0 */ +- <3 RK_PB5 3 &pcfg_pull_none_drv_level_3>, +- /* gmac1_txd1m0 */ +- <3 RK_PB6 3 &pcfg_pull_none_drv_level_3>, +- /* gmac1_txenm0 */ +- <3 RK_PB7 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1m0_rgmii_bus_level3: gmac1m0-rgmii-bus-level3 { +- rockchip,pins = +- /* gmac1_rxd2m0 */ +- <3 RK_PA4 3 &pcfg_pull_none>, +- /* gmac1_rxd3m0 */ +- <3 RK_PA5 3 &pcfg_pull_none>, +- /* gmac1_txd2m0 */ +- <3 RK_PA2 3 &pcfg_pull_none_drv_level_3>, +- /* gmac1_txd3m0 */ +- <3 RK_PA3 3 &pcfg_pull_none_drv_level_3>; +- }; +- +- /omit-if-no-ref/ +- gmac1m1_tx_bus2_level3: gmac1m1-tx-bus2-level3 { +- rockchip,pins = +- /* gmac1_txd0m1 */ +- <4 RK_PA4 3 &pcfg_pull_none_drv_level_3>, +- /* gmac1_txd1m1 */ +- <4 RK_PA5 3 &pcfg_pull_none_drv_level_3>, +- /* gmac1_txenm1 */ +- <4 RK_PA6 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1m1_rgmii_bus_level3: gmac1m1-rgmii-bus-level3 { +- rockchip,pins = +- /* gmac1_rxd2m1 */ +- <4 RK_PA1 3 &pcfg_pull_none>, +- /* gmac1_rxd3m1 */ +- <4 RK_PA2 3 &pcfg_pull_none>, +- /* gmac1_txd2m1 */ +- <3 RK_PD6 3 &pcfg_pull_none_drv_level_3>, +- /* gmac1_txd3m1 */ +- <3 RK_PD7 3 &pcfg_pull_none_drv_level_3>; +- }; +- }; +- +- gmac-txc-level2 { +- /omit-if-no-ref/ +- gmac0_rgmii_clk_level2: gmac0-rgmii-clk-level2 { +- rockchip,pins = +- /* gmac0_rxclk */ +- <2 RK_PA5 2 &pcfg_pull_none>, +- /* gmac0_txclk */ +- <2 RK_PB0 2 &pcfg_pull_none_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- gmac1m0_rgmii_clk_level2: gmac1m0-rgmii-clk-level2 { +- rockchip,pins = +- /* gmac1_rxclkm0 */ +- <3 RK_PA7 3 &pcfg_pull_none>, +- /* gmac1_txclkm0 */ +- <3 RK_PA6 3 &pcfg_pull_none_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- gmac1m1_rgmii_clk_level2: gmac1m1-rgmii-clk-level2 { +- rockchip,pins = +- /* gmac1_rxclkm1 */ +- <4 RK_PA3 3 &pcfg_pull_none>, +- /* gmac1_txclkm1 */ +- <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rk3568.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rk3568.dtsi +deleted file mode 100644 +index d225e6a45d5c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rk3568.dtsi ++++ /dev/null +@@ -1,593 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2021 Rockchip Electronics Co., Ltd. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "rockchip,rk3568"; +- +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- gpio2 = &gpio2; +- gpio3 = &gpio3; +- gpio4 = &gpio4; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- serial5 = &uart5; +- serial6 = &uart6; +- serial7 = &uart7; +- serial8 = &uart8; +- serial9 = &uart9; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x0>; +- clocks = <&scmi_clk 0>; +- enable-method = "psci"; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- cpu1: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- cpu2: cpu@200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x200>; +- enable-method = "psci"; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- cpu3: cpu@300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x300>; +- enable-method = "psci"; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- }; +- +- cpu0_opp_table: cpu0-opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-408000000 { +- opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <900000 900000 1150000>; +- clock-latency-ns = <40000>; +- }; +- +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <900000 900000 1150000>; +- }; +- +- opp-816000000 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <900000 900000 1150000>; +- opp-suspend; +- }; +- +- opp-1104000000 { +- opp-hz = /bits/ 64 <1104000000>; +- opp-microvolt = <900000 900000 1150000>; +- }; +- +- opp-1416000000 { +- opp-hz = /bits/ 64 <1416000000>; +- opp-microvolt = <900000 900000 1150000>; +- }; +- +- opp-1608000000 { +- opp-hz = /bits/ 64 <1608000000>; +- opp-microvolt = <975000 975000 1150000>; +- }; +- +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <1050000 1050000 1150000>; +- }; +- +- opp-1992000000 { +- opp-hz = /bits/ 64 <1992000000>; +- opp-microvolt = <1150000 1150000 1150000>; +- }; +- }; +- +- firmware { +- scmi: scmi { +- compatible = "arm,scmi-smc"; +- arm,smc-id = <0x82000010>; +- shmem = <&scmi_shmem>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- scmi_clk: protocol@14 { +- reg = <0x14>; +- #clock-cells = <1>; +- }; +- }; +- }; +- +- pmu { +- compatible = "arm,cortex-a55-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- arm,no-tick-in-suspend; +- }; +- +- xin24m: xin24m { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "xin24m"; +- #clock-cells = <0>; +- }; +- +- xin32k: xin32k { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-output-names = "xin32k"; +- pinctrl-0 = <&clk32k_out0>; +- pinctrl-names = "default"; +- #clock-cells = <0>; +- }; +- +- sram@10f000 { +- compatible = "mmio-sram"; +- reg = <0x0 0x0010f000 0x0 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x0 0x0010f000 0x100>; +- +- scmi_shmem: sram@0 { +- compatible = "arm,scmi-shmem"; +- reg = <0x0 0x100>; +- }; +- }; +- +- gic: interrupt-controller@fd400000 { +- compatible = "arm,gic-v3"; +- reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ +- <0x0 0xfd460000 0 0x80000>; /* GICR */ +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- mbi-alias = <0x0 0xfd100000>; +- mbi-ranges = <296 24>; +- msi-controller; +- }; +- +- pmugrf: syscon@fdc20000 { +- compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; +- reg = <0x0 0xfdc20000 0x0 0x10000>; +- }; +- +- grf: syscon@fdc60000 { +- compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; +- reg = <0x0 0xfdc60000 0x0 0x10000>; +- }; +- +- pmucru: clock-controller@fdd00000 { +- compatible = "rockchip,rk3568-pmucru"; +- reg = <0x0 0xfdd00000 0x0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- cru: clock-controller@fdd20000 { +- compatible = "rockchip,rk3568-cru"; +- reg = <0x0 0xfdd20000 0x0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- i2c0: i2c@fdd40000 { +- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfdd40000 0x0 0x1000>; +- interrupts = ; +- clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; +- clock-names = "i2c", "pclk"; +- pinctrl-0 = <&i2c0_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- uart0: serial@fdd50000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfdd50000 0x0 0x100>; +- interrupts = ; +- clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 0>, <&dmac0 1>; +- pinctrl-0 = <&uart0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- sdmmc2: mmc@fe000000 { +- compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xfe000000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, +- <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- max-frequency = <150000000>; +- resets = <&cru SRST_SDMMC2>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- sdmmc0: mmc@fe2b0000 { +- compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xfe2b0000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, +- <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- max-frequency = <150000000>; +- resets = <&cru SRST_SDMMC0>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- sdmmc1: mmc@fe2c0000 { +- compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xfe2c0000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, +- <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- max-frequency = <150000000>; +- resets = <&cru SRST_SDMMC1>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- sdhci: mmc@fe310000 { +- compatible = "rockchip,rk3568-dwcmshc"; +- reg = <0x0 0xfe310000 0x0 0x10000>; +- interrupts = ; +- assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; +- assigned-clock-rates = <200000000>, <24000000>; +- clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, +- <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, +- <&cru TCLK_EMMC>; +- clock-names = "core", "bus", "axi", "block", "timer"; +- status = "disabled"; +- }; +- +- dmac0: dmac@fe530000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xfe530000 0x0 0x4000>; +- interrupts = , +- ; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_BUS>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- }; +- +- dmac1: dmac@fe550000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xfe550000 0x0 0x4000>; +- interrupts = , +- ; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_BUS>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- }; +- +- i2c1: i2c@fe5a0000 { +- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfe5a0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; +- clock-names = "i2c", "pclk"; +- pinctrl-0 = <&i2c1_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@fe5b0000 { +- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfe5b0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; +- clock-names = "i2c", "pclk"; +- pinctrl-0 = <&i2c2m0_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@fe5c0000 { +- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfe5c0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; +- clock-names = "i2c", "pclk"; +- pinctrl-0 = <&i2c3m0_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@fe5d0000 { +- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfe5d0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; +- clock-names = "i2c", "pclk"; +- pinctrl-0 = <&i2c4m0_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c5: i2c@fe5e0000 { +- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfe5e0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; +- clock-names = "i2c", "pclk"; +- pinctrl-0 = <&i2c5m0_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- uart1: serial@fe650000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfe650000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 2>, <&dmac0 3>; +- pinctrl-0 = <&uart1m0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart2: serial@fe660000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfe660000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 4>, <&dmac0 5>; +- pinctrl-0 = <&uart2m0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart3: serial@fe670000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfe670000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 6>, <&dmac0 7>; +- pinctrl-0 = <&uart3m0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart4: serial@fe680000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfe680000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 8>, <&dmac0 9>; +- pinctrl-0 = <&uart4m0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart5: serial@fe690000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfe690000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 10>, <&dmac0 11>; +- pinctrl-0 = <&uart5m0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart6: serial@fe6a0000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfe6a0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 12>, <&dmac0 13>; +- pinctrl-0 = <&uart6m0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart7: serial@fe6b0000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfe6b0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 14>, <&dmac0 15>; +- pinctrl-0 = <&uart7m0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart8: serial@fe6c0000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfe6c0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 16>, <&dmac0 17>; +- pinctrl-0 = <&uart8m0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart9: serial@fe6d0000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfe6d0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 18>, <&dmac0 19>; +- pinctrl-0 = <&uart9m0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- pinctrl: pinctrl { +- compatible = "rockchip,rk3568-pinctrl"; +- rockchip,grf = <&grf>; +- rockchip,pmu = <&pmugrf>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gpio0: gpio@fdd60000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xfdd60000 0x0 0x100>; +- interrupts = ; +- clocks = <&pmucru PCLK_GPIO0>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio@fe740000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xfe740000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO1>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@fe750000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xfe750000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO2>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio@fe760000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xfe760000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO3>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio4: gpio@fe770000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xfe770000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO4>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; +-}; +- +-#include "rk3568-pinctrl.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/rockchip/rockchip-pinconf.dtsi b/scripts/dtc/include-prefixes/arm64/rockchip/rockchip-pinconf.dtsi +deleted file mode 100644 +index 5c645437b507..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/rockchip/rockchip-pinconf.dtsi ++++ /dev/null +@@ -1,344 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2021 Rockchip Electronics Co., Ltd. +- */ +- +-&pinctrl { +- /omit-if-no-ref/ +- pcfg_pull_up: pcfg-pull-up { +- bias-pull-up; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_down: pcfg-pull-down { +- bias-pull-down; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_none: pcfg-pull-none { +- bias-disable; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 { +- bias-disable; +- drive-strength = <0>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 { +- bias-disable; +- drive-strength = <1>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 { +- bias-disable; +- drive-strength = <2>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 { +- bias-disable; +- drive-strength = <3>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 { +- bias-disable; +- drive-strength = <4>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 { +- bias-disable; +- drive-strength = <5>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 { +- bias-disable; +- drive-strength = <6>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 { +- bias-disable; +- drive-strength = <7>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 { +- bias-disable; +- drive-strength = <8>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 { +- bias-disable; +- drive-strength = <9>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 { +- bias-disable; +- drive-strength = <10>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 { +- bias-disable; +- drive-strength = <11>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 { +- bias-disable; +- drive-strength = <12>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 { +- bias-disable; +- drive-strength = <13>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 { +- bias-disable; +- drive-strength = <14>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 { +- bias-disable; +- drive-strength = <15>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 { +- bias-pull-up; +- drive-strength = <0>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 { +- bias-pull-up; +- drive-strength = <1>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 { +- bias-pull-up; +- drive-strength = <2>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 { +- bias-pull-up; +- drive-strength = <3>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 { +- bias-pull-up; +- drive-strength = <4>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 { +- bias-pull-up; +- drive-strength = <5>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 { +- bias-pull-up; +- drive-strength = <6>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 { +- bias-pull-up; +- drive-strength = <7>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 { +- bias-pull-up; +- drive-strength = <8>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 { +- bias-pull-up; +- drive-strength = <9>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 { +- bias-pull-up; +- drive-strength = <10>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 { +- bias-pull-up; +- drive-strength = <11>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 { +- bias-pull-up; +- drive-strength = <12>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 { +- bias-pull-up; +- drive-strength = <13>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 { +- bias-pull-up; +- drive-strength = <14>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 { +- bias-pull-up; +- drive-strength = <15>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 { +- bias-pull-down; +- drive-strength = <0>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 { +- bias-pull-down; +- drive-strength = <1>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 { +- bias-pull-down; +- drive-strength = <2>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 { +- bias-pull-down; +- drive-strength = <3>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 { +- bias-pull-down; +- drive-strength = <4>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 { +- bias-pull-down; +- drive-strength = <5>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 { +- bias-pull-down; +- drive-strength = <6>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 { +- bias-pull-down; +- drive-strength = <7>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 { +- bias-pull-down; +- drive-strength = <8>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 { +- bias-pull-down; +- drive-strength = <9>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 { +- bias-pull-down; +- drive-strength = <10>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 { +- bias-pull-down; +- drive-strength = <11>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 { +- bias-pull-down; +- drive-strength = <12>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 { +- bias-pull-down; +- drive-strength = <13>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 { +- bias-pull-down; +- drive-strength = <14>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 { +- bias-pull-down; +- drive-strength = <15>; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_up_smt: pcfg-pull-up-smt { +- bias-pull-up; +- input-schmitt-enable; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_down_smt: pcfg-pull-down-smt { +- bias-pull-down; +- input-schmitt-enable; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_none_smt: pcfg-pull-none-smt { +- bias-disable; +- input-schmitt-enable; +- }; +- +- /omit-if-no-ref/ +- pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt { +- bias-disable; +- drive-strength = <0>; +- input-schmitt-enable; +- }; +- +- /omit-if-no-ref/ +- pcfg_output_high: pcfg-output-high { +- output-high; +- }; +- +- /omit-if-no-ref/ +- pcfg_output_low: pcfg-output-low { +- output-low; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/socionext/Makefile b/scripts/dtc/include-prefixes/arm64/socionext/Makefile +deleted file mode 100644 +index dda3da33614b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/socionext/Makefile ++++ /dev/null +@@ -1,8 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_UNIPHIER) += \ +- uniphier-ld11-global.dtb \ +- uniphier-ld11-ref.dtb \ +- uniphier-ld20-akebi96.dtb \ +- uniphier-ld20-global.dtb \ +- uniphier-ld20-ref.dtb \ +- uniphier-pxs3-ref.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld11-global.dts b/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld11-global.dts +deleted file mode 100644 +index da44a15a8adf..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld11-global.dts ++++ /dev/null +@@ -1,171 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier LD11 Global Board +-// +-// Copyright (C) 2016-2017 Socionext Inc. +-// Author: Masahiro Yamada +-// Kunihiko Hayashi +- +-/dts-v1/; +-#include +-#include "uniphier-ld11.dtsi" +- +-/ { +- model = "UniPhier LD11 Global Board (REF_LD11_GP)"; +- compatible = "socionext,uniphier-ld11-global", +- "socionext,uniphier-ld11"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- ethernet0 = ð +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0 0x80000000 0 0x40000000>; +- }; +- +- dvdd_reg: reg-fixed { +- compatible = "regulator-fixed"; +- regulator-name = "DVDD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- amp_vcc_reg: reg-fixed { +- compatible = "regulator-fixed"; +- regulator-name = "AMP_VCC"; +- regulator-min-microvolt = <24000000>; +- regulator-max-microvolt = <24000000>; +- }; +- +- sound { +- compatible = "audio-graph-card"; +- label = "UniPhier LD11"; +- widgets = "Headphone", "Headphones"; +- dais = <&i2s_port2 +- &i2s_port3 +- &i2s_port4 +- &spdif_port0 +- &comp_spdif_port0>; +- hp-det-gpio = <&gpio UNIPHIER_GPIO_IRQ(0) GPIO_ACTIVE_LOW>; +- }; +- +- spdif-out { +- compatible = "linux,spdif-dit"; +- #sound-dai-cells = <0>; +- +- port@0 { +- spdif_tx: endpoint { +- remote-endpoint = <&spdif_hiecout1>; +- }; +- }; +- }; +- +- comp-spdif-out { +- compatible = "linux,spdif-dit"; +- #sound-dai-cells = <0>; +- +- port@0 { +- comp_spdif_tx: endpoint { +- remote-endpoint = <&comp_spdif_hiecout1>; +- }; +- }; +- }; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&serial1 { +- status = "okay"; +-}; +- +-&i2s_hpcmout1 { +- dai-format = "i2s"; +- remote-endpoint = <&tas_speaker>; +-}; +- +-&spdif_hiecout1 { +- remote-endpoint = <&spdif_tx>; +-}; +- +-&comp_spdif_hiecout1 { +- remote-endpoint = <&comp_spdif_tx>; +-}; +- +-&i2c0 { +- status = "okay"; +- +- tas5707a@1d { +- compatible = "ti,tas5711"; +- reg = <0x1d>; +- reset-gpios = <&gpio UNIPHIER_GPIO_PORT(23, 4) GPIO_ACTIVE_LOW>; +- pdn-gpios = <&gpio UNIPHIER_GPIO_PORT(23, 5) GPIO_ACTIVE_LOW>; +- #sound-dai-cells = <0>; +- AVDD-supply = <&dvdd_reg>; +- DVDD-supply = <&dvdd_reg>; +- PVDD_A-supply = <&_vcc_reg>; +- PVDD_B-supply = <&_vcc_reg>; +- PVDD_C-supply = <&_vcc_reg>; +- PVDD_D-supply = <&_vcc_reg>; +- +- port@0 { +- tas_speaker: endpoint { +- dai-format = "i2s"; +- remote-endpoint = <&i2s_hpcmout1>; +- }; +- }; +- }; +- +- eeprom@50 { +- compatible = "st,24c64", "atmel,24c64"; +- reg = <0x50>; +- pagesize = <32>; +- }; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&usb2 { +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- phy-handle = <ðphy>; +-}; +- +-&mdio { +- ethphy: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&nand { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld11-ref.dts b/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld11-ref.dts +deleted file mode 100644 +index 617d2b1e9b1e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld11-ref.dts ++++ /dev/null +@@ -1,86 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier LD11 Reference Board +-// +-// Copyright (C) 2016 Socionext Inc. +-// Author: Masahiro Yamada +- +-/dts-v1/; +-#include "uniphier-ld11.dtsi" +-#include "uniphier-ref-daughter.dtsi" +-#include "uniphier-support-card.dtsi" +- +-/ { +- model = "UniPhier LD11 Reference Board"; +- compatible = "socionext,uniphier-ld11-ref", "socionext,uniphier-ld11"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serialsc; +- serial2 = &serial2; +- serial3 = &serial3; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- ethernet0 = ð +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0 0x80000000 0 0x40000000>; +- }; +-}; +- +-ðsc { +- interrupts = <0 8>; +-}; +- +-&serialsc { +- interrupts = <0 8>; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&gpio { +- xirq0 { +- gpio-hog; +- gpios = ; +- input; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&usb2 { +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- phy-handle = <ðphy>; +-}; +- +-&mdio { +- ethphy: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld11.dtsi b/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld11.dtsi +deleted file mode 100644 +index 15dcfc259854..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld11.dtsi ++++ /dev/null +@@ -1,663 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier LD11 SoC +-// +-// Copyright (C) 2016 Socionext Inc. +-// Author: Masahiro Yamada +- +-#include +-#include +- +-/ { +- compatible = "socionext,uniphier-ld11"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&gic>; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- }; +- }; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0 0x000>; +- clocks = <&sys_clk 33>; +- enable-method = "psci"; +- operating-points-v2 = <&cluster0_opp>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0 0x001>; +- clocks = <&sys_clk 33>; +- enable-method = "psci"; +- operating-points-v2 = <&cluster0_opp>; +- }; +- }; +- +- cluster0_opp: opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-245000000 { +- opp-hz = /bits/ 64 <245000000>; +- clock-latency-ns = <300>; +- }; +- opp-250000000 { +- opp-hz = /bits/ 64 <250000000>; +- clock-latency-ns = <300>; +- }; +- opp-490000000 { +- opp-hz = /bits/ 64 <490000000>; +- clock-latency-ns = <300>; +- }; +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- clock-latency-ns = <300>; +- }; +- opp-653334000 { +- opp-hz = /bits/ 64 <653334000>; +- clock-latency-ns = <300>; +- }; +- opp-666667000 { +- opp-hz = /bits/ 64 <666667000>; +- clock-latency-ns = <300>; +- }; +- opp-980000000 { +- opp-hz = /bits/ 64 <980000000>; +- clock-latency-ns = <300>; +- }; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- clocks { +- refclk: ref { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = <1 13 4>, +- <1 14 4>, +- <1 11 4>, +- <1 10 4>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- secure-memory@81000000 { +- reg = <0x0 0x81000000 0x0 0x01000000>; +- no-map; +- }; +- }; +- +- soc@0 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0 0xffffffff>; +- +- spi0: spi@54006000 { +- compatible = "socionext,uniphier-scssi"; +- status = "disabled"; +- reg = <0x54006000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 39 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0>; +- clocks = <&peri_clk 11>; +- resets = <&peri_rst 11>; +- }; +- +- spi1: spi@54006100 { +- compatible = "socionext,uniphier-scssi"; +- status = "disabled"; +- reg = <0x54006100 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 216 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1>; +- clocks = <&peri_clk 12>; +- resets = <&peri_rst 12>; +- }; +- +- serial0: serial@54006800 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006800 0x40>; +- interrupts = <0 33 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- clocks = <&peri_clk 0>; +- resets = <&peri_rst 0>; +- }; +- +- serial1: serial@54006900 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006900 0x40>; +- interrupts = <0 35 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- clocks = <&peri_clk 1>; +- resets = <&peri_rst 1>; +- }; +- +- serial2: serial@54006a00 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006a00 0x40>; +- interrupts = <0 37 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- clocks = <&peri_clk 2>; +- resets = <&peri_rst 2>; +- }; +- +- serial3: serial@54006b00 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006b00 0x40>; +- interrupts = <0 177 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- clocks = <&peri_clk 3>; +- resets = <&peri_rst 3>; +- }; +- +- gpio: gpio@55000000 { +- compatible = "socionext,uniphier-gpio"; +- reg = <0x55000000 0x200>; +- interrupt-parent = <&aidet>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 0 0>, +- <&pinctrl 43 0 0>, +- <&pinctrl 51 0 0>, +- <&pinctrl 96 0 0>, +- <&pinctrl 160 0 0>, +- <&pinctrl 184 0 0>; +- gpio-ranges-group-names = "gpio_range0", +- "gpio_range1", +- "gpio_range2", +- "gpio_range3", +- "gpio_range4", +- "gpio_range5"; +- ngpios = <200>; +- socionext,interrupt-ranges = <0 48 16>, <16 154 5>, +- <21 217 3>; +- }; +- +- audio@56000000 { +- compatible = "socionext,uniphier-ld11-aio"; +- reg = <0x56000000 0x80000>; +- interrupts = <0 144 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_aout1>, +- <&pinctrl_aoutiec1>; +- clock-names = "aio"; +- clocks = <&sys_clk 40>; +- reset-names = "aio"; +- resets = <&sys_rst 40>; +- #sound-dai-cells = <1>; +- socionext,syscon = <&soc_glue>; +- +- i2s_port0: port@0 { +- i2s_hdmi: endpoint { +- }; +- }; +- +- i2s_port1: port@1 { +- i2s_pcmin2: endpoint { +- }; +- }; +- +- i2s_port2: port@2 { +- i2s_line: endpoint { +- dai-format = "i2s"; +- remote-endpoint = <&evea_line>; +- }; +- }; +- +- i2s_port3: port@3 { +- i2s_hpcmout1: endpoint { +- }; +- }; +- +- i2s_port4: port@4 { +- i2s_hp: endpoint { +- dai-format = "i2s"; +- remote-endpoint = <&evea_hp>; +- }; +- }; +- +- spdif_port0: port@5 { +- spdif_hiecout1: endpoint { +- }; +- }; +- +- src_port0: port@6 { +- i2s_epcmout2: endpoint { +- }; +- }; +- +- src_port1: port@7 { +- i2s_epcmout3: endpoint { +- }; +- }; +- +- comp_spdif_port0: port@8 { +- comp_spdif_hiecout1: endpoint { +- }; +- }; +- }; +- +- codec@57900000 { +- compatible = "socionext,uniphier-evea"; +- reg = <0x57900000 0x1000>; +- clock-names = "evea", "exiv"; +- clocks = <&sys_clk 41>, <&sys_clk 42>; +- reset-names = "evea", "exiv", "adamv"; +- resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>; +- #sound-dai-cells = <1>; +- +- port@0 { +- evea_line: endpoint { +- remote-endpoint = <&i2s_line>; +- }; +- }; +- +- port@1 { +- evea_hp: endpoint { +- remote-endpoint = <&i2s_hp>; +- }; +- }; +- }; +- +- adamv@57920000 { +- compatible = "socionext,uniphier-ld11-adamv", +- "simple-mfd", "syscon"; +- reg = <0x57920000 0x1000>; +- +- adamv_rst: reset { +- compatible = "socionext,uniphier-ld11-adamv-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- i2c0: i2c@58780000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58780000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 41 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0>; +- clocks = <&peri_clk 4>; +- resets = <&peri_rst 4>; +- clock-frequency = <100000>; +- }; +- +- i2c1: i2c@58781000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58781000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 42 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clocks = <&peri_clk 5>; +- resets = <&peri_rst 5>; +- clock-frequency = <100000>; +- }; +- +- i2c2: i2c@58782000 { +- compatible = "socionext,uniphier-fi2c"; +- reg = <0x58782000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 43 4>; +- clocks = <&peri_clk 6>; +- resets = <&peri_rst 6>; +- clock-frequency = <400000>; +- }; +- +- i2c3: i2c@58783000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58783000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 44 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- clocks = <&peri_clk 7>; +- resets = <&peri_rst 7>; +- clock-frequency = <100000>; +- }; +- +- i2c4: i2c@58784000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58784000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 45 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- clocks = <&peri_clk 8>; +- resets = <&peri_rst 8>; +- clock-frequency = <100000>; +- }; +- +- i2c5: i2c@58785000 { +- compatible = "socionext,uniphier-fi2c"; +- reg = <0x58785000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 25 4>; +- clocks = <&peri_clk 9>; +- resets = <&peri_rst 9>; +- clock-frequency = <400000>; +- }; +- +- system_bus: system-bus@58c00000 { +- compatible = "socionext,uniphier-system-bus"; +- status = "disabled"; +- reg = <0x58c00000 0x400>; +- #address-cells = <2>; +- #size-cells = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_system_bus>; +- }; +- +- smpctrl@59801000 { +- compatible = "socionext,uniphier-smpctrl"; +- reg = <0x59801000 0x400>; +- }; +- +- sdctrl@59810000 { +- compatible = "socionext,uniphier-ld11-sdctrl", +- "simple-mfd", "syscon"; +- reg = <0x59810000 0x400>; +- +- sd_rst: reset { +- compatible = "socionext,uniphier-ld11-sd-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- perictrl@59820000 { +- compatible = "socionext,uniphier-ld11-perictrl", +- "simple-mfd", "syscon"; +- reg = <0x59820000 0x200>; +- +- peri_clk: clock { +- compatible = "socionext,uniphier-ld11-peri-clock"; +- #clock-cells = <1>; +- }; +- +- peri_rst: reset { +- compatible = "socionext,uniphier-ld11-peri-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- emmc: mmc@5a000000 { +- compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; +- reg = <0x5a000000 0x400>; +- interrupts = <0 78 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_emmc>; +- clocks = <&sys_clk 4>; +- resets = <&sys_rst 4>; +- bus-width = <8>; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- mmc-pwrseq = <&emmc_pwrseq>; +- cdns,phy-input-delay-legacy = <9>; +- cdns,phy-input-delay-mmc-highspeed = <2>; +- cdns,phy-input-delay-mmc-ddr = <3>; +- cdns,phy-dll-delay-sdclk = <21>; +- cdns,phy-dll-delay-sdclk-hsmmc = <21>; +- }; +- +- usb0: usb@5a800100 { +- compatible = "socionext,uniphier-ehci", "generic-ehci"; +- status = "disabled"; +- reg = <0x5a800100 0x100>; +- interrupts = <0 243 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb0>; +- clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, +- <&mio_clk 12>; +- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, +- <&mio_rst 12>; +- phy-names = "usb"; +- phys = <&usb_phy0>; +- has-transaction-translator; +- }; +- +- usb1: usb@5a810100 { +- compatible = "socionext,uniphier-ehci", "generic-ehci"; +- status = "disabled"; +- reg = <0x5a810100 0x100>; +- interrupts = <0 244 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb1>; +- clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, +- <&mio_clk 13>; +- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, +- <&mio_rst 13>; +- phy-names = "usb"; +- phys = <&usb_phy1>; +- has-transaction-translator; +- }; +- +- usb2: usb@5a820100 { +- compatible = "socionext,uniphier-ehci", "generic-ehci"; +- status = "disabled"; +- reg = <0x5a820100 0x100>; +- interrupts = <0 245 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb2>; +- clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, +- <&mio_clk 14>; +- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, +- <&mio_rst 14>; +- phy-names = "usb"; +- phys = <&usb_phy2>; +- has-transaction-translator; +- }; +- +- mioctrl@5b3e0000 { +- compatible = "socionext,uniphier-ld11-mioctrl", +- "simple-mfd", "syscon"; +- reg = <0x5b3e0000 0x800>; +- +- mio_clk: clock { +- compatible = "socionext,uniphier-ld11-mio-clock"; +- #clock-cells = <1>; +- }; +- +- mio_rst: reset { +- compatible = "socionext,uniphier-ld11-mio-reset"; +- #reset-cells = <1>; +- resets = <&sys_rst 7>; +- }; +- }; +- +- soc_glue: soc-glue@5f800000 { +- compatible = "socionext,uniphier-ld11-soc-glue", +- "simple-mfd", "syscon"; +- reg = <0x5f800000 0x2000>; +- +- pinctrl: pinctrl { +- compatible = "socionext,uniphier-ld11-pinctrl"; +- }; +- +- usb-phy { +- compatible = "socionext,uniphier-ld11-usb2-phy"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- usb_phy0: phy@0 { +- reg = <0>; +- #phy-cells = <0>; +- }; +- +- usb_phy1: phy@1 { +- reg = <1>; +- #phy-cells = <0>; +- }; +- +- usb_phy2: phy@2 { +- reg = <2>; +- #phy-cells = <0>; +- }; +- }; +- }; +- +- soc-glue@5f900000 { +- compatible = "socionext,uniphier-ld11-soc-glue-debug", +- "simple-mfd"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x5f900000 0x2000>; +- +- efuse@100 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x100 0x28>; +- }; +- +- efuse@200 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x200 0x68>; +- }; +- }; +- +- xdmac: dma-controller@5fc10000 { +- compatible = "socionext,uniphier-xdmac"; +- reg = <0x5fc10000 0x5300>; +- interrupts = <0 188 4>; +- dma-channels = <16>; +- #dma-cells = <2>; +- }; +- +- aidet: interrupt-controller@5fc20000 { +- compatible = "socionext,uniphier-ld11-aidet"; +- reg = <0x5fc20000 0x200>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gic: interrupt-controller@5fe00000 { +- compatible = "arm,gic-v3"; +- reg = <0x5fe00000 0x10000>, /* GICD */ +- <0x5fe40000 0x80000>; /* GICR */ +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = <1 9 4>; +- }; +- +- sysctrl@61840000 { +- compatible = "socionext,uniphier-ld11-sysctrl", +- "simple-mfd", "syscon"; +- reg = <0x61840000 0x10000>; +- +- sys_clk: clock { +- compatible = "socionext,uniphier-ld11-clock"; +- #clock-cells = <1>; +- }; +- +- sys_rst: reset { +- compatible = "socionext,uniphier-ld11-reset"; +- #reset-cells = <1>; +- }; +- +- watchdog { +- compatible = "socionext,uniphier-wdt"; +- }; +- }; +- +- eth: ethernet@65000000 { +- compatible = "socionext,uniphier-ld11-ave4"; +- status = "disabled"; +- reg = <0x65000000 0x8500>; +- interrupts = <0 66 4>; +- clock-names = "ether"; +- clocks = <&sys_clk 6>; +- reset-names = "ether"; +- resets = <&sys_rst 6>; +- phy-mode = "internal"; +- local-mac-address = [00 00 00 00 00 00]; +- socionext,syscon-phy-mode = <&soc_glue 0>; +- +- mdio: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- nand: nand-controller@68000000 { +- compatible = "socionext,uniphier-denali-nand-v5b"; +- status = "disabled"; +- reg-names = "nand_data", "denali_reg"; +- reg = <0x68000000 0x20>, <0x68100000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 65 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nand>; +- clock-names = "nand", "nand_x", "ecc"; +- clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; +- reset-names = "nand", "reg"; +- resets = <&sys_rst 2>, <&sys_rst 2>; +- }; +- }; +-}; +- +-#include "uniphier-pinctrl.dtsi" +- +-&pinctrl_aoutiec1 { +- drive-strength = <4>; /* default: 4mA */ +- +- ao1arc { +- pins = "AO1ARC"; +- drive-strength = <8>; /* 8mA */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld20-akebi96.dts b/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld20-akebi96.dts +deleted file mode 100644 +index aa159a11292c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld20-akebi96.dts ++++ /dev/null +@@ -1,189 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for Akebi96 Development Board +-// +-// Derived from uniphier-ld20-global.dts. +-// +-// Copyright (C) 2015-2017 Socionext Inc. +-// Copyright (C) 2019-2020 Linaro Ltd. +- +-/dts-v1/; +-#include +-#include "uniphier-ld20.dtsi" +- +-/ { +- model = "Akebi96"; +- compatible = "socionext,uniphier-ld20-akebi96", +- "socionext,uniphier-ld20"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- spi0 = &spi0; +- spi1 = &spi1; +- spi2 = &spi2; +- spi3 = &spi3; +- ethernet0 = ð +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0 0x80000000 0 0xc0000000>; +- }; +- +- framebuffer@c0000000 { +- compatible = "simple-framebuffer"; +- reg = <0 0xc0000000 0 0x02000000>; +- width = <1920>; +- height = <1080>; +- stride = <7680>; +- format = "a8r8g8b8"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- memory@c0000000 { +- reg = <0 0xc0000000 0 0x02000000>; +- no-map; +- }; +- }; +- +- sound { +- compatible = "audio-graph-card"; +- label = "UniPhier LD20"; +- dais = <&spdif_port0 +- &comp_spdif_port0>; +- }; +- +- spdif-out { +- compatible = "linux,spdif-dit"; +- #sound-dai-cells = <0>; +- +- port@0 { +- spdif_tx: endpoint { +- remote-endpoint = <&spdif_hiecout1>; +- }; +- }; +- }; +- +- comp-spdif-out { +- compatible = "linux,spdif-dit"; +- #sound-dai-cells = <0>; +- +- port@0 { +- comp_spdif_tx: endpoint { +- remote-endpoint = <&comp_spdif_hiecout1>; +- }; +- }; +- }; +- +- firmware { +- optee { +- compatible = "linaro,optee-tz"; +- method = "smc"; +- }; +- }; +-}; +- +-&spi3 { +- status = "okay"; +- #address-cells = <1>; +- #size-cells = <0>; +- usb-over-spi@0 { +- compatible = "maxim,max3421-udc"; +- reg = <0>; +- spi-max-frequency = <12500000>; +- interrupt-parent = <&gpio>; +- interrupt-names = "udc"; +- interrupts = <0 2>; +- }; +-}; +- +-&serial0 { +- /* Onboard USB-UART */ +- status = "okay"; +-}; +- +-&serial2 { +- /* LS connector UART1 */ +- status = "okay"; +-}; +- +-&serial3 { +- /* LS connector UART0 */ +- status = "okay"; +-}; +- +-&spdif_hiecout1 { +- remote-endpoint = <&spdif_tx>; +-}; +- +-&comp_spdif_hiecout1 { +- remote-endpoint = <&comp_spdif_tx>; +-}; +- +-&i2c0 { +- /* LS connector I2C0 */ +- status = "okay"; +-}; +- +-&i2c1 { +- /* LS connector I2C1 */ +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- phy-handle = <ðphy>; +-}; +- +-&mdio { +- ethphy: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&usb { +- status = "okay"; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&gpio { +- /* IRQs for Max3421 */ +- xirq0 { +- gpio-hog; +- gpios = ; +- input; +- }; +- xirq10 { +- gpio-hog; +- gpios = ; +- input; +- }; +-}; +- +-&pinctrl_aout1 { +- groups = "aout1b"; +-}; +- +-&pinctrl_uart3 { +- groups = "uart3", "uart3_ctsrts"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld20-global.dts b/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld20-global.dts +deleted file mode 100644 +index a01579cb3b79..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld20-global.dts ++++ /dev/null +@@ -1,155 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier LD20 Global Board +-// +-// Copyright (C) 2015-2017 Socionext Inc. +-// Author: Masahiro Yamada +-// Kunihiko Hayashi +- +-/dts-v1/; +-#include +-#include "uniphier-ld20.dtsi" +- +-/ { +- model = "UniPhier LD20 Global Board (REF_LD20_GP)"; +- compatible = "socionext,uniphier-ld20-global", +- "socionext,uniphier-ld20"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- ethernet0 = ð +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0 0x80000000 0 0xc0000000>; +- }; +- +- dvdd_reg: reg-fixed { +- compatible = "regulator-fixed"; +- regulator-name = "DVDD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- amp_vcc_reg: reg-fixed { +- compatible = "regulator-fixed"; +- regulator-name = "AMP_VCC"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- sound { +- compatible = "audio-graph-card"; +- label = "UniPhier LD20"; +- widgets = "Headphone", "Headphones"; +- dais = <&i2s_port2 +- &i2s_port3 +- &i2s_port4 +- &spdif_port0 +- &comp_spdif_port0>; +- hp-det-gpio = <&gpio UNIPHIER_GPIO_IRQ(0) GPIO_ACTIVE_LOW>; +- }; +- +- spdif-out { +- compatible = "linux,spdif-dit"; +- #sound-dai-cells = <0>; +- +- port@0 { +- spdif_tx: endpoint { +- remote-endpoint = <&spdif_hiecout1>; +- }; +- }; +- }; +- +- comp-spdif-out { +- compatible = "linux,spdif-dit"; +- #sound-dai-cells = <0>; +- +- port@0 { +- comp_spdif_tx: endpoint { +- remote-endpoint = <&comp_spdif_hiecout1>; +- }; +- }; +- }; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&serial1 { +- status = "okay"; +-}; +- +-&i2s_hpcmout1 { +- dai-format = "i2s"; +- remote-endpoint = <&tas_speaker>; +-}; +- +-&spdif_hiecout1 { +- remote-endpoint = <&spdif_tx>; +-}; +- +-&comp_spdif_hiecout1 { +- remote-endpoint = <&comp_spdif_tx>; +-}; +- +-&i2c0 { +- status = "okay"; +- +- tas5707@1b { +- compatible = "ti,tas5711"; +- reg = <0x1b>; +- reset-gpios = <&gpio UNIPHIER_GPIO_PORT(0, 0) GPIO_ACTIVE_LOW>; +- pdn-gpios = <&gpio UNIPHIER_GPIO_PORT(0, 1) GPIO_ACTIVE_LOW>; +- #sound-dai-cells = <0>; +- AVDD-supply = <&dvdd_reg>; +- DVDD-supply = <&dvdd_reg>; +- PVDD_A-supply = <&_vcc_reg>; +- PVDD_B-supply = <&_vcc_reg>; +- PVDD_C-supply = <&_vcc_reg>; +- PVDD_D-supply = <&_vcc_reg>; +- +- port@0 { +- tas_speaker: endpoint { +- dai-format = "i2s"; +- remote-endpoint = <&i2s_hpcmout1>; +- }; +- }; +- }; +-}; +- +-ð { +- status = "okay"; +- phy-mode = "rmii"; +- pinctrl-0 = <&pinctrl_ether_rmii>; +- phy-handle = <ðphy>; +-}; +- +-&mdio { +- ethphy: ethernet-phy@1 { +- reg = <1>; +- }; +-}; +- +-&usb { +- status = "okay"; +-}; +- +-&nand { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld20-ref.dts b/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld20-ref.dts +deleted file mode 100644 +index 39ee279a1eb9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld20-ref.dts ++++ /dev/null +@@ -1,86 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier LD20 Reference Board +-// +-// Copyright (C) 2015-2016 Socionext Inc. +-// Author: Masahiro Yamada +- +-/dts-v1/; +-#include "uniphier-ld20.dtsi" +-#include "uniphier-ref-daughter.dtsi" +-#include "uniphier-support-card.dtsi" +- +-/ { +- model = "UniPhier LD20 Reference Board"; +- compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serialsc; +- serial2 = &serial2; +- serial3 = &serial3; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- ethernet0 = ð +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0 0x80000000 0 0xc0000000>; +- }; +-}; +- +-ðsc { +- interrupts = <0 8>; +-}; +- +-&serialsc { +- interrupts = <0 8>; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&gpio { +- xirq0 { +- gpio-hog; +- gpios = ; +- input; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- phy-handle = <ðphy>; +-}; +- +-&mdio { +- ethphy: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&pinctrl_ether_rgmii { +- tx { +- pins = "RGMII_TXCLK", "RGMII_TXD0", "RGMII_TXD1", +- "RGMII_TXD2", "RGMII_TXD3", "RGMII_TXCTL"; +- drive-strength = <9>; +- }; +-}; +- +-&usb { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld20.dtsi b/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld20.dtsi +deleted file mode 100644 +index 8f2c1c1e2c64..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld20.dtsi ++++ /dev/null +@@ -1,982 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier LD20 SoC +-// +-// Copyright (C) 2015-2016 Socionext Inc. +-// Author: Masahiro Yamada +- +-#include +-#include +-#include +- +-/ { +- compatible = "socionext,uniphier-ld20"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&gic>; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&cpu2>; +- }; +- core1 { +- cpu = <&cpu3>; +- }; +- }; +- }; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0 0x000>; +- clocks = <&sys_clk 32>; +- enable-method = "psci"; +- operating-points-v2 = <&cluster0_opp>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a72"; +- reg = <0 0x001>; +- clocks = <&sys_clk 32>; +- enable-method = "psci"; +- operating-points-v2 = <&cluster0_opp>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0 0x100>; +- clocks = <&sys_clk 33>; +- enable-method = "psci"; +- operating-points-v2 = <&cluster1_opp>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0 0x101>; +- clocks = <&sys_clk 33>; +- enable-method = "psci"; +- operating-points-v2 = <&cluster1_opp>; +- #cooling-cells = <2>; +- }; +- }; +- +- cluster0_opp: opp-table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-250000000 { +- opp-hz = /bits/ 64 <250000000>; +- clock-latency-ns = <300>; +- }; +- opp-275000000 { +- opp-hz = /bits/ 64 <275000000>; +- clock-latency-ns = <300>; +- }; +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- clock-latency-ns = <300>; +- }; +- opp-550000000 { +- opp-hz = /bits/ 64 <550000000>; +- clock-latency-ns = <300>; +- }; +- opp-666667000 { +- opp-hz = /bits/ 64 <666667000>; +- clock-latency-ns = <300>; +- }; +- opp-733334000 { +- opp-hz = /bits/ 64 <733334000>; +- clock-latency-ns = <300>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- clock-latency-ns = <300>; +- }; +- opp-1100000000 { +- opp-hz = /bits/ 64 <1100000000>; +- clock-latency-ns = <300>; +- }; +- }; +- +- cluster1_opp: opp-table1 { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-250000000 { +- opp-hz = /bits/ 64 <250000000>; +- clock-latency-ns = <300>; +- }; +- opp-275000000 { +- opp-hz = /bits/ 64 <275000000>; +- clock-latency-ns = <300>; +- }; +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- clock-latency-ns = <300>; +- }; +- opp-550000000 { +- opp-hz = /bits/ 64 <550000000>; +- clock-latency-ns = <300>; +- }; +- opp-666667000 { +- opp-hz = /bits/ 64 <666667000>; +- clock-latency-ns = <300>; +- }; +- opp-733334000 { +- opp-hz = /bits/ 64 <733334000>; +- clock-latency-ns = <300>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- clock-latency-ns = <300>; +- }; +- opp-1100000000 { +- opp-hz = /bits/ 64 <1100000000>; +- clock-latency-ns = <300>; +- }; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- clocks { +- refclk: ref { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = <1 13 4>, +- <1 14 4>, +- <1 11 4>, +- <1 10 4>; +- }; +- +- thermal-zones { +- cpu-thermal { +- polling-delay-passive = <250>; /* 250ms */ +- polling-delay = <1000>; /* 1000ms */ +- thermal-sensors = <&pvtctl>; +- +- trips { +- cpu_crit: cpu-crit { +- temperature = <110000>; /* 110C */ +- hysteresis = <2000>; +- type = "critical"; +- }; +- cpu_alert: cpu-alert { +- temperature = <100000>; /* 100C */ +- hysteresis = <2000>; +- type = "passive"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- secure-memory@81000000 { +- reg = <0x0 0x81000000 0x0 0x01000000>; +- no-map; +- }; +- }; +- +- soc@0 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0 0xffffffff>; +- +- spi0: spi@54006000 { +- compatible = "socionext,uniphier-scssi"; +- status = "disabled"; +- reg = <0x54006000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 39 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0>; +- clocks = <&peri_clk 11>; +- resets = <&peri_rst 11>; +- }; +- +- spi1: spi@54006100 { +- compatible = "socionext,uniphier-scssi"; +- status = "disabled"; +- reg = <0x54006100 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 216 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1>; +- clocks = <&peri_clk 12>; +- resets = <&peri_rst 12>; +- }; +- +- spi2: spi@54006200 { +- compatible = "socionext,uniphier-scssi"; +- status = "disabled"; +- reg = <0x54006200 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 229 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi2>; +- clocks = <&peri_clk 13>; +- resets = <&peri_rst 13>; +- }; +- +- spi3: spi@54006300 { +- compatible = "socionext,uniphier-scssi"; +- status = "disabled"; +- reg = <0x54006300 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 230 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi3>; +- clocks = <&peri_clk 14>; +- resets = <&peri_rst 14>; +- }; +- +- serial0: serial@54006800 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006800 0x40>; +- interrupts = <0 33 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- clocks = <&peri_clk 0>; +- resets = <&peri_rst 0>; +- }; +- +- serial1: serial@54006900 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006900 0x40>; +- interrupts = <0 35 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- clocks = <&peri_clk 1>; +- resets = <&peri_rst 1>; +- }; +- +- serial2: serial@54006a00 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006a00 0x40>; +- interrupts = <0 37 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- clocks = <&peri_clk 2>; +- resets = <&peri_rst 2>; +- }; +- +- serial3: serial@54006b00 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006b00 0x40>; +- interrupts = <0 177 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- clocks = <&peri_clk 3>; +- resets = <&peri_rst 3>; +- }; +- +- gpio: gpio@55000000 { +- compatible = "socionext,uniphier-gpio"; +- reg = <0x55000000 0x200>; +- interrupt-parent = <&aidet>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 0 0>, +- <&pinctrl 96 0 0>, +- <&pinctrl 160 0 0>; +- gpio-ranges-group-names = "gpio_range0", +- "gpio_range1", +- "gpio_range2"; +- ngpios = <205>; +- socionext,interrupt-ranges = <0 48 16>, <16 154 5>, +- <21 217 3>; +- }; +- +- audio@56000000 { +- compatible = "socionext,uniphier-ld20-aio"; +- reg = <0x56000000 0x80000>; +- interrupts = <0 144 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_aout1>, +- <&pinctrl_aoutiec1>; +- clock-names = "aio"; +- clocks = <&sys_clk 40>; +- reset-names = "aio"; +- resets = <&sys_rst 40>; +- #sound-dai-cells = <1>; +- socionext,syscon = <&soc_glue>; +- +- i2s_port0: port@0 { +- i2s_hdmi: endpoint { +- }; +- }; +- +- i2s_port1: port@1 { +- i2s_pcmin2: endpoint { +- }; +- }; +- +- i2s_port2: port@2 { +- i2s_line: endpoint { +- dai-format = "i2s"; +- remote-endpoint = <&evea_line>; +- }; +- }; +- +- i2s_port3: port@3 { +- i2s_hpcmout1: endpoint { +- }; +- }; +- +- i2s_port4: port@4 { +- i2s_hp: endpoint { +- dai-format = "i2s"; +- remote-endpoint = <&evea_hp>; +- }; +- }; +- +- spdif_port0: port@5 { +- spdif_hiecout1: endpoint { +- }; +- }; +- +- src_port0: port@6 { +- i2s_epcmout2: endpoint { +- }; +- }; +- +- src_port1: port@7 { +- i2s_epcmout3: endpoint { +- }; +- }; +- +- comp_spdif_port0: port@8 { +- comp_spdif_hiecout1: endpoint { +- }; +- }; +- }; +- +- codec@57900000 { +- compatible = "socionext,uniphier-evea"; +- reg = <0x57900000 0x1000>; +- clock-names = "evea", "exiv"; +- clocks = <&sys_clk 41>, <&sys_clk 42>; +- reset-names = "evea", "exiv", "adamv"; +- resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>; +- #sound-dai-cells = <1>; +- +- port@0 { +- evea_line: endpoint { +- remote-endpoint = <&i2s_line>; +- }; +- }; +- +- port@1 { +- evea_hp: endpoint { +- remote-endpoint = <&i2s_hp>; +- }; +- }; +- }; +- +- adamv@57920000 { +- compatible = "socionext,uniphier-ld20-adamv", +- "simple-mfd", "syscon"; +- reg = <0x57920000 0x1000>; +- +- adamv_rst: reset { +- compatible = "socionext,uniphier-ld20-adamv-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- i2c0: i2c@58780000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58780000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 41 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0>; +- clocks = <&peri_clk 4>; +- resets = <&peri_rst 4>; +- clock-frequency = <100000>; +- }; +- +- i2c1: i2c@58781000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58781000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 42 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clocks = <&peri_clk 5>; +- resets = <&peri_rst 5>; +- clock-frequency = <100000>; +- }; +- +- i2c2: i2c@58782000 { +- compatible = "socionext,uniphier-fi2c"; +- reg = <0x58782000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 43 4>; +- clocks = <&peri_clk 6>; +- resets = <&peri_rst 6>; +- clock-frequency = <400000>; +- }; +- +- i2c3: i2c@58783000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58783000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 44 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- clocks = <&peri_clk 7>; +- resets = <&peri_rst 7>; +- clock-frequency = <100000>; +- }; +- +- i2c4: i2c@58784000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58784000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 45 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c4>; +- clocks = <&peri_clk 8>; +- resets = <&peri_rst 8>; +- clock-frequency = <100000>; +- }; +- +- i2c5: i2c@58785000 { +- compatible = "socionext,uniphier-fi2c"; +- reg = <0x58785000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 25 4>; +- clocks = <&peri_clk 9>; +- resets = <&peri_rst 9>; +- clock-frequency = <400000>; +- }; +- +- system_bus: system-bus@58c00000 { +- compatible = "socionext,uniphier-system-bus"; +- status = "disabled"; +- reg = <0x58c00000 0x400>; +- #address-cells = <2>; +- #size-cells = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_system_bus>; +- }; +- +- smpctrl@59801000 { +- compatible = "socionext,uniphier-smpctrl"; +- reg = <0x59801000 0x400>; +- }; +- +- sdctrl@59810000 { +- compatible = "socionext,uniphier-ld20-sdctrl", +- "simple-mfd", "syscon"; +- reg = <0x59810000 0x400>; +- +- sd_clk: clock { +- compatible = "socionext,uniphier-ld20-sd-clock"; +- #clock-cells = <1>; +- }; +- +- sd_rst: reset { +- compatible = "socionext,uniphier-ld20-sd-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- perictrl@59820000 { +- compatible = "socionext,uniphier-ld20-perictrl", +- "simple-mfd", "syscon"; +- reg = <0x59820000 0x200>; +- +- peri_clk: clock { +- compatible = "socionext,uniphier-ld20-peri-clock"; +- #clock-cells = <1>; +- }; +- +- peri_rst: reset { +- compatible = "socionext,uniphier-ld20-peri-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- emmc: mmc@5a000000 { +- compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; +- reg = <0x5a000000 0x400>; +- interrupts = <0 78 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_emmc>; +- clocks = <&sys_clk 4>; +- resets = <&sys_rst 4>; +- bus-width = <8>; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- mmc-pwrseq = <&emmc_pwrseq>; +- cdns,phy-input-delay-legacy = <9>; +- cdns,phy-input-delay-mmc-highspeed = <2>; +- cdns,phy-input-delay-mmc-ddr = <3>; +- cdns,phy-dll-delay-sdclk = <21>; +- cdns,phy-dll-delay-sdclk-hsmmc = <21>; +- }; +- +- sd: mmc@5a400000 { +- compatible = "socionext,uniphier-sd-v3.1.1"; +- status = "disabled"; +- reg = <0x5a400000 0x800>; +- interrupts = <0 76 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sd>; +- clocks = <&sd_clk 0>; +- reset-names = "host"; +- resets = <&sd_rst 0>; +- bus-width = <4>; +- cap-sd-highspeed; +- }; +- +- soc_glue: soc-glue@5f800000 { +- compatible = "socionext,uniphier-ld20-soc-glue", +- "simple-mfd", "syscon"; +- reg = <0x5f800000 0x2000>; +- +- pinctrl: pinctrl { +- compatible = "socionext,uniphier-ld20-pinctrl"; +- }; +- }; +- +- soc-glue@5f900000 { +- compatible = "socionext,uniphier-ld20-soc-glue-debug", +- "simple-mfd"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x5f900000 0x2000>; +- +- efuse@100 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x100 0x28>; +- }; +- +- efuse@200 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x200 0x68>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* USB cells */ +- usb_rterm0: trim@54,4 { +- reg = <0x54 1>; +- bits = <4 2>; +- }; +- usb_rterm1: trim@55,4 { +- reg = <0x55 1>; +- bits = <4 2>; +- }; +- usb_rterm2: trim@58,4 { +- reg = <0x58 1>; +- bits = <4 2>; +- }; +- usb_rterm3: trim@59,4 { +- reg = <0x59 1>; +- bits = <4 2>; +- }; +- usb_sel_t0: trim@54,0 { +- reg = <0x54 1>; +- bits = <0 4>; +- }; +- usb_sel_t1: trim@55,0 { +- reg = <0x55 1>; +- bits = <0 4>; +- }; +- usb_sel_t2: trim@58,0 { +- reg = <0x58 1>; +- bits = <0 4>; +- }; +- usb_sel_t3: trim@59,0 { +- reg = <0x59 1>; +- bits = <0 4>; +- }; +- usb_hs_i0: trim@56,0 { +- reg = <0x56 1>; +- bits = <0 4>; +- }; +- usb_hs_i2: trim@5a,0 { +- reg = <0x5a 1>; +- bits = <0 4>; +- }; +- }; +- }; +- +- xdmac: dma-controller@5fc10000 { +- compatible = "socionext,uniphier-xdmac"; +- reg = <0x5fc10000 0x5300>; +- interrupts = <0 188 4>; +- dma-channels = <16>; +- #dma-cells = <2>; +- }; +- +- aidet: interrupt-controller@5fc20000 { +- compatible = "socionext,uniphier-ld20-aidet"; +- reg = <0x5fc20000 0x200>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gic: interrupt-controller@5fe00000 { +- compatible = "arm,gic-v3"; +- reg = <0x5fe00000 0x10000>, /* GICD */ +- <0x5fe80000 0x80000>; /* GICR */ +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = <1 9 4>; +- }; +- +- sysctrl@61840000 { +- compatible = "socionext,uniphier-ld20-sysctrl", +- "simple-mfd", "syscon"; +- reg = <0x61840000 0x10000>; +- +- sys_clk: clock { +- compatible = "socionext,uniphier-ld20-clock"; +- #clock-cells = <1>; +- }; +- +- sys_rst: reset { +- compatible = "socionext,uniphier-ld20-reset"; +- #reset-cells = <1>; +- }; +- +- watchdog { +- compatible = "socionext,uniphier-wdt"; +- }; +- +- pvtctl: pvtctl { +- compatible = "socionext,uniphier-ld20-thermal"; +- interrupts = <0 3 4>; +- #thermal-sensor-cells = <0>; +- socionext,tmod-calibration = <0x0f22 0x68ee>; +- }; +- }; +- +- eth: ethernet@65000000 { +- compatible = "socionext,uniphier-ld20-ave4"; +- status = "disabled"; +- reg = <0x65000000 0x8500>; +- interrupts = <0 66 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ether_rgmii>; +- clock-names = "ether"; +- clocks = <&sys_clk 6>; +- reset-names = "ether"; +- resets = <&sys_rst 6>; +- phy-mode = "rgmii-id"; +- local-mac-address = [00 00 00 00 00 00]; +- socionext,syscon-phy-mode = <&soc_glue 0>; +- +- mdio: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- usb: usb@65a00000 { +- compatible = "socionext,uniphier-dwc3", "snps,dwc3"; +- status = "disabled"; +- reg = <0x65a00000 0xcd00>; +- interrupt-names = "host"; +- interrupts = <0 134 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>, +- <&pinctrl_usb2>, <&pinctrl_usb3>; +- clock-names = "ref", "bus_early", "suspend"; +- clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; +- resets = <&usb_rst 15>; +- phys = <&usb_hsphy0>, <&usb_hsphy1>, +- <&usb_hsphy2>, <&usb_hsphy3>, +- <&usb_ssphy0>, <&usb_ssphy1>; +- dr_mode = "host"; +- }; +- +- usb-glue@65b00000 { +- compatible = "socionext,uniphier-ld20-dwc3-glue", +- "simple-mfd"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x65b00000 0x400>; +- +- usb_rst: reset@0 { +- compatible = "socionext,uniphier-ld20-usb3-reset"; +- reg = <0x0 0x4>; +- #reset-cells = <1>; +- clock-names = "link"; +- clocks = <&sys_clk 14>; +- reset-names = "link"; +- resets = <&sys_rst 14>; +- }; +- +- usb_vbus0: regulator@100 { +- compatible = "socionext,uniphier-ld20-usb3-regulator"; +- reg = <0x100 0x10>; +- clock-names = "link"; +- clocks = <&sys_clk 14>; +- reset-names = "link"; +- resets = <&sys_rst 14>; +- }; +- +- usb_vbus1: regulator@110 { +- compatible = "socionext,uniphier-ld20-usb3-regulator"; +- reg = <0x110 0x10>; +- clock-names = "link"; +- clocks = <&sys_clk 14>; +- reset-names = "link"; +- resets = <&sys_rst 14>; +- }; +- +- usb_vbus2: regulator@120 { +- compatible = "socionext,uniphier-ld20-usb3-regulator"; +- reg = <0x120 0x10>; +- clock-names = "link"; +- clocks = <&sys_clk 14>; +- reset-names = "link"; +- resets = <&sys_rst 14>; +- }; +- +- usb_vbus3: regulator@130 { +- compatible = "socionext,uniphier-ld20-usb3-regulator"; +- reg = <0x130 0x10>; +- clock-names = "link"; +- clocks = <&sys_clk 14>; +- reset-names = "link"; +- resets = <&sys_rst 14>; +- }; +- +- usb_hsphy0: hs-phy@200 { +- compatible = "socionext,uniphier-ld20-usb3-hsphy"; +- reg = <0x200 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy"; +- clocks = <&sys_clk 14>, <&sys_clk 16>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 14>, <&sys_rst 16>; +- vbus-supply = <&usb_vbus0>; +- nvmem-cell-names = "rterm", "sel_t", "hs_i"; +- nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, +- <&usb_hs_i0>; +- }; +- +- usb_hsphy1: hs-phy@210 { +- compatible = "socionext,uniphier-ld20-usb3-hsphy"; +- reg = <0x210 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy"; +- clocks = <&sys_clk 14>, <&sys_clk 16>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 14>, <&sys_rst 16>; +- vbus-supply = <&usb_vbus1>; +- nvmem-cell-names = "rterm", "sel_t", "hs_i"; +- nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, +- <&usb_hs_i0>; +- }; +- +- usb_hsphy2: hs-phy@220 { +- compatible = "socionext,uniphier-ld20-usb3-hsphy"; +- reg = <0x220 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy"; +- clocks = <&sys_clk 14>, <&sys_clk 17>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 14>, <&sys_rst 17>; +- vbus-supply = <&usb_vbus2>; +- nvmem-cell-names = "rterm", "sel_t", "hs_i"; +- nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, +- <&usb_hs_i2>; +- }; +- +- usb_hsphy3: hs-phy@230 { +- compatible = "socionext,uniphier-ld20-usb3-hsphy"; +- reg = <0x230 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy"; +- clocks = <&sys_clk 14>, <&sys_clk 17>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 14>, <&sys_rst 17>; +- vbus-supply = <&usb_vbus3>; +- nvmem-cell-names = "rterm", "sel_t", "hs_i"; +- nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, +- <&usb_hs_i2>; +- }; +- +- usb_ssphy0: ss-phy@300 { +- compatible = "socionext,uniphier-ld20-usb3-ssphy"; +- reg = <0x300 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy"; +- clocks = <&sys_clk 14>, <&sys_clk 18>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 14>, <&sys_rst 18>; +- vbus-supply = <&usb_vbus0>; +- }; +- +- usb_ssphy1: ss-phy@310 { +- compatible = "socionext,uniphier-ld20-usb3-ssphy"; +- reg = <0x310 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy"; +- clocks = <&sys_clk 14>, <&sys_clk 19>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 14>, <&sys_rst 19>; +- vbus-supply = <&usb_vbus1>; +- }; +- }; +- +- pcie: pcie@66000000 { +- compatible = "socionext,uniphier-pcie", "snps,dw-pcie"; +- status = "disabled"; +- reg-names = "dbi", "link", "config"; +- reg = <0x66000000 0x1000>, <0x66010000 0x10000>, +- <0x2fff0000 0x10000>; +- #address-cells = <3>; +- #size-cells = <2>; +- clocks = <&sys_clk 24>; +- resets = <&sys_rst 24>; +- num-lanes = <1>; +- num-viewport = <1>; +- bus-range = <0x0 0xff>; +- device_type = "pci"; +- ranges = +- /* downstream I/O */ +- <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, +- /* non-prefetchable memory */ +- <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; +- #interrupt-cells = <1>; +- interrupt-names = "dma", "msi"; +- interrupts = <0 224 4>, <0 225 4>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ +- <0 0 0 2 &pcie_intc 1>, /* INTB */ +- <0 0 0 3 &pcie_intc 2>, /* INTC */ +- <0 0 0 4 &pcie_intc 3>; /* INTD */ +- phy-names = "pcie-phy"; +- phys = <&pcie_phy>; +- +- pcie_intc: legacy-interrupt-controller { +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&gic>; +- interrupts = <0 226 4>; +- }; +- }; +- +- pcie_phy: phy@66038000 { +- compatible = "socionext,uniphier-ld20-pcie-phy"; +- reg = <0x66038000 0x4000>; +- #phy-cells = <0>; +- clock-names = "link"; +- clocks = <&sys_clk 24>; +- reset-names = "link"; +- resets = <&sys_rst 24>; +- socionext,syscon = <&soc_glue>; +- }; +- +- nand: nand-controller@68000000 { +- compatible = "socionext,uniphier-denali-nand-v5b"; +- status = "disabled"; +- reg-names = "nand_data", "denali_reg"; +- reg = <0x68000000 0x20>, <0x68100000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 65 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nand>; +- clock-names = "nand", "nand_x", "ecc"; +- clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; +- reset-names = "nand", "reg"; +- resets = <&sys_rst 2>, <&sys_rst 2>; +- }; +- }; +-}; +- +-#include "uniphier-pinctrl.dtsi" +- +-&pinctrl_aout1 { +- drive-strength = <4>; /* default: 3.5mA */ +- +- ao1dacck { +- pins = "AO1DACCK"; +- drive-strength = <5>; /* 5mA */ +- }; +-}; +- +-&pinctrl_aoutiec1 { +- drive-strength = <4>; /* default: 3.5mA */ +- +- ao1arc { +- pins = "AO1ARC"; +- drive-strength = <11>; /* 11mA */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-pinctrl.dtsi b/scripts/dtc/include-prefixes/arm64/socionext/uniphier-pinctrl.dtsi +deleted file mode 100644 +index 9caabbb8bae3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-pinctrl.dtsi ++++ /dev/null +@@ -1 +0,0 @@ +-#include +diff --git a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-pxs3-ref.dts b/scripts/dtc/include-prefixes/arm64/socionext/uniphier-pxs3-ref.dts +deleted file mode 100644 +index 086040306fb3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-pxs3-ref.dts ++++ /dev/null +@@ -1,154 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier PXs3 Reference Board +-// +-// Copyright (C) 2017 Socionext Inc. +-// Author: Masahiro Yamada +- +-/dts-v1/; +-#include "uniphier-pxs3.dtsi" +-#include "uniphier-support-card.dtsi" +- +-/ { +- model = "UniPhier PXs3 Reference Board"; +- compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serialsc; +- serial2 = &serial2; +- serial3 = &serial3; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c6 = &i2c6; +- spi0 = &spi0; +- spi1 = &spi1; +- ethernet0 = ð0; +- ethernet1 = ð1; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0 0x80000000 0 0xa0000000>; +- }; +-}; +- +-ðsc { +- interrupts = <4 8>; +-}; +- +-&serialsc { +- interrupts = <4 8>; +-}; +- +-&spi0 { +- status = "okay"; +-}; +- +-&spi1 { +- status = "okay"; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&serial2 { +- status = "okay"; +-}; +- +-&serial3 { +- status = "okay"; +-}; +- +-&gpio { +- xirq4 { +- gpio-hog; +- gpios = ; +- input; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&sd { +- status = "okay"; +-}; +- +-ð0 { +- status = "okay"; +- phy-handle = <ðphy0>; +-}; +- +-&mdio0 { +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-ð1 { +- status = "okay"; +- phy-handle = <ðphy1>; +-}; +- +-&mdio1 { +- ethphy1: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&nand { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- }; +-}; +- +-&pinctrl_ether_rgmii { +- tx { +- pins = "RGMII0_TXCLK", "RGMII0_TXD0", "RGMII0_TXD1", +- "RGMII0_TXD2", "RGMII0_TXD3", "RGMII0_TXCTL"; +- drive-strength = <9>; +- }; +-}; +- +-&pinctrl_ether1_rgmii { +- tx { +- pins = "RGMII1_TXCLK", "RGMII1_TXD0", "RGMII1_TXD1", +- "RGMII1_TXD2", "RGMII1_TXD3", "RGMII1_TXCTL"; +- drive-strength = <9>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-pxs3.dtsi b/scripts/dtc/include-prefixes/arm64/socionext/uniphier-pxs3.dtsi +deleted file mode 100644 +index be97da132258..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-pxs3.dtsi ++++ /dev/null +@@ -1,861 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR MIT +-// +-// Device Tree Source for UniPhier PXs3 SoC +-// +-// Copyright (C) 2017 Socionext Inc. +-// Author: Masahiro Yamada +- +-#include +-#include +-#include +- +-/ { +- compatible = "socionext,uniphier-pxs3"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&gic>; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- core2 { +- cpu = <&cpu2>; +- }; +- core3 { +- cpu = <&cpu3>; +- }; +- }; +- }; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0 0x000>; +- clocks = <&sys_clk 33>; +- enable-method = "psci"; +- operating-points-v2 = <&cluster0_opp>; +- #cooling-cells = <2>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0 0x001>; +- clocks = <&sys_clk 33>; +- enable-method = "psci"; +- operating-points-v2 = <&cluster0_opp>; +- #cooling-cells = <2>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0 0x002>; +- clocks = <&sys_clk 33>; +- enable-method = "psci"; +- operating-points-v2 = <&cluster0_opp>; +- #cooling-cells = <2>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0 0x003>; +- clocks = <&sys_clk 33>; +- enable-method = "psci"; +- operating-points-v2 = <&cluster0_opp>; +- #cooling-cells = <2>; +- }; +- }; +- +- cluster0_opp: opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-250000000 { +- opp-hz = /bits/ 64 <250000000>; +- clock-latency-ns = <300>; +- }; +- opp-325000000 { +- opp-hz = /bits/ 64 <325000000>; +- clock-latency-ns = <300>; +- }; +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- clock-latency-ns = <300>; +- }; +- opp-650000000 { +- opp-hz = /bits/ 64 <650000000>; +- clock-latency-ns = <300>; +- }; +- opp-666667000 { +- opp-hz = /bits/ 64 <666667000>; +- clock-latency-ns = <300>; +- }; +- opp-866667000 { +- opp-hz = /bits/ 64 <866667000>; +- clock-latency-ns = <300>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- clock-latency-ns = <300>; +- }; +- opp-1300000000 { +- opp-hz = /bits/ 64 <1300000000>; +- clock-latency-ns = <300>; +- }; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- clocks { +- refclk: ref { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = <1 13 4>, +- <1 14 4>, +- <1 11 4>, +- <1 10 4>; +- }; +- +- thermal-zones { +- cpu-thermal { +- polling-delay-passive = <250>; /* 250ms */ +- polling-delay = <1000>; /* 1000ms */ +- thermal-sensors = <&pvtctl>; +- +- trips { +- cpu_crit: cpu-crit { +- temperature = <110000>; /* 110C */ +- hysteresis = <2000>; +- type = "critical"; +- }; +- cpu_alert: cpu-alert { +- temperature = <100000>; /* 100C */ +- hysteresis = <2000>; +- type = "passive"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- secure-memory@81000000 { +- reg = <0x0 0x81000000 0x0 0x01000000>; +- no-map; +- }; +- }; +- +- soc@0 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0 0xffffffff>; +- +- spi0: spi@54006000 { +- compatible = "socionext,uniphier-scssi"; +- status = "disabled"; +- reg = <0x54006000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 39 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi0>; +- clocks = <&peri_clk 11>; +- resets = <&peri_rst 11>; +- }; +- +- spi1: spi@54006100 { +- compatible = "socionext,uniphier-scssi"; +- status = "disabled"; +- reg = <0x54006100 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 216 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_spi1>; +- clocks = <&peri_clk 12>; +- resets = <&peri_rst 12>; +- }; +- +- serial0: serial@54006800 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006800 0x40>; +- interrupts = <0 33 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +- clocks = <&peri_clk 0>; +- resets = <&peri_rst 0>; +- }; +- +- serial1: serial@54006900 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006900 0x40>; +- interrupts = <0 35 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- clocks = <&peri_clk 1>; +- resets = <&peri_rst 1>; +- }; +- +- serial2: serial@54006a00 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006a00 0x40>; +- interrupts = <0 37 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- clocks = <&peri_clk 2>; +- resets = <&peri_rst 2>; +- }; +- +- serial3: serial@54006b00 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006b00 0x40>; +- interrupts = <0 177 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart3>; +- clocks = <&peri_clk 3>; +- resets = <&peri_rst 3>; +- }; +- +- gpio: gpio@55000000 { +- compatible = "socionext,uniphier-gpio"; +- reg = <0x55000000 0x200>; +- interrupt-parent = <&aidet>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 0 0>, +- <&pinctrl 104 0 0>, +- <&pinctrl 168 0 0>; +- gpio-ranges-group-names = "gpio_range0", +- "gpio_range1", +- "gpio_range2"; +- ngpios = <286>; +- socionext,interrupt-ranges = <0 48 16>, <16 154 5>, +- <21 217 3>; +- }; +- +- i2c0: i2c@58780000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58780000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 41 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c0>; +- clocks = <&peri_clk 4>; +- resets = <&peri_rst 4>; +- clock-frequency = <100000>; +- }; +- +- i2c1: i2c@58781000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58781000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 42 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- clocks = <&peri_clk 5>; +- resets = <&peri_rst 5>; +- clock-frequency = <100000>; +- }; +- +- i2c2: i2c@58782000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58782000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 43 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- clocks = <&peri_clk 6>; +- resets = <&peri_rst 6>; +- clock-frequency = <100000>; +- }; +- +- i2c3: i2c@58783000 { +- compatible = "socionext,uniphier-fi2c"; +- status = "disabled"; +- reg = <0x58783000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 44 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c3>; +- clocks = <&peri_clk 7>; +- resets = <&peri_rst 7>; +- clock-frequency = <100000>; +- }; +- +- /* chip-internal connection for HDMI */ +- i2c6: i2c@58786000 { +- compatible = "socionext,uniphier-fi2c"; +- reg = <0x58786000 0x80>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 26 4>; +- clocks = <&peri_clk 10>; +- resets = <&peri_rst 10>; +- clock-frequency = <400000>; +- }; +- +- system_bus: system-bus@58c00000 { +- compatible = "socionext,uniphier-system-bus"; +- status = "disabled"; +- reg = <0x58c00000 0x400>; +- #address-cells = <2>; +- #size-cells = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_system_bus>; +- }; +- +- smpctrl@59801000 { +- compatible = "socionext,uniphier-smpctrl"; +- reg = <0x59801000 0x400>; +- }; +- +- sdctrl@59810000 { +- compatible = "socionext,uniphier-pxs3-sdctrl", +- "simple-mfd", "syscon"; +- reg = <0x59810000 0x400>; +- +- sd_clk: clock { +- compatible = "socionext,uniphier-pxs3-sd-clock"; +- #clock-cells = <1>; +- }; +- +- sd_rst: reset { +- compatible = "socionext,uniphier-pxs3-sd-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- perictrl@59820000 { +- compatible = "socionext,uniphier-pxs3-perictrl", +- "simple-mfd", "syscon"; +- reg = <0x59820000 0x200>; +- +- peri_clk: clock { +- compatible = "socionext,uniphier-pxs3-peri-clock"; +- #clock-cells = <1>; +- }; +- +- peri_rst: reset { +- compatible = "socionext,uniphier-pxs3-peri-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- emmc: mmc@5a000000 { +- compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; +- reg = <0x5a000000 0x400>; +- interrupts = <0 78 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_emmc>; +- clocks = <&sys_clk 4>; +- resets = <&sys_rst 4>; +- bus-width = <8>; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- mmc-pwrseq = <&emmc_pwrseq>; +- cdns,phy-input-delay-legacy = <9>; +- cdns,phy-input-delay-mmc-highspeed = <2>; +- cdns,phy-input-delay-mmc-ddr = <3>; +- cdns,phy-dll-delay-sdclk = <21>; +- cdns,phy-dll-delay-sdclk-hsmmc = <21>; +- }; +- +- sd: mmc@5a400000 { +- compatible = "socionext,uniphier-sd-v3.1.1"; +- status = "disabled"; +- reg = <0x5a400000 0x800>; +- interrupts = <0 76 4>; +- pinctrl-names = "default", "uhs"; +- pinctrl-0 = <&pinctrl_sd>; +- pinctrl-1 = <&pinctrl_sd_uhs>; +- clocks = <&sd_clk 0>; +- reset-names = "host"; +- resets = <&sd_rst 0>; +- bus-width = <4>; +- cap-sd-highspeed; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- }; +- +- soc_glue: soc-glue@5f800000 { +- compatible = "socionext,uniphier-pxs3-soc-glue", +- "simple-mfd", "syscon"; +- reg = <0x5f800000 0x2000>; +- +- pinctrl: pinctrl { +- compatible = "socionext,uniphier-pxs3-pinctrl"; +- }; +- }; +- +- soc-glue@5f900000 { +- compatible = "socionext,uniphier-pxs3-soc-glue-debug", +- "simple-mfd"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x5f900000 0x2000>; +- +- efuse@100 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x100 0x28>; +- }; +- +- efuse@200 { +- compatible = "socionext,uniphier-efuse"; +- reg = <0x200 0x68>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* USB cells */ +- usb_rterm0: trim@54,4 { +- reg = <0x54 1>; +- bits = <4 2>; +- }; +- usb_rterm1: trim@55,4 { +- reg = <0x55 1>; +- bits = <4 2>; +- }; +- usb_rterm2: trim@58,4 { +- reg = <0x58 1>; +- bits = <4 2>; +- }; +- usb_rterm3: trim@59,4 { +- reg = <0x59 1>; +- bits = <4 2>; +- }; +- usb_sel_t0: trim@54,0 { +- reg = <0x54 1>; +- bits = <0 4>; +- }; +- usb_sel_t1: trim@55,0 { +- reg = <0x55 1>; +- bits = <0 4>; +- }; +- usb_sel_t2: trim@58,0 { +- reg = <0x58 1>; +- bits = <0 4>; +- }; +- usb_sel_t3: trim@59,0 { +- reg = <0x59 1>; +- bits = <0 4>; +- }; +- usb_hs_i0: trim@56,0 { +- reg = <0x56 1>; +- bits = <0 4>; +- }; +- usb_hs_i2: trim@5a,0 { +- reg = <0x5a 1>; +- bits = <0 4>; +- }; +- }; +- }; +- +- xdmac: dma-controller@5fc10000 { +- compatible = "socionext,uniphier-xdmac"; +- reg = <0x5fc10000 0x5300>; +- interrupts = <0 188 4>; +- dma-channels = <16>; +- #dma-cells = <2>; +- }; +- +- aidet: interrupt-controller@5fc20000 { +- compatible = "socionext,uniphier-pxs3-aidet"; +- reg = <0x5fc20000 0x200>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gic: interrupt-controller@5fe00000 { +- compatible = "arm,gic-v3"; +- reg = <0x5fe00000 0x10000>, /* GICD */ +- <0x5fe80000 0x80000>; /* GICR */ +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = <1 9 4>; +- }; +- +- sysctrl@61840000 { +- compatible = "socionext,uniphier-pxs3-sysctrl", +- "simple-mfd", "syscon"; +- reg = <0x61840000 0x10000>; +- +- sys_clk: clock { +- compatible = "socionext,uniphier-pxs3-clock"; +- #clock-cells = <1>; +- }; +- +- sys_rst: reset { +- compatible = "socionext,uniphier-pxs3-reset"; +- #reset-cells = <1>; +- }; +- +- watchdog { +- compatible = "socionext,uniphier-wdt"; +- }; +- +- pvtctl: pvtctl { +- compatible = "socionext,uniphier-pxs3-thermal"; +- interrupts = <0 3 4>; +- #thermal-sensor-cells = <0>; +- socionext,tmod-calibration = <0x0f22 0x68ee>; +- }; +- }; +- +- eth0: ethernet@65000000 { +- compatible = "socionext,uniphier-pxs3-ave4"; +- status = "disabled"; +- reg = <0x65000000 0x8500>; +- interrupts = <0 66 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ether_rgmii>; +- clock-names = "ether"; +- clocks = <&sys_clk 6>; +- reset-names = "ether"; +- resets = <&sys_rst 6>; +- phy-mode = "rgmii-id"; +- local-mac-address = [00 00 00 00 00 00]; +- socionext,syscon-phy-mode = <&soc_glue 0>; +- +- mdio0: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- eth1: ethernet@65200000 { +- compatible = "socionext,uniphier-pxs3-ave4"; +- status = "disabled"; +- reg = <0x65200000 0x8500>; +- interrupts = <0 67 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_ether1_rgmii>; +- clock-names = "ether"; +- clocks = <&sys_clk 7>; +- reset-names = "ether"; +- resets = <&sys_rst 7>; +- phy-mode = "rgmii-id"; +- local-mac-address = [00 00 00 00 00 00]; +- socionext,syscon-phy-mode = <&soc_glue 1>; +- +- mdio1: mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- usb0: usb@65a00000 { +- compatible = "socionext,uniphier-dwc3", "snps,dwc3"; +- status = "disabled"; +- reg = <0x65a00000 0xcd00>; +- interrupt-names = "host", "peripheral"; +- interrupts = <0 134 4>, <0 135 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; +- clock-names = "ref", "bus_early", "suspend"; +- clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; +- resets = <&usb0_rst 15>; +- phys = <&usb0_hsphy0>, <&usb0_hsphy1>, +- <&usb0_ssphy0>, <&usb0_ssphy1>; +- dr_mode = "host"; +- }; +- +- usb-glue@65b00000 { +- compatible = "socionext,uniphier-pxs3-dwc3-glue", +- "simple-mfd"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x65b00000 0x400>; +- +- usb0_rst: reset@0 { +- compatible = "socionext,uniphier-pxs3-usb3-reset"; +- reg = <0x0 0x4>; +- #reset-cells = <1>; +- clock-names = "link"; +- clocks = <&sys_clk 12>; +- reset-names = "link"; +- resets = <&sys_rst 12>; +- }; +- +- usb0_vbus0: regulator@100 { +- compatible = "socionext,uniphier-pxs3-usb3-regulator"; +- reg = <0x100 0x10>; +- clock-names = "link"; +- clocks = <&sys_clk 12>; +- reset-names = "link"; +- resets = <&sys_rst 12>; +- }; +- +- usb0_vbus1: regulator@110 { +- compatible = "socionext,uniphier-pxs3-usb3-regulator"; +- reg = <0x110 0x10>; +- clock-names = "link"; +- clocks = <&sys_clk 12>; +- reset-names = "link"; +- resets = <&sys_rst 12>; +- }; +- +- usb0_hsphy0: hs-phy@200 { +- compatible = "socionext,uniphier-pxs3-usb3-hsphy"; +- reg = <0x200 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy"; +- clocks = <&sys_clk 12>, <&sys_clk 16>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 12>, <&sys_rst 16>; +- vbus-supply = <&usb0_vbus0>; +- nvmem-cell-names = "rterm", "sel_t", "hs_i"; +- nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, +- <&usb_hs_i0>; +- }; +- +- usb0_hsphy1: hs-phy@210 { +- compatible = "socionext,uniphier-pxs3-usb3-hsphy"; +- reg = <0x210 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy"; +- clocks = <&sys_clk 12>, <&sys_clk 16>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 12>, <&sys_rst 16>; +- vbus-supply = <&usb0_vbus1>; +- nvmem-cell-names = "rterm", "sel_t", "hs_i"; +- nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, +- <&usb_hs_i0>; +- }; +- +- usb0_ssphy0: ss-phy@300 { +- compatible = "socionext,uniphier-pxs3-usb3-ssphy"; +- reg = <0x300 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy"; +- clocks = <&sys_clk 12>, <&sys_clk 17>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 12>, <&sys_rst 17>; +- vbus-supply = <&usb0_vbus0>; +- }; +- +- usb0_ssphy1: ss-phy@310 { +- compatible = "socionext,uniphier-pxs3-usb3-ssphy"; +- reg = <0x310 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy"; +- clocks = <&sys_clk 12>, <&sys_clk 18>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 12>, <&sys_rst 18>; +- vbus-supply = <&usb0_vbus1>; +- }; +- }; +- +- usb1: usb@65c00000 { +- compatible = "socionext,uniphier-dwc3", "snps,dwc3"; +- status = "disabled"; +- reg = <0x65c00000 0xcd00>; +- interrupt-names = "host", "peripheral"; +- interrupts = <0 137 4>, <0 138 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; +- clock-names = "ref", "bus_early", "suspend"; +- clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>; +- resets = <&usb1_rst 15>; +- phys = <&usb1_hsphy0>, <&usb1_hsphy1>, +- <&usb1_ssphy0>; +- dr_mode = "host"; +- }; +- +- usb-glue@65d00000 { +- compatible = "socionext,uniphier-pxs3-dwc3-glue", +- "simple-mfd"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x65d00000 0x400>; +- +- usb1_rst: reset@0 { +- compatible = "socionext,uniphier-pxs3-usb3-reset"; +- reg = <0x0 0x4>; +- #reset-cells = <1>; +- clock-names = "link"; +- clocks = <&sys_clk 13>; +- reset-names = "link"; +- resets = <&sys_rst 13>; +- }; +- +- usb1_vbus0: regulator@100 { +- compatible = "socionext,uniphier-pxs3-usb3-regulator"; +- reg = <0x100 0x10>; +- clock-names = "link"; +- clocks = <&sys_clk 13>; +- reset-names = "link"; +- resets = <&sys_rst 13>; +- }; +- +- usb1_vbus1: regulator@110 { +- compatible = "socionext,uniphier-pxs3-usb3-regulator"; +- reg = <0x110 0x10>; +- clock-names = "link"; +- clocks = <&sys_clk 13>; +- reset-names = "link"; +- resets = <&sys_rst 13>; +- }; +- +- usb1_hsphy0: hs-phy@200 { +- compatible = "socionext,uniphier-pxs3-usb3-hsphy"; +- reg = <0x200 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy", "phy-ext"; +- clocks = <&sys_clk 13>, <&sys_clk 20>, +- <&sys_clk 14>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 13>, <&sys_rst 20>; +- vbus-supply = <&usb1_vbus0>; +- nvmem-cell-names = "rterm", "sel_t", "hs_i"; +- nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, +- <&usb_hs_i2>; +- }; +- +- usb1_hsphy1: hs-phy@210 { +- compatible = "socionext,uniphier-pxs3-usb3-hsphy"; +- reg = <0x210 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy", "phy-ext"; +- clocks = <&sys_clk 13>, <&sys_clk 20>, +- <&sys_clk 14>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 13>, <&sys_rst 20>; +- vbus-supply = <&usb1_vbus1>; +- nvmem-cell-names = "rterm", "sel_t", "hs_i"; +- nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, +- <&usb_hs_i2>; +- }; +- +- usb1_ssphy0: ss-phy@300 { +- compatible = "socionext,uniphier-pxs3-usb3-ssphy"; +- reg = <0x300 0x10>; +- #phy-cells = <0>; +- clock-names = "link", "phy", "phy-ext"; +- clocks = <&sys_clk 13>, <&sys_clk 21>, +- <&sys_clk 14>; +- reset-names = "link", "phy"; +- resets = <&sys_rst 13>, <&sys_rst 21>; +- vbus-supply = <&usb1_vbus0>; +- }; +- }; +- +- pcie: pcie@66000000 { +- compatible = "socionext,uniphier-pcie", "snps,dw-pcie"; +- status = "disabled"; +- reg-names = "dbi", "link", "config"; +- reg = <0x66000000 0x1000>, <0x66010000 0x10000>, +- <0x2fff0000 0x10000>; +- #address-cells = <3>; +- #size-cells = <2>; +- clocks = <&sys_clk 24>; +- resets = <&sys_rst 24>; +- num-lanes = <1>; +- num-viewport = <1>; +- bus-range = <0x0 0xff>; +- device_type = "pci"; +- ranges = +- /* downstream I/O */ +- <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, +- /* non-prefetchable memory */ +- <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; +- #interrupt-cells = <1>; +- interrupt-names = "dma", "msi"; +- interrupts = <0 224 4>, <0 225 4>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ +- <0 0 0 2 &pcie_intc 1>, /* INTB */ +- <0 0 0 3 &pcie_intc 2>, /* INTC */ +- <0 0 0 4 &pcie_intc 3>; /* INTD */ +- phy-names = "pcie-phy"; +- phys = <&pcie_phy>; +- +- pcie_intc: legacy-interrupt-controller { +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&gic>; +- interrupts = <0 226 4>; +- }; +- }; +- +- pcie_phy: phy@66038000 { +- compatible = "socionext,uniphier-pxs3-pcie-phy"; +- reg = <0x66038000 0x4000>; +- #phy-cells = <0>; +- clock-names = "link"; +- clocks = <&sys_clk 24>; +- reset-names = "link"; +- resets = <&sys_rst 24>; +- socionext,syscon = <&soc_glue>; +- }; +- +- nand: nand-controller@68000000 { +- compatible = "socionext,uniphier-denali-nand-v5b"; +- status = "disabled"; +- reg-names = "nand_data", "denali_reg"; +- reg = <0x68000000 0x20>, <0x68100000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 65 4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nand>; +- clock-names = "nand", "nand_x", "ecc"; +- clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; +- reset-names = "nand", "reg"; +- resets = <&sys_rst 2>, <&sys_rst 2>; +- }; +- }; +-}; +- +-#include "uniphier-pinctrl.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ref-daughter.dtsi b/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ref-daughter.dtsi +deleted file mode 100644 +index e66d999d9f5d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ref-daughter.dtsi ++++ /dev/null +@@ -1 +0,0 @@ +-#include +diff --git a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-support-card.dtsi b/scripts/dtc/include-prefixes/arm64/socionext/uniphier-support-card.dtsi +deleted file mode 100644 +index 28c5b4ed1d95..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/socionext/uniphier-support-card.dtsi ++++ /dev/null +@@ -1 +0,0 @@ +-#include +diff --git a/scripts/dtc/include-prefixes/arm64/sprd/Makefile b/scripts/dtc/include-prefixes/arm64/sprd/Makefile +deleted file mode 100644 +index f4f1f5148cc2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/sprd/Makefile ++++ /dev/null +@@ -1,4 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \ +- sp9860g-1h10.dtb \ +- sp9863a-1h10.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/sprd/sc2731.dtsi b/scripts/dtc/include-prefixes/arm64/sprd/sc2731.dtsi +deleted file mode 100644 +index e15409f55f43..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/sprd/sc2731.dtsi ++++ /dev/null +@@ -1,258 +0,0 @@ +-/* +- * Spreadtrum SC2731 PMIC dts file +- * +- * Copyright (C) 2018, Spreadtrum Communications Inc. +- * +- * SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- */ +- +-&adi_bus { +- sc2731_pmic: pmic@0 { +- compatible = "sprd,sc2731"; +- reg = <0>; +- spi-max-frequency = <26000000>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- charger@0 { +- compatible = "sprd,sc2731-charger"; +- reg = <0x0>; +- monitored-battery = <&bat>; +- }; +- +- led-controller@200 { +- compatible = "sprd,sc2731-bltc"; +- reg = <0x200>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- led@0 { +- label = "red"; +- reg = <0x0>; +- }; +- +- led@1 { +- label = "green"; +- reg = <0x1>; +- }; +- +- led@2 { +- label = "blue"; +- reg = <0x2>; +- }; +- }; +- +- rtc@280 { +- compatible = "sprd,sc2731-rtc"; +- reg = <0x280>; +- interrupt-parent = <&sc2731_pmic>; +- interrupts = <2>; +- }; +- +- pmic_eic: gpio@300 { +- compatible = "sprd,sc2731-eic"; +- reg = <0x300>; +- interrupt-parent = <&sc2731_pmic>; +- interrupts = <5>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- efuse@380 { +- compatible = "sprd,sc2731-efuse"; +- reg = <0x380>; +- #address-cells = <1>; +- #size-cells = <1>; +- hwlocks = <&hwlock 12>; +- +- fgu_calib: calib@6 { +- reg = <0x6 0x2>; +- bits = <0 9>; +- }; +- +- adc_big_scale: calib@24 { +- reg = <0x24 0x2>; +- }; +- +- adc_small_scale: calib@26 { +- reg = <0x26 0x2>; +- }; +- }; +- +- pmic_adc: adc@480 { +- compatible = "sprd,sc2731-adc"; +- reg = <0x480>; +- interrupt-parent = <&sc2731_pmic>; +- interrupts = <0>; +- #io-channel-cells = <1>; +- hwlocks = <&hwlock 4>; +- nvmem-cell-names = "big_scale_calib", "small_scale_calib"; +- nvmem-cells = <&adc_big_scale>, <&adc_small_scale>; +- }; +- +- fgu@a00 { +- compatible = "sprd,sc2731-fgu"; +- reg = <0xa00>; +- bat-detect-gpio = <&pmic_eic 9 GPIO_ACTIVE_HIGH>; +- io-channels = <&pmic_adc 3>, <&pmic_adc 6>; +- io-channel-names = "bat-temp", "charge-vol"; +- monitored-battery = <&bat>; +- nvmem-cell-names = "fgu_calib"; +- nvmem-cells = <&fgu_calib>; +- interrupt-parent = <&sc2731_pmic>; +- interrupts = <4>; +- }; +- +- vibrator@ec8 { +- compatible = "sprd,sc2731-vibrator"; +- reg = <0xec8>; +- }; +- +- regulators { +- compatible = "sprd,sc2731-regulator"; +- +- vddarm0: BUCK_CPU0 { +- regulator-name = "vddarm0"; +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1996875>; +- regulator-ramp-delay = <25000>; +- regulator-always-on; +- }; +- +- vddarm1: BUCK_CPU1 { +- regulator-name = "vddarm1"; +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <1996875>; +- regulator-ramp-delay = <25000>; +- regulator-always-on; +- }; +- +- dcdcrf: BUCK_RF { +- regulator-name = "dcdcrf"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <2196875>; +- regulator-ramp-delay = <25000>; +- regulator-enable-ramp-delay = <100>; +- regulator-always-on; +- }; +- +- vddcama0: LDO_CAMA0 { +- regulator-name = "vddcama0"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3750000>; +- regulator-enable-ramp-delay = <100>; +- }; +- +- vddcama1: LDO_CAMA1 { +- regulator-name = "vddcama1"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3750000>; +- regulator-enable-ramp-delay = <100>; +- regulator-ramp-delay = <25000>; +- }; +- +- vddcammot: LDO_CAMMOT { +- regulator-name = "vddcammot"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3750000>; +- regulator-enable-ramp-delay = <100>; +- regulator-ramp-delay = <25000>; +- }; +- +- vddvldo: LDO_VLDO { +- regulator-name = "vddvldo"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3750000>; +- regulator-enable-ramp-delay = <100>; +- regulator-ramp-delay = <25000>; +- }; +- +- vddemmccore: LDO_EMMCCORE { +- regulator-name = "vddemmccore"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3750000>; +- regulator-enable-ramp-delay = <100>; +- regulator-ramp-delay = <25000>; +- regulator-boot-on; +- }; +- +- vddsdcore: LDO_SDCORE { +- regulator-name = "vddsdcore"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3750000>; +- regulator-enable-ramp-delay = <100>; +- regulator-ramp-delay = <25000>; +- }; +- +- vddsdio: LDO_SDIO { +- regulator-name = "vddsdio"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3750000>; +- regulator-enable-ramp-delay = <100>; +- regulator-ramp-delay = <25000>; +- }; +- +- vddwifipa: LDO_WIFIPA { +- regulator-name = "vddwifipa"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3750000>; +- regulator-enable-ramp-delay = <100>; +- regulator-ramp-delay = <25000>; +- }; +- +- vddusb33: LDO_USB33 { +- regulator-name = "vddusb33"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <3750000>; +- regulator-enable-ramp-delay = <100>; +- regulator-ramp-delay = <25000>; +- }; +- +- vddcamd0: LDO_CAMD0 { +- regulator-name = "vddcamd0"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1793750>; +- regulator-enable-ramp-delay = <100>; +- regulator-ramp-delay = <25000>; +- }; +- +- vddcamd1: LDO_CAMD1 { +- regulator-name = "vddcamd1"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1793750>; +- regulator-enable-ramp-delay = <100>; +- regulator-ramp-delay = <25000>; +- }; +- +- vddcon: LDO_CON { +- regulator-name = "vddcon"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1793750>; +- regulator-enable-ramp-delay = <100>; +- regulator-ramp-delay = <25000>; +- }; +- +- vddcamio: LDO_CAMIO { +- regulator-name = "vddcamio"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1793750>; +- regulator-enable-ramp-delay = <100>; +- regulator-ramp-delay = <25000>; +- }; +- +- vddsram: LDO_SRAM { +- regulator-name = "vddsram"; +- regulator-min-microvolt = <1000000>; +- regulator-max-microvolt = <1793750>; +- regulator-enable-ramp-delay = <100>; +- regulator-ramp-delay = <25000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/sprd/sc9836-openphone.dts b/scripts/dtc/include-prefixes/arm64/sprd/sc9836-openphone.dts +deleted file mode 100644 +index e5657c35cd10..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/sprd/sc9836-openphone.dts ++++ /dev/null +@@ -1,49 +0,0 @@ +-/* +- * Spreadtrum SC9836 openphone board DTS file +- * +- * Copyright (C) 2014, Spreadtrum Communications Inc. +- * +- * This file is licensed under a dual GPLv2 or X11 license. +- */ +- +-/dts-v1/; +- +-#include "sc9836.dtsi" +- +-/ { +- model = "Spreadtrum SC9836 Openphone Board"; +- +- compatible = "sprd,sc9836-openphone", "sprd,sc9836"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0 0x80000000 0 0x20000000>; +- }; +- +- chosen { +- stdout-path = "serial1:115200n8"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/sprd/sc9836.dtsi b/scripts/dtc/include-prefixes/arm64/sprd/sc9836.dtsi +deleted file mode 100644 +index 231436be0e3f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/sprd/sc9836.dtsi ++++ /dev/null +@@ -1,224 +0,0 @@ +-/* +- * Spreadtrum SC9836 SoC DTS file +- * +- * Copyright (C) 2014, Spreadtrum Communications Inc. +- * +- * This file is licensed under a dual GPLv2 or X11 license. +- */ +- +-#include "sharkl64.dtsi" +-#include +- +-/ { +- compatible = "sprd,sc9836"; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; +- enable-method = "psci"; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x2>; +- enable-method = "psci"; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x3>; +- enable-method = "psci"; +- }; +- }; +- +- etf@10003000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0x10003000 0 0x1000>; +- clocks = <&clk26mhz>; +- clock-names = "apb_pclk"; +- in-ports { +- port { +- etf_in: endpoint { +- remote-endpoint = <&funnel_out_port0>; +- }; +- }; +- }; +- }; +- +- funnel@10001000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x10001000 0 0x1000>; +- clocks = <&clk26mhz>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- funnel_out_port0: endpoint { +- remote-endpoint = <&etf_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- funnel_in_port0: endpoint { +- remote-endpoint = <&etm0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- funnel_in_port1: endpoint { +- remote-endpoint = <&etm1_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- funnel_in_port2: endpoint { +- remote-endpoint = <&etm2_out>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- funnel_in_port3: endpoint { +- remote-endpoint = <&etm3_out>; +- }; +- }; +- +- port@4 { +- reg = <4>; +- funnel_in_port4: endpoint { +- remote-endpoint = <&stm_out>; +- }; +- }; +- /* Other input ports aren't connected to anyone */ +- }; +- }; +- +- etm@10440000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x10440000 0 0x1000>; +- +- cpu = <&cpu0>; +- clocks = <&clk26mhz>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- etm0_out: endpoint { +- remote-endpoint = <&funnel_in_port0>; +- }; +- }; +- }; +- }; +- +- etm@10540000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x10540000 0 0x1000>; +- +- cpu = <&cpu1>; +- clocks = <&clk26mhz>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- etm1_out: endpoint { +- remote-endpoint = <&funnel_in_port1>; +- }; +- }; +- }; +- }; +- +- etm@10640000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x10640000 0 0x1000>; +- +- cpu = <&cpu2>; +- clocks = <&clk26mhz>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- etm2_out: endpoint { +- remote-endpoint = <&funnel_in_port2>; +- }; +- }; +- }; +- }; +- +- etm@10740000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x10740000 0 0x1000>; +- +- cpu = <&cpu3>; +- clocks = <&clk26mhz>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- etm3_out: endpoint { +- remote-endpoint = <&funnel_in_port3>; +- }; +- }; +- }; +- }; +- +- stm@10006000 { +- compatible = "arm,coresight-stm", "arm,primecell"; +- reg = <0 0x10006000 0 0x1000>, +- <0 0x01000000 0 0x180000>; +- reg-names = "stm-base", "stm-stimulus-base"; +- clocks = <&clk26mhz>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- stm_out: endpoint { +- remote-endpoint = <&funnel_in_port4>; +- }; +- }; +- }; +- }; +- +- gic: interrupt-controller@12001000 { +- compatible = "arm,gic-400"; +- reg = <0 0x12001000 0 0x1000>, +- <0 0x12002000 0 0x2000>, +- <0 0x12004000 0 0x2000>, +- <0 0x12006000 0 0x2000>; +- #interrupt-cells = <3>; +- interrupt-controller; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci"; +- method = "smc"; +- cpu_on = <0xc4000003>; +- cpu_off = <0x84000002>; +- cpu_suspend = <0xc4000001>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/sprd/sc9860.dtsi b/scripts/dtc/include-prefixes/arm64/sprd/sc9860.dtsi +deleted file mode 100644 +index e27eb3ed1d47..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/sprd/sc9860.dtsi ++++ /dev/null +@@ -1,716 +0,0 @@ +-/* +- * Spreadtrum SC9860 SoC +- * +- * Copyright (C) 2016, Spreadtrum Communications Inc. +- * +- * SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- */ +- +-#include +-#include +-#include +-#include "whale2.dtsi" +- +-/ { +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&CPU0>; +- }; +- core1 { +- cpu = <&CPU1>; +- }; +- core2 { +- cpu = <&CPU2>; +- }; +- core3 { +- cpu = <&CPU3>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&CPU4>; +- }; +- core1 { +- cpu = <&CPU5>; +- }; +- core2 { +- cpu = <&CPU6>; +- }; +- core3 { +- cpu = <&CPU7>; +- }; +- }; +- }; +- +- CPU0: cpu@530000 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x530000>; +- enable-method = "psci"; +- cpu-idle-states = <&CORE_PD &CLUSTER_PD>; +- }; +- +- CPU1: cpu@530001 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x530001>; +- enable-method = "psci"; +- cpu-idle-states = <&CORE_PD &CLUSTER_PD>; +- }; +- +- CPU2: cpu@530002 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x530002>; +- enable-method = "psci"; +- cpu-idle-states = <&CORE_PD &CLUSTER_PD>; +- }; +- +- CPU3: cpu@530003 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x530003>; +- enable-method = "psci"; +- cpu-idle-states = <&CORE_PD &CLUSTER_PD>; +- }; +- +- CPU4: cpu@530100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x530100>; +- enable-method = "psci"; +- cpu-idle-states = <&CORE_PD &CLUSTER_PD>; +- }; +- +- CPU5: cpu@530101 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x530101>; +- enable-method = "psci"; +- cpu-idle-states = <&CORE_PD &CLUSTER_PD>; +- }; +- +- CPU6: cpu@530102 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x530102>; +- enable-method = "psci"; +- cpu-idle-states = <&CORE_PD &CLUSTER_PD>; +- }; +- +- CPU7: cpu@530103 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0 0x530103>; +- enable-method = "psci"; +- cpu-idle-states = <&CORE_PD &CLUSTER_PD>; +- }; +- }; +- +- idle-states{ +- entry-method = "psci"; +- +- CORE_PD: core_pd { +- compatible = "arm,idle-state"; +- entry-latency-us = <1000>; +- exit-latency-us = <700>; +- min-residency-us = <2500>; +- local-timer-stop; +- arm,psci-suspend-param = <0x00010002>; +- }; +- +- CLUSTER_PD: cluster_pd { +- compatible = "arm,idle-state"; +- entry-latency-us = <1000>; +- exit-latency-us = <1000>; +- min-residency-us = <3000>; +- local-timer-stop; +- arm,psci-suspend-param = <0x01010003>; +- }; +- }; +- +- gic: interrupt-controller@12001000 { +- compatible = "arm,gic-400"; +- reg = <0 0x12001000 0 0x1000>, +- <0 0x12002000 0 0x2000>, +- <0 0x12004000 0 0x2000>, +- <0 0x12006000 0 0x2000>; +- #interrupt-cells = <3>; +- interrupt-controller; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-affinity = <&CPU0>, +- <&CPU1>, +- <&CPU2>, +- <&CPU3>, +- <&CPU4>, +- <&CPU5>, +- <&CPU6>, +- <&CPU7>; +- }; +- +- soc { +- pmu_gate: pmu-gate { +- compatible = "sprd,sc9860-pmu-gate"; +- sprd,syscon = <&pmu_regs>; /* 0x402b0000 */ +- clocks = <&ext_26m>; +- #clock-cells = <1>; +- }; +- +- pll: pll { +- compatible = "sprd,sc9860-pll"; +- sprd,syscon = <&ana_regs>; /* 0x40400000 */ +- clocks = <&pmu_gate 0>; +- #clock-cells = <1>; +- }; +- +- ap_clk: clock-controller@20000000 { +- compatible = "sprd,sc9860-ap-clk"; +- reg = <0 0x20000000 0 0x400>; +- clocks = <&ext_26m>, <&pll 0>, +- <&pmu_gate 0>; +- #clock-cells = <1>; +- }; +- +- aon_prediv: aon-prediv { +- compatible = "sprd,sc9860-aon-prediv"; +- reg = <0 0x402d0000 0 0x400>; +- clocks = <&ext_26m>, <&pll 0>, +- <&pmu_gate 0>; +- #clock-cells = <1>; +- }; +- +- apahb_gate: apahb-gate { +- compatible = "sprd,sc9860-apahb-gate"; +- sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */ +- clocks = <&aon_prediv 0>; +- #clock-cells = <1>; +- }; +- +- aon_gate: aon-gate { +- compatible = "sprd,sc9860-aon-gate"; +- sprd,syscon = <&aon_regs>; /* 0x402e0000 */ +- clocks = <&aon_prediv 0>; +- #clock-cells = <1>; +- }; +- +- aonsecure_clk: clock-controller@40880000 { +- compatible = "sprd,sc9860-aonsecure-clk"; +- reg = <0 0x40880000 0 0x400>; +- clocks = <&ext_26m>, <&pll 0>; +- #clock-cells = <1>; +- }; +- +- agcp_gate: agcp-gate { +- compatible = "sprd,sc9860-agcp-gate"; +- sprd,syscon = <&agcp_regs>; /* 0x415e0000 */ +- clocks = <&aon_prediv 0>; +- #clock-cells = <1>; +- }; +- +- gpu_clk: clock-controller@60200000 { +- compatible = "sprd,sc9860-gpu-clk"; +- reg = <0 0x60200000 0 0x400>; +- clocks = <&pll 0>; +- #clock-cells = <1>; +- }; +- +- vsp_clk: clock-controller@61000000 { +- compatible = "sprd,sc9860-vsp-clk"; +- reg = <0 0x61000000 0 0x400>; +- clocks = <&ext_26m>, <&pll 0>; +- #clock-cells = <1>; +- }; +- +- vsp_gate: vsp-gate { +- compatible = "sprd,sc9860-vsp-gate"; +- sprd,syscon = <&vsp_regs>; /* 0x61100000 */ +- clocks = <&vsp_clk 0>; +- #clock-cells = <1>; +- }; +- +- cam_clk: clock-controller@62000000 { +- compatible = "sprd,sc9860-cam-clk"; +- reg = <0 0x62000000 0 0x4000>; +- clocks = <&ext_26m>, <&pll 0>; +- #clock-cells = <1>; +- }; +- +- cam_gate: cam-gate { +- compatible = "sprd,sc9860-cam-gate"; +- sprd,syscon = <&cam_regs>; /* 0x62100000 */ +- clocks = <&cam_clk 0>; +- #clock-cells = <1>; +- }; +- +- disp_clk: clock-controller@63000000 { +- compatible = "sprd,sc9860-disp-clk"; +- reg = <0 0x63000000 0 0x400>; +- clocks = <&ext_26m>, <&pll 0>; +- #clock-cells = <1>; +- }; +- +- disp_gate: disp-gate { +- compatible = "sprd,sc9860-disp-gate"; +- sprd,syscon = <&disp_regs>; /* 0x63100000 */ +- clocks = <&disp_clk 0>; +- #clock-cells = <1>; +- }; +- +- apapb_gate: apapb-gate { +- compatible = "sprd,sc9860-apapb-gate"; +- sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */ +- clocks = <&ap_clk 0>; +- #clock-cells = <1>; +- }; +- +- funnel@10001000 { /* SoC Funnel */ +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x10001000 0 0x1000>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- soc_funnel_out_port: endpoint { +- remote-endpoint = <&etb_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- soc_funnel_in_port0: endpoint { +- remote-endpoint = +- <&main_funnel_out_port>; +- }; +- }; +- +- port@4 { +- reg = <4>; +- soc_funnel_in_port1: endpoint { +- remote-endpoint = +- <&stm_out_port>; +- }; +- }; +- }; +- }; +- +- etb@10003000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0x10003000 0 0x1000>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- etb_in: endpoint { +- remote-endpoint = +- <&soc_funnel_out_port>; +- }; +- }; +- }; +- }; +- +- stm@10006000 { +- compatible = "arm,coresight-stm", "arm,primecell"; +- reg = <0 0x10006000 0 0x1000>, +- <0 0x01000000 0 0x180000>; +- reg-names = "stm-base", "stm-stimulus-base"; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- stm_out_port: endpoint { +- remote-endpoint = +- <&soc_funnel_in_port1>; +- }; +- }; +- }; +- }; +- +- funnel@11001000 { /* Cluster0 Funnel */ +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x11001000 0 0x1000>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- cluster0_funnel_out_port: endpoint { +- remote-endpoint = +- <&cluster0_etf_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- cluster0_funnel_in_port0: endpoint { +- remote-endpoint = <&etm0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- cluster0_funnel_in_port1: endpoint { +- remote-endpoint = <&etm1_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- cluster0_funnel_in_port2: endpoint { +- remote-endpoint = <&etm2_out>; +- }; +- }; +- +- port@4 { +- reg = <4>; +- cluster0_funnel_in_port3: endpoint { +- remote-endpoint = <&etm3_out>; +- }; +- }; +- }; +- }; +- +- funnel@11002000 { /* Cluster1 Funnel */ +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x11002000 0 0x1000>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- out-ports { +- port { +- cluster1_funnel_out_port: endpoint { +- remote-endpoint = +- <&cluster1_etf_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- cluster1_funnel_in_port0: endpoint { +- remote-endpoint = <&etm4_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- cluster1_funnel_in_port1: endpoint { +- remote-endpoint = <&etm5_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- cluster1_funnel_in_port2: endpoint { +- remote-endpoint = <&etm6_out>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- cluster1_funnel_in_port3: endpoint { +- remote-endpoint = <&etm7_out>; +- }; +- }; +- }; +- }; +- +- etf@11003000 { /* ETF on Cluster0 */ +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0x11003000 0 0x1000>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- cluster0_etf_out: endpoint { +- remote-endpoint = +- <&main_funnel_in_port0>; +- }; +- }; +- }; +- +- in-ports { +- port { +- cluster0_etf_in: endpoint { +- remote-endpoint = +- <&cluster0_funnel_out_port>; +- }; +- }; +- }; +- }; +- +- etf@11004000 { /* ETF on Cluster1 */ +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0x11004000 0 0x1000>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- cluster1_etf_out: endpoint { +- remote-endpoint = +- <&main_funnel_in_port1>; +- }; +- }; +- }; +- +- in-ports { +- port { +- cluster1_etf_in: endpoint { +- remote-endpoint = +- <&cluster1_funnel_out_port>; +- }; +- }; +- }; +- }; +- +- funnel@11005000 { /* Main Funnel */ +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x11005000 0 0x1000>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- main_funnel_out_port: endpoint { +- remote-endpoint = +- <&soc_funnel_in_port0>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- main_funnel_in_port0: endpoint { +- remote-endpoint = +- <&cluster0_etf_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- main_funnel_in_port1: endpoint { +- remote-endpoint = +- <&cluster1_etf_out>; +- }; +- }; +- }; +- }; +- +- etm@11440000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x11440000 0 0x1000>; +- cpu = <&CPU0>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etm0_out: endpoint { +- remote-endpoint = +- <&cluster0_funnel_in_port0>; +- }; +- }; +- }; +- }; +- +- etm@11540000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x11540000 0 0x1000>; +- cpu = <&CPU1>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etm1_out: endpoint { +- remote-endpoint = +- <&cluster0_funnel_in_port1>; +- }; +- }; +- }; +- }; +- +- etm@11640000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x11640000 0 0x1000>; +- cpu = <&CPU2>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etm2_out: endpoint { +- remote-endpoint = +- <&cluster0_funnel_in_port2>; +- }; +- }; +- }; +- }; +- +- etm@11740000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x11740000 0 0x1000>; +- cpu = <&CPU3>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etm3_out: endpoint { +- remote-endpoint = +- <&cluster0_funnel_in_port3>; +- }; +- }; +- }; +- }; +- +- etm@11840000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x11840000 0 0x1000>; +- cpu = <&CPU4>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etm4_out: endpoint { +- remote-endpoint = +- <&cluster1_funnel_in_port0>; +- }; +- }; +- }; +- }; +- +- etm@11940000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x11940000 0 0x1000>; +- cpu = <&CPU5>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etm5_out: endpoint { +- remote-endpoint = +- <&cluster1_funnel_in_port1>; +- }; +- }; +- }; +- }; +- +- etm@11a40000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x11a40000 0 0x1000>; +- cpu = <&CPU6>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etm6_out: endpoint { +- remote-endpoint = +- <&cluster1_funnel_in_port2>; +- }; +- }; +- }; +- }; +- +- etm@11b40000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x11b40000 0 0x1000>; +- cpu = <&CPU7>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etm7_out: endpoint { +- remote-endpoint = +- <&cluster1_funnel_in_port3>; +- }; +- }; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- key-volumedown { +- label = "Volume Down Key"; +- linux,code = ; +- gpios = <&eic_debounce 2 GPIO_ACTIVE_LOW>; +- debounce-interval = <2>; +- wakeup-source; +- }; +- +- key-volumeup { +- label = "Volume Up Key"; +- linux,code = ; +- gpios = <&pmic_eic 10 GPIO_ACTIVE_HIGH>; +- debounce-interval = <2>; +- wakeup-source; +- }; +- +- key-power { +- label = "Power Key"; +- linux,code = ; +- gpios = <&pmic_eic 1 GPIO_ACTIVE_HIGH>; +- debounce-interval = <2>; +- wakeup-source; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/sprd/sc9863a.dtsi b/scripts/dtc/include-prefixes/arm64/sprd/sc9863a.dtsi +deleted file mode 100644 +index 8cf4a6575980..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/sprd/sc9863a.dtsi ++++ /dev/null +@@ -1,589 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Unisoc SC9863A SoC DTS file +- * +- * Copyright (C) 2019, Unisoc Inc. +- */ +- +-#include +-#include +-#include "sharkl3.dtsi" +- +-/ { +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&CPU0>; +- }; +- core1 { +- cpu = <&CPU1>; +- }; +- core2 { +- cpu = <&CPU2>; +- }; +- core3 { +- cpu = <&CPU3>; +- }; +- core4 { +- cpu = <&CPU4>; +- }; +- core5 { +- cpu = <&CPU5>; +- }; +- core6 { +- cpu = <&CPU6>; +- }; +- core7 { +- cpu = <&CPU7>; +- }; +- }; +- }; +- +- CPU0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x0>; +- enable-method = "psci"; +- cpu-idle-states = <&CORE_PD>; +- }; +- +- CPU1: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- cpu-idle-states = <&CORE_PD>; +- }; +- +- CPU2: cpu@200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x200>; +- enable-method = "psci"; +- cpu-idle-states = <&CORE_PD>; +- }; +- +- CPU3: cpu@300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x300>; +- enable-method = "psci"; +- cpu-idle-states = <&CORE_PD>; +- }; +- +- CPU4: cpu@400 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x400>; +- enable-method = "psci"; +- cpu-idle-states = <&CORE_PD>; +- }; +- +- CPU5: cpu@500 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x500>; +- enable-method = "psci"; +- cpu-idle-states = <&CORE_PD>; +- }; +- +- CPU6: cpu@600 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x600>; +- enable-method = "psci"; +- cpu-idle-states = <&CORE_PD>; +- }; +- +- CPU7: cpu@700 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x700>; +- enable-method = "psci"; +- cpu-idle-states = <&CORE_PD>; +- }; +- }; +- +- idle-states { +- entry-method = "psci"; +- CORE_PD: core-pd { +- compatible = "arm,idle-state"; +- entry-latency-us = <4000>; +- exit-latency-us = <4000>; +- min-residency-us = <10000>; +- local-timer-stop; +- arm,psci-suspend-param = <0x00010000>; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , /* Physical Secure PPI */ +- , /* Physical Non-Secure PPI */ +- , /* Virtual PPI */ +- ; /* Hipervisor PPI */ +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- }; +- +- soc { +- gic: interrupt-controller@14000000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- redistributor-stride = <0x0 0x20000>; /* 128KB stride */ +- #redistributor-regions = <1>; +- interrupt-controller; +- reg = <0x0 0x14000000 0 0x20000>, /* GICD */ +- <0x0 0x14040000 0 0x100000>; /* GICR */ +- interrupts = ; +- }; +- +- ap_clk: clock-controller@21500000 { +- compatible = "sprd,sc9863a-ap-clk"; +- reg = <0 0x21500000 0 0x1000>; +- clocks = <&ext_32k>, <&ext_26m>; +- clock-names = "ext-32k", "ext-26m"; +- #clock-cells = <1>; +- }; +- +- aon_clk: clock-controller@402d0000 { +- compatible = "sprd,sc9863a-aon-clk"; +- reg = <0 0x402d0000 0 0x1000>; +- clocks = <&ext_26m>, <&rco_100m>, +- <&ext_32k>, <&ext_4m>; +- clock-names = "ext-26m", "rco-100m", +- "ext-32k", "ext-4m"; +- #clock-cells = <1>; +- }; +- +- mm_clk: clock-controller@60900000 { +- compatible = "sprd,sc9863a-mm-clk"; +- reg = <0 0x60900000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- funnel@10001000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x10001000 0 0x1000>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- funnel_soc_out_port: endpoint { +- remote-endpoint = <&etb_in>; +- }; +- }; +- }; +- +- in-ports { +- port { +- funnel_soc_in_port: endpoint { +- remote-endpoint = +- <&funnel_ca55_out_port>; +- }; +- }; +- }; +- }; +- +- etb@10003000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0x10003000 0 0x1000>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- in-ports { +- port { +- etb_in: endpoint { +- remote-endpoint = +- <&funnel_soc_out_port>; +- }; +- }; +- }; +- }; +- +- funnel@12001000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x12001000 0 0x1000>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- funnel_little_out_port: endpoint { +- remote-endpoint = +- <&etf_little_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- funnel_little_in_port0: endpoint { +- remote-endpoint = <&etm0_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- funnel_little_in_port1: endpoint { +- remote-endpoint = <&etm1_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- funnel_little_in_port2: endpoint { +- remote-endpoint = <&etm2_out>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- funnel_little_in_port3: endpoint { +- remote-endpoint = <&etm3_out>; +- }; +- }; +- }; +- }; +- +- etf@12002000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0x12002000 0 0x1000>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etf_little_out: endpoint { +- remote-endpoint = +- <&funnel_ca55_in_port0>; +- }; +- }; +- }; +- +- in-port { +- port { +- etf_little_in: endpoint { +- remote-endpoint = +- <&funnel_little_out_port>; +- }; +- }; +- }; +- }; +- +- etf@12003000 { +- compatible = "arm,coresight-tmc", "arm,primecell"; +- reg = <0 0x12003000 0 0x1000>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etf_big_out: endpoint { +- remote-endpoint = +- <&funnel_ca55_in_port1>; +- }; +- }; +- }; +- +- in-ports { +- port { +- etf_big_in: endpoint { +- remote-endpoint = +- <&funnel_big_out_port>; +- }; +- }; +- }; +- }; +- +- funnel@12004000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x12004000 0 0x1000>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- funnel_ca55_out_port: endpoint { +- remote-endpoint = +- <&funnel_soc_in_port>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- funnel_ca55_in_port0: endpoint { +- remote-endpoint = +- <&etf_little_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- funnel_ca55_in_port1: endpoint { +- remote-endpoint = +- <&etf_big_out>; +- }; +- }; +- }; +- }; +- +- funnel@12005000 { +- compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; +- reg = <0 0x12005000 0 0x1000>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- funnel_big_out_port: endpoint { +- remote-endpoint = +- <&etf_big_in>; +- }; +- }; +- }; +- +- in-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- funnel_big_in_port0: endpoint { +- remote-endpoint = <&etm4_out>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- funnel_big_in_port1: endpoint { +- remote-endpoint = <&etm5_out>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- funnel_big_in_port2: endpoint { +- remote-endpoint = <&etm6_out>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- funnel_big_in_port3: endpoint { +- remote-endpoint = <&etm7_out>; +- }; +- }; +- }; +- }; +- +- etm@13040000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x13040000 0 0x1000>; +- cpu = <&CPU0>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etm0_out: endpoint { +- remote-endpoint = +- <&funnel_little_in_port0>; +- }; +- }; +- }; +- }; +- +- etm@13140000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x13140000 0 0x1000>; +- cpu = <&CPU1>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etm1_out: endpoint { +- remote-endpoint = +- <&funnel_little_in_port1>; +- }; +- }; +- }; +- }; +- +- etm@13240000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x13240000 0 0x1000>; +- cpu = <&CPU2>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etm2_out: endpoint { +- remote-endpoint = +- <&funnel_little_in_port2>; +- }; +- }; +- }; +- }; +- +- etm@13340000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x13340000 0 0x1000>; +- cpu = <&CPU3>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etm3_out: endpoint { +- remote-endpoint = +- <&funnel_little_in_port3>; +- }; +- }; +- }; +- }; +- +- etm@13440000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x13440000 0 0x1000>; +- cpu = <&CPU4>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etm4_out: endpoint { +- remote-endpoint = +- <&funnel_big_in_port0>; +- }; +- }; +- }; +- }; +- +- etm@13540000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x13540000 0 0x1000>; +- cpu = <&CPU5>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etm5_out: endpoint { +- remote-endpoint = +- <&funnel_big_in_port1>; +- }; +- }; +- }; +- }; +- +- etm@13640000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x13640000 0 0x1000>; +- cpu = <&CPU6>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etm6_out: endpoint { +- remote-endpoint = +- <&funnel_big_in_port2>; +- }; +- }; +- }; +- }; +- +- etm@13740000 { +- compatible = "arm,coresight-etm4x", "arm,primecell"; +- reg = <0 0x13740000 0 0x1000>; +- cpu = <&CPU7>; +- clocks = <&ext_26m>; +- clock-names = "apb_pclk"; +- +- out-ports { +- port { +- etm7_out: endpoint { +- remote-endpoint = +- <&funnel_big_in_port3>; +- }; +- }; +- }; +- }; +- +- ap-ahb { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- sdio0: sdio@20300000 { +- compatible = "sprd,sdhci-r11"; +- reg = <0 0x20300000 0 0x1000>; +- interrupts = ; +- +- clock-names = "sdio", "enable"; +- clocks = <&aon_clk CLK_SDIO0_2X>, +- <&apahb_gate CLK_SDIO0_EB>; +- assigned-clocks = <&aon_clk CLK_SDIO0_2X>; +- assigned-clock-parents = <&rpll CLK_RPLL_390M>; +- +- bus-width = <4>; +- no-sdio; +- no-mmc; +- }; +- +- sdio3: sdio@20600000 { +- compatible = "sprd,sdhci-r11"; +- reg = <0 0x20600000 0 0x1000>; +- interrupts = ; +- +- clock-names = "sdio", "enable"; +- clocks = <&aon_clk CLK_EMMC_2X>, +- <&apahb_gate CLK_EMMC_EB>; +- assigned-clocks = <&aon_clk CLK_EMMC_2X>; +- assigned-clock-parents = <&rpll CLK_RPLL_390M>; +- +- bus-width = <8>; +- non-removable; +- no-sdio; +- no-sd; +- cap-mmc-hw-reset; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/sprd/sharkl3.dtsi b/scripts/dtc/include-prefixes/arm64/sprd/sharkl3.dtsi +deleted file mode 100644 +index 206a4afdab1c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/sprd/sharkl3.dtsi ++++ /dev/null +@@ -1,242 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Unisoc Sharkl3 platform DTS file +- * +- * Copyright (C) 2019, Unisoc Inc. +- */ +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- soc: soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ap_ahb_regs: syscon@20e00000 { +- compatible = "sprd,sc9863a-glbregs", "syscon", +- "simple-mfd"; +- reg = <0 0x20e00000 0 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x20e00000 0x4000>; +- +- apahb_gate: apahb-gate { +- compatible = "sprd,sc9863a-apahb-gate"; +- reg = <0x0 0x1020>; +- #clock-cells = <1>; +- }; +- }; +- +- pmu_regs: syscon@402b0000 { +- compatible = "sprd,sc9863a-glbregs", "syscon", +- "simple-mfd"; +- reg = <0 0x402b0000 0 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x402b0000 0x4000>; +- +- pmu_gate: pmu-gate { +- compatible = "sprd,sc9863a-pmu-gate"; +- reg = <0 0x1200>; +- clocks = <&ext_26m>; +- clock-names = "ext-26m"; +- #clock-cells = <1>; +- }; +- }; +- +- aon_apb_regs: syscon@402e0000 { +- compatible = "sprd,sc9863a-glbregs", "syscon", +- "simple-mfd"; +- reg = <0 0x402e0000 0 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x402e0000 0x4000>; +- +- aonapb_gate: aonapb-gate { +- compatible = "sprd,sc9863a-aonapb-gate"; +- reg = <0 0x1100>; +- #clock-cells = <1>; +- }; +- }; +- +- anlg_phy_g2_regs: syscon@40353000 { +- compatible = "sprd,sc9863a-glbregs", "syscon", +- "simple-mfd"; +- reg = <0 0x40353000 0 0x3000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x40353000 0x3000>; +- +- pll: pll { +- compatible = "sprd,sc9863a-pll"; +- reg = <0 0x100>; +- clocks = <&ext_26m>; +- clock-names = "ext-26m"; +- #clock-cells = <1>; +- }; +- }; +- +- anlg_phy_g4_regs: syscon@40359000 { +- compatible = "sprd,sc9863a-glbregs", "syscon", +- "simple-mfd"; +- reg = <0 0x40359000 0 0x3000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x40359000 0x3000>; +- +- mpll: mpll { +- compatible = "sprd,sc9863a-mpll"; +- reg = <0 0x100>; +- #clock-cells = <1>; +- }; +- }; +- +- anlg_phy_g5_regs: syscon@4035c000 { +- compatible = "sprd,sc9863a-glbregs", "syscon", +- "simple-mfd"; +- reg = <0 0x4035c000 0 0x3000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x4035c000 0x3000>; +- +- rpll: rpll { +- compatible = "sprd,sc9863a-rpll"; +- reg = <0 0x100>; +- clocks = <&ext_26m>; +- clock-names = "ext-26m"; +- #clock-cells = <1>; +- }; +- }; +- +- anlg_phy_g7_regs: syscon@40363000 { +- compatible = "sprd,sc9863a-glbregs", "syscon", +- "simple-mfd"; +- reg = <0 0x40363000 0 0x3000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x40363000 0x3000>; +- +- dpll: dpll { +- compatible = "sprd,sc9863a-dpll"; +- reg = <0 0x100>; +- #clock-cells = <1>; +- }; +- }; +- +- mm_ahb_regs: syscon@60800000 { +- compatible = "sprd,sc9863a-glbregs", "syscon", +- "simple-mfd"; +- reg = <0 0x60800000 0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x60800000 0x3000>; +- +- mm_gate: mm-gate { +- compatible = "sprd,sc9863a-mm-gate"; +- reg = <0 0x1100>; +- #clock-cells = <1>; +- }; +- }; +- +- ap_apb_regs: syscon@71300000 { +- compatible = "sprd,sc9863a-glbregs", "syscon", +- "simple-mfd"; +- reg = <0 0x71300000 0 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x71300000 0x4000>; +- +- apapb_gate: apapb-gate { +- compatible = "sprd,sc9863a-apapb-gate"; +- reg = <0 0x1000>; +- clocks = <&ext_26m>; +- clock-names = "ext-26m"; +- #clock-cells = <1>; +- }; +- }; +- +- apb@70000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x0 0x70000000 0x10000000>; +- +- uart0: serial@0 { +- compatible = "sprd,sc9863a-uart", +- "sprd,sc9836-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clocks = <&ext_26m>; +- status = "disabled"; +- }; +- +- uart1: serial@100000 { +- compatible = "sprd,sc9863a-uart", +- "sprd,sc9836-uart"; +- reg = <0x100000 0x100>; +- interrupts = ; +- clocks = <&ext_26m>; +- status = "disabled"; +- }; +- +- uart2: serial@200000 { +- compatible = "sprd,sc9863a-uart", +- "sprd,sc9836-uart"; +- reg = <0x200000 0x100>; +- interrupts = ; +- clocks = <&ext_26m>; +- status = "disabled"; +- }; +- +- uart3: serial@300000 { +- compatible = "sprd,sc9863a-uart", +- "sprd,sc9836-uart"; +- reg = <0x300000 0x100>; +- interrupts = ; +- clocks = <&ext_26m>; +- status = "disabled"; +- }; +- +- uart4: serial@400000 { +- compatible = "sprd,sc9863a-uart", +- "sprd,sc9836-uart"; +- reg = <0x400000 0x100>; +- interrupts = ; +- clocks = <&ext_26m>; +- status = "disabled"; +- }; +- }; +- }; +- +- ext_26m: ext-26m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- clock-output-names = "ext-26m"; +- }; +- +- ext_32k: ext-32k { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "ext-32k"; +- }; +- +- ext_4m: ext-4m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <4000000>; +- clock-output-names = "ext-4m"; +- }; +- +- rco_100m: rco-100m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- clock-output-names = "rco-100m"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/sprd/sharkl64.dtsi b/scripts/dtc/include-prefixes/arm64/sprd/sharkl64.dtsi +deleted file mode 100644 +index 69f64e7fce7c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/sprd/sharkl64.dtsi ++++ /dev/null +@@ -1,65 +0,0 @@ +-/* +- * Spreadtrum Sharkl64 platform DTS file +- * +- * Copyright (C) 2014, Spreadtrum Communications Inc. +- * +- * This file is licensed under a dual GPLv2 or X11 license. +- */ +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ap-apb { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- uart0: serial@70000000 { +- compatible = "sprd,sc9836-uart"; +- reg = <0 0x70000000 0 0x100>; +- interrupts = <0 2 0xf04>; +- clocks = <&clk26mhz>; +- status = "disabled"; +- }; +- +- uart1: serial@70100000 { +- compatible = "sprd,sc9836-uart"; +- reg = <0 0x70100000 0 0x100>; +- interrupts = <0 3 0xf04>; +- clocks = <&clk26mhz>; +- status = "disabled"; +- }; +- +- uart2: serial@70200000 { +- compatible = "sprd,sc9836-uart"; +- reg = <0 0x70200000 0 0x100>; +- interrupts = <0 4 0xf04>; +- clocks = <&clk26mhz>; +- status = "disabled"; +- }; +- +- uart3: serial@70300000 { +- compatible = "sprd,sc9836-uart"; +- reg = <0 0x70300000 0 0x100>; +- interrupts = <0 5 0xf04>; +- clocks = <&clk26mhz>; +- status = "disabled"; +- }; +- }; +- }; +- +- clk26mhz: clk26mhz { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/sprd/sp9860g-1h10.dts b/scripts/dtc/include-prefixes/arm64/sprd/sp9860g-1h10.dts +deleted file mode 100644 +index 6b95fd94cee3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/sprd/sp9860g-1h10.dts ++++ /dev/null +@@ -1,74 +0,0 @@ +-/* +- * Spreadtrum SP9860g board +- * +- * Copyright (C) 2017, Spreadtrum Communications Inc. +- * +- * SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- */ +- +-/dts-v1/; +- +-#include "sc9860.dtsi" +-#include "sc2731.dtsi" +- +-/ { +- model = "Spreadtrum SP9860G 3GFHD Board"; +- +- compatible = "sprd,sp9860g-1h10", "sprd,sc9860"; +- +- aliases { +- serial0 = &uart0; /* for Bluetooth */ +- serial1 = &uart1; /* UART console */ +- serial2 = &uart2; /* Reserved */ +- serial3 = &uart3; /* for GPS */ +- spi0 = &adi_bus; +- }; +- +- memory{ +- device_type = "memory"; +- reg = <0x0 0x80000000 0 0x60000000>, +- <0x1 0x80000000 0 0x60000000>; +- }; +- +- chosen { +- stdout-path = "serial1:115200n8"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- }; +- +- bat: battery { +- compatible = "simple-battery"; +- charge-full-design-microamp-hours = <1900000>; +- charge-term-current-microamp = <120000>; +- constant_charge_voltage_max_microvolt = <4350000>; +- internal-resistance-micro-ohms = <250000>; +- ocv-capacity-celsius = <20>; +- ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>, +- <4022000 85>, <3983000 80>, <3949000 75>, +- <3917000 70>, <3889000 65>, <3864000 60>, +- <3835000 55>, <3805000 50>, <3787000 45>, +- <3777000 40>, <3773000 35>, <3770000 30>, +- <3765000 25>, <3752000 20>, <3724000 15>, +- <3680000 10>, <3605000 5>, <3400000 0>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/sprd/sp9863a-1h10.dts b/scripts/dtc/include-prefixes/arm64/sprd/sp9863a-1h10.dts +deleted file mode 100644 +index 5c32c1596337..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/sprd/sp9863a-1h10.dts ++++ /dev/null +@@ -1,39 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Unisoc SP9863A-1h10 boards DTS file +- * +- * Copyright (C) 2019, Unisoc Inc. +- */ +- +-/dts-v1/; +- +-#include "sc9863a.dtsi" +- +-/ { +- model = "Spreadtrum SP9863A-1H10 Board"; +- +- compatible = "sprd,sp9863a-1h10", "sprd,sc9863a"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0x80000000>; +- }; +- +- chosen { +- stdout-path = "serial1:115200n8"; +- bootargs = "earlycon"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/sprd/whale2.dtsi b/scripts/dtc/include-prefixes/arm64/sprd/whale2.dtsi +deleted file mode 100644 +index 79b9591c37aa..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/sprd/whale2.dtsi ++++ /dev/null +@@ -1,310 +0,0 @@ +-/* +- * Spreadtrum Whale2 platform peripherals +- * +- * Copyright (C) 2016, Spreadtrum Communications Inc. +- * +- * SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- */ +- +-#include +- +-/ { +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- soc: soc { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ap_ahb_regs: syscon@20210000 { +- compatible = "syscon"; +- reg = <0 0x20210000 0 0x10000>; +- }; +- +- pmu_regs: syscon@402b0000 { +- compatible = "syscon"; +- reg = <0 0x402b0000 0 0x10000>; +- }; +- +- aon_regs: syscon@402e0000 { +- compatible = "syscon"; +- reg = <0 0x402e0000 0 0x10000>; +- }; +- +- ana_regs: syscon@40400000 { +- compatible = "syscon"; +- reg = <0 0x40400000 0 0x10000>; +- }; +- +- agcp_regs: syscon@415e0000 { +- compatible = "syscon"; +- reg = <0 0x415e0000 0 0x1000000>; +- }; +- +- vsp_regs: syscon@61100000 { +- compatible = "syscon"; +- reg = <0 0x61100000 0 0x10000>; +- }; +- +- cam_regs: syscon@62100000 { +- compatible = "syscon"; +- reg = <0 0x62100000 0 0x10000>; +- }; +- +- disp_regs: syscon@63100000 { +- compatible = "syscon"; +- reg = <0 0x63100000 0 0x10000>; +- }; +- +- ap_apb_regs: syscon@70b00000 { +- compatible = "syscon"; +- reg = <0 0x70b00000 0 0x40000>; +- }; +- +- ap-apb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x0 0x70000000 0x10000000>; +- +- uart0: serial@0 { +- compatible = "sprd,sc9860-uart", +- "sprd,sc9836-uart"; +- reg = <0x0 0x100>; +- interrupts = ; +- clock-names = "enable", "uart", "source"; +- clocks = <&apapb_gate CLK_UART0_EB>, +- <&ap_clk CLK_UART0>, <&ext_26m>; +- status = "disabled"; +- }; +- +- uart1: serial@100000 { +- compatible = "sprd,sc9860-uart", +- "sprd,sc9836-uart"; +- reg = <0x100000 0x100>; +- interrupts = ; +- clock-names = "enable", "uart", "source"; +- clocks = <&apapb_gate CLK_UART1_EB>, +- <&ap_clk CLK_UART1>, <&ext_26m>; +- status = "disabled"; +- }; +- +- uart2: serial@200000 { +- compatible = "sprd,sc9860-uart", +- "sprd,sc9836-uart"; +- reg = <0x200000 0x100>; +- interrupts = ; +- clock-names = "enable", "uart", "source"; +- clocks = <&apapb_gate CLK_UART2_EB>, +- <&ap_clk CLK_UART2>, <&ext_26m>; +- status = "disabled"; +- }; +- +- uart3: serial@300000 { +- compatible = "sprd,sc9860-uart", +- "sprd,sc9836-uart"; +- reg = <0x300000 0x100>; +- interrupts = ; +- clock-names = "enable", "uart", "source"; +- clocks = <&apapb_gate CLK_UART3_EB>, +- <&ap_clk CLK_UART3>, <&ext_26m>; +- status = "disabled"; +- }; +- }; +- +- ap-ahb { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ap_dma: dma-controller@20100000 { +- compatible = "sprd,sc9860-dma"; +- reg = <0 0x20100000 0 0x4000>; +- interrupts = ; +- #dma-cells = <1>; +- #dma-channels = <32>; +- clock-names = "enable"; +- clocks = <&apahb_gate CLK_DMA_EB>; +- }; +- +- sdio3: sdio@50430000 { +- compatible = "sprd,sdhci-r11"; +- reg = <0 0x50430000 0 0x1000>; +- interrupts = ; +- +- clock-names = "sdio", "enable", "2x_enable"; +- clocks = <&aon_prediv CLK_EMMC_2X>, +- <&apahb_gate CLK_EMMC_EB>, +- <&aon_gate CLK_EMMC_2X_EN>; +- assigned-clocks = <&aon_prediv CLK_EMMC_2X>; +- assigned-clock-parents = <&clk_l0_409m6>; +- +- sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>; +- sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>; +- sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>; +- sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>; +- vmmc-supply = <&vddemmccore>; +- bus-width = <8>; +- non-removable; +- no-sdio; +- no-sd; +- cap-mmc-hw-reset; +- mmc-hs400-enhanced-strobe; +- mmc-hs400-1_8v; +- mmc-hs200-1_8v; +- mmc-ddr-1_8v; +- }; +- }; +- +- aon { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- adi_bus: spi@40030000 { +- compatible = "sprd,sc9860-adi"; +- reg = <0 0x40030000 0 0x10000>; +- hwlocks = <&hwlock 0>; +- hwlock-names = "adi"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- timer@40050000 { +- compatible = "sprd,sc9860-timer"; +- reg = <0 0x40050000 0 0x20>; +- interrupts = ; +- clocks = <&ext_32k>; +- }; +- +- timer@40050020 { +- compatible = "sprd,sc9860-suspend-timer"; +- reg = <0 0x40050020 0 0x20>; +- clocks = <&ext_32k>; +- }; +- +- hwlock: hwspinlock@40500000 { +- compatible = "sprd,hwspinlock-r3p0"; +- reg = <0 0x40500000 0 0x1000>; +- #hwlock-cells = <1>; +- clock-names = "enable"; +- clocks = <&aon_gate CLK_SPLK_EB>; +- }; +- +- eic_debounce: gpio@40210000 { +- compatible = "sprd,sc9860-eic-debounce"; +- reg = <0 0x40210000 0 0x80>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- +- eic_latch: gpio@40210080 { +- compatible = "sprd,sc9860-eic-latch"; +- reg = <0 0x40210080 0 0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- +- eic_async: gpio@402100a0 { +- compatible = "sprd,sc9860-eic-async"; +- reg = <0 0x402100a0 0 0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- +- eic_sync: gpio@402100c0 { +- compatible = "sprd,sc9860-eic-sync"; +- reg = <0 0x402100c0 0 0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- +- ap_gpio: gpio@40280000 { +- compatible = "sprd,sc9860-gpio"; +- reg = <0 0x40280000 0 0x1000>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- +- pin_controller: pinctrl@402a0000 { +- compatible = "sprd,sc9860-pinctrl"; +- reg = <0 0x402a0000 0 0x10000>; +- }; +- +- watchdog@40310000 { +- compatible = "sprd,sp9860-wdt"; +- reg = <0 0x40310000 0 0x1000>; +- interrupts = ; +- timeout-sec = <12>; +- clock-names = "enable", "rtc_enable"; +- clocks = <&aon_gate CLK_APCPU_WDG_EB>, +- <&aon_gate CLK_AP_WDG_RTC_EB>; +- }; +- }; +- +- agcp { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- agcp_dma: dma-controller@41580000 { +- compatible = "sprd,sc9860-dma"; +- reg = <0 0x41580000 0 0x4000>; +- #dma-cells = <1>; +- #dma-channels = <32>; +- clock-names = "enable", "ashb_eb"; +- clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>, +- <&agcp_gate CLK_AGCP_AP_ASHB_EB>; +- }; +- }; +- }; +- +- ext_32k: ext_32k { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- clock-output-names = "ext-32k"; +- }; +- +- ext_26m: ext_26m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- clock-output-names = "ext-26m"; +- }; +- +- ext_rco_100m: ext_rco_100m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- clock-output-names = "ext-rco-100m"; +- }; +- +- clk_l0_409m6: clk_l0_409m6 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <409600000>; +- clock-output-names = "ext-409m6"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/synaptics/Makefile b/scripts/dtc/include-prefixes/arm64/synaptics/Makefile +deleted file mode 100644 +index de71ddda6835..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/synaptics/Makefile ++++ /dev/null +@@ -1,4 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-# Berlin SoC Family +-dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-dmp.dtb +-dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-stb.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/synaptics/as370.dtsi b/scripts/dtc/include-prefixes/arm64/synaptics/as370.dtsi +deleted file mode 100644 +index 4bb5d650df9c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/synaptics/as370.dtsi ++++ /dev/null +@@ -1,173 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2018 Synaptics Incorporated +- * +- * Author: Jisheng Zhang +- */ +- +-#include +- +-/ { +- compatible = "syna,as370"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- cpu-idle-states = <&CPU_SLEEP_0>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x1>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- cpu-idle-states = <&CPU_SLEEP_0>; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x2>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- cpu-idle-states = <&CPU_SLEEP_0>; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x3>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- cpu-idle-states = <&CPU_SLEEP_0>; +- }; +- +- l2: cache { +- compatible = "cache"; +- }; +- +- idle-states { +- entry-method = "psci"; +- CPU_SLEEP_0: cpu-sleep-0 { +- compatible = "arm,idle-state"; +- local-timer-stop; +- arm,psci-suspend-param = <0x0010000>; +- entry-latency-us = <75>; +- exit-latency-us = <155>; +- min-residency-us = <1000>; +- }; +- }; +- }; +- +- osc: osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, +- <&cpu1>, +- <&cpu2>, +- <&cpu3>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- soc@f7000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xf7000000 0x1000000>; +- +- gic: interrupt-controller@901000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x901000 0x1000>, +- <0x902000 0x2000>, +- <0x904000 0x2000>, +- <0x906000 0x2000>; +- interrupts = ; +- }; +- +- apb@e80000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xe80000 0x10000>; +- +- uart0: serial@c00 { +- compatible = "snps,dw-apb-uart"; +- reg = <0xc00 0x100>; +- interrupts = ; +- clocks = <&osc>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- gpio0: gpio@1800 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x1800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- porta: gpio-port@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- }; +- +- gpio1: gpio@2000 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x2000 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- portb: gpio-port@1 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = ; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/synaptics/berlin4ct-dmp.dts b/scripts/dtc/include-prefixes/arm64/synaptics/berlin4ct-dmp.dts +deleted file mode 100644 +index c64a179ebbb7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/synaptics/berlin4ct-dmp.dts ++++ /dev/null +@@ -1,29 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2015 Marvell Technology Group Ltd. +- * +- * Author: Jisheng Zhang +- */ +- +-/dts-v1/; +- +-#include "berlin4ct.dtsi" +- +-/ { +- model = "Marvell BG4CT DMP board"; +- compatible = "marvell,berlin4ct-dmp", "marvell,berlin4ct", "marvell,berlin"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@1000000 { +- device_type = "memory"; +- /* the first 16MB is for firmwares' usage */ +- reg = <0 0x01000000 0 0x7f000000>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/synaptics/berlin4ct-stb.dts b/scripts/dtc/include-prefixes/arm64/synaptics/berlin4ct-stb.dts +deleted file mode 100644 +index 277dccfa05cb..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/synaptics/berlin4ct-stb.dts ++++ /dev/null +@@ -1,29 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2015 Marvell Technology Group Ltd. +- * +- * Author: Jisheng Zhang +- */ +- +-/dts-v1/; +- +-#include "berlin4ct.dtsi" +- +-/ { +- model = "Marvell BG4CT STB board"; +- compatible = "marvell,berlin4ct-stb", "marvell,berlin4ct", "marvell,berlin"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@1000000 { +- device_type = "memory"; +- /* the first 16MB is for firmwares' usage */ +- reg = <0 0x01000000 0 0x7f000000>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/synaptics/berlin4ct.dtsi b/scripts/dtc/include-prefixes/arm64/synaptics/berlin4ct.dtsi +deleted file mode 100644 +index 0949acee4728..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/synaptics/berlin4ct.dtsi ++++ /dev/null +@@ -1,314 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2015 Marvell Technology Group Ltd. +- * +- * Author: Jisheng Zhang +- */ +- +-#include +- +-/ { +- compatible = "marvell,berlin4ct", "marvell,berlin"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- serial0 = &uart0; +- }; +- +- psci { +- compatible = "arm,psci-1.0", "arm,psci-0.2"; +- method = "smc"; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x0>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- cpu-idle-states = <&CPU_SLEEP_0>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x1>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- cpu-idle-states = <&CPU_SLEEP_0>; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x2>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- cpu-idle-states = <&CPU_SLEEP_0>; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- reg = <0x3>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- cpu-idle-states = <&CPU_SLEEP_0>; +- }; +- +- l2: cache { +- compatible = "cache"; +- }; +- +- idle-states { +- entry-method = "psci"; +- CPU_SLEEP_0: cpu-sleep-0 { +- compatible = "arm,idle-state"; +- local-timer-stop; +- arm,psci-suspend-param = <0x0010000>; +- entry-latency-us = <75>; +- exit-latency-us = <155>; +- min-residency-us = <1000>; +- }; +- }; +- }; +- +- osc: osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- pmu { +- compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, +- <&cpu1>, +- <&cpu2>, +- <&cpu3>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- soc@f7000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0xf7000000 0x1000000>; +- +- gic: interrupt-controller@901000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x901000 0x1000>, +- <0x902000 0x2000>, +- <0x904000 0x2000>, +- <0x906000 0x2000>; +- interrupts = ; +- }; +- +- apb@e80000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- ranges = <0 0xe80000 0x10000>; +- interrupt-parent = <&aic>; +- +- gpio0: gpio@400 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x0400 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- porta: gpio-port@0 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <0>; +- }; +- }; +- +- gpio1: gpio@800 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x0800 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- portb: gpio-port@1 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <1>; +- }; +- }; +- +- gpio2: gpio@c00 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x0c00 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- portc: gpio-port@2 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <2>; +- }; +- }; +- +- gpio3: gpio@1000 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x1000 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- portd: gpio-port@3 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- reg = <0>; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <3>; +- }; +- }; +- +- aic: interrupt-controller@3800 { +- compatible = "snps,dw-apb-ictl"; +- reg = <0x3800 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +- +- soc_pinctrl: pin-controller@ea8000 { +- compatible = "marvell,berlin4ct-soc-pinctrl"; +- reg = <0xea8000 0x14>; +- }; +- +- avio_pinctrl: pin-controller@ea8400 { +- compatible = "marvell,berlin4ct-avio-pinctrl"; +- reg = <0xea8400 0x8>; +- }; +- +- apb@fc0000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xfc0000 0x10000>; +- interrupt-parent = <&sic>; +- +- sic: interrupt-controller@1000 { +- compatible = "snps,dw-apb-ictl"; +- reg = <0x1000 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- +- wdt0: watchdog@3000 { +- compatible = "snps,dw-wdt"; +- reg = <0x3000 0x100>; +- clocks = <&osc>; +- interrupts = <0>; +- }; +- +- wdt1: watchdog@4000 { +- compatible = "snps,dw-wdt"; +- reg = <0x4000 0x100>; +- clocks = <&osc>; +- interrupts = <1>; +- }; +- +- wdt2: watchdog@5000 { +- compatible = "snps,dw-wdt"; +- reg = <0x5000 0x100>; +- clocks = <&osc>; +- interrupts = <2>; +- }; +- +- sm_gpio0: gpio@8000 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x8000 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- porte: gpio-port@4 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- reg = <0>; +- }; +- }; +- +- sm_gpio1: gpio@9000 { +- compatible = "snps,dw-apb-gpio"; +- reg = <0x9000 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- portf: gpio-port@5 { +- compatible = "snps,dw-apb-gpio-port"; +- gpio-controller; +- #gpio-cells = <2>; +- ngpios = <32>; +- reg = <0>; +- }; +- }; +- +- uart0: uart@d000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0xd000 0x100>; +- interrupts = <8>; +- clocks = <&osc>; +- reg-shift = <2>; +- status = "disabled"; +- pinctrl-0 = <&uart0_pmux>; +- pinctrl-names = "default"; +- }; +- }; +- +- system_pinctrl: pin-controller@fe2200 { +- compatible = "marvell,berlin4ct-system-pinctrl"; +- reg = <0xfe2200 0xc>; +- +- uart0_pmux: uart0-pmux { +- groups = "SM_URT0_TXD", "SM_URT0_RXD"; +- function = "uart0"; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/Makefile b/scripts/dtc/include-prefixes/arm64/ti/Makefile +deleted file mode 100644 +index d56c742f5a10..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/Makefile ++++ /dev/null +@@ -1,19 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-# +-# Make file to build device tree binaries for boards based on +-# Texas Instruments Inc processors +-# +-# Copyright (C) 2016-2021 Texas Instruments Incorporated - https://www.ti.com/ +-# +- +-dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb +-dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb +-dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb +- +-dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb +- +-dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb +- +-dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb +- +-dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-am64-main.dtsi b/scripts/dtc/include-prefixes/arm64/ti/k3-am64-main.dtsi +deleted file mode 100644 +index 42d1d219a3fd..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-am64-main.dtsi ++++ /dev/null +@@ -1,976 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for AM642 SoC Family Main Domain peripherals +- * +- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include +-#include +- +-/ { +- serdes_refclk: clock-cmnrefclk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +-}; +- +-&cbass_main { +- oc_sram: sram@70000000 { +- compatible = "mmio-sram"; +- reg = <0x00 0x70000000 0x00 0x200000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x00 0x70000000 0x200000>; +- +- tfa-sram@1c0000 { +- reg = <0x1c0000 0x20000>; +- }; +- +- dmsc-sram@1e0000 { +- reg = <0x1e0000 0x1c000>; +- }; +- +- sproxy-sram@1fc000 { +- reg = <0x1fc000 0x4000>; +- }; +- }; +- +- main_conf: syscon@43000000 { +- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; +- reg = <0x0 0x43000000 0x0 0x20000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x43000000 0x20000>; +- +- serdes_ln_ctrl: mux-controller { +- compatible = "mmio-mux"; +- #mux-control-cells = <1>; +- mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ +- }; +- }; +- +- gic500: interrupt-controller@1800000 { +- compatible = "arm,gic-v3"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ +- <0x00 0x01840000 0x00 0xC0000>; /* GICR */ +- /* +- * vcpumntirq: +- * virtual CPU interface maintenance interrupt +- */ +- interrupts = ; +- +- gic_its: msi-controller@1820000 { +- compatible = "arm,gic-v3-its"; +- reg = <0x00 0x01820000 0x00 0x10000>; +- socionext,synquacer-pre-its = <0x1000000 0x400000>; +- msi-controller; +- #msi-cells = <1>; +- }; +- }; +- +- dmss: bus@48000000 { +- compatible = "simple-mfd"; +- #address-cells = <2>; +- #size-cells = <2>; +- dma-ranges; +- ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; +- +- ti,sci-dev-id = <25>; +- +- secure_proxy_main: mailbox@4d000000 { +- compatible = "ti,am654-secure-proxy"; +- #mbox-cells = <1>; +- reg-names = "target_data", "rt", "scfg"; +- reg = <0x00 0x4d000000 0x00 0x80000>, +- <0x00 0x4a600000 0x00 0x80000>, +- <0x00 0x4a400000 0x00 0x80000>; +- interrupt-names = "rx_012"; +- interrupts = ; +- }; +- +- inta_main_dmss: interrupt-controller@48000000 { +- compatible = "ti,sci-inta"; +- reg = <0x00 0x48000000 0x00 0x100000>; +- #interrupt-cells = <0>; +- interrupt-controller; +- interrupt-parent = <&gic500>; +- msi-controller; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <28>; +- ti,interrupt-ranges = <4 68 36>; +- ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; +- }; +- +- main_bcdma: dma-controller@485c0100 { +- compatible = "ti,am64-dmss-bcdma"; +- reg = <0x00 0x485c0100 0x00 0x100>, +- <0x00 0x4c000000 0x00 0x20000>, +- <0x00 0x4a820000 0x00 0x20000>, +- <0x00 0x4aa40000 0x00 0x20000>, +- <0x00 0x4bc00000 0x00 0x100000>; +- reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; +- msi-parent = <&inta_main_dmss>; +- #dma-cells = <3>; +- +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <26>; +- ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ +- ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ +- ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ +- }; +- +- main_pktdma: dma-controller@485c0000 { +- compatible = "ti,am64-dmss-pktdma"; +- reg = <0x00 0x485c0000 0x00 0x100>, +- <0x00 0x4a800000 0x00 0x20000>, +- <0x00 0x4aa00000 0x00 0x40000>, +- <0x00 0x4b800000 0x00 0x400000>; +- reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; +- msi-parent = <&inta_main_dmss>; +- #dma-cells = <2>; +- +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <30>; +- ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ +- <0x24>, /* CPSW_TX_CHAN */ +- <0x25>, /* SAUL_TX_0_CHAN */ +- <0x26>, /* SAUL_TX_1_CHAN */ +- <0x27>, /* ICSSG_0_TX_CHAN */ +- <0x28>; /* ICSSG_1_TX_CHAN */ +- ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ +- <0x11>, /* RING_CPSW_TX_CHAN */ +- <0x12>, /* RING_SAUL_TX_0_CHAN */ +- <0x13>, /* RING_SAUL_TX_1_CHAN */ +- <0x14>, /* RING_ICSSG_0_TX_CHAN */ +- <0x15>; /* RING_ICSSG_1_TX_CHAN */ +- ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ +- <0x2b>, /* CPSW_RX_CHAN */ +- <0x2d>, /* SAUL_RX_0_CHAN */ +- <0x2f>, /* SAUL_RX_1_CHAN */ +- <0x31>, /* SAUL_RX_2_CHAN */ +- <0x33>, /* SAUL_RX_3_CHAN */ +- <0x35>, /* ICSSG_0_RX_CHAN */ +- <0x37>; /* ICSSG_1_RX_CHAN */ +- ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ +- <0x2c>, /* FLOW_CPSW_RX_CHAN */ +- <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ +- <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */ +- <0x36>, /* FLOW_ICSSG_0_RX_CHAN */ +- <0x38>; /* FLOW_ICSSG_1_RX_CHAN */ +- }; +- }; +- +- dmsc: system-controller@44043000 { +- compatible = "ti,k2g-sci"; +- ti,host-id = <12>; +- mbox-names = "rx", "tx"; +- mboxes= <&secure_proxy_main 12>, +- <&secure_proxy_main 13>; +- reg-names = "debug_messages"; +- reg = <0x00 0x44043000 0x00 0xfe0>; +- +- k3_pds: power-controller { +- compatible = "ti,sci-pm-domain"; +- #power-domain-cells = <2>; +- }; +- +- k3_clks: clock-controller { +- compatible = "ti,k2g-sci-clk"; +- #clock-cells = <2>; +- }; +- +- k3_reset: reset-controller { +- compatible = "ti,sci-reset"; +- #reset-cells = <2>; +- }; +- }; +- +- main_pmx0: pinctrl@f4000 { +- compatible = "pinctrl-single"; +- reg = <0x00 0xf4000 0x00 0x2d0>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0xffffffff>; +- }; +- +- main_conf: syscon@43000000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x00 0x43000000 0x00 0x20000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00 0x00 0x43000000 0x20000>; +- +- chipid@14 { +- compatible = "ti,am654-chipid"; +- reg = <0x00000014 0x4>; +- }; +- +- phy_gmii_sel: phy@4044 { +- compatible = "ti,am654-phy-gmii-sel"; +- reg = <0x4044 0x8>; +- #phy-cells = <1>; +- }; +- +- epwm_tbclk: clock@4140 { +- compatible = "ti,am64-epwm-tbclk", "syscon"; +- reg = <0x4130 0x4>; +- #clock-cells = <1>; +- }; +- }; +- +- main_uart0: serial@2800000 { +- compatible = "ti,am64-uart", "ti,am654-uart"; +- reg = <0x00 0x02800000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 146 0>; +- clock-names = "fclk"; +- }; +- +- main_uart1: serial@2810000 { +- compatible = "ti,am64-uart", "ti,am654-uart"; +- reg = <0x00 0x02810000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 152 0>; +- clock-names = "fclk"; +- }; +- +- main_uart2: serial@2820000 { +- compatible = "ti,am64-uart", "ti,am654-uart"; +- reg = <0x00 0x02820000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 153 0>; +- clock-names = "fclk"; +- }; +- +- main_uart3: serial@2830000 { +- compatible = "ti,am64-uart", "ti,am654-uart"; +- reg = <0x00 0x02830000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 154 0>; +- clock-names = "fclk"; +- }; +- +- main_uart4: serial@2840000 { +- compatible = "ti,am64-uart", "ti,am654-uart"; +- reg = <0x00 0x02840000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 155 0>; +- clock-names = "fclk"; +- }; +- +- main_uart5: serial@2850000 { +- compatible = "ti,am64-uart", "ti,am654-uart"; +- reg = <0x00 0x02850000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 156 0>; +- clock-names = "fclk"; +- }; +- +- main_uart6: serial@2860000 { +- compatible = "ti,am64-uart", "ti,am654-uart"; +- reg = <0x00 0x02860000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 158 0>; +- clock-names = "fclk"; +- }; +- +- main_i2c0: i2c@20000000 { +- compatible = "ti,am64-i2c", "ti,omap4-i2c"; +- reg = <0x00 0x20000000 0x00 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 102 2>; +- clock-names = "fck"; +- }; +- +- main_i2c1: i2c@20010000 { +- compatible = "ti,am64-i2c", "ti,omap4-i2c"; +- reg = <0x00 0x20010000 0x00 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 103 2>; +- clock-names = "fck"; +- }; +- +- main_i2c2: i2c@20020000 { +- compatible = "ti,am64-i2c", "ti,omap4-i2c"; +- reg = <0x00 0x20020000 0x00 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 104 2>; +- clock-names = "fck"; +- }; +- +- main_i2c3: i2c@20030000 { +- compatible = "ti,am64-i2c", "ti,omap4-i2c"; +- reg = <0x00 0x20030000 0x00 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 105 2>; +- clock-names = "fck"; +- }; +- +- main_spi0: spi@20100000 { +- compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; +- reg = <0x00 0x20100000 0x00 0x400>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 141 0>; +- dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; +- dma-names = "tx0", "rx0"; +- }; +- +- main_spi1: spi@20110000 { +- compatible = "ti,am654-mcspi","ti,omap4-mcspi"; +- reg = <0x00 0x20110000 0x00 0x400>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 142 0>; +- }; +- +- main_spi2: spi@20120000 { +- compatible = "ti,am654-mcspi","ti,omap4-mcspi"; +- reg = <0x00 0x20120000 0x00 0x400>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 143 0>; +- }; +- +- main_spi3: spi@20130000 { +- compatible = "ti,am654-mcspi","ti,omap4-mcspi"; +- reg = <0x00 0x20130000 0x00 0x400>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 144 0>; +- }; +- +- main_spi4: spi@20140000 { +- compatible = "ti,am654-mcspi","ti,omap4-mcspi"; +- reg = <0x00 0x20140000 0x00 0x400>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 145 0>; +- }; +- +- main_gpio_intr: interrupt-controller@a00000 { +- compatible = "ti,sci-intr"; +- reg = <0x00 0x00a00000 0x00 0x800>; +- ti,intr-trigger-type = <1>; +- interrupt-controller; +- interrupt-parent = <&gic500>; +- #interrupt-cells = <1>; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <3>; +- ti,interrupt-ranges = <0 32 16>; +- }; +- +- main_gpio0: gpio@600000 { +- compatible = "ti,am64-gpio", "ti,keystone-gpio"; +- reg = <0x0 0x00600000 0x0 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&main_gpio_intr>; +- interrupts = <190>, <191>, <192>, +- <193>, <194>, <195>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <87>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 77 0>; +- clock-names = "gpio"; +- }; +- +- main_gpio1: gpio@601000 { +- compatible = "ti,am64-gpio", "ti,keystone-gpio"; +- reg = <0x0 0x00601000 0x0 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&main_gpio_intr>; +- interrupts = <180>, <181>, <182>, +- <183>, <184>, <185>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <88>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 78 0>; +- clock-names = "gpio"; +- }; +- +- sdhci0: mmc@fa10000 { +- compatible = "ti,am64-sdhci-8bit"; +- reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; +- interrupts = ; +- power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; +- clock-names = "clk_ahb", "clk_xin"; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- ti,trm-icp = <0x2>; +- ti,otap-del-sel-legacy = <0x0>; +- ti,otap-del-sel-mmc-hs = <0x0>; +- ti,otap-del-sel-ddr52 = <0x6>; +- ti,otap-del-sel-hs200 = <0x7>; +- ti,otap-del-sel-hs400 = <0x4>; +- }; +- +- sdhci1: mmc@fa00000 { +- compatible = "ti,am64-sdhci-4bit"; +- reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; +- interrupts = ; +- power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; +- clock-names = "clk_ahb", "clk_xin"; +- ti,trm-icp = <0x2>; +- ti,otap-del-sel-legacy = <0x0>; +- ti,otap-del-sel-sd-hs = <0xf>; +- ti,otap-del-sel-sdr12 = <0xf>; +- ti,otap-del-sel-sdr25 = <0xf>; +- ti,otap-del-sel-sdr50 = <0xc>; +- ti,otap-del-sel-sdr104 = <0x6>; +- ti,otap-del-sel-ddr50 = <0x9>; +- ti,clkbuf-sel = <0x7>; +- }; +- +- cpsw3g: ethernet@8000000 { +- compatible = "ti,am642-cpsw-nuss"; +- #address-cells = <2>; +- #size-cells = <2>; +- reg = <0x0 0x8000000 0x0 0x200000>; +- reg-names = "cpsw_nuss"; +- ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; +- clocks = <&k3_clks 13 0>; +- assigned-clocks = <&k3_clks 13 1>; +- assigned-clock-parents = <&k3_clks 13 9>; +- clock-names = "fck"; +- power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; +- +- dmas = <&main_pktdma 0xC500 15>, +- <&main_pktdma 0xC501 15>, +- <&main_pktdma 0xC502 15>, +- <&main_pktdma 0xC503 15>, +- <&main_pktdma 0xC504 15>, +- <&main_pktdma 0xC505 15>, +- <&main_pktdma 0xC506 15>, +- <&main_pktdma 0xC507 15>, +- <&main_pktdma 0x4500 15>; +- dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", +- "tx7", "rx"; +- +- ethernet-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpsw_port1: port@1 { +- reg = <1>; +- ti,mac-only; +- label = "port1"; +- phys = <&phy_gmii_sel 1>; +- mac-address = [00 00 00 00 00 00]; +- ti,syscon-efuse = <&main_conf 0x200>; +- }; +- +- cpsw_port2: port@2 { +- reg = <2>; +- ti,mac-only; +- label = "port2"; +- phys = <&phy_gmii_sel 2>; +- mac-address = [00 00 00 00 00 00]; +- }; +- }; +- +- cpsw3g_mdio: mdio@f00 { +- compatible = "ti,cpsw-mdio","ti,davinci_mdio"; +- reg = <0x0 0xf00 0x0 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&k3_clks 13 0>; +- clock-names = "fck"; +- bus_freq = <1000000>; +- }; +- +- cpts@3d000 { +- compatible = "ti,j721e-cpts"; +- reg = <0x0 0x3d000 0x0 0x400>; +- clocks = <&k3_clks 13 1>; +- clock-names = "cpts"; +- interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "cpts"; +- ti,cpts-ext-ts-inputs = <4>; +- ti,cpts-periodic-outputs = <2>; +- }; +- }; +- +- cpts@39000000 { +- compatible = "ti,j721e-cpts"; +- reg = <0x0 0x39000000 0x0 0x400>; +- reg-names = "cpts"; +- power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 84 0>; +- clock-names = "cpts"; +- assigned-clocks = <&k3_clks 84 0>; +- assigned-clock-parents = <&k3_clks 84 8>; +- interrupts = ; +- interrupt-names = "cpts"; +- ti,cpts-periodic-outputs = <6>; +- ti,cpts-ext-ts-inputs = <8>; +- }; +- +- usbss0: cdns-usb@f900000{ +- compatible = "ti,am64-usb"; +- reg = <0x00 0xf900000 0x00 0x100>; +- power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 161 9>, <&k3_clks 161 1>; +- clock-names = "ref", "lpm"; +- assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */ +- assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */ +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- usb0: usb@f400000{ +- compatible = "cdns,usb3"; +- reg = <0x00 0xf400000 0x00 0x10000>, +- <0x00 0xf410000 0x00 0x10000>, +- <0x00 0xf420000 0x00 0x10000>; +- reg-names = "otg", +- "xhci", +- "dev"; +- interrupts = , /* irq.0 */ +- , /* irq.6 */ +- ; /* otgirq */ +- interrupt-names = "host", +- "peripheral", +- "otg"; +- maximum-speed = "super-speed"; +- dr_mode = "otg"; +- }; +- }; +- +- tscadc0: tscadc@28001000 { +- compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; +- reg = <0x00 0x28001000 0x00 0x1000>; +- interrupts = ; +- power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 0 0>; +- assigned-clocks = <&k3_clks 0 0>; +- assigned-clock-parents = <&k3_clks 0 3>; +- assigned-clock-rates = <60000000>; +- clock-names = "adc_tsc_fck"; +- +- adc { +- #io-channel-cells = <1>; +- compatible = "ti,am654-adc", "ti,am3359-adc"; +- }; +- }; +- +- fss: bus@fc00000 { +- compatible = "simple-bus"; +- reg = <0x00 0x0fc00000 0x00 0x70000>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ospi0: spi@fc40000 { +- compatible = "ti,am654-ospi", "cdns,qspi-nor"; +- reg = <0x00 0x0fc40000 0x00 0x100>, +- <0x05 0x00000000 0x01 0x00000000>; +- interrupts = ; +- cdns,fifo-depth = <256>; +- cdns,fifo-width = <4>; +- cdns,trigger-address = <0x0>; +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- clocks = <&k3_clks 75 6>; +- assigned-clocks = <&k3_clks 75 6>; +- assigned-clock-parents = <&k3_clks 75 7>; +- assigned-clock-rates = <166666666>; +- power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; +- }; +- }; +- +- hwspinlock: spinlock@2a000000 { +- compatible = "ti,am64-hwspinlock"; +- reg = <0x00 0x2a000000 0x00 0x1000>; +- #hwlock-cells = <1>; +- }; +- +- mailbox0_cluster2: mailbox@29020000 { +- compatible = "ti,am64-mailbox"; +- reg = <0x00 0x29020000 0x00 0x200>; +- interrupts = , +- ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- }; +- +- mailbox0_cluster3: mailbox@29030000 { +- compatible = "ti,am64-mailbox"; +- reg = <0x00 0x29030000 0x00 0x200>; +- interrupts = , +- ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- }; +- +- mailbox0_cluster4: mailbox@29040000 { +- compatible = "ti,am64-mailbox"; +- reg = <0x00 0x29040000 0x00 0x200>; +- interrupts = , +- ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- }; +- +- mailbox0_cluster5: mailbox@29050000 { +- compatible = "ti,am64-mailbox"; +- reg = <0x00 0x29050000 0x00 0x200>; +- interrupts = , +- ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- }; +- +- mailbox0_cluster6: mailbox@29060000 { +- compatible = "ti,am64-mailbox"; +- reg = <0x00 0x29060000 0x00 0x200>; +- interrupts = ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- }; +- +- mailbox0_cluster7: mailbox@29070000 { +- compatible = "ti,am64-mailbox"; +- reg = <0x00 0x29070000 0x00 0x200>; +- interrupts = ; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- }; +- +- main_r5fss0: r5fss@78000000 { +- compatible = "ti,am64-r5fss"; +- ti,cluster-mode = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x78000000 0x00 0x78000000 0x10000>, +- <0x78100000 0x00 0x78100000 0x10000>, +- <0x78200000 0x00 0x78200000 0x08000>, +- <0x78300000 0x00 0x78300000 0x08000>; +- power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; +- +- main_r5fss0_core0: r5f@78000000 { +- compatible = "ti,am64-r5f"; +- reg = <0x78000000 0x00010000>, +- <0x78100000 0x00010000>; +- reg-names = "atcm", "btcm"; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <121>; +- ti,sci-proc-ids = <0x01 0xff>; +- resets = <&k3_reset 121 1>; +- firmware-name = "am64-main-r5f0_0-fw"; +- ti,atcm-enable = <1>; +- ti,btcm-enable = <1>; +- ti,loczrama = <1>; +- }; +- +- main_r5fss0_core1: r5f@78200000 { +- compatible = "ti,am64-r5f"; +- reg = <0x78200000 0x00008000>, +- <0x78300000 0x00008000>; +- reg-names = "atcm", "btcm"; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <122>; +- ti,sci-proc-ids = <0x02 0xff>; +- resets = <&k3_reset 122 1>; +- firmware-name = "am64-main-r5f0_1-fw"; +- ti,atcm-enable = <1>; +- ti,btcm-enable = <1>; +- ti,loczrama = <1>; +- }; +- }; +- +- main_r5fss1: r5fss@78400000 { +- compatible = "ti,am64-r5fss"; +- ti,cluster-mode = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x78400000 0x00 0x78400000 0x10000>, +- <0x78500000 0x00 0x78500000 0x10000>, +- <0x78600000 0x00 0x78600000 0x08000>, +- <0x78700000 0x00 0x78700000 0x08000>; +- power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; +- +- main_r5fss1_core0: r5f@78400000 { +- compatible = "ti,am64-r5f"; +- reg = <0x78400000 0x00010000>, +- <0x78500000 0x00010000>; +- reg-names = "atcm", "btcm"; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <123>; +- ti,sci-proc-ids = <0x06 0xff>; +- resets = <&k3_reset 123 1>; +- firmware-name = "am64-main-r5f1_0-fw"; +- ti,atcm-enable = <1>; +- ti,btcm-enable = <1>; +- ti,loczrama = <1>; +- }; +- +- main_r5fss1_core1: r5f@78600000 { +- compatible = "ti,am64-r5f"; +- reg = <0x78600000 0x00008000>, +- <0x78700000 0x00008000>; +- reg-names = "atcm", "btcm"; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <124>; +- ti,sci-proc-ids = <0x07 0xff>; +- resets = <&k3_reset 124 1>; +- firmware-name = "am64-main-r5f1_1-fw"; +- ti,atcm-enable = <1>; +- ti,btcm-enable = <1>; +- ti,loczrama = <1>; +- }; +- }; +- +- serdes_wiz0: wiz@f000000 { +- compatible = "ti,am64-wiz-10g"; +- #address-cells = <1>; +- #size-cells = <1>; +- power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>; +- clock-names = "fck", "core_ref_clk", "ext_ref_clk"; +- num-lanes = <1>; +- #reset-cells = <1>; +- #clock-cells = <1>; +- ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; +- +- assigned-clocks = <&k3_clks 162 1>; +- assigned-clock-parents = <&k3_clks 162 5>; +- +- serdes0: serdes@f000000 { +- compatible = "ti,j721e-serdes-10g"; +- reg = <0x0f000000 0x00010000>; +- reg-names = "torrent_phy"; +- resets = <&serdes_wiz0 0>; +- reset-names = "torrent_reset"; +- clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, +- <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; +- clock-names = "refclk", "phy_en_refclk"; +- assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, +- <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, +- <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; +- assigned-clock-parents = <&k3_clks 162 1>, +- <&k3_clks 162 1>, +- <&k3_clks 162 1>; +- #address-cells = <1>; +- #size-cells = <0>; +- #clock-cells = <1>; +- }; +- }; +- +- pcie0_rc: pcie@f102000 { +- compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host"; +- reg = <0x00 0x0f102000 0x00 0x1000>, +- <0x00 0x0f100000 0x00 0x400>, +- <0x00 0x0d000000 0x00 0x00800000>, +- <0x00 0x68000000 0x00 0x00001000>; +- reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; +- interrupt-names = "link_state"; +- interrupts = ; +- device_type = "pci"; +- ti,syscon-pcie-ctrl = <&main_conf 0x4070>; +- max-link-speed = <2>; +- num-lanes = <1>; +- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; +- clock-names = "fck", "pcie_refclk"; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x0 0xff>; +- cdns,no-bar-match-nbits = <64>; +- vendor-id = <0x104c>; +- device-id = <0xb010>; +- msi-map = <0x0 &gic_its 0x0 0x10000>; +- ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, +- <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; +- dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; +- }; +- +- pcie0_ep: pcie-ep@f102000 { +- compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep"; +- reg = <0x00 0x0f102000 0x00 0x1000>, +- <0x00 0x0f100000 0x00 0x400>, +- <0x00 0x0d000000 0x00 0x00800000>, +- <0x00 0x68000000 0x00 0x08000000>; +- reg-names = "intd_cfg", "user_cfg", "reg", "mem"; +- interrupt-names = "link_state"; +- interrupts = ; +- ti,syscon-pcie-ctrl = <&main_conf 0x4070>; +- max-link-speed = <2>; +- num-lanes = <1>; +- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 114 0>; +- clock-names = "fck"; +- max-functions = /bits/ 8 <1>; +- }; +- +- epwm0: pwm@23000000 { +- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x23000000 0x0 0x100>; +- power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; +- clock-names = "tbclk", "fck"; +- }; +- +- epwm1: pwm@23010000 { +- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x23010000 0x0 0x100>; +- power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; +- clock-names = "tbclk", "fck"; +- }; +- +- epwm2: pwm@23020000 { +- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x23020000 0x0 0x100>; +- power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; +- clock-names = "tbclk", "fck"; +- }; +- +- epwm3: pwm@23030000 { +- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x23030000 0x0 0x100>; +- power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>; +- clock-names = "tbclk", "fck"; +- }; +- +- epwm4: pwm@23040000 { +- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x23040000 0x0 0x100>; +- power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>; +- clock-names = "tbclk", "fck"; +- }; +- +- epwm5: pwm@23050000 { +- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x23050000 0x0 0x100>; +- power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>; +- clock-names = "tbclk", "fck"; +- }; +- +- epwm6: pwm@23060000 { +- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x23060000 0x0 0x100>; +- power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>; +- clock-names = "tbclk", "fck"; +- }; +- +- epwm7: pwm@23070000 { +- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x23070000 0x0 0x100>; +- power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>; +- clock-names = "tbclk", "fck"; +- }; +- +- epwm8: pwm@23080000 { +- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x23080000 0x0 0x100>; +- power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; +- clock-names = "tbclk", "fck"; +- }; +- +- ecap0: pwm@23100000 { +- compatible = "ti,am64-ecap", "ti,am3352-ecap"; +- #pwm-cells = <3>; +- reg = <0x0 0x23100000 0x0 0x60>; +- power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 51 0>; +- clock-names = "fck"; +- }; +- +- ecap1: pwm@23110000 { +- compatible = "ti,am64-ecap", "ti,am3352-ecap"; +- #pwm-cells = <3>; +- reg = <0x0 0x23110000 0x0 0x60>; +- power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 52 0>; +- clock-names = "fck"; +- }; +- +- ecap2: pwm@23120000 { +- compatible = "ti,am64-ecap", "ti,am3352-ecap"; +- #pwm-cells = <3>; +- reg = <0x0 0x23120000 0x0 0x60>; +- power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 53 0>; +- clock-names = "fck"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-am64-mcu.dtsi b/scripts/dtc/include-prefixes/arm64/ti/k3-am64-mcu.dtsi +deleted file mode 100644 +index 59cc58f7d0c8..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-am64-mcu.dtsi ++++ /dev/null +@@ -1,100 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for AM64 SoC Family MCU Domain peripherals +- * +- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-&cbass_mcu { +- mcu_uart0: serial@4a00000 { +- compatible = "ti,am64-uart", "ti,am654-uart"; +- reg = <0x00 0x04a00000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 149 0>; +- clock-names = "fclk"; +- }; +- +- mcu_uart1: serial@4a10000 { +- compatible = "ti,am64-uart", "ti,am654-uart"; +- reg = <0x00 0x04a10000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 160 0>; +- clock-names = "fclk"; +- }; +- +- mcu_i2c0: i2c@4900000 { +- compatible = "ti,am64-i2c", "ti,omap4-i2c"; +- reg = <0x00 0x04900000 0x00 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 106 2>; +- clock-names = "fck"; +- }; +- +- mcu_i2c1: i2c@4910000 { +- compatible = "ti,am64-i2c", "ti,omap4-i2c"; +- reg = <0x00 0x04910000 0x00 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 107 2>; +- clock-names = "fck"; +- }; +- +- mcu_spi0: spi@4b00000 { +- compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; +- reg = <0x00 0x04b00000 0x00 0x400>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 147 0>; +- }; +- +- mcu_spi1: spi@4b10000 { +- compatible = "ti,am654-mcspi","ti,omap4-mcspi"; +- reg = <0x00 0x04b10000 0x00 0x400>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 148 0>; +- }; +- +- mcu_gpio_intr: interrupt-controller@4210000 { +- compatible = "ti,sci-intr"; +- reg = <0x00 0x04210000 0x00 0x200>; +- ti,intr-trigger-type = <1>; +- interrupt-controller; +- interrupt-parent = <&gic500>; +- #interrupt-cells = <1>; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <5>; +- ti,interrupt-ranges = <0 104 4>; +- }; +- +- mcu_gpio0: gpio@4201000 { +- compatible = "ti,am64-gpio", "ti,keystone-gpio"; +- reg = <0x0 0x4201000 0x0 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&mcu_gpio_intr>; +- interrupts = <30>, <31>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <23>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 79 0>; +- clock-names = "gpio"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-am64.dtsi b/scripts/dtc/include-prefixes/arm64/ti/k3-am64.dtsi +deleted file mode 100644 +index de6805b0c72c..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-am64.dtsi ++++ /dev/null +@@ -1,105 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for AM642 SoC Family +- * +- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- model = "Texas Instruments K3 AM642 SoC"; +- compatible = "ti,am642"; +- interrupt-parent = <&gic500>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- serial0 = &mcu_uart0; +- serial1 = &mcu_uart1; +- serial2 = &main_uart0; +- serial3 = &main_uart1; +- serial4 = &main_uart2; +- serial5 = &main_uart3; +- serial6 = &main_uart4; +- serial7 = &main_uart5; +- serial8 = &main_uart6; +- ethernet0 = &cpsw_port1; +- ethernet1 = &cpsw_port2; +- }; +- +- chosen { }; +- +- firmware { +- optee { +- compatible = "linaro,optee-tz"; +- method = "smc"; +- }; +- +- psci: psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- }; +- +- a53_timer0: timer-cl0-cpu0 { +- compatible = "arm,armv8-timer"; +- interrupts = , /* cntpsirq */ +- , /* cntpnsirq */ +- , /* cntvirq */ +- ; /* cnthpirq */ +- }; +- +- pmu: pmu { +- compatible = "arm,cortex-a53-pmu"; +- interrupts = ; +- }; +- +- cbass_main: bus@f4000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */ +- <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ +- <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ +- <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ +- <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ +- <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */ +- <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */ +- <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ +- <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */ +- <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */ +- <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */ +- <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */ +- <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */ +- <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */ +- <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */ +- <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ +- <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */ +- <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */ +- <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ +- <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */ +- <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */ +- <0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */ +- <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */ +- <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ +- +- /* MCU Domain Range */ +- <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; +- +- cbass_mcu: bus@4000000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ +- }; +- }; +-}; +- +-/* Now include the peripherals for each bus segments */ +-#include "k3-am64-main.dtsi" +-#include "k3-am64-mcu.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-am642-evm.dts b/scripts/dtc/include-prefixes/arm64/ti/k3-am642-evm.dts +deleted file mode 100644 +index 24ce4942618d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-am642-evm.dts ++++ /dev/null +@@ -1,632 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include +-#include +-#include "k3-am642.dtsi" +- +-/ { +- compatible = "ti,am642-evm", "ti,am642"; +- model = "Texas Instruments AM642 EVM"; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- /* 2G RAM */ +- reg = <0x00000000 0x80000000 0x00000000 0x80000000>; +- +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- secure_ddr: optee@9e800000 { +- reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ +- alignment = <0x1000>; +- no-map; +- }; +- +- main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa0000000 0x00 0x100000>; +- no-map; +- }; +- +- main_r5fss0_core0_memory_region: r5f-memory@a0100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa0100000 0x00 0xf00000>; +- no-map; +- }; +- +- main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa1000000 0x00 0x100000>; +- no-map; +- }; +- +- main_r5fss0_core1_memory_region: r5f-memory@a1100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa1100000 0x00 0xf00000>; +- no-map; +- }; +- +- main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa2000000 0x00 0x100000>; +- no-map; +- }; +- +- main_r5fss1_core0_memory_region: r5f-memory@a2100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa2100000 0x00 0xf00000>; +- no-map; +- }; +- +- main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa3000000 0x00 0x100000>; +- no-map; +- }; +- +- main_r5fss1_core1_memory_region: r5f-memory@a3100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa3100000 0x00 0xf00000>; +- no-map; +- }; +- +- rtos_ipc_memory_region: ipc-memories@a5000000 { +- reg = <0x00 0xa5000000 0x00 0x00800000>; +- alignment = <0x1000>; +- no-map; +- }; +- }; +- +- evm_12v0: fixedregulator-evm12v0 { +- /* main DC jack */ +- compatible = "regulator-fixed"; +- regulator-name = "evm_12v0"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vsys_5v0: fixedregulator-vsys5v0 { +- /* output of LM5140 */ +- compatible = "regulator-fixed"; +- regulator-name = "vsys_5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&evm_12v0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vsys_3v3: fixedregulator-vsys3v3 { +- /* output of LM5140 */ +- compatible = "regulator-fixed"; +- regulator-name = "vsys_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&evm_12v0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_mmc1: fixed-regulator-sd { +- /* TPS2051BD */ +- compatible = "regulator-fixed"; +- regulator-name = "vdd_mmc1"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- enable-active-high; +- vin-supply = <&vsys_3v3>; +- gpio = <&exp1 6 GPIO_ACTIVE_HIGH>; +- }; +- +- vddb: fixedregulator-vddb { +- compatible = "regulator-fixed"; +- regulator-name = "vddb_3v3_display"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vsys_3v3>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- label = "am64-evm:red:heartbeat"; +- gpios = <&exp1 16 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- function = LED_FUNCTION_HEARTBEAT; +- default-state = "off"; +- }; +- }; +- +- mdio_mux: mux-controller { +- compatible = "gpio-mux"; +- #mux-control-cells = <0>; +- +- mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>; +- }; +- +- mdio-mux-1 { +- compatible = "mdio-mux-multiplexer"; +- mux-controls = <&mdio_mux>; +- mdio-parent-bus = <&cpsw3g_mdio>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- mdio@1 { +- reg = <0x1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpsw3g_phy3: ethernet-phy@3 { +- reg = <3>; +- }; +- }; +- }; +-}; +- +-&main_pmx0 { +- main_mmc1_pins_default: main-mmc1-pins-default { +- pinctrl-single,pins = < +- AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ +- AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ +- AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ +- AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ +- AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ +- AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ +- AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ +- AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */ +- AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */ +- >; +- }; +- +- main_uart0_pins_default: main-uart0-pins-default { +- pinctrl-single,pins = < +- AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ +- AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ +- AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ +- AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ +- >; +- }; +- +- main_spi0_pins_default: main-spi0-pins-default { +- pinctrl-single,pins = < +- AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */ +- AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */ +- AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */ +- AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ +- >; +- }; +- +- main_i2c1_pins_default: main-i2c1-pins-default { +- pinctrl-single,pins = < +- AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ +- AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ +- >; +- }; +- +- mdio1_pins_default: mdio1-pins-default { +- pinctrl-single,pins = < +- AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ +- AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ +- >; +- }; +- +- rgmii1_pins_default: rgmii1-pins-default { +- pinctrl-single,pins = < +- AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ +- AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ +- AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */ +- AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */ +- AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ +- AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ +- AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ +- AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ +- AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ +- AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ +- AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ +- AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ +- >; +- }; +- +- rgmii2_pins_default: rgmii2-pins-default { +- pinctrl-single,pins = < +- AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ +- AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ +- AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ +- AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ +- AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ +- AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ +- AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ +- AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ +- AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ +- AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ +- AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ +- AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ +- >; +- }; +- +- main_usb0_pins_default: main-usb0-pins-default { +- pinctrl-single,pins = < +- AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ +- >; +- }; +- +- ospi0_pins_default: ospi0-pins-default { +- pinctrl-single,pins = < +- AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ +- AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ +- AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ +- AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ +- AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ +- AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ +- AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ +- AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ +- AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ +- AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ +- AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ +- >; +- }; +- +- main_ecap0_pins_default: main-ecap0-pins-default { +- pinctrl-single,pins = < +- AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ +- >; +- }; +-}; +- +-&main_uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_uart0_pins_default>; +-}; +- +-/* main_uart1 is reserved for firmware usage */ +-&main_uart1 { +- status = "reserved"; +-}; +- +-&main_uart2 { +- status = "disabled"; +-}; +- +-&main_uart3 { +- status = "disabled"; +-}; +- +-&main_uart4 { +- status = "disabled"; +-}; +- +-&main_uart5 { +- status = "disabled"; +-}; +- +-&main_uart6 { +- status = "disabled"; +-}; +- +-&mcu_uart0 { +- status = "disabled"; +-}; +- +-&mcu_uart1 { +- status = "disabled"; +-}; +- +-&main_i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_i2c1_pins_default>; +- clock-frequency = <400000>; +- +- exp1: gpio@22 { +- compatible = "ti,tca6424"; +- reg = <0x22>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL", +- "GPIO_CPSW1_RST", "GPIO_RGMII1_RST", +- "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT", +- "MMC1_SD_EN", "FSI_FET_SEL", +- "MCAN0_STB_3V3", "MCAN1_STB_3V3", +- "CPSW_FET_SEL", "CPSW_FET2_SEL", +- "PRG1_RGMII2_FET_SEL", "TEST_GPIO2", +- "GPIO_OLED_RESETn", "VPP_LDO_EN", +- "TEST_LED1", "TP92", "TP90", "TP88", +- "TP87", "TP86", "TP89", "TP91"; +- }; +- +- /* osd9616p0899-10 */ +- display@3c { +- compatible = "solomon,ssd1306fb-i2c"; +- reg = <0x3c>; +- reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>; +- vbat-supply = <&vddb>; +- solomon,height = <16>; +- solomon,width = <96>; +- solomon,com-seq; +- solomon,com-invdir; +- solomon,page-offset = <0>; +- solomon,prechargep1 = <2>; +- solomon,prechargep2 = <13>; +- }; +-}; +- +-/* mcu_gpio0 is reserved for mcu firmware usage */ +-&mcu_gpio0 { +- status = "reserved"; +-}; +- +-&mcu_i2c0 { +- status = "disabled"; +-}; +- +-&mcu_i2c1 { +- status = "disabled"; +-}; +- +-&mcu_spi0 { +- status = "disabled"; +-}; +- +-&mcu_spi1 { +- status = "disabled"; +-}; +- +-&main_spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_spi0_pins_default>; +- ti,pindir-d0-out-d1-in; +- eeprom@0 { +- compatible = "microchip,93lc46b"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- spi-cs-high; +- data-size = <16>; +- }; +-}; +- +-&sdhci0 { +- /* emmc */ +- bus-width = <8>; +- non-removable; +- ti,driver-strength-ohm = <50>; +- disable-wp; +-}; +- +-&sdhci1 { +- /* SD/MMC */ +- vmmc-supply = <&vdd_mmc1>; +- pinctrl-names = "default"; +- bus-width = <4>; +- pinctrl-0 = <&main_mmc1_pins_default>; +- ti,driver-strength-ohm = <50>; +- disable-wp; +-}; +- +-&usbss0 { +- ti,vbus-divider; +- ti,usb2-only; +-}; +- +-&usb0 { +- dr_mode = "otg"; +- maximum-speed = "high-speed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&main_usb0_pins_default>; +-}; +- +-&cpsw3g { +- pinctrl-names = "default"; +- pinctrl-0 = <&mdio1_pins_default +- &rgmii1_pins_default +- &rgmii2_pins_default>; +-}; +- +-&cpsw_port1 { +- phy-mode = "rgmii-rxid"; +- phy-handle = <&cpsw3g_phy0>; +-}; +- +-&cpsw_port2 { +- phy-mode = "rgmii-rxid"; +- phy-handle = <&cpsw3g_phy3>; +-}; +- +-&cpsw3g_mdio { +- cpsw3g_phy0: ethernet-phy@0 { +- reg = <0>; +- ti,rx-internal-delay = ; +- ti,fifo-depth = ; +- }; +-}; +- +-&tscadc0 { +- /* ADC is reserved for R5 usage */ +- status = "reserved"; +-}; +- +-&ospi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ospi0_pins_default>; +- +- flash@0{ +- compatible = "jedec,spi-nor"; +- reg = <0x0>; +- spi-tx-bus-width = <8>; +- spi-rx-bus-width = <8>; +- spi-max-frequency = <25000000>; +- cdns,tshsl-ns = <60>; +- cdns,tsd2d-ns = <60>; +- cdns,tchsh-ns = <60>; +- cdns,tslch-ns = <60>; +- cdns,read-delay = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&mailbox0_cluster2 { +- mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { +- ti,mbox-rx = <0 0 2>; +- ti,mbox-tx = <1 0 2>; +- }; +- +- mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { +- ti,mbox-rx = <2 0 2>; +- ti,mbox-tx = <3 0 2>; +- }; +-}; +- +-&mailbox0_cluster3 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster4 { +- mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { +- ti,mbox-rx = <0 0 2>; +- ti,mbox-tx = <1 0 2>; +- }; +- +- mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { +- ti,mbox-rx = <2 0 2>; +- ti,mbox-tx = <3 0 2>; +- }; +-}; +- +-&mailbox0_cluster5 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster6 { +- mbox_m4_0: mbox-m4-0 { +- ti,mbox-rx = <0 0 2>; +- ti,mbox-tx = <1 0 2>; +- }; +-}; +- +-&mailbox0_cluster7 { +- status = "disabled"; +-}; +- +-&main_r5fss0_core0 { +- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; +- memory-region = <&main_r5fss0_core0_dma_memory_region>, +- <&main_r5fss0_core0_memory_region>; +-}; +- +-&main_r5fss0_core1 { +- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; +- memory-region = <&main_r5fss0_core1_dma_memory_region>, +- <&main_r5fss0_core1_memory_region>; +-}; +- +-&main_r5fss1_core0 { +- mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; +- memory-region = <&main_r5fss1_core0_dma_memory_region>, +- <&main_r5fss1_core0_memory_region>; +-}; +- +-&main_r5fss1_core1 { +- mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; +- memory-region = <&main_r5fss1_core1_dma_memory_region>, +- <&main_r5fss1_core1_memory_region>; +-}; +- +-&serdes_ln_ctrl { +- idle-states = ; +-}; +- +-&serdes0 { +- serdes0_pcie_link: phy@0 { +- reg = <0>; +- cdns,num-lanes = <1>; +- #phy-cells = <0>; +- cdns,phy-type = ; +- resets = <&serdes_wiz0 1>; +- }; +-}; +- +-&pcie0_rc { +- reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; +- phys = <&serdes0_pcie_link>; +- phy-names = "pcie-phy"; +- num-lanes = <1>; +-}; +- +-&pcie0_ep { +- phys = <&serdes0_pcie_link>; +- phy-names = "pcie-phy"; +- num-lanes = <1>; +- status = "disabled"; +-}; +- +-&ecap0 { +- /* PWM is available on Pin 1 of header J12 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&main_ecap0_pins_default>; +-}; +- +-&ecap1 { +- status = "disabled"; +-}; +- +-&ecap2 { +- status = "disabled"; +-}; +- +-&epwm0 { +- status = "disabled"; +-}; +- +-&epwm1 { +- status = "disabled"; +-}; +- +-&epwm2 { +- status = "disabled"; +-}; +- +-&epwm3 { +- status = "disabled"; +-}; +- +-&epwm4 { +- status = "disabled"; +-}; +- +-&epwm5 { +- status = "disabled"; +-}; +- +-&epwm6 { +- status = "disabled"; +-}; +- +-&epwm7 { +- status = "disabled"; +-}; +- +-&epwm8 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-am642-sk.dts b/scripts/dtc/include-prefixes/arm64/ti/k3-am642-sk.dts +deleted file mode 100644 +index 6b45cdeeeefa..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-am642-sk.dts ++++ /dev/null +@@ -1,519 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include +-#include "k3-am642.dtsi" +- +-/ { +- compatible = "ti,am642-sk", "ti,am642"; +- model = "Texas Instruments AM642 SK"; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- /* 2G RAM */ +- reg = <0x00000000 0x80000000 0x00000000 0x80000000>; +- +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- secure_ddr: optee@9e800000 { +- reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ +- alignment = <0x1000>; +- no-map; +- }; +- +- main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa0000000 0x00 0x100000>; +- no-map; +- }; +- +- main_r5fss0_core0_memory_region: r5f-memory@a0100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa0100000 0x00 0xf00000>; +- no-map; +- }; +- +- main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa1000000 0x00 0x100000>; +- no-map; +- }; +- +- main_r5fss0_core1_memory_region: r5f-memory@a1100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa1100000 0x00 0xf00000>; +- no-map; +- }; +- +- main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa2000000 0x00 0x100000>; +- no-map; +- }; +- +- main_r5fss1_core0_memory_region: r5f-memory@a2100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa2100000 0x00 0xf00000>; +- no-map; +- }; +- +- main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa3000000 0x00 0x100000>; +- no-map; +- }; +- +- main_r5fss1_core1_memory_region: r5f-memory@a3100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa3100000 0x00 0xf00000>; +- no-map; +- }; +- +- rtos_ipc_memory_region: ipc-memories@a5000000 { +- reg = <0x00 0xa5000000 0x00 0x00800000>; +- alignment = <0x1000>; +- no-map; +- }; +- }; +- +- vusb_main: fixed-regulator-vusb-main5v0 { +- /* USB MAIN INPUT 5V DC */ +- compatible = "regulator-fixed"; +- regulator-name = "vusb_main5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc_3v3_sys: fixedregulator-vcc-3v3-sys { +- /* output of LP8733xx */ +- compatible = "regulator-fixed"; +- regulator-name = "vcc_3v3_sys"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vusb_main>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_mmc1: fixed-regulator-sd { +- /* TPS2051BD */ +- compatible = "regulator-fixed"; +- regulator-name = "vdd_mmc1"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- enable-active-high; +- vin-supply = <&vcc_3v3_sys>; +- gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&main_pmx0 { +- main_mmc1_pins_default: main-mmc1-pins-default { +- pinctrl-single,pins = < +- AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */ +- AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */ +- AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */ +- AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */ +- AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */ +- AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */ +- AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */ +- AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */ +- >; +- }; +- +- main_usb0_pins_default: main-usb0-pins-default { +- pinctrl-single,pins = < +- AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ +- >; +- }; +- +- main_i2c1_pins_default: main-i2c1-pins-default { +- pinctrl-single,pins = < +- AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ +- AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ +- >; +- }; +- +- mdio1_pins_default: mdio1-pins-default { +- pinctrl-single,pins = < +- AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ +- AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ +- >; +- }; +- +- rgmii1_pins_default: rgmii1-pins-default { +- pinctrl-single,pins = < +- AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */ +- AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */ +- AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */ +- AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */ +- AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */ +- AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */ +- AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ +- AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ +- AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ +- AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ +- AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ +- AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ +- >; +- }; +- +- rgmii2_pins_default: rgmii2-pins-default { +- pinctrl-single,pins = < +- AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ +- AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ +- AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ +- AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ +- AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ +- AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ +- AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ +- AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ +- AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ +- AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ +- AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ +- AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ +- >; +- }; +- +- ospi0_pins_default: ospi0-pins-default { +- pinctrl-single,pins = < +- AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ +- AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ +- AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ +- AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ +- AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ +- AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ +- AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ +- AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ +- AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ +- AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ +- AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ +- >; +- }; +- +- main_ecap0_pins_default: main-ecap0-pins-default { +- pinctrl-single,pins = < +- AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ +- >; +- }; +-}; +- +-&mcu_uart0 { +- status = "disabled"; +-}; +- +-&mcu_uart1 { +- status = "disabled"; +-}; +- +-&main_uart1 { +- /* main_uart1 is reserved for firmware usage */ +- status = "reserved"; +-}; +- +-&main_uart2 { +- status = "disabled"; +-}; +- +-&main_uart3 { +- status = "disabled"; +-}; +- +-&main_uart4 { +- status = "disabled"; +-}; +- +-&main_uart5 { +- status = "disabled"; +-}; +- +-&main_uart6 { +- status = "disabled"; +-}; +- +-&mcu_i2c0 { +- status = "disabled"; +-}; +- +-&mcu_i2c1 { +- status = "disabled"; +-}; +- +-&main_i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_i2c1_pins_default>; +- clock-frequency = <400000>; +- +- exp1: gpio@70 { +- compatible = "nxp,pca9538"; +- reg = <0x70>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", +- "PRU_DETECT", "MMC1_SD_EN", +- "VPP_LDO_EN", "RPI_PS_3V3_En", +- "RPI_PS_5V0_En", "RPI_HAT_DETECT"; +- }; +-}; +- +-&main_i2c3 { +- status = "disabled"; +-}; +- +-&mcu_spi0 { +- status = "disabled"; +-}; +- +-&mcu_spi1 { +- status = "disabled"; +-}; +- +-/* mcu_gpio0 is reserved for mcu firmware usage */ +-&mcu_gpio0 { +- status = "reserved"; +-}; +- +-&sdhci1 { +- /* SD/MMC */ +- vmmc-supply = <&vdd_mmc1>; +- pinctrl-names = "default"; +- bus-width = <4>; +- pinctrl-0 = <&main_mmc1_pins_default>; +- ti,driver-strength-ohm = <50>; +- disable-wp; +-}; +- +-&serdes_ln_ctrl { +- idle-states = ; +-}; +- +-&serdes0 { +- serdes0_usb_link: phy@0 { +- reg = <0>; +- cdns,num-lanes = <1>; +- #phy-cells = <0>; +- cdns,phy-type = ; +- resets = <&serdes_wiz0 1>; +- }; +-}; +- +-&usbss0 { +- ti,vbus-divider; +-}; +- +-&usb0 { +- dr_mode = "host"; +- maximum-speed = "super-speed"; +- pinctrl-names = "default"; +- pinctrl-0 = <&main_usb0_pins_default>; +- phys = <&serdes0_usb_link>; +- phy-names = "cdns3,usb3-phy"; +-}; +- +-&cpsw3g { +- pinctrl-names = "default"; +- pinctrl-0 = <&mdio1_pins_default +- &rgmii1_pins_default +- &rgmii2_pins_default>; +-}; +- +-&cpsw_port1 { +- phy-mode = "rgmii-rxid"; +- phy-handle = <&cpsw3g_phy0>; +-}; +- +-&cpsw_port2 { +- phy-mode = "rgmii-rxid"; +- phy-handle = <&cpsw3g_phy1>; +-}; +- +-&cpsw3g_mdio { +- cpsw3g_phy0: ethernet-phy@0 { +- reg = <0>; +- ti,rx-internal-delay = ; +- ti,fifo-depth = ; +- }; +- +- cpsw3g_phy1: ethernet-phy@1 { +- reg = <1>; +- ti,rx-internal-delay = ; +- ti,fifo-depth = ; +- }; +-}; +- +-&tscadc0 { +- status = "disabled"; +-}; +- +-&ospi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ospi0_pins_default>; +- +- flash@0{ +- compatible = "jedec,spi-nor"; +- reg = <0x0>; +- spi-tx-bus-width = <8>; +- spi-rx-bus-width = <8>; +- spi-max-frequency = <25000000>; +- cdns,tshsl-ns = <60>; +- cdns,tsd2d-ns = <60>; +- cdns,tchsh-ns = <60>; +- cdns,tslch-ns = <60>; +- cdns,read-delay = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&mailbox0_cluster2 { +- mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { +- ti,mbox-rx = <0 0 2>; +- ti,mbox-tx = <1 0 2>; +- }; +- +- mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { +- ti,mbox-rx = <2 0 2>; +- ti,mbox-tx = <3 0 2>; +- }; +-}; +- +-&mailbox0_cluster3 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster4 { +- mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { +- ti,mbox-rx = <0 0 2>; +- ti,mbox-tx = <1 0 2>; +- }; +- +- mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { +- ti,mbox-rx = <2 0 2>; +- ti,mbox-tx = <3 0 2>; +- }; +-}; +- +-&mailbox0_cluster5 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster6 { +- mbox_m4_0: mbox-m4-0 { +- ti,mbox-rx = <0 0 2>; +- ti,mbox-tx = <1 0 2>; +- }; +-}; +- +-&mailbox0_cluster7 { +- status = "disabled"; +-}; +- +-&main_r5fss0_core0 { +- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; +- memory-region = <&main_r5fss0_core0_dma_memory_region>, +- <&main_r5fss0_core0_memory_region>; +-}; +- +-&main_r5fss0_core1 { +- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; +- memory-region = <&main_r5fss0_core1_dma_memory_region>, +- <&main_r5fss0_core1_memory_region>; +-}; +- +-&main_r5fss1_core0 { +- mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; +- memory-region = <&main_r5fss1_core0_dma_memory_region>, +- <&main_r5fss1_core0_memory_region>; +-}; +- +-&main_r5fss1_core1 { +- mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; +- memory-region = <&main_r5fss1_core1_dma_memory_region>, +- <&main_r5fss1_core1_memory_region>; +-}; +- +-&pcie0_rc { +- status = "disabled"; +-}; +- +-&pcie0_ep { +- status = "disabled"; +-}; +- +-&ecap0 { +- /* PWM is available on Pin 1 of header J3 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&main_ecap0_pins_default>; +-}; +- +-&ecap1 { +- status = "disabled"; +-}; +- +-&ecap2 { +- status = "disabled"; +-}; +- +-&epwm0 { +- status = "disabled"; +-}; +- +-&epwm1 { +- status = "disabled"; +-}; +- +-&epwm2 { +- status = "disabled"; +-}; +- +-&epwm3 { +- status = "disabled"; +-}; +- +-&epwm4 { +- /* +- * EPWM4_A, EPWM4_B is available on Pin 32 and 33 on J4 (RPi hat) +- * But RPi Hat will be used for other use cases, so marking epwm4 as disabled. +- */ +- status = "disabled"; +-}; +- +-&epwm5 { +- /* +- * EPWM5_A, EPWM5_B is available on Pin 29 and 31 on J4 (RPi hat) +- * But RPi Hat will be used for other use cases, so marking epwm5 as disabled. +- */ +- status = "disabled"; +-}; +- +-&epwm6 { +- status = "disabled"; +-}; +- +-&epwm7 { +- status = "disabled"; +-}; +- +-&epwm8 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-am642.dtsi b/scripts/dtc/include-prefixes/arm64/ti/k3-am642.dtsi +deleted file mode 100644 +index 8a76f4821b11..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-am642.dtsi ++++ /dev/null +@@ -1,65 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for AM642 SoC family in Dual core configuration +- * +- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/dts-v1/; +- +-#include "k3-am64.dtsi" +- +-/ { +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0: cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- +- core1 { +- cpu = <&cpu1>; +- }; +- }; +- }; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a53"; +- reg = <0x000>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&L2_0>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a53"; +- reg = <0x001>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&L2_0>; +- }; +- }; +- +- L2_0: l2-cache0 { +- compatible = "cache"; +- cache-level = <2>; +- cache-size = <0x40000>; +- cache-line-size = <64>; +- cache-sets = <256>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-am65-iot2050-common.dtsi b/scripts/dtc/include-prefixes/arm64/ti/k3-am65-iot2050-common.dtsi +deleted file mode 100644 +index 1008e9162ba2..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-am65-iot2050-common.dtsi ++++ /dev/null +@@ -1,716 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) Siemens AG, 2018-2021 +- * +- * Authors: +- * Le Jin +- * Jan Kiszka +- * +- * Common bits of the IOT2050 Basic and Advanced variants +- */ +- +-/dts-v1/; +- +-#include "k3-am654.dtsi" +-#include +- +-/ { +- aliases { +- spi0 = &mcu_spi0; +- }; +- +- chosen { +- stdout-path = "serial3:115200n8"; +- bootargs = "earlycon=ns16550a,mmio32,0x02810000"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- secure_ddr: secure-ddr@9e800000 { +- reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */ +- alignment = <0x1000>; +- no-map; +- }; +- +- mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { +- compatible = "shared-dma-pool"; +- reg = <0 0xa0000000 0 0x100000>; +- no-map; +- }; +- +- mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { +- compatible = "shared-dma-pool"; +- reg = <0 0xa0100000 0 0xf00000>; +- no-map; +- }; +- +- mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { +- compatible = "shared-dma-pool"; +- reg = <0 0xa1000000 0 0x100000>; +- no-map; +- }; +- +- mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { +- compatible = "shared-dma-pool"; +- reg = <0 0xa1100000 0 0xf00000>; +- no-map; +- }; +- +- rtos_ipc_memory_region: ipc-memories@a2000000 { +- reg = <0x00 0xa2000000 0x00 0x00200000>; +- alignment = <0x1000>; +- no-map; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&leds_pins_default>; +- +- status-led-red { +- gpios = <&wkup_gpio0 32 GPIO_ACTIVE_HIGH>; +- panic-indicator; +- }; +- +- status-led-green { +- gpios = <&wkup_gpio0 24 GPIO_ACTIVE_HIGH>; +- }; +- +- user-led1-red { +- gpios = <&pcal9535_3 14 GPIO_ACTIVE_HIGH>; +- }; +- +- user-led1-green { +- gpios = <&pcal9535_2 15 GPIO_ACTIVE_HIGH>; +- }; +- +- user-led2-red { +- gpios = <&wkup_gpio0 17 GPIO_ACTIVE_HIGH>; +- }; +- +- user-led2-green { +- gpios = <&wkup_gpio0 22 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- dp_refclk: clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <19200000>; +- }; +-}; +- +-&wkup_pmx0 { +- wkup_i2c0_pins_default: wkup-i2c0-pins-default { +- pinctrl-single,pins = < +- /* (AC7) WKUP_I2C0_SCL */ +- AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) +- /* (AD6) WKUP_I2C0_SDA */ +- AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) +- >; +- }; +- +- mcu_i2c0_pins_default: mcu-i2c0-pins-default { +- pinctrl-single,pins = < +- /* (AD8) MCU_I2C0_SCL */ +- AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) +- /* (AD7) MCU_I2C0_SDA */ +- AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) +- >; +- }; +- +- arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-pins-default { +- pinctrl-single,pins = < +- /* (R2) WKUP_GPIO0_21 */ +- AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7) +- >; +- }; +- +- push_button_pins_default: push-button-pins-default { +- pinctrl-single,pins = < +- /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ +- AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) +- >; +- }; +- +- arduino_uart_pins_default: arduino-uart-pins-default { +- pinctrl-single,pins = < +- /* (P4) MCU_UART0_RXD */ +- AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) +- /* (P5) MCU_UART0_TXD */ +- AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) +- >; +- }; +- +- arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-pins-default { +- pinctrl-single,pins = < +- /* (P1) WKUP_GPIO0_31 */ +- AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7) +- /* (N3) WKUP_GPIO0_33 */ +- AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 7) +- >; +- }; +- +- arduino_io_oe_pins_default: arduino-io-oe-pins-default { +- pinctrl-single,pins = < +- /* (N4) WKUP_GPIO0_34 */ +- AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7) +- /* (M2) WKUP_GPIO0_36 */ +- AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 7) +- /* (M3) WKUP_GPIO0_37 */ +- AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 7) +- /* (M4) WKUP_GPIO0_38 */ +- AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 7) +- /* (M1) WKUP_GPIO0_41 */ +- AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7) +- >; +- }; +- +- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { +- pinctrl-single,pins = < +- /* (V1) MCU_OSPI0_CLK */ +- AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) +- /* (U2) MCU_OSPI0_DQS */ +- AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) +- /* (U4) MCU_OSPI0_D0 */ +- AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) +- /* (U5) MCU_OSPI0_D1 */ +- AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) +- /* (R4) MCU_OSPI0_CSn0 */ +- AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) +- >; +- }; +- +- db9_com_mode_pins_default: db9-com-mode-pins-default { +- pinctrl-single,pins = < +- /* (AD3) WKUP_GPIO0_5, used as uart0 mode 0 */ +- AM65X_WKUP_IOPAD(0x00c4, PIN_OUTPUT, 7) +- /* (AC3) WKUP_GPIO0_4, used as uart0 mode 1 */ +- AM65X_WKUP_IOPAD(0x00c0, PIN_OUTPUT, 7) +- /* (AC1) WKUP_GPIO0_7, used as uart0 term */ +- AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 7) +- /* (AC2) WKUP_GPIO0_6, used as uart0 en */ +- AM65X_WKUP_IOPAD(0x00c8, PIN_OUTPUT, 7) +- >; +- }; +- +- leds_pins_default: leds-pins-default { +- pinctrl-single,pins = < +- /* (T2) WKUP_GPIO0_17, used as user led1 red */ +- AM65X_WKUP_IOPAD(0x0014, PIN_OUTPUT, 7) +- /* (R3) WKUP_GPIO0_22, used as user led1 green */ +- AM65X_WKUP_IOPAD(0x0028, PIN_OUTPUT, 7) +- /* (R5) WKUP_GPIO0_24, used as status led red */ +- AM65X_WKUP_IOPAD(0x0030, PIN_OUTPUT, 7) +- /* (N2) WKUP_GPIO0_32, used as status led green */ +- AM65X_WKUP_IOPAD(0x0050, PIN_OUTPUT, 7) +- >; +- }; +- +- mcu_spi0_pins_default: mcu-spi0-pins-default { +- pinctrl-single,pins = < +- /* (Y1) MCU_SPI0_CLK */ +- AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0) +- /* (Y3) MCU_SPI0_D0 */ +- AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0) +- /* (Y2) MCU_SPI0_D1 */ +- AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0) +- /* (Y4) MCU_SPI0_CS0 */ +- AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) +- >; +- }; +- +- minipcie_pins_default: minipcie-pins-default { +- pinctrl-single,pins = < +- /* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */ +- AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7) +- >; +- }; +-}; +- +-&main_pmx0 { +- main_uart1_pins_default: main-uart1-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */ +- AM65X_IOPAD(0x014c, PIN_OUTPUT, 6) /* (AD23) UART1_TXD */ +- AM65X_IOPAD(0x0178, PIN_INPUT, 6) /* (AD22) UART1_CTSn */ +- AM65X_IOPAD(0x017c, PIN_OUTPUT, 6) /* (AC21) UART1_RTSn */ +- >; +- }; +- +- main_i2c3_pins_default: main-i2c3-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x01c0, PIN_INPUT, 2) /* (AF13) I2C3_SCL */ +- AM65X_IOPAD(0x01d4, PIN_INPUT, 2) /* (AG12) I2C3_SDA */ +- >; +- }; +- +- main_mmc1_pins_default: main-mmc1-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ +- AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ +- AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */ +- AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */ +- AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */ +- AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */ +- AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */ +- AM65X_IOPAD(0x02e0, PIN_INPUT_PULLUP, 0) /* (C24) MMC1_SDWP */ +- >; +- }; +- +- usb0_pins_default: usb0-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ +- >; +- }; +- +- usb1_pins_default: usb1-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ +- >; +- }; +- +- arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (AG18) GPIO0_33 */ +- AM65X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (AF17) GPIO0_35 */ +- AM65X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (AH16) GPIO0_38 */ +- AM65X_IOPAD(0x00AC, PIN_OUTPUT, 7) /* (AH15) GPIO0_43 */ +- AM65X_IOPAD(0x00C0, PIN_OUTPUT, 7) /* (AG15) GPIO0_48 */ +- AM65X_IOPAD(0x00CC, PIN_OUTPUT, 7) /* (AD15) GPIO0_51 */ +- >; +- }; +- +- dss_vout1_pins_default: dss-vout1-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */ +- AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */ +- AM65X_IOPAD(0x0008, PIN_OUTPUT, 1) /* VOUT1_DATA2 */ +- AM65X_IOPAD(0x000c, PIN_OUTPUT, 1) /* VOUT1_DATA3 */ +- AM65X_IOPAD(0x0010, PIN_OUTPUT, 1) /* VOUT1_DATA4 */ +- AM65X_IOPAD(0x0014, PIN_OUTPUT, 1) /* VOUT1_DATA5 */ +- AM65X_IOPAD(0x0018, PIN_OUTPUT, 1) /* VOUT1_DATA6 */ +- AM65X_IOPAD(0x001c, PIN_OUTPUT, 1) /* VOUT1_DATA7 */ +- AM65X_IOPAD(0x0020, PIN_OUTPUT, 1) /* VOUT1_DATA8 */ +- AM65X_IOPAD(0x0024, PIN_OUTPUT, 1) /* VOUT1_DATA9 */ +- AM65X_IOPAD(0x0028, PIN_OUTPUT, 1) /* VOUT1_DATA10 */ +- AM65X_IOPAD(0x002c, PIN_OUTPUT, 1) /* VOUT1_DATA11 */ +- AM65X_IOPAD(0x0030, PIN_OUTPUT, 1) /* VOUT1_DATA12 */ +- AM65X_IOPAD(0x0034, PIN_OUTPUT, 1) /* VOUT1_DATA13 */ +- AM65X_IOPAD(0x0038, PIN_OUTPUT, 1) /* VOUT1_DATA14 */ +- AM65X_IOPAD(0x003c, PIN_OUTPUT, 1) /* VOUT1_DATA15 */ +- AM65X_IOPAD(0x0040, PIN_OUTPUT, 1) /* VOUT1_DATA16 */ +- AM65X_IOPAD(0x0044, PIN_OUTPUT, 1) /* VOUT1_DATA17 */ +- AM65X_IOPAD(0x0048, PIN_OUTPUT, 1) /* VOUT1_DATA18 */ +- AM65X_IOPAD(0x004c, PIN_OUTPUT, 1) /* VOUT1_DATA19 */ +- AM65X_IOPAD(0x0050, PIN_OUTPUT, 1) /* VOUT1_DATA20 */ +- AM65X_IOPAD(0x0054, PIN_OUTPUT, 1) /* VOUT1_DATA21 */ +- AM65X_IOPAD(0x0058, PIN_OUTPUT, 1) /* VOUT1_DATA22 */ +- AM65X_IOPAD(0x005c, PIN_OUTPUT, 1) /* VOUT1_DATA23 */ +- AM65X_IOPAD(0x0060, PIN_OUTPUT, 1) /* VOUT1_VSYNC */ +- AM65X_IOPAD(0x0064, PIN_OUTPUT, 1) /* VOUT1_HSYNC */ +- AM65X_IOPAD(0x0068, PIN_OUTPUT, 1) /* VOUT1_PCLK */ +- AM65X_IOPAD(0x006c, PIN_OUTPUT, 1) /* VOUT1_DE */ +- >; +- }; +- +- dp_pins_default: dp-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */ +- >; +- }; +- +- main_i2c2_pins_default: main-i2c2-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */ +- AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */ +- >; +- }; +-}; +- +-&main_pmx1 { +- main_i2c0_pins_default: main-i2c0-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */ +- AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */ +- >; +- }; +- +- main_i2c1_pins_default: main-i2c1-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */ +- AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */ +- >; +- }; +- +- ecap0_pins_default: ecap0-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ +- >; +- }; +-}; +- +-&wkup_uart0 { +- /* Wakeup UART is used by System firmware */ +- status = "reserved"; +-}; +- +-&main_uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_uart1_pins_default>; +-}; +- +-&main_uart2 { +- status = "disabled"; +-}; +- +-&mcu_uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&arduino_uart_pins_default>; +-}; +- +-&main_gpio0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&arduino_io_d4_to_d9_pins_default>; +- gpio-line-names = +- "main_gpio0-base", "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", "", +- "", "", "", "IO4", "", "IO5", "", "", "IO6", "", +- "", "", "", "IO7", "", "", "", "", "IO8", "", +- "", "IO9"; +-}; +- +-&wkup_gpio0 { +- pinctrl-names = "default"; +- pinctrl-0 = < +- &arduino_io_d2_to_d3_pins_default +- &arduino_i2c_aio_switch_pins_default +- &arduino_io_oe_pins_default +- &push_button_pins_default +- &db9_com_mode_pins_default +- >; +- gpio-line-names = +- /* 0..9 */ +- "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0", +- "UART0-enable", "UART0-terminate", "", "WIFI-disable", +- /* 10..19 */ +- "", "", "", "", "", "", "", "", "", "", +- /* 20..29 */ +- "", "A4A5-I2C-mux", "", "", "", "USER-button", "", "", "","IO0", +- /* 30..39 */ +- "IO1", "IO2", "", "IO3", "IO17-direction", "A5", +- "IO16-direction", "IO15-direction", "IO14-direction", "A3", +- /* 40..49 */ +- "", "IO18-direction", "A4", "A2", "A1", "A0", "", "", "IO13", +- "IO11", +- /* 50..51 */ +- "IO12", "IO10"; +-}; +- +-&wkup_i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&wkup_i2c0_pins_default>; +- clock-frequency = <400000>; +-}; +- +-&mcu_i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcu_i2c0_pins_default>; +- clock-frequency = <400000>; +- +- psu: regulator@60 { +- compatible = "ti,tps62363"; +- reg = <0x60>; +- regulator-name = "tps62363-vout"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1500000>; +- regulator-boot-on; +- ti,vsel0-state-high; +- ti,vsel1-state-high; +- ti,enable-vout-discharge; +- }; +- +- /* D4200 */ +- pcal9535_1: gpio@20 { +- compatible = "nxp,pcal9535"; +- reg = <0x20>; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-line-names = +- "A0-pull", "A1-pull", "A2-pull", "A3-pull", "A4-pull", +- "A5-pull", "", "", +- "IO14-enable", "IO15-enable", "IO16-enable", +- "IO17-enable", "IO18-enable", "IO19-enable"; +- }; +- +- /* D4201 */ +- pcal9535_2: gpio@21 { +- compatible = "nxp,pcal9535"; +- reg = <0x21>; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-line-names = +- "IO0-direction", "IO1-direction", "IO2-direction", +- "IO3-direction", "IO4-direction", "IO5-direction", +- "IO6-direction", "IO7-direction", +- "IO8-direction", "IO9-direction", "IO10-direction", +- "IO11-direction", "IO12-direction", "IO13-direction", +- "IO19-direction"; +- }; +- +- /* D4202 */ +- pcal9535_3: gpio@25 { +- compatible = "nxp,pcal9535"; +- reg = <0x25>; +- #gpio-cells = <2>; +- gpio-controller; +- gpio-line-names = +- "IO0-pull", "IO1-pull", "IO2-pull", "IO3-pull", +- "IO4-pull", "IO5-pull", "IO6-pull", "IO7-pull", +- "IO8-pull", "IO9-pull", "IO10-pull", "IO11-pull", +- "IO12-pull", "IO13-pull"; +- }; +-}; +- +-&main_i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_i2c0_pins_default>; +- clock-frequency = <400000>; +- +- rtc: rtc8564@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- +- eeprom: eeprom@54 { +- compatible = "atmel,24c08"; +- reg = <0x54>; +- pagesize = <16>; +- }; +-}; +- +-&main_i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_i2c1_pins_default>; +- clock-frequency = <400000>; +-}; +- +-&main_i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_i2c2_pins_default>; +- clock-frequency = <400000>; +-}; +- +-&main_i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_i2c3_pins_default>; +- clock-frequency = <400000>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- edp-bridge@f { +- compatible = "toshiba,tc358767"; +- reg = <0x0f>; +- pinctrl-names = "default"; +- pinctrl-0 = <&dp_pins_default>; +- reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; +- +- clock-names = "ref"; +- clocks = <&dp_refclk>; +- +- toshiba,hpd-pin = <0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <1>; +- +- bridge_in: endpoint { +- remote-endpoint = <&dpi_out>; +- }; +- }; +- }; +- }; +-}; +- +-&mcu_cpsw { +- status = "disabled"; +-}; +- +-&ecap0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ecap0_pins_default>; +-}; +- +-&sdhci1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_mmc1_pins_default>; +- ti,driver-strength-ohm = <50>; +- disable-wp; +- no-1-8-v; +-}; +- +-&usb0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb0_pins_default>; +- dr_mode = "host"; +-}; +- +-&usb1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb1_pins_default>; +- dr_mode = "host"; +-}; +- +-&mcu_spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcu_spi0_pins_default>; +- +- #address-cells = <1>; +- #size-cells= <0>; +- ti,pindir-d0-out-d1-in; +-}; +- +-&tscadc0 { +- status = "disabled"; +-}; +- +-&tscadc1 { +- adc { +- ti,adc-channels = <0 1 2 3 4 5>; +- }; +-}; +- +-&ospi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0x0>; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <1>; +- spi-max-frequency = <50000000>; +- cdns,tshsl-ns = <60>; +- cdns,tsd2d-ns = <60>; +- cdns,tchsh-ns = <60>; +- cdns,tslch-ns = <60>; +- cdns,read-delay = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&dss { +- pinctrl-names = "default"; +- pinctrl-0 = <&dss_vout1_pins_default>; +- +- assigned-clocks = <&k3_clks 67 2>; +- assigned-clock-parents = <&k3_clks 67 5>; +-}; +- +-&dss_ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@1 { +- reg = <1>; +- +- dpi_out: endpoint { +- remote-endpoint = <&bridge_in>; +- }; +- }; +-}; +- +-&serdes0 { +- status = "disabled"; +-}; +- +-&pcie0_rc { +- status = "disabled"; +-}; +- +-&pcie0_ep { +- status = "disabled"; +-}; +- +-&pcie1_rc { +- pinctrl-names = "default"; +- pinctrl-0 = <&minipcie_pins_default>; +- +- num-lanes = <1>; +- phys = <&serdes1 PHY_TYPE_PCIE 0>; +- phy-names = "pcie-phy0"; +- reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; +-}; +- +-&pcie1_ep { +- status = "disabled"; +-}; +- +-&mailbox0_cluster0 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster1 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster2 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster3 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster4 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster5 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster6 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster7 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster8 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster9 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster10 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster11 { +- status = "disabled"; +-}; +- +-&icssg0_mdio { +- status = "disabled"; +-}; +- +-&icssg1_mdio { +- status = "disabled"; +-}; +- +-&icssg2_mdio { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-am65-main.dtsi b/scripts/dtc/include-prefixes/arm64/ti/k3-am65-main.dtsi +deleted file mode 100644 +index ba4e5d3e1ed7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-am65-main.dtsi ++++ /dev/null +@@ -1,1342 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for AM6 SoC Family Main Domain peripherals +- * +- * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-#include +- +-&cbass_main { +- msmc_ram: sram@70000000 { +- compatible = "mmio-sram"; +- reg = <0x0 0x70000000 0x0 0x200000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x70000000 0x200000>; +- +- atf-sram@0 { +- reg = <0x0 0x20000>; +- }; +- +- sysfw-sram@f0000 { +- reg = <0xf0000 0x10000>; +- }; +- +- l3cache-sram@100000 { +- reg = <0x100000 0x100000>; +- }; +- }; +- +- gic500: interrupt-controller@1800000 { +- compatible = "arm,gic-v3"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ +- <0x00 0x01880000 0x00 0x90000>; /* GICR */ +- /* +- * vcpumntirq: +- * virtual CPU interface maintenance interrupt +- */ +- interrupts = ; +- +- gic_its: msi-controller@1820000 { +- compatible = "arm,gic-v3-its"; +- reg = <0x00 0x01820000 0x00 0x10000>; +- socionext,synquacer-pre-its = <0x1000000 0x400000>; +- msi-controller; +- #msi-cells = <1>; +- }; +- }; +- +- serdes0: serdes@900000 { +- compatible = "ti,phy-am654-serdes"; +- reg = <0x0 0x900000 0x0 0x2000>; +- reg-names = "serdes"; +- #phy-cells = <2>; +- power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; +- clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; +- assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; +- assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; +- ti,serdes-clk = <&serdes0_clk>; +- #clock-cells = <1>; +- mux-controls = <&serdes_mux 0>; +- }; +- +- serdes1: serdes@910000 { +- compatible = "ti,phy-am654-serdes"; +- reg = <0x0 0x910000 0x0 0x2000>; +- reg-names = "serdes"; +- #phy-cells = <2>; +- power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; +- clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; +- assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; +- assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; +- ti,serdes-clk = <&serdes1_clk>; +- #clock-cells = <1>; +- mux-controls = <&serdes_mux 1>; +- }; +- +- main_uart0: serial@2800000 { +- compatible = "ti,am654-uart"; +- reg = <0x00 0x02800000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- main_uart1: serial@2810000 { +- compatible = "ti,am654-uart"; +- reg = <0x00 0x02810000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- main_uart2: serial@2820000 { +- compatible = "ti,am654-uart"; +- reg = <0x00 0x02820000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- crypto: crypto@4e00000 { +- compatible = "ti,am654-sa2ul"; +- reg = <0x0 0x4e00000 0x0 0x1200>; +- power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; +- +- dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, +- <&main_udmap 0x4001>; +- dma-names = "tx", "rx1", "rx2"; +- dma-coherent; +- +- rng: rng@4e10000 { +- compatible = "inside-secure,safexcel-eip76"; +- reg = <0x0 0x4e10000 0x0 0x7d>; +- interrupts = ; +- clocks = <&k3_clks 136 1>; +- }; +- }; +- +- main_pmx0: pinctrl@11c000 { +- compatible = "pinctrl-single"; +- reg = <0x0 0x11c000 0x0 0x2e4>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0xffffffff>; +- }; +- +- main_pmx1: pinctrl@11c2e8 { +- compatible = "pinctrl-single"; +- reg = <0x0 0x11c2e8 0x0 0x24>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0xffffffff>; +- }; +- +- main_i2c0: i2c@2000000 { +- compatible = "ti,am654-i2c", "ti,omap4-i2c"; +- reg = <0x0 0x2000000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 110 1>; +- power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- main_i2c1: i2c@2010000 { +- compatible = "ti,am654-i2c", "ti,omap4-i2c"; +- reg = <0x0 0x2010000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 111 1>; +- power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- main_i2c2: i2c@2020000 { +- compatible = "ti,am654-i2c", "ti,omap4-i2c"; +- reg = <0x0 0x2020000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 112 1>; +- power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- main_i2c3: i2c@2030000 { +- compatible = "ti,am654-i2c", "ti,omap4-i2c"; +- reg = <0x0 0x2030000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 113 1>; +- power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- ecap0: pwm@3100000 { +- compatible = "ti,am654-ecap", "ti,am3352-ecap"; +- #pwm-cells = <3>; +- reg = <0x0 0x03100000 0x0 0x60>; +- power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 39 0>; +- clock-names = "fck"; +- }; +- +- main_spi0: spi@2100000 { +- compatible = "ti,am654-mcspi","ti,omap4-mcspi"; +- reg = <0x0 0x2100000 0x0 0x400>; +- interrupts = ; +- clocks = <&k3_clks 137 1>; +- power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <1>; +- #size-cells = <0>; +- dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; +- dma-names = "tx0", "rx0"; +- }; +- +- main_spi1: spi@2110000 { +- compatible = "ti,am654-mcspi","ti,omap4-mcspi"; +- reg = <0x0 0x2110000 0x0 0x400>; +- interrupts = ; +- clocks = <&k3_clks 138 1>; +- power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <1>; +- #size-cells = <0>; +- assigned-clocks = <&k3_clks 137 1>; +- assigned-clock-rates = <48000000>; +- }; +- +- main_spi2: spi@2120000 { +- compatible = "ti,am654-mcspi","ti,omap4-mcspi"; +- reg = <0x0 0x2120000 0x0 0x400>; +- interrupts = ; +- clocks = <&k3_clks 139 1>; +- power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- main_spi3: spi@2130000 { +- compatible = "ti,am654-mcspi","ti,omap4-mcspi"; +- reg = <0x0 0x2130000 0x0 0x400>; +- interrupts = ; +- clocks = <&k3_clks 140 1>; +- power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- main_spi4: spi@2140000 { +- compatible = "ti,am654-mcspi","ti,omap4-mcspi"; +- reg = <0x0 0x2140000 0x0 0x400>; +- interrupts = ; +- clocks = <&k3_clks 141 1>; +- power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- sdhci0: mmc@4f80000 { +- compatible = "ti,am654-sdhci-5.1"; +- reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; +- power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; +- clock-names = "clk_ahb", "clk_xin"; +- interrupts = ; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- ti,otap-del-sel-legacy = <0x0>; +- ti,otap-del-sel-mmc-hs = <0x0>; +- ti,otap-del-sel-sd-hs = <0x0>; +- ti,otap-del-sel-sdr12 = <0x0>; +- ti,otap-del-sel-sdr25 = <0x0>; +- ti,otap-del-sel-sdr50 = <0x8>; +- ti,otap-del-sel-sdr104 = <0x7>; +- ti,otap-del-sel-ddr50 = <0x5>; +- ti,otap-del-sel-ddr52 = <0x5>; +- ti,otap-del-sel-hs200 = <0x5>; +- ti,otap-del-sel-hs400 = <0x0>; +- ti,trm-icp = <0x8>; +- dma-coherent; +- }; +- +- sdhci1: mmc@4fa0000 { +- compatible = "ti,am654-sdhci-5.1"; +- reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>; +- power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 48 0>, <&k3_clks 48 1>; +- clock-names = "clk_ahb", "clk_xin"; +- interrupts = ; +- ti,otap-del-sel-legacy = <0x0>; +- ti,otap-del-sel-mmc-hs = <0x0>; +- ti,otap-del-sel-sd-hs = <0x0>; +- ti,otap-del-sel-sdr12 = <0x0>; +- ti,otap-del-sel-sdr25 = <0x0>; +- ti,otap-del-sel-sdr50 = <0x8>; +- ti,otap-del-sel-sdr104 = <0x7>; +- ti,otap-del-sel-ddr50 = <0x4>; +- ti,otap-del-sel-ddr52 = <0x4>; +- ti,otap-del-sel-hs200 = <0x7>; +- ti,clkbuf-sel = <0x7>; +- ti,otap-del-sel = <0x2>; +- ti,trm-icp = <0x8>; +- dma-coherent; +- }; +- +- scm_conf: scm-conf@100000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0 0x00100000 0 0x1c000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x00100000 0x1c000>; +- +- pcie0_mode: pcie-mode@4060 { +- compatible = "syscon"; +- reg = <0x00004060 0x4>; +- }; +- +- pcie1_mode: pcie-mode@4070 { +- compatible = "syscon"; +- reg = <0x00004070 0x4>; +- }; +- +- pcie_devid: pcie-devid@210 { +- compatible = "syscon"; +- reg = <0x00000210 0x4>; +- }; +- +- serdes0_clk: clock@4080 { +- compatible = "syscon"; +- reg = <0x00004080 0x4>; +- }; +- +- serdes1_clk: clock@4090 { +- compatible = "syscon"; +- reg = <0x00004090 0x4>; +- }; +- +- serdes_mux: mux-controller { +- compatible = "mmio-mux"; +- #mux-control-cells = <1>; +- mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ +- <0x4090 0x3>; /* SERDES1 lane select */ +- }; +- +- dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { +- compatible = "syscon"; +- reg = <0x0000041e0 0x14>; +- }; +- +- ehrpwm_tbclk: clock@4140 { +- compatible = "ti,am654-ehrpwm-tbclk", "syscon"; +- reg = <0x4140 0x18>; +- #clock-cells = <1>; +- }; +- }; +- +- dwc3_0: dwc3@4000000 { +- compatible = "ti,am654-dwc3"; +- reg = <0x0 0x4000000 0x0 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x4000000 0x20000>; +- interrupts = ; +- dma-coherent; +- power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; +- assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; +- assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ +- <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ +- +- usb0: usb@10000 { +- compatible = "snps,dwc3"; +- reg = <0x10000 0x10000>; +- interrupts = , +- , +- ; +- interrupt-names = "peripheral", +- "host", +- "otg"; +- maximum-speed = "high-speed"; +- dr_mode = "otg"; +- phys = <&usb0_phy>; +- phy-names = "usb2-phy"; +- snps,dis_u3_susphy_quirk; +- }; +- }; +- +- usb0_phy: phy@4100000 { +- compatible = "ti,am654-usb2", "ti,omap-usb2"; +- reg = <0x0 0x4100000 0x0 0x54>; +- syscon-phy-power = <&scm_conf 0x4000>; +- clocks = <&k3_clks 151 0>, <&k3_clks 151 1>; +- clock-names = "wkupclk", "refclk"; +- #phy-cells = <0>; +- }; +- +- dwc3_1: dwc3@4020000 { +- compatible = "ti,am654-dwc3"; +- reg = <0x0 0x4020000 0x0 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x4020000 0x20000>; +- interrupts = ; +- dma-coherent; +- power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 152 2>; +- assigned-clocks = <&k3_clks 152 2>; +- assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ +- +- usb1: usb@10000 { +- compatible = "snps,dwc3"; +- reg = <0x10000 0x10000>; +- interrupts = , +- , +- ; +- interrupt-names = "peripheral", +- "host", +- "otg"; +- maximum-speed = "high-speed"; +- dr_mode = "otg"; +- phys = <&usb1_phy>; +- phy-names = "usb2-phy"; +- }; +- }; +- +- usb1_phy: phy@4110000 { +- compatible = "ti,am654-usb2", "ti,omap-usb2"; +- reg = <0x0 0x4110000 0x0 0x54>; +- syscon-phy-power = <&scm_conf 0x4020>; +- clocks = <&k3_clks 152 0>, <&k3_clks 152 1>; +- clock-names = "wkupclk", "refclk"; +- #phy-cells = <0>; +- }; +- +- intr_main_gpio: interrupt-controller@a00000 { +- compatible = "ti,sci-intr"; +- reg = <0x0 0x00a00000 0x0 0x400>; +- ti,intr-trigger-type = <1>; +- interrupt-controller; +- interrupt-parent = <&gic500>; +- #interrupt-cells = <1>; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <100>; +- ti,interrupt-ranges = <0 392 32>; +- }; +- +- main_navss: bus@30800000 { +- compatible = "simple-mfd"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>; +- dma-coherent; +- dma-ranges; +- +- ti,sci-dev-id = <118>; +- +- intr_main_navss: interrupt-controller@310e0000 { +- compatible = "ti,sci-intr"; +- reg = <0x0 0x310e0000 0x0 0x2000>; +- ti,intr-trigger-type = <4>; +- interrupt-controller; +- interrupt-parent = <&gic500>; +- #interrupt-cells = <1>; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <182>; +- ti,interrupt-ranges = <0 64 64>, +- <64 448 64>; +- }; +- +- inta_main_udmass: interrupt-controller@33d00000 { +- compatible = "ti,sci-inta"; +- reg = <0x0 0x33d00000 0x0 0x100000>; +- interrupt-controller; +- interrupt-parent = <&intr_main_navss>; +- msi-controller; +- #interrupt-cells = <0>; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <179>; +- ti,interrupt-ranges = <0 0 256>; +- }; +- +- secure_proxy_main: mailbox@32c00000 { +- compatible = "ti,am654-secure-proxy"; +- #mbox-cells = <1>; +- reg-names = "target_data", "rt", "scfg"; +- reg = <0x00 0x32c00000 0x00 0x100000>, +- <0x00 0x32400000 0x00 0x100000>, +- <0x00 0x32800000 0x00 0x100000>; +- interrupt-names = "rx_011"; +- interrupts = ; +- }; +- +- hwspinlock: spinlock@30e00000 { +- compatible = "ti,am654-hwspinlock"; +- reg = <0x00 0x30e00000 0x00 0x1000>; +- #hwlock-cells = <1>; +- }; +- +- mailbox0_cluster0: mailbox@31f80000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f80000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&intr_main_navss>; +- }; +- +- mailbox0_cluster1: mailbox@31f81000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f81000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&intr_main_navss>; +- }; +- +- mailbox0_cluster2: mailbox@31f82000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f82000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&intr_main_navss>; +- }; +- +- mailbox0_cluster3: mailbox@31f83000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f83000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&intr_main_navss>; +- }; +- +- mailbox0_cluster4: mailbox@31f84000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f84000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&intr_main_navss>; +- }; +- +- mailbox0_cluster5: mailbox@31f85000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f85000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&intr_main_navss>; +- }; +- +- mailbox0_cluster6: mailbox@31f86000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f86000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&intr_main_navss>; +- }; +- +- mailbox0_cluster7: mailbox@31f87000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f87000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&intr_main_navss>; +- }; +- +- mailbox0_cluster8: mailbox@31f88000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f88000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&intr_main_navss>; +- }; +- +- mailbox0_cluster9: mailbox@31f89000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f89000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&intr_main_navss>; +- }; +- +- mailbox0_cluster10: mailbox@31f8a000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f8a000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&intr_main_navss>; +- }; +- +- mailbox0_cluster11: mailbox@31f8b000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f8b000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&intr_main_navss>; +- }; +- +- ringacc: ringacc@3c000000 { +- compatible = "ti,am654-navss-ringacc"; +- reg = <0x0 0x3c000000 0x0 0x400000>, +- <0x0 0x38000000 0x0 0x400000>, +- <0x0 0x31120000 0x0 0x100>, +- <0x0 0x33000000 0x0 0x40000>; +- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; +- ti,num-rings = <818>; +- ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <187>; +- msi-parent = <&inta_main_udmass>; +- }; +- +- main_udmap: dma-controller@31150000 { +- compatible = "ti,am654-navss-main-udmap"; +- reg = <0x0 0x31150000 0x0 0x100>, +- <0x0 0x34000000 0x0 0x100000>, +- <0x0 0x35000000 0x0 0x100000>; +- reg-names = "gcfg", "rchanrt", "tchanrt"; +- msi-parent = <&inta_main_udmass>; +- #dma-cells = <1>; +- +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <188>; +- ti,ringacc = <&ringacc>; +- +- ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ +- <0xd>; /* TX_CHAN */ +- ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ +- <0xa>; /* RX_CHAN */ +- ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ +- }; +- +- cpts@310d0000 { +- compatible = "ti,am65-cpts"; +- reg = <0x0 0x310d0000 0x0 0x400>; +- reg-names = "cpts"; +- clocks = <&main_cpts_mux>; +- clock-names = "cpts"; +- interrupts-extended = <&intr_main_navss 391>; +- interrupt-names = "cpts"; +- ti,cpts-periodic-outputs = <6>; +- ti,cpts-ext-ts-inputs = <8>; +- +- main_cpts_mux: refclk-mux { +- #clock-cells = <0>; +- clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, +- <&k3_clks 118 6>, <&k3_clks 118 3>, +- <&k3_clks 118 8>, <&k3_clks 118 14>, +- <&k3_clks 120 3>, <&k3_clks 121 3>; +- assigned-clocks = <&main_cpts_mux>; +- assigned-clock-parents = <&k3_clks 118 5>; +- }; +- }; +- }; +- +- main_gpio0: gpio@600000 { +- compatible = "ti,am654-gpio", "ti,keystone-gpio"; +- reg = <0x0 0x600000 0x0 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&intr_main_gpio>; +- interrupts = <192>, <193>, <194>, <195>, <196>, <197>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <96>; +- ti,davinci-gpio-unbanked = <0>; +- clocks = <&k3_clks 57 0>; +- clock-names = "gpio"; +- }; +- +- main_gpio1: gpio@601000 { +- compatible = "ti,am654-gpio", "ti,keystone-gpio"; +- reg = <0x0 0x601000 0x0 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&intr_main_gpio>; +- interrupts = <200>, <201>, <202>, <203>, <204>, <205>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <90>; +- ti,davinci-gpio-unbanked = <0>; +- clocks = <&k3_clks 58 0>; +- clock-names = "gpio"; +- }; +- +- pcie0_rc: pcie@5500000 { +- compatible = "ti,am654-pcie-rc"; +- reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; +- reg-names = "app", "dbics", "config", "atu"; +- power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <3>; +- #size-cells = <2>; +- ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000 +- 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; +- ti,syscon-pcie-id = <&pcie_devid>; +- ti,syscon-pcie-mode = <&pcie0_mode>; +- bus-range = <0x0 0xff>; +- num-viewport = <16>; +- max-link-speed = <2>; +- dma-coherent; +- interrupts = ; +- msi-map = <0x0 &gic_its 0x0 0x10000>; +- device_type = "pci"; +- }; +- +- pcie0_ep: pcie-ep@5500000 { +- compatible = "ti,am654-pcie-ep"; +- reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; +- reg-names = "app", "dbics", "addr_space", "atu"; +- power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; +- ti,syscon-pcie-mode = <&pcie0_mode>; +- num-ib-windows = <16>; +- num-ob-windows = <16>; +- max-link-speed = <2>; +- dma-coherent; +- interrupts = ; +- }; +- +- pcie1_rc: pcie@5600000 { +- compatible = "ti,am654-pcie-rc"; +- reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; +- reg-names = "app", "dbics", "config", "atu"; +- power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <3>; +- #size-cells = <2>; +- ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000 +- 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; +- ti,syscon-pcie-id = <&pcie_devid>; +- ti,syscon-pcie-mode = <&pcie1_mode>; +- bus-range = <0x0 0xff>; +- num-viewport = <16>; +- max-link-speed = <2>; +- dma-coherent; +- interrupts = ; +- msi-map = <0x0 &gic_its 0x10000 0x10000>; +- device_type = "pci"; +- }; +- +- pcie1_ep: pcie-ep@5600000 { +- compatible = "ti,am654-pcie-ep"; +- reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; +- reg-names = "app", "dbics", "addr_space", "atu"; +- power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; +- ti,syscon-pcie-mode = <&pcie1_mode>; +- num-ib-windows = <16>; +- num-ob-windows = <16>; +- max-link-speed = <2>; +- dma-coherent; +- interrupts = ; +- }; +- +- mcasp0: mcasp@2b00000 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x0 0x02b00000 0x0 0x2000>, +- <0x0 0x02b08000 0x0 0x1000>; +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- +- dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; +- dma-names = "tx", "rx"; +- +- clocks = <&k3_clks 104 0>; +- clock-names = "fck"; +- power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- mcasp1: mcasp@2b10000 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x0 0x02b10000 0x0 0x2000>, +- <0x0 0x02b18000 0x0 0x1000>; +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- +- dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; +- dma-names = "tx", "rx"; +- +- clocks = <&k3_clks 105 0>; +- clock-names = "fck"; +- power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- mcasp2: mcasp@2b20000 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x0 0x02b20000 0x0 0x2000>, +- <0x0 0x02b28000 0x0 0x1000>; +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- +- dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; +- dma-names = "tx", "rx"; +- +- clocks = <&k3_clks 106 0>; +- clock-names = "fck"; +- power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- cal: cal@6f03000 { +- compatible = "ti,am654-cal"; +- reg = <0x0 0x06f03000 0x0 0x400>, +- <0x0 0x06f03800 0x0 0x40>; +- reg-names = "cal_top", +- "cal_rx_core0"; +- interrupts = ; +- ti,camerrx-control = <&scm_conf 0x40c0>; +- clock-names = "fck"; +- clocks = <&k3_clks 2 0>; +- power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- csi2_0: port@0 { +- reg = <0>; +- }; +- }; +- }; +- +- dss: dss@4a00000 { +- compatible = "ti,am65x-dss"; +- reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ +- <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ +- <0x0 0x04a06000 0x0 0x1000>, /* vid */ +- <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ +- <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ +- <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ +- <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ +- reg-names = "common", "vidl1", "vid", +- "ovr1", "ovr2", "vp1", "vp2"; +- +- ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; +- +- power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; +- +- clocks = <&k3_clks 67 1>, +- <&k3_clks 216 1>, +- <&k3_clks 67 2>; +- clock-names = "fck", "vp1", "vp2"; +- +- /* +- * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via +- * DIV1. See "Figure 12-3365. DSS Integration" +- * in AM65x TRM for details. +- */ +- assigned-clocks = <&k3_clks 67 2>; +- assigned-clock-parents = <&k3_clks 67 5>; +- +- interrupts = ; +- +- dma-coherent; +- +- dss_ports: ports { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- ehrpwm0: pwm@3000000 { +- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x3000000 0x0 0x100>; +- power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>; +- clock-names = "tbclk", "fck"; +- }; +- +- ehrpwm1: pwm@3010000 { +- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x3010000 0x0 0x100>; +- power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>; +- clock-names = "tbclk", "fck"; +- }; +- +- ehrpwm2: pwm@3020000 { +- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x3020000 0x0 0x100>; +- power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>; +- clock-names = "tbclk", "fck"; +- }; +- +- ehrpwm3: pwm@3030000 { +- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x3030000 0x0 0x100>; +- power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>; +- clock-names = "tbclk", "fck"; +- }; +- +- ehrpwm4: pwm@3040000 { +- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x3040000 0x0 0x100>; +- power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>; +- clock-names = "tbclk", "fck"; +- }; +- +- ehrpwm5: pwm@3050000 { +- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; +- #pwm-cells = <3>; +- reg = <0x0 0x3050000 0x0 0x100>; +- power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; +- clock-names = "tbclk", "fck"; +- }; +- +- icssg0: icssg@b000000 { +- compatible = "ti,am654-icssg"; +- reg = <0x00 0xb000000 0x00 0x80000>; +- power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x00 0xb000000 0x80000>; +- +- icssg0_mem: memories@0 { +- reg = <0x0 0x2000>, +- <0x2000 0x2000>, +- <0x10000 0x10000>; +- reg-names = "dram0", "dram1", +- "shrdram2"; +- }; +- +- icssg0_cfg: cfg@26000 { +- compatible = "ti,pruss-cfg", "syscon"; +- reg = <0x26000 0x200>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x26000 0x2000>; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- icssg0_coreclk_mux: coreclk-mux@3c { +- reg = <0x3c>; +- #clock-cells = <0>; +- clocks = <&k3_clks 62 19>, /* icssg0_core_clk */ +- <&k3_clks 62 3>; /* icssg0_iclk */ +- assigned-clocks = <&icssg0_coreclk_mux>; +- assigned-clock-parents = <&k3_clks 62 3>; +- }; +- +- icssg0_iepclk_mux: iepclk-mux@30 { +- reg = <0x30>; +- #clock-cells = <0>; +- clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */ +- <&icssg0_coreclk_mux>; /* core_clk */ +- assigned-clocks = <&icssg0_iepclk_mux>; +- assigned-clock-parents = <&icssg0_coreclk_mux>; +- }; +- }; +- }; +- +- icssg0_mii_rt: mii-rt@32000 { +- compatible = "ti,pruss-mii", "syscon"; +- reg = <0x32000 0x100>; +- }; +- +- icssg0_mii_g_rt: mii-g-rt@33000 { +- compatible = "ti,pruss-mii-g", "syscon"; +- reg = <0x33000 0x1000>; +- }; +- +- icssg0_intc: interrupt-controller@20000 { +- compatible = "ti,icssg-intc"; +- reg = <0x20000 0x2000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "host_intr0", "host_intr1", +- "host_intr2", "host_intr3", +- "host_intr4", "host_intr5", +- "host_intr6", "host_intr7"; +- }; +- +- pru0_0: pru@34000 { +- compatible = "ti,am654-pru"; +- reg = <0x34000 0x4000>, +- <0x22000 0x100>, +- <0x22400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am65x-pru0_0-fw"; +- }; +- +- rtu0_0: rtu@4000 { +- compatible = "ti,am654-rtu"; +- reg = <0x4000 0x2000>, +- <0x23000 0x100>, +- <0x23400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am65x-rtu0_0-fw"; +- }; +- +- tx_pru0_0: txpru@a000 { +- compatible = "ti,am654-tx-pru"; +- reg = <0xa000 0x1800>, +- <0x25000 0x100>, +- <0x25400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am65x-txpru0_0-fw"; +- }; +- +- pru0_1: pru@38000 { +- compatible = "ti,am654-pru"; +- reg = <0x38000 0x4000>, +- <0x24000 0x100>, +- <0x24400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am65x-pru0_1-fw"; +- }; +- +- rtu0_1: rtu@6000 { +- compatible = "ti,am654-rtu"; +- reg = <0x6000 0x2000>, +- <0x23800 0x100>, +- <0x23c00 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am65x-rtu0_1-fw"; +- }; +- +- tx_pru0_1: txpru@c000 { +- compatible = "ti,am654-tx-pru"; +- reg = <0xc000 0x1800>, +- <0x25800 0x100>, +- <0x25c00 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am65x-txpru0_1-fw"; +- }; +- +- icssg0_mdio: mdio@32400 { +- compatible = "ti,davinci_mdio"; +- reg = <0x32400 0x100>; +- clocks = <&k3_clks 62 3>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <0>; +- bus_freq = <1000000>; +- }; +- }; +- +- icssg1: icssg@b100000 { +- compatible = "ti,am654-icssg"; +- reg = <0x00 0xb100000 0x00 0x80000>; +- power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x00 0xb100000 0x80000>; +- +- icssg1_mem: memories@0 { +- reg = <0x0 0x2000>, +- <0x2000 0x2000>, +- <0x10000 0x10000>; +- reg-names = "dram0", "dram1", +- "shrdram2"; +- }; +- +- icssg1_cfg: cfg@26000 { +- compatible = "ti,pruss-cfg", "syscon"; +- reg = <0x26000 0x200>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x26000 0x2000>; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- icssg1_coreclk_mux: coreclk-mux@3c { +- reg = <0x3c>; +- #clock-cells = <0>; +- clocks = <&k3_clks 63 19>, /* icssg1_core_clk */ +- <&k3_clks 63 3>; /* icssg1_iclk */ +- assigned-clocks = <&icssg1_coreclk_mux>; +- assigned-clock-parents = <&k3_clks 63 3>; +- }; +- +- icssg1_iepclk_mux: iepclk-mux@30 { +- reg = <0x30>; +- #clock-cells = <0>; +- clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */ +- <&icssg1_coreclk_mux>; /* core_clk */ +- assigned-clocks = <&icssg1_iepclk_mux>; +- assigned-clock-parents = <&icssg1_coreclk_mux>; +- }; +- }; +- }; +- +- icssg1_mii_rt: mii-rt@32000 { +- compatible = "ti,pruss-mii", "syscon"; +- reg = <0x32000 0x100>; +- }; +- +- icssg1_mii_g_rt: mii-g-rt@33000 { +- compatible = "ti,pruss-mii-g", "syscon"; +- reg = <0x33000 0x1000>; +- }; +- +- icssg1_intc: interrupt-controller@20000 { +- compatible = "ti,icssg-intc"; +- reg = <0x20000 0x2000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "host_intr0", "host_intr1", +- "host_intr2", "host_intr3", +- "host_intr4", "host_intr5", +- "host_intr6", "host_intr7"; +- }; +- +- pru1_0: pru@34000 { +- compatible = "ti,am654-pru"; +- reg = <0x34000 0x4000>, +- <0x22000 0x100>, +- <0x22400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am65x-pru1_0-fw"; +- }; +- +- rtu1_0: rtu@4000 { +- compatible = "ti,am654-rtu"; +- reg = <0x4000 0x2000>, +- <0x23000 0x100>, +- <0x23400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am65x-rtu1_0-fw"; +- }; +- +- tx_pru1_0: txpru@a000 { +- compatible = "ti,am654-tx-pru"; +- reg = <0xa000 0x1800>, +- <0x25000 0x100>, +- <0x25400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am65x-txpru1_0-fw"; +- }; +- +- pru1_1: pru@38000 { +- compatible = "ti,am654-pru"; +- reg = <0x38000 0x4000>, +- <0x24000 0x100>, +- <0x24400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am65x-pru1_1-fw"; +- }; +- +- rtu1_1: rtu@6000 { +- compatible = "ti,am654-rtu"; +- reg = <0x6000 0x2000>, +- <0x23800 0x100>, +- <0x23c00 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am65x-rtu1_1-fw"; +- }; +- +- tx_pru1_1: txpru@c000 { +- compatible = "ti,am654-tx-pru"; +- reg = <0xc000 0x1800>, +- <0x25800 0x100>, +- <0x25c00 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am65x-txpru1_1-fw"; +- }; +- +- icssg1_mdio: mdio@32400 { +- compatible = "ti,davinci_mdio"; +- reg = <0x32400 0x100>; +- clocks = <&k3_clks 63 3>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <0>; +- bus_freq = <1000000>; +- }; +- }; +- +- icssg2: icssg@b200000 { +- compatible = "ti,am654-icssg"; +- reg = <0x00 0xb200000 0x00 0x80000>; +- power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x00 0xb200000 0x80000>; +- +- icssg2_mem: memories@0 { +- reg = <0x0 0x2000>, +- <0x2000 0x2000>, +- <0x10000 0x10000>; +- reg-names = "dram0", "dram1", +- "shrdram2"; +- }; +- +- icssg2_cfg: cfg@26000 { +- compatible = "ti,pruss-cfg", "syscon"; +- reg = <0x26000 0x200>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x26000 0x2000>; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- icssg2_coreclk_mux: coreclk-mux@3c { +- reg = <0x3c>; +- #clock-cells = <0>; +- clocks = <&k3_clks 64 19>, /* icssg1_core_clk */ +- <&k3_clks 64 3>; /* icssg1_iclk */ +- assigned-clocks = <&icssg2_coreclk_mux>; +- assigned-clock-parents = <&k3_clks 64 3>; +- }; +- +- icssg2_iepclk_mux: iepclk-mux@30 { +- reg = <0x30>; +- #clock-cells = <0>; +- clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */ +- <&icssg2_coreclk_mux>; /* core_clk */ +- assigned-clocks = <&icssg2_iepclk_mux>; +- assigned-clock-parents = <&icssg2_coreclk_mux>; +- }; +- }; +- }; +- +- icssg2_mii_rt: mii-rt@32000 { +- compatible = "ti,pruss-mii", "syscon"; +- reg = <0x32000 0x100>; +- }; +- +- icssg2_mii_g_rt: mii-g-rt@33000 { +- compatible = "ti,pruss-mii-g", "syscon"; +- reg = <0x33000 0x1000>; +- }; +- +- icssg2_intc: interrupt-controller@20000 { +- compatible = "ti,icssg-intc"; +- reg = <0x20000 0x2000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "host_intr0", "host_intr1", +- "host_intr2", "host_intr3", +- "host_intr4", "host_intr5", +- "host_intr6", "host_intr7"; +- }; +- +- pru2_0: pru@34000 { +- compatible = "ti,am654-pru"; +- reg = <0x34000 0x4000>, +- <0x22000 0x100>, +- <0x22400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am65x-pru2_0-fw"; +- }; +- +- rtu2_0: rtu@4000 { +- compatible = "ti,am654-rtu"; +- reg = <0x4000 0x2000>, +- <0x23000 0x100>, +- <0x23400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am65x-rtu2_0-fw"; +- }; +- +- tx_pru2_0: txpru@a000 { +- compatible = "ti,am654-tx-pru"; +- reg = <0xa000 0x1800>, +- <0x25000 0x100>, +- <0x25400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am65x-txpru2_0-fw"; +- }; +- +- pru2_1: pru@38000 { +- compatible = "ti,am654-pru"; +- reg = <0x38000 0x4000>, +- <0x24000 0x100>, +- <0x24400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am65x-pru2_1-fw"; +- }; +- +- rtu2_1: rtu@6000 { +- compatible = "ti,am654-rtu"; +- reg = <0x6000 0x2000>, +- <0x23800 0x100>, +- <0x23c00 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am65x-rtu2_1-fw"; +- }; +- +- tx_pru2_1: txpru@c000 { +- compatible = "ti,am654-tx-pru"; +- reg = <0xc000 0x1800>, +- <0x25800 0x100>, +- <0x25c00 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "am65x-txpru2_1-fw"; +- }; +- +- icssg2_mdio: mdio@32400 { +- compatible = "ti,davinci_mdio"; +- reg = <0x32400 0x100>; +- clocks = <&k3_clks 64 3>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <0>; +- bus_freq = <1000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-am65-mcu.dtsi b/scripts/dtc/include-prefixes/arm64/ti/k3-am65-mcu.dtsi +deleted file mode 100644 +index c93ff1520a0e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-am65-mcu.dtsi ++++ /dev/null +@@ -1,318 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for AM6 SoC Family MCU Domain peripherals +- * +- * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-&cbass_mcu { +- mcu_conf: scm-conf@40f00000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x0 0x40f00000 0x0 0x20000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x40f00000 0x20000>; +- +- phy_gmii_sel: phy@4040 { +- compatible = "ti,am654-phy-gmii-sel"; +- reg = <0x4040 0x4>; +- #phy-cells = <1>; +- }; +- }; +- +- mcu_uart0: serial@40a00000 { +- compatible = "ti,am654-uart"; +- reg = <0x00 0x40a00000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <96000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- mcu_ram: sram@41c00000 { +- compatible = "mmio-sram"; +- reg = <0x00 0x41c00000 0x00 0x80000>; +- ranges = <0x0 0x00 0x41c00000 0x80000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- mcu_i2c0: i2c@40b00000 { +- compatible = "ti,am654-i2c", "ti,omap4-i2c"; +- reg = <0x0 0x40b00000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 114 1>; +- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- mcu_spi0: spi@40300000 { +- compatible = "ti,am654-mcspi","ti,omap4-mcspi"; +- reg = <0x0 0x40300000 0x0 0x400>; +- interrupts = ; +- clocks = <&k3_clks 142 1>; +- power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mcu_spi1: spi@40310000 { +- compatible = "ti,am654-mcspi","ti,omap4-mcspi"; +- reg = <0x0 0x40310000 0x0 0x400>; +- interrupts = ; +- clocks = <&k3_clks 143 1>; +- power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mcu_spi2: spi@40320000 { +- compatible = "ti,am654-mcspi","ti,omap4-mcspi"; +- reg = <0x0 0x40320000 0x0 0x400>; +- interrupts = ; +- clocks = <&k3_clks 144 1>; +- power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- tscadc0: tscadc@40200000 { +- compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; +- reg = <0x0 0x40200000 0x0 0x1000>; +- interrupts = ; +- clocks = <&k3_clks 0 2>; +- assigned-clocks = <&k3_clks 0 2>; +- assigned-clock-rates = <60000000>; +- clock-names = "adc_tsc_fck"; +- dmas = <&mcu_udmap 0x7100>, +- <&mcu_udmap 0x7101 >; +- dma-names = "fifo0", "fifo1"; +- +- adc { +- #io-channel-cells = <1>; +- compatible = "ti,am654-adc", "ti,am3359-adc"; +- }; +- }; +- +- tscadc1: tscadc@40210000 { +- compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; +- reg = <0x0 0x40210000 0x0 0x1000>; +- interrupts = ; +- clocks = <&k3_clks 1 2>; +- assigned-clocks = <&k3_clks 1 2>; +- assigned-clock-rates = <60000000>; +- clock-names = "adc_tsc_fck"; +- dmas = <&mcu_udmap 0x7102>, +- <&mcu_udmap 0x7103>; +- dma-names = "fifo0", "fifo1"; +- +- adc { +- #io-channel-cells = <1>; +- compatible = "ti,am654-adc", "ti,am3359-adc"; +- }; +- }; +- +- mcu_navss: bus@28380000 { +- compatible = "simple-mfd"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; +- dma-coherent; +- dma-ranges; +- +- ti,sci-dev-id = <119>; +- +- mcu_ringacc: ringacc@2b800000 { +- compatible = "ti,am654-navss-ringacc"; +- reg = <0x0 0x2b800000 0x0 0x400000>, +- <0x0 0x2b000000 0x0 0x400000>, +- <0x0 0x28590000 0x0 0x100>, +- <0x0 0x2a500000 0x0 0x40000>; +- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; +- ti,num-rings = <286>; +- ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <195>; +- msi-parent = <&inta_main_udmass>; +- }; +- +- mcu_udmap: dma-controller@285c0000 { +- compatible = "ti,am654-navss-mcu-udmap"; +- reg = <0x0 0x285c0000 0x0 0x100>, +- <0x0 0x2a800000 0x0 0x40000>, +- <0x0 0x2aa00000 0x0 0x40000>; +- reg-names = "gcfg", "rchanrt", "tchanrt"; +- msi-parent = <&inta_main_udmass>; +- #dma-cells = <1>; +- +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <194>; +- ti,ringacc = <&mcu_ringacc>; +- +- ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ +- <0xd>; /* TX_CHAN */ +- ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ +- <0xa>; /* RX_CHAN */ +- ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ +- }; +- }; +- +- fss: fss@47000000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ospi0: spi@47040000 { +- compatible = "ti,am654-ospi", "cdns,qspi-nor"; +- reg = <0x0 0x47040000 0x0 0x100>, +- <0x5 0x00000000 0x1 0x0000000>; +- interrupts = ; +- cdns,fifo-depth = <256>; +- cdns,fifo-width = <4>; +- cdns,trigger-address = <0x0>; +- clocks = <&k3_clks 248 0>; +- assigned-clocks = <&k3_clks 248 0>; +- assigned-clock-parents = <&k3_clks 248 2>; +- assigned-clock-rates = <166666666>; +- power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- ospi1: spi@47050000 { +- compatible = "ti,am654-ospi", "cdns,qspi-nor"; +- reg = <0x0 0x47050000 0x0 0x100>, +- <0x7 0x00000000 0x1 0x00000000>; +- interrupts = ; +- cdns,fifo-depth = <256>; +- cdns,fifo-width = <4>; +- cdns,trigger-address = <0x0>; +- clocks = <&k3_clks 249 6>; +- power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- mcu_cpsw: ethernet@46000000 { +- compatible = "ti,am654-cpsw-nuss"; +- #address-cells = <2>; +- #size-cells = <2>; +- reg = <0x0 0x46000000 0x0 0x200000>; +- reg-names = "cpsw_nuss"; +- ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; +- dma-coherent; +- clocks = <&k3_clks 5 10>; +- clock-names = "fck"; +- power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>; +- +- dmas = <&mcu_udmap 0xf000>, +- <&mcu_udmap 0xf001>, +- <&mcu_udmap 0xf002>, +- <&mcu_udmap 0xf003>, +- <&mcu_udmap 0xf004>, +- <&mcu_udmap 0xf005>, +- <&mcu_udmap 0xf006>, +- <&mcu_udmap 0xf007>, +- <&mcu_udmap 0x7000>; +- dma-names = "tx0", "tx1", "tx2", "tx3", +- "tx4", "tx5", "tx6", "tx7", +- "rx"; +- +- ethernet-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpsw_port1: port@1 { +- reg = <1>; +- ti,mac-only; +- label = "port1"; +- ti,syscon-efuse = <&mcu_conf 0x200>; +- phys = <&phy_gmii_sel 1>; +- }; +- }; +- +- davinci_mdio: mdio@f00 { +- compatible = "ti,cpsw-mdio","ti,davinci_mdio"; +- reg = <0x0 0xf00 0x0 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&k3_clks 5 10>; +- clock-names = "fck"; +- bus_freq = <1000000>; +- }; +- +- cpts@3d000 { +- compatible = "ti,am65-cpts"; +- reg = <0x0 0x3d000 0x0 0x400>; +- clocks = <&mcu_cpsw_cpts_mux>; +- clock-names = "cpts"; +- interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "cpts"; +- ti,cpts-ext-ts-inputs = <4>; +- ti,cpts-periodic-outputs = <2>; +- +- mcu_cpsw_cpts_mux: refclk-mux { +- #clock-cells = <0>; +- clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, +- <&k3_clks 118 6>, <&k3_clks 118 3>, +- <&k3_clks 118 8>, <&k3_clks 118 14>, +- <&k3_clks 120 3>, <&k3_clks 121 3>; +- assigned-clocks = <&mcu_cpsw_cpts_mux>; +- assigned-clock-parents = <&k3_clks 118 5>; +- }; +- }; +- }; +- +- mcu_r5fss0: r5fss@41000000 { +- compatible = "ti,am654-r5fss"; +- ti,cluster-mode = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x41000000 0x00 0x41000000 0x20000>, +- <0x41400000 0x00 0x41400000 0x20000>; +- power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>; +- +- mcu_r5fss0_core0: r5f@41000000 { +- compatible = "ti,am654-r5f"; +- reg = <0x41000000 0x00008000>, +- <0x41010000 0x00008000>; +- reg-names = "atcm", "btcm"; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <159>; +- ti,sci-proc-ids = <0x01 0xff>; +- resets = <&k3_reset 159 1>; +- firmware-name = "am65x-mcu-r5f0_0-fw"; +- ti,atcm-enable = <1>; +- ti,btcm-enable = <1>; +- ti,loczrama = <1>; +- }; +- +- mcu_r5fss0_core1: r5f@41400000 { +- compatible = "ti,am654-r5f"; +- reg = <0x41400000 0x00008000>, +- <0x41410000 0x00008000>; +- reg-names = "atcm", "btcm"; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <245>; +- ti,sci-proc-ids = <0x02 0xff>; +- resets = <&k3_reset 245 1>; +- firmware-name = "am65x-mcu-r5f0_1-fw"; +- ti,atcm-enable = <1>; +- ti,btcm-enable = <1>; +- ti,loczrama = <1>; +- }; +- }; +- +- mcu_rti1: watchdog@40610000 { +- compatible = "ti,j7-rti-wdt"; +- reg = <0x0 0x40610000 0x0 0x100>; +- clocks = <&k3_clks 135 0>; +- power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>; +- assigned-clocks = <&k3_clks 135 0>; +- assigned-clock-parents = <&k3_clks 135 4>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-am65-wakeup.dtsi b/scripts/dtc/include-prefixes/arm64/ti/k3-am65-wakeup.dtsi +deleted file mode 100644 +index 9d21cdf6fce8..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-am65-wakeup.dtsi ++++ /dev/null +@@ -1,107 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for AM6 SoC Family Wakeup Domain peripherals +- * +- * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-&cbass_wakeup { +- dmsc: system-controller@44083000 { +- compatible = "ti,am654-sci"; +- ti,host-id = <12>; +- +- mbox-names = "rx", "tx"; +- +- mboxes= <&secure_proxy_main 11>, +- <&secure_proxy_main 13>; +- +- reg-names = "debug_messages"; +- reg = <0x44083000 0x1000>; +- +- k3_pds: power-controller { +- compatible = "ti,sci-pm-domain"; +- #power-domain-cells = <2>; +- }; +- +- k3_clks: clock-controller { +- compatible = "ti,k2g-sci-clk"; +- #clock-cells = <2>; +- }; +- +- k3_reset: reset-controller { +- compatible = "ti,sci-reset"; +- #reset-cells = <2>; +- }; +- }; +- +- chipid@43000014 { +- compatible = "ti,am654-chipid"; +- reg = <0x43000014 0x4>; +- }; +- +- wkup_pmx0: pinctrl@4301c000 { +- compatible = "pinctrl-single"; +- reg = <0x4301c000 0x118>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0xffffffff>; +- }; +- +- wkup_uart0: serial@42300000 { +- compatible = "ti,am654-uart"; +- reg = <0x42300000 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- wkup_i2c0: i2c@42120000 { +- compatible = "ti,am654-i2c", "ti,omap4-i2c"; +- reg = <0x42120000 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 115 1>; +- power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- intr_wkup_gpio: interrupt-controller@42200000 { +- compatible = "ti,sci-intr"; +- reg = <0x42200000 0x200>; +- ti,intr-trigger-type = <1>; +- interrupt-controller; +- interrupt-parent = <&gic500>; +- #interrupt-cells = <1>; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <156>; +- ti,interrupt-ranges = <0 712 16>; +- }; +- +- wkup_gpio0: gpio@42110000 { +- compatible = "ti,am654-gpio", "ti,keystone-gpio"; +- reg = <0x42110000 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&intr_wkup_gpio>; +- interrupts = <60>, <61>, <62>, <63>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <56>; +- ti,davinci-gpio-unbanked = <0>; +- clocks = <&k3_clks 59 0>; +- clock-names = "gpio"; +- }; +- +- wkup_vtm0: temperature-sensor@42050000 { +- compatible = "ti,am654-vtm"; +- reg = <0x42050000 0x25c>; +- power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; +- #thermal-sensor-cells = <1>; +- }; +- +- thermal_zones: thermal-zones { +- #include "k3-am654-industrial-thermal.dtsi" +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-am65.dtsi b/scripts/dtc/include-prefixes/arm64/ti/k3-am65.dtsi +deleted file mode 100644 +index a9fc1af03f27..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-am65.dtsi ++++ /dev/null +@@ -1,123 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for AM6 SoC Family +- * +- * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- model = "Texas Instruments K3 AM654 SoC"; +- compatible = "ti,am654"; +- interrupt-parent = <&gic500>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- serial0 = &wkup_uart0; +- serial1 = &mcu_uart0; +- serial2 = &main_uart0; +- serial3 = &main_uart1; +- serial4 = &main_uart2; +- i2c0 = &wkup_i2c0; +- i2c1 = &mcu_i2c0; +- i2c2 = &main_i2c0; +- i2c3 = &main_i2c1; +- i2c4 = &main_i2c2; +- i2c5 = &main_i2c3; +- ethernet0 = &cpsw_port1; +- }; +- +- chosen { }; +- +- firmware { +- optee { +- compatible = "linaro,optee-tz"; +- method = "smc"; +- }; +- +- psci: psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- }; +- +- a53_timer0: timer-cl0-cpu0 { +- compatible = "arm,armv8-timer"; +- interrupts = , /* cntpsirq */ +- , /* cntpnsirq */ +- , /* cntvirq */ +- ; /* cnthpirq */ +- }; +- +- pmu: pmu { +- compatible = "arm,cortex-a53-pmu"; +- /* Recommendation from GIC500 TRM Table A.3 */ +- interrupts = ; +- }; +- +- cbass_main: bus@100000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ +- <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ +- <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ +- <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ +- <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ +- <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */ +- <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ +- /* MCUSS Range */ +- <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, +- <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, +- <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ +- <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, +- <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, +- <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, +- <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, +- <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, +- <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, +- <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, +- <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, +- <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>, +- <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, +- <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; +- +- cbass_mcu: bus@28380000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ +- <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */ +- <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ +- <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ +- <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ +- <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */ +- <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */ +- <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ +- <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ +- <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */ +- <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /* FSS OSPI0 data region 1 */ +- <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/ +- <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/ +- +- cbass_wakeup: bus@42040000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- /* WKUP Basic peripherals */ +- ranges = <0x42040000 0x00 0x42040000 0x03ac2400>; +- }; +- }; +- }; +-}; +- +-/* Now include the peripherals for each bus segments */ +-#include "k3-am65-main.dtsi" +-#include "k3-am65-mcu.dtsi" +-#include "k3-am65-wakeup.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-am6528-iot2050-basic.dts b/scripts/dtc/include-prefixes/arm64/ti/k3-am6528-iot2050-basic.dts +deleted file mode 100644 +index 94bb5dd39122..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-am6528-iot2050-basic.dts ++++ /dev/null +@@ -1,66 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) Siemens AG, 2018-2021 +- * +- * Authors: +- * Le Jin +- * Jan Kiszka +- * +- * AM6528-based (dual-core) IOT2050 Basic variant +- * 1 GB RAM, no eMMC, main_uart0 on connector X30 +- */ +- +-/dts-v1/; +- +-#include "k3-am65-iot2050-common.dtsi" +- +-/ { +- compatible = "siemens,iot2050-basic", "ti,am654"; +- model = "SIMATIC IOT2050 Basic"; +- +- memory@80000000 { +- device_type = "memory"; +- /* 1G RAM */ +- reg = <0x00000000 0x80000000 0x00000000 0x40000000>; +- }; +- +- cpus { +- cpu-map { +- /delete-node/ cluster1; +- }; +- /delete-node/ cpu@100; +- /delete-node/ cpu@101; +- }; +- +- /delete-node/ l2-cache1; +-}; +- +-/* eMMC */ +-&sdhci0 { +- status = "disabled"; +-}; +- +-&main_pmx0 { +- main_uart0_pins_default: main-uart0-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ +- AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ +- AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */ +- AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */ +- AM65X_IOPAD(0x0188, PIN_INPUT, 1) /* (D25) UART0_DCDn */ +- AM65X_IOPAD(0x018c, PIN_INPUT, 1) /* (B26) UART0_DSRn */ +- AM65X_IOPAD(0x0190, PIN_OUTPUT, 1) /* (A24) UART0_DTRn */ +- AM65X_IOPAD(0x0194, PIN_INPUT, 1) /* (E24) UART0_RIN */ +- >; +- }; +-}; +- +-&main_uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_uart0_pins_default>; +-}; +- +-&mcu_r5fss0 { +- /* lock-step mode not supported on this board */ +- ti,cluster-mode = <0>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-am654-base-board.dts b/scripts/dtc/include-prefixes/arm64/ti/k3-am654-base-board.dts +deleted file mode 100644 +index cfbcebfa37c1..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-am654-base-board.dts ++++ /dev/null +@@ -1,553 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/dts-v1/; +- +-#include "k3-am654.dtsi" +-#include +-#include +- +-/ { +- compatible = "ti,am654-evm", "ti,am654"; +- model = "Texas Instruments AM654 Base Board"; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- bootargs = "earlycon=ns16550a,mmio32,0x02800000"; +- }; +- +- memory@80000000 { +- device_type = "memory"; +- /* 4G RAM */ +- reg = <0x00000000 0x80000000 0x00000000 0x80000000>, +- <0x00000008 0x80000000 0x00000000 0x80000000>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- secure_ddr: secure-ddr@9e800000 { +- reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */ +- alignment = <0x1000>; +- no-map; +- }; +- +- mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { +- compatible = "shared-dma-pool"; +- reg = <0 0xa0000000 0 0x100000>; +- no-map; +- }; +- +- mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { +- compatible = "shared-dma-pool"; +- reg = <0 0xa0100000 0 0xf00000>; +- no-map; +- }; +- +- mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { +- compatible = "shared-dma-pool"; +- reg = <0 0xa1000000 0 0x100000>; +- no-map; +- }; +- +- mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { +- compatible = "shared-dma-pool"; +- reg = <0 0xa1100000 0 0xf00000>; +- no-map; +- }; +- +- rtos_ipc_memory_region: ipc-memories@a2000000 { +- reg = <0x00 0xa2000000 0x00 0x00100000>; +- alignment = <0x1000>; +- no-map; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- pinctrl-names = "default"; +- pinctrl-0 = <&push_button_pins_default>; +- +- sw5 { +- label = "GPIO Key USER1"; +- linux,code = ; +- gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>; +- }; +- +- sw6 { +- label = "GPIO Key USER2"; +- linux,code = ; +- gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- evm_12v0: fixedregulator-evm12v0 { +- /* main supply */ +- compatible = "regulator-fixed"; +- regulator-name = "evm_12v0"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc3v3_io: fixedregulator-vcc3v3io { +- /* Output of TPS54334 */ +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&evm_12v0>; +- }; +- +- vdd_mmc1_sd: fixedregulator-sd { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_mmc1_sd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- enable-active-high; +- vin-supply = <&vcc3v3_io>; +- gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&wkup_pmx0 { +- wkup_i2c0_pins_default: wkup-i2c0-pins-default { +- pinctrl-single,pins = < +- AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */ +- AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */ +- >; +- }; +- +- push_button_pins_default: push-button-pins-default { +- pinctrl-single,pins = < +- AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */ +- AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */ +- >; +- }; +- +- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { +- pinctrl-single,pins = < +- AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */ +- AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */ +- AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */ +- AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */ +- AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */ +- AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */ +- AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */ +- AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */ +- AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */ +- AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */ +- AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */ +- >; +- }; +- +- wkup_pca554_default: wkup-pca554-default { +- pinctrl-single,pins = < +- AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ +- >; +- }; +- +- mcu_cpsw_pins_default: mcu-cpsw-pins-default { +- pinctrl-single,pins = < +- AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */ +- AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */ +- AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */ +- AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */ +- AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */ +- AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */ +- AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */ +- AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */ +- AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */ +- AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */ +- AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */ +- AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */ +- >; +- }; +- +- mcu_mdio_pins_default: mcu-mdio1-pins-default { +- pinctrl-single,pins = < +- AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ +- AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ +- >; +- }; +-}; +- +-&main_pmx0 { +- main_uart0_pins_default: main-uart0-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ +- AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ +- AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */ +- AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */ +- >; +- }; +- +- main_i2c2_pins_default: main-i2c2-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */ +- AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */ +- >; +- }; +- +- main_spi0_pins_default: main-spi0-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */ +- AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */ +- AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */ +- AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */ +- >; +- }; +- +- main_mmc0_pins_default: main-mmc0-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ +- AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ +- AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ +- AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ +- AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ +- AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ +- AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ +- AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ +- AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ +- AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ +- AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */ +- AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ +- >; +- }; +- +- main_mmc1_pins_default: main-mmc1-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ +- AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ +- AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */ +- AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */ +- AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */ +- AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */ +- AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */ +- AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */ +- >; +- }; +- +- usb1_pins_default: usb1-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ +- >; +- }; +-}; +- +-&main_pmx1 { +- main_i2c0_pins_default: main-i2c0-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */ +- AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */ +- >; +- }; +- +- main_i2c1_pins_default: main-i2c1-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */ +- AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */ +- >; +- }; +- +- ecap0_pins_default: ecap0-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ +- >; +- }; +-}; +- +-&wkup_uart0 { +- /* Wakeup UART is used by System firmware */ +- status = "reserved"; +-}; +- +-&main_uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_uart0_pins_default>; +- power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; +-}; +- +-&wkup_i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&wkup_i2c0_pins_default>; +- clock-frequency = <400000>; +- +- pca9554: gpio@39 { +- compatible = "nxp,pca9554"; +- reg = <0x39>; +- gpio-controller; +- #gpio-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&wkup_pca554_default>; +- interrupt-parent = <&wkup_gpio0>; +- interrupts = <25 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +-}; +- +-&main_i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_i2c0_pins_default>; +- clock-frequency = <400000>; +- +- pca9555: gpio@21 { +- compatible = "nxp,pca9555"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&main_i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_i2c1_pins_default>; +- clock-frequency = <400000>; +-}; +- +-&main_i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_i2c2_pins_default>; +- clock-frequency = <400000>; +-}; +- +-&ecap0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&ecap0_pins_default>; +-}; +- +-&main_spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_spi0_pins_default>; +- #address-cells = <1>; +- #size-cells= <0>; +- ti,pindir-d0-out-d1-in; +- +- flash@0{ +- compatible = "jedec,spi-nor"; +- reg = <0x0>; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <1>; +- spi-max-frequency = <48000000>; +- #address-cells = <1>; +- #size-cells= <1>; +- }; +-}; +- +-&sdhci0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_mmc0_pins_default>; +- bus-width = <8>; +- non-removable; +- ti,driver-strength-ohm = <50>; +- disable-wp; +-}; +- +-/* +- * Because of erratas i2025 and i2026 for silicon revision 1.0, the +- * SD card interface might fail. Boards with sr1.0 are recommended to +- * disable sdhci1 +- */ +-&sdhci1 { +- vmmc-supply = <&vdd_mmc1_sd>; +- pinctrl-names = "default"; +- pinctrl-0 = <&main_mmc1_pins_default>; +- ti,driver-strength-ohm = <50>; +- disable-wp; +-}; +- +-&usb1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usb1_pins_default>; +- dr_mode = "otg"; +-}; +- +-&dwc3_0 { +- status = "disabled"; +-}; +- +-&usb0_phy { +- status = "disabled"; +-}; +- +-&tscadc0 { +- adc { +- ti,adc-channels = <0 1 2 3 4 5 6 7>; +- }; +-}; +- +-&tscadc1 { +- adc { +- ti,adc-channels = <0 1 2 3 4 5 6 7>; +- }; +-}; +- +-&serdes0 { +- status = "disabled"; +-}; +- +-&serdes1 { +- status = "disabled"; +-}; +- +-&pcie0_rc { +- status = "disabled"; +-}; +- +-&pcie0_ep { +- status = "disabled"; +-}; +- +-&pcie1_rc { +- status = "disabled"; +-}; +- +-&pcie1_ep { +- status = "disabled"; +-}; +- +-&mailbox0_cluster0 { +- interrupts = <436>; +- +- mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { +- ti,mbox-tx = <1 0 0>; +- ti,mbox-rx = <0 0 0>; +- }; +-}; +- +-&mailbox0_cluster1 { +- interrupts = <432>; +- +- mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { +- ti,mbox-tx = <1 0 0>; +- ti,mbox-rx = <0 0 0>; +- }; +-}; +- +-&mailbox0_cluster2 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster3 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster4 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster5 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster6 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster7 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster8 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster9 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster10 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster11 { +- status = "disabled"; +-}; +- +-&mcu_r5fss0_core0 { +- memory-region = <&mcu_r5fss0_core0_dma_memory_region>, +- <&mcu_r5fss0_core0_memory_region>; +- mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; +-}; +- +-&mcu_r5fss0_core1 { +- memory-region = <&mcu_r5fss0_core1_dma_memory_region>, +- <&mcu_r5fss0_core1_memory_region>; +- mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; +-}; +- +-&ospi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; +- +- flash@0{ +- compatible = "jedec,spi-nor"; +- reg = <0x0>; +- spi-tx-bus-width = <8>; +- spi-rx-bus-width = <8>; +- spi-max-frequency = <25000000>; +- cdns,tshsl-ns = <60>; +- cdns,tsd2d-ns = <60>; +- cdns,tchsh-ns = <60>; +- cdns,tslch-ns = <60>; +- cdns,read-delay = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&mcu_cpsw { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +-}; +- +-&davinci_mdio { +- phy0: ethernet-phy@0 { +- reg = <0>; +- ti,rx-internal-delay = ; +- ti,fifo-depth = ; +- }; +-}; +- +-&cpsw_port1 { +- phy-mode = "rgmii-rxid"; +- phy-handle = <&phy0>; +-}; +- +-&mcasp0 { +- status = "disabled"; +-}; +- +-&mcasp1 { +- status = "disabled"; +-}; +- +-&mcasp2 { +- status = "disabled"; +-}; +- +-&dss { +- status = "disabled"; +-}; +- +-&icssg0_mdio { +- status = "disabled"; +-}; +- +-&icssg1_mdio { +- status = "disabled"; +-}; +- +-&icssg2_mdio { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-am654-industrial-thermal.dtsi b/scripts/dtc/include-prefixes/arm64/ti/k3-am654-industrial-thermal.dtsi +deleted file mode 100644 +index 9021c738056b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-am654-industrial-thermal.dtsi ++++ /dev/null +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include +- +-mpu0_thermal: mpu0-thermal { +- polling-delay-passive = <250>; /* milliseconds */ +- polling-delay = <500>; /* milliseconds */ +- thermal-sensors = <&wkup_vtm0 0>; +- +- trips { +- mpu0_crit: mpu0-crit { +- temperature = <125000>; /* milliCelsius */ +- hysteresis = <2000>; /* milliCelsius */ +- type = "critical"; +- }; +- }; +-}; +- +-mpu1_thermal: mpu1-thermal { +- polling-delay-passive = <250>; /* milliseconds */ +- polling-delay = <500>; /* milliseconds */ +- thermal-sensors = <&wkup_vtm0 1>; +- +- trips { +- mpu1_crit: mpu1-crit { +- temperature = <125000>; /* milliCelsius */ +- hysteresis = <2000>; /* milliCelsius */ +- type = "critical"; +- }; +- }; +-}; +- +-mcu_thermal: mcu-thermal { +- polling-delay-passive = <250>; /* milliseconds */ +- polling-delay = <500>; /* milliseconds */ +- thermal-sensors = <&wkup_vtm0 2>; +- +- trips { +- mcu_crit: mcu-crit { +- temperature = <125000>; /* milliCelsius */ +- hysteresis = <2000>; /* milliCelsius */ +- type = "critical"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-am654.dtsi b/scripts/dtc/include-prefixes/arm64/ti/k3-am654.dtsi +deleted file mode 100644 +index f0a6541b8042..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-am654.dtsi ++++ /dev/null +@@ -1,115 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for AM6 SoC family in Quad core configuration +- * +- * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include "k3-am65.dtsi" +- +-/ { +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu-map { +- cluster0: cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- +- core1 { +- cpu = <&cpu1>; +- }; +- }; +- +- cluster1: cluster1 { +- core0 { +- cpu = <&cpu2>; +- }; +- +- core1 { +- cpu = <&cpu3>; +- }; +- }; +- }; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a53"; +- reg = <0x000>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&L2_0>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a53"; +- reg = <0x001>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&L2_0>; +- }; +- +- cpu2: cpu@100 { +- compatible = "arm,cortex-a53"; +- reg = <0x100>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&L2_1>; +- }; +- +- cpu3: cpu@101 { +- compatible = "arm,cortex-a53"; +- reg = <0x101>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0x8000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&L2_1>; +- }; +- }; +- +- L2_0: l2-cache0 { +- compatible = "cache"; +- cache-level = <2>; +- cache-size = <0x80000>; +- cache-line-size = <64>; +- cache-sets = <512>; +- next-level-cache = <&msmc_l3>; +- }; +- +- L2_1: l2-cache1 { +- compatible = "cache"; +- cache-level = <2>; +- cache-size = <0x80000>; +- cache-line-size = <64>; +- cache-sets = <512>; +- next-level-cache = <&msmc_l3>; +- }; +- +- msmc_l3: l3-cache0 { +- compatible = "cache"; +- cache-level = <3>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-am6548-iot2050-advanced.dts b/scripts/dtc/include-prefixes/arm64/ti/k3-am6548-iot2050-advanced.dts +deleted file mode 100644 +index ec9617c13cdb..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-am6548-iot2050-advanced.dts ++++ /dev/null +@@ -1,60 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) Siemens AG, 2018-2021 +- * +- * Authors: +- * Le Jin +- * Jan Kiszka +- * +- * AM6548-based (quad-core) IOT2050 Advanced variant +- * 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30 +- */ +- +-/dts-v1/; +- +-#include "k3-am65-iot2050-common.dtsi" +- +-/ { +- compatible = "siemens,iot2050-advanced", "ti,am654"; +- model = "SIMATIC IOT2050 Advanced"; +- +- memory@80000000 { +- device_type = "memory"; +- /* 2G RAM */ +- reg = <0x00000000 0x80000000 0x00000000 0x80000000>; +- }; +-}; +- +-&main_pmx0 { +- main_mmc0_pins_default: main-mmc0-pins-default { +- pinctrl-single,pins = < +- AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ +- AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ +- AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ +- AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ +- AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ +- AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ +- AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ +- AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ +- AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ +- AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ +- AM65X_IOPAD(0x01b8, PIN_OUTPUT_PULLUP, 7) /* (B23) MMC0_SDWP */ +- AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */ +- AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ +- >; +- }; +-}; +- +-/* eMMC */ +-&sdhci0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_mmc0_pins_default>; +- bus-width = <8>; +- non-removable; +- ti,driver-strength-ohm = <50>; +- disable-wp; +-}; +- +-&main_uart0 { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-j7200-common-proc-board.dts b/scripts/dtc/include-prefixes/arm64/ti/k3-j7200-common-proc-board.dts +deleted file mode 100644 +index d14f3c18b65f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-j7200-common-proc-board.dts ++++ /dev/null +@@ -1,352 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/dts-v1/; +- +-#include "k3-j7200-som-p0.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- chosen { +- stdout-path = "serial2:115200n8"; +- bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; +- }; +- +- evm_12v0: fixedregulator-evm12v0 { +- /* main supply */ +- compatible = "regulator-fixed"; +- regulator-name = "evm_12v0"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vsys_3v3: fixedregulator-vsys3v3 { +- /* Output of LM5140 */ +- compatible = "regulator-fixed"; +- regulator-name = "vsys_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&evm_12v0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vsys_5v0: fixedregulator-vsys5v0 { +- /* Output of LM5140 */ +- compatible = "regulator-fixed"; +- regulator-name = "vsys_5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&evm_12v0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_mmc1: fixedregulator-sd { +- /* Output of TPS22918 */ +- compatible = "regulator-fixed"; +- regulator-name = "vdd_mmc1"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- enable-active-high; +- vin-supply = <&vsys_3v3>; +- gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; +- }; +- +- vdd_sd_dv: gpio-regulator-TLV71033 { +- /* Output of TLV71033 */ +- compatible = "regulator-gpio"; +- regulator-name = "tlv71033"; +- pinctrl-names = "default"; +- pinctrl-0 = <&vdd_sd_dv_pins_default>; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- vin-supply = <&vsys_5v0>; +- gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>; +- states = <1800000 0x0>, +- <3300000 0x1>; +- }; +-}; +- +-&wkup_pmx0 { +- mcu_cpsw_pins_default: mcu-cpsw-pins-default { +- pinctrl-single,pins = < +- J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ +- J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ +- J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ +- J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ +- J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ +- J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ +- J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ +- J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ +- J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ +- J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ +- J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ +- J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ +- >; +- }; +- +- mcu_mdio_pins_default: mcu-mdio1-pins-default { +- pinctrl-single,pins = < +- J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ +- J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ +- >; +- }; +-}; +- +-&main_pmx0 { +- main_i2c0_pins_default: main-i2c0-pins-default { +- pinctrl-single,pins = < +- J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ +- J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ +- >; +- }; +- +- main_i2c1_pins_default: main-i2c1-pins-default { +- pinctrl-single,pins = < +- J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ +- J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */ +- >; +- }; +- +- main_mmc1_pins_default: main-mmc1-pins-default { +- pinctrl-single,pins = < +- J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ +- J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ +- J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ +- J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */ +- J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */ +- J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ +- J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ +- J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ +- >; +- }; +- +- main_usbss0_pins_default: main-usbss0-pins-default { +- pinctrl-single,pins = < +- J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ +- >; +- }; +- +- vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { +- pinctrl-single,pins = < +- J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ +- >; +- }; +-}; +- +-&wkup_uart0 { +- /* Wakeup UART is used by System firmware */ +- status = "reserved"; +-}; +- +-&main_uart0 { +- /* Shared with ATF on this platform */ +- power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; +-}; +- +-&main_uart2 { +- /* MAIN UART 2 is used by R5F firmware */ +- status = "reserved"; +-}; +- +-&main_uart3 { +- /* UART not brought out */ +- status = "disabled"; +-}; +- +-&main_uart4 { +- /* UART not brought out */ +- status = "disabled"; +-}; +- +-&main_uart5 { +- /* UART not brought out */ +- status = "disabled"; +-}; +- +-&main_uart6 { +- /* UART not brought out */ +- status = "disabled"; +-}; +- +-&main_uart7 { +- /* UART not brought out */ +- status = "disabled"; +-}; +- +-&main_uart8 { +- /* UART not brought out */ +- status = "disabled"; +-}; +- +-&main_uart9 { +- /* UART not brought out */ +- status = "disabled"; +-}; +- +-&main_gpio2 { +- status = "disabled"; +-}; +- +-&main_gpio4 { +- status = "disabled"; +-}; +- +-&main_gpio6 { +- status = "disabled"; +-}; +- +-&wkup_gpio1 { +- status = "disabled"; +-}; +- +-&mcu_cpsw { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +-}; +- +-&davinci_mdio { +- phy0: ethernet-phy@0 { +- reg = <0>; +- ti,rx-internal-delay = ; +- ti,fifo-depth = ; +- }; +-}; +- +-&cpsw_port1 { +- phy-mode = "rgmii-rxid"; +- phy-handle = <&phy0>; +-}; +- +-&main_i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_i2c0_pins_default>; +- clock-frequency = <400000>; +- +- exp1: gpio@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- exp2: gpio@22 { +- compatible = "ti,tca6424"; +- reg = <0x22>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-/* +- * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be +- * swapped on the CPB. +- * +- * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3. +- * The i2c1 of the CPB (as it is labeled) is not connected to j7200. +- */ +-&main_i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_i2c1_pins_default>; +- clock-frequency = <400000>; +- +- exp3: gpio@20 { +- compatible = "ti,tca6408"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn", +- "UB926_LOCK", "UB926_PWR_SW_CNTRL", +- "UB926_TUNER_RESET", "UB926_GPIO_SPARE", ""; +- }; +-}; +- +-&main_sdhci0 { +- /* eMMC */ +- non-removable; +- ti,driver-strength-ohm = <50>; +- disable-wp; +-}; +- +-&main_sdhci1 { +- /* SD card */ +- pinctrl-0 = <&main_mmc1_pins_default>; +- pinctrl-names = "default"; +- vmmc-supply = <&vdd_mmc1>; +- vqmmc-supply = <&vdd_sd_dv>; +- ti,driver-strength-ohm = <50>; +- disable-wp; +-}; +- +-&serdes_ln_ctrl { +- idle-states = , , +- , ; +-}; +- +-&usb_serdes_mux { +- idle-states = <1>; /* USB0 to SERDES lane 3 */ +-}; +- +-&usbss0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_usbss0_pins_default>; +- ti,vbus-divider; +- ti,usb2-only; +-}; +- +-&usb0 { +- dr_mode = "otg"; +- maximum-speed = "high-speed"; +-}; +- +-&tscadc0 { +- adc { +- ti,adc-channels = <0 1 2 3 4 5 6 7>; +- }; +-}; +- +-&serdes_refclk { +- clock-frequency = <100000000>; +-}; +- +-&serdes0 { +- serdes0_pcie_link: phy@0 { +- reg = <0>; +- cdns,num-lanes = <2>; +- #phy-cells = <0>; +- cdns,phy-type = ; +- resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; +- }; +- +- serdes0_qsgmii_link: phy@1 { +- reg = <2>; +- cdns,num-lanes = <1>; +- #phy-cells = <0>; +- cdns,phy-type = ; +- resets = <&serdes_wiz0 3>; +- }; +-}; +- +-&pcie1_rc { +- reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; +- phys = <&serdes0_pcie_link>; +- phy-names = "pcie-phy"; +- num-lanes = <2>; +-}; +- +-&pcie1_ep { +- phys = <&serdes0_pcie_link>; +- phy-names = "pcie-phy"; +- num-lanes = <2>; +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-j7200-main.dtsi b/scripts/dtc/include-prefixes/arm64/ti/k3-j7200-main.dtsi +deleted file mode 100644 +index 7daa28022044..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-j7200-main.dtsi ++++ /dev/null +@@ -1,777 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for J7200 SoC Family Main Domain peripherals +- * +- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/ { +- serdes_refclk: serdes-refclk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- }; +-}; +- +-&cbass_main { +- msmc_ram: sram@70000000 { +- compatible = "mmio-sram"; +- reg = <0x00 0x70000000 0x00 0x100000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00 0x00 0x70000000 0x100000>; +- +- atf-sram@0 { +- reg = <0x00 0x20000>; +- }; +- }; +- +- scm_conf: scm-conf@100000 { +- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; +- reg = <0x00 0x00100000 0x00 0x1c000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00 0x00 0x00100000 0x1c000>; +- +- serdes_ln_ctrl: mux-controller@4080 { +- compatible = "mmio-mux"; +- #mux-control-cells = <1>; +- mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ +- <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ +- }; +- +- usb_serdes_mux: mux-controller@4000 { +- compatible = "mmio-mux"; +- #mux-control-cells = <1>; +- mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ +- }; +- }; +- +- gic500: interrupt-controller@1800000 { +- compatible = "arm,gic-v3"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ +- <0x00 0x01900000 0x00 0x100000>; /* GICR */ +- +- /* vcpumntirq: virtual CPU interface maintenance interrupt */ +- interrupts = ; +- +- gic_its: msi-controller@1820000 { +- compatible = "arm,gic-v3-its"; +- reg = <0x00 0x01820000 0x00 0x10000>; +- socionext,synquacer-pre-its = <0x1000000 0x400000>; +- msi-controller; +- #msi-cells = <1>; +- }; +- }; +- +- main_gpio_intr: interrupt-controller@a00000 { +- compatible = "ti,sci-intr"; +- reg = <0x00 0x00a00000 0x00 0x800>; +- ti,intr-trigger-type = <1>; +- interrupt-controller; +- interrupt-parent = <&gic500>; +- #interrupt-cells = <1>; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <131>; +- ti,interrupt-ranges = <8 392 56>; +- }; +- +- main_navss: bus@30000000 { +- compatible = "simple-mfd"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; +- ti,sci-dev-id = <199>; +- dma-coherent; +- dma-ranges; +- +- main_navss_intr: interrupt-controller@310e0000 { +- compatible = "ti,sci-intr"; +- reg = <0x00 0x310e0000 0x00 0x4000>; +- ti,intr-trigger-type = <4>; +- interrupt-controller; +- interrupt-parent = <&gic500>; +- #interrupt-cells = <1>; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <213>; +- ti,interrupt-ranges = <0 64 64>, +- <64 448 64>, +- <128 672 64>; +- }; +- +- main_udmass_inta: msi-controller@33d00000 { +- compatible = "ti,sci-inta"; +- reg = <0x00 0x33d00000 0x00 0x100000>; +- interrupt-controller; +- #interrupt-cells = <0>; +- interrupt-parent = <&main_navss_intr>; +- msi-controller; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <209>; +- ti,interrupt-ranges = <0 0 256>; +- }; +- +- secure_proxy_main: mailbox@32c00000 { +- compatible = "ti,am654-secure-proxy"; +- #mbox-cells = <1>; +- reg-names = "target_data", "rt", "scfg"; +- reg = <0x00 0x32c00000 0x00 0x100000>, +- <0x00 0x32400000 0x00 0x100000>, +- <0x00 0x32800000 0x00 0x100000>; +- interrupt-names = "rx_011"; +- interrupts = ; +- }; +- +- hwspinlock: spinlock@30e00000 { +- compatible = "ti,am654-hwspinlock"; +- reg = <0x00 0x30e00000 0x00 0x1000>; +- #hwlock-cells = <1>; +- }; +- +- mailbox0_cluster0: mailbox@31f80000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f80000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster1: mailbox@31f81000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f81000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster2: mailbox@31f82000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f82000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster3: mailbox@31f83000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f83000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster4: mailbox@31f84000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f84000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster5: mailbox@31f85000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f85000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster6: mailbox@31f86000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f86000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster7: mailbox@31f87000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f87000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster8: mailbox@31f88000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f88000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster9: mailbox@31f89000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f89000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster10: mailbox@31f8a000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f8a000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster11: mailbox@31f8b000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f8b000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- main_ringacc: ringacc@3c000000 { +- compatible = "ti,am654-navss-ringacc"; +- reg = <0x00 0x3c000000 0x00 0x400000>, +- <0x00 0x38000000 0x00 0x400000>, +- <0x00 0x31120000 0x00 0x100>, +- <0x00 0x33000000 0x00 0x40000>; +- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; +- ti,num-rings = <1024>; +- ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <211>; +- msi-parent = <&main_udmass_inta>; +- }; +- +- main_udmap: dma-controller@31150000 { +- compatible = "ti,j721e-navss-main-udmap"; +- reg = <0x00 0x31150000 0x00 0x100>, +- <0x00 0x34000000 0x00 0x100000>, +- <0x00 0x35000000 0x00 0x100000>; +- reg-names = "gcfg", "rchanrt", "tchanrt"; +- msi-parent = <&main_udmass_inta>; +- #dma-cells = <1>; +- +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <212>; +- ti,ringacc = <&main_ringacc>; +- +- ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ +- <0x0f>, /* TX_HCHAN */ +- <0x10>; /* TX_UHCHAN */ +- ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ +- <0x0b>, /* RX_HCHAN */ +- <0x0c>; /* RX_UHCHAN */ +- ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ +- }; +- +- cpts@310d0000 { +- compatible = "ti,j721e-cpts"; +- reg = <0x00 0x310d0000 0x00 0x400>; +- reg-names = "cpts"; +- clocks = <&k3_clks 201 1>; +- clock-names = "cpts"; +- interrupts-extended = <&main_navss_intr 391>; +- interrupt-names = "cpts"; +- ti,cpts-periodic-outputs = <6>; +- ti,cpts-ext-ts-inputs = <8>; +- }; +- }; +- +- main_pmx0: pinctrl@11c000 { +- compatible = "pinctrl-single"; +- /* Proxy 0 addressing */ +- reg = <0x00 0x11c000 0x00 0x2b4>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0xffffffff>; +- }; +- +- main_uart0: serial@2800000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02800000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 146 2>; +- clock-names = "fclk"; +- }; +- +- main_uart1: serial@2810000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02810000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 278 2>; +- clock-names = "fclk"; +- }; +- +- main_uart2: serial@2820000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02820000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 279 2>; +- clock-names = "fclk"; +- }; +- +- main_uart3: serial@2830000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02830000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 280 2>; +- clock-names = "fclk"; +- }; +- +- main_uart4: serial@2840000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02840000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 281 2>; +- clock-names = "fclk"; +- }; +- +- main_uart5: serial@2850000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02850000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 282 2>; +- clock-names = "fclk"; +- }; +- +- main_uart6: serial@2860000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02860000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 283 2>; +- clock-names = "fclk"; +- }; +- +- main_uart7: serial@2870000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02870000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 284 2>; +- clock-names = "fclk"; +- }; +- +- main_uart8: serial@2880000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02880000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 285 2>; +- clock-names = "fclk"; +- }; +- +- main_uart9: serial@2890000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02890000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 286 2>; +- clock-names = "fclk"; +- }; +- +- main_i2c0: i2c@2000000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x00 0x2000000 0x00 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 187 1>; +- power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; +- }; +- +- main_i2c1: i2c@2010000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x00 0x2010000 0x00 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 188 1>; +- power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- main_i2c2: i2c@2020000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x00 0x2020000 0x00 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 189 1>; +- power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- main_i2c3: i2c@2030000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x00 0x2030000 0x00 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 190 1>; +- power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- main_i2c4: i2c@2040000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x00 0x2040000 0x00 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 191 1>; +- power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- main_i2c5: i2c@2050000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x00 0x2050000 0x00 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 192 1>; +- power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- main_i2c6: i2c@2060000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x00 0x2060000 0x00 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 193 1>; +- power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- main_sdhci0: mmc@4f80000 { +- compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; +- reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; +- interrupts = ; +- power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; +- clock-names = "clk_ahb", "clk_xin"; +- clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; +- ti,otap-del-sel-legacy = <0x0>; +- ti,otap-del-sel-mmc-hs = <0x0>; +- ti,otap-del-sel-ddr52 = <0x6>; +- ti,otap-del-sel-hs200 = <0x8>; +- ti,otap-del-sel-hs400 = <0x5>; +- ti,itap-del-sel-legacy = <0x10>; +- ti,itap-del-sel-mmc-hs = <0xa>; +- ti,strobe-sel = <0x77>; +- ti,clkbuf-sel = <0x7>; +- ti,trm-icp = <0x8>; +- bus-width = <8>; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- dma-coherent; +- }; +- +- main_sdhci1: mmc@4fb0000 { +- compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; +- reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; +- interrupts = ; +- power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; +- clock-names = "clk_ahb", "clk_xin"; +- clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; +- ti,otap-del-sel-legacy = <0x0>; +- ti,otap-del-sel-sd-hs = <0x0>; +- ti,otap-del-sel-sdr12 = <0xf>; +- ti,otap-del-sel-sdr25 = <0xf>; +- ti,otap-del-sel-sdr50 = <0xc>; +- ti,otap-del-sel-sdr104 = <0x5>; +- ti,otap-del-sel-ddr50 = <0xc>; +- ti,itap-del-sel-legacy = <0x0>; +- ti,itap-del-sel-sd-hs = <0x0>; +- ti,itap-del-sel-sdr12 = <0x0>; +- ti,itap-del-sel-sdr25 = <0x0>; +- ti,clkbuf-sel = <0x7>; +- ti,trm-icp = <0x8>; +- dma-coherent; +- }; +- +- serdes_wiz0: wiz@5060000 { +- compatible = "ti,j721e-wiz-10g"; +- #address-cells = <1>; +- #size-cells = <1>; +- power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; +- clock-names = "fck", "core_ref_clk", "ext_ref_clk"; +- num-lanes = <4>; +- #reset-cells = <1>; +- ranges = <0x5060000 0x0 0x5060000 0x10000>; +- +- assigned-clocks = <&k3_clks 292 85>; +- assigned-clock-parents = <&k3_clks 292 89>; +- +- wiz0_pll0_refclk: pll0-refclk { +- clocks = <&k3_clks 292 85>, <&serdes_refclk>; +- clock-output-names = "wiz0_pll0_refclk"; +- #clock-cells = <0>; +- assigned-clocks = <&wiz0_pll0_refclk>; +- assigned-clock-parents = <&k3_clks 292 85>; +- }; +- +- wiz0_pll1_refclk: pll1-refclk { +- clocks = <&k3_clks 292 85>, <&serdes_refclk>; +- clock-output-names = "wiz0_pll1_refclk"; +- #clock-cells = <0>; +- assigned-clocks = <&wiz0_pll1_refclk>; +- assigned-clock-parents = <&k3_clks 292 85>; +- }; +- +- wiz0_refclk_dig: refclk-dig { +- clocks = <&k3_clks 292 85>, <&serdes_refclk>; +- clock-output-names = "wiz0_refclk_dig"; +- #clock-cells = <0>; +- assigned-clocks = <&wiz0_refclk_dig>; +- assigned-clock-parents = <&k3_clks 292 85>; +- }; +- +- wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { +- clocks = <&wiz0_refclk_dig>; +- #clock-cells = <0>; +- }; +- +- serdes0: serdes@5060000 { +- compatible = "ti,j721e-serdes-10g"; +- reg = <0x05060000 0x00010000>; +- reg-names = "torrent_phy"; +- resets = <&serdes_wiz0 0>; +- reset-names = "torrent_reset"; +- clocks = <&wiz0_pll0_refclk>; +- clock-names = "refclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- pcie1_rc: pcie@2910000 { +- compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; +- reg = <0x00 0x02910000 0x00 0x1000>, +- <0x00 0x02917000 0x00 0x400>, +- <0x00 0x0d800000 0x00 0x00800000>, +- <0x00 0x18000000 0x00 0x00001000>; +- reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; +- interrupt-names = "link_state"; +- interrupts = ; +- device_type = "pci"; +- ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; +- max-link-speed = <3>; +- num-lanes = <4>; +- power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 240 6>; +- clock-names = "fck"; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x0 0xff>; +- cdns,no-bar-match-nbits = <64>; +- vendor-id = <0x104c>; +- device-id = <0xb00f>; +- msi-map = <0x0 &gic_its 0x0 0x10000>; +- dma-coherent; +- ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, +- <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; +- dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; +- }; +- +- pcie1_ep: pcie-ep@2910000 { +- compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; +- reg = <0x00 0x02910000 0x00 0x1000>, +- <0x00 0x02917000 0x00 0x400>, +- <0x00 0x0d800000 0x00 0x00800000>, +- <0x00 0x18000000 0x00 0x08000000>; +- reg-names = "intd_cfg", "user_cfg", "reg", "mem"; +- interrupt-names = "link_state"; +- interrupts = ; +- ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; +- max-link-speed = <3>; +- num-lanes = <4>; +- power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 240 6>; +- clock-names = "fck"; +- max-functions = /bits/ 8 <6>; +- dma-coherent; +- }; +- +- usbss0: cdns-usb@4104000 { +- compatible = "ti,j721e-usb"; +- reg = <0x00 0x4104000 0x00 0x100>; +- dma-coherent; +- power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; +- clock-names = "ref", "lpm"; +- assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ +- assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- usb0: usb@6000000 { +- compatible = "cdns,usb3"; +- reg = <0x00 0x6000000 0x00 0x10000>, +- <0x00 0x6010000 0x00 0x10000>, +- <0x00 0x6020000 0x00 0x10000>; +- reg-names = "otg", "xhci", "dev"; +- interrupts = , /* irq.0 */ +- , /* irq.6 */ +- ; /* otgirq.0 */ +- interrupt-names = "host", +- "peripheral", +- "otg"; +- maximum-speed = "super-speed"; +- dr_mode = "otg"; +- cdns,phyrst-a-enable; +- }; +- }; +- +- main_gpio0: gpio@600000 { +- compatible = "ti,j721e-gpio", "ti,keystone-gpio"; +- reg = <0x00 0x00600000 0x00 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&main_gpio_intr>; +- interrupts = <145>, <146>, <147>, <148>, +- <149>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <69>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 105 0>; +- clock-names = "gpio"; +- }; +- +- main_gpio2: gpio@610000 { +- compatible = "ti,j721e-gpio", "ti,keystone-gpio"; +- reg = <0x00 0x00610000 0x00 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&main_gpio_intr>; +- interrupts = <154>, <155>, <156>, <157>, +- <158>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <69>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 107 0>; +- clock-names = "gpio"; +- }; +- +- main_gpio4: gpio@620000 { +- compatible = "ti,j721e-gpio", "ti,keystone-gpio"; +- reg = <0x00 0x00620000 0x00 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&main_gpio_intr>; +- interrupts = <163>, <164>, <165>, <166>, +- <167>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <69>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 109 0>; +- clock-names = "gpio"; +- }; +- +- main_gpio6: gpio@630000 { +- compatible = "ti,j721e-gpio", "ti,keystone-gpio"; +- reg = <0x00 0x00630000 0x00 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&main_gpio_intr>; +- interrupts = <172>, <173>, <174>, <175>, +- <176>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <69>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 111 0>; +- clock-names = "gpio"; +- }; +- +- main_r5fss0: r5fss@5c00000 { +- compatible = "ti,j7200-r5fss"; +- ti,cluster-mode = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x5c00000 0x00 0x5c00000 0x20000>, +- <0x5d00000 0x00 0x5d00000 0x20000>; +- power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; +- +- main_r5fss0_core0: r5f@5c00000 { +- compatible = "ti,j7200-r5f"; +- reg = <0x5c00000 0x00010000>, +- <0x5c10000 0x00010000>; +- reg-names = "atcm", "btcm"; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <245>; +- ti,sci-proc-ids = <0x06 0xff>; +- resets = <&k3_reset 245 1>; +- firmware-name = "j7200-main-r5f0_0-fw"; +- ti,atcm-enable = <1>; +- ti,btcm-enable = <1>; +- ti,loczrama = <1>; +- }; +- +- main_r5fss0_core1: r5f@5d00000 { +- compatible = "ti,j7200-r5f"; +- reg = <0x5d00000 0x00008000>, +- <0x5d10000 0x00008000>; +- reg-names = "atcm", "btcm"; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <246>; +- ti,sci-proc-ids = <0x07 0xff>; +- resets = <&k3_reset 246 1>; +- firmware-name = "j7200-main-r5f0_1-fw"; +- ti,atcm-enable = <1>; +- ti,btcm-enable = <1>; +- ti,loczrama = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-j7200-mcu-wakeup.dtsi b/scripts/dtc/include-prefixes/arm64/ti/k3-j7200-mcu-wakeup.dtsi +deleted file mode 100644 +index 1044ec6c4b0d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-j7200-mcu-wakeup.dtsi ++++ /dev/null +@@ -1,378 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals +- * +- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-&cbass_mcu_wakeup { +- dmsc: system-controller@44083000 { +- compatible = "ti,k2g-sci"; +- ti,host-id = <12>; +- +- mbox-names = "rx", "tx"; +- +- mboxes= <&secure_proxy_main 11>, +- <&secure_proxy_main 13>; +- +- reg-names = "debug_messages"; +- reg = <0x00 0x44083000 0x00 0x1000>; +- +- k3_pds: power-controller { +- compatible = "ti,sci-pm-domain"; +- #power-domain-cells = <2>; +- }; +- +- k3_clks: clock-controller { +- compatible = "ti,k2g-sci-clk"; +- #clock-cells = <2>; +- }; +- +- k3_reset: reset-controller { +- compatible = "ti,sci-reset"; +- #reset-cells = <2>; +- }; +- }; +- +- mcu_conf: syscon@40f00000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x00 0x40f00000 0x00 0x20000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00 0x00 0x40f00000 0x20000>; +- +- phy_gmii_sel: phy@4040 { +- compatible = "ti,am654-phy-gmii-sel"; +- reg = <0x4040 0x4>; +- #phy-cells = <1>; +- }; +- }; +- +- chipid@43000014 { +- compatible = "ti,am654-chipid"; +- reg = <0x00 0x43000014 0x00 0x4>; +- }; +- +- wkup_pmx0: pinctrl@4301c000 { +- compatible = "pinctrl-single"; +- /* Proxy 0 addressing */ +- reg = <0x00 0x4301c000 0x00 0x178>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0xffffffff>; +- }; +- +- mcu_ram: sram@41c00000 { +- compatible = "mmio-sram"; +- reg = <0x00 0x41c00000 0x00 0x100000>; +- ranges = <0x00 0x00 0x41c00000 0x100000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- wkup_uart0: serial@42300000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x42300000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 287 2>; +- clock-names = "fclk"; +- }; +- +- mcu_uart0: serial@40a00000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x40a00000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <96000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 149 2>; +- clock-names = "fclk"; +- }; +- +- wkup_gpio_intr: interrupt-controller@42200000 { +- compatible = "ti,sci-intr"; +- reg = <0x00 0x42200000 0x00 0x400>; +- ti,intr-trigger-type = <1>; +- interrupt-controller; +- interrupt-parent = <&gic500>; +- #interrupt-cells = <1>; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <137>; +- ti,interrupt-ranges = <16 960 16>; +- }; +- +- wkup_gpio0: gpio@42110000 { +- compatible = "ti,j721e-gpio", "ti,keystone-gpio"; +- reg = <0x00 0x42110000 0x00 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&wkup_gpio_intr>; +- interrupts = <103>, <104>, <105>, <106>, <107>, <108>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <85>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 113 0>; +- clock-names = "gpio"; +- }; +- +- wkup_gpio1: gpio@42100000 { +- compatible = "ti,j721e-gpio", "ti,keystone-gpio"; +- reg = <0x00 0x42100000 0x00 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&wkup_gpio_intr>; +- interrupts = <112>, <113>, <114>, <115>, <116>, <117>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <85>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 114 0>; +- clock-names = "gpio"; +- }; +- +- mcu_navss: bus@28380000 { +- compatible = "simple-mfd"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; +- dma-coherent; +- dma-ranges; +- ti,sci-dev-id = <232>; +- +- mcu_ringacc: ringacc@2b800000 { +- compatible = "ti,am654-navss-ringacc"; +- reg = <0x00 0x2b800000 0x00 0x400000>, +- <0x00 0x2b000000 0x00 0x400000>, +- <0x00 0x28590000 0x00 0x100>, +- <0x00 0x2a500000 0x00 0x40000>; +- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; +- ti,num-rings = <286>; +- ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <235>; +- msi-parent = <&main_udmass_inta>; +- }; +- +- mcu_udmap: dma-controller@285c0000 { +- compatible = "ti,j721e-navss-mcu-udmap"; +- reg = <0x00 0x285c0000 0x00 0x100>, +- <0x00 0x2a800000 0x00 0x40000>, +- <0x00 0x2aa00000 0x00 0x40000>; +- reg-names = "gcfg", "rchanrt", "tchanrt"; +- msi-parent = <&main_udmass_inta>; +- #dma-cells = <1>; +- +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <236>; +- ti,ringacc = <&mcu_ringacc>; +- +- ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ +- <0x0f>; /* TX_HCHAN */ +- ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ +- <0x0b>; /* RX_HCHAN */ +- ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ +- }; +- }; +- +- mcu_cpsw: ethernet@46000000 { +- compatible = "ti,j721e-cpsw-nuss"; +- #address-cells = <2>; +- #size-cells = <2>; +- reg = <0x00 0x46000000 0x00 0x200000>; +- reg-names = "cpsw_nuss"; +- ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; +- dma-coherent; +- clocks = <&k3_clks 18 21>; +- clock-names = "fck"; +- power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; +- +- dmas = <&mcu_udmap 0xf000>, +- <&mcu_udmap 0xf001>, +- <&mcu_udmap 0xf002>, +- <&mcu_udmap 0xf003>, +- <&mcu_udmap 0xf004>, +- <&mcu_udmap 0xf005>, +- <&mcu_udmap 0xf006>, +- <&mcu_udmap 0xf007>, +- <&mcu_udmap 0x7000>; +- dma-names = "tx0", "tx1", "tx2", "tx3", +- "tx4", "tx5", "tx6", "tx7", +- "rx"; +- +- ethernet-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpsw_port1: port@1 { +- reg = <1>; +- ti,mac-only; +- label = "port1"; +- ti,syscon-efuse = <&mcu_conf 0x200>; +- phys = <&phy_gmii_sel 1>; +- }; +- }; +- +- davinci_mdio: mdio@f00 { +- compatible = "ti,cpsw-mdio","ti,davinci_mdio"; +- reg = <0x00 0xf00 0x00 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&k3_clks 18 21>; +- clock-names = "fck"; +- bus_freq = <1000000>; +- }; +- +- cpts@3d000 { +- compatible = "ti,am65-cpts"; +- reg = <0x00 0x3d000 0x00 0x400>; +- clocks = <&k3_clks 18 2>; +- clock-names = "cpts"; +- interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "cpts"; +- ti,cpts-ext-ts-inputs = <4>; +- ti,cpts-periodic-outputs = <2>; +- }; +- }; +- +- mcu_i2c0: i2c@40b00000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x00 0x40b00000 0x00 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 194 1>; +- power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- mcu_i2c1: i2c@40b10000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x00 0x40b10000 0x00 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 195 1>; +- power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- wkup_i2c0: i2c@42120000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x00 0x42120000 0x00 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 197 1>; +- power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; +- }; +- +- fss: syscon@47000000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x00 0x47000000 0x00 0x100>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- hbmc_mux: hbmc-mux { +- compatible = "mmio-mux"; +- #mux-control-cells = <1>; +- mux-reg-masks = <0x4 0x2>; /* HBMC select */ +- }; +- +- hbmc: hyperbus@47034000 { +- compatible = "ti,am654-hbmc"; +- reg = <0x00 0x47034000 0x00 0x100>, +- <0x05 0x00000000 0x01 0x0000000>; +- power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 102 0>; +- assigned-clocks = <&k3_clks 102 5>; +- assigned-clock-rates = <333333333>; +- #address-cells = <2>; +- #size-cells = <1>; +- mux-controls = <&hbmc_mux 0>; +- }; +- +- ospi0: spi@47040000 { +- compatible = "ti,am654-ospi", "cdns,qspi-nor"; +- reg = <0x0 0x47040000 0x0 0x100>, +- <0x5 0x00000000 0x1 0x0000000>; +- interrupts = ; +- cdns,fifo-depth = <256>; +- cdns,fifo-width = <4>; +- cdns,trigger-address = <0x0>; +- clocks = <&k3_clks 103 0>; +- assigned-clocks = <&k3_clks 103 0>; +- assigned-clock-parents = <&k3_clks 103 2>; +- assigned-clock-rates = <166666666>; +- power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- tscadc0: tscadc@40200000 { +- compatible = "ti,am3359-tscadc"; +- reg = <0x00 0x40200000 0x00 0x1000>; +- interrupts = ; +- power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 0 1>; +- assigned-clocks = <&k3_clks 0 3>; +- assigned-clock-rates = <60000000>; +- clock-names = "adc_tsc_fck"; +- dmas = <&main_udmap 0x7400>, +- <&main_udmap 0x7401>; +- dma-names = "fifo0", "fifo1"; +- +- adc { +- #io-channel-cells = <1>; +- compatible = "ti,am3359-adc"; +- }; +- }; +- +- mcu_r5fss0: r5fss@41000000 { +- compatible = "ti,j7200-r5fss"; +- ti,cluster-mode = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x41000000 0x00 0x41000000 0x20000>, +- <0x41400000 0x00 0x41400000 0x20000>; +- power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; +- +- mcu_r5fss0_core0: r5f@41000000 { +- compatible = "ti,j7200-r5f"; +- reg = <0x41000000 0x00010000>, +- <0x41010000 0x00010000>; +- reg-names = "atcm", "btcm"; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <250>; +- ti,sci-proc-ids = <0x01 0xff>; +- resets = <&k3_reset 250 1>; +- firmware-name = "j7200-mcu-r5f0_0-fw"; +- ti,atcm-enable = <1>; +- ti,btcm-enable = <1>; +- ti,loczrama = <1>; +- }; +- +- mcu_r5fss0_core1: r5f@41400000 { +- compatible = "ti,j7200-r5f"; +- reg = <0x41400000 0x00008000>, +- <0x41410000 0x00008000>; +- reg-names = "atcm", "btcm"; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <251>; +- ti,sci-proc-ids = <0x02 0xff>; +- resets = <&k3_reset 251 1>; +- firmware-name = "j7200-mcu-r5f0_1-fw"; +- ti,atcm-enable = <1>; +- ti,btcm-enable = <1>; +- ti,loczrama = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-j7200-som-p0.dtsi b/scripts/dtc/include-prefixes/arm64/ti/k3-j7200-som-p0.dtsi +deleted file mode 100644 +index 34724440171a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-j7200-som-p0.dtsi ++++ /dev/null +@@ -1,273 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/dts-v1/; +- +-#include "k3-j7200.dtsi" +- +-/ { +- memory@80000000 { +- device_type = "memory"; +- /* 4G RAM */ +- reg = <0x00 0x80000000 0x00 0x80000000>, +- <0x08 0x80000000 0x00 0x80000000>; +- }; +- +- reserved_memory: reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- secure_ddr: optee@9e800000 { +- reg = <0x00 0x9e800000 0x00 0x01800000>; +- alignment = <0x1000>; +- no-map; +- }; +- +- mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa0000000 0x00 0x100000>; +- no-map; +- }; +- +- mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa0100000 0x00 0xf00000>; +- no-map; +- }; +- +- mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa1000000 0x00 0x100000>; +- no-map; +- }; +- +- mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa1100000 0x00 0xf00000>; +- no-map; +- }; +- +- main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa2000000 0x00 0x100000>; +- no-map; +- }; +- +- main_r5fss0_core0_memory_region: r5f-memory@a2100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa2100000 0x00 0xf00000>; +- no-map; +- }; +- +- main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa3000000 0x00 0x100000>; +- no-map; +- }; +- +- main_r5fss0_core1_memory_region: r5f-memory@a3100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa3100000 0x00 0xf00000>; +- no-map; +- }; +- +- rtos_ipc_memory_region: ipc-memories@a4000000 { +- reg = <0x00 0xa4000000 0x00 0x00800000>; +- alignment = <0x1000>; +- no-map; +- }; +- }; +-}; +- +-&wkup_pmx0 { +- mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { +- pinctrl-single,pins = < +- J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ +- J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ +- J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ +- J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ +- J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ +- J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ +- J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ +- J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ +- J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ +- J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ +- J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ +- J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ +- J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ +- >; +- }; +- +- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { +- pinctrl-single,pins = < +- J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ +- J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ +- J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ +- J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ +- J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ +- J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ +- J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ +- J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ +- J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ +- J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ +- J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ +- >; +- }; +-}; +- +-&main_pmx0 { +- main_i2c0_pins_default: main-i2c0-pins-default { +- pinctrl-single,pins = < +- J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ +- J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ +- >; +- }; +-}; +- +-&hbmc { +- /* OSPI and HBMC are muxed inside FSS, Bootloader will enable +- * appropriate node based on board detection +- */ +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; +- ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ +- <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ +- +- flash@0,0 { +- compatible = "cypress,hyperflash", "cfi-flash"; +- reg = <0x00 0x00 0x4000000>; +- }; +-}; +- +-&mailbox0_cluster0 { +- interrupts = <436>; +- +- mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { +- ti,mbox-rx = <0 0 0>; +- ti,mbox-tx = <1 0 0>; +- }; +- +- mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { +- ti,mbox-rx = <2 0 0>; +- ti,mbox-tx = <3 0 0>; +- }; +-}; +- +-&mailbox0_cluster1 { +- interrupts = <432>; +- +- mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { +- ti,mbox-rx = <0 0 0>; +- ti,mbox-tx = <1 0 0>; +- }; +- +- mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { +- ti,mbox-rx = <2 0 0>; +- ti,mbox-tx = <3 0 0>; +- }; +-}; +- +-&mailbox0_cluster2 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster3 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster4 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster5 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster6 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster7 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster8 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster9 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster10 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster11 { +- status = "disabled"; +-}; +- +-&mcu_r5fss0_core0 { +- mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; +- memory-region = <&mcu_r5fss0_core0_dma_memory_region>, +- <&mcu_r5fss0_core0_memory_region>; +-}; +- +-&mcu_r5fss0_core1 { +- mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; +- memory-region = <&mcu_r5fss0_core1_dma_memory_region>, +- <&mcu_r5fss0_core1_memory_region>; +-}; +- +-&main_r5fss0_core0 { +- mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; +- memory-region = <&main_r5fss0_core0_dma_memory_region>, +- <&main_r5fss0_core0_memory_region>; +-}; +- +-&main_r5fss0_core1 { +- mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; +- memory-region = <&main_r5fss0_core1_dma_memory_region>, +- <&main_r5fss0_core1_memory_region>; +-}; +- +-&main_i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_i2c0_pins_default>; +- clock-frequency = <400000>; +- +- exp_som: gpio@21 { +- compatible = "ti,tca6408"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", +- "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", +- "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL", +- "GPIO_LIN_EN", "CAN_STB"; +- }; +-}; +- +-&ospi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; +- +- flash@0{ +- compatible = "jedec,spi-nor"; +- reg = <0x0>; +- spi-tx-bus-width = <8>; +- spi-rx-bus-width = <8>; +- spi-max-frequency = <25000000>; +- cdns,tshsl-ns = <60>; +- cdns,tsd2d-ns = <60>; +- cdns,tchsh-ns = <60>; +- cdns,tslch-ns = <60>; +- cdns,read-delay = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-j7200.dtsi b/scripts/dtc/include-prefixes/arm64/ti/k3-j7200.dtsi +deleted file mode 100644 +index 7586b5aea446..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-j7200.dtsi ++++ /dev/null +@@ -1,172 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for J7200 SoC Family +- * +- * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- model = "Texas Instruments K3 J7200 SoC"; +- compatible = "ti,j7200"; +- interrupt-parent = <&gic500>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- serial0 = &wkup_uart0; +- serial1 = &mcu_uart0; +- serial2 = &main_uart0; +- serial3 = &main_uart1; +- serial4 = &main_uart2; +- serial5 = &main_uart3; +- serial6 = &main_uart4; +- serial7 = &main_uart5; +- serial8 = &main_uart6; +- serial9 = &main_uart7; +- serial10 = &main_uart8; +- serial11 = &main_uart9; +- }; +- +- chosen { }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu-map { +- cluster0: cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- +- core1 { +- cpu = <&cpu1>; +- }; +- }; +- +- }; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a72"; +- reg = <0x000>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&L2_0>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a72"; +- reg = <0x001>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0xc000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&L2_0>; +- }; +- }; +- +- L2_0: l2-cache0 { +- compatible = "cache"; +- cache-level = <2>; +- cache-size = <0x100000>; +- cache-line-size = <64>; +- cache-sets = <1024>; +- next-level-cache = <&msmc_l3>; +- }; +- +- msmc_l3: l3-cache0 { +- compatible = "cache"; +- cache-level = <3>; +- }; +- +- firmware { +- optee { +- compatible = "linaro,optee-tz"; +- method = "smc"; +- }; +- +- psci: psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- }; +- +- a72_timer0: timer-cl0-cpu0 { +- compatible = "arm,armv8-timer"; +- interrupts = , /* cntpsirq */ +- , /* cntpnsirq */ +- , /* cntvirq */ +- ; /* cnthpirq */ +- }; +- +- pmu: pmu { +- compatible = "arm,cortex-a72-pmu"; +- interrupts = ; +- }; +- +- cbass_main: bus@100000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ +- <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ +- <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ +- <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ +- <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ +- <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ +- <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ +- <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ +- +- /* MCUSS_WKUP Range */ +- <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, +- <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, +- <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, +- <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, +- <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, +- <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, +- <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, +- <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, +- <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, +- <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, +- <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, +- <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, +- <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; +- +- cbass_mcu_wakeup: bus@28380000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ +- <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ +- <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ +- <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ +- <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ +- <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ +- <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ +- <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ +- <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ +- <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ +- <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ +- <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ +- <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */ +- }; +- }; +-}; +- +-/* Now include the peripherals for each bus segments */ +-#include "k3-j7200-main.dtsi" +-#include "k3-j7200-mcu-wakeup.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-j721e-common-proc-board.dts b/scripts/dtc/include-prefixes/arm64/ti/k3-j721e-common-proc-board.dts +deleted file mode 100644 +index 8bd02d9e28ad..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-j721e-common-proc-board.dts ++++ /dev/null +@@ -1,772 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/dts-v1/; +- +-#include "k3-j721e-som-p0.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- chosen { +- stdout-path = "serial2:115200n8"; +- bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; +- }; +- +- gpio_keys: gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- pinctrl-names = "default"; +- pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>; +- +- sw10: sw10 { +- label = "GPIO Key USER1"; +- linux,code = ; +- gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>; +- }; +- +- sw11: sw11 { +- label = "GPIO Key USER2"; +- linux,code = ; +- gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- evm_12v0: fixedregulator-evm12v0 { +- /* main supply */ +- compatible = "regulator-fixed"; +- regulator-name = "evm_12v0"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vsys_3v3: fixedregulator-vsys3v3 { +- /* Output of LMS140 */ +- compatible = "regulator-fixed"; +- regulator-name = "vsys_3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&evm_12v0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vsys_5v0: fixedregulator-vsys5v0 { +- /* Output of LM5140 */ +- compatible = "regulator-fixed"; +- regulator-name = "vsys_5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&evm_12v0>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vdd_mmc1: fixedregulator-sd { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_mmc1"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- enable-active-high; +- vin-supply = <&vsys_3v3>; +- gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; +- }; +- +- vdd_sd_dv_alt: gpio-regulator-TLV71033 { +- compatible = "regulator-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; +- regulator-name = "tlv71033"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- vin-supply = <&vsys_5v0>; +- gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; +- states = <1800000 0x0>, +- <3300000 0x1>; +- }; +- +- sound0: sound@0 { +- compatible = "ti,j721e-cpb-audio"; +- model = "j721e-cpb"; +- +- ti,cpb-mcasp = <&mcasp10>; +- ti,cpb-codec = <&pcm3168a_1>; +- +- clocks = <&k3_clks 184 1>, +- <&k3_clks 184 2>, <&k3_clks 184 4>, +- <&k3_clks 157 371>, +- <&k3_clks 157 400>, <&k3_clks 157 401>; +- clock-names = "cpb-mcasp-auxclk", +- "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100", +- "cpb-codec-scki", +- "cpb-codec-scki-48000", "cpb-codec-scki-44100"; +- }; +-}; +- +-&main_pmx0 { +- sw10_button_pins_default: sw10-button-pins-default { +- pinctrl-single,pins = < +- J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ +- >; +- }; +- +- main_mmc1_pins_default: main-mmc1-pins-default { +- pinctrl-single,pins = < +- J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ +- J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ +- J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ +- J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ +- J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ +- J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ +- J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ +- J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ +- J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ +- >; +- }; +- +- vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { +- pinctrl-single,pins = < +- J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ +- >; +- }; +- +- main_usbss0_pins_default: main-usbss0-pins-default { +- pinctrl-single,pins = < +- J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ +- J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ +- >; +- }; +- +- main_usbss1_pins_default: main-usbss1-pins-default { +- pinctrl-single,pins = < +- J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ +- >; +- }; +- +- main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default { +- pinctrl-single,pins = < +- J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ +- >; +- }; +- +- main_i2c0_pins_default: main-i2c0-pins-default { +- pinctrl-single,pins = < +- J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ +- J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ +- >; +- }; +- +- main_i2c1_pins_default: main-i2c1-pins-default { +- pinctrl-single,pins = < +- J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ +- J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ +- >; +- }; +- +- main_i2c3_pins_default: main-i2c3-pins-default { +- pinctrl-single,pins = < +- J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ +- J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ +- >; +- }; +- +- main_i2c6_pins_default: main-i2c6-pins-default { +- pinctrl-single,pins = < +- J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ +- J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ +- >; +- }; +- +- mcasp10_pins_default: mcasp10-pins-default { +- pinctrl-single,pins = < +- J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ +- J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ +- J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */ +- J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */ +- J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */ +- J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */ +- J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */ +- J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */ +- J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */ +- >; +- }; +- +- audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default { +- pinctrl-single,pins = < +- J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ +- >; +- }; +-}; +- +-&wkup_pmx0 { +- sw11_button_pins_default: sw11-button-pins-default { +- pinctrl-single,pins = < +- J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ +- >; +- }; +- +- mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { +- pinctrl-single,pins = < +- J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ +- J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ +- J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */ +- J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */ +- J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */ +- J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */ +- J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ +- J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ +- >; +- }; +- +- mcu_cpsw_pins_default: mcu-cpsw-pins-default { +- pinctrl-single,pins = < +- J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ +- J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ +- J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ +- J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ +- J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ +- J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ +- J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ +- J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ +- J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ +- J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ +- J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ +- J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ +- >; +- }; +- +- mcu_mdio_pins_default: mcu-mdio1-pins-default { +- pinctrl-single,pins = < +- J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ +- J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ +- >; +- }; +-}; +- +-&wkup_uart0 { +- /* Wakeup UART is used by System firmware */ +- status = "reserved"; +-}; +- +-&main_uart0 { +- power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; +-}; +- +-&main_uart3 { +- /* UART not brought out */ +- status = "disabled"; +-}; +- +-&main_uart5 { +- /* UART not brought out */ +- status = "disabled"; +-}; +- +-&main_uart6 { +- /* UART not brought out */ +- status = "disabled"; +-}; +- +-&main_uart7 { +- /* UART not brought out */ +- status = "disabled"; +-}; +- +-&main_uart8 { +- /* UART not brought out */ +- status = "disabled"; +-}; +- +-&main_uart9 { +- /* UART not brought out */ +- status = "disabled"; +-}; +- +-&main_gpio2 { +- status = "disabled"; +-}; +- +-&main_gpio3 { +- status = "disabled"; +-}; +- +-&main_gpio4 { +- status = "disabled"; +-}; +- +-&main_gpio5 { +- status = "disabled"; +-}; +- +-&main_gpio6 { +- status = "disabled"; +-}; +- +-&main_gpio7 { +- status = "disabled"; +-}; +- +-&wkup_gpio1 { +- status = "disabled"; +-}; +- +-&main_sdhci0 { +- /* eMMC */ +- non-removable; +- ti,driver-strength-ohm = <50>; +- disable-wp; +-}; +- +-&main_sdhci1 { +- /* SD/MMC */ +- vmmc-supply = <&vdd_mmc1>; +- vqmmc-supply = <&vdd_sd_dv_alt>; +- pinctrl-names = "default"; +- pinctrl-0 = <&main_mmc1_pins_default>; +- ti,driver-strength-ohm = <50>; +- disable-wp; +-}; +- +-&main_sdhci2 { +- /* Unused */ +- status = "disabled"; +-}; +- +-&usb_serdes_mux { +- idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ +-}; +- +-&serdes_ln_ctrl { +- idle-states = , , +- , , +- , , +- , , +- , , +- , ; +-}; +- +-&serdes_wiz3 { +- typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; +- typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ +-}; +- +-&serdes3 { +- serdes3_usb_link: phy@0 { +- reg = <0>; +- cdns,num-lanes = <2>; +- #phy-cells = <0>; +- cdns,phy-type = ; +- resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; +- }; +-}; +- +-&usbss0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_usbss0_pins_default>; +- ti,vbus-divider; +-}; +- +-&usb0 { +- dr_mode = "otg"; +- maximum-speed = "super-speed"; +- phys = <&serdes3_usb_link>; +- phy-names = "cdns3,usb3-phy"; +-}; +- +-&usbss1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_usbss1_pins_default>; +- ti,usb2-only; +-}; +- +-&usb1 { +- dr_mode = "host"; +- maximum-speed = "high-speed"; +-}; +- +-&ospi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; +- +- flash@0{ +- compatible = "jedec,spi-nor"; +- reg = <0x0>; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <4>; +- spi-max-frequency = <40000000>; +- cdns,tshsl-ns = <60>; +- cdns,tsd2d-ns = <60>; +- cdns,tchsh-ns = <60>; +- cdns,tslch-ns = <60>; +- cdns,read-delay = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&tscadc0 { +- adc { +- ti,adc-channels = <0 1 2 3 4 5 6 7>; +- }; +-}; +- +-&tscadc1 { +- adc { +- ti,adc-channels = <0 1 2 3 4 5 6 7>; +- }; +-}; +- +-&main_i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_i2c0_pins_default>; +- clock-frequency = <400000>; +- +- exp1: gpio@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- exp2: gpio@22 { +- compatible = "ti,tca6424"; +- reg = <0x22>; +- gpio-controller; +- #gpio-cells = <2>; +- +- p09-hog { +- /* P11 - MCASP/TRACE_MUX_S0 */ +- gpio-hog; +- gpios = <9 GPIO_ACTIVE_HIGH>; +- output-low; +- line-name = "MCASP/TRACE_MUX_S0"; +- }; +- +- p10-hog { +- /* P12 - MCASP/TRACE_MUX_S1 */ +- gpio-hog; +- gpios = <10 GPIO_ACTIVE_HIGH>; +- output-high; +- line-name = "MCASP/TRACE_MUX_S1"; +- }; +- }; +-}; +- +-&main_i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_i2c1_pins_default>; +- clock-frequency = <400000>; +- +- exp4: gpio@20 { +- compatible = "ti,tca6408"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- pinctrl-names = "default"; +- pinctrl-0 = <&main_i2c1_exp4_pins_default>; +- interrupt-parent = <&main_gpio1>; +- interrupts = <11 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +-}; +- +-&k3_clks { +- /* Confiure AUDIO_EXT_REFCLK2 pin as output */ +- pinctrl-names = "default"; +- pinctrl-0 = <&audi_ext_refclk2_pins_default>; +-}; +- +-&main_i2c3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_i2c3_pins_default>; +- clock-frequency = <400000>; +- +- exp3: gpio@20 { +- compatible = "ti,tca6408"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- pcm3168a_1: audio-codec@44 { +- compatible = "ti,pcm3168a"; +- reg = <0x44>; +- +- #sound-dai-cells = <1>; +- +- reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; +- +- /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */ +- clocks = <&k3_clks 157 371>; +- clock-names = "scki"; +- +- /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */ +- assigned-clocks = <&k3_clks 157 371>; +- assigned-clock-parents = <&k3_clks 157 400>; +- assigned-clock-rates = <24576000>; /* for 48KHz */ +- +- VDD1-supply = <&vsys_3v3>; +- VDD2-supply = <&vsys_3v3>; +- VCCAD1-supply = <&vsys_5v0>; +- VCCAD2-supply = <&vsys_5v0>; +- VCCDA1-supply = <&vsys_5v0>; +- VCCDA2-supply = <&vsys_5v0>; +- }; +-}; +- +-&main_i2c6 { +- pinctrl-names = "default"; +- pinctrl-0 = <&main_i2c6_pins_default>; +- clock-frequency = <400000>; +- +- exp5: gpio@20 { +- compatible = "ti,tca6408"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- +-&mcu_cpsw { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +-}; +- +-&davinci_mdio { +- phy0: ethernet-phy@0 { +- reg = <0>; +- ti,rx-internal-delay = ; +- ti,fifo-depth = ; +- }; +-}; +- +-&cpsw_port1 { +- phy-mode = "rgmii-rxid"; +- phy-handle = <&phy0>; +-}; +- +-&dss { +- /* +- * These clock assignments are chosen to enable the following outputs: +- * +- * VP0 - DisplayPort SST +- * VP1 - DPI0 +- * VP2 - DSI +- * VP3 - DPI1 +- */ +- +- assigned-clocks = <&k3_clks 152 1>, +- <&k3_clks 152 4>, +- <&k3_clks 152 9>, +- <&k3_clks 152 13>; +- assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ +- <&k3_clks 152 6>, /* PLL19_HSDIV0 */ +- <&k3_clks 152 11>, /* PLL18_HSDIV0 */ +- <&k3_clks 152 18>; /* PLL23_HSDIV0 */ +-}; +- +-&mcasp0 { +- status = "disabled"; +-}; +- +-&mcasp1 { +- status = "disabled"; +-}; +- +-&mcasp2 { +- status = "disabled"; +-}; +- +-&mcasp3 { +- status = "disabled"; +-}; +- +-&mcasp4 { +- status = "disabled"; +-}; +- +-&mcasp5 { +- status = "disabled"; +-}; +- +-&mcasp6 { +- status = "disabled"; +-}; +- +-&mcasp7 { +- status = "disabled"; +-}; +- +-&mcasp8 { +- status = "disabled"; +-}; +- +-&mcasp9 { +- status = "disabled"; +-}; +- +-&mcasp10 { +- #sound-dai-cells = <0>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&mcasp10_pins_default>; +- +- op-mode = <0>; /* MCASP_IIS_MODE */ +- tdm-slots = <2>; +- auxclk-fs-ratio = <256>; +- +- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ +- 1 1 1 1 +- 2 2 2 0 +- >; +- tx-num-evt = <0>; +- rx-num-evt = <0>; +-}; +- +-&mcasp11 { +- status = "disabled"; +-}; +- +-&cmn_refclk1 { +- clock-frequency = <100000000>; +-}; +- +-&wiz0_pll1_refclk { +- assigned-clocks = <&wiz0_pll1_refclk>; +- assigned-clock-parents = <&cmn_refclk1>; +-}; +- +-&wiz0_refclk_dig { +- assigned-clocks = <&wiz0_refclk_dig>; +- assigned-clock-parents = <&cmn_refclk1>; +-}; +- +-&wiz1_pll1_refclk { +- assigned-clocks = <&wiz1_pll1_refclk>; +- assigned-clock-parents = <&cmn_refclk1>; +-}; +- +-&wiz1_refclk_dig { +- assigned-clocks = <&wiz1_refclk_dig>; +- assigned-clock-parents = <&cmn_refclk1>; +-}; +- +-&wiz2_pll1_refclk { +- assigned-clocks = <&wiz2_pll1_refclk>; +- assigned-clock-parents = <&cmn_refclk1>; +-}; +- +-&wiz2_refclk_dig { +- assigned-clocks = <&wiz2_refclk_dig>; +- assigned-clock-parents = <&cmn_refclk1>; +-}; +- +-&serdes0 { +- assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>; +- assigned-clock-parents = <&wiz0_pll1_refclk>; +- +- serdes0_pcie_link: phy@0 { +- reg = <0>; +- cdns,num-lanes = <1>; +- #phy-cells = <0>; +- cdns,phy-type = ; +- resets = <&serdes_wiz0 1>; +- }; +-}; +- +-&serdes1 { +- assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>; +- assigned-clock-parents = <&wiz1_pll1_refclk>; +- +- serdes1_pcie_link: phy@0 { +- reg = <0>; +- cdns,num-lanes = <2>; +- #phy-cells = <0>; +- cdns,phy-type = ; +- resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; +- }; +-}; +- +-&serdes2 { +- assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>; +- assigned-clock-parents = <&wiz2_pll1_refclk>; +- +- serdes2_pcie_link: phy@0 { +- reg = <0>; +- cdns,num-lanes = <2>; +- #phy-cells = <0>; +- cdns,phy-type = ; +- resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>; +- }; +-}; +- +-&pcie0_rc { +- reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; +- phys = <&serdes0_pcie_link>; +- phy-names = "pcie-phy"; +- num-lanes = <1>; +-}; +- +-&pcie1_rc { +- reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; +- phys = <&serdes1_pcie_link>; +- phy-names = "pcie-phy"; +- num-lanes = <2>; +-}; +- +-&pcie2_rc { +- reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; +- phys = <&serdes2_pcie_link>; +- phy-names = "pcie-phy"; +- num-lanes = <2>; +-}; +- +-&pcie0_ep { +- phys = <&serdes0_pcie_link>; +- phy-names = "pcie-phy"; +- num-lanes = <1>; +- status = "disabled"; +-}; +- +-&pcie1_ep { +- phys = <&serdes1_pcie_link>; +- phy-names = "pcie-phy"; +- num-lanes = <2>; +- status = "disabled"; +-}; +- +-&pcie2_ep { +- phys = <&serdes2_pcie_link>; +- phy-names = "pcie-phy"; +- num-lanes = <2>; +- status = "disabled"; +-}; +- +-&pcie3_rc { +- status = "disabled"; +-}; +- +-&pcie3_ep { +- status = "disabled"; +-}; +- +-&dss { +- status = "disabled"; +-}; +- +-&icssg0_mdio { +- status = "disabled"; +-}; +- +-&icssg1_mdio { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-j721e-main.dtsi b/scripts/dtc/include-prefixes/arm64/ti/k3-j721e-main.dtsi +deleted file mode 100644 +index e85c89eebfa3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-j721e-main.dtsi ++++ /dev/null +@@ -1,1943 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for J721E SoC Family Main Domain peripherals +- * +- * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-#include +-#include +-#include +- +-/ { +- cmn_refclk: clock-cmnrefclk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +- +- cmn_refclk1: clock-cmnrefclk1 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <0>; +- }; +-}; +- +-&cbass_main { +- msmc_ram: sram@70000000 { +- compatible = "mmio-sram"; +- reg = <0x0 0x70000000 0x0 0x800000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x70000000 0x800000>; +- +- atf-sram@0 { +- reg = <0x0 0x20000>; +- }; +- }; +- +- scm_conf: scm-conf@100000 { +- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; +- reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x00100000 0x1c000>; +- +- serdes_ln_ctrl: mux-controller@4080 { +- compatible = "mmio-mux"; +- reg = <0x00004080 0x50>; +- #mux-control-cells = <1>; +- mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ +- <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ +- <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ +- <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ +- <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; +- /* SERDES4 lane0/1/2/3 select */ +- idle-states = , , +- , , +- , , +- , , +- , , +- , ; +- }; +- +- usb_serdes_mux: mux-controller@4000 { +- compatible = "mmio-mux"; +- #mux-control-cells = <1>; +- mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ +- <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ +- }; +- }; +- +- gic500: interrupt-controller@1800000 { +- compatible = "arm,gic-v3"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ +- <0x00 0x01900000 0x00 0x100000>; /* GICR */ +- +- /* vcpumntirq: virtual CPU interface maintenance interrupt */ +- interrupts = ; +- +- gic_its: msi-controller@1820000 { +- compatible = "arm,gic-v3-its"; +- reg = <0x00 0x01820000 0x00 0x10000>; +- socionext,synquacer-pre-its = <0x1000000 0x400000>; +- msi-controller; +- #msi-cells = <1>; +- }; +- }; +- +- main_gpio_intr: interrupt-controller@a00000 { +- compatible = "ti,sci-intr"; +- reg = <0x00 0x00a00000 0x00 0x800>; +- ti,intr-trigger-type = <1>; +- interrupt-controller; +- interrupt-parent = <&gic500>; +- #interrupt-cells = <1>; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <131>; +- ti,interrupt-ranges = <8 392 56>; +- }; +- +- main_navss: bus@30000000 { +- compatible = "simple-mfd"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; +- dma-coherent; +- dma-ranges; +- +- ti,sci-dev-id = <199>; +- +- main_navss_intr: interrupt-controller@310e0000 { +- compatible = "ti,sci-intr"; +- reg = <0x0 0x310e0000 0x0 0x4000>; +- ti,intr-trigger-type = <4>; +- interrupt-controller; +- interrupt-parent = <&gic500>; +- #interrupt-cells = <1>; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <213>; +- ti,interrupt-ranges = <0 64 64>, +- <64 448 64>, +- <128 672 64>; +- }; +- +- main_udmass_inta: interrupt-controller@33d00000 { +- compatible = "ti,sci-inta"; +- reg = <0x0 0x33d00000 0x0 0x100000>; +- interrupt-controller; +- interrupt-parent = <&main_navss_intr>; +- msi-controller; +- #interrupt-cells = <0>; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <209>; +- ti,interrupt-ranges = <0 0 256>; +- }; +- +- secure_proxy_main: mailbox@32c00000 { +- compatible = "ti,am654-secure-proxy"; +- #mbox-cells = <1>; +- reg-names = "target_data", "rt", "scfg"; +- reg = <0x00 0x32c00000 0x00 0x100000>, +- <0x00 0x32400000 0x00 0x100000>, +- <0x00 0x32800000 0x00 0x100000>; +- interrupt-names = "rx_011"; +- interrupts = ; +- }; +- +- smmu0: iommu@36600000 { +- compatible = "arm,smmu-v3"; +- reg = <0x0 0x36600000 0x0 0x100000>; +- interrupt-parent = <&gic500>; +- interrupts = , +- ; +- interrupt-names = "eventq", "gerror"; +- #iommu-cells = <1>; +- }; +- +- hwspinlock: spinlock@30e00000 { +- compatible = "ti,am654-hwspinlock"; +- reg = <0x00 0x30e00000 0x00 0x1000>; +- #hwlock-cells = <1>; +- }; +- +- mailbox0_cluster0: mailbox@31f80000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f80000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster1: mailbox@31f81000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f81000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster2: mailbox@31f82000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f82000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster3: mailbox@31f83000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f83000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster4: mailbox@31f84000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f84000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster5: mailbox@31f85000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f85000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster6: mailbox@31f86000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f86000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster7: mailbox@31f87000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f87000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster8: mailbox@31f88000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f88000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster9: mailbox@31f89000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f89000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster10: mailbox@31f8a000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f8a000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- mailbox0_cluster11: mailbox@31f8b000 { +- compatible = "ti,am654-mailbox"; +- reg = <0x00 0x31f8b000 0x00 0x200>; +- #mbox-cells = <1>; +- ti,mbox-num-users = <4>; +- ti,mbox-num-fifos = <16>; +- interrupt-parent = <&main_navss_intr>; +- }; +- +- main_ringacc: ringacc@3c000000 { +- compatible = "ti,am654-navss-ringacc"; +- reg = <0x0 0x3c000000 0x0 0x400000>, +- <0x0 0x38000000 0x0 0x400000>, +- <0x0 0x31120000 0x0 0x100>, +- <0x0 0x33000000 0x0 0x40000>; +- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; +- ti,num-rings = <1024>; +- ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <211>; +- msi-parent = <&main_udmass_inta>; +- }; +- +- main_udmap: dma-controller@31150000 { +- compatible = "ti,j721e-navss-main-udmap"; +- reg = <0x0 0x31150000 0x0 0x100>, +- <0x0 0x34000000 0x0 0x100000>, +- <0x0 0x35000000 0x0 0x100000>; +- reg-names = "gcfg", "rchanrt", "tchanrt"; +- msi-parent = <&main_udmass_inta>; +- #dma-cells = <1>; +- +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <212>; +- ti,ringacc = <&main_ringacc>; +- +- ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ +- <0x0f>, /* TX_HCHAN */ +- <0x10>; /* TX_UHCHAN */ +- ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ +- <0x0b>, /* RX_HCHAN */ +- <0x0c>; /* RX_UHCHAN */ +- ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ +- }; +- +- cpts@310d0000 { +- compatible = "ti,j721e-cpts"; +- reg = <0x0 0x310d0000 0x0 0x400>; +- reg-names = "cpts"; +- clocks = <&k3_clks 201 1>; +- clock-names = "cpts"; +- interrupts-extended = <&main_navss_intr 391>; +- interrupt-names = "cpts"; +- ti,cpts-periodic-outputs = <6>; +- ti,cpts-ext-ts-inputs = <8>; +- }; +- }; +- +- main_crypto: crypto@4e00000 { +- compatible = "ti,j721e-sa2ul"; +- reg = <0x0 0x4e00000 0x0 0x1200>; +- power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; +- +- dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, +- <&main_udmap 0x4001>; +- dma-names = "tx", "rx1", "rx2"; +- dma-coherent; +- +- rng: rng@4e10000 { +- compatible = "inside-secure,safexcel-eip76"; +- reg = <0x0 0x4e10000 0x0 0x7d>; +- interrupts = ; +- clocks = <&k3_clks 264 1>; +- }; +- }; +- +- main_pmx0: pinctrl@11c000 { +- compatible = "pinctrl-single"; +- /* Proxy 0 addressing */ +- reg = <0x0 0x11c000 0x0 0x2b4>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0xffffffff>; +- }; +- +- serdes_wiz0: wiz@5000000 { +- compatible = "ti,j721e-wiz-16g"; +- #address-cells = <1>; +- #size-cells = <1>; +- power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; +- clock-names = "fck", "core_ref_clk", "ext_ref_clk"; +- assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; +- assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; +- num-lanes = <2>; +- #reset-cells = <1>; +- ranges = <0x5000000 0x0 0x5000000 0x10000>; +- +- wiz0_pll0_refclk: pll0-refclk { +- clocks = <&k3_clks 292 11>, <&cmn_refclk>; +- #clock-cells = <0>; +- assigned-clocks = <&wiz0_pll0_refclk>; +- assigned-clock-parents = <&k3_clks 292 11>; +- }; +- +- wiz0_pll1_refclk: pll1-refclk { +- clocks = <&k3_clks 292 0>, <&cmn_refclk1>; +- #clock-cells = <0>; +- assigned-clocks = <&wiz0_pll1_refclk>; +- assigned-clock-parents = <&k3_clks 292 0>; +- }; +- +- wiz0_refclk_dig: refclk-dig { +- clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; +- #clock-cells = <0>; +- assigned-clocks = <&wiz0_refclk_dig>; +- assigned-clock-parents = <&k3_clks 292 11>; +- }; +- +- wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { +- clocks = <&wiz0_refclk_dig>; +- #clock-cells = <0>; +- }; +- +- wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { +- clocks = <&wiz0_pll1_refclk>; +- #clock-cells = <0>; +- }; +- +- serdes0: serdes@5000000 { +- compatible = "ti,sierra-phy-t0"; +- reg-names = "serdes"; +- reg = <0x5000000 0x10000>; +- #address-cells = <1>; +- #size-cells = <0>; +- #clock-cells = <1>; +- resets = <&serdes_wiz0 0>; +- reset-names = "sierra_reset"; +- clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, +- <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; +- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", +- "pll0_refclk", "pll1_refclk"; +- }; +- }; +- +- serdes_wiz1: wiz@5010000 { +- compatible = "ti,j721e-wiz-16g"; +- #address-cells = <1>; +- #size-cells = <1>; +- power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; +- clock-names = "fck", "core_ref_clk", "ext_ref_clk"; +- assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; +- assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; +- num-lanes = <2>; +- #reset-cells = <1>; +- ranges = <0x5010000 0x0 0x5010000 0x10000>; +- +- wiz1_pll0_refclk: pll0-refclk { +- clocks = <&k3_clks 293 13>, <&cmn_refclk>; +- #clock-cells = <0>; +- assigned-clocks = <&wiz1_pll0_refclk>; +- assigned-clock-parents = <&k3_clks 293 13>; +- }; +- +- wiz1_pll1_refclk: pll1-refclk { +- clocks = <&k3_clks 293 0>, <&cmn_refclk1>; +- #clock-cells = <0>; +- assigned-clocks = <&wiz1_pll1_refclk>; +- assigned-clock-parents = <&k3_clks 293 0>; +- }; +- +- wiz1_refclk_dig: refclk-dig { +- clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; +- #clock-cells = <0>; +- assigned-clocks = <&wiz1_refclk_dig>; +- assigned-clock-parents = <&k3_clks 293 13>; +- }; +- +- wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ +- clocks = <&wiz1_refclk_dig>; +- #clock-cells = <0>; +- }; +- +- wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { +- clocks = <&wiz1_pll1_refclk>; +- #clock-cells = <0>; +- }; +- +- serdes1: serdes@5010000 { +- compatible = "ti,sierra-phy-t0"; +- reg-names = "serdes"; +- reg = <0x5010000 0x10000>; +- #address-cells = <1>; +- #size-cells = <0>; +- #clock-cells = <1>; +- resets = <&serdes_wiz1 0>; +- reset-names = "sierra_reset"; +- clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, +- <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; +- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", +- "pll0_refclk", "pll1_refclk"; +- }; +- }; +- +- serdes_wiz2: wiz@5020000 { +- compatible = "ti,j721e-wiz-16g"; +- #address-cells = <1>; +- #size-cells = <1>; +- power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; +- clock-names = "fck", "core_ref_clk", "ext_ref_clk"; +- assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; +- assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; +- num-lanes = <2>; +- #reset-cells = <1>; +- ranges = <0x5020000 0x0 0x5020000 0x10000>; +- +- wiz2_pll0_refclk: pll0-refclk { +- clocks = <&k3_clks 294 11>, <&cmn_refclk>; +- #clock-cells = <0>; +- assigned-clocks = <&wiz2_pll0_refclk>; +- assigned-clock-parents = <&k3_clks 294 11>; +- }; +- +- wiz2_pll1_refclk: pll1-refclk { +- clocks = <&k3_clks 294 0>, <&cmn_refclk1>; +- #clock-cells = <0>; +- assigned-clocks = <&wiz2_pll1_refclk>; +- assigned-clock-parents = <&k3_clks 294 0>; +- }; +- +- wiz2_refclk_dig: refclk-dig { +- clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; +- #clock-cells = <0>; +- assigned-clocks = <&wiz2_refclk_dig>; +- assigned-clock-parents = <&k3_clks 294 11>; +- }; +- +- wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { +- clocks = <&wiz2_refclk_dig>; +- #clock-cells = <0>; +- }; +- +- wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { +- clocks = <&wiz2_pll1_refclk>; +- #clock-cells = <0>; +- }; +- +- serdes2: serdes@5020000 { +- compatible = "ti,sierra-phy-t0"; +- reg-names = "serdes"; +- reg = <0x5020000 0x10000>; +- #address-cells = <1>; +- #size-cells = <0>; +- #clock-cells = <1>; +- resets = <&serdes_wiz2 0>; +- reset-names = "sierra_reset"; +- clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, +- <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; +- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", +- "pll0_refclk", "pll1_refclk"; +- }; +- }; +- +- serdes_wiz3: wiz@5030000 { +- compatible = "ti,j721e-wiz-16g"; +- #address-cells = <1>; +- #size-cells = <1>; +- power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; +- clock-names = "fck", "core_ref_clk", "ext_ref_clk"; +- assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; +- assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; +- num-lanes = <2>; +- #reset-cells = <1>; +- ranges = <0x5030000 0x0 0x5030000 0x10000>; +- +- wiz3_pll0_refclk: pll0-refclk { +- clocks = <&k3_clks 295 9>, <&cmn_refclk>; +- #clock-cells = <0>; +- assigned-clocks = <&wiz3_pll0_refclk>; +- assigned-clock-parents = <&k3_clks 295 9>; +- }; +- +- wiz3_pll1_refclk: pll1-refclk { +- clocks = <&k3_clks 295 0>, <&cmn_refclk1>; +- #clock-cells = <0>; +- assigned-clocks = <&wiz3_pll1_refclk>; +- assigned-clock-parents = <&k3_clks 295 0>; +- }; +- +- wiz3_refclk_dig: refclk-dig { +- clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; +- #clock-cells = <0>; +- assigned-clocks = <&wiz3_refclk_dig>; +- assigned-clock-parents = <&k3_clks 295 9>; +- }; +- +- wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { +- clocks = <&wiz3_refclk_dig>; +- #clock-cells = <0>; +- }; +- +- wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { +- clocks = <&wiz3_pll1_refclk>; +- #clock-cells = <0>; +- }; +- +- serdes3: serdes@5030000 { +- compatible = "ti,sierra-phy-t0"; +- reg-names = "serdes"; +- reg = <0x5030000 0x10000>; +- #address-cells = <1>; +- #size-cells = <0>; +- #clock-cells = <1>; +- resets = <&serdes_wiz3 0>; +- reset-names = "sierra_reset"; +- clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, +- <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; +- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", +- "pll0_refclk", "pll1_refclk"; +- }; +- }; +- +- pcie0_rc: pcie@2900000 { +- compatible = "ti,j721e-pcie-host"; +- reg = <0x00 0x02900000 0x00 0x1000>, +- <0x00 0x02907000 0x00 0x400>, +- <0x00 0x0d000000 0x00 0x00800000>, +- <0x00 0x10000000 0x00 0x00001000>; +- reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; +- interrupt-names = "link_state"; +- interrupts = ; +- device_type = "pci"; +- ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; +- max-link-speed = <3>; +- num-lanes = <2>; +- power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 239 1>; +- clock-names = "fck"; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x0 0xff>; +- vendor-id = <0x104c>; +- device-id = <0xb00d>; +- msi-map = <0x0 &gic_its 0x0 0x10000>; +- dma-coherent; +- ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, +- <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; +- dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; +- }; +- +- pcie0_ep: pcie-ep@2900000 { +- compatible = "ti,j721e-pcie-ep"; +- reg = <0x00 0x02900000 0x00 0x1000>, +- <0x00 0x02907000 0x00 0x400>, +- <0x00 0x0d000000 0x00 0x00800000>, +- <0x00 0x10000000 0x00 0x08000000>; +- reg-names = "intd_cfg", "user_cfg", "reg", "mem"; +- interrupt-names = "link_state"; +- interrupts = ; +- ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; +- max-link-speed = <3>; +- num-lanes = <2>; +- power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 239 1>; +- clock-names = "fck"; +- max-functions = /bits/ 8 <6>; +- max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; +- dma-coherent; +- }; +- +- pcie1_rc: pcie@2910000 { +- compatible = "ti,j721e-pcie-host"; +- reg = <0x00 0x02910000 0x00 0x1000>, +- <0x00 0x02917000 0x00 0x400>, +- <0x00 0x0d800000 0x00 0x00800000>, +- <0x00 0x18000000 0x00 0x00001000>; +- reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; +- interrupt-names = "link_state"; +- interrupts = ; +- device_type = "pci"; +- ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; +- max-link-speed = <3>; +- num-lanes = <2>; +- power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 240 1>; +- clock-names = "fck"; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x0 0xff>; +- vendor-id = <0x104c>; +- device-id = <0xb00d>; +- msi-map = <0x0 &gic_its 0x10000 0x10000>; +- dma-coherent; +- ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, +- <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; +- dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; +- }; +- +- pcie1_ep: pcie-ep@2910000 { +- compatible = "ti,j721e-pcie-ep"; +- reg = <0x00 0x02910000 0x00 0x1000>, +- <0x00 0x02917000 0x00 0x400>, +- <0x00 0x0d800000 0x00 0x00800000>, +- <0x00 0x18000000 0x00 0x08000000>; +- reg-names = "intd_cfg", "user_cfg", "reg", "mem"; +- interrupt-names = "link_state"; +- interrupts = ; +- ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; +- max-link-speed = <3>; +- num-lanes = <2>; +- power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 240 1>; +- clock-names = "fck"; +- max-functions = /bits/ 8 <6>; +- max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; +- dma-coherent; +- }; +- +- pcie2_rc: pcie@2920000 { +- compatible = "ti,j721e-pcie-host"; +- reg = <0x00 0x02920000 0x00 0x1000>, +- <0x00 0x02927000 0x00 0x400>, +- <0x00 0x0e000000 0x00 0x00800000>, +- <0x44 0x00000000 0x00 0x00001000>; +- reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; +- interrupt-names = "link_state"; +- interrupts = ; +- device_type = "pci"; +- ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; +- max-link-speed = <3>; +- num-lanes = <2>; +- power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 241 1>; +- clock-names = "fck"; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x0 0xff>; +- vendor-id = <0x104c>; +- device-id = <0xb00d>; +- msi-map = <0x0 &gic_its 0x20000 0x10000>; +- dma-coherent; +- ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, +- <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; +- dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; +- }; +- +- pcie2_ep: pcie-ep@2920000 { +- compatible = "ti,j721e-pcie-ep"; +- reg = <0x00 0x02920000 0x00 0x1000>, +- <0x00 0x02927000 0x00 0x400>, +- <0x00 0x0e000000 0x00 0x00800000>, +- <0x44 0x00000000 0x00 0x08000000>; +- reg-names = "intd_cfg", "user_cfg", "reg", "mem"; +- interrupt-names = "link_state"; +- interrupts = ; +- ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; +- max-link-speed = <3>; +- num-lanes = <2>; +- power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 241 1>; +- clock-names = "fck"; +- max-functions = /bits/ 8 <6>; +- max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; +- dma-coherent; +- }; +- +- pcie3_rc: pcie@2930000 { +- compatible = "ti,j721e-pcie-host"; +- reg = <0x00 0x02930000 0x00 0x1000>, +- <0x00 0x02937000 0x00 0x400>, +- <0x00 0x0e800000 0x00 0x00800000>, +- <0x44 0x10000000 0x00 0x00001000>; +- reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; +- interrupt-names = "link_state"; +- interrupts = ; +- device_type = "pci"; +- ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; +- max-link-speed = <3>; +- num-lanes = <2>; +- power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 242 1>; +- clock-names = "fck"; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x0 0xff>; +- vendor-id = <0x104c>; +- device-id = <0xb00d>; +- msi-map = <0x0 &gic_its 0x30000 0x10000>; +- dma-coherent; +- ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, +- <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; +- dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; +- }; +- +- pcie3_ep: pcie-ep@2930000 { +- compatible = "ti,j721e-pcie-ep"; +- reg = <0x00 0x02930000 0x00 0x1000>, +- <0x00 0x02937000 0x00 0x400>, +- <0x00 0x0e800000 0x00 0x00800000>, +- <0x44 0x10000000 0x00 0x08000000>; +- reg-names = "intd_cfg", "user_cfg", "reg", "mem"; +- interrupt-names = "link_state"; +- interrupts = ; +- ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; +- max-link-speed = <3>; +- num-lanes = <2>; +- power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 242 1>; +- clock-names = "fck"; +- max-functions = /bits/ 8 <6>; +- max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; +- dma-coherent; +- #address-cells = <2>; +- #size-cells = <2>; +- }; +- +- main_uart0: serial@2800000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02800000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 146 0>; +- clock-names = "fclk"; +- }; +- +- main_uart1: serial@2810000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02810000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 278 0>; +- clock-names = "fclk"; +- }; +- +- main_uart2: serial@2820000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02820000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 279 0>; +- clock-names = "fclk"; +- }; +- +- main_uart3: serial@2830000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02830000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 280 0>; +- clock-names = "fclk"; +- }; +- +- main_uart4: serial@2840000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02840000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 281 0>; +- clock-names = "fclk"; +- }; +- +- main_uart5: serial@2850000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02850000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 282 0>; +- clock-names = "fclk"; +- }; +- +- main_uart6: serial@2860000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02860000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 283 0>; +- clock-names = "fclk"; +- }; +- +- main_uart7: serial@2870000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02870000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 284 0>; +- clock-names = "fclk"; +- }; +- +- main_uart8: serial@2880000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02880000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 285 0>; +- clock-names = "fclk"; +- }; +- +- main_uart9: serial@2890000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x02890000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 286 0>; +- clock-names = "fclk"; +- }; +- +- main_gpio0: gpio@600000 { +- compatible = "ti,j721e-gpio", "ti,keystone-gpio"; +- reg = <0x0 0x00600000 0x0 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&main_gpio_intr>; +- interrupts = <256>, <257>, <258>, <259>, +- <260>, <261>, <262>, <263>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <128>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 105 0>; +- clock-names = "gpio"; +- }; +- +- main_gpio1: gpio@601000 { +- compatible = "ti,j721e-gpio", "ti,keystone-gpio"; +- reg = <0x0 0x00601000 0x0 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&main_gpio_intr>; +- interrupts = <288>, <289>, <290>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <36>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 106 0>; +- clock-names = "gpio"; +- }; +- +- main_gpio2: gpio@610000 { +- compatible = "ti,j721e-gpio", "ti,keystone-gpio"; +- reg = <0x0 0x00610000 0x0 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&main_gpio_intr>; +- interrupts = <264>, <265>, <266>, <267>, +- <268>, <269>, <270>, <271>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <128>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 107 0>; +- clock-names = "gpio"; +- }; +- +- main_gpio3: gpio@611000 { +- compatible = "ti,j721e-gpio", "ti,keystone-gpio"; +- reg = <0x0 0x00611000 0x0 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&main_gpio_intr>; +- interrupts = <292>, <293>, <294>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <36>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 108 0>; +- clock-names = "gpio"; +- }; +- +- main_gpio4: gpio@620000 { +- compatible = "ti,j721e-gpio", "ti,keystone-gpio"; +- reg = <0x0 0x00620000 0x0 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&main_gpio_intr>; +- interrupts = <272>, <273>, <274>, <275>, +- <276>, <277>, <278>, <279>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <128>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 109 0>; +- clock-names = "gpio"; +- }; +- +- main_gpio5: gpio@621000 { +- compatible = "ti,j721e-gpio", "ti,keystone-gpio"; +- reg = <0x0 0x00621000 0x0 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&main_gpio_intr>; +- interrupts = <296>, <297>, <298>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <36>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 110 0>; +- clock-names = "gpio"; +- }; +- +- main_gpio6: gpio@630000 { +- compatible = "ti,j721e-gpio", "ti,keystone-gpio"; +- reg = <0x0 0x00630000 0x0 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&main_gpio_intr>; +- interrupts = <280>, <281>, <282>, <283>, +- <284>, <285>, <286>, <287>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <128>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 111 0>; +- clock-names = "gpio"; +- }; +- +- main_gpio7: gpio@631000 { +- compatible = "ti,j721e-gpio", "ti,keystone-gpio"; +- reg = <0x0 0x00631000 0x0 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&main_gpio_intr>; +- interrupts = <300>, <301>, <302>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <36>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 112 0>; +- clock-names = "gpio"; +- }; +- +- main_sdhci0: mmc@4f80000 { +- compatible = "ti,j721e-sdhci-8bit"; +- reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; +- interrupts = ; +- power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; +- clock-names = "clk_ahb", "clk_xin"; +- clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; +- assigned-clocks = <&k3_clks 91 1>; +- assigned-clock-parents = <&k3_clks 91 2>; +- bus-width = <8>; +- mmc-hs200-1_8v; +- mmc-ddr-1_8v; +- ti,otap-del-sel-legacy = <0xf>; +- ti,otap-del-sel-mmc-hs = <0xf>; +- ti,otap-del-sel-ddr52 = <0x5>; +- ti,otap-del-sel-hs200 = <0x6>; +- ti,otap-del-sel-hs400 = <0x0>; +- ti,itap-del-sel-legacy = <0x10>; +- ti,itap-del-sel-mmc-hs = <0xa>; +- ti,itap-del-sel-ddr52 = <0x3>; +- ti,trm-icp = <0x8>; +- ti,strobe-sel = <0x77>; +- dma-coherent; +- }; +- +- main_sdhci1: mmc@4fb0000 { +- compatible = "ti,j721e-sdhci-4bit"; +- reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; +- interrupts = ; +- power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; +- clock-names = "clk_ahb", "clk_xin"; +- clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; +- assigned-clocks = <&k3_clks 92 0>; +- assigned-clock-parents = <&k3_clks 92 1>; +- ti,otap-del-sel-legacy = <0x0>; +- ti,otap-del-sel-sd-hs = <0xf>; +- ti,otap-del-sel-sdr12 = <0xf>; +- ti,otap-del-sel-sdr25 = <0xf>; +- ti,otap-del-sel-sdr50 = <0xc>; +- ti,otap-del-sel-ddr50 = <0xc>; +- ti,itap-del-sel-legacy = <0x0>; +- ti,itap-del-sel-sd-hs = <0x0>; +- ti,itap-del-sel-sdr12 = <0x0>; +- ti,itap-del-sel-sdr25 = <0x0>; +- ti,itap-del-sel-ddr50 = <0x2>; +- ti,trm-icp = <0x8>; +- ti,clkbuf-sel = <0x7>; +- dma-coherent; +- sdhci-caps-mask = <0x2 0x0>; +- }; +- +- main_sdhci2: mmc@4f98000 { +- compatible = "ti,j721e-sdhci-4bit"; +- reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; +- interrupts = ; +- power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; +- clock-names = "clk_ahb", "clk_xin"; +- clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; +- assigned-clocks = <&k3_clks 93 0>; +- assigned-clock-parents = <&k3_clks 93 1>; +- ti,otap-del-sel-legacy = <0x0>; +- ti,otap-del-sel-sd-hs = <0xf>; +- ti,otap-del-sel-sdr12 = <0xf>; +- ti,otap-del-sel-sdr25 = <0xf>; +- ti,otap-del-sel-sdr50 = <0xc>; +- ti,otap-del-sel-ddr50 = <0xc>; +- ti,itap-del-sel-legacy = <0x0>; +- ti,itap-del-sel-sd-hs = <0x0>; +- ti,itap-del-sel-sdr12 = <0x0>; +- ti,itap-del-sel-sdr25 = <0x0>; +- ti,itap-del-sel-ddr50 = <0x2>; +- ti,trm-icp = <0x8>; +- ti,clkbuf-sel = <0x7>; +- dma-coherent; +- sdhci-caps-mask = <0x2 0x0>; +- }; +- +- usbss0: cdns-usb@4104000 { +- compatible = "ti,j721e-usb"; +- reg = <0x00 0x4104000 0x00 0x100>; +- dma-coherent; +- power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; +- clock-names = "ref", "lpm"; +- assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ +- assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- usb0: usb@6000000 { +- compatible = "cdns,usb3"; +- reg = <0x00 0x6000000 0x00 0x10000>, +- <0x00 0x6010000 0x00 0x10000>, +- <0x00 0x6020000 0x00 0x10000>; +- reg-names = "otg", "xhci", "dev"; +- interrupts = , /* irq.0 */ +- , /* irq.6 */ +- ; /* otgirq.0 */ +- interrupt-names = "host", +- "peripheral", +- "otg"; +- maximum-speed = "super-speed"; +- dr_mode = "otg"; +- }; +- }; +- +- usbss1: cdns-usb@4114000 { +- compatible = "ti,j721e-usb"; +- reg = <0x00 0x4114000 0x00 0x100>; +- dma-coherent; +- power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; +- clock-names = "ref", "lpm"; +- assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ +- assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- usb1: usb@6400000 { +- compatible = "cdns,usb3"; +- reg = <0x00 0x6400000 0x00 0x10000>, +- <0x00 0x6410000 0x00 0x10000>, +- <0x00 0x6420000 0x00 0x10000>; +- reg-names = "otg", "xhci", "dev"; +- interrupts = , /* irq.0 */ +- , /* irq.6 */ +- ; /* otgirq.0 */ +- interrupt-names = "host", +- "peripheral", +- "otg"; +- maximum-speed = "super-speed"; +- dr_mode = "otg"; +- }; +- }; +- +- main_i2c0: i2c@2000000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x0 0x2000000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 187 0>; +- power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; +- }; +- +- main_i2c1: i2c@2010000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x0 0x2010000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 188 0>; +- power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- main_i2c2: i2c@2020000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x0 0x2020000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 189 0>; +- power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- main_i2c3: i2c@2030000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x0 0x2030000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 190 0>; +- power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- main_i2c4: i2c@2040000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x0 0x2040000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 191 0>; +- power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- main_i2c5: i2c@2050000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x0 0x2050000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 192 0>; +- power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- main_i2c6: i2c@2060000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x0 0x2060000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 193 0>; +- power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- ufs_wrapper: ufs-wrapper@4e80000 { +- compatible = "ti,j721e-ufs"; +- reg = <0x0 0x4e80000 0x0 0x100>; +- power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 277 1>; +- assigned-clocks = <&k3_clks 277 1>; +- assigned-clock-parents = <&k3_clks 277 4>; +- ranges; +- #address-cells = <2>; +- #size-cells = <2>; +- +- ufs@4e84000 { +- compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; +- reg = <0x0 0x4e84000 0x0 0x10000>; +- interrupts = ; +- freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; +- clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; +- clock-names = "core_clk", "phy_clk", "ref_clk"; +- dma-coherent; +- }; +- }; +- +- dss: dss@4a00000 { +- compatible = "ti,j721e-dss"; +- reg = +- <0x00 0x04a00000 0x00 0x10000>, /* common_m */ +- <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ +- <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ +- <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ +- +- <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ +- <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ +- <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ +- <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ +- +- <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ +- <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ +- <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ +- <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ +- +- <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ +- <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ +- <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ +- <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ +- <0x00 0x04af0000 0x00 0x10000>; /* wb */ +- +- reg-names = "common_m", "common_s0", +- "common_s1", "common_s2", +- "vidl1", "vidl2","vid1","vid2", +- "ovr1", "ovr2", "ovr3", "ovr4", +- "vp1", "vp2", "vp3", "vp4", +- "wb"; +- +- clocks = <&k3_clks 152 0>, +- <&k3_clks 152 1>, +- <&k3_clks 152 4>, +- <&k3_clks 152 9>, +- <&k3_clks 152 13>; +- clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; +- +- power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; +- +- interrupts = , +- , +- , +- ; +- interrupt-names = "common_m", +- "common_s0", +- "common_s1", +- "common_s2"; +- +- dss_ports: ports { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- mcasp0: mcasp@2b00000 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x0 0x02b00000 0x0 0x2000>, +- <0x0 0x02b08000 0x0 0x1000>; +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- +- dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; +- dma-names = "tx", "rx"; +- +- clocks = <&k3_clks 174 1>; +- clock-names = "fck"; +- power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- mcasp1: mcasp@2b10000 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x0 0x02b10000 0x0 0x2000>, +- <0x0 0x02b18000 0x0 0x1000>; +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- +- dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; +- dma-names = "tx", "rx"; +- +- clocks = <&k3_clks 175 1>; +- clock-names = "fck"; +- power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- mcasp2: mcasp@2b20000 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x0 0x02b20000 0x0 0x2000>, +- <0x0 0x02b28000 0x0 0x1000>; +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- +- dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; +- dma-names = "tx", "rx"; +- +- clocks = <&k3_clks 176 1>; +- clock-names = "fck"; +- power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- mcasp3: mcasp@2b30000 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x0 0x02b30000 0x0 0x2000>, +- <0x0 0x02b38000 0x0 0x1000>; +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- +- dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; +- dma-names = "tx", "rx"; +- +- clocks = <&k3_clks 177 1>; +- clock-names = "fck"; +- power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- mcasp4: mcasp@2b40000 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x0 0x02b40000 0x0 0x2000>, +- <0x0 0x02b48000 0x0 0x1000>; +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- +- dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; +- dma-names = "tx", "rx"; +- +- clocks = <&k3_clks 178 1>; +- clock-names = "fck"; +- power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- mcasp5: mcasp@2b50000 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x0 0x02b50000 0x0 0x2000>, +- <0x0 0x02b58000 0x0 0x1000>; +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- +- dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; +- dma-names = "tx", "rx"; +- +- clocks = <&k3_clks 179 1>; +- clock-names = "fck"; +- power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- mcasp6: mcasp@2b60000 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x0 0x02b60000 0x0 0x2000>, +- <0x0 0x02b68000 0x0 0x1000>; +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- +- dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; +- dma-names = "tx", "rx"; +- +- clocks = <&k3_clks 180 1>; +- clock-names = "fck"; +- power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- mcasp7: mcasp@2b70000 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x0 0x02b70000 0x0 0x2000>, +- <0x0 0x02b78000 0x0 0x1000>; +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- +- dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; +- dma-names = "tx", "rx"; +- +- clocks = <&k3_clks 181 1>; +- clock-names = "fck"; +- power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- mcasp8: mcasp@2b80000 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x0 0x02b80000 0x0 0x2000>, +- <0x0 0x02b88000 0x0 0x1000>; +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- +- dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; +- dma-names = "tx", "rx"; +- +- clocks = <&k3_clks 182 1>; +- clock-names = "fck"; +- power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- mcasp9: mcasp@2b90000 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x0 0x02b90000 0x0 0x2000>, +- <0x0 0x02b98000 0x0 0x1000>; +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- +- dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; +- dma-names = "tx", "rx"; +- +- clocks = <&k3_clks 183 1>; +- clock-names = "fck"; +- power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- mcasp10: mcasp@2ba0000 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x0 0x02ba0000 0x0 0x2000>, +- <0x0 0x02ba8000 0x0 0x1000>; +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- +- dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; +- dma-names = "tx", "rx"; +- +- clocks = <&k3_clks 184 1>; +- clock-names = "fck"; +- power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- mcasp11: mcasp@2bb0000 { +- compatible = "ti,am33xx-mcasp-audio"; +- reg = <0x0 0x02bb0000 0x0 0x2000>, +- <0x0 0x02bb8000 0x0 0x1000>; +- reg-names = "mpu","dat"; +- interrupts = , +- ; +- interrupt-names = "tx", "rx"; +- +- dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; +- dma-names = "tx", "rx"; +- +- clocks = <&k3_clks 185 1>; +- clock-names = "fck"; +- power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- watchdog0: watchdog@2200000 { +- compatible = "ti,j7-rti-wdt"; +- reg = <0x0 0x2200000 0x0 0x100>; +- clocks = <&k3_clks 252 1>; +- power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; +- assigned-clocks = <&k3_clks 252 1>; +- assigned-clock-parents = <&k3_clks 252 5>; +- }; +- +- watchdog1: watchdog@2210000 { +- compatible = "ti,j7-rti-wdt"; +- reg = <0x0 0x2210000 0x0 0x100>; +- clocks = <&k3_clks 253 1>; +- power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; +- assigned-clocks = <&k3_clks 253 1>; +- assigned-clock-parents = <&k3_clks 253 5>; +- }; +- +- main_r5fss0: r5fss@5c00000 { +- compatible = "ti,j721e-r5fss"; +- ti,cluster-mode = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x5c00000 0x00 0x5c00000 0x20000>, +- <0x5d00000 0x00 0x5d00000 0x20000>; +- power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; +- +- main_r5fss0_core0: r5f@5c00000 { +- compatible = "ti,j721e-r5f"; +- reg = <0x5c00000 0x00008000>, +- <0x5c10000 0x00008000>; +- reg-names = "atcm", "btcm"; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <245>; +- ti,sci-proc-ids = <0x06 0xff>; +- resets = <&k3_reset 245 1>; +- firmware-name = "j7-main-r5f0_0-fw"; +- ti,atcm-enable = <1>; +- ti,btcm-enable = <1>; +- ti,loczrama = <1>; +- }; +- +- main_r5fss0_core1: r5f@5d00000 { +- compatible = "ti,j721e-r5f"; +- reg = <0x5d00000 0x00008000>, +- <0x5d10000 0x00008000>; +- reg-names = "atcm", "btcm"; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <246>; +- ti,sci-proc-ids = <0x07 0xff>; +- resets = <&k3_reset 246 1>; +- firmware-name = "j7-main-r5f0_1-fw"; +- ti,atcm-enable = <1>; +- ti,btcm-enable = <1>; +- ti,loczrama = <1>; +- }; +- }; +- +- main_r5fss1: r5fss@5e00000 { +- compatible = "ti,j721e-r5fss"; +- ti,cluster-mode = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x5e00000 0x00 0x5e00000 0x20000>, +- <0x5f00000 0x00 0x5f00000 0x20000>; +- power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; +- +- main_r5fss1_core0: r5f@5e00000 { +- compatible = "ti,j721e-r5f"; +- reg = <0x5e00000 0x00008000>, +- <0x5e10000 0x00008000>; +- reg-names = "atcm", "btcm"; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <247>; +- ti,sci-proc-ids = <0x08 0xff>; +- resets = <&k3_reset 247 1>; +- firmware-name = "j7-main-r5f1_0-fw"; +- ti,atcm-enable = <1>; +- ti,btcm-enable = <1>; +- ti,loczrama = <1>; +- }; +- +- main_r5fss1_core1: r5f@5f00000 { +- compatible = "ti,j721e-r5f"; +- reg = <0x5f00000 0x00008000>, +- <0x5f10000 0x00008000>; +- reg-names = "atcm", "btcm"; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <248>; +- ti,sci-proc-ids = <0x09 0xff>; +- resets = <&k3_reset 248 1>; +- firmware-name = "j7-main-r5f1_1-fw"; +- ti,atcm-enable = <1>; +- ti,btcm-enable = <1>; +- ti,loczrama = <1>; +- }; +- }; +- +- c66_0: dsp@4d80800000 { +- compatible = "ti,j721e-c66-dsp"; +- reg = <0x4d 0x80800000 0x00 0x00048000>, +- <0x4d 0x80e00000 0x00 0x00008000>, +- <0x4d 0x80f00000 0x00 0x00008000>; +- reg-names = "l2sram", "l1pram", "l1dram"; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <142>; +- ti,sci-proc-ids = <0x03 0xff>; +- resets = <&k3_reset 142 1>; +- firmware-name = "j7-c66_0-fw"; +- }; +- +- c66_1: dsp@4d81800000 { +- compatible = "ti,j721e-c66-dsp"; +- reg = <0x4d 0x81800000 0x00 0x00048000>, +- <0x4d 0x81e00000 0x00 0x00008000>, +- <0x4d 0x81f00000 0x00 0x00008000>; +- reg-names = "l2sram", "l1pram", "l1dram"; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <143>; +- ti,sci-proc-ids = <0x04 0xff>; +- resets = <&k3_reset 143 1>; +- firmware-name = "j7-c66_1-fw"; +- }; +- +- c71_0: dsp@64800000 { +- compatible = "ti,j721e-c71-dsp"; +- reg = <0x00 0x64800000 0x00 0x00080000>, +- <0x00 0x64e00000 0x00 0x0000c000>; +- reg-names = "l2sram", "l1dram"; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <15>; +- ti,sci-proc-ids = <0x30 0xff>; +- resets = <&k3_reset 15 1>; +- firmware-name = "j7-c71_0-fw"; +- }; +- +- icssg0: icssg@b000000 { +- compatible = "ti,j721e-icssg"; +- reg = <0x00 0xb000000 0x00 0x80000>; +- power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x00 0x0b000000 0x100000>; +- +- icssg0_mem: memories@0 { +- reg = <0x0 0x2000>, +- <0x2000 0x2000>, +- <0x10000 0x10000>; +- reg-names = "dram0", "dram1", +- "shrdram2"; +- }; +- +- icssg0_cfg: cfg@26000 { +- compatible = "ti,pruss-cfg", "syscon"; +- reg = <0x26000 0x200>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x26000 0x2000>; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- icssg0_coreclk_mux: coreclk-mux@3c { +- reg = <0x3c>; +- #clock-cells = <0>; +- clocks = <&k3_clks 119 24>, /* icssg0_core_clk */ +- <&k3_clks 119 1>; /* icssg0_iclk */ +- assigned-clocks = <&icssg0_coreclk_mux>; +- assigned-clock-parents = <&k3_clks 119 1>; +- }; +- +- icssg0_iepclk_mux: iepclk-mux@30 { +- reg = <0x30>; +- #clock-cells = <0>; +- clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */ +- <&icssg0_coreclk_mux>; /* core_clk */ +- assigned-clocks = <&icssg0_iepclk_mux>; +- assigned-clock-parents = <&icssg0_coreclk_mux>; +- }; +- }; +- }; +- +- icssg0_mii_rt: mii-rt@32000 { +- compatible = "ti,pruss-mii", "syscon"; +- reg = <0x32000 0x100>; +- }; +- +- icssg0_mii_g_rt: mii-g-rt@33000 { +- compatible = "ti,pruss-mii-g", "syscon"; +- reg = <0x33000 0x1000>; +- }; +- +- icssg0_intc: interrupt-controller@20000 { +- compatible = "ti,icssg-intc"; +- reg = <0x20000 0x2000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "host_intr0", "host_intr1", +- "host_intr2", "host_intr3", +- "host_intr4", "host_intr5", +- "host_intr6", "host_intr7"; +- }; +- +- pru0_0: pru@34000 { +- compatible = "ti,j721e-pru"; +- reg = <0x34000 0x3000>, +- <0x22000 0x100>, +- <0x22400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "j7-pru0_0-fw"; +- }; +- +- rtu0_0: rtu@4000 { +- compatible = "ti,j721e-rtu"; +- reg = <0x4000 0x2000>, +- <0x23000 0x100>, +- <0x23400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "j7-rtu0_0-fw"; +- }; +- +- tx_pru0_0: txpru@a000 { +- compatible = "ti,j721e-tx-pru"; +- reg = <0xa000 0x1800>, +- <0x25000 0x100>, +- <0x25400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "j7-txpru0_0-fw"; +- }; +- +- pru0_1: pru@38000 { +- compatible = "ti,j721e-pru"; +- reg = <0x38000 0x3000>, +- <0x24000 0x100>, +- <0x24400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "j7-pru0_1-fw"; +- }; +- +- rtu0_1: rtu@6000 { +- compatible = "ti,j721e-rtu"; +- reg = <0x6000 0x2000>, +- <0x23800 0x100>, +- <0x23c00 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "j7-rtu0_1-fw"; +- }; +- +- tx_pru0_1: txpru@c000 { +- compatible = "ti,j721e-tx-pru"; +- reg = <0xc000 0x1800>, +- <0x25800 0x100>, +- <0x25c00 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "j7-txpru0_1-fw"; +- }; +- +- icssg0_mdio: mdio@32400 { +- compatible = "ti,davinci_mdio"; +- reg = <0x32400 0x100>; +- clocks = <&k3_clks 119 1>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <0>; +- bus_freq = <1000000>; +- }; +- }; +- +- icssg1: icssg@b100000 { +- compatible = "ti,j721e-icssg"; +- reg = <0x00 0xb100000 0x00 0x80000>; +- power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x00 0x0b100000 0x100000>; +- +- icssg1_mem: memories@b100000 { +- reg = <0x0 0x2000>, +- <0x2000 0x2000>, +- <0x10000 0x10000>; +- reg-names = "dram0", "dram1", +- "shrdram2"; +- }; +- +- icssg1_cfg: cfg@26000 { +- compatible = "ti,pruss-cfg", "syscon"; +- reg = <0x26000 0x200>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x26000 0x2000>; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- icssg1_coreclk_mux: coreclk-mux@3c { +- reg = <0x3c>; +- #clock-cells = <0>; +- clocks = <&k3_clks 120 54>, /* icssg1_core_clk */ +- <&k3_clks 120 4>; /* icssg1_iclk */ +- assigned-clocks = <&icssg1_coreclk_mux>; +- assigned-clock-parents = <&k3_clks 120 4>; +- }; +- +- icssg1_iepclk_mux: iepclk-mux@30 { +- reg = <0x30>; +- #clock-cells = <0>; +- clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */ +- <&icssg1_coreclk_mux>; /* core_clk */ +- assigned-clocks = <&icssg1_iepclk_mux>; +- assigned-clock-parents = <&icssg1_coreclk_mux>; +- }; +- }; +- }; +- +- icssg1_mii_rt: mii-rt@32000 { +- compatible = "ti,pruss-mii", "syscon"; +- reg = <0x32000 0x100>; +- }; +- +- icssg1_mii_g_rt: mii-g-rt@33000 { +- compatible = "ti,pruss-mii-g", "syscon"; +- reg = <0x33000 0x1000>; +- }; +- +- icssg1_intc: interrupt-controller@20000 { +- compatible = "ti,icssg-intc"; +- reg = <0x20000 0x2000>; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- interrupt-names = "host_intr0", "host_intr1", +- "host_intr2", "host_intr3", +- "host_intr4", "host_intr5", +- "host_intr6", "host_intr7"; +- }; +- +- pru1_0: pru@34000 { +- compatible = "ti,j721e-pru"; +- reg = <0x34000 0x4000>, +- <0x22000 0x100>, +- <0x22400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "j7-pru1_0-fw"; +- }; +- +- rtu1_0: rtu@4000 { +- compatible = "ti,j721e-rtu"; +- reg = <0x4000 0x2000>, +- <0x23000 0x100>, +- <0x23400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "j7-rtu1_0-fw"; +- }; +- +- tx_pru1_0: txpru@a000 { +- compatible = "ti,j721e-tx-pru"; +- reg = <0xa000 0x1800>, +- <0x25000 0x100>, +- <0x25400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "j7-txpru1_0-fw"; +- }; +- +- pru1_1: pru@38000 { +- compatible = "ti,j721e-pru"; +- reg = <0x38000 0x4000>, +- <0x24000 0x100>, +- <0x24400 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "j7-pru1_1-fw"; +- }; +- +- rtu1_1: rtu@6000 { +- compatible = "ti,j721e-rtu"; +- reg = <0x6000 0x2000>, +- <0x23800 0x100>, +- <0x23c00 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "j7-rtu1_1-fw"; +- }; +- +- tx_pru1_1: txpru@c000 { +- compatible = "ti,j721e-tx-pru"; +- reg = <0xc000 0x1800>, +- <0x25800 0x100>, +- <0x25c00 0x100>; +- reg-names = "iram", "control", "debug"; +- firmware-name = "j7-txpru1_1-fw"; +- }; +- +- icssg1_mdio: mdio@32400 { +- compatible = "ti,davinci_mdio"; +- reg = <0x32400 0x100>; +- clocks = <&k3_clks 120 4>; +- clock-names = "fck"; +- #address-cells = <1>; +- #size-cells = <0>; +- bus_freq = <1000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-j721e-mcu-wakeup.dtsi b/scripts/dtc/include-prefixes/arm64/ti/k3-j721e-mcu-wakeup.dtsi +deleted file mode 100644 +index d2dceda72fe9..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-j721e-mcu-wakeup.dtsi ++++ /dev/null +@@ -1,393 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals +- * +- * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-&cbass_mcu_wakeup { +- dmsc: system-controller@44083000 { +- compatible = "ti,k2g-sci"; +- ti,host-id = <12>; +- +- mbox-names = "rx", "tx"; +- +- mboxes= <&secure_proxy_main 11>, +- <&secure_proxy_main 13>; +- +- reg-names = "debug_messages"; +- reg = <0x00 0x44083000 0x0 0x1000>; +- +- k3_pds: power-controller { +- compatible = "ti,sci-pm-domain"; +- #power-domain-cells = <2>; +- }; +- +- k3_clks: clock-controller { +- compatible = "ti,k2g-sci-clk"; +- #clock-cells = <2>; +- }; +- +- k3_reset: reset-controller { +- compatible = "ti,sci-reset"; +- #reset-cells = <2>; +- }; +- }; +- +- mcu_conf: syscon@40f00000 { +- compatible = "syscon", "simple-mfd"; +- reg = <0x0 0x40f00000 0x0 0x20000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x40f00000 0x20000>; +- +- phy_gmii_sel: phy@4040 { +- compatible = "ti,am654-phy-gmii-sel"; +- reg = <0x4040 0x4>; +- #phy-cells = <1>; +- }; +- }; +- +- chipid@43000014 { +- compatible = "ti,am654-chipid"; +- reg = <0x0 0x43000014 0x0 0x4>; +- }; +- +- wkup_pmx0: pinctrl@4301c000 { +- compatible = "pinctrl-single"; +- /* Proxy 0 addressing */ +- reg = <0x00 0x4301c000 0x00 0x178>; +- #pinctrl-cells = <1>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0xffffffff>; +- }; +- +- mcu_ram: sram@41c00000 { +- compatible = "mmio-sram"; +- reg = <0x00 0x41c00000 0x00 0x100000>; +- ranges = <0x0 0x00 0x41c00000 0x100000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- wkup_uart0: serial@42300000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x42300000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <48000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 287 0>; +- clock-names = "fclk"; +- }; +- +- mcu_uart0: serial@40a00000 { +- compatible = "ti,j721e-uart", "ti,am654-uart"; +- reg = <0x00 0x40a00000 0x00 0x100>; +- interrupts = ; +- clock-frequency = <96000000>; +- current-speed = <115200>; +- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 149 0>; +- clock-names = "fclk"; +- }; +- +- wkup_gpio_intr: interrupt-controller@42200000 { +- compatible = "ti,sci-intr"; +- reg = <0x00 0x42200000 0x00 0x400>; +- ti,intr-trigger-type = <1>; +- interrupt-controller; +- interrupt-parent = <&gic500>; +- #interrupt-cells = <1>; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <137>; +- ti,interrupt-ranges = <16 960 16>; +- }; +- +- wkup_gpio0: gpio@42110000 { +- compatible = "ti,j721e-gpio", "ti,keystone-gpio"; +- reg = <0x0 0x42110000 0x0 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&wkup_gpio_intr>; +- interrupts = <103>, <104>, <105>, <106>, <107>, <108>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <84>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 113 0>; +- clock-names = "gpio"; +- }; +- +- wkup_gpio1: gpio@42100000 { +- compatible = "ti,j721e-gpio", "ti,keystone-gpio"; +- reg = <0x0 0x42100000 0x0 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-parent = <&wkup_gpio_intr>; +- interrupts = <112>, <113>, <114>, <115>, <116>, <117>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <84>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 114 0>; +- clock-names = "gpio"; +- }; +- +- mcu_i2c0: i2c@40b00000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x0 0x40b00000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 194 0>; +- power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- mcu_i2c1: i2c@40b10000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x0 0x40b10000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 195 0>; +- power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; +- }; +- +- wkup_i2c0: i2c@42120000 { +- compatible = "ti,j721e-i2c", "ti,omap4-i2c"; +- reg = <0x0 0x42120000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 197 0>; +- power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; +- }; +- +- fss: fss@47000000 { +- compatible = "simple-bus"; +- reg = <0x0 0x47000000 0x0 0x100>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ospi0: spi@47040000 { +- compatible = "ti,am654-ospi", "cdns,qspi-nor"; +- reg = <0x0 0x47040000 0x0 0x100>, +- <0x5 0x00000000 0x1 0x0000000>; +- interrupts = ; +- cdns,fifo-depth = <256>; +- cdns,fifo-width = <4>; +- cdns,trigger-address = <0x0>; +- clocks = <&k3_clks 103 0>; +- assigned-clocks = <&k3_clks 103 0>; +- assigned-clock-parents = <&k3_clks 103 2>; +- assigned-clock-rates = <166666666>; +- power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- ospi1: spi@47050000 { +- compatible = "ti,am654-ospi", "cdns,qspi-nor"; +- reg = <0x0 0x47050000 0x0 0x100>, +- <0x7 0x00000000 0x1 0x00000000>; +- interrupts = ; +- cdns,fifo-depth = <256>; +- cdns,fifo-width = <4>; +- cdns,trigger-address = <0x0>; +- clocks = <&k3_clks 104 0>; +- power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- tscadc0: tscadc@40200000 { +- compatible = "ti,am3359-tscadc"; +- reg = <0x0 0x40200000 0x0 0x1000>; +- interrupts = ; +- power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 0 1>; +- assigned-clocks = <&k3_clks 0 3>; +- assigned-clock-rates = <60000000>; +- clock-names = "adc_tsc_fck"; +- dmas = <&main_udmap 0x7400>, +- <&main_udmap 0x7401>; +- dma-names = "fifo0", "fifo1"; +- +- adc { +- #io-channel-cells = <1>; +- compatible = "ti,am3359-adc"; +- }; +- }; +- +- tscadc1: tscadc@40210000 { +- compatible = "ti,am3359-tscadc"; +- reg = <0x0 0x40210000 0x0 0x1000>; +- interrupts = ; +- power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 1 1>; +- assigned-clocks = <&k3_clks 1 3>; +- assigned-clock-rates = <60000000>; +- clock-names = "adc_tsc_fck"; +- dmas = <&main_udmap 0x7402>, +- <&main_udmap 0x7403>; +- dma-names = "fifo0", "fifo1"; +- +- adc { +- #io-channel-cells = <1>; +- compatible = "ti,am3359-adc"; +- }; +- }; +- +- mcu_navss: bus@28380000 { +- compatible = "simple-mfd"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; +- dma-coherent; +- dma-ranges; +- +- ti,sci-dev-id = <232>; +- +- mcu_ringacc: ringacc@2b800000 { +- compatible = "ti,am654-navss-ringacc"; +- reg = <0x0 0x2b800000 0x0 0x400000>, +- <0x0 0x2b000000 0x0 0x400000>, +- <0x0 0x28590000 0x0 0x100>, +- <0x0 0x2a500000 0x0 0x40000>; +- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; +- ti,num-rings = <286>; +- ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <235>; +- msi-parent = <&main_udmass_inta>; +- }; +- +- mcu_udmap: dma-controller@285c0000 { +- compatible = "ti,j721e-navss-mcu-udmap"; +- reg = <0x0 0x285c0000 0x0 0x100>, +- <0x0 0x2a800000 0x0 0x40000>, +- <0x0 0x2aa00000 0x0 0x40000>; +- reg-names = "gcfg", "rchanrt", "tchanrt"; +- msi-parent = <&main_udmass_inta>; +- #dma-cells = <1>; +- +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <236>; +- ti,ringacc = <&mcu_ringacc>; +- +- ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ +- <0x0f>; /* TX_HCHAN */ +- ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ +- <0x0b>; /* RX_HCHAN */ +- ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ +- }; +- }; +- +- mcu_cpsw: ethernet@46000000 { +- compatible = "ti,j721e-cpsw-nuss"; +- #address-cells = <2>; +- #size-cells = <2>; +- reg = <0x0 0x46000000 0x0 0x200000>; +- reg-names = "cpsw_nuss"; +- ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; +- dma-coherent; +- clocks = <&k3_clks 18 22>; +- clock-names = "fck"; +- power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; +- +- dmas = <&mcu_udmap 0xf000>, +- <&mcu_udmap 0xf001>, +- <&mcu_udmap 0xf002>, +- <&mcu_udmap 0xf003>, +- <&mcu_udmap 0xf004>, +- <&mcu_udmap 0xf005>, +- <&mcu_udmap 0xf006>, +- <&mcu_udmap 0xf007>, +- <&mcu_udmap 0x7000>; +- dma-names = "tx0", "tx1", "tx2", "tx3", +- "tx4", "tx5", "tx6", "tx7", +- "rx"; +- +- ethernet-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpsw_port1: port@1 { +- reg = <1>; +- ti,mac-only; +- label = "port1"; +- ti,syscon-efuse = <&mcu_conf 0x200>; +- phys = <&phy_gmii_sel 1>; +- }; +- }; +- +- davinci_mdio: mdio@f00 { +- compatible = "ti,cpsw-mdio","ti,davinci_mdio"; +- reg = <0x0 0xf00 0x0 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&k3_clks 18 22>; +- clock-names = "fck"; +- bus_freq = <1000000>; +- }; +- +- cpts@3d000 { +- compatible = "ti,am65-cpts"; +- reg = <0x0 0x3d000 0x0 0x400>; +- clocks = <&k3_clks 18 2>; +- clock-names = "cpts"; +- interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "cpts"; +- ti,cpts-ext-ts-inputs = <4>; +- ti,cpts-periodic-outputs = <2>; +- }; +- }; +- +- mcu_r5fss0: r5fss@41000000 { +- compatible = "ti,j721e-r5fss"; +- ti,cluster-mode = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x41000000 0x00 0x41000000 0x20000>, +- <0x41400000 0x00 0x41400000 0x20000>; +- power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; +- +- mcu_r5fss0_core0: r5f@41000000 { +- compatible = "ti,j721e-r5f"; +- reg = <0x41000000 0x00008000>, +- <0x41010000 0x00008000>; +- reg-names = "atcm", "btcm"; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <250>; +- ti,sci-proc-ids = <0x01 0xff>; +- resets = <&k3_reset 250 1>; +- firmware-name = "j7-mcu-r5f0_0-fw"; +- ti,atcm-enable = <1>; +- ti,btcm-enable = <1>; +- ti,loczrama = <1>; +- }; +- +- mcu_r5fss0_core1: r5f@41400000 { +- compatible = "ti,j721e-r5f"; +- reg = <0x41400000 0x00008000>, +- <0x41410000 0x00008000>; +- reg-names = "atcm", "btcm"; +- ti,sci = <&dmsc>; +- ti,sci-dev-id = <251>; +- ti,sci-proc-ids = <0x02 0xff>; +- resets = <&k3_reset 251 1>; +- firmware-name = "j7-mcu-r5f0_1-fw"; +- ti,atcm-enable = <1>; +- ti,btcm-enable = <1>; +- ti,loczrama = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-j721e-som-p0.dtsi b/scripts/dtc/include-prefixes/arm64/ti/k3-j721e-som-p0.dtsi +deleted file mode 100644 +index 2fee2906183d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-j721e-som-p0.dtsi ++++ /dev/null +@@ -1,335 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-/dts-v1/; +- +-#include "k3-j721e.dtsi" +- +-/ { +- memory@80000000 { +- device_type = "memory"; +- /* 4G RAM */ +- reg = <0x00000000 0x80000000 0x00000000 0x80000000>, +- <0x00000008 0x80000000 0x00000000 0x80000000>; +- }; +- +- reserved_memory: reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- secure_ddr: optee@9e800000 { +- reg = <0x00 0x9e800000 0x00 0x01800000>; +- alignment = <0x1000>; +- no-map; +- }; +- +- mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa0000000 0x00 0x100000>; +- no-map; +- }; +- +- mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa0100000 0x00 0xf00000>; +- no-map; +- }; +- +- mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa1000000 0x00 0x100000>; +- no-map; +- }; +- +- mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa1100000 0x00 0xf00000>; +- no-map; +- }; +- +- main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa2000000 0x00 0x100000>; +- no-map; +- }; +- +- main_r5fss0_core0_memory_region: r5f-memory@a2100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa2100000 0x00 0xf00000>; +- no-map; +- }; +- +- main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa3000000 0x00 0x100000>; +- no-map; +- }; +- +- main_r5fss0_core1_memory_region: r5f-memory@a3100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa3100000 0x00 0xf00000>; +- no-map; +- }; +- +- main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa4000000 0x00 0x100000>; +- no-map; +- }; +- +- main_r5fss1_core0_memory_region: r5f-memory@a4100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa4100000 0x00 0xf00000>; +- no-map; +- }; +- +- main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa5000000 0x00 0x100000>; +- no-map; +- }; +- +- main_r5fss1_core1_memory_region: r5f-memory@a5100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa5100000 0x00 0xf00000>; +- no-map; +- }; +- +- c66_1_dma_memory_region: c66-dma-memory@a6000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa6000000 0x00 0x100000>; +- no-map; +- }; +- +- c66_0_memory_region: c66-memory@a6100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa6100000 0x00 0xf00000>; +- no-map; +- }; +- +- c66_0_dma_memory_region: c66-dma-memory@a7000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa7000000 0x00 0x100000>; +- no-map; +- }; +- +- c66_1_memory_region: c66-memory@a7100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa7100000 0x00 0xf00000>; +- no-map; +- }; +- +- c71_0_dma_memory_region: c71-dma-memory@a8000000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa8000000 0x00 0x100000>; +- no-map; +- }; +- +- c71_0_memory_region: c71-memory@a8100000 { +- compatible = "shared-dma-pool"; +- reg = <0x00 0xa8100000 0x00 0xf00000>; +- no-map; +- }; +- +- rtos_ipc_memory_region: ipc-memories@aa000000 { +- reg = <0x00 0xaa000000 0x00 0x01c00000>; +- alignment = <0x1000>; +- no-map; +- }; +- }; +-}; +- +-&wkup_pmx0 { +- wkup_i2c0_pins_default: wkup-i2c0-pins-default { +- pinctrl-single,pins = < +- J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ +- J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ +- >; +- }; +- +- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { +- pinctrl-single,pins = < +- J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ +- J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ +- J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ +- J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ +- J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ +- J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ +- J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ +- J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ +- J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ +- J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ +- J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ +- >; +- }; +-}; +- +-&ospi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; +- +- flash@0{ +- compatible = "jedec,spi-nor"; +- reg = <0x0>; +- spi-tx-bus-width = <8>; +- spi-rx-bus-width = <8>; +- spi-max-frequency = <25000000>; +- cdns,tshsl-ns = <60>; +- cdns,tsd2d-ns = <60>; +- cdns,tchsh-ns = <60>; +- cdns,tslch-ns = <60>; +- cdns,read-delay = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&mailbox0_cluster0 { +- interrupts = <436>; +- +- mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { +- ti,mbox-rx = <0 0 0>; +- ti,mbox-tx = <1 0 0>; +- }; +- +- mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { +- ti,mbox-rx = <2 0 0>; +- ti,mbox-tx = <3 0 0>; +- }; +-}; +- +-&mailbox0_cluster1 { +- interrupts = <432>; +- +- mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { +- ti,mbox-rx = <0 0 0>; +- ti,mbox-tx = <1 0 0>; +- }; +- +- mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { +- ti,mbox-rx = <2 0 0>; +- ti,mbox-tx = <3 0 0>; +- }; +-}; +- +-&mailbox0_cluster2 { +- interrupts = <428>; +- +- mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { +- ti,mbox-rx = <0 0 0>; +- ti,mbox-tx = <1 0 0>; +- }; +- +- mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { +- ti,mbox-rx = <2 0 0>; +- ti,mbox-tx = <3 0 0>; +- }; +-}; +- +-&mailbox0_cluster3 { +- interrupts = <424>; +- +- mbox_c66_0: mbox-c66-0 { +- ti,mbox-rx = <0 0 0>; +- ti,mbox-tx = <1 0 0>; +- }; +- +- mbox_c66_1: mbox-c66-1 { +- ti,mbox-rx = <2 0 0>; +- ti,mbox-tx = <3 0 0>; +- }; +-}; +- +-&mailbox0_cluster4 { +- interrupts = <420>; +- +- mbox_c71_0: mbox-c71-0 { +- ti,mbox-rx = <0 0 0>; +- ti,mbox-tx = <1 0 0>; +- }; +-}; +- +-&mailbox0_cluster5 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster6 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster7 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster8 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster9 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster10 { +- status = "disabled"; +-}; +- +-&mailbox0_cluster11 { +- status = "disabled"; +-}; +- +-&mcu_r5fss0_core0 { +- mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; +- memory-region = <&mcu_r5fss0_core0_dma_memory_region>, +- <&mcu_r5fss0_core0_memory_region>; +-}; +- +-&mcu_r5fss0_core1 { +- mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; +- memory-region = <&mcu_r5fss0_core1_dma_memory_region>, +- <&mcu_r5fss0_core1_memory_region>; +-}; +- +-&main_r5fss0_core0 { +- mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; +- memory-region = <&main_r5fss0_core0_dma_memory_region>, +- <&main_r5fss0_core0_memory_region>; +-}; +- +-&main_r5fss0_core1 { +- mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; +- memory-region = <&main_r5fss0_core1_dma_memory_region>, +- <&main_r5fss0_core1_memory_region>; +-}; +- +-&main_r5fss1_core0 { +- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; +- memory-region = <&main_r5fss1_core0_dma_memory_region>, +- <&main_r5fss1_core0_memory_region>; +-}; +- +-&main_r5fss1_core1 { +- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; +- memory-region = <&main_r5fss1_core1_dma_memory_region>, +- <&main_r5fss1_core1_memory_region>; +-}; +- +-&c66_0 { +- mboxes = <&mailbox0_cluster3 &mbox_c66_0>; +- memory-region = <&c66_0_dma_memory_region>, +- <&c66_0_memory_region>; +-}; +- +-&c66_1 { +- mboxes = <&mailbox0_cluster3 &mbox_c66_1>; +- memory-region = <&c66_1_dma_memory_region>, +- <&c66_1_memory_region>; +-}; +- +-&c71_0 { +- mboxes = <&mailbox0_cluster4 &mbox_c71_0>; +- memory-region = <&c71_0_dma_memory_region>, +- <&c71_0_memory_region>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/ti/k3-j721e.dtsi b/scripts/dtc/include-prefixes/arm64/ti/k3-j721e.dtsi +deleted file mode 100644 +index 69ce048a2136..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/ti/k3-j721e.dtsi ++++ /dev/null +@@ -1,184 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Device Tree Source for J721E SoC Family +- * +- * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#include +-#include +-#include +-#include +- +-/ { +- model = "Texas Instruments K3 J721E SoC"; +- compatible = "ti,j721e"; +- interrupt-parent = <&gic500>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- serial0 = &wkup_uart0; +- serial1 = &mcu_uart0; +- serial2 = &main_uart0; +- serial3 = &main_uart1; +- serial4 = &main_uart2; +- serial5 = &main_uart3; +- serial6 = &main_uart4; +- serial7 = &main_uart5; +- serial8 = &main_uart6; +- serial9 = &main_uart7; +- serial10 = &main_uart8; +- serial11 = &main_uart9; +- ethernet0 = &cpsw_port1; +- }; +- +- chosen { }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu-map { +- cluster0: cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- +- core1 { +- cpu = <&cpu1>; +- }; +- }; +- +- }; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a72"; +- reg = <0x000>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&L2_0>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a72"; +- reg = <0x001>; +- device_type = "cpu"; +- enable-method = "psci"; +- i-cache-size = <0xC000>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <0x8000>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&L2_0>; +- }; +- }; +- +- L2_0: l2-cache0 { +- compatible = "cache"; +- cache-level = <2>; +- cache-size = <0x100000>; +- cache-line-size = <64>; +- cache-sets = <1024>; +- next-level-cache = <&msmc_l3>; +- }; +- +- msmc_l3: l3-cache0 { +- compatible = "cache"; +- cache-level = <3>; +- }; +- +- firmware { +- optee { +- compatible = "linaro,optee-tz"; +- method = "smc"; +- }; +- +- psci: psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- }; +- +- a72_timer0: timer-cl0-cpu0 { +- compatible = "arm,armv8-timer"; +- interrupts = , /* cntpsirq */ +- , /* cntpnsirq */ +- , /* cntvirq */ +- ; /* cnthpirq */ +- }; +- +- pmu: pmu { +- compatible = "arm,cortex-a72-pmu"; +- /* Recommendation from GIC500 TRM Table A.3 */ +- interrupts = ; +- }; +- +- cbass_main: bus@100000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ +- <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ +- <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ +- <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ +- <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ +- <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ +- <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ +- <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ +- <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ +- <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ +- <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ +- <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ +- <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ +- <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ +- <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ +- <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ +- <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ +- <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ +- +- /* MCUSS_WKUP Range */ +- <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, +- <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, +- <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, +- <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, +- <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, +- <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, +- <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, +- <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, +- <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, +- <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, +- <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, +- <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, +- <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; +- +- cbass_mcu_wakeup: bus@28380000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ +- <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ +- <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ +- <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ +- <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ +- <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ +- <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ +- <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ +- <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ +- <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ +- <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ +- <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ +- <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ +- }; +- }; +-}; +- +-/* Now include the peripherals for each bus segments */ +-#include "k3-j721e-main.dtsi" +-#include "k3-j721e-mcu-wakeup.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/toshiba/Makefile b/scripts/dtc/include-prefixes/arm64/toshiba/Makefile +deleted file mode 100644 +index 8cd460d5b68e..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/toshiba/Makefile ++++ /dev/null +@@ -1,2 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_VISCONTI) += tmpv7708-rm-mbrc.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/toshiba/tmpv7708-rm-mbrc.dts b/scripts/dtc/include-prefixes/arm64/toshiba/tmpv7708-rm-mbrc.dts +deleted file mode 100644 +index 29a4d9fc1e47..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/toshiba/tmpv7708-rm-mbrc.dts ++++ /dev/null +@@ -1,78 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree File for TMPV7708 RM main board +- * +- * (C) Copyright 2020, Toshiba Corporation. +- * (C) Copyright 2020, Nobuhiro Iwamatsu +- */ +- +-/dts-v1/; +- +-#include "tmpv7708.dtsi" +- +-/ { +- model = "Toshiba TMPV7708 RM main board"; +- compatible = "toshiba,tmpv7708-rm-mbrc", "toshiba,tmpv7708"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- /* 768MB memory */ +- memory@80000000 { +- device_type = "memory"; +- reg = <0x0 0x80000000 0x0 0x30000000>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +- clocks = <&uart_clk>; +- clock-names = "apb_pclk"; +-}; +- +-&uart1 { +- status = "okay"; +- clocks = <&uart_clk>; +- clock-names = "apb_pclk"; +-}; +- +-&piether { +- status = "okay"; +- phy-handle = <&phy0>; +- phy-mode = "rgmii-id"; +- clocks = <&clk300mhz>, <&clk125mhz>; +- clock-names = "stmmaceth", "phy_ref_clk"; +- +- mdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy0: ethernet-phy@1 { +- device_type = "ethernet-phy"; +- reg = <0x1>; +- }; +- }; +-}; +- +-&wdt { +- status = "okay"; +- clocks = <&wdt_clk>; +-}; +- +-&gpio { +- status = "okay"; +-}; +- +-&pwm_mux { +- groups = "pwm0_gpio16_grp", "pwm1_gpio17_grp", "pwm2_gpio18_grp", "pwm3_gpio19_grp"; +-}; +- +-&pwm { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/toshiba/tmpv7708.dtsi b/scripts/dtc/include-prefixes/arm64/toshiba/tmpv7708.dtsi +deleted file mode 100644 +index 4b4231ff43cf..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/toshiba/tmpv7708.dtsi ++++ /dev/null +@@ -1,447 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Device Tree Source for the TMPV7708 +- * +- * (C) Copyright 2018 - 2020, Toshiba Corporation. +- * (C) Copyright 2020, Nobuhiro Iwamatsu +- * +- */ +- +-#include +-#include +- +-/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ +- +-/ { +- compatible = "toshiba,tmpv7708"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu0>; +- }; +- core1 { +- cpu = <&cpu1>; +- }; +- core2 { +- cpu = <&cpu2>; +- }; +- core3 { +- cpu = <&cpu3>; +- }; +- }; +- +- cluster1 { +- core0 { +- cpu = <&cpu4>; +- }; +- core1 { +- cpu = <&cpu5>; +- }; +- core2 { +- cpu = <&cpu6>; +- }; +- core3 { +- cpu = <&cpu7>; +- }; +- }; +- }; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x81100000>; +- reg = <0x00>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x81100000>; +- reg = <0x01>; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x81100000>; +- reg = <0x02>; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x81100000>; +- reg = <0x03>; +- }; +- +- cpu4: cpu@100 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x81100000>; +- reg = <0x100>; +- }; +- +- cpu5: cpu@101 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x81100000>; +- reg = <0x101>; +- }; +- +- cpu6: cpu@102 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x81100000>; +- reg = <0x102>; +- }; +- +- cpu7: cpu@103 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x81100000>; +- reg = <0x103>; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupt-parent = <&gic>; +- interrupts = +- , +- , +- , +- ; +- }; +- +- uart_clk: uart-clk { +- compatible = "fixed-clock"; +- clock-frequency = <150000000>; +- #clock-cells = <0>; +- }; +- +- clk125mhz: clk125mhz { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- #clock-cells = <0>; +- clock-output-names = "clk125mhz"; +- }; +- +- clk300mhz: clk300mhz { +- compatible = "fixed-clock"; +- clock-frequency = <300000000>; +- #clock-cells = <0>; +- clock-output-names = "clk300mhz"; +- }; +- +- wdt_clk: wdt-clk { +- compatible = "fixed-clock"; +- clock-frequency = <150000000>; +- #clock-cells = <0>; +- }; +- +- soc { +- #address-cells = <2>; +- #size-cells = <2>; +- compatible = "simple-bus"; +- interrupt-parent = <&gic>; +- ranges; +- +- gic: interrupt-controller@24001000 { +- compatible = "arm,gic-400"; +- interrupt-controller; +- #interrupt-cells = <3>; +- interrupts = ; +- reg = <0 0x24001000 0 0x1000>, +- <0 0x24002000 0 0x2000>, +- <0 0x24004000 0 0x2000>, +- <0 0x24006000 0 0x2000>; +- }; +- +- pmux: pmux@24190000 { +- compatible = "toshiba,tmpv7708-pinctrl"; +- reg = <0 0x24190000 0 0x10000>; +- }; +- +- gpio: gpio@28020000 { +- compatible = "toshiba,gpio-tmpv7708"; +- reg = <0 0x28020000 0 0x1000>; +- #gpio-cells = <0x2>; +- gpio-ranges = <&pmux 0 0 32>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupt-parent = <&gic>; +- }; +- +- uart0: serial@28200000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0 0x28200000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "disabled"; +- }; +- +- uart1: serial@28201000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0 0x28201000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart1_pins>; +- status = "disabled"; +- }; +- +- uart2: serial@28202000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0 0x28202000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "disabled"; +- }; +- +- uart3: serial@28203000 { +- compatible = "arm,pl011", "arm,primecell"; +- reg = <0 0x28203000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- status = "disabled"; +- }; +- +- i2c0: i2c@28030000 { +- compatible = "snps,designware-i2c"; +- reg = <0 0x28030000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- clock-frequency = <400000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@28031000 { +- compatible = "snps,designware-i2c"; +- reg = <0 0x28031000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- clock-frequency = <400000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@28032000 { +- compatible = "snps,designware-i2c"; +- reg = <0 0x28032000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- clock-frequency = <400000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@28033000 { +- compatible = "snps,designware-i2c"; +- reg = <0 0x28033000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- clock-frequency = <400000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@28034000 { +- compatible = "snps,designware-i2c"; +- reg = <0 0x28034000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pins>; +- clock-frequency = <400000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c5: i2c@28035000 { +- compatible = "snps,designware-i2c"; +- reg = <0 0x28035000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_pins>; +- clock-frequency = <400000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c6: i2c@28036000 { +- compatible = "snps,designware-i2c"; +- reg = <0 0x28036000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c6_pins>; +- clock-frequency = <400000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c7: i2c@28037000 { +- compatible = "snps,designware-i2c"; +- reg = <0 0x28037000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c7_pins>; +- clock-frequency = <400000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c8: i2c@28038000 { +- compatible = "snps,designware-i2c"; +- reg = <0 0x28038000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c8_pins>; +- clock-frequency = <400000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi0: spi@28140000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0 0x28140000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_pins>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi1: spi@28141000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0 0x28141000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi2: spi@28142000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0 0x28142000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pins>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi3: spi@28143000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0 0x28143000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi3_pins>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi4: spi@28144000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0 0x28144000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi4_pins>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi5: spi@28145000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0 0x28145000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi5_pins>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi6: spi@28146000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0 0x28146000 0 0x1000>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi6_pins>; +- num-cs = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- piether: ethernet@28000000 { +- compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a"; +- reg = <0 0x28000000 0 0x10000>; +- interrupts = ; +- interrupt-names = "macirq"; +- snps,txpbl = <4>; +- snps,rxpbl = <4>; +- snps,tso; +- status = "disabled"; +- }; +- +- wdt: wdt@28330000 { +- compatible = "toshiba,visconti-wdt"; +- reg = <0 0x28330000 0 0x1000>; +- status = "disabled"; +- }; +- +- pwm: pwm@241c0000 { +- compatible = "toshiba,visconti-pwm"; +- reg = <0 0x241c0000 0 0x1000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm_mux>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- }; +-}; +- +-#include "tmpv7708_pins.dtsi" +diff --git a/scripts/dtc/include-prefixes/arm64/toshiba/tmpv7708_pins.dtsi b/scripts/dtc/include-prefixes/arm64/toshiba/tmpv7708_pins.dtsi +deleted file mode 100644 +index a480c6ba5f5d..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/toshiba/tmpv7708_pins.dtsi ++++ /dev/null +@@ -1,98 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-&pmux { +- spi0_pins: spi0-pins { +- function = "spi0"; +- groups = "spi0_grp"; +- }; +- spi1_pins: spi1-pins { +- function = "spi1"; +- groups = "spi1_grp"; +- }; +- spi2_pins: spi2-pins { +- function = "spi2"; +- groups = "spi2_grp"; +- }; +- spi3_pins: spi3-pins { +- function = "spi3"; +- groups = "spi3_grp"; +- }; +- spi4_pins: spi4-pins { +- function = "spi4"; +- groups = "spi4_grp"; +- }; +- spi5_pins: spi5-pins { +- function = "spi5"; +- groups = "spi5_grp"; +- }; +- spi6_pins: spi6-pins { +- function = "spi6"; +- groups = "spi6_grp"; +- }; +- uart0_pins: uart0-pins { +- function = "uart0"; +- groups = "uart0_grp"; +- }; +- uart1_pins: uart1-pins { +- function = "uart1"; +- groups = "uart1_grp"; +- }; +- uart2_pins: uart2-pins { +- function = "uart2"; +- groups = "uart2_grp"; +- }; +- uart3_pins: uart3-pins { +- function = "uart3"; +- groups = "uart3_grp"; +- }; +- i2c0_pins: i2c0-pins { +- function = "i2c0"; +- groups = "i2c0_grp"; +- bias-pull-up; +- }; +- i2c1_pins: i2c1-pins { +- function = "i2c1"; +- groups = "i2c1_grp"; +- bias-pull-up; +- }; +- i2c2_pins: i2c2-pins { +- function = "i2c2"; +- groups = "i2c2_grp"; +- bias-pull-up; +- }; +- i2c3_pins: i2c3-pins { +- function = "i2c3"; +- groups = "i2c3_grp"; +- bias-pull-up; +- }; +- i2c4_pins: i2c4-pins { +- function = "i2c4"; +- groups = "i2c4_grp"; +- bias-pull-up; +- }; +- i2c5_pins: i2c5-pins { +- function = "i2c5"; +- groups = "i2c5_grp"; +- bias-pull-up; +- }; +- i2c6_pins: i2c6-pins { +- function = "i2c6"; +- groups = "i2c6_grp"; +- bias-pull-up; +- }; +- i2c7_pins: i2c7-pins { +- function = "i2c7"; +- groups = "i2c7_grp"; +- bias-pull-up; +- }; +- i2c8_pins: i2c8-pins { +- function = "i2c8"; +- groups = "i2c8_grp"; +- bias-pull-up; +- }; +- +- pwm_mux: pwm_mux { +- function = "pwm"; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/Makefile b/scripts/dtc/include-prefixes/arm64/xilinx/Makefile +deleted file mode 100644 +index 11fb4fd3ebd4..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/Makefile ++++ /dev/null +@@ -1,18 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_ZYNQMP) += avnet-ultra96-rev1.dtb +-dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb +-dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb +-dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb +-dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm015-dc1.dtb +-dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm016-dc2.dtb +-dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm017-dc3.dtb +-dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm018-dc4.dtb +-dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm019-dc5.dtb +-dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb +-dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb +-dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb +-dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb +-dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb +-dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revC.dtb +-dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb +-dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/avnet-ultra96-rev1.dts b/scripts/dtc/include-prefixes/arm64/xilinx/avnet-ultra96-rev1.dts +deleted file mode 100644 +index 88aa06fa78a8..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/avnet-ultra96-rev1.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * dts file for Avnet Ultra96 rev1 +- * +- * (C) Copyright 2018, Xilinx, Inc. +- * +- * Michal Simek +- */ +- +-/dts-v1/; +- +-#include "zynqmp-zcu100-revC.dts" +- +-/ { +- model = "Avnet Ultra96 Rev1"; +- compatible = "avnet,ultra96-rev1", "avnet,ultra96", +- "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", +- "xlnx,zynqmp"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-clk-ccf.dtsi b/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-clk-ccf.dtsi +deleted file mode 100644 +index cf5295224750..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-clk-ccf.dtsi ++++ /dev/null +@@ -1,239 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Clock specification for Xilinx ZynqMP +- * +- * (C) Copyright 2017 - 2019, Xilinx, Inc. +- * +- * Michal Simek +- */ +- +-#include +-/ { +- pss_ref_clk: pss_ref_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <33333333>; +- }; +- +- video_clk: video_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- }; +- +- pss_alt_ref_clk: pss_alt_ref_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <0>; +- }; +- +- gt_crx_ref_clk: gt_crx_ref_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <108000000>; +- }; +- +- aux_ref_clk: aux_ref_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- }; +-}; +- +-&can0 { +- clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&can1 { +- clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&cpu0 { +- clocks = <&zynqmp_clk ACPU>; +-}; +- +-&fpd_dma_chan1 { +- clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&fpd_dma_chan2 { +- clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&fpd_dma_chan3 { +- clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&fpd_dma_chan4 { +- clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&fpd_dma_chan5 { +- clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&fpd_dma_chan6 { +- clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&fpd_dma_chan7 { +- clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&fpd_dma_chan8 { +- clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&lpd_dma_chan1 { +- clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&lpd_dma_chan2 { +- clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&lpd_dma_chan3 { +- clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&lpd_dma_chan4 { +- clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&lpd_dma_chan5 { +- clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&lpd_dma_chan6 { +- clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&lpd_dma_chan7 { +- clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&lpd_dma_chan8 { +- clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&nand0 { +- clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&gem0 { +- clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, +- <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, +- <&zynqmp_clk GEM_TSU>; +- clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; +-}; +- +-&gem1 { +- clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, +- <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, +- <&zynqmp_clk GEM_TSU>; +- clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; +-}; +- +-&gem2 { +- clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, +- <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, +- <&zynqmp_clk GEM_TSU>; +- clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; +-}; +- +-&gem3 { +- clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, +- <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, +- <&zynqmp_clk GEM_TSU>; +- clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; +-}; +- +-&gpio { +- clocks = <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&i2c0 { +- clocks = <&zynqmp_clk I2C0_REF>; +-}; +- +-&i2c1 { +- clocks = <&zynqmp_clk I2C1_REF>; +-}; +- +-&pcie { +- clocks = <&zynqmp_clk PCIE_REF>; +-}; +- +-&qspi { +- clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&sata { +- clocks = <&zynqmp_clk SATA_REF>; +-}; +- +-&sdhci0 { +- clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&sdhci1 { +- clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&spi0 { +- clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&spi1 { +- clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&ttc0 { +- clocks = <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&ttc1 { +- clocks = <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&ttc2 { +- clocks = <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&ttc3 { +- clocks = <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&uart0 { +- clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&uart1 { +- clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; +-}; +- +-&usb0 { +- clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; +-}; +- +-&usb1 { +- clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; +-}; +- +-&watchdog0 { +- clocks = <&zynqmp_clk WDT>; +-}; +- +-&lpd_watchdog { +- clocks = <&zynqmp_clk LPD_WDT>; +-}; +- +-&zynqmp_dpdma { +- clocks = <&zynqmp_clk DPDMA_REF>; +-}; +- +-&zynqmp_dpsub { +- clocks = <&zynqmp_clk TOPSW_LSBUS>, +- <&zynqmp_clk DP_AUDIO_REF>, +- <&zynqmp_clk DP_VIDEO_REF>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1232-revA.dts b/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1232-revA.dts +deleted file mode 100644 +index 2e05fa416955..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1232-revA.dts ++++ /dev/null +@@ -1,54 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * dts file for Xilinx ZynqMP ZC1232 +- * +- * (C) Copyright 2017 - 2019, Xilinx, Inc. +- * +- * Michal Simek +- */ +- +-/dts-v1/; +- +-#include "zynqmp.dtsi" +-#include "zynqmp-clk-ccf.dtsi" +- +-/ { +- model = "ZynqMP ZC1232 RevA"; +- compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &dcc; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +-}; +- +-&dcc { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +- /* SATA OOB timing settings */ +- ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; +- ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; +- ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; +- ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +- ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; +- ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; +- ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; +- ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1254-revA.dts b/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1254-revA.dts +deleted file mode 100644 +index 3d0aaa02f184..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1254-revA.dts ++++ /dev/null +@@ -1,42 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * dts file for Xilinx ZynqMP ZC1254 +- * +- * (C) Copyright 2015 - 2019, Xilinx, Inc. +- * +- * Michal Simek +- * Siva Durga Prasad Paladugu +- */ +- +-/dts-v1/; +- +-#include "zynqmp.dtsi" +-#include "zynqmp-clk-ccf.dtsi" +- +-/ { +- model = "ZynqMP ZC1254 RevA"; +- compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &dcc; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +-}; +- +-&dcc { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1275-revA.dts b/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1275-revA.dts +deleted file mode 100644 +index 66a90483b004..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1275-revA.dts ++++ /dev/null +@@ -1,42 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * dts file for Xilinx ZynqMP ZC1275 +- * +- * (C) Copyright 2017 - 2019, Xilinx, Inc. +- * +- * Michal Simek +- * Siva Durga Prasad Paladugu +- */ +- +-/dts-v1/; +- +-#include "zynqmp.dtsi" +-#include "zynqmp-clk-ccf.dtsi" +- +-/ { +- model = "ZynqMP ZC1275 RevA"; +- compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &dcc; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +-}; +- +-&dcc { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts b/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts +deleted file mode 100644 +index 69f6e4610739..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts ++++ /dev/null +@@ -1,132 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * dts file for Xilinx ZynqMP zc1751-xm015-dc1 +- * +- * (C) Copyright 2015 - 2019, Xilinx, Inc. +- * +- * Michal Simek +- */ +- +-/dts-v1/; +- +-#include "zynqmp.dtsi" +-#include "zynqmp-clk-ccf.dtsi" +-#include +- +-/ { +- model = "ZynqMP zc1751-xm015-dc1 RevA"; +- compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; +- +- aliases { +- ethernet0 = &gem3; +- i2c0 = &i2c1; +- mmc0 = &sdhci0; +- mmc1 = &sdhci1; +- rtc0 = &rtc; +- serial0 = &uart0; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; +- }; +-}; +- +-&fpd_dma_chan1 { +- status = "okay"; +-}; +- +-&fpd_dma_chan2 { +- status = "okay"; +-}; +- +-&fpd_dma_chan3 { +- status = "okay"; +-}; +- +-&fpd_dma_chan4 { +- status = "okay"; +-}; +- +-&fpd_dma_chan5 { +- status = "okay"; +-}; +- +-&fpd_dma_chan6 { +- status = "okay"; +-}; +- +-&fpd_dma_chan7 { +- status = "okay"; +-}; +- +-&fpd_dma_chan8 { +- status = "okay"; +-}; +- +-&gem3 { +- status = "okay"; +- phy-handle = <&phy0>; +- phy-mode = "rgmii-id"; +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&gpio { +- status = "okay"; +-}; +- +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- eeprom: eeprom@55 { +- compatible = "atmel,24c64"; /* 24AA64 */ +- reg = <0x55>; +- }; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +- /* SATA phy OOB timing settings */ +- ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; +- ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; +- ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; +- ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +- ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; +- ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; +- ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; +- ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +-}; +- +-/* eMMC */ +-&sdhci0 { +- status = "okay"; +- bus-width = <8>; +-}; +- +-/* SD1 with level shifter */ +-&sdhci1 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-/* ULPI SMSC USB3320 */ +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts b/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts +deleted file mode 100644 +index f7124e15f0ff..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts ++++ /dev/null +@@ -1,170 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * dts file for Xilinx ZynqMP zc1751-xm016-dc2 +- * +- * (C) Copyright 2015 - 2019, Xilinx, Inc. +- * +- * Michal Simek +- */ +- +-/dts-v1/; +- +-#include "zynqmp.dtsi" +-#include "zynqmp-clk-ccf.dtsi" +-#include +- +-/ { +- model = "ZynqMP zc1751-xm016-dc2 RevA"; +- compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; +- +- aliases { +- can0 = &can0; +- can1 = &can1; +- ethernet0 = &gem2; +- i2c0 = &i2c0; +- rtc0 = &rtc; +- serial0 = &uart0; +- serial1 = &uart1; +- spi0 = &spi0; +- spi1 = &spi1; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; +- }; +-}; +- +-&can0 { +- status = "okay"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&fpd_dma_chan1 { +- status = "okay"; +-}; +- +-&fpd_dma_chan2 { +- status = "okay"; +-}; +- +-&fpd_dma_chan3 { +- status = "okay"; +-}; +- +-&fpd_dma_chan4 { +- status = "okay"; +-}; +- +-&fpd_dma_chan5 { +- status = "okay"; +-}; +- +-&fpd_dma_chan6 { +- status = "okay"; +-}; +- +-&fpd_dma_chan7 { +- status = "okay"; +-}; +- +-&fpd_dma_chan8 { +- status = "okay"; +-}; +- +-&gem2 { +- status = "okay"; +- phy-handle = <&phy0>; +- phy-mode = "rgmii-id"; +- phy0: ethernet-phy@5 { +- reg = <5>; +- ti,rx-internal-delay = <0x8>; +- ti,tx-internal-delay = <0xa>; +- ti,fifo-depth = <0x1>; +- ti,dp83867-rxctrl-strap-quirk; +- }; +-}; +- +-&gpio { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <400000>; +- +- tca6416_u26: gpio@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- /* IRQ not connected */ +- }; +- +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&spi0 { +- status = "okay"; +- num-cs = <1>; +- +- spi0_flash0: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "sst,sst25wf080", "jedec,spi-nor"; +- spi-max-frequency = <50000000>; +- reg = <0>; +- +- partition@0 { +- label = "spi0-data"; +- reg = <0x0 0x100000>; +- }; +- }; +-}; +- +-&spi1 { +- status = "okay"; +- num-cs = <1>; +- +- spi1_flash0: flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- +- partition@0 { +- label = "spi1-data"; +- reg = <0x0 0x84000>; +- }; +- }; +-}; +- +-/* ULPI SMSC USB3320 */ +-&usb1 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1751-xm017-dc3.dts b/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1751-xm017-dc3.dts +deleted file mode 100644 +index 4ea6ef5a7f2b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1751-xm017-dc3.dts ++++ /dev/null +@@ -1,150 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * dts file for Xilinx ZynqMP zc1751-xm017-dc3 +- * +- * (C) Copyright 2016 - 2019, Xilinx, Inc. +- * +- * Michal Simek +- */ +- +-/dts-v1/; +- +-#include "zynqmp.dtsi" +-#include "zynqmp-clk-ccf.dtsi" +- +-/ { +- model = "ZynqMP zc1751-xm017-dc3 RevA"; +- compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; +- +- aliases { +- ethernet0 = &gem0; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- mmc0 = &sdhci1; +- rtc0 = &rtc; +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; +- }; +-}; +- +-&fpd_dma_chan1 { +- status = "okay"; +-}; +- +-&fpd_dma_chan2 { +- status = "okay"; +-}; +- +-&fpd_dma_chan3 { +- status = "okay"; +-}; +- +-&fpd_dma_chan4 { +- status = "okay"; +-}; +- +-&fpd_dma_chan5 { +- status = "okay"; +-}; +- +-&fpd_dma_chan6 { +- status = "okay"; +-}; +- +-&fpd_dma_chan7 { +- status = "okay"; +-}; +- +-&fpd_dma_chan8 { +- status = "okay"; +-}; +- +-&gem0 { +- status = "okay"; +- phy-handle = <&phy0>; +- phy-mode = "rgmii-id"; +- phy0: ethernet-phy@0 { /* VSC8211 */ +- reg = <0>; +- }; +-}; +- +-&gpio { +- status = "okay"; +-}; +- +-/* just eeprom here */ +-&i2c0 { +- status = "okay"; +- clock-frequency = <400000>; +- +- tca6416_u26: gpio@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- /* IRQ not connected */ +- }; +- +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +-}; +- +-/* eeprom24c02 and SE98A temp chip pca9306 */ +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +- /* SATA phy OOB timing settings */ +- ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; +- ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; +- ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; +- ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +- ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; +- ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; +- ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; +- ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +-}; +- +-&sdhci1 { /* emmc with some settings */ +- status = "okay"; +-}; +- +-/* main */ +-&uart0 { +- status = "okay"; +-}; +- +-/* DB9 */ +-&uart1 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-/* ULPI SMSC USB3320 */ +-&usb1 { +- status = "okay"; +- dr_mode = "host"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1751-xm018-dc4.dts b/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1751-xm018-dc4.dts +deleted file mode 100644 +index 2366cd9f091a..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1751-xm018-dc4.dts ++++ /dev/null +@@ -1,178 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * dts file for Xilinx ZynqMP zc1751-xm018-dc4 +- * +- * (C) Copyright 2015 - 2019, Xilinx, Inc. +- * +- * Michal Simek +- */ +- +-/dts-v1/; +- +-#include "zynqmp.dtsi" +-#include "zynqmp-clk-ccf.dtsi" +- +-/ { +- model = "ZynqMP zc1751-xm018-dc4"; +- compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; +- +- aliases { +- ethernet0 = &gem0; +- ethernet1 = &gem1; +- ethernet2 = &gem2; +- ethernet3 = &gem3; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- rtc0 = &rtc; +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; +- }; +-}; +- +-&can0 { +- status = "okay"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&fpd_dma_chan1 { +- status = "okay"; +-}; +- +-&fpd_dma_chan2 { +- status = "okay"; +-}; +- +-&fpd_dma_chan3 { +- status = "okay"; +-}; +- +-&fpd_dma_chan4 { +- status = "okay"; +-}; +- +-&fpd_dma_chan5 { +- status = "okay"; +-}; +- +-&fpd_dma_chan6 { +- status = "okay"; +-}; +- +-&fpd_dma_chan7 { +- status = "okay"; +-}; +- +-&fpd_dma_chan8 { +- status = "okay"; +-}; +- +-&lpd_dma_chan1 { +- status = "okay"; +-}; +- +-&lpd_dma_chan2 { +- status = "okay"; +-}; +- +-&lpd_dma_chan3 { +- status = "okay"; +-}; +- +-&lpd_dma_chan4 { +- status = "okay"; +-}; +- +-&lpd_dma_chan5 { +- status = "okay"; +-}; +- +-&lpd_dma_chan6 { +- status = "okay"; +-}; +- +-&lpd_dma_chan7 { +- status = "okay"; +-}; +- +-&lpd_dma_chan8 { +- status = "okay"; +-}; +- +-&gem0 { +- status = "okay"; +- phy-mode = "rgmii-id"; +- phy-handle = <ðernet_phy0>; +- ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ +- reg = <0>; +- }; +- ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ +- reg = <7>; +- }; +- ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ +- reg = <3>; +- }; +- ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ +- reg = <8>; +- }; +-}; +- +-&gem1 { +- status = "okay"; +- phy-mode = "rgmii-id"; +- phy-handle = <ðernet_phy7>; +-}; +- +-&gem2 { +- status = "okay"; +- phy-mode = "rgmii-id"; +- phy-handle = <ðernet_phy3>; +-}; +- +-&gem3 { +- status = "okay"; +- phy-mode = "rgmii-id"; +- phy-handle = <ðernet_phy8>; +-}; +- +-&gpio { +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <400000>; +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&watchdog0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts b/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts +deleted file mode 100644 +index 41934e3525c6..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts ++++ /dev/null +@@ -1,125 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * dts file for Xilinx ZynqMP zc1751-xm019-dc5 +- * +- * (C) Copyright 2015 - 2019, Xilinx, Inc. +- * +- * Siva Durga Prasad +- * Michal Simek +- */ +- +-/dts-v1/; +- +-#include "zynqmp.dtsi" +-#include "zynqmp-clk-ccf.dtsi" +-#include +- +-/ { +- model = "ZynqMP zc1751-xm019-dc5 RevA"; +- compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; +- +- aliases { +- ethernet0 = &gem1; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- mmc0 = &sdhci0; +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; +- }; +-}; +- +-&fpd_dma_chan1 { +- status = "okay"; +-}; +- +-&fpd_dma_chan2 { +- status = "okay"; +-}; +- +-&fpd_dma_chan3 { +- status = "okay"; +-}; +- +-&fpd_dma_chan4 { +- status = "okay"; +-}; +- +-&fpd_dma_chan5 { +- status = "okay"; +-}; +- +-&fpd_dma_chan6 { +- status = "okay"; +-}; +- +-&fpd_dma_chan7 { +- status = "okay"; +-}; +- +-&fpd_dma_chan8 { +- status = "okay"; +-}; +- +-&gem1 { +- status = "okay"; +- phy-handle = <&phy0>; +- phy-mode = "rgmii-id"; +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +-}; +- +-&gpio { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&sdhci0 { +- status = "okay"; +- no-1-8-v; +-}; +- +-&ttc0 { +- status = "okay"; +-}; +- +-&ttc1 { +- status = "okay"; +-}; +- +-&ttc2 { +- status = "okay"; +-}; +- +-&ttc3 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&watchdog0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu100-revC.dts b/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu100-revC.dts +deleted file mode 100644 +index a53598c3624b..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu100-revC.dts ++++ /dev/null +@@ -1,328 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * dts file for Xilinx ZynqMP ZCU100 revC +- * +- * (C) Copyright 2016 - 2019, Xilinx, Inc. +- * +- * Michal Simek +- * Nathalie Chan King Choy +- */ +- +-/dts-v1/; +- +-#include "zynqmp.dtsi" +-#include "zynqmp-clk-ccf.dtsi" +-#include +-#include +-#include +-#include +- +-/ { +- model = "ZynqMP ZCU100 RevC"; +- compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; +- +- aliases { +- i2c0 = &i2c1; +- rtc0 = &rtc; +- serial0 = &uart1; +- serial1 = &uart0; +- serial2 = &dcc; +- spi0 = &spi0; +- spi1 = &spi1; +- mmc0 = &sdhci0; +- mmc1 = &sdhci1; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- sw4 { +- label = "sw4"; +- gpios = <&gpio 23 GPIO_ACTIVE_LOW>; +- linux,code = ; +- wakeup-source; +- autorepeat; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-ds2 { +- label = "ds2"; +- gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led-ds3 { +- label = "ds3"; +- gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "phy0tx"; /* WLAN tx */ +- default-state = "off"; +- }; +- +- led-ds4 { +- label = "ds4"; +- gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "phy0rx"; /* WLAN rx */ +- default-state = "off"; +- }; +- +- led-ds5 { +- label = "ds5"; +- gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "bluetooth-power"; +- }; +- +- vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ +- label = "vbus_det"; +- gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- wmmcsdio_fixed: fixedregulator-mmcsdio { +- compatible = "regulator-fixed"; +- regulator-name = "wmmcsdio_fixed"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ +- post-power-on-delay-ms = <10>; +- }; +- +- ina226 { +- compatible = "iio-hwmon"; +- io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; +- }; +- +- si5335a_0: clk26 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +- +- si5335a_1: clk27 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- }; +-}; +- +-&dcc { +- status = "okay"; +-}; +- +-&gpio { +- status = "okay"; +- gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", +- "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", +- "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", +- "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", +- "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", +- "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", +- "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", +- "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", +- "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", +- "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", +- "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", +- "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", +- "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", +- "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", +- "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", +- "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ +- "", "", +- "", "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", "", "", +- "", "", "", ""; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <100000>; +- i2c-mux@75 { /* u11 */ +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x75>; +- i2csw_0: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- label = "LS-I2C0"; +- }; +- i2csw_1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- label = "LS-I2C1"; +- }; +- i2csw_2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- label = "HS-I2C2"; +- }; +- i2csw_3: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- label = "HS-I2C3"; +- }; +- i2csw_4: i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x4>; +- +- pmic: pmic@5e { /* Custom TI PMIC u33 */ +- compatible = "ti,tps65086"; +- reg = <0x5e>; +- interrupt-parent = <&gpio>; +- interrupts = <77 IRQ_TYPE_LEVEL_LOW>; +- #gpio-cells = <2>; +- gpio-controller; +- }; +- }; +- i2csw_5: i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- /* PS_PMBUS */ +- u35: ina226@40 { /* u35 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- reg = <0x40>; +- shunt-resistor = <10000>; +- /* MIO31 is alert which should be routed to PMUFW */ +- }; +- }; +- i2csw_6: i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- /* +- * Not Connected +- */ +- }; +- i2csw_7: i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- /* +- * usb5744 (DNP) - U5 +- * 100kHz - this is default freq for us +- */ +- }; +- }; +-}; +- +-&psgtr { +- status = "okay"; +- /* usb3, dps */ +- clocks = <&si5335a_0>, <&si5335a_1>; +- clock-names = "ref0", "ref1"; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-/* SD0 only supports 3.3V, no level shifter */ +-&sdhci0 { +- status = "okay"; +- no-1-8-v; +- disable-wp; +- xlnx,mio-bank = <0>; +-}; +- +-&sdhci1 { +- status = "okay"; +- bus-width = <0x4>; +- xlnx,mio-bank = <0>; +- non-removable; +- disable-wp; +- cap-power-off-card; +- mmc-pwrseq = <&sdio_pwrseq>; +- vqmmc-supply = <&wmmcsdio_fixed>; +- #address-cells = <1>; +- #size-cells = <0>; +- wlcore: wifi@2 { +- compatible = "ti,wl1831"; +- reg = <2>; +- interrupt-parent = <&gpio>; +- interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ +- }; +-}; +- +-&spi0 { /* Low Speed connector */ +- status = "okay"; +- label = "LS-SPI0"; +- num-cs = <1>; +-}; +- +-&spi1 { /* High Speed connector */ +- status = "okay"; +- label = "HS-SPI1"; +- num-cs = <1>; +-}; +- +-&uart0 { +- status = "okay"; +- bluetooth { +- compatible = "ti,wl1831-st"; +- enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&uart1 { +- status = "okay"; +- +-}; +- +-/* ULPI SMSC USB3320 */ +-&usb0 { +- status = "okay"; +- dr_mode = "peripheral"; +-}; +- +-/* ULPI SMSC USB3320 */ +-&usb1 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&watchdog0 { +- status = "okay"; +-}; +- +-&zynqmp_dpdma { +- status = "okay"; +-}; +- +-&zynqmp_dpsub { +- status = "okay"; +- phy-names = "dp-phy0", "dp-phy1"; +- phys = <&psgtr 1 PHY_TYPE_DP 0 1>, +- <&psgtr 0 PHY_TYPE_DP 1 1>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu102-rev1.0.dts b/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu102-rev1.0.dts +deleted file mode 100644 +index 6647e97edba3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu102-rev1.0.dts ++++ /dev/null +@@ -1,36 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * dts file for Xilinx ZynqMP ZCU102 Rev1.0 +- * +- * (C) Copyright 2016 - 2018, Xilinx, Inc. +- * +- * Michal Simek +- */ +- +-#include "zynqmp-zcu102-revB.dts" +- +-/ { +- model = "ZynqMP ZCU102 Rev1.0"; +- compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; +-}; +- +-&eeprom { +- #address-cells = <1>; +- #size-cells = <1>; +- +- board_sn: board-sn@0 { +- reg = <0x0 0x14>; +- }; +- +- eth_mac: eth-mac@20 { +- reg = <0x20 0x6>; +- }; +- +- board_name: board-name@d0 { +- reg = <0xd0 0x6>; +- }; +- +- board_revision: board-revision@e0 { +- reg = <0xe0 0x3>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu102-revA.dts b/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu102-revA.dts +deleted file mode 100644 +index eca6c2de84a7..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu102-revA.dts ++++ /dev/null +@@ -1,708 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * dts file for Xilinx ZynqMP ZCU102 RevA +- * +- * (C) Copyright 2015 - 2019, Xilinx, Inc. +- * +- * Michal Simek +- */ +- +-/dts-v1/; +- +-#include "zynqmp.dtsi" +-#include "zynqmp-clk-ccf.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "ZynqMP ZCU102 RevA"; +- compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; +- +- aliases { +- ethernet0 = &gem3; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- mmc0 = &sdhci1; +- rtc0 = &rtc; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &dcc; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- sw19 { +- label = "sw19"; +- gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- wakeup-source; +- autorepeat; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- heartbeat-led { +- label = "heartbeat"; +- gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- ina226-u76 { +- compatible = "iio-hwmon"; +- io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; +- }; +- ina226-u77 { +- compatible = "iio-hwmon"; +- io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; +- }; +- ina226-u78 { +- compatible = "iio-hwmon"; +- io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; +- }; +- ina226-u87 { +- compatible = "iio-hwmon"; +- io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; +- }; +- ina226-u85 { +- compatible = "iio-hwmon"; +- io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; +- }; +- ina226-u86 { +- compatible = "iio-hwmon"; +- io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; +- }; +- ina226-u93 { +- compatible = "iio-hwmon"; +- io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; +- }; +- ina226-u88 { +- compatible = "iio-hwmon"; +- io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; +- }; +- ina226-u15 { +- compatible = "iio-hwmon"; +- io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; +- }; +- ina226-u92 { +- compatible = "iio-hwmon"; +- io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; +- }; +- ina226-u79 { +- compatible = "iio-hwmon"; +- io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; +- }; +- ina226-u81 { +- compatible = "iio-hwmon"; +- io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; +- }; +- ina226-u80 { +- compatible = "iio-hwmon"; +- io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; +- }; +- ina226-u84 { +- compatible = "iio-hwmon"; +- io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; +- }; +- ina226-u16 { +- compatible = "iio-hwmon"; +- io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; +- }; +- ina226-u65 { +- compatible = "iio-hwmon"; +- io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; +- }; +- ina226-u74 { +- compatible = "iio-hwmon"; +- io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; +- }; +- ina226-u75 { +- compatible = "iio-hwmon"; +- io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; +- }; +- +- /* 48MHz reference crystal */ +- ref48: ref48M { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <48000000>; +- }; +- +- refhdmi: refhdmi { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <114285000>; +- }; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&dcc { +- status = "okay"; +-}; +- +-&fpd_dma_chan1 { +- status = "okay"; +-}; +- +-&fpd_dma_chan2 { +- status = "okay"; +-}; +- +-&fpd_dma_chan3 { +- status = "okay"; +-}; +- +-&fpd_dma_chan4 { +- status = "okay"; +-}; +- +-&fpd_dma_chan5 { +- status = "okay"; +-}; +- +-&fpd_dma_chan6 { +- status = "okay"; +-}; +- +-&fpd_dma_chan7 { +- status = "okay"; +-}; +- +-&fpd_dma_chan8 { +- status = "okay"; +-}; +- +-&gem3 { +- status = "okay"; +- phy-handle = <&phy0>; +- phy-mode = "rgmii-id"; +- phy0: ethernet-phy@21 { +- reg = <21>; +- ti,rx-internal-delay = <0x8>; +- ti,tx-internal-delay = <0xa>; +- ti,fifo-depth = <0x1>; +- ti,dp83867-rxctrl-strap-quirk; +- }; +-}; +- +-&gpio { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <400000>; +- +- tca6416_u97: gpio@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- gpio-controller; /* IRQ not connected */ +- #gpio-cells = <2>; +- gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", +- "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", +- "", "", "", "", "", "", "", "", ""; +- gtr-sel0-hog { +- gpio-hog; +- gpios = <0 0>; +- output-low; /* PCIE = 0, DP = 1 */ +- line-name = "sel0"; +- }; +- gtr-sel1-hog { +- gpio-hog; +- gpios = <1 0>; +- output-high; /* PCIE = 0, DP = 1 */ +- line-name = "sel1"; +- }; +- gtr-sel2-hog { +- gpio-hog; +- gpios = <2 0>; +- output-high; /* PCIE = 0, USB0 = 1 */ +- line-name = "sel2"; +- }; +- gtr-sel3-hog { +- gpio-hog; +- gpios = <3 0>; +- output-high; /* PCIE = 0, SATA = 1 */ +- line-name = "sel3"; +- }; +- }; +- +- tca6416_u61: gpio@21 { +- compatible = "ti,tca6416"; +- reg = <0x21>; +- gpio-controller; /* IRQ not connected */ +- #gpio-cells = <2>; +- gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", +- "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", +- "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", +- "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; +- }; +- +- i2c-mux@75 { /* u60 */ +- compatible = "nxp,pca9544"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x75>; +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- /* PS_PMBUS */ +- u76: ina226@40 { /* u76 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u76"; +- reg = <0x40>; +- shunt-resistor = <5000>; +- }; +- u77: ina226@41 { /* u77 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u77"; +- reg = <0x41>; +- shunt-resistor = <5000>; +- }; +- u78: ina226@42 { /* u78 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u78"; +- reg = <0x42>; +- shunt-resistor = <5000>; +- }; +- u87: ina226@43 { /* u87 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u87"; +- reg = <0x43>; +- shunt-resistor = <5000>; +- }; +- u85: ina226@44 { /* u85 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u85"; +- reg = <0x44>; +- shunt-resistor = <5000>; +- }; +- u86: ina226@45 { /* u86 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u86"; +- reg = <0x45>; +- shunt-resistor = <5000>; +- }; +- u93: ina226@46 { /* u93 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u93"; +- reg = <0x46>; +- shunt-resistor = <5000>; +- }; +- u88: ina226@47 { /* u88 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u88"; +- reg = <0x47>; +- shunt-resistor = <5000>; +- }; +- u15: ina226@4a { /* u15 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u15"; +- reg = <0x4a>; +- shunt-resistor = <5000>; +- }; +- u92: ina226@4b { /* u92 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u92"; +- reg = <0x4b>; +- shunt-resistor = <5000>; +- }; +- }; +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- /* PL_PMBUS */ +- u79: ina226@40 { /* u79 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u79"; +- reg = <0x40>; +- shunt-resistor = <2000>; +- }; +- u81: ina226@41 { /* u81 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u81"; +- reg = <0x41>; +- shunt-resistor = <5000>; +- }; +- u80: ina226@42 { /* u80 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u80"; +- reg = <0x42>; +- shunt-resistor = <5000>; +- }; +- u84: ina226@43 { /* u84 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u84"; +- reg = <0x43>; +- shunt-resistor = <5000>; +- }; +- u16: ina226@44 { /* u16 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u16"; +- reg = <0x44>; +- shunt-resistor = <5000>; +- }; +- u65: ina226@45 { /* u65 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u65"; +- reg = <0x45>; +- shunt-resistor = <5000>; +- }; +- u74: ina226@46 { /* u74 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u74"; +- reg = <0x46>; +- shunt-resistor = <5000>; +- }; +- u75: ina226@47 { /* u75 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u75"; +- reg = <0x47>; +- shunt-resistor = <5000>; +- }; +- }; +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- /* MAXIM_PMBUS - 00 */ +- max15301@a { /* u46 */ +- compatible = "maxim,max15301"; +- reg = <0xa>; +- }; +- max15303@b { /* u4 */ +- compatible = "maxim,max15303"; +- reg = <0xb>; +- }; +- max15303@10 { /* u13 */ +- compatible = "maxim,max15303"; +- reg = <0x10>; +- }; +- max15301@13 { /* u47 */ +- compatible = "maxim,max15301"; +- reg = <0x13>; +- }; +- max15303@14 { /* u7 */ +- compatible = "maxim,max15303"; +- reg = <0x14>; +- }; +- max15303@15 { /* u6 */ +- compatible = "maxim,max15303"; +- reg = <0x15>; +- }; +- max15303@16 { /* u10 */ +- compatible = "maxim,max15303"; +- reg = <0x16>; +- }; +- max15303@17 { /* u9 */ +- compatible = "maxim,max15303"; +- reg = <0x17>; +- }; +- max15301@18 { /* u63 */ +- compatible = "maxim,max15301"; +- reg = <0x18>; +- }; +- max15303@1a { /* u49 */ +- compatible = "maxim,max15303"; +- reg = <0x1a>; +- }; +- max15303@1d { /* u18 */ +- compatible = "maxim,max15303"; +- reg = <0x1d>; +- }; +- max15303@20 { /* u8 */ +- compatible = "maxim,max15303"; +- status = "disabled"; /* unreachable */ +- reg = <0x20>; +- }; +- +- max20751@72 { /* u95 */ +- compatible = "maxim,max20751"; +- reg = <0x72>; +- }; +- max20751@73 { /* u96 */ +- compatible = "maxim,max20751"; +- reg = <0x73>; +- }; +- }; +- /* Bus 3 is not connected */ +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- /* PL i2c via PCA9306 - u45 */ +- i2c-mux@74 { /* u34 */ +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x74>; +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- /* +- * IIC_EEPROM 1kB memory which uses 256B blocks +- * where every block has different address. +- * 0 - 256B address 0x54 +- * 256B - 512B address 0x55 +- * 512B - 768B address 0x56 +- * 768B - 1024B address 0x57 +- */ +- eeprom: eeprom@54 { /* u23 */ +- compatible = "atmel,24c08"; +- reg = <0x54>; +- }; +- }; +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- si5341: clock-generator@36 { /* SI5341 - u69 */ +- compatible = "silabs,si5341"; +- reg = <0x36>; +- #clock-cells = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&ref48>; +- clock-names = "xtal"; +- clock-output-names = "si5341"; +- +- si5341_0: out@0 { +- /* refclk0 for PS-GT, used for DP */ +- reg = <0>; +- always-on; +- }; +- si5341_2: out@2 { +- /* refclk2 for PS-GT, used for USB3 */ +- reg = <2>; +- always-on; +- }; +- si5341_3: out@3 { +- /* refclk3 for PS-GT, used for SATA */ +- reg = <3>; +- always-on; +- }; +- si5341_4: out@4 { +- /* refclk4 for PS-GT, used for PCIE slot */ +- reg = <4>; +- always-on; +- }; +- si5341_5: out@5 { +- /* refclk5 for PS-GT, used for PCIE */ +- reg = <5>; +- always-on; +- }; +- si5341_6: out@6 { +- /* refclk6 PL CLK125 */ +- reg = <6>; +- always-on; +- }; +- si5341_7: out@7 { +- /* refclk7 PL CLK74 */ +- reg = <7>; +- always-on; +- }; +- si5341_9: out@9 { +- /* refclk9 used for PS_REF_CLK 33.3 MHz */ +- reg = <9>; +- always-on; +- }; +- }; +- }; +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- si570_1: clock-generator@5d { /* USER SI570 - u42 */ +- #clock-cells = <0>; +- compatible = "silabs,si570"; +- reg = <0x5d>; +- temperature-stability = <50>; +- factory-fout = <300000000>; +- clock-frequency = <300000000>; +- clock-output-names = "si570_user"; +- }; +- }; +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ +- #clock-cells = <0>; +- compatible = "silabs,si570"; +- reg = <0x5d>; +- temperature-stability = <50>; /* copy from zc702 */ +- factory-fout = <156250000>; +- clock-frequency = <148500000>; +- clock-output-names = "si570_mgt"; +- }; +- }; +- i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- /* SI5328 - u20 */ +- }; +- /* 5 - 7 unconnected */ +- }; +- +- i2c-mux@75 { +- compatible = "nxp,pca9548"; /* u135 */ +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x75>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- /* HPC0_IIC */ +- }; +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- /* HPC1_IIC */ +- }; +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- /* SYSMON */ +- }; +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- /* DDR4 SODIMM */ +- }; +- i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- /* SEP 3 */ +- }; +- i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- /* SEP 2 */ +- }; +- i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- /* SEP 1 */ +- }; +- i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- /* SEP 0 */ +- }; +- }; +-}; +- +-&pcie { +- status = "okay"; +-}; +- +-&psgtr { +- status = "okay"; +- /* pcie, sata, usb3, dp */ +- clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; +- clock-names = "ref0", "ref1", "ref2", "ref3"; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +- /* SATA OOB timing settings */ +- ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; +- ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; +- ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; +- ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +- ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; +- ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; +- ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; +- ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +- phy-names = "sata-phy"; +- phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; +-}; +- +-/* SD1 with level shifter */ +-&sdhci1 { +- status = "okay"; +- no-1-8-v; +- xlnx,mio-bank = <1>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-/* ULPI SMSC USB3320 */ +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&watchdog0 { +- status = "okay"; +-}; +- +-&zynqmp_dpdma { +- status = "okay"; +-}; +- +-&zynqmp_dpsub { +- status = "okay"; +- phy-names = "dp-phy0"; +- phys = <&psgtr 1 PHY_TYPE_DP 0 3>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu102-revB.dts b/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu102-revB.dts +deleted file mode 100644 +index d9ad8a4b20d3..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu102-revB.dts ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * dts file for Xilinx ZynqMP ZCU102 RevB +- * +- * (C) Copyright 2016 - 2018, Xilinx, Inc. +- * +- * Michal Simek +- */ +- +-#include "zynqmp-zcu102-revA.dts" +- +-/ { +- model = "ZynqMP ZCU102 RevB"; +- compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; +-}; +- +-&gem3 { +- phy-handle = <&phyc>; +- phyc: ethernet-phy@c { +- reg = <0xc>; +- ti,rx-internal-delay = <0x8>; +- ti,tx-internal-delay = <0xa>; +- ti,fifo-depth = <0x1>; +- ti,dp83867-rxctrl-strap-quirk; +- }; +- /* Cleanup from RevA */ +- /delete-node/ ethernet-phy@21; +-}; +- +-/* Fix collision with u61 */ +-&i2c0 { +- i2c-mux@75 { +- i2c@2 { +- max15303@1b { /* u8 */ +- compatible = "maxim,max15303"; +- reg = <0x1b>; +- }; +- /delete-node/ max15303@20; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu104-revA.dts b/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu104-revA.dts +deleted file mode 100644 +index 5637e1c17fdf..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu104-revA.dts ++++ /dev/null +@@ -1,237 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * dts file for Xilinx ZynqMP ZCU104 +- * +- * (C) Copyright 2017 - 2019, Xilinx, Inc. +- * +- * Michal Simek +- */ +- +-/dts-v1/; +- +-#include "zynqmp.dtsi" +-#include "zynqmp-clk-ccf.dtsi" +-#include +-#include +- +-/ { +- model = "ZynqMP ZCU104 RevA"; +- compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; +- +- aliases { +- ethernet0 = &gem3; +- i2c0 = &i2c1; +- mmc0 = &sdhci1; +- rtc0 = &rtc; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &dcc; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- clock_8t49n287_5: clk125 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- }; +- +- clock_8t49n287_2: clk26 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +- +- clock_8t49n287_3: clk27 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- }; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&dcc { +- status = "okay"; +-}; +- +-&gem3 { +- status = "okay"; +- phy-handle = <&phy0>; +- phy-mode = "rgmii-id"; +- phy0: ethernet-phy@c { +- reg = <0xc>; +- ti,rx-internal-delay = <0x8>; +- ti,tx-internal-delay = <0xa>; +- ti,fifo-depth = <0x1>; +- ti,dp83867-rxctrl-strap-quirk; +- }; +-}; +- +-&gpio { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- /* Another connection to this bus via PL i2c via PCA9306 - u45 */ +- i2c-mux@74 { /* u34 */ +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x74>; +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- /* +- * IIC_EEPROM 1kB memory which uses 256B blocks +- * where every block has different address. +- * 0 - 256B address 0x54 +- * 256B - 512B address 0x55 +- * 512B - 768B address 0x56 +- * 768B - 1024B address 0x57 +- */ +- eeprom@54 { /* u23 */ +- compatible = "atmel,24c08"; +- reg = <0x54>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- }; +- +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ +- reg = <0x6c>; +- }; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ +- reg = <0x43>; +- }; +- irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ +- reg = <0x4d>; +- }; +- }; +- +- i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- tca6416_u97: gpio@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- /* +- * IRQ not connected +- * Lines: +- * 0 - IRPS5401_ALERT_B +- * 1 - HDMI_8T49N241_INT_ALM +- * 2 - MAX6643_OT_B +- * 3 - MAX6643_FANFAIL_B +- * 5 - IIC_MUX_RESET_B +- * 6 - GEM3_EXP_RESET_B +- * 7 - FMC_LPC_PRSNT_M2C_B +- * 4, 10 - 17 - not connected +- */ +- }; +- }; +- +- i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- +- /* 3, 6 not connected */ +- }; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&psgtr { +- status = "okay"; +- /* nc, sata, usb3, dp */ +- clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; +- clock-names = "ref1", "ref2", "ref3"; +-}; +- +-&sata { +- status = "okay"; +- /* SATA OOB timing settings */ +- ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; +- ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; +- ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; +- ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +- ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; +- ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; +- ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; +- ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +- phy-names = "sata-phy"; +- phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; +-}; +- +-/* SD1 with level shifter */ +-&sdhci1 { +- status = "okay"; +- no-1-8-v; +- xlnx,mio-bank = <1>; +- disable-wp; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-/* ULPI SMSC USB3320 */ +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&watchdog0 { +- status = "okay"; +-}; +- +-&zynqmp_dpdma { +- status = "okay"; +-}; +- +-&zynqmp_dpsub { +- status = "okay"; +- phy-names = "dp-phy0", "dp-phy1"; +- phys = <&psgtr 1 PHY_TYPE_DP 0 3>, +- <&psgtr 0 PHY_TYPE_DP 1 3>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu104-revC.dts b/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu104-revC.dts +deleted file mode 100644 +index 7f2e32831b05..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu104-revC.dts ++++ /dev/null +@@ -1,293 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * dts file for Xilinx ZynqMP ZCU104 +- * +- * (C) Copyright 2017 - 2020, Xilinx, Inc. +- * +- * Michal Simek +- */ +- +-/dts-v1/; +- +-#include "zynqmp.dtsi" +-#include "zynqmp-clk-ccf.dtsi" +-#include +-#include +- +-/ { +- model = "ZynqMP ZCU104 RevC"; +- compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; +- +- aliases { +- ethernet0 = &gem3; +- i2c0 = &i2c1; +- mmc0 = &sdhci1; +- rtc0 = &rtc; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &dcc; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>; +- }; +- +- ina226 { +- compatible = "iio-hwmon"; +- io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; +- }; +- +- clock_8t49n287_5: clk125 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- }; +- +- clock_8t49n287_2: clk26 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <26000000>; +- }; +- +- clock_8t49n287_3: clk27 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- }; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&dcc { +- status = "okay"; +-}; +- +-&fpd_dma_chan1 { +- status = "okay"; +-}; +- +-&fpd_dma_chan2 { +- status = "okay"; +-}; +- +-&fpd_dma_chan3 { +- status = "okay"; +-}; +- +-&fpd_dma_chan4 { +- status = "okay"; +-}; +- +-&fpd_dma_chan5 { +- status = "okay"; +-}; +- +-&fpd_dma_chan6 { +- status = "okay"; +-}; +- +-&fpd_dma_chan7 { +- status = "okay"; +-}; +- +-&fpd_dma_chan8 { +- status = "okay"; +-}; +- +-&gem3 { +- status = "okay"; +- phy-handle = <&phy0>; +- phy-mode = "rgmii-id"; +- phy0: ethernet-phy@c { +- reg = <0xc>; +- ti,rx-internal-delay = <0x8>; +- ti,tx-internal-delay = <0xa>; +- ti,fifo-depth = <0x1>; +- ti,dp83867-rxctrl-strap-quirk; +- }; +-}; +- +-&gpio { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- tca6416_u97: gpio@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- gpio-controller; +- #gpio-cells = <2>; +- /* +- * IRQ not connected +- * Lines: +- * 0 - IRPS5401_ALERT_B +- * 1 - HDMI_8T49N241_INT_ALM +- * 2 - MAX6643_OT_B +- * 3 - MAX6643_FANFAIL_B +- * 5 - IIC_MUX_RESET_B +- * 6 - GEM3_EXP_RESET_B +- * 7 - FMC_LPC_PRSNT_M2C_B +- * 4, 10 - 17 - not connected +- */ +- }; +- +- /* Another connection to this bus via PL i2c via PCA9306 - u45 */ +- i2c-mux@74 { /* u34 */ +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x74>; +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- /* +- * IIC_EEPROM 1kB memory which uses 256B blocks +- * where every block has different address. +- * 0 - 256B address 0x54 +- * 256B - 512B address 0x55 +- * 512B - 768B address 0x56 +- * 768B - 1024B address 0x57 +- */ +- eeprom: eeprom@54 { /* u23 */ +- compatible = "atmel,24c08"; +- reg = <0x54>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- }; +- +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ +- reg = <0x6c>; +- }; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ +- compatible = "infineon,irps5401"; +- reg = <0x43>; /* pmbus / i2c 0x13 */ +- }; +- irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ +- compatible = "infineon,irps5401"; +- reg = <0x44>; /* pmbus / i2c 0x14 */ +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- u183: ina226@40 { /* u183 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- reg = <0x40>; +- shunt-resistor = <5000>; +- }; +- }; +- +- i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- }; +- +- i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- }; +- +- /* 4, 6 not connected */ +- }; +-}; +- +-&qspi { +- status = "okay"; +- flash@0 { +- compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x0>; +- }; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&psgtr { +- status = "okay"; +- /* nc, sata, usb3, dp */ +- clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; +- clock-names = "ref1", "ref2", "ref3"; +-}; +- +-&sata { +- status = "okay"; +- /* SATA OOB timing settings */ +- ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; +- ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; +- ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; +- ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +- ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; +- ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; +- ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; +- ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +- phy-names = "sata-phy"; +- phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; +-}; +- +-/* SD1 with level shifter */ +-&sdhci1 { +- status = "okay"; +- no-1-8-v; +- xlnx,mio-bank = <1>; +- disable-wp; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-/* ULPI SMSC USB3320 */ +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&watchdog0 { +- status = "okay"; +-}; +- +-&zynqmp_dpdma { +- status = "okay"; +-}; +- +-&zynqmp_dpsub { +- status = "okay"; +- phy-names = "dp-phy0", "dp-phy1"; +- phys = <&psgtr 1 PHY_TYPE_DP 0 3>, +- <&psgtr 0 PHY_TYPE_DP 1 3>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu106-revA.dts b/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu106-revA.dts +deleted file mode 100644 +index eff7c6447087..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu106-revA.dts ++++ /dev/null +@@ -1,704 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * dts file for Xilinx ZynqMP ZCU106 +- * +- * (C) Copyright 2016 - 2019, Xilinx, Inc. +- * +- * Michal Simek +- */ +- +-/dts-v1/; +- +-#include "zynqmp.dtsi" +-#include "zynqmp-clk-ccf.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "ZynqMP ZCU106 RevA"; +- compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; +- +- aliases { +- ethernet0 = &gem3; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- mmc0 = &sdhci1; +- rtc0 = &rtc; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &dcc; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- sw19 { +- label = "sw19"; +- gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- wakeup-source; +- autorepeat; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- heartbeat-led { +- label = "heartbeat"; +- gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- ina226-u76 { +- compatible = "iio-hwmon"; +- io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; +- }; +- ina226-u77 { +- compatible = "iio-hwmon"; +- io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; +- }; +- ina226-u78 { +- compatible = "iio-hwmon"; +- io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; +- }; +- ina226-u87 { +- compatible = "iio-hwmon"; +- io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; +- }; +- ina226-u85 { +- compatible = "iio-hwmon"; +- io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; +- }; +- ina226-u86 { +- compatible = "iio-hwmon"; +- io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; +- }; +- ina226-u93 { +- compatible = "iio-hwmon"; +- io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; +- }; +- ina226-u88 { +- compatible = "iio-hwmon"; +- io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; +- }; +- ina226-u15 { +- compatible = "iio-hwmon"; +- io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; +- }; +- ina226-u92 { +- compatible = "iio-hwmon"; +- io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; +- }; +- ina226-u79 { +- compatible = "iio-hwmon"; +- io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; +- }; +- ina226-u81 { +- compatible = "iio-hwmon"; +- io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; +- }; +- ina226-u80 { +- compatible = "iio-hwmon"; +- io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; +- }; +- ina226-u84 { +- compatible = "iio-hwmon"; +- io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; +- }; +- ina226-u16 { +- compatible = "iio-hwmon"; +- io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; +- }; +- ina226-u65 { +- compatible = "iio-hwmon"; +- io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; +- }; +- ina226-u74 { +- compatible = "iio-hwmon"; +- io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; +- }; +- ina226-u75 { +- compatible = "iio-hwmon"; +- io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; +- }; +- +- /* 48MHz reference crystal */ +- ref48: ref48M { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <48000000>; +- }; +- +- refhdmi: refhdmi { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <114285000>; +- }; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&dcc { +- status = "okay"; +-}; +- +-&zynqmp_dpdma { +- status = "okay"; +-}; +- +-&zynqmp_dpsub { +- status = "okay"; +- phy-names = "dp-phy0", "dp-phy1"; +- phys = <&psgtr 1 PHY_TYPE_DP 0 3>, +- <&psgtr 0 PHY_TYPE_DP 1 3>; +-}; +- +-/* fpd_dma clk 667MHz, lpd_dma 500MHz */ +-&fpd_dma_chan1 { +- status = "okay"; +-}; +- +-&fpd_dma_chan2 { +- status = "okay"; +-}; +- +-&fpd_dma_chan3 { +- status = "okay"; +-}; +- +-&fpd_dma_chan4 { +- status = "okay"; +-}; +- +-&fpd_dma_chan5 { +- status = "okay"; +-}; +- +-&fpd_dma_chan6 { +- status = "okay"; +-}; +- +-&fpd_dma_chan7 { +- status = "okay"; +-}; +- +-&fpd_dma_chan8 { +- status = "okay"; +-}; +- +-&gem3 { +- status = "okay"; +- phy-handle = <&phy0>; +- phy-mode = "rgmii-id"; +- phy0: ethernet-phy@c { +- reg = <0xc>; +- ti,rx-internal-delay = <0x8>; +- ti,tx-internal-delay = <0xa>; +- ti,fifo-depth = <0x1>; +- ti,dp83867-rxctrl-strap-quirk; +- }; +-}; +- +-&gpio { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <400000>; +- +- tca6416_u97: gpio@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- gpio-controller; /* interrupt not connected */ +- #gpio-cells = <2>; +- /* +- * IRQ not connected +- * Lines: +- * 0 - SFP_SI5328_INT_ALM +- * 1 - HDMI_SI5328_INT_ALM +- * 5 - IIC_MUX_RESET_B +- * 6 - GEM3_EXP_RESET_B +- * 10 - FMC_HPC0_PRSNT_M2C_B +- * 11 - FMC_HPC1_PRSNT_M2C_B +- * 2-4, 7, 12-17 - not connected +- */ +- }; +- +- tca6416_u61: gpio@21 { +- compatible = "ti,tca6416"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- /* +- * IRQ not connected +- * Lines: +- * 0 - VCCPSPLL_EN +- * 1 - MGTRAVCC_EN +- * 2 - MGTRAVTT_EN +- * 3 - VCCPSDDRPLL_EN +- * 4 - MIO26_PMU_INPUT_LS +- * 5 - PL_PMBUS_ALERT +- * 6 - PS_PMBUS_ALERT +- * 7 - MAXIM_PMBUS_ALERT +- * 10 - PL_DDR4_VTERM_EN +- * 11 - PL_DDR4_VPP_2V5_EN +- * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON +- * 13 - PS_DIMM_SUSPEND_EN +- * 14 - PS_DDR4_VTERM_EN +- * 15 - PS_DDR4_VPP_2V5_EN +- * 16 - 17 - not connected +- */ +- }; +- +- i2c-mux@75 { /* u60 */ +- compatible = "nxp,pca9544"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x75>; +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- /* PS_PMBUS */ +- u76: ina226@40 { /* u76 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u76"; +- reg = <0x40>; +- shunt-resistor = <5000>; +- }; +- u77: ina226@41 { /* u77 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u77"; +- reg = <0x41>; +- shunt-resistor = <5000>; +- }; +- u78: ina226@42 { /* u78 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u78"; +- reg = <0x42>; +- shunt-resistor = <5000>; +- }; +- u87: ina226@43 { /* u87 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u87"; +- reg = <0x43>; +- shunt-resistor = <5000>; +- }; +- u85: ina226@44 { /* u85 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u85"; +- reg = <0x44>; +- shunt-resistor = <5000>; +- }; +- u86: ina226@45 { /* u86 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u86"; +- reg = <0x45>; +- shunt-resistor = <5000>; +- }; +- u93: ina226@46 { /* u93 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u93"; +- reg = <0x46>; +- shunt-resistor = <5000>; +- }; +- u88: ina226@47 { /* u88 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u88"; +- reg = <0x47>; +- shunt-resistor = <5000>; +- }; +- u15: ina226@4a { /* u15 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u15"; +- reg = <0x4a>; +- shunt-resistor = <5000>; +- }; +- u92: ina226@4b { /* u92 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u92"; +- reg = <0x4b>; +- shunt-resistor = <5000>; +- }; +- }; +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- /* PL_PMBUS */ +- u79: ina226@40 { /* u79 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u79"; +- reg = <0x40>; +- shunt-resistor = <2000>; +- }; +- u81: ina226@41 { /* u81 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u81"; +- reg = <0x41>; +- shunt-resistor = <5000>; +- }; +- u80: ina226@42 { /* u80 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u80"; +- reg = <0x42>; +- shunt-resistor = <5000>; +- }; +- u84: ina226@43 { /* u84 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u84"; +- reg = <0x43>; +- shunt-resistor = <5000>; +- }; +- u16: ina226@44 { /* u16 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u16"; +- reg = <0x44>; +- shunt-resistor = <5000>; +- }; +- u65: ina226@45 { /* u65 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u65"; +- reg = <0x45>; +- shunt-resistor = <5000>; +- }; +- u74: ina226@46 { /* u74 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u74"; +- reg = <0x46>; +- shunt-resistor = <5000>; +- }; +- u75: ina226@47 { /* u75 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u75"; +- reg = <0x47>; +- shunt-resistor = <5000>; +- }; +- }; +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- /* MAXIM_PMBUS - 00 */ +- max15301@a { /* u46 */ +- compatible = "maxim,max15301"; +- reg = <0xa>; +- }; +- max15303@b { /* u4 */ +- compatible = "maxim,max15303"; +- reg = <0xb>; +- }; +- max15303@10 { /* u13 */ +- compatible = "maxim,max15303"; +- reg = <0x10>; +- }; +- max15301@13 { /* u47 */ +- compatible = "maxim,max15301"; +- reg = <0x13>; +- }; +- max15303@14 { /* u7 */ +- compatible = "maxim,max15303"; +- reg = <0x14>; +- }; +- max15303@15 { /* u6 */ +- compatible = "maxim,max15303"; +- reg = <0x15>; +- }; +- max15303@16 { /* u10 */ +- compatible = "maxim,max15303"; +- reg = <0x16>; +- }; +- max15303@17 { /* u9 */ +- compatible = "maxim,max15303"; +- reg = <0x17>; +- }; +- max15301@18 { /* u63 */ +- compatible = "maxim,max15301"; +- reg = <0x18>; +- }; +- max15303@1a { /* u49 */ +- compatible = "maxim,max15303"; +- reg = <0x1a>; +- }; +- max15303@1b { /* u8 */ +- compatible = "maxim,max15303"; +- reg = <0x1b>; +- }; +- max15303@1d { /* u18 */ +- compatible = "maxim,max15303"; +- reg = <0x1d>; +- }; +- +- max20751@72 { /* u95 */ +- compatible = "maxim,max20751"; +- reg = <0x72>; +- }; +- max20751@73 { /* u96 */ +- compatible = "maxim,max20751"; +- reg = <0x73>; +- }; +- }; +- /* Bus 3 is not connected */ +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- /* PL i2c via PCA9306 - u45 */ +- i2c-mux@74 { /* u34 */ +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x74>; +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- /* +- * IIC_EEPROM 1kB memory which uses 256B blocks +- * where every block has different address. +- * 0 - 256B address 0x54 +- * 256B - 512B address 0x55 +- * 512B - 768B address 0x56 +- * 768B - 1024B address 0x57 +- */ +- eeprom: eeprom@54 { /* u23 */ +- compatible = "atmel,24c08"; +- reg = <0x54>; +- }; +- }; +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- si5341: clock-generator@36 { /* SI5341 - u69 */ +- compatible = "silabs,si5341"; +- reg = <0x36>; +- #clock-cells = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&ref48>; +- clock-names = "xtal"; +- clock-output-names = "si5341"; +- +- si5341_0: out@0 { +- /* refclk0 for PS-GT, used for DP */ +- reg = <0>; +- always-on; +- }; +- si5341_2: out@2 { +- /* refclk2 for PS-GT, used for USB3 */ +- reg = <2>; +- always-on; +- }; +- si5341_3: out@3 { +- /* refclk3 for PS-GT, used for SATA */ +- reg = <3>; +- always-on; +- }; +- si5341_6: out@6 { +- /* refclk6 PL CLK125 */ +- reg = <6>; +- always-on; +- }; +- si5341_7: out@7 { +- /* refclk7 PL CLK74 */ +- reg = <7>; +- always-on; +- }; +- si5341_9: out@9 { +- /* refclk9 used for PS_REF_CLK 33.3 MHz */ +- reg = <9>; +- always-on; +- }; +- }; +- +- }; +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- si570_1: clock-generator@5d { /* USER SI570 - u42 */ +- #clock-cells = <0>; +- compatible = "silabs,si570"; +- reg = <0x5d>; +- temperature-stability = <50>; +- factory-fout = <300000000>; +- clock-frequency = <300000000>; +- clock-output-names = "si570_user"; +- }; +- }; +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ +- #clock-cells = <0>; +- compatible = "silabs,si570"; +- reg = <0x5d>; +- temperature-stability = <50>; /* copy from zc702 */ +- factory-fout = <156250000>; +- clock-frequency = <148500000>; +- clock-output-names = "si570_mgt"; +- }; +- }; +- i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- /* SI5328 - u20 */ +- }; +- i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; /* FAN controller */ +- temp@4c {/* lm96163 - u128 */ +- compatible = "national,lm96163"; +- reg = <0x4c>; +- }; +- }; +- /* 6 - 7 unconnected */ +- }; +- +- i2c-mux@75 { +- compatible = "nxp,pca9548"; /* u135 */ +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x75>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- /* HPC0_IIC */ +- }; +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- /* HPC1_IIC */ +- }; +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- /* SYSMON */ +- }; +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- /* DDR4 SODIMM */ +- }; +- i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- /* SEP 3 */ +- }; +- i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- /* SEP 2 */ +- }; +- i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- /* SEP 1 */ +- }; +- i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- /* SEP 0 */ +- }; +- }; +-}; +- +-&psgtr { +- status = "okay"; +- /* nc, sata, usb3, dp */ +- clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; +- clock-names = "ref1", "ref2", "ref3"; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +- /* SATA OOB timing settings */ +- ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; +- ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; +- ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; +- ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +- ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; +- ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; +- ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; +- ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +- phy-names = "sata-phy"; +- phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; +-}; +- +-/* SD1 with level shifter */ +-&sdhci1 { +- status = "okay"; +- no-1-8-v; +- xlnx,mio-bank = <1>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-/* ULPI SMSC USB3320 */ +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&watchdog0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu111-revA.dts b/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu111-revA.dts +deleted file mode 100644 +index d4b68f0d0098..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp-zcu111-revA.dts ++++ /dev/null +@@ -1,597 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * dts file for Xilinx ZynqMP ZCU111 +- * +- * (C) Copyright 2017 - 2019, Xilinx, Inc. +- * +- * Michal Simek +- */ +- +-/dts-v1/; +- +-#include "zynqmp.dtsi" +-#include "zynqmp-clk-ccf.dtsi" +-#include +-#include +-#include +- +-/ { +- model = "ZynqMP ZCU111 RevA"; +- compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; +- +- aliases { +- ethernet0 = &gem3; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- mmc0 = &sdhci1; +- rtc0 = &rtc; +- serial0 = &uart0; +- serial1 = &dcc; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; +- /* Another 4GB connected to PL */ +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- autorepeat; +- sw19 { +- label = "sw19"; +- gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- wakeup-source; +- autorepeat; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- heartbeat-led { +- label = "heartbeat"; +- gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- ina226-u67 { +- compatible = "iio-hwmon"; +- io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; +- }; +- ina226-u59 { +- compatible = "iio-hwmon"; +- io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; +- }; +- ina226-u61 { +- compatible = "iio-hwmon"; +- io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; +- }; +- ina226-u60 { +- compatible = "iio-hwmon"; +- io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; +- }; +- ina226-u64 { +- compatible = "iio-hwmon"; +- io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; +- }; +- ina226-u69 { +- compatible = "iio-hwmon"; +- io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; +- }; +- ina226-u66 { +- compatible = "iio-hwmon"; +- io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; +- }; +- ina226-u65 { +- compatible = "iio-hwmon"; +- io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; +- }; +- ina226-u63 { +- compatible = "iio-hwmon"; +- io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; +- }; +- ina226-u3 { +- compatible = "iio-hwmon"; +- io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; +- }; +- ina226-u71 { +- compatible = "iio-hwmon"; +- io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; +- }; +- ina226-u77 { +- compatible = "iio-hwmon"; +- io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; +- }; +- ina226-u73 { +- compatible = "iio-hwmon"; +- io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; +- }; +- ina226-u79 { +- compatible = "iio-hwmon"; +- io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; +- }; +- +- /* 48MHz reference crystal */ +- ref48: ref48M { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <48000000>; +- }; +-}; +- +-&dcc { +- status = "okay"; +-}; +- +-&fpd_dma_chan1 { +- status = "okay"; +-}; +- +-&fpd_dma_chan2 { +- status = "okay"; +-}; +- +-&fpd_dma_chan3 { +- status = "okay"; +-}; +- +-&fpd_dma_chan4 { +- status = "okay"; +-}; +- +-&fpd_dma_chan5 { +- status = "okay"; +-}; +- +-&fpd_dma_chan6 { +- status = "okay"; +-}; +- +-&fpd_dma_chan7 { +- status = "okay"; +-}; +- +-&fpd_dma_chan8 { +- status = "okay"; +-}; +- +-&gem3 { +- status = "okay"; +- phy-handle = <&phy0>; +- phy-mode = "rgmii-id"; +- phy0: ethernet-phy@c { +- reg = <0xc>; +- ti,rx-internal-delay = <0x8>; +- ti,tx-internal-delay = <0xa>; +- ti,fifo-depth = <0x1>; +- ti,dp83867-rxctrl-strap-quirk; +- }; +-}; +- +-&gpio { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- clock-frequency = <400000>; +- +- tca6416_u22: gpio@20 { +- compatible = "ti,tca6416"; +- reg = <0x20>; +- gpio-controller; /* interrupt not connected */ +- #gpio-cells = <2>; +- /* +- * IRQ not connected +- * Lines: +- * 0 - MAX6643_OT_B +- * 1 - MAX6643_FANFAIL_B +- * 2 - MIO26_PMU_INPUT_LS +- * 4 - SFP_SI5382_INT_ALM +- * 5 - IIC_MUX_RESET_B +- * 6 - GEM3_EXP_RESET_B +- * 10 - FMCP_HSPC_PRSNT_M2C_B +- * 11 - CLK_SPI_MUX_SEL0 +- * 12 - CLK_SPI_MUX_SEL1 +- * 16 - IRPS5401_ALERT_B +- * 17 - INA226_PMBUS_ALERT +- * 3, 7, 13-15 - not connected +- */ +- }; +- +- i2c-mux@75 { /* u23 */ +- compatible = "nxp,pca9544"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x75>; +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- /* PS_PMBUS */ +- /* PMBUS_ALERT done via pca9544 */ +- u67: ina226@40 { /* u67 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u67"; +- reg = <0x40>; +- shunt-resistor = <2000>; +- }; +- u59: ina226@41 { /* u59 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u59"; +- reg = <0x41>; +- shunt-resistor = <5000>; +- }; +- u61: ina226@42 { /* u61 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u61"; +- reg = <0x42>; +- shunt-resistor = <5000>; +- }; +- u60: ina226@43 { /* u60 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u60"; +- reg = <0x43>; +- shunt-resistor = <5000>; +- }; +- u64: ina226@45 { /* u64 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u64"; +- reg = <0x45>; +- shunt-resistor = <5000>; +- }; +- u69: ina226@46 { /* u69 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u69"; +- reg = <0x46>; +- shunt-resistor = <2000>; +- }; +- u66: ina226@47 { /* u66 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u66"; +- reg = <0x47>; +- shunt-resistor = <5000>; +- }; +- u65: ina226@48 { /* u65 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u65"; +- reg = <0x48>; +- shunt-resistor = <5000>; +- }; +- u63: ina226@49 { /* u63 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u63"; +- reg = <0x49>; +- shunt-resistor = <5000>; +- }; +- u3: ina226@4a { /* u3 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u3"; +- reg = <0x4a>; +- shunt-resistor = <5000>; +- }; +- u71: ina226@4b { /* u71 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u71"; +- reg = <0x4b>; +- shunt-resistor = <5000>; +- }; +- u77: ina226@4c { /* u77 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u77"; +- reg = <0x4c>; +- shunt-resistor = <5000>; +- }; +- u73: ina226@4d { /* u73 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u73"; +- reg = <0x4d>; +- shunt-resistor = <5000>; +- }; +- u79: ina226@4e { /* u79 */ +- compatible = "ti,ina226"; +- #io-channel-cells = <1>; +- label = "ina226-u79"; +- reg = <0x4e>; +- shunt-resistor = <5000>; +- }; +- }; +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- /* NC */ +- }; +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ +- reg = <0x43>; +- }; +- irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ +- reg = <0x44>; +- }; +- irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ +- reg = <0x45>; +- }; +- /* u68 IR38064 +0 */ +- /* u70 IR38060 +1 */ +- /* u74 IR38060 +2 */ +- /* u75 IR38060 +6 */ +- /* J19 header too */ +- +- }; +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- /* SYSMON */ +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- clock-frequency = <400000>; +- +- i2c-mux@74 { /* u26 */ +- compatible = "nxp,pca9548"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x74>; +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- /* +- * IIC_EEPROM 1kB memory which uses 256B blocks +- * where every block has different address. +- * 0 - 256B address 0x54 +- * 256B - 512B address 0x55 +- * 512B - 768B address 0x56 +- * 768B - 1024B address 0x57 +- */ +- eeprom: eeprom@54 { /* u88 */ +- compatible = "atmel,24c08"; +- reg = <0x54>; +- }; +- }; +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- si5341: clock-generator@36 { /* SI5341 - u46 */ +- compatible = "silabs,si5341"; +- reg = <0x36>; +- #clock-cells = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&ref48>; +- clock-names = "xtal"; +- clock-output-names = "si5341"; +- +- si5341_0: out@0 { +- /* refclk0 for PS-GT, used for DP */ +- reg = <0>; +- always-on; +- }; +- si5341_2: out@2 { +- /* refclk2 for PS-GT, used for USB3 */ +- reg = <2>; +- always-on; +- }; +- si5341_3: out@3 { +- /* refclk3 for PS-GT, used for SATA */ +- reg = <3>; +- always-on; +- }; +- si5341_5: out@5 { +- /* refclk5 PL CLK100 */ +- reg = <5>; +- always-on; +- }; +- si5341_6: out@6 { +- /* refclk6 PL CLK125 */ +- reg = <6>; +- always-on; +- }; +- si5341_9: out@9 { +- /* refclk9 used for PS_REF_CLK 33.3 MHz */ +- reg = <9>; +- always-on; +- }; +- }; +- }; +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- si570_1: clock-generator@5d { /* USER SI570 - u47 */ +- #clock-cells = <0>; +- compatible = "silabs,si570"; +- reg = <0x5d>; +- temperature-stability = <50>; +- factory-fout = <300000000>; +- clock-frequency = <300000000>; +- clock-output-names = "si570_user"; +- }; +- }; +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ +- #clock-cells = <0>; +- compatible = "silabs,si570"; +- reg = <0x5d>; +- temperature-stability = <50>; +- factory-fout = <156250000>; +- clock-frequency = <156250000>; +- clock-output-names = "si570_mgt"; +- }; +- }; +- i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- si5382: clock-generator@69 { /* SI5382 - u48 */ +- reg = <0x69>; +- }; +- }; +- i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- sc18is603@2f { /* sc18is602 - u93 */ +- compatible = "nxp,sc18is603"; +- reg = <0x2f>; +- /* 4 gpios for CS not handled by driver */ +- /* +- * USB2ANY cable or +- * LMK04208 - u90 or +- * LMX2594 - u102 or +- * LMX2594 - u103 or +- * LMX2594 - u104 +- */ +- }; +- }; +- i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- /* FMC connector */ +- }; +- /* 7 NC */ +- }; +- +- i2c-mux@75 { +- compatible = "nxp,pca9548"; /* u27 */ +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x75>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- /* FMCP_HSPC_IIC */ +- }; +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- /* NC */ +- }; +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- /* SYSMON */ +- }; +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- /* DDR4 SODIMM */ +- }; +- i2c@4 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <4>; +- /* SFP3 */ +- }; +- i2c@5 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <5>; +- /* SFP2 */ +- }; +- i2c@6 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <6>; +- /* SFP1 */ +- }; +- i2c@7 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <7>; +- /* SFP0 */ +- }; +- }; +-}; +- +-&psgtr { +- status = "okay"; +- /* nc, sata, usb3, dp */ +- clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; +- clock-names = "ref1", "ref2", "ref3"; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +- /* SATA OOB timing settings */ +- ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; +- ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; +- ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; +- ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +- ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; +- ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; +- ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; +- ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +- phy-names = "sata-phy"; +- phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; +-}; +- +-/* SD1 with level shifter */ +-&sdhci1 { +- status = "okay"; +- no-1-8-v; +- xlnx,mio-bank = <1>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-/* ULPI SMSC USB3320 */ +-&usb0 { +- status = "okay"; +- dr_mode = "host"; +-}; +- +-&zynqmp_dpdma { +- status = "okay"; +-}; +- +-&zynqmp_dpsub { +- status = "okay"; +- phy-names = "dp-phy0", "dp-phy1"; +- phys = <&psgtr 1 PHY_TYPE_DP 0 1>, +- <&psgtr 0 PHY_TYPE_DP 1 1>; +-}; +diff --git a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp.dtsi b/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp.dtsi +deleted file mode 100644 +index 8278876ad33f..000000000000 +--- a/scripts/dtc/include-prefixes/arm64/xilinx/zynqmp.dtsi ++++ /dev/null +@@ -1,884 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * dts file for Xilinx ZynqMP +- * +- * (C) Copyright 2014 - 2019, Xilinx, Inc. +- * +- * Michal Simek +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- */ +- +-#include +-#include +-#include +- +-/ { +- compatible = "xlnx,zynqmp"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "psci"; +- operating-points-v2 = <&cpu_opp_table>; +- reg = <0x0>; +- cpu-idle-states = <&CPU_SLEEP_0>; +- }; +- +- cpu1: cpu@1 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "psci"; +- reg = <0x1>; +- operating-points-v2 = <&cpu_opp_table>; +- cpu-idle-states = <&CPU_SLEEP_0>; +- }; +- +- cpu2: cpu@2 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "psci"; +- reg = <0x2>; +- operating-points-v2 = <&cpu_opp_table>; +- cpu-idle-states = <&CPU_SLEEP_0>; +- }; +- +- cpu3: cpu@3 { +- compatible = "arm,cortex-a53"; +- device_type = "cpu"; +- enable-method = "psci"; +- reg = <0x3>; +- operating-points-v2 = <&cpu_opp_table>; +- cpu-idle-states = <&CPU_SLEEP_0>; +- }; +- +- idle-states { +- entry-method = "psci"; +- +- CPU_SLEEP_0: cpu-sleep-0 { +- compatible = "arm,idle-state"; +- arm,psci-suspend-param = <0x40000000>; +- local-timer-stop; +- entry-latency-us = <300>; +- exit-latency-us = <600>; +- min-residency-us = <10000>; +- }; +- }; +- }; +- +- cpu_opp_table: cpu-opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- opp00 { +- opp-hz = /bits/ 64 <1199999988>; +- opp-microvolt = <1000000>; +- clock-latency-ns = <500000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <599999994>; +- opp-microvolt = <1000000>; +- clock-latency-ns = <500000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <399999996>; +- opp-microvolt = <1000000>; +- clock-latency-ns = <500000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <299999997>; +- opp-microvolt = <1000000>; +- clock-latency-ns = <500000>; +- }; +- }; +- +- zynqmp_ipi: zynqmp_ipi { +- compatible = "xlnx,zynqmp-ipi-mailbox"; +- interrupt-parent = <&gic>; +- interrupts = <0 35 4>; +- xlnx,ipi-id = <0>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- ipi_mailbox_pmu1: mailbox@ff990400 { +- reg = <0x0 0xff9905c0 0x0 0x20>, +- <0x0 0xff9905e0 0x0 0x20>, +- <0x0 0xff990e80 0x0 0x20>, +- <0x0 0xff990ea0 0x0 0x20>; +- reg-names = "local_request_region", +- "local_response_region", +- "remote_request_region", +- "remote_response_region"; +- #mbox-cells = <1>; +- xlnx,ipi-id = <4>; +- }; +- }; +- +- dcc: dcc { +- compatible = "arm,dcc"; +- status = "disabled"; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupt-parent = <&gic>; +- interrupts = <0 143 4>, +- <0 144 4>, +- <0 145 4>, +- <0 146 4>; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- firmware { +- zynqmp_firmware: zynqmp-firmware { +- compatible = "xlnx,zynqmp-firmware"; +- #power-domain-cells = <1>; +- method = "smc"; +- +- zynqmp_power: zynqmp-power { +- compatible = "xlnx,zynqmp-power"; +- interrupt-parent = <&gic>; +- interrupts = <0 35 4>; +- mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; +- mbox-names = "tx", "rx"; +- }; +- +- zynqmp_clk: clock-controller { +- #clock-cells = <1>; +- compatible = "xlnx,zynqmp-clk"; +- clocks = <&pss_ref_clk>, +- <&video_clk>, +- <&pss_alt_ref_clk>, +- <&aux_ref_clk>, +- <>_crx_ref_clk>; +- clock-names = "pss_ref_clk", +- "video_clk", +- "pss_alt_ref_clk", +- "aux_ref_clk", +- "gt_crx_ref_clk"; +- }; +- +- nvmem_firmware { +- compatible = "xlnx,zynqmp-nvmem-fw"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- soc_revision: soc_revision@0 { +- reg = <0x0 0x4>; +- }; +- }; +- +- zynqmp_pcap: pcap { +- compatible = "xlnx,zynqmp-pcap-fpga"; +- }; +- +- xlnx_aes: zynqmp-aes { +- compatible = "xlnx,zynqmp-aes"; +- }; +- +- zynqmp_reset: reset-controller { +- compatible = "xlnx,zynqmp-reset"; +- #reset-cells = <1>; +- }; +- }; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupt-parent = <&gic>; +- interrupts = <1 13 0xf08>, +- <1 14 0xf08>, +- <1 11 0xf08>, +- <1 10 0xf08>; +- }; +- +- fpga_full: fpga-full { +- compatible = "fpga-region"; +- fpga-mgr = <&zynqmp_pcap>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- }; +- +- amba: axi { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- can0: can@ff060000 { +- compatible = "xlnx,zynq-can-1.0"; +- status = "disabled"; +- clock-names = "can_clk", "pclk"; +- reg = <0x0 0xff060000 0x0 0x1000>; +- interrupts = <0 23 4>; +- interrupt-parent = <&gic>; +- tx-fifo-depth = <0x40>; +- rx-fifo-depth = <0x40>; +- power-domains = <&zynqmp_firmware PD_CAN_0>; +- }; +- +- can1: can@ff070000 { +- compatible = "xlnx,zynq-can-1.0"; +- status = "disabled"; +- clock-names = "can_clk", "pclk"; +- reg = <0x0 0xff070000 0x0 0x1000>; +- interrupts = <0 24 4>; +- interrupt-parent = <&gic>; +- tx-fifo-depth = <0x40>; +- rx-fifo-depth = <0x40>; +- power-domains = <&zynqmp_firmware PD_CAN_1>; +- }; +- +- cci: cci@fd6e0000 { +- compatible = "arm,cci-400"; +- reg = <0x0 0xfd6e0000 0x0 0x9000>; +- ranges = <0x0 0x0 0xfd6e0000 0x10000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- pmu@9000 { +- compatible = "arm,cci-400-pmu,r1"; +- reg = <0x9000 0x5000>; +- interrupt-parent = <&gic>; +- interrupts = <0 123 4>, +- <0 123 4>, +- <0 123 4>, +- <0 123 4>, +- <0 123 4>; +- }; +- }; +- +- /* GDMA */ +- fpd_dma_chan1: dma@fd500000 { +- status = "disabled"; +- compatible = "xlnx,zynqmp-dma-1.0"; +- reg = <0x0 0xfd500000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = <0 124 4>; +- clock-names = "clk_main", "clk_apb"; +- xlnx,bus-width = <128>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x14e8>; +- power-domains = <&zynqmp_firmware PD_GDMA>; +- }; +- +- fpd_dma_chan2: dma@fd510000 { +- status = "disabled"; +- compatible = "xlnx,zynqmp-dma-1.0"; +- reg = <0x0 0xfd510000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = <0 125 4>; +- clock-names = "clk_main", "clk_apb"; +- xlnx,bus-width = <128>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x14e9>; +- power-domains = <&zynqmp_firmware PD_GDMA>; +- }; +- +- fpd_dma_chan3: dma@fd520000 { +- status = "disabled"; +- compatible = "xlnx,zynqmp-dma-1.0"; +- reg = <0x0 0xfd520000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = <0 126 4>; +- clock-names = "clk_main", "clk_apb"; +- xlnx,bus-width = <128>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x14ea>; +- power-domains = <&zynqmp_firmware PD_GDMA>; +- }; +- +- fpd_dma_chan4: dma@fd530000 { +- status = "disabled"; +- compatible = "xlnx,zynqmp-dma-1.0"; +- reg = <0x0 0xfd530000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = <0 127 4>; +- clock-names = "clk_main", "clk_apb"; +- xlnx,bus-width = <128>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x14eb>; +- power-domains = <&zynqmp_firmware PD_GDMA>; +- }; +- +- fpd_dma_chan5: dma@fd540000 { +- status = "disabled"; +- compatible = "xlnx,zynqmp-dma-1.0"; +- reg = <0x0 0xfd540000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = <0 128 4>; +- clock-names = "clk_main", "clk_apb"; +- xlnx,bus-width = <128>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x14ec>; +- power-domains = <&zynqmp_firmware PD_GDMA>; +- }; +- +- fpd_dma_chan6: dma@fd550000 { +- status = "disabled"; +- compatible = "xlnx,zynqmp-dma-1.0"; +- reg = <0x0 0xfd550000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = <0 129 4>; +- clock-names = "clk_main", "clk_apb"; +- xlnx,bus-width = <128>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x14ed>; +- power-domains = <&zynqmp_firmware PD_GDMA>; +- }; +- +- fpd_dma_chan7: dma@fd560000 { +- status = "disabled"; +- compatible = "xlnx,zynqmp-dma-1.0"; +- reg = <0x0 0xfd560000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = <0 130 4>; +- clock-names = "clk_main", "clk_apb"; +- xlnx,bus-width = <128>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x14ee>; +- power-domains = <&zynqmp_firmware PD_GDMA>; +- }; +- +- fpd_dma_chan8: dma@fd570000 { +- status = "disabled"; +- compatible = "xlnx,zynqmp-dma-1.0"; +- reg = <0x0 0xfd570000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = <0 131 4>; +- clock-names = "clk_main", "clk_apb"; +- xlnx,bus-width = <128>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x14ef>; +- power-domains = <&zynqmp_firmware PD_GDMA>; +- }; +- +- gic: interrupt-controller@f9010000 { +- compatible = "arm,gic-400"; +- #address-cells = <0>; +- #interrupt-cells = <3>; +- reg = <0x0 0xf9010000 0x0 0x10000>, +- <0x0 0xf9020000 0x0 0x20000>, +- <0x0 0xf9040000 0x0 0x20000>, +- <0x0 0xf9060000 0x0 0x20000>; +- interrupt-controller; +- interrupt-parent = <&gic>; +- interrupts = <1 9 0xf04>; +- }; +- +- /* LPDDMA default allows only secured access. inorder to enable +- * These dma channels, Users should ensure that these dma +- * Channels are allowed for non secure access. +- */ +- lpd_dma_chan1: dma@ffa80000 { +- status = "disabled"; +- compatible = "xlnx,zynqmp-dma-1.0"; +- reg = <0x0 0xffa80000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = <0 77 4>; +- clock-names = "clk_main", "clk_apb"; +- xlnx,bus-width = <64>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x868>; +- power-domains = <&zynqmp_firmware PD_ADMA>; +- }; +- +- lpd_dma_chan2: dma@ffa90000 { +- status = "disabled"; +- compatible = "xlnx,zynqmp-dma-1.0"; +- reg = <0x0 0xffa90000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = <0 78 4>; +- clock-names = "clk_main", "clk_apb"; +- xlnx,bus-width = <64>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x869>; +- power-domains = <&zynqmp_firmware PD_ADMA>; +- }; +- +- lpd_dma_chan3: dma@ffaa0000 { +- status = "disabled"; +- compatible = "xlnx,zynqmp-dma-1.0"; +- reg = <0x0 0xffaa0000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = <0 79 4>; +- clock-names = "clk_main", "clk_apb"; +- xlnx,bus-width = <64>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x86a>; +- power-domains = <&zynqmp_firmware PD_ADMA>; +- }; +- +- lpd_dma_chan4: dma@ffab0000 { +- status = "disabled"; +- compatible = "xlnx,zynqmp-dma-1.0"; +- reg = <0x0 0xffab0000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = <0 80 4>; +- clock-names = "clk_main", "clk_apb"; +- xlnx,bus-width = <64>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x86b>; +- power-domains = <&zynqmp_firmware PD_ADMA>; +- }; +- +- lpd_dma_chan5: dma@ffac0000 { +- status = "disabled"; +- compatible = "xlnx,zynqmp-dma-1.0"; +- reg = <0x0 0xffac0000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = <0 81 4>; +- clock-names = "clk_main", "clk_apb"; +- xlnx,bus-width = <64>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x86c>; +- power-domains = <&zynqmp_firmware PD_ADMA>; +- }; +- +- lpd_dma_chan6: dma@ffad0000 { +- status = "disabled"; +- compatible = "xlnx,zynqmp-dma-1.0"; +- reg = <0x0 0xffad0000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = <0 82 4>; +- clock-names = "clk_main", "clk_apb"; +- xlnx,bus-width = <64>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x86d>; +- power-domains = <&zynqmp_firmware PD_ADMA>; +- }; +- +- lpd_dma_chan7: dma@ffae0000 { +- status = "disabled"; +- compatible = "xlnx,zynqmp-dma-1.0"; +- reg = <0x0 0xffae0000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = <0 83 4>; +- clock-names = "clk_main", "clk_apb"; +- xlnx,bus-width = <64>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x86e>; +- power-domains = <&zynqmp_firmware PD_ADMA>; +- }; +- +- lpd_dma_chan8: dma@ffaf0000 { +- status = "disabled"; +- compatible = "xlnx,zynqmp-dma-1.0"; +- reg = <0x0 0xffaf0000 0x0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = <0 84 4>; +- clock-names = "clk_main", "clk_apb"; +- xlnx,bus-width = <64>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x86f>; +- power-domains = <&zynqmp_firmware PD_ADMA>; +- }; +- +- mc: memory-controller@fd070000 { +- compatible = "xlnx,zynqmp-ddrc-2.40a"; +- reg = <0x0 0xfd070000 0x0 0x30000>; +- interrupt-parent = <&gic>; +- interrupts = <0 112 4>; +- }; +- +- nand0: nand-controller@ff100000 { +- compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; +- status = "disabled"; +- reg = <0x0 0xff100000 0x0 0x1000>; +- clock-names = "controller", "bus"; +- interrupt-parent = <&gic>; +- interrupts = <0 14 4>; +- #address-cells = <1>; +- #size-cells = <0>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x872>; +- power-domains = <&zynqmp_firmware PD_NAND>; +- }; +- +- gem0: ethernet@ff0b0000 { +- compatible = "cdns,zynqmp-gem", "cdns,gem"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 57 4>, <0 57 4>; +- reg = <0x0 0xff0b0000 0x0 0x1000>; +- clock-names = "pclk", "hclk", "tx_clk"; +- #address-cells = <1>; +- #size-cells = <0>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x874>; +- power-domains = <&zynqmp_firmware PD_ETH_0>; +- }; +- +- gem1: ethernet@ff0c0000 { +- compatible = "cdns,zynqmp-gem", "cdns,gem"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 59 4>, <0 59 4>; +- reg = <0x0 0xff0c0000 0x0 0x1000>; +- clock-names = "pclk", "hclk", "tx_clk"; +- #address-cells = <1>; +- #size-cells = <0>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x875>; +- power-domains = <&zynqmp_firmware PD_ETH_1>; +- }; +- +- gem2: ethernet@ff0d0000 { +- compatible = "cdns,zynqmp-gem", "cdns,gem"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 61 4>, <0 61 4>; +- reg = <0x0 0xff0d0000 0x0 0x1000>; +- clock-names = "pclk", "hclk", "tx_clk"; +- #address-cells = <1>; +- #size-cells = <0>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x876>; +- power-domains = <&zynqmp_firmware PD_ETH_2>; +- }; +- +- gem3: ethernet@ff0e0000 { +- compatible = "cdns,zynqmp-gem", "cdns,gem"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 63 4>, <0 63 4>; +- reg = <0x0 0xff0e0000 0x0 0x1000>; +- clock-names = "pclk", "hclk", "tx_clk"; +- #address-cells = <1>; +- #size-cells = <0>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x877>; +- power-domains = <&zynqmp_firmware PD_ETH_3>; +- }; +- +- gpio: gpio@ff0a0000 { +- compatible = "xlnx,zynqmp-gpio-1.0"; +- status = "disabled"; +- #address-cells = <0>; +- #gpio-cells = <0x2>; +- gpio-controller; +- interrupt-parent = <&gic>; +- interrupts = <0 16 4>; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x0 0xff0a0000 0x0 0x1000>; +- power-domains = <&zynqmp_firmware PD_GPIO>; +- }; +- +- i2c0: i2c@ff020000 { +- compatible = "cdns,i2c-r1p14"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 17 4>; +- reg = <0x0 0xff020000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&zynqmp_firmware PD_I2C_0>; +- }; +- +- i2c1: i2c@ff030000 { +- compatible = "cdns,i2c-r1p14"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 18 4>; +- reg = <0x0 0xff030000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&zynqmp_firmware PD_I2C_1>; +- }; +- +- pcie: pcie@fd0e0000 { +- compatible = "xlnx,nwl-pcie-2.11"; +- status = "disabled"; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- msi-controller; +- device_type = "pci"; +- interrupt-parent = <&gic>; +- interrupts = <0 118 4>, +- <0 117 4>, +- <0 116 4>, +- <0 115 4>, /* MSI_1 [63...32] */ +- <0 114 4>; /* MSI_0 [31...0] */ +- interrupt-names = "misc", "dummy", "intx", +- "msi1", "msi0"; +- msi-parent = <&pcie>; +- reg = <0x0 0xfd0e0000 0x0 0x1000>, +- <0x0 0xfd480000 0x0 0x1000>, +- <0x80 0x00000000 0x0 0x1000000>; +- reg-names = "breg", "pcireg", "cfg"; +- ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ +- <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ +- bus-range = <0x00 0xff>; +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, +- <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, +- <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, +- <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; +- power-domains = <&zynqmp_firmware PD_PCIE>; +- pcie_intc: legacy-interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- }; +- }; +- +- qspi: spi@ff0f0000 { +- compatible = "xlnx,zynqmp-qspi-1.0"; +- status = "disabled"; +- clock-names = "ref_clk", "pclk"; +- interrupts = <0 15 4>; +- interrupt-parent = <&gic>; +- num-cs = <1>; +- reg = <0x0 0xff0f0000 0x0 0x1000>, +- <0x0 0xc0000000 0x0 0x8000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x873>; +- power-domains = <&zynqmp_firmware PD_QSPI>; +- }; +- +- psgtr: phy@fd400000 { +- compatible = "xlnx,zynqmp-psgtr-v1.1"; +- status = "disabled"; +- reg = <0x0 0xfd400000 0x0 0x40000>, +- <0x0 0xfd3d0000 0x0 0x1000>; +- reg-names = "serdes", "siou"; +- #phy-cells = <4>; +- }; +- +- rtc: rtc@ffa60000 { +- compatible = "xlnx,zynqmp-rtc"; +- status = "disabled"; +- reg = <0x0 0xffa60000 0x0 0x100>; +- interrupt-parent = <&gic>; +- interrupts = <0 26 4>, <0 27 4>; +- interrupt-names = "alarm", "sec"; +- calibration = <0x8000>; +- }; +- +- sata: ahci@fd0c0000 { +- compatible = "ceva,ahci-1v84"; +- status = "disabled"; +- reg = <0x0 0xfd0c0000 0x0 0x2000>; +- interrupt-parent = <&gic>; +- interrupts = <0 133 4>; +- power-domains = <&zynqmp_firmware PD_SATA>; +- #stream-id-cells = <4>; +- iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, +- <&smmu 0x4c2>, <&smmu 0x4c3>; +- }; +- +- sdhci0: mmc@ff160000 { +- compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 48 4>; +- reg = <0x0 0xff160000 0x0 0x1000>; +- clock-names = "clk_xin", "clk_ahb"; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x870>; +- #clock-cells = <1>; +- clock-output-names = "clk_out_sd0", "clk_in_sd0"; +- power-domains = <&zynqmp_firmware PD_SD_0>; +- }; +- +- sdhci1: mmc@ff170000 { +- compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 49 4>; +- reg = <0x0 0xff170000 0x0 0x1000>; +- clock-names = "clk_xin", "clk_ahb"; +- #stream-id-cells = <1>; +- iommus = <&smmu 0x871>; +- #clock-cells = <1>; +- clock-output-names = "clk_out_sd1", "clk_in_sd1"; +- power-domains = <&zynqmp_firmware PD_SD_1>; +- }; +- +- smmu: iommu@fd800000 { +- compatible = "arm,mmu-500"; +- reg = <0x0 0xfd800000 0x0 0x20000>; +- #iommu-cells = <1>; +- status = "disabled"; +- #global-interrupts = <1>; +- interrupt-parent = <&gic>; +- interrupts = <0 155 4>, +- <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, +- <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, +- <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, +- <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; +- }; +- +- spi0: spi@ff040000 { +- compatible = "cdns,spi-r1p6"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 19 4>; +- reg = <0x0 0xff040000 0x0 0x1000>; +- clock-names = "ref_clk", "pclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&zynqmp_firmware PD_SPI_0>; +- }; +- +- spi1: spi@ff050000 { +- compatible = "cdns,spi-r1p6"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 20 4>; +- reg = <0x0 0xff050000 0x0 0x1000>; +- clock-names = "ref_clk", "pclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- power-domains = <&zynqmp_firmware PD_SPI_1>; +- }; +- +- ttc0: timer@ff110000 { +- compatible = "cdns,ttc"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 36 4>, <0 37 4>, <0 38 4>; +- reg = <0x0 0xff110000 0x0 0x1000>; +- timer-width = <32>; +- power-domains = <&zynqmp_firmware PD_TTC_0>; +- }; +- +- ttc1: timer@ff120000 { +- compatible = "cdns,ttc"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 39 4>, <0 40 4>, <0 41 4>; +- reg = <0x0 0xff120000 0x0 0x1000>; +- timer-width = <32>; +- power-domains = <&zynqmp_firmware PD_TTC_1>; +- }; +- +- ttc2: timer@ff130000 { +- compatible = "cdns,ttc"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 42 4>, <0 43 4>, <0 44 4>; +- reg = <0x0 0xff130000 0x0 0x1000>; +- timer-width = <32>; +- power-domains = <&zynqmp_firmware PD_TTC_2>; +- }; +- +- ttc3: timer@ff140000 { +- compatible = "cdns,ttc"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 45 4>, <0 46 4>, <0 47 4>; +- reg = <0x0 0xff140000 0x0 0x1000>; +- timer-width = <32>; +- power-domains = <&zynqmp_firmware PD_TTC_3>; +- }; +- +- uart0: serial@ff000000 { +- compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 21 4>; +- reg = <0x0 0xff000000 0x0 0x1000>; +- clock-names = "uart_clk", "pclk"; +- power-domains = <&zynqmp_firmware PD_UART_0>; +- }; +- +- uart1: serial@ff010000 { +- compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 22 4>; +- reg = <0x0 0xff010000 0x0 0x1000>; +- clock-names = "uart_clk", "pclk"; +- power-domains = <&zynqmp_firmware PD_UART_1>; +- }; +- +- usb0: usb@fe200000 { +- compatible = "snps,dwc3"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 65 4>; +- reg = <0x0 0xfe200000 0x0 0x40000>; +- clock-names = "clk_xin", "clk_ahb"; +- power-domains = <&zynqmp_firmware PD_USB_0>; +- }; +- +- usb1: usb@fe300000 { +- compatible = "snps,dwc3"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 70 4>; +- reg = <0x0 0xfe300000 0x0 0x40000>; +- clock-names = "clk_xin", "clk_ahb"; +- power-domains = <&zynqmp_firmware PD_USB_1>; +- }; +- +- watchdog0: watchdog@fd4d0000 { +- compatible = "cdns,wdt-r1p2"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 113 1>; +- reg = <0x0 0xfd4d0000 0x0 0x1000>; +- timeout-sec = <10>; +- }; +- +- lpd_watchdog: watchdog@ff150000 { +- compatible = "cdns,wdt-r1p2"; +- status = "disabled"; +- interrupt-parent = <&gic>; +- interrupts = <0 52 1>; +- reg = <0x0 0xff150000 0x0 0x1000>; +- timeout-sec = <10>; +- }; +- +- zynqmp_dpdma: dma-controller@fd4c0000 { +- compatible = "xlnx,zynqmp-dpdma"; +- status = "disabled"; +- reg = <0x0 0xfd4c0000 0x0 0x1000>; +- interrupts = <0 122 4>; +- interrupt-parent = <&gic>; +- clock-names = "axi_clk"; +- power-domains = <&zynqmp_firmware PD_DP>; +- #dma-cells = <1>; +- }; +- +- zynqmp_dpsub: display@fd4a0000 { +- compatible = "xlnx,zynqmp-dpsub-1.7"; +- status = "disabled"; +- reg = <0x0 0xfd4a0000 0x0 0x1000>, +- <0x0 0xfd4aa000 0x0 0x1000>, +- <0x0 0xfd4ab000 0x0 0x1000>, +- <0x0 0xfd4ac000 0x0 0x1000>; +- reg-names = "dp", "blend", "av_buf", "aud"; +- interrupts = <0 119 4>; +- interrupt-parent = <&gic>; +- clock-names = "dp_apb_clk", "dp_aud_clk", +- "dp_vtc_pixel_clk_in"; +- power-domains = <&zynqmp_firmware PD_DP>; +- resets = <&zynqmp_reset ZYNQMP_RESET_DP>; +- dma-names = "vid0", "vid1", "vid2", "gfx0"; +- dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, +- <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, +- <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, +- <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/dt-bindings b/scripts/dtc/include-prefixes/dt-bindings +new file mode 120000 +index 000000000000..04fdbb3af016 +--- /dev/null ++++ b/scripts/dtc/include-prefixes/dt-bindings +@@ -0,0 +1 @@ ++../../../include/dt-bindings +\ No newline at end of file +diff --git a/scripts/dtc/include-prefixes/dt-bindings/arm/coresight-cti-dt.h b/scripts/dtc/include-prefixes/dt-bindings/arm/coresight-cti-dt.h +deleted file mode 100644 +index 61e7bdf8ea6e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/arm/coresight-cti-dt.h ++++ /dev/null +@@ -1,37 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for the defined trigger signal +- * types on CoreSight CTI. +- */ +- +-#ifndef _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H +-#define _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H +- +-#define GEN_IO 0 +-#define GEN_INTREQ 1 +-#define GEN_INTACK 2 +-#define GEN_HALTREQ 3 +-#define GEN_RESTARTREQ 4 +-#define PE_EDBGREQ 5 +-#define PE_DBGRESTART 6 +-#define PE_CTIIRQ 7 +-#define PE_PMUIRQ 8 +-#define PE_DBGTRIGGER 9 +-#define ETM_EXTOUT 10 +-#define ETM_EXTIN 11 +-#define SNK_FULL 12 +-#define SNK_ACQCOMP 13 +-#define SNK_FLUSHCOMP 14 +-#define SNK_FLUSHIN 15 +-#define SNK_TRIGIN 16 +-#define STM_ASYNCOUT 17 +-#define STM_TOUT_SPTE 18 +-#define STM_TOUT_SW 19 +-#define STM_TOUT_HETE 20 +-#define STM_HWEVENT 21 +-#define ELA_TSTART 22 +-#define ELA_TSTOP 23 +-#define ELA_DBGREQ 24 +-#define CTI_TRIG_MAX 25 +- +-#endif /*_DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/arm/ux500_pm_domains.h b/scripts/dtc/include-prefixes/dt-bindings/arm/ux500_pm_domains.h +deleted file mode 100644 +index 9bd764f0c9e6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/arm/ux500_pm_domains.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2014 Linaro Ltd. +- * +- * Author: Ulf Hansson +- */ +-#ifndef _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H +-#define _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H +- +-#define DOMAIN_VAPE 0 +- +-/* Number of PM domains. */ +-#define NR_DOMAINS (DOMAIN_VAPE + 1) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/bus/moxtet.h b/scripts/dtc/include-prefixes/dt-bindings/bus/moxtet.h +deleted file mode 100644 +index 10528de7b3ef..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/bus/moxtet.h ++++ /dev/null +@@ -1,16 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Constant for device tree bindings for Turris Mox module configuration bus +- * +- * Copyright (C) 2019 Marek Behún +- */ +- +-#ifndef _DT_BINDINGS_BUS_MOXTET_H +-#define _DT_BINDINGS_BUS_MOXTET_H +- +-#define MOXTET_IRQ_PCI 0 +-#define MOXTET_IRQ_USB3 4 +-#define MOXTET_IRQ_PERIDOT(n) (8 + (n)) +-#define MOXTET_IRQ_TOPAZ 12 +- +-#endif /* _DT_BINDINGS_BUS_MOXTET_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/bus/ti-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/bus/ti-sysc.h +deleted file mode 100644 +index 76b07826ed05..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/bus/ti-sysc.h ++++ /dev/null +@@ -1,29 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* TI sysc interconnect target module defines */ +- +-/* Generic sysc found on omap2 and later, also known as type1 */ +-#define SYSC_OMAP2_CLOCKACTIVITY (3 << 8) +-#define SYSC_OMAP2_EMUFREE (1 << 5) +-#define SYSC_OMAP2_ENAWAKEUP (1 << 2) +-#define SYSC_OMAP2_SOFTRESET (1 << 1) +-#define SYSC_OMAP2_AUTOIDLE (1 << 0) +- +-/* Generic sysc found on omap4 and later, also known as type2 */ +-#define SYSC_OMAP4_DMADISABLE (1 << 16) +-#define SYSC_OMAP4_FREEEMU (1 << 1) /* Also known as EMUFREE */ +-#define SYSC_OMAP4_SOFTRESET (1 << 0) +- +-/* SmartReflex sysc found on 36xx and later */ +-#define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26) +- +-#define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4) +- +-/* PRUSS sysc found on AM33xx/AM43xx/AM57xx */ +-#define SYSC_PRUSS_SUB_MWAIT (1 << 5) +-#define SYSC_PRUSS_STANDBY_INIT (1 << 4) +- +-/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */ +-#define SYSC_IDLE_FORCE 0 +-#define SYSC_IDLE_NO 1 +-#define SYSC_IDLE_SMART 2 +-#define SYSC_IDLE_SMART_WKUP 3 +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clk/lochnagar.h b/scripts/dtc/include-prefixes/dt-bindings/clk/lochnagar.h +deleted file mode 100644 +index 8fa20551ff17..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clk/lochnagar.h ++++ /dev/null +@@ -1,26 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Device Tree defines for Lochnagar clocking +- * +- * Copyright (c) 2017-2018 Cirrus Logic, Inc. and +- * Cirrus Logic International Semiconductor Ltd. +- * +- * Author: Charles Keepax +- */ +- +-#ifndef DT_BINDINGS_CLK_LOCHNAGAR_H +-#define DT_BINDINGS_CLK_LOCHNAGAR_H +- +-#define LOCHNAGAR_CDC_MCLK1 0 +-#define LOCHNAGAR_CDC_MCLK2 1 +-#define LOCHNAGAR_DSP_CLKIN 2 +-#define LOCHNAGAR_GF_CLKOUT1 3 +-#define LOCHNAGAR_GF_CLKOUT2 4 +-#define LOCHNAGAR_PSIA1_MCLK 5 +-#define LOCHNAGAR_PSIA2_MCLK 6 +-#define LOCHNAGAR_SPDIF_MCLK 7 +-#define LOCHNAGAR_ADAT_MCLK 8 +-#define LOCHNAGAR_SOUNDCARD_MCLK 9 +-#define LOCHNAGAR_SPDIF_CLKOUT 10 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clk/versaclock.h b/scripts/dtc/include-prefixes/dt-bindings/clk/versaclock.h +deleted file mode 100644 +index c6a6a0946564..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clk/versaclock.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +- +-/* This file defines field values used by the versaclock 6 family +- * for defining output type +- */ +- +-#define VC5_LVPECL 0 +-#define VC5_CMOS 1 +-#define VC5_HCSL33 2 +-#define VC5_LVDS 3 +-#define VC5_CMOS2 4 +-#define VC5_CMOSD 5 +-#define VC5_HCSL25 6 +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/actions,s500-cmu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/actions,s500-cmu.h +deleted file mode 100644 +index a237eb26accb..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/actions,s500-cmu.h ++++ /dev/null +@@ -1,85 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Device Tree binding constants for Actions Semi S500 Clock Management Unit +- * +- * Copyright (c) 2014 Actions Semi Inc. +- * Copyright (c) 2018 LSI-TEC - Caninos Loucos +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_S500_CMU_H +-#define __DT_BINDINGS_CLOCK_S500_CMU_H +- +-#define CLK_NONE 0 +- +-/* fixed rate clocks */ +-#define CLK_LOSC 1 +-#define CLK_HOSC 2 +- +-/* pll clocks */ +-#define CLK_CORE_PLL 3 +-#define CLK_DEV_PLL 4 +-#define CLK_DDR_PLL 5 +-#define CLK_NAND_PLL 6 +-#define CLK_DISPLAY_PLL 7 +-#define CLK_ETHERNET_PLL 8 +-#define CLK_AUDIO_PLL 9 +- +-/* system clock */ +-#define CLK_DEV 10 +-#define CLK_H 11 +-#define CLK_AHBPREDIV 12 +-#define CLK_AHB 13 +-#define CLK_DE 14 +-#define CLK_BISP 15 +-#define CLK_VCE 16 +-#define CLK_VDE 17 +- +-/* peripheral device clock */ +-#define CLK_TIMER 18 +-#define CLK_I2C0 19 +-#define CLK_I2C1 20 +-#define CLK_I2C2 21 +-#define CLK_I2C3 22 +-#define CLK_PWM0 23 +-#define CLK_PWM1 24 +-#define CLK_PWM2 25 +-#define CLK_PWM3 26 +-#define CLK_PWM4 27 +-#define CLK_PWM5 28 +-#define CLK_SD0 29 +-#define CLK_SD1 30 +-#define CLK_SD2 31 +-#define CLK_SENSOR0 32 +-#define CLK_SENSOR1 33 +-#define CLK_SPI0 34 +-#define CLK_SPI1 35 +-#define CLK_SPI2 36 +-#define CLK_SPI3 37 +-#define CLK_UART0 38 +-#define CLK_UART1 39 +-#define CLK_UART2 40 +-#define CLK_UART3 41 +-#define CLK_UART4 42 +-#define CLK_UART5 43 +-#define CLK_UART6 44 +-#define CLK_DE1 45 +-#define CLK_DE2 46 +-#define CLK_I2SRX 47 +-#define CLK_I2STX 48 +-#define CLK_HDMI_AUDIO 49 +-#define CLK_HDMI 50 +-#define CLK_SPDIF 51 +-#define CLK_NAND 52 +-#define CLK_ECC 53 +-#define CLK_RMII_REF 54 +-#define CLK_GPIO 55 +- +-/* additional clocks */ +-#define CLK_APB 56 +-#define CLK_DMAC 57 +-#define CLK_NIC 58 +-#define CLK_ETHERNET 59 +- +-#define CLK_NR_CLKS (CLK_ETHERNET + 1) +- +-#endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/actions,s700-cmu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/actions,s700-cmu.h +deleted file mode 100644 +index 3e1942996724..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/actions,s700-cmu.h ++++ /dev/null +@@ -1,118 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 +- * +- * Device Tree binding constants for Actions Semi S700 Clock Management Unit +- * +- * Copyright (c) 2014 Actions Semi Inc. +- * Author: David Liu +- * +- * Author: Pathiban Nallathambi +- * Author: Saravanan Sekar +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_S700_H +-#define __DT_BINDINGS_CLOCK_S700_H +- +-#define CLK_NONE 0 +- +-/* pll clocks */ +-#define CLK_CORE_PLL 1 +-#define CLK_DEV_PLL 2 +-#define CLK_DDR_PLL 3 +-#define CLK_NAND_PLL 4 +-#define CLK_DISPLAY_PLL 5 +-#define CLK_TVOUT_PLL 6 +-#define CLK_CVBS_PLL 7 +-#define CLK_AUDIO_PLL 8 +-#define CLK_ETHERNET_PLL 9 +- +-/* system clock */ +-#define CLK_CPU 10 +-#define CLK_DEV 11 +-#define CLK_AHB 12 +-#define CLK_APB 13 +-#define CLK_DMAC 14 +-#define CLK_NOC0_CLK_MUX 15 +-#define CLK_NOC1_CLK_MUX 16 +-#define CLK_HP_CLK_MUX 17 +-#define CLK_HP_CLK_DIV 18 +-#define CLK_NOC1_CLK_DIV 19 +-#define CLK_NOC0 20 +-#define CLK_NOC1 21 +-#define CLK_SENOR_SRC 22 +- +-/* peripheral device clock */ +-#define CLK_GPIO 23 +-#define CLK_TIMER 24 +-#define CLK_DSI 25 +-#define CLK_CSI 26 +-#define CLK_SI 27 +-#define CLK_DE 28 +-#define CLK_HDE 29 +-#define CLK_VDE 30 +-#define CLK_VCE 31 +-#define CLK_NAND 32 +-#define CLK_SD0 33 +-#define CLK_SD1 34 +-#define CLK_SD2 35 +- +-#define CLK_UART0 36 +-#define CLK_UART1 37 +-#define CLK_UART2 38 +-#define CLK_UART3 39 +-#define CLK_UART4 40 +-#define CLK_UART5 41 +-#define CLK_UART6 42 +- +-#define CLK_PWM0 43 +-#define CLK_PWM1 44 +-#define CLK_PWM2 45 +-#define CLK_PWM3 46 +-#define CLK_PWM4 47 +-#define CLK_PWM5 48 +-#define CLK_GPU3D 49 +- +-#define CLK_I2C0 50 +-#define CLK_I2C1 51 +-#define CLK_I2C2 52 +-#define CLK_I2C3 53 +- +-#define CLK_SPI0 54 +-#define CLK_SPI1 55 +-#define CLK_SPI2 56 +-#define CLK_SPI3 57 +- +-#define CLK_USB3_480MPLL0 58 +-#define CLK_USB3_480MPHY0 59 +-#define CLK_USB3_5GPHY 60 +-#define CLK_USB3_CCE 61 +-#define CLK_USB3_MAC 62 +- +-#define CLK_LCD 63 +-#define CLK_HDMI_AUDIO 64 +-#define CLK_I2SRX 65 +-#define CLK_I2STX 66 +- +-#define CLK_SENSOR0 67 +-#define CLK_SENSOR1 68 +- +-#define CLK_HDMI_DEV 69 +- +-#define CLK_ETHERNET 70 +-#define CLK_RMII_REF 71 +- +-#define CLK_USB2H0_PLLEN 72 +-#define CLK_USB2H0_PHY 73 +-#define CLK_USB2H0_CCE 74 +-#define CLK_USB2H1_PLLEN 75 +-#define CLK_USB2H1_PHY 76 +-#define CLK_USB2H1_CCE 77 +- +-#define CLK_TVOUT 78 +- +-#define CLK_THERMAL_SENSOR 79 +- +-#define CLK_IRC_SWITCH 80 +-#define CLK_PCM1 81 +-#define CLK_NR_CLKS (CLK_PCM1 + 1) +- +-#endif /* __DT_BINDINGS_CLOCK_S700_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/actions,s900-cmu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/actions,s900-cmu.h +deleted file mode 100644 +index 7c1251565f43..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/actions,s900-cmu.h ++++ /dev/null +@@ -1,129 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-// +-// Device Tree binding constants for Actions Semi S900 Clock Management Unit +-// +-// Copyright (c) 2014 Actions Semi Inc. +-// Copyright (c) 2018 Linaro Ltd. +- +-#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H +-#define __DT_BINDINGS_CLOCK_S900_CMU_H +- +-#define CLK_NONE 0 +- +-/* fixed rate clocks */ +-#define CLK_LOSC 1 +-#define CLK_HOSC 2 +- +-/* pll clocks */ +-#define CLK_CORE_PLL 3 +-#define CLK_DEV_PLL 4 +-#define CLK_DDR_PLL 5 +-#define CLK_NAND_PLL 6 +-#define CLK_DISPLAY_PLL 7 +-#define CLK_DSI_PLL 8 +-#define CLK_ASSIST_PLL 9 +-#define CLK_AUDIO_PLL 10 +- +-/* system clock */ +-#define CLK_CPU 15 +-#define CLK_DEV 16 +-#define CLK_NOC 17 +-#define CLK_NOC_MUX 18 +-#define CLK_NOC_DIV 19 +-#define CLK_AHB 20 +-#define CLK_APB 21 +-#define CLK_DMAC 22 +- +-/* peripheral device clock */ +-#define CLK_GPIO 23 +- +-#define CLK_BISP 24 +-#define CLK_CSI0 25 +-#define CLK_CSI1 26 +- +-#define CLK_DE0 27 +-#define CLK_DE1 28 +-#define CLK_DE2 29 +-#define CLK_DE3 30 +-#define CLK_DSI 32 +- +-#define CLK_GPU 33 +-#define CLK_GPU_CORE 34 +-#define CLK_GPU_MEM 35 +-#define CLK_GPU_SYS 36 +- +-#define CLK_HDE 37 +-#define CLK_I2C0 38 +-#define CLK_I2C1 39 +-#define CLK_I2C2 40 +-#define CLK_I2C3 41 +-#define CLK_I2C4 42 +-#define CLK_I2C5 43 +-#define CLK_I2SRX 44 +-#define CLK_I2STX 45 +-#define CLK_IMX 46 +-#define CLK_LCD 47 +-#define CLK_NAND0 48 +-#define CLK_NAND1 49 +-#define CLK_PWM0 50 +-#define CLK_PWM1 51 +-#define CLK_PWM2 52 +-#define CLK_PWM3 53 +-#define CLK_PWM4 54 +-#define CLK_PWM5 55 +-#define CLK_SD0 56 +-#define CLK_SD1 57 +-#define CLK_SD2 58 +-#define CLK_SD3 59 +-#define CLK_SENSOR 60 +-#define CLK_SPEED_SENSOR 61 +-#define CLK_SPI0 62 +-#define CLK_SPI1 63 +-#define CLK_SPI2 64 +-#define CLK_SPI3 65 +-#define CLK_THERMAL_SENSOR 66 +-#define CLK_UART0 67 +-#define CLK_UART1 68 +-#define CLK_UART2 69 +-#define CLK_UART3 70 +-#define CLK_UART4 71 +-#define CLK_UART5 72 +-#define CLK_UART6 73 +-#define CLK_VCE 74 +-#define CLK_VDE 75 +- +-#define CLK_USB3_480MPLL0 76 +-#define CLK_USB3_480MPHY0 77 +-#define CLK_USB3_5GPHY 78 +-#define CLK_USB3_CCE 79 +-#define CLK_USB3_MAC 80 +- +-#define CLK_TIMER 83 +- +-#define CLK_HDMI_AUDIO 84 +- +-#define CLK_24M 85 +- +-#define CLK_EDP 86 +- +-#define CLK_24M_EDP 87 +-#define CLK_EDP_PLL 88 +-#define CLK_EDP_LINK 89 +- +-#define CLK_USB2H0_PLLEN 90 +-#define CLK_USB2H0_PHY 91 +-#define CLK_USB2H0_CCE 92 +-#define CLK_USB2H1_PLLEN 93 +-#define CLK_USB2H1_PHY 94 +-#define CLK_USB2H1_CCE 95 +- +-#define CLK_DDR0 96 +-#define CLK_DDR1 97 +-#define CLK_DMM 98 +- +-#define CLK_ETH_MAC 99 +-#define CLK_RMII_REF 100 +- +-#define CLK_NR_CLKS (CLK_RMII_REF + 1) +- +-#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/agilex-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/agilex-clock.h +deleted file mode 100644 +index 06feca07e08e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/agilex-clock.h ++++ /dev/null +@@ -1,72 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2019, Intel Corporation +- */ +- +-#ifndef __AGILEX_CLOCK_H +-#define __AGILEX_CLOCK_H +- +-/* fixed rate clocks */ +-#define AGILEX_OSC1 0 +-#define AGILEX_CB_INTOSC_HS_DIV2_CLK 1 +-#define AGILEX_CB_INTOSC_LS_CLK 2 +-#define AGILEX_L4_SYS_FREE_CLK 3 +-#define AGILEX_F2S_FREE_CLK 4 +- +-/* PLL clocks */ +-#define AGILEX_MAIN_PLL_CLK 5 +-#define AGILEX_MAIN_PLL_C0_CLK 6 +-#define AGILEX_MAIN_PLL_C1_CLK 7 +-#define AGILEX_MAIN_PLL_C2_CLK 8 +-#define AGILEX_MAIN_PLL_C3_CLK 9 +-#define AGILEX_PERIPH_PLL_CLK 10 +-#define AGILEX_PERIPH_PLL_C0_CLK 11 +-#define AGILEX_PERIPH_PLL_C1_CLK 12 +-#define AGILEX_PERIPH_PLL_C2_CLK 13 +-#define AGILEX_PERIPH_PLL_C3_CLK 14 +-#define AGILEX_MPU_FREE_CLK 15 +-#define AGILEX_MPU_CCU_CLK 16 +-#define AGILEX_BOOT_CLK 17 +- +-/* fixed factor clocks */ +-#define AGILEX_L3_MAIN_FREE_CLK 18 +-#define AGILEX_NOC_FREE_CLK 19 +-#define AGILEX_S2F_USR0_CLK 20 +-#define AGILEX_NOC_CLK 21 +-#define AGILEX_EMAC_A_FREE_CLK 22 +-#define AGILEX_EMAC_B_FREE_CLK 23 +-#define AGILEX_EMAC_PTP_FREE_CLK 24 +-#define AGILEX_GPIO_DB_FREE_CLK 25 +-#define AGILEX_SDMMC_FREE_CLK 26 +-#define AGILEX_S2F_USER0_FREE_CLK 27 +-#define AGILEX_S2F_USER1_FREE_CLK 28 +-#define AGILEX_PSI_REF_FREE_CLK 29 +- +-/* Gate clocks */ +-#define AGILEX_MPU_CLK 30 +-#define AGILEX_MPU_L2RAM_CLK 31 +-#define AGILEX_MPU_PERIPH_CLK 32 +-#define AGILEX_L4_MAIN_CLK 33 +-#define AGILEX_L4_MP_CLK 34 +-#define AGILEX_L4_SP_CLK 35 +-#define AGILEX_CS_AT_CLK 36 +-#define AGILEX_CS_TRACE_CLK 37 +-#define AGILEX_CS_PDBG_CLK 38 +-#define AGILEX_CS_TIMER_CLK 39 +-#define AGILEX_S2F_USER0_CLK 40 +-#define AGILEX_EMAC0_CLK 41 +-#define AGILEX_EMAC1_CLK 43 +-#define AGILEX_EMAC2_CLK 44 +-#define AGILEX_EMAC_PTP_CLK 45 +-#define AGILEX_GPIO_DB_CLK 46 +-#define AGILEX_NAND_CLK 47 +-#define AGILEX_PSI_REF_CLK 48 +-#define AGILEX_S2F_USER1_CLK 49 +-#define AGILEX_SDMMC_CLK 50 +-#define AGILEX_SPI_M_CLK 51 +-#define AGILEX_USB_CLK 52 +-#define AGILEX_NAND_X_CLK 53 +-#define AGILEX_NAND_ECC_CLK 54 +-#define AGILEX_NUM_CLKS 55 +- +-#endif /* __AGILEX_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/alphascale,asm9260.h b/scripts/dtc/include-prefixes/dt-bindings/clock/alphascale,asm9260.h +deleted file mode 100644 +index d3871c63308b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/alphascale,asm9260.h ++++ /dev/null +@@ -1,89 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2014 Oleksij Rempel +- */ +- +-#ifndef _DT_BINDINGS_CLK_ASM9260_H +-#define _DT_BINDINGS_CLK_ASM9260_H +- +-/* ahb gate */ +-#define CLKID_AHB_ROM 0 +-#define CLKID_AHB_RAM 1 +-#define CLKID_AHB_GPIO 2 +-#define CLKID_AHB_MAC 3 +-#define CLKID_AHB_EMI 4 +-#define CLKID_AHB_USB0 5 +-#define CLKID_AHB_USB1 6 +-#define CLKID_AHB_DMA0 7 +-#define CLKID_AHB_DMA1 8 +-#define CLKID_AHB_UART0 9 +-#define CLKID_AHB_UART1 10 +-#define CLKID_AHB_UART2 11 +-#define CLKID_AHB_UART3 12 +-#define CLKID_AHB_UART4 13 +-#define CLKID_AHB_UART5 14 +-#define CLKID_AHB_UART6 15 +-#define CLKID_AHB_UART7 16 +-#define CLKID_AHB_UART8 17 +-#define CLKID_AHB_UART9 18 +-#define CLKID_AHB_I2S0 19 +-#define CLKID_AHB_I2C0 20 +-#define CLKID_AHB_I2C1 21 +-#define CLKID_AHB_SSP0 22 +-#define CLKID_AHB_IOCONFIG 23 +-#define CLKID_AHB_WDT 24 +-#define CLKID_AHB_CAN0 25 +-#define CLKID_AHB_CAN1 26 +-#define CLKID_AHB_MPWM 27 +-#define CLKID_AHB_SPI0 28 +-#define CLKID_AHB_SPI1 29 +-#define CLKID_AHB_QEI 30 +-#define CLKID_AHB_QUADSPI0 31 +-#define CLKID_AHB_CAMIF 32 +-#define CLKID_AHB_LCDIF 33 +-#define CLKID_AHB_TIMER0 34 +-#define CLKID_AHB_TIMER1 35 +-#define CLKID_AHB_TIMER2 36 +-#define CLKID_AHB_TIMER3 37 +-#define CLKID_AHB_IRQ 38 +-#define CLKID_AHB_RTC 39 +-#define CLKID_AHB_NAND 40 +-#define CLKID_AHB_ADC0 41 +-#define CLKID_AHB_LED 42 +-#define CLKID_AHB_DAC0 43 +-#define CLKID_AHB_LCD 44 +-#define CLKID_AHB_I2S1 45 +-#define CLKID_AHB_MAC1 46 +- +-/* devider */ +-#define CLKID_SYS_CPU 47 +-#define CLKID_SYS_AHB 48 +-#define CLKID_SYS_I2S0M 49 +-#define CLKID_SYS_I2S0S 50 +-#define CLKID_SYS_I2S1M 51 +-#define CLKID_SYS_I2S1S 52 +-#define CLKID_SYS_UART0 53 +-#define CLKID_SYS_UART1 54 +-#define CLKID_SYS_UART2 55 +-#define CLKID_SYS_UART3 56 +-#define CLKID_SYS_UART4 56 +-#define CLKID_SYS_UART5 57 +-#define CLKID_SYS_UART6 58 +-#define CLKID_SYS_UART7 59 +-#define CLKID_SYS_UART8 60 +-#define CLKID_SYS_UART9 61 +-#define CLKID_SYS_SPI0 62 +-#define CLKID_SYS_SPI1 63 +-#define CLKID_SYS_QUADSPI 64 +-#define CLKID_SYS_SSP0 65 +-#define CLKID_SYS_NAND 66 +-#define CLKID_SYS_TRACE 67 +-#define CLKID_SYS_CAMM 68 +-#define CLKID_SYS_WDT 69 +-#define CLKID_SYS_CLKOUT 70 +-#define CLKID_SYS_MAC 71 +-#define CLKID_SYS_LCD 72 +-#define CLKID_SYS_ADCANA 73 +- +-#define MAX_CLKS 74 +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/am3.h b/scripts/dtc/include-prefixes/dt-bindings/clock/am3.h +deleted file mode 100644 +index 894951541276..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/am3.h ++++ /dev/null +@@ -1,219 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2017 Texas Instruments, Inc. +- */ +-#ifndef __DT_BINDINGS_CLK_AM3_H +-#define __DT_BINDINGS_CLK_AM3_H +- +-#define AM3_CLKCTRL_OFFSET 0x0 +-#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) +- +-/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ +- +-/* l4_per clocks */ +-#define AM3_L4_PER_CLKCTRL_OFFSET 0x14 +-#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) +-#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14) +-#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18) +-#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c) +-#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24) +-#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28) +-#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c) +-#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30) +-#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34) +-#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38) +-#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c) +-#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40) +-#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44) +-#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48) +-#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c) +-#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50) +-#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60) +-#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68) +-#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c) +-#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70) +-#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74) +-#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78) +-#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c) +-#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80) +-#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84) +-#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88) +-#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90) +-#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94) +-#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0) +-#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac) +-#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0) +-#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4) +-#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc) +-#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0) +-#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4) +-#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc) +-#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4) +-#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8) +-#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc) +-#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0) +-#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8) +-#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec) +-#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0) +-#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4) +-#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8) +-#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc) +-#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100) +-#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c) +-#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110) +-#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120) +-#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130) +-#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c) +- +-/* l4_wkup clocks */ +-#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4 +-#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET) +-#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4) +-#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8) +-#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc) +-#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14) +-#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0) +-#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4) +-#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8) +-#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc) +-#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0) +-#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4) +-#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8) +-#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4) +- +-/* mpu clocks */ +-#define AM3_MPU_CLKCTRL_OFFSET 0x4 +-#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET) +-#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4) +- +-/* l4_rtc clocks */ +-#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) +- +-/* gfx_l3 clocks */ +-#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4 +-#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET) +-#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4) +- +-/* l4_cefuse clocks */ +-#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20 +-#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET) +-#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20) +- +-/* XXX: Compatibility part end */ +- +-/* l4ls clocks */ +-#define AM3_L4LS_CLKCTRL_OFFSET 0x38 +-#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET) +-#define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38) +-#define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c) +-#define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40) +-#define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44) +-#define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48) +-#define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c) +-#define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50) +-#define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60) +-#define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c) +-#define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70) +-#define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74) +-#define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78) +-#define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c) +-#define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80) +-#define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84) +-#define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88) +-#define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90) +-#define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac) +-#define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0) +-#define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4) +-#define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0) +-#define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4) +-#define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc) +-#define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4) +-#define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8) +-#define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec) +-#define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0) +-#define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4) +-#define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c) +-#define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110) +-#define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130) +- +-/* l3s clocks */ +-#define AM3_L3S_CLKCTRL_OFFSET 0x1c +-#define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET) +-#define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c) +-#define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30) +-#define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34) +-#define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68) +-#define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8) +- +-/* l3 clocks */ +-#define AM3_L3_CLKCTRL_OFFSET 0x24 +-#define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET) +-#define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24) +-#define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28) +-#define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c) +-#define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94) +-#define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0) +-#define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc) +-#define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc) +-#define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0) +-#define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc) +-#define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100) +- +-/* l4hs clocks */ +-#define AM3_L4HS_CLKCTRL_OFFSET 0x120 +-#define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET) +-#define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120) +- +-/* pruss_ocp clocks */ +-#define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8 +-#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET) +-#define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8) +- +-/* cpsw_125mhz clocks */ +-#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14) +- +-/* lcdc clocks */ +-#define AM3_LCDC_CLKCTRL_OFFSET 0x18 +-#define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET) +-#define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18) +- +-/* clk_24mhz clocks */ +-#define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c +-#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET) +-#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c) +- +-/* l4_wkup clocks */ +-#define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4) +-#define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8) +-#define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc) +-#define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4) +-#define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8) +-#define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc) +-#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0) +-#define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4) +-#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8) +-#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4) +- +-/* l3_aon clocks */ +-#define AM3_L3_AON_CLKCTRL_OFFSET 0x14 +-#define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET) +-#define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14) +- +-/* l4_wkup_aon clocks */ +-#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0 +-#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET) +-#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0) +- +-/* mpu clocks */ +-#define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4) +- +-/* l4_rtc clocks */ +-#define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) +- +-/* gfx_l3 clocks */ +-#define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4) +- +-/* l4_cefuse clocks */ +-#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/am4.h b/scripts/dtc/include-prefixes/dt-bindings/clock/am4.h +deleted file mode 100644 +index d961e7cb3682..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/am4.h ++++ /dev/null +@@ -1,237 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2017 Texas Instruments, Inc. +- */ +-#ifndef __DT_BINDINGS_CLK_AM4_H +-#define __DT_BINDINGS_CLK_AM4_H +- +-#define AM4_CLKCTRL_OFFSET 0x20 +-#define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET) +- +-/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ +- +-/* l4_wkup clocks */ +-#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120) +-#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220) +-#define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228) +-#define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230) +-#define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328) +-#define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338) +-#define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340) +-#define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348) +-#define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350) +-#define AM4_SMARTREFLEX1_CLKCTRL AM4_CLKCTRL_INDEX(0x358) +-#define AM4_CONTROL_CLKCTRL AM4_CLKCTRL_INDEX(0x360) +-#define AM4_GPIO1_CLKCTRL AM4_CLKCTRL_INDEX(0x368) +- +-/* mpu clocks */ +-#define AM4_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20) +- +-/* gfx_l3 clocks */ +-#define AM4_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20) +- +-/* l4_rtc clocks */ +-#define AM4_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20) +- +-/* l4_per clocks */ +-#define AM4_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20) +-#define AM4_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28) +-#define AM4_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30) +-#define AM4_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40) +-#define AM4_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50) +-#define AM4_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58) +-#define AM4_VPFE0_CLKCTRL AM4_CLKCTRL_INDEX(0x68) +-#define AM4_VPFE1_CLKCTRL AM4_CLKCTRL_INDEX(0x70) +-#define AM4_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78) +-#define AM4_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80) +-#define AM4_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88) +-#define AM4_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90) +-#define AM4_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0) +-#define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220) +-#define AM4_MCASP0_CLKCTRL AM4_CLKCTRL_INDEX(0x238) +-#define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240) +-#define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248) +-#define AM4_QSPI_CLKCTRL AM4_CLKCTRL_INDEX(0x258) +-#define AM4_USB_OTG_SS0_CLKCTRL AM4_CLKCTRL_INDEX(0x260) +-#define AM4_USB_OTG_SS1_CLKCTRL AM4_CLKCTRL_INDEX(0x268) +-#define AM4_PRUSS_CLKCTRL AM4_CLKCTRL_INDEX(0x320) +-#define AM4_L4_LS_CLKCTRL AM4_CLKCTRL_INDEX(0x420) +-#define AM4_D_CAN0_CLKCTRL AM4_CLKCTRL_INDEX(0x428) +-#define AM4_D_CAN1_CLKCTRL AM4_CLKCTRL_INDEX(0x430) +-#define AM4_EPWMSS0_CLKCTRL AM4_CLKCTRL_INDEX(0x438) +-#define AM4_EPWMSS1_CLKCTRL AM4_CLKCTRL_INDEX(0x440) +-#define AM4_EPWMSS2_CLKCTRL AM4_CLKCTRL_INDEX(0x448) +-#define AM4_EPWMSS3_CLKCTRL AM4_CLKCTRL_INDEX(0x450) +-#define AM4_EPWMSS4_CLKCTRL AM4_CLKCTRL_INDEX(0x458) +-#define AM4_EPWMSS5_CLKCTRL AM4_CLKCTRL_INDEX(0x460) +-#define AM4_ELM_CLKCTRL AM4_CLKCTRL_INDEX(0x468) +-#define AM4_GPIO2_CLKCTRL AM4_CLKCTRL_INDEX(0x478) +-#define AM4_GPIO3_CLKCTRL AM4_CLKCTRL_INDEX(0x480) +-#define AM4_GPIO4_CLKCTRL AM4_CLKCTRL_INDEX(0x488) +-#define AM4_GPIO5_CLKCTRL AM4_CLKCTRL_INDEX(0x490) +-#define AM4_GPIO6_CLKCTRL AM4_CLKCTRL_INDEX(0x498) +-#define AM4_HDQ1W_CLKCTRL AM4_CLKCTRL_INDEX(0x4a0) +-#define AM4_I2C2_CLKCTRL AM4_CLKCTRL_INDEX(0x4a8) +-#define AM4_I2C3_CLKCTRL AM4_CLKCTRL_INDEX(0x4b0) +-#define AM4_MAILBOX_CLKCTRL AM4_CLKCTRL_INDEX(0x4b8) +-#define AM4_MMC1_CLKCTRL AM4_CLKCTRL_INDEX(0x4c0) +-#define AM4_MMC2_CLKCTRL AM4_CLKCTRL_INDEX(0x4c8) +-#define AM4_RNG_CLKCTRL AM4_CLKCTRL_INDEX(0x4e0) +-#define AM4_SPI0_CLKCTRL AM4_CLKCTRL_INDEX(0x500) +-#define AM4_SPI1_CLKCTRL AM4_CLKCTRL_INDEX(0x508) +-#define AM4_SPI2_CLKCTRL AM4_CLKCTRL_INDEX(0x510) +-#define AM4_SPI3_CLKCTRL AM4_CLKCTRL_INDEX(0x518) +-#define AM4_SPI4_CLKCTRL AM4_CLKCTRL_INDEX(0x520) +-#define AM4_SPINLOCK_CLKCTRL AM4_CLKCTRL_INDEX(0x528) +-#define AM4_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x530) +-#define AM4_TIMER3_CLKCTRL AM4_CLKCTRL_INDEX(0x538) +-#define AM4_TIMER4_CLKCTRL AM4_CLKCTRL_INDEX(0x540) +-#define AM4_TIMER5_CLKCTRL AM4_CLKCTRL_INDEX(0x548) +-#define AM4_TIMER6_CLKCTRL AM4_CLKCTRL_INDEX(0x550) +-#define AM4_TIMER7_CLKCTRL AM4_CLKCTRL_INDEX(0x558) +-#define AM4_TIMER8_CLKCTRL AM4_CLKCTRL_INDEX(0x560) +-#define AM4_TIMER9_CLKCTRL AM4_CLKCTRL_INDEX(0x568) +-#define AM4_TIMER10_CLKCTRL AM4_CLKCTRL_INDEX(0x570) +-#define AM4_TIMER11_CLKCTRL AM4_CLKCTRL_INDEX(0x578) +-#define AM4_UART2_CLKCTRL AM4_CLKCTRL_INDEX(0x580) +-#define AM4_UART3_CLKCTRL AM4_CLKCTRL_INDEX(0x588) +-#define AM4_UART4_CLKCTRL AM4_CLKCTRL_INDEX(0x590) +-#define AM4_UART5_CLKCTRL AM4_CLKCTRL_INDEX(0x598) +-#define AM4_UART6_CLKCTRL AM4_CLKCTRL_INDEX(0x5a0) +-#define AM4_OCP2SCP0_CLKCTRL AM4_CLKCTRL_INDEX(0x5b8) +-#define AM4_OCP2SCP1_CLKCTRL AM4_CLKCTRL_INDEX(0x5c0) +-#define AM4_EMIF_CLKCTRL AM4_CLKCTRL_INDEX(0x720) +-#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20) +-#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20) +- +-/* XXX: Compatibility part end. */ +- +-/* l3s_tsc clocks */ +-#define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120 +-#define AM4_L3S_TSC_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET) +-#define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120) +- +-/* l4_wkup_aon clocks */ +-#define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228 +-#define AM4_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_AON_CLKCTRL_OFFSET) +-#define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228) +-#define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230) +- +-/* l4_wkup clocks */ +-#define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220 +-#define AM4_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_CLKCTRL_OFFSET) +-#define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220) +-#define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328) +-#define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338) +-#define AM4_L4_WKUP_I2C1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x340) +-#define AM4_L4_WKUP_UART1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x348) +-#define AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x350) +-#define AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x358) +-#define AM4_L4_WKUP_CONTROL_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x360) +-#define AM4_L4_WKUP_GPIO1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x368) +- +-/* mpu clocks */ +-#define AM4_MPU_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20) +- +-/* gfx_l3 clocks */ +-#define AM4_GFX_L3_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20) +- +-/* l4_rtc clocks */ +-#define AM4_L4_RTC_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20) +- +-/* l3 clocks */ +-#define AM4_L3_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20) +-#define AM4_L3_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28) +-#define AM4_L3_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30) +-#define AM4_L3_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40) +-#define AM4_L3_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50) +-#define AM4_L3_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58) +-#define AM4_L3_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78) +-#define AM4_L3_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80) +-#define AM4_L3_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88) +-#define AM4_L3_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90) +-#define AM4_L3_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0) +- +-/* l3s clocks */ +-#define AM4_L3S_CLKCTRL_OFFSET 0x68 +-#define AM4_L3S_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_CLKCTRL_OFFSET) +-#define AM4_L3S_VPFE0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x68) +-#define AM4_L3S_VPFE1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x70) +-#define AM4_L3S_GPMC_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x220) +-#define AM4_L3S_MCASP0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x238) +-#define AM4_L3S_MCASP1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x240) +-#define AM4_L3S_MMC3_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x248) +-#define AM4_L3S_QSPI_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x258) +-#define AM4_L3S_USB_OTG_SS0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x260) +-#define AM4_L3S_USB_OTG_SS1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x268) +- +-/* pruss_ocp clocks */ +-#define AM4_PRUSS_OCP_CLKCTRL_OFFSET 0x320 +-#define AM4_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM4_PRUSS_OCP_CLKCTRL_OFFSET) +-#define AM4_PRUSS_OCP_PRUSS_CLKCTRL AM4_PRUSS_OCP_CLKCTRL_INDEX(0x320) +- +-/* l4ls clocks */ +-#define AM4_L4LS_CLKCTRL_OFFSET 0x420 +-#define AM4_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM4_L4LS_CLKCTRL_OFFSET) +-#define AM4_L4LS_L4_LS_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x420) +-#define AM4_L4LS_D_CAN0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x428) +-#define AM4_L4LS_D_CAN1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x430) +-#define AM4_L4LS_EPWMSS0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x438) +-#define AM4_L4LS_EPWMSS1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x440) +-#define AM4_L4LS_EPWMSS2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x448) +-#define AM4_L4LS_EPWMSS3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x450) +-#define AM4_L4LS_EPWMSS4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x458) +-#define AM4_L4LS_EPWMSS5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x460) +-#define AM4_L4LS_ELM_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x468) +-#define AM4_L4LS_GPIO2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x478) +-#define AM4_L4LS_GPIO3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x480) +-#define AM4_L4LS_GPIO4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x488) +-#define AM4_L4LS_GPIO5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x490) +-#define AM4_L4LS_GPIO6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x498) +-#define AM4_L4LS_HDQ1W_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a0) +-#define AM4_L4LS_I2C2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a8) +-#define AM4_L4LS_I2C3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b0) +-#define AM4_L4LS_MAILBOX_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b8) +-#define AM4_L4LS_MMC1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c0) +-#define AM4_L4LS_MMC2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c8) +-#define AM4_L4LS_RNG_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4e0) +-#define AM4_L4LS_SPI0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x500) +-#define AM4_L4LS_SPI1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x508) +-#define AM4_L4LS_SPI2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x510) +-#define AM4_L4LS_SPI3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x518) +-#define AM4_L4LS_SPI4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x520) +-#define AM4_L4LS_SPINLOCK_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x528) +-#define AM4_L4LS_TIMER2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x530) +-#define AM4_L4LS_TIMER3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x538) +-#define AM4_L4LS_TIMER4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x540) +-#define AM4_L4LS_TIMER5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x548) +-#define AM4_L4LS_TIMER6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x550) +-#define AM4_L4LS_TIMER7_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x558) +-#define AM4_L4LS_TIMER8_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x560) +-#define AM4_L4LS_TIMER9_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x568) +-#define AM4_L4LS_TIMER10_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x570) +-#define AM4_L4LS_TIMER11_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x578) +-#define AM4_L4LS_UART2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x580) +-#define AM4_L4LS_UART3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x588) +-#define AM4_L4LS_UART4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x590) +-#define AM4_L4LS_UART5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x598) +-#define AM4_L4LS_UART6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5a0) +-#define AM4_L4LS_OCP2SCP0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5b8) +-#define AM4_L4LS_OCP2SCP1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5c0) +- +-/* emif clocks */ +-#define AM4_EMIF_CLKCTRL_OFFSET 0x720 +-#define AM4_EMIF_CLKCTRL_INDEX(offset) ((offset) - AM4_EMIF_CLKCTRL_OFFSET) +-#define AM4_EMIF_EMIF_CLKCTRL AM4_EMIF_CLKCTRL_INDEX(0x720) +- +-/* dss clocks */ +-#define AM4_DSS_CLKCTRL_OFFSET 0xa20 +-#define AM4_DSS_CLKCTRL_INDEX(offset) ((offset) - AM4_DSS_CLKCTRL_OFFSET) +-#define AM4_DSS_DSS_CORE_CLKCTRL AM4_DSS_CLKCTRL_INDEX(0xa20) +- +-/* cpsw_125mhz clocks */ +-#define AM4_CPSW_125MHZ_CLKCTRL_OFFSET 0xb20 +-#define AM4_CPSW_125MHZ_CLKCTRL_INDEX(offset) ((offset) - AM4_CPSW_125MHZ_CLKCTRL_OFFSET) +-#define AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL AM4_CPSW_125MHZ_CLKCTRL_INDEX(0xb20) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/aspeed-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/aspeed-clock.h +deleted file mode 100644 +index 9ff4f6e4558c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/aspeed-clock.h ++++ /dev/null +@@ -1,56 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +- +-#ifndef DT_BINDINGS_ASPEED_CLOCK_H +-#define DT_BINDINGS_ASPEED_CLOCK_H +- +-#define ASPEED_CLK_GATE_ECLK 0 +-#define ASPEED_CLK_GATE_GCLK 1 +-#define ASPEED_CLK_GATE_MCLK 2 +-#define ASPEED_CLK_GATE_VCLK 3 +-#define ASPEED_CLK_GATE_BCLK 4 +-#define ASPEED_CLK_GATE_DCLK 5 +-#define ASPEED_CLK_GATE_REFCLK 6 +-#define ASPEED_CLK_GATE_USBPORT2CLK 7 +-#define ASPEED_CLK_GATE_LCLK 8 +-#define ASPEED_CLK_GATE_USBUHCICLK 9 +-#define ASPEED_CLK_GATE_D1CLK 10 +-#define ASPEED_CLK_GATE_YCLK 11 +-#define ASPEED_CLK_GATE_USBPORT1CLK 12 +-#define ASPEED_CLK_GATE_UART1CLK 13 +-#define ASPEED_CLK_GATE_UART2CLK 14 +-#define ASPEED_CLK_GATE_UART5CLK 15 +-#define ASPEED_CLK_GATE_ESPICLK 16 +-#define ASPEED_CLK_GATE_MAC1CLK 17 +-#define ASPEED_CLK_GATE_MAC2CLK 18 +-#define ASPEED_CLK_GATE_RSACLK 19 +-#define ASPEED_CLK_GATE_UART3CLK 20 +-#define ASPEED_CLK_GATE_UART4CLK 21 +-#define ASPEED_CLK_GATE_SDCLK 22 +-#define ASPEED_CLK_GATE_LHCCLK 23 +-#define ASPEED_CLK_HPLL 24 +-#define ASPEED_CLK_AHB 25 +-#define ASPEED_CLK_APB 26 +-#define ASPEED_CLK_UART 27 +-#define ASPEED_CLK_SDIO 28 +-#define ASPEED_CLK_ECLK 29 +-#define ASPEED_CLK_ECLK_MUX 30 +-#define ASPEED_CLK_LHCLK 31 +-#define ASPEED_CLK_MAC 32 +-#define ASPEED_CLK_BCLK 33 +-#define ASPEED_CLK_MPLL 34 +-#define ASPEED_CLK_24M 35 +-#define ASPEED_CLK_MAC1RCLK 36 +-#define ASPEED_CLK_MAC2RCLK 37 +- +-#define ASPEED_RESET_XDMA 0 +-#define ASPEED_RESET_MCTP 1 +-#define ASPEED_RESET_ADC 2 +-#define ASPEED_RESET_JTAG_MASTER 3 +-#define ASPEED_RESET_MIC 4 +-#define ASPEED_RESET_PWM 5 +-#define ASPEED_RESET_PECI 6 +-#define ASPEED_RESET_I2C 7 +-#define ASPEED_RESET_AHB 8 +-#define ASPEED_RESET_CRT1 9 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/ast2600-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/ast2600-clock.h +deleted file mode 100644 +index 62b9520a00fd..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/ast2600-clock.h ++++ /dev/null +@@ -1,117 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */ +-#ifndef DT_BINDINGS_AST2600_CLOCK_H +-#define DT_BINDINGS_AST2600_CLOCK_H +- +-#define ASPEED_CLK_GATE_ECLK 0 +-#define ASPEED_CLK_GATE_GCLK 1 +- +-#define ASPEED_CLK_GATE_MCLK 2 +- +-#define ASPEED_CLK_GATE_VCLK 3 +-#define ASPEED_CLK_GATE_BCLK 4 +-#define ASPEED_CLK_GATE_DCLK 5 +- +-#define ASPEED_CLK_GATE_LCLK 6 +-#define ASPEED_CLK_GATE_LHCCLK 7 +- +-#define ASPEED_CLK_GATE_D1CLK 8 +-#define ASPEED_CLK_GATE_YCLK 9 +- +-#define ASPEED_CLK_GATE_REF0CLK 10 +-#define ASPEED_CLK_GATE_REF1CLK 11 +- +-#define ASPEED_CLK_GATE_ESPICLK 12 +- +-#define ASPEED_CLK_GATE_USBUHCICLK 13 +-#define ASPEED_CLK_GATE_USBPORT1CLK 14 +-#define ASPEED_CLK_GATE_USBPORT2CLK 15 +- +-#define ASPEED_CLK_GATE_RSACLK 16 +-#define ASPEED_CLK_GATE_RVASCLK 17 +- +-#define ASPEED_CLK_GATE_MAC1CLK 18 +-#define ASPEED_CLK_GATE_MAC2CLK 19 +-#define ASPEED_CLK_GATE_MAC3CLK 20 +-#define ASPEED_CLK_GATE_MAC4CLK 21 +- +-#define ASPEED_CLK_GATE_UART1CLK 22 +-#define ASPEED_CLK_GATE_UART2CLK 23 +-#define ASPEED_CLK_GATE_UART3CLK 24 +-#define ASPEED_CLK_GATE_UART4CLK 25 +-#define ASPEED_CLK_GATE_UART5CLK 26 +-#define ASPEED_CLK_GATE_UART6CLK 27 +-#define ASPEED_CLK_GATE_UART7CLK 28 +-#define ASPEED_CLK_GATE_UART8CLK 29 +-#define ASPEED_CLK_GATE_UART9CLK 30 +-#define ASPEED_CLK_GATE_UART10CLK 31 +-#define ASPEED_CLK_GATE_UART11CLK 32 +-#define ASPEED_CLK_GATE_UART12CLK 33 +-#define ASPEED_CLK_GATE_UART13CLK 34 +- +-#define ASPEED_CLK_GATE_SDCLK 35 +-#define ASPEED_CLK_GATE_EMMCCLK 36 +- +-#define ASPEED_CLK_GATE_I3C0CLK 37 +-#define ASPEED_CLK_GATE_I3C1CLK 38 +-#define ASPEED_CLK_GATE_I3C2CLK 39 +-#define ASPEED_CLK_GATE_I3C3CLK 40 +-#define ASPEED_CLK_GATE_I3C4CLK 41 +-#define ASPEED_CLK_GATE_I3C5CLK 42 +-#define ASPEED_CLK_GATE_I3C6CLK 43 +-#define ASPEED_CLK_GATE_I3C7CLK 44 +- +-#define ASPEED_CLK_GATE_FSICLK 45 +- +-#define ASPEED_CLK_HPLL 46 +-#define ASPEED_CLK_MPLL 47 +-#define ASPEED_CLK_DPLL 48 +-#define ASPEED_CLK_EPLL 49 +-#define ASPEED_CLK_APLL 50 +-#define ASPEED_CLK_AHB 51 +-#define ASPEED_CLK_APB1 52 +-#define ASPEED_CLK_APB2 53 +-#define ASPEED_CLK_BCLK 54 +-#define ASPEED_CLK_D1CLK 55 +-#define ASPEED_CLK_VCLK 56 +-#define ASPEED_CLK_LHCLK 57 +-#define ASPEED_CLK_UART 58 +-#define ASPEED_CLK_UARTX 59 +-#define ASPEED_CLK_SDIO 60 +-#define ASPEED_CLK_EMMC 61 +-#define ASPEED_CLK_ECLK 62 +-#define ASPEED_CLK_ECLK_MUX 63 +-#define ASPEED_CLK_MAC12 64 +-#define ASPEED_CLK_MAC34 65 +-#define ASPEED_CLK_USBPHY_40M 66 +-#define ASPEED_CLK_MAC1RCLK 67 +-#define ASPEED_CLK_MAC2RCLK 68 +-#define ASPEED_CLK_MAC3RCLK 69 +-#define ASPEED_CLK_MAC4RCLK 70 +- +-/* Only list resets here that are not part of a gate */ +-#define ASPEED_RESET_ADC 55 +-#define ASPEED_RESET_JTAG_MASTER2 54 +-#define ASPEED_RESET_I3C_DMA 39 +-#define ASPEED_RESET_PWM 37 +-#define ASPEED_RESET_PECI 36 +-#define ASPEED_RESET_MII 35 +-#define ASPEED_RESET_I2C 34 +-#define ASPEED_RESET_H2X 31 +-#define ASPEED_RESET_GP_MCU 30 +-#define ASPEED_RESET_DP_MCU 29 +-#define ASPEED_RESET_DP 28 +-#define ASPEED_RESET_RC_XDMA 27 +-#define ASPEED_RESET_GRAPHICS 26 +-#define ASPEED_RESET_DEV_XDMA 25 +-#define ASPEED_RESET_DEV_MCTP 24 +-#define ASPEED_RESET_RC_MCTP 23 +-#define ASPEED_RESET_JTAG_MASTER 22 +-#define ASPEED_RESET_PCIE_DEV_O 21 +-#define ASPEED_RESET_PCIE_DEV_OEN 20 +-#define ASPEED_RESET_PCIE_RC_O 19 +-#define ASPEED_RESET_PCIE_RC_OEN 18 +-#define ASPEED_RESET_PCI_DP 5 +-#define ASPEED_RESET_AHB 1 +-#define ASPEED_RESET_SDRAM 0 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/at91.h b/scripts/dtc/include-prefixes/dt-bindings/clock/at91.h +deleted file mode 100644 +index 98e1b2ab6403..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/at91.h ++++ /dev/null +@@ -1,52 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * This header provides constants for AT91 pmc status. +- * +- * The constants defined in this header are being used in dts. +- */ +- +-#ifndef _DT_BINDINGS_CLK_AT91_H +-#define _DT_BINDINGS_CLK_AT91_H +- +-#define PMC_TYPE_CORE 0 +-#define PMC_TYPE_SYSTEM 1 +-#define PMC_TYPE_PERIPHERAL 2 +-#define PMC_TYPE_GCK 3 +-#define PMC_TYPE_PROGRAMMABLE 4 +- +-#define PMC_SLOW 0 +-#define PMC_MCK 1 +-#define PMC_UTMI 2 +-#define PMC_MAIN 3 +-#define PMC_MCK2 4 +-#define PMC_I2S0_MUX 5 +-#define PMC_I2S1_MUX 6 +-#define PMC_PLLACK 7 +-#define PMC_PLLBCK 8 +-#define PMC_AUDIOPLLCK 9 +- +-/* SAMA7G5 */ +-#define PMC_CPUPLL (PMC_MAIN + 1) +-#define PMC_SYSPLL (PMC_MAIN + 2) +-#define PMC_DDRPLL (PMC_MAIN + 3) +-#define PMC_IMGPLL (PMC_MAIN + 4) +-#define PMC_BAUDPLL (PMC_MAIN + 5) +-#define PMC_AUDIOPMCPLL (PMC_MAIN + 6) +-#define PMC_AUDIOIOPLL (PMC_MAIN + 7) +-#define PMC_ETHPLL (PMC_MAIN + 8) +-#define PMC_CPU (PMC_MAIN + 9) +- +-#ifndef AT91_PMC_MOSCS +-#define AT91_PMC_MOSCS 0 /* MOSCS Flag */ +-#define AT91_PMC_LOCKA 1 /* PLLA Lock */ +-#define AT91_PMC_LOCKB 2 /* PLLB Lock */ +-#define AT91_PMC_MCKRDY 3 /* Master Clock */ +-#define AT91_PMC_LOCKU 6 /* UPLL Lock */ +-#define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */ +-#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */ +-#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */ +-#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */ +-#define AT91_PMC_GCKRDY 24 /* Generated Clocks */ +-#endif +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/ath79-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/ath79-clk.h +deleted file mode 100644 +index eec8f399b9e6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/ath79-clk.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2014, 2016 Antony Pavlov +- */ +- +-#ifndef __DT_BINDINGS_ATH79_CLK_H +-#define __DT_BINDINGS_ATH79_CLK_H +- +-#define ATH79_CLK_CPU 0 +-#define ATH79_CLK_DDR 1 +-#define ATH79_CLK_AHB 2 +-#define ATH79_CLK_REF 3 +-#define ATH79_CLK_MDIO 4 +- +-#define ATH79_CLK_END 5 +- +-#endif /* __DT_BINDINGS_ATH79_CLK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/axg-aoclkc.h b/scripts/dtc/include-prefixes/dt-bindings/clock/axg-aoclkc.h +deleted file mode 100644 +index 8ec4a269c7a6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/axg-aoclkc.h ++++ /dev/null +@@ -1,31 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +-/* +- * Copyright (c) 2016 BayLibre, SAS +- * Author: Neil Armstrong +- * +- * Copyright (c) 2018 Amlogic, inc. +- * Author: Qiufang Dai +- */ +- +-#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK +-#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK +- +-#define CLKID_AO_REMOTE 0 +-#define CLKID_AO_I2C_MASTER 1 +-#define CLKID_AO_I2C_SLAVE 2 +-#define CLKID_AO_UART1 3 +-#define CLKID_AO_UART2 4 +-#define CLKID_AO_IR_BLASTER 5 +-#define CLKID_AO_SAR_ADC 6 +-#define CLKID_AO_CLK81 7 +-#define CLKID_AO_SAR_ADC_SEL 8 +-#define CLKID_AO_SAR_ADC_DIV 9 +-#define CLKID_AO_SAR_ADC_CLK 10 +-#define CLKID_AO_CTS_OSCIN 11 +-#define CLKID_AO_32K_PRE 12 +-#define CLKID_AO_32K_DIV 13 +-#define CLKID_AO_32K_SEL 14 +-#define CLKID_AO_32K 15 +-#define CLKID_AO_CTS_RTC_OSCIN 16 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/axg-audio-clkc.h b/scripts/dtc/include-prefixes/dt-bindings/clock/axg-audio-clkc.h +deleted file mode 100644 +index f561f5c5ef8f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/axg-audio-clkc.h ++++ /dev/null +@@ -1,94 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +-/* +- * Copyright (c) 2018 Baylibre SAS. +- * Author: Jerome Brunet +- */ +- +-#ifndef __AXG_AUDIO_CLKC_BINDINGS_H +-#define __AXG_AUDIO_CLKC_BINDINGS_H +- +-#define AUD_CLKID_DDR_ARB 29 +-#define AUD_CLKID_PDM 30 +-#define AUD_CLKID_TDMIN_A 31 +-#define AUD_CLKID_TDMIN_B 32 +-#define AUD_CLKID_TDMIN_C 33 +-#define AUD_CLKID_TDMIN_LB 34 +-#define AUD_CLKID_TDMOUT_A 35 +-#define AUD_CLKID_TDMOUT_B 36 +-#define AUD_CLKID_TDMOUT_C 37 +-#define AUD_CLKID_FRDDR_A 38 +-#define AUD_CLKID_FRDDR_B 39 +-#define AUD_CLKID_FRDDR_C 40 +-#define AUD_CLKID_TODDR_A 41 +-#define AUD_CLKID_TODDR_B 42 +-#define AUD_CLKID_TODDR_C 43 +-#define AUD_CLKID_LOOPBACK 44 +-#define AUD_CLKID_SPDIFIN 45 +-#define AUD_CLKID_SPDIFOUT 46 +-#define AUD_CLKID_RESAMPLE 47 +-#define AUD_CLKID_POWER_DETECT 48 +-#define AUD_CLKID_MST_A_MCLK 49 +-#define AUD_CLKID_MST_B_MCLK 50 +-#define AUD_CLKID_MST_C_MCLK 51 +-#define AUD_CLKID_MST_D_MCLK 52 +-#define AUD_CLKID_MST_E_MCLK 53 +-#define AUD_CLKID_MST_F_MCLK 54 +-#define AUD_CLKID_SPDIFOUT_CLK 55 +-#define AUD_CLKID_SPDIFIN_CLK 56 +-#define AUD_CLKID_PDM_DCLK 57 +-#define AUD_CLKID_PDM_SYSCLK 58 +-#define AUD_CLKID_MST_A_SCLK 79 +-#define AUD_CLKID_MST_B_SCLK 80 +-#define AUD_CLKID_MST_C_SCLK 81 +-#define AUD_CLKID_MST_D_SCLK 82 +-#define AUD_CLKID_MST_E_SCLK 83 +-#define AUD_CLKID_MST_F_SCLK 84 +-#define AUD_CLKID_MST_A_LRCLK 86 +-#define AUD_CLKID_MST_B_LRCLK 87 +-#define AUD_CLKID_MST_C_LRCLK 88 +-#define AUD_CLKID_MST_D_LRCLK 89 +-#define AUD_CLKID_MST_E_LRCLK 90 +-#define AUD_CLKID_MST_F_LRCLK 91 +-#define AUD_CLKID_TDMIN_A_SCLK_SEL 116 +-#define AUD_CLKID_TDMIN_B_SCLK_SEL 117 +-#define AUD_CLKID_TDMIN_C_SCLK_SEL 118 +-#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119 +-#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120 +-#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121 +-#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122 +-#define AUD_CLKID_TDMIN_A_SCLK 123 +-#define AUD_CLKID_TDMIN_B_SCLK 124 +-#define AUD_CLKID_TDMIN_C_SCLK 125 +-#define AUD_CLKID_TDMIN_LB_SCLK 126 +-#define AUD_CLKID_TDMOUT_A_SCLK 127 +-#define AUD_CLKID_TDMOUT_B_SCLK 128 +-#define AUD_CLKID_TDMOUT_C_SCLK 129 +-#define AUD_CLKID_TDMIN_A_LRCLK 130 +-#define AUD_CLKID_TDMIN_B_LRCLK 131 +-#define AUD_CLKID_TDMIN_C_LRCLK 132 +-#define AUD_CLKID_TDMIN_LB_LRCLK 133 +-#define AUD_CLKID_TDMOUT_A_LRCLK 134 +-#define AUD_CLKID_TDMOUT_B_LRCLK 135 +-#define AUD_CLKID_TDMOUT_C_LRCLK 136 +-#define AUD_CLKID_SPDIFOUT_B 151 +-#define AUD_CLKID_SPDIFOUT_B_CLK 152 +-#define AUD_CLKID_TDM_MCLK_PAD0 155 +-#define AUD_CLKID_TDM_MCLK_PAD1 156 +-#define AUD_CLKID_TDM_LRCLK_PAD0 157 +-#define AUD_CLKID_TDM_LRCLK_PAD1 158 +-#define AUD_CLKID_TDM_LRCLK_PAD2 159 +-#define AUD_CLKID_TDM_SCLK_PAD0 160 +-#define AUD_CLKID_TDM_SCLK_PAD1 161 +-#define AUD_CLKID_TDM_SCLK_PAD2 162 +-#define AUD_CLKID_TOP 163 +-#define AUD_CLKID_TORAM 164 +-#define AUD_CLKID_EQDRC 165 +-#define AUD_CLKID_RESAMPLE_B 166 +-#define AUD_CLKID_TOVAD 167 +-#define AUD_CLKID_LOCKER 168 +-#define AUD_CLKID_SPDIFIN_LB 169 +-#define AUD_CLKID_FRDDR_D 170 +-#define AUD_CLKID_TODDR_D 171 +-#define AUD_CLKID_LOOPBACK_B 172 +- +-#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/axg-clkc.h b/scripts/dtc/include-prefixes/dt-bindings/clock/axg-clkc.h +deleted file mode 100644 +index 93752ea107e3..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/axg-clkc.h ++++ /dev/null +@@ -1,100 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +-/* +- * Meson-AXG clock tree IDs +- * +- * Copyright (c) 2017 Amlogic, Inc. All rights reserved. +- */ +- +-#ifndef __AXG_CLKC_H +-#define __AXG_CLKC_H +- +-#define CLKID_SYS_PLL 0 +-#define CLKID_FIXED_PLL 1 +-#define CLKID_FCLK_DIV2 2 +-#define CLKID_FCLK_DIV3 3 +-#define CLKID_FCLK_DIV4 4 +-#define CLKID_FCLK_DIV5 5 +-#define CLKID_FCLK_DIV7 6 +-#define CLKID_GP0_PLL 7 +-#define CLKID_CLK81 10 +-#define CLKID_MPLL0 11 +-#define CLKID_MPLL1 12 +-#define CLKID_MPLL2 13 +-#define CLKID_MPLL3 14 +-#define CLKID_DDR 15 +-#define CLKID_AUDIO_LOCKER 16 +-#define CLKID_MIPI_DSI_HOST 17 +-#define CLKID_ISA 18 +-#define CLKID_PL301 19 +-#define CLKID_PERIPHS 20 +-#define CLKID_SPICC0 21 +-#define CLKID_I2C 22 +-#define CLKID_RNG0 23 +-#define CLKID_UART0 24 +-#define CLKID_MIPI_DSI_PHY 25 +-#define CLKID_SPICC1 26 +-#define CLKID_PCIE_A 27 +-#define CLKID_PCIE_B 28 +-#define CLKID_HIU_IFACE 29 +-#define CLKID_ASSIST_MISC 30 +-#define CLKID_SD_EMMC_B 31 +-#define CLKID_SD_EMMC_C 32 +-#define CLKID_DMA 33 +-#define CLKID_SPI 34 +-#define CLKID_AUDIO 35 +-#define CLKID_ETH 36 +-#define CLKID_UART1 37 +-#define CLKID_G2D 38 +-#define CLKID_USB0 39 +-#define CLKID_USB1 40 +-#define CLKID_RESET 41 +-#define CLKID_USB 42 +-#define CLKID_AHB_ARB0 43 +-#define CLKID_EFUSE 44 +-#define CLKID_BOOT_ROM 45 +-#define CLKID_AHB_DATA_BUS 46 +-#define CLKID_AHB_CTRL_BUS 47 +-#define CLKID_USB1_DDR_BRIDGE 48 +-#define CLKID_USB0_DDR_BRIDGE 49 +-#define CLKID_MMC_PCLK 50 +-#define CLKID_VPU_INTR 51 +-#define CLKID_SEC_AHB_AHB3_BRIDGE 52 +-#define CLKID_GIC 53 +-#define CLKID_AO_MEDIA_CPU 54 +-#define CLKID_AO_AHB_SRAM 55 +-#define CLKID_AO_AHB_BUS 56 +-#define CLKID_AO_IFACE 57 +-#define CLKID_AO_I2C 58 +-#define CLKID_SD_EMMC_B_CLK0 59 +-#define CLKID_SD_EMMC_C_CLK0 60 +-#define CLKID_HIFI_PLL 69 +-#define CLKID_PCIE_CML_EN0 79 +-#define CLKID_PCIE_CML_EN1 80 +-#define CLKID_GEN_CLK 84 +-#define CLKID_VPU_0_SEL 92 +-#define CLKID_VPU_0 93 +-#define CLKID_VPU_1_SEL 95 +-#define CLKID_VPU_1 96 +-#define CLKID_VPU 97 +-#define CLKID_VAPB_0_SEL 99 +-#define CLKID_VAPB_0 100 +-#define CLKID_VAPB_1_SEL 102 +-#define CLKID_VAPB_1 103 +-#define CLKID_VAPB_SEL 104 +-#define CLKID_VAPB 105 +-#define CLKID_VCLK 106 +-#define CLKID_VCLK2 107 +-#define CLKID_VCLK_DIV1 122 +-#define CLKID_VCLK_DIV2 123 +-#define CLKID_VCLK_DIV4 124 +-#define CLKID_VCLK_DIV6 125 +-#define CLKID_VCLK_DIV12 126 +-#define CLKID_VCLK2_DIV1 127 +-#define CLKID_VCLK2_DIV2 128 +-#define CLKID_VCLK2_DIV4 129 +-#define CLKID_VCLK2_DIV6 130 +-#define CLKID_VCLK2_DIV12 131 +-#define CLKID_CTS_ENCL 133 +-#define CLKID_VDIN_MEAS 136 +- +-#endif /* __AXG_CLKC_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/axis,artpec6-clkctrl.h b/scripts/dtc/include-prefixes/dt-bindings/clock/axis,artpec6-clkctrl.h +deleted file mode 100644 +index b1f4971642e6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/axis,artpec6-clkctrl.h ++++ /dev/null +@@ -1,35 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * ARTPEC-6 clock controller indexes +- * +- * Copyright 2016 Axis Comunications AB. +- */ +- +-#ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H +-#define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H +- +-#define ARTPEC6_CLK_CPU 0 +-#define ARTPEC6_CLK_CPU_PERIPH 1 +-#define ARTPEC6_CLK_NAND_CLKA 2 +-#define ARTPEC6_CLK_NAND_CLKB 3 +-#define ARTPEC6_CLK_ETH_ACLK 4 +-#define ARTPEC6_CLK_DMA_ACLK 5 +-#define ARTPEC6_CLK_PTP_REF 6 +-#define ARTPEC6_CLK_SD_PCLK 7 +-#define ARTPEC6_CLK_SD_IMCLK 8 +-#define ARTPEC6_CLK_I2S_HST 9 +-#define ARTPEC6_CLK_I2S0_CLK 10 +-#define ARTPEC6_CLK_I2S1_CLK 11 +-#define ARTPEC6_CLK_UART_PCLK 12 +-#define ARTPEC6_CLK_UART_REFCLK 13 +-#define ARTPEC6_CLK_I2C 14 +-#define ARTPEC6_CLK_SPI_PCLK 15 +-#define ARTPEC6_CLK_SPI_SSPCLK 16 +-#define ARTPEC6_CLK_SYS_TIMER 17 +-#define ARTPEC6_CLK_FRACDIV_IN 18 +-#define ARTPEC6_CLK_DBG_PCLK 19 +- +-/* This must be the highest clock index plus one. */ +-#define ARTPEC6_CLK_NUMCLOCKS 20 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm-cygnus.h b/scripts/dtc/include-prefixes/dt-bindings/clock/bcm-cygnus.h +deleted file mode 100644 +index 62ac5d782a00..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm-cygnus.h ++++ /dev/null +@@ -1,74 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2014 Broadcom Corporation. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#ifndef _CLOCK_BCM_CYGNUS_H +-#define _CLOCK_BCM_CYGNUS_H +- +-/* GENPLL clock ID */ +-#define BCM_CYGNUS_GENPLL 0 +-#define BCM_CYGNUS_GENPLL_AXI21_CLK 1 +-#define BCM_CYGNUS_GENPLL_250MHZ_CLK 2 +-#define BCM_CYGNUS_GENPLL_IHOST_SYS_CLK 3 +-#define BCM_CYGNUS_GENPLL_ENET_SW_CLK 4 +-#define BCM_CYGNUS_GENPLL_AUDIO_125_CLK 5 +-#define BCM_CYGNUS_GENPLL_CAN_CLK 6 +- +-/* LCPLL0 clock ID */ +-#define BCM_CYGNUS_LCPLL0 0 +-#define BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK 1 +-#define BCM_CYGNUS_LCPLL0_DDR_PHY_CLK 2 +-#define BCM_CYGNUS_LCPLL0_SDIO_CLK 3 +-#define BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK 4 +-#define BCM_CYGNUS_LCPLL0_SMART_CARD_CLK 5 +-#define BCM_CYGNUS_LCPLL0_CH5_UNUSED 6 +- +-/* MIPI PLL clock ID */ +-#define BCM_CYGNUS_MIPIPLL 0 +-#define BCM_CYGNUS_MIPIPLL_CH0_UNUSED 1 +-#define BCM_CYGNUS_MIPIPLL_CH1_LCD 2 +-#define BCM_CYGNUS_MIPIPLL_CH2_V3D 3 +-#define BCM_CYGNUS_MIPIPLL_CH3_UNUSED 4 +-#define BCM_CYGNUS_MIPIPLL_CH4_UNUSED 5 +-#define BCM_CYGNUS_MIPIPLL_CH5_UNUSED 6 +- +-/* ASIU clock ID */ +-#define BCM_CYGNUS_ASIU_KEYPAD_CLK 0 +-#define BCM_CYGNUS_ASIU_ADC_CLK 1 +-#define BCM_CYGNUS_ASIU_PWM_CLK 2 +- +-/* AUDIO clock ID */ +-#define BCM_CYGNUS_AUDIOPLL 0 +-#define BCM_CYGNUS_AUDIOPLL_CH0 1 +-#define BCM_CYGNUS_AUDIOPLL_CH1 2 +-#define BCM_CYGNUS_AUDIOPLL_CH2 3 +- +-#endif /* _CLOCK_BCM_CYGNUS_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm-ns2.h b/scripts/dtc/include-prefixes/dt-bindings/clock/bcm-ns2.h +deleted file mode 100644 +index d99c7a2e70cb..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm-ns2.h ++++ /dev/null +@@ -1,72 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2015 Broadcom Corporation. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#ifndef _CLOCK_BCM_NS2_H +-#define _CLOCK_BCM_NS2_H +- +-/* GENPLL SCR clock channel ID */ +-#define BCM_NS2_GENPLL_SCR 0 +-#define BCM_NS2_GENPLL_SCR_SCR_CLK 1 +-#define BCM_NS2_GENPLL_SCR_FS_CLK 2 +-#define BCM_NS2_GENPLL_SCR_AUDIO_CLK 3 +-#define BCM_NS2_GENPLL_SCR_CH3_UNUSED 4 +-#define BCM_NS2_GENPLL_SCR_CH4_UNUSED 5 +-#define BCM_NS2_GENPLL_SCR_CH5_UNUSED 6 +- +-/* GENPLL SW clock channel ID */ +-#define BCM_NS2_GENPLL_SW 0 +-#define BCM_NS2_GENPLL_SW_RPE_CLK 1 +-#define BCM_NS2_GENPLL_SW_250_CLK 2 +-#define BCM_NS2_GENPLL_SW_NIC_CLK 3 +-#define BCM_NS2_GENPLL_SW_CHIMP_CLK 4 +-#define BCM_NS2_GENPLL_SW_PORT_CLK 5 +-#define BCM_NS2_GENPLL_SW_SDIO_CLK 6 +- +-/* LCPLL DDR clock channel ID */ +-#define BCM_NS2_LCPLL_DDR 0 +-#define BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK 1 +-#define BCM_NS2_LCPLL_DDR_DDR_CLK 2 +-#define BCM_NS2_LCPLL_DDR_CH2_UNUSED 3 +-#define BCM_NS2_LCPLL_DDR_CH3_UNUSED 4 +-#define BCM_NS2_LCPLL_DDR_CH4_UNUSED 5 +-#define BCM_NS2_LCPLL_DDR_CH5_UNUSED 6 +- +-/* LCPLL PORTS clock channel ID */ +-#define BCM_NS2_LCPLL_PORTS 0 +-#define BCM_NS2_LCPLL_PORTS_WAN_CLK 1 +-#define BCM_NS2_LCPLL_PORTS_RGMII_CLK 2 +-#define BCM_NS2_LCPLL_PORTS_CH2_UNUSED 3 +-#define BCM_NS2_LCPLL_PORTS_CH3_UNUSED 4 +-#define BCM_NS2_LCPLL_PORTS_CH4_UNUSED 5 +-#define BCM_NS2_LCPLL_PORTS_CH5_UNUSED 6 +- +-#endif /* _CLOCK_BCM_NS2_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm-nsp.h b/scripts/dtc/include-prefixes/dt-bindings/clock/bcm-nsp.h +deleted file mode 100644 +index ad5827cde782..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm-nsp.h ++++ /dev/null +@@ -1,51 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2015 Broadcom Corporation. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#ifndef _CLOCK_BCM_NSP_H +-#define _CLOCK_BCM_NSP_H +- +-/* GENPLL clock channel ID */ +-#define BCM_NSP_GENPLL 0 +-#define BCM_NSP_GENPLL_PHY_CLK 1 +-#define BCM_NSP_GENPLL_ENET_SW_CLK 2 +-#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3 +-#define BCM_NSP_GENPLL_IPROCFAST_CLK 4 +-#define BCM_NSP_GENPLL_SATA1_CLK 5 +-#define BCM_NSP_GENPLL_SATA2_CLK 6 +- +-/* LCPLL0 clock channel ID */ +-#define BCM_NSP_LCPLL0 0 +-#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 1 +-#define BCM_NSP_LCPLL0_SDIO_CLK 2 +-#define BCM_NSP_LCPLL0_DDR_PHY_CLK 3 +- +-#endif /* _CLOCK_BCM_NSP_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm-sr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/bcm-sr.h +deleted file mode 100644 +index 419011ba1a94..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm-sr.h ++++ /dev/null +@@ -1,111 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2017 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#ifndef _CLOCK_BCM_SR_H +-#define _CLOCK_BCM_SR_H +- +-/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */ +-#define BCM_SR_GENPLL0 0 +-#define BCM_SR_GENPLL0_125M_CLK 1 +-#define BCM_SR_GENPLL0_SCR_CLK 2 +-#define BCM_SR_GENPLL0_250M_CLK 3 +-#define BCM_SR_GENPLL0_PCIE_AXI_CLK 4 +-#define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK 5 +-#define BCM_SR_GENPLL0_PAXC_AXI_CLK 6 +- +-/* GENPLL 1 clock channel ID MHB PCIE NITRO */ +-#define BCM_SR_GENPLL1 0 +-#define BCM_SR_GENPLL1_PCIE_TL_CLK 1 +-#define BCM_SR_GENPLL1_MHB_APB_CLK 2 +- +-/* GENPLL 2 clock channel ID NITRO MHB*/ +-#define BCM_SR_GENPLL2 0 +-#define BCM_SR_GENPLL2_NIC_CLK 1 +-#define BCM_SR_GENPLL2_TS_500_CLK 2 +-#define BCM_SR_GENPLL2_125_NITRO_CLK 3 +-#define BCM_SR_GENPLL2_CHIMP_CLK 4 +-#define BCM_SR_GENPLL2_NIC_FLASH_CLK 5 +-#define BCM_SR_GENPLL2_FS4_CLK 6 +- +-/* GENPLL 3 HSLS clock channel ID */ +-#define BCM_SR_GENPLL3 0 +-#define BCM_SR_GENPLL3_HSLS_CLK 1 +-#define BCM_SR_GENPLL3_SDIO_CLK 2 +- +-/* GENPLL 4 SCR clock channel ID */ +-#define BCM_SR_GENPLL4 0 +-#define BCM_SR_GENPLL4_CCN_CLK 1 +-#define BCM_SR_GENPLL4_TPIU_PLL_CLK 2 +-#define BCM_SR_GENPLL4_NOC_CLK 3 +-#define BCM_SR_GENPLL4_CHCLK_FS4_CLK 4 +-#define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 5 +- +-/* GENPLL 5 FS4 clock channel ID */ +-#define BCM_SR_GENPLL5 0 +-#define BCM_SR_GENPLL5_FS4_HF_CLK 1 +-#define BCM_SR_GENPLL5_CRYPTO_AE_CLK 2 +-#define BCM_SR_GENPLL5_RAID_AE_CLK 3 +- +-/* GENPLL 6 NITRO clock channel ID */ +-#define BCM_SR_GENPLL6 0 +-#define BCM_SR_GENPLL6_48_USB_CLK 1 +- +-/* LCPLL0 clock channel ID */ +-#define BCM_SR_LCPLL0 0 +-#define BCM_SR_LCPLL0_SATA_REFP_CLK 1 +-#define BCM_SR_LCPLL0_SATA_REFN_CLK 2 +-#define BCM_SR_LCPLL0_SATA_350_CLK 3 +-#define BCM_SR_LCPLL0_SATA_500_CLK 4 +- +-/* LCPLL1 clock channel ID */ +-#define BCM_SR_LCPLL1 0 +-#define BCM_SR_LCPLL1_WAN_CLK 1 +-#define BCM_SR_LCPLL1_USB_REF_CLK 2 +-#define BCM_SR_LCPLL1_CRMU_TS_CLK 3 +- +-/* LCPLL PCIE clock channel ID */ +-#define BCM_SR_LCPLL_PCIE 0 +-#define BCM_SR_LCPLL_PCIE_PHY_REF_CLK 1 +- +-/* GENPLL EMEM0 clock channel ID */ +-#define BCM_SR_EMEMPLL0 0 +-#define BCM_SR_EMEMPLL0_EMEM_CLK 1 +- +-/* GENPLL EMEM0 clock channel ID */ +-#define BCM_SR_EMEMPLL1 0 +-#define BCM_SR_EMEMPLL1_EMEM_CLK 1 +- +-/* GENPLL EMEM0 clock channel ID */ +-#define BCM_SR_EMEMPLL2 0 +-#define BCM_SR_EMEMPLL2_EMEM_CLK 1 +- +-#endif /* _CLOCK_BCM_SR_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm21664.h b/scripts/dtc/include-prefixes/dt-bindings/clock/bcm21664.h +deleted file mode 100644 +index 5a7f0e4750a8..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm21664.h ++++ /dev/null +@@ -1,62 +0,0 @@ +-/* +- * Copyright (C) 2013 Broadcom Corporation +- * Copyright 2013 Linaro Limited +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation version 2. +- * +- * This program is distributed "as is" WITHOUT ANY WARRANTY of any +- * kind, whether express or implied; without even the implied warranty +- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#ifndef _CLOCK_BCM21664_H +-#define _CLOCK_BCM21664_H +- +-/* +- * This file defines the values used to specify clocks provided by +- * the clock control units (CCUs) on Broadcom BCM21664 family SoCs. +- */ +- +-/* bcm21664 CCU device tree "compatible" strings */ +-#define BCM21664_DT_ROOT_CCU_COMPAT "brcm,bcm21664-root-ccu" +-#define BCM21664_DT_AON_CCU_COMPAT "brcm,bcm21664-aon-ccu" +-#define BCM21664_DT_MASTER_CCU_COMPAT "brcm,bcm21664-master-ccu" +-#define BCM21664_DT_SLAVE_CCU_COMPAT "brcm,bcm21664-slave-ccu" +- +-/* root CCU clock ids */ +- +-#define BCM21664_ROOT_CCU_FRAC_1M 0 +-#define BCM21664_ROOT_CCU_CLOCK_COUNT 1 +- +-/* aon CCU clock ids */ +- +-#define BCM21664_AON_CCU_HUB_TIMER 0 +-#define BCM21664_AON_CCU_CLOCK_COUNT 1 +- +-/* master CCU clock ids */ +- +-#define BCM21664_MASTER_CCU_SDIO1 0 +-#define BCM21664_MASTER_CCU_SDIO2 1 +-#define BCM21664_MASTER_CCU_SDIO3 2 +-#define BCM21664_MASTER_CCU_SDIO4 3 +-#define BCM21664_MASTER_CCU_SDIO1_SLEEP 4 +-#define BCM21664_MASTER_CCU_SDIO2_SLEEP 5 +-#define BCM21664_MASTER_CCU_SDIO3_SLEEP 6 +-#define BCM21664_MASTER_CCU_SDIO4_SLEEP 7 +-#define BCM21664_MASTER_CCU_CLOCK_COUNT 8 +- +-/* slave CCU clock ids */ +- +-#define BCM21664_SLAVE_CCU_UARTB 0 +-#define BCM21664_SLAVE_CCU_UARTB2 1 +-#define BCM21664_SLAVE_CCU_UARTB3 2 +-#define BCM21664_SLAVE_CCU_BSC1 3 +-#define BCM21664_SLAVE_CCU_BSC2 4 +-#define BCM21664_SLAVE_CCU_BSC3 5 +-#define BCM21664_SLAVE_CCU_BSC4 6 +-#define BCM21664_SLAVE_CCU_CLOCK_COUNT 7 +- +-#endif /* _CLOCK_BCM21664_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm281xx.h b/scripts/dtc/include-prefixes/dt-bindings/clock/bcm281xx.h +deleted file mode 100644 +index a763460cf1af..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm281xx.h ++++ /dev/null +@@ -1,77 +0,0 @@ +-/* +- * Copyright (C) 2013 Broadcom Corporation +- * Copyright 2013 Linaro Limited +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation version 2. +- * +- * This program is distributed "as is" WITHOUT ANY WARRANTY of any +- * kind, whether express or implied; without even the implied warranty +- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#ifndef _CLOCK_BCM281XX_H +-#define _CLOCK_BCM281XX_H +- +-/* +- * This file defines the values used to specify clocks provided by +- * the clock control units (CCUs) on Broadcom BCM281XX family SoCs. +- */ +- +-/* +- * These are the bcm281xx CCU device tree "compatible" strings. +- * We're stuck with using "bcm11351" in the string because wild +- * cards aren't allowed, and that name was the first one defined +- * in this family of devices. +- */ +-#define BCM281XX_DT_ROOT_CCU_COMPAT "brcm,bcm11351-root-ccu" +-#define BCM281XX_DT_AON_CCU_COMPAT "brcm,bcm11351-aon-ccu" +-#define BCM281XX_DT_HUB_CCU_COMPAT "brcm,bcm11351-hub-ccu" +-#define BCM281XX_DT_MASTER_CCU_COMPAT "brcm,bcm11351-master-ccu" +-#define BCM281XX_DT_SLAVE_CCU_COMPAT "brcm,bcm11351-slave-ccu" +- +-/* root CCU clock ids */ +- +-#define BCM281XX_ROOT_CCU_FRAC_1M 0 +-#define BCM281XX_ROOT_CCU_CLOCK_COUNT 1 +- +-/* aon CCU clock ids */ +- +-#define BCM281XX_AON_CCU_HUB_TIMER 0 +-#define BCM281XX_AON_CCU_PMU_BSC 1 +-#define BCM281XX_AON_CCU_PMU_BSC_VAR 2 +-#define BCM281XX_AON_CCU_CLOCK_COUNT 3 +- +-/* hub CCU clock ids */ +- +-#define BCM281XX_HUB_CCU_TMON_1M 0 +-#define BCM281XX_HUB_CCU_CLOCK_COUNT 1 +- +-/* master CCU clock ids */ +- +-#define BCM281XX_MASTER_CCU_SDIO1 0 +-#define BCM281XX_MASTER_CCU_SDIO2 1 +-#define BCM281XX_MASTER_CCU_SDIO3 2 +-#define BCM281XX_MASTER_CCU_SDIO4 3 +-#define BCM281XX_MASTER_CCU_USB_IC 4 +-#define BCM281XX_MASTER_CCU_HSIC2_48M 5 +-#define BCM281XX_MASTER_CCU_HSIC2_12M 6 +-#define BCM281XX_MASTER_CCU_CLOCK_COUNT 7 +- +-/* slave CCU clock ids */ +- +-#define BCM281XX_SLAVE_CCU_UARTB 0 +-#define BCM281XX_SLAVE_CCU_UARTB2 1 +-#define BCM281XX_SLAVE_CCU_UARTB3 2 +-#define BCM281XX_SLAVE_CCU_UARTB4 3 +-#define BCM281XX_SLAVE_CCU_SSP0 4 +-#define BCM281XX_SLAVE_CCU_SSP2 5 +-#define BCM281XX_SLAVE_CCU_BSC1 6 +-#define BCM281XX_SLAVE_CCU_BSC2 7 +-#define BCM281XX_SLAVE_CCU_BSC3 8 +-#define BCM281XX_SLAVE_CCU_PWM 9 +-#define BCM281XX_SLAVE_CCU_CLOCK_COUNT 10 +- +-#endif /* _CLOCK_BCM281XX_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm2835-aux.h b/scripts/dtc/include-prefixes/dt-bindings/clock/bcm2835-aux.h +deleted file mode 100644 +index bb79de383a3b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm2835-aux.h ++++ /dev/null +@@ -1,9 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2015 Broadcom Corporation +- */ +- +-#define BCM2835_AUX_CLOCK_UART 0 +-#define BCM2835_AUX_CLOCK_SPI1 1 +-#define BCM2835_AUX_CLOCK_SPI2 2 +-#define BCM2835_AUX_CLOCK_COUNT 3 +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm2835.h b/scripts/dtc/include-prefixes/dt-bindings/clock/bcm2835.h +deleted file mode 100644 +index b60c03430cf1..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm2835.h ++++ /dev/null +@@ -1,62 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2015 Broadcom Corporation +- */ +- +-#define BCM2835_PLLA 0 +-#define BCM2835_PLLB 1 +-#define BCM2835_PLLC 2 +-#define BCM2835_PLLD 3 +-#define BCM2835_PLLH 4 +- +-#define BCM2835_PLLA_CORE 5 +-#define BCM2835_PLLA_PER 6 +-#define BCM2835_PLLB_ARM 7 +-#define BCM2835_PLLC_CORE0 8 +-#define BCM2835_PLLC_CORE1 9 +-#define BCM2835_PLLC_CORE2 10 +-#define BCM2835_PLLC_PER 11 +-#define BCM2835_PLLD_CORE 12 +-#define BCM2835_PLLD_PER 13 +-#define BCM2835_PLLH_RCAL 14 +-#define BCM2835_PLLH_AUX 15 +-#define BCM2835_PLLH_PIX 16 +- +-#define BCM2835_CLOCK_TIMER 17 +-#define BCM2835_CLOCK_OTP 18 +-#define BCM2835_CLOCK_UART 19 +-#define BCM2835_CLOCK_VPU 20 +-#define BCM2835_CLOCK_V3D 21 +-#define BCM2835_CLOCK_ISP 22 +-#define BCM2835_CLOCK_H264 23 +-#define BCM2835_CLOCK_VEC 24 +-#define BCM2835_CLOCK_HSM 25 +-#define BCM2835_CLOCK_SDRAM 26 +-#define BCM2835_CLOCK_TSENS 27 +-#define BCM2835_CLOCK_EMMC 28 +-#define BCM2835_CLOCK_PERI_IMAGE 29 +-#define BCM2835_CLOCK_PWM 30 +-#define BCM2835_CLOCK_PCM 31 +- +-#define BCM2835_PLLA_DSI0 32 +-#define BCM2835_PLLA_CCP2 33 +-#define BCM2835_PLLD_DSI0 34 +-#define BCM2835_PLLD_DSI1 35 +- +-#define BCM2835_CLOCK_AVEO 36 +-#define BCM2835_CLOCK_DFT 37 +-#define BCM2835_CLOCK_GP0 38 +-#define BCM2835_CLOCK_GP1 39 +-#define BCM2835_CLOCK_GP2 40 +-#define BCM2835_CLOCK_SLIM 41 +-#define BCM2835_CLOCK_SMI 42 +-#define BCM2835_CLOCK_TEC 43 +-#define BCM2835_CLOCK_DPI 44 +-#define BCM2835_CLOCK_CAM0 45 +-#define BCM2835_CLOCK_CAM1 46 +-#define BCM2835_CLOCK_DSI0E 47 +-#define BCM2835_CLOCK_DSI1E 48 +-#define BCM2835_CLOCK_DSI0P 49 +-#define BCM2835_CLOCK_DSI1P 50 +- +-#define BCM2711_CLOCK_EMMC2 51 +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm3368-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/bcm3368-clock.h +deleted file mode 100644 +index 74a7382f77b8..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm3368-clock.h ++++ /dev/null +@@ -1,24 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef __DT_BINDINGS_CLOCK_BCM3368_H +-#define __DT_BINDINGS_CLOCK_BCM3368_H +- +-#define BCM3368_CLK_MAC 3 +-#define BCM3368_CLK_TC 5 +-#define BCM3368_CLK_US_TOP 6 +-#define BCM3368_CLK_DS_TOP 7 +-#define BCM3368_CLK_ACM 8 +-#define BCM3368_CLK_SPI 9 +-#define BCM3368_CLK_USBS 10 +-#define BCM3368_CLK_BMU 11 +-#define BCM3368_CLK_PCM 12 +-#define BCM3368_CLK_NTP 13 +-#define BCM3368_CLK_ACP_B 14 +-#define BCM3368_CLK_ACP_A 15 +-#define BCM3368_CLK_EMUSB 17 +-#define BCM3368_CLK_ENET0 18 +-#define BCM3368_CLK_ENET1 19 +-#define BCM3368_CLK_USBSU 20 +-#define BCM3368_CLK_EPHY 21 +- +-#endif /* __DT_BINDINGS_CLOCK_BCM3368_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm6318-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/bcm6318-clock.h +deleted file mode 100644 +index c4417f8983ab..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm6318-clock.h ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef __DT_BINDINGS_CLOCK_BCM6318_H +-#define __DT_BINDINGS_CLOCK_BCM6318_H +- +-#define BCM6318_CLK_ADSL_ASB 0 +-#define BCM6318_CLK_USB_ASB 1 +-#define BCM6318_CLK_MIPS_ASB 2 +-#define BCM6318_CLK_PCIE_ASB 3 +-#define BCM6318_CLK_PHYMIPS_ASB 4 +-#define BCM6318_CLK_ROBOSW_ASB 5 +-#define BCM6318_CLK_SAR_ASB 6 +-#define BCM6318_CLK_SDR_ASB 7 +-#define BCM6318_CLK_SWREG_ASB 8 +-#define BCM6318_CLK_PERIPH_ASB 9 +-#define BCM6318_CLK_CPUBUS160 10 +-#define BCM6318_CLK_ADSL 11 +-#define BCM6318_CLK_SAR125 12 +-#define BCM6318_CLK_MIPS 13 +-#define BCM6318_CLK_PCIE 14 +-#define BCM6318_CLK_ROBOSW250 16 +-#define BCM6318_CLK_ROBOSW025 17 +-#define BCM6318_CLK_SDR 19 +-#define BCM6318_CLK_USBD 20 +-#define BCM6318_CLK_HSSPI 25 +-#define BCM6318_CLK_PCIE25 27 +-#define BCM6318_CLK_PHYMIPS 28 +-#define BCM6318_CLK_AFE 29 +-#define BCM6318_CLK_QPROC 30 +- +-#define BCM6318_UCLK_ADSL 0 +-#define BCM6318_UCLK_ARB 1 +-#define BCM6318_UCLK_MIPS 2 +-#define BCM6318_UCLK_PCIE 3 +-#define BCM6318_UCLK_PERIPH 4 +-#define BCM6318_UCLK_PHYMIPS 5 +-#define BCM6318_UCLK_ROBOSW 6 +-#define BCM6318_UCLK_SAR 7 +-#define BCM6318_UCLK_SDR 8 +-#define BCM6318_UCLK_USB 9 +- +-#endif /* __DT_BINDINGS_CLOCK_BCM6318_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm63268-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/bcm63268-clock.h +deleted file mode 100644 +index da23e691d359..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm63268-clock.h ++++ /dev/null +@@ -1,30 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef __DT_BINDINGS_CLOCK_BCM63268_H +-#define __DT_BINDINGS_CLOCK_BCM63268_H +- +-#define BCM63268_CLK_DIS_GLESS 0 +-#define BCM63268_CLK_VDSL_QPROC 1 +-#define BCM63268_CLK_VDSL_AFE 2 +-#define BCM63268_CLK_VDSL 3 +-#define BCM63268_CLK_MIPS 4 +-#define BCM63268_CLK_WLAN_OCP 5 +-#define BCM63268_CLK_DECT 6 +-#define BCM63268_CLK_FAP0 7 +-#define BCM63268_CLK_FAP1 8 +-#define BCM63268_CLK_SAR 9 +-#define BCM63268_CLK_ROBOSW 10 +-#define BCM63268_CLK_PCM 11 +-#define BCM63268_CLK_USBD 12 +-#define BCM63268_CLK_USBH 13 +-#define BCM63268_CLK_IPSEC 14 +-#define BCM63268_CLK_SPI 15 +-#define BCM63268_CLK_HSSPI 16 +-#define BCM63268_CLK_PCIE 17 +-#define BCM63268_CLK_PHYMIPS 18 +-#define BCM63268_CLK_GMAC 19 +-#define BCM63268_CLK_NAND 20 +-#define BCM63268_CLK_TBUS 27 +-#define BCM63268_CLK_ROBOSW250 31 +- +-#endif /* __DT_BINDINGS_CLOCK_BCM63268_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm6328-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/bcm6328-clock.h +deleted file mode 100644 +index 1f6a3103f3dc..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm6328-clock.h ++++ /dev/null +@@ -1,19 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef __DT_BINDINGS_CLOCK_BCM6328_H +-#define __DT_BINDINGS_CLOCK_BCM6328_H +- +-#define BCM6328_CLK_PHYMIPS 0 +-#define BCM6328_CLK_ADSL_QPROC 1 +-#define BCM6328_CLK_ADSL_AFE 2 +-#define BCM6328_CLK_ADSL 3 +-#define BCM6328_CLK_MIPS 4 +-#define BCM6328_CLK_SAR 5 +-#define BCM6328_CLK_PCM 6 +-#define BCM6328_CLK_USBD 7 +-#define BCM6328_CLK_USBH 8 +-#define BCM6328_CLK_HSSPI 9 +-#define BCM6328_CLK_PCIE 10 +-#define BCM6328_CLK_ROBOSW 11 +- +-#endif /* __DT_BINDINGS_CLOCK_BCM6328_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm6358-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/bcm6358-clock.h +deleted file mode 100644 +index 980c9cac4765..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm6358-clock.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef __DT_BINDINGS_CLOCK_BCM6358_H +-#define __DT_BINDINGS_CLOCK_BCM6358_H +- +-#define BCM6358_CLK_ENET 4 +-#define BCM6358_CLK_ADSLPHY 5 +-#define BCM6358_CLK_PCM 8 +-#define BCM6358_CLK_SPI 9 +-#define BCM6358_CLK_USBS 10 +-#define BCM6358_CLK_SAR 11 +-#define BCM6358_CLK_EMUSB 17 +-#define BCM6358_CLK_ENET0 18 +-#define BCM6358_CLK_ENET1 19 +-#define BCM6358_CLK_USBSU 20 +-#define BCM6358_CLK_EPHY 21 +- +-#endif /* __DT_BINDINGS_CLOCK_BCM6358_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm6362-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/bcm6362-clock.h +deleted file mode 100644 +index 17655cd5bf25..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm6362-clock.h ++++ /dev/null +@@ -1,26 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef __DT_BINDINGS_CLOCK_BCM6362_H +-#define __DT_BINDINGS_CLOCK_BCM6362_H +- +-#define BCM6362_CLK_ADSL_QPROC 1 +-#define BCM6362_CLK_ADSL_AFE 2 +-#define BCM6362_CLK_ADSL 3 +-#define BCM6362_CLK_MIPS 4 +-#define BCM6362_CLK_WLAN_OCP 5 +-#define BCM6362_CLK_SWPKT_USB 7 +-#define BCM6362_CLK_SWPKT_SAR 8 +-#define BCM6362_CLK_SAR 9 +-#define BCM6362_CLK_ROBOSW 10 +-#define BCM6362_CLK_PCM 11 +-#define BCM6362_CLK_USBD 12 +-#define BCM6362_CLK_USBH 13 +-#define BCM6362_CLK_IPSEC 14 +-#define BCM6362_CLK_SPI 15 +-#define BCM6362_CLK_HSSPI 16 +-#define BCM6362_CLK_PCIE 17 +-#define BCM6362_CLK_FAP 18 +-#define BCM6362_CLK_PHYMIPS 19 +-#define BCM6362_CLK_NAND 20 +- +-#endif /* __DT_BINDINGS_CLOCK_BCM6362_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm6368-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/bcm6368-clock.h +deleted file mode 100644 +index f161d5333883..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/bcm6368-clock.h ++++ /dev/null +@@ -1,24 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef __DT_BINDINGS_CLOCK_BCM6368_H +-#define __DT_BINDINGS_CLOCK_BCM6368_H +- +-#define BCM6368_CLK_VDSL_QPROC 2 +-#define BCM6368_CLK_VDSL_AFE 3 +-#define BCM6368_CLK_VDSL_BONDING 4 +-#define BCM6368_CLK_VDSL 5 +-#define BCM6368_CLK_PHYMIPS 6 +-#define BCM6368_CLK_SWPKT_USB 7 +-#define BCM6368_CLK_SWPKT_SAR 8 +-#define BCM6368_CLK_SPI 9 +-#define BCM6368_CLK_USBD 10 +-#define BCM6368_CLK_SAR 11 +-#define BCM6368_CLK_ROBOSW 12 +-#define BCM6368_CLK_UTOPIA 13 +-#define BCM6368_CLK_PCM 14 +-#define BCM6368_CLK_USBH 15 +-#define BCM6368_CLK_DIS_GLESS 16 +-#define BCM6368_CLK_NAND 17 +-#define BCM6368_CLK_IPSEC 18 +- +-#endif /* __DT_BINDINGS_CLOCK_BCM6368_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/berlin2.h b/scripts/dtc/include-prefixes/dt-bindings/clock/berlin2.h +deleted file mode 100644 +index b07b8efab075..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/berlin2.h ++++ /dev/null +@@ -1,46 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Berlin2 BG2/BG2CD clock tree IDs +- */ +- +-#define CLKID_SYS 0 +-#define CLKID_CPU 1 +-#define CLKID_DRMFIGO 2 +-#define CLKID_CFG 3 +-#define CLKID_GFX 4 +-#define CLKID_ZSP 5 +-#define CLKID_PERIF 6 +-#define CLKID_PCUBE 7 +-#define CLKID_VSCOPE 8 +-#define CLKID_NFC_ECC 9 +-#define CLKID_VPP 10 +-#define CLKID_APP 11 +-#define CLKID_AUDIO0 12 +-#define CLKID_AUDIO2 13 +-#define CLKID_AUDIO3 14 +-#define CLKID_AUDIO1 15 +-#define CLKID_GFX3D_CORE 16 +-#define CLKID_GFX3D_SYS 17 +-#define CLKID_ARC 18 +-#define CLKID_VIP 19 +-#define CLKID_SDIO0XIN 20 +-#define CLKID_SDIO1XIN 21 +-#define CLKID_GFX3D_EXTRA 22 +-#define CLKID_GC360 23 +-#define CLKID_SDIO_DLLMST 24 +-#define CLKID_GETH0 25 +-#define CLKID_GETH1 26 +-#define CLKID_SATA 27 +-#define CLKID_AHBAPB 28 +-#define CLKID_USB0 29 +-#define CLKID_USB1 30 +-#define CLKID_PBRIDGE 31 +-#define CLKID_SDIO0 32 +-#define CLKID_SDIO1 33 +-#define CLKID_NFC 34 +-#define CLKID_SMEMC 35 +-#define CLKID_AUDIOHD 36 +-#define CLKID_VIDEO0 37 +-#define CLKID_VIDEO1 38 +-#define CLKID_VIDEO2 39 +-#define CLKID_TWD 40 +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/berlin2q.h b/scripts/dtc/include-prefixes/dt-bindings/clock/berlin2q.h +deleted file mode 100644 +index 44b4ac382850..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/berlin2q.h ++++ /dev/null +@@ -1,33 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Berlin2 BG2Q clock tree IDs +- */ +- +-#define CLKID_SYS 0 +-#define CLKID_DRMFIGO 1 +-#define CLKID_CFG 2 +-#define CLKID_GFX2D 3 +-#define CLKID_ZSP 4 +-#define CLKID_PERIF 5 +-#define CLKID_PCUBE 6 +-#define CLKID_VSCOPE 7 +-#define CLKID_NFC_ECC 8 +-#define CLKID_VPP 9 +-#define CLKID_APP 10 +-#define CLKID_SDIO0XIN 11 +-#define CLKID_SDIO1XIN 12 +-#define CLKID_GFX2DAXI 13 +-#define CLKID_GETH0 14 +-#define CLKID_SATA 15 +-#define CLKID_AHBAPB 16 +-#define CLKID_USB0 17 +-#define CLKID_USB1 18 +-#define CLKID_USB2 19 +-#define CLKID_USB3 20 +-#define CLKID_PBRIDGE 21 +-#define CLKID_SDIO 22 +-#define CLKID_NFC 23 +-#define CLKID_SMEMC 24 +-#define CLKID_PCIE 25 +-#define CLKID_TWD 26 +-#define CLKID_CPU 27 +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/bm1880-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/bm1880-clock.h +deleted file mode 100644 +index b46732361b25..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/bm1880-clock.h ++++ /dev/null +@@ -1,82 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Device Tree binding constants for Bitmain BM1880 SoC +- * +- * Copyright (c) 2019 Linaro Ltd. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_BM1880_H +-#define __DT_BINDINGS_CLOCK_BM1880_H +- +-#define BM1880_CLK_OSC 0 +-#define BM1880_CLK_MPLL 1 +-#define BM1880_CLK_SPLL 2 +-#define BM1880_CLK_FPLL 3 +-#define BM1880_CLK_DDRPLL 4 +-#define BM1880_CLK_A53 5 +-#define BM1880_CLK_50M_A53 6 +-#define BM1880_CLK_AHB_ROM 7 +-#define BM1880_CLK_AXI_SRAM 8 +-#define BM1880_CLK_DDR_AXI 9 +-#define BM1880_CLK_EFUSE 10 +-#define BM1880_CLK_APB_EFUSE 11 +-#define BM1880_CLK_AXI5_EMMC 12 +-#define BM1880_CLK_EMMC 13 +-#define BM1880_CLK_100K_EMMC 14 +-#define BM1880_CLK_AXI5_SD 15 +-#define BM1880_CLK_SD 16 +-#define BM1880_CLK_100K_SD 17 +-#define BM1880_CLK_500M_ETH0 18 +-#define BM1880_CLK_AXI4_ETH0 19 +-#define BM1880_CLK_500M_ETH1 20 +-#define BM1880_CLK_AXI4_ETH1 21 +-#define BM1880_CLK_AXI1_GDMA 22 +-#define BM1880_CLK_APB_GPIO 23 +-#define BM1880_CLK_APB_GPIO_INTR 24 +-#define BM1880_CLK_GPIO_DB 25 +-#define BM1880_CLK_AXI1_MINER 26 +-#define BM1880_CLK_AHB_SF 27 +-#define BM1880_CLK_SDMA_AXI 28 +-#define BM1880_CLK_SDMA_AUD 29 +-#define BM1880_CLK_APB_I2C 30 +-#define BM1880_CLK_APB_WDT 31 +-#define BM1880_CLK_APB_JPEG 32 +-#define BM1880_CLK_JPEG_AXI 33 +-#define BM1880_CLK_AXI5_NF 34 +-#define BM1880_CLK_APB_NF 35 +-#define BM1880_CLK_NF 36 +-#define BM1880_CLK_APB_PWM 37 +-#define BM1880_CLK_DIV_0_RV 38 +-#define BM1880_CLK_DIV_1_RV 39 +-#define BM1880_CLK_MUX_RV 40 +-#define BM1880_CLK_RV 41 +-#define BM1880_CLK_APB_SPI 42 +-#define BM1880_CLK_TPU_AXI 43 +-#define BM1880_CLK_DIV_UART_500M 44 +-#define BM1880_CLK_UART_500M 45 +-#define BM1880_CLK_APB_UART 46 +-#define BM1880_CLK_APB_I2S 47 +-#define BM1880_CLK_AXI4_USB 48 +-#define BM1880_CLK_APB_USB 49 +-#define BM1880_CLK_125M_USB 50 +-#define BM1880_CLK_33K_USB 51 +-#define BM1880_CLK_DIV_12M_USB 52 +-#define BM1880_CLK_12M_USB 53 +-#define BM1880_CLK_APB_VIDEO 54 +-#define BM1880_CLK_VIDEO_AXI 55 +-#define BM1880_CLK_VPP_AXI 56 +-#define BM1880_CLK_APB_VPP 57 +-#define BM1880_CLK_DIV_0_AXI1 58 +-#define BM1880_CLK_DIV_1_AXI1 59 +-#define BM1880_CLK_AXI1 60 +-#define BM1880_CLK_AXI2 61 +-#define BM1880_CLK_AXI3 62 +-#define BM1880_CLK_AXI4 63 +-#define BM1880_CLK_AXI5 64 +-#define BM1880_CLK_DIV_0_AXI6 65 +-#define BM1880_CLK_DIV_1_AXI6 66 +-#define BM1880_CLK_MUX_AXI6 67 +-#define BM1880_CLK_AXI6 68 +-#define BM1880_NR_CLKS 69 +- +-#endif /* __DT_BINDINGS_CLOCK_BM1880_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/boston-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/boston-clock.h +deleted file mode 100644 +index a6f009821137..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/boston-clock.h ++++ /dev/null +@@ -1,14 +0,0 @@ +-/* +- * Copyright (C) 2016 Imagination Technologies +- * +- * SPDX-License-Identifier: GPL-2.0 +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ +-#define __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ +- +-#define BOSTON_CLK_INPUT 0 +-#define BOSTON_CLK_SYS 1 +-#define BOSTON_CLK_CPU 2 +- +-#endif /* __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/bt1-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/bt1-ccu.h +deleted file mode 100644 +index 5f166d27a00a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/bt1-ccu.h ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC +- * +- * Baikal-T1 CCU clock indices +- */ +-#ifndef __DT_BINDINGS_CLOCK_BT1_CCU_H +-#define __DT_BINDINGS_CLOCK_BT1_CCU_H +- +-#define CCU_CPU_PLL 0 +-#define CCU_SATA_PLL 1 +-#define CCU_DDR_PLL 2 +-#define CCU_PCIE_PLL 3 +-#define CCU_ETH_PLL 4 +- +-#define CCU_AXI_MAIN_CLK 0 +-#define CCU_AXI_DDR_CLK 1 +-#define CCU_AXI_SATA_CLK 2 +-#define CCU_AXI_GMAC0_CLK 3 +-#define CCU_AXI_GMAC1_CLK 4 +-#define CCU_AXI_XGMAC_CLK 5 +-#define CCU_AXI_PCIE_M_CLK 6 +-#define CCU_AXI_PCIE_S_CLK 7 +-#define CCU_AXI_USB_CLK 8 +-#define CCU_AXI_HWA_CLK 9 +-#define CCU_AXI_SRAM_CLK 10 +- +-#define CCU_SYS_SATA_REF_CLK 0 +-#define CCU_SYS_APB_CLK 1 +-#define CCU_SYS_GMAC0_TX_CLK 2 +-#define CCU_SYS_GMAC0_PTP_CLK 3 +-#define CCU_SYS_GMAC1_TX_CLK 4 +-#define CCU_SYS_GMAC1_PTP_CLK 5 +-#define CCU_SYS_XGMAC_REF_CLK 6 +-#define CCU_SYS_XGMAC_PTP_CLK 7 +-#define CCU_SYS_USB_CLK 8 +-#define CCU_SYS_PVT_CLK 9 +-#define CCU_SYS_HWA_CLK 10 +-#define CCU_SYS_UART_CLK 11 +-#define CCU_SYS_I2C1_CLK 12 +-#define CCU_SYS_I2C2_CLK 13 +-#define CCU_SYS_GPIO_CLK 14 +-#define CCU_SYS_TIMER0_CLK 15 +-#define CCU_SYS_TIMER1_CLK 16 +-#define CCU_SYS_TIMER2_CLK 17 +-#define CCU_SYS_WDT_CLK 18 +- +-#endif /* __DT_BINDINGS_CLOCK_BT1_CCU_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/clps711x-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/clps711x-clock.h +deleted file mode 100644 +index 55b403d8b4c3..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/clps711x-clock.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2014 Alexander Shiyan +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_CLPS711X_H +-#define __DT_BINDINGS_CLOCK_CLPS711X_H +- +-#define CLPS711X_CLK_DUMMY 0 +-#define CLPS711X_CLK_CPU 1 +-#define CLPS711X_CLK_BUS 2 +-#define CLPS711X_CLK_PLL 3 +-#define CLPS711X_CLK_TIMERREF 4 +-#define CLPS711X_CLK_TIMER1 5 +-#define CLPS711X_CLK_TIMER2 6 +-#define CLPS711X_CLK_PWM 7 +-#define CLPS711X_CLK_SPIREF 8 +-#define CLPS711X_CLK_SPI 9 +-#define CLPS711X_CLK_UART 10 +-#define CLPS711X_CLK_TICK 11 +-#define CLPS711X_CLK_MAX 12 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/cortina,gemini-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/cortina,gemini-clock.h +deleted file mode 100644 +index 04c3404b2d33..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/cortina,gemini-clock.h ++++ /dev/null +@@ -1,30 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef DT_BINDINGS_CORTINA_GEMINI_CLOCK_H +-#define DT_BINDINGS_CORTINA_GEMINI_CLOCK_H +- +-/* RTC, AHB, APB, CPU, PCI, TVC, UART clocks and 13 gates */ +-#define GEMINI_NUM_CLKS 20 +- +-#define GEMINI_CLK_RTC 0 +-#define GEMINI_CLK_AHB 1 +-#define GEMINI_CLK_APB 2 +-#define GEMINI_CLK_CPU 3 +-#define GEMINI_CLK_PCI 4 +-#define GEMINI_CLK_TVC 5 +-#define GEMINI_CLK_UART 6 +-#define GEMINI_CLK_GATES 7 +-#define GEMINI_CLK_GATE_SECURITY 7 +-#define GEMINI_CLK_GATE_GMAC0 8 +-#define GEMINI_CLK_GATE_GMAC1 9 +-#define GEMINI_CLK_GATE_SATA0 10 +-#define GEMINI_CLK_GATE_SATA1 11 +-#define GEMINI_CLK_GATE_USB0 12 +-#define GEMINI_CLK_GATE_USB1 13 +-#define GEMINI_CLK_GATE_IDE 14 +-#define GEMINI_CLK_GATE_PCI 15 +-#define GEMINI_CLK_GATE_DDR 16 +-#define GEMINI_CLK_GATE_FLASH 17 +-#define GEMINI_CLK_GATE_TVC 18 +-#define GEMINI_CLK_GATE_BOOT 19 +- +-#endif /* DT_BINDINGS_CORTINA_GEMINI_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/dm814.h b/scripts/dtc/include-prefixes/dt-bindings/clock/dm814.h +deleted file mode 100644 +index 33b8826d936b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/dm814.h ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2017 Texas Instruments, Inc. +- */ +-#ifndef __DT_BINDINGS_CLK_DM814_H +-#define __DT_BINDINGS_CLK_DM814_H +- +-#define DM814_CLKCTRL_OFFSET 0x0 +-#define DM814_CLKCTRL_INDEX(offset) ((offset) - DM814_CLKCTRL_OFFSET) +- +-/* default clocks */ +-#define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58) +- +-/* alwon clocks */ +-#define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150) +-#define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154) +-#define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158) +-#define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c) +-#define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160) +-#define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164) +-#define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168) +-#define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c) +-#define DM814_MCSPI1_CLKCTRL DM814_CLKCTRL_INDEX(0x190) +-#define DM814_GPMC_CLKCTRL DM814_CLKCTRL_INDEX(0x1d0) +-#define DM814_CPGMAC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1d4) +-#define DM814_MPU_CLKCTRL DM814_CLKCTRL_INDEX(0x1dc) +-#define DM814_RTC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f0) +-#define DM814_TPCC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f4) +-#define DM814_TPTC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1f8) +-#define DM814_TPTC1_CLKCTRL DM814_CLKCTRL_INDEX(0x1fc) +-#define DM814_TPTC2_CLKCTRL DM814_CLKCTRL_INDEX(0x200) +-#define DM814_TPTC3_CLKCTRL DM814_CLKCTRL_INDEX(0x204) +-#define DM814_MMC1_CLKCTRL DM814_CLKCTRL_INDEX(0x21c) +-#define DM814_MMC2_CLKCTRL DM814_CLKCTRL_INDEX(0x220) +-#define DM814_MMC3_CLKCTRL DM814_CLKCTRL_INDEX(0x224) +- +-/* alwon_ethernet clocks */ +-#define DM814_ETHERNET_CLKCTRL_OFFSET 0x1d4 +-#define DM814_ETHERNET_CLKCTRL_INDEX(offset) ((offset) - DM814_ETHERNET_CLKCTRL_OFFSET) +-#define DM814_ETHERNET_CPGMAC0_CLKCTRL DM814_ETHERNET_CLKCTRL_INDEX(0x1d4) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/dm816.h b/scripts/dtc/include-prefixes/dt-bindings/clock/dm816.h +deleted file mode 100644 +index fb0d94174d29..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/dm816.h ++++ /dev/null +@@ -1,45 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2017 Texas Instruments, Inc. +- */ +-#ifndef __DT_BINDINGS_CLK_DM816_H +-#define __DT_BINDINGS_CLK_DM816_H +- +-#define DM816_CLKCTRL_OFFSET 0x0 +-#define DM816_CLKCTRL_INDEX(offset) ((offset) - DM816_CLKCTRL_OFFSET) +- +-/* default clocks */ +-#define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58) +- +-/* alwon clocks */ +-#define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150) +-#define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154) +-#define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158) +-#define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c) +-#define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160) +-#define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164) +-#define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168) +-#define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170) +-#define DM816_TIMER2_CLKCTRL DM816_CLKCTRL_INDEX(0x174) +-#define DM816_TIMER3_CLKCTRL DM816_CLKCTRL_INDEX(0x178) +-#define DM816_TIMER4_CLKCTRL DM816_CLKCTRL_INDEX(0x17c) +-#define DM816_TIMER5_CLKCTRL DM816_CLKCTRL_INDEX(0x180) +-#define DM816_TIMER6_CLKCTRL DM816_CLKCTRL_INDEX(0x184) +-#define DM816_TIMER7_CLKCTRL DM816_CLKCTRL_INDEX(0x188) +-#define DM816_WD_TIMER_CLKCTRL DM816_CLKCTRL_INDEX(0x18c) +-#define DM816_MCSPI1_CLKCTRL DM816_CLKCTRL_INDEX(0x190) +-#define DM816_MAILBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x194) +-#define DM816_SPINBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x198) +-#define DM816_MMC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1b0) +-#define DM816_GPMC_CLKCTRL DM816_CLKCTRL_INDEX(0x1d0) +-#define DM816_DAVINCI_MDIO_CLKCTRL DM816_CLKCTRL_INDEX(0x1d4) +-#define DM816_EMAC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1d8) +-#define DM816_MPU_CLKCTRL DM816_CLKCTRL_INDEX(0x1dc) +-#define DM816_RTC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f0) +-#define DM816_TPCC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f4) +-#define DM816_TPTC0_CLKCTRL DM816_CLKCTRL_INDEX(0x1f8) +-#define DM816_TPTC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1fc) +-#define DM816_TPTC2_CLKCTRL DM816_CLKCTRL_INDEX(0x200) +-#define DM816_TPTC3_CLKCTRL DM816_CLKCTRL_INDEX(0x204) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/dra7.h b/scripts/dtc/include-prefixes/dt-bindings/clock/dra7.h +deleted file mode 100644 +index 7d57063b8a65..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/dra7.h ++++ /dev/null +@@ -1,383 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2017 Texas Instruments, Inc. +- */ +-#ifndef __DT_BINDINGS_CLK_DRA7_H +-#define __DT_BINDINGS_CLK_DRA7_H +- +-#define DRA7_CLKCTRL_OFFSET 0x20 +-#define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET) +- +-/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ +- +-/* mpu clocks */ +-#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +- +-/* ipu clocks */ +-#define _DRA7_IPU_CLKCTRL_OFFSET 0x40 +-#define _DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - _DRA7_IPU_CLKCTRL_OFFSET) +-#define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50) +-#define DRA7_TIMER5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x58) +-#define DRA7_TIMER6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x60) +-#define DRA7_TIMER7_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x68) +-#define DRA7_TIMER8_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x70) +-#define DRA7_I2C5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x78) +-#define DRA7_UART6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x80) +- +-/* rtc clocks */ +-#define DRA7_RTC_CLKCTRL_OFFSET 0x40 +-#define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET) +-#define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44) +- +-/* vip clocks */ +-#define DRA7_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +-#define DRA7_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +-#define DRA7_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +- +-/* vpe clocks */ +-#define DRA7_VPE_CLKCTRL_OFFSET 0x60 +-#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET) +-#define DRA7_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64) +- +-/* coreaon clocks */ +-#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +-#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) +- +-/* l3main1 clocks */ +-#define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +-#define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +-#define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) +-#define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) +-#define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) +-#define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) +-#define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) +- +-/* dma clocks */ +-#define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +- +-/* emif clocks */ +-#define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +- +-/* atl clocks */ +-#define DRA7_ATL_CLKCTRL_OFFSET 0x0 +-#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET) +-#define DRA7_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0) +- +-/* l4cfg clocks */ +-#define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +-#define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +-#define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +-#define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) +-#define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) +-#define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58) +-#define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60) +-#define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68) +-#define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) +-#define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) +-#define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) +-#define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) +-#define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) +-#define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98) +-#define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) +- +-/* l3instr clocks */ +-#define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +-#define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +- +-/* iva clocks */ +-#define DRA7_IVA_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +-#define DRA7_SL2IF_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +- +-/* dss clocks */ +-#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +-#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +- +-/* gpu clocks */ +-#define DRA7_GPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +- +-/* l3init clocks */ +-#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +-#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +-#define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) +-#define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) +-#define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) +-#define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) +-#define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0) +-#define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8) +-#define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0) +-#define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0) +-#define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8) +-#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) +- +-/* l4per clocks */ +-#define _DRA7_L4PER_CLKCTRL_OFFSET 0x0 +-#define _DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - _DRA7_L4PER_CLKCTRL_OFFSET) +-#define DRA7_L4_PER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc) +-#define DRA7_L4_PER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x14) +-#define DRA7_TIMER10_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x28) +-#define DRA7_TIMER11_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x30) +-#define DRA7_TIMER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x38) +-#define DRA7_TIMER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x40) +-#define DRA7_TIMER4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x48) +-#define DRA7_TIMER9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x50) +-#define DRA7_ELM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x58) +-#define DRA7_GPIO2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x60) +-#define DRA7_GPIO3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x68) +-#define DRA7_GPIO4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x70) +-#define DRA7_GPIO5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x78) +-#define DRA7_GPIO6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x80) +-#define DRA7_HDQ1W_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x88) +-#define DRA7_EPWMSS1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x90) +-#define DRA7_EPWMSS2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x98) +-#define DRA7_I2C1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa0) +-#define DRA7_I2C2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa8) +-#define DRA7_I2C3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb0) +-#define DRA7_I2C4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb8) +-#define DRA7_L4_PER1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc0) +-#define DRA7_EPWMSS0_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc4) +-#define DRA7_TIMER13_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc8) +-#define DRA7_TIMER14_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd0) +-#define DRA7_TIMER15_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd8) +-#define DRA7_MCSPI1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf0) +-#define DRA7_MCSPI2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf8) +-#define DRA7_MCSPI3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x100) +-#define DRA7_MCSPI4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x108) +-#define DRA7_GPIO7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x110) +-#define DRA7_GPIO8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x118) +-#define DRA7_MMC3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x120) +-#define DRA7_MMC4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x128) +-#define DRA7_TIMER16_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x130) +-#define DRA7_QSPI_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x138) +-#define DRA7_UART1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x140) +-#define DRA7_UART2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x148) +-#define DRA7_UART3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x150) +-#define DRA7_UART4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x158) +-#define DRA7_MCASP2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x160) +-#define DRA7_MCASP3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x168) +-#define DRA7_UART5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x170) +-#define DRA7_MCASP5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x178) +-#define DRA7_MCASP8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x190) +-#define DRA7_MCASP4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x198) +-#define DRA7_AES1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a0) +-#define DRA7_AES2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a8) +-#define DRA7_DES_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1b0) +-#define DRA7_RNG_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c0) +-#define DRA7_SHAM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c8) +-#define DRA7_UART7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1d0) +-#define DRA7_UART8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e0) +-#define DRA7_UART9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e8) +-#define DRA7_DCAN2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1f0) +-#define DRA7_MCASP6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x204) +-#define DRA7_MCASP7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x208) +- +-/* wkupaon clocks */ +-#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +-#define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +-#define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) +-#define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) +-#define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) +-#define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) +-#define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) +-#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) +-#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) +- +-/* XXX: Compatibility part end. */ +- +-/* mpu clocks */ +-#define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +- +-/* dsp1 clocks */ +-#define DRA7_DSP1_MMU0_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +- +-/* ipu1 clocks */ +-#define DRA7_IPU1_MMU_IPU1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +- +-/* ipu clocks */ +-#define DRA7_IPU_CLKCTRL_OFFSET 0x50 +-#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET) +-#define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50) +-#define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58) +-#define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60) +-#define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68) +-#define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70) +-#define DRA7_IPU_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78) +-#define DRA7_IPU_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80) +- +-/* dsp2 clocks */ +-#define DRA7_DSP2_MMU0_DSP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +- +-/* rtc clocks */ +-#define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44) +- +-/* vip clocks */ +-#define DRA7_CAM_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +-#define DRA7_CAM_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +-#define DRA7_CAM_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +- +-/* vpe clocks */ +-#define DRA7_VPE_CLKCTRL_OFFSET 0x60 +-#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET) +-#define DRA7_VPE_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64) +- +-/* coreaon clocks */ +-#define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +-#define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) +- +-/* l3main1 clocks */ +-#define DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +-#define DRA7_L3MAIN1_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +-#define DRA7_L3MAIN1_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) +-#define DRA7_L3MAIN1_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) +-#define DRA7_L3MAIN1_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) +-#define DRA7_L3MAIN1_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) +-#define DRA7_L3MAIN1_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) +- +-/* ipu2 clocks */ +-#define DRA7_IPU2_MMU_IPU2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +- +-/* dma clocks */ +-#define DRA7_DMA_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +- +-/* emif clocks */ +-#define DRA7_EMIF_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +- +-/* atl clocks */ +-#define DRA7_ATL_CLKCTRL_OFFSET 0x0 +-#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET) +-#define DRA7_ATL_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0) +- +-/* l4cfg clocks */ +-#define DRA7_L4CFG_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +-#define DRA7_L4CFG_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +-#define DRA7_L4CFG_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +-#define DRA7_L4CFG_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) +-#define DRA7_L4CFG_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) +-#define DRA7_L4CFG_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58) +-#define DRA7_L4CFG_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60) +-#define DRA7_L4CFG_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68) +-#define DRA7_L4CFG_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) +-#define DRA7_L4CFG_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) +-#define DRA7_L4CFG_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) +-#define DRA7_L4CFG_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) +-#define DRA7_L4CFG_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) +-#define DRA7_L4CFG_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98) +-#define DRA7_L4CFG_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) +- +-/* l3instr clocks */ +-#define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +-#define DRA7_L3INSTR_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +- +-/* dss clocks */ +-#define DRA7_DSS_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +-#define DRA7_DSS_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +- +-/* l3init clocks */ +-#define DRA7_L3INIT_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +-#define DRA7_L3INIT_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +-#define DRA7_L3INIT_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) +-#define DRA7_L3INIT_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) +-#define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) +-#define DRA7_L3INIT_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) +-#define DRA7_L3INIT_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0) +-#define DRA7_L3INIT_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8) +-#define DRA7_L3INIT_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) +- +-/* pcie clocks */ +-#define DRA7_PCIE_CLKCTRL_OFFSET 0xb0 +-#define DRA7_PCIE_CLKCTRL_INDEX(offset) ((offset) - DRA7_PCIE_CLKCTRL_OFFSET) +-#define DRA7_PCIE_PCIE1_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb0) +-#define DRA7_PCIE_PCIE2_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb8) +- +-/* gmac clocks */ +-#define DRA7_GMAC_CLKCTRL_OFFSET 0xd0 +-#define DRA7_GMAC_CLKCTRL_INDEX(offset) ((offset) - DRA7_GMAC_CLKCTRL_OFFSET) +-#define DRA7_GMAC_GMAC_CLKCTRL DRA7_GMAC_CLKCTRL_INDEX(0xd0) +- +-/* l4per clocks */ +-#define DRA7_L4PER_CLKCTRL_OFFSET 0x28 +-#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET) +-#define DRA7_L4PER_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28) +-#define DRA7_L4PER_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30) +-#define DRA7_L4PER_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38) +-#define DRA7_L4PER_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40) +-#define DRA7_L4PER_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48) +-#define DRA7_L4PER_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50) +-#define DRA7_L4PER_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58) +-#define DRA7_L4PER_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60) +-#define DRA7_L4PER_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68) +-#define DRA7_L4PER_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70) +-#define DRA7_L4PER_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78) +-#define DRA7_L4PER_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80) +-#define DRA7_L4PER_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88) +-#define DRA7_L4PER_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0) +-#define DRA7_L4PER_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8) +-#define DRA7_L4PER_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0) +-#define DRA7_L4PER_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8) +-#define DRA7_L4PER_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0) +-#define DRA7_L4PER_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0) +-#define DRA7_L4PER_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8) +-#define DRA7_L4PER_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100) +-#define DRA7_L4PER_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108) +-#define DRA7_L4PER_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110) +-#define DRA7_L4PER_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118) +-#define DRA7_L4PER_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120) +-#define DRA7_L4PER_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128) +-#define DRA7_L4PER_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140) +-#define DRA7_L4PER_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148) +-#define DRA7_L4PER_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150) +-#define DRA7_L4PER_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158) +-#define DRA7_L4PER_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170) +- +-/* l4sec clocks */ +-#define DRA7_L4SEC_CLKCTRL_OFFSET 0x1a0 +-#define DRA7_L4SEC_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4SEC_CLKCTRL_OFFSET) +-#define DRA7_L4SEC_AES1_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a0) +-#define DRA7_L4SEC_AES2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a8) +-#define DRA7_L4SEC_DES_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1b0) +-#define DRA7_L4SEC_RNG_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c0) +-#define DRA7_L4SEC_SHAM_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c8) +-#define DRA7_L4SEC_SHAM2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1f8) +- +-/* l4per2 clocks */ +-#define DRA7_L4PER2_CLKCTRL_OFFSET 0xc +-#define DRA7_L4PER2_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER2_CLKCTRL_OFFSET) +-#define DRA7_L4PER2_L4_PER2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc) +-#define DRA7_L4PER2_PRUSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x18) +-#define DRA7_L4PER2_PRUSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x20) +-#define DRA7_L4PER2_EPWMSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x90) +-#define DRA7_L4PER2_EPWMSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x98) +-#define DRA7_L4PER2_EPWMSS0_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc4) +-#define DRA7_L4PER2_QSPI_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x138) +-#define DRA7_L4PER2_MCASP2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x160) +-#define DRA7_L4PER2_MCASP3_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x168) +-#define DRA7_L4PER2_MCASP5_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x178) +-#define DRA7_L4PER2_MCASP8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x190) +-#define DRA7_L4PER2_MCASP4_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x198) +-#define DRA7_L4PER2_UART7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1d0) +-#define DRA7_L4PER2_UART8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e0) +-#define DRA7_L4PER2_UART9_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e8) +-#define DRA7_L4PER2_DCAN2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1f0) +-#define DRA7_L4PER2_MCASP6_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x204) +-#define DRA7_L4PER2_MCASP7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x208) +- +-/* l4per3 clocks */ +-#define DRA7_L4PER3_CLKCTRL_OFFSET 0x14 +-#define DRA7_L4PER3_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER3_CLKCTRL_OFFSET) +-#define DRA7_L4PER3_L4_PER3_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x14) +-#define DRA7_L4PER3_TIMER13_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xc8) +-#define DRA7_L4PER3_TIMER14_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd0) +-#define DRA7_L4PER3_TIMER15_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd8) +-#define DRA7_L4PER3_TIMER16_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x130) +- +-/* wkupaon clocks */ +-#define DRA7_WKUPAON_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +-#define DRA7_WKUPAON_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +-#define DRA7_WKUPAON_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) +-#define DRA7_WKUPAON_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) +-#define DRA7_WKUPAON_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) +-#define DRA7_WKUPAON_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) +-#define DRA7_WKUPAON_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) +-#define DRA7_WKUPAON_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) +-#define DRA7_WKUPAON_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/efm32-cmu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/efm32-cmu.h +deleted file mode 100644 +index 4b48d15fe194..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/efm32-cmu.h ++++ /dev/null +@@ -1,43 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_BINDINGS_CLOCK_EFM32_CMU_H +-#define __DT_BINDINGS_CLOCK_EFM32_CMU_H +- +-#define clk_HFXO 0 +-#define clk_HFRCO 1 +-#define clk_LFXO 2 +-#define clk_LFRCO 3 +-#define clk_ULFRCO 4 +-#define clk_AUXHFRCO 5 +-#define clk_HFCLKNODIV 6 +-#define clk_HFCLK 7 +-#define clk_HFPERCLK 8 +-#define clk_HFCORECLK 9 +-#define clk_LFACLK 10 +-#define clk_LFBCLK 11 +-#define clk_WDOGCLK 12 +-#define clk_HFCORECLKDMA 13 +-#define clk_HFCORECLKAES 14 +-#define clk_HFCORECLKUSBC 15 +-#define clk_HFCORECLKUSB 16 +-#define clk_HFCORECLKLE 17 +-#define clk_HFCORECLKEBI 18 +-#define clk_HFPERCLKUSART0 19 +-#define clk_HFPERCLKUSART1 20 +-#define clk_HFPERCLKUSART2 21 +-#define clk_HFPERCLKUART0 22 +-#define clk_HFPERCLKUART1 23 +-#define clk_HFPERCLKTIMER0 24 +-#define clk_HFPERCLKTIMER1 25 +-#define clk_HFPERCLKTIMER2 26 +-#define clk_HFPERCLKTIMER3 27 +-#define clk_HFPERCLKACMP0 28 +-#define clk_HFPERCLKACMP1 29 +-#define clk_HFPERCLKI2C0 30 +-#define clk_HFPERCLKI2C1 31 +-#define clk_HFPERCLKGPIO 32 +-#define clk_HFPERCLKVCMP 33 +-#define clk_HFPERCLKPRS 34 +-#define clk_HFPERCLKADC0 35 +-#define clk_HFPERCLKDAC0 36 +- +-#endif /* __DT_BINDINGS_CLOCK_EFM32_CMU_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/exynos-audss-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/exynos-audss-clk.h +deleted file mode 100644 +index eee9fcc6e6af..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/exynos-audss-clk.h ++++ /dev/null +@@ -1,27 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for Samsung audio subsystem +- * clock controller. +- * +- * The constants defined in this header are being used in dts +- * and exynos audss driver. +- */ +- +-#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H +-#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H +- +-#define EXYNOS_MOUT_AUDSS 0 +-#define EXYNOS_MOUT_I2S 1 +-#define EXYNOS_DOUT_SRP 2 +-#define EXYNOS_DOUT_AUD_BUS 3 +-#define EXYNOS_DOUT_I2S 4 +-#define EXYNOS_SRP_CLK 5 +-#define EXYNOS_I2S_BUS 6 +-#define EXYNOS_SCLK_I2S 7 +-#define EXYNOS_PCM_BUS 8 +-#define EXYNOS_SCLK_PCM 9 +-#define EXYNOS_ADMA 10 +- +-#define EXYNOS_AUDSS_MAX_CLKS 11 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/exynos3250.h b/scripts/dtc/include-prefixes/dt-bindings/clock/exynos3250.h +deleted file mode 100644 +index fe8214017b46..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/exynos3250.h ++++ /dev/null +@@ -1,353 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2014 Samsung Electronics Co., Ltd. +- * Author: Tomasz Figa +- * +- * Device Tree binding constants for Samsung Exynos3250 clock controllers. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H +-#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H +- +-/* +- * Let each exported clock get a unique index, which is used on DT-enabled +- * platforms to lookup the clock from a clock specifier. These indices are +- * therefore considered an ABI and so must not be changed. This implies +- * that new clocks should be added either in free spaces between clock groups +- * or at the end. +- */ +- +- +-/* +- * Main CMU +- */ +- +-#define CLK_OSCSEL 1 +-#define CLK_FIN_PLL 2 +-#define CLK_FOUT_APLL 3 +-#define CLK_FOUT_VPLL 4 +-#define CLK_FOUT_UPLL 5 +-#define CLK_FOUT_MPLL 6 +-#define CLK_ARM_CLK 7 +- +-/* Muxes */ +-#define CLK_MOUT_MPLL_USER_L 16 +-#define CLK_MOUT_GDL 17 +-#define CLK_MOUT_MPLL_USER_R 18 +-#define CLK_MOUT_GDR 19 +-#define CLK_MOUT_EBI 20 +-#define CLK_MOUT_ACLK_200 21 +-#define CLK_MOUT_ACLK_160 22 +-#define CLK_MOUT_ACLK_100 23 +-#define CLK_MOUT_ACLK_266_1 24 +-#define CLK_MOUT_ACLK_266_0 25 +-#define CLK_MOUT_ACLK_266 26 +-#define CLK_MOUT_VPLL 27 +-#define CLK_MOUT_EPLL_USER 28 +-#define CLK_MOUT_EBI_1 29 +-#define CLK_MOUT_UPLL 30 +-#define CLK_MOUT_ACLK_400_MCUISP_SUB 31 +-#define CLK_MOUT_MPLL 32 +-#define CLK_MOUT_ACLK_400_MCUISP 33 +-#define CLK_MOUT_VPLLSRC 34 +-#define CLK_MOUT_CAM1 35 +-#define CLK_MOUT_CAM_BLK 36 +-#define CLK_MOUT_MFC 37 +-#define CLK_MOUT_MFC_1 38 +-#define CLK_MOUT_MFC_0 39 +-#define CLK_MOUT_G3D 40 +-#define CLK_MOUT_G3D_1 41 +-#define CLK_MOUT_G3D_0 42 +-#define CLK_MOUT_MIPI0 43 +-#define CLK_MOUT_FIMD0 44 +-#define CLK_MOUT_UART_ISP 45 +-#define CLK_MOUT_SPI1_ISP 46 +-#define CLK_MOUT_SPI0_ISP 47 +-#define CLK_MOUT_TSADC 48 +-#define CLK_MOUT_MMC1 49 +-#define CLK_MOUT_MMC0 50 +-#define CLK_MOUT_UART1 51 +-#define CLK_MOUT_UART0 52 +-#define CLK_MOUT_SPI1 53 +-#define CLK_MOUT_SPI0 54 +-#define CLK_MOUT_AUDIO 55 +-#define CLK_MOUT_MPLL_USER_C 56 +-#define CLK_MOUT_HPM 57 +-#define CLK_MOUT_CORE 58 +-#define CLK_MOUT_APLL 59 +-#define CLK_MOUT_ACLK_266_SUB 60 +-#define CLK_MOUT_UART2 61 +-#define CLK_MOUT_MMC2 62 +- +-/* Dividers */ +-#define CLK_DIV_GPL 64 +-#define CLK_DIV_GDL 65 +-#define CLK_DIV_GPR 66 +-#define CLK_DIV_GDR 67 +-#define CLK_DIV_MPLL_PRE 68 +-#define CLK_DIV_ACLK_400_MCUISP 69 +-#define CLK_DIV_EBI 70 +-#define CLK_DIV_ACLK_200 71 +-#define CLK_DIV_ACLK_160 72 +-#define CLK_DIV_ACLK_100 73 +-#define CLK_DIV_ACLK_266 74 +-#define CLK_DIV_CAM1 75 +-#define CLK_DIV_CAM_BLK 76 +-#define CLK_DIV_MFC 77 +-#define CLK_DIV_G3D 78 +-#define CLK_DIV_MIPI0_PRE 79 +-#define CLK_DIV_MIPI0 80 +-#define CLK_DIV_FIMD0 81 +-#define CLK_DIV_UART_ISP 82 +-#define CLK_DIV_SPI1_ISP_PRE 83 +-#define CLK_DIV_SPI1_ISP 84 +-#define CLK_DIV_SPI0_ISP_PRE 85 +-#define CLK_DIV_SPI0_ISP 86 +-#define CLK_DIV_TSADC_PRE 87 +-#define CLK_DIV_TSADC 88 +-#define CLK_DIV_MMC1_PRE 89 +-#define CLK_DIV_MMC1 90 +-#define CLK_DIV_MMC0_PRE 91 +-#define CLK_DIV_MMC0 92 +-#define CLK_DIV_UART1 93 +-#define CLK_DIV_UART0 94 +-#define CLK_DIV_SPI1_PRE 95 +-#define CLK_DIV_SPI1 96 +-#define CLK_DIV_SPI0_PRE 97 +-#define CLK_DIV_SPI0 98 +-#define CLK_DIV_PCM 99 +-#define CLK_DIV_AUDIO 100 +-#define CLK_DIV_I2S 101 +-#define CLK_DIV_CORE2 102 +-#define CLK_DIV_APLL 103 +-#define CLK_DIV_PCLK_DBG 104 +-#define CLK_DIV_ATB 105 +-#define CLK_DIV_COREM 106 +-#define CLK_DIV_CORE 107 +-#define CLK_DIV_HPM 108 +-#define CLK_DIV_COPY 109 +-#define CLK_DIV_UART2 110 +-#define CLK_DIV_MMC2_PRE 111 +-#define CLK_DIV_MMC2 112 +- +-/* Gates */ +-#define CLK_ASYNC_G3D 128 +-#define CLK_ASYNC_MFCL 129 +-#define CLK_PPMULEFT 130 +-#define CLK_GPIO_LEFT 131 +-#define CLK_ASYNC_ISPMX 132 +-#define CLK_ASYNC_FSYSD 133 +-#define CLK_ASYNC_LCD0X 134 +-#define CLK_ASYNC_CAMX 135 +-#define CLK_PPMURIGHT 136 +-#define CLK_GPIO_RIGHT 137 +-#define CLK_MONOCNT 138 +-#define CLK_TZPC6 139 +-#define CLK_PROVISIONKEY1 140 +-#define CLK_PROVISIONKEY0 141 +-#define CLK_CMU_ISPPART 142 +-#define CLK_TMU_APBIF 143 +-#define CLK_KEYIF 144 +-#define CLK_RTC 145 +-#define CLK_WDT 146 +-#define CLK_MCT 147 +-#define CLK_SECKEY 148 +-#define CLK_TZPC5 149 +-#define CLK_TZPC4 150 +-#define CLK_TZPC3 151 +-#define CLK_TZPC2 152 +-#define CLK_TZPC1 153 +-#define CLK_TZPC0 154 +-#define CLK_CMU_COREPART 155 +-#define CLK_CMU_TOPPART 156 +-#define CLK_PMU_APBIF 157 +-#define CLK_SYSREG 158 +-#define CLK_CHIP_ID 159 +-#define CLK_QEJPEG 160 +-#define CLK_PIXELASYNCM1 161 +-#define CLK_PIXELASYNCM0 162 +-#define CLK_PPMUCAMIF 163 +-#define CLK_QEM2MSCALER 164 +-#define CLK_QEGSCALER1 165 +-#define CLK_QEGSCALER0 166 +-#define CLK_SMMUJPEG 167 +-#define CLK_SMMUM2M2SCALER 168 +-#define CLK_SMMUGSCALER1 169 +-#define CLK_SMMUGSCALER0 170 +-#define CLK_JPEG 171 +-#define CLK_M2MSCALER 172 +-#define CLK_GSCALER1 173 +-#define CLK_GSCALER0 174 +-#define CLK_QEMFC 175 +-#define CLK_PPMUMFC_L 176 +-#define CLK_SMMUMFC_L 177 +-#define CLK_MFC 178 +-#define CLK_SMMUG3D 179 +-#define CLK_QEG3D 180 +-#define CLK_PPMUG3D 181 +-#define CLK_G3D 182 +-#define CLK_QE_CH1_LCD 183 +-#define CLK_QE_CH0_LCD 184 +-#define CLK_PPMULCD0 185 +-#define CLK_SMMUFIMD0 186 +-#define CLK_DSIM0 187 +-#define CLK_FIMD0 188 +-#define CLK_CAM1 189 +-#define CLK_UART_ISP_TOP 190 +-#define CLK_SPI1_ISP_TOP 191 +-#define CLK_SPI0_ISP_TOP 192 +-#define CLK_TSADC 193 +-#define CLK_PPMUFILE 194 +-#define CLK_USBOTG 195 +-#define CLK_USBHOST 196 +-#define CLK_SROMC 197 +-#define CLK_SDMMC1 198 +-#define CLK_SDMMC0 199 +-#define CLK_PDMA1 200 +-#define CLK_PDMA0 201 +-#define CLK_PWM 202 +-#define CLK_PCM 203 +-#define CLK_I2S 204 +-#define CLK_SPI1 205 +-#define CLK_SPI0 206 +-#define CLK_I2C7 207 +-#define CLK_I2C6 208 +-#define CLK_I2C5 209 +-#define CLK_I2C4 210 +-#define CLK_I2C3 211 +-#define CLK_I2C2 212 +-#define CLK_I2C1 213 +-#define CLK_I2C0 214 +-#define CLK_UART1 215 +-#define CLK_UART0 216 +-#define CLK_BLOCK_LCD 217 +-#define CLK_BLOCK_G3D 218 +-#define CLK_BLOCK_MFC 219 +-#define CLK_BLOCK_CAM 220 +-#define CLK_SMIES 221 +-#define CLK_UART2 222 +-#define CLK_SDMMC2 223 +- +-/* Special clocks */ +-#define CLK_SCLK_JPEG 224 +-#define CLK_SCLK_M2MSCALER 225 +-#define CLK_SCLK_GSCALER1 226 +-#define CLK_SCLK_GSCALER0 227 +-#define CLK_SCLK_MFC 228 +-#define CLK_SCLK_G3D 229 +-#define CLK_SCLK_MIPIDPHY2L 230 +-#define CLK_SCLK_MIPI0 231 +-#define CLK_SCLK_FIMD0 232 +-#define CLK_SCLK_CAM1 233 +-#define CLK_SCLK_UART_ISP 234 +-#define CLK_SCLK_SPI1_ISP 235 +-#define CLK_SCLK_SPI0_ISP 236 +-#define CLK_SCLK_UPLL 237 +-#define CLK_SCLK_TSADC 238 +-#define CLK_SCLK_EBI 239 +-#define CLK_SCLK_MMC1 240 +-#define CLK_SCLK_MMC0 241 +-#define CLK_SCLK_I2S 242 +-#define CLK_SCLK_PCM 243 +-#define CLK_SCLK_SPI1 244 +-#define CLK_SCLK_SPI0 245 +-#define CLK_SCLK_UART1 246 +-#define CLK_SCLK_UART0 247 +-#define CLK_SCLK_UART2 248 +-#define CLK_SCLK_MMC2 249 +- +-/* +- * Total number of clocks of main CMU. +- * NOTE: Must be equal to last clock ID increased by one. +- */ +-#define CLK_NR_CLKS 250 +- +-/* +- * CMU DMC +- */ +- +-#define CLK_FOUT_BPLL 1 +-#define CLK_FOUT_EPLL 2 +- +-/* Muxes */ +-#define CLK_MOUT_MPLL_MIF 8 +-#define CLK_MOUT_BPLL 9 +-#define CLK_MOUT_DPHY 10 +-#define CLK_MOUT_DMC_BUS 11 +-#define CLK_MOUT_EPLL 12 +- +-/* Dividers */ +-#define CLK_DIV_DMC 16 +-#define CLK_DIV_DPHY 17 +-#define CLK_DIV_DMC_PRE 18 +-#define CLK_DIV_DMCP 19 +-#define CLK_DIV_DMCD 20 +- +-/* +- * Total number of clocks of main CMU. +- * NOTE: Must be equal to last clock ID increased by one. +- */ +-#define NR_CLKS_DMC 21 +- +-/* +- * CMU ISP +- */ +- +-/* Dividers */ +- +-#define CLK_DIV_ISP1 1 +-#define CLK_DIV_ISP0 2 +-#define CLK_DIV_MCUISP1 3 +-#define CLK_DIV_MCUISP0 4 +-#define CLK_DIV_MPWM 5 +- +-/* Gates */ +- +-#define CLK_UART_ISP 8 +-#define CLK_WDT_ISP 9 +-#define CLK_PWM_ISP 10 +-#define CLK_I2C1_ISP 11 +-#define CLK_I2C0_ISP 12 +-#define CLK_MPWM_ISP 13 +-#define CLK_MCUCTL_ISP 14 +-#define CLK_PPMUISPX 15 +-#define CLK_PPMUISPMX 16 +-#define CLK_QE_LITE1 17 +-#define CLK_QE_LITE0 18 +-#define CLK_QE_FD 19 +-#define CLK_QE_DRC 20 +-#define CLK_QE_ISP 21 +-#define CLK_CSIS1 22 +-#define CLK_SMMU_LITE1 23 +-#define CLK_SMMU_LITE0 24 +-#define CLK_SMMU_FD 25 +-#define CLK_SMMU_DRC 26 +-#define CLK_SMMU_ISP 27 +-#define CLK_GICISP 28 +-#define CLK_CSIS0 29 +-#define CLK_MCUISP 30 +-#define CLK_LITE1 31 +-#define CLK_LITE0 32 +-#define CLK_FD 33 +-#define CLK_DRC 34 +-#define CLK_ISP 35 +-#define CLK_QE_ISPCX 36 +-#define CLK_QE_SCALERP 37 +-#define CLK_QE_SCALERC 38 +-#define CLK_SMMU_SCALERP 39 +-#define CLK_SMMU_SCALERC 40 +-#define CLK_SCALERP 41 +-#define CLK_SCALERC 42 +-#define CLK_SPI1_ISP 43 +-#define CLK_SPI0_ISP 44 +-#define CLK_SMMU_ISPCX 45 +-#define CLK_ASYNCAXIM 46 +-#define CLK_SCLK_MPWM_ISP 47 +- +-/* +- * Total number of clocks of CMU_ISP. +- * NOTE: Must be equal to last clock ID increased by one. +- */ +-#define NR_CLKS_ISP 48 +- +-#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/exynos4.h b/scripts/dtc/include-prefixes/dt-bindings/clock/exynos4.h +deleted file mode 100644 +index 88ec3968b90a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/exynos4.h ++++ /dev/null +@@ -1,278 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * Author: Andrzej Hajda +- * +- * Device Tree binding constants for Exynos4 clock controller. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H +-#define _DT_BINDINGS_CLOCK_EXYNOS_4_H +- +-/* core clocks */ +-#define CLK_XXTI 1 +-#define CLK_XUSBXTI 2 +-#define CLK_FIN_PLL 3 +-#define CLK_FOUT_APLL 4 +-#define CLK_FOUT_MPLL 5 +-#define CLK_FOUT_EPLL 6 +-#define CLK_FOUT_VPLL 7 +-#define CLK_SCLK_APLL 8 +-#define CLK_SCLK_MPLL 9 +-#define CLK_SCLK_EPLL 10 +-#define CLK_SCLK_VPLL 11 +-#define CLK_ARM_CLK 12 +-#define CLK_ACLK200 13 +-#define CLK_ACLK100 14 +-#define CLK_ACLK160 15 +-#define CLK_ACLK133 16 +-#define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */ +-#define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */ +-#define CLK_MOUT_CORE 19 +-#define CLK_MOUT_APLL 20 +-#define CLK_SCLK_HDMIPHY 22 +-#define CLK_OUT_DMC 23 +-#define CLK_OUT_TOP 24 +-#define CLK_OUT_LEFTBUS 25 +-#define CLK_OUT_RIGHTBUS 26 +-#define CLK_OUT_CPU 27 +- +-/* gate for special clocks (sclk) */ +-#define CLK_SCLK_FIMC0 128 +-#define CLK_SCLK_FIMC1 129 +-#define CLK_SCLK_FIMC2 130 +-#define CLK_SCLK_FIMC3 131 +-#define CLK_SCLK_CAM0 132 +-#define CLK_SCLK_CAM1 133 +-#define CLK_SCLK_CSIS0 134 +-#define CLK_SCLK_CSIS1 135 +-#define CLK_SCLK_HDMI 136 +-#define CLK_SCLK_MIXER 137 +-#define CLK_SCLK_DAC 138 +-#define CLK_SCLK_PIXEL 139 +-#define CLK_SCLK_FIMD0 140 +-#define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */ +-#define CLK_SCLK_MDNIE_PWM0 142 +-#define CLK_SCLK_MIPI0 143 +-#define CLK_SCLK_AUDIO0 144 +-#define CLK_SCLK_MMC0 145 +-#define CLK_SCLK_MMC1 146 +-#define CLK_SCLK_MMC2 147 +-#define CLK_SCLK_MMC3 148 +-#define CLK_SCLK_MMC4 149 +-#define CLK_SCLK_SATA 150 /* Exynos4210 only */ +-#define CLK_SCLK_UART0 151 +-#define CLK_SCLK_UART1 152 +-#define CLK_SCLK_UART2 153 +-#define CLK_SCLK_UART3 154 +-#define CLK_SCLK_UART4 155 +-#define CLK_SCLK_AUDIO1 156 +-#define CLK_SCLK_AUDIO2 157 +-#define CLK_SCLK_SPDIF 158 +-#define CLK_SCLK_SPI0 159 +-#define CLK_SCLK_SPI1 160 +-#define CLK_SCLK_SPI2 161 +-#define CLK_SCLK_SLIMBUS 162 +-#define CLK_SCLK_FIMD1 163 /* Exynos4210 only */ +-#define CLK_SCLK_MIPI1 164 /* Exynos4210 only */ +-#define CLK_SCLK_PCM1 165 +-#define CLK_SCLK_PCM2 166 +-#define CLK_SCLK_I2S1 167 +-#define CLK_SCLK_I2S2 168 +-#define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */ +-#define CLK_SCLK_MFC 170 +-#define CLK_SCLK_PCM0 171 +-#define CLK_SCLK_G3D 172 +-#define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */ +-#define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */ +-#define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */ +-#define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */ +-#define CLK_SCLK_FIMG2D 177 +- +-/* gate clocks */ +-#define CLK_SSS 255 +-#define CLK_FIMC0 256 +-#define CLK_FIMC1 257 +-#define CLK_FIMC2 258 +-#define CLK_FIMC3 259 +-#define CLK_CSIS0 260 +-#define CLK_CSIS1 261 +-#define CLK_JPEG 262 +-#define CLK_SMMU_FIMC0 263 +-#define CLK_SMMU_FIMC1 264 +-#define CLK_SMMU_FIMC2 265 +-#define CLK_SMMU_FIMC3 266 +-#define CLK_SMMU_JPEG 267 +-#define CLK_VP 268 +-#define CLK_MIXER 269 +-#define CLK_TVENC 270 /* Exynos4210 only */ +-#define CLK_HDMI 271 +-#define CLK_SMMU_TV 272 +-#define CLK_MFC 273 +-#define CLK_SMMU_MFCL 274 +-#define CLK_SMMU_MFCR 275 +-#define CLK_G3D 276 +-#define CLK_G2D 277 +-#define CLK_ROTATOR 278 +-#define CLK_MDMA 279 +-#define CLK_SMMU_G2D 280 +-#define CLK_SMMU_ROTATOR 281 +-#define CLK_SMMU_MDMA 282 +-#define CLK_FIMD0 283 +-#define CLK_MIE0 284 +-#define CLK_MDNIE0 285 /* Exynos4412 only */ +-#define CLK_DSIM0 286 +-#define CLK_SMMU_FIMD0 287 +-#define CLK_FIMD1 288 /* Exynos4210 only */ +-#define CLK_MIE1 289 /* Exynos4210 only */ +-#define CLK_DSIM1 290 /* Exynos4210 only */ +-#define CLK_SMMU_FIMD1 291 /* Exynos4210 only */ +-#define CLK_PDMA0 292 +-#define CLK_PDMA1 293 +-#define CLK_PCIE_PHY 294 +-#define CLK_SATA_PHY 295 /* Exynos4210 only */ +-#define CLK_TSI 296 +-#define CLK_SDMMC0 297 +-#define CLK_SDMMC1 298 +-#define CLK_SDMMC2 299 +-#define CLK_SDMMC3 300 +-#define CLK_SDMMC4 301 +-#define CLK_SATA 302 /* Exynos4210 only */ +-#define CLK_SROMC 303 +-#define CLK_USB_HOST 304 +-#define CLK_USB_DEVICE 305 +-#define CLK_PCIE 306 +-#define CLK_ONENAND 307 +-#define CLK_NFCON 308 +-#define CLK_SMMU_PCIE 309 +-#define CLK_GPS 310 +-#define CLK_SMMU_GPS 311 +-#define CLK_UART0 312 +-#define CLK_UART1 313 +-#define CLK_UART2 314 +-#define CLK_UART3 315 +-#define CLK_UART4 316 +-#define CLK_I2C0 317 +-#define CLK_I2C1 318 +-#define CLK_I2C2 319 +-#define CLK_I2C3 320 +-#define CLK_I2C4 321 +-#define CLK_I2C5 322 +-#define CLK_I2C6 323 +-#define CLK_I2C7 324 +-#define CLK_I2C_HDMI 325 +-#define CLK_TSADC 326 +-#define CLK_SPI0 327 +-#define CLK_SPI1 328 +-#define CLK_SPI2 329 +-#define CLK_I2S1 330 +-#define CLK_I2S2 331 +-#define CLK_PCM0 332 +-#define CLK_I2S0 333 +-#define CLK_PCM1 334 +-#define CLK_PCM2 335 +-#define CLK_PWM 336 +-#define CLK_SLIMBUS 337 +-#define CLK_SPDIF 338 +-#define CLK_AC97 339 +-#define CLK_MODEMIF 340 +-#define CLK_CHIPID 341 +-#define CLK_SYSREG 342 +-#define CLK_HDMI_CEC 343 +-#define CLK_MCT 344 +-#define CLK_WDT 345 +-#define CLK_RTC 346 +-#define CLK_KEYIF 347 +-#define CLK_AUDSS 348 +-#define CLK_MIPI_HSI 349 /* Exynos4210 only */ +-#define CLK_PIXELASYNCM0 351 +-#define CLK_PIXELASYNCM1 352 +-#define CLK_ASYNC_G3D 353 /* Exynos4x12 only */ +-#define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ +-#define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ +-#define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */ +-#define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */ +-#define CLK_TMU_APBIF 383 +- +-/* mux clocks */ +-#define CLK_MOUT_FIMC0 384 +-#define CLK_MOUT_FIMC1 385 +-#define CLK_MOUT_FIMC2 386 +-#define CLK_MOUT_FIMC3 387 +-#define CLK_MOUT_CAM0 388 +-#define CLK_MOUT_CAM1 389 +-#define CLK_MOUT_CSIS0 390 +-#define CLK_MOUT_CSIS1 391 +-#define CLK_MOUT_G3D0 392 +-#define CLK_MOUT_G3D1 393 +-#define CLK_MOUT_G3D 394 +-#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */ +-#define CLK_MOUT_HDMI 396 +-#define CLK_MOUT_MIXER 397 +- +-/* gate clocks - ppmu */ +-#define CLK_PPMULEFT 400 +-#define CLK_PPMURIGHT 401 +-#define CLK_PPMUCAMIF 402 +-#define CLK_PPMUTV 403 +-#define CLK_PPMUMFC_L 404 +-#define CLK_PPMUMFC_R 405 +-#define CLK_PPMUG3D 406 +-#define CLK_PPMUIMAGE 407 +-#define CLK_PPMULCD0 408 +-#define CLK_PPMULCD1 409 /* Exynos4210 only */ +-#define CLK_PPMUFILE 410 +-#define CLK_PPMUGPS 411 +-#define CLK_PPMUDMC0 412 +-#define CLK_PPMUDMC1 413 +-#define CLK_PPMUCPU 414 +-#define CLK_PPMUACP 415 +- +-/* div clocks */ +-#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ +-#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ +-#define CLK_DIV_ACP 456 +-#define CLK_DIV_DMC 457 +-#define CLK_DIV_C2C 458 /* Exynos4x12 only */ +-#define CLK_DIV_GDL 459 +-#define CLK_DIV_GDR 460 +- +-/* must be greater than maximal clock id */ +-#define CLK_NR_CLKS 461 +- +-/* Exynos4x12 ISP clocks */ +-#define CLK_ISP_FIMC_ISP 1 +-#define CLK_ISP_FIMC_DRC 2 +-#define CLK_ISP_FIMC_FD 3 +-#define CLK_ISP_FIMC_LITE0 4 +-#define CLK_ISP_FIMC_LITE1 5 +-#define CLK_ISP_MCUISP 6 +-#define CLK_ISP_GICISP 7 +-#define CLK_ISP_SMMU_ISP 8 +-#define CLK_ISP_SMMU_DRC 9 +-#define CLK_ISP_SMMU_FD 10 +-#define CLK_ISP_SMMU_LITE0 11 +-#define CLK_ISP_SMMU_LITE1 12 +-#define CLK_ISP_PPMUISPMX 13 +-#define CLK_ISP_PPMUISPX 14 +-#define CLK_ISP_MCUCTL_ISP 15 +-#define CLK_ISP_MPWM_ISP 16 +-#define CLK_ISP_I2C0_ISP 17 +-#define CLK_ISP_I2C1_ISP 18 +-#define CLK_ISP_MTCADC_ISP 19 +-#define CLK_ISP_PWM_ISP 20 +-#define CLK_ISP_WDT_ISP 21 +-#define CLK_ISP_UART_ISP 22 +-#define CLK_ISP_ASYNCAXIM 23 +-#define CLK_ISP_SMMU_ISPCX 24 +-#define CLK_ISP_SPI0_ISP 25 +-#define CLK_ISP_SPI1_ISP 26 +- +-#define CLK_ISP_DIV_ISP0 27 +-#define CLK_ISP_DIV_ISP1 28 +-#define CLK_ISP_DIV_MCUISP0 29 +-#define CLK_ISP_DIV_MCUISP1 30 +- +-#define CLK_NR_ISP_CLKS 31 +- +-#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/exynos5250.h b/scripts/dtc/include-prefixes/dt-bindings/clock/exynos5250.h +deleted file mode 100644 +index e259cc01f22f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/exynos5250.h ++++ /dev/null +@@ -1,181 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * Author: Andrzej Hajda +- * +- * Device Tree binding constants for Exynos5250 clock controller. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H +-#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H +- +-/* core clocks */ +-#define CLK_FIN_PLL 1 +-#define CLK_FOUT_APLL 2 +-#define CLK_FOUT_MPLL 3 +-#define CLK_FOUT_BPLL 4 +-#define CLK_FOUT_GPLL 5 +-#define CLK_FOUT_CPLL 6 +-#define CLK_FOUT_EPLL 7 +-#define CLK_FOUT_VPLL 8 +-#define CLK_ARM_CLK 9 +- +-/* gate for special clocks (sclk) */ +-#define CLK_SCLK_CAM_BAYER 128 +-#define CLK_SCLK_CAM0 129 +-#define CLK_SCLK_CAM1 130 +-#define CLK_SCLK_GSCL_WA 131 +-#define CLK_SCLK_GSCL_WB 132 +-#define CLK_SCLK_FIMD1 133 +-#define CLK_SCLK_MIPI1 134 +-#define CLK_SCLK_DP 135 +-#define CLK_SCLK_HDMI 136 +-#define CLK_SCLK_PIXEL 137 +-#define CLK_SCLK_AUDIO0 138 +-#define CLK_SCLK_MMC0 139 +-#define CLK_SCLK_MMC1 140 +-#define CLK_SCLK_MMC2 141 +-#define CLK_SCLK_MMC3 142 +-#define CLK_SCLK_SATA 143 +-#define CLK_SCLK_USB3 144 +-#define CLK_SCLK_JPEG 145 +-#define CLK_SCLK_UART0 146 +-#define CLK_SCLK_UART1 147 +-#define CLK_SCLK_UART2 148 +-#define CLK_SCLK_UART3 149 +-#define CLK_SCLK_PWM 150 +-#define CLK_SCLK_AUDIO1 151 +-#define CLK_SCLK_AUDIO2 152 +-#define CLK_SCLK_SPDIF 153 +-#define CLK_SCLK_SPI0 154 +-#define CLK_SCLK_SPI1 155 +-#define CLK_SCLK_SPI2 156 +-#define CLK_DIV_I2S1 157 +-#define CLK_DIV_I2S2 158 +-#define CLK_SCLK_HDMIPHY 159 +-#define CLK_DIV_PCM0 160 +- +-/* gate clocks */ +-#define CLK_GSCL0 256 +-#define CLK_GSCL1 257 +-#define CLK_GSCL2 258 +-#define CLK_GSCL3 259 +-#define CLK_GSCL_WA 260 +-#define CLK_GSCL_WB 261 +-#define CLK_SMMU_GSCL0 262 +-#define CLK_SMMU_GSCL1 263 +-#define CLK_SMMU_GSCL2 264 +-#define CLK_SMMU_GSCL3 265 +-#define CLK_MFC 266 +-#define CLK_SMMU_MFCL 267 +-#define CLK_SMMU_MFCR 268 +-#define CLK_ROTATOR 269 +-#define CLK_JPEG 270 +-#define CLK_MDMA1 271 +-#define CLK_SMMU_ROTATOR 272 +-#define CLK_SMMU_JPEG 273 +-#define CLK_SMMU_MDMA1 274 +-#define CLK_PDMA0 275 +-#define CLK_PDMA1 276 +-#define CLK_SATA 277 +-#define CLK_USBOTG 278 +-#define CLK_MIPI_HSI 279 +-#define CLK_SDMMC0 280 +-#define CLK_SDMMC1 281 +-#define CLK_SDMMC2 282 +-#define CLK_SDMMC3 283 +-#define CLK_SROMC 284 +-#define CLK_USB2 285 +-#define CLK_USB3 286 +-#define CLK_SATA_PHYCTRL 287 +-#define CLK_SATA_PHYI2C 288 +-#define CLK_UART0 289 +-#define CLK_UART1 290 +-#define CLK_UART2 291 +-#define CLK_UART3 292 +-#define CLK_UART4 293 +-#define CLK_I2C0 294 +-#define CLK_I2C1 295 +-#define CLK_I2C2 296 +-#define CLK_I2C3 297 +-#define CLK_I2C4 298 +-#define CLK_I2C5 299 +-#define CLK_I2C6 300 +-#define CLK_I2C7 301 +-#define CLK_I2C_HDMI 302 +-#define CLK_ADC 303 +-#define CLK_SPI0 304 +-#define CLK_SPI1 305 +-#define CLK_SPI2 306 +-#define CLK_I2S1 307 +-#define CLK_I2S2 308 +-#define CLK_PCM1 309 +-#define CLK_PCM2 310 +-#define CLK_PWM 311 +-#define CLK_SPDIF 312 +-#define CLK_AC97 313 +-#define CLK_HSI2C0 314 +-#define CLK_HSI2C1 315 +-#define CLK_HSI2C2 316 +-#define CLK_HSI2C3 317 +-#define CLK_CHIPID 318 +-#define CLK_SYSREG 319 +-#define CLK_PMU 320 +-#define CLK_CMU_TOP 321 +-#define CLK_CMU_CORE 322 +-#define CLK_CMU_MEM 323 +-#define CLK_TZPC0 324 +-#define CLK_TZPC1 325 +-#define CLK_TZPC2 326 +-#define CLK_TZPC3 327 +-#define CLK_TZPC4 328 +-#define CLK_TZPC5 329 +-#define CLK_TZPC6 330 +-#define CLK_TZPC7 331 +-#define CLK_TZPC8 332 +-#define CLK_TZPC9 333 +-#define CLK_HDMI_CEC 334 +-#define CLK_MCT 335 +-#define CLK_WDT 336 +-#define CLK_RTC 337 +-#define CLK_TMU 338 +-#define CLK_FIMD1 339 +-#define CLK_MIE1 340 +-#define CLK_DSIM0 341 +-#define CLK_DP 342 +-#define CLK_MIXER 343 +-#define CLK_HDMI 344 +-#define CLK_G2D 345 +-#define CLK_MDMA0 346 +-#define CLK_SMMU_MDMA0 347 +-#define CLK_SSS 348 +-#define CLK_G3D 349 +-#define CLK_SMMU_TV 350 +-#define CLK_SMMU_FIMD1 351 +-#define CLK_SMMU_2D 352 +-#define CLK_SMMU_FIMC_ISP 353 +-#define CLK_SMMU_FIMC_DRC 354 +-#define CLK_SMMU_FIMC_SCC 355 +-#define CLK_SMMU_FIMC_SCP 356 +-#define CLK_SMMU_FIMC_FD 357 +-#define CLK_SMMU_FIMC_MCU 358 +-#define CLK_SMMU_FIMC_ODC 359 +-#define CLK_SMMU_FIMC_DIS0 360 +-#define CLK_SMMU_FIMC_DIS1 361 +-#define CLK_SMMU_FIMC_3DNR 362 +-#define CLK_SMMU_FIMC_LITE0 363 +-#define CLK_SMMU_FIMC_LITE1 364 +-#define CLK_CAMIF_TOP 365 +- +-/* mux clocks */ +-#define CLK_MOUT_HDMI 1024 +-#define CLK_MOUT_GPLL 1025 +-#define CLK_MOUT_ACLK200_DISP1_SUB 1026 +-#define CLK_MOUT_ACLK300_DISP1_SUB 1027 +-#define CLK_MOUT_APLL 1028 +-#define CLK_MOUT_MPLL 1029 +- +-/* must be greater than maximal clock id */ +-#define CLK_NR_CLKS 1030 +- +-#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/exynos5260-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/exynos5260-clk.h +deleted file mode 100644 +index 98a58cbd81b2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/exynos5260-clk.h ++++ /dev/null +@@ -1,466 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2014 Samsung Electronics Co., Ltd. +- * Author: Rahul Sharma +- * +- * Provides Constants for Exynos5260 clocks. +- */ +- +-#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H +-#define _DT_BINDINGS_CLK_EXYNOS5260_H +- +-/* Clock names: */ +- +-/* List Of Clocks For CMU_TOP */ +- +-#define TOP_FOUT_DISP_PLL 1 +-#define TOP_FOUT_AUD_PLL 2 +-#define TOP_MOUT_AUDTOP_PLL_USER 3 +-#define TOP_MOUT_AUD_PLL 4 +-#define TOP_MOUT_DISP_PLL 5 +-#define TOP_MOUT_BUSTOP_PLL_USER 6 +-#define TOP_MOUT_MEMTOP_PLL_USER 7 +-#define TOP_MOUT_MEDIATOP_PLL_USER 8 +-#define TOP_MOUT_DISP_DISP_333 9 +-#define TOP_MOUT_ACLK_DISP_333 10 +-#define TOP_MOUT_DISP_DISP_222 11 +-#define TOP_MOUT_ACLK_DISP_222 12 +-#define TOP_MOUT_DISP_MEDIA_PIXEL 13 +-#define TOP_MOUT_FIMD1 14 +-#define TOP_MOUT_SCLK_PERI_SPI0_CLK 15 +-#define TOP_MOUT_SCLK_PERI_SPI1_CLK 16 +-#define TOP_MOUT_SCLK_PERI_SPI2_CLK 17 +-#define TOP_MOUT_SCLK_PERI_UART0_UCLK 18 +-#define TOP_MOUT_SCLK_PERI_UART2_UCLK 19 +-#define TOP_MOUT_SCLK_PERI_UART1_UCLK 20 +-#define TOP_MOUT_BUS4_BUSTOP_100 21 +-#define TOP_MOUT_BUS4_BUSTOP_400 22 +-#define TOP_MOUT_BUS3_BUSTOP_100 23 +-#define TOP_MOUT_BUS3_BUSTOP_400 24 +-#define TOP_MOUT_BUS2_BUSTOP_400 25 +-#define TOP_MOUT_BUS2_BUSTOP_100 26 +-#define TOP_MOUT_BUS1_BUSTOP_100 27 +-#define TOP_MOUT_BUS1_BUSTOP_400 28 +-#define TOP_MOUT_SCLK_FSYS_USB 29 +-#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A 30 +-#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A 31 +-#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A 32 +-#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B 33 +-#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B 34 +-#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B 35 +-#define TOP_MOUT_ACLK_ISP1_266 36 +-#define TOP_MOUT_ISP1_MEDIA_266 37 +-#define TOP_MOUT_ACLK_ISP1_400 38 +-#define TOP_MOUT_ISP1_MEDIA_400 39 +-#define TOP_MOUT_SCLK_ISP1_SPI0 40 +-#define TOP_MOUT_SCLK_ISP1_SPI1 41 +-#define TOP_MOUT_SCLK_ISP1_UART 42 +-#define TOP_MOUT_SCLK_ISP1_SENSOR2 43 +-#define TOP_MOUT_SCLK_ISP1_SENSOR1 44 +-#define TOP_MOUT_SCLK_ISP1_SENSOR0 45 +-#define TOP_MOUT_ACLK_MFC_333 46 +-#define TOP_MOUT_MFC_BUSTOP_333 47 +-#define TOP_MOUT_ACLK_G2D_333 48 +-#define TOP_MOUT_G2D_BUSTOP_333 49 +-#define TOP_MOUT_ACLK_GSCL_FIMC 50 +-#define TOP_MOUT_GSCL_BUSTOP_FIMC 51 +-#define TOP_MOUT_ACLK_GSCL_333 52 +-#define TOP_MOUT_GSCL_BUSTOP_333 53 +-#define TOP_MOUT_ACLK_GSCL_400 54 +-#define TOP_MOUT_M2M_MEDIATOP_400 55 +-#define TOP_DOUT_ACLK_MFC_333 56 +-#define TOP_DOUT_ACLK_G2D_333 57 +-#define TOP_DOUT_SCLK_ISP1_SENSOR2_A 58 +-#define TOP_DOUT_SCLK_ISP1_SENSOR1_A 59 +-#define TOP_DOUT_SCLK_ISP1_SENSOR0_A 60 +-#define TOP_DOUT_ACLK_GSCL_FIMC 61 +-#define TOP_DOUT_ACLK_GSCL_400 62 +-#define TOP_DOUT_ACLK_GSCL_333 63 +-#define TOP_DOUT_SCLK_ISP1_SPI0_B 64 +-#define TOP_DOUT_SCLK_ISP1_SPI0_A 65 +-#define TOP_DOUT_ACLK_ISP1_400 66 +-#define TOP_DOUT_ACLK_ISP1_266 67 +-#define TOP_DOUT_SCLK_ISP1_UART 68 +-#define TOP_DOUT_SCLK_ISP1_SPI1_B 69 +-#define TOP_DOUT_SCLK_ISP1_SPI1_A 70 +-#define TOP_DOUT_SCLK_ISP1_SENSOR2_B 71 +-#define TOP_DOUT_SCLK_ISP1_SENSOR1_B 72 +-#define TOP_DOUT_SCLK_ISP1_SENSOR0_B 73 +-#define TOP_DOUTTOP__SCLK_HPM_TARGETCLK 74 +-#define TOP_DOUT_SCLK_DISP_PIXEL 75 +-#define TOP_DOUT_ACLK_DISP_222 76 +-#define TOP_DOUT_ACLK_DISP_333 77 +-#define TOP_DOUT_ACLK_BUS4_100 78 +-#define TOP_DOUT_ACLK_BUS4_400 79 +-#define TOP_DOUT_ACLK_BUS3_100 80 +-#define TOP_DOUT_ACLK_BUS3_400 81 +-#define TOP_DOUT_ACLK_BUS2_100 82 +-#define TOP_DOUT_ACLK_BUS2_400 83 +-#define TOP_DOUT_ACLK_BUS1_100 84 +-#define TOP_DOUT_ACLK_BUS1_400 85 +-#define TOP_DOUT_SCLK_PERI_SPI1_B 86 +-#define TOP_DOUT_SCLK_PERI_SPI1_A 87 +-#define TOP_DOUT_SCLK_PERI_SPI0_B 88 +-#define TOP_DOUT_SCLK_PERI_SPI0_A 89 +-#define TOP_DOUT_SCLK_PERI_UART0 90 +-#define TOP_DOUT_SCLK_PERI_UART2 91 +-#define TOP_DOUT_SCLK_PERI_UART1 92 +-#define TOP_DOUT_SCLK_PERI_SPI2_B 93 +-#define TOP_DOUT_SCLK_PERI_SPI2_A 94 +-#define TOP_DOUT_ACLK_PERI_AUD 95 +-#define TOP_DOUT_ACLK_PERI_66 96 +-#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B 97 +-#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A 98 +-#define TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK 99 +-#define TOP_DOUT_ACLK_FSYS_200 100 +-#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B 101 +-#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A 102 +-#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B 103 +-#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A 104 +-#define TOP_SCLK_FIMD1 105 +-#define TOP_SCLK_MMC2 106 +-#define TOP_SCLK_MMC1 107 +-#define TOP_SCLK_MMC0 108 +-#define PHYCLK_DPTX_PHY_CH3_TXD_CLK 109 +-#define PHYCLK_DPTX_PHY_CH2_TXD_CLK 110 +-#define PHYCLK_DPTX_PHY_CH1_TXD_CLK 111 +-#define PHYCLK_DPTX_PHY_CH0_TXD_CLK 112 +-#define phyclk_hdmi_phy_tmds_clko 113 +-#define PHYCLK_HDMI_PHY_PIXEL_CLKO 114 +-#define PHYCLK_HDMI_LINK_O_TMDS_CLKHI 115 +-#define PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS 116 +-#define PHYCLK_DPTX_PHY_O_REF_CLK_24M 117 +-#define PHYCLK_DPTX_PHY_CLK_DIV2 118 +-#define PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0 119 +-#define PHYCLK_USBHOST20_PHY_PHYCLOCK 120 +-#define PHYCLK_USBHOST20_PHY_FREECLK 121 +-#define PHYCLK_USBHOST20_PHY_CLK48MOHCI 122 +-#define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 123 +-#define PHYCLK_USBDRD30_UDRD30_PHYCLOCK 124 +-#define TOP_NR_CLK 125 +- +- +-/* List Of Clocks For CMU_EGL */ +- +-#define EGL_FOUT_EGL_PLL 1 +-#define EGL_FOUT_EGL_DPLL 2 +-#define EGL_MOUT_EGL_B 3 +-#define EGL_MOUT_EGL_PLL 4 +-#define EGL_DOUT_EGL_PLL 5 +-#define EGL_DOUT_EGL_PCLK_DBG 6 +-#define EGL_DOUT_EGL_ATCLK 7 +-#define EGL_DOUT_PCLK_EGL 8 +-#define EGL_DOUT_ACLK_EGL 9 +-#define EGL_DOUT_EGL2 10 +-#define EGL_DOUT_EGL1 11 +-#define EGL_NR_CLK 12 +- +- +-/* List Of Clocks For CMU_KFC */ +- +-#define KFC_FOUT_KFC_PLL 1 +-#define KFC_MOUT_KFC_PLL 2 +-#define KFC_MOUT_KFC 3 +-#define KFC_DOUT_KFC_PLL 4 +-#define KFC_DOUT_PCLK_KFC 5 +-#define KFC_DOUT_ACLK_KFC 6 +-#define KFC_DOUT_KFC_PCLK_DBG 7 +-#define KFC_DOUT_KFC_ATCLK 8 +-#define KFC_DOUT_KFC2 9 +-#define KFC_DOUT_KFC1 10 +-#define KFC_NR_CLK 11 +- +- +-/* List Of Clocks For CMU_MIF */ +- +-#define MIF_FOUT_MEM_PLL 1 +-#define MIF_FOUT_MEDIA_PLL 2 +-#define MIF_FOUT_BUS_PLL 3 +-#define MIF_MOUT_CLK2X_PHY 4 +-#define MIF_MOUT_MIF_DREX2X 5 +-#define MIF_MOUT_CLKM_PHY 6 +-#define MIF_MOUT_MIF_DREX 7 +-#define MIF_MOUT_MEDIA_PLL 8 +-#define MIF_MOUT_BUS_PLL 9 +-#define MIF_MOUT_MEM_PLL 10 +-#define MIF_DOUT_ACLK_BUS_100 11 +-#define MIF_DOUT_ACLK_BUS_200 12 +-#define MIF_DOUT_ACLK_MIF_466 13 +-#define MIF_DOUT_CLK2X_PHY 14 +-#define MIF_DOUT_CLKM_PHY 15 +-#define MIF_DOUT_BUS_PLL 16 +-#define MIF_DOUT_MEM_PLL 17 +-#define MIF_DOUT_MEDIA_PLL 18 +-#define MIF_CLK_LPDDR3PHY_WRAP1 19 +-#define MIF_CLK_LPDDR3PHY_WRAP0 20 +-#define MIF_CLK_MONOCNT 21 +-#define MIF_CLK_MIF_RTC 22 +-#define MIF_CLK_DREX1 23 +-#define MIF_CLK_DREX0 24 +-#define MIF_CLK_INTMEM 25 +-#define MIF_SCLK_LPDDR3PHY_WRAP_U1 26 +-#define MIF_SCLK_LPDDR3PHY_WRAP_U0 27 +-#define MIF_NR_CLK 28 +- +- +-/* List Of Clocks For CMU_G3D */ +- +-#define G3D_FOUT_G3D_PLL 1 +-#define G3D_MOUT_G3D_PLL 2 +-#define G3D_DOUT_PCLK_G3D 3 +-#define G3D_DOUT_ACLK_G3D 4 +-#define G3D_CLK_G3D_HPM 5 +-#define G3D_CLK_G3D 6 +-#define G3D_NR_CLK 7 +- +- +-/* List Of Clocks For CMU_AUD */ +- +-#define AUD_MOUT_SCLK_AUD_PCM 1 +-#define AUD_MOUT_SCLK_AUD_I2S 2 +-#define AUD_MOUT_AUD_PLL_USER 3 +-#define AUD_DOUT_ACLK_AUD_131 4 +-#define AUD_DOUT_SCLK_AUD_UART 5 +-#define AUD_DOUT_SCLK_AUD_PCM 6 +-#define AUD_DOUT_SCLK_AUD_I2S 7 +-#define AUD_CLK_AUD_UART 8 +-#define AUD_CLK_PCM 9 +-#define AUD_CLK_I2S 10 +-#define AUD_CLK_DMAC 11 +-#define AUD_CLK_SRAMC 12 +-#define AUD_SCLK_AUD_UART 13 +-#define AUD_SCLK_PCM 14 +-#define AUD_SCLK_I2S 15 +-#define AUD_NR_CLK 16 +- +- +-/* List Of Clocks For CMU_MFC */ +- +-#define MFC_MOUT_ACLK_MFC_333_USER 1 +-#define MFC_DOUT_PCLK_MFC_83 2 +-#define MFC_CLK_MFC 3 +-#define MFC_CLK_SMMU2_MFCM1 4 +-#define MFC_CLK_SMMU2_MFCM0 5 +-#define MFC_NR_CLK 6 +- +- +-/* List Of Clocks For CMU_GSCL */ +- +-#define GSCL_MOUT_ACLK_CSIS 1 +-#define GSCL_MOUT_ACLK_GSCL_FIMC_USER 2 +-#define GSCL_MOUT_ACLK_M2M_400_USER 3 +-#define GSCL_MOUT_ACLK_GSCL_333_USER 4 +-#define GSCL_DOUT_ACLK_CSIS_200 5 +-#define GSCL_DOUT_PCLK_M2M_100 6 +-#define GSCL_CLK_PIXEL_GSCL1 7 +-#define GSCL_CLK_PIXEL_GSCL0 8 +-#define GSCL_CLK_MSCL1 9 +-#define GSCL_CLK_MSCL0 10 +-#define GSCL_CLK_GSCL1 11 +-#define GSCL_CLK_GSCL0 12 +-#define GSCL_CLK_FIMC_LITE_D 13 +-#define GSCL_CLK_FIMC_LITE_B 14 +-#define GSCL_CLK_FIMC_LITE_A 15 +-#define GSCL_CLK_CSIS1 16 +-#define GSCL_CLK_CSIS0 17 +-#define GSCL_CLK_SMMU3_LITE_D 18 +-#define GSCL_CLK_SMMU3_LITE_B 19 +-#define GSCL_CLK_SMMU3_LITE_A 20 +-#define GSCL_CLK_SMMU3_GSCL0 21 +-#define GSCL_CLK_SMMU3_GSCL1 22 +-#define GSCL_CLK_SMMU3_MSCL0 23 +-#define GSCL_CLK_SMMU3_MSCL1 24 +-#define GSCL_SCLK_CSIS1_WRAP 25 +-#define GSCL_SCLK_CSIS0_WRAP 26 +-#define GSCL_NR_CLK 27 +- +- +-/* List Of Clocks For CMU_FSYS */ +- +-#define FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER 1 +-#define FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER 2 +-#define FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER 3 +-#define FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER 4 +-#define FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER 5 +-#define FSYS_CLK_TSI 6 +-#define FSYS_CLK_USBLINK 7 +-#define FSYS_CLK_USBHOST20 8 +-#define FSYS_CLK_USBDRD30 9 +-#define FSYS_CLK_SROMC 10 +-#define FSYS_CLK_PDMA 11 +-#define FSYS_CLK_MMC2 12 +-#define FSYS_CLK_MMC1 13 +-#define FSYS_CLK_MMC0 14 +-#define FSYS_CLK_RTIC 15 +-#define FSYS_CLK_SMMU_RTIC 16 +-#define FSYS_PHYCLK_USBDRD30 17 +-#define FSYS_PHYCLK_USBHOST20 18 +-#define FSYS_NR_CLK 19 +- +- +-/* List Of Clocks For CMU_PERI */ +- +-#define PERI_MOUT_SCLK_SPDIF 1 +-#define PERI_MOUT_SCLK_I2SCOD 2 +-#define PERI_MOUT_SCLK_PCM 3 +-#define PERI_DOUT_I2S 4 +-#define PERI_DOUT_PCM 5 +-#define PERI_CLK_WDT_KFC 6 +-#define PERI_CLK_WDT_EGL 7 +-#define PERI_CLK_HSIC3 8 +-#define PERI_CLK_HSIC2 9 +-#define PERI_CLK_HSIC1 10 +-#define PERI_CLK_HSIC0 11 +-#define PERI_CLK_PCM 12 +-#define PERI_CLK_MCT 13 +-#define PERI_CLK_I2S 14 +-#define PERI_CLK_I2CHDMI 15 +-#define PERI_CLK_I2C7 16 +-#define PERI_CLK_I2C6 17 +-#define PERI_CLK_I2C5 18 +-#define PERI_CLK_I2C4 19 +-#define PERI_CLK_I2C9 20 +-#define PERI_CLK_I2C8 21 +-#define PERI_CLK_I2C11 22 +-#define PERI_CLK_I2C10 23 +-#define PERI_CLK_HDMICEC 24 +-#define PERI_CLK_EFUSE_WRITER 25 +-#define PERI_CLK_ABB 26 +-#define PERI_CLK_UART2 27 +-#define PERI_CLK_UART1 28 +-#define PERI_CLK_UART0 29 +-#define PERI_CLK_ADC 30 +-#define PERI_CLK_TMU4 31 +-#define PERI_CLK_TMU3 32 +-#define PERI_CLK_TMU2 33 +-#define PERI_CLK_TMU1 34 +-#define PERI_CLK_TMU0 35 +-#define PERI_CLK_SPI2 36 +-#define PERI_CLK_SPI1 37 +-#define PERI_CLK_SPI0 38 +-#define PERI_CLK_SPDIF 39 +-#define PERI_CLK_PWM 40 +-#define PERI_CLK_UART4 41 +-#define PERI_CLK_CHIPID 42 +-#define PERI_CLK_PROVKEY0 43 +-#define PERI_CLK_PROVKEY1 44 +-#define PERI_CLK_SECKEY 45 +-#define PERI_CLK_TOP_RTC 46 +-#define PERI_CLK_TZPC10 47 +-#define PERI_CLK_TZPC9 48 +-#define PERI_CLK_TZPC8 49 +-#define PERI_CLK_TZPC7 50 +-#define PERI_CLK_TZPC6 51 +-#define PERI_CLK_TZPC5 52 +-#define PERI_CLK_TZPC4 53 +-#define PERI_CLK_TZPC3 54 +-#define PERI_CLK_TZPC2 55 +-#define PERI_CLK_TZPC1 56 +-#define PERI_CLK_TZPC0 57 +-#define PERI_SCLK_UART2 58 +-#define PERI_SCLK_UART1 59 +-#define PERI_SCLK_UART0 60 +-#define PERI_SCLK_SPI2 61 +-#define PERI_SCLK_SPI1 62 +-#define PERI_SCLK_SPI0 63 +-#define PERI_SCLK_SPDIF 64 +-#define PERI_SCLK_I2S 65 +-#define PERI_SCLK_PCM1 66 +-#define PERI_NR_CLK 67 +- +- +-/* List Of Clocks For CMU_DISP */ +- +-#define DISP_MOUT_SCLK_HDMI_SPDIF 1 +-#define DISP_MOUT_SCLK_HDMI_PIXEL 2 +-#define DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER 3 +-#define DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER 4 +-#define DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER 5 +-#define DISP_MOUT_HDMI_PHY_PIXEL 6 +-#define DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER 7 +-#define DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS 8 +-#define DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER 9 +-#define DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER 10 +-#define DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER 11 +-#define DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER 12 +-#define DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER 13 +-#define DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER 14 +-#define DISP_MOUT_ACLK_DISP_222_USER 15 +-#define DISP_MOUT_SCLK_DISP_PIXEL_USER 16 +-#define DISP_MOUT_ACLK_DISP_333_USER 17 +-#define DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI 18 +-#define DISP_DOUT_SCLK_FIMD1_EXTCLKPLL 19 +-#define DISP_DOUT_PCLK_DISP_111 20 +-#define DISP_CLK_SMMU_TV 21 +-#define DISP_CLK_SMMU_FIMD1M1 22 +-#define DISP_CLK_SMMU_FIMD1M0 23 +-#define DISP_CLK_PIXEL_MIXER 24 +-#define DISP_CLK_PIXEL_DISP 25 +-#define DISP_CLK_MIXER 26 +-#define DISP_CLK_MIPIPHY 27 +-#define DISP_CLK_HDMIPHY 28 +-#define DISP_CLK_HDMI 29 +-#define DISP_CLK_FIMD1 30 +-#define DISP_CLK_DSIM1 31 +-#define DISP_CLK_DPPHY 32 +-#define DISP_CLK_DP 33 +-#define DISP_SCLK_PIXEL 34 +-#define DISP_MOUT_HDMI_PHY_PIXEL_USER 35 +-#define DISP_NR_CLK 36 +- +- +-/* List Of Clocks For CMU_G2D */ +- +-#define G2D_MOUT_ACLK_G2D_333_USER 1 +-#define G2D_DOUT_PCLK_G2D_83 2 +-#define G2D_CLK_SMMU3_JPEG 3 +-#define G2D_CLK_MDMA 4 +-#define G2D_CLK_JPEG 5 +-#define G2D_CLK_G2D 6 +-#define G2D_CLK_SSS 7 +-#define G2D_CLK_SLIM_SSS 8 +-#define G2D_CLK_SMMU_SLIM_SSS 9 +-#define G2D_CLK_SMMU_SSS 10 +-#define G2D_CLK_SMMU_MDMA 11 +-#define G2D_CLK_SMMU3_G2D 12 +-#define G2D_NR_CLK 13 +- +- +-/* List Of Clocks For CMU_ISP */ +- +-#define ISP_MOUT_ISP_400_USER 1 +-#define ISP_MOUT_ISP_266_USER 2 +-#define ISP_DOUT_SCLK_MPWM 3 +-#define ISP_DOUT_CA5_PCLKDBG 4 +-#define ISP_DOUT_CA5_ATCLKIN 5 +-#define ISP_DOUT_PCLK_ISP_133 6 +-#define ISP_DOUT_PCLK_ISP_66 7 +-#define ISP_CLK_GIC 8 +-#define ISP_CLK_WDT 9 +-#define ISP_CLK_UART 10 +-#define ISP_CLK_SPI1 11 +-#define ISP_CLK_SPI0 12 +-#define ISP_CLK_SMMU_SCALERP 13 +-#define ISP_CLK_SMMU_SCALERC 14 +-#define ISP_CLK_SMMU_ISPCX 15 +-#define ISP_CLK_SMMU_ISP 16 +-#define ISP_CLK_SMMU_FD 17 +-#define ISP_CLK_SMMU_DRC 18 +-#define ISP_CLK_PWM 19 +-#define ISP_CLK_MTCADC 20 +-#define ISP_CLK_MPWM 21 +-#define ISP_CLK_MCUCTL 22 +-#define ISP_CLK_I2C1 23 +-#define ISP_CLK_I2C0 24 +-#define ISP_CLK_FIMC_SCALERP 25 +-#define ISP_CLK_FIMC_SCALERC 26 +-#define ISP_CLK_FIMC 27 +-#define ISP_CLK_FIMC_FD 28 +-#define ISP_CLK_FIMC_DRC 29 +-#define ISP_CLK_CA5 30 +-#define ISP_SCLK_SPI0_EXT 31 +-#define ISP_SCLK_SPI1_EXT 32 +-#define ISP_SCLK_UART_EXT 33 +-#define ISP_NR_CLK 34 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/exynos5410.h b/scripts/dtc/include-prefixes/dt-bindings/clock/exynos5410.h +deleted file mode 100644 +index 86c2ad56c5ef..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/exynos5410.h ++++ /dev/null +@@ -1,66 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2014 Samsung Electronics Co., Ltd. +- * Copyright (c) 2016 Krzysztof Kozlowski +- * +- * Device Tree binding constants for Exynos5421 clock controller. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H +-#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H +- +-/* core clocks */ +-#define CLK_FIN_PLL 1 +-#define CLK_FOUT_APLL 2 +-#define CLK_FOUT_CPLL 3 +-#define CLK_FOUT_MPLL 4 +-#define CLK_FOUT_BPLL 5 +-#define CLK_FOUT_KPLL 6 +-#define CLK_FOUT_EPLL 7 +- +-/* gate for special clocks (sclk) */ +-#define CLK_SCLK_UART0 128 +-#define CLK_SCLK_UART1 129 +-#define CLK_SCLK_UART2 130 +-#define CLK_SCLK_UART3 131 +-#define CLK_SCLK_MMC0 132 +-#define CLK_SCLK_MMC1 133 +-#define CLK_SCLK_MMC2 134 +-#define CLK_SCLK_USBD300 150 +-#define CLK_SCLK_USBD301 151 +-#define CLK_SCLK_USBPHY300 152 +-#define CLK_SCLK_USBPHY301 153 +-#define CLK_SCLK_PWM 155 +- +-/* gate clocks */ +-#define CLK_UART0 257 +-#define CLK_UART1 258 +-#define CLK_UART2 259 +-#define CLK_UART3 260 +-#define CLK_I2C0 261 +-#define CLK_I2C1 262 +-#define CLK_I2C2 263 +-#define CLK_I2C3 264 +-#define CLK_USI0 265 +-#define CLK_USI1 266 +-#define CLK_USI2 267 +-#define CLK_USI3 268 +-#define CLK_TSADC 270 +-#define CLK_PWM 279 +-#define CLK_MCT 315 +-#define CLK_WDT 316 +-#define CLK_RTC 317 +-#define CLK_TMU 318 +-#define CLK_MMC0 351 +-#define CLK_MMC1 352 +-#define CLK_MMC2 353 +-#define CLK_PDMA0 362 +-#define CLK_PDMA1 363 +-#define CLK_USBH20 365 +-#define CLK_USBD300 366 +-#define CLK_USBD301 367 +-#define CLK_SSS 471 +- +-#define CLK_NR_CLKS 512 +- +-#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/exynos5420.h b/scripts/dtc/include-prefixes/dt-bindings/clock/exynos5420.h +deleted file mode 100644 +index 9fffc6ceaadd..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/exynos5420.h ++++ /dev/null +@@ -1,277 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * Author: Andrzej Hajda +- * +- * Device Tree binding constants for Exynos5420 clock controller. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H +-#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H +- +-/* core clocks */ +-#define CLK_FIN_PLL 1 +-#define CLK_FOUT_APLL 2 +-#define CLK_FOUT_CPLL 3 +-#define CLK_FOUT_DPLL 4 +-#define CLK_FOUT_EPLL 5 +-#define CLK_FOUT_RPLL 6 +-#define CLK_FOUT_IPLL 7 +-#define CLK_FOUT_SPLL 8 +-#define CLK_FOUT_VPLL 9 +-#define CLK_FOUT_MPLL 10 +-#define CLK_FOUT_BPLL 11 +-#define CLK_FOUT_KPLL 12 +-#define CLK_ARM_CLK 13 +-#define CLK_KFC_CLK 14 +- +-/* gate for special clocks (sclk) */ +-#define CLK_SCLK_UART0 128 +-#define CLK_SCLK_UART1 129 +-#define CLK_SCLK_UART2 130 +-#define CLK_SCLK_UART3 131 +-#define CLK_SCLK_MMC0 132 +-#define CLK_SCLK_MMC1 133 +-#define CLK_SCLK_MMC2 134 +-#define CLK_SCLK_SPI0 135 +-#define CLK_SCLK_SPI1 136 +-#define CLK_SCLK_SPI2 137 +-#define CLK_SCLK_I2S1 138 +-#define CLK_SCLK_I2S2 139 +-#define CLK_SCLK_PCM1 140 +-#define CLK_SCLK_PCM2 141 +-#define CLK_SCLK_SPDIF 142 +-#define CLK_SCLK_HDMI 143 +-#define CLK_SCLK_PIXEL 144 +-#define CLK_SCLK_DP1 145 +-#define CLK_SCLK_MIPI1 146 +-#define CLK_SCLK_FIMD1 147 +-#define CLK_SCLK_MAUDIO0 148 +-#define CLK_SCLK_MAUPCM0 149 +-#define CLK_SCLK_USBD300 150 +-#define CLK_SCLK_USBD301 151 +-#define CLK_SCLK_USBPHY300 152 +-#define CLK_SCLK_USBPHY301 153 +-#define CLK_SCLK_UNIPRO 154 +-#define CLK_SCLK_PWM 155 +-#define CLK_SCLK_GSCL_WA 156 +-#define CLK_SCLK_GSCL_WB 157 +-#define CLK_SCLK_HDMIPHY 158 +-#define CLK_MAU_EPLL 159 +-#define CLK_SCLK_HSIC_12M 160 +-#define CLK_SCLK_MPHY_IXTAL24 161 +-#define CLK_SCLK_BPLL 162 +- +-/* gate clocks */ +-#define CLK_UART0 257 +-#define CLK_UART1 258 +-#define CLK_UART2 259 +-#define CLK_UART3 260 +-#define CLK_I2C0 261 +-#define CLK_I2C1 262 +-#define CLK_I2C2 263 +-#define CLK_I2C3 264 +-#define CLK_USI0 265 +-#define CLK_USI1 266 +-#define CLK_USI2 267 +-#define CLK_USI3 268 +-#define CLK_I2C_HDMI 269 +-#define CLK_TSADC 270 +-#define CLK_SPI0 271 +-#define CLK_SPI1 272 +-#define CLK_SPI2 273 +-#define CLK_KEYIF 274 +-#define CLK_I2S1 275 +-#define CLK_I2S2 276 +-#define CLK_PCM1 277 +-#define CLK_PCM2 278 +-#define CLK_PWM 279 +-#define CLK_SPDIF 280 +-#define CLK_USI4 281 +-#define CLK_USI5 282 +-#define CLK_USI6 283 +-#define CLK_ACLK66_PSGEN 300 +-#define CLK_CHIPID 301 +-#define CLK_SYSREG 302 +-#define CLK_TZPC0 303 +-#define CLK_TZPC1 304 +-#define CLK_TZPC2 305 +-#define CLK_TZPC3 306 +-#define CLK_TZPC4 307 +-#define CLK_TZPC5 308 +-#define CLK_TZPC6 309 +-#define CLK_TZPC7 310 +-#define CLK_TZPC8 311 +-#define CLK_TZPC9 312 +-#define CLK_HDMI_CEC 313 +-#define CLK_SECKEY 314 +-#define CLK_MCT 315 +-#define CLK_WDT 316 +-#define CLK_RTC 317 +-#define CLK_TMU 318 +-#define CLK_TMU_GPU 319 +-#define CLK_PCLK66_GPIO 330 +-#define CLK_ACLK200_FSYS2 350 +-#define CLK_MMC0 351 +-#define CLK_MMC1 352 +-#define CLK_MMC2 353 +-#define CLK_SROMC 354 +-#define CLK_UFS 355 +-#define CLK_ACLK200_FSYS 360 +-#define CLK_TSI 361 +-#define CLK_PDMA0 362 +-#define CLK_PDMA1 363 +-#define CLK_RTIC 364 +-#define CLK_USBH20 365 +-#define CLK_USBD300 366 +-#define CLK_USBD301 367 +-#define CLK_ACLK400_MSCL 380 +-#define CLK_MSCL0 381 +-#define CLK_MSCL1 382 +-#define CLK_MSCL2 383 +-#define CLK_SMMU_MSCL0 384 +-#define CLK_SMMU_MSCL1 385 +-#define CLK_SMMU_MSCL2 386 +-#define CLK_ACLK333 400 +-#define CLK_MFC 401 +-#define CLK_SMMU_MFCL 402 +-#define CLK_SMMU_MFCR 403 +-#define CLK_ACLK200_DISP1 410 +-#define CLK_DSIM1 411 +-#define CLK_DP1 412 +-#define CLK_HDMI 413 +-#define CLK_ACLK300_DISP1 420 +-#define CLK_FIMD1 421 +-#define CLK_SMMU_FIMD1M0 422 +-#define CLK_SMMU_FIMD1M1 423 +-#define CLK_ACLK166 430 +-#define CLK_MIXER 431 +-#define CLK_ACLK266 440 +-#define CLK_ROTATOR 441 +-#define CLK_MDMA1 442 +-#define CLK_SMMU_ROTATOR 443 +-#define CLK_SMMU_MDMA1 444 +-#define CLK_ACLK300_JPEG 450 +-#define CLK_JPEG 451 +-#define CLK_JPEG2 452 +-#define CLK_SMMU_JPEG 453 +-#define CLK_SMMU_JPEG2 454 +-#define CLK_ACLK300_GSCL 460 +-#define CLK_SMMU_GSCL0 461 +-#define CLK_SMMU_GSCL1 462 +-#define CLK_GSCL_WA 463 +-#define CLK_GSCL_WB 464 +-#define CLK_GSCL0 465 +-#define CLK_GSCL1 466 +-#define CLK_FIMC_3AA 467 +-#define CLK_ACLK266_G2D 470 +-#define CLK_SSS 471 +-#define CLK_SLIM_SSS 472 +-#define CLK_MDMA0 473 +-#define CLK_ACLK333_G2D 480 +-#define CLK_G2D 481 +-#define CLK_ACLK333_432_GSCL 490 +-#define CLK_SMMU_3AA 491 +-#define CLK_SMMU_FIMCL0 492 +-#define CLK_SMMU_FIMCL1 493 +-#define CLK_SMMU_FIMCL3 494 +-#define CLK_FIMC_LITE3 495 +-#define CLK_FIMC_LITE0 496 +-#define CLK_FIMC_LITE1 497 +-#define CLK_ACLK_G3D 500 +-#define CLK_G3D 501 +-#define CLK_SMMU_MIXER 502 +-#define CLK_SMMU_G2D 503 +-#define CLK_SMMU_MDMA0 504 +-#define CLK_MC 505 +-#define CLK_TOP_RTC 506 +-#define CLK_SCLK_UART_ISP 510 +-#define CLK_SCLK_SPI0_ISP 511 +-#define CLK_SCLK_SPI1_ISP 512 +-#define CLK_SCLK_PWM_ISP 513 +-#define CLK_SCLK_ISP_SENSOR0 514 +-#define CLK_SCLK_ISP_SENSOR1 515 +-#define CLK_SCLK_ISP_SENSOR2 516 +-#define CLK_ACLK432_SCALER 517 +-#define CLK_ACLK432_CAM 518 +-#define CLK_ACLK_FL1550_CAM 519 +-#define CLK_ACLK550_CAM 520 +-#define CLK_CLKM_PHY0 521 +-#define CLK_CLKM_PHY1 522 +-#define CLK_ACLK_PPMU_DREX0_0 523 +-#define CLK_ACLK_PPMU_DREX0_1 524 +-#define CLK_ACLK_PPMU_DREX1_0 525 +-#define CLK_ACLK_PPMU_DREX1_1 526 +-#define CLK_PCLK_PPMU_DREX0_0 527 +-#define CLK_PCLK_PPMU_DREX0_1 528 +-#define CLK_PCLK_PPMU_DREX1_0 529 +-#define CLK_PCLK_PPMU_DREX1_1 530 +- +-/* mux clocks */ +-#define CLK_MOUT_HDMI 640 +-#define CLK_MOUT_G3D 641 +-#define CLK_MOUT_VPLL 642 +-#define CLK_MOUT_MAUDIO0 643 +-#define CLK_MOUT_USER_ACLK333 644 +-#define CLK_MOUT_SW_ACLK333 645 +-#define CLK_MOUT_USER_ACLK200_DISP1 646 +-#define CLK_MOUT_SW_ACLK200 647 +-#define CLK_MOUT_USER_ACLK300_DISP1 648 +-#define CLK_MOUT_SW_ACLK300 649 +-#define CLK_MOUT_USER_ACLK400_DISP1 650 +-#define CLK_MOUT_SW_ACLK400 651 +-#define CLK_MOUT_USER_ACLK300_GSCL 652 +-#define CLK_MOUT_SW_ACLK300_GSCL 653 +-#define CLK_MOUT_MCLK_CDREX 654 +-#define CLK_MOUT_BPLL 655 +-#define CLK_MOUT_MX_MSPLL_CCORE 656 +-#define CLK_MOUT_EPLL 657 +-#define CLK_MOUT_MAU_EPLL 658 +-#define CLK_MOUT_USER_MAU_EPLL 659 +-#define CLK_MOUT_SCLK_SPLL 660 +-#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661 +-#define CLK_MOUT_SW_ACLK_G3D 662 +-#define CLK_MOUT_APLL 663 +-#define CLK_MOUT_MSPLL_CPU 664 +-#define CLK_MOUT_KPLL 665 +-#define CLK_MOUT_MSPLL_KFC 666 +- +- +-/* divider clocks */ +-#define CLK_DOUT_PIXEL 768 +-#define CLK_DOUT_ACLK400_WCORE 769 +-#define CLK_DOUT_ACLK400_ISP 770 +-#define CLK_DOUT_ACLK400_MSCL 771 +-#define CLK_DOUT_ACLK200 772 +-#define CLK_DOUT_ACLK200_FSYS2 773 +-#define CLK_DOUT_ACLK100_NOC 774 +-#define CLK_DOUT_PCLK200_FSYS 775 +-#define CLK_DOUT_ACLK200_FSYS 776 +-#define CLK_DOUT_ACLK333_432_GSCL 777 +-#define CLK_DOUT_ACLK333_432_ISP 778 +-#define CLK_DOUT_ACLK66 779 +-#define CLK_DOUT_ACLK333_432_ISP0 780 +-#define CLK_DOUT_ACLK266 781 +-#define CLK_DOUT_ACLK166 782 +-#define CLK_DOUT_ACLK333 783 +-#define CLK_DOUT_ACLK333_G2D 784 +-#define CLK_DOUT_ACLK266_G2D 785 +-#define CLK_DOUT_ACLK_G3D 786 +-#define CLK_DOUT_ACLK300_JPEG 787 +-#define CLK_DOUT_ACLK300_DISP1 788 +-#define CLK_DOUT_ACLK300_GSCL 789 +-#define CLK_DOUT_ACLK400_DISP1 790 +-#define CLK_DOUT_PCLK_CDREX 791 +-#define CLK_DOUT_SCLK_CDREX 792 +-#define CLK_DOUT_ACLK_CDREX1 793 +-#define CLK_DOUT_CCLK_DREX0 794 +-#define CLK_DOUT_CLK2X_PHY0 795 +-#define CLK_DOUT_PCLK_CORE_MEM 796 +-#define CLK_FF_DOUT_SPLL2 797 +-#define CLK_DOUT_PCLK_DREX0 798 +-#define CLK_DOUT_PCLK_DREX1 799 +- +-/* must be greater than maximal clock id */ +-#define CLK_NR_CLKS 800 +- +-#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/exynos5433.h b/scripts/dtc/include-prefixes/dt-bindings/clock/exynos5433.h +deleted file mode 100644 +index 25ffa53573a5..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/exynos5433.h ++++ /dev/null +@@ -1,1415 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2014 Samsung Electronics Co., Ltd. +- * Author: Chanwoo Choi +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H +-#define _DT_BINDINGS_CLOCK_EXYNOS5433_H +- +-/* CMU_TOP */ +-#define CLK_FOUT_ISP_PLL 1 +-#define CLK_FOUT_AUD_PLL 2 +- +-#define CLK_MOUT_AUD_PLL 10 +-#define CLK_MOUT_ISP_PLL 11 +-#define CLK_MOUT_AUD_PLL_USER_T 12 +-#define CLK_MOUT_MPHY_PLL_USER 13 +-#define CLK_MOUT_MFC_PLL_USER 14 +-#define CLK_MOUT_BUS_PLL_USER 15 +-#define CLK_MOUT_ACLK_HEVC_400 16 +-#define CLK_MOUT_ACLK_CAM1_333 17 +-#define CLK_MOUT_ACLK_CAM1_552_B 18 +-#define CLK_MOUT_ACLK_CAM1_552_A 19 +-#define CLK_MOUT_ACLK_ISP_DIS_400 20 +-#define CLK_MOUT_ACLK_ISP_400 21 +-#define CLK_MOUT_ACLK_BUS0_400 22 +-#define CLK_MOUT_ACLK_MSCL_400_B 23 +-#define CLK_MOUT_ACLK_MSCL_400_A 24 +-#define CLK_MOUT_ACLK_GSCL_333 25 +-#define CLK_MOUT_ACLK_G2D_400_B 26 +-#define CLK_MOUT_ACLK_G2D_400_A 27 +-#define CLK_MOUT_SCLK_JPEG_C 28 +-#define CLK_MOUT_SCLK_JPEG_B 29 +-#define CLK_MOUT_SCLK_JPEG_A 30 +-#define CLK_MOUT_SCLK_MMC2_B 31 +-#define CLK_MOUT_SCLK_MMC2_A 32 +-#define CLK_MOUT_SCLK_MMC1_B 33 +-#define CLK_MOUT_SCLK_MMC1_A 34 +-#define CLK_MOUT_SCLK_MMC0_D 35 +-#define CLK_MOUT_SCLK_MMC0_C 36 +-#define CLK_MOUT_SCLK_MMC0_B 37 +-#define CLK_MOUT_SCLK_MMC0_A 38 +-#define CLK_MOUT_SCLK_SPI4 39 +-#define CLK_MOUT_SCLK_SPI3 40 +-#define CLK_MOUT_SCLK_UART2 41 +-#define CLK_MOUT_SCLK_UART1 42 +-#define CLK_MOUT_SCLK_UART0 43 +-#define CLK_MOUT_SCLK_SPI2 44 +-#define CLK_MOUT_SCLK_SPI1 45 +-#define CLK_MOUT_SCLK_SPI0 46 +-#define CLK_MOUT_ACLK_MFC_400_C 47 +-#define CLK_MOUT_ACLK_MFC_400_B 48 +-#define CLK_MOUT_ACLK_MFC_400_A 49 +-#define CLK_MOUT_SCLK_ISP_SENSOR2 50 +-#define CLK_MOUT_SCLK_ISP_SENSOR1 51 +-#define CLK_MOUT_SCLK_ISP_SENSOR0 52 +-#define CLK_MOUT_SCLK_ISP_UART 53 +-#define CLK_MOUT_SCLK_ISP_SPI1 54 +-#define CLK_MOUT_SCLK_ISP_SPI0 55 +-#define CLK_MOUT_SCLK_PCIE_100 56 +-#define CLK_MOUT_SCLK_UFSUNIPRO 57 +-#define CLK_MOUT_SCLK_USBHOST30 58 +-#define CLK_MOUT_SCLK_USBDRD30 59 +-#define CLK_MOUT_SCLK_SLIMBUS 60 +-#define CLK_MOUT_SCLK_SPDIF 61 +-#define CLK_MOUT_SCLK_AUDIO1 62 +-#define CLK_MOUT_SCLK_AUDIO0 63 +-#define CLK_MOUT_SCLK_HDMI_SPDIF 64 +- +-#define CLK_DIV_ACLK_FSYS_200 100 +-#define CLK_DIV_ACLK_IMEM_SSSX_266 101 +-#define CLK_DIV_ACLK_IMEM_200 102 +-#define CLK_DIV_ACLK_IMEM_266 103 +-#define CLK_DIV_ACLK_PERIC_66_B 104 +-#define CLK_DIV_ACLK_PERIC_66_A 105 +-#define CLK_DIV_ACLK_PERIS_66_B 106 +-#define CLK_DIV_ACLK_PERIS_66_A 107 +-#define CLK_DIV_SCLK_MMC1_B 108 +-#define CLK_DIV_SCLK_MMC1_A 109 +-#define CLK_DIV_SCLK_MMC0_B 110 +-#define CLK_DIV_SCLK_MMC0_A 111 +-#define CLK_DIV_SCLK_MMC2_B 112 +-#define CLK_DIV_SCLK_MMC2_A 113 +-#define CLK_DIV_SCLK_SPI1_B 114 +-#define CLK_DIV_SCLK_SPI1_A 115 +-#define CLK_DIV_SCLK_SPI0_B 116 +-#define CLK_DIV_SCLK_SPI0_A 117 +-#define CLK_DIV_SCLK_SPI2_B 118 +-#define CLK_DIV_SCLK_SPI2_A 119 +-#define CLK_DIV_SCLK_UART2 120 +-#define CLK_DIV_SCLK_UART1 121 +-#define CLK_DIV_SCLK_UART0 122 +-#define CLK_DIV_SCLK_SPI4_B 123 +-#define CLK_DIV_SCLK_SPI4_A 124 +-#define CLK_DIV_SCLK_SPI3_B 125 +-#define CLK_DIV_SCLK_SPI3_A 126 +-#define CLK_DIV_SCLK_I2S1 127 +-#define CLK_DIV_SCLK_PCM1 128 +-#define CLK_DIV_SCLK_AUDIO1 129 +-#define CLK_DIV_SCLK_AUDIO0 130 +-#define CLK_DIV_ACLK_GSCL_111 131 +-#define CLK_DIV_ACLK_GSCL_333 132 +-#define CLK_DIV_ACLK_HEVC_400 133 +-#define CLK_DIV_ACLK_MFC_400 134 +-#define CLK_DIV_ACLK_G2D_266 135 +-#define CLK_DIV_ACLK_G2D_400 136 +-#define CLK_DIV_ACLK_G3D_400 137 +-#define CLK_DIV_ACLK_BUS0_400 138 +-#define CLK_DIV_ACLK_BUS1_400 139 +-#define CLK_DIV_SCLK_PCIE_100 140 +-#define CLK_DIV_SCLK_USBHOST30 141 +-#define CLK_DIV_SCLK_UFSUNIPRO 142 +-#define CLK_DIV_SCLK_USBDRD30 143 +-#define CLK_DIV_SCLK_JPEG 144 +-#define CLK_DIV_ACLK_MSCL_400 145 +-#define CLK_DIV_ACLK_ISP_DIS_400 146 +-#define CLK_DIV_ACLK_ISP_400 147 +-#define CLK_DIV_ACLK_CAM0_333 148 +-#define CLK_DIV_ACLK_CAM0_400 149 +-#define CLK_DIV_ACLK_CAM0_552 150 +-#define CLK_DIV_ACLK_CAM1_333 151 +-#define CLK_DIV_ACLK_CAM1_400 152 +-#define CLK_DIV_ACLK_CAM1_552 153 +-#define CLK_DIV_SCLK_ISP_UART 154 +-#define CLK_DIV_SCLK_ISP_SPI1_B 155 +-#define CLK_DIV_SCLK_ISP_SPI1_A 156 +-#define CLK_DIV_SCLK_ISP_SPI0_B 157 +-#define CLK_DIV_SCLK_ISP_SPI0_A 158 +-#define CLK_DIV_SCLK_ISP_SENSOR2_B 159 +-#define CLK_DIV_SCLK_ISP_SENSOR2_A 160 +-#define CLK_DIV_SCLK_ISP_SENSOR1_B 161 +-#define CLK_DIV_SCLK_ISP_SENSOR1_A 162 +-#define CLK_DIV_SCLK_ISP_SENSOR0_B 163 +-#define CLK_DIV_SCLK_ISP_SENSOR0_A 164 +- +-#define CLK_ACLK_PERIC_66 200 +-#define CLK_ACLK_PERIS_66 201 +-#define CLK_ACLK_FSYS_200 202 +-#define CLK_SCLK_MMC2_FSYS 203 +-#define CLK_SCLK_MMC1_FSYS 204 +-#define CLK_SCLK_MMC0_FSYS 205 +-#define CLK_SCLK_SPI4_PERIC 206 +-#define CLK_SCLK_SPI3_PERIC 207 +-#define CLK_SCLK_UART2_PERIC 208 +-#define CLK_SCLK_UART1_PERIC 209 +-#define CLK_SCLK_UART0_PERIC 210 +-#define CLK_SCLK_SPI2_PERIC 211 +-#define CLK_SCLK_SPI1_PERIC 212 +-#define CLK_SCLK_SPI0_PERIC 213 +-#define CLK_SCLK_SPDIF_PERIC 214 +-#define CLK_SCLK_I2S1_PERIC 215 +-#define CLK_SCLK_PCM1_PERIC 216 +-#define CLK_SCLK_SLIMBUS 217 +-#define CLK_SCLK_AUDIO1 218 +-#define CLK_SCLK_AUDIO0 219 +-#define CLK_ACLK_G2D_266 220 +-#define CLK_ACLK_G2D_400 221 +-#define CLK_ACLK_G3D_400 222 +-#define CLK_ACLK_IMEM_SSSX_266 223 +-#define CLK_ACLK_BUS0_400 224 +-#define CLK_ACLK_BUS1_400 225 +-#define CLK_ACLK_IMEM_200 226 +-#define CLK_ACLK_IMEM_266 227 +-#define CLK_SCLK_PCIE_100_FSYS 228 +-#define CLK_SCLK_UFSUNIPRO_FSYS 229 +-#define CLK_SCLK_USBHOST30_FSYS 230 +-#define CLK_SCLK_USBDRD30_FSYS 231 +-#define CLK_ACLK_GSCL_111 232 +-#define CLK_ACLK_GSCL_333 233 +-#define CLK_SCLK_JPEG_MSCL 234 +-#define CLK_ACLK_MSCL_400 235 +-#define CLK_ACLK_MFC_400 236 +-#define CLK_ACLK_HEVC_400 237 +-#define CLK_ACLK_ISP_DIS_400 238 +-#define CLK_ACLK_ISP_400 239 +-#define CLK_ACLK_CAM0_333 240 +-#define CLK_ACLK_CAM0_400 241 +-#define CLK_ACLK_CAM0_552 242 +-#define CLK_ACLK_CAM1_333 243 +-#define CLK_ACLK_CAM1_400 244 +-#define CLK_ACLK_CAM1_552 245 +-#define CLK_SCLK_ISP_SENSOR2 246 +-#define CLK_SCLK_ISP_SENSOR1 247 +-#define CLK_SCLK_ISP_SENSOR0 248 +-#define CLK_SCLK_ISP_MCTADC_CAM1 249 +-#define CLK_SCLK_ISP_UART_CAM1 250 +-#define CLK_SCLK_ISP_SPI1_CAM1 251 +-#define CLK_SCLK_ISP_SPI0_CAM1 252 +-#define CLK_SCLK_HDMI_SPDIF_DISP 253 +- +-#define TOP_NR_CLK 254 +- +-/* CMU_CPIF */ +-#define CLK_FOUT_MPHY_PLL 1 +- +-#define CLK_MOUT_MPHY_PLL 2 +- +-#define CLK_DIV_SCLK_MPHY 10 +- +-#define CLK_SCLK_MPHY_PLL 11 +-#define CLK_SCLK_UFS_MPHY 11 +- +-#define CPIF_NR_CLK 12 +- +-/* CMU_MIF */ +-#define CLK_FOUT_MEM0_PLL 1 +-#define CLK_FOUT_MEM1_PLL 2 +-#define CLK_FOUT_BUS_PLL 3 +-#define CLK_FOUT_MFC_PLL 4 +-#define CLK_DOUT_MFC_PLL 5 +-#define CLK_DOUT_BUS_PLL 6 +-#define CLK_DOUT_MEM1_PLL 7 +-#define CLK_DOUT_MEM0_PLL 8 +- +-#define CLK_MOUT_MFC_PLL_DIV2 10 +-#define CLK_MOUT_BUS_PLL_DIV2 11 +-#define CLK_MOUT_MEM1_PLL_DIV2 12 +-#define CLK_MOUT_MEM0_PLL_DIV2 13 +-#define CLK_MOUT_MFC_PLL 14 +-#define CLK_MOUT_BUS_PLL 15 +-#define CLK_MOUT_MEM1_PLL 16 +-#define CLK_MOUT_MEM0_PLL 17 +-#define CLK_MOUT_CLK2X_PHY_C 18 +-#define CLK_MOUT_CLK2X_PHY_B 19 +-#define CLK_MOUT_CLK2X_PHY_A 20 +-#define CLK_MOUT_CLKM_PHY_C 21 +-#define CLK_MOUT_CLKM_PHY_B 22 +-#define CLK_MOUT_CLKM_PHY_A 23 +-#define CLK_MOUT_ACLK_MIFNM_200 24 +-#define CLK_MOUT_ACLK_MIFNM_400 25 +-#define CLK_MOUT_ACLK_DISP_333_B 26 +-#define CLK_MOUT_ACLK_DISP_333_A 27 +-#define CLK_MOUT_SCLK_DECON_VCLK_C 28 +-#define CLK_MOUT_SCLK_DECON_VCLK_B 29 +-#define CLK_MOUT_SCLK_DECON_VCLK_A 30 +-#define CLK_MOUT_SCLK_DECON_ECLK_C 31 +-#define CLK_MOUT_SCLK_DECON_ECLK_B 32 +-#define CLK_MOUT_SCLK_DECON_ECLK_A 33 +-#define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34 +-#define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35 +-#define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36 +-#define CLK_MOUT_SCLK_DSD_C 37 +-#define CLK_MOUT_SCLK_DSD_B 38 +-#define CLK_MOUT_SCLK_DSD_A 39 +-#define CLK_MOUT_SCLK_DSIM0_C 40 +-#define CLK_MOUT_SCLK_DSIM0_B 41 +-#define CLK_MOUT_SCLK_DSIM0_A 42 +-#define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46 +-#define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47 +-#define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48 +-#define CLK_MOUT_SCLK_DSIM1_C 49 +-#define CLK_MOUT_SCLK_DSIM1_B 50 +-#define CLK_MOUT_SCLK_DSIM1_A 51 +- +-#define CLK_DIV_SCLK_HPM_MIF 55 +-#define CLK_DIV_ACLK_DREX1 56 +-#define CLK_DIV_ACLK_DREX0 57 +-#define CLK_DIV_CLK2XPHY 58 +-#define CLK_DIV_ACLK_MIF_266 59 +-#define CLK_DIV_ACLK_MIFND_133 60 +-#define CLK_DIV_ACLK_MIF_133 61 +-#define CLK_DIV_ACLK_MIFNM_200 62 +-#define CLK_DIV_ACLK_MIF_200 63 +-#define CLK_DIV_ACLK_MIF_400 64 +-#define CLK_DIV_ACLK_BUS2_400 65 +-#define CLK_DIV_ACLK_DISP_333 66 +-#define CLK_DIV_ACLK_CPIF_200 67 +-#define CLK_DIV_SCLK_DSIM1 68 +-#define CLK_DIV_SCLK_DECON_TV_VCLK 69 +-#define CLK_DIV_SCLK_DSIM0 70 +-#define CLK_DIV_SCLK_DSD 71 +-#define CLK_DIV_SCLK_DECON_TV_ECLK 72 +-#define CLK_DIV_SCLK_DECON_VCLK 73 +-#define CLK_DIV_SCLK_DECON_ECLK 74 +-#define CLK_DIV_MIF_PRE 75 +- +-#define CLK_CLK2X_PHY1 80 +-#define CLK_CLK2X_PHY0 81 +-#define CLK_CLKM_PHY1 82 +-#define CLK_CLKM_PHY0 83 +-#define CLK_RCLK_DREX1 84 +-#define CLK_RCLK_DREX0 85 +-#define CLK_ACLK_DREX1_TZ 86 +-#define CLK_ACLK_DREX0_TZ 87 +-#define CLK_ACLK_DREX1_PEREV 88 +-#define CLK_ACLK_DREX0_PEREV 89 +-#define CLK_ACLK_DREX1_MEMIF 90 +-#define CLK_ACLK_DREX0_MEMIF 91 +-#define CLK_ACLK_DREX1_SCH 92 +-#define CLK_ACLK_DREX0_SCH 93 +-#define CLK_ACLK_DREX1_BUSIF 94 +-#define CLK_ACLK_DREX0_BUSIF 95 +-#define CLK_ACLK_DREX1_BUSIF_RD 96 +-#define CLK_ACLK_DREX0_BUSIF_RD 97 +-#define CLK_ACLK_DREX1 98 +-#define CLK_ACLK_DREX0 99 +-#define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100 +-#define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101 +-#define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102 +-#define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103 +-#define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104 +-#define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105 +-#define CLK_ACLK_ASYNCAXIS_CP1 106 +-#define CLK_ACLK_ASYNCAXIM_CP1 107 +-#define CLK_ACLK_ASYNCAXIS_CP0 108 +-#define CLK_ACLK_ASYNCAXIM_CP0 109 +-#define CLK_ACLK_ASYNCAXIS_DREX1_3 110 +-#define CLK_ACLK_ASYNCAXIM_DREX1_3 111 +-#define CLK_ACLK_ASYNCAXIS_DREX1_1 112 +-#define CLK_ACLK_ASYNCAXIM_DREX1_1 113 +-#define CLK_ACLK_ASYNCAXIS_DREX1_0 114 +-#define CLK_ACLK_ASYNCAXIM_DREX1_0 115 +-#define CLK_ACLK_ASYNCAXIS_DREX0_3 116 +-#define CLK_ACLK_ASYNCAXIM_DREX0_3 117 +-#define CLK_ACLK_ASYNCAXIS_DREX0_1 118 +-#define CLK_ACLK_ASYNCAXIM_DREX0_1 119 +-#define CLK_ACLK_ASYNCAXIS_DREX0_0 120 +-#define CLK_ACLK_ASYNCAXIM_DREX0_0 121 +-#define CLK_ACLK_AHB2APB_MIF2P 122 +-#define CLK_ACLK_AHB2APB_MIF1P 123 +-#define CLK_ACLK_AHB2APB_MIF0P 124 +-#define CLK_ACLK_IXIU_CCI 125 +-#define CLK_ACLK_XIU_MIFSFRX 126 +-#define CLK_ACLK_MIFNP_133 127 +-#define CLK_ACLK_MIFNM_200 128 +-#define CLK_ACLK_MIFND_133 129 +-#define CLK_ACLK_MIFND_400 130 +-#define CLK_ACLK_CCI 131 +-#define CLK_ACLK_MIFND_266 132 +-#define CLK_ACLK_PPMU_DREX1S3 133 +-#define CLK_ACLK_PPMU_DREX1S1 134 +-#define CLK_ACLK_PPMU_DREX1S0 135 +-#define CLK_ACLK_PPMU_DREX0S3 136 +-#define CLK_ACLK_PPMU_DREX0S1 137 +-#define CLK_ACLK_PPMU_DREX0S0 138 +-#define CLK_ACLK_BTS_APOLLO 139 +-#define CLK_ACLK_BTS_ATLAS 140 +-#define CLK_ACLK_ACE_SEL_APOLL 141 +-#define CLK_ACLK_ACE_SEL_ATLAS 142 +-#define CLK_ACLK_AXIDS_CCI_MIFSFRX 143 +-#define CLK_ACLK_AXIUS_ATLAS_CCI 144 +-#define CLK_ACLK_AXISYNCDNS_CCI 145 +-#define CLK_ACLK_AXISYNCDN_CCI 146 +-#define CLK_ACLK_AXISYNCDN_NOC_D 147 +-#define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148 +-#define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149 +-#define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150 +-#define CLK_ACLK_BUS2_400 151 +-#define CLK_ACLK_DISP_333 152 +-#define CLK_ACLK_CPIF_200 153 +-#define CLK_PCLK_PPMU_DREX1S3 154 +-#define CLK_PCLK_PPMU_DREX1S1 155 +-#define CLK_PCLK_PPMU_DREX1S0 156 +-#define CLK_PCLK_PPMU_DREX0S3 157 +-#define CLK_PCLK_PPMU_DREX0S1 158 +-#define CLK_PCLK_PPMU_DREX0S0 159 +-#define CLK_PCLK_BTS_APOLLO 160 +-#define CLK_PCLK_BTS_ATLAS 161 +-#define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162 +-#define CLK_PCLK_ASYNCAXI_CP1 163 +-#define CLK_PCLK_ASYNCAXI_CP0 164 +-#define CLK_PCLK_ASYNCAXI_DREX1_3 165 +-#define CLK_PCLK_ASYNCAXI_DREX1_1 166 +-#define CLK_PCLK_ASYNCAXI_DREX1_0 167 +-#define CLK_PCLK_ASYNCAXI_DREX0_3 168 +-#define CLK_PCLK_ASYNCAXI_DREX0_1 169 +-#define CLK_PCLK_ASYNCAXI_DREX0_0 170 +-#define CLK_PCLK_MIFSRVND_133 171 +-#define CLK_PCLK_PMU_MIF 172 +-#define CLK_PCLK_SYSREG_MIF 173 +-#define CLK_PCLK_GPIO_ALIVE 174 +-#define CLK_PCLK_ABB 175 +-#define CLK_PCLK_PMU_APBIF 176 +-#define CLK_PCLK_DDR_PHY1 177 +-#define CLK_PCLK_DREX1 178 +-#define CLK_PCLK_DDR_PHY0 179 +-#define CLK_PCLK_DREX0 180 +-#define CLK_PCLK_DREX0_TZ 181 +-#define CLK_PCLK_DREX1_TZ 182 +-#define CLK_PCLK_MONOTONIC_CNT 183 +-#define CLK_PCLK_RTC 184 +-#define CLK_SCLK_DSIM1_DISP 185 +-#define CLK_SCLK_DECON_TV_VCLK_DISP 186 +-#define CLK_SCLK_FREQ_DET_BUS_PLL 187 +-#define CLK_SCLK_FREQ_DET_MFC_PLL 188 +-#define CLK_SCLK_FREQ_DET_MEM0_PLL 189 +-#define CLK_SCLK_FREQ_DET_MEM1_PLL 190 +-#define CLK_SCLK_DSIM0_DISP 191 +-#define CLK_SCLK_DSD_DISP 192 +-#define CLK_SCLK_DECON_TV_ECLK_DISP 193 +-#define CLK_SCLK_DECON_VCLK_DISP 194 +-#define CLK_SCLK_DECON_ECLK_DISP 195 +-#define CLK_SCLK_HPM_MIF 196 +-#define CLK_SCLK_MFC_PLL 197 +-#define CLK_SCLK_BUS_PLL 198 +-#define CLK_SCLK_BUS_PLL_APOLLO 199 +-#define CLK_SCLK_BUS_PLL_ATLAS 200 +- +-#define MIF_NR_CLK 201 +- +-/* CMU_PERIC */ +-#define CLK_PCLK_SPI2 1 +-#define CLK_PCLK_SPI1 2 +-#define CLK_PCLK_SPI0 3 +-#define CLK_PCLK_UART2 4 +-#define CLK_PCLK_UART1 5 +-#define CLK_PCLK_UART0 6 +-#define CLK_PCLK_HSI2C3 7 +-#define CLK_PCLK_HSI2C2 8 +-#define CLK_PCLK_HSI2C1 9 +-#define CLK_PCLK_HSI2C0 10 +-#define CLK_PCLK_I2C7 11 +-#define CLK_PCLK_I2C6 12 +-#define CLK_PCLK_I2C5 13 +-#define CLK_PCLK_I2C4 14 +-#define CLK_PCLK_I2C3 15 +-#define CLK_PCLK_I2C2 16 +-#define CLK_PCLK_I2C1 17 +-#define CLK_PCLK_I2C0 18 +-#define CLK_PCLK_SPI4 19 +-#define CLK_PCLK_SPI3 20 +-#define CLK_PCLK_HSI2C11 21 +-#define CLK_PCLK_HSI2C10 22 +-#define CLK_PCLK_HSI2C9 23 +-#define CLK_PCLK_HSI2C8 24 +-#define CLK_PCLK_HSI2C7 25 +-#define CLK_PCLK_HSI2C6 26 +-#define CLK_PCLK_HSI2C5 27 +-#define CLK_PCLK_HSI2C4 28 +-#define CLK_SCLK_SPI4 29 +-#define CLK_SCLK_SPI3 30 +-#define CLK_SCLK_SPI2 31 +-#define CLK_SCLK_SPI1 32 +-#define CLK_SCLK_SPI0 33 +-#define CLK_SCLK_UART2 34 +-#define CLK_SCLK_UART1 35 +-#define CLK_SCLK_UART0 36 +-#define CLK_ACLK_AHB2APB_PERIC2P 37 +-#define CLK_ACLK_AHB2APB_PERIC1P 38 +-#define CLK_ACLK_AHB2APB_PERIC0P 39 +-#define CLK_ACLK_PERICNP_66 40 +-#define CLK_PCLK_SCI 41 +-#define CLK_PCLK_GPIO_FINGER 42 +-#define CLK_PCLK_GPIO_ESE 43 +-#define CLK_PCLK_PWM 44 +-#define CLK_PCLK_SPDIF 45 +-#define CLK_PCLK_PCM1 46 +-#define CLK_PCLK_I2S1 47 +-#define CLK_PCLK_ADCIF 48 +-#define CLK_PCLK_GPIO_TOUCH 49 +-#define CLK_PCLK_GPIO_NFC 50 +-#define CLK_PCLK_GPIO_PERIC 51 +-#define CLK_PCLK_PMU_PERIC 52 +-#define CLK_PCLK_SYSREG_PERIC 53 +-#define CLK_SCLK_IOCLK_SPI4 54 +-#define CLK_SCLK_IOCLK_SPI3 55 +-#define CLK_SCLK_SCI 56 +-#define CLK_SCLK_SC_IN 57 +-#define CLK_SCLK_PWM 58 +-#define CLK_SCLK_IOCLK_SPI2 59 +-#define CLK_SCLK_IOCLK_SPI1 60 +-#define CLK_SCLK_IOCLK_SPI0 61 +-#define CLK_SCLK_IOCLK_I2S1_BCLK 62 +-#define CLK_SCLK_SPDIF 63 +-#define CLK_SCLK_PCM1 64 +-#define CLK_SCLK_I2S1 65 +- +-#define CLK_DIV_SCLK_SCI 70 +-#define CLK_DIV_SCLK_SC_IN 71 +- +-#define PERIC_NR_CLK 72 +- +-/* CMU_PERIS */ +-#define CLK_PCLK_HPM_APBIF 1 +-#define CLK_PCLK_TMU1_APBIF 2 +-#define CLK_PCLK_TMU0_APBIF 3 +-#define CLK_PCLK_PMU_PERIS 4 +-#define CLK_PCLK_SYSREG_PERIS 5 +-#define CLK_PCLK_CMU_TOP_APBIF 6 +-#define CLK_PCLK_WDT_APOLLO 7 +-#define CLK_PCLK_WDT_ATLAS 8 +-#define CLK_PCLK_MCT 9 +-#define CLK_PCLK_HDMI_CEC 10 +-#define CLK_ACLK_AHB2APB_PERIS1P 11 +-#define CLK_ACLK_AHB2APB_PERIS0P 12 +-#define CLK_ACLK_PERISNP_66 13 +-#define CLK_PCLK_TZPC12 14 +-#define CLK_PCLK_TZPC11 15 +-#define CLK_PCLK_TZPC10 16 +-#define CLK_PCLK_TZPC9 17 +-#define CLK_PCLK_TZPC8 18 +-#define CLK_PCLK_TZPC7 19 +-#define CLK_PCLK_TZPC6 20 +-#define CLK_PCLK_TZPC5 21 +-#define CLK_PCLK_TZPC4 22 +-#define CLK_PCLK_TZPC3 23 +-#define CLK_PCLK_TZPC2 24 +-#define CLK_PCLK_TZPC1 25 +-#define CLK_PCLK_TZPC0 26 +-#define CLK_PCLK_SECKEY_APBIF 27 +-#define CLK_PCLK_CHIPID_APBIF 28 +-#define CLK_PCLK_TOPRTC 29 +-#define CLK_PCLK_CUSTOM_EFUSE_APBIF 30 +-#define CLK_PCLK_ANTIRBK_CNT_APBIF 31 +-#define CLK_PCLK_OTP_CON_APBIF 32 +-#define CLK_SCLK_ASV_TB 33 +-#define CLK_SCLK_TMU1 34 +-#define CLK_SCLK_TMU0 35 +-#define CLK_SCLK_SECKEY 36 +-#define CLK_SCLK_CHIPID 37 +-#define CLK_SCLK_TOPRTC 38 +-#define CLK_SCLK_CUSTOM_EFUSE 39 +-#define CLK_SCLK_ANTIRBK_CNT 40 +-#define CLK_SCLK_OTP_CON 41 +- +-#define PERIS_NR_CLK 42 +- +-/* CMU_FSYS */ +-#define CLK_MOUT_ACLK_FSYS_200_USER 1 +-#define CLK_MOUT_SCLK_MMC2_USER 2 +-#define CLK_MOUT_SCLK_MMC1_USER 3 +-#define CLK_MOUT_SCLK_MMC0_USER 4 +-#define CLK_MOUT_SCLK_UFS_MPHY_USER 5 +-#define CLK_MOUT_SCLK_PCIE_100_USER 6 +-#define CLK_MOUT_SCLK_UFSUNIPRO_USER 7 +-#define CLK_MOUT_SCLK_USBHOST30_USER 8 +-#define CLK_MOUT_SCLK_USBDRD30_USER 9 +-#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10 +-#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11 +-#define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12 +-#define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13 +-#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14 +-#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15 +-#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16 +-#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17 +-#define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18 +-#define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19 +-#define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20 +-#define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21 +-#define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22 +-#define CLK_MOUT_SCLK_MPHY 23 +- +-#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25 +-#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY 26 +-#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY 27 +-#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY 28 +-#define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY 29 +-#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30 +-#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY 31 +-#define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32 +-#define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY 33 +-#define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY 34 +-#define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35 +-#define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36 +-#define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY 37 +- +-#define CLK_ACLK_PCIE 50 +-#define CLK_ACLK_PDMA1 51 +-#define CLK_ACLK_TSI 52 +-#define CLK_ACLK_MMC2 53 +-#define CLK_ACLK_MMC1 54 +-#define CLK_ACLK_MMC0 55 +-#define CLK_ACLK_UFS 56 +-#define CLK_ACLK_USBHOST20 57 +-#define CLK_ACLK_USBHOST30 58 +-#define CLK_ACLK_USBDRD30 59 +-#define CLK_ACLK_PDMA0 60 +-#define CLK_SCLK_MMC2 61 +-#define CLK_SCLK_MMC1 62 +-#define CLK_SCLK_MMC0 63 +-#define CLK_PDMA1 64 +-#define CLK_PDMA0 65 +-#define CLK_ACLK_XIU_FSYSPX 66 +-#define CLK_ACLK_AHB_USBLINKH1 67 +-#define CLK_ACLK_SMMU_PDMA1 68 +-#define CLK_ACLK_BTS_PCIE 69 +-#define CLK_ACLK_AXIUS_PDMA1 70 +-#define CLK_ACLK_SMMU_PDMA0 71 +-#define CLK_ACLK_BTS_UFS 72 +-#define CLK_ACLK_BTS_USBHOST30 73 +-#define CLK_ACLK_BTS_USBDRD30 74 +-#define CLK_ACLK_AXIUS_PDMA0 75 +-#define CLK_ACLK_AXIUS_USBHS 76 +-#define CLK_ACLK_AXIUS_FSYSSX 77 +-#define CLK_ACLK_AHB2APB_FSYSP 78 +-#define CLK_ACLK_AHB2AXI_USBHS 79 +-#define CLK_ACLK_AHB_USBLINKH0 80 +-#define CLK_ACLK_AHB_USBHS 81 +-#define CLK_ACLK_AHB_FSYSH 82 +-#define CLK_ACLK_XIU_FSYSX 83 +-#define CLK_ACLK_XIU_FSYSSX 84 +-#define CLK_ACLK_FSYSNP_200 85 +-#define CLK_ACLK_FSYSND_200 86 +-#define CLK_PCLK_PCIE_CTRL 87 +-#define CLK_PCLK_SMMU_PDMA1 88 +-#define CLK_PCLK_PCIE_PHY 89 +-#define CLK_PCLK_BTS_PCIE 90 +-#define CLK_PCLK_SMMU_PDMA0 91 +-#define CLK_PCLK_BTS_UFS 92 +-#define CLK_PCLK_BTS_USBHOST30 93 +-#define CLK_PCLK_BTS_USBDRD30 94 +-#define CLK_PCLK_GPIO_FSYS 95 +-#define CLK_PCLK_PMU_FSYS 96 +-#define CLK_PCLK_SYSREG_FSYS 97 +-#define CLK_SCLK_PCIE_100 98 +-#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99 +-#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100 +-#define CLK_PHYCLK_UFS_RX1_SYMBOL 101 +-#define CLK_PHYCLK_UFS_RX0_SYMBOL 102 +-#define CLK_PHYCLK_UFS_TX1_SYMBOL 103 +-#define CLK_PHYCLK_UFS_TX0_SYMBOL 104 +-#define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105 +-#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106 +-#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107 +-#define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108 +-#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109 +-#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110 +-#define CLK_SCLK_MPHY 111 +-#define CLK_SCLK_UFSUNIPRO 112 +-#define CLK_SCLK_USBHOST30 113 +-#define CLK_SCLK_USBDRD30 114 +-#define CLK_PCIE 115 +- +-#define FSYS_NR_CLK 116 +- +-/* CMU_G2D */ +-#define CLK_MUX_ACLK_G2D_266_USER 1 +-#define CLK_MUX_ACLK_G2D_400_USER 2 +- +-#define CLK_DIV_PCLK_G2D 3 +- +-#define CLK_ACLK_SMMU_MDMA1 4 +-#define CLK_ACLK_BTS_MDMA1 5 +-#define CLK_ACLK_BTS_G2D 6 +-#define CLK_ACLK_ALB_G2D 7 +-#define CLK_ACLK_AXIUS_G2DX 8 +-#define CLK_ACLK_ASYNCAXI_SYSX 9 +-#define CLK_ACLK_AHB2APB_G2D1P 10 +-#define CLK_ACLK_AHB2APB_G2D0P 11 +-#define CLK_ACLK_XIU_G2DX 12 +-#define CLK_ACLK_G2DNP_133 13 +-#define CLK_ACLK_G2DND_400 14 +-#define CLK_ACLK_MDMA1 15 +-#define CLK_ACLK_G2D 16 +-#define CLK_ACLK_SMMU_G2D 17 +-#define CLK_PCLK_SMMU_MDMA1 18 +-#define CLK_PCLK_BTS_MDMA1 19 +-#define CLK_PCLK_BTS_G2D 20 +-#define CLK_PCLK_ALB_G2D 21 +-#define CLK_PCLK_ASYNCAXI_SYSX 22 +-#define CLK_PCLK_PMU_G2D 23 +-#define CLK_PCLK_SYSREG_G2D 24 +-#define CLK_PCLK_G2D 25 +-#define CLK_PCLK_SMMU_G2D 26 +- +-#define G2D_NR_CLK 27 +- +-/* CMU_DISP */ +-#define CLK_FOUT_DISP_PLL 1 +- +-#define CLK_MOUT_DISP_PLL 2 +-#define CLK_MOUT_SCLK_DSIM1_USER 3 +-#define CLK_MOUT_SCLK_DSIM0_USER 4 +-#define CLK_MOUT_SCLK_DSD_USER 5 +-#define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6 +-#define CLK_MOUT_SCLK_DECON_VCLK_USER 7 +-#define CLK_MOUT_SCLK_DECON_ECLK_USER 8 +-#define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9 +-#define CLK_MOUT_ACLK_DISP_333_USER 10 +-#define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11 +-#define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12 +-#define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13 +-#define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14 +-#define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15 +-#define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16 +-#define CLK_MOUT_SCLK_DSIM0 17 +-#define CLK_MOUT_SCLK_DECON_TV_ECLK 18 +-#define CLK_MOUT_SCLK_DECON_VCLK 19 +-#define CLK_MOUT_SCLK_DECON_ECLK 20 +-#define CLK_MOUT_SCLK_DSIM1_B_DISP 21 +-#define CLK_MOUT_SCLK_DSIM1_A_DISP 22 +-#define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23 +-#define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24 +-#define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25 +- +-#define CLK_DIV_SCLK_DSIM1_DISP 30 +-#define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31 +-#define CLK_DIV_SCLK_DSIM0_DISP 32 +-#define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33 +-#define CLK_DIV_SCLK_DECON_VCLK_DISP 34 +-#define CLK_DIV_SCLK_DECON_ECLK_DISP 35 +-#define CLK_DIV_PCLK_DISP 36 +- +-#define CLK_ACLK_DECON_TV 40 +-#define CLK_ACLK_DECON 41 +-#define CLK_ACLK_SMMU_TV1X 42 +-#define CLK_ACLK_SMMU_TV0X 43 +-#define CLK_ACLK_SMMU_DECON1X 44 +-#define CLK_ACLK_SMMU_DECON0X 45 +-#define CLK_ACLK_BTS_DECON_TV_M3 46 +-#define CLK_ACLK_BTS_DECON_TV_M2 47 +-#define CLK_ACLK_BTS_DECON_TV_M1 48 +-#define CLK_ACLK_BTS_DECON_TV_M0 49 +-#define CLK_ACLK_BTS_DECON_NM4 50 +-#define CLK_ACLK_BTS_DECON_NM3 51 +-#define CLK_ACLK_BTS_DECON_NM2 52 +-#define CLK_ACLK_BTS_DECON_NM1 53 +-#define CLK_ACLK_BTS_DECON_NM0 54 +-#define CLK_ACLK_AHB2APB_DISPSFR2P 55 +-#define CLK_ACLK_AHB2APB_DISPSFR1P 56 +-#define CLK_ACLK_AHB2APB_DISPSFR0P 57 +-#define CLK_ACLK_AHB_DISPH 58 +-#define CLK_ACLK_XIU_TV1X 59 +-#define CLK_ACLK_XIU_TV0X 60 +-#define CLK_ACLK_XIU_DECON1X 61 +-#define CLK_ACLK_XIU_DECON0X 62 +-#define CLK_ACLK_XIU_DISP1X 63 +-#define CLK_ACLK_XIU_DISPNP_100 64 +-#define CLK_ACLK_DISP1ND_333 65 +-#define CLK_ACLK_DISP0ND_333 66 +-#define CLK_PCLK_SMMU_TV1X 67 +-#define CLK_PCLK_SMMU_TV0X 68 +-#define CLK_PCLK_SMMU_DECON1X 69 +-#define CLK_PCLK_SMMU_DECON0X 70 +-#define CLK_PCLK_BTS_DECON_TV_M3 71 +-#define CLK_PCLK_BTS_DECON_TV_M2 72 +-#define CLK_PCLK_BTS_DECON_TV_M1 73 +-#define CLK_PCLK_BTS_DECON_TV_M0 74 +-#define CLK_PCLK_BTS_DECONM4 75 +-#define CLK_PCLK_BTS_DECONM3 76 +-#define CLK_PCLK_BTS_DECONM2 77 +-#define CLK_PCLK_BTS_DECONM1 78 +-#define CLK_PCLK_BTS_DECONM0 79 +-#define CLK_PCLK_MIC1 80 +-#define CLK_PCLK_PMU_DISP 81 +-#define CLK_PCLK_SYSREG_DISP 82 +-#define CLK_PCLK_HDMIPHY 83 +-#define CLK_PCLK_HDMI 84 +-#define CLK_PCLK_MIC0 85 +-#define CLK_PCLK_DSIM1 86 +-#define CLK_PCLK_DSIM0 87 +-#define CLK_PCLK_DECON_TV 88 +-#define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89 +-#define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90 +-#define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91 +-#define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92 +-#define CLK_SCLK_DSIM1 93 +-#define CLK_SCLK_DECON_TV_VCLK 94 +-#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95 +-#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96 +-#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97 +-#define CLK_PHYCLK_HDMI_PIXEL 98 +-#define CLK_SCLK_RGB_VCLK_TO_SMIES 99 +-#define CLK_SCLK_FREQ_DET_DISP_PLL 100 +-#define CLK_SCLK_RGB_VCLK_TO_DSIM0 101 +-#define CLK_SCLK_RGB_VCLK_TO_MIC0 102 +-#define CLK_SCLK_DSD 103 +-#define CLK_SCLK_HDMI_SPDIF 104 +-#define CLK_SCLK_DSIM0 105 +-#define CLK_SCLK_DECON_TV_ECLK 106 +-#define CLK_SCLK_DECON_VCLK 107 +-#define CLK_SCLK_DECON_ECLK 108 +-#define CLK_SCLK_RGB_VCLK 109 +-#define CLK_SCLK_RGB_TV_VCLK 110 +- +-#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY 111 +-#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY 112 +- +-#define CLK_PCLK_DECON 113 +- +-#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114 +-#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115 +- +-#define DISP_NR_CLK 116 +- +-/* CMU_AUD */ +-#define CLK_MOUT_AUD_PLL_USER 1 +-#define CLK_MOUT_SCLK_AUD_PCM 2 +-#define CLK_MOUT_SCLK_AUD_I2S 3 +- +-#define CLK_DIV_ATCLK_AUD 4 +-#define CLK_DIV_PCLK_DBG_AUD 5 +-#define CLK_DIV_ACLK_AUD 6 +-#define CLK_DIV_AUD_CA5 7 +-#define CLK_DIV_SCLK_AUD_SLIMBUS 8 +-#define CLK_DIV_SCLK_AUD_UART 9 +-#define CLK_DIV_SCLK_AUD_PCM 10 +-#define CLK_DIV_SCLK_AUD_I2S 11 +- +-#define CLK_ACLK_INTR_CTRL 12 +-#define CLK_ACLK_AXIDS2_LPASSP 13 +-#define CLK_ACLK_AXIDS1_LPASSP 14 +-#define CLK_ACLK_AXI2APB1_LPASSP 15 +-#define CLK_ACLK_AXI2APH_LPASSP 16 +-#define CLK_ACLK_SMMU_LPASSX 17 +-#define CLK_ACLK_AXIDS0_LPASSP 18 +-#define CLK_ACLK_AXI2APB0_LPASSP 19 +-#define CLK_ACLK_XIU_LPASSX 20 +-#define CLK_ACLK_AUDNP_133 21 +-#define CLK_ACLK_AUDND_133 22 +-#define CLK_ACLK_SRAMC 23 +-#define CLK_ACLK_DMAC 24 +-#define CLK_PCLK_WDT1 25 +-#define CLK_PCLK_WDT0 26 +-#define CLK_PCLK_SFR1 27 +-#define CLK_PCLK_SMMU_LPASSX 28 +-#define CLK_PCLK_GPIO_AUD 29 +-#define CLK_PCLK_PMU_AUD 30 +-#define CLK_PCLK_SYSREG_AUD 31 +-#define CLK_PCLK_AUD_SLIMBUS 32 +-#define CLK_PCLK_AUD_UART 33 +-#define CLK_PCLK_AUD_PCM 34 +-#define CLK_PCLK_AUD_I2S 35 +-#define CLK_PCLK_TIMER 36 +-#define CLK_PCLK_SFR0_CTRL 37 +-#define CLK_ATCLK_AUD 38 +-#define CLK_PCLK_DBG_AUD 39 +-#define CLK_SCLK_AUD_CA5 40 +-#define CLK_SCLK_JTAG_TCK 41 +-#define CLK_SCLK_SLIMBUS_CLKIN 42 +-#define CLK_SCLK_AUD_SLIMBUS 43 +-#define CLK_SCLK_AUD_UART 44 +-#define CLK_SCLK_AUD_PCM 45 +-#define CLK_SCLK_I2S_BCLK 46 +-#define CLK_SCLK_AUD_I2S 47 +- +-#define AUD_NR_CLK 48 +- +-/* CMU_BUS{0|1|2} */ +-#define CLK_DIV_PCLK_BUS_133 1 +- +-#define CLK_ACLK_AHB2APB_BUSP 2 +-#define CLK_ACLK_BUSNP_133 3 +-#define CLK_ACLK_BUSND_400 4 +-#define CLK_PCLK_BUSSRVND_133 5 +-#define CLK_PCLK_PMU_BUS 6 +-#define CLK_PCLK_SYSREG_BUS 7 +- +-#define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */ +-#define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */ +-#define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */ +- +-#define BUSx_NR_CLK 11 +- +-/* CMU_G3D */ +-#define CLK_FOUT_G3D_PLL 1 +- +-#define CLK_MOUT_ACLK_G3D_400 2 +-#define CLK_MOUT_G3D_PLL 3 +- +-#define CLK_DIV_SCLK_HPM_G3D 4 +-#define CLK_DIV_PCLK_G3D 5 +-#define CLK_DIV_ACLK_G3D 6 +-#define CLK_ACLK_BTS_G3D1 7 +-#define CLK_ACLK_BTS_G3D0 8 +-#define CLK_ACLK_ASYNCAPBS_G3D 9 +-#define CLK_ACLK_ASYNCAPBM_G3D 10 +-#define CLK_ACLK_AHB2APB_G3DP 11 +-#define CLK_ACLK_G3DNP_150 12 +-#define CLK_ACLK_G3DND_600 13 +-#define CLK_ACLK_G3D 14 +-#define CLK_PCLK_BTS_G3D1 15 +-#define CLK_PCLK_BTS_G3D0 16 +-#define CLK_PCLK_PMU_G3D 17 +-#define CLK_PCLK_SYSREG_G3D 18 +-#define CLK_SCLK_HPM_G3D 19 +- +-#define G3D_NR_CLK 20 +- +-/* CMU_GSCL */ +-#define CLK_MOUT_ACLK_GSCL_111_USER 1 +-#define CLK_MOUT_ACLK_GSCL_333_USER 2 +- +-#define CLK_ACLK_BTS_GSCL2 3 +-#define CLK_ACLK_BTS_GSCL1 4 +-#define CLK_ACLK_BTS_GSCL0 5 +-#define CLK_ACLK_AHB2APB_GSCLP 6 +-#define CLK_ACLK_XIU_GSCLX 7 +-#define CLK_ACLK_GSCLNP_111 8 +-#define CLK_ACLK_GSCLRTND_333 9 +-#define CLK_ACLK_GSCLBEND_333 10 +-#define CLK_ACLK_GSD 11 +-#define CLK_ACLK_GSCL2 12 +-#define CLK_ACLK_GSCL1 13 +-#define CLK_ACLK_GSCL0 14 +-#define CLK_ACLK_SMMU_GSCL0 15 +-#define CLK_ACLK_SMMU_GSCL1 16 +-#define CLK_ACLK_SMMU_GSCL2 17 +-#define CLK_PCLK_BTS_GSCL2 18 +-#define CLK_PCLK_BTS_GSCL1 19 +-#define CLK_PCLK_BTS_GSCL0 20 +-#define CLK_PCLK_PMU_GSCL 21 +-#define CLK_PCLK_SYSREG_GSCL 22 +-#define CLK_PCLK_GSCL2 23 +-#define CLK_PCLK_GSCL1 24 +-#define CLK_PCLK_GSCL0 25 +-#define CLK_PCLK_SMMU_GSCL0 26 +-#define CLK_PCLK_SMMU_GSCL1 27 +-#define CLK_PCLK_SMMU_GSCL2 28 +- +-#define GSCL_NR_CLK 29 +- +-/* CMU_APOLLO */ +-#define CLK_FOUT_APOLLO_PLL 1 +- +-#define CLK_MOUT_APOLLO_PLL 2 +-#define CLK_MOUT_BUS_PLL_APOLLO_USER 3 +-#define CLK_MOUT_APOLLO 4 +- +-#define CLK_DIV_CNTCLK_APOLLO 5 +-#define CLK_DIV_PCLK_DBG_APOLLO 6 +-#define CLK_DIV_ATCLK_APOLLO 7 +-#define CLK_DIV_PCLK_APOLLO 8 +-#define CLK_DIV_ACLK_APOLLO 9 +-#define CLK_DIV_APOLLO2 10 +-#define CLK_DIV_APOLLO1 11 +-#define CLK_DIV_SCLK_HPM_APOLLO 12 +-#define CLK_DIV_APOLLO_PLL 13 +- +-#define CLK_ACLK_ATBDS_APOLLO_3 14 +-#define CLK_ACLK_ATBDS_APOLLO_2 15 +-#define CLK_ACLK_ATBDS_APOLLO_1 16 +-#define CLK_ACLK_ATBDS_APOLLO_0 17 +-#define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18 +-#define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS 19 +-#define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS 20 +-#define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS 21 +-#define CLK_ACLK_ASYNCACES_APOLLO_CCI 22 +-#define CLK_ACLK_AHB2APB_APOLLOP 23 +-#define CLK_ACLK_APOLLONP_200 24 +-#define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25 +-#define CLK_PCLK_PMU_APOLLO 26 +-#define CLK_PCLK_SYSREG_APOLLO 27 +-#define CLK_CNTCLK_APOLLO 28 +-#define CLK_SCLK_HPM_APOLLO 29 +-#define CLK_SCLK_APOLLO 30 +- +-#define APOLLO_NR_CLK 31 +- +-/* CMU_ATLAS */ +-#define CLK_FOUT_ATLAS_PLL 1 +- +-#define CLK_MOUT_ATLAS_PLL 2 +-#define CLK_MOUT_BUS_PLL_ATLAS_USER 3 +-#define CLK_MOUT_ATLAS 4 +- +-#define CLK_DIV_CNTCLK_ATLAS 5 +-#define CLK_DIV_PCLK_DBG_ATLAS 6 +-#define CLK_DIV_ATCLK_ATLASO 7 +-#define CLK_DIV_PCLK_ATLAS 8 +-#define CLK_DIV_ACLK_ATLAS 9 +-#define CLK_DIV_ATLAS2 10 +-#define CLK_DIV_ATLAS1 11 +-#define CLK_DIV_SCLK_HPM_ATLAS 12 +-#define CLK_DIV_ATLAS_PLL 13 +- +-#define CLK_ACLK_ATB_AUD_CSSYS 14 +-#define CLK_ACLK_ATB_APOLLO3_CSSYS 15 +-#define CLK_ACLK_ATB_APOLLO2_CSSYS 16 +-#define CLK_ACLK_ATB_APOLLO1_CSSYS 17 +-#define CLK_ACLK_ATB_APOLLO0_CSSYS 18 +-#define CLK_ACLK_ASYNCAHBS_CSSYS_SSS 19 +-#define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX 20 +-#define CLK_ACLK_ASYNCACES_ATLAS_CCI 21 +-#define CLK_ACLK_AHB2APB_ATLASP 22 +-#define CLK_ACLK_ATLASNP_200 23 +-#define CLK_PCLK_ASYNCAPB_AUD_CSSYS 24 +-#define CLK_PCLK_ASYNCAPB_ISP_CSSYS 25 +-#define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS 26 +-#define CLK_PCLK_PMU_ATLAS 27 +-#define CLK_PCLK_SYSREG_ATLAS 28 +-#define CLK_PCLK_SECJTAG 29 +-#define CLK_CNTCLK_ATLAS 30 +-#define CLK_SCLK_FREQ_DET_ATLAS_PLL 31 +-#define CLK_SCLK_HPM_ATLAS 32 +-#define CLK_TRACECLK 33 +-#define CLK_CTMCLK 34 +-#define CLK_HCLK_CSSYS 35 +-#define CLK_PCLK_DBG_CSSYS 36 +-#define CLK_PCLK_DBG 37 +-#define CLK_ATCLK 38 +-#define CLK_SCLK_ATLAS 39 +- +-#define ATLAS_NR_CLK 40 +- +-/* CMU_MSCL */ +-#define CLK_MOUT_SCLK_JPEG_USER 1 +-#define CLK_MOUT_ACLK_MSCL_400_USER 2 +-#define CLK_MOUT_SCLK_JPEG 3 +- +-#define CLK_DIV_PCLK_MSCL 4 +- +-#define CLK_ACLK_BTS_JPEG 5 +-#define CLK_ACLK_BTS_M2MSCALER1 6 +-#define CLK_ACLK_BTS_M2MSCALER0 7 +-#define CLK_ACLK_AHB2APB_MSCL0P 8 +-#define CLK_ACLK_XIU_MSCLX 9 +-#define CLK_ACLK_MSCLNP_100 10 +-#define CLK_ACLK_MSCLND_400 11 +-#define CLK_ACLK_JPEG 12 +-#define CLK_ACLK_M2MSCALER1 13 +-#define CLK_ACLK_M2MSCALER0 14 +-#define CLK_ACLK_SMMU_M2MSCALER0 15 +-#define CLK_ACLK_SMMU_M2MSCALER1 16 +-#define CLK_ACLK_SMMU_JPEG 17 +-#define CLK_PCLK_BTS_JPEG 18 +-#define CLK_PCLK_BTS_M2MSCALER1 19 +-#define CLK_PCLK_BTS_M2MSCALER0 20 +-#define CLK_PCLK_PMU_MSCL 21 +-#define CLK_PCLK_SYSREG_MSCL 22 +-#define CLK_PCLK_JPEG 23 +-#define CLK_PCLK_M2MSCALER1 24 +-#define CLK_PCLK_M2MSCALER0 25 +-#define CLK_PCLK_SMMU_M2MSCALER0 26 +-#define CLK_PCLK_SMMU_M2MSCALER1 27 +-#define CLK_PCLK_SMMU_JPEG 28 +-#define CLK_SCLK_JPEG 29 +- +-#define MSCL_NR_CLK 30 +- +-/* CMU_MFC */ +-#define CLK_MOUT_ACLK_MFC_400_USER 1 +- +-#define CLK_DIV_PCLK_MFC 2 +- +-#define CLK_ACLK_BTS_MFC_1 3 +-#define CLK_ACLK_BTS_MFC_0 4 +-#define CLK_ACLK_AHB2APB_MFCP 5 +-#define CLK_ACLK_XIU_MFCX 6 +-#define CLK_ACLK_MFCNP_100 7 +-#define CLK_ACLK_MFCND_400 8 +-#define CLK_ACLK_MFC 9 +-#define CLK_ACLK_SMMU_MFC_1 10 +-#define CLK_ACLK_SMMU_MFC_0 11 +-#define CLK_PCLK_BTS_MFC_1 12 +-#define CLK_PCLK_BTS_MFC_0 13 +-#define CLK_PCLK_PMU_MFC 14 +-#define CLK_PCLK_SYSREG_MFC 15 +-#define CLK_PCLK_MFC 16 +-#define CLK_PCLK_SMMU_MFC_1 17 +-#define CLK_PCLK_SMMU_MFC_0 18 +- +-#define MFC_NR_CLK 19 +- +-/* CMU_HEVC */ +-#define CLK_MOUT_ACLK_HEVC_400_USER 1 +- +-#define CLK_DIV_PCLK_HEVC 2 +- +-#define CLK_ACLK_BTS_HEVC_1 3 +-#define CLK_ACLK_BTS_HEVC_0 4 +-#define CLK_ACLK_AHB2APB_HEVCP 5 +-#define CLK_ACLK_XIU_HEVCX 6 +-#define CLK_ACLK_HEVCNP_100 7 +-#define CLK_ACLK_HEVCND_400 8 +-#define CLK_ACLK_HEVC 9 +-#define CLK_ACLK_SMMU_HEVC_1 10 +-#define CLK_ACLK_SMMU_HEVC_0 11 +-#define CLK_PCLK_BTS_HEVC_1 12 +-#define CLK_PCLK_BTS_HEVC_0 13 +-#define CLK_PCLK_PMU_HEVC 14 +-#define CLK_PCLK_SYSREG_HEVC 15 +-#define CLK_PCLK_HEVC 16 +-#define CLK_PCLK_SMMU_HEVC_1 17 +-#define CLK_PCLK_SMMU_HEVC_0 18 +- +-#define HEVC_NR_CLK 19 +- +-/* CMU_ISP */ +-#define CLK_MOUT_ACLK_ISP_DIS_400_USER 1 +-#define CLK_MOUT_ACLK_ISP_400_USER 2 +- +-#define CLK_DIV_PCLK_ISP_DIS 3 +-#define CLK_DIV_PCLK_ISP 4 +-#define CLK_DIV_ACLK_ISP_D_200 5 +-#define CLK_DIV_ACLK_ISP_C_200 6 +- +-#define CLK_ACLK_ISP_D_GLUE 7 +-#define CLK_ACLK_SCALERP 8 +-#define CLK_ACLK_3DNR 9 +-#define CLK_ACLK_DIS 10 +-#define CLK_ACLK_SCALERC 11 +-#define CLK_ACLK_DRC 12 +-#define CLK_ACLK_ISP 13 +-#define CLK_ACLK_AXIUS_SCALERP 14 +-#define CLK_ACLK_AXIUS_SCALERC 15 +-#define CLK_ACLK_AXIUS_DRC 16 +-#define CLK_ACLK_ASYNCAHBM_ISP2P 17 +-#define CLK_ACLK_ASYNCAHBM_ISP1P 18 +-#define CLK_ACLK_ASYNCAXIS_DIS1 19 +-#define CLK_ACLK_ASYNCAXIS_DIS0 20 +-#define CLK_ACLK_ASYNCAXIM_DIS1 21 +-#define CLK_ACLK_ASYNCAXIM_DIS0 22 +-#define CLK_ACLK_ASYNCAXIM_ISP2P 23 +-#define CLK_ACLK_ASYNCAXIM_ISP1P 24 +-#define CLK_ACLK_AHB2APB_ISP2P 25 +-#define CLK_ACLK_AHB2APB_ISP1P 26 +-#define CLK_ACLK_AXI2APB_ISP2P 27 +-#define CLK_ACLK_AXI2APB_ISP1P 28 +-#define CLK_ACLK_XIU_ISPEX1 29 +-#define CLK_ACLK_XIU_ISPEX0 30 +-#define CLK_ACLK_ISPND_400 31 +-#define CLK_ACLK_SMMU_SCALERP 32 +-#define CLK_ACLK_SMMU_3DNR 33 +-#define CLK_ACLK_SMMU_DIS1 34 +-#define CLK_ACLK_SMMU_DIS0 35 +-#define CLK_ACLK_SMMU_SCALERC 36 +-#define CLK_ACLK_SMMU_DRC 37 +-#define CLK_ACLK_SMMU_ISP 38 +-#define CLK_ACLK_BTS_SCALERP 39 +-#define CLK_ACLK_BTS_3DR 40 +-#define CLK_ACLK_BTS_DIS1 41 +-#define CLK_ACLK_BTS_DIS0 42 +-#define CLK_ACLK_BTS_SCALERC 43 +-#define CLK_ACLK_BTS_DRC 44 +-#define CLK_ACLK_BTS_ISP 45 +-#define CLK_PCLK_SMMU_SCALERP 46 +-#define CLK_PCLK_SMMU_3DNR 47 +-#define CLK_PCLK_SMMU_DIS1 48 +-#define CLK_PCLK_SMMU_DIS0 49 +-#define CLK_PCLK_SMMU_SCALERC 50 +-#define CLK_PCLK_SMMU_DRC 51 +-#define CLK_PCLK_SMMU_ISP 52 +-#define CLK_PCLK_BTS_SCALERP 53 +-#define CLK_PCLK_BTS_3DNR 54 +-#define CLK_PCLK_BTS_DIS1 55 +-#define CLK_PCLK_BTS_DIS0 56 +-#define CLK_PCLK_BTS_SCALERC 57 +-#define CLK_PCLK_BTS_DRC 58 +-#define CLK_PCLK_BTS_ISP 59 +-#define CLK_PCLK_ASYNCAXI_DIS1 60 +-#define CLK_PCLK_ASYNCAXI_DIS0 61 +-#define CLK_PCLK_PMU_ISP 62 +-#define CLK_PCLK_SYSREG_ISP 63 +-#define CLK_PCLK_CMU_ISP_LOCAL 64 +-#define CLK_PCLK_SCALERP 65 +-#define CLK_PCLK_3DNR 66 +-#define CLK_PCLK_DIS_CORE 67 +-#define CLK_PCLK_DIS 68 +-#define CLK_PCLK_SCALERC 69 +-#define CLK_PCLK_DRC 70 +-#define CLK_PCLK_ISP 71 +-#define CLK_SCLK_PIXELASYNCS_DIS 72 +-#define CLK_SCLK_PIXELASYNCM_DIS 73 +-#define CLK_SCLK_PIXELASYNCS_SCALERP 74 +-#define CLK_SCLK_PIXELASYNCM_ISPD 75 +-#define CLK_SCLK_PIXELASYNCS_ISPC 76 +-#define CLK_SCLK_PIXELASYNCM_ISPC 77 +- +-#define ISP_NR_CLK 78 +- +-/* CMU_CAM0 */ +-#define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY 1 +-#define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY 2 +- +-#define CLK_MOUT_ACLK_CAM0_333_USER 3 +-#define CLK_MOUT_ACLK_CAM0_400_USER 4 +-#define CLK_MOUT_ACLK_CAM0_552_USER 5 +-#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER 6 +-#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER 7 +-#define CLK_MOUT_ACLK_LITE_D_B 8 +-#define CLK_MOUT_ACLK_LITE_D_A 9 +-#define CLK_MOUT_ACLK_LITE_B_B 10 +-#define CLK_MOUT_ACLK_LITE_B_A 11 +-#define CLK_MOUT_ACLK_LITE_A_B 12 +-#define CLK_MOUT_ACLK_LITE_A_A 13 +-#define CLK_MOUT_ACLK_CAM0_400 14 +-#define CLK_MOUT_ACLK_CSIS1_B 15 +-#define CLK_MOUT_ACLK_CSIS1_A 16 +-#define CLK_MOUT_ACLK_CSIS0_B 17 +-#define CLK_MOUT_ACLK_CSIS0_A 18 +-#define CLK_MOUT_ACLK_3AA1_B 19 +-#define CLK_MOUT_ACLK_3AA1_A 20 +-#define CLK_MOUT_ACLK_3AA0_B 21 +-#define CLK_MOUT_ACLK_3AA0_A 22 +-#define CLK_MOUT_SCLK_LITE_FREECNT_C 23 +-#define CLK_MOUT_SCLK_LITE_FREECNT_B 24 +-#define CLK_MOUT_SCLK_LITE_FREECNT_A 25 +-#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B 26 +-#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A 27 +-#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B 28 +-#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A 29 +- +-#define CLK_DIV_PCLK_CAM0_50 30 +-#define CLK_DIV_ACLK_CAM0_200 31 +-#define CLK_DIV_ACLK_CAM0_BUS_400 32 +-#define CLK_DIV_PCLK_LITE_D 33 +-#define CLK_DIV_ACLK_LITE_D 34 +-#define CLK_DIV_PCLK_LITE_B 35 +-#define CLK_DIV_ACLK_LITE_B 36 +-#define CLK_DIV_PCLK_LITE_A 37 +-#define CLK_DIV_ACLK_LITE_A 38 +-#define CLK_DIV_ACLK_CSIS1 39 +-#define CLK_DIV_ACLK_CSIS0 40 +-#define CLK_DIV_PCLK_3AA1 41 +-#define CLK_DIV_ACLK_3AA1 42 +-#define CLK_DIV_PCLK_3AA0 43 +-#define CLK_DIV_ACLK_3AA0 44 +-#define CLK_DIV_SCLK_PIXELASYNC_LITE_C 45 +-#define CLK_DIV_PCLK_PIXELASYNC_LITE_C 46 +-#define CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT 47 +- +-#define CLK_ACLK_CSIS1 50 +-#define CLK_ACLK_CSIS0 51 +-#define CLK_ACLK_3AA1 52 +-#define CLK_ACLK_3AA0 53 +-#define CLK_ACLK_LITE_D 54 +-#define CLK_ACLK_LITE_B 55 +-#define CLK_ACLK_LITE_A 56 +-#define CLK_ACLK_AHBSYNCDN 57 +-#define CLK_ACLK_AXIUS_LITE_D 58 +-#define CLK_ACLK_AXIUS_LITE_B 59 +-#define CLK_ACLK_AXIUS_LITE_A 60 +-#define CLK_ACLK_ASYNCAPBM_3AA1 61 +-#define CLK_ACLK_ASYNCAPBS_3AA1 62 +-#define CLK_ACLK_ASYNCAPBM_3AA0 63 +-#define CLK_ACLK_ASYNCAPBS_3AA0 64 +-#define CLK_ACLK_ASYNCAPBM_LITE_D 65 +-#define CLK_ACLK_ASYNCAPBS_LITE_D 66 +-#define CLK_ACLK_ASYNCAPBM_LITE_B 67 +-#define CLK_ACLK_ASYNCAPBS_LITE_B 68 +-#define CLK_ACLK_ASYNCAPBM_LITE_A 69 +-#define CLK_ACLK_ASYNCAPBS_LITE_A 70 +-#define CLK_ACLK_ASYNCAXIM_ISP0P 71 +-#define CLK_ACLK_ASYNCAXIM_3AA1 72 +-#define CLK_ACLK_ASYNCAXIS_3AA1 73 +-#define CLK_ACLK_ASYNCAXIM_3AA0 74 +-#define CLK_ACLK_ASYNCAXIS_3AA0 75 +-#define CLK_ACLK_ASYNCAXIM_LITE_D 76 +-#define CLK_ACLK_ASYNCAXIS_LITE_D 77 +-#define CLK_ACLK_ASYNCAXIM_LITE_B 78 +-#define CLK_ACLK_ASYNCAXIS_LITE_B 79 +-#define CLK_ACLK_ASYNCAXIM_LITE_A 80 +-#define CLK_ACLK_ASYNCAXIS_LITE_A 81 +-#define CLK_ACLK_AHB2APB_ISPSFRP 82 +-#define CLK_ACLK_AXI2APB_ISP0P 83 +-#define CLK_ACLK_AXI2AHB_ISP0P 84 +-#define CLK_ACLK_XIU_IS0X 85 +-#define CLK_ACLK_XIU_ISP0EX 86 +-#define CLK_ACLK_CAM0NP_276 87 +-#define CLK_ACLK_CAM0ND_400 88 +-#define CLK_ACLK_SMMU_3AA1 89 +-#define CLK_ACLK_SMMU_3AA0 90 +-#define CLK_ACLK_SMMU_LITE_D 91 +-#define CLK_ACLK_SMMU_LITE_B 92 +-#define CLK_ACLK_SMMU_LITE_A 93 +-#define CLK_ACLK_BTS_3AA1 94 +-#define CLK_ACLK_BTS_3AA0 95 +-#define CLK_ACLK_BTS_LITE_D 96 +-#define CLK_ACLK_BTS_LITE_B 97 +-#define CLK_ACLK_BTS_LITE_A 98 +-#define CLK_PCLK_SMMU_3AA1 99 +-#define CLK_PCLK_SMMU_3AA0 100 +-#define CLK_PCLK_SMMU_LITE_D 101 +-#define CLK_PCLK_SMMU_LITE_B 102 +-#define CLK_PCLK_SMMU_LITE_A 103 +-#define CLK_PCLK_BTS_3AA1 104 +-#define CLK_PCLK_BTS_3AA0 105 +-#define CLK_PCLK_BTS_LITE_D 106 +-#define CLK_PCLK_BTS_LITE_B 107 +-#define CLK_PCLK_BTS_LITE_A 108 +-#define CLK_PCLK_ASYNCAXI_CAM1 109 +-#define CLK_PCLK_ASYNCAXI_3AA1 110 +-#define CLK_PCLK_ASYNCAXI_3AA0 111 +-#define CLK_PCLK_ASYNCAXI_LITE_D 112 +-#define CLK_PCLK_ASYNCAXI_LITE_B 113 +-#define CLK_PCLK_ASYNCAXI_LITE_A 114 +-#define CLK_PCLK_PMU_CAM0 115 +-#define CLK_PCLK_SYSREG_CAM0 116 +-#define CLK_PCLK_CMU_CAM0_LOCAL 117 +-#define CLK_PCLK_CSIS1 118 +-#define CLK_PCLK_CSIS0 119 +-#define CLK_PCLK_3AA1 120 +-#define CLK_PCLK_3AA0 121 +-#define CLK_PCLK_LITE_D 122 +-#define CLK_PCLK_LITE_B 123 +-#define CLK_PCLK_LITE_A 124 +-#define CLK_PHYCLK_RXBYTECLKHS0_S4 125 +-#define CLK_PHYCLK_RXBYTECLKHS0_S2A 126 +-#define CLK_SCLK_LITE_FREECNT 127 +-#define CLK_SCLK_PIXELASYNCM_3AA1 128 +-#define CLK_SCLK_PIXELASYNCM_3AA0 129 +-#define CLK_SCLK_PIXELASYNCS_3AA0 130 +-#define CLK_SCLK_PIXELASYNCM_LITE_C 131 +-#define CLK_SCLK_PIXELASYNCM_LITE_C_INIT 132 +-#define CLK_SCLK_PIXELASYNCS_LITE_C_INIT 133 +- +-#define CAM0_NR_CLK 134 +- +-/* CMU_CAM1 */ +-#define CLK_PHYCLK_RXBYTEECLKHS0_S2B 1 +- +-#define CLK_MOUT_SCLK_ISP_UART_USER 2 +-#define CLK_MOUT_SCLK_ISP_SPI1_USER 3 +-#define CLK_MOUT_SCLK_ISP_SPI0_USER 4 +-#define CLK_MOUT_ACLK_CAM1_333_USER 5 +-#define CLK_MOUT_ACLK_CAM1_400_USER 6 +-#define CLK_MOUT_ACLK_CAM1_552_USER 7 +-#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER 8 +-#define CLK_MOUT_ACLK_CSIS2_B 9 +-#define CLK_MOUT_ACLK_CSIS2_A 10 +-#define CLK_MOUT_ACLK_FD_B 11 +-#define CLK_MOUT_ACLK_FD_A 12 +-#define CLK_MOUT_ACLK_LITE_C_B 13 +-#define CLK_MOUT_ACLK_LITE_C_A 14 +- +-#define CLK_DIV_SCLK_ISP_MPWM 15 +-#define CLK_DIV_PCLK_CAM1_83 16 +-#define CLK_DIV_PCLK_CAM1_166 17 +-#define CLK_DIV_PCLK_DBG_CAM1 18 +-#define CLK_DIV_ATCLK_CAM1 19 +-#define CLK_DIV_ACLK_CSIS2 20 +-#define CLK_DIV_PCLK_FD 21 +-#define CLK_DIV_ACLK_FD 22 +-#define CLK_DIV_PCLK_LITE_C 23 +-#define CLK_DIV_ACLK_LITE_C 24 +- +-#define CLK_ACLK_ISP_GIC 25 +-#define CLK_ACLK_FD 26 +-#define CLK_ACLK_LITE_C 27 +-#define CLK_ACLK_CSIS2 28 +-#define CLK_ACLK_ASYNCAPBM_FD 29 +-#define CLK_ACLK_ASYNCAPBS_FD 30 +-#define CLK_ACLK_ASYNCAPBM_LITE_C 31 +-#define CLK_ACLK_ASYNCAPBS_LITE_C 32 +-#define CLK_ACLK_ASYNCAHBS_SFRISP2H2 33 +-#define CLK_ACLK_ASYNCAHBS_SFRISP2H1 34 +-#define CLK_ACLK_ASYNCAXIM_CA5 35 +-#define CLK_ACLK_ASYNCAXIS_CA5 36 +-#define CLK_ACLK_ASYNCAXIS_ISPX2 37 +-#define CLK_ACLK_ASYNCAXIS_ISPX1 38 +-#define CLK_ACLK_ASYNCAXIS_ISPX0 39 +-#define CLK_ACLK_ASYNCAXIM_ISPEX 40 +-#define CLK_ACLK_ASYNCAXIM_ISP3P 41 +-#define CLK_ACLK_ASYNCAXIS_ISP3P 42 +-#define CLK_ACLK_ASYNCAXIM_FD 43 +-#define CLK_ACLK_ASYNCAXIS_FD 44 +-#define CLK_ACLK_ASYNCAXIM_LITE_C 45 +-#define CLK_ACLK_ASYNCAXIS_LITE_C 46 +-#define CLK_ACLK_AHB2APB_ISP5P 47 +-#define CLK_ACLK_AHB2APB_ISP3P 48 +-#define CLK_ACLK_AXI2APB_ISP3P 49 +-#define CLK_ACLK_AHB_SFRISP2H 50 +-#define CLK_ACLK_AXI_ISP_HX_R 51 +-#define CLK_ACLK_AXI_ISP_CX_R 52 +-#define CLK_ACLK_AXI_ISP_HX 53 +-#define CLK_ACLK_AXI_ISP_CX 54 +-#define CLK_ACLK_XIU_ISPX 55 +-#define CLK_ACLK_XIU_ISPEX 56 +-#define CLK_ACLK_CAM1NP_333 57 +-#define CLK_ACLK_CAM1ND_400 58 +-#define CLK_ACLK_SMMU_ISPCPU 59 +-#define CLK_ACLK_SMMU_FD 60 +-#define CLK_ACLK_SMMU_LITE_C 61 +-#define CLK_ACLK_BTS_ISP3P 62 +-#define CLK_ACLK_BTS_FD 63 +-#define CLK_ACLK_BTS_LITE_C 64 +-#define CLK_ACLK_AHBDN_SFRISP2H 65 +-#define CLK_ACLK_AHBDN_ISP5P 66 +-#define CLK_ACLK_AXIUS_ISP3P 67 +-#define CLK_ACLK_AXIUS_FD 68 +-#define CLK_ACLK_AXIUS_LITE_C 69 +-#define CLK_PCLK_SMMU_ISPCPU 70 +-#define CLK_PCLK_SMMU_FD 71 +-#define CLK_PCLK_SMMU_LITE_C 72 +-#define CLK_PCLK_BTS_ISP3P 73 +-#define CLK_PCLK_BTS_FD 74 +-#define CLK_PCLK_BTS_LITE_C 75 +-#define CLK_PCLK_ASYNCAXIM_CA5 76 +-#define CLK_PCLK_ASYNCAXIM_ISPEX 77 +-#define CLK_PCLK_ASYNCAXIM_ISP3P 78 +-#define CLK_PCLK_ASYNCAXIM_FD 79 +-#define CLK_PCLK_ASYNCAXIM_LITE_C 80 +-#define CLK_PCLK_PMU_CAM1 81 +-#define CLK_PCLK_SYSREG_CAM1 82 +-#define CLK_PCLK_CMU_CAM1_LOCAL 83 +-#define CLK_PCLK_ISP_MCTADC 84 +-#define CLK_PCLK_ISP_WDT 85 +-#define CLK_PCLK_ISP_PWM 86 +-#define CLK_PCLK_ISP_UART 87 +-#define CLK_PCLK_ISP_MCUCTL 88 +-#define CLK_PCLK_ISP_SPI1 89 +-#define CLK_PCLK_ISP_SPI0 90 +-#define CLK_PCLK_ISP_I2C2 91 +-#define CLK_PCLK_ISP_I2C1 92 +-#define CLK_PCLK_ISP_I2C0 93 +-#define CLK_PCLK_ISP_MPWM 94 +-#define CLK_PCLK_FD 95 +-#define CLK_PCLK_LITE_C 96 +-#define CLK_PCLK_CSIS2 97 +-#define CLK_SCLK_ISP_I2C2 98 +-#define CLK_SCLK_ISP_I2C1 99 +-#define CLK_SCLK_ISP_I2C0 100 +-#define CLK_SCLK_ISP_PWM 101 +-#define CLK_PHYCLK_RXBYTECLKHS0_S2B 102 +-#define CLK_SCLK_LITE_C_FREECNT 103 +-#define CLK_SCLK_PIXELASYNCM_FD 104 +-#define CLK_SCLK_ISP_MCTADC 105 +-#define CLK_SCLK_ISP_UART 106 +-#define CLK_SCLK_ISP_SPI1 107 +-#define CLK_SCLK_ISP_SPI0 108 +-#define CLK_SCLK_ISP_MPWM 109 +-#define CLK_PCLK_DBG_ISP 110 +-#define CLK_ATCLK_ISP 111 +-#define CLK_SCLK_ISP_CA5 112 +- +-#define CAM1_NR_CLK 113 +- +-/* CMU_IMEM */ +-#define CLK_ACLK_SLIMSSS 2 +-#define CLK_PCLK_SLIMSSS 35 +- +-#define IMEM_NR_CLK 36 +- +-#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/exynos7-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/exynos7-clk.h +deleted file mode 100644 +index fce33c7050c8..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/exynos7-clk.h ++++ /dev/null +@@ -1,204 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2014 Samsung Electronics Co., Ltd. +- * Author: Naveen Krishna Ch +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H +-#define _DT_BINDINGS_CLOCK_EXYNOS7_H +- +-/* TOPC */ +-#define DOUT_ACLK_PERIS 1 +-#define DOUT_SCLK_BUS0_PLL 2 +-#define DOUT_SCLK_BUS1_PLL 3 +-#define DOUT_SCLK_CC_PLL 4 +-#define DOUT_SCLK_MFC_PLL 5 +-#define DOUT_ACLK_CCORE_133 6 +-#define DOUT_ACLK_MSCL_532 7 +-#define ACLK_MSCL_532 8 +-#define DOUT_SCLK_AUD_PLL 9 +-#define FOUT_AUD_PLL 10 +-#define SCLK_AUD_PLL 11 +-#define SCLK_MFC_PLL_B 12 +-#define SCLK_MFC_PLL_A 13 +-#define SCLK_BUS1_PLL_B 14 +-#define SCLK_BUS1_PLL_A 15 +-#define SCLK_BUS0_PLL_B 16 +-#define SCLK_BUS0_PLL_A 17 +-#define SCLK_CC_PLL_B 18 +-#define SCLK_CC_PLL_A 19 +-#define ACLK_CCORE_133 20 +-#define ACLK_PERIS_66 21 +-#define TOPC_NR_CLK 22 +- +-/* TOP0 */ +-#define DOUT_ACLK_PERIC1 1 +-#define DOUT_ACLK_PERIC0 2 +-#define CLK_SCLK_UART0 3 +-#define CLK_SCLK_UART1 4 +-#define CLK_SCLK_UART2 5 +-#define CLK_SCLK_UART3 6 +-#define CLK_SCLK_SPI0 7 +-#define CLK_SCLK_SPI1 8 +-#define CLK_SCLK_SPI2 9 +-#define CLK_SCLK_SPI3 10 +-#define CLK_SCLK_SPI4 11 +-#define CLK_SCLK_SPDIF 12 +-#define CLK_SCLK_PCM1 13 +-#define CLK_SCLK_I2S1 14 +-#define CLK_ACLK_PERIC0_66 15 +-#define CLK_ACLK_PERIC1_66 16 +-#define TOP0_NR_CLK 17 +- +-/* TOP1 */ +-#define DOUT_ACLK_FSYS1_200 1 +-#define DOUT_ACLK_FSYS0_200 2 +-#define DOUT_SCLK_MMC2 3 +-#define DOUT_SCLK_MMC1 4 +-#define DOUT_SCLK_MMC0 5 +-#define CLK_SCLK_MMC2 6 +-#define CLK_SCLK_MMC1 7 +-#define CLK_SCLK_MMC0 8 +-#define CLK_ACLK_FSYS0_200 9 +-#define CLK_ACLK_FSYS1_200 10 +-#define CLK_SCLK_PHY_FSYS1 11 +-#define CLK_SCLK_PHY_FSYS1_26M 12 +-#define MOUT_SCLK_UFSUNIPRO20 13 +-#define DOUT_SCLK_UFSUNIPRO20 14 +-#define CLK_SCLK_UFSUNIPRO20 15 +-#define DOUT_SCLK_PHY_FSYS1 16 +-#define DOUT_SCLK_PHY_FSYS1_26M 17 +-#define TOP1_NR_CLK 18 +- +-/* CCORE */ +-#define PCLK_RTC 1 +-#define CCORE_NR_CLK 2 +- +-/* PERIC0 */ +-#define PCLK_UART0 1 +-#define SCLK_UART0 2 +-#define PCLK_HSI2C0 3 +-#define PCLK_HSI2C1 4 +-#define PCLK_HSI2C4 5 +-#define PCLK_HSI2C5 6 +-#define PCLK_HSI2C9 7 +-#define PCLK_HSI2C10 8 +-#define PCLK_HSI2C11 9 +-#define PCLK_PWM 10 +-#define SCLK_PWM 11 +-#define PCLK_ADCIF 12 +-#define PERIC0_NR_CLK 13 +- +-/* PERIC1 */ +-#define PCLK_UART1 1 +-#define PCLK_UART2 2 +-#define PCLK_UART3 3 +-#define SCLK_UART1 4 +-#define SCLK_UART2 5 +-#define SCLK_UART3 6 +-#define PCLK_HSI2C2 7 +-#define PCLK_HSI2C3 8 +-#define PCLK_HSI2C6 9 +-#define PCLK_HSI2C7 10 +-#define PCLK_HSI2C8 11 +-#define PCLK_SPI0 12 +-#define PCLK_SPI1 13 +-#define PCLK_SPI2 14 +-#define PCLK_SPI3 15 +-#define PCLK_SPI4 16 +-#define SCLK_SPI0 17 +-#define SCLK_SPI1 18 +-#define SCLK_SPI2 19 +-#define SCLK_SPI3 20 +-#define SCLK_SPI4 21 +-#define PCLK_I2S1 22 +-#define PCLK_PCM1 23 +-#define PCLK_SPDIF 24 +-#define SCLK_I2S1 25 +-#define SCLK_PCM1 26 +-#define SCLK_SPDIF 27 +-#define PERIC1_NR_CLK 28 +- +-/* PERIS */ +-#define PCLK_CHIPID 1 +-#define SCLK_CHIPID 2 +-#define PCLK_WDT 3 +-#define PCLK_TMU 4 +-#define SCLK_TMU 5 +-#define PERIS_NR_CLK 6 +- +-/* FSYS0 */ +-#define ACLK_MMC2 1 +-#define ACLK_AXIUS_USBDRD30X_FSYS0X 2 +-#define ACLK_USBDRD300 3 +-#define SCLK_USBDRD300_SUSPENDCLK 4 +-#define SCLK_USBDRD300_REFCLK 5 +-#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6 +-#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7 +-#define OSCCLK_PHY_CLKOUT_USB30_PHY 8 +-#define ACLK_PDMA0 9 +-#define ACLK_PDMA1 10 +-#define FSYS0_NR_CLK 11 +- +-/* FSYS1 */ +-#define ACLK_MMC1 1 +-#define ACLK_MMC0 2 +-#define PHYCLK_UFS20_TX0_SYMBOL 3 +-#define PHYCLK_UFS20_RX0_SYMBOL 4 +-#define PHYCLK_UFS20_RX1_SYMBOL 5 +-#define ACLK_UFS20_LINK 6 +-#define SCLK_UFSUNIPRO20_USER 7 +-#define PHYCLK_UFS20_RX1_SYMBOL_USER 8 +-#define PHYCLK_UFS20_RX0_SYMBOL_USER 9 +-#define PHYCLK_UFS20_TX0_SYMBOL_USER 10 +-#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11 +-#define SCLK_COMBO_PHY_EMBEDDED_26M 12 +-#define DOUT_PCLK_FSYS1 13 +-#define PCLK_GPIO_FSYS1 14 +-#define MOUT_FSYS1_PHYCLK_SEL1 15 +-#define FSYS1_NR_CLK 16 +- +-/* MSCL */ +-#define USERMUX_ACLK_MSCL_532 1 +-#define DOUT_PCLK_MSCL 2 +-#define ACLK_MSCL_0 3 +-#define ACLK_MSCL_1 4 +-#define ACLK_JPEG 5 +-#define ACLK_G2D 6 +-#define ACLK_LH_ASYNC_SI_MSCL_0 7 +-#define ACLK_LH_ASYNC_SI_MSCL_1 8 +-#define ACLK_AXI2ACEL_BRIDGE 9 +-#define ACLK_XIU_MSCLX_0 10 +-#define ACLK_XIU_MSCLX_1 11 +-#define ACLK_QE_MSCL_0 12 +-#define ACLK_QE_MSCL_1 13 +-#define ACLK_QE_JPEG 14 +-#define ACLK_QE_G2D 15 +-#define ACLK_PPMU_MSCL_0 16 +-#define ACLK_PPMU_MSCL_1 17 +-#define ACLK_MSCLNP_133 18 +-#define ACLK_AHB2APB_MSCL0P 19 +-#define ACLK_AHB2APB_MSCL1P 20 +- +-#define PCLK_MSCL_0 21 +-#define PCLK_MSCL_1 22 +-#define PCLK_JPEG 23 +-#define PCLK_G2D 24 +-#define PCLK_QE_MSCL_0 25 +-#define PCLK_QE_MSCL_1 26 +-#define PCLK_QE_JPEG 27 +-#define PCLK_QE_G2D 28 +-#define PCLK_PPMU_MSCL_0 29 +-#define PCLK_PPMU_MSCL_1 30 +-#define PCLK_AXI2ACEL_BRIDGE 31 +-#define PCLK_PMU_MSCL 32 +-#define MSCL_NR_CLK 33 +- +-/* AUD */ +-#define SCLK_I2S 1 +-#define SCLK_PCM 2 +-#define PCLK_I2S 3 +-#define PCLK_PCM 4 +-#define ACLK_ADMA 5 +-#define AUD_NR_CLK 6 +-#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/fsl,qoriq-clockgen.h b/scripts/dtc/include-prefixes/dt-bindings/clock/fsl,qoriq-clockgen.h +deleted file mode 100644 +index ddec7d0bdc7f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/fsl,qoriq-clockgen.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +- +-#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H +-#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H +- +-#define QORIQ_CLK_SYSCLK 0 +-#define QORIQ_CLK_CMUX 1 +-#define QORIQ_CLK_HWACCEL 2 +-#define QORIQ_CLK_FMAN 3 +-#define QORIQ_CLK_PLATFORM_PLL 4 +-#define QORIQ_CLK_CORECLK 5 +- +-#define QORIQ_CLK_PLL_DIV(x) ((x) - 1) +- +-#endif /* DT_CLOCK_FSL_QORIQ_CLOCKGEN_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/g12a-aoclkc.h b/scripts/dtc/include-prefixes/dt-bindings/clock/g12a-aoclkc.h +deleted file mode 100644 +index e916e49ff288..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/g12a-aoclkc.h ++++ /dev/null +@@ -1,36 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +-/* +- * Copyright (c) 2016 BayLibre, SAS +- * Author: Neil Armstrong +- * +- * Copyright (c) 2018 Amlogic, inc. +- * Author: Qiufang Dai +- */ +- +-#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK +-#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK +- +-#define CLKID_AO_AHB 0 +-#define CLKID_AO_IR_IN 1 +-#define CLKID_AO_I2C_M0 2 +-#define CLKID_AO_I2C_S0 3 +-#define CLKID_AO_UART 4 +-#define CLKID_AO_PROD_I2C 5 +-#define CLKID_AO_UART2 6 +-#define CLKID_AO_IR_OUT 7 +-#define CLKID_AO_SAR_ADC 8 +-#define CLKID_AO_MAILBOX 9 +-#define CLKID_AO_M3 10 +-#define CLKID_AO_AHB_SRAM 11 +-#define CLKID_AO_RTI 12 +-#define CLKID_AO_M4_FCLK 13 +-#define CLKID_AO_M4_HCLK 14 +-#define CLKID_AO_CLK81 15 +-#define CLKID_AO_SAR_ADC_SEL 16 +-#define CLKID_AO_SAR_ADC_CLK 18 +-#define CLKID_AO_CTS_OSCIN 19 +-#define CLKID_AO_32K 23 +-#define CLKID_AO_CEC 27 +-#define CLKID_AO_CTS_RTC_OSCIN 28 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/g12a-clkc.h b/scripts/dtc/include-prefixes/dt-bindings/clock/g12a-clkc.h +deleted file mode 100644 +index a93b58c5e18e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/g12a-clkc.h ++++ /dev/null +@@ -1,153 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ +-/* +- * Meson-G12A clock tree IDs +- * +- * Copyright (c) 2018 Amlogic, Inc. All rights reserved. +- */ +- +-#ifndef __G12A_CLKC_H +-#define __G12A_CLKC_H +- +-#define CLKID_SYS_PLL 0 +-#define CLKID_FIXED_PLL 1 +-#define CLKID_FCLK_DIV2 2 +-#define CLKID_FCLK_DIV3 3 +-#define CLKID_FCLK_DIV4 4 +-#define CLKID_FCLK_DIV5 5 +-#define CLKID_FCLK_DIV7 6 +-#define CLKID_GP0_PLL 7 +-#define CLKID_CLK81 10 +-#define CLKID_MPLL0 11 +-#define CLKID_MPLL1 12 +-#define CLKID_MPLL2 13 +-#define CLKID_MPLL3 14 +-#define CLKID_DDR 15 +-#define CLKID_DOS 16 +-#define CLKID_AUDIO_LOCKER 17 +-#define CLKID_MIPI_DSI_HOST 18 +-#define CLKID_ETH_PHY 19 +-#define CLKID_ISA 20 +-#define CLKID_PL301 21 +-#define CLKID_PERIPHS 22 +-#define CLKID_SPICC0 23 +-#define CLKID_I2C 24 +-#define CLKID_SANA 25 +-#define CLKID_SD 26 +-#define CLKID_RNG0 27 +-#define CLKID_UART0 28 +-#define CLKID_SPICC1 29 +-#define CLKID_HIU_IFACE 30 +-#define CLKID_MIPI_DSI_PHY 31 +-#define CLKID_ASSIST_MISC 32 +-#define CLKID_SD_EMMC_A 33 +-#define CLKID_SD_EMMC_B 34 +-#define CLKID_SD_EMMC_C 35 +-#define CLKID_AUDIO_CODEC 36 +-#define CLKID_AUDIO 37 +-#define CLKID_ETH 38 +-#define CLKID_DEMUX 39 +-#define CLKID_AUDIO_IFIFO 40 +-#define CLKID_ADC 41 +-#define CLKID_UART1 42 +-#define CLKID_G2D 43 +-#define CLKID_RESET 44 +-#define CLKID_PCIE_COMB 45 +-#define CLKID_PARSER 46 +-#define CLKID_USB 47 +-#define CLKID_PCIE_PHY 48 +-#define CLKID_AHB_ARB0 49 +-#define CLKID_AHB_DATA_BUS 50 +-#define CLKID_AHB_CTRL_BUS 51 +-#define CLKID_HTX_HDCP22 52 +-#define CLKID_HTX_PCLK 53 +-#define CLKID_BT656 54 +-#define CLKID_USB1_DDR_BRIDGE 55 +-#define CLKID_MMC_PCLK 56 +-#define CLKID_UART2 57 +-#define CLKID_VPU_INTR 58 +-#define CLKID_GIC 59 +-#define CLKID_SD_EMMC_A_CLK0 60 +-#define CLKID_SD_EMMC_B_CLK0 61 +-#define CLKID_SD_EMMC_C_CLK0 62 +-#define CLKID_HIFI_PLL 74 +-#define CLKID_VCLK2_VENCI0 80 +-#define CLKID_VCLK2_VENCI1 81 +-#define CLKID_VCLK2_VENCP0 82 +-#define CLKID_VCLK2_VENCP1 83 +-#define CLKID_VCLK2_VENCT0 84 +-#define CLKID_VCLK2_VENCT1 85 +-#define CLKID_VCLK2_OTHER 86 +-#define CLKID_VCLK2_ENCI 87 +-#define CLKID_VCLK2_ENCP 88 +-#define CLKID_DAC_CLK 89 +-#define CLKID_AOCLK 90 +-#define CLKID_IEC958 91 +-#define CLKID_ENC480P 92 +-#define CLKID_RNG1 93 +-#define CLKID_VCLK2_ENCT 94 +-#define CLKID_VCLK2_ENCL 95 +-#define CLKID_VCLK2_VENCLMMC 96 +-#define CLKID_VCLK2_VENCL 97 +-#define CLKID_VCLK2_OTHER1 98 +-#define CLKID_FCLK_DIV2P5 99 +-#define CLKID_DMA 105 +-#define CLKID_EFUSE 106 +-#define CLKID_ROM_BOOT 107 +-#define CLKID_RESET_SEC 108 +-#define CLKID_SEC_AHB_APB3 109 +-#define CLKID_VPU_0_SEL 110 +-#define CLKID_VPU_0 112 +-#define CLKID_VPU_1_SEL 113 +-#define CLKID_VPU_1 115 +-#define CLKID_VPU 116 +-#define CLKID_VAPB_0_SEL 117 +-#define CLKID_VAPB_0 119 +-#define CLKID_VAPB_1_SEL 120 +-#define CLKID_VAPB_1 122 +-#define CLKID_VAPB_SEL 123 +-#define CLKID_VAPB 124 +-#define CLKID_HDMI_PLL 128 +-#define CLKID_VID_PLL 129 +-#define CLKID_VCLK 138 +-#define CLKID_VCLK2 139 +-#define CLKID_VCLK_DIV1 148 +-#define CLKID_VCLK_DIV2 149 +-#define CLKID_VCLK_DIV4 150 +-#define CLKID_VCLK_DIV6 151 +-#define CLKID_VCLK_DIV12 152 +-#define CLKID_VCLK2_DIV1 153 +-#define CLKID_VCLK2_DIV2 154 +-#define CLKID_VCLK2_DIV4 155 +-#define CLKID_VCLK2_DIV6 156 +-#define CLKID_VCLK2_DIV12 157 +-#define CLKID_CTS_ENCI 162 +-#define CLKID_CTS_ENCP 163 +-#define CLKID_CTS_VDAC 164 +-#define CLKID_HDMI_TX 165 +-#define CLKID_HDMI 168 +-#define CLKID_MALI_0_SEL 169 +-#define CLKID_MALI_0 171 +-#define CLKID_MALI_1_SEL 172 +-#define CLKID_MALI_1 174 +-#define CLKID_MALI 175 +-#define CLKID_MPLL_50M 177 +-#define CLKID_CPU_CLK 187 +-#define CLKID_PCIE_PLL 201 +-#define CLKID_VDEC_1 204 +-#define CLKID_VDEC_HEVC 207 +-#define CLKID_VDEC_HEVCF 210 +-#define CLKID_TS 212 +-#define CLKID_CPUB_CLK 224 +-#define CLKID_GP1_PLL 243 +-#define CLKID_DSU_CLK 252 +-#define CLKID_CPU1_CLK 253 +-#define CLKID_CPU2_CLK 254 +-#define CLKID_CPU3_CLK 255 +-#define CLKID_SPICC0_SCLK 258 +-#define CLKID_SPICC1_SCLK 261 +-#define CLKID_NNA_AXI_CLK 264 +-#define CLKID_NNA_CORE_CLK 267 +-#define CLKID_MIPI_DSI_PXCLK_SEL 269 +-#define CLKID_MIPI_DSI_PXCLK 270 +- +-#endif /* __G12A_CLKC_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/gxbb-aoclkc.h b/scripts/dtc/include-prefixes/dt-bindings/clock/gxbb-aoclkc.h +deleted file mode 100644 +index ec3b26319fc4..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/gxbb-aoclkc.h ++++ /dev/null +@@ -1,74 +0,0 @@ +-/* +- * This file is provided under a dual BSD/GPLv2 license. When using or +- * redistributing this file, you may do so under either license. +- * +- * GPL LICENSE SUMMARY +- * +- * Copyright (c) 2016 BayLibre, SAS. +- * Author: Neil Armstrong +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of version 2 of the GNU General Public License as +- * published by the Free Software Foundation. +- * +- * This program is distributed in the hope that it will be useful, but +- * WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +- * General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, see . +- * The full GNU General Public License is included in this distribution +- * in the file called COPYING. +- * +- * BSD LICENSE +- * +- * Copyright (c) 2016 BayLibre, SAS. +- * Author: Neil Armstrong +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Intel Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK +-#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK +- +-#define CLKID_AO_REMOTE 0 +-#define CLKID_AO_I2C_MASTER 1 +-#define CLKID_AO_I2C_SLAVE 2 +-#define CLKID_AO_UART1 3 +-#define CLKID_AO_UART2 4 +-#define CLKID_AO_IR_BLASTER 5 +-#define CLKID_AO_CEC_32K 6 +-#define CLKID_AO_CTS_OSCIN 7 +-#define CLKID_AO_32K_PRE 8 +-#define CLKID_AO_32K_DIV 9 +-#define CLKID_AO_32K_SEL 10 +-#define CLKID_AO_32K 11 +-#define CLKID_AO_CTS_RTC_OSCIN 12 +-#define CLKID_AO_CLK81 13 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/gxbb-clkc.h b/scripts/dtc/include-prefixes/dt-bindings/clock/gxbb-clkc.h +deleted file mode 100644 +index 4073eb7a9da1..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/gxbb-clkc.h ++++ /dev/null +@@ -1,151 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * GXBB clock tree IDs +- */ +- +-#ifndef __GXBB_CLKC_H +-#define __GXBB_CLKC_H +- +-#define CLKID_SYS_PLL 0 +-#define CLKID_HDMI_PLL 2 +-#define CLKID_FIXED_PLL 3 +-#define CLKID_FCLK_DIV2 4 +-#define CLKID_FCLK_DIV3 5 +-#define CLKID_FCLK_DIV4 6 +-#define CLKID_FCLK_DIV5 7 +-#define CLKID_FCLK_DIV7 8 +-#define CLKID_GP0_PLL 9 +-#define CLKID_CLK81 12 +-#define CLKID_MPLL0 13 +-#define CLKID_MPLL1 14 +-#define CLKID_MPLL2 15 +-#define CLKID_DDR 16 +-#define CLKID_DOS 17 +-#define CLKID_ISA 18 +-#define CLKID_PL301 19 +-#define CLKID_PERIPHS 20 +-#define CLKID_SPICC 21 +-#define CLKID_I2C 22 +-#define CLKID_SAR_ADC 23 +-#define CLKID_SMART_CARD 24 +-#define CLKID_RNG0 25 +-#define CLKID_UART0 26 +-#define CLKID_SDHC 27 +-#define CLKID_STREAM 28 +-#define CLKID_ASYNC_FIFO 29 +-#define CLKID_SDIO 30 +-#define CLKID_ABUF 31 +-#define CLKID_HIU_IFACE 32 +-#define CLKID_ASSIST_MISC 33 +-#define CLKID_SPI 34 +-#define CLKID_ETH 36 +-#define CLKID_I2S_SPDIF 35 +-#define CLKID_DEMUX 37 +-#define CLKID_AIU_GLUE 38 +-#define CLKID_IEC958 39 +-#define CLKID_I2S_OUT 40 +-#define CLKID_AMCLK 41 +-#define CLKID_AIFIFO2 42 +-#define CLKID_MIXER 43 +-#define CLKID_MIXER_IFACE 44 +-#define CLKID_ADC 45 +-#define CLKID_BLKMV 46 +-#define CLKID_AIU 47 +-#define CLKID_UART1 48 +-#define CLKID_G2D 49 +-#define CLKID_USB0 50 +-#define CLKID_USB1 51 +-#define CLKID_RESET 52 +-#define CLKID_NAND 53 +-#define CLKID_DOS_PARSER 54 +-#define CLKID_USB 55 +-#define CLKID_VDIN1 56 +-#define CLKID_AHB_ARB0 57 +-#define CLKID_EFUSE 58 +-#define CLKID_BOOT_ROM 59 +-#define CLKID_AHB_DATA_BUS 60 +-#define CLKID_AHB_CTRL_BUS 61 +-#define CLKID_HDMI_INTR_SYNC 62 +-#define CLKID_HDMI_PCLK 63 +-#define CLKID_USB1_DDR_BRIDGE 64 +-#define CLKID_USB0_DDR_BRIDGE 65 +-#define CLKID_MMC_PCLK 66 +-#define CLKID_DVIN 67 +-#define CLKID_UART2 68 +-#define CLKID_SANA 69 +-#define CLKID_VPU_INTR 70 +-#define CLKID_SEC_AHB_AHB3_BRIDGE 71 +-#define CLKID_CLK81_A53 72 +-#define CLKID_VCLK2_VENCI0 73 +-#define CLKID_VCLK2_VENCI1 74 +-#define CLKID_VCLK2_VENCP0 75 +-#define CLKID_VCLK2_VENCP1 76 +-#define CLKID_GCLK_VENCI_INT0 77 +-#define CLKID_GCLK_VENCI_INT 78 +-#define CLKID_DAC_CLK 79 +-#define CLKID_AOCLK_GATE 80 +-#define CLKID_IEC958_GATE 81 +-#define CLKID_ENC480P 82 +-#define CLKID_RNG1 83 +-#define CLKID_GCLK_VENCI_INT1 84 +-#define CLKID_VCLK2_VENCLMCC 85 +-#define CLKID_VCLK2_VENCL 86 +-#define CLKID_VCLK_OTHER 87 +-#define CLKID_EDP 88 +-#define CLKID_AO_MEDIA_CPU 89 +-#define CLKID_AO_AHB_SRAM 90 +-#define CLKID_AO_AHB_BUS 91 +-#define CLKID_AO_IFACE 92 +-#define CLKID_AO_I2C 93 +-#define CLKID_SD_EMMC_A 94 +-#define CLKID_SD_EMMC_B 95 +-#define CLKID_SD_EMMC_C 96 +-#define CLKID_SAR_ADC_CLK 97 +-#define CLKID_SAR_ADC_SEL 98 +-#define CLKID_MALI_0_SEL 100 +-#define CLKID_MALI_0 102 +-#define CLKID_MALI_1_SEL 103 +-#define CLKID_MALI_1 105 +-#define CLKID_MALI 106 +-#define CLKID_CTS_AMCLK 107 +-#define CLKID_CTS_MCLK_I958 110 +-#define CLKID_CTS_I958 113 +-#define CLKID_32K_CLK 114 +-#define CLKID_SD_EMMC_A_CLK0 119 +-#define CLKID_SD_EMMC_B_CLK0 122 +-#define CLKID_SD_EMMC_C_CLK0 125 +-#define CLKID_VPU_0_SEL 126 +-#define CLKID_VPU_0 128 +-#define CLKID_VPU_1_SEL 129 +-#define CLKID_VPU_1 131 +-#define CLKID_VPU 132 +-#define CLKID_VAPB_0_SEL 133 +-#define CLKID_VAPB_0 135 +-#define CLKID_VAPB_1_SEL 136 +-#define CLKID_VAPB_1 138 +-#define CLKID_VAPB_SEL 139 +-#define CLKID_VAPB 140 +-#define CLKID_VDEC_1 153 +-#define CLKID_VDEC_HEVC 156 +-#define CLKID_GEN_CLK 159 +-#define CLKID_VID_PLL 166 +-#define CLKID_VCLK 175 +-#define CLKID_VCLK2 176 +-#define CLKID_VCLK_DIV1 185 +-#define CLKID_VCLK_DIV2 186 +-#define CLKID_VCLK_DIV4 187 +-#define CLKID_VCLK_DIV6 188 +-#define CLKID_VCLK_DIV12 189 +-#define CLKID_VCLK2_DIV1 190 +-#define CLKID_VCLK2_DIV2 191 +-#define CLKID_VCLK2_DIV4 192 +-#define CLKID_VCLK2_DIV6 193 +-#define CLKID_VCLK2_DIV12 194 +-#define CLKID_CTS_ENCI 199 +-#define CLKID_CTS_ENCP 200 +-#define CLKID_CTS_VDAC 201 +-#define CLKID_HDMI_TX 202 +-#define CLKID_HDMI 205 +-#define CLKID_ACODEC 206 +- +-#endif /* __GXBB_CLKC_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/hi3516cv300-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/hi3516cv300-clock.h +deleted file mode 100644 +index ccea1bab7a6f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/hi3516cv300-clock.h ++++ /dev/null +@@ -1,36 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. +- */ +- +-#ifndef __DTS_HI3516CV300_CLOCK_H +-#define __DTS_HI3516CV300_CLOCK_H +- +-/* hi3516CV300 core CRG */ +-#define HI3516CV300_APB_CLK 0 +-#define HI3516CV300_UART0_CLK 1 +-#define HI3516CV300_UART1_CLK 2 +-#define HI3516CV300_UART2_CLK 3 +-#define HI3516CV300_SPI0_CLK 4 +-#define HI3516CV300_SPI1_CLK 5 +-#define HI3516CV300_FMC_CLK 6 +-#define HI3516CV300_MMC0_CLK 7 +-#define HI3516CV300_MMC1_CLK 8 +-#define HI3516CV300_MMC2_CLK 9 +-#define HI3516CV300_MMC3_CLK 10 +-#define HI3516CV300_ETH_CLK 11 +-#define HI3516CV300_ETH_MACIF_CLK 12 +-#define HI3516CV300_DMAC_CLK 13 +-#define HI3516CV300_PWM_CLK 14 +-#define HI3516CV300_USB2_BUS_CLK 15 +-#define HI3516CV300_USB2_OHCI48M_CLK 16 +-#define HI3516CV300_USB2_OHCI12M_CLK 17 +-#define HI3516CV300_USB2_OTG_UTMI_CLK 18 +-#define HI3516CV300_USB2_HST_PHY_CLK 19 +-#define HI3516CV300_USB2_UTMI0_CLK 20 +-#define HI3516CV300_USB2_PHY_CLK 21 +- +-/* hi3516CV300 sysctrl CRG */ +-#define HI3516CV300_WDT_CLK 1 +- +-#endif /* __DTS_HI3516CV300_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/hi3519-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/hi3519-clock.h +deleted file mode 100644 +index 43354105f629..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/hi3519-clock.h ++++ /dev/null +@@ -1,28 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. +- */ +- +-#ifndef __DTS_HI3519_CLOCK_H +-#define __DTS_HI3519_CLOCK_H +- +-#define HI3519_FMC_CLK 1 +-#define HI3519_SPI0_CLK 2 +-#define HI3519_SPI1_CLK 3 +-#define HI3519_SPI2_CLK 4 +-#define HI3519_UART0_CLK 5 +-#define HI3519_UART1_CLK 6 +-#define HI3519_UART2_CLK 7 +-#define HI3519_UART3_CLK 8 +-#define HI3519_UART4_CLK 9 +-#define HI3519_PWM_CLK 10 +-#define HI3519_DMA_CLK 11 +-#define HI3519_IR_CLK 12 +-#define HI3519_ETH_PHY_CLK 13 +-#define HI3519_ETH_MAC_CLK 14 +-#define HI3519_ETH_MACIF_CLK 15 +-#define HI3519_USB2_BUS_CLK 16 +-#define HI3519_USB2_PORT_CLK 17 +-#define HI3519_USB3_CLK 18 +- +-#endif /* __DTS_HI3519_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/hi3559av100-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/hi3559av100-clock.h +deleted file mode 100644 +index 5fe7689010a0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/hi3559av100-clock.h ++++ /dev/null +@@ -1,165 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-2-Clause */ +-/* +- * Copyright (c) 2019-2020, Huawei Tech. Co., Ltd. +- * +- * Author: Dongjiu Geng +- */ +- +-#ifndef __DTS_HI3559AV100_CLOCK_H +-#define __DTS_HI3559AV100_CLOCK_H +- +-/* fixed rate */ +-#define HI3559AV100_FIXED_1188M 1 +-#define HI3559AV100_FIXED_1000M 2 +-#define HI3559AV100_FIXED_842M 3 +-#define HI3559AV100_FIXED_792M 4 +-#define HI3559AV100_FIXED_750M 5 +-#define HI3559AV100_FIXED_710M 6 +-#define HI3559AV100_FIXED_680M 7 +-#define HI3559AV100_FIXED_667M 8 +-#define HI3559AV100_FIXED_631M 9 +-#define HI3559AV100_FIXED_600M 10 +-#define HI3559AV100_FIXED_568M 11 +-#define HI3559AV100_FIXED_500M 12 +-#define HI3559AV100_FIXED_475M 13 +-#define HI3559AV100_FIXED_428M 14 +-#define HI3559AV100_FIXED_400M 15 +-#define HI3559AV100_FIXED_396M 16 +-#define HI3559AV100_FIXED_300M 17 +-#define HI3559AV100_FIXED_250M 18 +-#define HI3559AV100_FIXED_198M 19 +-#define HI3559AV100_FIXED_187p5M 20 +-#define HI3559AV100_FIXED_150M 21 +-#define HI3559AV100_FIXED_148p5M 22 +-#define HI3559AV100_FIXED_125M 23 +-#define HI3559AV100_FIXED_107M 24 +-#define HI3559AV100_FIXED_100M 25 +-#define HI3559AV100_FIXED_99M 26 +-#define HI3559AV100_FIXED_74p25M 27 +-#define HI3559AV100_FIXED_72M 28 +-#define HI3559AV100_FIXED_60M 29 +-#define HI3559AV100_FIXED_54M 30 +-#define HI3559AV100_FIXED_50M 31 +-#define HI3559AV100_FIXED_49p5M 32 +-#define HI3559AV100_FIXED_37p125M 33 +-#define HI3559AV100_FIXED_36M 34 +-#define HI3559AV100_FIXED_32p4M 35 +-#define HI3559AV100_FIXED_27M 36 +-#define HI3559AV100_FIXED_25M 37 +-#define HI3559AV100_FIXED_24M 38 +-#define HI3559AV100_FIXED_12M 39 +-#define HI3559AV100_FIXED_3M 40 +-#define HI3559AV100_FIXED_1p6M 41 +-#define HI3559AV100_FIXED_400K 42 +-#define HI3559AV100_FIXED_100K 43 +-#define HI3559AV100_FIXED_200M 44 +-#define HI3559AV100_FIXED_75M 75 +- +-#define HI3559AV100_I2C0_CLK 50 +-#define HI3559AV100_I2C1_CLK 51 +-#define HI3559AV100_I2C2_CLK 52 +-#define HI3559AV100_I2C3_CLK 53 +-#define HI3559AV100_I2C4_CLK 54 +-#define HI3559AV100_I2C5_CLK 55 +-#define HI3559AV100_I2C6_CLK 56 +-#define HI3559AV100_I2C7_CLK 57 +-#define HI3559AV100_I2C8_CLK 58 +-#define HI3559AV100_I2C9_CLK 59 +-#define HI3559AV100_I2C10_CLK 60 +-#define HI3559AV100_I2C11_CLK 61 +- +-#define HI3559AV100_SPI0_CLK 62 +-#define HI3559AV100_SPI1_CLK 63 +-#define HI3559AV100_SPI2_CLK 64 +-#define HI3559AV100_SPI3_CLK 65 +-#define HI3559AV100_SPI4_CLK 66 +-#define HI3559AV100_SPI5_CLK 67 +-#define HI3559AV100_SPI6_CLK 68 +- +-#define HI3559AV100_EDMAC_CLK 69 +-#define HI3559AV100_EDMAC_AXICLK 70 +-#define HI3559AV100_EDMAC1_CLK 71 +-#define HI3559AV100_EDMAC1_AXICLK 72 +-#define HI3559AV100_VDMAC_CLK 73 +- +-/* mux clocks */ +-#define HI3559AV100_FMC_MUX 80 +-#define HI3559AV100_SYSAPB_MUX 81 +-#define HI3559AV100_UART_MUX 82 +-#define HI3559AV100_SYSBUS_MUX 83 +-#define HI3559AV100_A73_MUX 84 +-#define HI3559AV100_MMC0_MUX 85 +-#define HI3559AV100_MMC1_MUX 86 +-#define HI3559AV100_MMC2_MUX 87 +-#define HI3559AV100_MMC3_MUX 88 +- +-/* gate clocks */ +-#define HI3559AV100_FMC_CLK 90 +-#define HI3559AV100_UART0_CLK 91 +-#define HI3559AV100_UART1_CLK 92 +-#define HI3559AV100_UART2_CLK 93 +-#define HI3559AV100_UART3_CLK 94 +-#define HI3559AV100_UART4_CLK 95 +-#define HI3559AV100_MMC0_CLK 96 +-#define HI3559AV100_MMC1_CLK 97 +-#define HI3559AV100_MMC2_CLK 98 +-#define HI3559AV100_MMC3_CLK 99 +- +-#define HI3559AV100_ETH_CLK 100 +-#define HI3559AV100_ETH_MACIF_CLK 101 +-#define HI3559AV100_ETH1_CLK 102 +-#define HI3559AV100_ETH1_MACIF_CLK 103 +- +-/* complex */ +-#define HI3559AV100_MAC0_CLK 110 +-#define HI3559AV100_MAC1_CLK 111 +-#define HI3559AV100_SATA_CLK 112 +-#define HI3559AV100_USB_CLK 113 +-#define HI3559AV100_USB1_CLK 114 +- +-/* pll clocks */ +-#define HI3559AV100_APLL_CLK 250 +-#define HI3559AV100_GPLL_CLK 251 +- +-#define HI3559AV100_CRG_NR_CLKS 256 +- +-#define HI3559AV100_SHUB_SOURCE_SOC_24M 0 +-#define HI3559AV100_SHUB_SOURCE_SOC_200M 1 +-#define HI3559AV100_SHUB_SOURCE_SOC_300M 2 +-#define HI3559AV100_SHUB_SOURCE_PLL 3 +-#define HI3559AV100_SHUB_SOURCE_CLK 4 +- +-#define HI3559AV100_SHUB_I2C0_CLK 10 +-#define HI3559AV100_SHUB_I2C1_CLK 11 +-#define HI3559AV100_SHUB_I2C2_CLK 12 +-#define HI3559AV100_SHUB_I2C3_CLK 13 +-#define HI3559AV100_SHUB_I2C4_CLK 14 +-#define HI3559AV100_SHUB_I2C5_CLK 15 +-#define HI3559AV100_SHUB_I2C6_CLK 16 +-#define HI3559AV100_SHUB_I2C7_CLK 17 +- +-#define HI3559AV100_SHUB_SPI_SOURCE_CLK 20 +-#define HI3559AV100_SHUB_SPI4_SOURCE_CLK 21 +-#define HI3559AV100_SHUB_SPI0_CLK 22 +-#define HI3559AV100_SHUB_SPI1_CLK 23 +-#define HI3559AV100_SHUB_SPI2_CLK 24 +-#define HI3559AV100_SHUB_SPI3_CLK 25 +-#define HI3559AV100_SHUB_SPI4_CLK 26 +- +-#define HI3559AV100_SHUB_UART_CLK_32K 30 +-#define HI3559AV100_SHUB_UART_SOURCE_CLK 31 +-#define HI3559AV100_SHUB_UART_DIV_CLK 32 +-#define HI3559AV100_SHUB_UART0_CLK 33 +-#define HI3559AV100_SHUB_UART1_CLK 34 +-#define HI3559AV100_SHUB_UART2_CLK 35 +-#define HI3559AV100_SHUB_UART3_CLK 36 +-#define HI3559AV100_SHUB_UART4_CLK 37 +-#define HI3559AV100_SHUB_UART5_CLK 38 +-#define HI3559AV100_SHUB_UART6_CLK 39 +- +-#define HI3559AV100_SHUB_EDMAC_CLK 40 +- +-#define HI3559AV100_SHUB_NR_CLKS 50 +- +-#endif /* __DTS_HI3559AV100_CLOCK_H */ +- +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/hi3620-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/hi3620-clock.h +deleted file mode 100644 +index f9dc6f6d3021..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/hi3620-clock.h ++++ /dev/null +@@ -1,143 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (c) 2012-2013 Hisilicon Limited. +- * Copyright (c) 2012-2013 Linaro Limited. +- * +- * Author: Haojian Zhuang +- * Xin Li +- */ +- +-#ifndef __DTS_HI3620_CLOCK_H +-#define __DTS_HI3620_CLOCK_H +- +-#define HI3620_NONE_CLOCK 0 +- +-/* fixed rate & fixed factor clocks */ +-#define HI3620_OSC32K 1 +-#define HI3620_OSC26M 2 +-#define HI3620_PCLK 3 +-#define HI3620_PLL_ARM0 4 +-#define HI3620_PLL_ARM1 5 +-#define HI3620_PLL_PERI 6 +-#define HI3620_PLL_USB 7 +-#define HI3620_PLL_HDMI 8 +-#define HI3620_PLL_GPU 9 +-#define HI3620_RCLK_TCXO 10 +-#define HI3620_RCLK_CFGAXI 11 +-#define HI3620_RCLK_PICO 12 +- +-/* mux clocks */ +-#define HI3620_TIMER0_MUX 32 +-#define HI3620_TIMER1_MUX 33 +-#define HI3620_TIMER2_MUX 34 +-#define HI3620_TIMER3_MUX 35 +-#define HI3620_TIMER4_MUX 36 +-#define HI3620_TIMER5_MUX 37 +-#define HI3620_TIMER6_MUX 38 +-#define HI3620_TIMER7_MUX 39 +-#define HI3620_TIMER8_MUX 40 +-#define HI3620_TIMER9_MUX 41 +-#define HI3620_UART0_MUX 42 +-#define HI3620_UART1_MUX 43 +-#define HI3620_UART2_MUX 44 +-#define HI3620_UART3_MUX 45 +-#define HI3620_UART4_MUX 46 +-#define HI3620_SPI0_MUX 47 +-#define HI3620_SPI1_MUX 48 +-#define HI3620_SPI2_MUX 49 +-#define HI3620_SAXI_MUX 50 +-#define HI3620_PWM0_MUX 51 +-#define HI3620_PWM1_MUX 52 +-#define HI3620_SD_MUX 53 +-#define HI3620_MMC1_MUX 54 +-#define HI3620_MMC1_MUX2 55 +-#define HI3620_G2D_MUX 56 +-#define HI3620_VENC_MUX 57 +-#define HI3620_VDEC_MUX 58 +-#define HI3620_VPP_MUX 59 +-#define HI3620_EDC0_MUX 60 +-#define HI3620_LDI0_MUX 61 +-#define HI3620_EDC1_MUX 62 +-#define HI3620_LDI1_MUX 63 +-#define HI3620_RCLK_HSIC 64 +-#define HI3620_MMC2_MUX 65 +-#define HI3620_MMC3_MUX 66 +- +-/* divider clocks */ +-#define HI3620_SHAREAXI_DIV 128 +-#define HI3620_CFGAXI_DIV 129 +-#define HI3620_SD_DIV 130 +-#define HI3620_MMC1_DIV 131 +-#define HI3620_HSIC_DIV 132 +-#define HI3620_MMC2_DIV 133 +-#define HI3620_MMC3_DIV 134 +- +-/* gate clocks */ +-#define HI3620_TIMERCLK01 160 +-#define HI3620_TIMER_RCLK01 161 +-#define HI3620_TIMERCLK23 162 +-#define HI3620_TIMER_RCLK23 163 +-#define HI3620_TIMERCLK45 164 +-#define HI3620_TIMERCLK67 165 +-#define HI3620_TIMERCLK89 166 +-#define HI3620_RTCCLK 167 +-#define HI3620_KPC_CLK 168 +-#define HI3620_GPIOCLK0 169 +-#define HI3620_GPIOCLK1 170 +-#define HI3620_GPIOCLK2 171 +-#define HI3620_GPIOCLK3 172 +-#define HI3620_GPIOCLK4 173 +-#define HI3620_GPIOCLK5 174 +-#define HI3620_GPIOCLK6 175 +-#define HI3620_GPIOCLK7 176 +-#define HI3620_GPIOCLK8 177 +-#define HI3620_GPIOCLK9 178 +-#define HI3620_GPIOCLK10 179 +-#define HI3620_GPIOCLK11 180 +-#define HI3620_GPIOCLK12 181 +-#define HI3620_GPIOCLK13 182 +-#define HI3620_GPIOCLK14 183 +-#define HI3620_GPIOCLK15 184 +-#define HI3620_GPIOCLK16 185 +-#define HI3620_GPIOCLK17 186 +-#define HI3620_GPIOCLK18 187 +-#define HI3620_GPIOCLK19 188 +-#define HI3620_GPIOCLK20 189 +-#define HI3620_GPIOCLK21 190 +-#define HI3620_DPHY0_CLK 191 +-#define HI3620_DPHY1_CLK 192 +-#define HI3620_DPHY2_CLK 193 +-#define HI3620_USBPHY_CLK 194 +-#define HI3620_ACP_CLK 195 +-#define HI3620_PWMCLK0 196 +-#define HI3620_PWMCLK1 197 +-#define HI3620_UARTCLK0 198 +-#define HI3620_UARTCLK1 199 +-#define HI3620_UARTCLK2 200 +-#define HI3620_UARTCLK3 201 +-#define HI3620_UARTCLK4 202 +-#define HI3620_SPICLK0 203 +-#define HI3620_SPICLK1 204 +-#define HI3620_SPICLK2 205 +-#define HI3620_I2CCLK0 206 +-#define HI3620_I2CCLK1 207 +-#define HI3620_I2CCLK2 208 +-#define HI3620_I2CCLK3 209 +-#define HI3620_SCI_CLK 210 +-#define HI3620_DDRC_PER_CLK 211 +-#define HI3620_DMAC_CLK 212 +-#define HI3620_USB2DVC_CLK 213 +-#define HI3620_SD_CLK 214 +-#define HI3620_MMC_CLK1 215 +-#define HI3620_MMC_CLK2 216 +-#define HI3620_MMC_CLK3 217 +-#define HI3620_MCU_CLK 218 +- +-#define HI3620_SD_CIUCLK 0 +-#define HI3620_MMC_CIUCLK1 1 +-#define HI3620_MMC_CIUCLK2 2 +-#define HI3620_MMC_CIUCLK3 3 +- +-#define HI3620_NR_CLKS 219 +- +-#endif /* __DTS_HI3620_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/hi3660-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/hi3660-clock.h +deleted file mode 100644 +index e1374e180943..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/hi3660-clock.h ++++ /dev/null +@@ -1,214 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (c) 2016-2017 Linaro Ltd. +- * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. +- */ +- +-#ifndef __DTS_HI3660_CLOCK_H +-#define __DTS_HI3660_CLOCK_H +- +-/* fixed rate clocks */ +-#define HI3660_CLKIN_SYS 0 +-#define HI3660_CLKIN_REF 1 +-#define HI3660_CLK_FLL_SRC 2 +-#define HI3660_CLK_PPLL0 3 +-#define HI3660_CLK_PPLL1 4 +-#define HI3660_CLK_PPLL2 5 +-#define HI3660_CLK_PPLL3 6 +-#define HI3660_CLK_SCPLL 7 +-#define HI3660_PCLK 8 +-#define HI3660_CLK_UART0_DBG 9 +-#define HI3660_CLK_UART6 10 +-#define HI3660_OSC32K 11 +-#define HI3660_OSC19M 12 +-#define HI3660_CLK_480M 13 +-#define HI3660_CLK_INV 14 +- +-/* clk in crgctrl */ +-#define HI3660_FACTOR_UART3 15 +-#define HI3660_CLK_FACTOR_MMC 16 +-#define HI3660_CLK_GATE_I2C0 17 +-#define HI3660_CLK_GATE_I2C1 18 +-#define HI3660_CLK_GATE_I2C2 19 +-#define HI3660_CLK_GATE_I2C6 20 +-#define HI3660_CLK_DIV_SYSBUS 21 +-#define HI3660_CLK_DIV_320M 22 +-#define HI3660_CLK_DIV_A53 23 +-#define HI3660_CLK_GATE_SPI0 24 +-#define HI3660_CLK_GATE_SPI2 25 +-#define HI3660_PCIEPHY_REF 26 +-#define HI3660_CLK_ABB_USB 27 +-#define HI3660_HCLK_GATE_SDIO0 28 +-#define HI3660_HCLK_GATE_SD 29 +-#define HI3660_CLK_GATE_AOMM 30 +-#define HI3660_PCLK_GPIO0 31 +-#define HI3660_PCLK_GPIO1 32 +-#define HI3660_PCLK_GPIO2 33 +-#define HI3660_PCLK_GPIO3 34 +-#define HI3660_PCLK_GPIO4 35 +-#define HI3660_PCLK_GPIO5 36 +-#define HI3660_PCLK_GPIO6 37 +-#define HI3660_PCLK_GPIO7 38 +-#define HI3660_PCLK_GPIO8 39 +-#define HI3660_PCLK_GPIO9 40 +-#define HI3660_PCLK_GPIO10 41 +-#define HI3660_PCLK_GPIO11 42 +-#define HI3660_PCLK_GPIO12 43 +-#define HI3660_PCLK_GPIO13 44 +-#define HI3660_PCLK_GPIO14 45 +-#define HI3660_PCLK_GPIO15 46 +-#define HI3660_PCLK_GPIO16 47 +-#define HI3660_PCLK_GPIO17 48 +-#define HI3660_PCLK_GPIO18 49 +-#define HI3660_PCLK_GPIO19 50 +-#define HI3660_PCLK_GPIO20 51 +-#define HI3660_PCLK_GPIO21 52 +-#define HI3660_CLK_GATE_SPI3 53 +-#define HI3660_CLK_GATE_I2C7 54 +-#define HI3660_CLK_GATE_I2C3 55 +-#define HI3660_CLK_GATE_SPI1 56 +-#define HI3660_CLK_GATE_UART1 57 +-#define HI3660_CLK_GATE_UART2 58 +-#define HI3660_CLK_GATE_UART4 59 +-#define HI3660_CLK_GATE_UART5 60 +-#define HI3660_CLK_GATE_I2C4 61 +-#define HI3660_CLK_GATE_DMAC 62 +-#define HI3660_PCLK_GATE_DSS 63 +-#define HI3660_ACLK_GATE_DSS 64 +-#define HI3660_CLK_GATE_LDI1 65 +-#define HI3660_CLK_GATE_LDI0 66 +-#define HI3660_CLK_GATE_VIVOBUS 67 +-#define HI3660_CLK_GATE_EDC0 68 +-#define HI3660_CLK_GATE_TXDPHY0_CFG 69 +-#define HI3660_CLK_GATE_TXDPHY0_REF 70 +-#define HI3660_CLK_GATE_TXDPHY1_CFG 71 +-#define HI3660_CLK_GATE_TXDPHY1_REF 72 +-#define HI3660_ACLK_GATE_USB3OTG 73 +-#define HI3660_CLK_GATE_SPI4 74 +-#define HI3660_CLK_GATE_SD 75 +-#define HI3660_CLK_GATE_SDIO0 76 +-#define HI3660_CLK_GATE_UFS_SUBSYS 77 +-#define HI3660_PCLK_GATE_DSI0 78 +-#define HI3660_PCLK_GATE_DSI1 79 +-#define HI3660_ACLK_GATE_PCIE 80 +-#define HI3660_PCLK_GATE_PCIE_SYS 81 +-#define HI3660_CLK_GATE_PCIEAUX 82 +-#define HI3660_PCLK_GATE_PCIE_PHY 83 +-#define HI3660_CLK_ANDGT_LDI0 84 +-#define HI3660_CLK_ANDGT_LDI1 85 +-#define HI3660_CLK_ANDGT_EDC0 86 +-#define HI3660_CLK_GATE_UFSPHY_GT 87 +-#define HI3660_CLK_ANDGT_MMC 88 +-#define HI3660_CLK_ANDGT_SD 89 +-#define HI3660_CLK_A53HPM_ANDGT 90 +-#define HI3660_CLK_ANDGT_SDIO 91 +-#define HI3660_CLK_ANDGT_UART0 92 +-#define HI3660_CLK_ANDGT_UART1 93 +-#define HI3660_CLK_ANDGT_UARTH 94 +-#define HI3660_CLK_ANDGT_SPI 95 +-#define HI3660_CLK_VIVOBUS_ANDGT 96 +-#define HI3660_CLK_AOMM_ANDGT 97 +-#define HI3660_CLK_320M_PLL_GT 98 +-#define HI3660_AUTODIV_EMMC0BUS 99 +-#define HI3660_AUTODIV_SYSBUS 100 +-#define HI3660_CLK_GATE_UFSPHY_CFG 101 +-#define HI3660_CLK_GATE_UFSIO_REF 102 +-#define HI3660_CLK_MUX_SYSBUS 103 +-#define HI3660_CLK_MUX_UART0 104 +-#define HI3660_CLK_MUX_UART1 105 +-#define HI3660_CLK_MUX_UARTH 106 +-#define HI3660_CLK_MUX_SPI 107 +-#define HI3660_CLK_MUX_I2C 108 +-#define HI3660_CLK_MUX_MMC_PLL 109 +-#define HI3660_CLK_MUX_LDI1 110 +-#define HI3660_CLK_MUX_LDI0 111 +-#define HI3660_CLK_MUX_SD_PLL 112 +-#define HI3660_CLK_MUX_SD_SYS 113 +-#define HI3660_CLK_MUX_EDC0 114 +-#define HI3660_CLK_MUX_SDIO_SYS 115 +-#define HI3660_CLK_MUX_SDIO_PLL 116 +-#define HI3660_CLK_MUX_VIVOBUS 117 +-#define HI3660_CLK_MUX_A53HPM 118 +-#define HI3660_CLK_MUX_320M 119 +-#define HI3660_CLK_MUX_IOPERI 120 +-#define HI3660_CLK_DIV_UART0 121 +-#define HI3660_CLK_DIV_UART1 122 +-#define HI3660_CLK_DIV_UARTH 123 +-#define HI3660_CLK_DIV_MMC 124 +-#define HI3660_CLK_DIV_SD 125 +-#define HI3660_CLK_DIV_EDC0 126 +-#define HI3660_CLK_DIV_LDI0 127 +-#define HI3660_CLK_DIV_SDIO 128 +-#define HI3660_CLK_DIV_LDI1 129 +-#define HI3660_CLK_DIV_SPI 130 +-#define HI3660_CLK_DIV_VIVOBUS 131 +-#define HI3660_CLK_DIV_I2C 132 +-#define HI3660_CLK_DIV_UFSPHY 133 +-#define HI3660_CLK_DIV_CFGBUS 134 +-#define HI3660_CLK_DIV_MMC0BUS 135 +-#define HI3660_CLK_DIV_MMC1BUS 136 +-#define HI3660_CLK_DIV_UFSPERI 137 +-#define HI3660_CLK_DIV_AOMM 138 +-#define HI3660_CLK_DIV_IOPERI 139 +-#define HI3660_VENC_VOLT_HOLD 140 +-#define HI3660_PERI_VOLT_HOLD 141 +-#define HI3660_CLK_GATE_VENC 142 +-#define HI3660_CLK_GATE_VDEC 143 +-#define HI3660_CLK_ANDGT_VENC 144 +-#define HI3660_CLK_ANDGT_VDEC 145 +-#define HI3660_CLK_MUX_VENC 146 +-#define HI3660_CLK_MUX_VDEC 147 +-#define HI3660_CLK_DIV_VENC 148 +-#define HI3660_CLK_DIV_VDEC 149 +-#define HI3660_CLK_FAC_ISP_SNCLK 150 +-#define HI3660_CLK_GATE_ISP_SNCLK0 151 +-#define HI3660_CLK_GATE_ISP_SNCLK1 152 +-#define HI3660_CLK_GATE_ISP_SNCLK2 153 +-#define HI3660_CLK_ANGT_ISP_SNCLK 154 +-#define HI3660_CLK_MUX_ISP_SNCLK 155 +-#define HI3660_CLK_DIV_ISP_SNCLK 156 +- +-/* clk in pmuctrl */ +-#define HI3660_GATE_ABB_192 0 +- +-/* clk in pctrl */ +-#define HI3660_GATE_UFS_TCXO_EN 0 +-#define HI3660_GATE_USB_TCXO_EN 1 +- +-/* clk in sctrl */ +-#define HI3660_PCLK_AO_GPIO0 0 +-#define HI3660_PCLK_AO_GPIO1 1 +-#define HI3660_PCLK_AO_GPIO2 2 +-#define HI3660_PCLK_AO_GPIO3 3 +-#define HI3660_PCLK_AO_GPIO4 4 +-#define HI3660_PCLK_AO_GPIO5 5 +-#define HI3660_PCLK_AO_GPIO6 6 +-#define HI3660_PCLK_GATE_MMBUF 7 +-#define HI3660_CLK_GATE_DSS_AXI_MM 8 +-#define HI3660_PCLK_MMBUF_ANDGT 9 +-#define HI3660_CLK_MMBUF_PLL_ANDGT 10 +-#define HI3660_CLK_FLL_MMBUF_ANDGT 11 +-#define HI3660_CLK_SYS_MMBUF_ANDGT 12 +-#define HI3660_CLK_GATE_PCIEPHY_GT 13 +-#define HI3660_ACLK_MUX_MMBUF 14 +-#define HI3660_CLK_SW_MMBUF 15 +-#define HI3660_CLK_DIV_AOBUS 16 +-#define HI3660_PCLK_DIV_MMBUF 17 +-#define HI3660_ACLK_DIV_MMBUF 18 +-#define HI3660_CLK_DIV_PCIEPHY 19 +- +-/* clk in iomcu */ +-#define HI3660_CLK_I2C0_IOMCU 0 +-#define HI3660_CLK_I2C1_IOMCU 1 +-#define HI3660_CLK_I2C2_IOMCU 2 +-#define HI3660_CLK_I2C6_IOMCU 3 +-#define HI3660_CLK_IOMCU_PERI0 4 +- +-/* clk in stub clock */ +-#define HI3660_CLK_STUB_CLUSTER0 0 +-#define HI3660_CLK_STUB_CLUSTER1 1 +-#define HI3660_CLK_STUB_GPU 2 +-#define HI3660_CLK_STUB_DDR 3 +-#define HI3660_CLK_STUB_NUM 4 +- +-#endif /* __DTS_HI3660_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/hi3670-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/hi3670-clock.h +deleted file mode 100644 +index fa48583f87d6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/hi3670-clock.h ++++ /dev/null +@@ -1,348 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Device Tree binding constants for HiSilicon Hi3670 SoC +- * +- * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd. +- * Copyright (c) 2018 Linaro Ltd. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_HI3670_H +-#define __DT_BINDINGS_CLOCK_HI3670_H +- +-/* clk in stub clock */ +-#define HI3670_CLK_STUB_CLUSTER0 0 +-#define HI3670_CLK_STUB_CLUSTER1 1 +-#define HI3670_CLK_STUB_GPU 2 +-#define HI3670_CLK_STUB_DDR 3 +-#define HI3670_CLK_STUB_DDR_VOTE 4 +-#define HI3670_CLK_STUB_DDR_LIMIT 5 +-#define HI3670_CLK_STUB_NUM 6 +- +-/* clk in crg clock */ +-#define HI3670_CLKIN_SYS 0 +-#define HI3670_CLKIN_REF 1 +-#define HI3670_CLK_FLL_SRC 2 +-#define HI3670_CLK_PPLL0 3 +-#define HI3670_CLK_PPLL1 4 +-#define HI3670_CLK_PPLL2 5 +-#define HI3670_CLK_PPLL3 6 +-#define HI3670_CLK_PPLL4 7 +-#define HI3670_CLK_PPLL6 8 +-#define HI3670_CLK_PPLL7 9 +-#define HI3670_CLK_PPLL_PCIE 10 +-#define HI3670_CLK_PCIEPLL_REV 11 +-#define HI3670_CLK_SCPLL 12 +-#define HI3670_PCLK 13 +-#define HI3670_CLK_UART0_DBG 14 +-#define HI3670_CLK_UART6 15 +-#define HI3670_OSC32K 16 +-#define HI3670_OSC19M 17 +-#define HI3670_CLK_480M 18 +-#define HI3670_CLK_INVALID 19 +-#define HI3670_CLK_DIV_SYSBUS 20 +-#define HI3670_CLK_FACTOR_MMC 21 +-#define HI3670_CLK_SD_SYS 22 +-#define HI3670_CLK_SDIO_SYS 23 +-#define HI3670_CLK_DIV_A53HPM 24 +-#define HI3670_CLK_DIV_320M 25 +-#define HI3670_PCLK_GATE_UART0 26 +-#define HI3670_CLK_FACTOR_UART0 27 +-#define HI3670_CLK_FACTOR_USB3PHY_PLL 28 +-#define HI3670_CLK_GATE_ABB_USB 29 +-#define HI3670_CLK_GATE_UFSPHY_REF 30 +-#define HI3670_ICS_VOLT_HIGH 31 +-#define HI3670_ICS_VOLT_MIDDLE 32 +-#define HI3670_VENC_VOLT_HOLD 33 +-#define HI3670_VDEC_VOLT_HOLD 34 +-#define HI3670_EDC_VOLT_HOLD 35 +-#define HI3670_CLK_ISP_SNCLK_FAC 36 +-#define HI3670_CLK_FACTOR_RXDPHY 37 +-#define HI3670_AUTODIV_SYSBUS 38 +-#define HI3670_AUTODIV_EMMC0BUS 39 +-#define HI3670_PCLK_ANDGT_MMC1_PCIE 40 +-#define HI3670_CLK_GATE_VCODECBUS_GT 41 +-#define HI3670_CLK_ANDGT_SD 42 +-#define HI3670_CLK_SD_SYS_GT 43 +-#define HI3670_CLK_ANDGT_SDIO 44 +-#define HI3670_CLK_SDIO_SYS_GT 45 +-#define HI3670_CLK_A53HPM_ANDGT 46 +-#define HI3670_CLK_320M_PLL_GT 47 +-#define HI3670_CLK_ANDGT_UARTH 48 +-#define HI3670_CLK_ANDGT_UARTL 49 +-#define HI3670_CLK_ANDGT_UART0 50 +-#define HI3670_CLK_ANDGT_SPI 51 +-#define HI3670_CLK_ANDGT_PCIEAXI 52 +-#define HI3670_CLK_DIV_AO_ASP_GT 53 +-#define HI3670_CLK_GATE_CSI_TRANS 54 +-#define HI3670_CLK_GATE_DSI_TRANS 55 +-#define HI3670_CLK_ANDGT_PTP 56 +-#define HI3670_CLK_ANDGT_OUT0 57 +-#define HI3670_CLK_ANDGT_OUT1 58 +-#define HI3670_CLKGT_DP_AUDIO_PLL_AO 59 +-#define HI3670_CLK_ANDGT_VDEC 60 +-#define HI3670_CLK_ANDGT_VENC 61 +-#define HI3670_CLK_ISP_SNCLK_ANGT 62 +-#define HI3670_CLK_ANDGT_RXDPHY 63 +-#define HI3670_CLK_ANDGT_ICS 64 +-#define HI3670_AUTODIV_DMABUS 65 +-#define HI3670_CLK_MUX_SYSBUS 66 +-#define HI3670_CLK_MUX_VCODECBUS 67 +-#define HI3670_CLK_MUX_SD_SYS 68 +-#define HI3670_CLK_MUX_SD_PLL 69 +-#define HI3670_CLK_MUX_SDIO_SYS 70 +-#define HI3670_CLK_MUX_SDIO_PLL 71 +-#define HI3670_CLK_MUX_A53HPM 72 +-#define HI3670_CLK_MUX_320M 73 +-#define HI3670_CLK_MUX_UARTH 74 +-#define HI3670_CLK_MUX_UARTL 75 +-#define HI3670_CLK_MUX_UART0 76 +-#define HI3670_CLK_MUX_I2C 77 +-#define HI3670_CLK_MUX_SPI 78 +-#define HI3670_CLK_MUX_PCIEAXI 79 +-#define HI3670_CLK_MUX_AO_ASP 80 +-#define HI3670_CLK_MUX_VDEC 81 +-#define HI3670_CLK_MUX_VENC 82 +-#define HI3670_CLK_ISP_SNCLK_MUX0 83 +-#define HI3670_CLK_ISP_SNCLK_MUX1 84 +-#define HI3670_CLK_ISP_SNCLK_MUX2 85 +-#define HI3670_CLK_MUX_RXDPHY_CFG 86 +-#define HI3670_CLK_MUX_ICS 87 +-#define HI3670_CLK_DIV_CFGBUS 88 +-#define HI3670_CLK_DIV_MMC0BUS 89 +-#define HI3670_CLK_DIV_MMC1BUS 90 +-#define HI3670_PCLK_DIV_MMC1_PCIE 91 +-#define HI3670_CLK_DIV_VCODECBUS 92 +-#define HI3670_CLK_DIV_SD 93 +-#define HI3670_CLK_DIV_SDIO 94 +-#define HI3670_CLK_DIV_UARTH 95 +-#define HI3670_CLK_DIV_UARTL 96 +-#define HI3670_CLK_DIV_UART0 97 +-#define HI3670_CLK_DIV_I2C 98 +-#define HI3670_CLK_DIV_SPI 99 +-#define HI3670_CLK_DIV_PCIEAXI 100 +-#define HI3670_CLK_DIV_AO_ASP 101 +-#define HI3670_CLK_DIV_CSI_TRANS 102 +-#define HI3670_CLK_DIV_DSI_TRANS 103 +-#define HI3670_CLK_DIV_PTP 104 +-#define HI3670_CLK_DIV_CLKOUT0_PLL 105 +-#define HI3670_CLK_DIV_CLKOUT1_PLL 106 +-#define HI3670_CLKDIV_DP_AUDIO_PLL_AO 107 +-#define HI3670_CLK_DIV_VDEC 108 +-#define HI3670_CLK_DIV_VENC 109 +-#define HI3670_CLK_ISP_SNCLK_DIV0 110 +-#define HI3670_CLK_ISP_SNCLK_DIV1 111 +-#define HI3670_CLK_ISP_SNCLK_DIV2 112 +-#define HI3670_CLK_DIV_ICS 113 +-#define HI3670_PPLL1_EN_ACPU 114 +-#define HI3670_PPLL2_EN_ACPU 115 +-#define HI3670_PPLL3_EN_ACPU 116 +-#define HI3670_PPLL1_GT_CPU 117 +-#define HI3670_PPLL2_GT_CPU 118 +-#define HI3670_PPLL3_GT_CPU 119 +-#define HI3670_CLK_GATE_PPLL2_MEDIA 120 +-#define HI3670_CLK_GATE_PPLL3_MEDIA 121 +-#define HI3670_CLK_GATE_PPLL4_MEDIA 122 +-#define HI3670_CLK_GATE_PPLL6_MEDIA 123 +-#define HI3670_CLK_GATE_PPLL7_MEDIA 124 +-#define HI3670_PCLK_GPIO0 125 +-#define HI3670_PCLK_GPIO1 126 +-#define HI3670_PCLK_GPIO2 127 +-#define HI3670_PCLK_GPIO3 128 +-#define HI3670_PCLK_GPIO4 129 +-#define HI3670_PCLK_GPIO5 130 +-#define HI3670_PCLK_GPIO6 131 +-#define HI3670_PCLK_GPIO7 132 +-#define HI3670_PCLK_GPIO8 133 +-#define HI3670_PCLK_GPIO9 134 +-#define HI3670_PCLK_GPIO10 135 +-#define HI3670_PCLK_GPIO11 136 +-#define HI3670_PCLK_GPIO12 137 +-#define HI3670_PCLK_GPIO13 138 +-#define HI3670_PCLK_GPIO14 139 +-#define HI3670_PCLK_GPIO15 140 +-#define HI3670_PCLK_GPIO16 141 +-#define HI3670_PCLK_GPIO17 142 +-#define HI3670_PCLK_GPIO20 143 +-#define HI3670_PCLK_GPIO21 144 +-#define HI3670_PCLK_GATE_DSI0 145 +-#define HI3670_PCLK_GATE_DSI1 146 +-#define HI3670_HCLK_GATE_USB3OTG 147 +-#define HI3670_ACLK_GATE_USB3DVFS 148 +-#define HI3670_HCLK_GATE_SDIO 149 +-#define HI3670_PCLK_GATE_PCIE_SYS 150 +-#define HI3670_PCLK_GATE_PCIE_PHY 151 +-#define HI3670_PCLK_GATE_MMC1_PCIE 152 +-#define HI3670_PCLK_GATE_MMC0_IOC 153 +-#define HI3670_PCLK_GATE_MMC1_IOC 154 +-#define HI3670_CLK_GATE_DMAC 155 +-#define HI3670_CLK_GATE_VCODECBUS2DDR 156 +-#define HI3670_CLK_CCI400_BYPASS 157 +-#define HI3670_CLK_GATE_CCI400 158 +-#define HI3670_CLK_GATE_SD 159 +-#define HI3670_HCLK_GATE_SD 160 +-#define HI3670_CLK_GATE_SDIO 161 +-#define HI3670_CLK_GATE_A57HPM 162 +-#define HI3670_CLK_GATE_A53HPM 163 +-#define HI3670_CLK_GATE_PA_A53 164 +-#define HI3670_CLK_GATE_PA_A57 165 +-#define HI3670_CLK_GATE_PA_G3D 166 +-#define HI3670_CLK_GATE_GPUHPM 167 +-#define HI3670_CLK_GATE_PERIHPM 168 +-#define HI3670_CLK_GATE_AOHPM 169 +-#define HI3670_CLK_GATE_UART1 170 +-#define HI3670_CLK_GATE_UART4 171 +-#define HI3670_PCLK_GATE_UART1 172 +-#define HI3670_PCLK_GATE_UART4 173 +-#define HI3670_CLK_GATE_UART2 174 +-#define HI3670_CLK_GATE_UART5 175 +-#define HI3670_PCLK_GATE_UART2 176 +-#define HI3670_PCLK_GATE_UART5 177 +-#define HI3670_CLK_GATE_UART0 178 +-#define HI3670_CLK_GATE_I2C3 179 +-#define HI3670_CLK_GATE_I2C4 180 +-#define HI3670_CLK_GATE_I2C7 181 +-#define HI3670_PCLK_GATE_I2C3 182 +-#define HI3670_PCLK_GATE_I2C4 183 +-#define HI3670_PCLK_GATE_I2C7 184 +-#define HI3670_CLK_GATE_SPI1 185 +-#define HI3670_CLK_GATE_SPI4 186 +-#define HI3670_PCLK_GATE_SPI1 187 +-#define HI3670_PCLK_GATE_SPI4 188 +-#define HI3670_CLK_GATE_USB3OTG_REF 189 +-#define HI3670_CLK_GATE_USB2PHY_REF 190 +-#define HI3670_CLK_GATE_PCIEAUX 191 +-#define HI3670_ACLK_GATE_PCIE 192 +-#define HI3670_CLK_GATE_MMC1_PCIEAXI 193 +-#define HI3670_CLK_GATE_PCIEPHY_REF 194 +-#define HI3670_CLK_GATE_PCIE_DEBOUNCE 195 +-#define HI3670_CLK_GATE_PCIEIO 196 +-#define HI3670_CLK_GATE_PCIE_HP 197 +-#define HI3670_CLK_GATE_AO_ASP 198 +-#define HI3670_PCLK_GATE_PCTRL 199 +-#define HI3670_CLK_CSI_TRANS_GT 200 +-#define HI3670_CLK_DSI_TRANS_GT 201 +-#define HI3670_CLK_GATE_PWM 202 +-#define HI3670_ABB_AUDIO_EN0 203 +-#define HI3670_ABB_AUDIO_EN1 204 +-#define HI3670_ABB_AUDIO_GT_EN0 205 +-#define HI3670_ABB_AUDIO_GT_EN1 206 +-#define HI3670_CLK_GATE_DP_AUDIO_PLL_AO 207 +-#define HI3670_PERI_VOLT_HOLD 208 +-#define HI3670_PERI_VOLT_MIDDLE 209 +-#define HI3670_CLK_GATE_ISP_SNCLK0 210 +-#define HI3670_CLK_GATE_ISP_SNCLK1 211 +-#define HI3670_CLK_GATE_ISP_SNCLK2 212 +-#define HI3670_CLK_GATE_RXDPHY0_CFG 213 +-#define HI3670_CLK_GATE_RXDPHY1_CFG 214 +-#define HI3670_CLK_GATE_RXDPHY2_CFG 215 +-#define HI3670_CLK_GATE_TXDPHY0_CFG 216 +-#define HI3670_CLK_GATE_TXDPHY0_REF 217 +-#define HI3670_CLK_GATE_TXDPHY1_CFG 218 +-#define HI3670_CLK_GATE_TXDPHY1_REF 219 +-#define HI3670_CLK_GATE_MEDIA_TCXO 220 +- +-/* clk in sctrl */ +-#define HI3670_CLK_ANDGT_IOPERI 0 +-#define HI3670_CLKANDGT_ASP_SUBSYS_PERI 1 +-#define HI3670_CLK_ANGT_ASP_SUBSYS 2 +-#define HI3670_CLK_MUX_UFS_SUBSYS 3 +-#define HI3670_CLK_MUX_CLKOUT0 4 +-#define HI3670_CLK_MUX_CLKOUT1 5 +-#define HI3670_CLK_MUX_ASP_SUBSYS_PERI 6 +-#define HI3670_CLK_MUX_ASP_PLL 7 +-#define HI3670_CLK_DIV_AOBUS 8 +-#define HI3670_CLK_DIV_UFS_SUBSYS 9 +-#define HI3670_CLK_DIV_IOPERI 10 +-#define HI3670_CLK_DIV_CLKOUT0_TCXO 11 +-#define HI3670_CLK_DIV_CLKOUT1_TCXO 12 +-#define HI3670_CLK_ASP_SUBSYS_PERI_DIV 13 +-#define HI3670_CLK_DIV_ASP_SUBSYS 14 +-#define HI3670_PPLL0_EN_ACPU 15 +-#define HI3670_PPLL0_GT_CPU 16 +-#define HI3670_CLK_GATE_PPLL0_MEDIA 17 +-#define HI3670_PCLK_GPIO18 18 +-#define HI3670_PCLK_GPIO19 19 +-#define HI3670_CLK_GATE_SPI 20 +-#define HI3670_PCLK_GATE_SPI 21 +-#define HI3670_CLK_GATE_UFS_SUBSYS 22 +-#define HI3670_CLK_GATE_UFSIO_REF 23 +-#define HI3670_PCLK_AO_GPIO0 24 +-#define HI3670_PCLK_AO_GPIO1 25 +-#define HI3670_PCLK_AO_GPIO2 26 +-#define HI3670_PCLK_AO_GPIO3 27 +-#define HI3670_PCLK_AO_GPIO4 28 +-#define HI3670_PCLK_AO_GPIO5 29 +-#define HI3670_PCLK_AO_GPIO6 30 +-#define HI3670_CLK_GATE_OUT0 31 +-#define HI3670_CLK_GATE_OUT1 32 +-#define HI3670_PCLK_GATE_SYSCNT 33 +-#define HI3670_CLK_GATE_SYSCNT 34 +-#define HI3670_CLK_GATE_ASP_SUBSYS_PERI 35 +-#define HI3670_CLK_GATE_ASP_SUBSYS 36 +-#define HI3670_CLK_GATE_ASP_TCXO 37 +-#define HI3670_CLK_GATE_DP_AUDIO_PLL 38 +- +-/* clk in pmuctrl */ +-#define HI3670_GATE_ABB_192 0 +- +-/* clk in pctrl */ +-#define HI3670_GATE_UFS_TCXO_EN 0 +-#define HI3670_GATE_USB_TCXO_EN 1 +- +-/* clk in iomcu */ +-#define HI3670_CLK_GATE_I2C0 0 +-#define HI3670_CLK_GATE_I2C1 1 +-#define HI3670_CLK_GATE_I2C2 2 +-#define HI3670_CLK_GATE_SPI0 3 +-#define HI3670_CLK_GATE_SPI2 4 +-#define HI3670_CLK_GATE_UART3 5 +-#define HI3670_CLK_I2C0_GATE_IOMCU 6 +-#define HI3670_CLK_I2C1_GATE_IOMCU 7 +-#define HI3670_CLK_I2C2_GATE_IOMCU 8 +-#define HI3670_CLK_SPI0_GATE_IOMCU 9 +-#define HI3670_CLK_SPI2_GATE_IOMCU 10 +-#define HI3670_CLK_UART3_GATE_IOMCU 11 +-#define HI3670_CLK_GATE_PERI0_IOMCU 12 +- +-/* clk in media1 */ +-#define HI3670_CLK_GATE_VIVOBUS_ANDGT 0 +-#define HI3670_CLK_ANDGT_EDC0 1 +-#define HI3670_CLK_ANDGT_LDI0 2 +-#define HI3670_CLK_ANDGT_LDI1 3 +-#define HI3670_CLK_MMBUF_PLL_ANDGT 4 +-#define HI3670_PCLK_MMBUF_ANDGT 5 +-#define HI3670_CLK_MUX_VIVOBUS 6 +-#define HI3670_CLK_MUX_EDC0 7 +-#define HI3670_CLK_MUX_LDI0 8 +-#define HI3670_CLK_MUX_LDI1 9 +-#define HI3670_CLK_SW_MMBUF 10 +-#define HI3670_CLK_DIV_VIVOBUS 11 +-#define HI3670_CLK_DIV_EDC0 12 +-#define HI3670_CLK_DIV_LDI0 13 +-#define HI3670_CLK_DIV_LDI1 14 +-#define HI3670_ACLK_DIV_MMBUF 15 +-#define HI3670_PCLK_DIV_MMBUF 16 +-#define HI3670_ACLK_GATE_NOC_DSS 17 +-#define HI3670_PCLK_GATE_NOC_DSS_CFG 18 +-#define HI3670_PCLK_GATE_MMBUF_CFG 19 +-#define HI3670_PCLK_GATE_DISP_NOC_SUBSYS 20 +-#define HI3670_ACLK_GATE_DISP_NOC_SUBSYS 21 +-#define HI3670_PCLK_GATE_DSS 22 +-#define HI3670_ACLK_GATE_DSS 23 +-#define HI3670_CLK_GATE_VIVOBUSFREQ 24 +-#define HI3670_CLK_GATE_EDC0 25 +-#define HI3670_CLK_GATE_LDI0 26 +-#define HI3670_CLK_GATE_LDI1FREQ 27 +-#define HI3670_CLK_GATE_BRG 28 +-#define HI3670_ACLK_GATE_ASC 29 +-#define HI3670_CLK_GATE_DSS_AXI_MM 30 +-#define HI3670_CLK_GATE_MMBUF 31 +-#define HI3670_PCLK_GATE_MMBUF 32 +-#define HI3670_CLK_GATE_ATDIV_VIVO 33 +- +-/* clk in media2 */ +-#define HI3670_CLK_GATE_VDECFREQ 0 +-#define HI3670_CLK_GATE_VENCFREQ 1 +-#define HI3670_CLK_GATE_ICSFREQ 2 +- +-#endif /* __DT_BINDINGS_CLOCK_HI3670_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/hi6220-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/hi6220-clock.h +deleted file mode 100644 +index 9e40605e6140..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/hi6220-clock.h ++++ /dev/null +@@ -1,178 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2015 Hisilicon Limited. +- * +- * Author: Bintian Wang +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_HI6220_H +-#define __DT_BINDINGS_CLOCK_HI6220_H +- +-/* clk in Hi6220 AO (always on) controller */ +-#define HI6220_NONE_CLOCK 0 +- +-/* fixed rate clocks */ +-#define HI6220_REF32K 1 +-#define HI6220_CLK_TCXO 2 +-#define HI6220_MMC1_PAD 3 +-#define HI6220_MMC2_PAD 4 +-#define HI6220_MMC0_PAD 5 +-#define HI6220_PLL_BBP 6 +-#define HI6220_PLL_GPU 7 +-#define HI6220_PLL1_DDR 8 +-#define HI6220_PLL_SYS 9 +-#define HI6220_PLL_SYS_MEDIA 10 +-#define HI6220_DDR_SRC 11 +-#define HI6220_PLL_MEDIA 12 +-#define HI6220_PLL_DDR 13 +- +-/* fixed factor clocks */ +-#define HI6220_300M 14 +-#define HI6220_150M 15 +-#define HI6220_PICOPHY_SRC 16 +-#define HI6220_MMC0_SRC_SEL 17 +-#define HI6220_MMC1_SRC_SEL 18 +-#define HI6220_MMC2_SRC_SEL 19 +-#define HI6220_VPU_CODEC 20 +-#define HI6220_MMC0_SMP 21 +-#define HI6220_MMC1_SMP 22 +-#define HI6220_MMC2_SMP 23 +- +-/* gate clocks */ +-#define HI6220_WDT0_PCLK 24 +-#define HI6220_WDT1_PCLK 25 +-#define HI6220_WDT2_PCLK 26 +-#define HI6220_TIMER0_PCLK 27 +-#define HI6220_TIMER1_PCLK 28 +-#define HI6220_TIMER2_PCLK 29 +-#define HI6220_TIMER3_PCLK 30 +-#define HI6220_TIMER4_PCLK 31 +-#define HI6220_TIMER5_PCLK 32 +-#define HI6220_TIMER6_PCLK 33 +-#define HI6220_TIMER7_PCLK 34 +-#define HI6220_TIMER8_PCLK 35 +-#define HI6220_UART0_PCLK 36 +-#define HI6220_RTC0_PCLK 37 +-#define HI6220_RTC1_PCLK 38 +-#define HI6220_AO_NR_CLKS 39 +- +-/* clk in Hi6220 systrl */ +-/* gate clock */ +-#define HI6220_MMC0_CLK 1 +-#define HI6220_MMC0_CIUCLK 2 +-#define HI6220_MMC1_CLK 3 +-#define HI6220_MMC1_CIUCLK 4 +-#define HI6220_MMC2_CLK 5 +-#define HI6220_MMC2_CIUCLK 6 +-#define HI6220_USBOTG_HCLK 7 +-#define HI6220_CLK_PICOPHY 8 +-#define HI6220_HIFI 9 +-#define HI6220_DACODEC_PCLK 10 +-#define HI6220_EDMAC_ACLK 11 +-#define HI6220_CS_ATB 12 +-#define HI6220_I2C0_CLK 13 +-#define HI6220_I2C1_CLK 14 +-#define HI6220_I2C2_CLK 15 +-#define HI6220_I2C3_CLK 16 +-#define HI6220_UART1_PCLK 17 +-#define HI6220_UART2_PCLK 18 +-#define HI6220_UART3_PCLK 19 +-#define HI6220_UART4_PCLK 20 +-#define HI6220_SPI_CLK 21 +-#define HI6220_TSENSOR_CLK 22 +-#define HI6220_MMU_CLK 23 +-#define HI6220_HIFI_SEL 24 +-#define HI6220_MMC0_SYSPLL 25 +-#define HI6220_MMC1_SYSPLL 26 +-#define HI6220_MMC2_SYSPLL 27 +-#define HI6220_MMC0_SEL 28 +-#define HI6220_MMC1_SEL 29 +-#define HI6220_BBPPLL_SEL 30 +-#define HI6220_MEDIA_PLL_SRC 31 +-#define HI6220_MMC2_SEL 32 +-#define HI6220_CS_ATB_SYSPLL 33 +- +-/* mux clocks */ +-#define HI6220_MMC0_SRC 34 +-#define HI6220_MMC0_SMP_IN 35 +-#define HI6220_MMC1_SRC 36 +-#define HI6220_MMC1_SMP_IN 37 +-#define HI6220_MMC2_SRC 38 +-#define HI6220_MMC2_SMP_IN 39 +-#define HI6220_HIFI_SRC 40 +-#define HI6220_UART1_SRC 41 +-#define HI6220_UART2_SRC 42 +-#define HI6220_UART3_SRC 43 +-#define HI6220_UART4_SRC 44 +-#define HI6220_MMC0_MUX0 45 +-#define HI6220_MMC1_MUX0 46 +-#define HI6220_MMC2_MUX0 47 +-#define HI6220_MMC0_MUX1 48 +-#define HI6220_MMC1_MUX1 49 +-#define HI6220_MMC2_MUX1 50 +- +-/* divider clocks */ +-#define HI6220_CLK_BUS 51 +-#define HI6220_MMC0_DIV 52 +-#define HI6220_MMC1_DIV 53 +-#define HI6220_MMC2_DIV 54 +-#define HI6220_HIFI_DIV 55 +-#define HI6220_BBPPLL0_DIV 56 +-#define HI6220_CS_DAPB 57 +-#define HI6220_CS_ATB_DIV 58 +- +-/* gate clock */ +-#define HI6220_DAPB_CLK 59 +- +-#define HI6220_SYS_NR_CLKS 60 +- +-/* clk in Hi6220 media controller */ +-/* gate clocks */ +-#define HI6220_DSI_PCLK 1 +-#define HI6220_G3D_PCLK 2 +-#define HI6220_ACLK_CODEC_VPU 3 +-#define HI6220_ISP_SCLK 4 +-#define HI6220_ADE_CORE 5 +-#define HI6220_MED_MMU 6 +-#define HI6220_CFG_CSI4PHY 7 +-#define HI6220_CFG_CSI2PHY 8 +-#define HI6220_ISP_SCLK_GATE 9 +-#define HI6220_ISP_SCLK_GATE1 10 +-#define HI6220_ADE_CORE_GATE 11 +-#define HI6220_CODEC_VPU_GATE 12 +-#define HI6220_MED_SYSPLL 13 +- +-/* mux clocks */ +-#define HI6220_1440_1200 14 +-#define HI6220_1000_1200 15 +-#define HI6220_1000_1440 16 +- +-/* divider clocks */ +-#define HI6220_CODEC_JPEG 17 +-#define HI6220_ISP_SCLK_SRC 18 +-#define HI6220_ISP_SCLK1 19 +-#define HI6220_ADE_CORE_SRC 20 +-#define HI6220_ADE_PIX_SRC 21 +-#define HI6220_G3D_CLK 22 +-#define HI6220_CODEC_VPU_SRC 23 +- +-#define HI6220_MEDIA_NR_CLKS 24 +- +-/* clk in Hi6220 power controller */ +-/* gate clocks */ +-#define HI6220_PLL_GPU_GATE 1 +-#define HI6220_PLL1_DDR_GATE 2 +-#define HI6220_PLL_DDR_GATE 3 +-#define HI6220_PLL_MEDIA_GATE 4 +-#define HI6220_PLL0_BBP_GATE 5 +- +-/* divider clocks */ +-#define HI6220_DDRC_SRC 6 +-#define HI6220_DDRC_AXI1 7 +- +-#define HI6220_POWER_NR_CLKS 8 +- +-/* clk in Hi6220 acpu sctrl */ +-#define HI6220_ACPU_SFT_AT_S 0 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/hip04-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/hip04-clock.h +deleted file mode 100644 +index 088d70cd794d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/hip04-clock.h ++++ /dev/null +@@ -1,21 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (c) 2013-2014 Hisilicon Limited. +- * Copyright (c) 2013-2014 Linaro Limited. +- * +- * Author: Haojian Zhuang +- */ +- +-#ifndef __DTS_HIP04_CLOCK_H +-#define __DTS_HIP04_CLOCK_H +- +-#define HIP04_NONE_CLOCK 0 +- +-/* fixed rate & fixed factor clocks */ +-#define HIP04_OSC50M 1 +-#define HIP04_CLK_50M 2 +-#define HIP04_CLK_168M 3 +- +-#define HIP04_NR_CLKS 64 +- +-#endif /* __DTS_HIP04_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/histb-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/histb-clock.h +deleted file mode 100644 +index e64e5770ada6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/histb-clock.h ++++ /dev/null +@@ -1,70 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. +- */ +- +-#ifndef __DTS_HISTB_CLOCK_H +-#define __DTS_HISTB_CLOCK_H +- +-/* clocks provided by core CRG */ +-#define HISTB_OSC_CLK 0 +-#define HISTB_APB_CLK 1 +-#define HISTB_AHB_CLK 2 +-#define HISTB_UART1_CLK 3 +-#define HISTB_UART2_CLK 4 +-#define HISTB_UART3_CLK 5 +-#define HISTB_I2C0_CLK 6 +-#define HISTB_I2C1_CLK 7 +-#define HISTB_I2C2_CLK 8 +-#define HISTB_I2C3_CLK 9 +-#define HISTB_I2C4_CLK 10 +-#define HISTB_I2C5_CLK 11 +-#define HISTB_SPI0_CLK 12 +-#define HISTB_SPI1_CLK 13 +-#define HISTB_SPI2_CLK 14 +-#define HISTB_SCI_CLK 15 +-#define HISTB_FMC_CLK 16 +-#define HISTB_MMC_BIU_CLK 17 +-#define HISTB_MMC_CIU_CLK 18 +-#define HISTB_MMC_DRV_CLK 19 +-#define HISTB_MMC_SAMPLE_CLK 20 +-#define HISTB_SDIO0_BIU_CLK 21 +-#define HISTB_SDIO0_CIU_CLK 22 +-#define HISTB_SDIO0_DRV_CLK 23 +-#define HISTB_SDIO0_SAMPLE_CLK 24 +-#define HISTB_PCIE_AUX_CLK 25 +-#define HISTB_PCIE_PIPE_CLK 26 +-#define HISTB_PCIE_SYS_CLK 27 +-#define HISTB_PCIE_BUS_CLK 28 +-#define HISTB_ETH0_MAC_CLK 29 +-#define HISTB_ETH0_MACIF_CLK 30 +-#define HISTB_ETH1_MAC_CLK 31 +-#define HISTB_ETH1_MACIF_CLK 32 +-#define HISTB_COMBPHY1_CLK 33 +-#define HISTB_USB2_BUS_CLK 34 +-#define HISTB_USB2_PHY_CLK 35 +-#define HISTB_USB2_UTMI_CLK 36 +-#define HISTB_USB2_12M_CLK 37 +-#define HISTB_USB2_48M_CLK 38 +-#define HISTB_USB2_OTG_UTMI_CLK 39 +-#define HISTB_USB2_PHY1_REF_CLK 40 +-#define HISTB_USB2_PHY2_REF_CLK 41 +-#define HISTB_COMBPHY0_CLK 42 +-#define HISTB_USB3_BUS_CLK 43 +-#define HISTB_USB3_UTMI_CLK 44 +-#define HISTB_USB3_PIPE_CLK 45 +-#define HISTB_USB3_SUSPEND_CLK 46 +-#define HISTB_USB3_BUS_CLK1 47 +-#define HISTB_USB3_UTMI_CLK1 48 +-#define HISTB_USB3_PIPE_CLK1 49 +-#define HISTB_USB3_SUSPEND_CLK1 50 +- +-/* clocks provided by mcu CRG */ +-#define HISTB_MCE_CLK 1 +-#define HISTB_IR_CLK 2 +-#define HISTB_TIMER01_CLK 3 +-#define HISTB_LEDC_CLK 4 +-#define HISTB_UART0_CLK 5 +-#define HISTB_LSADC_CLK 6 +- +-#endif /* __DTS_HISTB_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/hix5hd2-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/hix5hd2-clock.h +deleted file mode 100644 +index 2b8779f1ac99..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/hix5hd2-clock.h ++++ /dev/null +@@ -1,82 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014 Linaro Ltd. +- * Copyright (c) 2014 Hisilicon Limited. +- */ +- +-#ifndef __DTS_HIX5HD2_CLOCK_H +-#define __DTS_HIX5HD2_CLOCK_H +- +-/* fixed rate */ +-#define HIX5HD2_FIXED_1200M 1 +-#define HIX5HD2_FIXED_400M 2 +-#define HIX5HD2_FIXED_48M 3 +-#define HIX5HD2_FIXED_24M 4 +-#define HIX5HD2_FIXED_600M 5 +-#define HIX5HD2_FIXED_300M 6 +-#define HIX5HD2_FIXED_75M 7 +-#define HIX5HD2_FIXED_200M 8 +-#define HIX5HD2_FIXED_100M 9 +-#define HIX5HD2_FIXED_40M 10 +-#define HIX5HD2_FIXED_150M 11 +-#define HIX5HD2_FIXED_1728M 12 +-#define HIX5HD2_FIXED_28P8M 13 +-#define HIX5HD2_FIXED_432M 14 +-#define HIX5HD2_FIXED_345P6M 15 +-#define HIX5HD2_FIXED_288M 16 +-#define HIX5HD2_FIXED_60M 17 +-#define HIX5HD2_FIXED_750M 18 +-#define HIX5HD2_FIXED_500M 19 +-#define HIX5HD2_FIXED_54M 20 +-#define HIX5HD2_FIXED_27M 21 +-#define HIX5HD2_FIXED_1500M 22 +-#define HIX5HD2_FIXED_375M 23 +-#define HIX5HD2_FIXED_187M 24 +-#define HIX5HD2_FIXED_250M 25 +-#define HIX5HD2_FIXED_125M 26 +-#define HIX5HD2_FIXED_2P02M 27 +-#define HIX5HD2_FIXED_50M 28 +-#define HIX5HD2_FIXED_25M 29 +-#define HIX5HD2_FIXED_83M 30 +- +-/* mux clocks */ +-#define HIX5HD2_SFC_MUX 64 +-#define HIX5HD2_MMC_MUX 65 +-#define HIX5HD2_FEPHY_MUX 66 +-#define HIX5HD2_SD_MUX 67 +- +-/* gate clocks */ +-#define HIX5HD2_SFC_RST 128 +-#define HIX5HD2_SFC_CLK 129 +-#define HIX5HD2_MMC_CIU_CLK 130 +-#define HIX5HD2_MMC_BIU_CLK 131 +-#define HIX5HD2_MMC_CIU_RST 132 +-#define HIX5HD2_FWD_BUS_CLK 133 +-#define HIX5HD2_FWD_SYS_CLK 134 +-#define HIX5HD2_MAC0_PHY_CLK 135 +-#define HIX5HD2_SD_CIU_CLK 136 +-#define HIX5HD2_SD_BIU_CLK 137 +-#define HIX5HD2_SD_CIU_RST 138 +-#define HIX5HD2_WDG0_CLK 139 +-#define HIX5HD2_WDG0_RST 140 +-#define HIX5HD2_I2C0_CLK 141 +-#define HIX5HD2_I2C0_RST 142 +-#define HIX5HD2_I2C1_CLK 143 +-#define HIX5HD2_I2C1_RST 144 +-#define HIX5HD2_I2C2_CLK 145 +-#define HIX5HD2_I2C2_RST 146 +-#define HIX5HD2_I2C3_CLK 147 +-#define HIX5HD2_I2C3_RST 148 +-#define HIX5HD2_I2C4_CLK 149 +-#define HIX5HD2_I2C4_RST 150 +-#define HIX5HD2_I2C5_CLK 151 +-#define HIX5HD2_I2C5_RST 152 +- +-/* complex */ +-#define HIX5HD2_MAC0_CLK 192 +-#define HIX5HD2_MAC1_CLK 193 +-#define HIX5HD2_SATA_CLK 194 +-#define HIX5HD2_USB_CLK 195 +- +-#define HIX5HD2_NR_CLKS 256 +-#endif /* __DTS_HIX5HD2_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/imx1-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/imx1-clock.h +deleted file mode 100644 +index 3730a46e7c8e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/imx1-clock.h ++++ /dev/null +@@ -1,36 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2014 Alexander Shiyan +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_IMX1_H +-#define __DT_BINDINGS_CLOCK_IMX1_H +- +-#define IMX1_CLK_DUMMY 0 +-#define IMX1_CLK_CLK32 1 +-#define IMX1_CLK_CLK16M_EXT 2 +-#define IMX1_CLK_CLK16M 3 +-#define IMX1_CLK_CLK32_PREMULT 4 +-#define IMX1_CLK_PREM 5 +-#define IMX1_CLK_MPLL 6 +-#define IMX1_CLK_MPLL_GATE 7 +-#define IMX1_CLK_SPLL 8 +-#define IMX1_CLK_SPLL_GATE 9 +-#define IMX1_CLK_MCU 10 +-#define IMX1_CLK_FCLK 11 +-#define IMX1_CLK_HCLK 12 +-#define IMX1_CLK_CLK48M 13 +-#define IMX1_CLK_PER1 14 +-#define IMX1_CLK_PER2 15 +-#define IMX1_CLK_PER3 16 +-#define IMX1_CLK_CLKO 17 +-#define IMX1_CLK_UART3_GATE 18 +-#define IMX1_CLK_SSI2_GATE 19 +-#define IMX1_CLK_BROM_GATE 20 +-#define IMX1_CLK_DMA_GATE 21 +-#define IMX1_CLK_CSI_GATE 22 +-#define IMX1_CLK_MMA_GATE 23 +-#define IMX1_CLK_USBD_GATE 24 +-#define IMX1_CLK_MAX 25 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/imx21-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/imx21-clock.h +deleted file mode 100644 +index 66d0ec5e4c9b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/imx21-clock.h ++++ /dev/null +@@ -1,76 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2014 Alexander Shiyan +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_IMX21_H +-#define __DT_BINDINGS_CLOCK_IMX21_H +- +-#define IMX21_CLK_DUMMY 0 +-#define IMX21_CLK_CKIL 1 +-#define IMX21_CLK_CKIH 2 +-#define IMX21_CLK_FPM 3 +-#define IMX21_CLK_CKIH_DIV1P5 4 +-#define IMX21_CLK_MPLL_GATE 5 +-#define IMX21_CLK_SPLL_GATE 6 +-#define IMX21_CLK_FPM_GATE 7 +-#define IMX21_CLK_CKIH_GATE 8 +-#define IMX21_CLK_MPLL_OSC_SEL 9 +-#define IMX21_CLK_IPG 10 +-#define IMX21_CLK_HCLK 11 +-#define IMX21_CLK_MPLL_SEL 12 +-#define IMX21_CLK_SPLL_SEL 13 +-#define IMX21_CLK_SSI1_SEL 14 +-#define IMX21_CLK_SSI2_SEL 15 +-#define IMX21_CLK_USB_DIV 16 +-#define IMX21_CLK_FCLK 17 +-#define IMX21_CLK_MPLL 18 +-#define IMX21_CLK_SPLL 19 +-#define IMX21_CLK_NFC_DIV 20 +-#define IMX21_CLK_SSI1_DIV 21 +-#define IMX21_CLK_SSI2_DIV 22 +-#define IMX21_CLK_PER1 23 +-#define IMX21_CLK_PER2 24 +-#define IMX21_CLK_PER3 25 +-#define IMX21_CLK_PER4 26 +-#define IMX21_CLK_UART1_IPG_GATE 27 +-#define IMX21_CLK_UART2_IPG_GATE 28 +-#define IMX21_CLK_UART3_IPG_GATE 29 +-#define IMX21_CLK_UART4_IPG_GATE 30 +-#define IMX21_CLK_CSPI1_IPG_GATE 31 +-#define IMX21_CLK_CSPI2_IPG_GATE 32 +-#define IMX21_CLK_SSI1_GATE 33 +-#define IMX21_CLK_SSI2_GATE 34 +-#define IMX21_CLK_SDHC1_IPG_GATE 35 +-#define IMX21_CLK_SDHC2_IPG_GATE 36 +-#define IMX21_CLK_GPIO_GATE 37 +-#define IMX21_CLK_I2C_GATE 38 +-#define IMX21_CLK_DMA_GATE 39 +-#define IMX21_CLK_USB_GATE 40 +-#define IMX21_CLK_EMMA_GATE 41 +-#define IMX21_CLK_SSI2_BAUD_GATE 42 +-#define IMX21_CLK_SSI1_BAUD_GATE 43 +-#define IMX21_CLK_LCDC_IPG_GATE 44 +-#define IMX21_CLK_NFC_GATE 45 +-#define IMX21_CLK_LCDC_HCLK_GATE 46 +-#define IMX21_CLK_PER4_GATE 47 +-#define IMX21_CLK_BMI_GATE 48 +-#define IMX21_CLK_USB_HCLK_GATE 49 +-#define IMX21_CLK_SLCDC_GATE 50 +-#define IMX21_CLK_SLCDC_HCLK_GATE 51 +-#define IMX21_CLK_EMMA_HCLK_GATE 52 +-#define IMX21_CLK_BROM_GATE 53 +-#define IMX21_CLK_DMA_HCLK_GATE 54 +-#define IMX21_CLK_CSI_HCLK_GATE 55 +-#define IMX21_CLK_CSPI3_IPG_GATE 56 +-#define IMX21_CLK_WDOG_GATE 57 +-#define IMX21_CLK_GPT1_IPG_GATE 58 +-#define IMX21_CLK_GPT2_IPG_GATE 59 +-#define IMX21_CLK_GPT3_IPG_GATE 60 +-#define IMX21_CLK_PWM_IPG_GATE 61 +-#define IMX21_CLK_RTC_GATE 62 +-#define IMX21_CLK_KPP_GATE 63 +-#define IMX21_CLK_OWIRE_GATE 64 +-#define IMX21_CLK_MAX 65 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/imx27-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/imx27-clock.h +deleted file mode 100644 +index 1ff448b80368..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/imx27-clock.h ++++ /dev/null +@@ -1,104 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2014 Alexander Shiyan +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_IMX27_H +-#define __DT_BINDINGS_CLOCK_IMX27_H +- +-#define IMX27_CLK_DUMMY 0 +-#define IMX27_CLK_CKIH 1 +-#define IMX27_CLK_CKIL 2 +-#define IMX27_CLK_MPLL 3 +-#define IMX27_CLK_SPLL 4 +-#define IMX27_CLK_MPLL_MAIN2 5 +-#define IMX27_CLK_AHB 6 +-#define IMX27_CLK_IPG 7 +-#define IMX27_CLK_NFC_DIV 8 +-#define IMX27_CLK_PER1_DIV 9 +-#define IMX27_CLK_PER2_DIV 10 +-#define IMX27_CLK_PER3_DIV 11 +-#define IMX27_CLK_PER4_DIV 12 +-#define IMX27_CLK_VPU_SEL 13 +-#define IMX27_CLK_VPU_DIV 14 +-#define IMX27_CLK_USB_DIV 15 +-#define IMX27_CLK_CPU_SEL 16 +-#define IMX27_CLK_CLKO_SEL 17 +-#define IMX27_CLK_CPU_DIV 18 +-#define IMX27_CLK_CLKO_DIV 19 +-#define IMX27_CLK_SSI1_SEL 20 +-#define IMX27_CLK_SSI2_SEL 21 +-#define IMX27_CLK_SSI1_DIV 22 +-#define IMX27_CLK_SSI2_DIV 23 +-#define IMX27_CLK_CLKO_EN 24 +-#define IMX27_CLK_SSI2_IPG_GATE 25 +-#define IMX27_CLK_SSI1_IPG_GATE 26 +-#define IMX27_CLK_SLCDC_IPG_GATE 27 +-#define IMX27_CLK_SDHC3_IPG_GATE 28 +-#define IMX27_CLK_SDHC2_IPG_GATE 29 +-#define IMX27_CLK_SDHC1_IPG_GATE 30 +-#define IMX27_CLK_SCC_IPG_GATE 31 +-#define IMX27_CLK_SAHARA_IPG_GATE 32 +-#define IMX27_CLK_RTC_IPG_GATE 33 +-#define IMX27_CLK_PWM_IPG_GATE 34 +-#define IMX27_CLK_OWIRE_IPG_GATE 35 +-#define IMX27_CLK_LCDC_IPG_GATE 36 +-#define IMX27_CLK_KPP_IPG_GATE 37 +-#define IMX27_CLK_IIM_IPG_GATE 38 +-#define IMX27_CLK_I2C2_IPG_GATE 39 +-#define IMX27_CLK_I2C1_IPG_GATE 40 +-#define IMX27_CLK_GPT6_IPG_GATE 41 +-#define IMX27_CLK_GPT5_IPG_GATE 42 +-#define IMX27_CLK_GPT4_IPG_GATE 43 +-#define IMX27_CLK_GPT3_IPG_GATE 44 +-#define IMX27_CLK_GPT2_IPG_GATE 45 +-#define IMX27_CLK_GPT1_IPG_GATE 46 +-#define IMX27_CLK_GPIO_IPG_GATE 47 +-#define IMX27_CLK_FEC_IPG_GATE 48 +-#define IMX27_CLK_EMMA_IPG_GATE 49 +-#define IMX27_CLK_DMA_IPG_GATE 50 +-#define IMX27_CLK_CSPI3_IPG_GATE 51 +-#define IMX27_CLK_CSPI2_IPG_GATE 52 +-#define IMX27_CLK_CSPI1_IPG_GATE 53 +-#define IMX27_CLK_NFC_BAUD_GATE 54 +-#define IMX27_CLK_SSI2_BAUD_GATE 55 +-#define IMX27_CLK_SSI1_BAUD_GATE 56 +-#define IMX27_CLK_VPU_BAUD_GATE 57 +-#define IMX27_CLK_PER4_GATE 58 +-#define IMX27_CLK_PER3_GATE 59 +-#define IMX27_CLK_PER2_GATE 60 +-#define IMX27_CLK_PER1_GATE 61 +-#define IMX27_CLK_USB_AHB_GATE 62 +-#define IMX27_CLK_SLCDC_AHB_GATE 63 +-#define IMX27_CLK_SAHARA_AHB_GATE 64 +-#define IMX27_CLK_LCDC_AHB_GATE 65 +-#define IMX27_CLK_VPU_AHB_GATE 66 +-#define IMX27_CLK_FEC_AHB_GATE 67 +-#define IMX27_CLK_EMMA_AHB_GATE 68 +-#define IMX27_CLK_EMI_AHB_GATE 69 +-#define IMX27_CLK_DMA_AHB_GATE 70 +-#define IMX27_CLK_CSI_AHB_GATE 71 +-#define IMX27_CLK_BROM_AHB_GATE 72 +-#define IMX27_CLK_ATA_AHB_GATE 73 +-#define IMX27_CLK_WDOG_IPG_GATE 74 +-#define IMX27_CLK_USB_IPG_GATE 75 +-#define IMX27_CLK_UART6_IPG_GATE 76 +-#define IMX27_CLK_UART5_IPG_GATE 77 +-#define IMX27_CLK_UART4_IPG_GATE 78 +-#define IMX27_CLK_UART3_IPG_GATE 79 +-#define IMX27_CLK_UART2_IPG_GATE 80 +-#define IMX27_CLK_UART1_IPG_GATE 81 +-#define IMX27_CLK_CKIH_DIV1P5 82 +-#define IMX27_CLK_FPM 83 +-#define IMX27_CLK_MPLL_OSC_SEL 84 +-#define IMX27_CLK_MPLL_SEL 85 +-#define IMX27_CLK_SPLL_GATE 86 +-#define IMX27_CLK_MSHC_DIV 87 +-#define IMX27_CLK_RTIC_IPG_GATE 88 +-#define IMX27_CLK_MSHC_IPG_GATE 89 +-#define IMX27_CLK_RTIC_AHB_GATE 90 +-#define IMX27_CLK_MSHC_BAUD_GATE 91 +-#define IMX27_CLK_CKIH_GATE 92 +-#define IMX27_CLK_MAX 93 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/imx5-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/imx5-clock.h +deleted file mode 100644 +index bc65e30695b9..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/imx5-clock.h ++++ /dev/null +@@ -1,216 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2013 Lucas Stach, Pengutronix +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_IMX5_H +-#define __DT_BINDINGS_CLOCK_IMX5_H +- +-#define IMX5_CLK_DUMMY 0 +-#define IMX5_CLK_CKIL 1 +-#define IMX5_CLK_OSC 2 +-#define IMX5_CLK_CKIH1 3 +-#define IMX5_CLK_CKIH2 4 +-#define IMX5_CLK_AHB 5 +-#define IMX5_CLK_IPG 6 +-#define IMX5_CLK_AXI_A 7 +-#define IMX5_CLK_AXI_B 8 +-#define IMX5_CLK_UART_PRED 9 +-#define IMX5_CLK_UART_ROOT 10 +-#define IMX5_CLK_ESDHC_A_PRED 11 +-#define IMX5_CLK_ESDHC_B_PRED 12 +-#define IMX5_CLK_ESDHC_C_SEL 13 +-#define IMX5_CLK_ESDHC_D_SEL 14 +-#define IMX5_CLK_EMI_SEL 15 +-#define IMX5_CLK_EMI_SLOW_PODF 16 +-#define IMX5_CLK_NFC_PODF 17 +-#define IMX5_CLK_ECSPI_PRED 18 +-#define IMX5_CLK_ECSPI_PODF 19 +-#define IMX5_CLK_USBOH3_PRED 20 +-#define IMX5_CLK_USBOH3_PODF 21 +-#define IMX5_CLK_USB_PHY_PRED 22 +-#define IMX5_CLK_USB_PHY_PODF 23 +-#define IMX5_CLK_CPU_PODF 24 +-#define IMX5_CLK_DI_PRED 25 +-#define IMX5_CLK_TVE_SEL 27 +-#define IMX5_CLK_UART1_IPG_GATE 28 +-#define IMX5_CLK_UART1_PER_GATE 29 +-#define IMX5_CLK_UART2_IPG_GATE 30 +-#define IMX5_CLK_UART2_PER_GATE 31 +-#define IMX5_CLK_UART3_IPG_GATE 32 +-#define IMX5_CLK_UART3_PER_GATE 33 +-#define IMX5_CLK_I2C1_GATE 34 +-#define IMX5_CLK_I2C2_GATE 35 +-#define IMX5_CLK_GPT_IPG_GATE 36 +-#define IMX5_CLK_PWM1_IPG_GATE 37 +-#define IMX5_CLK_PWM1_HF_GATE 38 +-#define IMX5_CLK_PWM2_IPG_GATE 39 +-#define IMX5_CLK_PWM2_HF_GATE 40 +-#define IMX5_CLK_GPT_HF_GATE 41 +-#define IMX5_CLK_FEC_GATE 42 +-#define IMX5_CLK_USBOH3_PER_GATE 43 +-#define IMX5_CLK_ESDHC1_IPG_GATE 44 +-#define IMX5_CLK_ESDHC2_IPG_GATE 45 +-#define IMX5_CLK_ESDHC3_IPG_GATE 46 +-#define IMX5_CLK_ESDHC4_IPG_GATE 47 +-#define IMX5_CLK_SSI1_IPG_GATE 48 +-#define IMX5_CLK_SSI2_IPG_GATE 49 +-#define IMX5_CLK_SSI3_IPG_GATE 50 +-#define IMX5_CLK_ECSPI1_IPG_GATE 51 +-#define IMX5_CLK_ECSPI1_PER_GATE 52 +-#define IMX5_CLK_ECSPI2_IPG_GATE 53 +-#define IMX5_CLK_ECSPI2_PER_GATE 54 +-#define IMX5_CLK_CSPI_IPG_GATE 55 +-#define IMX5_CLK_SDMA_GATE 56 +-#define IMX5_CLK_EMI_SLOW_GATE 57 +-#define IMX5_CLK_IPU_SEL 58 +-#define IMX5_CLK_IPU_GATE 59 +-#define IMX5_CLK_NFC_GATE 60 +-#define IMX5_CLK_IPU_DI1_GATE 61 +-#define IMX5_CLK_VPU_SEL 62 +-#define IMX5_CLK_VPU_GATE 63 +-#define IMX5_CLK_VPU_REFERENCE_GATE 64 +-#define IMX5_CLK_UART4_IPG_GATE 65 +-#define IMX5_CLK_UART4_PER_GATE 66 +-#define IMX5_CLK_UART5_IPG_GATE 67 +-#define IMX5_CLK_UART5_PER_GATE 68 +-#define IMX5_CLK_TVE_GATE 69 +-#define IMX5_CLK_TVE_PRED 70 +-#define IMX5_CLK_ESDHC1_PER_GATE 71 +-#define IMX5_CLK_ESDHC2_PER_GATE 72 +-#define IMX5_CLK_ESDHC3_PER_GATE 73 +-#define IMX5_CLK_ESDHC4_PER_GATE 74 +-#define IMX5_CLK_USB_PHY_GATE 75 +-#define IMX5_CLK_HSI2C_GATE 76 +-#define IMX5_CLK_MIPI_HSC1_GATE 77 +-#define IMX5_CLK_MIPI_HSC2_GATE 78 +-#define IMX5_CLK_MIPI_ESC_GATE 79 +-#define IMX5_CLK_MIPI_HSP_GATE 80 +-#define IMX5_CLK_LDB_DI1_DIV_3_5 81 +-#define IMX5_CLK_LDB_DI1_DIV 82 +-#define IMX5_CLK_LDB_DI0_DIV_3_5 83 +-#define IMX5_CLK_LDB_DI0_DIV 84 +-#define IMX5_CLK_LDB_DI1_GATE 85 +-#define IMX5_CLK_CAN2_SERIAL_GATE 86 +-#define IMX5_CLK_CAN2_IPG_GATE 87 +-#define IMX5_CLK_I2C3_GATE 88 +-#define IMX5_CLK_LP_APM 89 +-#define IMX5_CLK_PERIPH_APM 90 +-#define IMX5_CLK_MAIN_BUS 91 +-#define IMX5_CLK_AHB_MAX 92 +-#define IMX5_CLK_AIPS_TZ1 93 +-#define IMX5_CLK_AIPS_TZ2 94 +-#define IMX5_CLK_TMAX1 95 +-#define IMX5_CLK_TMAX2 96 +-#define IMX5_CLK_TMAX3 97 +-#define IMX5_CLK_SPBA 98 +-#define IMX5_CLK_UART_SEL 99 +-#define IMX5_CLK_ESDHC_A_SEL 100 +-#define IMX5_CLK_ESDHC_B_SEL 101 +-#define IMX5_CLK_ESDHC_A_PODF 102 +-#define IMX5_CLK_ESDHC_B_PODF 103 +-#define IMX5_CLK_ECSPI_SEL 104 +-#define IMX5_CLK_USBOH3_SEL 105 +-#define IMX5_CLK_USB_PHY_SEL 106 +-#define IMX5_CLK_IIM_GATE 107 +-#define IMX5_CLK_USBOH3_GATE 108 +-#define IMX5_CLK_EMI_FAST_GATE 109 +-#define IMX5_CLK_IPU_DI0_GATE 110 +-#define IMX5_CLK_GPC_DVFS 111 +-#define IMX5_CLK_PLL1_SW 112 +-#define IMX5_CLK_PLL2_SW 113 +-#define IMX5_CLK_PLL3_SW 114 +-#define IMX5_CLK_IPU_DI0_SEL 115 +-#define IMX5_CLK_IPU_DI1_SEL 116 +-#define IMX5_CLK_TVE_EXT_SEL 117 +-#define IMX5_CLK_MX51_MIPI 118 +-#define IMX5_CLK_PLL4_SW 119 +-#define IMX5_CLK_LDB_DI1_SEL 120 +-#define IMX5_CLK_DI_PLL4_PODF 121 +-#define IMX5_CLK_LDB_DI0_SEL 122 +-#define IMX5_CLK_LDB_DI0_GATE 123 +-#define IMX5_CLK_USB_PHY1_GATE 124 +-#define IMX5_CLK_USB_PHY2_GATE 125 +-#define IMX5_CLK_PER_LP_APM 126 +-#define IMX5_CLK_PER_PRED1 127 +-#define IMX5_CLK_PER_PRED2 128 +-#define IMX5_CLK_PER_PODF 129 +-#define IMX5_CLK_PER_ROOT 130 +-#define IMX5_CLK_SSI_APM 131 +-#define IMX5_CLK_SSI1_ROOT_SEL 132 +-#define IMX5_CLK_SSI2_ROOT_SEL 133 +-#define IMX5_CLK_SSI3_ROOT_SEL 134 +-#define IMX5_CLK_SSI_EXT1_SEL 135 +-#define IMX5_CLK_SSI_EXT2_SEL 136 +-#define IMX5_CLK_SSI_EXT1_COM_SEL 137 +-#define IMX5_CLK_SSI_EXT2_COM_SEL 138 +-#define IMX5_CLK_SSI1_ROOT_PRED 139 +-#define IMX5_CLK_SSI1_ROOT_PODF 140 +-#define IMX5_CLK_SSI2_ROOT_PRED 141 +-#define IMX5_CLK_SSI2_ROOT_PODF 142 +-#define IMX5_CLK_SSI_EXT1_PRED 143 +-#define IMX5_CLK_SSI_EXT1_PODF 144 +-#define IMX5_CLK_SSI_EXT2_PRED 145 +-#define IMX5_CLK_SSI_EXT2_PODF 146 +-#define IMX5_CLK_SSI1_ROOT_GATE 147 +-#define IMX5_CLK_SSI2_ROOT_GATE 148 +-#define IMX5_CLK_SSI3_ROOT_GATE 149 +-#define IMX5_CLK_SSI_EXT1_GATE 150 +-#define IMX5_CLK_SSI_EXT2_GATE 151 +-#define IMX5_CLK_EPIT1_IPG_GATE 152 +-#define IMX5_CLK_EPIT1_HF_GATE 153 +-#define IMX5_CLK_EPIT2_IPG_GATE 154 +-#define IMX5_CLK_EPIT2_HF_GATE 155 +-#define IMX5_CLK_CAN_SEL 156 +-#define IMX5_CLK_CAN1_SERIAL_GATE 157 +-#define IMX5_CLK_CAN1_IPG_GATE 158 +-#define IMX5_CLK_OWIRE_GATE 159 +-#define IMX5_CLK_GPU3D_SEL 160 +-#define IMX5_CLK_GPU2D_SEL 161 +-#define IMX5_CLK_GPU3D_GATE 162 +-#define IMX5_CLK_GPU2D_GATE 163 +-#define IMX5_CLK_GARB_GATE 164 +-#define IMX5_CLK_CKO1_SEL 165 +-#define IMX5_CLK_CKO1_PODF 166 +-#define IMX5_CLK_CKO1 167 +-#define IMX5_CLK_CKO2_SEL 168 +-#define IMX5_CLK_CKO2_PODF 169 +-#define IMX5_CLK_CKO2 170 +-#define IMX5_CLK_SRTC_GATE 171 +-#define IMX5_CLK_PATA_GATE 172 +-#define IMX5_CLK_SATA_GATE 173 +-#define IMX5_CLK_SPDIF_XTAL_SEL 174 +-#define IMX5_CLK_SPDIF0_SEL 175 +-#define IMX5_CLK_SPDIF1_SEL 176 +-#define IMX5_CLK_SPDIF0_PRED 177 +-#define IMX5_CLK_SPDIF0_PODF 178 +-#define IMX5_CLK_SPDIF1_PRED 179 +-#define IMX5_CLK_SPDIF1_PODF 180 +-#define IMX5_CLK_SPDIF0_COM_SEL 181 +-#define IMX5_CLK_SPDIF1_COM_SEL 182 +-#define IMX5_CLK_SPDIF0_GATE 183 +-#define IMX5_CLK_SPDIF1_GATE 184 +-#define IMX5_CLK_SPDIF_IPG_GATE 185 +-#define IMX5_CLK_OCRAM 186 +-#define IMX5_CLK_SAHARA_IPG_GATE 187 +-#define IMX5_CLK_SATA_REF 188 +-#define IMX5_CLK_STEP_SEL 189 +-#define IMX5_CLK_CPU_PODF_SEL 190 +-#define IMX5_CLK_ARM 191 +-#define IMX5_CLK_FIRI_PRED 192 +-#define IMX5_CLK_FIRI_SEL 193 +-#define IMX5_CLK_FIRI_PODF 194 +-#define IMX5_CLK_FIRI_SERIAL_GATE 195 +-#define IMX5_CLK_FIRI_IPG_GATE 196 +-#define IMX5_CLK_CSI0_MCLK1_PRED 197 +-#define IMX5_CLK_CSI0_MCLK1_SEL 198 +-#define IMX5_CLK_CSI0_MCLK1_PODF 199 +-#define IMX5_CLK_CSI0_MCLK1_GATE 200 +-#define IMX5_CLK_IEEE1588_PRED 201 +-#define IMX5_CLK_IEEE1588_SEL 202 +-#define IMX5_CLK_IEEE1588_PODF 203 +-#define IMX5_CLK_IEEE1588_GATE 204 +-#define IMX5_CLK_SCC2_IPG_GATE 205 +-#define IMX5_CLK_END 206 +- +-#endif /* __DT_BINDINGS_CLOCK_IMX5_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/imx6qdl-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/imx6qdl-clock.h +deleted file mode 100644 +index e20c43cc36f6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/imx6qdl-clock.h ++++ /dev/null +@@ -1,278 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2014 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H +-#define __DT_BINDINGS_CLOCK_IMX6QDL_H +- +-#define IMX6QDL_CLK_DUMMY 0 +-#define IMX6QDL_CLK_CKIL 1 +-#define IMX6QDL_CLK_CKIH 2 +-#define IMX6QDL_CLK_OSC 3 +-#define IMX6QDL_CLK_PLL2_PFD0_352M 4 +-#define IMX6QDL_CLK_PLL2_PFD1_594M 5 +-#define IMX6QDL_CLK_PLL2_PFD2_396M 6 +-#define IMX6QDL_CLK_PLL3_PFD0_720M 7 +-#define IMX6QDL_CLK_PLL3_PFD1_540M 8 +-#define IMX6QDL_CLK_PLL3_PFD2_508M 9 +-#define IMX6QDL_CLK_PLL3_PFD3_454M 10 +-#define IMX6QDL_CLK_PLL2_198M 11 +-#define IMX6QDL_CLK_PLL3_120M 12 +-#define IMX6QDL_CLK_PLL3_80M 13 +-#define IMX6QDL_CLK_PLL3_60M 14 +-#define IMX6QDL_CLK_TWD 15 +-#define IMX6QDL_CLK_STEP 16 +-#define IMX6QDL_CLK_PLL1_SW 17 +-#define IMX6QDL_CLK_PERIPH_PRE 18 +-#define IMX6QDL_CLK_PERIPH2_PRE 19 +-#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20 +-#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21 +-#define IMX6QDL_CLK_AXI_SEL 22 +-#define IMX6QDL_CLK_ESAI_SEL 23 +-#define IMX6QDL_CLK_ASRC_SEL 24 +-#define IMX6QDL_CLK_SPDIF_SEL 25 +-#define IMX6QDL_CLK_GPU2D_AXI 26 +-#define IMX6QDL_CLK_GPU3D_AXI 27 +-#define IMX6QDL_CLK_GPU2D_CORE_SEL 28 +-#define IMX6QDL_CLK_GPU3D_CORE_SEL 29 +-#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30 +-#define IMX6QDL_CLK_IPU1_SEL 31 +-#define IMX6QDL_CLK_IPU2_SEL 32 +-#define IMX6QDL_CLK_LDB_DI0_SEL 33 +-#define IMX6QDL_CLK_LDB_DI1_SEL 34 +-#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35 +-#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36 +-#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37 +-#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38 +-#define IMX6QDL_CLK_IPU1_DI0_SEL 39 +-#define IMX6QDL_CLK_IPU1_DI1_SEL 40 +-#define IMX6QDL_CLK_IPU2_DI0_SEL 41 +-#define IMX6QDL_CLK_IPU2_DI1_SEL 42 +-#define IMX6QDL_CLK_HSI_TX_SEL 43 +-#define IMX6QDL_CLK_PCIE_AXI_SEL 44 +-#define IMX6QDL_CLK_SSI1_SEL 45 +-#define IMX6QDL_CLK_SSI2_SEL 46 +-#define IMX6QDL_CLK_SSI3_SEL 47 +-#define IMX6QDL_CLK_USDHC1_SEL 48 +-#define IMX6QDL_CLK_USDHC2_SEL 49 +-#define IMX6QDL_CLK_USDHC3_SEL 50 +-#define IMX6QDL_CLK_USDHC4_SEL 51 +-#define IMX6QDL_CLK_ENFC_SEL 52 +-#define IMX6QDL_CLK_EIM_SEL 53 +-#define IMX6QDL_CLK_EIM_SLOW_SEL 54 +-#define IMX6QDL_CLK_VDO_AXI_SEL 55 +-#define IMX6QDL_CLK_VPU_AXI_SEL 56 +-#define IMX6QDL_CLK_CKO1_SEL 57 +-#define IMX6QDL_CLK_PERIPH 58 +-#define IMX6QDL_CLK_PERIPH2 59 +-#define IMX6QDL_CLK_PERIPH_CLK2 60 +-#define IMX6QDL_CLK_PERIPH2_CLK2 61 +-#define IMX6QDL_CLK_IPG 62 +-#define IMX6QDL_CLK_IPG_PER 63 +-#define IMX6QDL_CLK_ESAI_PRED 64 +-#define IMX6QDL_CLK_ESAI_PODF 65 +-#define IMX6QDL_CLK_ASRC_PRED 66 +-#define IMX6QDL_CLK_ASRC_PODF 67 +-#define IMX6QDL_CLK_SPDIF_PRED 68 +-#define IMX6QDL_CLK_SPDIF_PODF 69 +-#define IMX6QDL_CLK_CAN_ROOT 70 +-#define IMX6QDL_CLK_ECSPI_ROOT 71 +-#define IMX6QDL_CLK_GPU2D_CORE_PODF 72 +-#define IMX6QDL_CLK_GPU3D_CORE_PODF 73 +-#define IMX6QDL_CLK_GPU3D_SHADER 74 +-#define IMX6QDL_CLK_IPU1_PODF 75 +-#define IMX6QDL_CLK_IPU2_PODF 76 +-#define IMX6QDL_CLK_LDB_DI0_PODF 77 +-#define IMX6QDL_CLK_LDB_DI1_PODF 78 +-#define IMX6QDL_CLK_IPU1_DI0_PRE 79 +-#define IMX6QDL_CLK_IPU1_DI1_PRE 80 +-#define IMX6QDL_CLK_IPU2_DI0_PRE 81 +-#define IMX6QDL_CLK_IPU2_DI1_PRE 82 +-#define IMX6QDL_CLK_HSI_TX_PODF 83 +-#define IMX6QDL_CLK_SSI1_PRED 84 +-#define IMX6QDL_CLK_SSI1_PODF 85 +-#define IMX6QDL_CLK_SSI2_PRED 86 +-#define IMX6QDL_CLK_SSI2_PODF 87 +-#define IMX6QDL_CLK_SSI3_PRED 88 +-#define IMX6QDL_CLK_SSI3_PODF 89 +-#define IMX6QDL_CLK_UART_SERIAL_PODF 90 +-#define IMX6QDL_CLK_USDHC1_PODF 91 +-#define IMX6QDL_CLK_USDHC2_PODF 92 +-#define IMX6QDL_CLK_USDHC3_PODF 93 +-#define IMX6QDL_CLK_USDHC4_PODF 94 +-#define IMX6QDL_CLK_ENFC_PRED 95 +-#define IMX6QDL_CLK_ENFC_PODF 96 +-#define IMX6QDL_CLK_EIM_PODF 97 +-#define IMX6QDL_CLK_EIM_SLOW_PODF 98 +-#define IMX6QDL_CLK_VPU_AXI_PODF 99 +-#define IMX6QDL_CLK_CKO1_PODF 100 +-#define IMX6QDL_CLK_AXI 101 +-#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102 +-#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103 +-#define IMX6QDL_CLK_ARM 104 +-#define IMX6QDL_CLK_AHB 105 +-#define IMX6QDL_CLK_APBH_DMA 106 +-#define IMX6QDL_CLK_ASRC 107 +-#define IMX6QDL_CLK_CAN1_IPG 108 +-#define IMX6QDL_CLK_CAN1_SERIAL 109 +-#define IMX6QDL_CLK_CAN2_IPG 110 +-#define IMX6QDL_CLK_CAN2_SERIAL 111 +-#define IMX6QDL_CLK_ECSPI1 112 +-#define IMX6QDL_CLK_ECSPI2 113 +-#define IMX6QDL_CLK_ECSPI3 114 +-#define IMX6QDL_CLK_ECSPI4 115 +-#define IMX6Q_CLK_ECSPI5 116 +-#define IMX6DL_CLK_I2C4 116 +-#define IMX6QDL_CLK_ENET 117 +-#define IMX6QDL_CLK_ESAI_EXTAL 118 +-#define IMX6QDL_CLK_GPT_IPG 119 +-#define IMX6QDL_CLK_GPT_IPG_PER 120 +-#define IMX6QDL_CLK_GPU2D_CORE 121 +-#define IMX6QDL_CLK_GPU3D_CORE 122 +-#define IMX6QDL_CLK_HDMI_IAHB 123 +-#define IMX6QDL_CLK_HDMI_ISFR 124 +-#define IMX6QDL_CLK_I2C1 125 +-#define IMX6QDL_CLK_I2C2 126 +-#define IMX6QDL_CLK_I2C3 127 +-#define IMX6QDL_CLK_IIM 128 +-#define IMX6QDL_CLK_ENFC 129 +-#define IMX6QDL_CLK_IPU1 130 +-#define IMX6QDL_CLK_IPU1_DI0 131 +-#define IMX6QDL_CLK_IPU1_DI1 132 +-#define IMX6QDL_CLK_IPU2 133 +-#define IMX6QDL_CLK_IPU2_DI0 134 +-#define IMX6QDL_CLK_LDB_DI0 135 +-#define IMX6QDL_CLK_LDB_DI1 136 +-#define IMX6QDL_CLK_IPU2_DI1 137 +-#define IMX6QDL_CLK_HSI_TX 138 +-#define IMX6QDL_CLK_MLB 139 +-#define IMX6QDL_CLK_MMDC_CH0_AXI 140 +-#define IMX6QDL_CLK_MMDC_CH1_AXI 141 +-#define IMX6QDL_CLK_OCRAM 142 +-#define IMX6QDL_CLK_OPENVG_AXI 143 +-#define IMX6QDL_CLK_PCIE_AXI 144 +-#define IMX6QDL_CLK_PWM1 145 +-#define IMX6QDL_CLK_PWM2 146 +-#define IMX6QDL_CLK_PWM3 147 +-#define IMX6QDL_CLK_PWM4 148 +-#define IMX6QDL_CLK_PER1_BCH 149 +-#define IMX6QDL_CLK_GPMI_BCH_APB 150 +-#define IMX6QDL_CLK_GPMI_BCH 151 +-#define IMX6QDL_CLK_GPMI_IO 152 +-#define IMX6QDL_CLK_GPMI_APB 153 +-#define IMX6QDL_CLK_SATA 154 +-#define IMX6QDL_CLK_SDMA 155 +-#define IMX6QDL_CLK_SPBA 156 +-#define IMX6QDL_CLK_SSI1 157 +-#define IMX6QDL_CLK_SSI2 158 +-#define IMX6QDL_CLK_SSI3 159 +-#define IMX6QDL_CLK_UART_IPG 160 +-#define IMX6QDL_CLK_UART_SERIAL 161 +-#define IMX6QDL_CLK_USBOH3 162 +-#define IMX6QDL_CLK_USDHC1 163 +-#define IMX6QDL_CLK_USDHC2 164 +-#define IMX6QDL_CLK_USDHC3 165 +-#define IMX6QDL_CLK_USDHC4 166 +-#define IMX6QDL_CLK_VDO_AXI 167 +-#define IMX6QDL_CLK_VPU_AXI 168 +-#define IMX6QDL_CLK_CKO1 169 +-#define IMX6QDL_CLK_PLL1_SYS 170 +-#define IMX6QDL_CLK_PLL2_BUS 171 +-#define IMX6QDL_CLK_PLL3_USB_OTG 172 +-#define IMX6QDL_CLK_PLL4_AUDIO 173 +-#define IMX6QDL_CLK_PLL5_VIDEO 174 +-#define IMX6QDL_CLK_PLL8_MLB 175 +-#define IMX6QDL_CLK_PLL7_USB_HOST 176 +-#define IMX6QDL_CLK_PLL6_ENET 177 +-#define IMX6QDL_CLK_SSI1_IPG 178 +-#define IMX6QDL_CLK_SSI2_IPG 179 +-#define IMX6QDL_CLK_SSI3_IPG 180 +-#define IMX6QDL_CLK_ROM 181 +-#define IMX6QDL_CLK_USBPHY1 182 +-#define IMX6QDL_CLK_USBPHY2 183 +-#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184 +-#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185 +-#define IMX6QDL_CLK_SATA_REF 186 +-#define IMX6QDL_CLK_SATA_REF_100M 187 +-#define IMX6QDL_CLK_PCIE_REF 188 +-#define IMX6QDL_CLK_PCIE_REF_125M 189 +-#define IMX6QDL_CLK_ENET_REF 190 +-#define IMX6QDL_CLK_USBPHY1_GATE 191 +-#define IMX6QDL_CLK_USBPHY2_GATE 192 +-#define IMX6QDL_CLK_PLL4_POST_DIV 193 +-#define IMX6QDL_CLK_PLL5_POST_DIV 194 +-#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195 +-#define IMX6QDL_CLK_EIM_SLOW 196 +-#define IMX6QDL_CLK_SPDIF 197 +-#define IMX6QDL_CLK_CKO2_SEL 198 +-#define IMX6QDL_CLK_CKO2_PODF 199 +-#define IMX6QDL_CLK_CKO2 200 +-#define IMX6QDL_CLK_CKO 201 +-#define IMX6QDL_CLK_VDOA 202 +-#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203 +-#define IMX6QDL_CLK_LVDS1_SEL 204 +-#define IMX6QDL_CLK_LVDS2_SEL 205 +-#define IMX6QDL_CLK_LVDS1_GATE 206 +-#define IMX6QDL_CLK_LVDS2_GATE 207 +-#define IMX6QDL_CLK_ESAI_IPG 208 +-#define IMX6QDL_CLK_ESAI_MEM 209 +-#define IMX6QDL_CLK_ASRC_IPG 210 +-#define IMX6QDL_CLK_ASRC_MEM 211 +-#define IMX6QDL_CLK_LVDS1_IN 212 +-#define IMX6QDL_CLK_LVDS2_IN 213 +-#define IMX6QDL_CLK_ANACLK1 214 +-#define IMX6QDL_CLK_ANACLK2 215 +-#define IMX6QDL_PLL1_BYPASS_SRC 216 +-#define IMX6QDL_PLL2_BYPASS_SRC 217 +-#define IMX6QDL_PLL3_BYPASS_SRC 218 +-#define IMX6QDL_PLL4_BYPASS_SRC 219 +-#define IMX6QDL_PLL5_BYPASS_SRC 220 +-#define IMX6QDL_PLL6_BYPASS_SRC 221 +-#define IMX6QDL_PLL7_BYPASS_SRC 222 +-#define IMX6QDL_CLK_PLL1 223 +-#define IMX6QDL_CLK_PLL2 224 +-#define IMX6QDL_CLK_PLL3 225 +-#define IMX6QDL_CLK_PLL4 226 +-#define IMX6QDL_CLK_PLL5 227 +-#define IMX6QDL_CLK_PLL6 228 +-#define IMX6QDL_CLK_PLL7 229 +-#define IMX6QDL_PLL1_BYPASS 230 +-#define IMX6QDL_PLL2_BYPASS 231 +-#define IMX6QDL_PLL3_BYPASS 232 +-#define IMX6QDL_PLL4_BYPASS 233 +-#define IMX6QDL_PLL5_BYPASS 234 +-#define IMX6QDL_PLL6_BYPASS 235 +-#define IMX6QDL_PLL7_BYPASS 236 +-#define IMX6QDL_CLK_GPT_3M 237 +-#define IMX6QDL_CLK_VIDEO_27M 238 +-#define IMX6QDL_CLK_MIPI_CORE_CFG 239 +-#define IMX6QDL_CLK_MIPI_IPG 240 +-#define IMX6QDL_CLK_CAAM_MEM 241 +-#define IMX6QDL_CLK_CAAM_ACLK 242 +-#define IMX6QDL_CLK_CAAM_IPG 243 +-#define IMX6QDL_CLK_SPDIF_GCLK 244 +-#define IMX6QDL_CLK_UART_SEL 245 +-#define IMX6QDL_CLK_IPG_PER_SEL 246 +-#define IMX6QDL_CLK_ECSPI_SEL 247 +-#define IMX6QDL_CLK_CAN_SEL 248 +-#define IMX6QDL_CLK_MMDC_CH1_AXI_CG 249 +-#define IMX6QDL_CLK_PRE0 250 +-#define IMX6QDL_CLK_PRE1 251 +-#define IMX6QDL_CLK_PRE2 252 +-#define IMX6QDL_CLK_PRE3 253 +-#define IMX6QDL_CLK_PRG0_AXI 254 +-#define IMX6QDL_CLK_PRG1_AXI 255 +-#define IMX6QDL_CLK_PRG0_APB 256 +-#define IMX6QDL_CLK_PRG1_APB 257 +-#define IMX6QDL_CLK_PRE_AXI 258 +-#define IMX6QDL_CLK_MLB_SEL 259 +-#define IMX6QDL_CLK_MLB_PODF 260 +-#define IMX6QDL_CLK_EPIT1 261 +-#define IMX6QDL_CLK_EPIT2 262 +-#define IMX6QDL_CLK_MMDC_P0_IPG 263 +-#define IMX6QDL_CLK_DCIC1 264 +-#define IMX6QDL_CLK_DCIC2 265 +-#define IMX6QDL_CLK_END 266 +- +-#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/imx6sl-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/imx6sl-clock.h +deleted file mode 100644 +index 31364d2caae6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/imx6sl-clock.h ++++ /dev/null +@@ -1,178 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H +-#define __DT_BINDINGS_CLOCK_IMX6SL_H +- +-#define IMX6SL_CLK_DUMMY 0 +-#define IMX6SL_CLK_CKIL 1 +-#define IMX6SL_CLK_OSC 2 +-#define IMX6SL_CLK_PLL1_SYS 3 +-#define IMX6SL_CLK_PLL2_BUS 4 +-#define IMX6SL_CLK_PLL3_USB_OTG 5 +-#define IMX6SL_CLK_PLL4_AUDIO 6 +-#define IMX6SL_CLK_PLL5_VIDEO 7 +-#define IMX6SL_CLK_PLL6_ENET 8 +-#define IMX6SL_CLK_PLL7_USB_HOST 9 +-#define IMX6SL_CLK_USBPHY1 10 +-#define IMX6SL_CLK_USBPHY2 11 +-#define IMX6SL_CLK_USBPHY1_GATE 12 +-#define IMX6SL_CLK_USBPHY2_GATE 13 +-#define IMX6SL_CLK_PLL4_POST_DIV 14 +-#define IMX6SL_CLK_PLL5_POST_DIV 15 +-#define IMX6SL_CLK_PLL5_VIDEO_DIV 16 +-#define IMX6SL_CLK_ENET_REF 17 +-#define IMX6SL_CLK_PLL2_PFD0 18 +-#define IMX6SL_CLK_PLL2_PFD1 19 +-#define IMX6SL_CLK_PLL2_PFD2 20 +-#define IMX6SL_CLK_PLL3_PFD0 21 +-#define IMX6SL_CLK_PLL3_PFD1 22 +-#define IMX6SL_CLK_PLL3_PFD2 23 +-#define IMX6SL_CLK_PLL3_PFD3 24 +-#define IMX6SL_CLK_PLL2_198M 25 +-#define IMX6SL_CLK_PLL3_120M 26 +-#define IMX6SL_CLK_PLL3_80M 27 +-#define IMX6SL_CLK_PLL3_60M 28 +-#define IMX6SL_CLK_STEP 29 +-#define IMX6SL_CLK_PLL1_SW 30 +-#define IMX6SL_CLK_OCRAM_ALT_SEL 31 +-#define IMX6SL_CLK_OCRAM_SEL 32 +-#define IMX6SL_CLK_PRE_PERIPH2_SEL 33 +-#define IMX6SL_CLK_PRE_PERIPH_SEL 34 +-#define IMX6SL_CLK_PERIPH2_CLK2_SEL 35 +-#define IMX6SL_CLK_PERIPH_CLK2_SEL 36 +-#define IMX6SL_CLK_CSI_SEL 37 +-#define IMX6SL_CLK_LCDIF_AXI_SEL 38 +-#define IMX6SL_CLK_USDHC1_SEL 39 +-#define IMX6SL_CLK_USDHC2_SEL 40 +-#define IMX6SL_CLK_USDHC3_SEL 41 +-#define IMX6SL_CLK_USDHC4_SEL 42 +-#define IMX6SL_CLK_SSI1_SEL 43 +-#define IMX6SL_CLK_SSI2_SEL 44 +-#define IMX6SL_CLK_SSI3_SEL 45 +-#define IMX6SL_CLK_PERCLK_SEL 46 +-#define IMX6SL_CLK_PXP_AXI_SEL 47 +-#define IMX6SL_CLK_EPDC_AXI_SEL 48 +-#define IMX6SL_CLK_GPU2D_OVG_SEL 49 +-#define IMX6SL_CLK_GPU2D_SEL 50 +-#define IMX6SL_CLK_LCDIF_PIX_SEL 51 +-#define IMX6SL_CLK_EPDC_PIX_SEL 52 +-#define IMX6SL_CLK_SPDIF0_SEL 53 +-#define IMX6SL_CLK_SPDIF1_SEL 54 +-#define IMX6SL_CLK_EXTERN_AUDIO_SEL 55 +-#define IMX6SL_CLK_ECSPI_SEL 56 +-#define IMX6SL_CLK_UART_SEL 57 +-#define IMX6SL_CLK_PERIPH 58 +-#define IMX6SL_CLK_PERIPH2 59 +-#define IMX6SL_CLK_OCRAM_PODF 60 +-#define IMX6SL_CLK_PERIPH_CLK2_PODF 61 +-#define IMX6SL_CLK_PERIPH2_CLK2_PODF 62 +-#define IMX6SL_CLK_IPG 63 +-#define IMX6SL_CLK_CSI_PODF 64 +-#define IMX6SL_CLK_LCDIF_AXI_PODF 65 +-#define IMX6SL_CLK_USDHC1_PODF 66 +-#define IMX6SL_CLK_USDHC2_PODF 67 +-#define IMX6SL_CLK_USDHC3_PODF 68 +-#define IMX6SL_CLK_USDHC4_PODF 69 +-#define IMX6SL_CLK_SSI1_PRED 70 +-#define IMX6SL_CLK_SSI1_PODF 71 +-#define IMX6SL_CLK_SSI2_PRED 72 +-#define IMX6SL_CLK_SSI2_PODF 73 +-#define IMX6SL_CLK_SSI3_PRED 74 +-#define IMX6SL_CLK_SSI3_PODF 75 +-#define IMX6SL_CLK_PERCLK 76 +-#define IMX6SL_CLK_PXP_AXI_PODF 77 +-#define IMX6SL_CLK_EPDC_AXI_PODF 78 +-#define IMX6SL_CLK_GPU2D_OVG_PODF 79 +-#define IMX6SL_CLK_GPU2D_PODF 80 +-#define IMX6SL_CLK_LCDIF_PIX_PRED 81 +-#define IMX6SL_CLK_EPDC_PIX_PRED 82 +-#define IMX6SL_CLK_LCDIF_PIX_PODF 83 +-#define IMX6SL_CLK_EPDC_PIX_PODF 84 +-#define IMX6SL_CLK_SPDIF0_PRED 85 +-#define IMX6SL_CLK_SPDIF0_PODF 86 +-#define IMX6SL_CLK_SPDIF1_PRED 87 +-#define IMX6SL_CLK_SPDIF1_PODF 88 +-#define IMX6SL_CLK_EXTERN_AUDIO_PRED 89 +-#define IMX6SL_CLK_EXTERN_AUDIO_PODF 90 +-#define IMX6SL_CLK_ECSPI_ROOT 91 +-#define IMX6SL_CLK_UART_ROOT 92 +-#define IMX6SL_CLK_AHB 93 +-#define IMX6SL_CLK_MMDC_ROOT 94 +-#define IMX6SL_CLK_ARM 95 +-#define IMX6SL_CLK_ECSPI1 96 +-#define IMX6SL_CLK_ECSPI2 97 +-#define IMX6SL_CLK_ECSPI3 98 +-#define IMX6SL_CLK_ECSPI4 99 +-#define IMX6SL_CLK_EPIT1 100 +-#define IMX6SL_CLK_EPIT2 101 +-#define IMX6SL_CLK_EXTERN_AUDIO 102 +-#define IMX6SL_CLK_GPT 103 +-#define IMX6SL_CLK_GPT_SERIAL 104 +-#define IMX6SL_CLK_GPU2D_OVG 105 +-#define IMX6SL_CLK_I2C1 106 +-#define IMX6SL_CLK_I2C2 107 +-#define IMX6SL_CLK_I2C3 108 +-#define IMX6SL_CLK_OCOTP 109 +-#define IMX6SL_CLK_CSI 110 +-#define IMX6SL_CLK_PXP_AXI 111 +-#define IMX6SL_CLK_EPDC_AXI 112 +-#define IMX6SL_CLK_LCDIF_AXI 113 +-#define IMX6SL_CLK_LCDIF_PIX 114 +-#define IMX6SL_CLK_EPDC_PIX 115 +-#define IMX6SL_CLK_OCRAM 116 +-#define IMX6SL_CLK_PWM1 117 +-#define IMX6SL_CLK_PWM2 118 +-#define IMX6SL_CLK_PWM3 119 +-#define IMX6SL_CLK_PWM4 120 +-#define IMX6SL_CLK_SDMA 121 +-#define IMX6SL_CLK_SPDIF 122 +-#define IMX6SL_CLK_SSI1 123 +-#define IMX6SL_CLK_SSI2 124 +-#define IMX6SL_CLK_SSI3 125 +-#define IMX6SL_CLK_UART 126 +-#define IMX6SL_CLK_UART_SERIAL 127 +-#define IMX6SL_CLK_USBOH3 128 +-#define IMX6SL_CLK_USDHC1 129 +-#define IMX6SL_CLK_USDHC2 130 +-#define IMX6SL_CLK_USDHC3 131 +-#define IMX6SL_CLK_USDHC4 132 +-#define IMX6SL_CLK_PLL4_AUDIO_DIV 133 +-#define IMX6SL_CLK_SPBA 134 +-#define IMX6SL_CLK_ENET 135 +-#define IMX6SL_CLK_LVDS1_SEL 136 +-#define IMX6SL_CLK_LVDS1_OUT 137 +-#define IMX6SL_CLK_LVDS1_IN 138 +-#define IMX6SL_CLK_ANACLK1 139 +-#define IMX6SL_PLL1_BYPASS_SRC 140 +-#define IMX6SL_PLL2_BYPASS_SRC 141 +-#define IMX6SL_PLL3_BYPASS_SRC 142 +-#define IMX6SL_PLL4_BYPASS_SRC 143 +-#define IMX6SL_PLL5_BYPASS_SRC 144 +-#define IMX6SL_PLL6_BYPASS_SRC 145 +-#define IMX6SL_PLL7_BYPASS_SRC 146 +-#define IMX6SL_CLK_PLL1 147 +-#define IMX6SL_CLK_PLL2 148 +-#define IMX6SL_CLK_PLL3 149 +-#define IMX6SL_CLK_PLL4 150 +-#define IMX6SL_CLK_PLL5 151 +-#define IMX6SL_CLK_PLL6 152 +-#define IMX6SL_CLK_PLL7 153 +-#define IMX6SL_PLL1_BYPASS 154 +-#define IMX6SL_PLL2_BYPASS 155 +-#define IMX6SL_PLL3_BYPASS 156 +-#define IMX6SL_PLL4_BYPASS 157 +-#define IMX6SL_PLL5_BYPASS 158 +-#define IMX6SL_PLL6_BYPASS 159 +-#define IMX6SL_PLL7_BYPASS 160 +-#define IMX6SL_CLK_SSI1_IPG 161 +-#define IMX6SL_CLK_SSI2_IPG 162 +-#define IMX6SL_CLK_SSI3_IPG 163 +-#define IMX6SL_CLK_SPDIF_GCLK 164 +-#define IMX6SL_CLK_MMDC_P0_IPG 165 +-#define IMX6SL_CLK_MMDC_P1_IPG 166 +-#define IMX6SL_CLK_END 167 +- +-#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/imx6sll-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/imx6sll-clock.h +deleted file mode 100644 +index f446710fe63d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/imx6sll-clock.h ++++ /dev/null +@@ -1,210 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2016 Freescale Semiconductor, Inc. +- * Copyright 2017-2018 NXP. +- * +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H +-#define __DT_BINDINGS_CLOCK_IMX6SLL_H +- +-#define IMX6SLL_CLK_DUMMY 0 +-#define IMX6SLL_CLK_CKIL 1 +-#define IMX6SLL_CLK_OSC 2 +-#define IMX6SLL_PLL1_BYPASS_SRC 3 +-#define IMX6SLL_PLL2_BYPASS_SRC 4 +-#define IMX6SLL_PLL3_BYPASS_SRC 5 +-#define IMX6SLL_PLL4_BYPASS_SRC 6 +-#define IMX6SLL_PLL5_BYPASS_SRC 7 +-#define IMX6SLL_PLL6_BYPASS_SRC 8 +-#define IMX6SLL_PLL7_BYPASS_SRC 9 +-#define IMX6SLL_CLK_PLL1 10 +-#define IMX6SLL_CLK_PLL2 11 +-#define IMX6SLL_CLK_PLL3 12 +-#define IMX6SLL_CLK_PLL4 13 +-#define IMX6SLL_CLK_PLL5 14 +-#define IMX6SLL_CLK_PLL6 15 +-#define IMX6SLL_CLK_PLL7 16 +-#define IMX6SLL_PLL1_BYPASS 17 +-#define IMX6SLL_PLL2_BYPASS 18 +-#define IMX6SLL_PLL3_BYPASS 19 +-#define IMX6SLL_PLL4_BYPASS 20 +-#define IMX6SLL_PLL5_BYPASS 21 +-#define IMX6SLL_PLL6_BYPASS 22 +-#define IMX6SLL_PLL7_BYPASS 23 +-#define IMX6SLL_CLK_PLL1_SYS 24 +-#define IMX6SLL_CLK_PLL2_BUS 25 +-#define IMX6SLL_CLK_PLL3_USB_OTG 26 +-#define IMX6SLL_CLK_PLL4_AUDIO 27 +-#define IMX6SLL_CLK_PLL5_VIDEO 28 +-#define IMX6SLL_CLK_PLL6_ENET 29 +-#define IMX6SLL_CLK_PLL7_USB_HOST 30 +-#define IMX6SLL_CLK_USBPHY1 31 +-#define IMX6SLL_CLK_USBPHY2 32 +-#define IMX6SLL_CLK_USBPHY1_GATE 33 +-#define IMX6SLL_CLK_USBPHY2_GATE 34 +-#define IMX6SLL_CLK_PLL2_PFD0 35 +-#define IMX6SLL_CLK_PLL2_PFD1 36 +-#define IMX6SLL_CLK_PLL2_PFD2 37 +-#define IMX6SLL_CLK_PLL2_PFD3 38 +-#define IMX6SLL_CLK_PLL3_PFD0 39 +-#define IMX6SLL_CLK_PLL3_PFD1 40 +-#define IMX6SLL_CLK_PLL3_PFD2 41 +-#define IMX6SLL_CLK_PLL3_PFD3 42 +-#define IMX6SLL_CLK_PLL4_POST_DIV 43 +-#define IMX6SLL_CLK_PLL4_AUDIO_DIV 44 +-#define IMX6SLL_CLK_PLL5_POST_DIV 45 +-#define IMX6SLL_CLK_PLL5_VIDEO_DIV 46 +-#define IMX6SLL_CLK_PLL2_198M 47 +-#define IMX6SLL_CLK_PLL3_120M 48 +-#define IMX6SLL_CLK_PLL3_80M 49 +-#define IMX6SLL_CLK_PLL3_60M 50 +-#define IMX6SLL_CLK_STEP 51 +-#define IMX6SLL_CLK_PLL1_SW 52 +-#define IMX6SLL_CLK_AXI_ALT_SEL 53 +-#define IMX6SLL_CLK_AXI_SEL 54 +-#define IMX6SLL_CLK_PERIPH_PRE 55 +-#define IMX6SLL_CLK_PERIPH2_PRE 56 +-#define IMX6SLL_CLK_PERIPH_CLK2_SEL 57 +-#define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58 +-#define IMX6SLL_CLK_PERCLK_SEL 59 +-#define IMX6SLL_CLK_USDHC1_SEL 60 +-#define IMX6SLL_CLK_USDHC2_SEL 61 +-#define IMX6SLL_CLK_USDHC3_SEL 62 +-#define IMX6SLL_CLK_SSI1_SEL 63 +-#define IMX6SLL_CLK_SSI2_SEL 64 +-#define IMX6SLL_CLK_SSI3_SEL 65 +-#define IMX6SLL_CLK_PXP_SEL 66 +-#define IMX6SLL_CLK_LCDIF_PRE_SEL 67 +-#define IMX6SLL_CLK_LCDIF_SEL 68 +-#define IMX6SLL_CLK_EPDC_PRE_SEL 69 +-#define IMX6SLL_CLK_SPDIF_SEL 70 +-#define IMX6SLL_CLK_ECSPI_SEL 71 +-#define IMX6SLL_CLK_UART_SEL 72 +-#define IMX6SLL_CLK_ARM 73 +-#define IMX6SLL_CLK_PERIPH 74 +-#define IMX6SLL_CLK_PERIPH2 75 +-#define IMX6SLL_CLK_PERIPH2_CLK2 76 +-#define IMX6SLL_CLK_PERIPH_CLK2 77 +-#define IMX6SLL_CLK_MMDC_PODF 78 +-#define IMX6SLL_CLK_AXI_PODF 79 +-#define IMX6SLL_CLK_AHB 80 +-#define IMX6SLL_CLK_IPG 81 +-#define IMX6SLL_CLK_PERCLK 82 +-#define IMX6SLL_CLK_USDHC1_PODF 83 +-#define IMX6SLL_CLK_USDHC2_PODF 84 +-#define IMX6SLL_CLK_USDHC3_PODF 85 +-#define IMX6SLL_CLK_SSI1_PRED 86 +-#define IMX6SLL_CLK_SSI2_PRED 87 +-#define IMX6SLL_CLK_SSI3_PRED 88 +-#define IMX6SLL_CLK_SSI1_PODF 89 +-#define IMX6SLL_CLK_SSI2_PODF 90 +-#define IMX6SLL_CLK_SSI3_PODF 91 +-#define IMX6SLL_CLK_PXP_PODF 92 +-#define IMX6SLL_CLK_LCDIF_PRED 93 +-#define IMX6SLL_CLK_LCDIF_PODF 94 +-#define IMX6SLL_CLK_EPDC_SEL 95 +-#define IMX6SLL_CLK_EPDC_PODF 96 +-#define IMX6SLL_CLK_SPDIF_PRED 97 +-#define IMX6SLL_CLK_SPDIF_PODF 98 +-#define IMX6SLL_CLK_ECSPI_PODF 99 +-#define IMX6SLL_CLK_UART_PODF 100 +- +-/* CCGR 0 */ +-#define IMX6SLL_CLK_AIPSTZ1 101 +-#define IMX6SLL_CLK_AIPSTZ2 102 +-#define IMX6SLL_CLK_DCP 103 +-#define IMX6SLL_CLK_UART2_IPG 104 +-#define IMX6SLL_CLK_UART2_SERIAL 105 +- +-/* CCGR 1 */ +-#define IMX6SLL_CLK_ECSPI1 106 +-#define IMX6SLL_CLK_ECSPI2 107 +-#define IMX6SLL_CLK_ECSPI3 108 +-#define IMX6SLL_CLK_ECSPI4 109 +-#define IMX6SLL_CLK_UART3_IPG 110 +-#define IMX6SLL_CLK_UART3_SERIAL 111 +-#define IMX6SLL_CLK_UART4_IPG 112 +-#define IMX6SLL_CLK_UART4_SERIAL 113 +-#define IMX6SLL_CLK_EPIT1 114 +-#define IMX6SLL_CLK_EPIT2 115 +-#define IMX6SLL_CLK_GPT_BUS 116 +-#define IMX6SLL_CLK_GPT_SERIAL 117 +- +-/* CCGR2 */ +-#define IMX6SLL_CLK_CSI 118 +-#define IMX6SLL_CLK_I2C1 119 +-#define IMX6SLL_CLK_I2C2 120 +-#define IMX6SLL_CLK_I2C3 121 +-#define IMX6SLL_CLK_OCOTP 122 +-#define IMX6SLL_CLK_LCDIF_APB 123 +-#define IMX6SLL_CLK_PXP 124 +- +-/* CCGR3 */ +-#define IMX6SLL_CLK_UART5_IPG 125 +-#define IMX6SLL_CLK_UART5_SERIAL 126 +-#define IMX6SLL_CLK_EPDC_AXI 127 +-#define IMX6SLL_CLK_EPDC_PIX 128 +-#define IMX6SLL_CLK_LCDIF_PIX 129 +-#define IMX6SLL_CLK_WDOG1 130 +-#define IMX6SLL_CLK_MMDC_P0_FAST 131 +-#define IMX6SLL_CLK_MMDC_P0_IPG 132 +-#define IMX6SLL_CLK_OCRAM 133 +- +-/* CCGR4 */ +-#define IMX6SLL_CLK_PWM1 134 +-#define IMX6SLL_CLK_PWM2 135 +-#define IMX6SLL_CLK_PWM3 136 +-#define IMX6SLL_CLK_PWM4 137 +- +-/* CCGR 5 */ +-#define IMX6SLL_CLK_ROM 138 +-#define IMX6SLL_CLK_SDMA 139 +-#define IMX6SLL_CLK_KPP 140 +-#define IMX6SLL_CLK_WDOG2 141 +-#define IMX6SLL_CLK_SPBA 142 +-#define IMX6SLL_CLK_SPDIF 143 +-#define IMX6SLL_CLK_SPDIF_GCLK 144 +-#define IMX6SLL_CLK_SSI1 145 +-#define IMX6SLL_CLK_SSI1_IPG 146 +-#define IMX6SLL_CLK_SSI2 147 +-#define IMX6SLL_CLK_SSI2_IPG 148 +-#define IMX6SLL_CLK_SSI3 149 +-#define IMX6SLL_CLK_SSI3_IPG 150 +-#define IMX6SLL_CLK_UART1_IPG 151 +-#define IMX6SLL_CLK_UART1_SERIAL 152 +- +-/* CCGR 6 */ +-#define IMX6SLL_CLK_USBOH3 153 +-#define IMX6SLL_CLK_USDHC1 154 +-#define IMX6SLL_CLK_USDHC2 155 +-#define IMX6SLL_CLK_USDHC3 156 +- +-#define IMX6SLL_CLK_IPP_DI0 157 +-#define IMX6SLL_CLK_IPP_DI1 158 +-#define IMX6SLL_CLK_LDB_DI0_SEL 159 +-#define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160 +-#define IMX6SLL_CLK_LDB_DI0_DIV_7 161 +-#define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162 +-#define IMX6SLL_CLK_LDB_DI0 163 +-#define IMX6SLL_CLK_LDB_DI1_SEL 164 +-#define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165 +-#define IMX6SLL_CLK_LDB_DI1_DIV_7 166 +-#define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167 +-#define IMX6SLL_CLK_LDB_DI1 168 +-#define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169 +-#define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170 +-#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171 +-#define IMX6SLL_CLK_EXTERN_AUDIO 172 +- +-#define IMX6SLL_CLK_GPIO1 173 +-#define IMX6SLL_CLK_GPIO2 174 +-#define IMX6SLL_CLK_GPIO3 175 +-#define IMX6SLL_CLK_GPIO4 176 +-#define IMX6SLL_CLK_GPIO5 177 +-#define IMX6SLL_CLK_GPIO6 178 +-#define IMX6SLL_CLK_MMDC_P1_IPG 179 +- +-#define IMX6SLL_CLK_END 180 +- +-#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/imx6sx-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/imx6sx-clock.h +deleted file mode 100644 +index 1c64997d6196..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/imx6sx-clock.h ++++ /dev/null +@@ -1,281 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2014 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H +-#define __DT_BINDINGS_CLOCK_IMX6SX_H +- +-#define IMX6SX_CLK_DUMMY 0 +-#define IMX6SX_CLK_CKIL 1 +-#define IMX6SX_CLK_CKIH 2 +-#define IMX6SX_CLK_OSC 3 +-#define IMX6SX_CLK_PLL1_SYS 4 +-#define IMX6SX_CLK_PLL2_BUS 5 +-#define IMX6SX_CLK_PLL3_USB_OTG 6 +-#define IMX6SX_CLK_PLL4_AUDIO 7 +-#define IMX6SX_CLK_PLL5_VIDEO 8 +-#define IMX6SX_CLK_PLL6_ENET 9 +-#define IMX6SX_CLK_PLL7_USB_HOST 10 +-#define IMX6SX_CLK_USBPHY1 11 +-#define IMX6SX_CLK_USBPHY2 12 +-#define IMX6SX_CLK_USBPHY1_GATE 13 +-#define IMX6SX_CLK_USBPHY2_GATE 14 +-#define IMX6SX_CLK_PCIE_REF 15 +-#define IMX6SX_CLK_PCIE_REF_125M 16 +-#define IMX6SX_CLK_ENET_REF 17 +-#define IMX6SX_CLK_PLL2_PFD0 18 +-#define IMX6SX_CLK_PLL2_PFD1 19 +-#define IMX6SX_CLK_PLL2_PFD2 20 +-#define IMX6SX_CLK_PLL2_PFD3 21 +-#define IMX6SX_CLK_PLL3_PFD0 22 +-#define IMX6SX_CLK_PLL3_PFD1 23 +-#define IMX6SX_CLK_PLL3_PFD2 24 +-#define IMX6SX_CLK_PLL3_PFD3 25 +-#define IMX6SX_CLK_PLL2_198M 26 +-#define IMX6SX_CLK_PLL3_120M 27 +-#define IMX6SX_CLK_PLL3_80M 28 +-#define IMX6SX_CLK_PLL3_60M 29 +-#define IMX6SX_CLK_TWD 30 +-#define IMX6SX_CLK_PLL4_POST_DIV 31 +-#define IMX6SX_CLK_PLL4_AUDIO_DIV 32 +-#define IMX6SX_CLK_PLL5_POST_DIV 33 +-#define IMX6SX_CLK_PLL5_VIDEO_DIV 34 +-#define IMX6SX_CLK_STEP 35 +-#define IMX6SX_CLK_PLL1_SW 36 +-#define IMX6SX_CLK_OCRAM_SEL 37 +-#define IMX6SX_CLK_PERIPH_PRE 38 +-#define IMX6SX_CLK_PERIPH2_PRE 39 +-#define IMX6SX_CLK_PERIPH_CLK2_SEL 40 +-#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41 +-#define IMX6SX_CLK_PCIE_AXI_SEL 42 +-#define IMX6SX_CLK_GPU_AXI_SEL 43 +-#define IMX6SX_CLK_GPU_CORE_SEL 44 +-#define IMX6SX_CLK_EIM_SLOW_SEL 45 +-#define IMX6SX_CLK_USDHC1_SEL 46 +-#define IMX6SX_CLK_USDHC2_SEL 47 +-#define IMX6SX_CLK_USDHC3_SEL 48 +-#define IMX6SX_CLK_USDHC4_SEL 49 +-#define IMX6SX_CLK_SSI1_SEL 50 +-#define IMX6SX_CLK_SSI2_SEL 51 +-#define IMX6SX_CLK_SSI3_SEL 52 +-#define IMX6SX_CLK_QSPI1_SEL 53 +-#define IMX6SX_CLK_PERCLK_SEL 54 +-#define IMX6SX_CLK_VID_SEL 55 +-#define IMX6SX_CLK_ESAI_SEL 56 +-#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57 +-#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58 +-#define IMX6SX_CLK_CAN_SEL 59 +-#define IMX6SX_CLK_UART_SEL 60 +-#define IMX6SX_CLK_QSPI2_SEL 61 +-#define IMX6SX_CLK_LDB_DI1_SEL 62 +-#define IMX6SX_CLK_LDB_DI0_SEL 63 +-#define IMX6SX_CLK_SPDIF_SEL 64 +-#define IMX6SX_CLK_AUDIO_SEL 65 +-#define IMX6SX_CLK_ENET_PRE_SEL 66 +-#define IMX6SX_CLK_ENET_SEL 67 +-#define IMX6SX_CLK_M4_PRE_SEL 68 +-#define IMX6SX_CLK_M4_SEL 69 +-#define IMX6SX_CLK_ECSPI_SEL 70 +-#define IMX6SX_CLK_LCDIF1_PRE_SEL 71 +-#define IMX6SX_CLK_LCDIF2_PRE_SEL 72 +-#define IMX6SX_CLK_LCDIF1_SEL 73 +-#define IMX6SX_CLK_LCDIF2_SEL 74 +-#define IMX6SX_CLK_DISPLAY_SEL 75 +-#define IMX6SX_CLK_CSI_SEL 76 +-#define IMX6SX_CLK_CKO1_SEL 77 +-#define IMX6SX_CLK_CKO2_SEL 78 +-#define IMX6SX_CLK_CKO 79 +-#define IMX6SX_CLK_PERIPH_CLK2 80 +-#define IMX6SX_CLK_PERIPH2_CLK2 81 +-#define IMX6SX_CLK_IPG 82 +-#define IMX6SX_CLK_GPU_CORE_PODF 83 +-#define IMX6SX_CLK_GPU_AXI_PODF 84 +-#define IMX6SX_CLK_LCDIF1_PODF 85 +-#define IMX6SX_CLK_QSPI1_PODF 86 +-#define IMX6SX_CLK_EIM_SLOW_PODF 87 +-#define IMX6SX_CLK_LCDIF2_PODF 88 +-#define IMX6SX_CLK_PERCLK 89 +-#define IMX6SX_CLK_VID_PODF 90 +-#define IMX6SX_CLK_CAN_PODF 91 +-#define IMX6SX_CLK_USDHC1_PODF 92 +-#define IMX6SX_CLK_USDHC2_PODF 93 +-#define IMX6SX_CLK_USDHC3_PODF 94 +-#define IMX6SX_CLK_USDHC4_PODF 95 +-#define IMX6SX_CLK_UART_PODF 96 +-#define IMX6SX_CLK_ESAI_PRED 97 +-#define IMX6SX_CLK_ESAI_PODF 98 +-#define IMX6SX_CLK_SSI3_PRED 99 +-#define IMX6SX_CLK_SSI3_PODF 100 +-#define IMX6SX_CLK_SSI1_PRED 101 +-#define IMX6SX_CLK_SSI1_PODF 102 +-#define IMX6SX_CLK_QSPI2_PRED 103 +-#define IMX6SX_CLK_QSPI2_PODF 104 +-#define IMX6SX_CLK_SSI2_PRED 105 +-#define IMX6SX_CLK_SSI2_PODF 106 +-#define IMX6SX_CLK_SPDIF_PRED 107 +-#define IMX6SX_CLK_SPDIF_PODF 108 +-#define IMX6SX_CLK_AUDIO_PRED 109 +-#define IMX6SX_CLK_AUDIO_PODF 110 +-#define IMX6SX_CLK_ENET_PODF 111 +-#define IMX6SX_CLK_M4_PODF 112 +-#define IMX6SX_CLK_ECSPI_PODF 113 +-#define IMX6SX_CLK_LCDIF1_PRED 114 +-#define IMX6SX_CLK_LCDIF2_PRED 115 +-#define IMX6SX_CLK_DISPLAY_PODF 116 +-#define IMX6SX_CLK_CSI_PODF 117 +-#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118 +-#define IMX6SX_CLK_LDB_DI0_DIV_7 119 +-#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120 +-#define IMX6SX_CLK_LDB_DI1_DIV_7 121 +-#define IMX6SX_CLK_CKO1_PODF 122 +-#define IMX6SX_CLK_CKO2_PODF 123 +-#define IMX6SX_CLK_PERIPH 124 +-#define IMX6SX_CLK_PERIPH2 125 +-#define IMX6SX_CLK_OCRAM 126 +-#define IMX6SX_CLK_AHB 127 +-#define IMX6SX_CLK_MMDC_PODF 128 +-#define IMX6SX_CLK_ARM 129 +-#define IMX6SX_CLK_AIPS_TZ1 130 +-#define IMX6SX_CLK_AIPS_TZ2 131 +-#define IMX6SX_CLK_APBH_DMA 132 +-#define IMX6SX_CLK_ASRC_GATE 133 +-#define IMX6SX_CLK_CAAM_MEM 134 +-#define IMX6SX_CLK_CAAM_ACLK 135 +-#define IMX6SX_CLK_CAAM_IPG 136 +-#define IMX6SX_CLK_CAN1_IPG 137 +-#define IMX6SX_CLK_CAN1_SERIAL 138 +-#define IMX6SX_CLK_CAN2_IPG 139 +-#define IMX6SX_CLK_CAN2_SERIAL 140 +-#define IMX6SX_CLK_CPU_DEBUG 141 +-#define IMX6SX_CLK_DCIC1 142 +-#define IMX6SX_CLK_DCIC2 143 +-#define IMX6SX_CLK_AIPS_TZ3 144 +-#define IMX6SX_CLK_ECSPI1 145 +-#define IMX6SX_CLK_ECSPI2 146 +-#define IMX6SX_CLK_ECSPI3 147 +-#define IMX6SX_CLK_ECSPI4 148 +-#define IMX6SX_CLK_ECSPI5 149 +-#define IMX6SX_CLK_EPIT1 150 +-#define IMX6SX_CLK_EPIT2 151 +-#define IMX6SX_CLK_ESAI_EXTAL 152 +-#define IMX6SX_CLK_WAKEUP 153 +-#define IMX6SX_CLK_GPT_BUS 154 +-#define IMX6SX_CLK_GPT_SERIAL 155 +-#define IMX6SX_CLK_GPU 156 +-#define IMX6SX_CLK_OCRAM_S 157 +-#define IMX6SX_CLK_CANFD 158 +-#define IMX6SX_CLK_CSI 159 +-#define IMX6SX_CLK_I2C1 160 +-#define IMX6SX_CLK_I2C2 161 +-#define IMX6SX_CLK_I2C3 162 +-#define IMX6SX_CLK_OCOTP 163 +-#define IMX6SX_CLK_IOMUXC 164 +-#define IMX6SX_CLK_IPMUX1 165 +-#define IMX6SX_CLK_IPMUX2 166 +-#define IMX6SX_CLK_IPMUX3 167 +-#define IMX6SX_CLK_TZASC1 168 +-#define IMX6SX_CLK_LCDIF_APB 169 +-#define IMX6SX_CLK_PXP_AXI 170 +-#define IMX6SX_CLK_M4 171 +-#define IMX6SX_CLK_ENET 172 +-#define IMX6SX_CLK_DISPLAY_AXI 173 +-#define IMX6SX_CLK_LCDIF2_PIX 174 +-#define IMX6SX_CLK_LCDIF1_PIX 175 +-#define IMX6SX_CLK_LDB_DI0 176 +-#define IMX6SX_CLK_QSPI1 177 +-#define IMX6SX_CLK_MLB 178 +-#define IMX6SX_CLK_MMDC_P0_FAST 179 +-#define IMX6SX_CLK_MMDC_P0_IPG 180 +-#define IMX6SX_CLK_AXI 181 +-#define IMX6SX_CLK_PCIE_AXI 182 +-#define IMX6SX_CLK_QSPI2 183 +-#define IMX6SX_CLK_PER1_BCH 184 +-#define IMX6SX_CLK_PER2_MAIN 185 +-#define IMX6SX_CLK_PWM1 186 +-#define IMX6SX_CLK_PWM2 187 +-#define IMX6SX_CLK_PWM3 188 +-#define IMX6SX_CLK_PWM4 189 +-#define IMX6SX_CLK_GPMI_BCH_APB 190 +-#define IMX6SX_CLK_GPMI_BCH 191 +-#define IMX6SX_CLK_GPMI_IO 192 +-#define IMX6SX_CLK_GPMI_APB 193 +-#define IMX6SX_CLK_ROM 194 +-#define IMX6SX_CLK_SDMA 195 +-#define IMX6SX_CLK_SPBA 196 +-#define IMX6SX_CLK_SPDIF 197 +-#define IMX6SX_CLK_SSI1_IPG 198 +-#define IMX6SX_CLK_SSI2_IPG 199 +-#define IMX6SX_CLK_SSI3_IPG 200 +-#define IMX6SX_CLK_SSI1 201 +-#define IMX6SX_CLK_SSI2 202 +-#define IMX6SX_CLK_SSI3 203 +-#define IMX6SX_CLK_UART_IPG 204 +-#define IMX6SX_CLK_UART_SERIAL 205 +-#define IMX6SX_CLK_SAI1 206 +-#define IMX6SX_CLK_SAI2 207 +-#define IMX6SX_CLK_USBOH3 208 +-#define IMX6SX_CLK_USDHC1 209 +-#define IMX6SX_CLK_USDHC2 210 +-#define IMX6SX_CLK_USDHC3 211 +-#define IMX6SX_CLK_USDHC4 212 +-#define IMX6SX_CLK_EIM_SLOW 213 +-#define IMX6SX_CLK_PWM8 214 +-#define IMX6SX_CLK_VADC 215 +-#define IMX6SX_CLK_GIS 216 +-#define IMX6SX_CLK_I2C4 217 +-#define IMX6SX_CLK_PWM5 218 +-#define IMX6SX_CLK_PWM6 219 +-#define IMX6SX_CLK_PWM7 220 +-#define IMX6SX_CLK_CKO1 221 +-#define IMX6SX_CLK_CKO2 222 +-#define IMX6SX_CLK_IPP_DI0 223 +-#define IMX6SX_CLK_IPP_DI1 224 +-#define IMX6SX_CLK_ENET_AHB 225 +-#define IMX6SX_CLK_OCRAM_PODF 226 +-#define IMX6SX_CLK_GPT_3M 227 +-#define IMX6SX_CLK_ENET_PTP 228 +-#define IMX6SX_CLK_ENET_PTP_REF 229 +-#define IMX6SX_CLK_ENET2_REF 230 +-#define IMX6SX_CLK_ENET2_REF_125M 231 +-#define IMX6SX_CLK_AUDIO 232 +-#define IMX6SX_CLK_LVDS1_SEL 233 +-#define IMX6SX_CLK_LVDS1_OUT 234 +-#define IMX6SX_CLK_ASRC_IPG 235 +-#define IMX6SX_CLK_ASRC_MEM 236 +-#define IMX6SX_CLK_SAI1_IPG 237 +-#define IMX6SX_CLK_SAI2_IPG 238 +-#define IMX6SX_CLK_ESAI_IPG 239 +-#define IMX6SX_CLK_ESAI_MEM 240 +-#define IMX6SX_CLK_LVDS1_IN 241 +-#define IMX6SX_CLK_ANACLK1 242 +-#define IMX6SX_PLL1_BYPASS_SRC 243 +-#define IMX6SX_PLL2_BYPASS_SRC 244 +-#define IMX6SX_PLL3_BYPASS_SRC 245 +-#define IMX6SX_PLL4_BYPASS_SRC 246 +-#define IMX6SX_PLL5_BYPASS_SRC 247 +-#define IMX6SX_PLL6_BYPASS_SRC 248 +-#define IMX6SX_PLL7_BYPASS_SRC 249 +-#define IMX6SX_CLK_PLL1 250 +-#define IMX6SX_CLK_PLL2 251 +-#define IMX6SX_CLK_PLL3 252 +-#define IMX6SX_CLK_PLL4 253 +-#define IMX6SX_CLK_PLL5 254 +-#define IMX6SX_CLK_PLL6 255 +-#define IMX6SX_CLK_PLL7 256 +-#define IMX6SX_PLL1_BYPASS 257 +-#define IMX6SX_PLL2_BYPASS 258 +-#define IMX6SX_PLL3_BYPASS 259 +-#define IMX6SX_PLL4_BYPASS 260 +-#define IMX6SX_PLL5_BYPASS 261 +-#define IMX6SX_PLL6_BYPASS 262 +-#define IMX6SX_PLL7_BYPASS 263 +-#define IMX6SX_CLK_SPDIF_GCLK 264 +-#define IMX6SX_CLK_LVDS2_SEL 265 +-#define IMX6SX_CLK_LVDS2_OUT 266 +-#define IMX6SX_CLK_LVDS2_IN 267 +-#define IMX6SX_CLK_ANACLK2 268 +-#define IMX6SX_CLK_MMDC_P1_IPG 269 +-#define IMX6SX_CLK_CLK_END 270 +- +-#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/imx6ul-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/imx6ul-clock.h +deleted file mode 100644 +index 79094338e6f1..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/imx6ul-clock.h ++++ /dev/null +@@ -1,262 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2015 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H +-#define __DT_BINDINGS_CLOCK_IMX6UL_H +- +-#define IMX6UL_CLK_DUMMY 0 +-#define IMX6UL_CLK_CKIL 1 +-#define IMX6UL_CLK_CKIH 2 +-#define IMX6UL_CLK_OSC 3 +-#define IMX6UL_PLL1_BYPASS_SRC 4 +-#define IMX6UL_PLL2_BYPASS_SRC 5 +-#define IMX6UL_PLL3_BYPASS_SRC 6 +-#define IMX6UL_PLL4_BYPASS_SRC 7 +-#define IMX6UL_PLL5_BYPASS_SRC 8 +-#define IMX6UL_PLL6_BYPASS_SRC 9 +-#define IMX6UL_PLL7_BYPASS_SRC 10 +-#define IMX6UL_CLK_PLL1 11 +-#define IMX6UL_CLK_PLL2 12 +-#define IMX6UL_CLK_PLL3 13 +-#define IMX6UL_CLK_PLL4 14 +-#define IMX6UL_CLK_PLL5 15 +-#define IMX6UL_CLK_PLL6 16 +-#define IMX6UL_CLK_PLL7 17 +-#define IMX6UL_PLL1_BYPASS 18 +-#define IMX6UL_PLL2_BYPASS 19 +-#define IMX6UL_PLL3_BYPASS 20 +-#define IMX6UL_PLL4_BYPASS 21 +-#define IMX6UL_PLL5_BYPASS 22 +-#define IMX6UL_PLL6_BYPASS 23 +-#define IMX6UL_PLL7_BYPASS 24 +-#define IMX6UL_CLK_PLL1_SYS 25 +-#define IMX6UL_CLK_PLL2_BUS 26 +-#define IMX6UL_CLK_PLL3_USB_OTG 27 +-#define IMX6UL_CLK_PLL4_AUDIO 28 +-#define IMX6UL_CLK_PLL5_VIDEO 29 +-#define IMX6UL_CLK_PLL6_ENET 30 +-#define IMX6UL_CLK_PLL7_USB_HOST 31 +-#define IMX6UL_CLK_USBPHY1 32 +-#define IMX6UL_CLK_USBPHY2 33 +-#define IMX6UL_CLK_USBPHY1_GATE 34 +-#define IMX6UL_CLK_USBPHY2_GATE 35 +-#define IMX6UL_CLK_PLL2_PFD0 36 +-#define IMX6UL_CLK_PLL2_PFD1 37 +-#define IMX6UL_CLK_PLL2_PFD2 38 +-#define IMX6UL_CLK_PLL2_PFD3 39 +-#define IMX6UL_CLK_PLL3_PFD0 40 +-#define IMX6UL_CLK_PLL3_PFD1 41 +-#define IMX6UL_CLK_PLL3_PFD2 42 +-#define IMX6UL_CLK_PLL3_PFD3 43 +-#define IMX6UL_CLK_ENET_REF 44 +-#define IMX6UL_CLK_ENET2_REF 45 +-#define IMX6UL_CLK_ENET2_REF_125M 46 +-#define IMX6UL_CLK_ENET_PTP_REF 47 +-#define IMX6UL_CLK_ENET_PTP 48 +-#define IMX6UL_CLK_PLL4_POST_DIV 49 +-#define IMX6UL_CLK_PLL4_AUDIO_DIV 50 +-#define IMX6UL_CLK_PLL5_POST_DIV 51 +-#define IMX6UL_CLK_PLL5_VIDEO_DIV 52 +-#define IMX6UL_CLK_PLL2_198M 53 +-#define IMX6UL_CLK_PLL3_80M 54 +-#define IMX6UL_CLK_PLL3_60M 55 +-#define IMX6UL_CLK_STEP 56 +-#define IMX6UL_CLK_PLL1_SW 57 +-#define IMX6UL_CLK_AXI_ALT_SEL 58 +-#define IMX6UL_CLK_AXI_SEL 59 +-#define IMX6UL_CLK_PERIPH_PRE 60 +-#define IMX6UL_CLK_PERIPH2_PRE 61 +-#define IMX6UL_CLK_PERIPH_CLK2_SEL 62 +-#define IMX6UL_CLK_PERIPH2_CLK2_SEL 63 +-#define IMX6UL_CLK_USDHC1_SEL 64 +-#define IMX6UL_CLK_USDHC2_SEL 65 +-#define IMX6UL_CLK_BCH_SEL 66 +-#define IMX6UL_CLK_GPMI_SEL 67 +-#define IMX6UL_CLK_EIM_SLOW_SEL 68 +-#define IMX6UL_CLK_SPDIF_SEL 69 +-#define IMX6UL_CLK_SAI1_SEL 70 +-#define IMX6UL_CLK_SAI2_SEL 71 +-#define IMX6UL_CLK_SAI3_SEL 72 +-#define IMX6UL_CLK_LCDIF_PRE_SEL 73 +-#define IMX6UL_CLK_SIM_PRE_SEL 74 +-#define IMX6UL_CLK_LDB_DI0_SEL 75 +-#define IMX6UL_CLK_LDB_DI1_SEL 76 +-#define IMX6UL_CLK_ENFC_SEL 77 +-#define IMX6UL_CLK_CAN_SEL 78 +-#define IMX6UL_CLK_ECSPI_SEL 79 +-#define IMX6UL_CLK_UART_SEL 80 +-#define IMX6UL_CLK_QSPI1_SEL 81 +-#define IMX6UL_CLK_PERCLK_SEL 82 +-#define IMX6UL_CLK_LCDIF_SEL 83 +-#define IMX6UL_CLK_SIM_SEL 84 +-#define IMX6UL_CLK_PERIPH 85 +-#define IMX6UL_CLK_PERIPH2 86 +-#define IMX6UL_CLK_LDB_DI0_DIV_3_5 87 +-#define IMX6UL_CLK_LDB_DI0_DIV_7 88 +-#define IMX6UL_CLK_LDB_DI1_DIV_3_5 89 +-#define IMX6UL_CLK_LDB_DI1_DIV_7 90 +-#define IMX6UL_CLK_LDB_DI0_DIV_SEL 91 +-#define IMX6UL_CLK_LDB_DI1_DIV_SEL 92 +-#define IMX6UL_CLK_ARM 93 +-#define IMX6UL_CLK_PERIPH_CLK2 94 +-#define IMX6UL_CLK_PERIPH2_CLK2 95 +-#define IMX6UL_CLK_AHB 96 +-#define IMX6UL_CLK_MMDC_PODF 97 +-#define IMX6UL_CLK_AXI_PODF 98 +-#define IMX6UL_CLK_PERCLK 99 +-#define IMX6UL_CLK_IPG 100 +-#define IMX6UL_CLK_USDHC1_PODF 101 +-#define IMX6UL_CLK_USDHC2_PODF 102 +-#define IMX6UL_CLK_BCH_PODF 103 +-#define IMX6UL_CLK_GPMI_PODF 104 +-#define IMX6UL_CLK_EIM_SLOW_PODF 105 +-#define IMX6UL_CLK_SPDIF_PRED 106 +-#define IMX6UL_CLK_SPDIF_PODF 107 +-#define IMX6UL_CLK_SAI1_PRED 108 +-#define IMX6UL_CLK_SAI1_PODF 109 +-#define IMX6UL_CLK_SAI2_PRED 110 +-#define IMX6UL_CLK_SAI2_PODF 111 +-#define IMX6UL_CLK_SAI3_PRED 112 +-#define IMX6UL_CLK_SAI3_PODF 113 +-#define IMX6UL_CLK_LCDIF_PRED 114 +-#define IMX6UL_CLK_LCDIF_PODF 115 +-#define IMX6UL_CLK_SIM_PODF 116 +-#define IMX6UL_CLK_QSPI1_PDOF 117 +-#define IMX6UL_CLK_ENFC_PRED 118 +-#define IMX6UL_CLK_ENFC_PODF 119 +-#define IMX6UL_CLK_CAN_PODF 120 +-#define IMX6UL_CLK_ECSPI_PODF 121 +-#define IMX6UL_CLK_UART_PODF 122 +-#define IMX6UL_CLK_ADC1 123 +-#define IMX6UL_CLK_ADC2 124 +-#define IMX6UL_CLK_AIPSTZ1 125 +-#define IMX6UL_CLK_AIPSTZ2 126 +-#define IMX6UL_CLK_AIPSTZ3 127 +-#define IMX6UL_CLK_APBHDMA 128 +-#define IMX6UL_CLK_ASRC_IPG 129 +-#define IMX6UL_CLK_ASRC_MEM 130 +-#define IMX6UL_CLK_GPMI_BCH_APB 131 +-#define IMX6UL_CLK_GPMI_BCH 132 +-#define IMX6UL_CLK_GPMI_IO 133 +-#define IMX6UL_CLK_GPMI_APB 134 +-#define IMX6UL_CLK_CAAM_MEM 135 +-#define IMX6UL_CLK_CAAM_ACLK 136 +-#define IMX6UL_CLK_CAAM_IPG 137 +-#define IMX6UL_CLK_CSI 138 +-#define IMX6UL_CLK_ECSPI1 139 +-#define IMX6UL_CLK_ECSPI2 140 +-#define IMX6UL_CLK_ECSPI3 141 +-#define IMX6UL_CLK_ECSPI4 142 +-#define IMX6UL_CLK_EIM 143 +-#define IMX6UL_CLK_ENET 144 +-#define IMX6UL_CLK_ENET_AHB 145 +-#define IMX6UL_CLK_EPIT1 146 +-#define IMX6UL_CLK_EPIT2 147 +-#define IMX6UL_CLK_CAN1_IPG 148 +-#define IMX6UL_CLK_CAN1_SERIAL 149 +-#define IMX6UL_CLK_CAN2_IPG 150 +-#define IMX6UL_CLK_CAN2_SERIAL 151 +-#define IMX6UL_CLK_GPT1_BUS 152 +-#define IMX6UL_CLK_GPT1_SERIAL 153 +-#define IMX6UL_CLK_GPT2_BUS 154 +-#define IMX6UL_CLK_GPT2_SERIAL 155 +-#define IMX6UL_CLK_I2C1 156 +-#define IMX6UL_CLK_I2C2 157 +-#define IMX6UL_CLK_I2C3 158 +-#define IMX6UL_CLK_I2C4 159 +-#define IMX6UL_CLK_IOMUXC 160 +-#define IMX6UL_CLK_LCDIF_APB 161 +-#define IMX6UL_CLK_LCDIF_PIX 162 +-#define IMX6UL_CLK_MMDC_P0_FAST 163 +-#define IMX6UL_CLK_MMDC_P0_IPG 164 +-#define IMX6UL_CLK_OCOTP 165 +-#define IMX6UL_CLK_OCRAM 166 +-#define IMX6UL_CLK_PWM1 167 +-#define IMX6UL_CLK_PWM2 168 +-#define IMX6UL_CLK_PWM3 169 +-#define IMX6UL_CLK_PWM4 170 +-#define IMX6UL_CLK_PWM5 171 +-#define IMX6UL_CLK_PWM6 172 +-#define IMX6UL_CLK_PWM7 173 +-#define IMX6UL_CLK_PWM8 174 +-#define IMX6UL_CLK_PXP 175 +-#define IMX6UL_CLK_QSPI 176 +-#define IMX6UL_CLK_ROM 177 +-#define IMX6UL_CLK_SAI1 178 +-#define IMX6UL_CLK_SAI1_IPG 179 +-#define IMX6UL_CLK_SAI2 180 +-#define IMX6UL_CLK_SAI2_IPG 181 +-#define IMX6UL_CLK_SAI3 182 +-#define IMX6UL_CLK_SAI3_IPG 183 +-#define IMX6UL_CLK_SDMA 184 +-#define IMX6UL_CLK_SIM 185 +-#define IMX6UL_CLK_SIM_S 186 +-#define IMX6UL_CLK_SPBA 187 +-#define IMX6UL_CLK_SPDIF 188 +-#define IMX6UL_CLK_UART1_IPG 189 +-#define IMX6UL_CLK_UART1_SERIAL 190 +-#define IMX6UL_CLK_UART2_IPG 191 +-#define IMX6UL_CLK_UART2_SERIAL 192 +-#define IMX6UL_CLK_UART3_IPG 193 +-#define IMX6UL_CLK_UART3_SERIAL 194 +-#define IMX6UL_CLK_UART4_IPG 195 +-#define IMX6UL_CLK_UART4_SERIAL 196 +-#define IMX6UL_CLK_UART5_IPG 197 +-#define IMX6UL_CLK_UART5_SERIAL 198 +-#define IMX6UL_CLK_UART6_IPG 199 +-#define IMX6UL_CLK_UART6_SERIAL 200 +-#define IMX6UL_CLK_UART7_IPG 201 +-#define IMX6UL_CLK_UART7_SERIAL 202 +-#define IMX6UL_CLK_UART8_IPG 203 +-#define IMX6UL_CLK_UART8_SERIAL 204 +-#define IMX6UL_CLK_USBOH3 205 +-#define IMX6UL_CLK_USDHC1 206 +-#define IMX6UL_CLK_USDHC2 207 +-#define IMX6UL_CLK_WDOG1 208 +-#define IMX6UL_CLK_WDOG2 209 +-#define IMX6UL_CLK_WDOG3 210 +-#define IMX6UL_CLK_LDB_DI0 211 +-#define IMX6UL_CLK_AXI 212 +-#define IMX6UL_CLK_SPDIF_GCLK 213 +-#define IMX6UL_CLK_GPT_3M 214 +-#define IMX6UL_CLK_SIM2 215 +-#define IMX6UL_CLK_SIM1 216 +-#define IMX6UL_CLK_IPP_DI0 217 +-#define IMX6UL_CLK_IPP_DI1 218 +-#define IMX6UL_CA7_SECONDARY_SEL 219 +-#define IMX6UL_CLK_PER_BCH 220 +-#define IMX6UL_CLK_CSI_SEL 221 +-#define IMX6UL_CLK_CSI_PODF 222 +-#define IMX6UL_CLK_PLL3_120M 223 +-#define IMX6UL_CLK_KPP 224 +-#define IMX6ULL_CLK_ESAI_PRED 225 +-#define IMX6ULL_CLK_ESAI_PODF 226 +-#define IMX6ULL_CLK_ESAI_EXTAL 227 +-#define IMX6ULL_CLK_ESAI_MEM 228 +-#define IMX6ULL_CLK_ESAI_IPG 229 +-#define IMX6ULL_CLK_DCP_CLK 230 +-#define IMX6ULL_CLK_EPDC_PRE_SEL 231 +-#define IMX6ULL_CLK_EPDC_SEL 232 +-#define IMX6ULL_CLK_EPDC_PODF 233 +-#define IMX6ULL_CLK_EPDC_ACLK 234 +-#define IMX6ULL_CLK_EPDC_PIX 235 +-#define IMX6ULL_CLK_ESAI_SEL 236 +-#define IMX6UL_CLK_CKO1_SEL 237 +-#define IMX6UL_CLK_CKO1_PODF 238 +-#define IMX6UL_CLK_CKO1 239 +-#define IMX6UL_CLK_CKO2_SEL 240 +-#define IMX6UL_CLK_CKO2_PODF 241 +-#define IMX6UL_CLK_CKO2 242 +-#define IMX6UL_CLK_CKO 243 +-#define IMX6UL_CLK_GPIO1 244 +-#define IMX6UL_CLK_GPIO2 245 +-#define IMX6UL_CLK_GPIO3 246 +-#define IMX6UL_CLK_GPIO4 247 +-#define IMX6UL_CLK_GPIO5 248 +-#define IMX6UL_CLK_MMDC_P1_IPG 249 +- +-#define IMX6UL_CLK_END 250 +- +-#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/imx7d-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/imx7d-clock.h +deleted file mode 100644 +index 1d4c0dfe0202..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/imx7d-clock.h ++++ /dev/null +@@ -1,456 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_IMX7D_H +-#define __DT_BINDINGS_CLOCK_IMX7D_H +- +-#define IMX7D_OSC_24M_CLK 0 +-#define IMX7D_PLL_ARM_MAIN 1 +-#define IMX7D_PLL_ARM_MAIN_CLK 2 +-#define IMX7D_PLL_ARM_MAIN_SRC 3 +-#define IMX7D_PLL_ARM_MAIN_BYPASS 4 +-#define IMX7D_PLL_SYS_MAIN 5 +-#define IMX7D_PLL_SYS_MAIN_CLK 6 +-#define IMX7D_PLL_SYS_MAIN_SRC 7 +-#define IMX7D_PLL_SYS_MAIN_BYPASS 8 +-#define IMX7D_PLL_SYS_MAIN_480M 9 +-#define IMX7D_PLL_SYS_MAIN_240M 10 +-#define IMX7D_PLL_SYS_MAIN_120M 11 +-#define IMX7D_PLL_SYS_MAIN_480M_CLK 12 +-#define IMX7D_PLL_SYS_MAIN_240M_CLK 13 +-#define IMX7D_PLL_SYS_MAIN_120M_CLK 14 +-#define IMX7D_PLL_SYS_PFD0_392M_CLK 15 +-#define IMX7D_PLL_SYS_PFD0_196M 16 +-#define IMX7D_PLL_SYS_PFD0_196M_CLK 17 +-#define IMX7D_PLL_SYS_PFD1_332M_CLK 18 +-#define IMX7D_PLL_SYS_PFD1_166M 19 +-#define IMX7D_PLL_SYS_PFD1_166M_CLK 20 +-#define IMX7D_PLL_SYS_PFD2_270M_CLK 21 +-#define IMX7D_PLL_SYS_PFD2_135M 22 +-#define IMX7D_PLL_SYS_PFD2_135M_CLK 23 +-#define IMX7D_PLL_SYS_PFD3_CLK 24 +-#define IMX7D_PLL_SYS_PFD4_CLK 25 +-#define IMX7D_PLL_SYS_PFD5_CLK 26 +-#define IMX7D_PLL_SYS_PFD6_CLK 27 +-#define IMX7D_PLL_SYS_PFD7_CLK 28 +-#define IMX7D_PLL_ENET_MAIN 29 +-#define IMX7D_PLL_ENET_MAIN_CLK 30 +-#define IMX7D_PLL_ENET_MAIN_SRC 31 +-#define IMX7D_PLL_ENET_MAIN_BYPASS 32 +-#define IMX7D_PLL_ENET_MAIN_500M 33 +-#define IMX7D_PLL_ENET_MAIN_250M 34 +-#define IMX7D_PLL_ENET_MAIN_125M 35 +-#define IMX7D_PLL_ENET_MAIN_100M 36 +-#define IMX7D_PLL_ENET_MAIN_50M 37 +-#define IMX7D_PLL_ENET_MAIN_40M 38 +-#define IMX7D_PLL_ENET_MAIN_25M 39 +-#define IMX7D_PLL_ENET_MAIN_500M_CLK 40 +-#define IMX7D_PLL_ENET_MAIN_250M_CLK 41 +-#define IMX7D_PLL_ENET_MAIN_125M_CLK 42 +-#define IMX7D_PLL_ENET_MAIN_100M_CLK 43 +-#define IMX7D_PLL_ENET_MAIN_50M_CLK 44 +-#define IMX7D_PLL_ENET_MAIN_40M_CLK 45 +-#define IMX7D_PLL_ENET_MAIN_25M_CLK 46 +-#define IMX7D_PLL_DRAM_MAIN 47 +-#define IMX7D_PLL_DRAM_MAIN_CLK 48 +-#define IMX7D_PLL_DRAM_MAIN_SRC 49 +-#define IMX7D_PLL_DRAM_MAIN_BYPASS 50 +-#define IMX7D_PLL_DRAM_MAIN_533M 51 +-#define IMX7D_PLL_DRAM_MAIN_533M_CLK 52 +-#define IMX7D_PLL_AUDIO_MAIN 53 +-#define IMX7D_PLL_AUDIO_MAIN_CLK 54 +-#define IMX7D_PLL_AUDIO_MAIN_SRC 55 +-#define IMX7D_PLL_AUDIO_MAIN_BYPASS 56 +-#define IMX7D_PLL_VIDEO_MAIN_CLK 57 +-#define IMX7D_PLL_VIDEO_MAIN 58 +-#define IMX7D_PLL_VIDEO_MAIN_SRC 59 +-#define IMX7D_PLL_VIDEO_MAIN_BYPASS 60 +-#define IMX7D_USB_MAIN_480M_CLK 61 +-#define IMX7D_ARM_A7_ROOT_CLK 62 +-#define IMX7D_ARM_A7_ROOT_SRC 63 +-#define IMX7D_ARM_A7_ROOT_CG 64 +-#define IMX7D_ARM_A7_ROOT_DIV 65 +-#define IMX7D_ARM_M4_ROOT_CLK 66 +-#define IMX7D_ARM_M4_ROOT_SRC 67 +-#define IMX7D_ARM_M4_ROOT_CG 68 +-#define IMX7D_ARM_M4_ROOT_DIV 69 +-#define IMX7D_ARM_M0_ROOT_CLK 70 /* unused */ +-#define IMX7D_ARM_M0_ROOT_SRC 71 /* unused */ +-#define IMX7D_ARM_M0_ROOT_CG 72 /* unused */ +-#define IMX7D_ARM_M0_ROOT_DIV 73 /* unused */ +-#define IMX7D_MAIN_AXI_ROOT_CLK 74 +-#define IMX7D_MAIN_AXI_ROOT_SRC 75 +-#define IMX7D_MAIN_AXI_ROOT_CG 76 +-#define IMX7D_MAIN_AXI_ROOT_DIV 77 +-#define IMX7D_DISP_AXI_ROOT_CLK 78 +-#define IMX7D_DISP_AXI_ROOT_SRC 79 +-#define IMX7D_DISP_AXI_ROOT_CG 80 +-#define IMX7D_DISP_AXI_ROOT_DIV 81 +-#define IMX7D_ENET_AXI_ROOT_CLK 82 +-#define IMX7D_ENET_AXI_ROOT_SRC 83 +-#define IMX7D_ENET_AXI_ROOT_CG 84 +-#define IMX7D_ENET_AXI_ROOT_DIV 85 +-#define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86 +-#define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87 +-#define IMX7D_NAND_USDHC_BUS_ROOT_CG 88 +-#define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89 +-#define IMX7D_AHB_CHANNEL_ROOT_CLK 90 +-#define IMX7D_AHB_CHANNEL_ROOT_SRC 91 +-#define IMX7D_AHB_CHANNEL_ROOT_CG 92 +-#define IMX7D_AHB_CHANNEL_ROOT_DIV 93 +-#define IMX7D_DRAM_PHYM_ROOT_CLK 94 +-#define IMX7D_DRAM_PHYM_ROOT_SRC 95 +-#define IMX7D_DRAM_PHYM_ROOT_CG 96 +-#define IMX7D_DRAM_PHYM_ROOT_DIV 97 +-#define IMX7D_DRAM_ROOT_CLK 98 +-#define IMX7D_DRAM_ROOT_SRC 99 +-#define IMX7D_DRAM_ROOT_CG 100 +-#define IMX7D_DRAM_ROOT_DIV 101 +-#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102 +-#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103 +-#define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104 +-#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105 +-#define IMX7D_DRAM_ALT_ROOT_CLK 106 +-#define IMX7D_DRAM_ALT_ROOT_SRC 107 +-#define IMX7D_DRAM_ALT_ROOT_CG 108 +-#define IMX7D_DRAM_ALT_ROOT_DIV 109 +-#define IMX7D_USB_HSIC_ROOT_CLK 110 +-#define IMX7D_USB_HSIC_ROOT_SRC 111 +-#define IMX7D_USB_HSIC_ROOT_CG 112 +-#define IMX7D_USB_HSIC_ROOT_DIV 113 +-#define IMX7D_PCIE_CTRL_ROOT_CLK 114 +-#define IMX7D_PCIE_CTRL_ROOT_SRC 115 +-#define IMX7D_PCIE_CTRL_ROOT_CG 116 +-#define IMX7D_PCIE_CTRL_ROOT_DIV 117 +-#define IMX7D_PCIE_PHY_ROOT_CLK 118 +-#define IMX7D_PCIE_PHY_ROOT_SRC 119 +-#define IMX7D_PCIE_PHY_ROOT_CG 120 +-#define IMX7D_PCIE_PHY_ROOT_DIV 121 +-#define IMX7D_EPDC_PIXEL_ROOT_CLK 122 +-#define IMX7D_EPDC_PIXEL_ROOT_SRC 123 +-#define IMX7D_EPDC_PIXEL_ROOT_CG 124 +-#define IMX7D_EPDC_PIXEL_ROOT_DIV 125 +-#define IMX7D_LCDIF_PIXEL_ROOT_CLK 126 +-#define IMX7D_LCDIF_PIXEL_ROOT_SRC 127 +-#define IMX7D_LCDIF_PIXEL_ROOT_CG 128 +-#define IMX7D_LCDIF_PIXEL_ROOT_DIV 129 +-#define IMX7D_MIPI_DSI_ROOT_CLK 130 +-#define IMX7D_MIPI_DSI_ROOT_SRC 131 +-#define IMX7D_MIPI_DSI_ROOT_CG 132 +-#define IMX7D_MIPI_DSI_ROOT_DIV 133 +-#define IMX7D_MIPI_CSI_ROOT_CLK 134 +-#define IMX7D_MIPI_CSI_ROOT_SRC 135 +-#define IMX7D_MIPI_CSI_ROOT_CG 136 +-#define IMX7D_MIPI_CSI_ROOT_DIV 137 +-#define IMX7D_MIPI_DPHY_ROOT_CLK 138 +-#define IMX7D_MIPI_DPHY_ROOT_SRC 139 +-#define IMX7D_MIPI_DPHY_ROOT_CG 140 +-#define IMX7D_MIPI_DPHY_ROOT_DIV 141 +-#define IMX7D_SAI1_ROOT_CLK 142 +-#define IMX7D_SAI1_ROOT_SRC 143 +-#define IMX7D_SAI1_ROOT_CG 144 +-#define IMX7D_SAI1_ROOT_DIV 145 +-#define IMX7D_SAI2_ROOT_CLK 146 +-#define IMX7D_SAI2_ROOT_SRC 147 +-#define IMX7D_SAI2_ROOT_CG 148 +-#define IMX7D_SAI2_ROOT_DIV 149 +-#define IMX7D_SAI3_ROOT_CLK 150 +-#define IMX7D_SAI3_ROOT_SRC 151 +-#define IMX7D_SAI3_ROOT_CG 152 +-#define IMX7D_SAI3_ROOT_DIV 153 +-#define IMX7D_SPDIF_ROOT_CLK 154 +-#define IMX7D_SPDIF_ROOT_SRC 155 +-#define IMX7D_SPDIF_ROOT_CG 156 +-#define IMX7D_SPDIF_ROOT_DIV 157 +-#define IMX7D_ENET1_IPG_ROOT_CLK 158 +-#define IMX7D_ENET1_REF_ROOT_SRC 159 +-#define IMX7D_ENET1_REF_ROOT_CG 160 +-#define IMX7D_ENET1_REF_ROOT_DIV 161 +-#define IMX7D_ENET1_TIME_ROOT_CLK 162 +-#define IMX7D_ENET1_TIME_ROOT_SRC 163 +-#define IMX7D_ENET1_TIME_ROOT_CG 164 +-#define IMX7D_ENET1_TIME_ROOT_DIV 165 +-#define IMX7D_ENET2_IPG_ROOT_CLK 166 +-#define IMX7D_ENET2_REF_ROOT_SRC 167 +-#define IMX7D_ENET2_REF_ROOT_CG 168 +-#define IMX7D_ENET2_REF_ROOT_DIV 169 +-#define IMX7D_ENET2_TIME_ROOT_CLK 170 +-#define IMX7D_ENET2_TIME_ROOT_SRC 171 +-#define IMX7D_ENET2_TIME_ROOT_CG 172 +-#define IMX7D_ENET2_TIME_ROOT_DIV 173 +-#define IMX7D_ENET_PHY_REF_ROOT_CLK 174 +-#define IMX7D_ENET_PHY_REF_ROOT_SRC 175 +-#define IMX7D_ENET_PHY_REF_ROOT_CG 176 +-#define IMX7D_ENET_PHY_REF_ROOT_DIV 177 +-#define IMX7D_EIM_ROOT_CLK 178 +-#define IMX7D_EIM_ROOT_SRC 179 +-#define IMX7D_EIM_ROOT_CG 180 +-#define IMX7D_EIM_ROOT_DIV 181 +-#define IMX7D_NAND_ROOT_CLK 182 +-#define IMX7D_NAND_ROOT_SRC 183 +-#define IMX7D_NAND_ROOT_CG 184 +-#define IMX7D_NAND_ROOT_DIV 185 +-#define IMX7D_QSPI_ROOT_CLK 186 +-#define IMX7D_QSPI_ROOT_SRC 187 +-#define IMX7D_QSPI_ROOT_CG 188 +-#define IMX7D_QSPI_ROOT_DIV 189 +-#define IMX7D_USDHC1_ROOT_CLK 190 +-#define IMX7D_USDHC1_ROOT_SRC 191 +-#define IMX7D_USDHC1_ROOT_CG 192 +-#define IMX7D_USDHC1_ROOT_DIV 193 +-#define IMX7D_USDHC2_ROOT_CLK 194 +-#define IMX7D_USDHC2_ROOT_SRC 195 +-#define IMX7D_USDHC2_ROOT_CG 196 +-#define IMX7D_USDHC2_ROOT_DIV 197 +-#define IMX7D_USDHC3_ROOT_CLK 198 +-#define IMX7D_USDHC3_ROOT_SRC 199 +-#define IMX7D_USDHC3_ROOT_CG 200 +-#define IMX7D_USDHC3_ROOT_DIV 201 +-#define IMX7D_CAN1_ROOT_CLK 202 +-#define IMX7D_CAN1_ROOT_SRC 203 +-#define IMX7D_CAN1_ROOT_CG 204 +-#define IMX7D_CAN1_ROOT_DIV 205 +-#define IMX7D_CAN2_ROOT_CLK 206 +-#define IMX7D_CAN2_ROOT_SRC 207 +-#define IMX7D_CAN2_ROOT_CG 208 +-#define IMX7D_CAN2_ROOT_DIV 209 +-#define IMX7D_I2C1_ROOT_CLK 210 +-#define IMX7D_I2C1_ROOT_SRC 211 +-#define IMX7D_I2C1_ROOT_CG 212 +-#define IMX7D_I2C1_ROOT_DIV 213 +-#define IMX7D_I2C2_ROOT_CLK 214 +-#define IMX7D_I2C2_ROOT_SRC 215 +-#define IMX7D_I2C2_ROOT_CG 216 +-#define IMX7D_I2C2_ROOT_DIV 217 +-#define IMX7D_I2C3_ROOT_CLK 218 +-#define IMX7D_I2C3_ROOT_SRC 219 +-#define IMX7D_I2C3_ROOT_CG 220 +-#define IMX7D_I2C3_ROOT_DIV 221 +-#define IMX7D_I2C4_ROOT_CLK 222 +-#define IMX7D_I2C4_ROOT_SRC 223 +-#define IMX7D_I2C4_ROOT_CG 224 +-#define IMX7D_I2C4_ROOT_DIV 225 +-#define IMX7D_UART1_ROOT_CLK 226 +-#define IMX7D_UART1_ROOT_SRC 227 +-#define IMX7D_UART1_ROOT_CG 228 +-#define IMX7D_UART1_ROOT_DIV 229 +-#define IMX7D_UART2_ROOT_CLK 230 +-#define IMX7D_UART2_ROOT_SRC 231 +-#define IMX7D_UART2_ROOT_CG 232 +-#define IMX7D_UART2_ROOT_DIV 233 +-#define IMX7D_UART3_ROOT_CLK 234 +-#define IMX7D_UART3_ROOT_SRC 235 +-#define IMX7D_UART3_ROOT_CG 236 +-#define IMX7D_UART3_ROOT_DIV 237 +-#define IMX7D_UART4_ROOT_CLK 238 +-#define IMX7D_UART4_ROOT_SRC 239 +-#define IMX7D_UART4_ROOT_CG 240 +-#define IMX7D_UART4_ROOT_DIV 241 +-#define IMX7D_UART5_ROOT_CLK 242 +-#define IMX7D_UART5_ROOT_SRC 243 +-#define IMX7D_UART5_ROOT_CG 244 +-#define IMX7D_UART5_ROOT_DIV 245 +-#define IMX7D_UART6_ROOT_CLK 246 +-#define IMX7D_UART6_ROOT_SRC 247 +-#define IMX7D_UART6_ROOT_CG 248 +-#define IMX7D_UART6_ROOT_DIV 249 +-#define IMX7D_UART7_ROOT_CLK 250 +-#define IMX7D_UART7_ROOT_SRC 251 +-#define IMX7D_UART7_ROOT_CG 252 +-#define IMX7D_UART7_ROOT_DIV 253 +-#define IMX7D_ECSPI1_ROOT_CLK 254 +-#define IMX7D_ECSPI1_ROOT_SRC 255 +-#define IMX7D_ECSPI1_ROOT_CG 256 +-#define IMX7D_ECSPI1_ROOT_DIV 257 +-#define IMX7D_ECSPI2_ROOT_CLK 258 +-#define IMX7D_ECSPI2_ROOT_SRC 259 +-#define IMX7D_ECSPI2_ROOT_CG 260 +-#define IMX7D_ECSPI2_ROOT_DIV 261 +-#define IMX7D_ECSPI3_ROOT_CLK 262 +-#define IMX7D_ECSPI3_ROOT_SRC 263 +-#define IMX7D_ECSPI3_ROOT_CG 264 +-#define IMX7D_ECSPI3_ROOT_DIV 265 +-#define IMX7D_ECSPI4_ROOT_CLK 266 +-#define IMX7D_ECSPI4_ROOT_SRC 267 +-#define IMX7D_ECSPI4_ROOT_CG 268 +-#define IMX7D_ECSPI4_ROOT_DIV 269 +-#define IMX7D_PWM1_ROOT_CLK 270 +-#define IMX7D_PWM1_ROOT_SRC 271 +-#define IMX7D_PWM1_ROOT_CG 272 +-#define IMX7D_PWM1_ROOT_DIV 273 +-#define IMX7D_PWM2_ROOT_CLK 274 +-#define IMX7D_PWM2_ROOT_SRC 275 +-#define IMX7D_PWM2_ROOT_CG 276 +-#define IMX7D_PWM2_ROOT_DIV 277 +-#define IMX7D_PWM3_ROOT_CLK 278 +-#define IMX7D_PWM3_ROOT_SRC 279 +-#define IMX7D_PWM3_ROOT_CG 280 +-#define IMX7D_PWM3_ROOT_DIV 281 +-#define IMX7D_PWM4_ROOT_CLK 282 +-#define IMX7D_PWM4_ROOT_SRC 283 +-#define IMX7D_PWM4_ROOT_CG 284 +-#define IMX7D_PWM4_ROOT_DIV 285 +-#define IMX7D_FLEXTIMER1_ROOT_CLK 286 +-#define IMX7D_FLEXTIMER1_ROOT_SRC 287 +-#define IMX7D_FLEXTIMER1_ROOT_CG 288 +-#define IMX7D_FLEXTIMER1_ROOT_DIV 289 +-#define IMX7D_FLEXTIMER2_ROOT_CLK 290 +-#define IMX7D_FLEXTIMER2_ROOT_SRC 291 +-#define IMX7D_FLEXTIMER2_ROOT_CG 292 +-#define IMX7D_FLEXTIMER2_ROOT_DIV 293 +-#define IMX7D_SIM1_ROOT_CLK 294 +-#define IMX7D_SIM1_ROOT_SRC 295 +-#define IMX7D_SIM1_ROOT_CG 296 +-#define IMX7D_SIM1_ROOT_DIV 297 +-#define IMX7D_SIM2_ROOT_CLK 298 +-#define IMX7D_SIM2_ROOT_SRC 299 +-#define IMX7D_SIM2_ROOT_CG 300 +-#define IMX7D_SIM2_ROOT_DIV 301 +-#define IMX7D_GPT1_ROOT_CLK 302 +-#define IMX7D_GPT1_ROOT_SRC 303 +-#define IMX7D_GPT1_ROOT_CG 304 +-#define IMX7D_GPT1_ROOT_DIV 305 +-#define IMX7D_GPT2_ROOT_CLK 306 +-#define IMX7D_GPT2_ROOT_SRC 307 +-#define IMX7D_GPT2_ROOT_CG 308 +-#define IMX7D_GPT2_ROOT_DIV 309 +-#define IMX7D_GPT3_ROOT_CLK 310 +-#define IMX7D_GPT3_ROOT_SRC 311 +-#define IMX7D_GPT3_ROOT_CG 312 +-#define IMX7D_GPT3_ROOT_DIV 313 +-#define IMX7D_GPT4_ROOT_CLK 314 +-#define IMX7D_GPT4_ROOT_SRC 315 +-#define IMX7D_GPT4_ROOT_CG 316 +-#define IMX7D_GPT4_ROOT_DIV 317 +-#define IMX7D_TRACE_ROOT_CLK 318 +-#define IMX7D_TRACE_ROOT_SRC 319 +-#define IMX7D_TRACE_ROOT_CG 320 +-#define IMX7D_TRACE_ROOT_DIV 321 +-#define IMX7D_WDOG1_ROOT_CLK 322 +-#define IMX7D_WDOG_ROOT_SRC 323 +-#define IMX7D_WDOG_ROOT_CG 324 +-#define IMX7D_WDOG_ROOT_DIV 325 +-#define IMX7D_CSI_MCLK_ROOT_CLK 326 +-#define IMX7D_CSI_MCLK_ROOT_SRC 327 +-#define IMX7D_CSI_MCLK_ROOT_CG 328 +-#define IMX7D_CSI_MCLK_ROOT_DIV 329 +-#define IMX7D_AUDIO_MCLK_ROOT_CLK 330 +-#define IMX7D_AUDIO_MCLK_ROOT_SRC 331 +-#define IMX7D_AUDIO_MCLK_ROOT_CG 332 +-#define IMX7D_AUDIO_MCLK_ROOT_DIV 333 +-#define IMX7D_WRCLK_ROOT_CLK 334 +-#define IMX7D_WRCLK_ROOT_SRC 335 +-#define IMX7D_WRCLK_ROOT_CG 336 +-#define IMX7D_WRCLK_ROOT_DIV 337 +-#define IMX7D_CLKO1_ROOT_SRC 338 +-#define IMX7D_CLKO1_ROOT_CG 339 +-#define IMX7D_CLKO1_ROOT_DIV 340 +-#define IMX7D_CLKO2_ROOT_SRC 341 +-#define IMX7D_CLKO2_ROOT_CG 342 +-#define IMX7D_CLKO2_ROOT_DIV 343 +-#define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344 +-#define IMX7D_DISP_AXI_ROOT_PRE_DIV 345 +-#define IMX7D_ENET_AXI_ROOT_PRE_DIV 346 +-#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347 +-#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348 +-#define IMX7D_USB_HSIC_ROOT_PRE_DIV 349 +-#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350 +-#define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351 +-#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352 +-#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353 +-#define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354 +-#define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355 +-#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356 +-#define IMX7D_SAI1_ROOT_PRE_DIV 357 +-#define IMX7D_SAI2_ROOT_PRE_DIV 358 +-#define IMX7D_SAI3_ROOT_PRE_DIV 359 +-#define IMX7D_SPDIF_ROOT_PRE_DIV 360 +-#define IMX7D_ENET1_REF_ROOT_PRE_DIV 361 +-#define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362 +-#define IMX7D_ENET2_REF_ROOT_PRE_DIV 363 +-#define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364 +-#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365 +-#define IMX7D_EIM_ROOT_PRE_DIV 366 +-#define IMX7D_NAND_ROOT_PRE_DIV 367 +-#define IMX7D_QSPI_ROOT_PRE_DIV 368 +-#define IMX7D_USDHC1_ROOT_PRE_DIV 369 +-#define IMX7D_USDHC2_ROOT_PRE_DIV 370 +-#define IMX7D_USDHC3_ROOT_PRE_DIV 371 +-#define IMX7D_CAN1_ROOT_PRE_DIV 372 +-#define IMX7D_CAN2_ROOT_PRE_DIV 373 +-#define IMX7D_I2C1_ROOT_PRE_DIV 374 +-#define IMX7D_I2C2_ROOT_PRE_DIV 375 +-#define IMX7D_I2C3_ROOT_PRE_DIV 376 +-#define IMX7D_I2C4_ROOT_PRE_DIV 377 +-#define IMX7D_UART1_ROOT_PRE_DIV 378 +-#define IMX7D_UART2_ROOT_PRE_DIV 379 +-#define IMX7D_UART3_ROOT_PRE_DIV 380 +-#define IMX7D_UART4_ROOT_PRE_DIV 381 +-#define IMX7D_UART5_ROOT_PRE_DIV 382 +-#define IMX7D_UART6_ROOT_PRE_DIV 383 +-#define IMX7D_UART7_ROOT_PRE_DIV 384 +-#define IMX7D_ECSPI1_ROOT_PRE_DIV 385 +-#define IMX7D_ECSPI2_ROOT_PRE_DIV 386 +-#define IMX7D_ECSPI3_ROOT_PRE_DIV 387 +-#define IMX7D_ECSPI4_ROOT_PRE_DIV 388 +-#define IMX7D_PWM1_ROOT_PRE_DIV 389 +-#define IMX7D_PWM2_ROOT_PRE_DIV 390 +-#define IMX7D_PWM3_ROOT_PRE_DIV 391 +-#define IMX7D_PWM4_ROOT_PRE_DIV 392 +-#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393 +-#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394 +-#define IMX7D_SIM1_ROOT_PRE_DIV 395 +-#define IMX7D_SIM2_ROOT_PRE_DIV 396 +-#define IMX7D_GPT1_ROOT_PRE_DIV 397 +-#define IMX7D_GPT2_ROOT_PRE_DIV 398 +-#define IMX7D_GPT3_ROOT_PRE_DIV 399 +-#define IMX7D_GPT4_ROOT_PRE_DIV 400 +-#define IMX7D_TRACE_ROOT_PRE_DIV 401 +-#define IMX7D_WDOG_ROOT_PRE_DIV 402 +-#define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403 +-#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404 +-#define IMX7D_WRCLK_ROOT_PRE_DIV 405 +-#define IMX7D_CLKO1_ROOT_PRE_DIV 406 +-#define IMX7D_CLKO2_ROOT_PRE_DIV 407 +-#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408 +-#define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409 +-#define IMX7D_LVDS1_IN_CLK 410 +-#define IMX7D_LVDS1_OUT_SEL 411 +-#define IMX7D_LVDS1_OUT_CLK 412 +-#define IMX7D_CLK_DUMMY 413 +-#define IMX7D_GPT_3M_CLK 414 +-#define IMX7D_OCRAM_CLK 415 +-#define IMX7D_OCRAM_S_CLK 416 +-#define IMX7D_WDOG2_ROOT_CLK 417 +-#define IMX7D_WDOG3_ROOT_CLK 418 +-#define IMX7D_WDOG4_ROOT_CLK 419 +-#define IMX7D_SDMA_CORE_CLK 420 +-#define IMX7D_USB1_MAIN_480M_CLK 421 +-#define IMX7D_USB_CTRL_CLK 422 +-#define IMX7D_USB_PHY1_CLK 423 +-#define IMX7D_USB_PHY2_CLK 424 +-#define IMX7D_IPG_ROOT_CLK 425 +-#define IMX7D_SAI1_IPG_CLK 426 +-#define IMX7D_SAI2_IPG_CLK 427 +-#define IMX7D_SAI3_IPG_CLK 428 +-#define IMX7D_PLL_AUDIO_TEST_DIV 429 +-#define IMX7D_PLL_AUDIO_POST_DIV 430 +-#define IMX7D_PLL_VIDEO_TEST_DIV 431 +-#define IMX7D_PLL_VIDEO_POST_DIV 432 +-#define IMX7D_MU_ROOT_CLK 433 +-#define IMX7D_SEMA4_HS_ROOT_CLK 434 +-#define IMX7D_PLL_DRAM_TEST_DIV 435 +-#define IMX7D_ADC_ROOT_CLK 436 +-#define IMX7D_CLK_ARM 437 +-#define IMX7D_CKIL 438 +-#define IMX7D_OCOTP_CLK 439 +-#define IMX7D_NAND_RAWNAND_CLK 440 +-#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441 +-#define IMX7D_SNVS_CLK 442 +-#define IMX7D_CAAM_CLK 443 +-#define IMX7D_KPP_ROOT_CLK 444 +-#define IMX7D_PXP_CLK 445 +-#define IMX7D_CLK_END 446 +-#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/imx7ulp-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/imx7ulp-clock.h +deleted file mode 100644 +index b58370d146e2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/imx7ulp-clock.h ++++ /dev/null +@@ -1,119 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright (C) 2016 Freescale Semiconductor, Inc. +- * Copyright 2017~2018 NXP +- * +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H +-#define __DT_BINDINGS_CLOCK_IMX7ULP_H +- +-/* SCG1 */ +- +-#define IMX7ULP_CLK_DUMMY 0 +-#define IMX7ULP_CLK_ROSC 1 +-#define IMX7ULP_CLK_SOSC 2 +-#define IMX7ULP_CLK_FIRC 3 +-#define IMX7ULP_CLK_SPLL_PRE_SEL 4 +-#define IMX7ULP_CLK_SPLL_PRE_DIV 5 +-#define IMX7ULP_CLK_SPLL 6 +-#define IMX7ULP_CLK_SPLL_POST_DIV1 7 +-#define IMX7ULP_CLK_SPLL_POST_DIV2 8 +-#define IMX7ULP_CLK_SPLL_PFD0 9 +-#define IMX7ULP_CLK_SPLL_PFD1 10 +-#define IMX7ULP_CLK_SPLL_PFD2 11 +-#define IMX7ULP_CLK_SPLL_PFD3 12 +-#define IMX7ULP_CLK_SPLL_PFD_SEL 13 +-#define IMX7ULP_CLK_SPLL_SEL 14 +-#define IMX7ULP_CLK_APLL_PRE_SEL 15 +-#define IMX7ULP_CLK_APLL_PRE_DIV 16 +-#define IMX7ULP_CLK_APLL 17 +-#define IMX7ULP_CLK_APLL_POST_DIV1 18 +-#define IMX7ULP_CLK_APLL_POST_DIV2 19 +-#define IMX7ULP_CLK_APLL_PFD0 20 +-#define IMX7ULP_CLK_APLL_PFD1 21 +-#define IMX7ULP_CLK_APLL_PFD2 22 +-#define IMX7ULP_CLK_APLL_PFD3 23 +-#define IMX7ULP_CLK_APLL_PFD_SEL 24 +-#define IMX7ULP_CLK_APLL_SEL 25 +-#define IMX7ULP_CLK_UPLL 26 +-#define IMX7ULP_CLK_SYS_SEL 27 +-#define IMX7ULP_CLK_CORE_DIV 28 +-#define IMX7ULP_CLK_BUS_DIV 29 +-#define IMX7ULP_CLK_PLAT_DIV 30 +-#define IMX7ULP_CLK_DDR_SEL 31 +-#define IMX7ULP_CLK_DDR_DIV 32 +-#define IMX7ULP_CLK_NIC_SEL 33 +-#define IMX7ULP_CLK_NIC0_DIV 34 +-#define IMX7ULP_CLK_GPU_DIV 35 +-#define IMX7ULP_CLK_NIC1_DIV 36 +-#define IMX7ULP_CLK_NIC1_BUS_DIV 37 +-#define IMX7ULP_CLK_NIC1_EXT_DIV 38 +-/* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */ +-#define IMX7ULP_CLK_MIPI_PLL 39 +-#define IMX7ULP_CLK_SIRC 40 +-#define IMX7ULP_CLK_SOSC_BUS_CLK 41 +-#define IMX7ULP_CLK_FIRC_BUS_CLK 42 +-#define IMX7ULP_CLK_SPLL_BUS_CLK 43 +-#define IMX7ULP_CLK_HSRUN_SYS_SEL 44 +-#define IMX7ULP_CLK_HSRUN_CORE_DIV 45 +- +-#define IMX7ULP_CLK_CORE 46 +-#define IMX7ULP_CLK_HSRUN_CORE 47 +- +-#define IMX7ULP_CLK_SCG1_END 48 +- +-/* PCC2 */ +-#define IMX7ULP_CLK_DMA1 0 +-#define IMX7ULP_CLK_RGPIO2P1 1 +-#define IMX7ULP_CLK_FLEXBUS 2 +-#define IMX7ULP_CLK_SEMA42_1 3 +-#define IMX7ULP_CLK_DMA_MUX1 4 +-#define IMX7ULP_CLK_CAAM 6 +-#define IMX7ULP_CLK_LPTPM4 7 +-#define IMX7ULP_CLK_LPTPM5 8 +-#define IMX7ULP_CLK_LPIT1 9 +-#define IMX7ULP_CLK_LPSPI2 10 +-#define IMX7ULP_CLK_LPSPI3 11 +-#define IMX7ULP_CLK_LPI2C4 12 +-#define IMX7ULP_CLK_LPI2C5 13 +-#define IMX7ULP_CLK_LPUART4 14 +-#define IMX7ULP_CLK_LPUART5 15 +-#define IMX7ULP_CLK_FLEXIO1 16 +-#define IMX7ULP_CLK_USB0 17 +-#define IMX7ULP_CLK_USB1 18 +-#define IMX7ULP_CLK_USB_PHY 19 +-#define IMX7ULP_CLK_USB_PL301 20 +-#define IMX7ULP_CLK_USDHC0 21 +-#define IMX7ULP_CLK_USDHC1 22 +-#define IMX7ULP_CLK_WDG1 23 +-#define IMX7ULP_CLK_WDG2 24 +- +-#define IMX7ULP_CLK_PCC2_END 25 +- +-/* PCC3 */ +-#define IMX7ULP_CLK_LPTPM6 0 +-#define IMX7ULP_CLK_LPTPM7 1 +-#define IMX7ULP_CLK_LPI2C6 2 +-#define IMX7ULP_CLK_LPI2C7 3 +-#define IMX7ULP_CLK_LPUART6 4 +-#define IMX7ULP_CLK_LPUART7 5 +-#define IMX7ULP_CLK_VIU 6 +-#define IMX7ULP_CLK_DSI 7 +-#define IMX7ULP_CLK_LCDIF 8 +-#define IMX7ULP_CLK_MMDC 9 +-#define IMX7ULP_CLK_PCTLC 10 +-#define IMX7ULP_CLK_PCTLD 11 +-#define IMX7ULP_CLK_PCTLE 12 +-#define IMX7ULP_CLK_PCTLF 13 +-#define IMX7ULP_CLK_GPU3D 14 +-#define IMX7ULP_CLK_GPU2D 15 +- +-#define IMX7ULP_CLK_PCC3_END 16 +- +-/* SMC1 */ +-#define IMX7ULP_CLK_ARM 0 +- +-#define IMX7ULP_CLK_SMC1_END 1 +- +-#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/imx8-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/imx8-clock.h +deleted file mode 100644 +index 2e60ce4d2622..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/imx8-clock.h ++++ /dev/null +@@ -1,167 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright 2018 NXP +- * Dong Aisheng +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_IMX_H +-#define __DT_BINDINGS_CLOCK_IMX_H +- +-/* LPCG clocks */ +- +-/* LSIO SS LPCG */ +-#define IMX_LSIO_LPCG_PWM0_IPG_CLK 0 +-#define IMX_LSIO_LPCG_PWM0_IPG_S_CLK 1 +-#define IMX_LSIO_LPCG_PWM0_IPG_HF_CLK 2 +-#define IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK 3 +-#define IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK 4 +-#define IMX_LSIO_LPCG_PWM1_IPG_CLK 5 +-#define IMX_LSIO_LPCG_PWM1_IPG_S_CLK 6 +-#define IMX_LSIO_LPCG_PWM1_IPG_HF_CLK 7 +-#define IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK 8 +-#define IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK 9 +-#define IMX_LSIO_LPCG_PWM2_IPG_CLK 10 +-#define IMX_LSIO_LPCG_PWM2_IPG_S_CLK 11 +-#define IMX_LSIO_LPCG_PWM2_IPG_HF_CLK 12 +-#define IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK 13 +-#define IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK 14 +-#define IMX_LSIO_LPCG_PWM3_IPG_CLK 15 +-#define IMX_LSIO_LPCG_PWM3_IPG_S_CLK 16 +-#define IMX_LSIO_LPCG_PWM3_IPG_HF_CLK 17 +-#define IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK 18 +-#define IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK 19 +-#define IMX_LSIO_LPCG_PWM4_IPG_CLK 20 +-#define IMX_LSIO_LPCG_PWM4_IPG_S_CLK 21 +-#define IMX_LSIO_LPCG_PWM4_IPG_HF_CLK 22 +-#define IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK 23 +-#define IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK 24 +-#define IMX_LSIO_LPCG_PWM5_IPG_CLK 25 +-#define IMX_LSIO_LPCG_PWM5_IPG_S_CLK 26 +-#define IMX_LSIO_LPCG_PWM5_IPG_HF_CLK 27 +-#define IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK 28 +-#define IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK 29 +-#define IMX_LSIO_LPCG_PWM6_IPG_CLK 30 +-#define IMX_LSIO_LPCG_PWM6_IPG_S_CLK 31 +-#define IMX_LSIO_LPCG_PWM6_IPG_HF_CLK 32 +-#define IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK 33 +-#define IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK 34 +-#define IMX_LSIO_LPCG_PWM7_IPG_CLK 35 +-#define IMX_LSIO_LPCG_PWM7_IPG_S_CLK 36 +-#define IMX_LSIO_LPCG_PWM7_IPG_HF_CLK 37 +-#define IMX_LSIO_LPCG_PWM7_IPG_SLV_CLK 38 +-#define IMX_LSIO_LPCG_PWM7_IPG_MSTR_CLK 39 +-#define IMX_LSIO_LPCG_GPT0_IPG_CLK 40 +-#define IMX_LSIO_LPCG_GPT0_IPG_S_CLK 41 +-#define IMX_LSIO_LPCG_GPT0_IPG_HF_CLK 42 +-#define IMX_LSIO_LPCG_GPT0_IPG_SLV_CLK 43 +-#define IMX_LSIO_LPCG_GPT0_IPG_MSTR_CLK 44 +-#define IMX_LSIO_LPCG_GPT1_IPG_CLK 45 +-#define IMX_LSIO_LPCG_GPT1_IPG_S_CLK 46 +-#define IMX_LSIO_LPCG_GPT1_IPG_HF_CLK 47 +-#define IMX_LSIO_LPCG_GPT1_IPG_SLV_CLK 48 +-#define IMX_LSIO_LPCG_GPT1_IPG_MSTR_CLK 49 +-#define IMX_LSIO_LPCG_GPT2_IPG_CLK 50 +-#define IMX_LSIO_LPCG_GPT2_IPG_S_CLK 51 +-#define IMX_LSIO_LPCG_GPT2_IPG_HF_CLK 52 +-#define IMX_LSIO_LPCG_GPT2_IPG_SLV_CLK 53 +-#define IMX_LSIO_LPCG_GPT2_IPG_MSTR_CLK 54 +-#define IMX_LSIO_LPCG_GPT3_IPG_CLK 55 +-#define IMX_LSIO_LPCG_GPT3_IPG_S_CLK 56 +-#define IMX_LSIO_LPCG_GPT3_IPG_HF_CLK 57 +-#define IMX_LSIO_LPCG_GPT3_IPG_SLV_CLK 58 +-#define IMX_LSIO_LPCG_GPT3_IPG_MSTR_CLK 59 +-#define IMX_LSIO_LPCG_GPT4_IPG_CLK 60 +-#define IMX_LSIO_LPCG_GPT4_IPG_S_CLK 61 +-#define IMX_LSIO_LPCG_GPT4_IPG_HF_CLK 62 +-#define IMX_LSIO_LPCG_GPT4_IPG_SLV_CLK 63 +-#define IMX_LSIO_LPCG_GPT4_IPG_MSTR_CLK 64 +-#define IMX_LSIO_LPCG_FSPI0_HCLK 65 +-#define IMX_LSIO_LPCG_FSPI0_IPG_CLK 66 +-#define IMX_LSIO_LPCG_FSPI0_IPG_S_CLK 67 +-#define IMX_LSIO_LPCG_FSPI0_IPG_SFCK 68 +-#define IMX_LSIO_LPCG_FSPI1_HCLK 69 +-#define IMX_LSIO_LPCG_FSPI1_IPG_CLK 70 +-#define IMX_LSIO_LPCG_FSPI1_IPG_S_CLK 71 +-#define IMX_LSIO_LPCG_FSPI1_IPG_SFCK 72 +- +-#define IMX_LSIO_LPCG_CLK_END 73 +- +-/* Connectivity SS LPCG */ +-#define IMX_CONN_LPCG_SDHC0_IPG_CLK 0 +-#define IMX_CONN_LPCG_SDHC0_PER_CLK 1 +-#define IMX_CONN_LPCG_SDHC0_HCLK 2 +-#define IMX_CONN_LPCG_SDHC1_IPG_CLK 3 +-#define IMX_CONN_LPCG_SDHC1_PER_CLK 4 +-#define IMX_CONN_LPCG_SDHC1_HCLK 5 +-#define IMX_CONN_LPCG_SDHC2_IPG_CLK 6 +-#define IMX_CONN_LPCG_SDHC2_PER_CLK 7 +-#define IMX_CONN_LPCG_SDHC2_HCLK 8 +-#define IMX_CONN_LPCG_GPMI_APB_CLK 9 +-#define IMX_CONN_LPCG_GPMI_BCH_APB_CLK 10 +-#define IMX_CONN_LPCG_GPMI_BCH_IO_CLK 11 +-#define IMX_CONN_LPCG_GPMI_BCH_CLK 12 +-#define IMX_CONN_LPCG_APBHDMA_CLK 13 +-#define IMX_CONN_LPCG_ENET0_ROOT_CLK 14 +-#define IMX_CONN_LPCG_ENET0_TX_CLK 15 +-#define IMX_CONN_LPCG_ENET0_AHB_CLK 16 +-#define IMX_CONN_LPCG_ENET0_IPG_S_CLK 17 +-#define IMX_CONN_LPCG_ENET0_IPG_CLK 18 +- +-#define IMX_CONN_LPCG_ENET1_ROOT_CLK 19 +-#define IMX_CONN_LPCG_ENET1_TX_CLK 20 +-#define IMX_CONN_LPCG_ENET1_AHB_CLK 21 +-#define IMX_CONN_LPCG_ENET1_IPG_S_CLK 22 +-#define IMX_CONN_LPCG_ENET1_IPG_CLK 23 +- +-#define IMX_CONN_LPCG_CLK_END 24 +- +-/* ADMA SS LPCG */ +-#define IMX_ADMA_LPCG_UART0_IPG_CLK 0 +-#define IMX_ADMA_LPCG_UART0_BAUD_CLK 1 +-#define IMX_ADMA_LPCG_UART1_IPG_CLK 2 +-#define IMX_ADMA_LPCG_UART1_BAUD_CLK 3 +-#define IMX_ADMA_LPCG_UART2_IPG_CLK 4 +-#define IMX_ADMA_LPCG_UART2_BAUD_CLK 5 +-#define IMX_ADMA_LPCG_UART3_IPG_CLK 6 +-#define IMX_ADMA_LPCG_UART3_BAUD_CLK 7 +-#define IMX_ADMA_LPCG_SPI0_IPG_CLK 8 +-#define IMX_ADMA_LPCG_SPI1_IPG_CLK 9 +-#define IMX_ADMA_LPCG_SPI2_IPG_CLK 10 +-#define IMX_ADMA_LPCG_SPI3_IPG_CLK 11 +-#define IMX_ADMA_LPCG_SPI0_CLK 12 +-#define IMX_ADMA_LPCG_SPI1_CLK 13 +-#define IMX_ADMA_LPCG_SPI2_CLK 14 +-#define IMX_ADMA_LPCG_SPI3_CLK 15 +-#define IMX_ADMA_LPCG_CAN0_IPG_CLK 16 +-#define IMX_ADMA_LPCG_CAN0_IPG_PE_CLK 17 +-#define IMX_ADMA_LPCG_CAN0_IPG_CHI_CLK 18 +-#define IMX_ADMA_LPCG_CAN1_IPG_CLK 19 +-#define IMX_ADMA_LPCG_CAN1_IPG_PE_CLK 20 +-#define IMX_ADMA_LPCG_CAN1_IPG_CHI_CLK 21 +-#define IMX_ADMA_LPCG_CAN2_IPG_CLK 22 +-#define IMX_ADMA_LPCG_CAN2_IPG_PE_CLK 23 +-#define IMX_ADMA_LPCG_CAN2_IPG_CHI_CLK 24 +-#define IMX_ADMA_LPCG_I2C0_CLK 25 +-#define IMX_ADMA_LPCG_I2C1_CLK 26 +-#define IMX_ADMA_LPCG_I2C2_CLK 27 +-#define IMX_ADMA_LPCG_I2C3_CLK 28 +-#define IMX_ADMA_LPCG_I2C0_IPG_CLK 29 +-#define IMX_ADMA_LPCG_I2C1_IPG_CLK 30 +-#define IMX_ADMA_LPCG_I2C2_IPG_CLK 31 +-#define IMX_ADMA_LPCG_I2C3_IPG_CLK 32 +-#define IMX_ADMA_LPCG_FTM0_CLK 33 +-#define IMX_ADMA_LPCG_FTM1_CLK 34 +-#define IMX_ADMA_LPCG_FTM0_IPG_CLK 35 +-#define IMX_ADMA_LPCG_FTM1_IPG_CLK 36 +-#define IMX_ADMA_LPCG_PWM_HI_CLK 37 +-#define IMX_ADMA_LPCG_PWM_IPG_CLK 38 +-#define IMX_ADMA_LPCG_LCD_PIX_CLK 39 +-#define IMX_ADMA_LPCG_LCD_APB_CLK 40 +-#define IMX_ADMA_LPCG_DSP_ADB_CLK 41 +-#define IMX_ADMA_LPCG_DSP_IPG_CLK 42 +-#define IMX_ADMA_LPCG_DSP_CORE_CLK 43 +-#define IMX_ADMA_LPCG_OCRAM_IPG_CLK 44 +- +-#define IMX_ADMA_LPCG_CLK_END 45 +- +-#endif /* __DT_BINDINGS_CLOCK_IMX_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/imx8-lpcg.h b/scripts/dtc/include-prefixes/dt-bindings/clock/imx8-lpcg.h +deleted file mode 100644 +index d202715652c3..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/imx8-lpcg.h ++++ /dev/null +@@ -1,14 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright 2019-2020 NXP +- * Dong Aisheng +- */ +- +-#define IMX_LPCG_CLK_0 0 +-#define IMX_LPCG_CLK_1 4 +-#define IMX_LPCG_CLK_2 8 +-#define IMX_LPCG_CLK_3 12 +-#define IMX_LPCG_CLK_4 16 +-#define IMX_LPCG_CLK_5 20 +-#define IMX_LPCG_CLK_6 24 +-#define IMX_LPCG_CLK_7 28 +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/imx8mm-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/imx8mm-clock.h +deleted file mode 100644 +index 47c6f7f9582c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/imx8mm-clock.h ++++ /dev/null +@@ -1,287 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright 2017-2018 NXP +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H +-#define __DT_BINDINGS_CLOCK_IMX8MM_H +- +-#define IMX8MM_CLK_DUMMY 0 +-#define IMX8MM_CLK_32K 1 +-#define IMX8MM_CLK_24M 2 +-#define IMX8MM_OSC_HDMI_CLK 3 +-#define IMX8MM_CLK_EXT1 4 +-#define IMX8MM_CLK_EXT2 5 +-#define IMX8MM_CLK_EXT3 6 +-#define IMX8MM_CLK_EXT4 7 +-#define IMX8MM_AUDIO_PLL1_REF_SEL 8 +-#define IMX8MM_AUDIO_PLL2_REF_SEL 9 +-#define IMX8MM_VIDEO_PLL1_REF_SEL 10 +-#define IMX8MM_DRAM_PLL_REF_SEL 11 +-#define IMX8MM_GPU_PLL_REF_SEL 12 +-#define IMX8MM_VPU_PLL_REF_SEL 13 +-#define IMX8MM_ARM_PLL_REF_SEL 14 +-#define IMX8MM_SYS_PLL1_REF_SEL 15 +-#define IMX8MM_SYS_PLL2_REF_SEL 16 +-#define IMX8MM_SYS_PLL3_REF_SEL 17 +-#define IMX8MM_AUDIO_PLL1 18 +-#define IMX8MM_AUDIO_PLL2 19 +-#define IMX8MM_VIDEO_PLL1 20 +-#define IMX8MM_DRAM_PLL 21 +-#define IMX8MM_GPU_PLL 22 +-#define IMX8MM_VPU_PLL 23 +-#define IMX8MM_ARM_PLL 24 +-#define IMX8MM_SYS_PLL1 25 +-#define IMX8MM_SYS_PLL2 26 +-#define IMX8MM_SYS_PLL3 27 +-#define IMX8MM_AUDIO_PLL1_BYPASS 28 +-#define IMX8MM_AUDIO_PLL2_BYPASS 29 +-#define IMX8MM_VIDEO_PLL1_BYPASS 30 +-#define IMX8MM_DRAM_PLL_BYPASS 31 +-#define IMX8MM_GPU_PLL_BYPASS 32 +-#define IMX8MM_VPU_PLL_BYPASS 33 +-#define IMX8MM_ARM_PLL_BYPASS 34 +-#define IMX8MM_SYS_PLL1_BYPASS 35 +-#define IMX8MM_SYS_PLL2_BYPASS 36 +-#define IMX8MM_SYS_PLL3_BYPASS 37 +-#define IMX8MM_AUDIO_PLL1_OUT 38 +-#define IMX8MM_AUDIO_PLL2_OUT 39 +-#define IMX8MM_VIDEO_PLL1_OUT 40 +-#define IMX8MM_DRAM_PLL_OUT 41 +-#define IMX8MM_GPU_PLL_OUT 42 +-#define IMX8MM_VPU_PLL_OUT 43 +-#define IMX8MM_ARM_PLL_OUT 44 +-#define IMX8MM_SYS_PLL1_OUT 45 +-#define IMX8MM_SYS_PLL2_OUT 46 +-#define IMX8MM_SYS_PLL3_OUT 47 +-#define IMX8MM_SYS_PLL1_40M 48 +-#define IMX8MM_SYS_PLL1_80M 49 +-#define IMX8MM_SYS_PLL1_100M 50 +-#define IMX8MM_SYS_PLL1_133M 51 +-#define IMX8MM_SYS_PLL1_160M 52 +-#define IMX8MM_SYS_PLL1_200M 53 +-#define IMX8MM_SYS_PLL1_266M 54 +-#define IMX8MM_SYS_PLL1_400M 55 +-#define IMX8MM_SYS_PLL1_800M 56 +-#define IMX8MM_SYS_PLL2_50M 57 +-#define IMX8MM_SYS_PLL2_100M 58 +-#define IMX8MM_SYS_PLL2_125M 59 +-#define IMX8MM_SYS_PLL2_166M 60 +-#define IMX8MM_SYS_PLL2_200M 61 +-#define IMX8MM_SYS_PLL2_250M 62 +-#define IMX8MM_SYS_PLL2_333M 63 +-#define IMX8MM_SYS_PLL2_500M 64 +-#define IMX8MM_SYS_PLL2_1000M 65 +- +-/* core */ +-#define IMX8MM_CLK_A53_SRC 66 +-#define IMX8MM_CLK_M4_SRC 67 +-#define IMX8MM_CLK_VPU_SRC 68 +-#define IMX8MM_CLK_GPU3D_SRC 69 +-#define IMX8MM_CLK_GPU2D_SRC 70 +-#define IMX8MM_CLK_A53_CG 71 +-#define IMX8MM_CLK_M4_CG 72 +-#define IMX8MM_CLK_VPU_CG 73 +-#define IMX8MM_CLK_GPU3D_CG 74 +-#define IMX8MM_CLK_GPU2D_CG 75 +-#define IMX8MM_CLK_A53_DIV 76 +-#define IMX8MM_CLK_M4_DIV 77 +-#define IMX8MM_CLK_VPU_DIV 78 +-#define IMX8MM_CLK_GPU3D_DIV 79 +-#define IMX8MM_CLK_GPU2D_DIV 80 +- +-/* bus */ +-#define IMX8MM_CLK_MAIN_AXI 81 +-#define IMX8MM_CLK_ENET_AXI 82 +-#define IMX8MM_CLK_NAND_USDHC_BUS 83 +-#define IMX8MM_CLK_VPU_BUS 84 +-#define IMX8MM_CLK_DISP_AXI 85 +-#define IMX8MM_CLK_DISP_APB 86 +-#define IMX8MM_CLK_DISP_RTRM 87 +-#define IMX8MM_CLK_USB_BUS 88 +-#define IMX8MM_CLK_GPU_AXI 89 +-#define IMX8MM_CLK_GPU_AHB 90 +-#define IMX8MM_CLK_NOC 91 +-#define IMX8MM_CLK_NOC_APB 92 +- +-#define IMX8MM_CLK_AHB 93 +-#define IMX8MM_CLK_AUDIO_AHB 94 +-#define IMX8MM_CLK_IPG_ROOT 95 +-#define IMX8MM_CLK_IPG_AUDIO_ROOT 96 +- +-#define IMX8MM_CLK_DRAM_ALT 97 +-#define IMX8MM_CLK_DRAM_APB 98 +-#define IMX8MM_CLK_VPU_G1 99 +-#define IMX8MM_CLK_VPU_G2 100 +-#define IMX8MM_CLK_DISP_DTRC 101 +-#define IMX8MM_CLK_DISP_DC8000 102 +-#define IMX8MM_CLK_PCIE1_CTRL 103 +-#define IMX8MM_CLK_PCIE1_PHY 104 +-#define IMX8MM_CLK_PCIE1_AUX 105 +-#define IMX8MM_CLK_DC_PIXEL 106 +-#define IMX8MM_CLK_LCDIF_PIXEL 107 +-#define IMX8MM_CLK_SAI1 108 +-#define IMX8MM_CLK_SAI2 109 +-#define IMX8MM_CLK_SAI3 110 +-#define IMX8MM_CLK_SAI4 111 +-#define IMX8MM_CLK_SAI5 112 +-#define IMX8MM_CLK_SAI6 113 +-#define IMX8MM_CLK_SPDIF1 114 +-#define IMX8MM_CLK_SPDIF2 115 +-#define IMX8MM_CLK_ENET_REF 116 +-#define IMX8MM_CLK_ENET_TIMER 117 +-#define IMX8MM_CLK_ENET_PHY_REF 118 +-#define IMX8MM_CLK_NAND 119 +-#define IMX8MM_CLK_QSPI 120 +-#define IMX8MM_CLK_USDHC1 121 +-#define IMX8MM_CLK_USDHC2 122 +-#define IMX8MM_CLK_I2C1 123 +-#define IMX8MM_CLK_I2C2 124 +-#define IMX8MM_CLK_I2C3 125 +-#define IMX8MM_CLK_I2C4 126 +-#define IMX8MM_CLK_UART1 127 +-#define IMX8MM_CLK_UART2 128 +-#define IMX8MM_CLK_UART3 129 +-#define IMX8MM_CLK_UART4 130 +-#define IMX8MM_CLK_USB_CORE_REF 131 +-#define IMX8MM_CLK_USB_PHY_REF 132 +-#define IMX8MM_CLK_ECSPI1 133 +-#define IMX8MM_CLK_ECSPI2 134 +-#define IMX8MM_CLK_PWM1 135 +-#define IMX8MM_CLK_PWM2 136 +-#define IMX8MM_CLK_PWM3 137 +-#define IMX8MM_CLK_PWM4 138 +-#define IMX8MM_CLK_GPT1 139 +-#define IMX8MM_CLK_WDOG 140 +-#define IMX8MM_CLK_WRCLK 141 +-#define IMX8MM_CLK_DSI_CORE 142 +-#define IMX8MM_CLK_DSI_PHY_REF 143 +-#define IMX8MM_CLK_DSI_DBI 144 +-#define IMX8MM_CLK_USDHC3 145 +-#define IMX8MM_CLK_CSI1_CORE 146 +-#define IMX8MM_CLK_CSI1_PHY_REF 147 +-#define IMX8MM_CLK_CSI1_ESC 148 +-#define IMX8MM_CLK_CSI2_CORE 149 +-#define IMX8MM_CLK_CSI2_PHY_REF 150 +-#define IMX8MM_CLK_CSI2_ESC 151 +-#define IMX8MM_CLK_PCIE2_CTRL 152 +-#define IMX8MM_CLK_PCIE2_PHY 153 +-#define IMX8MM_CLK_PCIE2_AUX 154 +-#define IMX8MM_CLK_ECSPI3 155 +-#define IMX8MM_CLK_PDM 156 +-#define IMX8MM_CLK_VPU_H1 157 +-#define IMX8MM_CLK_CLKO1 158 +- +-#define IMX8MM_CLK_ECSPI1_ROOT 159 +-#define IMX8MM_CLK_ECSPI2_ROOT 160 +-#define IMX8MM_CLK_ECSPI3_ROOT 161 +-#define IMX8MM_CLK_ENET1_ROOT 162 +-#define IMX8MM_CLK_GPT1_ROOT 163 +-#define IMX8MM_CLK_I2C1_ROOT 164 +-#define IMX8MM_CLK_I2C2_ROOT 165 +-#define IMX8MM_CLK_I2C3_ROOT 166 +-#define IMX8MM_CLK_I2C4_ROOT 167 +-#define IMX8MM_CLK_OCOTP_ROOT 168 +-#define IMX8MM_CLK_PCIE1_ROOT 169 +-#define IMX8MM_CLK_PWM1_ROOT 170 +-#define IMX8MM_CLK_PWM2_ROOT 171 +-#define IMX8MM_CLK_PWM3_ROOT 172 +-#define IMX8MM_CLK_PWM4_ROOT 173 +-#define IMX8MM_CLK_QSPI_ROOT 174 +-#define IMX8MM_CLK_NAND_ROOT 175 +-#define IMX8MM_CLK_SAI1_ROOT 176 +-#define IMX8MM_CLK_SAI1_IPG 177 +-#define IMX8MM_CLK_SAI2_ROOT 178 +-#define IMX8MM_CLK_SAI2_IPG 179 +-#define IMX8MM_CLK_SAI3_ROOT 180 +-#define IMX8MM_CLK_SAI3_IPG 181 +-#define IMX8MM_CLK_SAI4_ROOT 182 +-#define IMX8MM_CLK_SAI4_IPG 183 +-#define IMX8MM_CLK_SAI5_ROOT 184 +-#define IMX8MM_CLK_SAI5_IPG 185 +-#define IMX8MM_CLK_SAI6_ROOT 186 +-#define IMX8MM_CLK_SAI6_IPG 187 +-#define IMX8MM_CLK_UART1_ROOT 188 +-#define IMX8MM_CLK_UART2_ROOT 189 +-#define IMX8MM_CLK_UART3_ROOT 190 +-#define IMX8MM_CLK_UART4_ROOT 191 +-#define IMX8MM_CLK_USB1_CTRL_ROOT 192 +-#define IMX8MM_CLK_GPU3D_ROOT 193 +-#define IMX8MM_CLK_USDHC1_ROOT 194 +-#define IMX8MM_CLK_USDHC2_ROOT 195 +-#define IMX8MM_CLK_WDOG1_ROOT 196 +-#define IMX8MM_CLK_WDOG2_ROOT 197 +-#define IMX8MM_CLK_WDOG3_ROOT 198 +-#define IMX8MM_CLK_VPU_G1_ROOT 199 +-#define IMX8MM_CLK_GPU_BUS_ROOT 200 +-#define IMX8MM_CLK_VPU_H1_ROOT 201 +-#define IMX8MM_CLK_VPU_G2_ROOT 202 +-#define IMX8MM_CLK_PDM_ROOT 203 +-#define IMX8MM_CLK_DISP_ROOT 204 +-#define IMX8MM_CLK_DISP_AXI_ROOT 205 +-#define IMX8MM_CLK_DISP_APB_ROOT 206 +-#define IMX8MM_CLK_DISP_RTRM_ROOT 207 +-#define IMX8MM_CLK_USDHC3_ROOT 208 +-#define IMX8MM_CLK_TMU_ROOT 209 +-#define IMX8MM_CLK_VPU_DEC_ROOT 210 +-#define IMX8MM_CLK_SDMA1_ROOT 211 +-#define IMX8MM_CLK_SDMA2_ROOT 212 +-#define IMX8MM_CLK_SDMA3_ROOT 213 +-#define IMX8MM_CLK_GPT_3M 214 +-#define IMX8MM_CLK_ARM 215 +-#define IMX8MM_CLK_PDM_IPG 216 +-#define IMX8MM_CLK_GPU2D_ROOT 217 +-#define IMX8MM_CLK_MU_ROOT 218 +-#define IMX8MM_CLK_CSI1_ROOT 219 +- +-#define IMX8MM_CLK_DRAM_CORE 220 +-#define IMX8MM_CLK_DRAM_ALT_ROOT 221 +- +-#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222 +- +-#define IMX8MM_CLK_GPIO1_ROOT 223 +-#define IMX8MM_CLK_GPIO2_ROOT 224 +-#define IMX8MM_CLK_GPIO3_ROOT 225 +-#define IMX8MM_CLK_GPIO4_ROOT 226 +-#define IMX8MM_CLK_GPIO5_ROOT 227 +- +-#define IMX8MM_CLK_SNVS_ROOT 228 +-#define IMX8MM_CLK_GIC 229 +- +-#define IMX8MM_SYS_PLL1_40M_CG 230 +-#define IMX8MM_SYS_PLL1_80M_CG 231 +-#define IMX8MM_SYS_PLL1_100M_CG 232 +-#define IMX8MM_SYS_PLL1_133M_CG 233 +-#define IMX8MM_SYS_PLL1_160M_CG 234 +-#define IMX8MM_SYS_PLL1_200M_CG 235 +-#define IMX8MM_SYS_PLL1_266M_CG 236 +-#define IMX8MM_SYS_PLL1_400M_CG 237 +-#define IMX8MM_SYS_PLL2_50M_CG 238 +-#define IMX8MM_SYS_PLL2_100M_CG 239 +-#define IMX8MM_SYS_PLL2_125M_CG 240 +-#define IMX8MM_SYS_PLL2_166M_CG 241 +-#define IMX8MM_SYS_PLL2_200M_CG 242 +-#define IMX8MM_SYS_PLL2_250M_CG 243 +-#define IMX8MM_SYS_PLL2_333M_CG 244 +-#define IMX8MM_SYS_PLL2_500M_CG 245 +- +-#define IMX8MM_CLK_M4_CORE 246 +-#define IMX8MM_CLK_VPU_CORE 247 +-#define IMX8MM_CLK_GPU3D_CORE 248 +-#define IMX8MM_CLK_GPU2D_CORE 249 +- +-#define IMX8MM_CLK_CLKO2 250 +- +-#define IMX8MM_CLK_A53_CORE 251 +- +-#define IMX8MM_CLK_CLKOUT1_SEL 252 +-#define IMX8MM_CLK_CLKOUT1_DIV 253 +-#define IMX8MM_CLK_CLKOUT1 254 +-#define IMX8MM_CLK_CLKOUT2_SEL 255 +-#define IMX8MM_CLK_CLKOUT2_DIV 256 +-#define IMX8MM_CLK_CLKOUT2 257 +- +- +-#define IMX8MM_CLK_END 258 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/imx8mn-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/imx8mn-clock.h +deleted file mode 100644 +index 01e8bab1d767..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/imx8mn-clock.h ++++ /dev/null +@@ -1,248 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright 2018-2019 NXP +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H +-#define __DT_BINDINGS_CLOCK_IMX8MN_H +- +-#define IMX8MN_CLK_DUMMY 0 +-#define IMX8MN_CLK_32K 1 +-#define IMX8MN_CLK_24M 2 +-#define IMX8MN_OSC_HDMI_CLK 3 +-#define IMX8MN_CLK_EXT1 4 +-#define IMX8MN_CLK_EXT2 5 +-#define IMX8MN_CLK_EXT3 6 +-#define IMX8MN_CLK_EXT4 7 +-#define IMX8MN_AUDIO_PLL1_REF_SEL 8 +-#define IMX8MN_AUDIO_PLL2_REF_SEL 9 +-#define IMX8MN_VIDEO_PLL1_REF_SEL 10 +-#define IMX8MN_DRAM_PLL_REF_SEL 11 +-#define IMX8MN_GPU_PLL_REF_SEL 12 +-#define IMX8MN_VPU_PLL_REF_SEL 13 +-#define IMX8MN_ARM_PLL_REF_SEL 14 +-#define IMX8MN_SYS_PLL1_REF_SEL 15 +-#define IMX8MN_SYS_PLL2_REF_SEL 16 +-#define IMX8MN_SYS_PLL3_REF_SEL 17 +-#define IMX8MN_AUDIO_PLL1 18 +-#define IMX8MN_AUDIO_PLL2 19 +-#define IMX8MN_VIDEO_PLL1 20 +-#define IMX8MN_DRAM_PLL 21 +-#define IMX8MN_GPU_PLL 22 +-#define IMX8MN_VPU_PLL 23 +-#define IMX8MN_ARM_PLL 24 +-#define IMX8MN_SYS_PLL1 25 +-#define IMX8MN_SYS_PLL2 26 +-#define IMX8MN_SYS_PLL3 27 +-#define IMX8MN_AUDIO_PLL1_BYPASS 28 +-#define IMX8MN_AUDIO_PLL2_BYPASS 29 +-#define IMX8MN_VIDEO_PLL1_BYPASS 30 +-#define IMX8MN_DRAM_PLL_BYPASS 31 +-#define IMX8MN_GPU_PLL_BYPASS 32 +-#define IMX8MN_VPU_PLL_BYPASS 33 +-#define IMX8MN_ARM_PLL_BYPASS 34 +-#define IMX8MN_SYS_PLL1_BYPASS 35 +-#define IMX8MN_SYS_PLL2_BYPASS 36 +-#define IMX8MN_SYS_PLL3_BYPASS 37 +-#define IMX8MN_AUDIO_PLL1_OUT 38 +-#define IMX8MN_AUDIO_PLL2_OUT 39 +-#define IMX8MN_VIDEO_PLL1_OUT 40 +-#define IMX8MN_DRAM_PLL_OUT 41 +-#define IMX8MN_GPU_PLL_OUT 42 +-#define IMX8MN_VPU_PLL_OUT 43 +-#define IMX8MN_ARM_PLL_OUT 44 +-#define IMX8MN_SYS_PLL1_OUT 45 +-#define IMX8MN_SYS_PLL2_OUT 46 +-#define IMX8MN_SYS_PLL3_OUT 47 +-#define IMX8MN_SYS_PLL1_40M 48 +-#define IMX8MN_SYS_PLL1_80M 49 +-#define IMX8MN_SYS_PLL1_100M 50 +-#define IMX8MN_SYS_PLL1_133M 51 +-#define IMX8MN_SYS_PLL1_160M 52 +-#define IMX8MN_SYS_PLL1_200M 53 +-#define IMX8MN_SYS_PLL1_266M 54 +-#define IMX8MN_SYS_PLL1_400M 55 +-#define IMX8MN_SYS_PLL1_800M 56 +-#define IMX8MN_SYS_PLL2_50M 57 +-#define IMX8MN_SYS_PLL2_100M 58 +-#define IMX8MN_SYS_PLL2_125M 59 +-#define IMX8MN_SYS_PLL2_166M 60 +-#define IMX8MN_SYS_PLL2_200M 61 +-#define IMX8MN_SYS_PLL2_250M 62 +-#define IMX8MN_SYS_PLL2_333M 63 +-#define IMX8MN_SYS_PLL2_500M 64 +-#define IMX8MN_SYS_PLL2_1000M 65 +- +-/* CORE CLOCK ROOT */ +-#define IMX8MN_CLK_A53_SRC 66 +-#define IMX8MN_CLK_GPU_CORE_SRC 67 +-#define IMX8MN_CLK_GPU_SHADER_SRC 68 +-#define IMX8MN_CLK_A53_CG 69 +-#define IMX8MN_CLK_GPU_CORE_CG 70 +-#define IMX8MN_CLK_GPU_SHADER_CG 71 +-#define IMX8MN_CLK_A53_DIV 72 +-#define IMX8MN_CLK_GPU_CORE_DIV 73 +-#define IMX8MN_CLK_GPU_SHADER_DIV 74 +- +-/* BUS CLOCK ROOT */ +-#define IMX8MN_CLK_MAIN_AXI 75 +-#define IMX8MN_CLK_ENET_AXI 76 +-#define IMX8MN_CLK_NAND_USDHC_BUS 77 +-#define IMX8MN_CLK_DISP_AXI 78 +-#define IMX8MN_CLK_DISP_APB 79 +-#define IMX8MN_CLK_USB_BUS 80 +-#define IMX8MN_CLK_GPU_AXI 81 +-#define IMX8MN_CLK_GPU_AHB 82 +-#define IMX8MN_CLK_NOC 83 +-#define IMX8MN_CLK_AHB 84 +-#define IMX8MN_CLK_AUDIO_AHB 85 +- +-/* IPG CLOCK ROOT */ +-#define IMX8MN_CLK_IPG_ROOT 86 +-#define IMX8MN_CLK_IPG_AUDIO_ROOT 87 +- +-/* IP */ +-#define IMX8MN_CLK_DRAM_CORE 88 +-#define IMX8MN_CLK_DRAM_ALT 89 +-#define IMX8MN_CLK_DRAM_APB 90 +-#define IMX8MN_CLK_DRAM_ALT_ROOT 91 +-#define IMX8MN_CLK_DISP_PIXEL 92 +-#define IMX8MN_CLK_SAI2 93 +-#define IMX8MN_CLK_SAI3 94 +-#define IMX8MN_CLK_SAI5 95 +-#define IMX8MN_CLK_SAI6 96 +-#define IMX8MN_CLK_SPDIF1 97 +-#define IMX8MN_CLK_ENET_REF 98 +-#define IMX8MN_CLK_ENET_TIMER 99 +-#define IMX8MN_CLK_ENET_PHY_REF 100 +-#define IMX8MN_CLK_NAND 101 +-#define IMX8MN_CLK_QSPI 102 +-#define IMX8MN_CLK_USDHC1 103 +-#define IMX8MN_CLK_USDHC2 104 +-#define IMX8MN_CLK_I2C1 105 +-#define IMX8MN_CLK_I2C2 106 +-#define IMX8MN_CLK_I2C3 107 +-#define IMX8MN_CLK_I2C4 108 +-#define IMX8MN_CLK_UART1 109 +-#define IMX8MN_CLK_UART2 110 +-#define IMX8MN_CLK_UART3 111 +-#define IMX8MN_CLK_UART4 112 +-#define IMX8MN_CLK_USB_CORE_REF 113 +-#define IMX8MN_CLK_USB_PHY_REF 114 +-#define IMX8MN_CLK_ECSPI1 115 +-#define IMX8MN_CLK_ECSPI2 116 +-#define IMX8MN_CLK_PWM1 117 +-#define IMX8MN_CLK_PWM2 118 +-#define IMX8MN_CLK_PWM3 119 +-#define IMX8MN_CLK_PWM4 120 +-#define IMX8MN_CLK_WDOG 121 +-#define IMX8MN_CLK_WRCLK 122 +-#define IMX8MN_CLK_CLKO1 123 +-#define IMX8MN_CLK_CLKO2 124 +-#define IMX8MN_CLK_DSI_CORE 125 +-#define IMX8MN_CLK_DSI_PHY_REF 126 +-#define IMX8MN_CLK_DSI_DBI 127 +-#define IMX8MN_CLK_USDHC3 128 +-#define IMX8MN_CLK_CAMERA_PIXEL 129 +-#define IMX8MN_CLK_CSI1_PHY_REF 130 +-#define IMX8MN_CLK_CSI2_PHY_REF 131 +-#define IMX8MN_CLK_CSI2_ESC 132 +-#define IMX8MN_CLK_ECSPI3 133 +-#define IMX8MN_CLK_PDM 134 +-#define IMX8MN_CLK_SAI7 135 +- +-#define IMX8MN_CLK_ECSPI1_ROOT 136 +-#define IMX8MN_CLK_ECSPI2_ROOT 137 +-#define IMX8MN_CLK_ECSPI3_ROOT 138 +-#define IMX8MN_CLK_ENET1_ROOT 139 +-#define IMX8MN_CLK_GPIO1_ROOT 140 +-#define IMX8MN_CLK_GPIO2_ROOT 141 +-#define IMX8MN_CLK_GPIO3_ROOT 142 +-#define IMX8MN_CLK_GPIO4_ROOT 143 +-#define IMX8MN_CLK_GPIO5_ROOT 144 +-#define IMX8MN_CLK_I2C1_ROOT 145 +-#define IMX8MN_CLK_I2C2_ROOT 146 +-#define IMX8MN_CLK_I2C3_ROOT 147 +-#define IMX8MN_CLK_I2C4_ROOT 148 +-#define IMX8MN_CLK_MU_ROOT 149 +-#define IMX8MN_CLK_OCOTP_ROOT 150 +-#define IMX8MN_CLK_PWM1_ROOT 151 +-#define IMX8MN_CLK_PWM2_ROOT 152 +-#define IMX8MN_CLK_PWM3_ROOT 153 +-#define IMX8MN_CLK_PWM4_ROOT 154 +-#define IMX8MN_CLK_QSPI_ROOT 155 +-#define IMX8MN_CLK_NAND_ROOT 156 +-#define IMX8MN_CLK_SAI2_ROOT 157 +-#define IMX8MN_CLK_SAI2_IPG 158 +-#define IMX8MN_CLK_SAI3_ROOT 159 +-#define IMX8MN_CLK_SAI3_IPG 160 +-#define IMX8MN_CLK_SAI5_ROOT 161 +-#define IMX8MN_CLK_SAI5_IPG 162 +-#define IMX8MN_CLK_SAI6_ROOT 163 +-#define IMX8MN_CLK_SAI6_IPG 164 +-#define IMX8MN_CLK_SAI7_ROOT 165 +-#define IMX8MN_CLK_SAI7_IPG 166 +-#define IMX8MN_CLK_SDMA1_ROOT 167 +-#define IMX8MN_CLK_SDMA2_ROOT 168 +-#define IMX8MN_CLK_UART1_ROOT 169 +-#define IMX8MN_CLK_UART2_ROOT 170 +-#define IMX8MN_CLK_UART3_ROOT 171 +-#define IMX8MN_CLK_UART4_ROOT 172 +-#define IMX8MN_CLK_USB1_CTRL_ROOT 173 +-#define IMX8MN_CLK_USDHC1_ROOT 174 +-#define IMX8MN_CLK_USDHC2_ROOT 175 +-#define IMX8MN_CLK_WDOG1_ROOT 176 +-#define IMX8MN_CLK_WDOG2_ROOT 177 +-#define IMX8MN_CLK_WDOG3_ROOT 178 +-#define IMX8MN_CLK_GPU_BUS_ROOT 179 +-#define IMX8MN_CLK_ASRC_ROOT 180 +-#define IMX8MN_CLK_GPU3D_ROOT 181 +-#define IMX8MN_CLK_PDM_ROOT 182 +-#define IMX8MN_CLK_PDM_IPG 183 +-#define IMX8MN_CLK_DISP_AXI_ROOT 184 +-#define IMX8MN_CLK_DISP_APB_ROOT 185 +-#define IMX8MN_CLK_DISP_PIXEL_ROOT 186 +-#define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187 +-#define IMX8MN_CLK_USDHC3_ROOT 188 +-#define IMX8MN_CLK_SDMA3_ROOT 189 +-#define IMX8MN_CLK_TMU_ROOT 190 +-#define IMX8MN_CLK_ARM 191 +-#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192 +-#define IMX8MN_CLK_GPU_CORE_ROOT 193 +-#define IMX8MN_CLK_GIC 194 +- +-#define IMX8MN_SYS_PLL1_40M_CG 195 +-#define IMX8MN_SYS_PLL1_80M_CG 196 +-#define IMX8MN_SYS_PLL1_100M_CG 197 +-#define IMX8MN_SYS_PLL1_133M_CG 198 +-#define IMX8MN_SYS_PLL1_160M_CG 199 +-#define IMX8MN_SYS_PLL1_200M_CG 200 +-#define IMX8MN_SYS_PLL1_266M_CG 201 +-#define IMX8MN_SYS_PLL1_400M_CG 202 +-#define IMX8MN_SYS_PLL2_50M_CG 203 +-#define IMX8MN_SYS_PLL2_100M_CG 204 +-#define IMX8MN_SYS_PLL2_125M_CG 205 +-#define IMX8MN_SYS_PLL2_166M_CG 206 +-#define IMX8MN_SYS_PLL2_200M_CG 207 +-#define IMX8MN_SYS_PLL2_250M_CG 208 +-#define IMX8MN_SYS_PLL2_333M_CG 209 +-#define IMX8MN_SYS_PLL2_500M_CG 210 +- +-#define IMX8MN_CLK_SNVS_ROOT 211 +-#define IMX8MN_CLK_GPU_CORE 212 +-#define IMX8MN_CLK_GPU_SHADER 213 +- +-#define IMX8MN_CLK_A53_CORE 214 +- +-#define IMX8MN_CLK_CLKOUT1_SEL 215 +-#define IMX8MN_CLK_CLKOUT1_DIV 216 +-#define IMX8MN_CLK_CLKOUT1 217 +-#define IMX8MN_CLK_CLKOUT2_SEL 218 +-#define IMX8MN_CLK_CLKOUT2_DIV 219 +-#define IMX8MN_CLK_CLKOUT2 220 +- +-#define IMX8MN_CLK_M7_CORE 221 +- +-#define IMX8MN_CLK_END 222 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/imx8mp-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/imx8mp-clock.h +deleted file mode 100644 +index 43927a1b9e94..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/imx8mp-clock.h ++++ /dev/null +@@ -1,386 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright 2019 NXP +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_IMX8MP_H +-#define __DT_BINDINGS_CLOCK_IMX8MP_H +- +-#define IMX8MP_CLK_DUMMY 0 +-#define IMX8MP_CLK_32K 1 +-#define IMX8MP_CLK_24M 2 +-#define IMX8MP_OSC_HDMI_CLK 3 +-#define IMX8MP_CLK_EXT1 4 +-#define IMX8MP_CLK_EXT2 5 +-#define IMX8MP_CLK_EXT3 6 +-#define IMX8MP_CLK_EXT4 7 +-#define IMX8MP_AUDIO_PLL1_REF_SEL 8 +-#define IMX8MP_AUDIO_PLL2_REF_SEL 9 +-#define IMX8MP_VIDEO_PLL1_REF_SEL 10 +-#define IMX8MP_DRAM_PLL_REF_SEL 11 +-#define IMX8MP_GPU_PLL_REF_SEL 12 +-#define IMX8MP_VPU_PLL_REF_SEL 13 +-#define IMX8MP_ARM_PLL_REF_SEL 14 +-#define IMX8MP_SYS_PLL1_REF_SEL 15 +-#define IMX8MP_SYS_PLL2_REF_SEL 16 +-#define IMX8MP_SYS_PLL3_REF_SEL 17 +-#define IMX8MP_AUDIO_PLL1 18 +-#define IMX8MP_AUDIO_PLL2 19 +-#define IMX8MP_VIDEO_PLL1 20 +-#define IMX8MP_DRAM_PLL 21 +-#define IMX8MP_GPU_PLL 22 +-#define IMX8MP_VPU_PLL 23 +-#define IMX8MP_ARM_PLL 24 +-#define IMX8MP_SYS_PLL1 25 +-#define IMX8MP_SYS_PLL2 26 +-#define IMX8MP_SYS_PLL3 27 +-#define IMX8MP_AUDIO_PLL1_BYPASS 28 +-#define IMX8MP_AUDIO_PLL2_BYPASS 29 +-#define IMX8MP_VIDEO_PLL1_BYPASS 30 +-#define IMX8MP_DRAM_PLL_BYPASS 31 +-#define IMX8MP_GPU_PLL_BYPASS 32 +-#define IMX8MP_VPU_PLL_BYPASS 33 +-#define IMX8MP_ARM_PLL_BYPASS 34 +-#define IMX8MP_SYS_PLL1_BYPASS 35 +-#define IMX8MP_SYS_PLL2_BYPASS 36 +-#define IMX8MP_SYS_PLL3_BYPASS 37 +-#define IMX8MP_AUDIO_PLL1_OUT 38 +-#define IMX8MP_AUDIO_PLL2_OUT 39 +-#define IMX8MP_VIDEO_PLL1_OUT 40 +-#define IMX8MP_DRAM_PLL_OUT 41 +-#define IMX8MP_GPU_PLL_OUT 42 +-#define IMX8MP_VPU_PLL_OUT 43 +-#define IMX8MP_ARM_PLL_OUT 44 +-#define IMX8MP_SYS_PLL1_OUT 45 +-#define IMX8MP_SYS_PLL2_OUT 46 +-#define IMX8MP_SYS_PLL3_OUT 47 +-#define IMX8MP_SYS_PLL1_40M 48 +-#define IMX8MP_SYS_PLL1_80M 49 +-#define IMX8MP_SYS_PLL1_100M 50 +-#define IMX8MP_SYS_PLL1_133M 51 +-#define IMX8MP_SYS_PLL1_160M 52 +-#define IMX8MP_SYS_PLL1_200M 53 +-#define IMX8MP_SYS_PLL1_266M 54 +-#define IMX8MP_SYS_PLL1_400M 55 +-#define IMX8MP_SYS_PLL1_800M 56 +-#define IMX8MP_SYS_PLL2_50M 57 +-#define IMX8MP_SYS_PLL2_100M 58 +-#define IMX8MP_SYS_PLL2_125M 59 +-#define IMX8MP_SYS_PLL2_166M 60 +-#define IMX8MP_SYS_PLL2_200M 61 +-#define IMX8MP_SYS_PLL2_250M 62 +-#define IMX8MP_SYS_PLL2_333M 63 +-#define IMX8MP_SYS_PLL2_500M 64 +-#define IMX8MP_SYS_PLL2_1000M 65 +-#define IMX8MP_CLK_A53_SRC 66 +-#define IMX8MP_CLK_M7_SRC 67 +-#define IMX8MP_CLK_ML_SRC 68 +-#define IMX8MP_CLK_GPU3D_CORE_SRC 69 +-#define IMX8MP_CLK_GPU3D_SHADER_SRC 70 +-#define IMX8MP_CLK_GPU2D_SRC 71 +-#define IMX8MP_CLK_AUDIO_AXI_SRC 72 +-#define IMX8MP_CLK_HSIO_AXI_SRC 73 +-#define IMX8MP_CLK_MEDIA_ISP_SRC 74 +-#define IMX8MP_CLK_A53_CG 75 +-#define IMX8MP_CLK_M4_CG 76 +-#define IMX8MP_CLK_ML_CG 77 +-#define IMX8MP_CLK_GPU3D_CORE_CG 78 +-#define IMX8MP_CLK_GPU3D_SHADER_CG 79 +-#define IMX8MP_CLK_GPU2D_CG 80 +-#define IMX8MP_CLK_AUDIO_AXI_CG 81 +-#define IMX8MP_CLK_HSIO_AXI_CG 82 +-#define IMX8MP_CLK_MEDIA_ISP_CG 83 +-#define IMX8MP_CLK_A53_DIV 84 +-#define IMX8MP_CLK_M7_DIV 85 +-#define IMX8MP_CLK_ML_DIV 86 +-#define IMX8MP_CLK_GPU3D_CORE_DIV 87 +-#define IMX8MP_CLK_GPU3D_SHADER_DIV 88 +-#define IMX8MP_CLK_GPU2D_DIV 89 +-#define IMX8MP_CLK_AUDIO_AXI_DIV 90 +-#define IMX8MP_CLK_HSIO_AXI_DIV 91 +-#define IMX8MP_CLK_MEDIA_ISP_DIV 92 +-#define IMX8MP_CLK_MAIN_AXI 93 +-#define IMX8MP_CLK_ENET_AXI 94 +-#define IMX8MP_CLK_NAND_USDHC_BUS 95 +-#define IMX8MP_CLK_VPU_BUS 96 +-#define IMX8MP_CLK_MEDIA_AXI 97 +-#define IMX8MP_CLK_MEDIA_APB 98 +-#define IMX8MP_CLK_HDMI_APB 99 +-#define IMX8MP_CLK_HDMI_AXI 100 +-#define IMX8MP_CLK_GPU_AXI 101 +-#define IMX8MP_CLK_GPU_AHB 102 +-#define IMX8MP_CLK_NOC 103 +-#define IMX8MP_CLK_NOC_IO 104 +-#define IMX8MP_CLK_ML_AXI 105 +-#define IMX8MP_CLK_ML_AHB 106 +-#define IMX8MP_CLK_AHB 107 +-#define IMX8MP_CLK_AUDIO_AHB 108 +-#define IMX8MP_CLK_MIPI_DSI_ESC_RX 109 +-#define IMX8MP_CLK_IPG_ROOT 110 +-#define IMX8MP_CLK_IPG_AUDIO_ROOT 111 +-#define IMX8MP_CLK_DRAM_ALT 112 +-#define IMX8MP_CLK_DRAM_APB 113 +-#define IMX8MP_CLK_VPU_G1 114 +-#define IMX8MP_CLK_VPU_G2 115 +-#define IMX8MP_CLK_CAN1 116 +-#define IMX8MP_CLK_CAN2 117 +-#define IMX8MP_CLK_MEMREPAIR 118 +-#define IMX8MP_CLK_PCIE_AUX 120 +-#define IMX8MP_CLK_I2C5 121 +-#define IMX8MP_CLK_I2C6 122 +-#define IMX8MP_CLK_SAI1 123 +-#define IMX8MP_CLK_SAI2 124 +-#define IMX8MP_CLK_SAI3 125 +-#define IMX8MP_CLK_SAI4 126 +-#define IMX8MP_CLK_SAI5 127 +-#define IMX8MP_CLK_SAI6 128 +-#define IMX8MP_CLK_ENET_QOS 129 +-#define IMX8MP_CLK_ENET_QOS_TIMER 130 +-#define IMX8MP_CLK_ENET_REF 131 +-#define IMX8MP_CLK_ENET_TIMER 132 +-#define IMX8MP_CLK_ENET_PHY_REF 133 +-#define IMX8MP_CLK_NAND 134 +-#define IMX8MP_CLK_QSPI 135 +-#define IMX8MP_CLK_USDHC1 136 +-#define IMX8MP_CLK_USDHC2 137 +-#define IMX8MP_CLK_I2C1 138 +-#define IMX8MP_CLK_I2C2 139 +-#define IMX8MP_CLK_I2C3 140 +-#define IMX8MP_CLK_I2C4 141 +-#define IMX8MP_CLK_UART1 142 +-#define IMX8MP_CLK_UART2 143 +-#define IMX8MP_CLK_UART3 144 +-#define IMX8MP_CLK_UART4 145 +-#define IMX8MP_CLK_USB_CORE_REF 146 +-#define IMX8MP_CLK_USB_PHY_REF 147 +-#define IMX8MP_CLK_GIC 148 +-#define IMX8MP_CLK_ECSPI1 149 +-#define IMX8MP_CLK_ECSPI2 150 +-#define IMX8MP_CLK_PWM1 151 +-#define IMX8MP_CLK_PWM2 152 +-#define IMX8MP_CLK_PWM3 153 +-#define IMX8MP_CLK_PWM4 154 +-#define IMX8MP_CLK_GPT1 155 +-#define IMX8MP_CLK_GPT2 156 +-#define IMX8MP_CLK_GPT3 157 +-#define IMX8MP_CLK_GPT4 158 +-#define IMX8MP_CLK_GPT5 159 +-#define IMX8MP_CLK_GPT6 160 +-#define IMX8MP_CLK_TRACE 161 +-#define IMX8MP_CLK_WDOG 162 +-#define IMX8MP_CLK_WRCLK 163 +-#define IMX8MP_CLK_IPP_DO_CLKO1 164 +-#define IMX8MP_CLK_IPP_DO_CLKO2 165 +-#define IMX8MP_CLK_HDMI_FDCC_TST 166 +-#define IMX8MP_CLK_HDMI_24M 167 +-#define IMX8MP_CLK_HDMI_REF_266M 168 +-#define IMX8MP_CLK_USDHC3 169 +-#define IMX8MP_CLK_MEDIA_CAM1_PIX 170 +-#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF 171 +-#define IMX8MP_CLK_MEDIA_DISP1_PIX 172 +-#define IMX8MP_CLK_MEDIA_CAM2_PIX 173 +-#define IMX8MP_CLK_MEDIA_LDB 174 +-#define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175 +-#define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178 +-#define IMX8MP_CLK_ECSPI3 179 +-#define IMX8MP_CLK_PDM 180 +-#define IMX8MP_CLK_VPU_VC8000E 181 +-#define IMX8MP_CLK_SAI7 182 +-#define IMX8MP_CLK_GPC_ROOT 183 +-#define IMX8MP_CLK_ANAMIX_ROOT 184 +-#define IMX8MP_CLK_CPU_ROOT 185 +-#define IMX8MP_CLK_CSU_ROOT 186 +-#define IMX8MP_CLK_DEBUG_ROOT 187 +-#define IMX8MP_CLK_DRAM1_ROOT 188 +-#define IMX8MP_CLK_ECSPI1_ROOT 189 +-#define IMX8MP_CLK_ECSPI2_ROOT 190 +-#define IMX8MP_CLK_ECSPI3_ROOT 191 +-#define IMX8MP_CLK_ENET1_ROOT 192 +-#define IMX8MP_CLK_GPIO1_ROOT 193 +-#define IMX8MP_CLK_GPIO2_ROOT 194 +-#define IMX8MP_CLK_GPIO3_ROOT 195 +-#define IMX8MP_CLK_GPIO4_ROOT 196 +-#define IMX8MP_CLK_GPIO5_ROOT 197 +-#define IMX8MP_CLK_GPT1_ROOT 198 +-#define IMX8MP_CLK_GPT2_ROOT 199 +-#define IMX8MP_CLK_GPT3_ROOT 200 +-#define IMX8MP_CLK_GPT4_ROOT 201 +-#define IMX8MP_CLK_GPT5_ROOT 202 +-#define IMX8MP_CLK_GPT6_ROOT 203 +-#define IMX8MP_CLK_HS_ROOT 204 +-#define IMX8MP_CLK_I2C1_ROOT 205 +-#define IMX8MP_CLK_I2C2_ROOT 206 +-#define IMX8MP_CLK_I2C3_ROOT 207 +-#define IMX8MP_CLK_I2C4_ROOT 208 +-#define IMX8MP_CLK_IOMUX_ROOT 209 +-#define IMX8MP_CLK_IPMUX1_ROOT 210 +-#define IMX8MP_CLK_IPMUX2_ROOT 211 +-#define IMX8MP_CLK_IPMUX3_ROOT 212 +-#define IMX8MP_CLK_MU_ROOT 213 +-#define IMX8MP_CLK_OCOTP_ROOT 214 +-#define IMX8MP_CLK_OCRAM_ROOT 215 +-#define IMX8MP_CLK_OCRAM_S_ROOT 216 +-#define IMX8MP_CLK_PCIE_ROOT 217 +-#define IMX8MP_CLK_PERFMON1_ROOT 218 +-#define IMX8MP_CLK_PERFMON2_ROOT 219 +-#define IMX8MP_CLK_PWM1_ROOT 220 +-#define IMX8MP_CLK_PWM2_ROOT 221 +-#define IMX8MP_CLK_PWM3_ROOT 222 +-#define IMX8MP_CLK_PWM4_ROOT 223 +-#define IMX8MP_CLK_QOS_ROOT 224 +-#define IMX8MP_CLK_QOS_ENET_ROOT 225 +-#define IMX8MP_CLK_QSPI_ROOT 226 +-#define IMX8MP_CLK_NAND_ROOT 227 +-#define IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK 228 +-#define IMX8MP_CLK_RDC_ROOT 229 +-#define IMX8MP_CLK_ROM_ROOT 230 +-#define IMX8MP_CLK_I2C5_ROOT 231 +-#define IMX8MP_CLK_I2C6_ROOT 232 +-#define IMX8MP_CLK_CAN1_ROOT 233 +-#define IMX8MP_CLK_CAN2_ROOT 234 +-#define IMX8MP_CLK_SCTR_ROOT 235 +-#define IMX8MP_CLK_SDMA1_ROOT 236 +-#define IMX8MP_CLK_ENET_QOS_ROOT 237 +-#define IMX8MP_CLK_SEC_DEBUG_ROOT 238 +-#define IMX8MP_CLK_SEMA1_ROOT 239 +-#define IMX8MP_CLK_SEMA2_ROOT 240 +-#define IMX8MP_CLK_IRQ_STEER_ROOT 241 +-#define IMX8MP_CLK_SIM_ENET_ROOT 242 +-#define IMX8MP_CLK_SIM_M_ROOT 243 +-#define IMX8MP_CLK_SIM_MAIN_ROOT 244 +-#define IMX8MP_CLK_SIM_S_ROOT 245 +-#define IMX8MP_CLK_SIM_WAKEUP_ROOT 246 +-#define IMX8MP_CLK_GPU2D_ROOT 247 +-#define IMX8MP_CLK_GPU3D_ROOT 248 +-#define IMX8MP_CLK_SNVS_ROOT 249 +-#define IMX8MP_CLK_TRACE_ROOT 250 +-#define IMX8MP_CLK_UART1_ROOT 251 +-#define IMX8MP_CLK_UART2_ROOT 252 +-#define IMX8MP_CLK_UART3_ROOT 253 +-#define IMX8MP_CLK_UART4_ROOT 254 +-#define IMX8MP_CLK_USB_ROOT 255 +-#define IMX8MP_CLK_USB_PHY_ROOT 256 +-#define IMX8MP_CLK_USDHC1_ROOT 257 +-#define IMX8MP_CLK_USDHC2_ROOT 258 +-#define IMX8MP_CLK_WDOG1_ROOT 259 +-#define IMX8MP_CLK_WDOG2_ROOT 260 +-#define IMX8MP_CLK_WDOG3_ROOT 261 +-#define IMX8MP_CLK_VPU_G1_ROOT 262 +-#define IMX8MP_CLK_GPU_ROOT 263 +-#define IMX8MP_CLK_NOC_WRAPPER_ROOT 264 +-#define IMX8MP_CLK_VPU_VC8KE_ROOT 265 +-#define IMX8MP_CLK_VPU_G2_ROOT 266 +-#define IMX8MP_CLK_NPU_ROOT 267 +-#define IMX8MP_CLK_HSIO_ROOT 268 +-#define IMX8MP_CLK_MEDIA_APB_ROOT 269 +-#define IMX8MP_CLK_MEDIA_AXI_ROOT 270 +-#define IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT 271 +-#define IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT 272 +-#define IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT 273 +-#define IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT 274 +-#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT 275 +-#define IMX8MP_CLK_MEDIA_ISP_ROOT 276 +-#define IMX8MP_CLK_USDHC3_ROOT 277 +-#define IMX8MP_CLK_HDMI_ROOT 278 +-#define IMX8MP_CLK_XTAL_ROOT 279 +-#define IMX8MP_CLK_PLL_ROOT 280 +-#define IMX8MP_CLK_TSENSOR_ROOT 281 +-#define IMX8MP_CLK_VPU_ROOT 282 +-#define IMX8MP_CLK_MRPR_ROOT 283 +-#define IMX8MP_CLK_AUDIO_ROOT 284 +-#define IMX8MP_CLK_DRAM_ALT_ROOT 285 +-#define IMX8MP_CLK_DRAM_CORE 286 +-#define IMX8MP_CLK_ARM 287 +-#define IMX8MP_CLK_A53_CORE 288 +- +-#define IMX8MP_SYS_PLL1_40M_CG 289 +-#define IMX8MP_SYS_PLL1_80M_CG 290 +-#define IMX8MP_SYS_PLL1_100M_CG 291 +-#define IMX8MP_SYS_PLL1_133M_CG 292 +-#define IMX8MP_SYS_PLL1_160M_CG 293 +-#define IMX8MP_SYS_PLL1_200M_CG 294 +-#define IMX8MP_SYS_PLL1_266M_CG 295 +-#define IMX8MP_SYS_PLL1_400M_CG 296 +-#define IMX8MP_SYS_PLL2_50M_CG 297 +-#define IMX8MP_SYS_PLL2_100M_CG 298 +-#define IMX8MP_SYS_PLL2_125M_CG 299 +-#define IMX8MP_SYS_PLL2_166M_CG 300 +-#define IMX8MP_SYS_PLL2_200M_CG 301 +-#define IMX8MP_SYS_PLL2_250M_CG 302 +-#define IMX8MP_SYS_PLL2_333M_CG 303 +-#define IMX8MP_SYS_PLL2_500M_CG 304 +- +-#define IMX8MP_CLK_M7_CORE 305 +-#define IMX8MP_CLK_ML_CORE 306 +-#define IMX8MP_CLK_GPU3D_CORE 307 +-#define IMX8MP_CLK_GPU3D_SHADER_CORE 308 +-#define IMX8MP_CLK_GPU2D_CORE 309 +-#define IMX8MP_CLK_AUDIO_AXI 310 +-#define IMX8MP_CLK_HSIO_AXI 311 +-#define IMX8MP_CLK_MEDIA_ISP 312 +- +-#define IMX8MP_CLK_END 313 +- +-#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 +-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 +-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2 +-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3 +-#define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4 +-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5 +-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6 +-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7 +-#define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8 +-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9 +-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10 +-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11 +-#define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12 +-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13 +-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14 +-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15 +-#define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16 +-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17 +-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18 +-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19 +-#define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20 +-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21 +-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22 +-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23 +-#define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24 +-#define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25 +-#define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26 +-#define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27 +-#define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28 +-#define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29 +-#define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30 +-#define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31 +-#define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32 +-#define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33 +-#define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34 +-#define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35 +-#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36 +-#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37 +-#define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38 +-#define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39 +-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40 +-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41 +-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42 +-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43 +-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44 +-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45 +-#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46 +-#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47 +-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48 +-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49 +-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50 +-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51 +-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52 +-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53 +-#define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54 +-#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55 +-#define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56 +-#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57 +-#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58 +- +-#define IMX8MP_CLK_AUDIOMIX_END 59 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/imx8mq-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/imx8mq-clock.h +deleted file mode 100644 +index afa74d7ba100..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/imx8mq-clock.h ++++ /dev/null +@@ -1,431 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright 2016 Freescale Semiconductor, Inc. +- * Copyright 2017 NXP +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H +-#define __DT_BINDINGS_CLOCK_IMX8MQ_H +- +-#define IMX8MQ_CLK_DUMMY 0 +-#define IMX8MQ_CLK_32K 1 +-#define IMX8MQ_CLK_25M 2 +-#define IMX8MQ_CLK_27M 3 +-#define IMX8MQ_CLK_EXT1 4 +-#define IMX8MQ_CLK_EXT2 5 +-#define IMX8MQ_CLK_EXT3 6 +-#define IMX8MQ_CLK_EXT4 7 +- +-/* ANAMIX PLL clocks */ +-/* FRAC PLLs */ +-/* ARM PLL */ +-#define IMX8MQ_ARM_PLL_REF_SEL 8 +-#define IMX8MQ_ARM_PLL_REF_DIV 9 +-#define IMX8MQ_ARM_PLL 10 +-#define IMX8MQ_ARM_PLL_BYPASS 11 +-#define IMX8MQ_ARM_PLL_OUT 12 +- +-/* GPU PLL */ +-#define IMX8MQ_GPU_PLL_REF_SEL 13 +-#define IMX8MQ_GPU_PLL_REF_DIV 14 +-#define IMX8MQ_GPU_PLL 15 +-#define IMX8MQ_GPU_PLL_BYPASS 16 +-#define IMX8MQ_GPU_PLL_OUT 17 +- +-/* VPU PLL */ +-#define IMX8MQ_VPU_PLL_REF_SEL 18 +-#define IMX8MQ_VPU_PLL_REF_DIV 19 +-#define IMX8MQ_VPU_PLL 20 +-#define IMX8MQ_VPU_PLL_BYPASS 21 +-#define IMX8MQ_VPU_PLL_OUT 22 +- +-/* AUDIO PLL1 */ +-#define IMX8MQ_AUDIO_PLL1_REF_SEL 23 +-#define IMX8MQ_AUDIO_PLL1_REF_DIV 24 +-#define IMX8MQ_AUDIO_PLL1 25 +-#define IMX8MQ_AUDIO_PLL1_BYPASS 26 +-#define IMX8MQ_AUDIO_PLL1_OUT 27 +- +-/* AUDIO PLL2 */ +-#define IMX8MQ_AUDIO_PLL2_REF_SEL 28 +-#define IMX8MQ_AUDIO_PLL2_REF_DIV 29 +-#define IMX8MQ_AUDIO_PLL2 30 +-#define IMX8MQ_AUDIO_PLL2_BYPASS 31 +-#define IMX8MQ_AUDIO_PLL2_OUT 32 +- +-/* VIDEO PLL1 */ +-#define IMX8MQ_VIDEO_PLL1_REF_SEL 33 +-#define IMX8MQ_VIDEO_PLL1_REF_DIV 34 +-#define IMX8MQ_VIDEO_PLL1 35 +-#define IMX8MQ_VIDEO_PLL1_BYPASS 36 +-#define IMX8MQ_VIDEO_PLL1_OUT 37 +- +-/* SYS1 PLL */ +-#define IMX8MQ_SYS1_PLL1_REF_SEL 38 +-#define IMX8MQ_SYS1_PLL1_REF_DIV 39 +-#define IMX8MQ_SYS1_PLL1 40 +-#define IMX8MQ_SYS1_PLL1_OUT 41 +-#define IMX8MQ_SYS1_PLL1_OUT_DIV 42 +-#define IMX8MQ_SYS1_PLL2 43 +-#define IMX8MQ_SYS1_PLL2_DIV 44 +-#define IMX8MQ_SYS1_PLL2_OUT 45 +- +-/* SYS2 PLL */ +-#define IMX8MQ_SYS2_PLL1_REF_SEL 46 +-#define IMX8MQ_SYS2_PLL1_REF_DIV 47 +-#define IMX8MQ_SYS2_PLL1 48 +-#define IMX8MQ_SYS2_PLL1_OUT 49 +-#define IMX8MQ_SYS2_PLL1_OUT_DIV 50 +-#define IMX8MQ_SYS2_PLL2 51 +-#define IMX8MQ_SYS2_PLL2_DIV 52 +-#define IMX8MQ_SYS2_PLL2_OUT 53 +- +-/* SYS3 PLL */ +-#define IMX8MQ_SYS3_PLL1_REF_SEL 54 +-#define IMX8MQ_SYS3_PLL1_REF_DIV 55 +-#define IMX8MQ_SYS3_PLL1 56 +-#define IMX8MQ_SYS3_PLL1_OUT 57 +-#define IMX8MQ_SYS3_PLL1_OUT_DIV 58 +-#define IMX8MQ_SYS3_PLL2 59 +-#define IMX8MQ_SYS3_PLL2_DIV 60 +-#define IMX8MQ_SYS3_PLL2_OUT 61 +- +-/* DRAM PLL */ +-#define IMX8MQ_DRAM_PLL1_REF_SEL 62 +-#define IMX8MQ_DRAM_PLL1_REF_DIV 63 +-#define IMX8MQ_DRAM_PLL1 64 +-#define IMX8MQ_DRAM_PLL1_OUT 65 +-#define IMX8MQ_DRAM_PLL1_OUT_DIV 66 +-#define IMX8MQ_DRAM_PLL2 67 +-#define IMX8MQ_DRAM_PLL2_DIV 68 +-#define IMX8MQ_DRAM_PLL2_OUT 69 +- +-/* SYS PLL DIV */ +-#define IMX8MQ_SYS1_PLL_40M 70 +-#define IMX8MQ_SYS1_PLL_80M 71 +-#define IMX8MQ_SYS1_PLL_100M 72 +-#define IMX8MQ_SYS1_PLL_133M 73 +-#define IMX8MQ_SYS1_PLL_160M 74 +-#define IMX8MQ_SYS1_PLL_200M 75 +-#define IMX8MQ_SYS1_PLL_266M 76 +-#define IMX8MQ_SYS1_PLL_400M 77 +-#define IMX8MQ_SYS1_PLL_800M 78 +- +-#define IMX8MQ_SYS2_PLL_50M 79 +-#define IMX8MQ_SYS2_PLL_100M 80 +-#define IMX8MQ_SYS2_PLL_125M 81 +-#define IMX8MQ_SYS2_PLL_166M 82 +-#define IMX8MQ_SYS2_PLL_200M 83 +-#define IMX8MQ_SYS2_PLL_250M 84 +-#define IMX8MQ_SYS2_PLL_333M 85 +-#define IMX8MQ_SYS2_PLL_500M 86 +-#define IMX8MQ_SYS2_PLL_1000M 87 +- +-/* CCM ROOT clocks */ +-/* A53 */ +-#define IMX8MQ_CLK_A53_SRC 88 +-#define IMX8MQ_CLK_A53_CG 89 +-#define IMX8MQ_CLK_A53_DIV 90 +-/* M4 */ +-#define IMX8MQ_CLK_M4_SRC 91 +-#define IMX8MQ_CLK_M4_CG 92 +-#define IMX8MQ_CLK_M4_DIV 93 +-/* VPU */ +-#define IMX8MQ_CLK_VPU_SRC 94 +-#define IMX8MQ_CLK_VPU_CG 95 +-#define IMX8MQ_CLK_VPU_DIV 96 +-/* GPU CORE */ +-#define IMX8MQ_CLK_GPU_CORE_SRC 97 +-#define IMX8MQ_CLK_GPU_CORE_CG 98 +-#define IMX8MQ_CLK_GPU_CORE_DIV 99 +-/* GPU SHADER */ +-#define IMX8MQ_CLK_GPU_SHADER_SRC 100 +-#define IMX8MQ_CLK_GPU_SHADER_CG 101 +-#define IMX8MQ_CLK_GPU_SHADER_DIV 102 +- +-/* BUS TYPE */ +-/* MAIN AXI */ +-#define IMX8MQ_CLK_MAIN_AXI 103 +-/* ENET AXI */ +-#define IMX8MQ_CLK_ENET_AXI 104 +-/* NAND_USDHC_BUS */ +-#define IMX8MQ_CLK_NAND_USDHC_BUS 105 +-/* VPU BUS */ +-#define IMX8MQ_CLK_VPU_BUS 106 +-/* DISP_AXI */ +-#define IMX8MQ_CLK_DISP_AXI 107 +-/* DISP APB */ +-#define IMX8MQ_CLK_DISP_APB 108 +-/* DISP RTRM */ +-#define IMX8MQ_CLK_DISP_RTRM 109 +-/* USB_BUS */ +-#define IMX8MQ_CLK_USB_BUS 110 +-/* GPU_AXI */ +-#define IMX8MQ_CLK_GPU_AXI 111 +-/* GPU_AHB */ +-#define IMX8MQ_CLK_GPU_AHB 112 +-/* NOC */ +-#define IMX8MQ_CLK_NOC 113 +-/* NOC_APB */ +-#define IMX8MQ_CLK_NOC_APB 115 +- +-/* AHB */ +-#define IMX8MQ_CLK_AHB 116 +-/* AUDIO AHB */ +-#define IMX8MQ_CLK_AUDIO_AHB 117 +- +-/* DRAM_ALT */ +-#define IMX8MQ_CLK_DRAM_ALT 118 +-/* DRAM APB */ +-#define IMX8MQ_CLK_DRAM_APB 119 +-/* VPU_G1 */ +-#define IMX8MQ_CLK_VPU_G1 120 +-/* VPU_G2 */ +-#define IMX8MQ_CLK_VPU_G2 121 +-/* DISP_DTRC */ +-#define IMX8MQ_CLK_DISP_DTRC 122 +-/* DISP_DC8000 */ +-#define IMX8MQ_CLK_DISP_DC8000 123 +-/* PCIE_CTRL */ +-#define IMX8MQ_CLK_PCIE1_CTRL 124 +-/* PCIE_PHY */ +-#define IMX8MQ_CLK_PCIE1_PHY 125 +-/* PCIE_AUX */ +-#define IMX8MQ_CLK_PCIE1_AUX 126 +-/* DC_PIXEL */ +-#define IMX8MQ_CLK_DC_PIXEL 127 +-/* LCDIF_PIXEL */ +-#define IMX8MQ_CLK_LCDIF_PIXEL 128 +-/* SAI1~6 */ +-#define IMX8MQ_CLK_SAI1 129 +- +-#define IMX8MQ_CLK_SAI2 130 +- +-#define IMX8MQ_CLK_SAI3 131 +- +-#define IMX8MQ_CLK_SAI4 132 +- +-#define IMX8MQ_CLK_SAI5 133 +- +-#define IMX8MQ_CLK_SAI6 134 +-/* SPDIF1 */ +-#define IMX8MQ_CLK_SPDIF1 135 +-/* SPDIF2 */ +-#define IMX8MQ_CLK_SPDIF2 136 +-/* ENET_REF */ +-#define IMX8MQ_CLK_ENET_REF 137 +-/* ENET_TIMER */ +-#define IMX8MQ_CLK_ENET_TIMER 138 +-/* ENET_PHY */ +-#define IMX8MQ_CLK_ENET_PHY_REF 139 +-/* NAND */ +-#define IMX8MQ_CLK_NAND 140 +-/* QSPI */ +-#define IMX8MQ_CLK_QSPI 141 +-/* USDHC1 */ +-#define IMX8MQ_CLK_USDHC1 142 +-/* USDHC2 */ +-#define IMX8MQ_CLK_USDHC2 143 +-/* I2C1 */ +-#define IMX8MQ_CLK_I2C1 144 +-/* I2C2 */ +-#define IMX8MQ_CLK_I2C2 145 +-/* I2C3 */ +-#define IMX8MQ_CLK_I2C3 146 +-/* I2C4 */ +-#define IMX8MQ_CLK_I2C4 147 +-/* UART1 */ +-#define IMX8MQ_CLK_UART1 148 +-/* UART2 */ +-#define IMX8MQ_CLK_UART2 149 +-/* UART3 */ +-#define IMX8MQ_CLK_UART3 150 +-/* UART4 */ +-#define IMX8MQ_CLK_UART4 151 +-/* USB_CORE_REF */ +-#define IMX8MQ_CLK_USB_CORE_REF 152 +-/* USB_PHY_REF */ +-#define IMX8MQ_CLK_USB_PHY_REF 153 +-/* ECSPI1 */ +-#define IMX8MQ_CLK_ECSPI1 154 +-/* ECSPI2 */ +-#define IMX8MQ_CLK_ECSPI2 155 +-/* PWM1 */ +-#define IMX8MQ_CLK_PWM1 156 +-/* PWM2 */ +-#define IMX8MQ_CLK_PWM2 157 +-/* PWM3 */ +-#define IMX8MQ_CLK_PWM3 158 +-/* PWM4 */ +-#define IMX8MQ_CLK_PWM4 159 +-/* GPT1 */ +-#define IMX8MQ_CLK_GPT1 160 +-/* WDOG */ +-#define IMX8MQ_CLK_WDOG 161 +-/* WRCLK */ +-#define IMX8MQ_CLK_WRCLK 162 +-/* DSI_CORE */ +-#define IMX8MQ_CLK_DSI_CORE 163 +-/* DSI_PHY */ +-#define IMX8MQ_CLK_DSI_PHY_REF 164 +-/* DSI_DBI */ +-#define IMX8MQ_CLK_DSI_DBI 165 +-/*DSI_ESC */ +-#define IMX8MQ_CLK_DSI_ESC 166 +-/* CSI1_CORE */ +-#define IMX8MQ_CLK_CSI1_CORE 167 +-/* CSI1_PHY */ +-#define IMX8MQ_CLK_CSI1_PHY_REF 168 +-/* CSI_ESC */ +-#define IMX8MQ_CLK_CSI1_ESC 169 +-/* CSI2_CORE */ +-#define IMX8MQ_CLK_CSI2_CORE 170 +-/* CSI2_PHY */ +-#define IMX8MQ_CLK_CSI2_PHY_REF 171 +-/* CSI2_ESC */ +-#define IMX8MQ_CLK_CSI2_ESC 172 +-/* PCIE2_CTRL */ +-#define IMX8MQ_CLK_PCIE2_CTRL 173 +-/* PCIE2_PHY */ +-#define IMX8MQ_CLK_PCIE2_PHY 174 +-/* PCIE2_AUX */ +-#define IMX8MQ_CLK_PCIE2_AUX 175 +-/* ECSPI3 */ +-#define IMX8MQ_CLK_ECSPI3 176 +- +-/* CCGR clocks */ +-#define IMX8MQ_CLK_A53_ROOT 177 +-#define IMX8MQ_CLK_DRAM_ROOT 178 +-#define IMX8MQ_CLK_ECSPI1_ROOT 179 +-#define IMX8MQ_CLK_ECSPI2_ROOT 180 +-#define IMX8MQ_CLK_ECSPI3_ROOT 181 +-#define IMX8MQ_CLK_ENET1_ROOT 182 +-#define IMX8MQ_CLK_GPT1_ROOT 183 +-#define IMX8MQ_CLK_I2C1_ROOT 184 +-#define IMX8MQ_CLK_I2C2_ROOT 185 +-#define IMX8MQ_CLK_I2C3_ROOT 186 +-#define IMX8MQ_CLK_I2C4_ROOT 187 +-#define IMX8MQ_CLK_M4_ROOT 188 +-#define IMX8MQ_CLK_PCIE1_ROOT 189 +-#define IMX8MQ_CLK_PCIE2_ROOT 190 +-#define IMX8MQ_CLK_PWM1_ROOT 191 +-#define IMX8MQ_CLK_PWM2_ROOT 192 +-#define IMX8MQ_CLK_PWM3_ROOT 193 +-#define IMX8MQ_CLK_PWM4_ROOT 194 +-#define IMX8MQ_CLK_QSPI_ROOT 195 +-#define IMX8MQ_CLK_SAI1_ROOT 196 +-#define IMX8MQ_CLK_SAI2_ROOT 197 +-#define IMX8MQ_CLK_SAI3_ROOT 198 +-#define IMX8MQ_CLK_SAI4_ROOT 199 +-#define IMX8MQ_CLK_SAI5_ROOT 200 +-#define IMX8MQ_CLK_SAI6_ROOT 201 +-#define IMX8MQ_CLK_UART1_ROOT 202 +-#define IMX8MQ_CLK_UART2_ROOT 203 +-#define IMX8MQ_CLK_UART3_ROOT 204 +-#define IMX8MQ_CLK_UART4_ROOT 205 +-#define IMX8MQ_CLK_USB1_CTRL_ROOT 206 +-#define IMX8MQ_CLK_USB2_CTRL_ROOT 207 +-#define IMX8MQ_CLK_USB1_PHY_ROOT 208 +-#define IMX8MQ_CLK_USB2_PHY_ROOT 209 +-#define IMX8MQ_CLK_USDHC1_ROOT 210 +-#define IMX8MQ_CLK_USDHC2_ROOT 211 +-#define IMX8MQ_CLK_WDOG1_ROOT 212 +-#define IMX8MQ_CLK_WDOG2_ROOT 213 +-#define IMX8MQ_CLK_WDOG3_ROOT 214 +-#define IMX8MQ_CLK_GPU_ROOT 215 +-#define IMX8MQ_CLK_HEVC_ROOT 216 +-#define IMX8MQ_CLK_AVC_ROOT 217 +-#define IMX8MQ_CLK_VP9_ROOT 218 +-#define IMX8MQ_CLK_HEVC_INTER_ROOT 219 +-#define IMX8MQ_CLK_DISP_ROOT 220 +-#define IMX8MQ_CLK_HDMI_ROOT 221 +-#define IMX8MQ_CLK_HDMI_PHY_ROOT 222 +-#define IMX8MQ_CLK_VPU_DEC_ROOT 223 +-#define IMX8MQ_CLK_CSI1_ROOT 224 +-#define IMX8MQ_CLK_CSI2_ROOT 225 +-#define IMX8MQ_CLK_RAWNAND_ROOT 226 +-#define IMX8MQ_CLK_SDMA1_ROOT 227 +-#define IMX8MQ_CLK_SDMA2_ROOT 228 +-#define IMX8MQ_CLK_VPU_G1_ROOT 229 +-#define IMX8MQ_CLK_VPU_G2_ROOT 230 +- +-/* SCCG PLL GATE */ +-#define IMX8MQ_SYS1_PLL_OUT 231 +-#define IMX8MQ_SYS2_PLL_OUT 232 +-#define IMX8MQ_SYS3_PLL_OUT 233 +-#define IMX8MQ_DRAM_PLL_OUT 234 +- +-#define IMX8MQ_GPT_3M_CLK 235 +- +-#define IMX8MQ_CLK_IPG_ROOT 236 +-#define IMX8MQ_CLK_IPG_AUDIO_ROOT 237 +-#define IMX8MQ_CLK_SAI1_IPG 238 +-#define IMX8MQ_CLK_SAI2_IPG 239 +-#define IMX8MQ_CLK_SAI3_IPG 240 +-#define IMX8MQ_CLK_SAI4_IPG 241 +-#define IMX8MQ_CLK_SAI5_IPG 242 +-#define IMX8MQ_CLK_SAI6_IPG 243 +- +-/* DSI AHB/IPG clocks */ +-/* rxesc clock */ +-#define IMX8MQ_CLK_DSI_AHB 244 +-/* txesc clock */ +-#define IMX8MQ_CLK_DSI_IPG_DIV 245 +- +-#define IMX8MQ_CLK_TMU_ROOT 246 +- +-/* Display root clocks */ +-#define IMX8MQ_CLK_DISP_AXI_ROOT 247 +-#define IMX8MQ_CLK_DISP_APB_ROOT 248 +-#define IMX8MQ_CLK_DISP_RTRM_ROOT 249 +- +-#define IMX8MQ_CLK_OCOTP_ROOT 250 +- +-#define IMX8MQ_CLK_DRAM_ALT_ROOT 251 +-#define IMX8MQ_CLK_DRAM_CORE 252 +- +-#define IMX8MQ_CLK_MU_ROOT 253 +-#define IMX8MQ_VIDEO2_PLL_OUT 254 +- +-#define IMX8MQ_CLK_CLKO2 255 +- +-#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 256 +- +-#define IMX8MQ_CLK_CLKO1 257 +-#define IMX8MQ_CLK_ARM 258 +- +-#define IMX8MQ_CLK_GPIO1_ROOT 259 +-#define IMX8MQ_CLK_GPIO2_ROOT 260 +-#define IMX8MQ_CLK_GPIO3_ROOT 261 +-#define IMX8MQ_CLK_GPIO4_ROOT 262 +-#define IMX8MQ_CLK_GPIO5_ROOT 263 +- +-#define IMX8MQ_CLK_SNVS_ROOT 264 +-#define IMX8MQ_CLK_GIC 265 +- +-#define IMX8MQ_VIDEO2_PLL1_REF_SEL 266 +- +-#define IMX8MQ_CLK_GPU_CORE 285 +-#define IMX8MQ_CLK_GPU_SHADER 286 +-#define IMX8MQ_CLK_M4_CORE 287 +-#define IMX8MQ_CLK_VPU_CORE 288 +- +-#define IMX8MQ_CLK_A53_CORE 289 +- +-#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV 290 +-#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV 291 +-#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV 292 +-#define IMX8MQ_CLK_MON_GPU_PLL_DIV 293 +-#define IMX8MQ_CLK_MON_VPU_PLL_DIV 294 +-#define IMX8MQ_CLK_MON_ARM_PLL_DIV 295 +-#define IMX8MQ_CLK_MON_SYS_PLL1_DIV 296 +-#define IMX8MQ_CLK_MON_SYS_PLL2_DIV 297 +-#define IMX8MQ_CLK_MON_SYS_PLL3_DIV 298 +-#define IMX8MQ_CLK_MON_DRAM_PLL_DIV 299 +-#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV 300 +-#define IMX8MQ_CLK_MON_SEL 301 +-#define IMX8MQ_CLK_MON_CLK2_OUT 302 +- +-#define IMX8MQ_CLK_END 303 +- +-#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/ingenic,sysost.h b/scripts/dtc/include-prefixes/dt-bindings/clock/ingenic,sysost.h +deleted file mode 100644 +index d7aa42c08ded..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/ingenic,sysost.h ++++ /dev/null +@@ -1,35 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides clock numbers for the Ingenic OST DT binding. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_INGENIC_OST_H__ +-#define __DT_BINDINGS_CLOCK_INGENIC_OST_H__ +- +-#define OST_CLK_PERCPU_TIMER 1 +-#define OST_CLK_GLOBAL_TIMER 0 +-#define OST_CLK_PERCPU_TIMER0 1 +-#define OST_CLK_PERCPU_TIMER1 2 +-#define OST_CLK_PERCPU_TIMER2 3 +-#define OST_CLK_PERCPU_TIMER3 4 +- +-#define OST_CLK_EVENT_TIMER 1 +- +-#define OST_CLK_EVENT_TIMER0 0 +-#define OST_CLK_EVENT_TIMER1 1 +-#define OST_CLK_EVENT_TIMER2 2 +-#define OST_CLK_EVENT_TIMER3 3 +-#define OST_CLK_EVENT_TIMER4 4 +-#define OST_CLK_EVENT_TIMER5 5 +-#define OST_CLK_EVENT_TIMER6 6 +-#define OST_CLK_EVENT_TIMER7 7 +-#define OST_CLK_EVENT_TIMER8 8 +-#define OST_CLK_EVENT_TIMER9 9 +-#define OST_CLK_EVENT_TIMER10 10 +-#define OST_CLK_EVENT_TIMER11 11 +-#define OST_CLK_EVENT_TIMER12 12 +-#define OST_CLK_EVENT_TIMER13 13 +-#define OST_CLK_EVENT_TIMER14 14 +-#define OST_CLK_EVENT_TIMER15 15 +- +-#endif /* __DT_BINDINGS_CLOCK_INGENIC_OST_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/ingenic,tcu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/ingenic,tcu.h +deleted file mode 100644 +index d569650a7945..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/ingenic,tcu.h ++++ /dev/null +@@ -1,20 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides clock numbers for the ingenic,tcu DT binding. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_INGENIC_TCU_H__ +-#define __DT_BINDINGS_CLOCK_INGENIC_TCU_H__ +- +-#define TCU_CLK_TIMER0 0 +-#define TCU_CLK_TIMER1 1 +-#define TCU_CLK_TIMER2 2 +-#define TCU_CLK_TIMER3 3 +-#define TCU_CLK_TIMER4 4 +-#define TCU_CLK_TIMER5 5 +-#define TCU_CLK_TIMER6 6 +-#define TCU_CLK_TIMER7 7 +-#define TCU_CLK_WDT 8 +-#define TCU_CLK_OST 9 +- +-#endif /* __DT_BINDINGS_CLOCK_INGENIC_TCU_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/intel,lgm-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/intel,lgm-clk.h +deleted file mode 100644 +index 92f5be6490bb..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/intel,lgm-clk.h ++++ /dev/null +@@ -1,165 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +-/* +- * Copyright (C) 2020 Intel Corporation. +- * Lei Chuanhua +- * Zhu Yixin +- */ +-#ifndef __INTEL_LGM_CLK_H +-#define __INTEL_LGM_CLK_H +- +-/* PLL clocks */ +-#define LGM_CLK_OSC 1 +-#define LGM_CLK_PLLPP 2 +-#define LGM_CLK_PLL2 3 +-#define LGM_CLK_PLL0CZ 4 +-#define LGM_CLK_PLL0B 5 +-#define LGM_CLK_PLL1 6 +-#define LGM_CLK_LJPLL3 7 +-#define LGM_CLK_LJPLL4 8 +-#define LGM_CLK_PLL0CM0 9 +-#define LGM_CLK_PLL0CM1 10 +- +-/* clocks from PLLs */ +- +-/* ROPLL clocks */ +-#define LGM_CLK_PP_HW 15 +-#define LGM_CLK_PP_UC 16 +-#define LGM_CLK_PP_FXD 17 +-#define LGM_CLK_PP_TBM 18 +- +-/* PLL2 clocks */ +-#define LGM_CLK_DDR 20 +- +-/* PLL0CZ */ +-#define LGM_CLK_CM 25 +-#define LGM_CLK_IC 26 +-#define LGM_CLK_SDXC3 27 +- +-/* PLL0B */ +-#define LGM_CLK_NGI 30 +-#define LGM_CLK_NOC4 31 +-#define LGM_CLK_SW 32 +-#define LGM_CLK_QSPI 33 +-#define LGM_CLK_CQEM LGM_CLK_SW +-#define LGM_CLK_EMMC5 LGM_CLK_NOC4 +- +-/* PLL1 */ +-#define LGM_CLK_CT 35 +-#define LGM_CLK_DSP 36 +-#define LGM_CLK_VIF 37 +- +-/* LJPLL3 */ +-#define LGM_CLK_CML 40 +-#define LGM_CLK_SERDES 41 +-#define LGM_CLK_POOL 42 +-#define LGM_CLK_PTP 43 +- +-/* LJPLL4 */ +-#define LGM_CLK_PCIE 45 +-#define LGM_CLK_SATA LGM_CLK_PCIE +- +-/* PLL0CM0 */ +-#define LGM_CLK_CPU0 50 +- +-/* PLL0CM1 */ +-#define LGM_CLK_CPU1 55 +- +-/* Miscellaneous clocks */ +-#define LGM_CLK_EMMC4 60 +-#define LGM_CLK_SDXC2 61 +-#define LGM_CLK_EMMC 62 +-#define LGM_CLK_SDXC 63 +-#define LGM_CLK_SLIC 64 +-#define LGM_CLK_DCL 65 +-#define LGM_CLK_DOCSIS 66 +-#define LGM_CLK_PCM 67 +-#define LGM_CLK_DDR_PHY 68 +-#define LGM_CLK_PONDEF 69 +-#define LGM_CLK_PL25M 70 +-#define LGM_CLK_PL10M 71 +-#define LGM_CLK_PL1544K 72 +-#define LGM_CLK_PL2048K 73 +-#define LGM_CLK_PL8K 74 +-#define LGM_CLK_PON_NTR 75 +-#define LGM_CLK_SYNC0 76 +-#define LGM_CLK_SYNC1 77 +-#define LGM_CLK_PROGDIV 78 +-#define LGM_CLK_OD0 79 +-#define LGM_CLK_OD1 80 +-#define LGM_CLK_CBPHY0 81 +-#define LGM_CLK_CBPHY1 82 +-#define LGM_CLK_CBPHY2 83 +-#define LGM_CLK_CBPHY3 84 +- +-/* Gate clocks */ +-/* Gate CLK0 */ +-#define LGM_GCLK_C55 100 +-#define LGM_GCLK_QSPI 101 +-#define LGM_GCLK_EIP197 102 +-#define LGM_GCLK_VAULT 103 +-#define LGM_GCLK_TOE 104 +-#define LGM_GCLK_SDXC 105 +-#define LGM_GCLK_EMMC 106 +-#define LGM_GCLK_SPI_DBG 107 +-#define LGM_GCLK_DMA3 108 +- +-/* Gate CLK1 */ +-#define LGM_GCLK_DMA0 120 +-#define LGM_GCLK_LEDC0 121 +-#define LGM_GCLK_LEDC1 122 +-#define LGM_GCLK_I2S0 123 +-#define LGM_GCLK_I2S1 124 +-#define LGM_GCLK_EBU 125 +-#define LGM_GCLK_PWM 126 +-#define LGM_GCLK_I2C0 127 +-#define LGM_GCLK_I2C1 128 +-#define LGM_GCLK_I2C2 129 +-#define LGM_GCLK_I2C3 130 +-#define LGM_GCLK_SSC0 131 +-#define LGM_GCLK_SSC1 132 +-#define LGM_GCLK_SSC2 133 +-#define LGM_GCLK_SSC3 134 +-#define LGM_GCLK_GPTC0 135 +-#define LGM_GCLK_GPTC1 136 +-#define LGM_GCLK_GPTC2 137 +-#define LGM_GCLK_GPTC3 138 +-#define LGM_GCLK_ASC0 139 +-#define LGM_GCLK_ASC1 140 +-#define LGM_GCLK_ASC2 141 +-#define LGM_GCLK_ASC3 142 +-#define LGM_GCLK_PCM0 143 +-#define LGM_GCLK_PCM1 144 +-#define LGM_GCLK_PCM2 145 +- +-/* Gate CLK2 */ +-#define LGM_GCLK_PCIE10 150 +-#define LGM_GCLK_PCIE11 151 +-#define LGM_GCLK_PCIE30 152 +-#define LGM_GCLK_PCIE31 153 +-#define LGM_GCLK_PCIE20 154 +-#define LGM_GCLK_PCIE21 155 +-#define LGM_GCLK_PCIE40 156 +-#define LGM_GCLK_PCIE41 157 +-#define LGM_GCLK_XPCS0 158 +-#define LGM_GCLK_XPCS1 159 +-#define LGM_GCLK_XPCS2 160 +-#define LGM_GCLK_XPCS3 161 +-#define LGM_GCLK_SATA0 162 +-#define LGM_GCLK_SATA1 163 +-#define LGM_GCLK_SATA2 164 +-#define LGM_GCLK_SATA3 165 +- +-/* Gate CLK3 */ +-#define LGM_GCLK_ARCEM4 170 +-#define LGM_GCLK_IDMAR1 171 +-#define LGM_GCLK_IDMAT0 172 +-#define LGM_GCLK_IDMAT1 173 +-#define LGM_GCLK_IDMAT2 174 +-#define LGM_GCLK_PPV4 175 +-#define LGM_GCLK_GSWIPO 176 +-#define LGM_GCLK_CQEM 177 +-#define LGM_GCLK_XPCS5 178 +-#define LGM_GCLK_USB1 179 +-#define LGM_GCLK_USB2 180 +- +-#endif /* __INTEL_LGM_CLK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/jz4725b-cgu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/jz4725b-cgu.h +deleted file mode 100644 +index 31f1ab0fe42c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/jz4725b-cgu.h ++++ /dev/null +@@ -1,36 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides clock numbers for the ingenic,jz4725b-cgu DT binding. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ +-#define __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ +- +-#define JZ4725B_CLK_EXT 0 +-#define JZ4725B_CLK_OSC32K 1 +-#define JZ4725B_CLK_PLL 2 +-#define JZ4725B_CLK_PLL_HALF 3 +-#define JZ4725B_CLK_CCLK 4 +-#define JZ4725B_CLK_HCLK 5 +-#define JZ4725B_CLK_PCLK 6 +-#define JZ4725B_CLK_MCLK 7 +-#define JZ4725B_CLK_IPU 8 +-#define JZ4725B_CLK_LCD 9 +-#define JZ4725B_CLK_I2S 10 +-#define JZ4725B_CLK_SPI 11 +-#define JZ4725B_CLK_MMC_MUX 12 +-#define JZ4725B_CLK_UDC 13 +-#define JZ4725B_CLK_UART 14 +-#define JZ4725B_CLK_DMA 15 +-#define JZ4725B_CLK_ADC 16 +-#define JZ4725B_CLK_I2C 17 +-#define JZ4725B_CLK_AIC 18 +-#define JZ4725B_CLK_MMC0 19 +-#define JZ4725B_CLK_MMC1 20 +-#define JZ4725B_CLK_BCH 21 +-#define JZ4725B_CLK_TCU 22 +-#define JZ4725B_CLK_EXT512 23 +-#define JZ4725B_CLK_RTC 24 +-#define JZ4725B_CLK_UDC_PHY 25 +- +-#endif /* __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/jz4740-cgu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/jz4740-cgu.h +deleted file mode 100644 +index e82d77028581..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/jz4740-cgu.h ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides clock numbers for the ingenic,jz4740-cgu DT binding. +- * +- * They are roughly ordered as: +- * - external clocks +- * - PLLs +- * - muxes/dividers in the order they appear in the jz4740 programmers manual +- * - gates in order of their bit in the CLKGR* registers +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ +-#define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ +- +-#define JZ4740_CLK_EXT 0 +-#define JZ4740_CLK_RTC 1 +-#define JZ4740_CLK_PLL 2 +-#define JZ4740_CLK_PLL_HALF 3 +-#define JZ4740_CLK_CCLK 4 +-#define JZ4740_CLK_HCLK 5 +-#define JZ4740_CLK_PCLK 6 +-#define JZ4740_CLK_MCLK 7 +-#define JZ4740_CLK_LCD 8 +-#define JZ4740_CLK_LCD_PCLK 9 +-#define JZ4740_CLK_I2S 10 +-#define JZ4740_CLK_SPI 11 +-#define JZ4740_CLK_MMC 12 +-#define JZ4740_CLK_UHC 13 +-#define JZ4740_CLK_UDC 14 +-#define JZ4740_CLK_UART0 15 +-#define JZ4740_CLK_UART1 16 +-#define JZ4740_CLK_DMA 17 +-#define JZ4740_CLK_IPU 18 +-#define JZ4740_CLK_ADC 19 +-#define JZ4740_CLK_I2C 20 +-#define JZ4740_CLK_AIC 21 +-#define JZ4740_CLK_TCU 22 +- +-#endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/jz4760-cgu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/jz4760-cgu.h +deleted file mode 100644 +index 4bb2e19c4743..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/jz4760-cgu.h ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides clock numbers for the ingenic,jz4760-cgu DT binding. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ +-#define __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ +- +-#define JZ4760_CLK_EXT 0 +-#define JZ4760_CLK_OSC32K 1 +-#define JZ4760_CLK_PLL0 2 +-#define JZ4760_CLK_PLL0_HALF 3 +-#define JZ4760_CLK_PLL1 4 +-#define JZ4760_CLK_CCLK 5 +-#define JZ4760_CLK_HCLK 6 +-#define JZ4760_CLK_SCLK 7 +-#define JZ4760_CLK_H2CLK 8 +-#define JZ4760_CLK_MCLK 9 +-#define JZ4760_CLK_PCLK 10 +-#define JZ4760_CLK_MMC_MUX 11 +-#define JZ4760_CLK_MMC0 12 +-#define JZ4760_CLK_MMC1 13 +-#define JZ4760_CLK_MMC2 14 +-#define JZ4760_CLK_CIM 15 +-#define JZ4760_CLK_UHC 16 +-#define JZ4760_CLK_GPU 17 +-#define JZ4760_CLK_GPS 18 +-#define JZ4760_CLK_SSI_MUX 19 +-#define JZ4760_CLK_PCM 20 +-#define JZ4760_CLK_I2S 21 +-#define JZ4760_CLK_OTG 22 +-#define JZ4760_CLK_SSI0 23 +-#define JZ4760_CLK_SSI1 24 +-#define JZ4760_CLK_SSI2 25 +-#define JZ4760_CLK_DMA 26 +-#define JZ4760_CLK_I2C0 27 +-#define JZ4760_CLK_I2C1 28 +-#define JZ4760_CLK_UART0 29 +-#define JZ4760_CLK_UART1 30 +-#define JZ4760_CLK_UART2 31 +-#define JZ4760_CLK_UART3 32 +-#define JZ4760_CLK_IPU 33 +-#define JZ4760_CLK_ADC 34 +-#define JZ4760_CLK_AIC 35 +-#define JZ4760_CLK_VPU 36 +-#define JZ4760_CLK_UHC_PHY 37 +-#define JZ4760_CLK_OTG_PHY 38 +-#define JZ4760_CLK_EXT512 39 +-#define JZ4760_CLK_RTC 40 +-#define JZ4760_CLK_LPCLK_DIV 41 +-#define JZ4760_CLK_TVE 42 +-#define JZ4760_CLK_LPCLK 43 +- +-#endif /* __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/jz4770-cgu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/jz4770-cgu.h +deleted file mode 100644 +index d68a7695a1f8..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/jz4770-cgu.h ++++ /dev/null +@@ -1,58 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides clock numbers for the ingenic,jz4770-cgu DT binding. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ +-#define __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ +- +-#define JZ4770_CLK_EXT 0 +-#define JZ4770_CLK_OSC32K 1 +-#define JZ4770_CLK_PLL0 2 +-#define JZ4770_CLK_PLL1 3 +-#define JZ4770_CLK_CCLK 4 +-#define JZ4770_CLK_H0CLK 5 +-#define JZ4770_CLK_H1CLK 6 +-#define JZ4770_CLK_H2CLK 7 +-#define JZ4770_CLK_C1CLK 8 +-#define JZ4770_CLK_PCLK 9 +-#define JZ4770_CLK_MMC0_MUX 10 +-#define JZ4770_CLK_MMC0 11 +-#define JZ4770_CLK_MMC1_MUX 12 +-#define JZ4770_CLK_MMC1 13 +-#define JZ4770_CLK_MMC2_MUX 14 +-#define JZ4770_CLK_MMC2 15 +-#define JZ4770_CLK_CIM 16 +-#define JZ4770_CLK_UHC 17 +-#define JZ4770_CLK_GPU 18 +-#define JZ4770_CLK_BCH 19 +-#define JZ4770_CLK_LPCLK_MUX 20 +-#define JZ4770_CLK_GPS 21 +-#define JZ4770_CLK_SSI_MUX 22 +-#define JZ4770_CLK_PCM_MUX 23 +-#define JZ4770_CLK_I2S 24 +-#define JZ4770_CLK_OTG 25 +-#define JZ4770_CLK_SSI0 26 +-#define JZ4770_CLK_SSI1 27 +-#define JZ4770_CLK_SSI2 28 +-#define JZ4770_CLK_PCM0 29 +-#define JZ4770_CLK_PCM1 30 +-#define JZ4770_CLK_DMA 31 +-#define JZ4770_CLK_I2C0 32 +-#define JZ4770_CLK_I2C1 33 +-#define JZ4770_CLK_I2C2 34 +-#define JZ4770_CLK_UART0 35 +-#define JZ4770_CLK_UART1 36 +-#define JZ4770_CLK_UART2 37 +-#define JZ4770_CLK_UART3 38 +-#define JZ4770_CLK_IPU 39 +-#define JZ4770_CLK_ADC 40 +-#define JZ4770_CLK_AIC 41 +-#define JZ4770_CLK_AUX 42 +-#define JZ4770_CLK_VPU 43 +-#define JZ4770_CLK_UHC_PHY 44 +-#define JZ4770_CLK_OTG_PHY 45 +-#define JZ4770_CLK_EXT512 46 +-#define JZ4770_CLK_RTC 47 +- +-#endif /* __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/jz4780-cgu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/jz4780-cgu.h +deleted file mode 100644 +index 85cf8eb5081b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/jz4780-cgu.h ++++ /dev/null +@@ -1,91 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides clock numbers for the ingenic,jz4780-cgu DT binding. +- * +- * They are roughly ordered as: +- * - external clocks +- * - PLLs +- * - muxes/dividers in the order they appear in the jz4780 programmers manual +- * - gates in order of their bit in the CLKGR* registers +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ +-#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ +- +-#define JZ4780_CLK_EXCLK 0 +-#define JZ4780_CLK_RTCLK 1 +-#define JZ4780_CLK_APLL 2 +-#define JZ4780_CLK_MPLL 3 +-#define JZ4780_CLK_EPLL 4 +-#define JZ4780_CLK_VPLL 5 +-#define JZ4780_CLK_OTGPHY 6 +-#define JZ4780_CLK_SCLKA 7 +-#define JZ4780_CLK_CPUMUX 8 +-#define JZ4780_CLK_CPU 9 +-#define JZ4780_CLK_L2CACHE 10 +-#define JZ4780_CLK_AHB0 11 +-#define JZ4780_CLK_AHB2PMUX 12 +-#define JZ4780_CLK_AHB2 13 +-#define JZ4780_CLK_PCLK 14 +-#define JZ4780_CLK_DDR 15 +-#define JZ4780_CLK_VPU 16 +-#define JZ4780_CLK_I2SPLL 17 +-#define JZ4780_CLK_I2S 18 +-#define JZ4780_CLK_LCD0PIXCLK 19 +-#define JZ4780_CLK_LCD1PIXCLK 20 +-#define JZ4780_CLK_MSCMUX 21 +-#define JZ4780_CLK_MSC0 22 +-#define JZ4780_CLK_MSC1 23 +-#define JZ4780_CLK_MSC2 24 +-#define JZ4780_CLK_UHC 25 +-#define JZ4780_CLK_SSIPLL 26 +-#define JZ4780_CLK_SSI 27 +-#define JZ4780_CLK_CIMMCLK 28 +-#define JZ4780_CLK_PCMPLL 29 +-#define JZ4780_CLK_PCM 30 +-#define JZ4780_CLK_GPU 31 +-#define JZ4780_CLK_HDMI 32 +-#define JZ4780_CLK_BCH 33 +-#define JZ4780_CLK_NEMC 34 +-#define JZ4780_CLK_OTG0 35 +-#define JZ4780_CLK_SSI0 36 +-#define JZ4780_CLK_SMB0 37 +-#define JZ4780_CLK_SMB1 38 +-#define JZ4780_CLK_SCC 39 +-#define JZ4780_CLK_AIC 40 +-#define JZ4780_CLK_TSSI0 41 +-#define JZ4780_CLK_OWI 42 +-#define JZ4780_CLK_KBC 43 +-#define JZ4780_CLK_SADC 44 +-#define JZ4780_CLK_UART0 45 +-#define JZ4780_CLK_UART1 46 +-#define JZ4780_CLK_UART2 47 +-#define JZ4780_CLK_UART3 48 +-#define JZ4780_CLK_SSI1 49 +-#define JZ4780_CLK_SSI2 50 +-#define JZ4780_CLK_PDMA 51 +-#define JZ4780_CLK_GPS 52 +-#define JZ4780_CLK_MAC 53 +-#define JZ4780_CLK_SMB2 54 +-#define JZ4780_CLK_CIM 55 +-#define JZ4780_CLK_LCD 56 +-#define JZ4780_CLK_TVE 57 +-#define JZ4780_CLK_IPU 58 +-#define JZ4780_CLK_DDR0 59 +-#define JZ4780_CLK_DDR1 60 +-#define JZ4780_CLK_SMB3 61 +-#define JZ4780_CLK_TSSI1 62 +-#define JZ4780_CLK_COMPRESS 63 +-#define JZ4780_CLK_AIC1 64 +-#define JZ4780_CLK_GPVLC 65 +-#define JZ4780_CLK_OTG1 66 +-#define JZ4780_CLK_UART4 67 +-#define JZ4780_CLK_AHBMON 68 +-#define JZ4780_CLK_SMB4 69 +-#define JZ4780_CLK_DES 70 +-#define JZ4780_CLK_X2D 71 +-#define JZ4780_CLK_CORE1 72 +-#define JZ4780_CLK_EXCLK_DIV512 73 +-#define JZ4780_CLK_RTC 74 +- +-#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/k210-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/k210-clk.h +deleted file mode 100644 +index b2de702cbf75..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/k210-clk.h ++++ /dev/null +@@ -1,53 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (C) 2019-20 Sean Anderson +- * Copyright (c) 2020 Western Digital Corporation or its affiliates. +- */ +-#ifndef CLOCK_K210_CLK_H +-#define CLOCK_K210_CLK_H +- +-/* +- * Kendryte K210 SoC clock identifiers (arbitrary values). +- */ +-#define K210_CLK_CPU 0 +-#define K210_CLK_SRAM0 1 +-#define K210_CLK_SRAM1 2 +-#define K210_CLK_AI 3 +-#define K210_CLK_DMA 4 +-#define K210_CLK_FFT 5 +-#define K210_CLK_ROM 6 +-#define K210_CLK_DVP 7 +-#define K210_CLK_APB0 8 +-#define K210_CLK_APB1 9 +-#define K210_CLK_APB2 10 +-#define K210_CLK_I2S0 11 +-#define K210_CLK_I2S1 12 +-#define K210_CLK_I2S2 13 +-#define K210_CLK_I2S0_M 14 +-#define K210_CLK_I2S1_M 15 +-#define K210_CLK_I2S2_M 16 +-#define K210_CLK_WDT0 17 +-#define K210_CLK_WDT1 18 +-#define K210_CLK_SPI0 19 +-#define K210_CLK_SPI1 20 +-#define K210_CLK_SPI2 21 +-#define K210_CLK_I2C0 22 +-#define K210_CLK_I2C1 23 +-#define K210_CLK_I2C2 24 +-#define K210_CLK_SPI3 25 +-#define K210_CLK_TIMER0 26 +-#define K210_CLK_TIMER1 27 +-#define K210_CLK_TIMER2 28 +-#define K210_CLK_GPIO 29 +-#define K210_CLK_UART1 30 +-#define K210_CLK_UART2 31 +-#define K210_CLK_UART3 32 +-#define K210_CLK_FPIOA 33 +-#define K210_CLK_SHA 34 +-#define K210_CLK_AES 35 +-#define K210_CLK_OTP 36 +-#define K210_CLK_RTC 37 +- +-#define K210_NUM_CLKS 38 +- +-#endif /* CLOCK_K210_CLK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/lpc18xx-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/lpc18xx-ccu.h +deleted file mode 100644 +index bbfe00b6ab7d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/lpc18xx-ccu.h ++++ /dev/null +@@ -1,74 +0,0 @@ +-/* +- * Copyright (c) 2015 Joachim Eastwood +- * +- * This code is released using a dual license strategy: BSD/GPL +- * You can choose the licence that better fits your requirements. +- * +- * Released under the terms of 3-clause BSD License +- * Released under the terms of GNU General Public License Version 2.0 +- * +- */ +- +-/* Clock Control Unit 1 (CCU1) clock offsets */ +-#define CLK_APB3_BUS 0x100 +-#define CLK_APB3_I2C1 0x108 +-#define CLK_APB3_DAC 0x110 +-#define CLK_APB3_ADC0 0x118 +-#define CLK_APB3_ADC1 0x120 +-#define CLK_APB3_CAN0 0x128 +-#define CLK_APB1_BUS 0x200 +-#define CLK_APB1_MOTOCON_PWM 0x208 +-#define CLK_APB1_I2C0 0x210 +-#define CLK_APB1_I2S 0x218 +-#define CLK_APB1_CAN1 0x220 +-#define CLK_SPIFI 0x300 +-#define CLK_CPU_BUS 0x400 +-#define CLK_CPU_SPIFI 0x408 +-#define CLK_CPU_GPIO 0x410 +-#define CLK_CPU_LCD 0x418 +-#define CLK_CPU_ETHERNET 0x420 +-#define CLK_CPU_USB0 0x428 +-#define CLK_CPU_EMC 0x430 +-#define CLK_CPU_SDIO 0x438 +-#define CLK_CPU_DMA 0x440 +-#define CLK_CPU_CORE 0x448 +-#define CLK_CPU_SCT 0x468 +-#define CLK_CPU_USB1 0x470 +-#define CLK_CPU_EMCDIV 0x478 +-#define CLK_CPU_FLASHA 0x480 +-#define CLK_CPU_FLASHB 0x488 +-#define CLK_CPU_M0APP 0x490 +-#define CLK_CPU_ADCHS 0x498 +-#define CLK_CPU_EEPROM 0x4a0 +-#define CLK_CPU_WWDT 0x500 +-#define CLK_CPU_UART0 0x508 +-#define CLK_CPU_UART1 0x510 +-#define CLK_CPU_SSP0 0x518 +-#define CLK_CPU_TIMER0 0x520 +-#define CLK_CPU_TIMER1 0x528 +-#define CLK_CPU_SCU 0x530 +-#define CLK_CPU_CREG 0x538 +-#define CLK_CPU_RITIMER 0x600 +-#define CLK_CPU_UART2 0x608 +-#define CLK_CPU_UART3 0x610 +-#define CLK_CPU_TIMER2 0x618 +-#define CLK_CPU_TIMER3 0x620 +-#define CLK_CPU_SSP1 0x628 +-#define CLK_CPU_QEI 0x630 +-#define CLK_PERIPH_BUS 0x700 +-#define CLK_PERIPH_CORE 0x710 +-#define CLK_PERIPH_SGPIO 0x718 +-#define CLK_USB0 0x800 +-#define CLK_USB1 0x900 +-#define CLK_SPI 0xA00 +-#define CLK_ADCHS 0xB00 +- +-/* Clock Control Unit 2 (CCU2) clock offsets */ +-#define CLK_AUDIO 0x100 +-#define CLK_APB2_UART3 0x200 +-#define CLK_APB2_UART2 0x300 +-#define CLK_APB0_UART1 0x400 +-#define CLK_APB0_UART0 0x500 +-#define CLK_APB2_SSP1 0x600 +-#define CLK_APB0_SSP0 0x700 +-#define CLK_SDIO 0x800 +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/lpc18xx-cgu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/lpc18xx-cgu.h +deleted file mode 100644 +index 6e57c6d2ca66..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/lpc18xx-cgu.h ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * Copyright (c) 2015 Joachim Eastwood +- * +- * This code is released using a dual license strategy: BSD/GPL +- * You can choose the licence that better fits your requirements. +- * +- * Released under the terms of 3-clause BSD License +- * Released under the terms of GNU General Public License Version 2.0 +- * +- */ +- +-/* LPC18xx/43xx base clock ids */ +-#define BASE_SAFE_CLK 0 +-#define BASE_USB0_CLK 1 +-#define BASE_PERIPH_CLK 2 +-#define BASE_USB1_CLK 3 +-#define BASE_CPU_CLK 4 +-#define BASE_SPIFI_CLK 5 +-#define BASE_SPI_CLK 6 +-#define BASE_PHY_RX_CLK 7 +-#define BASE_PHY_TX_CLK 8 +-#define BASE_APB1_CLK 9 +-#define BASE_APB3_CLK 10 +-#define BASE_LCD_CLK 11 +-#define BASE_ADCHS_CLK 12 +-#define BASE_SDIO_CLK 13 +-#define BASE_SSP0_CLK 14 +-#define BASE_SSP1_CLK 15 +-#define BASE_UART0_CLK 16 +-#define BASE_UART1_CLK 17 +-#define BASE_UART2_CLK 18 +-#define BASE_UART3_CLK 19 +-#define BASE_OUT_CLK 20 +-#define BASE_RES1_CLK 21 +-#define BASE_RES2_CLK 22 +-#define BASE_RES3_CLK 23 +-#define BASE_RES4_CLK 24 +-#define BASE_AUDIO_CLK 25 +-#define BASE_CGU_OUT0_CLK 26 +-#define BASE_CGU_OUT1_CLK 27 +-#define BASE_CLK_MAX (BASE_CGU_OUT1_CLK + 1) +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/lpc32xx-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/lpc32xx-clock.h +deleted file mode 100644 +index e624d3a52798..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/lpc32xx-clock.h ++++ /dev/null +@@ -1,58 +0,0 @@ +-/* +- * Copyright (c) 2015 Vladimir Zapolskiy +- * +- * This code is released using a dual license strategy: BSD/GPL +- * You can choose the licence that better fits your requirements. +- * +- * Released under the terms of 3-clause BSD License +- * Released under the terms of GNU General Public License Version 2.0 +- * +- */ +- +-#ifndef __DT_BINDINGS_LPC32XX_CLOCK_H +-#define __DT_BINDINGS_LPC32XX_CLOCK_H +- +-/* LPC32XX System Control Block clocks */ +-#define LPC32XX_CLK_RTC 1 +-#define LPC32XX_CLK_DMA 2 +-#define LPC32XX_CLK_MLC 3 +-#define LPC32XX_CLK_SLC 4 +-#define LPC32XX_CLK_LCD 5 +-#define LPC32XX_CLK_MAC 6 +-#define LPC32XX_CLK_SD 7 +-#define LPC32XX_CLK_DDRAM 8 +-#define LPC32XX_CLK_SSP0 9 +-#define LPC32XX_CLK_SSP1 10 +-#define LPC32XX_CLK_UART3 11 +-#define LPC32XX_CLK_UART4 12 +-#define LPC32XX_CLK_UART5 13 +-#define LPC32XX_CLK_UART6 14 +-#define LPC32XX_CLK_IRDA 15 +-#define LPC32XX_CLK_I2C1 16 +-#define LPC32XX_CLK_I2C2 17 +-#define LPC32XX_CLK_TIMER0 18 +-#define LPC32XX_CLK_TIMER1 19 +-#define LPC32XX_CLK_TIMER2 20 +-#define LPC32XX_CLK_TIMER3 21 +-#define LPC32XX_CLK_TIMER4 22 +-#define LPC32XX_CLK_TIMER5 23 +-#define LPC32XX_CLK_WDOG 24 +-#define LPC32XX_CLK_I2S0 25 +-#define LPC32XX_CLK_I2S1 26 +-#define LPC32XX_CLK_SPI1 27 +-#define LPC32XX_CLK_SPI2 28 +-#define LPC32XX_CLK_MCPWM 29 +-#define LPC32XX_CLK_HSTIMER 30 +-#define LPC32XX_CLK_KEY 31 +-#define LPC32XX_CLK_PWM1 32 +-#define LPC32XX_CLK_PWM2 33 +-#define LPC32XX_CLK_ADC 34 +-#define LPC32XX_CLK_HCLK_PLL 35 +-#define LPC32XX_CLK_PERIPH 36 +- +-/* LPC32XX USB clocks */ +-#define LPC32XX_USB_CLK_I2C 1 +-#define LPC32XX_USB_CLK_DEVICE 2 +-#define LPC32XX_USB_CLK_HOST 3 +- +-#endif /* __DT_BINDINGS_LPC32XX_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/lsi,axm5516-clks.h b/scripts/dtc/include-prefixes/dt-bindings/clock/lsi,axm5516-clks.h +deleted file mode 100644 +index 050bbdab4f2d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/lsi,axm5516-clks.h ++++ /dev/null +@@ -1,33 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014 LSI Corporation +- */ +- +-#ifndef _DT_BINDINGS_CLK_AXM5516_H +-#define _DT_BINDINGS_CLK_AXM5516_H +- +-#define AXXIA_CLK_FAB_PLL 0 +-#define AXXIA_CLK_CPU_PLL 1 +-#define AXXIA_CLK_SYS_PLL 2 +-#define AXXIA_CLK_SM0_PLL 3 +-#define AXXIA_CLK_SM1_PLL 4 +-#define AXXIA_CLK_FAB_DIV 5 +-#define AXXIA_CLK_SYS_DIV 6 +-#define AXXIA_CLK_NRCP_DIV 7 +-#define AXXIA_CLK_CPU0_DIV 8 +-#define AXXIA_CLK_CPU1_DIV 9 +-#define AXXIA_CLK_CPU2_DIV 10 +-#define AXXIA_CLK_CPU3_DIV 11 +-#define AXXIA_CLK_PER_DIV 12 +-#define AXXIA_CLK_MMC_DIV 13 +-#define AXXIA_CLK_FAB 14 +-#define AXXIA_CLK_SYS 15 +-#define AXXIA_CLK_NRCP 16 +-#define AXXIA_CLK_CPU0 17 +-#define AXXIA_CLK_CPU1 18 +-#define AXXIA_CLK_CPU2 19 +-#define AXXIA_CLK_CPU3 20 +-#define AXXIA_CLK_PER 21 +-#define AXXIA_CLK_MMC 22 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/marvell,mmp2-audio.h b/scripts/dtc/include-prefixes/dt-bindings/clock/marvell,mmp2-audio.h +deleted file mode 100644 +index 20664776f497..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/marvell,mmp2-audio.h ++++ /dev/null +@@ -1,10 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */ +-#ifndef __DT_BINDINGS_CLOCK_MARVELL_MMP2_AUDIO_H +-#define __DT_BINDINGS_CLOCK_MARVELL_MMP2_AUDIO_H +- +-#define MMP2_CLK_AUDIO_SYSCLK 0 +-#define MMP2_CLK_AUDIO_SSPA0 1 +-#define MMP2_CLK_AUDIO_SSPA1 2 +- +-#define MMP2_CLK_AUDIO_NR_CLKS 3 +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/marvell,mmp2.h b/scripts/dtc/include-prefixes/dt-bindings/clock/marvell,mmp2.h +deleted file mode 100644 +index 87f5ad5df72f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/marvell,mmp2.h ++++ /dev/null +@@ -1,95 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DTS_MARVELL_MMP2_CLOCK_H +-#define __DTS_MARVELL_MMP2_CLOCK_H +- +-/* fixed clocks and plls */ +-#define MMP2_CLK_CLK32 1 +-#define MMP2_CLK_VCTCXO 2 +-#define MMP2_CLK_PLL1 3 +-#define MMP2_CLK_PLL1_2 8 +-#define MMP2_CLK_PLL1_4 9 +-#define MMP2_CLK_PLL1_8 10 +-#define MMP2_CLK_PLL1_16 11 +-#define MMP2_CLK_PLL1_3 12 +-#define MMP2_CLK_PLL1_6 13 +-#define MMP2_CLK_PLL1_12 14 +-#define MMP2_CLK_PLL1_20 15 +-#define MMP2_CLK_PLL2 16 +-#define MMP2_CLK_PLL2_2 17 +-#define MMP2_CLK_PLL2_4 18 +-#define MMP2_CLK_PLL2_8 19 +-#define MMP2_CLK_PLL2_16 20 +-#define MMP2_CLK_PLL2_3 21 +-#define MMP2_CLK_PLL2_6 22 +-#define MMP2_CLK_PLL2_12 23 +-#define MMP2_CLK_VCTCXO_2 24 +-#define MMP2_CLK_VCTCXO_4 25 +-#define MMP2_CLK_UART_PLL 26 +-#define MMP2_CLK_USB_PLL 27 +-#define MMP3_CLK_PLL1_P 28 +-#define MMP3_CLK_PLL2_P 29 +-#define MMP3_CLK_PLL3 30 +-#define MMP2_CLK_I2S0 31 +-#define MMP2_CLK_I2S1 32 +- +-/* apb periphrals */ +-#define MMP2_CLK_TWSI0 60 +-#define MMP2_CLK_TWSI1 61 +-#define MMP2_CLK_TWSI2 62 +-#define MMP2_CLK_TWSI3 63 +-#define MMP2_CLK_TWSI4 64 +-#define MMP2_CLK_TWSI5 65 +-#define MMP2_CLK_GPIO 66 +-#define MMP2_CLK_KPC 67 +-#define MMP2_CLK_RTC 68 +-#define MMP2_CLK_PWM0 69 +-#define MMP2_CLK_PWM1 70 +-#define MMP2_CLK_PWM2 71 +-#define MMP2_CLK_PWM3 72 +-#define MMP2_CLK_UART0 73 +-#define MMP2_CLK_UART1 74 +-#define MMP2_CLK_UART2 75 +-#define MMP2_CLK_UART3 76 +-#define MMP2_CLK_SSP0 77 +-#define MMP2_CLK_SSP1 78 +-#define MMP2_CLK_SSP2 79 +-#define MMP2_CLK_SSP3 80 +-#define MMP2_CLK_TIMER 81 +-#define MMP2_CLK_THERMAL0 82 +-#define MMP3_CLK_THERMAL1 83 +-#define MMP3_CLK_THERMAL2 84 +-#define MMP3_CLK_THERMAL3 85 +- +-/* axi periphrals */ +-#define MMP2_CLK_SDH0 101 +-#define MMP2_CLK_SDH1 102 +-#define MMP2_CLK_SDH2 103 +-#define MMP2_CLK_SDH3 104 +-#define MMP2_CLK_USB 105 +-#define MMP2_CLK_DISP0 106 +-#define MMP2_CLK_DISP0_MUX 107 +-#define MMP2_CLK_DISP0_SPHY 108 +-#define MMP2_CLK_DISP1 109 +-#define MMP2_CLK_DISP1_MUX 110 +-#define MMP2_CLK_CCIC_ARBITER 111 +-#define MMP2_CLK_CCIC0 112 +-#define MMP2_CLK_CCIC0_MIX 113 +-#define MMP2_CLK_CCIC0_PHY 114 +-#define MMP2_CLK_CCIC0_SPHY 115 +-#define MMP2_CLK_CCIC1 116 +-#define MMP2_CLK_CCIC1_MIX 117 +-#define MMP2_CLK_CCIC1_PHY 118 +-#define MMP2_CLK_CCIC1_SPHY 119 +-#define MMP2_CLK_DISP0_LCDC 120 +-#define MMP2_CLK_USBHSIC0 121 +-#define MMP2_CLK_USBHSIC1 122 +-#define MMP2_CLK_GPU_BUS 123 +-#define MMP3_CLK_GPU_BUS MMP2_CLK_GPU_BUS +-#define MMP2_CLK_GPU_3D 124 +-#define MMP3_CLK_GPU_3D MMP2_CLK_GPU_3D +-#define MMP3_CLK_GPU_2D 125 +-#define MMP3_CLK_SDH4 126 +-#define MMP2_CLK_AUDIO 127 +- +-#define MMP2_NR_CLKS 200 +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/marvell,pxa168.h b/scripts/dtc/include-prefixes/dt-bindings/clock/marvell,pxa168.h +deleted file mode 100644 +index caf90436b848..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/marvell,pxa168.h ++++ /dev/null +@@ -1,61 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DTS_MARVELL_PXA168_CLOCK_H +-#define __DTS_MARVELL_PXA168_CLOCK_H +- +-/* fixed clocks and plls */ +-#define PXA168_CLK_CLK32 1 +-#define PXA168_CLK_VCTCXO 2 +-#define PXA168_CLK_PLL1 3 +-#define PXA168_CLK_PLL1_2 8 +-#define PXA168_CLK_PLL1_4 9 +-#define PXA168_CLK_PLL1_8 10 +-#define PXA168_CLK_PLL1_16 11 +-#define PXA168_CLK_PLL1_6 12 +-#define PXA168_CLK_PLL1_12 13 +-#define PXA168_CLK_PLL1_24 14 +-#define PXA168_CLK_PLL1_48 15 +-#define PXA168_CLK_PLL1_96 16 +-#define PXA168_CLK_PLL1_13 17 +-#define PXA168_CLK_PLL1_13_1_5 18 +-#define PXA168_CLK_PLL1_2_1_5 19 +-#define PXA168_CLK_PLL1_3_16 20 +-#define PXA168_CLK_PLL1_192 21 +-#define PXA168_CLK_UART_PLL 27 +-#define PXA168_CLK_USB_PLL 28 +- +-/* apb periphrals */ +-#define PXA168_CLK_TWSI0 60 +-#define PXA168_CLK_TWSI1 61 +-#define PXA168_CLK_TWSI2 62 +-#define PXA168_CLK_TWSI3 63 +-#define PXA168_CLK_GPIO 64 +-#define PXA168_CLK_KPC 65 +-#define PXA168_CLK_RTC 66 +-#define PXA168_CLK_PWM0 67 +-#define PXA168_CLK_PWM1 68 +-#define PXA168_CLK_PWM2 69 +-#define PXA168_CLK_PWM3 70 +-#define PXA168_CLK_UART0 71 +-#define PXA168_CLK_UART1 72 +-#define PXA168_CLK_UART2 73 +-#define PXA168_CLK_SSP0 74 +-#define PXA168_CLK_SSP1 75 +-#define PXA168_CLK_SSP2 76 +-#define PXA168_CLK_SSP3 77 +-#define PXA168_CLK_SSP4 78 +-#define PXA168_CLK_TIMER 79 +- +-/* axi periphrals */ +-#define PXA168_CLK_DFC 100 +-#define PXA168_CLK_SDH0 101 +-#define PXA168_CLK_SDH1 102 +-#define PXA168_CLK_SDH2 103 +-#define PXA168_CLK_USB 104 +-#define PXA168_CLK_SPH 105 +-#define PXA168_CLK_DISP0 106 +-#define PXA168_CLK_CCIC0 107 +-#define PXA168_CLK_CCIC0_PHY 108 +-#define PXA168_CLK_CCIC0_SPHY 109 +- +-#define PXA168_NR_CLKS 200 +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/marvell,pxa1928.h b/scripts/dtc/include-prefixes/dt-bindings/clock/marvell,pxa1928.h +deleted file mode 100644 +index 5dca4820297f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/marvell,pxa1928.h ++++ /dev/null +@@ -1,58 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DTS_MARVELL_PXA1928_CLOCK_H +-#define __DTS_MARVELL_PXA1928_CLOCK_H +- +-/* +- * Clock ID values here correspond to the control register offset/4. +- */ +- +-/* apb peripherals */ +-#define PXA1928_CLK_RTC 0x00 +-#define PXA1928_CLK_TWSI0 0x01 +-#define PXA1928_CLK_TWSI1 0x02 +-#define PXA1928_CLK_TWSI2 0x03 +-#define PXA1928_CLK_TWSI3 0x04 +-#define PXA1928_CLK_OWIRE 0x05 +-#define PXA1928_CLK_KPC 0x06 +-#define PXA1928_CLK_TB_ROTARY 0x07 +-#define PXA1928_CLK_SW_JTAG 0x08 +-#define PXA1928_CLK_TIMER1 0x09 +-#define PXA1928_CLK_UART0 0x0b +-#define PXA1928_CLK_UART1 0x0c +-#define PXA1928_CLK_UART2 0x0d +-#define PXA1928_CLK_GPIO 0x0e +-#define PXA1928_CLK_PWM0 0x0f +-#define PXA1928_CLK_PWM1 0x10 +-#define PXA1928_CLK_PWM2 0x11 +-#define PXA1928_CLK_PWM3 0x12 +-#define PXA1928_CLK_SSP0 0x13 +-#define PXA1928_CLK_SSP1 0x14 +-#define PXA1928_CLK_SSP2 0x15 +- +-#define PXA1928_CLK_TWSI4 0x1f +-#define PXA1928_CLK_TWSI5 0x20 +-#define PXA1928_CLK_UART3 0x22 +-#define PXA1928_CLK_THSENS_GLOB 0x24 +-#define PXA1928_CLK_THSENS_CPU 0x26 +-#define PXA1928_CLK_THSENS_VPU 0x27 +-#define PXA1928_CLK_THSENS_GC 0x28 +-#define PXA1928_APBC_NR_CLKS 0x30 +- +- +-/* axi peripherals */ +-#define PXA1928_CLK_SDH0 0x15 +-#define PXA1928_CLK_SDH1 0x16 +-#define PXA1928_CLK_USB 0x17 +-#define PXA1928_CLK_NAND 0x18 +-#define PXA1928_CLK_DMA 0x19 +- +-#define PXA1928_CLK_SDH2 0x3a +-#define PXA1928_CLK_SDH3 0x3b +-#define PXA1928_CLK_HSIC 0x3e +-#define PXA1928_CLK_SDH4 0x57 +-#define PXA1928_CLK_GC3D 0x5d +-#define PXA1928_CLK_GC2D 0x5f +- +-#define PXA1928_APMU_NR_CLKS 0x60 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/marvell,pxa910.h b/scripts/dtc/include-prefixes/dt-bindings/clock/marvell,pxa910.h +deleted file mode 100644 +index 7bf46238946e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/marvell,pxa910.h ++++ /dev/null +@@ -1,59 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DTS_MARVELL_PXA910_CLOCK_H +-#define __DTS_MARVELL_PXA910_CLOCK_H +- +-/* fixed clocks and plls */ +-#define PXA910_CLK_CLK32 1 +-#define PXA910_CLK_VCTCXO 2 +-#define PXA910_CLK_PLL1 3 +-#define PXA910_CLK_PLL1_2 8 +-#define PXA910_CLK_PLL1_4 9 +-#define PXA910_CLK_PLL1_8 10 +-#define PXA910_CLK_PLL1_16 11 +-#define PXA910_CLK_PLL1_6 12 +-#define PXA910_CLK_PLL1_12 13 +-#define PXA910_CLK_PLL1_24 14 +-#define PXA910_CLK_PLL1_48 15 +-#define PXA910_CLK_PLL1_96 16 +-#define PXA910_CLK_PLL1_13 17 +-#define PXA910_CLK_PLL1_13_1_5 18 +-#define PXA910_CLK_PLL1_2_1_5 19 +-#define PXA910_CLK_PLL1_3_16 20 +-#define PXA910_CLK_PLL1_192 21 +-#define PXA910_CLK_UART_PLL 27 +-#define PXA910_CLK_USB_PLL 28 +- +-/* apb periphrals */ +-#define PXA910_CLK_TWSI0 60 +-#define PXA910_CLK_TWSI1 61 +-#define PXA910_CLK_TWSI2 62 +-#define PXA910_CLK_TWSI3 63 +-#define PXA910_CLK_GPIO 64 +-#define PXA910_CLK_KPC 65 +-#define PXA910_CLK_RTC 66 +-#define PXA910_CLK_PWM0 67 +-#define PXA910_CLK_PWM1 68 +-#define PXA910_CLK_PWM2 69 +-#define PXA910_CLK_PWM3 70 +-#define PXA910_CLK_UART0 71 +-#define PXA910_CLK_UART1 72 +-#define PXA910_CLK_UART2 73 +-#define PXA910_CLK_SSP0 74 +-#define PXA910_CLK_SSP1 75 +-#define PXA910_CLK_TIMER0 76 +-#define PXA910_CLK_TIMER1 77 +- +-/* axi periphrals */ +-#define PXA910_CLK_DFC 100 +-#define PXA910_CLK_SDH0 101 +-#define PXA910_CLK_SDH1 102 +-#define PXA910_CLK_SDH2 103 +-#define PXA910_CLK_USB 104 +-#define PXA910_CLK_SPH 105 +-#define PXA910_CLK_DISP0 106 +-#define PXA910_CLK_CCIC0 107 +-#define PXA910_CLK_CCIC0_PHY 108 +-#define PXA910_CLK_CCIC0_SPHY 109 +- +-#define PXA910_NR_CLKS 200 +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/maxim,max77620.h b/scripts/dtc/include-prefixes/dt-bindings/clock/maxim,max77620.h +deleted file mode 100644 +index 9d6609aaa10f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/maxim,max77620.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. +- * +- * Device Tree binding constants clocks for the Maxim 77620 PMIC. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77620_CLOCK_H +-#define _DT_BINDINGS_CLOCK_MAXIM_MAX77620_CLOCK_H +- +-/* Fixed rate clocks. */ +- +-#define MAX77620_CLK_32K_OUT0 0 +- +-/* Total number of clocks. */ +-#define MAX77620_CLKS_NUM (MAX77620_CLK_32K_OUT0 + 1) +- +-#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77620_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/maxim,max77686.h b/scripts/dtc/include-prefixes/dt-bindings/clock/maxim,max77686.h +deleted file mode 100644 +index af8261dcace1..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/maxim,max77686.h ++++ /dev/null +@@ -1,20 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2014 Google, Inc +- * +- * Device Tree binding constants clocks for the Maxim 77686 PMIC. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H +-#define _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H +- +-/* Fixed rate clocks. */ +- +-#define MAX77686_CLK_AP 0 +-#define MAX77686_CLK_CP 1 +-#define MAX77686_CLK_PMIC 2 +- +-/* Total number of clocks. */ +-#define MAX77686_CLKS_NUM (MAX77686_CLK_PMIC + 1) +- +-#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/maxim,max77802.h b/scripts/dtc/include-prefixes/dt-bindings/clock/maxim,max77802.h +deleted file mode 100644 +index 51adcbaed697..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/maxim,max77802.h ++++ /dev/null +@@ -1,19 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2014 Google, Inc +- * +- * Device Tree binding constants clocks for the Maxim 77802 PMIC. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H +-#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H +- +-/* Fixed rate clocks. */ +- +-#define MAX77802_CLK_32K_AP 0 +-#define MAX77802_CLK_32K_CP 1 +- +-/* Total number of clocks. */ +-#define MAX77802_CLKS_NUM (MAX77802_CLK_32K_CP + 1) +- +-#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/maxim,max9485.h b/scripts/dtc/include-prefixes/dt-bindings/clock/maxim,max9485.h +deleted file mode 100644 +index 368719a1b8de..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/maxim,max9485.h ++++ /dev/null +@@ -1,14 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2018 Daniel Mack +- */ +- +-#ifndef __DT_BINDINGS_MAX9485_CLK_H +-#define __DT_BINDINGS_MAX9485_CLK_H +- +-#define MAX9485_MCLKOUT 0 +-#define MAX9485_CLKOUT 1 +-#define MAX9485_CLKOUT1 2 +-#define MAX9485_CLKOUT2 3 +- +-#endif /* __DT_BINDINGS_MAX9485_CLK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/meson8-ddr-clkc.h b/scripts/dtc/include-prefixes/dt-bindings/clock/meson8-ddr-clkc.h +deleted file mode 100644 +index a8e0fa2987ab..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/meson8-ddr-clkc.h ++++ /dev/null +@@ -1,4 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +- +-#define DDR_CLKID_DDR_PLL_DCO 0 +-#define DDR_CLKID_DDR_PLL 1 +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/meson8b-clkc.h b/scripts/dtc/include-prefixes/dt-bindings/clock/meson8b-clkc.h +deleted file mode 100644 +index f33781338eda..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/meson8b-clkc.h ++++ /dev/null +@@ -1,118 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Meson8b clock tree IDs +- */ +- +-#ifndef __MESON8B_CLKC_H +-#define __MESON8B_CLKC_H +- +-#define CLKID_PLL_FIXED 2 +-#define CLKID_PLL_VID 3 +-#define CLKID_PLL_SYS 4 +-#define CLKID_FCLK_DIV2 5 +-#define CLKID_FCLK_DIV3 6 +-#define CLKID_FCLK_DIV4 7 +-#define CLKID_FCLK_DIV5 8 +-#define CLKID_FCLK_DIV7 9 +-#define CLKID_CLK81 10 +-#define CLKID_MALI 11 +-#define CLKID_CPUCLK 12 +-#define CLKID_ZERO 13 +-#define CLKID_MPEG_SEL 14 +-#define CLKID_MPEG_DIV 15 +-#define CLKID_DDR 16 +-#define CLKID_DOS 17 +-#define CLKID_ISA 18 +-#define CLKID_PL301 19 +-#define CLKID_PERIPHS 20 +-#define CLKID_SPICC 21 +-#define CLKID_I2C 22 +-#define CLKID_SAR_ADC 23 +-#define CLKID_SMART_CARD 24 +-#define CLKID_RNG0 25 +-#define CLKID_UART0 26 +-#define CLKID_SDHC 27 +-#define CLKID_STREAM 28 +-#define CLKID_ASYNC_FIFO 29 +-#define CLKID_SDIO 30 +-#define CLKID_ABUF 31 +-#define CLKID_HIU_IFACE 32 +-#define CLKID_ASSIST_MISC 33 +-#define CLKID_SPI 34 +-#define CLKID_I2S_SPDIF 35 +-#define CLKID_ETH 36 +-#define CLKID_DEMUX 37 +-#define CLKID_AIU_GLUE 38 +-#define CLKID_IEC958 39 +-#define CLKID_I2S_OUT 40 +-#define CLKID_AMCLK 41 +-#define CLKID_AIFIFO2 42 +-#define CLKID_MIXER 43 +-#define CLKID_MIXER_IFACE 44 +-#define CLKID_ADC 45 +-#define CLKID_BLKMV 46 +-#define CLKID_AIU 47 +-#define CLKID_UART1 48 +-#define CLKID_G2D 49 +-#define CLKID_USB0 50 +-#define CLKID_USB1 51 +-#define CLKID_RESET 52 +-#define CLKID_NAND 53 +-#define CLKID_DOS_PARSER 54 +-#define CLKID_USB 55 +-#define CLKID_VDIN1 56 +-#define CLKID_AHB_ARB0 57 +-#define CLKID_EFUSE 58 +-#define CLKID_BOOT_ROM 59 +-#define CLKID_AHB_DATA_BUS 60 +-#define CLKID_AHB_CTRL_BUS 61 +-#define CLKID_HDMI_INTR_SYNC 62 +-#define CLKID_HDMI_PCLK 63 +-#define CLKID_USB1_DDR_BRIDGE 64 +-#define CLKID_USB0_DDR_BRIDGE 65 +-#define CLKID_MMC_PCLK 66 +-#define CLKID_DVIN 67 +-#define CLKID_UART2 68 +-#define CLKID_SANA 69 +-#define CLKID_VPU_INTR 70 +-#define CLKID_SEC_AHB_AHB3_BRIDGE 71 +-#define CLKID_CLK81_A9 72 +-#define CLKID_VCLK2_VENCI0 73 +-#define CLKID_VCLK2_VENCI1 74 +-#define CLKID_VCLK2_VENCP0 75 +-#define CLKID_VCLK2_VENCP1 76 +-#define CLKID_GCLK_VENCI_INT 77 +-#define CLKID_GCLK_VENCP_INT 78 +-#define CLKID_DAC_CLK 79 +-#define CLKID_AOCLK_GATE 80 +-#define CLKID_IEC958_GATE 81 +-#define CLKID_ENC480P 82 +-#define CLKID_RNG1 83 +-#define CLKID_GCLK_VENCL_INT 84 +-#define CLKID_VCLK2_VENCLMCC 85 +-#define CLKID_VCLK2_VENCL 86 +-#define CLKID_VCLK2_OTHER 87 +-#define CLKID_EDP 88 +-#define CLKID_AO_MEDIA_CPU 89 +-#define CLKID_AO_AHB_SRAM 90 +-#define CLKID_AO_AHB_BUS 91 +-#define CLKID_AO_IFACE 92 +-#define CLKID_MPLL0 93 +-#define CLKID_MPLL1 94 +-#define CLKID_MPLL2 95 +-#define CLKID_NAND_CLK 112 +-#define CLKID_APB 124 +-#define CLKID_PERIPH 126 +-#define CLKID_AXI 128 +-#define CLKID_L2_DRAM 130 +-#define CLKID_HDMI_SYS 174 +-#define CLKID_VPU 190 +-#define CLKID_VDEC_1 196 +-#define CLKID_VDEC_HCODEC 199 +-#define CLKID_VDEC_2 202 +-#define CLKID_VDEC_HEVC 206 +-#define CLKID_CTS_AMCLK 209 +-#define CLKID_CTS_MCLK_I958 212 +-#define CLKID_CTS_I958 213 +- +-#endif /* __MESON8B_CLKC_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/microchip,pic32-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/microchip,pic32-clock.h +deleted file mode 100644 +index 371668d98997..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/microchip,pic32-clock.h ++++ /dev/null +@@ -1,34 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Purna Chandra Mandal, +- * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ +-#define _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ +- +-/* clock output indices */ +-#define POSCCLK 0 +-#define FRCCLK 1 +-#define BFRCCLK 2 +-#define LPRCCLK 3 +-#define SOSCCLK 4 +-#define FRCDIVCLK 5 +-#define PLLCLK 6 +-#define SCLK 7 +-#define PB1CLK 8 +-#define PB2CLK 9 +-#define PB3CLK 10 +-#define PB4CLK 11 +-#define PB5CLK 12 +-#define PB6CLK 13 +-#define PB7CLK 14 +-#define REF1CLK 15 +-#define REF2CLK 16 +-#define REF3CLK 17 +-#define REF4CLK 18 +-#define REF5CLK 19 +-#define UPLLCLK 20 +-#define MAXCLKS 21 +- +-#endif /* _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/microchip,sparx5.h b/scripts/dtc/include-prefixes/dt-bindings/clock/microchip,sparx5.h +deleted file mode 100644 +index 4b04dabacec2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/microchip,sparx5.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2019 Microchip Inc. +- * +- * Author: Lars Povlsen +- */ +- +-#ifndef _DT_BINDINGS_CLK_SPARX5_H +-#define _DT_BINDINGS_CLK_SPARX5_H +- +-#define CLK_ID_CORE 0 +-#define CLK_ID_DDR 1 +-#define CLK_ID_CPU2 2 +-#define CLK_ID_ARM2 3 +-#define CLK_ID_AUX1 4 +-#define CLK_ID_AUX2 5 +-#define CLK_ID_AUX3 6 +-#define CLK_ID_AUX4 7 +-#define CLK_ID_SYNCE 8 +- +-#define N_CLOCKS 9 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/mpc512x-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/mpc512x-clock.h +deleted file mode 100644 +index 13c316bf2796..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/mpc512x-clock.h ++++ /dev/null +@@ -1,77 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for MPC512x clock specs in DT bindings. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H +-#define _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H +- +-#define MPC512x_CLK_DUMMY 0 +-#define MPC512x_CLK_REF 1 +-#define MPC512x_CLK_SYS 2 +-#define MPC512x_CLK_DIU 3 +-#define MPC512x_CLK_VIU 4 +-#define MPC512x_CLK_CSB 5 +-#define MPC512x_CLK_E300 6 +-#define MPC512x_CLK_IPS 7 +-#define MPC512x_CLK_FEC 8 +-#define MPC512x_CLK_SATA 9 +-#define MPC512x_CLK_PATA 10 +-#define MPC512x_CLK_NFC 11 +-#define MPC512x_CLK_LPC 12 +-#define MPC512x_CLK_MBX_BUS 13 +-#define MPC512x_CLK_MBX 14 +-#define MPC512x_CLK_MBX_3D 15 +-#define MPC512x_CLK_AXE 16 +-#define MPC512x_CLK_USB1 17 +-#define MPC512x_CLK_USB2 18 +-#define MPC512x_CLK_I2C 19 +-#define MPC512x_CLK_MSCAN0_MCLK 20 +-#define MPC512x_CLK_MSCAN1_MCLK 21 +-#define MPC512x_CLK_MSCAN2_MCLK 22 +-#define MPC512x_CLK_MSCAN3_MCLK 23 +-#define MPC512x_CLK_BDLC 24 +-#define MPC512x_CLK_SDHC 25 +-#define MPC512x_CLK_PCI 26 +-#define MPC512x_CLK_PSC_MCLK_IN 27 +-#define MPC512x_CLK_SPDIF_TX 28 +-#define MPC512x_CLK_SPDIF_RX 29 +-#define MPC512x_CLK_SPDIF_MCLK 30 +-#define MPC512x_CLK_SPDIF 31 +-#define MPC512x_CLK_AC97 32 +-#define MPC512x_CLK_PSC0_MCLK 33 +-#define MPC512x_CLK_PSC1_MCLK 34 +-#define MPC512x_CLK_PSC2_MCLK 35 +-#define MPC512x_CLK_PSC3_MCLK 36 +-#define MPC512x_CLK_PSC4_MCLK 37 +-#define MPC512x_CLK_PSC5_MCLK 38 +-#define MPC512x_CLK_PSC6_MCLK 39 +-#define MPC512x_CLK_PSC7_MCLK 40 +-#define MPC512x_CLK_PSC8_MCLK 41 +-#define MPC512x_CLK_PSC9_MCLK 42 +-#define MPC512x_CLK_PSC10_MCLK 43 +-#define MPC512x_CLK_PSC11_MCLK 44 +-#define MPC512x_CLK_PSC_FIFO 45 +-#define MPC512x_CLK_PSC0 46 +-#define MPC512x_CLK_PSC1 47 +-#define MPC512x_CLK_PSC2 48 +-#define MPC512x_CLK_PSC3 49 +-#define MPC512x_CLK_PSC4 50 +-#define MPC512x_CLK_PSC5 51 +-#define MPC512x_CLK_PSC6 52 +-#define MPC512x_CLK_PSC7 53 +-#define MPC512x_CLK_PSC8 54 +-#define MPC512x_CLK_PSC9 55 +-#define MPC512x_CLK_PSC10 56 +-#define MPC512x_CLK_PSC11 57 +-#define MPC512x_CLK_SDHC2 58 +-#define MPC512x_CLK_FEC2 59 +-#define MPC512x_CLK_OUT0_CLK 60 +-#define MPC512x_CLK_OUT1_CLK 61 +-#define MPC512x_CLK_OUT2_CLK 62 +-#define MPC512x_CLK_OUT3_CLK 63 +-#define MPC512x_CLK_CAN_CLK_IN 64 +- +-#define MPC512x_CLK_LAST_PUBLIC 64 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/mstar-msc313-mpll.h b/scripts/dtc/include-prefixes/dt-bindings/clock/mstar-msc313-mpll.h +deleted file mode 100644 +index 1b30b02317b6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/mstar-msc313-mpll.h ++++ /dev/null +@@ -1,19 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +-/* +- * Output definitions for the MStar/SigmaStar MPLL +- * +- * Copyright (C) 2020 Daniel Palmer +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_MSTAR_MSC313_MPLL_H +-#define _DT_BINDINGS_CLOCK_MSTAR_MSC313_MPLL_H +- +-#define MSTAR_MSC313_MPLL_DIV2 1 +-#define MSTAR_MSC313_MPLL_DIV3 2 +-#define MSTAR_MSC313_MPLL_DIV4 3 +-#define MSTAR_MSC313_MPLL_DIV5 4 +-#define MSTAR_MSC313_MPLL_DIV6 5 +-#define MSTAR_MSC313_MPLL_DIV7 6 +-#define MSTAR_MSC313_MPLL_DIV10 7 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/mt2701-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/mt2701-clk.h +deleted file mode 100644 +index 6d531d5ae065..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/mt2701-clk.h ++++ /dev/null +@@ -1,484 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014 MediaTek Inc. +- * Author: Shunli Wang +- */ +- +-#ifndef _DT_BINDINGS_CLK_MT2701_H +-#define _DT_BINDINGS_CLK_MT2701_H +- +-/* TOPCKGEN */ +-#define CLK_TOP_SYSPLL 1 +-#define CLK_TOP_SYSPLL_D2 2 +-#define CLK_TOP_SYSPLL_D3 3 +-#define CLK_TOP_SYSPLL_D5 4 +-#define CLK_TOP_SYSPLL_D7 5 +-#define CLK_TOP_SYSPLL1_D2 6 +-#define CLK_TOP_SYSPLL1_D4 7 +-#define CLK_TOP_SYSPLL1_D8 8 +-#define CLK_TOP_SYSPLL1_D16 9 +-#define CLK_TOP_SYSPLL2_D2 10 +-#define CLK_TOP_SYSPLL2_D4 11 +-#define CLK_TOP_SYSPLL2_D8 12 +-#define CLK_TOP_SYSPLL3_D2 13 +-#define CLK_TOP_SYSPLL3_D4 14 +-#define CLK_TOP_SYSPLL4_D2 15 +-#define CLK_TOP_SYSPLL4_D4 16 +-#define CLK_TOP_UNIVPLL 17 +-#define CLK_TOP_UNIVPLL_D2 18 +-#define CLK_TOP_UNIVPLL_D3 19 +-#define CLK_TOP_UNIVPLL_D5 20 +-#define CLK_TOP_UNIVPLL_D7 21 +-#define CLK_TOP_UNIVPLL_D26 22 +-#define CLK_TOP_UNIVPLL_D52 23 +-#define CLK_TOP_UNIVPLL_D108 24 +-#define CLK_TOP_USB_PHY48M 25 +-#define CLK_TOP_UNIVPLL1_D2 26 +-#define CLK_TOP_UNIVPLL1_D4 27 +-#define CLK_TOP_UNIVPLL1_D8 28 +-#define CLK_TOP_UNIVPLL2_D2 29 +-#define CLK_TOP_UNIVPLL2_D4 30 +-#define CLK_TOP_UNIVPLL2_D8 31 +-#define CLK_TOP_UNIVPLL2_D16 32 +-#define CLK_TOP_UNIVPLL2_D32 33 +-#define CLK_TOP_UNIVPLL3_D2 34 +-#define CLK_TOP_UNIVPLL3_D4 35 +-#define CLK_TOP_UNIVPLL3_D8 36 +-#define CLK_TOP_MSDCPLL 37 +-#define CLK_TOP_MSDCPLL_D2 38 +-#define CLK_TOP_MSDCPLL_D4 39 +-#define CLK_TOP_MSDCPLL_D8 40 +-#define CLK_TOP_MMPLL 41 +-#define CLK_TOP_MMPLL_D2 42 +-#define CLK_TOP_DMPLL 43 +-#define CLK_TOP_DMPLL_D2 44 +-#define CLK_TOP_DMPLL_D4 45 +-#define CLK_TOP_DMPLL_X2 46 +-#define CLK_TOP_TVDPLL 47 +-#define CLK_TOP_TVDPLL_D2 48 +-#define CLK_TOP_TVDPLL_D4 49 +-#define CLK_TOP_TVD2PLL 50 +-#define CLK_TOP_TVD2PLL_D2 51 +-#define CLK_TOP_HADDS2PLL_98M 52 +-#define CLK_TOP_HADDS2PLL_294M 53 +-#define CLK_TOP_HADDS2_FB 54 +-#define CLK_TOP_MIPIPLL_D2 55 +-#define CLK_TOP_MIPIPLL_D4 56 +-#define CLK_TOP_HDMIPLL 57 +-#define CLK_TOP_HDMIPLL_D2 58 +-#define CLK_TOP_HDMIPLL_D3 59 +-#define CLK_TOP_HDMI_SCL_RX 60 +-#define CLK_TOP_HDMI_0_PIX340M 61 +-#define CLK_TOP_HDMI_0_DEEP340M 62 +-#define CLK_TOP_HDMI_0_PLL340M 63 +-#define CLK_TOP_AUD1PLL_98M 64 +-#define CLK_TOP_AUD2PLL_90M 65 +-#define CLK_TOP_AUDPLL 66 +-#define CLK_TOP_AUDPLL_D4 67 +-#define CLK_TOP_AUDPLL_D8 68 +-#define CLK_TOP_AUDPLL_D16 69 +-#define CLK_TOP_AUDPLL_D24 70 +-#define CLK_TOP_ETHPLL_500M 71 +-#define CLK_TOP_VDECPLL 72 +-#define CLK_TOP_VENCPLL 73 +-#define CLK_TOP_MIPIPLL 74 +-#define CLK_TOP_ARMPLL_1P3G 75 +- +-#define CLK_TOP_MM_SEL 76 +-#define CLK_TOP_DDRPHYCFG_SEL 77 +-#define CLK_TOP_MEM_SEL 78 +-#define CLK_TOP_AXI_SEL 79 +-#define CLK_TOP_CAMTG_SEL 80 +-#define CLK_TOP_MFG_SEL 81 +-#define CLK_TOP_VDEC_SEL 82 +-#define CLK_TOP_PWM_SEL 83 +-#define CLK_TOP_MSDC30_0_SEL 84 +-#define CLK_TOP_USB20_SEL 85 +-#define CLK_TOP_SPI0_SEL 86 +-#define CLK_TOP_UART_SEL 87 +-#define CLK_TOP_AUDINTBUS_SEL 88 +-#define CLK_TOP_AUDIO_SEL 89 +-#define CLK_TOP_MSDC30_2_SEL 90 +-#define CLK_TOP_MSDC30_1_SEL 91 +-#define CLK_TOP_DPI1_SEL 92 +-#define CLK_TOP_DPI0_SEL 93 +-#define CLK_TOP_SCP_SEL 94 +-#define CLK_TOP_PMICSPI_SEL 95 +-#define CLK_TOP_APLL_SEL 96 +-#define CLK_TOP_HDMI_SEL 97 +-#define CLK_TOP_TVE_SEL 98 +-#define CLK_TOP_EMMC_HCLK_SEL 99 +-#define CLK_TOP_NFI2X_SEL 100 +-#define CLK_TOP_RTC_SEL 101 +-#define CLK_TOP_OSD_SEL 102 +-#define CLK_TOP_NR_SEL 103 +-#define CLK_TOP_DI_SEL 104 +-#define CLK_TOP_FLASH_SEL 105 +-#define CLK_TOP_ASM_M_SEL 106 +-#define CLK_TOP_ASM_I_SEL 107 +-#define CLK_TOP_INTDIR_SEL 108 +-#define CLK_TOP_HDMIRX_BIST_SEL 109 +-#define CLK_TOP_ETHIF_SEL 110 +-#define CLK_TOP_MS_CARD_SEL 111 +-#define CLK_TOP_ASM_H_SEL 112 +-#define CLK_TOP_SPI1_SEL 113 +-#define CLK_TOP_CMSYS_SEL 114 +-#define CLK_TOP_MSDC30_3_SEL 115 +-#define CLK_TOP_HDMIRX26_24_SEL 116 +-#define CLK_TOP_AUD2DVD_SEL 117 +-#define CLK_TOP_8BDAC_SEL 118 +-#define CLK_TOP_SPI2_SEL 119 +-#define CLK_TOP_AUD_MUX1_SEL 120 +-#define CLK_TOP_AUD_MUX2_SEL 121 +-#define CLK_TOP_AUDPLL_MUX_SEL 122 +-#define CLK_TOP_AUD_K1_SRC_SEL 123 +-#define CLK_TOP_AUD_K2_SRC_SEL 124 +-#define CLK_TOP_AUD_K3_SRC_SEL 125 +-#define CLK_TOP_AUD_K4_SRC_SEL 126 +-#define CLK_TOP_AUD_K5_SRC_SEL 127 +-#define CLK_TOP_AUD_K6_SRC_SEL 128 +-#define CLK_TOP_PADMCLK_SEL 129 +-#define CLK_TOP_AUD_EXTCK1_DIV 130 +-#define CLK_TOP_AUD_EXTCK2_DIV 131 +-#define CLK_TOP_AUD_MUX1_DIV 132 +-#define CLK_TOP_AUD_MUX2_DIV 133 +-#define CLK_TOP_AUD_K1_SRC_DIV 134 +-#define CLK_TOP_AUD_K2_SRC_DIV 135 +-#define CLK_TOP_AUD_K3_SRC_DIV 136 +-#define CLK_TOP_AUD_K4_SRC_DIV 137 +-#define CLK_TOP_AUD_K5_SRC_DIV 138 +-#define CLK_TOP_AUD_K6_SRC_DIV 139 +-#define CLK_TOP_AUD_I2S1_MCLK 140 +-#define CLK_TOP_AUD_I2S2_MCLK 141 +-#define CLK_TOP_AUD_I2S3_MCLK 142 +-#define CLK_TOP_AUD_I2S4_MCLK 143 +-#define CLK_TOP_AUD_I2S5_MCLK 144 +-#define CLK_TOP_AUD_I2S6_MCLK 145 +-#define CLK_TOP_AUD_48K_TIMING 146 +-#define CLK_TOP_AUD_44K_TIMING 147 +- +-#define CLK_TOP_32K_INTERNAL 148 +-#define CLK_TOP_32K_EXTERNAL 149 +-#define CLK_TOP_CLK26M_D8 150 +-#define CLK_TOP_8BDAC 151 +-#define CLK_TOP_WBG_DIG_416M 152 +-#define CLK_TOP_DPI 153 +-#define CLK_TOP_DSI0_LNTC_DSI 154 +-#define CLK_TOP_AUD_EXT1 155 +-#define CLK_TOP_AUD_EXT2 156 +-#define CLK_TOP_NFI1X_PAD 157 +-#define CLK_TOP_AXISEL_D4 158 +-#define CLK_TOP_NR 159 +- +-/* APMIXEDSYS */ +- +-#define CLK_APMIXED_ARMPLL 1 +-#define CLK_APMIXED_MAINPLL 2 +-#define CLK_APMIXED_UNIVPLL 3 +-#define CLK_APMIXED_MMPLL 4 +-#define CLK_APMIXED_MSDCPLL 5 +-#define CLK_APMIXED_TVDPLL 6 +-#define CLK_APMIXED_AUD1PLL 7 +-#define CLK_APMIXED_TRGPLL 8 +-#define CLK_APMIXED_ETHPLL 9 +-#define CLK_APMIXED_VDECPLL 10 +-#define CLK_APMIXED_HADDS2PLL 11 +-#define CLK_APMIXED_AUD2PLL 12 +-#define CLK_APMIXED_TVD2PLL 13 +-#define CLK_APMIXED_HDMI_REF 14 +-#define CLK_APMIXED_NR 15 +- +-/* DDRPHY */ +- +-#define CLK_DDRPHY_VENCPLL 1 +-#define CLK_DDRPHY_NR 2 +- +-/* INFRACFG */ +- +-#define CLK_INFRA_DBG 1 +-#define CLK_INFRA_SMI 2 +-#define CLK_INFRA_QAXI_CM4 3 +-#define CLK_INFRA_AUD_SPLIN_B 4 +-#define CLK_INFRA_AUDIO 5 +-#define CLK_INFRA_EFUSE 6 +-#define CLK_INFRA_L2C_SRAM 7 +-#define CLK_INFRA_M4U 8 +-#define CLK_INFRA_CONNMCU 9 +-#define CLK_INFRA_TRNG 10 +-#define CLK_INFRA_RAMBUFIF 11 +-#define CLK_INFRA_CPUM 12 +-#define CLK_INFRA_KP 13 +-#define CLK_INFRA_CEC 14 +-#define CLK_INFRA_IRRX 15 +-#define CLK_INFRA_PMICSPI 16 +-#define CLK_INFRA_PMICWRAP 17 +-#define CLK_INFRA_DDCCI 18 +-#define CLK_INFRA_CLK_13M 19 +-#define CLK_INFRA_CPUSEL 20 +-#define CLK_INFRA_NR 21 +- +-/* PERICFG */ +- +-#define CLK_PERI_NFI 1 +-#define CLK_PERI_THERM 2 +-#define CLK_PERI_PWM1 3 +-#define CLK_PERI_PWM2 4 +-#define CLK_PERI_PWM3 5 +-#define CLK_PERI_PWM4 6 +-#define CLK_PERI_PWM5 7 +-#define CLK_PERI_PWM6 8 +-#define CLK_PERI_PWM7 9 +-#define CLK_PERI_PWM 10 +-#define CLK_PERI_USB0 11 +-#define CLK_PERI_USB1 12 +-#define CLK_PERI_AP_DMA 13 +-#define CLK_PERI_MSDC30_0 14 +-#define CLK_PERI_MSDC30_1 15 +-#define CLK_PERI_MSDC30_2 16 +-#define CLK_PERI_MSDC30_3 17 +-#define CLK_PERI_MSDC50_3 18 +-#define CLK_PERI_NLI 19 +-#define CLK_PERI_UART0 20 +-#define CLK_PERI_UART1 21 +-#define CLK_PERI_UART2 22 +-#define CLK_PERI_UART3 23 +-#define CLK_PERI_BTIF 24 +-#define CLK_PERI_I2C0 25 +-#define CLK_PERI_I2C1 26 +-#define CLK_PERI_I2C2 27 +-#define CLK_PERI_I2C3 28 +-#define CLK_PERI_AUXADC 29 +-#define CLK_PERI_SPI0 30 +-#define CLK_PERI_ETH 31 +-#define CLK_PERI_USB0_MCU 32 +- +-#define CLK_PERI_USB1_MCU 33 +-#define CLK_PERI_USB_SLV 34 +-#define CLK_PERI_GCPU 35 +-#define CLK_PERI_NFI_ECC 36 +-#define CLK_PERI_NFI_PAD 37 +-#define CLK_PERI_FLASH 38 +-#define CLK_PERI_HOST89_INT 39 +-#define CLK_PERI_HOST89_SPI 40 +-#define CLK_PERI_HOST89_DVD 41 +-#define CLK_PERI_SPI1 42 +-#define CLK_PERI_SPI2 43 +-#define CLK_PERI_FCI 44 +- +-#define CLK_PERI_UART0_SEL 45 +-#define CLK_PERI_UART1_SEL 46 +-#define CLK_PERI_UART2_SEL 47 +-#define CLK_PERI_UART3_SEL 48 +-#define CLK_PERI_NR 49 +- +-/* AUDIO */ +- +-#define CLK_AUD_AFE 1 +-#define CLK_AUD_LRCK_DETECT 2 +-#define CLK_AUD_I2S 3 +-#define CLK_AUD_APLL_TUNER 4 +-#define CLK_AUD_HDMI 5 +-#define CLK_AUD_SPDF 6 +-#define CLK_AUD_SPDF2 7 +-#define CLK_AUD_APLL 8 +-#define CLK_AUD_TML 9 +-#define CLK_AUD_AHB_IDLE_EXT 10 +-#define CLK_AUD_AHB_IDLE_INT 11 +- +-#define CLK_AUD_I2SIN1 12 +-#define CLK_AUD_I2SIN2 13 +-#define CLK_AUD_I2SIN3 14 +-#define CLK_AUD_I2SIN4 15 +-#define CLK_AUD_I2SIN5 16 +-#define CLK_AUD_I2SIN6 17 +-#define CLK_AUD_I2SO1 18 +-#define CLK_AUD_I2SO2 19 +-#define CLK_AUD_I2SO3 20 +-#define CLK_AUD_I2SO4 21 +-#define CLK_AUD_I2SO5 22 +-#define CLK_AUD_I2SO6 23 +-#define CLK_AUD_ASRCI1 24 +-#define CLK_AUD_ASRCI2 25 +-#define CLK_AUD_ASRCO1 26 +-#define CLK_AUD_ASRCO2 27 +-#define CLK_AUD_ASRC11 28 +-#define CLK_AUD_ASRC12 29 +-#define CLK_AUD_HDMIRX 30 +-#define CLK_AUD_INTDIR 31 +-#define CLK_AUD_A1SYS 32 +-#define CLK_AUD_A2SYS 33 +-#define CLK_AUD_AFE_CONN 34 +-#define CLK_AUD_AFE_PCMIF 35 +-#define CLK_AUD_AFE_MRGIF 36 +- +-#define CLK_AUD_MMIF_UL1 37 +-#define CLK_AUD_MMIF_UL2 38 +-#define CLK_AUD_MMIF_UL3 39 +-#define CLK_AUD_MMIF_UL4 40 +-#define CLK_AUD_MMIF_UL5 41 +-#define CLK_AUD_MMIF_UL6 42 +-#define CLK_AUD_MMIF_DL1 43 +-#define CLK_AUD_MMIF_DL2 44 +-#define CLK_AUD_MMIF_DL3 45 +-#define CLK_AUD_MMIF_DL4 46 +-#define CLK_AUD_MMIF_DL5 47 +-#define CLK_AUD_MMIF_DL6 48 +-#define CLK_AUD_MMIF_DLMCH 49 +-#define CLK_AUD_MMIF_ARB1 50 +-#define CLK_AUD_MMIF_AWB1 51 +-#define CLK_AUD_MMIF_AWB2 52 +-#define CLK_AUD_MMIF_DAI 53 +- +-#define CLK_AUD_DMIC1 54 +-#define CLK_AUD_DMIC2 55 +-#define CLK_AUD_ASRCI3 56 +-#define CLK_AUD_ASRCI4 57 +-#define CLK_AUD_ASRCI5 58 +-#define CLK_AUD_ASRCI6 59 +-#define CLK_AUD_ASRCO3 60 +-#define CLK_AUD_ASRCO4 61 +-#define CLK_AUD_ASRCO5 62 +-#define CLK_AUD_ASRCO6 63 +-#define CLK_AUD_MEM_ASRC1 64 +-#define CLK_AUD_MEM_ASRC2 65 +-#define CLK_AUD_MEM_ASRC3 66 +-#define CLK_AUD_MEM_ASRC4 67 +-#define CLK_AUD_MEM_ASRC5 68 +-#define CLK_AUD_DSD_ENC 69 +-#define CLK_AUD_ASRC_BRG 70 +-#define CLK_AUD_NR 71 +- +-/* MMSYS */ +- +-#define CLK_MM_SMI_COMMON 1 +-#define CLK_MM_SMI_LARB0 2 +-#define CLK_MM_CMDQ 3 +-#define CLK_MM_MUTEX 4 +-#define CLK_MM_DISP_COLOR 5 +-#define CLK_MM_DISP_BLS 6 +-#define CLK_MM_DISP_WDMA 7 +-#define CLK_MM_DISP_RDMA 8 +-#define CLK_MM_DISP_OVL 9 +-#define CLK_MM_MDP_TDSHP 10 +-#define CLK_MM_MDP_WROT 11 +-#define CLK_MM_MDP_WDMA 12 +-#define CLK_MM_MDP_RSZ1 13 +-#define CLK_MM_MDP_RSZ0 14 +-#define CLK_MM_MDP_RDMA 15 +-#define CLK_MM_MDP_BLS_26M 16 +-#define CLK_MM_CAM_MDP 17 +-#define CLK_MM_FAKE_ENG 18 +-#define CLK_MM_MUTEX_32K 19 +-#define CLK_MM_DISP_RDMA1 20 +-#define CLK_MM_DISP_UFOE 21 +- +-#define CLK_MM_DSI_ENGINE 22 +-#define CLK_MM_DSI_DIG 23 +-#define CLK_MM_DPI_DIGL 24 +-#define CLK_MM_DPI_ENGINE 25 +-#define CLK_MM_DPI1_DIGL 26 +-#define CLK_MM_DPI1_ENGINE 27 +-#define CLK_MM_TVE_OUTPUT 28 +-#define CLK_MM_TVE_INPUT 29 +-#define CLK_MM_HDMI_PIXEL 30 +-#define CLK_MM_HDMI_PLL 31 +-#define CLK_MM_HDMI_AUDIO 32 +-#define CLK_MM_HDMI_SPDIF 33 +-#define CLK_MM_TVE_FMM 34 +-#define CLK_MM_NR 35 +- +-/* IMGSYS */ +- +-#define CLK_IMG_SMI_COMM 1 +-#define CLK_IMG_RESZ 2 +-#define CLK_IMG_JPGDEC_SMI 3 +-#define CLK_IMG_JPGDEC 4 +-#define CLK_IMG_VENC_LT 5 +-#define CLK_IMG_VENC 6 +-#define CLK_IMG_NR 7 +- +-/* VDEC */ +- +-#define CLK_VDEC_CKGEN 1 +-#define CLK_VDEC_LARB 2 +-#define CLK_VDEC_NR 3 +- +-/* HIFSYS */ +- +-#define CLK_HIFSYS_USB0PHY 1 +-#define CLK_HIFSYS_USB1PHY 2 +-#define CLK_HIFSYS_PCIE0 3 +-#define CLK_HIFSYS_PCIE1 4 +-#define CLK_HIFSYS_PCIE2 5 +-#define CLK_HIFSYS_NR 6 +- +-/* ETHSYS */ +-#define CLK_ETHSYS_HSDMA 1 +-#define CLK_ETHSYS_ESW 2 +-#define CLK_ETHSYS_GP2 3 +-#define CLK_ETHSYS_GP1 4 +-#define CLK_ETHSYS_PCM 5 +-#define CLK_ETHSYS_GDMA 6 +-#define CLK_ETHSYS_I2S 7 +-#define CLK_ETHSYS_CRYPTO 8 +-#define CLK_ETHSYS_NR 9 +- +-/* G3DSYS */ +-#define CLK_G3DSYS_CORE 1 +-#define CLK_G3DSYS_NR 2 +- +-/* BDP */ +- +-#define CLK_BDP_BRG_BA 1 +-#define CLK_BDP_BRG_DRAM 2 +-#define CLK_BDP_LARB_DRAM 3 +-#define CLK_BDP_WR_VDI_PXL 4 +-#define CLK_BDP_WR_VDI_DRAM 5 +-#define CLK_BDP_WR_B 6 +-#define CLK_BDP_DGI_IN 7 +-#define CLK_BDP_DGI_OUT 8 +-#define CLK_BDP_FMT_MAST_27 9 +-#define CLK_BDP_FMT_B 10 +-#define CLK_BDP_OSD_B 11 +-#define CLK_BDP_OSD_DRAM 12 +-#define CLK_BDP_OSD_AGENT 13 +-#define CLK_BDP_OSD_PXL 14 +-#define CLK_BDP_RLE_B 15 +-#define CLK_BDP_RLE_AGENT 16 +-#define CLK_BDP_RLE_DRAM 17 +-#define CLK_BDP_F27M 18 +-#define CLK_BDP_F27M_VDOUT 19 +-#define CLK_BDP_F27_74_74 20 +-#define CLK_BDP_F2FS 21 +-#define CLK_BDP_F2FS74_148 22 +-#define CLK_BDP_FB 23 +-#define CLK_BDP_VDO_DRAM 24 +-#define CLK_BDP_VDO_2FS 25 +-#define CLK_BDP_VDO_B 26 +-#define CLK_BDP_WR_DI_PXL 27 +-#define CLK_BDP_WR_DI_DRAM 28 +-#define CLK_BDP_WR_DI_B 29 +-#define CLK_BDP_NR_PXL 30 +-#define CLK_BDP_NR_DRAM 31 +-#define CLK_BDP_NR_B 32 +- +-#define CLK_BDP_RX_F 33 +-#define CLK_BDP_RX_X 34 +-#define CLK_BDP_RXPDT 35 +-#define CLK_BDP_RX_CSCL_N 36 +-#define CLK_BDP_RX_CSCL 37 +-#define CLK_BDP_RX_DDCSCL_N 38 +-#define CLK_BDP_RX_DDCSCL 39 +-#define CLK_BDP_RX_VCO 40 +-#define CLK_BDP_RX_DP 41 +-#define CLK_BDP_RX_P 42 +-#define CLK_BDP_RX_M 43 +-#define CLK_BDP_RX_PLL 44 +-#define CLK_BDP_BRG_RT_B 45 +-#define CLK_BDP_BRG_RT_DRAM 46 +-#define CLK_BDP_LARBRT_DRAM 47 +-#define CLK_BDP_TMDS_SYN 48 +-#define CLK_BDP_HDMI_MON 49 +-#define CLK_BDP_NR 50 +- +-#endif /* _DT_BINDINGS_CLK_MT2701_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/mt2712-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/mt2712-clk.h +deleted file mode 100644 +index 0800d9ce7c6a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/mt2712-clk.h ++++ /dev/null +@@ -1,428 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2017 MediaTek Inc. +- * Author: Weiyi Lu +- */ +- +-#ifndef _DT_BINDINGS_CLK_MT2712_H +-#define _DT_BINDINGS_CLK_MT2712_H +- +-/* APMIXEDSYS */ +- +-#define CLK_APMIXED_MAINPLL 0 +-#define CLK_APMIXED_UNIVPLL 1 +-#define CLK_APMIXED_VCODECPLL 2 +-#define CLK_APMIXED_VENCPLL 3 +-#define CLK_APMIXED_APLL1 4 +-#define CLK_APMIXED_APLL2 5 +-#define CLK_APMIXED_LVDSPLL 6 +-#define CLK_APMIXED_LVDSPLL2 7 +-#define CLK_APMIXED_MSDCPLL 8 +-#define CLK_APMIXED_MSDCPLL2 9 +-#define CLK_APMIXED_TVDPLL 10 +-#define CLK_APMIXED_MMPLL 11 +-#define CLK_APMIXED_ARMCA35PLL 12 +-#define CLK_APMIXED_ARMCA72PLL 13 +-#define CLK_APMIXED_ETHERPLL 14 +-#define CLK_APMIXED_NR_CLK 15 +- +-/* TOPCKGEN */ +- +-#define CLK_TOP_ARMCA35PLL 0 +-#define CLK_TOP_ARMCA35PLL_600M 1 +-#define CLK_TOP_ARMCA35PLL_400M 2 +-#define CLK_TOP_ARMCA72PLL 3 +-#define CLK_TOP_SYSPLL 4 +-#define CLK_TOP_SYSPLL_D2 5 +-#define CLK_TOP_SYSPLL1_D2 6 +-#define CLK_TOP_SYSPLL1_D4 7 +-#define CLK_TOP_SYSPLL1_D8 8 +-#define CLK_TOP_SYSPLL1_D16 9 +-#define CLK_TOP_SYSPLL_D3 10 +-#define CLK_TOP_SYSPLL2_D2 11 +-#define CLK_TOP_SYSPLL2_D4 12 +-#define CLK_TOP_SYSPLL_D5 13 +-#define CLK_TOP_SYSPLL3_D2 14 +-#define CLK_TOP_SYSPLL3_D4 15 +-#define CLK_TOP_SYSPLL_D7 16 +-#define CLK_TOP_SYSPLL4_D2 17 +-#define CLK_TOP_SYSPLL4_D4 18 +-#define CLK_TOP_UNIVPLL 19 +-#define CLK_TOP_UNIVPLL_D7 20 +-#define CLK_TOP_UNIVPLL_D26 21 +-#define CLK_TOP_UNIVPLL_D52 22 +-#define CLK_TOP_UNIVPLL_D104 23 +-#define CLK_TOP_UNIVPLL_D208 24 +-#define CLK_TOP_UNIVPLL_D2 25 +-#define CLK_TOP_UNIVPLL1_D2 26 +-#define CLK_TOP_UNIVPLL1_D4 27 +-#define CLK_TOP_UNIVPLL1_D8 28 +-#define CLK_TOP_UNIVPLL_D3 29 +-#define CLK_TOP_UNIVPLL2_D2 30 +-#define CLK_TOP_UNIVPLL2_D4 31 +-#define CLK_TOP_UNIVPLL2_D8 32 +-#define CLK_TOP_UNIVPLL_D5 33 +-#define CLK_TOP_UNIVPLL3_D2 34 +-#define CLK_TOP_UNIVPLL3_D4 35 +-#define CLK_TOP_UNIVPLL3_D8 36 +-#define CLK_TOP_F_MP0_PLL1 37 +-#define CLK_TOP_F_MP0_PLL2 38 +-#define CLK_TOP_F_BIG_PLL1 39 +-#define CLK_TOP_F_BIG_PLL2 40 +-#define CLK_TOP_F_BUS_PLL1 41 +-#define CLK_TOP_F_BUS_PLL2 42 +-#define CLK_TOP_APLL1 43 +-#define CLK_TOP_APLL1_D2 44 +-#define CLK_TOP_APLL1_D4 45 +-#define CLK_TOP_APLL1_D8 46 +-#define CLK_TOP_APLL1_D16 47 +-#define CLK_TOP_APLL2 48 +-#define CLK_TOP_APLL2_D2 49 +-#define CLK_TOP_APLL2_D4 50 +-#define CLK_TOP_APLL2_D8 51 +-#define CLK_TOP_APLL2_D16 52 +-#define CLK_TOP_LVDSPLL 53 +-#define CLK_TOP_LVDSPLL_D2 54 +-#define CLK_TOP_LVDSPLL_D4 55 +-#define CLK_TOP_LVDSPLL_D8 56 +-#define CLK_TOP_LVDSPLL2 57 +-#define CLK_TOP_LVDSPLL2_D2 58 +-#define CLK_TOP_LVDSPLL2_D4 59 +-#define CLK_TOP_LVDSPLL2_D8 60 +-#define CLK_TOP_ETHERPLL_125M 61 +-#define CLK_TOP_ETHERPLL_50M 62 +-#define CLK_TOP_CVBS 63 +-#define CLK_TOP_CVBS_D2 64 +-#define CLK_TOP_SYS_26M 65 +-#define CLK_TOP_MMPLL 66 +-#define CLK_TOP_MMPLL_D2 67 +-#define CLK_TOP_VENCPLL 68 +-#define CLK_TOP_VENCPLL_D2 69 +-#define CLK_TOP_VCODECPLL 70 +-#define CLK_TOP_VCODECPLL_D2 71 +-#define CLK_TOP_TVDPLL 72 +-#define CLK_TOP_TVDPLL_D2 73 +-#define CLK_TOP_TVDPLL_D4 74 +-#define CLK_TOP_TVDPLL_D8 75 +-#define CLK_TOP_TVDPLL_429M 76 +-#define CLK_TOP_TVDPLL_429M_D2 77 +-#define CLK_TOP_TVDPLL_429M_D4 78 +-#define CLK_TOP_MSDCPLL 79 +-#define CLK_TOP_MSDCPLL_D2 80 +-#define CLK_TOP_MSDCPLL_D4 81 +-#define CLK_TOP_MSDCPLL2 82 +-#define CLK_TOP_MSDCPLL2_D2 83 +-#define CLK_TOP_MSDCPLL2_D4 84 +-#define CLK_TOP_CLK26M_D2 85 +-#define CLK_TOP_D2A_ULCLK_6P5M 86 +-#define CLK_TOP_VPLL3_DPIX 87 +-#define CLK_TOP_VPLL_DPIX 88 +-#define CLK_TOP_LTEPLL_FS26M 89 +-#define CLK_TOP_DMPLL 90 +-#define CLK_TOP_DSI0_LNTC 91 +-#define CLK_TOP_DSI1_LNTC 92 +-#define CLK_TOP_LVDSTX3_CLKDIG_CTS 93 +-#define CLK_TOP_LVDSTX_CLKDIG_CTS 94 +-#define CLK_TOP_CLKRTC_EXT 95 +-#define CLK_TOP_CLKRTC_INT 96 +-#define CLK_TOP_CSI0 97 +-#define CLK_TOP_CVBSPLL 98 +-#define CLK_TOP_AXI_SEL 99 +-#define CLK_TOP_MEM_SEL 100 +-#define CLK_TOP_MM_SEL 101 +-#define CLK_TOP_PWM_SEL 102 +-#define CLK_TOP_VDEC_SEL 103 +-#define CLK_TOP_VENC_SEL 104 +-#define CLK_TOP_MFG_SEL 105 +-#define CLK_TOP_CAMTG_SEL 106 +-#define CLK_TOP_UART_SEL 107 +-#define CLK_TOP_SPI_SEL 108 +-#define CLK_TOP_USB20_SEL 109 +-#define CLK_TOP_USB30_SEL 110 +-#define CLK_TOP_MSDC50_0_HCLK_SEL 111 +-#define CLK_TOP_MSDC50_0_SEL 112 +-#define CLK_TOP_MSDC30_1_SEL 113 +-#define CLK_TOP_MSDC30_2_SEL 114 +-#define CLK_TOP_MSDC30_3_SEL 115 +-#define CLK_TOP_AUDIO_SEL 116 +-#define CLK_TOP_AUD_INTBUS_SEL 117 +-#define CLK_TOP_PMICSPI_SEL 118 +-#define CLK_TOP_DPILVDS1_SEL 119 +-#define CLK_TOP_ATB_SEL 120 +-#define CLK_TOP_NR_SEL 121 +-#define CLK_TOP_NFI2X_SEL 122 +-#define CLK_TOP_IRDA_SEL 123 +-#define CLK_TOP_CCI400_SEL 124 +-#define CLK_TOP_AUD_1_SEL 125 +-#define CLK_TOP_AUD_2_SEL 126 +-#define CLK_TOP_MEM_MFG_IN_AS_SEL 127 +-#define CLK_TOP_AXI_MFG_IN_AS_SEL 128 +-#define CLK_TOP_SCAM_SEL 129 +-#define CLK_TOP_NFIECC_SEL 130 +-#define CLK_TOP_PE2_MAC_P0_SEL 131 +-#define CLK_TOP_PE2_MAC_P1_SEL 132 +-#define CLK_TOP_DPILVDS_SEL 133 +-#define CLK_TOP_MSDC50_3_HCLK_SEL 134 +-#define CLK_TOP_HDCP_SEL 135 +-#define CLK_TOP_HDCP_24M_SEL 136 +-#define CLK_TOP_RTC_SEL 137 +-#define CLK_TOP_SPINOR_SEL 138 +-#define CLK_TOP_APLL_SEL 139 +-#define CLK_TOP_APLL2_SEL 140 +-#define CLK_TOP_A1SYS_HP_SEL 141 +-#define CLK_TOP_A2SYS_HP_SEL 142 +-#define CLK_TOP_ASM_L_SEL 143 +-#define CLK_TOP_ASM_M_SEL 144 +-#define CLK_TOP_ASM_H_SEL 145 +-#define CLK_TOP_I2SO1_SEL 146 +-#define CLK_TOP_I2SO2_SEL 147 +-#define CLK_TOP_I2SO3_SEL 148 +-#define CLK_TOP_TDMO0_SEL 149 +-#define CLK_TOP_TDMO1_SEL 150 +-#define CLK_TOP_I2SI1_SEL 151 +-#define CLK_TOP_I2SI2_SEL 152 +-#define CLK_TOP_I2SI3_SEL 153 +-#define CLK_TOP_ETHER_125M_SEL 154 +-#define CLK_TOP_ETHER_50M_SEL 155 +-#define CLK_TOP_JPGDEC_SEL 156 +-#define CLK_TOP_SPISLV_SEL 157 +-#define CLK_TOP_ETHER_50M_RMII_SEL 158 +-#define CLK_TOP_CAM2TG_SEL 159 +-#define CLK_TOP_DI_SEL 160 +-#define CLK_TOP_TVD_SEL 161 +-#define CLK_TOP_I2C_SEL 162 +-#define CLK_TOP_PWM_INFRA_SEL 163 +-#define CLK_TOP_MSDC0P_AES_SEL 164 +-#define CLK_TOP_CMSYS_SEL 165 +-#define CLK_TOP_GCPU_SEL 166 +-#define CLK_TOP_AUD_APLL1_SEL 167 +-#define CLK_TOP_AUD_APLL2_SEL 168 +-#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 169 +-#define CLK_TOP_APLL_DIV0 170 +-#define CLK_TOP_APLL_DIV1 171 +-#define CLK_TOP_APLL_DIV2 172 +-#define CLK_TOP_APLL_DIV3 173 +-#define CLK_TOP_APLL_DIV4 174 +-#define CLK_TOP_APLL_DIV5 175 +-#define CLK_TOP_APLL_DIV6 176 +-#define CLK_TOP_APLL_DIV7 177 +-#define CLK_TOP_APLL_DIV_PDN0 178 +-#define CLK_TOP_APLL_DIV_PDN1 179 +-#define CLK_TOP_APLL_DIV_PDN2 180 +-#define CLK_TOP_APLL_DIV_PDN3 181 +-#define CLK_TOP_APLL_DIV_PDN4 182 +-#define CLK_TOP_APLL_DIV_PDN5 183 +-#define CLK_TOP_APLL_DIV_PDN6 184 +-#define CLK_TOP_APLL_DIV_PDN7 185 +-#define CLK_TOP_APLL1_D3 186 +-#define CLK_TOP_APLL1_REF_SEL 187 +-#define CLK_TOP_APLL2_REF_SEL 188 +-#define CLK_TOP_NFI2X_EN 189 +-#define CLK_TOP_NFIECC_EN 190 +-#define CLK_TOP_NFI1X_CK_EN 191 +-#define CLK_TOP_APLL2_D3 192 +-#define CLK_TOP_NR_CLK 193 +- +-/* INFRACFG */ +- +-#define CLK_INFRA_DBGCLK 0 +-#define CLK_INFRA_GCE 1 +-#define CLK_INFRA_M4U 2 +-#define CLK_INFRA_KP 3 +-#define CLK_INFRA_AO_SPI0 4 +-#define CLK_INFRA_AO_SPI1 5 +-#define CLK_INFRA_AO_UART5 6 +-#define CLK_INFRA_NR_CLK 7 +- +-/* PERICFG */ +- +-#define CLK_PERI_NFI 0 +-#define CLK_PERI_THERM 1 +-#define CLK_PERI_PWM0 2 +-#define CLK_PERI_PWM1 3 +-#define CLK_PERI_PWM2 4 +-#define CLK_PERI_PWM3 5 +-#define CLK_PERI_PWM4 6 +-#define CLK_PERI_PWM5 7 +-#define CLK_PERI_PWM6 8 +-#define CLK_PERI_PWM7 9 +-#define CLK_PERI_PWM 10 +-#define CLK_PERI_AP_DMA 11 +-#define CLK_PERI_MSDC30_0 12 +-#define CLK_PERI_MSDC30_1 13 +-#define CLK_PERI_MSDC30_2 14 +-#define CLK_PERI_MSDC30_3 15 +-#define CLK_PERI_UART0 16 +-#define CLK_PERI_UART1 17 +-#define CLK_PERI_UART2 18 +-#define CLK_PERI_UART3 19 +-#define CLK_PERI_I2C0 20 +-#define CLK_PERI_I2C1 21 +-#define CLK_PERI_I2C2 22 +-#define CLK_PERI_I2C3 23 +-#define CLK_PERI_I2C4 24 +-#define CLK_PERI_AUXADC 25 +-#define CLK_PERI_SPI0 26 +-#define CLK_PERI_SPI 27 +-#define CLK_PERI_I2C5 28 +-#define CLK_PERI_SPI2 29 +-#define CLK_PERI_SPI3 30 +-#define CLK_PERI_SPI5 31 +-#define CLK_PERI_UART4 32 +-#define CLK_PERI_SFLASH 33 +-#define CLK_PERI_GMAC 34 +-#define CLK_PERI_PCIE0 35 +-#define CLK_PERI_PCIE1 36 +-#define CLK_PERI_GMAC_PCLK 37 +-#define CLK_PERI_MSDC50_0_EN 38 +-#define CLK_PERI_MSDC30_1_EN 39 +-#define CLK_PERI_MSDC30_2_EN 40 +-#define CLK_PERI_MSDC30_3_EN 41 +-#define CLK_PERI_MSDC50_0_HCLK_EN 42 +-#define CLK_PERI_MSDC50_3_HCLK_EN 43 +-#define CLK_PERI_MSDC30_0_QTR_EN 44 +-#define CLK_PERI_MSDC30_3_QTR_EN 45 +-#define CLK_PERI_NR_CLK 46 +- +-/* MCUCFG */ +- +-#define CLK_MCU_MP0_SEL 0 +-#define CLK_MCU_MP2_SEL 1 +-#define CLK_MCU_BUS_SEL 2 +-#define CLK_MCU_NR_CLK 3 +- +-/* MFGCFG */ +- +-#define CLK_MFG_BG3D 0 +-#define CLK_MFG_NR_CLK 1 +- +-/* MMSYS */ +- +-#define CLK_MM_SMI_COMMON 0 +-#define CLK_MM_SMI_LARB0 1 +-#define CLK_MM_CAM_MDP 2 +-#define CLK_MM_MDP_RDMA0 3 +-#define CLK_MM_MDP_RDMA1 4 +-#define CLK_MM_MDP_RSZ0 5 +-#define CLK_MM_MDP_RSZ1 6 +-#define CLK_MM_MDP_RSZ2 7 +-#define CLK_MM_MDP_TDSHP0 8 +-#define CLK_MM_MDP_TDSHP1 9 +-#define CLK_MM_MDP_CROP 10 +-#define CLK_MM_MDP_WDMA 11 +-#define CLK_MM_MDP_WROT0 12 +-#define CLK_MM_MDP_WROT1 13 +-#define CLK_MM_FAKE_ENG 14 +-#define CLK_MM_MUTEX_32K 15 +-#define CLK_MM_DISP_OVL0 16 +-#define CLK_MM_DISP_OVL1 17 +-#define CLK_MM_DISP_RDMA0 18 +-#define CLK_MM_DISP_RDMA1 19 +-#define CLK_MM_DISP_RDMA2 20 +-#define CLK_MM_DISP_WDMA0 21 +-#define CLK_MM_DISP_WDMA1 22 +-#define CLK_MM_DISP_COLOR0 23 +-#define CLK_MM_DISP_COLOR1 24 +-#define CLK_MM_DISP_AAL 25 +-#define CLK_MM_DISP_GAMMA 26 +-#define CLK_MM_DISP_UFOE 27 +-#define CLK_MM_DISP_SPLIT0 28 +-#define CLK_MM_DISP_OD 29 +-#define CLK_MM_DISP_PWM0_MM 30 +-#define CLK_MM_DISP_PWM0_26M 31 +-#define CLK_MM_DISP_PWM1_MM 32 +-#define CLK_MM_DISP_PWM1_26M 33 +-#define CLK_MM_DSI0_ENGINE 34 +-#define CLK_MM_DSI0_DIGITAL 35 +-#define CLK_MM_DSI1_ENGINE 36 +-#define CLK_MM_DSI1_DIGITAL 37 +-#define CLK_MM_DPI_PIXEL 38 +-#define CLK_MM_DPI_ENGINE 39 +-#define CLK_MM_DPI1_PIXEL 40 +-#define CLK_MM_DPI1_ENGINE 41 +-#define CLK_MM_LVDS_PIXEL 42 +-#define CLK_MM_LVDS_CTS 43 +-#define CLK_MM_SMI_LARB4 44 +-#define CLK_MM_SMI_COMMON1 45 +-#define CLK_MM_SMI_LARB5 46 +-#define CLK_MM_MDP_RDMA2 47 +-#define CLK_MM_MDP_TDSHP2 48 +-#define CLK_MM_DISP_OVL2 49 +-#define CLK_MM_DISP_WDMA2 50 +-#define CLK_MM_DISP_COLOR2 51 +-#define CLK_MM_DISP_AAL1 52 +-#define CLK_MM_DISP_OD1 53 +-#define CLK_MM_LVDS1_PIXEL 54 +-#define CLK_MM_LVDS1_CTS 55 +-#define CLK_MM_SMI_LARB7 56 +-#define CLK_MM_MDP_RDMA3 57 +-#define CLK_MM_MDP_WROT2 58 +-#define CLK_MM_DSI2 59 +-#define CLK_MM_DSI2_DIGITAL 60 +-#define CLK_MM_DSI3 61 +-#define CLK_MM_DSI3_DIGITAL 62 +-#define CLK_MM_NR_CLK 63 +- +-/* IMGSYS */ +- +-#define CLK_IMG_SMI_LARB2 0 +-#define CLK_IMG_SENINF_SCAM_EN 1 +-#define CLK_IMG_SENINF_CAM_EN 2 +-#define CLK_IMG_CAM_SV_EN 3 +-#define CLK_IMG_CAM_SV1_EN 4 +-#define CLK_IMG_CAM_SV2_EN 5 +-#define CLK_IMG_NR_CLK 6 +- +-/* BDPSYS */ +- +-#define CLK_BDP_BRIDGE_B 0 +-#define CLK_BDP_BRIDGE_DRAM 1 +-#define CLK_BDP_LARB_DRAM 2 +-#define CLK_BDP_WR_CHANNEL_VDI_PXL 3 +-#define CLK_BDP_WR_CHANNEL_VDI_DRAM 4 +-#define CLK_BDP_WR_CHANNEL_VDI_B 5 +-#define CLK_BDP_MT_B 6 +-#define CLK_BDP_DISPFMT_27M 7 +-#define CLK_BDP_DISPFMT_27M_VDOUT 8 +-#define CLK_BDP_DISPFMT_27_74_74 9 +-#define CLK_BDP_DISPFMT_2FS 10 +-#define CLK_BDP_DISPFMT_2FS_2FS74_148 11 +-#define CLK_BDP_DISPFMT_B 12 +-#define CLK_BDP_VDO_DRAM 13 +-#define CLK_BDP_VDO_2FS 14 +-#define CLK_BDP_VDO_B 15 +-#define CLK_BDP_WR_CHANNEL_DI_PXL 16 +-#define CLK_BDP_WR_CHANNEL_DI_DRAM 17 +-#define CLK_BDP_WR_CHANNEL_DI_B 18 +-#define CLK_BDP_NR_AGENT 19 +-#define CLK_BDP_NR_DRAM 20 +-#define CLK_BDP_NR_B 21 +-#define CLK_BDP_BRIDGE_RT_B 22 +-#define CLK_BDP_BRIDGE_RT_DRAM 23 +-#define CLK_BDP_LARB_RT_DRAM 24 +-#define CLK_BDP_TVD_TDC 25 +-#define CLK_BDP_TVD_54 26 +-#define CLK_BDP_TVD_CBUS 27 +-#define CLK_BDP_NR_CLK 28 +- +-/* VDECSYS */ +- +-#define CLK_VDEC_CKEN 0 +-#define CLK_VDEC_LARB1_CKEN 1 +-#define CLK_VDEC_IMGRZ_CKEN 2 +-#define CLK_VDEC_NR_CLK 3 +- +-/* VENCSYS */ +- +-#define CLK_VENC_SMI_COMMON_CON 0 +-#define CLK_VENC_VENC 1 +-#define CLK_VENC_SMI_LARB6 2 +-#define CLK_VENC_NR_CLK 3 +- +-/* JPGDECSYS */ +- +-#define CLK_JPGDEC_JPGDEC1 0 +-#define CLK_JPGDEC_JPGDEC 1 +-#define CLK_JPGDEC_NR_CLK 2 +- +-#endif /* _DT_BINDINGS_CLK_MT2712_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/mt6765-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/mt6765-clk.h +deleted file mode 100644 +index eb97e568518e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/mt6765-clk.h ++++ /dev/null +@@ -1,313 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +- +-#ifndef _DT_BINDINGS_CLK_MT6765_H +-#define _DT_BINDINGS_CLK_MT6765_H +- +-/* FIX Clks */ +-#define CLK_TOP_CLK26M 0 +- +-/* APMIXEDSYS */ +-#define CLK_APMIXED_ARMPLL_L 0 +-#define CLK_APMIXED_ARMPLL 1 +-#define CLK_APMIXED_CCIPLL 2 +-#define CLK_APMIXED_MAINPLL 3 +-#define CLK_APMIXED_MFGPLL 4 +-#define CLK_APMIXED_MMPLL 5 +-#define CLK_APMIXED_UNIV2PLL 6 +-#define CLK_APMIXED_MSDCPLL 7 +-#define CLK_APMIXED_APLL1 8 +-#define CLK_APMIXED_MPLL 9 +-#define CLK_APMIXED_ULPOSC1 10 +-#define CLK_APMIXED_ULPOSC2 11 +-#define CLK_APMIXED_SSUSB26M 12 +-#define CLK_APMIXED_APPLL26M 13 +-#define CLK_APMIXED_MIPIC0_26M 14 +-#define CLK_APMIXED_MDPLLGP26M 15 +-#define CLK_APMIXED_MMSYS_F26M 16 +-#define CLK_APMIXED_UFS26M 17 +-#define CLK_APMIXED_MIPIC1_26M 18 +-#define CLK_APMIXED_MEMPLL26M 19 +-#define CLK_APMIXED_CLKSQ_LVPLL_26M 20 +-#define CLK_APMIXED_MIPID0_26M 21 +-#define CLK_APMIXED_NR_CLK 22 +- +-/* TOPCKGEN */ +-#define CLK_TOP_SYSPLL 0 +-#define CLK_TOP_SYSPLL_D2 1 +-#define CLK_TOP_SYSPLL1_D2 2 +-#define CLK_TOP_SYSPLL1_D4 3 +-#define CLK_TOP_SYSPLL1_D8 4 +-#define CLK_TOP_SYSPLL1_D16 5 +-#define CLK_TOP_SYSPLL_D3 6 +-#define CLK_TOP_SYSPLL2_D2 7 +-#define CLK_TOP_SYSPLL2_D4 8 +-#define CLK_TOP_SYSPLL2_D8 9 +-#define CLK_TOP_SYSPLL_D5 10 +-#define CLK_TOP_SYSPLL3_D2 11 +-#define CLK_TOP_SYSPLL3_D4 12 +-#define CLK_TOP_SYSPLL_D7 13 +-#define CLK_TOP_SYSPLL4_D2 14 +-#define CLK_TOP_SYSPLL4_D4 15 +-#define CLK_TOP_USB20_192M 16 +-#define CLK_TOP_USB20_192M_D4 17 +-#define CLK_TOP_USB20_192M_D8 18 +-#define CLK_TOP_USB20_192M_D16 19 +-#define CLK_TOP_USB20_192M_D32 20 +-#define CLK_TOP_UNIVPLL 21 +-#define CLK_TOP_UNIVPLL_D2 22 +-#define CLK_TOP_UNIVPLL1_D2 23 +-#define CLK_TOP_UNIVPLL1_D4 24 +-#define CLK_TOP_UNIVPLL_D3 25 +-#define CLK_TOP_UNIVPLL2_D2 26 +-#define CLK_TOP_UNIVPLL2_D4 27 +-#define CLK_TOP_UNIVPLL2_D8 28 +-#define CLK_TOP_UNIVPLL2_D32 29 +-#define CLK_TOP_UNIVPLL_D5 30 +-#define CLK_TOP_UNIVPLL3_D2 31 +-#define CLK_TOP_UNIVPLL3_D4 32 +-#define CLK_TOP_MMPLL 33 +-#define CLK_TOP_MMPLL_D2 34 +-#define CLK_TOP_MPLL 35 +-#define CLK_TOP_DA_MPLL_104M_DIV 36 +-#define CLK_TOP_DA_MPLL_52M_DIV 37 +-#define CLK_TOP_MFGPLL 38 +-#define CLK_TOP_MSDCPLL 39 +-#define CLK_TOP_MSDCPLL_D2 40 +-#define CLK_TOP_APLL1 41 +-#define CLK_TOP_APLL1_D2 42 +-#define CLK_TOP_APLL1_D4 43 +-#define CLK_TOP_APLL1_D8 44 +-#define CLK_TOP_ULPOSC1 45 +-#define CLK_TOP_ULPOSC1_D2 46 +-#define CLK_TOP_ULPOSC1_D4 47 +-#define CLK_TOP_ULPOSC1_D8 48 +-#define CLK_TOP_ULPOSC1_D16 49 +-#define CLK_TOP_ULPOSC1_D32 50 +-#define CLK_TOP_DMPLL 51 +-#define CLK_TOP_F_FRTC 52 +-#define CLK_TOP_F_F26M 53 +-#define CLK_TOP_AXI 54 +-#define CLK_TOP_MM 55 +-#define CLK_TOP_SCP 56 +-#define CLK_TOP_MFG 57 +-#define CLK_TOP_F_FUART 58 +-#define CLK_TOP_SPI 59 +-#define CLK_TOP_MSDC50_0 60 +-#define CLK_TOP_MSDC30_1 61 +-#define CLK_TOP_AUDIO 62 +-#define CLK_TOP_AUD_1 63 +-#define CLK_TOP_AUD_ENGEN1 64 +-#define CLK_TOP_F_FDISP_PWM 65 +-#define CLK_TOP_SSPM 66 +-#define CLK_TOP_DXCC 67 +-#define CLK_TOP_I2C 68 +-#define CLK_TOP_F_FPWM 69 +-#define CLK_TOP_F_FSENINF 70 +-#define CLK_TOP_AES_FDE 71 +-#define CLK_TOP_F_BIST2FPC 72 +-#define CLK_TOP_ARMPLL_DIVIDER_PLL0 73 +-#define CLK_TOP_ARMPLL_DIVIDER_PLL1 74 +-#define CLK_TOP_ARMPLL_DIVIDER_PLL2 75 +-#define CLK_TOP_DA_USB20_48M_DIV 76 +-#define CLK_TOP_DA_UNIV_48M_DIV 77 +-#define CLK_TOP_APLL12_DIV0 78 +-#define CLK_TOP_APLL12_DIV1 79 +-#define CLK_TOP_APLL12_DIV2 80 +-#define CLK_TOP_APLL12_DIV3 81 +-#define CLK_TOP_ARMPLL_DIVIDER_PLL0_EN 82 +-#define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN 83 +-#define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN 84 +-#define CLK_TOP_FMEM_OCC_DRC_EN 85 +-#define CLK_TOP_USB20_48M_EN 86 +-#define CLK_TOP_UNIVPLL_48M_EN 87 +-#define CLK_TOP_MPLL_104M_EN 88 +-#define CLK_TOP_MPLL_52M_EN 89 +-#define CLK_TOP_F_UFS_MP_SAP_CFG_EN 90 +-#define CLK_TOP_F_BIST2FPC_EN 91 +-#define CLK_TOP_MD_32K 92 +-#define CLK_TOP_MD_26M 93 +-#define CLK_TOP_MD2_32K 94 +-#define CLK_TOP_MD2_26M 95 +-#define CLK_TOP_AXI_SEL 96 +-#define CLK_TOP_MEM_SEL 97 +-#define CLK_TOP_MM_SEL 98 +-#define CLK_TOP_SCP_SEL 99 +-#define CLK_TOP_MFG_SEL 100 +-#define CLK_TOP_ATB_SEL 101 +-#define CLK_TOP_CAMTG_SEL 102 +-#define CLK_TOP_CAMTG1_SEL 103 +-#define CLK_TOP_CAMTG2_SEL 104 +-#define CLK_TOP_CAMTG3_SEL 105 +-#define CLK_TOP_UART_SEL 106 +-#define CLK_TOP_SPI_SEL 107 +-#define CLK_TOP_MSDC50_0_HCLK_SEL 108 +-#define CLK_TOP_MSDC50_0_SEL 109 +-#define CLK_TOP_MSDC30_1_SEL 110 +-#define CLK_TOP_AUDIO_SEL 111 +-#define CLK_TOP_AUD_INTBUS_SEL 112 +-#define CLK_TOP_AUD_1_SEL 113 +-#define CLK_TOP_AUD_ENGEN1_SEL 114 +-#define CLK_TOP_DISP_PWM_SEL 115 +-#define CLK_TOP_SSPM_SEL 116 +-#define CLK_TOP_DXCC_SEL 117 +-#define CLK_TOP_USB_TOP_SEL 118 +-#define CLK_TOP_SPM_SEL 119 +-#define CLK_TOP_I2C_SEL 120 +-#define CLK_TOP_PWM_SEL 121 +-#define CLK_TOP_SENINF_SEL 122 +-#define CLK_TOP_AES_FDE_SEL 123 +-#define CLK_TOP_PWRAP_ULPOSC_SEL 124 +-#define CLK_TOP_CAMTM_SEL 125 +-#define CLK_TOP_NR_CLK 126 +- +-/* INFRACFG */ +-#define CLK_IFR_ICUSB 0 +-#define CLK_IFR_GCE 1 +-#define CLK_IFR_THERM 2 +-#define CLK_IFR_I2C_AP 3 +-#define CLK_IFR_I2C_CCU 4 +-#define CLK_IFR_I2C_SSPM 5 +-#define CLK_IFR_I2C_RSV 6 +-#define CLK_IFR_PWM_HCLK 7 +-#define CLK_IFR_PWM1 8 +-#define CLK_IFR_PWM2 9 +-#define CLK_IFR_PWM3 10 +-#define CLK_IFR_PWM4 11 +-#define CLK_IFR_PWM5 12 +-#define CLK_IFR_PWM 13 +-#define CLK_IFR_UART0 14 +-#define CLK_IFR_UART1 15 +-#define CLK_IFR_GCE_26M 16 +-#define CLK_IFR_CQ_DMA_FPC 17 +-#define CLK_IFR_BTIF 18 +-#define CLK_IFR_SPI0 19 +-#define CLK_IFR_MSDC0 20 +-#define CLK_IFR_MSDC1 21 +-#define CLK_IFR_TRNG 22 +-#define CLK_IFR_AUXADC 23 +-#define CLK_IFR_CCIF1_AP 24 +-#define CLK_IFR_CCIF1_MD 25 +-#define CLK_IFR_AUXADC_MD 26 +-#define CLK_IFR_AP_DMA 27 +-#define CLK_IFR_DEVICE_APC 28 +-#define CLK_IFR_CCIF_AP 29 +-#define CLK_IFR_AUDIO 30 +-#define CLK_IFR_CCIF_MD 31 +-#define CLK_IFR_RG_PWM_FBCLK6 32 +-#define CLK_IFR_DISP_PWM 33 +-#define CLK_IFR_CLDMA_BCLK 34 +-#define CLK_IFR_AUDIO_26M_BCLK 35 +-#define CLK_IFR_SPI1 36 +-#define CLK_IFR_I2C4 37 +-#define CLK_IFR_SPI2 38 +-#define CLK_IFR_SPI3 39 +-#define CLK_IFR_I2C5 40 +-#define CLK_IFR_I2C5_ARBITER 41 +-#define CLK_IFR_I2C5_IMM 42 +-#define CLK_IFR_I2C1_ARBITER 43 +-#define CLK_IFR_I2C1_IMM 44 +-#define CLK_IFR_I2C2_ARBITER 45 +-#define CLK_IFR_I2C2_IMM 46 +-#define CLK_IFR_SPI4 47 +-#define CLK_IFR_SPI5 48 +-#define CLK_IFR_CQ_DMA 49 +-#define CLK_IFR_FAES_FDE 50 +-#define CLK_IFR_MSDC0_SELF 51 +-#define CLK_IFR_MSDC1_SELF 52 +-#define CLK_IFR_I2C6 53 +-#define CLK_IFR_AP_MSDC0 54 +-#define CLK_IFR_MD_MSDC0 55 +-#define CLK_IFR_MSDC0_SRC 56 +-#define CLK_IFR_MSDC1_SRC 57 +-#define CLK_IFR_AES_TOP0_BCLK 58 +-#define CLK_IFR_MCU_PM_BCLK 59 +-#define CLK_IFR_CCIF2_AP 60 +-#define CLK_IFR_CCIF2_MD 61 +-#define CLK_IFR_CCIF3_AP 62 +-#define CLK_IFR_CCIF3_MD 63 +-#define CLK_IFR_NR_CLK 64 +- +-/* AUDIO */ +-#define CLK_AUDIO_AFE 0 +-#define CLK_AUDIO_22M 1 +-#define CLK_AUDIO_APLL_TUNER 2 +-#define CLK_AUDIO_ADC 3 +-#define CLK_AUDIO_DAC 4 +-#define CLK_AUDIO_DAC_PREDIS 5 +-#define CLK_AUDIO_TML 6 +-#define CLK_AUDIO_I2S1_BCLK 7 +-#define CLK_AUDIO_I2S2_BCLK 8 +-#define CLK_AUDIO_I2S3_BCLK 9 +-#define CLK_AUDIO_I2S4_BCLK 10 +-#define CLK_AUDIO_NR_CLK 11 +- +-/* MIPI_RX_ANA_CSI0A */ +- +-#define CLK_MIPI0A_CSR_CSI_EN_0A 0 +-#define CLK_MIPI0A_NR_CLK 1 +- +-/* MMSYS_CONFIG */ +- +-#define CLK_MM_MDP_RDMA0 0 +-#define CLK_MM_MDP_CCORR0 1 +-#define CLK_MM_MDP_RSZ0 2 +-#define CLK_MM_MDP_RSZ1 3 +-#define CLK_MM_MDP_TDSHP0 4 +-#define CLK_MM_MDP_WROT0 5 +-#define CLK_MM_MDP_WDMA0 6 +-#define CLK_MM_DISP_OVL0 7 +-#define CLK_MM_DISP_OVL0_2L 8 +-#define CLK_MM_DISP_RSZ0 9 +-#define CLK_MM_DISP_RDMA0 10 +-#define CLK_MM_DISP_WDMA0 11 +-#define CLK_MM_DISP_COLOR0 12 +-#define CLK_MM_DISP_CCORR0 13 +-#define CLK_MM_DISP_AAL0 14 +-#define CLK_MM_DISP_GAMMA0 15 +-#define CLK_MM_DISP_DITHER0 16 +-#define CLK_MM_DSI0 17 +-#define CLK_MM_FAKE_ENG 18 +-#define CLK_MM_SMI_COMMON 19 +-#define CLK_MM_SMI_LARB0 20 +-#define CLK_MM_SMI_COMM0 21 +-#define CLK_MM_SMI_COMM1 22 +-#define CLK_MM_CAM_MDP 23 +-#define CLK_MM_SMI_IMG 24 +-#define CLK_MM_SMI_CAM 25 +-#define CLK_MM_IMG_DL_RELAY 26 +-#define CLK_MM_IMG_DL_ASYNC_TOP 27 +-#define CLK_MM_DIG_DSI 28 +-#define CLK_MM_F26M_HRTWT 29 +-#define CLK_MM_NR_CLK 30 +- +-/* IMGSYS */ +- +-#define CLK_IMG_LARB2 0 +-#define CLK_IMG_DIP 1 +-#define CLK_IMG_FDVT 2 +-#define CLK_IMG_DPE 3 +-#define CLK_IMG_RSC 4 +-#define CLK_IMG_NR_CLK 5 +- +-/* VENCSYS */ +- +-#define CLK_VENC_SET0_LARB 0 +-#define CLK_VENC_SET1_VENC 1 +-#define CLK_VENC_SET2_JPGENC 2 +-#define CLK_VENC_SET3_VDEC 3 +-#define CLK_VENC_NR_CLK 4 +- +-/* CAMSYS */ +- +-#define CLK_CAM_LARB3 0 +-#define CLK_CAM_DFP_VAD 1 +-#define CLK_CAM 2 +-#define CLK_CAMTG 3 +-#define CLK_CAM_SENINF 4 +-#define CLK_CAMSV0 5 +-#define CLK_CAMSV1 6 +-#define CLK_CAMSV2 7 +-#define CLK_CAM_CCU 8 +-#define CLK_CAM_NR_CLK 9 +- +-#endif /* _DT_BINDINGS_CLK_MT6765_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/mt6779-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/mt6779-clk.h +deleted file mode 100644 +index b083139afbd2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/mt6779-clk.h ++++ /dev/null +@@ -1,436 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2019 MediaTek Inc. +- * Author: Wendell Lin +- */ +- +-#ifndef _DT_BINDINGS_CLK_MT6779_H +-#define _DT_BINDINGS_CLK_MT6779_H +- +-/* TOPCKGEN */ +-#define CLK_TOP_AXI 1 +-#define CLK_TOP_MM 2 +-#define CLK_TOP_CAM 3 +-#define CLK_TOP_MFG 4 +-#define CLK_TOP_CAMTG 5 +-#define CLK_TOP_UART 6 +-#define CLK_TOP_SPI 7 +-#define CLK_TOP_MSDC50_0_HCLK 8 +-#define CLK_TOP_MSDC50_0 9 +-#define CLK_TOP_MSDC30_1 10 +-#define CLK_TOP_MSDC30_2 11 +-#define CLK_TOP_AUD 12 +-#define CLK_TOP_AUD_INTBUS 13 +-#define CLK_TOP_FPWRAP_ULPOSC 14 +-#define CLK_TOP_SCP 15 +-#define CLK_TOP_ATB 16 +-#define CLK_TOP_SSPM 17 +-#define CLK_TOP_DPI0 18 +-#define CLK_TOP_SCAM 19 +-#define CLK_TOP_AUD_1 20 +-#define CLK_TOP_AUD_2 21 +-#define CLK_TOP_DISP_PWM 22 +-#define CLK_TOP_SSUSB_TOP_XHCI 23 +-#define CLK_TOP_USB_TOP 24 +-#define CLK_TOP_SPM 25 +-#define CLK_TOP_I2C 26 +-#define CLK_TOP_F52M_MFG 27 +-#define CLK_TOP_SENINF 28 +-#define CLK_TOP_DXCC 29 +-#define CLK_TOP_CAMTG2 30 +-#define CLK_TOP_AUD_ENG1 31 +-#define CLK_TOP_AUD_ENG2 32 +-#define CLK_TOP_FAES_UFSFDE 33 +-#define CLK_TOP_FUFS 34 +-#define CLK_TOP_IMG 35 +-#define CLK_TOP_DSP 36 +-#define CLK_TOP_DSP1 37 +-#define CLK_TOP_DSP2 38 +-#define CLK_TOP_IPU_IF 39 +-#define CLK_TOP_CAMTG3 40 +-#define CLK_TOP_CAMTG4 41 +-#define CLK_TOP_PMICSPI 42 +-#define CLK_TOP_MAINPLL_CK 43 +-#define CLK_TOP_MAINPLL_D2 44 +-#define CLK_TOP_MAINPLL_D3 45 +-#define CLK_TOP_MAINPLL_D5 46 +-#define CLK_TOP_MAINPLL_D7 47 +-#define CLK_TOP_MAINPLL_D2_D2 48 +-#define CLK_TOP_MAINPLL_D2_D4 49 +-#define CLK_TOP_MAINPLL_D2_D8 50 +-#define CLK_TOP_MAINPLL_D2_D16 51 +-#define CLK_TOP_MAINPLL_D3_D2 52 +-#define CLK_TOP_MAINPLL_D3_D4 53 +-#define CLK_TOP_MAINPLL_D3_D8 54 +-#define CLK_TOP_MAINPLL_D5_D2 55 +-#define CLK_TOP_MAINPLL_D5_D4 56 +-#define CLK_TOP_MAINPLL_D7_D2 57 +-#define CLK_TOP_MAINPLL_D7_D4 58 +-#define CLK_TOP_UNIVPLL_CK 59 +-#define CLK_TOP_UNIVPLL_D2 60 +-#define CLK_TOP_UNIVPLL_D3 61 +-#define CLK_TOP_UNIVPLL_D5 62 +-#define CLK_TOP_UNIVPLL_D7 63 +-#define CLK_TOP_UNIVPLL_D2_D2 64 +-#define CLK_TOP_UNIVPLL_D2_D4 65 +-#define CLK_TOP_UNIVPLL_D2_D8 66 +-#define CLK_TOP_UNIVPLL_D3_D2 67 +-#define CLK_TOP_UNIVPLL_D3_D4 68 +-#define CLK_TOP_UNIVPLL_D3_D8 69 +-#define CLK_TOP_UNIVPLL_D5_D2 70 +-#define CLK_TOP_UNIVPLL_D5_D4 71 +-#define CLK_TOP_UNIVPLL_D5_D8 72 +-#define CLK_TOP_APLL1_CK 73 +-#define CLK_TOP_APLL1_D2 74 +-#define CLK_TOP_APLL1_D4 75 +-#define CLK_TOP_APLL1_D8 76 +-#define CLK_TOP_APLL2_CK 77 +-#define CLK_TOP_APLL2_D2 78 +-#define CLK_TOP_APLL2_D4 79 +-#define CLK_TOP_APLL2_D8 80 +-#define CLK_TOP_TVDPLL_CK 81 +-#define CLK_TOP_TVDPLL_D2 82 +-#define CLK_TOP_TVDPLL_D4 83 +-#define CLK_TOP_TVDPLL_D8 84 +-#define CLK_TOP_TVDPLL_D16 85 +-#define CLK_TOP_MSDCPLL_CK 86 +-#define CLK_TOP_MSDCPLL_D2 87 +-#define CLK_TOP_MSDCPLL_D4 88 +-#define CLK_TOP_MSDCPLL_D8 89 +-#define CLK_TOP_MSDCPLL_D16 90 +-#define CLK_TOP_AD_OSC_CK 91 +-#define CLK_TOP_OSC_D2 92 +-#define CLK_TOP_OSC_D4 93 +-#define CLK_TOP_OSC_D8 94 +-#define CLK_TOP_OSC_D16 95 +-#define CLK_TOP_F26M_CK_D2 96 +-#define CLK_TOP_MFGPLL_CK 97 +-#define CLK_TOP_UNIVP_192M_CK 98 +-#define CLK_TOP_UNIVP_192M_D2 99 +-#define CLK_TOP_UNIVP_192M_D4 100 +-#define CLK_TOP_UNIVP_192M_D8 101 +-#define CLK_TOP_UNIVP_192M_D16 102 +-#define CLK_TOP_UNIVP_192M_D32 103 +-#define CLK_TOP_MMPLL_CK 104 +-#define CLK_TOP_MMPLL_D4 105 +-#define CLK_TOP_MMPLL_D4_D2 106 +-#define CLK_TOP_MMPLL_D4_D4 107 +-#define CLK_TOP_MMPLL_D5 108 +-#define CLK_TOP_MMPLL_D5_D2 109 +-#define CLK_TOP_MMPLL_D5_D4 110 +-#define CLK_TOP_MMPLL_D6 111 +-#define CLK_TOP_MMPLL_D7 112 +-#define CLK_TOP_CLK26M 113 +-#define CLK_TOP_CLK13M 114 +-#define CLK_TOP_ADSP 115 +-#define CLK_TOP_DPMAIF 116 +-#define CLK_TOP_VENC 117 +-#define CLK_TOP_VDEC 118 +-#define CLK_TOP_CAMTM 119 +-#define CLK_TOP_PWM 120 +-#define CLK_TOP_ADSPPLL_CK 121 +-#define CLK_TOP_I2S0_M_SEL 122 +-#define CLK_TOP_I2S1_M_SEL 123 +-#define CLK_TOP_I2S2_M_SEL 124 +-#define CLK_TOP_I2S3_M_SEL 125 +-#define CLK_TOP_I2S4_M_SEL 126 +-#define CLK_TOP_I2S5_M_SEL 127 +-#define CLK_TOP_APLL12_DIV0 128 +-#define CLK_TOP_APLL12_DIV1 129 +-#define CLK_TOP_APLL12_DIV2 130 +-#define CLK_TOP_APLL12_DIV3 131 +-#define CLK_TOP_APLL12_DIV4 132 +-#define CLK_TOP_APLL12_DIVB 133 +-#define CLK_TOP_APLL12_DIV5 134 +-#define CLK_TOP_IPE 135 +-#define CLK_TOP_DPE 136 +-#define CLK_TOP_CCU 137 +-#define CLK_TOP_DSP3 138 +-#define CLK_TOP_SENINF1 139 +-#define CLK_TOP_SENINF2 140 +-#define CLK_TOP_AUD_H 141 +-#define CLK_TOP_CAMTG5 142 +-#define CLK_TOP_TVDPLL_MAINPLL_D2_CK 143 +-#define CLK_TOP_AD_OSC2_CK 144 +-#define CLK_TOP_OSC2_D2 145 +-#define CLK_TOP_OSC2_D3 146 +-#define CLK_TOP_FMEM_466M_CK 147 +-#define CLK_TOP_ADSPPLL_D4 148 +-#define CLK_TOP_ADSPPLL_D5 149 +-#define CLK_TOP_ADSPPLL_D6 150 +-#define CLK_TOP_OSC_D10 151 +-#define CLK_TOP_UNIVPLL_D3_D16 152 +-#define CLK_TOP_NR_CLK 153 +- +-/* APMIXED */ +-#define CLK_APMIXED_ARMPLL_LL 1 +-#define CLK_APMIXED_ARMPLL_BL 2 +-#define CLK_APMIXED_ARMPLL_BB 3 +-#define CLK_APMIXED_CCIPLL 4 +-#define CLK_APMIXED_MAINPLL 5 +-#define CLK_APMIXED_UNIV2PLL 6 +-#define CLK_APMIXED_MSDCPLL 7 +-#define CLK_APMIXED_ADSPPLL 8 +-#define CLK_APMIXED_MMPLL 9 +-#define CLK_APMIXED_MFGPLL 10 +-#define CLK_APMIXED_TVDPLL 11 +-#define CLK_APMIXED_APLL1 12 +-#define CLK_APMIXED_APLL2 13 +-#define CLK_APMIXED_SSUSB26M 14 +-#define CLK_APMIXED_APPLL26M 15 +-#define CLK_APMIXED_MIPIC0_26M 16 +-#define CLK_APMIXED_MDPLLGP26M 17 +-#define CLK_APMIXED_MM_F26M 18 +-#define CLK_APMIXED_UFS26M 19 +-#define CLK_APMIXED_MIPIC1_26M 20 +-#define CLK_APMIXED_MEMPLL26M 21 +-#define CLK_APMIXED_CLKSQ_LVPLL_26M 22 +-#define CLK_APMIXED_MIPID0_26M 23 +-#define CLK_APMIXED_MIPID1_26M 24 +-#define CLK_APMIXED_NR_CLK 25 +- +-/* CAMSYS */ +-#define CLK_CAM_LARB10 1 +-#define CLK_CAM_DFP_VAD 2 +-#define CLK_CAM_LARB11 3 +-#define CLK_CAM_LARB9 4 +-#define CLK_CAM_CAM 5 +-#define CLK_CAM_CAMTG 6 +-#define CLK_CAM_SENINF 7 +-#define CLK_CAM_CAMSV0 8 +-#define CLK_CAM_CAMSV1 9 +-#define CLK_CAM_CAMSV2 10 +-#define CLK_CAM_CAMSV3 11 +-#define CLK_CAM_CCU 12 +-#define CLK_CAM_FAKE_ENG 13 +-#define CLK_CAM_NR_CLK 14 +- +-/* INFRA */ +-#define CLK_INFRA_PMIC_TMR 1 +-#define CLK_INFRA_PMIC_AP 2 +-#define CLK_INFRA_PMIC_MD 3 +-#define CLK_INFRA_PMIC_CONN 4 +-#define CLK_INFRA_SCPSYS 5 +-#define CLK_INFRA_SEJ 6 +-#define CLK_INFRA_APXGPT 7 +-#define CLK_INFRA_ICUSB 8 +-#define CLK_INFRA_GCE 9 +-#define CLK_INFRA_THERM 10 +-#define CLK_INFRA_I2C0 11 +-#define CLK_INFRA_I2C1 12 +-#define CLK_INFRA_I2C2 13 +-#define CLK_INFRA_I2C3 14 +-#define CLK_INFRA_PWM_HCLK 15 +-#define CLK_INFRA_PWM1 16 +-#define CLK_INFRA_PWM2 17 +-#define CLK_INFRA_PWM3 18 +-#define CLK_INFRA_PWM4 19 +-#define CLK_INFRA_PWM 20 +-#define CLK_INFRA_UART0 21 +-#define CLK_INFRA_UART1 22 +-#define CLK_INFRA_UART2 23 +-#define CLK_INFRA_UART3 24 +-#define CLK_INFRA_GCE_26M 25 +-#define CLK_INFRA_CQ_DMA_FPC 26 +-#define CLK_INFRA_BTIF 27 +-#define CLK_INFRA_SPI0 28 +-#define CLK_INFRA_MSDC0 29 +-#define CLK_INFRA_MSDC1 30 +-#define CLK_INFRA_MSDC2 31 +-#define CLK_INFRA_MSDC0_SCK 32 +-#define CLK_INFRA_DVFSRC 33 +-#define CLK_INFRA_GCPU 34 +-#define CLK_INFRA_TRNG 35 +-#define CLK_INFRA_AUXADC 36 +-#define CLK_INFRA_CPUM 37 +-#define CLK_INFRA_CCIF1_AP 38 +-#define CLK_INFRA_CCIF1_MD 39 +-#define CLK_INFRA_AUXADC_MD 40 +-#define CLK_INFRA_MSDC1_SCK 41 +-#define CLK_INFRA_MSDC2_SCK 42 +-#define CLK_INFRA_AP_DMA 43 +-#define CLK_INFRA_XIU 44 +-#define CLK_INFRA_DEVICE_APC 45 +-#define CLK_INFRA_CCIF_AP 46 +-#define CLK_INFRA_DEBUGSYS 47 +-#define CLK_INFRA_AUD 48 +-#define CLK_INFRA_CCIF_MD 49 +-#define CLK_INFRA_DXCC_SEC_CORE 50 +-#define CLK_INFRA_DXCC_AO 51 +-#define CLK_INFRA_DRAMC_F26M 52 +-#define CLK_INFRA_IRTX 53 +-#define CLK_INFRA_DISP_PWM 54 +-#define CLK_INFRA_DPMAIF_CK 55 +-#define CLK_INFRA_AUD_26M_BCLK 56 +-#define CLK_INFRA_SPI1 57 +-#define CLK_INFRA_I2C4 58 +-#define CLK_INFRA_MODEM_TEMP_SHARE 59 +-#define CLK_INFRA_SPI2 60 +-#define CLK_INFRA_SPI3 61 +-#define CLK_INFRA_UNIPRO_SCK 62 +-#define CLK_INFRA_UNIPRO_TICK 63 +-#define CLK_INFRA_UFS_MP_SAP_BCLK 64 +-#define CLK_INFRA_MD32_BCLK 65 +-#define CLK_INFRA_SSPM 66 +-#define CLK_INFRA_UNIPRO_MBIST 67 +-#define CLK_INFRA_SSPM_BUS_HCLK 68 +-#define CLK_INFRA_I2C5 69 +-#define CLK_INFRA_I2C5_ARBITER 70 +-#define CLK_INFRA_I2C5_IMM 71 +-#define CLK_INFRA_I2C1_ARBITER 72 +-#define CLK_INFRA_I2C1_IMM 73 +-#define CLK_INFRA_I2C2_ARBITER 74 +-#define CLK_INFRA_I2C2_IMM 75 +-#define CLK_INFRA_SPI4 76 +-#define CLK_INFRA_SPI5 77 +-#define CLK_INFRA_CQ_DMA 78 +-#define CLK_INFRA_UFS 79 +-#define CLK_INFRA_AES_UFSFDE 80 +-#define CLK_INFRA_UFS_TICK 81 +-#define CLK_INFRA_MSDC0_SELF 82 +-#define CLK_INFRA_MSDC1_SELF 83 +-#define CLK_INFRA_MSDC2_SELF 84 +-#define CLK_INFRA_SSPM_26M_SELF 85 +-#define CLK_INFRA_SSPM_32K_SELF 86 +-#define CLK_INFRA_UFS_AXI 87 +-#define CLK_INFRA_I2C6 88 +-#define CLK_INFRA_AP_MSDC0 89 +-#define CLK_INFRA_MD_MSDC0 90 +-#define CLK_INFRA_USB 91 +-#define CLK_INFRA_DEVMPU_BCLK 92 +-#define CLK_INFRA_CCIF2_AP 93 +-#define CLK_INFRA_CCIF2_MD 94 +-#define CLK_INFRA_CCIF3_AP 95 +-#define CLK_INFRA_CCIF3_MD 96 +-#define CLK_INFRA_SEJ_F13M 97 +-#define CLK_INFRA_AES_BCLK 98 +-#define CLK_INFRA_I2C7 99 +-#define CLK_INFRA_I2C8 100 +-#define CLK_INFRA_FBIST2FPC 101 +-#define CLK_INFRA_CCIF4_AP 102 +-#define CLK_INFRA_CCIF4_MD 103 +-#define CLK_INFRA_FADSP 104 +-#define CLK_INFRA_SSUSB_XHCI 105 +-#define CLK_INFRA_SPI6 106 +-#define CLK_INFRA_SPI7 107 +-#define CLK_INFRA_NR_CLK 108 +- +-/* MFGCFG */ +-#define CLK_MFGCFG_BG3D 1 +-#define CLK_MFGCFG_NR_CLK 2 +- +-/* IMG */ +-#define CLK_IMG_WPE_A 1 +-#define CLK_IMG_MFB 2 +-#define CLK_IMG_DIP 3 +-#define CLK_IMG_LARB6 4 +-#define CLK_IMG_LARB5 5 +-#define CLK_IMG_NR_CLK 6 +- +-/* IPE */ +-#define CLK_IPE_LARB7 1 +-#define CLK_IPE_LARB8 2 +-#define CLK_IPE_SMI_SUBCOM 3 +-#define CLK_IPE_FD 4 +-#define CLK_IPE_FE 5 +-#define CLK_IPE_RSC 6 +-#define CLK_IPE_DPE 7 +-#define CLK_IPE_NR_CLK 8 +- +-/* MM_CONFIG */ +-#define CLK_MM_SMI_COMMON 1 +-#define CLK_MM_SMI_LARB0 2 +-#define CLK_MM_SMI_LARB1 3 +-#define CLK_MM_GALS_COMM0 4 +-#define CLK_MM_GALS_COMM1 5 +-#define CLK_MM_GALS_CCU2MM 6 +-#define CLK_MM_GALS_IPU12MM 7 +-#define CLK_MM_GALS_IMG2MM 8 +-#define CLK_MM_GALS_CAM2MM 9 +-#define CLK_MM_GALS_IPU2MM 10 +-#define CLK_MM_MDP_DL_TXCK 11 +-#define CLK_MM_IPU_DL_TXCK 12 +-#define CLK_MM_MDP_RDMA0 13 +-#define CLK_MM_MDP_RDMA1 14 +-#define CLK_MM_MDP_RSZ0 15 +-#define CLK_MM_MDP_RSZ1 16 +-#define CLK_MM_MDP_TDSHP 17 +-#define CLK_MM_MDP_WROT0 18 +-#define CLK_MM_FAKE_ENG 19 +-#define CLK_MM_DISP_OVL0 20 +-#define CLK_MM_DISP_OVL0_2L 21 +-#define CLK_MM_DISP_OVL1_2L 22 +-#define CLK_MM_DISP_RDMA0 23 +-#define CLK_MM_DISP_RDMA1 24 +-#define CLK_MM_DISP_WDMA0 25 +-#define CLK_MM_DISP_COLOR0 26 +-#define CLK_MM_DISP_CCORR0 27 +-#define CLK_MM_DISP_AAL0 28 +-#define CLK_MM_DISP_GAMMA0 29 +-#define CLK_MM_DISP_DITHER0 30 +-#define CLK_MM_DISP_SPLIT 31 +-#define CLK_MM_DSI0_MM_CK 32 +-#define CLK_MM_DSI0_IF_CK 33 +-#define CLK_MM_DPI_MM_CK 34 +-#define CLK_MM_DPI_IF_CK 35 +-#define CLK_MM_FAKE_ENG2 36 +-#define CLK_MM_MDP_DL_RX_CK 37 +-#define CLK_MM_IPU_DL_RX_CK 38 +-#define CLK_MM_26M 39 +-#define CLK_MM_MM_R2Y 40 +-#define CLK_MM_DISP_RSZ 41 +-#define CLK_MM_MDP_WDMA0 42 +-#define CLK_MM_MDP_AAL 43 +-#define CLK_MM_MDP_HDR 44 +-#define CLK_MM_DBI_MM_CK 45 +-#define CLK_MM_DBI_IF_CK 46 +-#define CLK_MM_MDP_WROT1 47 +-#define CLK_MM_DISP_POSTMASK0 48 +-#define CLK_MM_DISP_HRT_BW 49 +-#define CLK_MM_DISP_OVL_FBDC 50 +-#define CLK_MM_NR_CLK 51 +- +-/* VDEC_GCON */ +-#define CLK_VDEC_VDEC 1 +-#define CLK_VDEC_LARB1 2 +-#define CLK_VDEC_GCON_NR_CLK 3 +- +-/* VENC_GCON */ +-#define CLK_VENC_GCON_LARB 1 +-#define CLK_VENC_GCON_VENC 2 +-#define CLK_VENC_GCON_JPGENC 3 +-#define CLK_VENC_GCON_GALS 4 +-#define CLK_VENC_GCON_NR_CLK 5 +- +-/* AUD */ +-#define CLK_AUD_AFE 1 +-#define CLK_AUD_22M 2 +-#define CLK_AUD_24M 3 +-#define CLK_AUD_APLL2_TUNER 4 +-#define CLK_AUD_APLL_TUNER 5 +-#define CLK_AUD_TDM 6 +-#define CLK_AUD_ADC 7 +-#define CLK_AUD_DAC 8 +-#define CLK_AUD_DAC_PREDIS 9 +-#define CLK_AUD_TML 10 +-#define CLK_AUD_NLE 11 +-#define CLK_AUD_I2S1_BCLK_SW 12 +-#define CLK_AUD_I2S2_BCLK_SW 13 +-#define CLK_AUD_I2S3_BCLK_SW 14 +-#define CLK_AUD_I2S4_BCLK_SW 15 +-#define CLK_AUD_I2S5_BCLK_SW 16 +-#define CLK_AUD_CONN_I2S_ASRC 17 +-#define CLK_AUD_GENERAL1_ASRC 18 +-#define CLK_AUD_GENERAL2_ASRC 19 +-#define CLK_AUD_DAC_HIRES 20 +-#define CLK_AUD_PDN_ADDA6_ADC 21 +-#define CLK_AUD_ADC_HIRES 22 +-#define CLK_AUD_ADC_HIRES_TML 23 +-#define CLK_AUD_ADDA6_ADC_HIRES 24 +-#define CLK_AUD_3RD_DAC 25 +-#define CLK_AUD_3RD_DAC_PREDIS 26 +-#define CLK_AUD_3RD_DAC_TML 27 +-#define CLK_AUD_3RD_DAC_HIRES 28 +-#define CLK_AUD_NR_CLK 29 +- +-#endif /* _DT_BINDINGS_CLK_MT6779_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/mt6797-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/mt6797-clk.h +deleted file mode 100644 +index dc23ddb754b1..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/mt6797-clk.h ++++ /dev/null +@@ -1,273 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2017 MediaTek Inc. +- * Author: Kevin Chen +- */ +- +-#ifndef _DT_BINDINGS_CLK_MT6797_H +-#define _DT_BINDINGS_CLK_MT6797_H +- +-/* TOPCKGEN */ +-#define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE 1 +-#define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX 2 +-#define CLK_TOP_MUX_AXI 3 +-#define CLK_TOP_MUX_MEM 4 +-#define CLK_TOP_MUX_DDRPHYCFG 5 +-#define CLK_TOP_MUX_MM 6 +-#define CLK_TOP_MUX_PWM 7 +-#define CLK_TOP_MUX_VDEC 8 +-#define CLK_TOP_MUX_VENC 9 +-#define CLK_TOP_MUX_MFG 10 +-#define CLK_TOP_MUX_CAMTG 11 +-#define CLK_TOP_MUX_UART 12 +-#define CLK_TOP_MUX_SPI 13 +-#define CLK_TOP_MUX_ULPOSC_SPI_CK_MUX 14 +-#define CLK_TOP_MUX_USB20 15 +-#define CLK_TOP_MUX_MSDC50_0_HCLK 16 +-#define CLK_TOP_MUX_MSDC50_0 17 +-#define CLK_TOP_MUX_MSDC30_1 18 +-#define CLK_TOP_MUX_MSDC30_2 19 +-#define CLK_TOP_MUX_AUDIO 20 +-#define CLK_TOP_MUX_AUD_INTBUS 21 +-#define CLK_TOP_MUX_PMICSPI 22 +-#define CLK_TOP_MUX_SCP 23 +-#define CLK_TOP_MUX_ATB 24 +-#define CLK_TOP_MUX_MJC 25 +-#define CLK_TOP_MUX_DPI0 26 +-#define CLK_TOP_MUX_AUD_1 27 +-#define CLK_TOP_MUX_AUD_2 28 +-#define CLK_TOP_MUX_SSUSB_TOP_SYS 29 +-#define CLK_TOP_MUX_SPM 30 +-#define CLK_TOP_MUX_BSI_SPI 31 +-#define CLK_TOP_MUX_AUDIO_H 32 +-#define CLK_TOP_MUX_ANC_MD32 33 +-#define CLK_TOP_MUX_MFG_52M 34 +-#define CLK_TOP_SYSPLL_CK 35 +-#define CLK_TOP_SYSPLL_D2 36 +-#define CLK_TOP_SYSPLL1_D2 37 +-#define CLK_TOP_SYSPLL1_D4 38 +-#define CLK_TOP_SYSPLL1_D8 39 +-#define CLK_TOP_SYSPLL1_D16 40 +-#define CLK_TOP_SYSPLL_D3 41 +-#define CLK_TOP_SYSPLL_D3_D3 42 +-#define CLK_TOP_SYSPLL2_D2 43 +-#define CLK_TOP_SYSPLL2_D4 44 +-#define CLK_TOP_SYSPLL2_D8 45 +-#define CLK_TOP_SYSPLL_D5 46 +-#define CLK_TOP_SYSPLL3_D2 47 +-#define CLK_TOP_SYSPLL3_D4 48 +-#define CLK_TOP_SYSPLL_D7 49 +-#define CLK_TOP_SYSPLL4_D2 50 +-#define CLK_TOP_SYSPLL4_D4 51 +-#define CLK_TOP_UNIVPLL_CK 52 +-#define CLK_TOP_UNIVPLL_D7 53 +-#define CLK_TOP_UNIVPLL_D26 54 +-#define CLK_TOP_SSUSB_PHY_48M_CK 55 +-#define CLK_TOP_USB_PHY48M_CK 56 +-#define CLK_TOP_UNIVPLL_D2 57 +-#define CLK_TOP_UNIVPLL1_D2 58 +-#define CLK_TOP_UNIVPLL1_D4 59 +-#define CLK_TOP_UNIVPLL1_D8 60 +-#define CLK_TOP_UNIVPLL_D3 61 +-#define CLK_TOP_UNIVPLL2_D2 62 +-#define CLK_TOP_UNIVPLL2_D4 63 +-#define CLK_TOP_UNIVPLL2_D8 64 +-#define CLK_TOP_UNIVPLL_D5 65 +-#define CLK_TOP_UNIVPLL3_D2 66 +-#define CLK_TOP_UNIVPLL3_D4 67 +-#define CLK_TOP_UNIVPLL3_D8 68 +-#define CLK_TOP_ULPOSC_CK_ORG 69 +-#define CLK_TOP_ULPOSC_CK 70 +-#define CLK_TOP_ULPOSC_D2 71 +-#define CLK_TOP_ULPOSC_D3 72 +-#define CLK_TOP_ULPOSC_D4 73 +-#define CLK_TOP_ULPOSC_D8 74 +-#define CLK_TOP_ULPOSC_D10 75 +-#define CLK_TOP_APLL1_CK 76 +-#define CLK_TOP_APLL2_CK 77 +-#define CLK_TOP_MFGPLL_CK 78 +-#define CLK_TOP_MFGPLL_D2 79 +-#define CLK_TOP_IMGPLL_CK 80 +-#define CLK_TOP_IMGPLL_D2 81 +-#define CLK_TOP_IMGPLL_D4 82 +-#define CLK_TOP_CODECPLL_CK 83 +-#define CLK_TOP_CODECPLL_D2 84 +-#define CLK_TOP_VDECPLL_CK 85 +-#define CLK_TOP_TVDPLL_CK 86 +-#define CLK_TOP_TVDPLL_D2 87 +-#define CLK_TOP_TVDPLL_D4 88 +-#define CLK_TOP_TVDPLL_D8 89 +-#define CLK_TOP_TVDPLL_D16 90 +-#define CLK_TOP_MSDCPLL_CK 91 +-#define CLK_TOP_MSDCPLL_D2 92 +-#define CLK_TOP_MSDCPLL_D4 93 +-#define CLK_TOP_MSDCPLL_D8 94 +-#define CLK_TOP_NR 95 +- +-/* APMIXED_SYS */ +-#define CLK_APMIXED_MAINPLL 1 +-#define CLK_APMIXED_UNIVPLL 2 +-#define CLK_APMIXED_MFGPLL 3 +-#define CLK_APMIXED_MSDCPLL 4 +-#define CLK_APMIXED_IMGPLL 5 +-#define CLK_APMIXED_TVDPLL 6 +-#define CLK_APMIXED_CODECPLL 7 +-#define CLK_APMIXED_VDECPLL 8 +-#define CLK_APMIXED_APLL1 9 +-#define CLK_APMIXED_APLL2 10 +-#define CLK_APMIXED_NR 11 +- +-/* INFRA_SYS */ +-#define CLK_INFRA_PMIC_TMR 1 +-#define CLK_INFRA_PMIC_AP 2 +-#define CLK_INFRA_PMIC_MD 3 +-#define CLK_INFRA_PMIC_CONN 4 +-#define CLK_INFRA_SCP 5 +-#define CLK_INFRA_SEJ 6 +-#define CLK_INFRA_APXGPT 7 +-#define CLK_INFRA_SEJ_13M 8 +-#define CLK_INFRA_ICUSB 9 +-#define CLK_INFRA_GCE 10 +-#define CLK_INFRA_THERM 11 +-#define CLK_INFRA_I2C0 12 +-#define CLK_INFRA_I2C1 13 +-#define CLK_INFRA_I2C2 14 +-#define CLK_INFRA_I2C3 15 +-#define CLK_INFRA_PWM_HCLK 16 +-#define CLK_INFRA_PWM1 17 +-#define CLK_INFRA_PWM2 18 +-#define CLK_INFRA_PWM3 19 +-#define CLK_INFRA_PWM4 20 +-#define CLK_INFRA_PWM 21 +-#define CLK_INFRA_UART0 22 +-#define CLK_INFRA_UART1 23 +-#define CLK_INFRA_UART2 24 +-#define CLK_INFRA_UART3 25 +-#define CLK_INFRA_MD2MD_CCIF_0 26 +-#define CLK_INFRA_MD2MD_CCIF_1 27 +-#define CLK_INFRA_MD2MD_CCIF_2 28 +-#define CLK_INFRA_FHCTL 29 +-#define CLK_INFRA_BTIF 30 +-#define CLK_INFRA_MD2MD_CCIF_3 31 +-#define CLK_INFRA_SPI 32 +-#define CLK_INFRA_MSDC0 33 +-#define CLK_INFRA_MD2MD_CCIF_4 34 +-#define CLK_INFRA_MSDC1 35 +-#define CLK_INFRA_MSDC2 36 +-#define CLK_INFRA_MD2MD_CCIF_5 37 +-#define CLK_INFRA_GCPU 38 +-#define CLK_INFRA_TRNG 39 +-#define CLK_INFRA_AUXADC 40 +-#define CLK_INFRA_CPUM 41 +-#define CLK_INFRA_AP_C2K_CCIF_0 42 +-#define CLK_INFRA_AP_C2K_CCIF_1 43 +-#define CLK_INFRA_CLDMA 44 +-#define CLK_INFRA_DISP_PWM 45 +-#define CLK_INFRA_AP_DMA 46 +-#define CLK_INFRA_DEVICE_APC 47 +-#define CLK_INFRA_L2C_SRAM 48 +-#define CLK_INFRA_CCIF_AP 49 +-#define CLK_INFRA_AUDIO 50 +-#define CLK_INFRA_CCIF_MD 51 +-#define CLK_INFRA_DRAMC_F26M 52 +-#define CLK_INFRA_I2C4 53 +-#define CLK_INFRA_I2C_APPM 54 +-#define CLK_INFRA_I2C_GPUPM 55 +-#define CLK_INFRA_I2C2_IMM 56 +-#define CLK_INFRA_I2C2_ARB 57 +-#define CLK_INFRA_I2C3_IMM 58 +-#define CLK_INFRA_I2C3_ARB 59 +-#define CLK_INFRA_I2C5 60 +-#define CLK_INFRA_SYS_CIRQ 61 +-#define CLK_INFRA_SPI1 62 +-#define CLK_INFRA_DRAMC_B_F26M 63 +-#define CLK_INFRA_ANC_MD32 64 +-#define CLK_INFRA_ANC_MD32_32K 65 +-#define CLK_INFRA_DVFS_SPM1 66 +-#define CLK_INFRA_AES_TOP0 67 +-#define CLK_INFRA_AES_TOP1 68 +-#define CLK_INFRA_SSUSB_BUS 69 +-#define CLK_INFRA_SPI2 70 +-#define CLK_INFRA_SPI3 71 +-#define CLK_INFRA_SPI4 72 +-#define CLK_INFRA_SPI5 73 +-#define CLK_INFRA_IRTX 74 +-#define CLK_INFRA_SSUSB_SYS 75 +-#define CLK_INFRA_SSUSB_REF 76 +-#define CLK_INFRA_AUDIO_26M 77 +-#define CLK_INFRA_AUDIO_26M_PAD_TOP 78 +-#define CLK_INFRA_MODEM_TEMP_SHARE 79 +-#define CLK_INFRA_VAD_WRAP_SOC 80 +-#define CLK_INFRA_DRAMC_CONF 81 +-#define CLK_INFRA_DRAMC_B_CONF 82 +-#define CLK_INFRA_MFG_VCG 83 +-#define CLK_INFRA_13M 84 +-#define CLK_INFRA_NR 85 +- +-/* IMG_SYS */ +-#define CLK_IMG_FDVT 1 +-#define CLK_IMG_DPE 2 +-#define CLK_IMG_DIP 3 +-#define CLK_IMG_LARB6 4 +-#define CLK_IMG_NR 5 +- +-/* MM_SYS */ +-#define CLK_MM_SMI_COMMON 1 +-#define CLK_MM_SMI_LARB0 2 +-#define CLK_MM_SMI_LARB5 3 +-#define CLK_MM_CAM_MDP 4 +-#define CLK_MM_MDP_RDMA0 5 +-#define CLK_MM_MDP_RDMA1 6 +-#define CLK_MM_MDP_RSZ0 7 +-#define CLK_MM_MDP_RSZ1 8 +-#define CLK_MM_MDP_RSZ2 9 +-#define CLK_MM_MDP_TDSHP 10 +-#define CLK_MM_MDP_COLOR 11 +-#define CLK_MM_MDP_WDMA 12 +-#define CLK_MM_MDP_WROT0 13 +-#define CLK_MM_MDP_WROT1 14 +-#define CLK_MM_FAKE_ENG 15 +-#define CLK_MM_DISP_OVL0 16 +-#define CLK_MM_DISP_OVL1 17 +-#define CLK_MM_DISP_OVL0_2L 18 +-#define CLK_MM_DISP_OVL1_2L 19 +-#define CLK_MM_DISP_RDMA0 20 +-#define CLK_MM_DISP_RDMA1 21 +-#define CLK_MM_DISP_WDMA0 22 +-#define CLK_MM_DISP_WDMA1 23 +-#define CLK_MM_DISP_COLOR 24 +-#define CLK_MM_DISP_CCORR 25 +-#define CLK_MM_DISP_AAL 26 +-#define CLK_MM_DISP_GAMMA 27 +-#define CLK_MM_DISP_OD 28 +-#define CLK_MM_DISP_DITHER 29 +-#define CLK_MM_DISP_UFOE 30 +-#define CLK_MM_DISP_DSC 31 +-#define CLK_MM_DISP_SPLIT 32 +-#define CLK_MM_DSI0_MM_CLOCK 33 +-#define CLK_MM_DSI1_MM_CLOCK 34 +-#define CLK_MM_DPI_MM_CLOCK 35 +-#define CLK_MM_DPI_INTERFACE_CLOCK 36 +-#define CLK_MM_LARB4_AXI_ASIF_MM_CLOCK 37 +-#define CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK 38 +-#define CLK_MM_DISP_OVL0_MOUT_CLOCK 39 +-#define CLK_MM_FAKE_ENG2 40 +-#define CLK_MM_DSI0_INTERFACE_CLOCK 41 +-#define CLK_MM_DSI1_INTERFACE_CLOCK 42 +-#define CLK_MM_NR 43 +- +-/* VDEC_SYS */ +-#define CLK_VDEC_CKEN_ENG 1 +-#define CLK_VDEC_ACTIVE 2 +-#define CLK_VDEC_CKEN 3 +-#define CLK_VDEC_LARB1_CKEN 4 +-#define CLK_VDEC_NR 5 +- +-/* VENC_SYS */ +-#define CLK_VENC_0 1 +-#define CLK_VENC_1 2 +-#define CLK_VENC_2 3 +-#define CLK_VENC_3 4 +-#define CLK_VENC_NR 5 +- +-#endif /* _DT_BINDINGS_CLK_MT6797_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/mt7621-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/mt7621-clk.h +deleted file mode 100644 +index 1422badcf9de..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/mt7621-clk.h ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Author: Sergio Paracuellos +- */ +- +-#ifndef _DT_BINDINGS_CLK_MT7621_H +-#define _DT_BINDINGS_CLK_MT7621_H +- +-#define MT7621_CLK_XTAL 0 +-#define MT7621_CLK_CPU 1 +-#define MT7621_CLK_BUS 2 +-#define MT7621_CLK_50M 3 +-#define MT7621_CLK_125M 4 +-#define MT7621_CLK_150M 5 +-#define MT7621_CLK_250M 6 +-#define MT7621_CLK_270M 7 +- +-#define MT7621_CLK_HSDMA 8 +-#define MT7621_CLK_FE 9 +-#define MT7621_CLK_SP_DIVTX 10 +-#define MT7621_CLK_TIMER 11 +-#define MT7621_CLK_PCM 12 +-#define MT7621_CLK_PIO 13 +-#define MT7621_CLK_GDMA 14 +-#define MT7621_CLK_NAND 15 +-#define MT7621_CLK_I2C 16 +-#define MT7621_CLK_I2S 17 +-#define MT7621_CLK_SPI 18 +-#define MT7621_CLK_UART1 19 +-#define MT7621_CLK_UART2 20 +-#define MT7621_CLK_UART3 21 +-#define MT7621_CLK_ETH 22 +-#define MT7621_CLK_PCIE0 23 +-#define MT7621_CLK_PCIE1 24 +-#define MT7621_CLK_PCIE2 25 +-#define MT7621_CLK_CRYPTO 26 +-#define MT7621_CLK_SHXC 27 +- +-#define MT7621_CLK_MAX 28 +- +-#endif /* _DT_BINDINGS_CLK_MT7621_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/mt7622-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/mt7622-clk.h +deleted file mode 100644 +index c12e7eab0788..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/mt7622-clk.h ++++ /dev/null +@@ -1,282 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2017 MediaTek Inc. +- * Author: Chen Zhong +- */ +- +-#ifndef _DT_BINDINGS_CLK_MT7622_H +-#define _DT_BINDINGS_CLK_MT7622_H +- +-/* TOPCKGEN */ +- +-#define CLK_TOP_TO_U2_PHY 0 +-#define CLK_TOP_TO_U2_PHY_1P 1 +-#define CLK_TOP_PCIE0_PIPE_EN 2 +-#define CLK_TOP_PCIE1_PIPE_EN 3 +-#define CLK_TOP_SSUSB_TX250M 4 +-#define CLK_TOP_SSUSB_EQ_RX250M 5 +-#define CLK_TOP_SSUSB_CDR_REF 6 +-#define CLK_TOP_SSUSB_CDR_FB 7 +-#define CLK_TOP_SATA_ASIC 8 +-#define CLK_TOP_SATA_RBC 9 +-#define CLK_TOP_TO_USB3_SYS 10 +-#define CLK_TOP_P1_1MHZ 11 +-#define CLK_TOP_4MHZ 12 +-#define CLK_TOP_P0_1MHZ 13 +-#define CLK_TOP_TXCLK_SRC_PRE 14 +-#define CLK_TOP_RTC 15 +-#define CLK_TOP_MEMPLL 16 +-#define CLK_TOP_DMPLL 17 +-#define CLK_TOP_SYSPLL_D2 18 +-#define CLK_TOP_SYSPLL1_D2 19 +-#define CLK_TOP_SYSPLL1_D4 20 +-#define CLK_TOP_SYSPLL1_D8 21 +-#define CLK_TOP_SYSPLL2_D4 22 +-#define CLK_TOP_SYSPLL2_D8 23 +-#define CLK_TOP_SYSPLL_D5 24 +-#define CLK_TOP_SYSPLL3_D2 25 +-#define CLK_TOP_SYSPLL3_D4 26 +-#define CLK_TOP_SYSPLL4_D2 27 +-#define CLK_TOP_SYSPLL4_D4 28 +-#define CLK_TOP_SYSPLL4_D16 29 +-#define CLK_TOP_UNIVPLL 30 +-#define CLK_TOP_UNIVPLL_D2 31 +-#define CLK_TOP_UNIVPLL1_D2 32 +-#define CLK_TOP_UNIVPLL1_D4 33 +-#define CLK_TOP_UNIVPLL1_D8 34 +-#define CLK_TOP_UNIVPLL1_D16 35 +-#define CLK_TOP_UNIVPLL2_D2 36 +-#define CLK_TOP_UNIVPLL2_D4 37 +-#define CLK_TOP_UNIVPLL2_D8 38 +-#define CLK_TOP_UNIVPLL2_D16 39 +-#define CLK_TOP_UNIVPLL_D5 40 +-#define CLK_TOP_UNIVPLL3_D2 41 +-#define CLK_TOP_UNIVPLL3_D4 42 +-#define CLK_TOP_UNIVPLL3_D16 43 +-#define CLK_TOP_UNIVPLL_D7 44 +-#define CLK_TOP_UNIVPLL_D80_D4 45 +-#define CLK_TOP_UNIV48M 46 +-#define CLK_TOP_SGMIIPLL 47 +-#define CLK_TOP_SGMIIPLL_D2 48 +-#define CLK_TOP_AUD1PLL 49 +-#define CLK_TOP_AUD2PLL 50 +-#define CLK_TOP_AUD_I2S2_MCK 51 +-#define CLK_TOP_TO_USB3_REF 52 +-#define CLK_TOP_PCIE1_MAC_EN 53 +-#define CLK_TOP_PCIE0_MAC_EN 54 +-#define CLK_TOP_ETH_500M 55 +-#define CLK_TOP_AXI_SEL 56 +-#define CLK_TOP_MEM_SEL 57 +-#define CLK_TOP_DDRPHYCFG_SEL 58 +-#define CLK_TOP_ETH_SEL 59 +-#define CLK_TOP_PWM_SEL 60 +-#define CLK_TOP_F10M_REF_SEL 61 +-#define CLK_TOP_NFI_INFRA_SEL 62 +-#define CLK_TOP_FLASH_SEL 63 +-#define CLK_TOP_UART_SEL 64 +-#define CLK_TOP_SPI0_SEL 65 +-#define CLK_TOP_SPI1_SEL 66 +-#define CLK_TOP_MSDC50_0_SEL 67 +-#define CLK_TOP_MSDC30_0_SEL 68 +-#define CLK_TOP_MSDC30_1_SEL 69 +-#define CLK_TOP_A1SYS_HP_SEL 70 +-#define CLK_TOP_A2SYS_HP_SEL 71 +-#define CLK_TOP_INTDIR_SEL 72 +-#define CLK_TOP_AUD_INTBUS_SEL 73 +-#define CLK_TOP_PMICSPI_SEL 74 +-#define CLK_TOP_SCP_SEL 75 +-#define CLK_TOP_ATB_SEL 76 +-#define CLK_TOP_HIF_SEL 77 +-#define CLK_TOP_AUDIO_SEL 78 +-#define CLK_TOP_U2_SEL 79 +-#define CLK_TOP_AUD1_SEL 80 +-#define CLK_TOP_AUD2_SEL 81 +-#define CLK_TOP_IRRX_SEL 82 +-#define CLK_TOP_IRTX_SEL 83 +-#define CLK_TOP_ASM_L_SEL 84 +-#define CLK_TOP_ASM_M_SEL 85 +-#define CLK_TOP_ASM_H_SEL 86 +-#define CLK_TOP_APLL1_SEL 87 +-#define CLK_TOP_APLL2_SEL 88 +-#define CLK_TOP_I2S0_MCK_SEL 89 +-#define CLK_TOP_I2S1_MCK_SEL 90 +-#define CLK_TOP_I2S2_MCK_SEL 91 +-#define CLK_TOP_I2S3_MCK_SEL 92 +-#define CLK_TOP_APLL1_DIV 93 +-#define CLK_TOP_APLL2_DIV 94 +-#define CLK_TOP_I2S0_MCK_DIV 95 +-#define CLK_TOP_I2S1_MCK_DIV 96 +-#define CLK_TOP_I2S2_MCK_DIV 97 +-#define CLK_TOP_I2S3_MCK_DIV 98 +-#define CLK_TOP_A1SYS_HP_DIV 99 +-#define CLK_TOP_A2SYS_HP_DIV 100 +-#define CLK_TOP_APLL1_DIV_PD 101 +-#define CLK_TOP_APLL2_DIV_PD 102 +-#define CLK_TOP_I2S0_MCK_DIV_PD 103 +-#define CLK_TOP_I2S1_MCK_DIV_PD 104 +-#define CLK_TOP_I2S2_MCK_DIV_PD 105 +-#define CLK_TOP_I2S3_MCK_DIV_PD 106 +-#define CLK_TOP_A1SYS_HP_DIV_PD 107 +-#define CLK_TOP_A2SYS_HP_DIV_PD 108 +-#define CLK_TOP_NR_CLK 109 +- +-/* INFRACFG */ +- +-#define CLK_INFRA_MUX1_SEL 0 +-#define CLK_INFRA_DBGCLK_PD 1 +-#define CLK_INFRA_AUDIO_PD 2 +-#define CLK_INFRA_IRRX_PD 3 +-#define CLK_INFRA_APXGPT_PD 4 +-#define CLK_INFRA_PMIC_PD 5 +-#define CLK_INFRA_TRNG 6 +-#define CLK_INFRA_NR_CLK 7 +- +-/* PERICFG */ +- +-#define CLK_PERIBUS_SEL 0 +-#define CLK_PERI_THERM_PD 1 +-#define CLK_PERI_PWM1_PD 2 +-#define CLK_PERI_PWM2_PD 3 +-#define CLK_PERI_PWM3_PD 4 +-#define CLK_PERI_PWM4_PD 5 +-#define CLK_PERI_PWM5_PD 6 +-#define CLK_PERI_PWM6_PD 7 +-#define CLK_PERI_PWM7_PD 8 +-#define CLK_PERI_PWM_PD 9 +-#define CLK_PERI_AP_DMA_PD 10 +-#define CLK_PERI_MSDC30_0_PD 11 +-#define CLK_PERI_MSDC30_1_PD 12 +-#define CLK_PERI_UART0_PD 13 +-#define CLK_PERI_UART1_PD 14 +-#define CLK_PERI_UART2_PD 15 +-#define CLK_PERI_UART3_PD 16 +-#define CLK_PERI_UART4_PD 17 +-#define CLK_PERI_BTIF_PD 18 +-#define CLK_PERI_I2C0_PD 19 +-#define CLK_PERI_I2C1_PD 20 +-#define CLK_PERI_I2C2_PD 21 +-#define CLK_PERI_SPI1_PD 22 +-#define CLK_PERI_AUXADC_PD 23 +-#define CLK_PERI_SPI0_PD 24 +-#define CLK_PERI_SNFI_PD 25 +-#define CLK_PERI_NFI_PD 26 +-#define CLK_PERI_NFIECC_PD 27 +-#define CLK_PERI_FLASH_PD 28 +-#define CLK_PERI_IRTX_PD 29 +-#define CLK_PERI_NR_CLK 30 +- +-/* APMIXEDSYS */ +- +-#define CLK_APMIXED_ARMPLL 0 +-#define CLK_APMIXED_MAINPLL 1 +-#define CLK_APMIXED_UNIV2PLL 2 +-#define CLK_APMIXED_ETH1PLL 3 +-#define CLK_APMIXED_ETH2PLL 4 +-#define CLK_APMIXED_AUD1PLL 5 +-#define CLK_APMIXED_AUD2PLL 6 +-#define CLK_APMIXED_TRGPLL 7 +-#define CLK_APMIXED_SGMIPLL 8 +-#define CLK_APMIXED_MAIN_CORE_EN 9 +-#define CLK_APMIXED_NR_CLK 10 +- +-/* AUDIOSYS */ +- +-#define CLK_AUDIO_AFE 0 +-#define CLK_AUDIO_HDMI 1 +-#define CLK_AUDIO_SPDF 2 +-#define CLK_AUDIO_APLL 3 +-#define CLK_AUDIO_I2SIN1 4 +-#define CLK_AUDIO_I2SIN2 5 +-#define CLK_AUDIO_I2SIN3 6 +-#define CLK_AUDIO_I2SIN4 7 +-#define CLK_AUDIO_I2SO1 8 +-#define CLK_AUDIO_I2SO2 9 +-#define CLK_AUDIO_I2SO3 10 +-#define CLK_AUDIO_I2SO4 11 +-#define CLK_AUDIO_ASRCI1 12 +-#define CLK_AUDIO_ASRCI2 13 +-#define CLK_AUDIO_ASRCO1 14 +-#define CLK_AUDIO_ASRCO2 15 +-#define CLK_AUDIO_INTDIR 16 +-#define CLK_AUDIO_A1SYS 17 +-#define CLK_AUDIO_A2SYS 18 +-#define CLK_AUDIO_UL1 19 +-#define CLK_AUDIO_UL2 20 +-#define CLK_AUDIO_UL3 21 +-#define CLK_AUDIO_UL4 22 +-#define CLK_AUDIO_UL5 23 +-#define CLK_AUDIO_UL6 24 +-#define CLK_AUDIO_DL1 25 +-#define CLK_AUDIO_DL2 26 +-#define CLK_AUDIO_DL3 27 +-#define CLK_AUDIO_DL4 28 +-#define CLK_AUDIO_DL5 29 +-#define CLK_AUDIO_DL6 30 +-#define CLK_AUDIO_DLMCH 31 +-#define CLK_AUDIO_ARB1 32 +-#define CLK_AUDIO_AWB 33 +-#define CLK_AUDIO_AWB2 34 +-#define CLK_AUDIO_DAI 35 +-#define CLK_AUDIO_MOD 36 +-#define CLK_AUDIO_ASRCI3 37 +-#define CLK_AUDIO_ASRCI4 38 +-#define CLK_AUDIO_ASRCO3 39 +-#define CLK_AUDIO_ASRCO4 40 +-#define CLK_AUDIO_MEM_ASRC1 41 +-#define CLK_AUDIO_MEM_ASRC2 42 +-#define CLK_AUDIO_MEM_ASRC3 43 +-#define CLK_AUDIO_MEM_ASRC4 44 +-#define CLK_AUDIO_MEM_ASRC5 45 +-#define CLK_AUDIO_AFE_CONN 46 +-#define CLK_AUDIO_NR_CLK 47 +- +-/* SSUSBSYS */ +- +-#define CLK_SSUSB_U2_PHY_1P_EN 0 +-#define CLK_SSUSB_U2_PHY_EN 1 +-#define CLK_SSUSB_REF_EN 2 +-#define CLK_SSUSB_SYS_EN 3 +-#define CLK_SSUSB_MCU_EN 4 +-#define CLK_SSUSB_DMA_EN 5 +-#define CLK_SSUSB_NR_CLK 6 +- +-/* PCIESYS */ +- +-#define CLK_PCIE_P1_AUX_EN 0 +-#define CLK_PCIE_P1_OBFF_EN 1 +-#define CLK_PCIE_P1_AHB_EN 2 +-#define CLK_PCIE_P1_AXI_EN 3 +-#define CLK_PCIE_P1_MAC_EN 4 +-#define CLK_PCIE_P1_PIPE_EN 5 +-#define CLK_PCIE_P0_AUX_EN 6 +-#define CLK_PCIE_P0_OBFF_EN 7 +-#define CLK_PCIE_P0_AHB_EN 8 +-#define CLK_PCIE_P0_AXI_EN 9 +-#define CLK_PCIE_P0_MAC_EN 10 +-#define CLK_PCIE_P0_PIPE_EN 11 +-#define CLK_SATA_AHB_EN 12 +-#define CLK_SATA_AXI_EN 13 +-#define CLK_SATA_ASIC_EN 14 +-#define CLK_SATA_RBC_EN 15 +-#define CLK_SATA_PM_EN 16 +-#define CLK_PCIE_NR_CLK 17 +- +-/* ETHSYS */ +- +-#define CLK_ETH_HSDMA_EN 0 +-#define CLK_ETH_ESW_EN 1 +-#define CLK_ETH_GP2_EN 2 +-#define CLK_ETH_GP1_EN 3 +-#define CLK_ETH_GP0_EN 4 +-#define CLK_ETH_NR_CLK 5 +- +-/* SGMIISYS */ +- +-#define CLK_SGMII_TX250M_EN 0 +-#define CLK_SGMII_RX250M_EN 1 +-#define CLK_SGMII_CDR_REF 2 +-#define CLK_SGMII_CDR_FB 3 +-#define CLK_SGMII_NR_CLK 4 +- +-#endif /* _DT_BINDINGS_CLK_MT7622_H */ +- +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/mt7629-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/mt7629-clk.h +deleted file mode 100644 +index ad8e6d7f0154..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/mt7629-clk.h ++++ /dev/null +@@ -1,203 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2018 MediaTek Inc. +- */ +- +-#ifndef _DT_BINDINGS_CLK_MT7629_H +-#define _DT_BINDINGS_CLK_MT7629_H +- +-/* TOPCKGEN */ +-#define CLK_TOP_TO_U2_PHY 0 +-#define CLK_TOP_TO_U2_PHY_1P 1 +-#define CLK_TOP_PCIE0_PIPE_EN 2 +-#define CLK_TOP_PCIE1_PIPE_EN 3 +-#define CLK_TOP_SSUSB_TX250M 4 +-#define CLK_TOP_SSUSB_EQ_RX250M 5 +-#define CLK_TOP_SSUSB_CDR_REF 6 +-#define CLK_TOP_SSUSB_CDR_FB 7 +-#define CLK_TOP_SATA_ASIC 8 +-#define CLK_TOP_SATA_RBC 9 +-#define CLK_TOP_TO_USB3_SYS 10 +-#define CLK_TOP_P1_1MHZ 11 +-#define CLK_TOP_4MHZ 12 +-#define CLK_TOP_P0_1MHZ 13 +-#define CLK_TOP_ETH_500M 14 +-#define CLK_TOP_TXCLK_SRC_PRE 15 +-#define CLK_TOP_RTC 16 +-#define CLK_TOP_PWM_QTR_26M 17 +-#define CLK_TOP_CPUM_TCK_IN 18 +-#define CLK_TOP_TO_USB3_DA_TOP 19 +-#define CLK_TOP_MEMPLL 20 +-#define CLK_TOP_DMPLL 21 +-#define CLK_TOP_DMPLL_D4 22 +-#define CLK_TOP_DMPLL_D8 23 +-#define CLK_TOP_SYSPLL_D2 24 +-#define CLK_TOP_SYSPLL1_D2 25 +-#define CLK_TOP_SYSPLL1_D4 26 +-#define CLK_TOP_SYSPLL1_D8 27 +-#define CLK_TOP_SYSPLL1_D16 28 +-#define CLK_TOP_SYSPLL2_D2 29 +-#define CLK_TOP_SYSPLL2_D4 30 +-#define CLK_TOP_SYSPLL2_D8 31 +-#define CLK_TOP_SYSPLL_D5 32 +-#define CLK_TOP_SYSPLL3_D2 33 +-#define CLK_TOP_SYSPLL3_D4 34 +-#define CLK_TOP_SYSPLL_D7 35 +-#define CLK_TOP_SYSPLL4_D2 36 +-#define CLK_TOP_SYSPLL4_D4 37 +-#define CLK_TOP_SYSPLL4_D16 38 +-#define CLK_TOP_UNIVPLL 39 +-#define CLK_TOP_UNIVPLL1_D2 40 +-#define CLK_TOP_UNIVPLL1_D4 41 +-#define CLK_TOP_UNIVPLL1_D8 42 +-#define CLK_TOP_UNIVPLL_D3 43 +-#define CLK_TOP_UNIVPLL2_D2 44 +-#define CLK_TOP_UNIVPLL2_D4 45 +-#define CLK_TOP_UNIVPLL2_D8 46 +-#define CLK_TOP_UNIVPLL2_D16 47 +-#define CLK_TOP_UNIVPLL_D5 48 +-#define CLK_TOP_UNIVPLL3_D2 49 +-#define CLK_TOP_UNIVPLL3_D4 50 +-#define CLK_TOP_UNIVPLL3_D16 51 +-#define CLK_TOP_UNIVPLL_D7 52 +-#define CLK_TOP_UNIVPLL_D80_D4 53 +-#define CLK_TOP_UNIV48M 54 +-#define CLK_TOP_SGMIIPLL_D2 55 +-#define CLK_TOP_CLKXTAL_D4 56 +-#define CLK_TOP_HD_FAXI 57 +-#define CLK_TOP_FAXI 58 +-#define CLK_TOP_F_FAUD_INTBUS 59 +-#define CLK_TOP_AP2WBHIF_HCLK 60 +-#define CLK_TOP_10M_INFRAO 61 +-#define CLK_TOP_MSDC30_1 62 +-#define CLK_TOP_SPI 63 +-#define CLK_TOP_SF 64 +-#define CLK_TOP_FLASH 65 +-#define CLK_TOP_TO_USB3_REF 66 +-#define CLK_TOP_TO_USB3_MCU 67 +-#define CLK_TOP_TO_USB3_DMA 68 +-#define CLK_TOP_FROM_TOP_AHB 69 +-#define CLK_TOP_FROM_TOP_AXI 70 +-#define CLK_TOP_PCIE1_MAC_EN 71 +-#define CLK_TOP_PCIE0_MAC_EN 72 +-#define CLK_TOP_AXI_SEL 73 +-#define CLK_TOP_MEM_SEL 74 +-#define CLK_TOP_DDRPHYCFG_SEL 75 +-#define CLK_TOP_ETH_SEL 76 +-#define CLK_TOP_PWM_SEL 77 +-#define CLK_TOP_F10M_REF_SEL 78 +-#define CLK_TOP_NFI_INFRA_SEL 79 +-#define CLK_TOP_FLASH_SEL 80 +-#define CLK_TOP_UART_SEL 81 +-#define CLK_TOP_SPI0_SEL 82 +-#define CLK_TOP_SPI1_SEL 83 +-#define CLK_TOP_MSDC50_0_SEL 84 +-#define CLK_TOP_MSDC30_0_SEL 85 +-#define CLK_TOP_MSDC30_1_SEL 86 +-#define CLK_TOP_AP2WBMCU_SEL 87 +-#define CLK_TOP_AP2WBHIF_SEL 88 +-#define CLK_TOP_AUDIO_SEL 89 +-#define CLK_TOP_AUD_INTBUS_SEL 90 +-#define CLK_TOP_PMICSPI_SEL 91 +-#define CLK_TOP_SCP_SEL 92 +-#define CLK_TOP_ATB_SEL 93 +-#define CLK_TOP_HIF_SEL 94 +-#define CLK_TOP_SATA_SEL 95 +-#define CLK_TOP_U2_SEL 96 +-#define CLK_TOP_AUD1_SEL 97 +-#define CLK_TOP_AUD2_SEL 98 +-#define CLK_TOP_IRRX_SEL 99 +-#define CLK_TOP_IRTX_SEL 100 +-#define CLK_TOP_SATA_MCU_SEL 101 +-#define CLK_TOP_PCIE0_MCU_SEL 102 +-#define CLK_TOP_PCIE1_MCU_SEL 103 +-#define CLK_TOP_SSUSB_MCU_SEL 104 +-#define CLK_TOP_CRYPTO_SEL 105 +-#define CLK_TOP_SGMII_REF_1_SEL 106 +-#define CLK_TOP_10M_SEL 107 +-#define CLK_TOP_NR_CLK 108 +- +-/* INFRACFG */ +-#define CLK_INFRA_MUX1_SEL 0 +-#define CLK_INFRA_DBGCLK_PD 1 +-#define CLK_INFRA_TRNG_PD 2 +-#define CLK_INFRA_DEVAPC_PD 3 +-#define CLK_INFRA_APXGPT_PD 4 +-#define CLK_INFRA_SEJ_PD 5 +-#define CLK_INFRA_NR_CLK 6 +- +-/* PERICFG */ +-#define CLK_PERIBUS_SEL 0 +-#define CLK_PERI_PWM1_PD 1 +-#define CLK_PERI_PWM2_PD 2 +-#define CLK_PERI_PWM3_PD 3 +-#define CLK_PERI_PWM4_PD 4 +-#define CLK_PERI_PWM5_PD 5 +-#define CLK_PERI_PWM6_PD 6 +-#define CLK_PERI_PWM7_PD 7 +-#define CLK_PERI_PWM_PD 8 +-#define CLK_PERI_AP_DMA_PD 9 +-#define CLK_PERI_MSDC30_1_PD 10 +-#define CLK_PERI_UART0_PD 11 +-#define CLK_PERI_UART1_PD 12 +-#define CLK_PERI_UART2_PD 13 +-#define CLK_PERI_UART3_PD 14 +-#define CLK_PERI_BTIF_PD 15 +-#define CLK_PERI_I2C0_PD 16 +-#define CLK_PERI_SPI0_PD 17 +-#define CLK_PERI_SNFI_PD 18 +-#define CLK_PERI_NFI_PD 19 +-#define CLK_PERI_NFIECC_PD 20 +-#define CLK_PERI_FLASH_PD 21 +-#define CLK_PERI_NR_CLK 22 +- +-/* APMIXEDSYS */ +-#define CLK_APMIXED_ARMPLL 0 +-#define CLK_APMIXED_MAINPLL 1 +-#define CLK_APMIXED_UNIV2PLL 2 +-#define CLK_APMIXED_ETH1PLL 3 +-#define CLK_APMIXED_ETH2PLL 4 +-#define CLK_APMIXED_SGMIPLL 5 +-#define CLK_APMIXED_MAIN_CORE_EN 6 +-#define CLK_APMIXED_NR_CLK 7 +- +-/* SSUSBSYS */ +-#define CLK_SSUSB_U2_PHY_1P_EN 0 +-#define CLK_SSUSB_U2_PHY_EN 1 +-#define CLK_SSUSB_REF_EN 2 +-#define CLK_SSUSB_SYS_EN 3 +-#define CLK_SSUSB_MCU_EN 4 +-#define CLK_SSUSB_DMA_EN 5 +-#define CLK_SSUSB_NR_CLK 6 +- +-/* PCIESYS */ +-#define CLK_PCIE_P1_AUX_EN 0 +-#define CLK_PCIE_P1_OBFF_EN 1 +-#define CLK_PCIE_P1_AHB_EN 2 +-#define CLK_PCIE_P1_AXI_EN 3 +-#define CLK_PCIE_P1_MAC_EN 4 +-#define CLK_PCIE_P1_PIPE_EN 5 +-#define CLK_PCIE_P0_AUX_EN 6 +-#define CLK_PCIE_P0_OBFF_EN 7 +-#define CLK_PCIE_P0_AHB_EN 8 +-#define CLK_PCIE_P0_AXI_EN 9 +-#define CLK_PCIE_P0_MAC_EN 10 +-#define CLK_PCIE_P0_PIPE_EN 11 +-#define CLK_PCIE_NR_CLK 12 +- +-/* ETHSYS */ +-#define CLK_ETH_FE_EN 0 +-#define CLK_ETH_GP2_EN 1 +-#define CLK_ETH_GP1_EN 2 +-#define CLK_ETH_GP0_EN 3 +-#define CLK_ETH_ESW_EN 4 +-#define CLK_ETH_NR_CLK 5 +- +-/* SGMIISYS */ +-#define CLK_SGMII_TX_EN 0 +-#define CLK_SGMII_RX_EN 1 +-#define CLK_SGMII_CDR_REF 2 +-#define CLK_SGMII_CDR_FB 3 +-#define CLK_SGMII_NR_CLK 4 +- +-#endif /* _DT_BINDINGS_CLK_MT7629_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/mt8135-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/mt8135-clk.h +deleted file mode 100644 +index dad8365a4da3..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/mt8135-clk.h ++++ /dev/null +@@ -1,186 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014 MediaTek Inc. +- * Author: James Liao +- */ +- +-#ifndef _DT_BINDINGS_CLK_MT8135_H +-#define _DT_BINDINGS_CLK_MT8135_H +- +-/* TOPCKGEN */ +- +-#define CLK_TOP_DSI0_LNTC_DSICLK 1 +-#define CLK_TOP_HDMITX_CLKDIG_CTS 2 +-#define CLK_TOP_CLKPH_MCK 3 +-#define CLK_TOP_CPUM_TCK_IN 4 +-#define CLK_TOP_MAINPLL_806M 5 +-#define CLK_TOP_MAINPLL_537P3M 6 +-#define CLK_TOP_MAINPLL_322P4M 7 +-#define CLK_TOP_MAINPLL_230P3M 8 +-#define CLK_TOP_UNIVPLL_624M 9 +-#define CLK_TOP_UNIVPLL_416M 10 +-#define CLK_TOP_UNIVPLL_249P6M 11 +-#define CLK_TOP_UNIVPLL_178P3M 12 +-#define CLK_TOP_UNIVPLL_48M 13 +-#define CLK_TOP_MMPLL_D2 14 +-#define CLK_TOP_MMPLL_D3 15 +-#define CLK_TOP_MMPLL_D5 16 +-#define CLK_TOP_MMPLL_D7 17 +-#define CLK_TOP_MMPLL_D4 18 +-#define CLK_TOP_MMPLL_D6 19 +-#define CLK_TOP_SYSPLL_D2 20 +-#define CLK_TOP_SYSPLL_D4 21 +-#define CLK_TOP_SYSPLL_D6 22 +-#define CLK_TOP_SYSPLL_D8 23 +-#define CLK_TOP_SYSPLL_D10 24 +-#define CLK_TOP_SYSPLL_D12 25 +-#define CLK_TOP_SYSPLL_D16 26 +-#define CLK_TOP_SYSPLL_D24 27 +-#define CLK_TOP_SYSPLL_D3 28 +-#define CLK_TOP_SYSPLL_D2P5 29 +-#define CLK_TOP_SYSPLL_D5 30 +-#define CLK_TOP_SYSPLL_D3P5 31 +-#define CLK_TOP_UNIVPLL1_D2 32 +-#define CLK_TOP_UNIVPLL1_D4 33 +-#define CLK_TOP_UNIVPLL1_D6 34 +-#define CLK_TOP_UNIVPLL1_D8 35 +-#define CLK_TOP_UNIVPLL1_D10 36 +-#define CLK_TOP_UNIVPLL2_D2 37 +-#define CLK_TOP_UNIVPLL2_D4 38 +-#define CLK_TOP_UNIVPLL2_D6 39 +-#define CLK_TOP_UNIVPLL2_D8 40 +-#define CLK_TOP_UNIVPLL_D3 41 +-#define CLK_TOP_UNIVPLL_D5 42 +-#define CLK_TOP_UNIVPLL_D7 43 +-#define CLK_TOP_UNIVPLL_D10 44 +-#define CLK_TOP_UNIVPLL_D26 45 +-#define CLK_TOP_APLL 46 +-#define CLK_TOP_APLL_D4 47 +-#define CLK_TOP_APLL_D8 48 +-#define CLK_TOP_APLL_D16 49 +-#define CLK_TOP_APLL_D24 50 +-#define CLK_TOP_LVDSPLL_D2 51 +-#define CLK_TOP_LVDSPLL_D4 52 +-#define CLK_TOP_LVDSPLL_D8 53 +-#define CLK_TOP_LVDSTX_CLKDIG_CT 54 +-#define CLK_TOP_VPLL_DPIX 55 +-#define CLK_TOP_TVHDMI_H 56 +-#define CLK_TOP_HDMITX_CLKDIG_D2 57 +-#define CLK_TOP_HDMITX_CLKDIG_D3 58 +-#define CLK_TOP_TVHDMI_D2 59 +-#define CLK_TOP_TVHDMI_D4 60 +-#define CLK_TOP_MEMPLL_MCK_D4 61 +-#define CLK_TOP_AXI_SEL 62 +-#define CLK_TOP_SMI_SEL 63 +-#define CLK_TOP_MFG_SEL 64 +-#define CLK_TOP_IRDA_SEL 65 +-#define CLK_TOP_CAM_SEL 66 +-#define CLK_TOP_AUD_INTBUS_SEL 67 +-#define CLK_TOP_JPG_SEL 68 +-#define CLK_TOP_DISP_SEL 69 +-#define CLK_TOP_MSDC30_1_SEL 70 +-#define CLK_TOP_MSDC30_2_SEL 71 +-#define CLK_TOP_MSDC30_3_SEL 72 +-#define CLK_TOP_MSDC30_4_SEL 73 +-#define CLK_TOP_USB20_SEL 74 +-#define CLK_TOP_VENC_SEL 75 +-#define CLK_TOP_SPI_SEL 76 +-#define CLK_TOP_UART_SEL 77 +-#define CLK_TOP_MEM_SEL 78 +-#define CLK_TOP_CAMTG_SEL 79 +-#define CLK_TOP_AUDIO_SEL 80 +-#define CLK_TOP_FIX_SEL 81 +-#define CLK_TOP_VDEC_SEL 82 +-#define CLK_TOP_DDRPHYCFG_SEL 83 +-#define CLK_TOP_DPILVDS_SEL 84 +-#define CLK_TOP_PMICSPI_SEL 85 +-#define CLK_TOP_MSDC30_0_SEL 86 +-#define CLK_TOP_SMI_MFG_AS_SEL 87 +-#define CLK_TOP_GCPU_SEL 88 +-#define CLK_TOP_DPI1_SEL 89 +-#define CLK_TOP_CCI_SEL 90 +-#define CLK_TOP_APLL_SEL 91 +-#define CLK_TOP_HDMIPLL_SEL 92 +-#define CLK_TOP_NR_CLK 93 +- +-/* APMIXED_SYS */ +- +-#define CLK_APMIXED_ARMPLL1 1 +-#define CLK_APMIXED_ARMPLL2 2 +-#define CLK_APMIXED_MAINPLL 3 +-#define CLK_APMIXED_UNIVPLL 4 +-#define CLK_APMIXED_MMPLL 5 +-#define CLK_APMIXED_MSDCPLL 6 +-#define CLK_APMIXED_TVDPLL 7 +-#define CLK_APMIXED_LVDSPLL 8 +-#define CLK_APMIXED_AUDPLL 9 +-#define CLK_APMIXED_VDECPLL 10 +-#define CLK_APMIXED_NR_CLK 11 +- +-/* INFRA_SYS */ +- +-#define CLK_INFRA_PMIC_WRAP 1 +-#define CLK_INFRA_PMICSPI 2 +-#define CLK_INFRA_CCIF1_AP_CTRL 3 +-#define CLK_INFRA_CCIF0_AP_CTRL 4 +-#define CLK_INFRA_KP 5 +-#define CLK_INFRA_CPUM 6 +-#define CLK_INFRA_M4U 7 +-#define CLK_INFRA_MFGAXI 8 +-#define CLK_INFRA_DEVAPC 9 +-#define CLK_INFRA_AUDIO 10 +-#define CLK_INFRA_MFG_BUS 11 +-#define CLK_INFRA_SMI 12 +-#define CLK_INFRA_DBGCLK 13 +-#define CLK_INFRA_NR_CLK 14 +- +-/* PERI_SYS */ +- +-#define CLK_PERI_I2C5 1 +-#define CLK_PERI_I2C4 2 +-#define CLK_PERI_I2C3 3 +-#define CLK_PERI_I2C2 4 +-#define CLK_PERI_I2C1 5 +-#define CLK_PERI_I2C0 6 +-#define CLK_PERI_UART3 7 +-#define CLK_PERI_UART2 8 +-#define CLK_PERI_UART1 9 +-#define CLK_PERI_UART0 10 +-#define CLK_PERI_IRDA 11 +-#define CLK_PERI_NLI 12 +-#define CLK_PERI_MD_HIF 13 +-#define CLK_PERI_AP_HIF 14 +-#define CLK_PERI_MSDC30_3 15 +-#define CLK_PERI_MSDC30_2 16 +-#define CLK_PERI_MSDC30_1 17 +-#define CLK_PERI_MSDC20_2 18 +-#define CLK_PERI_MSDC20_1 19 +-#define CLK_PERI_AP_DMA 20 +-#define CLK_PERI_USB1 21 +-#define CLK_PERI_USB0 22 +-#define CLK_PERI_PWM 23 +-#define CLK_PERI_PWM7 24 +-#define CLK_PERI_PWM6 25 +-#define CLK_PERI_PWM5 26 +-#define CLK_PERI_PWM4 27 +-#define CLK_PERI_PWM3 28 +-#define CLK_PERI_PWM2 29 +-#define CLK_PERI_PWM1 30 +-#define CLK_PERI_THERM 31 +-#define CLK_PERI_NFI 32 +-#define CLK_PERI_USBSLV 33 +-#define CLK_PERI_USB1_MCU 34 +-#define CLK_PERI_USB0_MCU 35 +-#define CLK_PERI_GCPU 36 +-#define CLK_PERI_FHCTL 37 +-#define CLK_PERI_SPI1 38 +-#define CLK_PERI_AUXADC 39 +-#define CLK_PERI_PERI_PWRAP 40 +-#define CLK_PERI_I2C6 41 +-#define CLK_PERI_UART0_SEL 42 +-#define CLK_PERI_UART1_SEL 43 +-#define CLK_PERI_UART2_SEL 44 +-#define CLK_PERI_UART3_SEL 45 +-#define CLK_PERI_NR_CLK 46 +- +-#endif /* _DT_BINDINGS_CLK_MT8135_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/mt8167-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/mt8167-clk.h +deleted file mode 100644 +index a96158edd817..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/mt8167-clk.h ++++ /dev/null +@@ -1,131 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2020 MediaTek Inc. +- * Copyright (c) 2020 BayLibre, SAS. +- * Author: James Liao +- * Fabien Parent +- */ +- +-#ifndef _DT_BINDINGS_CLK_MT8167_H +-#define _DT_BINDINGS_CLK_MT8167_H +- +-/* MT8167 is based on MT8516 */ +-#include +- +-/* APMIXEDSYS */ +- +-#define CLK_APMIXED_TVDPLL (CLK_APMIXED_NR_CLK + 0) +-#define CLK_APMIXED_LVDSPLL (CLK_APMIXED_NR_CLK + 1) +-#define CLK_APMIXED_HDMI_REF (CLK_APMIXED_NR_CLK + 2) +-#define MT8167_CLK_APMIXED_NR_CLK (CLK_APMIXED_NR_CLK + 3) +- +-/* TOPCKGEN */ +- +-#define CLK_TOP_DSI0_LNTC_DSICK (CLK_TOP_NR_CLK + 0) +-#define CLK_TOP_VPLL_DPIX (CLK_TOP_NR_CLK + 1) +-#define CLK_TOP_LVDSTX_CLKDIG_CTS (CLK_TOP_NR_CLK + 2) +-#define CLK_TOP_HDMTX_CLKDIG_CTS (CLK_TOP_NR_CLK + 3) +-#define CLK_TOP_LVDSPLL (CLK_TOP_NR_CLK + 4) +-#define CLK_TOP_LVDSPLL_D2 (CLK_TOP_NR_CLK + 5) +-#define CLK_TOP_LVDSPLL_D4 (CLK_TOP_NR_CLK + 6) +-#define CLK_TOP_LVDSPLL_D8 (CLK_TOP_NR_CLK + 7) +-#define CLK_TOP_MIPI_26M (CLK_TOP_NR_CLK + 8) +-#define CLK_TOP_TVDPLL (CLK_TOP_NR_CLK + 9) +-#define CLK_TOP_TVDPLL_D2 (CLK_TOP_NR_CLK + 10) +-#define CLK_TOP_TVDPLL_D4 (CLK_TOP_NR_CLK + 11) +-#define CLK_TOP_TVDPLL_D8 (CLK_TOP_NR_CLK + 12) +-#define CLK_TOP_TVDPLL_D16 (CLK_TOP_NR_CLK + 13) +-#define CLK_TOP_PWM_MM (CLK_TOP_NR_CLK + 14) +-#define CLK_TOP_CAM_MM (CLK_TOP_NR_CLK + 15) +-#define CLK_TOP_MFG_MM (CLK_TOP_NR_CLK + 16) +-#define CLK_TOP_SPM_52M (CLK_TOP_NR_CLK + 17) +-#define CLK_TOP_MIPI_26M_DBG (CLK_TOP_NR_CLK + 18) +-#define CLK_TOP_SCAM_MM (CLK_TOP_NR_CLK + 19) +-#define CLK_TOP_SMI_MM (CLK_TOP_NR_CLK + 20) +-#define CLK_TOP_26M_HDMI_SIFM (CLK_TOP_NR_CLK + 21) +-#define CLK_TOP_26M_CEC (CLK_TOP_NR_CLK + 22) +-#define CLK_TOP_32K_CEC (CLK_TOP_NR_CLK + 23) +-#define CLK_TOP_GCPU_B (CLK_TOP_NR_CLK + 24) +-#define CLK_TOP_RG_VDEC (CLK_TOP_NR_CLK + 25) +-#define CLK_TOP_RG_FDPI0 (CLK_TOP_NR_CLK + 26) +-#define CLK_TOP_RG_FDPI1 (CLK_TOP_NR_CLK + 27) +-#define CLK_TOP_RG_AXI_MFG (CLK_TOP_NR_CLK + 28) +-#define CLK_TOP_RG_SLOW_MFG (CLK_TOP_NR_CLK + 29) +-#define CLK_TOP_GFMUX_EMI1X_SEL (CLK_TOP_NR_CLK + 30) +-#define CLK_TOP_CSW_MUX_MFG_SEL (CLK_TOP_NR_CLK + 31) +-#define CLK_TOP_CAMTG_MM_SEL (CLK_TOP_NR_CLK + 32) +-#define CLK_TOP_PWM_MM_SEL (CLK_TOP_NR_CLK + 33) +-#define CLK_TOP_SPM_52M_SEL (CLK_TOP_NR_CLK + 34) +-#define CLK_TOP_MFG_MM_SEL (CLK_TOP_NR_CLK + 35) +-#define CLK_TOP_SMI_MM_SEL (CLK_TOP_NR_CLK + 36) +-#define CLK_TOP_SCAM_MM_SEL (CLK_TOP_NR_CLK + 37) +-#define CLK_TOP_VDEC_MM_SEL (CLK_TOP_NR_CLK + 38) +-#define CLK_TOP_DPI0_MM_SEL (CLK_TOP_NR_CLK + 39) +-#define CLK_TOP_DPI1_MM_SEL (CLK_TOP_NR_CLK + 40) +-#define CLK_TOP_AXI_MFG_IN_SEL (CLK_TOP_NR_CLK + 41) +-#define CLK_TOP_SLOW_MFG_SEL (CLK_TOP_NR_CLK + 42) +-#define MT8167_CLK_TOP_NR_CLK (CLK_TOP_NR_CLK + 43) +- +-/* MFGCFG */ +- +-#define CLK_MFG_BAXI 0 +-#define CLK_MFG_BMEM 1 +-#define CLK_MFG_BG3D 2 +-#define CLK_MFG_B26M 3 +-#define CLK_MFG_NR_CLK 4 +- +-/* MMSYS */ +- +-#define CLK_MM_SMI_COMMON 0 +-#define CLK_MM_SMI_LARB0 1 +-#define CLK_MM_CAM_MDP 2 +-#define CLK_MM_MDP_RDMA 3 +-#define CLK_MM_MDP_RSZ0 4 +-#define CLK_MM_MDP_RSZ1 5 +-#define CLK_MM_MDP_TDSHP 6 +-#define CLK_MM_MDP_WDMA 7 +-#define CLK_MM_MDP_WROT 8 +-#define CLK_MM_FAKE_ENG 9 +-#define CLK_MM_DISP_OVL0 10 +-#define CLK_MM_DISP_RDMA0 11 +-#define CLK_MM_DISP_RDMA1 12 +-#define CLK_MM_DISP_WDMA 13 +-#define CLK_MM_DISP_COLOR 14 +-#define CLK_MM_DISP_CCORR 15 +-#define CLK_MM_DISP_AAL 16 +-#define CLK_MM_DISP_GAMMA 17 +-#define CLK_MM_DISP_DITHER 18 +-#define CLK_MM_DISP_UFOE 19 +-#define CLK_MM_DISP_PWM_MM 20 +-#define CLK_MM_DISP_PWM_26M 21 +-#define CLK_MM_DSI_ENGINE 22 +-#define CLK_MM_DSI_DIGITAL 23 +-#define CLK_MM_DPI0_ENGINE 24 +-#define CLK_MM_DPI0_PXL 25 +-#define CLK_MM_LVDS_PXL 26 +-#define CLK_MM_LVDS_CTS 27 +-#define CLK_MM_DPI1_ENGINE 28 +-#define CLK_MM_DPI1_PXL 29 +-#define CLK_MM_HDMI_PXL 30 +-#define CLK_MM_HDMI_SPDIF 31 +-#define CLK_MM_HDMI_ADSP_BCK 32 +-#define CLK_MM_HDMI_PLL 33 +-#define CLK_MM_NR_CLK 34 +- +-/* IMGSYS */ +- +-#define CLK_IMG_LARB1_SMI 0 +-#define CLK_IMG_CAM_SMI 1 +-#define CLK_IMG_CAM_CAM 2 +-#define CLK_IMG_SEN_TG 3 +-#define CLK_IMG_SEN_CAM 4 +-#define CLK_IMG_VENC 5 +-#define CLK_IMG_NR_CLK 6 +- +-/* VDECSYS */ +- +-#define CLK_VDEC_CKEN 0 +-#define CLK_VDEC_LARB1_CKEN 1 +-#define CLK_VDEC_NR_CLK 2 +- +-#endif /* _DT_BINDINGS_CLK_MT8167_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/mt8173-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/mt8173-clk.h +deleted file mode 100644 +index 3d00c98b9654..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/mt8173-clk.h ++++ /dev/null +@@ -1,322 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014 MediaTek Inc. +- * Author: James Liao +- */ +- +-#ifndef _DT_BINDINGS_CLK_MT8173_H +-#define _DT_BINDINGS_CLK_MT8173_H +- +-/* TOPCKGEN */ +- +-#define CLK_TOP_CLKPH_MCK_O 1 +-#define CLK_TOP_USB_SYSPLL_125M 3 +-#define CLK_TOP_HDMITX_DIG_CTS 4 +-#define CLK_TOP_ARMCA7PLL_754M 5 +-#define CLK_TOP_ARMCA7PLL_502M 6 +-#define CLK_TOP_MAIN_H546M 7 +-#define CLK_TOP_MAIN_H364M 8 +-#define CLK_TOP_MAIN_H218P4M 9 +-#define CLK_TOP_MAIN_H156M 10 +-#define CLK_TOP_TVDPLL_445P5M 11 +-#define CLK_TOP_TVDPLL_594M 12 +-#define CLK_TOP_UNIV_624M 13 +-#define CLK_TOP_UNIV_416M 14 +-#define CLK_TOP_UNIV_249P6M 15 +-#define CLK_TOP_UNIV_178P3M 16 +-#define CLK_TOP_UNIV_48M 17 +-#define CLK_TOP_CLKRTC_EXT 18 +-#define CLK_TOP_CLKRTC_INT 19 +-#define CLK_TOP_FPC 20 +-#define CLK_TOP_HDMITXPLL_D2 21 +-#define CLK_TOP_HDMITXPLL_D3 22 +-#define CLK_TOP_ARMCA7PLL_D2 23 +-#define CLK_TOP_ARMCA7PLL_D3 24 +-#define CLK_TOP_APLL1 25 +-#define CLK_TOP_APLL2 26 +-#define CLK_TOP_DMPLL 27 +-#define CLK_TOP_DMPLL_D2 28 +-#define CLK_TOP_DMPLL_D4 29 +-#define CLK_TOP_DMPLL_D8 30 +-#define CLK_TOP_DMPLL_D16 31 +-#define CLK_TOP_LVDSPLL_D2 32 +-#define CLK_TOP_LVDSPLL_D4 33 +-#define CLK_TOP_LVDSPLL_D8 34 +-#define CLK_TOP_MMPLL 35 +-#define CLK_TOP_MMPLL_D2 36 +-#define CLK_TOP_MSDCPLL 37 +-#define CLK_TOP_MSDCPLL_D2 38 +-#define CLK_TOP_MSDCPLL_D4 39 +-#define CLK_TOP_MSDCPLL2 40 +-#define CLK_TOP_MSDCPLL2_D2 41 +-#define CLK_TOP_MSDCPLL2_D4 42 +-#define CLK_TOP_SYSPLL_D2 43 +-#define CLK_TOP_SYSPLL1_D2 44 +-#define CLK_TOP_SYSPLL1_D4 45 +-#define CLK_TOP_SYSPLL1_D8 46 +-#define CLK_TOP_SYSPLL1_D16 47 +-#define CLK_TOP_SYSPLL_D3 48 +-#define CLK_TOP_SYSPLL2_D2 49 +-#define CLK_TOP_SYSPLL2_D4 50 +-#define CLK_TOP_SYSPLL_D5 51 +-#define CLK_TOP_SYSPLL3_D2 52 +-#define CLK_TOP_SYSPLL3_D4 53 +-#define CLK_TOP_SYSPLL_D7 54 +-#define CLK_TOP_SYSPLL4_D2 55 +-#define CLK_TOP_SYSPLL4_D4 56 +-#define CLK_TOP_TVDPLL 57 +-#define CLK_TOP_TVDPLL_D2 58 +-#define CLK_TOP_TVDPLL_D4 59 +-#define CLK_TOP_TVDPLL_D8 60 +-#define CLK_TOP_TVDPLL_D16 61 +-#define CLK_TOP_UNIVPLL_D2 62 +-#define CLK_TOP_UNIVPLL1_D2 63 +-#define CLK_TOP_UNIVPLL1_D4 64 +-#define CLK_TOP_UNIVPLL1_D8 65 +-#define CLK_TOP_UNIVPLL_D3 66 +-#define CLK_TOP_UNIVPLL2_D2 67 +-#define CLK_TOP_UNIVPLL2_D4 68 +-#define CLK_TOP_UNIVPLL2_D8 69 +-#define CLK_TOP_UNIVPLL_D5 70 +-#define CLK_TOP_UNIVPLL3_D2 71 +-#define CLK_TOP_UNIVPLL3_D4 72 +-#define CLK_TOP_UNIVPLL3_D8 73 +-#define CLK_TOP_UNIVPLL_D7 74 +-#define CLK_TOP_UNIVPLL_D26 75 +-#define CLK_TOP_UNIVPLL_D52 76 +-#define CLK_TOP_VCODECPLL 77 +-#define CLK_TOP_VCODECPLL_370P5 78 +-#define CLK_TOP_VENCPLL 79 +-#define CLK_TOP_VENCPLL_D2 80 +-#define CLK_TOP_VENCPLL_D4 81 +-#define CLK_TOP_AXI_SEL 82 +-#define CLK_TOP_MEM_SEL 83 +-#define CLK_TOP_DDRPHYCFG_SEL 84 +-#define CLK_TOP_MM_SEL 85 +-#define CLK_TOP_PWM_SEL 86 +-#define CLK_TOP_VDEC_SEL 87 +-#define CLK_TOP_VENC_SEL 88 +-#define CLK_TOP_MFG_SEL 89 +-#define CLK_TOP_CAMTG_SEL 90 +-#define CLK_TOP_UART_SEL 91 +-#define CLK_TOP_SPI_SEL 92 +-#define CLK_TOP_USB20_SEL 93 +-#define CLK_TOP_USB30_SEL 94 +-#define CLK_TOP_MSDC50_0_H_SEL 95 +-#define CLK_TOP_MSDC50_0_SEL 96 +-#define CLK_TOP_MSDC30_1_SEL 97 +-#define CLK_TOP_MSDC30_2_SEL 98 +-#define CLK_TOP_MSDC30_3_SEL 99 +-#define CLK_TOP_AUDIO_SEL 100 +-#define CLK_TOP_AUD_INTBUS_SEL 101 +-#define CLK_TOP_PMICSPI_SEL 102 +-#define CLK_TOP_SCP_SEL 103 +-#define CLK_TOP_ATB_SEL 104 +-#define CLK_TOP_VENC_LT_SEL 105 +-#define CLK_TOP_DPI0_SEL 106 +-#define CLK_TOP_IRDA_SEL 107 +-#define CLK_TOP_CCI400_SEL 108 +-#define CLK_TOP_AUD_1_SEL 109 +-#define CLK_TOP_AUD_2_SEL 110 +-#define CLK_TOP_MEM_MFG_IN_SEL 111 +-#define CLK_TOP_AXI_MFG_IN_SEL 112 +-#define CLK_TOP_SCAM_SEL 113 +-#define CLK_TOP_SPINFI_IFR_SEL 114 +-#define CLK_TOP_HDMI_SEL 115 +-#define CLK_TOP_DPILVDS_SEL 116 +-#define CLK_TOP_MSDC50_2_H_SEL 117 +-#define CLK_TOP_HDCP_SEL 118 +-#define CLK_TOP_HDCP_24M_SEL 119 +-#define CLK_TOP_RTC_SEL 120 +-#define CLK_TOP_APLL1_DIV0 121 +-#define CLK_TOP_APLL1_DIV1 122 +-#define CLK_TOP_APLL1_DIV2 123 +-#define CLK_TOP_APLL1_DIV3 124 +-#define CLK_TOP_APLL1_DIV4 125 +-#define CLK_TOP_APLL1_DIV5 126 +-#define CLK_TOP_APLL2_DIV0 127 +-#define CLK_TOP_APLL2_DIV1 128 +-#define CLK_TOP_APLL2_DIV2 129 +-#define CLK_TOP_APLL2_DIV3 130 +-#define CLK_TOP_APLL2_DIV4 131 +-#define CLK_TOP_APLL2_DIV5 132 +-#define CLK_TOP_I2S0_M_SEL 133 +-#define CLK_TOP_I2S1_M_SEL 134 +-#define CLK_TOP_I2S2_M_SEL 135 +-#define CLK_TOP_I2S3_M_SEL 136 +-#define CLK_TOP_I2S3_B_SEL 137 +-#define CLK_TOP_DSI0_DIG 138 +-#define CLK_TOP_DSI1_DIG 139 +-#define CLK_TOP_LVDS_PXL 140 +-#define CLK_TOP_LVDS_CTS 141 +-#define CLK_TOP_NR_CLK 142 +- +-/* APMIXED_SYS */ +- +-#define CLK_APMIXED_ARMCA15PLL 1 +-#define CLK_APMIXED_ARMCA7PLL 2 +-#define CLK_APMIXED_MAINPLL 3 +-#define CLK_APMIXED_UNIVPLL 4 +-#define CLK_APMIXED_MMPLL 5 +-#define CLK_APMIXED_MSDCPLL 6 +-#define CLK_APMIXED_VENCPLL 7 +-#define CLK_APMIXED_TVDPLL 8 +-#define CLK_APMIXED_MPLL 9 +-#define CLK_APMIXED_VCODECPLL 10 +-#define CLK_APMIXED_APLL1 11 +-#define CLK_APMIXED_APLL2 12 +-#define CLK_APMIXED_LVDSPLL 13 +-#define CLK_APMIXED_MSDCPLL2 14 +-#define CLK_APMIXED_REF2USB_TX 15 +-#define CLK_APMIXED_HDMI_REF 16 +-#define CLK_APMIXED_NR_CLK 17 +- +-/* INFRA_SYS */ +- +-#define CLK_INFRA_DBGCLK 1 +-#define CLK_INFRA_SMI 2 +-#define CLK_INFRA_AUDIO 3 +-#define CLK_INFRA_GCE 4 +-#define CLK_INFRA_L2C_SRAM 5 +-#define CLK_INFRA_M4U 6 +-#define CLK_INFRA_CPUM 7 +-#define CLK_INFRA_KP 8 +-#define CLK_INFRA_CEC 9 +-#define CLK_INFRA_PMICSPI 10 +-#define CLK_INFRA_PMICWRAP 11 +-#define CLK_INFRA_CLK_13M 12 +-#define CLK_INFRA_CA53SEL 13 +-#define CLK_INFRA_CA72SEL 14 +-#define CLK_INFRA_NR_CLK 15 +- +-/* PERI_SYS */ +- +-#define CLK_PERI_NFI 1 +-#define CLK_PERI_THERM 2 +-#define CLK_PERI_PWM1 3 +-#define CLK_PERI_PWM2 4 +-#define CLK_PERI_PWM3 5 +-#define CLK_PERI_PWM4 6 +-#define CLK_PERI_PWM5 7 +-#define CLK_PERI_PWM6 8 +-#define CLK_PERI_PWM7 9 +-#define CLK_PERI_PWM 10 +-#define CLK_PERI_USB0 11 +-#define CLK_PERI_USB1 12 +-#define CLK_PERI_AP_DMA 13 +-#define CLK_PERI_MSDC30_0 14 +-#define CLK_PERI_MSDC30_1 15 +-#define CLK_PERI_MSDC30_2 16 +-#define CLK_PERI_MSDC30_3 17 +-#define CLK_PERI_NLI_ARB 18 +-#define CLK_PERI_IRDA 19 +-#define CLK_PERI_UART0 20 +-#define CLK_PERI_UART1 21 +-#define CLK_PERI_UART2 22 +-#define CLK_PERI_UART3 23 +-#define CLK_PERI_I2C0 24 +-#define CLK_PERI_I2C1 25 +-#define CLK_PERI_I2C2 26 +-#define CLK_PERI_I2C3 27 +-#define CLK_PERI_I2C4 28 +-#define CLK_PERI_AUXADC 29 +-#define CLK_PERI_SPI0 30 +-#define CLK_PERI_I2C5 31 +-#define CLK_PERI_NFIECC 32 +-#define CLK_PERI_SPI 33 +-#define CLK_PERI_IRRX 34 +-#define CLK_PERI_I2C6 35 +-#define CLK_PERI_UART0_SEL 36 +-#define CLK_PERI_UART1_SEL 37 +-#define CLK_PERI_UART2_SEL 38 +-#define CLK_PERI_UART3_SEL 39 +-#define CLK_PERI_NR_CLK 40 +- +-/* IMG_SYS */ +- +-#define CLK_IMG_LARB2_SMI 1 +-#define CLK_IMG_CAM_SMI 2 +-#define CLK_IMG_CAM_CAM 3 +-#define CLK_IMG_SEN_TG 4 +-#define CLK_IMG_SEN_CAM 5 +-#define CLK_IMG_CAM_SV 6 +-#define CLK_IMG_FD 7 +-#define CLK_IMG_NR_CLK 8 +- +-/* MM_SYS */ +- +-#define CLK_MM_SMI_COMMON 1 +-#define CLK_MM_SMI_LARB0 2 +-#define CLK_MM_CAM_MDP 3 +-#define CLK_MM_MDP_RDMA0 4 +-#define CLK_MM_MDP_RDMA1 5 +-#define CLK_MM_MDP_RSZ0 6 +-#define CLK_MM_MDP_RSZ1 7 +-#define CLK_MM_MDP_RSZ2 8 +-#define CLK_MM_MDP_TDSHP0 9 +-#define CLK_MM_MDP_TDSHP1 10 +-#define CLK_MM_MDP_WDMA 11 +-#define CLK_MM_MDP_WROT0 12 +-#define CLK_MM_MDP_WROT1 13 +-#define CLK_MM_FAKE_ENG 14 +-#define CLK_MM_MUTEX_32K 15 +-#define CLK_MM_DISP_OVL0 16 +-#define CLK_MM_DISP_OVL1 17 +-#define CLK_MM_DISP_RDMA0 18 +-#define CLK_MM_DISP_RDMA1 19 +-#define CLK_MM_DISP_RDMA2 20 +-#define CLK_MM_DISP_WDMA0 21 +-#define CLK_MM_DISP_WDMA1 22 +-#define CLK_MM_DISP_COLOR0 23 +-#define CLK_MM_DISP_COLOR1 24 +-#define CLK_MM_DISP_AAL 25 +-#define CLK_MM_DISP_GAMMA 26 +-#define CLK_MM_DISP_UFOE 27 +-#define CLK_MM_DISP_SPLIT0 28 +-#define CLK_MM_DISP_SPLIT1 29 +-#define CLK_MM_DISP_MERGE 30 +-#define CLK_MM_DISP_OD 31 +-#define CLK_MM_DISP_PWM0MM 32 +-#define CLK_MM_DISP_PWM026M 33 +-#define CLK_MM_DISP_PWM1MM 34 +-#define CLK_MM_DISP_PWM126M 35 +-#define CLK_MM_DSI0_ENGINE 36 +-#define CLK_MM_DSI0_DIGITAL 37 +-#define CLK_MM_DSI1_ENGINE 38 +-#define CLK_MM_DSI1_DIGITAL 39 +-#define CLK_MM_DPI_PIXEL 40 +-#define CLK_MM_DPI_ENGINE 41 +-#define CLK_MM_DPI1_PIXEL 42 +-#define CLK_MM_DPI1_ENGINE 43 +-#define CLK_MM_HDMI_PIXEL 44 +-#define CLK_MM_HDMI_PLLCK 45 +-#define CLK_MM_HDMI_AUDIO 46 +-#define CLK_MM_HDMI_SPDIF 47 +-#define CLK_MM_LVDS_PIXEL 48 +-#define CLK_MM_LVDS_CTS 49 +-#define CLK_MM_SMI_LARB4 50 +-#define CLK_MM_HDMI_HDCP 51 +-#define CLK_MM_HDMI_HDCP24M 52 +-#define CLK_MM_NR_CLK 53 +- +-/* VDEC_SYS */ +- +-#define CLK_VDEC_CKEN 1 +-#define CLK_VDEC_LARB_CKEN 2 +-#define CLK_VDEC_NR_CLK 3 +- +-/* VENC_SYS */ +- +-#define CLK_VENC_CKE0 1 +-#define CLK_VENC_CKE1 2 +-#define CLK_VENC_CKE2 3 +-#define CLK_VENC_CKE3 4 +-#define CLK_VENC_NR_CLK 5 +- +-/* VENCLT_SYS */ +- +-#define CLK_VENCLT_CKE0 1 +-#define CLK_VENCLT_CKE1 2 +-#define CLK_VENCLT_NR_CLK 3 +- +-#endif /* _DT_BINDINGS_CLK_MT8173_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/mt8183-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/mt8183-clk.h +deleted file mode 100644 +index a7b470b0ec8a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/mt8183-clk.h ++++ /dev/null +@@ -1,426 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2018 MediaTek Inc. +- * Author: Weiyi Lu +- */ +- +-#ifndef _DT_BINDINGS_CLK_MT8183_H +-#define _DT_BINDINGS_CLK_MT8183_H +- +-/* APMIXED */ +-#define CLK_APMIXED_ARMPLL_LL 0 +-#define CLK_APMIXED_ARMPLL_L 1 +-#define CLK_APMIXED_CCIPLL 2 +-#define CLK_APMIXED_MAINPLL 3 +-#define CLK_APMIXED_UNIV2PLL 4 +-#define CLK_APMIXED_MSDCPLL 5 +-#define CLK_APMIXED_MMPLL 6 +-#define CLK_APMIXED_MFGPLL 7 +-#define CLK_APMIXED_TVDPLL 8 +-#define CLK_APMIXED_APLL1 9 +-#define CLK_APMIXED_APLL2 10 +-#define CLK_APMIXED_SSUSB_26M 11 +-#define CLK_APMIXED_APPLL_26M 12 +-#define CLK_APMIXED_MIPIC0_26M 13 +-#define CLK_APMIXED_MDPLLGP_26M 14 +-#define CLK_APMIXED_MMSYS_26M 15 +-#define CLK_APMIXED_UFS_26M 16 +-#define CLK_APMIXED_MIPIC1_26M 17 +-#define CLK_APMIXED_MEMPLL_26M 18 +-#define CLK_APMIXED_CLKSQ_LVPLL_26M 19 +-#define CLK_APMIXED_MIPID0_26M 20 +-#define CLK_APMIXED_MIPID1_26M 21 +-#define CLK_APMIXED_NR_CLK 22 +- +-/* TOPCKGEN */ +-#define CLK_TOP_MUX_AXI 0 +-#define CLK_TOP_MUX_MM 1 +-#define CLK_TOP_MUX_CAM 2 +-#define CLK_TOP_MUX_MFG 3 +-#define CLK_TOP_MUX_CAMTG 4 +-#define CLK_TOP_MUX_UART 5 +-#define CLK_TOP_MUX_SPI 6 +-#define CLK_TOP_MUX_MSDC50_0_HCLK 7 +-#define CLK_TOP_MUX_MSDC50_0 8 +-#define CLK_TOP_MUX_MSDC30_1 9 +-#define CLK_TOP_MUX_MSDC30_2 10 +-#define CLK_TOP_MUX_AUDIO 11 +-#define CLK_TOP_MUX_AUD_INTBUS 12 +-#define CLK_TOP_MUX_FPWRAP_ULPOSC 13 +-#define CLK_TOP_MUX_SCP 14 +-#define CLK_TOP_MUX_ATB 15 +-#define CLK_TOP_MUX_SSPM 16 +-#define CLK_TOP_MUX_DPI0 17 +-#define CLK_TOP_MUX_SCAM 18 +-#define CLK_TOP_MUX_AUD_1 19 +-#define CLK_TOP_MUX_AUD_2 20 +-#define CLK_TOP_MUX_DISP_PWM 21 +-#define CLK_TOP_MUX_SSUSB_TOP_XHCI 22 +-#define CLK_TOP_MUX_USB_TOP 23 +-#define CLK_TOP_MUX_SPM 24 +-#define CLK_TOP_MUX_I2C 25 +-#define CLK_TOP_MUX_F52M_MFG 26 +-#define CLK_TOP_MUX_SENINF 27 +-#define CLK_TOP_MUX_DXCC 28 +-#define CLK_TOP_MUX_CAMTG2 29 +-#define CLK_TOP_MUX_AUD_ENG1 30 +-#define CLK_TOP_MUX_AUD_ENG2 31 +-#define CLK_TOP_MUX_FAES_UFSFDE 32 +-#define CLK_TOP_MUX_FUFS 33 +-#define CLK_TOP_MUX_IMG 34 +-#define CLK_TOP_MUX_DSP 35 +-#define CLK_TOP_MUX_DSP1 36 +-#define CLK_TOP_MUX_DSP2 37 +-#define CLK_TOP_MUX_IPU_IF 38 +-#define CLK_TOP_MUX_CAMTG3 39 +-#define CLK_TOP_MUX_CAMTG4 40 +-#define CLK_TOP_MUX_PMICSPI 41 +-#define CLK_TOP_SYSPLL_CK 42 +-#define CLK_TOP_SYSPLL_D2 43 +-#define CLK_TOP_SYSPLL_D3 44 +-#define CLK_TOP_SYSPLL_D5 45 +-#define CLK_TOP_SYSPLL_D7 46 +-#define CLK_TOP_SYSPLL_D2_D2 47 +-#define CLK_TOP_SYSPLL_D2_D4 48 +-#define CLK_TOP_SYSPLL_D2_D8 49 +-#define CLK_TOP_SYSPLL_D2_D16 50 +-#define CLK_TOP_SYSPLL_D3_D2 51 +-#define CLK_TOP_SYSPLL_D3_D4 52 +-#define CLK_TOP_SYSPLL_D3_D8 53 +-#define CLK_TOP_SYSPLL_D5_D2 54 +-#define CLK_TOP_SYSPLL_D5_D4 55 +-#define CLK_TOP_SYSPLL_D7_D2 56 +-#define CLK_TOP_SYSPLL_D7_D4 57 +-#define CLK_TOP_UNIVPLL_CK 58 +-#define CLK_TOP_UNIVPLL_D2 59 +-#define CLK_TOP_UNIVPLL_D3 60 +-#define CLK_TOP_UNIVPLL_D5 61 +-#define CLK_TOP_UNIVPLL_D7 62 +-#define CLK_TOP_UNIVPLL_D2_D2 63 +-#define CLK_TOP_UNIVPLL_D2_D4 64 +-#define CLK_TOP_UNIVPLL_D2_D8 65 +-#define CLK_TOP_UNIVPLL_D3_D2 66 +-#define CLK_TOP_UNIVPLL_D3_D4 67 +-#define CLK_TOP_UNIVPLL_D3_D8 68 +-#define CLK_TOP_UNIVPLL_D5_D2 69 +-#define CLK_TOP_UNIVPLL_D5_D4 70 +-#define CLK_TOP_UNIVPLL_D5_D8 71 +-#define CLK_TOP_APLL1_CK 72 +-#define CLK_TOP_APLL1_D2 73 +-#define CLK_TOP_APLL1_D4 74 +-#define CLK_TOP_APLL1_D8 75 +-#define CLK_TOP_APLL2_CK 76 +-#define CLK_TOP_APLL2_D2 77 +-#define CLK_TOP_APLL2_D4 78 +-#define CLK_TOP_APLL2_D8 79 +-#define CLK_TOP_TVDPLL_CK 80 +-#define CLK_TOP_TVDPLL_D2 81 +-#define CLK_TOP_TVDPLL_D4 82 +-#define CLK_TOP_TVDPLL_D8 83 +-#define CLK_TOP_TVDPLL_D16 84 +-#define CLK_TOP_MSDCPLL_CK 85 +-#define CLK_TOP_MSDCPLL_D2 86 +-#define CLK_TOP_MSDCPLL_D4 87 +-#define CLK_TOP_MSDCPLL_D8 88 +-#define CLK_TOP_MSDCPLL_D16 89 +-#define CLK_TOP_AD_OSC_CK 90 +-#define CLK_TOP_OSC_D2 91 +-#define CLK_TOP_OSC_D4 92 +-#define CLK_TOP_OSC_D8 93 +-#define CLK_TOP_OSC_D16 94 +-#define CLK_TOP_F26M_CK_D2 95 +-#define CLK_TOP_MFGPLL_CK 96 +-#define CLK_TOP_UNIVP_192M_CK 97 +-#define CLK_TOP_UNIVP_192M_D2 98 +-#define CLK_TOP_UNIVP_192M_D4 99 +-#define CLK_TOP_UNIVP_192M_D8 100 +-#define CLK_TOP_UNIVP_192M_D16 101 +-#define CLK_TOP_UNIVP_192M_D32 102 +-#define CLK_TOP_MMPLL_CK 103 +-#define CLK_TOP_MMPLL_D4 104 +-#define CLK_TOP_MMPLL_D4_D2 105 +-#define CLK_TOP_MMPLL_D4_D4 106 +-#define CLK_TOP_MMPLL_D5 107 +-#define CLK_TOP_MMPLL_D5_D2 108 +-#define CLK_TOP_MMPLL_D5_D4 109 +-#define CLK_TOP_MMPLL_D6 110 +-#define CLK_TOP_MMPLL_D7 111 +-#define CLK_TOP_CLK26M 112 +-#define CLK_TOP_CLK13M 113 +-#define CLK_TOP_ULPOSC 114 +-#define CLK_TOP_UNIVP_192M 115 +-#define CLK_TOP_MUX_APLL_I2S0 116 +-#define CLK_TOP_MUX_APLL_I2S1 117 +-#define CLK_TOP_MUX_APLL_I2S2 118 +-#define CLK_TOP_MUX_APLL_I2S3 119 +-#define CLK_TOP_MUX_APLL_I2S4 120 +-#define CLK_TOP_MUX_APLL_I2S5 121 +-#define CLK_TOP_APLL12_DIV0 122 +-#define CLK_TOP_APLL12_DIV1 123 +-#define CLK_TOP_APLL12_DIV2 124 +-#define CLK_TOP_APLL12_DIV3 125 +-#define CLK_TOP_APLL12_DIV4 126 +-#define CLK_TOP_APLL12_DIVB 127 +-#define CLK_TOP_UNIVPLL 128 +-#define CLK_TOP_ARMPLL_DIV_PLL1 129 +-#define CLK_TOP_ARMPLL_DIV_PLL2 130 +-#define CLK_TOP_UNIVPLL_D3_D16 131 +-#define CLK_TOP_NR_CLK 132 +- +-/* CAMSYS */ +-#define CLK_CAM_LARB6 0 +-#define CLK_CAM_DFP_VAD 1 +-#define CLK_CAM_CAM 2 +-#define CLK_CAM_CAMTG 3 +-#define CLK_CAM_SENINF 4 +-#define CLK_CAM_CAMSV0 5 +-#define CLK_CAM_CAMSV1 6 +-#define CLK_CAM_CAMSV2 7 +-#define CLK_CAM_CCU 8 +-#define CLK_CAM_LARB3 9 +-#define CLK_CAM_NR_CLK 10 +- +-/* INFRACFG_AO */ +-#define CLK_INFRA_PMIC_TMR 0 +-#define CLK_INFRA_PMIC_AP 1 +-#define CLK_INFRA_PMIC_MD 2 +-#define CLK_INFRA_PMIC_CONN 3 +-#define CLK_INFRA_SCPSYS 4 +-#define CLK_INFRA_SEJ 5 +-#define CLK_INFRA_APXGPT 6 +-#define CLK_INFRA_ICUSB 7 +-#define CLK_INFRA_GCE 8 +-#define CLK_INFRA_THERM 9 +-#define CLK_INFRA_I2C0 10 +-#define CLK_INFRA_I2C1 11 +-#define CLK_INFRA_I2C2 12 +-#define CLK_INFRA_I2C3 13 +-#define CLK_INFRA_PWM_HCLK 14 +-#define CLK_INFRA_PWM1 15 +-#define CLK_INFRA_PWM2 16 +-#define CLK_INFRA_PWM3 17 +-#define CLK_INFRA_PWM4 18 +-#define CLK_INFRA_PWM 19 +-#define CLK_INFRA_UART0 20 +-#define CLK_INFRA_UART1 21 +-#define CLK_INFRA_UART2 22 +-#define CLK_INFRA_UART3 23 +-#define CLK_INFRA_GCE_26M 24 +-#define CLK_INFRA_CQ_DMA_FPC 25 +-#define CLK_INFRA_BTIF 26 +-#define CLK_INFRA_SPI0 27 +-#define CLK_INFRA_MSDC0 28 +-#define CLK_INFRA_MSDC1 29 +-#define CLK_INFRA_MSDC2 30 +-#define CLK_INFRA_MSDC0_SCK 31 +-#define CLK_INFRA_DVFSRC 32 +-#define CLK_INFRA_GCPU 33 +-#define CLK_INFRA_TRNG 34 +-#define CLK_INFRA_AUXADC 35 +-#define CLK_INFRA_CPUM 36 +-#define CLK_INFRA_CCIF1_AP 37 +-#define CLK_INFRA_CCIF1_MD 38 +-#define CLK_INFRA_AUXADC_MD 39 +-#define CLK_INFRA_MSDC1_SCK 40 +-#define CLK_INFRA_MSDC2_SCK 41 +-#define CLK_INFRA_AP_DMA 42 +-#define CLK_INFRA_XIU 43 +-#define CLK_INFRA_DEVICE_APC 44 +-#define CLK_INFRA_CCIF_AP 45 +-#define CLK_INFRA_DEBUGSYS 46 +-#define CLK_INFRA_AUDIO 47 +-#define CLK_INFRA_CCIF_MD 48 +-#define CLK_INFRA_DXCC_SEC_CORE 49 +-#define CLK_INFRA_DXCC_AO 50 +-#define CLK_INFRA_DRAMC_F26M 51 +-#define CLK_INFRA_IRTX 52 +-#define CLK_INFRA_DISP_PWM 53 +-#define CLK_INFRA_CLDMA_BCLK 54 +-#define CLK_INFRA_AUDIO_26M_BCLK 55 +-#define CLK_INFRA_SPI1 56 +-#define CLK_INFRA_I2C4 57 +-#define CLK_INFRA_MODEM_TEMP_SHARE 58 +-#define CLK_INFRA_SPI2 59 +-#define CLK_INFRA_SPI3 60 +-#define CLK_INFRA_UNIPRO_SCK 61 +-#define CLK_INFRA_UNIPRO_TICK 62 +-#define CLK_INFRA_UFS_MP_SAP_BCLK 63 +-#define CLK_INFRA_MD32_BCLK 64 +-#define CLK_INFRA_SSPM 65 +-#define CLK_INFRA_UNIPRO_MBIST 66 +-#define CLK_INFRA_SSPM_BUS_HCLK 67 +-#define CLK_INFRA_I2C5 68 +-#define CLK_INFRA_I2C5_ARBITER 69 +-#define CLK_INFRA_I2C5_IMM 70 +-#define CLK_INFRA_I2C1_ARBITER 71 +-#define CLK_INFRA_I2C1_IMM 72 +-#define CLK_INFRA_I2C2_ARBITER 73 +-#define CLK_INFRA_I2C2_IMM 74 +-#define CLK_INFRA_SPI4 75 +-#define CLK_INFRA_SPI5 76 +-#define CLK_INFRA_CQ_DMA 77 +-#define CLK_INFRA_UFS 78 +-#define CLK_INFRA_AES_UFSFDE 79 +-#define CLK_INFRA_UFS_TICK 80 +-#define CLK_INFRA_MSDC0_SELF 81 +-#define CLK_INFRA_MSDC1_SELF 82 +-#define CLK_INFRA_MSDC2_SELF 83 +-#define CLK_INFRA_SSPM_26M_SELF 84 +-#define CLK_INFRA_SSPM_32K_SELF 85 +-#define CLK_INFRA_UFS_AXI 86 +-#define CLK_INFRA_I2C6 87 +-#define CLK_INFRA_AP_MSDC0 88 +-#define CLK_INFRA_MD_MSDC0 89 +-#define CLK_INFRA_USB 90 +-#define CLK_INFRA_DEVMPU_BCLK 91 +-#define CLK_INFRA_CCIF2_AP 92 +-#define CLK_INFRA_CCIF2_MD 93 +-#define CLK_INFRA_CCIF3_AP 94 +-#define CLK_INFRA_CCIF3_MD 95 +-#define CLK_INFRA_SEJ_F13M 96 +-#define CLK_INFRA_AES_BCLK 97 +-#define CLK_INFRA_I2C7 98 +-#define CLK_INFRA_I2C8 99 +-#define CLK_INFRA_FBIST2FPC 100 +-#define CLK_INFRA_NR_CLK 101 +- +-/* PERICFG */ +-#define CLK_PERI_AXI 0 +-#define CLK_PERI_NR_CLK 1 +- +-/* MFGCFG */ +-#define CLK_MFG_BG3D 0 +-#define CLK_MFG_NR_CLK 1 +- +-/* IMG */ +-#define CLK_IMG_OWE 0 +-#define CLK_IMG_WPE_B 1 +-#define CLK_IMG_WPE_A 2 +-#define CLK_IMG_MFB 3 +-#define CLK_IMG_RSC 4 +-#define CLK_IMG_DPE 5 +-#define CLK_IMG_FDVT 6 +-#define CLK_IMG_DIP 7 +-#define CLK_IMG_LARB2 8 +-#define CLK_IMG_LARB5 9 +-#define CLK_IMG_NR_CLK 10 +- +-/* MMSYS_CONFIG */ +-#define CLK_MM_SMI_COMMON 0 +-#define CLK_MM_SMI_LARB0 1 +-#define CLK_MM_SMI_LARB1 2 +-#define CLK_MM_GALS_COMM0 3 +-#define CLK_MM_GALS_COMM1 4 +-#define CLK_MM_GALS_CCU2MM 5 +-#define CLK_MM_GALS_IPU12MM 6 +-#define CLK_MM_GALS_IMG2MM 7 +-#define CLK_MM_GALS_CAM2MM 8 +-#define CLK_MM_GALS_IPU2MM 9 +-#define CLK_MM_MDP_DL_TXCK 10 +-#define CLK_MM_IPU_DL_TXCK 11 +-#define CLK_MM_MDP_RDMA0 12 +-#define CLK_MM_MDP_RDMA1 13 +-#define CLK_MM_MDP_RSZ0 14 +-#define CLK_MM_MDP_RSZ1 15 +-#define CLK_MM_MDP_TDSHP 16 +-#define CLK_MM_MDP_WROT0 17 +-#define CLK_MM_FAKE_ENG 18 +-#define CLK_MM_DISP_OVL0 19 +-#define CLK_MM_DISP_OVL0_2L 20 +-#define CLK_MM_DISP_OVL1_2L 21 +-#define CLK_MM_DISP_RDMA0 22 +-#define CLK_MM_DISP_RDMA1 23 +-#define CLK_MM_DISP_WDMA0 24 +-#define CLK_MM_DISP_COLOR0 25 +-#define CLK_MM_DISP_CCORR0 26 +-#define CLK_MM_DISP_AAL0 27 +-#define CLK_MM_DISP_GAMMA0 28 +-#define CLK_MM_DISP_DITHER0 29 +-#define CLK_MM_DISP_SPLIT 30 +-#define CLK_MM_DSI0_MM 31 +-#define CLK_MM_DSI0_IF 32 +-#define CLK_MM_DPI_MM 33 +-#define CLK_MM_DPI_IF 34 +-#define CLK_MM_FAKE_ENG2 35 +-#define CLK_MM_MDP_DL_RX 36 +-#define CLK_MM_IPU_DL_RX 37 +-#define CLK_MM_26M 38 +-#define CLK_MM_MMSYS_R2Y 39 +-#define CLK_MM_DISP_RSZ 40 +-#define CLK_MM_MDP_WDMA0 41 +-#define CLK_MM_MDP_AAL 42 +-#define CLK_MM_MDP_CCORR 43 +-#define CLK_MM_DBI_MM 44 +-#define CLK_MM_DBI_IF 45 +-#define CLK_MM_NR_CLK 46 +- +-/* VDEC_GCON */ +-#define CLK_VDEC_VDEC 0 +-#define CLK_VDEC_LARB1 1 +-#define CLK_VDEC_NR_CLK 2 +- +-/* VENC_GCON */ +-#define CLK_VENC_LARB 0 +-#define CLK_VENC_VENC 1 +-#define CLK_VENC_JPGENC 2 +-#define CLK_VENC_NR_CLK 3 +- +-/* AUDIO */ +-#define CLK_AUDIO_TML 0 +-#define CLK_AUDIO_DAC_PREDIS 1 +-#define CLK_AUDIO_DAC 2 +-#define CLK_AUDIO_ADC 3 +-#define CLK_AUDIO_APLL_TUNER 4 +-#define CLK_AUDIO_APLL2_TUNER 5 +-#define CLK_AUDIO_24M 6 +-#define CLK_AUDIO_22M 7 +-#define CLK_AUDIO_AFE 8 +-#define CLK_AUDIO_I2S4 9 +-#define CLK_AUDIO_I2S3 10 +-#define CLK_AUDIO_I2S2 11 +-#define CLK_AUDIO_I2S1 12 +-#define CLK_AUDIO_PDN_ADDA6_ADC 13 +-#define CLK_AUDIO_TDM 14 +-#define CLK_AUDIO_NR_CLK 15 +- +-/* IPU_CONN */ +-#define CLK_IPU_CONN_IPU 0 +-#define CLK_IPU_CONN_AHB 1 +-#define CLK_IPU_CONN_AXI 2 +-#define CLK_IPU_CONN_ISP 3 +-#define CLK_IPU_CONN_CAM_ADL 4 +-#define CLK_IPU_CONN_IMG_ADL 5 +-#define CLK_IPU_CONN_DAP_RX 6 +-#define CLK_IPU_CONN_APB2AXI 7 +-#define CLK_IPU_CONN_APB2AHB 8 +-#define CLK_IPU_CONN_IPU_CAB1TO2 9 +-#define CLK_IPU_CONN_IPU1_CAB1TO2 10 +-#define CLK_IPU_CONN_IPU2_CAB1TO2 11 +-#define CLK_IPU_CONN_CAB3TO3 12 +-#define CLK_IPU_CONN_CAB2TO1 13 +-#define CLK_IPU_CONN_CAB3TO1_SLICE 14 +-#define CLK_IPU_CONN_NR_CLK 15 +- +-/* IPU_ADL */ +-#define CLK_IPU_ADL_CABGEN 0 +-#define CLK_IPU_ADL_NR_CLK 1 +- +-/* IPU_CORE0 */ +-#define CLK_IPU_CORE0_JTAG 0 +-#define CLK_IPU_CORE0_AXI 1 +-#define CLK_IPU_CORE0_IPU 2 +-#define CLK_IPU_CORE0_NR_CLK 3 +- +-/* IPU_CORE1 */ +-#define CLK_IPU_CORE1_JTAG 0 +-#define CLK_IPU_CORE1_AXI 1 +-#define CLK_IPU_CORE1_IPU 2 +-#define CLK_IPU_CORE1_NR_CLK 3 +- +-/* MCUCFG */ +-#define CLK_MCU_MP0_SEL 0 +-#define CLK_MCU_MP2_SEL 1 +-#define CLK_MCU_BUS_SEL 2 +-#define CLK_MCU_NR_CLK 3 +- +-#endif /* _DT_BINDINGS_CLK_MT8183_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/mt8192-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/mt8192-clk.h +deleted file mode 100644 +index 5ab68f15a256..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/mt8192-clk.h ++++ /dev/null +@@ -1,585 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2021 MediaTek Inc. +- * Author: Chun-Jie Chen +- */ +- +-#ifndef _DT_BINDINGS_CLK_MT8192_H +-#define _DT_BINDINGS_CLK_MT8192_H +- +-/* TOPCKGEN */ +- +-#define CLK_TOP_AXI_SEL 0 +-#define CLK_TOP_SPM_SEL 1 +-#define CLK_TOP_SCP_SEL 2 +-#define CLK_TOP_BUS_AXIMEM_SEL 3 +-#define CLK_TOP_DISP_SEL 4 +-#define CLK_TOP_MDP_SEL 5 +-#define CLK_TOP_IMG1_SEL 6 +-#define CLK_TOP_IMG2_SEL 7 +-#define CLK_TOP_IPE_SEL 8 +-#define CLK_TOP_DPE_SEL 9 +-#define CLK_TOP_CAM_SEL 10 +-#define CLK_TOP_CCU_SEL 11 +-#define CLK_TOP_DSP7_SEL 12 +-#define CLK_TOP_MFG_REF_SEL 13 +-#define CLK_TOP_MFG_PLL_SEL 14 +-#define CLK_TOP_CAMTG_SEL 15 +-#define CLK_TOP_CAMTG2_SEL 16 +-#define CLK_TOP_CAMTG3_SEL 17 +-#define CLK_TOP_CAMTG4_SEL 18 +-#define CLK_TOP_CAMTG5_SEL 19 +-#define CLK_TOP_CAMTG6_SEL 20 +-#define CLK_TOP_UART_SEL 21 +-#define CLK_TOP_SPI_SEL 22 +-#define CLK_TOP_MSDC50_0_H_SEL 23 +-#define CLK_TOP_MSDC50_0_SEL 24 +-#define CLK_TOP_MSDC30_1_SEL 25 +-#define CLK_TOP_MSDC30_2_SEL 26 +-#define CLK_TOP_AUDIO_SEL 27 +-#define CLK_TOP_AUD_INTBUS_SEL 28 +-#define CLK_TOP_PWRAP_ULPOSC_SEL 29 +-#define CLK_TOP_ATB_SEL 30 +-#define CLK_TOP_DPI_SEL 31 +-#define CLK_TOP_SCAM_SEL 32 +-#define CLK_TOP_DISP_PWM_SEL 33 +-#define CLK_TOP_USB_TOP_SEL 34 +-#define CLK_TOP_SSUSB_XHCI_SEL 35 +-#define CLK_TOP_I2C_SEL 36 +-#define CLK_TOP_SENINF_SEL 37 +-#define CLK_TOP_SENINF1_SEL 38 +-#define CLK_TOP_SENINF2_SEL 39 +-#define CLK_TOP_SENINF3_SEL 40 +-#define CLK_TOP_TL_SEL 41 +-#define CLK_TOP_DXCC_SEL 42 +-#define CLK_TOP_AUD_ENGEN1_SEL 43 +-#define CLK_TOP_AUD_ENGEN2_SEL 44 +-#define CLK_TOP_AES_UFSFDE_SEL 45 +-#define CLK_TOP_UFS_SEL 46 +-#define CLK_TOP_AUD_1_SEL 47 +-#define CLK_TOP_AUD_2_SEL 48 +-#define CLK_TOP_ADSP_SEL 49 +-#define CLK_TOP_DPMAIF_MAIN_SEL 50 +-#define CLK_TOP_VENC_SEL 51 +-#define CLK_TOP_VDEC_SEL 52 +-#define CLK_TOP_CAMTM_SEL 53 +-#define CLK_TOP_PWM_SEL 54 +-#define CLK_TOP_AUDIO_H_SEL 55 +-#define CLK_TOP_SPMI_MST_SEL 56 +-#define CLK_TOP_AES_MSDCFDE_SEL 57 +-#define CLK_TOP_SFLASH_SEL 58 +-#define CLK_TOP_APLL_I2S0_M_SEL 59 +-#define CLK_TOP_APLL_I2S1_M_SEL 60 +-#define CLK_TOP_APLL_I2S2_M_SEL 61 +-#define CLK_TOP_APLL_I2S3_M_SEL 62 +-#define CLK_TOP_APLL_I2S4_M_SEL 63 +-#define CLK_TOP_APLL_I2S5_M_SEL 64 +-#define CLK_TOP_APLL_I2S6_M_SEL 65 +-#define CLK_TOP_APLL_I2S7_M_SEL 66 +-#define CLK_TOP_APLL_I2S8_M_SEL 67 +-#define CLK_TOP_APLL_I2S9_M_SEL 68 +-#define CLK_TOP_MAINPLL_D3 69 +-#define CLK_TOP_MAINPLL_D4 70 +-#define CLK_TOP_MAINPLL_D4_D2 71 +-#define CLK_TOP_MAINPLL_D4_D4 72 +-#define CLK_TOP_MAINPLL_D4_D8 73 +-#define CLK_TOP_MAINPLL_D4_D16 74 +-#define CLK_TOP_MAINPLL_D5 75 +-#define CLK_TOP_MAINPLL_D5_D2 76 +-#define CLK_TOP_MAINPLL_D5_D4 77 +-#define CLK_TOP_MAINPLL_D5_D8 78 +-#define CLK_TOP_MAINPLL_D6 79 +-#define CLK_TOP_MAINPLL_D6_D2 80 +-#define CLK_TOP_MAINPLL_D6_D4 81 +-#define CLK_TOP_MAINPLL_D7 82 +-#define CLK_TOP_MAINPLL_D7_D2 83 +-#define CLK_TOP_MAINPLL_D7_D4 84 +-#define CLK_TOP_MAINPLL_D7_D8 85 +-#define CLK_TOP_UNIVPLL_D3 86 +-#define CLK_TOP_UNIVPLL_D4 87 +-#define CLK_TOP_UNIVPLL_D4_D2 88 +-#define CLK_TOP_UNIVPLL_D4_D4 89 +-#define CLK_TOP_UNIVPLL_D4_D8 90 +-#define CLK_TOP_UNIVPLL_D5 91 +-#define CLK_TOP_UNIVPLL_D5_D2 92 +-#define CLK_TOP_UNIVPLL_D5_D4 93 +-#define CLK_TOP_UNIVPLL_D5_D8 94 +-#define CLK_TOP_UNIVPLL_D6 95 +-#define CLK_TOP_UNIVPLL_D6_D2 96 +-#define CLK_TOP_UNIVPLL_D6_D4 97 +-#define CLK_TOP_UNIVPLL_D6_D8 98 +-#define CLK_TOP_UNIVPLL_D6_D16 99 +-#define CLK_TOP_UNIVPLL_D7 100 +-#define CLK_TOP_APLL1 101 +-#define CLK_TOP_APLL1_D2 102 +-#define CLK_TOP_APLL1_D4 103 +-#define CLK_TOP_APLL1_D8 104 +-#define CLK_TOP_APLL2 105 +-#define CLK_TOP_APLL2_D2 106 +-#define CLK_TOP_APLL2_D4 107 +-#define CLK_TOP_APLL2_D8 108 +-#define CLK_TOP_MMPLL_D4 109 +-#define CLK_TOP_MMPLL_D4_D2 110 +-#define CLK_TOP_MMPLL_D5 111 +-#define CLK_TOP_MMPLL_D5_D2 112 +-#define CLK_TOP_MMPLL_D6 113 +-#define CLK_TOP_MMPLL_D6_D2 114 +-#define CLK_TOP_MMPLL_D7 115 +-#define CLK_TOP_MMPLL_D9 116 +-#define CLK_TOP_APUPLL 117 +-#define CLK_TOP_NPUPLL 118 +-#define CLK_TOP_TVDPLL 119 +-#define CLK_TOP_TVDPLL_D2 120 +-#define CLK_TOP_TVDPLL_D4 121 +-#define CLK_TOP_TVDPLL_D8 122 +-#define CLK_TOP_TVDPLL_D16 123 +-#define CLK_TOP_MSDCPLL 124 +-#define CLK_TOP_MSDCPLL_D2 125 +-#define CLK_TOP_MSDCPLL_D4 126 +-#define CLK_TOP_ULPOSC 127 +-#define CLK_TOP_OSC_D2 128 +-#define CLK_TOP_OSC_D4 129 +-#define CLK_TOP_OSC_D8 130 +-#define CLK_TOP_OSC_D10 131 +-#define CLK_TOP_OSC_D16 132 +-#define CLK_TOP_OSC_D20 133 +-#define CLK_TOP_CSW_F26M_D2 134 +-#define CLK_TOP_ADSPPLL 135 +-#define CLK_TOP_UNIVPLL_192M 136 +-#define CLK_TOP_UNIVPLL_192M_D2 137 +-#define CLK_TOP_UNIVPLL_192M_D4 138 +-#define CLK_TOP_UNIVPLL_192M_D8 139 +-#define CLK_TOP_UNIVPLL_192M_D16 140 +-#define CLK_TOP_UNIVPLL_192M_D32 141 +-#define CLK_TOP_APLL12_DIV0 142 +-#define CLK_TOP_APLL12_DIV1 143 +-#define CLK_TOP_APLL12_DIV2 144 +-#define CLK_TOP_APLL12_DIV3 145 +-#define CLK_TOP_APLL12_DIV4 146 +-#define CLK_TOP_APLL12_DIVB 147 +-#define CLK_TOP_APLL12_DIV5 148 +-#define CLK_TOP_APLL12_DIV6 149 +-#define CLK_TOP_APLL12_DIV7 150 +-#define CLK_TOP_APLL12_DIV8 151 +-#define CLK_TOP_APLL12_DIV9 152 +-#define CLK_TOP_SSUSB_TOP_REF 153 +-#define CLK_TOP_SSUSB_PHY_REF 154 +-#define CLK_TOP_NR_CLK 155 +- +-/* INFRACFG */ +- +-#define CLK_INFRA_PMIC_TMR 0 +-#define CLK_INFRA_PMIC_AP 1 +-#define CLK_INFRA_PMIC_MD 2 +-#define CLK_INFRA_PMIC_CONN 3 +-#define CLK_INFRA_SCPSYS 4 +-#define CLK_INFRA_SEJ 5 +-#define CLK_INFRA_APXGPT 6 +-#define CLK_INFRA_GCE 7 +-#define CLK_INFRA_GCE2 8 +-#define CLK_INFRA_THERM 9 +-#define CLK_INFRA_I2C0 10 +-#define CLK_INFRA_AP_DMA_PSEUDO 11 +-#define CLK_INFRA_I2C2 12 +-#define CLK_INFRA_I2C3 13 +-#define CLK_INFRA_PWM_H 14 +-#define CLK_INFRA_PWM1 15 +-#define CLK_INFRA_PWM2 16 +-#define CLK_INFRA_PWM3 17 +-#define CLK_INFRA_PWM4 18 +-#define CLK_INFRA_PWM 19 +-#define CLK_INFRA_UART0 20 +-#define CLK_INFRA_UART1 21 +-#define CLK_INFRA_UART2 22 +-#define CLK_INFRA_UART3 23 +-#define CLK_INFRA_GCE_26M 24 +-#define CLK_INFRA_CQ_DMA_FPC 25 +-#define CLK_INFRA_BTIF 26 +-#define CLK_INFRA_SPI0 27 +-#define CLK_INFRA_MSDC0 28 +-#define CLK_INFRA_MSDC1 29 +-#define CLK_INFRA_MSDC2 30 +-#define CLK_INFRA_MSDC0_SRC 31 +-#define CLK_INFRA_GCPU 32 +-#define CLK_INFRA_TRNG 33 +-#define CLK_INFRA_AUXADC 34 +-#define CLK_INFRA_CPUM 35 +-#define CLK_INFRA_CCIF1_AP 36 +-#define CLK_INFRA_CCIF1_MD 37 +-#define CLK_INFRA_AUXADC_MD 38 +-#define CLK_INFRA_PCIE_TL_26M 39 +-#define CLK_INFRA_MSDC1_SRC 40 +-#define CLK_INFRA_MSDC2_SRC 41 +-#define CLK_INFRA_PCIE_TL_96M 42 +-#define CLK_INFRA_PCIE_PL_P_250M 43 +-#define CLK_INFRA_DEVICE_APC 44 +-#define CLK_INFRA_CCIF_AP 45 +-#define CLK_INFRA_DEBUGSYS 46 +-#define CLK_INFRA_AUDIO 47 +-#define CLK_INFRA_CCIF_MD 48 +-#define CLK_INFRA_DXCC_SEC_CORE 49 +-#define CLK_INFRA_DXCC_AO 50 +-#define CLK_INFRA_DBG_TRACE 51 +-#define CLK_INFRA_DEVMPU_B 52 +-#define CLK_INFRA_DRAMC_F26M 53 +-#define CLK_INFRA_IRTX 54 +-#define CLK_INFRA_SSUSB 55 +-#define CLK_INFRA_DISP_PWM 56 +-#define CLK_INFRA_CLDMA_B 57 +-#define CLK_INFRA_AUDIO_26M_B 58 +-#define CLK_INFRA_MODEM_TEMP_SHARE 59 +-#define CLK_INFRA_SPI1 60 +-#define CLK_INFRA_I2C4 61 +-#define CLK_INFRA_SPI2 62 +-#define CLK_INFRA_SPI3 63 +-#define CLK_INFRA_UNIPRO_SYS 64 +-#define CLK_INFRA_UNIPRO_TICK 65 +-#define CLK_INFRA_UFS_MP_SAP_B 66 +-#define CLK_INFRA_MD32_B 67 +-#define CLK_INFRA_UNIPRO_MBIST 68 +-#define CLK_INFRA_I2C5 69 +-#define CLK_INFRA_I2C5_ARBITER 70 +-#define CLK_INFRA_I2C5_IMM 71 +-#define CLK_INFRA_I2C1_ARBITER 72 +-#define CLK_INFRA_I2C1_IMM 73 +-#define CLK_INFRA_I2C2_ARBITER 74 +-#define CLK_INFRA_I2C2_IMM 75 +-#define CLK_INFRA_SPI4 76 +-#define CLK_INFRA_SPI5 77 +-#define CLK_INFRA_CQ_DMA 78 +-#define CLK_INFRA_UFS 79 +-#define CLK_INFRA_AES_UFSFDE 80 +-#define CLK_INFRA_UFS_TICK 81 +-#define CLK_INFRA_SSUSB_XHCI 82 +-#define CLK_INFRA_MSDC0_SELF 83 +-#define CLK_INFRA_MSDC1_SELF 84 +-#define CLK_INFRA_MSDC2_SELF 85 +-#define CLK_INFRA_UFS_AXI 86 +-#define CLK_INFRA_I2C6 87 +-#define CLK_INFRA_AP_MSDC0 88 +-#define CLK_INFRA_MD_MSDC0 89 +-#define CLK_INFRA_CCIF5_AP 90 +-#define CLK_INFRA_CCIF5_MD 91 +-#define CLK_INFRA_PCIE_TOP_H_133M 92 +-#define CLK_INFRA_FLASHIF_TOP_H_133M 93 +-#define CLK_INFRA_PCIE_PERI_26M 94 +-#define CLK_INFRA_CCIF2_AP 95 +-#define CLK_INFRA_CCIF2_MD 96 +-#define CLK_INFRA_CCIF3_AP 97 +-#define CLK_INFRA_CCIF3_MD 98 +-#define CLK_INFRA_SEJ_F13M 99 +-#define CLK_INFRA_AES 100 +-#define CLK_INFRA_I2C7 101 +-#define CLK_INFRA_I2C8 102 +-#define CLK_INFRA_FBIST2FPC 103 +-#define CLK_INFRA_DEVICE_APC_SYNC 104 +-#define CLK_INFRA_DPMAIF_MAIN 105 +-#define CLK_INFRA_PCIE_TL_32K 106 +-#define CLK_INFRA_CCIF4_AP 107 +-#define CLK_INFRA_CCIF4_MD 108 +-#define CLK_INFRA_SPI6 109 +-#define CLK_INFRA_SPI7 110 +-#define CLK_INFRA_133M 111 +-#define CLK_INFRA_66M 112 +-#define CLK_INFRA_66M_PERI_BUS 113 +-#define CLK_INFRA_FREE_DCM_133M 114 +-#define CLK_INFRA_FREE_DCM_66M 115 +-#define CLK_INFRA_PERI_BUS_DCM_133M 116 +-#define CLK_INFRA_PERI_BUS_DCM_66M 117 +-#define CLK_INFRA_FLASHIF_PERI_26M 118 +-#define CLK_INFRA_FLASHIF_SFLASH 119 +-#define CLK_INFRA_AP_DMA 120 +-#define CLK_INFRA_NR_CLK 121 +- +-/* PERICFG */ +- +-#define CLK_PERI_PERIAXI 0 +-#define CLK_PERI_NR_CLK 1 +- +-/* APMIXEDSYS */ +- +-#define CLK_APMIXED_MAINPLL 0 +-#define CLK_APMIXED_UNIVPLL 1 +-#define CLK_APMIXED_USBPLL 2 +-#define CLK_APMIXED_MSDCPLL 3 +-#define CLK_APMIXED_MMPLL 4 +-#define CLK_APMIXED_ADSPPLL 5 +-#define CLK_APMIXED_MFGPLL 6 +-#define CLK_APMIXED_TVDPLL 7 +-#define CLK_APMIXED_APLL1 8 +-#define CLK_APMIXED_APLL2 9 +-#define CLK_APMIXED_MIPID26M 10 +-#define CLK_APMIXED_NR_CLK 11 +- +-/* SCP_ADSP */ +- +-#define CLK_SCP_ADSP_AUDIODSP 0 +-#define CLK_SCP_ADSP_NR_CLK 1 +- +-/* IMP_IIC_WRAP_C */ +- +-#define CLK_IMP_IIC_WRAP_C_I2C10 0 +-#define CLK_IMP_IIC_WRAP_C_I2C11 1 +-#define CLK_IMP_IIC_WRAP_C_I2C12 2 +-#define CLK_IMP_IIC_WRAP_C_I2C13 3 +-#define CLK_IMP_IIC_WRAP_C_NR_CLK 4 +- +-/* AUDSYS */ +- +-#define CLK_AUD_AFE 0 +-#define CLK_AUD_22M 1 +-#define CLK_AUD_24M 2 +-#define CLK_AUD_APLL2_TUNER 3 +-#define CLK_AUD_APLL_TUNER 4 +-#define CLK_AUD_TDM 5 +-#define CLK_AUD_ADC 6 +-#define CLK_AUD_DAC 7 +-#define CLK_AUD_DAC_PREDIS 8 +-#define CLK_AUD_TML 9 +-#define CLK_AUD_NLE 10 +-#define CLK_AUD_I2S1_B 11 +-#define CLK_AUD_I2S2_B 12 +-#define CLK_AUD_I2S3_B 13 +-#define CLK_AUD_I2S4_B 14 +-#define CLK_AUD_CONNSYS_I2S_ASRC 15 +-#define CLK_AUD_GENERAL1_ASRC 16 +-#define CLK_AUD_GENERAL2_ASRC 17 +-#define CLK_AUD_DAC_HIRES 18 +-#define CLK_AUD_ADC_HIRES 19 +-#define CLK_AUD_ADC_HIRES_TML 20 +-#define CLK_AUD_ADDA6_ADC 21 +-#define CLK_AUD_ADDA6_ADC_HIRES 22 +-#define CLK_AUD_3RD_DAC 23 +-#define CLK_AUD_3RD_DAC_PREDIS 24 +-#define CLK_AUD_3RD_DAC_TML 25 +-#define CLK_AUD_3RD_DAC_HIRES 26 +-#define CLK_AUD_I2S5_B 27 +-#define CLK_AUD_I2S6_B 28 +-#define CLK_AUD_I2S7_B 29 +-#define CLK_AUD_I2S8_B 30 +-#define CLK_AUD_I2S9_B 31 +-#define CLK_AUD_NR_CLK 32 +- +-/* IMP_IIC_WRAP_E */ +- +-#define CLK_IMP_IIC_WRAP_E_I2C3 0 +-#define CLK_IMP_IIC_WRAP_E_NR_CLK 1 +- +-/* IMP_IIC_WRAP_S */ +- +-#define CLK_IMP_IIC_WRAP_S_I2C7 0 +-#define CLK_IMP_IIC_WRAP_S_I2C8 1 +-#define CLK_IMP_IIC_WRAP_S_I2C9 2 +-#define CLK_IMP_IIC_WRAP_S_NR_CLK 3 +- +-/* IMP_IIC_WRAP_WS */ +- +-#define CLK_IMP_IIC_WRAP_WS_I2C1 0 +-#define CLK_IMP_IIC_WRAP_WS_I2C2 1 +-#define CLK_IMP_IIC_WRAP_WS_I2C4 2 +-#define CLK_IMP_IIC_WRAP_WS_NR_CLK 3 +- +-/* IMP_IIC_WRAP_W */ +- +-#define CLK_IMP_IIC_WRAP_W_I2C5 0 +-#define CLK_IMP_IIC_WRAP_W_NR_CLK 1 +- +-/* IMP_IIC_WRAP_N */ +- +-#define CLK_IMP_IIC_WRAP_N_I2C0 0 +-#define CLK_IMP_IIC_WRAP_N_I2C6 1 +-#define CLK_IMP_IIC_WRAP_N_NR_CLK 2 +- +-/* MSDC_TOP */ +- +-#define CLK_MSDC_TOP_AES_0P 0 +-#define CLK_MSDC_TOP_SRC_0P 1 +-#define CLK_MSDC_TOP_SRC_1P 2 +-#define CLK_MSDC_TOP_SRC_2P 3 +-#define CLK_MSDC_TOP_P_MSDC0 4 +-#define CLK_MSDC_TOP_P_MSDC1 5 +-#define CLK_MSDC_TOP_P_MSDC2 6 +-#define CLK_MSDC_TOP_P_CFG 7 +-#define CLK_MSDC_TOP_AXI 8 +-#define CLK_MSDC_TOP_H_MST_0P 9 +-#define CLK_MSDC_TOP_H_MST_1P 10 +-#define CLK_MSDC_TOP_H_MST_2P 11 +-#define CLK_MSDC_TOP_MEM_OFF_DLY_26M 12 +-#define CLK_MSDC_TOP_32K 13 +-#define CLK_MSDC_TOP_AHB2AXI_BRG_AXI 14 +-#define CLK_MSDC_TOP_NR_CLK 15 +- +-/* MSDC */ +- +-#define CLK_MSDC_AXI_WRAP 0 +-#define CLK_MSDC_NR_CLK 1 +- +-/* MFGCFG */ +- +-#define CLK_MFG_BG3D 0 +-#define CLK_MFG_NR_CLK 1 +- +-/* MMSYS */ +- +-#define CLK_MM_DISP_MUTEX0 0 +-#define CLK_MM_DISP_CONFIG 1 +-#define CLK_MM_DISP_OVL0 2 +-#define CLK_MM_DISP_RDMA0 3 +-#define CLK_MM_DISP_OVL0_2L 4 +-#define CLK_MM_DISP_WDMA0 5 +-#define CLK_MM_DISP_UFBC_WDMA0 6 +-#define CLK_MM_DISP_RSZ0 7 +-#define CLK_MM_DISP_AAL0 8 +-#define CLK_MM_DISP_CCORR0 9 +-#define CLK_MM_DISP_DITHER0 10 +-#define CLK_MM_SMI_INFRA 11 +-#define CLK_MM_DISP_GAMMA0 12 +-#define CLK_MM_DISP_POSTMASK0 13 +-#define CLK_MM_DISP_DSC_WRAP0 14 +-#define CLK_MM_DSI0 15 +-#define CLK_MM_DISP_COLOR0 16 +-#define CLK_MM_SMI_COMMON 17 +-#define CLK_MM_DISP_FAKE_ENG0 18 +-#define CLK_MM_DISP_FAKE_ENG1 19 +-#define CLK_MM_MDP_TDSHP4 20 +-#define CLK_MM_MDP_RSZ4 21 +-#define CLK_MM_MDP_AAL4 22 +-#define CLK_MM_MDP_HDR4 23 +-#define CLK_MM_MDP_RDMA4 24 +-#define CLK_MM_MDP_COLOR4 25 +-#define CLK_MM_DISP_Y2R0 26 +-#define CLK_MM_SMI_GALS 27 +-#define CLK_MM_DISP_OVL2_2L 28 +-#define CLK_MM_DISP_RDMA4 29 +-#define CLK_MM_DISP_DPI0 30 +-#define CLK_MM_SMI_IOMMU 31 +-#define CLK_MM_DSI_DSI0 32 +-#define CLK_MM_DPI_DPI0 33 +-#define CLK_MM_26MHZ 34 +-#define CLK_MM_32KHZ 35 +-#define CLK_MM_NR_CLK 36 +- +-/* IMGSYS */ +- +-#define CLK_IMG_LARB9 0 +-#define CLK_IMG_LARB10 1 +-#define CLK_IMG_DIP 2 +-#define CLK_IMG_GALS 3 +-#define CLK_IMG_NR_CLK 4 +- +-/* IMGSYS2 */ +- +-#define CLK_IMG2_LARB11 0 +-#define CLK_IMG2_LARB12 1 +-#define CLK_IMG2_MFB 2 +-#define CLK_IMG2_WPE 3 +-#define CLK_IMG2_MSS 4 +-#define CLK_IMG2_GALS 5 +-#define CLK_IMG2_NR_CLK 6 +- +-/* VDECSYS_SOC */ +- +-#define CLK_VDEC_SOC_LARB1 0 +-#define CLK_VDEC_SOC_LAT 1 +-#define CLK_VDEC_SOC_LAT_ACTIVE 2 +-#define CLK_VDEC_SOC_VDEC 3 +-#define CLK_VDEC_SOC_VDEC_ACTIVE 4 +-#define CLK_VDEC_SOC_NR_CLK 5 +- +-/* VDECSYS */ +- +-#define CLK_VDEC_LARB1 0 +-#define CLK_VDEC_LAT 1 +-#define CLK_VDEC_LAT_ACTIVE 2 +-#define CLK_VDEC_VDEC 3 +-#define CLK_VDEC_ACTIVE 4 +-#define CLK_VDEC_NR_CLK 5 +- +-/* VENCSYS */ +- +-#define CLK_VENC_SET0_LARB 0 +-#define CLK_VENC_SET1_VENC 1 +-#define CLK_VENC_SET2_JPGENC 2 +-#define CLK_VENC_SET5_GALS 3 +-#define CLK_VENC_NR_CLK 4 +- +-/* CAMSYS */ +- +-#define CLK_CAM_LARB13 0 +-#define CLK_CAM_DFP_VAD 1 +-#define CLK_CAM_LARB14 2 +-#define CLK_CAM_CAM 3 +-#define CLK_CAM_CAMTG 4 +-#define CLK_CAM_SENINF 5 +-#define CLK_CAM_CAMSV0 6 +-#define CLK_CAM_CAMSV1 7 +-#define CLK_CAM_CAMSV2 8 +-#define CLK_CAM_CAMSV3 9 +-#define CLK_CAM_CCU0 10 +-#define CLK_CAM_CCU1 11 +-#define CLK_CAM_MRAW0 12 +-#define CLK_CAM_FAKE_ENG 13 +-#define CLK_CAM_CCU_GALS 14 +-#define CLK_CAM_CAM2MM_GALS 15 +-#define CLK_CAM_NR_CLK 16 +- +-/* CAMSYS_RAWA */ +- +-#define CLK_CAM_RAWA_LARBX 0 +-#define CLK_CAM_RAWA_CAM 1 +-#define CLK_CAM_RAWA_CAMTG 2 +-#define CLK_CAM_RAWA_NR_CLK 3 +- +-/* CAMSYS_RAWB */ +- +-#define CLK_CAM_RAWB_LARBX 0 +-#define CLK_CAM_RAWB_CAM 1 +-#define CLK_CAM_RAWB_CAMTG 2 +-#define CLK_CAM_RAWB_NR_CLK 3 +- +-/* CAMSYS_RAWC */ +- +-#define CLK_CAM_RAWC_LARBX 0 +-#define CLK_CAM_RAWC_CAM 1 +-#define CLK_CAM_RAWC_CAMTG 2 +-#define CLK_CAM_RAWC_NR_CLK 3 +- +-/* IPESYS */ +- +-#define CLK_IPE_LARB19 0 +-#define CLK_IPE_LARB20 1 +-#define CLK_IPE_SMI_SUBCOM 2 +-#define CLK_IPE_FD 3 +-#define CLK_IPE_FE 4 +-#define CLK_IPE_RSC 5 +-#define CLK_IPE_DPE 6 +-#define CLK_IPE_GALS 7 +-#define CLK_IPE_NR_CLK 8 +- +-/* MDPSYS */ +- +-#define CLK_MDP_RDMA0 0 +-#define CLK_MDP_TDSHP0 1 +-#define CLK_MDP_IMG_DL_ASYNC0 2 +-#define CLK_MDP_IMG_DL_ASYNC1 3 +-#define CLK_MDP_RDMA1 4 +-#define CLK_MDP_TDSHP1 5 +-#define CLK_MDP_SMI0 6 +-#define CLK_MDP_APB_BUS 7 +-#define CLK_MDP_WROT0 8 +-#define CLK_MDP_RSZ0 9 +-#define CLK_MDP_HDR0 10 +-#define CLK_MDP_MUTEX0 11 +-#define CLK_MDP_WROT1 12 +-#define CLK_MDP_RSZ1 13 +-#define CLK_MDP_HDR1 14 +-#define CLK_MDP_FAKE_ENG0 15 +-#define CLK_MDP_AAL0 16 +-#define CLK_MDP_AAL1 17 +-#define CLK_MDP_COLOR0 18 +-#define CLK_MDP_COLOR1 19 +-#define CLK_MDP_IMG_DL_RELAY0_ASYNC0 20 +-#define CLK_MDP_IMG_DL_RELAY1_ASYNC1 21 +-#define CLK_MDP_NR_CLK 22 +- +-#endif /* _DT_BINDINGS_CLK_MT8192_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/mt8516-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/mt8516-clk.h +deleted file mode 100644 +index 816447b98edd..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/mt8516-clk.h ++++ /dev/null +@@ -1,228 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2019 MediaTek Inc. +- * Copyright (c) 2019 BayLibre, SAS. +- * Author: James Liao +- */ +- +-#ifndef _DT_BINDINGS_CLK_MT8516_H +-#define _DT_BINDINGS_CLK_MT8516_H +- +-/* APMIXEDSYS */ +- +-#define CLK_APMIXED_ARMPLL 0 +-#define CLK_APMIXED_MAINPLL 1 +-#define CLK_APMIXED_UNIVPLL 2 +-#define CLK_APMIXED_MMPLL 3 +-#define CLK_APMIXED_APLL1 4 +-#define CLK_APMIXED_APLL2 5 +-#define CLK_APMIXED_NR_CLK 6 +- +-/* INFRACFG */ +- +-#define CLK_IFR_MUX1_SEL 0 +-#define CLK_IFR_ETH_25M_SEL 1 +-#define CLK_IFR_I2C0_SEL 2 +-#define CLK_IFR_I2C1_SEL 3 +-#define CLK_IFR_I2C2_SEL 4 +-#define CLK_IFR_NR_CLK 5 +- +-/* TOPCKGEN */ +- +-#define CLK_TOP_CLK_NULL 0 +-#define CLK_TOP_I2S_INFRA_BCK 1 +-#define CLK_TOP_MEMPLL 2 +-#define CLK_TOP_DMPLL 3 +-#define CLK_TOP_MAINPLL_D2 4 +-#define CLK_TOP_MAINPLL_D4 5 +-#define CLK_TOP_MAINPLL_D8 6 +-#define CLK_TOP_MAINPLL_D16 7 +-#define CLK_TOP_MAINPLL_D11 8 +-#define CLK_TOP_MAINPLL_D22 9 +-#define CLK_TOP_MAINPLL_D3 10 +-#define CLK_TOP_MAINPLL_D6 11 +-#define CLK_TOP_MAINPLL_D12 12 +-#define CLK_TOP_MAINPLL_D5 13 +-#define CLK_TOP_MAINPLL_D10 14 +-#define CLK_TOP_MAINPLL_D20 15 +-#define CLK_TOP_MAINPLL_D40 16 +-#define CLK_TOP_MAINPLL_D7 17 +-#define CLK_TOP_MAINPLL_D14 18 +-#define CLK_TOP_UNIVPLL_D2 19 +-#define CLK_TOP_UNIVPLL_D4 20 +-#define CLK_TOP_UNIVPLL_D8 21 +-#define CLK_TOP_UNIVPLL_D16 22 +-#define CLK_TOP_UNIVPLL_D3 23 +-#define CLK_TOP_UNIVPLL_D6 24 +-#define CLK_TOP_UNIVPLL_D12 25 +-#define CLK_TOP_UNIVPLL_D24 26 +-#define CLK_TOP_UNIVPLL_D5 27 +-#define CLK_TOP_UNIVPLL_D20 28 +-#define CLK_TOP_MMPLL380M 29 +-#define CLK_TOP_MMPLL_D2 30 +-#define CLK_TOP_MMPLL_200M 31 +-#define CLK_TOP_USB_PHY48M 32 +-#define CLK_TOP_APLL1 33 +-#define CLK_TOP_APLL1_D2 34 +-#define CLK_TOP_APLL1_D4 35 +-#define CLK_TOP_APLL1_D8 36 +-#define CLK_TOP_APLL2 37 +-#define CLK_TOP_APLL2_D2 38 +-#define CLK_TOP_APLL2_D4 39 +-#define CLK_TOP_APLL2_D8 40 +-#define CLK_TOP_CLK26M 41 +-#define CLK_TOP_CLK26M_D2 42 +-#define CLK_TOP_AHB_INFRA_D2 43 +-#define CLK_TOP_NFI1X 44 +-#define CLK_TOP_ETH_D2 45 +-#define CLK_TOP_THEM 46 +-#define CLK_TOP_APDMA 47 +-#define CLK_TOP_I2C0 48 +-#define CLK_TOP_I2C1 49 +-#define CLK_TOP_AUXADC1 50 +-#define CLK_TOP_NFI 51 +-#define CLK_TOP_NFIECC 52 +-#define CLK_TOP_DEBUGSYS 53 +-#define CLK_TOP_PWM 54 +-#define CLK_TOP_UART0 55 +-#define CLK_TOP_UART1 56 +-#define CLK_TOP_BTIF 57 +-#define CLK_TOP_USB 58 +-#define CLK_TOP_FLASHIF_26M 59 +-#define CLK_TOP_AUXADC2 60 +-#define CLK_TOP_I2C2 61 +-#define CLK_TOP_MSDC0 62 +-#define CLK_TOP_MSDC1 63 +-#define CLK_TOP_NFI2X 64 +-#define CLK_TOP_PMICWRAP_AP 65 +-#define CLK_TOP_SEJ 66 +-#define CLK_TOP_MEMSLP_DLYER 67 +-#define CLK_TOP_SPI 68 +-#define CLK_TOP_APXGPT 69 +-#define CLK_TOP_AUDIO 70 +-#define CLK_TOP_PMICWRAP_MD 71 +-#define CLK_TOP_PMICWRAP_CONN 72 +-#define CLK_TOP_PMICWRAP_26M 73 +-#define CLK_TOP_AUX_ADC 74 +-#define CLK_TOP_AUX_TP 75 +-#define CLK_TOP_MSDC2 76 +-#define CLK_TOP_RBIST 77 +-#define CLK_TOP_NFI_BUS 78 +-#define CLK_TOP_GCE 79 +-#define CLK_TOP_TRNG 80 +-#define CLK_TOP_SEJ_13M 81 +-#define CLK_TOP_AES 82 +-#define CLK_TOP_PWM_B 83 +-#define CLK_TOP_PWM1_FB 84 +-#define CLK_TOP_PWM2_FB 85 +-#define CLK_TOP_PWM3_FB 86 +-#define CLK_TOP_PWM4_FB 87 +-#define CLK_TOP_PWM5_FB 88 +-#define CLK_TOP_USB_1P 89 +-#define CLK_TOP_FLASHIF_FREERUN 90 +-#define CLK_TOP_66M_ETH 91 +-#define CLK_TOP_133M_ETH 92 +-#define CLK_TOP_FETH_25M 93 +-#define CLK_TOP_FETH_50M 94 +-#define CLK_TOP_FLASHIF_AXI 95 +-#define CLK_TOP_USBIF 96 +-#define CLK_TOP_UART2 97 +-#define CLK_TOP_BSI 98 +-#define CLK_TOP_RG_SPINOR 99 +-#define CLK_TOP_RG_MSDC2 100 +-#define CLK_TOP_RG_ETH 101 +-#define CLK_TOP_RG_AUD1 102 +-#define CLK_TOP_RG_AUD2 103 +-#define CLK_TOP_RG_AUD_ENGEN1 104 +-#define CLK_TOP_RG_AUD_ENGEN2 105 +-#define CLK_TOP_RG_I2C 106 +-#define CLK_TOP_RG_PWM_INFRA 107 +-#define CLK_TOP_RG_AUD_SPDIF_IN 108 +-#define CLK_TOP_RG_UART2 109 +-#define CLK_TOP_RG_BSI 110 +-#define CLK_TOP_RG_DBG_ATCLK 111 +-#define CLK_TOP_RG_NFIECC 112 +-#define CLK_TOP_RG_APLL1_D2_EN 113 +-#define CLK_TOP_RG_APLL1_D4_EN 114 +-#define CLK_TOP_RG_APLL1_D8_EN 115 +-#define CLK_TOP_RG_APLL2_D2_EN 116 +-#define CLK_TOP_RG_APLL2_D4_EN 117 +-#define CLK_TOP_RG_APLL2_D8_EN 118 +-#define CLK_TOP_APLL12_DIV0 119 +-#define CLK_TOP_APLL12_DIV1 120 +-#define CLK_TOP_APLL12_DIV2 121 +-#define CLK_TOP_APLL12_DIV3 122 +-#define CLK_TOP_APLL12_DIV4 123 +-#define CLK_TOP_APLL12_DIV4B 124 +-#define CLK_TOP_APLL12_DIV5 125 +-#define CLK_TOP_APLL12_DIV5B 126 +-#define CLK_TOP_APLL12_DIV6 127 +-#define CLK_TOP_UART0_SEL 128 +-#define CLK_TOP_EMI_DDRPHY_SEL 129 +-#define CLK_TOP_AHB_INFRA_SEL 130 +-#define CLK_TOP_MSDC0_SEL 131 +-#define CLK_TOP_UART1_SEL 132 +-#define CLK_TOP_MSDC1_SEL 133 +-#define CLK_TOP_PMICSPI_SEL 134 +-#define CLK_TOP_QAXI_AUD26M_SEL 135 +-#define CLK_TOP_AUD_INTBUS_SEL 136 +-#define CLK_TOP_NFI2X_PAD_SEL 137 +-#define CLK_TOP_NFI1X_PAD_SEL 138 +-#define CLK_TOP_DDRPHYCFG_SEL 139 +-#define CLK_TOP_USB_78M_SEL 140 +-#define CLK_TOP_SPINOR_SEL 141 +-#define CLK_TOP_MSDC2_SEL 142 +-#define CLK_TOP_ETH_SEL 143 +-#define CLK_TOP_AUD1_SEL 144 +-#define CLK_TOP_AUD2_SEL 145 +-#define CLK_TOP_AUD_ENGEN1_SEL 146 +-#define CLK_TOP_AUD_ENGEN2_SEL 147 +-#define CLK_TOP_I2C_SEL 148 +-#define CLK_TOP_AUD_I2S0_M_SEL 149 +-#define CLK_TOP_AUD_I2S1_M_SEL 150 +-#define CLK_TOP_AUD_I2S2_M_SEL 151 +-#define CLK_TOP_AUD_I2S3_M_SEL 152 +-#define CLK_TOP_AUD_I2S4_M_SEL 153 +-#define CLK_TOP_AUD_I2S5_M_SEL 154 +-#define CLK_TOP_AUD_SPDIF_B_SEL 155 +-#define CLK_TOP_PWM_SEL 156 +-#define CLK_TOP_SPI_SEL 157 +-#define CLK_TOP_AUD_SPDIFIN_SEL 158 +-#define CLK_TOP_UART2_SEL 159 +-#define CLK_TOP_BSI_SEL 160 +-#define CLK_TOP_DBG_ATCLK_SEL 161 +-#define CLK_TOP_CSW_NFIECC_SEL 162 +-#define CLK_TOP_NFIECC_SEL 163 +-#define CLK_TOP_APLL12_CK_DIV0 164 +-#define CLK_TOP_APLL12_CK_DIV1 165 +-#define CLK_TOP_APLL12_CK_DIV2 166 +-#define CLK_TOP_APLL12_CK_DIV3 167 +-#define CLK_TOP_APLL12_CK_DIV4 168 +-#define CLK_TOP_APLL12_CK_DIV4B 169 +-#define CLK_TOP_APLL12_CK_DIV5 170 +-#define CLK_TOP_APLL12_CK_DIV5B 171 +-#define CLK_TOP_APLL12_CK_DIV6 172 +-#define CLK_TOP_USB_78M 173 +-#define CLK_TOP_MSDC0_INFRA 174 +-#define CLK_TOP_MSDC1_INFRA 175 +-#define CLK_TOP_MSDC2_INFRA 176 +-#define CLK_TOP_NR_CLK 177 +- +-/* AUDSYS */ +- +-#define CLK_AUD_AFE 0 +-#define CLK_AUD_I2S 1 +-#define CLK_AUD_22M 2 +-#define CLK_AUD_24M 3 +-#define CLK_AUD_INTDIR 4 +-#define CLK_AUD_APLL2_TUNER 5 +-#define CLK_AUD_APLL_TUNER 6 +-#define CLK_AUD_HDMI 7 +-#define CLK_AUD_SPDF 8 +-#define CLK_AUD_ADC 9 +-#define CLK_AUD_DAC 10 +-#define CLK_AUD_DAC_PREDIS 11 +-#define CLK_AUD_TML 12 +-#define CLK_AUD_NR_CLK 13 +- +-#endif /* _DT_BINDINGS_CLK_MT8516_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/nuvoton,npcm7xx-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/nuvoton,npcm7xx-clock.h +deleted file mode 100644 +index f21522605b94..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/nuvoton,npcm7xx-clock.h ++++ /dev/null +@@ -1,44 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Nuvoton NPCM7xx Clock Generator binding +- * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk +- * +- * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com +- * +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H +-#define __DT_BINDINGS_CLOCK_NPCM7XX_H +- +- +-#define NPCM7XX_CLK_CPU 0 +-#define NPCM7XX_CLK_GFX_PIXEL 1 +-#define NPCM7XX_CLK_MC 2 +-#define NPCM7XX_CLK_ADC 3 +-#define NPCM7XX_CLK_AHB 4 +-#define NPCM7XX_CLK_TIMER 5 +-#define NPCM7XX_CLK_UART 6 +-#define NPCM7XX_CLK_MMC 7 +-#define NPCM7XX_CLK_SPI3 8 +-#define NPCM7XX_CLK_PCI 9 +-#define NPCM7XX_CLK_AXI 10 +-#define NPCM7XX_CLK_APB4 11 +-#define NPCM7XX_CLK_APB3 12 +-#define NPCM7XX_CLK_APB2 13 +-#define NPCM7XX_CLK_APB1 14 +-#define NPCM7XX_CLK_APB5 15 +-#define NPCM7XX_CLK_CLKOUT 16 +-#define NPCM7XX_CLK_GFX 17 +-#define NPCM7XX_CLK_SU 18 +-#define NPCM7XX_CLK_SU48 19 +-#define NPCM7XX_CLK_SDHC 20 +-#define NPCM7XX_CLK_SPI0 21 +-#define NPCM7XX_CLK_SPIX 22 +- +-#define NPCM7XX_CLK_REFCLK 23 +-#define NPCM7XX_CLK_SYSBYPCK 24 +-#define NPCM7XX_CLK_MCBYPCK 25 +- +-#define NPCM7XX_NUM_CLOCKS (NPCM7XX_CLK_MCBYPCK+1) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/omap4.h b/scripts/dtc/include-prefixes/dt-bindings/clock/omap4.h +deleted file mode 100644 +index 88d73be84b94..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/omap4.h ++++ /dev/null +@@ -1,149 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2017 Texas Instruments, Inc. +- */ +-#ifndef __DT_BINDINGS_CLK_OMAP4_H +-#define __DT_BINDINGS_CLK_OMAP4_H +- +-#define OMAP4_CLKCTRL_OFFSET 0x20 +-#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET) +- +-/* mpuss clocks */ +-#define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +- +-/* tesla clocks */ +-#define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +- +-/* abe clocks */ +-#define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +-#define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +-#define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +-#define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) +-#define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) +-#define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) +-#define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) +-#define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) +-#define OMAP4_SLIMBUS1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) +-#define OMAP4_TIMER5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) +-#define OMAP4_TIMER6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) +-#define OMAP4_TIMER7_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) +-#define OMAP4_TIMER8_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) +-#define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) +- +-/* l4_ao clocks */ +-#define OMAP4_SMARTREFLEX_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +-#define OMAP4_SMARTREFLEX_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +-#define OMAP4_SMARTREFLEX_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) +- +-/* l3_1 clocks */ +-#define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +- +-/* l3_2 clocks */ +-#define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +-#define OMAP4_GPMC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +-#define OMAP4_OCMC_RAM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +- +-/* ducati clocks */ +-#define OMAP4_IPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +- +-/* l3_dma clocks */ +-#define OMAP4_DMA_SYSTEM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +- +-/* l3_emif clocks */ +-#define OMAP4_DMM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +-#define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +-#define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) +- +-/* d2d clocks */ +-#define OMAP4_C2C_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +- +-/* l4_cfg clocks */ +-#define OMAP4_L4_CFG_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +-#define OMAP4_SPINLOCK_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +-#define OMAP4_MAILBOX_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +- +-/* l3_instr clocks */ +-#define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +-#define OMAP4_L3_INSTR_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +-#define OMAP4_OCP_WP_NOC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) +- +-/* ivahd clocks */ +-#define OMAP4_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +-#define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +- +-/* iss clocks */ +-#define OMAP4_ISS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +-#define OMAP4_FDIF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +- +-/* l3_dss clocks */ +-#define OMAP4_DSS_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +- +-/* l3_gfx clocks */ +-#define OMAP4_GPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +- +-/* l3_init clocks */ +-#define OMAP4_MMC1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +-#define OMAP4_MMC2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +-#define OMAP4_HSI_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) +-#define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) +-#define OMAP4_USB_OTG_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) +-#define OMAP4_USB_TLL_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) +-#define OMAP4_USB_HOST_FS_CLKCTRL OMAP4_CLKCTRL_INDEX(0xd0) +-#define OMAP4_OCP2SCP_USB_PHY_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) +- +-/* l4_per clocks */ +-#define OMAP4_TIMER10_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +-#define OMAP4_TIMER11_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +-#define OMAP4_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) +-#define OMAP4_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) +-#define OMAP4_TIMER4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) +-#define OMAP4_TIMER9_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) +-#define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) +-#define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) +-#define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) +-#define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) +-#define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) +-#define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) +-#define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) +-#define OMAP4_I2C1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa0) +-#define OMAP4_I2C2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa8) +-#define OMAP4_I2C3_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb0) +-#define OMAP4_I2C4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb8) +-#define OMAP4_L4_PER_CLKCTRL OMAP4_CLKCTRL_INDEX(0xc0) +-#define OMAP4_MCBSP4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) +-#define OMAP4_MCSPI1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf0) +-#define OMAP4_MCSPI2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf8) +-#define OMAP4_MCSPI3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x100) +-#define OMAP4_MCSPI4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x108) +-#define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x120) +-#define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x128) +-#define OMAP4_SLIMBUS2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x138) +-#define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x140) +-#define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148) +-#define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x150) +-#define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158) +-#define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160) +- +-/* l4_secure clocks */ +-#define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0 +-#define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET) +-#define OMAP4_AES1_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0) +-#define OMAP4_AES2_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8) +-#define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0) +-#define OMAP4_PKA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8) +-#define OMAP4_RNG_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0) +-#define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8) +-#define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8) +- +-/* l4_wkup clocks */ +-#define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +-#define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +-#define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) +-#define OMAP4_TIMER1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) +-#define OMAP4_COUNTER_32K_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) +-#define OMAP4_KBD_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) +- +-/* emu_sys clocks */ +-#define OMAP4_DEBUGSS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/omap5.h b/scripts/dtc/include-prefixes/dt-bindings/clock/omap5.h +deleted file mode 100644 +index 90e0d4b00127..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/omap5.h ++++ /dev/null +@@ -1,131 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2017 Texas Instruments, Inc. +- */ +-#ifndef __DT_BINDINGS_CLK_OMAP5_H +-#define __DT_BINDINGS_CLK_OMAP5_H +- +-#define OMAP5_CLKCTRL_OFFSET 0x20 +-#define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET) +- +-/* mpu clocks */ +-#define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +- +-/* dsp clocks */ +-#define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +- +-/* abe clocks */ +-#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +-#define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +-#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +-#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) +-#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) +-#define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) +-#define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) +-#define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) +-#define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) +-#define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) +-#define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) +- +-/* l3main1 clocks */ +-#define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +- +-/* l3main2 clocks */ +-#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +-#define OMAP5_L3_MAIN_2_GPMC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +-#define OMAP5_L3_MAIN_2_OCMC_RAM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +- +-/* ipu clocks */ +-#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +- +-/* dma clocks */ +-#define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +- +-/* emif clocks */ +-#define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +-#define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +-#define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) +- +-/* l4cfg clocks */ +-#define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +-#define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +-#define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +- +-/* l3instr clocks */ +-#define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +-#define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +- +-/* l4per clocks */ +-#define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +-#define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +-#define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) +-#define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) +-#define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) +-#define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) +-#define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60) +-#define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) +-#define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) +-#define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) +-#define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) +-#define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0) +-#define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8) +-#define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0) +-#define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8) +-#define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0) +-#define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) +-#define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8) +-#define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100) +-#define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108) +-#define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110) +-#define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118) +-#define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120) +-#define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128) +-#define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140) +-#define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148) +-#define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150) +-#define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158) +-#define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160) +-#define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168) +-#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) +-#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) +- +-/* l4_secure clocks */ +-#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0 +-#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET) +-#define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0) +-#define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8) +-#define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0) +-#define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8) +-#define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0) +-#define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8) +-#define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8) +- +-/* iva clocks */ +-#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +-#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +- +-/* dss clocks */ +-#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +- +-/* gpu clocks */ +-#define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +- +-/* l3init clocks */ +-#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +-#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +-#define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) +-#define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) +-#define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88) +-#define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0) +-#define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8) +-#define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) +- +-/* wkupaon clocks */ +-#define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +-#define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +-#define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) +-#define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) +-#define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) +-#define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/oxsemi,ox810se.h b/scripts/dtc/include-prefixes/dt-bindings/clock/oxsemi,ox810se.h +deleted file mode 100644 +index 7256365160f8..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/oxsemi,ox810se.h ++++ /dev/null +@@ -1,19 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2016 Neil Armstrong +- */ +- +-#ifndef DT_CLOCK_OXSEMI_OX810SE_H +-#define DT_CLOCK_OXSEMI_OX810SE_H +- +-#define CLK_810_LEON 0 +-#define CLK_810_DMA_SGDMA 1 +-#define CLK_810_CIPHER 2 +-#define CLK_810_SATA 3 +-#define CLK_810_AUDIO 4 +-#define CLK_810_USBMPH 5 +-#define CLK_810_ETHA 6 +-#define CLK_810_PCIEA 7 +-#define CLK_810_NAND 8 +- +-#endif /* DT_CLOCK_OXSEMI_OX810SE_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/oxsemi,ox820.h b/scripts/dtc/include-prefixes/dt-bindings/clock/oxsemi,ox820.h +deleted file mode 100644 +index 55f4226e2f3f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/oxsemi,ox820.h ++++ /dev/null +@@ -1,29 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2016 Neil Armstrong +- */ +- +-#ifndef DT_CLOCK_OXSEMI_OX820_H +-#define DT_CLOCK_OXSEMI_OX820_H +- +-/* PLLs */ +-#define CLK_820_PLLA 0 +-#define CLK_820_PLLB 1 +- +-/* Gate Clocks */ +-#define CLK_820_LEON 2 +-#define CLK_820_DMA_SGDMA 3 +-#define CLK_820_CIPHER 4 +-#define CLK_820_SD 5 +-#define CLK_820_SATA 6 +-#define CLK_820_AUDIO 7 +-#define CLK_820_USBMPH 8 +-#define CLK_820_ETHA 9 +-#define CLK_820_PCIEA 10 +-#define CLK_820_NAND 11 +-#define CLK_820_PCIEB 12 +-#define CLK_820_ETHB 13 +-#define CLK_820_REF600 14 +-#define CLK_820_USBDEV 15 +- +-#endif /* DT_CLOCK_OXSEMI_OX820_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/pistachio-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/pistachio-clk.h +deleted file mode 100644 +index ec7a8683f3e8..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/pistachio-clk.h ++++ /dev/null +@@ -1,180 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2014 Google, Inc. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_PISTACHIO_H +-#define _DT_BINDINGS_CLOCK_PISTACHIO_H +- +-/* PLLs */ +-#define CLK_MIPS_PLL 0 +-#define CLK_AUDIO_PLL 1 +-#define CLK_RPU_V_PLL 2 +-#define CLK_RPU_L_PLL 3 +-#define CLK_SYS_PLL 4 +-#define CLK_WIFI_PLL 5 +-#define CLK_BT_PLL 6 +- +-/* Fixed-factor clocks */ +-#define CLK_WIFI_DIV4 16 +-#define CLK_WIFI_DIV8 17 +- +-/* Gate clocks */ +-#define CLK_MIPS 32 +-#define CLK_AUDIO_IN 33 +-#define CLK_AUDIO 34 +-#define CLK_I2S 35 +-#define CLK_SPDIF 36 +-#define CLK_AUDIO_DAC 37 +-#define CLK_RPU_V 38 +-#define CLK_RPU_L 39 +-#define CLK_RPU_SLEEP 40 +-#define CLK_WIFI_PLL_GATE 41 +-#define CLK_RPU_CORE 42 +-#define CLK_WIFI_ADC 43 +-#define CLK_WIFI_DAC 44 +-#define CLK_USB_PHY 45 +-#define CLK_ENET_IN 46 +-#define CLK_ENET 47 +-#define CLK_UART0 48 +-#define CLK_UART1 49 +-#define CLK_PERIPH_SYS 50 +-#define CLK_SPI0 51 +-#define CLK_SPI1 52 +-#define CLK_EVENT_TIMER 53 +-#define CLK_AUX_ADC_INTERNAL 54 +-#define CLK_AUX_ADC 55 +-#define CLK_SD_HOST 56 +-#define CLK_BT 57 +-#define CLK_BT_DIV4 58 +-#define CLK_BT_DIV8 59 +-#define CLK_BT_1MHZ 60 +- +-/* Divider clocks */ +-#define CLK_MIPS_INTERNAL_DIV 64 +-#define CLK_MIPS_DIV 65 +-#define CLK_AUDIO_DIV 66 +-#define CLK_I2S_DIV 67 +-#define CLK_SPDIF_DIV 68 +-#define CLK_AUDIO_DAC_DIV 69 +-#define CLK_RPU_V_DIV 70 +-#define CLK_RPU_L_DIV 71 +-#define CLK_RPU_SLEEP_DIV 72 +-#define CLK_RPU_CORE_DIV 73 +-#define CLK_USB_PHY_DIV 74 +-#define CLK_ENET_DIV 75 +-#define CLK_UART0_INTERNAL_DIV 76 +-#define CLK_UART0_DIV 77 +-#define CLK_UART1_INTERNAL_DIV 78 +-#define CLK_UART1_DIV 79 +-#define CLK_SYS_INTERNAL_DIV 80 +-#define CLK_SPI0_INTERNAL_DIV 81 +-#define CLK_SPI0_DIV 82 +-#define CLK_SPI1_INTERNAL_DIV 83 +-#define CLK_SPI1_DIV 84 +-#define CLK_EVENT_TIMER_INTERNAL_DIV 85 +-#define CLK_EVENT_TIMER_DIV 86 +-#define CLK_AUX_ADC_INTERNAL_DIV 87 +-#define CLK_AUX_ADC_DIV 88 +-#define CLK_SD_HOST_DIV 89 +-#define CLK_BT_DIV 90 +-#define CLK_BT_DIV4_DIV 91 +-#define CLK_BT_DIV8_DIV 92 +-#define CLK_BT_1MHZ_INTERNAL_DIV 93 +-#define CLK_BT_1MHZ_DIV 94 +- +-/* Mux clocks */ +-#define CLK_AUDIO_REF_MUX 96 +-#define CLK_MIPS_PLL_MUX 97 +-#define CLK_AUDIO_PLL_MUX 98 +-#define CLK_AUDIO_MUX 99 +-#define CLK_RPU_V_PLL_MUX 100 +-#define CLK_RPU_L_PLL_MUX 101 +-#define CLK_RPU_L_MUX 102 +-#define CLK_WIFI_PLL_MUX 103 +-#define CLK_WIFI_DIV4_MUX 104 +-#define CLK_WIFI_DIV8_MUX 105 +-#define CLK_RPU_CORE_MUX 106 +-#define CLK_SYS_PLL_MUX 107 +-#define CLK_ENET_MUX 108 +-#define CLK_EVENT_TIMER_MUX 109 +-#define CLK_SD_HOST_MUX 110 +-#define CLK_BT_PLL_MUX 111 +-#define CLK_DEBUG_MUX 112 +- +-#define CLK_NR_CLKS 113 +- +-/* Peripheral gate clocks */ +-#define PERIPH_CLK_SYS 0 +-#define PERIPH_CLK_SYS_BUS 1 +-#define PERIPH_CLK_DDR 2 +-#define PERIPH_CLK_ROM 3 +-#define PERIPH_CLK_COUNTER_FAST 4 +-#define PERIPH_CLK_COUNTER_SLOW 5 +-#define PERIPH_CLK_IR 6 +-#define PERIPH_CLK_WD 7 +-#define PERIPH_CLK_PDM 8 +-#define PERIPH_CLK_PWM 9 +-#define PERIPH_CLK_I2C0 10 +-#define PERIPH_CLK_I2C1 11 +-#define PERIPH_CLK_I2C2 12 +-#define PERIPH_CLK_I2C3 13 +- +-/* Peripheral divider clocks */ +-#define PERIPH_CLK_ROM_DIV 32 +-#define PERIPH_CLK_COUNTER_FAST_DIV 33 +-#define PERIPH_CLK_COUNTER_SLOW_PRE_DIV 34 +-#define PERIPH_CLK_COUNTER_SLOW_DIV 35 +-#define PERIPH_CLK_IR_PRE_DIV 36 +-#define PERIPH_CLK_IR_DIV 37 +-#define PERIPH_CLK_WD_PRE_DIV 38 +-#define PERIPH_CLK_WD_DIV 39 +-#define PERIPH_CLK_PDM_PRE_DIV 40 +-#define PERIPH_CLK_PDM_DIV 41 +-#define PERIPH_CLK_PWM_PRE_DIV 42 +-#define PERIPH_CLK_PWM_DIV 43 +-#define PERIPH_CLK_I2C0_PRE_DIV 44 +-#define PERIPH_CLK_I2C0_DIV 45 +-#define PERIPH_CLK_I2C1_PRE_DIV 46 +-#define PERIPH_CLK_I2C1_DIV 47 +-#define PERIPH_CLK_I2C2_PRE_DIV 48 +-#define PERIPH_CLK_I2C2_DIV 49 +-#define PERIPH_CLK_I2C3_PRE_DIV 50 +-#define PERIPH_CLK_I2C3_DIV 51 +- +-#define PERIPH_CLK_NR_CLKS 52 +- +-/* System gate clocks */ +-#define SYS_CLK_I2C0 0 +-#define SYS_CLK_I2C1 1 +-#define SYS_CLK_I2C2 2 +-#define SYS_CLK_I2C3 3 +-#define SYS_CLK_I2S_IN 4 +-#define SYS_CLK_PAUD_OUT 5 +-#define SYS_CLK_SPDIF_OUT 6 +-#define SYS_CLK_SPI0_MASTER 7 +-#define SYS_CLK_SPI0_SLAVE 8 +-#define SYS_CLK_PWM 9 +-#define SYS_CLK_UART0 10 +-#define SYS_CLK_UART1 11 +-#define SYS_CLK_SPI1 12 +-#define SYS_CLK_MDC 13 +-#define SYS_CLK_SD_HOST 14 +-#define SYS_CLK_ENET 15 +-#define SYS_CLK_IR 16 +-#define SYS_CLK_WD 17 +-#define SYS_CLK_TIMER 18 +-#define SYS_CLK_I2S_OUT 24 +-#define SYS_CLK_SPDIF_IN 25 +-#define SYS_CLK_EVENT_TIMER 26 +-#define SYS_CLK_HASH 27 +- +-#define SYS_CLK_NR_CLKS 28 +- +-/* Gates for external input clocks */ +-#define EXT_CLK_AUDIO_IN 0 +-#define EXT_CLK_ENET_IN 1 +- +-#define EXT_CLK_NR_CLKS 2 +- +-#endif /* _DT_BINDINGS_CLOCK_PISTACHIO_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/px30-cru.h b/scripts/dtc/include-prefixes/dt-bindings/clock/px30-cru.h +deleted file mode 100644 +index 5b1416fcde6f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/px30-cru.h ++++ /dev/null +@@ -1,391 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +- +-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H +-#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H +- +-/* core clocks */ +-#define PLL_APLL 1 +-#define PLL_DPLL 2 +-#define PLL_CPLL 3 +-#define PLL_NPLL 4 +-#define APLL_BOOST_H 5 +-#define APLL_BOOST_L 6 +-#define ARMCLK 7 +- +-/* sclk gates (special clocks) */ +-#define USB480M 14 +-#define SCLK_PDM 15 +-#define SCLK_I2S0_TX 16 +-#define SCLK_I2S0_TX_OUT 17 +-#define SCLK_I2S0_RX 18 +-#define SCLK_I2S0_RX_OUT 19 +-#define SCLK_I2S1 20 +-#define SCLK_I2S1_OUT 21 +-#define SCLK_I2S2 22 +-#define SCLK_I2S2_OUT 23 +-#define SCLK_UART1 24 +-#define SCLK_UART2 25 +-#define SCLK_UART3 26 +-#define SCLK_UART4 27 +-#define SCLK_UART5 28 +-#define SCLK_I2C0 29 +-#define SCLK_I2C1 30 +-#define SCLK_I2C2 31 +-#define SCLK_I2C3 32 +-#define SCLK_I2C4 33 +-#define SCLK_PWM0 34 +-#define SCLK_PWM1 35 +-#define SCLK_SPI0 36 +-#define SCLK_SPI1 37 +-#define SCLK_TIMER0 38 +-#define SCLK_TIMER1 39 +-#define SCLK_TIMER2 40 +-#define SCLK_TIMER3 41 +-#define SCLK_TIMER4 42 +-#define SCLK_TIMER5 43 +-#define SCLK_TSADC 44 +-#define SCLK_SARADC 45 +-#define SCLK_OTP 46 +-#define SCLK_OTP_USR 47 +-#define SCLK_CRYPTO 48 +-#define SCLK_CRYPTO_APK 49 +-#define SCLK_DDRC 50 +-#define SCLK_ISP 51 +-#define SCLK_CIF_OUT 52 +-#define SCLK_RGA_CORE 53 +-#define SCLK_VOPB_PWM 54 +-#define SCLK_NANDC 55 +-#define SCLK_SDIO 56 +-#define SCLK_EMMC 57 +-#define SCLK_SFC 58 +-#define SCLK_SDMMC 59 +-#define SCLK_OTG_ADP 60 +-#define SCLK_GMAC_SRC 61 +-#define SCLK_GMAC 62 +-#define SCLK_GMAC_RX_TX 63 +-#define SCLK_MAC_REF 64 +-#define SCLK_MAC_REFOUT 65 +-#define SCLK_MAC_OUT 66 +-#define SCLK_SDMMC_DRV 67 +-#define SCLK_SDMMC_SAMPLE 68 +-#define SCLK_SDIO_DRV 69 +-#define SCLK_SDIO_SAMPLE 70 +-#define SCLK_EMMC_DRV 71 +-#define SCLK_EMMC_SAMPLE 72 +-#define SCLK_GPU 73 +-#define SCLK_PVTM 74 +-#define SCLK_CORE_VPU 75 +-#define SCLK_GMAC_RMII 76 +-#define SCLK_UART2_SRC 77 +-#define SCLK_NANDC_DIV 78 +-#define SCLK_NANDC_DIV50 79 +-#define SCLK_SDIO_DIV 80 +-#define SCLK_SDIO_DIV50 81 +-#define SCLK_EMMC_DIV 82 +-#define SCLK_EMMC_DIV50 83 +-#define SCLK_DDRCLK 84 +-#define SCLK_UART1_SRC 85 +-#define SCLK_SDMMC_DIV 86 +-#define SCLK_SDMMC_DIV50 87 +- +-/* dclk gates */ +-#define DCLK_VOPB 150 +-#define DCLK_VOPL 151 +- +-/* aclk gates */ +-#define ACLK_GPU 170 +-#define ACLK_BUS_PRE 171 +-#define ACLK_CRYPTO 172 +-#define ACLK_VI_PRE 173 +-#define ACLK_VO_PRE 174 +-#define ACLK_VPU 175 +-#define ACLK_PERI_PRE 176 +-#define ACLK_GMAC 178 +-#define ACLK_CIF 179 +-#define ACLK_ISP 180 +-#define ACLK_VOPB 181 +-#define ACLK_VOPL 182 +-#define ACLK_RGA 183 +-#define ACLK_GIC 184 +-#define ACLK_DCF 186 +-#define ACLK_DMAC 187 +-#define ACLK_BUS_SRC 188 +-#define ACLK_PERI_SRC 189 +- +-/* hclk gates */ +-#define HCLK_BUS_PRE 240 +-#define HCLK_CRYPTO 241 +-#define HCLK_VI_PRE 242 +-#define HCLK_VO_PRE 243 +-#define HCLK_VPU 244 +-#define HCLK_PERI_PRE 245 +-#define HCLK_MMC_NAND 246 +-#define HCLK_SDMMC 247 +-#define HCLK_USB 248 +-#define HCLK_CIF 249 +-#define HCLK_ISP 250 +-#define HCLK_VOPB 251 +-#define HCLK_VOPL 252 +-#define HCLK_RGA 253 +-#define HCLK_NANDC 254 +-#define HCLK_SDIO 255 +-#define HCLK_EMMC 256 +-#define HCLK_SFC 257 +-#define HCLK_OTG 258 +-#define HCLK_HOST 259 +-#define HCLK_HOST_ARB 260 +-#define HCLK_PDM 261 +-#define HCLK_I2S0 262 +-#define HCLK_I2S1 263 +-#define HCLK_I2S2 264 +- +-/* pclk gates */ +-#define PCLK_BUS_PRE 320 +-#define PCLK_DDR 321 +-#define PCLK_VO_PRE 322 +-#define PCLK_GMAC 323 +-#define PCLK_MIPI_DSI 324 +-#define PCLK_MIPIDSIPHY 325 +-#define PCLK_MIPICSIPHY 326 +-#define PCLK_USB_GRF 327 +-#define PCLK_DCF 328 +-#define PCLK_UART1 329 +-#define PCLK_UART2 330 +-#define PCLK_UART3 331 +-#define PCLK_UART4 332 +-#define PCLK_UART5 333 +-#define PCLK_I2C0 334 +-#define PCLK_I2C1 335 +-#define PCLK_I2C2 336 +-#define PCLK_I2C3 337 +-#define PCLK_I2C4 338 +-#define PCLK_PWM0 339 +-#define PCLK_PWM1 340 +-#define PCLK_SPI0 341 +-#define PCLK_SPI1 342 +-#define PCLK_SARADC 343 +-#define PCLK_TSADC 344 +-#define PCLK_TIMER 345 +-#define PCLK_OTP_NS 346 +-#define PCLK_WDT_NS 347 +-#define PCLK_GPIO1 348 +-#define PCLK_GPIO2 349 +-#define PCLK_GPIO3 350 +-#define PCLK_ISP 351 +-#define PCLK_CIF 352 +-#define PCLK_OTP_PHY 353 +- +-#define CLK_NR_CLKS (PCLK_OTP_PHY + 1) +- +-/* pmu-clocks indices */ +- +-#define PLL_GPLL 1 +- +-#define SCLK_RTC32K_PMU 4 +-#define SCLK_WIFI_PMU 5 +-#define SCLK_UART0_PMU 6 +-#define SCLK_PVTM_PMU 7 +-#define PCLK_PMU_PRE 8 +-#define SCLK_REF24M_PMU 9 +-#define SCLK_USBPHY_REF 10 +-#define SCLK_MIPIDSIPHY_REF 11 +- +-#define XIN24M_DIV 12 +- +-#define PCLK_GPIO0_PMU 20 +-#define PCLK_UART0_PMU 21 +- +-#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1) +- +-/* soft-reset indices */ +-#define SRST_CORE0_PO 0 +-#define SRST_CORE1_PO 1 +-#define SRST_CORE2_PO 2 +-#define SRST_CORE3_PO 3 +-#define SRST_CORE0 4 +-#define SRST_CORE1 5 +-#define SRST_CORE2 6 +-#define SRST_CORE3 7 +-#define SRST_CORE0_DBG 8 +-#define SRST_CORE1_DBG 9 +-#define SRST_CORE2_DBG 10 +-#define SRST_CORE3_DBG 11 +-#define SRST_TOPDBG 12 +-#define SRST_CORE_NOC 13 +-#define SRST_STRC_A 14 +-#define SRST_L2C 15 +- +-#define SRST_DAP 16 +-#define SRST_CORE_PVTM 17 +-#define SRST_GPU 18 +-#define SRST_GPU_NIU 19 +-#define SRST_UPCTL2 20 +-#define SRST_UPCTL2_A 21 +-#define SRST_UPCTL2_P 22 +-#define SRST_MSCH 23 +-#define SRST_MSCH_P 24 +-#define SRST_DDRMON_P 25 +-#define SRST_DDRSTDBY_P 26 +-#define SRST_DDRSTDBY 27 +-#define SRST_DDRGRF_p 28 +-#define SRST_AXI_SPLIT_A 29 +-#define SRST_AXI_CMD_A 30 +-#define SRST_AXI_CMD_P 31 +- +-#define SRST_DDRPHY 32 +-#define SRST_DDRPHYDIV 33 +-#define SRST_DDRPHY_P 34 +-#define SRST_VPU_A 36 +-#define SRST_VPU_NIU_A 37 +-#define SRST_VPU_H 38 +-#define SRST_VPU_NIU_H 39 +-#define SRST_VI_NIU_A 40 +-#define SRST_VI_NIU_H 41 +-#define SRST_ISP_H 42 +-#define SRST_ISP 43 +-#define SRST_CIF_A 44 +-#define SRST_CIF_H 45 +-#define SRST_CIF_PCLKIN 46 +-#define SRST_MIPICSIPHY_P 47 +- +-#define SRST_VO_NIU_A 48 +-#define SRST_VO_NIU_H 49 +-#define SRST_VO_NIU_P 50 +-#define SRST_VOPB_A 51 +-#define SRST_VOPB_H 52 +-#define SRST_VOPB 53 +-#define SRST_PWM_VOPB 54 +-#define SRST_VOPL_A 55 +-#define SRST_VOPL_H 56 +-#define SRST_VOPL 57 +-#define SRST_RGA_A 58 +-#define SRST_RGA_H 59 +-#define SRST_RGA 60 +-#define SRST_MIPIDSI_HOST_P 61 +-#define SRST_MIPIDSIPHY_P 62 +-#define SRST_VPU_CORE 63 +- +-#define SRST_PERI_NIU_A 64 +-#define SRST_USB_NIU_H 65 +-#define SRST_USB2OTG_H 66 +-#define SRST_USB2OTG 67 +-#define SRST_USB2OTG_ADP 68 +-#define SRST_USB2HOST_H 69 +-#define SRST_USB2HOST_ARB_H 70 +-#define SRST_USB2HOST_AUX_H 71 +-#define SRST_USB2HOST_EHCI 72 +-#define SRST_USB2HOST 73 +-#define SRST_USBPHYPOR 74 +-#define SRST_USBPHY_OTG_PORT 75 +-#define SRST_USBPHY_HOST_PORT 76 +-#define SRST_USBPHY_GRF 77 +-#define SRST_CPU_BOOST_P 78 +-#define SRST_CPU_BOOST 79 +- +-#define SRST_MMC_NAND_NIU_H 80 +-#define SRST_SDIO_H 81 +-#define SRST_EMMC_H 82 +-#define SRST_SFC_H 83 +-#define SRST_SFC 84 +-#define SRST_SDCARD_NIU_H 85 +-#define SRST_SDMMC_H 86 +-#define SRST_NANDC_H 89 +-#define SRST_NANDC 90 +-#define SRST_GMAC_NIU_A 92 +-#define SRST_GMAC_NIU_P 93 +-#define SRST_GMAC_A 94 +- +-#define SRST_PMU_NIU_P 96 +-#define SRST_PMU_SGRF_P 97 +-#define SRST_PMU_GRF_P 98 +-#define SRST_PMU 99 +-#define SRST_PMU_MEM_P 100 +-#define SRST_PMU_GPIO0_P 101 +-#define SRST_PMU_UART0_P 102 +-#define SRST_PMU_CRU_P 103 +-#define SRST_PMU_PVTM 104 +-#define SRST_PMU_UART 105 +-#define SRST_PMU_NIU_H 106 +-#define SRST_PMU_DDR_FAIL_SAVE 107 +-#define SRST_PMU_CORE_PERF_A 108 +-#define SRST_PMU_CORE_GRF_P 109 +-#define SRST_PMU_GPU_PERF_A 110 +-#define SRST_PMU_GPU_GRF_P 111 +- +-#define SRST_CRYPTO_NIU_A 112 +-#define SRST_CRYPTO_NIU_H 113 +-#define SRST_CRYPTO_A 114 +-#define SRST_CRYPTO_H 115 +-#define SRST_CRYPTO 116 +-#define SRST_CRYPTO_APK 117 +-#define SRST_BUS_NIU_H 120 +-#define SRST_USB_NIU_P 121 +-#define SRST_BUS_TOP_NIU_P 122 +-#define SRST_INTMEM_A 123 +-#define SRST_GIC_A 124 +-#define SRST_ROM_H 126 +-#define SRST_DCF_A 127 +- +-#define SRST_DCF_P 128 +-#define SRST_PDM_H 129 +-#define SRST_PDM 130 +-#define SRST_I2S0_H 131 +-#define SRST_I2S0_TX 132 +-#define SRST_I2S1_H 133 +-#define SRST_I2S1 134 +-#define SRST_I2S2_H 135 +-#define SRST_I2S2 136 +-#define SRST_UART1_P 137 +-#define SRST_UART1 138 +-#define SRST_UART2_P 139 +-#define SRST_UART2 140 +-#define SRST_UART3_P 141 +-#define SRST_UART3 142 +-#define SRST_UART4_P 143 +- +-#define SRST_UART4 144 +-#define SRST_UART5_P 145 +-#define SRST_UART5 146 +-#define SRST_I2C0_P 147 +-#define SRST_I2C0 148 +-#define SRST_I2C1_P 149 +-#define SRST_I2C1 150 +-#define SRST_I2C2_P 151 +-#define SRST_I2C2 152 +-#define SRST_I2C3_P 153 +-#define SRST_I2C3 154 +-#define SRST_PWM0_P 157 +-#define SRST_PWM0 158 +-#define SRST_PWM1_P 159 +- +-#define SRST_PWM1 160 +-#define SRST_SPI0_P 161 +-#define SRST_SPI0 162 +-#define SRST_SPI1_P 163 +-#define SRST_SPI1 164 +-#define SRST_SARADC_P 165 +-#define SRST_SARADC 166 +-#define SRST_TSADC_P 167 +-#define SRST_TSADC 168 +-#define SRST_TIMER_P 169 +-#define SRST_TIMER0 170 +-#define SRST_TIMER1 171 +-#define SRST_TIMER2 172 +-#define SRST_TIMER3 173 +-#define SRST_TIMER4 174 +-#define SRST_TIMER5 175 +- +-#define SRST_OTP_NS_P 176 +-#define SRST_OTP_NS_SBPI 177 +-#define SRST_OTP_NS_USR 178 +-#define SRST_OTP_PHY_P 179 +-#define SRST_OTP_PHY 180 +-#define SRST_WDT_NS_P 181 +-#define SRST_GPIO1_P 182 +-#define SRST_GPIO2_P 183 +-#define SRST_GPIO3_P 184 +-#define SRST_SGRF_P 185 +-#define SRST_GRF_P 186 +-#define SRST_I2S0_RX 191 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/pxa-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/pxa-clock.h +deleted file mode 100644 +index ce3d6b6a2e4f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/pxa-clock.h ++++ /dev/null +@@ -1,74 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Inspired by original work from pxa2xx-regs.h by Nicolas Pitre +- * Copyright (C) 2014 Robert Jarzmik +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_PXA2XX_H__ +-#define __DT_BINDINGS_CLOCK_PXA2XX_H__ +- +-#define CLK_NONE 0 +-#define CLK_1WIRE 1 +-#define CLK_AC97 2 +-#define CLK_AC97CONF 3 +-#define CLK_ASSP 4 +-#define CLK_BOOT 5 +-#define CLK_BTUART 6 +-#define CLK_CAMERA 7 +-#define CLK_CIR 8 +-#define CLK_CORE 9 +-#define CLK_DMC 10 +-#define CLK_FFUART 11 +-#define CLK_FICP 12 +-#define CLK_GPIO 13 +-#define CLK_HSIO2 14 +-#define CLK_HWUART 15 +-#define CLK_I2C 16 +-#define CLK_I2S 17 +-#define CLK_IM 18 +-#define CLK_INC 19 +-#define CLK_ISC 20 +-#define CLK_KEYPAD 21 +-#define CLK_LCD 22 +-#define CLK_MEMC 23 +-#define CLK_MEMSTK 24 +-#define CLK_MINI_IM 25 +-#define CLK_MINI_LCD 26 +-#define CLK_MMC 27 +-#define CLK_MMC1 28 +-#define CLK_MMC2 29 +-#define CLK_MMC3 30 +-#define CLK_MSL 31 +-#define CLK_MSL0 32 +-#define CLK_MVED 33 +-#define CLK_NAND 34 +-#define CLK_NSSP 35 +-#define CLK_OSTIMER 36 +-#define CLK_PWM0 37 +-#define CLK_PWM1 38 +-#define CLK_PWM2 39 +-#define CLK_PWM3 40 +-#define CLK_PWRI2C 41 +-#define CLK_PXA300_GCU 42 +-#define CLK_PXA320_GCU 43 +-#define CLK_SMC 44 +-#define CLK_SSP 45 +-#define CLK_SSP1 46 +-#define CLK_SSP2 47 +-#define CLK_SSP3 48 +-#define CLK_SSP4 49 +-#define CLK_STUART 50 +-#define CLK_TOUCH 51 +-#define CLK_TPM 52 +-#define CLK_UDC 53 +-#define CLK_USB 54 +-#define CLK_USB2 55 +-#define CLK_USBH 56 +-#define CLK_USBHOST 57 +-#define CLK_USIM 58 +-#define CLK_USIM1 59 +-#define CLK_USMI0 60 +-#define CLK_OSC32k768 61 +-#define CLK_MAX 62 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,apss-ipq.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,apss-ipq.h +deleted file mode 100644 +index 77b6e05492e2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,apss-ipq.h ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2018, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H +-#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H +- +-#define APCS_ALIAS0_CLK_SRC 0 +-#define APCS_ALIAS0_CORE_CLK 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,camcc-sc7180.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,camcc-sc7180.h +deleted file mode 100644 +index ef7d3a041b88..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,camcc-sc7180.h ++++ /dev/null +@@ -1,121 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SC7180_H +-#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SC7180_H +- +-/* CAM_CC clocks */ +-#define CAM_CC_PLL2_OUT_EARLY 0 +-#define CAM_CC_PLL0 1 +-#define CAM_CC_PLL1 2 +-#define CAM_CC_PLL2 3 +-#define CAM_CC_PLL2_OUT_AUX 4 +-#define CAM_CC_PLL3 5 +-#define CAM_CC_CAMNOC_AXI_CLK 6 +-#define CAM_CC_CCI_0_CLK 7 +-#define CAM_CC_CCI_0_CLK_SRC 8 +-#define CAM_CC_CCI_1_CLK 9 +-#define CAM_CC_CCI_1_CLK_SRC 10 +-#define CAM_CC_CORE_AHB_CLK 11 +-#define CAM_CC_CPAS_AHB_CLK 12 +-#define CAM_CC_CPHY_RX_CLK_SRC 13 +-#define CAM_CC_CSI0PHYTIMER_CLK 14 +-#define CAM_CC_CSI0PHYTIMER_CLK_SRC 15 +-#define CAM_CC_CSI1PHYTIMER_CLK 16 +-#define CAM_CC_CSI1PHYTIMER_CLK_SRC 17 +-#define CAM_CC_CSI2PHYTIMER_CLK 18 +-#define CAM_CC_CSI2PHYTIMER_CLK_SRC 19 +-#define CAM_CC_CSI3PHYTIMER_CLK 20 +-#define CAM_CC_CSI3PHYTIMER_CLK_SRC 21 +-#define CAM_CC_CSIPHY0_CLK 22 +-#define CAM_CC_CSIPHY1_CLK 23 +-#define CAM_CC_CSIPHY2_CLK 24 +-#define CAM_CC_CSIPHY3_CLK 25 +-#define CAM_CC_FAST_AHB_CLK_SRC 26 +-#define CAM_CC_ICP_APB_CLK 27 +-#define CAM_CC_ICP_ATB_CLK 28 +-#define CAM_CC_ICP_CLK 29 +-#define CAM_CC_ICP_CLK_SRC 30 +-#define CAM_CC_ICP_CTI_CLK 31 +-#define CAM_CC_ICP_TS_CLK 32 +-#define CAM_CC_IFE_0_AXI_CLK 33 +-#define CAM_CC_IFE_0_CLK 34 +-#define CAM_CC_IFE_0_CLK_SRC 35 +-#define CAM_CC_IFE_0_CPHY_RX_CLK 36 +-#define CAM_CC_IFE_0_CSID_CLK 37 +-#define CAM_CC_IFE_0_CSID_CLK_SRC 38 +-#define CAM_CC_IFE_0_DSP_CLK 39 +-#define CAM_CC_IFE_1_AXI_CLK 40 +-#define CAM_CC_IFE_1_CLK 41 +-#define CAM_CC_IFE_1_CLK_SRC 42 +-#define CAM_CC_IFE_1_CPHY_RX_CLK 43 +-#define CAM_CC_IFE_1_CSID_CLK 44 +-#define CAM_CC_IFE_1_CSID_CLK_SRC 45 +-#define CAM_CC_IFE_1_DSP_CLK 46 +-#define CAM_CC_IFE_LITE_CLK 47 +-#define CAM_CC_IFE_LITE_CLK_SRC 48 +-#define CAM_CC_IFE_LITE_CPHY_RX_CLK 49 +-#define CAM_CC_IFE_LITE_CSID_CLK 50 +-#define CAM_CC_IFE_LITE_CSID_CLK_SRC 51 +-#define CAM_CC_IPE_0_AHB_CLK 52 +-#define CAM_CC_IPE_0_AREG_CLK 53 +-#define CAM_CC_IPE_0_AXI_CLK 54 +-#define CAM_CC_IPE_0_CLK 55 +-#define CAM_CC_IPE_0_CLK_SRC 56 +-#define CAM_CC_JPEG_CLK 57 +-#define CAM_CC_JPEG_CLK_SRC 58 +-#define CAM_CC_LRME_CLK 59 +-#define CAM_CC_LRME_CLK_SRC 60 +-#define CAM_CC_MCLK0_CLK 61 +-#define CAM_CC_MCLK0_CLK_SRC 62 +-#define CAM_CC_MCLK1_CLK 63 +-#define CAM_CC_MCLK1_CLK_SRC 64 +-#define CAM_CC_MCLK2_CLK 65 +-#define CAM_CC_MCLK2_CLK_SRC 66 +-#define CAM_CC_MCLK3_CLK 67 +-#define CAM_CC_MCLK3_CLK_SRC 68 +-#define CAM_CC_MCLK4_CLK 69 +-#define CAM_CC_MCLK4_CLK_SRC 70 +-#define CAM_CC_BPS_AHB_CLK 71 +-#define CAM_CC_BPS_AREG_CLK 72 +-#define CAM_CC_BPS_AXI_CLK 73 +-#define CAM_CC_BPS_CLK 74 +-#define CAM_CC_BPS_CLK_SRC 75 +-#define CAM_CC_SLOW_AHB_CLK_SRC 76 +-#define CAM_CC_SOC_AHB_CLK 77 +-#define CAM_CC_SYS_TMR_CLK 78 +- +-/* CAM_CC power domains */ +-#define BPS_GDSC 0 +-#define IFE_0_GDSC 1 +-#define IFE_1_GDSC 2 +-#define IPE_0_GDSC 3 +-#define TITAN_TOP_GDSC 4 +- +-/* CAM_CC resets */ +-#define CAM_CC_BPS_BCR 0 +-#define CAM_CC_CAMNOC_BCR 1 +-#define CAM_CC_CCI_0_BCR 2 +-#define CAM_CC_CCI_1_BCR 3 +-#define CAM_CC_CPAS_BCR 4 +-#define CAM_CC_CSI0PHY_BCR 5 +-#define CAM_CC_CSI1PHY_BCR 6 +-#define CAM_CC_CSI2PHY_BCR 7 +-#define CAM_CC_CSI3PHY_BCR 8 +-#define CAM_CC_ICP_BCR 9 +-#define CAM_CC_IFE_0_BCR 10 +-#define CAM_CC_IFE_1_BCR 11 +-#define CAM_CC_IFE_LITE_BCR 12 +-#define CAM_CC_IPE_0_BCR 13 +-#define CAM_CC_JPEG_BCR 14 +-#define CAM_CC_LRME_BCR 15 +-#define CAM_CC_MCLK0_BCR 16 +-#define CAM_CC_MCLK1_BCR 17 +-#define CAM_CC_MCLK2_BCR 18 +-#define CAM_CC_MCLK3_BCR 19 +-#define CAM_CC_MCLK4_BCR 20 +-#define CAM_CC_TITAN_TOP_BCR 21 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,camcc-sdm845.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,camcc-sdm845.h +deleted file mode 100644 +index 4f7a2d2320bf..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,camcc-sdm845.h ++++ /dev/null +@@ -1,116 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2018, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H +-#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H +- +-/* CAM_CC clock registers */ +-#define CAM_CC_BPS_AHB_CLK 0 +-#define CAM_CC_BPS_AREG_CLK 1 +-#define CAM_CC_BPS_AXI_CLK 2 +-#define CAM_CC_BPS_CLK 3 +-#define CAM_CC_BPS_CLK_SRC 4 +-#define CAM_CC_CAMNOC_ATB_CLK 5 +-#define CAM_CC_CAMNOC_AXI_CLK 6 +-#define CAM_CC_CCI_CLK 7 +-#define CAM_CC_CCI_CLK_SRC 8 +-#define CAM_CC_CPAS_AHB_CLK 9 +-#define CAM_CC_CPHY_RX_CLK_SRC 10 +-#define CAM_CC_CSI0PHYTIMER_CLK 11 +-#define CAM_CC_CSI0PHYTIMER_CLK_SRC 12 +-#define CAM_CC_CSI1PHYTIMER_CLK 13 +-#define CAM_CC_CSI1PHYTIMER_CLK_SRC 14 +-#define CAM_CC_CSI2PHYTIMER_CLK 15 +-#define CAM_CC_CSI2PHYTIMER_CLK_SRC 16 +-#define CAM_CC_CSI3PHYTIMER_CLK 17 +-#define CAM_CC_CSI3PHYTIMER_CLK_SRC 18 +-#define CAM_CC_CSIPHY0_CLK 19 +-#define CAM_CC_CSIPHY1_CLK 20 +-#define CAM_CC_CSIPHY2_CLK 21 +-#define CAM_CC_CSIPHY3_CLK 22 +-#define CAM_CC_FAST_AHB_CLK_SRC 23 +-#define CAM_CC_FD_CORE_CLK 24 +-#define CAM_CC_FD_CORE_CLK_SRC 25 +-#define CAM_CC_FD_CORE_UAR_CLK 26 +-#define CAM_CC_ICP_APB_CLK 27 +-#define CAM_CC_ICP_ATB_CLK 28 +-#define CAM_CC_ICP_CLK 29 +-#define CAM_CC_ICP_CLK_SRC 30 +-#define CAM_CC_ICP_CTI_CLK 31 +-#define CAM_CC_ICP_TS_CLK 32 +-#define CAM_CC_IFE_0_AXI_CLK 33 +-#define CAM_CC_IFE_0_CLK 34 +-#define CAM_CC_IFE_0_CLK_SRC 35 +-#define CAM_CC_IFE_0_CPHY_RX_CLK 36 +-#define CAM_CC_IFE_0_CSID_CLK 37 +-#define CAM_CC_IFE_0_CSID_CLK_SRC 38 +-#define CAM_CC_IFE_0_DSP_CLK 39 +-#define CAM_CC_IFE_1_AXI_CLK 40 +-#define CAM_CC_IFE_1_CLK 41 +-#define CAM_CC_IFE_1_CLK_SRC 42 +-#define CAM_CC_IFE_1_CPHY_RX_CLK 43 +-#define CAM_CC_IFE_1_CSID_CLK 44 +-#define CAM_CC_IFE_1_CSID_CLK_SRC 45 +-#define CAM_CC_IFE_1_DSP_CLK 46 +-#define CAM_CC_IFE_LITE_CLK 47 +-#define CAM_CC_IFE_LITE_CLK_SRC 48 +-#define CAM_CC_IFE_LITE_CPHY_RX_CLK 49 +-#define CAM_CC_IFE_LITE_CSID_CLK 50 +-#define CAM_CC_IFE_LITE_CSID_CLK_SRC 51 +-#define CAM_CC_IPE_0_AHB_CLK 52 +-#define CAM_CC_IPE_0_AREG_CLK 53 +-#define CAM_CC_IPE_0_AXI_CLK 54 +-#define CAM_CC_IPE_0_CLK 55 +-#define CAM_CC_IPE_0_CLK_SRC 56 +-#define CAM_CC_IPE_1_AHB_CLK 57 +-#define CAM_CC_IPE_1_AREG_CLK 58 +-#define CAM_CC_IPE_1_AXI_CLK 59 +-#define CAM_CC_IPE_1_CLK 60 +-#define CAM_CC_IPE_1_CLK_SRC 61 +-#define CAM_CC_JPEG_CLK 62 +-#define CAM_CC_JPEG_CLK_SRC 63 +-#define CAM_CC_LRME_CLK 64 +-#define CAM_CC_LRME_CLK_SRC 65 +-#define CAM_CC_MCLK0_CLK 66 +-#define CAM_CC_MCLK0_CLK_SRC 67 +-#define CAM_CC_MCLK1_CLK 68 +-#define CAM_CC_MCLK1_CLK_SRC 69 +-#define CAM_CC_MCLK2_CLK 70 +-#define CAM_CC_MCLK2_CLK_SRC 71 +-#define CAM_CC_MCLK3_CLK 72 +-#define CAM_CC_MCLK3_CLK_SRC 73 +-#define CAM_CC_PLL0 74 +-#define CAM_CC_PLL0_OUT_EVEN 75 +-#define CAM_CC_PLL1 76 +-#define CAM_CC_PLL1_OUT_EVEN 77 +-#define CAM_CC_PLL2 78 +-#define CAM_CC_PLL2_OUT_EVEN 79 +-#define CAM_CC_PLL3 80 +-#define CAM_CC_PLL3_OUT_EVEN 81 +-#define CAM_CC_SLOW_AHB_CLK_SRC 82 +-#define CAM_CC_SOC_AHB_CLK 83 +-#define CAM_CC_SYS_TMR_CLK 84 +- +-/* CAM_CC Resets */ +-#define TITAN_CAM_CC_CCI_BCR 0 +-#define TITAN_CAM_CC_CPAS_BCR 1 +-#define TITAN_CAM_CC_CSI0PHY_BCR 2 +-#define TITAN_CAM_CC_CSI1PHY_BCR 3 +-#define TITAN_CAM_CC_CSI2PHY_BCR 4 +-#define TITAN_CAM_CC_MCLK0_BCR 5 +-#define TITAN_CAM_CC_MCLK1_BCR 6 +-#define TITAN_CAM_CC_MCLK2_BCR 7 +-#define TITAN_CAM_CC_MCLK3_BCR 8 +-#define TITAN_CAM_CC_TITAN_TOP_BCR 9 +- +-/* CAM_CC GDSCRs */ +-#define BPS_GDSC 0 +-#define IPE_0_GDSC 1 +-#define IPE_1_GDSC 2 +-#define IFE_0_GDSC 3 +-#define IFE_1_GDSC 4 +-#define TITAN_TOP_GDSC 5 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,camcc-sm8250.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,camcc-sm8250.h +deleted file mode 100644 +index 383ead17608d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,camcc-sm8250.h ++++ /dev/null +@@ -1,138 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8250_H +-#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8250_H +- +-/* CAM_CC clocks */ +-#define CAM_CC_BPS_AHB_CLK 0 +-#define CAM_CC_BPS_AREG_CLK 1 +-#define CAM_CC_BPS_AXI_CLK 2 +-#define CAM_CC_BPS_CLK 3 +-#define CAM_CC_BPS_CLK_SRC 4 +-#define CAM_CC_CAMNOC_AXI_CLK 5 +-#define CAM_CC_CAMNOC_AXI_CLK_SRC 6 +-#define CAM_CC_CAMNOC_DCD_XO_CLK 7 +-#define CAM_CC_CCI_0_CLK 8 +-#define CAM_CC_CCI_0_CLK_SRC 9 +-#define CAM_CC_CCI_1_CLK 10 +-#define CAM_CC_CCI_1_CLK_SRC 11 +-#define CAM_CC_CORE_AHB_CLK 12 +-#define CAM_CC_CPAS_AHB_CLK 13 +-#define CAM_CC_CPHY_RX_CLK_SRC 14 +-#define CAM_CC_CSI0PHYTIMER_CLK 15 +-#define CAM_CC_CSI0PHYTIMER_CLK_SRC 16 +-#define CAM_CC_CSI1PHYTIMER_CLK 17 +-#define CAM_CC_CSI1PHYTIMER_CLK_SRC 18 +-#define CAM_CC_CSI2PHYTIMER_CLK 19 +-#define CAM_CC_CSI2PHYTIMER_CLK_SRC 20 +-#define CAM_CC_CSI3PHYTIMER_CLK 21 +-#define CAM_CC_CSI3PHYTIMER_CLK_SRC 22 +-#define CAM_CC_CSI4PHYTIMER_CLK 23 +-#define CAM_CC_CSI4PHYTIMER_CLK_SRC 24 +-#define CAM_CC_CSI5PHYTIMER_CLK 25 +-#define CAM_CC_CSI5PHYTIMER_CLK_SRC 26 +-#define CAM_CC_CSIPHY0_CLK 27 +-#define CAM_CC_CSIPHY1_CLK 28 +-#define CAM_CC_CSIPHY2_CLK 29 +-#define CAM_CC_CSIPHY3_CLK 30 +-#define CAM_CC_CSIPHY4_CLK 31 +-#define CAM_CC_CSIPHY5_CLK 32 +-#define CAM_CC_FAST_AHB_CLK_SRC 33 +-#define CAM_CC_FD_CORE_CLK 34 +-#define CAM_CC_FD_CORE_CLK_SRC 35 +-#define CAM_CC_FD_CORE_UAR_CLK 36 +-#define CAM_CC_GDSC_CLK 37 +-#define CAM_CC_ICP_AHB_CLK 38 +-#define CAM_CC_ICP_CLK 39 +-#define CAM_CC_ICP_CLK_SRC 40 +-#define CAM_CC_IFE_0_AHB_CLK 41 +-#define CAM_CC_IFE_0_AREG_CLK 42 +-#define CAM_CC_IFE_0_AXI_CLK 43 +-#define CAM_CC_IFE_0_CLK 44 +-#define CAM_CC_IFE_0_CLK_SRC 45 +-#define CAM_CC_IFE_0_CPHY_RX_CLK 46 +-#define CAM_CC_IFE_0_CSID_CLK 47 +-#define CAM_CC_IFE_0_CSID_CLK_SRC 48 +-#define CAM_CC_IFE_0_DSP_CLK 49 +-#define CAM_CC_IFE_1_AHB_CLK 50 +-#define CAM_CC_IFE_1_AREG_CLK 51 +-#define CAM_CC_IFE_1_AXI_CLK 52 +-#define CAM_CC_IFE_1_CLK 53 +-#define CAM_CC_IFE_1_CLK_SRC 54 +-#define CAM_CC_IFE_1_CPHY_RX_CLK 55 +-#define CAM_CC_IFE_1_CSID_CLK 56 +-#define CAM_CC_IFE_1_CSID_CLK_SRC 57 +-#define CAM_CC_IFE_1_DSP_CLK 58 +-#define CAM_CC_IFE_LITE_AHB_CLK 59 +-#define CAM_CC_IFE_LITE_AXI_CLK 60 +-#define CAM_CC_IFE_LITE_CLK 61 +-#define CAM_CC_IFE_LITE_CLK_SRC 62 +-#define CAM_CC_IFE_LITE_CPHY_RX_CLK 63 +-#define CAM_CC_IFE_LITE_CSID_CLK 64 +-#define CAM_CC_IFE_LITE_CSID_CLK_SRC 65 +-#define CAM_CC_IPE_0_AHB_CLK 66 +-#define CAM_CC_IPE_0_AREG_CLK 67 +-#define CAM_CC_IPE_0_AXI_CLK 68 +-#define CAM_CC_IPE_0_CLK 69 +-#define CAM_CC_IPE_0_CLK_SRC 70 +-#define CAM_CC_JPEG_CLK 71 +-#define CAM_CC_JPEG_CLK_SRC 72 +-#define CAM_CC_MCLK0_CLK 73 +-#define CAM_CC_MCLK0_CLK_SRC 74 +-#define CAM_CC_MCLK1_CLK 75 +-#define CAM_CC_MCLK1_CLK_SRC 76 +-#define CAM_CC_MCLK2_CLK 77 +-#define CAM_CC_MCLK2_CLK_SRC 78 +-#define CAM_CC_MCLK3_CLK 79 +-#define CAM_CC_MCLK3_CLK_SRC 80 +-#define CAM_CC_MCLK4_CLK 81 +-#define CAM_CC_MCLK4_CLK_SRC 82 +-#define CAM_CC_MCLK5_CLK 83 +-#define CAM_CC_MCLK5_CLK_SRC 84 +-#define CAM_CC_MCLK6_CLK 85 +-#define CAM_CC_MCLK6_CLK_SRC 86 +-#define CAM_CC_PLL0 87 +-#define CAM_CC_PLL0_OUT_EVEN 88 +-#define CAM_CC_PLL0_OUT_ODD 89 +-#define CAM_CC_PLL1 90 +-#define CAM_CC_PLL1_OUT_EVEN 91 +-#define CAM_CC_PLL2 92 +-#define CAM_CC_PLL2_OUT_MAIN 93 +-#define CAM_CC_PLL3 94 +-#define CAM_CC_PLL3_OUT_EVEN 95 +-#define CAM_CC_PLL4 96 +-#define CAM_CC_PLL4_OUT_EVEN 97 +-#define CAM_CC_SBI_AHB_CLK 98 +-#define CAM_CC_SBI_AXI_CLK 99 +-#define CAM_CC_SBI_CLK 100 +-#define CAM_CC_SBI_CPHY_RX_CLK 101 +-#define CAM_CC_SBI_CSID_CLK 102 +-#define CAM_CC_SBI_CSID_CLK_SRC 103 +-#define CAM_CC_SBI_DIV_CLK_SRC 104 +-#define CAM_CC_SBI_IFE_0_CLK 105 +-#define CAM_CC_SBI_IFE_1_CLK 106 +-#define CAM_CC_SLEEP_CLK 107 +-#define CAM_CC_SLEEP_CLK_SRC 108 +-#define CAM_CC_SLOW_AHB_CLK_SRC 109 +-#define CAM_CC_XO_CLK_SRC 110 +- +-/* CAM_CC resets */ +-#define CAM_CC_BPS_BCR 0 +-#define CAM_CC_ICP_BCR 1 +-#define CAM_CC_IFE_0_BCR 2 +-#define CAM_CC_IFE_1_BCR 3 +-#define CAM_CC_IPE_0_BCR 4 +-#define CAM_CC_SBI_BCR 5 +- +-/* CAM_CC GDSCRs */ +-#define BPS_GDSC 0 +-#define IPE_0_GDSC 1 +-#define SBI_GDSC 2 +-#define IFE_0_GDSC 3 +-#define IFE_1_GDSC 4 +-#define TITAN_TOP_GDSC 5 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,dispcc-sc7180.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,dispcc-sc7180.h +deleted file mode 100644 +index b9b51617a335..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,dispcc-sc7180.h ++++ /dev/null +@@ -1,46 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2019, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H +-#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H +- +-#define DISP_CC_PLL0 0 +-#define DISP_CC_PLL0_OUT_EVEN 1 +-#define DISP_CC_MDSS_AHB_CLK 2 +-#define DISP_CC_MDSS_AHB_CLK_SRC 3 +-#define DISP_CC_MDSS_BYTE0_CLK 4 +-#define DISP_CC_MDSS_BYTE0_CLK_SRC 5 +-#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6 +-#define DISP_CC_MDSS_BYTE0_INTF_CLK 7 +-#define DISP_CC_MDSS_DP_AUX_CLK 8 +-#define DISP_CC_MDSS_DP_AUX_CLK_SRC 9 +-#define DISP_CC_MDSS_DP_CRYPTO_CLK 10 +-#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 11 +-#define DISP_CC_MDSS_DP_LINK_CLK 12 +-#define DISP_CC_MDSS_DP_LINK_CLK_SRC 13 +-#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 14 +-#define DISP_CC_MDSS_DP_LINK_INTF_CLK 15 +-#define DISP_CC_MDSS_DP_PIXEL_CLK 16 +-#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 17 +-#define DISP_CC_MDSS_ESC0_CLK 18 +-#define DISP_CC_MDSS_ESC0_CLK_SRC 19 +-#define DISP_CC_MDSS_MDP_CLK 20 +-#define DISP_CC_MDSS_MDP_CLK_SRC 21 +-#define DISP_CC_MDSS_MDP_LUT_CLK 22 +-#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 23 +-#define DISP_CC_MDSS_PCLK0_CLK 24 +-#define DISP_CC_MDSS_PCLK0_CLK_SRC 25 +-#define DISP_CC_MDSS_ROT_CLK 26 +-#define DISP_CC_MDSS_ROT_CLK_SRC 27 +-#define DISP_CC_MDSS_RSCC_AHB_CLK 28 +-#define DISP_CC_MDSS_RSCC_VSYNC_CLK 29 +-#define DISP_CC_MDSS_VSYNC_CLK 30 +-#define DISP_CC_MDSS_VSYNC_CLK_SRC 31 +-#define DISP_CC_XO_CLK 32 +- +-/* DISP_CC GDSCR */ +-#define MDSS_GDSC 0 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,dispcc-sc7280.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,dispcc-sc7280.h +deleted file mode 100644 +index a4a692c20acf..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,dispcc-sc7280.h ++++ /dev/null +@@ -1,55 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +-/* +- * Copyright (c) 2021, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H +-#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H +- +-/* DISP_CC clocks */ +-#define DISP_CC_PLL0 0 +-#define DISP_CC_MDSS_AHB_CLK 1 +-#define DISP_CC_MDSS_AHB_CLK_SRC 2 +-#define DISP_CC_MDSS_BYTE0_CLK 3 +-#define DISP_CC_MDSS_BYTE0_CLK_SRC 4 +-#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5 +-#define DISP_CC_MDSS_BYTE0_INTF_CLK 6 +-#define DISP_CC_MDSS_DP_AUX_CLK 7 +-#define DISP_CC_MDSS_DP_AUX_CLK_SRC 8 +-#define DISP_CC_MDSS_DP_CRYPTO_CLK 9 +-#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 10 +-#define DISP_CC_MDSS_DP_LINK_CLK 11 +-#define DISP_CC_MDSS_DP_LINK_CLK_SRC 12 +-#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 13 +-#define DISP_CC_MDSS_DP_LINK_INTF_CLK 14 +-#define DISP_CC_MDSS_DP_PIXEL_CLK 15 +-#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 16 +-#define DISP_CC_MDSS_EDP_AUX_CLK 17 +-#define DISP_CC_MDSS_EDP_AUX_CLK_SRC 18 +-#define DISP_CC_MDSS_EDP_LINK_CLK 19 +-#define DISP_CC_MDSS_EDP_LINK_CLK_SRC 20 +-#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 21 +-#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 22 +-#define DISP_CC_MDSS_EDP_PIXEL_CLK 23 +-#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 24 +-#define DISP_CC_MDSS_ESC0_CLK 25 +-#define DISP_CC_MDSS_ESC0_CLK_SRC 26 +-#define DISP_CC_MDSS_MDP_CLK 27 +-#define DISP_CC_MDSS_MDP_CLK_SRC 28 +-#define DISP_CC_MDSS_MDP_LUT_CLK 29 +-#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 30 +-#define DISP_CC_MDSS_PCLK0_CLK 31 +-#define DISP_CC_MDSS_PCLK0_CLK_SRC 32 +-#define DISP_CC_MDSS_ROT_CLK 33 +-#define DISP_CC_MDSS_ROT_CLK_SRC 34 +-#define DISP_CC_MDSS_RSCC_AHB_CLK 35 +-#define DISP_CC_MDSS_RSCC_VSYNC_CLK 36 +-#define DISP_CC_MDSS_VSYNC_CLK 37 +-#define DISP_CC_MDSS_VSYNC_CLK_SRC 38 +-#define DISP_CC_SLEEP_CLK 39 +-#define DISP_CC_XO_CLK 40 +- +-/* DISP_CC power domains */ +-#define DISP_CC_MDSS_CORE_GDSC 0 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,dispcc-sdm845.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,dispcc-sdm845.h +deleted file mode 100644 +index 4016fd1d5b46..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,dispcc-sdm845.h ++++ /dev/null +@@ -1,56 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H +-#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H +- +-/* DISP_CC clock registers */ +-#define DISP_CC_MDSS_AHB_CLK 0 +-#define DISP_CC_MDSS_AXI_CLK 1 +-#define DISP_CC_MDSS_BYTE0_CLK 2 +-#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 +-#define DISP_CC_MDSS_BYTE0_INTF_CLK 4 +-#define DISP_CC_MDSS_BYTE1_CLK 5 +-#define DISP_CC_MDSS_BYTE1_CLK_SRC 6 +-#define DISP_CC_MDSS_BYTE1_INTF_CLK 7 +-#define DISP_CC_MDSS_ESC0_CLK 8 +-#define DISP_CC_MDSS_ESC0_CLK_SRC 9 +-#define DISP_CC_MDSS_ESC1_CLK 10 +-#define DISP_CC_MDSS_ESC1_CLK_SRC 11 +-#define DISP_CC_MDSS_MDP_CLK 12 +-#define DISP_CC_MDSS_MDP_CLK_SRC 13 +-#define DISP_CC_MDSS_MDP_LUT_CLK 14 +-#define DISP_CC_MDSS_PCLK0_CLK 15 +-#define DISP_CC_MDSS_PCLK0_CLK_SRC 16 +-#define DISP_CC_MDSS_PCLK1_CLK 17 +-#define DISP_CC_MDSS_PCLK1_CLK_SRC 18 +-#define DISP_CC_MDSS_ROT_CLK 19 +-#define DISP_CC_MDSS_ROT_CLK_SRC 20 +-#define DISP_CC_MDSS_RSCC_AHB_CLK 21 +-#define DISP_CC_MDSS_RSCC_VSYNC_CLK 22 +-#define DISP_CC_MDSS_VSYNC_CLK 23 +-#define DISP_CC_MDSS_VSYNC_CLK_SRC 24 +-#define DISP_CC_PLL0 25 +-#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26 +-#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27 +-#define DISP_CC_MDSS_DP_AUX_CLK 28 +-#define DISP_CC_MDSS_DP_AUX_CLK_SRC 29 +-#define DISP_CC_MDSS_DP_CRYPTO_CLK 30 +-#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 31 +-#define DISP_CC_MDSS_DP_LINK_CLK 32 +-#define DISP_CC_MDSS_DP_LINK_CLK_SRC 33 +-#define DISP_CC_MDSS_DP_LINK_INTF_CLK 34 +-#define DISP_CC_MDSS_DP_PIXEL1_CLK 35 +-#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 36 +-#define DISP_CC_MDSS_DP_PIXEL_CLK 37 +-#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 38 +- +-/* DISP_CC Reset */ +-#define DISP_CC_MDSS_RSCC_BCR 0 +- +-/* DISP_CC GDSCR */ +-#define MDSS_GDSC 0 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,dispcc-sm8150.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,dispcc-sm8150.h +deleted file mode 100644 +index ce001cbbc27f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,dispcc-sm8150.h ++++ /dev/null +@@ -1,75 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H +-#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H +- +-/* DISP_CC clock registers */ +-#define DISP_CC_MDSS_AHB_CLK 0 +-#define DISP_CC_MDSS_AHB_CLK_SRC 1 +-#define DISP_CC_MDSS_BYTE0_CLK 2 +-#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 +-#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4 +-#define DISP_CC_MDSS_BYTE0_INTF_CLK 5 +-#define DISP_CC_MDSS_BYTE1_CLK 6 +-#define DISP_CC_MDSS_BYTE1_CLK_SRC 7 +-#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 8 +-#define DISP_CC_MDSS_BYTE1_INTF_CLK 9 +-#define DISP_CC_MDSS_DP_AUX1_CLK 10 +-#define DISP_CC_MDSS_DP_AUX1_CLK_SRC 11 +-#define DISP_CC_MDSS_DP_AUX_CLK 12 +-#define DISP_CC_MDSS_DP_AUX_CLK_SRC 13 +-#define DISP_CC_MDSS_DP_LINK1_CLK 14 +-#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 15 +-#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC 16 +-#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 17 +-#define DISP_CC_MDSS_DP_LINK_CLK 18 +-#define DISP_CC_MDSS_DP_LINK_CLK_SRC 19 +-#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 20 +-#define DISP_CC_MDSS_DP_LINK_INTF_CLK 21 +-#define DISP_CC_MDSS_DP_PIXEL1_CLK 22 +-#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 23 +-#define DISP_CC_MDSS_DP_PIXEL2_CLK 24 +-#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 25 +-#define DISP_CC_MDSS_DP_PIXEL_CLK 26 +-#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 27 +-#define DISP_CC_MDSS_ESC0_CLK 28 +-#define DISP_CC_MDSS_ESC0_CLK_SRC 29 +-#define DISP_CC_MDSS_ESC1_CLK 30 +-#define DISP_CC_MDSS_ESC1_CLK_SRC 31 +-#define DISP_CC_MDSS_MDP_CLK 32 +-#define DISP_CC_MDSS_MDP_CLK_SRC 33 +-#define DISP_CC_MDSS_MDP_LUT_CLK 34 +-#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 35 +-#define DISP_CC_MDSS_PCLK0_CLK 36 +-#define DISP_CC_MDSS_PCLK0_CLK_SRC 37 +-#define DISP_CC_MDSS_PCLK1_CLK 38 +-#define DISP_CC_MDSS_PCLK1_CLK_SRC 39 +-#define DISP_CC_MDSS_ROT_CLK 40 +-#define DISP_CC_MDSS_ROT_CLK_SRC 41 +-#define DISP_CC_MDSS_RSCC_AHB_CLK 42 +-#define DISP_CC_MDSS_RSCC_VSYNC_CLK 43 +-#define DISP_CC_MDSS_VSYNC_CLK 44 +-#define DISP_CC_MDSS_VSYNC_CLK_SRC 45 +-#define DISP_CC_PLL0 46 +-#define DISP_CC_PLL1 47 +-#define DISP_CC_MDSS_EDP_AUX_CLK 48 +-#define DISP_CC_MDSS_EDP_AUX_CLK_SRC 49 +-#define DISP_CC_MDSS_EDP_GTC_CLK 50 +-#define DISP_CC_MDSS_EDP_GTC_CLK_SRC 51 +-#define DISP_CC_MDSS_EDP_LINK_CLK 52 +-#define DISP_CC_MDSS_EDP_LINK_CLK_SRC 53 +-#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 54 +-#define DISP_CC_MDSS_EDP_PIXEL_CLK 55 +-#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 56 +- +-/* DISP_CC Reset */ +-#define DISP_CC_MDSS_CORE_BCR 0 +-#define DISP_CC_MDSS_RSCC_BCR 1 +- +-/* DISP_CC GDSCR */ +-#define MDSS_GDSC 0 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,dispcc-sm8250.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,dispcc-sm8250.h +deleted file mode 100644 +index ce001cbbc27f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,dispcc-sm8250.h ++++ /dev/null +@@ -1,75 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H +-#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H +- +-/* DISP_CC clock registers */ +-#define DISP_CC_MDSS_AHB_CLK 0 +-#define DISP_CC_MDSS_AHB_CLK_SRC 1 +-#define DISP_CC_MDSS_BYTE0_CLK 2 +-#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 +-#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4 +-#define DISP_CC_MDSS_BYTE0_INTF_CLK 5 +-#define DISP_CC_MDSS_BYTE1_CLK 6 +-#define DISP_CC_MDSS_BYTE1_CLK_SRC 7 +-#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 8 +-#define DISP_CC_MDSS_BYTE1_INTF_CLK 9 +-#define DISP_CC_MDSS_DP_AUX1_CLK 10 +-#define DISP_CC_MDSS_DP_AUX1_CLK_SRC 11 +-#define DISP_CC_MDSS_DP_AUX_CLK 12 +-#define DISP_CC_MDSS_DP_AUX_CLK_SRC 13 +-#define DISP_CC_MDSS_DP_LINK1_CLK 14 +-#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 15 +-#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC 16 +-#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 17 +-#define DISP_CC_MDSS_DP_LINK_CLK 18 +-#define DISP_CC_MDSS_DP_LINK_CLK_SRC 19 +-#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 20 +-#define DISP_CC_MDSS_DP_LINK_INTF_CLK 21 +-#define DISP_CC_MDSS_DP_PIXEL1_CLK 22 +-#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 23 +-#define DISP_CC_MDSS_DP_PIXEL2_CLK 24 +-#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 25 +-#define DISP_CC_MDSS_DP_PIXEL_CLK 26 +-#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 27 +-#define DISP_CC_MDSS_ESC0_CLK 28 +-#define DISP_CC_MDSS_ESC0_CLK_SRC 29 +-#define DISP_CC_MDSS_ESC1_CLK 30 +-#define DISP_CC_MDSS_ESC1_CLK_SRC 31 +-#define DISP_CC_MDSS_MDP_CLK 32 +-#define DISP_CC_MDSS_MDP_CLK_SRC 33 +-#define DISP_CC_MDSS_MDP_LUT_CLK 34 +-#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 35 +-#define DISP_CC_MDSS_PCLK0_CLK 36 +-#define DISP_CC_MDSS_PCLK0_CLK_SRC 37 +-#define DISP_CC_MDSS_PCLK1_CLK 38 +-#define DISP_CC_MDSS_PCLK1_CLK_SRC 39 +-#define DISP_CC_MDSS_ROT_CLK 40 +-#define DISP_CC_MDSS_ROT_CLK_SRC 41 +-#define DISP_CC_MDSS_RSCC_AHB_CLK 42 +-#define DISP_CC_MDSS_RSCC_VSYNC_CLK 43 +-#define DISP_CC_MDSS_VSYNC_CLK 44 +-#define DISP_CC_MDSS_VSYNC_CLK_SRC 45 +-#define DISP_CC_PLL0 46 +-#define DISP_CC_PLL1 47 +-#define DISP_CC_MDSS_EDP_AUX_CLK 48 +-#define DISP_CC_MDSS_EDP_AUX_CLK_SRC 49 +-#define DISP_CC_MDSS_EDP_GTC_CLK 50 +-#define DISP_CC_MDSS_EDP_GTC_CLK_SRC 51 +-#define DISP_CC_MDSS_EDP_LINK_CLK 52 +-#define DISP_CC_MDSS_EDP_LINK_CLK_SRC 53 +-#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 54 +-#define DISP_CC_MDSS_EDP_PIXEL_CLK 55 +-#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 56 +- +-/* DISP_CC Reset */ +-#define DISP_CC_MDSS_CORE_BCR 0 +-#define DISP_CC_MDSS_RSCC_BCR 1 +- +-/* DISP_CC GDSCR */ +-#define MDSS_GDSC 0 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-apq8084.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-apq8084.h +deleted file mode 100644 +index 7f657cf8cc8a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-apq8084.h ++++ /dev/null +@@ -1,349 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_APQ_GCC_8084_H +-#define _DT_BINDINGS_CLK_APQ_GCC_8084_H +- +-#define GPLL0 0 +-#define GPLL0_VOTE 1 +-#define GPLL1 2 +-#define GPLL1_VOTE 3 +-#define GPLL2 4 +-#define GPLL2_VOTE 5 +-#define GPLL3 6 +-#define GPLL3_VOTE 7 +-#define GPLL4 8 +-#define GPLL4_VOTE 9 +-#define CONFIG_NOC_CLK_SRC 10 +-#define PERIPH_NOC_CLK_SRC 11 +-#define SYSTEM_NOC_CLK_SRC 12 +-#define BLSP_UART_SIM_CLK_SRC 13 +-#define QDSS_TSCTR_CLK_SRC 14 +-#define UFS_AXI_CLK_SRC 15 +-#define RPM_CLK_SRC 16 +-#define KPSS_AHB_CLK_SRC 17 +-#define QDSS_AT_CLK_SRC 18 +-#define BIMC_DDR_CLK_SRC 19 +-#define USB30_MASTER_CLK_SRC 20 +-#define USB30_SEC_MASTER_CLK_SRC 21 +-#define USB_HSIC_AHB_CLK_SRC 22 +-#define MMSS_BIMC_GFX_CLK_SRC 23 +-#define QDSS_STM_CLK_SRC 24 +-#define ACC_CLK_SRC 25 +-#define SEC_CTRL_CLK_SRC 26 +-#define BLSP1_QUP1_I2C_APPS_CLK_SRC 27 +-#define BLSP1_QUP1_SPI_APPS_CLK_SRC 28 +-#define BLSP1_QUP2_I2C_APPS_CLK_SRC 29 +-#define BLSP1_QUP2_SPI_APPS_CLK_SRC 30 +-#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 +-#define BLSP1_QUP3_SPI_APPS_CLK_SRC 32 +-#define BLSP1_QUP4_I2C_APPS_CLK_SRC 33 +-#define BLSP1_QUP4_SPI_APPS_CLK_SRC 34 +-#define BLSP1_QUP5_I2C_APPS_CLK_SRC 35 +-#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 +-#define BLSP1_QUP6_I2C_APPS_CLK_SRC 37 +-#define BLSP1_QUP6_SPI_APPS_CLK_SRC 38 +-#define BLSP1_UART1_APPS_CLK_SRC 39 +-#define BLSP1_UART2_APPS_CLK_SRC 40 +-#define BLSP1_UART3_APPS_CLK_SRC 41 +-#define BLSP1_UART4_APPS_CLK_SRC 42 +-#define BLSP1_UART5_APPS_CLK_SRC 43 +-#define BLSP1_UART6_APPS_CLK_SRC 44 +-#define BLSP2_QUP1_I2C_APPS_CLK_SRC 45 +-#define BLSP2_QUP1_SPI_APPS_CLK_SRC 46 +-#define BLSP2_QUP2_I2C_APPS_CLK_SRC 47 +-#define BLSP2_QUP2_SPI_APPS_CLK_SRC 48 +-#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 +-#define BLSP2_QUP3_SPI_APPS_CLK_SRC 50 +-#define BLSP2_QUP4_I2C_APPS_CLK_SRC 51 +-#define BLSP2_QUP4_SPI_APPS_CLK_SRC 52 +-#define BLSP2_QUP5_I2C_APPS_CLK_SRC 53 +-#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 +-#define BLSP2_QUP6_I2C_APPS_CLK_SRC 55 +-#define BLSP2_QUP6_SPI_APPS_CLK_SRC 56 +-#define BLSP2_UART1_APPS_CLK_SRC 57 +-#define BLSP2_UART2_APPS_CLK_SRC 58 +-#define BLSP2_UART3_APPS_CLK_SRC 59 +-#define BLSP2_UART4_APPS_CLK_SRC 60 +-#define BLSP2_UART5_APPS_CLK_SRC 61 +-#define BLSP2_UART6_APPS_CLK_SRC 62 +-#define CE1_CLK_SRC 63 +-#define CE2_CLK_SRC 64 +-#define CE3_CLK_SRC 65 +-#define GP1_CLK_SRC 66 +-#define GP2_CLK_SRC 67 +-#define GP3_CLK_SRC 68 +-#define PDM2_CLK_SRC 69 +-#define QDSS_TRACECLKIN_CLK_SRC 70 +-#define RBCPR_CLK_SRC 71 +-#define SATA_ASIC0_CLK_SRC 72 +-#define SATA_PMALIVE_CLK_SRC 73 +-#define SATA_RX_CLK_SRC 74 +-#define SATA_RX_OOB_CLK_SRC 75 +-#define SDCC1_APPS_CLK_SRC 76 +-#define SDCC2_APPS_CLK_SRC 77 +-#define SDCC3_APPS_CLK_SRC 78 +-#define SDCC4_APPS_CLK_SRC 79 +-#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 80 +-#define SPMI_AHB_CLK_SRC 81 +-#define SPMI_SER_CLK_SRC 82 +-#define TSIF_REF_CLK_SRC 83 +-#define USB30_MOCK_UTMI_CLK_SRC 84 +-#define USB30_SEC_MOCK_UTMI_CLK_SRC 85 +-#define USB_HS_SYSTEM_CLK_SRC 86 +-#define USB_HSIC_CLK_SRC 87 +-#define USB_HSIC_IO_CAL_CLK_SRC 88 +-#define USB_HSIC_MOCK_UTMI_CLK_SRC 89 +-#define USB_HSIC_SYSTEM_CLK_SRC 90 +-#define GCC_BAM_DMA_AHB_CLK 91 +-#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 92 +-#define DDR_CLK_SRC 93 +-#define GCC_BIMC_CFG_AHB_CLK 94 +-#define GCC_BIMC_CLK 95 +-#define GCC_BIMC_KPSS_AXI_CLK 96 +-#define GCC_BIMC_SLEEP_CLK 97 +-#define GCC_BIMC_SYSNOC_AXI_CLK 98 +-#define GCC_BIMC_XO_CLK 99 +-#define GCC_BLSP1_AHB_CLK 100 +-#define GCC_BLSP1_SLEEP_CLK 101 +-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 102 +-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 103 +-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 104 +-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 105 +-#define GCC_BLSP1_QUP3_I2C_APPS_CLK 106 +-#define GCC_BLSP1_QUP3_SPI_APPS_CLK 107 +-#define GCC_BLSP1_QUP4_I2C_APPS_CLK 108 +-#define GCC_BLSP1_QUP4_SPI_APPS_CLK 109 +-#define GCC_BLSP1_QUP5_I2C_APPS_CLK 110 +-#define GCC_BLSP1_QUP5_SPI_APPS_CLK 111 +-#define GCC_BLSP1_QUP6_I2C_APPS_CLK 112 +-#define GCC_BLSP1_QUP6_SPI_APPS_CLK 113 +-#define GCC_BLSP1_UART1_APPS_CLK 114 +-#define GCC_BLSP1_UART1_SIM_CLK 115 +-#define GCC_BLSP1_UART2_APPS_CLK 116 +-#define GCC_BLSP1_UART2_SIM_CLK 117 +-#define GCC_BLSP1_UART3_APPS_CLK 118 +-#define GCC_BLSP1_UART3_SIM_CLK 119 +-#define GCC_BLSP1_UART4_APPS_CLK 120 +-#define GCC_BLSP1_UART4_SIM_CLK 121 +-#define GCC_BLSP1_UART5_APPS_CLK 122 +-#define GCC_BLSP1_UART5_SIM_CLK 123 +-#define GCC_BLSP1_UART6_APPS_CLK 124 +-#define GCC_BLSP1_UART6_SIM_CLK 125 +-#define GCC_BLSP2_AHB_CLK 126 +-#define GCC_BLSP2_SLEEP_CLK 127 +-#define GCC_BLSP2_QUP1_I2C_APPS_CLK 128 +-#define GCC_BLSP2_QUP1_SPI_APPS_CLK 129 +-#define GCC_BLSP2_QUP2_I2C_APPS_CLK 130 +-#define GCC_BLSP2_QUP2_SPI_APPS_CLK 131 +-#define GCC_BLSP2_QUP3_I2C_APPS_CLK 132 +-#define GCC_BLSP2_QUP3_SPI_APPS_CLK 133 +-#define GCC_BLSP2_QUP4_I2C_APPS_CLK 134 +-#define GCC_BLSP2_QUP4_SPI_APPS_CLK 135 +-#define GCC_BLSP2_QUP5_I2C_APPS_CLK 136 +-#define GCC_BLSP2_QUP5_SPI_APPS_CLK 137 +-#define GCC_BLSP2_QUP6_I2C_APPS_CLK 138 +-#define GCC_BLSP2_QUP6_SPI_APPS_CLK 139 +-#define GCC_BLSP2_UART1_APPS_CLK 140 +-#define GCC_BLSP2_UART1_SIM_CLK 141 +-#define GCC_BLSP2_UART2_APPS_CLK 142 +-#define GCC_BLSP2_UART2_SIM_CLK 143 +-#define GCC_BLSP2_UART3_APPS_CLK 144 +-#define GCC_BLSP2_UART3_SIM_CLK 145 +-#define GCC_BLSP2_UART4_APPS_CLK 146 +-#define GCC_BLSP2_UART4_SIM_CLK 147 +-#define GCC_BLSP2_UART5_APPS_CLK 148 +-#define GCC_BLSP2_UART5_SIM_CLK 149 +-#define GCC_BLSP2_UART6_APPS_CLK 150 +-#define GCC_BLSP2_UART6_SIM_CLK 151 +-#define GCC_BOOT_ROM_AHB_CLK 152 +-#define GCC_CE1_AHB_CLK 153 +-#define GCC_CE1_AXI_CLK 154 +-#define GCC_CE1_CLK 155 +-#define GCC_CE2_AHB_CLK 156 +-#define GCC_CE2_AXI_CLK 157 +-#define GCC_CE2_CLK 158 +-#define GCC_CE3_AHB_CLK 159 +-#define GCC_CE3_AXI_CLK 160 +-#define GCC_CE3_CLK 161 +-#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 162 +-#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 163 +-#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 164 +-#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 165 +-#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 166 +-#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 167 +-#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 168 +-#define GCC_CNOC_BUS_TIMEOUT7_AHB_CLK 169 +-#define GCC_CFG_NOC_AHB_CLK 170 +-#define GCC_CFG_NOC_DDR_CFG_CLK 171 +-#define GCC_CFG_NOC_RPM_AHB_CLK 172 +-#define GCC_COPSS_SMMU_AHB_CLK 173 +-#define GCC_COPSS_SMMU_AXI_CLK 174 +-#define GCC_DCD_XO_CLK 175 +-#define GCC_BIMC_DDR_CH0_CLK 176 +-#define GCC_BIMC_DDR_CH1_CLK 177 +-#define GCC_BIMC_DDR_CPLL0_CLK 178 +-#define GCC_BIMC_DDR_CPLL1_CLK 179 +-#define GCC_BIMC_GFX_CLK 180 +-#define GCC_DDR_DIM_CFG_CLK 181 +-#define GCC_DDR_DIM_SLEEP_CLK 182 +-#define GCC_DEHR_CLK 183 +-#define GCC_AHB_CLK 184 +-#define GCC_IM_SLEEP_CLK 185 +-#define GCC_XO_CLK 186 +-#define GCC_XO_DIV4_CLK 187 +-#define GCC_GP1_CLK 188 +-#define GCC_GP2_CLK 189 +-#define GCC_GP3_CLK 190 +-#define GCC_IMEM_AXI_CLK 191 +-#define GCC_IMEM_CFG_AHB_CLK 192 +-#define GCC_KPSS_AHB_CLK 193 +-#define GCC_KPSS_AXI_CLK 194 +-#define GCC_LPASS_MPORT_AXI_CLK 195 +-#define GCC_LPASS_Q6_AXI_CLK 196 +-#define GCC_LPASS_SWAY_CLK 197 +-#define GCC_MMSS_BIMC_GFX_CLK 198 +-#define GCC_MMSS_NOC_AT_CLK 199 +-#define GCC_MMSS_NOC_CFG_AHB_CLK 200 +-#define GCC_MMSS_VPU_MAPLE_SYS_NOC_AXI_CLK 201 +-#define GCC_OCMEM_NOC_CFG_AHB_CLK 202 +-#define GCC_OCMEM_SYS_NOC_AXI_CLK 203 +-#define GCC_MPM_AHB_CLK 204 +-#define GCC_MSG_RAM_AHB_CLK 205 +-#define GCC_NOC_CONF_XPU_AHB_CLK 206 +-#define GCC_PDM2_CLK 207 +-#define GCC_PDM_AHB_CLK 208 +-#define GCC_PDM_XO4_CLK 209 +-#define GCC_PERIPH_NOC_AHB_CLK 210 +-#define GCC_PERIPH_NOC_AT_CLK 211 +-#define GCC_PERIPH_NOC_CFG_AHB_CLK 212 +-#define GCC_PERIPH_NOC_USB_HSIC_AHB_CLK 213 +-#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 214 +-#define GCC_PERIPH_XPU_AHB_CLK 215 +-#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 216 +-#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 217 +-#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 218 +-#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 219 +-#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 220 +-#define GCC_PRNG_AHB_CLK 221 +-#define GCC_QDSS_AT_CLK 222 +-#define GCC_QDSS_CFG_AHB_CLK 223 +-#define GCC_QDSS_DAP_AHB_CLK 224 +-#define GCC_QDSS_DAP_CLK 225 +-#define GCC_QDSS_ETR_USB_CLK 226 +-#define GCC_QDSS_STM_CLK 227 +-#define GCC_QDSS_TRACECLKIN_CLK 228 +-#define GCC_QDSS_TSCTR_DIV16_CLK 229 +-#define GCC_QDSS_TSCTR_DIV2_CLK 230 +-#define GCC_QDSS_TSCTR_DIV3_CLK 231 +-#define GCC_QDSS_TSCTR_DIV4_CLK 232 +-#define GCC_QDSS_TSCTR_DIV8_CLK 233 +-#define GCC_QDSS_RBCPR_XPU_AHB_CLK 234 +-#define GCC_RBCPR_AHB_CLK 235 +-#define GCC_RBCPR_CLK 236 +-#define GCC_RPM_BUS_AHB_CLK 237 +-#define GCC_RPM_PROC_HCLK 238 +-#define GCC_RPM_SLEEP_CLK 239 +-#define GCC_RPM_TIMER_CLK 240 +-#define GCC_SATA_ASIC0_CLK 241 +-#define GCC_SATA_AXI_CLK 242 +-#define GCC_SATA_CFG_AHB_CLK 243 +-#define GCC_SATA_PMALIVE_CLK 244 +-#define GCC_SATA_RX_CLK 245 +-#define GCC_SATA_RX_OOB_CLK 246 +-#define GCC_SDCC1_AHB_CLK 247 +-#define GCC_SDCC1_APPS_CLK 248 +-#define GCC_SDCC1_CDCCAL_FF_CLK 249 +-#define GCC_SDCC1_CDCCAL_SLEEP_CLK 250 +-#define GCC_SDCC2_AHB_CLK 251 +-#define GCC_SDCC2_APPS_CLK 252 +-#define GCC_SDCC2_INACTIVITY_TIMERS_CLK 253 +-#define GCC_SDCC3_AHB_CLK 254 +-#define GCC_SDCC3_APPS_CLK 255 +-#define GCC_SDCC3_INACTIVITY_TIMERS_CLK 256 +-#define GCC_SDCC4_AHB_CLK 257 +-#define GCC_SDCC4_APPS_CLK 258 +-#define GCC_SDCC4_INACTIVITY_TIMERS_CLK 259 +-#define GCC_SEC_CTRL_ACC_CLK 260 +-#define GCC_SEC_CTRL_AHB_CLK 261 +-#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 262 +-#define GCC_SEC_CTRL_CLK 263 +-#define GCC_SEC_CTRL_SENSE_CLK 264 +-#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 265 +-#define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK 266 +-#define GCC_SPDM_BIMC_CY_CLK 267 +-#define GCC_SPDM_CFG_AHB_CLK 268 +-#define GCC_SPDM_DEBUG_CY_CLK 269 +-#define GCC_SPDM_FF_CLK 270 +-#define GCC_SPDM_MSTR_AHB_CLK 271 +-#define GCC_SPDM_PNOC_CY_CLK 272 +-#define GCC_SPDM_RPM_CY_CLK 273 +-#define GCC_SPDM_SNOC_CY_CLK 274 +-#define GCC_SPMI_AHB_CLK 275 +-#define GCC_SPMI_CNOC_AHB_CLK 276 +-#define GCC_SPMI_SER_CLK 277 +-#define GCC_SPSS_AHB_CLK 278 +-#define GCC_SNOC_CNOC_AHB_CLK 279 +-#define GCC_SNOC_PNOC_AHB_CLK 280 +-#define GCC_SYS_NOC_AT_CLK 281 +-#define GCC_SYS_NOC_AXI_CLK 282 +-#define GCC_SYS_NOC_KPSS_AHB_CLK 283 +-#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 284 +-#define GCC_SYS_NOC_UFS_AXI_CLK 285 +-#define GCC_SYS_NOC_USB3_AXI_CLK 286 +-#define GCC_SYS_NOC_USB3_SEC_AXI_CLK 287 +-#define GCC_TCSR_AHB_CLK 288 +-#define GCC_TLMM_AHB_CLK 289 +-#define GCC_TLMM_CLK 290 +-#define GCC_TSIF_AHB_CLK 291 +-#define GCC_TSIF_INACTIVITY_TIMERS_CLK 292 +-#define GCC_TSIF_REF_CLK 293 +-#define GCC_UFS_AHB_CLK 294 +-#define GCC_UFS_AXI_CLK 295 +-#define GCC_UFS_RX_CFG_CLK 296 +-#define GCC_UFS_RX_SYMBOL_0_CLK 297 +-#define GCC_UFS_RX_SYMBOL_1_CLK 298 +-#define GCC_UFS_TX_CFG_CLK 299 +-#define GCC_UFS_TX_SYMBOL_0_CLK 300 +-#define GCC_UFS_TX_SYMBOL_1_CLK 301 +-#define GCC_USB2A_PHY_SLEEP_CLK 302 +-#define GCC_USB2B_PHY_SLEEP_CLK 303 +-#define GCC_USB30_MASTER_CLK 304 +-#define GCC_USB30_MOCK_UTMI_CLK 305 +-#define GCC_USB30_SLEEP_CLK 306 +-#define GCC_USB30_SEC_MASTER_CLK 307 +-#define GCC_USB30_SEC_MOCK_UTMI_CLK 308 +-#define GCC_USB30_SEC_SLEEP_CLK 309 +-#define GCC_USB_HS_AHB_CLK 310 +-#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 311 +-#define GCC_USB_HS_SYSTEM_CLK 312 +-#define GCC_USB_HSIC_AHB_CLK 313 +-#define GCC_USB_HSIC_CLK 314 +-#define GCC_USB_HSIC_IO_CAL_CLK 315 +-#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 316 +-#define GCC_USB_HSIC_MOCK_UTMI_CLK 317 +-#define GCC_USB_HSIC_SYSTEM_CLK 318 +-#define PCIE_0_AUX_CLK_SRC 319 +-#define PCIE_0_PIPE_CLK_SRC 320 +-#define PCIE_1_AUX_CLK_SRC 321 +-#define PCIE_1_PIPE_CLK_SRC 322 +-#define GCC_PCIE_0_AUX_CLK 323 +-#define GCC_PCIE_0_CFG_AHB_CLK 324 +-#define GCC_PCIE_0_MSTR_AXI_CLK 325 +-#define GCC_PCIE_0_PIPE_CLK 326 +-#define GCC_PCIE_0_SLV_AXI_CLK 327 +-#define GCC_PCIE_1_AUX_CLK 328 +-#define GCC_PCIE_1_CFG_AHB_CLK 329 +-#define GCC_PCIE_1_MSTR_AXI_CLK 330 +-#define GCC_PCIE_1_PIPE_CLK 331 +-#define GCC_PCIE_1_SLV_AXI_CLK 332 +- +-/* gdscs */ +-#define USB_HS_HSIC_GDSC 0 +-#define PCIE0_GDSC 1 +-#define PCIE1_GDSC 2 +-#define USB30_GDSC 3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h +deleted file mode 100644 +index 7e8a7be6dcda..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h ++++ /dev/null +@@ -1,169 +0,0 @@ +-/* Copyright (c) 2015 The Linux Foundation. All rights reserved. +- * +- * Permission to use, copy, modify, and/or distribute this software for any +- * purpose with or without fee is hereby granted, provided that the above +- * copyright notice and this permission notice appear in all copies. +- * +- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +- * +- */ +-#ifndef __QCOM_CLK_IPQ4019_H__ +-#define __QCOM_CLK_IPQ4019_H__ +- +-#define GCC_DUMMY_CLK 0 +-#define AUDIO_CLK_SRC 1 +-#define BLSP1_QUP1_I2C_APPS_CLK_SRC 2 +-#define BLSP1_QUP1_SPI_APPS_CLK_SRC 3 +-#define BLSP1_QUP2_I2C_APPS_CLK_SRC 4 +-#define BLSP1_QUP2_SPI_APPS_CLK_SRC 5 +-#define BLSP1_UART1_APPS_CLK_SRC 6 +-#define BLSP1_UART2_APPS_CLK_SRC 7 +-#define GCC_USB3_MOCK_UTMI_CLK_SRC 8 +-#define GCC_APPS_CLK_SRC 9 +-#define GCC_APPS_AHB_CLK_SRC 10 +-#define GP1_CLK_SRC 11 +-#define GP2_CLK_SRC 12 +-#define GP3_CLK_SRC 13 +-#define SDCC1_APPS_CLK_SRC 14 +-#define FEPHY_125M_DLY_CLK_SRC 15 +-#define WCSS2G_CLK_SRC 16 +-#define WCSS5G_CLK_SRC 17 +-#define GCC_APSS_AHB_CLK 18 +-#define GCC_AUDIO_AHB_CLK 19 +-#define GCC_AUDIO_PWM_CLK 20 +-#define GCC_BLSP1_AHB_CLK 21 +-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22 +-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23 +-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24 +-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25 +-#define GCC_BLSP1_UART1_APPS_CLK 26 +-#define GCC_BLSP1_UART2_APPS_CLK 27 +-#define GCC_DCD_XO_CLK 28 +-#define GCC_GP1_CLK 29 +-#define GCC_GP2_CLK 30 +-#define GCC_GP3_CLK 31 +-#define GCC_BOOT_ROM_AHB_CLK 32 +-#define GCC_CRYPTO_AHB_CLK 33 +-#define GCC_CRYPTO_AXI_CLK 34 +-#define GCC_CRYPTO_CLK 35 +-#define GCC_ESS_CLK 36 +-#define GCC_IMEM_AXI_CLK 37 +-#define GCC_IMEM_CFG_AHB_CLK 38 +-#define GCC_PCIE_AHB_CLK 39 +-#define GCC_PCIE_AXI_M_CLK 40 +-#define GCC_PCIE_AXI_S_CLK 41 +-#define GCC_PCNOC_AHB_CLK 42 +-#define GCC_PRNG_AHB_CLK 43 +-#define GCC_QPIC_AHB_CLK 44 +-#define GCC_QPIC_CLK 45 +-#define GCC_SDCC1_AHB_CLK 46 +-#define GCC_SDCC1_APPS_CLK 47 +-#define GCC_SNOC_PCNOC_AHB_CLK 48 +-#define GCC_SYS_NOC_125M_CLK 49 +-#define GCC_SYS_NOC_AXI_CLK 50 +-#define GCC_TCSR_AHB_CLK 51 +-#define GCC_TLMM_AHB_CLK 52 +-#define GCC_USB2_MASTER_CLK 53 +-#define GCC_USB2_SLEEP_CLK 54 +-#define GCC_USB2_MOCK_UTMI_CLK 55 +-#define GCC_USB3_MASTER_CLK 56 +-#define GCC_USB3_SLEEP_CLK 57 +-#define GCC_USB3_MOCK_UTMI_CLK 58 +-#define GCC_WCSS2G_CLK 59 +-#define GCC_WCSS2G_REF_CLK 60 +-#define GCC_WCSS2G_RTC_CLK 61 +-#define GCC_WCSS5G_CLK 62 +-#define GCC_WCSS5G_REF_CLK 63 +-#define GCC_WCSS5G_RTC_CLK 64 +-#define GCC_APSS_DDRPLL_VCO 65 +-#define GCC_SDCC_PLLDIV_CLK 66 +-#define GCC_FEPLL_VCO 67 +-#define GCC_FEPLL125_CLK 68 +-#define GCC_FEPLL125DLY_CLK 69 +-#define GCC_FEPLL200_CLK 70 +-#define GCC_FEPLL500_CLK 71 +-#define GCC_FEPLL_WCSS2G_CLK 72 +-#define GCC_FEPLL_WCSS5G_CLK 73 +-#define GCC_APSS_CPU_PLLDIV_CLK 74 +-#define GCC_PCNOC_AHB_CLK_SRC 75 +- +-#define WIFI0_CPU_INIT_RESET 0 +-#define WIFI0_RADIO_SRIF_RESET 1 +-#define WIFI0_RADIO_WARM_RESET 2 +-#define WIFI0_RADIO_COLD_RESET 3 +-#define WIFI0_CORE_WARM_RESET 4 +-#define WIFI0_CORE_COLD_RESET 5 +-#define WIFI1_CPU_INIT_RESET 6 +-#define WIFI1_RADIO_SRIF_RESET 7 +-#define WIFI1_RADIO_WARM_RESET 8 +-#define WIFI1_RADIO_COLD_RESET 9 +-#define WIFI1_CORE_WARM_RESET 10 +-#define WIFI1_CORE_COLD_RESET 11 +-#define USB3_UNIPHY_PHY_ARES 12 +-#define USB3_HSPHY_POR_ARES 13 +-#define USB3_HSPHY_S_ARES 14 +-#define USB2_HSPHY_POR_ARES 15 +-#define USB2_HSPHY_S_ARES 16 +-#define PCIE_PHY_AHB_ARES 17 +-#define PCIE_AHB_ARES 18 +-#define PCIE_PWR_ARES 19 +-#define PCIE_PIPE_STICKY_ARES 20 +-#define PCIE_AXI_M_STICKY_ARES 21 +-#define PCIE_PHY_ARES 22 +-#define PCIE_PARF_XPU_ARES 23 +-#define PCIE_AXI_S_XPU_ARES 24 +-#define PCIE_AXI_M_VMIDMT_ARES 25 +-#define PCIE_PIPE_ARES 26 +-#define PCIE_AXI_S_ARES 27 +-#define PCIE_AXI_M_ARES 28 +-#define ESS_RESET 29 +-#define GCC_BLSP1_BCR 30 +-#define GCC_BLSP1_QUP1_BCR 31 +-#define GCC_BLSP1_UART1_BCR 32 +-#define GCC_BLSP1_QUP2_BCR 33 +-#define GCC_BLSP1_UART2_BCR 34 +-#define GCC_BIMC_BCR 35 +-#define GCC_TLMM_BCR 36 +-#define GCC_IMEM_BCR 37 +-#define GCC_ESS_BCR 38 +-#define GCC_PRNG_BCR 39 +-#define GCC_BOOT_ROM_BCR 40 +-#define GCC_CRYPTO_BCR 41 +-#define GCC_SDCC1_BCR 42 +-#define GCC_SEC_CTRL_BCR 43 +-#define GCC_AUDIO_BCR 44 +-#define GCC_QPIC_BCR 45 +-#define GCC_PCIE_BCR 46 +-#define GCC_USB2_BCR 47 +-#define GCC_USB2_PHY_BCR 48 +-#define GCC_USB3_BCR 49 +-#define GCC_USB3_PHY_BCR 50 +-#define GCC_SYSTEM_NOC_BCR 51 +-#define GCC_PCNOC_BCR 52 +-#define GCC_DCD_BCR 53 +-#define GCC_SNOC_BUS_TIMEOUT0_BCR 54 +-#define GCC_SNOC_BUS_TIMEOUT1_BCR 55 +-#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 +-#define GCC_SNOC_BUS_TIMEOUT3_BCR 57 +-#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58 +-#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59 +-#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60 +-#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61 +-#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62 +-#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63 +-#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64 +-#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65 +-#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66 +-#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67 +-#define GCC_TCSR_BCR 68 +-#define GCC_QDSS_BCR 69 +-#define GCC_MPM_BCR 70 +-#define GCC_SPDM_BCR 71 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq6018.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq6018.h +deleted file mode 100644 +index 6f4be3aa0acf..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq6018.h ++++ /dev/null +@@ -1,262 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2018, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H +-#define _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H +- +-#define GPLL0 0 +-#define UBI32_PLL 1 +-#define GPLL6 2 +-#define GPLL4 3 +-#define PCNOC_BFDCD_CLK_SRC 4 +-#define GPLL2 5 +-#define NSS_CRYPTO_PLL 6 +-#define NSS_PPE_CLK_SRC 7 +-#define GCC_XO_CLK_SRC 8 +-#define NSS_CE_CLK_SRC 9 +-#define GCC_SLEEP_CLK_SRC 10 +-#define APSS_AHB_CLK_SRC 11 +-#define NSS_PORT5_RX_CLK_SRC 12 +-#define NSS_PORT5_TX_CLK_SRC 13 +-#define PCIE0_AXI_CLK_SRC 14 +-#define USB0_MASTER_CLK_SRC 15 +-#define APSS_AHB_POSTDIV_CLK_SRC 16 +-#define NSS_PORT1_RX_CLK_SRC 17 +-#define NSS_PORT1_TX_CLK_SRC 18 +-#define NSS_PORT2_RX_CLK_SRC 19 +-#define NSS_PORT2_TX_CLK_SRC 20 +-#define NSS_PORT3_RX_CLK_SRC 21 +-#define NSS_PORT3_TX_CLK_SRC 22 +-#define NSS_PORT4_RX_CLK_SRC 23 +-#define NSS_PORT4_TX_CLK_SRC 24 +-#define NSS_PORT5_RX_DIV_CLK_SRC 25 +-#define NSS_PORT5_TX_DIV_CLK_SRC 26 +-#define APSS_AXI_CLK_SRC 27 +-#define NSS_CRYPTO_CLK_SRC 28 +-#define NSS_PORT1_RX_DIV_CLK_SRC 29 +-#define NSS_PORT1_TX_DIV_CLK_SRC 30 +-#define NSS_PORT2_RX_DIV_CLK_SRC 31 +-#define NSS_PORT2_TX_DIV_CLK_SRC 32 +-#define NSS_PORT3_RX_DIV_CLK_SRC 33 +-#define NSS_PORT3_TX_DIV_CLK_SRC 34 +-#define NSS_PORT4_RX_DIV_CLK_SRC 35 +-#define NSS_PORT4_TX_DIV_CLK_SRC 36 +-#define NSS_UBI0_CLK_SRC 37 +-#define BLSP1_QUP1_I2C_APPS_CLK_SRC 38 +-#define BLSP1_QUP1_SPI_APPS_CLK_SRC 39 +-#define BLSP1_QUP2_I2C_APPS_CLK_SRC 40 +-#define BLSP1_QUP2_SPI_APPS_CLK_SRC 41 +-#define BLSP1_QUP3_I2C_APPS_CLK_SRC 42 +-#define BLSP1_QUP3_SPI_APPS_CLK_SRC 43 +-#define BLSP1_QUP4_I2C_APPS_CLK_SRC 44 +-#define BLSP1_QUP4_SPI_APPS_CLK_SRC 45 +-#define BLSP1_QUP5_I2C_APPS_CLK_SRC 46 +-#define BLSP1_QUP5_SPI_APPS_CLK_SRC 47 +-#define BLSP1_QUP6_I2C_APPS_CLK_SRC 48 +-#define BLSP1_QUP6_SPI_APPS_CLK_SRC 49 +-#define BLSP1_UART1_APPS_CLK_SRC 50 +-#define BLSP1_UART2_APPS_CLK_SRC 51 +-#define BLSP1_UART3_APPS_CLK_SRC 52 +-#define BLSP1_UART4_APPS_CLK_SRC 53 +-#define BLSP1_UART5_APPS_CLK_SRC 54 +-#define BLSP1_UART6_APPS_CLK_SRC 55 +-#define CRYPTO_CLK_SRC 56 +-#define NSS_UBI0_DIV_CLK_SRC 57 +-#define PCIE0_AUX_CLK_SRC 58 +-#define PCIE0_PIPE_CLK_SRC 59 +-#define SDCC1_APPS_CLK_SRC 60 +-#define USB0_AUX_CLK_SRC 61 +-#define USB0_MOCK_UTMI_CLK_SRC 62 +-#define USB0_PIPE_CLK_SRC 63 +-#define USB1_MOCK_UTMI_CLK_SRC 64 +-#define GCC_APSS_AHB_CLK 65 +-#define GCC_APSS_AXI_CLK 66 +-#define GCC_BLSP1_AHB_CLK 67 +-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 68 +-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 69 +-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 70 +-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 71 +-#define GCC_BLSP1_QUP3_I2C_APPS_CLK 72 +-#define GCC_BLSP1_QUP3_SPI_APPS_CLK 73 +-#define GCC_BLSP1_QUP4_I2C_APPS_CLK 74 +-#define GCC_BLSP1_QUP4_SPI_APPS_CLK 75 +-#define GCC_BLSP1_QUP5_I2C_APPS_CLK 76 +-#define GCC_BLSP1_QUP5_SPI_APPS_CLK 77 +-#define GCC_BLSP1_QUP6_I2C_APPS_CLK 78 +-#define GCC_BLSP1_QUP6_SPI_APPS_CLK 79 +-#define GCC_BLSP1_UART1_APPS_CLK 80 +-#define GCC_BLSP1_UART2_APPS_CLK 81 +-#define GCC_BLSP1_UART3_APPS_CLK 82 +-#define GCC_BLSP1_UART4_APPS_CLK 83 +-#define GCC_BLSP1_UART5_APPS_CLK 84 +-#define GCC_BLSP1_UART6_APPS_CLK 85 +-#define GCC_CRYPTO_AHB_CLK 86 +-#define GCC_CRYPTO_AXI_CLK 87 +-#define GCC_CRYPTO_CLK 88 +-#define GCC_XO_CLK 89 +-#define GCC_XO_DIV4_CLK 90 +-#define GCC_MDIO_AHB_CLK 91 +-#define GCC_CRYPTO_PPE_CLK 92 +-#define GCC_NSS_CE_APB_CLK 93 +-#define GCC_NSS_CE_AXI_CLK 94 +-#define GCC_NSS_CFG_CLK 95 +-#define GCC_NSS_CRYPTO_CLK 96 +-#define GCC_NSS_CSR_CLK 97 +-#define GCC_NSS_EDMA_CFG_CLK 98 +-#define GCC_NSS_EDMA_CLK 99 +-#define GCC_NSS_NOC_CLK 100 +-#define GCC_NSS_PORT1_RX_CLK 101 +-#define GCC_NSS_PORT1_TX_CLK 102 +-#define GCC_NSS_PORT2_RX_CLK 103 +-#define GCC_NSS_PORT2_TX_CLK 104 +-#define GCC_NSS_PORT3_RX_CLK 105 +-#define GCC_NSS_PORT3_TX_CLK 106 +-#define GCC_NSS_PORT4_RX_CLK 107 +-#define GCC_NSS_PORT4_TX_CLK 108 +-#define GCC_NSS_PORT5_RX_CLK 109 +-#define GCC_NSS_PORT5_TX_CLK 110 +-#define GCC_NSS_PPE_CFG_CLK 111 +-#define GCC_NSS_PPE_CLK 112 +-#define GCC_NSS_PPE_IPE_CLK 113 +-#define GCC_NSS_PTP_REF_CLK 114 +-#define GCC_NSSNOC_CE_APB_CLK 115 +-#define GCC_NSSNOC_CE_AXI_CLK 116 +-#define GCC_NSSNOC_CRYPTO_CLK 117 +-#define GCC_NSSNOC_PPE_CFG_CLK 118 +-#define GCC_NSSNOC_PPE_CLK 119 +-#define GCC_NSSNOC_QOSGEN_REF_CLK 120 +-#define GCC_NSSNOC_TIMEOUT_REF_CLK 121 +-#define GCC_NSSNOC_UBI0_AHB_CLK 122 +-#define GCC_PORT1_MAC_CLK 123 +-#define GCC_PORT2_MAC_CLK 124 +-#define GCC_PORT3_MAC_CLK 125 +-#define GCC_PORT4_MAC_CLK 126 +-#define GCC_PORT5_MAC_CLK 127 +-#define GCC_UBI0_AHB_CLK 128 +-#define GCC_UBI0_AXI_CLK 129 +-#define GCC_UBI0_CORE_CLK 130 +-#define GCC_PCIE0_AHB_CLK 131 +-#define GCC_PCIE0_AUX_CLK 132 +-#define GCC_PCIE0_AXI_M_CLK 133 +-#define GCC_PCIE0_AXI_S_CLK 134 +-#define GCC_PCIE0_PIPE_CLK 135 +-#define GCC_PRNG_AHB_CLK 136 +-#define GCC_QPIC_AHB_CLK 137 +-#define GCC_QPIC_CLK 138 +-#define GCC_SDCC1_AHB_CLK 139 +-#define GCC_SDCC1_APPS_CLK 140 +-#define GCC_UNIPHY0_AHB_CLK 141 +-#define GCC_UNIPHY0_PORT1_RX_CLK 142 +-#define GCC_UNIPHY0_PORT1_TX_CLK 143 +-#define GCC_UNIPHY0_PORT2_RX_CLK 144 +-#define GCC_UNIPHY0_PORT2_TX_CLK 145 +-#define GCC_UNIPHY0_PORT3_RX_CLK 146 +-#define GCC_UNIPHY0_PORT3_TX_CLK 147 +-#define GCC_UNIPHY0_PORT4_RX_CLK 148 +-#define GCC_UNIPHY0_PORT4_TX_CLK 149 +-#define GCC_UNIPHY0_PORT5_RX_CLK 150 +-#define GCC_UNIPHY0_PORT5_TX_CLK 151 +-#define GCC_UNIPHY0_SYS_CLK 152 +-#define GCC_UNIPHY1_AHB_CLK 153 +-#define GCC_UNIPHY1_PORT5_RX_CLK 154 +-#define GCC_UNIPHY1_PORT5_TX_CLK 155 +-#define GCC_UNIPHY1_SYS_CLK 156 +-#define GCC_USB0_AUX_CLK 157 +-#define GCC_USB0_MASTER_CLK 158 +-#define GCC_USB0_MOCK_UTMI_CLK 159 +-#define GCC_USB0_PHY_CFG_AHB_CLK 160 +-#define GCC_USB0_PIPE_CLK 161 +-#define GCC_USB0_SLEEP_CLK 162 +-#define GCC_USB1_MASTER_CLK 163 +-#define GCC_USB1_MOCK_UTMI_CLK 164 +-#define GCC_USB1_PHY_CFG_AHB_CLK 165 +-#define GCC_USB1_SLEEP_CLK 166 +-#define GP1_CLK_SRC 167 +-#define GP2_CLK_SRC 168 +-#define GP3_CLK_SRC 169 +-#define GCC_GP1_CLK 170 +-#define GCC_GP2_CLK 171 +-#define GCC_GP3_CLK 172 +-#define SYSTEM_NOC_BFDCD_CLK_SRC 173 +-#define GCC_NSSNOC_SNOC_CLK 174 +-#define GCC_UBI0_NC_AXI_CLK 175 +-#define GCC_UBI1_NC_AXI_CLK 176 +-#define GPLL0_MAIN 177 +-#define UBI32_PLL_MAIN 178 +-#define GPLL6_MAIN 179 +-#define GPLL4_MAIN 180 +-#define GPLL2_MAIN 181 +-#define NSS_CRYPTO_PLL_MAIN 182 +-#define GCC_CMN_12GPLL_AHB_CLK 183 +-#define GCC_CMN_12GPLL_SYS_CLK 184 +-#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 185 +-#define GCC_SYS_NOC_USB0_AXI_CLK 186 +-#define GCC_SYS_NOC_PCIE0_AXI_CLK 187 +-#define QDSS_TSCTR_CLK_SRC 188 +-#define QDSS_AT_CLK_SRC 189 +-#define GCC_QDSS_AT_CLK 190 +-#define GCC_QDSS_DAP_CLK 191 +-#define ADSS_PWM_CLK_SRC 192 +-#define GCC_ADSS_PWM_CLK 193 +-#define SDCC1_ICE_CORE_CLK_SRC 194 +-#define GCC_SDCC1_ICE_CORE_CLK 195 +-#define GCC_DCC_CLK 196 +-#define PCIE0_RCHNG_CLK_SRC 197 +-#define GCC_PCIE0_AXI_S_BRIDGE_CLK 198 +-#define PCIE0_RCHNG_CLK 199 +-#define UBI32_MEM_NOC_BFDCD_CLK_SRC 200 +-#define WCSS_AHB_CLK_SRC 201 +-#define Q6_AXI_CLK_SRC 202 +-#define GCC_Q6SS_PCLKDBG_CLK 203 +-#define GCC_Q6_TSCTR_1TO2_CLK 204 +-#define GCC_WCSS_CORE_TBU_CLK 205 +-#define GCC_WCSS_AXI_M_CLK 206 +-#define GCC_SYS_NOC_WCSS_AHB_CLK 207 +-#define GCC_Q6_AXIM_CLK 208 +-#define GCC_Q6SS_ATBM_CLK 209 +-#define GCC_WCSS_Q6_TBU_CLK 210 +-#define GCC_Q6_AXIM2_CLK 211 +-#define GCC_Q6_AHB_CLK 212 +-#define GCC_Q6_AHB_S_CLK 213 +-#define GCC_WCSS_DBG_IFC_APB_CLK 214 +-#define GCC_WCSS_DBG_IFC_ATB_CLK 215 +-#define GCC_WCSS_DBG_IFC_NTS_CLK 216 +-#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 217 +-#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 218 +-#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 219 +-#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 220 +-#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 221 +-#define GCC_WCSS_ECAHB_CLK 222 +-#define GCC_WCSS_ACMT_CLK 223 +-#define GCC_WCSS_AHB_S_CLK 224 +-#define GCC_RBCPR_WCSS_CLK 225 +-#define RBCPR_WCSS_CLK_SRC 226 +-#define GCC_RBCPR_WCSS_AHB_CLK 227 +-#define GCC_LPASS_CORE_AXIM_CLK 228 +-#define GCC_LPASS_SNOC_CFG_CLK 229 +-#define GCC_LPASS_Q6_AXIM_CLK 230 +-#define GCC_LPASS_Q6_ATBM_AT_CLK 231 +-#define GCC_LPASS_Q6_PCLKDBG_CLK 232 +-#define GCC_LPASS_Q6SS_TSCTR_1TO2_CLK 233 +-#define GCC_LPASS_Q6SS_TRIG_CLK 234 +-#define GCC_LPASS_TBU_CLK 235 +-#define LPASS_CORE_AXIM_CLK_SRC 236 +-#define LPASS_SNOC_CFG_CLK_SRC 237 +-#define LPASS_Q6_AXIM_CLK_SRC 238 +-#define GCC_PCNOC_LPASS_CLK 239 +-#define GCC_UBI0_UTCM_CLK 240 +-#define SNOC_NSSNOC_BFDCD_CLK_SRC 241 +-#define GCC_SNOC_NSSNOC_CLK 242 +-#define GCC_MEM_NOC_Q6_AXI_CLK 243 +-#define GCC_MEM_NOC_UBI32_CLK 244 +-#define GCC_MEM_NOC_LPASS_CLK 245 +-#define GCC_SNOC_LPASS_CFG_CLK 246 +-#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 247 +-#define GCC_QDSS_STM_CLK 248 +-#define GCC_QDSS_TRACECLKIN_CLK 249 +-#define QDSS_STM_CLK_SRC 250 +-#define QDSS_TRACECLKIN_CLK_SRC 251 +-#define GCC_NSSNOC_ATB_CLK 252 +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq806x.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq806x.h +deleted file mode 100644 +index 7deec14a6dee..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq806x.h ++++ /dev/null +@@ -1,287 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H +-#define _DT_BINDINGS_CLK_GCC_IPQ806X_H +- +-#define AFAB_CLK_SRC 0 +-#define QDSS_STM_CLK 1 +-#define SCSS_A_CLK 2 +-#define SCSS_H_CLK 3 +-#define AFAB_CORE_CLK 4 +-#define SCSS_XO_SRC_CLK 5 +-#define AFAB_EBI1_CH0_A_CLK 6 +-#define AFAB_EBI1_CH1_A_CLK 7 +-#define AFAB_AXI_S0_FCLK 8 +-#define AFAB_AXI_S1_FCLK 9 +-#define AFAB_AXI_S2_FCLK 10 +-#define AFAB_AXI_S3_FCLK 11 +-#define AFAB_AXI_S4_FCLK 12 +-#define SFAB_CORE_CLK 13 +-#define SFAB_AXI_S0_FCLK 14 +-#define SFAB_AXI_S1_FCLK 15 +-#define SFAB_AXI_S2_FCLK 16 +-#define SFAB_AXI_S3_FCLK 17 +-#define SFAB_AXI_S4_FCLK 18 +-#define SFAB_AXI_S5_FCLK 19 +-#define SFAB_AHB_S0_FCLK 20 +-#define SFAB_AHB_S1_FCLK 21 +-#define SFAB_AHB_S2_FCLK 22 +-#define SFAB_AHB_S3_FCLK 23 +-#define SFAB_AHB_S4_FCLK 24 +-#define SFAB_AHB_S5_FCLK 25 +-#define SFAB_AHB_S6_FCLK 26 +-#define SFAB_AHB_S7_FCLK 27 +-#define QDSS_AT_CLK_SRC 28 +-#define QDSS_AT_CLK 29 +-#define QDSS_TRACECLKIN_CLK_SRC 30 +-#define QDSS_TRACECLKIN_CLK 31 +-#define QDSS_TSCTR_CLK_SRC 32 +-#define QDSS_TSCTR_CLK 33 +-#define SFAB_ADM0_M0_A_CLK 34 +-#define SFAB_ADM0_M1_A_CLK 35 +-#define SFAB_ADM0_M2_H_CLK 36 +-#define ADM0_CLK 37 +-#define ADM0_PBUS_CLK 38 +-#define IMEM0_A_CLK 39 +-#define QDSS_H_CLK 40 +-#define PCIE_A_CLK 41 +-#define PCIE_AUX_CLK 42 +-#define PCIE_H_CLK 43 +-#define PCIE_PHY_CLK 44 +-#define SFAB_CLK_SRC 45 +-#define SFAB_LPASS_Q6_A_CLK 46 +-#define SFAB_AFAB_M_A_CLK 47 +-#define AFAB_SFAB_M0_A_CLK 48 +-#define AFAB_SFAB_M1_A_CLK 49 +-#define SFAB_SATA_S_H_CLK 50 +-#define DFAB_CLK_SRC 51 +-#define DFAB_CLK 52 +-#define SFAB_DFAB_M_A_CLK 53 +-#define DFAB_SFAB_M_A_CLK 54 +-#define DFAB_SWAY0_H_CLK 55 +-#define DFAB_SWAY1_H_CLK 56 +-#define DFAB_ARB0_H_CLK 57 +-#define DFAB_ARB1_H_CLK 58 +-#define PPSS_H_CLK 59 +-#define PPSS_PROC_CLK 60 +-#define PPSS_TIMER0_CLK 61 +-#define PPSS_TIMER1_CLK 62 +-#define PMEM_A_CLK 63 +-#define DMA_BAM_H_CLK 64 +-#define SIC_H_CLK 65 +-#define SPS_TIC_H_CLK 66 +-#define CFPB_2X_CLK_SRC 67 +-#define CFPB_CLK 68 +-#define CFPB0_H_CLK 69 +-#define CFPB1_H_CLK 70 +-#define CFPB2_H_CLK 71 +-#define SFAB_CFPB_M_H_CLK 72 +-#define CFPB_MASTER_H_CLK 73 +-#define SFAB_CFPB_S_H_CLK 74 +-#define CFPB_SPLITTER_H_CLK 75 +-#define TSIF_H_CLK 76 +-#define TSIF_INACTIVITY_TIMERS_CLK 77 +-#define TSIF_REF_SRC 78 +-#define TSIF_REF_CLK 79 +-#define CE1_H_CLK 80 +-#define CE1_CORE_CLK 81 +-#define CE1_SLEEP_CLK 82 +-#define CE2_H_CLK 83 +-#define CE2_CORE_CLK 84 +-#define SFPB_H_CLK_SRC 85 +-#define SFPB_H_CLK 86 +-#define SFAB_SFPB_M_H_CLK 87 +-#define SFAB_SFPB_S_H_CLK 88 +-#define RPM_PROC_CLK 89 +-#define RPM_BUS_H_CLK 90 +-#define RPM_SLEEP_CLK 91 +-#define RPM_TIMER_CLK 92 +-#define RPM_MSG_RAM_H_CLK 93 +-#define PMIC_ARB0_H_CLK 94 +-#define PMIC_ARB1_H_CLK 95 +-#define PMIC_SSBI2_SRC 96 +-#define PMIC_SSBI2_CLK 97 +-#define SDC1_H_CLK 98 +-#define SDC2_H_CLK 99 +-#define SDC3_H_CLK 100 +-#define SDC4_H_CLK 101 +-#define SDC1_SRC 102 +-#define SDC1_CLK 103 +-#define SDC2_SRC 104 +-#define SDC2_CLK 105 +-#define SDC3_SRC 106 +-#define SDC3_CLK 107 +-#define SDC4_SRC 108 +-#define SDC4_CLK 109 +-#define USB_HS1_H_CLK 110 +-#define USB_HS1_XCVR_SRC 111 +-#define USB_HS1_XCVR_CLK 112 +-#define USB_HSIC_H_CLK 113 +-#define USB_HSIC_XCVR_SRC 114 +-#define USB_HSIC_XCVR_CLK 115 +-#define USB_HSIC_SYSTEM_CLK_SRC 116 +-#define USB_HSIC_SYSTEM_CLK 117 +-#define CFPB0_C0_H_CLK 118 +-#define CFPB0_D0_H_CLK 119 +-#define CFPB0_C1_H_CLK 120 +-#define CFPB0_D1_H_CLK 121 +-#define USB_FS1_H_CLK 122 +-#define USB_FS1_XCVR_SRC 123 +-#define USB_FS1_XCVR_CLK 124 +-#define USB_FS1_SYSTEM_CLK 125 +-#define GSBI_COMMON_SIM_SRC 126 +-#define GSBI1_H_CLK 127 +-#define GSBI2_H_CLK 128 +-#define GSBI3_H_CLK 129 +-#define GSBI4_H_CLK 130 +-#define GSBI5_H_CLK 131 +-#define GSBI6_H_CLK 132 +-#define GSBI7_H_CLK 133 +-#define GSBI1_QUP_SRC 134 +-#define GSBI1_QUP_CLK 135 +-#define GSBI2_QUP_SRC 136 +-#define GSBI2_QUP_CLK 137 +-#define GSBI3_QUP_SRC 138 +-#define GSBI3_QUP_CLK 139 +-#define GSBI4_QUP_SRC 140 +-#define GSBI4_QUP_CLK 141 +-#define GSBI5_QUP_SRC 142 +-#define GSBI5_QUP_CLK 143 +-#define GSBI6_QUP_SRC 144 +-#define GSBI6_QUP_CLK 145 +-#define GSBI7_QUP_SRC 146 +-#define GSBI7_QUP_CLK 147 +-#define GSBI1_UART_SRC 148 +-#define GSBI1_UART_CLK 149 +-#define GSBI2_UART_SRC 150 +-#define GSBI2_UART_CLK 151 +-#define GSBI3_UART_SRC 152 +-#define GSBI3_UART_CLK 153 +-#define GSBI4_UART_SRC 154 +-#define GSBI4_UART_CLK 155 +-#define GSBI5_UART_SRC 156 +-#define GSBI5_UART_CLK 157 +-#define GSBI6_UART_SRC 158 +-#define GSBI6_UART_CLK 159 +-#define GSBI7_UART_SRC 160 +-#define GSBI7_UART_CLK 161 +-#define GSBI1_SIM_CLK 162 +-#define GSBI2_SIM_CLK 163 +-#define GSBI3_SIM_CLK 164 +-#define GSBI4_SIM_CLK 165 +-#define GSBI5_SIM_CLK 166 +-#define GSBI6_SIM_CLK 167 +-#define GSBI7_SIM_CLK 168 +-#define USB_HSIC_HSIC_CLK_SRC 169 +-#define USB_HSIC_HSIC_CLK 170 +-#define USB_HSIC_HSIO_CAL_CLK 171 +-#define SPDM_CFG_H_CLK 172 +-#define SPDM_MSTR_H_CLK 173 +-#define SPDM_FF_CLK_SRC 174 +-#define SPDM_FF_CLK 175 +-#define SEC_CTRL_CLK 176 +-#define SEC_CTRL_ACC_CLK_SRC 177 +-#define SEC_CTRL_ACC_CLK 178 +-#define TLMM_H_CLK 179 +-#define TLMM_CLK 180 +-#define SATA_H_CLK 181 +-#define SATA_CLK_SRC 182 +-#define SATA_RXOOB_CLK 183 +-#define SATA_PMALIVE_CLK 184 +-#define SATA_PHY_REF_CLK 185 +-#define SATA_A_CLK 186 +-#define SATA_PHY_CFG_CLK 187 +-#define TSSC_CLK_SRC 188 +-#define TSSC_CLK 189 +-#define PDM_SRC 190 +-#define PDM_CLK 191 +-#define GP0_SRC 192 +-#define GP0_CLK 193 +-#define GP1_SRC 194 +-#define GP1_CLK 195 +-#define GP2_SRC 196 +-#define GP2_CLK 197 +-#define MPM_CLK 198 +-#define EBI1_CLK_SRC 199 +-#define EBI1_CH0_CLK 200 +-#define EBI1_CH1_CLK 201 +-#define EBI1_2X_CLK 202 +-#define EBI1_CH0_DQ_CLK 203 +-#define EBI1_CH1_DQ_CLK 204 +-#define EBI1_CH0_CA_CLK 205 +-#define EBI1_CH1_CA_CLK 206 +-#define EBI1_XO_CLK 207 +-#define SFAB_SMPSS_S_H_CLK 208 +-#define PRNG_SRC 209 +-#define PRNG_CLK 210 +-#define PXO_SRC 211 +-#define SPDM_CY_PORT0_CLK 212 +-#define SPDM_CY_PORT1_CLK 213 +-#define SPDM_CY_PORT2_CLK 214 +-#define SPDM_CY_PORT3_CLK 215 +-#define SPDM_CY_PORT4_CLK 216 +-#define SPDM_CY_PORT5_CLK 217 +-#define SPDM_CY_PORT6_CLK 218 +-#define SPDM_CY_PORT7_CLK 219 +-#define PLL0 220 +-#define PLL0_VOTE 221 +-#define PLL3 222 +-#define PLL3_VOTE 223 +-#define PLL4_VOTE 225 +-#define PLL8 226 +-#define PLL8_VOTE 227 +-#define PLL9 228 +-#define PLL10 229 +-#define PLL11 230 +-#define PLL12 231 +-#define PLL14 232 +-#define PLL14_VOTE 233 +-#define PLL18 234 +-#define CE5_SRC 235 +-#define CE5_H_CLK 236 +-#define CE5_CORE_CLK 237 +-#define CE3_SLEEP_CLK 238 +-#define SFAB_AHB_S8_FCLK 239 +-#define SPDM_CY_PORT8_CLK 246 +-#define PCIE_ALT_REF_SRC 247 +-#define PCIE_ALT_REF_CLK 248 +-#define PCIE_1_A_CLK 249 +-#define PCIE_1_AUX_CLK 250 +-#define PCIE_1_H_CLK 251 +-#define PCIE_1_PHY_CLK 252 +-#define PCIE_1_ALT_REF_SRC 253 +-#define PCIE_1_ALT_REF_CLK 254 +-#define PCIE_2_A_CLK 255 +-#define PCIE_2_AUX_CLK 256 +-#define PCIE_2_H_CLK 257 +-#define PCIE_2_PHY_CLK 258 +-#define PCIE_2_ALT_REF_SRC 259 +-#define PCIE_2_ALT_REF_CLK 260 +-#define EBI2_CLK 261 +-#define USB30_SLEEP_CLK 262 +-#define USB30_UTMI_SRC 263 +-#define USB30_0_UTMI_CLK 264 +-#define USB30_1_UTMI_CLK 265 +-#define USB30_MASTER_SRC 266 +-#define USB30_0_MASTER_CLK 267 +-#define USB30_1_MASTER_CLK 268 +-#define GMAC_CORE1_CLK_SRC 269 +-#define GMAC_CORE2_CLK_SRC 270 +-#define GMAC_CORE3_CLK_SRC 271 +-#define GMAC_CORE4_CLK_SRC 272 +-#define GMAC_CORE1_CLK 273 +-#define GMAC_CORE2_CLK 274 +-#define GMAC_CORE3_CLK 275 +-#define GMAC_CORE4_CLK 276 +-#define UBI32_CORE1_CLK_SRC 277 +-#define UBI32_CORE2_CLK_SRC 278 +-#define UBI32_CORE1_CLK 279 +-#define UBI32_CORE2_CLK 280 +-#define EBI2_AON_CLK 281 +-#define NSSTCM_CLK_SRC 282 +-#define NSSTCM_CLK 283 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq8074.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq8074.h +deleted file mode 100644 +index 8e2bec1c91bf..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq8074.h ++++ /dev/null +@@ -1,370 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H +-#define _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H +- +-#define GPLL0 0 +-#define GPLL0_MAIN 1 +-#define GCC_SLEEP_CLK_SRC 2 +-#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3 +-#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4 +-#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5 +-#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6 +-#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7 +-#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8 +-#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9 +-#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10 +-#define BLSP1_QUP5_I2C_APPS_CLK_SRC 11 +-#define BLSP1_QUP5_SPI_APPS_CLK_SRC 12 +-#define BLSP1_QUP6_I2C_APPS_CLK_SRC 13 +-#define BLSP1_QUP6_SPI_APPS_CLK_SRC 14 +-#define BLSP1_UART1_APPS_CLK_SRC 15 +-#define BLSP1_UART2_APPS_CLK_SRC 16 +-#define BLSP1_UART3_APPS_CLK_SRC 17 +-#define BLSP1_UART4_APPS_CLK_SRC 18 +-#define BLSP1_UART5_APPS_CLK_SRC 19 +-#define BLSP1_UART6_APPS_CLK_SRC 20 +-#define GCC_BLSP1_AHB_CLK 21 +-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22 +-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23 +-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24 +-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25 +-#define GCC_BLSP1_QUP3_I2C_APPS_CLK 26 +-#define GCC_BLSP1_QUP3_SPI_APPS_CLK 27 +-#define GCC_BLSP1_QUP4_I2C_APPS_CLK 28 +-#define GCC_BLSP1_QUP4_SPI_APPS_CLK 29 +-#define GCC_BLSP1_QUP5_I2C_APPS_CLK 30 +-#define GCC_BLSP1_QUP5_SPI_APPS_CLK 31 +-#define GCC_BLSP1_QUP6_I2C_APPS_CLK 32 +-#define GCC_BLSP1_QUP6_SPI_APPS_CLK 33 +-#define GCC_BLSP1_UART1_APPS_CLK 34 +-#define GCC_BLSP1_UART2_APPS_CLK 35 +-#define GCC_BLSP1_UART3_APPS_CLK 36 +-#define GCC_BLSP1_UART4_APPS_CLK 37 +-#define GCC_BLSP1_UART5_APPS_CLK 38 +-#define GCC_BLSP1_UART6_APPS_CLK 39 +-#define GCC_PRNG_AHB_CLK 40 +-#define GCC_QPIC_AHB_CLK 41 +-#define GCC_QPIC_CLK 42 +-#define PCNOC_BFDCD_CLK_SRC 43 +-#define GPLL2_MAIN 44 +-#define GPLL2 45 +-#define GPLL4_MAIN 46 +-#define GPLL4 47 +-#define GPLL6_MAIN 48 +-#define GPLL6 49 +-#define UBI32_PLL_MAIN 50 +-#define UBI32_PLL 51 +-#define NSS_CRYPTO_PLL_MAIN 52 +-#define NSS_CRYPTO_PLL 53 +-#define PCIE0_AXI_CLK_SRC 54 +-#define PCIE0_AUX_CLK_SRC 55 +-#define PCIE0_PIPE_CLK_SRC 56 +-#define PCIE1_AXI_CLK_SRC 57 +-#define PCIE1_AUX_CLK_SRC 58 +-#define PCIE1_PIPE_CLK_SRC 59 +-#define SDCC1_APPS_CLK_SRC 60 +-#define SDCC1_ICE_CORE_CLK_SRC 61 +-#define SDCC2_APPS_CLK_SRC 62 +-#define USB0_MASTER_CLK_SRC 63 +-#define USB0_AUX_CLK_SRC 64 +-#define USB0_MOCK_UTMI_CLK_SRC 65 +-#define USB0_PIPE_CLK_SRC 66 +-#define USB1_MASTER_CLK_SRC 67 +-#define USB1_AUX_CLK_SRC 68 +-#define USB1_MOCK_UTMI_CLK_SRC 69 +-#define USB1_PIPE_CLK_SRC 70 +-#define GCC_XO_CLK_SRC 71 +-#define SYSTEM_NOC_BFDCD_CLK_SRC 72 +-#define NSS_CE_CLK_SRC 73 +-#define NSS_NOC_BFDCD_CLK_SRC 74 +-#define NSS_CRYPTO_CLK_SRC 75 +-#define NSS_UBI0_CLK_SRC 76 +-#define NSS_UBI0_DIV_CLK_SRC 77 +-#define NSS_UBI1_CLK_SRC 78 +-#define NSS_UBI1_DIV_CLK_SRC 79 +-#define UBI_MPT_CLK_SRC 80 +-#define NSS_IMEM_CLK_SRC 81 +-#define NSS_PPE_CLK_SRC 82 +-#define NSS_PORT1_RX_CLK_SRC 83 +-#define NSS_PORT1_RX_DIV_CLK_SRC 84 +-#define NSS_PORT1_TX_CLK_SRC 85 +-#define NSS_PORT1_TX_DIV_CLK_SRC 86 +-#define NSS_PORT2_RX_CLK_SRC 87 +-#define NSS_PORT2_RX_DIV_CLK_SRC 88 +-#define NSS_PORT2_TX_CLK_SRC 89 +-#define NSS_PORT2_TX_DIV_CLK_SRC 90 +-#define NSS_PORT3_RX_CLK_SRC 91 +-#define NSS_PORT3_RX_DIV_CLK_SRC 92 +-#define NSS_PORT3_TX_CLK_SRC 93 +-#define NSS_PORT3_TX_DIV_CLK_SRC 94 +-#define NSS_PORT4_RX_CLK_SRC 95 +-#define NSS_PORT4_RX_DIV_CLK_SRC 96 +-#define NSS_PORT4_TX_CLK_SRC 97 +-#define NSS_PORT4_TX_DIV_CLK_SRC 98 +-#define NSS_PORT5_RX_CLK_SRC 99 +-#define NSS_PORT5_RX_DIV_CLK_SRC 100 +-#define NSS_PORT5_TX_CLK_SRC 101 +-#define NSS_PORT5_TX_DIV_CLK_SRC 102 +-#define NSS_PORT6_RX_CLK_SRC 103 +-#define NSS_PORT6_RX_DIV_CLK_SRC 104 +-#define NSS_PORT6_TX_CLK_SRC 105 +-#define NSS_PORT6_TX_DIV_CLK_SRC 106 +-#define CRYPTO_CLK_SRC 107 +-#define GP1_CLK_SRC 108 +-#define GP2_CLK_SRC 109 +-#define GP3_CLK_SRC 110 +-#define GCC_PCIE0_AHB_CLK 111 +-#define GCC_PCIE0_AUX_CLK 112 +-#define GCC_PCIE0_AXI_M_CLK 113 +-#define GCC_PCIE0_AXI_S_CLK 114 +-#define GCC_PCIE0_PIPE_CLK 115 +-#define GCC_SYS_NOC_PCIE0_AXI_CLK 116 +-#define GCC_PCIE1_AHB_CLK 117 +-#define GCC_PCIE1_AUX_CLK 118 +-#define GCC_PCIE1_AXI_M_CLK 119 +-#define GCC_PCIE1_AXI_S_CLK 120 +-#define GCC_PCIE1_PIPE_CLK 121 +-#define GCC_SYS_NOC_PCIE1_AXI_CLK 122 +-#define GCC_USB0_AUX_CLK 123 +-#define GCC_SYS_NOC_USB0_AXI_CLK 124 +-#define GCC_USB0_MASTER_CLK 125 +-#define GCC_USB0_MOCK_UTMI_CLK 126 +-#define GCC_USB0_PHY_CFG_AHB_CLK 127 +-#define GCC_USB0_PIPE_CLK 128 +-#define GCC_USB0_SLEEP_CLK 129 +-#define GCC_USB1_AUX_CLK 130 +-#define GCC_SYS_NOC_USB1_AXI_CLK 131 +-#define GCC_USB1_MASTER_CLK 132 +-#define GCC_USB1_MOCK_UTMI_CLK 133 +-#define GCC_USB1_PHY_CFG_AHB_CLK 134 +-#define GCC_USB1_PIPE_CLK 135 +-#define GCC_USB1_SLEEP_CLK 136 +-#define GCC_SDCC1_AHB_CLK 137 +-#define GCC_SDCC1_APPS_CLK 138 +-#define GCC_SDCC1_ICE_CORE_CLK 139 +-#define GCC_SDCC2_AHB_CLK 140 +-#define GCC_SDCC2_APPS_CLK 141 +-#define GCC_MEM_NOC_NSS_AXI_CLK 142 +-#define GCC_NSS_CE_APB_CLK 143 +-#define GCC_NSS_CE_AXI_CLK 144 +-#define GCC_NSS_CFG_CLK 145 +-#define GCC_NSS_CRYPTO_CLK 146 +-#define GCC_NSS_CSR_CLK 147 +-#define GCC_NSS_EDMA_CFG_CLK 148 +-#define GCC_NSS_EDMA_CLK 149 +-#define GCC_NSS_IMEM_CLK 150 +-#define GCC_NSS_NOC_CLK 151 +-#define GCC_NSS_PPE_BTQ_CLK 152 +-#define GCC_NSS_PPE_CFG_CLK 153 +-#define GCC_NSS_PPE_CLK 154 +-#define GCC_NSS_PPE_IPE_CLK 155 +-#define GCC_NSS_PTP_REF_CLK 156 +-#define GCC_NSSNOC_CE_APB_CLK 157 +-#define GCC_NSSNOC_CE_AXI_CLK 158 +-#define GCC_NSSNOC_CRYPTO_CLK 159 +-#define GCC_NSSNOC_PPE_CFG_CLK 160 +-#define GCC_NSSNOC_PPE_CLK 161 +-#define GCC_NSSNOC_QOSGEN_REF_CLK 162 +-#define GCC_NSSNOC_SNOC_CLK 163 +-#define GCC_NSSNOC_TIMEOUT_REF_CLK 164 +-#define GCC_NSSNOC_UBI0_AHB_CLK 165 +-#define GCC_NSSNOC_UBI1_AHB_CLK 166 +-#define GCC_UBI0_AHB_CLK 167 +-#define GCC_UBI0_AXI_CLK 168 +-#define GCC_UBI0_NC_AXI_CLK 169 +-#define GCC_UBI0_CORE_CLK 170 +-#define GCC_UBI0_MPT_CLK 171 +-#define GCC_UBI1_AHB_CLK 172 +-#define GCC_UBI1_AXI_CLK 173 +-#define GCC_UBI1_NC_AXI_CLK 174 +-#define GCC_UBI1_CORE_CLK 175 +-#define GCC_UBI1_MPT_CLK 176 +-#define GCC_CMN_12GPLL_AHB_CLK 177 +-#define GCC_CMN_12GPLL_SYS_CLK 178 +-#define GCC_MDIO_AHB_CLK 179 +-#define GCC_UNIPHY0_AHB_CLK 180 +-#define GCC_UNIPHY0_SYS_CLK 181 +-#define GCC_UNIPHY1_AHB_CLK 182 +-#define GCC_UNIPHY1_SYS_CLK 183 +-#define GCC_UNIPHY2_AHB_CLK 184 +-#define GCC_UNIPHY2_SYS_CLK 185 +-#define GCC_NSS_PORT1_RX_CLK 186 +-#define GCC_NSS_PORT1_TX_CLK 187 +-#define GCC_NSS_PORT2_RX_CLK 188 +-#define GCC_NSS_PORT2_TX_CLK 189 +-#define GCC_NSS_PORT3_RX_CLK 190 +-#define GCC_NSS_PORT3_TX_CLK 191 +-#define GCC_NSS_PORT4_RX_CLK 192 +-#define GCC_NSS_PORT4_TX_CLK 193 +-#define GCC_NSS_PORT5_RX_CLK 194 +-#define GCC_NSS_PORT5_TX_CLK 195 +-#define GCC_NSS_PORT6_RX_CLK 196 +-#define GCC_NSS_PORT6_TX_CLK 197 +-#define GCC_PORT1_MAC_CLK 198 +-#define GCC_PORT2_MAC_CLK 199 +-#define GCC_PORT3_MAC_CLK 200 +-#define GCC_PORT4_MAC_CLK 201 +-#define GCC_PORT5_MAC_CLK 202 +-#define GCC_PORT6_MAC_CLK 203 +-#define GCC_UNIPHY0_PORT1_RX_CLK 204 +-#define GCC_UNIPHY0_PORT1_TX_CLK 205 +-#define GCC_UNIPHY0_PORT2_RX_CLK 206 +-#define GCC_UNIPHY0_PORT2_TX_CLK 207 +-#define GCC_UNIPHY0_PORT3_RX_CLK 208 +-#define GCC_UNIPHY0_PORT3_TX_CLK 209 +-#define GCC_UNIPHY0_PORT4_RX_CLK 210 +-#define GCC_UNIPHY0_PORT4_TX_CLK 211 +-#define GCC_UNIPHY0_PORT5_RX_CLK 212 +-#define GCC_UNIPHY0_PORT5_TX_CLK 213 +-#define GCC_UNIPHY1_PORT5_RX_CLK 214 +-#define GCC_UNIPHY1_PORT5_TX_CLK 215 +-#define GCC_UNIPHY2_PORT6_RX_CLK 216 +-#define GCC_UNIPHY2_PORT6_TX_CLK 217 +-#define GCC_CRYPTO_AHB_CLK 218 +-#define GCC_CRYPTO_AXI_CLK 219 +-#define GCC_CRYPTO_CLK 220 +-#define GCC_GP1_CLK 221 +-#define GCC_GP2_CLK 222 +-#define GCC_GP3_CLK 223 +-#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 +-#define GCC_PCIE0_RCHNG_CLK_SRC 225 +-#define GCC_PCIE0_RCHNG_CLK 226 +- +-#define GCC_BLSP1_BCR 0 +-#define GCC_BLSP1_QUP1_BCR 1 +-#define GCC_BLSP1_UART1_BCR 2 +-#define GCC_BLSP1_QUP2_BCR 3 +-#define GCC_BLSP1_UART2_BCR 4 +-#define GCC_BLSP1_QUP3_BCR 5 +-#define GCC_BLSP1_UART3_BCR 6 +-#define GCC_BLSP1_QUP4_BCR 7 +-#define GCC_BLSP1_UART4_BCR 8 +-#define GCC_BLSP1_QUP5_BCR 9 +-#define GCC_BLSP1_UART5_BCR 10 +-#define GCC_BLSP1_QUP6_BCR 11 +-#define GCC_BLSP1_UART6_BCR 12 +-#define GCC_IMEM_BCR 13 +-#define GCC_SMMU_BCR 14 +-#define GCC_APSS_TCU_BCR 15 +-#define GCC_SMMU_XPU_BCR 16 +-#define GCC_PCNOC_TBU_BCR 17 +-#define GCC_SMMU_CFG_BCR 18 +-#define GCC_PRNG_BCR 19 +-#define GCC_BOOT_ROM_BCR 20 +-#define GCC_CRYPTO_BCR 21 +-#define GCC_WCSS_BCR 22 +-#define GCC_WCSS_Q6_BCR 23 +-#define GCC_NSS_BCR 24 +-#define GCC_SEC_CTRL_BCR 25 +-#define GCC_ADSS_BCR 26 +-#define GCC_DDRSS_BCR 27 +-#define GCC_SYSTEM_NOC_BCR 28 +-#define GCC_PCNOC_BCR 29 +-#define GCC_TCSR_BCR 30 +-#define GCC_QDSS_BCR 31 +-#define GCC_DCD_BCR 32 +-#define GCC_MSG_RAM_BCR 33 +-#define GCC_MPM_BCR 34 +-#define GCC_SPMI_BCR 35 +-#define GCC_SPDM_BCR 36 +-#define GCC_RBCPR_BCR 37 +-#define GCC_RBCPR_MX_BCR 38 +-#define GCC_TLMM_BCR 39 +-#define GCC_RBCPR_WCSS_BCR 40 +-#define GCC_USB0_PHY_BCR 41 +-#define GCC_USB3PHY_0_PHY_BCR 42 +-#define GCC_USB0_BCR 43 +-#define GCC_USB1_PHY_BCR 44 +-#define GCC_USB3PHY_1_PHY_BCR 45 +-#define GCC_USB1_BCR 46 +-#define GCC_QUSB2_0_PHY_BCR 47 +-#define GCC_QUSB2_1_PHY_BCR 48 +-#define GCC_SDCC1_BCR 49 +-#define GCC_SDCC2_BCR 50 +-#define GCC_SNOC_BUS_TIMEOUT0_BCR 51 +-#define GCC_SNOC_BUS_TIMEOUT2_BCR 52 +-#define GCC_SNOC_BUS_TIMEOUT3_BCR 53 +-#define GCC_PCNOC_BUS_TIMEOUT0_BCR 54 +-#define GCC_PCNOC_BUS_TIMEOUT1_BCR 55 +-#define GCC_PCNOC_BUS_TIMEOUT2_BCR 56 +-#define GCC_PCNOC_BUS_TIMEOUT3_BCR 57 +-#define GCC_PCNOC_BUS_TIMEOUT4_BCR 58 +-#define GCC_PCNOC_BUS_TIMEOUT5_BCR 59 +-#define GCC_PCNOC_BUS_TIMEOUT6_BCR 60 +-#define GCC_PCNOC_BUS_TIMEOUT7_BCR 61 +-#define GCC_PCNOC_BUS_TIMEOUT8_BCR 62 +-#define GCC_PCNOC_BUS_TIMEOUT9_BCR 63 +-#define GCC_UNIPHY0_BCR 64 +-#define GCC_UNIPHY1_BCR 65 +-#define GCC_UNIPHY2_BCR 66 +-#define GCC_CMN_12GPLL_BCR 67 +-#define GCC_QPIC_BCR 68 +-#define GCC_MDIO_BCR 69 +-#define GCC_PCIE1_TBU_BCR 70 +-#define GCC_WCSS_CORE_TBU_BCR 71 +-#define GCC_WCSS_Q6_TBU_BCR 72 +-#define GCC_USB0_TBU_BCR 73 +-#define GCC_USB1_TBU_BCR 74 +-#define GCC_PCIE0_TBU_BCR 75 +-#define GCC_NSS_NOC_TBU_BCR 76 +-#define GCC_PCIE0_BCR 77 +-#define GCC_PCIE0_PHY_BCR 78 +-#define GCC_PCIE0PHY_PHY_BCR 79 +-#define GCC_PCIE0_LINK_DOWN_BCR 80 +-#define GCC_PCIE1_BCR 81 +-#define GCC_PCIE1_PHY_BCR 82 +-#define GCC_PCIE1PHY_PHY_BCR 83 +-#define GCC_PCIE1_LINK_DOWN_BCR 84 +-#define GCC_DCC_BCR 85 +-#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 86 +-#define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR 87 +-#define GCC_SMMU_CATS_BCR 88 +-#define GCC_UBI0_AXI_ARES 89 +-#define GCC_UBI0_AHB_ARES 90 +-#define GCC_UBI0_NC_AXI_ARES 91 +-#define GCC_UBI0_DBG_ARES 92 +-#define GCC_UBI0_CORE_CLAMP_ENABLE 93 +-#define GCC_UBI0_CLKRST_CLAMP_ENABLE 94 +-#define GCC_UBI1_AXI_ARES 95 +-#define GCC_UBI1_AHB_ARES 96 +-#define GCC_UBI1_NC_AXI_ARES 97 +-#define GCC_UBI1_DBG_ARES 98 +-#define GCC_UBI1_CORE_CLAMP_ENABLE 99 +-#define GCC_UBI1_CLKRST_CLAMP_ENABLE 100 +-#define GCC_NSS_CFG_ARES 101 +-#define GCC_NSS_IMEM_ARES 102 +-#define GCC_NSS_NOC_ARES 103 +-#define GCC_NSS_CRYPTO_ARES 104 +-#define GCC_NSS_CSR_ARES 105 +-#define GCC_NSS_CE_APB_ARES 106 +-#define GCC_NSS_CE_AXI_ARES 107 +-#define GCC_NSSNOC_CE_APB_ARES 108 +-#define GCC_NSSNOC_CE_AXI_ARES 109 +-#define GCC_NSSNOC_UBI0_AHB_ARES 110 +-#define GCC_NSSNOC_UBI1_AHB_ARES 111 +-#define GCC_NSSNOC_SNOC_ARES 112 +-#define GCC_NSSNOC_CRYPTO_ARES 113 +-#define GCC_NSSNOC_ATB_ARES 114 +-#define GCC_NSSNOC_QOSGEN_REF_ARES 115 +-#define GCC_NSSNOC_TIMEOUT_REF_ARES 116 +-#define GCC_PCIE0_PIPE_ARES 117 +-#define GCC_PCIE0_SLEEP_ARES 118 +-#define GCC_PCIE0_CORE_STICKY_ARES 119 +-#define GCC_PCIE0_AXI_MASTER_ARES 120 +-#define GCC_PCIE0_AXI_SLAVE_ARES 121 +-#define GCC_PCIE0_AHB_ARES 122 +-#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 123 +-#define GCC_PCIE1_PIPE_ARES 124 +-#define GCC_PCIE1_SLEEP_ARES 125 +-#define GCC_PCIE1_CORE_STICKY_ARES 126 +-#define GCC_PCIE1_AXI_MASTER_ARES 127 +-#define GCC_PCIE1_AXI_SLAVE_ARES 128 +-#define GCC_PCIE1_AHB_ARES 129 +-#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 +-#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-mdm9607.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-mdm9607.h +deleted file mode 100644 +index 357a680a40da..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-mdm9607.h ++++ /dev/null +@@ -1,104 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ +-/* +- * Copyright (c) 2021, Konrad Dybcio +- */ +- +-#ifndef _DT_BINDINGS_CLK_MSM_GCC_9607_H +-#define _DT_BINDINGS_CLK_MSM_GCC_9607_H +- +-#define GPLL0 0 +-#define GPLL0_EARLY 1 +-#define GPLL1 2 +-#define GPLL1_VOTE 3 +-#define GPLL2 4 +-#define GPLL2_EARLY 5 +-#define PCNOC_BFDCD_CLK_SRC 6 +-#define SYSTEM_NOC_BFDCD_CLK_SRC 7 +-#define GCC_SMMU_CFG_CLK 8 +-#define APSS_AHB_CLK_SRC 9 +-#define GCC_QDSS_DAP_CLK 10 +-#define BLSP1_QUP1_I2C_APPS_CLK_SRC 11 +-#define BLSP1_QUP1_SPI_APPS_CLK_SRC 12 +-#define BLSP1_QUP2_I2C_APPS_CLK_SRC 13 +-#define BLSP1_QUP2_SPI_APPS_CLK_SRC 14 +-#define BLSP1_QUP3_I2C_APPS_CLK_SRC 15 +-#define BLSP1_QUP3_SPI_APPS_CLK_SRC 16 +-#define BLSP1_QUP4_I2C_APPS_CLK_SRC 17 +-#define BLSP1_QUP4_SPI_APPS_CLK_SRC 18 +-#define BLSP1_QUP5_I2C_APPS_CLK_SRC 19 +-#define BLSP1_QUP5_SPI_APPS_CLK_SRC 20 +-#define BLSP1_QUP6_I2C_APPS_CLK_SRC 21 +-#define BLSP1_QUP6_SPI_APPS_CLK_SRC 22 +-#define BLSP1_UART1_APPS_CLK_SRC 23 +-#define BLSP1_UART2_APPS_CLK_SRC 24 +-#define CRYPTO_CLK_SRC 25 +-#define GP1_CLK_SRC 26 +-#define GP2_CLK_SRC 27 +-#define GP3_CLK_SRC 28 +-#define PDM2_CLK_SRC 29 +-#define SDCC1_APPS_CLK_SRC 30 +-#define SDCC2_APPS_CLK_SRC 31 +-#define APSS_TCU_CLK_SRC 32 +-#define USB_HS_SYSTEM_CLK_SRC 33 +-#define GCC_BLSP1_AHB_CLK 34 +-#define GCC_BLSP1_SLEEP_CLK 35 +-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 36 +-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 37 +-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 38 +-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 39 +-#define GCC_BLSP1_QUP3_I2C_APPS_CLK 40 +-#define GCC_BLSP1_QUP3_SPI_APPS_CLK 41 +-#define GCC_BLSP1_QUP4_I2C_APPS_CLK 42 +-#define GCC_BLSP1_QUP4_SPI_APPS_CLK 43 +-#define GCC_BLSP1_QUP5_I2C_APPS_CLK 44 +-#define GCC_BLSP1_QUP5_SPI_APPS_CLK 45 +-#define GCC_BLSP1_QUP6_I2C_APPS_CLK 46 +-#define GCC_BLSP1_QUP6_SPI_APPS_CLK 47 +-#define GCC_BLSP1_UART1_APPS_CLK 48 +-#define GCC_BLSP1_UART2_APPS_CLK 49 +-#define GCC_BOOT_ROM_AHB_CLK 50 +-#define GCC_CRYPTO_AHB_CLK 51 +-#define GCC_CRYPTO_AXI_CLK 52 +-#define GCC_CRYPTO_CLK 53 +-#define GCC_GP1_CLK 54 +-#define GCC_GP2_CLK 55 +-#define GCC_GP3_CLK 56 +-#define GCC_MSS_CFG_AHB_CLK 57 +-#define GCC_PDM2_CLK 58 +-#define GCC_PDM_AHB_CLK 59 +-#define GCC_PRNG_AHB_CLK 60 +-#define GCC_SDCC1_AHB_CLK 61 +-#define GCC_SDCC1_APPS_CLK 62 +-#define GCC_SDCC2_AHB_CLK 63 +-#define GCC_SDCC2_APPS_CLK 64 +-#define GCC_USB2A_PHY_SLEEP_CLK 65 +-#define GCC_USB_HS_AHB_CLK 66 +-#define GCC_USB_HS_SYSTEM_CLK 67 +-#define GCC_APSS_TCU_CLK 68 +-#define GCC_MSS_Q6_BIMC_AXI_CLK 69 +-#define BIMC_PLL 70 +-#define BIMC_PLL_VOTE 71 +-#define BIMC_DDR_CLK_SRC 72 +-#define BLSP1_UART3_APPS_CLK_SRC 73 +-#define BLSP1_UART4_APPS_CLK_SRC 74 +-#define BLSP1_UART5_APPS_CLK_SRC 75 +-#define BLSP1_UART6_APPS_CLK_SRC 76 +-#define GCC_BLSP1_UART3_APPS_CLK 77 +-#define GCC_BLSP1_UART4_APPS_CLK 78 +-#define GCC_BLSP1_UART5_APPS_CLK 79 +-#define GCC_BLSP1_UART6_APPS_CLK 80 +-#define GCC_APSS_AHB_CLK 81 +-#define GCC_APSS_AXI_CLK 82 +-#define GCC_USB_HS_PHY_CFG_AHB_CLK 83 +-#define GCC_USB_HSIC_CLK_SRC 84 +-#define GCC_USB_HSIC_IO_CAL_CLK_SRC 85 +-#define GCC_USB_HSIC_SYSTEM_CLK_SRC 86 +- +-/* Resets */ +-#define USB2_HS_PHY_ONLY_BCR 0 +-#define QUSB2_PHY_BCR 1 +-#define GCC_MSS_RESTART 2 +-#define USB_HS_HSIC_BCR 3 +-#define USB_HS_BCR 4 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-mdm9615.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-mdm9615.h +deleted file mode 100644 +index 9e4c34823dad..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-mdm9615.h ++++ /dev/null +@@ -1,321 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2013, The Linux Foundation. All rights reserved. +- * Copyright (c) BayLibre, SAS. +- * Author : Neil Armstrong +- */ +- +-#ifndef _DT_BINDINGS_CLK_MDM_GCC_9615_H +-#define _DT_BINDINGS_CLK_MDM_GCC_9615_H +- +-#define AFAB_CLK_SRC 0 +-#define AFAB_CORE_CLK 1 +-#define SFAB_MSS_Q6_SW_A_CLK 2 +-#define SFAB_MSS_Q6_FW_A_CLK 3 +-#define QDSS_STM_CLK 4 +-#define SCSS_A_CLK 5 +-#define SCSS_H_CLK 6 +-#define SCSS_XO_SRC_CLK 7 +-#define AFAB_EBI1_CH0_A_CLK 8 +-#define AFAB_EBI1_CH1_A_CLK 9 +-#define AFAB_AXI_S0_FCLK 10 +-#define AFAB_AXI_S1_FCLK 11 +-#define AFAB_AXI_S2_FCLK 12 +-#define AFAB_AXI_S3_FCLK 13 +-#define AFAB_AXI_S4_FCLK 14 +-#define SFAB_CORE_CLK 15 +-#define SFAB_AXI_S0_FCLK 16 +-#define SFAB_AXI_S1_FCLK 17 +-#define SFAB_AXI_S2_FCLK 18 +-#define SFAB_AXI_S3_FCLK 19 +-#define SFAB_AXI_S4_FCLK 20 +-#define SFAB_AHB_S0_FCLK 21 +-#define SFAB_AHB_S1_FCLK 22 +-#define SFAB_AHB_S2_FCLK 23 +-#define SFAB_AHB_S3_FCLK 24 +-#define SFAB_AHB_S4_FCLK 25 +-#define SFAB_AHB_S5_FCLK 26 +-#define SFAB_AHB_S6_FCLK 27 +-#define SFAB_AHB_S7_FCLK 28 +-#define QDSS_AT_CLK_SRC 29 +-#define QDSS_AT_CLK 30 +-#define QDSS_TRACECLKIN_CLK_SRC 31 +-#define QDSS_TRACECLKIN_CLK 32 +-#define QDSS_TSCTR_CLK_SRC 33 +-#define QDSS_TSCTR_CLK 34 +-#define SFAB_ADM0_M0_A_CLK 35 +-#define SFAB_ADM0_M1_A_CLK 36 +-#define SFAB_ADM0_M2_H_CLK 37 +-#define ADM0_CLK 38 +-#define ADM0_PBUS_CLK 39 +-#define MSS_XPU_CLK 40 +-#define IMEM0_A_CLK 41 +-#define QDSS_H_CLK 42 +-#define PCIE_A_CLK 43 +-#define PCIE_AUX_CLK 44 +-#define PCIE_PHY_REF_CLK 45 +-#define PCIE_H_CLK 46 +-#define SFAB_CLK_SRC 47 +-#define MAHB0_CLK 48 +-#define Q6SW_CLK_SRC 49 +-#define Q6SW_CLK 50 +-#define Q6FW_CLK_SRC 51 +-#define Q6FW_CLK 52 +-#define SFAB_MSS_M_A_CLK 53 +-#define SFAB_USB3_M_A_CLK 54 +-#define SFAB_LPASS_Q6_A_CLK 55 +-#define SFAB_AFAB_M_A_CLK 56 +-#define AFAB_SFAB_M0_A_CLK 57 +-#define AFAB_SFAB_M1_A_CLK 58 +-#define SFAB_SATA_S_H_CLK 59 +-#define DFAB_CLK_SRC 60 +-#define DFAB_CLK 61 +-#define SFAB_DFAB_M_A_CLK 62 +-#define DFAB_SFAB_M_A_CLK 63 +-#define DFAB_SWAY0_H_CLK 64 +-#define DFAB_SWAY1_H_CLK 65 +-#define DFAB_ARB0_H_CLK 66 +-#define DFAB_ARB1_H_CLK 67 +-#define PPSS_H_CLK 68 +-#define PPSS_PROC_CLK 69 +-#define PPSS_TIMER0_CLK 70 +-#define PPSS_TIMER1_CLK 71 +-#define PMEM_A_CLK 72 +-#define DMA_BAM_H_CLK 73 +-#define SIC_H_CLK 74 +-#define SPS_TIC_H_CLK 75 +-#define SLIMBUS_H_CLK 76 +-#define SLIMBUS_XO_SRC_CLK 77 +-#define CFPB_2X_CLK_SRC 78 +-#define CFPB_CLK 79 +-#define CFPB0_H_CLK 80 +-#define CFPB1_H_CLK 81 +-#define CFPB2_H_CLK 82 +-#define SFAB_CFPB_M_H_CLK 83 +-#define CFPB_MASTER_H_CLK 84 +-#define SFAB_CFPB_S_H_CLK 85 +-#define CFPB_SPLITTER_H_CLK 86 +-#define TSIF_H_CLK 87 +-#define TSIF_INACTIVITY_TIMERS_CLK 88 +-#define TSIF_REF_SRC 89 +-#define TSIF_REF_CLK 90 +-#define CE1_H_CLK 91 +-#define CE1_CORE_CLK 92 +-#define CE1_SLEEP_CLK 93 +-#define CE2_H_CLK 94 +-#define CE2_CORE_CLK 95 +-#define SFPB_H_CLK_SRC 97 +-#define SFPB_H_CLK 98 +-#define SFAB_SFPB_M_H_CLK 99 +-#define SFAB_SFPB_S_H_CLK 100 +-#define RPM_PROC_CLK 101 +-#define RPM_BUS_H_CLK 102 +-#define RPM_SLEEP_CLK 103 +-#define RPM_TIMER_CLK 104 +-#define RPM_MSG_RAM_H_CLK 105 +-#define PMIC_ARB0_H_CLK 106 +-#define PMIC_ARB1_H_CLK 107 +-#define PMIC_SSBI2_SRC 108 +-#define PMIC_SSBI2_CLK 109 +-#define SDC1_H_CLK 110 +-#define SDC2_H_CLK 111 +-#define SDC3_H_CLK 112 +-#define SDC4_H_CLK 113 +-#define SDC5_H_CLK 114 +-#define SDC1_SRC 115 +-#define SDC2_SRC 116 +-#define SDC3_SRC 117 +-#define SDC4_SRC 118 +-#define SDC5_SRC 119 +-#define SDC1_CLK 120 +-#define SDC2_CLK 121 +-#define SDC3_CLK 122 +-#define SDC4_CLK 123 +-#define SDC5_CLK 124 +-#define DFAB_A2_H_CLK 125 +-#define USB_HS1_H_CLK 126 +-#define USB_HS1_XCVR_SRC 127 +-#define USB_HS1_XCVR_CLK 128 +-#define USB_HSIC_H_CLK 129 +-#define USB_HSIC_XCVR_FS_SRC 130 +-#define USB_HSIC_XCVR_FS_CLK 131 +-#define USB_HSIC_SYSTEM_CLK_SRC 132 +-#define USB_HSIC_SYSTEM_CLK 133 +-#define CFPB0_C0_H_CLK 134 +-#define CFPB0_C1_H_CLK 135 +-#define CFPB0_D0_H_CLK 136 +-#define CFPB0_D1_H_CLK 137 +-#define USB_FS1_H_CLK 138 +-#define USB_FS1_XCVR_FS_SRC 139 +-#define USB_FS1_XCVR_FS_CLK 140 +-#define USB_FS1_SYSTEM_CLK 141 +-#define USB_FS2_H_CLK 142 +-#define USB_FS2_XCVR_FS_SRC 143 +-#define USB_FS2_XCVR_FS_CLK 144 +-#define USB_FS2_SYSTEM_CLK 145 +-#define GSBI_COMMON_SIM_SRC 146 +-#define GSBI1_H_CLK 147 +-#define GSBI2_H_CLK 148 +-#define GSBI3_H_CLK 149 +-#define GSBI4_H_CLK 150 +-#define GSBI5_H_CLK 151 +-#define GSBI6_H_CLK 152 +-#define GSBI7_H_CLK 153 +-#define GSBI8_H_CLK 154 +-#define GSBI9_H_CLK 155 +-#define GSBI10_H_CLK 156 +-#define GSBI11_H_CLK 157 +-#define GSBI12_H_CLK 158 +-#define GSBI1_UART_SRC 159 +-#define GSBI1_UART_CLK 160 +-#define GSBI2_UART_SRC 161 +-#define GSBI2_UART_CLK 162 +-#define GSBI3_UART_SRC 163 +-#define GSBI3_UART_CLK 164 +-#define GSBI4_UART_SRC 165 +-#define GSBI4_UART_CLK 166 +-#define GSBI5_UART_SRC 167 +-#define GSBI5_UART_CLK 168 +-#define GSBI6_UART_SRC 169 +-#define GSBI6_UART_CLK 170 +-#define GSBI7_UART_SRC 171 +-#define GSBI7_UART_CLK 172 +-#define GSBI8_UART_SRC 173 +-#define GSBI8_UART_CLK 174 +-#define GSBI9_UART_SRC 175 +-#define GSBI9_UART_CLK 176 +-#define GSBI10_UART_SRC 177 +-#define GSBI10_UART_CLK 178 +-#define GSBI11_UART_SRC 179 +-#define GSBI11_UART_CLK 180 +-#define GSBI12_UART_SRC 181 +-#define GSBI12_UART_CLK 182 +-#define GSBI1_QUP_SRC 183 +-#define GSBI1_QUP_CLK 184 +-#define GSBI2_QUP_SRC 185 +-#define GSBI2_QUP_CLK 186 +-#define GSBI3_QUP_SRC 187 +-#define GSBI3_QUP_CLK 188 +-#define GSBI4_QUP_SRC 189 +-#define GSBI4_QUP_CLK 190 +-#define GSBI5_QUP_SRC 191 +-#define GSBI5_QUP_CLK 192 +-#define GSBI6_QUP_SRC 193 +-#define GSBI6_QUP_CLK 194 +-#define GSBI7_QUP_SRC 195 +-#define GSBI7_QUP_CLK 196 +-#define GSBI8_QUP_SRC 197 +-#define GSBI8_QUP_CLK 198 +-#define GSBI9_QUP_SRC 199 +-#define GSBI9_QUP_CLK 200 +-#define GSBI10_QUP_SRC 201 +-#define GSBI10_QUP_CLK 202 +-#define GSBI11_QUP_SRC 203 +-#define GSBI11_QUP_CLK 204 +-#define GSBI12_QUP_SRC 205 +-#define GSBI12_QUP_CLK 206 +-#define GSBI1_SIM_CLK 207 +-#define GSBI2_SIM_CLK 208 +-#define GSBI3_SIM_CLK 209 +-#define GSBI4_SIM_CLK 210 +-#define GSBI5_SIM_CLK 211 +-#define GSBI6_SIM_CLK 212 +-#define GSBI7_SIM_CLK 213 +-#define GSBI8_SIM_CLK 214 +-#define GSBI9_SIM_CLK 215 +-#define GSBI10_SIM_CLK 216 +-#define GSBI11_SIM_CLK 217 +-#define GSBI12_SIM_CLK 218 +-#define USB_HSIC_HSIC_CLK_SRC 219 +-#define USB_HSIC_HSIC_CLK 220 +-#define USB_HSIC_HSIO_CAL_CLK 221 +-#define SPDM_CFG_H_CLK 222 +-#define SPDM_MSTR_H_CLK 223 +-#define SPDM_FF_CLK_SRC 224 +-#define SPDM_FF_CLK 225 +-#define SEC_CTRL_CLK 226 +-#define SEC_CTRL_ACC_CLK_SRC 227 +-#define SEC_CTRL_ACC_CLK 228 +-#define TLMM_H_CLK 229 +-#define TLMM_CLK 230 +-#define SFAB_MSS_S_H_CLK 231 +-#define MSS_SLP_CLK 232 +-#define MSS_Q6SW_JTAG_CLK 233 +-#define MSS_Q6FW_JTAG_CLK 234 +-#define MSS_S_H_CLK 235 +-#define MSS_CXO_SRC_CLK 236 +-#define SATA_H_CLK 237 +-#define SATA_CLK_SRC 238 +-#define SATA_RXOOB_CLK 239 +-#define SATA_PMALIVE_CLK 240 +-#define SATA_PHY_REF_CLK 241 +-#define TSSC_CLK_SRC 242 +-#define TSSC_CLK 243 +-#define PDM_SRC 244 +-#define PDM_CLK 245 +-#define GP0_SRC 246 +-#define GP0_CLK 247 +-#define GP1_SRC 248 +-#define GP1_CLK 249 +-#define GP2_SRC 250 +-#define GP2_CLK 251 +-#define MPM_CLK 252 +-#define EBI1_CLK_SRC 253 +-#define EBI1_CH0_CLK 254 +-#define EBI1_CH1_CLK 255 +-#define EBI1_2X_CLK 256 +-#define EBI1_CH0_DQ_CLK 257 +-#define EBI1_CH1_DQ_CLK 258 +-#define EBI1_CH0_CA_CLK 259 +-#define EBI1_CH1_CA_CLK 260 +-#define EBI1_XO_CLK 261 +-#define SFAB_SMPSS_S_H_CLK 262 +-#define PRNG_SRC 263 +-#define PRNG_CLK 264 +-#define PXO_SRC 265 +-#define LPASS_CXO_CLK 266 +-#define LPASS_PXO_CLK 267 +-#define SPDM_CY_PORT0_CLK 268 +-#define SPDM_CY_PORT1_CLK 269 +-#define SPDM_CY_PORT2_CLK 270 +-#define SPDM_CY_PORT3_CLK 271 +-#define SPDM_CY_PORT4_CLK 272 +-#define SPDM_CY_PORT5_CLK 273 +-#define SPDM_CY_PORT6_CLK 274 +-#define SPDM_CY_PORT7_CLK 275 +-#define PLL0 276 +-#define PLL0_VOTE 277 +-#define PLL3 278 +-#define PLL3_VOTE 279 +-#define PLL4_VOTE 280 +-#define PLL5 281 +-#define PLL5_VOTE 282 +-#define PLL6 283 +-#define PLL6_VOTE 284 +-#define PLL7_VOTE 285 +-#define PLL8 286 +-#define PLL8_VOTE 287 +-#define PLL9 288 +-#define PLL10 289 +-#define PLL11 290 +-#define PLL12 291 +-#define PLL13 292 +-#define PLL14 293 +-#define PLL14_VOTE 294 +-#define USB_HS3_H_CLK 295 +-#define USB_HS3_XCVR_SRC 296 +-#define USB_HS3_XCVR_CLK 297 +-#define USB_HS4_H_CLK 298 +-#define USB_HS4_XCVR_SRC 299 +-#define USB_HS4_XCVR_CLK 300 +-#define SATA_PHY_CFG_CLK 301 +-#define SATA_A_CLK 302 +-#define CE3_SRC 303 +-#define CE3_CORE_CLK 304 +-#define CE3_H_CLK 305 +-#define USB_HS1_SYSTEM_CLK_SRC 306 +-#define USB_HS1_SYSTEM_CLK 307 +-#define EBI2_CLK 308 +-#define EBI2_AON_CLK 309 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8660.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8660.h +deleted file mode 100644 +index 4777c002711a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8660.h ++++ /dev/null +@@ -1,268 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2013, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_MSM_GCC_8660_H +-#define _DT_BINDINGS_CLK_MSM_GCC_8660_H +- +-#define AFAB_CLK_SRC 0 +-#define AFAB_CORE_CLK 1 +-#define SCSS_A_CLK 2 +-#define SCSS_H_CLK 3 +-#define SCSS_XO_SRC_CLK 4 +-#define AFAB_EBI1_CH0_A_CLK 5 +-#define AFAB_EBI1_CH1_A_CLK 6 +-#define AFAB_AXI_S0_FCLK 7 +-#define AFAB_AXI_S1_FCLK 8 +-#define AFAB_AXI_S2_FCLK 9 +-#define AFAB_AXI_S3_FCLK 10 +-#define AFAB_AXI_S4_FCLK 11 +-#define SFAB_CORE_CLK 12 +-#define SFAB_AXI_S0_FCLK 13 +-#define SFAB_AXI_S1_FCLK 14 +-#define SFAB_AXI_S2_FCLK 15 +-#define SFAB_AXI_S3_FCLK 16 +-#define SFAB_AXI_S4_FCLK 17 +-#define SFAB_AHB_S0_FCLK 18 +-#define SFAB_AHB_S1_FCLK 19 +-#define SFAB_AHB_S2_FCLK 20 +-#define SFAB_AHB_S3_FCLK 21 +-#define SFAB_AHB_S4_FCLK 22 +-#define SFAB_AHB_S5_FCLK 23 +-#define SFAB_AHB_S6_FCLK 24 +-#define SFAB_ADM0_M0_A_CLK 25 +-#define SFAB_ADM0_M1_A_CLK 26 +-#define SFAB_ADM0_M2_A_CLK 27 +-#define ADM0_CLK 28 +-#define ADM0_PBUS_CLK 29 +-#define SFAB_ADM1_M0_A_CLK 30 +-#define SFAB_ADM1_M1_A_CLK 31 +-#define SFAB_ADM1_M2_A_CLK 32 +-#define MMFAB_ADM1_M3_A_CLK 33 +-#define ADM1_CLK 34 +-#define ADM1_PBUS_CLK 35 +-#define IMEM0_A_CLK 36 +-#define MAHB0_CLK 37 +-#define SFAB_LPASS_Q6_A_CLK 38 +-#define SFAB_AFAB_M_A_CLK 39 +-#define AFAB_SFAB_M0_A_CLK 40 +-#define AFAB_SFAB_M1_A_CLK 41 +-#define DFAB_CLK_SRC 42 +-#define DFAB_CLK 43 +-#define DFAB_CORE_CLK 44 +-#define SFAB_DFAB_M_A_CLK 45 +-#define DFAB_SFAB_M_A_CLK 46 +-#define DFAB_SWAY0_H_CLK 47 +-#define DFAB_SWAY1_H_CLK 48 +-#define DFAB_ARB0_H_CLK 49 +-#define DFAB_ARB1_H_CLK 50 +-#define PPSS_H_CLK 51 +-#define PPSS_PROC_CLK 52 +-#define PPSS_TIMER0_CLK 53 +-#define PPSS_TIMER1_CLK 54 +-#define PMEM_A_CLK 55 +-#define DMA_BAM_H_CLK 56 +-#define SIC_H_CLK 57 +-#define SPS_TIC_H_CLK 58 +-#define SLIMBUS_H_CLK 59 +-#define SLIMBUS_XO_SRC_CLK 60 +-#define CFPB_2X_CLK_SRC 61 +-#define CFPB_CLK 62 +-#define CFPB0_H_CLK 63 +-#define CFPB1_H_CLK 64 +-#define CFPB2_H_CLK 65 +-#define EBI2_2X_CLK 66 +-#define EBI2_CLK 67 +-#define SFAB_CFPB_M_H_CLK 68 +-#define CFPB_MASTER_H_CLK 69 +-#define SFAB_CFPB_S_HCLK 70 +-#define CFPB_SPLITTER_H_CLK 71 +-#define TSIF_H_CLK 72 +-#define TSIF_INACTIVITY_TIMERS_CLK 73 +-#define TSIF_REF_SRC 74 +-#define TSIF_REF_CLK 75 +-#define CE1_H_CLK 76 +-#define CE2_H_CLK 77 +-#define SFPB_H_CLK_SRC 78 +-#define SFPB_H_CLK 79 +-#define SFAB_SFPB_M_H_CLK 80 +-#define SFAB_SFPB_S_H_CLK 81 +-#define RPM_PROC_CLK 82 +-#define RPM_BUS_H_CLK 83 +-#define RPM_SLEEP_CLK 84 +-#define RPM_TIMER_CLK 85 +-#define MODEM_AHB1_H_CLK 86 +-#define MODEM_AHB2_H_CLK 87 +-#define RPM_MSG_RAM_H_CLK 88 +-#define SC_H_CLK 89 +-#define SC_A_CLK 90 +-#define PMIC_ARB0_H_CLK 91 +-#define PMIC_ARB1_H_CLK 92 +-#define PMIC_SSBI2_SRC 93 +-#define PMIC_SSBI2_CLK 94 +-#define SDC1_H_CLK 95 +-#define SDC2_H_CLK 96 +-#define SDC3_H_CLK 97 +-#define SDC4_H_CLK 98 +-#define SDC5_H_CLK 99 +-#define SDC1_SRC 100 +-#define SDC2_SRC 101 +-#define SDC3_SRC 102 +-#define SDC4_SRC 103 +-#define SDC5_SRC 104 +-#define SDC1_CLK 105 +-#define SDC2_CLK 106 +-#define SDC3_CLK 107 +-#define SDC4_CLK 108 +-#define SDC5_CLK 109 +-#define USB_HS1_H_CLK 110 +-#define USB_HS1_XCVR_SRC 111 +-#define USB_HS1_XCVR_CLK 112 +-#define USB_HS2_H_CLK 113 +-#define USB_HS2_XCVR_SRC 114 +-#define USB_HS2_XCVR_CLK 115 +-#define USB_FS1_H_CLK 116 +-#define USB_FS1_XCVR_FS_SRC 117 +-#define USB_FS1_XCVR_FS_CLK 118 +-#define USB_FS1_SYSTEM_CLK 119 +-#define USB_FS2_H_CLK 120 +-#define USB_FS2_XCVR_FS_SRC 121 +-#define USB_FS2_XCVR_FS_CLK 122 +-#define USB_FS2_SYSTEM_CLK 123 +-#define GSBI_COMMON_SIM_SRC 124 +-#define GSBI1_H_CLK 125 +-#define GSBI2_H_CLK 126 +-#define GSBI3_H_CLK 127 +-#define GSBI4_H_CLK 128 +-#define GSBI5_H_CLK 129 +-#define GSBI6_H_CLK 130 +-#define GSBI7_H_CLK 131 +-#define GSBI8_H_CLK 132 +-#define GSBI9_H_CLK 133 +-#define GSBI10_H_CLK 134 +-#define GSBI11_H_CLK 135 +-#define GSBI12_H_CLK 136 +-#define GSBI1_UART_SRC 137 +-#define GSBI1_UART_CLK 138 +-#define GSBI2_UART_SRC 139 +-#define GSBI2_UART_CLK 140 +-#define GSBI3_UART_SRC 141 +-#define GSBI3_UART_CLK 142 +-#define GSBI4_UART_SRC 143 +-#define GSBI4_UART_CLK 144 +-#define GSBI5_UART_SRC 145 +-#define GSBI5_UART_CLK 146 +-#define GSBI6_UART_SRC 147 +-#define GSBI6_UART_CLK 148 +-#define GSBI7_UART_SRC 149 +-#define GSBI7_UART_CLK 150 +-#define GSBI8_UART_SRC 151 +-#define GSBI8_UART_CLK 152 +-#define GSBI9_UART_SRC 153 +-#define GSBI9_UART_CLK 154 +-#define GSBI10_UART_SRC 155 +-#define GSBI10_UART_CLK 156 +-#define GSBI11_UART_SRC 157 +-#define GSBI11_UART_CLK 158 +-#define GSBI12_UART_SRC 159 +-#define GSBI12_UART_CLK 160 +-#define GSBI1_QUP_SRC 161 +-#define GSBI1_QUP_CLK 162 +-#define GSBI2_QUP_SRC 163 +-#define GSBI2_QUP_CLK 164 +-#define GSBI3_QUP_SRC 165 +-#define GSBI3_QUP_CLK 166 +-#define GSBI4_QUP_SRC 167 +-#define GSBI4_QUP_CLK 168 +-#define GSBI5_QUP_SRC 169 +-#define GSBI5_QUP_CLK 170 +-#define GSBI6_QUP_SRC 171 +-#define GSBI6_QUP_CLK 172 +-#define GSBI7_QUP_SRC 173 +-#define GSBI7_QUP_CLK 174 +-#define GSBI8_QUP_SRC 175 +-#define GSBI8_QUP_CLK 176 +-#define GSBI9_QUP_SRC 177 +-#define GSBI9_QUP_CLK 178 +-#define GSBI10_QUP_SRC 179 +-#define GSBI10_QUP_CLK 180 +-#define GSBI11_QUP_SRC 181 +-#define GSBI11_QUP_CLK 182 +-#define GSBI12_QUP_SRC 183 +-#define GSBI12_QUP_CLK 184 +-#define GSBI1_SIM_CLK 185 +-#define GSBI2_SIM_CLK 186 +-#define GSBI3_SIM_CLK 187 +-#define GSBI4_SIM_CLK 188 +-#define GSBI5_SIM_CLK 189 +-#define GSBI6_SIM_CLK 190 +-#define GSBI7_SIM_CLK 191 +-#define GSBI8_SIM_CLK 192 +-#define GSBI9_SIM_CLK 193 +-#define GSBI10_SIM_CLK 194 +-#define GSBI11_SIM_CLK 195 +-#define GSBI12_SIM_CLK 196 +-#define SPDM_CFG_H_CLK 197 +-#define SPDM_MSTR_H_CLK 198 +-#define SPDM_FF_CLK_SRC 199 +-#define SPDM_FF_CLK 200 +-#define SEC_CTRL_CLK 201 +-#define SEC_CTRL_ACC_CLK_SRC 202 +-#define SEC_CTRL_ACC_CLK 203 +-#define TLMM_H_CLK 204 +-#define TLMM_CLK 205 +-#define MARM_CLK_SRC 206 +-#define MARM_CLK 207 +-#define MAHB1_SRC 208 +-#define MAHB1_CLK 209 +-#define SFAB_MSS_S_H_CLK 210 +-#define MAHB2_SRC 211 +-#define MAHB2_CLK 212 +-#define MSS_MODEM_CLK_SRC 213 +-#define MSS_MODEM_CXO_CLK 214 +-#define MSS_SLP_CLK 215 +-#define MSS_SYS_REF_CLK 216 +-#define TSSC_CLK_SRC 217 +-#define TSSC_CLK 218 +-#define PDM_SRC 219 +-#define PDM_CLK 220 +-#define GP0_SRC 221 +-#define GP0_CLK 222 +-#define GP1_SRC 223 +-#define GP1_CLK 224 +-#define GP2_SRC 225 +-#define GP2_CLK 226 +-#define PMEM_CLK 227 +-#define MPM_CLK 228 +-#define EBI1_ASFAB_SRC 229 +-#define EBI1_CLK_SRC 230 +-#define EBI1_CH0_CLK 231 +-#define EBI1_CH1_CLK 232 +-#define SFAB_SMPSS_S_H_CLK 233 +-#define PRNG_SRC 234 +-#define PRNG_CLK 235 +-#define PXO_SRC 236 +-#define LPASS_CXO_CLK 237 +-#define LPASS_PXO_CLK 238 +-#define SPDM_CY_PORT0_CLK 239 +-#define SPDM_CY_PORT1_CLK 240 +-#define SPDM_CY_PORT2_CLK 241 +-#define SPDM_CY_PORT3_CLK 242 +-#define SPDM_CY_PORT4_CLK 243 +-#define SPDM_CY_PORT5_CLK 244 +-#define SPDM_CY_PORT6_CLK 245 +-#define SPDM_CY_PORT7_CLK 246 +-#define PLL0 247 +-#define PLL0_VOTE 248 +-#define PLL5 249 +-#define PLL6 250 +-#define PLL6_VOTE 251 +-#define PLL8 252 +-#define PLL8_VOTE 253 +-#define PLL9 254 +-#define PLL10 255 +-#define PLL11 256 +-#define PLL12 257 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8916.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8916.h +deleted file mode 100644 +index 563034406184..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8916.h ++++ /dev/null +@@ -1,179 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2015 Linaro Limited +- */ +- +-#ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H +-#define _DT_BINDINGS_CLK_MSM_GCC_8916_H +- +-#define GPLL0 0 +-#define GPLL0_VOTE 1 +-#define BIMC_PLL 2 +-#define BIMC_PLL_VOTE 3 +-#define GPLL1 4 +-#define GPLL1_VOTE 5 +-#define GPLL2 6 +-#define GPLL2_VOTE 7 +-#define PCNOC_BFDCD_CLK_SRC 8 +-#define SYSTEM_NOC_BFDCD_CLK_SRC 9 +-#define CAMSS_AHB_CLK_SRC 10 +-#define APSS_AHB_CLK_SRC 11 +-#define CSI0_CLK_SRC 12 +-#define CSI1_CLK_SRC 13 +-#define GFX3D_CLK_SRC 14 +-#define VFE0_CLK_SRC 15 +-#define BLSP1_QUP1_I2C_APPS_CLK_SRC 16 +-#define BLSP1_QUP1_SPI_APPS_CLK_SRC 17 +-#define BLSP1_QUP2_I2C_APPS_CLK_SRC 18 +-#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19 +-#define BLSP1_QUP3_I2C_APPS_CLK_SRC 20 +-#define BLSP1_QUP3_SPI_APPS_CLK_SRC 21 +-#define BLSP1_QUP4_I2C_APPS_CLK_SRC 22 +-#define BLSP1_QUP4_SPI_APPS_CLK_SRC 23 +-#define BLSP1_QUP5_I2C_APPS_CLK_SRC 24 +-#define BLSP1_QUP5_SPI_APPS_CLK_SRC 25 +-#define BLSP1_QUP6_I2C_APPS_CLK_SRC 26 +-#define BLSP1_QUP6_SPI_APPS_CLK_SRC 27 +-#define BLSP1_UART1_APPS_CLK_SRC 28 +-#define BLSP1_UART2_APPS_CLK_SRC 29 +-#define CCI_CLK_SRC 30 +-#define CAMSS_GP0_CLK_SRC 31 +-#define CAMSS_GP1_CLK_SRC 32 +-#define JPEG0_CLK_SRC 33 +-#define MCLK0_CLK_SRC 34 +-#define MCLK1_CLK_SRC 35 +-#define CSI0PHYTIMER_CLK_SRC 36 +-#define CSI1PHYTIMER_CLK_SRC 37 +-#define CPP_CLK_SRC 38 +-#define CRYPTO_CLK_SRC 39 +-#define GP1_CLK_SRC 40 +-#define GP2_CLK_SRC 41 +-#define GP3_CLK_SRC 42 +-#define BYTE0_CLK_SRC 43 +-#define ESC0_CLK_SRC 44 +-#define MDP_CLK_SRC 45 +-#define PCLK0_CLK_SRC 46 +-#define VSYNC_CLK_SRC 47 +-#define PDM2_CLK_SRC 48 +-#define SDCC1_APPS_CLK_SRC 49 +-#define SDCC2_APPS_CLK_SRC 50 +-#define APSS_TCU_CLK_SRC 51 +-#define USB_HS_SYSTEM_CLK_SRC 52 +-#define VCODEC0_CLK_SRC 53 +-#define GCC_BLSP1_AHB_CLK 54 +-#define GCC_BLSP1_SLEEP_CLK 55 +-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 56 +-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 57 +-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 58 +-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 59 +-#define GCC_BLSP1_QUP3_I2C_APPS_CLK 60 +-#define GCC_BLSP1_QUP3_SPI_APPS_CLK 61 +-#define GCC_BLSP1_QUP4_I2C_APPS_CLK 62 +-#define GCC_BLSP1_QUP4_SPI_APPS_CLK 63 +-#define GCC_BLSP1_QUP5_I2C_APPS_CLK 64 +-#define GCC_BLSP1_QUP5_SPI_APPS_CLK 65 +-#define GCC_BLSP1_QUP6_I2C_APPS_CLK 66 +-#define GCC_BLSP1_QUP6_SPI_APPS_CLK 67 +-#define GCC_BLSP1_UART1_APPS_CLK 68 +-#define GCC_BLSP1_UART2_APPS_CLK 69 +-#define GCC_BOOT_ROM_AHB_CLK 70 +-#define GCC_CAMSS_CCI_AHB_CLK 71 +-#define GCC_CAMSS_CCI_CLK 72 +-#define GCC_CAMSS_CSI0_AHB_CLK 73 +-#define GCC_CAMSS_CSI0_CLK 74 +-#define GCC_CAMSS_CSI0PHY_CLK 75 +-#define GCC_CAMSS_CSI0PIX_CLK 76 +-#define GCC_CAMSS_CSI0RDI_CLK 77 +-#define GCC_CAMSS_CSI1_AHB_CLK 78 +-#define GCC_CAMSS_CSI1_CLK 79 +-#define GCC_CAMSS_CSI1PHY_CLK 80 +-#define GCC_CAMSS_CSI1PIX_CLK 81 +-#define GCC_CAMSS_CSI1RDI_CLK 82 +-#define GCC_CAMSS_CSI_VFE0_CLK 83 +-#define GCC_CAMSS_GP0_CLK 84 +-#define GCC_CAMSS_GP1_CLK 85 +-#define GCC_CAMSS_ISPIF_AHB_CLK 86 +-#define GCC_CAMSS_JPEG0_CLK 87 +-#define GCC_CAMSS_JPEG_AHB_CLK 88 +-#define GCC_CAMSS_JPEG_AXI_CLK 89 +-#define GCC_CAMSS_MCLK0_CLK 90 +-#define GCC_CAMSS_MCLK1_CLK 91 +-#define GCC_CAMSS_MICRO_AHB_CLK 92 +-#define GCC_CAMSS_CSI0PHYTIMER_CLK 93 +-#define GCC_CAMSS_CSI1PHYTIMER_CLK 94 +-#define GCC_CAMSS_AHB_CLK 95 +-#define GCC_CAMSS_TOP_AHB_CLK 96 +-#define GCC_CAMSS_CPP_AHB_CLK 97 +-#define GCC_CAMSS_CPP_CLK 98 +-#define GCC_CAMSS_VFE0_CLK 99 +-#define GCC_CAMSS_VFE_AHB_CLK 100 +-#define GCC_CAMSS_VFE_AXI_CLK 101 +-#define GCC_CRYPTO_AHB_CLK 102 +-#define GCC_CRYPTO_AXI_CLK 103 +-#define GCC_CRYPTO_CLK 104 +-#define GCC_OXILI_GMEM_CLK 105 +-#define GCC_GP1_CLK 106 +-#define GCC_GP2_CLK 107 +-#define GCC_GP3_CLK 108 +-#define GCC_MDSS_AHB_CLK 109 +-#define GCC_MDSS_AXI_CLK 110 +-#define GCC_MDSS_BYTE0_CLK 111 +-#define GCC_MDSS_ESC0_CLK 112 +-#define GCC_MDSS_MDP_CLK 113 +-#define GCC_MDSS_PCLK0_CLK 114 +-#define GCC_MDSS_VSYNC_CLK 115 +-#define GCC_MSS_CFG_AHB_CLK 116 +-#define GCC_OXILI_AHB_CLK 117 +-#define GCC_OXILI_GFX3D_CLK 118 +-#define GCC_PDM2_CLK 119 +-#define GCC_PDM_AHB_CLK 120 +-#define GCC_PRNG_AHB_CLK 121 +-#define GCC_SDCC1_AHB_CLK 122 +-#define GCC_SDCC1_APPS_CLK 123 +-#define GCC_SDCC2_AHB_CLK 124 +-#define GCC_SDCC2_APPS_CLK 125 +-#define GCC_GTCU_AHB_CLK 126 +-#define GCC_JPEG_TBU_CLK 127 +-#define GCC_MDP_TBU_CLK 128 +-#define GCC_SMMU_CFG_CLK 129 +-#define GCC_VENUS_TBU_CLK 130 +-#define GCC_VFE_TBU_CLK 131 +-#define GCC_USB2A_PHY_SLEEP_CLK 132 +-#define GCC_USB_HS_AHB_CLK 133 +-#define GCC_USB_HS_SYSTEM_CLK 134 +-#define GCC_VENUS0_AHB_CLK 135 +-#define GCC_VENUS0_AXI_CLK 136 +-#define GCC_VENUS0_VCODEC0_CLK 137 +-#define BIMC_DDR_CLK_SRC 138 +-#define GCC_APSS_TCU_CLK 139 +-#define GCC_GFX_TCU_CLK 140 +-#define BIMC_GPU_CLK_SRC 141 +-#define GCC_BIMC_GFX_CLK 142 +-#define GCC_BIMC_GPU_CLK 143 +-#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 144 +-#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 145 +-#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 146 +-#define ULTAUDIO_XO_CLK_SRC 147 +-#define ULTAUDIO_AHBFABRIC_CLK_SRC 148 +-#define CODEC_DIGCODEC_CLK_SRC 149 +-#define GCC_ULTAUDIO_PCNOC_MPORT_CLK 150 +-#define GCC_ULTAUDIO_PCNOC_SWAY_CLK 151 +-#define GCC_ULTAUDIO_AVSYNC_XO_CLK 152 +-#define GCC_ULTAUDIO_STC_XO_CLK 153 +-#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 154 +-#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 155 +-#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 156 +-#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 157 +-#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 158 +-#define GCC_CODEC_DIGCODEC_CLK 159 +-#define GCC_MSS_Q6_BIMC_AXI_CLK 160 +- +-/* Indexes for GDSCs */ +-#define BIMC_GDSC 0 +-#define VENUS_GDSC 1 +-#define MDSS_GDSC 2 +-#define JPEG_GDSC 3 +-#define VFE_GDSC 4 +-#define OXILI_GDSC 5 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8939.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8939.h +deleted file mode 100644 +index 0634467c4ce5..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8939.h ++++ /dev/null +@@ -1,206 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2020 Linaro Limited +- */ +- +-#ifndef _DT_BINDINGS_CLK_MSM_GCC_8939_H +-#define _DT_BINDINGS_CLK_MSM_GCC_8939_H +- +-#define GPLL0 0 +-#define GPLL0_VOTE 1 +-#define BIMC_PLL 2 +-#define BIMC_PLL_VOTE 3 +-#define GPLL1 4 +-#define GPLL1_VOTE 5 +-#define GPLL2 6 +-#define GPLL2_VOTE 7 +-#define PCNOC_BFDCD_CLK_SRC 8 +-#define SYSTEM_NOC_BFDCD_CLK_SRC 9 +-#define CAMSS_AHB_CLK_SRC 10 +-#define APSS_AHB_CLK_SRC 11 +-#define CSI0_CLK_SRC 12 +-#define CSI1_CLK_SRC 13 +-#define GFX3D_CLK_SRC 14 +-#define VFE0_CLK_SRC 15 +-#define BLSP1_QUP1_I2C_APPS_CLK_SRC 16 +-#define BLSP1_QUP1_SPI_APPS_CLK_SRC 17 +-#define BLSP1_QUP2_I2C_APPS_CLK_SRC 18 +-#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19 +-#define BLSP1_QUP3_I2C_APPS_CLK_SRC 20 +-#define BLSP1_QUP3_SPI_APPS_CLK_SRC 21 +-#define BLSP1_QUP4_I2C_APPS_CLK_SRC 22 +-#define BLSP1_QUP4_SPI_APPS_CLK_SRC 23 +-#define BLSP1_QUP5_I2C_APPS_CLK_SRC 24 +-#define BLSP1_QUP5_SPI_APPS_CLK_SRC 25 +-#define BLSP1_QUP6_I2C_APPS_CLK_SRC 26 +-#define BLSP1_QUP6_SPI_APPS_CLK_SRC 27 +-#define BLSP1_UART1_APPS_CLK_SRC 28 +-#define BLSP1_UART2_APPS_CLK_SRC 29 +-#define CCI_CLK_SRC 30 +-#define CAMSS_GP0_CLK_SRC 31 +-#define CAMSS_GP1_CLK_SRC 32 +-#define JPEG0_CLK_SRC 33 +-#define MCLK0_CLK_SRC 34 +-#define MCLK1_CLK_SRC 35 +-#define CSI0PHYTIMER_CLK_SRC 36 +-#define CSI1PHYTIMER_CLK_SRC 37 +-#define CPP_CLK_SRC 38 +-#define CRYPTO_CLK_SRC 39 +-#define GP1_CLK_SRC 40 +-#define GP2_CLK_SRC 41 +-#define GP3_CLK_SRC 42 +-#define BYTE0_CLK_SRC 43 +-#define ESC0_CLK_SRC 44 +-#define MDP_CLK_SRC 45 +-#define PCLK0_CLK_SRC 46 +-#define VSYNC_CLK_SRC 47 +-#define PDM2_CLK_SRC 48 +-#define SDCC1_APPS_CLK_SRC 49 +-#define SDCC2_APPS_CLK_SRC 50 +-#define APSS_TCU_CLK_SRC 51 +-#define USB_HS_SYSTEM_CLK_SRC 52 +-#define VCODEC0_CLK_SRC 53 +-#define GCC_BLSP1_AHB_CLK 54 +-#define GCC_BLSP1_SLEEP_CLK 55 +-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 56 +-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 57 +-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 58 +-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 59 +-#define GCC_BLSP1_QUP3_I2C_APPS_CLK 60 +-#define GCC_BLSP1_QUP3_SPI_APPS_CLK 61 +-#define GCC_BLSP1_QUP4_I2C_APPS_CLK 62 +-#define GCC_BLSP1_QUP4_SPI_APPS_CLK 63 +-#define GCC_BLSP1_QUP5_I2C_APPS_CLK 64 +-#define GCC_BLSP1_QUP5_SPI_APPS_CLK 65 +-#define GCC_BLSP1_QUP6_I2C_APPS_CLK 66 +-#define GCC_BLSP1_QUP6_SPI_APPS_CLK 67 +-#define GCC_BLSP1_UART1_APPS_CLK 68 +-#define GCC_BLSP1_UART2_APPS_CLK 69 +-#define GCC_BOOT_ROM_AHB_CLK 70 +-#define GCC_CAMSS_CCI_AHB_CLK 71 +-#define GCC_CAMSS_CCI_CLK 72 +-#define GCC_CAMSS_CSI0_AHB_CLK 73 +-#define GCC_CAMSS_CSI0_CLK 74 +-#define GCC_CAMSS_CSI0PHY_CLK 75 +-#define GCC_CAMSS_CSI0PIX_CLK 76 +-#define GCC_CAMSS_CSI0RDI_CLK 77 +-#define GCC_CAMSS_CSI1_AHB_CLK 78 +-#define GCC_CAMSS_CSI1_CLK 79 +-#define GCC_CAMSS_CSI1PHY_CLK 80 +-#define GCC_CAMSS_CSI1PIX_CLK 81 +-#define GCC_CAMSS_CSI1RDI_CLK 82 +-#define GCC_CAMSS_CSI_VFE0_CLK 83 +-#define GCC_CAMSS_GP0_CLK 84 +-#define GCC_CAMSS_GP1_CLK 85 +-#define GCC_CAMSS_ISPIF_AHB_CLK 86 +-#define GCC_CAMSS_JPEG0_CLK 87 +-#define GCC_CAMSS_JPEG_AHB_CLK 88 +-#define GCC_CAMSS_JPEG_AXI_CLK 89 +-#define GCC_CAMSS_MCLK0_CLK 90 +-#define GCC_CAMSS_MCLK1_CLK 91 +-#define GCC_CAMSS_MICRO_AHB_CLK 92 +-#define GCC_CAMSS_CSI0PHYTIMER_CLK 93 +-#define GCC_CAMSS_CSI1PHYTIMER_CLK 94 +-#define GCC_CAMSS_AHB_CLK 95 +-#define GCC_CAMSS_TOP_AHB_CLK 96 +-#define GCC_CAMSS_CPP_AHB_CLK 97 +-#define GCC_CAMSS_CPP_CLK 98 +-#define GCC_CAMSS_VFE0_CLK 99 +-#define GCC_CAMSS_VFE_AHB_CLK 100 +-#define GCC_CAMSS_VFE_AXI_CLK 101 +-#define GCC_CRYPTO_AHB_CLK 102 +-#define GCC_CRYPTO_AXI_CLK 103 +-#define GCC_CRYPTO_CLK 104 +-#define GCC_OXILI_GMEM_CLK 105 +-#define GCC_GP1_CLK 106 +-#define GCC_GP2_CLK 107 +-#define GCC_GP3_CLK 108 +-#define GCC_MDSS_AHB_CLK 109 +-#define GCC_MDSS_AXI_CLK 110 +-#define GCC_MDSS_BYTE0_CLK 111 +-#define GCC_MDSS_ESC0_CLK 112 +-#define GCC_MDSS_MDP_CLK 113 +-#define GCC_MDSS_PCLK0_CLK 114 +-#define GCC_MDSS_VSYNC_CLK 115 +-#define GCC_MSS_CFG_AHB_CLK 116 +-#define GCC_OXILI_AHB_CLK 117 +-#define GCC_OXILI_GFX3D_CLK 118 +-#define GCC_PDM2_CLK 119 +-#define GCC_PDM_AHB_CLK 120 +-#define GCC_PRNG_AHB_CLK 121 +-#define GCC_SDCC1_AHB_CLK 122 +-#define GCC_SDCC1_APPS_CLK 123 +-#define GCC_SDCC2_AHB_CLK 124 +-#define GCC_SDCC2_APPS_CLK 125 +-#define GCC_GTCU_AHB_CLK 126 +-#define GCC_JPEG_TBU_CLK 127 +-#define GCC_MDP_TBU_CLK 128 +-#define GCC_SMMU_CFG_CLK 129 +-#define GCC_VENUS_TBU_CLK 130 +-#define GCC_VFE_TBU_CLK 131 +-#define GCC_USB2A_PHY_SLEEP_CLK 132 +-#define GCC_USB_HS_AHB_CLK 133 +-#define GCC_USB_HS_SYSTEM_CLK 134 +-#define GCC_VENUS0_AHB_CLK 135 +-#define GCC_VENUS0_AXI_CLK 136 +-#define GCC_VENUS0_VCODEC0_CLK 137 +-#define BIMC_DDR_CLK_SRC 138 +-#define GCC_APSS_TCU_CLK 139 +-#define GCC_GFX_TCU_CLK 140 +-#define BIMC_GPU_CLK_SRC 141 +-#define GCC_BIMC_GFX_CLK 142 +-#define GCC_BIMC_GPU_CLK 143 +-#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 144 +-#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 145 +-#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 146 +-#define ULTAUDIO_XO_CLK_SRC 147 +-#define ULTAUDIO_AHBFABRIC_CLK_SRC 148 +-#define CODEC_DIGCODEC_CLK_SRC 149 +-#define GCC_ULTAUDIO_PCNOC_MPORT_CLK 150 +-#define GCC_ULTAUDIO_PCNOC_SWAY_CLK 151 +-#define GCC_ULTAUDIO_AVSYNC_XO_CLK 152 +-#define GCC_ULTAUDIO_STC_XO_CLK 153 +-#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 154 +-#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 155 +-#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 156 +-#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 157 +-#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 158 +-#define GCC_CODEC_DIGCODEC_CLK 159 +-#define GCC_MSS_Q6_BIMC_AXI_CLK 160 +-#define GPLL3 161 +-#define GPLL3_VOTE 162 +-#define GPLL4 163 +-#define GPLL4_VOTE 164 +-#define GPLL5 165 +-#define GPLL5_VOTE 166 +-#define GPLL6 167 +-#define GPLL6_VOTE 168 +-#define BYTE1_CLK_SRC 169 +-#define GCC_MDSS_BYTE1_CLK 170 +-#define ESC1_CLK_SRC 171 +-#define GCC_MDSS_ESC1_CLK 172 +-#define PCLK1_CLK_SRC 173 +-#define GCC_MDSS_PCLK1_CLK 174 +-#define GCC_GFX_TBU_CLK 175 +-#define GCC_CPP_TBU_CLK 176 +-#define GCC_MDP_RT_TBU_CLK 177 +-#define USB_FS_SYSTEM_CLK_SRC 178 +-#define USB_FS_IC_CLK_SRC 179 +-#define GCC_USB_FS_AHB_CLK 180 +-#define GCC_USB_FS_IC_CLK 181 +-#define GCC_USB_FS_SYSTEM_CLK 182 +-#define GCC_VENUS0_CORE0_VCODEC0_CLK 183 +-#define GCC_VENUS0_CORE1_VCODEC0_CLK 184 +-#define GCC_OXILI_TIMER_CLK 185 +- +-/* Indexes for GDSCs */ +-#define BIMC_GDSC 0 +-#define VENUS_GDSC 1 +-#define MDSS_GDSC 2 +-#define JPEG_GDSC 3 +-#define VFE_GDSC 4 +-#define OXILI_GDSC 5 +-#define VENUS_CORE0_GDSC 6 +-#define VENUS_CORE1_GDSC 7 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8953.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8953.h +deleted file mode 100644 +index 783162da6148..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8953.h ++++ /dev/null +@@ -1,234 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +- +-#ifndef _DT_BINDINGS_CLK_MSM_GCC_8953_H +-#define _DT_BINDINGS_CLK_MSM_GCC_8953_H +- +-/* Clocks */ +-#define APC0_DROOP_DETECTOR_CLK_SRC 0 +-#define APC1_DROOP_DETECTOR_CLK_SRC 1 +-#define APSS_AHB_CLK_SRC 2 +-#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3 +-#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4 +-#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5 +-#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6 +-#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7 +-#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8 +-#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9 +-#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10 +-#define BLSP1_UART1_APPS_CLK_SRC 11 +-#define BLSP1_UART2_APPS_CLK_SRC 12 +-#define BLSP2_QUP1_I2C_APPS_CLK_SRC 13 +-#define BLSP2_QUP1_SPI_APPS_CLK_SRC 14 +-#define BLSP2_QUP2_I2C_APPS_CLK_SRC 15 +-#define BLSP2_QUP2_SPI_APPS_CLK_SRC 16 +-#define BLSP2_QUP3_I2C_APPS_CLK_SRC 17 +-#define BLSP2_QUP3_SPI_APPS_CLK_SRC 18 +-#define BLSP2_QUP4_I2C_APPS_CLK_SRC 19 +-#define BLSP2_QUP4_SPI_APPS_CLK_SRC 20 +-#define BLSP2_UART1_APPS_CLK_SRC 21 +-#define BLSP2_UART2_APPS_CLK_SRC 22 +-#define BYTE0_CLK_SRC 23 +-#define BYTE1_CLK_SRC 24 +-#define CAMSS_GP0_CLK_SRC 25 +-#define CAMSS_GP1_CLK_SRC 26 +-#define CAMSS_TOP_AHB_CLK_SRC 27 +-#define CCI_CLK_SRC 28 +-#define CPP_CLK_SRC 29 +-#define CRYPTO_CLK_SRC 30 +-#define CSI0PHYTIMER_CLK_SRC 31 +-#define CSI0P_CLK_SRC 32 +-#define CSI0_CLK_SRC 33 +-#define CSI1PHYTIMER_CLK_SRC 34 +-#define CSI1P_CLK_SRC 35 +-#define CSI1_CLK_SRC 36 +-#define CSI2PHYTIMER_CLK_SRC 37 +-#define CSI2P_CLK_SRC 38 +-#define CSI2_CLK_SRC 39 +-#define ESC0_CLK_SRC 40 +-#define ESC1_CLK_SRC 41 +-#define GCC_APC0_DROOP_DETECTOR_GPLL0_CLK 42 +-#define GCC_APC1_DROOP_DETECTOR_GPLL0_CLK 43 +-#define GCC_APSS_AHB_CLK 44 +-#define GCC_APSS_AXI_CLK 45 +-#define GCC_APSS_TCU_ASYNC_CLK 46 +-#define GCC_BIMC_GFX_CLK 47 +-#define GCC_BIMC_GPU_CLK 48 +-#define GCC_BLSP1_AHB_CLK 49 +-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 50 +-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 51 +-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 52 +-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 53 +-#define GCC_BLSP1_QUP3_I2C_APPS_CLK 54 +-#define GCC_BLSP1_QUP3_SPI_APPS_CLK 55 +-#define GCC_BLSP1_QUP4_I2C_APPS_CLK 56 +-#define GCC_BLSP1_QUP4_SPI_APPS_CLK 57 +-#define GCC_BLSP1_UART1_APPS_CLK 58 +-#define GCC_BLSP1_UART2_APPS_CLK 59 +-#define GCC_BLSP2_AHB_CLK 60 +-#define GCC_BLSP2_QUP1_I2C_APPS_CLK 61 +-#define GCC_BLSP2_QUP1_SPI_APPS_CLK 62 +-#define GCC_BLSP2_QUP2_I2C_APPS_CLK 63 +-#define GCC_BLSP2_QUP2_SPI_APPS_CLK 64 +-#define GCC_BLSP2_QUP3_I2C_APPS_CLK 65 +-#define GCC_BLSP2_QUP3_SPI_APPS_CLK 66 +-#define GCC_BLSP2_QUP4_I2C_APPS_CLK 67 +-#define GCC_BLSP2_QUP4_SPI_APPS_CLK 68 +-#define GCC_BLSP2_UART1_APPS_CLK 69 +-#define GCC_BLSP2_UART2_APPS_CLK 70 +-#define GCC_BOOT_ROM_AHB_CLK 71 +-#define GCC_CAMSS_AHB_CLK 72 +-#define GCC_CAMSS_CCI_AHB_CLK 73 +-#define GCC_CAMSS_CCI_CLK 74 +-#define GCC_CAMSS_CPP_AHB_CLK 75 +-#define GCC_CAMSS_CPP_AXI_CLK 76 +-#define GCC_CAMSS_CPP_CLK 77 +-#define GCC_CAMSS_CSI0PHYTIMER_CLK 78 +-#define GCC_CAMSS_CSI0PHY_CLK 79 +-#define GCC_CAMSS_CSI0PIX_CLK 80 +-#define GCC_CAMSS_CSI0RDI_CLK 81 +-#define GCC_CAMSS_CSI0_AHB_CLK 82 +-#define GCC_CAMSS_CSI0_CLK 83 +-#define GCC_CAMSS_CSI0_CSIPHY_3P_CLK 84 +-#define GCC_CAMSS_CSI1PHYTIMER_CLK 85 +-#define GCC_CAMSS_CSI1PHY_CLK 86 +-#define GCC_CAMSS_CSI1PIX_CLK 87 +-#define GCC_CAMSS_CSI1RDI_CLK 88 +-#define GCC_CAMSS_CSI1_AHB_CLK 89 +-#define GCC_CAMSS_CSI1_CLK 90 +-#define GCC_CAMSS_CSI1_CSIPHY_3P_CLK 91 +-#define GCC_CAMSS_CSI2PHYTIMER_CLK 92 +-#define GCC_CAMSS_CSI2PHY_CLK 93 +-#define GCC_CAMSS_CSI2PIX_CLK 94 +-#define GCC_CAMSS_CSI2RDI_CLK 95 +-#define GCC_CAMSS_CSI2_AHB_CLK 96 +-#define GCC_CAMSS_CSI2_CLK 97 +-#define GCC_CAMSS_CSI2_CSIPHY_3P_CLK 98 +-#define GCC_CAMSS_CSI_VFE0_CLK 99 +-#define GCC_CAMSS_CSI_VFE1_CLK 100 +-#define GCC_CAMSS_GP0_CLK 101 +-#define GCC_CAMSS_GP1_CLK 102 +-#define GCC_CAMSS_ISPIF_AHB_CLK 103 +-#define GCC_CAMSS_JPEG0_CLK 104 +-#define GCC_CAMSS_JPEG_AHB_CLK 105 +-#define GCC_CAMSS_JPEG_AXI_CLK 106 +-#define GCC_CAMSS_MCLK0_CLK 107 +-#define GCC_CAMSS_MCLK1_CLK 108 +-#define GCC_CAMSS_MCLK2_CLK 109 +-#define GCC_CAMSS_MCLK3_CLK 110 +-#define GCC_CAMSS_MICRO_AHB_CLK 111 +-#define GCC_CAMSS_TOP_AHB_CLK 112 +-#define GCC_CAMSS_VFE0_AHB_CLK 113 +-#define GCC_CAMSS_VFE0_AXI_CLK 114 +-#define GCC_CAMSS_VFE0_CLK 115 +-#define GCC_CAMSS_VFE1_AHB_CLK 116 +-#define GCC_CAMSS_VFE1_AXI_CLK 117 +-#define GCC_CAMSS_VFE1_CLK 118 +-#define GCC_CPP_TBU_CLK 119 +-#define GCC_CRYPTO_AHB_CLK 120 +-#define GCC_CRYPTO_AXI_CLK 121 +-#define GCC_CRYPTO_CLK 122 +-#define GCC_DCC_CLK 123 +-#define GCC_GP1_CLK 124 +-#define GCC_GP2_CLK 125 +-#define GCC_GP3_CLK 126 +-#define GCC_JPEG_TBU_CLK 127 +-#define GCC_MDP_TBU_CLK 128 +-#define GCC_MDSS_AHB_CLK 129 +-#define GCC_MDSS_AXI_CLK 130 +-#define GCC_MDSS_BYTE0_CLK 131 +-#define GCC_MDSS_BYTE1_CLK 132 +-#define GCC_MDSS_ESC0_CLK 133 +-#define GCC_MDSS_ESC1_CLK 134 +-#define GCC_MDSS_MDP_CLK 135 +-#define GCC_MDSS_PCLK0_CLK 136 +-#define GCC_MDSS_PCLK1_CLK 137 +-#define GCC_MDSS_VSYNC_CLK 138 +-#define GCC_MSS_CFG_AHB_CLK 139 +-#define GCC_MSS_Q6_BIMC_AXI_CLK 140 +-#define GCC_OXILI_AHB_CLK 141 +-#define GCC_OXILI_AON_CLK 142 +-#define GCC_OXILI_GFX3D_CLK 143 +-#define GCC_OXILI_TIMER_CLK 144 +-#define GCC_PCNOC_USB3_AXI_CLK 145 +-#define GCC_PDM2_CLK 146 +-#define GCC_PDM_AHB_CLK 147 +-#define GCC_PRNG_AHB_CLK 148 +-#define GCC_QDSS_DAP_CLK 149 +-#define GCC_QUSB_REF_CLK 150 +-#define GCC_RBCPR_GFX_CLK 151 +-#define GCC_SDCC1_AHB_CLK 152 +-#define GCC_SDCC1_APPS_CLK 153 +-#define GCC_SDCC1_ICE_CORE_CLK 154 +-#define GCC_SDCC2_AHB_CLK 155 +-#define GCC_SDCC2_APPS_CLK 156 +-#define GCC_SMMU_CFG_CLK 157 +-#define GCC_USB30_MASTER_CLK 158 +-#define GCC_USB30_MOCK_UTMI_CLK 159 +-#define GCC_USB30_SLEEP_CLK 160 +-#define GCC_USB3_AUX_CLK 161 +-#define GCC_USB3_PIPE_CLK 162 +-#define GCC_USB_PHY_CFG_AHB_CLK 163 +-#define GCC_USB_SS_REF_CLK 164 +-#define GCC_VENUS0_AHB_CLK 165 +-#define GCC_VENUS0_AXI_CLK 166 +-#define GCC_VENUS0_CORE0_VCODEC0_CLK 167 +-#define GCC_VENUS0_VCODEC0_CLK 168 +-#define GCC_VENUS_TBU_CLK 169 +-#define GCC_VFE1_TBU_CLK 170 +-#define GCC_VFE_TBU_CLK 171 +-#define GFX3D_CLK_SRC 172 +-#define GP1_CLK_SRC 173 +-#define GP2_CLK_SRC 174 +-#define GP3_CLK_SRC 175 +-#define GPLL0 176 +-#define GPLL0_EARLY 177 +-#define GPLL2 178 +-#define GPLL2_EARLY 179 +-#define GPLL3 180 +-#define GPLL3_EARLY 181 +-#define GPLL4 182 +-#define GPLL4_EARLY 183 +-#define GPLL6 184 +-#define GPLL6_EARLY 185 +-#define JPEG0_CLK_SRC 186 +-#define MCLK0_CLK_SRC 187 +-#define MCLK1_CLK_SRC 188 +-#define MCLK2_CLK_SRC 189 +-#define MCLK3_CLK_SRC 190 +-#define MDP_CLK_SRC 191 +-#define PCLK0_CLK_SRC 192 +-#define PCLK1_CLK_SRC 193 +-#define PDM2_CLK_SRC 194 +-#define RBCPR_GFX_CLK_SRC 195 +-#define SDCC1_APPS_CLK_SRC 196 +-#define SDCC1_ICE_CORE_CLK_SRC 197 +-#define SDCC2_APPS_CLK_SRC 198 +-#define USB30_MASTER_CLK_SRC 199 +-#define USB30_MOCK_UTMI_CLK_SRC 200 +-#define USB3_AUX_CLK_SRC 201 +-#define VCODEC0_CLK_SRC 202 +-#define VFE0_CLK_SRC 203 +-#define VFE1_CLK_SRC 204 +-#define VSYNC_CLK_SRC 205 +- +-/* GCC block resets */ +-#define GCC_CAMSS_MICRO_BCR 0 +-#define GCC_MSS_BCR 1 +-#define GCC_QUSB2_PHY_BCR 2 +-#define GCC_USB3PHY_PHY_BCR 3 +-#define GCC_USB3_PHY_BCR 4 +-#define GCC_USB_30_BCR 5 +- +-/* GDSCs */ +-#define CPP_GDSC 0 +-#define JPEG_GDSC 1 +-#define MDSS_GDSC 2 +-#define OXILI_CX_GDSC 3 +-#define OXILI_GX_GDSC 4 +-#define USB30_GDSC 5 +-#define VENUS_CORE0_GDSC 6 +-#define VENUS_GDSC 7 +-#define VFE0_GDSC 8 +-#define VFE1_GDSC 9 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8960.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8960.h +deleted file mode 100644 +index 950b8286262f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8960.h ++++ /dev/null +@@ -1,317 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2013, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_MSM_GCC_8960_H +-#define _DT_BINDINGS_CLK_MSM_GCC_8960_H +- +-#define AFAB_CLK_SRC 0 +-#define AFAB_CORE_CLK 1 +-#define SFAB_MSS_Q6_SW_A_CLK 2 +-#define SFAB_MSS_Q6_FW_A_CLK 3 +-#define QDSS_STM_CLK 4 +-#define SCSS_A_CLK 5 +-#define SCSS_H_CLK 6 +-#define SCSS_XO_SRC_CLK 7 +-#define AFAB_EBI1_CH0_A_CLK 8 +-#define AFAB_EBI1_CH1_A_CLK 9 +-#define AFAB_AXI_S0_FCLK 10 +-#define AFAB_AXI_S1_FCLK 11 +-#define AFAB_AXI_S2_FCLK 12 +-#define AFAB_AXI_S3_FCLK 13 +-#define AFAB_AXI_S4_FCLK 14 +-#define SFAB_CORE_CLK 15 +-#define SFAB_AXI_S0_FCLK 16 +-#define SFAB_AXI_S1_FCLK 17 +-#define SFAB_AXI_S2_FCLK 18 +-#define SFAB_AXI_S3_FCLK 19 +-#define SFAB_AXI_S4_FCLK 20 +-#define SFAB_AHB_S0_FCLK 21 +-#define SFAB_AHB_S1_FCLK 22 +-#define SFAB_AHB_S2_FCLK 23 +-#define SFAB_AHB_S3_FCLK 24 +-#define SFAB_AHB_S4_FCLK 25 +-#define SFAB_AHB_S5_FCLK 26 +-#define SFAB_AHB_S6_FCLK 27 +-#define SFAB_AHB_S7_FCLK 28 +-#define QDSS_AT_CLK_SRC 29 +-#define QDSS_AT_CLK 30 +-#define QDSS_TRACECLKIN_CLK_SRC 31 +-#define QDSS_TRACECLKIN_CLK 32 +-#define QDSS_TSCTR_CLK_SRC 33 +-#define QDSS_TSCTR_CLK 34 +-#define SFAB_ADM0_M0_A_CLK 35 +-#define SFAB_ADM0_M1_A_CLK 36 +-#define SFAB_ADM0_M2_H_CLK 37 +-#define ADM0_CLK 38 +-#define ADM0_PBUS_CLK 39 +-#define MSS_XPU_CLK 40 +-#define IMEM0_A_CLK 41 +-#define QDSS_H_CLK 42 +-#define PCIE_A_CLK 43 +-#define PCIE_AUX_CLK 44 +-#define PCIE_PHY_REF_CLK 45 +-#define PCIE_H_CLK 46 +-#define SFAB_CLK_SRC 47 +-#define MAHB0_CLK 48 +-#define Q6SW_CLK_SRC 49 +-#define Q6SW_CLK 50 +-#define Q6FW_CLK_SRC 51 +-#define Q6FW_CLK 52 +-#define SFAB_MSS_M_A_CLK 53 +-#define SFAB_USB3_M_A_CLK 54 +-#define SFAB_LPASS_Q6_A_CLK 55 +-#define SFAB_AFAB_M_A_CLK 56 +-#define AFAB_SFAB_M0_A_CLK 57 +-#define AFAB_SFAB_M1_A_CLK 58 +-#define SFAB_SATA_S_H_CLK 59 +-#define DFAB_CLK_SRC 60 +-#define DFAB_CLK 61 +-#define SFAB_DFAB_M_A_CLK 62 +-#define DFAB_SFAB_M_A_CLK 63 +-#define DFAB_SWAY0_H_CLK 64 +-#define DFAB_SWAY1_H_CLK 65 +-#define DFAB_ARB0_H_CLK 66 +-#define DFAB_ARB1_H_CLK 67 +-#define PPSS_H_CLK 68 +-#define PPSS_PROC_CLK 69 +-#define PPSS_TIMER0_CLK 70 +-#define PPSS_TIMER1_CLK 71 +-#define PMEM_A_CLK 72 +-#define DMA_BAM_H_CLK 73 +-#define SIC_H_CLK 74 +-#define SPS_TIC_H_CLK 75 +-#define SLIMBUS_H_CLK 76 +-#define SLIMBUS_XO_SRC_CLK 77 +-#define CFPB_2X_CLK_SRC 78 +-#define CFPB_CLK 79 +-#define CFPB0_H_CLK 80 +-#define CFPB1_H_CLK 81 +-#define CFPB2_H_CLK 82 +-#define SFAB_CFPB_M_H_CLK 83 +-#define CFPB_MASTER_H_CLK 84 +-#define SFAB_CFPB_S_H_CLK 85 +-#define CFPB_SPLITTER_H_CLK 86 +-#define TSIF_H_CLK 87 +-#define TSIF_INACTIVITY_TIMERS_CLK 88 +-#define TSIF_REF_SRC 89 +-#define TSIF_REF_CLK 90 +-#define CE1_H_CLK 91 +-#define CE1_CORE_CLK 92 +-#define CE1_SLEEP_CLK 93 +-#define CE2_H_CLK 94 +-#define CE2_CORE_CLK 95 +-#define SFPB_H_CLK_SRC 97 +-#define SFPB_H_CLK 98 +-#define SFAB_SFPB_M_H_CLK 99 +-#define SFAB_SFPB_S_H_CLK 100 +-#define RPM_PROC_CLK 101 +-#define RPM_BUS_H_CLK 102 +-#define RPM_SLEEP_CLK 103 +-#define RPM_TIMER_CLK 104 +-#define RPM_MSG_RAM_H_CLK 105 +-#define PMIC_ARB0_H_CLK 106 +-#define PMIC_ARB1_H_CLK 107 +-#define PMIC_SSBI2_SRC 108 +-#define PMIC_SSBI2_CLK 109 +-#define SDC1_H_CLK 110 +-#define SDC2_H_CLK 111 +-#define SDC3_H_CLK 112 +-#define SDC4_H_CLK 113 +-#define SDC5_H_CLK 114 +-#define SDC1_SRC 115 +-#define SDC2_SRC 116 +-#define SDC3_SRC 117 +-#define SDC4_SRC 118 +-#define SDC5_SRC 119 +-#define SDC1_CLK 120 +-#define SDC2_CLK 121 +-#define SDC3_CLK 122 +-#define SDC4_CLK 123 +-#define SDC5_CLK 124 +-#define DFAB_A2_H_CLK 125 +-#define USB_HS1_H_CLK 126 +-#define USB_HS1_XCVR_SRC 127 +-#define USB_HS1_XCVR_CLK 128 +-#define USB_HSIC_H_CLK 129 +-#define USB_HSIC_XCVR_FS_SRC 130 +-#define USB_HSIC_XCVR_FS_CLK 131 +-#define USB_HSIC_SYSTEM_CLK_SRC 132 +-#define USB_HSIC_SYSTEM_CLK 133 +-#define CFPB0_C0_H_CLK 134 +-#define CFPB0_C1_H_CLK 135 +-#define CFPB0_D0_H_CLK 136 +-#define CFPB0_D1_H_CLK 137 +-#define USB_FS1_H_CLK 138 +-#define USB_FS1_XCVR_FS_SRC 139 +-#define USB_FS1_XCVR_FS_CLK 140 +-#define USB_FS1_SYSTEM_CLK 141 +-#define USB_FS2_H_CLK 142 +-#define USB_FS2_XCVR_FS_SRC 143 +-#define USB_FS2_XCVR_FS_CLK 144 +-#define USB_FS2_SYSTEM_CLK 145 +-#define GSBI_COMMON_SIM_SRC 146 +-#define GSBI1_H_CLK 147 +-#define GSBI2_H_CLK 148 +-#define GSBI3_H_CLK 149 +-#define GSBI4_H_CLK 150 +-#define GSBI5_H_CLK 151 +-#define GSBI6_H_CLK 152 +-#define GSBI7_H_CLK 153 +-#define GSBI8_H_CLK 154 +-#define GSBI9_H_CLK 155 +-#define GSBI10_H_CLK 156 +-#define GSBI11_H_CLK 157 +-#define GSBI12_H_CLK 158 +-#define GSBI1_UART_SRC 159 +-#define GSBI1_UART_CLK 160 +-#define GSBI2_UART_SRC 161 +-#define GSBI2_UART_CLK 162 +-#define GSBI3_UART_SRC 163 +-#define GSBI3_UART_CLK 164 +-#define GSBI4_UART_SRC 165 +-#define GSBI4_UART_CLK 166 +-#define GSBI5_UART_SRC 167 +-#define GSBI5_UART_CLK 168 +-#define GSBI6_UART_SRC 169 +-#define GSBI6_UART_CLK 170 +-#define GSBI7_UART_SRC 171 +-#define GSBI7_UART_CLK 172 +-#define GSBI8_UART_SRC 173 +-#define GSBI8_UART_CLK 174 +-#define GSBI9_UART_SRC 175 +-#define GSBI9_UART_CLK 176 +-#define GSBI10_UART_SRC 177 +-#define GSBI10_UART_CLK 178 +-#define GSBI11_UART_SRC 179 +-#define GSBI11_UART_CLK 180 +-#define GSBI12_UART_SRC 181 +-#define GSBI12_UART_CLK 182 +-#define GSBI1_QUP_SRC 183 +-#define GSBI1_QUP_CLK 184 +-#define GSBI2_QUP_SRC 185 +-#define GSBI2_QUP_CLK 186 +-#define GSBI3_QUP_SRC 187 +-#define GSBI3_QUP_CLK 188 +-#define GSBI4_QUP_SRC 189 +-#define GSBI4_QUP_CLK 190 +-#define GSBI5_QUP_SRC 191 +-#define GSBI5_QUP_CLK 192 +-#define GSBI6_QUP_SRC 193 +-#define GSBI6_QUP_CLK 194 +-#define GSBI7_QUP_SRC 195 +-#define GSBI7_QUP_CLK 196 +-#define GSBI8_QUP_SRC 197 +-#define GSBI8_QUP_CLK 198 +-#define GSBI9_QUP_SRC 199 +-#define GSBI9_QUP_CLK 200 +-#define GSBI10_QUP_SRC 201 +-#define GSBI10_QUP_CLK 202 +-#define GSBI11_QUP_SRC 203 +-#define GSBI11_QUP_CLK 204 +-#define GSBI12_QUP_SRC 205 +-#define GSBI12_QUP_CLK 206 +-#define GSBI1_SIM_CLK 207 +-#define GSBI2_SIM_CLK 208 +-#define GSBI3_SIM_CLK 209 +-#define GSBI4_SIM_CLK 210 +-#define GSBI5_SIM_CLK 211 +-#define GSBI6_SIM_CLK 212 +-#define GSBI7_SIM_CLK 213 +-#define GSBI8_SIM_CLK 214 +-#define GSBI9_SIM_CLK 215 +-#define GSBI10_SIM_CLK 216 +-#define GSBI11_SIM_CLK 217 +-#define GSBI12_SIM_CLK 218 +-#define USB_HSIC_HSIC_CLK_SRC 219 +-#define USB_HSIC_HSIC_CLK 220 +-#define USB_HSIC_HSIO_CAL_CLK 221 +-#define SPDM_CFG_H_CLK 222 +-#define SPDM_MSTR_H_CLK 223 +-#define SPDM_FF_CLK_SRC 224 +-#define SPDM_FF_CLK 225 +-#define SEC_CTRL_CLK 226 +-#define SEC_CTRL_ACC_CLK_SRC 227 +-#define SEC_CTRL_ACC_CLK 228 +-#define TLMM_H_CLK 229 +-#define TLMM_CLK 230 +-#define SFAB_MSS_S_H_CLK 231 +-#define MSS_SLP_CLK 232 +-#define MSS_Q6SW_JTAG_CLK 233 +-#define MSS_Q6FW_JTAG_CLK 234 +-#define MSS_S_H_CLK 235 +-#define MSS_CXO_SRC_CLK 236 +-#define SATA_H_CLK 237 +-#define SATA_CLK_SRC 238 +-#define SATA_RXOOB_CLK 239 +-#define SATA_PMALIVE_CLK 240 +-#define SATA_PHY_REF_CLK 241 +-#define TSSC_CLK_SRC 242 +-#define TSSC_CLK 243 +-#define PDM_SRC 244 +-#define PDM_CLK 245 +-#define GP0_SRC 246 +-#define GP0_CLK 247 +-#define GP1_SRC 248 +-#define GP1_CLK 249 +-#define GP2_SRC 250 +-#define GP2_CLK 251 +-#define MPM_CLK 252 +-#define EBI1_CLK_SRC 253 +-#define EBI1_CH0_CLK 254 +-#define EBI1_CH1_CLK 255 +-#define EBI1_2X_CLK 256 +-#define EBI1_CH0_DQ_CLK 257 +-#define EBI1_CH1_DQ_CLK 258 +-#define EBI1_CH0_CA_CLK 259 +-#define EBI1_CH1_CA_CLK 260 +-#define EBI1_XO_CLK 261 +-#define SFAB_SMPSS_S_H_CLK 262 +-#define PRNG_SRC 263 +-#define PRNG_CLK 264 +-#define PXO_SRC 265 +-#define LPASS_CXO_CLK 266 +-#define LPASS_PXO_CLK 267 +-#define SPDM_CY_PORT0_CLK 268 +-#define SPDM_CY_PORT1_CLK 269 +-#define SPDM_CY_PORT2_CLK 270 +-#define SPDM_CY_PORT3_CLK 271 +-#define SPDM_CY_PORT4_CLK 272 +-#define SPDM_CY_PORT5_CLK 273 +-#define SPDM_CY_PORT6_CLK 274 +-#define SPDM_CY_PORT7_CLK 275 +-#define PLL0 276 +-#define PLL0_VOTE 277 +-#define PLL3 278 +-#define PLL3_VOTE 279 +-#define PLL4_VOTE 280 +-#define PLL5 281 +-#define PLL5_VOTE 282 +-#define PLL6 283 +-#define PLL6_VOTE 284 +-#define PLL7_VOTE 285 +-#define PLL8 286 +-#define PLL8_VOTE 287 +-#define PLL9 288 +-#define PLL10 289 +-#define PLL11 290 +-#define PLL12 291 +-#define PLL13 292 +-#define PLL14 293 +-#define PLL14_VOTE 294 +-#define USB_HS3_H_CLK 295 +-#define USB_HS3_XCVR_SRC 296 +-#define USB_HS3_XCVR_CLK 297 +-#define USB_HS4_H_CLK 298 +-#define USB_HS4_XCVR_SRC 299 +-#define USB_HS4_XCVR_CLK 300 +-#define SATA_PHY_CFG_CLK 301 +-#define SATA_A_CLK 302 +-#define CE3_SRC 303 +-#define CE3_CORE_CLK 304 +-#define CE3_H_CLK 305 +-#define PLL16 306 +-#define PLL17 307 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8974.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8974.h +deleted file mode 100644 +index 5c10570988e0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8974.h ++++ /dev/null +@@ -1,319 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2013, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_MSM_GCC_8974_H +-#define _DT_BINDINGS_CLK_MSM_GCC_8974_H +- +-#define GPLL0 0 +-#define GPLL0_VOTE 1 +-#define CONFIG_NOC_CLK_SRC 2 +-#define GPLL2 3 +-#define GPLL2_VOTE 4 +-#define GPLL3 5 +-#define GPLL3_VOTE 6 +-#define PERIPH_NOC_CLK_SRC 7 +-#define BLSP_UART_SIM_CLK_SRC 8 +-#define QDSS_TSCTR_CLK_SRC 9 +-#define BIMC_DDR_CLK_SRC 10 +-#define SYSTEM_NOC_CLK_SRC 11 +-#define GPLL1 12 +-#define GPLL1_VOTE 13 +-#define RPM_CLK_SRC 14 +-#define GCC_BIMC_CLK 15 +-#define BIMC_DDR_CPLL0_ROOT_CLK_SRC 16 +-#define KPSS_AHB_CLK_SRC 17 +-#define QDSS_AT_CLK_SRC 18 +-#define USB30_MASTER_CLK_SRC 19 +-#define BIMC_DDR_CPLL1_ROOT_CLK_SRC 20 +-#define QDSS_STM_CLK_SRC 21 +-#define ACC_CLK_SRC 22 +-#define SEC_CTRL_CLK_SRC 23 +-#define BLSP1_QUP1_I2C_APPS_CLK_SRC 24 +-#define BLSP1_QUP1_SPI_APPS_CLK_SRC 25 +-#define BLSP1_QUP2_I2C_APPS_CLK_SRC 26 +-#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 +-#define BLSP1_QUP3_I2C_APPS_CLK_SRC 28 +-#define BLSP1_QUP3_SPI_APPS_CLK_SRC 29 +-#define BLSP1_QUP4_I2C_APPS_CLK_SRC 30 +-#define BLSP1_QUP4_SPI_APPS_CLK_SRC 31 +-#define BLSP1_QUP5_I2C_APPS_CLK_SRC 32 +-#define BLSP1_QUP5_SPI_APPS_CLK_SRC 33 +-#define BLSP1_QUP6_I2C_APPS_CLK_SRC 34 +-#define BLSP1_QUP6_SPI_APPS_CLK_SRC 35 +-#define BLSP1_UART1_APPS_CLK_SRC 36 +-#define BLSP1_UART2_APPS_CLK_SRC 37 +-#define BLSP1_UART3_APPS_CLK_SRC 38 +-#define BLSP1_UART4_APPS_CLK_SRC 39 +-#define BLSP1_UART5_APPS_CLK_SRC 40 +-#define BLSP1_UART6_APPS_CLK_SRC 41 +-#define BLSP2_QUP1_I2C_APPS_CLK_SRC 42 +-#define BLSP2_QUP1_SPI_APPS_CLK_SRC 43 +-#define BLSP2_QUP2_I2C_APPS_CLK_SRC 44 +-#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 +-#define BLSP2_QUP3_I2C_APPS_CLK_SRC 46 +-#define BLSP2_QUP3_SPI_APPS_CLK_SRC 47 +-#define BLSP2_QUP4_I2C_APPS_CLK_SRC 48 +-#define BLSP2_QUP4_SPI_APPS_CLK_SRC 49 +-#define BLSP2_QUP5_I2C_APPS_CLK_SRC 50 +-#define BLSP2_QUP5_SPI_APPS_CLK_SRC 51 +-#define BLSP2_QUP6_I2C_APPS_CLK_SRC 52 +-#define BLSP2_QUP6_SPI_APPS_CLK_SRC 53 +-#define BLSP2_UART1_APPS_CLK_SRC 54 +-#define BLSP2_UART2_APPS_CLK_SRC 55 +-#define BLSP2_UART3_APPS_CLK_SRC 56 +-#define BLSP2_UART4_APPS_CLK_SRC 57 +-#define BLSP2_UART5_APPS_CLK_SRC 58 +-#define BLSP2_UART6_APPS_CLK_SRC 59 +-#define CE1_CLK_SRC 60 +-#define CE2_CLK_SRC 61 +-#define GP1_CLK_SRC 62 +-#define GP2_CLK_SRC 63 +-#define GP3_CLK_SRC 64 +-#define PDM2_CLK_SRC 65 +-#define QDSS_TRACECLKIN_CLK_SRC 66 +-#define RBCPR_CLK_SRC 67 +-#define SDCC1_APPS_CLK_SRC 68 +-#define SDCC2_APPS_CLK_SRC 69 +-#define SDCC3_APPS_CLK_SRC 70 +-#define SDCC4_APPS_CLK_SRC 71 +-#define SPMI_AHB_CLK_SRC 72 +-#define SPMI_SER_CLK_SRC 73 +-#define TSIF_REF_CLK_SRC 74 +-#define USB30_MOCK_UTMI_CLK_SRC 75 +-#define USB_HS_SYSTEM_CLK_SRC 76 +-#define USB_HSIC_CLK_SRC 77 +-#define USB_HSIC_IO_CAL_CLK_SRC 78 +-#define USB_HSIC_SYSTEM_CLK_SRC 79 +-#define GCC_BAM_DMA_AHB_CLK 80 +-#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 81 +-#define GCC_BIMC_CFG_AHB_CLK 82 +-#define GCC_BIMC_KPSS_AXI_CLK 83 +-#define GCC_BIMC_SLEEP_CLK 84 +-#define GCC_BIMC_SYSNOC_AXI_CLK 85 +-#define GCC_BIMC_XO_CLK 86 +-#define GCC_BLSP1_AHB_CLK 87 +-#define GCC_BLSP1_SLEEP_CLK 88 +-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 89 +-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 90 +-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 91 +-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 92 +-#define GCC_BLSP1_QUP3_I2C_APPS_CLK 93 +-#define GCC_BLSP1_QUP3_SPI_APPS_CLK 94 +-#define GCC_BLSP1_QUP4_I2C_APPS_CLK 95 +-#define GCC_BLSP1_QUP4_SPI_APPS_CLK 96 +-#define GCC_BLSP1_QUP5_I2C_APPS_CLK 97 +-#define GCC_BLSP1_QUP5_SPI_APPS_CLK 98 +-#define GCC_BLSP1_QUP6_I2C_APPS_CLK 99 +-#define GCC_BLSP1_QUP6_SPI_APPS_CLK 100 +-#define GCC_BLSP1_UART1_APPS_CLK 101 +-#define GCC_BLSP1_UART1_SIM_CLK 102 +-#define GCC_BLSP1_UART2_APPS_CLK 103 +-#define GCC_BLSP1_UART2_SIM_CLK 104 +-#define GCC_BLSP1_UART3_APPS_CLK 105 +-#define GCC_BLSP1_UART3_SIM_CLK 106 +-#define GCC_BLSP1_UART4_APPS_CLK 107 +-#define GCC_BLSP1_UART4_SIM_CLK 108 +-#define GCC_BLSP1_UART5_APPS_CLK 109 +-#define GCC_BLSP1_UART5_SIM_CLK 110 +-#define GCC_BLSP1_UART6_APPS_CLK 111 +-#define GCC_BLSP1_UART6_SIM_CLK 112 +-#define GCC_BLSP2_AHB_CLK 113 +-#define GCC_BLSP2_SLEEP_CLK 114 +-#define GCC_BLSP2_QUP1_I2C_APPS_CLK 115 +-#define GCC_BLSP2_QUP1_SPI_APPS_CLK 116 +-#define GCC_BLSP2_QUP2_I2C_APPS_CLK 117 +-#define GCC_BLSP2_QUP2_SPI_APPS_CLK 118 +-#define GCC_BLSP2_QUP3_I2C_APPS_CLK 119 +-#define GCC_BLSP2_QUP3_SPI_APPS_CLK 120 +-#define GCC_BLSP2_QUP4_I2C_APPS_CLK 121 +-#define GCC_BLSP2_QUP4_SPI_APPS_CLK 122 +-#define GCC_BLSP2_QUP5_I2C_APPS_CLK 123 +-#define GCC_BLSP2_QUP5_SPI_APPS_CLK 124 +-#define GCC_BLSP2_QUP6_I2C_APPS_CLK 125 +-#define GCC_BLSP2_QUP6_SPI_APPS_CLK 126 +-#define GCC_BLSP2_UART1_APPS_CLK 127 +-#define GCC_BLSP2_UART1_SIM_CLK 128 +-#define GCC_BLSP2_UART2_APPS_CLK 129 +-#define GCC_BLSP2_UART2_SIM_CLK 130 +-#define GCC_BLSP2_UART3_APPS_CLK 131 +-#define GCC_BLSP2_UART3_SIM_CLK 132 +-#define GCC_BLSP2_UART4_APPS_CLK 133 +-#define GCC_BLSP2_UART4_SIM_CLK 134 +-#define GCC_BLSP2_UART5_APPS_CLK 135 +-#define GCC_BLSP2_UART5_SIM_CLK 136 +-#define GCC_BLSP2_UART6_APPS_CLK 137 +-#define GCC_BLSP2_UART6_SIM_CLK 138 +-#define GCC_BOOT_ROM_AHB_CLK 139 +-#define GCC_CE1_AHB_CLK 140 +-#define GCC_CE1_AXI_CLK 141 +-#define GCC_CE1_CLK 142 +-#define GCC_CE2_AHB_CLK 143 +-#define GCC_CE2_AXI_CLK 144 +-#define GCC_CE2_CLK 145 +-#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 146 +-#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 147 +-#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 148 +-#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 149 +-#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 150 +-#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 151 +-#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 152 +-#define GCC_CFG_NOC_AHB_CLK 153 +-#define GCC_CFG_NOC_DDR_CFG_CLK 154 +-#define GCC_CFG_NOC_RPM_AHB_CLK 155 +-#define GCC_BIMC_DDR_CPLL0_CLK 156 +-#define GCC_BIMC_DDR_CPLL1_CLK 157 +-#define GCC_DDR_DIM_CFG_CLK 158 +-#define GCC_DDR_DIM_SLEEP_CLK 159 +-#define GCC_DEHR_CLK 160 +-#define GCC_AHB_CLK 161 +-#define GCC_IM_SLEEP_CLK 162 +-#define GCC_XO_CLK 163 +-#define GCC_XO_DIV4_CLK 164 +-#define GCC_GP1_CLK 165 +-#define GCC_GP2_CLK 166 +-#define GCC_GP3_CLK 167 +-#define GCC_IMEM_AXI_CLK 168 +-#define GCC_IMEM_CFG_AHB_CLK 169 +-#define GCC_KPSS_AHB_CLK 170 +-#define GCC_KPSS_AXI_CLK 171 +-#define GCC_LPASS_Q6_AXI_CLK 172 +-#define GCC_MMSS_NOC_AT_CLK 173 +-#define GCC_MMSS_NOC_CFG_AHB_CLK 174 +-#define GCC_OCMEM_NOC_CFG_AHB_CLK 175 +-#define GCC_OCMEM_SYS_NOC_AXI_CLK 176 +-#define GCC_MPM_AHB_CLK 177 +-#define GCC_MSG_RAM_AHB_CLK 178 +-#define GCC_MSS_CFG_AHB_CLK 179 +-#define GCC_MSS_Q6_BIMC_AXI_CLK 180 +-#define GCC_NOC_CONF_XPU_AHB_CLK 181 +-#define GCC_PDM2_CLK 182 +-#define GCC_PDM_AHB_CLK 183 +-#define GCC_PDM_XO4_CLK 184 +-#define GCC_PERIPH_NOC_AHB_CLK 185 +-#define GCC_PERIPH_NOC_AT_CLK 186 +-#define GCC_PERIPH_NOC_CFG_AHB_CLK 187 +-#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 188 +-#define GCC_PERIPH_XPU_AHB_CLK 189 +-#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 190 +-#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 191 +-#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 192 +-#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 193 +-#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 194 +-#define GCC_PRNG_AHB_CLK 195 +-#define GCC_QDSS_AT_CLK 196 +-#define GCC_QDSS_CFG_AHB_CLK 197 +-#define GCC_QDSS_DAP_AHB_CLK 198 +-#define GCC_QDSS_DAP_CLK 199 +-#define GCC_QDSS_ETR_USB_CLK 200 +-#define GCC_QDSS_STM_CLK 201 +-#define GCC_QDSS_TRACECLKIN_CLK 202 +-#define GCC_QDSS_TSCTR_DIV16_CLK 203 +-#define GCC_QDSS_TSCTR_DIV2_CLK 204 +-#define GCC_QDSS_TSCTR_DIV3_CLK 205 +-#define GCC_QDSS_TSCTR_DIV4_CLK 206 +-#define GCC_QDSS_TSCTR_DIV8_CLK 207 +-#define GCC_QDSS_RBCPR_XPU_AHB_CLK 208 +-#define GCC_RBCPR_AHB_CLK 209 +-#define GCC_RBCPR_CLK 210 +-#define GCC_RPM_BUS_AHB_CLK 211 +-#define GCC_RPM_PROC_HCLK 212 +-#define GCC_RPM_SLEEP_CLK 213 +-#define GCC_RPM_TIMER_CLK 214 +-#define GCC_SDCC1_AHB_CLK 215 +-#define GCC_SDCC1_APPS_CLK 216 +-#define GCC_SDCC1_INACTIVITY_TIMERS_CLK 217 +-#define GCC_SDCC2_AHB_CLK 218 +-#define GCC_SDCC2_APPS_CLK 219 +-#define GCC_SDCC2_INACTIVITY_TIMERS_CLK 220 +-#define GCC_SDCC3_AHB_CLK 221 +-#define GCC_SDCC3_APPS_CLK 222 +-#define GCC_SDCC3_INACTIVITY_TIMERS_CLK 223 +-#define GCC_SDCC4_AHB_CLK 224 +-#define GCC_SDCC4_APPS_CLK 225 +-#define GCC_SDCC4_INACTIVITY_TIMERS_CLK 226 +-#define GCC_SEC_CTRL_ACC_CLK 227 +-#define GCC_SEC_CTRL_AHB_CLK 228 +-#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 229 +-#define GCC_SEC_CTRL_CLK 230 +-#define GCC_SEC_CTRL_SENSE_CLK 231 +-#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 232 +-#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 233 +-#define GCC_SPDM_BIMC_CY_CLK 234 +-#define GCC_SPDM_CFG_AHB_CLK 235 +-#define GCC_SPDM_DEBUG_CY_CLK 236 +-#define GCC_SPDM_FF_CLK 237 +-#define GCC_SPDM_MSTR_AHB_CLK 238 +-#define GCC_SPDM_PNOC_CY_CLK 239 +-#define GCC_SPDM_RPM_CY_CLK 240 +-#define GCC_SPDM_SNOC_CY_CLK 241 +-#define GCC_SPMI_AHB_CLK 242 +-#define GCC_SPMI_CNOC_AHB_CLK 243 +-#define GCC_SPMI_SER_CLK 244 +-#define GCC_SNOC_CNOC_AHB_CLK 245 +-#define GCC_SNOC_PNOC_AHB_CLK 246 +-#define GCC_SYS_NOC_AT_CLK 247 +-#define GCC_SYS_NOC_AXI_CLK 248 +-#define GCC_SYS_NOC_KPSS_AHB_CLK 249 +-#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 250 +-#define GCC_SYS_NOC_USB3_AXI_CLK 251 +-#define GCC_TCSR_AHB_CLK 252 +-#define GCC_TLMM_AHB_CLK 253 +-#define GCC_TLMM_CLK 254 +-#define GCC_TSIF_AHB_CLK 255 +-#define GCC_TSIF_INACTIVITY_TIMERS_CLK 256 +-#define GCC_TSIF_REF_CLK 257 +-#define GCC_USB2A_PHY_SLEEP_CLK 258 +-#define GCC_USB2B_PHY_SLEEP_CLK 259 +-#define GCC_USB30_MASTER_CLK 260 +-#define GCC_USB30_MOCK_UTMI_CLK 261 +-#define GCC_USB30_SLEEP_CLK 262 +-#define GCC_USB_HS_AHB_CLK 263 +-#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 264 +-#define GCC_USB_HS_SYSTEM_CLK 265 +-#define GCC_USB_HSIC_AHB_CLK 266 +-#define GCC_USB_HSIC_CLK 267 +-#define GCC_USB_HSIC_IO_CAL_CLK 268 +-#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 269 +-#define GCC_USB_HSIC_SYSTEM_CLK 270 +-#define GCC_WCSS_GPLL1_CLK_SRC 271 +-#define GCC_MMSS_GPLL0_CLK_SRC 272 +-#define GCC_LPASS_GPLL0_CLK_SRC 273 +-#define GCC_WCSS_GPLL1_CLK_SRC_SLEEP_ENA 274 +-#define GCC_MMSS_GPLL0_CLK_SRC_SLEEP_ENA 275 +-#define GCC_LPASS_GPLL0_CLK_SRC_SLEEP_ENA 276 +-#define GCC_IMEM_AXI_CLK_SLEEP_ENA 277 +-#define GCC_SYS_NOC_KPSS_AHB_CLK_SLEEP_ENA 278 +-#define GCC_BIMC_KPSS_AXI_CLK_SLEEP_ENA 279 +-#define GCC_KPSS_AHB_CLK_SLEEP_ENA 280 +-#define GCC_KPSS_AXI_CLK_SLEEP_ENA 281 +-#define GCC_MPM_AHB_CLK_SLEEP_ENA 282 +-#define GCC_OCMEM_SYS_NOC_AXI_CLK_SLEEP_ENA 283 +-#define GCC_BLSP1_AHB_CLK_SLEEP_ENA 284 +-#define GCC_BLSP1_SLEEP_CLK_SLEEP_ENA 285 +-#define GCC_BLSP2_AHB_CLK_SLEEP_ENA 286 +-#define GCC_BLSP2_SLEEP_CLK_SLEEP_ENA 287 +-#define GCC_PRNG_AHB_CLK_SLEEP_ENA 288 +-#define GCC_BAM_DMA_AHB_CLK_SLEEP_ENA 289 +-#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK_SLEEP_ENA 290 +-#define GCC_BOOT_ROM_AHB_CLK_SLEEP_ENA 291 +-#define GCC_MSG_RAM_AHB_CLK_SLEEP_ENA 292 +-#define GCC_TLMM_AHB_CLK_SLEEP_ENA 293 +-#define GCC_TLMM_CLK_SLEEP_ENA 294 +-#define GCC_SPMI_CNOC_AHB_CLK_SLEEP_ENA 295 +-#define GCC_CE1_CLK_SLEEP_ENA 296 +-#define GCC_CE1_AXI_CLK_SLEEP_ENA 297 +-#define GCC_CE1_AHB_CLK_SLEEP_ENA 298 +-#define GCC_CE2_CLK_SLEEP_ENA 299 +-#define GCC_CE2_AXI_CLK_SLEEP_ENA 300 +-#define GCC_CE2_AHB_CLK_SLEEP_ENA 301 +-#define GPLL4 302 +-#define GPLL4_VOTE 303 +-#define GCC_SDCC1_CDCCAL_SLEEP_CLK 304 +-#define GCC_SDCC1_CDCCAL_FF_CLK 305 +- +-/* gdscs */ +-#define USB_HS_HSIC_GDSC 0 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8994.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8994.h +deleted file mode 100644 +index 507b8d6effd2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8994.h ++++ /dev/null +@@ -1,166 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2016, The Linux Foundation. All rights reserved. +- */ +- +- +-#ifndef _DT_BINDINGS_CLK_MSM_GCC_8994_H +-#define _DT_BINDINGS_CLK_MSM_GCC_8994_H +- +-#define GPLL0_EARLY 0 +-#define GPLL0 1 +-#define GPLL4_EARLY 2 +-#define GPLL4 3 +-#define UFS_AXI_CLK_SRC 4 +-#define USB30_MASTER_CLK_SRC 5 +-#define BLSP1_QUP1_I2C_APPS_CLK_SRC 6 +-#define BLSP1_QUP1_SPI_APPS_CLK_SRC 7 +-#define BLSP1_QUP2_I2C_APPS_CLK_SRC 8 +-#define BLSP1_QUP2_SPI_APPS_CLK_SRC 9 +-#define BLSP1_QUP3_I2C_APPS_CLK_SRC 10 +-#define BLSP1_QUP3_SPI_APPS_CLK_SRC 11 +-#define BLSP1_QUP4_I2C_APPS_CLK_SRC 12 +-#define BLSP1_QUP4_SPI_APPS_CLK_SRC 13 +-#define BLSP1_QUP5_I2C_APPS_CLK_SRC 14 +-#define BLSP1_QUP5_SPI_APPS_CLK_SRC 15 +-#define BLSP1_QUP6_I2C_APPS_CLK_SRC 16 +-#define BLSP1_QUP6_SPI_APPS_CLK_SRC 17 +-#define BLSP1_UART1_APPS_CLK_SRC 18 +-#define BLSP1_UART2_APPS_CLK_SRC 19 +-#define BLSP1_UART3_APPS_CLK_SRC 20 +-#define BLSP1_UART4_APPS_CLK_SRC 21 +-#define BLSP1_UART5_APPS_CLK_SRC 22 +-#define BLSP1_UART6_APPS_CLK_SRC 23 +-#define BLSP2_QUP1_I2C_APPS_CLK_SRC 24 +-#define BLSP2_QUP1_SPI_APPS_CLK_SRC 25 +-#define BLSP2_QUP2_I2C_APPS_CLK_SRC 26 +-#define BLSP2_QUP2_SPI_APPS_CLK_SRC 27 +-#define BLSP2_QUP3_I2C_APPS_CLK_SRC 28 +-#define BLSP2_QUP3_SPI_APPS_CLK_SRC 29 +-#define BLSP2_QUP4_I2C_APPS_CLK_SRC 30 +-#define BLSP2_QUP4_SPI_APPS_CLK_SRC 31 +-#define BLSP2_QUP5_I2C_APPS_CLK_SRC 32 +-#define BLSP2_QUP5_SPI_APPS_CLK_SRC 33 +-#define BLSP2_QUP6_I2C_APPS_CLK_SRC 34 +-#define BLSP2_QUP6_SPI_APPS_CLK_SRC 35 +-#define BLSP2_UART1_APPS_CLK_SRC 36 +-#define BLSP2_UART2_APPS_CLK_SRC 37 +-#define BLSP2_UART3_APPS_CLK_SRC 38 +-#define BLSP2_UART4_APPS_CLK_SRC 39 +-#define BLSP2_UART5_APPS_CLK_SRC 40 +-#define BLSP2_UART6_APPS_CLK_SRC 41 +-#define GP1_CLK_SRC 42 +-#define GP2_CLK_SRC 43 +-#define GP3_CLK_SRC 44 +-#define PCIE_0_AUX_CLK_SRC 45 +-#define PCIE_0_PIPE_CLK_SRC 46 +-#define PCIE_1_AUX_CLK_SRC 47 +-#define PCIE_1_PIPE_CLK_SRC 48 +-#define PDM2_CLK_SRC 49 +-#define SDCC1_APPS_CLK_SRC 50 +-#define SDCC2_APPS_CLK_SRC 51 +-#define SDCC3_APPS_CLK_SRC 52 +-#define SDCC4_APPS_CLK_SRC 53 +-#define TSIF_REF_CLK_SRC 54 +-#define USB30_MOCK_UTMI_CLK_SRC 55 +-#define USB3_PHY_AUX_CLK_SRC 56 +-#define USB_HS_SYSTEM_CLK_SRC 57 +-#define GCC_BLSP1_AHB_CLK 58 +-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 59 +-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 60 +-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 61 +-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 62 +-#define GCC_BLSP1_QUP3_I2C_APPS_CLK 63 +-#define GCC_BLSP1_QUP3_SPI_APPS_CLK 64 +-#define GCC_BLSP1_QUP4_I2C_APPS_CLK 65 +-#define GCC_BLSP1_QUP4_SPI_APPS_CLK 66 +-#define GCC_BLSP1_QUP5_I2C_APPS_CLK 67 +-#define GCC_BLSP1_QUP5_SPI_APPS_CLK 68 +-#define GCC_BLSP1_QUP6_I2C_APPS_CLK 69 +-#define GCC_BLSP1_QUP6_SPI_APPS_CLK 70 +-#define GCC_BLSP1_UART1_APPS_CLK 71 +-#define GCC_BLSP1_UART2_APPS_CLK 72 +-#define GCC_BLSP1_UART3_APPS_CLK 73 +-#define GCC_BLSP1_UART4_APPS_CLK 74 +-#define GCC_BLSP1_UART5_APPS_CLK 75 +-#define GCC_BLSP1_UART6_APPS_CLK 76 +-#define GCC_BLSP2_AHB_CLK 77 +-#define GCC_BLSP2_QUP1_I2C_APPS_CLK 78 +-#define GCC_BLSP2_QUP1_SPI_APPS_CLK 79 +-#define GCC_BLSP2_QUP2_I2C_APPS_CLK 80 +-#define GCC_BLSP2_QUP2_SPI_APPS_CLK 81 +-#define GCC_BLSP2_QUP3_I2C_APPS_CLK 82 +-#define GCC_BLSP2_QUP3_SPI_APPS_CLK 83 +-#define GCC_BLSP2_QUP4_I2C_APPS_CLK 84 +-#define GCC_BLSP2_QUP4_SPI_APPS_CLK 85 +-#define GCC_BLSP2_QUP5_I2C_APPS_CLK 86 +-#define GCC_BLSP2_QUP5_SPI_APPS_CLK 87 +-#define GCC_BLSP2_QUP6_I2C_APPS_CLK 88 +-#define GCC_BLSP2_QUP6_SPI_APPS_CLK 89 +-#define GCC_BLSP2_UART1_APPS_CLK 90 +-#define GCC_BLSP2_UART2_APPS_CLK 91 +-#define GCC_BLSP2_UART3_APPS_CLK 92 +-#define GCC_BLSP2_UART4_APPS_CLK 93 +-#define GCC_BLSP2_UART5_APPS_CLK 94 +-#define GCC_BLSP2_UART6_APPS_CLK 95 +-#define GCC_GP1_CLK 96 +-#define GCC_GP2_CLK 97 +-#define GCC_GP3_CLK 98 +-#define GCC_PCIE_0_AUX_CLK 99 +-#define GCC_PCIE_0_PIPE_CLK 100 +-#define GCC_PCIE_1_AUX_CLK 101 +-#define GCC_PCIE_1_PIPE_CLK 102 +-#define GCC_PDM2_CLK 103 +-#define GCC_SDCC1_APPS_CLK 104 +-#define GCC_SDCC2_APPS_CLK 105 +-#define GCC_SDCC3_APPS_CLK 106 +-#define GCC_SDCC4_APPS_CLK 107 +-#define GCC_SYS_NOC_UFS_AXI_CLK 108 +-#define GCC_SYS_NOC_USB3_AXI_CLK 109 +-#define GCC_TSIF_REF_CLK 110 +-#define GCC_UFS_AXI_CLK 111 +-#define GCC_UFS_RX_CFG_CLK 112 +-#define GCC_UFS_TX_CFG_CLK 113 +-#define GCC_USB30_MASTER_CLK 114 +-#define GCC_USB30_MOCK_UTMI_CLK 115 +-#define GCC_USB3_PHY_AUX_CLK 116 +-#define GCC_USB_HS_SYSTEM_CLK 117 +-#define GCC_SDCC1_AHB_CLK 118 +-#define GCC_LPASS_Q6_AXI_CLK 119 +-#define GCC_MSS_Q6_BIMC_AXI_CLK 120 +-#define GCC_PCIE_0_CFG_AHB_CLK 121 +-#define GCC_PCIE_0_MSTR_AXI_CLK 122 +-#define GCC_PCIE_0_SLV_AXI_CLK 123 +-#define GCC_PCIE_1_CFG_AHB_CLK 124 +-#define GCC_PCIE_1_MSTR_AXI_CLK 125 +-#define GCC_PCIE_1_SLV_AXI_CLK 126 +-#define GCC_PDM_AHB_CLK 127 +-#define GCC_SDCC2_AHB_CLK 128 +-#define GCC_SDCC3_AHB_CLK 129 +-#define GCC_SDCC4_AHB_CLK 130 +-#define GCC_TSIF_AHB_CLK 131 +-#define GCC_UFS_AHB_CLK 132 +-#define GCC_UFS_RX_SYMBOL_0_CLK 133 +-#define GCC_UFS_RX_SYMBOL_1_CLK 134 +-#define GCC_UFS_TX_SYMBOL_0_CLK 135 +-#define GCC_UFS_TX_SYMBOL_1_CLK 136 +-#define GCC_USB2_HS_PHY_SLEEP_CLK 137 +-#define GCC_USB30_SLEEP_CLK 138 +-#define GCC_USB_HS_AHB_CLK 139 +-#define GCC_USB_PHY_CFG_AHB2PHY_CLK 140 +- +-/* GDSCs */ +-#define PCIE_GDSC 0 +-#define PCIE_0_GDSC 1 +-#define PCIE_1_GDSC 2 +-#define USB30_GDSC 3 +-#define UFS_GDSC 4 +- +-/* Resets */ +-#define USB3_PHY_RESET 0 +-#define USB3PHY_PHY_RESET 1 +-#define PCIE_PHY_0_RESET 2 +-#define PCIE_PHY_1_RESET 3 +-#define QUSB2_PHY_RESET 4 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8996.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8996.h +deleted file mode 100644 +index 03bf49d43d24..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8996.h ++++ /dev/null +@@ -1,359 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2015, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H +-#define _DT_BINDINGS_CLK_MSM_GCC_8996_H +- +-#define GPLL0_EARLY 0 +-#define GPLL0 1 +-#define GPLL1_EARLY 2 +-#define GPLL1 3 +-#define GPLL2_EARLY 4 +-#define GPLL2 5 +-#define GPLL3_EARLY 6 +-#define GPLL3 7 +-#define GPLL4_EARLY 8 +-#define GPLL4 9 +-#define SYSTEM_NOC_CLK_SRC 10 +-#define CONFIG_NOC_CLK_SRC 11 +-#define PERIPH_NOC_CLK_SRC 12 +-#define MMSS_BIMC_GFX_CLK_SRC 13 +-#define USB30_MASTER_CLK_SRC 14 +-#define USB30_MOCK_UTMI_CLK_SRC 15 +-#define USB3_PHY_AUX_CLK_SRC 16 +-#define USB20_MASTER_CLK_SRC 17 +-#define USB20_MOCK_UTMI_CLK_SRC 18 +-#define SDCC1_APPS_CLK_SRC 19 +-#define SDCC1_ICE_CORE_CLK_SRC 20 +-#define SDCC2_APPS_CLK_SRC 21 +-#define SDCC3_APPS_CLK_SRC 22 +-#define SDCC4_APPS_CLK_SRC 23 +-#define BLSP1_QUP1_SPI_APPS_CLK_SRC 24 +-#define BLSP1_QUP1_I2C_APPS_CLK_SRC 25 +-#define BLSP1_UART1_APPS_CLK_SRC 26 +-#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 +-#define BLSP1_QUP2_I2C_APPS_CLK_SRC 28 +-#define BLSP1_UART2_APPS_CLK_SRC 29 +-#define BLSP1_QUP3_SPI_APPS_CLK_SRC 30 +-#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 +-#define BLSP1_UART3_APPS_CLK_SRC 32 +-#define BLSP1_QUP4_SPI_APPS_CLK_SRC 33 +-#define BLSP1_QUP4_I2C_APPS_CLK_SRC 34 +-#define BLSP1_UART4_APPS_CLK_SRC 35 +-#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 +-#define BLSP1_QUP5_I2C_APPS_CLK_SRC 37 +-#define BLSP1_UART5_APPS_CLK_SRC 38 +-#define BLSP1_QUP6_SPI_APPS_CLK_SRC 39 +-#define BLSP1_QUP6_I2C_APPS_CLK_SRC 40 +-#define BLSP1_UART6_APPS_CLK_SRC 41 +-#define BLSP2_QUP1_SPI_APPS_CLK_SRC 42 +-#define BLSP2_QUP1_I2C_APPS_CLK_SRC 43 +-#define BLSP2_UART1_APPS_CLK_SRC 44 +-#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 +-#define BLSP2_QUP2_I2C_APPS_CLK_SRC 46 +-#define BLSP2_UART2_APPS_CLK_SRC 47 +-#define BLSP2_QUP3_SPI_APPS_CLK_SRC 48 +-#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 +-#define BLSP2_UART3_APPS_CLK_SRC 50 +-#define BLSP2_QUP4_SPI_APPS_CLK_SRC 51 +-#define BLSP2_QUP4_I2C_APPS_CLK_SRC 52 +-#define BLSP2_UART4_APPS_CLK_SRC 53 +-#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 +-#define BLSP2_QUP5_I2C_APPS_CLK_SRC 55 +-#define BLSP2_UART5_APPS_CLK_SRC 56 +-#define BLSP2_QUP6_SPI_APPS_CLK_SRC 57 +-#define BLSP2_QUP6_I2C_APPS_CLK_SRC 58 +-#define BLSP2_UART6_APPS_CLK_SRC 59 +-#define PDM2_CLK_SRC 60 +-#define TSIF_REF_CLK_SRC 61 +-#define CE1_CLK_SRC 62 +-#define GCC_SLEEP_CLK_SRC 63 +-#define BIMC_CLK_SRC 64 +-#define HMSS_AHB_CLK_SRC 65 +-#define BIMC_HMSS_AXI_CLK_SRC 66 +-#define HMSS_RBCPR_CLK_SRC 67 +-#define HMSS_GPLL0_CLK_SRC 68 +-#define GP1_CLK_SRC 69 +-#define GP2_CLK_SRC 70 +-#define GP3_CLK_SRC 71 +-#define PCIE_AUX_CLK_SRC 72 +-#define UFS_AXI_CLK_SRC 73 +-#define UFS_ICE_CORE_CLK_SRC 74 +-#define QSPI_SER_CLK_SRC 75 +-#define GCC_SYS_NOC_AXI_CLK 76 +-#define GCC_SYS_NOC_HMSS_AHB_CLK 77 +-#define GCC_SNOC_CNOC_AHB_CLK 78 +-#define GCC_SNOC_PNOC_AHB_CLK 79 +-#define GCC_SYS_NOC_AT_CLK 80 +-#define GCC_SYS_NOC_USB3_AXI_CLK 81 +-#define GCC_SYS_NOC_UFS_AXI_CLK 82 +-#define GCC_CFG_NOC_AHB_CLK 83 +-#define GCC_PERIPH_NOC_AHB_CLK 84 +-#define GCC_PERIPH_NOC_USB20_AHB_CLK 85 +-#define GCC_TIC_CLK 86 +-#define GCC_IMEM_AXI_CLK 87 +-#define GCC_MMSS_SYS_NOC_AXI_CLK 88 +-#define GCC_MMSS_NOC_CFG_AHB_CLK 89 +-#define GCC_MMSS_BIMC_GFX_CLK 90 +-#define GCC_USB30_MASTER_CLK 91 +-#define GCC_USB30_SLEEP_CLK 92 +-#define GCC_USB30_MOCK_UTMI_CLK 93 +-#define GCC_USB3_PHY_AUX_CLK 94 +-#define GCC_USB3_PHY_PIPE_CLK 95 +-#define GCC_USB20_MASTER_CLK 96 +-#define GCC_USB20_SLEEP_CLK 97 +-#define GCC_USB20_MOCK_UTMI_CLK 98 +-#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99 +-#define GCC_SDCC1_APPS_CLK 100 +-#define GCC_SDCC1_AHB_CLK 101 +-#define GCC_SDCC1_ICE_CORE_CLK 102 +-#define GCC_SDCC2_APPS_CLK 103 +-#define GCC_SDCC2_AHB_CLK 104 +-#define GCC_SDCC3_APPS_CLK 105 +-#define GCC_SDCC3_AHB_CLK 106 +-#define GCC_SDCC4_APPS_CLK 107 +-#define GCC_SDCC4_AHB_CLK 108 +-#define GCC_BLSP1_AHB_CLK 109 +-#define GCC_BLSP1_SLEEP_CLK 110 +-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 111 +-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 112 +-#define GCC_BLSP1_UART1_APPS_CLK 113 +-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 114 +-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 115 +-#define GCC_BLSP1_UART2_APPS_CLK 116 +-#define GCC_BLSP1_QUP3_SPI_APPS_CLK 117 +-#define GCC_BLSP1_QUP3_I2C_APPS_CLK 118 +-#define GCC_BLSP1_UART3_APPS_CLK 119 +-#define GCC_BLSP1_QUP4_SPI_APPS_CLK 120 +-#define GCC_BLSP1_QUP4_I2C_APPS_CLK 121 +-#define GCC_BLSP1_UART4_APPS_CLK 122 +-#define GCC_BLSP1_QUP5_SPI_APPS_CLK 123 +-#define GCC_BLSP1_QUP5_I2C_APPS_CLK 124 +-#define GCC_BLSP1_UART5_APPS_CLK 125 +-#define GCC_BLSP1_QUP6_SPI_APPS_CLK 126 +-#define GCC_BLSP1_QUP6_I2C_APPS_CLK 127 +-#define GCC_BLSP1_UART6_APPS_CLK 128 +-#define GCC_BLSP2_AHB_CLK 129 +-#define GCC_BLSP2_SLEEP_CLK 130 +-#define GCC_BLSP2_QUP1_SPI_APPS_CLK 131 +-#define GCC_BLSP2_QUP1_I2C_APPS_CLK 132 +-#define GCC_BLSP2_UART1_APPS_CLK 133 +-#define GCC_BLSP2_QUP2_SPI_APPS_CLK 134 +-#define GCC_BLSP2_QUP2_I2C_APPS_CLK 135 +-#define GCC_BLSP2_UART2_APPS_CLK 136 +-#define GCC_BLSP2_QUP3_SPI_APPS_CLK 137 +-#define GCC_BLSP2_QUP3_I2C_APPS_CLK 138 +-#define GCC_BLSP2_UART3_APPS_CLK 139 +-#define GCC_BLSP2_QUP4_SPI_APPS_CLK 140 +-#define GCC_BLSP2_QUP4_I2C_APPS_CLK 141 +-#define GCC_BLSP2_UART4_APPS_CLK 142 +-#define GCC_BLSP2_QUP5_SPI_APPS_CLK 143 +-#define GCC_BLSP2_QUP5_I2C_APPS_CLK 144 +-#define GCC_BLSP2_UART5_APPS_CLK 145 +-#define GCC_BLSP2_QUP6_SPI_APPS_CLK 146 +-#define GCC_BLSP2_QUP6_I2C_APPS_CLK 147 +-#define GCC_BLSP2_UART6_APPS_CLK 148 +-#define GCC_PDM_AHB_CLK 149 +-#define GCC_PDM_XO4_CLK 150 +-#define GCC_PDM2_CLK 151 +-#define GCC_PRNG_AHB_CLK 152 +-#define GCC_TSIF_AHB_CLK 153 +-#define GCC_TSIF_REF_CLK 154 +-#define GCC_TSIF_INACTIVITY_TIMERS_CLK 155 +-#define GCC_TCSR_AHB_CLK 156 +-#define GCC_BOOT_ROM_AHB_CLK 157 +-#define GCC_MSG_RAM_AHB_CLK 158 +-#define GCC_TLMM_AHB_CLK 159 +-#define GCC_TLMM_CLK 160 +-#define GCC_MPM_AHB_CLK 161 +-#define GCC_SPMI_SER_CLK 162 +-#define GCC_SPMI_CNOC_AHB_CLK 163 +-#define GCC_CE1_CLK 164 +-#define GCC_CE1_AXI_CLK 165 +-#define GCC_CE1_AHB_CLK 166 +-#define GCC_BIMC_HMSS_AXI_CLK 167 +-#define GCC_BIMC_GFX_CLK 168 +-#define GCC_HMSS_AHB_CLK 169 +-#define GCC_HMSS_SLV_AXI_CLK 170 +-#define GCC_HMSS_MSTR_AXI_CLK 171 +-#define GCC_HMSS_RBCPR_CLK 172 +-#define GCC_GP1_CLK 173 +-#define GCC_GP2_CLK 174 +-#define GCC_GP3_CLK 175 +-#define GCC_PCIE_0_SLV_AXI_CLK 176 +-#define GCC_PCIE_0_MSTR_AXI_CLK 177 +-#define GCC_PCIE_0_CFG_AHB_CLK 178 +-#define GCC_PCIE_0_AUX_CLK 179 +-#define GCC_PCIE_0_PIPE_CLK 180 +-#define GCC_PCIE_1_SLV_AXI_CLK 181 +-#define GCC_PCIE_1_MSTR_AXI_CLK 182 +-#define GCC_PCIE_1_CFG_AHB_CLK 183 +-#define GCC_PCIE_1_AUX_CLK 184 +-#define GCC_PCIE_1_PIPE_CLK 185 +-#define GCC_PCIE_2_SLV_AXI_CLK 186 +-#define GCC_PCIE_2_MSTR_AXI_CLK 187 +-#define GCC_PCIE_2_CFG_AHB_CLK 188 +-#define GCC_PCIE_2_AUX_CLK 189 +-#define GCC_PCIE_2_PIPE_CLK 190 +-#define GCC_PCIE_PHY_CFG_AHB_CLK 191 +-#define GCC_PCIE_PHY_AUX_CLK 192 +-#define GCC_UFS_AXI_CLK 193 +-#define GCC_UFS_AHB_CLK 194 +-#define GCC_UFS_TX_CFG_CLK 195 +-#define GCC_UFS_RX_CFG_CLK 196 +-#define GCC_UFS_TX_SYMBOL_0_CLK 197 +-#define GCC_UFS_RX_SYMBOL_0_CLK 198 +-#define GCC_UFS_RX_SYMBOL_1_CLK 199 +-#define GCC_UFS_UNIPRO_CORE_CLK 200 +-#define GCC_UFS_ICE_CORE_CLK 201 +-#define GCC_UFS_SYS_CLK_CORE_CLK 202 +-#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 203 +-#define GCC_AGGRE0_SNOC_AXI_CLK 204 +-#define GCC_AGGRE0_CNOC_AHB_CLK 205 +-#define GCC_SMMU_AGGRE0_AXI_CLK 206 +-#define GCC_SMMU_AGGRE0_AHB_CLK 207 +-#define GCC_AGGRE1_PNOC_AHB_CLK 208 +-#define GCC_AGGRE2_UFS_AXI_CLK 209 +-#define GCC_AGGRE2_USB3_AXI_CLK 210 +-#define GCC_QSPI_AHB_CLK 211 +-#define GCC_QSPI_SER_CLK 212 +-#define GCC_USB3_CLKREF_CLK 213 +-#define GCC_HDMI_CLKREF_CLK 214 +-#define GCC_UFS_CLKREF_CLK 215 +-#define GCC_PCIE_CLKREF_CLK 216 +-#define GCC_RX2_USB2_CLKREF_CLK 217 +-#define GCC_RX1_USB2_CLKREF_CLK 218 +-#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219 +-#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220 +-#define GCC_EDP_CLKREF_CLK 221 +-#define GCC_MSS_CFG_AHB_CLK 222 +-#define GCC_MSS_Q6_BIMC_AXI_CLK 223 +-#define GCC_MSS_SNOC_AXI_CLK 224 +-#define GCC_MSS_MNOC_BIMC_AXI_CLK 225 +-#define GCC_DCC_AHB_CLK 226 +-#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 227 +-#define GCC_MMSS_GPLL0_DIV_CLK 228 +-#define GCC_MSS_GPLL0_DIV_CLK 229 +- +-#define GCC_SYSTEM_NOC_BCR 0 +-#define GCC_CONFIG_NOC_BCR 1 +-#define GCC_PERIPH_NOC_BCR 2 +-#define GCC_IMEM_BCR 3 +-#define GCC_MMSS_BCR 4 +-#define GCC_PIMEM_BCR 5 +-#define GCC_QDSS_BCR 6 +-#define GCC_USB_30_BCR 7 +-#define GCC_USB_20_BCR 8 +-#define GCC_QUSB2PHY_PRIM_BCR 9 +-#define GCC_QUSB2PHY_SEC_BCR 10 +-#define GCC_USB_PHY_CFG_AHB2PHY_BCR 11 +-#define GCC_SDCC1_BCR 12 +-#define GCC_SDCC2_BCR 13 +-#define GCC_SDCC3_BCR 14 +-#define GCC_SDCC4_BCR 15 +-#define GCC_BLSP1_BCR 16 +-#define GCC_BLSP1_QUP1_BCR 17 +-#define GCC_BLSP1_UART1_BCR 18 +-#define GCC_BLSP1_QUP2_BCR 19 +-#define GCC_BLSP1_UART2_BCR 20 +-#define GCC_BLSP1_QUP3_BCR 21 +-#define GCC_BLSP1_UART3_BCR 22 +-#define GCC_BLSP1_QUP4_BCR 23 +-#define GCC_BLSP1_UART4_BCR 24 +-#define GCC_BLSP1_QUP5_BCR 25 +-#define GCC_BLSP1_UART5_BCR 26 +-#define GCC_BLSP1_QUP6_BCR 27 +-#define GCC_BLSP1_UART6_BCR 28 +-#define GCC_BLSP2_BCR 29 +-#define GCC_BLSP2_QUP1_BCR 30 +-#define GCC_BLSP2_UART1_BCR 31 +-#define GCC_BLSP2_QUP2_BCR 32 +-#define GCC_BLSP2_UART2_BCR 33 +-#define GCC_BLSP2_QUP3_BCR 34 +-#define GCC_BLSP2_UART3_BCR 35 +-#define GCC_BLSP2_QUP4_BCR 36 +-#define GCC_BLSP2_UART4_BCR 37 +-#define GCC_BLSP2_QUP5_BCR 38 +-#define GCC_BLSP2_UART5_BCR 39 +-#define GCC_BLSP2_QUP6_BCR 40 +-#define GCC_BLSP2_UART6_BCR 41 +-#define GCC_PDM_BCR 42 +-#define GCC_PRNG_BCR 43 +-#define GCC_TSIF_BCR 44 +-#define GCC_TCSR_BCR 45 +-#define GCC_BOOT_ROM_BCR 46 +-#define GCC_MSG_RAM_BCR 47 +-#define GCC_TLMM_BCR 48 +-#define GCC_MPM_BCR 49 +-#define GCC_SEC_CTRL_BCR 50 +-#define GCC_SPMI_BCR 51 +-#define GCC_SPDM_BCR 52 +-#define GCC_CE1_BCR 53 +-#define GCC_BIMC_BCR 54 +-#define GCC_SNOC_BUS_TIMEOUT0_BCR 55 +-#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 +-#define GCC_SNOC_BUS_TIMEOUT1_BCR 57 +-#define GCC_SNOC_BUS_TIMEOUT3_BCR 58 +-#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 59 +-#define GCC_PNOC_BUS_TIMEOUT0_BCR 60 +-#define GCC_PNOC_BUS_TIMEOUT1_BCR 61 +-#define GCC_PNOC_BUS_TIMEOUT2_BCR 62 +-#define GCC_PNOC_BUS_TIMEOUT3_BCR 63 +-#define GCC_PNOC_BUS_TIMEOUT4_BCR 64 +-#define GCC_CNOC_BUS_TIMEOUT0_BCR 65 +-#define GCC_CNOC_BUS_TIMEOUT1_BCR 66 +-#define GCC_CNOC_BUS_TIMEOUT2_BCR 67 +-#define GCC_CNOC_BUS_TIMEOUT3_BCR 68 +-#define GCC_CNOC_BUS_TIMEOUT4_BCR 69 +-#define GCC_CNOC_BUS_TIMEOUT5_BCR 70 +-#define GCC_CNOC_BUS_TIMEOUT6_BCR 71 +-#define GCC_CNOC_BUS_TIMEOUT7_BCR 72 +-#define GCC_CNOC_BUS_TIMEOUT8_BCR 73 +-#define GCC_CNOC_BUS_TIMEOUT9_BCR 74 +-#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 75 +-#define GCC_APB2JTAG_BCR 76 +-#define GCC_RBCPR_CX_BCR 77 +-#define GCC_RBCPR_MX_BCR 78 +-#define GCC_PCIE_0_BCR 79 +-#define GCC_PCIE_0_PHY_BCR 80 +-#define GCC_PCIE_1_BCR 81 +-#define GCC_PCIE_1_PHY_BCR 82 +-#define GCC_PCIE_2_BCR 83 +-#define GCC_PCIE_2_PHY_BCR 84 +-#define GCC_PCIE_PHY_BCR 85 +-#define GCC_DCD_BCR 86 +-#define GCC_OBT_ODT_BCR 87 +-#define GCC_UFS_BCR 88 +-#define GCC_SSC_BCR 89 +-#define GCC_VS_BCR 90 +-#define GCC_AGGRE0_NOC_BCR 91 +-#define GCC_AGGRE1_NOC_BCR 92 +-#define GCC_AGGRE2_NOC_BCR 93 +-#define GCC_DCC_BCR 94 +-#define GCC_IPA_BCR 95 +-#define GCC_QSPI_BCR 96 +-#define GCC_SKL_BCR 97 +-#define GCC_MSMPU_BCR 98 +-#define GCC_MSS_Q6_BCR 99 +-#define GCC_QREFS_VBG_CAL_BCR 100 +-#define GCC_PCIE_PHY_COM_BCR 101 +-#define GCC_PCIE_PHY_COM_NOCSR_BCR 102 +-#define GCC_USB3_PHY_BCR 103 +-#define GCC_USB3PHY_PHY_BCR 104 +-#define GCC_MSS_RESTART 105 +- +- +-/* Indexes for GDSCs */ +-#define AGGRE0_NOC_GDSC 0 +-#define HLOS1_VOTE_AGGRE0_NOC_GDSC 1 +-#define HLOS1_VOTE_LPASS_ADSP_GDSC 2 +-#define HLOS1_VOTE_LPASS_CORE_GDSC 3 +-#define USB30_GDSC 4 +-#define PCIE0_GDSC 5 +-#define PCIE1_GDSC 6 +-#define PCIE2_GDSC 7 +-#define UFS_GDSC 8 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8998.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8998.h +deleted file mode 100644 +index 72c99e486d86..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-msm8998.h ++++ /dev/null +@@ -1,304 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2016, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H +-#define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H +- +-#define BLSP1_QUP1_I2C_APPS_CLK_SRC 0 +-#define BLSP1_QUP1_SPI_APPS_CLK_SRC 1 +-#define BLSP1_QUP2_I2C_APPS_CLK_SRC 2 +-#define BLSP1_QUP2_SPI_APPS_CLK_SRC 3 +-#define BLSP1_QUP3_I2C_APPS_CLK_SRC 4 +-#define BLSP1_QUP3_SPI_APPS_CLK_SRC 5 +-#define BLSP1_QUP4_I2C_APPS_CLK_SRC 6 +-#define BLSP1_QUP4_SPI_APPS_CLK_SRC 7 +-#define BLSP1_QUP5_I2C_APPS_CLK_SRC 8 +-#define BLSP1_QUP5_SPI_APPS_CLK_SRC 9 +-#define BLSP1_QUP6_I2C_APPS_CLK_SRC 10 +-#define BLSP1_QUP6_SPI_APPS_CLK_SRC 11 +-#define BLSP1_UART1_APPS_CLK_SRC 12 +-#define BLSP1_UART2_APPS_CLK_SRC 13 +-#define BLSP1_UART3_APPS_CLK_SRC 14 +-#define BLSP2_QUP1_I2C_APPS_CLK_SRC 15 +-#define BLSP2_QUP1_SPI_APPS_CLK_SRC 16 +-#define BLSP2_QUP2_I2C_APPS_CLK_SRC 17 +-#define BLSP2_QUP2_SPI_APPS_CLK_SRC 18 +-#define BLSP2_QUP3_I2C_APPS_CLK_SRC 19 +-#define BLSP2_QUP3_SPI_APPS_CLK_SRC 20 +-#define BLSP2_QUP4_I2C_APPS_CLK_SRC 21 +-#define BLSP2_QUP4_SPI_APPS_CLK_SRC 22 +-#define BLSP2_QUP5_I2C_APPS_CLK_SRC 23 +-#define BLSP2_QUP5_SPI_APPS_CLK_SRC 24 +-#define BLSP2_QUP6_I2C_APPS_CLK_SRC 25 +-#define BLSP2_QUP6_SPI_APPS_CLK_SRC 26 +-#define BLSP2_UART1_APPS_CLK_SRC 27 +-#define BLSP2_UART2_APPS_CLK_SRC 28 +-#define BLSP2_UART3_APPS_CLK_SRC 29 +-#define GCC_AGGRE1_NOC_XO_CLK 30 +-#define GCC_AGGRE1_UFS_AXI_CLK 31 +-#define GCC_AGGRE1_USB3_AXI_CLK 32 +-#define GCC_APSS_QDSS_TSCTR_DIV2_CLK 33 +-#define GCC_APSS_QDSS_TSCTR_DIV8_CLK 34 +-#define GCC_BIMC_HMSS_AXI_CLK 35 +-#define GCC_BIMC_MSS_Q6_AXI_CLK 36 +-#define GCC_BLSP1_AHB_CLK 37 +-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 38 +-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 39 +-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 40 +-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 41 +-#define GCC_BLSP1_QUP3_I2C_APPS_CLK 42 +-#define GCC_BLSP1_QUP3_SPI_APPS_CLK 43 +-#define GCC_BLSP1_QUP4_I2C_APPS_CLK 44 +-#define GCC_BLSP1_QUP4_SPI_APPS_CLK 45 +-#define GCC_BLSP1_QUP5_I2C_APPS_CLK 46 +-#define GCC_BLSP1_QUP5_SPI_APPS_CLK 47 +-#define GCC_BLSP1_QUP6_I2C_APPS_CLK 48 +-#define GCC_BLSP1_QUP6_SPI_APPS_CLK 49 +-#define GCC_BLSP1_SLEEP_CLK 50 +-#define GCC_BLSP1_UART1_APPS_CLK 51 +-#define GCC_BLSP1_UART2_APPS_CLK 52 +-#define GCC_BLSP1_UART3_APPS_CLK 53 +-#define GCC_BLSP2_AHB_CLK 54 +-#define GCC_BLSP2_QUP1_I2C_APPS_CLK 55 +-#define GCC_BLSP2_QUP1_SPI_APPS_CLK 56 +-#define GCC_BLSP2_QUP2_I2C_APPS_CLK 57 +-#define GCC_BLSP2_QUP2_SPI_APPS_CLK 58 +-#define GCC_BLSP2_QUP3_I2C_APPS_CLK 59 +-#define GCC_BLSP2_QUP3_SPI_APPS_CLK 60 +-#define GCC_BLSP2_QUP4_I2C_APPS_CLK 61 +-#define GCC_BLSP2_QUP4_SPI_APPS_CLK 62 +-#define GCC_BLSP2_QUP5_I2C_APPS_CLK 63 +-#define GCC_BLSP2_QUP5_SPI_APPS_CLK 64 +-#define GCC_BLSP2_QUP6_I2C_APPS_CLK 65 +-#define GCC_BLSP2_QUP6_SPI_APPS_CLK 66 +-#define GCC_BLSP2_SLEEP_CLK 67 +-#define GCC_BLSP2_UART1_APPS_CLK 68 +-#define GCC_BLSP2_UART2_APPS_CLK 69 +-#define GCC_BLSP2_UART3_APPS_CLK 70 +-#define GCC_CFG_NOC_USB3_AXI_CLK 71 +-#define GCC_GP1_CLK 72 +-#define GCC_GP2_CLK 73 +-#define GCC_GP3_CLK 74 +-#define GCC_GPU_BIMC_GFX_CLK 75 +-#define GCC_GPU_BIMC_GFX_SRC_CLK 76 +-#define GCC_GPU_CFG_AHB_CLK 77 +-#define GCC_GPU_SNOC_DVM_GFX_CLK 78 +-#define GCC_HMSS_AHB_CLK 79 +-#define GCC_HMSS_AT_CLK 80 +-#define GCC_HMSS_DVM_BUS_CLK 81 +-#define GCC_HMSS_RBCPR_CLK 82 +-#define GCC_HMSS_TRIG_CLK 83 +-#define GCC_LPASS_AT_CLK 84 +-#define GCC_LPASS_TRIG_CLK 85 +-#define GCC_MMSS_NOC_CFG_AHB_CLK 86 +-#define GCC_MMSS_QM_AHB_CLK 87 +-#define GCC_MMSS_QM_CORE_CLK 88 +-#define GCC_MMSS_SYS_NOC_AXI_CLK 89 +-#define GCC_MSS_AT_CLK 90 +-#define GCC_PCIE_0_AUX_CLK 91 +-#define GCC_PCIE_0_CFG_AHB_CLK 92 +-#define GCC_PCIE_0_MSTR_AXI_CLK 93 +-#define GCC_PCIE_0_PIPE_CLK 94 +-#define GCC_PCIE_0_SLV_AXI_CLK 95 +-#define GCC_PCIE_PHY_AUX_CLK 96 +-#define GCC_PDM2_CLK 97 +-#define GCC_PDM_AHB_CLK 98 +-#define GCC_PDM_XO4_CLK 99 +-#define GCC_PRNG_AHB_CLK 100 +-#define GCC_SDCC2_AHB_CLK 101 +-#define GCC_SDCC2_APPS_CLK 102 +-#define GCC_SDCC4_AHB_CLK 103 +-#define GCC_SDCC4_APPS_CLK 104 +-#define GCC_TSIF_AHB_CLK 105 +-#define GCC_TSIF_INACTIVITY_TIMERS_CLK 106 +-#define GCC_TSIF_REF_CLK 107 +-#define GCC_UFS_AHB_CLK 108 +-#define GCC_UFS_AXI_CLK 109 +-#define GCC_UFS_ICE_CORE_CLK 110 +-#define GCC_UFS_PHY_AUX_CLK 111 +-#define GCC_UFS_RX_SYMBOL_0_CLK 112 +-#define GCC_UFS_RX_SYMBOL_1_CLK 113 +-#define GCC_UFS_TX_SYMBOL_0_CLK 114 +-#define GCC_UFS_UNIPRO_CORE_CLK 115 +-#define GCC_USB30_MASTER_CLK 116 +-#define GCC_USB30_MOCK_UTMI_CLK 117 +-#define GCC_USB30_SLEEP_CLK 118 +-#define GCC_USB3_PHY_AUX_CLK 119 +-#define GCC_USB3_PHY_PIPE_CLK 120 +-#define GCC_USB_PHY_CFG_AHB2PHY_CLK 121 +-#define GP1_CLK_SRC 122 +-#define GP2_CLK_SRC 123 +-#define GP3_CLK_SRC 124 +-#define GPLL0 125 +-#define GPLL0_OUT_EVEN 126 +-#define GPLL0_OUT_MAIN 127 +-#define GPLL0_OUT_ODD 128 +-#define GPLL0_OUT_TEST 129 +-#define GPLL1 130 +-#define GPLL1_OUT_EVEN 131 +-#define GPLL1_OUT_MAIN 132 +-#define GPLL1_OUT_ODD 133 +-#define GPLL1_OUT_TEST 134 +-#define GPLL2 135 +-#define GPLL2_OUT_EVEN 136 +-#define GPLL2_OUT_MAIN 137 +-#define GPLL2_OUT_ODD 138 +-#define GPLL2_OUT_TEST 139 +-#define GPLL3 140 +-#define GPLL3_OUT_EVEN 141 +-#define GPLL3_OUT_MAIN 142 +-#define GPLL3_OUT_ODD 143 +-#define GPLL3_OUT_TEST 144 +-#define GPLL4 145 +-#define GPLL4_OUT_EVEN 146 +-#define GPLL4_OUT_MAIN 147 +-#define GPLL4_OUT_ODD 148 +-#define GPLL4_OUT_TEST 149 +-#define GPLL6 150 +-#define GPLL6_OUT_EVEN 151 +-#define GPLL6_OUT_MAIN 152 +-#define GPLL6_OUT_ODD 153 +-#define GPLL6_OUT_TEST 154 +-#define HMSS_AHB_CLK_SRC 155 +-#define HMSS_RBCPR_CLK_SRC 156 +-#define PCIE_AUX_CLK_SRC 157 +-#define PDM2_CLK_SRC 158 +-#define SDCC2_APPS_CLK_SRC 159 +-#define SDCC4_APPS_CLK_SRC 160 +-#define TSIF_REF_CLK_SRC 161 +-#define UFS_AXI_CLK_SRC 162 +-#define USB30_MASTER_CLK_SRC 163 +-#define USB30_MOCK_UTMI_CLK_SRC 164 +-#define USB3_PHY_AUX_CLK_SRC 165 +-#define GCC_USB3_CLKREF_CLK 166 +-#define GCC_HDMI_CLKREF_CLK 167 +-#define GCC_UFS_CLKREF_CLK 168 +-#define GCC_PCIE_CLKREF_CLK 169 +-#define GCC_RX1_USB2_CLKREF_CLK 170 +-#define GCC_MSS_CFG_AHB_CLK 171 +-#define GCC_BOOT_ROM_AHB_CLK 172 +-#define GCC_MSS_GPLL0_DIV_CLK_SRC 173 +-#define GCC_MSS_SNOC_AXI_CLK 174 +-#define GCC_MSS_MNOC_BIMC_AXI_CLK 175 +-#define GCC_BIMC_GFX_CLK 176 +-#define UFS_UNIPRO_CORE_CLK_SRC 177 +-#define GCC_MMSS_GPLL0_CLK 178 +-#define HMSS_GPLL0_CLK_SRC 179 +- +-#define PCIE_0_GDSC 0 +-#define UFS_GDSC 1 +-#define USB_30_GDSC 2 +- +-#define GCC_BLSP1_QUP1_BCR 0 +-#define GCC_BLSP1_QUP2_BCR 1 +-#define GCC_BLSP1_QUP3_BCR 2 +-#define GCC_BLSP1_QUP4_BCR 3 +-#define GCC_BLSP1_QUP5_BCR 4 +-#define GCC_BLSP1_QUP6_BCR 5 +-#define GCC_BLSP2_QUP1_BCR 6 +-#define GCC_BLSP2_QUP2_BCR 7 +-#define GCC_BLSP2_QUP3_BCR 8 +-#define GCC_BLSP2_QUP4_BCR 9 +-#define GCC_BLSP2_QUP5_BCR 10 +-#define GCC_BLSP2_QUP6_BCR 11 +-#define GCC_PCIE_0_BCR 12 +-#define GCC_PDM_BCR 13 +-#define GCC_SDCC2_BCR 14 +-#define GCC_SDCC4_BCR 15 +-#define GCC_TSIF_BCR 16 +-#define GCC_UFS_BCR 17 +-#define GCC_USB_30_BCR 18 +-#define GCC_SYSTEM_NOC_BCR 19 +-#define GCC_CONFIG_NOC_BCR 20 +-#define GCC_AHB2PHY_EAST_BCR 21 +-#define GCC_IMEM_BCR 22 +-#define GCC_PIMEM_BCR 23 +-#define GCC_MMSS_BCR 24 +-#define GCC_QDSS_BCR 25 +-#define GCC_WCSS_BCR 26 +-#define GCC_BLSP1_BCR 27 +-#define GCC_BLSP1_UART1_BCR 28 +-#define GCC_BLSP1_UART2_BCR 29 +-#define GCC_BLSP1_UART3_BCR 30 +-#define GCC_CM_PHY_REFGEN1_BCR 31 +-#define GCC_CM_PHY_REFGEN2_BCR 32 +-#define GCC_BLSP2_BCR 33 +-#define GCC_BLSP2_UART1_BCR 34 +-#define GCC_BLSP2_UART2_BCR 35 +-#define GCC_BLSP2_UART3_BCR 36 +-#define GCC_SRAM_SENSOR_BCR 37 +-#define GCC_PRNG_BCR 38 +-#define GCC_TSIF_0_RESET 39 +-#define GCC_TSIF_1_RESET 40 +-#define GCC_TCSR_BCR 41 +-#define GCC_BOOT_ROM_BCR 42 +-#define GCC_MSG_RAM_BCR 43 +-#define GCC_TLMM_BCR 44 +-#define GCC_MPM_BCR 45 +-#define GCC_SEC_CTRL_BCR 46 +-#define GCC_SPMI_BCR 47 +-#define GCC_SPDM_BCR 48 +-#define GCC_CE1_BCR 49 +-#define GCC_BIMC_BCR 50 +-#define GCC_SNOC_BUS_TIMEOUT0_BCR 51 +-#define GCC_SNOC_BUS_TIMEOUT1_BCR 52 +-#define GCC_SNOC_BUS_TIMEOUT3_BCR 53 +-#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 54 +-#define GCC_PNOC_BUS_TIMEOUT0_BCR 55 +-#define GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR 56 +-#define GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR 57 +-#define GCC_CNOC_BUS_TIMEOUT0_BCR 58 +-#define GCC_CNOC_BUS_TIMEOUT1_BCR 59 +-#define GCC_CNOC_BUS_TIMEOUT2_BCR 60 +-#define GCC_CNOC_BUS_TIMEOUT3_BCR 61 +-#define GCC_CNOC_BUS_TIMEOUT4_BCR 62 +-#define GCC_CNOC_BUS_TIMEOUT5_BCR 63 +-#define GCC_CNOC_BUS_TIMEOUT6_BCR 64 +-#define GCC_CNOC_BUS_TIMEOUT7_BCR 65 +-#define GCC_APB2JTAG_BCR 66 +-#define GCC_RBCPR_CX_BCR 67 +-#define GCC_RBCPR_MX_BCR 68 +-#define GCC_USB3_PHY_BCR 69 +-#define GCC_USB3PHY_PHY_BCR 70 +-#define GCC_USB3_DP_PHY_BCR 71 +-#define GCC_SSC_BCR 72 +-#define GCC_SSC_RESET 73 +-#define GCC_USB_PHY_CFG_AHB2PHY_BCR 74 +-#define GCC_PCIE_0_LINK_DOWN_BCR 75 +-#define GCC_PCIE_0_PHY_BCR 76 +-#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 77 +-#define GCC_PCIE_PHY_BCR 78 +-#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 79 +-#define GCC_PCIE_PHY_CFG_AHB_BCR 80 +-#define GCC_PCIE_PHY_COM_BCR 81 +-#define GCC_GPU_BCR 82 +-#define GCC_SPSS_BCR 83 +-#define GCC_OBT_ODT_BCR 84 +-#define GCC_VS_BCR 85 +-#define GCC_MSS_VS_RESET 86 +-#define GCC_GPU_VS_RESET 87 +-#define GCC_APC0_VS_RESET 88 +-#define GCC_APC1_VS_RESET 89 +-#define GCC_CNOC_BUS_TIMEOUT8_BCR 90 +-#define GCC_CNOC_BUS_TIMEOUT9_BCR 91 +-#define GCC_CNOC_BUS_TIMEOUT10_BCR 92 +-#define GCC_CNOC_BUS_TIMEOUT11_BCR 93 +-#define GCC_CNOC_BUS_TIMEOUT12_BCR 94 +-#define GCC_CNOC_BUS_TIMEOUT13_BCR 95 +-#define GCC_CNOC_BUS_TIMEOUT14_BCR 96 +-#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 97 +-#define GCC_AGGRE1_NOC_BCR 98 +-#define GCC_AGGRE2_NOC_BCR 99 +-#define GCC_DCC_BCR 100 +-#define GCC_QREFS_VBG_CAL_BCR 101 +-#define GCC_IPA_BCR 102 +-#define GCC_GLM_BCR 103 +-#define GCC_SKL_BCR 104 +-#define GCC_MSMPU_BCR 105 +-#define GCC_QUSB2PHY_PRIM_BCR 106 +-#define GCC_QUSB2PHY_SEC_BCR 107 +-#define GCC_MSS_RESTART 108 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-qcs404.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-qcs404.h +deleted file mode 100644 +index bc3051543347..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-qcs404.h ++++ /dev/null +@@ -1,180 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2018, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H +-#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H +- +-#define GCC_APSS_AHB_CLK_SRC 0 +-#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC 1 +-#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC 2 +-#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 3 +-#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 4 +-#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 5 +-#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 6 +-#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 7 +-#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 8 +-#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 9 +-#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 10 +-#define GCC_BLSP1_UART0_APPS_CLK_SRC 11 +-#define GCC_BLSP1_UART1_APPS_CLK_SRC 12 +-#define GCC_BLSP1_UART2_APPS_CLK_SRC 13 +-#define GCC_BLSP1_UART3_APPS_CLK_SRC 14 +-#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC 15 +-#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC 16 +-#define GCC_BLSP2_UART0_APPS_CLK_SRC 17 +-#define GCC_BYTE0_CLK_SRC 18 +-#define GCC_EMAC_CLK_SRC 19 +-#define GCC_EMAC_PTP_CLK_SRC 20 +-#define GCC_ESC0_CLK_SRC 21 +-#define GCC_APSS_AHB_CLK 22 +-#define GCC_APSS_AXI_CLK 23 +-#define GCC_BIMC_APSS_AXI_CLK 24 +-#define GCC_BIMC_GFX_CLK 25 +-#define GCC_BIMC_MDSS_CLK 26 +-#define GCC_BLSP1_AHB_CLK 27 +-#define GCC_BLSP1_QUP0_I2C_APPS_CLK 28 +-#define GCC_BLSP1_QUP0_SPI_APPS_CLK 29 +-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 30 +-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 31 +-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 32 +-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 33 +-#define GCC_BLSP1_QUP3_I2C_APPS_CLK 34 +-#define GCC_BLSP1_QUP3_SPI_APPS_CLK 35 +-#define GCC_BLSP1_QUP4_I2C_APPS_CLK 36 +-#define GCC_BLSP1_QUP4_SPI_APPS_CLK 37 +-#define GCC_BLSP1_UART0_APPS_CLK 38 +-#define GCC_BLSP1_UART1_APPS_CLK 39 +-#define GCC_BLSP1_UART2_APPS_CLK 40 +-#define GCC_BLSP1_UART3_APPS_CLK 41 +-#define GCC_BLSP2_AHB_CLK 42 +-#define GCC_BLSP2_QUP0_I2C_APPS_CLK 43 +-#define GCC_BLSP2_QUP0_SPI_APPS_CLK 44 +-#define GCC_BLSP2_UART0_APPS_CLK 45 +-#define GCC_BOOT_ROM_AHB_CLK 46 +-#define GCC_DCC_CLK 47 +-#define GCC_GENI_IR_H_CLK 48 +-#define GCC_ETH_AXI_CLK 49 +-#define GCC_ETH_PTP_CLK 50 +-#define GCC_ETH_RGMII_CLK 51 +-#define GCC_ETH_SLAVE_AHB_CLK 52 +-#define GCC_GENI_IR_S_CLK 53 +-#define GCC_GP1_CLK 54 +-#define GCC_GP2_CLK 55 +-#define GCC_GP3_CLK 56 +-#define GCC_MDSS_AHB_CLK 57 +-#define GCC_MDSS_AXI_CLK 58 +-#define GCC_MDSS_BYTE0_CLK 59 +-#define GCC_MDSS_ESC0_CLK 60 +-#define GCC_MDSS_HDMI_APP_CLK 61 +-#define GCC_MDSS_HDMI_PCLK_CLK 62 +-#define GCC_MDSS_MDP_CLK 63 +-#define GCC_MDSS_PCLK0_CLK 64 +-#define GCC_MDSS_VSYNC_CLK 65 +-#define GCC_OXILI_AHB_CLK 66 +-#define GCC_OXILI_GFX3D_CLK 67 +-#define GCC_PCIE_0_AUX_CLK 68 +-#define GCC_PCIE_0_CFG_AHB_CLK 69 +-#define GCC_PCIE_0_MSTR_AXI_CLK 70 +-#define GCC_PCIE_0_PIPE_CLK 71 +-#define GCC_PCIE_0_SLV_AXI_CLK 72 +-#define GCC_PCNOC_USB2_CLK 73 +-#define GCC_PCNOC_USB3_CLK 74 +-#define GCC_PDM2_CLK 75 +-#define GCC_PDM_AHB_CLK 76 +-#define GCC_VSYNC_CLK_SRC 77 +-#define GCC_PRNG_AHB_CLK 78 +-#define GCC_PWM0_XO512_CLK 79 +-#define GCC_PWM1_XO512_CLK 80 +-#define GCC_PWM2_XO512_CLK 81 +-#define GCC_SDCC1_AHB_CLK 82 +-#define GCC_SDCC1_APPS_CLK 83 +-#define GCC_SDCC1_ICE_CORE_CLK 84 +-#define GCC_SDCC2_AHB_CLK 85 +-#define GCC_SDCC2_APPS_CLK 86 +-#define GCC_SYS_NOC_USB3_CLK 87 +-#define GCC_USB20_MOCK_UTMI_CLK 88 +-#define GCC_USB2A_PHY_SLEEP_CLK 89 +-#define GCC_USB30_MASTER_CLK 90 +-#define GCC_USB30_MOCK_UTMI_CLK 91 +-#define GCC_USB30_SLEEP_CLK 92 +-#define GCC_USB3_PHY_AUX_CLK 93 +-#define GCC_USB3_PHY_PIPE_CLK 94 +-#define GCC_USB_HS_PHY_CFG_AHB_CLK 95 +-#define GCC_USB_HS_SYSTEM_CLK 96 +-#define GCC_GFX3D_CLK_SRC 97 +-#define GCC_GP1_CLK_SRC 98 +-#define GCC_GP2_CLK_SRC 99 +-#define GCC_GP3_CLK_SRC 100 +-#define GCC_GPLL0_OUT_MAIN 101 +-#define GCC_GPLL1_OUT_MAIN 102 +-#define GCC_GPLL3_OUT_MAIN 103 +-#define GCC_GPLL4_OUT_MAIN 104 +-#define GCC_HDMI_APP_CLK_SRC 105 +-#define GCC_HDMI_PCLK_CLK_SRC 106 +-#define GCC_MDP_CLK_SRC 107 +-#define GCC_PCIE_0_AUX_CLK_SRC 108 +-#define GCC_PCIE_0_PIPE_CLK_SRC 109 +-#define GCC_PCLK0_CLK_SRC 110 +-#define GCC_PDM2_CLK_SRC 111 +-#define GCC_SDCC1_APPS_CLK_SRC 112 +-#define GCC_SDCC1_ICE_CORE_CLK_SRC 113 +-#define GCC_SDCC2_APPS_CLK_SRC 114 +-#define GCC_USB20_MOCK_UTMI_CLK_SRC 115 +-#define GCC_USB30_MASTER_CLK_SRC 116 +-#define GCC_USB30_MOCK_UTMI_CLK_SRC 117 +-#define GCC_USB3_PHY_AUX_CLK_SRC 118 +-#define GCC_USB_HS_SYSTEM_CLK_SRC 119 +-#define GCC_GPLL0_AO_CLK_SRC 120 +-#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 122 +-#define GCC_GPLL0_AO_OUT_MAIN 123 +-#define GCC_GPLL0_SLEEP_CLK_SRC 124 +-#define GCC_GPLL6 125 +-#define GCC_GPLL6_OUT_AUX 126 +-#define GCC_MDSS_MDP_VOTE_CLK 127 +-#define GCC_MDSS_ROTATOR_VOTE_CLK 128 +-#define GCC_BIMC_GPU_CLK 129 +-#define GCC_GTCU_AHB_CLK 130 +-#define GCC_GFX_TCU_CLK 131 +-#define GCC_GFX_TBU_CLK 132 +-#define GCC_SMMU_CFG_CLK 133 +-#define GCC_APSS_TCU_CLK 134 +-#define GCC_CRYPTO_AHB_CLK 135 +-#define GCC_CRYPTO_AXI_CLK 136 +-#define GCC_CRYPTO_CLK 137 +-#define GCC_MDP_TBU_CLK 138 +-#define GCC_QDSS_DAP_CLK 139 +-#define GCC_DCC_XO_CLK 140 +-#define GCC_WCSS_Q6_AHB_CLK 141 +-#define GCC_WCSS_Q6_AXIM_CLK 142 +-#define GCC_CDSP_CFG_AHB_CLK 143 +-#define GCC_BIMC_CDSP_CLK 144 +-#define GCC_CDSP_TBU_CLK 145 +-#define GCC_CDSP_BIMC_CLK_SRC 146 +- +-#define GCC_GENI_IR_BCR 0 +-#define GCC_USB_HS_BCR 1 +-#define GCC_USB2_HS_PHY_ONLY_BCR 2 +-#define GCC_QUSB2_PHY_BCR 3 +-#define GCC_USB_HS_PHY_CFG_AHB_BCR 4 +-#define GCC_USB2A_PHY_BCR 5 +-#define GCC_USB3_PHY_BCR 6 +-#define GCC_USB_30_BCR 7 +-#define GCC_USB3PHY_PHY_BCR 8 +-#define GCC_PCIE_0_BCR 9 +-#define GCC_PCIE_0_PHY_BCR 10 +-#define GCC_PCIE_0_LINK_DOWN_BCR 11 +-#define GCC_PCIEPHY_0_PHY_BCR 12 +-#define GCC_EMAC_BCR 13 +-#define GCC_CDSP_RESTART 14 +-#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 15 +-#define GCC_PCIE_0_AHB_ARES 16 +-#define GCC_PCIE_0_AXI_SLAVE_ARES 17 +-#define GCC_PCIE_0_AXI_MASTER_ARES 18 +-#define GCC_PCIE_0_CORE_STICKY_ARES 19 +-#define GCC_PCIE_0_SLEEP_ARES 20 +-#define GCC_PCIE_0_PIPE_ARES 21 +-#define GCC_WDSP_RESTART 22 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sc7180.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sc7180.h +deleted file mode 100644 +index bdf43adc7897..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sc7180.h ++++ /dev/null +@@ -1,162 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H +-#define _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H +- +-/* GCC clocks */ +-#define GCC_GPLL0_MAIN_DIV_CDIV 0 +-#define GPLL0 1 +-#define GPLL0_OUT_EVEN 2 +-#define GPLL1 3 +-#define GPLL4 4 +-#define GPLL6 5 +-#define GPLL7 6 +-#define GCC_AGGRE_UFS_PHY_AXI_CLK 7 +-#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8 +-#define GCC_BOOT_ROM_AHB_CLK 9 +-#define GCC_CAMERA_AHB_CLK 10 +-#define GCC_CAMERA_HF_AXI_CLK 11 +-#define GCC_CAMERA_THROTTLE_HF_AXI_CLK 12 +-#define GCC_CAMERA_XO_CLK 13 +-#define GCC_CE1_AHB_CLK 14 +-#define GCC_CE1_AXI_CLK 15 +-#define GCC_CE1_CLK 16 +-#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17 +-#define GCC_CPUSS_AHB_CLK 18 +-#define GCC_CPUSS_AHB_CLK_SRC 19 +-#define GCC_CPUSS_GNOC_CLK 20 +-#define GCC_CPUSS_RBCPR_CLK 21 +-#define GCC_DDRSS_GPU_AXI_CLK 22 +-#define GCC_DISP_AHB_CLK 23 +-#define GCC_DISP_GPLL0_CLK_SRC 24 +-#define GCC_DISP_GPLL0_DIV_CLK_SRC 25 +-#define GCC_DISP_HF_AXI_CLK 26 +-#define GCC_DISP_THROTTLE_HF_AXI_CLK 27 +-#define GCC_DISP_XO_CLK 28 +-#define GCC_GP1_CLK 29 +-#define GCC_GP1_CLK_SRC 30 +-#define GCC_GP2_CLK 31 +-#define GCC_GP2_CLK_SRC 32 +-#define GCC_GP3_CLK 33 +-#define GCC_GP3_CLK_SRC 34 +-#define GCC_GPU_CFG_AHB_CLK 35 +-#define GCC_GPU_GPLL0_CLK_SRC 36 +-#define GCC_GPU_GPLL0_DIV_CLK_SRC 37 +-#define GCC_GPU_MEMNOC_GFX_CLK 38 +-#define GCC_GPU_SNOC_DVM_GFX_CLK 39 +-#define GCC_NPU_AXI_CLK 40 +-#define GCC_NPU_BWMON_AXI_CLK 41 +-#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 42 +-#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 43 +-#define GCC_NPU_CFG_AHB_CLK 44 +-#define GCC_NPU_DMA_CLK 45 +-#define GCC_NPU_GPLL0_CLK_SRC 46 +-#define GCC_NPU_GPLL0_DIV_CLK_SRC 47 +-#define GCC_PDM2_CLK 48 +-#define GCC_PDM2_CLK_SRC 49 +-#define GCC_PDM_AHB_CLK 50 +-#define GCC_PDM_XO4_CLK 51 +-#define GCC_PRNG_AHB_CLK 52 +-#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 53 +-#define GCC_QSPI_CORE_CLK 54 +-#define GCC_QSPI_CORE_CLK_SRC 55 +-#define GCC_QUPV3_WRAP0_CORE_2X_CLK 56 +-#define GCC_QUPV3_WRAP0_CORE_CLK 57 +-#define GCC_QUPV3_WRAP0_S0_CLK 58 +-#define GCC_QUPV3_WRAP0_S0_CLK_SRC 59 +-#define GCC_QUPV3_WRAP0_S1_CLK 60 +-#define GCC_QUPV3_WRAP0_S1_CLK_SRC 61 +-#define GCC_QUPV3_WRAP0_S2_CLK 62 +-#define GCC_QUPV3_WRAP0_S2_CLK_SRC 63 +-#define GCC_QUPV3_WRAP0_S3_CLK 64 +-#define GCC_QUPV3_WRAP0_S3_CLK_SRC 65 +-#define GCC_QUPV3_WRAP0_S4_CLK 66 +-#define GCC_QUPV3_WRAP0_S4_CLK_SRC 67 +-#define GCC_QUPV3_WRAP0_S5_CLK 68 +-#define GCC_QUPV3_WRAP0_S5_CLK_SRC 69 +-#define GCC_QUPV3_WRAP1_CORE_2X_CLK 70 +-#define GCC_QUPV3_WRAP1_CORE_CLK 71 +-#define GCC_QUPV3_WRAP1_S0_CLK 72 +-#define GCC_QUPV3_WRAP1_S0_CLK_SRC 73 +-#define GCC_QUPV3_WRAP1_S1_CLK 74 +-#define GCC_QUPV3_WRAP1_S1_CLK_SRC 75 +-#define GCC_QUPV3_WRAP1_S2_CLK 76 +-#define GCC_QUPV3_WRAP1_S2_CLK_SRC 77 +-#define GCC_QUPV3_WRAP1_S3_CLK 78 +-#define GCC_QUPV3_WRAP1_S3_CLK_SRC 79 +-#define GCC_QUPV3_WRAP1_S4_CLK 80 +-#define GCC_QUPV3_WRAP1_S4_CLK_SRC 81 +-#define GCC_QUPV3_WRAP1_S5_CLK 82 +-#define GCC_QUPV3_WRAP1_S5_CLK_SRC 83 +-#define GCC_QUPV3_WRAP_0_M_AHB_CLK 84 +-#define GCC_QUPV3_WRAP_0_S_AHB_CLK 85 +-#define GCC_QUPV3_WRAP_1_M_AHB_CLK 86 +-#define GCC_QUPV3_WRAP_1_S_AHB_CLK 87 +-#define GCC_SDCC1_AHB_CLK 88 +-#define GCC_SDCC1_APPS_CLK 89 +-#define GCC_SDCC1_APPS_CLK_SRC 90 +-#define GCC_SDCC1_ICE_CORE_CLK 91 +-#define GCC_SDCC1_ICE_CORE_CLK_SRC 92 +-#define GCC_SDCC2_AHB_CLK 93 +-#define GCC_SDCC2_APPS_CLK 94 +-#define GCC_SDCC2_APPS_CLK_SRC 95 +-#define GCC_SYS_NOC_CPUSS_AHB_CLK 96 +-#define GCC_UFS_MEM_CLKREF_CLK 97 +-#define GCC_UFS_PHY_AHB_CLK 98 +-#define GCC_UFS_PHY_AXI_CLK 99 +-#define GCC_UFS_PHY_AXI_CLK_SRC 100 +-#define GCC_UFS_PHY_ICE_CORE_CLK 101 +-#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102 +-#define GCC_UFS_PHY_PHY_AUX_CLK 103 +-#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104 +-#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105 +-#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 106 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK 107 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 108 +-#define GCC_USB30_PRIM_MASTER_CLK 109 +-#define GCC_USB30_PRIM_MASTER_CLK_SRC 110 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112 +-#define GCC_USB30_PRIM_SLEEP_CLK 113 +-#define GCC_USB3_PRIM_CLKREF_CLK 114 +-#define GCC_USB3_PRIM_PHY_AUX_CLK 115 +-#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116 +-#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117 +-#define GCC_USB3_PRIM_PHY_PIPE_CLK 118 +-#define GCC_USB_PHY_CFG_AHB2PHY_CLK 119 +-#define GCC_VIDEO_AHB_CLK 120 +-#define GCC_VIDEO_AXI_CLK 121 +-#define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122 +-#define GCC_VIDEO_THROTTLE_AXI_CLK 123 +-#define GCC_VIDEO_XO_CLK 124 +-#define GCC_MSS_CFG_AHB_CLK 125 +-#define GCC_MSS_MFAB_AXIS_CLK 126 +-#define GCC_MSS_NAV_AXI_CLK 127 +-#define GCC_MSS_Q6_MEMNOC_AXI_CLK 128 +-#define GCC_MSS_SNOC_AXI_CLK 129 +-#define GCC_SEC_CTRL_CLK_SRC 130 +-#define GCC_LPASS_CFG_NOC_SWAY_CLK 131 +- +-/* GCC resets */ +-#define GCC_QUSB2PHY_PRIM_BCR 0 +-#define GCC_QUSB2PHY_SEC_BCR 1 +-#define GCC_UFS_PHY_BCR 2 +-#define GCC_USB30_PRIM_BCR 3 +-#define GCC_USB3_DP_PHY_PRIM_BCR 4 +-#define GCC_USB3_DP_PHY_SEC_BCR 5 +-#define GCC_USB3_PHY_PRIM_BCR 6 +-#define GCC_USB3_PHY_SEC_BCR 7 +-#define GCC_USB3PHY_PHY_PRIM_BCR 8 +-#define GCC_USB3PHY_PHY_SEC_BCR 9 +-#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10 +- +-/* GCC GDSCRs */ +-#define UFS_PHY_GDSC 0 +-#define USB30_PRIM_GDSC 1 +-#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2 +-#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sc7280.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sc7280.h +deleted file mode 100644 +index 3d5724b79bff..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sc7280.h ++++ /dev/null +@@ -1,226 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +-/* +- * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7280_H +-#define _DT_BINDINGS_CLK_QCOM_GCC_SC7280_H +- +-/* GCC clocks */ +-#define GCC_GPLL0 0 +-#define GCC_GPLL0_OUT_EVEN 1 +-#define GCC_GPLL0_OUT_ODD 2 +-#define GCC_GPLL1 3 +-#define GCC_GPLL10 4 +-#define GCC_GPLL4 5 +-#define GCC_GPLL9 6 +-#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 7 +-#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 8 +-#define GCC_AGGRE_UFS_PHY_AXI_CLK 9 +-#define GCC_AGGRE_USB3_PRIM_AXI_CLK 10 +-#define GCC_CAMERA_AHB_CLK 11 +-#define GCC_CAMERA_HF_AXI_CLK 12 +-#define GCC_CAMERA_SF_AXI_CLK 13 +-#define GCC_CAMERA_XO_CLK 14 +-#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 15 +-#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 16 +-#define GCC_CPUSS_AHB_CLK 17 +-#define GCC_CPUSS_AHB_CLK_SRC 18 +-#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 19 +-#define GCC_DDRSS_GPU_AXI_CLK 20 +-#define GCC_DDRSS_PCIE_SF_CLK 21 +-#define GCC_DISP_AHB_CLK 22 +-#define GCC_DISP_GPLL0_CLK_SRC 23 +-#define GCC_DISP_HF_AXI_CLK 24 +-#define GCC_DISP_SF_AXI_CLK 25 +-#define GCC_DISP_XO_CLK 26 +-#define GCC_GP1_CLK 27 +-#define GCC_GP1_CLK_SRC 28 +-#define GCC_GP2_CLK 29 +-#define GCC_GP2_CLK_SRC 30 +-#define GCC_GP3_CLK 31 +-#define GCC_GP3_CLK_SRC 32 +-#define GCC_GPU_CFG_AHB_CLK 33 +-#define GCC_GPU_GPLL0_CLK_SRC 34 +-#define GCC_GPU_GPLL0_DIV_CLK_SRC 35 +-#define GCC_GPU_IREF_EN 36 +-#define GCC_GPU_MEMNOC_GFX_CLK 37 +-#define GCC_GPU_SNOC_DVM_GFX_CLK 38 +-#define GCC_PCIE0_PHY_RCHNG_CLK 39 +-#define GCC_PCIE1_PHY_RCHNG_CLK 40 +-#define GCC_PCIE_0_AUX_CLK 41 +-#define GCC_PCIE_0_AUX_CLK_SRC 42 +-#define GCC_PCIE_0_CFG_AHB_CLK 43 +-#define GCC_PCIE_0_MSTR_AXI_CLK 44 +-#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 45 +-#define GCC_PCIE_0_PIPE_CLK 46 +-#define GCC_PCIE_0_PIPE_CLK_SRC 47 +-#define GCC_PCIE_0_SLV_AXI_CLK 48 +-#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 49 +-#define GCC_PCIE_1_AUX_CLK 50 +-#define GCC_PCIE_1_AUX_CLK_SRC 51 +-#define GCC_PCIE_1_CFG_AHB_CLK 52 +-#define GCC_PCIE_1_MSTR_AXI_CLK 53 +-#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 54 +-#define GCC_PCIE_1_PIPE_CLK 55 +-#define GCC_PCIE_1_PIPE_CLK_SRC 56 +-#define GCC_PCIE_1_SLV_AXI_CLK 57 +-#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 58 +-#define GCC_PCIE_THROTTLE_CORE_CLK 59 +-#define GCC_PDM2_CLK 60 +-#define GCC_PDM2_CLK_SRC 61 +-#define GCC_PDM_AHB_CLK 62 +-#define GCC_PDM_XO4_CLK 63 +-#define GCC_QMIP_CAMERA_NRT_AHB_CLK 64 +-#define GCC_QMIP_CAMERA_RT_AHB_CLK 65 +-#define GCC_QMIP_DISP_AHB_CLK 66 +-#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 67 +-#define GCC_QUPV3_WRAP0_CORE_2X_CLK 68 +-#define GCC_QUPV3_WRAP0_CORE_CLK 69 +-#define GCC_QUPV3_WRAP0_S0_CLK 70 +-#define GCC_QUPV3_WRAP0_S0_CLK_SRC 71 +-#define GCC_QUPV3_WRAP0_S1_CLK 72 +-#define GCC_QUPV3_WRAP0_S1_CLK_SRC 73 +-#define GCC_QUPV3_WRAP0_S2_CLK 74 +-#define GCC_QUPV3_WRAP0_S2_CLK_SRC 75 +-#define GCC_QUPV3_WRAP0_S3_CLK 76 +-#define GCC_QUPV3_WRAP0_S3_CLK_SRC 77 +-#define GCC_QUPV3_WRAP0_S4_CLK 78 +-#define GCC_QUPV3_WRAP0_S4_CLK_SRC 79 +-#define GCC_QUPV3_WRAP0_S5_CLK 80 +-#define GCC_QUPV3_WRAP0_S5_CLK_SRC 81 +-#define GCC_QUPV3_WRAP0_S6_CLK 82 +-#define GCC_QUPV3_WRAP0_S6_CLK_SRC 83 +-#define GCC_QUPV3_WRAP0_S7_CLK 84 +-#define GCC_QUPV3_WRAP0_S7_CLK_SRC 85 +-#define GCC_QUPV3_WRAP1_CORE_2X_CLK 86 +-#define GCC_QUPV3_WRAP1_CORE_CLK 87 +-#define GCC_QUPV3_WRAP1_S0_CLK 88 +-#define GCC_QUPV3_WRAP1_S0_CLK_SRC 89 +-#define GCC_QUPV3_WRAP1_S1_CLK 90 +-#define GCC_QUPV3_WRAP1_S1_CLK_SRC 91 +-#define GCC_QUPV3_WRAP1_S2_CLK 92 +-#define GCC_QUPV3_WRAP1_S2_CLK_SRC 93 +-#define GCC_QUPV3_WRAP1_S3_CLK 94 +-#define GCC_QUPV3_WRAP1_S3_CLK_SRC 95 +-#define GCC_QUPV3_WRAP1_S4_CLK 96 +-#define GCC_QUPV3_WRAP1_S4_CLK_SRC 97 +-#define GCC_QUPV3_WRAP1_S5_CLK 98 +-#define GCC_QUPV3_WRAP1_S5_CLK_SRC 99 +-#define GCC_QUPV3_WRAP1_S6_CLK 100 +-#define GCC_QUPV3_WRAP1_S6_CLK_SRC 101 +-#define GCC_QUPV3_WRAP1_S7_CLK 102 +-#define GCC_QUPV3_WRAP1_S7_CLK_SRC 103 +-#define GCC_QUPV3_WRAP_0_M_AHB_CLK 104 +-#define GCC_QUPV3_WRAP_0_S_AHB_CLK 105 +-#define GCC_QUPV3_WRAP_1_M_AHB_CLK 106 +-#define GCC_QUPV3_WRAP_1_S_AHB_CLK 107 +-#define GCC_SDCC1_AHB_CLK 108 +-#define GCC_SDCC1_APPS_CLK 109 +-#define GCC_SDCC1_APPS_CLK_SRC 110 +-#define GCC_SDCC1_ICE_CORE_CLK 111 +-#define GCC_SDCC1_ICE_CORE_CLK_SRC 112 +-#define GCC_SDCC2_AHB_CLK 113 +-#define GCC_SDCC2_APPS_CLK 114 +-#define GCC_SDCC2_APPS_CLK_SRC 115 +-#define GCC_SDCC4_AHB_CLK 116 +-#define GCC_SDCC4_APPS_CLK 117 +-#define GCC_SDCC4_APPS_CLK_SRC 118 +-#define GCC_SYS_NOC_CPUSS_AHB_CLK 119 +-#define GCC_THROTTLE_PCIE_AHB_CLK 120 +-#define GCC_TITAN_NRT_THROTTLE_CORE_CLK 121 +-#define GCC_TITAN_RT_THROTTLE_CORE_CLK 122 +-#define GCC_UFS_1_CLKREF_EN 123 +-#define GCC_UFS_PHY_AHB_CLK 124 +-#define GCC_UFS_PHY_AXI_CLK 125 +-#define GCC_UFS_PHY_AXI_CLK_SRC 126 +-#define GCC_UFS_PHY_ICE_CORE_CLK 127 +-#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 128 +-#define GCC_UFS_PHY_PHY_AUX_CLK 129 +-#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 130 +-#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 131 +-#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 132 +-#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 133 +-#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 134 +-#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 135 +-#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 136 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK 137 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 138 +-#define GCC_USB30_PRIM_MASTER_CLK 139 +-#define GCC_USB30_PRIM_MASTER_CLK_SRC 140 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK 141 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 142 +-#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 143 +-#define GCC_USB30_PRIM_SLEEP_CLK 144 +-#define GCC_USB30_SEC_MASTER_CLK 145 +-#define GCC_USB30_SEC_MASTER_CLK_SRC 146 +-#define GCC_USB30_SEC_MOCK_UTMI_CLK 147 +-#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 148 +-#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 149 +-#define GCC_USB30_SEC_SLEEP_CLK 150 +-#define GCC_USB3_PRIM_PHY_AUX_CLK 151 +-#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 152 +-#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 153 +-#define GCC_USB3_PRIM_PHY_PIPE_CLK 154 +-#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 155 +-#define GCC_USB3_SEC_PHY_AUX_CLK 156 +-#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 157 +-#define GCC_USB3_SEC_PHY_COM_AUX_CLK 158 +-#define GCC_USB3_SEC_PHY_PIPE_CLK 159 +-#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 160 +-#define GCC_VIDEO_AHB_CLK 161 +-#define GCC_VIDEO_AXI0_CLK 162 +-#define GCC_VIDEO_MVP_THROTTLE_CORE_CLK 163 +-#define GCC_VIDEO_XO_CLK 164 +-#define GCC_GPLL0_MAIN_DIV_CDIV 165 +-#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 166 +-#define GCC_QSPI_CORE_CLK 167 +-#define GCC_QSPI_CORE_CLK_SRC 168 +-#define GCC_CFG_NOC_LPASS_CLK 169 +-#define GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC 170 +-#define GCC_MSS_CFG_AHB_CLK 171 +-#define GCC_MSS_OFFLINE_AXI_CLK 172 +-#define GCC_MSS_SNOC_AXI_CLK 173 +-#define GCC_MSS_Q6_MEMNOC_AXI_CLK 174 +-#define GCC_MSS_Q6SS_BOOT_CLK_SRC 175 +-#define GCC_AGGRE_USB3_SEC_AXI_CLK 176 +-#define GCC_AGGRE_NOC_PCIE_TBU_CLK 177 +-#define GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK 178 +-#define GCC_PCIE_CLKREF_EN 179 +-#define GCC_WPSS_AHB_CLK 180 +-#define GCC_WPSS_AHB_BDG_MST_CLK 181 +-#define GCC_WPSS_RSCP_CLK 182 +-#define GCC_EDP_CLKREF_EN 183 +-#define GCC_SEC_CTRL_CLK_SRC 184 +- +-/* GCC power domains */ +-#define GCC_PCIE_0_GDSC 0 +-#define GCC_PCIE_1_GDSC 1 +-#define GCC_UFS_PHY_GDSC 2 +-#define GCC_USB30_PRIM_GDSC 3 +-#define GCC_USB30_SEC_GDSC 4 +-#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 5 +-#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 6 +-#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 7 +-#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 8 +-#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 9 +- +-/* GCC resets */ +-#define GCC_PCIE_0_BCR 0 +-#define GCC_PCIE_0_PHY_BCR 1 +-#define GCC_PCIE_1_BCR 2 +-#define GCC_PCIE_1_PHY_BCR 3 +-#define GCC_QUSB2PHY_PRIM_BCR 4 +-#define GCC_QUSB2PHY_SEC_BCR 5 +-#define GCC_SDCC1_BCR 6 +-#define GCC_SDCC2_BCR 7 +-#define GCC_SDCC4_BCR 8 +-#define GCC_UFS_PHY_BCR 9 +-#define GCC_USB30_PRIM_BCR 10 +-#define GCC_USB30_SEC_BCR 11 +-#define GCC_USB3_DP_PHY_PRIM_BCR 12 +-#define GCC_USB3_PHY_PRIM_BCR 13 +-#define GCC_USB3PHY_PHY_PRIM_BCR 14 +-#define GCC_USB_PHY_CFG_AHB2PHY_BCR 15 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sc8180x.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sc8180x.h +deleted file mode 100644 +index e893415ae13d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sc8180x.h ++++ /dev/null +@@ -1,309 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +-/* +- * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. +- * Copyright (c) 2021, Linaro Ltd. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC8180X_H +-#define _DT_BINDINGS_CLK_QCOM_GCC_SC8180X_H +- +-#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 +-#define GCC_AGGRE_UFS_CARD_AXI_CLK 1 +-#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 2 +-#define GCC_AGGRE_UFS_PHY_AXI_CLK 3 +-#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 4 +-#define GCC_AGGRE_USB3_MP_AXI_CLK 5 +-#define GCC_AGGRE_USB3_PRIM_AXI_CLK 6 +-#define GCC_AGGRE_USB3_SEC_AXI_CLK 7 +-#define GCC_BOOT_ROM_AHB_CLK 8 +-#define GCC_CAMERA_HF_AXI_CLK 9 +-#define GCC_CAMERA_SF_AXI_CLK 10 +-#define GCC_CFG_NOC_USB3_MP_AXI_CLK 11 +-#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 +-#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 +-#define GCC_CPUSS_AHB_CLK 14 +-#define GCC_CPUSS_AHB_CLK_SRC 15 +-#define GCC_CPUSS_RBCPR_CLK 16 +-#define GCC_DDRSS_GPU_AXI_CLK 17 +-#define GCC_DISP_HF_AXI_CLK 18 +-#define GCC_DISP_SF_AXI_CLK 19 +-#define GCC_EMAC_AXI_CLK 20 +-#define GCC_EMAC_PTP_CLK 21 +-#define GCC_EMAC_PTP_CLK_SRC 22 +-#define GCC_EMAC_RGMII_CLK 23 +-#define GCC_EMAC_RGMII_CLK_SRC 24 +-#define GCC_EMAC_SLV_AHB_CLK 25 +-#define GCC_GP1_CLK 26 +-#define GCC_GP1_CLK_SRC 27 +-#define GCC_GP2_CLK 28 +-#define GCC_GP2_CLK_SRC 29 +-#define GCC_GP3_CLK 30 +-#define GCC_GP3_CLK_SRC 31 +-#define GCC_GP4_CLK 32 +-#define GCC_GP4_CLK_SRC 33 +-#define GCC_GP5_CLK 34 +-#define GCC_GP5_CLK_SRC 35 +-#define GCC_GPU_GPLL0_CLK_SRC 36 +-#define GCC_GPU_GPLL0_DIV_CLK_SRC 37 +-#define GCC_GPU_MEMNOC_GFX_CLK 38 +-#define GCC_GPU_SNOC_DVM_GFX_CLK 39 +-#define GCC_NPU_AT_CLK 40 +-#define GCC_NPU_AXI_CLK 41 +-#define GCC_NPU_AXI_CLK_SRC 42 +-#define GCC_NPU_GPLL0_CLK_SRC 43 +-#define GCC_NPU_GPLL0_DIV_CLK_SRC 44 +-#define GCC_NPU_TRIG_CLK 45 +-#define GCC_PCIE0_PHY_REFGEN_CLK 46 +-#define GCC_PCIE1_PHY_REFGEN_CLK 47 +-#define GCC_PCIE2_PHY_REFGEN_CLK 48 +-#define GCC_PCIE3_PHY_REFGEN_CLK 49 +-#define GCC_PCIE_0_AUX_CLK 50 +-#define GCC_PCIE_0_AUX_CLK_SRC 51 +-#define GCC_PCIE_0_CFG_AHB_CLK 52 +-#define GCC_PCIE_0_MSTR_AXI_CLK 53 +-#define GCC_PCIE_0_PIPE_CLK 54 +-#define GCC_PCIE_0_SLV_AXI_CLK 55 +-#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 56 +-#define GCC_PCIE_1_AUX_CLK 57 +-#define GCC_PCIE_1_AUX_CLK_SRC 58 +-#define GCC_PCIE_1_CFG_AHB_CLK 59 +-#define GCC_PCIE_1_MSTR_AXI_CLK 60 +-#define GCC_PCIE_1_PIPE_CLK 61 +-#define GCC_PCIE_1_SLV_AXI_CLK 62 +-#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 63 +-#define GCC_PCIE_2_AUX_CLK 64 +-#define GCC_PCIE_2_AUX_CLK_SRC 65 +-#define GCC_PCIE_2_CFG_AHB_CLK 66 +-#define GCC_PCIE_2_MSTR_AXI_CLK 67 +-#define GCC_PCIE_2_PIPE_CLK 68 +-#define GCC_PCIE_2_SLV_AXI_CLK 69 +-#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 70 +-#define GCC_PCIE_3_AUX_CLK 71 +-#define GCC_PCIE_3_AUX_CLK_SRC 72 +-#define GCC_PCIE_3_CFG_AHB_CLK 73 +-#define GCC_PCIE_3_MSTR_AXI_CLK 74 +-#define GCC_PCIE_3_PIPE_CLK 75 +-#define GCC_PCIE_3_SLV_AXI_CLK 76 +-#define GCC_PCIE_3_SLV_Q2A_AXI_CLK 77 +-#define GCC_PCIE_PHY_AUX_CLK 78 +-#define GCC_PCIE_PHY_REFGEN_CLK_SRC 79 +-#define GCC_PDM2_CLK 80 +-#define GCC_PDM2_CLK_SRC 81 +-#define GCC_PDM_AHB_CLK 82 +-#define GCC_PDM_XO4_CLK 83 +-#define GCC_PRNG_AHB_CLK 84 +-#define GCC_QMIP_CAMERA_NRT_AHB_CLK 85 +-#define GCC_QMIP_CAMERA_RT_AHB_CLK 86 +-#define GCC_QMIP_DISP_AHB_CLK 87 +-#define GCC_QMIP_VIDEO_CVP_AHB_CLK 88 +-#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 89 +-#define GCC_QSPI_1_CNOC_PERIPH_AHB_CLK 90 +-#define GCC_QSPI_1_CORE_CLK 91 +-#define GCC_QSPI_1_CORE_CLK_SRC 92 +-#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 93 +-#define GCC_QSPI_CORE_CLK 94 +-#define GCC_QSPI_CORE_CLK_SRC 95 +-#define GCC_QUPV3_WRAP0_S0_CLK 96 +-#define GCC_QUPV3_WRAP0_S0_CLK_SRC 97 +-#define GCC_QUPV3_WRAP0_S1_CLK 98 +-#define GCC_QUPV3_WRAP0_S1_CLK_SRC 99 +-#define GCC_QUPV3_WRAP0_S2_CLK 100 +-#define GCC_QUPV3_WRAP0_S2_CLK_SRC 101 +-#define GCC_QUPV3_WRAP0_S3_CLK 102 +-#define GCC_QUPV3_WRAP0_S3_CLK_SRC 103 +-#define GCC_QUPV3_WRAP0_S4_CLK 104 +-#define GCC_QUPV3_WRAP0_S4_CLK_SRC 105 +-#define GCC_QUPV3_WRAP0_S5_CLK 106 +-#define GCC_QUPV3_WRAP0_S5_CLK_SRC 107 +-#define GCC_QUPV3_WRAP0_S6_CLK 108 +-#define GCC_QUPV3_WRAP0_S6_CLK_SRC 109 +-#define GCC_QUPV3_WRAP0_S7_CLK 110 +-#define GCC_QUPV3_WRAP0_S7_CLK_SRC 111 +-#define GCC_QUPV3_WRAP1_S0_CLK 112 +-#define GCC_QUPV3_WRAP1_S0_CLK_SRC 113 +-#define GCC_QUPV3_WRAP1_S1_CLK 114 +-#define GCC_QUPV3_WRAP1_S1_CLK_SRC 115 +-#define GCC_QUPV3_WRAP1_S2_CLK 116 +-#define GCC_QUPV3_WRAP1_S2_CLK_SRC 117 +-#define GCC_QUPV3_WRAP1_S3_CLK 118 +-#define GCC_QUPV3_WRAP1_S3_CLK_SRC 119 +-#define GCC_QUPV3_WRAP1_S4_CLK 120 +-#define GCC_QUPV3_WRAP1_S4_CLK_SRC 121 +-#define GCC_QUPV3_WRAP1_S5_CLK 122 +-#define GCC_QUPV3_WRAP1_S5_CLK_SRC 123 +-#define GCC_QUPV3_WRAP2_S0_CLK 124 +-#define GCC_QUPV3_WRAP2_S0_CLK_SRC 125 +-#define GCC_QUPV3_WRAP2_S1_CLK 126 +-#define GCC_QUPV3_WRAP2_S1_CLK_SRC 127 +-#define GCC_QUPV3_WRAP2_S2_CLK 128 +-#define GCC_QUPV3_WRAP2_S2_CLK_SRC 129 +-#define GCC_QUPV3_WRAP2_S3_CLK 130 +-#define GCC_QUPV3_WRAP2_S3_CLK_SRC 131 +-#define GCC_QUPV3_WRAP2_S4_CLK 132 +-#define GCC_QUPV3_WRAP2_S4_CLK_SRC 133 +-#define GCC_QUPV3_WRAP2_S5_CLK 134 +-#define GCC_QUPV3_WRAP2_S5_CLK_SRC 135 +-#define GCC_QUPV3_WRAP_0_M_AHB_CLK 136 +-#define GCC_QUPV3_WRAP_0_S_AHB_CLK 137 +-#define GCC_QUPV3_WRAP_1_M_AHB_CLK 138 +-#define GCC_QUPV3_WRAP_1_S_AHB_CLK 139 +-#define GCC_QUPV3_WRAP_2_M_AHB_CLK 140 +-#define GCC_QUPV3_WRAP_2_S_AHB_CLK 141 +-#define GCC_SDCC2_AHB_CLK 142 +-#define GCC_SDCC2_APPS_CLK 143 +-#define GCC_SDCC2_APPS_CLK_SRC 144 +-#define GCC_SDCC4_AHB_CLK 145 +-#define GCC_SDCC4_APPS_CLK 146 +-#define GCC_SDCC4_APPS_CLK_SRC 147 +-#define GCC_SYS_NOC_CPUSS_AHB_CLK 148 +-#define GCC_TSIF_AHB_CLK 149 +-#define GCC_TSIF_INACTIVITY_TIMERS_CLK 150 +-#define GCC_TSIF_REF_CLK 151 +-#define GCC_TSIF_REF_CLK_SRC 152 +-#define GCC_UFS_CARD_2_AHB_CLK 153 +-#define GCC_UFS_CARD_2_AXI_CLK 154 +-#define GCC_UFS_CARD_2_AXI_CLK_SRC 155 +-#define GCC_UFS_CARD_2_ICE_CORE_CLK 156 +-#define GCC_UFS_CARD_2_ICE_CORE_CLK_SRC 157 +-#define GCC_UFS_CARD_2_PHY_AUX_CLK 158 +-#define GCC_UFS_CARD_2_PHY_AUX_CLK_SRC 159 +-#define GCC_UFS_CARD_2_RX_SYMBOL_0_CLK 160 +-#define GCC_UFS_CARD_2_RX_SYMBOL_1_CLK 161 +-#define GCC_UFS_CARD_2_TX_SYMBOL_0_CLK 162 +-#define GCC_UFS_CARD_2_UNIPRO_CORE_CLK 163 +-#define GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC 164 +-#define GCC_UFS_CARD_AHB_CLK 165 +-#define GCC_UFS_CARD_AXI_CLK 166 +-#define GCC_UFS_CARD_AXI_CLK_SRC 167 +-#define GCC_UFS_CARD_AXI_HW_CTL_CLK 168 +-#define GCC_UFS_CARD_ICE_CORE_CLK 169 +-#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 170 +-#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 171 +-#define GCC_UFS_CARD_PHY_AUX_CLK 172 +-#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 173 +-#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 174 +-#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 175 +-#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 176 +-#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 177 +-#define GCC_UFS_CARD_UNIPRO_CORE_CLK 178 +-#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 179 +-#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 180 +-#define GCC_UFS_PHY_AHB_CLK 181 +-#define GCC_UFS_PHY_AXI_CLK 182 +-#define GCC_UFS_PHY_AXI_CLK_SRC 183 +-#define GCC_UFS_PHY_AXI_HW_CTL_CLK 184 +-#define GCC_UFS_PHY_ICE_CORE_CLK 185 +-#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 186 +-#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 187 +-#define GCC_UFS_PHY_PHY_AUX_CLK 188 +-#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 189 +-#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 190 +-#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 191 +-#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 192 +-#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 193 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK 194 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 195 +-#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 196 +-#define GCC_USB30_MP_MASTER_CLK 197 +-#define GCC_USB30_MP_MASTER_CLK_SRC 198 +-#define GCC_USB30_MP_MOCK_UTMI_CLK 199 +-#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 200 +-#define GCC_USB30_MP_SLEEP_CLK 201 +-#define GCC_USB30_PRIM_MASTER_CLK 202 +-#define GCC_USB30_PRIM_MASTER_CLK_SRC 203 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK 204 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 205 +-#define GCC_USB30_PRIM_SLEEP_CLK 206 +-#define GCC_USB30_SEC_MASTER_CLK 207 +-#define GCC_USB30_SEC_MASTER_CLK_SRC 208 +-#define GCC_USB30_SEC_MOCK_UTMI_CLK 209 +-#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 210 +-#define GCC_USB30_SEC_SLEEP_CLK 211 +-#define GCC_USB3_MP_PHY_AUX_CLK 212 +-#define GCC_USB3_MP_PHY_AUX_CLK_SRC 213 +-#define GCC_USB3_MP_PHY_COM_AUX_CLK 214 +-#define GCC_USB3_MP_PHY_PIPE_0_CLK 215 +-#define GCC_USB3_MP_PHY_PIPE_1_CLK 216 +-#define GCC_USB3_PRIM_PHY_AUX_CLK 217 +-#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 218 +-#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 219 +-#define GCC_USB3_PRIM_PHY_PIPE_CLK 220 +-#define GCC_USB3_SEC_PHY_AUX_CLK 221 +-#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 222 +-#define GCC_USB3_SEC_PHY_COM_AUX_CLK 223 +-#define GCC_USB3_SEC_PHY_PIPE_CLK 224 +-#define GCC_VIDEO_AXI0_CLK 225 +-#define GCC_VIDEO_AXI1_CLK 226 +-#define GCC_VIDEO_AXIC_CLK 227 +-#define GPLL0 228 +-#define GPLL0_OUT_EVEN 229 +-#define GPLL1 230 +-#define GPLL4 231 +-#define GPLL7 232 +-#define GCC_PCIE_0_CLKREF_CLK 233 +-#define GCC_PCIE_1_CLKREF_CLK 234 +-#define GCC_PCIE_2_CLKREF_CLK 235 +-#define GCC_PCIE_3_CLKREF_CLK 236 +-#define GCC_USB3_PRIM_CLKREF_CLK 237 +-#define GCC_USB3_SEC_CLKREF_CLK 238 +- +-#define GCC_EMAC_BCR 0 +-#define GCC_GPU_BCR 1 +-#define GCC_MMSS_BCR 2 +-#define GCC_NPU_BCR 3 +-#define GCC_PCIE_0_BCR 4 +-#define GCC_PCIE_0_PHY_BCR 5 +-#define GCC_PCIE_1_BCR 6 +-#define GCC_PCIE_1_PHY_BCR 7 +-#define GCC_PCIE_2_BCR 8 +-#define GCC_PCIE_2_PHY_BCR 9 +-#define GCC_PCIE_3_BCR 10 +-#define GCC_PCIE_3_PHY_BCR 11 +-#define GCC_PCIE_PHY_BCR 12 +-#define GCC_PDM_BCR 13 +-#define GCC_PRNG_BCR 14 +-#define GCC_QSPI_1_BCR 15 +-#define GCC_QSPI_BCR 16 +-#define GCC_QUPV3_WRAPPER_0_BCR 17 +-#define GCC_QUPV3_WRAPPER_1_BCR 18 +-#define GCC_QUPV3_WRAPPER_2_BCR 19 +-#define GCC_QUSB2PHY_5_BCR 20 +-#define GCC_QUSB2PHY_MP0_BCR 21 +-#define GCC_QUSB2PHY_MP1_BCR 22 +-#define GCC_QUSB2PHY_PRIM_BCR 23 +-#define GCC_QUSB2PHY_SEC_BCR 24 +-#define GCC_USB3_PHY_PRIM_SP0_BCR 25 +-#define GCC_USB3_PHY_PRIM_SP1_BCR 26 +-#define GCC_USB3_DP_PHY_PRIM_SP0_BCR 27 +-#define GCC_USB3_DP_PHY_PRIM_SP1_BCR 28 +-#define GCC_USB3_PHY_SEC_BCR 29 +-#define GCC_USB3PHY_PHY_SEC_BCR 30 +-#define GCC_SDCC2_BCR 31 +-#define GCC_SDCC4_BCR 32 +-#define GCC_TSIF_BCR 33 +-#define GCC_UFS_CARD_2_BCR 34 +-#define GCC_UFS_CARD_BCR 35 +-#define GCC_UFS_PHY_BCR 36 +-#define GCC_USB30_MP_BCR 37 +-#define GCC_USB30_PRIM_BCR 38 +-#define GCC_USB30_SEC_BCR 39 +-#define GCC_USB_PHY_CFG_AHB2PHY_BCR 40 +-#define GCC_VIDEO_AXIC_CLK_BCR 41 +-#define GCC_VIDEO_AXI0_CLK_BCR 42 +-#define GCC_VIDEO_AXI1_CLK_BCR 43 +-#define GCC_USB3_DP_PHY_SEC_BCR 44 +- +-/* GCC GDSCRs */ +-#define EMAC_GDSC 0 +-#define PCIE_0_GDSC 1 +-#define PCIE_1_GDSC 2 +-#define PCIE_2_GDSC 3 +-#define PCIE_3_GDSC 4 +-#define UFS_CARD_2_GDSC 5 +-#define UFS_CARD_GDSC 6 +-#define UFS_PHY_GDSC 7 +-#define USB30_MP_GDSC 8 +-#define USB30_PRIM_GDSC 9 +-#define USB30_SEC_GDSC 10 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sdm660.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sdm660.h +deleted file mode 100644 +index df8a6f3d367e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sdm660.h ++++ /dev/null +@@ -1,157 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. +- * Copyright (c) 2018, Craig Tatlor. +- */ +- +-#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H +-#define _DT_BINDINGS_CLK_MSM_GCC_660_H +- +-#define BLSP1_QUP1_I2C_APPS_CLK_SRC 0 +-#define BLSP1_QUP1_SPI_APPS_CLK_SRC 1 +-#define BLSP1_QUP2_I2C_APPS_CLK_SRC 2 +-#define BLSP1_QUP2_SPI_APPS_CLK_SRC 3 +-#define BLSP1_QUP3_I2C_APPS_CLK_SRC 4 +-#define BLSP1_QUP3_SPI_APPS_CLK_SRC 5 +-#define BLSP1_QUP4_I2C_APPS_CLK_SRC 6 +-#define BLSP1_QUP4_SPI_APPS_CLK_SRC 7 +-#define BLSP1_UART1_APPS_CLK_SRC 8 +-#define BLSP1_UART2_APPS_CLK_SRC 9 +-#define BLSP2_QUP1_I2C_APPS_CLK_SRC 10 +-#define BLSP2_QUP1_SPI_APPS_CLK_SRC 11 +-#define BLSP2_QUP2_I2C_APPS_CLK_SRC 12 +-#define BLSP2_QUP2_SPI_APPS_CLK_SRC 13 +-#define BLSP2_QUP3_I2C_APPS_CLK_SRC 14 +-#define BLSP2_QUP3_SPI_APPS_CLK_SRC 15 +-#define BLSP2_QUP4_I2C_APPS_CLK_SRC 16 +-#define BLSP2_QUP4_SPI_APPS_CLK_SRC 17 +-#define BLSP2_UART1_APPS_CLK_SRC 18 +-#define BLSP2_UART2_APPS_CLK_SRC 19 +-#define GCC_AGGRE2_UFS_AXI_CLK 20 +-#define GCC_AGGRE2_USB3_AXI_CLK 21 +-#define GCC_BIMC_GFX_CLK 22 +-#define GCC_BIMC_HMSS_AXI_CLK 23 +-#define GCC_BIMC_MSS_Q6_AXI_CLK 24 +-#define GCC_BLSP1_AHB_CLK 25 +-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 26 +-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 27 +-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 28 +-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 29 +-#define GCC_BLSP1_QUP3_I2C_APPS_CLK 30 +-#define GCC_BLSP1_QUP3_SPI_APPS_CLK 31 +-#define GCC_BLSP1_QUP4_I2C_APPS_CLK 32 +-#define GCC_BLSP1_QUP4_SPI_APPS_CLK 33 +-#define GCC_BLSP1_UART1_APPS_CLK 34 +-#define GCC_BLSP1_UART2_APPS_CLK 35 +-#define GCC_BLSP2_AHB_CLK 36 +-#define GCC_BLSP2_QUP1_I2C_APPS_CLK 37 +-#define GCC_BLSP2_QUP1_SPI_APPS_CLK 38 +-#define GCC_BLSP2_QUP2_I2C_APPS_CLK 39 +-#define GCC_BLSP2_QUP2_SPI_APPS_CLK 40 +-#define GCC_BLSP2_QUP3_I2C_APPS_CLK 41 +-#define GCC_BLSP2_QUP3_SPI_APPS_CLK 42 +-#define GCC_BLSP2_QUP4_I2C_APPS_CLK 43 +-#define GCC_BLSP2_QUP4_SPI_APPS_CLK 44 +-#define GCC_BLSP2_UART1_APPS_CLK 45 +-#define GCC_BLSP2_UART2_APPS_CLK 46 +-#define GCC_BOOT_ROM_AHB_CLK 47 +-#define GCC_CFG_NOC_USB2_AXI_CLK 48 +-#define GCC_CFG_NOC_USB3_AXI_CLK 49 +-#define GCC_DCC_AHB_CLK 50 +-#define GCC_GP1_CLK 51 +-#define GCC_GP2_CLK 52 +-#define GCC_GP3_CLK 53 +-#define GCC_GPU_BIMC_GFX_CLK 54 +-#define GCC_GPU_CFG_AHB_CLK 55 +-#define GCC_GPU_GPLL0_CLK 56 +-#define GCC_GPU_GPLL0_DIV_CLK 57 +-#define GCC_HMSS_DVM_BUS_CLK 58 +-#define GCC_HMSS_RBCPR_CLK 59 +-#define GCC_MMSS_GPLL0_CLK 60 +-#define GCC_MMSS_GPLL0_DIV_CLK 61 +-#define GCC_MMSS_NOC_CFG_AHB_CLK 62 +-#define GCC_MMSS_SYS_NOC_AXI_CLK 63 +-#define GCC_MSS_CFG_AHB_CLK 64 +-#define GCC_MSS_GPLL0_DIV_CLK 65 +-#define GCC_MSS_MNOC_BIMC_AXI_CLK 66 +-#define GCC_MSS_Q6_BIMC_AXI_CLK 67 +-#define GCC_MSS_SNOC_AXI_CLK 68 +-#define GCC_PDM2_CLK 69 +-#define GCC_PDM_AHB_CLK 70 +-#define GCC_PRNG_AHB_CLK 71 +-#define GCC_QSPI_AHB_CLK 72 +-#define GCC_QSPI_SER_CLK 73 +-#define GCC_SDCC1_AHB_CLK 74 +-#define GCC_SDCC1_APPS_CLK 75 +-#define GCC_SDCC1_ICE_CORE_CLK 76 +-#define GCC_SDCC2_AHB_CLK 77 +-#define GCC_SDCC2_APPS_CLK 78 +-#define GCC_UFS_AHB_CLK 79 +-#define GCC_UFS_AXI_CLK 80 +-#define GCC_UFS_CLKREF_CLK 81 +-#define GCC_UFS_ICE_CORE_CLK 82 +-#define GCC_UFS_PHY_AUX_CLK 83 +-#define GCC_UFS_RX_SYMBOL_0_CLK 84 +-#define GCC_UFS_RX_SYMBOL_1_CLK 85 +-#define GCC_UFS_TX_SYMBOL_0_CLK 86 +-#define GCC_UFS_UNIPRO_CORE_CLK 87 +-#define GCC_USB20_MASTER_CLK 88 +-#define GCC_USB20_MOCK_UTMI_CLK 89 +-#define GCC_USB20_SLEEP_CLK 90 +-#define GCC_USB30_MASTER_CLK 91 +-#define GCC_USB30_MOCK_UTMI_CLK 92 +-#define GCC_USB30_SLEEP_CLK 93 +-#define GCC_USB3_CLKREF_CLK 94 +-#define GCC_USB3_PHY_AUX_CLK 95 +-#define GCC_USB3_PHY_PIPE_CLK 96 +-#define GCC_USB_PHY_CFG_AHB2PHY_CLK 97 +-#define GP1_CLK_SRC 98 +-#define GP2_CLK_SRC 99 +-#define GP3_CLK_SRC 100 +-#define GPLL0 101 +-#define GPLL0_EARLY 102 +-#define GPLL1 103 +-#define GPLL1_EARLY 104 +-#define GPLL4 105 +-#define GPLL4_EARLY 106 +-#define HMSS_GPLL0_CLK_SRC 107 +-#define HMSS_GPLL4_CLK_SRC 108 +-#define HMSS_RBCPR_CLK_SRC 109 +-#define PDM2_CLK_SRC 110 +-#define QSPI_SER_CLK_SRC 111 +-#define SDCC1_APPS_CLK_SRC 112 +-#define SDCC1_ICE_CORE_CLK_SRC 113 +-#define SDCC2_APPS_CLK_SRC 114 +-#define UFS_AXI_CLK_SRC 115 +-#define UFS_ICE_CORE_CLK_SRC 116 +-#define UFS_PHY_AUX_CLK_SRC 117 +-#define UFS_UNIPRO_CORE_CLK_SRC 118 +-#define USB20_MASTER_CLK_SRC 119 +-#define USB20_MOCK_UTMI_CLK_SRC 120 +-#define USB30_MASTER_CLK_SRC 121 +-#define USB30_MOCK_UTMI_CLK_SRC 122 +-#define USB3_PHY_AUX_CLK_SRC 123 +-#define GPLL0_OUT_MSSCC 124 +-#define GCC_UFS_AXI_HW_CTL_CLK 125 +-#define GCC_UFS_ICE_CORE_HW_CTL_CLK 126 +-#define GCC_UFS_PHY_AUX_HW_CTL_CLK 127 +-#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 128 +-#define GCC_RX0_USB2_CLKREF_CLK 129 +-#define GCC_RX1_USB2_CLKREF_CLK 130 +- +-#define PCIE_0_GDSC 0 +-#define UFS_GDSC 1 +-#define USB_30_GDSC 2 +- +-#define GCC_QUSB2PHY_PRIM_BCR 0 +-#define GCC_QUSB2PHY_SEC_BCR 1 +-#define GCC_UFS_BCR 2 +-#define GCC_USB3_DP_PHY_BCR 3 +-#define GCC_USB3_PHY_BCR 4 +-#define GCC_USB3PHY_PHY_BCR 5 +-#define GCC_USB_20_BCR 6 +-#define GCC_USB_30_BCR 7 +-#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8 +-#define GCC_MSS_RESTART 9 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sdm845.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sdm845.h +deleted file mode 100644 +index 968fa65b9c42..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sdm845.h ++++ /dev/null +@@ -1,246 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2018, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H +-#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H +- +-/* GCC clock registers */ +-#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 +-#define GCC_AGGRE_UFS_CARD_AXI_CLK 1 +-#define GCC_AGGRE_UFS_PHY_AXI_CLK 2 +-#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3 +-#define GCC_AGGRE_USB3_SEC_AXI_CLK 4 +-#define GCC_BOOT_ROM_AHB_CLK 5 +-#define GCC_CAMERA_AHB_CLK 6 +-#define GCC_CAMERA_AXI_CLK 7 +-#define GCC_CAMERA_XO_CLK 8 +-#define GCC_CE1_AHB_CLK 9 +-#define GCC_CE1_AXI_CLK 10 +-#define GCC_CE1_CLK 11 +-#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 +-#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 +-#define GCC_CPUSS_AHB_CLK 14 +-#define GCC_CPUSS_AHB_CLK_SRC 15 +-#define GCC_CPUSS_RBCPR_CLK 16 +-#define GCC_CPUSS_RBCPR_CLK_SRC 17 +-#define GCC_DDRSS_GPU_AXI_CLK 18 +-#define GCC_DISP_AHB_CLK 19 +-#define GCC_DISP_AXI_CLK 20 +-#define GCC_DISP_GPLL0_CLK_SRC 21 +-#define GCC_DISP_GPLL0_DIV_CLK_SRC 22 +-#define GCC_DISP_XO_CLK 23 +-#define GCC_GP1_CLK 24 +-#define GCC_GP1_CLK_SRC 25 +-#define GCC_GP2_CLK 26 +-#define GCC_GP2_CLK_SRC 27 +-#define GCC_GP3_CLK 28 +-#define GCC_GP3_CLK_SRC 29 +-#define GCC_GPU_CFG_AHB_CLK 30 +-#define GCC_GPU_GPLL0_CLK_SRC 31 +-#define GCC_GPU_GPLL0_DIV_CLK_SRC 32 +-#define GCC_GPU_MEMNOC_GFX_CLK 33 +-#define GCC_GPU_SNOC_DVM_GFX_CLK 34 +-#define GCC_MSS_AXIS2_CLK 35 +-#define GCC_MSS_CFG_AHB_CLK 36 +-#define GCC_MSS_GPLL0_DIV_CLK_SRC 37 +-#define GCC_MSS_MFAB_AXIS_CLK 38 +-#define GCC_MSS_Q6_MEMNOC_AXI_CLK 39 +-#define GCC_MSS_SNOC_AXI_CLK 40 +-#define GCC_PCIE_0_AUX_CLK 41 +-#define GCC_PCIE_0_AUX_CLK_SRC 42 +-#define GCC_PCIE_0_CFG_AHB_CLK 43 +-#define GCC_PCIE_0_CLKREF_CLK 44 +-#define GCC_PCIE_0_MSTR_AXI_CLK 45 +-#define GCC_PCIE_0_PIPE_CLK 46 +-#define GCC_PCIE_0_SLV_AXI_CLK 47 +-#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48 +-#define GCC_PCIE_1_AUX_CLK 49 +-#define GCC_PCIE_1_AUX_CLK_SRC 50 +-#define GCC_PCIE_1_CFG_AHB_CLK 51 +-#define GCC_PCIE_1_CLKREF_CLK 52 +-#define GCC_PCIE_1_MSTR_AXI_CLK 53 +-#define GCC_PCIE_1_PIPE_CLK 54 +-#define GCC_PCIE_1_SLV_AXI_CLK 55 +-#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 56 +-#define GCC_PCIE_PHY_AUX_CLK 57 +-#define GCC_PCIE_PHY_REFGEN_CLK 58 +-#define GCC_PCIE_PHY_REFGEN_CLK_SRC 59 +-#define GCC_PDM2_CLK 60 +-#define GCC_PDM2_CLK_SRC 61 +-#define GCC_PDM_AHB_CLK 62 +-#define GCC_PDM_XO4_CLK 63 +-#define GCC_PRNG_AHB_CLK 64 +-#define GCC_QMIP_CAMERA_AHB_CLK 65 +-#define GCC_QMIP_DISP_AHB_CLK 66 +-#define GCC_QMIP_VIDEO_AHB_CLK 67 +-#define GCC_QUPV3_WRAP0_S0_CLK 68 +-#define GCC_QUPV3_WRAP0_S0_CLK_SRC 69 +-#define GCC_QUPV3_WRAP0_S1_CLK 70 +-#define GCC_QUPV3_WRAP0_S1_CLK_SRC 71 +-#define GCC_QUPV3_WRAP0_S2_CLK 72 +-#define GCC_QUPV3_WRAP0_S2_CLK_SRC 73 +-#define GCC_QUPV3_WRAP0_S3_CLK 74 +-#define GCC_QUPV3_WRAP0_S3_CLK_SRC 75 +-#define GCC_QUPV3_WRAP0_S4_CLK 76 +-#define GCC_QUPV3_WRAP0_S4_CLK_SRC 77 +-#define GCC_QUPV3_WRAP0_S5_CLK 78 +-#define GCC_QUPV3_WRAP0_S5_CLK_SRC 79 +-#define GCC_QUPV3_WRAP0_S6_CLK 80 +-#define GCC_QUPV3_WRAP0_S6_CLK_SRC 81 +-#define GCC_QUPV3_WRAP0_S7_CLK 82 +-#define GCC_QUPV3_WRAP0_S7_CLK_SRC 83 +-#define GCC_QUPV3_WRAP1_S0_CLK 84 +-#define GCC_QUPV3_WRAP1_S0_CLK_SRC 85 +-#define GCC_QUPV3_WRAP1_S1_CLK 86 +-#define GCC_QUPV3_WRAP1_S1_CLK_SRC 87 +-#define GCC_QUPV3_WRAP1_S2_CLK 88 +-#define GCC_QUPV3_WRAP1_S2_CLK_SRC 89 +-#define GCC_QUPV3_WRAP1_S3_CLK 90 +-#define GCC_QUPV3_WRAP1_S3_CLK_SRC 91 +-#define GCC_QUPV3_WRAP1_S4_CLK 92 +-#define GCC_QUPV3_WRAP1_S4_CLK_SRC 93 +-#define GCC_QUPV3_WRAP1_S5_CLK 94 +-#define GCC_QUPV3_WRAP1_S5_CLK_SRC 95 +-#define GCC_QUPV3_WRAP1_S6_CLK 96 +-#define GCC_QUPV3_WRAP1_S6_CLK_SRC 97 +-#define GCC_QUPV3_WRAP1_S7_CLK 98 +-#define GCC_QUPV3_WRAP1_S7_CLK_SRC 99 +-#define GCC_QUPV3_WRAP_0_M_AHB_CLK 100 +-#define GCC_QUPV3_WRAP_0_S_AHB_CLK 101 +-#define GCC_QUPV3_WRAP_1_M_AHB_CLK 102 +-#define GCC_QUPV3_WRAP_1_S_AHB_CLK 103 +-#define GCC_SDCC2_AHB_CLK 104 +-#define GCC_SDCC2_APPS_CLK 105 +-#define GCC_SDCC2_APPS_CLK_SRC 106 +-#define GCC_SDCC4_AHB_CLK 107 +-#define GCC_SDCC4_APPS_CLK 108 +-#define GCC_SDCC4_APPS_CLK_SRC 109 +-#define GCC_SYS_NOC_CPUSS_AHB_CLK 110 +-#define GCC_TSIF_AHB_CLK 111 +-#define GCC_TSIF_INACTIVITY_TIMERS_CLK 112 +-#define GCC_TSIF_REF_CLK 113 +-#define GCC_TSIF_REF_CLK_SRC 114 +-#define GCC_UFS_CARD_AHB_CLK 115 +-#define GCC_UFS_CARD_AXI_CLK 116 +-#define GCC_UFS_CARD_AXI_CLK_SRC 117 +-#define GCC_UFS_CARD_CLKREF_CLK 118 +-#define GCC_UFS_CARD_ICE_CORE_CLK 119 +-#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 120 +-#define GCC_UFS_CARD_PHY_AUX_CLK 121 +-#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 122 +-#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 123 +-#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 124 +-#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 125 +-#define GCC_UFS_CARD_UNIPRO_CORE_CLK 126 +-#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 127 +-#define GCC_UFS_MEM_CLKREF_CLK 128 +-#define GCC_UFS_PHY_AHB_CLK 129 +-#define GCC_UFS_PHY_AXI_CLK 130 +-#define GCC_UFS_PHY_AXI_CLK_SRC 131 +-#define GCC_UFS_PHY_ICE_CORE_CLK 132 +-#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 133 +-#define GCC_UFS_PHY_PHY_AUX_CLK 134 +-#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 135 +-#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 136 +-#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 137 +-#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK 139 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 140 +-#define GCC_USB30_PRIM_MASTER_CLK 141 +-#define GCC_USB30_PRIM_MASTER_CLK_SRC 142 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK 143 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144 +-#define GCC_USB30_PRIM_SLEEP_CLK 145 +-#define GCC_USB30_SEC_MASTER_CLK 146 +-#define GCC_USB30_SEC_MASTER_CLK_SRC 147 +-#define GCC_USB30_SEC_MOCK_UTMI_CLK 148 +-#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 149 +-#define GCC_USB30_SEC_SLEEP_CLK 150 +-#define GCC_USB3_PRIM_CLKREF_CLK 151 +-#define GCC_USB3_PRIM_PHY_AUX_CLK 152 +-#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 153 +-#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 154 +-#define GCC_USB3_PRIM_PHY_PIPE_CLK 155 +-#define GCC_USB3_SEC_CLKREF_CLK 156 +-#define GCC_USB3_SEC_PHY_AUX_CLK 157 +-#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 158 +-#define GCC_USB3_SEC_PHY_PIPE_CLK 159 +-#define GCC_USB3_SEC_PHY_COM_AUX_CLK 160 +-#define GCC_USB_PHY_CFG_AHB2PHY_CLK 161 +-#define GCC_VIDEO_AHB_CLK 162 +-#define GCC_VIDEO_AXI_CLK 163 +-#define GCC_VIDEO_XO_CLK 164 +-#define GPLL0 165 +-#define GPLL0_OUT_EVEN 166 +-#define GPLL0_OUT_MAIN 167 +-#define GCC_GPU_IREF_CLK 168 +-#define GCC_SDCC1_AHB_CLK 169 +-#define GCC_SDCC1_APPS_CLK 170 +-#define GCC_SDCC1_ICE_CORE_CLK 171 +-#define GCC_SDCC1_APPS_CLK_SRC 172 +-#define GCC_SDCC1_ICE_CORE_CLK_SRC 173 +-#define GCC_APC_VS_CLK 174 +-#define GCC_GPU_VS_CLK 175 +-#define GCC_MSS_VS_CLK 176 +-#define GCC_VDDA_VS_CLK 177 +-#define GCC_VDDCX_VS_CLK 178 +-#define GCC_VDDMX_VS_CLK 179 +-#define GCC_VS_CTRL_AHB_CLK 180 +-#define GCC_VS_CTRL_CLK 181 +-#define GCC_VS_CTRL_CLK_SRC 182 +-#define GCC_VSENSOR_CLK_SRC 183 +-#define GPLL4 184 +-#define GCC_CPUSS_DVM_BUS_CLK 185 +-#define GCC_CPUSS_GNOC_CLK 186 +-#define GCC_QSPI_CORE_CLK_SRC 187 +-#define GCC_QSPI_CORE_CLK 188 +-#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 +-#define GCC_LPASS_Q6_AXI_CLK 190 +-#define GCC_LPASS_SWAY_CLK 191 +- +-/* GCC Resets */ +-#define GCC_MMSS_BCR 0 +-#define GCC_PCIE_0_BCR 1 +-#define GCC_PCIE_1_BCR 2 +-#define GCC_PCIE_PHY_BCR 3 +-#define GCC_PDM_BCR 4 +-#define GCC_PRNG_BCR 5 +-#define GCC_QUPV3_WRAPPER_0_BCR 6 +-#define GCC_QUPV3_WRAPPER_1_BCR 7 +-#define GCC_QUSB2PHY_PRIM_BCR 8 +-#define GCC_QUSB2PHY_SEC_BCR 9 +-#define GCC_SDCC2_BCR 10 +-#define GCC_SDCC4_BCR 11 +-#define GCC_TSIF_BCR 12 +-#define GCC_UFS_CARD_BCR 13 +-#define GCC_UFS_PHY_BCR 14 +-#define GCC_USB30_PRIM_BCR 15 +-#define GCC_USB30_SEC_BCR 16 +-#define GCC_USB3_PHY_PRIM_BCR 17 +-#define GCC_USB3PHY_PHY_PRIM_BCR 18 +-#define GCC_USB3_DP_PHY_PRIM_BCR 19 +-#define GCC_USB3_PHY_SEC_BCR 20 +-#define GCC_USB3PHY_PHY_SEC_BCR 21 +-#define GCC_USB3_DP_PHY_SEC_BCR 22 +-#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 +-#define GCC_PCIE_0_PHY_BCR 24 +-#define GCC_PCIE_1_PHY_BCR 25 +- +-/* GCC GDSCRs */ +-#define PCIE_0_GDSC 0 +-#define PCIE_1_GDSC 1 +-#define UFS_CARD_GDSC 2 +-#define UFS_PHY_GDSC 3 +-#define USB30_PRIM_GDSC 4 +-#define USB30_SEC_GDSC 5 +-#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 6 +-#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 7 +-#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 8 +-#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 9 +-#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 10 +-#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11 +-#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 12 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sdx55.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sdx55.h +deleted file mode 100644 +index fb9a5942f793..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sdx55.h ++++ /dev/null +@@ -1,117 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +-/* +- * Copyright (c) 2018, The Linux Foundation. All rights reserved. +- * Copyright (c) 2020, Linaro Ltd. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX55_H +-#define _DT_BINDINGS_CLK_QCOM_GCC_SDX55_H +- +-#define GPLL0 3 +-#define GPLL0_OUT_EVEN 4 +-#define GPLL4 5 +-#define GPLL4_OUT_EVEN 6 +-#define GPLL5 7 +-#define GCC_AHB_PCIE_LINK_CLK 8 +-#define GCC_BLSP1_AHB_CLK 9 +-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 10 +-#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 11 +-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 12 +-#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 13 +-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 14 +-#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 15 +-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 16 +-#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 17 +-#define GCC_BLSP1_QUP3_I2C_APPS_CLK 18 +-#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 19 +-#define GCC_BLSP1_QUP3_SPI_APPS_CLK 20 +-#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 21 +-#define GCC_BLSP1_QUP4_I2C_APPS_CLK 22 +-#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 23 +-#define GCC_BLSP1_QUP4_SPI_APPS_CLK 24 +-#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 25 +-#define GCC_BLSP1_UART1_APPS_CLK 26 +-#define GCC_BLSP1_UART1_APPS_CLK_SRC 27 +-#define GCC_BLSP1_UART2_APPS_CLK 28 +-#define GCC_BLSP1_UART2_APPS_CLK_SRC 29 +-#define GCC_BLSP1_UART3_APPS_CLK 30 +-#define GCC_BLSP1_UART3_APPS_CLK_SRC 31 +-#define GCC_BLSP1_UART4_APPS_CLK 32 +-#define GCC_BLSP1_UART4_APPS_CLK_SRC 33 +-#define GCC_BOOT_ROM_AHB_CLK 34 +-#define GCC_CE1_AHB_CLK 35 +-#define GCC_CE1_AXI_CLK 36 +-#define GCC_CE1_CLK 37 +-#define GCC_CPUSS_AHB_CLK 38 +-#define GCC_CPUSS_AHB_CLK_SRC 39 +-#define GCC_CPUSS_GNOC_CLK 40 +-#define GCC_CPUSS_RBCPR_CLK 41 +-#define GCC_CPUSS_RBCPR_CLK_SRC 42 +-#define GCC_EMAC_CLK_SRC 43 +-#define GCC_EMAC_PTP_CLK_SRC 44 +-#define GCC_ETH_AXI_CLK 45 +-#define GCC_ETH_PTP_CLK 46 +-#define GCC_ETH_RGMII_CLK 47 +-#define GCC_ETH_SLAVE_AHB_CLK 48 +-#define GCC_GP1_CLK 49 +-#define GCC_GP1_CLK_SRC 50 +-#define GCC_GP2_CLK 51 +-#define GCC_GP2_CLK_SRC 52 +-#define GCC_GP3_CLK 53 +-#define GCC_GP3_CLK_SRC 54 +-#define GCC_PCIE_0_CLKREF_CLK 55 +-#define GCC_PCIE_AUX_CLK 56 +-#define GCC_PCIE_AUX_PHY_CLK_SRC 57 +-#define GCC_PCIE_CFG_AHB_CLK 58 +-#define GCC_PCIE_MSTR_AXI_CLK 59 +-#define GCC_PCIE_PIPE_CLK 60 +-#define GCC_PCIE_RCHNG_PHY_CLK 61 +-#define GCC_PCIE_RCHNG_PHY_CLK_SRC 62 +-#define GCC_PCIE_SLEEP_CLK 63 +-#define GCC_PCIE_SLV_AXI_CLK 64 +-#define GCC_PCIE_SLV_Q2A_AXI_CLK 65 +-#define GCC_PDM2_CLK 66 +-#define GCC_PDM2_CLK_SRC 67 +-#define GCC_PDM_AHB_CLK 68 +-#define GCC_PDM_XO4_CLK 69 +-#define GCC_SDCC1_AHB_CLK 70 +-#define GCC_SDCC1_APPS_CLK 71 +-#define GCC_SDCC1_APPS_CLK_SRC 72 +-#define GCC_SYS_NOC_CPUSS_AHB_CLK 73 +-#define GCC_USB30_MASTER_CLK 74 +-#define GCC_USB30_MASTER_CLK_SRC 75 +-#define GCC_USB30_MOCK_UTMI_CLK 76 +-#define GCC_USB30_MOCK_UTMI_CLK_SRC 77 +-#define GCC_USB30_MSTR_AXI_CLK 78 +-#define GCC_USB30_SLEEP_CLK 79 +-#define GCC_USB30_SLV_AHB_CLK 80 +-#define GCC_USB3_PHY_AUX_CLK 81 +-#define GCC_USB3_PHY_AUX_CLK_SRC 82 +-#define GCC_USB3_PHY_PIPE_CLK 83 +-#define GCC_USB3_PRIM_CLKREF_CLK 84 +-#define GCC_USB_PHY_CFG_AHB2PHY_CLK 85 +-#define GCC_XO_DIV4_CLK 86 +-#define GCC_XO_PCIE_LINK_CLK 87 +- +-#define GCC_EMAC_BCR 0 +-#define GCC_PCIE_BCR 1 +-#define GCC_PCIE_LINK_DOWN_BCR 2 +-#define GCC_PCIE_NOCSR_COM_PHY_BCR 3 +-#define GCC_PCIE_PHY_BCR 4 +-#define GCC_PCIE_PHY_CFG_AHB_BCR 5 +-#define GCC_PCIE_PHY_COM_BCR 6 +-#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 7 +-#define GCC_PDM_BCR 8 +-#define GCC_QUSB2PHY_BCR 9 +-#define GCC_TCSR_PCIE_BCR 10 +-#define GCC_USB30_BCR 11 +-#define GCC_USB3_PHY_BCR 12 +-#define GCC_USB3PHY_PHY_BCR 13 +-#define GCC_USB_PHY_CFG_AHB2PHY_BCR 14 +- +-/* GCC power domains */ +-#define USB30_GDSC 0 +-#define PCIE_GDSC 1 +-#define EMAC_GDSC 2 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sm6115.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sm6115.h +deleted file mode 100644 +index b91a7b460433..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sm6115.h ++++ /dev/null +@@ -1,201 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +-/* +- * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6115_H +-#define _DT_BINDINGS_CLK_QCOM_GCC_SM6115_H +- +-/* GCC clocks */ +-#define GPLL0 0 +-#define GPLL0_OUT_AUX2 1 +-#define GPLL0_OUT_MAIN 2 +-#define GPLL10 3 +-#define GPLL10_OUT_MAIN 4 +-#define GPLL11 5 +-#define GPLL11_OUT_MAIN 6 +-#define GPLL3 7 +-#define GPLL4 8 +-#define GPLL4_OUT_MAIN 9 +-#define GPLL6 10 +-#define GPLL6_OUT_MAIN 11 +-#define GPLL7 12 +-#define GPLL7_OUT_MAIN 13 +-#define GPLL8 14 +-#define GPLL8_OUT_MAIN 15 +-#define GPLL9 16 +-#define GPLL9_OUT_MAIN 17 +-#define GCC_CAMSS_CSI0PHYTIMER_CLK 18 +-#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 19 +-#define GCC_CAMSS_CSI1PHYTIMER_CLK 20 +-#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 21 +-#define GCC_CAMSS_CSI2PHYTIMER_CLK 22 +-#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC 23 +-#define GCC_CAMSS_MCLK0_CLK 24 +-#define GCC_CAMSS_MCLK0_CLK_SRC 25 +-#define GCC_CAMSS_MCLK1_CLK 26 +-#define GCC_CAMSS_MCLK1_CLK_SRC 27 +-#define GCC_CAMSS_MCLK2_CLK 28 +-#define GCC_CAMSS_MCLK2_CLK_SRC 29 +-#define GCC_CAMSS_MCLK3_CLK 30 +-#define GCC_CAMSS_MCLK3_CLK_SRC 31 +-#define GCC_CAMSS_NRT_AXI_CLK 32 +-#define GCC_CAMSS_OPE_AHB_CLK 33 +-#define GCC_CAMSS_OPE_AHB_CLK_SRC 34 +-#define GCC_CAMSS_OPE_CLK 35 +-#define GCC_CAMSS_OPE_CLK_SRC 36 +-#define GCC_CAMSS_RT_AXI_CLK 37 +-#define GCC_CAMSS_TFE_0_CLK 38 +-#define GCC_CAMSS_TFE_0_CLK_SRC 39 +-#define GCC_CAMSS_TFE_0_CPHY_RX_CLK 40 +-#define GCC_CAMSS_TFE_0_CSID_CLK 41 +-#define GCC_CAMSS_TFE_0_CSID_CLK_SRC 42 +-#define GCC_CAMSS_TFE_1_CLK 43 +-#define GCC_CAMSS_TFE_1_CLK_SRC 44 +-#define GCC_CAMSS_TFE_1_CPHY_RX_CLK 45 +-#define GCC_CAMSS_TFE_1_CSID_CLK 46 +-#define GCC_CAMSS_TFE_1_CSID_CLK_SRC 47 +-#define GCC_CAMSS_TFE_2_CLK 48 +-#define GCC_CAMSS_TFE_2_CLK_SRC 49 +-#define GCC_CAMSS_TFE_2_CPHY_RX_CLK 50 +-#define GCC_CAMSS_TFE_2_CSID_CLK 51 +-#define GCC_CAMSS_TFE_2_CSID_CLK_SRC 52 +-#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC 53 +-#define GCC_CAMSS_TOP_AHB_CLK 54 +-#define GCC_CAMSS_TOP_AHB_CLK_SRC 55 +-#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 56 +-#define GCC_CPUSS_AHB_CLK 57 +-#define GCC_CPUSS_GNOC_CLK 60 +-#define GCC_DISP_AHB_CLK 61 +-#define GCC_DISP_GPLL0_DIV_CLK_SRC 62 +-#define GCC_DISP_HF_AXI_CLK 63 +-#define GCC_DISP_THROTTLE_CORE_CLK 64 +-#define GCC_DISP_XO_CLK 65 +-#define GCC_GP1_CLK 66 +-#define GCC_GP1_CLK_SRC 67 +-#define GCC_GP2_CLK 68 +-#define GCC_GP2_CLK_SRC 69 +-#define GCC_GP3_CLK 70 +-#define GCC_GP3_CLK_SRC 71 +-#define GCC_GPU_CFG_AHB_CLK 72 +-#define GCC_GPU_GPLL0_CLK_SRC 73 +-#define GCC_GPU_GPLL0_DIV_CLK_SRC 74 +-#define GCC_GPU_IREF_CLK 75 +-#define GCC_GPU_MEMNOC_GFX_CLK 76 +-#define GCC_GPU_SNOC_DVM_GFX_CLK 77 +-#define GCC_GPU_THROTTLE_CORE_CLK 78 +-#define GCC_GPU_THROTTLE_XO_CLK 79 +-#define GCC_PDM2_CLK 80 +-#define GCC_PDM2_CLK_SRC 81 +-#define GCC_PDM_AHB_CLK 82 +-#define GCC_PDM_XO4_CLK 83 +-#define GCC_PRNG_AHB_CLK 84 +-#define GCC_QMIP_CAMERA_NRT_AHB_CLK 85 +-#define GCC_QMIP_CAMERA_RT_AHB_CLK 86 +-#define GCC_QMIP_DISP_AHB_CLK 87 +-#define GCC_QMIP_GPU_CFG_AHB_CLK 88 +-#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 89 +-#define GCC_QUPV3_WRAP0_CORE_2X_CLK 90 +-#define GCC_QUPV3_WRAP0_CORE_CLK 91 +-#define GCC_QUPV3_WRAP0_S0_CLK 92 +-#define GCC_QUPV3_WRAP0_S0_CLK_SRC 93 +-#define GCC_QUPV3_WRAP0_S1_CLK 94 +-#define GCC_QUPV3_WRAP0_S1_CLK_SRC 95 +-#define GCC_QUPV3_WRAP0_S2_CLK 96 +-#define GCC_QUPV3_WRAP0_S2_CLK_SRC 97 +-#define GCC_QUPV3_WRAP0_S3_CLK 98 +-#define GCC_QUPV3_WRAP0_S3_CLK_SRC 99 +-#define GCC_QUPV3_WRAP0_S4_CLK 100 +-#define GCC_QUPV3_WRAP0_S4_CLK_SRC 101 +-#define GCC_QUPV3_WRAP0_S5_CLK 102 +-#define GCC_QUPV3_WRAP0_S5_CLK_SRC 103 +-#define GCC_QUPV3_WRAP_0_M_AHB_CLK 104 +-#define GCC_QUPV3_WRAP_0_S_AHB_CLK 105 +-#define GCC_SDCC1_AHB_CLK 106 +-#define GCC_SDCC1_APPS_CLK 107 +-#define GCC_SDCC1_APPS_CLK_SRC 108 +-#define GCC_SDCC1_ICE_CORE_CLK 109 +-#define GCC_SDCC1_ICE_CORE_CLK_SRC 110 +-#define GCC_SDCC2_AHB_CLK 111 +-#define GCC_SDCC2_APPS_CLK 112 +-#define GCC_SDCC2_APPS_CLK_SRC 113 +-#define GCC_SYS_NOC_CPUSS_AHB_CLK 114 +-#define GCC_SYS_NOC_UFS_PHY_AXI_CLK 115 +-#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 116 +-#define GCC_UFS_PHY_AHB_CLK 117 +-#define GCC_UFS_PHY_AXI_CLK 118 +-#define GCC_UFS_PHY_AXI_CLK_SRC 119 +-#define GCC_UFS_PHY_ICE_CORE_CLK 120 +-#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 121 +-#define GCC_UFS_PHY_PHY_AUX_CLK 122 +-#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 123 +-#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 124 +-#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 125 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK 126 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 127 +-#define GCC_USB30_PRIM_MASTER_CLK 128 +-#define GCC_USB30_PRIM_MASTER_CLK_SRC 129 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK 130 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 131 +-#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 132 +-#define GCC_USB30_PRIM_SLEEP_CLK 133 +-#define GCC_USB3_PRIM_CLKREF_CLK 134 +-#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 135 +-#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 136 +-#define GCC_USB3_PRIM_PHY_PIPE_CLK 137 +-#define GCC_VCODEC0_AXI_CLK 138 +-#define GCC_VENUS_AHB_CLK 139 +-#define GCC_VENUS_CTL_AXI_CLK 140 +-#define GCC_VIDEO_AHB_CLK 141 +-#define GCC_VIDEO_AXI0_CLK 142 +-#define GCC_VIDEO_THROTTLE_CORE_CLK 143 +-#define GCC_VIDEO_VCODEC0_SYS_CLK 144 +-#define GCC_VIDEO_VENUS_CLK_SRC 145 +-#define GCC_VIDEO_VENUS_CTL_CLK 146 +-#define GCC_VIDEO_XO_CLK 147 +-#define GCC_AHB2PHY_CSI_CLK 148 +-#define GCC_AHB2PHY_USB_CLK 149 +-#define GCC_BIMC_GPU_AXI_CLK 150 +-#define GCC_BOOT_ROM_AHB_CLK 151 +-#define GCC_CAM_THROTTLE_NRT_CLK 152 +-#define GCC_CAM_THROTTLE_RT_CLK 153 +-#define GCC_CAMERA_AHB_CLK 154 +-#define GCC_CAMERA_XO_CLK 155 +-#define GCC_CAMSS_AXI_CLK 156 +-#define GCC_CAMSS_AXI_CLK_SRC 157 +-#define GCC_CAMSS_CAMNOC_ATB_CLK 158 +-#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 159 +-#define GCC_CAMSS_CCI_0_CLK 160 +-#define GCC_CAMSS_CCI_CLK_SRC 161 +-#define GCC_CAMSS_CPHY_0_CLK 162 +-#define GCC_CAMSS_CPHY_1_CLK 163 +-#define GCC_CAMSS_CPHY_2_CLK 164 +-#define GCC_UFS_CLKREF_CLK 165 +-#define GCC_DISP_GPLL0_CLK_SRC 166 +- +-/* GCC resets */ +-#define GCC_QUSB2PHY_PRIM_BCR 0 +-#define GCC_QUSB2PHY_SEC_BCR 1 +-#define GCC_SDCC1_BCR 2 +-#define GCC_UFS_PHY_BCR 3 +-#define GCC_USB30_PRIM_BCR 4 +-#define GCC_USB_PHY_CFG_AHB2PHY_BCR 5 +-#define GCC_VCODEC0_BCR 6 +-#define GCC_VENUS_BCR 7 +-#define GCC_VIDEO_INTERFACE_BCR 8 +-#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 9 +-#define GCC_USB3_PHY_PRIM_SP0_BCR 10 +-#define GCC_SDCC2_BCR 11 +- +-/* Indexes for GDSCs */ +-#define GCC_CAMSS_TOP_GDSC 0 +-#define GCC_UFS_PHY_GDSC 1 +-#define GCC_USB30_PRIM_GDSC 2 +-#define GCC_VCODEC0_GDSC 3 +-#define GCC_VENUS_GDSC 4 +-#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 5 +-#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 6 +-#define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC 7 +-#define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC 8 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sm6125.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sm6125.h +deleted file mode 100644 +index 08ea18086824..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sm6125.h ++++ /dev/null +@@ -1,240 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +-/* +- * Copyright (c) 2021, Konrad Dybcio +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6125_H +-#define _DT_BINDINGS_CLK_QCOM_GCC_SM6125_H +- +-#define GPLL0_OUT_AUX2 0 +-#define GPLL0_OUT_MAIN 1 +-#define GPLL6_OUT_MAIN 2 +-#define GPLL7_OUT_MAIN 3 +-#define GPLL8_OUT_MAIN 4 +-#define GPLL9_OUT_MAIN 5 +-#define GPLL0_OUT_EARLY 6 +-#define GPLL3_OUT_EARLY 7 +-#define GPLL4_OUT_MAIN 8 +-#define GPLL5_OUT_MAIN 9 +-#define GPLL6_OUT_EARLY 10 +-#define GPLL7_OUT_EARLY 11 +-#define GPLL8_OUT_EARLY 12 +-#define GPLL9_OUT_EARLY 13 +-#define GCC_AHB2PHY_CSI_CLK 14 +-#define GCC_AHB2PHY_USB_CLK 15 +-#define GCC_APC_VS_CLK 16 +-#define GCC_BOOT_ROM_AHB_CLK 17 +-#define GCC_CAMERA_AHB_CLK 18 +-#define GCC_CAMERA_XO_CLK 19 +-#define GCC_CAMSS_AHB_CLK_SRC 20 +-#define GCC_CAMSS_CCI_AHB_CLK 21 +-#define GCC_CAMSS_CCI_CLK 22 +-#define GCC_CAMSS_CCI_CLK_SRC 23 +-#define GCC_CAMSS_CPHY_CSID0_CLK 24 +-#define GCC_CAMSS_CPHY_CSID1_CLK 25 +-#define GCC_CAMSS_CPHY_CSID2_CLK 26 +-#define GCC_CAMSS_CPHY_CSID3_CLK 27 +-#define GCC_CAMSS_CPP_AHB_CLK 28 +-#define GCC_CAMSS_CPP_AXI_CLK 29 +-#define GCC_CAMSS_CPP_CLK 30 +-#define GCC_CAMSS_CPP_CLK_SRC 31 +-#define GCC_CAMSS_CPP_VBIF_AHB_CLK 32 +-#define GCC_CAMSS_CSI0_AHB_CLK 33 +-#define GCC_CAMSS_CSI0_CLK 34 +-#define GCC_CAMSS_CSI0_CLK_SRC 35 +-#define GCC_CAMSS_CSI0PHYTIMER_CLK 36 +-#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 37 +-#define GCC_CAMSS_CSI0PIX_CLK 38 +-#define GCC_CAMSS_CSI0RDI_CLK 39 +-#define GCC_CAMSS_CSI1_AHB_CLK 40 +-#define GCC_CAMSS_CSI1_CLK 41 +-#define GCC_CAMSS_CSI1_CLK_SRC 42 +-#define GCC_CAMSS_CSI1PHYTIMER_CLK 43 +-#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 44 +-#define GCC_CAMSS_CSI1PIX_CLK 45 +-#define GCC_CAMSS_CSI1RDI_CLK 46 +-#define GCC_CAMSS_CSI2_AHB_CLK 47 +-#define GCC_CAMSS_CSI2_CLK 48 +-#define GCC_CAMSS_CSI2_CLK_SRC 49 +-#define GCC_CAMSS_CSI2PHYTIMER_CLK 50 +-#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC 51 +-#define GCC_CAMSS_CSI2PIX_CLK 52 +-#define GCC_CAMSS_CSI2RDI_CLK 53 +-#define GCC_CAMSS_CSI3_AHB_CLK 54 +-#define GCC_CAMSS_CSI3_CLK 55 +-#define GCC_CAMSS_CSI3_CLK_SRC 56 +-#define GCC_CAMSS_CSI3PIX_CLK 57 +-#define GCC_CAMSS_CSI3RDI_CLK 58 +-#define GCC_CAMSS_CSI_VFE0_CLK 59 +-#define GCC_CAMSS_CSI_VFE1_CLK 60 +-#define GCC_CAMSS_CSIPHY0_CLK 61 +-#define GCC_CAMSS_CSIPHY1_CLK 62 +-#define GCC_CAMSS_CSIPHY2_CLK 63 +-#define GCC_CAMSS_CSIPHY_CLK_SRC 64 +-#define GCC_CAMSS_GP0_CLK 65 +-#define GCC_CAMSS_GP0_CLK_SRC 66 +-#define GCC_CAMSS_GP1_CLK 67 +-#define GCC_CAMSS_GP1_CLK_SRC 68 +-#define GCC_CAMSS_ISPIF_AHB_CLK 69 +-#define GCC_CAMSS_JPEG_AHB_CLK 70 +-#define GCC_CAMSS_JPEG_AXI_CLK 71 +-#define GCC_CAMSS_JPEG_CLK 72 +-#define GCC_CAMSS_JPEG_CLK_SRC 73 +-#define GCC_CAMSS_MCLK0_CLK 74 +-#define GCC_CAMSS_MCLK0_CLK_SRC 75 +-#define GCC_CAMSS_MCLK1_CLK 76 +-#define GCC_CAMSS_MCLK1_CLK_SRC 77 +-#define GCC_CAMSS_MCLK2_CLK 78 +-#define GCC_CAMSS_MCLK2_CLK_SRC 79 +-#define GCC_CAMSS_MCLK3_CLK 80 +-#define GCC_CAMSS_MCLK3_CLK_SRC 81 +-#define GCC_CAMSS_MICRO_AHB_CLK 82 +-#define GCC_CAMSS_THROTTLE_NRT_AXI_CLK 83 +-#define GCC_CAMSS_THROTTLE_RT_AXI_CLK 84 +-#define GCC_CAMSS_TOP_AHB_CLK 85 +-#define GCC_CAMSS_VFE0_AHB_CLK 86 +-#define GCC_CAMSS_VFE0_CLK 87 +-#define GCC_CAMSS_VFE0_CLK_SRC 88 +-#define GCC_CAMSS_VFE0_STREAM_CLK 89 +-#define GCC_CAMSS_VFE1_AHB_CLK 90 +-#define GCC_CAMSS_VFE1_CLK 91 +-#define GCC_CAMSS_VFE1_CLK_SRC 92 +-#define GCC_CAMSS_VFE1_STREAM_CLK 93 +-#define GCC_CAMSS_VFE_TSCTR_CLK 94 +-#define GCC_CAMSS_VFE_VBIF_AHB_CLK 95 +-#define GCC_CAMSS_VFE_VBIF_AXI_CLK 96 +-#define GCC_CE1_AHB_CLK 97 +-#define GCC_CE1_AXI_CLK 98 +-#define GCC_CE1_CLK 99 +-#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 100 +-#define GCC_CPUSS_GNOC_CLK 101 +-#define GCC_DISP_AHB_CLK 102 +-#define GCC_DISP_GPLL0_DIV_CLK_SRC 103 +-#define GCC_DISP_HF_AXI_CLK 104 +-#define GCC_DISP_THROTTLE_CORE_CLK 105 +-#define GCC_DISP_XO_CLK 106 +-#define GCC_GP1_CLK 107 +-#define GCC_GP1_CLK_SRC 108 +-#define GCC_GP2_CLK 109 +-#define GCC_GP2_CLK_SRC 110 +-#define GCC_GP3_CLK 111 +-#define GCC_GP3_CLK_SRC 112 +-#define GCC_GPU_CFG_AHB_CLK 113 +-#define GCC_GPU_GPLL0_CLK_SRC 114 +-#define GCC_GPU_GPLL0_DIV_CLK_SRC 115 +-#define GCC_GPU_MEMNOC_GFX_CLK 116 +-#define GCC_GPU_SNOC_DVM_GFX_CLK 117 +-#define GCC_GPU_THROTTLE_CORE_CLK 118 +-#define GCC_GPU_THROTTLE_XO_CLK 119 +-#define GCC_MSS_VS_CLK 120 +-#define GCC_PDM2_CLK 121 +-#define GCC_PDM2_CLK_SRC 122 +-#define GCC_PDM_AHB_CLK 123 +-#define GCC_PDM_XO4_CLK 124 +-#define GCC_PRNG_AHB_CLK 125 +-#define GCC_QMIP_CAMERA_NRT_AHB_CLK 126 +-#define GCC_QMIP_CAMERA_RT_AHB_CLK 127 +-#define GCC_QMIP_DISP_AHB_CLK 128 +-#define GCC_QMIP_GPU_CFG_AHB_CLK 129 +-#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 130 +-#define GCC_QUPV3_WRAP0_CORE_2X_CLK 131 +-#define GCC_QUPV3_WRAP0_CORE_CLK 132 +-#define GCC_QUPV3_WRAP0_S0_CLK 133 +-#define GCC_QUPV3_WRAP0_S0_CLK_SRC 134 +-#define GCC_QUPV3_WRAP0_S1_CLK 135 +-#define GCC_QUPV3_WRAP0_S1_CLK_SRC 136 +-#define GCC_QUPV3_WRAP0_S2_CLK 137 +-#define GCC_QUPV3_WRAP0_S2_CLK_SRC 138 +-#define GCC_QUPV3_WRAP0_S3_CLK 139 +-#define GCC_QUPV3_WRAP0_S3_CLK_SRC 140 +-#define GCC_QUPV3_WRAP0_S4_CLK 141 +-#define GCC_QUPV3_WRAP0_S4_CLK_SRC 142 +-#define GCC_QUPV3_WRAP0_S5_CLK 143 +-#define GCC_QUPV3_WRAP0_S5_CLK_SRC 144 +-#define GCC_QUPV3_WRAP1_CORE_2X_CLK 145 +-#define GCC_QUPV3_WRAP1_CORE_CLK 146 +-#define GCC_QUPV3_WRAP1_S0_CLK 147 +-#define GCC_QUPV3_WRAP1_S0_CLK_SRC 148 +-#define GCC_QUPV3_WRAP1_S1_CLK 149 +-#define GCC_QUPV3_WRAP1_S1_CLK_SRC 150 +-#define GCC_QUPV3_WRAP1_S2_CLK 151 +-#define GCC_QUPV3_WRAP1_S2_CLK_SRC 152 +-#define GCC_QUPV3_WRAP1_S3_CLK 153 +-#define GCC_QUPV3_WRAP1_S3_CLK_SRC 154 +-#define GCC_QUPV3_WRAP1_S4_CLK 155 +-#define GCC_QUPV3_WRAP1_S4_CLK_SRC 156 +-#define GCC_QUPV3_WRAP1_S5_CLK 157 +-#define GCC_QUPV3_WRAP1_S5_CLK_SRC 158 +-#define GCC_QUPV3_WRAP_0_M_AHB_CLK 159 +-#define GCC_QUPV3_WRAP_0_S_AHB_CLK 160 +-#define GCC_QUPV3_WRAP_1_M_AHB_CLK 161 +-#define GCC_QUPV3_WRAP_1_S_AHB_CLK 162 +-#define GCC_SDCC1_AHB_CLK 163 +-#define GCC_SDCC1_APPS_CLK 164 +-#define GCC_SDCC1_APPS_CLK_SRC 165 +-#define GCC_SDCC1_ICE_CORE_CLK 166 +-#define GCC_SDCC1_ICE_CORE_CLK_SRC 167 +-#define GCC_SDCC2_AHB_CLK 168 +-#define GCC_SDCC2_APPS_CLK 169 +-#define GCC_SDCC2_APPS_CLK_SRC 170 +-#define GCC_SYS_NOC_CPUSS_AHB_CLK 171 +-#define GCC_SYS_NOC_UFS_PHY_AXI_CLK 172 +-#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 173 +-#define GCC_UFS_PHY_AHB_CLK 174 +-#define GCC_UFS_PHY_AXI_CLK 175 +-#define GCC_UFS_PHY_AXI_CLK_SRC 176 +-#define GCC_UFS_PHY_ICE_CORE_CLK 177 +-#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 178 +-#define GCC_UFS_PHY_PHY_AUX_CLK 179 +-#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 180 +-#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 181 +-#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 182 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK 183 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 184 +-#define GCC_USB30_PRIM_MASTER_CLK 185 +-#define GCC_USB30_PRIM_MASTER_CLK_SRC 186 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK 187 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 188 +-#define GCC_USB30_PRIM_SLEEP_CLK 189 +-#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 190 +-#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 191 +-#define GCC_USB3_PRIM_PHY_PIPE_CLK 192 +-#define GCC_VDDA_VS_CLK 193 +-#define GCC_VDDCX_VS_CLK 194 +-#define GCC_VDDMX_VS_CLK 195 +-#define GCC_VIDEO_AHB_CLK 196 +-#define GCC_VIDEO_AXI0_CLK 197 +-#define GCC_VIDEO_THROTTLE_CORE_CLK 198 +-#define GCC_VIDEO_XO_CLK 199 +-#define GCC_VS_CTRL_AHB_CLK 200 +-#define GCC_VS_CTRL_CLK 201 +-#define GCC_VS_CTRL_CLK_SRC 202 +-#define GCC_VSENSOR_CLK_SRC 203 +-#define GCC_WCSS_VS_CLK 204 +-#define GCC_USB3_PRIM_CLKREF_CLK 205 +-#define GCC_SYS_NOC_COMPUTE_SF_AXI_CLK 206 +-#define GCC_BIMC_GPU_AXI_CLK 207 +-#define GCC_UFS_MEM_CLKREF_CLK 208 +- +-/* GDSCs */ +-#define USB30_PRIM_GDSC 0 +-#define UFS_PHY_GDSC 1 +-#define CAMSS_VFE0_GDSC 2 +-#define CAMSS_VFE1_GDSC 3 +-#define CAMSS_TOP_GDSC 4 +-#define CAM_CPP_GDSC 5 +-#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 6 +-#define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC 7 +-#define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC 8 +-#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 9 +- +-#define GCC_QUSB2PHY_PRIM_BCR 0 +-#define GCC_QUSB2PHY_SEC_BCR 1 +-#define GCC_UFS_PHY_BCR 2 +-#define GCC_USB30_PRIM_BCR 3 +-#define GCC_USB_PHY_CFG_AHB2PHY_BCR 4 +-#define GCC_USB3_PHY_PRIM_SP0_BCR 5 +-#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 6 +-#define GCC_CAMSS_MICRO_BCR 7 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sm6350.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sm6350.h +deleted file mode 100644 +index ba584ca33c39..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sm6350.h ++++ /dev/null +@@ -1,178 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +-/* +- * Copyright (c) 2021, The Linux Foundation. All rights reserved. +- * Copyright (c) 2021, Konrad Dybcio +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6350_H +-#define _DT_BINDINGS_CLK_QCOM_GCC_SM6350_H +- +-/* GCC clocks */ +-#define GPLL0 0 +-#define GPLL0_OUT_EVEN 1 +-#define GPLL0_OUT_ODD 2 +-#define GPLL6 3 +-#define GPLL6_OUT_EVEN 4 +-#define GPLL7 5 +-#define GCC_AGGRE_CNOC_PERIPH_CENTER_AHB_CLK 6 +-#define GCC_AGGRE_NOC_CENTER_AHB_CLK 7 +-#define GCC_AGGRE_NOC_PCIE_SF_AXI_CLK 8 +-#define GCC_AGGRE_NOC_PCIE_TBU_CLK 9 +-#define GCC_AGGRE_NOC_WLAN_AXI_CLK 10 +-#define GCC_AGGRE_UFS_PHY_AXI_CLK 11 +-#define GCC_AGGRE_USB3_PRIM_AXI_CLK 12 +-#define GCC_BOOT_ROM_AHB_CLK 13 +-#define GCC_CAMERA_AHB_CLK 14 +-#define GCC_CAMERA_AXI_CLK 15 +-#define GCC_CAMERA_THROTTLE_NRT_AXI_CLK 16 +-#define GCC_CAMERA_THROTTLE_RT_AXI_CLK 17 +-#define GCC_CAMERA_XO_CLK 18 +-#define GCC_CE1_AHB_CLK 19 +-#define GCC_CE1_AXI_CLK 20 +-#define GCC_CE1_CLK 21 +-#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 22 +-#define GCC_CPUSS_AHB_CLK 23 +-#define GCC_CPUSS_AHB_CLK_SRC 24 +-#define GCC_CPUSS_AHB_DIV_CLK_SRC 25 +-#define GCC_CPUSS_GNOC_CLK 26 +-#define GCC_CPUSS_RBCPR_CLK 27 +-#define GCC_DDRSS_GPU_AXI_CLK 28 +-#define GCC_DISP_AHB_CLK 29 +-#define GCC_DISP_AXI_CLK 30 +-#define GCC_DISP_CC_SLEEP_CLK 31 +-#define GCC_DISP_CC_XO_CLK 32 +-#define GCC_DISP_GPLL0_CLK 33 +-#define GCC_DISP_THROTTLE_AXI_CLK 34 +-#define GCC_DISP_XO_CLK 35 +-#define GCC_GP1_CLK 36 +-#define GCC_GP1_CLK_SRC 37 +-#define GCC_GP2_CLK 38 +-#define GCC_GP2_CLK_SRC 39 +-#define GCC_GP3_CLK 40 +-#define GCC_GP3_CLK_SRC 41 +-#define GCC_GPU_CFG_AHB_CLK 42 +-#define GCC_GPU_GPLL0_CLK 43 +-#define GCC_GPU_GPLL0_DIV_CLK 44 +-#define GCC_GPU_MEMNOC_GFX_CLK 45 +-#define GCC_GPU_SNOC_DVM_GFX_CLK 46 +-#define GCC_NPU_AXI_CLK 47 +-#define GCC_NPU_BWMON_AXI_CLK 48 +-#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 49 +-#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 50 +-#define GCC_NPU_CFG_AHB_CLK 51 +-#define GCC_NPU_DMA_CLK 52 +-#define GCC_NPU_GPLL0_CLK 53 +-#define GCC_NPU_GPLL0_DIV_CLK 54 +-#define GCC_PCIE_0_AUX_CLK 55 +-#define GCC_PCIE_0_AUX_CLK_SRC 56 +-#define GCC_PCIE_0_CFG_AHB_CLK 57 +-#define GCC_PCIE_0_MSTR_AXI_CLK 58 +-#define GCC_PCIE_0_PIPE_CLK 59 +-#define GCC_PCIE_0_SLV_AXI_CLK 60 +-#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 61 +-#define GCC_PCIE_PHY_RCHNG_CLK 62 +-#define GCC_PCIE_PHY_RCHNG_CLK_SRC 63 +-#define GCC_PDM2_CLK 64 +-#define GCC_PDM2_CLK_SRC 65 +-#define GCC_PDM_AHB_CLK 66 +-#define GCC_PDM_XO4_CLK 67 +-#define GCC_PRNG_AHB_CLK 68 +-#define GCC_QUPV3_WRAP0_CORE_2X_CLK 69 +-#define GCC_QUPV3_WRAP0_CORE_CLK 70 +-#define GCC_QUPV3_WRAP0_S0_CLK 71 +-#define GCC_QUPV3_WRAP0_S0_CLK_SRC 72 +-#define GCC_QUPV3_WRAP0_S1_CLK 73 +-#define GCC_QUPV3_WRAP0_S1_CLK_SRC 74 +-#define GCC_QUPV3_WRAP0_S2_CLK 75 +-#define GCC_QUPV3_WRAP0_S2_CLK_SRC 76 +-#define GCC_QUPV3_WRAP0_S3_CLK 77 +-#define GCC_QUPV3_WRAP0_S3_CLK_SRC 78 +-#define GCC_QUPV3_WRAP0_S4_CLK 79 +-#define GCC_QUPV3_WRAP0_S4_CLK_SRC 80 +-#define GCC_QUPV3_WRAP0_S5_CLK 81 +-#define GCC_QUPV3_WRAP0_S5_CLK_SRC 82 +-#define GCC_QUPV3_WRAP1_CORE_2X_CLK 83 +-#define GCC_QUPV3_WRAP1_CORE_CLK 84 +-#define GCC_QUPV3_WRAP1_S0_CLK 85 +-#define GCC_QUPV3_WRAP1_S0_CLK_SRC 86 +-#define GCC_QUPV3_WRAP1_S1_CLK 87 +-#define GCC_QUPV3_WRAP1_S1_CLK_SRC 88 +-#define GCC_QUPV3_WRAP1_S2_CLK 89 +-#define GCC_QUPV3_WRAP1_S2_CLK_SRC 90 +-#define GCC_QUPV3_WRAP1_S3_CLK 91 +-#define GCC_QUPV3_WRAP1_S3_CLK_SRC 92 +-#define GCC_QUPV3_WRAP1_S4_CLK 93 +-#define GCC_QUPV3_WRAP1_S4_CLK_SRC 94 +-#define GCC_QUPV3_WRAP1_S5_CLK 95 +-#define GCC_QUPV3_WRAP1_S5_CLK_SRC 96 +-#define GCC_QUPV3_WRAP_0_M_AHB_CLK 97 +-#define GCC_QUPV3_WRAP_0_S_AHB_CLK 98 +-#define GCC_QUPV3_WRAP_1_M_AHB_CLK 99 +-#define GCC_QUPV3_WRAP_1_S_AHB_CLK 100 +-#define GCC_SDCC1_AHB_CLK 101 +-#define GCC_SDCC1_APPS_CLK 102 +-#define GCC_SDCC1_APPS_CLK_SRC 103 +-#define GCC_SDCC1_ICE_CORE_CLK 104 +-#define GCC_SDCC1_ICE_CORE_CLK_SRC 105 +-#define GCC_SDCC2_AHB_CLK 106 +-#define GCC_SDCC2_APPS_CLK 107 +-#define GCC_SDCC2_APPS_CLK_SRC 108 +-#define GCC_SYS_NOC_CPUSS_AHB_CLK 109 +-#define GCC_UFS_MEM_CLKREF_CLK 110 +-#define GCC_UFS_PHY_AHB_CLK 111 +-#define GCC_UFS_PHY_AXI_CLK 112 +-#define GCC_UFS_PHY_AXI_CLK_SRC 113 +-#define GCC_UFS_PHY_ICE_CORE_CLK 114 +-#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 115 +-#define GCC_UFS_PHY_PHY_AUX_CLK 116 +-#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 117 +-#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 118 +-#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 119 +-#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 120 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK 121 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 122 +-#define GCC_USB30_PRIM_MASTER_CLK 123 +-#define GCC_USB30_PRIM_MASTER_CLK_SRC 124 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK 125 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 126 +-#define GCC_USB30_PRIM_MOCK_UTMI_DIV_CLK_SRC 127 +-#define GCC_USB3_PRIM_CLKREF_CLK 128 +-#define GCC_USB30_PRIM_SLEEP_CLK 129 +-#define GCC_USB3_PRIM_PHY_AUX_CLK 130 +-#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 131 +-#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 132 +-#define GCC_USB3_PRIM_PHY_PIPE_CLK 133 +-#define GCC_VIDEO_AHB_CLK 134 +-#define GCC_VIDEO_AXI_CLK 135 +-#define GCC_VIDEO_THROTTLE_AXI_CLK 136 +-#define GCC_VIDEO_XO_CLK 137 +-#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 138 +-#define GCC_UFS_PHY_AXI_HW_CTL_CLK 139 +-#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 140 +-#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 141 +-#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 142 +-#define GCC_RX5_PCIE_CLKREF_CLK 143 +-#define GCC_GPU_GPLL0_MAIN_DIV_CLK_SRC 144 +-#define GCC_NPU_PLL0_MAIN_DIV_CLK_SRC 145 +- +-/* GCC resets */ +-#define GCC_QUSB2PHY_PRIM_BCR 0 +-#define GCC_QUSB2PHY_SEC_BCR 1 +-#define GCC_SDCC1_BCR 2 +-#define GCC_SDCC2_BCR 3 +-#define GCC_UFS_PHY_BCR 4 +-#define GCC_USB30_PRIM_BCR 5 +-#define GCC_PCIE_0_BCR 6 +-#define GCC_PCIE_0_PHY_BCR 7 +-#define GCC_QUPV3_WRAPPER_0_BCR 8 +-#define GCC_QUPV3_WRAPPER_1_BCR 9 +-#define GCC_USB3_PHY_PRIM_BCR 10 +-#define GCC_USB3_DP_PHY_PRIM_BCR 11 +- +-/* GCC GDSCs */ +-#define USB30_PRIM_GDSC 0 +-#define UFS_PHY_GDSC 1 +-#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2 +-#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sm8150.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sm8150.h +deleted file mode 100644 +index 3e1a91876610..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sm8150.h ++++ /dev/null +@@ -1,247 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2019, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H +-#define _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H +- +-/* GCC clocks */ +-#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 +-#define GCC_AGGRE_UFS_CARD_AXI_CLK 1 +-#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 2 +-#define GCC_AGGRE_UFS_PHY_AXI_CLK 3 +-#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 4 +-#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5 +-#define GCC_AGGRE_USB3_SEC_AXI_CLK 6 +-#define GCC_BOOT_ROM_AHB_CLK 7 +-#define GCC_CAMERA_AHB_CLK 8 +-#define GCC_CAMERA_HF_AXI_CLK 9 +-#define GCC_CAMERA_SF_AXI_CLK 10 +-#define GCC_CAMERA_XO_CLK 11 +-#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 +-#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 +-#define GCC_CPUSS_AHB_CLK 14 +-#define GCC_CPUSS_AHB_CLK_SRC 15 +-#define GCC_CPUSS_DVM_BUS_CLK 16 +-#define GCC_CPUSS_GNOC_CLK 17 +-#define GCC_CPUSS_RBCPR_CLK 18 +-#define GCC_DDRSS_GPU_AXI_CLK 19 +-#define GCC_DISP_AHB_CLK 20 +-#define GCC_DISP_HF_AXI_CLK 21 +-#define GCC_DISP_SF_AXI_CLK 22 +-#define GCC_DISP_XO_CLK 23 +-#define GCC_EMAC_AXI_CLK 24 +-#define GCC_EMAC_PTP_CLK 25 +-#define GCC_EMAC_PTP_CLK_SRC 26 +-#define GCC_EMAC_RGMII_CLK 27 +-#define GCC_EMAC_RGMII_CLK_SRC 28 +-#define GCC_EMAC_SLV_AHB_CLK 29 +-#define GCC_GP1_CLK 30 +-#define GCC_GP1_CLK_SRC 31 +-#define GCC_GP2_CLK 32 +-#define GCC_GP2_CLK_SRC 33 +-#define GCC_GP3_CLK 34 +-#define GCC_GP3_CLK_SRC 35 +-#define GCC_GPU_CFG_AHB_CLK 36 +-#define GCC_GPU_GPLL0_CLK_SRC 37 +-#define GCC_GPU_GPLL0_DIV_CLK_SRC 38 +-#define GCC_GPU_IREF_CLK 39 +-#define GCC_GPU_MEMNOC_GFX_CLK 40 +-#define GCC_GPU_SNOC_DVM_GFX_CLK 41 +-#define GCC_NPU_AT_CLK 42 +-#define GCC_NPU_AXI_CLK 43 +-#define GCC_NPU_CFG_AHB_CLK 44 +-#define GCC_NPU_GPLL0_CLK_SRC 45 +-#define GCC_NPU_GPLL0_DIV_CLK_SRC 46 +-#define GCC_NPU_TRIG_CLK 47 +-#define GCC_PCIE0_PHY_REFGEN_CLK 48 +-#define GCC_PCIE1_PHY_REFGEN_CLK 49 +-#define GCC_PCIE_0_AUX_CLK 50 +-#define GCC_PCIE_0_AUX_CLK_SRC 51 +-#define GCC_PCIE_0_CFG_AHB_CLK 52 +-#define GCC_PCIE_0_CLKREF_CLK 53 +-#define GCC_PCIE_0_MSTR_AXI_CLK 54 +-#define GCC_PCIE_0_PIPE_CLK 55 +-#define GCC_PCIE_0_SLV_AXI_CLK 56 +-#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57 +-#define GCC_PCIE_1_AUX_CLK 58 +-#define GCC_PCIE_1_AUX_CLK_SRC 59 +-#define GCC_PCIE_1_CFG_AHB_CLK 60 +-#define GCC_PCIE_1_CLKREF_CLK 61 +-#define GCC_PCIE_1_MSTR_AXI_CLK 62 +-#define GCC_PCIE_1_PIPE_CLK 63 +-#define GCC_PCIE_1_SLV_AXI_CLK 64 +-#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 65 +-#define GCC_PCIE_PHY_AUX_CLK 66 +-#define GCC_PCIE_PHY_REFGEN_CLK_SRC 67 +-#define GCC_PDM2_CLK 68 +-#define GCC_PDM2_CLK_SRC 69 +-#define GCC_PDM_AHB_CLK 70 +-#define GCC_PDM_XO4_CLK 71 +-#define GCC_PRNG_AHB_CLK 72 +-#define GCC_QMIP_CAMERA_NRT_AHB_CLK 73 +-#define GCC_QMIP_CAMERA_RT_AHB_CLK 74 +-#define GCC_QMIP_DISP_AHB_CLK 75 +-#define GCC_QMIP_VIDEO_CVP_AHB_CLK 76 +-#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 77 +-#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 78 +-#define GCC_QSPI_CORE_CLK 79 +-#define GCC_QSPI_CORE_CLK_SRC 80 +-#define GCC_QUPV3_WRAP0_S0_CLK 81 +-#define GCC_QUPV3_WRAP0_S0_CLK_SRC 82 +-#define GCC_QUPV3_WRAP0_S1_CLK 83 +-#define GCC_QUPV3_WRAP0_S1_CLK_SRC 84 +-#define GCC_QUPV3_WRAP0_S2_CLK 85 +-#define GCC_QUPV3_WRAP0_S2_CLK_SRC 86 +-#define GCC_QUPV3_WRAP0_S3_CLK 87 +-#define GCC_QUPV3_WRAP0_S3_CLK_SRC 88 +-#define GCC_QUPV3_WRAP0_S4_CLK 89 +-#define GCC_QUPV3_WRAP0_S4_CLK_SRC 90 +-#define GCC_QUPV3_WRAP0_S5_CLK 91 +-#define GCC_QUPV3_WRAP0_S5_CLK_SRC 92 +-#define GCC_QUPV3_WRAP0_S6_CLK 93 +-#define GCC_QUPV3_WRAP0_S6_CLK_SRC 94 +-#define GCC_QUPV3_WRAP0_S7_CLK 95 +-#define GCC_QUPV3_WRAP0_S7_CLK_SRC 96 +-#define GCC_QUPV3_WRAP1_S0_CLK 97 +-#define GCC_QUPV3_WRAP1_S0_CLK_SRC 98 +-#define GCC_QUPV3_WRAP1_S1_CLK 99 +-#define GCC_QUPV3_WRAP1_S1_CLK_SRC 100 +-#define GCC_QUPV3_WRAP1_S2_CLK 101 +-#define GCC_QUPV3_WRAP1_S2_CLK_SRC 102 +-#define GCC_QUPV3_WRAP1_S3_CLK 103 +-#define GCC_QUPV3_WRAP1_S3_CLK_SRC 104 +-#define GCC_QUPV3_WRAP1_S4_CLK 105 +-#define GCC_QUPV3_WRAP1_S4_CLK_SRC 106 +-#define GCC_QUPV3_WRAP1_S5_CLK 107 +-#define GCC_QUPV3_WRAP1_S5_CLK_SRC 108 +-#define GCC_QUPV3_WRAP2_S0_CLK 109 +-#define GCC_QUPV3_WRAP2_S0_CLK_SRC 110 +-#define GCC_QUPV3_WRAP2_S1_CLK 111 +-#define GCC_QUPV3_WRAP2_S1_CLK_SRC 112 +-#define GCC_QUPV3_WRAP2_S2_CLK 113 +-#define GCC_QUPV3_WRAP2_S2_CLK_SRC 114 +-#define GCC_QUPV3_WRAP2_S3_CLK 115 +-#define GCC_QUPV3_WRAP2_S3_CLK_SRC 116 +-#define GCC_QUPV3_WRAP2_S4_CLK 117 +-#define GCC_QUPV3_WRAP2_S4_CLK_SRC 118 +-#define GCC_QUPV3_WRAP2_S5_CLK 119 +-#define GCC_QUPV3_WRAP2_S5_CLK_SRC 120 +-#define GCC_QUPV3_WRAP_0_M_AHB_CLK 121 +-#define GCC_QUPV3_WRAP_0_S_AHB_CLK 122 +-#define GCC_QUPV3_WRAP_1_M_AHB_CLK 123 +-#define GCC_QUPV3_WRAP_1_S_AHB_CLK 124 +-#define GCC_QUPV3_WRAP_2_M_AHB_CLK 125 +-#define GCC_QUPV3_WRAP_2_S_AHB_CLK 126 +-#define GCC_SDCC2_AHB_CLK 127 +-#define GCC_SDCC2_APPS_CLK 128 +-#define GCC_SDCC2_APPS_CLK_SRC 129 +-#define GCC_SDCC4_AHB_CLK 130 +-#define GCC_SDCC4_APPS_CLK 131 +-#define GCC_SDCC4_APPS_CLK_SRC 132 +-#define GCC_SYS_NOC_CPUSS_AHB_CLK 133 +-#define GCC_TSIF_AHB_CLK 134 +-#define GCC_TSIF_INACTIVITY_TIMERS_CLK 135 +-#define GCC_TSIF_REF_CLK 136 +-#define GCC_TSIF_REF_CLK_SRC 137 +-#define GCC_UFS_CARD_AHB_CLK 138 +-#define GCC_UFS_CARD_AXI_CLK 139 +-#define GCC_UFS_CARD_AXI_CLK_SRC 140 +-#define GCC_UFS_CARD_AXI_HW_CTL_CLK 141 +-#define GCC_UFS_CARD_CLKREF_CLK 142 +-#define GCC_UFS_CARD_ICE_CORE_CLK 143 +-#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 144 +-#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 145 +-#define GCC_UFS_CARD_PHY_AUX_CLK 146 +-#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 147 +-#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 148 +-#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 149 +-#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 150 +-#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 151 +-#define GCC_UFS_CARD_UNIPRO_CORE_CLK 152 +-#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 153 +-#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 154 +-#define GCC_UFS_MEM_CLKREF_CLK 155 +-#define GCC_UFS_PHY_AHB_CLK 156 +-#define GCC_UFS_PHY_AXI_CLK 157 +-#define GCC_UFS_PHY_AXI_CLK_SRC 158 +-#define GCC_UFS_PHY_AXI_HW_CTL_CLK 159 +-#define GCC_UFS_PHY_ICE_CORE_CLK 160 +-#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 161 +-#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 162 +-#define GCC_UFS_PHY_PHY_AUX_CLK 163 +-#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 164 +-#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 165 +-#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 166 +-#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 167 +-#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 168 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK 169 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 170 +-#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 171 +-#define GCC_USB30_PRIM_MASTER_CLK 172 +-#define GCC_USB30_PRIM_MASTER_CLK_SRC 173 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK 174 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 175 +-#define GCC_USB30_PRIM_SLEEP_CLK 176 +-#define GCC_USB30_SEC_MASTER_CLK 177 +-#define GCC_USB30_SEC_MASTER_CLK_SRC 178 +-#define GCC_USB30_SEC_MOCK_UTMI_CLK 179 +-#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 180 +-#define GCC_USB30_SEC_SLEEP_CLK 181 +-#define GCC_USB3_PRIM_CLKREF_CLK 182 +-#define GCC_USB3_PRIM_PHY_AUX_CLK 183 +-#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 184 +-#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 185 +-#define GCC_USB3_PRIM_PHY_PIPE_CLK 186 +-#define GCC_USB3_SEC_CLKREF_CLK 187 +-#define GCC_USB3_SEC_PHY_AUX_CLK 188 +-#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 189 +-#define GCC_USB3_SEC_PHY_COM_AUX_CLK 190 +-#define GCC_USB3_SEC_PHY_PIPE_CLK 191 +-#define GCC_VIDEO_AHB_CLK 192 +-#define GCC_VIDEO_AXI0_CLK 193 +-#define GCC_VIDEO_AXI1_CLK 194 +-#define GCC_VIDEO_AXIC_CLK 195 +-#define GCC_VIDEO_XO_CLK 196 +-#define GPLL0 197 +-#define GPLL0_OUT_EVEN 198 +-#define GPLL7 199 +-#define GPLL9 200 +- +-/* Reset clocks */ +-#define GCC_EMAC_BCR 0 +-#define GCC_GPU_BCR 1 +-#define GCC_MMSS_BCR 2 +-#define GCC_NPU_BCR 3 +-#define GCC_PCIE_0_BCR 4 +-#define GCC_PCIE_0_PHY_BCR 5 +-#define GCC_PCIE_1_BCR 6 +-#define GCC_PCIE_1_PHY_BCR 7 +-#define GCC_PCIE_PHY_BCR 8 +-#define GCC_PDM_BCR 9 +-#define GCC_PRNG_BCR 10 +-#define GCC_QSPI_BCR 11 +-#define GCC_QUPV3_WRAPPER_0_BCR 12 +-#define GCC_QUPV3_WRAPPER_1_BCR 13 +-#define GCC_QUPV3_WRAPPER_2_BCR 14 +-#define GCC_QUSB2PHY_PRIM_BCR 15 +-#define GCC_QUSB2PHY_SEC_BCR 16 +-#define GCC_USB3_PHY_PRIM_BCR 17 +-#define GCC_USB3_DP_PHY_PRIM_BCR 18 +-#define GCC_USB3_PHY_SEC_BCR 19 +-#define GCC_USB3PHY_PHY_SEC_BCR 20 +-#define GCC_SDCC2_BCR 21 +-#define GCC_SDCC4_BCR 22 +-#define GCC_TSIF_BCR 23 +-#define GCC_UFS_CARD_BCR 24 +-#define GCC_UFS_PHY_BCR 25 +-#define GCC_USB30_PRIM_BCR 26 +-#define GCC_USB30_SEC_BCR 27 +-#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 +- +-/* GCC GDSCRs */ +-#define USB30_PRIM_GDSC 4 +-#define USB30_SEC_GDSC 5 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sm8250.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sm8250.h +deleted file mode 100644 +index 7b7abe327e37..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sm8250.h ++++ /dev/null +@@ -1,271 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H +-#define _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H +- +-/* GCC clocks */ +-#define GPLL0 0 +-#define GPLL0_OUT_EVEN 1 +-#define GPLL4 2 +-#define GPLL9 3 +-#define GCC_AGGRE_NOC_PCIE_TBU_CLK 4 +-#define GCC_AGGRE_UFS_CARD_AXI_CLK 5 +-#define GCC_AGGRE_UFS_PHY_AXI_CLK 6 +-#define GCC_AGGRE_USB3_PRIM_AXI_CLK 7 +-#define GCC_AGGRE_USB3_SEC_AXI_CLK 8 +-#define GCC_BOOT_ROM_AHB_CLK 9 +-#define GCC_CAMERA_AHB_CLK 10 +-#define GCC_CAMERA_HF_AXI_CLK 11 +-#define GCC_CAMERA_SF_AXI_CLK 12 +-#define GCC_CAMERA_XO_CLK 13 +-#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 14 +-#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 15 +-#define GCC_CPUSS_AHB_CLK 16 +-#define GCC_CPUSS_AHB_CLK_SRC 17 +-#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 18 +-#define GCC_CPUSS_DVM_BUS_CLK 19 +-#define GCC_CPUSS_RBCPR_CLK 20 +-#define GCC_DDRSS_GPU_AXI_CLK 21 +-#define GCC_DDRSS_PCIE_SF_TBU_CLK 22 +-#define GCC_DISP_AHB_CLK 23 +-#define GCC_DISP_HF_AXI_CLK 24 +-#define GCC_DISP_SF_AXI_CLK 25 +-#define GCC_DISP_XO_CLK 26 +-#define GCC_GP1_CLK 27 +-#define GCC_GP1_CLK_SRC 28 +-#define GCC_GP2_CLK 29 +-#define GCC_GP2_CLK_SRC 30 +-#define GCC_GP3_CLK 31 +-#define GCC_GP3_CLK_SRC 32 +-#define GCC_GPU_CFG_AHB_CLK 33 +-#define GCC_GPU_GPLL0_CLK_SRC 34 +-#define GCC_GPU_GPLL0_DIV_CLK_SRC 35 +-#define GCC_GPU_IREF_EN 36 +-#define GCC_GPU_MEMNOC_GFX_CLK 37 +-#define GCC_GPU_SNOC_DVM_GFX_CLK 38 +-#define GCC_NPU_AXI_CLK 39 +-#define GCC_NPU_BWMON_AXI_CLK 40 +-#define GCC_NPU_BWMON_CFG_AHB_CLK 41 +-#define GCC_NPU_CFG_AHB_CLK 42 +-#define GCC_NPU_DMA_CLK 43 +-#define GCC_NPU_GPLL0_CLK_SRC 44 +-#define GCC_NPU_GPLL0_DIV_CLK_SRC 45 +-#define GCC_PCIE0_PHY_REFGEN_CLK 46 +-#define GCC_PCIE1_PHY_REFGEN_CLK 47 +-#define GCC_PCIE2_PHY_REFGEN_CLK 48 +-#define GCC_PCIE_0_AUX_CLK 49 +-#define GCC_PCIE_0_AUX_CLK_SRC 50 +-#define GCC_PCIE_0_CFG_AHB_CLK 51 +-#define GCC_PCIE_0_MSTR_AXI_CLK 52 +-#define GCC_PCIE_0_PIPE_CLK 53 +-#define GCC_PCIE_0_SLV_AXI_CLK 54 +-#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 55 +-#define GCC_PCIE_1_AUX_CLK 56 +-#define GCC_PCIE_1_AUX_CLK_SRC 57 +-#define GCC_PCIE_1_CFG_AHB_CLK 58 +-#define GCC_PCIE_1_MSTR_AXI_CLK 59 +-#define GCC_PCIE_1_PIPE_CLK 60 +-#define GCC_PCIE_1_SLV_AXI_CLK 61 +-#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 62 +-#define GCC_PCIE_2_AUX_CLK 63 +-#define GCC_PCIE_2_AUX_CLK_SRC 64 +-#define GCC_PCIE_2_CFG_AHB_CLK 65 +-#define GCC_PCIE_2_MSTR_AXI_CLK 66 +-#define GCC_PCIE_2_PIPE_CLK 67 +-#define GCC_PCIE_2_SLV_AXI_CLK 68 +-#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 69 +-#define GCC_PCIE_MDM_CLKREF_EN 70 +-#define GCC_PCIE_PHY_AUX_CLK 71 +-#define GCC_PCIE_PHY_REFGEN_CLK_SRC 72 +-#define GCC_PCIE_WIFI_CLKREF_EN 73 +-#define GCC_PCIE_WIGIG_CLKREF_EN 74 +-#define GCC_PDM2_CLK 75 +-#define GCC_PDM2_CLK_SRC 76 +-#define GCC_PDM_AHB_CLK 77 +-#define GCC_PDM_XO4_CLK 78 +-#define GCC_PRNG_AHB_CLK 79 +-#define GCC_QMIP_CAMERA_NRT_AHB_CLK 80 +-#define GCC_QMIP_CAMERA_RT_AHB_CLK 81 +-#define GCC_QMIP_DISP_AHB_CLK 82 +-#define GCC_QMIP_VIDEO_CVP_AHB_CLK 83 +-#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 84 +-#define GCC_QUPV3_WRAP0_CORE_2X_CLK 85 +-#define GCC_QUPV3_WRAP0_CORE_CLK 86 +-#define GCC_QUPV3_WRAP0_S0_CLK 87 +-#define GCC_QUPV3_WRAP0_S0_CLK_SRC 88 +-#define GCC_QUPV3_WRAP0_S1_CLK 89 +-#define GCC_QUPV3_WRAP0_S1_CLK_SRC 90 +-#define GCC_QUPV3_WRAP0_S2_CLK 91 +-#define GCC_QUPV3_WRAP0_S2_CLK_SRC 92 +-#define GCC_QUPV3_WRAP0_S3_CLK 93 +-#define GCC_QUPV3_WRAP0_S3_CLK_SRC 94 +-#define GCC_QUPV3_WRAP0_S4_CLK 95 +-#define GCC_QUPV3_WRAP0_S4_CLK_SRC 96 +-#define GCC_QUPV3_WRAP0_S5_CLK 97 +-#define GCC_QUPV3_WRAP0_S5_CLK_SRC 98 +-#define GCC_QUPV3_WRAP0_S6_CLK 99 +-#define GCC_QUPV3_WRAP0_S6_CLK_SRC 100 +-#define GCC_QUPV3_WRAP0_S7_CLK 101 +-#define GCC_QUPV3_WRAP0_S7_CLK_SRC 102 +-#define GCC_QUPV3_WRAP1_CORE_2X_CLK 103 +-#define GCC_QUPV3_WRAP1_CORE_CLK 104 +-#define GCC_QUPV3_WRAP1_S0_CLK 105 +-#define GCC_QUPV3_WRAP1_S0_CLK_SRC 106 +-#define GCC_QUPV3_WRAP1_S1_CLK 107 +-#define GCC_QUPV3_WRAP1_S1_CLK_SRC 108 +-#define GCC_QUPV3_WRAP1_S2_CLK 109 +-#define GCC_QUPV3_WRAP1_S2_CLK_SRC 110 +-#define GCC_QUPV3_WRAP1_S3_CLK 111 +-#define GCC_QUPV3_WRAP1_S3_CLK_SRC 112 +-#define GCC_QUPV3_WRAP1_S4_CLK 113 +-#define GCC_QUPV3_WRAP1_S4_CLK_SRC 114 +-#define GCC_QUPV3_WRAP1_S5_CLK 115 +-#define GCC_QUPV3_WRAP1_S5_CLK_SRC 116 +-#define GCC_QUPV3_WRAP2_CORE_2X_CLK 117 +-#define GCC_QUPV3_WRAP2_CORE_CLK 118 +-#define GCC_QUPV3_WRAP2_S0_CLK 119 +-#define GCC_QUPV3_WRAP2_S0_CLK_SRC 120 +-#define GCC_QUPV3_WRAP2_S1_CLK 121 +-#define GCC_QUPV3_WRAP2_S1_CLK_SRC 122 +-#define GCC_QUPV3_WRAP2_S2_CLK 123 +-#define GCC_QUPV3_WRAP2_S2_CLK_SRC 124 +-#define GCC_QUPV3_WRAP2_S3_CLK 125 +-#define GCC_QUPV3_WRAP2_S3_CLK_SRC 126 +-#define GCC_QUPV3_WRAP2_S4_CLK 127 +-#define GCC_QUPV3_WRAP2_S4_CLK_SRC 128 +-#define GCC_QUPV3_WRAP2_S5_CLK 129 +-#define GCC_QUPV3_WRAP2_S5_CLK_SRC 130 +-#define GCC_QUPV3_WRAP_0_M_AHB_CLK 131 +-#define GCC_QUPV3_WRAP_0_S_AHB_CLK 132 +-#define GCC_QUPV3_WRAP_1_M_AHB_CLK 133 +-#define GCC_QUPV3_WRAP_1_S_AHB_CLK 134 +-#define GCC_QUPV3_WRAP_2_M_AHB_CLK 135 +-#define GCC_QUPV3_WRAP_2_S_AHB_CLK 136 +-#define GCC_SDCC2_AHB_CLK 137 +-#define GCC_SDCC2_APPS_CLK 138 +-#define GCC_SDCC2_APPS_CLK_SRC 139 +-#define GCC_SDCC4_AHB_CLK 140 +-#define GCC_SDCC4_APPS_CLK 141 +-#define GCC_SDCC4_APPS_CLK_SRC 142 +-#define GCC_SYS_NOC_CPUSS_AHB_CLK 143 +-#define GCC_TSIF_AHB_CLK 144 +-#define GCC_TSIF_INACTIVITY_TIMERS_CLK 145 +-#define GCC_TSIF_REF_CLK 146 +-#define GCC_TSIF_REF_CLK_SRC 147 +-#define GCC_UFS_1X_CLKREF_EN 148 +-#define GCC_UFS_CARD_AHB_CLK 149 +-#define GCC_UFS_CARD_AXI_CLK 150 +-#define GCC_UFS_CARD_AXI_CLK_SRC 151 +-#define GCC_UFS_CARD_ICE_CORE_CLK 152 +-#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 153 +-#define GCC_UFS_CARD_PHY_AUX_CLK 154 +-#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 155 +-#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 156 +-#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 157 +-#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 158 +-#define GCC_UFS_CARD_UNIPRO_CORE_CLK 159 +-#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 160 +-#define GCC_UFS_PHY_AHB_CLK 161 +-#define GCC_UFS_PHY_AXI_CLK 162 +-#define GCC_UFS_PHY_AXI_CLK_SRC 163 +-#define GCC_UFS_PHY_ICE_CORE_CLK 164 +-#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 165 +-#define GCC_UFS_PHY_PHY_AUX_CLK 166 +-#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 167 +-#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 168 +-#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 169 +-#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 170 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK 171 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 172 +-#define GCC_USB30_PRIM_MASTER_CLK 173 +-#define GCC_USB30_PRIM_MASTER_CLK_SRC 174 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK 175 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 176 +-#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 177 +-#define GCC_USB30_PRIM_SLEEP_CLK 178 +-#define GCC_USB30_SEC_MASTER_CLK 179 +-#define GCC_USB30_SEC_MASTER_CLK_SRC 180 +-#define GCC_USB30_SEC_MOCK_UTMI_CLK 181 +-#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 182 +-#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 183 +-#define GCC_USB30_SEC_SLEEP_CLK 184 +-#define GCC_USB3_PRIM_PHY_AUX_CLK 185 +-#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 186 +-#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 187 +-#define GCC_USB3_PRIM_PHY_PIPE_CLK 188 +-#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 189 +-#define GCC_USB3_SEC_CLKREF_EN 190 +-#define GCC_USB3_SEC_PHY_AUX_CLK 191 +-#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 192 +-#define GCC_USB3_SEC_PHY_COM_AUX_CLK 193 +-#define GCC_USB3_SEC_PHY_PIPE_CLK 194 +-#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 195 +-#define GCC_VIDEO_AHB_CLK 196 +-#define GCC_VIDEO_AXI0_CLK 197 +-#define GCC_VIDEO_AXI1_CLK 198 +-#define GCC_VIDEO_XO_CLK 199 +- +-/* GCC resets */ +-#define GCC_GPU_BCR 0 +-#define GCC_MMSS_BCR 1 +-#define GCC_NPU_BWMON_BCR 2 +-#define GCC_NPU_BCR 3 +-#define GCC_PCIE_0_BCR 4 +-#define GCC_PCIE_0_LINK_DOWN_BCR 5 +-#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6 +-#define GCC_PCIE_0_PHY_BCR 7 +-#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8 +-#define GCC_PCIE_1_BCR 9 +-#define GCC_PCIE_1_LINK_DOWN_BCR 10 +-#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11 +-#define GCC_PCIE_1_PHY_BCR 12 +-#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13 +-#define GCC_PCIE_2_BCR 14 +-#define GCC_PCIE_2_LINK_DOWN_BCR 15 +-#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 16 +-#define GCC_PCIE_2_PHY_BCR 17 +-#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 18 +-#define GCC_PCIE_PHY_BCR 19 +-#define GCC_PCIE_PHY_CFG_AHB_BCR 20 +-#define GCC_PCIE_PHY_COM_BCR 21 +-#define GCC_PDM_BCR 22 +-#define GCC_PRNG_BCR 23 +-#define GCC_QUPV3_WRAPPER_0_BCR 24 +-#define GCC_QUPV3_WRAPPER_1_BCR 25 +-#define GCC_QUPV3_WRAPPER_2_BCR 26 +-#define GCC_QUSB2PHY_PRIM_BCR 27 +-#define GCC_QUSB2PHY_SEC_BCR 28 +-#define GCC_SDCC2_BCR 29 +-#define GCC_SDCC4_BCR 30 +-#define GCC_TSIF_BCR 31 +-#define GCC_UFS_CARD_BCR 32 +-#define GCC_UFS_PHY_BCR 33 +-#define GCC_USB30_PRIM_BCR 34 +-#define GCC_USB30_SEC_BCR 35 +-#define GCC_USB3_DP_PHY_PRIM_BCR 36 +-#define GCC_USB3_DP_PHY_SEC_BCR 37 +-#define GCC_USB3_PHY_PRIM_BCR 38 +-#define GCC_USB3_PHY_SEC_BCR 39 +-#define GCC_USB3PHY_PHY_PRIM_BCR 40 +-#define GCC_USB3PHY_PHY_SEC_BCR 41 +-#define GCC_USB_PHY_CFG_AHB2PHY_BCR 42 +-#define GCC_VIDEO_AXI0_CLK_ARES 43 +-#define GCC_VIDEO_AXI1_CLK_ARES 44 +- +-/* GCC power domains */ +-#define PCIE_0_GDSC 0 +-#define PCIE_1_GDSC 1 +-#define PCIE_2_GDSC 2 +-#define UFS_CARD_GDSC 3 +-#define UFS_PHY_GDSC 4 +-#define USB30_PRIM_GDSC 5 +-#define USB30_SEC_GDSC 6 +-#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 7 +-#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 8 +-#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 9 +-#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 10 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sm8350.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sm8350.h +deleted file mode 100644 +index f6be3da5f781..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sm8350.h ++++ /dev/null +@@ -1,266 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +-/* +- * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. +- * Copyright (c) 2020-2021, Linaro Limited +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8350_H +-#define _DT_BINDINGS_CLK_QCOM_GCC_SM8350_H +- +-/* GCC HW clocks */ +-#define CORE_BI_PLL_TEST_SE 0 +-#define PCIE_0_PIPE_CLK 1 +-#define PCIE_1_PIPE_CLK 2 +-#define UFS_CARD_RX_SYMBOL_0_CLK 3 +-#define UFS_CARD_RX_SYMBOL_1_CLK 4 +-#define UFS_CARD_TX_SYMBOL_0_CLK 5 +-#define UFS_PHY_RX_SYMBOL_0_CLK 6 +-#define UFS_PHY_RX_SYMBOL_1_CLK 7 +-#define UFS_PHY_TX_SYMBOL_0_CLK 8 +-#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK 9 +-#define USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK 10 +- +-/* GCC clocks */ +-#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 11 +-#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 12 +-#define GCC_AGGRE_NOC_PCIE_TBU_CLK 13 +-#define GCC_AGGRE_UFS_CARD_AXI_CLK 14 +-#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 15 +-#define GCC_AGGRE_UFS_PHY_AXI_CLK 16 +-#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 17 +-#define GCC_AGGRE_USB3_PRIM_AXI_CLK 18 +-#define GCC_AGGRE_USB3_SEC_AXI_CLK 19 +-#define GCC_BOOT_ROM_AHB_CLK 20 +-#define GCC_CAMERA_HF_AXI_CLK 21 +-#define GCC_CAMERA_SF_AXI_CLK 22 +-#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 23 +-#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 24 +-#define GCC_DDRSS_GPU_AXI_CLK 25 +-#define GCC_DDRSS_PCIE_SF_TBU_CLK 26 +-#define GCC_DISP_HF_AXI_CLK 27 +-#define GCC_DISP_SF_AXI_CLK 28 +-#define GCC_GP1_CLK 29 +-#define GCC_GP1_CLK_SRC 30 +-#define GCC_GP2_CLK 31 +-#define GCC_GP2_CLK_SRC 32 +-#define GCC_GP3_CLK 33 +-#define GCC_GP3_CLK_SRC 34 +-#define GCC_GPLL0 35 +-#define GCC_GPLL0_OUT_EVEN 36 +-#define GCC_GPLL4 37 +-#define GCC_GPLL9 38 +-#define GCC_GPU_GPLL0_CLK_SRC 39 +-#define GCC_GPU_GPLL0_DIV_CLK_SRC 40 +-#define GCC_GPU_IREF_EN 41 +-#define GCC_GPU_MEMNOC_GFX_CLK 42 +-#define GCC_GPU_SNOC_DVM_GFX_CLK 43 +-#define GCC_PCIE0_PHY_RCHNG_CLK 44 +-#define GCC_PCIE1_PHY_RCHNG_CLK 45 +-#define GCC_PCIE_0_AUX_CLK 46 +-#define GCC_PCIE_0_AUX_CLK_SRC 47 +-#define GCC_PCIE_0_CFG_AHB_CLK 48 +-#define GCC_PCIE_0_CLKREF_EN 49 +-#define GCC_PCIE_0_MSTR_AXI_CLK 50 +-#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 51 +-#define GCC_PCIE_0_PIPE_CLK 52 +-#define GCC_PCIE_0_PIPE_CLK_SRC 53 +-#define GCC_PCIE_0_SLV_AXI_CLK 54 +-#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 55 +-#define GCC_PCIE_1_AUX_CLK 56 +-#define GCC_PCIE_1_AUX_CLK_SRC 57 +-#define GCC_PCIE_1_CFG_AHB_CLK 58 +-#define GCC_PCIE_1_CLKREF_EN 59 +-#define GCC_PCIE_1_MSTR_AXI_CLK 60 +-#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 61 +-#define GCC_PCIE_1_PIPE_CLK 62 +-#define GCC_PCIE_1_PIPE_CLK_SRC 63 +-#define GCC_PCIE_1_SLV_AXI_CLK 64 +-#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 65 +-#define GCC_PDM2_CLK 66 +-#define GCC_PDM2_CLK_SRC 67 +-#define GCC_PDM_AHB_CLK 68 +-#define GCC_PDM_XO4_CLK 69 +-#define GCC_QMIP_CAMERA_NRT_AHB_CLK 70 +-#define GCC_QMIP_CAMERA_RT_AHB_CLK 71 +-#define GCC_QMIP_DISP_AHB_CLK 72 +-#define GCC_QMIP_VIDEO_CVP_AHB_CLK 73 +-#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 74 +-#define GCC_QUPV3_WRAP0_CORE_2X_CLK 75 +-#define GCC_QUPV3_WRAP0_CORE_CLK 76 +-#define GCC_QUPV3_WRAP0_S0_CLK 77 +-#define GCC_QUPV3_WRAP0_S0_CLK_SRC 78 +-#define GCC_QUPV3_WRAP0_S1_CLK 79 +-#define GCC_QUPV3_WRAP0_S1_CLK_SRC 80 +-#define GCC_QUPV3_WRAP0_S2_CLK 81 +-#define GCC_QUPV3_WRAP0_S2_CLK_SRC 82 +-#define GCC_QUPV3_WRAP0_S3_CLK 83 +-#define GCC_QUPV3_WRAP0_S3_CLK_SRC 84 +-#define GCC_QUPV3_WRAP0_S4_CLK 85 +-#define GCC_QUPV3_WRAP0_S4_CLK_SRC 86 +-#define GCC_QUPV3_WRAP0_S5_CLK 87 +-#define GCC_QUPV3_WRAP0_S5_CLK_SRC 88 +-#define GCC_QUPV3_WRAP0_S6_CLK 89 +-#define GCC_QUPV3_WRAP0_S6_CLK_SRC 90 +-#define GCC_QUPV3_WRAP0_S7_CLK 91 +-#define GCC_QUPV3_WRAP0_S7_CLK_SRC 92 +-#define GCC_QUPV3_WRAP1_CORE_2X_CLK 93 +-#define GCC_QUPV3_WRAP1_CORE_CLK 94 +-#define GCC_QUPV3_WRAP1_S0_CLK 95 +-#define GCC_QUPV3_WRAP1_S0_CLK_SRC 96 +-#define GCC_QUPV3_WRAP1_S1_CLK 97 +-#define GCC_QUPV3_WRAP1_S1_CLK_SRC 98 +-#define GCC_QUPV3_WRAP1_S2_CLK 99 +-#define GCC_QUPV3_WRAP1_S2_CLK_SRC 100 +-#define GCC_QUPV3_WRAP1_S3_CLK 101 +-#define GCC_QUPV3_WRAP1_S3_CLK_SRC 102 +-#define GCC_QUPV3_WRAP1_S4_CLK 103 +-#define GCC_QUPV3_WRAP1_S4_CLK_SRC 104 +-#define GCC_QUPV3_WRAP1_S5_CLK 105 +-#define GCC_QUPV3_WRAP1_S5_CLK_SRC 106 +-#define GCC_QUPV3_WRAP2_CORE_2X_CLK 107 +-#define GCC_QUPV3_WRAP2_CORE_CLK 108 +-#define GCC_QUPV3_WRAP2_S0_CLK 109 +-#define GCC_QUPV3_WRAP2_S0_CLK_SRC 110 +-#define GCC_QUPV3_WRAP2_S1_CLK 111 +-#define GCC_QUPV3_WRAP2_S1_CLK_SRC 112 +-#define GCC_QUPV3_WRAP2_S2_CLK 113 +-#define GCC_QUPV3_WRAP2_S2_CLK_SRC 114 +-#define GCC_QUPV3_WRAP2_S3_CLK 115 +-#define GCC_QUPV3_WRAP2_S3_CLK_SRC 116 +-#define GCC_QUPV3_WRAP2_S4_CLK 117 +-#define GCC_QUPV3_WRAP2_S4_CLK_SRC 118 +-#define GCC_QUPV3_WRAP2_S5_CLK 119 +-#define GCC_QUPV3_WRAP2_S5_CLK_SRC 120 +-#define GCC_QUPV3_WRAP_0_M_AHB_CLK 121 +-#define GCC_QUPV3_WRAP_0_S_AHB_CLK 122 +-#define GCC_QUPV3_WRAP_1_M_AHB_CLK 123 +-#define GCC_QUPV3_WRAP_1_S_AHB_CLK 124 +-#define GCC_QUPV3_WRAP_2_M_AHB_CLK 125 +-#define GCC_QUPV3_WRAP_2_S_AHB_CLK 126 +-#define GCC_SDCC2_AHB_CLK 127 +-#define GCC_SDCC2_APPS_CLK 128 +-#define GCC_SDCC2_APPS_CLK_SRC 129 +-#define GCC_SDCC4_AHB_CLK 130 +-#define GCC_SDCC4_APPS_CLK 131 +-#define GCC_SDCC4_APPS_CLK_SRC 132 +-#define GCC_THROTTLE_PCIE_AHB_CLK 133 +-#define GCC_UFS_1_CLKREF_EN 134 +-#define GCC_UFS_CARD_AHB_CLK 135 +-#define GCC_UFS_CARD_AXI_CLK 136 +-#define GCC_UFS_CARD_AXI_CLK_SRC 137 +-#define GCC_UFS_CARD_AXI_HW_CTL_CLK 138 +-#define GCC_UFS_CARD_ICE_CORE_CLK 139 +-#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 140 +-#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 141 +-#define GCC_UFS_CARD_PHY_AUX_CLK 142 +-#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 143 +-#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 144 +-#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 145 +-#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 146 +-#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 147 +-#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 148 +-#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 149 +-#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 150 +-#define GCC_UFS_CARD_UNIPRO_CORE_CLK 151 +-#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 152 +-#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 153 +-#define GCC_UFS_PHY_AHB_CLK 154 +-#define GCC_UFS_PHY_AXI_CLK 155 +-#define GCC_UFS_PHY_AXI_CLK_SRC 156 +-#define GCC_UFS_PHY_AXI_HW_CTL_CLK 157 +-#define GCC_UFS_PHY_ICE_CORE_CLK 158 +-#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 159 +-#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 160 +-#define GCC_UFS_PHY_PHY_AUX_CLK 161 +-#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 162 +-#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 163 +-#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 164 +-#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 165 +-#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 166 +-#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 167 +-#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 168 +-#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 169 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK 170 +-#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 171 +-#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 172 +-#define GCC_USB30_PRIM_MASTER_CLK 173 +-#define GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON 174 +-#define GCC_USB30_PRIM_MASTER_CLK_SRC 175 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK 176 +-#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 177 +-#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 178 +-#define GCC_USB30_PRIM_SLEEP_CLK 179 +-#define GCC_USB30_SEC_MASTER_CLK 180 +-#define GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON 181 +-#define GCC_USB30_SEC_MASTER_CLK_SRC 182 +-#define GCC_USB30_SEC_MOCK_UTMI_CLK 183 +-#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 184 +-#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 185 +-#define GCC_USB30_SEC_SLEEP_CLK 186 +-#define GCC_USB3_PRIM_PHY_AUX_CLK 187 +-#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 188 +-#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 189 +-#define GCC_USB3_PRIM_PHY_PIPE_CLK 190 +-#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 191 +-#define GCC_USB3_SEC_CLKREF_EN 192 +-#define GCC_USB3_SEC_PHY_AUX_CLK 193 +-#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 194 +-#define GCC_USB3_SEC_PHY_COM_AUX_CLK 195 +-#define GCC_USB3_SEC_PHY_PIPE_CLK 196 +-#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 197 +-#define GCC_VIDEO_AXI0_CLK 198 +-#define GCC_VIDEO_AXI1_CLK 199 +- +-/* GCC resets */ +-#define GCC_CAMERA_BCR 0 +-#define GCC_DISPLAY_BCR 1 +-#define GCC_GPU_BCR 2 +-#define GCC_MMSS_BCR 3 +-#define GCC_PCIE_0_BCR 4 +-#define GCC_PCIE_0_LINK_DOWN_BCR 5 +-#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6 +-#define GCC_PCIE_0_PHY_BCR 7 +-#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8 +-#define GCC_PCIE_1_BCR 9 +-#define GCC_PCIE_1_LINK_DOWN_BCR 10 +-#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11 +-#define GCC_PCIE_1_PHY_BCR 12 +-#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13 +-#define GCC_PCIE_PHY_CFG_AHB_BCR 14 +-#define GCC_PCIE_PHY_COM_BCR 15 +-#define GCC_PDM_BCR 16 +-#define GCC_QUPV3_WRAPPER_0_BCR 17 +-#define GCC_QUPV3_WRAPPER_1_BCR 18 +-#define GCC_QUPV3_WRAPPER_2_BCR 19 +-#define GCC_QUSB2PHY_PRIM_BCR 20 +-#define GCC_QUSB2PHY_SEC_BCR 21 +-#define GCC_SDCC2_BCR 22 +-#define GCC_SDCC4_BCR 23 +-#define GCC_UFS_CARD_BCR 24 +-#define GCC_UFS_PHY_BCR 25 +-#define GCC_USB30_PRIM_BCR 26 +-#define GCC_USB30_SEC_BCR 27 +-#define GCC_USB3_DP_PHY_PRIM_BCR 28 +-#define GCC_USB3_DP_PHY_SEC_BCR 29 +-#define GCC_USB3_PHY_PRIM_BCR 30 +-#define GCC_USB3_PHY_SEC_BCR 31 +-#define GCC_USB3PHY_PHY_PRIM_BCR 32 +-#define GCC_USB3PHY_PHY_SEC_BCR 33 +-#define GCC_USB_PHY_CFG_AHB2PHY_BCR 34 +-#define GCC_VIDEO_AXI0_CLK_ARES 35 +-#define GCC_VIDEO_AXI1_CLK_ARES 36 +-#define GCC_VIDEO_BCR 37 +- +-/* GCC power domains */ +-#define PCIE_0_GDSC 0 +-#define PCIE_1_GDSC 1 +-#define UFS_CARD_GDSC 2 +-#define UFS_PHY_GDSC 3 +-#define USB30_PRIM_GDSC 4 +-#define USB30_SEC_GDSC 5 +-#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 6 +-#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 7 +-#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 8 +-#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 9 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-msm8998.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-msm8998.h +deleted file mode 100644 +index 2623570ee974..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-msm8998.h ++++ /dev/null +@@ -1,29 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2019, Jeffrey Hugo +- */ +- +-#ifndef _DT_BINDINGS_CLK_MSM_GPUCC_8998_H +-#define _DT_BINDINGS_CLK_MSM_GPUCC_8998_H +- +-#define GPUPLL0 0 +-#define GPUPLL0_OUT_EVEN 1 +-#define RBCPR_CLK_SRC 2 +-#define GFX3D_CLK_SRC 3 +-#define RBBMTIMER_CLK_SRC 4 +-#define GFX3D_ISENSE_CLK_SRC 5 +-#define RBCPR_CLK 6 +-#define GFX3D_CLK 7 +-#define RBBMTIMER_CLK 8 +-#define GFX3D_ISENSE_CLK 9 +-#define GPUCC_CXO_CLK 10 +- +-#define GPU_CX_BCR 0 +-#define RBCPR_BCR 1 +-#define GPU_GX_BCR 2 +-#define GPU_ISENSE_BCR 3 +- +-#define GPU_CX_GDSC 1 +-#define GPU_GX_GDSC 2 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-sc7180.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-sc7180.h +deleted file mode 100644 +index 65e706d7d9c6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-sc7180.h ++++ /dev/null +@@ -1,22 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2019, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7180_H +-#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7180_H +- +-#define GPU_CC_PLL1 0 +-#define GPU_CC_AHB_CLK 1 +-#define GPU_CC_CRC_AHB_CLK 2 +-#define GPU_CC_CX_GMU_CLK 3 +-#define GPU_CC_CX_SNOC_DVM_CLK 4 +-#define GPU_CC_CXO_AON_CLK 5 +-#define GPU_CC_CXO_CLK 6 +-#define GPU_CC_GMU_CLK_SRC 7 +- +-/* GPU_CC GDSCRs */ +-#define CX_GDSC 0 +-#define GX_GDSC 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-sc7280.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-sc7280.h +deleted file mode 100644 +index 669b23b606ba..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-sc7280.h ++++ /dev/null +@@ -1,35 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +-/* +- * Copyright (c) 2021, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7280_H +-#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7280_H +- +-/* GPU_CC clocks */ +-#define GPU_CC_PLL0 0 +-#define GPU_CC_PLL1 1 +-#define GPU_CC_AHB_CLK 2 +-#define GPU_CC_CB_CLK 3 +-#define GPU_CC_CRC_AHB_CLK 4 +-#define GPU_CC_CX_GMU_CLK 5 +-#define GPU_CC_CX_SNOC_DVM_CLK 6 +-#define GPU_CC_CXO_AON_CLK 7 +-#define GPU_CC_CXO_CLK 8 +-#define GPU_CC_GMU_CLK_SRC 9 +-#define GPU_CC_GX_GMU_CLK 10 +-#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 11 +-#define GPU_CC_HUB_AHB_DIV_CLK_SRC 12 +-#define GPU_CC_HUB_AON_CLK 13 +-#define GPU_CC_HUB_CLK_SRC 14 +-#define GPU_CC_HUB_CX_INT_CLK 15 +-#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 16 +-#define GPU_CC_MND1X_0_GFX3D_CLK 17 +-#define GPU_CC_MND1X_1_GFX3D_CLK 18 +-#define GPU_CC_SLEEP_CLK 19 +- +-/* GPU_CC power domains */ +-#define GPU_CC_CX_GDSC 0 +-#define GPU_CC_GX_GDSC 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-sdm660.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-sdm660.h +deleted file mode 100644 +index 7ea3e53df58c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-sdm660.h ++++ /dev/null +@@ -1,28 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- * Copyright (c) 2020, AngeloGioacchino Del Regno +- */ +- +-#ifndef _DT_BINDINGS_CLK_SDM_GPUCC_660_H +-#define _DT_BINDINGS_CLK_SDM_GPUCC_660_H +- +-#define GPUCC_CXO_CLK 0 +-#define GPU_PLL0_PLL 1 +-#define GPU_PLL1_PLL 2 +-#define GFX3D_CLK_SRC 3 +-#define RBCPR_CLK_SRC 4 +-#define RBBMTIMER_CLK_SRC 5 +-#define GPUCC_RBCPR_CLK 6 +-#define GPUCC_GFX3D_CLK 7 +-#define GPUCC_RBBMTIMER_CLK 8 +- +-#define GPU_CX_GDSC 0 +-#define GPU_GX_GDSC 1 +- +-#define GPU_CX_BCR 0 +-#define GPU_GX_BCR 1 +-#define RBCPR_BCR 2 +-#define SPDM_BCR 3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-sdm845.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-sdm845.h +deleted file mode 100644 +index 9690d901b50a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-sdm845.h ++++ /dev/null +@@ -1,24 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2018, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H +-#define _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H +- +-/* GPU_CC clock registers */ +-#define GPU_CC_CX_GMU_CLK 0 +-#define GPU_CC_CXO_CLK 1 +-#define GPU_CC_GMU_CLK_SRC 2 +-#define GPU_CC_PLL1 3 +- +-/* GPU_CC Resets */ +-#define GPUCC_GPU_CC_CX_BCR 0 +-#define GPUCC_GPU_CC_GMU_BCR 1 +-#define GPUCC_GPU_CC_XO_BCR 2 +- +-/* GPU_CC GDSCRs */ +-#define GPU_CX_GDSC 0 +-#define GPU_GX_GDSC 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-sm8150.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-sm8150.h +deleted file mode 100644 +index c5b70aad7770..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-sm8150.h ++++ /dev/null +@@ -1,33 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H +-#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H +- +-/* GPU_CC clock registers */ +-#define GPU_CC_AHB_CLK 0 +-#define GPU_CC_CRC_AHB_CLK 1 +-#define GPU_CC_CX_APB_CLK 2 +-#define GPU_CC_CX_GMU_CLK 3 +-#define GPU_CC_CX_SNOC_DVM_CLK 4 +-#define GPU_CC_CXO_AON_CLK 5 +-#define GPU_CC_CXO_CLK 6 +-#define GPU_CC_GMU_CLK_SRC 7 +-#define GPU_CC_GX_GMU_CLK 8 +-#define GPU_CC_PLL1 9 +- +-/* GPU_CC Resets */ +-#define GPUCC_GPU_CC_CX_BCR 0 +-#define GPUCC_GPU_CC_GFX3D_AON_BCR 1 +-#define GPUCC_GPU_CC_GMU_BCR 2 +-#define GPUCC_GPU_CC_GX_BCR 3 +-#define GPUCC_GPU_CC_SPDM_BCR 4 +-#define GPUCC_GPU_CC_XO_BCR 5 +- +-/* GPU_CC GDSCRs */ +-#define GPU_CX_GDSC 0 +-#define GPU_GX_GDSC 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-sm8250.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-sm8250.h +deleted file mode 100644 +index dc8e387c48ad..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-sm8250.h ++++ /dev/null +@@ -1,34 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H +-#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H +- +-/* GPU_CC clock registers */ +-#define GPU_CC_AHB_CLK 0 +-#define GPU_CC_CRC_AHB_CLK 1 +-#define GPU_CC_CX_APB_CLK 2 +-#define GPU_CC_CX_GMU_CLK 3 +-#define GPU_CC_CX_SNOC_DVM_CLK 4 +-#define GPU_CC_CXO_AON_CLK 5 +-#define GPU_CC_CXO_CLK 6 +-#define GPU_CC_GMU_CLK_SRC 7 +-#define GPU_CC_GX_GMU_CLK 8 +-#define GPU_CC_PLL1 9 +-#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 10 +- +-/* GPU_CC Resets */ +-#define GPUCC_GPU_CC_ACD_BCR 0 +-#define GPUCC_GPU_CC_CX_BCR 1 +-#define GPUCC_GPU_CC_GFX3D_AON_BCR 2 +-#define GPUCC_GPU_CC_GMU_BCR 3 +-#define GPUCC_GPU_CC_GX_BCR 4 +-#define GPUCC_GPU_CC_XO_BCR 5 +- +-/* GPU_CC GDSCRs */ +-#define GPU_CX_GDSC 0 +-#define GPU_GX_GDSC 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,lcc-ipq806x.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,lcc-ipq806x.h +deleted file mode 100644 +index 25b92bbf0ab4..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,lcc-ipq806x.h ++++ /dev/null +@@ -1,22 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_LCC_IPQ806X_H +-#define _DT_BINDINGS_CLK_LCC_IPQ806X_H +- +-#define PLL4 0 +-#define MI2S_OSR_SRC 1 +-#define MI2S_OSR_CLK 2 +-#define MI2S_DIV_CLK 3 +-#define MI2S_BIT_DIV_CLK 4 +-#define MI2S_BIT_CLK 5 +-#define PCM_SRC 6 +-#define PCM_CLK_OUT 7 +-#define PCM_CLK 8 +-#define SPDIF_SRC 9 +-#define SPDIF_CLK 10 +-#define AHBIX_CLK 11 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,lcc-mdm9615.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,lcc-mdm9615.h +deleted file mode 100644 +index 299338ee1d88..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,lcc-mdm9615.h ++++ /dev/null +@@ -1,44 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014, The Linux Foundation. All rights reserved. +- * Copyright (c) BayLibre, SAS. +- * Author : Neil Armstrong +- */ +- +-#ifndef _DT_BINDINGS_CLK_LCC_MDM9615_H +-#define _DT_BINDINGS_CLK_LCC_MDM9615_H +- +-#define PLL4 0 +-#define MI2S_OSR_SRC 1 +-#define MI2S_OSR_CLK 2 +-#define MI2S_DIV_CLK 3 +-#define MI2S_BIT_DIV_CLK 4 +-#define MI2S_BIT_CLK 5 +-#define PCM_SRC 6 +-#define PCM_CLK_OUT 7 +-#define PCM_CLK 8 +-#define SLIMBUS_SRC 9 +-#define AUDIO_SLIMBUS_CLK 10 +-#define SPS_SLIMBUS_CLK 11 +-#define CODEC_I2S_MIC_OSR_SRC 12 +-#define CODEC_I2S_MIC_OSR_CLK 13 +-#define CODEC_I2S_MIC_DIV_CLK 14 +-#define CODEC_I2S_MIC_BIT_DIV_CLK 15 +-#define CODEC_I2S_MIC_BIT_CLK 16 +-#define SPARE_I2S_MIC_OSR_SRC 17 +-#define SPARE_I2S_MIC_OSR_CLK 18 +-#define SPARE_I2S_MIC_DIV_CLK 19 +-#define SPARE_I2S_MIC_BIT_DIV_CLK 20 +-#define SPARE_I2S_MIC_BIT_CLK 21 +-#define CODEC_I2S_SPKR_OSR_SRC 22 +-#define CODEC_I2S_SPKR_OSR_CLK 23 +-#define CODEC_I2S_SPKR_DIV_CLK 24 +-#define CODEC_I2S_SPKR_BIT_DIV_CLK 25 +-#define CODEC_I2S_SPKR_BIT_CLK 26 +-#define SPARE_I2S_SPKR_OSR_SRC 27 +-#define SPARE_I2S_SPKR_OSR_CLK 28 +-#define SPARE_I2S_SPKR_DIV_CLK 29 +-#define SPARE_I2S_SPKR_BIT_DIV_CLK 30 +-#define SPARE_I2S_SPKR_BIT_CLK 31 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,lcc-msm8960.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,lcc-msm8960.h +deleted file mode 100644 +index d115a49f4cb6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,lcc-msm8960.h ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_LCC_MSM8960_H +-#define _DT_BINDINGS_CLK_LCC_MSM8960_H +- +-#define PLL4 0 +-#define MI2S_OSR_SRC 1 +-#define MI2S_OSR_CLK 2 +-#define MI2S_DIV_CLK 3 +-#define MI2S_BIT_DIV_CLK 4 +-#define MI2S_BIT_CLK 5 +-#define PCM_SRC 6 +-#define PCM_CLK_OUT 7 +-#define PCM_CLK 8 +-#define SLIMBUS_SRC 9 +-#define AUDIO_SLIMBUS_CLK 10 +-#define SPS_SLIMBUS_CLK 11 +-#define CODEC_I2S_MIC_OSR_SRC 12 +-#define CODEC_I2S_MIC_OSR_CLK 13 +-#define CODEC_I2S_MIC_DIV_CLK 14 +-#define CODEC_I2S_MIC_BIT_DIV_CLK 15 +-#define CODEC_I2S_MIC_BIT_CLK 16 +-#define SPARE_I2S_MIC_OSR_SRC 17 +-#define SPARE_I2S_MIC_OSR_CLK 18 +-#define SPARE_I2S_MIC_DIV_CLK 19 +-#define SPARE_I2S_MIC_BIT_DIV_CLK 20 +-#define SPARE_I2S_MIC_BIT_CLK 21 +-#define CODEC_I2S_SPKR_OSR_SRC 22 +-#define CODEC_I2S_SPKR_OSR_CLK 23 +-#define CODEC_I2S_SPKR_DIV_CLK 24 +-#define CODEC_I2S_SPKR_BIT_DIV_CLK 25 +-#define CODEC_I2S_SPKR_BIT_CLK 26 +-#define SPARE_I2S_SPKR_OSR_SRC 27 +-#define SPARE_I2S_SPKR_OSR_CLK 28 +-#define SPARE_I2S_SPKR_DIV_CLK 29 +-#define SPARE_I2S_SPKR_BIT_DIV_CLK 30 +-#define SPARE_I2S_SPKR_BIT_CLK 31 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,lpass-sdm845.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,lpass-sdm845.h +deleted file mode 100644 +index 659050846f61..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,lpass-sdm845.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2018, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H +-#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H +- +-#define LPASS_Q6SS_AHBM_AON_CLK 0 +-#define LPASS_Q6SS_AHBS_AON_CLK 1 +-#define LPASS_QDSP6SS_XO_CLK 2 +-#define LPASS_QDSP6SS_SLEEP_CLK 3 +-#define LPASS_QDSP6SS_CORE_CLK 4 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,lpasscorecc-sc7180.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,lpasscorecc-sc7180.h +deleted file mode 100644 +index a55d01db2b20..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,lpasscorecc-sc7180.h ++++ /dev/null +@@ -1,29 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H +-#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H +- +-/* LPASS_CORE_CC clocks */ +-#define LPASS_LPAAUDIO_DIG_PLL 0 +-#define LPASS_LPAAUDIO_DIG_PLL_OUT_ODD 1 +-#define CORE_CLK_SRC 2 +-#define EXT_MCLK0_CLK_SRC 3 +-#define LPAIF_PRI_CLK_SRC 4 +-#define LPAIF_SEC_CLK_SRC 5 +-#define LPASS_AUDIO_CORE_CORE_CLK 6 +-#define LPASS_AUDIO_CORE_EXT_MCLK0_CLK 7 +-#define LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK 8 +-#define LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK 9 +-#define LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK 10 +- +-/* LPASS Core power domains */ +-#define LPASS_CORE_HM_GDSCR 0 +- +-/* LPASS Audio power domains */ +-#define LPASS_AUDIO_HM_GDSCR 0 +-#define LPASS_PDC_HM_GDSCR 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-apq8084.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-apq8084.h +deleted file mode 100644 +index 9d42b1b25a91..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-apq8084.h ++++ /dev/null +@@ -1,185 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_APQ_MMCC_8084_H +-#define _DT_BINDINGS_CLK_APQ_MMCC_8084_H +- +-#define MMSS_AHB_CLK_SRC 0 +-#define MMSS_AXI_CLK_SRC 1 +-#define MMPLL0 2 +-#define MMPLL0_VOTE 3 +-#define MMPLL1 4 +-#define MMPLL1_VOTE 5 +-#define MMPLL2 6 +-#define MMPLL3 7 +-#define MMPLL4 8 +-#define CSI0_CLK_SRC 9 +-#define CSI1_CLK_SRC 10 +-#define CSI2_CLK_SRC 11 +-#define CSI3_CLK_SRC 12 +-#define VCODEC0_CLK_SRC 13 +-#define VFE0_CLK_SRC 14 +-#define VFE1_CLK_SRC 15 +-#define MDP_CLK_SRC 16 +-#define PCLK0_CLK_SRC 17 +-#define PCLK1_CLK_SRC 18 +-#define OCMEMNOC_CLK_SRC 19 +-#define GFX3D_CLK_SRC 20 +-#define JPEG0_CLK_SRC 21 +-#define JPEG1_CLK_SRC 22 +-#define JPEG2_CLK_SRC 23 +-#define EDPPIXEL_CLK_SRC 24 +-#define EXTPCLK_CLK_SRC 25 +-#define VP_CLK_SRC 26 +-#define CCI_CLK_SRC 27 +-#define CAMSS_GP0_CLK_SRC 28 +-#define CAMSS_GP1_CLK_SRC 29 +-#define MCLK0_CLK_SRC 30 +-#define MCLK1_CLK_SRC 31 +-#define MCLK2_CLK_SRC 32 +-#define MCLK3_CLK_SRC 33 +-#define CSI0PHYTIMER_CLK_SRC 34 +-#define CSI1PHYTIMER_CLK_SRC 35 +-#define CSI2PHYTIMER_CLK_SRC 36 +-#define CPP_CLK_SRC 37 +-#define BYTE0_CLK_SRC 38 +-#define BYTE1_CLK_SRC 39 +-#define EDPAUX_CLK_SRC 40 +-#define EDPLINK_CLK_SRC 41 +-#define ESC0_CLK_SRC 42 +-#define ESC1_CLK_SRC 43 +-#define HDMI_CLK_SRC 44 +-#define VSYNC_CLK_SRC 45 +-#define MMSS_RBCPR_CLK_SRC 46 +-#define RBBMTIMER_CLK_SRC 47 +-#define MAPLE_CLK_SRC 48 +-#define VDP_CLK_SRC 49 +-#define VPU_BUS_CLK_SRC 50 +-#define MMSS_CXO_CLK 51 +-#define MMSS_SLEEPCLK_CLK 52 +-#define AVSYNC_AHB_CLK 53 +-#define AVSYNC_EDPPIXEL_CLK 54 +-#define AVSYNC_EXTPCLK_CLK 55 +-#define AVSYNC_PCLK0_CLK 56 +-#define AVSYNC_PCLK1_CLK 57 +-#define AVSYNC_VP_CLK 58 +-#define CAMSS_AHB_CLK 59 +-#define CAMSS_CCI_CCI_AHB_CLK 60 +-#define CAMSS_CCI_CCI_CLK 61 +-#define CAMSS_CSI0_AHB_CLK 62 +-#define CAMSS_CSI0_CLK 63 +-#define CAMSS_CSI0PHY_CLK 64 +-#define CAMSS_CSI0PIX_CLK 65 +-#define CAMSS_CSI0RDI_CLK 66 +-#define CAMSS_CSI1_AHB_CLK 67 +-#define CAMSS_CSI1_CLK 68 +-#define CAMSS_CSI1PHY_CLK 69 +-#define CAMSS_CSI1PIX_CLK 70 +-#define CAMSS_CSI1RDI_CLK 71 +-#define CAMSS_CSI2_AHB_CLK 72 +-#define CAMSS_CSI2_CLK 73 +-#define CAMSS_CSI2PHY_CLK 74 +-#define CAMSS_CSI2PIX_CLK 75 +-#define CAMSS_CSI2RDI_CLK 76 +-#define CAMSS_CSI3_AHB_CLK 77 +-#define CAMSS_CSI3_CLK 78 +-#define CAMSS_CSI3PHY_CLK 79 +-#define CAMSS_CSI3PIX_CLK 80 +-#define CAMSS_CSI3RDI_CLK 81 +-#define CAMSS_CSI_VFE0_CLK 82 +-#define CAMSS_CSI_VFE1_CLK 83 +-#define CAMSS_GP0_CLK 84 +-#define CAMSS_GP1_CLK 85 +-#define CAMSS_ISPIF_AHB_CLK 86 +-#define CAMSS_JPEG_JPEG0_CLK 87 +-#define CAMSS_JPEG_JPEG1_CLK 88 +-#define CAMSS_JPEG_JPEG2_CLK 89 +-#define CAMSS_JPEG_JPEG_AHB_CLK 90 +-#define CAMSS_JPEG_JPEG_AXI_CLK 91 +-#define CAMSS_MCLK0_CLK 92 +-#define CAMSS_MCLK1_CLK 93 +-#define CAMSS_MCLK2_CLK 94 +-#define CAMSS_MCLK3_CLK 95 +-#define CAMSS_MICRO_AHB_CLK 96 +-#define CAMSS_PHY0_CSI0PHYTIMER_CLK 97 +-#define CAMSS_PHY1_CSI1PHYTIMER_CLK 98 +-#define CAMSS_PHY2_CSI2PHYTIMER_CLK 99 +-#define CAMSS_TOP_AHB_CLK 100 +-#define CAMSS_VFE_CPP_AHB_CLK 101 +-#define CAMSS_VFE_CPP_CLK 102 +-#define CAMSS_VFE_VFE0_CLK 103 +-#define CAMSS_VFE_VFE1_CLK 104 +-#define CAMSS_VFE_VFE_AHB_CLK 105 +-#define CAMSS_VFE_VFE_AXI_CLK 106 +-#define MDSS_AHB_CLK 107 +-#define MDSS_AXI_CLK 108 +-#define MDSS_BYTE0_CLK 109 +-#define MDSS_BYTE1_CLK 110 +-#define MDSS_EDPAUX_CLK 111 +-#define MDSS_EDPLINK_CLK 112 +-#define MDSS_EDPPIXEL_CLK 113 +-#define MDSS_ESC0_CLK 114 +-#define MDSS_ESC1_CLK 115 +-#define MDSS_EXTPCLK_CLK 116 +-#define MDSS_HDMI_AHB_CLK 117 +-#define MDSS_HDMI_CLK 118 +-#define MDSS_MDP_CLK 119 +-#define MDSS_MDP_LUT_CLK 120 +-#define MDSS_PCLK0_CLK 121 +-#define MDSS_PCLK1_CLK 122 +-#define MDSS_VSYNC_CLK 123 +-#define MMSS_RBCPR_AHB_CLK 124 +-#define MMSS_RBCPR_CLK 125 +-#define MMSS_SPDM_AHB_CLK 126 +-#define MMSS_SPDM_AXI_CLK 127 +-#define MMSS_SPDM_CSI0_CLK 128 +-#define MMSS_SPDM_GFX3D_CLK 129 +-#define MMSS_SPDM_JPEG0_CLK 130 +-#define MMSS_SPDM_JPEG1_CLK 131 +-#define MMSS_SPDM_JPEG2_CLK 132 +-#define MMSS_SPDM_MDP_CLK 133 +-#define MMSS_SPDM_PCLK0_CLK 134 +-#define MMSS_SPDM_PCLK1_CLK 135 +-#define MMSS_SPDM_VCODEC0_CLK 136 +-#define MMSS_SPDM_VFE0_CLK 137 +-#define MMSS_SPDM_VFE1_CLK 138 +-#define MMSS_SPDM_RM_AXI_CLK 139 +-#define MMSS_SPDM_RM_OCMEMNOC_CLK 140 +-#define MMSS_MISC_AHB_CLK 141 +-#define MMSS_MMSSNOC_AHB_CLK 142 +-#define MMSS_MMSSNOC_BTO_AHB_CLK 143 +-#define MMSS_MMSSNOC_AXI_CLK 144 +-#define MMSS_S0_AXI_CLK 145 +-#define OCMEMCX_AHB_CLK 146 +-#define OCMEMCX_OCMEMNOC_CLK 147 +-#define OXILI_OCMEMGX_CLK 148 +-#define OXILI_GFX3D_CLK 149 +-#define OXILI_RBBMTIMER_CLK 150 +-#define OXILICX_AHB_CLK 151 +-#define VENUS0_AHB_CLK 152 +-#define VENUS0_AXI_CLK 153 +-#define VENUS0_CORE0_VCODEC_CLK 154 +-#define VENUS0_CORE1_VCODEC_CLK 155 +-#define VENUS0_OCMEMNOC_CLK 156 +-#define VENUS0_VCODEC0_CLK 157 +-#define VPU_AHB_CLK 158 +-#define VPU_AXI_CLK 159 +-#define VPU_BUS_CLK 160 +-#define VPU_CXO_CLK 161 +-#define VPU_MAPLE_CLK 162 +-#define VPU_SLEEP_CLK 163 +-#define VPU_VDP_CLK 164 +- +-/* GDSCs */ +-#define VENUS0_GDSC 0 +-#define VENUS0_CORE0_GDSC 1 +-#define VENUS0_CORE1_GDSC 2 +-#define MDSS_GDSC 3 +-#define CAMSS_JPEG_GDSC 4 +-#define CAMSS_VFE_GDSC 5 +-#define OXILI_GDSC 6 +-#define OXILICX_GDSC 7 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-msm8960.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-msm8960.h +deleted file mode 100644 +index 81714fc859c5..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-msm8960.h ++++ /dev/null +@@ -1,137 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2013, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8960_H +-#define _DT_BINDINGS_CLK_MSM_MMCC_8960_H +- +-#define MMSS_AHB_SRC 0 +-#define FAB_AHB_CLK 1 +-#define APU_AHB_CLK 2 +-#define TV_ENC_AHB_CLK 3 +-#define AMP_AHB_CLK 4 +-#define DSI2_S_AHB_CLK 5 +-#define JPEGD_AHB_CLK 6 +-#define GFX2D0_AHB_CLK 7 +-#define DSI_S_AHB_CLK 8 +-#define DSI2_M_AHB_CLK 9 +-#define VPE_AHB_CLK 10 +-#define SMMU_AHB_CLK 11 +-#define HDMI_M_AHB_CLK 12 +-#define VFE_AHB_CLK 13 +-#define ROT_AHB_CLK 14 +-#define VCODEC_AHB_CLK 15 +-#define MDP_AHB_CLK 16 +-#define DSI_M_AHB_CLK 17 +-#define CSI_AHB_CLK 18 +-#define MMSS_IMEM_AHB_CLK 19 +-#define IJPEG_AHB_CLK 20 +-#define HDMI_S_AHB_CLK 21 +-#define GFX3D_AHB_CLK 22 +-#define GFX2D1_AHB_CLK 23 +-#define MMSS_FPB_CLK 24 +-#define MMSS_AXI_SRC 25 +-#define MMSS_FAB_CORE 26 +-#define FAB_MSP_AXI_CLK 27 +-#define JPEGD_AXI_CLK 28 +-#define GMEM_AXI_CLK 29 +-#define MDP_AXI_CLK 30 +-#define MMSS_IMEM_AXI_CLK 31 +-#define IJPEG_AXI_CLK 32 +-#define GFX3D_AXI_CLK 33 +-#define VCODEC_AXI_CLK 34 +-#define VFE_AXI_CLK 35 +-#define VPE_AXI_CLK 36 +-#define ROT_AXI_CLK 37 +-#define VCODEC_AXI_A_CLK 38 +-#define VCODEC_AXI_B_CLK 39 +-#define MM_AXI_S3_FCLK 40 +-#define MM_AXI_S2_FCLK 41 +-#define MM_AXI_S1_FCLK 42 +-#define MM_AXI_S0_FCLK 43 +-#define MM_AXI_S2_CLK 44 +-#define MM_AXI_S1_CLK 45 +-#define MM_AXI_S0_CLK 46 +-#define CSI0_SRC 47 +-#define CSI0_CLK 48 +-#define CSI0_PHY_CLK 49 +-#define CSI1_SRC 50 +-#define CSI1_CLK 51 +-#define CSI1_PHY_CLK 52 +-#define CSI2_SRC 53 +-#define CSI2_CLK 54 +-#define CSI2_PHY_CLK 55 +-#define DSI_SRC 56 +-#define DSI_CLK 57 +-#define CSI_PIX_CLK 58 +-#define CSI_RDI_CLK 59 +-#define MDP_VSYNC_CLK 60 +-#define HDMI_DIV_CLK 61 +-#define HDMI_APP_CLK 62 +-#define CSI_PIX1_CLK 63 +-#define CSI_RDI2_CLK 64 +-#define CSI_RDI1_CLK 65 +-#define GFX2D0_SRC 66 +-#define GFX2D0_CLK 67 +-#define GFX2D1_SRC 68 +-#define GFX2D1_CLK 69 +-#define GFX3D_SRC 70 +-#define GFX3D_CLK 71 +-#define IJPEG_SRC 72 +-#define IJPEG_CLK 73 +-#define JPEGD_SRC 74 +-#define JPEGD_CLK 75 +-#define MDP_SRC 76 +-#define MDP_CLK 77 +-#define MDP_LUT_CLK 78 +-#define DSI2_PIXEL_SRC 79 +-#define DSI2_PIXEL_CLK 80 +-#define DSI2_SRC 81 +-#define DSI2_CLK 82 +-#define DSI1_BYTE_SRC 83 +-#define DSI1_BYTE_CLK 84 +-#define DSI2_BYTE_SRC 85 +-#define DSI2_BYTE_CLK 86 +-#define DSI1_ESC_SRC 87 +-#define DSI1_ESC_CLK 88 +-#define DSI2_ESC_SRC 89 +-#define DSI2_ESC_CLK 90 +-#define ROT_SRC 91 +-#define ROT_CLK 92 +-#define TV_ENC_CLK 93 +-#define TV_DAC_CLK 94 +-#define HDMI_TV_CLK 95 +-#define MDP_TV_CLK 96 +-#define TV_SRC 97 +-#define VCODEC_SRC 98 +-#define VCODEC_CLK 99 +-#define VFE_SRC 100 +-#define VFE_CLK 101 +-#define VFE_CSI_CLK 102 +-#define VPE_SRC 103 +-#define VPE_CLK 104 +-#define DSI_PIXEL_SRC 105 +-#define DSI_PIXEL_CLK 106 +-#define CAMCLK0_SRC 107 +-#define CAMCLK0_CLK 108 +-#define CAMCLK1_SRC 109 +-#define CAMCLK1_CLK 110 +-#define CAMCLK2_SRC 111 +-#define CAMCLK2_CLK 112 +-#define CSIPHYTIMER_SRC 113 +-#define CSIPHY2_TIMER_CLK 114 +-#define CSIPHY1_TIMER_CLK 115 +-#define CSIPHY0_TIMER_CLK 116 +-#define PLL1 117 +-#define PLL2 118 +-#define RGB_TV_CLK 119 +-#define NPL_TV_CLK 120 +-#define VCAP_AHB_CLK 121 +-#define VCAP_AXI_CLK 122 +-#define VCAP_SRC 123 +-#define VCAP_CLK 124 +-#define VCAP_NPL_CLK 125 +-#define PLL15 126 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-msm8974.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-msm8974.h +deleted file mode 100644 +index a62cb0629a7a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-msm8974.h ++++ /dev/null +@@ -1,161 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2013, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8974_H +-#define _DT_BINDINGS_CLK_MSM_MMCC_8974_H +- +-#define MMSS_AHB_CLK_SRC 0 +-#define MMSS_AXI_CLK_SRC 1 +-#define MMPLL0 2 +-#define MMPLL0_VOTE 3 +-#define MMPLL1 4 +-#define MMPLL1_VOTE 5 +-#define MMPLL2 6 +-#define MMPLL3 7 +-#define CSI0_CLK_SRC 8 +-#define CSI1_CLK_SRC 9 +-#define CSI2_CLK_SRC 10 +-#define CSI3_CLK_SRC 11 +-#define VFE0_CLK_SRC 12 +-#define VFE1_CLK_SRC 13 +-#define MDP_CLK_SRC 14 +-#define GFX3D_CLK_SRC 15 +-#define JPEG0_CLK_SRC 16 +-#define JPEG1_CLK_SRC 17 +-#define JPEG2_CLK_SRC 18 +-#define PCLK0_CLK_SRC 19 +-#define PCLK1_CLK_SRC 20 +-#define VCODEC0_CLK_SRC 21 +-#define CCI_CLK_SRC 22 +-#define CAMSS_GP0_CLK_SRC 23 +-#define CAMSS_GP1_CLK_SRC 24 +-#define MCLK0_CLK_SRC 25 +-#define MCLK1_CLK_SRC 26 +-#define MCLK2_CLK_SRC 27 +-#define MCLK3_CLK_SRC 28 +-#define CSI0PHYTIMER_CLK_SRC 29 +-#define CSI1PHYTIMER_CLK_SRC 30 +-#define CSI2PHYTIMER_CLK_SRC 31 +-#define CPP_CLK_SRC 32 +-#define BYTE0_CLK_SRC 33 +-#define BYTE1_CLK_SRC 34 +-#define EDPAUX_CLK_SRC 35 +-#define EDPLINK_CLK_SRC 36 +-#define EDPPIXEL_CLK_SRC 37 +-#define ESC0_CLK_SRC 38 +-#define ESC1_CLK_SRC 39 +-#define EXTPCLK_CLK_SRC 40 +-#define HDMI_CLK_SRC 41 +-#define VSYNC_CLK_SRC 42 +-#define MMSS_RBCPR_CLK_SRC 43 +-#define CAMSS_CCI_CCI_AHB_CLK 44 +-#define CAMSS_CCI_CCI_CLK 45 +-#define CAMSS_CSI0_AHB_CLK 46 +-#define CAMSS_CSI0_CLK 47 +-#define CAMSS_CSI0PHY_CLK 48 +-#define CAMSS_CSI0PIX_CLK 49 +-#define CAMSS_CSI0RDI_CLK 50 +-#define CAMSS_CSI1_AHB_CLK 51 +-#define CAMSS_CSI1_CLK 52 +-#define CAMSS_CSI1PHY_CLK 53 +-#define CAMSS_CSI1PIX_CLK 54 +-#define CAMSS_CSI1RDI_CLK 55 +-#define CAMSS_CSI2_AHB_CLK 56 +-#define CAMSS_CSI2_CLK 57 +-#define CAMSS_CSI2PHY_CLK 58 +-#define CAMSS_CSI2PIX_CLK 59 +-#define CAMSS_CSI2RDI_CLK 60 +-#define CAMSS_CSI3_AHB_CLK 61 +-#define CAMSS_CSI3_CLK 62 +-#define CAMSS_CSI3PHY_CLK 63 +-#define CAMSS_CSI3PIX_CLK 64 +-#define CAMSS_CSI3RDI_CLK 65 +-#define CAMSS_CSI_VFE0_CLK 66 +-#define CAMSS_CSI_VFE1_CLK 67 +-#define CAMSS_GP0_CLK 68 +-#define CAMSS_GP1_CLK 69 +-#define CAMSS_ISPIF_AHB_CLK 70 +-#define CAMSS_JPEG_JPEG0_CLK 71 +-#define CAMSS_JPEG_JPEG1_CLK 72 +-#define CAMSS_JPEG_JPEG2_CLK 73 +-#define CAMSS_JPEG_JPEG_AHB_CLK 74 +-#define CAMSS_JPEG_JPEG_AXI_CLK 75 +-#define CAMSS_JPEG_JPEG_OCMEMNOC_CLK 76 +-#define CAMSS_MCLK0_CLK 77 +-#define CAMSS_MCLK1_CLK 78 +-#define CAMSS_MCLK2_CLK 79 +-#define CAMSS_MCLK3_CLK 80 +-#define CAMSS_MICRO_AHB_CLK 81 +-#define CAMSS_PHY0_CSI0PHYTIMER_CLK 82 +-#define CAMSS_PHY1_CSI1PHYTIMER_CLK 83 +-#define CAMSS_PHY2_CSI2PHYTIMER_CLK 84 +-#define CAMSS_TOP_AHB_CLK 85 +-#define CAMSS_VFE_CPP_AHB_CLK 86 +-#define CAMSS_VFE_CPP_CLK 87 +-#define CAMSS_VFE_VFE0_CLK 88 +-#define CAMSS_VFE_VFE1_CLK 89 +-#define CAMSS_VFE_VFE_AHB_CLK 90 +-#define CAMSS_VFE_VFE_AXI_CLK 91 +-#define CAMSS_VFE_VFE_OCMEMNOC_CLK 92 +-#define MDSS_AHB_CLK 93 +-#define MDSS_AXI_CLK 94 +-#define MDSS_BYTE0_CLK 95 +-#define MDSS_BYTE1_CLK 96 +-#define MDSS_EDPAUX_CLK 97 +-#define MDSS_EDPLINK_CLK 98 +-#define MDSS_EDPPIXEL_CLK 99 +-#define MDSS_ESC0_CLK 100 +-#define MDSS_ESC1_CLK 101 +-#define MDSS_EXTPCLK_CLK 102 +-#define MDSS_HDMI_AHB_CLK 103 +-#define MDSS_HDMI_CLK 104 +-#define MDSS_MDP_CLK 105 +-#define MDSS_MDP_LUT_CLK 106 +-#define MDSS_PCLK0_CLK 107 +-#define MDSS_PCLK1_CLK 108 +-#define MDSS_VSYNC_CLK 109 +-#define MMSS_MISC_AHB_CLK 110 +-#define MMSS_MMSSNOC_AHB_CLK 111 +-#define MMSS_MMSSNOC_BTO_AHB_CLK 112 +-#define MMSS_MMSSNOC_AXI_CLK 113 +-#define MMSS_S0_AXI_CLK 114 +-#define OCMEMCX_AHB_CLK 115 +-#define OCMEMCX_OCMEMNOC_CLK 116 +-#define OXILI_OCMEMGX_CLK 117 +-#define OCMEMNOC_CLK 118 +-#define OXILI_GFX3D_CLK 119 +-#define OXILICX_AHB_CLK 120 +-#define OXILICX_AXI_CLK 121 +-#define VENUS0_AHB_CLK 122 +-#define VENUS0_AXI_CLK 123 +-#define VENUS0_OCMEMNOC_CLK 124 +-#define VENUS0_VCODEC0_CLK 125 +-#define OCMEMNOC_CLK_SRC 126 +-#define SPDM_JPEG0 127 +-#define SPDM_JPEG1 128 +-#define SPDM_MDP 129 +-#define SPDM_AXI 130 +-#define SPDM_VCODEC0 131 +-#define SPDM_VFE0 132 +-#define SPDM_VFE1 133 +-#define SPDM_JPEG2 134 +-#define SPDM_PCLK1 135 +-#define SPDM_GFX3D 136 +-#define SPDM_AHB 137 +-#define SPDM_PCLK0 138 +-#define SPDM_OCMEMNOC 139 +-#define SPDM_CSI0 140 +-#define SPDM_RM_AXI 141 +-#define SPDM_RM_OCMEMNOC 142 +- +-/* gdscs */ +-#define VENUS0_GDSC 0 +-#define MDSS_GDSC 1 +-#define CAMSS_JPEG_GDSC 2 +-#define CAMSS_VFE_GDSC 3 +-#define OXILI_GDSC 4 +-#define OXILICX_GDSC 5 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-msm8994.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-msm8994.h +deleted file mode 100644 +index 4b289092f5a2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-msm8994.h ++++ /dev/null +@@ -1,155 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2020, Konrad Dybcio +- */ +- +-#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8994_H +-#define _DT_BINDINGS_CLK_MSM_MMCC_8994_H +- +-/* Clocks */ +-#define MMPLL0_EARLY 0 +-#define MMPLL0_PLL 1 +-#define MMPLL1_EARLY 2 +-#define MMPLL1_PLL 3 +-#define MMPLL3_EARLY 4 +-#define MMPLL3_PLL 5 +-#define MMPLL4_EARLY 6 +-#define MMPLL4_PLL 7 +-#define MMPLL5_EARLY 8 +-#define MMPLL5_PLL 9 +-#define AXI_CLK_SRC 10 +-#define RBBMTIMER_CLK_SRC 11 +-#define PCLK0_CLK_SRC 12 +-#define PCLK1_CLK_SRC 13 +-#define MDP_CLK_SRC 14 +-#define VSYNC_CLK_SRC 15 +-#define BYTE0_CLK_SRC 16 +-#define BYTE1_CLK_SRC 17 +-#define ESC0_CLK_SRC 18 +-#define ESC1_CLK_SRC 19 +-#define MDSS_AHB_CLK 20 +-#define MDSS_PCLK0_CLK 21 +-#define MDSS_PCLK1_CLK 22 +-#define MDSS_VSYNC_CLK 23 +-#define MDSS_BYTE0_CLK 24 +-#define MDSS_BYTE1_CLK 25 +-#define MDSS_ESC0_CLK 26 +-#define MDSS_ESC1_CLK 27 +-#define CSI0_CLK_SRC 28 +-#define CSI1_CLK_SRC 29 +-#define CSI2_CLK_SRC 30 +-#define CSI3_CLK_SRC 31 +-#define VFE0_CLK_SRC 32 +-#define VFE1_CLK_SRC 33 +-#define CPP_CLK_SRC 34 +-#define JPEG0_CLK_SRC 35 +-#define JPEG1_CLK_SRC 36 +-#define JPEG2_CLK_SRC 37 +-#define CSI2PHYTIMER_CLK_SRC 38 +-#define FD_CORE_CLK_SRC 39 +-#define OCMEMNOC_CLK_SRC 40 +-#define CCI_CLK_SRC 41 +-#define MMSS_GP0_CLK_SRC 42 +-#define MMSS_GP1_CLK_SRC 43 +-#define JPEG_DMA_CLK_SRC 44 +-#define MCLK0_CLK_SRC 45 +-#define MCLK1_CLK_SRC 46 +-#define MCLK2_CLK_SRC 47 +-#define MCLK3_CLK_SRC 48 +-#define CSI0PHYTIMER_CLK_SRC 49 +-#define CSI1PHYTIMER_CLK_SRC 50 +-#define EXTPCLK_CLK_SRC 51 +-#define HDMI_CLK_SRC 52 +-#define CAMSS_AHB_CLK 53 +-#define CAMSS_CCI_CCI_AHB_CLK 54 +-#define CAMSS_CCI_CCI_CLK 55 +-#define CAMSS_VFE_CPP_AHB_CLK 56 +-#define CAMSS_VFE_CPP_AXI_CLK 57 +-#define CAMSS_VFE_CPP_CLK 58 +-#define CAMSS_CSI0_AHB_CLK 59 +-#define CAMSS_CSI0_CLK 60 +-#define CAMSS_CSI0PHY_CLK 61 +-#define CAMSS_CSI0PIX_CLK 62 +-#define CAMSS_CSI0RDI_CLK 63 +-#define CAMSS_CSI1_AHB_CLK 64 +-#define CAMSS_CSI1_CLK 65 +-#define CAMSS_CSI1PHY_CLK 66 +-#define CAMSS_CSI1PIX_CLK 67 +-#define CAMSS_CSI1RDI_CLK 68 +-#define CAMSS_CSI2_AHB_CLK 69 +-#define CAMSS_CSI2_CLK 70 +-#define CAMSS_CSI2PHY_CLK 71 +-#define CAMSS_CSI2PIX_CLK 72 +-#define CAMSS_CSI2RDI_CLK 73 +-#define CAMSS_CSI3_AHB_CLK 74 +-#define CAMSS_CSI3_CLK 75 +-#define CAMSS_CSI3PHY_CLK 76 +-#define CAMSS_CSI3PIX_CLK 77 +-#define CAMSS_CSI3RDI_CLK 78 +-#define CAMSS_CSI_VFE0_CLK 79 +-#define CAMSS_CSI_VFE1_CLK 80 +-#define CAMSS_GP0_CLK 81 +-#define CAMSS_GP1_CLK 82 +-#define CAMSS_ISPIF_AHB_CLK 83 +-#define CAMSS_JPEG_DMA_CLK 84 +-#define CAMSS_JPEG_JPEG0_CLK 85 +-#define CAMSS_JPEG_JPEG1_CLK 86 +-#define CAMSS_JPEG_JPEG2_CLK 87 +-#define CAMSS_JPEG_JPEG_AHB_CLK 88 +-#define CAMSS_JPEG_JPEG_AXI_CLK 89 +-#define CAMSS_MCLK0_CLK 90 +-#define CAMSS_MCLK1_CLK 91 +-#define CAMSS_MCLK2_CLK 92 +-#define CAMSS_MCLK3_CLK 93 +-#define CAMSS_MICRO_AHB_CLK 94 +-#define CAMSS_PHY0_CSI0PHYTIMER_CLK 95 +-#define CAMSS_PHY1_CSI1PHYTIMER_CLK 96 +-#define CAMSS_PHY2_CSI2PHYTIMER_CLK 97 +-#define CAMSS_TOP_AHB_CLK 98 +-#define CAMSS_VFE_VFE0_CLK 99 +-#define CAMSS_VFE_VFE1_CLK 100 +-#define CAMSS_VFE_VFE_AHB_CLK 101 +-#define CAMSS_VFE_VFE_AXI_CLK 102 +-#define FD_AXI_CLK 103 +-#define FD_CORE_CLK 104 +-#define FD_CORE_UAR_CLK 105 +-#define MDSS_AXI_CLK 106 +-#define MDSS_EXTPCLK_CLK 107 +-#define MDSS_HDMI_AHB_CLK 108 +-#define MDSS_HDMI_CLK 109 +-#define MDSS_MDP_CLK 110 +-#define MMSS_MISC_AHB_CLK 111 +-#define MMSS_MMSSNOC_AXI_CLK 112 +-#define MMSS_S0_AXI_CLK 113 +-#define OCMEMCX_OCMEMNOC_CLK 114 +-#define OXILI_GFX3D_CLK 115 +-#define OXILI_RBBMTIMER_CLK 116 +-#define OXILICX_AHB_CLK 117 +-#define VENUS0_AHB_CLK 118 +-#define VENUS0_AXI_CLK 119 +-#define VENUS0_OCMEMNOC_CLK 120 +-#define VENUS0_VCODEC0_CLK 121 +-#define VENUS0_CORE0_VCODEC_CLK 122 +-#define VENUS0_CORE1_VCODEC_CLK 123 +-#define VENUS0_CORE2_VCODEC_CLK 124 +-#define AHB_CLK_SRC 125 +-#define FD_AHB_CLK 126 +- +-/* GDSCs */ +-#define VENUS_GDSC 0 +-#define VENUS_CORE0_GDSC 1 +-#define VENUS_CORE1_GDSC 2 +-#define VENUS_CORE2_GDSC 3 +-#define CAMSS_TOP_GDSC 4 +-#define MDSS_GDSC 5 +-#define JPEG_GDSC 6 +-#define VFE_GDSC 7 +-#define CPP_GDSC 8 +-#define OXILI_GX_GDSC 9 +-#define OXILI_CX_GDSC 10 +-#define FD_GDSC 11 +- +-/* Resets */ +-#define CAMSS_MICRO_BCR 0 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-msm8996.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-msm8996.h +deleted file mode 100644 +index d51f9ac70566..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-msm8996.h ++++ /dev/null +@@ -1,295 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2015, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H +-#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H +- +-#define MMPLL0_EARLY 0 +-#define MMPLL0_PLL 1 +-#define MMPLL1_EARLY 2 +-#define MMPLL1_PLL 3 +-#define MMPLL2_EARLY 4 +-#define MMPLL2_PLL 5 +-#define MMPLL3_EARLY 6 +-#define MMPLL3_PLL 7 +-#define MMPLL4_EARLY 8 +-#define MMPLL4_PLL 9 +-#define MMPLL5_EARLY 10 +-#define MMPLL5_PLL 11 +-#define MMPLL8_EARLY 12 +-#define MMPLL8_PLL 13 +-#define MMPLL9_EARLY 14 +-#define MMPLL9_PLL 15 +-#define AHB_CLK_SRC 16 +-#define AXI_CLK_SRC 17 +-#define MAXI_CLK_SRC 18 +-#define DSA_CORE_CLK_SRC 19 +-#define GFX3D_CLK_SRC 20 +-#define RBBMTIMER_CLK_SRC 21 +-#define ISENSE_CLK_SRC 22 +-#define RBCPR_CLK_SRC 23 +-#define VIDEO_CORE_CLK_SRC 24 +-#define VIDEO_SUBCORE0_CLK_SRC 25 +-#define VIDEO_SUBCORE1_CLK_SRC 26 +-#define PCLK0_CLK_SRC 27 +-#define PCLK1_CLK_SRC 28 +-#define MDP_CLK_SRC 29 +-#define EXTPCLK_CLK_SRC 30 +-#define VSYNC_CLK_SRC 31 +-#define HDMI_CLK_SRC 32 +-#define BYTE0_CLK_SRC 33 +-#define BYTE1_CLK_SRC 34 +-#define ESC0_CLK_SRC 35 +-#define ESC1_CLK_SRC 36 +-#define CAMSS_GP0_CLK_SRC 37 +-#define CAMSS_GP1_CLK_SRC 38 +-#define MCLK0_CLK_SRC 39 +-#define MCLK1_CLK_SRC 40 +-#define MCLK2_CLK_SRC 41 +-#define MCLK3_CLK_SRC 42 +-#define CCI_CLK_SRC 43 +-#define CSI0PHYTIMER_CLK_SRC 44 +-#define CSI1PHYTIMER_CLK_SRC 45 +-#define CSI2PHYTIMER_CLK_SRC 46 +-#define CSIPHY0_3P_CLK_SRC 47 +-#define CSIPHY1_3P_CLK_SRC 48 +-#define CSIPHY2_3P_CLK_SRC 49 +-#define JPEG0_CLK_SRC 50 +-#define JPEG2_CLK_SRC 51 +-#define JPEG_DMA_CLK_SRC 52 +-#define VFE0_CLK_SRC 53 +-#define VFE1_CLK_SRC 54 +-#define CPP_CLK_SRC 55 +-#define CSI0_CLK_SRC 56 +-#define CSI1_CLK_SRC 57 +-#define CSI2_CLK_SRC 58 +-#define CSI3_CLK_SRC 59 +-#define FD_CORE_CLK_SRC 60 +-#define MMSS_CXO_CLK 61 +-#define MMSS_SLEEPCLK_CLK 62 +-#define MMSS_MMAGIC_AHB_CLK 63 +-#define MMSS_MMAGIC_CFG_AHB_CLK 64 +-#define MMSS_MISC_AHB_CLK 65 +-#define MMSS_MISC_CXO_CLK 66 +-#define MMSS_BTO_AHB_CLK 67 +-#define MMSS_MMAGIC_AXI_CLK 68 +-#define MMSS_S0_AXI_CLK 69 +-#define MMSS_MMAGIC_MAXI_CLK 70 +-#define DSA_CORE_CLK 71 +-#define DSA_NOC_CFG_AHB_CLK 72 +-#define MMAGIC_CAMSS_AXI_CLK 73 +-#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 74 +-#define THROTTLE_CAMSS_CXO_CLK 75 +-#define THROTTLE_CAMSS_AHB_CLK 76 +-#define THROTTLE_CAMSS_AXI_CLK 77 +-#define SMMU_VFE_AHB_CLK 78 +-#define SMMU_VFE_AXI_CLK 79 +-#define SMMU_CPP_AHB_CLK 80 +-#define SMMU_CPP_AXI_CLK 81 +-#define SMMU_JPEG_AHB_CLK 82 +-#define SMMU_JPEG_AXI_CLK 83 +-#define MMAGIC_MDSS_AXI_CLK 84 +-#define MMAGIC_MDSS_NOC_CFG_AHB_CLK 85 +-#define THROTTLE_MDSS_CXO_CLK 86 +-#define THROTTLE_MDSS_AHB_CLK 87 +-#define THROTTLE_MDSS_AXI_CLK 88 +-#define SMMU_ROT_AHB_CLK 89 +-#define SMMU_ROT_AXI_CLK 90 +-#define SMMU_MDP_AHB_CLK 91 +-#define SMMU_MDP_AXI_CLK 92 +-#define MMAGIC_VIDEO_AXI_CLK 93 +-#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 94 +-#define THROTTLE_VIDEO_CXO_CLK 95 +-#define THROTTLE_VIDEO_AHB_CLK 96 +-#define THROTTLE_VIDEO_AXI_CLK 97 +-#define SMMU_VIDEO_AHB_CLK 98 +-#define SMMU_VIDEO_AXI_CLK 99 +-#define MMAGIC_BIMC_AXI_CLK 100 +-#define MMAGIC_BIMC_NOC_CFG_AHB_CLK 101 +-#define GPU_GX_GFX3D_CLK 102 +-#define GPU_GX_RBBMTIMER_CLK 103 +-#define GPU_AHB_CLK 104 +-#define GPU_AON_ISENSE_CLK 105 +-#define VMEM_MAXI_CLK 106 +-#define VMEM_AHB_CLK 107 +-#define MMSS_RBCPR_CLK 108 +-#define MMSS_RBCPR_AHB_CLK 109 +-#define VIDEO_CORE_CLK 110 +-#define VIDEO_AXI_CLK 111 +-#define VIDEO_MAXI_CLK 112 +-#define VIDEO_AHB_CLK 113 +-#define VIDEO_SUBCORE0_CLK 114 +-#define VIDEO_SUBCORE1_CLK 115 +-#define MDSS_AHB_CLK 116 +-#define MDSS_HDMI_AHB_CLK 117 +-#define MDSS_AXI_CLK 118 +-#define MDSS_PCLK0_CLK 119 +-#define MDSS_PCLK1_CLK 120 +-#define MDSS_MDP_CLK 121 +-#define MDSS_EXTPCLK_CLK 122 +-#define MDSS_VSYNC_CLK 123 +-#define MDSS_HDMI_CLK 124 +-#define MDSS_BYTE0_CLK 125 +-#define MDSS_BYTE1_CLK 126 +-#define MDSS_ESC0_CLK 127 +-#define MDSS_ESC1_CLK 128 +-#define CAMSS_TOP_AHB_CLK 129 +-#define CAMSS_AHB_CLK 130 +-#define CAMSS_MICRO_AHB_CLK 131 +-#define CAMSS_GP0_CLK 132 +-#define CAMSS_GP1_CLK 133 +-#define CAMSS_MCLK0_CLK 134 +-#define CAMSS_MCLK1_CLK 135 +-#define CAMSS_MCLK2_CLK 136 +-#define CAMSS_MCLK3_CLK 137 +-#define CAMSS_CCI_CLK 138 +-#define CAMSS_CCI_AHB_CLK 139 +-#define CAMSS_CSI0PHYTIMER_CLK 140 +-#define CAMSS_CSI1PHYTIMER_CLK 141 +-#define CAMSS_CSI2PHYTIMER_CLK 142 +-#define CAMSS_CSIPHY0_3P_CLK 143 +-#define CAMSS_CSIPHY1_3P_CLK 144 +-#define CAMSS_CSIPHY2_3P_CLK 145 +-#define CAMSS_JPEG0_CLK 146 +-#define CAMSS_JPEG2_CLK 147 +-#define CAMSS_JPEG_DMA_CLK 148 +-#define CAMSS_JPEG_AHB_CLK 149 +-#define CAMSS_JPEG_AXI_CLK 150 +-#define CAMSS_VFE_AHB_CLK 151 +-#define CAMSS_VFE_AXI_CLK 152 +-#define CAMSS_VFE0_CLK 153 +-#define CAMSS_VFE0_STREAM_CLK 154 +-#define CAMSS_VFE0_AHB_CLK 155 +-#define CAMSS_VFE1_CLK 156 +-#define CAMSS_VFE1_STREAM_CLK 157 +-#define CAMSS_VFE1_AHB_CLK 158 +-#define CAMSS_CSI_VFE0_CLK 159 +-#define CAMSS_CSI_VFE1_CLK 160 +-#define CAMSS_CPP_VBIF_AHB_CLK 161 +-#define CAMSS_CPP_AXI_CLK 162 +-#define CAMSS_CPP_CLK 163 +-#define CAMSS_CPP_AHB_CLK 164 +-#define CAMSS_CSI0_CLK 165 +-#define CAMSS_CSI0_AHB_CLK 166 +-#define CAMSS_CSI0PHY_CLK 167 +-#define CAMSS_CSI0RDI_CLK 168 +-#define CAMSS_CSI0PIX_CLK 169 +-#define CAMSS_CSI1_CLK 170 +-#define CAMSS_CSI1_AHB_CLK 171 +-#define CAMSS_CSI1PHY_CLK 172 +-#define CAMSS_CSI1RDI_CLK 173 +-#define CAMSS_CSI1PIX_CLK 174 +-#define CAMSS_CSI2_CLK 175 +-#define CAMSS_CSI2_AHB_CLK 176 +-#define CAMSS_CSI2PHY_CLK 177 +-#define CAMSS_CSI2RDI_CLK 178 +-#define CAMSS_CSI2PIX_CLK 179 +-#define CAMSS_CSI3_CLK 180 +-#define CAMSS_CSI3_AHB_CLK 181 +-#define CAMSS_CSI3PHY_CLK 182 +-#define CAMSS_CSI3RDI_CLK 183 +-#define CAMSS_CSI3PIX_CLK 184 +-#define CAMSS_ISPIF_AHB_CLK 185 +-#define FD_CORE_CLK 186 +-#define FD_CORE_UAR_CLK 187 +-#define FD_AHB_CLK 188 +-#define MMSS_SPDM_CSI0_CLK 189 +-#define MMSS_SPDM_JPEG_DMA_CLK 190 +-#define MMSS_SPDM_CPP_CLK 191 +-#define MMSS_SPDM_PCLK0_CLK 192 +-#define MMSS_SPDM_AHB_CLK 193 +-#define MMSS_SPDM_GFX3D_CLK 194 +-#define MMSS_SPDM_PCLK1_CLK 195 +-#define MMSS_SPDM_JPEG2_CLK 196 +-#define MMSS_SPDM_DEBUG_CLK 197 +-#define MMSS_SPDM_VFE1_CLK 198 +-#define MMSS_SPDM_VFE0_CLK 199 +-#define MMSS_SPDM_VIDEO_CORE_CLK 200 +-#define MMSS_SPDM_AXI_CLK 201 +-#define MMSS_SPDM_MDP_CLK 202 +-#define MMSS_SPDM_JPEG0_CLK 203 +-#define MMSS_SPDM_RM_AXI_CLK 204 +-#define MMSS_SPDM_RM_MAXI_CLK 205 +- +-#define MMAGICAHB_BCR 0 +-#define MMAGIC_CFG_BCR 1 +-#define MISC_BCR 2 +-#define BTO_BCR 3 +-#define MMAGICAXI_BCR 4 +-#define MMAGICMAXI_BCR 5 +-#define DSA_BCR 6 +-#define MMAGIC_CAMSS_BCR 7 +-#define THROTTLE_CAMSS_BCR 8 +-#define SMMU_VFE_BCR 9 +-#define SMMU_CPP_BCR 10 +-#define SMMU_JPEG_BCR 11 +-#define MMAGIC_MDSS_BCR 12 +-#define THROTTLE_MDSS_BCR 13 +-#define SMMU_ROT_BCR 14 +-#define SMMU_MDP_BCR 15 +-#define MMAGIC_VIDEO_BCR 16 +-#define THROTTLE_VIDEO_BCR 17 +-#define SMMU_VIDEO_BCR 18 +-#define MMAGIC_BIMC_BCR 19 +-#define GPU_GX_BCR 20 +-#define GPU_BCR 21 +-#define GPU_AON_BCR 22 +-#define VMEM_BCR 23 +-#define MMSS_RBCPR_BCR 24 +-#define VIDEO_BCR 25 +-#define MDSS_BCR 26 +-#define CAMSS_TOP_BCR 27 +-#define CAMSS_AHB_BCR 28 +-#define CAMSS_MICRO_BCR 29 +-#define CAMSS_CCI_BCR 30 +-#define CAMSS_PHY0_BCR 31 +-#define CAMSS_PHY1_BCR 32 +-#define CAMSS_PHY2_BCR 33 +-#define CAMSS_CSIPHY0_3P_BCR 34 +-#define CAMSS_CSIPHY1_3P_BCR 35 +-#define CAMSS_CSIPHY2_3P_BCR 36 +-#define CAMSS_JPEG_BCR 37 +-#define CAMSS_VFE_BCR 38 +-#define CAMSS_VFE0_BCR 39 +-#define CAMSS_VFE1_BCR 40 +-#define CAMSS_CSI_VFE0_BCR 41 +-#define CAMSS_CSI_VFE1_BCR 42 +-#define CAMSS_CPP_TOP_BCR 43 +-#define CAMSS_CPP_BCR 44 +-#define CAMSS_CSI0_BCR 45 +-#define CAMSS_CSI0RDI_BCR 46 +-#define CAMSS_CSI0PIX_BCR 47 +-#define CAMSS_CSI1_BCR 48 +-#define CAMSS_CSI1RDI_BCR 49 +-#define CAMSS_CSI1PIX_BCR 50 +-#define CAMSS_CSI2_BCR 51 +-#define CAMSS_CSI2RDI_BCR 52 +-#define CAMSS_CSI2PIX_BCR 53 +-#define CAMSS_CSI3_BCR 54 +-#define CAMSS_CSI3RDI_BCR 55 +-#define CAMSS_CSI3PIX_BCR 56 +-#define CAMSS_ISPIF_BCR 57 +-#define FD_BCR 58 +-#define MMSS_SPDM_RM_BCR 59 +- +-/* Indexes for GDSCs */ +-#define MMAGIC_VIDEO_GDSC 0 +-#define MMAGIC_MDSS_GDSC 1 +-#define MMAGIC_CAMSS_GDSC 2 +-#define GPU_GDSC 3 +-#define VENUS_GDSC 4 +-#define VENUS_CORE0_GDSC 5 +-#define VENUS_CORE1_GDSC 6 +-#define CAMSS_GDSC 7 +-#define VFE0_GDSC 8 +-#define VFE1_GDSC 9 +-#define JPEG_GDSC 10 +-#define CPP_GDSC 11 +-#define FD_GDSC 12 +-#define MDSS_GDSC 13 +-#define GPU_GX_GDSC 14 +-#define MMAGIC_BIMC_GDSC 15 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-msm8998.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-msm8998.h +deleted file mode 100644 +index ecbafdb930aa..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-msm8998.h ++++ /dev/null +@@ -1,210 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2019, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8998_H +-#define _DT_BINDINGS_CLK_MSM_MMCC_8998_H +- +-#define MMPLL0 0 +-#define MMPLL0_OUT_EVEN 1 +-#define MMPLL1 2 +-#define MMPLL1_OUT_EVEN 3 +-#define MMPLL3 4 +-#define MMPLL3_OUT_EVEN 5 +-#define MMPLL4 6 +-#define MMPLL4_OUT_EVEN 7 +-#define MMPLL5 8 +-#define MMPLL5_OUT_EVEN 9 +-#define MMPLL6 10 +-#define MMPLL6_OUT_EVEN 11 +-#define MMPLL7 12 +-#define MMPLL7_OUT_EVEN 13 +-#define MMPLL10 14 +-#define MMPLL10_OUT_EVEN 15 +-#define BYTE0_CLK_SRC 16 +-#define BYTE1_CLK_SRC 17 +-#define CCI_CLK_SRC 18 +-#define CPP_CLK_SRC 19 +-#define CSI0_CLK_SRC 20 +-#define CSI1_CLK_SRC 21 +-#define CSI2_CLK_SRC 22 +-#define CSI3_CLK_SRC 23 +-#define CSIPHY_CLK_SRC 24 +-#define CSI0PHYTIMER_CLK_SRC 25 +-#define CSI1PHYTIMER_CLK_SRC 26 +-#define CSI2PHYTIMER_CLK_SRC 27 +-#define DP_AUX_CLK_SRC 28 +-#define DP_CRYPTO_CLK_SRC 29 +-#define DP_LINK_CLK_SRC 30 +-#define DP_PIXEL_CLK_SRC 31 +-#define ESC0_CLK_SRC 32 +-#define ESC1_CLK_SRC 33 +-#define EXTPCLK_CLK_SRC 34 +-#define FD_CORE_CLK_SRC 35 +-#define HDMI_CLK_SRC 36 +-#define JPEG0_CLK_SRC 37 +-#define MAXI_CLK_SRC 38 +-#define MCLK0_CLK_SRC 39 +-#define MCLK1_CLK_SRC 40 +-#define MCLK2_CLK_SRC 41 +-#define MCLK3_CLK_SRC 42 +-#define MDP_CLK_SRC 43 +-#define VSYNC_CLK_SRC 44 +-#define AHB_CLK_SRC 45 +-#define AXI_CLK_SRC 46 +-#define PCLK0_CLK_SRC 47 +-#define PCLK1_CLK_SRC 48 +-#define ROT_CLK_SRC 49 +-#define VIDEO_CORE_CLK_SRC 50 +-#define VIDEO_SUBCORE0_CLK_SRC 51 +-#define VIDEO_SUBCORE1_CLK_SRC 52 +-#define VFE0_CLK_SRC 53 +-#define VFE1_CLK_SRC 54 +-#define MISC_AHB_CLK 55 +-#define VIDEO_CORE_CLK 56 +-#define VIDEO_AHB_CLK 57 +-#define VIDEO_AXI_CLK 58 +-#define VIDEO_MAXI_CLK 59 +-#define VIDEO_SUBCORE0_CLK 60 +-#define VIDEO_SUBCORE1_CLK 61 +-#define MDSS_AHB_CLK 62 +-#define MDSS_HDMI_DP_AHB_CLK 63 +-#define MDSS_AXI_CLK 64 +-#define MDSS_PCLK0_CLK 65 +-#define MDSS_PCLK1_CLK 66 +-#define MDSS_MDP_CLK 67 +-#define MDSS_MDP_LUT_CLK 68 +-#define MDSS_EXTPCLK_CLK 69 +-#define MDSS_VSYNC_CLK 70 +-#define MDSS_HDMI_CLK 71 +-#define MDSS_BYTE0_CLK 72 +-#define MDSS_BYTE1_CLK 73 +-#define MDSS_ESC0_CLK 74 +-#define MDSS_ESC1_CLK 75 +-#define MDSS_ROT_CLK 76 +-#define MDSS_DP_LINK_CLK 77 +-#define MDSS_DP_LINK_INTF_CLK 78 +-#define MDSS_DP_CRYPTO_CLK 79 +-#define MDSS_DP_PIXEL_CLK 80 +-#define MDSS_DP_AUX_CLK 81 +-#define MDSS_BYTE0_INTF_CLK 82 +-#define MDSS_BYTE1_INTF_CLK 83 +-#define CAMSS_CSI0PHYTIMER_CLK 84 +-#define CAMSS_CSI1PHYTIMER_CLK 85 +-#define CAMSS_CSI2PHYTIMER_CLK 86 +-#define CAMSS_CSI0_CLK 87 +-#define CAMSS_CSI0_AHB_CLK 88 +-#define CAMSS_CSI0RDI_CLK 89 +-#define CAMSS_CSI0PIX_CLK 90 +-#define CAMSS_CSI1_CLK 91 +-#define CAMSS_CSI1_AHB_CLK 92 +-#define CAMSS_CSI1RDI_CLK 93 +-#define CAMSS_CSI1PIX_CLK 94 +-#define CAMSS_CSI2_CLK 95 +-#define CAMSS_CSI2_AHB_CLK 96 +-#define CAMSS_CSI2RDI_CLK 97 +-#define CAMSS_CSI2PIX_CLK 98 +-#define CAMSS_CSI3_CLK 99 +-#define CAMSS_CSI3_AHB_CLK 100 +-#define CAMSS_CSI3RDI_CLK 101 +-#define CAMSS_CSI3PIX_CLK 102 +-#define CAMSS_ISPIF_AHB_CLK 103 +-#define CAMSS_CCI_CLK 104 +-#define CAMSS_CCI_AHB_CLK 105 +-#define CAMSS_MCLK0_CLK 106 +-#define CAMSS_MCLK1_CLK 107 +-#define CAMSS_MCLK2_CLK 108 +-#define CAMSS_MCLK3_CLK 109 +-#define CAMSS_TOP_AHB_CLK 110 +-#define CAMSS_AHB_CLK 111 +-#define CAMSS_MICRO_AHB_CLK 112 +-#define CAMSS_JPEG0_CLK 113 +-#define CAMSS_JPEG_AHB_CLK 114 +-#define CAMSS_JPEG_AXI_CLK 115 +-#define CAMSS_VFE0_AHB_CLK 116 +-#define CAMSS_VFE1_AHB_CLK 117 +-#define CAMSS_VFE0_CLK 118 +-#define CAMSS_VFE1_CLK 119 +-#define CAMSS_CPP_CLK 120 +-#define CAMSS_CPP_AHB_CLK 121 +-#define CAMSS_VFE_VBIF_AHB_CLK 122 +-#define CAMSS_VFE_VBIF_AXI_CLK 123 +-#define CAMSS_CPP_AXI_CLK 124 +-#define CAMSS_CPP_VBIF_AHB_CLK 125 +-#define CAMSS_CSI_VFE0_CLK 126 +-#define CAMSS_CSI_VFE1_CLK 127 +-#define CAMSS_VFE0_STREAM_CLK 128 +-#define CAMSS_VFE1_STREAM_CLK 129 +-#define CAMSS_CPHY_CSID0_CLK 130 +-#define CAMSS_CPHY_CSID1_CLK 131 +-#define CAMSS_CPHY_CSID2_CLK 132 +-#define CAMSS_CPHY_CSID3_CLK 133 +-#define CAMSS_CSIPHY0_CLK 134 +-#define CAMSS_CSIPHY1_CLK 135 +-#define CAMSS_CSIPHY2_CLK 136 +-#define FD_CORE_CLK 137 +-#define FD_CORE_UAR_CLK 138 +-#define FD_AHB_CLK 139 +-#define MNOC_AHB_CLK 140 +-#define BIMC_SMMU_AHB_CLK 141 +-#define BIMC_SMMU_AXI_CLK 142 +-#define MNOC_MAXI_CLK 143 +-#define VMEM_MAXI_CLK 144 +-#define VMEM_AHB_CLK 145 +- +-#define SPDM_BCR 0 +-#define SPDM_RM_BCR 1 +-#define MISC_BCR 2 +-#define VIDEO_TOP_BCR 3 +-#define THROTTLE_VIDEO_BCR 4 +-#define MDSS_BCR 5 +-#define THROTTLE_MDSS_BCR 6 +-#define CAMSS_PHY0_BCR 7 +-#define CAMSS_PHY1_BCR 8 +-#define CAMSS_PHY2_BCR 9 +-#define CAMSS_CSI0_BCR 10 +-#define CAMSS_CSI0RDI_BCR 11 +-#define CAMSS_CSI0PIX_BCR 12 +-#define CAMSS_CSI1_BCR 13 +-#define CAMSS_CSI1RDI_BCR 14 +-#define CAMSS_CSI1PIX_BCR 15 +-#define CAMSS_CSI2_BCR 16 +-#define CAMSS_CSI2RDI_BCR 17 +-#define CAMSS_CSI2PIX_BCR 18 +-#define CAMSS_CSI3_BCR 19 +-#define CAMSS_CSI3RDI_BCR 20 +-#define CAMSS_CSI3PIX_BCR 21 +-#define CAMSS_ISPIF_BCR 22 +-#define CAMSS_CCI_BCR 23 +-#define CAMSS_TOP_BCR 24 +-#define CAMSS_AHB_BCR 25 +-#define CAMSS_MICRO_BCR 26 +-#define CAMSS_JPEG_BCR 27 +-#define CAMSS_VFE0_BCR 28 +-#define CAMSS_VFE1_BCR 29 +-#define CAMSS_VFE_VBIF_BCR 30 +-#define CAMSS_CPP_TOP_BCR 31 +-#define CAMSS_CPP_BCR 32 +-#define CAMSS_CSI_VFE0_BCR 33 +-#define CAMSS_CSI_VFE1_BCR 34 +-#define CAMSS_FD_BCR 35 +-#define THROTTLE_CAMSS_BCR 36 +-#define MNOCAHB_BCR 37 +-#define MNOCAXI_BCR 38 +-#define BMIC_SMMU_BCR 39 +-#define MNOC_MAXI_BCR 40 +-#define VMEM_BCR 41 +-#define BTO_BCR 42 +- +-#define VIDEO_TOP_GDSC 1 +-#define VIDEO_SUBCORE0_GDSC 2 +-#define VIDEO_SUBCORE1_GDSC 3 +-#define MDSS_GDSC 4 +-#define CAMSS_TOP_GDSC 5 +-#define CAMSS_VFE0_GDSC 6 +-#define CAMSS_VFE1_GDSC 7 +-#define CAMSS_CPP_GDSC 8 +-#define BIMC_SMMU_GDSC 9 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-sdm660.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-sdm660.h +deleted file mode 100644 +index f9dbc21cb5c7..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-sdm660.h ++++ /dev/null +@@ -1,162 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_MSM_MMCC_660_H +-#define _DT_BINDINGS_CLK_MSM_MMCC_660_H +- +-#define AHB_CLK_SRC 0 +-#define BYTE0_CLK_SRC 1 +-#define BYTE1_CLK_SRC 2 +-#define CAMSS_GP0_CLK_SRC 3 +-#define CAMSS_GP1_CLK_SRC 4 +-#define CCI_CLK_SRC 5 +-#define CPP_CLK_SRC 6 +-#define CSI0_CLK_SRC 7 +-#define CSI0PHYTIMER_CLK_SRC 8 +-#define CSI1_CLK_SRC 9 +-#define CSI1PHYTIMER_CLK_SRC 10 +-#define CSI2_CLK_SRC 11 +-#define CSI2PHYTIMER_CLK_SRC 12 +-#define CSI3_CLK_SRC 13 +-#define CSIPHY_CLK_SRC 14 +-#define DP_AUX_CLK_SRC 15 +-#define DP_CRYPTO_CLK_SRC 16 +-#define DP_GTC_CLK_SRC 17 +-#define DP_LINK_CLK_SRC 18 +-#define DP_PIXEL_CLK_SRC 19 +-#define ESC0_CLK_SRC 20 +-#define ESC1_CLK_SRC 21 +-#define JPEG0_CLK_SRC 22 +-#define MCLK0_CLK_SRC 23 +-#define MCLK1_CLK_SRC 24 +-#define MCLK2_CLK_SRC 25 +-#define MCLK3_CLK_SRC 26 +-#define MDP_CLK_SRC 27 +-#define MMPLL0_PLL 28 +-#define MMPLL10_PLL 29 +-#define MMPLL1_PLL 30 +-#define MMPLL3_PLL 31 +-#define MMPLL4_PLL 32 +-#define MMPLL5_PLL 33 +-#define MMPLL6_PLL 34 +-#define MMPLL7_PLL 35 +-#define MMPLL8_PLL 36 +-#define BIMC_SMMU_AHB_CLK 37 +-#define BIMC_SMMU_AXI_CLK 38 +-#define CAMSS_AHB_CLK 39 +-#define CAMSS_CCI_AHB_CLK 40 +-#define CAMSS_CCI_CLK 41 +-#define CAMSS_CPHY_CSID0_CLK 42 +-#define CAMSS_CPHY_CSID1_CLK 43 +-#define CAMSS_CPHY_CSID2_CLK 44 +-#define CAMSS_CPHY_CSID3_CLK 45 +-#define CAMSS_CPP_AHB_CLK 46 +-#define CAMSS_CPP_AXI_CLK 47 +-#define CAMSS_CPP_CLK 48 +-#define CAMSS_CPP_VBIF_AHB_CLK 49 +-#define CAMSS_CSI0_AHB_CLK 50 +-#define CAMSS_CSI0_CLK 51 +-#define CAMSS_CSI0PHYTIMER_CLK 52 +-#define CAMSS_CSI0PIX_CLK 53 +-#define CAMSS_CSI0RDI_CLK 54 +-#define CAMSS_CSI1_AHB_CLK 55 +-#define CAMSS_CSI1_CLK 56 +-#define CAMSS_CSI1PHYTIMER_CLK 57 +-#define CAMSS_CSI1PIX_CLK 58 +-#define CAMSS_CSI1RDI_CLK 59 +-#define CAMSS_CSI2_AHB_CLK 60 +-#define CAMSS_CSI2_CLK 61 +-#define CAMSS_CSI2PHYTIMER_CLK 62 +-#define CAMSS_CSI2PIX_CLK 63 +-#define CAMSS_CSI2RDI_CLK 64 +-#define CAMSS_CSI3_AHB_CLK 65 +-#define CAMSS_CSI3_CLK 66 +-#define CAMSS_CSI3PIX_CLK 67 +-#define CAMSS_CSI3RDI_CLK 68 +-#define CAMSS_CSI_VFE0_CLK 69 +-#define CAMSS_CSI_VFE1_CLK 70 +-#define CAMSS_CSIPHY0_CLK 71 +-#define CAMSS_CSIPHY1_CLK 72 +-#define CAMSS_CSIPHY2_CLK 73 +-#define CAMSS_GP0_CLK 74 +-#define CAMSS_GP1_CLK 75 +-#define CAMSS_ISPIF_AHB_CLK 76 +-#define CAMSS_JPEG0_CLK 77 +-#define CAMSS_JPEG_AHB_CLK 78 +-#define CAMSS_JPEG_AXI_CLK 79 +-#define CAMSS_MCLK0_CLK 80 +-#define CAMSS_MCLK1_CLK 81 +-#define CAMSS_MCLK2_CLK 82 +-#define CAMSS_MCLK3_CLK 83 +-#define CAMSS_MICRO_AHB_CLK 84 +-#define CAMSS_TOP_AHB_CLK 85 +-#define CAMSS_VFE0_AHB_CLK 86 +-#define CAMSS_VFE0_CLK 87 +-#define CAMSS_VFE0_STREAM_CLK 88 +-#define CAMSS_VFE1_AHB_CLK 89 +-#define CAMSS_VFE1_CLK 90 +-#define CAMSS_VFE1_STREAM_CLK 91 +-#define CAMSS_VFE_VBIF_AHB_CLK 92 +-#define CAMSS_VFE_VBIF_AXI_CLK 93 +-#define CSIPHY_AHB2CRIF_CLK 94 +-#define CXO_CLK 95 +-#define MDSS_AHB_CLK 96 +-#define MDSS_AXI_CLK 97 +-#define MDSS_BYTE0_CLK 98 +-#define MDSS_BYTE0_INTF_CLK 99 +-#define MDSS_BYTE0_INTF_DIV_CLK 100 +-#define MDSS_BYTE1_CLK 101 +-#define MDSS_BYTE1_INTF_CLK 102 +-#define MDSS_DP_AUX_CLK 103 +-#define MDSS_DP_CRYPTO_CLK 104 +-#define MDSS_DP_GTC_CLK 105 +-#define MDSS_DP_LINK_CLK 106 +-#define MDSS_DP_LINK_INTF_CLK 107 +-#define MDSS_DP_PIXEL_CLK 108 +-#define MDSS_ESC0_CLK 109 +-#define MDSS_ESC1_CLK 110 +-#define MDSS_HDMI_DP_AHB_CLK 111 +-#define MDSS_MDP_CLK 112 +-#define MDSS_PCLK0_CLK 113 +-#define MDSS_PCLK1_CLK 114 +-#define MDSS_ROT_CLK 115 +-#define MDSS_VSYNC_CLK 116 +-#define MISC_AHB_CLK 117 +-#define MISC_CXO_CLK 118 +-#define MNOC_AHB_CLK 119 +-#define SNOC_DVM_AXI_CLK 120 +-#define THROTTLE_CAMSS_AHB_CLK 121 +-#define THROTTLE_CAMSS_AXI_CLK 122 +-#define THROTTLE_MDSS_AHB_CLK 123 +-#define THROTTLE_MDSS_AXI_CLK 124 +-#define THROTTLE_VIDEO_AHB_CLK 125 +-#define THROTTLE_VIDEO_AXI_CLK 126 +-#define VIDEO_AHB_CLK 127 +-#define VIDEO_AXI_CLK 128 +-#define VIDEO_CORE_CLK 129 +-#define VIDEO_SUBCORE0_CLK 130 +-#define PCLK0_CLK_SRC 131 +-#define PCLK1_CLK_SRC 132 +-#define ROT_CLK_SRC 133 +-#define VFE0_CLK_SRC 134 +-#define VFE1_CLK_SRC 135 +-#define VIDEO_CORE_CLK_SRC 136 +-#define VSYNC_CLK_SRC 137 +-#define MDSS_BYTE1_INTF_DIV_CLK 138 +-#define AXI_CLK_SRC 139 +- +-#define VENUS_GDSC 0 +-#define VENUS_CORE0_GDSC 1 +-#define MDSS_GDSC 2 +-#define CAMSS_TOP_GDSC 3 +-#define CAMSS_VFE0_GDSC 4 +-#define CAMSS_VFE1_GDSC 5 +-#define CAMSS_CPP_GDSC 6 +-#define BIMC_SMMU_GDSC 7 +- +-#define CAMSS_MICRO_BCR 0 +- +-#endif +- +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mss-sc7180.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mss-sc7180.h +deleted file mode 100644 +index f15a9ded2961..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mss-sc7180.h ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_MSS_SC7180_H +-#define _DT_BINDINGS_CLK_QCOM_MSS_SC7180_H +- +-#define MSS_AXI_CRYPTO_CLK 0 +-#define MSS_AXI_NAV_CLK 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,q6sstopcc-qcs404.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,q6sstopcc-qcs404.h +deleted file mode 100644 +index c6f5290f0914..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,q6sstopcc-qcs404.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2018, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_Q6SSTOP_QCS404_H +-#define _DT_BINDINGS_CLK_Q6SSTOP_QCS404_H +- +-#define LCC_AHBFABRIC_CBC_CLK 0 +-#define LCC_Q6SS_AHBS_CBC_CLK 1 +-#define LCC_Q6SS_TCM_SLAVE_CBC_CLK 2 +-#define LCC_Q6SS_AHBM_CBC_CLK 3 +-#define LCC_Q6SS_AXIM_CBC_CLK 4 +-#define LCC_Q6SS_BCR_SLEEP_CLK 5 +-#define TCSR_Q6SS_LCC_CBCR_CLK 6 +- +-#define Q6SSTOP_BCR_RESET 1 +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,rpmcc.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,rpmcc.h +deleted file mode 100644 +index aa834d516234..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,rpmcc.h ++++ /dev/null +@@ -1,163 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2015 Linaro Limited +- */ +- +-#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H +-#define _DT_BINDINGS_CLK_MSM_RPMCC_H +- +-/* RPM clocks */ +-#define RPM_PXO_CLK 0 +-#define RPM_PXO_A_CLK 1 +-#define RPM_CXO_CLK 2 +-#define RPM_CXO_A_CLK 3 +-#define RPM_APPS_FABRIC_CLK 4 +-#define RPM_APPS_FABRIC_A_CLK 5 +-#define RPM_CFPB_CLK 6 +-#define RPM_CFPB_A_CLK 7 +-#define RPM_QDSS_CLK 8 +-#define RPM_QDSS_A_CLK 9 +-#define RPM_DAYTONA_FABRIC_CLK 10 +-#define RPM_DAYTONA_FABRIC_A_CLK 11 +-#define RPM_EBI1_CLK 12 +-#define RPM_EBI1_A_CLK 13 +-#define RPM_MM_FABRIC_CLK 14 +-#define RPM_MM_FABRIC_A_CLK 15 +-#define RPM_MMFPB_CLK 16 +-#define RPM_MMFPB_A_CLK 17 +-#define RPM_SYS_FABRIC_CLK 18 +-#define RPM_SYS_FABRIC_A_CLK 19 +-#define RPM_SFPB_CLK 20 +-#define RPM_SFPB_A_CLK 21 +-#define RPM_SMI_CLK 22 +-#define RPM_SMI_A_CLK 23 +-#define RPM_PLL4_CLK 24 +-#define RPM_XO_D0 25 +-#define RPM_XO_D1 26 +-#define RPM_XO_A0 27 +-#define RPM_XO_A1 28 +-#define RPM_XO_A2 29 +-#define RPM_NSS_FABRIC_0_CLK 30 +-#define RPM_NSS_FABRIC_0_A_CLK 31 +-#define RPM_NSS_FABRIC_1_CLK 32 +-#define RPM_NSS_FABRIC_1_A_CLK 33 +- +-/* SMD RPM clocks */ +-#define RPM_SMD_XO_CLK_SRC 0 +-#define RPM_SMD_XO_A_CLK_SRC 1 +-#define RPM_SMD_PCNOC_CLK 2 +-#define RPM_SMD_PCNOC_A_CLK 3 +-#define RPM_SMD_SNOC_CLK 4 +-#define RPM_SMD_SNOC_A_CLK 5 +-#define RPM_SMD_BIMC_CLK 6 +-#define RPM_SMD_BIMC_A_CLK 7 +-#define RPM_SMD_QDSS_CLK 8 +-#define RPM_SMD_QDSS_A_CLK 9 +-#define RPM_SMD_BB_CLK1 10 +-#define RPM_SMD_BB_CLK1_A 11 +-#define RPM_SMD_BB_CLK2 12 +-#define RPM_SMD_BB_CLK2_A 13 +-#define RPM_SMD_RF_CLK1 14 +-#define RPM_SMD_RF_CLK1_A 15 +-#define RPM_SMD_RF_CLK2 16 +-#define RPM_SMD_RF_CLK2_A 17 +-#define RPM_SMD_BB_CLK1_PIN 18 +-#define RPM_SMD_BB_CLK1_A_PIN 19 +-#define RPM_SMD_BB_CLK2_PIN 20 +-#define RPM_SMD_BB_CLK2_A_PIN 21 +-#define RPM_SMD_RF_CLK1_PIN 22 +-#define RPM_SMD_RF_CLK1_A_PIN 23 +-#define RPM_SMD_RF_CLK2_PIN 24 +-#define RPM_SMD_RF_CLK2_A_PIN 25 +-#define RPM_SMD_PNOC_CLK 26 +-#define RPM_SMD_PNOC_A_CLK 27 +-#define RPM_SMD_CNOC_CLK 28 +-#define RPM_SMD_CNOC_A_CLK 29 +-#define RPM_SMD_MMSSNOC_AHB_CLK 30 +-#define RPM_SMD_MMSSNOC_AHB_A_CLK 31 +-#define RPM_SMD_GFX3D_CLK_SRC 32 +-#define RPM_SMD_GFX3D_A_CLK_SRC 33 +-#define RPM_SMD_OCMEMGX_CLK 34 +-#define RPM_SMD_OCMEMGX_A_CLK 35 +-#define RPM_SMD_CXO_D0 36 +-#define RPM_SMD_CXO_D0_A 37 +-#define RPM_SMD_CXO_D1 38 +-#define RPM_SMD_CXO_D1_A 39 +-#define RPM_SMD_CXO_A0 40 +-#define RPM_SMD_CXO_A0_A 41 +-#define RPM_SMD_CXO_A1 42 +-#define RPM_SMD_CXO_A1_A 43 +-#define RPM_SMD_CXO_A2 44 +-#define RPM_SMD_CXO_A2_A 45 +-#define RPM_SMD_DIV_CLK1 46 +-#define RPM_SMD_DIV_A_CLK1 47 +-#define RPM_SMD_DIV_CLK2 48 +-#define RPM_SMD_DIV_A_CLK2 49 +-#define RPM_SMD_DIFF_CLK 50 +-#define RPM_SMD_DIFF_A_CLK 51 +-#define RPM_SMD_CXO_D0_PIN 52 +-#define RPM_SMD_CXO_D0_A_PIN 53 +-#define RPM_SMD_CXO_D1_PIN 54 +-#define RPM_SMD_CXO_D1_A_PIN 55 +-#define RPM_SMD_CXO_A0_PIN 56 +-#define RPM_SMD_CXO_A0_A_PIN 57 +-#define RPM_SMD_CXO_A1_PIN 58 +-#define RPM_SMD_CXO_A1_A_PIN 59 +-#define RPM_SMD_CXO_A2_PIN 60 +-#define RPM_SMD_CXO_A2_A_PIN 61 +-#define RPM_SMD_AGGR1_NOC_CLK 62 +-#define RPM_SMD_AGGR1_NOC_A_CLK 63 +-#define RPM_SMD_AGGR2_NOC_CLK 64 +-#define RPM_SMD_AGGR2_NOC_A_CLK 65 +-#define RPM_SMD_MMAXI_CLK 66 +-#define RPM_SMD_MMAXI_A_CLK 67 +-#define RPM_SMD_IPA_CLK 68 +-#define RPM_SMD_IPA_A_CLK 69 +-#define RPM_SMD_CE1_CLK 70 +-#define RPM_SMD_CE1_A_CLK 71 +-#define RPM_SMD_DIV_CLK3 72 +-#define RPM_SMD_DIV_A_CLK3 73 +-#define RPM_SMD_LN_BB_CLK 74 +-#define RPM_SMD_LN_BB_A_CLK 75 +-#define RPM_SMD_BIMC_GPU_CLK 76 +-#define RPM_SMD_BIMC_GPU_A_CLK 77 +-#define RPM_SMD_QPIC_CLK 78 +-#define RPM_SMD_QPIC_CLK_A 79 +-#define RPM_SMD_LN_BB_CLK1 80 +-#define RPM_SMD_LN_BB_CLK1_A 81 +-#define RPM_SMD_LN_BB_CLK2 82 +-#define RPM_SMD_LN_BB_CLK2_A 83 +-#define RPM_SMD_LN_BB_CLK3_PIN 84 +-#define RPM_SMD_LN_BB_CLK3_A_PIN 85 +-#define RPM_SMD_RF_CLK3 86 +-#define RPM_SMD_RF_CLK3_A 87 +-#define RPM_SMD_RF_CLK3_PIN 88 +-#define RPM_SMD_RF_CLK3_A_PIN 89 +-#define RPM_SMD_MMSSNOC_AXI_CLK 90 +-#define RPM_SMD_MMSSNOC_AXI_CLK_A 91 +-#define RPM_SMD_CNOC_PERIPH_CLK 92 +-#define RPM_SMD_CNOC_PERIPH_A_CLK 93 +-#define RPM_SMD_LN_BB_CLK3 94 +-#define RPM_SMD_LN_BB_CLK3_A 95 +-#define RPM_SMD_LN_BB_CLK1_PIN 96 +-#define RPM_SMD_LN_BB_CLK1_A_PIN 97 +-#define RPM_SMD_LN_BB_CLK2_PIN 98 +-#define RPM_SMD_LN_BB_CLK2_A_PIN 99 +-#define RPM_SMD_SYSMMNOC_CLK 100 +-#define RPM_SMD_SYSMMNOC_A_CLK 101 +-#define RPM_SMD_CE2_CLK 102 +-#define RPM_SMD_CE2_A_CLK 103 +-#define RPM_SMD_CE3_CLK 104 +-#define RPM_SMD_CE3_A_CLK 105 +-#define RPM_SMD_QUP_CLK 106 +-#define RPM_SMD_QUP_A_CLK 107 +-#define RPM_SMD_MMRT_CLK 108 +-#define RPM_SMD_MMRT_A_CLK 109 +-#define RPM_SMD_MMNRT_CLK 110 +-#define RPM_SMD_MMNRT_A_CLK 111 +-#define RPM_SMD_SNOC_PERIPH_CLK 112 +-#define RPM_SMD_SNOC_PERIPH_A_CLK 113 +-#define RPM_SMD_SNOC_LPASS_CLK 114 +-#define RPM_SMD_SNOC_LPASS_A_CLK 115 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,rpmh.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,rpmh.h +deleted file mode 100644 +index 0a7d1be0d124..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,rpmh.h ++++ /dev/null +@@ -1,37 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. */ +- +- +-#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H +-#define _DT_BINDINGS_CLK_MSM_RPMH_H +- +-/* RPMh controlled clocks */ +-#define RPMH_CXO_CLK 0 +-#define RPMH_CXO_CLK_A 1 +-#define RPMH_LN_BB_CLK2 2 +-#define RPMH_LN_BB_CLK2_A 3 +-#define RPMH_LN_BB_CLK3 4 +-#define RPMH_LN_BB_CLK3_A 5 +-#define RPMH_RF_CLK1 6 +-#define RPMH_RF_CLK1_A 7 +-#define RPMH_RF_CLK2 8 +-#define RPMH_RF_CLK2_A 9 +-#define RPMH_RF_CLK3 10 +-#define RPMH_RF_CLK3_A 11 +-#define RPMH_IPA_CLK 12 +-#define RPMH_LN_BB_CLK1 13 +-#define RPMH_LN_BB_CLK1_A 14 +-#define RPMH_CE_CLK 15 +-#define RPMH_QPIC_CLK 16 +-#define RPMH_DIV_CLK1 17 +-#define RPMH_DIV_CLK1_A 18 +-#define RPMH_RF_CLK4 19 +-#define RPMH_RF_CLK4_A 20 +-#define RPMH_RF_CLK5 21 +-#define RPMH_RF_CLK5_A 22 +-#define RPMH_PKA_CLK 23 +-#define RPMH_HWKM_CLK 24 +-#define RPMH_QLINK_CLK 25 +-#define RPMH_QLINK_CLK_A 26 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,sm8250-lpass-aoncc.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,sm8250-lpass-aoncc.h +deleted file mode 100644 +index f5a1cfac8612..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,sm8250-lpass-aoncc.h ++++ /dev/null +@@ -1,11 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +- +-#ifndef _DT_BINDINGS_CLK_LPASS_AONCC_SM8250_H +-#define _DT_BINDINGS_CLK_LPASS_AONCC_SM8250_H +- +-/* from AOCC */ +-#define LPASS_CDC_VA_MCLK 0 +-#define LPASS_CDC_TX_NPL 1 +-#define LPASS_CDC_TX_MCLK 2 +- +-#endif /* _DT_BINDINGS_CLK_LPASS_AONCC_SM8250_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,sm8250-lpass-audiocc.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,sm8250-lpass-audiocc.h +deleted file mode 100644 +index a1aa6cb5d840..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,sm8250-lpass-audiocc.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +- +-#ifndef _DT_BINDINGS_CLK_LPASS_AUDIOCC_SM8250_H +-#define _DT_BINDINGS_CLK_LPASS_AUDIOCC_SM8250_H +- +-/* From AudioCC */ +-#define LPASS_CDC_WSA_NPL 0 +-#define LPASS_CDC_WSA_MCLK 1 +-#define LPASS_CDC_RX_MCLK 2 +-#define LPASS_CDC_RX_NPL 3 +-#define LPASS_CDC_RX_MCLK_MCLK2 4 +- +-#endif /* _DT_BINDINGS_CLK_LPASS_AUDIOCC_SM8250_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,turingcc-qcs404.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,turingcc-qcs404.h +deleted file mode 100644 +index 838faef57c67..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,turingcc-qcs404.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2019, Linaro Ltd +- */ +- +-#ifndef _DT_BINDINGS_CLK_TURING_QCS404_H +-#define _DT_BINDINGS_CLK_TURING_QCS404_H +- +-#define TURING_Q6SS_Q6_AXIM_CLK 0 +-#define TURING_Q6SS_AHBM_AON_CLK 1 +-#define TURING_WRAPPER_AON_CLK 2 +-#define TURING_Q6SS_AHBS_AON_CLK 3 +-#define TURING_WRAPPER_QOS_AHBS_AON_CLK 4 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,videocc-sc7180.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,videocc-sc7180.h +deleted file mode 100644 +index 7acaf1366b13..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,videocc-sc7180.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2019, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SC7180_H +-#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SC7180_H +- +-/* VIDEO_CC clocks */ +-#define VIDEO_PLL0 0 +-#define VIDEO_CC_VCODEC0_AXI_CLK 1 +-#define VIDEO_CC_VCODEC0_CORE_CLK 2 +-#define VIDEO_CC_VENUS_AHB_CLK 3 +-#define VIDEO_CC_VENUS_CLK_SRC 4 +-#define VIDEO_CC_VENUS_CTL_AXI_CLK 5 +-#define VIDEO_CC_VENUS_CTL_CORE_CLK 6 +-#define VIDEO_CC_XO_CLK 7 +- +-/* VIDEO_CC GDSCRs */ +-#define VENUS_GDSC 0 +-#define VCODEC0_GDSC 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,videocc-sc7280.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,videocc-sc7280.h +deleted file mode 100644 +index 9e00c3a5f75e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,videocc-sc7280.h ++++ /dev/null +@@ -1,27 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +-/* +- * Copyright (c) 2021, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SC7280_H +-#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SC7280_H +- +-/* VIDEO_CC clocks */ +-#define VIDEO_PLL0 0 +-#define VIDEO_CC_IRIS_AHB_CLK 1 +-#define VIDEO_CC_IRIS_CLK_SRC 2 +-#define VIDEO_CC_MVS0_AXI_CLK 3 +-#define VIDEO_CC_MVS0_CORE_CLK 4 +-#define VIDEO_CC_MVSC_CORE_CLK 5 +-#define VIDEO_CC_MVSC_CTL_AXI_CLK 6 +-#define VIDEO_CC_SLEEP_CLK 7 +-#define VIDEO_CC_SLEEP_CLK_SRC 8 +-#define VIDEO_CC_VENUS_AHB_CLK 9 +-#define VIDEO_CC_XO_CLK 10 +-#define VIDEO_CC_XO_CLK_SRC 11 +- +-/* VIDEO_CC power domains */ +-#define MVS0_GDSC 0 +-#define MVSC_GDSC 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,videocc-sdm845.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,videocc-sdm845.h +deleted file mode 100644 +index 1b868165e8ce..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,videocc-sdm845.h ++++ /dev/null +@@ -1,35 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2018, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H +-#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H +- +-/* VIDEO_CC clock registers */ +-#define VIDEO_CC_APB_CLK 0 +-#define VIDEO_CC_AT_CLK 1 +-#define VIDEO_CC_QDSS_TRIG_CLK 2 +-#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK 3 +-#define VIDEO_CC_VCODEC0_AXI_CLK 4 +-#define VIDEO_CC_VCODEC0_CORE_CLK 5 +-#define VIDEO_CC_VCODEC1_AXI_CLK 6 +-#define VIDEO_CC_VCODEC1_CORE_CLK 7 +-#define VIDEO_CC_VENUS_AHB_CLK 8 +-#define VIDEO_CC_VENUS_CLK_SRC 9 +-#define VIDEO_CC_VENUS_CTL_AXI_CLK 10 +-#define VIDEO_CC_VENUS_CTL_CORE_CLK 11 +-#define VIDEO_PLL0 12 +- +-/* VIDEO_CC Resets */ +-#define VIDEO_CC_VENUS_BCR 0 +-#define VIDEO_CC_VCODEC0_BCR 1 +-#define VIDEO_CC_VCODEC1_BCR 2 +-#define VIDEO_CC_INTERFACE_BCR 3 +- +-/* VIDEO_CC GDSCRs */ +-#define VENUS_GDSC 0 +-#define VCODEC0_GDSC 1 +-#define VCODEC1_GDSC 2 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,videocc-sm8150.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,videocc-sm8150.h +deleted file mode 100644 +index e24ee840cfdb..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,videocc-sm8150.h ++++ /dev/null +@@ -1,25 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8150_H +-#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8150_H +- +-/* VIDEO_CC clocks */ +-#define VIDEO_CC_IRIS_AHB_CLK 0 +-#define VIDEO_CC_IRIS_CLK_SRC 1 +-#define VIDEO_CC_MVS0_CORE_CLK 2 +-#define VIDEO_CC_MVS1_CORE_CLK 3 +-#define VIDEO_CC_MVSC_CORE_CLK 4 +-#define VIDEO_CC_PLL0 5 +- +-/* VIDEO_CC Resets */ +-#define VIDEO_CC_MVSC_CORE_CLK_BCR 0 +- +-/* VIDEO_CC GDSCRs */ +-#define VENUS_GDSC 0 +-#define VCODEC0_GDSC 1 +-#define VCODEC1_GDSC 2 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,videocc-sm8250.h b/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,videocc-sm8250.h +deleted file mode 100644 +index 8d321ac3b1fa..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,videocc-sm8250.h ++++ /dev/null +@@ -1,36 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8250_H +-#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8250_H +- +-/* VIDEO_CC clocks */ +-#define VIDEO_CC_MVS0_CLK_SRC 0 +-#define VIDEO_CC_MVS0C_CLK 1 +-#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 2 +-#define VIDEO_CC_MVS1_CLK_SRC 3 +-#define VIDEO_CC_MVS1_DIV2_CLK 4 +-#define VIDEO_CC_MVS1C_CLK 5 +-#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 6 +-#define VIDEO_CC_PLL0 7 +-#define VIDEO_CC_PLL1 8 +-#define VIDEO_CC_MVS0_DIV_CLK_SRC 9 +-#define VIDEO_CC_MVS0_CLK 10 +- +-/* VIDEO_CC resets */ +-#define VIDEO_CC_CVP_INTERFACE_BCR 0 +-#define VIDEO_CC_CVP_MVS0_BCR 1 +-#define VIDEO_CC_MVS0C_CLK_ARES 2 +-#define VIDEO_CC_CVP_MVS0C_BCR 3 +-#define VIDEO_CC_CVP_MVS1_BCR 4 +-#define VIDEO_CC_MVS1C_CLK_ARES 5 +-#define VIDEO_CC_CVP_MVS1C_BCR 6 +- +-#define MVS0C_GDSC 0 +-#define MVS1C_GDSC 1 +-#define MVS0_GDSC 2 +-#define MVS1_GDSC 3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r7s72100-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r7s72100-clock.h +deleted file mode 100644 +index a267ac250143..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r7s72100-clock.h ++++ /dev/null +@@ -1,112 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 +- * +- * Copyright (C) 2014 Renesas Solutions Corp. +- * Copyright (C) 2014 Wolfram Sang, Sang Engineering +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__ +-#define __DT_BINDINGS_CLOCK_R7S72100_H__ +- +-#define R7S72100_CLK_PLL 0 +-#define R7S72100_CLK_I 1 +-#define R7S72100_CLK_G 2 +- +-/* MSTP2 */ +-#define R7S72100_CLK_CORESIGHT 0 +- +-/* MSTP3 */ +-#define R7S72100_CLK_IEBUS 7 +-#define R7S72100_CLK_IRDA 6 +-#define R7S72100_CLK_LIN0 5 +-#define R7S72100_CLK_LIN1 4 +-#define R7S72100_CLK_MTU2 3 +-#define R7S72100_CLK_CAN 2 +-#define R7S72100_CLK_ADCPWR 1 +-#define R7S72100_CLK_PWM 0 +- +-/* MSTP4 */ +-#define R7S72100_CLK_SCIF0 7 +-#define R7S72100_CLK_SCIF1 6 +-#define R7S72100_CLK_SCIF2 5 +-#define R7S72100_CLK_SCIF3 4 +-#define R7S72100_CLK_SCIF4 3 +-#define R7S72100_CLK_SCIF5 2 +-#define R7S72100_CLK_SCIF6 1 +-#define R7S72100_CLK_SCIF7 0 +- +-/* MSTP5 */ +-#define R7S72100_CLK_SCI0 7 +-#define R7S72100_CLK_SCI1 6 +-#define R7S72100_CLK_SG0 5 +-#define R7S72100_CLK_SG1 4 +-#define R7S72100_CLK_SG2 3 +-#define R7S72100_CLK_SG3 2 +-#define R7S72100_CLK_OSTM0 1 +-#define R7S72100_CLK_OSTM1 0 +- +-/* MSTP6 */ +-#define R7S72100_CLK_ADC 7 +-#define R7S72100_CLK_CEU 6 +-#define R7S72100_CLK_DOC0 5 +-#define R7S72100_CLK_DOC1 4 +-#define R7S72100_CLK_DRC0 3 +-#define R7S72100_CLK_DRC1 2 +-#define R7S72100_CLK_JCU 1 +-#define R7S72100_CLK_RTC 0 +- +-/* MSTP7 */ +-#define R7S72100_CLK_VDEC0 7 +-#define R7S72100_CLK_VDEC1 6 +-#define R7S72100_CLK_ETHER 4 +-#define R7S72100_CLK_NAND 3 +-#define R7S72100_CLK_USB0 1 +-#define R7S72100_CLK_USB1 0 +- +-/* MSTP8 */ +-#define R7S72100_CLK_IMR0 7 +-#define R7S72100_CLK_IMR1 6 +-#define R7S72100_CLK_IMRDISP 5 +-#define R7S72100_CLK_MMCIF 4 +-#define R7S72100_CLK_MLB 3 +-#define R7S72100_CLK_ETHAVB 2 +-#define R7S72100_CLK_SCUX 1 +- +-/* MSTP9 */ +-#define R7S72100_CLK_I2C0 7 +-#define R7S72100_CLK_I2C1 6 +-#define R7S72100_CLK_I2C2 5 +-#define R7S72100_CLK_I2C3 4 +-#define R7S72100_CLK_SPIBSC0 3 +-#define R7S72100_CLK_SPIBSC1 2 +-#define R7S72100_CLK_VDC50 1 /* and LVDS */ +-#define R7S72100_CLK_VDC51 0 +- +-/* MSTP10 */ +-#define R7S72100_CLK_SPI0 7 +-#define R7S72100_CLK_SPI1 6 +-#define R7S72100_CLK_SPI2 5 +-#define R7S72100_CLK_SPI3 4 +-#define R7S72100_CLK_SPI4 3 +-#define R7S72100_CLK_CDROM 2 +-#define R7S72100_CLK_SPDIF 1 +-#define R7S72100_CLK_RGPVG2 0 +- +-/* MSTP11 */ +-#define R7S72100_CLK_SSI0 5 +-#define R7S72100_CLK_SSI1 4 +-#define R7S72100_CLK_SSI2 3 +-#define R7S72100_CLK_SSI3 2 +-#define R7S72100_CLK_SSI4 1 +-#define R7S72100_CLK_SSI5 0 +- +-/* MSTP12 */ +-#define R7S72100_CLK_SDHI00 3 +-#define R7S72100_CLK_SDHI01 2 +-#define R7S72100_CLK_SDHI10 1 +-#define R7S72100_CLK_SDHI11 0 +- +-/* MSTP13 */ +-#define R7S72100_CLK_PIX1 2 +-#define R7S72100_CLK_PIX0 1 +- +-#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r7s9210-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r7s9210-cpg-mssr.h +deleted file mode 100644 +index b6f85ca149aa..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r7s9210-cpg-mssr.h ++++ /dev/null +@@ -1,20 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- * +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ +- +-#include +- +-/* R7S9210 CPG Core Clocks */ +-#define R7S9210_CLK_I 0 +-#define R7S9210_CLK_G 1 +-#define R7S9210_CLK_B 2 +-#define R7S9210_CLK_P1 3 +-#define R7S9210_CLK_P1C 4 +-#define R7S9210_CLK_P0 5 +- +-#endif /* __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a73a4-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a73a4-clock.h +deleted file mode 100644 +index 1ec4827b8091..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a73a4-clock.h ++++ /dev/null +@@ -1,60 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright 2014 Ulrich Hecht +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_R8A73A4_H__ +-#define __DT_BINDINGS_CLOCK_R8A73A4_H__ +- +-/* CPG */ +-#define R8A73A4_CLK_MAIN 0 +-#define R8A73A4_CLK_PLL0 1 +-#define R8A73A4_CLK_PLL1 2 +-#define R8A73A4_CLK_PLL2 3 +-#define R8A73A4_CLK_PLL2S 4 +-#define R8A73A4_CLK_PLL2H 5 +-#define R8A73A4_CLK_Z 6 +-#define R8A73A4_CLK_Z2 7 +-#define R8A73A4_CLK_I 8 +-#define R8A73A4_CLK_M3 9 +-#define R8A73A4_CLK_B 10 +-#define R8A73A4_CLK_M1 11 +-#define R8A73A4_CLK_M2 12 +-#define R8A73A4_CLK_ZX 13 +-#define R8A73A4_CLK_ZS 14 +-#define R8A73A4_CLK_HP 15 +- +-/* MSTP2 */ +-#define R8A73A4_CLK_DMAC 18 +-#define R8A73A4_CLK_SCIFB3 17 +-#define R8A73A4_CLK_SCIFB2 16 +-#define R8A73A4_CLK_SCIFB1 7 +-#define R8A73A4_CLK_SCIFB0 6 +-#define R8A73A4_CLK_SCIFA0 4 +-#define R8A73A4_CLK_SCIFA1 3 +- +-/* MSTP3 */ +-#define R8A73A4_CLK_CMT1 29 +-#define R8A73A4_CLK_IIC1 23 +-#define R8A73A4_CLK_IIC0 18 +-#define R8A73A4_CLK_IIC7 17 +-#define R8A73A4_CLK_IIC6 16 +-#define R8A73A4_CLK_MMCIF0 15 +-#define R8A73A4_CLK_SDHI0 14 +-#define R8A73A4_CLK_SDHI1 13 +-#define R8A73A4_CLK_SDHI2 12 +-#define R8A73A4_CLK_MMCIF1 5 +-#define R8A73A4_CLK_IIC2 0 +- +-/* MSTP4 */ +-#define R8A73A4_CLK_IIC3 11 +-#define R8A73A4_CLK_IIC4 10 +-#define R8A73A4_CLK_IIC5 9 +-#define R8A73A4_CLK_INTC_SYS 8 +-#define R8A73A4_CLK_IRQC 7 +- +-/* MSTP5 */ +-#define R8A73A4_CLK_THERMAL 22 +-#define R8A73A4_CLK_IIC8 15 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A73A4_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7740-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7740-clock.h +deleted file mode 100644 +index 1b3fdb39cc42..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7740-clock.h ++++ /dev/null +@@ -1,74 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright 2014 Ulrich Hecht +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_R8A7740_H__ +-#define __DT_BINDINGS_CLOCK_R8A7740_H__ +- +-/* CPG */ +-#define R8A7740_CLK_SYSTEM 0 +-#define R8A7740_CLK_PLLC0 1 +-#define R8A7740_CLK_PLLC1 2 +-#define R8A7740_CLK_PLLC2 3 +-#define R8A7740_CLK_R 4 +-#define R8A7740_CLK_USB24S 5 +-#define R8A7740_CLK_I 6 +-#define R8A7740_CLK_ZG 7 +-#define R8A7740_CLK_B 8 +-#define R8A7740_CLK_M1 9 +-#define R8A7740_CLK_HP 10 +-#define R8A7740_CLK_HPP 11 +-#define R8A7740_CLK_USBP 12 +-#define R8A7740_CLK_S 13 +-#define R8A7740_CLK_ZB 14 +-#define R8A7740_CLK_M3 15 +-#define R8A7740_CLK_CP 16 +- +-/* MSTP1 */ +-#define R8A7740_CLK_CEU21 28 +-#define R8A7740_CLK_CEU20 27 +-#define R8A7740_CLK_TMU0 25 +-#define R8A7740_CLK_LCDC1 17 +-#define R8A7740_CLK_IIC0 16 +-#define R8A7740_CLK_TMU1 11 +-#define R8A7740_CLK_LCDC0 0 +- +-/* MSTP2 */ +-#define R8A7740_CLK_SCIFA6 30 +-#define R8A7740_CLK_INTCA 29 +-#define R8A7740_CLK_SCIFA7 22 +-#define R8A7740_CLK_DMAC1 18 +-#define R8A7740_CLK_DMAC2 17 +-#define R8A7740_CLK_DMAC3 16 +-#define R8A7740_CLK_USBDMAC 14 +-#define R8A7740_CLK_SCIFA5 7 +-#define R8A7740_CLK_SCIFB 6 +-#define R8A7740_CLK_SCIFA0 4 +-#define R8A7740_CLK_SCIFA1 3 +-#define R8A7740_CLK_SCIFA2 2 +-#define R8A7740_CLK_SCIFA3 1 +-#define R8A7740_CLK_SCIFA4 0 +- +-/* MSTP3 */ +-#define R8A7740_CLK_CMT1 29 +-#define R8A7740_CLK_FSI 28 +-#define R8A7740_CLK_IIC1 23 +-#define R8A7740_CLK_USBF 20 +-#define R8A7740_CLK_SDHI0 14 +-#define R8A7740_CLK_SDHI1 13 +-#define R8A7740_CLK_MMC 12 +-#define R8A7740_CLK_GETHER 9 +-#define R8A7740_CLK_TPU0 4 +- +-/* MSTP4 */ +-#define R8A7740_CLK_USBH 16 +-#define R8A7740_CLK_SDHI2 15 +-#define R8A7740_CLK_USBFUNC 7 +-#define R8A7740_CLK_USBPHY 6 +- +-/* SUBCK* */ +-#define R8A7740_CLK_SUBCK 9 +-#define R8A7740_CLK_SUBCK2 10 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A7740_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7742-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7742-cpg-mssr.h +deleted file mode 100644 +index e68191c24881..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7742-cpg-mssr.h ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ +- +-#include +- +-/* r8a7742 CPG Core Clocks */ +-#define R8A7742_CLK_Z 0 +-#define R8A7742_CLK_Z2 1 +-#define R8A7742_CLK_ZG 2 +-#define R8A7742_CLK_ZTR 3 +-#define R8A7742_CLK_ZTRD2 4 +-#define R8A7742_CLK_ZT 5 +-#define R8A7742_CLK_ZX 6 +-#define R8A7742_CLK_ZS 7 +-#define R8A7742_CLK_HP 8 +-#define R8A7742_CLK_B 9 +-#define R8A7742_CLK_LB 10 +-#define R8A7742_CLK_P 11 +-#define R8A7742_CLK_CL 12 +-#define R8A7742_CLK_M2 13 +-#define R8A7742_CLK_ZB3 14 +-#define R8A7742_CLK_ZB3D2 15 +-#define R8A7742_CLK_DDR 16 +-#define R8A7742_CLK_SDH 17 +-#define R8A7742_CLK_SD0 18 +-#define R8A7742_CLK_SD1 19 +-#define R8A7742_CLK_SD2 20 +-#define R8A7742_CLK_SD3 21 +-#define R8A7742_CLK_MMC0 22 +-#define R8A7742_CLK_MMC1 23 +-#define R8A7742_CLK_MP 24 +-#define R8A7742_CLK_QSPI 25 +-#define R8A7742_CLK_CP 26 +-#define R8A7742_CLK_RCAN 27 +-#define R8A7742_CLK_R 28 +-#define R8A7742_CLK_OSC 29 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7743-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7743-cpg-mssr.h +deleted file mode 100644 +index 3ba936029d9f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7743-cpg-mssr.h ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ +- * +- * Copyright (C) 2016 Cogent Embedded Inc. +- */ +-#ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ +- +-#include +- +-/* r8a7743 CPG Core Clocks */ +-#define R8A7743_CLK_Z 0 +-#define R8A7743_CLK_ZG 1 +-#define R8A7743_CLK_ZTR 2 +-#define R8A7743_CLK_ZTRD2 3 +-#define R8A7743_CLK_ZT 4 +-#define R8A7743_CLK_ZX 5 +-#define R8A7743_CLK_ZS 6 +-#define R8A7743_CLK_HP 7 +-#define R8A7743_CLK_B 9 +-#define R8A7743_CLK_LB 10 +-#define R8A7743_CLK_P 11 +-#define R8A7743_CLK_CL 12 +-#define R8A7743_CLK_M2 13 +-#define R8A7743_CLK_ZB3 15 +-#define R8A7743_CLK_ZB3D2 16 +-#define R8A7743_CLK_DDR 17 +-#define R8A7743_CLK_SDH 18 +-#define R8A7743_CLK_SD0 19 +-#define R8A7743_CLK_SD2 20 +-#define R8A7743_CLK_SD3 21 +-#define R8A7743_CLK_MMC0 22 +-#define R8A7743_CLK_MP 23 +-#define R8A7743_CLK_QSPI 26 +-#define R8A7743_CLK_CP 27 +-#define R8A7743_CLK_RCAN 28 +-#define R8A7743_CLK_R 29 +-#define R8A7743_CLK_OSC 30 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7744-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7744-cpg-mssr.h +deleted file mode 100644 +index 2690be0c3e22..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7744-cpg-mssr.h ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ +- +-#include +- +-/* r8a7744 CPG Core Clocks */ +-#define R8A7744_CLK_Z 0 +-#define R8A7744_CLK_ZG 1 +-#define R8A7744_CLK_ZTR 2 +-#define R8A7744_CLK_ZTRD2 3 +-#define R8A7744_CLK_ZT 4 +-#define R8A7744_CLK_ZX 5 +-#define R8A7744_CLK_ZS 6 +-#define R8A7744_CLK_HP 7 +-#define R8A7744_CLK_B 9 +-#define R8A7744_CLK_LB 10 +-#define R8A7744_CLK_P 11 +-#define R8A7744_CLK_CL 12 +-#define R8A7744_CLK_M2 13 +-#define R8A7744_CLK_ZB3 15 +-#define R8A7744_CLK_ZB3D2 16 +-#define R8A7744_CLK_DDR 17 +-#define R8A7744_CLK_SDH 18 +-#define R8A7744_CLK_SD0 19 +-#define R8A7744_CLK_SD2 20 +-#define R8A7744_CLK_SD3 21 +-#define R8A7744_CLK_MMC0 22 +-#define R8A7744_CLK_MP 23 +-#define R8A7744_CLK_QSPI 26 +-#define R8A7744_CLK_CP 27 +-#define R8A7744_CLK_RCAN 28 +-#define R8A7744_CLK_R 29 +-#define R8A7744_CLK_OSC 30 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7745-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7745-cpg-mssr.h +deleted file mode 100644 +index f81066c9d192..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7745-cpg-mssr.h ++++ /dev/null +@@ -1,40 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ +- * +- * Copyright (C) 2016 Cogent Embedded Inc. +- */ +-#ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ +- +-#include +- +-/* r8a7745 CPG Core Clocks */ +-#define R8A7745_CLK_Z2 0 +-#define R8A7745_CLK_ZG 1 +-#define R8A7745_CLK_ZTR 2 +-#define R8A7745_CLK_ZTRD2 3 +-#define R8A7745_CLK_ZT 4 +-#define R8A7745_CLK_ZX 5 +-#define R8A7745_CLK_ZS 6 +-#define R8A7745_CLK_HP 7 +-#define R8A7745_CLK_B 9 +-#define R8A7745_CLK_LB 10 +-#define R8A7745_CLK_P 11 +-#define R8A7745_CLK_CL 12 +-#define R8A7745_CLK_CP 13 +-#define R8A7745_CLK_M2 14 +-#define R8A7745_CLK_ZB3 16 +-#define R8A7745_CLK_ZB3D2 17 +-#define R8A7745_CLK_DDR 18 +-#define R8A7745_CLK_SDH 19 +-#define R8A7745_CLK_SD0 20 +-#define R8A7745_CLK_SD2 21 +-#define R8A7745_CLK_SD3 22 +-#define R8A7745_CLK_MMC0 23 +-#define R8A7745_CLK_MP 24 +-#define R8A7745_CLK_QSPI 25 +-#define R8A7745_CLK_CPEX 26 +-#define R8A7745_CLK_RCAN 27 +-#define R8A7745_CLK_R 28 +-#define R8A7745_CLK_OSC 29 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77470-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77470-cpg-mssr.h +deleted file mode 100644 +index 34cba49d0f84..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77470-cpg-mssr.h ++++ /dev/null +@@ -1,36 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ +- +-#include +- +-/* r8a77470 CPG Core Clocks */ +-#define R8A77470_CLK_Z2 0 +-#define R8A77470_CLK_ZTR 1 +-#define R8A77470_CLK_ZTRD2 2 +-#define R8A77470_CLK_ZT 3 +-#define R8A77470_CLK_ZX 4 +-#define R8A77470_CLK_ZS 5 +-#define R8A77470_CLK_HP 6 +-#define R8A77470_CLK_B 7 +-#define R8A77470_CLK_LB 8 +-#define R8A77470_CLK_P 9 +-#define R8A77470_CLK_CL 10 +-#define R8A77470_CLK_CP 11 +-#define R8A77470_CLK_M2 12 +-#define R8A77470_CLK_ZB3 13 +-#define R8A77470_CLK_SDH 14 +-#define R8A77470_CLK_SD0 15 +-#define R8A77470_CLK_SD1 16 +-#define R8A77470_CLK_SD2 17 +-#define R8A77470_CLK_MP 18 +-#define R8A77470_CLK_QSPI 19 +-#define R8A77470_CLK_CPEX 20 +-#define R8A77470_CLK_RCAN 21 +-#define R8A77470_CLK_R 22 +-#define R8A77470_CLK_OSC 23 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a774a1-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a774a1-cpg-mssr.h +deleted file mode 100644 +index e355363f40c2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a774a1-cpg-mssr.h ++++ /dev/null +@@ -1,59 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ +- +-#include +- +-/* r8a774a1 CPG Core Clocks */ +-#define R8A774A1_CLK_Z 0 +-#define R8A774A1_CLK_Z2 1 +-#define R8A774A1_CLK_ZG 2 +-#define R8A774A1_CLK_ZTR 3 +-#define R8A774A1_CLK_ZTRD2 4 +-#define R8A774A1_CLK_ZT 5 +-#define R8A774A1_CLK_ZX 6 +-#define R8A774A1_CLK_S0D1 7 +-#define R8A774A1_CLK_S0D2 8 +-#define R8A774A1_CLK_S0D3 9 +-#define R8A774A1_CLK_S0D4 10 +-#define R8A774A1_CLK_S0D6 11 +-#define R8A774A1_CLK_S0D8 12 +-#define R8A774A1_CLK_S0D12 13 +-#define R8A774A1_CLK_S1D2 14 +-#define R8A774A1_CLK_S1D4 15 +-#define R8A774A1_CLK_S2D1 16 +-#define R8A774A1_CLK_S2D2 17 +-#define R8A774A1_CLK_S2D4 18 +-#define R8A774A1_CLK_S3D1 19 +-#define R8A774A1_CLK_S3D2 20 +-#define R8A774A1_CLK_S3D4 21 +-#define R8A774A1_CLK_LB 22 +-#define R8A774A1_CLK_CL 23 +-#define R8A774A1_CLK_ZB3 24 +-#define R8A774A1_CLK_ZB3D2 25 +-#define R8A774A1_CLK_ZB3D4 26 +-#define R8A774A1_CLK_CR 27 +-#define R8A774A1_CLK_CRD2 28 +-#define R8A774A1_CLK_SD0H 29 +-#define R8A774A1_CLK_SD0 30 +-#define R8A774A1_CLK_SD1H 31 +-#define R8A774A1_CLK_SD1 32 +-#define R8A774A1_CLK_SD2H 33 +-#define R8A774A1_CLK_SD2 34 +-#define R8A774A1_CLK_SD3H 35 +-#define R8A774A1_CLK_SD3 36 +-#define R8A774A1_CLK_RPC 37 +-#define R8A774A1_CLK_RPCD2 38 +-#define R8A774A1_CLK_MSO 39 +-#define R8A774A1_CLK_HDMI 40 +-#define R8A774A1_CLK_CSI0 41 +-#define R8A774A1_CLK_CP 42 +-#define R8A774A1_CLK_CPEX 43 +-#define R8A774A1_CLK_R 44 +-#define R8A774A1_CLK_OSC 45 +-#define R8A774A1_CLK_CANFD 46 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a774b1-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a774b1-cpg-mssr.h +deleted file mode 100644 +index 1355451b74b0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a774b1-cpg-mssr.h ++++ /dev/null +@@ -1,57 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 +- * +- * Copyright (C) 2019 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ +- +-#include +- +-/* r8a774b1 CPG Core Clocks */ +-#define R8A774B1_CLK_Z 0 +-#define R8A774B1_CLK_ZG 1 +-#define R8A774B1_CLK_ZTR 2 +-#define R8A774B1_CLK_ZTRD2 3 +-#define R8A774B1_CLK_ZT 4 +-#define R8A774B1_CLK_ZX 5 +-#define R8A774B1_CLK_S0D1 6 +-#define R8A774B1_CLK_S0D2 7 +-#define R8A774B1_CLK_S0D3 8 +-#define R8A774B1_CLK_S0D4 9 +-#define R8A774B1_CLK_S0D6 10 +-#define R8A774B1_CLK_S0D8 11 +-#define R8A774B1_CLK_S0D12 12 +-#define R8A774B1_CLK_S1D2 13 +-#define R8A774B1_CLK_S1D4 14 +-#define R8A774B1_CLK_S2D1 15 +-#define R8A774B1_CLK_S2D2 16 +-#define R8A774B1_CLK_S2D4 17 +-#define R8A774B1_CLK_S3D1 18 +-#define R8A774B1_CLK_S3D2 19 +-#define R8A774B1_CLK_S3D4 20 +-#define R8A774B1_CLK_LB 21 +-#define R8A774B1_CLK_CL 22 +-#define R8A774B1_CLK_ZB3 23 +-#define R8A774B1_CLK_ZB3D2 24 +-#define R8A774B1_CLK_CR 25 +-#define R8A774B1_CLK_DDR 26 +-#define R8A774B1_CLK_SD0H 27 +-#define R8A774B1_CLK_SD0 28 +-#define R8A774B1_CLK_SD1H 29 +-#define R8A774B1_CLK_SD1 30 +-#define R8A774B1_CLK_SD2H 31 +-#define R8A774B1_CLK_SD2 32 +-#define R8A774B1_CLK_SD3H 33 +-#define R8A774B1_CLK_SD3 34 +-#define R8A774B1_CLK_RPC 35 +-#define R8A774B1_CLK_RPCD2 36 +-#define R8A774B1_CLK_MSO 37 +-#define R8A774B1_CLK_HDMI 38 +-#define R8A774B1_CLK_CSI0 39 +-#define R8A774B1_CLK_CP 40 +-#define R8A774B1_CLK_CPEX 41 +-#define R8A774B1_CLK_R 42 +-#define R8A774B1_CLK_OSC 43 +-#define R8A774B1_CLK_CANFD 44 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a774c0-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a774c0-cpg-mssr.h +deleted file mode 100644 +index 8ad9cd6be8e9..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a774c0-cpg-mssr.h ++++ /dev/null +@@ -1,61 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ +- +-#include +- +-/* r8a774c0 CPG Core Clocks */ +-#define R8A774C0_CLK_Z2 0 +-#define R8A774C0_CLK_ZG 1 +-#define R8A774C0_CLK_ZTR 2 +-#define R8A774C0_CLK_ZT 3 +-#define R8A774C0_CLK_ZX 4 +-#define R8A774C0_CLK_S0D1 5 +-#define R8A774C0_CLK_S0D3 6 +-#define R8A774C0_CLK_S0D6 7 +-#define R8A774C0_CLK_S0D12 8 +-#define R8A774C0_CLK_S0D24 9 +-#define R8A774C0_CLK_S1D1 10 +-#define R8A774C0_CLK_S1D2 11 +-#define R8A774C0_CLK_S1D4 12 +-#define R8A774C0_CLK_S2D1 13 +-#define R8A774C0_CLK_S2D2 14 +-#define R8A774C0_CLK_S2D4 15 +-#define R8A774C0_CLK_S3D1 16 +-#define R8A774C0_CLK_S3D2 17 +-#define R8A774C0_CLK_S3D4 18 +-#define R8A774C0_CLK_S0D6C 19 +-#define R8A774C0_CLK_S3D1C 20 +-#define R8A774C0_CLK_S3D2C 21 +-#define R8A774C0_CLK_S3D4C 22 +-#define R8A774C0_CLK_LB 23 +-#define R8A774C0_CLK_CL 24 +-#define R8A774C0_CLK_ZB3 25 +-#define R8A774C0_CLK_ZB3D2 26 +-#define R8A774C0_CLK_CR 27 +-#define R8A774C0_CLK_CRD2 28 +-#define R8A774C0_CLK_SD0H 29 +-#define R8A774C0_CLK_SD0 30 +-#define R8A774C0_CLK_SD1H 31 +-#define R8A774C0_CLK_SD1 32 +-#define R8A774C0_CLK_SD3H 33 +-#define R8A774C0_CLK_SD3 34 +-#define R8A774C0_CLK_RPC 35 +-#define R8A774C0_CLK_RPCD2 36 +-#define R8A774C0_CLK_ZA2 37 +-#define R8A774C0_CLK_ZA8 38 +-#define R8A774C0_CLK_Z2D 39 +-#define R8A774C0_CLK_MSO 40 +-#define R8A774C0_CLK_R 41 +-#define R8A774C0_CLK_OSC 42 +-#define R8A774C0_CLK_LV0 43 +-#define R8A774C0_CLK_LV1 44 +-#define R8A774C0_CLK_CSI0 45 +-#define R8A774C0_CLK_CP 46 +-#define R8A774C0_CLK_CPEX 47 +-#define R8A774C0_CLK_CANFD 48 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a774e1-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a774e1-cpg-mssr.h +deleted file mode 100644 +index b2fc1d1c3c47..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a774e1-cpg-mssr.h ++++ /dev/null +@@ -1,59 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ +- +-#include +- +-/* R8A774E1 CPG Core Clocks */ +-#define R8A774E1_CLK_Z 0 +-#define R8A774E1_CLK_Z2 1 +-#define R8A774E1_CLK_ZG 2 +-#define R8A774E1_CLK_ZTR 3 +-#define R8A774E1_CLK_ZTRD2 4 +-#define R8A774E1_CLK_ZT 5 +-#define R8A774E1_CLK_ZX 6 +-#define R8A774E1_CLK_S0D1 7 +-#define R8A774E1_CLK_S0D2 8 +-#define R8A774E1_CLK_S0D3 9 +-#define R8A774E1_CLK_S0D4 10 +-#define R8A774E1_CLK_S0D6 11 +-#define R8A774E1_CLK_S0D8 12 +-#define R8A774E1_CLK_S0D12 13 +-#define R8A774E1_CLK_S1D2 14 +-#define R8A774E1_CLK_S1D4 15 +-#define R8A774E1_CLK_S2D1 16 +-#define R8A774E1_CLK_S2D2 17 +-#define R8A774E1_CLK_S2D4 18 +-#define R8A774E1_CLK_S3D1 19 +-#define R8A774E1_CLK_S3D2 20 +-#define R8A774E1_CLK_S3D4 21 +-#define R8A774E1_CLK_LB 22 +-#define R8A774E1_CLK_CL 23 +-#define R8A774E1_CLK_ZB3 24 +-#define R8A774E1_CLK_ZB3D2 25 +-#define R8A774E1_CLK_ZB3D4 26 +-#define R8A774E1_CLK_CR 27 +-#define R8A774E1_CLK_CRD2 28 +-#define R8A774E1_CLK_SD0H 29 +-#define R8A774E1_CLK_SD0 30 +-#define R8A774E1_CLK_SD1H 31 +-#define R8A774E1_CLK_SD1 32 +-#define R8A774E1_CLK_SD2H 33 +-#define R8A774E1_CLK_SD2 34 +-#define R8A774E1_CLK_SD3H 35 +-#define R8A774E1_CLK_SD3 36 +-#define R8A774E1_CLK_RPC 37 +-#define R8A774E1_CLK_RPCD2 38 +-#define R8A774E1_CLK_MSO 39 +-#define R8A774E1_CLK_HDMI 40 +-#define R8A774E1_CLK_CSI0 41 +-#define R8A774E1_CLK_CP 42 +-#define R8A774E1_CLK_CPEX 43 +-#define R8A774E1_CLK_R 44 +-#define R8A774E1_CLK_OSC 45 +-#define R8A774E1_CLK_CANFD 46 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7778-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7778-clock.h +deleted file mode 100644 +index 4a32b364fd20..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7778-clock.h ++++ /dev/null +@@ -1,69 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (C) 2014 Ulrich Hecht +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_R8A7778_H__ +-#define __DT_BINDINGS_CLOCK_R8A7778_H__ +- +-/* CPG */ +-#define R8A7778_CLK_PLLA 0 +-#define R8A7778_CLK_PLLB 1 +-#define R8A7778_CLK_B 2 +-#define R8A7778_CLK_OUT 3 +-#define R8A7778_CLK_P 4 +-#define R8A7778_CLK_S 5 +-#define R8A7778_CLK_S1 6 +- +-/* MSTP0 */ +-#define R8A7778_CLK_I2C0 30 +-#define R8A7778_CLK_I2C1 29 +-#define R8A7778_CLK_I2C2 28 +-#define R8A7778_CLK_I2C3 27 +-#define R8A7778_CLK_SCIF0 26 +-#define R8A7778_CLK_SCIF1 25 +-#define R8A7778_CLK_SCIF2 24 +-#define R8A7778_CLK_SCIF3 23 +-#define R8A7778_CLK_SCIF4 22 +-#define R8A7778_CLK_SCIF5 21 +-#define R8A7778_CLK_HSCIF0 19 +-#define R8A7778_CLK_HSCIF1 18 +-#define R8A7778_CLK_TMU0 16 +-#define R8A7778_CLK_TMU1 15 +-#define R8A7778_CLK_TMU2 14 +-#define R8A7778_CLK_SSI0 12 +-#define R8A7778_CLK_SSI1 11 +-#define R8A7778_CLK_SSI2 10 +-#define R8A7778_CLK_SSI3 9 +-#define R8A7778_CLK_SRU 8 +-#define R8A7778_CLK_HSPI 7 +- +-/* MSTP1 */ +-#define R8A7778_CLK_ETHER 14 +-#define R8A7778_CLK_VIN0 10 +-#define R8A7778_CLK_VIN1 9 +-#define R8A7778_CLK_USB 0 +- +-/* MSTP3 */ +-#define R8A7778_CLK_MMC 31 +-#define R8A7778_CLK_SDHI0 23 +-#define R8A7778_CLK_SDHI1 22 +-#define R8A7778_CLK_SDHI2 21 +-#define R8A7778_CLK_SSI4 11 +-#define R8A7778_CLK_SSI5 10 +-#define R8A7778_CLK_SSI6 9 +-#define R8A7778_CLK_SSI7 8 +-#define R8A7778_CLK_SSI8 7 +- +-/* MSTP5 */ +-#define R8A7778_CLK_SRU_SRC0 31 +-#define R8A7778_CLK_SRU_SRC1 30 +-#define R8A7778_CLK_SRU_SRC2 29 +-#define R8A7778_CLK_SRU_SRC3 28 +-#define R8A7778_CLK_SRU_SRC4 27 +-#define R8A7778_CLK_SRU_SRC5 26 +-#define R8A7778_CLK_SRU_SRC6 25 +-#define R8A7778_CLK_SRU_SRC7 24 +-#define R8A7778_CLK_SRU_SRC8 23 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A7778_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7779-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7779-clock.h +deleted file mode 100644 +index f0549234b7d8..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7779-clock.h ++++ /dev/null +@@ -1,60 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (C) 2013 Horms Solutions Ltd. +- * +- * Contact: Simon Horman +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_R8A7779_H__ +-#define __DT_BINDINGS_CLOCK_R8A7779_H__ +- +-/* CPG */ +-#define R8A7779_CLK_PLLA 0 +-#define R8A7779_CLK_Z 1 +-#define R8A7779_CLK_ZS 2 +-#define R8A7779_CLK_S 3 +-#define R8A7779_CLK_S1 4 +-#define R8A7779_CLK_P 5 +-#define R8A7779_CLK_B 6 +-#define R8A7779_CLK_OUT 7 +- +-/* MSTP 0 */ +-#define R8A7779_CLK_HSPI 7 +-#define R8A7779_CLK_TMU2 14 +-#define R8A7779_CLK_TMU1 15 +-#define R8A7779_CLK_TMU0 16 +-#define R8A7779_CLK_HSCIF1 18 +-#define R8A7779_CLK_HSCIF0 19 +-#define R8A7779_CLK_SCIF5 21 +-#define R8A7779_CLK_SCIF4 22 +-#define R8A7779_CLK_SCIF3 23 +-#define R8A7779_CLK_SCIF2 24 +-#define R8A7779_CLK_SCIF1 25 +-#define R8A7779_CLK_SCIF0 26 +-#define R8A7779_CLK_I2C3 27 +-#define R8A7779_CLK_I2C2 28 +-#define R8A7779_CLK_I2C1 29 +-#define R8A7779_CLK_I2C0 30 +- +-/* MSTP 1 */ +-#define R8A7779_CLK_USB01 0 +-#define R8A7779_CLK_USB2 1 +-#define R8A7779_CLK_DU 3 +-#define R8A7779_CLK_VIN2 8 +-#define R8A7779_CLK_VIN1 9 +-#define R8A7779_CLK_VIN0 10 +-#define R8A7779_CLK_ETHER 14 +-#define R8A7779_CLK_SATA 15 +-#define R8A7779_CLK_PCIE 16 +-#define R8A7779_CLK_VIN3 20 +- +-/* MSTP 3 */ +-#define R8A7779_CLK_SDHI3 20 +-#define R8A7779_CLK_SDHI2 21 +-#define R8A7779_CLK_SDHI1 22 +-#define R8A7779_CLK_SDHI0 23 +-#define R8A7779_CLK_MMC1 30 +-#define R8A7779_CLK_MMC0 31 +- +- +-#endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7790-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7790-clock.h +deleted file mode 100644 +index c92ff1e60223..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7790-clock.h ++++ /dev/null +@@ -1,158 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright 2013 Ideas On Board SPRL +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__ +-#define __DT_BINDINGS_CLOCK_R8A7790_H__ +- +-/* CPG */ +-#define R8A7790_CLK_MAIN 0 +-#define R8A7790_CLK_PLL0 1 +-#define R8A7790_CLK_PLL1 2 +-#define R8A7790_CLK_PLL3 3 +-#define R8A7790_CLK_LB 4 +-#define R8A7790_CLK_QSPI 5 +-#define R8A7790_CLK_SDH 6 +-#define R8A7790_CLK_SD0 7 +-#define R8A7790_CLK_SD1 8 +-#define R8A7790_CLK_Z 9 +-#define R8A7790_CLK_RCAN 10 +-#define R8A7790_CLK_ADSP 11 +- +-/* MSTP0 */ +-#define R8A7790_CLK_MSIOF0 0 +- +-/* MSTP1 */ +-#define R8A7790_CLK_VCP1 0 +-#define R8A7790_CLK_VCP0 1 +-#define R8A7790_CLK_VPC1 2 +-#define R8A7790_CLK_VPC0 3 +-#define R8A7790_CLK_JPU 6 +-#define R8A7790_CLK_SSP1 9 +-#define R8A7790_CLK_TMU1 11 +-#define R8A7790_CLK_3DG 12 +-#define R8A7790_CLK_2DDMAC 15 +-#define R8A7790_CLK_FDP1_2 17 +-#define R8A7790_CLK_FDP1_1 18 +-#define R8A7790_CLK_FDP1_0 19 +-#define R8A7790_CLK_TMU3 21 +-#define R8A7790_CLK_TMU2 22 +-#define R8A7790_CLK_CMT0 24 +-#define R8A7790_CLK_TMU0 25 +-#define R8A7790_CLK_VSP1_DU1 27 +-#define R8A7790_CLK_VSP1_DU0 28 +-#define R8A7790_CLK_VSP1_R 30 +-#define R8A7790_CLK_VSP1_S 31 +- +-/* MSTP2 */ +-#define R8A7790_CLK_SCIFA2 2 +-#define R8A7790_CLK_SCIFA1 3 +-#define R8A7790_CLK_SCIFA0 4 +-#define R8A7790_CLK_MSIOF2 5 +-#define R8A7790_CLK_SCIFB0 6 +-#define R8A7790_CLK_SCIFB1 7 +-#define R8A7790_CLK_MSIOF1 8 +-#define R8A7790_CLK_MSIOF3 15 +-#define R8A7790_CLK_SCIFB2 16 +-#define R8A7790_CLK_SYS_DMAC1 18 +-#define R8A7790_CLK_SYS_DMAC0 19 +- +-/* MSTP3 */ +-#define R8A7790_CLK_IIC2 0 +-#define R8A7790_CLK_TPU0 4 +-#define R8A7790_CLK_MMCIF1 5 +-#define R8A7790_CLK_SCIF2 10 +-#define R8A7790_CLK_SDHI3 11 +-#define R8A7790_CLK_SDHI2 12 +-#define R8A7790_CLK_SDHI1 13 +-#define R8A7790_CLK_SDHI0 14 +-#define R8A7790_CLK_MMCIF0 15 +-#define R8A7790_CLK_IIC0 18 +-#define R8A7790_CLK_PCIEC 19 +-#define R8A7790_CLK_IIC1 23 +-#define R8A7790_CLK_SSUSB 28 +-#define R8A7790_CLK_CMT1 29 +-#define R8A7790_CLK_USBDMAC0 30 +-#define R8A7790_CLK_USBDMAC1 31 +- +-/* MSTP4 */ +-#define R8A7790_CLK_IRQC 7 +-#define R8A7790_CLK_INTC_SYS 8 +- +-/* MSTP5 */ +-#define R8A7790_CLK_AUDIO_DMAC1 1 +-#define R8A7790_CLK_AUDIO_DMAC0 2 +-#define R8A7790_CLK_ADSP_MOD 6 +-#define R8A7790_CLK_THERMAL 22 +-#define R8A7790_CLK_PWM 23 +- +-/* MSTP7 */ +-#define R8A7790_CLK_EHCI 3 +-#define R8A7790_CLK_HSUSB 4 +-#define R8A7790_CLK_HSCIF1 16 +-#define R8A7790_CLK_HSCIF0 17 +-#define R8A7790_CLK_SCIF1 20 +-#define R8A7790_CLK_SCIF0 21 +-#define R8A7790_CLK_DU2 22 +-#define R8A7790_CLK_DU1 23 +-#define R8A7790_CLK_DU0 24 +-#define R8A7790_CLK_LVDS1 25 +-#define R8A7790_CLK_LVDS0 26 +- +-/* MSTP8 */ +-#define R8A7790_CLK_MLB 2 +-#define R8A7790_CLK_VIN3 8 +-#define R8A7790_CLK_VIN2 9 +-#define R8A7790_CLK_VIN1 10 +-#define R8A7790_CLK_VIN0 11 +-#define R8A7790_CLK_ETHERAVB 12 +-#define R8A7790_CLK_ETHER 13 +-#define R8A7790_CLK_SATA1 14 +-#define R8A7790_CLK_SATA0 15 +- +-/* MSTP9 */ +-#define R8A7790_CLK_GPIO5 7 +-#define R8A7790_CLK_GPIO4 8 +-#define R8A7790_CLK_GPIO3 9 +-#define R8A7790_CLK_GPIO2 10 +-#define R8A7790_CLK_GPIO1 11 +-#define R8A7790_CLK_GPIO0 12 +-#define R8A7790_CLK_RCAN1 15 +-#define R8A7790_CLK_RCAN0 16 +-#define R8A7790_CLK_QSPI_MOD 17 +-#define R8A7790_CLK_IICDVFS 26 +-#define R8A7790_CLK_I2C3 28 +-#define R8A7790_CLK_I2C2 29 +-#define R8A7790_CLK_I2C1 30 +-#define R8A7790_CLK_I2C0 31 +- +-/* MSTP10 */ +-#define R8A7790_CLK_SSI_ALL 5 +-#define R8A7790_CLK_SSI9 6 +-#define R8A7790_CLK_SSI8 7 +-#define R8A7790_CLK_SSI7 8 +-#define R8A7790_CLK_SSI6 9 +-#define R8A7790_CLK_SSI5 10 +-#define R8A7790_CLK_SSI4 11 +-#define R8A7790_CLK_SSI3 12 +-#define R8A7790_CLK_SSI2 13 +-#define R8A7790_CLK_SSI1 14 +-#define R8A7790_CLK_SSI0 15 +-#define R8A7790_CLK_SCU_ALL 17 +-#define R8A7790_CLK_SCU_DVC1 18 +-#define R8A7790_CLK_SCU_DVC0 19 +-#define R8A7790_CLK_SCU_CTU1_MIX1 20 +-#define R8A7790_CLK_SCU_CTU0_MIX0 21 +-#define R8A7790_CLK_SCU_SRC9 22 +-#define R8A7790_CLK_SCU_SRC8 23 +-#define R8A7790_CLK_SCU_SRC7 24 +-#define R8A7790_CLK_SCU_SRC6 25 +-#define R8A7790_CLK_SCU_SRC5 26 +-#define R8A7790_CLK_SCU_SRC4 27 +-#define R8A7790_CLK_SCU_SRC3 28 +-#define R8A7790_CLK_SCU_SRC2 29 +-#define R8A7790_CLK_SCU_SRC1 30 +-#define R8A7790_CLK_SCU_SRC0 31 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7790-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7790-cpg-mssr.h +deleted file mode 100644 +index c5955b56b36d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7790-cpg-mssr.h ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ +- * +- * Copyright (C) 2015 Renesas Electronics Corp. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ +- +-#include +- +-/* r8a7790 CPG Core Clocks */ +-#define R8A7790_CLK_Z 0 +-#define R8A7790_CLK_Z2 1 +-#define R8A7790_CLK_ZG 2 +-#define R8A7790_CLK_ZTR 3 +-#define R8A7790_CLK_ZTRD2 4 +-#define R8A7790_CLK_ZT 5 +-#define R8A7790_CLK_ZX 6 +-#define R8A7790_CLK_ZS 7 +-#define R8A7790_CLK_HP 8 +-#define R8A7790_CLK_I 9 +-#define R8A7790_CLK_B 10 +-#define R8A7790_CLK_LB 11 +-#define R8A7790_CLK_P 12 +-#define R8A7790_CLK_CL 13 +-#define R8A7790_CLK_M2 14 +-#define R8A7790_CLK_ADSP 15 +-#define R8A7790_CLK_IMP 16 +-#define R8A7790_CLK_ZB3 17 +-#define R8A7790_CLK_ZB3D2 18 +-#define R8A7790_CLK_DDR 19 +-#define R8A7790_CLK_SDH 20 +-#define R8A7790_CLK_SD0 21 +-#define R8A7790_CLK_SD1 22 +-#define R8A7790_CLK_SD2 23 +-#define R8A7790_CLK_SD3 24 +-#define R8A7790_CLK_MMC0 25 +-#define R8A7790_CLK_MMC1 26 +-#define R8A7790_CLK_MP 27 +-#define R8A7790_CLK_SSP 28 +-#define R8A7790_CLK_SSPRS 29 +-#define R8A7790_CLK_QSPI 30 +-#define R8A7790_CLK_CP 31 +-#define R8A7790_CLK_RCAN 32 +-#define R8A7790_CLK_R 33 +-#define R8A7790_CLK_OSC 34 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7791-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7791-clock.h +deleted file mode 100644 +index bb4f18b1b3d5..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7791-clock.h ++++ /dev/null +@@ -1,161 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright 2013 Ideas On Board SPRL +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__ +-#define __DT_BINDINGS_CLOCK_R8A7791_H__ +- +-/* CPG */ +-#define R8A7791_CLK_MAIN 0 +-#define R8A7791_CLK_PLL0 1 +-#define R8A7791_CLK_PLL1 2 +-#define R8A7791_CLK_PLL3 3 +-#define R8A7791_CLK_LB 4 +-#define R8A7791_CLK_QSPI 5 +-#define R8A7791_CLK_SDH 6 +-#define R8A7791_CLK_SD0 7 +-#define R8A7791_CLK_Z 8 +-#define R8A7791_CLK_RCAN 9 +-#define R8A7791_CLK_ADSP 10 +- +-/* MSTP0 */ +-#define R8A7791_CLK_MSIOF0 0 +- +-/* MSTP1 */ +-#define R8A7791_CLK_VCP0 1 +-#define R8A7791_CLK_VPC0 3 +-#define R8A7791_CLK_JPU 6 +-#define R8A7791_CLK_SSP1 9 +-#define R8A7791_CLK_TMU1 11 +-#define R8A7791_CLK_3DG 12 +-#define R8A7791_CLK_2DDMAC 15 +-#define R8A7791_CLK_FDP1_1 18 +-#define R8A7791_CLK_FDP1_0 19 +-#define R8A7791_CLK_TMU3 21 +-#define R8A7791_CLK_TMU2 22 +-#define R8A7791_CLK_CMT0 24 +-#define R8A7791_CLK_TMU0 25 +-#define R8A7791_CLK_VSP1_DU1 27 +-#define R8A7791_CLK_VSP1_DU0 28 +-#define R8A7791_CLK_VSP1_S 31 +- +-/* MSTP2 */ +-#define R8A7791_CLK_SCIFA2 2 +-#define R8A7791_CLK_SCIFA1 3 +-#define R8A7791_CLK_SCIFA0 4 +-#define R8A7791_CLK_MSIOF2 5 +-#define R8A7791_CLK_SCIFB0 6 +-#define R8A7791_CLK_SCIFB1 7 +-#define R8A7791_CLK_MSIOF1 8 +-#define R8A7791_CLK_SCIFB2 16 +-#define R8A7791_CLK_SYS_DMAC1 18 +-#define R8A7791_CLK_SYS_DMAC0 19 +- +-/* MSTP3 */ +-#define R8A7791_CLK_TPU0 4 +-#define R8A7791_CLK_SDHI2 11 +-#define R8A7791_CLK_SDHI1 12 +-#define R8A7791_CLK_SDHI0 14 +-#define R8A7791_CLK_MMCIF0 15 +-#define R8A7791_CLK_IIC0 18 +-#define R8A7791_CLK_PCIEC 19 +-#define R8A7791_CLK_IIC1 23 +-#define R8A7791_CLK_SSUSB 28 +-#define R8A7791_CLK_CMT1 29 +-#define R8A7791_CLK_USBDMAC0 30 +-#define R8A7791_CLK_USBDMAC1 31 +- +-/* MSTP4 */ +-#define R8A7791_CLK_IRQC 7 +-#define R8A7791_CLK_INTC_SYS 8 +- +-/* MSTP5 */ +-#define R8A7791_CLK_AUDIO_DMAC1 1 +-#define R8A7791_CLK_AUDIO_DMAC0 2 +-#define R8A7791_CLK_ADSP_MOD 6 +-#define R8A7791_CLK_THERMAL 22 +-#define R8A7791_CLK_PWM 23 +- +-/* MSTP7 */ +-#define R8A7791_CLK_EHCI 3 +-#define R8A7791_CLK_HSUSB 4 +-#define R8A7791_CLK_HSCIF2 13 +-#define R8A7791_CLK_SCIF5 14 +-#define R8A7791_CLK_SCIF4 15 +-#define R8A7791_CLK_HSCIF1 16 +-#define R8A7791_CLK_HSCIF0 17 +-#define R8A7791_CLK_SCIF3 18 +-#define R8A7791_CLK_SCIF2 19 +-#define R8A7791_CLK_SCIF1 20 +-#define R8A7791_CLK_SCIF0 21 +-#define R8A7791_CLK_DU1 23 +-#define R8A7791_CLK_DU0 24 +-#define R8A7791_CLK_LVDS0 26 +- +-/* MSTP8 */ +-#define R8A7791_CLK_IPMMU_SGX 0 +-#define R8A7791_CLK_MLB 2 +-#define R8A7791_CLK_VIN2 9 +-#define R8A7791_CLK_VIN1 10 +-#define R8A7791_CLK_VIN0 11 +-#define R8A7791_CLK_ETHERAVB 12 +-#define R8A7791_CLK_ETHER 13 +-#define R8A7791_CLK_SATA1 14 +-#define R8A7791_CLK_SATA0 15 +- +-/* MSTP9 */ +-#define R8A7791_CLK_GYROADC 1 +-#define R8A7791_CLK_GPIO7 4 +-#define R8A7791_CLK_GPIO6 5 +-#define R8A7791_CLK_GPIO5 7 +-#define R8A7791_CLK_GPIO4 8 +-#define R8A7791_CLK_GPIO3 9 +-#define R8A7791_CLK_GPIO2 10 +-#define R8A7791_CLK_GPIO1 11 +-#define R8A7791_CLK_GPIO0 12 +-#define R8A7791_CLK_RCAN1 15 +-#define R8A7791_CLK_RCAN0 16 +-#define R8A7791_CLK_QSPI_MOD 17 +-#define R8A7791_CLK_I2C5 25 +-#define R8A7791_CLK_IICDVFS 26 +-#define R8A7791_CLK_I2C4 27 +-#define R8A7791_CLK_I2C3 28 +-#define R8A7791_CLK_I2C2 29 +-#define R8A7791_CLK_I2C1 30 +-#define R8A7791_CLK_I2C0 31 +- +-/* MSTP10 */ +-#define R8A7791_CLK_SSI_ALL 5 +-#define R8A7791_CLK_SSI9 6 +-#define R8A7791_CLK_SSI8 7 +-#define R8A7791_CLK_SSI7 8 +-#define R8A7791_CLK_SSI6 9 +-#define R8A7791_CLK_SSI5 10 +-#define R8A7791_CLK_SSI4 11 +-#define R8A7791_CLK_SSI3 12 +-#define R8A7791_CLK_SSI2 13 +-#define R8A7791_CLK_SSI1 14 +-#define R8A7791_CLK_SSI0 15 +-#define R8A7791_CLK_SCU_ALL 17 +-#define R8A7791_CLK_SCU_DVC1 18 +-#define R8A7791_CLK_SCU_DVC0 19 +-#define R8A7791_CLK_SCU_CTU1_MIX1 20 +-#define R8A7791_CLK_SCU_CTU0_MIX0 21 +-#define R8A7791_CLK_SCU_SRC9 22 +-#define R8A7791_CLK_SCU_SRC8 23 +-#define R8A7791_CLK_SCU_SRC7 24 +-#define R8A7791_CLK_SCU_SRC6 25 +-#define R8A7791_CLK_SCU_SRC5 26 +-#define R8A7791_CLK_SCU_SRC4 27 +-#define R8A7791_CLK_SCU_SRC3 28 +-#define R8A7791_CLK_SCU_SRC2 29 +-#define R8A7791_CLK_SCU_SRC1 30 +-#define R8A7791_CLK_SCU_SRC0 31 +- +-/* MSTP11 */ +-#define R8A7791_CLK_SCIFA3 6 +-#define R8A7791_CLK_SCIFA4 7 +-#define R8A7791_CLK_SCIFA5 8 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7791-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7791-cpg-mssr.h +deleted file mode 100644 +index aadd06c566c0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7791-cpg-mssr.h ++++ /dev/null +@@ -1,44 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ +- * +- * Copyright (C) 2015 Renesas Electronics Corp. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ +- +-#include +- +-/* r8a7791 CPG Core Clocks */ +-#define R8A7791_CLK_Z 0 +-#define R8A7791_CLK_ZG 1 +-#define R8A7791_CLK_ZTR 2 +-#define R8A7791_CLK_ZTRD2 3 +-#define R8A7791_CLK_ZT 4 +-#define R8A7791_CLK_ZX 5 +-#define R8A7791_CLK_ZS 6 +-#define R8A7791_CLK_HP 7 +-#define R8A7791_CLK_I 8 +-#define R8A7791_CLK_B 9 +-#define R8A7791_CLK_LB 10 +-#define R8A7791_CLK_P 11 +-#define R8A7791_CLK_CL 12 +-#define R8A7791_CLK_M2 13 +-#define R8A7791_CLK_ADSP 14 +-#define R8A7791_CLK_ZB3 15 +-#define R8A7791_CLK_ZB3D2 16 +-#define R8A7791_CLK_DDR 17 +-#define R8A7791_CLK_SDH 18 +-#define R8A7791_CLK_SD0 19 +-#define R8A7791_CLK_SD2 20 +-#define R8A7791_CLK_SD3 21 +-#define R8A7791_CLK_MMC0 22 +-#define R8A7791_CLK_MP 23 +-#define R8A7791_CLK_SSP 24 +-#define R8A7791_CLK_SSPRS 25 +-#define R8A7791_CLK_QSPI 26 +-#define R8A7791_CLK_CP 27 +-#define R8A7791_CLK_RCAN 28 +-#define R8A7791_CLK_R 29 +-#define R8A7791_CLK_OSC 30 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7792-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7792-clock.h +deleted file mode 100644 +index 2948d9ce3a14..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7792-clock.h ++++ /dev/null +@@ -1,98 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (C) 2016 Cogent Embedded, Inc. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__ +-#define __DT_BINDINGS_CLOCK_R8A7792_H__ +- +-/* CPG */ +-#define R8A7792_CLK_MAIN 0 +-#define R8A7792_CLK_PLL0 1 +-#define R8A7792_CLK_PLL1 2 +-#define R8A7792_CLK_PLL3 3 +-#define R8A7792_CLK_LB 4 +-#define R8A7792_CLK_QSPI 5 +- +-/* MSTP0 */ +-#define R8A7792_CLK_MSIOF0 0 +- +-/* MSTP1 */ +-#define R8A7792_CLK_JPU 6 +-#define R8A7792_CLK_TMU1 11 +-#define R8A7792_CLK_TMU3 21 +-#define R8A7792_CLK_TMU2 22 +-#define R8A7792_CLK_CMT0 24 +-#define R8A7792_CLK_TMU0 25 +-#define R8A7792_CLK_VSP1DU1 27 +-#define R8A7792_CLK_VSP1DU0 28 +-#define R8A7792_CLK_VSP1_SY 31 +- +-/* MSTP2 */ +-#define R8A7792_CLK_MSIOF1 8 +-#define R8A7792_CLK_SYS_DMAC1 18 +-#define R8A7792_CLK_SYS_DMAC0 19 +- +-/* MSTP3 */ +-#define R8A7792_CLK_TPU0 4 +-#define R8A7792_CLK_SDHI0 14 +-#define R8A7792_CLK_CMT1 29 +- +-/* MSTP4 */ +-#define R8A7792_CLK_IRQC 7 +-#define R8A7792_CLK_INTC_SYS 8 +- +-/* MSTP5 */ +-#define R8A7792_CLK_AUDIO_DMAC0 2 +-#define R8A7792_CLK_THERMAL 22 +-#define R8A7792_CLK_PWM 23 +- +-/* MSTP7 */ +-#define R8A7792_CLK_HSCIF1 16 +-#define R8A7792_CLK_HSCIF0 17 +-#define R8A7792_CLK_SCIF3 18 +-#define R8A7792_CLK_SCIF2 19 +-#define R8A7792_CLK_SCIF1 20 +-#define R8A7792_CLK_SCIF0 21 +-#define R8A7792_CLK_DU1 23 +-#define R8A7792_CLK_DU0 24 +- +-/* MSTP8 */ +-#define R8A7792_CLK_VIN5 4 +-#define R8A7792_CLK_VIN4 5 +-#define R8A7792_CLK_VIN3 8 +-#define R8A7792_CLK_VIN2 9 +-#define R8A7792_CLK_VIN1 10 +-#define R8A7792_CLK_VIN0 11 +-#define R8A7792_CLK_ETHERAVB 12 +- +-/* MSTP9 */ +-#define R8A7792_CLK_GPIO7 4 +-#define R8A7792_CLK_GPIO6 5 +-#define R8A7792_CLK_GPIO5 7 +-#define R8A7792_CLK_GPIO4 8 +-#define R8A7792_CLK_GPIO3 9 +-#define R8A7792_CLK_GPIO2 10 +-#define R8A7792_CLK_GPIO1 11 +-#define R8A7792_CLK_GPIO0 12 +-#define R8A7792_CLK_GPIO11 13 +-#define R8A7792_CLK_GPIO10 14 +-#define R8A7792_CLK_CAN1 15 +-#define R8A7792_CLK_CAN0 16 +-#define R8A7792_CLK_QSPI_MOD 17 +-#define R8A7792_CLK_GPIO9 19 +-#define R8A7792_CLK_GPIO8 21 +-#define R8A7792_CLK_I2C5 25 +-#define R8A7792_CLK_IICDVFS 26 +-#define R8A7792_CLK_I2C4 27 +-#define R8A7792_CLK_I2C3 28 +-#define R8A7792_CLK_I2C2 29 +-#define R8A7792_CLK_I2C1 30 +-#define R8A7792_CLK_I2C0 31 +- +-/* MSTP10 */ +-#define R8A7792_CLK_SSI_ALL 5 +-#define R8A7792_CLK_SSI4 11 +-#define R8A7792_CLK_SSI3 12 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7792-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7792-cpg-mssr.h +deleted file mode 100644 +index 829c44db0271..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7792-cpg-mssr.h ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ +- * +- * Copyright (C) 2015 Renesas Electronics Corp. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ +- +-#include +- +-/* r8a7792 CPG Core Clocks */ +-#define R8A7792_CLK_Z 0 +-#define R8A7792_CLK_ZG 1 +-#define R8A7792_CLK_ZTR 2 +-#define R8A7792_CLK_ZTRD2 3 +-#define R8A7792_CLK_ZT 4 +-#define R8A7792_CLK_ZX 5 +-#define R8A7792_CLK_ZS 6 +-#define R8A7792_CLK_HP 7 +-#define R8A7792_CLK_I 8 +-#define R8A7792_CLK_B 9 +-#define R8A7792_CLK_LB 10 +-#define R8A7792_CLK_P 11 +-#define R8A7792_CLK_CL 12 +-#define R8A7792_CLK_M2 13 +-#define R8A7792_CLK_IMP 14 +-#define R8A7792_CLK_ZB3 15 +-#define R8A7792_CLK_ZB3D2 16 +-#define R8A7792_CLK_DDR 17 +-#define R8A7792_CLK_SD 18 +-#define R8A7792_CLK_MP 19 +-#define R8A7792_CLK_QSPI 20 +-#define R8A7792_CLK_CP 21 +-#define R8A7792_CLK_CPEX 22 +-#define R8A7792_CLK_RCAN 23 +-#define R8A7792_CLK_R 24 +-#define R8A7792_CLK_OSC 25 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7793-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7793-clock.h +deleted file mode 100644 +index 49c66d8ed178..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7793-clock.h ++++ /dev/null +@@ -1,159 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 +- * +- * r8a7793 clock definition +- * +- * Copyright (C) 2014 Renesas Electronics Corporation +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__ +-#define __DT_BINDINGS_CLOCK_R8A7793_H__ +- +-/* CPG */ +-#define R8A7793_CLK_MAIN 0 +-#define R8A7793_CLK_PLL0 1 +-#define R8A7793_CLK_PLL1 2 +-#define R8A7793_CLK_PLL3 3 +-#define R8A7793_CLK_LB 4 +-#define R8A7793_CLK_QSPI 5 +-#define R8A7793_CLK_SDH 6 +-#define R8A7793_CLK_SD0 7 +-#define R8A7793_CLK_Z 8 +-#define R8A7793_CLK_RCAN 9 +-#define R8A7793_CLK_ADSP 10 +- +-/* MSTP0 */ +-#define R8A7793_CLK_MSIOF0 0 +- +-/* MSTP1 */ +-#define R8A7793_CLK_VCP0 1 +-#define R8A7793_CLK_VPC0 3 +-#define R8A7793_CLK_SSP1 9 +-#define R8A7793_CLK_TMU1 11 +-#define R8A7793_CLK_3DG 12 +-#define R8A7793_CLK_2DDMAC 15 +-#define R8A7793_CLK_FDP1_1 18 +-#define R8A7793_CLK_FDP1_0 19 +-#define R8A7793_CLK_TMU3 21 +-#define R8A7793_CLK_TMU2 22 +-#define R8A7793_CLK_CMT0 24 +-#define R8A7793_CLK_TMU0 25 +-#define R8A7793_CLK_VSP1_DU1 27 +-#define R8A7793_CLK_VSP1_DU0 28 +-#define R8A7793_CLK_VSP1_S 31 +- +-/* MSTP2 */ +-#define R8A7793_CLK_SCIFA2 2 +-#define R8A7793_CLK_SCIFA1 3 +-#define R8A7793_CLK_SCIFA0 4 +-#define R8A7793_CLK_MSIOF2 5 +-#define R8A7793_CLK_SCIFB0 6 +-#define R8A7793_CLK_SCIFB1 7 +-#define R8A7793_CLK_MSIOF1 8 +-#define R8A7793_CLK_SCIFB2 16 +-#define R8A7793_CLK_SYS_DMAC1 18 +-#define R8A7793_CLK_SYS_DMAC0 19 +- +-/* MSTP3 */ +-#define R8A7793_CLK_TPU0 4 +-#define R8A7793_CLK_SDHI2 11 +-#define R8A7793_CLK_SDHI1 12 +-#define R8A7793_CLK_SDHI0 14 +-#define R8A7793_CLK_MMCIF0 15 +-#define R8A7793_CLK_IIC0 18 +-#define R8A7793_CLK_PCIEC 19 +-#define R8A7793_CLK_IIC1 23 +-#define R8A7793_CLK_SSUSB 28 +-#define R8A7793_CLK_CMT1 29 +-#define R8A7793_CLK_USBDMAC0 30 +-#define R8A7793_CLK_USBDMAC1 31 +- +-/* MSTP4 */ +-#define R8A7793_CLK_IRQC 7 +-#define R8A7793_CLK_INTC_SYS 8 +- +-/* MSTP5 */ +-#define R8A7793_CLK_AUDIO_DMAC1 1 +-#define R8A7793_CLK_AUDIO_DMAC0 2 +-#define R8A7793_CLK_ADSP_MOD 6 +-#define R8A7793_CLK_THERMAL 22 +-#define R8A7793_CLK_PWM 23 +- +-/* MSTP7 */ +-#define R8A7793_CLK_EHCI 3 +-#define R8A7793_CLK_HSUSB 4 +-#define R8A7793_CLK_HSCIF2 13 +-#define R8A7793_CLK_SCIF5 14 +-#define R8A7793_CLK_SCIF4 15 +-#define R8A7793_CLK_HSCIF1 16 +-#define R8A7793_CLK_HSCIF0 17 +-#define R8A7793_CLK_SCIF3 18 +-#define R8A7793_CLK_SCIF2 19 +-#define R8A7793_CLK_SCIF1 20 +-#define R8A7793_CLK_SCIF0 21 +-#define R8A7793_CLK_DU1 23 +-#define R8A7793_CLK_DU0 24 +-#define R8A7793_CLK_LVDS0 26 +- +-/* MSTP8 */ +-#define R8A7793_CLK_IPMMU_SGX 0 +-#define R8A7793_CLK_VIN2 9 +-#define R8A7793_CLK_VIN1 10 +-#define R8A7793_CLK_VIN0 11 +-#define R8A7793_CLK_ETHER 13 +-#define R8A7793_CLK_SATA1 14 +-#define R8A7793_CLK_SATA0 15 +- +-/* MSTP9 */ +-#define R8A7793_CLK_GPIO7 4 +-#define R8A7793_CLK_GPIO6 5 +-#define R8A7793_CLK_GPIO5 7 +-#define R8A7793_CLK_GPIO4 8 +-#define R8A7793_CLK_GPIO3 9 +-#define R8A7793_CLK_GPIO2 10 +-#define R8A7793_CLK_GPIO1 11 +-#define R8A7793_CLK_GPIO0 12 +-#define R8A7793_CLK_RCAN1 15 +-#define R8A7793_CLK_RCAN0 16 +-#define R8A7793_CLK_QSPI_MOD 17 +-#define R8A7793_CLK_I2C5 25 +-#define R8A7793_CLK_IICDVFS 26 +-#define R8A7793_CLK_I2C4 27 +-#define R8A7793_CLK_I2C3 28 +-#define R8A7793_CLK_I2C2 29 +-#define R8A7793_CLK_I2C1 30 +-#define R8A7793_CLK_I2C0 31 +- +-/* MSTP10 */ +-#define R8A7793_CLK_SSI_ALL 5 +-#define R8A7793_CLK_SSI9 6 +-#define R8A7793_CLK_SSI8 7 +-#define R8A7793_CLK_SSI7 8 +-#define R8A7793_CLK_SSI6 9 +-#define R8A7793_CLK_SSI5 10 +-#define R8A7793_CLK_SSI4 11 +-#define R8A7793_CLK_SSI3 12 +-#define R8A7793_CLK_SSI2 13 +-#define R8A7793_CLK_SSI1 14 +-#define R8A7793_CLK_SSI0 15 +-#define R8A7793_CLK_SCU_ALL 17 +-#define R8A7793_CLK_SCU_DVC1 18 +-#define R8A7793_CLK_SCU_DVC0 19 +-#define R8A7793_CLK_SCU_CTU1_MIX1 20 +-#define R8A7793_CLK_SCU_CTU0_MIX0 21 +-#define R8A7793_CLK_SCU_SRC9 22 +-#define R8A7793_CLK_SCU_SRC8 23 +-#define R8A7793_CLK_SCU_SRC7 24 +-#define R8A7793_CLK_SCU_SRC6 25 +-#define R8A7793_CLK_SCU_SRC5 26 +-#define R8A7793_CLK_SCU_SRC4 27 +-#define R8A7793_CLK_SCU_SRC3 28 +-#define R8A7793_CLK_SCU_SRC2 29 +-#define R8A7793_CLK_SCU_SRC1 30 +-#define R8A7793_CLK_SCU_SRC0 31 +- +-/* MSTP11 */ +-#define R8A7793_CLK_SCIFA3 6 +-#define R8A7793_CLK_SCIFA4 7 +-#define R8A7793_CLK_SCIFA5 8 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7793-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7793-cpg-mssr.h +deleted file mode 100644 +index d1ff646c31f2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7793-cpg-mssr.h ++++ /dev/null +@@ -1,44 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ +- * +- * Copyright (C) 2015 Renesas Electronics Corp. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ +- +-#include +- +-/* r8a7793 CPG Core Clocks */ +-#define R8A7793_CLK_Z 0 +-#define R8A7793_CLK_ZG 1 +-#define R8A7793_CLK_ZTR 2 +-#define R8A7793_CLK_ZTRD2 3 +-#define R8A7793_CLK_ZT 4 +-#define R8A7793_CLK_ZX 5 +-#define R8A7793_CLK_ZS 6 +-#define R8A7793_CLK_HP 7 +-#define R8A7793_CLK_I 8 +-#define R8A7793_CLK_B 9 +-#define R8A7793_CLK_LB 10 +-#define R8A7793_CLK_P 11 +-#define R8A7793_CLK_CL 12 +-#define R8A7793_CLK_M2 13 +-#define R8A7793_CLK_ADSP 14 +-#define R8A7793_CLK_ZB3 15 +-#define R8A7793_CLK_ZB3D2 16 +-#define R8A7793_CLK_DDR 17 +-#define R8A7793_CLK_SDH 18 +-#define R8A7793_CLK_SD0 19 +-#define R8A7793_CLK_SD2 20 +-#define R8A7793_CLK_SD3 21 +-#define R8A7793_CLK_MMC0 22 +-#define R8A7793_CLK_MP 23 +-#define R8A7793_CLK_SSP 24 +-#define R8A7793_CLK_SSPRS 25 +-#define R8A7793_CLK_QSPI 26 +-#define R8A7793_CLK_CP 27 +-#define R8A7793_CLK_RCAN 28 +-#define R8A7793_CLK_R 29 +-#define R8A7793_CLK_OSC 30 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7794-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7794-clock.h +deleted file mode 100644 +index 649f005782d0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7794-clock.h ++++ /dev/null +@@ -1,137 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ +- * +- * Copyright (C) 2014 Renesas Electronics Corporation +- * Copyright 2013 Ideas On Board SPRL +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__ +-#define __DT_BINDINGS_CLOCK_R8A7794_H__ +- +-/* CPG */ +-#define R8A7794_CLK_MAIN 0 +-#define R8A7794_CLK_PLL0 1 +-#define R8A7794_CLK_PLL1 2 +-#define R8A7794_CLK_PLL3 3 +-#define R8A7794_CLK_LB 4 +-#define R8A7794_CLK_QSPI 5 +-#define R8A7794_CLK_SDH 6 +-#define R8A7794_CLK_SD0 7 +-#define R8A7794_CLK_RCAN 8 +- +-/* MSTP0 */ +-#define R8A7794_CLK_MSIOF0 0 +- +-/* MSTP1 */ +-#define R8A7794_CLK_VCP0 1 +-#define R8A7794_CLK_VPC0 3 +-#define R8A7794_CLK_TMU1 11 +-#define R8A7794_CLK_3DG 12 +-#define R8A7794_CLK_2DDMAC 15 +-#define R8A7794_CLK_FDP1_0 19 +-#define R8A7794_CLK_TMU3 21 +-#define R8A7794_CLK_TMU2 22 +-#define R8A7794_CLK_CMT0 24 +-#define R8A7794_CLK_TMU0 25 +-#define R8A7794_CLK_VSP1_DU0 28 +-#define R8A7794_CLK_VSP1_S 31 +- +-/* MSTP2 */ +-#define R8A7794_CLK_SCIFA2 2 +-#define R8A7794_CLK_SCIFA1 3 +-#define R8A7794_CLK_SCIFA0 4 +-#define R8A7794_CLK_MSIOF2 5 +-#define R8A7794_CLK_SCIFB0 6 +-#define R8A7794_CLK_SCIFB1 7 +-#define R8A7794_CLK_MSIOF1 8 +-#define R8A7794_CLK_SCIFB2 16 +-#define R8A7794_CLK_SYS_DMAC1 18 +-#define R8A7794_CLK_SYS_DMAC0 19 +- +-/* MSTP3 */ +-#define R8A7794_CLK_SDHI2 11 +-#define R8A7794_CLK_SDHI1 12 +-#define R8A7794_CLK_SDHI0 14 +-#define R8A7794_CLK_MMCIF0 15 +-#define R8A7794_CLK_IIC0 18 +-#define R8A7794_CLK_IIC1 23 +-#define R8A7794_CLK_CMT1 29 +-#define R8A7794_CLK_USBDMAC0 30 +-#define R8A7794_CLK_USBDMAC1 31 +- +-/* MSTP4 */ +-#define R8A7794_CLK_IRQC 7 +-#define R8A7794_CLK_INTC_SYS 8 +- +-/* MSTP5 */ +-#define R8A7794_CLK_AUDIO_DMAC0 2 +-#define R8A7794_CLK_PWM 23 +- +-/* MSTP7 */ +-#define R8A7794_CLK_EHCI 3 +-#define R8A7794_CLK_HSUSB 4 +-#define R8A7794_CLK_HSCIF2 13 +-#define R8A7794_CLK_SCIF5 14 +-#define R8A7794_CLK_SCIF4 15 +-#define R8A7794_CLK_HSCIF1 16 +-#define R8A7794_CLK_HSCIF0 17 +-#define R8A7794_CLK_SCIF3 18 +-#define R8A7794_CLK_SCIF2 19 +-#define R8A7794_CLK_SCIF1 20 +-#define R8A7794_CLK_SCIF0 21 +-#define R8A7794_CLK_DU1 23 +-#define R8A7794_CLK_DU0 24 +- +-/* MSTP8 */ +-#define R8A7794_CLK_VIN1 10 +-#define R8A7794_CLK_VIN0 11 +-#define R8A7794_CLK_ETHERAVB 12 +-#define R8A7794_CLK_ETHER 13 +- +-/* MSTP9 */ +-#define R8A7794_CLK_GPIO6 5 +-#define R8A7794_CLK_GPIO5 7 +-#define R8A7794_CLK_GPIO4 8 +-#define R8A7794_CLK_GPIO3 9 +-#define R8A7794_CLK_GPIO2 10 +-#define R8A7794_CLK_GPIO1 11 +-#define R8A7794_CLK_GPIO0 12 +-#define R8A7794_CLK_RCAN1 15 +-#define R8A7794_CLK_RCAN0 16 +-#define R8A7794_CLK_QSPI_MOD 17 +-#define R8A7794_CLK_I2C5 25 +-#define R8A7794_CLK_I2C4 27 +-#define R8A7794_CLK_I2C3 28 +-#define R8A7794_CLK_I2C2 29 +-#define R8A7794_CLK_I2C1 30 +-#define R8A7794_CLK_I2C0 31 +- +-/* MSTP10 */ +-#define R8A7794_CLK_SSI_ALL 5 +-#define R8A7794_CLK_SSI9 6 +-#define R8A7794_CLK_SSI8 7 +-#define R8A7794_CLK_SSI7 8 +-#define R8A7794_CLK_SSI6 9 +-#define R8A7794_CLK_SSI5 10 +-#define R8A7794_CLK_SSI4 11 +-#define R8A7794_CLK_SSI3 12 +-#define R8A7794_CLK_SSI2 13 +-#define R8A7794_CLK_SSI1 14 +-#define R8A7794_CLK_SSI0 15 +-#define R8A7794_CLK_SCU_ALL 17 +-#define R8A7794_CLK_SCU_DVC1 18 +-#define R8A7794_CLK_SCU_DVC0 19 +-#define R8A7794_CLK_SCU_CTU1_MIX1 20 +-#define R8A7794_CLK_SCU_CTU0_MIX0 21 +-#define R8A7794_CLK_SCU_SRC6 25 +-#define R8A7794_CLK_SCU_SRC5 26 +-#define R8A7794_CLK_SCU_SRC4 27 +-#define R8A7794_CLK_SCU_SRC3 28 +-#define R8A7794_CLK_SCU_SRC2 29 +-#define R8A7794_CLK_SCU_SRC1 30 +- +-/* MSTP11 */ +-#define R8A7794_CLK_SCIFA3 6 +-#define R8A7794_CLK_SCIFA4 7 +-#define R8A7794_CLK_SCIFA5 8 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7794-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7794-cpg-mssr.h +deleted file mode 100644 +index 6314e23b51af..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7794-cpg-mssr.h ++++ /dev/null +@@ -1,43 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ +- * +- * Copyright (C) 2015 Renesas Electronics Corp. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ +- +-#include +- +-/* r8a7794 CPG Core Clocks */ +-#define R8A7794_CLK_Z2 0 +-#define R8A7794_CLK_ZG 1 +-#define R8A7794_CLK_ZTR 2 +-#define R8A7794_CLK_ZTRD2 3 +-#define R8A7794_CLK_ZT 4 +-#define R8A7794_CLK_ZX 5 +-#define R8A7794_CLK_ZS 6 +-#define R8A7794_CLK_HP 7 +-#define R8A7794_CLK_I 8 +-#define R8A7794_CLK_B 9 +-#define R8A7794_CLK_LB 10 +-#define R8A7794_CLK_P 11 +-#define R8A7794_CLK_CL 12 +-#define R8A7794_CLK_CP 13 +-#define R8A7794_CLK_M2 14 +-#define R8A7794_CLK_ADSP 15 +-#define R8A7794_CLK_ZB3 16 +-#define R8A7794_CLK_ZB3D2 17 +-#define R8A7794_CLK_DDR 18 +-#define R8A7794_CLK_SDH 19 +-#define R8A7794_CLK_SD0 20 +-#define R8A7794_CLK_SD2 21 +-#define R8A7794_CLK_SD3 22 +-#define R8A7794_CLK_MMC0 23 +-#define R8A7794_CLK_MP 24 +-#define R8A7794_CLK_QSPI 25 +-#define R8A7794_CLK_CPEX 26 +-#define R8A7794_CLK_RCAN 27 +-#define R8A7794_CLK_R 28 +-#define R8A7794_CLK_OSC 29 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7795-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7795-cpg-mssr.h +deleted file mode 100644 +index 92b3e2a95179..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7795-cpg-mssr.h ++++ /dev/null +@@ -1,66 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ +- * +- * Copyright (C) 2015 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ +- +-#include +- +-/* r8a7795 CPG Core Clocks */ +-#define R8A7795_CLK_Z 0 +-#define R8A7795_CLK_Z2 1 +-#define R8A7795_CLK_ZR 2 +-#define R8A7795_CLK_ZG 3 +-#define R8A7795_CLK_ZTR 4 +-#define R8A7795_CLK_ZTRD2 5 +-#define R8A7795_CLK_ZT 6 +-#define R8A7795_CLK_ZX 7 +-#define R8A7795_CLK_S0D1 8 +-#define R8A7795_CLK_S0D4 9 +-#define R8A7795_CLK_S1D1 10 +-#define R8A7795_CLK_S1D2 11 +-#define R8A7795_CLK_S1D4 12 +-#define R8A7795_CLK_S2D1 13 +-#define R8A7795_CLK_S2D2 14 +-#define R8A7795_CLK_S2D4 15 +-#define R8A7795_CLK_S3D1 16 +-#define R8A7795_CLK_S3D2 17 +-#define R8A7795_CLK_S3D4 18 +-#define R8A7795_CLK_LB 19 +-#define R8A7795_CLK_CL 20 +-#define R8A7795_CLK_ZB3 21 +-#define R8A7795_CLK_ZB3D2 22 +-#define R8A7795_CLK_CR 23 +-#define R8A7795_CLK_CRD2 24 +-#define R8A7795_CLK_SD0H 25 +-#define R8A7795_CLK_SD0 26 +-#define R8A7795_CLK_SD1H 27 +-#define R8A7795_CLK_SD1 28 +-#define R8A7795_CLK_SD2H 29 +-#define R8A7795_CLK_SD2 30 +-#define R8A7795_CLK_SD3H 31 +-#define R8A7795_CLK_SD3 32 +-#define R8A7795_CLK_SSP2 33 +-#define R8A7795_CLK_SSP1 34 +-#define R8A7795_CLK_SSPRS 35 +-#define R8A7795_CLK_RPC 36 +-#define R8A7795_CLK_RPCD2 37 +-#define R8A7795_CLK_MSO 38 +-#define R8A7795_CLK_CANFD 39 +-#define R8A7795_CLK_HDMI 40 +-#define R8A7795_CLK_CSI0 41 +-/* CLK_CSIREF was removed */ +-#define R8A7795_CLK_CP 43 +-#define R8A7795_CLK_CPEX 44 +-#define R8A7795_CLK_R 45 +-#define R8A7795_CLK_OSC 46 +- +-/* r8a7795 ES2.0 CPG Core Clocks */ +-#define R8A7795_CLK_S0D2 47 +-#define R8A7795_CLK_S0D3 48 +-#define R8A7795_CLK_S0D6 49 +-#define R8A7795_CLK_S0D8 50 +-#define R8A7795_CLK_S0D12 51 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7796-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7796-cpg-mssr.h +deleted file mode 100644 +index c0957cf45840..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7796-cpg-mssr.h ++++ /dev/null +@@ -1,65 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ +- * +- * Copyright (C) 2016 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ +- +-#include +- +-/* r8a7796 CPG Core Clocks */ +-#define R8A7796_CLK_Z 0 +-#define R8A7796_CLK_Z2 1 +-#define R8A7796_CLK_ZR 2 +-#define R8A7796_CLK_ZG 3 +-#define R8A7796_CLK_ZTR 4 +-#define R8A7796_CLK_ZTRD2 5 +-#define R8A7796_CLK_ZT 6 +-#define R8A7796_CLK_ZX 7 +-#define R8A7796_CLK_S0D1 8 +-#define R8A7796_CLK_S0D2 9 +-#define R8A7796_CLK_S0D3 10 +-#define R8A7796_CLK_S0D4 11 +-#define R8A7796_CLK_S0D6 12 +-#define R8A7796_CLK_S0D8 13 +-#define R8A7796_CLK_S0D12 14 +-#define R8A7796_CLK_S1D1 15 +-#define R8A7796_CLK_S1D2 16 +-#define R8A7796_CLK_S1D4 17 +-#define R8A7796_CLK_S2D1 18 +-#define R8A7796_CLK_S2D2 19 +-#define R8A7796_CLK_S2D4 20 +-#define R8A7796_CLK_S3D1 21 +-#define R8A7796_CLK_S3D2 22 +-#define R8A7796_CLK_S3D4 23 +-#define R8A7796_CLK_LB 24 +-#define R8A7796_CLK_CL 25 +-#define R8A7796_CLK_ZB3 26 +-#define R8A7796_CLK_ZB3D2 27 +-#define R8A7796_CLK_ZB3D4 28 +-#define R8A7796_CLK_CR 29 +-#define R8A7796_CLK_CRD2 30 +-#define R8A7796_CLK_SD0H 31 +-#define R8A7796_CLK_SD0 32 +-#define R8A7796_CLK_SD1H 33 +-#define R8A7796_CLK_SD1 34 +-#define R8A7796_CLK_SD2H 35 +-#define R8A7796_CLK_SD2 36 +-#define R8A7796_CLK_SD3H 37 +-#define R8A7796_CLK_SD3 38 +-#define R8A7796_CLK_SSP2 39 +-#define R8A7796_CLK_SSP1 40 +-#define R8A7796_CLK_SSPRS 41 +-#define R8A7796_CLK_RPC 42 +-#define R8A7796_CLK_RPCD2 43 +-#define R8A7796_CLK_MSO 44 +-#define R8A7796_CLK_CANFD 45 +-#define R8A7796_CLK_HDMI 46 +-#define R8A7796_CLK_CSI0 47 +-/* CLK_CSIREF was removed */ +-#define R8A7796_CLK_CP 49 +-#define R8A7796_CLK_CPEX 50 +-#define R8A7796_CLK_R 51 +-#define R8A7796_CLK_OSC 52 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77961-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77961-cpg-mssr.h +deleted file mode 100644 +index 7921d785546d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77961-cpg-mssr.h ++++ /dev/null +@@ -1,65 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ +- * +- * Copyright (C) 2019 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ +- +-#include +- +-/* r8a77961 CPG Core Clocks */ +-#define R8A77961_CLK_Z 0 +-#define R8A77961_CLK_Z2 1 +-#define R8A77961_CLK_ZR 2 +-#define R8A77961_CLK_ZG 3 +-#define R8A77961_CLK_ZTR 4 +-#define R8A77961_CLK_ZTRD2 5 +-#define R8A77961_CLK_ZT 6 +-#define R8A77961_CLK_ZX 7 +-#define R8A77961_CLK_S0D1 8 +-#define R8A77961_CLK_S0D2 9 +-#define R8A77961_CLK_S0D3 10 +-#define R8A77961_CLK_S0D4 11 +-#define R8A77961_CLK_S0D6 12 +-#define R8A77961_CLK_S0D8 13 +-#define R8A77961_CLK_S0D12 14 +-#define R8A77961_CLK_S1D1 15 +-#define R8A77961_CLK_S1D2 16 +-#define R8A77961_CLK_S1D4 17 +-#define R8A77961_CLK_S2D1 18 +-#define R8A77961_CLK_S2D2 19 +-#define R8A77961_CLK_S2D4 20 +-#define R8A77961_CLK_S3D1 21 +-#define R8A77961_CLK_S3D2 22 +-#define R8A77961_CLK_S3D4 23 +-#define R8A77961_CLK_LB 24 +-#define R8A77961_CLK_CL 25 +-#define R8A77961_CLK_ZB3 26 +-#define R8A77961_CLK_ZB3D2 27 +-#define R8A77961_CLK_ZB3D4 28 +-#define R8A77961_CLK_CR 29 +-#define R8A77961_CLK_CRD2 30 +-#define R8A77961_CLK_SD0H 31 +-#define R8A77961_CLK_SD0 32 +-#define R8A77961_CLK_SD1H 33 +-#define R8A77961_CLK_SD1 34 +-#define R8A77961_CLK_SD2H 35 +-#define R8A77961_CLK_SD2 36 +-#define R8A77961_CLK_SD3H 37 +-#define R8A77961_CLK_SD3 38 +-#define R8A77961_CLK_SSP2 39 +-#define R8A77961_CLK_SSP1 40 +-#define R8A77961_CLK_SSPRS 41 +-#define R8A77961_CLK_RPC 42 +-#define R8A77961_CLK_RPCD2 43 +-#define R8A77961_CLK_MSO 44 +-#define R8A77961_CLK_CANFD 45 +-#define R8A77961_CLK_HDMI 46 +-#define R8A77961_CLK_CSI0 47 +-/* CLK_CSIREF was removed */ +-#define R8A77961_CLK_CP 49 +-#define R8A77961_CLK_CPEX 50 +-#define R8A77961_CLK_R 51 +-#define R8A77961_CLK_OSC 52 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77965-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77965-cpg-mssr.h +deleted file mode 100644 +index 6d3b5a9a6084..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77965-cpg-mssr.h ++++ /dev/null +@@ -1,62 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2018 Jacopo Mondi +- */ +-#ifndef __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ +- +-#include +- +-/* r8a77965 CPG Core Clocks */ +-#define R8A77965_CLK_Z 0 +-#define R8A77965_CLK_ZR 1 +-#define R8A77965_CLK_ZG 2 +-#define R8A77965_CLK_ZTR 3 +-#define R8A77965_CLK_ZTRD2 4 +-#define R8A77965_CLK_ZT 5 +-#define R8A77965_CLK_ZX 6 +-#define R8A77965_CLK_S0D1 7 +-#define R8A77965_CLK_S0D2 8 +-#define R8A77965_CLK_S0D3 9 +-#define R8A77965_CLK_S0D4 10 +-#define R8A77965_CLK_S0D6 11 +-#define R8A77965_CLK_S0D8 12 +-#define R8A77965_CLK_S0D12 13 +-#define R8A77965_CLK_S1D1 14 +-#define R8A77965_CLK_S1D2 15 +-#define R8A77965_CLK_S1D4 16 +-#define R8A77965_CLK_S2D1 17 +-#define R8A77965_CLK_S2D2 18 +-#define R8A77965_CLK_S2D4 19 +-#define R8A77965_CLK_S3D1 20 +-#define R8A77965_CLK_S3D2 21 +-#define R8A77965_CLK_S3D4 22 +-#define R8A77965_CLK_LB 23 +-#define R8A77965_CLK_CL 24 +-#define R8A77965_CLK_ZB3 25 +-#define R8A77965_CLK_ZB3D2 26 +-#define R8A77965_CLK_CR 27 +-#define R8A77965_CLK_CRD2 28 +-#define R8A77965_CLK_SD0H 29 +-#define R8A77965_CLK_SD0 30 +-#define R8A77965_CLK_SD1H 31 +-#define R8A77965_CLK_SD1 32 +-#define R8A77965_CLK_SD2H 33 +-#define R8A77965_CLK_SD2 34 +-#define R8A77965_CLK_SD3H 35 +-#define R8A77965_CLK_SD3 36 +-#define R8A77965_CLK_SSP2 37 +-#define R8A77965_CLK_SSP1 38 +-#define R8A77965_CLK_SSPRS 39 +-#define R8A77965_CLK_RPC 40 +-#define R8A77965_CLK_RPCD2 41 +-#define R8A77965_CLK_MSO 42 +-#define R8A77965_CLK_CANFD 43 +-#define R8A77965_CLK_HDMI 44 +-#define R8A77965_CLK_CSI0 45 +-#define R8A77965_CLK_CP 46 +-#define R8A77965_CLK_CPEX 47 +-#define R8A77965_CLK_R 48 +-#define R8A77965_CLK_OSC 49 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77970-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77970-cpg-mssr.h +deleted file mode 100644 +index 6145ebe66361..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77970-cpg-mssr.h ++++ /dev/null +@@ -1,44 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ +- * +- * Copyright (C) 2016 Renesas Electronics Corp. +- * Copyright (C) 2017 Cogent Embedded, Inc. +- */ +-#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ +- +-#include +- +-/* r8a77970 CPG Core Clocks */ +-#define R8A77970_CLK_Z2 0 +-#define R8A77970_CLK_ZR 1 +-#define R8A77970_CLK_ZTR 2 +-#define R8A77970_CLK_ZTRD2 3 +-#define R8A77970_CLK_ZT 4 +-#define R8A77970_CLK_ZX 5 +-#define R8A77970_CLK_S1D1 6 +-#define R8A77970_CLK_S1D2 7 +-#define R8A77970_CLK_S1D4 8 +-#define R8A77970_CLK_S2D1 9 +-#define R8A77970_CLK_S2D2 10 +-#define R8A77970_CLK_S2D4 11 +-#define R8A77970_CLK_LB 12 +-#define R8A77970_CLK_CL 13 +-#define R8A77970_CLK_ZB3 14 +-#define R8A77970_CLK_ZB3D2 15 +-#define R8A77970_CLK_DDR 16 +-#define R8A77970_CLK_CR 17 +-#define R8A77970_CLK_CRD2 18 +-#define R8A77970_CLK_SD0H 19 +-#define R8A77970_CLK_SD0 20 +-#define R8A77970_CLK_RPC 21 +-#define R8A77970_CLK_RPCD2 22 +-#define R8A77970_CLK_MSO 23 +-#define R8A77970_CLK_CANFD 24 +-#define R8A77970_CLK_CSI0 25 +-#define R8A77970_CLK_FRAY 26 +-#define R8A77970_CLK_CP 27 +-#define R8A77970_CLK_CPEX 28 +-#define R8A77970_CLK_R 29 +-#define R8A77970_CLK_OSC 30 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77980-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77980-cpg-mssr.h +deleted file mode 100644 +index a4c0d76c392e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77980-cpg-mssr.h ++++ /dev/null +@@ -1,51 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright (C) 2018 Renesas Electronics Corp. +- * Copyright (C) 2018 Cogent Embedded, Inc. +- */ +-#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ +- +-#include +- +-/* r8a77980 CPG Core Clocks */ +-#define R8A77980_CLK_Z2 0 +-#define R8A77980_CLK_ZR 1 +-#define R8A77980_CLK_ZTR 2 +-#define R8A77980_CLK_ZTRD2 3 +-#define R8A77980_CLK_ZT 4 +-#define R8A77980_CLK_ZX 5 +-#define R8A77980_CLK_S0D1 6 +-#define R8A77980_CLK_S0D2 7 +-#define R8A77980_CLK_S0D3 8 +-#define R8A77980_CLK_S0D4 9 +-#define R8A77980_CLK_S0D6 10 +-#define R8A77980_CLK_S0D12 11 +-#define R8A77980_CLK_S0D24 12 +-#define R8A77980_CLK_S1D1 13 +-#define R8A77980_CLK_S1D2 14 +-#define R8A77980_CLK_S1D4 15 +-#define R8A77980_CLK_S2D1 16 +-#define R8A77980_CLK_S2D2 17 +-#define R8A77980_CLK_S2D4 18 +-#define R8A77980_CLK_S3D1 19 +-#define R8A77980_CLK_S3D2 20 +-#define R8A77980_CLK_S3D4 21 +-#define R8A77980_CLK_LB 22 +-#define R8A77980_CLK_CL 23 +-#define R8A77980_CLK_ZB3 24 +-#define R8A77980_CLK_ZB3D2 25 +-#define R8A77980_CLK_ZB3D4 26 +-#define R8A77980_CLK_SD0H 27 +-#define R8A77980_CLK_SD0 28 +-#define R8A77980_CLK_RPC 29 +-#define R8A77980_CLK_RPCD2 30 +-#define R8A77980_CLK_MSO 31 +-#define R8A77980_CLK_CANFD 32 +-#define R8A77980_CLK_CSI0 33 +-#define R8A77980_CLK_CP 34 +-#define R8A77980_CLK_CPEX 35 +-#define R8A77980_CLK_R 36 +-#define R8A77980_CLK_OSC 37 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77990-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77990-cpg-mssr.h +deleted file mode 100644 +index a596a482f3a9..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77990-cpg-mssr.h ++++ /dev/null +@@ -1,62 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ +- +-#include +- +-/* r8a77990 CPG Core Clocks */ +-#define R8A77990_CLK_Z2 0 +-#define R8A77990_CLK_ZR 1 +-#define R8A77990_CLK_ZG 2 +-#define R8A77990_CLK_ZTR 3 +-#define R8A77990_CLK_ZT 4 +-#define R8A77990_CLK_ZX 5 +-#define R8A77990_CLK_S0D1 6 +-#define R8A77990_CLK_S0D3 7 +-#define R8A77990_CLK_S0D6 8 +-#define R8A77990_CLK_S0D12 9 +-#define R8A77990_CLK_S0D24 10 +-#define R8A77990_CLK_S1D1 11 +-#define R8A77990_CLK_S1D2 12 +-#define R8A77990_CLK_S1D4 13 +-#define R8A77990_CLK_S2D1 14 +-#define R8A77990_CLK_S2D2 15 +-#define R8A77990_CLK_S2D4 16 +-#define R8A77990_CLK_S3D1 17 +-#define R8A77990_CLK_S3D2 18 +-#define R8A77990_CLK_S3D4 19 +-#define R8A77990_CLK_S0D6C 20 +-#define R8A77990_CLK_S3D1C 21 +-#define R8A77990_CLK_S3D2C 22 +-#define R8A77990_CLK_S3D4C 23 +-#define R8A77990_CLK_LB 24 +-#define R8A77990_CLK_CL 25 +-#define R8A77990_CLK_ZB3 26 +-#define R8A77990_CLK_ZB3D2 27 +-#define R8A77990_CLK_CR 28 +-#define R8A77990_CLK_CRD2 29 +-#define R8A77990_CLK_SD0H 30 +-#define R8A77990_CLK_SD0 31 +-#define R8A77990_CLK_SD1H 32 +-#define R8A77990_CLK_SD1 33 +-#define R8A77990_CLK_SD3H 34 +-#define R8A77990_CLK_SD3 35 +-#define R8A77990_CLK_RPC 36 +-#define R8A77990_CLK_RPCD2 37 +-#define R8A77990_CLK_ZA2 38 +-#define R8A77990_CLK_ZA8 39 +-#define R8A77990_CLK_Z2D 40 +-#define R8A77990_CLK_CANFD 41 +-#define R8A77990_CLK_MSO 42 +-#define R8A77990_CLK_R 43 +-#define R8A77990_CLK_OSC 44 +-#define R8A77990_CLK_LV0 45 +-#define R8A77990_CLK_LV1 46 +-#define R8A77990_CLK_CSI0 47 +-#define R8A77990_CLK_CP 48 +-#define R8A77990_CLK_CPEX 49 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77995-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77995-cpg-mssr.h +deleted file mode 100644 +index fd701c4e87cf..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a77995-cpg-mssr.h ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ +- * +- * Copyright (C) 2017 Glider bvba +- */ +-#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ +- +-#include +- +-/* r8a77995 CPG Core Clocks */ +-#define R8A77995_CLK_Z2 0 +-#define R8A77995_CLK_ZG 1 +-#define R8A77995_CLK_ZTR 2 +-#define R8A77995_CLK_ZT 3 +-#define R8A77995_CLK_ZX 4 +-#define R8A77995_CLK_S0D1 5 +-#define R8A77995_CLK_S1D1 6 +-#define R8A77995_CLK_S1D2 7 +-#define R8A77995_CLK_S1D4 8 +-#define R8A77995_CLK_S2D1 9 +-#define R8A77995_CLK_S2D2 10 +-#define R8A77995_CLK_S2D4 11 +-#define R8A77995_CLK_S3D1 12 +-#define R8A77995_CLK_S3D2 13 +-#define R8A77995_CLK_S3D4 14 +-#define R8A77995_CLK_S1D4C 15 +-#define R8A77995_CLK_S3D1C 16 +-#define R8A77995_CLK_S3D2C 17 +-#define R8A77995_CLK_S3D4C 18 +-#define R8A77995_CLK_LB 19 +-#define R8A77995_CLK_CL 20 +-#define R8A77995_CLK_ZB3 21 +-#define R8A77995_CLK_ZB3D2 22 +-#define R8A77995_CLK_CR 23 +-#define R8A77995_CLK_CRD2 24 +-#define R8A77995_CLK_SD0H 25 +-#define R8A77995_CLK_SD0 26 +-/* CLK_SSP2 was removed */ +-/* CLK_SSP1 was removed */ +-#define R8A77995_CLK_RPC 29 +-#define R8A77995_CLK_RPCD2 30 +-#define R8A77995_CLK_ZA2 31 +-#define R8A77995_CLK_ZA8 32 +-#define R8A77995_CLK_Z2D 33 +-#define R8A77995_CLK_CANFD 34 +-#define R8A77995_CLK_MSO 35 +-#define R8A77995_CLK_R 36 +-#define R8A77995_CLK_OSC 37 +-#define R8A77995_CLK_LV0 38 +-#define R8A77995_CLK_LV1 39 +-#define R8A77995_CLK_CP 40 +-#define R8A77995_CLK_CPEX 41 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a779a0-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r8a779a0-cpg-mssr.h +deleted file mode 100644 +index f1d737ca7ca1..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r8a779a0-cpg-mssr.h ++++ /dev/null +@@ -1,55 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ +- +-#include +- +-/* r8a779A0 CPG Core Clocks */ +-#define R8A779A0_CLK_Z0 0 +-#define R8A779A0_CLK_ZX 1 +-#define R8A779A0_CLK_Z1 2 +-#define R8A779A0_CLK_ZR 3 +-#define R8A779A0_CLK_ZS 4 +-#define R8A779A0_CLK_ZT 5 +-#define R8A779A0_CLK_ZTR 6 +-#define R8A779A0_CLK_S1D1 7 +-#define R8A779A0_CLK_S1D2 8 +-#define R8A779A0_CLK_S1D4 9 +-#define R8A779A0_CLK_S1D8 10 +-#define R8A779A0_CLK_S1D12 11 +-#define R8A779A0_CLK_S3D1 12 +-#define R8A779A0_CLK_S3D2 13 +-#define R8A779A0_CLK_S3D4 14 +-#define R8A779A0_CLK_LB 15 +-#define R8A779A0_CLK_CP 16 +-#define R8A779A0_CLK_CL 17 +-#define R8A779A0_CLK_CL16MCK 18 +-#define R8A779A0_CLK_ZB30 19 +-#define R8A779A0_CLK_ZB30D2 20 +-#define R8A779A0_CLK_ZB30D4 21 +-#define R8A779A0_CLK_ZB31 22 +-#define R8A779A0_CLK_ZB31D2 23 +-#define R8A779A0_CLK_ZB31D4 24 +-#define R8A779A0_CLK_SD0H 25 +-#define R8A779A0_CLK_SD0 26 +-#define R8A779A0_CLK_RPC 27 +-#define R8A779A0_CLK_RPCD2 28 +-#define R8A779A0_CLK_MSO 29 +-#define R8A779A0_CLK_CANFD 30 +-#define R8A779A0_CLK_CSI0 31 +-#define R8A779A0_CLK_FRAY 32 +-#define R8A779A0_CLK_DSI 33 +-#define R8A779A0_CLK_VIP 34 +-#define R8A779A0_CLK_ADGH 35 +-#define R8A779A0_CLK_CNNDSP 36 +-#define R8A779A0_CLK_ICU 37 +-#define R8A779A0_CLK_ICUD2 38 +-#define R8A779A0_CLK_VCBUS 39 +-#define R8A779A0_CLK_CBFUSA 40 +-#define R8A779A0_CLK_R 41 +-#define R8A779A0_CLK_OSC 42 +- +-#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r9a06g032-sysctrl.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r9a06g032-sysctrl.h +deleted file mode 100644 +index 90c0f3dc1ba1..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r9a06g032-sysctrl.h ++++ /dev/null +@@ -1,148 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * R9A06G032 sysctrl IDs +- * +- * Copyright (C) 2018 Renesas Electronics Europe Limited +- * +- * Michel Pollet , +- */ +- +-#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__ +-#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__ +- +-#define R9A06G032_CLK_PLL_USB 1 +-#define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */ +-#define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */ +-#define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */ +-#define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */ +-#define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */ +-#define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */ +-#define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */ +-#define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */ +-#define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */ +-#define R9A06G032_CLK_25_PG4 26 +-#define R9A06G032_CLK_25_PG5 27 +-#define R9A06G032_CLK_25_PG6 28 +-#define R9A06G032_CLK_25_PG7 29 +-#define R9A06G032_CLK_25_PG8 30 +-#define R9A06G032_CLK_ADC 31 +-#define R9A06G032_CLK_ECAT100 32 +-#define R9A06G032_CLK_HSR100 33 +-#define R9A06G032_CLK_I2C0 34 +-#define R9A06G032_CLK_I2C1 35 +-#define R9A06G032_CLK_MII_REF 36 +-#define R9A06G032_CLK_NAND 37 +-#define R9A06G032_CLK_NOUSBP2_PG6 38 +-#define R9A06G032_CLK_P1_PG2 39 +-#define R9A06G032_CLK_P1_PG3 40 +-#define R9A06G032_CLK_P1_PG4 41 +-#define R9A06G032_CLK_P4_PG3 42 +-#define R9A06G032_CLK_P4_PG4 43 +-#define R9A06G032_CLK_P6_PG1 44 +-#define R9A06G032_CLK_P6_PG2 45 +-#define R9A06G032_CLK_P6_PG3 46 +-#define R9A06G032_CLK_P6_PG4 47 +-#define R9A06G032_CLK_PCI_USB 48 +-#define R9A06G032_CLK_QSPI0 49 +-#define R9A06G032_CLK_QSPI1 50 +-#define R9A06G032_CLK_RGMII_REF 51 +-#define R9A06G032_CLK_RMII_REF 52 +-#define R9A06G032_CLK_SDIO0 53 +-#define R9A06G032_CLK_SDIO1 54 +-#define R9A06G032_CLK_SERCOS100 55 +-#define R9A06G032_CLK_SLCD 56 +-#define R9A06G032_CLK_SPI0 57 +-#define R9A06G032_CLK_SPI1 58 +-#define R9A06G032_CLK_SPI2 59 +-#define R9A06G032_CLK_SPI3 60 +-#define R9A06G032_CLK_SPI4 61 +-#define R9A06G032_CLK_SPI5 62 +-#define R9A06G032_CLK_SWITCH 63 +-#define R9A06G032_HCLK_ECAT125 65 +-#define R9A06G032_HCLK_PINCONFIG 66 +-#define R9A06G032_HCLK_SERCOS 67 +-#define R9A06G032_HCLK_SGPIO2 68 +-#define R9A06G032_HCLK_SGPIO3 69 +-#define R9A06G032_HCLK_SGPIO4 70 +-#define R9A06G032_HCLK_TIMER0 71 +-#define R9A06G032_HCLK_TIMER1 72 +-#define R9A06G032_HCLK_USBF 73 +-#define R9A06G032_HCLK_USBH 74 +-#define R9A06G032_HCLK_USBPM 75 +-#define R9A06G032_CLK_48_PG_F 76 +-#define R9A06G032_CLK_48_PG4 77 +-#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */ +-#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */ +-#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */ +-#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */ +-#define R9A06G032_HCLK_CAN0 85 +-#define R9A06G032_HCLK_CAN1 86 +-#define R9A06G032_HCLK_DELTASIGMA 87 +-#define R9A06G032_HCLK_PWMPTO 88 +-#define R9A06G032_HCLK_RSV 89 +-#define R9A06G032_HCLK_SGPIO0 90 +-#define R9A06G032_HCLK_SGPIO1 91 +-#define R9A06G032_RTOS_MDC 92 +-#define R9A06G032_CLK_CM3 93 +-#define R9A06G032_CLK_DDRC 94 +-#define R9A06G032_CLK_ECAT25 95 +-#define R9A06G032_CLK_HSR50 96 +-#define R9A06G032_CLK_HW_RTOS 97 +-#define R9A06G032_CLK_SERCOS50 98 +-#define R9A06G032_HCLK_ADC 99 +-#define R9A06G032_HCLK_CM3 100 +-#define R9A06G032_HCLK_CRYPTO_EIP150 101 +-#define R9A06G032_HCLK_CRYPTO_EIP93 102 +-#define R9A06G032_HCLK_DDRC 103 +-#define R9A06G032_HCLK_DMA0 104 +-#define R9A06G032_HCLK_DMA1 105 +-#define R9A06G032_HCLK_GMAC0 106 +-#define R9A06G032_HCLK_GMAC1 107 +-#define R9A06G032_HCLK_GPIO0 108 +-#define R9A06G032_HCLK_GPIO1 109 +-#define R9A06G032_HCLK_GPIO2 110 +-#define R9A06G032_HCLK_HSR 111 +-#define R9A06G032_HCLK_I2C0 112 +-#define R9A06G032_HCLK_I2C1 113 +-#define R9A06G032_HCLK_LCD 114 +-#define R9A06G032_HCLK_MSEBI_M 115 +-#define R9A06G032_HCLK_MSEBI_S 116 +-#define R9A06G032_HCLK_NAND 117 +-#define R9A06G032_HCLK_PG_I 118 +-#define R9A06G032_HCLK_PG19 119 +-#define R9A06G032_HCLK_PG20 120 +-#define R9A06G032_HCLK_PG3 121 +-#define R9A06G032_HCLK_PG4 122 +-#define R9A06G032_HCLK_QSPI0 123 +-#define R9A06G032_HCLK_QSPI1 124 +-#define R9A06G032_HCLK_ROM 125 +-#define R9A06G032_HCLK_RTC 126 +-#define R9A06G032_HCLK_SDIO0 127 +-#define R9A06G032_HCLK_SDIO1 128 +-#define R9A06G032_HCLK_SEMAP 129 +-#define R9A06G032_HCLK_SPI0 130 +-#define R9A06G032_HCLK_SPI1 131 +-#define R9A06G032_HCLK_SPI2 132 +-#define R9A06G032_HCLK_SPI3 133 +-#define R9A06G032_HCLK_SPI4 134 +-#define R9A06G032_HCLK_SPI5 135 +-#define R9A06G032_HCLK_SWITCH 136 +-#define R9A06G032_HCLK_SWITCH_RG 137 +-#define R9A06G032_HCLK_UART0 138 +-#define R9A06G032_HCLK_UART1 139 +-#define R9A06G032_HCLK_UART2 140 +-#define R9A06G032_HCLK_UART3 141 +-#define R9A06G032_HCLK_UART4 142 +-#define R9A06G032_HCLK_UART5 143 +-#define R9A06G032_HCLK_UART6 144 +-#define R9A06G032_HCLK_UART7 145 +-#define R9A06G032_CLK_UART0 146 +-#define R9A06G032_CLK_UART1 147 +-#define R9A06G032_CLK_UART2 148 +-#define R9A06G032_CLK_UART3 149 +-#define R9A06G032_CLK_UART4 150 +-#define R9A06G032_CLK_UART5 151 +-#define R9A06G032_CLK_UART6 152 +-#define R9A06G032_CLK_UART7 153 +- +-#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/r9a07g044-cpg.h b/scripts/dtc/include-prefixes/dt-bindings/clock/r9a07g044-cpg.h +deleted file mode 100644 +index 0bb17ff1a01a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/r9a07g044-cpg.h ++++ /dev/null +@@ -1,220 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +- * +- * Copyright (C) 2021 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ +-#define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ +- +-#include +- +-/* R9A07G044 CPG Core Clocks */ +-#define R9A07G044_CLK_I 0 +-#define R9A07G044_CLK_I2 1 +-#define R9A07G044_CLK_G 2 +-#define R9A07G044_CLK_S0 3 +-#define R9A07G044_CLK_S1 4 +-#define R9A07G044_CLK_SPI0 5 +-#define R9A07G044_CLK_SPI1 6 +-#define R9A07G044_CLK_SD0 7 +-#define R9A07G044_CLK_SD1 8 +-#define R9A07G044_CLK_M0 9 +-#define R9A07G044_CLK_M1 10 +-#define R9A07G044_CLK_M2 11 +-#define R9A07G044_CLK_M3 12 +-#define R9A07G044_CLK_M4 13 +-#define R9A07G044_CLK_HP 14 +-#define R9A07G044_CLK_TSU 15 +-#define R9A07G044_CLK_ZT 16 +-#define R9A07G044_CLK_P0 17 +-#define R9A07G044_CLK_P1 18 +-#define R9A07G044_CLK_P2 19 +-#define R9A07G044_CLK_AT 20 +-#define R9A07G044_OSCCLK 21 +-#define R9A07G044_CLK_P0_DIV2 22 +- +-/* R9A07G044 Module Clocks */ +-#define R9A07G044_CA55_SCLK 0 +-#define R9A07G044_CA55_PCLK 1 +-#define R9A07G044_CA55_ATCLK 2 +-#define R9A07G044_CA55_GICCLK 3 +-#define R9A07G044_CA55_PERICLK 4 +-#define R9A07G044_CA55_ACLK 5 +-#define R9A07G044_CA55_TSCLK 6 +-#define R9A07G044_GIC600_GICCLK 7 +-#define R9A07G044_IA55_CLK 8 +-#define R9A07G044_IA55_PCLK 9 +-#define R9A07G044_MHU_PCLK 10 +-#define R9A07G044_SYC_CNT_CLK 11 +-#define R9A07G044_DMAC_ACLK 12 +-#define R9A07G044_DMAC_PCLK 13 +-#define R9A07G044_OSTM0_PCLK 14 +-#define R9A07G044_OSTM1_PCLK 15 +-#define R9A07G044_OSTM2_PCLK 16 +-#define R9A07G044_MTU_X_MCK_MTU3 17 +-#define R9A07G044_POE3_CLKM_POE 18 +-#define R9A07G044_GPT_PCLK 19 +-#define R9A07G044_POEG_A_CLKP 20 +-#define R9A07G044_POEG_B_CLKP 21 +-#define R9A07G044_POEG_C_CLKP 22 +-#define R9A07G044_POEG_D_CLKP 23 +-#define R9A07G044_WDT0_PCLK 24 +-#define R9A07G044_WDT0_CLK 25 +-#define R9A07G044_WDT1_PCLK 26 +-#define R9A07G044_WDT1_CLK 27 +-#define R9A07G044_WDT2_PCLK 28 +-#define R9A07G044_WDT2_CLK 29 +-#define R9A07G044_SPI_CLK2 30 +-#define R9A07G044_SPI_CLK 31 +-#define R9A07G044_SDHI0_IMCLK 32 +-#define R9A07G044_SDHI0_IMCLK2 33 +-#define R9A07G044_SDHI0_CLK_HS 34 +-#define R9A07G044_SDHI0_ACLK 35 +-#define R9A07G044_SDHI1_IMCLK 36 +-#define R9A07G044_SDHI1_IMCLK2 37 +-#define R9A07G044_SDHI1_CLK_HS 38 +-#define R9A07G044_SDHI1_ACLK 39 +-#define R9A07G044_GPU_CLK 40 +-#define R9A07G044_GPU_AXI_CLK 41 +-#define R9A07G044_GPU_ACE_CLK 42 +-#define R9A07G044_ISU_ACLK 43 +-#define R9A07G044_ISU_PCLK 44 +-#define R9A07G044_H264_CLK_A 45 +-#define R9A07G044_H264_CLK_P 46 +-#define R9A07G044_CRU_SYSCLK 47 +-#define R9A07G044_CRU_VCLK 48 +-#define R9A07G044_CRU_PCLK 49 +-#define R9A07G044_CRU_ACLK 50 +-#define R9A07G044_MIPI_DSI_PLLCLK 51 +-#define R9A07G044_MIPI_DSI_SYSCLK 52 +-#define R9A07G044_MIPI_DSI_ACLK 53 +-#define R9A07G044_MIPI_DSI_PCLK 54 +-#define R9A07G044_MIPI_DSI_VCLK 55 +-#define R9A07G044_MIPI_DSI_LPCLK 56 +-#define R9A07G044_LCDC_CLK_A 57 +-#define R9A07G044_LCDC_CLK_P 58 +-#define R9A07G044_LCDC_CLK_D 59 +-#define R9A07G044_SSI0_PCLK2 60 +-#define R9A07G044_SSI0_PCLK_SFR 61 +-#define R9A07G044_SSI1_PCLK2 62 +-#define R9A07G044_SSI1_PCLK_SFR 63 +-#define R9A07G044_SSI2_PCLK2 64 +-#define R9A07G044_SSI2_PCLK_SFR 65 +-#define R9A07G044_SSI3_PCLK2 66 +-#define R9A07G044_SSI3_PCLK_SFR 67 +-#define R9A07G044_SRC_CLKP 68 +-#define R9A07G044_USB_U2H0_HCLK 69 +-#define R9A07G044_USB_U2H1_HCLK 70 +-#define R9A07G044_USB_U2P_EXR_CPUCLK 71 +-#define R9A07G044_USB_PCLK 72 +-#define R9A07G044_ETH0_CLK_AXI 73 +-#define R9A07G044_ETH0_CLK_CHI 74 +-#define R9A07G044_ETH1_CLK_AXI 75 +-#define R9A07G044_ETH1_CLK_CHI 76 +-#define R9A07G044_I2C0_PCLK 77 +-#define R9A07G044_I2C1_PCLK 78 +-#define R9A07G044_I2C2_PCLK 79 +-#define R9A07G044_I2C3_PCLK 80 +-#define R9A07G044_SCIF0_CLK_PCK 81 +-#define R9A07G044_SCIF1_CLK_PCK 82 +-#define R9A07G044_SCIF2_CLK_PCK 83 +-#define R9A07G044_SCIF3_CLK_PCK 84 +-#define R9A07G044_SCIF4_CLK_PCK 85 +-#define R9A07G044_SCI0_CLKP 86 +-#define R9A07G044_SCI1_CLKP 87 +-#define R9A07G044_IRDA_CLKP 88 +-#define R9A07G044_RSPI0_CLKB 89 +-#define R9A07G044_RSPI1_CLKB 90 +-#define R9A07G044_RSPI2_CLKB 91 +-#define R9A07G044_CANFD_PCLK 92 +-#define R9A07G044_GPIO_HCLK 93 +-#define R9A07G044_ADC_ADCLK 94 +-#define R9A07G044_ADC_PCLK 95 +-#define R9A07G044_TSU_PCLK 96 +- +-/* R9A07G044 Resets */ +-#define R9A07G044_CA55_RST_1_0 0 +-#define R9A07G044_CA55_RST_1_1 1 +-#define R9A07G044_CA55_RST_3_0 2 +-#define R9A07G044_CA55_RST_3_1 3 +-#define R9A07G044_CA55_RST_4 4 +-#define R9A07G044_CA55_RST_5 5 +-#define R9A07G044_CA55_RST_6 6 +-#define R9A07G044_CA55_RST_7 7 +-#define R9A07G044_CA55_RST_8 8 +-#define R9A07G044_CA55_RST_9 9 +-#define R9A07G044_CA55_RST_10 10 +-#define R9A07G044_CA55_RST_11 11 +-#define R9A07G044_CA55_RST_12 12 +-#define R9A07G044_GIC600_GICRESET_N 13 +-#define R9A07G044_GIC600_DBG_GICRESET_N 14 +-#define R9A07G044_IA55_RESETN 15 +-#define R9A07G044_MHU_RESETN 16 +-#define R9A07G044_DMAC_ARESETN 17 +-#define R9A07G044_DMAC_RST_ASYNC 18 +-#define R9A07G044_SYC_RESETN 19 +-#define R9A07G044_OSTM0_PRESETZ 20 +-#define R9A07G044_OSTM1_PRESETZ 21 +-#define R9A07G044_OSTM2_PRESETZ 22 +-#define R9A07G044_MTU_X_PRESET_MTU3 23 +-#define R9A07G044_POE3_RST_M_REG 24 +-#define R9A07G044_GPT_RST_C 25 +-#define R9A07G044_POEG_A_RST 26 +-#define R9A07G044_POEG_B_RST 27 +-#define R9A07G044_POEG_C_RST 28 +-#define R9A07G044_POEG_D_RST 29 +-#define R9A07G044_WDT0_PRESETN 30 +-#define R9A07G044_WDT1_PRESETN 31 +-#define R9A07G044_WDT2_PRESETN 32 +-#define R9A07G044_SPI_RST 33 +-#define R9A07G044_SDHI0_IXRST 34 +-#define R9A07G044_SDHI1_IXRST 35 +-#define R9A07G044_GPU_RESETN 36 +-#define R9A07G044_GPU_AXI_RESETN 37 +-#define R9A07G044_GPU_ACE_RESETN 38 +-#define R9A07G044_ISU_ARESETN 39 +-#define R9A07G044_ISU_PRESETN 40 +-#define R9A07G044_H264_X_RESET_VCP 41 +-#define R9A07G044_H264_CP_PRESET_P 42 +-#define R9A07G044_CRU_CMN_RSTB 43 +-#define R9A07G044_CRU_PRESETN 44 +-#define R9A07G044_CRU_ARESETN 45 +-#define R9A07G044_MIPI_DSI_CMN_RSTB 46 +-#define R9A07G044_MIPI_DSI_ARESET_N 47 +-#define R9A07G044_MIPI_DSI_PRESET_N 48 +-#define R9A07G044_LCDC_RESET_N 49 +-#define R9A07G044_SSI0_RST_M2_REG 50 +-#define R9A07G044_SSI1_RST_M2_REG 51 +-#define R9A07G044_SSI2_RST_M2_REG 52 +-#define R9A07G044_SSI3_RST_M2_REG 53 +-#define R9A07G044_SRC_RST 54 +-#define R9A07G044_USB_U2H0_HRESETN 55 +-#define R9A07G044_USB_U2H1_HRESETN 56 +-#define R9A07G044_USB_U2P_EXL_SYSRST 57 +-#define R9A07G044_USB_PRESETN 58 +-#define R9A07G044_ETH0_RST_HW_N 59 +-#define R9A07G044_ETH1_RST_HW_N 60 +-#define R9A07G044_I2C0_MRST 61 +-#define R9A07G044_I2C1_MRST 62 +-#define R9A07G044_I2C2_MRST 63 +-#define R9A07G044_I2C3_MRST 64 +-#define R9A07G044_SCIF0_RST_SYSTEM_N 65 +-#define R9A07G044_SCIF1_RST_SYSTEM_N 66 +-#define R9A07G044_SCIF2_RST_SYSTEM_N 67 +-#define R9A07G044_SCIF3_RST_SYSTEM_N 68 +-#define R9A07G044_SCIF4_RST_SYSTEM_N 69 +-#define R9A07G044_SCI0_RST 70 +-#define R9A07G044_SCI1_RST 71 +-#define R9A07G044_IRDA_RST 72 +-#define R9A07G044_RSPI0_RST 73 +-#define R9A07G044_RSPI1_RST 74 +-#define R9A07G044_RSPI2_RST 75 +-#define R9A07G044_CANFD_RSTP_N 76 +-#define R9A07G044_CANFD_RSTC_N 77 +-#define R9A07G044_GPIO_RSTN 78 +-#define R9A07G044_GPIO_PORT_RESETN 79 +-#define R9A07G044_GPIO_SPARE_RESETN 80 +-#define R9A07G044_ADC_PRESETN 81 +-#define R9A07G044_ADC_ADRST_N 82 +-#define R9A07G044_TSU_PRESETN 83 +- +-#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/renesas-cpg-mssr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/renesas-cpg-mssr.h +deleted file mode 100644 +index 8169ad063f0a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/renesas-cpg-mssr.h ++++ /dev/null +@@ -1,11 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ +- * +- * Copyright (C) 2015 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ +-#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ +- +-#define CPG_CORE 0 /* Core Clock */ +-#define CPG_MOD 1 /* Module Clock */ +- +-#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3036-cru.h b/scripts/dtc/include-prefixes/dt-bindings/clock/rk3036-cru.h +deleted file mode 100644 +index a96a9870ad59..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3036-cru.h ++++ /dev/null +@@ -1,187 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (c) 2015 Rockchip Electronics Co. Ltd. +- * Author: Xing Zheng +- */ +- +-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H +-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H +- +-/* core clocks */ +-#define PLL_APLL 1 +-#define PLL_DPLL 2 +-#define PLL_GPLL 3 +-#define ARMCLK 4 +- +-/* sclk gates (special clocks) */ +-#define SCLK_GPU 64 +-#define SCLK_SPI 65 +-#define SCLK_SDMMC 68 +-#define SCLK_SDIO 69 +-#define SCLK_EMMC 71 +-#define SCLK_NANDC 76 +-#define SCLK_UART0 77 +-#define SCLK_UART1 78 +-#define SCLK_UART2 79 +-#define SCLK_I2S 82 +-#define SCLK_SPDIF 83 +-#define SCLK_TIMER0 85 +-#define SCLK_TIMER1 86 +-#define SCLK_TIMER2 87 +-#define SCLK_TIMER3 88 +-#define SCLK_OTGPHY0 93 +-#define SCLK_LCDC 100 +-#define SCLK_HDMI 109 +-#define SCLK_HEVC 111 +-#define SCLK_I2S_OUT 113 +-#define SCLK_SDMMC_DRV 114 +-#define SCLK_SDIO_DRV 115 +-#define SCLK_EMMC_DRV 117 +-#define SCLK_SDMMC_SAMPLE 118 +-#define SCLK_SDIO_SAMPLE 119 +-#define SCLK_EMMC_SAMPLE 121 +-#define SCLK_PVTM_CORE 123 +-#define SCLK_PVTM_GPU 124 +-#define SCLK_PVTM_VIDEO 125 +-#define SCLK_MAC 151 +-#define SCLK_MACREF 152 +-#define SCLK_MACPLL 153 +-#define SCLK_SFC 160 +- +-/* aclk gates */ +-#define ACLK_DMAC2 194 +-#define ACLK_LCDC 197 +-#define ACLK_VIO 203 +-#define ACLK_VCODEC 208 +-#define ACLK_CPU 209 +-#define ACLK_PERI 210 +- +-/* pclk gates */ +-#define PCLK_GPIO0 320 +-#define PCLK_GPIO1 321 +-#define PCLK_GPIO2 322 +-#define PCLK_GRF 329 +-#define PCLK_I2C0 332 +-#define PCLK_I2C1 333 +-#define PCLK_I2C2 334 +-#define PCLK_SPI 338 +-#define PCLK_UART0 341 +-#define PCLK_UART1 342 +-#define PCLK_UART2 343 +-#define PCLK_PWM 350 +-#define PCLK_TIMER 353 +-#define PCLK_HDMI 360 +-#define PCLK_CPU 362 +-#define PCLK_PERI 363 +-#define PCLK_DDRUPCTL 364 +-#define PCLK_WDT 368 +-#define PCLK_ACODEC 369 +- +-/* hclk gates */ +-#define HCLK_OTG0 449 +-#define HCLK_OTG1 450 +-#define HCLK_NANDC 453 +-#define HCLK_SFC 454 +-#define HCLK_SDMMC 456 +-#define HCLK_SDIO 457 +-#define HCLK_EMMC 459 +-#define HCLK_MAC 460 +-#define HCLK_I2S 462 +-#define HCLK_LCDC 465 +-#define HCLK_ROM 467 +-#define HCLK_VIO_BUS 472 +-#define HCLK_VCODEC 476 +-#define HCLK_CPU 477 +-#define HCLK_PERI 478 +- +-#define CLK_NR_CLKS (HCLK_PERI + 1) +- +-/* soft-reset indices */ +-#define SRST_CORE0 0 +-#define SRST_CORE1 1 +-#define SRST_CORE0_DBG 4 +-#define SRST_CORE1_DBG 5 +-#define SRST_CORE0_POR 8 +-#define SRST_CORE1_POR 9 +-#define SRST_L2C 12 +-#define SRST_TOPDBG 13 +-#define SRST_STRC_SYS_A 14 +-#define SRST_PD_CORE_NIU 15 +- +-#define SRST_TIMER2 16 +-#define SRST_CPUSYS_H 17 +-#define SRST_AHB2APB_H 19 +-#define SRST_TIMER3 20 +-#define SRST_INTMEM 21 +-#define SRST_ROM 22 +-#define SRST_PERI_NIU 23 +-#define SRST_I2S 24 +-#define SRST_DDR_PLL 25 +-#define SRST_GPU_DLL 26 +-#define SRST_TIMER0 27 +-#define SRST_TIMER1 28 +-#define SRST_CORE_DLL 29 +-#define SRST_EFUSE_P 30 +-#define SRST_ACODEC_P 31 +- +-#define SRST_GPIO0 32 +-#define SRST_GPIO1 33 +-#define SRST_GPIO2 34 +-#define SRST_UART0 39 +-#define SRST_UART1 40 +-#define SRST_UART2 41 +-#define SRST_I2C0 43 +-#define SRST_I2C1 44 +-#define SRST_I2C2 45 +-#define SRST_SFC 47 +- +-#define SRST_PWM0 48 +-#define SRST_DAP 51 +-#define SRST_DAP_SYS 52 +-#define SRST_GRF 55 +-#define SRST_PERIPHSYS_A 57 +-#define SRST_PERIPHSYS_H 58 +-#define SRST_PERIPHSYS_P 59 +-#define SRST_CPU_PERI 61 +-#define SRST_EMEM_PERI 62 +-#define SRST_USB_PERI 63 +- +-#define SRST_DMA2 64 +-#define SRST_MAC 66 +-#define SRST_NANDC 68 +-#define SRST_USBOTG0 69 +-#define SRST_OTGC0 71 +-#define SRST_USBOTG1 72 +-#define SRST_OTGC1 74 +-#define SRST_DDRMSCH 79 +- +-#define SRST_MMC0 81 +-#define SRST_SDIO 82 +-#define SRST_EMMC 83 +-#define SRST_SPI0 84 +-#define SRST_WDT 86 +-#define SRST_DDRPHY 88 +-#define SRST_DDRPHY_P 89 +-#define SRST_DDRCTRL 90 +-#define SRST_DDRCTRL_P 91 +- +-#define SRST_HDMI_P 96 +-#define SRST_VIO_BUS_H 99 +-#define SRST_UTMI0 103 +-#define SRST_UTMI1 104 +-#define SRST_USBPOR 105 +- +-#define SRST_VCODEC_A 112 +-#define SRST_VCODEC_H 113 +-#define SRST_VIO1_A 114 +-#define SRST_HEVC 115 +-#define SRST_VCODEC_NIU_A 116 +-#define SRST_LCDC1_A 117 +-#define SRST_LCDC1_H 118 +-#define SRST_LCDC1_D 119 +-#define SRST_GPU 120 +-#define SRST_GPU_NIU_A 122 +- +-#define SRST_DBG_P 131 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3066a-cru.h b/scripts/dtc/include-prefixes/dt-bindings/clock/rk3066a-cru.h +deleted file mode 100644 +index 553f9728350b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3066a-cru.h ++++ /dev/null +@@ -1,31 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (c) 2014 MundoReader S.L. +- * Author: Heiko Stuebner +- */ +- +-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H +-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H +- +-#include +- +-/* soft-reset indices */ +-#define SRST_SRST1 0 +-#define SRST_SRST2 1 +- +-#define SRST_L2MEM 18 +-#define SRST_I2S0 23 +-#define SRST_I2S1 24 +-#define SRST_I2S2 25 +-#define SRST_TIMER2 29 +- +-#define SRST_GPIO4 36 +-#define SRST_GPIO6 38 +- +-#define SRST_TSADC 92 +- +-#define SRST_HDMI 96 +-#define SRST_HDMI_APB 97 +-#define SRST_CIF1 111 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3128-cru.h b/scripts/dtc/include-prefixes/dt-bindings/clock/rk3128-cru.h +deleted file mode 100644 +index 6a47825dac5d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3128-cru.h ++++ /dev/null +@@ -1,273 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (c) 2017 Rockchip Electronics Co. Ltd. +- * Author: Elaine +- */ +- +-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H +-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H +- +-/* core clocks */ +-#define PLL_APLL 1 +-#define PLL_DPLL 2 +-#define PLL_CPLL 3 +-#define PLL_GPLL 4 +-#define ARMCLK 5 +-#define PLL_GPLL_DIV2 6 +-#define PLL_GPLL_DIV3 7 +- +-/* sclk gates (special clocks) */ +-#define SCLK_SPI0 65 +-#define SCLK_NANDC 67 +-#define SCLK_SDMMC 68 +-#define SCLK_SDIO 69 +-#define SCLK_EMMC 71 +-#define SCLK_UART0 77 +-#define SCLK_UART1 78 +-#define SCLK_UART2 79 +-#define SCLK_I2S0 80 +-#define SCLK_I2S1 81 +-#define SCLK_SPDIF 83 +-#define SCLK_TIMER0 85 +-#define SCLK_TIMER1 86 +-#define SCLK_TIMER2 87 +-#define SCLK_TIMER3 88 +-#define SCLK_TIMER4 89 +-#define SCLK_TIMER5 90 +-#define SCLK_SARADC 91 +-#define SCLK_I2S_OUT 113 +-#define SCLK_SDMMC_DRV 114 +-#define SCLK_SDIO_DRV 115 +-#define SCLK_EMMC_DRV 117 +-#define SCLK_SDMMC_SAMPLE 118 +-#define SCLK_SDIO_SAMPLE 119 +-#define SCLK_EMMC_SAMPLE 121 +-#define SCLK_VOP 122 +-#define SCLK_MAC_SRC 124 +-#define SCLK_MAC 126 +-#define SCLK_MAC_REFOUT 127 +-#define SCLK_MAC_REF 128 +-#define SCLK_MAC_RX 129 +-#define SCLK_MAC_TX 130 +-#define SCLK_HEVC_CORE 134 +-#define SCLK_RGA 135 +-#define SCLK_CRYPTO 138 +-#define SCLK_TSP 139 +-#define SCLK_OTGPHY0 142 +-#define SCLK_OTGPHY1 143 +-#define SCLK_DDRC 144 +-#define SCLK_PVTM_FUNC 145 +-#define SCLK_PVTM_CORE 146 +-#define SCLK_PVTM_GPU 147 +-#define SCLK_MIPI_24M 148 +-#define SCLK_PVTM 149 +-#define SCLK_CIF_SRC 150 +-#define SCLK_CIF_OUT_SRC 151 +-#define SCLK_CIF_OUT 152 +-#define SCLK_SFC 153 +-#define SCLK_USB480M 154 +- +-/* dclk gates */ +-#define DCLK_VOP 190 +-#define DCLK_EBC 191 +- +-/* aclk gates */ +-#define ACLK_VIO0 192 +-#define ACLK_VIO1 193 +-#define ACLK_DMAC 194 +-#define ACLK_CPU 195 +-#define ACLK_VEPU 196 +-#define ACLK_VDPU 197 +-#define ACLK_CIF 198 +-#define ACLK_IEP 199 +-#define ACLK_LCDC0 204 +-#define ACLK_RGA 205 +-#define ACLK_PERI 210 +-#define ACLK_VOP 211 +-#define ACLK_GMAC 212 +-#define ACLK_GPU 213 +- +-/* pclk gates */ +-#define PCLK_SARADC 318 +-#define PCLK_WDT 319 +-#define PCLK_GPIO0 320 +-#define PCLK_GPIO1 321 +-#define PCLK_GPIO2 322 +-#define PCLK_GPIO3 323 +-#define PCLK_VIO_H2P 324 +-#define PCLK_MIPI 325 +-#define PCLK_EFUSE 326 +-#define PCLK_HDMI 327 +-#define PCLK_ACODEC 328 +-#define PCLK_GRF 329 +-#define PCLK_I2C0 332 +-#define PCLK_I2C1 333 +-#define PCLK_I2C2 334 +-#define PCLK_I2C3 335 +-#define PCLK_SPI0 338 +-#define PCLK_UART0 341 +-#define PCLK_UART1 342 +-#define PCLK_UART2 343 +-#define PCLK_TSADC 344 +-#define PCLK_PWM 350 +-#define PCLK_TIMER 353 +-#define PCLK_CPU 354 +-#define PCLK_PERI 363 +-#define PCLK_GMAC 367 +-#define PCLK_PMU_PRE 368 +-#define PCLK_SIM_CARD 369 +- +-/* hclk gates */ +-#define HCLK_SPDIF 440 +-#define HCLK_GPS 441 +-#define HCLK_USBHOST 442 +-#define HCLK_I2S_8CH 443 +-#define HCLK_I2S_2CH 444 +-#define HCLK_VOP 452 +-#define HCLK_NANDC 453 +-#define HCLK_SDMMC 456 +-#define HCLK_SDIO 457 +-#define HCLK_EMMC 459 +-#define HCLK_CPU 460 +-#define HCLK_VEPU 461 +-#define HCLK_VDPU 462 +-#define HCLK_LCDC0 463 +-#define HCLK_EBC 465 +-#define HCLK_VIO 466 +-#define HCLK_RGA 467 +-#define HCLK_IEP 468 +-#define HCLK_VIO_H2P 469 +-#define HCLK_CIF 470 +-#define HCLK_HOST2 473 +-#define HCLK_OTG 474 +-#define HCLK_TSP 475 +-#define HCLK_CRYPTO 476 +-#define HCLK_PERI 478 +- +-#define CLK_NR_CLKS (HCLK_PERI + 1) +- +-/* soft-reset indices */ +-#define SRST_CORE0_PO 0 +-#define SRST_CORE1_PO 1 +-#define SRST_CORE2_PO 2 +-#define SRST_CORE3_PO 3 +-#define SRST_CORE0 4 +-#define SRST_CORE1 5 +-#define SRST_CORE2 6 +-#define SRST_CORE3 7 +-#define SRST_CORE0_DBG 8 +-#define SRST_CORE1_DBG 9 +-#define SRST_CORE2_DBG 10 +-#define SRST_CORE3_DBG 11 +-#define SRST_TOPDBG 12 +-#define SRST_ACLK_CORE 13 +-#define SRST_STRC_SYS_A 14 +-#define SRST_L2C 15 +- +-#define SRST_CPUSYS_H 18 +-#define SRST_AHB2APBSYS_H 19 +-#define SRST_SPDIF 20 +-#define SRST_INTMEM 21 +-#define SRST_ROM 22 +-#define SRST_PERI_NIU 23 +-#define SRST_I2S_2CH 24 +-#define SRST_I2S_8CH 25 +-#define SRST_GPU_PVTM 26 +-#define SRST_FUNC_PVTM 27 +-#define SRST_CORE_PVTM 29 +-#define SRST_EFUSE_P 30 +-#define SRST_ACODEC_P 31 +- +-#define SRST_GPIO0 32 +-#define SRST_GPIO1 33 +-#define SRST_GPIO2 34 +-#define SRST_GPIO3 35 +-#define SRST_MIPIPHY_P 36 +-#define SRST_UART0 39 +-#define SRST_UART1 40 +-#define SRST_UART2 41 +-#define SRST_I2C0 43 +-#define SRST_I2C1 44 +-#define SRST_I2C2 45 +-#define SRST_I2C3 46 +-#define SRST_SFC 47 +- +-#define SRST_PWM 48 +-#define SRST_DAP_PO 50 +-#define SRST_DAP 51 +-#define SRST_DAP_SYS 52 +-#define SRST_CRYPTO 53 +-#define SRST_GRF 55 +-#define SRST_GMAC 56 +-#define SRST_PERIPH_SYS_A 57 +-#define SRST_PERIPH_SYS_H 58 +-#define SRST_PERIPH_SYS_P 59 +-#define SRST_SMART_CARD 60 +-#define SRST_CPU_PERI 61 +-#define SRST_EMEM_PERI 62 +-#define SRST_USB_PERI 63 +- +-#define SRST_DMA 64 +-#define SRST_GPS 67 +-#define SRST_NANDC 68 +-#define SRST_USBOTG0 69 +-#define SRST_OTGC0 71 +-#define SRST_USBOTG1 72 +-#define SRST_OTGC1 74 +-#define SRST_DDRMSCH 79 +- +-#define SRST_SDMMC 81 +-#define SRST_SDIO 82 +-#define SRST_EMMC 83 +-#define SRST_SPI 84 +-#define SRST_WDT 86 +-#define SRST_SARADC 87 +-#define SRST_DDRPHY 88 +-#define SRST_DDRPHY_P 89 +-#define SRST_DDRCTRL 90 +-#define SRST_DDRCTRL_P 91 +-#define SRST_TSP 92 +-#define SRST_TSP_CLKIN 93 +-#define SRST_HOST0_ECHI 94 +- +-#define SRST_HDMI_P 96 +-#define SRST_VIO_ARBI_H 97 +-#define SRST_VIO0_A 98 +-#define SRST_VIO_BUS_H 99 +-#define SRST_VOP_A 100 +-#define SRST_VOP_H 101 +-#define SRST_VOP_D 102 +-#define SRST_UTMI0 103 +-#define SRST_UTMI1 104 +-#define SRST_USBPOR 105 +-#define SRST_IEP_A 106 +-#define SRST_IEP_H 107 +-#define SRST_RGA_A 108 +-#define SRST_RGA_H 109 +-#define SRST_CIF0 110 +-#define SRST_PMU 111 +- +-#define SRST_VCODEC_A 112 +-#define SRST_VCODEC_H 113 +-#define SRST_VIO1_A 114 +-#define SRST_HEVC_CORE 115 +-#define SRST_VCODEC_NIU_A 116 +-#define SRST_PMU_NIU_P 117 +-#define SRST_LCDC0_S 119 +-#define SRST_GPU 120 +-#define SRST_GPU_NIU_A 122 +-#define SRST_EBC_A 123 +-#define SRST_EBC_H 124 +- +-#define SRST_CORE_DBG 128 +-#define SRST_DBG_P 129 +-#define SRST_TIMER0 130 +-#define SRST_TIMER1 131 +-#define SRST_TIMER2 132 +-#define SRST_TIMER3 133 +-#define SRST_TIMER4 134 +-#define SRST_TIMER5 135 +-#define SRST_VIO_H2P 136 +-#define SRST_VIO_MIPI_DSI 137 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3188-cru-common.h b/scripts/dtc/include-prefixes/dt-bindings/clock/rk3188-cru-common.h +deleted file mode 100644 +index afad90680fce..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3188-cru-common.h ++++ /dev/null +@@ -1,261 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (c) 2014 MundoReader S.L. +- * Author: Heiko Stuebner +- */ +- +-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H +-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H +- +-/* core clocks from */ +-#define PLL_APLL 1 +-#define PLL_DPLL 2 +-#define PLL_CPLL 3 +-#define PLL_GPLL 4 +-#define CORE_PERI 5 +-#define CORE_L2C 6 +-#define ARMCLK 7 +- +-/* sclk gates (special clocks) */ +-#define SCLK_UART0 64 +-#define SCLK_UART1 65 +-#define SCLK_UART2 66 +-#define SCLK_UART3 67 +-#define SCLK_MAC 68 +-#define SCLK_SPI0 69 +-#define SCLK_SPI1 70 +-#define SCLK_SARADC 71 +-#define SCLK_SDMMC 72 +-#define SCLK_SDIO 73 +-#define SCLK_EMMC 74 +-#define SCLK_I2S0 75 +-#define SCLK_I2S1 76 +-#define SCLK_I2S2 77 +-#define SCLK_SPDIF 78 +-#define SCLK_CIF0 79 +-#define SCLK_CIF1 80 +-#define SCLK_OTGPHY0 81 +-#define SCLK_OTGPHY1 82 +-#define SCLK_HSADC 83 +-#define SCLK_TIMER0 84 +-#define SCLK_TIMER1 85 +-#define SCLK_TIMER2 86 +-#define SCLK_TIMER3 87 +-#define SCLK_TIMER4 88 +-#define SCLK_TIMER5 89 +-#define SCLK_TIMER6 90 +-#define SCLK_JTAG 91 +-#define SCLK_SMC 92 +-#define SCLK_TSADC 93 +- +-#define DCLK_LCDC0 190 +-#define DCLK_LCDC1 191 +- +-/* aclk gates */ +-#define ACLK_DMA1 192 +-#define ACLK_DMA2 193 +-#define ACLK_GPS 194 +-#define ACLK_LCDC0 195 +-#define ACLK_LCDC1 196 +-#define ACLK_GPU 197 +-#define ACLK_SMC 198 +-#define ACLK_CIF1 199 +-#define ACLK_IPP 200 +-#define ACLK_RGA 201 +-#define ACLK_CIF0 202 +-#define ACLK_CPU 203 +-#define ACLK_PERI 204 +-#define ACLK_VEPU 205 +-#define ACLK_VDPU 206 +- +-/* pclk gates */ +-#define PCLK_GRF 320 +-#define PCLK_PMU 321 +-#define PCLK_TIMER0 322 +-#define PCLK_TIMER1 323 +-#define PCLK_TIMER2 324 +-#define PCLK_TIMER3 325 +-#define PCLK_PWM01 326 +-#define PCLK_PWM23 327 +-#define PCLK_SPI0 328 +-#define PCLK_SPI1 329 +-#define PCLK_SARADC 330 +-#define PCLK_WDT 331 +-#define PCLK_UART0 332 +-#define PCLK_UART1 333 +-#define PCLK_UART2 334 +-#define PCLK_UART3 335 +-#define PCLK_I2C0 336 +-#define PCLK_I2C1 337 +-#define PCLK_I2C2 338 +-#define PCLK_I2C3 339 +-#define PCLK_I2C4 340 +-#define PCLK_GPIO0 341 +-#define PCLK_GPIO1 342 +-#define PCLK_GPIO2 343 +-#define PCLK_GPIO3 344 +-#define PCLK_GPIO4 345 +-#define PCLK_GPIO6 346 +-#define PCLK_EFUSE 347 +-#define PCLK_TZPC 348 +-#define PCLK_TSADC 349 +-#define PCLK_CPU 350 +-#define PCLK_PERI 351 +-#define PCLK_DDRUPCTL 352 +-#define PCLK_PUBL 353 +- +-/* hclk gates */ +-#define HCLK_SDMMC 448 +-#define HCLK_SDIO 449 +-#define HCLK_EMMC 450 +-#define HCLK_OTG0 451 +-#define HCLK_EMAC 452 +-#define HCLK_SPDIF 453 +-#define HCLK_I2S0 454 +-#define HCLK_I2S1 455 +-#define HCLK_I2S2 456 +-#define HCLK_OTG1 457 +-#define HCLK_HSIC 458 +-#define HCLK_HSADC 459 +-#define HCLK_PIDF 460 +-#define HCLK_LCDC0 461 +-#define HCLK_LCDC1 462 +-#define HCLK_ROM 463 +-#define HCLK_CIF0 464 +-#define HCLK_IPP 465 +-#define HCLK_RGA 466 +-#define HCLK_NANDC0 467 +-#define HCLK_CPU 468 +-#define HCLK_PERI 469 +-#define HCLK_CIF1 470 +-#define HCLK_VEPU 471 +-#define HCLK_VDPU 472 +-#define HCLK_HDMI 473 +- +-#define CLK_NR_CLKS (HCLK_HDMI + 1) +- +-/* soft-reset indices */ +-#define SRST_MCORE 2 +-#define SRST_CORE0 3 +-#define SRST_CORE1 4 +-#define SRST_MCORE_DBG 7 +-#define SRST_CORE0_DBG 8 +-#define SRST_CORE1_DBG 9 +-#define SRST_CORE0_WDT 12 +-#define SRST_CORE1_WDT 13 +-#define SRST_STRC_SYS 14 +-#define SRST_L2C 15 +- +-#define SRST_CPU_AHB 17 +-#define SRST_AHB2APB 19 +-#define SRST_DMA1 20 +-#define SRST_INTMEM 21 +-#define SRST_ROM 22 +-#define SRST_SPDIF 26 +-#define SRST_TIMER0 27 +-#define SRST_TIMER1 28 +-#define SRST_EFUSE 30 +- +-#define SRST_GPIO0 32 +-#define SRST_GPIO1 33 +-#define SRST_GPIO2 34 +-#define SRST_GPIO3 35 +- +-#define SRST_UART0 39 +-#define SRST_UART1 40 +-#define SRST_UART2 41 +-#define SRST_UART3 42 +-#define SRST_I2C0 43 +-#define SRST_I2C1 44 +-#define SRST_I2C2 45 +-#define SRST_I2C3 46 +-#define SRST_I2C4 47 +- +-#define SRST_PWM0 48 +-#define SRST_PWM1 49 +-#define SRST_DAP_PO 50 +-#define SRST_DAP 51 +-#define SRST_DAP_SYS 52 +-#define SRST_TPIU_ATB 53 +-#define SRST_PMU_APB 54 +-#define SRST_GRF 55 +-#define SRST_PMU 56 +-#define SRST_PERI_AXI 57 +-#define SRST_PERI_AHB 58 +-#define SRST_PERI_APB 59 +-#define SRST_PERI_NIU 60 +-#define SRST_CPU_PERI 61 +-#define SRST_EMEM_PERI 62 +-#define SRST_USB_PERI 63 +- +-#define SRST_DMA2 64 +-#define SRST_SMC 65 +-#define SRST_MAC 66 +-#define SRST_NANC0 68 +-#define SRST_USBOTG0 69 +-#define SRST_USBPHY0 70 +-#define SRST_OTGC0 71 +-#define SRST_USBOTG1 72 +-#define SRST_USBPHY1 73 +-#define SRST_OTGC1 74 +-#define SRST_HSADC 76 +-#define SRST_PIDFILTER 77 +-#define SRST_DDR_MSCH 79 +- +-#define SRST_TZPC 80 +-#define SRST_SDMMC 81 +-#define SRST_SDIO 82 +-#define SRST_EMMC 83 +-#define SRST_SPI0 84 +-#define SRST_SPI1 85 +-#define SRST_WDT 86 +-#define SRST_SARADC 87 +-#define SRST_DDRPHY 88 +-#define SRST_DDRPHY_APB 89 +-#define SRST_DDRCTL 90 +-#define SRST_DDRCTL_APB 91 +-#define SRST_DDRPUB 93 +- +-#define SRST_VIO0_AXI 98 +-#define SRST_VIO0_AHB 99 +-#define SRST_LCDC0_AXI 100 +-#define SRST_LCDC0_AHB 101 +-#define SRST_LCDC0_DCLK 102 +-#define SRST_LCDC1_AXI 103 +-#define SRST_LCDC1_AHB 104 +-#define SRST_LCDC1_DCLK 105 +-#define SRST_IPP_AXI 106 +-#define SRST_IPP_AHB 107 +-#define SRST_RGA_AXI 108 +-#define SRST_RGA_AHB 109 +-#define SRST_CIF0 110 +- +-#define SRST_VCODEC_AXI 112 +-#define SRST_VCODEC_AHB 113 +-#define SRST_VIO1_AXI 114 +-#define SRST_VCODEC_CPU 115 +-#define SRST_VCODEC_NIU 116 +-#define SRST_GPU 120 +-#define SRST_GPU_NIU 122 +-#define SRST_TFUN_ATB 125 +-#define SRST_TFUN_APB 126 +-#define SRST_CTI4_APB 127 +- +-#define SRST_TPIU_APB 128 +-#define SRST_TRACE 129 +-#define SRST_CORE_DBG 130 +-#define SRST_DBG_APB 131 +-#define SRST_CTI0 132 +-#define SRST_CTI0_APB 133 +-#define SRST_CTI1 134 +-#define SRST_CTI1_APB 135 +-#define SRST_PTM_CORE0 136 +-#define SRST_PTM_CORE1 137 +-#define SRST_PTM0 138 +-#define SRST_PTM0_ATB 139 +-#define SRST_PTM1 140 +-#define SRST_PTM1_ATB 141 +-#define SRST_CTM 142 +-#define SRST_TS 143 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3188-cru.h b/scripts/dtc/include-prefixes/dt-bindings/clock/rk3188-cru.h +deleted file mode 100644 +index c45916ae6878..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3188-cru.h ++++ /dev/null +@@ -1,47 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (c) 2014 MundoReader S.L. +- * Author: Heiko Stuebner +- */ +- +-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H +-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H +- +-#include +- +-/* soft-reset indices */ +-#define SRST_PTM_CORE2 0 +-#define SRST_PTM_CORE3 1 +-#define SRST_CORE2 5 +-#define SRST_CORE3 6 +-#define SRST_CORE2_DBG 10 +-#define SRST_CORE3_DBG 11 +- +-#define SRST_TIMER2 16 +-#define SRST_TIMER4 23 +-#define SRST_I2S0 24 +-#define SRST_TIMER5 25 +-#define SRST_TIMER3 29 +-#define SRST_TIMER6 31 +- +-#define SRST_PTM3 36 +-#define SRST_PTM3_ATB 37 +- +-#define SRST_GPS 67 +-#define SRST_HSICPHY 75 +-#define SRST_TIMER 78 +- +-#define SRST_PTM2 92 +-#define SRST_CORE2_WDT 94 +-#define SRST_CORE3_WDT 95 +- +-#define SRST_PTM2_ATB 111 +- +-#define SRST_HSIC 117 +-#define SRST_CTI2 118 +-#define SRST_CTI2_APB 119 +-#define SRST_GPU_BRIDGE 121 +-#define SRST_CTI3 123 +-#define SRST_CTI3_APB 124 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3228-cru.h b/scripts/dtc/include-prefixes/dt-bindings/clock/rk3228-cru.h +deleted file mode 100644 +index de550ea56eeb..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3228-cru.h ++++ /dev/null +@@ -1,287 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (c) 2015 Rockchip Electronics Co. Ltd. +- * Author: Jeffy Chen +- */ +- +-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H +-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H +- +-/* core clocks */ +-#define PLL_APLL 1 +-#define PLL_DPLL 2 +-#define PLL_CPLL 3 +-#define PLL_GPLL 4 +-#define ARMCLK 5 +- +-/* sclk gates (special clocks) */ +-#define SCLK_SPI0 65 +-#define SCLK_NANDC 67 +-#define SCLK_SDMMC 68 +-#define SCLK_SDIO 69 +-#define SCLK_EMMC 71 +-#define SCLK_TSADC 72 +-#define SCLK_UART0 77 +-#define SCLK_UART1 78 +-#define SCLK_UART2 79 +-#define SCLK_I2S0 80 +-#define SCLK_I2S1 81 +-#define SCLK_I2S2 82 +-#define SCLK_SPDIF 83 +-#define SCLK_TIMER0 85 +-#define SCLK_TIMER1 86 +-#define SCLK_TIMER2 87 +-#define SCLK_TIMER3 88 +-#define SCLK_TIMER4 89 +-#define SCLK_TIMER5 90 +-#define SCLK_I2S_OUT 113 +-#define SCLK_SDMMC_DRV 114 +-#define SCLK_SDIO_DRV 115 +-#define SCLK_EMMC_DRV 117 +-#define SCLK_SDMMC_SAMPLE 118 +-#define SCLK_SDIO_SAMPLE 119 +-#define SCLK_SDIO_SRC 120 +-#define SCLK_EMMC_SAMPLE 121 +-#define SCLK_VOP 122 +-#define SCLK_HDMI_HDCP 123 +-#define SCLK_MAC_SRC 124 +-#define SCLK_MAC_EXTCLK 125 +-#define SCLK_MAC 126 +-#define SCLK_MAC_REFOUT 127 +-#define SCLK_MAC_REF 128 +-#define SCLK_MAC_RX 129 +-#define SCLK_MAC_TX 130 +-#define SCLK_MAC_PHY 131 +-#define SCLK_MAC_OUT 132 +-#define SCLK_VDEC_CABAC 133 +-#define SCLK_VDEC_CORE 134 +-#define SCLK_RGA 135 +-#define SCLK_HDCP 136 +-#define SCLK_HDMI_CEC 137 +-#define SCLK_CRYPTO 138 +-#define SCLK_TSP 139 +-#define SCLK_HSADC 140 +-#define SCLK_WIFI 141 +-#define SCLK_OTGPHY0 142 +-#define SCLK_OTGPHY1 143 +-#define SCLK_HDMI_PHY 144 +- +-/* dclk gates */ +-#define DCLK_VOP 190 +-#define DCLK_HDMI_PHY 191 +- +-/* aclk gates */ +-#define ACLK_DMAC 194 +-#define ACLK_CPU 195 +-#define ACLK_VPU_PRE 196 +-#define ACLK_RKVDEC_PRE 197 +-#define ACLK_RGA_PRE 198 +-#define ACLK_IEP_PRE 199 +-#define ACLK_HDCP_PRE 200 +-#define ACLK_VOP_PRE 201 +-#define ACLK_VPU 202 +-#define ACLK_RKVDEC 203 +-#define ACLK_IEP 204 +-#define ACLK_RGA 205 +-#define ACLK_HDCP 206 +-#define ACLK_PERI 210 +-#define ACLK_VOP 211 +-#define ACLK_GMAC 212 +-#define ACLK_GPU 213 +- +-/* pclk gates */ +-#define PCLK_GPIO0 320 +-#define PCLK_GPIO1 321 +-#define PCLK_GPIO2 322 +-#define PCLK_GPIO3 323 +-#define PCLK_VIO_H2P 324 +-#define PCLK_HDCP 325 +-#define PCLK_EFUSE_1024 326 +-#define PCLK_EFUSE_256 327 +-#define PCLK_GRF 329 +-#define PCLK_I2C0 332 +-#define PCLK_I2C1 333 +-#define PCLK_I2C2 334 +-#define PCLK_I2C3 335 +-#define PCLK_SPI0 338 +-#define PCLK_UART0 341 +-#define PCLK_UART1 342 +-#define PCLK_UART2 343 +-#define PCLK_TSADC 344 +-#define PCLK_PWM 350 +-#define PCLK_TIMER 353 +-#define PCLK_CPU 354 +-#define PCLK_PERI 363 +-#define PCLK_HDMI_CTRL 364 +-#define PCLK_HDMI_PHY 365 +-#define PCLK_GMAC 367 +- +-/* hclk gates */ +-#define HCLK_I2S0_8CH 442 +-#define HCLK_I2S1_8CH 443 +-#define HCLK_I2S2_2CH 444 +-#define HCLK_SPDIF_8CH 445 +-#define HCLK_VOP 452 +-#define HCLK_NANDC 453 +-#define HCLK_SDMMC 456 +-#define HCLK_SDIO 457 +-#define HCLK_EMMC 459 +-#define HCLK_CPU 460 +-#define HCLK_VPU_PRE 461 +-#define HCLK_RKVDEC_PRE 462 +-#define HCLK_VIO_PRE 463 +-#define HCLK_VPU 464 +-#define HCLK_RKVDEC 465 +-#define HCLK_VIO 466 +-#define HCLK_RGA 467 +-#define HCLK_IEP 468 +-#define HCLK_VIO_H2P 469 +-#define HCLK_HDCP_MMU 470 +-#define HCLK_HOST0 471 +-#define HCLK_HOST1 472 +-#define HCLK_HOST2 473 +-#define HCLK_OTG 474 +-#define HCLK_TSP 475 +-#define HCLK_M_CRYPTO 476 +-#define HCLK_S_CRYPTO 477 +-#define HCLK_PERI 478 +- +-#define CLK_NR_CLKS (HCLK_PERI + 1) +- +-/* soft-reset indices */ +-#define SRST_CORE0_PO 0 +-#define SRST_CORE1_PO 1 +-#define SRST_CORE2_PO 2 +-#define SRST_CORE3_PO 3 +-#define SRST_CORE0 4 +-#define SRST_CORE1 5 +-#define SRST_CORE2 6 +-#define SRST_CORE3 7 +-#define SRST_CORE0_DBG 8 +-#define SRST_CORE1_DBG 9 +-#define SRST_CORE2_DBG 10 +-#define SRST_CORE3_DBG 11 +-#define SRST_TOPDBG 12 +-#define SRST_ACLK_CORE 13 +-#define SRST_NOC 14 +-#define SRST_L2C 15 +- +-#define SRST_CPUSYS_H 18 +-#define SRST_BUSSYS_H 19 +-#define SRST_SPDIF 20 +-#define SRST_INTMEM 21 +-#define SRST_ROM 22 +-#define SRST_OTG_ADP 23 +-#define SRST_I2S0 24 +-#define SRST_I2S1 25 +-#define SRST_I2S2 26 +-#define SRST_ACODEC_P 27 +-#define SRST_DFIMON 28 +-#define SRST_MSCH 29 +-#define SRST_EFUSE1024 30 +-#define SRST_EFUSE256 31 +- +-#define SRST_GPIO0 32 +-#define SRST_GPIO1 33 +-#define SRST_GPIO2 34 +-#define SRST_GPIO3 35 +-#define SRST_PERIPH_NOC_A 36 +-#define SRST_PERIPH_NOC_BUS_H 37 +-#define SRST_PERIPH_NOC_P 38 +-#define SRST_UART0 39 +-#define SRST_UART1 40 +-#define SRST_UART2 41 +-#define SRST_PHYNOC 42 +-#define SRST_I2C0 43 +-#define SRST_I2C1 44 +-#define SRST_I2C2 45 +-#define SRST_I2C3 46 +- +-#define SRST_PWM 48 +-#define SRST_A53_GIC 49 +-#define SRST_DAP 51 +-#define SRST_DAP_NOC 52 +-#define SRST_CRYPTO 53 +-#define SRST_SGRF 54 +-#define SRST_GRF 55 +-#define SRST_GMAC 56 +-#define SRST_PERIPH_NOC_H 58 +-#define SRST_MACPHY 63 +- +-#define SRST_DMA 64 +-#define SRST_NANDC 68 +-#define SRST_USBOTG 69 +-#define SRST_OTGC 70 +-#define SRST_USBHOST0 71 +-#define SRST_HOST_CTRL0 72 +-#define SRST_USBHOST1 73 +-#define SRST_HOST_CTRL1 74 +-#define SRST_USBHOST2 75 +-#define SRST_HOST_CTRL2 76 +-#define SRST_USBPOR0 77 +-#define SRST_USBPOR1 78 +-#define SRST_DDRMSCH 79 +- +-#define SRST_SMART_CARD 80 +-#define SRST_SDMMC 81 +-#define SRST_SDIO 82 +-#define SRST_EMMC 83 +-#define SRST_SPI 84 +-#define SRST_TSP_H 85 +-#define SRST_TSP 86 +-#define SRST_TSADC 87 +-#define SRST_DDRPHY 88 +-#define SRST_DDRPHY_P 89 +-#define SRST_DDRCTRL 90 +-#define SRST_DDRCTRL_P 91 +-#define SRST_HOST0_ECHI 92 +-#define SRST_HOST1_ECHI 93 +-#define SRST_HOST2_ECHI 94 +-#define SRST_VOP_NOC_A 95 +- +-#define SRST_HDMI_P 96 +-#define SRST_VIO_ARBI_H 97 +-#define SRST_IEP_NOC_A 98 +-#define SRST_VIO_NOC_H 99 +-#define SRST_VOP_A 100 +-#define SRST_VOP_H 101 +-#define SRST_VOP_D 102 +-#define SRST_UTMI0 103 +-#define SRST_UTMI1 104 +-#define SRST_UTMI2 105 +-#define SRST_UTMI3 106 +-#define SRST_RGA 107 +-#define SRST_RGA_NOC_A 108 +-#define SRST_RGA_A 109 +-#define SRST_RGA_H 110 +-#define SRST_HDCP_A 111 +- +-#define SRST_VPU_A 112 +-#define SRST_VPU_H 113 +-#define SRST_VPU_NOC_A 116 +-#define SRST_VPU_NOC_H 117 +-#define SRST_RKVDEC_A 118 +-#define SRST_RKVDEC_NOC_A 119 +-#define SRST_RKVDEC_H 120 +-#define SRST_RKVDEC_NOC_H 121 +-#define SRST_RKVDEC_CORE 122 +-#define SRST_RKVDEC_CABAC 123 +-#define SRST_IEP_A 124 +-#define SRST_IEP_H 125 +-#define SRST_GPU_A 126 +-#define SRST_GPU_NOC_A 127 +- +-#define SRST_CORE_DBG 128 +-#define SRST_DBG_P 129 +-#define SRST_TIMER0 130 +-#define SRST_TIMER1 131 +-#define SRST_TIMER2 132 +-#define SRST_TIMER3 133 +-#define SRST_TIMER4 134 +-#define SRST_TIMER5 135 +-#define SRST_VIO_H2P 136 +-#define SRST_HDMIPHY 139 +-#define SRST_VDAC 140 +-#define SRST_TIMER_6CH_P 141 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3288-cru.h b/scripts/dtc/include-prefixes/dt-bindings/clock/rk3288-cru.h +deleted file mode 100644 +index 33819acbfc56..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3288-cru.h ++++ /dev/null +@@ -1,380 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (c) 2014 MundoReader S.L. +- * Author: Heiko Stuebner +- */ +- +-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H +-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H +- +-/* core clocks */ +-#define PLL_APLL 1 +-#define PLL_DPLL 2 +-#define PLL_CPLL 3 +-#define PLL_GPLL 4 +-#define PLL_NPLL 5 +-#define ARMCLK 6 +- +-/* sclk gates (special clocks) */ +-#define SCLK_GPU 64 +-#define SCLK_SPI0 65 +-#define SCLK_SPI1 66 +-#define SCLK_SPI2 67 +-#define SCLK_SDMMC 68 +-#define SCLK_SDIO0 69 +-#define SCLK_SDIO1 70 +-#define SCLK_EMMC 71 +-#define SCLK_TSADC 72 +-#define SCLK_SARADC 73 +-#define SCLK_PS2C 74 +-#define SCLK_NANDC0 75 +-#define SCLK_NANDC1 76 +-#define SCLK_UART0 77 +-#define SCLK_UART1 78 +-#define SCLK_UART2 79 +-#define SCLK_UART3 80 +-#define SCLK_UART4 81 +-#define SCLK_I2S0 82 +-#define SCLK_SPDIF 83 +-#define SCLK_SPDIF8CH 84 +-#define SCLK_TIMER0 85 +-#define SCLK_TIMER1 86 +-#define SCLK_TIMER2 87 +-#define SCLK_TIMER3 88 +-#define SCLK_TIMER4 89 +-#define SCLK_TIMER5 90 +-#define SCLK_TIMER6 91 +-#define SCLK_HSADC 92 +-#define SCLK_OTGPHY0 93 +-#define SCLK_OTGPHY1 94 +-#define SCLK_OTGPHY2 95 +-#define SCLK_OTG_ADP 96 +-#define SCLK_HSICPHY480M 97 +-#define SCLK_HSICPHY12M 98 +-#define SCLK_MACREF 99 +-#define SCLK_LCDC_PWM0 100 +-#define SCLK_LCDC_PWM1 101 +-#define SCLK_MAC_RX 102 +-#define SCLK_MAC_TX 103 +-#define SCLK_EDP_24M 104 +-#define SCLK_EDP 105 +-#define SCLK_RGA 106 +-#define SCLK_ISP 107 +-#define SCLK_ISP_JPE 108 +-#define SCLK_HDMI_HDCP 109 +-#define SCLK_HDMI_CEC 110 +-#define SCLK_HEVC_CABAC 111 +-#define SCLK_HEVC_CORE 112 +-#define SCLK_I2S0_OUT 113 +-#define SCLK_SDMMC_DRV 114 +-#define SCLK_SDIO0_DRV 115 +-#define SCLK_SDIO1_DRV 116 +-#define SCLK_EMMC_DRV 117 +-#define SCLK_SDMMC_SAMPLE 118 +-#define SCLK_SDIO0_SAMPLE 119 +-#define SCLK_SDIO1_SAMPLE 120 +-#define SCLK_EMMC_SAMPLE 121 +-#define SCLK_USBPHY480M_SRC 122 +-#define SCLK_PVTM_CORE 123 +-#define SCLK_PVTM_GPU 124 +-#define SCLK_CRYPTO 125 +-#define SCLK_MIPIDSI_24M 126 +-#define SCLK_VIP_OUT 127 +- +-#define SCLK_MAC 151 +-#define SCLK_MACREF_OUT 152 +- +-#define DCLK_VOP0 190 +-#define DCLK_VOP1 191 +- +-/* aclk gates */ +-#define ACLK_GPU 192 +-#define ACLK_DMAC1 193 +-#define ACLK_DMAC2 194 +-#define ACLK_MMU 195 +-#define ACLK_GMAC 196 +-#define ACLK_VOP0 197 +-#define ACLK_VOP1 198 +-#define ACLK_CRYPTO 199 +-#define ACLK_RGA 200 +-#define ACLK_RGA_NIU 201 +-#define ACLK_IEP 202 +-#define ACLK_VIO0_NIU 203 +-#define ACLK_VIP 204 +-#define ACLK_ISP 205 +-#define ACLK_VIO1_NIU 206 +-#define ACLK_HEVC 207 +-#define ACLK_VCODEC 208 +-#define ACLK_CPU 209 +-#define ACLK_PERI 210 +- +-/* pclk gates */ +-#define PCLK_GPIO0 320 +-#define PCLK_GPIO1 321 +-#define PCLK_GPIO2 322 +-#define PCLK_GPIO3 323 +-#define PCLK_GPIO4 324 +-#define PCLK_GPIO5 325 +-#define PCLK_GPIO6 326 +-#define PCLK_GPIO7 327 +-#define PCLK_GPIO8 328 +-#define PCLK_GRF 329 +-#define PCLK_SGRF 330 +-#define PCLK_PMU 331 +-#define PCLK_I2C0 332 +-#define PCLK_I2C1 333 +-#define PCLK_I2C2 334 +-#define PCLK_I2C3 335 +-#define PCLK_I2C4 336 +-#define PCLK_I2C5 337 +-#define PCLK_SPI0 338 +-#define PCLK_SPI1 339 +-#define PCLK_SPI2 340 +-#define PCLK_UART0 341 +-#define PCLK_UART1 342 +-#define PCLK_UART2 343 +-#define PCLK_UART3 344 +-#define PCLK_UART4 345 +-#define PCLK_TSADC 346 +-#define PCLK_SARADC 347 +-#define PCLK_SIM 348 +-#define PCLK_GMAC 349 +-#define PCLK_PWM 350 +-#define PCLK_RKPWM 351 +-#define PCLK_PS2C 352 +-#define PCLK_TIMER 353 +-#define PCLK_TZPC 354 +-#define PCLK_EDP_CTRL 355 +-#define PCLK_MIPI_DSI0 356 +-#define PCLK_MIPI_DSI1 357 +-#define PCLK_MIPI_CSI 358 +-#define PCLK_LVDS_PHY 359 +-#define PCLK_HDMI_CTRL 360 +-#define PCLK_VIO2_H2P 361 +-#define PCLK_CPU 362 +-#define PCLK_PERI 363 +-#define PCLK_DDRUPCTL0 364 +-#define PCLK_PUBL0 365 +-#define PCLK_DDRUPCTL1 366 +-#define PCLK_PUBL1 367 +-#define PCLK_WDT 368 +-#define PCLK_EFUSE256 369 +-#define PCLK_EFUSE1024 370 +-#define PCLK_ISP_IN 371 +- +-/* hclk gates */ +-#define HCLK_GPS 448 +-#define HCLK_OTG0 449 +-#define HCLK_USBHOST0 450 +-#define HCLK_USBHOST1 451 +-#define HCLK_HSIC 452 +-#define HCLK_NANDC0 453 +-#define HCLK_NANDC1 454 +-#define HCLK_TSP 455 +-#define HCLK_SDMMC 456 +-#define HCLK_SDIO0 457 +-#define HCLK_SDIO1 458 +-#define HCLK_EMMC 459 +-#define HCLK_HSADC 460 +-#define HCLK_CRYPTO 461 +-#define HCLK_I2S0 462 +-#define HCLK_SPDIF 463 +-#define HCLK_SPDIF8CH 464 +-#define HCLK_VOP0 465 +-#define HCLK_VOP1 466 +-#define HCLK_ROM 467 +-#define HCLK_IEP 468 +-#define HCLK_ISP 469 +-#define HCLK_RGA 470 +-#define HCLK_VIO_AHB_ARBI 471 +-#define HCLK_VIO_NIU 472 +-#define HCLK_VIP 473 +-#define HCLK_VIO2_H2P 474 +-#define HCLK_HEVC 475 +-#define HCLK_VCODEC 476 +-#define HCLK_CPU 477 +-#define HCLK_PERI 478 +- +-#define CLK_NR_CLKS (HCLK_PERI + 1) +- +-/* soft-reset indices */ +-#define SRST_CORE0 0 +-#define SRST_CORE1 1 +-#define SRST_CORE2 2 +-#define SRST_CORE3 3 +-#define SRST_CORE0_PO 4 +-#define SRST_CORE1_PO 5 +-#define SRST_CORE2_PO 6 +-#define SRST_CORE3_PO 7 +-#define SRST_PDCORE_STRSYS 8 +-#define SRST_PDBUS_STRSYS 9 +-#define SRST_L2C 10 +-#define SRST_TOPDBG 11 +-#define SRST_CORE0_DBG 12 +-#define SRST_CORE1_DBG 13 +-#define SRST_CORE2_DBG 14 +-#define SRST_CORE3_DBG 15 +- +-#define SRST_PDBUG_AHB_ARBITOR 16 +-#define SRST_EFUSE256 17 +-#define SRST_DMAC1 18 +-#define SRST_INTMEM 19 +-#define SRST_ROM 20 +-#define SRST_SPDIF8CH 21 +-#define SRST_TIMER 22 +-#define SRST_I2S0 23 +-#define SRST_SPDIF 24 +-#define SRST_TIMER0 25 +-#define SRST_TIMER1 26 +-#define SRST_TIMER2 27 +-#define SRST_TIMER3 28 +-#define SRST_TIMER4 29 +-#define SRST_TIMER5 30 +-#define SRST_EFUSE 31 +- +-#define SRST_GPIO0 32 +-#define SRST_GPIO1 33 +-#define SRST_GPIO2 34 +-#define SRST_GPIO3 35 +-#define SRST_GPIO4 36 +-#define SRST_GPIO5 37 +-#define SRST_GPIO6 38 +-#define SRST_GPIO7 39 +-#define SRST_GPIO8 40 +-#define SRST_I2C0 42 +-#define SRST_I2C1 43 +-#define SRST_I2C2 44 +-#define SRST_I2C3 45 +-#define SRST_I2C4 46 +-#define SRST_I2C5 47 +- +-#define SRST_DWPWM 48 +-#define SRST_MMC_PERI 49 +-#define SRST_PERIPH_MMU 50 +-#define SRST_DAP 51 +-#define SRST_DAP_SYS 52 +-#define SRST_TPIU 53 +-#define SRST_PMU_APB 54 +-#define SRST_GRF 55 +-#define SRST_PMU 56 +-#define SRST_PERIPH_AXI 57 +-#define SRST_PERIPH_AHB 58 +-#define SRST_PERIPH_APB 59 +-#define SRST_PERIPH_NIU 60 +-#define SRST_PDPERI_AHB_ARBI 61 +-#define SRST_EMEM 62 +-#define SRST_USB_PERI 63 +- +-#define SRST_DMAC2 64 +-#define SRST_MAC 66 +-#define SRST_GPS 67 +-#define SRST_RKPWM 69 +-#define SRST_CCP 71 +-#define SRST_USBHOST0 72 +-#define SRST_HSIC 73 +-#define SRST_HSIC_AUX 74 +-#define SRST_HSIC_PHY 75 +-#define SRST_HSADC 76 +-#define SRST_NANDC0 77 +-#define SRST_NANDC1 78 +- +-#define SRST_TZPC 80 +-#define SRST_SPI0 83 +-#define SRST_SPI1 84 +-#define SRST_SPI2 85 +-#define SRST_SARADC 87 +-#define SRST_PDALIVE_NIU 88 +-#define SRST_PDPMU_INTMEM 89 +-#define SRST_PDPMU_NIU 90 +-#define SRST_SGRF 91 +- +-#define SRST_VIO_ARBI 96 +-#define SRST_RGA_NIU 97 +-#define SRST_VIO0_NIU_AXI 98 +-#define SRST_VIO_NIU_AHB 99 +-#define SRST_LCDC0_AXI 100 +-#define SRST_LCDC0_AHB 101 +-#define SRST_LCDC0_DCLK 102 +-#define SRST_VIO1_NIU_AXI 103 +-#define SRST_VIP 104 +-#define SRST_RGA_CORE 105 +-#define SRST_IEP_AXI 106 +-#define SRST_IEP_AHB 107 +-#define SRST_RGA_AXI 108 +-#define SRST_RGA_AHB 109 +-#define SRST_ISP 110 +-#define SRST_EDP 111 +- +-#define SRST_VCODEC_AXI 112 +-#define SRST_VCODEC_AHB 113 +-#define SRST_VIO_H2P 114 +-#define SRST_MIPIDSI0 115 +-#define SRST_MIPIDSI1 116 +-#define SRST_MIPICSI 117 +-#define SRST_LVDS_PHY 118 +-#define SRST_LVDS_CON 119 +-#define SRST_GPU 120 +-#define SRST_HDMI 121 +-#define SRST_CORE_PVTM 124 +-#define SRST_GPU_PVTM 125 +- +-#define SRST_MMC0 128 +-#define SRST_SDIO0 129 +-#define SRST_SDIO1 130 +-#define SRST_EMMC 131 +-#define SRST_USBOTG_AHB 132 +-#define SRST_USBOTG_PHY 133 +-#define SRST_USBOTG_CON 134 +-#define SRST_USBHOST0_AHB 135 +-#define SRST_USBHOST0_PHY 136 +-#define SRST_USBHOST0_CON 137 +-#define SRST_USBHOST1_AHB 138 +-#define SRST_USBHOST1_PHY 139 +-#define SRST_USBHOST1_CON 140 +-#define SRST_USB_ADP 141 +-#define SRST_ACC_EFUSE 142 +- +-#define SRST_CORESIGHT 144 +-#define SRST_PD_CORE_AHB_NOC 145 +-#define SRST_PD_CORE_APB_NOC 146 +-#define SRST_PD_CORE_MP_AXI 147 +-#define SRST_GIC 148 +-#define SRST_LCDC_PWM0 149 +-#define SRST_LCDC_PWM1 150 +-#define SRST_VIO0_H2P_BRG 151 +-#define SRST_VIO1_H2P_BRG 152 +-#define SRST_RGA_H2P_BRG 153 +-#define SRST_HEVC 154 +-#define SRST_TSADC 159 +- +-#define SRST_DDRPHY0 160 +-#define SRST_DDRPHY0_APB 161 +-#define SRST_DDRCTRL0 162 +-#define SRST_DDRCTRL0_APB 163 +-#define SRST_DDRPHY0_CTRL 164 +-#define SRST_DDRPHY1 165 +-#define SRST_DDRPHY1_APB 166 +-#define SRST_DDRCTRL1 167 +-#define SRST_DDRCTRL1_APB 168 +-#define SRST_DDRPHY1_CTRL 169 +-#define SRST_DDRMSCH0 170 +-#define SRST_DDRMSCH1 171 +-#define SRST_CRYPTO 174 +-#define SRST_C2C_HOST 175 +- +-#define SRST_LCDC1_AXI 176 +-#define SRST_LCDC1_AHB 177 +-#define SRST_LCDC1_DCLK 178 +-#define SRST_UART0 179 +-#define SRST_UART1 180 +-#define SRST_UART2 181 +-#define SRST_UART3 182 +-#define SRST_UART4 183 +-#define SRST_SIMC 186 +-#define SRST_PS2C 187 +-#define SRST_TSP 188 +-#define SRST_TSP_CLKIN0 189 +-#define SRST_TSP_CLKIN1 190 +-#define SRST_TSP_27M 191 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3308-cru.h b/scripts/dtc/include-prefixes/dt-bindings/clock/rk3308-cru.h +deleted file mode 100644 +index d97840f9ee2e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3308-cru.h ++++ /dev/null +@@ -1,387 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2019 Rockchip Electronics Co. Ltd. +- * Author: Finley Xiao +- */ +- +-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H +-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H +- +-/* core clocks */ +-#define PLL_APLL 1 +-#define PLL_DPLL 2 +-#define PLL_VPLL0 3 +-#define PLL_VPLL1 4 +-#define ARMCLK 5 +- +-/* sclk (special clocks) */ +-#define USB480M 14 +-#define SCLK_RTC32K 15 +-#define SCLK_PVTM_CORE 16 +-#define SCLK_UART0 17 +-#define SCLK_UART1 18 +-#define SCLK_UART2 19 +-#define SCLK_UART3 20 +-#define SCLK_UART4 21 +-#define SCLK_I2C0 22 +-#define SCLK_I2C1 23 +-#define SCLK_I2C2 24 +-#define SCLK_I2C3 25 +-#define SCLK_PWM0 26 +-#define SCLK_SPI0 27 +-#define SCLK_SPI1 28 +-#define SCLK_SPI2 29 +-#define SCLK_TIMER0 30 +-#define SCLK_TIMER1 31 +-#define SCLK_TIMER2 32 +-#define SCLK_TIMER3 33 +-#define SCLK_TIMER4 34 +-#define SCLK_TIMER5 35 +-#define SCLK_TSADC 36 +-#define SCLK_SARADC 37 +-#define SCLK_OTP 38 +-#define SCLK_OTP_USR 39 +-#define SCLK_CPU_BOOST 40 +-#define SCLK_CRYPTO 41 +-#define SCLK_CRYPTO_APK 42 +-#define SCLK_NANDC_DIV 43 +-#define SCLK_NANDC_DIV50 44 +-#define SCLK_NANDC 45 +-#define SCLK_SDMMC_DIV 46 +-#define SCLK_SDMMC_DIV50 47 +-#define SCLK_SDMMC 48 +-#define SCLK_SDMMC_DRV 49 +-#define SCLK_SDMMC_SAMPLE 50 +-#define SCLK_SDIO_DIV 51 +-#define SCLK_SDIO_DIV50 52 +-#define SCLK_SDIO 53 +-#define SCLK_SDIO_DRV 54 +-#define SCLK_SDIO_SAMPLE 55 +-#define SCLK_EMMC_DIV 56 +-#define SCLK_EMMC_DIV50 57 +-#define SCLK_EMMC 58 +-#define SCLK_EMMC_DRV 59 +-#define SCLK_EMMC_SAMPLE 60 +-#define SCLK_SFC 61 +-#define SCLK_OTG_ADP 62 +-#define SCLK_MAC_SRC 63 +-#define SCLK_MAC 64 +-#define SCLK_MAC_REF 65 +-#define SCLK_MAC_RX_TX 66 +-#define SCLK_MAC_RMII 67 +-#define SCLK_DDR_MON_TIMER 68 +-#define SCLK_DDR_MON 69 +-#define SCLK_DDRCLK 70 +-#define SCLK_PMU 71 +-#define SCLK_USBPHY_REF 72 +-#define SCLK_WIFI 73 +-#define SCLK_PVTM_PMU 74 +-#define SCLK_PDM 75 +-#define SCLK_I2S0_8CH_TX 76 +-#define SCLK_I2S0_8CH_TX_OUT 77 +-#define SCLK_I2S0_8CH_RX 78 +-#define SCLK_I2S0_8CH_RX_OUT 79 +-#define SCLK_I2S1_8CH_TX 80 +-#define SCLK_I2S1_8CH_TX_OUT 81 +-#define SCLK_I2S1_8CH_RX 82 +-#define SCLK_I2S1_8CH_RX_OUT 83 +-#define SCLK_I2S2_8CH_TX 84 +-#define SCLK_I2S2_8CH_TX_OUT 85 +-#define SCLK_I2S2_8CH_RX 86 +-#define SCLK_I2S2_8CH_RX_OUT 87 +-#define SCLK_I2S3_8CH_TX 88 +-#define SCLK_I2S3_8CH_TX_OUT 89 +-#define SCLK_I2S3_8CH_RX 90 +-#define SCLK_I2S3_8CH_RX_OUT 91 +-#define SCLK_I2S0_2CH 92 +-#define SCLK_I2S0_2CH_OUT 93 +-#define SCLK_I2S1_2CH 94 +-#define SCLK_I2S1_2CH_OUT 95 +-#define SCLK_SPDIF_TX_DIV 96 +-#define SCLK_SPDIF_TX_DIV50 97 +-#define SCLK_SPDIF_TX 98 +-#define SCLK_SPDIF_RX_DIV 99 +-#define SCLK_SPDIF_RX_DIV50 100 +-#define SCLK_SPDIF_RX 101 +-#define SCLK_I2S0_8CH_TX_MUX 102 +-#define SCLK_I2S0_8CH_RX_MUX 103 +-#define SCLK_I2S1_8CH_TX_MUX 104 +-#define SCLK_I2S1_8CH_RX_MUX 105 +-#define SCLK_I2S2_8CH_TX_MUX 106 +-#define SCLK_I2S2_8CH_RX_MUX 107 +-#define SCLK_I2S3_8CH_TX_MUX 108 +-#define SCLK_I2S3_8CH_RX_MUX 109 +-#define SCLK_I2S0_8CH_TX_SRC 110 +-#define SCLK_I2S0_8CH_RX_SRC 111 +-#define SCLK_I2S1_8CH_TX_SRC 112 +-#define SCLK_I2S1_8CH_RX_SRC 113 +-#define SCLK_I2S2_8CH_TX_SRC 114 +-#define SCLK_I2S2_8CH_RX_SRC 115 +-#define SCLK_I2S3_8CH_TX_SRC 116 +-#define SCLK_I2S3_8CH_RX_SRC 117 +-#define SCLK_I2S0_2CH_SRC 118 +-#define SCLK_I2S1_2CH_SRC 119 +-#define SCLK_PWM1 120 +-#define SCLK_PWM2 121 +-#define SCLK_OWIRE 122 +- +-/* dclk */ +-#define DCLK_VOP 125 +- +-/* aclk */ +-#define ACLK_BUS_SRC 130 +-#define ACLK_BUS 131 +-#define ACLK_PERI_SRC 132 +-#define ACLK_PERI 133 +-#define ACLK_MAC 134 +-#define ACLK_CRYPTO 135 +-#define ACLK_VOP 136 +-#define ACLK_GIC 137 +-#define ACLK_DMAC0 138 +-#define ACLK_DMAC1 139 +- +-/* hclk */ +-#define HCLK_BUS 150 +-#define HCLK_PERI 151 +-#define HCLK_AUDIO 152 +-#define HCLK_NANDC 153 +-#define HCLK_SDMMC 154 +-#define HCLK_SDIO 155 +-#define HCLK_EMMC 156 +-#define HCLK_SFC 157 +-#define HCLK_OTG 158 +-#define HCLK_HOST 159 +-#define HCLK_HOST_ARB 160 +-#define HCLK_PDM 161 +-#define HCLK_SPDIFTX 162 +-#define HCLK_SPDIFRX 163 +-#define HCLK_I2S0_8CH 164 +-#define HCLK_I2S1_8CH 165 +-#define HCLK_I2S2_8CH 166 +-#define HCLK_I2S3_8CH 167 +-#define HCLK_I2S0_2CH 168 +-#define HCLK_I2S1_2CH 169 +-#define HCLK_VAD 170 +-#define HCLK_CRYPTO 171 +-#define HCLK_VOP 172 +- +-/* pclk */ +-#define PCLK_BUS 190 +-#define PCLK_DDR 191 +-#define PCLK_PERI 192 +-#define PCLK_PMU 193 +-#define PCLK_AUDIO 194 +-#define PCLK_MAC 195 +-#define PCLK_ACODEC 196 +-#define PCLK_UART0 197 +-#define PCLK_UART1 198 +-#define PCLK_UART2 199 +-#define PCLK_UART3 200 +-#define PCLK_UART4 201 +-#define PCLK_I2C0 202 +-#define PCLK_I2C1 203 +-#define PCLK_I2C2 204 +-#define PCLK_I2C3 205 +-#define PCLK_PWM0 206 +-#define PCLK_SPI0 207 +-#define PCLK_SPI1 208 +-#define PCLK_SPI2 209 +-#define PCLK_SARADC 210 +-#define PCLK_TSADC 211 +-#define PCLK_TIMER 212 +-#define PCLK_OTP_NS 213 +-#define PCLK_WDT 214 +-#define PCLK_GPIO0 215 +-#define PCLK_GPIO1 216 +-#define PCLK_GPIO2 217 +-#define PCLK_GPIO3 218 +-#define PCLK_GPIO4 219 +-#define PCLK_SGRF 220 +-#define PCLK_GRF 221 +-#define PCLK_USBSD_DET 222 +-#define PCLK_DDR_UPCTL 223 +-#define PCLK_DDR_MON 224 +-#define PCLK_DDRPHY 225 +-#define PCLK_DDR_STDBY 226 +-#define PCLK_USB_GRF 227 +-#define PCLK_CRU 228 +-#define PCLK_OTP_PHY 229 +-#define PCLK_CPU_BOOST 230 +-#define PCLK_PWM1 231 +-#define PCLK_PWM2 232 +-#define PCLK_CAN 233 +-#define PCLK_OWIRE 234 +- +-#define CLK_NR_CLKS (PCLK_OWIRE + 1) +- +-/* soft-reset indices */ +- +-/* cru_softrst_con0 */ +-#define SRST_CORE0_PO 0 +-#define SRST_CORE1_PO 1 +-#define SRST_CORE2_PO 2 +-#define SRST_CORE3_PO 3 +-#define SRST_CORE0 4 +-#define SRST_CORE1 5 +-#define SRST_CORE2 6 +-#define SRST_CORE3 7 +-#define SRST_CORE0_DBG 8 +-#define SRST_CORE1_DBG 9 +-#define SRST_CORE2_DBG 10 +-#define SRST_CORE3_DBG 11 +-#define SRST_TOPDBG 12 +-#define SRST_CORE_NOC 13 +-#define SRST_STRC_A 14 +-#define SRST_L2C 15 +- +-/* cru_softrst_con1 */ +-#define SRST_DAP 16 +-#define SRST_CORE_PVTM 17 +-#define SRST_CORE_PRF 18 +-#define SRST_CORE_GRF 19 +-#define SRST_DDRUPCTL 20 +-#define SRST_DDRUPCTL_P 22 +-#define SRST_MSCH 23 +-#define SRST_DDRMON_P 25 +-#define SRST_DDRSTDBY_P 26 +-#define SRST_DDRSTDBY 27 +-#define SRST_DDRPHY 28 +-#define SRST_DDRPHY_DIV 29 +-#define SRST_DDRPHY_P 30 +- +-/* cru_softrst_con2 */ +-#define SRST_BUS_NIU_H 32 +-#define SRST_USB_NIU_P 33 +-#define SRST_CRYPTO_A 34 +-#define SRST_CRYPTO_H 35 +-#define SRST_CRYPTO 36 +-#define SRST_CRYPTO_APK 37 +-#define SRST_VOP_A 38 +-#define SRST_VOP_H 39 +-#define SRST_VOP_D 40 +-#define SRST_INTMEM_A 41 +-#define SRST_ROM_H 42 +-#define SRST_GIC_A 43 +-#define SRST_UART0_P 44 +-#define SRST_UART0 45 +-#define SRST_UART1_P 46 +-#define SRST_UART1 47 +- +-/* cru_softrst_con3 */ +-#define SRST_UART2_P 48 +-#define SRST_UART2 49 +-#define SRST_UART3_P 50 +-#define SRST_UART3 51 +-#define SRST_UART4_P 52 +-#define SRST_UART4 53 +-#define SRST_I2C0_P 54 +-#define SRST_I2C0 55 +-#define SRST_I2C1_P 56 +-#define SRST_I2C1 57 +-#define SRST_I2C2_P 58 +-#define SRST_I2C2 59 +-#define SRST_I2C3_P 60 +-#define SRST_I2C3 61 +-#define SRST_PWM0_P 62 +-#define SRST_PWM0 63 +- +-/* cru_softrst_con4 */ +-#define SRST_SPI0_P 64 +-#define SRST_SPI0 65 +-#define SRST_SPI1_P 66 +-#define SRST_SPI1 67 +-#define SRST_SPI2_P 68 +-#define SRST_SPI2 69 +-#define SRST_SARADC_P 70 +-#define SRST_TSADC_P 71 +-#define SRST_TSADC 72 +-#define SRST_TIMER0_P 73 +-#define SRST_TIMER0 74 +-#define SRST_TIMER1 75 +-#define SRST_TIMER2 76 +-#define SRST_TIMER3 77 +-#define SRST_TIMER4 78 +-#define SRST_TIMER5 79 +- +-/* cru_softrst_con5 */ +-#define SRST_OTP_NS_P 80 +-#define SRST_OTP_NS_SBPI 81 +-#define SRST_OTP_NS_USR 82 +-#define SRST_OTP_PHY_P 83 +-#define SRST_OTP_PHY 84 +-#define SRST_GPIO0_P 86 +-#define SRST_GPIO1_P 87 +-#define SRST_GPIO2_P 88 +-#define SRST_GPIO3_P 89 +-#define SRST_GPIO4_P 90 +-#define SRST_GRF_P 91 +-#define SRST_USBSD_DET_P 92 +-#define SRST_PMU 93 +-#define SRST_PMU_PVTM 94 +-#define SRST_USB_GRF_P 95 +- +-/* cru_softrst_con6 */ +-#define SRST_CPU_BOOST 96 +-#define SRST_CPU_BOOST_P 97 +-#define SRST_PWM1_P 98 +-#define SRST_PWM1 99 +-#define SRST_PWM2_P 100 +-#define SRST_PWM2 101 +-#define SRST_PERI_NIU_A 104 +-#define SRST_PERI_NIU_H 105 +-#define SRST_PERI_NIU_p 106 +-#define SRST_USB2OTG_H 107 +-#define SRST_USB2OTG 108 +-#define SRST_USB2OTG_ADP 109 +-#define SRST_USB2HOST_H 110 +-#define SRST_USB2HOST_ARB_H 111 +- +-/* cru_softrst_con7 */ +-#define SRST_USB2HOST_AUX_H 112 +-#define SRST_USB2HOST_EHCI 113 +-#define SRST_USB2HOST 114 +-#define SRST_USBPHYPOR 115 +-#define SRST_UTMI0 116 +-#define SRST_UTMI1 117 +-#define SRST_SDIO_H 118 +-#define SRST_EMMC_H 119 +-#define SRST_SFC_H 120 +-#define SRST_SFC 121 +-#define SRST_SD_H 122 +-#define SRST_NANDC_H 123 +-#define SRST_NANDC_N 124 +-#define SRST_MAC_A 125 +-#define SRST_CAN_P 126 +-#define SRST_OWIRE_P 127 +- +-/* cru_softrst_con8 */ +-#define SRST_AUDIO_NIU_H 128 +-#define SRST_AUDIO_NIU_P 129 +-#define SRST_PDM_H 130 +-#define SRST_PDM_M 131 +-#define SRST_SPDIFTX_H 132 +-#define SRST_SPDIFTX_M 133 +-#define SRST_SPDIFRX_H 134 +-#define SRST_SPDIFRX_M 135 +-#define SRST_I2S0_8CH_H 136 +-#define SRST_I2S0_8CH_TX_M 137 +-#define SRST_I2S0_8CH_RX_M 138 +-#define SRST_I2S1_8CH_H 139 +-#define SRST_I2S1_8CH_TX_M 140 +-#define SRST_I2S1_8CH_RX_M 141 +-#define SRST_I2S2_8CH_H 142 +-#define SRST_I2S2_8CH_TX_M 143 +- +-/* cru_softrst_con9 */ +-#define SRST_I2S2_8CH_RX_M 144 +-#define SRST_I2S3_8CH_H 145 +-#define SRST_I2S3_8CH_TX_M 146 +-#define SRST_I2S3_8CH_RX_M 147 +-#define SRST_I2S0_2CH_H 148 +-#define SRST_I2S0_2CH_M 149 +-#define SRST_I2S1_2CH_H 150 +-#define SRST_I2S1_2CH_M 151 +-#define SRST_VAD_H 152 +-#define SRST_ACODEC_P 153 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3328-cru.h b/scripts/dtc/include-prefixes/dt-bindings/clock/rk3328-cru.h +deleted file mode 100644 +index 555b4ff660ae..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3328-cru.h ++++ /dev/null +@@ -1,393 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (c) 2016 Rockchip Electronics Co. Ltd. +- * Author: Elaine +- */ +- +-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H +-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H +- +-/* core clocks */ +-#define PLL_APLL 1 +-#define PLL_DPLL 2 +-#define PLL_CPLL 3 +-#define PLL_GPLL 4 +-#define PLL_NPLL 5 +-#define ARMCLK 6 +- +-/* sclk gates (special clocks) */ +-#define SCLK_RTC32K 30 +-#define SCLK_SDMMC_EXT 31 +-#define SCLK_SPI 32 +-#define SCLK_SDMMC 33 +-#define SCLK_SDIO 34 +-#define SCLK_EMMC 35 +-#define SCLK_TSADC 36 +-#define SCLK_SARADC 37 +-#define SCLK_UART0 38 +-#define SCLK_UART1 39 +-#define SCLK_UART2 40 +-#define SCLK_I2S0 41 +-#define SCLK_I2S1 42 +-#define SCLK_I2S2 43 +-#define SCLK_I2S1_OUT 44 +-#define SCLK_I2S2_OUT 45 +-#define SCLK_SPDIF 46 +-#define SCLK_TIMER0 47 +-#define SCLK_TIMER1 48 +-#define SCLK_TIMER2 49 +-#define SCLK_TIMER3 50 +-#define SCLK_TIMER4 51 +-#define SCLK_TIMER5 52 +-#define SCLK_WIFI 53 +-#define SCLK_CIF_OUT 54 +-#define SCLK_I2C0 55 +-#define SCLK_I2C1 56 +-#define SCLK_I2C2 57 +-#define SCLK_I2C3 58 +-#define SCLK_CRYPTO 59 +-#define SCLK_PWM 60 +-#define SCLK_PDM 61 +-#define SCLK_EFUSE 62 +-#define SCLK_OTP 63 +-#define SCLK_DDRCLK 64 +-#define SCLK_VDEC_CABAC 65 +-#define SCLK_VDEC_CORE 66 +-#define SCLK_VENC_DSP 67 +-#define SCLK_VENC_CORE 68 +-#define SCLK_RGA 69 +-#define SCLK_HDMI_SFC 70 +-#define SCLK_HDMI_CEC 71 +-#define SCLK_USB3_REF 72 +-#define SCLK_USB3_SUSPEND 73 +-#define SCLK_SDMMC_DRV 74 +-#define SCLK_SDIO_DRV 75 +-#define SCLK_EMMC_DRV 76 +-#define SCLK_SDMMC_EXT_DRV 77 +-#define SCLK_SDMMC_SAMPLE 78 +-#define SCLK_SDIO_SAMPLE 79 +-#define SCLK_EMMC_SAMPLE 80 +-#define SCLK_SDMMC_EXT_SAMPLE 81 +-#define SCLK_VOP 82 +-#define SCLK_MAC2PHY_RXTX 83 +-#define SCLK_MAC2PHY_SRC 84 +-#define SCLK_MAC2PHY_REF 85 +-#define SCLK_MAC2PHY_OUT 86 +-#define SCLK_MAC2IO_RX 87 +-#define SCLK_MAC2IO_TX 88 +-#define SCLK_MAC2IO_REFOUT 89 +-#define SCLK_MAC2IO_REF 90 +-#define SCLK_MAC2IO_OUT 91 +-#define SCLK_TSP 92 +-#define SCLK_HSADC_TSP 93 +-#define SCLK_USB3PHY_REF 94 +-#define SCLK_REF_USB3OTG 95 +-#define SCLK_USB3OTG_REF 96 +-#define SCLK_USB3OTG_SUSPEND 97 +-#define SCLK_REF_USB3OTG_SRC 98 +-#define SCLK_MAC2IO_SRC 99 +-#define SCLK_MAC2IO 100 +-#define SCLK_MAC2PHY 101 +-#define SCLK_MAC2IO_EXT 102 +- +-/* dclk gates */ +-#define DCLK_LCDC 120 +-#define DCLK_HDMIPHY 121 +-#define HDMIPHY 122 +-#define USB480M 123 +-#define DCLK_LCDC_SRC 124 +- +-/* aclk gates */ +-#define ACLK_AXISRAM 130 +-#define ACLK_VOP_PRE 131 +-#define ACLK_USB3OTG 132 +-#define ACLK_RGA_PRE 133 +-#define ACLK_DMAC 134 +-#define ACLK_GPU 135 +-#define ACLK_BUS_PRE 136 +-#define ACLK_PERI_PRE 137 +-#define ACLK_RKVDEC_PRE 138 +-#define ACLK_RKVDEC 139 +-#define ACLK_RKVENC 140 +-#define ACLK_VPU_PRE 141 +-#define ACLK_VIO_PRE 142 +-#define ACLK_VPU 143 +-#define ACLK_VIO 144 +-#define ACLK_VOP 145 +-#define ACLK_GMAC 146 +-#define ACLK_H265 147 +-#define ACLK_H264 148 +-#define ACLK_MAC2PHY 149 +-#define ACLK_MAC2IO 150 +-#define ACLK_DCF 151 +-#define ACLK_TSP 152 +-#define ACLK_PERI 153 +-#define ACLK_RGA 154 +-#define ACLK_IEP 155 +-#define ACLK_CIF 156 +-#define ACLK_HDCP 157 +- +-/* pclk gates */ +-#define PCLK_GPIO0 200 +-#define PCLK_GPIO1 201 +-#define PCLK_GPIO2 202 +-#define PCLK_GPIO3 203 +-#define PCLK_GRF 204 +-#define PCLK_I2C0 205 +-#define PCLK_I2C1 206 +-#define PCLK_I2C2 207 +-#define PCLK_I2C3 208 +-#define PCLK_SPI 209 +-#define PCLK_UART0 210 +-#define PCLK_UART1 211 +-#define PCLK_UART2 212 +-#define PCLK_TSADC 213 +-#define PCLK_PWM 214 +-#define PCLK_TIMER 215 +-#define PCLK_BUS_PRE 216 +-#define PCLK_PERI_PRE 217 +-#define PCLK_HDMI_CTRL 218 +-#define PCLK_HDMI_PHY 219 +-#define PCLK_GMAC 220 +-#define PCLK_H265 221 +-#define PCLK_MAC2PHY 222 +-#define PCLK_MAC2IO 223 +-#define PCLK_USB3PHY_OTG 224 +-#define PCLK_USB3PHY_PIPE 225 +-#define PCLK_USB3_GRF 226 +-#define PCLK_USB2_GRF 227 +-#define PCLK_HDMIPHY 228 +-#define PCLK_DDR 229 +-#define PCLK_PERI 230 +-#define PCLK_HDMI 231 +-#define PCLK_HDCP 232 +-#define PCLK_DCF 233 +-#define PCLK_SARADC 234 +-#define PCLK_ACODECPHY 235 +-#define PCLK_WDT 236 +- +-/* hclk gates */ +-#define HCLK_PERI 308 +-#define HCLK_TSP 309 +-#define HCLK_GMAC 310 +-#define HCLK_I2S0_8CH 311 +-#define HCLK_I2S1_8CH 312 +-#define HCLK_I2S2_2CH 313 +-#define HCLK_SPDIF_8CH 314 +-#define HCLK_VOP 315 +-#define HCLK_NANDC 316 +-#define HCLK_SDMMC 317 +-#define HCLK_SDIO 318 +-#define HCLK_EMMC 319 +-#define HCLK_SDMMC_EXT 320 +-#define HCLK_RKVDEC_PRE 321 +-#define HCLK_RKVDEC 322 +-#define HCLK_RKVENC 323 +-#define HCLK_VPU_PRE 324 +-#define HCLK_VIO_PRE 325 +-#define HCLK_VPU 326 +-#define HCLK_BUS_PRE 328 +-#define HCLK_PERI_PRE 329 +-#define HCLK_H264 330 +-#define HCLK_CIF 331 +-#define HCLK_OTG_PMU 332 +-#define HCLK_OTG 333 +-#define HCLK_HOST0 334 +-#define HCLK_HOST0_ARB 335 +-#define HCLK_CRYPTO_MST 336 +-#define HCLK_CRYPTO_SLV 337 +-#define HCLK_PDM 338 +-#define HCLK_IEP 339 +-#define HCLK_RGA 340 +-#define HCLK_HDCP 341 +- +-#define CLK_NR_CLKS (HCLK_HDCP + 1) +- +-/* soft-reset indices */ +-#define SRST_CORE0_PO 0 +-#define SRST_CORE1_PO 1 +-#define SRST_CORE2_PO 2 +-#define SRST_CORE3_PO 3 +-#define SRST_CORE0 4 +-#define SRST_CORE1 5 +-#define SRST_CORE2 6 +-#define SRST_CORE3 7 +-#define SRST_CORE0_DBG 8 +-#define SRST_CORE1_DBG 9 +-#define SRST_CORE2_DBG 10 +-#define SRST_CORE3_DBG 11 +-#define SRST_TOPDBG 12 +-#define SRST_CORE_NIU 13 +-#define SRST_STRC_A 14 +-#define SRST_L2C 15 +- +-#define SRST_A53_GIC 18 +-#define SRST_DAP 19 +-#define SRST_PMU_P 21 +-#define SRST_EFUSE 22 +-#define SRST_BUSSYS_H 23 +-#define SRST_BUSSYS_P 24 +-#define SRST_SPDIF 25 +-#define SRST_INTMEM 26 +-#define SRST_ROM 27 +-#define SRST_GPIO0 28 +-#define SRST_GPIO1 29 +-#define SRST_GPIO2 30 +-#define SRST_GPIO3 31 +- +-#define SRST_I2S0 32 +-#define SRST_I2S1 33 +-#define SRST_I2S2 34 +-#define SRST_I2S0_H 35 +-#define SRST_I2S1_H 36 +-#define SRST_I2S2_H 37 +-#define SRST_UART0 38 +-#define SRST_UART1 39 +-#define SRST_UART2 40 +-#define SRST_UART0_P 41 +-#define SRST_UART1_P 42 +-#define SRST_UART2_P 43 +-#define SRST_I2C0 44 +-#define SRST_I2C1 45 +-#define SRST_I2C2 46 +-#define SRST_I2C3 47 +- +-#define SRST_I2C0_P 48 +-#define SRST_I2C1_P 49 +-#define SRST_I2C2_P 50 +-#define SRST_I2C3_P 51 +-#define SRST_EFUSE_SE_P 52 +-#define SRST_EFUSE_NS_P 53 +-#define SRST_PWM0 54 +-#define SRST_PWM0_P 55 +-#define SRST_DMA 56 +-#define SRST_TSP_A 57 +-#define SRST_TSP_H 58 +-#define SRST_TSP 59 +-#define SRST_TSP_HSADC 60 +-#define SRST_DCF_A 61 +-#define SRST_DCF_P 62 +- +-#define SRST_SCR 64 +-#define SRST_SPI 65 +-#define SRST_TSADC 66 +-#define SRST_TSADC_P 67 +-#define SRST_CRYPTO 68 +-#define SRST_SGRF 69 +-#define SRST_GRF 70 +-#define SRST_USB_GRF 71 +-#define SRST_TIMER_6CH_P 72 +-#define SRST_TIMER0 73 +-#define SRST_TIMER1 74 +-#define SRST_TIMER2 75 +-#define SRST_TIMER3 76 +-#define SRST_TIMER4 77 +-#define SRST_TIMER5 78 +-#define SRST_USB3GRF 79 +- +-#define SRST_PHYNIU 80 +-#define SRST_HDMIPHY 81 +-#define SRST_VDAC 82 +-#define SRST_ACODEC_p 83 +-#define SRST_SARADC 85 +-#define SRST_SARADC_P 86 +-#define SRST_GRF_DDR 87 +-#define SRST_DFIMON 88 +-#define SRST_MSCH 89 +-#define SRST_DDRMSCH 91 +-#define SRST_DDRCTRL 92 +-#define SRST_DDRCTRL_P 93 +-#define SRST_DDRPHY 94 +-#define SRST_DDRPHY_P 95 +- +-#define SRST_GMAC_NIU_A 96 +-#define SRST_GMAC_NIU_P 97 +-#define SRST_GMAC2PHY_A 98 +-#define SRST_GMAC2IO_A 99 +-#define SRST_MACPHY 100 +-#define SRST_OTP_PHY 101 +-#define SRST_GPU_A 102 +-#define SRST_GPU_NIU_A 103 +-#define SRST_SDMMCEXT 104 +-#define SRST_PERIPH_NIU_A 105 +-#define SRST_PERIHP_NIU_H 106 +-#define SRST_PERIHP_P 107 +-#define SRST_PERIPHSYS_H 108 +-#define SRST_MMC0 109 +-#define SRST_SDIO 110 +-#define SRST_EMMC 111 +- +-#define SRST_USB2OTG_H 112 +-#define SRST_USB2OTG 113 +-#define SRST_USB2OTG_ADP 114 +-#define SRST_USB2HOST_H 115 +-#define SRST_USB2HOST_ARB 116 +-#define SRST_USB2HOST_AUX 117 +-#define SRST_USB2HOST_EHCIPHY 118 +-#define SRST_USB2HOST_UTMI 119 +-#define SRST_USB3OTG 120 +-#define SRST_USBPOR 121 +-#define SRST_USB2OTG_UTMI 122 +-#define SRST_USB2HOST_PHY_UTMI 123 +-#define SRST_USB3OTG_UTMI 124 +-#define SRST_USB3PHY_U2 125 +-#define SRST_USB3PHY_U3 126 +-#define SRST_USB3PHY_PIPE 127 +- +-#define SRST_VIO_A 128 +-#define SRST_VIO_BUS_H 129 +-#define SRST_VIO_H2P_H 130 +-#define SRST_VIO_ARBI_H 131 +-#define SRST_VOP_NIU_A 132 +-#define SRST_VOP_A 133 +-#define SRST_VOP_H 134 +-#define SRST_VOP_D 135 +-#define SRST_RGA 136 +-#define SRST_RGA_NIU_A 137 +-#define SRST_RGA_A 138 +-#define SRST_RGA_H 139 +-#define SRST_IEP_A 140 +-#define SRST_IEP_H 141 +-#define SRST_HDMI 142 +-#define SRST_HDMI_P 143 +- +-#define SRST_HDCP_A 144 +-#define SRST_HDCP 145 +-#define SRST_HDCP_H 146 +-#define SRST_CIF_A 147 +-#define SRST_CIF_H 148 +-#define SRST_CIF_P 149 +-#define SRST_OTP_P 150 +-#define SRST_OTP_SBPI 151 +-#define SRST_OTP_USER 152 +-#define SRST_DDRCTRL_A 153 +-#define SRST_DDRSTDY_P 154 +-#define SRST_DDRSTDY 155 +-#define SRST_PDM_H 156 +-#define SRST_PDM 157 +-#define SRST_USB3PHY_OTG_P 158 +-#define SRST_USB3PHY_PIPE_P 159 +- +-#define SRST_VCODEC_A 160 +-#define SRST_VCODEC_NIU_A 161 +-#define SRST_VCODEC_H 162 +-#define SRST_VCODEC_NIU_H 163 +-#define SRST_VDEC_A 164 +-#define SRST_VDEC_NIU_A 165 +-#define SRST_VDEC_H 166 +-#define SRST_VDEC_NIU_H 167 +-#define SRST_VDEC_CORE 168 +-#define SRST_VDEC_CABAC 169 +-#define SRST_DDRPHYDIV 175 +- +-#define SRST_RKVENC_NIU_A 176 +-#define SRST_RKVENC_NIU_H 177 +-#define SRST_RKVENC_H265_A 178 +-#define SRST_RKVENC_H265_P 179 +-#define SRST_RKVENC_H265_CORE 180 +-#define SRST_RKVENC_H265_DSP 181 +-#define SRST_RKVENC_H264_A 182 +-#define SRST_RKVENC_H264_H 183 +-#define SRST_RKVENC_INTMEM 184 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3368-cru.h b/scripts/dtc/include-prefixes/dt-bindings/clock/rk3368-cru.h +deleted file mode 100644 +index 83c72a163fd3..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3368-cru.h ++++ /dev/null +@@ -1,384 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (c) 2015 Heiko Stuebner +- */ +- +-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H +-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H +- +-/* core clocks */ +-#define PLL_APLLB 1 +-#define PLL_APLLL 2 +-#define PLL_DPLL 3 +-#define PLL_CPLL 4 +-#define PLL_GPLL 5 +-#define PLL_NPLL 6 +-#define ARMCLKB 7 +-#define ARMCLKL 8 +- +-/* sclk gates (special clocks) */ +-#define SCLK_GPU_CORE 64 +-#define SCLK_SPI0 65 +-#define SCLK_SPI1 66 +-#define SCLK_SPI2 67 +-#define SCLK_SDMMC 68 +-#define SCLK_SDIO0 69 +-#define SCLK_EMMC 71 +-#define SCLK_TSADC 72 +-#define SCLK_SARADC 73 +-#define SCLK_NANDC0 75 +-#define SCLK_UART0 77 +-#define SCLK_UART1 78 +-#define SCLK_UART2 79 +-#define SCLK_UART3 80 +-#define SCLK_UART4 81 +-#define SCLK_I2S_8CH 82 +-#define SCLK_SPDIF_8CH 83 +-#define SCLK_I2S_2CH 84 +-#define SCLK_TIMER00 85 +-#define SCLK_TIMER01 86 +-#define SCLK_TIMER02 87 +-#define SCLK_TIMER03 88 +-#define SCLK_TIMER04 89 +-#define SCLK_TIMER05 90 +-#define SCLK_OTGPHY0 93 +-#define SCLK_OTG_ADP 96 +-#define SCLK_HSICPHY480M 97 +-#define SCLK_HSICPHY12M 98 +-#define SCLK_MACREF 99 +-#define SCLK_VOP0_PWM 100 +-#define SCLK_MAC_RX 102 +-#define SCLK_MAC_TX 103 +-#define SCLK_EDP_24M 104 +-#define SCLK_EDP 105 +-#define SCLK_RGA 106 +-#define SCLK_ISP 107 +-#define SCLK_HDCP 108 +-#define SCLK_HDMI_HDCP 109 +-#define SCLK_HDMI_CEC 110 +-#define SCLK_HEVC_CABAC 111 +-#define SCLK_HEVC_CORE 112 +-#define SCLK_I2S_8CH_OUT 113 +-#define SCLK_SDMMC_DRV 114 +-#define SCLK_SDIO0_DRV 115 +-#define SCLK_EMMC_DRV 117 +-#define SCLK_SDMMC_SAMPLE 118 +-#define SCLK_SDIO0_SAMPLE 119 +-#define SCLK_EMMC_SAMPLE 121 +-#define SCLK_USBPHY480M 122 +-#define SCLK_PVTM_CORE 123 +-#define SCLK_PVTM_GPU 124 +-#define SCLK_PVTM_PMU 125 +-#define SCLK_SFC 126 +-#define SCLK_MAC 127 +-#define SCLK_MACREF_OUT 128 +-#define SCLK_TIMER10 133 +-#define SCLK_TIMER11 134 +-#define SCLK_TIMER12 135 +-#define SCLK_TIMER13 136 +-#define SCLK_TIMER14 137 +-#define SCLK_TIMER15 138 +-#define SCLK_VIP_OUT 139 +- +-#define DCLK_VOP 190 +-#define MCLK_CRYPTO 191 +- +-/* aclk gates */ +-#define ACLK_GPU_MEM 192 +-#define ACLK_GPU_CFG 193 +-#define ACLK_DMAC_BUS 194 +-#define ACLK_DMAC_PERI 195 +-#define ACLK_PERI_MMU 196 +-#define ACLK_GMAC 197 +-#define ACLK_VOP 198 +-#define ACLK_VOP_IEP 199 +-#define ACLK_RGA 200 +-#define ACLK_HDCP 201 +-#define ACLK_IEP 202 +-#define ACLK_VIO0_NOC 203 +-#define ACLK_VIP 204 +-#define ACLK_ISP 205 +-#define ACLK_VIO1_NOC 206 +-#define ACLK_VIDEO 208 +-#define ACLK_BUS 209 +-#define ACLK_PERI 210 +- +-/* pclk gates */ +-#define PCLK_GPIO0 320 +-#define PCLK_GPIO1 321 +-#define PCLK_GPIO2 322 +-#define PCLK_GPIO3 323 +-#define PCLK_PMUGRF 324 +-#define PCLK_MAILBOX 325 +-#define PCLK_GRF 329 +-#define PCLK_SGRF 330 +-#define PCLK_PMU 331 +-#define PCLK_I2C0 332 +-#define PCLK_I2C1 333 +-#define PCLK_I2C2 334 +-#define PCLK_I2C3 335 +-#define PCLK_I2C4 336 +-#define PCLK_I2C5 337 +-#define PCLK_SPI0 338 +-#define PCLK_SPI1 339 +-#define PCLK_SPI2 340 +-#define PCLK_UART0 341 +-#define PCLK_UART1 342 +-#define PCLK_UART2 343 +-#define PCLK_UART3 344 +-#define PCLK_UART4 345 +-#define PCLK_TSADC 346 +-#define PCLK_SARADC 347 +-#define PCLK_SIM 348 +-#define PCLK_GMAC 349 +-#define PCLK_PWM0 350 +-#define PCLK_PWM1 351 +-#define PCLK_TIMER0 353 +-#define PCLK_TIMER1 354 +-#define PCLK_EDP_CTRL 355 +-#define PCLK_MIPI_DSI0 356 +-#define PCLK_MIPI_CSI 358 +-#define PCLK_HDCP 359 +-#define PCLK_HDMI_CTRL 360 +-#define PCLK_VIO_H2P 361 +-#define PCLK_BUS 362 +-#define PCLK_PERI 363 +-#define PCLK_DDRUPCTL 364 +-#define PCLK_DDRPHY 365 +-#define PCLK_ISP 366 +-#define PCLK_VIP 367 +-#define PCLK_WDT 368 +-#define PCLK_EFUSE256 369 +-#define PCLK_DPHYRX 370 +-#define PCLK_DPHYTX0 371 +- +-/* hclk gates */ +-#define HCLK_SFC 448 +-#define HCLK_OTG0 449 +-#define HCLK_HOST0 450 +-#define HCLK_HOST1 451 +-#define HCLK_HSIC 452 +-#define HCLK_NANDC0 453 +-#define HCLK_TSP 455 +-#define HCLK_SDMMC 456 +-#define HCLK_SDIO0 457 +-#define HCLK_EMMC 459 +-#define HCLK_HSADC 460 +-#define HCLK_CRYPTO 461 +-#define HCLK_I2S_2CH 462 +-#define HCLK_I2S_8CH 463 +-#define HCLK_SPDIF 464 +-#define HCLK_VOP 465 +-#define HCLK_ROM 467 +-#define HCLK_IEP 468 +-#define HCLK_ISP 469 +-#define HCLK_RGA 470 +-#define HCLK_VIO_AHB_ARBI 471 +-#define HCLK_VIO_NOC 472 +-#define HCLK_VIP 473 +-#define HCLK_VIO_H2P 474 +-#define HCLK_VIO_HDCPMMU 475 +-#define HCLK_VIDEO 476 +-#define HCLK_BUS 477 +-#define HCLK_PERI 478 +- +-#define CLK_NR_CLKS (HCLK_PERI + 1) +- +-/* soft-reset indices */ +-#define SRST_CORE_B0 0 +-#define SRST_CORE_B1 1 +-#define SRST_CORE_B2 2 +-#define SRST_CORE_B3 3 +-#define SRST_CORE_B0_PO 4 +-#define SRST_CORE_B1_PO 5 +-#define SRST_CORE_B2_PO 6 +-#define SRST_CORE_B3_PO 7 +-#define SRST_L2_B 8 +-#define SRST_ADB_B 9 +-#define SRST_PD_CORE_B_NIU 10 +-#define SRST_PDBUS_STRSYS 11 +-#define SRST_SOCDBG_B 14 +-#define SRST_CORE_B_DBG 15 +- +-#define SRST_DMAC1 18 +-#define SRST_INTMEM 19 +-#define SRST_ROM 20 +-#define SRST_SPDIF8CH 21 +-#define SRST_I2S8CH 23 +-#define SRST_MAILBOX 24 +-#define SRST_I2S2CH 25 +-#define SRST_EFUSE_256 26 +-#define SRST_MCU_SYS 28 +-#define SRST_MCU_PO 29 +-#define SRST_MCU_NOC 30 +-#define SRST_EFUSE 31 +- +-#define SRST_GPIO0 32 +-#define SRST_GPIO1 33 +-#define SRST_GPIO2 34 +-#define SRST_GPIO3 35 +-#define SRST_GPIO4 36 +-#define SRST_PMUGRF 41 +-#define SRST_I2C0 42 +-#define SRST_I2C1 43 +-#define SRST_I2C2 44 +-#define SRST_I2C3 45 +-#define SRST_I2C4 46 +-#define SRST_I2C5 47 +- +-#define SRST_DWPWM 48 +-#define SRST_MMC_PERI 49 +-#define SRST_PERIPH_MMU 50 +-#define SRST_GRF 55 +-#define SRST_PMU 56 +-#define SRST_PERIPH_AXI 57 +-#define SRST_PERIPH_AHB 58 +-#define SRST_PERIPH_APB 59 +-#define SRST_PERIPH_NIU 60 +-#define SRST_PDPERI_AHB_ARBI 61 +-#define SRST_EMEM 62 +-#define SRST_USB_PERI 63 +- +-#define SRST_DMAC2 64 +-#define SRST_MAC 66 +-#define SRST_GPS 67 +-#define SRST_RKPWM 69 +-#define SRST_USBHOST0 72 +-#define SRST_HSIC 73 +-#define SRST_HSIC_AUX 74 +-#define SRST_HSIC_PHY 75 +-#define SRST_HSADC 76 +-#define SRST_NANDC0 77 +-#define SRST_SFC 79 +- +-#define SRST_SPI0 83 +-#define SRST_SPI1 84 +-#define SRST_SPI2 85 +-#define SRST_SARADC 87 +-#define SRST_PDALIVE_NIU 88 +-#define SRST_PDPMU_INTMEM 89 +-#define SRST_PDPMU_NIU 90 +-#define SRST_SGRF 91 +- +-#define SRST_VIO_ARBI 96 +-#define SRST_RGA_NIU 97 +-#define SRST_VIO0_NIU_AXI 98 +-#define SRST_VIO_NIU_AHB 99 +-#define SRST_LCDC0_AXI 100 +-#define SRST_LCDC0_AHB 101 +-#define SRST_LCDC0_DCLK 102 +-#define SRST_VIP 104 +-#define SRST_RGA_CORE 105 +-#define SRST_IEP_AXI 106 +-#define SRST_IEP_AHB 107 +-#define SRST_RGA_AXI 108 +-#define SRST_RGA_AHB 109 +-#define SRST_ISP 110 +-#define SRST_EDP_24M 111 +- +-#define SRST_VIDEO_AXI 112 +-#define SRST_VIDEO_AHB 113 +-#define SRST_MIPIDPHYTX 114 +-#define SRST_MIPIDSI0 115 +-#define SRST_MIPIDPHYRX 116 +-#define SRST_MIPICSI 117 +-#define SRST_GPU 120 +-#define SRST_HDMI 121 +-#define SRST_EDP 122 +-#define SRST_PMU_PVTM 123 +-#define SRST_CORE_PVTM 124 +-#define SRST_GPU_PVTM 125 +-#define SRST_GPU_SYS 126 +-#define SRST_GPU_MEM_NIU 127 +- +-#define SRST_MMC0 128 +-#define SRST_SDIO0 129 +-#define SRST_EMMC 131 +-#define SRST_USBOTG_AHB 132 +-#define SRST_USBOTG_PHY 133 +-#define SRST_USBOTG_CON 134 +-#define SRST_USBHOST0_AHB 135 +-#define SRST_USBHOST0_PHY 136 +-#define SRST_USBHOST0_CON 137 +-#define SRST_USBOTG_UTMI 138 +-#define SRST_USBHOST1_UTMI 139 +-#define SRST_USB_ADP 141 +- +-#define SRST_CORESIGHT 144 +-#define SRST_PD_CORE_AHB_NOC 145 +-#define SRST_PD_CORE_APB_NOC 146 +-#define SRST_GIC 148 +-#define SRST_LCDC_PWM0 149 +-#define SRST_RGA_H2P_BRG 153 +-#define SRST_VIDEO 154 +-#define SRST_GPU_CFG_NIU 157 +-#define SRST_TSADC 159 +- +-#define SRST_DDRPHY0 160 +-#define SRST_DDRPHY0_APB 161 +-#define SRST_DDRCTRL0 162 +-#define SRST_DDRCTRL0_APB 163 +-#define SRST_VIDEO_NIU 165 +-#define SRST_VIDEO_NIU_AHB 167 +-#define SRST_DDRMSCH0 170 +-#define SRST_PDBUS_AHB 173 +-#define SRST_CRYPTO 174 +- +-#define SRST_UART0 179 +-#define SRST_UART1 180 +-#define SRST_UART2 181 +-#define SRST_UART3 182 +-#define SRST_UART4 183 +-#define SRST_SIMC 186 +-#define SRST_TSP 188 +-#define SRST_TSP_CLKIN0 189 +- +-#define SRST_CORE_L0 192 +-#define SRST_CORE_L1 193 +-#define SRST_CORE_L2 194 +-#define SRST_CORE_L3 195 +-#define SRST_CORE_L0_PO 195 +-#define SRST_CORE_L1_PO 197 +-#define SRST_CORE_L2_PO 198 +-#define SRST_CORE_L3_PO 199 +-#define SRST_L2_L 200 +-#define SRST_ADB_L 201 +-#define SRST_PD_CORE_L_NIU 202 +-#define SRST_CCI_SYS 203 +-#define SRST_CCI_DDR 204 +-#define SRST_CCI 205 +-#define SRST_SOCDBG_L 206 +-#define SRST_CORE_L_DBG 207 +- +-#define SRST_CORE_B0_NC 208 +-#define SRST_CORE_B0_PO_NC 209 +-#define SRST_L2_B_NC 210 +-#define SRST_ADB_B_NC 211 +-#define SRST_PD_CORE_B_NIU_NC 212 +-#define SRST_PDBUS_STRSYS_NC 213 +-#define SRST_CORE_L0_NC 214 +-#define SRST_CORE_L0_PO_NC 215 +-#define SRST_L2_L_NC 216 +-#define SRST_ADB_L_NC 217 +-#define SRST_PD_CORE_L_NIU_NC 218 +-#define SRST_CCI_SYS_NC 219 +-#define SRST_CCI_DDR_NC 220 +-#define SRST_CCI_NC 221 +-#define SRST_TRACE_NC 222 +- +-#define SRST_TIMER00 224 +-#define SRST_TIMER01 225 +-#define SRST_TIMER02 226 +-#define SRST_TIMER03 227 +-#define SRST_TIMER04 228 +-#define SRST_TIMER05 229 +-#define SRST_TIMER10 230 +-#define SRST_TIMER11 231 +-#define SRST_TIMER12 232 +-#define SRST_TIMER13 233 +-#define SRST_TIMER14 234 +-#define SRST_TIMER15 235 +-#define SRST_TIMER0_APB 236 +-#define SRST_TIMER1_APB 237 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3399-cru.h b/scripts/dtc/include-prefixes/dt-bindings/clock/rk3399-cru.h +deleted file mode 100644 +index 44e0a319f077..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3399-cru.h ++++ /dev/null +@@ -1,751 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (c) 2016 Rockchip Electronics Co. Ltd. +- * Author: Xing Zheng +- */ +- +-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H +-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H +- +-/* core clocks */ +-#define PLL_APLLL 1 +-#define PLL_APLLB 2 +-#define PLL_DPLL 3 +-#define PLL_CPLL 4 +-#define PLL_GPLL 5 +-#define PLL_NPLL 6 +-#define PLL_VPLL 7 +-#define ARMCLKL 8 +-#define ARMCLKB 9 +- +-/* sclk gates (special clocks) */ +-#define SCLK_I2C1 65 +-#define SCLK_I2C2 66 +-#define SCLK_I2C3 67 +-#define SCLK_I2C5 68 +-#define SCLK_I2C6 69 +-#define SCLK_I2C7 70 +-#define SCLK_SPI0 71 +-#define SCLK_SPI1 72 +-#define SCLK_SPI2 73 +-#define SCLK_SPI4 74 +-#define SCLK_SPI5 75 +-#define SCLK_SDMMC 76 +-#define SCLK_SDIO 77 +-#define SCLK_EMMC 78 +-#define SCLK_TSADC 79 +-#define SCLK_SARADC 80 +-#define SCLK_UART0 81 +-#define SCLK_UART1 82 +-#define SCLK_UART2 83 +-#define SCLK_UART3 84 +-#define SCLK_SPDIF_8CH 85 +-#define SCLK_I2S0_8CH 86 +-#define SCLK_I2S1_8CH 87 +-#define SCLK_I2S2_8CH 88 +-#define SCLK_I2S_8CH_OUT 89 +-#define SCLK_TIMER00 90 +-#define SCLK_TIMER01 91 +-#define SCLK_TIMER02 92 +-#define SCLK_TIMER03 93 +-#define SCLK_TIMER04 94 +-#define SCLK_TIMER05 95 +-#define SCLK_TIMER06 96 +-#define SCLK_TIMER07 97 +-#define SCLK_TIMER08 98 +-#define SCLK_TIMER09 99 +-#define SCLK_TIMER10 100 +-#define SCLK_TIMER11 101 +-#define SCLK_MACREF 102 +-#define SCLK_MAC_RX 103 +-#define SCLK_MAC_TX 104 +-#define SCLK_MAC 105 +-#define SCLK_MACREF_OUT 106 +-#define SCLK_VOP0_PWM 107 +-#define SCLK_VOP1_PWM 108 +-#define SCLK_RGA_CORE 109 +-#define SCLK_ISP0 110 +-#define SCLK_ISP1 111 +-#define SCLK_HDMI_CEC 112 +-#define SCLK_HDMI_SFR 113 +-#define SCLK_DP_CORE 114 +-#define SCLK_PVTM_CORE_L 115 +-#define SCLK_PVTM_CORE_B 116 +-#define SCLK_PVTM_GPU 117 +-#define SCLK_PVTM_DDR 118 +-#define SCLK_MIPIDPHY_REF 119 +-#define SCLK_MIPIDPHY_CFG 120 +-#define SCLK_HSICPHY 121 +-#define SCLK_USBPHY480M 122 +-#define SCLK_USB2PHY0_REF 123 +-#define SCLK_USB2PHY1_REF 124 +-#define SCLK_UPHY0_TCPDPHY_REF 125 +-#define SCLK_UPHY0_TCPDCORE 126 +-#define SCLK_UPHY1_TCPDPHY_REF 127 +-#define SCLK_UPHY1_TCPDCORE 128 +-#define SCLK_USB3OTG0_REF 129 +-#define SCLK_USB3OTG1_REF 130 +-#define SCLK_USB3OTG0_SUSPEND 131 +-#define SCLK_USB3OTG1_SUSPEND 132 +-#define SCLK_CRYPTO0 133 +-#define SCLK_CRYPTO1 134 +-#define SCLK_CCI_TRACE 135 +-#define SCLK_CS 136 +-#define SCLK_CIF_OUT 137 +-#define SCLK_PCIEPHY_REF 138 +-#define SCLK_PCIE_CORE 139 +-#define SCLK_M0_PERILP 140 +-#define SCLK_M0_PERILP_DEC 141 +-#define SCLK_CM0S 142 +-#define SCLK_DBG_NOC 143 +-#define SCLK_DBG_PD_CORE_B 144 +-#define SCLK_DBG_PD_CORE_L 145 +-#define SCLK_DFIMON0_TIMER 146 +-#define SCLK_DFIMON1_TIMER 147 +-#define SCLK_INTMEM0 148 +-#define SCLK_INTMEM1 149 +-#define SCLK_INTMEM2 150 +-#define SCLK_INTMEM3 151 +-#define SCLK_INTMEM4 152 +-#define SCLK_INTMEM5 153 +-#define SCLK_SDMMC_DRV 154 +-#define SCLK_SDMMC_SAMPLE 155 +-#define SCLK_SDIO_DRV 156 +-#define SCLK_SDIO_SAMPLE 157 +-#define SCLK_VDU_CORE 158 +-#define SCLK_VDU_CA 159 +-#define SCLK_PCIE_PM 160 +-#define SCLK_SPDIF_REC_DPTX 161 +-#define SCLK_DPHY_PLL 162 +-#define SCLK_DPHY_TX0_CFG 163 +-#define SCLK_DPHY_TX1RX1_CFG 164 +-#define SCLK_DPHY_RX0_CFG 165 +-#define SCLK_RMII_SRC 166 +-#define SCLK_PCIEPHY_REF100M 167 +-#define SCLK_DDRC 168 +-#define SCLK_TESTCLKOUT1 169 +-#define SCLK_TESTCLKOUT2 170 +- +-#define DCLK_VOP0 180 +-#define DCLK_VOP1 181 +-#define DCLK_VOP0_DIV 182 +-#define DCLK_VOP1_DIV 183 +-#define DCLK_M0_PERILP 184 +-#define DCLK_VOP0_FRAC 185 +-#define DCLK_VOP1_FRAC 186 +- +-#define FCLK_CM0S 190 +- +-/* aclk gates */ +-#define ACLK_PERIHP 192 +-#define ACLK_PERIHP_NOC 193 +-#define ACLK_PERILP0 194 +-#define ACLK_PERILP0_NOC 195 +-#define ACLK_PERF_PCIE 196 +-#define ACLK_PCIE 197 +-#define ACLK_INTMEM 198 +-#define ACLK_TZMA 199 +-#define ACLK_DCF 200 +-#define ACLK_CCI 201 +-#define ACLK_CCI_NOC0 202 +-#define ACLK_CCI_NOC1 203 +-#define ACLK_CCI_GRF 204 +-#define ACLK_CENTER 205 +-#define ACLK_CENTER_MAIN_NOC 206 +-#define ACLK_CENTER_PERI_NOC 207 +-#define ACLK_GPU 208 +-#define ACLK_PERF_GPU 209 +-#define ACLK_GPU_GRF 210 +-#define ACLK_DMAC0_PERILP 211 +-#define ACLK_DMAC1_PERILP 212 +-#define ACLK_GMAC 213 +-#define ACLK_GMAC_NOC 214 +-#define ACLK_PERF_GMAC 215 +-#define ACLK_VOP0_NOC 216 +-#define ACLK_VOP0 217 +-#define ACLK_VOP1_NOC 218 +-#define ACLK_VOP1 219 +-#define ACLK_RGA 220 +-#define ACLK_RGA_NOC 221 +-#define ACLK_HDCP 222 +-#define ACLK_HDCP_NOC 223 +-#define ACLK_HDCP22 224 +-#define ACLK_IEP 225 +-#define ACLK_IEP_NOC 226 +-#define ACLK_VIO 227 +-#define ACLK_VIO_NOC 228 +-#define ACLK_ISP0 229 +-#define ACLK_ISP1 230 +-#define ACLK_ISP0_NOC 231 +-#define ACLK_ISP1_NOC 232 +-#define ACLK_ISP0_WRAPPER 233 +-#define ACLK_ISP1_WRAPPER 234 +-#define ACLK_VCODEC 235 +-#define ACLK_VCODEC_NOC 236 +-#define ACLK_VDU 237 +-#define ACLK_VDU_NOC 238 +-#define ACLK_PERI 239 +-#define ACLK_EMMC 240 +-#define ACLK_EMMC_CORE 241 +-#define ACLK_EMMC_NOC 242 +-#define ACLK_EMMC_GRF 243 +-#define ACLK_USB3 244 +-#define ACLK_USB3_NOC 245 +-#define ACLK_USB3OTG0 246 +-#define ACLK_USB3OTG1 247 +-#define ACLK_USB3_RKSOC_AXI_PERF 248 +-#define ACLK_USB3_GRF 249 +-#define ACLK_GIC 250 +-#define ACLK_GIC_NOC 251 +-#define ACLK_GIC_ADB400_CORE_L_2_GIC 252 +-#define ACLK_GIC_ADB400_CORE_B_2_GIC 253 +-#define ACLK_GIC_ADB400_GIC_2_CORE_L 254 +-#define ACLK_GIC_ADB400_GIC_2_CORE_B 255 +-#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 +-#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 +-#define ACLK_ADB400M_PD_CORE_L 258 +-#define ACLK_ADB400M_PD_CORE_B 259 +-#define ACLK_PERF_CORE_L 260 +-#define ACLK_PERF_CORE_B 261 +-#define ACLK_GIC_PRE 262 +-#define ACLK_VOP0_PRE 263 +-#define ACLK_VOP1_PRE 264 +- +-/* pclk gates */ +-#define PCLK_PERIHP 320 +-#define PCLK_PERIHP_NOC 321 +-#define PCLK_PERILP0 322 +-#define PCLK_PERILP1 323 +-#define PCLK_PERILP1_NOC 324 +-#define PCLK_PERILP_SGRF 325 +-#define PCLK_PERIHP_GRF 326 +-#define PCLK_PCIE 327 +-#define PCLK_SGRF 328 +-#define PCLK_INTR_ARB 329 +-#define PCLK_CENTER_MAIN_NOC 330 +-#define PCLK_CIC 331 +-#define PCLK_COREDBG_B 332 +-#define PCLK_COREDBG_L 333 +-#define PCLK_DBG_CXCS_PD_CORE_B 334 +-#define PCLK_DCF 335 +-#define PCLK_GPIO2 336 +-#define PCLK_GPIO3 337 +-#define PCLK_GPIO4 338 +-#define PCLK_GRF 339 +-#define PCLK_HSICPHY 340 +-#define PCLK_I2C1 341 +-#define PCLK_I2C2 342 +-#define PCLK_I2C3 343 +-#define PCLK_I2C5 344 +-#define PCLK_I2C6 345 +-#define PCLK_I2C7 346 +-#define PCLK_SPI0 347 +-#define PCLK_SPI1 348 +-#define PCLK_SPI2 349 +-#define PCLK_SPI4 350 +-#define PCLK_SPI5 351 +-#define PCLK_UART0 352 +-#define PCLK_UART1 353 +-#define PCLK_UART2 354 +-#define PCLK_UART3 355 +-#define PCLK_TSADC 356 +-#define PCLK_SARADC 357 +-#define PCLK_GMAC 358 +-#define PCLK_GMAC_NOC 359 +-#define PCLK_TIMER0 360 +-#define PCLK_TIMER1 361 +-#define PCLK_EDP 362 +-#define PCLK_EDP_NOC 363 +-#define PCLK_EDP_CTRL 364 +-#define PCLK_VIO 365 +-#define PCLK_VIO_NOC 366 +-#define PCLK_VIO_GRF 367 +-#define PCLK_MIPI_DSI0 368 +-#define PCLK_MIPI_DSI1 369 +-#define PCLK_HDCP 370 +-#define PCLK_HDCP_NOC 371 +-#define PCLK_HDMI_CTRL 372 +-#define PCLK_DP_CTRL 373 +-#define PCLK_HDCP22 374 +-#define PCLK_GASKET 375 +-#define PCLK_DDR 376 +-#define PCLK_DDR_MON 377 +-#define PCLK_DDR_SGRF 378 +-#define PCLK_ISP1_WRAPPER 379 +-#define PCLK_WDT 380 +-#define PCLK_EFUSE1024NS 381 +-#define PCLK_EFUSE1024S 382 +-#define PCLK_PMU_INTR_ARB 383 +-#define PCLK_MAILBOX0 384 +-#define PCLK_USBPHY_MUX_G 385 +-#define PCLK_UPHY0_TCPHY_G 386 +-#define PCLK_UPHY0_TCPD_G 387 +-#define PCLK_UPHY1_TCPHY_G 388 +-#define PCLK_UPHY1_TCPD_G 389 +-#define PCLK_ALIVE 390 +- +-/* hclk gates */ +-#define HCLK_PERIHP 448 +-#define HCLK_PERILP0 449 +-#define HCLK_PERILP1 450 +-#define HCLK_PERILP0_NOC 451 +-#define HCLK_PERILP1_NOC 452 +-#define HCLK_M0_PERILP 453 +-#define HCLK_M0_PERILP_NOC 454 +-#define HCLK_AHB1TOM 455 +-#define HCLK_HOST0 456 +-#define HCLK_HOST0_ARB 457 +-#define HCLK_HOST1 458 +-#define HCLK_HOST1_ARB 459 +-#define HCLK_HSIC 460 +-#define HCLK_SD 461 +-#define HCLK_SDMMC 462 +-#define HCLK_SDMMC_NOC 463 +-#define HCLK_M_CRYPTO0 464 +-#define HCLK_M_CRYPTO1 465 +-#define HCLK_S_CRYPTO0 466 +-#define HCLK_S_CRYPTO1 467 +-#define HCLK_I2S0_8CH 468 +-#define HCLK_I2S1_8CH 469 +-#define HCLK_I2S2_8CH 470 +-#define HCLK_SPDIF 471 +-#define HCLK_VOP0_NOC 472 +-#define HCLK_VOP0 473 +-#define HCLK_VOP1_NOC 474 +-#define HCLK_VOP1 475 +-#define HCLK_ROM 476 +-#define HCLK_IEP 477 +-#define HCLK_IEP_NOC 478 +-#define HCLK_ISP0 479 +-#define HCLK_ISP1 480 +-#define HCLK_ISP0_NOC 481 +-#define HCLK_ISP1_NOC 482 +-#define HCLK_ISP0_WRAPPER 483 +-#define HCLK_ISP1_WRAPPER 484 +-#define HCLK_RGA 485 +-#define HCLK_RGA_NOC 486 +-#define HCLK_HDCP 487 +-#define HCLK_HDCP_NOC 488 +-#define HCLK_HDCP22 489 +-#define HCLK_VCODEC 490 +-#define HCLK_VCODEC_NOC 491 +-#define HCLK_VDU 492 +-#define HCLK_VDU_NOC 493 +-#define HCLK_SDIO 494 +-#define HCLK_SDIO_NOC 495 +-#define HCLK_SDIOAUDIO_NOC 496 +- +-#define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) +- +-/* pmu-clocks indices */ +- +-#define PLL_PPLL 1 +- +-#define SCLK_32K_SUSPEND_PMU 2 +-#define SCLK_SPI3_PMU 3 +-#define SCLK_TIMER12_PMU 4 +-#define SCLK_TIMER13_PMU 5 +-#define SCLK_UART4_PMU 6 +-#define SCLK_PVTM_PMU 7 +-#define SCLK_WIFI_PMU 8 +-#define SCLK_I2C0_PMU 9 +-#define SCLK_I2C4_PMU 10 +-#define SCLK_I2C8_PMU 11 +- +-#define PCLK_SRC_PMU 19 +-#define PCLK_PMU 20 +-#define PCLK_PMUGRF_PMU 21 +-#define PCLK_INTMEM1_PMU 22 +-#define PCLK_GPIO0_PMU 23 +-#define PCLK_GPIO1_PMU 24 +-#define PCLK_SGRF_PMU 25 +-#define PCLK_NOC_PMU 26 +-#define PCLK_I2C0_PMU 27 +-#define PCLK_I2C4_PMU 28 +-#define PCLK_I2C8_PMU 29 +-#define PCLK_RKPWM_PMU 30 +-#define PCLK_SPI3_PMU 31 +-#define PCLK_TIMER_PMU 32 +-#define PCLK_MAILBOX_PMU 33 +-#define PCLK_UART4_PMU 34 +-#define PCLK_WDT_M0_PMU 35 +- +-#define FCLK_CM0S_SRC_PMU 44 +-#define FCLK_CM0S_PMU 45 +-#define SCLK_CM0S_PMU 46 +-#define HCLK_CM0S_PMU 47 +-#define DCLK_CM0S_PMU 48 +-#define PCLK_INTR_ARB_PMU 49 +-#define HCLK_NOC_PMU 50 +- +-#define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1) +- +-/* soft-reset indices */ +- +-/* cru_softrst_con0 */ +-#define SRST_CORE_L0 0 +-#define SRST_CORE_B0 1 +-#define SRST_CORE_PO_L0 2 +-#define SRST_CORE_PO_B0 3 +-#define SRST_L2_L 4 +-#define SRST_L2_B 5 +-#define SRST_ADB_L 6 +-#define SRST_ADB_B 7 +-#define SRST_A_CCI 8 +-#define SRST_A_CCIM0_NOC 9 +-#define SRST_A_CCIM1_NOC 10 +-#define SRST_DBG_NOC 11 +- +-/* cru_softrst_con1 */ +-#define SRST_CORE_L0_T 16 +-#define SRST_CORE_L1 17 +-#define SRST_CORE_L2 18 +-#define SRST_CORE_L3 19 +-#define SRST_CORE_PO_L0_T 20 +-#define SRST_CORE_PO_L1 21 +-#define SRST_CORE_PO_L2 22 +-#define SRST_CORE_PO_L3 23 +-#define SRST_A_ADB400_GIC2COREL 24 +-#define SRST_A_ADB400_COREL2GIC 25 +-#define SRST_P_DBG_L 26 +-#define SRST_L2_L_T 28 +-#define SRST_ADB_L_T 29 +-#define SRST_A_RKPERF_L 30 +-#define SRST_PVTM_CORE_L 31 +- +-/* cru_softrst_con2 */ +-#define SRST_CORE_B0_T 32 +-#define SRST_CORE_B1 33 +-#define SRST_CORE_PO_B0_T 36 +-#define SRST_CORE_PO_B1 37 +-#define SRST_A_ADB400_GIC2COREB 40 +-#define SRST_A_ADB400_COREB2GIC 41 +-#define SRST_P_DBG_B 42 +-#define SRST_L2_B_T 43 +-#define SRST_ADB_B_T 45 +-#define SRST_A_RKPERF_B 46 +-#define SRST_PVTM_CORE_B 47 +- +-/* cru_softrst_con3 */ +-#define SRST_A_CCI_T 50 +-#define SRST_A_CCIM0_NOC_T 51 +-#define SRST_A_CCIM1_NOC_T 52 +-#define SRST_A_ADB400M_PD_CORE_B_T 53 +-#define SRST_A_ADB400M_PD_CORE_L_T 54 +-#define SRST_DBG_NOC_T 55 +-#define SRST_DBG_CXCS 56 +-#define SRST_CCI_TRACE 57 +-#define SRST_P_CCI_GRF 58 +- +-/* cru_softrst_con4 */ +-#define SRST_A_CENTER_MAIN_NOC 64 +-#define SRST_A_CENTER_PERI_NOC 65 +-#define SRST_P_CENTER_MAIN 66 +-#define SRST_P_DDRMON 67 +-#define SRST_P_CIC 68 +-#define SRST_P_CENTER_SGRF 69 +-#define SRST_DDR0_MSCH 70 +-#define SRST_DDRCFG0_MSCH 71 +-#define SRST_DDR0 72 +-#define SRST_DDRPHY0 73 +-#define SRST_DDR1_MSCH 74 +-#define SRST_DDRCFG1_MSCH 75 +-#define SRST_DDR1 76 +-#define SRST_DDRPHY1 77 +-#define SRST_DDR_CIC 78 +-#define SRST_PVTM_DDR 79 +- +-/* cru_softrst_con5 */ +-#define SRST_A_VCODEC_NOC 80 +-#define SRST_A_VCODEC 81 +-#define SRST_H_VCODEC_NOC 82 +-#define SRST_H_VCODEC 83 +-#define SRST_A_VDU_NOC 88 +-#define SRST_A_VDU 89 +-#define SRST_H_VDU_NOC 90 +-#define SRST_H_VDU 91 +-#define SRST_VDU_CORE 92 +-#define SRST_VDU_CA 93 +- +-/* cru_softrst_con6 */ +-#define SRST_A_IEP_NOC 96 +-#define SRST_A_VOP_IEP 97 +-#define SRST_A_IEP 98 +-#define SRST_H_IEP_NOC 99 +-#define SRST_H_IEP 100 +-#define SRST_A_RGA_NOC 102 +-#define SRST_A_RGA 103 +-#define SRST_H_RGA_NOC 104 +-#define SRST_H_RGA 105 +-#define SRST_RGA_CORE 106 +-#define SRST_EMMC_NOC 108 +-#define SRST_EMMC 109 +-#define SRST_EMMC_GRF 110 +- +-/* cru_softrst_con7 */ +-#define SRST_A_PERIHP_NOC 112 +-#define SRST_P_PERIHP_GRF 113 +-#define SRST_H_PERIHP_NOC 114 +-#define SRST_USBHOST0 115 +-#define SRST_HOSTC0_AUX 116 +-#define SRST_HOST0_ARB 117 +-#define SRST_USBHOST1 118 +-#define SRST_HOSTC1_AUX 119 +-#define SRST_HOST1_ARB 120 +-#define SRST_SDIO0 121 +-#define SRST_SDMMC 122 +-#define SRST_HSIC 123 +-#define SRST_HSIC_AUX 124 +-#define SRST_AHB1TOM 125 +-#define SRST_P_PERIHP_NOC 126 +-#define SRST_HSICPHY 127 +- +-/* cru_softrst_con8 */ +-#define SRST_A_PCIE 128 +-#define SRST_P_PCIE 129 +-#define SRST_PCIE_CORE 130 +-#define SRST_PCIE_MGMT 131 +-#define SRST_PCIE_MGMT_STICKY 132 +-#define SRST_PCIE_PIPE 133 +-#define SRST_PCIE_PM 134 +-#define SRST_PCIEPHY 135 +-#define SRST_A_GMAC_NOC 136 +-#define SRST_A_GMAC 137 +-#define SRST_P_GMAC_NOC 138 +-#define SRST_P_GMAC_GRF 140 +-#define SRST_HSICPHY_POR 142 +-#define SRST_HSICPHY_UTMI 143 +- +-/* cru_softrst_con9 */ +-#define SRST_USB2PHY0_POR 144 +-#define SRST_USB2PHY0_UTMI_PORT0 145 +-#define SRST_USB2PHY0_UTMI_PORT1 146 +-#define SRST_USB2PHY0_EHCIPHY 147 +-#define SRST_UPHY0_PIPE_L00 148 +-#define SRST_UPHY0 149 +-#define SRST_UPHY0_TCPDPWRUP 150 +-#define SRST_USB2PHY1_POR 152 +-#define SRST_USB2PHY1_UTMI_PORT0 153 +-#define SRST_USB2PHY1_UTMI_PORT1 154 +-#define SRST_USB2PHY1_EHCIPHY 155 +-#define SRST_UPHY1_PIPE_L00 156 +-#define SRST_UPHY1 157 +-#define SRST_UPHY1_TCPDPWRUP 158 +- +-/* cru_softrst_con10 */ +-#define SRST_A_PERILP0_NOC 160 +-#define SRST_A_DCF 161 +-#define SRST_GIC500 162 +-#define SRST_DMAC0_PERILP0 163 +-#define SRST_DMAC1_PERILP0 164 +-#define SRST_TZMA 165 +-#define SRST_INTMEM 166 +-#define SRST_ADB400_MST0 167 +-#define SRST_ADB400_MST1 168 +-#define SRST_ADB400_SLV0 169 +-#define SRST_ADB400_SLV1 170 +-#define SRST_H_PERILP0 171 +-#define SRST_H_PERILP0_NOC 172 +-#define SRST_ROM 173 +-#define SRST_CRYPTO_S 174 +-#define SRST_CRYPTO_M 175 +- +-/* cru_softrst_con11 */ +-#define SRST_P_DCF 176 +-#define SRST_CM0S_NOC 177 +-#define SRST_CM0S 178 +-#define SRST_CM0S_DBG 179 +-#define SRST_CM0S_PO 180 +-#define SRST_CRYPTO 181 +-#define SRST_P_PERILP1_SGRF 182 +-#define SRST_P_PERILP1_GRF 183 +-#define SRST_CRYPTO1_S 184 +-#define SRST_CRYPTO1_M 185 +-#define SRST_CRYPTO1 186 +-#define SRST_GIC_NOC 188 +-#define SRST_SD_NOC 189 +-#define SRST_SDIOAUDIO_BRG 190 +- +-/* cru_softrst_con12 */ +-#define SRST_H_PERILP1 192 +-#define SRST_H_PERILP1_NOC 193 +-#define SRST_H_I2S0_8CH 194 +-#define SRST_H_I2S1_8CH 195 +-#define SRST_H_I2S2_8CH 196 +-#define SRST_H_SPDIF_8CH 197 +-#define SRST_P_PERILP1_NOC 198 +-#define SRST_P_EFUSE_1024 199 +-#define SRST_P_EFUSE_1024S 200 +-#define SRST_P_I2C0 201 +-#define SRST_P_I2C1 202 +-#define SRST_P_I2C2 203 +-#define SRST_P_I2C3 204 +-#define SRST_P_I2C4 205 +-#define SRST_P_I2C5 206 +-#define SRST_P_MAILBOX0 207 +- +-/* cru_softrst_con13 */ +-#define SRST_P_UART0 208 +-#define SRST_P_UART1 209 +-#define SRST_P_UART2 210 +-#define SRST_P_UART3 211 +-#define SRST_P_SARADC 212 +-#define SRST_P_TSADC 213 +-#define SRST_P_SPI0 214 +-#define SRST_P_SPI1 215 +-#define SRST_P_SPI2 216 +-#define SRST_P_SPI3 217 +-#define SRST_P_SPI4 218 +-#define SRST_SPI0 219 +-#define SRST_SPI1 220 +-#define SRST_SPI2 221 +-#define SRST_SPI3 222 +-#define SRST_SPI4 223 +- +-/* cru_softrst_con14 */ +-#define SRST_I2S0_8CH 224 +-#define SRST_I2S1_8CH 225 +-#define SRST_I2S2_8CH 226 +-#define SRST_SPDIF_8CH 227 +-#define SRST_UART0 228 +-#define SRST_UART1 229 +-#define SRST_UART2 230 +-#define SRST_UART3 231 +-#define SRST_TSADC 232 +-#define SRST_I2C0 233 +-#define SRST_I2C1 234 +-#define SRST_I2C2 235 +-#define SRST_I2C3 236 +-#define SRST_I2C4 237 +-#define SRST_I2C5 238 +-#define SRST_SDIOAUDIO_NOC 239 +- +-/* cru_softrst_con15 */ +-#define SRST_A_VIO_NOC 240 +-#define SRST_A_HDCP_NOC 241 +-#define SRST_A_HDCP 242 +-#define SRST_H_HDCP_NOC 243 +-#define SRST_H_HDCP 244 +-#define SRST_P_HDCP_NOC 245 +-#define SRST_P_HDCP 246 +-#define SRST_P_HDMI_CTRL 247 +-#define SRST_P_DP_CTRL 248 +-#define SRST_S_DP_CTRL 249 +-#define SRST_C_DP_CTRL 250 +-#define SRST_P_MIPI_DSI0 251 +-#define SRST_P_MIPI_DSI1 252 +-#define SRST_DP_CORE 253 +-#define SRST_DP_I2S 254 +- +-/* cru_softrst_con16 */ +-#define SRST_GASKET 256 +-#define SRST_VIO_GRF 258 +-#define SRST_DPTX_SPDIF_REC 259 +-#define SRST_HDMI_CTRL 260 +-#define SRST_HDCP_CTRL 261 +-#define SRST_A_ISP0_NOC 262 +-#define SRST_A_ISP1_NOC 263 +-#define SRST_H_ISP0_NOC 266 +-#define SRST_H_ISP1_NOC 267 +-#define SRST_H_ISP0 268 +-#define SRST_H_ISP1 269 +-#define SRST_ISP0 270 +-#define SRST_ISP1 271 +- +-/* cru_softrst_con17 */ +-#define SRST_A_VOP0_NOC 272 +-#define SRST_A_VOP1_NOC 273 +-#define SRST_A_VOP0 274 +-#define SRST_A_VOP1 275 +-#define SRST_H_VOP0_NOC 276 +-#define SRST_H_VOP1_NOC 277 +-#define SRST_H_VOP0 278 +-#define SRST_H_VOP1 279 +-#define SRST_D_VOP0 280 +-#define SRST_D_VOP1 281 +-#define SRST_VOP0_PWM 282 +-#define SRST_VOP1_PWM 283 +-#define SRST_P_EDP_NOC 284 +-#define SRST_P_EDP_CTRL 285 +- +-/* cru_softrst_con18 */ +-#define SRST_A_GPU 288 +-#define SRST_A_GPU_NOC 289 +-#define SRST_A_GPU_GRF 290 +-#define SRST_PVTM_GPU 291 +-#define SRST_A_USB3_NOC 292 +-#define SRST_A_USB3_OTG0 293 +-#define SRST_A_USB3_OTG1 294 +-#define SRST_A_USB3_GRF 295 +-#define SRST_PMU 296 +- +-/* cru_softrst_con19 */ +-#define SRST_P_TIMER0_5 304 +-#define SRST_TIMER0 305 +-#define SRST_TIMER1 306 +-#define SRST_TIMER2 307 +-#define SRST_TIMER3 308 +-#define SRST_TIMER4 309 +-#define SRST_TIMER5 310 +-#define SRST_P_TIMER6_11 311 +-#define SRST_TIMER6 312 +-#define SRST_TIMER7 313 +-#define SRST_TIMER8 314 +-#define SRST_TIMER9 315 +-#define SRST_TIMER10 316 +-#define SRST_TIMER11 317 +-#define SRST_P_INTR_ARB_PMU 318 +-#define SRST_P_ALIVE_SGRF 319 +- +-/* cru_softrst_con20 */ +-#define SRST_P_GPIO2 320 +-#define SRST_P_GPIO3 321 +-#define SRST_P_GPIO4 322 +-#define SRST_P_GRF 323 +-#define SRST_P_ALIVE_NOC 324 +-#define SRST_P_WDT0 325 +-#define SRST_P_WDT1 326 +-#define SRST_P_INTR_ARB 327 +-#define SRST_P_UPHY0_DPTX 328 +-#define SRST_P_UPHY0_APB 330 +-#define SRST_P_UPHY0_TCPHY 332 +-#define SRST_P_UPHY1_TCPHY 333 +-#define SRST_P_UPHY0_TCPDCTRL 334 +-#define SRST_P_UPHY1_TCPDCTRL 335 +- +-/* pmu soft-reset indices */ +- +-/* pmu_cru_softrst_con0 */ +-#define SRST_P_NOC 0 +-#define SRST_P_INTMEM 1 +-#define SRST_H_CM0S 2 +-#define SRST_H_CM0S_NOC 3 +-#define SRST_DBG_CM0S 4 +-#define SRST_PO_CM0S 5 +-#define SRST_P_SPI6 6 +-#define SRST_SPI6 7 +-#define SRST_P_TIMER_0_1 8 +-#define SRST_P_TIMER_0 9 +-#define SRST_P_TIMER_1 10 +-#define SRST_P_UART4 11 +-#define SRST_UART4 12 +-#define SRST_P_WDT 13 +- +-/* pmu_cru_softrst_con1 */ +-#define SRST_P_I2C6 16 +-#define SRST_P_I2C7 17 +-#define SRST_P_I2C8 18 +-#define SRST_P_MAILBOX 19 +-#define SRST_P_RKPWM 20 +-#define SRST_P_PMUGRF 21 +-#define SRST_P_SGRF 22 +-#define SRST_P_GPIO0 23 +-#define SRST_P_GPIO1 24 +-#define SRST_P_CRU 25 +-#define SRST_P_INTR 26 +-#define SRST_PVTM 27 +-#define SRST_I2C6 28 +-#define SRST_I2C7 29 +-#define SRST_I2C8 30 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3399-ddr.h b/scripts/dtc/include-prefixes/dt-bindings/clock/rk3399-ddr.h +deleted file mode 100644 +index ed2280844963..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3399-ddr.h ++++ /dev/null +@@ -1,56 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +- +-#ifndef DT_BINDINGS_DDR_H +-#define DT_BINDINGS_DDR_H +- +-/* +- * DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for +- * each corresponding bin. +- */ +- +-/* DDR3-800 (5-5-5) */ +-#define DDR3_800D 0 +-/* DDR3-800 (6-6-6) */ +-#define DDR3_800E 1 +-/* DDR3-1066 (6-6-6) */ +-#define DDR3_1066E 2 +-/* DDR3-1066 (7-7-7) */ +-#define DDR3_1066F 3 +-/* DDR3-1066 (8-8-8) */ +-#define DDR3_1066G 4 +-/* DDR3-1333 (7-7-7) */ +-#define DDR3_1333F 5 +-/* DDR3-1333 (8-8-8) */ +-#define DDR3_1333G 6 +-/* DDR3-1333 (9-9-9) */ +-#define DDR3_1333H 7 +-/* DDR3-1333 (10-10-10) */ +-#define DDR3_1333J 8 +-/* DDR3-1600 (8-8-8) */ +-#define DDR3_1600G 9 +-/* DDR3-1600 (9-9-9) */ +-#define DDR3_1600H 10 +-/* DDR3-1600 (10-10-10) */ +-#define DDR3_1600J 11 +-/* DDR3-1600 (11-11-11) */ +-#define DDR3_1600K 12 +-/* DDR3-1600 (10-10-10) */ +-#define DDR3_1866J 13 +-/* DDR3-1866 (11-11-11) */ +-#define DDR3_1866K 14 +-/* DDR3-1866 (12-12-12) */ +-#define DDR3_1866L 15 +-/* DDR3-1866 (13-13-13) */ +-#define DDR3_1866M 16 +-/* DDR3-2133 (11-11-11) */ +-#define DDR3_2133K 17 +-/* DDR3-2133 (12-12-12) */ +-#define DDR3_2133L 18 +-/* DDR3-2133 (13-13-13) */ +-#define DDR3_2133M 19 +-/* DDR3-2133 (14-14-14) */ +-#define DDR3_2133N 20 +-/* DDR3 ATF default */ +-#define DDR3_DEFAULT 21 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3568-cru.h b/scripts/dtc/include-prefixes/dt-bindings/clock/rk3568-cru.h +deleted file mode 100644 +index d29890865150..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/rk3568-cru.h ++++ /dev/null +@@ -1,926 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2021 Rockchip Electronics Co. Ltd. +- * Author: Elaine Zhang +- */ +- +-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H +-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H +- +-/* pmucru-clocks indices */ +- +-/* pmucru plls */ +-#define PLL_PPLL 1 +-#define PLL_HPLL 2 +- +-/* pmucru clocks */ +-#define XIN_OSC0_DIV 4 +-#define CLK_RTC_32K 5 +-#define CLK_PMU 6 +-#define CLK_I2C0 7 +-#define CLK_RTC32K_FRAC 8 +-#define CLK_UART0_DIV 9 +-#define CLK_UART0_FRAC 10 +-#define SCLK_UART0 11 +-#define DBCLK_GPIO0 12 +-#define CLK_PWM0 13 +-#define CLK_CAPTURE_PWM0_NDFT 14 +-#define CLK_PMUPVTM 15 +-#define CLK_CORE_PMUPVTM 16 +-#define CLK_REF24M 17 +-#define XIN_OSC0_USBPHY0_G 18 +-#define CLK_USBPHY0_REF 19 +-#define XIN_OSC0_USBPHY1_G 20 +-#define CLK_USBPHY1_REF 21 +-#define XIN_OSC0_MIPIDSIPHY0_G 22 +-#define CLK_MIPIDSIPHY0_REF 23 +-#define XIN_OSC0_MIPIDSIPHY1_G 24 +-#define CLK_MIPIDSIPHY1_REF 25 +-#define CLK_WIFI_DIV 26 +-#define CLK_WIFI_OSC0 27 +-#define CLK_WIFI 28 +-#define CLK_PCIEPHY0_DIV 29 +-#define CLK_PCIEPHY0_OSC0 30 +-#define CLK_PCIEPHY0_REF 31 +-#define CLK_PCIEPHY1_DIV 32 +-#define CLK_PCIEPHY1_OSC0 33 +-#define CLK_PCIEPHY1_REF 34 +-#define CLK_PCIEPHY2_DIV 35 +-#define CLK_PCIEPHY2_OSC0 36 +-#define CLK_PCIEPHY2_REF 37 +-#define CLK_PCIE30PHY_REF_M 38 +-#define CLK_PCIE30PHY_REF_N 39 +-#define CLK_HDMI_REF 40 +-#define XIN_OSC0_EDPPHY_G 41 +-#define PCLK_PDPMU 42 +-#define PCLK_PMU 43 +-#define PCLK_UART0 44 +-#define PCLK_I2C0 45 +-#define PCLK_GPIO0 46 +-#define PCLK_PMUPVTM 47 +-#define PCLK_PWM0 48 +-#define CLK_PDPMU 49 +-#define SCLK_32K_IOE 50 +- +-#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1) +- +-/* cru-clocks indices */ +- +-/* cru plls */ +-#define PLL_APLL 1 +-#define PLL_DPLL 2 +-#define PLL_CPLL 3 +-#define PLL_GPLL 4 +-#define PLL_VPLL 5 +-#define PLL_NPLL 6 +- +-/* cru clocks */ +-#define CPLL_333M 9 +-#define ARMCLK 10 +-#define USB480M 11 +-#define ACLK_CORE_NIU2BUS 18 +-#define CLK_CORE_PVTM 19 +-#define CLK_CORE_PVTM_CORE 20 +-#define CLK_CORE_PVTPLL 21 +-#define CLK_GPU_SRC 22 +-#define CLK_GPU_PRE_NDFT 23 +-#define CLK_GPU_PRE_MUX 24 +-#define ACLK_GPU_PRE 25 +-#define PCLK_GPU_PRE 26 +-#define CLK_GPU 27 +-#define CLK_GPU_NP5 28 +-#define PCLK_GPU_PVTM 29 +-#define CLK_GPU_PVTM 30 +-#define CLK_GPU_PVTM_CORE 31 +-#define CLK_GPU_PVTPLL 32 +-#define CLK_NPU_SRC 33 +-#define CLK_NPU_PRE_NDFT 34 +-#define CLK_NPU 35 +-#define CLK_NPU_NP5 36 +-#define HCLK_NPU_PRE 37 +-#define PCLK_NPU_PRE 38 +-#define ACLK_NPU_PRE 39 +-#define ACLK_NPU 40 +-#define HCLK_NPU 41 +-#define PCLK_NPU_PVTM 42 +-#define CLK_NPU_PVTM 43 +-#define CLK_NPU_PVTM_CORE 44 +-#define CLK_NPU_PVTPLL 45 +-#define CLK_DDRPHY1X_SRC 46 +-#define CLK_DDRPHY1X_HWFFC_SRC 47 +-#define CLK_DDR1X 48 +-#define CLK_MSCH 49 +-#define CLK24_DDRMON 50 +-#define ACLK_GIC_AUDIO 51 +-#define HCLK_GIC_AUDIO 52 +-#define HCLK_SDMMC_BUFFER 53 +-#define DCLK_SDMMC_BUFFER 54 +-#define ACLK_GIC600 55 +-#define ACLK_SPINLOCK 56 +-#define HCLK_I2S0_8CH 57 +-#define HCLK_I2S1_8CH 58 +-#define HCLK_I2S2_2CH 59 +-#define HCLK_I2S3_2CH 60 +-#define CLK_I2S0_8CH_TX_SRC 61 +-#define CLK_I2S0_8CH_TX_FRAC 62 +-#define MCLK_I2S0_8CH_TX 63 +-#define I2S0_MCLKOUT_TX 64 +-#define CLK_I2S0_8CH_RX_SRC 65 +-#define CLK_I2S0_8CH_RX_FRAC 66 +-#define MCLK_I2S0_8CH_RX 67 +-#define I2S0_MCLKOUT_RX 68 +-#define CLK_I2S1_8CH_TX_SRC 69 +-#define CLK_I2S1_8CH_TX_FRAC 70 +-#define MCLK_I2S1_8CH_TX 71 +-#define I2S1_MCLKOUT_TX 72 +-#define CLK_I2S1_8CH_RX_SRC 73 +-#define CLK_I2S1_8CH_RX_FRAC 74 +-#define MCLK_I2S1_8CH_RX 75 +-#define I2S1_MCLKOUT_RX 76 +-#define CLK_I2S2_2CH_SRC 77 +-#define CLK_I2S2_2CH_FRAC 78 +-#define MCLK_I2S2_2CH 79 +-#define I2S2_MCLKOUT 80 +-#define CLK_I2S3_2CH_TX_SRC 81 +-#define CLK_I2S3_2CH_TX_FRAC 82 +-#define MCLK_I2S3_2CH_TX 83 +-#define I2S3_MCLKOUT_TX 84 +-#define CLK_I2S3_2CH_RX_SRC 85 +-#define CLK_I2S3_2CH_RX_FRAC 86 +-#define MCLK_I2S3_2CH_RX 87 +-#define I2S3_MCLKOUT_RX 88 +-#define HCLK_PDM 89 +-#define MCLK_PDM 90 +-#define HCLK_VAD 91 +-#define HCLK_SPDIF_8CH 92 +-#define MCLK_SPDIF_8CH_SRC 93 +-#define MCLK_SPDIF_8CH_FRAC 94 +-#define MCLK_SPDIF_8CH 95 +-#define HCLK_AUDPWM 96 +-#define SCLK_AUDPWM_SRC 97 +-#define SCLK_AUDPWM_FRAC 98 +-#define SCLK_AUDPWM 99 +-#define HCLK_ACDCDIG 100 +-#define CLK_ACDCDIG_I2C 101 +-#define CLK_ACDCDIG_DAC 102 +-#define CLK_ACDCDIG_ADC 103 +-#define ACLK_SECURE_FLASH 104 +-#define HCLK_SECURE_FLASH 105 +-#define ACLK_CRYPTO_NS 106 +-#define HCLK_CRYPTO_NS 107 +-#define CLK_CRYPTO_NS_CORE 108 +-#define CLK_CRYPTO_NS_PKA 109 +-#define CLK_CRYPTO_NS_RNG 110 +-#define HCLK_TRNG_NS 111 +-#define CLK_TRNG_NS 112 +-#define PCLK_OTPC_NS 113 +-#define CLK_OTPC_NS_SBPI 114 +-#define CLK_OTPC_NS_USR 115 +-#define HCLK_NANDC 116 +-#define NCLK_NANDC 117 +-#define HCLK_SFC 118 +-#define HCLK_SFC_XIP 119 +-#define SCLK_SFC 120 +-#define ACLK_EMMC 121 +-#define HCLK_EMMC 122 +-#define BCLK_EMMC 123 +-#define CCLK_EMMC 124 +-#define TCLK_EMMC 125 +-#define ACLK_PIPE 126 +-#define PCLK_PIPE 127 +-#define PCLK_PIPE_GRF 128 +-#define ACLK_PCIE20_MST 129 +-#define ACLK_PCIE20_SLV 130 +-#define ACLK_PCIE20_DBI 131 +-#define PCLK_PCIE20 132 +-#define CLK_PCIE20_AUX_NDFT 133 +-#define CLK_PCIE20_AUX_DFT 134 +-#define CLK_PCIE20_PIPE_DFT 135 +-#define ACLK_PCIE30X1_MST 136 +-#define ACLK_PCIE30X1_SLV 137 +-#define ACLK_PCIE30X1_DBI 138 +-#define PCLK_PCIE30X1 139 +-#define CLK_PCIE30X1_AUX_NDFT 140 +-#define CLK_PCIE30X1_AUX_DFT 141 +-#define CLK_PCIE30X1_PIPE_DFT 142 +-#define ACLK_PCIE30X2_MST 143 +-#define ACLK_PCIE30X2_SLV 144 +-#define ACLK_PCIE30X2_DBI 145 +-#define PCLK_PCIE30X2 146 +-#define CLK_PCIE30X2_AUX_NDFT 147 +-#define CLK_PCIE30X2_AUX_DFT 148 +-#define CLK_PCIE30X2_PIPE_DFT 149 +-#define ACLK_SATA0 150 +-#define CLK_SATA0_PMALIVE 151 +-#define CLK_SATA0_RXOOB 152 +-#define CLK_SATA0_PIPE_NDFT 153 +-#define CLK_SATA0_PIPE_DFT 154 +-#define ACLK_SATA1 155 +-#define CLK_SATA1_PMALIVE 156 +-#define CLK_SATA1_RXOOB 157 +-#define CLK_SATA1_PIPE_NDFT 158 +-#define CLK_SATA1_PIPE_DFT 159 +-#define ACLK_SATA2 160 +-#define CLK_SATA2_PMALIVE 161 +-#define CLK_SATA2_RXOOB 162 +-#define CLK_SATA2_PIPE_NDFT 163 +-#define CLK_SATA2_PIPE_DFT 164 +-#define ACLK_USB3OTG0 165 +-#define CLK_USB3OTG0_REF 166 +-#define CLK_USB3OTG0_SUSPEND 167 +-#define ACLK_USB3OTG1 168 +-#define CLK_USB3OTG1_REF 169 +-#define CLK_USB3OTG1_SUSPEND 170 +-#define CLK_XPCS_EEE 171 +-#define PCLK_XPCS 172 +-#define ACLK_PHP 173 +-#define HCLK_PHP 174 +-#define PCLK_PHP 175 +-#define HCLK_SDMMC0 176 +-#define CLK_SDMMC0 177 +-#define HCLK_SDMMC1 178 +-#define CLK_SDMMC1 179 +-#define ACLK_GMAC0 180 +-#define PCLK_GMAC0 181 +-#define CLK_MAC0_2TOP 182 +-#define CLK_MAC0_OUT 183 +-#define CLK_MAC0_REFOUT 184 +-#define CLK_GMAC0_PTP_REF 185 +-#define ACLK_USB 186 +-#define HCLK_USB 187 +-#define PCLK_USB 188 +-#define HCLK_USB2HOST0 189 +-#define HCLK_USB2HOST0_ARB 190 +-#define HCLK_USB2HOST1 191 +-#define HCLK_USB2HOST1_ARB 192 +-#define HCLK_SDMMC2 193 +-#define CLK_SDMMC2 194 +-#define ACLK_GMAC1 195 +-#define PCLK_GMAC1 196 +-#define CLK_MAC1_2TOP 197 +-#define CLK_MAC1_OUT 198 +-#define CLK_MAC1_REFOUT 199 +-#define CLK_GMAC1_PTP_REF 200 +-#define ACLK_PERIMID 201 +-#define HCLK_PERIMID 202 +-#define ACLK_VI 203 +-#define HCLK_VI 204 +-#define PCLK_VI 205 +-#define ACLK_VICAP 206 +-#define HCLK_VICAP 207 +-#define DCLK_VICAP 208 +-#define ICLK_VICAP_G 209 +-#define ACLK_ISP 210 +-#define HCLK_ISP 211 +-#define CLK_ISP 212 +-#define PCLK_CSI2HOST1 213 +-#define CLK_CIF_OUT 214 +-#define CLK_CAM0_OUT 215 +-#define CLK_CAM1_OUT 216 +-#define ACLK_VO 217 +-#define HCLK_VO 218 +-#define PCLK_VO 219 +-#define ACLK_VOP_PRE 220 +-#define ACLK_VOP 221 +-#define HCLK_VOP 222 +-#define DCLK_VOP0 223 +-#define DCLK_VOP1 224 +-#define DCLK_VOP2 225 +-#define CLK_VOP_PWM 226 +-#define ACLK_HDCP 227 +-#define HCLK_HDCP 228 +-#define PCLK_HDCP 229 +-#define PCLK_HDMI_HOST 230 +-#define CLK_HDMI_SFR 231 +-#define PCLK_DSITX_0 232 +-#define PCLK_DSITX_1 233 +-#define PCLK_EDP_CTRL 234 +-#define CLK_EDP_200M 235 +-#define ACLK_VPU_PRE 236 +-#define HCLK_VPU_PRE 237 +-#define ACLK_VPU 238 +-#define HCLK_VPU 239 +-#define ACLK_RGA_PRE 240 +-#define HCLK_RGA_PRE 241 +-#define PCLK_RGA_PRE 242 +-#define ACLK_RGA 243 +-#define HCLK_RGA 244 +-#define CLK_RGA_CORE 245 +-#define ACLK_IEP 246 +-#define HCLK_IEP 247 +-#define CLK_IEP_CORE 248 +-#define HCLK_EBC 249 +-#define DCLK_EBC 250 +-#define ACLK_JDEC 251 +-#define HCLK_JDEC 252 +-#define ACLK_JENC 253 +-#define HCLK_JENC 254 +-#define PCLK_EINK 255 +-#define HCLK_EINK 256 +-#define ACLK_RKVENC_PRE 257 +-#define HCLK_RKVENC_PRE 258 +-#define ACLK_RKVENC 259 +-#define HCLK_RKVENC 260 +-#define CLK_RKVENC_CORE 261 +-#define ACLK_RKVDEC_PRE 262 +-#define HCLK_RKVDEC_PRE 263 +-#define ACLK_RKVDEC 264 +-#define HCLK_RKVDEC 265 +-#define CLK_RKVDEC_CA 266 +-#define CLK_RKVDEC_CORE 267 +-#define CLK_RKVDEC_HEVC_CA 268 +-#define ACLK_BUS 269 +-#define PCLK_BUS 270 +-#define PCLK_TSADC 271 +-#define CLK_TSADC_TSEN 272 +-#define CLK_TSADC 273 +-#define PCLK_SARADC 274 +-#define CLK_SARADC 275 +-#define PCLK_SCR 276 +-#define PCLK_WDT_NS 277 +-#define TCLK_WDT_NS 278 +-#define ACLK_DMAC0 279 +-#define ACLK_DMAC1 280 +-#define ACLK_MCU 281 +-#define PCLK_INTMUX 282 +-#define PCLK_MAILBOX 283 +-#define PCLK_UART1 284 +-#define CLK_UART1_SRC 285 +-#define CLK_UART1_FRAC 286 +-#define SCLK_UART1 287 +-#define PCLK_UART2 288 +-#define CLK_UART2_SRC 289 +-#define CLK_UART2_FRAC 290 +-#define SCLK_UART2 291 +-#define PCLK_UART3 292 +-#define CLK_UART3_SRC 293 +-#define CLK_UART3_FRAC 294 +-#define SCLK_UART3 295 +-#define PCLK_UART4 296 +-#define CLK_UART4_SRC 297 +-#define CLK_UART4_FRAC 298 +-#define SCLK_UART4 299 +-#define PCLK_UART5 300 +-#define CLK_UART5_SRC 301 +-#define CLK_UART5_FRAC 302 +-#define SCLK_UART5 303 +-#define PCLK_UART6 304 +-#define CLK_UART6_SRC 305 +-#define CLK_UART6_FRAC 306 +-#define SCLK_UART6 307 +-#define PCLK_UART7 308 +-#define CLK_UART7_SRC 309 +-#define CLK_UART7_FRAC 310 +-#define SCLK_UART7 311 +-#define PCLK_UART8 312 +-#define CLK_UART8_SRC 313 +-#define CLK_UART8_FRAC 314 +-#define SCLK_UART8 315 +-#define PCLK_UART9 316 +-#define CLK_UART9_SRC 317 +-#define CLK_UART9_FRAC 318 +-#define SCLK_UART9 319 +-#define PCLK_CAN0 320 +-#define CLK_CAN0 321 +-#define PCLK_CAN1 322 +-#define CLK_CAN1 323 +-#define PCLK_CAN2 324 +-#define CLK_CAN2 325 +-#define CLK_I2C 326 +-#define PCLK_I2C1 327 +-#define CLK_I2C1 328 +-#define PCLK_I2C2 329 +-#define CLK_I2C2 330 +-#define PCLK_I2C3 331 +-#define CLK_I2C3 332 +-#define PCLK_I2C4 333 +-#define CLK_I2C4 334 +-#define PCLK_I2C5 335 +-#define CLK_I2C5 336 +-#define PCLK_SPI0 337 +-#define CLK_SPI0 338 +-#define PCLK_SPI1 339 +-#define CLK_SPI1 340 +-#define PCLK_SPI2 341 +-#define CLK_SPI2 342 +-#define PCLK_SPI3 343 +-#define CLK_SPI3 344 +-#define PCLK_PWM1 345 +-#define CLK_PWM1 346 +-#define CLK_PWM1_CAPTURE 347 +-#define PCLK_PWM2 348 +-#define CLK_PWM2 349 +-#define CLK_PWM2_CAPTURE 350 +-#define PCLK_PWM3 351 +-#define CLK_PWM3 352 +-#define CLK_PWM3_CAPTURE 353 +-#define DBCLK_GPIO 354 +-#define PCLK_GPIO1 355 +-#define DBCLK_GPIO1 356 +-#define PCLK_GPIO2 357 +-#define DBCLK_GPIO2 358 +-#define PCLK_GPIO3 359 +-#define DBCLK_GPIO3 360 +-#define PCLK_GPIO4 361 +-#define DBCLK_GPIO4 362 +-#define OCC_SCAN_CLK_GPIO 363 +-#define PCLK_TIMER 364 +-#define CLK_TIMER0 365 +-#define CLK_TIMER1 366 +-#define CLK_TIMER2 367 +-#define CLK_TIMER3 368 +-#define CLK_TIMER4 369 +-#define CLK_TIMER5 370 +-#define ACLK_TOP_HIGH 371 +-#define ACLK_TOP_LOW 372 +-#define HCLK_TOP 373 +-#define PCLK_TOP 374 +-#define PCLK_PCIE30PHY 375 +-#define CLK_OPTC_ARB 376 +-#define PCLK_MIPICSIPHY 377 +-#define PCLK_MIPIDSIPHY0 378 +-#define PCLK_MIPIDSIPHY1 379 +-#define PCLK_PIPEPHY0 380 +-#define PCLK_PIPEPHY1 381 +-#define PCLK_PIPEPHY2 382 +-#define PCLK_CPU_BOOST 383 +-#define CLK_CPU_BOOST 384 +-#define PCLK_OTPPHY 385 +-#define SCLK_GMAC0 386 +-#define SCLK_GMAC0_RGMII_SPEED 387 +-#define SCLK_GMAC0_RMII_SPEED 388 +-#define SCLK_GMAC0_RX_TX 389 +-#define SCLK_GMAC1 390 +-#define SCLK_GMAC1_RGMII_SPEED 391 +-#define SCLK_GMAC1_RMII_SPEED 392 +-#define SCLK_GMAC1_RX_TX 393 +-#define SCLK_SDMMC0_DRV 394 +-#define SCLK_SDMMC0_SAMPLE 395 +-#define SCLK_SDMMC1_DRV 396 +-#define SCLK_SDMMC1_SAMPLE 397 +-#define SCLK_SDMMC2_DRV 398 +-#define SCLK_SDMMC2_SAMPLE 399 +-#define SCLK_EMMC_DRV 400 +-#define SCLK_EMMC_SAMPLE 401 +-#define PCLK_EDPPHY_GRF 402 +-#define CLK_HDMI_CEC 403 +-#define CLK_I2S0_8CH_TX 404 +-#define CLK_I2S0_8CH_RX 405 +-#define CLK_I2S1_8CH_TX 406 +-#define CLK_I2S1_8CH_RX 407 +-#define CLK_I2S2_2CH 408 +-#define CLK_I2S3_2CH_TX 409 +-#define CLK_I2S3_2CH_RX 410 +-#define CPLL_500M 411 +-#define CPLL_250M 412 +-#define CPLL_125M 413 +-#define CPLL_62P5M 414 +-#define CPLL_50M 415 +-#define CPLL_25M 416 +-#define CPLL_100M 417 +-#define SCLK_DDRCLK 418 +- +-#define PCLK_CORE_PVTM 450 +- +-#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1) +- +-/* pmu soft-reset indices */ +-/* pmucru_softrst_con0 */ +-#define SRST_P_PDPMU_NIU 0 +-#define SRST_P_PMUCRU 1 +-#define SRST_P_PMUGRF 2 +-#define SRST_P_I2C0 3 +-#define SRST_I2C0 4 +-#define SRST_P_UART0 5 +-#define SRST_S_UART0 6 +-#define SRST_P_PWM0 7 +-#define SRST_PWM0 8 +-#define SRST_P_GPIO0 9 +-#define SRST_GPIO0 10 +-#define SRST_P_PMUPVTM 11 +-#define SRST_PMUPVTM 12 +- +-/* soft-reset indices */ +- +-/* cru_softrst_con0 */ +-#define SRST_NCORERESET0 0 +-#define SRST_NCORERESET1 1 +-#define SRST_NCORERESET2 2 +-#define SRST_NCORERESET3 3 +-#define SRST_NCPUPORESET0 4 +-#define SRST_NCPUPORESET1 5 +-#define SRST_NCPUPORESET2 6 +-#define SRST_NCPUPORESET3 7 +-#define SRST_NSRESET 8 +-#define SRST_NSPORESET 9 +-#define SRST_NATRESET 10 +-#define SRST_NGICRESET 11 +-#define SRST_NPRESET 12 +-#define SRST_NPERIPHRESET 13 +- +-/* cru_softrst_con1 */ +-#define SRST_A_CORE_NIU2DDR 16 +-#define SRST_A_CORE_NIU2BUS 17 +-#define SRST_P_DBG_NIU 18 +-#define SRST_P_DBG 19 +-#define SRST_P_DBG_DAPLITE 20 +-#define SRST_DAP 21 +-#define SRST_A_ADB400_CORE2GIC 22 +-#define SRST_A_ADB400_GIC2CORE 23 +-#define SRST_P_CORE_GRF 24 +-#define SRST_P_CORE_PVTM 25 +-#define SRST_CORE_PVTM 26 +-#define SRST_CORE_PVTPLL 27 +- +-/* cru_softrst_con2 */ +-#define SRST_GPU 32 +-#define SRST_A_GPU_NIU 33 +-#define SRST_P_GPU_NIU 34 +-#define SRST_P_GPU_PVTM 35 +-#define SRST_GPU_PVTM 36 +-#define SRST_GPU_PVTPLL 37 +-#define SRST_A_NPU_NIU 40 +-#define SRST_H_NPU_NIU 41 +-#define SRST_P_NPU_NIU 42 +-#define SRST_A_NPU 43 +-#define SRST_H_NPU 44 +-#define SRST_P_NPU_PVTM 45 +-#define SRST_NPU_PVTM 46 +-#define SRST_NPU_PVTPLL 47 +- +-/* cru_softrst_con3 */ +-#define SRST_A_MSCH 51 +-#define SRST_HWFFC_CTRL 52 +-#define SRST_DDR_ALWAYSON 53 +-#define SRST_A_DDRSPLIT 54 +-#define SRST_DDRDFI_CTL 55 +-#define SRST_A_DMA2DDR 57 +- +-/* cru_softrst_con4 */ +-#define SRST_A_PERIMID_NIU 64 +-#define SRST_H_PERIMID_NIU 65 +-#define SRST_A_GIC_AUDIO_NIU 66 +-#define SRST_H_GIC_AUDIO_NIU 67 +-#define SRST_A_GIC600 68 +-#define SRST_A_GIC600_DEBUG 69 +-#define SRST_A_GICADB_CORE2GIC 70 +-#define SRST_A_GICADB_GIC2CORE 71 +-#define SRST_A_SPINLOCK 72 +-#define SRST_H_SDMMC_BUFFER 73 +-#define SRST_D_SDMMC_BUFFER 74 +-#define SRST_H_I2S0_8CH 75 +-#define SRST_H_I2S1_8CH 76 +-#define SRST_H_I2S2_2CH 77 +-#define SRST_H_I2S3_2CH 78 +- +-/* cru_softrst_con5 */ +-#define SRST_M_I2S0_8CH_TX 80 +-#define SRST_M_I2S0_8CH_RX 81 +-#define SRST_M_I2S1_8CH_TX 82 +-#define SRST_M_I2S1_8CH_RX 83 +-#define SRST_M_I2S2_2CH 84 +-#define SRST_M_I2S3_2CH_TX 85 +-#define SRST_M_I2S3_2CH_RX 86 +-#define SRST_H_PDM 87 +-#define SRST_M_PDM 88 +-#define SRST_H_VAD 89 +-#define SRST_H_SPDIF_8CH 90 +-#define SRST_M_SPDIF_8CH 91 +-#define SRST_H_AUDPWM 92 +-#define SRST_S_AUDPWM 93 +-#define SRST_H_ACDCDIG 94 +-#define SRST_ACDCDIG 95 +- +-/* cru_softrst_con6 */ +-#define SRST_A_SECURE_FLASH_NIU 96 +-#define SRST_H_SECURE_FLASH_NIU 97 +-#define SRST_A_CRYPTO_NS 103 +-#define SRST_H_CRYPTO_NS 104 +-#define SRST_CRYPTO_NS_CORE 105 +-#define SRST_CRYPTO_NS_PKA 106 +-#define SRST_CRYPTO_NS_RNG 107 +-#define SRST_H_TRNG_NS 108 +-#define SRST_TRNG_NS 109 +- +-/* cru_softrst_con7 */ +-#define SRST_H_NANDC 112 +-#define SRST_N_NANDC 113 +-#define SRST_H_SFC 114 +-#define SRST_H_SFC_XIP 115 +-#define SRST_S_SFC 116 +-#define SRST_A_EMMC 117 +-#define SRST_H_EMMC 118 +-#define SRST_B_EMMC 119 +-#define SRST_C_EMMC 120 +-#define SRST_T_EMMC 121 +- +-/* cru_softrst_con8 */ +-#define SRST_A_PIPE_NIU 128 +-#define SRST_P_PIPE_NIU 130 +-#define SRST_P_PIPE_GRF 133 +-#define SRST_A_SATA0 134 +-#define SRST_SATA0_PIPE 135 +-#define SRST_SATA0_PMALIVE 136 +-#define SRST_SATA0_RXOOB 137 +-#define SRST_A_SATA1 138 +-#define SRST_SATA1_PIPE 139 +-#define SRST_SATA1_PMALIVE 140 +-#define SRST_SATA1_RXOOB 141 +- +-/* cru_softrst_con9 */ +-#define SRST_A_SATA2 144 +-#define SRST_SATA2_PIPE 145 +-#define SRST_SATA2_PMALIVE 146 +-#define SRST_SATA2_RXOOB 147 +-#define SRST_USB3OTG0 148 +-#define SRST_USB3OTG1 149 +-#define SRST_XPCS 150 +-#define SRST_XPCS_TX_DIV10 151 +-#define SRST_XPCS_RX_DIV10 152 +-#define SRST_XPCS_XGXS_RX 153 +- +-/* cru_softrst_con10 */ +-#define SRST_P_PCIE20 160 +-#define SRST_PCIE20_POWERUP 161 +-#define SRST_MSTR_ARESET_PCIE20 162 +-#define SRST_SLV_ARESET_PCIE20 163 +-#define SRST_DBI_ARESET_PCIE20 164 +-#define SRST_BRESET_PCIE20 165 +-#define SRST_PERST_PCIE20 166 +-#define SRST_CORE_RST_PCIE20 167 +-#define SRST_NSTICKY_RST_PCIE20 168 +-#define SRST_STICKY_RST_PCIE20 169 +-#define SRST_PWR_RST_PCIE20 170 +- +-/* cru_softrst_con11 */ +-#define SRST_P_PCIE30X1 176 +-#define SRST_PCIE30X1_POWERUP 177 +-#define SRST_M_ARESET_PCIE30X1 178 +-#define SRST_S_ARESET_PCIE30X1 179 +-#define SRST_D_ARESET_PCIE30X1 180 +-#define SRST_BRESET_PCIE30X1 181 +-#define SRST_PERST_PCIE30X1 182 +-#define SRST_CORE_RST_PCIE30X1 183 +-#define SRST_NSTC_RST_PCIE30X1 184 +-#define SRST_STC_RST_PCIE30X1 185 +-#define SRST_PWR_RST_PCIE30X1 186 +- +-/* cru_softrst_con12 */ +-#define SRST_P_PCIE30X2 192 +-#define SRST_PCIE30X2_POWERUP 193 +-#define SRST_M_ARESET_PCIE30X2 194 +-#define SRST_S_ARESET_PCIE30X2 195 +-#define SRST_D_ARESET_PCIE30X2 196 +-#define SRST_BRESET_PCIE30X2 197 +-#define SRST_PERST_PCIE30X2 198 +-#define SRST_CORE_RST_PCIE30X2 199 +-#define SRST_NSTC_RST_PCIE30X2 200 +-#define SRST_STC_RST_PCIE30X2 201 +-#define SRST_PWR_RST_PCIE30X2 202 +- +-/* cru_softrst_con13 */ +-#define SRST_A_PHP_NIU 208 +-#define SRST_H_PHP_NIU 209 +-#define SRST_P_PHP_NIU 210 +-#define SRST_H_SDMMC0 211 +-#define SRST_SDMMC0 212 +-#define SRST_H_SDMMC1 213 +-#define SRST_SDMMC1 214 +-#define SRST_A_GMAC0 215 +-#define SRST_GMAC0_TIMESTAMP 216 +- +-/* cru_softrst_con14 */ +-#define SRST_A_USB_NIU 224 +-#define SRST_H_USB_NIU 225 +-#define SRST_P_USB_NIU 226 +-#define SRST_P_USB_GRF 227 +-#define SRST_H_USB2HOST0 228 +-#define SRST_H_USB2HOST0_ARB 229 +-#define SRST_USB2HOST0_UTMI 230 +-#define SRST_H_USB2HOST1 231 +-#define SRST_H_USB2HOST1_ARB 232 +-#define SRST_USB2HOST1_UTMI 233 +-#define SRST_H_SDMMC2 234 +-#define SRST_SDMMC2 235 +-#define SRST_A_GMAC1 236 +-#define SRST_GMAC1_TIMESTAMP 237 +- +-/* cru_softrst_con15 */ +-#define SRST_A_VI_NIU 240 +-#define SRST_H_VI_NIU 241 +-#define SRST_P_VI_NIU 242 +-#define SRST_A_VICAP 247 +-#define SRST_H_VICAP 248 +-#define SRST_D_VICAP 249 +-#define SRST_I_VICAP 250 +-#define SRST_P_VICAP 251 +-#define SRST_H_ISP 252 +-#define SRST_ISP 253 +-#define SRST_P_CSI2HOST1 255 +- +-/* cru_softrst_con16 */ +-#define SRST_A_VO_NIU 256 +-#define SRST_H_VO_NIU 257 +-#define SRST_P_VO_NIU 258 +-#define SRST_A_VOP_NIU 259 +-#define SRST_A_VOP 260 +-#define SRST_H_VOP 261 +-#define SRST_VOP0 262 +-#define SRST_VOP1 263 +-#define SRST_VOP2 264 +-#define SRST_VOP_PWM 265 +-#define SRST_A_HDCP 266 +-#define SRST_H_HDCP 267 +-#define SRST_P_HDCP 268 +-#define SRST_P_HDMI_HOST 270 +-#define SRST_HDMI_HOST 271 +- +-/* cru_softrst_con17 */ +-#define SRST_P_DSITX_0 272 +-#define SRST_P_DSITX_1 273 +-#define SRST_P_EDP_CTRL 274 +-#define SRST_EDP_24M 275 +-#define SRST_A_VPU_NIU 280 +-#define SRST_H_VPU_NIU 281 +-#define SRST_A_VPU 282 +-#define SRST_H_VPU 283 +-#define SRST_H_EINK 286 +-#define SRST_P_EINK 287 +- +-/* cru_softrst_con18 */ +-#define SRST_A_RGA_NIU 288 +-#define SRST_H_RGA_NIU 289 +-#define SRST_P_RGA_NIU 290 +-#define SRST_A_RGA 292 +-#define SRST_H_RGA 293 +-#define SRST_RGA_CORE 294 +-#define SRST_A_IEP 295 +-#define SRST_H_IEP 296 +-#define SRST_IEP_CORE 297 +-#define SRST_H_EBC 298 +-#define SRST_D_EBC 299 +-#define SRST_A_JDEC 300 +-#define SRST_H_JDEC 301 +-#define SRST_A_JENC 302 +-#define SRST_H_JENC 303 +- +-/* cru_softrst_con19 */ +-#define SRST_A_VENC_NIU 304 +-#define SRST_H_VENC_NIU 305 +-#define SRST_A_RKVENC 307 +-#define SRST_H_RKVENC 308 +-#define SRST_RKVENC_CORE 309 +- +-/* cru_softrst_con20 */ +-#define SRST_A_RKVDEC_NIU 320 +-#define SRST_H_RKVDEC_NIU 321 +-#define SRST_A_RKVDEC 322 +-#define SRST_H_RKVDEC 323 +-#define SRST_RKVDEC_CA 324 +-#define SRST_RKVDEC_CORE 325 +-#define SRST_RKVDEC_HEVC_CA 326 +- +-/* cru_softrst_con21 */ +-#define SRST_A_BUS_NIU 336 +-#define SRST_P_BUS_NIU 338 +-#define SRST_P_CAN0 340 +-#define SRST_CAN0 341 +-#define SRST_P_CAN1 342 +-#define SRST_CAN1 343 +-#define SRST_P_CAN2 344 +-#define SRST_CAN2 345 +-#define SRST_P_GPIO1 346 +-#define SRST_GPIO1 347 +-#define SRST_P_GPIO2 348 +-#define SRST_GPIO2 349 +-#define SRST_P_GPIO3 350 +-#define SRST_GPIO3 351 +- +-/* cru_softrst_con22 */ +-#define SRST_P_GPIO4 352 +-#define SRST_GPIO4 353 +-#define SRST_P_I2C1 354 +-#define SRST_I2C1 355 +-#define SRST_P_I2C2 356 +-#define SRST_I2C2 357 +-#define SRST_P_I2C3 358 +-#define SRST_I2C3 359 +-#define SRST_P_I2C4 360 +-#define SRST_I2C4 361 +-#define SRST_P_I2C5 362 +-#define SRST_I2C5 363 +-#define SRST_P_OTPC_NS 364 +-#define SRST_OTPC_NS_SBPI 365 +-#define SRST_OTPC_NS_USR 366 +- +-/* cru_softrst_con23 */ +-#define SRST_P_PWM1 368 +-#define SRST_PWM1 369 +-#define SRST_P_PWM2 370 +-#define SRST_PWM2 371 +-#define SRST_P_PWM3 372 +-#define SRST_PWM3 373 +-#define SRST_P_SPI0 374 +-#define SRST_SPI0 375 +-#define SRST_P_SPI1 376 +-#define SRST_SPI1 377 +-#define SRST_P_SPI2 378 +-#define SRST_SPI2 379 +-#define SRST_P_SPI3 380 +-#define SRST_SPI3 381 +- +-/* cru_softrst_con24 */ +-#define SRST_P_SARADC 384 +-#define SRST_P_TSADC 385 +-#define SRST_TSADC 386 +-#define SRST_P_TIMER 387 +-#define SRST_TIMER0 388 +-#define SRST_TIMER1 389 +-#define SRST_TIMER2 390 +-#define SRST_TIMER3 391 +-#define SRST_TIMER4 392 +-#define SRST_TIMER5 393 +-#define SRST_P_UART1 394 +-#define SRST_S_UART1 395 +- +-/* cru_softrst_con25 */ +-#define SRST_P_UART2 400 +-#define SRST_S_UART2 401 +-#define SRST_P_UART3 402 +-#define SRST_S_UART3 403 +-#define SRST_P_UART4 404 +-#define SRST_S_UART4 405 +-#define SRST_P_UART5 406 +-#define SRST_S_UART5 407 +-#define SRST_P_UART6 408 +-#define SRST_S_UART6 409 +-#define SRST_P_UART7 410 +-#define SRST_S_UART7 411 +-#define SRST_P_UART8 412 +-#define SRST_S_UART8 413 +-#define SRST_P_UART9 414 +-#define SRST_S_UART9 415 +- +-/* cru_softrst_con26 */ +-#define SRST_P_GRF 416 +-#define SRST_P_GRF_VCCIO12 417 +-#define SRST_P_GRF_VCCIO34 418 +-#define SRST_P_GRF_VCCIO567 419 +-#define SRST_P_SCR 420 +-#define SRST_P_WDT_NS 421 +-#define SRST_T_WDT_NS 422 +-#define SRST_P_DFT2APB 423 +-#define SRST_A_MCU 426 +-#define SRST_P_INTMUX 427 +-#define SRST_P_MAILBOX 428 +- +-/* cru_softrst_con27 */ +-#define SRST_A_TOP_HIGH_NIU 432 +-#define SRST_A_TOP_LOW_NIU 433 +-#define SRST_H_TOP_NIU 434 +-#define SRST_P_TOP_NIU 435 +-#define SRST_P_TOP_CRU 438 +-#define SRST_P_DDRPHY 439 +-#define SRST_DDRPHY 440 +-#define SRST_P_MIPICSIPHY 442 +-#define SRST_P_MIPIDSIPHY0 443 +-#define SRST_P_MIPIDSIPHY1 444 +-#define SRST_P_PCIE30PHY 445 +-#define SRST_PCIE30PHY 446 +-#define SRST_P_PCIE30PHY_GRF 447 +- +-/* cru_softrst_con28 */ +-#define SRST_P_APB2ASB_LEFT 448 +-#define SRST_P_APB2ASB_BOTTOM 449 +-#define SRST_P_ASB2APB_LEFT 450 +-#define SRST_P_ASB2APB_BOTTOM 451 +-#define SRST_P_PIPEPHY0 452 +-#define SRST_PIPEPHY0 453 +-#define SRST_P_PIPEPHY1 454 +-#define SRST_PIPEPHY1 455 +-#define SRST_P_PIPEPHY2 456 +-#define SRST_PIPEPHY2 457 +-#define SRST_P_USB2PHY0_GRF 458 +-#define SRST_P_USB2PHY1_GRF 459 +-#define SRST_P_CPU_BOOST 460 +-#define SRST_CPU_BOOST 461 +-#define SRST_P_OTPPHY 462 +-#define SRST_OTPPHY 463 +- +-/* cru_softrst_con29 */ +-#define SRST_USB2PHY0_POR 464 +-#define SRST_USB2PHY0_USB3OTG0 465 +-#define SRST_USB2PHY0_USB3OTG1 466 +-#define SRST_USB2PHY1_POR 467 +-#define SRST_USB2PHY1_USB2HOST0 468 +-#define SRST_USB2PHY1_USB2HOST1 469 +-#define SRST_P_EDPPHY_GRF 470 +-#define SRST_TSADCPHY 471 +-#define SRST_GMAC0_DELAYLINE 472 +-#define SRST_GMAC1_DELAYLINE 473 +-#define SRST_OTPC_ARB 474 +-#define SRST_P_PIPEPHY0_GRF 475 +-#define SRST_P_PIPEPHY1_GRF 476 +-#define SRST_P_PIPEPHY2_GRF 477 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/rockchip,rk808.h b/scripts/dtc/include-prefixes/dt-bindings/clock/rockchip,rk808.h +deleted file mode 100644 +index 75dabfc6adc1..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/rockchip,rk808.h ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants clk index RK808 pmic clkout +- */ +-#ifndef _CLK_ROCKCHIP_RK808 +-#define _CLK_ROCKCHIP_RK808 +- +-/* CLOCKOUT index */ +-#define RK808_CLKOUT0 0 +-#define RK808_CLKOUT1 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/rv1108-cru.h b/scripts/dtc/include-prefixes/dt-bindings/clock/rv1108-cru.h +deleted file mode 100644 +index 41d7d6080ea7..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/rv1108-cru.h ++++ /dev/null +@@ -1,353 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright (c) 2016 Rockchip Electronics Co. Ltd. +- * Author: Shawn Lin +- */ +- +-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H +-#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H +- +-/* pll id */ +-#define PLL_APLL 0 +-#define PLL_DPLL 1 +-#define PLL_GPLL 2 +-#define ARMCLK 3 +- +-/* sclk gates (special clocks) */ +-#define SCLK_SPI0 65 +-#define SCLK_NANDC 67 +-#define SCLK_SDMMC 68 +-#define SCLK_SDIO 69 +-#define SCLK_EMMC 71 +-#define SCLK_UART0 72 +-#define SCLK_UART1 73 +-#define SCLK_UART2 74 +-#define SCLK_I2S0 75 +-#define SCLK_I2S1 76 +-#define SCLK_I2S2 77 +-#define SCLK_TIMER0 78 +-#define SCLK_TIMER1 79 +-#define SCLK_SFC 80 +-#define SCLK_SDMMC_DRV 81 +-#define SCLK_SDIO_DRV 82 +-#define SCLK_EMMC_DRV 83 +-#define SCLK_SDMMC_SAMPLE 84 +-#define SCLK_SDIO_SAMPLE 85 +-#define SCLK_EMMC_SAMPLE 86 +-#define SCLK_VENC_CORE 87 +-#define SCLK_HEVC_CORE 88 +-#define SCLK_HEVC_CABAC 89 +-#define SCLK_PWM0_PMU 90 +-#define SCLK_I2C0_PMU 91 +-#define SCLK_WIFI 92 +-#define SCLK_CIFOUT 93 +-#define SCLK_MIPI_CSI_OUT 94 +-#define SCLK_CIF0 95 +-#define SCLK_CIF1 96 +-#define SCLK_CIF2 97 +-#define SCLK_CIF3 98 +-#define SCLK_DSP 99 +-#define SCLK_DSP_IOP 100 +-#define SCLK_DSP_EPP 101 +-#define SCLK_DSP_EDP 102 +-#define SCLK_DSP_EDAP 103 +-#define SCLK_CVBS_HOST 104 +-#define SCLK_HDMI_SFR 105 +-#define SCLK_HDMI_CEC 106 +-#define SCLK_CRYPTO 107 +-#define SCLK_SPI 108 +-#define SCLK_SARADC 109 +-#define SCLK_TSADC 110 +-#define SCLK_MAC_PRE 111 +-#define SCLK_MAC 112 +-#define SCLK_MAC_RX 113 +-#define SCLK_MAC_REF 114 +-#define SCLK_MAC_REFOUT 115 +-#define SCLK_DSP_PFM 116 +-#define SCLK_RGA 117 +-#define SCLK_I2C1 118 +-#define SCLK_I2C2 119 +-#define SCLK_I2C3 120 +-#define SCLK_PWM 121 +-#define SCLK_ISP 122 +-#define SCLK_USBPHY 123 +-#define SCLK_I2S0_SRC 124 +-#define SCLK_I2S1_SRC 125 +-#define SCLK_I2S2_SRC 126 +-#define SCLK_UART0_SRC 127 +-#define SCLK_UART1_SRC 128 +-#define SCLK_UART2_SRC 129 +- +-#define DCLK_VOP_SRC 185 +-#define DCLK_HDMIPHY 186 +-#define DCLK_VOP 187 +- +-/* aclk gates */ +-#define ACLK_DMAC 192 +-#define ACLK_PRE 193 +-#define ACLK_CORE 194 +-#define ACLK_ENMCORE 195 +-#define ACLK_RKVENC 196 +-#define ACLK_RKVDEC 197 +-#define ACLK_VPU 198 +-#define ACLK_CIF0 199 +-#define ACLK_VIO0 200 +-#define ACLK_VIO1 201 +-#define ACLK_VOP 202 +-#define ACLK_IEP 203 +-#define ACLK_RGA 204 +-#define ACLK_ISP 205 +-#define ACLK_CIF1 206 +-#define ACLK_CIF2 207 +-#define ACLK_CIF3 208 +-#define ACLK_PERI 209 +-#define ACLK_GMAC 210 +- +-/* pclk gates */ +-#define PCLK_GPIO1 256 +-#define PCLK_GPIO2 257 +-#define PCLK_GPIO3 258 +-#define PCLK_GRF 259 +-#define PCLK_I2C1 260 +-#define PCLK_I2C2 261 +-#define PCLK_I2C3 262 +-#define PCLK_SPI 263 +-#define PCLK_SFC 264 +-#define PCLK_UART0 265 +-#define PCLK_UART1 266 +-#define PCLK_UART2 267 +-#define PCLK_TSADC 268 +-#define PCLK_PWM 269 +-#define PCLK_TIMER 270 +-#define PCLK_PERI 271 +-#define PCLK_GPIO0_PMU 272 +-#define PCLK_I2C0_PMU 273 +-#define PCLK_PWM0_PMU 274 +-#define PCLK_ISP 275 +-#define PCLK_VIO 276 +-#define PCLK_MIPI_DSI 277 +-#define PCLK_HDMI_CTRL 278 +-#define PCLK_SARADC 279 +-#define PCLK_DSP_CFG 280 +-#define PCLK_BUS 281 +-#define PCLK_EFUSE0 282 +-#define PCLK_EFUSE1 283 +-#define PCLK_WDT 284 +-#define PCLK_GMAC 285 +- +-/* hclk gates */ +-#define HCLK_I2S0_8CH 320 +-#define HCLK_I2S1_2CH 321 +-#define HCLK_I2S2_2CH 322 +-#define HCLK_NANDC 323 +-#define HCLK_SDMMC 324 +-#define HCLK_SDIO 325 +-#define HCLK_EMMC 326 +-#define HCLK_PERI 327 +-#define HCLK_SFC 328 +-#define HCLK_RKVENC 329 +-#define HCLK_RKVDEC 330 +-#define HCLK_CIF0 331 +-#define HCLK_VIO 332 +-#define HCLK_VOP 333 +-#define HCLK_IEP 334 +-#define HCLK_RGA 335 +-#define HCLK_ISP 336 +-#define HCLK_CRYPTO_MST 337 +-#define HCLK_CRYPTO_SLV 338 +-#define HCLK_HOST0 339 +-#define HCLK_OTG 340 +-#define HCLK_CIF1 341 +-#define HCLK_CIF2 342 +-#define HCLK_CIF3 343 +-#define HCLK_BUS 344 +-#define HCLK_VPU 345 +- +-#define CLK_NR_CLKS (HCLK_VPU + 1) +- +-/* reset id */ +-#define SRST_CORE_PO_AD 0 +-#define SRST_CORE_AD 1 +-#define SRST_L2_AD 2 +-#define SRST_CPU_NIU_AD 3 +-#define SRST_CORE_PO 4 +-#define SRST_CORE 5 +-#define SRST_L2 6 +-#define SRST_CORE_DBG 8 +-#define PRST_DBG 9 +-#define RST_DAP 10 +-#define PRST_DBG_NIU 11 +-#define ARST_STRC_SYS_AD 15 +- +-#define SRST_DDRPHY_CLKDIV 16 +-#define SRST_DDRPHY 17 +-#define PRST_DDRPHY 18 +-#define PRST_HDMIPHY 19 +-#define PRST_VDACPHY 20 +-#define PRST_VADCPHY 21 +-#define PRST_MIPI_CSI_PHY 22 +-#define PRST_MIPI_DSI_PHY 23 +-#define PRST_ACODEC 24 +-#define ARST_BUS_NIU 25 +-#define PRST_TOP_NIU 26 +-#define ARST_INTMEM 27 +-#define HRST_ROM 28 +-#define ARST_DMAC 29 +-#define SRST_MSCH_NIU 30 +-#define PRST_MSCH_NIU 31 +- +-#define PRST_DDRUPCTL 32 +-#define NRST_DDRUPCTL 33 +-#define PRST_DDRMON 34 +-#define HRST_I2S0_8CH 35 +-#define MRST_I2S0_8CH 36 +-#define HRST_I2S1_2CH 37 +-#define MRST_IS21_2CH 38 +-#define HRST_I2S2_2CH 39 +-#define MRST_I2S2_2CH 40 +-#define HRST_CRYPTO 41 +-#define SRST_CRYPTO 42 +-#define PRST_SPI 43 +-#define SRST_SPI 44 +-#define PRST_UART0 45 +-#define PRST_UART1 46 +-#define PRST_UART2 47 +- +-#define SRST_UART0 48 +-#define SRST_UART1 49 +-#define SRST_UART2 50 +-#define PRST_I2C1 51 +-#define PRST_I2C2 52 +-#define PRST_I2C3 53 +-#define SRST_I2C1 54 +-#define SRST_I2C2 55 +-#define SRST_I2C3 56 +-#define PRST_PWM1 58 +-#define SRST_PWM1 60 +-#define PRST_WDT 61 +-#define PRST_GPIO1 62 +-#define PRST_GPIO2 63 +- +-#define PRST_GPIO3 64 +-#define PRST_GRF 65 +-#define PRST_EFUSE 66 +-#define PRST_EFUSE512 67 +-#define PRST_TIMER0 68 +-#define SRST_TIMER0 69 +-#define SRST_TIMER1 70 +-#define PRST_TSADC 71 +-#define SRST_TSADC 72 +-#define PRST_SARADC 73 +-#define SRST_SARADC 74 +-#define HRST_SYSBUS 75 +-#define PRST_USBGRF 76 +- +-#define ARST_PERIPH_NIU 80 +-#define HRST_PERIPH_NIU 81 +-#define PRST_PERIPH_NIU 82 +-#define HRST_PERIPH 83 +-#define HRST_SDMMC 84 +-#define HRST_SDIO 85 +-#define HRST_EMMC 86 +-#define HRST_NANDC 87 +-#define NRST_NANDC 88 +-#define HRST_SFC 89 +-#define SRST_SFC 90 +-#define ARST_GMAC 91 +-#define HRST_OTG 92 +-#define SRST_OTG 93 +-#define SRST_OTG_ADP 94 +-#define HRST_HOST0 95 +- +-#define HRST_HOST0_AUX 96 +-#define HRST_HOST0_ARB 97 +-#define SRST_HOST0_EHCIPHY 98 +-#define SRST_HOST0_UTMI 99 +-#define SRST_USBPOR 100 +-#define SRST_UTMI0 101 +-#define SRST_UTMI1 102 +- +-#define ARST_VIO0_NIU 102 +-#define ARST_VIO1_NIU 103 +-#define HRST_VIO_NIU 104 +-#define PRST_VIO_NIU 105 +-#define ARST_VOP 106 +-#define HRST_VOP 107 +-#define DRST_VOP 108 +-#define ARST_IEP 109 +-#define HRST_IEP 110 +-#define ARST_RGA 111 +-#define HRST_RGA 112 +-#define SRST_RGA 113 +-#define PRST_CVBS 114 +-#define PRST_HDMI 115 +-#define SRST_HDMI 116 +-#define PRST_MIPI_DSI 117 +- +-#define ARST_ISP_NIU 118 +-#define HRST_ISP_NIU 119 +-#define HRST_ISP 120 +-#define SRST_ISP 121 +-#define ARST_VIP0 122 +-#define HRST_VIP0 123 +-#define PRST_VIP0 124 +-#define ARST_VIP1 125 +-#define HRST_VIP1 126 +-#define PRST_VIP1 127 +-#define ARST_VIP2 128 +-#define HRST_VIP2 129 +-#define PRST_VIP2 120 +-#define ARST_VIP3 121 +-#define HRST_VIP3 122 +-#define PRST_VIP4 123 +- +-#define PRST_CIF1TO4 124 +-#define SRST_CVBS_CLK 125 +-#define HRST_CVBS 126 +- +-#define ARST_VPU_NIU 140 +-#define HRST_VPU_NIU 141 +-#define ARST_VPU 142 +-#define HRST_VPU 143 +-#define ARST_RKVDEC_NIU 144 +-#define HRST_RKVDEC_NIU 145 +-#define ARST_RKVDEC 146 +-#define HRST_RKVDEC 147 +-#define SRST_RKVDEC_CABAC 148 +-#define SRST_RKVDEC_CORE 149 +-#define ARST_RKVENC_NIU 150 +-#define HRST_RKVENC_NIU 151 +-#define ARST_RKVENC 152 +-#define HRST_RKVENC 153 +-#define SRST_RKVENC_CORE 154 +- +-#define SRST_DSP_CORE 156 +-#define SRST_DSP_SYS 157 +-#define SRST_DSP_GLOBAL 158 +-#define SRST_DSP_OECM 159 +-#define PRST_DSP_IOP_NIU 160 +-#define ARST_DSP_EPP_NIU 161 +-#define ARST_DSP_EDP_NIU 162 +-#define PRST_DSP_DBG_NIU 163 +-#define PRST_DSP_CFG_NIU 164 +-#define PRST_DSP_GRF 165 +-#define PRST_DSP_MAILBOX 166 +-#define PRST_DSP_INTC 167 +-#define PRST_DSP_PFM_MON 169 +-#define SRST_DSP_PFM_MON 170 +-#define ARST_DSP_EDAP_NIU 171 +- +-#define SRST_PMU 172 +-#define SRST_PMU_I2C0 173 +-#define PRST_PMU_I2C0 174 +-#define PRST_PMU_GPIO0 175 +-#define PRST_PMU_INTMEM 176 +-#define PRST_PMU_PWM0 177 +-#define SRST_PMU_PWM0 178 +-#define PRST_PMU_GRF 179 +-#define SRST_PMU_NIU 180 +-#define SRST_PMU_PVTM 181 +-#define ARST_DSP_EDP_PERF 184 +-#define ARST_DSP_EPP_PERF 185 +- +-#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/s3c2410.h b/scripts/dtc/include-prefixes/dt-bindings/clock/s3c2410.h +deleted file mode 100644 +index 0fb65c3f2f59..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/s3c2410.h ++++ /dev/null +@@ -1,59 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2013 Heiko Stuebner +- * +- * Device Tree binding constants clock controllers of Samsung S3C2410 and later. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H +-#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H +- +-/* +- * Let each exported clock get a unique index, which is used on DT-enabled +- * platforms to lookup the clock from a clock specifier. These indices are +- * therefore considered an ABI and so must not be changed. This implies +- * that new clocks should be added either in free spaces between clock groups +- * or at the end. +- */ +- +-/* Core clocks. */ +- +-/* id 1 is reserved */ +-#define MPLL 2 +-#define UPLL 3 +-#define FCLK 4 +-#define HCLK 5 +-#define PCLK 6 +-#define UCLK 7 +-#define ARMCLK 8 +- +-/* pclk-gates */ +-#define PCLK_UART0 16 +-#define PCLK_UART1 17 +-#define PCLK_UART2 18 +-#define PCLK_I2C 19 +-#define PCLK_SDI 20 +-#define PCLK_SPI 21 +-#define PCLK_ADC 22 +-#define PCLK_AC97 23 +-#define PCLK_I2S 24 +-#define PCLK_PWM 25 +-#define PCLK_RTC 26 +-#define PCLK_GPIO 27 +- +- +-/* hclk-gates */ +-#define HCLK_LCD 32 +-#define HCLK_USBH 33 +-#define HCLK_USBD 34 +-#define HCLK_NAND 35 +-#define HCLK_CAM 36 +- +- +-#define CAMIF 40 +- +- +-/* Total number of clocks. */ +-#define NR_CLKS (CAMIF + 1) +- +-#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/s3c2412.h b/scripts/dtc/include-prefixes/dt-bindings/clock/s3c2412.h +deleted file mode 100644 +index b4656156cc0f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/s3c2412.h ++++ /dev/null +@@ -1,70 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2013 Heiko Stuebner +- * +- * Device Tree binding constants clock controllers of Samsung S3C2412. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H +-#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H +- +-/* +- * Let each exported clock get a unique index, which is used on DT-enabled +- * platforms to lookup the clock from a clock specifier. These indices are +- * therefore considered an ABI and so must not be changed. This implies +- * that new clocks should be added either in free spaces between clock groups +- * or at the end. +- */ +- +-/* Core clocks. */ +- +-/* id 1 is reserved */ +-#define MPLL 2 +-#define UPLL 3 +-#define MDIVCLK 4 +-#define MSYSCLK 5 +-#define USYSCLK 6 +-#define HCLK 7 +-#define PCLK 8 +-#define ARMDIV 9 +-#define ARMCLK 10 +- +- +-/* Special clocks */ +-#define SCLK_CAM 16 +-#define SCLK_UART 17 +-#define SCLK_I2S 18 +-#define SCLK_USBD 19 +-#define SCLK_USBH 20 +- +-/* pclk-gates */ +-#define PCLK_WDT 32 +-#define PCLK_SPI 33 +-#define PCLK_I2S 34 +-#define PCLK_I2C 35 +-#define PCLK_ADC 36 +-#define PCLK_RTC 37 +-#define PCLK_GPIO 38 +-#define PCLK_UART2 39 +-#define PCLK_UART1 40 +-#define PCLK_UART0 41 +-#define PCLK_SDI 42 +-#define PCLK_PWM 43 +-#define PCLK_USBD 44 +- +-/* hclk-gates */ +-#define HCLK_HALF 48 +-#define HCLK_X2 49 +-#define HCLK_SDRAM 50 +-#define HCLK_USBH 51 +-#define HCLK_LCD 52 +-#define HCLK_NAND 53 +-#define HCLK_DMA3 54 +-#define HCLK_DMA2 55 +-#define HCLK_DMA1 56 +-#define HCLK_DMA0 57 +- +-/* Total number of clocks. */ +-#define NR_CLKS (HCLK_DMA0 + 1) +- +-#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/s3c2443.h b/scripts/dtc/include-prefixes/dt-bindings/clock/s3c2443.h +deleted file mode 100644 +index a9d2f105d536..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/s3c2443.h ++++ /dev/null +@@ -1,91 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2013 Heiko Stuebner +- * +- * Device Tree binding constants clock controllers of Samsung S3C2443 and later. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H +-#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H +- +-/* +- * Let each exported clock get a unique index, which is used on DT-enabled +- * platforms to lookup the clock from a clock specifier. These indices are +- * therefore considered an ABI and so must not be changed. This implies +- * that new clocks should be added either in free spaces between clock groups +- * or at the end. +- */ +- +-/* Core clocks. */ +-#define MSYSCLK 1 +-#define ESYSCLK 2 +-#define ARMDIV 3 +-#define ARMCLK 4 +-#define HCLK 5 +-#define PCLK 6 +-#define MPLL 7 +-#define EPLL 8 +- +-/* Special clocks */ +-#define SCLK_HSSPI0 16 +-#define SCLK_FIMD 17 +-#define SCLK_I2S0 18 +-#define SCLK_I2S1 19 +-#define SCLK_HSMMC1 20 +-#define SCLK_HSMMC_EXT 21 +-#define SCLK_CAM 22 +-#define SCLK_UART 23 +-#define SCLK_USBH 24 +- +-/* Muxes */ +-#define MUX_HSSPI0 32 +-#define MUX_HSSPI1 33 +-#define MUX_HSMMC0 34 +-#define MUX_HSMMC1 35 +- +-/* hclk-gates */ +-#define HCLK_DMA0 48 +-#define HCLK_DMA1 49 +-#define HCLK_DMA2 50 +-#define HCLK_DMA3 51 +-#define HCLK_DMA4 52 +-#define HCLK_DMA5 53 +-#define HCLK_DMA6 54 +-#define HCLK_DMA7 55 +-#define HCLK_CAM 56 +-#define HCLK_LCD 57 +-#define HCLK_USBH 58 +-#define HCLK_USBD 59 +-#define HCLK_IROM 60 +-#define HCLK_HSMMC0 61 +-#define HCLK_HSMMC1 62 +-#define HCLK_CFC 63 +-#define HCLK_SSMC 64 +-#define HCLK_DRAM 65 +-#define HCLK_2D 66 +- +-/* pclk-gates */ +-#define PCLK_UART0 72 +-#define PCLK_UART1 73 +-#define PCLK_UART2 74 +-#define PCLK_UART3 75 +-#define PCLK_I2C0 76 +-#define PCLK_SDI 77 +-#define PCLK_SPI0 78 +-#define PCLK_ADC 79 +-#define PCLK_AC97 80 +-#define PCLK_I2S0 81 +-#define PCLK_PWM 82 +-#define PCLK_WDT 83 +-#define PCLK_RTC 84 +-#define PCLK_GPIO 85 +-#define PCLK_SPI1 86 +-#define PCLK_CHIPID 87 +-#define PCLK_I2C1 88 +-#define PCLK_I2S1 89 +-#define PCLK_PCM 90 +- +-/* Total number of clocks. */ +-#define NR_CLKS (PCLK_PCM + 1) +- +-#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/s5pv210-audss.h b/scripts/dtc/include-prefixes/dt-bindings/clock/s5pv210-audss.h +deleted file mode 100644 +index 84d62fe7a738..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/s5pv210-audss.h ++++ /dev/null +@@ -1,31 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014 Tomasz Figa +- * +- * This header provides constants for Samsung audio subsystem +- * clock controller. +- * +- * The constants defined in this header are being used in dts +- * and s5pv210 audss driver. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H +-#define _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H +- +-#define CLK_MOUT_AUDSS 0 +-#define CLK_MOUT_I2S_A 1 +- +-#define CLK_DOUT_AUD_BUS 2 +-#define CLK_DOUT_I2S_A 3 +- +-#define CLK_I2S 4 +-#define CLK_HCLK_I2S 5 +-#define CLK_HCLK_UART 6 +-#define CLK_HCLK_HWA 7 +-#define CLK_HCLK_DMA 8 +-#define CLK_HCLK_BUF 9 +-#define CLK_HCLK_RP 10 +- +-#define AUDSS_MAX_CLKS 11 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/s5pv210.h b/scripts/dtc/include-prefixes/dt-bindings/clock/s5pv210.h +deleted file mode 100644 +index c36699c2fa33..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/s5pv210.h ++++ /dev/null +@@ -1,236 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2013 Samsung Electronics Co., Ltd. +- * Author: Mateusz Krawczuk +- * +- * Device Tree binding constants for Samsung S5PV210 clock controller. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_S5PV210_H +-#define _DT_BINDINGS_CLOCK_S5PV210_H +- +-/* Core clocks. */ +-#define FIN_PLL 1 +-#define FOUT_APLL 2 +-#define FOUT_MPLL 3 +-#define FOUT_EPLL 4 +-#define FOUT_VPLL 5 +- +-/* Muxes. */ +-#define MOUT_FLASH 6 +-#define MOUT_PSYS 7 +-#define MOUT_DSYS 8 +-#define MOUT_MSYS 9 +-#define MOUT_VPLL 10 +-#define MOUT_EPLL 11 +-#define MOUT_MPLL 12 +-#define MOUT_APLL 13 +-#define MOUT_VPLLSRC 14 +-#define MOUT_CSIS 15 +-#define MOUT_FIMD 16 +-#define MOUT_CAM1 17 +-#define MOUT_CAM0 18 +-#define MOUT_DAC 19 +-#define MOUT_MIXER 20 +-#define MOUT_HDMI 21 +-#define MOUT_G2D 22 +-#define MOUT_MFC 23 +-#define MOUT_G3D 24 +-#define MOUT_FIMC2 25 +-#define MOUT_FIMC1 26 +-#define MOUT_FIMC0 27 +-#define MOUT_UART3 28 +-#define MOUT_UART2 29 +-#define MOUT_UART1 30 +-#define MOUT_UART0 31 +-#define MOUT_MMC3 32 +-#define MOUT_MMC2 33 +-#define MOUT_MMC1 34 +-#define MOUT_MMC0 35 +-#define MOUT_PWM 36 +-#define MOUT_SPI0 37 +-#define MOUT_SPI1 38 +-#define MOUT_DMC0 39 +-#define MOUT_PWI 40 +-#define MOUT_HPM 41 +-#define MOUT_SPDIF 42 +-#define MOUT_AUDIO2 43 +-#define MOUT_AUDIO1 44 +-#define MOUT_AUDIO0 45 +- +-/* Dividers. */ +-#define DOUT_PCLKP 46 +-#define DOUT_HCLKP 47 +-#define DOUT_PCLKD 48 +-#define DOUT_HCLKD 49 +-#define DOUT_PCLKM 50 +-#define DOUT_HCLKM 51 +-#define DOUT_A2M 52 +-#define DOUT_APLL 53 +-#define DOUT_CSIS 54 +-#define DOUT_FIMD 55 +-#define DOUT_CAM1 56 +-#define DOUT_CAM0 57 +-#define DOUT_TBLK 58 +-#define DOUT_G2D 59 +-#define DOUT_MFC 60 +-#define DOUT_G3D 61 +-#define DOUT_FIMC2 62 +-#define DOUT_FIMC1 63 +-#define DOUT_FIMC0 64 +-#define DOUT_UART3 65 +-#define DOUT_UART2 66 +-#define DOUT_UART1 67 +-#define DOUT_UART0 68 +-#define DOUT_MMC3 69 +-#define DOUT_MMC2 70 +-#define DOUT_MMC1 71 +-#define DOUT_MMC0 72 +-#define DOUT_PWM 73 +-#define DOUT_SPI1 74 +-#define DOUT_SPI0 75 +-#define DOUT_DMC0 76 +-#define DOUT_PWI 77 +-#define DOUT_HPM 78 +-#define DOUT_COPY 79 +-#define DOUT_FLASH 80 +-#define DOUT_AUDIO2 81 +-#define DOUT_AUDIO1 82 +-#define DOUT_AUDIO0 83 +-#define DOUT_DPM 84 +-#define DOUT_DVSEM 85 +- +-/* Gates */ +-#define SCLK_FIMC 86 +-#define CLK_CSIS 87 +-#define CLK_ROTATOR 88 +-#define CLK_FIMC2 89 +-#define CLK_FIMC1 90 +-#define CLK_FIMC0 91 +-#define CLK_MFC 92 +-#define CLK_G2D 93 +-#define CLK_G3D 94 +-#define CLK_IMEM 95 +-#define CLK_PDMA1 96 +-#define CLK_PDMA0 97 +-#define CLK_MDMA 98 +-#define CLK_DMC1 99 +-#define CLK_DMC0 100 +-#define CLK_NFCON 101 +-#define CLK_SROMC 102 +-#define CLK_CFCON 103 +-#define CLK_NANDXL 104 +-#define CLK_USB_HOST 105 +-#define CLK_USB_OTG 106 +-#define CLK_HDMI 107 +-#define CLK_TVENC 108 +-#define CLK_MIXER 109 +-#define CLK_VP 110 +-#define CLK_DSIM 111 +-#define CLK_FIMD 112 +-#define CLK_TZIC3 113 +-#define CLK_TZIC2 114 +-#define CLK_TZIC1 115 +-#define CLK_TZIC0 116 +-#define CLK_VIC3 117 +-#define CLK_VIC2 118 +-#define CLK_VIC1 119 +-#define CLK_VIC0 120 +-#define CLK_TSI 121 +-#define CLK_HSMMC3 122 +-#define CLK_HSMMC2 123 +-#define CLK_HSMMC1 124 +-#define CLK_HSMMC0 125 +-#define CLK_JTAG 126 +-#define CLK_MODEMIF 127 +-#define CLK_CORESIGHT 128 +-#define CLK_SDM 129 +-#define CLK_SECSS 130 +-#define CLK_PCM2 131 +-#define CLK_PCM1 132 +-#define CLK_PCM0 133 +-#define CLK_SYSCON 134 +-#define CLK_GPIO 135 +-#define CLK_TSADC 136 +-#define CLK_PWM 137 +-#define CLK_WDT 138 +-#define CLK_KEYIF 139 +-#define CLK_UART3 140 +-#define CLK_UART2 141 +-#define CLK_UART1 142 +-#define CLK_UART0 143 +-#define CLK_SYSTIMER 144 +-#define CLK_RTC 145 +-#define CLK_SPI1 146 +-#define CLK_SPI0 147 +-#define CLK_I2C_HDMI_PHY 148 +-#define CLK_I2C1 149 +-#define CLK_I2C2 150 +-#define CLK_I2C0 151 +-#define CLK_I2S1 152 +-#define CLK_I2S2 153 +-#define CLK_I2S0 154 +-#define CLK_AC97 155 +-#define CLK_SPDIF 156 +-#define CLK_TZPC3 157 +-#define CLK_TZPC2 158 +-#define CLK_TZPC1 159 +-#define CLK_TZPC0 160 +-#define CLK_SECKEY 161 +-#define CLK_IEM_APC 162 +-#define CLK_IEM_IEC 163 +-#define CLK_CHIPID 164 +-#define CLK_JPEG 163 +- +-/* Special clocks*/ +-#define SCLK_PWI 164 +-#define SCLK_SPDIF 165 +-#define SCLK_AUDIO2 166 +-#define SCLK_AUDIO1 167 +-#define SCLK_AUDIO0 168 +-#define SCLK_PWM 169 +-#define SCLK_SPI1 170 +-#define SCLK_SPI0 171 +-#define SCLK_UART3 172 +-#define SCLK_UART2 173 +-#define SCLK_UART1 174 +-#define SCLK_UART0 175 +-#define SCLK_MMC3 176 +-#define SCLK_MMC2 177 +-#define SCLK_MMC1 178 +-#define SCLK_MMC0 179 +-#define SCLK_FINVPLL 180 +-#define SCLK_CSIS 181 +-#define SCLK_FIMD 182 +-#define SCLK_CAM1 183 +-#define SCLK_CAM0 184 +-#define SCLK_DAC 185 +-#define SCLK_MIXER 186 +-#define SCLK_HDMI 187 +-#define SCLK_FIMC2 188 +-#define SCLK_FIMC1 189 +-#define SCLK_FIMC0 190 +-#define SCLK_HDMI27M 191 +-#define SCLK_HDMIPHY 192 +-#define SCLK_USBPHY0 193 +-#define SCLK_USBPHY1 194 +- +-/* S5P6442-specific clocks */ +-#define MOUT_D0SYNC 195 +-#define MOUT_D1SYNC 196 +-#define DOUT_MIXER 197 +-#define CLK_ETB 198 +-#define CLK_ETM 199 +- +-/* CLKOUT */ +-#define FOUT_APLL_CLKOUT 200 +-#define FOUT_MPLL_CLKOUT 201 +-#define DOUT_APLL_CLKOUT 202 +-#define MOUT_CLKSEL 203 +-#define DOUT_CLKOUT 204 +-#define MOUT_CLKOUT 205 +- +-/* Total number of clocks. */ +-#define NR_CLKS 206 +- +-#endif /* _DT_BINDINGS_CLOCK_S5PV210_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/samsung,s2mps11.h b/scripts/dtc/include-prefixes/dt-bindings/clock/samsung,s2mps11.h +deleted file mode 100644 +index 5ece35d429ff..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/samsung,s2mps11.h ++++ /dev/null +@@ -1,20 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2015 Markus Reichl +- * +- * Device Tree binding constants clocks for the Samsung S2MPS11 PMIC. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S2MPS11_CLOCK_H +-#define _DT_BINDINGS_CLOCK_SAMSUNG_S2MPS11_CLOCK_H +- +-/* Fixed rate clocks. */ +- +-#define S2MPS11_CLK_AP 0 +-#define S2MPS11_CLK_CP 1 +-#define S2MPS11_CLK_BT 2 +- +-/* Total number of clocks. */ +-#define S2MPS11_CLKS_NUM (S2MPS11_CLK_BT + 1) +- +-#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S2MPS11_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/samsung,s3c64xx-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/samsung,s3c64xx-clock.h +deleted file mode 100644 +index 19d233f37e2f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/samsung,s3c64xx-clock.h ++++ /dev/null +@@ -1,175 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2013 Tomasz Figa +- * +- * Device Tree binding constants for Samsung S3C64xx clock controller. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H +-#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H +- +-/* +- * Let each exported clock get a unique index, which is used on DT-enabled +- * platforms to lookup the clock from a clock specifier. These indices are +- * therefore considered an ABI and so must not be changed. This implies +- * that new clocks should be added either in free spaces between clock groups +- * or at the end. +- */ +- +-/* Core clocks. */ +-#define CLK27M 1 +-#define CLK48M 2 +-#define FOUT_APLL 3 +-#define FOUT_MPLL 4 +-#define FOUT_EPLL 5 +-#define ARMCLK 6 +-#define HCLKX2 7 +-#define HCLK 8 +-#define PCLK 9 +- +-/* HCLK bus clocks. */ +-#define HCLK_3DSE 16 +-#define HCLK_UHOST 17 +-#define HCLK_SECUR 18 +-#define HCLK_SDMA1 19 +-#define HCLK_SDMA0 20 +-#define HCLK_IROM 21 +-#define HCLK_DDR1 22 +-#define HCLK_MEM1 23 +-#define HCLK_MEM0 24 +-#define HCLK_USB 25 +-#define HCLK_HSMMC2 26 +-#define HCLK_HSMMC1 27 +-#define HCLK_HSMMC0 28 +-#define HCLK_MDP 29 +-#define HCLK_DHOST 30 +-#define HCLK_IHOST 31 +-#define HCLK_DMA1 32 +-#define HCLK_DMA0 33 +-#define HCLK_JPEG 34 +-#define HCLK_CAMIF 35 +-#define HCLK_SCALER 36 +-#define HCLK_2D 37 +-#define HCLK_TV 38 +-#define HCLK_POST0 39 +-#define HCLK_ROT 40 +-#define HCLK_LCD 41 +-#define HCLK_TZIC 42 +-#define HCLK_INTC 43 +-#define HCLK_MFC 44 +-#define HCLK_DDR0 45 +- +-/* PCLK bus clocks. */ +-#define PCLK_IIC1 48 +-#define PCLK_IIS2 49 +-#define PCLK_SKEY 50 +-#define PCLK_CHIPID 51 +-#define PCLK_SPI1 52 +-#define PCLK_SPI0 53 +-#define PCLK_HSIRX 54 +-#define PCLK_HSITX 55 +-#define PCLK_GPIO 56 +-#define PCLK_IIC0 57 +-#define PCLK_IIS1 58 +-#define PCLK_IIS0 59 +-#define PCLK_AC97 60 +-#define PCLK_TZPC 61 +-#define PCLK_TSADC 62 +-#define PCLK_KEYPAD 63 +-#define PCLK_IRDA 64 +-#define PCLK_PCM1 65 +-#define PCLK_PCM0 66 +-#define PCLK_PWM 67 +-#define PCLK_RTC 68 +-#define PCLK_WDT 69 +-#define PCLK_UART3 70 +-#define PCLK_UART2 71 +-#define PCLK_UART1 72 +-#define PCLK_UART0 73 +-#define PCLK_MFC 74 +- +-/* Special clocks. */ +-#define SCLK_UHOST 80 +-#define SCLK_MMC2_48 81 +-#define SCLK_MMC1_48 82 +-#define SCLK_MMC0_48 83 +-#define SCLK_MMC2 84 +-#define SCLK_MMC1 85 +-#define SCLK_MMC0 86 +-#define SCLK_SPI1_48 87 +-#define SCLK_SPI0_48 88 +-#define SCLK_SPI1 89 +-#define SCLK_SPI0 90 +-#define SCLK_DAC27 91 +-#define SCLK_TV27 92 +-#define SCLK_SCALER27 93 +-#define SCLK_SCALER 94 +-#define SCLK_LCD27 95 +-#define SCLK_LCD 96 +-#define SCLK_FIMC 97 +-#define SCLK_POST0_27 98 +-#define SCLK_AUDIO2 99 +-#define SCLK_POST0 100 +-#define SCLK_AUDIO1 101 +-#define SCLK_AUDIO0 102 +-#define SCLK_SECUR 103 +-#define SCLK_IRDA 104 +-#define SCLK_UART 105 +-#define SCLK_MFC 106 +-#define SCLK_CAM 107 +-#define SCLK_JPEG 108 +-#define SCLK_ONENAND 109 +- +-/* MEM0 bus clocks - S3C6410-specific. */ +-#define MEM0_CFCON 112 +-#define MEM0_ONENAND1 113 +-#define MEM0_ONENAND0 114 +-#define MEM0_NFCON 115 +-#define MEM0_SROM 116 +- +-/* Muxes. */ +-#define MOUT_APLL 128 +-#define MOUT_MPLL 129 +-#define MOUT_EPLL 130 +-#define MOUT_MFC 131 +-#define MOUT_AUDIO0 132 +-#define MOUT_AUDIO1 133 +-#define MOUT_UART 134 +-#define MOUT_SPI0 135 +-#define MOUT_SPI1 136 +-#define MOUT_MMC0 137 +-#define MOUT_MMC1 138 +-#define MOUT_MMC2 139 +-#define MOUT_UHOST 140 +-#define MOUT_IRDA 141 +-#define MOUT_LCD 142 +-#define MOUT_SCALER 143 +-#define MOUT_DAC27 144 +-#define MOUT_TV27 145 +-#define MOUT_AUDIO2 146 +- +-/* Dividers. */ +-#define DOUT_MPLL 160 +-#define DOUT_SECUR 161 +-#define DOUT_CAM 162 +-#define DOUT_JPEG 163 +-#define DOUT_MFC 164 +-#define DOUT_MMC0 165 +-#define DOUT_MMC1 166 +-#define DOUT_MMC2 167 +-#define DOUT_LCD 168 +-#define DOUT_SCALER 169 +-#define DOUT_UHOST 170 +-#define DOUT_SPI0 171 +-#define DOUT_SPI1 172 +-#define DOUT_AUDIO0 173 +-#define DOUT_AUDIO1 174 +-#define DOUT_UART 175 +-#define DOUT_IRDA 176 +-#define DOUT_FIMC 177 +-#define DOUT_AUDIO2 178 +- +-/* Total number of clocks. */ +-#define NR_CLKS (DOUT_AUDIO2 + 1) +- +-#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sh73a0-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sh73a0-clock.h +deleted file mode 100644 +index 5b544ad7f9b7..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sh73a0-clock.h ++++ /dev/null +@@ -1,82 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright 2014 Ulrich Hecht +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_SH73A0_H__ +-#define __DT_BINDINGS_CLOCK_SH73A0_H__ +- +-/* CPG */ +-#define SH73A0_CLK_MAIN 0 +-#define SH73A0_CLK_PLL0 1 +-#define SH73A0_CLK_PLL1 2 +-#define SH73A0_CLK_PLL2 3 +-#define SH73A0_CLK_PLL3 4 +-#define SH73A0_CLK_DSI0PHY 5 +-#define SH73A0_CLK_DSI1PHY 6 +-#define SH73A0_CLK_ZG 7 +-#define SH73A0_CLK_M3 8 +-#define SH73A0_CLK_B 9 +-#define SH73A0_CLK_M1 10 +-#define SH73A0_CLK_M2 11 +-#define SH73A0_CLK_Z 12 +-#define SH73A0_CLK_ZX 13 +-#define SH73A0_CLK_HP 14 +- +-/* MSTP0 */ +-#define SH73A0_CLK_IIC2 1 +-#define SH73A0_CLK_MSIOF0 0 +- +-/* MSTP1 */ +-#define SH73A0_CLK_CEU1 29 +-#define SH73A0_CLK_CSI2_RX1 28 +-#define SH73A0_CLK_CEU0 27 +-#define SH73A0_CLK_CSI2_RX0 26 +-#define SH73A0_CLK_TMU0 25 +-#define SH73A0_CLK_DSITX0 18 +-#define SH73A0_CLK_IIC0 16 +-#define SH73A0_CLK_SGX 12 +-#define SH73A0_CLK_LCDC0 0 +- +-/* MSTP2 */ +-#define SH73A0_CLK_SCIFA7 19 +-#define SH73A0_CLK_SY_DMAC 18 +-#define SH73A0_CLK_MP_DMAC 17 +-#define SH73A0_CLK_MSIOF3 15 +-#define SH73A0_CLK_MSIOF1 8 +-#define SH73A0_CLK_SCIFA5 7 +-#define SH73A0_CLK_SCIFB 6 +-#define SH73A0_CLK_MSIOF2 5 +-#define SH73A0_CLK_SCIFA0 4 +-#define SH73A0_CLK_SCIFA1 3 +-#define SH73A0_CLK_SCIFA2 2 +-#define SH73A0_CLK_SCIFA3 1 +-#define SH73A0_CLK_SCIFA4 0 +- +-/* MSTP3 */ +-#define SH73A0_CLK_SCIFA6 31 +-#define SH73A0_CLK_CMT1 29 +-#define SH73A0_CLK_FSI 28 +-#define SH73A0_CLK_IRDA 25 +-#define SH73A0_CLK_IIC1 23 +-#define SH73A0_CLK_USB 22 +-#define SH73A0_CLK_FLCTL 15 +-#define SH73A0_CLK_SDHI0 14 +-#define SH73A0_CLK_SDHI1 13 +-#define SH73A0_CLK_MMCIF0 12 +-#define SH73A0_CLK_SDHI2 11 +-#define SH73A0_CLK_TPU0 4 +-#define SH73A0_CLK_TPU1 3 +-#define SH73A0_CLK_TPU2 2 +-#define SH73A0_CLK_TPU3 1 +-#define SH73A0_CLK_TPU4 0 +- +-/* MSTP4 */ +-#define SH73A0_CLK_IIC3 11 +-#define SH73A0_CLK_IIC4 10 +-#define SH73A0_CLK_KEYSC 3 +- +-/* MSTP5 */ +-#define SH73A0_CLK_INTCA0 8 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sifive-fu540-prci.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sifive-fu540-prci.h +deleted file mode 100644 +index 3b21d0522c91..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sifive-fu540-prci.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +-/* +- * Copyright (C) 2018-2019 SiFive, Inc. +- * Wesley Terpstra +- * Paul Walmsley +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H +-#define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H +- +-/* Clock indexes for use by Device Tree data and the PRCI driver */ +- +-#define PRCI_CLK_COREPLL 0 +-#define PRCI_CLK_DDRPLL 1 +-#define PRCI_CLK_GEMGXLPLL 2 +-#define PRCI_CLK_TLCLK 3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sifive-fu740-prci.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sifive-fu740-prci.h +deleted file mode 100644 +index 7899b7fee7db..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sifive-fu740-prci.h ++++ /dev/null +@@ -1,24 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +-/* +- * Copyright (C) 2019 SiFive, Inc. +- * Wesley Terpstra +- * Paul Walmsley +- * Zong Li +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H +-#define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H +- +-/* Clock indexes for use by Device Tree data and the PRCI driver */ +- +-#define PRCI_CLK_COREPLL 0 +-#define PRCI_CLK_DDRPLL 1 +-#define PRCI_CLK_GEMGXLPLL 2 +-#define PRCI_CLK_DVFSCOREPLL 3 +-#define PRCI_CLK_HFPCLKPLL 4 +-#define PRCI_CLK_CLTXPLL 5 +-#define PRCI_CLK_TLCLK 6 +-#define PRCI_CLK_PCLK 7 +-#define PRCI_CLK_PCIE_AUX 8 +- +-#endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sprd,sc9860-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sprd,sc9860-clk.h +deleted file mode 100644 +index f2ab4631df0d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sprd,sc9860-clk.h ++++ /dev/null +@@ -1,423 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// +-// Spreadtrum SC9860 platform clocks +-// +-// Copyright (C) 2017, Spreadtrum Communications Inc. +- +-#ifndef _DT_BINDINGS_CLK_SC9860_H_ +-#define _DT_BINDINGS_CLK_SC9860_H_ +- +-#define CLK_FAC_4M 0 +-#define CLK_FAC_2M 1 +-#define CLK_FAC_1M 2 +-#define CLK_FAC_250K 3 +-#define CLK_FAC_RPLL0_26M 4 +-#define CLK_FAC_RPLL1_26M 5 +-#define CLK_FAC_RCO25M 6 +-#define CLK_FAC_RCO4M 7 +-#define CLK_FAC_RCO2M 8 +-#define CLK_FAC_3K2 9 +-#define CLK_FAC_1K 10 +-#define CLK_MPLL0_GATE 11 +-#define CLK_MPLL1_GATE 12 +-#define CLK_DPLL0_GATE 13 +-#define CLK_DPLL1_GATE 14 +-#define CLK_LTEPLL0_GATE 15 +-#define CLK_TWPLL_GATE 16 +-#define CLK_LTEPLL1_GATE 17 +-#define CLK_RPLL0_GATE 18 +-#define CLK_RPLL1_GATE 19 +-#define CLK_CPPLL_GATE 20 +-#define CLK_GPLL_GATE 21 +-#define CLK_PMU_GATE_NUM (CLK_GPLL_GATE + 1) +- +-#define CLK_MPLL0 0 +-#define CLK_MPLL1 1 +-#define CLK_DPLL0 2 +-#define CLK_DPLL1 3 +-#define CLK_RPLL0 4 +-#define CLK_RPLL1 5 +-#define CLK_TWPLL 6 +-#define CLK_LTEPLL0 7 +-#define CLK_LTEPLL1 8 +-#define CLK_GPLL 9 +-#define CLK_CPPLL 10 +-#define CLK_GPLL_42M5 11 +-#define CLK_TWPLL_768M 12 +-#define CLK_TWPLL_384M 13 +-#define CLK_TWPLL_192M 14 +-#define CLK_TWPLL_96M 15 +-#define CLK_TWPLL_48M 16 +-#define CLK_TWPLL_24M 17 +-#define CLK_TWPLL_12M 18 +-#define CLK_TWPLL_512M 19 +-#define CLK_TWPLL_256M 20 +-#define CLK_TWPLL_128M 21 +-#define CLK_TWPLL_64M 22 +-#define CLK_TWPLL_307M2 23 +-#define CLK_TWPLL_153M6 24 +-#define CLK_TWPLL_76M8 25 +-#define CLK_TWPLL_51M2 26 +-#define CLK_TWPLL_38M4 27 +-#define CLK_TWPLL_19M2 28 +-#define CLK_L0_614M4 29 +-#define CLK_L0_409M6 30 +-#define CLK_L0_38M 31 +-#define CLK_L1_38M 32 +-#define CLK_RPLL0_192M 33 +-#define CLK_RPLL0_96M 34 +-#define CLK_RPLL0_48M 35 +-#define CLK_RPLL1_468M 36 +-#define CLK_RPLL1_192M 37 +-#define CLK_RPLL1_96M 38 +-#define CLK_RPLL1_64M 39 +-#define CLK_RPLL1_48M 40 +-#define CLK_DPLL0_50M 41 +-#define CLK_DPLL1_50M 42 +-#define CLK_CPPLL_50M 43 +-#define CLK_M0_39M 44 +-#define CLK_M1_63M 45 +-#define CLK_PLL_NUM (CLK_M1_63M + 1) +- +- +-#define CLK_AP_APB 0 +-#define CLK_AP_USB3 1 +-#define CLK_UART0 2 +-#define CLK_UART1 3 +-#define CLK_UART2 4 +-#define CLK_UART3 5 +-#define CLK_UART4 6 +-#define CLK_I2C0 7 +-#define CLK_I2C1 8 +-#define CLK_I2C2 9 +-#define CLK_I2C3 10 +-#define CLK_I2C4 11 +-#define CLK_I2C5 12 +-#define CLK_SPI0 13 +-#define CLK_SPI1 14 +-#define CLK_SPI2 15 +-#define CLK_SPI3 16 +-#define CLK_IIS0 17 +-#define CLK_IIS1 18 +-#define CLK_IIS2 19 +-#define CLK_IIS3 20 +-#define CLK_AP_CLK_NUM (CLK_IIS3 + 1) +- +-#define CLK_AON_APB 0 +-#define CLK_AUX0 1 +-#define CLK_AUX1 2 +-#define CLK_AUX2 3 +-#define CLK_PROBE 4 +-#define CLK_SP_AHB 5 +-#define CLK_CCI 6 +-#define CLK_GIC 7 +-#define CLK_CSSYS 8 +-#define CLK_SDIO0_2X 9 +-#define CLK_SDIO1_2X 10 +-#define CLK_SDIO2_2X 11 +-#define CLK_EMMC_2X 12 +-#define CLK_SDIO0_1X 13 +-#define CLK_SDIO1_1X 14 +-#define CLK_SDIO2_1X 15 +-#define CLK_EMMC_1X 16 +-#define CLK_ADI 17 +-#define CLK_PWM0 18 +-#define CLK_PWM1 19 +-#define CLK_PWM2 20 +-#define CLK_PWM3 21 +-#define CLK_EFUSE 22 +-#define CLK_CM3_UART0 23 +-#define CLK_CM3_UART1 24 +-#define CLK_THM 25 +-#define CLK_CM3_I2C0 26 +-#define CLK_CM3_I2C1 27 +-#define CLK_CM4_SPI 28 +-#define CLK_AON_I2C 29 +-#define CLK_AVS 30 +-#define CLK_CA53_DAP 31 +-#define CLK_CA53_TS 32 +-#define CLK_DJTAG_TCK 33 +-#define CLK_PMU 34 +-#define CLK_PMU_26M 35 +-#define CLK_DEBOUNCE 36 +-#define CLK_OTG2_REF 37 +-#define CLK_USB3_REF 38 +-#define CLK_AP_AXI 39 +-#define CLK_AON_PREDIV_NUM (CLK_AP_AXI + 1) +- +-#define CLK_USB3_EB 0 +-#define CLK_USB3_SUSPEND_EB 1 +-#define CLK_USB3_REF_EB 2 +-#define CLK_DMA_EB 3 +-#define CLK_SDIO0_EB 4 +-#define CLK_SDIO1_EB 5 +-#define CLK_SDIO2_EB 6 +-#define CLK_EMMC_EB 7 +-#define CLK_ROM_EB 8 +-#define CLK_BUSMON_EB 9 +-#define CLK_CC63S_EB 10 +-#define CLK_CC63P_EB 11 +-#define CLK_CE0_EB 12 +-#define CLK_CE1_EB 13 +-#define CLK_APAHB_GATE_NUM (CLK_CE1_EB + 1) +- +-#define CLK_AVS_LIT_EB 0 +-#define CLK_AVS_BIG_EB 1 +-#define CLK_AP_INTC5_EB 2 +-#define CLK_GPIO_EB 3 +-#define CLK_PWM0_EB 4 +-#define CLK_PWM1_EB 5 +-#define CLK_PWM2_EB 6 +-#define CLK_PWM3_EB 7 +-#define CLK_KPD_EB 8 +-#define CLK_AON_SYS_EB 9 +-#define CLK_AP_SYS_EB 10 +-#define CLK_AON_TMR_EB 11 +-#define CLK_AP_TMR0_EB 12 +-#define CLK_EFUSE_EB 13 +-#define CLK_EIC_EB 14 +-#define CLK_PUB1_REG_EB 15 +-#define CLK_ADI_EB 16 +-#define CLK_AP_INTC0_EB 17 +-#define CLK_AP_INTC1_EB 18 +-#define CLK_AP_INTC2_EB 19 +-#define CLK_AP_INTC3_EB 20 +-#define CLK_AP_INTC4_EB 21 +-#define CLK_SPLK_EB 22 +-#define CLK_MSPI_EB 23 +-#define CLK_PUB0_REG_EB 24 +-#define CLK_PIN_EB 25 +-#define CLK_AON_CKG_EB 26 +-#define CLK_GPU_EB 27 +-#define CLK_APCPU_TS0_EB 28 +-#define CLK_APCPU_TS1_EB 29 +-#define CLK_DAP_EB 30 +-#define CLK_I2C_EB 31 +-#define CLK_PMU_EB 32 +-#define CLK_THM_EB 33 +-#define CLK_AUX0_EB 34 +-#define CLK_AUX1_EB 35 +-#define CLK_AUX2_EB 36 +-#define CLK_PROBE_EB 37 +-#define CLK_GPU0_AVS_EB 38 +-#define CLK_GPU1_AVS_EB 39 +-#define CLK_APCPU_WDG_EB 40 +-#define CLK_AP_TMR1_EB 41 +-#define CLK_AP_TMR2_EB 42 +-#define CLK_DISP_EMC_EB 43 +-#define CLK_ZIP_EMC_EB 44 +-#define CLK_GSP_EMC_EB 45 +-#define CLK_OSC_AON_EB 46 +-#define CLK_LVDS_TRX_EB 47 +-#define CLK_LVDS_TCXO_EB 48 +-#define CLK_MDAR_EB 49 +-#define CLK_RTC4M0_CAL_EB 50 +-#define CLK_RCT100M_CAL_EB 51 +-#define CLK_DJTAG_EB 52 +-#define CLK_MBOX_EB 53 +-#define CLK_AON_DMA_EB 54 +-#define CLK_DBG_EMC_EB 55 +-#define CLK_LVDS_PLL_DIV_EN 56 +-#define CLK_DEF_EB 57 +-#define CLK_AON_APB_RSV0 58 +-#define CLK_ORP_JTAG_EB 59 +-#define CLK_VSP_EB 60 +-#define CLK_CAM_EB 61 +-#define CLK_DISP_EB 62 +-#define CLK_DBG_AXI_IF_EB 63 +-#define CLK_SDIO0_2X_EN 64 +-#define CLK_SDIO1_2X_EN 65 +-#define CLK_SDIO2_2X_EN 66 +-#define CLK_EMMC_2X_EN 67 +-#define CLK_ARCH_RTC_EB 68 +-#define CLK_KPB_RTC_EB 69 +-#define CLK_AON_SYST_RTC_EB 70 +-#define CLK_AP_SYST_RTC_EB 71 +-#define CLK_AON_TMR_RTC_EB 72 +-#define CLK_AP_TMR0_RTC_EB 73 +-#define CLK_EIC_RTC_EB 74 +-#define CLK_EIC_RTCDV5_EB 75 +-#define CLK_AP_WDG_RTC_EB 76 +-#define CLK_AP_TMR1_RTC_EB 77 +-#define CLK_AP_TMR2_RTC_EB 78 +-#define CLK_DCXO_TMR_RTC_EB 79 +-#define CLK_BB_CAL_RTC_EB 80 +-#define CLK_AVS_BIG_RTC_EB 81 +-#define CLK_AVS_LIT_RTC_EB 82 +-#define CLK_AVS_GPU0_RTC_EB 83 +-#define CLK_AVS_GPU1_RTC_EB 84 +-#define CLK_GPU_TS_EB 85 +-#define CLK_RTCDV10_EB 86 +-#define CLK_AON_GATE_NUM (CLK_RTCDV10_EB + 1) +- +-#define CLK_LIT_MCU 0 +-#define CLK_BIG_MCU 1 +-#define CLK_AONSECURE_NUM (CLK_BIG_MCU + 1) +- +-#define CLK_AGCP_IIS0_EB 0 +-#define CLK_AGCP_IIS1_EB 1 +-#define CLK_AGCP_IIS2_EB 2 +-#define CLK_AGCP_IIS3_EB 3 +-#define CLK_AGCP_UART_EB 4 +-#define CLK_AGCP_DMACP_EB 5 +-#define CLK_AGCP_DMAAP_EB 6 +-#define CLK_AGCP_ARC48K_EB 7 +-#define CLK_AGCP_SRC44P1K_EB 8 +-#define CLK_AGCP_MCDT_EB 9 +-#define CLK_AGCP_VBCIFD_EB 10 +-#define CLK_AGCP_VBC_EB 11 +-#define CLK_AGCP_SPINLOCK_EB 12 +-#define CLK_AGCP_ICU_EB 13 +-#define CLK_AGCP_AP_ASHB_EB 14 +-#define CLK_AGCP_CP_ASHB_EB 15 +-#define CLK_AGCP_AUD_EB 16 +-#define CLK_AGCP_AUDIF_EB 17 +-#define CLK_AGCP_GATE_NUM (CLK_AGCP_AUDIF_EB + 1) +- +-#define CLK_GPU 0 +-#define CLK_GPU_NUM (CLK_GPU + 1) +- +-#define CLK_AHB_VSP 0 +-#define CLK_VSP 1 +-#define CLK_VSP_ENC 2 +-#define CLK_VPP 3 +-#define CLK_VSP_26M 4 +-#define CLK_VSP_NUM (CLK_VSP_26M + 1) +- +-#define CLK_VSP_DEC_EB 0 +-#define CLK_VSP_CKG_EB 1 +-#define CLK_VSP_MMU_EB 2 +-#define CLK_VSP_ENC_EB 3 +-#define CLK_VPP_EB 4 +-#define CLK_VSP_26M_EB 5 +-#define CLK_VSP_AXI_GATE 6 +-#define CLK_VSP_ENC_GATE 7 +-#define CLK_VPP_AXI_GATE 8 +-#define CLK_VSP_BM_GATE 9 +-#define CLK_VSP_ENC_BM_GATE 10 +-#define CLK_VPP_BM_GATE 11 +-#define CLK_VSP_GATE_NUM (CLK_VPP_BM_GATE + 1) +- +-#define CLK_AHB_CAM 0 +-#define CLK_SENSOR0 1 +-#define CLK_SENSOR1 2 +-#define CLK_SENSOR2 3 +-#define CLK_MIPI_CSI0_EB 4 +-#define CLK_MIPI_CSI1_EB 5 +-#define CLK_CAM_NUM (CLK_MIPI_CSI1_EB + 1) +- +-#define CLK_DCAM0_EB 0 +-#define CLK_DCAM1_EB 1 +-#define CLK_ISP0_EB 2 +-#define CLK_CSI0_EB 3 +-#define CLK_CSI1_EB 4 +-#define CLK_JPG0_EB 5 +-#define CLK_JPG1_EB 6 +-#define CLK_CAM_CKG_EB 7 +-#define CLK_CAM_MMU_EB 8 +-#define CLK_ISP1_EB 9 +-#define CLK_CPP_EB 10 +-#define CLK_MMU_PF_EB 11 +-#define CLK_ISP2_EB 12 +-#define CLK_DCAM2ISP_IF_EB 13 +-#define CLK_ISP2DCAM_IF_EB 14 +-#define CLK_ISP_LCLK_EB 15 +-#define CLK_ISP_ICLK_EB 16 +-#define CLK_ISP_MCLK_EB 17 +-#define CLK_ISP_PCLK_EB 18 +-#define CLK_ISP_ISP2DCAM_EB 19 +-#define CLK_DCAM0_IF_EB 20 +-#define CLK_CLK26M_IF_EB 21 +-#define CLK_CPHY0_GATE 22 +-#define CLK_MIPI_CSI0_GATE 23 +-#define CLK_CPHY1_GATE 24 +-#define CLK_MIPI_CSI1 25 +-#define CLK_DCAM0_AXI_GATE 26 +-#define CLK_DCAM1_AXI_GATE 27 +-#define CLK_SENSOR0_GATE 28 +-#define CLK_SENSOR1_GATE 29 +-#define CLK_JPG0_AXI_GATE 30 +-#define CLK_GPG1_AXI_GATE 31 +-#define CLK_ISP0_AXI_GATE 32 +-#define CLK_ISP1_AXI_GATE 33 +-#define CLK_ISP2_AXI_GATE 34 +-#define CLK_CPP_AXI_GATE 35 +-#define CLK_D0_IF_AXI_GATE 36 +-#define CLK_D2I_IF_AXI_GATE 37 +-#define CLK_I2D_IF_AXI_GATE 38 +-#define CLK_SPARE_AXI_GATE 39 +-#define CLK_SENSOR2_GATE 40 +-#define CLK_D0IF_IN_D_EN 41 +-#define CLK_D1IF_IN_D_EN 42 +-#define CLK_D0IF_IN_D2I_EN 43 +-#define CLK_D1IF_IN_D2I_EN 44 +-#define CLK_IA_IN_D2I_EN 45 +-#define CLK_IB_IN_D2I_EN 46 +-#define CLK_IC_IN_D2I_EN 47 +-#define CLK_IA_IN_I_EN 48 +-#define CLK_IB_IN_I_EN 49 +-#define CLK_IC_IN_I_EN 50 +-#define CLK_CAM_GATE_NUM (CLK_IC_IN_I_EN + 1) +- +-#define CLK_AHB_DISP 0 +-#define CLK_DISPC0_DPI 1 +-#define CLK_DISPC1_DPI 2 +-#define CLK_DISP_NUM (CLK_DISPC1_DPI + 1) +- +-#define CLK_DISPC0_EB 0 +-#define CLK_DISPC1_EB 1 +-#define CLK_DISPC_MMU_EB 2 +-#define CLK_GSP0_EB 3 +-#define CLK_GSP1_EB 4 +-#define CLK_GSP0_MMU_EB 5 +-#define CLK_GSP1_MMU_EB 6 +-#define CLK_DSI0_EB 7 +-#define CLK_DSI1_EB 8 +-#define CLK_DISP_CKG_EB 9 +-#define CLK_DISP_GPU_EB 10 +-#define CLK_GPU_MTX_EB 11 +-#define CLK_GSP_MTX_EB 12 +-#define CLK_TMC_MTX_EB 13 +-#define CLK_DISPC_MTX_EB 14 +-#define CLK_DPHY0_GATE 15 +-#define CLK_DPHY1_GATE 16 +-#define CLK_GSP0_A_GATE 17 +-#define CLK_GSP1_A_GATE 18 +-#define CLK_GSP0_F_GATE 19 +-#define CLK_GSP1_F_GATE 20 +-#define CLK_D_MTX_F_GATE 21 +-#define CLK_D_MTX_A_GATE 22 +-#define CLK_D_NOC_F_GATE 23 +-#define CLK_D_NOC_A_GATE 24 +-#define CLK_GSP_MTX_F_GATE 25 +-#define CLK_GSP_MTX_A_GATE 26 +-#define CLK_GSP_NOC_F_GATE 27 +-#define CLK_GSP_NOC_A_GATE 28 +-#define CLK_DISPM0IDLE_GATE 29 +-#define CLK_GSPM0IDLE_GATE 30 +-#define CLK_DISP_GATE_NUM (CLK_GSPM0IDLE_GATE + 1) +- +-#define CLK_SIM0_EB 0 +-#define CLK_IIS0_EB 1 +-#define CLK_IIS1_EB 2 +-#define CLK_IIS2_EB 3 +-#define CLK_IIS3_EB 4 +-#define CLK_SPI0_EB 5 +-#define CLK_SPI1_EB 6 +-#define CLK_SPI2_EB 7 +-#define CLK_I2C0_EB 8 +-#define CLK_I2C1_EB 9 +-#define CLK_I2C2_EB 10 +-#define CLK_I2C3_EB 11 +-#define CLK_I2C4_EB 12 +-#define CLK_I2C5_EB 13 +-#define CLK_UART0_EB 14 +-#define CLK_UART1_EB 15 +-#define CLK_UART2_EB 16 +-#define CLK_UART3_EB 17 +-#define CLK_UART4_EB 18 +-#define CLK_AP_CKG_EB 19 +-#define CLK_SPI3_EB 20 +-#define CLK_APAPB_GATE_NUM (CLK_SPI3_EB + 1) +- +-#endif /* _DT_BINDINGS_CLK_SC9860_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sprd,sc9863a-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sprd,sc9863a-clk.h +deleted file mode 100644 +index 4e030421641f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sprd,sc9863a-clk.h ++++ /dev/null +@@ -1,339 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Unisoc SC9863A platform clocks +- * +- * Copyright (C) 2019, Unisoc Communications Inc. +- */ +- +-#ifndef _DT_BINDINGS_CLK_SC9863A_H_ +-#define _DT_BINDINGS_CLK_SC9863A_H_ +- +-#define CLK_MPLL0_GATE 0 +-#define CLK_DPLL0_GATE 1 +-#define CLK_LPLL_GATE 2 +-#define CLK_GPLL_GATE 3 +-#define CLK_DPLL1_GATE 4 +-#define CLK_MPLL1_GATE 5 +-#define CLK_MPLL2_GATE 6 +-#define CLK_ISPPLL_GATE 7 +-#define CLK_PMU_APB_NUM (CLK_ISPPLL_GATE + 1) +- +-#define CLK_AUDIO_GATE 0 +-#define CLK_RPLL 1 +-#define CLK_RPLL_390M 2 +-#define CLK_RPLL_260M 3 +-#define CLK_RPLL_195M 4 +-#define CLK_RPLL_26M 5 +-#define CLK_ANLG_PHY_G5_NUM (CLK_RPLL_26M + 1) +- +-#define CLK_TWPLL 0 +-#define CLK_TWPLL_768M 1 +-#define CLK_TWPLL_384M 2 +-#define CLK_TWPLL_192M 3 +-#define CLK_TWPLL_96M 4 +-#define CLK_TWPLL_48M 5 +-#define CLK_TWPLL_24M 6 +-#define CLK_TWPLL_12M 7 +-#define CLK_TWPLL_512M 8 +-#define CLK_TWPLL_256M 9 +-#define CLK_TWPLL_128M 10 +-#define CLK_TWPLL_64M 11 +-#define CLK_TWPLL_307M2 12 +-#define CLK_TWPLL_219M4 13 +-#define CLK_TWPLL_170M6 14 +-#define CLK_TWPLL_153M6 15 +-#define CLK_TWPLL_76M8 16 +-#define CLK_TWPLL_51M2 17 +-#define CLK_TWPLL_38M4 18 +-#define CLK_TWPLL_19M2 19 +-#define CLK_LPLL 20 +-#define CLK_LPLL_409M6 21 +-#define CLK_LPLL_245M76 22 +-#define CLK_GPLL 23 +-#define CLK_ISPPLL 24 +-#define CLK_ISPPLL_468M 25 +-#define CLK_ANLG_PHY_G1_NUM (CLK_ISPPLL_468M + 1) +- +-#define CLK_DPLL0 0 +-#define CLK_DPLL1 1 +-#define CLK_DPLL0_933M 2 +-#define CLK_DPLL0_622M3 3 +-#define CLK_DPLL0_400M 4 +-#define CLK_DPLL0_266M7 5 +-#define CLK_DPLL0_123M1 6 +-#define CLK_DPLL0_50M 7 +-#define CLK_ANLG_PHY_G7_NUM (CLK_DPLL0_50M + 1) +- +-#define CLK_MPLL0 0 +-#define CLK_MPLL1 1 +-#define CLK_MPLL2 2 +-#define CLK_MPLL2_675M 3 +-#define CLK_ANLG_PHY_G4_NUM (CLK_MPLL2_675M + 1) +- +-#define CLK_AP_APB 0 +-#define CLK_AP_CE 1 +-#define CLK_NANDC_ECC 2 +-#define CLK_NANDC_26M 3 +-#define CLK_EMMC_32K 4 +-#define CLK_SDIO0_32K 5 +-#define CLK_SDIO1_32K 6 +-#define CLK_SDIO2_32K 7 +-#define CLK_OTG_UTMI 8 +-#define CLK_AP_UART0 9 +-#define CLK_AP_UART1 10 +-#define CLK_AP_UART2 11 +-#define CLK_AP_UART3 12 +-#define CLK_AP_UART4 13 +-#define CLK_AP_I2C0 14 +-#define CLK_AP_I2C1 15 +-#define CLK_AP_I2C2 16 +-#define CLK_AP_I2C3 17 +-#define CLK_AP_I2C4 18 +-#define CLK_AP_I2C5 19 +-#define CLK_AP_I2C6 20 +-#define CLK_AP_SPI0 21 +-#define CLK_AP_SPI1 22 +-#define CLK_AP_SPI2 23 +-#define CLK_AP_SPI3 24 +-#define CLK_AP_IIS0 25 +-#define CLK_AP_IIS1 26 +-#define CLK_AP_IIS2 27 +-#define CLK_SIM0 28 +-#define CLK_SIM0_32K 29 +-#define CLK_AP_CLK_NUM (CLK_SIM0_32K + 1) +- +-#define CLK_13M 0 +-#define CLK_6M5 1 +-#define CLK_4M3 2 +-#define CLK_2M 3 +-#define CLK_250K 4 +-#define CLK_RCO_25M 5 +-#define CLK_RCO_4M 6 +-#define CLK_RCO_2M 7 +-#define CLK_EMC 8 +-#define CLK_AON_APB 9 +-#define CLK_ADI 10 +-#define CLK_AUX0 11 +-#define CLK_AUX1 12 +-#define CLK_AUX2 13 +-#define CLK_PROBE 14 +-#define CLK_PWM0 15 +-#define CLK_PWM1 16 +-#define CLK_PWM2 17 +-#define CLK_AON_THM 18 +-#define CLK_AUDIF 19 +-#define CLK_CPU_DAP 20 +-#define CLK_CPU_TS 21 +-#define CLK_DJTAG_TCK 22 +-#define CLK_EMC_REF 23 +-#define CLK_CSSYS 24 +-#define CLK_AON_PMU 25 +-#define CLK_PMU_26M 26 +-#define CLK_AON_TMR 27 +-#define CLK_POWER_CPU 28 +-#define CLK_AP_AXI 29 +-#define CLK_SDIO0_2X 30 +-#define CLK_SDIO1_2X 31 +-#define CLK_SDIO2_2X 32 +-#define CLK_EMMC_2X 33 +-#define CLK_DPU 34 +-#define CLK_DPU_DPI 35 +-#define CLK_OTG_REF 36 +-#define CLK_SDPHY_APB 37 +-#define CLK_ALG_IO_APB 38 +-#define CLK_GPU_CORE 39 +-#define CLK_GPU_SOC 40 +-#define CLK_MM_EMC 41 +-#define CLK_MM_AHB 42 +-#define CLK_BPC 43 +-#define CLK_DCAM_IF 44 +-#define CLK_ISP 45 +-#define CLK_JPG 46 +-#define CLK_CPP 47 +-#define CLK_SENSOR0 48 +-#define CLK_SENSOR1 49 +-#define CLK_SENSOR2 50 +-#define CLK_MM_VEMC 51 +-#define CLK_MM_VAHB 52 +-#define CLK_VSP 53 +-#define CLK_CORE0 54 +-#define CLK_CORE1 55 +-#define CLK_CORE2 56 +-#define CLK_CORE3 57 +-#define CLK_CORE4 58 +-#define CLK_CORE5 59 +-#define CLK_CORE6 60 +-#define CLK_CORE7 61 +-#define CLK_SCU 62 +-#define CLK_ACE 63 +-#define CLK_AXI_PERIPH 64 +-#define CLK_AXI_ACP 65 +-#define CLK_ATB 66 +-#define CLK_DEBUG_APB 67 +-#define CLK_GIC 68 +-#define CLK_PERIPH 69 +-#define CLK_AON_CLK_NUM (CLK_VSP + 1) +- +-#define CLK_OTG_EB 0 +-#define CLK_DMA_EB 1 +-#define CLK_CE_EB 2 +-#define CLK_NANDC_EB 3 +-#define CLK_SDIO0_EB 4 +-#define CLK_SDIO1_EB 5 +-#define CLK_SDIO2_EB 6 +-#define CLK_EMMC_EB 7 +-#define CLK_EMMC_32K_EB 8 +-#define CLK_SDIO0_32K_EB 9 +-#define CLK_SDIO1_32K_EB 10 +-#define CLK_SDIO2_32K_EB 11 +-#define CLK_NANDC_26M_EB 12 +-#define CLK_DMA_EB2 13 +-#define CLK_CE_EB2 14 +-#define CLK_AP_AHB_GATE_NUM (CLK_CE_EB2 + 1) +- +-#define CLK_GPIO_EB 0 +-#define CLK_PWM0_EB 1 +-#define CLK_PWM1_EB 2 +-#define CLK_PWM2_EB 3 +-#define CLK_PWM3_EB 4 +-#define CLK_KPD_EB 5 +-#define CLK_AON_SYST_EB 6 +-#define CLK_AP_SYST_EB 7 +-#define CLK_AON_TMR_EB 8 +-#define CLK_EFUSE_EB 9 +-#define CLK_EIC_EB 10 +-#define CLK_INTC_EB 11 +-#define CLK_ADI_EB 12 +-#define CLK_AUDIF_EB 13 +-#define CLK_AUD_EB 14 +-#define CLK_VBC_EB 15 +-#define CLK_PIN_EB 16 +-#define CLK_AP_WDG_EB 17 +-#define CLK_MM_EB 18 +-#define CLK_AON_APB_CKG_EB 19 +-#define CLK_CA53_TS0_EB 20 +-#define CLK_CA53_TS1_EB 21 +-#define CLK_CS53_DAP_EB 22 +-#define CLK_PMU_EB 23 +-#define CLK_THM_EB 24 +-#define CLK_AUX0_EB 25 +-#define CLK_AUX1_EB 26 +-#define CLK_AUX2_EB 27 +-#define CLK_PROBE_EB 28 +-#define CLK_EMC_REF_EB 29 +-#define CLK_CA53_WDG_EB 30 +-#define CLK_AP_TMR1_EB 31 +-#define CLK_AP_TMR2_EB 32 +-#define CLK_DISP_EMC_EB 33 +-#define CLK_ZIP_EMC_EB 34 +-#define CLK_GSP_EMC_EB 35 +-#define CLK_MM_VSP_EB 36 +-#define CLK_MDAR_EB 37 +-#define CLK_RTC4M0_CAL_EB 38 +-#define CLK_RTC4M1_CAL_EB 39 +-#define CLK_DJTAG_EB 40 +-#define CLK_MBOX_EB 41 +-#define CLK_AON_DMA_EB 42 +-#define CLK_AON_APB_DEF_EB 43 +-#define CLK_CA5_TS0_EB 44 +-#define CLK_DBG_EB 45 +-#define CLK_DBG_EMC_EB 46 +-#define CLK_CROSS_TRIG_EB 47 +-#define CLK_SERDES_DPHY_EB 48 +-#define CLK_ARCH_RTC_EB 49 +-#define CLK_KPD_RTC_EB 50 +-#define CLK_AON_SYST_RTC_EB 51 +-#define CLK_AP_SYST_RTC_EB 52 +-#define CLK_AON_TMR_RTC_EB 53 +-#define CLK_AP_TMR0_RTC_EB 54 +-#define CLK_EIC_RTC_EB 55 +-#define CLK_EIC_RTCDV5_EB 56 +-#define CLK_AP_WDG_RTC_EB 57 +-#define CLK_CA53_WDG_RTC_EB 58 +-#define CLK_THM_RTC_EB 59 +-#define CLK_ATHMA_RTC_EB 60 +-#define CLK_GTHMA_RTC_EB 61 +-#define CLK_ATHMA_RTC_A_EB 62 +-#define CLK_GTHMA_RTC_A_EB 63 +-#define CLK_AP_TMR1_RTC_EB 64 +-#define CLK_AP_TMR2_RTC_EB 65 +-#define CLK_DXCO_LC_RTC_EB 66 +-#define CLK_BB_CAL_RTC_EB 67 +-#define CLK_GNU_EB 68 +-#define CLK_DISP_EB 69 +-#define CLK_MM_EMC_EB 70 +-#define CLK_POWER_CPU_EB 71 +-#define CLK_HW_I2C_EB 72 +-#define CLK_MM_VSP_EMC_EB 73 +-#define CLK_VSP_EB 74 +-#define CLK_CSSYS_EB 75 +-#define CLK_DMC_EB 76 +-#define CLK_ROSC_EB 77 +-#define CLK_S_D_CFG_EB 78 +-#define CLK_S_D_REF_EB 79 +-#define CLK_B_DMA_EB 80 +-#define CLK_ANLG_EB 81 +-#define CLK_ANLG_APB_EB 82 +-#define CLK_BSMTMR_EB 83 +-#define CLK_AP_AXI_EB 84 +-#define CLK_AP_INTC0_EB 85 +-#define CLK_AP_INTC1_EB 86 +-#define CLK_AP_INTC2_EB 87 +-#define CLK_AP_INTC3_EB 88 +-#define CLK_AP_INTC4_EB 89 +-#define CLK_AP_INTC5_EB 90 +-#define CLK_SCC_EB 91 +-#define CLK_DPHY_CFG_EB 92 +-#define CLK_DPHY_REF_EB 93 +-#define CLK_CPHY_CFG_EB 94 +-#define CLK_OTG_REF_EB 95 +-#define CLK_SERDES_EB 96 +-#define CLK_AON_AP_EMC_EB 97 +-#define CLK_AON_APB_GATE_NUM (CLK_AON_AP_EMC_EB + 1) +- +-#define CLK_MAHB_CKG_EB 0 +-#define CLK_MDCAM_EB 1 +-#define CLK_MISP_EB 2 +-#define CLK_MAHBCSI_EB 3 +-#define CLK_MCSI_S_EB 4 +-#define CLK_MCSI_T_EB 5 +-#define CLK_DCAM_AXI_EB 6 +-#define CLK_ISP_AXI_EB 7 +-#define CLK_MCSI_EB 8 +-#define CLK_MCSI_S_CKG_EB 9 +-#define CLK_MCSI_T_CKG_EB 10 +-#define CLK_SENSOR0_EB 11 +-#define CLK_SENSOR1_EB 12 +-#define CLK_SENSOR2_EB 13 +-#define CLK_MCPHY_CFG_EB 14 +-#define CLK_MM_GATE_NUM (CLK_MCPHY_CFG_EB + 1) +- +-#define CLK_MIPI_CSI 0 +-#define CLK_MIPI_CSI_S 1 +-#define CLK_MIPI_CSI_M 2 +-#define CLK_MM_CLK_NUM (CLK_MIPI_CSI_M + 1) +- +-#define CLK_SIM0_EB 0 +-#define CLK_IIS0_EB 1 +-#define CLK_IIS1_EB 2 +-#define CLK_IIS2_EB 3 +-#define CLK_SPI0_EB 4 +-#define CLK_SPI1_EB 5 +-#define CLK_SPI2_EB 6 +-#define CLK_I2C0_EB 7 +-#define CLK_I2C1_EB 8 +-#define CLK_I2C2_EB 9 +-#define CLK_I2C3_EB 10 +-#define CLK_I2C4_EB 11 +-#define CLK_UART0_EB 12 +-#define CLK_UART1_EB 13 +-#define CLK_UART2_EB 14 +-#define CLK_UART3_EB 15 +-#define CLK_UART4_EB 16 +-#define CLK_SIM0_32K_EB 17 +-#define CLK_SPI3_EB 18 +-#define CLK_I2C5_EB 19 +-#define CLK_I2C6_EB 20 +-#define CLK_AP_APB_GATE_NUM (CLK_I2C6_EB + 1) +- +-#endif /* _DT_BINDINGS_CLK_SC9863A_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/ste-ab8500.h b/scripts/dtc/include-prefixes/dt-bindings/clock/ste-ab8500.h +deleted file mode 100644 +index fb42dd0cab5f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/ste-ab8500.h ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __STE_CLK_AB8500_H__ +-#define __STE_CLK_AB8500_H__ +- +-#define AB8500_SYSCLK_BUF2 0 +-#define AB8500_SYSCLK_BUF3 1 +-#define AB8500_SYSCLK_BUF4 2 +-#define AB8500_SYSCLK_ULP 3 +-#define AB8500_SYSCLK_INT 4 +-#define AB8500_SYSCLK_AUDIO 5 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/stih407-clks.h b/scripts/dtc/include-prefixes/dt-bindings/clock/stih407-clks.h +deleted file mode 100644 +index f0936c133772..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/stih407-clks.h ++++ /dev/null +@@ -1,91 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants clk index STMicroelectronics +- * STiH407 SoC. +- */ +-#ifndef _DT_BINDINGS_CLK_STIH407 +-#define _DT_BINDINGS_CLK_STIH407 +- +-/* CLOCKGEN A0 */ +-#define CLK_IC_LMI0 0 +-#define CLK_IC_LMI1 1 +- +-/* CLOCKGEN C0 */ +-#define CLK_ICN_GPU 0 +-#define CLK_FDMA 1 +-#define CLK_NAND 2 +-#define CLK_HVA 3 +-#define CLK_PROC_STFE 4 +-#define CLK_PROC_TP 5 +-#define CLK_RX_ICN_DMU 6 +-#define CLK_RX_ICN_DISP_0 6 +-#define CLK_RX_ICN_DISP_1 6 +-#define CLK_RX_ICN_HVA 7 +-#define CLK_RX_ICN_TS 7 +-#define CLK_ICN_CPU 8 +-#define CLK_TX_ICN_DMU 9 +-#define CLK_TX_ICN_HVA 9 +-#define CLK_TX_ICN_TS 9 +-#define CLK_ICN_COMPO 9 +-#define CLK_MMC_0 10 +-#define CLK_MMC_1 11 +-#define CLK_JPEGDEC 12 +-#define CLK_ICN_REG 13 +-#define CLK_TRACE_A9 13 +-#define CLK_PTI_STM 13 +-#define CLK_EXT2F_A9 13 +-#define CLK_IC_BDISP_0 14 +-#define CLK_IC_BDISP_1 15 +-#define CLK_PP_DMU 16 +-#define CLK_VID_DMU 17 +-#define CLK_DSS_LPC 18 +-#define CLK_ST231_AUD_0 19 +-#define CLK_ST231_GP_0 19 +-#define CLK_ST231_GP_1 20 +-#define CLK_ST231_DMU 21 +-#define CLK_ICN_LMI 22 +-#define CLK_TX_ICN_DISP_0 23 +-#define CLK_TX_ICN_DISP_1 23 +-#define CLK_ICN_SBC 24 +-#define CLK_STFE_FRC2 25 +-#define CLK_ETH_PHY 26 +-#define CLK_ETH_REF_PHYCLK 27 +-#define CLK_FLASH_PROMIP 28 +-#define CLK_MAIN_DISP 29 +-#define CLK_AUX_DISP 30 +-#define CLK_COMPO_DVP 31 +- +-/* CLOCKGEN D0 */ +-#define CLK_PCM_0 0 +-#define CLK_PCM_1 1 +-#define CLK_PCM_2 2 +-#define CLK_SPDIFF 3 +- +-/* CLOCKGEN D2 */ +-#define CLK_PIX_MAIN_DISP 0 +-#define CLK_PIX_PIP 1 +-#define CLK_PIX_GDP1 2 +-#define CLK_PIX_GDP2 3 +-#define CLK_PIX_GDP3 4 +-#define CLK_PIX_GDP4 5 +-#define CLK_PIX_AUX_DISP 6 +-#define CLK_DENC 7 +-#define CLK_PIX_HDDAC 8 +-#define CLK_HDDAC 9 +-#define CLK_SDDAC 10 +-#define CLK_PIX_DVO 11 +-#define CLK_DVO 12 +-#define CLK_PIX_HDMI 13 +-#define CLK_TMDS_HDMI 14 +-#define CLK_REF_HDMIPHY 15 +- +-/* CLOCKGEN D3 */ +-#define CLK_STFE_FRC1 0 +-#define CLK_TSOUT_0 1 +-#define CLK_TSOUT_1 2 +-#define CLK_MCHI 3 +-#define CLK_VSENS_COMPO 4 +-#define CLK_FRC1_REMOTE 5 +-#define CLK_LPC_0 6 +-#define CLK_LPC_1 7 +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/stih410-clks.h b/scripts/dtc/include-prefixes/dt-bindings/clock/stih410-clks.h +deleted file mode 100644 +index 90cbe6154c39..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/stih410-clks.h ++++ /dev/null +@@ -1,26 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants clk index STMicroelectronics +- * STiH410 SoC. +- */ +-#ifndef _DT_BINDINGS_CLK_STIH410 +-#define _DT_BINDINGS_CLK_STIH410 +- +-#include "stih407-clks.h" +- +-/* STiH410 introduces new clock outputs compared to STiH407 */ +- +-/* CLOCKGEN C0 */ +-#define CLK_TX_ICN_HADES 32 +-#define CLK_RX_ICN_HADES 33 +-#define CLK_ICN_REG_16 34 +-#define CLK_PP_HADES 35 +-#define CLK_CLUST_HADES 36 +-#define CLK_HWPE_HADES 37 +-#define CLK_FC_HADES 38 +- +-/* CLOCKGEN D0 */ +-#define CLK_PCMR10_MASTER 4 +-#define CLK_USB2_PHY 5 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/stih416-clks.h b/scripts/dtc/include-prefixes/dt-bindings/clock/stih416-clks.h +deleted file mode 100644 +index 74302278024e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/stih416-clks.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants clk index STMicroelectronics +- * STiH416 SoC. +- */ +-#ifndef _CLK_STIH416 +-#define _CLK_STIH416 +- +-/* CLOCKGEN A0 */ +-#define CLK_ICN_REG 0 +-#define CLK_ETH1_PHY 4 +- +-/* CLOCKGEN A1 */ +-#define CLK_ICN_IF_2 0 +-#define CLK_GMAC0_PHY 3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/stih418-clks.h b/scripts/dtc/include-prefixes/dt-bindings/clock/stih418-clks.h +deleted file mode 100644 +index 0e7fba0c52b3..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/stih418-clks.h ++++ /dev/null +@@ -1,35 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants clk index STMicroelectronics +- * STiH418 SoC. +- */ +-#ifndef _DT_BINDINGS_CLK_STIH418 +-#define _DT_BINDINGS_CLK_STIH418 +- +-#include "stih410-clks.h" +- +-/* STiH418 introduces new clock outputs compared to STiH410 */ +- +-/* CLOCKGEN C0 */ +-#define CLK_PROC_BDISP_0 14 +-#define CLK_PROC_BDISP_1 15 +-#define CLK_TX_ICN_1 23 +-#define CLK_ETH_PHYREF 27 +-#define CLK_PP_HEVC 35 +-#define CLK_CLUST_HEVC 36 +-#define CLK_HWPE_HEVC 37 +-#define CLK_FC_HEVC 38 +-#define CLK_PROC_MIXER 39 +-#define CLK_PROC_SC 40 +-#define CLK_AVSP_HEVC 41 +- +-/* CLOCKGEN D2 */ +-#undef CLK_PIX_PIP +-#undef CLK_PIX_GDP1 +-#undef CLK_PIX_GDP2 +-#undef CLK_PIX_GDP3 +-#undef CLK_PIX_GDP4 +- +-#define CLK_TMDS_HDMI_DIV2 5 +-#define CLK_VP9 47 +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/stm32fx-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/stm32fx-clock.h +deleted file mode 100644 +index 1cc89c548578..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/stm32fx-clock.h ++++ /dev/null +@@ -1,63 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * stm32fx-clock.h +- * +- * Copyright (C) 2016 STMicroelectronics +- * Author: Gabriel Fernandez for STMicroelectronics. +- */ +- +-/* +- * List of clocks wich are not derived from system clock (SYSCLOCK) +- * +- * The index of these clocks is the secondary index of DT bindings +- * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt) +- * +- * e.g: +- ; +-*/ +- +-#ifndef _DT_BINDINGS_CLK_STMFX_H +-#define _DT_BINDINGS_CLK_STMFX_H +- +-#define SYSTICK 0 +-#define FCLK 1 +-#define CLK_LSI 2 +-#define CLK_LSE 3 +-#define CLK_HSE_RTC 4 +-#define CLK_RTC 5 +-#define PLL_VCO_I2S 6 +-#define PLL_VCO_SAI 7 +-#define CLK_LCD 8 +-#define CLK_I2S 9 +-#define CLK_SAI1 10 +-#define CLK_SAI2 11 +-#define CLK_I2SQ_PDIV 12 +-#define CLK_SAIQ_PDIV 13 +-#define CLK_HSI 14 +-#define CLK_SYSCLK 15 +-#define CLK_F469_DSI 16 +- +-#define END_PRIMARY_CLK 17 +- +-#define CLK_HDMI_CEC 16 +-#define CLK_SPDIF 17 +-#define CLK_USART1 18 +-#define CLK_USART2 19 +-#define CLK_USART3 20 +-#define CLK_UART4 21 +-#define CLK_UART5 22 +-#define CLK_USART6 23 +-#define CLK_UART7 24 +-#define CLK_UART8 25 +-#define CLK_I2C1 26 +-#define CLK_I2C2 27 +-#define CLK_I2C3 28 +-#define CLK_I2C4 29 +-#define CLK_LPTIMER 30 +-#define CLK_PLL_SRC 31 +-#define CLK_DFSDM1 32 +-#define CLK_ADFSDM1 33 +-#define CLK_F769_DSI 34 +-#define END_PRIMARY_CLK_F7 35 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/stm32h7-clks.h b/scripts/dtc/include-prefixes/dt-bindings/clock/stm32h7-clks.h +deleted file mode 100644 +index 6637272b3242..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/stm32h7-clks.h ++++ /dev/null +@@ -1,165 +0,0 @@ +-/* SYS, CORE AND BUS CLOCKS */ +-#define SYS_D1CPRE 0 +-#define HCLK 1 +-#define PCLK1 2 +-#define PCLK2 3 +-#define PCLK3 4 +-#define PCLK4 5 +-#define HSI_DIV 6 +-#define HSE_1M 7 +-#define I2S_CKIN 8 +-#define CK_DSI_PHY 9 +-#define HSE_CK 10 +-#define LSE_CK 11 +-#define CSI_KER_DIV122 12 +-#define RTC_CK 13 +-#define CPU_SYSTICK 14 +- +-/* OSCILLATOR BANK */ +-#define OSC_BANK 18 +-#define HSI_CK 18 +-#define HSI_KER_CK 19 +-#define CSI_CK 20 +-#define CSI_KER_CK 21 +-#define RC48_CK 22 +-#define LSI_CK 23 +- +-/* MCLOCK BANK */ +-#define MCLK_BANK 28 +-#define PER_CK 28 +-#define PLLSRC 29 +-#define SYS_CK 30 +-#define TRACEIN_CK 31 +- +-/* ODF BANK */ +-#define ODF_BANK 32 +-#define PLL1_P 32 +-#define PLL1_Q 33 +-#define PLL1_R 34 +-#define PLL2_P 35 +-#define PLL2_Q 36 +-#define PLL2_R 37 +-#define PLL3_P 38 +-#define PLL3_Q 39 +-#define PLL3_R 40 +- +-/* MCO BANK */ +-#define MCO_BANK 41 +-#define MCO1 41 +-#define MCO2 42 +- +-/* PERIF BANK */ +-#define PERIF_BANK 50 +-#define D1SRAM1_CK 50 +-#define ITCM_CK 51 +-#define DTCM2_CK 52 +-#define DTCM1_CK 53 +-#define FLITF_CK 54 +-#define JPGDEC_CK 55 +-#define DMA2D_CK 56 +-#define MDMA_CK 57 +-#define USB2ULPI_CK 58 +-#define USB1ULPI_CK 59 +-#define ETH1RX_CK 60 +-#define ETH1TX_CK 61 +-#define ETH1MAC_CK 62 +-#define ART_CK 63 +-#define DMA2_CK 64 +-#define DMA1_CK 65 +-#define D2SRAM3_CK 66 +-#define D2SRAM2_CK 67 +-#define D2SRAM1_CK 68 +-#define HASH_CK 69 +-#define CRYPT_CK 70 +-#define CAMITF_CK 71 +-#define BKPRAM_CK 72 +-#define HSEM_CK 73 +-#define BDMA_CK 74 +-#define CRC_CK 75 +-#define GPIOK_CK 76 +-#define GPIOJ_CK 77 +-#define GPIOI_CK 78 +-#define GPIOH_CK 79 +-#define GPIOG_CK 80 +-#define GPIOF_CK 81 +-#define GPIOE_CK 82 +-#define GPIOD_CK 83 +-#define GPIOC_CK 84 +-#define GPIOB_CK 85 +-#define GPIOA_CK 86 +-#define WWDG1_CK 87 +-#define DAC12_CK 88 +-#define WWDG2_CK 89 +-#define TIM14_CK 90 +-#define TIM13_CK 91 +-#define TIM12_CK 92 +-#define TIM7_CK 93 +-#define TIM6_CK 94 +-#define TIM5_CK 95 +-#define TIM4_CK 96 +-#define TIM3_CK 97 +-#define TIM2_CK 98 +-#define MDIOS_CK 99 +-#define OPAMP_CK 100 +-#define CRS_CK 101 +-#define TIM17_CK 102 +-#define TIM16_CK 103 +-#define TIM15_CK 104 +-#define TIM8_CK 105 +-#define TIM1_CK 106 +-#define TMPSENS_CK 107 +-#define RTCAPB_CK 108 +-#define VREF_CK 109 +-#define COMP12_CK 110 +-#define SYSCFG_CK 111 +- +-/* KERNEL BANK */ +-#define KERN_BANK 120 +-#define SDMMC1_CK 120 +-#define QUADSPI_CK 121 +-#define FMC_CK 122 +-#define USB2OTG_CK 123 +-#define USB1OTG_CK 124 +-#define ADC12_CK 125 +-#define SDMMC2_CK 126 +-#define RNG_CK 127 +-#define ADC3_CK 128 +-#define DSI_CK 129 +-#define LTDC_CK 130 +-#define USART8_CK 131 +-#define USART7_CK 132 +-#define HDMICEC_CK 133 +-#define I2C3_CK 134 +-#define I2C2_CK 135 +-#define I2C1_CK 136 +-#define UART5_CK 137 +-#define UART4_CK 138 +-#define USART3_CK 139 +-#define USART2_CK 140 +-#define SPDIFRX_CK 141 +-#define SPI3_CK 142 +-#define SPI2_CK 143 +-#define LPTIM1_CK 144 +-#define FDCAN_CK 145 +-#define SWP_CK 146 +-#define HRTIM_CK 147 +-#define DFSDM1_CK 148 +-#define SAI3_CK 149 +-#define SAI2_CK 150 +-#define SAI1_CK 151 +-#define SPI5_CK 152 +-#define SPI4_CK 153 +-#define SPI1_CK 154 +-#define USART6_CK 155 +-#define USART1_CK 156 +-#define SAI4B_CK 157 +-#define SAI4A_CK 158 +-#define LPTIM5_CK 159 +-#define LPTIM4_CK 160 +-#define LPTIM3_CK 161 +-#define LPTIM2_CK 162 +-#define I2C4_CK 163 +-#define SPI6_CK 164 +-#define LPUART1_CK 165 +- +-#define STM32H7_MAX_CLKS 166 +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/stm32mp1-clks.h b/scripts/dtc/include-prefixes/dt-bindings/clock/stm32mp1-clks.h +deleted file mode 100644 +index e02770b98e6c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/stm32mp1-clks.h ++++ /dev/null +@@ -1,278 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +-/* +- * Copyright (C) STMicroelectronics 2018 - All Rights Reserved +- * Author: Gabriel Fernandez for STMicroelectronics. +- */ +- +-#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_ +-#define _DT_BINDINGS_STM32MP1_CLKS_H_ +- +-/* OSCILLATOR clocks */ +-#define CK_HSE 0 +-#define CK_CSI 1 +-#define CK_LSI 2 +-#define CK_LSE 3 +-#define CK_HSI 4 +-#define CK_HSE_DIV2 5 +- +-/* Bus clocks */ +-#define TIM2 6 +-#define TIM3 7 +-#define TIM4 8 +-#define TIM5 9 +-#define TIM6 10 +-#define TIM7 11 +-#define TIM12 12 +-#define TIM13 13 +-#define TIM14 14 +-#define LPTIM1 15 +-#define SPI2 16 +-#define SPI3 17 +-#define USART2 18 +-#define USART3 19 +-#define UART4 20 +-#define UART5 21 +-#define UART7 22 +-#define UART8 23 +-#define I2C1 24 +-#define I2C2 25 +-#define I2C3 26 +-#define I2C5 27 +-#define SPDIF 28 +-#define CEC 29 +-#define DAC12 30 +-#define MDIO 31 +-#define TIM1 32 +-#define TIM8 33 +-#define TIM15 34 +-#define TIM16 35 +-#define TIM17 36 +-#define SPI1 37 +-#define SPI4 38 +-#define SPI5 39 +-#define USART6 40 +-#define SAI1 41 +-#define SAI2 42 +-#define SAI3 43 +-#define DFSDM 44 +-#define FDCAN 45 +-#define LPTIM2 46 +-#define LPTIM3 47 +-#define LPTIM4 48 +-#define LPTIM5 49 +-#define SAI4 50 +-#define SYSCFG 51 +-#define VREF 52 +-#define TMPSENS 53 +-#define PMBCTRL 54 +-#define HDP 55 +-#define LTDC 56 +-#define DSI 57 +-#define IWDG2 58 +-#define USBPHY 59 +-#define STGENRO 60 +-#define SPI6 61 +-#define I2C4 62 +-#define I2C6 63 +-#define USART1 64 +-#define RTCAPB 65 +-#define TZC1 66 +-#define TZPC 67 +-#define IWDG1 68 +-#define BSEC 69 +-#define STGEN 70 +-#define DMA1 71 +-#define DMA2 72 +-#define DMAMUX 73 +-#define ADC12 74 +-#define USBO 75 +-#define SDMMC3 76 +-#define DCMI 77 +-#define CRYP2 78 +-#define HASH2 79 +-#define RNG2 80 +-#define CRC2 81 +-#define HSEM 82 +-#define IPCC 83 +-#define GPIOA 84 +-#define GPIOB 85 +-#define GPIOC 86 +-#define GPIOD 87 +-#define GPIOE 88 +-#define GPIOF 89 +-#define GPIOG 90 +-#define GPIOH 91 +-#define GPIOI 92 +-#define GPIOJ 93 +-#define GPIOK 94 +-#define GPIOZ 95 +-#define CRYP1 96 +-#define HASH1 97 +-#define RNG1 98 +-#define BKPSRAM 99 +-#define MDMA 100 +-#define GPU 101 +-#define ETHCK 102 +-#define ETHTX 103 +-#define ETHRX 104 +-#define ETHMAC 105 +-#define FMC 106 +-#define QSPI 107 +-#define SDMMC1 108 +-#define SDMMC2 109 +-#define CRC1 110 +-#define USBH 111 +-#define ETHSTP 112 +-#define TZC2 113 +- +-/* Kernel clocks */ +-#define SDMMC1_K 118 +-#define SDMMC2_K 119 +-#define SDMMC3_K 120 +-#define FMC_K 121 +-#define QSPI_K 122 +-#define ETHCK_K 123 +-#define RNG1_K 124 +-#define RNG2_K 125 +-#define GPU_K 126 +-#define USBPHY_K 127 +-#define STGEN_K 128 +-#define SPDIF_K 129 +-#define SPI1_K 130 +-#define SPI2_K 131 +-#define SPI3_K 132 +-#define SPI4_K 133 +-#define SPI5_K 134 +-#define SPI6_K 135 +-#define CEC_K 136 +-#define I2C1_K 137 +-#define I2C2_K 138 +-#define I2C3_K 139 +-#define I2C4_K 140 +-#define I2C5_K 141 +-#define I2C6_K 142 +-#define LPTIM1_K 143 +-#define LPTIM2_K 144 +-#define LPTIM3_K 145 +-#define LPTIM4_K 146 +-#define LPTIM5_K 147 +-#define USART1_K 148 +-#define USART2_K 149 +-#define USART3_K 150 +-#define UART4_K 151 +-#define UART5_K 152 +-#define USART6_K 153 +-#define UART7_K 154 +-#define UART8_K 155 +-#define DFSDM_K 156 +-#define FDCAN_K 157 +-#define SAI1_K 158 +-#define SAI2_K 159 +-#define SAI3_K 160 +-#define SAI4_K 161 +-#define ADC12_K 162 +-#define DSI_K 163 +-#define DSI_PX 164 +-#define ADFSDM_K 165 +-#define USBO_K 166 +-#define LTDC_PX 167 +-#define DAC12_K 168 +-#define ETHPTP_K 169 +- +-/* PLL */ +-#define PLL1 176 +-#define PLL2 177 +-#define PLL3 178 +-#define PLL4 179 +- +-/* ODF */ +-#define PLL1_P 180 +-#define PLL1_Q 181 +-#define PLL1_R 182 +-#define PLL2_P 183 +-#define PLL2_Q 184 +-#define PLL2_R 185 +-#define PLL3_P 186 +-#define PLL3_Q 187 +-#define PLL3_R 188 +-#define PLL4_P 189 +-#define PLL4_Q 190 +-#define PLL4_R 191 +- +-/* AUX */ +-#define RTC 192 +- +-/* MCLK */ +-#define CK_PER 193 +-#define CK_MPU 194 +-#define CK_AXI 195 +-#define CK_MCU 196 +- +-/* Time base */ +-#define TIM2_K 197 +-#define TIM3_K 198 +-#define TIM4_K 199 +-#define TIM5_K 200 +-#define TIM6_K 201 +-#define TIM7_K 202 +-#define TIM12_K 203 +-#define TIM13_K 204 +-#define TIM14_K 205 +-#define TIM1_K 206 +-#define TIM8_K 207 +-#define TIM15_K 208 +-#define TIM16_K 209 +-#define TIM17_K 210 +- +-/* MCO clocks */ +-#define CK_MCO1 211 +-#define CK_MCO2 212 +- +-/* TRACE & DEBUG clocks */ +-#define CK_DBG 214 +-#define CK_TRACE 215 +- +-/* DDR */ +-#define DDRC1 220 +-#define DDRC1LP 221 +-#define DDRC2 222 +-#define DDRC2LP 223 +-#define DDRPHYC 224 +-#define DDRPHYCLP 225 +-#define DDRCAPB 226 +-#define DDRCAPBLP 227 +-#define AXIDCG 228 +-#define DDRPHYCAPB 229 +-#define DDRPHYCAPBLP 230 +-#define DDRPERFM 231 +- +-#define STM32MP1_LAST_CLK 232 +- +-/* SCMI clock identifiers */ +-#define CK_SCMI0_HSE 0 +-#define CK_SCMI0_HSI 1 +-#define CK_SCMI0_CSI 2 +-#define CK_SCMI0_LSE 3 +-#define CK_SCMI0_LSI 4 +-#define CK_SCMI0_PLL2_Q 5 +-#define CK_SCMI0_PLL2_R 6 +-#define CK_SCMI0_MPU 7 +-#define CK_SCMI0_AXI 8 +-#define CK_SCMI0_BSEC 9 +-#define CK_SCMI0_CRYP1 10 +-#define CK_SCMI0_GPIOZ 11 +-#define CK_SCMI0_HASH1 12 +-#define CK_SCMI0_I2C4 13 +-#define CK_SCMI0_I2C6 14 +-#define CK_SCMI0_IWDG1 15 +-#define CK_SCMI0_RNG1 16 +-#define CK_SCMI0_RTC 17 +-#define CK_SCMI0_RTCAPB 18 +-#define CK_SCMI0_SPI6 19 +-#define CK_SCMI0_USART1 20 +- +-#define CK_SCMI1_PLL3_Q 0 +-#define CK_SCMI1_PLL3_R 1 +-#define CK_SCMI1_MCU 2 +- +-#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/stratix10-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/stratix10-clock.h +deleted file mode 100644 +index 08b98e20b7cc..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/stratix10-clock.h ++++ /dev/null +@@ -1,86 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2017, Intel Corporation +- */ +- +-#ifndef __STRATIX10_CLOCK_H +-#define __STRATIX10_CLOCK_H +- +-/* fixed rate clocks */ +-#define STRATIX10_OSC1 0 +-#define STRATIX10_CB_INTOSC_HS_DIV2_CLK 1 +-#define STRATIX10_CB_INTOSC_LS_CLK 2 +-#define STRATIX10_F2S_FREE_CLK 3 +- +-/* fixed factor clocks */ +-#define STRATIX10_L4_SYS_FREE_CLK 4 +-#define STRATIX10_MPU_PERIPH_CLK 5 +-#define STRATIX10_MPU_L2RAM_CLK 6 +-#define STRATIX10_SDMMC_CIU_CLK 7 +- +-/* PLL clocks */ +-#define STRATIX10_MAIN_PLL_CLK 8 +-#define STRATIX10_PERIPH_PLL_CLK 9 +-#define STRATIX10_BOOT_CLK 10 +- +-/* Periph clocks */ +-#define STRATIX10_MAIN_MPU_BASE_CLK 11 +-#define STRATIX10_MAIN_NOC_BASE_CLK 12 +-#define STRATIX10_MAIN_EMACA_CLK 13 +-#define STRATIX10_MAIN_EMACB_CLK 14 +-#define STRATIX10_MAIN_EMAC_PTP_CLK 15 +-#define STRATIX10_MAIN_GPIO_DB_CLK 16 +-#define STRATIX10_MAIN_SDMMC_CLK 17 +-#define STRATIX10_MAIN_S2F_USR0_CLK 18 +-#define STRATIX10_MAIN_S2F_USR1_CLK 19 +-#define STRATIX10_MAIN_PSI_REF_CLK 20 +- +-#define STRATIX10_PERI_MPU_BASE_CLK 21 +-#define STRATIX10_PERI_NOC_BASE_CLK 22 +-#define STRATIX10_PERI_EMACA_CLK 23 +-#define STRATIX10_PERI_EMACB_CLK 24 +-#define STRATIX10_PERI_EMAC_PTP_CLK 25 +-#define STRATIX10_PERI_GPIO_DB_CLK 26 +-#define STRATIX10_PERI_SDMMC_CLK 27 +-#define STRATIX10_PERI_S2F_USR0_CLK 28 +-#define STRATIX10_PERI_S2F_USR1_CLK 29 +-#define STRATIX10_PERI_PSI_REF_CLK 30 +- +-#define STRATIX10_MPU_FREE_CLK 31 +-#define STRATIX10_NOC_FREE_CLK 32 +-#define STRATIX10_S2F_USR0_CLK 33 +-#define STRATIX10_NOC_CLK 34 +-#define STRATIX10_EMAC_A_FREE_CLK 35 +-#define STRATIX10_EMAC_B_FREE_CLK 36 +-#define STRATIX10_EMAC_PTP_FREE_CLK 37 +-#define STRATIX10_GPIO_DB_FREE_CLK 38 +-#define STRATIX10_SDMMC_FREE_CLK 39 +-#define STRATIX10_S2F_USER1_FREE_CLK 40 +-#define STRATIX10_PSI_REF_FREE_CLK 41 +- +-/* Gate clocks */ +-#define STRATIX10_MPU_CLK 42 +-#define STRATIX10_L4_MAIN_CLK 43 +-#define STRATIX10_L4_MP_CLK 44 +-#define STRATIX10_L4_SP_CLK 45 +-#define STRATIX10_CS_AT_CLK 46 +-#define STRATIX10_CS_TRACE_CLK 47 +-#define STRATIX10_CS_PDBG_CLK 48 +-#define STRATIX10_CS_TIMER_CLK 49 +-#define STRATIX10_S2F_USER0_CLK 50 +-#define STRATIX10_S2F_USER1_CLK 51 +-#define STRATIX10_EMAC0_CLK 52 +-#define STRATIX10_EMAC1_CLK 53 +-#define STRATIX10_EMAC2_CLK 54 +-#define STRATIX10_EMAC_PTP_CLK 55 +-#define STRATIX10_GPIO_DB_CLK 56 +-#define STRATIX10_SDMMC_CLK 57 +-#define STRATIX10_PSI_REF_CLK 58 +-#define STRATIX10_USB_CLK 59 +-#define STRATIX10_SPI_M_CLK 60 +-#define STRATIX10_NAND_CLK 61 +-#define STRATIX10_NAND_X_CLK 62 +-#define STRATIX10_NAND_ECC_CLK 63 +-#define STRATIX10_NUM_CLKS 64 +- +-#endif /* __STRATIX10_CLOCK_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun4i-a10-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun4i-a10-ccu.h +deleted file mode 100644 +index e4fa61be5c75..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun4i-a10-ccu.h ++++ /dev/null +@@ -1,202 +0,0 @@ +-/* +- * Copyright (C) 2017 Priit Laes +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_ +-#define _DT_BINDINGS_CLK_SUN4I_A10_H_ +- +-#define CLK_HOSC 1 +-#define CLK_PLL_VIDEO0_2X 9 +-#define CLK_PLL_VIDEO1_2X 18 +-#define CLK_CPU 20 +- +-/* AHB Gates */ +-#define CLK_AHB_OTG 26 +-#define CLK_AHB_EHCI0 27 +-#define CLK_AHB_OHCI0 28 +-#define CLK_AHB_EHCI1 29 +-#define CLK_AHB_OHCI1 30 +-#define CLK_AHB_SS 31 +-#define CLK_AHB_DMA 32 +-#define CLK_AHB_BIST 33 +-#define CLK_AHB_MMC0 34 +-#define CLK_AHB_MMC1 35 +-#define CLK_AHB_MMC2 36 +-#define CLK_AHB_MMC3 37 +-#define CLK_AHB_MS 38 +-#define CLK_AHB_NAND 39 +-#define CLK_AHB_SDRAM 40 +-#define CLK_AHB_ACE 41 +-#define CLK_AHB_EMAC 42 +-#define CLK_AHB_TS 43 +-#define CLK_AHB_SPI0 44 +-#define CLK_AHB_SPI1 45 +-#define CLK_AHB_SPI2 46 +-#define CLK_AHB_SPI3 47 +-#define CLK_AHB_PATA 48 +-#define CLK_AHB_SATA 49 +-#define CLK_AHB_GPS 50 +-#define CLK_AHB_HSTIMER 51 +-#define CLK_AHB_VE 52 +-#define CLK_AHB_TVD 53 +-#define CLK_AHB_TVE0 54 +-#define CLK_AHB_TVE1 55 +-#define CLK_AHB_LCD0 56 +-#define CLK_AHB_LCD1 57 +-#define CLK_AHB_CSI0 58 +-#define CLK_AHB_CSI1 59 +-#define CLK_AHB_HDMI0 60 +-#define CLK_AHB_HDMI1 61 +-#define CLK_AHB_DE_BE0 62 +-#define CLK_AHB_DE_BE1 63 +-#define CLK_AHB_DE_FE0 64 +-#define CLK_AHB_DE_FE1 65 +-#define CLK_AHB_GMAC 66 +-#define CLK_AHB_MP 67 +-#define CLK_AHB_GPU 68 +- +-/* APB0 Gates */ +-#define CLK_APB0_CODEC 69 +-#define CLK_APB0_SPDIF 70 +-#define CLK_APB0_I2S0 71 +-#define CLK_APB0_AC97 72 +-#define CLK_APB0_I2S1 73 +-#define CLK_APB0_PIO 74 +-#define CLK_APB0_IR0 75 +-#define CLK_APB0_IR1 76 +-#define CLK_APB0_I2S2 77 +-#define CLK_APB0_KEYPAD 78 +- +-/* APB1 Gates */ +-#define CLK_APB1_I2C0 79 +-#define CLK_APB1_I2C1 80 +-#define CLK_APB1_I2C2 81 +-#define CLK_APB1_I2C3 82 +-#define CLK_APB1_CAN 83 +-#define CLK_APB1_SCR 84 +-#define CLK_APB1_PS20 85 +-#define CLK_APB1_PS21 86 +-#define CLK_APB1_I2C4 87 +-#define CLK_APB1_UART0 88 +-#define CLK_APB1_UART1 89 +-#define CLK_APB1_UART2 90 +-#define CLK_APB1_UART3 91 +-#define CLK_APB1_UART4 92 +-#define CLK_APB1_UART5 93 +-#define CLK_APB1_UART6 94 +-#define CLK_APB1_UART7 95 +- +-/* IP clocks */ +-#define CLK_NAND 96 +-#define CLK_MS 97 +-#define CLK_MMC0 98 +-#define CLK_MMC0_OUTPUT 99 +-#define CLK_MMC0_SAMPLE 100 +-#define CLK_MMC1 101 +-#define CLK_MMC1_OUTPUT 102 +-#define CLK_MMC1_SAMPLE 103 +-#define CLK_MMC2 104 +-#define CLK_MMC2_OUTPUT 105 +-#define CLK_MMC2_SAMPLE 106 +-#define CLK_MMC3 107 +-#define CLK_MMC3_OUTPUT 108 +-#define CLK_MMC3_SAMPLE 109 +-#define CLK_TS 110 +-#define CLK_SS 111 +-#define CLK_SPI0 112 +-#define CLK_SPI1 113 +-#define CLK_SPI2 114 +-#define CLK_PATA 115 +-#define CLK_IR0 116 +-#define CLK_IR1 117 +-#define CLK_I2S0 118 +-#define CLK_AC97 119 +-#define CLK_SPDIF 120 +-#define CLK_KEYPAD 121 +-#define CLK_SATA 122 +-#define CLK_USB_OHCI0 123 +-#define CLK_USB_OHCI1 124 +-#define CLK_USB_PHY 125 +-#define CLK_GPS 126 +-#define CLK_SPI3 127 +-#define CLK_I2S1 128 +-#define CLK_I2S2 129 +- +-/* DRAM Gates */ +-#define CLK_DRAM_VE 130 +-#define CLK_DRAM_CSI0 131 +-#define CLK_DRAM_CSI1 132 +-#define CLK_DRAM_TS 133 +-#define CLK_DRAM_TVD 134 +-#define CLK_DRAM_TVE0 135 +-#define CLK_DRAM_TVE1 136 +-#define CLK_DRAM_OUT 137 +-#define CLK_DRAM_DE_FE1 138 +-#define CLK_DRAM_DE_FE0 139 +-#define CLK_DRAM_DE_BE0 140 +-#define CLK_DRAM_DE_BE1 141 +-#define CLK_DRAM_MP 142 +-#define CLK_DRAM_ACE 143 +- +-/* Display Engine Clocks */ +-#define CLK_DE_BE0 144 +-#define CLK_DE_BE1 145 +-#define CLK_DE_FE0 146 +-#define CLK_DE_FE1 147 +-#define CLK_DE_MP 148 +-#define CLK_TCON0_CH0 149 +-#define CLK_TCON1_CH0 150 +-#define CLK_CSI_SCLK 151 +-#define CLK_TVD_SCLK2 152 +-#define CLK_TVD 153 +-#define CLK_TCON0_CH1_SCLK2 154 +-#define CLK_TCON0_CH1 155 +-#define CLK_TCON1_CH1_SCLK2 156 +-#define CLK_TCON1_CH1 157 +-#define CLK_CSI0 158 +-#define CLK_CSI1 159 +-#define CLK_CODEC 160 +-#define CLK_VE 161 +-#define CLK_AVS 162 +-#define CLK_ACE 163 +-#define CLK_HDMI 164 +-#define CLK_GPU 165 +- +-#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun4i-a10-pll2.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun4i-a10-pll2.h +deleted file mode 100644 +index 071c8112d531..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun4i-a10-pll2.h ++++ /dev/null +@@ -1,53 +0,0 @@ +-/* +- * Copyright 2015 Maxime Ripard +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ +-#define __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ +- +-#define SUN4I_A10_PLL2_1X 0 +-#define SUN4I_A10_PLL2_2X 1 +-#define SUN4I_A10_PLL2_4X 2 +-#define SUN4I_A10_PLL2_8X 3 +- +-#endif /* __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-a100-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-a100-ccu.h +deleted file mode 100644 +index 28dc36e1a232..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-a100-ccu.h ++++ /dev/null +@@ -1,116 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +-/* +- * Copyright (c) 2020 Yangtao Li +- */ +- +-#ifndef _DT_BINDINGS_CLK_SUN50I_A100_H_ +-#define _DT_BINDINGS_CLK_SUN50I_A100_H_ +- +-#define CLK_PLL_PERIPH0 3 +- +-#define CLK_CPUX 24 +- +-#define CLK_APB1 29 +- +-#define CLK_MBUS 31 +-#define CLK_DE 32 +-#define CLK_BUS_DE 33 +-#define CLK_G2D 34 +-#define CLK_BUS_G2D 35 +-#define CLK_GPU 36 +-#define CLK_BUS_GPU 37 +-#define CLK_CE 38 +-#define CLK_BUS_CE 39 +-#define CLK_VE 40 +-#define CLK_BUS_VE 41 +-#define CLK_BUS_DMA 42 +-#define CLK_BUS_MSGBOX 43 +-#define CLK_BUS_SPINLOCK 44 +-#define CLK_BUS_HSTIMER 45 +-#define CLK_AVS 46 +-#define CLK_BUS_DBG 47 +-#define CLK_BUS_PSI 48 +-#define CLK_BUS_PWM 49 +-#define CLK_BUS_IOMMU 50 +-#define CLK_MBUS_DMA 51 +-#define CLK_MBUS_VE 52 +-#define CLK_MBUS_CE 53 +-#define CLK_MBUS_NAND 54 +-#define CLK_MBUS_CSI 55 +-#define CLK_MBUS_ISP 56 +-#define CLK_MBUS_G2D 57 +- +-#define CLK_NAND0 59 +-#define CLK_NAND1 60 +-#define CLK_BUS_NAND 61 +-#define CLK_MMC0 62 +-#define CLK_MMC1 63 +-#define CLK_MMC2 64 +-#define CLK_MMC3 65 +-#define CLK_BUS_MMC0 66 +-#define CLK_BUS_MMC1 67 +-#define CLK_BUS_MMC2 68 +-#define CLK_BUS_UART0 69 +-#define CLK_BUS_UART1 70 +-#define CLK_BUS_UART2 71 +-#define CLK_BUS_UART3 72 +-#define CLK_BUS_UART4 73 +-#define CLK_BUS_I2C0 74 +-#define CLK_BUS_I2C1 75 +-#define CLK_BUS_I2C2 76 +-#define CLK_BUS_I2C3 77 +-#define CLK_SPI0 78 +-#define CLK_SPI1 79 +-#define CLK_SPI2 80 +-#define CLK_BUS_SPI0 81 +-#define CLK_BUS_SPI1 82 +-#define CLK_BUS_SPI2 83 +-#define CLK_EMAC_25M 84 +-#define CLK_BUS_EMAC 85 +-#define CLK_IR_RX 86 +-#define CLK_BUS_IR_RX 87 +-#define CLK_IR_TX 88 +-#define CLK_BUS_IR_TX 89 +-#define CLK_BUS_GPADC 90 +-#define CLK_BUS_THS 91 +-#define CLK_I2S0 92 +-#define CLK_I2S1 93 +-#define CLK_I2S2 94 +-#define CLK_I2S3 95 +-#define CLK_BUS_I2S0 96 +-#define CLK_BUS_I2S1 97 +-#define CLK_BUS_I2S2 98 +-#define CLK_BUS_I2S3 99 +-#define CLK_SPDIF 100 +-#define CLK_BUS_SPDIF 101 +-#define CLK_DMIC 102 +-#define CLK_BUS_DMIC 103 +-#define CLK_AUDIO_DAC 104 +-#define CLK_AUDIO_ADC 105 +-#define CLK_AUDIO_4X 106 +-#define CLK_BUS_AUDIO_CODEC 107 +-#define CLK_USB_OHCI0 108 +-#define CLK_USB_PHY0 109 +-#define CLK_USB_OHCI1 110 +-#define CLK_USB_PHY1 111 +-#define CLK_BUS_OHCI0 112 +-#define CLK_BUS_OHCI1 113 +-#define CLK_BUS_EHCI0 114 +-#define CLK_BUS_EHCI1 115 +-#define CLK_BUS_OTG 116 +-#define CLK_BUS_LRADC 117 +-#define CLK_BUS_DPSS_TOP0 118 +-#define CLK_BUS_DPSS_TOP1 119 +-#define CLK_MIPI_DSI 120 +-#define CLK_BUS_MIPI_DSI 121 +-#define CLK_TCON_LCD 122 +-#define CLK_BUS_TCON_LCD 123 +-#define CLK_LEDC 124 +-#define CLK_BUS_LEDC 125 +-#define CLK_CSI_TOP 126 +-#define CLK_CSI0_MCLK 127 +-#define CLK_CSI1_MCLK 128 +-#define CLK_BUS_CSI 129 +-#define CLK_CSI_ISP 130 +- +-#endif /* _DT_BINDINGS_CLK_SUN50I_A100_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-a100-r-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-a100-r-ccu.h +deleted file mode 100644 +index 07312e7264fb..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-a100-r-ccu.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2020 Yangtao Li +- */ +- +-#ifndef _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_ +-#define _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_ +- +-#define CLK_R_APB1 2 +- +-#define CLK_R_APB1_TIMER 4 +-#define CLK_R_APB1_TWD 5 +-#define CLK_R_APB1_PWM 6 +-#define CLK_R_APB1_BUS_PWM 7 +-#define CLK_R_APB1_PPU 8 +-#define CLK_R_APB2_UART 9 +-#define CLK_R_APB2_I2C0 10 +-#define CLK_R_APB2_I2C1 11 +-#define CLK_R_APB1_IR 12 +-#define CLK_R_APB1_BUS_IR 13 +-#define CLK_R_AHB_BUS_RTC 14 +- +-#endif /* _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-a64-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-a64-ccu.h +deleted file mode 100644 +index 318eb15c414c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-a64-ccu.h ++++ /dev/null +@@ -1,138 +0,0 @@ +-/* +- * Copyright (C) 2016 Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ +-#define _DT_BINDINGS_CLK_SUN50I_A64_H_ +- +-#define CLK_PLL_VIDEO0 7 +-#define CLK_PLL_PERIPH0 11 +- +-#define CLK_CPUX 21 +-#define CLK_BUS_MIPI_DSI 28 +-#define CLK_BUS_CE 29 +-#define CLK_BUS_DMA 30 +-#define CLK_BUS_MMC0 31 +-#define CLK_BUS_MMC1 32 +-#define CLK_BUS_MMC2 33 +-#define CLK_BUS_NAND 34 +-#define CLK_BUS_DRAM 35 +-#define CLK_BUS_EMAC 36 +-#define CLK_BUS_TS 37 +-#define CLK_BUS_HSTIMER 38 +-#define CLK_BUS_SPI0 39 +-#define CLK_BUS_SPI1 40 +-#define CLK_BUS_OTG 41 +-#define CLK_BUS_EHCI0 42 +-#define CLK_BUS_EHCI1 43 +-#define CLK_BUS_OHCI0 44 +-#define CLK_BUS_OHCI1 45 +-#define CLK_BUS_VE 46 +-#define CLK_BUS_TCON0 47 +-#define CLK_BUS_TCON1 48 +-#define CLK_BUS_DEINTERLACE 49 +-#define CLK_BUS_CSI 50 +-#define CLK_BUS_HDMI 51 +-#define CLK_BUS_DE 52 +-#define CLK_BUS_GPU 53 +-#define CLK_BUS_MSGBOX 54 +-#define CLK_BUS_SPINLOCK 55 +-#define CLK_BUS_CODEC 56 +-#define CLK_BUS_SPDIF 57 +-#define CLK_BUS_PIO 58 +-#define CLK_BUS_THS 59 +-#define CLK_BUS_I2S0 60 +-#define CLK_BUS_I2S1 61 +-#define CLK_BUS_I2S2 62 +-#define CLK_BUS_I2C0 63 +-#define CLK_BUS_I2C1 64 +-#define CLK_BUS_I2C2 65 +-#define CLK_BUS_SCR 66 +-#define CLK_BUS_UART0 67 +-#define CLK_BUS_UART1 68 +-#define CLK_BUS_UART2 69 +-#define CLK_BUS_UART3 70 +-#define CLK_BUS_UART4 71 +-#define CLK_BUS_DBG 72 +-#define CLK_THS 73 +-#define CLK_NAND 74 +-#define CLK_MMC0 75 +-#define CLK_MMC1 76 +-#define CLK_MMC2 77 +-#define CLK_TS 78 +-#define CLK_CE 79 +-#define CLK_SPI0 80 +-#define CLK_SPI1 81 +-#define CLK_I2S0 82 +-#define CLK_I2S1 83 +-#define CLK_I2S2 84 +-#define CLK_SPDIF 85 +-#define CLK_USB_PHY0 86 +-#define CLK_USB_PHY1 87 +-#define CLK_USB_HSIC 88 +-#define CLK_USB_HSIC_12M 89 +- +-#define CLK_USB_OHCI0 91 +- +-#define CLK_USB_OHCI1 93 +- +-#define CLK_DRAM_VE 95 +-#define CLK_DRAM_CSI 96 +-#define CLK_DRAM_DEINTERLACE 97 +-#define CLK_DRAM_TS 98 +-#define CLK_DE 99 +-#define CLK_TCON0 100 +-#define CLK_TCON1 101 +-#define CLK_DEINTERLACE 102 +-#define CLK_CSI_MISC 103 +-#define CLK_CSI_SCLK 104 +-#define CLK_CSI_MCLK 105 +-#define CLK_VE 106 +-#define CLK_AC_DIG 107 +-#define CLK_AC_DIG_4X 108 +-#define CLK_AVS 109 +-#define CLK_HDMI 110 +-#define CLK_HDMI_DDC 111 +-#define CLK_MBUS 112 +-#define CLK_DSI_DPHY 113 +-#define CLK_GPU 114 +- +-#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-h6-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-h6-ccu.h +deleted file mode 100644 +index a1545cd60e75..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-h6-ccu.h ++++ /dev/null +@@ -1,125 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ or MIT) +-/* +- * Copyright (C) 2017 Icenowy Zheng +- */ +- +-#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_ +-#define _DT_BINDINGS_CLK_SUN50I_H6_H_ +- +-#define CLK_PLL_PERIPH0 3 +- +-#define CLK_CPUX 21 +- +-#define CLK_APB1 26 +- +-#define CLK_DE 29 +-#define CLK_BUS_DE 30 +-#define CLK_DEINTERLACE 31 +-#define CLK_BUS_DEINTERLACE 32 +-#define CLK_GPU 33 +-#define CLK_BUS_GPU 34 +-#define CLK_CE 35 +-#define CLK_BUS_CE 36 +-#define CLK_VE 37 +-#define CLK_BUS_VE 38 +-#define CLK_EMCE 39 +-#define CLK_BUS_EMCE 40 +-#define CLK_VP9 41 +-#define CLK_BUS_VP9 42 +-#define CLK_BUS_DMA 43 +-#define CLK_BUS_MSGBOX 44 +-#define CLK_BUS_SPINLOCK 45 +-#define CLK_BUS_HSTIMER 46 +-#define CLK_AVS 47 +-#define CLK_BUS_DBG 48 +-#define CLK_BUS_PSI 49 +-#define CLK_BUS_PWM 50 +-#define CLK_BUS_IOMMU 51 +- +-#define CLK_MBUS_DMA 53 +-#define CLK_MBUS_VE 54 +-#define CLK_MBUS_CE 55 +-#define CLK_MBUS_TS 56 +-#define CLK_MBUS_NAND 57 +-#define CLK_MBUS_CSI 58 +-#define CLK_MBUS_DEINTERLACE 59 +- +-#define CLK_NAND0 61 +-#define CLK_NAND1 62 +-#define CLK_BUS_NAND 63 +-#define CLK_MMC0 64 +-#define CLK_MMC1 65 +-#define CLK_MMC2 66 +-#define CLK_BUS_MMC0 67 +-#define CLK_BUS_MMC1 68 +-#define CLK_BUS_MMC2 69 +-#define CLK_BUS_UART0 70 +-#define CLK_BUS_UART1 71 +-#define CLK_BUS_UART2 72 +-#define CLK_BUS_UART3 73 +-#define CLK_BUS_I2C0 74 +-#define CLK_BUS_I2C1 75 +-#define CLK_BUS_I2C2 76 +-#define CLK_BUS_I2C3 77 +-#define CLK_BUS_SCR0 78 +-#define CLK_BUS_SCR1 79 +-#define CLK_SPI0 80 +-#define CLK_SPI1 81 +-#define CLK_BUS_SPI0 82 +-#define CLK_BUS_SPI1 83 +-#define CLK_BUS_EMAC 84 +-#define CLK_TS 85 +-#define CLK_BUS_TS 86 +-#define CLK_IR_TX 87 +-#define CLK_BUS_IR_TX 88 +-#define CLK_BUS_THS 89 +-#define CLK_I2S3 90 +-#define CLK_I2S0 91 +-#define CLK_I2S1 92 +-#define CLK_I2S2 93 +-#define CLK_BUS_I2S0 94 +-#define CLK_BUS_I2S1 95 +-#define CLK_BUS_I2S2 96 +-#define CLK_BUS_I2S3 97 +-#define CLK_SPDIF 98 +-#define CLK_BUS_SPDIF 99 +-#define CLK_DMIC 100 +-#define CLK_BUS_DMIC 101 +-#define CLK_AUDIO_HUB 102 +-#define CLK_BUS_AUDIO_HUB 103 +-#define CLK_USB_OHCI0 104 +-#define CLK_USB_PHY0 105 +-#define CLK_USB_PHY1 106 +-#define CLK_USB_OHCI3 107 +-#define CLK_USB_PHY3 108 +-#define CLK_USB_HSIC_12M 109 +-#define CLK_USB_HSIC 110 +-#define CLK_BUS_OHCI0 111 +-#define CLK_BUS_OHCI3 112 +-#define CLK_BUS_EHCI0 113 +-#define CLK_BUS_XHCI 114 +-#define CLK_BUS_EHCI3 115 +-#define CLK_BUS_OTG 116 +-#define CLK_PCIE_REF_100M 117 +-#define CLK_PCIE_REF 118 +-#define CLK_PCIE_REF_OUT 119 +-#define CLK_PCIE_MAXI 120 +-#define CLK_PCIE_AUX 121 +-#define CLK_BUS_PCIE 122 +-#define CLK_HDMI 123 +-#define CLK_HDMI_SLOW 124 +-#define CLK_HDMI_CEC 125 +-#define CLK_BUS_HDMI 126 +-#define CLK_BUS_TCON_TOP 127 +-#define CLK_TCON_LCD0 128 +-#define CLK_BUS_TCON_LCD0 129 +-#define CLK_TCON_TV0 130 +-#define CLK_BUS_TCON_TV0 131 +-#define CLK_CSI_CCI 132 +-#define CLK_CSI_TOP 133 +-#define CLK_CSI_MCLK 134 +-#define CLK_BUS_CSI 135 +-#define CLK_HDCP 136 +-#define CLK_BUS_HDCP 137 +- +-#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-h6-r-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-h6-r-ccu.h +deleted file mode 100644 +index 890368d252c4..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-h6-r-ccu.h ++++ /dev/null +@@ -1,26 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2017 Icenowy Zheng +- */ +- +-#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ +-#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ +- +-#define CLK_AR100 0 +- +-#define CLK_R_APB1 2 +- +-#define CLK_R_APB1_TIMER 4 +-#define CLK_R_APB1_TWD 5 +-#define CLK_R_APB1_PWM 6 +-#define CLK_R_APB2_UART 7 +-#define CLK_R_APB2_I2C 8 +-#define CLK_R_APB1_IR 9 +-#define CLK_R_APB1_W1 10 +- +-#define CLK_IR 11 +-#define CLK_W1 12 +- +-#define CLK_R_APB2_RSB 13 +- +-#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-h616-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-h616-ccu.h +deleted file mode 100644 +index 4fc08b0df2f3..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-h616-ccu.h ++++ /dev/null +@@ -1,115 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +-/* +- * Copyright (C) 2020 Arm Ltd. +- */ +- +-#ifndef _DT_BINDINGS_CLK_SUN50I_H616_H_ +-#define _DT_BINDINGS_CLK_SUN50I_H616_H_ +- +-#define CLK_PLL_PERIPH0 4 +- +-#define CLK_CPUX 21 +- +-#define CLK_APB1 26 +- +-#define CLK_DE 29 +-#define CLK_BUS_DE 30 +-#define CLK_DEINTERLACE 31 +-#define CLK_BUS_DEINTERLACE 32 +-#define CLK_G2D 33 +-#define CLK_BUS_G2D 34 +-#define CLK_GPU0 35 +-#define CLK_BUS_GPU 36 +-#define CLK_GPU1 37 +-#define CLK_CE 38 +-#define CLK_BUS_CE 39 +-#define CLK_VE 40 +-#define CLK_BUS_VE 41 +-#define CLK_BUS_DMA 42 +-#define CLK_BUS_HSTIMER 43 +-#define CLK_AVS 44 +-#define CLK_BUS_DBG 45 +-#define CLK_BUS_PSI 46 +-#define CLK_BUS_PWM 47 +-#define CLK_BUS_IOMMU 48 +- +-#define CLK_MBUS_DMA 50 +-#define CLK_MBUS_VE 51 +-#define CLK_MBUS_CE 52 +-#define CLK_MBUS_TS 53 +-#define CLK_MBUS_NAND 54 +-#define CLK_MBUS_G2D 55 +- +-#define CLK_NAND0 57 +-#define CLK_NAND1 58 +-#define CLK_BUS_NAND 59 +-#define CLK_MMC0 60 +-#define CLK_MMC1 61 +-#define CLK_MMC2 62 +-#define CLK_BUS_MMC0 63 +-#define CLK_BUS_MMC1 64 +-#define CLK_BUS_MMC2 65 +-#define CLK_BUS_UART0 66 +-#define CLK_BUS_UART1 67 +-#define CLK_BUS_UART2 68 +-#define CLK_BUS_UART3 69 +-#define CLK_BUS_UART4 70 +-#define CLK_BUS_UART5 71 +-#define CLK_BUS_I2C0 72 +-#define CLK_BUS_I2C1 73 +-#define CLK_BUS_I2C2 74 +-#define CLK_BUS_I2C3 75 +-#define CLK_BUS_I2C4 76 +-#define CLK_SPI0 77 +-#define CLK_SPI1 78 +-#define CLK_BUS_SPI0 79 +-#define CLK_BUS_SPI1 80 +-#define CLK_EMAC_25M 81 +-#define CLK_BUS_EMAC0 82 +-#define CLK_BUS_EMAC1 83 +-#define CLK_TS 84 +-#define CLK_BUS_TS 85 +-#define CLK_BUS_THS 86 +-#define CLK_SPDIF 87 +-#define CLK_BUS_SPDIF 88 +-#define CLK_DMIC 89 +-#define CLK_BUS_DMIC 90 +-#define CLK_AUDIO_CODEC_1X 91 +-#define CLK_AUDIO_CODEC_4X 92 +-#define CLK_BUS_AUDIO_CODEC 93 +-#define CLK_AUDIO_HUB 94 +-#define CLK_BUS_AUDIO_HUB 95 +-#define CLK_USB_OHCI0 96 +-#define CLK_USB_PHY0 97 +-#define CLK_USB_OHCI1 98 +-#define CLK_USB_PHY1 99 +-#define CLK_USB_OHCI2 100 +-#define CLK_USB_PHY2 101 +-#define CLK_USB_OHCI3 102 +-#define CLK_USB_PHY3 103 +-#define CLK_BUS_OHCI0 104 +-#define CLK_BUS_OHCI1 105 +-#define CLK_BUS_OHCI2 106 +-#define CLK_BUS_OHCI3 107 +-#define CLK_BUS_EHCI0 108 +-#define CLK_BUS_EHCI1 109 +-#define CLK_BUS_EHCI2 110 +-#define CLK_BUS_EHCI3 111 +-#define CLK_BUS_OTG 112 +-#define CLK_BUS_KEYADC 113 +-#define CLK_HDMI 114 +-#define CLK_HDMI_SLOW 115 +-#define CLK_HDMI_CEC 116 +-#define CLK_BUS_HDMI 117 +-#define CLK_BUS_TCON_TOP 118 +-#define CLK_TCON_TV0 119 +-#define CLK_TCON_TV1 120 +-#define CLK_BUS_TCON_TV0 121 +-#define CLK_BUS_TCON_TV1 122 +-#define CLK_TVE0 123 +-#define CLK_BUS_TVE_TOP 124 +-#define CLK_BUS_TVE0 125 +-#define CLK_HDCP 126 +-#define CLK_BUS_HDCP 127 +- +-#endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun5i-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun5i-ccu.h +deleted file mode 100644 +index 75fe5619c3d9..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun5i-ccu.h ++++ /dev/null +@@ -1,97 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright 2016 Maxime Ripard +- * +- * Maxime Ripard +- */ +- +-#ifndef _DT_BINDINGS_CLK_SUN5I_H_ +-#define _DT_BINDINGS_CLK_SUN5I_H_ +- +-#define CLK_HOSC 1 +- +-#define CLK_PLL_VIDEO0_2X 9 +- +-#define CLK_PLL_VIDEO1_2X 16 +-#define CLK_CPU 17 +- +-#define CLK_AHB_OTG 23 +-#define CLK_AHB_EHCI 24 +-#define CLK_AHB_OHCI 25 +-#define CLK_AHB_SS 26 +-#define CLK_AHB_DMA 27 +-#define CLK_AHB_BIST 28 +-#define CLK_AHB_MMC0 29 +-#define CLK_AHB_MMC1 30 +-#define CLK_AHB_MMC2 31 +-#define CLK_AHB_NAND 32 +-#define CLK_AHB_SDRAM 33 +-#define CLK_AHB_EMAC 34 +-#define CLK_AHB_TS 35 +-#define CLK_AHB_SPI0 36 +-#define CLK_AHB_SPI1 37 +-#define CLK_AHB_SPI2 38 +-#define CLK_AHB_GPS 39 +-#define CLK_AHB_HSTIMER 40 +-#define CLK_AHB_VE 41 +-#define CLK_AHB_TVE 42 +-#define CLK_AHB_LCD 43 +-#define CLK_AHB_CSI 44 +-#define CLK_AHB_HDMI 45 +-#define CLK_AHB_DE_BE 46 +-#define CLK_AHB_DE_FE 47 +-#define CLK_AHB_IEP 48 +-#define CLK_AHB_GPU 49 +-#define CLK_APB0_CODEC 50 +-#define CLK_APB0_SPDIF 51 +-#define CLK_APB0_I2S 52 +-#define CLK_APB0_PIO 53 +-#define CLK_APB0_IR 54 +-#define CLK_APB0_KEYPAD 55 +-#define CLK_APB1_I2C0 56 +-#define CLK_APB1_I2C1 57 +-#define CLK_APB1_I2C2 58 +-#define CLK_APB1_UART0 59 +-#define CLK_APB1_UART1 60 +-#define CLK_APB1_UART2 61 +-#define CLK_APB1_UART3 62 +-#define CLK_NAND 63 +-#define CLK_MMC0 64 +-#define CLK_MMC1 65 +-#define CLK_MMC2 66 +-#define CLK_TS 67 +-#define CLK_SS 68 +-#define CLK_SPI0 69 +-#define CLK_SPI1 70 +-#define CLK_SPI2 71 +-#define CLK_IR 72 +-#define CLK_I2S 73 +-#define CLK_SPDIF 74 +-#define CLK_KEYPAD 75 +-#define CLK_USB_OHCI 76 +-#define CLK_USB_PHY0 77 +-#define CLK_USB_PHY1 78 +-#define CLK_GPS 79 +-#define CLK_DRAM_VE 80 +-#define CLK_DRAM_CSI 81 +-#define CLK_DRAM_TS 82 +-#define CLK_DRAM_TVE 83 +-#define CLK_DRAM_DE_FE 84 +-#define CLK_DRAM_DE_BE 85 +-#define CLK_DRAM_ACE 86 +-#define CLK_DRAM_IEP 87 +-#define CLK_DE_BE 88 +-#define CLK_DE_FE 89 +-#define CLK_TCON_CH0 90 +- +-#define CLK_TCON_CH1 92 +-#define CLK_CSI 93 +-#define CLK_VE 94 +-#define CLK_CODEC 95 +-#define CLK_AVS 96 +-#define CLK_HDMI 97 +-#define CLK_GPU 98 +-#define CLK_MBUS 99 +-#define CLK_IEP 100 +- +-#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun6i-a31-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun6i-a31-ccu.h +deleted file mode 100644 +index 39878d9dce9f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun6i-a31-ccu.h ++++ /dev/null +@@ -1,193 +0,0 @@ +-/* +- * Copyright (C) 2016 Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_ +-#define _DT_BINDINGS_CLK_SUN6I_A31_H_ +- +-#define CLK_PLL_VIDEO0_2X 7 +- +-#define CLK_PLL_PERIPH 10 +- +-#define CLK_PLL_VIDEO1_2X 13 +- +-#define CLK_PLL_MIPI 15 +- +-#define CLK_CPU 18 +- +-#define CLK_AHB1_MIPIDSI 23 +-#define CLK_AHB1_SS 24 +-#define CLK_AHB1_DMA 25 +-#define CLK_AHB1_MMC0 26 +-#define CLK_AHB1_MMC1 27 +-#define CLK_AHB1_MMC2 28 +-#define CLK_AHB1_MMC3 29 +-#define CLK_AHB1_NAND1 30 +-#define CLK_AHB1_NAND0 31 +-#define CLK_AHB1_SDRAM 32 +-#define CLK_AHB1_EMAC 33 +-#define CLK_AHB1_TS 34 +-#define CLK_AHB1_HSTIMER 35 +-#define CLK_AHB1_SPI0 36 +-#define CLK_AHB1_SPI1 37 +-#define CLK_AHB1_SPI2 38 +-#define CLK_AHB1_SPI3 39 +-#define CLK_AHB1_OTG 40 +-#define CLK_AHB1_EHCI0 41 +-#define CLK_AHB1_EHCI1 42 +-#define CLK_AHB1_OHCI0 43 +-#define CLK_AHB1_OHCI1 44 +-#define CLK_AHB1_OHCI2 45 +-#define CLK_AHB1_VE 46 +-#define CLK_AHB1_LCD0 47 +-#define CLK_AHB1_LCD1 48 +-#define CLK_AHB1_CSI 49 +-#define CLK_AHB1_HDMI 50 +-#define CLK_AHB1_BE0 51 +-#define CLK_AHB1_BE1 52 +-#define CLK_AHB1_FE0 53 +-#define CLK_AHB1_FE1 54 +-#define CLK_AHB1_MP 55 +-#define CLK_AHB1_GPU 56 +-#define CLK_AHB1_DEU0 57 +-#define CLK_AHB1_DEU1 58 +-#define CLK_AHB1_DRC0 59 +-#define CLK_AHB1_DRC1 60 +- +-#define CLK_APB1_CODEC 61 +-#define CLK_APB1_SPDIF 62 +-#define CLK_APB1_DIGITAL_MIC 63 +-#define CLK_APB1_PIO 64 +-#define CLK_APB1_DAUDIO0 65 +-#define CLK_APB1_DAUDIO1 66 +- +-#define CLK_APB2_I2C0 67 +-#define CLK_APB2_I2C1 68 +-#define CLK_APB2_I2C2 69 +-#define CLK_APB2_I2C3 70 +-#define CLK_APB2_UART0 71 +-#define CLK_APB2_UART1 72 +-#define CLK_APB2_UART2 73 +-#define CLK_APB2_UART3 74 +-#define CLK_APB2_UART4 75 +-#define CLK_APB2_UART5 76 +- +-#define CLK_NAND0 77 +-#define CLK_NAND1 78 +-#define CLK_MMC0 79 +-#define CLK_MMC0_SAMPLE 80 +-#define CLK_MMC0_OUTPUT 81 +-#define CLK_MMC1 82 +-#define CLK_MMC1_SAMPLE 83 +-#define CLK_MMC1_OUTPUT 84 +-#define CLK_MMC2 85 +-#define CLK_MMC2_SAMPLE 86 +-#define CLK_MMC2_OUTPUT 87 +-#define CLK_MMC3 88 +-#define CLK_MMC3_SAMPLE 89 +-#define CLK_MMC3_OUTPUT 90 +-#define CLK_TS 91 +-#define CLK_SS 92 +-#define CLK_SPI0 93 +-#define CLK_SPI1 94 +-#define CLK_SPI2 95 +-#define CLK_SPI3 96 +-#define CLK_DAUDIO0 97 +-#define CLK_DAUDIO1 98 +-#define CLK_SPDIF 99 +-#define CLK_USB_PHY0 100 +-#define CLK_USB_PHY1 101 +-#define CLK_USB_PHY2 102 +-#define CLK_USB_OHCI0 103 +-#define CLK_USB_OHCI1 104 +-#define CLK_USB_OHCI2 105 +- +-#define CLK_DRAM_VE 110 +-#define CLK_DRAM_CSI_ISP 111 +-#define CLK_DRAM_TS 112 +-#define CLK_DRAM_DRC0 113 +-#define CLK_DRAM_DRC1 114 +-#define CLK_DRAM_DEU0 115 +-#define CLK_DRAM_DEU1 116 +-#define CLK_DRAM_FE0 117 +-#define CLK_DRAM_FE1 118 +-#define CLK_DRAM_BE0 119 +-#define CLK_DRAM_BE1 120 +-#define CLK_DRAM_MP 121 +- +-#define CLK_BE0 122 +-#define CLK_BE1 123 +-#define CLK_FE0 124 +-#define CLK_FE1 125 +-#define CLK_MP 126 +-#define CLK_LCD0_CH0 127 +-#define CLK_LCD1_CH0 128 +-#define CLK_LCD0_CH1 129 +-#define CLK_LCD1_CH1 130 +-#define CLK_CSI0_SCLK 131 +-#define CLK_CSI0_MCLK 132 +-#define CLK_CSI1_MCLK 133 +-#define CLK_VE 134 +-#define CLK_CODEC 135 +-#define CLK_AVS 136 +-#define CLK_DIGITAL_MIC 137 +-#define CLK_HDMI 138 +-#define CLK_HDMI_DDC 139 +-#define CLK_PS 140 +- +-#define CLK_MIPI_DSI 143 +-#define CLK_MIPI_DSI_DPHY 144 +-#define CLK_MIPI_CSI_DPHY 145 +-#define CLK_IEP_DRC0 146 +-#define CLK_IEP_DRC1 147 +-#define CLK_IEP_DEU0 148 +-#define CLK_IEP_DEU1 149 +-#define CLK_GPU_CORE 150 +-#define CLK_GPU_MEMORY 151 +-#define CLK_GPU_HYD 152 +-#define CLK_ATS 153 +-#define CLK_TRACE 154 +- +-#define CLK_OUT_A 155 +-#define CLK_OUT_B 156 +-#define CLK_OUT_C 157 +- +-#endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun7i-a20-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun7i-a20-ccu.h +deleted file mode 100644 +index 045a5178da0c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun7i-a20-ccu.h ++++ /dev/null +@@ -1,53 +0,0 @@ +-/* +- * Copyright (C) 2017 Priit Laes +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_CLK_SUN7I_A20_H_ +-#define _DT_BINDINGS_CLK_SUN7I_A20_H_ +- +-#include +- +-#define CLK_MBUS 166 +-#define CLK_HDMI1_SLOW 167 +-#define CLK_HDMI1 168 +-#define CLK_OUT_A 169 +-#define CLK_OUT_B 170 +- +-#endif /* _DT_BINDINGS_CLK_SUN7I_A20_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-a23-a33-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-a23-a33-ccu.h +deleted file mode 100644 +index eb524d0bbd01..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-a23-a33-ccu.h ++++ /dev/null +@@ -1,129 +0,0 @@ +-/* +- * Copyright (C) 2016 Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ +-#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ +- +-#define CLK_PLL_MIPI 13 +- +-#define CLK_CPUX 18 +- +-#define CLK_BUS_MIPI_DSI 23 +-#define CLK_BUS_SS 24 +-#define CLK_BUS_DMA 25 +-#define CLK_BUS_MMC0 26 +-#define CLK_BUS_MMC1 27 +-#define CLK_BUS_MMC2 28 +-#define CLK_BUS_NAND 29 +-#define CLK_BUS_DRAM 30 +-#define CLK_BUS_HSTIMER 31 +-#define CLK_BUS_SPI0 32 +-#define CLK_BUS_SPI1 33 +-#define CLK_BUS_OTG 34 +-#define CLK_BUS_EHCI 35 +-#define CLK_BUS_OHCI 36 +-#define CLK_BUS_VE 37 +-#define CLK_BUS_LCD 38 +-#define CLK_BUS_CSI 39 +-#define CLK_BUS_DE_BE 40 +-#define CLK_BUS_DE_FE 41 +-#define CLK_BUS_GPU 42 +-#define CLK_BUS_MSGBOX 43 +-#define CLK_BUS_SPINLOCK 44 +-#define CLK_BUS_DRC 45 +-#define CLK_BUS_SAT 46 +-#define CLK_BUS_CODEC 47 +-#define CLK_BUS_PIO 48 +-#define CLK_BUS_I2S0 49 +-#define CLK_BUS_I2S1 50 +-#define CLK_BUS_I2C0 51 +-#define CLK_BUS_I2C1 52 +-#define CLK_BUS_I2C2 53 +-#define CLK_BUS_UART0 54 +-#define CLK_BUS_UART1 55 +-#define CLK_BUS_UART2 56 +-#define CLK_BUS_UART3 57 +-#define CLK_BUS_UART4 58 +-#define CLK_NAND 59 +-#define CLK_MMC0 60 +-#define CLK_MMC0_SAMPLE 61 +-#define CLK_MMC0_OUTPUT 62 +-#define CLK_MMC1 63 +-#define CLK_MMC1_SAMPLE 64 +-#define CLK_MMC1_OUTPUT 65 +-#define CLK_MMC2 66 +-#define CLK_MMC2_SAMPLE 67 +-#define CLK_MMC2_OUTPUT 68 +-#define CLK_SS 69 +-#define CLK_SPI0 70 +-#define CLK_SPI1 71 +-#define CLK_I2S0 72 +-#define CLK_I2S1 73 +-#define CLK_USB_PHY0 74 +-#define CLK_USB_PHY1 75 +-#define CLK_USB_HSIC 76 +-#define CLK_USB_HSIC_12M 77 +-#define CLK_USB_OHCI 78 +- +-#define CLK_DRAM_VE 80 +-#define CLK_DRAM_CSI 81 +-#define CLK_DRAM_DRC 82 +-#define CLK_DRAM_DE_FE 83 +-#define CLK_DRAM_DE_BE 84 +-#define CLK_DE_BE 85 +-#define CLK_DE_FE 86 +-#define CLK_LCD_CH0 87 +-#define CLK_LCD_CH1 88 +-#define CLK_CSI_SCLK 89 +-#define CLK_CSI_MCLK 90 +-#define CLK_VE 91 +-#define CLK_AC_DIG 92 +-#define CLK_AC_DIG_4X 93 +-#define CLK_AVS 94 +- +-#define CLK_DSI_SCLK 96 +-#define CLK_DSI_DPHY 97 +-#define CLK_DRC 98 +-#define CLK_GPU 99 +-#define CLK_ATS 100 +- +-#endif /* _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-a83t-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-a83t-ccu.h +deleted file mode 100644 +index 78af5085f630..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-a83t-ccu.h ++++ /dev/null +@@ -1,140 +0,0 @@ +-/* +- * Copyright (C) 2017 Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ +-#define _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ +- +-#define CLK_PLL_PERIPH 6 +- +-#define CLK_PLL_DE 9 +- +-#define CLK_C0CPUX 11 +-#define CLK_C1CPUX 12 +- +-#define CLK_BUS_MIPI_DSI 19 +-#define CLK_BUS_SS 20 +-#define CLK_BUS_DMA 21 +-#define CLK_BUS_MMC0 22 +-#define CLK_BUS_MMC1 23 +-#define CLK_BUS_MMC2 24 +-#define CLK_BUS_NAND 25 +-#define CLK_BUS_DRAM 26 +-#define CLK_BUS_EMAC 27 +-#define CLK_BUS_HSTIMER 28 +-#define CLK_BUS_SPI0 29 +-#define CLK_BUS_SPI1 30 +-#define CLK_BUS_OTG 31 +-#define CLK_BUS_EHCI0 32 +-#define CLK_BUS_EHCI1 33 +-#define CLK_BUS_OHCI0 34 +- +-#define CLK_BUS_VE 35 +-#define CLK_BUS_TCON0 36 +-#define CLK_BUS_TCON1 37 +-#define CLK_BUS_CSI 38 +-#define CLK_BUS_HDMI 39 +-#define CLK_BUS_DE 40 +-#define CLK_BUS_GPU 41 +-#define CLK_BUS_MSGBOX 42 +-#define CLK_BUS_SPINLOCK 43 +- +-#define CLK_BUS_SPDIF 44 +-#define CLK_BUS_PIO 45 +-#define CLK_BUS_I2S0 46 +-#define CLK_BUS_I2S1 47 +-#define CLK_BUS_I2S2 48 +-#define CLK_BUS_TDM 49 +- +-#define CLK_BUS_I2C0 50 +-#define CLK_BUS_I2C1 51 +-#define CLK_BUS_I2C2 52 +-#define CLK_BUS_UART0 53 +-#define CLK_BUS_UART1 54 +-#define CLK_BUS_UART2 55 +-#define CLK_BUS_UART3 56 +-#define CLK_BUS_UART4 57 +- +-#define CLK_NAND 59 +-#define CLK_MMC0 60 +-#define CLK_MMC0_SAMPLE 61 +-#define CLK_MMC0_OUTPUT 62 +-#define CLK_MMC1 63 +-#define CLK_MMC1_SAMPLE 64 +-#define CLK_MMC1_OUTPUT 65 +-#define CLK_MMC2 66 +-#define CLK_MMC2_SAMPLE 67 +-#define CLK_MMC2_OUTPUT 68 +-#define CLK_SS 69 +-#define CLK_SPI0 70 +-#define CLK_SPI1 71 +-#define CLK_I2S0 72 +-#define CLK_I2S1 73 +-#define CLK_I2S2 74 +-#define CLK_TDM 75 +-#define CLK_SPDIF 76 +-#define CLK_USB_PHY0 77 +-#define CLK_USB_PHY1 78 +-#define CLK_USB_HSIC 79 +-#define CLK_USB_HSIC_12M 80 +-#define CLK_USB_OHCI0 81 +- +-#define CLK_DRAM_VE 83 +-#define CLK_DRAM_CSI 84 +- +-#define CLK_TCON0 85 +-#define CLK_TCON1 86 +-#define CLK_CSI_MISC 87 +-#define CLK_MIPI_CSI 88 +-#define CLK_CSI_MCLK 89 +-#define CLK_CSI_SCLK 90 +-#define CLK_VE 91 +-#define CLK_AVS 92 +-#define CLK_HDMI 93 +-#define CLK_HDMI_SLOW 94 +- +-#define CLK_MIPI_DSI0 96 +-#define CLK_MIPI_DSI1 97 +-#define CLK_GPU_CORE 98 +-#define CLK_GPU_MEMORY 99 +-#define CLK_GPU_HYD 100 +- +-#endif /* _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-de2.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-de2.h +deleted file mode 100644 +index 7768f73b051e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-de2.h ++++ /dev/null +@@ -1,21 +0,0 @@ +-/* +- * Copyright (C) 2016 Icenowy Zheng +- * +- * SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ +-#define _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ +- +-#define CLK_BUS_MIXER0 0 +-#define CLK_BUS_MIXER1 1 +-#define CLK_BUS_WB 2 +- +-#define CLK_MIXER0 6 +-#define CLK_MIXER1 7 +-#define CLK_WB 8 +- +-#define CLK_BUS_ROT 9 +-#define CLK_ROT 10 +- +-#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-h3-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-h3-ccu.h +deleted file mode 100644 +index 30d2d15373a2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-h3-ccu.h ++++ /dev/null +@@ -1,152 +0,0 @@ +-/* +- * Copyright (C) 2016 Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_ +-#define _DT_BINDINGS_CLK_SUN8I_H3_H_ +- +-#define CLK_PLL_VIDEO 6 +- +-#define CLK_PLL_PERIPH0 9 +- +-#define CLK_CPUX 14 +- +-#define CLK_BUS_CE 20 +-#define CLK_BUS_DMA 21 +-#define CLK_BUS_MMC0 22 +-#define CLK_BUS_MMC1 23 +-#define CLK_BUS_MMC2 24 +-#define CLK_BUS_NAND 25 +-#define CLK_BUS_DRAM 26 +-#define CLK_BUS_EMAC 27 +-#define CLK_BUS_TS 28 +-#define CLK_BUS_HSTIMER 29 +-#define CLK_BUS_SPI0 30 +-#define CLK_BUS_SPI1 31 +-#define CLK_BUS_OTG 32 +-#define CLK_BUS_EHCI0 33 +-#define CLK_BUS_EHCI1 34 +-#define CLK_BUS_EHCI2 35 +-#define CLK_BUS_EHCI3 36 +-#define CLK_BUS_OHCI0 37 +-#define CLK_BUS_OHCI1 38 +-#define CLK_BUS_OHCI2 39 +-#define CLK_BUS_OHCI3 40 +-#define CLK_BUS_VE 41 +-#define CLK_BUS_TCON0 42 +-#define CLK_BUS_TCON1 43 +-#define CLK_BUS_DEINTERLACE 44 +-#define CLK_BUS_CSI 45 +-#define CLK_BUS_TVE 46 +-#define CLK_BUS_HDMI 47 +-#define CLK_BUS_DE 48 +-#define CLK_BUS_GPU 49 +-#define CLK_BUS_MSGBOX 50 +-#define CLK_BUS_SPINLOCK 51 +-#define CLK_BUS_CODEC 52 +-#define CLK_BUS_SPDIF 53 +-#define CLK_BUS_PIO 54 +-#define CLK_BUS_THS 55 +-#define CLK_BUS_I2S0 56 +-#define CLK_BUS_I2S1 57 +-#define CLK_BUS_I2S2 58 +-#define CLK_BUS_I2C0 59 +-#define CLK_BUS_I2C1 60 +-#define CLK_BUS_I2C2 61 +-#define CLK_BUS_UART0 62 +-#define CLK_BUS_UART1 63 +-#define CLK_BUS_UART2 64 +-#define CLK_BUS_UART3 65 +-#define CLK_BUS_SCR0 66 +-#define CLK_BUS_EPHY 67 +-#define CLK_BUS_DBG 68 +- +-#define CLK_THS 69 +-#define CLK_NAND 70 +-#define CLK_MMC0 71 +-#define CLK_MMC0_SAMPLE 72 +-#define CLK_MMC0_OUTPUT 73 +-#define CLK_MMC1 74 +-#define CLK_MMC1_SAMPLE 75 +-#define CLK_MMC1_OUTPUT 76 +-#define CLK_MMC2 77 +-#define CLK_MMC2_SAMPLE 78 +-#define CLK_MMC2_OUTPUT 79 +-#define CLK_TS 80 +-#define CLK_CE 81 +-#define CLK_SPI0 82 +-#define CLK_SPI1 83 +-#define CLK_I2S0 84 +-#define CLK_I2S1 85 +-#define CLK_I2S2 86 +-#define CLK_SPDIF 87 +-#define CLK_USB_PHY0 88 +-#define CLK_USB_PHY1 89 +-#define CLK_USB_PHY2 90 +-#define CLK_USB_PHY3 91 +-#define CLK_USB_OHCI0 92 +-#define CLK_USB_OHCI1 93 +-#define CLK_USB_OHCI2 94 +-#define CLK_USB_OHCI3 95 +- +-#define CLK_DRAM_VE 97 +-#define CLK_DRAM_CSI 98 +-#define CLK_DRAM_DEINTERLACE 99 +-#define CLK_DRAM_TS 100 +-#define CLK_DE 101 +-#define CLK_TCON0 102 +-#define CLK_TVE 103 +-#define CLK_DEINTERLACE 104 +-#define CLK_CSI_MISC 105 +-#define CLK_CSI_SCLK 106 +-#define CLK_CSI_MCLK 107 +-#define CLK_VE 108 +-#define CLK_AC_DIG 109 +-#define CLK_AVS 110 +-#define CLK_HDMI 111 +-#define CLK_HDMI_DDC 112 +-#define CLK_MBUS 113 +-#define CLK_GPU 114 +- +-/* New clocks imported in H5 */ +-#define CLK_BUS_SCR1 115 +- +-#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-r-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-r-ccu.h +deleted file mode 100644 +index 779d20aa0d05..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-r-ccu.h ++++ /dev/null +@@ -1,59 +0,0 @@ +-/* +- * Copyright (c) 2016 Icenowy Zheng +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ +-#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ +- +-#define CLK_AR100 0 +- +-#define CLK_APB0_PIO 3 +-#define CLK_APB0_IR 4 +-#define CLK_APB0_TIMER 5 +-#define CLK_APB0_RSB 6 +-#define CLK_APB0_UART 7 +-/* 8 is reserved for CLK_APB0_W1 on A31 */ +-#define CLK_APB0_I2C 9 +-#define CLK_APB0_TWD 10 +- +-#define CLK_IR 11 +- +-#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-r40-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-r40-ccu.h +deleted file mode 100644 +index d7337b55a4ef..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-r40-ccu.h ++++ /dev/null +@@ -1,191 +0,0 @@ +-/* +- * Copyright (C) 2017 Icenowy Zheng +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_ +-#define _DT_BINDINGS_CLK_SUN8I_R40_H_ +- +-#define CLK_PLL_VIDEO0 7 +- +-#define CLK_PLL_VIDEO1 16 +- +-#define CLK_CPU 24 +- +-#define CLK_BUS_MIPI_DSI 29 +-#define CLK_BUS_CE 30 +-#define CLK_BUS_DMA 31 +-#define CLK_BUS_MMC0 32 +-#define CLK_BUS_MMC1 33 +-#define CLK_BUS_MMC2 34 +-#define CLK_BUS_MMC3 35 +-#define CLK_BUS_NAND 36 +-#define CLK_BUS_DRAM 37 +-#define CLK_BUS_EMAC 38 +-#define CLK_BUS_TS 39 +-#define CLK_BUS_HSTIMER 40 +-#define CLK_BUS_SPI0 41 +-#define CLK_BUS_SPI1 42 +-#define CLK_BUS_SPI2 43 +-#define CLK_BUS_SPI3 44 +-#define CLK_BUS_SATA 45 +-#define CLK_BUS_OTG 46 +-#define CLK_BUS_EHCI0 47 +-#define CLK_BUS_EHCI1 48 +-#define CLK_BUS_EHCI2 49 +-#define CLK_BUS_OHCI0 50 +-#define CLK_BUS_OHCI1 51 +-#define CLK_BUS_OHCI2 52 +-#define CLK_BUS_VE 53 +-#define CLK_BUS_MP 54 +-#define CLK_BUS_DEINTERLACE 55 +-#define CLK_BUS_CSI0 56 +-#define CLK_BUS_CSI1 57 +-#define CLK_BUS_HDMI1 58 +-#define CLK_BUS_HDMI0 59 +-#define CLK_BUS_DE 60 +-#define CLK_BUS_TVE0 61 +-#define CLK_BUS_TVE1 62 +-#define CLK_BUS_TVE_TOP 63 +-#define CLK_BUS_GMAC 64 +-#define CLK_BUS_GPU 65 +-#define CLK_BUS_TVD0 66 +-#define CLK_BUS_TVD1 67 +-#define CLK_BUS_TVD2 68 +-#define CLK_BUS_TVD3 69 +-#define CLK_BUS_TVD_TOP 70 +-#define CLK_BUS_TCON_LCD0 71 +-#define CLK_BUS_TCON_LCD1 72 +-#define CLK_BUS_TCON_TV0 73 +-#define CLK_BUS_TCON_TV1 74 +-#define CLK_BUS_TCON_TOP 75 +-#define CLK_BUS_CODEC 76 +-#define CLK_BUS_SPDIF 77 +-#define CLK_BUS_AC97 78 +-#define CLK_BUS_PIO 79 +-#define CLK_BUS_IR0 80 +-#define CLK_BUS_IR1 81 +-#define CLK_BUS_THS 82 +-#define CLK_BUS_KEYPAD 83 +-#define CLK_BUS_I2S0 84 +-#define CLK_BUS_I2S1 85 +-#define CLK_BUS_I2S2 86 +-#define CLK_BUS_I2C0 87 +-#define CLK_BUS_I2C1 88 +-#define CLK_BUS_I2C2 89 +-#define CLK_BUS_I2C3 90 +-#define CLK_BUS_CAN 91 +-#define CLK_BUS_SCR 92 +-#define CLK_BUS_PS20 93 +-#define CLK_BUS_PS21 94 +-#define CLK_BUS_I2C4 95 +-#define CLK_BUS_UART0 96 +-#define CLK_BUS_UART1 97 +-#define CLK_BUS_UART2 98 +-#define CLK_BUS_UART3 99 +-#define CLK_BUS_UART4 100 +-#define CLK_BUS_UART5 101 +-#define CLK_BUS_UART6 102 +-#define CLK_BUS_UART7 103 +-#define CLK_BUS_DBG 104 +- +-#define CLK_THS 105 +-#define CLK_NAND 106 +-#define CLK_MMC0 107 +-#define CLK_MMC1 108 +-#define CLK_MMC2 109 +-#define CLK_MMC3 110 +-#define CLK_TS 111 +-#define CLK_CE 112 +-#define CLK_SPI0 113 +-#define CLK_SPI1 114 +-#define CLK_SPI2 115 +-#define CLK_SPI3 116 +-#define CLK_I2S0 117 +-#define CLK_I2S1 118 +-#define CLK_I2S2 119 +-#define CLK_AC97 120 +-#define CLK_SPDIF 121 +-#define CLK_KEYPAD 122 +-#define CLK_SATA 123 +-#define CLK_USB_PHY0 124 +-#define CLK_USB_PHY1 125 +-#define CLK_USB_PHY2 126 +-#define CLK_USB_OHCI0 127 +-#define CLK_USB_OHCI1 128 +-#define CLK_USB_OHCI2 129 +-#define CLK_IR0 130 +-#define CLK_IR1 131 +- +-#define CLK_DRAM_VE 133 +-#define CLK_DRAM_CSI0 134 +-#define CLK_DRAM_CSI1 135 +-#define CLK_DRAM_TS 136 +-#define CLK_DRAM_TVD 137 +-#define CLK_DRAM_MP 138 +-#define CLK_DRAM_DEINTERLACE 139 +-#define CLK_DE 140 +-#define CLK_MP 141 +-#define CLK_TCON_LCD0 142 +-#define CLK_TCON_LCD1 143 +-#define CLK_TCON_TV0 144 +-#define CLK_TCON_TV1 145 +-#define CLK_DEINTERLACE 146 +-#define CLK_CSI1_MCLK 147 +-#define CLK_CSI_SCLK 148 +-#define CLK_CSI0_MCLK 149 +-#define CLK_VE 150 +-#define CLK_CODEC 151 +-#define CLK_AVS 152 +-#define CLK_HDMI 153 +-#define CLK_HDMI_SLOW 154 +-#define CLK_MBUS 155 +-#define CLK_DSI_DPHY 156 +-#define CLK_TVE0 157 +-#define CLK_TVE1 158 +-#define CLK_TVD0 159 +-#define CLK_TVD1 160 +-#define CLK_TVD2 161 +-#define CLK_TVD3 162 +-#define CLK_GPU 163 +-#define CLK_OUTA 164 +-#define CLK_OUTB 165 +- +-#endif /* _DT_BINDINGS_CLK_SUN8I_R40_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-tcon-top.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-tcon-top.h +deleted file mode 100644 +index 25164d767835..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-tcon-top.h ++++ /dev/null +@@ -1,11 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +-/* Copyright (C) 2018 Jernej Skrabec */ +- +-#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ +-#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ +- +-#define CLK_TCON_TOP_TV0 0 +-#define CLK_TCON_TOP_TV1 1 +-#define CLK_TCON_TOP_DSI 2 +- +-#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-v3s-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-v3s-ccu.h +deleted file mode 100644 +index 014ac6123d17..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun8i-v3s-ccu.h ++++ /dev/null +@@ -1,111 +0,0 @@ +-/* +- * Copyright (c) 2016 Icenowy Zheng +- * +- * Based on sun8i-h3-ccu.h, which is: +- * Copyright (C) 2016 Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_ +-#define _DT_BINDINGS_CLK_SUN8I_V3S_H_ +- +-#define CLK_CPU 14 +- +-#define CLK_BUS_CE 20 +-#define CLK_BUS_DMA 21 +-#define CLK_BUS_MMC0 22 +-#define CLK_BUS_MMC1 23 +-#define CLK_BUS_MMC2 24 +-#define CLK_BUS_DRAM 25 +-#define CLK_BUS_EMAC 26 +-#define CLK_BUS_HSTIMER 27 +-#define CLK_BUS_SPI0 28 +-#define CLK_BUS_OTG 29 +-#define CLK_BUS_EHCI0 30 +-#define CLK_BUS_OHCI0 31 +-#define CLK_BUS_VE 32 +-#define CLK_BUS_TCON0 33 +-#define CLK_BUS_CSI 34 +-#define CLK_BUS_DE 35 +-#define CLK_BUS_CODEC 36 +-#define CLK_BUS_PIO 37 +-#define CLK_BUS_I2C0 38 +-#define CLK_BUS_I2C1 39 +-#define CLK_BUS_UART0 40 +-#define CLK_BUS_UART1 41 +-#define CLK_BUS_UART2 42 +-#define CLK_BUS_EPHY 43 +-#define CLK_BUS_DBG 44 +- +-#define CLK_MMC0 45 +-#define CLK_MMC0_SAMPLE 46 +-#define CLK_MMC0_OUTPUT 47 +-#define CLK_MMC1 48 +-#define CLK_MMC1_SAMPLE 49 +-#define CLK_MMC1_OUTPUT 50 +-#define CLK_MMC2 51 +-#define CLK_MMC2_SAMPLE 52 +-#define CLK_MMC2_OUTPUT 53 +-#define CLK_CE 54 +-#define CLK_SPI0 55 +-#define CLK_USB_PHY0 56 +-#define CLK_USB_OHCI0 57 +- +-#define CLK_DRAM_VE 59 +-#define CLK_DRAM_CSI 60 +-#define CLK_DRAM_EHCI 61 +-#define CLK_DRAM_OHCI 62 +-#define CLK_DE 63 +-#define CLK_TCON0 64 +-#define CLK_CSI_MISC 65 +-#define CLK_CSI0_MCLK 66 +-#define CLK_CSI1_SCLK 67 +-#define CLK_CSI1_MCLK 68 +-#define CLK_VE 69 +-#define CLK_AC_DIG 70 +-#define CLK_AVS 71 +- +-#define CLK_MIPI_CSI 73 +- +-/* Clocks not available on V3s */ +-#define CLK_BUS_I2S0 75 +-#define CLK_I2S0 76 +- +-#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun9i-a80-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun9i-a80-ccu.h +deleted file mode 100644 +index 6ea1492a73a6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun9i-a80-ccu.h ++++ /dev/null +@@ -1,162 +0,0 @@ +-/* +- * Copyright (C) 2016 Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ +-#define _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ +- +-#define CLK_PLL_AUDIO 2 +-#define CLK_PLL_PERIPH0 3 +- +-#define CLK_C0CPUX 12 +-#define CLK_C1CPUX 13 +- +-#define CLK_OUT_A 27 +-#define CLK_OUT_B 28 +- +-#define CLK_NAND0_0 29 +-#define CLK_NAND0_1 30 +-#define CLK_NAND1_0 31 +-#define CLK_NAND1_1 32 +-#define CLK_MMC0 33 +-#define CLK_MMC0_SAMPLE 34 +-#define CLK_MMC0_OUTPUT 35 +-#define CLK_MMC1 36 +-#define CLK_MMC1_SAMPLE 37 +-#define CLK_MMC1_OUTPUT 38 +-#define CLK_MMC2 39 +-#define CLK_MMC2_SAMPLE 40 +-#define CLK_MMC2_OUTPUT 41 +-#define CLK_MMC3 42 +-#define CLK_MMC3_SAMPLE 43 +-#define CLK_MMC3_OUTPUT 44 +-#define CLK_TS 45 +-#define CLK_SS 46 +-#define CLK_SPI0 47 +-#define CLK_SPI1 48 +-#define CLK_SPI2 49 +-#define CLK_SPI3 50 +-#define CLK_I2S0 51 +-#define CLK_I2S1 52 +-#define CLK_SPDIF 53 +-#define CLK_SDRAM 54 +-#define CLK_DE 55 +-#define CLK_EDP 56 +-#define CLK_MP 57 +-#define CLK_LCD0 58 +-#define CLK_LCD1 59 +-#define CLK_MIPI_DSI0 60 +-#define CLK_MIPI_DSI1 61 +-#define CLK_HDMI 62 +-#define CLK_HDMI_SLOW 63 +-#define CLK_MIPI_CSI 64 +-#define CLK_CSI_ISP 65 +-#define CLK_CSI_MISC 66 +-#define CLK_CSI0_MCLK 67 +-#define CLK_CSI1_MCLK 68 +-#define CLK_FD 69 +-#define CLK_VE 70 +-#define CLK_AVS 71 +-#define CLK_GPU_CORE 72 +-#define CLK_GPU_MEMORY 73 +-#define CLK_GPU_AXI 74 +-#define CLK_SATA 75 +-#define CLK_AC97 76 +-#define CLK_MIPI_HSI 77 +-#define CLK_GPADC 78 +-#define CLK_CIR_TX 79 +- +-#define CLK_BUS_FD 80 +-#define CLK_BUS_VE 81 +-#define CLK_BUS_GPU_CTRL 82 +-#define CLK_BUS_SS 83 +-#define CLK_BUS_MMC 84 +-#define CLK_BUS_NAND0 85 +-#define CLK_BUS_NAND1 86 +-#define CLK_BUS_SDRAM 87 +-#define CLK_BUS_MIPI_HSI 88 +-#define CLK_BUS_SATA 89 +-#define CLK_BUS_TS 90 +-#define CLK_BUS_SPI0 91 +-#define CLK_BUS_SPI1 92 +-#define CLK_BUS_SPI2 93 +-#define CLK_BUS_SPI3 94 +- +-#define CLK_BUS_OTG 95 +-#define CLK_BUS_USB 96 +-#define CLK_BUS_GMAC 97 +-#define CLK_BUS_MSGBOX 98 +-#define CLK_BUS_SPINLOCK 99 +-#define CLK_BUS_HSTIMER 100 +-#define CLK_BUS_DMA 101 +- +-#define CLK_BUS_LCD0 102 +-#define CLK_BUS_LCD1 103 +-#define CLK_BUS_EDP 104 +-#define CLK_BUS_CSI 105 +-#define CLK_BUS_HDMI 106 +-#define CLK_BUS_DE 107 +-#define CLK_BUS_MP 108 +-#define CLK_BUS_MIPI_DSI 109 +- +-#define CLK_BUS_SPDIF 110 +-#define CLK_BUS_PIO 111 +-#define CLK_BUS_AC97 112 +-#define CLK_BUS_I2S0 113 +-#define CLK_BUS_I2S1 114 +-#define CLK_BUS_LRADC 115 +-#define CLK_BUS_GPADC 116 +-#define CLK_BUS_TWD 117 +-#define CLK_BUS_CIR_TX 118 +- +-#define CLK_BUS_I2C0 119 +-#define CLK_BUS_I2C1 120 +-#define CLK_BUS_I2C2 121 +-#define CLK_BUS_I2C3 122 +-#define CLK_BUS_I2C4 123 +-#define CLK_BUS_UART0 124 +-#define CLK_BUS_UART1 125 +-#define CLK_BUS_UART2 126 +-#define CLK_BUS_UART3 127 +-#define CLK_BUS_UART4 128 +-#define CLK_BUS_UART5 129 +- +-#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun9i-a80-de.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun9i-a80-de.h +deleted file mode 100644 +index 3dad6c3cd131..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun9i-a80-de.h ++++ /dev/null +@@ -1,80 +0,0 @@ +-/* +- * Copyright (C) 2016 Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ +-#define _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ +- +-#define CLK_FE0 0 +-#define CLK_FE1 1 +-#define CLK_FE2 2 +-#define CLK_IEP_DEU0 3 +-#define CLK_IEP_DEU1 4 +-#define CLK_BE0 5 +-#define CLK_BE1 6 +-#define CLK_BE2 7 +-#define CLK_IEP_DRC0 8 +-#define CLK_IEP_DRC1 9 +-#define CLK_MERGE 10 +- +-#define CLK_DRAM_FE0 11 +-#define CLK_DRAM_FE1 12 +-#define CLK_DRAM_FE2 13 +-#define CLK_DRAM_DEU0 14 +-#define CLK_DRAM_DEU1 15 +-#define CLK_DRAM_BE0 16 +-#define CLK_DRAM_BE1 17 +-#define CLK_DRAM_BE2 18 +-#define CLK_DRAM_DRC0 19 +-#define CLK_DRAM_DRC1 20 +- +-#define CLK_BUS_FE0 21 +-#define CLK_BUS_FE1 22 +-#define CLK_BUS_FE2 23 +-#define CLK_BUS_DEU0 24 +-#define CLK_BUS_DEU1 25 +-#define CLK_BUS_BE0 26 +-#define CLK_BUS_BE1 27 +-#define CLK_BUS_BE2 28 +-#define CLK_BUS_DRC0 29 +-#define CLK_BUS_DRC1 30 +- +-#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/sun9i-a80-usb.h b/scripts/dtc/include-prefixes/dt-bindings/clock/sun9i-a80-usb.h +deleted file mode 100644 +index 783a60d2ccea..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/sun9i-a80-usb.h ++++ /dev/null +@@ -1,59 +0,0 @@ +-/* +- * Copyright (C) 2016 Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ +-#define _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ +- +-#define CLK_BUS_HCI0 0 +-#define CLK_USB_OHCI0 1 +-#define CLK_BUS_HCI1 2 +-#define CLK_BUS_HCI2 3 +-#define CLK_USB_OHCI2 4 +- +-#define CLK_USB0_PHY 5 +-#define CLK_USB1_HSIC 6 +-#define CLK_USB1_PHY 7 +-#define CLK_USB2_HSIC 8 +-#define CLK_USB2_PHY 9 +-#define CLK_USB_HSIC 10 +- +-#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/suniv-ccu-f1c100s.h b/scripts/dtc/include-prefixes/dt-bindings/clock/suniv-ccu-f1c100s.h +deleted file mode 100644 +index f5ac155c9c70..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/suniv-ccu-f1c100s.h ++++ /dev/null +@@ -1,70 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- * +- * Copyright (c) 2018 Icenowy Zheng +- * +- */ +- +-#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ +-#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ +- +-#define CLK_CPU 11 +- +-#define CLK_BUS_DMA 14 +-#define CLK_BUS_MMC0 15 +-#define CLK_BUS_MMC1 16 +-#define CLK_BUS_DRAM 17 +-#define CLK_BUS_SPI0 18 +-#define CLK_BUS_SPI1 19 +-#define CLK_BUS_OTG 20 +-#define CLK_BUS_VE 21 +-#define CLK_BUS_LCD 22 +-#define CLK_BUS_DEINTERLACE 23 +-#define CLK_BUS_CSI 24 +-#define CLK_BUS_TVD 25 +-#define CLK_BUS_TVE 26 +-#define CLK_BUS_DE_BE 27 +-#define CLK_BUS_DE_FE 28 +-#define CLK_BUS_CODEC 29 +-#define CLK_BUS_SPDIF 30 +-#define CLK_BUS_IR 31 +-#define CLK_BUS_RSB 32 +-#define CLK_BUS_I2S0 33 +-#define CLK_BUS_I2C0 34 +-#define CLK_BUS_I2C1 35 +-#define CLK_BUS_I2C2 36 +-#define CLK_BUS_PIO 37 +-#define CLK_BUS_UART0 38 +-#define CLK_BUS_UART1 39 +-#define CLK_BUS_UART2 40 +- +-#define CLK_MMC0 41 +-#define CLK_MMC0_SAMPLE 42 +-#define CLK_MMC0_OUTPUT 43 +-#define CLK_MMC1 44 +-#define CLK_MMC1_SAMPLE 45 +-#define CLK_MMC1_OUTPUT 46 +-#define CLK_I2S 47 +-#define CLK_SPDIF 48 +- +-#define CLK_USB_PHY0 49 +- +-#define CLK_DRAM_VE 50 +-#define CLK_DRAM_CSI 51 +-#define CLK_DRAM_DEINTERLACE 52 +-#define CLK_DRAM_TVD 53 +-#define CLK_DRAM_DE_FE 54 +-#define CLK_DRAM_DE_BE 55 +- +-#define CLK_DE_BE 56 +-#define CLK_DE_FE 57 +-#define CLK_TCON 58 +-#define CLK_DEINTERLACE 59 +-#define CLK_TVE2_CLK 60 +-#define CLK_TVE1_CLK 61 +-#define CLK_TVD 62 +-#define CLK_CSI 63 +-#define CLK_VE 64 +-#define CLK_CODEC 65 +-#define CLK_AVS 66 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/tegra114-car.h b/scripts/dtc/include-prefixes/dt-bindings/clock/tegra114-car.h +deleted file mode 100644 +index a93426f008ac..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/tegra114-car.h ++++ /dev/null +@@ -1,346 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for binding nvidia,tegra114-car. +- * +- * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB +- * registers. These IDs often match those in the CAR's RST_DEVICES registers, +- * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In +- * this case, those clocks are assigned IDs above 160 in order to highlight +- * this issue. Implementations that interpret these clock IDs as bit values +- * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to +- * explicitly handle these special cases. +- * +- * The balance of the clocks controlled by the CAR are assigned IDs of 160 and +- * above. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H +-#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H +- +-/* 0 */ +-/* 1 */ +-/* 2 */ +-/* 3 */ +-#define TEGRA114_CLK_RTC 4 +-#define TEGRA114_CLK_TIMER 5 +-#define TEGRA114_CLK_UARTA 6 +-/* 7 (register bit affects uartb and vfir) */ +-/* 8 */ +-#define TEGRA114_CLK_SDMMC2 9 +-/* 10 (register bit affects spdif_in and spdif_out) */ +-#define TEGRA114_CLK_I2S1 11 +-#define TEGRA114_CLK_I2C1 12 +-#define TEGRA114_CLK_NDFLASH 13 +-#define TEGRA114_CLK_SDMMC1 14 +-#define TEGRA114_CLK_SDMMC4 15 +-/* 16 */ +-#define TEGRA114_CLK_PWM 17 +-#define TEGRA114_CLK_I2S2 18 +-#define TEGRA114_CLK_EPP 19 +-/* 20 (register bit affects vi and vi_sensor) */ +-#define TEGRA114_CLK_GR2D 21 +-#define TEGRA114_CLK_USBD 22 +-#define TEGRA114_CLK_ISP 23 +-#define TEGRA114_CLK_GR3D 24 +-/* 25 */ +-#define TEGRA114_CLK_DISP2 26 +-#define TEGRA114_CLK_DISP1 27 +-#define TEGRA114_CLK_HOST1X 28 +-#define TEGRA114_CLK_VCP 29 +-#define TEGRA114_CLK_I2S0 30 +-/* 31 */ +- +-#define TEGRA114_CLK_MC 32 +-/* 33 */ +-#define TEGRA114_CLK_APBDMA 34 +-/* 35 */ +-#define TEGRA114_CLK_KBC 36 +-/* 37 */ +-/* 38 */ +-/* 39 (register bit affects fuse and fuse_burn) */ +-#define TEGRA114_CLK_KFUSE 40 +-#define TEGRA114_CLK_SBC1 41 +-#define TEGRA114_CLK_NOR 42 +-/* 43 */ +-#define TEGRA114_CLK_SBC2 44 +-/* 45 */ +-#define TEGRA114_CLK_SBC3 46 +-#define TEGRA114_CLK_I2C5 47 +-#define TEGRA114_CLK_DSIA 48 +-/* 49 */ +-#define TEGRA114_CLK_MIPI 50 +-#define TEGRA114_CLK_HDMI 51 +-#define TEGRA114_CLK_CSI 52 +-/* 53 */ +-#define TEGRA114_CLK_I2C2 54 +-#define TEGRA114_CLK_UARTC 55 +-#define TEGRA114_CLK_MIPI_CAL 56 +-#define TEGRA114_CLK_EMC 57 +-#define TEGRA114_CLK_USB2 58 +-#define TEGRA114_CLK_USB3 59 +-/* 60 */ +-#define TEGRA114_CLK_VDE 61 +-#define TEGRA114_CLK_BSEA 62 +-#define TEGRA114_CLK_BSEV 63 +- +-/* 64 */ +-#define TEGRA114_CLK_UARTD 65 +-/* 66 */ +-#define TEGRA114_CLK_I2C3 67 +-#define TEGRA114_CLK_SBC4 68 +-#define TEGRA114_CLK_SDMMC3 69 +-/* 70 */ +-#define TEGRA114_CLK_OWR 71 +-/* 72 */ +-#define TEGRA114_CLK_CSITE 73 +-/* 74 */ +-/* 75 */ +-#define TEGRA114_CLK_LA 76 +-#define TEGRA114_CLK_TRACE 77 +-#define TEGRA114_CLK_SOC_THERM 78 +-#define TEGRA114_CLK_DTV 79 +-#define TEGRA114_CLK_NDSPEED 80 +-#define TEGRA114_CLK_I2CSLOW 81 +-#define TEGRA114_CLK_DSIB 82 +-#define TEGRA114_CLK_TSEC 83 +-/* 84 */ +-/* 85 */ +-/* 86 */ +-/* 87 */ +-/* 88 */ +-#define TEGRA114_CLK_XUSB_HOST 89 +-/* 90 */ +-#define TEGRA114_CLK_MSENC 91 +-#define TEGRA114_CLK_CSUS 92 +-/* 93 */ +-/* 94 */ +-/* 95 (bit affects xusb_dev and xusb_dev_src) */ +- +-/* 96 */ +-/* 97 */ +-/* 98 */ +-#define TEGRA114_CLK_MSELECT 99 +-#define TEGRA114_CLK_TSENSOR 100 +-#define TEGRA114_CLK_I2S3 101 +-#define TEGRA114_CLK_I2S4 102 +-#define TEGRA114_CLK_I2C4 103 +-#define TEGRA114_CLK_SBC5 104 +-#define TEGRA114_CLK_SBC6 105 +-#define TEGRA114_CLK_D_AUDIO 106 +-#define TEGRA114_CLK_APBIF 107 +-#define TEGRA114_CLK_DAM0 108 +-#define TEGRA114_CLK_DAM1 109 +-#define TEGRA114_CLK_DAM2 110 +-#define TEGRA114_CLK_HDA2CODEC_2X 111 +-/* 112 */ +-#define TEGRA114_CLK_AUDIO0_2X 113 +-#define TEGRA114_CLK_AUDIO1_2X 114 +-#define TEGRA114_CLK_AUDIO2_2X 115 +-#define TEGRA114_CLK_AUDIO3_2X 116 +-#define TEGRA114_CLK_AUDIO4_2X 117 +-#define TEGRA114_CLK_SPDIF_2X 118 +-#define TEGRA114_CLK_ACTMON 119 +-#define TEGRA114_CLK_EXTERN1 120 +-#define TEGRA114_CLK_EXTERN2 121 +-#define TEGRA114_CLK_EXTERN3 122 +-/* 123 */ +-/* 124 */ +-#define TEGRA114_CLK_HDA 125 +-/* 126 */ +-#define TEGRA114_CLK_SE 127 +- +-#define TEGRA114_CLK_HDA2HDMI 128 +-/* 129 */ +-/* 130 */ +-/* 131 */ +-/* 132 */ +-/* 133 */ +-/* 134 */ +-/* 135 */ +-#define TEGRA114_CLK_CEC 136 +-/* 137 */ +-/* 138 */ +-/* 139 */ +-/* 140 */ +-/* 141 */ +-/* 142 */ +-/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ +-/* xusb_host_src and xusb_ss_src) */ +-#define TEGRA114_CLK_CILAB 144 +-#define TEGRA114_CLK_CILCD 145 +-#define TEGRA114_CLK_CILE 146 +-#define TEGRA114_CLK_DSIALP 147 +-#define TEGRA114_CLK_DSIBLP 148 +-/* 149 */ +-#define TEGRA114_CLK_DDS 150 +-/* 151 */ +-#define TEGRA114_CLK_DP2 152 +-#define TEGRA114_CLK_AMX 153 +-#define TEGRA114_CLK_ADX 154 +-/* 155 (bit affects dfll_ref and dfll_soc) */ +-#define TEGRA114_CLK_XUSB_SS 156 +-/* 157 */ +-/* 158 */ +-/* 159 */ +- +-/* 160 */ +-/* 161 */ +-/* 162 */ +-/* 163 */ +-/* 164 */ +-/* 165 */ +-/* 166 */ +-/* 167 */ +-/* 168 */ +-/* 169 */ +-/* 170 */ +-/* 171 */ +-/* 172 */ +-/* 173 */ +-/* 174 */ +-/* 175 */ +-/* 176 */ +-/* 177 */ +-/* 178 */ +-/* 179 */ +-/* 180 */ +-/* 181 */ +-/* 182 */ +-/* 183 */ +-/* 184 */ +-/* 185 */ +-/* 186 */ +-/* 187 */ +-/* 188 */ +-/* 189 */ +-/* 190 */ +-/* 191 */ +- +-#define TEGRA114_CLK_UARTB 192 +-#define TEGRA114_CLK_VFIR 193 +-#define TEGRA114_CLK_SPDIF_IN 194 +-#define TEGRA114_CLK_SPDIF_OUT 195 +-#define TEGRA114_CLK_VI 196 +-#define TEGRA114_CLK_VI_SENSOR 197 +-#define TEGRA114_CLK_FUSE 198 +-#define TEGRA114_CLK_FUSE_BURN 199 +-#define TEGRA114_CLK_CLK_32K 200 +-#define TEGRA114_CLK_CLK_M 201 +-#define TEGRA114_CLK_CLK_M_DIV2 202 +-#define TEGRA114_CLK_CLK_M_DIV4 203 +-#define TEGRA114_CLK_OSC_DIV2 202 +-#define TEGRA114_CLK_OSC_DIV4 203 +-#define TEGRA114_CLK_PLL_REF 204 +-#define TEGRA114_CLK_PLL_C 205 +-#define TEGRA114_CLK_PLL_C_OUT1 206 +-#define TEGRA114_CLK_PLL_C2 207 +-#define TEGRA114_CLK_PLL_C3 208 +-#define TEGRA114_CLK_PLL_M 209 +-#define TEGRA114_CLK_PLL_M_OUT1 210 +-#define TEGRA114_CLK_PLL_P 211 +-#define TEGRA114_CLK_PLL_P_OUT1 212 +-#define TEGRA114_CLK_PLL_P_OUT2 213 +-#define TEGRA114_CLK_PLL_P_OUT3 214 +-#define TEGRA114_CLK_PLL_P_OUT4 215 +-#define TEGRA114_CLK_PLL_A 216 +-#define TEGRA114_CLK_PLL_A_OUT0 217 +-#define TEGRA114_CLK_PLL_D 218 +-#define TEGRA114_CLK_PLL_D_OUT0 219 +-#define TEGRA114_CLK_PLL_D2 220 +-#define TEGRA114_CLK_PLL_D2_OUT0 221 +-#define TEGRA114_CLK_PLL_U 222 +-#define TEGRA114_CLK_PLL_U_480M 223 +- +-#define TEGRA114_CLK_PLL_U_60M 224 +-#define TEGRA114_CLK_PLL_U_48M 225 +-#define TEGRA114_CLK_PLL_U_12M 226 +-#define TEGRA114_CLK_PLL_X 227 +-#define TEGRA114_CLK_PLL_X_OUT0 228 +-#define TEGRA114_CLK_PLL_RE_VCO 229 +-#define TEGRA114_CLK_PLL_RE_OUT 230 +-#define TEGRA114_CLK_PLL_E_OUT0 231 +-#define TEGRA114_CLK_SPDIF_IN_SYNC 232 +-#define TEGRA114_CLK_I2S0_SYNC 233 +-#define TEGRA114_CLK_I2S1_SYNC 234 +-#define TEGRA114_CLK_I2S2_SYNC 235 +-#define TEGRA114_CLK_I2S3_SYNC 236 +-#define TEGRA114_CLK_I2S4_SYNC 237 +-#define TEGRA114_CLK_VIMCLK_SYNC 238 +-#define TEGRA114_CLK_AUDIO0 239 +-#define TEGRA114_CLK_AUDIO1 240 +-#define TEGRA114_CLK_AUDIO2 241 +-#define TEGRA114_CLK_AUDIO3 242 +-#define TEGRA114_CLK_AUDIO4 243 +-#define TEGRA114_CLK_SPDIF 244 +-/* 245 */ +-/* 246 */ +-/* 247 */ +-/* 248 */ +-#define TEGRA114_CLK_OSC 249 +-/* 250 */ +-/* 251 */ +-#define TEGRA114_CLK_XUSB_HOST_SRC 252 +-#define TEGRA114_CLK_XUSB_FALCON_SRC 253 +-#define TEGRA114_CLK_XUSB_FS_SRC 254 +-#define TEGRA114_CLK_XUSB_SS_SRC 255 +- +-#define TEGRA114_CLK_XUSB_DEV_SRC 256 +-#define TEGRA114_CLK_XUSB_DEV 257 +-#define TEGRA114_CLK_XUSB_HS_SRC 258 +-#define TEGRA114_CLK_SCLK 259 +-#define TEGRA114_CLK_HCLK 260 +-#define TEGRA114_CLK_PCLK 261 +-#define TEGRA114_CLK_CCLK_G 262 +-#define TEGRA114_CLK_CCLK_LP 263 +-#define TEGRA114_CLK_DFLL_REF 264 +-#define TEGRA114_CLK_DFLL_SOC 265 +-/* 266 */ +-/* 267 */ +-/* 268 */ +-/* 269 */ +-/* 270 */ +-/* 271 */ +-/* 272 */ +-/* 273 */ +-/* 274 */ +-/* 275 */ +-/* 276 */ +-/* 277 */ +-/* 278 */ +-/* 279 */ +-/* 280 */ +-/* 281 */ +-/* 282 */ +-/* 283 */ +-/* 284 */ +-/* 285 */ +-/* 286 */ +-/* 287 */ +- +-/* 288 */ +-/* 289 */ +-/* 290 */ +-/* 291 */ +-/* 292 */ +-/* 293 */ +-/* 294 */ +-/* 295 */ +-/* 296 */ +-/* 297 */ +-/* 298 */ +-/* 299 */ +-#define TEGRA114_CLK_AUDIO0_MUX 300 +-#define TEGRA114_CLK_AUDIO1_MUX 301 +-#define TEGRA114_CLK_AUDIO2_MUX 302 +-#define TEGRA114_CLK_AUDIO3_MUX 303 +-#define TEGRA114_CLK_AUDIO4_MUX 304 +-#define TEGRA114_CLK_SPDIF_MUX 305 +-/* 306 */ +-/* 307 */ +-/* 308 */ +-#define TEGRA114_CLK_DSIA_MUX 309 +-#define TEGRA114_CLK_DSIB_MUX 310 +-#define TEGRA114_CLK_XUSB_SS_DIV2 311 +-#define TEGRA114_CLK_CLK_MAX 312 +- +-#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/tegra124-car-common.h b/scripts/dtc/include-prefixes/dt-bindings/clock/tegra124-car-common.h +deleted file mode 100644 +index c59f9de01b4d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/tegra124-car-common.h ++++ /dev/null +@@ -1,349 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for binding nvidia,tegra124-car or +- * nvidia,tegra132-car. +- * +- * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB +- * registers. These IDs often match those in the CAR's RST_DEVICES registers, +- * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In +- * this case, those clocks are assigned IDs above 185 in order to highlight +- * this issue. Implementations that interpret these clock IDs as bit values +- * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to +- * explicitly handle these special cases. +- * +- * The balance of the clocks controlled by the CAR are assigned IDs of 185 and +- * above. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H +-#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H +- +-/* 0 */ +-/* 1 */ +-/* 2 */ +-#define TEGRA124_CLK_ISPB 3 +-#define TEGRA124_CLK_RTC 4 +-#define TEGRA124_CLK_TIMER 5 +-#define TEGRA124_CLK_UARTA 6 +-/* 7 (register bit affects uartb and vfir) */ +-/* 8 */ +-#define TEGRA124_CLK_SDMMC2 9 +-/* 10 (register bit affects spdif_in and spdif_out) */ +-#define TEGRA124_CLK_I2S1 11 +-#define TEGRA124_CLK_I2C1 12 +-/* 13 */ +-#define TEGRA124_CLK_SDMMC1 14 +-#define TEGRA124_CLK_SDMMC4 15 +-/* 16 */ +-#define TEGRA124_CLK_PWM 17 +-#define TEGRA124_CLK_I2S2 18 +-/* 20 (register bit affects vi and vi_sensor) */ +-/* 21 */ +-#define TEGRA124_CLK_USBD 22 +-#define TEGRA124_CLK_ISP 23 +-/* 26 */ +-/* 25 */ +-#define TEGRA124_CLK_DISP2 26 +-#define TEGRA124_CLK_DISP1 27 +-#define TEGRA124_CLK_HOST1X 28 +-#define TEGRA124_CLK_VCP 29 +-#define TEGRA124_CLK_I2S0 30 +-/* 31 */ +- +-#define TEGRA124_CLK_MC 32 +-/* 33 */ +-#define TEGRA124_CLK_APBDMA 34 +-/* 35 */ +-#define TEGRA124_CLK_KBC 36 +-/* 37 */ +-/* 38 */ +-/* 39 (register bit affects fuse and fuse_burn) */ +-#define TEGRA124_CLK_KFUSE 40 +-#define TEGRA124_CLK_SBC1 41 +-#define TEGRA124_CLK_NOR 42 +-/* 43 */ +-#define TEGRA124_CLK_SBC2 44 +-/* 45 */ +-#define TEGRA124_CLK_SBC3 46 +-#define TEGRA124_CLK_I2C5 47 +-#define TEGRA124_CLK_DSIA 48 +-/* 49 */ +-#define TEGRA124_CLK_MIPI 50 +-#define TEGRA124_CLK_HDMI 51 +-#define TEGRA124_CLK_CSI 52 +-/* 53 */ +-#define TEGRA124_CLK_I2C2 54 +-#define TEGRA124_CLK_UARTC 55 +-#define TEGRA124_CLK_MIPI_CAL 56 +-#define TEGRA124_CLK_EMC 57 +-#define TEGRA124_CLK_USB2 58 +-#define TEGRA124_CLK_USB3 59 +-/* 60 */ +-#define TEGRA124_CLK_VDE 61 +-#define TEGRA124_CLK_BSEA 62 +-#define TEGRA124_CLK_BSEV 63 +- +-/* 64 */ +-#define TEGRA124_CLK_UARTD 65 +-/* 66 */ +-#define TEGRA124_CLK_I2C3 67 +-#define TEGRA124_CLK_SBC4 68 +-#define TEGRA124_CLK_SDMMC3 69 +-#define TEGRA124_CLK_PCIE 70 +-#define TEGRA124_CLK_OWR 71 +-#define TEGRA124_CLK_AFI 72 +-#define TEGRA124_CLK_CSITE 73 +-/* 74 */ +-/* 75 */ +-#define TEGRA124_CLK_LA 76 +-#define TEGRA124_CLK_TRACE 77 +-#define TEGRA124_CLK_SOC_THERM 78 +-#define TEGRA124_CLK_DTV 79 +-/* 80 */ +-#define TEGRA124_CLK_I2CSLOW 81 +-#define TEGRA124_CLK_DSIB 82 +-#define TEGRA124_CLK_TSEC 83 +-/* 84 */ +-/* 85 */ +-/* 86 */ +-/* 87 */ +-/* 88 */ +-#define TEGRA124_CLK_XUSB_HOST 89 +-/* 90 */ +-#define TEGRA124_CLK_MSENC 91 +-#define TEGRA124_CLK_CSUS 92 +-/* 93 */ +-/* 94 */ +-/* 95 (bit affects xusb_dev and xusb_dev_src) */ +- +-/* 96 */ +-/* 97 */ +-/* 98 */ +-#define TEGRA124_CLK_MSELECT 99 +-#define TEGRA124_CLK_TSENSOR 100 +-#define TEGRA124_CLK_I2S3 101 +-#define TEGRA124_CLK_I2S4 102 +-#define TEGRA124_CLK_I2C4 103 +-#define TEGRA124_CLK_SBC5 104 +-#define TEGRA124_CLK_SBC6 105 +-#define TEGRA124_CLK_D_AUDIO 106 +-#define TEGRA124_CLK_APBIF 107 +-#define TEGRA124_CLK_DAM0 108 +-#define TEGRA124_CLK_DAM1 109 +-#define TEGRA124_CLK_DAM2 110 +-#define TEGRA124_CLK_HDA2CODEC_2X 111 +-/* 112 */ +-#define TEGRA124_CLK_AUDIO0_2X 113 +-#define TEGRA124_CLK_AUDIO1_2X 114 +-#define TEGRA124_CLK_AUDIO2_2X 115 +-#define TEGRA124_CLK_AUDIO3_2X 116 +-#define TEGRA124_CLK_AUDIO4_2X 117 +-#define TEGRA124_CLK_SPDIF_2X 118 +-#define TEGRA124_CLK_ACTMON 119 +-#define TEGRA124_CLK_EXTERN1 120 +-#define TEGRA124_CLK_EXTERN2 121 +-#define TEGRA124_CLK_EXTERN3 122 +-#define TEGRA124_CLK_SATA_OOB 123 +-#define TEGRA124_CLK_SATA 124 +-#define TEGRA124_CLK_HDA 125 +-/* 126 */ +-#define TEGRA124_CLK_SE 127 +- +-#define TEGRA124_CLK_HDA2HDMI 128 +-#define TEGRA124_CLK_SATA_COLD 129 +-/* 130 */ +-/* 131 */ +-/* 132 */ +-/* 133 */ +-/* 134 */ +-/* 135 */ +-#define TEGRA124_CLK_CEC 136 +-/* 137 */ +-/* 138 */ +-/* 139 */ +-/* 140 */ +-/* 141 */ +-/* 142 */ +-/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ +-/* xusb_host_src and xusb_ss_src) */ +-#define TEGRA124_CLK_CILAB 144 +-#define TEGRA124_CLK_CILCD 145 +-#define TEGRA124_CLK_CILE 146 +-#define TEGRA124_CLK_DSIALP 147 +-#define TEGRA124_CLK_DSIBLP 148 +-#define TEGRA124_CLK_ENTROPY 149 +-#define TEGRA124_CLK_DDS 150 +-/* 151 */ +-#define TEGRA124_CLK_DP2 152 +-#define TEGRA124_CLK_AMX 153 +-#define TEGRA124_CLK_ADX 154 +-/* 155 (bit affects dfll_ref and dfll_soc) */ +-#define TEGRA124_CLK_XUSB_SS 156 +-/* 157 */ +-/* 158 */ +-/* 159 */ +- +-/* 160 */ +-/* 161 */ +-/* 162 */ +-/* 163 */ +-/* 164 */ +-/* 165 */ +-#define TEGRA124_CLK_I2C6 166 +-/* 167 */ +-/* 168 */ +-/* 169 */ +-/* 170 */ +-#define TEGRA124_CLK_VIM2_CLK 171 +-/* 172 */ +-/* 173 */ +-/* 174 */ +-/* 175 */ +-#define TEGRA124_CLK_HDMI_AUDIO 176 +-#define TEGRA124_CLK_CLK72MHZ 177 +-#define TEGRA124_CLK_VIC03 178 +-/* 179 */ +-#define TEGRA124_CLK_ADX1 180 +-#define TEGRA124_CLK_DPAUX 181 +-#define TEGRA124_CLK_SOR0 182 +-/* 183 */ +-#define TEGRA124_CLK_GPU 184 +-#define TEGRA124_CLK_AMX1 185 +-/* 186 */ +-/* 187 */ +-/* 188 */ +-/* 189 */ +-/* 190 */ +-/* 191 */ +-#define TEGRA124_CLK_UARTB 192 +-#define TEGRA124_CLK_VFIR 193 +-#define TEGRA124_CLK_SPDIF_IN 194 +-#define TEGRA124_CLK_SPDIF_OUT 195 +-#define TEGRA124_CLK_VI 196 +-#define TEGRA124_CLK_VI_SENSOR 197 +-#define TEGRA124_CLK_FUSE 198 +-#define TEGRA124_CLK_FUSE_BURN 199 +-#define TEGRA124_CLK_CLK_32K 200 +-#define TEGRA124_CLK_CLK_M 201 +-#define TEGRA124_CLK_CLK_M_DIV2 202 +-#define TEGRA124_CLK_CLK_M_DIV4 203 +-#define TEGRA124_CLK_OSC_DIV2 202 +-#define TEGRA124_CLK_OSC_DIV4 203 +-#define TEGRA124_CLK_PLL_REF 204 +-#define TEGRA124_CLK_PLL_C 205 +-#define TEGRA124_CLK_PLL_C_OUT1 206 +-#define TEGRA124_CLK_PLL_C2 207 +-#define TEGRA124_CLK_PLL_C3 208 +-#define TEGRA124_CLK_PLL_M 209 +-#define TEGRA124_CLK_PLL_M_OUT1 210 +-#define TEGRA124_CLK_PLL_P 211 +-#define TEGRA124_CLK_PLL_P_OUT1 212 +-#define TEGRA124_CLK_PLL_P_OUT2 213 +-#define TEGRA124_CLK_PLL_P_OUT3 214 +-#define TEGRA124_CLK_PLL_P_OUT4 215 +-#define TEGRA124_CLK_PLL_A 216 +-#define TEGRA124_CLK_PLL_A_OUT0 217 +-#define TEGRA124_CLK_PLL_D 218 +-#define TEGRA124_CLK_PLL_D_OUT0 219 +-#define TEGRA124_CLK_PLL_D2 220 +-#define TEGRA124_CLK_PLL_D2_OUT0 221 +-#define TEGRA124_CLK_PLL_U 222 +-#define TEGRA124_CLK_PLL_U_480M 223 +- +-#define TEGRA124_CLK_PLL_U_60M 224 +-#define TEGRA124_CLK_PLL_U_48M 225 +-#define TEGRA124_CLK_PLL_U_12M 226 +-/* 227 */ +-/* 228 */ +-#define TEGRA124_CLK_PLL_RE_VCO 229 +-#define TEGRA124_CLK_PLL_RE_OUT 230 +-#define TEGRA124_CLK_PLL_E 231 +-#define TEGRA124_CLK_SPDIF_IN_SYNC 232 +-#define TEGRA124_CLK_I2S0_SYNC 233 +-#define TEGRA124_CLK_I2S1_SYNC 234 +-#define TEGRA124_CLK_I2S2_SYNC 235 +-#define TEGRA124_CLK_I2S3_SYNC 236 +-#define TEGRA124_CLK_I2S4_SYNC 237 +-#define TEGRA124_CLK_VIMCLK_SYNC 238 +-#define TEGRA124_CLK_AUDIO0 239 +-#define TEGRA124_CLK_AUDIO1 240 +-#define TEGRA124_CLK_AUDIO2 241 +-#define TEGRA124_CLK_AUDIO3 242 +-#define TEGRA124_CLK_AUDIO4 243 +-#define TEGRA124_CLK_SPDIF 244 +-/* 245 */ +-/* 246 */ +-/* 247 */ +-/* 248 */ +-#define TEGRA124_CLK_OSC 249 +-/* 250 */ +-/* 251 */ +-#define TEGRA124_CLK_XUSB_HOST_SRC 252 +-#define TEGRA124_CLK_XUSB_FALCON_SRC 253 +-#define TEGRA124_CLK_XUSB_FS_SRC 254 +-#define TEGRA124_CLK_XUSB_SS_SRC 255 +- +-#define TEGRA124_CLK_XUSB_DEV_SRC 256 +-#define TEGRA124_CLK_XUSB_DEV 257 +-#define TEGRA124_CLK_XUSB_HS_SRC 258 +-#define TEGRA124_CLK_SCLK 259 +-#define TEGRA124_CLK_HCLK 260 +-#define TEGRA124_CLK_PCLK 261 +-/* 262 */ +-/* 263 */ +-#define TEGRA124_CLK_DFLL_REF 264 +-#define TEGRA124_CLK_DFLL_SOC 265 +-#define TEGRA124_CLK_VI_SENSOR2 266 +-#define TEGRA124_CLK_PLL_P_OUT5 267 +-#define TEGRA124_CLK_CML0 268 +-#define TEGRA124_CLK_CML1 269 +-#define TEGRA124_CLK_PLL_C4 270 +-#define TEGRA124_CLK_PLL_DP 271 +-#define TEGRA124_CLK_PLL_E_MUX 272 +-#define TEGRA124_CLK_PLL_D_DSI_OUT 273 +-/* 274 */ +-/* 275 */ +-/* 276 */ +-/* 277 */ +-/* 278 */ +-/* 279 */ +-/* 280 */ +-/* 281 */ +-/* 282 */ +-/* 283 */ +-/* 284 */ +-/* 285 */ +-/* 286 */ +-/* 287 */ +- +-/* 288 */ +-/* 289 */ +-/* 290 */ +-/* 291 */ +-/* 292 */ +-/* 293 */ +-/* 294 */ +-/* 295 */ +-/* 296 */ +-/* 297 */ +-/* 298 */ +-/* 299 */ +-#define TEGRA124_CLK_AUDIO0_MUX 300 +-#define TEGRA124_CLK_AUDIO1_MUX 301 +-#define TEGRA124_CLK_AUDIO2_MUX 302 +-#define TEGRA124_CLK_AUDIO3_MUX 303 +-#define TEGRA124_CLK_AUDIO4_MUX 304 +-#define TEGRA124_CLK_SPDIF_MUX 305 +-/* 306 */ +-/* 307 */ +-/* 308 */ +-/* 309 */ +-/* 310 */ +-#define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */ +-#define TEGRA124_CLK_SOR0_OUT 311 +-#define TEGRA124_CLK_XUSB_SS_DIV2 312 +- +-#define TEGRA124_CLK_PLL_M_UD 313 +-#define TEGRA124_CLK_PLL_C_UD 314 +- +-#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/tegra124-car.h b/scripts/dtc/include-prefixes/dt-bindings/clock/tegra124-car.h +deleted file mode 100644 +index c520ee231950..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/tegra124-car.h ++++ /dev/null +@@ -1,20 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides Tegra124-specific constants for binding +- * nvidia,tegra124-car. +- */ +- +-#include +- +-#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H +-#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H +- +-#define TEGRA124_CLK_PLL_X 227 +-#define TEGRA124_CLK_PLL_X_OUT0 228 +- +-#define TEGRA124_CLK_CCLK_G 262 +-#define TEGRA124_CLK_CCLK_LP 263 +- +-#define TEGRA124_CLK_CLK_MAX 315 +- +-#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/tegra186-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/tegra186-clock.h +deleted file mode 100644 +index d6b525f4566f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/tegra186-clock.h ++++ /dev/null +@@ -1,941 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/** @file */ +- +-#ifndef _MACH_T186_CLK_T186_H +-#define _MACH_T186_CLK_T186_H +- +-/** +- * @defgroup clock_ids Clock Identifiers +- * @{ +- * @defgroup extern_input external input clocks +- * @{ +- * @def TEGRA186_CLK_OSC +- * @def TEGRA186_CLK_CLK_32K +- * @def TEGRA186_CLK_DTV_INPUT +- * @def TEGRA186_CLK_SOR0_PAD_CLKOUT +- * @def TEGRA186_CLK_SOR1_PAD_CLKOUT +- * @def TEGRA186_CLK_I2S1_SYNC_INPUT +- * @def TEGRA186_CLK_I2S2_SYNC_INPUT +- * @def TEGRA186_CLK_I2S3_SYNC_INPUT +- * @def TEGRA186_CLK_I2S4_SYNC_INPUT +- * @def TEGRA186_CLK_I2S5_SYNC_INPUT +- * @def TEGRA186_CLK_I2S6_SYNC_INPUT +- * @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT +- * @} +- * +- * @defgroup extern_output external output clocks +- * @{ +- * @def TEGRA186_CLK_EXTPERIPH1 +- * @def TEGRA186_CLK_EXTPERIPH2 +- * @def TEGRA186_CLK_EXTPERIPH3 +- * @def TEGRA186_CLK_EXTPERIPH4 +- * @} +- * +- * @defgroup display_clks display related clocks +- * @{ +- * @def TEGRA186_CLK_CEC +- * @def TEGRA186_CLK_DSIC +- * @def TEGRA186_CLK_DSIC_LP +- * @def TEGRA186_CLK_DSID +- * @def TEGRA186_CLK_DSID_LP +- * @def TEGRA186_CLK_DPAUX1 +- * @def TEGRA186_CLK_DPAUX +- * @def TEGRA186_CLK_HDA2HDMICODEC +- * @def TEGRA186_CLK_NVDISPLAY_DISP +- * @def TEGRA186_CLK_NVDISPLAY_DSC +- * @def TEGRA186_CLK_NVDISPLAY_P0 +- * @def TEGRA186_CLK_NVDISPLAY_P1 +- * @def TEGRA186_CLK_NVDISPLAY_P2 +- * @def TEGRA186_CLK_NVDISPLAYHUB +- * @def TEGRA186_CLK_SOR_SAFE +- * @def TEGRA186_CLK_SOR0 +- * @def TEGRA186_CLK_SOR0_OUT +- * @def TEGRA186_CLK_SOR1 +- * @def TEGRA186_CLK_SOR1_OUT +- * @def TEGRA186_CLK_DSI +- * @def TEGRA186_CLK_MIPI_CAL +- * @def TEGRA186_CLK_DSIA_LP +- * @def TEGRA186_CLK_DSIB +- * @def TEGRA186_CLK_DSIB_LP +- * @} +- * +- * @defgroup camera_clks camera related clocks +- * @{ +- * @def TEGRA186_CLK_NVCSI +- * @def TEGRA186_CLK_NVCSILP +- * @def TEGRA186_CLK_VI +- * @} +- * +- * @defgroup audio_clks audio related clocks +- * @{ +- * @def TEGRA186_CLK_ACLK +- * @def TEGRA186_CLK_ADSP +- * @def TEGRA186_CLK_ADSPNEON +- * @def TEGRA186_CLK_AHUB +- * @def TEGRA186_CLK_APE +- * @def TEGRA186_CLK_APB2APE +- * @def TEGRA186_CLK_AUD_MCLK +- * @def TEGRA186_CLK_DMIC1 +- * @def TEGRA186_CLK_DMIC2 +- * @def TEGRA186_CLK_DMIC3 +- * @def TEGRA186_CLK_DMIC4 +- * @def TEGRA186_CLK_DSPK1 +- * @def TEGRA186_CLK_DSPK2 +- * @def TEGRA186_CLK_HDA +- * @def TEGRA186_CLK_HDA2CODEC_2X +- * @def TEGRA186_CLK_I2S1 +- * @def TEGRA186_CLK_I2S2 +- * @def TEGRA186_CLK_I2S3 +- * @def TEGRA186_CLK_I2S4 +- * @def TEGRA186_CLK_I2S5 +- * @def TEGRA186_CLK_I2S6 +- * @def TEGRA186_CLK_MAUD +- * @def TEGRA186_CLK_PLL_A_OUT0 +- * @def TEGRA186_CLK_SPDIF_DOUBLER +- * @def TEGRA186_CLK_SPDIF_IN +- * @def TEGRA186_CLK_SPDIF_OUT +- * @def TEGRA186_CLK_SYNC_DMIC1 +- * @def TEGRA186_CLK_SYNC_DMIC2 +- * @def TEGRA186_CLK_SYNC_DMIC3 +- * @def TEGRA186_CLK_SYNC_DMIC4 +- * @def TEGRA186_CLK_SYNC_DMIC5 +- * @def TEGRA186_CLK_SYNC_DSPK1 +- * @def TEGRA186_CLK_SYNC_DSPK2 +- * @def TEGRA186_CLK_SYNC_I2S1 +- * @def TEGRA186_CLK_SYNC_I2S2 +- * @def TEGRA186_CLK_SYNC_I2S3 +- * @def TEGRA186_CLK_SYNC_I2S4 +- * @def TEGRA186_CLK_SYNC_I2S5 +- * @def TEGRA186_CLK_SYNC_I2S6 +- * @def TEGRA186_CLK_SYNC_SPDIF +- * @} +- * +- * @defgroup uart_clks UART clocks +- * @{ +- * @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL +- * @def TEGRA186_CLK_UARTA +- * @def TEGRA186_CLK_UARTB +- * @def TEGRA186_CLK_UARTC +- * @def TEGRA186_CLK_UARTD +- * @def TEGRA186_CLK_UARTE +- * @def TEGRA186_CLK_UARTF +- * @def TEGRA186_CLK_UARTG +- * @def TEGRA186_CLK_UART_FST_MIPI_CAL +- * @} +- * +- * @defgroup i2c_clks I2C clocks +- * @{ +- * @def TEGRA186_CLK_AON_I2C_SLOW +- * @def TEGRA186_CLK_I2C1 +- * @def TEGRA186_CLK_I2C2 +- * @def TEGRA186_CLK_I2C3 +- * @def TEGRA186_CLK_I2C4 +- * @def TEGRA186_CLK_I2C5 +- * @def TEGRA186_CLK_I2C6 +- * @def TEGRA186_CLK_I2C8 +- * @def TEGRA186_CLK_I2C9 +- * @def TEGRA186_CLK_I2C1 +- * @def TEGRA186_CLK_I2C12 +- * @def TEGRA186_CLK_I2C13 +- * @def TEGRA186_CLK_I2C14 +- * @def TEGRA186_CLK_I2C_SLOW +- * @def TEGRA186_CLK_VI_I2C +- * @} +- * +- * @defgroup spi_clks SPI clocks +- * @{ +- * @def TEGRA186_CLK_SPI1 +- * @def TEGRA186_CLK_SPI2 +- * @def TEGRA186_CLK_SPI3 +- * @def TEGRA186_CLK_SPI4 +- * @} +- * +- * @defgroup storage storage related clocks +- * @{ +- * @def TEGRA186_CLK_SATA +- * @def TEGRA186_CLK_SATA_OOB +- * @def TEGRA186_CLK_SATA_IOBIST +- * @def TEGRA186_CLK_SDMMC_LEGACY_TM +- * @def TEGRA186_CLK_SDMMC1 +- * @def TEGRA186_CLK_SDMMC2 +- * @def TEGRA186_CLK_SDMMC3 +- * @def TEGRA186_CLK_SDMMC4 +- * @def TEGRA186_CLK_QSPI +- * @def TEGRA186_CLK_QSPI_OUT +- * @def TEGRA186_CLK_UFSDEV_REF +- * @def TEGRA186_CLK_UFSHC +- * @} +- * +- * @defgroup pwm_clks PWM clocks +- * @{ +- * @def TEGRA186_CLK_PWM1 +- * @def TEGRA186_CLK_PWM2 +- * @def TEGRA186_CLK_PWM3 +- * @def TEGRA186_CLK_PWM4 +- * @def TEGRA186_CLK_PWM5 +- * @def TEGRA186_CLK_PWM6 +- * @def TEGRA186_CLK_PWM7 +- * @def TEGRA186_CLK_PWM8 +- * @} +- * +- * @defgroup plls PLLs and related clocks +- * @{ +- * @def TEGRA186_CLK_PLLREFE_OUT_GATED +- * @def TEGRA186_CLK_PLLREFE_OUT1 +- * @def TEGRA186_CLK_PLLD_OUT1 +- * @def TEGRA186_CLK_PLLP_OUT0 +- * @def TEGRA186_CLK_PLLP_OUT5 +- * @def TEGRA186_CLK_PLLA +- * @def TEGRA186_CLK_PLLE_PWRSEQ +- * @def TEGRA186_CLK_PLLA_OUT1 +- * @def TEGRA186_CLK_PLLREFE_REF +- * @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ +- * @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ +- * @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH +- * @def TEGRA186_CLK_PLLREFE_PEX +- * @def TEGRA186_CLK_PLLREFE_IDDQ +- * @def TEGRA186_CLK_PLLC_OUT_AON +- * @def TEGRA186_CLK_PLLC_OUT_ISP +- * @def TEGRA186_CLK_PLLC_OUT_VE +- * @def TEGRA186_CLK_PLLC4_OUT +- * @def TEGRA186_CLK_PLLREFE_OUT +- * @def TEGRA186_CLK_PLLREFE_PLL_REF +- * @def TEGRA186_CLK_PLLE +- * @def TEGRA186_CLK_PLLC +- * @def TEGRA186_CLK_PLLP +- * @def TEGRA186_CLK_PLLD +- * @def TEGRA186_CLK_PLLD2 +- * @def TEGRA186_CLK_PLLREFE_VCO +- * @def TEGRA186_CLK_PLLC2 +- * @def TEGRA186_CLK_PLLC3 +- * @def TEGRA186_CLK_PLLDP +- * @def TEGRA186_CLK_PLLC4_VCO +- * @def TEGRA186_CLK_PLLA1 +- * @def TEGRA186_CLK_PLLNVCSI +- * @def TEGRA186_CLK_PLLDISPHUB +- * @def TEGRA186_CLK_PLLD3 +- * @def TEGRA186_CLK_PLLBPMPCAM +- * @def TEGRA186_CLK_PLLAON +- * @def TEGRA186_CLK_PLLU +- * @def TEGRA186_CLK_PLLC4_VCO_DIV2 +- * @def TEGRA186_CLK_PLL_REF +- * @def TEGRA186_CLK_PLLREFE_OUT1_DIV5 +- * @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ +- * @def TEGRA186_CLK_PLL_U_48M +- * @def TEGRA186_CLK_PLL_U_480M +- * @def TEGRA186_CLK_PLLC4_OUT0 +- * @def TEGRA186_CLK_PLLC4_OUT1 +- * @def TEGRA186_CLK_PLLC4_OUT2 +- * @def TEGRA186_CLK_PLLC4_OUT_MUX +- * @def TEGRA186_CLK_DFLLDISP_DIV +- * @def TEGRA186_CLK_PLLDISPHUB_DIV +- * @def TEGRA186_CLK_PLLP_DIV8 +- * @} +- * +- * @defgroup nafll_clks NAFLL clock sources +- * @{ +- * @def TEGRA186_CLK_NAFLL_AXI_CBB +- * @def TEGRA186_CLK_NAFLL_BCPU +- * @def TEGRA186_CLK_NAFLL_BPMP +- * @def TEGRA186_CLK_NAFLL_DISP +- * @def TEGRA186_CLK_NAFLL_GPU +- * @def TEGRA186_CLK_NAFLL_ISP +- * @def TEGRA186_CLK_NAFLL_MCPU +- * @def TEGRA186_CLK_NAFLL_NVDEC +- * @def TEGRA186_CLK_NAFLL_NVENC +- * @def TEGRA186_CLK_NAFLL_NVJPG +- * @def TEGRA186_CLK_NAFLL_SCE +- * @def TEGRA186_CLK_NAFLL_SE +- * @def TEGRA186_CLK_NAFLL_TSEC +- * @def TEGRA186_CLK_NAFLL_TSECB +- * @def TEGRA186_CLK_NAFLL_VI +- * @def TEGRA186_CLK_NAFLL_VIC +- * @} +- * +- * @defgroup mphy MPHY related clocks +- * @{ +- * @def TEGRA186_CLK_MPHY_L0_RX_SYMB +- * @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT +- * @def TEGRA186_CLK_MPHY_L0_TX_SYMB +- * @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT +- * @def TEGRA186_CLK_MPHY_L0_RX_ANA +- * @def TEGRA186_CLK_MPHY_L1_RX_ANA +- * @def TEGRA186_CLK_MPHY_IOBIST +- * @def TEGRA186_CLK_MPHY_TX_1MHZ_REF +- * @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED +- * @} +- * +- * @defgroup eavb EAVB related clocks +- * @{ +- * @def TEGRA186_CLK_EQOS_AXI +- * @def TEGRA186_CLK_EQOS_PTP_REF +- * @def TEGRA186_CLK_EQOS_RX +- * @def TEGRA186_CLK_EQOS_RX_INPUT +- * @def TEGRA186_CLK_EQOS_TX +- * @} +- * +- * @defgroup usb USB related clocks +- * @{ +- * @def TEGRA186_CLK_PEX_USB_PAD0_MGMT +- * @def TEGRA186_CLK_PEX_USB_PAD1_MGMT +- * @def TEGRA186_CLK_HSIC_TRK +- * @def TEGRA186_CLK_USB2_TRK +- * @def TEGRA186_CLK_USB2_HSIC_TRK +- * @def TEGRA186_CLK_XUSB_CORE_SS +- * @def TEGRA186_CLK_XUSB_CORE_DEV +- * @def TEGRA186_CLK_XUSB_FALCON +- * @def TEGRA186_CLK_XUSB_FS +- * @def TEGRA186_CLK_XUSB +- * @def TEGRA186_CLK_XUSB_DEV +- * @def TEGRA186_CLK_XUSB_HOST +- * @def TEGRA186_CLK_XUSB_SS +- * @} +- * +- * @defgroup bigblock compute block related clocks +- * @{ +- * @def TEGRA186_CLK_GPCCLK +- * @def TEGRA186_CLK_GPC2CLK +- * @def TEGRA186_CLK_GPU +- * @def TEGRA186_CLK_HOST1X +- * @def TEGRA186_CLK_ISP +- * @def TEGRA186_CLK_NVDEC +- * @def TEGRA186_CLK_NVENC +- * @def TEGRA186_CLK_NVJPG +- * @def TEGRA186_CLK_SE +- * @def TEGRA186_CLK_TSEC +- * @def TEGRA186_CLK_TSECB +- * @def TEGRA186_CLK_VIC +- * @} +- * +- * @defgroup can CAN bus related clocks +- * @{ +- * @def TEGRA186_CLK_CAN1 +- * @def TEGRA186_CLK_CAN1_HOST +- * @def TEGRA186_CLK_CAN2 +- * @def TEGRA186_CLK_CAN2_HOST +- * @} +- * +- * @defgroup system basic system clocks +- * @{ +- * @def TEGRA186_CLK_ACTMON +- * @def TEGRA186_CLK_AON_APB +- * @def TEGRA186_CLK_AON_CPU_NIC +- * @def TEGRA186_CLK_AON_NIC +- * @def TEGRA186_CLK_AXI_CBB +- * @def TEGRA186_CLK_BPMP_APB +- * @def TEGRA186_CLK_BPMP_CPU_NIC +- * @def TEGRA186_CLK_BPMP_NIC_RATE +- * @def TEGRA186_CLK_CLK_M +- * @def TEGRA186_CLK_EMC +- * @def TEGRA186_CLK_MSS_ENCRYPT +- * @def TEGRA186_CLK_SCE_APB +- * @def TEGRA186_CLK_SCE_CPU_NIC +- * @def TEGRA186_CLK_SCE_NIC +- * @def TEGRA186_CLK_TSC +- * @} +- * +- * @defgroup pcie_clks PCIe related clocks +- * @{ +- * @def TEGRA186_CLK_AFI +- * @def TEGRA186_CLK_PCIE +- * @def TEGRA186_CLK_PCIE2_IOBIST +- * @def TEGRA186_CLK_PCIERX0 +- * @def TEGRA186_CLK_PCIERX1 +- * @def TEGRA186_CLK_PCIERX2 +- * @def TEGRA186_CLK_PCIERX3 +- * @def TEGRA186_CLK_PCIERX4 +- * @} +- */ +- +-/** @brief output of gate CLK_ENB_FUSE */ +-#define TEGRA186_CLK_FUSE 0 +-/** +- * @brief It's not what you think +- * @details output of gate CLK_ENB_GPU. This output connects to the GPU +- * pwrclk. @warning: This is almost certainly not the clock you think +- * it is. If you're looking for the clock of the graphics engine, see +- * TEGRA186_GPCCLK +- */ +-#define TEGRA186_CLK_GPU 1 +-/** @brief output of gate CLK_ENB_PCIE */ +-#define TEGRA186_CLK_PCIE 3 +-/** @brief output of the divider IPFS_CLK_DIVISOR */ +-#define TEGRA186_CLK_AFI 4 +-/** @brief output of gate CLK_ENB_PCIE2_IOBIST */ +-#define TEGRA186_CLK_PCIE2_IOBIST 5 +-/** @brief output of gate CLK_ENB_PCIERX0*/ +-#define TEGRA186_CLK_PCIERX0 6 +-/** @brief output of gate CLK_ENB_PCIERX1*/ +-#define TEGRA186_CLK_PCIERX1 7 +-/** @brief output of gate CLK_ENB_PCIERX2*/ +-#define TEGRA186_CLK_PCIERX2 8 +-/** @brief output of gate CLK_ENB_PCIERX3*/ +-#define TEGRA186_CLK_PCIERX3 9 +-/** @brief output of gate CLK_ENB_PCIERX4*/ +-#define TEGRA186_CLK_PCIERX4 10 +-/** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */ +-#define TEGRA186_CLK_PLLC_OUT_ISP 11 +-/** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */ +-#define TEGRA186_CLK_PLLC_OUT_VE 12 +-/** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */ +-#define TEGRA186_CLK_PLLC_OUT_AON 13 +-/** @brief output of gate CLK_ENB_SOR_SAFE */ +-#define TEGRA186_CLK_SOR_SAFE 39 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ +-#define TEGRA186_CLK_I2S2 42 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ +-#define TEGRA186_CLK_I2S3 43 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */ +-#define TEGRA186_CLK_SPDIF_IN 44 +-/** @brief output of gate CLK_ENB_SPDIF_DOUBLER */ +-#define TEGRA186_CLK_SPDIF_DOUBLER 45 +-/** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */ +-#define TEGRA186_CLK_SPI3 46 +-/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */ +-#define TEGRA186_CLK_I2C1 47 +-/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */ +-#define TEGRA186_CLK_I2C5 48 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */ +-#define TEGRA186_CLK_SPI1 49 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */ +-#define TEGRA186_CLK_ISP 50 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */ +-#define TEGRA186_CLK_VI 51 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */ +-#define TEGRA186_CLK_SDMMC1 52 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */ +-#define TEGRA186_CLK_SDMMC2 53 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ +-#define TEGRA186_CLK_SDMMC4 54 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ +-#define TEGRA186_CLK_UARTA 55 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */ +-#define TEGRA186_CLK_UARTB 56 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ +-#define TEGRA186_CLK_HOST1X 57 +-/** +- * @brief controls the EMC clock frequency. +- * @details Doing a clk_set_rate on this clock will select the +- * appropriate clock source, program the source rate and execute a +- * specific sequence to switch to the new clock source for both memory +- * controllers. This can be used to control the balance between memory +- * throughput and memory controller power. +- */ +-#define TEGRA186_CLK_EMC 58 +-/* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */ +-#define TEGRA186_CLK_EXTPERIPH4 73 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */ +-#define TEGRA186_CLK_SPI4 74 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ +-#define TEGRA186_CLK_I2C3 75 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */ +-#define TEGRA186_CLK_SDMMC3 76 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */ +-#define TEGRA186_CLK_UARTD 77 +-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ +-#define TEGRA186_CLK_I2S1 79 +-/** output of gate CLK_ENB_DTV */ +-#define TEGRA186_CLK_DTV 80 +-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */ +-#define TEGRA186_CLK_TSEC 81 +-/** @brief output of gate CLK_ENB_DP2 */ +-#define TEGRA186_CLK_DP2 82 +-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ +-#define TEGRA186_CLK_I2S4 84 +-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ +-#define TEGRA186_CLK_I2S5 85 +-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ +-#define TEGRA186_CLK_I2C4 86 +-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ +-#define TEGRA186_CLK_AHUB 87 +-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */ +-#define TEGRA186_CLK_HDA2CODEC_2X 88 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */ +-#define TEGRA186_CLK_EXTPERIPH1 89 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */ +-#define TEGRA186_CLK_EXTPERIPH2 90 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */ +-#define TEGRA186_CLK_EXTPERIPH3 91 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */ +-#define TEGRA186_CLK_I2C_SLOW 92 +-/** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ +-#define TEGRA186_CLK_SOR1 93 +-/** @brief output of gate CLK_ENB_CEC */ +-#define TEGRA186_CLK_CEC 94 +-/** @brief output of gate CLK_ENB_DPAUX1 */ +-#define TEGRA186_CLK_DPAUX1 95 +-/** @brief output of gate CLK_ENB_DPAUX */ +-#define TEGRA186_CLK_DPAUX 96 +-/** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ +-#define TEGRA186_CLK_SOR0 97 +-/** @brief output of gate CLK_ENB_HDA2HDMICODEC */ +-#define TEGRA186_CLK_HDA2HDMICODEC 98 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */ +-#define TEGRA186_CLK_SATA 99 +-/** @brief output of gate CLK_ENB_SATA_OOB */ +-#define TEGRA186_CLK_SATA_OOB 100 +-/** @brief output of gate CLK_ENB_SATA_IOBIST */ +-#define TEGRA186_CLK_SATA_IOBIST 101 +-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */ +-#define TEGRA186_CLK_HDA 102 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */ +-#define TEGRA186_CLK_SE 103 +-/** @brief output of gate CLK_ENB_APB2APE */ +-#define TEGRA186_CLK_APB2APE 104 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ +-#define TEGRA186_CLK_APE 105 +-/** @brief output of gate CLK_ENB_IQC1 */ +-#define TEGRA186_CLK_IQC1 106 +-/** @brief output of gate CLK_ENB_IQC2 */ +-#define TEGRA186_CLK_IQC2 107 +-/** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */ +-#define TEGRA186_CLK_PLLREFE_OUT 108 +-/** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */ +-#define TEGRA186_CLK_PLLREFE_PLL_REF 109 +-/** @brief output of gate CLK_ENB_PLLC4_OUT */ +-#define TEGRA186_CLK_PLLC4_OUT 110 +-/** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */ +-#define TEGRA186_CLK_XUSB 111 +-/** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */ +-#define TEGRA186_CLK_XUSB_DEV 112 +-/** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */ +-#define TEGRA186_CLK_XUSB_HOST 113 +-/** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */ +-#define TEGRA186_CLK_XUSB_SS 114 +-/** @brief output of gate CLK_ENB_DSI */ +-#define TEGRA186_CLK_DSI 115 +-/** @brief output of gate CLK_ENB_MIPI_CAL */ +-#define TEGRA186_CLK_MIPI_CAL 116 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */ +-#define TEGRA186_CLK_DSIA_LP 117 +-/** @brief output of gate CLK_ENB_DSIB */ +-#define TEGRA186_CLK_DSIB 118 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */ +-#define TEGRA186_CLK_DSIB_LP 119 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ +-#define TEGRA186_CLK_DMIC1 122 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ +-#define TEGRA186_CLK_DMIC2 123 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ +-#define TEGRA186_CLK_AUD_MCLK 124 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ +-#define TEGRA186_CLK_I2C6 125 +-/**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */ +-#define TEGRA186_CLK_UART_FST_MIPI_CAL 126 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ +-#define TEGRA186_CLK_VIC 127 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */ +-#define TEGRA186_CLK_SDMMC_LEGACY_TM 128 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */ +-#define TEGRA186_CLK_NVDEC 129 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */ +-#define TEGRA186_CLK_NVJPG 130 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */ +-#define TEGRA186_CLK_NVENC 131 +-/** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ +-#define TEGRA186_CLK_QSPI 132 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */ +-#define TEGRA186_CLK_VI_I2C 133 +-/** @brief output of gate CLK_ENB_HSIC_TRK */ +-#define TEGRA186_CLK_HSIC_TRK 134 +-/** @brief output of gate CLK_ENB_USB2_TRK */ +-#define TEGRA186_CLK_USB2_TRK 135 +-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */ +-#define TEGRA186_CLK_MAUD 136 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */ +-#define TEGRA186_CLK_TSECB 137 +-/** @brief output of gate CLK_ENB_ADSP */ +-#define TEGRA186_CLK_ADSP 138 +-/** @brief output of gate CLK_ENB_ADSPNEON */ +-#define TEGRA186_CLK_ADSPNEON 139 +-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */ +-#define TEGRA186_CLK_MPHY_L0_RX_SYMB 140 +-/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */ +-#define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141 +-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */ +-#define TEGRA186_CLK_MPHY_L0_TX_SYMB 142 +-/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */ +-#define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143 +-/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */ +-#define TEGRA186_CLK_MPHY_L0_RX_ANA 144 +-/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */ +-#define TEGRA186_CLK_MPHY_L1_RX_ANA 145 +-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */ +-#define TEGRA186_CLK_MPHY_IOBIST 146 +-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */ +-#define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147 +-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */ +-#define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */ +-#define TEGRA186_CLK_AXI_CBB 149 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ +-#define TEGRA186_CLK_DMIC3 150 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ +-#define TEGRA186_CLK_DMIC4 151 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ +-#define TEGRA186_CLK_DSPK1 152 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ +-#define TEGRA186_CLK_DSPK2 153 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ +-#define TEGRA186_CLK_I2S6 154 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */ +-#define TEGRA186_CLK_NVDISPLAY_P0 155 +-/** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */ +-#define TEGRA186_CLK_NVDISPLAY_DISP 156 +-/** @brief output of gate CLK_ENB_NVDISPLAY_DSC */ +-#define TEGRA186_CLK_NVDISPLAY_DSC 157 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */ +-#define TEGRA186_CLK_NVDISPLAYHUB 158 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */ +-#define TEGRA186_CLK_NVDISPLAY_P1 159 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */ +-#define TEGRA186_CLK_NVDISPLAY_P2 160 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */ +-#define TEGRA186_CLK_TACH 166 +-/** @brief output of gate CLK_ENB_EQOS */ +-#define TEGRA186_CLK_EQOS_AXI 167 +-/** @brief output of gate CLK_ENB_EQOS_RX */ +-#define TEGRA186_CLK_EQOS_RX 168 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */ +-#define TEGRA186_CLK_UFSHC 178 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */ +-#define TEGRA186_CLK_UFSDEV_REF 179 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */ +-#define TEGRA186_CLK_NVCSI 180 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */ +-#define TEGRA186_CLK_NVCSILP 181 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ +-#define TEGRA186_CLK_I2C7 182 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ +-#define TEGRA186_CLK_I2C9 183 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */ +-#define TEGRA186_CLK_I2C12 184 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */ +-#define TEGRA186_CLK_I2C13 185 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */ +-#define TEGRA186_CLK_I2C14 186 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ +-#define TEGRA186_CLK_PWM1 187 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ +-#define TEGRA186_CLK_PWM2 188 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ +-#define TEGRA186_CLK_PWM3 189 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ +-#define TEGRA186_CLK_PWM5 190 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ +-#define TEGRA186_CLK_PWM6 191 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ +-#define TEGRA186_CLK_PWM7 192 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ +-#define TEGRA186_CLK_PWM8 193 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */ +-#define TEGRA186_CLK_UARTE 194 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */ +-#define TEGRA186_CLK_UARTF 195 +-/** @deprecated */ +-#define TEGRA186_CLK_DBGAPB 196 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */ +-#define TEGRA186_CLK_BPMP_CPU_NIC 197 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */ +-#define TEGRA186_CLK_BPMP_APB 199 +-/** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */ +-#define TEGRA186_CLK_ACTMON 201 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */ +-#define TEGRA186_CLK_AON_CPU_NIC 208 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */ +-#define TEGRA186_CLK_CAN1 210 +-/** @brief output of gate CLK_ENB_CAN1_HOST */ +-#define TEGRA186_CLK_CAN1_HOST 211 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */ +-#define TEGRA186_CLK_CAN2 212 +-/** @brief output of gate CLK_ENB_CAN2_HOST */ +-#define TEGRA186_CLK_CAN2_HOST 213 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */ +-#define TEGRA186_CLK_AON_APB 214 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */ +-#define TEGRA186_CLK_UARTC 215 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */ +-#define TEGRA186_CLK_UARTG 216 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */ +-#define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ +-#define TEGRA186_CLK_I2C2 218 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ +-#define TEGRA186_CLK_I2C8 219 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */ +-#define TEGRA186_CLK_I2C10 220 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */ +-#define TEGRA186_CLK_AON_I2C_SLOW 221 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */ +-#define TEGRA186_CLK_SPI2 222 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */ +-#define TEGRA186_CLK_DMIC5 223 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */ +-#define TEGRA186_CLK_AON_TOUCH 224 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ +-#define TEGRA186_CLK_PWM4 225 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */ +-#define TEGRA186_CLK_TSC 226 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */ +-#define TEGRA186_CLK_MSS_ENCRYPT 227 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */ +-#define TEGRA186_CLK_SCE_CPU_NIC 228 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */ +-#define TEGRA186_CLK_SCE_APB 230 +-/** @brief output of gate CLK_ENB_DSIC */ +-#define TEGRA186_CLK_DSIC 231 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */ +-#define TEGRA186_CLK_DSIC_LP 232 +-/** @brief output of gate CLK_ENB_DSID */ +-#define TEGRA186_CLK_DSID 233 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */ +-#define TEGRA186_CLK_DSID_LP 234 +-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */ +-#define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */ +-#define TEGRA186_CLK_SPDIF_OUT 238 +-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */ +-#define TEGRA186_CLK_EQOS_PTP_REF 239 +-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */ +-#define TEGRA186_CLK_EQOS_TX 240 +-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */ +-#define TEGRA186_CLK_USB2_HSIC_TRK 241 +-/** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */ +-#define TEGRA186_CLK_XUSB_CORE_SS 242 +-/** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */ +-#define TEGRA186_CLK_XUSB_CORE_DEV 243 +-/** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */ +-#define TEGRA186_CLK_XUSB_FALCON 244 +-/** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */ +-#define TEGRA186_CLK_XUSB_FS 245 +-/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ +-#define TEGRA186_CLK_PLL_A_OUT0 246 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ +-#define TEGRA186_CLK_SYNC_I2S1 247 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ +-#define TEGRA186_CLK_SYNC_I2S2 248 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ +-#define TEGRA186_CLK_SYNC_I2S3 249 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ +-#define TEGRA186_CLK_SYNC_I2S4 250 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ +-#define TEGRA186_CLK_SYNC_I2S5 251 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ +-#define TEGRA186_CLK_SYNC_I2S6 252 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ +-#define TEGRA186_CLK_SYNC_DSPK1 253 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ +-#define TEGRA186_CLK_SYNC_DSPK2 254 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ +-#define TEGRA186_CLK_SYNC_DMIC1 255 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ +-#define TEGRA186_CLK_SYNC_DMIC2 256 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ +-#define TEGRA186_CLK_SYNC_DMIC3 257 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ +-#define TEGRA186_CLK_SYNC_DMIC4 259 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */ +-#define TEGRA186_CLK_SYNC_SPDIF 260 +-/** @brief output of gate CLK_ENB_PLLREFE_OUT */ +-#define TEGRA186_CLK_PLLREFE_OUT_GATED 261 +-/** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs: +- * * VCO/pdiv defined by this clock object +- * * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT +- */ +-#define TEGRA186_CLK_PLLREFE_OUT1 262 +-#define TEGRA186_CLK_PLLD_OUT1 267 +-/** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */ +-#define TEGRA186_CLK_PLLP_OUT0 269 +-/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */ +-#define TEGRA186_CLK_PLLP_OUT5 270 +-/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ +-#define TEGRA186_CLK_PLLA 271 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */ +-#define TEGRA186_CLK_ACLK 273 +-/** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */ +-#define TEGRA186_CLK_PLL_U_48M 274 +-/** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */ +-#define TEGRA186_CLK_PLL_U_480M 275 +-/** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */ +-#define TEGRA186_CLK_PLLC4_OUT0 276 +-/** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */ +-#define TEGRA186_CLK_PLLC4_OUT1 277 +-/** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */ +-#define TEGRA186_CLK_PLLC4_OUT2 278 +-/** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */ +-#define TEGRA186_CLK_PLLC4_OUT_MUX 279 +-/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ +-#define TEGRA186_CLK_DFLLDISP_DIV 284 +-/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ +-#define TEGRA186_CLK_PLLDISPHUB_DIV 285 +-/** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */ +-#define TEGRA186_CLK_PLLP_DIV8 286 +-/** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */ +-#define TEGRA186_CLK_BPMP_NIC 287 +-/** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */ +-#define TEGRA186_CLK_PLL_A_OUT1 288 +-/** @deprecated */ +-#define TEGRA186_CLK_GPC2CLK 289 +-/** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */ +-#define TEGRA186_CLK_KFUSE 293 +-/** +- * @brief controls the PLLE hardware sequencer. +- * @details This clock only has enable and disable methods. When the +- * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by +- * hw based on the control signals from the PCIe, SATA and XUSB +- * clocks. When the PLLE hw sequencer is disabled, the state of PLLE +- * is controlled by sw using clk_enable/clk_disable on +- * TEGRA186_CLK_PLLE. +- */ +-#define TEGRA186_CLK_PLLE_PWRSEQ 294 +-/** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */ +-#define TEGRA186_CLK_PLLREFE_REF 295 +-/** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ +-#define TEGRA186_CLK_SOR0_OUT 296 +-/** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ +-#define TEGRA186_CLK_SOR1_OUT 297 +-/** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */ +-#define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298 +-/** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */ +-#define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301 +-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */ +-#define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302 +-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */ +-#define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303 +-/** @brief controls the UPHY_PLL0 hardware sqeuencer */ +-#define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304 +-/** @brief controls the UPHY_PLL1 hardware sqeuencer */ +-#define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305 +-/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */ +-#define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306 +-/** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */ +-#define TEGRA186_CLK_PLLREFE_PEX 307 +-/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */ +-#define TEGRA186_CLK_PLLREFE_IDDQ 308 +-/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ +-#define TEGRA186_CLK_QSPI_OUT 309 +-/** +- * @brief GPC2CLK-div-2 +- * @details fixed /2 divider. Output frequency is +- * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the +- * frequency at which the GPU graphics engine runs. */ +-#define TEGRA186_CLK_GPCCLK 310 +-/** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */ +-#define TEGRA186_CLK_AON_NIC 450 +-/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */ +-#define TEGRA186_CLK_SCE_NIC 451 +-/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */ +-#define TEGRA186_CLK_PLLE 512 +-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */ +-#define TEGRA186_CLK_PLLC 513 +-/** Fixed 408MHz PLL for use by peripheral clocks */ +-#define TEGRA186_CLK_PLLP 516 +-/** @deprecated */ +-#define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP +-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */ +-#define TEGRA186_CLK_PLLD 518 +-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */ +-#define TEGRA186_CLK_PLLD2 519 +-/** +- * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE. +- * @details Note that this clock only controls the VCO output, before +- * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more +- * information. +- */ +-#define TEGRA186_CLK_PLLREFE_VCO 520 +-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */ +-#define TEGRA186_CLK_PLLC2 521 +-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */ +-#define TEGRA186_CLK_PLLC3 522 +-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */ +-#define TEGRA186_CLK_PLLDP 523 +-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ +-#define TEGRA186_CLK_PLLC4_VCO 524 +-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */ +-#define TEGRA186_CLK_PLLA1 525 +-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */ +-#define TEGRA186_CLK_PLLNVCSI 526 +-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */ +-#define TEGRA186_CLK_PLLDISPHUB 527 +-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */ +-#define TEGRA186_CLK_PLLD3 528 +-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */ +-#define TEGRA186_CLK_PLLBPMPCAM 531 +-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */ +-#define TEGRA186_CLK_PLLAON 532 +-/** Fixed frequency 960MHz PLL for USB and EAVB */ +-#define TEGRA186_CLK_PLLU 533 +-/** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */ +-#define TEGRA186_CLK_PLLC4_VCO_DIV2 535 +-/** @brief NAFLL clock source for AXI_CBB */ +-#define TEGRA186_CLK_NAFLL_AXI_CBB 564 +-/** @brief NAFLL clock source for BPMP */ +-#define TEGRA186_CLK_NAFLL_BPMP 565 +-/** @brief NAFLL clock source for ISP */ +-#define TEGRA186_CLK_NAFLL_ISP 566 +-/** @brief NAFLL clock source for NVDEC */ +-#define TEGRA186_CLK_NAFLL_NVDEC 567 +-/** @brief NAFLL clock source for NVENC */ +-#define TEGRA186_CLK_NAFLL_NVENC 568 +-/** @brief NAFLL clock source for NVJPG */ +-#define TEGRA186_CLK_NAFLL_NVJPG 569 +-/** @brief NAFLL clock source for SCE */ +-#define TEGRA186_CLK_NAFLL_SCE 570 +-/** @brief NAFLL clock source for SE */ +-#define TEGRA186_CLK_NAFLL_SE 571 +-/** @brief NAFLL clock source for TSEC */ +-#define TEGRA186_CLK_NAFLL_TSEC 572 +-/** @brief NAFLL clock source for TSECB */ +-#define TEGRA186_CLK_NAFLL_TSECB 573 +-/** @brief NAFLL clock source for VI */ +-#define TEGRA186_CLK_NAFLL_VI 574 +-/** @brief NAFLL clock source for VIC */ +-#define TEGRA186_CLK_NAFLL_VIC 575 +-/** @brief NAFLL clock source for DISP */ +-#define TEGRA186_CLK_NAFLL_DISP 576 +-/** @brief NAFLL clock source for GPU */ +-#define TEGRA186_CLK_NAFLL_GPU 577 +-/** @brief NAFLL clock source for M-CPU cluster */ +-#define TEGRA186_CLK_NAFLL_MCPU 578 +-/** @brief NAFLL clock source for B-CPU cluster */ +-#define TEGRA186_CLK_NAFLL_BCPU 579 +-/** @brief input from Tegra's CLK_32K_IN pad */ +-#define TEGRA186_CLK_CLK_32K 608 +-/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */ +-#define TEGRA186_CLK_CLK_M 609 +-/** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */ +-#define TEGRA186_CLK_PLL_REF 610 +-/** @brief input from Tegra's XTAL_IN */ +-#define TEGRA186_CLK_OSC 612 +-/** @brief clock recovered from EAVB input */ +-#define TEGRA186_CLK_EQOS_RX_INPUT 613 +-/** @brief clock recovered from DTV input */ +-#define TEGRA186_CLK_DTV_INPUT 614 +-/** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/ +-#define TEGRA186_CLK_SOR0_PAD_CLKOUT 615 +-/** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/ +-#define TEGRA186_CLK_SOR1_PAD_CLKOUT 616 +-/** @brief clock recovered from I2S1 input */ +-#define TEGRA186_CLK_I2S1_SYNC_INPUT 617 +-/** @brief clock recovered from I2S2 input */ +-#define TEGRA186_CLK_I2S2_SYNC_INPUT 618 +-/** @brief clock recovered from I2S3 input */ +-#define TEGRA186_CLK_I2S3_SYNC_INPUT 619 +-/** @brief clock recovered from I2S4 input */ +-#define TEGRA186_CLK_I2S4_SYNC_INPUT 620 +-/** @brief clock recovered from I2S5 input */ +-#define TEGRA186_CLK_I2S5_SYNC_INPUT 621 +-/** @brief clock recovered from I2S6 input */ +-#define TEGRA186_CLK_I2S6_SYNC_INPUT 622 +-/** @brief clock recovered from SPDIFIN input */ +-#define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623 +- +-/** +- * @brief subject to change +- * @details maximum clock identifier value plus one. +- */ +-#define TEGRA186_CLK_CLK_MAX 624 +- +-/** @} */ +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/tegra194-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/tegra194-clock.h +deleted file mode 100644 +index a2ff66342d69..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/tegra194-clock.h ++++ /dev/null +@@ -1,321 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ +- +-#ifndef __ABI_MACH_T194_CLOCK_H +-#define __ABI_MACH_T194_CLOCK_H +- +-#define TEGRA194_CLK_ACTMON 1 +-#define TEGRA194_CLK_ADSP 2 +-#define TEGRA194_CLK_ADSPNEON 3 +-#define TEGRA194_CLK_AHUB 4 +-#define TEGRA194_CLK_APB2APE 5 +-#define TEGRA194_CLK_APE 6 +-#define TEGRA194_CLK_AUD_MCLK 7 +-#define TEGRA194_CLK_AXI_CBB 8 +-#define TEGRA194_CLK_CAN1 9 +-#define TEGRA194_CLK_CAN1_HOST 10 +-#define TEGRA194_CLK_CAN2 11 +-#define TEGRA194_CLK_CAN2_HOST 12 +-#define TEGRA194_CLK_CEC 13 +-#define TEGRA194_CLK_CLK_M 14 +-#define TEGRA194_CLK_DMIC1 15 +-#define TEGRA194_CLK_DMIC2 16 +-#define TEGRA194_CLK_DMIC3 17 +-#define TEGRA194_CLK_DMIC4 18 +-#define TEGRA194_CLK_DPAUX 19 +-#define TEGRA194_CLK_DPAUX1 20 +-#define TEGRA194_CLK_ACLK 21 +-#define TEGRA194_CLK_MSS_ENCRYPT 22 +-#define TEGRA194_CLK_EQOS_RX_INPUT 23 +-#define TEGRA194_CLK_IQC2 24 +-#define TEGRA194_CLK_AON_APB 25 +-#define TEGRA194_CLK_AON_NIC 26 +-#define TEGRA194_CLK_AON_CPU_NIC 27 +-#define TEGRA194_CLK_PLLA1 28 +-#define TEGRA194_CLK_DSPK1 29 +-#define TEGRA194_CLK_DSPK2 30 +-#define TEGRA194_CLK_EMC 31 +-#define TEGRA194_CLK_EQOS_AXI 32 +-#define TEGRA194_CLK_EQOS_PTP_REF 33 +-#define TEGRA194_CLK_EQOS_RX 34 +-#define TEGRA194_CLK_EQOS_TX 35 +-#define TEGRA194_CLK_EXTPERIPH1 36 +-#define TEGRA194_CLK_EXTPERIPH2 37 +-#define TEGRA194_CLK_EXTPERIPH3 38 +-#define TEGRA194_CLK_EXTPERIPH4 39 +-#define TEGRA194_CLK_FUSE 40 +-#define TEGRA194_CLK_GPCCLK 41 +-#define TEGRA194_CLK_GPU_PWR 42 +-#define TEGRA194_CLK_HDA 43 +-#define TEGRA194_CLK_HDA2CODEC_2X 44 +-#define TEGRA194_CLK_HDA2HDMICODEC 45 +-#define TEGRA194_CLK_HOST1X 46 +-#define TEGRA194_CLK_HSIC_TRK 47 +-#define TEGRA194_CLK_I2C1 48 +-#define TEGRA194_CLK_I2C2 49 +-#define TEGRA194_CLK_I2C3 50 +-#define TEGRA194_CLK_I2C4 51 +-#define TEGRA194_CLK_I2C6 52 +-#define TEGRA194_CLK_I2C7 53 +-#define TEGRA194_CLK_I2C8 54 +-#define TEGRA194_CLK_I2C9 55 +-#define TEGRA194_CLK_I2S1 56 +-#define TEGRA194_CLK_I2S1_SYNC_INPUT 57 +-#define TEGRA194_CLK_I2S2 58 +-#define TEGRA194_CLK_I2S2_SYNC_INPUT 59 +-#define TEGRA194_CLK_I2S3 60 +-#define TEGRA194_CLK_I2S3_SYNC_INPUT 61 +-#define TEGRA194_CLK_I2S4 62 +-#define TEGRA194_CLK_I2S4_SYNC_INPUT 63 +-#define TEGRA194_CLK_I2S5 64 +-#define TEGRA194_CLK_I2S5_SYNC_INPUT 65 +-#define TEGRA194_CLK_I2S6 66 +-#define TEGRA194_CLK_I2S6_SYNC_INPUT 67 +-#define TEGRA194_CLK_IQC1 68 +-#define TEGRA194_CLK_ISP 69 +-#define TEGRA194_CLK_KFUSE 70 +-#define TEGRA194_CLK_MAUD 71 +-#define TEGRA194_CLK_MIPI_CAL 72 +-#define TEGRA194_CLK_MPHY_CORE_PLL_FIXED 73 +-#define TEGRA194_CLK_MPHY_L0_RX_ANA 74 +-#define TEGRA194_CLK_MPHY_L0_RX_LS_BIT 75 +-#define TEGRA194_CLK_MPHY_L0_RX_SYMB 76 +-#define TEGRA194_CLK_MPHY_L0_TX_LS_3XBIT 77 +-#define TEGRA194_CLK_MPHY_L0_TX_SYMB 78 +-#define TEGRA194_CLK_MPHY_L1_RX_ANA 79 +-#define TEGRA194_CLK_MPHY_TX_1MHZ_REF 80 +-#define TEGRA194_CLK_NVCSI 81 +-#define TEGRA194_CLK_NVCSILP 82 +-#define TEGRA194_CLK_NVDEC 83 +-#define TEGRA194_CLK_NVDISPLAYHUB 84 +-#define TEGRA194_CLK_NVDISPLAY_DISP 85 +-#define TEGRA194_CLK_NVDISPLAY_P0 86 +-#define TEGRA194_CLK_NVDISPLAY_P1 87 +-#define TEGRA194_CLK_NVDISPLAY_P2 88 +-#define TEGRA194_CLK_NVENC 89 +-#define TEGRA194_CLK_NVJPG 90 +-#define TEGRA194_CLK_OSC 91 +-#define TEGRA194_CLK_AON_TOUCH 92 +-#define TEGRA194_CLK_PLLA 93 +-#define TEGRA194_CLK_PLLAON 94 +-#define TEGRA194_CLK_PLLD 95 +-#define TEGRA194_CLK_PLLD2 96 +-#define TEGRA194_CLK_PLLD3 97 +-#define TEGRA194_CLK_PLLDP 98 +-#define TEGRA194_CLK_PLLD4 99 +-#define TEGRA194_CLK_PLLE 100 +-#define TEGRA194_CLK_PLLP 101 +-#define TEGRA194_CLK_PLLP_OUT0 102 +-#define TEGRA194_CLK_UTMIPLL 103 +-#define TEGRA194_CLK_PLLA_OUT0 104 +-#define TEGRA194_CLK_PWM1 105 +-#define TEGRA194_CLK_PWM2 106 +-#define TEGRA194_CLK_PWM3 107 +-#define TEGRA194_CLK_PWM4 108 +-#define TEGRA194_CLK_PWM5 109 +-#define TEGRA194_CLK_PWM6 110 +-#define TEGRA194_CLK_PWM7 111 +-#define TEGRA194_CLK_PWM8 112 +-#define TEGRA194_CLK_RCE_CPU_NIC 113 +-#define TEGRA194_CLK_RCE_NIC 114 +-#define TEGRA194_CLK_SATA 115 +-#define TEGRA194_CLK_SATA_OOB 116 +-#define TEGRA194_CLK_AON_I2C_SLOW 117 +-#define TEGRA194_CLK_SCE_CPU_NIC 118 +-#define TEGRA194_CLK_SCE_NIC 119 +-#define TEGRA194_CLK_SDMMC1 120 +-#define TEGRA194_CLK_UPHY_PLL3 121 +-#define TEGRA194_CLK_SDMMC3 122 +-#define TEGRA194_CLK_SDMMC4 123 +-#define TEGRA194_CLK_SE 124 +-#define TEGRA194_CLK_SOR0_OUT 125 +-#define TEGRA194_CLK_SOR0_REF 126 +-#define TEGRA194_CLK_SOR0_PAD_CLKOUT 127 +-#define TEGRA194_CLK_SOR1_OUT 128 +-#define TEGRA194_CLK_SOR1_REF 129 +-#define TEGRA194_CLK_SOR1_PAD_CLKOUT 130 +-#define TEGRA194_CLK_SOR_SAFE 131 +-#define TEGRA194_CLK_IQC1_IN 132 +-#define TEGRA194_CLK_IQC2_IN 133 +-#define TEGRA194_CLK_DMIC5 134 +-#define TEGRA194_CLK_SPI1 135 +-#define TEGRA194_CLK_SPI2 136 +-#define TEGRA194_CLK_SPI3 137 +-#define TEGRA194_CLK_I2C_SLOW 138 +-#define TEGRA194_CLK_SYNC_DMIC1 139 +-#define TEGRA194_CLK_SYNC_DMIC2 140 +-#define TEGRA194_CLK_SYNC_DMIC3 141 +-#define TEGRA194_CLK_SYNC_DMIC4 142 +-#define TEGRA194_CLK_SYNC_DSPK1 143 +-#define TEGRA194_CLK_SYNC_DSPK2 144 +-#define TEGRA194_CLK_SYNC_I2S1 145 +-#define TEGRA194_CLK_SYNC_I2S2 146 +-#define TEGRA194_CLK_SYNC_I2S3 147 +-#define TEGRA194_CLK_SYNC_I2S4 148 +-#define TEGRA194_CLK_SYNC_I2S5 149 +-#define TEGRA194_CLK_SYNC_I2S6 150 +-#define TEGRA194_CLK_MPHY_FORCE_LS_MODE 151 +-#define TEGRA194_CLK_TACH 152 +-#define TEGRA194_CLK_TSEC 153 +-#define TEGRA194_CLK_TSECB 154 +-#define TEGRA194_CLK_UARTA 155 +-#define TEGRA194_CLK_UARTB 156 +-#define TEGRA194_CLK_UARTC 157 +-#define TEGRA194_CLK_UARTD 158 +-#define TEGRA194_CLK_UARTE 159 +-#define TEGRA194_CLK_UARTF 160 +-#define TEGRA194_CLK_UARTG 161 +-#define TEGRA194_CLK_UART_FST_MIPI_CAL 162 +-#define TEGRA194_CLK_UFSDEV_REF 163 +-#define TEGRA194_CLK_UFSHC 164 +-#define TEGRA194_CLK_USB2_TRK 165 +-#define TEGRA194_CLK_VI 166 +-#define TEGRA194_CLK_VIC 167 +-#define TEGRA194_CLK_PVA0_AXI 168 +-#define TEGRA194_CLK_PVA0_VPS0 169 +-#define TEGRA194_CLK_PVA0_VPS1 170 +-#define TEGRA194_CLK_PVA1_AXI 171 +-#define TEGRA194_CLK_PVA1_VPS0 172 +-#define TEGRA194_CLK_PVA1_VPS1 173 +-#define TEGRA194_CLK_DLA0_FALCON 174 +-#define TEGRA194_CLK_DLA0_CORE 175 +-#define TEGRA194_CLK_DLA1_FALCON 176 +-#define TEGRA194_CLK_DLA1_CORE 177 +-#define TEGRA194_CLK_SOR2_OUT 178 +-#define TEGRA194_CLK_SOR2_REF 179 +-#define TEGRA194_CLK_SOR2_PAD_CLKOUT 180 +-#define TEGRA194_CLK_SOR3_OUT 181 +-#define TEGRA194_CLK_SOR3_REF 182 +-#define TEGRA194_CLK_SOR3_PAD_CLKOUT 183 +-#define TEGRA194_CLK_NVDISPLAY_P3 184 +-#define TEGRA194_CLK_DPAUX2 185 +-#define TEGRA194_CLK_DPAUX3 186 +-#define TEGRA194_CLK_NVDEC1 187 +-#define TEGRA194_CLK_NVENC1 188 +-#define TEGRA194_CLK_SE_FREE 189 +-#define TEGRA194_CLK_UARTH 190 +-#define TEGRA194_CLK_FUSE_SERIAL 191 +-#define TEGRA194_CLK_QSPI0 192 +-#define TEGRA194_CLK_QSPI1 193 +-#define TEGRA194_CLK_QSPI0_PM 194 +-#define TEGRA194_CLK_QSPI1_PM 195 +-#define TEGRA194_CLK_VI_CONST 196 +-#define TEGRA194_CLK_NAFLL_BPMP 197 +-#define TEGRA194_CLK_NAFLL_SCE 198 +-#define TEGRA194_CLK_NAFLL_NVDEC 199 +-#define TEGRA194_CLK_NAFLL_NVJPG 200 +-#define TEGRA194_CLK_NAFLL_TSEC 201 +-#define TEGRA194_CLK_NAFLL_TSECB 202 +-#define TEGRA194_CLK_NAFLL_VI 203 +-#define TEGRA194_CLK_NAFLL_SE 204 +-#define TEGRA194_CLK_NAFLL_NVENC 205 +-#define TEGRA194_CLK_NAFLL_ISP 206 +-#define TEGRA194_CLK_NAFLL_VIC 207 +-#define TEGRA194_CLK_NAFLL_NVDISPLAYHUB 208 +-#define TEGRA194_CLK_NAFLL_AXICBB 209 +-#define TEGRA194_CLK_NAFLL_DLA 210 +-#define TEGRA194_CLK_NAFLL_PVA_CORE 211 +-#define TEGRA194_CLK_NAFLL_PVA_VPS 212 +-#define TEGRA194_CLK_NAFLL_CVNAS 213 +-#define TEGRA194_CLK_NAFLL_RCE 214 +-#define TEGRA194_CLK_NAFLL_NVENC1 215 +-#define TEGRA194_CLK_NAFLL_DLA_FALCON 216 +-#define TEGRA194_CLK_NAFLL_NVDEC1 217 +-#define TEGRA194_CLK_NAFLL_GPU 218 +-#define TEGRA194_CLK_SDMMC_LEGACY_TM 219 +-#define TEGRA194_CLK_PEX0_CORE_0 220 +-#define TEGRA194_CLK_PEX0_CORE_1 221 +-#define TEGRA194_CLK_PEX0_CORE_2 222 +-#define TEGRA194_CLK_PEX0_CORE_3 223 +-#define TEGRA194_CLK_PEX0_CORE_4 224 +-#define TEGRA194_CLK_PEX1_CORE_5 225 +-#define TEGRA194_CLK_PEX_REF1 226 +-#define TEGRA194_CLK_PEX_REF2 227 +-#define TEGRA194_CLK_CSI_A 229 +-#define TEGRA194_CLK_CSI_B 230 +-#define TEGRA194_CLK_CSI_C 231 +-#define TEGRA194_CLK_CSI_D 232 +-#define TEGRA194_CLK_CSI_E 233 +-#define TEGRA194_CLK_CSI_F 234 +-#define TEGRA194_CLK_CSI_G 235 +-#define TEGRA194_CLK_CSI_H 236 +-#define TEGRA194_CLK_PLLC4 237 +-#define TEGRA194_CLK_PLLC4_OUT 238 +-#define TEGRA194_CLK_PLLC4_OUT1 239 +-#define TEGRA194_CLK_PLLC4_OUT2 240 +-#define TEGRA194_CLK_PLLC4_MUXED 241 +-#define TEGRA194_CLK_PLLC4_VCO_DIV2 242 +-#define TEGRA194_CLK_CSI_A_PAD 244 +-#define TEGRA194_CLK_CSI_B_PAD 245 +-#define TEGRA194_CLK_CSI_C_PAD 246 +-#define TEGRA194_CLK_CSI_D_PAD 247 +-#define TEGRA194_CLK_CSI_E_PAD 248 +-#define TEGRA194_CLK_CSI_F_PAD 249 +-#define TEGRA194_CLK_CSI_G_PAD 250 +-#define TEGRA194_CLK_CSI_H_PAD 251 +-#define TEGRA194_CLK_PEX_SATA_USB_RX_BYP 254 +-#define TEGRA194_CLK_PEX_USB_PAD_PLL0_MGMT 255 +-#define TEGRA194_CLK_PEX_USB_PAD_PLL1_MGMT 256 +-#define TEGRA194_CLK_PEX_USB_PAD_PLL2_MGMT 257 +-#define TEGRA194_CLK_PEX_USB_PAD_PLL3_MGMT 258 +-#define TEGRA194_CLK_XUSB_CORE_DEV 265 +-#define TEGRA194_CLK_XUSB_CORE_MUX 266 +-#define TEGRA194_CLK_XUSB_CORE_HOST 267 +-#define TEGRA194_CLK_XUSB_CORE_SS 268 +-#define TEGRA194_CLK_XUSB_FALCON 269 +-#define TEGRA194_CLK_XUSB_FALCON_HOST 270 +-#define TEGRA194_CLK_XUSB_FALCON_SS 271 +-#define TEGRA194_CLK_XUSB_FS 272 +-#define TEGRA194_CLK_XUSB_FS_HOST 273 +-#define TEGRA194_CLK_XUSB_FS_DEV 274 +-#define TEGRA194_CLK_XUSB_SS 275 +-#define TEGRA194_CLK_XUSB_SS_DEV 276 +-#define TEGRA194_CLK_XUSB_SS_SUPERSPEED 277 +-#define TEGRA194_CLK_PLLDISPHUB 278 +-#define TEGRA194_CLK_PLLDISPHUB_DIV 279 +-#define TEGRA194_CLK_NAFLL_CLUSTER0 280 +-#define TEGRA194_CLK_NAFLL_CLUSTER1 281 +-#define TEGRA194_CLK_NAFLL_CLUSTER2 282 +-#define TEGRA194_CLK_NAFLL_CLUSTER3 283 +-#define TEGRA194_CLK_CAN1_CORE 284 +-#define TEGRA194_CLK_CAN2_CORE 285 +-#define TEGRA194_CLK_PLLA1_OUT1 286 +-#define TEGRA194_CLK_PLLREFE_VCOOUT 288 +-#define TEGRA194_CLK_CLK_32K 289 +-#define TEGRA194_CLK_SPDIFIN_SYNC_INPUT 290 +-#define TEGRA194_CLK_UTMIPLL_CLKOUT48 291 +-#define TEGRA194_CLK_UTMIPLL_CLKOUT480 292 +-#define TEGRA194_CLK_CVNAS 293 +-#define TEGRA194_CLK_PLLNVCSI 294 +-#define TEGRA194_CLK_PVA0_CPU_AXI 295 +-#define TEGRA194_CLK_PVA1_CPU_AXI 296 +-#define TEGRA194_CLK_PVA0_VPS 297 +-#define TEGRA194_CLK_PVA1_VPS 298 +-#define TEGRA194_CLK_DLA0_FALCON_MUX 299 +-#define TEGRA194_CLK_DLA1_FALCON_MUX 300 +-#define TEGRA194_CLK_DLA0_CORE_MUX 301 +-#define TEGRA194_CLK_DLA1_CORE_MUX 302 +-#define TEGRA194_CLK_UTMIPLL_HPS 304 +-#define TEGRA194_CLK_I2C5 305 +-#define TEGRA194_CLK_I2C10 306 +-#define TEGRA194_CLK_BPMP_CPU_NIC 307 +-#define TEGRA194_CLK_BPMP_APB 308 +-#define TEGRA194_CLK_TSC 309 +-#define TEGRA194_CLK_EMCSA 310 +-#define TEGRA194_CLK_EMCSB 311 +-#define TEGRA194_CLK_EMCSC 312 +-#define TEGRA194_CLK_EMCSD 313 +-#define TEGRA194_CLK_PLLC 314 +-#define TEGRA194_CLK_PLLC2 315 +-#define TEGRA194_CLK_PLLC3 316 +-#define TEGRA194_CLK_TSC_REF 317 +-#define TEGRA194_CLK_FUSE_BURN 318 +-#define TEGRA194_CLK_PEX0_CORE_0M 319 +-#define TEGRA194_CLK_PEX0_CORE_1M 320 +-#define TEGRA194_CLK_PEX0_CORE_2M 321 +-#define TEGRA194_CLK_PEX0_CORE_3M 322 +-#define TEGRA194_CLK_PEX0_CORE_4M 323 +-#define TEGRA194_CLK_PEX1_CORE_5M 324 +-#define TEGRA194_CLK_PLLE_HPS 326 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/tegra20-car.h b/scripts/dtc/include-prefixes/dt-bindings/clock/tegra20-car.h +deleted file mode 100644 +index fe541f627965..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/tegra20-car.h ++++ /dev/null +@@ -1,159 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for binding nvidia,tegra20-car. +- * +- * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB +- * registers. These IDs often match those in the CAR's RST_DEVICES registers, +- * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In +- * this case, those clocks are assigned IDs above 95 in order to highlight +- * this issue. Implementations that interpret these clock IDs as bit values +- * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to +- * explicitly handle these special cases. +- * +- * The balance of the clocks controlled by the CAR are assigned IDs of 96 and +- * above. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H +-#define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H +- +-#define TEGRA20_CLK_CPU 0 +-/* 1 */ +-/* 2 */ +-#define TEGRA20_CLK_AC97 3 +-#define TEGRA20_CLK_RTC 4 +-#define TEGRA20_CLK_TIMER 5 +-#define TEGRA20_CLK_UARTA 6 +-/* 7 (register bit affects uart2 and vfir) */ +-#define TEGRA20_CLK_GPIO 8 +-#define TEGRA20_CLK_SDMMC2 9 +-/* 10 (register bit affects spdif_in and spdif_out) */ +-#define TEGRA20_CLK_I2S1 11 +-#define TEGRA20_CLK_I2C1 12 +-#define TEGRA20_CLK_NDFLASH 13 +-#define TEGRA20_CLK_SDMMC1 14 +-#define TEGRA20_CLK_SDMMC4 15 +-#define TEGRA20_CLK_TWC 16 +-#define TEGRA20_CLK_PWM 17 +-#define TEGRA20_CLK_I2S2 18 +-#define TEGRA20_CLK_EPP 19 +-/* 20 (register bit affects vi and vi_sensor) */ +-#define TEGRA20_CLK_GR2D 21 +-#define TEGRA20_CLK_USBD 22 +-#define TEGRA20_CLK_ISP 23 +-#define TEGRA20_CLK_GR3D 24 +-#define TEGRA20_CLK_IDE 25 +-#define TEGRA20_CLK_DISP2 26 +-#define TEGRA20_CLK_DISP1 27 +-#define TEGRA20_CLK_HOST1X 28 +-#define TEGRA20_CLK_VCP 29 +-/* 30 */ +-#define TEGRA20_CLK_CACHE2 31 +- +-#define TEGRA20_CLK_MC 32 +-#define TEGRA20_CLK_AHBDMA 33 +-#define TEGRA20_CLK_APBDMA 34 +-/* 35 */ +-#define TEGRA20_CLK_KBC 36 +-#define TEGRA20_CLK_STAT_MON 37 +-#define TEGRA20_CLK_PMC 38 +-#define TEGRA20_CLK_FUSE 39 +-#define TEGRA20_CLK_KFUSE 40 +-#define TEGRA20_CLK_SBC1 41 +-#define TEGRA20_CLK_NOR 42 +-#define TEGRA20_CLK_SPI 43 +-#define TEGRA20_CLK_SBC2 44 +-#define TEGRA20_CLK_XIO 45 +-#define TEGRA20_CLK_SBC3 46 +-#define TEGRA20_CLK_DVC 47 +-#define TEGRA20_CLK_DSI 48 +-/* 49 (register bit affects tvo and cve) */ +-#define TEGRA20_CLK_MIPI 50 +-#define TEGRA20_CLK_HDMI 51 +-#define TEGRA20_CLK_CSI 52 +-#define TEGRA20_CLK_TVDAC 53 +-#define TEGRA20_CLK_I2C2 54 +-#define TEGRA20_CLK_UARTC 55 +-/* 56 */ +-#define TEGRA20_CLK_EMC 57 +-#define TEGRA20_CLK_USB2 58 +-#define TEGRA20_CLK_USB3 59 +-#define TEGRA20_CLK_MPE 60 +-#define TEGRA20_CLK_VDE 61 +-#define TEGRA20_CLK_BSEA 62 +-#define TEGRA20_CLK_BSEV 63 +- +-#define TEGRA20_CLK_SPEEDO 64 +-#define TEGRA20_CLK_UARTD 65 +-#define TEGRA20_CLK_UARTE 66 +-#define TEGRA20_CLK_I2C3 67 +-#define TEGRA20_CLK_SBC4 68 +-#define TEGRA20_CLK_SDMMC3 69 +-#define TEGRA20_CLK_PEX 70 +-#define TEGRA20_CLK_OWR 71 +-#define TEGRA20_CLK_AFI 72 +-#define TEGRA20_CLK_CSITE 73 +-/* 74 */ +-#define TEGRA20_CLK_AVPUCQ 75 +-#define TEGRA20_CLK_LA 76 +-/* 77 */ +-/* 78 */ +-/* 79 */ +-/* 80 */ +-/* 81 */ +-/* 82 */ +-/* 83 */ +-#define TEGRA20_CLK_IRAMA 84 +-#define TEGRA20_CLK_IRAMB 85 +-#define TEGRA20_CLK_IRAMC 86 +-#define TEGRA20_CLK_IRAMD 87 +-#define TEGRA20_CLK_CRAM2 88 +-#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */ +-#define TEGRA20_CLK_CLK_D 90 +-/* 91 */ +-#define TEGRA20_CLK_CSUS 92 +-#define TEGRA20_CLK_CDEV2 93 +-#define TEGRA20_CLK_CDEV1 94 +-/* 95 */ +- +-#define TEGRA20_CLK_UARTB 96 +-#define TEGRA20_CLK_VFIR 97 +-#define TEGRA20_CLK_SPDIF_IN 98 +-#define TEGRA20_CLK_SPDIF_OUT 99 +-#define TEGRA20_CLK_VI 100 +-#define TEGRA20_CLK_VI_SENSOR 101 +-#define TEGRA20_CLK_TVO 102 +-#define TEGRA20_CLK_CVE 103 +-#define TEGRA20_CLK_OSC 104 +-#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */ +-#define TEGRA20_CLK_CLK_M 106 +-#define TEGRA20_CLK_SCLK 107 +-#define TEGRA20_CLK_CCLK 108 +-#define TEGRA20_CLK_HCLK 109 +-#define TEGRA20_CLK_PCLK 110 +-/* 111 */ +-#define TEGRA20_CLK_PLL_A 112 +-#define TEGRA20_CLK_PLL_A_OUT0 113 +-#define TEGRA20_CLK_PLL_C 114 +-#define TEGRA20_CLK_PLL_C_OUT1 115 +-#define TEGRA20_CLK_PLL_D 116 +-#define TEGRA20_CLK_PLL_D_OUT0 117 +-#define TEGRA20_CLK_PLL_E 118 +-#define TEGRA20_CLK_PLL_M 119 +-#define TEGRA20_CLK_PLL_M_OUT1 120 +-#define TEGRA20_CLK_PLL_P 121 +-#define TEGRA20_CLK_PLL_P_OUT1 122 +-#define TEGRA20_CLK_PLL_P_OUT2 123 +-#define TEGRA20_CLK_PLL_P_OUT3 124 +-#define TEGRA20_CLK_PLL_P_OUT4 125 +-#define TEGRA20_CLK_PLL_S 126 +-#define TEGRA20_CLK_PLL_U 127 +- +-#define TEGRA20_CLK_PLL_X 128 +-#define TEGRA20_CLK_COP 129 /* a/k/a avp */ +-#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */ +-#define TEGRA20_CLK_PLL_REF 131 +-#define TEGRA20_CLK_TWD 132 +-#define TEGRA20_CLK_CLK_MAX 133 +- +-#endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/tegra210-car.h b/scripts/dtc/include-prefixes/dt-bindings/clock/tegra210-car.h +deleted file mode 100644 +index 9cfcc3baa52c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/tegra210-car.h ++++ /dev/null +@@ -1,414 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for binding nvidia,tegra210-car. +- * +- * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB +- * registers. These IDs often match those in the CAR's RST_DEVICES registers, +- * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In +- * this case, those clocks are assigned IDs above 224 in order to highlight +- * this issue. Implementations that interpret these clock IDs as bit values +- * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to +- * explicitly handle these special cases. +- * +- * The balance of the clocks controlled by the CAR are assigned IDs of 224 and +- * above. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H +-#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H +- +-/* 0 */ +-/* 1 */ +-/* 2 */ +-#define TEGRA210_CLK_ISPB 3 +-#define TEGRA210_CLK_RTC 4 +-#define TEGRA210_CLK_TIMER 5 +-#define TEGRA210_CLK_UARTA 6 +-/* 7 (register bit affects uartb and vfir) */ +-#define TEGRA210_CLK_GPIO 8 +-#define TEGRA210_CLK_SDMMC2 9 +-/* 10 (register bit affects spdif_in and spdif_out) */ +-#define TEGRA210_CLK_I2S1 11 +-#define TEGRA210_CLK_I2C1 12 +-/* 13 */ +-#define TEGRA210_CLK_SDMMC1 14 +-#define TEGRA210_CLK_SDMMC4 15 +-/* 16 */ +-#define TEGRA210_CLK_PWM 17 +-#define TEGRA210_CLK_I2S2 18 +-/* 19 */ +-/* 20 (register bit affects vi and vi_sensor) */ +-/* 21 */ +-#define TEGRA210_CLK_USBD 22 +-#define TEGRA210_CLK_ISPA 23 +-/* 24 */ +-/* 25 */ +-#define TEGRA210_CLK_DISP2 26 +-#define TEGRA210_CLK_DISP1 27 +-#define TEGRA210_CLK_HOST1X 28 +-/* 29 */ +-#define TEGRA210_CLK_I2S0 30 +-/* 31 */ +- +-#define TEGRA210_CLK_MC 32 +-#define TEGRA210_CLK_AHBDMA 33 +-#define TEGRA210_CLK_APBDMA 34 +-/* 35 */ +-/* 36 */ +-/* 37 */ +-#define TEGRA210_CLK_PMC 38 +-/* 39 (register bit affects fuse and fuse_burn) */ +-#define TEGRA210_CLK_KFUSE 40 +-#define TEGRA210_CLK_SBC1 41 +-/* 42 */ +-/* 43 */ +-#define TEGRA210_CLK_SBC2 44 +-/* 45 */ +-#define TEGRA210_CLK_SBC3 46 +-#define TEGRA210_CLK_I2C5 47 +-#define TEGRA210_CLK_DSIA 48 +-/* 49 */ +-/* 50 */ +-/* 51 */ +-#define TEGRA210_CLK_CSI 52 +-/* 53 */ +-#define TEGRA210_CLK_I2C2 54 +-#define TEGRA210_CLK_UARTC 55 +-#define TEGRA210_CLK_MIPI_CAL 56 +-#define TEGRA210_CLK_EMC 57 +-#define TEGRA210_CLK_USB2 58 +-/* 59 */ +-/* 60 */ +-/* 61 */ +-/* 62 */ +-#define TEGRA210_CLK_BSEV 63 +- +-/* 64 */ +-#define TEGRA210_CLK_UARTD 65 +-/* 66 */ +-#define TEGRA210_CLK_I2C3 67 +-#define TEGRA210_CLK_SBC4 68 +-#define TEGRA210_CLK_SDMMC3 69 +-#define TEGRA210_CLK_PCIE 70 +-#define TEGRA210_CLK_OWR 71 +-#define TEGRA210_CLK_AFI 72 +-#define TEGRA210_CLK_CSITE 73 +-/* 74 */ +-/* 75 */ +-#define TEGRA210_CLK_LA 76 +-/* 77 */ +-#define TEGRA210_CLK_SOC_THERM 78 +-#define TEGRA210_CLK_DTV 79 +-/* 80 */ +-#define TEGRA210_CLK_I2CSLOW 81 +-#define TEGRA210_CLK_DSIB 82 +-#define TEGRA210_CLK_TSEC 83 +-/* 84 */ +-/* 85 */ +-/* 86 */ +-/* 87 */ +-/* 88 */ +-#define TEGRA210_CLK_XUSB_HOST 89 +-/* 90 */ +-/* 91 */ +-#define TEGRA210_CLK_CSUS 92 +-/* 93 */ +-/* 94 */ +-/* 95 (bit affects xusb_dev and xusb_dev_src) */ +- +-/* 96 */ +-/* 97 */ +-/* 98 */ +-#define TEGRA210_CLK_MSELECT 99 +-#define TEGRA210_CLK_TSENSOR 100 +-#define TEGRA210_CLK_I2S3 101 +-#define TEGRA210_CLK_I2S4 102 +-#define TEGRA210_CLK_I2C4 103 +-/* 104 */ +-/* 105 */ +-#define TEGRA210_CLK_D_AUDIO 106 +-#define TEGRA210_CLK_APB2APE 107 +-/* 108 */ +-/* 109 */ +-/* 110 */ +-#define TEGRA210_CLK_HDA2CODEC_2X 111 +-/* 112 */ +-/* 113 */ +-/* 114 */ +-/* 115 */ +-/* 116 */ +-/* 117 */ +-#define TEGRA210_CLK_SPDIF_2X 118 +-#define TEGRA210_CLK_ACTMON 119 +-#define TEGRA210_CLK_EXTERN1 120 +-#define TEGRA210_CLK_EXTERN2 121 +-#define TEGRA210_CLK_EXTERN3 122 +-#define TEGRA210_CLK_SATA_OOB 123 +-#define TEGRA210_CLK_SATA 124 +-#define TEGRA210_CLK_HDA 125 +-/* 126 */ +-/* 127 */ +- +-#define TEGRA210_CLK_HDA2HDMI 128 +-/* 129 */ +-/* 130 */ +-/* 131 */ +-/* 132 */ +-/* 133 */ +-/* 134 */ +-/* 135 */ +-#define TEGRA210_CLK_CEC 136 +-/* 137 */ +-/* 138 */ +-/* 139 */ +-/* 140 */ +-/* 141 */ +-/* 142 */ +-/* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */ +-#define TEGRA210_CLK_XUSB_GATE 143 +-#define TEGRA210_CLK_CILAB 144 +-#define TEGRA210_CLK_CILCD 145 +-#define TEGRA210_CLK_CILE 146 +-#define TEGRA210_CLK_DSIALP 147 +-#define TEGRA210_CLK_DSIBLP 148 +-#define TEGRA210_CLK_ENTROPY 149 +-/* 150 */ +-/* 151 */ +-#define TEGRA210_CLK_DP2 152 +-/* 153 */ +-/* 154 */ +-/* 155 (bit affects dfll_ref and dfll_soc) */ +-#define TEGRA210_CLK_XUSB_SS 156 +-/* 157 */ +-/* 158 */ +-/* 159 */ +- +-/* 160 */ +-#define TEGRA210_CLK_DMIC1 161 +-#define TEGRA210_CLK_DMIC2 162 +-/* 163 */ +-/* 164 */ +-/* 165 */ +-#define TEGRA210_CLK_I2C6 166 +-/* 167 */ +-/* 168 */ +-/* 169 */ +-/* 170 */ +-#define TEGRA210_CLK_VIM2_CLK 171 +-/* 172 */ +-#define TEGRA210_CLK_MIPIBIF 173 +-/* 174 */ +-/* 175 */ +-/* 176 */ +-#define TEGRA210_CLK_CLK72MHZ 177 +-#define TEGRA210_CLK_VIC03 178 +-/* 179 */ +-/* 180 */ +-#define TEGRA210_CLK_DPAUX 181 +-#define TEGRA210_CLK_SOR0 182 +-#define TEGRA210_CLK_SOR1 183 +-#define TEGRA210_CLK_GPU 184 +-#define TEGRA210_CLK_DBGAPB 185 +-/* 186 */ +-#define TEGRA210_CLK_PLL_P_OUT_ADSP 187 +-/* 188 ((bit affects pll_a_out_adsp and pll_a_out0_out_adsp)*/ +-#define TEGRA210_CLK_PLL_G_REF 189 +-/* 190 */ +-/* 191 */ +- +-/* 192 */ +-#define TEGRA210_CLK_SDMMC_LEGACY 193 +-#define TEGRA210_CLK_NVDEC 194 +-#define TEGRA210_CLK_NVJPG 195 +-/* 196 */ +-#define TEGRA210_CLK_DMIC3 197 +-#define TEGRA210_CLK_APE 198 +-#define TEGRA210_CLK_ADSP 199 +-/* 200 */ +-/* 201 */ +-#define TEGRA210_CLK_MAUD 202 +-/* 203 */ +-/* 204 */ +-/* 205 */ +-#define TEGRA210_CLK_TSECB 206 +-#define TEGRA210_CLK_DPAUX1 207 +-#define TEGRA210_CLK_VI_I2C 208 +-#define TEGRA210_CLK_HSIC_TRK 209 +-#define TEGRA210_CLK_USB2_TRK 210 +-#define TEGRA210_CLK_QSPI 211 +-#define TEGRA210_CLK_UARTAPE 212 +-/* 213 */ +-/* 214 */ +-/* 215 */ +-/* 216 */ +-/* 217 */ +-#define TEGRA210_CLK_ADSP_NEON 218 +-#define TEGRA210_CLK_NVENC 219 +-#define TEGRA210_CLK_IQC2 220 +-#define TEGRA210_CLK_IQC1 221 +-#define TEGRA210_CLK_SOR_SAFE 222 +-#define TEGRA210_CLK_PLL_P_OUT_CPU 223 +- +- +-#define TEGRA210_CLK_UARTB 224 +-#define TEGRA210_CLK_VFIR 225 +-#define TEGRA210_CLK_SPDIF_IN 226 +-#define TEGRA210_CLK_SPDIF_OUT 227 +-#define TEGRA210_CLK_VI 228 +-#define TEGRA210_CLK_VI_SENSOR 229 +-#define TEGRA210_CLK_FUSE 230 +-#define TEGRA210_CLK_FUSE_BURN 231 +-#define TEGRA210_CLK_CLK_32K 232 +-#define TEGRA210_CLK_CLK_M 233 +-#define TEGRA210_CLK_CLK_M_DIV2 234 +-#define TEGRA210_CLK_CLK_M_DIV4 235 +-#define TEGRA210_CLK_OSC_DIV2 234 +-#define TEGRA210_CLK_OSC_DIV4 235 +-#define TEGRA210_CLK_PLL_REF 236 +-#define TEGRA210_CLK_PLL_C 237 +-#define TEGRA210_CLK_PLL_C_OUT1 238 +-#define TEGRA210_CLK_PLL_C2 239 +-#define TEGRA210_CLK_PLL_C3 240 +-#define TEGRA210_CLK_PLL_M 241 +-#define TEGRA210_CLK_PLL_M_OUT1 242 +-#define TEGRA210_CLK_PLL_P 243 +-#define TEGRA210_CLK_PLL_P_OUT1 244 +-#define TEGRA210_CLK_PLL_P_OUT2 245 +-#define TEGRA210_CLK_PLL_P_OUT3 246 +-#define TEGRA210_CLK_PLL_P_OUT4 247 +-#define TEGRA210_CLK_PLL_A 248 +-#define TEGRA210_CLK_PLL_A_OUT0 249 +-#define TEGRA210_CLK_PLL_D 250 +-#define TEGRA210_CLK_PLL_D_OUT0 251 +-#define TEGRA210_CLK_PLL_D2 252 +-#define TEGRA210_CLK_PLL_D2_OUT0 253 +-#define TEGRA210_CLK_PLL_U 254 +-#define TEGRA210_CLK_PLL_U_480M 255 +- +-#define TEGRA210_CLK_PLL_U_60M 256 +-#define TEGRA210_CLK_PLL_U_48M 257 +-/* 258 */ +-#define TEGRA210_CLK_PLL_X 259 +-#define TEGRA210_CLK_PLL_X_OUT0 260 +-#define TEGRA210_CLK_PLL_RE_VCO 261 +-#define TEGRA210_CLK_PLL_RE_OUT 262 +-#define TEGRA210_CLK_PLL_E 263 +-#define TEGRA210_CLK_SPDIF_IN_SYNC 264 +-#define TEGRA210_CLK_I2S0_SYNC 265 +-#define TEGRA210_CLK_I2S1_SYNC 266 +-#define TEGRA210_CLK_I2S2_SYNC 267 +-#define TEGRA210_CLK_I2S3_SYNC 268 +-#define TEGRA210_CLK_I2S4_SYNC 269 +-#define TEGRA210_CLK_VIMCLK_SYNC 270 +-#define TEGRA210_CLK_AUDIO0 271 +-#define TEGRA210_CLK_AUDIO1 272 +-#define TEGRA210_CLK_AUDIO2 273 +-#define TEGRA210_CLK_AUDIO3 274 +-#define TEGRA210_CLK_AUDIO4 275 +-#define TEGRA210_CLK_SPDIF 276 +-/* 277 */ +-#define TEGRA210_CLK_QSPI_PM 278 +-/* 279 */ +-/* 280 */ +-#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */ +-#define TEGRA210_CLK_SOR0_OUT 281 +-#define TEGRA210_CLK_SOR1_OUT 282 +-/* 283 */ +-#define TEGRA210_CLK_XUSB_HOST_SRC 284 +-#define TEGRA210_CLK_XUSB_FALCON_SRC 285 +-#define TEGRA210_CLK_XUSB_FS_SRC 286 +-#define TEGRA210_CLK_XUSB_SS_SRC 287 +- +-#define TEGRA210_CLK_XUSB_DEV_SRC 288 +-#define TEGRA210_CLK_XUSB_DEV 289 +-#define TEGRA210_CLK_XUSB_HS_SRC 290 +-#define TEGRA210_CLK_SCLK 291 +-#define TEGRA210_CLK_HCLK 292 +-#define TEGRA210_CLK_PCLK 293 +-#define TEGRA210_CLK_CCLK_G 294 +-#define TEGRA210_CLK_CCLK_LP 295 +-#define TEGRA210_CLK_DFLL_REF 296 +-#define TEGRA210_CLK_DFLL_SOC 297 +-#define TEGRA210_CLK_VI_SENSOR2 298 +-#define TEGRA210_CLK_PLL_P_OUT5 299 +-#define TEGRA210_CLK_CML0 300 +-#define TEGRA210_CLK_CML1 301 +-#define TEGRA210_CLK_PLL_C4 302 +-#define TEGRA210_CLK_PLL_DP 303 +-#define TEGRA210_CLK_PLL_E_MUX 304 +-#define TEGRA210_CLK_PLL_MB 305 +-#define TEGRA210_CLK_PLL_A1 306 +-#define TEGRA210_CLK_PLL_D_DSI_OUT 307 +-#define TEGRA210_CLK_PLL_C4_OUT0 308 +-#define TEGRA210_CLK_PLL_C4_OUT1 309 +-#define TEGRA210_CLK_PLL_C4_OUT2 310 +-#define TEGRA210_CLK_PLL_C4_OUT3 311 +-#define TEGRA210_CLK_PLL_U_OUT 312 +-#define TEGRA210_CLK_PLL_U_OUT1 313 +-#define TEGRA210_CLK_PLL_U_OUT2 314 +-#define TEGRA210_CLK_USB2_HSIC_TRK 315 +-#define TEGRA210_CLK_PLL_P_OUT_HSIO 316 +-#define TEGRA210_CLK_PLL_P_OUT_XUSB 317 +-#define TEGRA210_CLK_XUSB_SSP_SRC 318 +-#define TEGRA210_CLK_PLL_RE_OUT1 319 +-#define TEGRA210_CLK_PLL_MB_UD 320 +-#define TEGRA210_CLK_PLL_P_UD 321 +-#define TEGRA210_CLK_ISP 322 +-#define TEGRA210_CLK_PLL_A_OUT_ADSP 323 +-#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324 +-/* 325 */ +-#define TEGRA210_CLK_OSC 326 +-#define TEGRA210_CLK_CSI_TPG 327 +-/* 328 */ +-/* 329 */ +-/* 330 */ +-/* 331 */ +-/* 332 */ +-/* 333 */ +-/* 334 */ +-/* 335 */ +-/* 336 */ +-/* 337 */ +-/* 338 */ +-/* 339 */ +-/* 340 */ +-/* 341 */ +-/* 342 */ +-/* 343 */ +-/* 344 */ +-/* 345 */ +-/* 346 */ +-/* 347 */ +-/* 348 */ +-/* 349 */ +- +-#define TEGRA210_CLK_AUDIO0_MUX 350 +-#define TEGRA210_CLK_AUDIO1_MUX 351 +-#define TEGRA210_CLK_AUDIO2_MUX 352 +-#define TEGRA210_CLK_AUDIO3_MUX 353 +-#define TEGRA210_CLK_AUDIO4_MUX 354 +-#define TEGRA210_CLK_SPDIF_MUX 355 +-/* 356 */ +-/* 357 */ +-/* 358 */ +-#define TEGRA210_CLK_DSIA_MUX 359 +-#define TEGRA210_CLK_DSIB_MUX 360 +-/* 361 */ +-#define TEGRA210_CLK_XUSB_SS_DIV2 362 +- +-#define TEGRA210_CLK_PLL_M_UD 363 +-#define TEGRA210_CLK_PLL_C_UD 364 +-#define TEGRA210_CLK_SCLK_MUX 365 +- +-#define TEGRA210_CLK_ACLK 370 +- +-#define TEGRA210_CLK_DMIC1_SYNC_CLK 388 +-#define TEGRA210_CLK_DMIC1_SYNC_CLK_MUX 389 +-#define TEGRA210_CLK_DMIC2_SYNC_CLK 390 +-#define TEGRA210_CLK_DMIC2_SYNC_CLK_MUX 391 +-#define TEGRA210_CLK_DMIC3_SYNC_CLK 392 +-#define TEGRA210_CLK_DMIC3_SYNC_CLK_MUX 393 +- +-#define TEGRA210_CLK_CLK_MAX 394 +- +-#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/tegra234-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/tegra234-clock.h +deleted file mode 100644 +index 2c82072950ee..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/tegra234-clock.h ++++ /dev/null +@@ -1,14 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */ +- +-#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H +-#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H +- +-/** @brief output of gate CLK_ENB_FUSE */ +-#define TEGRA234_CLK_FUSE 40 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ +-#define TEGRA234_CLK_SDMMC4 123 +-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ +-#define TEGRA234_CLK_UARTA 155 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/tegra30-car.h b/scripts/dtc/include-prefixes/dt-bindings/clock/tegra30-car.h +deleted file mode 100644 +index f193663e6f28..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/tegra30-car.h ++++ /dev/null +@@ -1,276 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for binding nvidia,tegra30-car. +- * +- * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB +- * registers. These IDs often match those in the CAR's RST_DEVICES registers, +- * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In +- * this case, those clocks are assigned IDs above 160 in order to highlight +- * this issue. Implementations that interpret these clock IDs as bit values +- * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to +- * explicitly handle these special cases. +- * +- * The balance of the clocks controlled by the CAR are assigned IDs of 160 and +- * above. +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H +-#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H +- +-#define TEGRA30_CLK_CPU 0 +-/* 1 */ +-/* 2 */ +-/* 3 */ +-#define TEGRA30_CLK_RTC 4 +-#define TEGRA30_CLK_TIMER 5 +-#define TEGRA30_CLK_UARTA 6 +-/* 7 (register bit affects uartb and vfir) */ +-#define TEGRA30_CLK_GPIO 8 +-#define TEGRA30_CLK_SDMMC2 9 +-/* 10 (register bit affects spdif_in and spdif_out) */ +-#define TEGRA30_CLK_I2S1 11 +-#define TEGRA30_CLK_I2C1 12 +-#define TEGRA30_CLK_NDFLASH 13 +-#define TEGRA30_CLK_SDMMC1 14 +-#define TEGRA30_CLK_SDMMC4 15 +-/* 16 */ +-#define TEGRA30_CLK_PWM 17 +-#define TEGRA30_CLK_I2S2 18 +-#define TEGRA30_CLK_EPP 19 +-/* 20 (register bit affects vi and vi_sensor) */ +-#define TEGRA30_CLK_GR2D 21 +-#define TEGRA30_CLK_USBD 22 +-#define TEGRA30_CLK_ISP 23 +-#define TEGRA30_CLK_GR3D 24 +-/* 25 */ +-#define TEGRA30_CLK_DISP2 26 +-#define TEGRA30_CLK_DISP1 27 +-#define TEGRA30_CLK_HOST1X 28 +-#define TEGRA30_CLK_VCP 29 +-#define TEGRA30_CLK_I2S0 30 +-#define TEGRA30_CLK_COP_CACHE 31 +- +-#define TEGRA30_CLK_MC 32 +-#define TEGRA30_CLK_AHBDMA 33 +-#define TEGRA30_CLK_APBDMA 34 +-/* 35 */ +-#define TEGRA30_CLK_KBC 36 +-#define TEGRA30_CLK_STATMON 37 +-#define TEGRA30_CLK_PMC 38 +-/* 39 (register bit affects fuse and fuse_burn) */ +-#define TEGRA30_CLK_KFUSE 40 +-#define TEGRA30_CLK_SBC1 41 +-#define TEGRA30_CLK_NOR 42 +-/* 43 */ +-#define TEGRA30_CLK_SBC2 44 +-/* 45 */ +-#define TEGRA30_CLK_SBC3 46 +-#define TEGRA30_CLK_I2C5 47 +-#define TEGRA30_CLK_DSIA 48 +-/* 49 (register bit affects cve and tvo) */ +-#define TEGRA30_CLK_MIPI 50 +-#define TEGRA30_CLK_HDMI 51 +-#define TEGRA30_CLK_CSI 52 +-#define TEGRA30_CLK_TVDAC 53 +-#define TEGRA30_CLK_I2C2 54 +-#define TEGRA30_CLK_UARTC 55 +-/* 56 */ +-#define TEGRA30_CLK_EMC 57 +-#define TEGRA30_CLK_USB2 58 +-#define TEGRA30_CLK_USB3 59 +-#define TEGRA30_CLK_MPE 60 +-#define TEGRA30_CLK_VDE 61 +-#define TEGRA30_CLK_BSEA 62 +-#define TEGRA30_CLK_BSEV 63 +- +-#define TEGRA30_CLK_SPEEDO 64 +-#define TEGRA30_CLK_UARTD 65 +-#define TEGRA30_CLK_UARTE 66 +-#define TEGRA30_CLK_I2C3 67 +-#define TEGRA30_CLK_SBC4 68 +-#define TEGRA30_CLK_SDMMC3 69 +-#define TEGRA30_CLK_PCIE 70 +-#define TEGRA30_CLK_OWR 71 +-#define TEGRA30_CLK_AFI 72 +-#define TEGRA30_CLK_CSITE 73 +-/* 74 */ +-#define TEGRA30_CLK_AVPUCQ 75 +-#define TEGRA30_CLK_LA 76 +-/* 77 */ +-/* 78 */ +-#define TEGRA30_CLK_DTV 79 +-#define TEGRA30_CLK_NDSPEED 80 +-#define TEGRA30_CLK_I2CSLOW 81 +-#define TEGRA30_CLK_DSIB 82 +-/* 83 */ +-#define TEGRA30_CLK_IRAMA 84 +-#define TEGRA30_CLK_IRAMB 85 +-#define TEGRA30_CLK_IRAMC 86 +-#define TEGRA30_CLK_IRAMD 87 +-#define TEGRA30_CLK_CRAM2 88 +-/* 89 */ +-#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */ +-/* 91 */ +-#define TEGRA30_CLK_CSUS 92 +-#define TEGRA30_CLK_CDEV2 93 +-#define TEGRA30_CLK_CDEV1 94 +-/* 95 */ +- +-#define TEGRA30_CLK_CPU_G 96 +-#define TEGRA30_CLK_CPU_LP 97 +-#define TEGRA30_CLK_GR3D2 98 +-#define TEGRA30_CLK_MSELECT 99 +-#define TEGRA30_CLK_TSENSOR 100 +-#define TEGRA30_CLK_I2S3 101 +-#define TEGRA30_CLK_I2S4 102 +-#define TEGRA30_CLK_I2C4 103 +-#define TEGRA30_CLK_SBC5 104 +-#define TEGRA30_CLK_SBC6 105 +-#define TEGRA30_CLK_D_AUDIO 106 +-#define TEGRA30_CLK_APBIF 107 +-#define TEGRA30_CLK_DAM0 108 +-#define TEGRA30_CLK_DAM1 109 +-#define TEGRA30_CLK_DAM2 110 +-#define TEGRA30_CLK_HDA2CODEC_2X 111 +-#define TEGRA30_CLK_ATOMICS 112 +-#define TEGRA30_CLK_AUDIO0_2X 113 +-#define TEGRA30_CLK_AUDIO1_2X 114 +-#define TEGRA30_CLK_AUDIO2_2X 115 +-#define TEGRA30_CLK_AUDIO3_2X 116 +-#define TEGRA30_CLK_AUDIO4_2X 117 +-#define TEGRA30_CLK_SPDIF_2X 118 +-#define TEGRA30_CLK_ACTMON 119 +-#define TEGRA30_CLK_EXTERN1 120 +-#define TEGRA30_CLK_EXTERN2 121 +-#define TEGRA30_CLK_EXTERN3 122 +-#define TEGRA30_CLK_SATA_OOB 123 +-#define TEGRA30_CLK_SATA 124 +-#define TEGRA30_CLK_HDA 125 +-/* 126 */ +-#define TEGRA30_CLK_SE 127 +- +-#define TEGRA30_CLK_HDA2HDMI 128 +-#define TEGRA30_CLK_SATA_COLD 129 +-/* 130 */ +-/* 131 */ +-/* 132 */ +-/* 133 */ +-/* 134 */ +-/* 135 */ +-#define TEGRA30_CLK_CEC 136 +-/* 137 */ +-/* 138 */ +-/* 139 */ +-/* 140 */ +-/* 141 */ +-/* 142 */ +-/* 143 */ +-/* 144 */ +-/* 145 */ +-/* 146 */ +-/* 147 */ +-/* 148 */ +-/* 149 */ +-/* 150 */ +-/* 151 */ +-/* 152 */ +-/* 153 */ +-/* 154 */ +-/* 155 */ +-/* 156 */ +-/* 157 */ +-/* 158 */ +-/* 159 */ +- +-#define TEGRA30_CLK_UARTB 160 +-#define TEGRA30_CLK_VFIR 161 +-#define TEGRA30_CLK_SPDIF_IN 162 +-#define TEGRA30_CLK_SPDIF_OUT 163 +-#define TEGRA30_CLK_VI 164 +-#define TEGRA30_CLK_VI_SENSOR 165 +-#define TEGRA30_CLK_FUSE 166 +-#define TEGRA30_CLK_FUSE_BURN 167 +-#define TEGRA30_CLK_CVE 168 +-#define TEGRA30_CLK_TVO 169 +-#define TEGRA30_CLK_CLK_32K 170 +-#define TEGRA30_CLK_CLK_M 171 +-#define TEGRA30_CLK_CLK_M_DIV2 172 +-#define TEGRA30_CLK_CLK_M_DIV4 173 +-#define TEGRA30_CLK_OSC_DIV2 172 +-#define TEGRA30_CLK_OSC_DIV4 173 +-#define TEGRA30_CLK_PLL_REF 174 +-#define TEGRA30_CLK_PLL_C 175 +-#define TEGRA30_CLK_PLL_C_OUT1 176 +-#define TEGRA30_CLK_PLL_M 177 +-#define TEGRA30_CLK_PLL_M_OUT1 178 +-#define TEGRA30_CLK_PLL_P 179 +-#define TEGRA30_CLK_PLL_P_OUT1 180 +-#define TEGRA30_CLK_PLL_P_OUT2 181 +-#define TEGRA30_CLK_PLL_P_OUT3 182 +-#define TEGRA30_CLK_PLL_P_OUT4 183 +-#define TEGRA30_CLK_PLL_A 184 +-#define TEGRA30_CLK_PLL_A_OUT0 185 +-#define TEGRA30_CLK_PLL_D 186 +-#define TEGRA30_CLK_PLL_D_OUT0 187 +-#define TEGRA30_CLK_PLL_D2 188 +-#define TEGRA30_CLK_PLL_D2_OUT0 189 +-#define TEGRA30_CLK_PLL_U 190 +-#define TEGRA30_CLK_PLL_X 191 +- +-#define TEGRA30_CLK_PLL_X_OUT0 192 +-#define TEGRA30_CLK_PLL_E 193 +-#define TEGRA30_CLK_SPDIF_IN_SYNC 194 +-#define TEGRA30_CLK_I2S0_SYNC 195 +-#define TEGRA30_CLK_I2S1_SYNC 196 +-#define TEGRA30_CLK_I2S2_SYNC 197 +-#define TEGRA30_CLK_I2S3_SYNC 198 +-#define TEGRA30_CLK_I2S4_SYNC 199 +-#define TEGRA30_CLK_VIMCLK_SYNC 200 +-#define TEGRA30_CLK_AUDIO0 201 +-#define TEGRA30_CLK_AUDIO1 202 +-#define TEGRA30_CLK_AUDIO2 203 +-#define TEGRA30_CLK_AUDIO3 204 +-#define TEGRA30_CLK_AUDIO4 205 +-#define TEGRA30_CLK_SPDIF 206 +-/* 207 */ +-/* 208 */ +-/* 209 */ +-#define TEGRA30_CLK_SCLK 210 +-/* 211 */ +-#define TEGRA30_CLK_CCLK_G 212 +-#define TEGRA30_CLK_CCLK_LP 213 +-#define TEGRA30_CLK_TWD 214 +-#define TEGRA30_CLK_CML0 215 +-#define TEGRA30_CLK_CML1 216 +-#define TEGRA30_CLK_HCLK 217 +-#define TEGRA30_CLK_PCLK 218 +-/* 219 */ +-#define TEGRA30_CLK_OSC 220 +-/* 221 */ +-/* 222 */ +-/* 223 */ +- +-/* 288 */ +-/* 289 */ +-/* 290 */ +-/* 291 */ +-/* 292 */ +-/* 293 */ +-/* 294 */ +-/* 295 */ +-/* 296 */ +-/* 297 */ +-/* 298 */ +-/* 299 */ +-/* 300 */ +-/* 301 */ +-/* 302 */ +-#define TEGRA30_CLK_AUDIO0_MUX 303 +-#define TEGRA30_CLK_AUDIO1_MUX 304 +-#define TEGRA30_CLK_AUDIO2_MUX 305 +-#define TEGRA30_CLK_AUDIO3_MUX 306 +-#define TEGRA30_CLK_AUDIO4_MUX 307 +-#define TEGRA30_CLK_SPDIF_MUX 308 +-#define TEGRA30_CLK_CLK_MAX 309 +- +-#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/ti-dra7-atl.h b/scripts/dtc/include-prefixes/dt-bindings/clock/ti-dra7-atl.h +deleted file mode 100644 +index 42dd4164f6f4..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/ti-dra7-atl.h ++++ /dev/null +@@ -1,40 +0,0 @@ +-/* +- * This header provides constants for DRA7 ATL (Audio Tracking Logic) +- * +- * The constants defined in this header are used in dts files +- * +- * Copyright (C) 2013 Texas Instruments, Inc. +- * +- * Peter Ujfalusi +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License version 2 as +- * published by the Free Software Foundation. +- * +- * This program is distributed "as is" WITHOUT ANY WARRANTY of any +- * kind, whether express or implied; without even the implied warranty +- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#ifndef _DT_BINDINGS_CLK_DRA7_ATL_H +-#define _DT_BINDINGS_CLK_DRA7_ATL_H +- +-#define DRA7_ATL_WS_MCASP1_FSR 0 +-#define DRA7_ATL_WS_MCASP1_FSX 1 +-#define DRA7_ATL_WS_MCASP2_FSR 2 +-#define DRA7_ATL_WS_MCASP2_FSX 3 +-#define DRA7_ATL_WS_MCASP3_FSX 4 +-#define DRA7_ATL_WS_MCASP4_FSX 5 +-#define DRA7_ATL_WS_MCASP5_FSX 6 +-#define DRA7_ATL_WS_MCASP6_FSX 7 +-#define DRA7_ATL_WS_MCASP7_FSX 8 +-#define DRA7_ATL_WS_MCASP8_FSX 9 +-#define DRA7_ATL_WS_MCASP8_AHCLKX 10 +-#define DRA7_ATL_WS_XREF_CLK3 11 +-#define DRA7_ATL_WS_XREF_CLK0 12 +-#define DRA7_ATL_WS_XREF_CLK1 13 +-#define DRA7_ATL_WS_XREF_CLK2 14 +-#define DRA7_ATL_WS_OSC1_X1 15 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/vf610-clock.h b/scripts/dtc/include-prefixes/dt-bindings/clock/vf610-clock.h +deleted file mode 100644 +index 373644e46747..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/vf610-clock.h ++++ /dev/null +@@ -1,202 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright 2013 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_VF610_H +-#define __DT_BINDINGS_CLOCK_VF610_H +- +-#define VF610_CLK_DUMMY 0 +-#define VF610_CLK_SIRC_128K 1 +-#define VF610_CLK_SIRC_32K 2 +-#define VF610_CLK_FIRC 3 +-#define VF610_CLK_SXOSC 4 +-#define VF610_CLK_FXOSC 5 +-#define VF610_CLK_FXOSC_HALF 6 +-#define VF610_CLK_SLOW_CLK_SEL 7 +-#define VF610_CLK_FASK_CLK_SEL 8 +-#define VF610_CLK_AUDIO_EXT 9 +-#define VF610_CLK_ENET_EXT 10 +-#define VF610_CLK_PLL1_SYS 11 +-#define VF610_CLK_PLL1_PFD1 12 +-#define VF610_CLK_PLL1_PFD2 13 +-#define VF610_CLK_PLL1_PFD3 14 +-#define VF610_CLK_PLL1_PFD4 15 +-#define VF610_CLK_PLL2_BUS 16 +-#define VF610_CLK_PLL2_PFD1 17 +-#define VF610_CLK_PLL2_PFD2 18 +-#define VF610_CLK_PLL2_PFD3 19 +-#define VF610_CLK_PLL2_PFD4 20 +-#define VF610_CLK_PLL3_USB_OTG 21 +-#define VF610_CLK_PLL3_PFD1 22 +-#define VF610_CLK_PLL3_PFD2 23 +-#define VF610_CLK_PLL3_PFD3 24 +-#define VF610_CLK_PLL3_PFD4 25 +-#define VF610_CLK_PLL4_AUDIO 26 +-#define VF610_CLK_PLL5_ENET 27 +-#define VF610_CLK_PLL6_VIDEO 28 +-#define VF610_CLK_PLL3_MAIN_DIV 29 +-#define VF610_CLK_PLL4_MAIN_DIV 30 +-#define VF610_CLK_PLL6_MAIN_DIV 31 +-#define VF610_CLK_PLL1_PFD_SEL 32 +-#define VF610_CLK_PLL2_PFD_SEL 33 +-#define VF610_CLK_SYS_SEL 34 +-#define VF610_CLK_DDR_SEL 35 +-#define VF610_CLK_SYS_BUS 36 +-#define VF610_CLK_PLATFORM_BUS 37 +-#define VF610_CLK_IPG_BUS 38 +-#define VF610_CLK_UART0 39 +-#define VF610_CLK_UART1 40 +-#define VF610_CLK_UART2 41 +-#define VF610_CLK_UART3 42 +-#define VF610_CLK_UART4 43 +-#define VF610_CLK_UART5 44 +-#define VF610_CLK_PIT 45 +-#define VF610_CLK_I2C0 46 +-#define VF610_CLK_I2C1 47 +-#define VF610_CLK_I2C2 48 +-#define VF610_CLK_I2C3 49 +-#define VF610_CLK_FTM0_EXT_SEL 50 +-#define VF610_CLK_FTM0_FIX_SEL 51 +-#define VF610_CLK_FTM0_EXT_FIX_EN 52 +-#define VF610_CLK_FTM1_EXT_SEL 53 +-#define VF610_CLK_FTM1_FIX_SEL 54 +-#define VF610_CLK_FTM1_EXT_FIX_EN 55 +-#define VF610_CLK_FTM2_EXT_SEL 56 +-#define VF610_CLK_FTM2_FIX_SEL 57 +-#define VF610_CLK_FTM2_EXT_FIX_EN 58 +-#define VF610_CLK_FTM3_EXT_SEL 59 +-#define VF610_CLK_FTM3_FIX_SEL 60 +-#define VF610_CLK_FTM3_EXT_FIX_EN 61 +-#define VF610_CLK_FTM0 62 +-#define VF610_CLK_FTM1 63 +-#define VF610_CLK_FTM2 64 +-#define VF610_CLK_FTM3 65 +-#define VF610_CLK_ENET_50M 66 +-#define VF610_CLK_ENET_25M 67 +-#define VF610_CLK_ENET_SEL 68 +-#define VF610_CLK_ENET 69 +-#define VF610_CLK_ENET_TS_SEL 70 +-#define VF610_CLK_ENET_TS 71 +-#define VF610_CLK_DSPI0 72 +-#define VF610_CLK_DSPI1 73 +-#define VF610_CLK_DSPI2 74 +-#define VF610_CLK_DSPI3 75 +-#define VF610_CLK_WDT 76 +-#define VF610_CLK_ESDHC0_SEL 77 +-#define VF610_CLK_ESDHC0_EN 78 +-#define VF610_CLK_ESDHC0_DIV 79 +-#define VF610_CLK_ESDHC0 80 +-#define VF610_CLK_ESDHC1_SEL 81 +-#define VF610_CLK_ESDHC1_EN 82 +-#define VF610_CLK_ESDHC1_DIV 83 +-#define VF610_CLK_ESDHC1 84 +-#define VF610_CLK_DCU0_SEL 85 +-#define VF610_CLK_DCU0_EN 86 +-#define VF610_CLK_DCU0_DIV 87 +-#define VF610_CLK_DCU0 88 +-#define VF610_CLK_DCU1_SEL 89 +-#define VF610_CLK_DCU1_EN 90 +-#define VF610_CLK_DCU1_DIV 91 +-#define VF610_CLK_DCU1 92 +-#define VF610_CLK_ESAI_SEL 93 +-#define VF610_CLK_ESAI_EN 94 +-#define VF610_CLK_ESAI_DIV 95 +-#define VF610_CLK_ESAI 96 +-#define VF610_CLK_SAI0_SEL 97 +-#define VF610_CLK_SAI0_EN 98 +-#define VF610_CLK_SAI0_DIV 99 +-#define VF610_CLK_SAI0 100 +-#define VF610_CLK_SAI1_SEL 101 +-#define VF610_CLK_SAI1_EN 102 +-#define VF610_CLK_SAI1_DIV 103 +-#define VF610_CLK_SAI1 104 +-#define VF610_CLK_SAI2_SEL 105 +-#define VF610_CLK_SAI2_EN 106 +-#define VF610_CLK_SAI2_DIV 107 +-#define VF610_CLK_SAI2 108 +-#define VF610_CLK_SAI3_SEL 109 +-#define VF610_CLK_SAI3_EN 110 +-#define VF610_CLK_SAI3_DIV 111 +-#define VF610_CLK_SAI3 112 +-#define VF610_CLK_USBC0 113 +-#define VF610_CLK_USBC1 114 +-#define VF610_CLK_QSPI0_SEL 115 +-#define VF610_CLK_QSPI0_EN 116 +-#define VF610_CLK_QSPI0_X4_DIV 117 +-#define VF610_CLK_QSPI0_X2_DIV 118 +-#define VF610_CLK_QSPI0_X1_DIV 119 +-#define VF610_CLK_QSPI1_SEL 120 +-#define VF610_CLK_QSPI1_EN 121 +-#define VF610_CLK_QSPI1_X4_DIV 122 +-#define VF610_CLK_QSPI1_X2_DIV 123 +-#define VF610_CLK_QSPI1_X1_DIV 124 +-#define VF610_CLK_QSPI0 125 +-#define VF610_CLK_QSPI1 126 +-#define VF610_CLK_NFC_SEL 127 +-#define VF610_CLK_NFC_EN 128 +-#define VF610_CLK_NFC_PRE_DIV 129 +-#define VF610_CLK_NFC_FRAC_DIV 130 +-#define VF610_CLK_NFC_INV 131 +-#define VF610_CLK_NFC 132 +-#define VF610_CLK_VADC_SEL 133 +-#define VF610_CLK_VADC_EN 134 +-#define VF610_CLK_VADC_DIV 135 +-#define VF610_CLK_VADC_DIV_HALF 136 +-#define VF610_CLK_VADC 137 +-#define VF610_CLK_ADC0 138 +-#define VF610_CLK_ADC1 139 +-#define VF610_CLK_DAC0 140 +-#define VF610_CLK_DAC1 141 +-#define VF610_CLK_FLEXCAN0 142 +-#define VF610_CLK_FLEXCAN1 143 +-#define VF610_CLK_ASRC 144 +-#define VF610_CLK_GPU_SEL 145 +-#define VF610_CLK_GPU_EN 146 +-#define VF610_CLK_GPU2D 147 +-#define VF610_CLK_ENET0 148 +-#define VF610_CLK_ENET1 149 +-#define VF610_CLK_DMAMUX0 150 +-#define VF610_CLK_DMAMUX1 151 +-#define VF610_CLK_DMAMUX2 152 +-#define VF610_CLK_DMAMUX3 153 +-#define VF610_CLK_FLEXCAN0_EN 154 +-#define VF610_CLK_FLEXCAN1_EN 155 +-#define VF610_CLK_PLL7_USB_HOST 156 +-#define VF610_CLK_USBPHY0 157 +-#define VF610_CLK_USBPHY1 158 +-#define VF610_CLK_LVDS1_IN 159 +-#define VF610_CLK_ANACLK1 160 +-#define VF610_CLK_PLL1_BYPASS_SRC 161 +-#define VF610_CLK_PLL2_BYPASS_SRC 162 +-#define VF610_CLK_PLL3_BYPASS_SRC 163 +-#define VF610_CLK_PLL4_BYPASS_SRC 164 +-#define VF610_CLK_PLL5_BYPASS_SRC 165 +-#define VF610_CLK_PLL6_BYPASS_SRC 166 +-#define VF610_CLK_PLL7_BYPASS_SRC 167 +-#define VF610_CLK_PLL1 168 +-#define VF610_CLK_PLL2 169 +-#define VF610_CLK_PLL3 170 +-#define VF610_CLK_PLL4 171 +-#define VF610_CLK_PLL5 172 +-#define VF610_CLK_PLL6 173 +-#define VF610_CLK_PLL7 174 +-#define VF610_PLL1_BYPASS 175 +-#define VF610_PLL2_BYPASS 176 +-#define VF610_PLL3_BYPASS 177 +-#define VF610_PLL4_BYPASS 178 +-#define VF610_PLL5_BYPASS 179 +-#define VF610_PLL6_BYPASS 180 +-#define VF610_PLL7_BYPASS 181 +-#define VF610_CLK_SNVS 182 +-#define VF610_CLK_DAP 183 +-#define VF610_CLK_OCOTP 184 +-#define VF610_CLK_DDRMC 185 +-#define VF610_CLK_WKPU 186 +-#define VF610_CLK_TCON0 187 +-#define VF610_CLK_TCON1 188 +-#define VF610_CLK_CAAM 189 +-#define VF610_CLK_CRC 190 +-#define VF610_CLK_END 191 +- +-#endif /* __DT_BINDINGS_CLOCK_VF610_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/x1000-cgu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/x1000-cgu.h +deleted file mode 100644 +index f187e0719fd3..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/x1000-cgu.h ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides clock numbers for the ingenic,x1000-cgu DT binding. +- * +- * They are roughly ordered as: +- * - external clocks +- * - PLLs +- * - muxes/dividers in the order they appear in the x1000 programmers manual +- * - gates in order of their bit in the CLKGR* registers +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__ +-#define __DT_BINDINGS_CLOCK_X1000_CGU_H__ +- +-#define X1000_CLK_EXCLK 0 +-#define X1000_CLK_RTCLK 1 +-#define X1000_CLK_APLL 2 +-#define X1000_CLK_MPLL 3 +-#define X1000_CLK_OTGPHY 4 +-#define X1000_CLK_SCLKA 5 +-#define X1000_CLK_CPUMUX 6 +-#define X1000_CLK_CPU 7 +-#define X1000_CLK_L2CACHE 8 +-#define X1000_CLK_AHB0 9 +-#define X1000_CLK_AHB2PMUX 10 +-#define X1000_CLK_AHB2 11 +-#define X1000_CLK_PCLK 12 +-#define X1000_CLK_DDR 13 +-#define X1000_CLK_MAC 14 +-#define X1000_CLK_LCD 15 +-#define X1000_CLK_MSCMUX 16 +-#define X1000_CLK_MSC0 17 +-#define X1000_CLK_MSC1 18 +-#define X1000_CLK_OTG 19 +-#define X1000_CLK_SSIPLL 20 +-#define X1000_CLK_SSIPLL_DIV2 21 +-#define X1000_CLK_SSIMUX 22 +-#define X1000_CLK_EMC 23 +-#define X1000_CLK_EFUSE 24 +-#define X1000_CLK_SFC 25 +-#define X1000_CLK_I2C0 26 +-#define X1000_CLK_I2C1 27 +-#define X1000_CLK_I2C2 28 +-#define X1000_CLK_UART0 29 +-#define X1000_CLK_UART1 30 +-#define X1000_CLK_UART2 31 +-#define X1000_CLK_TCU 32 +-#define X1000_CLK_SSI 33 +-#define X1000_CLK_OST 34 +-#define X1000_CLK_PDMA 35 +-#define X1000_CLK_EXCLK_DIV512 36 +-#define X1000_CLK_RTC 37 +- +-#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/x1830-cgu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/x1830-cgu.h +deleted file mode 100644 +index 88455376a950..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/x1830-cgu.h ++++ /dev/null +@@ -1,57 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides clock numbers for the ingenic,x1830-cgu DT binding. +- * +- * They are roughly ordered as: +- * - external clocks +- * - PLLs +- * - muxes/dividers in the order they appear in the x1830 programmers manual +- * - gates in order of their bit in the CLKGR* registers +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__ +-#define __DT_BINDINGS_CLOCK_X1830_CGU_H__ +- +-#define X1830_CLK_EXCLK 0 +-#define X1830_CLK_RTCLK 1 +-#define X1830_CLK_APLL 2 +-#define X1830_CLK_MPLL 3 +-#define X1830_CLK_EPLL 4 +-#define X1830_CLK_VPLL 5 +-#define X1830_CLK_OTGPHY 6 +-#define X1830_CLK_SCLKA 7 +-#define X1830_CLK_CPUMUX 8 +-#define X1830_CLK_CPU 9 +-#define X1830_CLK_L2CACHE 10 +-#define X1830_CLK_AHB0 11 +-#define X1830_CLK_AHB2PMUX 12 +-#define X1830_CLK_AHB2 13 +-#define X1830_CLK_PCLK 14 +-#define X1830_CLK_DDR 15 +-#define X1830_CLK_MAC 16 +-#define X1830_CLK_LCD 17 +-#define X1830_CLK_MSCMUX 18 +-#define X1830_CLK_MSC0 19 +-#define X1830_CLK_MSC1 20 +-#define X1830_CLK_SSIPLL 21 +-#define X1830_CLK_SSIPLL_DIV2 22 +-#define X1830_CLK_SSIMUX 23 +-#define X1830_CLK_EMC 24 +-#define X1830_CLK_EFUSE 25 +-#define X1830_CLK_OTG 26 +-#define X1830_CLK_SSI0 27 +-#define X1830_CLK_SMB0 28 +-#define X1830_CLK_SMB1 29 +-#define X1830_CLK_SMB2 30 +-#define X1830_CLK_UART0 31 +-#define X1830_CLK_UART1 32 +-#define X1830_CLK_SSI1 33 +-#define X1830_CLK_SFC 34 +-#define X1830_CLK_PDMA 35 +-#define X1830_CLK_TCU 36 +-#define X1830_CLK_DTRNG 37 +-#define X1830_CLK_OST 38 +-#define X1830_CLK_EXCLK_DIV512 39 +-#define X1830_CLK_RTC 40 +- +-#endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/xlnx-vcu.h b/scripts/dtc/include-prefixes/dt-bindings/clock/xlnx-vcu.h +deleted file mode 100644 +index 1ed76b9563b6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/xlnx-vcu.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2020 Pengutronix, Michael Tretter +- */ +- +-#ifndef _DT_BINDINGS_CLOCK_XLNX_VCU_H +-#define _DT_BINDINGS_CLOCK_XLNX_VCU_H +- +-#define CLK_XVCU_ENC_CORE 0 +-#define CLK_XVCU_ENC_MCU 1 +-#define CLK_XVCU_DEC_CORE 2 +-#define CLK_XVCU_DEC_MCU 3 +-#define CLK_XVCU_NUM_CLOCKS 4 +- +-#endif /* _DT_BINDINGS_CLOCK_XLNX_VCU_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/xlnx-versal-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/xlnx-versal-clk.h +deleted file mode 100644 +index 264d634d226e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/xlnx-versal-clk.h ++++ /dev/null +@@ -1,123 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2019 Xilinx Inc. +- * +- */ +- +-#ifndef _DT_BINDINGS_CLK_VERSAL_H +-#define _DT_BINDINGS_CLK_VERSAL_H +- +-#define PMC_PLL 1 +-#define APU_PLL 2 +-#define RPU_PLL 3 +-#define CPM_PLL 4 +-#define NOC_PLL 5 +-#define PLL_MAX 6 +-#define PMC_PRESRC 7 +-#define PMC_POSTCLK 8 +-#define PMC_PLL_OUT 9 +-#define PPLL 10 +-#define NOC_PRESRC 11 +-#define NOC_POSTCLK 12 +-#define NOC_PLL_OUT 13 +-#define NPLL 14 +-#define APU_PRESRC 15 +-#define APU_POSTCLK 16 +-#define APU_PLL_OUT 17 +-#define APLL 18 +-#define RPU_PRESRC 19 +-#define RPU_POSTCLK 20 +-#define RPU_PLL_OUT 21 +-#define RPLL 22 +-#define CPM_PRESRC 23 +-#define CPM_POSTCLK 24 +-#define CPM_PLL_OUT 25 +-#define CPLL 26 +-#define PPLL_TO_XPD 27 +-#define NPLL_TO_XPD 28 +-#define APLL_TO_XPD 29 +-#define RPLL_TO_XPD 30 +-#define EFUSE_REF 31 +-#define SYSMON_REF 32 +-#define IRO_SUSPEND_REF 33 +-#define USB_SUSPEND 34 +-#define SWITCH_TIMEOUT 35 +-#define RCLK_PMC 36 +-#define RCLK_LPD 37 +-#define WDT 38 +-#define TTC0 39 +-#define TTC1 40 +-#define TTC2 41 +-#define TTC3 42 +-#define GEM_TSU 43 +-#define GEM_TSU_LB 44 +-#define MUXED_IRO_DIV2 45 +-#define MUXED_IRO_DIV4 46 +-#define PSM_REF 47 +-#define GEM0_RX 48 +-#define GEM0_TX 49 +-#define GEM1_RX 50 +-#define GEM1_TX 51 +-#define CPM_CORE_REF 52 +-#define CPM_LSBUS_REF 53 +-#define CPM_DBG_REF 54 +-#define CPM_AUX0_REF 55 +-#define CPM_AUX1_REF 56 +-#define QSPI_REF 57 +-#define OSPI_REF 58 +-#define SDIO0_REF 59 +-#define SDIO1_REF 60 +-#define PMC_LSBUS_REF 61 +-#define I2C_REF 62 +-#define TEST_PATTERN_REF 63 +-#define DFT_OSC_REF 64 +-#define PMC_PL0_REF 65 +-#define PMC_PL1_REF 66 +-#define PMC_PL2_REF 67 +-#define PMC_PL3_REF 68 +-#define CFU_REF 69 +-#define SPARE_REF 70 +-#define NPI_REF 71 +-#define HSM0_REF 72 +-#define HSM1_REF 73 +-#define SD_DLL_REF 74 +-#define FPD_TOP_SWITCH 75 +-#define FPD_LSBUS 76 +-#define ACPU 77 +-#define DBG_TRACE 78 +-#define DBG_FPD 79 +-#define LPD_TOP_SWITCH 80 +-#define ADMA 81 +-#define LPD_LSBUS 82 +-#define CPU_R5 83 +-#define CPU_R5_CORE 84 +-#define CPU_R5_OCM 85 +-#define CPU_R5_OCM2 86 +-#define IOU_SWITCH 87 +-#define GEM0_REF 88 +-#define GEM1_REF 89 +-#define GEM_TSU_REF 90 +-#define USB0_BUS_REF 91 +-#define UART0_REF 92 +-#define UART1_REF 93 +-#define SPI0_REF 94 +-#define SPI1_REF 95 +-#define CAN0_REF 96 +-#define CAN1_REF 97 +-#define I2C0_REF 98 +-#define I2C1_REF 99 +-#define DBG_LPD 100 +-#define TIMESTAMP_REF 101 +-#define DBG_TSTMP 102 +-#define CPM_TOPSW_REF 103 +-#define USB3_DUAL_REF 104 +-#define OUTCLK_MAX 105 +-#define REF_CLK 106 +-#define PL_ALT_REF_CLK 107 +-#define MUXED_IRO 108 +-#define PL_EXT 109 +-#define PL_LB 110 +-#define MIO_50_OR_51 111 +-#define MIO_24_OR_25 112 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/clock/xlnx-zynqmp-clk.h b/scripts/dtc/include-prefixes/dt-bindings/clock/xlnx-zynqmp-clk.h +deleted file mode 100644 +index cdc4c0b9a374..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/clock/xlnx-zynqmp-clk.h ++++ /dev/null +@@ -1,126 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Xilinx Zynq MPSoC Firmware layer +- * +- * Copyright (C) 2014-2018 Xilinx, Inc. +- * +- */ +- +-#ifndef _DT_BINDINGS_CLK_ZYNQMP_H +-#define _DT_BINDINGS_CLK_ZYNQMP_H +- +-#define IOPLL 0 +-#define RPLL 1 +-#define APLL 2 +-#define DPLL 3 +-#define VPLL 4 +-#define IOPLL_TO_FPD 5 +-#define RPLL_TO_FPD 6 +-#define APLL_TO_LPD 7 +-#define DPLL_TO_LPD 8 +-#define VPLL_TO_LPD 9 +-#define ACPU 10 +-#define ACPU_HALF 11 +-#define DBF_FPD 12 +-#define DBF_LPD 13 +-#define DBG_TRACE 14 +-#define DBG_TSTMP 15 +-#define DP_VIDEO_REF 16 +-#define DP_AUDIO_REF 17 +-#define DP_STC_REF 18 +-#define GDMA_REF 19 +-#define DPDMA_REF 20 +-#define DDR_REF 21 +-#define SATA_REF 22 +-#define PCIE_REF 23 +-#define GPU_REF 24 +-#define GPU_PP0_REF 25 +-#define GPU_PP1_REF 26 +-#define TOPSW_MAIN 27 +-#define TOPSW_LSBUS 28 +-#define GTGREF0_REF 29 +-#define LPD_SWITCH 30 +-#define LPD_LSBUS 31 +-#define USB0_BUS_REF 32 +-#define USB1_BUS_REF 33 +-#define USB3_DUAL_REF 34 +-#define USB0 35 +-#define USB1 36 +-#define CPU_R5 37 +-#define CPU_R5_CORE 38 +-#define CSU_SPB 39 +-#define CSU_PLL 40 +-#define PCAP 41 +-#define IOU_SWITCH 42 +-#define GEM_TSU_REF 43 +-#define GEM_TSU 44 +-#define GEM0_TX 45 +-#define GEM1_TX 46 +-#define GEM2_TX 47 +-#define GEM3_TX 48 +-#define GEM0_RX 49 +-#define GEM1_RX 50 +-#define GEM2_RX 51 +-#define GEM3_RX 52 +-#define QSPI_REF 53 +-#define SDIO0_REF 54 +-#define SDIO1_REF 55 +-#define UART0_REF 56 +-#define UART1_REF 57 +-#define SPI0_REF 58 +-#define SPI1_REF 59 +-#define NAND_REF 60 +-#define I2C0_REF 61 +-#define I2C1_REF 62 +-#define CAN0_REF 63 +-#define CAN1_REF 64 +-#define CAN0 65 +-#define CAN1 66 +-#define DLL_REF 67 +-#define ADMA_REF 68 +-#define TIMESTAMP_REF 69 +-#define AMS_REF 70 +-#define PL0_REF 71 +-#define PL1_REF 72 +-#define PL2_REF 73 +-#define PL3_REF 74 +-#define WDT 75 +-#define IOPLL_INT 76 +-#define IOPLL_PRE_SRC 77 +-#define IOPLL_HALF 78 +-#define IOPLL_INT_MUX 79 +-#define IOPLL_POST_SRC 80 +-#define RPLL_INT 81 +-#define RPLL_PRE_SRC 82 +-#define RPLL_HALF 83 +-#define RPLL_INT_MUX 84 +-#define RPLL_POST_SRC 85 +-#define APLL_INT 86 +-#define APLL_PRE_SRC 87 +-#define APLL_HALF 88 +-#define APLL_INT_MUX 89 +-#define APLL_POST_SRC 90 +-#define DPLL_INT 91 +-#define DPLL_PRE_SRC 92 +-#define DPLL_HALF 93 +-#define DPLL_INT_MUX 94 +-#define DPLL_POST_SRC 95 +-#define VPLL_INT 96 +-#define VPLL_PRE_SRC 97 +-#define VPLL_HALF 98 +-#define VPLL_INT_MUX 99 +-#define VPLL_POST_SRC 100 +-#define CAN0_MIO 101 +-#define CAN1_MIO 102 +-#define ACPU_FULL 103 +-#define GEM0_REF 104 +-#define GEM1_REF 105 +-#define GEM2_REF 106 +-#define GEM3_REF 107 +-#define GEM0_REF_UNG 108 +-#define GEM1_REF_UNG 109 +-#define GEM2_REF_UNG 110 +-#define GEM3_REF_UNG 111 +-#define LPD_WDT 112 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/display/sdtv-standards.h b/scripts/dtc/include-prefixes/dt-bindings/display/sdtv-standards.h +deleted file mode 100644 +index fbc1a3db2ea7..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/display/sdtv-standards.h ++++ /dev/null +@@ -1,76 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only or X11 */ +-/* +- * Copyright 2019 Pengutronix, Marco Felsch +- */ +- +-#ifndef _DT_BINDINGS_DISPLAY_SDTV_STDS_H +-#define _DT_BINDINGS_DISPLAY_SDTV_STDS_H +- +-/* +- * Attention: Keep the SDTV_STD_* bit definitions in sync with +- * include/uapi/linux/videodev2.h V4L2_STD_* bit definitions. +- */ +-/* One bit for each standard */ +-#define SDTV_STD_PAL_B 0x00000001 +-#define SDTV_STD_PAL_B1 0x00000002 +-#define SDTV_STD_PAL_G 0x00000004 +-#define SDTV_STD_PAL_H 0x00000008 +-#define SDTV_STD_PAL_I 0x00000010 +-#define SDTV_STD_PAL_D 0x00000020 +-#define SDTV_STD_PAL_D1 0x00000040 +-#define SDTV_STD_PAL_K 0x00000080 +- +-#define SDTV_STD_PAL (SDTV_STD_PAL_B | \ +- SDTV_STD_PAL_B1 | \ +- SDTV_STD_PAL_G | \ +- SDTV_STD_PAL_H | \ +- SDTV_STD_PAL_I | \ +- SDTV_STD_PAL_D | \ +- SDTV_STD_PAL_D1 | \ +- SDTV_STD_PAL_K) +- +-#define SDTV_STD_PAL_M 0x00000100 +-#define SDTV_STD_PAL_N 0x00000200 +-#define SDTV_STD_PAL_Nc 0x00000400 +-#define SDTV_STD_PAL_60 0x00000800 +- +-#define SDTV_STD_NTSC_M 0x00001000 /* BTSC */ +-#define SDTV_STD_NTSC_M_JP 0x00002000 /* EIA-J */ +-#define SDTV_STD_NTSC_443 0x00004000 +-#define SDTV_STD_NTSC_M_KR 0x00008000 /* FM A2 */ +- +-#define SDTV_STD_NTSC (SDTV_STD_NTSC_M | \ +- SDTV_STD_NTSC_M_JP | \ +- SDTV_STD_NTSC_M_KR) +- +-#define SDTV_STD_SECAM_B 0x00010000 +-#define SDTV_STD_SECAM_D 0x00020000 +-#define SDTV_STD_SECAM_G 0x00040000 +-#define SDTV_STD_SECAM_H 0x00080000 +-#define SDTV_STD_SECAM_K 0x00100000 +-#define SDTV_STD_SECAM_K1 0x00200000 +-#define SDTV_STD_SECAM_L 0x00400000 +-#define SDTV_STD_SECAM_LC 0x00800000 +- +-#define SDTV_STD_SECAM (SDTV_STD_SECAM_B | \ +- SDTV_STD_SECAM_D | \ +- SDTV_STD_SECAM_G | \ +- SDTV_STD_SECAM_H | \ +- SDTV_STD_SECAM_K | \ +- SDTV_STD_SECAM_K1 | \ +- SDTV_STD_SECAM_L | \ +- SDTV_STD_SECAM_LC) +- +-/* Standards for Countries with 60Hz Line frequency */ +-#define SDTV_STD_525_60 (SDTV_STD_PAL_M | \ +- SDTV_STD_PAL_60 | \ +- SDTV_STD_NTSC | \ +- SDTV_STD_NTSC_443) +- +-/* Standards for Countries with 50Hz Line frequency */ +-#define SDTV_STD_625_50 (SDTV_STD_PAL | \ +- SDTV_STD_PAL_N | \ +- SDTV_STD_PAL_Nc | \ +- SDTV_STD_SECAM) +- +-#endif /* _DT_BINDINGS_DISPLAY_SDTV_STDS_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/display/tda998x.h b/scripts/dtc/include-prefixes/dt-bindings/display/tda998x.h +deleted file mode 100644 +index 746831ff396c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/display/tda998x.h ++++ /dev/null +@@ -1,8 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef _DT_BINDINGS_TDA998X_H +-#define _DT_BINDINGS_TDA998X_H +- +-#define TDA998x_SPDIF 1 +-#define TDA998x_I2S 2 +- +-#endif /*_DT_BINDINGS_TDA998X_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/dma/at91.h b/scripts/dtc/include-prefixes/dt-bindings/dma/at91.h +deleted file mode 100644 +index e7b3e06554ce..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/dma/at91.h ++++ /dev/null +@@ -1,51 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * This header provides macros for at91 dma bindings. +- * +- * Copyright (C) 2013 Ludovic Desroches +- */ +- +-#ifndef __DT_BINDINGS_AT91_DMA_H__ +-#define __DT_BINDINGS_AT91_DMA_H__ +- +-/* ---------- HDMAC ---------- */ +- +-/* +- * Source and/or destination peripheral ID +- */ +-#define AT91_DMA_CFG_PER_ID_MASK (0xff) +-#define AT91_DMA_CFG_PER_ID(id) (id & AT91_DMA_CFG_PER_ID_MASK) +- +-/* +- * FIFO configuration: it defines when a request is serviced. +- */ +-#define AT91_DMA_CFG_FIFOCFG_OFFSET (8) +-#define AT91_DMA_CFG_FIFOCFG_MASK (0xf << AT91_DMA_CFG_FIFOCFG_OFFSET) +-#define AT91_DMA_CFG_FIFOCFG_HALF (0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* half FIFO (default behavior) */ +-#define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */ +-#define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */ +- +- +-/* ---------- XDMAC ---------- */ +-#define AT91_XDMAC_DT_MEM_IF_MASK (0x1) +-#define AT91_XDMAC_DT_MEM_IF_OFFSET (13) +-#define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \ +- << AT91_XDMAC_DT_MEM_IF_OFFSET) +-#define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \ +- & AT91_XDMAC_DT_MEM_IF_MASK) +- +-#define AT91_XDMAC_DT_PER_IF_MASK (0x1) +-#define AT91_XDMAC_DT_PER_IF_OFFSET (14) +-#define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \ +- << AT91_XDMAC_DT_PER_IF_OFFSET) +-#define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \ +- & AT91_XDMAC_DT_PER_IF_MASK) +- +-#define AT91_XDMAC_DT_PERID_MASK (0x7f) +-#define AT91_XDMAC_DT_PERID_OFFSET (24) +-#define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \ +- << AT91_XDMAC_DT_PERID_OFFSET) +-#define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \ +- & AT91_XDMAC_DT_PERID_MASK) +- +-#endif /* __DT_BINDINGS_AT91_DMA_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/dma/axi-dmac.h b/scripts/dtc/include-prefixes/dt-bindings/dma/axi-dmac.h +deleted file mode 100644 +index ad9e6ecb9c2f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/dma/axi-dmac.h ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef __DT_BINDINGS_DMA_AXI_DMAC_H__ +-#define __DT_BINDINGS_DMA_AXI_DMAC_H__ +- +-#define AXI_DMAC_BUS_TYPE_AXI_MM 0 +-#define AXI_DMAC_BUS_TYPE_AXI_STREAM 1 +-#define AXI_DMAC_BUS_TYPE_FIFO 2 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/dma/dw-dmac.h b/scripts/dtc/include-prefixes/dt-bindings/dma/dw-dmac.h +deleted file mode 100644 +index d1ca705c95b3..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/dma/dw-dmac.h ++++ /dev/null +@@ -1,14 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +- +-#ifndef __DT_BINDINGS_DMA_DW_DMAC_H__ +-#define __DT_BINDINGS_DMA_DW_DMAC_H__ +- +-/* +- * Protection Control bits provide protection against illegal transactions. +- * The protection bits[0:2] are one-to-one mapped to AHB HPROT[3:1] signals. +- */ +-#define DW_DMAC_HPROT1_PRIVILEGED_MODE (1 << 0) /* Privileged Mode */ +-#define DW_DMAC_HPROT2_BUFFERABLE (1 << 1) /* DMA is bufferable */ +-#define DW_DMAC_HPROT3_CACHEABLE (1 << 2) /* DMA is cacheable */ +- +-#endif /* __DT_BINDINGS_DMA_DW_DMAC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/dma/jz4775-dma.h b/scripts/dtc/include-prefixes/dt-bindings/dma/jz4775-dma.h +deleted file mode 100644 +index 8d27e2c69dca..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/dma/jz4775-dma.h ++++ /dev/null +@@ -1,44 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * This header provides macros for JZ4775 DMA bindings. +- * +- * Copyright (c) 2020 周琰杰 (Zhou Yanjie) +- */ +- +-#ifndef __DT_BINDINGS_DMA_JZ4775_DMA_H__ +-#define __DT_BINDINGS_DMA_JZ4775_DMA_H__ +- +-/* +- * Request type numbers for the JZ4775 DMA controller (written to the DRTn +- * register for the channel). +- */ +-#define JZ4775_DMA_I2S0_TX 0x6 +-#define JZ4775_DMA_I2S0_RX 0x7 +-#define JZ4775_DMA_AUTO 0x8 +-#define JZ4775_DMA_SADC_RX 0x9 +-#define JZ4775_DMA_UART3_TX 0x0e +-#define JZ4775_DMA_UART3_RX 0x0f +-#define JZ4775_DMA_UART2_TX 0x10 +-#define JZ4775_DMA_UART2_RX 0x11 +-#define JZ4775_DMA_UART1_TX 0x12 +-#define JZ4775_DMA_UART1_RX 0x13 +-#define JZ4775_DMA_UART0_TX 0x14 +-#define JZ4775_DMA_UART0_RX 0x15 +-#define JZ4775_DMA_SSI0_TX 0x16 +-#define JZ4775_DMA_SSI0_RX 0x17 +-#define JZ4775_DMA_MSC0_TX 0x1a +-#define JZ4775_DMA_MSC0_RX 0x1b +-#define JZ4775_DMA_MSC1_TX 0x1c +-#define JZ4775_DMA_MSC1_RX 0x1d +-#define JZ4775_DMA_MSC2_TX 0x1e +-#define JZ4775_DMA_MSC2_RX 0x1f +-#define JZ4775_DMA_PCM0_TX 0x20 +-#define JZ4775_DMA_PCM0_RX 0x21 +-#define JZ4775_DMA_SMB0_TX 0x24 +-#define JZ4775_DMA_SMB0_RX 0x25 +-#define JZ4775_DMA_SMB1_TX 0x26 +-#define JZ4775_DMA_SMB1_RX 0x27 +-#define JZ4775_DMA_SMB2_TX 0x28 +-#define JZ4775_DMA_SMB2_RX 0x29 +- +-#endif /* __DT_BINDINGS_DMA_JZ4775_DMA_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/dma/jz4780-dma.h b/scripts/dtc/include-prefixes/dt-bindings/dma/jz4780-dma.h +deleted file mode 100644 +index df017fdfb44e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/dma/jz4780-dma.h ++++ /dev/null +@@ -1,49 +0,0 @@ +-#ifndef __DT_BINDINGS_DMA_JZ4780_DMA_H__ +-#define __DT_BINDINGS_DMA_JZ4780_DMA_H__ +- +-/* +- * Request type numbers for the JZ4780 DMA controller (written to the DRTn +- * register for the channel). +- */ +-#define JZ4780_DMA_I2S1_TX 0x4 +-#define JZ4780_DMA_I2S1_RX 0x5 +-#define JZ4780_DMA_I2S0_TX 0x6 +-#define JZ4780_DMA_I2S0_RX 0x7 +-#define JZ4780_DMA_AUTO 0x8 +-#define JZ4780_DMA_SADC_RX 0x9 +-#define JZ4780_DMA_UART4_TX 0xc +-#define JZ4780_DMA_UART4_RX 0xd +-#define JZ4780_DMA_UART3_TX 0xe +-#define JZ4780_DMA_UART3_RX 0xf +-#define JZ4780_DMA_UART2_TX 0x10 +-#define JZ4780_DMA_UART2_RX 0x11 +-#define JZ4780_DMA_UART1_TX 0x12 +-#define JZ4780_DMA_UART1_RX 0x13 +-#define JZ4780_DMA_UART0_TX 0x14 +-#define JZ4780_DMA_UART0_RX 0x15 +-#define JZ4780_DMA_SSI0_TX 0x16 +-#define JZ4780_DMA_SSI0_RX 0x17 +-#define JZ4780_DMA_SSI1_TX 0x18 +-#define JZ4780_DMA_SSI1_RX 0x19 +-#define JZ4780_DMA_MSC0_TX 0x1a +-#define JZ4780_DMA_MSC0_RX 0x1b +-#define JZ4780_DMA_MSC1_TX 0x1c +-#define JZ4780_DMA_MSC1_RX 0x1d +-#define JZ4780_DMA_MSC2_TX 0x1e +-#define JZ4780_DMA_MSC2_RX 0x1f +-#define JZ4780_DMA_PCM0_TX 0x20 +-#define JZ4780_DMA_PCM0_RX 0x21 +-#define JZ4780_DMA_SMB0_TX 0x24 +-#define JZ4780_DMA_SMB0_RX 0x25 +-#define JZ4780_DMA_SMB1_TX 0x26 +-#define JZ4780_DMA_SMB1_RX 0x27 +-#define JZ4780_DMA_SMB2_TX 0x28 +-#define JZ4780_DMA_SMB2_RX 0x29 +-#define JZ4780_DMA_SMB3_TX 0x2a +-#define JZ4780_DMA_SMB3_RX 0x2b +-#define JZ4780_DMA_SMB4_TX 0x2c +-#define JZ4780_DMA_SMB4_RX 0x2d +-#define JZ4780_DMA_DES_TX 0x2e +-#define JZ4780_DMA_DES_RX 0x2f +- +-#endif /* __DT_BINDINGS_DMA_JZ4780_DMA_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/dma/nbpfaxi.h b/scripts/dtc/include-prefixes/dt-bindings/dma/nbpfaxi.h +deleted file mode 100644 +index 88e59acc0678..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/dma/nbpfaxi.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2013-2014 Renesas Electronics Europe Ltd. +- * Author: Guennadi Liakhovetski +- */ +- +-#ifndef DT_BINDINGS_NBPFAXI_H +-#define DT_BINDINGS_NBPFAXI_H +- +-/** +- * Use "#dma-cells = <2>;" with the second integer defining slave DMA flags: +- */ +-#define NBPF_SLAVE_RQ_HIGH 1 +-#define NBPF_SLAVE_RQ_LOW 2 +-#define NBPF_SLAVE_RQ_LEVEL 4 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/dma/qcom-gpi.h b/scripts/dtc/include-prefixes/dt-bindings/dma/qcom-gpi.h +deleted file mode 100644 +index ebda2a37f52a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/dma/qcom-gpi.h ++++ /dev/null +@@ -1,11 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +-/* Copyright (c) 2020, Linaro Ltd. */ +- +-#ifndef __DT_BINDINGS_DMA_QCOM_GPI_H__ +-#define __DT_BINDINGS_DMA_QCOM_GPI_H__ +- +-#define QCOM_GPI_SPI 1 +-#define QCOM_GPI_UART 2 +-#define QCOM_GPI_I2C 3 +- +-#endif /* __DT_BINDINGS_DMA_QCOM_GPI_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/dma/sun4i-a10.h b/scripts/dtc/include-prefixes/dt-bindings/dma/sun4i-a10.h +deleted file mode 100644 +index 8caba9ef7e9d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/dma/sun4i-a10.h ++++ /dev/null +@@ -1,56 +0,0 @@ +-/* +- * Copyright 2014 Maxime Ripard +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef __DT_BINDINGS_DMA_SUN4I_A10_H_ +-#define __DT_BINDINGS_DMA_SUN4I_A10_H_ +- +-#define SUN4I_DMA_NORMAL 0 +-#define SUN4I_DMA_DEDICATED 1 +- +-#endif /* __DT_BINDINGS_DMA_SUN4I_A10_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/dma/x1000-dma.h b/scripts/dtc/include-prefixes/dt-bindings/dma/x1000-dma.h +deleted file mode 100644 +index 401e1656e696..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/dma/x1000-dma.h ++++ /dev/null +@@ -1,40 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * This header provides macros for X1000 DMA bindings. +- * +- * Copyright (c) 2019 Zhou Yanjie +- */ +- +-#ifndef __DT_BINDINGS_DMA_X1000_DMA_H__ +-#define __DT_BINDINGS_DMA_X1000_DMA_H__ +- +-/* +- * Request type numbers for the X1000 DMA controller (written to the DRTn +- * register for the channel). +- */ +-#define X1000_DMA_DMIC_RX 0x5 +-#define X1000_DMA_I2S0_TX 0x6 +-#define X1000_DMA_I2S0_RX 0x7 +-#define X1000_DMA_AUTO 0x8 +-#define X1000_DMA_UART2_TX 0x10 +-#define X1000_DMA_UART2_RX 0x11 +-#define X1000_DMA_UART1_TX 0x12 +-#define X1000_DMA_UART1_RX 0x13 +-#define X1000_DMA_UART0_TX 0x14 +-#define X1000_DMA_UART0_RX 0x15 +-#define X1000_DMA_SSI0_TX 0x16 +-#define X1000_DMA_SSI0_RX 0x17 +-#define X1000_DMA_MSC0_TX 0x1a +-#define X1000_DMA_MSC0_RX 0x1b +-#define X1000_DMA_MSC1_TX 0x1c +-#define X1000_DMA_MSC1_RX 0x1d +-#define X1000_DMA_PCM0_TX 0x20 +-#define X1000_DMA_PCM0_RX 0x21 +-#define X1000_DMA_SMB0_TX 0x24 +-#define X1000_DMA_SMB0_RX 0x25 +-#define X1000_DMA_SMB1_TX 0x26 +-#define X1000_DMA_SMB1_RX 0x27 +-#define X1000_DMA_SMB2_TX 0x28 +-#define X1000_DMA_SMB2_RX 0x29 +- +-#endif /* __DT_BINDINGS_DMA_X1000_DMA_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/dma/x1830-dma.h b/scripts/dtc/include-prefixes/dt-bindings/dma/x1830-dma.h +deleted file mode 100644 +index 35bcb8966ea4..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/dma/x1830-dma.h ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * This header provides macros for X1830 DMA bindings. +- * +- * Copyright (c) 2019 周琰杰 (Zhou Yanjie) +- */ +- +-#ifndef __DT_BINDINGS_DMA_X1830_DMA_H__ +-#define __DT_BINDINGS_DMA_X1830_DMA_H__ +- +-/* +- * Request type numbers for the X1830 DMA controller (written to the DRTn +- * register for the channel). +- */ +-#define X1830_DMA_I2S0_TX 0x6 +-#define X1830_DMA_I2S0_RX 0x7 +-#define X1830_DMA_AUTO 0x8 +-#define X1830_DMA_SADC_RX 0x9 +-#define X1830_DMA_UART1_TX 0x12 +-#define X1830_DMA_UART1_RX 0x13 +-#define X1830_DMA_UART0_TX 0x14 +-#define X1830_DMA_UART0_RX 0x15 +-#define X1830_DMA_SSI0_TX 0x16 +-#define X1830_DMA_SSI0_RX 0x17 +-#define X1830_DMA_SSI1_TX 0x18 +-#define X1830_DMA_SSI1_RX 0x19 +-#define X1830_DMA_MSC0_TX 0x1a +-#define X1830_DMA_MSC0_RX 0x1b +-#define X1830_DMA_MSC1_TX 0x1c +-#define X1830_DMA_MSC1_RX 0x1d +-#define X1830_DMA_DMIC_RX 0x21 +-#define X1830_DMA_SMB0_TX 0x24 +-#define X1830_DMA_SMB0_RX 0x25 +-#define X1830_DMA_SMB1_TX 0x26 +-#define X1830_DMA_SMB1_RX 0x27 +-#define X1830_DMA_DES_TX 0x2e +-#define X1830_DMA_DES_RX 0x2f +- +-#endif /* __DT_BINDINGS_DMA_X1830_DMA_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/dma/x2000-dma.h b/scripts/dtc/include-prefixes/dt-bindings/dma/x2000-dma.h +deleted file mode 100644 +index db2cd4830b00..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/dma/x2000-dma.h ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * This header provides macros for X2000 DMA bindings. +- * +- * Copyright (c) 2020 周琰杰 (Zhou Yanjie) +- */ +- +-#ifndef __DT_BINDINGS_DMA_X2000_DMA_H__ +-#define __DT_BINDINGS_DMA_X2000_DMA_H__ +- +-/* +- * Request type numbers for the X2000 DMA controller (written to the DRTn +- * register for the channel). +- */ +-#define X2000_DMA_AUTO 0x8 +-#define X2000_DMA_UART5_TX 0xa +-#define X2000_DMA_UART5_RX 0xb +-#define X2000_DMA_UART4_TX 0xc +-#define X2000_DMA_UART4_RX 0xd +-#define X2000_DMA_UART3_TX 0xe +-#define X2000_DMA_UART3_RX 0xf +-#define X2000_DMA_UART2_TX 0x10 +-#define X2000_DMA_UART2_RX 0x11 +-#define X2000_DMA_UART1_TX 0x12 +-#define X2000_DMA_UART1_RX 0x13 +-#define X2000_DMA_UART0_TX 0x14 +-#define X2000_DMA_UART0_RX 0x15 +-#define X2000_DMA_SSI0_TX 0x16 +-#define X2000_DMA_SSI0_RX 0x17 +-#define X2000_DMA_SSI1_TX 0x18 +-#define X2000_DMA_SSI1_RX 0x19 +-#define X2000_DMA_I2C0_TX 0x24 +-#define X2000_DMA_I2C0_RX 0x25 +-#define X2000_DMA_I2C1_TX 0x26 +-#define X2000_DMA_I2C1_RX 0x27 +-#define X2000_DMA_I2C2_TX 0x28 +-#define X2000_DMA_I2C2_RX 0x29 +-#define X2000_DMA_I2C3_TX 0x2a +-#define X2000_DMA_I2C3_RX 0x2b +-#define X2000_DMA_I2C4_TX 0x2c +-#define X2000_DMA_I2C4_RX 0x2d +-#define X2000_DMA_I2C5_TX 0x2e +-#define X2000_DMA_I2C5_RX 0x2f +-#define X2000_DMA_UART6_TX 0x30 +-#define X2000_DMA_UART6_RX 0x31 +-#define X2000_DMA_UART7_TX 0x32 +-#define X2000_DMA_UART7_RX 0x33 +-#define X2000_DMA_UART8_TX 0x34 +-#define X2000_DMA_UART8_RX 0x35 +-#define X2000_DMA_UART9_TX 0x36 +-#define X2000_DMA_UART9_RX 0x37 +-#define X2000_DMA_SADC_RX 0x38 +- +-#endif /* __DT_BINDINGS_DMA_X2000_DMA_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/dma/xlnx-zynqmp-dpdma.h b/scripts/dtc/include-prefixes/dt-bindings/dma/xlnx-zynqmp-dpdma.h +deleted file mode 100644 +index 3719cda5679d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/dma/xlnx-zynqmp-dpdma.h ++++ /dev/null +@@ -1,16 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +-/* +- * Copyright 2019 Laurent Pinchart +- */ +- +-#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ +-#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ +- +-#define ZYNQMP_DPDMA_VIDEO0 0 +-#define ZYNQMP_DPDMA_VIDEO1 1 +-#define ZYNQMP_DPDMA_VIDEO2 2 +-#define ZYNQMP_DPDMA_GRAPHICS 3 +-#define ZYNQMP_DPDMA_AUDIO0 4 +-#define ZYNQMP_DPDMA_AUDIO1 5 +- +-#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/firmware/imx/rsrc.h b/scripts/dtc/include-prefixes/dt-bindings/firmware/imx/rsrc.h +deleted file mode 100644 +index 43885056557c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/firmware/imx/rsrc.h ++++ /dev/null +@@ -1,635 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright (C) 2016 Freescale Semiconductor, Inc. +- * Copyright 2017-2018 NXP +- */ +- +-#ifndef __DT_BINDINGS_RSCRC_IMX_H +-#define __DT_BINDINGS_RSCRC_IMX_H +- +-/* +- * These defines are used to indicate a resource. Resources include peripherals +- * and bus masters (but not memory regions). Note items from list should +- * never be changed or removed (only added to at the end of the list). +- */ +- +-#define IMX_SC_R_A53 0 +-#define IMX_SC_R_A53_0 1 +-#define IMX_SC_R_A53_1 2 +-#define IMX_SC_R_A53_2 3 +-#define IMX_SC_R_A53_3 4 +-#define IMX_SC_R_A72 5 +-#define IMX_SC_R_A72_0 6 +-#define IMX_SC_R_A72_1 7 +-#define IMX_SC_R_A72_2 8 +-#define IMX_SC_R_A72_3 9 +-#define IMX_SC_R_CCI 10 +-#define IMX_SC_R_DB 11 +-#define IMX_SC_R_DRC_0 12 +-#define IMX_SC_R_DRC_1 13 +-#define IMX_SC_R_GIC_SMMU 14 +-#define IMX_SC_R_IRQSTR_M4_0 15 +-#define IMX_SC_R_IRQSTR_M4_1 16 +-#define IMX_SC_R_SMMU 17 +-#define IMX_SC_R_GIC 18 +-#define IMX_SC_R_DC_0_BLIT0 19 +-#define IMX_SC_R_DC_0_BLIT1 20 +-#define IMX_SC_R_DC_0_BLIT2 21 +-#define IMX_SC_R_DC_0_BLIT_OUT 22 +-#define IMX_SC_R_PERF 23 +-#define IMX_SC_R_DC_0_WARP 25 +-#define IMX_SC_R_DC_0_VIDEO0 28 +-#define IMX_SC_R_DC_0_VIDEO1 29 +-#define IMX_SC_R_DC_0_FRAC0 30 +-#define IMX_SC_R_DC_0 32 +-#define IMX_SC_R_GPU_2_PID0 33 +-#define IMX_SC_R_DC_0_PLL_0 34 +-#define IMX_SC_R_DC_0_PLL_1 35 +-#define IMX_SC_R_DC_1_BLIT0 36 +-#define IMX_SC_R_DC_1_BLIT1 37 +-#define IMX_SC_R_DC_1_BLIT2 38 +-#define IMX_SC_R_DC_1_BLIT_OUT 39 +-#define IMX_SC_R_DC_1_WARP 42 +-#define IMX_SC_R_DC_1_VIDEO0 45 +-#define IMX_SC_R_DC_1_VIDEO1 46 +-#define IMX_SC_R_DC_1_FRAC0 47 +-#define IMX_SC_R_DC_1 49 +-#define IMX_SC_R_DC_1_PLL_0 51 +-#define IMX_SC_R_DC_1_PLL_1 52 +-#define IMX_SC_R_SPI_0 53 +-#define IMX_SC_R_SPI_1 54 +-#define IMX_SC_R_SPI_2 55 +-#define IMX_SC_R_SPI_3 56 +-#define IMX_SC_R_UART_0 57 +-#define IMX_SC_R_UART_1 58 +-#define IMX_SC_R_UART_2 59 +-#define IMX_SC_R_UART_3 60 +-#define IMX_SC_R_UART_4 61 +-#define IMX_SC_R_EMVSIM_0 62 +-#define IMX_SC_R_EMVSIM_1 63 +-#define IMX_SC_R_DMA_0_CH0 64 +-#define IMX_SC_R_DMA_0_CH1 65 +-#define IMX_SC_R_DMA_0_CH2 66 +-#define IMX_SC_R_DMA_0_CH3 67 +-#define IMX_SC_R_DMA_0_CH4 68 +-#define IMX_SC_R_DMA_0_CH5 69 +-#define IMX_SC_R_DMA_0_CH6 70 +-#define IMX_SC_R_DMA_0_CH7 71 +-#define IMX_SC_R_DMA_0_CH8 72 +-#define IMX_SC_R_DMA_0_CH9 73 +-#define IMX_SC_R_DMA_0_CH10 74 +-#define IMX_SC_R_DMA_0_CH11 75 +-#define IMX_SC_R_DMA_0_CH12 76 +-#define IMX_SC_R_DMA_0_CH13 77 +-#define IMX_SC_R_DMA_0_CH14 78 +-#define IMX_SC_R_DMA_0_CH15 79 +-#define IMX_SC_R_DMA_0_CH16 80 +-#define IMX_SC_R_DMA_0_CH17 81 +-#define IMX_SC_R_DMA_0_CH18 82 +-#define IMX_SC_R_DMA_0_CH19 83 +-#define IMX_SC_R_DMA_0_CH20 84 +-#define IMX_SC_R_DMA_0_CH21 85 +-#define IMX_SC_R_DMA_0_CH22 86 +-#define IMX_SC_R_DMA_0_CH23 87 +-#define IMX_SC_R_DMA_0_CH24 88 +-#define IMX_SC_R_DMA_0_CH25 89 +-#define IMX_SC_R_DMA_0_CH26 90 +-#define IMX_SC_R_DMA_0_CH27 91 +-#define IMX_SC_R_DMA_0_CH28 92 +-#define IMX_SC_R_DMA_0_CH29 93 +-#define IMX_SC_R_DMA_0_CH30 94 +-#define IMX_SC_R_DMA_0_CH31 95 +-#define IMX_SC_R_I2C_0 96 +-#define IMX_SC_R_I2C_1 97 +-#define IMX_SC_R_I2C_2 98 +-#define IMX_SC_R_I2C_3 99 +-#define IMX_SC_R_I2C_4 100 +-#define IMX_SC_R_ADC_0 101 +-#define IMX_SC_R_ADC_1 102 +-#define IMX_SC_R_FTM_0 103 +-#define IMX_SC_R_FTM_1 104 +-#define IMX_SC_R_CAN_0 105 +-#define IMX_SC_R_CAN_1 106 +-#define IMX_SC_R_CAN_2 107 +-#define IMX_SC_R_CAN(x) (IMX_SC_R_CAN_0 + (x)) +-#define IMX_SC_R_DMA_1_CH0 108 +-#define IMX_SC_R_DMA_1_CH1 109 +-#define IMX_SC_R_DMA_1_CH2 110 +-#define IMX_SC_R_DMA_1_CH3 111 +-#define IMX_SC_R_DMA_1_CH4 112 +-#define IMX_SC_R_DMA_1_CH5 113 +-#define IMX_SC_R_DMA_1_CH6 114 +-#define IMX_SC_R_DMA_1_CH7 115 +-#define IMX_SC_R_DMA_1_CH8 116 +-#define IMX_SC_R_DMA_1_CH9 117 +-#define IMX_SC_R_DMA_1_CH10 118 +-#define IMX_SC_R_DMA_1_CH11 119 +-#define IMX_SC_R_DMA_1_CH12 120 +-#define IMX_SC_R_DMA_1_CH13 121 +-#define IMX_SC_R_DMA_1_CH14 122 +-#define IMX_SC_R_DMA_1_CH15 123 +-#define IMX_SC_R_DMA_1_CH16 124 +-#define IMX_SC_R_DMA_1_CH17 125 +-#define IMX_SC_R_DMA_1_CH18 126 +-#define IMX_SC_R_DMA_1_CH19 127 +-#define IMX_SC_R_DMA_1_CH20 128 +-#define IMX_SC_R_DMA_1_CH21 129 +-#define IMX_SC_R_DMA_1_CH22 130 +-#define IMX_SC_R_DMA_1_CH23 131 +-#define IMX_SC_R_DMA_1_CH24 132 +-#define IMX_SC_R_DMA_1_CH25 133 +-#define IMX_SC_R_DMA_1_CH26 134 +-#define IMX_SC_R_DMA_1_CH27 135 +-#define IMX_SC_R_DMA_1_CH28 136 +-#define IMX_SC_R_DMA_1_CH29 137 +-#define IMX_SC_R_DMA_1_CH30 138 +-#define IMX_SC_R_DMA_1_CH31 139 +-#define IMX_SC_R_UNUSED1 140 +-#define IMX_SC_R_UNUSED2 141 +-#define IMX_SC_R_UNUSED3 142 +-#define IMX_SC_R_UNUSED4 143 +-#define IMX_SC_R_GPU_0_PID0 144 +-#define IMX_SC_R_GPU_0_PID1 145 +-#define IMX_SC_R_GPU_0_PID2 146 +-#define IMX_SC_R_GPU_0_PID3 147 +-#define IMX_SC_R_GPU_1_PID0 148 +-#define IMX_SC_R_GPU_1_PID1 149 +-#define IMX_SC_R_GPU_1_PID2 150 +-#define IMX_SC_R_GPU_1_PID3 151 +-#define IMX_SC_R_PCIE_A 152 +-#define IMX_SC_R_SERDES_0 153 +-#define IMX_SC_R_MATCH_0 154 +-#define IMX_SC_R_MATCH_1 155 +-#define IMX_SC_R_MATCH_2 156 +-#define IMX_SC_R_MATCH_3 157 +-#define IMX_SC_R_MATCH_4 158 +-#define IMX_SC_R_MATCH_5 159 +-#define IMX_SC_R_MATCH_6 160 +-#define IMX_SC_R_MATCH_7 161 +-#define IMX_SC_R_MATCH_8 162 +-#define IMX_SC_R_MATCH_9 163 +-#define IMX_SC_R_MATCH_10 164 +-#define IMX_SC_R_MATCH_11 165 +-#define IMX_SC_R_MATCH_12 166 +-#define IMX_SC_R_MATCH_13 167 +-#define IMX_SC_R_MATCH_14 168 +-#define IMX_SC_R_PCIE_B 169 +-#define IMX_SC_R_SATA_0 170 +-#define IMX_SC_R_SERDES_1 171 +-#define IMX_SC_R_HSIO_GPIO 172 +-#define IMX_SC_R_MATCH_15 173 +-#define IMX_SC_R_MATCH_16 174 +-#define IMX_SC_R_MATCH_17 175 +-#define IMX_SC_R_MATCH_18 176 +-#define IMX_SC_R_MATCH_19 177 +-#define IMX_SC_R_MATCH_20 178 +-#define IMX_SC_R_MATCH_21 179 +-#define IMX_SC_R_MATCH_22 180 +-#define IMX_SC_R_MATCH_23 181 +-#define IMX_SC_R_MATCH_24 182 +-#define IMX_SC_R_MATCH_25 183 +-#define IMX_SC_R_MATCH_26 184 +-#define IMX_SC_R_MATCH_27 185 +-#define IMX_SC_R_MATCH_28 186 +-#define IMX_SC_R_LCD_0 187 +-#define IMX_SC_R_LCD_0_PWM_0 188 +-#define IMX_SC_R_LCD_0_I2C_0 189 +-#define IMX_SC_R_LCD_0_I2C_1 190 +-#define IMX_SC_R_PWM_0 191 +-#define IMX_SC_R_PWM_1 192 +-#define IMX_SC_R_PWM_2 193 +-#define IMX_SC_R_PWM_3 194 +-#define IMX_SC_R_PWM_4 195 +-#define IMX_SC_R_PWM_5 196 +-#define IMX_SC_R_PWM_6 197 +-#define IMX_SC_R_PWM_7 198 +-#define IMX_SC_R_GPIO_0 199 +-#define IMX_SC_R_GPIO_1 200 +-#define IMX_SC_R_GPIO_2 201 +-#define IMX_SC_R_GPIO_3 202 +-#define IMX_SC_R_GPIO_4 203 +-#define IMX_SC_R_GPIO_5 204 +-#define IMX_SC_R_GPIO_6 205 +-#define IMX_SC_R_GPIO_7 206 +-#define IMX_SC_R_GPT_0 207 +-#define IMX_SC_R_GPT_1 208 +-#define IMX_SC_R_GPT_2 209 +-#define IMX_SC_R_GPT_3 210 +-#define IMX_SC_R_GPT_4 211 +-#define IMX_SC_R_KPP 212 +-#define IMX_SC_R_MU_0A 213 +-#define IMX_SC_R_MU_1A 214 +-#define IMX_SC_R_MU_2A 215 +-#define IMX_SC_R_MU_3A 216 +-#define IMX_SC_R_MU_4A 217 +-#define IMX_SC_R_MU_5A 218 +-#define IMX_SC_R_MU_6A 219 +-#define IMX_SC_R_MU_7A 220 +-#define IMX_SC_R_MU_8A 221 +-#define IMX_SC_R_MU_9A 222 +-#define IMX_SC_R_MU_10A 223 +-#define IMX_SC_R_MU_11A 224 +-#define IMX_SC_R_MU_12A 225 +-#define IMX_SC_R_MU_13A 226 +-#define IMX_SC_R_MU_5B 227 +-#define IMX_SC_R_MU_6B 228 +-#define IMX_SC_R_MU_7B 229 +-#define IMX_SC_R_MU_8B 230 +-#define IMX_SC_R_MU_9B 231 +-#define IMX_SC_R_MU_10B 232 +-#define IMX_SC_R_MU_11B 233 +-#define IMX_SC_R_MU_12B 234 +-#define IMX_SC_R_MU_13B 235 +-#define IMX_SC_R_ROM_0 236 +-#define IMX_SC_R_FSPI_0 237 +-#define IMX_SC_R_FSPI_1 238 +-#define IMX_SC_R_IEE 239 +-#define IMX_SC_R_IEE_R0 240 +-#define IMX_SC_R_IEE_R1 241 +-#define IMX_SC_R_IEE_R2 242 +-#define IMX_SC_R_IEE_R3 243 +-#define IMX_SC_R_IEE_R4 244 +-#define IMX_SC_R_IEE_R5 245 +-#define IMX_SC_R_IEE_R6 246 +-#define IMX_SC_R_IEE_R7 247 +-#define IMX_SC_R_SDHC_0 248 +-#define IMX_SC_R_SDHC_1 249 +-#define IMX_SC_R_SDHC_2 250 +-#define IMX_SC_R_ENET_0 251 +-#define IMX_SC_R_ENET_1 252 +-#define IMX_SC_R_MLB_0 253 +-#define IMX_SC_R_DMA_2_CH0 254 +-#define IMX_SC_R_DMA_2_CH1 255 +-#define IMX_SC_R_DMA_2_CH2 256 +-#define IMX_SC_R_DMA_2_CH3 257 +-#define IMX_SC_R_DMA_2_CH4 258 +-#define IMX_SC_R_USB_0 259 +-#define IMX_SC_R_USB_1 260 +-#define IMX_SC_R_USB_0_PHY 261 +-#define IMX_SC_R_USB_2 262 +-#define IMX_SC_R_USB_2_PHY 263 +-#define IMX_SC_R_DTCP 264 +-#define IMX_SC_R_NAND 265 +-#define IMX_SC_R_LVDS_0 266 +-#define IMX_SC_R_LVDS_0_PWM_0 267 +-#define IMX_SC_R_LVDS_0_I2C_0 268 +-#define IMX_SC_R_LVDS_0_I2C_1 269 +-#define IMX_SC_R_LVDS_1 270 +-#define IMX_SC_R_LVDS_1_PWM_0 271 +-#define IMX_SC_R_LVDS_1_I2C_0 272 +-#define IMX_SC_R_LVDS_1_I2C_1 273 +-#define IMX_SC_R_LVDS_2 274 +-#define IMX_SC_R_LVDS_2_PWM_0 275 +-#define IMX_SC_R_LVDS_2_I2C_0 276 +-#define IMX_SC_R_LVDS_2_I2C_1 277 +-#define IMX_SC_R_M4_0_PID0 278 +-#define IMX_SC_R_M4_0_PID1 279 +-#define IMX_SC_R_M4_0_PID2 280 +-#define IMX_SC_R_M4_0_PID3 281 +-#define IMX_SC_R_M4_0_PID4 282 +-#define IMX_SC_R_M4_0_RGPIO 283 +-#define IMX_SC_R_M4_0_SEMA42 284 +-#define IMX_SC_R_M4_0_TPM 285 +-#define IMX_SC_R_M4_0_PIT 286 +-#define IMX_SC_R_M4_0_UART 287 +-#define IMX_SC_R_M4_0_I2C 288 +-#define IMX_SC_R_M4_0_INTMUX 289 +-#define IMX_SC_R_M4_0_MU_0B 292 +-#define IMX_SC_R_M4_0_MU_0A0 293 +-#define IMX_SC_R_M4_0_MU_0A1 294 +-#define IMX_SC_R_M4_0_MU_0A2 295 +-#define IMX_SC_R_M4_0_MU_0A3 296 +-#define IMX_SC_R_M4_0_MU_1A 297 +-#define IMX_SC_R_M4_1_PID0 298 +-#define IMX_SC_R_M4_1_PID1 299 +-#define IMX_SC_R_M4_1_PID2 300 +-#define IMX_SC_R_M4_1_PID3 301 +-#define IMX_SC_R_M4_1_PID4 302 +-#define IMX_SC_R_M4_1_RGPIO 303 +-#define IMX_SC_R_M4_1_SEMA42 304 +-#define IMX_SC_R_M4_1_TPM 305 +-#define IMX_SC_R_M4_1_PIT 306 +-#define IMX_SC_R_M4_1_UART 307 +-#define IMX_SC_R_M4_1_I2C 308 +-#define IMX_SC_R_M4_1_INTMUX 309 +-#define IMX_SC_R_M4_1_MU_0B 312 +-#define IMX_SC_R_M4_1_MU_0A0 313 +-#define IMX_SC_R_M4_1_MU_0A1 314 +-#define IMX_SC_R_M4_1_MU_0A2 315 +-#define IMX_SC_R_M4_1_MU_0A3 316 +-#define IMX_SC_R_M4_1_MU_1A 317 +-#define IMX_SC_R_SAI_0 318 +-#define IMX_SC_R_SAI_1 319 +-#define IMX_SC_R_SAI_2 320 +-#define IMX_SC_R_IRQSTR_SCU2 321 +-#define IMX_SC_R_IRQSTR_DSP 322 +-#define IMX_SC_R_ELCDIF_PLL 323 +-#define IMX_SC_R_OCRAM 324 +-#define IMX_SC_R_AUDIO_PLL_0 325 +-#define IMX_SC_R_PI_0 326 +-#define IMX_SC_R_PI_0_PWM_0 327 +-#define IMX_SC_R_PI_0_PWM_1 328 +-#define IMX_SC_R_PI_0_I2C_0 329 +-#define IMX_SC_R_PI_0_PLL 330 +-#define IMX_SC_R_PI_1 331 +-#define IMX_SC_R_PI_1_PWM_0 332 +-#define IMX_SC_R_PI_1_PWM_1 333 +-#define IMX_SC_R_PI_1_I2C_0 334 +-#define IMX_SC_R_PI_1_PLL 335 +-#define IMX_SC_R_SC_PID0 336 +-#define IMX_SC_R_SC_PID1 337 +-#define IMX_SC_R_SC_PID2 338 +-#define IMX_SC_R_SC_PID3 339 +-#define IMX_SC_R_SC_PID4 340 +-#define IMX_SC_R_SC_SEMA42 341 +-#define IMX_SC_R_SC_TPM 342 +-#define IMX_SC_R_SC_PIT 343 +-#define IMX_SC_R_SC_UART 344 +-#define IMX_SC_R_SC_I2C 345 +-#define IMX_SC_R_SC_MU_0B 346 +-#define IMX_SC_R_SC_MU_0A0 347 +-#define IMX_SC_R_SC_MU_0A1 348 +-#define IMX_SC_R_SC_MU_0A2 349 +-#define IMX_SC_R_SC_MU_0A3 350 +-#define IMX_SC_R_SC_MU_1A 351 +-#define IMX_SC_R_SYSCNT_RD 352 +-#define IMX_SC_R_SYSCNT_CMP 353 +-#define IMX_SC_R_DEBUG 354 +-#define IMX_SC_R_SYSTEM 355 +-#define IMX_SC_R_SNVS 356 +-#define IMX_SC_R_OTP 357 +-#define IMX_SC_R_VPU_PID0 358 +-#define IMX_SC_R_VPU_PID1 359 +-#define IMX_SC_R_VPU_PID2 360 +-#define IMX_SC_R_VPU_PID3 361 +-#define IMX_SC_R_VPU_PID4 362 +-#define IMX_SC_R_VPU_PID5 363 +-#define IMX_SC_R_VPU_PID6 364 +-#define IMX_SC_R_VPU_PID7 365 +-#define IMX_SC_R_VPU_UART 366 +-#define IMX_SC_R_VPUCORE 367 +-#define IMX_SC_R_VPUCORE_0 368 +-#define IMX_SC_R_VPUCORE_1 369 +-#define IMX_SC_R_VPUCORE_2 370 +-#define IMX_SC_R_VPUCORE_3 371 +-#define IMX_SC_R_DMA_4_CH0 372 +-#define IMX_SC_R_DMA_4_CH1 373 +-#define IMX_SC_R_DMA_4_CH2 374 +-#define IMX_SC_R_DMA_4_CH3 375 +-#define IMX_SC_R_DMA_4_CH4 376 +-#define IMX_SC_R_ISI_CH0 377 +-#define IMX_SC_R_ISI_CH1 378 +-#define IMX_SC_R_ISI_CH2 379 +-#define IMX_SC_R_ISI_CH3 380 +-#define IMX_SC_R_ISI_CH4 381 +-#define IMX_SC_R_ISI_CH5 382 +-#define IMX_SC_R_ISI_CH6 383 +-#define IMX_SC_R_ISI_CH7 384 +-#define IMX_SC_R_MJPEG_DEC_S0 385 +-#define IMX_SC_R_MJPEG_DEC_S1 386 +-#define IMX_SC_R_MJPEG_DEC_S2 387 +-#define IMX_SC_R_MJPEG_DEC_S3 388 +-#define IMX_SC_R_MJPEG_ENC_S0 389 +-#define IMX_SC_R_MJPEG_ENC_S1 390 +-#define IMX_SC_R_MJPEG_ENC_S2 391 +-#define IMX_SC_R_MJPEG_ENC_S3 392 +-#define IMX_SC_R_MIPI_0 393 +-#define IMX_SC_R_MIPI_0_PWM_0 394 +-#define IMX_SC_R_MIPI_0_I2C_0 395 +-#define IMX_SC_R_MIPI_0_I2C_1 396 +-#define IMX_SC_R_MIPI_1 397 +-#define IMX_SC_R_MIPI_1_PWM_0 398 +-#define IMX_SC_R_MIPI_1_I2C_0 399 +-#define IMX_SC_R_MIPI_1_I2C_1 400 +-#define IMX_SC_R_CSI_0 401 +-#define IMX_SC_R_CSI_0_PWM_0 402 +-#define IMX_SC_R_CSI_0_I2C_0 403 +-#define IMX_SC_R_CSI_1 404 +-#define IMX_SC_R_CSI_1_PWM_0 405 +-#define IMX_SC_R_CSI_1_I2C_0 406 +-#define IMX_SC_R_HDMI 407 +-#define IMX_SC_R_HDMI_I2S 408 +-#define IMX_SC_R_HDMI_I2C_0 409 +-#define IMX_SC_R_HDMI_PLL_0 410 +-#define IMX_SC_R_HDMI_RX 411 +-#define IMX_SC_R_HDMI_RX_BYPASS 412 +-#define IMX_SC_R_HDMI_RX_I2C_0 413 +-#define IMX_SC_R_ASRC_0 414 +-#define IMX_SC_R_ESAI_0 415 +-#define IMX_SC_R_SPDIF_0 416 +-#define IMX_SC_R_SPDIF_1 417 +-#define IMX_SC_R_SAI_3 418 +-#define IMX_SC_R_SAI_4 419 +-#define IMX_SC_R_SAI_5 420 +-#define IMX_SC_R_GPT_5 421 +-#define IMX_SC_R_GPT_6 422 +-#define IMX_SC_R_GPT_7 423 +-#define IMX_SC_R_GPT_8 424 +-#define IMX_SC_R_GPT_9 425 +-#define IMX_SC_R_GPT_10 426 +-#define IMX_SC_R_DMA_2_CH5 427 +-#define IMX_SC_R_DMA_2_CH6 428 +-#define IMX_SC_R_DMA_2_CH7 429 +-#define IMX_SC_R_DMA_2_CH8 430 +-#define IMX_SC_R_DMA_2_CH9 431 +-#define IMX_SC_R_DMA_2_CH10 432 +-#define IMX_SC_R_DMA_2_CH11 433 +-#define IMX_SC_R_DMA_2_CH12 434 +-#define IMX_SC_R_DMA_2_CH13 435 +-#define IMX_SC_R_DMA_2_CH14 436 +-#define IMX_SC_R_DMA_2_CH15 437 +-#define IMX_SC_R_DMA_2_CH16 438 +-#define IMX_SC_R_DMA_2_CH17 439 +-#define IMX_SC_R_DMA_2_CH18 440 +-#define IMX_SC_R_DMA_2_CH19 441 +-#define IMX_SC_R_DMA_2_CH20 442 +-#define IMX_SC_R_DMA_2_CH21 443 +-#define IMX_SC_R_DMA_2_CH22 444 +-#define IMX_SC_R_DMA_2_CH23 445 +-#define IMX_SC_R_DMA_2_CH24 446 +-#define IMX_SC_R_DMA_2_CH25 447 +-#define IMX_SC_R_DMA_2_CH26 448 +-#define IMX_SC_R_DMA_2_CH27 449 +-#define IMX_SC_R_DMA_2_CH28 450 +-#define IMX_SC_R_DMA_2_CH29 451 +-#define IMX_SC_R_DMA_2_CH30 452 +-#define IMX_SC_R_DMA_2_CH31 453 +-#define IMX_SC_R_ASRC_1 454 +-#define IMX_SC_R_ESAI_1 455 +-#define IMX_SC_R_SAI_6 456 +-#define IMX_SC_R_SAI_7 457 +-#define IMX_SC_R_AMIX 458 +-#define IMX_SC_R_MQS_0 459 +-#define IMX_SC_R_DMA_3_CH0 460 +-#define IMX_SC_R_DMA_3_CH1 461 +-#define IMX_SC_R_DMA_3_CH2 462 +-#define IMX_SC_R_DMA_3_CH3 463 +-#define IMX_SC_R_DMA_3_CH4 464 +-#define IMX_SC_R_DMA_3_CH5 465 +-#define IMX_SC_R_DMA_3_CH6 466 +-#define IMX_SC_R_DMA_3_CH7 467 +-#define IMX_SC_R_DMA_3_CH8 468 +-#define IMX_SC_R_DMA_3_CH9 469 +-#define IMX_SC_R_DMA_3_CH10 470 +-#define IMX_SC_R_DMA_3_CH11 471 +-#define IMX_SC_R_DMA_3_CH12 472 +-#define IMX_SC_R_DMA_3_CH13 473 +-#define IMX_SC_R_DMA_3_CH14 474 +-#define IMX_SC_R_DMA_3_CH15 475 +-#define IMX_SC_R_DMA_3_CH16 476 +-#define IMX_SC_R_DMA_3_CH17 477 +-#define IMX_SC_R_DMA_3_CH18 478 +-#define IMX_SC_R_DMA_3_CH19 479 +-#define IMX_SC_R_DMA_3_CH20 480 +-#define IMX_SC_R_DMA_3_CH21 481 +-#define IMX_SC_R_DMA_3_CH22 482 +-#define IMX_SC_R_DMA_3_CH23 483 +-#define IMX_SC_R_DMA_3_CH24 484 +-#define IMX_SC_R_DMA_3_CH25 485 +-#define IMX_SC_R_DMA_3_CH26 486 +-#define IMX_SC_R_DMA_3_CH27 487 +-#define IMX_SC_R_DMA_3_CH28 488 +-#define IMX_SC_R_DMA_3_CH29 489 +-#define IMX_SC_R_DMA_3_CH30 490 +-#define IMX_SC_R_DMA_3_CH31 491 +-#define IMX_SC_R_AUDIO_PLL_1 492 +-#define IMX_SC_R_AUDIO_CLK_0 493 +-#define IMX_SC_R_AUDIO_CLK_1 494 +-#define IMX_SC_R_MCLK_OUT_0 495 +-#define IMX_SC_R_MCLK_OUT_1 496 +-#define IMX_SC_R_PMIC_0 497 +-#define IMX_SC_R_PMIC_1 498 +-#define IMX_SC_R_SECO 499 +-#define IMX_SC_R_CAAM_JR1 500 +-#define IMX_SC_R_CAAM_JR2 501 +-#define IMX_SC_R_CAAM_JR3 502 +-#define IMX_SC_R_SECO_MU_2 503 +-#define IMX_SC_R_SECO_MU_3 504 +-#define IMX_SC_R_SECO_MU_4 505 +-#define IMX_SC_R_HDMI_RX_PWM_0 506 +-#define IMX_SC_R_A35 507 +-#define IMX_SC_R_A35_0 508 +-#define IMX_SC_R_A35_1 509 +-#define IMX_SC_R_A35_2 510 +-#define IMX_SC_R_A35_3 511 +-#define IMX_SC_R_DSP 512 +-#define IMX_SC_R_DSP_RAM 513 +-#define IMX_SC_R_CAAM_JR1_OUT 514 +-#define IMX_SC_R_CAAM_JR2_OUT 515 +-#define IMX_SC_R_CAAM_JR3_OUT 516 +-#define IMX_SC_R_VPU_DEC_0 517 +-#define IMX_SC_R_VPU_ENC_0 518 +-#define IMX_SC_R_CAAM_JR0 519 +-#define IMX_SC_R_CAAM_JR0_OUT 520 +-#define IMX_SC_R_PMIC_2 521 +-#define IMX_SC_R_DBLOGIC 522 +-#define IMX_SC_R_HDMI_PLL_1 523 +-#define IMX_SC_R_BOARD_R0 524 +-#define IMX_SC_R_BOARD_R1 525 +-#define IMX_SC_R_BOARD_R2 526 +-#define IMX_SC_R_BOARD_R3 527 +-#define IMX_SC_R_BOARD_R4 528 +-#define IMX_SC_R_BOARD_R5 529 +-#define IMX_SC_R_BOARD_R6 530 +-#define IMX_SC_R_BOARD_R7 531 +-#define IMX_SC_R_MJPEG_DEC_MP 532 +-#define IMX_SC_R_MJPEG_ENC_MP 533 +-#define IMX_SC_R_VPU_TS_0 534 +-#define IMX_SC_R_VPU_MU_0 535 +-#define IMX_SC_R_VPU_MU_1 536 +-#define IMX_SC_R_VPU_MU_2 537 +-#define IMX_SC_R_VPU_MU_3 538 +-#define IMX_SC_R_VPU_ENC_1 539 +-#define IMX_SC_R_VPU 540 +-#define IMX_SC_R_DMA_5_CH0 541 +-#define IMX_SC_R_DMA_5_CH1 542 +-#define IMX_SC_R_DMA_5_CH2 543 +-#define IMX_SC_R_DMA_5_CH3 544 +-#define IMX_SC_R_ATTESTATION 545 +-#define IMX_SC_R_LAST 546 +- +-/* +- * Defines for SC PM CLK +- */ +-#define IMX_SC_PM_CLK_SLV_BUS 0 /* Slave bus clock */ +-#define IMX_SC_PM_CLK_MST_BUS 1 /* Master bus clock */ +-#define IMX_SC_PM_CLK_PER 2 /* Peripheral clock */ +-#define IMX_SC_PM_CLK_PHY 3 /* Phy clock */ +-#define IMX_SC_PM_CLK_MISC 4 /* Misc clock */ +-#define IMX_SC_PM_CLK_MISC0 0 /* Misc 0 clock */ +-#define IMX_SC_PM_CLK_MISC1 1 /* Misc 1 clock */ +-#define IMX_SC_PM_CLK_MISC2 2 /* Misc 2 clock */ +-#define IMX_SC_PM_CLK_MISC3 3 /* Misc 3 clock */ +-#define IMX_SC_PM_CLK_MISC4 4 /* Misc 4 clock */ +-#define IMX_SC_PM_CLK_CPU 2 /* CPU clock */ +-#define IMX_SC_PM_CLK_PLL 4 /* PLL */ +-#define IMX_SC_PM_CLK_BYPASS 4 /* Bypass clock */ +- +-/* +- * Defines for SC CONTROL +- */ +-#define IMX_SC_C_TEMP 0 +-#define IMX_SC_C_TEMP_HI 1 +-#define IMX_SC_C_TEMP_LOW 2 +-#define IMX_SC_C_PXL_LINK_MST1_ADDR 3 +-#define IMX_SC_C_PXL_LINK_MST2_ADDR 4 +-#define IMX_SC_C_PXL_LINK_MST_ENB 5 +-#define IMX_SC_C_PXL_LINK_MST1_ENB 6 +-#define IMX_SC_C_PXL_LINK_MST2_ENB 7 +-#define IMX_SC_C_PXL_LINK_SLV1_ADDR 8 +-#define IMX_SC_C_PXL_LINK_SLV2_ADDR 9 +-#define IMX_SC_C_PXL_LINK_MST_VLD 10 +-#define IMX_SC_C_PXL_LINK_MST1_VLD 11 +-#define IMX_SC_C_PXL_LINK_MST2_VLD 12 +-#define IMX_SC_C_SINGLE_MODE 13 +-#define IMX_SC_C_ID 14 +-#define IMX_SC_C_PXL_CLK_POLARITY 15 +-#define IMX_SC_C_LINESTATE 16 +-#define IMX_SC_C_PCIE_G_RST 17 +-#define IMX_SC_C_PCIE_BUTTON_RST 18 +-#define IMX_SC_C_PCIE_PERST 19 +-#define IMX_SC_C_PHY_RESET 20 +-#define IMX_SC_C_PXL_LINK_RATE_CORRECTION 21 +-#define IMX_SC_C_PANIC 22 +-#define IMX_SC_C_PRIORITY_GROUP 23 +-#define IMX_SC_C_TXCLK 24 +-#define IMX_SC_C_CLKDIV 25 +-#define IMX_SC_C_DISABLE_50 26 +-#define IMX_SC_C_DISABLE_125 27 +-#define IMX_SC_C_SEL_125 28 +-#define IMX_SC_C_MODE 29 +-#define IMX_SC_C_SYNC_CTRL0 30 +-#define IMX_SC_C_KACHUNK_CNT 31 +-#define IMX_SC_C_KACHUNK_SEL 32 +-#define IMX_SC_C_SYNC_CTRL1 33 +-#define IMX_SC_C_DPI_RESET 34 +-#define IMX_SC_C_MIPI_RESET 35 +-#define IMX_SC_C_DUAL_MODE 36 +-#define IMX_SC_C_VOLTAGE 37 +-#define IMX_SC_C_PXL_LINK_SEL 38 +-#define IMX_SC_C_OFS_SEL 39 +-#define IMX_SC_C_OFS_AUDIO 40 +-#define IMX_SC_C_OFS_PERIPH 41 +-#define IMX_SC_C_OFS_IRQ 42 +-#define IMX_SC_C_RST0 43 +-#define IMX_SC_C_RST1 44 +-#define IMX_SC_C_SEL0 45 +-#define IMX_SC_C_CALIB0 46 +-#define IMX_SC_C_CALIB1 47 +-#define IMX_SC_C_CALIB2 48 +-#define IMX_SC_C_IPG_DEBUG 49 +-#define IMX_SC_C_IPG_DOZE 50 +-#define IMX_SC_C_IPG_WAIT 51 +-#define IMX_SC_C_IPG_STOP 52 +-#define IMX_SC_C_IPG_STOP_MODE 53 +-#define IMX_SC_C_IPG_STOP_ACK 54 +-#define IMX_SC_C_SYNC_CTRL 55 +-#define IMX_SC_C_OFS_AUDIO_ALT 56 +-#define IMX_SC_C_DSP_BYP 57 +-#define IMX_SC_C_CLK_GEN_EN 58 +-#define IMX_SC_C_INTF_SEL 59 +-#define IMX_SC_C_RXC_DLY 60 +-#define IMX_SC_C_TIMER_SEL 61 +-#define IMX_SC_C_LAST 62 +- +-#endif /* __DT_BINDINGS_RSCRC_IMX_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/gce/mt6779-gce.h b/scripts/dtc/include-prefixes/dt-bindings/gce/mt6779-gce.h +deleted file mode 100644 +index 06101316ace4..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/gce/mt6779-gce.h ++++ /dev/null +@@ -1,222 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2019 MediaTek Inc. +- * Author: Dennis-YC Hsieh +- */ +- +-#ifndef _DT_BINDINGS_GCE_MT6779_H +-#define _DT_BINDINGS_GCE_MT6779_H +- +-#define CMDQ_NO_TIMEOUT 0xffffffff +- +-/* GCE HW thread priority */ +-#define CMDQ_THR_PRIO_LOWEST 0 +-#define CMDQ_THR_PRIO_1 1 +-#define CMDQ_THR_PRIO_2 2 +-#define CMDQ_THR_PRIO_3 3 +-#define CMDQ_THR_PRIO_4 4 +-#define CMDQ_THR_PRIO_5 5 +-#define CMDQ_THR_PRIO_6 6 +-#define CMDQ_THR_PRIO_HIGHEST 7 +- +-/* GCE subsys table */ +-#define SUBSYS_1300XXXX 0 +-#define SUBSYS_1400XXXX 1 +-#define SUBSYS_1401XXXX 2 +-#define SUBSYS_1402XXXX 3 +-#define SUBSYS_1502XXXX 4 +-#define SUBSYS_1880XXXX 5 +-#define SUBSYS_1881XXXX 6 +-#define SUBSYS_1882XXXX 7 +-#define SUBSYS_1883XXXX 8 +-#define SUBSYS_1884XXXX 9 +-#define SUBSYS_1000XXXX 10 +-#define SUBSYS_1001XXXX 11 +-#define SUBSYS_1002XXXX 12 +-#define SUBSYS_1003XXXX 13 +-#define SUBSYS_1004XXXX 14 +-#define SUBSYS_1005XXXX 15 +-#define SUBSYS_1020XXXX 16 +-#define SUBSYS_1028XXXX 17 +-#define SUBSYS_1700XXXX 18 +-#define SUBSYS_1701XXXX 19 +-#define SUBSYS_1702XXXX 20 +-#define SUBSYS_1703XXXX 21 +-#define SUBSYS_1800XXXX 22 +-#define SUBSYS_1801XXXX 23 +-#define SUBSYS_1802XXXX 24 +-#define SUBSYS_1804XXXX 25 +-#define SUBSYS_1805XXXX 26 +-#define SUBSYS_1808XXXX 27 +-#define SUBSYS_180aXXXX 28 +-#define SUBSYS_180bXXXX 29 +-#define CMDQ_SUBSYS_OFF 32 +- +-/* GCE hardware events */ +-#define CMDQ_EVENT_DISP_RDMA0_SOF 0 +-#define CMDQ_EVENT_DISP_RDMA1_SOF 1 +-#define CMDQ_EVENT_MDP_RDMA0_SOF 2 +-#define CMDQ_EVENT_MDP_RDMA1_SOF 3 +-#define CMDQ_EVENT_MDP_RSZ0_SOF 4 +-#define CMDQ_EVENT_MDP_RSZ1_SOF 5 +-#define CMDQ_EVENT_MDP_TDSHP_SOF 6 +-#define CMDQ_EVENT_MDP_WROT0_SOF 7 +-#define CMDQ_EVENT_MDP_WROT1_SOF 8 +-#define CMDQ_EVENT_DISP_OVL0_SOF 9 +-#define CMDQ_EVENT_DISP_2L_OVL0_SOF 10 +-#define CMDQ_EVENT_DISP_2L_OVL1_SOF 11 +-#define CMDQ_EVENT_DISP_WDMA0_SOF 12 +-#define CMDQ_EVENT_DISP_COLOR0_SOF 13 +-#define CMDQ_EVENT_DISP_CCORR0_SOF 14 +-#define CMDQ_EVENT_DISP_AAL0_SOF 15 +-#define CMDQ_EVENT_DISP_GAMMA0_SOF 16 +-#define CMDQ_EVENT_DISP_DITHER0_SOF 17 +-#define CMDQ_EVENT_DISP_PWM0_SOF 18 +-#define CMDQ_EVENT_DISP_DSI0_SOF 19 +-#define CMDQ_EVENT_DISP_DPI0_SOF 20 +-#define CMDQ_EVENT_DISP_POSTMASK0_SOF 21 +-#define CMDQ_EVENT_DISP_RSZ0_SOF 22 +-#define CMDQ_EVENT_MDP_AAL_SOF 23 +-#define CMDQ_EVENT_MDP_CCORR_SOF 24 +-#define CMDQ_EVENT_DISP_DBI0_SOF 25 +-#define CMDQ_EVENT_ISP_RELAY_SOF 26 +-#define CMDQ_EVENT_IPU_RELAY_SOF 27 +-#define CMDQ_EVENT_DISP_RDMA0_EOF 28 +-#define CMDQ_EVENT_DISP_RDMA1_EOF 29 +-#define CMDQ_EVENT_MDP_RDMA0_EOF 30 +-#define CMDQ_EVENT_MDP_RDMA1_EOF 31 +-#define CMDQ_EVENT_MDP_RSZ0_EOF 32 +-#define CMDQ_EVENT_MDP_RSZ1_EOF 33 +-#define CMDQ_EVENT_MDP_TDSHP_EOF 34 +-#define CMDQ_EVENT_MDP_WROT0_W_EOF 35 +-#define CMDQ_EVENT_MDP_WROT1_W_EOF 36 +-#define CMDQ_EVENT_DISP_OVL0_EOF 37 +-#define CMDQ_EVENT_DISP_2L_OVL0_EOF 38 +-#define CMDQ_EVENT_DISP_2L_OVL1_EOF 39 +-#define CMDQ_EVENT_DISP_WDMA0_EOF 40 +-#define CMDQ_EVENT_DISP_COLOR0_EOF 41 +-#define CMDQ_EVENT_DISP_CCORR0_EOF 42 +-#define CMDQ_EVENT_DISP_AAL0_EOF 43 +-#define CMDQ_EVENT_DISP_GAMMA0_EOF 44 +-#define CMDQ_EVENT_DISP_DITHER0_EOF 45 +-#define CMDQ_EVENT_DISP_DSI0_EOF 46 +-#define CMDQ_EVENT_DISP_DPI0_EOF 47 +-#define CMDQ_EVENT_DISP_RSZ0_EOF 49 +-#define CMDQ_EVENT_MDP_AAL_FRAME_DONE 50 +-#define CMDQ_EVENT_MDP_CCORR_FRAME_DONE 51 +-#define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 52 +-#define CMDQ_EVENT_MUTEX0_STREAM_EOF 130 +-#define CMDQ_EVENT_MUTEX1_STREAM_EOF 131 +-#define CMDQ_EVENT_MUTEX2_STREAM_EOF 132 +-#define CMDQ_EVENT_MUTEX3_STREAM_EOF 133 +-#define CMDQ_EVENT_MUTEX4_STREAM_EOF 134 +-#define CMDQ_EVENT_MUTEX5_STREAM_EOF 135 +-#define CMDQ_EVENT_MUTEX6_STREAM_EOF 136 +-#define CMDQ_EVENT_MUTEX7_STREAM_EOF 137 +-#define CMDQ_EVENT_MUTEX8_STREAM_EOF 138 +-#define CMDQ_EVENT_MUTEX9_STREAM_EOF 139 +-#define CMDQ_EVENT_MUTEX10_STREAM_EOF 140 +-#define CMDQ_EVENT_MUTEX11_STREAM_EOF 141 +-#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 142 +-#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 143 +-#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 144 +-#define CMDQ_EVENT_DISP_RDMA3_UNDERRUN 145 +-#define CMDQ_EVENT_DSI0_TE 146 +-#define CMDQ_EVENT_DSI0_IRQ_EVENT 147 +-#define CMDQ_EVENT_DSI0_DONE_EVENT 148 +-#define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE 150 +-#define CMDQ_EVENT_DISP_WDMA0_RST_DONE 151 +-#define CMDQ_EVENT_MDP_WROT0_RST_DONE 153 +-#define CMDQ_EVENT_MDP_RDMA0_RST_DONE 154 +-#define CMDQ_EVENT_DISP_OVL0_RST_DONE 155 +-#define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE 156 +-#define CMDQ_EVENT_DISP_OVL1_2L_RST_DONE 157 +-#define CMDQ_EVENT_DIP_CQ_THREAD0_EOF 257 +-#define CMDQ_EVENT_DIP_CQ_THREAD1_EOF 258 +-#define CMDQ_EVENT_DIP_CQ_THREAD2_EOF 259 +-#define CMDQ_EVENT_DIP_CQ_THREAD3_EOF 260 +-#define CMDQ_EVENT_DIP_CQ_THREAD4_EOF 261 +-#define CMDQ_EVENT_DIP_CQ_THREAD5_EOF 262 +-#define CMDQ_EVENT_DIP_CQ_THREAD6_EOF 263 +-#define CMDQ_EVENT_DIP_CQ_THREAD7_EOF 264 +-#define CMDQ_EVENT_DIP_CQ_THREAD8_EOF 265 +-#define CMDQ_EVENT_DIP_CQ_THREAD9_EOF 266 +-#define CMDQ_EVENT_DIP_CQ_THREAD10_EOF 267 +-#define CMDQ_EVENT_DIP_CQ_THREAD11_EOF 268 +-#define CMDQ_EVENT_DIP_CQ_THREAD12_EOF 269 +-#define CMDQ_EVENT_DIP_CQ_THREAD13_EOF 270 +-#define CMDQ_EVENT_DIP_CQ_THREAD14_EOF 271 +-#define CMDQ_EVENT_DIP_CQ_THREAD15_EOF 272 +-#define CMDQ_EVENT_DIP_CQ_THREAD16_EOF 273 +-#define CMDQ_EVENT_DIP_CQ_THREAD17_EOF 274 +-#define CMDQ_EVENT_DIP_CQ_THREAD18_EOF 275 +-#define CMDQ_EVENT_DIP_DMA_ERR_EVENT 276 +-#define CMDQ_EVENT_AMD_FRAME_DONE 277 +-#define CMDQ_EVENT_MFB_DONE 278 +-#define CMDQ_EVENT_WPE_A_EOF 279 +-#define CMDQ_EVENT_VENC_EOF 289 +-#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 290 +-#define CMDQ_EVENT_JPEG_ENC_EOF 291 +-#define CMDQ_EVENT_VENC_MB_DONE 292 +-#define CMDQ_EVENT_VENC_128BYTE_CNT_DONE 293 +-#define CMDQ_EVENT_ISP_FRAME_DONE_A 321 +-#define CMDQ_EVENT_ISP_FRAME_DONE_B 322 +-#define CMDQ_EVENT_ISP_FRAME_DONE_C 323 +-#define CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE 324 +-#define CMDQ_EVENT_ISP_CAMSV_0_2_PASS1_DONE 325 +-#define CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE 326 +-#define CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE 327 +-#define CMDQ_EVENT_ISP_CAMSV_3_PASS1_DONE 328 +-#define CMDQ_EVENT_ISP_TSF_DONE 329 +-#define CMDQ_EVENT_SENINF_0_FIFO_FULL 330 +-#define CMDQ_EVENT_SENINF_1_FIFO_FULL 331 +-#define CMDQ_EVENT_SENINF_2_FIFO_FULL 332 +-#define CMDQ_EVENT_SENINF_3_FIFO_FULL 333 +-#define CMDQ_EVENT_SENINF_4_FIFO_FULL 334 +-#define CMDQ_EVENT_SENINF_5_FIFO_FULL 335 +-#define CMDQ_EVENT_SENINF_6_FIFO_FULL 336 +-#define CMDQ_EVENT_SENINF_7_FIFO_FULL 337 +-#define CMDQ_EVENT_TG_OVRUN_A_INT_DLY 338 +-#define CMDQ_EVENT_TG_OVRUN_B_INT_DLY 339 +-#define CMDQ_EVENT_TG_OVRUN_C_INT 340 +-#define CMDQ_EVENT_TG_GRABERR_A_INT_DLY 341 +-#define CMDQ_EVENT_TG_GRABERR_B_INT_DLY 342 +-#define CMDQ_EVENT_TG_GRABERR_C_INT 343 +-#define CMDQ_EVENT_CQ_VR_SNAP_A_INT_DLY 344 +-#define CMDQ_EVENT_CQ_VR_SNAP_B_INT_DLY 345 +-#define CMDQ_EVENT_CQ_VR_SNAP_C_INT 346 +-#define CMDQ_EVENT_DMA_R1_ERROR_A_INT_DLY 347 +-#define CMDQ_EVENT_DMA_R1_ERROR_B_INT_DLY 348 +-#define CMDQ_EVENT_DMA_R1_ERROR_C_INT 349 +-#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_0 353 +-#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_1 354 +-#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_2 355 +-#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_3 356 +-#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_0 385 +-#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_1 386 +-#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_2 387 +-#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_3 388 +-#define CMDQ_EVENT_VDEC_EVENT_0 416 +-#define CMDQ_EVENT_VDEC_EVENT_1 417 +-#define CMDQ_EVENT_VDEC_EVENT_2 418 +-#define CMDQ_EVENT_VDEC_EVENT_3 419 +-#define CMDQ_EVENT_VDEC_EVENT_4 420 +-#define CMDQ_EVENT_VDEC_EVENT_5 421 +-#define CMDQ_EVENT_VDEC_EVENT_6 422 +-#define CMDQ_EVENT_VDEC_EVENT_7 423 +-#define CMDQ_EVENT_VDEC_EVENT_8 424 +-#define CMDQ_EVENT_VDEC_EVENT_9 425 +-#define CMDQ_EVENT_VDEC_EVENT_10 426 +-#define CMDQ_EVENT_VDEC_EVENT_11 427 +-#define CMDQ_EVENT_VDEC_EVENT_12 428 +-#define CMDQ_EVENT_VDEC_EVENT_13 429 +-#define CMDQ_EVENT_VDEC_EVENT_14 430 +-#define CMDQ_EVENT_VDEC_EVENT_15 431 +-#define CMDQ_EVENT_FDVT_DONE 449 +-#define CMDQ_EVENT_FE_DONE 450 +-#define CMDQ_EVENT_RSC_EOF 451 +-#define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 452 +-#define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 453 +-#define CMDQ_EVENT_DSI0_TE_INFRA 898 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/gce/mt8173-gce.h b/scripts/dtc/include-prefixes/dt-bindings/gce/mt8173-gce.h +deleted file mode 100644 +index ffcf94ba96c6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/gce/mt8173-gce.h ++++ /dev/null +@@ -1,44 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2018 MediaTek Inc. +- * Author: Houlong Wei +- * +- */ +- +-#ifndef _DT_BINDINGS_GCE_MT8173_H +-#define _DT_BINDINGS_GCE_MT8173_H +- +-/* GCE HW thread priority */ +-#define CMDQ_THR_PRIO_LOWEST 0 +-#define CMDQ_THR_PRIO_HIGHEST 1 +- +-/* GCE SUBSYS */ +-#define SUBSYS_1400XXXX 1 +-#define SUBSYS_1401XXXX 2 +-#define SUBSYS_1402XXXX 3 +- +-/* GCE HW EVENT */ +-#define CMDQ_EVENT_DISP_OVL0_SOF 11 +-#define CMDQ_EVENT_DISP_OVL1_SOF 12 +-#define CMDQ_EVENT_DISP_RDMA0_SOF 13 +-#define CMDQ_EVENT_DISP_RDMA1_SOF 14 +-#define CMDQ_EVENT_DISP_RDMA2_SOF 15 +-#define CMDQ_EVENT_DISP_WDMA0_SOF 16 +-#define CMDQ_EVENT_DISP_WDMA1_SOF 17 +-#define CMDQ_EVENT_DISP_OVL0_EOF 39 +-#define CMDQ_EVENT_DISP_OVL1_EOF 40 +-#define CMDQ_EVENT_DISP_RDMA0_EOF 41 +-#define CMDQ_EVENT_DISP_RDMA1_EOF 42 +-#define CMDQ_EVENT_DISP_RDMA2_EOF 43 +-#define CMDQ_EVENT_DISP_WDMA0_EOF 44 +-#define CMDQ_EVENT_DISP_WDMA1_EOF 45 +-#define CMDQ_EVENT_MUTEX0_STREAM_EOF 53 +-#define CMDQ_EVENT_MUTEX1_STREAM_EOF 54 +-#define CMDQ_EVENT_MUTEX2_STREAM_EOF 55 +-#define CMDQ_EVENT_MUTEX3_STREAM_EOF 56 +-#define CMDQ_EVENT_MUTEX4_STREAM_EOF 57 +-#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 63 +-#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 64 +-#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 65 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/gce/mt8183-gce.h b/scripts/dtc/include-prefixes/dt-bindings/gce/mt8183-gce.h +deleted file mode 100644 +index 29c967476f73..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/gce/mt8183-gce.h ++++ /dev/null +@@ -1,175 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2019 MediaTek Inc. +- * Author: Bibby Hsieh +- * +- */ +- +-#ifndef _DT_BINDINGS_GCE_MT8183_H +-#define _DT_BINDINGS_GCE_MT8183_H +- +-#define CMDQ_NO_TIMEOUT 0xffffffff +- +-/* GCE HW thread priority */ +-#define CMDQ_THR_PRIO_LOWEST 0 +-#define CMDQ_THR_PRIO_HIGHEST 1 +- +-/* GCE SUBSYS */ +-#define SUBSYS_1300XXXX 0 +-#define SUBSYS_1400XXXX 1 +-#define SUBSYS_1401XXXX 2 +-#define SUBSYS_1402XXXX 3 +-#define SUBSYS_1502XXXX 4 +-#define SUBSYS_1880XXXX 5 +-#define SUBSYS_1881XXXX 6 +-#define SUBSYS_1882XXXX 7 +-#define SUBSYS_1883XXXX 8 +-#define SUBSYS_1884XXXX 9 +-#define SUBSYS_1000XXXX 10 +-#define SUBSYS_1001XXXX 11 +-#define SUBSYS_1002XXXX 12 +-#define SUBSYS_1003XXXX 13 +-#define SUBSYS_1004XXXX 14 +-#define SUBSYS_1005XXXX 15 +-#define SUBSYS_1020XXXX 16 +-#define SUBSYS_1028XXXX 17 +-#define SUBSYS_1700XXXX 18 +-#define SUBSYS_1701XXXX 19 +-#define SUBSYS_1702XXXX 20 +-#define SUBSYS_1703XXXX 21 +-#define SUBSYS_1800XXXX 22 +-#define SUBSYS_1801XXXX 23 +-#define SUBSYS_1802XXXX 24 +-#define SUBSYS_1804XXXX 25 +-#define SUBSYS_1805XXXX 26 +-#define SUBSYS_1808XXXX 27 +-#define SUBSYS_180aXXXX 28 +-#define SUBSYS_180bXXXX 29 +- +-#define CMDQ_EVENT_DISP_RDMA0_SOF 0 +-#define CMDQ_EVENT_DISP_RDMA1_SOF 1 +-#define CMDQ_EVENT_MDP_RDMA0_SOF 2 +-#define CMDQ_EVENT_MDP_RSZ0_SOF 4 +-#define CMDQ_EVENT_MDP_RSZ1_SOF 5 +-#define CMDQ_EVENT_MDP_TDSHP_SOF 6 +-#define CMDQ_EVENT_MDP_WROT0_SOF 7 +-#define CMDQ_EVENT_MDP_WDMA0_SOF 8 +-#define CMDQ_EVENT_DISP_OVL0_SOF 9 +-#define CMDQ_EVENT_DISP_OVL0_2L_SOF 10 +-#define CMDQ_EVENT_DISP_OVL1_2L_SOF 11 +-#define CMDQ_EVENT_DISP_WDMA0_SOF 12 +-#define CMDQ_EVENT_DISP_COLOR0_SOF 13 +-#define CMDQ_EVENT_DISP_CCORR0_SOF 14 +-#define CMDQ_EVENT_DISP_AAL0_SOF 15 +-#define CMDQ_EVENT_DISP_GAMMA0_SOF 16 +-#define CMDQ_EVENT_DISP_DITHER0_SOF 17 +-#define CMDQ_EVENT_DISP_PWM0_SOF 18 +-#define CMDQ_EVENT_DISP_DSI0_SOF 19 +-#define CMDQ_EVENT_DISP_DPI0_SOF 20 +-#define CMDQ_EVENT_DISP_RSZ_SOF 22 +-#define CMDQ_EVENT_MDP_AAL_SOF 23 +-#define CMDQ_EVENT_MDP_CCORR_SOF 24 +-#define CMDQ_EVENT_DISP_DBI_SOF 25 +-#define CMDQ_EVENT_DISP_RDMA0_EOF 26 +-#define CMDQ_EVENT_DISP_RDMA1_EOF 27 +-#define CMDQ_EVENT_MDP_RDMA0_EOF 28 +-#define CMDQ_EVENT_MDP_RSZ0_EOF 30 +-#define CMDQ_EVENT_MDP_RSZ1_EOF 31 +-#define CMDQ_EVENT_MDP_TDSHP_EOF 32 +-#define CMDQ_EVENT_MDP_WROT0_EOF 33 +-#define CMDQ_EVENT_MDP_WDMA0_EOF 34 +-#define CMDQ_EVENT_DISP_OVL0_EOF 35 +-#define CMDQ_EVENT_DISP_OVL0_2L_EOF 36 +-#define CMDQ_EVENT_DISP_OVL1_2L_EOF 37 +-#define CMDQ_EVENT_DISP_WDMA0_EOF 38 +-#define CMDQ_EVENT_DISP_COLOR0_EOF 39 +-#define CMDQ_EVENT_DISP_CCORR0_EOF 40 +-#define CMDQ_EVENT_DISP_AAL0_EOF 41 +-#define CMDQ_EVENT_DISP_GAMMA0_EOF 42 +-#define CMDQ_EVENT_DISP_DITHER0_EOF 43 +-#define CMDQ_EVENT_DSI0_EOF 44 +-#define CMDQ_EVENT_DPI0_EOF 45 +-#define CMDQ_EVENT_DISP_RSZ_EOF 47 +-#define CMDQ_EVENT_MDP_AAL_EOF 48 +-#define CMDQ_EVENT_MDP_CCORR_EOF 49 +-#define CMDQ_EVENT_DBI_EOF 50 +-#define CMDQ_EVENT_MUTEX_STREAM_DONE0 130 +-#define CMDQ_EVENT_MUTEX_STREAM_DONE1 131 +-#define CMDQ_EVENT_MUTEX_STREAM_DONE2 132 +-#define CMDQ_EVENT_MUTEX_STREAM_DONE3 133 +-#define CMDQ_EVENT_MUTEX_STREAM_DONE4 134 +-#define CMDQ_EVENT_MUTEX_STREAM_DONE5 135 +-#define CMDQ_EVENT_MUTEX_STREAM_DONE6 136 +-#define CMDQ_EVENT_MUTEX_STREAM_DONE7 137 +-#define CMDQ_EVENT_MUTEX_STREAM_DONE8 138 +-#define CMDQ_EVENT_MUTEX_STREAM_DONE9 139 +-#define CMDQ_EVENT_MUTEX_STREAM_DONE10 140 +-#define CMDQ_EVENT_MUTEX_STREAM_DONE11 141 +-#define CMDQ_EVENT_DISP_RDMA0_BUF_UNDERRUN_EVEN 142 +-#define CMDQ_EVENT_DISP_RDMA1_BUF_UNDERRUN_EVEN 143 +-#define CMDQ_EVENT_DSI0_TE_EVENT 144 +-#define CMDQ_EVENT_DSI0_IRQ_EVENT 145 +-#define CMDQ_EVENT_DSI0_DONE_EVENT 146 +-#define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE 150 +-#define CMDQ_EVENT_MDP_WDMA_SW_RST_DONE 151 +-#define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE 152 +-#define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE 154 +-#define CMDQ_EVENT_DISP_OVL0_FRAME_RST_DONE_PULE 155 +-#define CMDQ_EVENT_DISP_OVL0_2L_FRAME_RST_DONE_ULSE 156 +-#define CMDQ_EVENT_DISP_OVL1_2L_FRAME_RST_DONE_ULSE 157 +-#define CMDQ_EVENT_ISP_FRAME_DONE_P2_0 257 +-#define CMDQ_EVENT_ISP_FRAME_DONE_P2_1 258 +-#define CMDQ_EVENT_ISP_FRAME_DONE_P2_2 259 +-#define CMDQ_EVENT_ISP_FRAME_DONE_P2_3 260 +-#define CMDQ_EVENT_ISP_FRAME_DONE_P2_4 261 +-#define CMDQ_EVENT_ISP_FRAME_DONE_P2_5 262 +-#define CMDQ_EVENT_ISP_FRAME_DONE_P2_6 263 +-#define CMDQ_EVENT_ISP_FRAME_DONE_P2_7 264 +-#define CMDQ_EVENT_ISP_FRAME_DONE_P2_8 265 +-#define CMDQ_EVENT_ISP_FRAME_DONE_P2_9 266 +-#define CMDQ_EVENT_ISP_FRAME_DONE_P2_10 267 +-#define CMDQ_EVENT_ISP_FRAME_DONE_P2_11 268 +-#define CMDQ_EVENT_ISP_FRAME_DONE_P2_12 269 +-#define CMDQ_EVENT_ISP_FRAME_DONE_P2_13 270 +-#define CMDQ_EVENT_ISP_FRAME_DONE_P2_14 271 +-#define CMDQ_EVENT_ISP_FRAME_DONE_P2_15 272 +-#define CMDQ_EVENT_ISP_FRAME_DONE_P2_16 273 +-#define CMDQ_EVENT_ISP_FRAME_DONE_P2_17 274 +-#define CMDQ_EVENT_ISP_FRAME_DONE_P2_18 275 +-#define CMDQ_EVENT_AMD_FRAME_DONE 276 +-#define CMDQ_EVENT_DVE_DONE 277 +-#define CMDQ_EVENT_WMFE_DONE 278 +-#define CMDQ_EVENT_RSC_DONE 279 +-#define CMDQ_EVENT_MFB_DONE 280 +-#define CMDQ_EVENT_WPE_A_DONE 281 +-#define CMDQ_EVENT_SPE_B_DONE 282 +-#define CMDQ_EVENT_OCC_DONE 283 +-#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 289 +-#define CMDQ_EVENT_JPG_ENC_CMDQ_DONE 290 +-#define CMDQ_EVENT_JPG_DEC_CMDQ_DONE 291 +-#define CMDQ_EVENT_VENC_CMDQ_MB_DONE 292 +-#define CMDQ_EVENT_VENC_CMDQ_128BYTE_DONE 293 +-#define CMDQ_EVENT_ISP_FRAME_DONE_A 321 +-#define CMDQ_EVENT_ISP_FRAME_DONE_B 322 +-#define CMDQ_EVENT_CAMSV0_PASS1_DONE 323 +-#define CMDQ_EVENT_CAMSV1_PASS1_DONE 324 +-#define CMDQ_EVENT_CAMSV2_PASS1_DONE 325 +-#define CMDQ_EVENT_TSF_DONE 326 +-#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 327 +-#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 328 +-#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 329 +-#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 330 +-#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 331 +-#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 332 +-#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 333 +-#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 334 +-#define CMDQ_EVENT_IPU_CORE0_DONE0 353 +-#define CMDQ_EVENT_IPU_CORE0_DONE1 354 +-#define CMDQ_EVENT_IPU_CORE0_DONE2 355 +-#define CMDQ_EVENT_IPU_CORE0_DONE3 356 +-#define CMDQ_EVENT_IPU_CORE1_DONE0 385 +-#define CMDQ_EVENT_IPU_CORE1_DONE1 386 +-#define CMDQ_EVENT_IPU_CORE1_DONE2 387 +-#define CMDQ_EVENT_IPU_CORE1_DONE3 388 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/gce/mt8192-gce.h b/scripts/dtc/include-prefixes/dt-bindings/gce/mt8192-gce.h +deleted file mode 100644 +index 9e5a0eb040a0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/gce/mt8192-gce.h ++++ /dev/null +@@ -1,335 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2020 MediaTek Inc. +- * Author: Yongqiang Niu +- */ +- +-#ifndef _DT_BINDINGS_GCE_MT8192_H +-#define _DT_BINDINGS_GCE_MT8192_H +- +-/* assign timeout 0 also means default */ +-#define CMDQ_NO_TIMEOUT 0xffffffff +-#define CMDQ_TIMEOUT_DEFAULT 1000 +- +-/* GCE thread priority */ +-#define CMDQ_THR_PRIO_LOWEST 0 +-#define CMDQ_THR_PRIO_1 1 +-#define CMDQ_THR_PRIO_2 2 +-#define CMDQ_THR_PRIO_3 3 +-#define CMDQ_THR_PRIO_4 4 +-#define CMDQ_THR_PRIO_5 5 +-#define CMDQ_THR_PRIO_6 6 +-#define CMDQ_THR_PRIO_HIGHEST 7 +- +-/* CPR count in 32bit register */ +-#define GCE_CPR_COUNT 1312 +- +-/* GCE subsys table */ +-#define SUBSYS_1300XXXX 0 +-#define SUBSYS_1400XXXX 1 +-#define SUBSYS_1401XXXX 2 +-#define SUBSYS_1402XXXX 3 +-#define SUBSYS_1502XXXX 4 +-#define SUBSYS_1880XXXX 5 +-#define SUBSYS_1881XXXX 6 +-#define SUBSYS_1882XXXX 7 +-#define SUBSYS_1883XXXX 8 +-#define SUBSYS_1884XXXX 9 +-#define SUBSYS_1000XXXX 10 +-#define SUBSYS_1001XXXX 11 +-#define SUBSYS_1002XXXX 12 +-#define SUBSYS_1003XXXX 13 +-#define SUBSYS_1004XXXX 14 +-#define SUBSYS_1005XXXX 15 +-#define SUBSYS_1020XXXX 16 +-#define SUBSYS_1028XXXX 17 +-#define SUBSYS_1700XXXX 18 +-#define SUBSYS_1701XXXX 19 +-#define SUBSYS_1702XXXX 20 +-#define SUBSYS_1703XXXX 21 +-#define SUBSYS_1800XXXX 22 +-#define SUBSYS_1801XXXX 23 +-#define SUBSYS_1802XXXX 24 +-#define SUBSYS_1804XXXX 25 +-#define SUBSYS_1805XXXX 26 +-#define SUBSYS_1808XXXX 27 +-#define SUBSYS_180aXXXX 28 +-#define SUBSYS_180bXXXX 29 +- +-#define CMDQ_EVENT_VDEC_LAT_SOF_0 0 +-#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_0 1 +-#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_1 2 +-#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_2 3 +-#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_3 4 +-#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_4 5 +-#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_5 6 +-#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_6 7 +-#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_0 8 +-#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_1 9 +-#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_2 10 +-#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_3 11 +-#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_4 12 +-#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_5 13 +-#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_6 14 +-#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_7 15 +- +-#define CMDQ_EVENT_ISP_FRAME_DONE_A 65 +-#define CMDQ_EVENT_ISP_FRAME_DONE_B 66 +-#define CMDQ_EVENT_ISP_FRAME_DONE_C 67 +-#define CMDQ_EVENT_CAMSV0_PASS1_DONE 68 +-#define CMDQ_EVENT_CAMSV02_PASS1_DONE 69 +-#define CMDQ_EVENT_CAMSV1_PASS1_DONE 70 +-#define CMDQ_EVENT_CAMSV2_PASS1_DONE 71 +-#define CMDQ_EVENT_CAMSV3_PASS1_DONE 72 +-#define CMDQ_EVENT_MRAW_0_PASS1_DONE 73 +-#define CMDQ_EVENT_MRAW_1_PASS1_DONE 74 +-#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 75 +-#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 76 +-#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 77 +-#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 78 +-#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 79 +-#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 80 +-#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 81 +-#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 82 +-#define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL 83 +-#define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL 84 +-#define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL 85 +-#define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL 86 +-#define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL 87 +-#define CMDQ_EVENT_TG_OVRUN_A_INT 88 +-#define CMDQ_EVENT_DMA_R1_ERROR_A_INT 89 +-#define CMDQ_EVENT_TG_OVRUN_B_INT 90 +-#define CMDQ_EVENT_DMA_R1_ERROR_B_INT 91 +-#define CMDQ_EVENT_TG_OVRUN_C_INT 92 +-#define CMDQ_EVENT_DMA_R1_ERROR_C_INT 93 +-#define CMDQ_EVENT_TG_OVRUN_M0_INT 94 +-#define CMDQ_EVENT_DMA_R1_ERROR_M0_INT 95 +-#define CMDQ_EVENT_TG_GRABERR_M0_INT 96 +-#define CMDQ_EVENT_TG_GRABERR_M1_INT 97 +-#define CMDQ_EVENT_TG_GRABERR_A_INT 98 +-#define CMDQ_EVENT_CQ_VR_SNAP_A_INT 99 +-#define CMDQ_EVENT_TG_GRABERR_B_INT 100 +-#define CMDQ_EVENT_CQ_VR_SNAP_B_INT 101 +-#define CMDQ_EVENT_TG_GRABERR_C_INT 102 +-#define CMDQ_EVENT_CQ_VR_SNAP_C_INT 103 +- +-#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 129 +-#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 130 +-#define CMDQ_EVENT_JPGENC_CMDQ_DONE 131 +-#define CMDQ_EVENT_VENC_CMDQ_MB_DONE 132 +-#define CMDQ_EVENT_VENC_CMDQ_128BYTE_CNT_DONE 133 +-#define CMDQ_EVENT_VENC_C0_CMDQ_WP_2ND_STAGE_DONE 134 +-#define CMDQ_EVENT_VENC_C0_CMDQ_WP_3RD_STAGE_DONE 135 +-#define CMDQ_EVENT_VENC_CMDQ_PPS_DONE 136 +-#define CMDQ_EVENT_VENC_CMDQ_SPS_DONE 137 +-#define CMDQ_EVENT_VENC_CMDQ_VPS_DONE 138 +- +-#define CMDQ_EVENT_VDEC_CORE0_SOF_0 160 +-#define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_0 161 +-#define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_1 162 +-#define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_2 163 +-#define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_3 164 +-#define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_4 165 +-#define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_5 166 +-#define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_6 167 +-#define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_0 168 +-#define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_1 169 +-#define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_2 170 +-#define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_3 171 +-#define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_4 172 +-#define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_5 173 +-#define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_6 174 +-#define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_7 175 +-#define CMDQ_EVENT_FDVT_DONE 177 +-#define CMDQ_EVENT_FE_DONE 178 +-#define CMDQ_EVENT_RSC_DONE 179 +-#define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 180 +-#define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 181 +- +-#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_0 193 +-#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_1 194 +-#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_2 195 +-#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_3 196 +-#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_4 197 +-#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_5 198 +-#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_6 199 +-#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_7 200 +-#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_8 201 +-#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_9 202 +-#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_10 203 +-#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_11 204 +-#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_12 205 +-#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_13 206 +-#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_14 207 +-#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_15 208 +-#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_16 209 +-#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_17 210 +-#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_18 211 +-#define CMDQ_EVENT_IMG2_DIP_DMA_ERR_EVENT 212 +-#define CMDQ_EVENT_IMG2_AMD_FRAME_DONE 213 +-#define CMDQ_EVENT_IMG2_MFB_DONE_LINK_MISC 214 +-#define CMDQ_EVENT_IMG2_WPE_A_DONE_LINK_MISC 215 +-#define CMDQ_EVENT_IMG2_MSS_DONE_LINK_MISC 216 +- +-#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_0 225 +-#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_1 226 +-#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_2 227 +-#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_3 228 +-#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_4 229 +-#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_5 230 +-#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_6 231 +-#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_7 232 +-#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_8 233 +-#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_9 234 +-#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_10 235 +-#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_11 236 +-#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_12 237 +-#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_13 238 +-#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_14 239 +-#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_15 240 +-#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_16 241 +-#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_17 242 +-#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_18 243 +-#define CMDQ_EVENT_IMG1_DIP_DMA_ERR_EVENT 244 +-#define CMDQ_EVENT_IMG1_AMD_FRAME_DONE 245 +-#define CMDQ_EVENT_IMG1_MFB_DONE_LINK_MISC 246 +-#define CMDQ_EVENT_IMG1_WPE_A_DONE_LINK_MISC 247 +-#define CMDQ_EVENT_IMG1_MSS_DONE_LINK_MISC 248 +- +-#define CMDQ_EVENT_MDP_RDMA0_SOF 256 +-#define CMDQ_EVENT_MDP_RDMA1_SOF 257 +-#define CMDQ_EVENT_MDP_AAL0_SOF 258 +-#define CMDQ_EVENT_MDP_AAL1_SOF 259 +-#define CMDQ_EVENT_MDP_HDR0_SOF 260 +-#define CMDQ_EVENT_MDP_HDR1_SOF 261 +-#define CMDQ_EVENT_MDP_RSZ0_SOF 262 +-#define CMDQ_EVENT_MDP_RSZ1_SOF 263 +-#define CMDQ_EVENT_MDP_WROT0_SOF 264 +-#define CMDQ_EVENT_MDP_WROT1_SOF 265 +-#define CMDQ_EVENT_MDP_TDSHP0_SOF 266 +-#define CMDQ_EVENT_MDP_TDSHP1_SOF 267 +-#define CMDQ_EVENT_IMG_DL_RELAY0_SOF 268 +-#define CMDQ_EVENT_IMG_DL_RELAY1_SOF 269 +-#define CMDQ_EVENT_MDP_COLOR0_SOF 270 +-#define CMDQ_EVENT_MDP_COLOR1_SOF 271 +-#define CMDQ_EVENT_MDP_WROT1_FRAME_DONE 290 +-#define CMDQ_EVENT_MDP_WROT0_FRAME_DONE 291 +-#define CMDQ_EVENT_MDP_TDSHP1_FRAME_DONE 294 +-#define CMDQ_EVENT_MDP_TDSHP0_FRAME_DONE 295 +-#define CMDQ_EVENT_MDP_RSZ1_FRAME_DONE 302 +-#define CMDQ_EVENT_MDP_RSZ0_FRAME_DONE 303 +-#define CMDQ_EVENT_MDP_RDMA1_FRAME_DONE 306 +-#define CMDQ_EVENT_MDP_RDMA0_FRAME_DONE 307 +-#define CMDQ_EVENT_MDP_HDR1_FRAME_DONE 308 +-#define CMDQ_EVENT_MDP_HDR0_FRAME_DONE 309 +-#define CMDQ_EVENT_MDP_COLOR1_FRAME_DONE 312 +-#define CMDQ_EVENT_MDP_COLOR0_FRAME_DONE 313 +-#define CMDQ_EVENT_MDP_AAL1_FRAME_DONE 316 +-#define CMDQ_EVENT_MDP_AAL0_FRAME_DONE 317 +-#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_0 320 +-#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1 321 +-#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_2 322 +-#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_3 323 +-#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_4 324 +-#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_5 325 +-#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_6 326 +-#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_7 327 +-#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_8 328 +-#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_9 329 +-#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_10 330 +-#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_11 331 +-#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_12 332 +-#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_13 333 +-#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_14 334 +-#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_15 335 +-#define CMDQ_EVENT_MDP_WROT1_SW_RST_DONE_ENG_EVENT 338 +-#define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE_ENG_EVENT 339 +-#define CMDQ_EVENT_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 342 +-#define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 343 +- +-#define CMDQ_EVENT_DISP_OVL0_SOF 384 +-#define CMDQ_EVENT_DISP_OVL0_2L_SOF 385 +-#define CMDQ_EVENT_DISP_RDMA0_SOF 386 +-#define CMDQ_EVENT_DISP_RSZ0_SOF 387 +-#define CMDQ_EVENT_DISP_COLOR0_SOF 388 +-#define CMDQ_EVENT_DISP_CCORR0_SOF 389 +-#define CMDQ_EVENT_DISP_AAL0_SOF 390 +-#define CMDQ_EVENT_DISP_GAMMA0_SOF 391 +-#define CMDQ_EVENT_DISP_POSTMASK0_SOF 392 +-#define CMDQ_EVENT_DISP_DITHER0_SOF 393 +-#define CMDQ_EVENT_DISP_DSC_WRAP0_CORE0_SOF 394 +-#define CMDQ_EVENT_DISP_DSC_WRAP0_CORE1_SOF 395 +-#define CMDQ_EVENT_DSI0_SOF 396 +-#define CMDQ_EVENT_DISP_WDMA0_SOF 397 +-#define CMDQ_EVENT_DISP_UFBC_WDMA0_SOF 398 +-#define CMDQ_EVENT_DISP_PWM0_SOF 399 +-#define CMDQ_EVENT_DISP_OVL2_2L_SOF 400 +-#define CMDQ_EVENT_DISP_RDMA4_SOF 401 +-#define CMDQ_EVENT_DISP_DPI0_SOF 402 +-#define CMDQ_EVENT_MDP_RDMA4_SOF 403 +-#define CMDQ_EVENT_MDP_HDR4_SOF 404 +-#define CMDQ_EVENT_MDP_RSZ4_SOF 405 +-#define CMDQ_EVENT_MDP_AAL4_SOF 406 +-#define CMDQ_EVENT_MDP_TDSHP4_SOF 407 +-#define CMDQ_EVENT_MDP_COLOR4_SOF 408 +-#define CMDQ_EVENT_DISP_Y2R0_SOF 409 +-#define CMDQ_EVENT_MDP_TDSHP4_FRAME_DONE 410 +-#define CMDQ_EVENT_MDP_RSZ4_FRAME_DONE 411 +-#define CMDQ_EVENT_MDP_RDMA4_FRAME_DONE 412 +-#define CMDQ_EVENT_MDP_HDR4_FRAME_DONE 413 +-#define CMDQ_EVENT_MDP_COLOR4_FRAME_DONE 414 +-#define CMDQ_EVENT_MDP_AAL4_FRAME_DONE 415 +-#define CMDQ_EVENT_DSI0_FRAME_DONE 416 +-#define CMDQ_EVENT_DISP_WDMA0_FRAME_DONE 417 +-#define CMDQ_EVENT_DISP_UFBC_WDMA0_FRAME_DONE 418 +-#define CMDQ_EVENT_DISP_RSZ0_FRAME_DONE 419 +-#define CMDQ_EVENT_DISP_RDMA4_FRAME_DONE 420 +-#define CMDQ_EVENT_DISP_RDMA0_FRAME_DONE 421 +-#define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 422 +-#define CMDQ_EVENT_DISP_OVL2_2L_FRAME_DONE 423 +-#define CMDQ_EVENT_DISP_OVL0_FRAME_DONE 424 +-#define CMDQ_EVENT_DISP_OVL0_2L_FRAME_DONE 425 +-#define CMDQ_EVENT_DISP_GAMMA0_FRAME_DONE 426 +-#define CMDQ_EVENT_DISP_DSC_WRAP0_CORE1_FRAME_DONE 427 +-#define CMDQ_EVENT_DISP_DSC_WRAP0_CORE0_FRAME_DONE 428 +-#define CMDQ_EVENT_DISP_DPI0_FRAME_DONE 429 +-#define CMDQ_EVENT_DISP_DITHER0_FRAME_DONE 430 +-#define CMDQ_EVENT_DISP_COLOR0_FRAME_DONE 431 +-#define CMDQ_EVENT_DISP_CCORR0_FRAME_DONE 432 +-#define CMDQ_EVENT_DISP_AAL0_FRAME_DONE 433 +-#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0 434 +-#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1 435 +-#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_2 436 +-#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_3 437 +-#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_4 438 +-#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_5 439 +-#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_6 440 +-#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_7 441 +-#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_8 442 +-#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_9 443 +-#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_10 444 +-#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_11 445 +-#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_12 446 +-#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_13 447 +-#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_14 448 +-#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_15 449 +-#define CMDQ_EVENT_DSI0_TE_ENG_EVENT 450 +-#define CMDQ_EVENT_DSI0_IRQ_ENG_EVENT 451 +-#define CMDQ_EVENT_DSI0_DONE_ENG_EVENT 452 +-#define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 453 +-#define CMDQ_EVENT_DISP_SMIASSERT_ENG_EVENT 454 +-#define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE_ENG_EVENT 455 +-#define CMDQ_EVENT_DISP_OVL2_2L_RST_DONE_ENG_EVENT 456 +-#define CMDQ_EVENT_DISP_OVL0_RST_DONE_ENG_EVENT 457 +-#define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE_ENG_EVENT 458 +-#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_0 459 +-#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_1 460 +-#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_2 461 +-#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_3 462 +-#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_4 463 +-#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_5 464 +-#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_6 465 +-#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_7 466 +-#define CMDQ_MAX_HW_EVENT 512 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/gce/mt8195-gce.h b/scripts/dtc/include-prefixes/dt-bindings/gce/mt8195-gce.h +deleted file mode 100644 +index dcfb302b8a5b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/gce/mt8195-gce.h ++++ /dev/null +@@ -1,812 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2021 MediaTek Inc. +- * Author: Jason-JH Lin +- */ +- +-#ifndef _DT_BINDINGS_GCE_MT8195_H +-#define _DT_BINDINGS_GCE_MT8195_H +- +-/* assign timeout 0 also means default */ +-#define CMDQ_NO_TIMEOUT 0xffffffff +-#define CMDQ_TIMEOUT_DEFAULT 1000 +- +-/* GCE thread priority */ +-#define CMDQ_THR_PRIO_LOWEST 0 +-#define CMDQ_THR_PRIO_1 1 +-#define CMDQ_THR_PRIO_2 2 +-#define CMDQ_THR_PRIO_3 3 +-#define CMDQ_THR_PRIO_4 4 +-#define CMDQ_THR_PRIO_5 5 +-#define CMDQ_THR_PRIO_6 6 +-#define CMDQ_THR_PRIO_HIGHEST 7 +- +-/* CPR count in 32bit register */ +-#define GCE_CPR_COUNT 1312 +- +-/* GCE subsys table */ +-#define SUBSYS_1400XXXX 0 +-#define SUBSYS_1401XXXX 1 +-#define SUBSYS_1402XXXX 2 +-#define SUBSYS_1c00XXXX 3 +-#define SUBSYS_1c01XXXX 4 +-#define SUBSYS_1c02XXXX 5 +-#define SUBSYS_1c10XXXX 6 +-#define SUBSYS_1c11XXXX 7 +-#define SUBSYS_1c12XXXX 8 +-#define SUBSYS_14f0XXXX 9 +-#define SUBSYS_14f1XXXX 10 +-#define SUBSYS_14f2XXXX 11 +-#define SUBSYS_1800XXXX 12 +-#define SUBSYS_1801XXXX 13 +-#define SUBSYS_1802XXXX 14 +-#define SUBSYS_1803XXXX 15 +-#define SUBSYS_1032XXXX 16 +-#define SUBSYS_1033XXXX 17 +-#define SUBSYS_1600XXXX 18 +-#define SUBSYS_1601XXXX 19 +-#define SUBSYS_14e0XXXX 20 +-#define SUBSYS_1c20XXXX 21 +-#define SUBSYS_1c30XXXX 22 +-#define SUBSYS_1c40XXXX 23 +-#define SUBSYS_1c50XXXX 24 +-#define SUBSYS_1c60XXXX 25 +- +-/* GCE General Purpose Register (GPR) support */ +-#define GCE_GPR_R00 0x0 +-#define GCE_GPR_R01 0x1 +-#define GCE_GPR_R02 0x2 +-#define GCE_GPR_R03 0x3 +-#define GCE_GPR_R04 0x4 +-#define GCE_GPR_R05 0x5 +-#define GCE_GPR_R06 0x6 +-#define GCE_GPR_R07 0x7 +-#define GCE_GPR_R08 0x8 +-#define GCE_GPR_R09 0x9 +-#define GCE_GPR_R10 0xa +-#define GCE_GPR_R11 0xb +-#define GCE_GPR_R12 0xc +-#define GCE_GPR_R13 0xd +-#define GCE_GPR_R14 0xe +-#define GCE_GPR_R15 0xf +- +-/* GCE hw event id */ +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_0 1 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_1 2 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_2 3 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_3 4 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_4 5 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_5 6 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_6 7 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_7 8 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_8 9 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_9 10 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_10 11 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_11 12 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_12 13 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_13 14 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_14 15 +-#define CMDQ_EVENT_TRAW0_DMA_ERROR_INT 16 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_0 17 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_1 18 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_2 19 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_3 20 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_4 21 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_5 22 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_6 23 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_7 24 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_8 25 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_9 26 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_10 27 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_11 28 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_12 29 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_13 30 +-#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_14 31 +-#define CMDQ_EVENT_TRAW1_DMA_ERROR_INT 32 +- +-#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_0 65 +-#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_1 66 +-#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_2 67 +-#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_3 68 +-#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_4 69 +-#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_5 70 +-#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_6 71 +-#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_7 72 +-#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_8 73 +-#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_9 74 +-#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_10 75 +-#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_11 76 +-#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_12 77 +-#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_13 78 +-#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_14 79 +-#define CMDQ_EVENT_DIP0_DMA_ERR 80 +-#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_0 81 +-#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_1 82 +-#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_2 83 +-#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_3 84 +-#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_4 85 +-#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_5 86 +-#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_6 87 +-#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_7 88 +-#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_8 89 +-#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_9 90 +-#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_10 91 +-#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_11 92 +-#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_12 93 +-#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_13 94 +-#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_14 95 +-#define CMDQ_EVENT_PQA0_DMA_ERR 96 +-#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_0 97 +-#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_1 98 +-#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_2 99 +-#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_3 100 +-#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_4 101 +-#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_5 102 +-#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_6 103 +-#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_7 104 +-#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_8 105 +-#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_9 106 +-#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_10 107 +-#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_11 108 +-#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_12 109 +-#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_13 110 +-#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_14 111 +-#define CMDQ_EVENT_PQB0_DMA_ERR 112 +-#define CMDQ_EVENT_DIP0_DUMMY_0 113 +-#define CMDQ_EVENT_DIP0_DUMMY_1 114 +-#define CMDQ_EVENT_DIP0_DUMMY_2 115 +-#define CMDQ_EVENT_DIP0_DUMMY_3 116 +-#define CMDQ_EVENT_WPE0_EIS_GCE_FRAME_DONE 117 +-#define CMDQ_EVENT_WPE0_EIS_DONE_SYNC_OUT 118 +-#define CMDQ_EVENT_WPE0_TNR_GCE_FRAME_DONE 119 +-#define CMDQ_EVENT_WPE0_TNR_DONE_SYNC_OUT 120 +-#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_0 121 +-#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_1 122 +-#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_2 123 +-#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_3 124 +-#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_4 125 +-#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_5 126 +-#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_6 127 +-#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_7 128 +-#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_8 129 +-#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_9 130 +-#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_10 131 +-#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_11 132 +-#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_12 133 +-#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_13 134 +-#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_14 135 +-#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_0 136 +-#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_1 137 +-#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_2 138 +-#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_3 139 +-#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_4 140 +-#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_5 141 +-#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_6 142 +-#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_7 143 +-#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_8 144 +-#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_9 145 +-#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_10 146 +-#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_11 147 +-#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_12 148 +-#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_13 149 +-#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_14 150 +-#define CMDQ_EVENT_WPE0_DUMMY_0 151 +-#define CMDQ_EVENT_IMGSYS_IPE_DUMMY 152 +-#define CMDQ_EVENT_IMGSYS_IPE_FDVT_DONE 153 +-#define CMDQ_EVENT_IMGSYS_IPE_ME_DONE 154 +-#define CMDQ_EVENT_IMGSYS_IPE_DVS_DONE 155 +-#define CMDQ_EVENT_IMGSYS_IPE_DVP_DONE 156 +- +-#define CMDQ_EVENT_TPR_0 194 +-#define CMDQ_EVENT_TPR_1 195 +-#define CMDQ_EVENT_TPR_2 196 +-#define CMDQ_EVENT_TPR_3 197 +-#define CMDQ_EVENT_TPR_4 198 +-#define CMDQ_EVENT_TPR_5 199 +-#define CMDQ_EVENT_TPR_6 200 +-#define CMDQ_EVENT_TPR_7 201 +-#define CMDQ_EVENT_TPR_8 202 +-#define CMDQ_EVENT_TPR_9 203 +-#define CMDQ_EVENT_TPR_10 204 +-#define CMDQ_EVENT_TPR_11 205 +-#define CMDQ_EVENT_TPR_12 206 +-#define CMDQ_EVENT_TPR_13 207 +-#define CMDQ_EVENT_TPR_14 208 +-#define CMDQ_EVENT_TPR_15 209 +-#define CMDQ_EVENT_TPR_16 210 +-#define CMDQ_EVENT_TPR_17 211 +-#define CMDQ_EVENT_TPR_18 212 +-#define CMDQ_EVENT_TPR_19 213 +-#define CMDQ_EVENT_TPR_20 214 +-#define CMDQ_EVENT_TPR_21 215 +-#define CMDQ_EVENT_TPR_22 216 +-#define CMDQ_EVENT_TPR_23 217 +-#define CMDQ_EVENT_TPR_24 218 +-#define CMDQ_EVENT_TPR_25 219 +-#define CMDQ_EVENT_TPR_26 220 +-#define CMDQ_EVENT_TPR_27 221 +-#define CMDQ_EVENT_TPR_28 222 +-#define CMDQ_EVENT_TPR_29 223 +-#define CMDQ_EVENT_TPR_30 224 +-#define CMDQ_EVENT_TPR_31 225 +-#define CMDQ_EVENT_TPR_TIMEOUT_0 226 +-#define CMDQ_EVENT_TPR_TIMEOUT_1 227 +-#define CMDQ_EVENT_TPR_TIMEOUT_2 228 +-#define CMDQ_EVENT_TPR_TIMEOUT_3 229 +-#define CMDQ_EVENT_TPR_TIMEOUT_4 230 +-#define CMDQ_EVENT_TPR_TIMEOUT_5 231 +-#define CMDQ_EVENT_TPR_TIMEOUT_6 232 +-#define CMDQ_EVENT_TPR_TIMEOUT_7 233 +-#define CMDQ_EVENT_TPR_TIMEOUT_8 234 +-#define CMDQ_EVENT_TPR_TIMEOUT_9 235 +-#define CMDQ_EVENT_TPR_TIMEOUT_10 236 +-#define CMDQ_EVENT_TPR_TIMEOUT_11 237 +-#define CMDQ_EVENT_TPR_TIMEOUT_12 238 +-#define CMDQ_EVENT_TPR_TIMEOUT_13 239 +-#define CMDQ_EVENT_TPR_TIMEOUT_14 240 +-#define CMDQ_EVENT_TPR_TIMEOUT_15 241 +- +-#define CMDQ_EVENT_VPP0_MDP_RDMA_SOF 256 +-#define CMDQ_EVENT_VPP0_MDP_FG_SOF 257 +-#define CMDQ_EVENT_VPP0_STITCH_SOF 258 +-#define CMDQ_EVENT_VPP0_MDP_HDR_SOF 259 +-#define CMDQ_EVENT_VPP0_MDP_AAL_SOF 260 +-#define CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF 261 +-#define CMDQ_EVENT_VPP0_MDP_TDSHP_SOF 262 +-#define CMDQ_EVENT_VPP0_DISP_COLOR_SOF 263 +-#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_SOF 264 +-#define CMDQ_EVENT_VPP0_VPP_PADDING_IN_PADDING_SOF 265 +-#define CMDQ_EVENT_VPP0_MDP_TCC_IN_SOF 266 +-#define CMDQ_EVENT_VPP0_MDP_WROT_SOF 267 +- +-#define CMDQ_EVENT_VPP0_WARP0_MMSYS_TOP_RELAY_SOF_PRE 269 +-#define CMDQ_EVENT_VPP0_WARP1_MMSYS_TOP_RELAY_SOF_PRE 270 +-#define CMDQ_EVENT_VPP0_VPP1_MMSYS_TOP_RELAY_SOF 271 +-#define CMDQ_EVENT_VPP0_VPP1_IN_MMSYS_TOP_RELAY_SOF_PRE 272 +- +-#define CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE 288 +-#define CMDQ_EVENT_VPP0_MDP_FG_TILE_DONE 289 +-#define CMDQ_EVENT_VPP0_STITCH_FRAME_DONE 290 +-#define CMDQ_EVENT_VPP0_MDP_HDR_FRAME_DONE 291 +-#define CMDQ_EVENT_VPP0_MDP_AAL_FRAME_DONE 292 +-#define CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE 293 +-#define CMDQ_EVENT_VPP0_MDP_TDSHP_FRAME_DONE 294 +-#define CMDQ_EVENT_VPP0_DISP_COLOR_FRAME_DONE 295 +-#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_FRAME_DONE 296 +-#define CMDQ_EVENT_VPP0_VPP_PADDING_IN_PADDING_FRAME_DONE 297 +-#define CMDQ_EVENT_VPP0_MDP_TCC_TCC_FRAME_DONE 298 +-#define CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE 299 +- +-#define CMDQ_EVENT_VPP0_STREAM_DONE_0 320 +-#define CMDQ_EVENT_VPP0_STREAM_DONE_1 321 +-#define CMDQ_EVENT_VPP0_STREAM_DONE_2 322 +-#define CMDQ_EVENT_VPP0_STREAM_DONE_3 323 +-#define CMDQ_EVENT_VPP0_STREAM_DONE_4 324 +-#define CMDQ_EVENT_VPP0_STREAM_DONE_5 325 +-#define CMDQ_EVENT_VPP0_STREAM_DONE_6 326 +-#define CMDQ_EVENT_VPP0_STREAM_DONE_7 327 +-#define CMDQ_EVENT_VPP0_STREAM_DONE_8 328 +-#define CMDQ_EVENT_VPP0_STREAM_DONE_9 329 +-#define CMDQ_EVENT_VPP0_STREAM_DONE_10 330 +-#define CMDQ_EVENT_VPP0_STREAM_DONE_11 331 +-#define CMDQ_EVENT_VPP0_STREAM_DONE_12 332 +-#define CMDQ_EVENT_VPP0_STREAM_DONE_13 333 +-#define CMDQ_EVENT_VPP0_STREAM_DONE_14 334 +-#define CMDQ_EVENT_VPP0_STREAM_DONE_15 335 +-#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_0 336 +-#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_1 337 +-#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_2 338 +-#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_3 339 +-#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_4 340 +-#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_5 341 +-#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_6 342 +-#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_7 343 +-#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_8 344 +-#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_9 345 +-#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_10 346 +-#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_11 347 +-#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_12 348 +-#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_13 349 +-#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_14 350 +-#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_15 351 +-#define CMDQ_EVENT_VPP0_MDP_RDMA_SW_RST_DONE 352 +-#define CMDQ_EVENT_VPP0_MDP_RDMA_PM_VALID 353 +-#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_FRAME_RESET_DONE_PULSE 354 +-#define CMDQ_EVENT_VPP0_MDP_WROT_SW_RST_DONE 355 +- +-#define CMDQ_EVENT_VPP1_HDMI_META_SOF 384 +-#define CMDQ_EVENT_VPP1_DGI_SOF 385 +-#define CMDQ_EVENT_VPP1_VPP_SPLIT_SOF 386 +-#define CMDQ_EVENT_VPP1_SVPP1_MDP_TCC_SOF 387 +-#define CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF 388 +-#define CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF 389 +-#define CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF 390 +-#define CMDQ_EVENT_VPP1_SVPP1_MDP_FG_SOF 391 +-#define CMDQ_EVENT_VPP1_SVPP2_MDP_FG_SOF 392 +-#define CMDQ_EVENT_VPP1_SVPP3_MDP_FG_SOF 393 +-#define CMDQ_EVENT_VPP1_SVPP1_MDP_HDR_SOF 394 +-#define CMDQ_EVENT_VPP1_SVPP2_MDP_HDR_SOF 395 +-#define CMDQ_EVENT_VPP1_SVPP3_MDP_HDR_SOF 396 +-#define CMDQ_EVENT_VPP1_SVPP1_MDP_AAL_SOF 397 +-#define CMDQ_EVENT_VPP1_SVPP2_MDP_AAL_SOF 398 +-#define CMDQ_EVENT_VPP1_SVPP3_MDP_AAL_SOF 399 +-#define CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF 400 +-#define CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF 401 +-#define CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF 402 +-#define CMDQ_EVENT_VPP1_SVPP1_TDSHP_SOF 403 +-#define CMDQ_EVENT_VPP1_SVPP2_TDSHP_SOF 404 +-#define CMDQ_EVENT_VPP1_SVPP3_TDSHP_SOF 405 +-#define CMDQ_EVENT_VPP1_SVPP2_VPP_MERGE_SOF 406 +-#define CMDQ_EVENT_VPP1_SVPP3_VPP_MERGE_SOF 407 +-#define CMDQ_EVENT_VPP1_SVPP1_MDP_COLOR_SOF 408 +-#define CMDQ_EVENT_VPP1_SVPP2_MDP_COLOR_SOF 409 +-#define CMDQ_EVENT_VPP1_SVPP3_MDP_COLOR_SOF 410 +-#define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_SOF 411 +-#define CMDQ_EVENT_VPP1_SVPP1_VPP_PAD_SOF 412 +-#define CMDQ_EVENT_VPP1_SVPP2_VPP_PAD_SOF 413 +-#define CMDQ_EVENT_VPP1_SVPP3_VPP_PAD_SOF 414 +-#define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF 415 +-#define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF 416 +-#define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF 417 +-#define CMDQ_EVENT_VPP1_VPP0_DL_IRLY_SOF 418 +-#define CMDQ_EVENT_VPP1_VPP0_DL_ORLY_SOF 419 +-#define CMDQ_EVENT_VPP1_VDO0_DL_ORLY_0_SOF 420 +-#define CMDQ_EVENT_VPP1_VDO0_DL_ORLY_1_SOF 421 +-#define CMDQ_EVENT_VPP1_VDO1_DL_ORLY_0_SOF 422 +-#define CMDQ_EVENT_VPP1_VDO1_DL_ORLY_1_SOF 423 +-#define CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE 424 +-#define CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE 425 +-#define CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE 426 +-#define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE 427 +-#define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE 428 +-#define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE 429 +-#define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_FRAME_DONE 430 +-#define CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE 431 +-#define CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE 432 +-#define CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE 433 +-#define CMDQ_EVENT_VPP1_FRAME_DONE_10 434 +-#define CMDQ_EVENT_VPP1_FRAME_DONE_11 435 +-#define CMDQ_EVENT_VPP1_FRAME_DONE_12 436 +-#define CMDQ_EVENT_VPP1_FRAME_DONE_13 437 +-#define CMDQ_EVENT_VPP1_FRAME_DONE_14 438 +-#define CMDQ_EVENT_VPP1_STREAM_DONE_0 439 +-#define CMDQ_EVENT_VPP1_STREAM_DONE_1 440 +-#define CMDQ_EVENT_VPP1_STREAM_DONE_2 441 +-#define CMDQ_EVENT_VPP1_STREAM_DONE_3 442 +-#define CMDQ_EVENT_VPP1_STREAM_DONE_4 443 +-#define CMDQ_EVENT_VPP1_STREAM_DONE_5 444 +-#define CMDQ_EVENT_VPP1_STREAM_DONE_6 445 +-#define CMDQ_EVENT_VPP1_STREAM_DONE_7 446 +-#define CMDQ_EVENT_VPP1_STREAM_DONE_8 447 +-#define CMDQ_EVENT_VPP1_STREAM_DONE_9 448 +-#define CMDQ_EVENT_VPP1_STREAM_DONE_10 449 +-#define CMDQ_EVENT_VPP1_STREAM_DONE_11 450 +-#define CMDQ_EVENT_VPP1_STREAM_DONE_12 451 +-#define CMDQ_EVENT_VPP1_STREAM_DONE_13 452 +-#define CMDQ_EVENT_VPP1_STREAM_DONE_14 453 +-#define CMDQ_EVENT_VPP1_STREAM_DONE_15 454 +-#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_0 455 +-#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_1 456 +-#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_2 457 +-#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_3 458 +-#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_4 459 +-#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_5 460 +-#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_6 461 +-#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_7 462 +-#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_8 463 +-#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_9 464 +-#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_10 465 +-#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_11 466 +-#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_12 467 +-#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_13 468 +-#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_14 469 +-#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_15 470 +-#define CMDQ_EVENT_VPP1_DGI_0 471 +-#define CMDQ_EVENT_VPP1_DGI_1 472 +-#define CMDQ_EVENT_VPP1_DGI_2 473 +-#define CMDQ_EVENT_VPP1_DGI_3 474 +-#define CMDQ_EVENT_VPP1_DGI_4 475 +-#define CMDQ_EVENT_VPP1_DGI_5 476 +-#define CMDQ_EVENT_VPP1_DGI_6 477 +-#define CMDQ_EVENT_VPP1_DGI_7 478 +-#define CMDQ_EVENT_VPP1_DGI_8 479 +-#define CMDQ_EVENT_VPP1_DGI_9 480 +-#define CMDQ_EVENT_VPP1_DGI_10 481 +-#define CMDQ_EVENT_VPP1_DGI_11 482 +-#define CMDQ_EVENT_VPP1_DGI_12 483 +-#define CMDQ_EVENT_VPP1_DGI_13 484 +-#define CMDQ_EVENT_VPP1_SVPP3_VPP_MERGE 485 +-#define CMDQ_EVENT_VPP1_SVPP2_VPP_MERGE 486 +-#define CMDQ_EVENT_VPP1_MDP_OVL_FRAME_RESET_DONE_PULSE 487 +-#define CMDQ_EVENT_VPP1_VPP_SPLIT_DGI 488 +-#define CMDQ_EVENT_VPP1_VPP_SPLIT_HDMI 489 +-#define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SW_RST_DONE 490 +-#define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SW_RST_DONE 491 +-#define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SW_RST_DONE 492 +-#define CMDQ_EVENT_VPP1_SVPP3_MDP_FG_TILE_DONE 493 +-#define CMDQ_EVENT_VPP1_SVPP2_MDP_FG_TILE_DONE 494 +-#define CMDQ_EVENT_VPP1_SVPP1_MDP_FG_TILE_DONE 495 +- +-#define CMDQ_EVENT_VDO0_DISP_OVL0_SOF 512 +-#define CMDQ_EVENT_VDO0_DISP_WDMA0_SOF 513 +-#define CMDQ_EVENT_VDO0_DISP_RDMA0_SOF 514 +-#define CMDQ_EVENT_VDO0_DISP_COLOR0_SOF 515 +-#define CMDQ_EVENT_VDO0_DISP_CCORR0_SOF 516 +-#define CMDQ_EVENT_VDO0_DISP_AAL0_SOF 517 +-#define CMDQ_EVENT_VDO0_DISP_GAMMA0_SOF 518 +-#define CMDQ_EVENT_VDO0_DISP_DITHER0_SOF 519 +-#define CMDQ_EVENT_VDO0_DSI0_SOF 520 +-#define CMDQ_EVENT_VDO0_DSC_WRAP0C0_SOF 521 +-#define CMDQ_EVENT_VDO0_DISP_OVL1_SOF 522 +-#define CMDQ_EVENT_VDO0_DISP_WDMA1_SOF 523 +-#define CMDQ_EVENT_VDO0_DISP_RDMA1_SOF 524 +-#define CMDQ_EVENT_VDO0_DISP_COLOR1_SOF 525 +-#define CMDQ_EVENT_VDO0_DISP_CCORR1_SOF 526 +-#define CMDQ_EVENT_VDO0_DISP_AAL1_SOF 527 +-#define CMDQ_EVENT_VDO0_DISP_GAMMA1_SOF 528 +-#define CMDQ_EVENT_VDO0_DISP_DITHER1_SOF 529 +-#define CMDQ_EVENT_VDO0_DSI1_SOF 530 +-#define CMDQ_EVENT_VDO0_DSC_WRAP0C1_SOF 531 +-#define CMDQ_EVENT_VDO0_VPP_MERGE0_SOF 532 +-#define CMDQ_EVENT_VDO0_DP_INTF0_SOF 533 +-#define CMDQ_EVENT_VDO0_VPP1_DL_RELAY0_SOF 534 +-#define CMDQ_EVENT_VDO0_VPP1_DL_RELAY1_SOF 535 +-#define CMDQ_EVENT_VDO0_VDO1_DL_RELAY2_SOF 536 +-#define CMDQ_EVENT_VDO0_VDO0_DL_RELAY3_SOF 537 +-#define CMDQ_EVENT_VDO0_VDO0_DL_RELAY4_SOF 538 +-#define CMDQ_EVENT_VDO0_DISP_PWM0_SOF 539 +-#define CMDQ_EVENT_VDO0_DISP_PWM1_SOF 540 +- +-#define CMDQ_EVENT_VDO0_DISP_OVL0_FRAME_DONE 544 +-#define CMDQ_EVENT_VDO0_DISP_WDMA0_FRAME_DONE 545 +-#define CMDQ_EVENT_VDO0_DISP_RDMA0_FRAME_DONE 546 +-#define CMDQ_EVENT_VDO0_DISP_COLOR0_FRAME_DONE 547 +-#define CMDQ_EVENT_VDO0_DISP_CCORR0_FRAME_DONE 548 +-#define CMDQ_EVENT_VDO0_DISP_AAL0_FRAME_DONE 549 +-#define CMDQ_EVENT_VDO0_DISP_GAMMA0_FRAME_DONE 550 +-#define CMDQ_EVENT_VDO0_DISP_DITHER0_FRAME_DONE 551 +-#define CMDQ_EVENT_VDO0_DSI0_FRAME_DONE 552 +-#define CMDQ_EVENT_VDO0_DSC_WRAP0C0_FRAME_DONE 553 +-#define CMDQ_EVENT_VDO0_DISP_OVL1_FRAME_DONE 554 +-#define CMDQ_EVENT_VDO0_DISP_WDMA1_FRAME_DONE 555 +-#define CMDQ_EVENT_VDO0_DISP_RDMA1_FRAME_DONE 556 +-#define CMDQ_EVENT_VDO0_DISP_COLOR1_FRAME_DONE 557 +-#define CMDQ_EVENT_VDO0_DISP_CCORR1_FRAME_DONE 558 +-#define CMDQ_EVENT_VDO0_DISP_AAL1_FRAME_DONE 559 +-#define CMDQ_EVENT_VDO0_DISP_GAMMA1_FRAME_DONE 560 +-#define CMDQ_EVENT_VDO0_DISP_DITHER1_FRAME_DONE 561 +-#define CMDQ_EVENT_VDO0_DSI1_FRAME_DONE 562 +-#define CMDQ_EVENT_VDO0_DSC_WRAP0C1_FRAME_DONE 563 +- +-#define CMDQ_EVENT_VDO0_DP_INTF0_FRAME_DONE 565 +- +-#define CMDQ_EVENT_VDO0_DISP_SMIASSERT_ENG 576 +-#define CMDQ_EVENT_VDO0_DSI0_IRQ_ENG_EVENT_MM 577 +-#define CMDQ_EVENT_VDO0_DSI0_TE_ENG_EVENT_MM 578 +-#define CMDQ_EVENT_VDO0_DSI0_DONE_ENG_EVENT_MM 579 +-#define CMDQ_EVENT_VDO0_DSI0_SOF_ENG_EVENT_MM 580 +-#define CMDQ_EVENT_VDO0_DSI0_VACTL_ENG_EVENT_MM 581 +-#define CMDQ_EVENT_VDO0_DSI1_IRQ_ENG_EVENT_MM 582 +-#define CMDQ_EVENT_VDO0_DSI1_TE_ENG_EVENT_MM 583 +-#define CMDQ_EVENT_VDO0_DSI1_DONE_ENG_EVENT_MM 584 +-#define CMDQ_EVENT_VDO0_DSI1_SOF_ENG_EVENT_MM 585 +-#define CMDQ_EVENT_VDO0_DSI1_VACTL_ENG_EVENT_MM 586 +-#define CMDQ_EVENT_VDO0_DISP_WDMA0_SW_RST_DONE_ENG 587 +-#define CMDQ_EVENT_VDO0_DISP_WDMA1_SW_RST_DONE_ENG 588 +-#define CMDQ_EVENT_VDO0_DISP_OVL0_RST_DONE_ENG 589 +-#define CMDQ_EVENT_VDO0_DISP_OVL1_RST_DONE_ENG 590 +-#define CMDQ_EVENT_VDO0_DP_INTF0_VSYNC_START_ENG_EVENT_MM 591 +-#define CMDQ_EVENT_VDO0_DP_INTF0_VSYNC_END_ENG_EVENT_MM 592 +-#define CMDQ_EVENT_VDO0_DP_INTF0_VDE_START_ENG_EVENT_MM 593 +-#define CMDQ_EVENT_VDO0_DP_INTF0_VDE_END_ENG_EVENT_MM 594 +-#define CMDQ_EVENT_VDO0_DP_INTF0_TARGET_LINE_ENG_EVENT_MM 595 +-#define CMDQ_EVENT_VDO0_VPP_MERGE0_ENG 596 +-#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0 597 +-#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_1 598 +-#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_2 599 +-#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_3 600 +-#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_4 601 +-#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_5 602 +-#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_6 603 +-#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_7 604 +-#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_8 605 +-#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_9 606 +-#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_10 607 +-#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_11 608 +-#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_12 609 +-#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_13 610 +-#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_14 611 +-#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_15 612 +-#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_0 613 +-#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_1 614 +-#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_2 615 +-#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_3 616 +-#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_4 617 +-#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_5 618 +-#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_6 619 +-#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_7 620 +-#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_8 621 +-#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_9 622 +-#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_10 623 +-#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_11 624 +-#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_12 625 +-#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_13 626 +-#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_14 627 +-#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_15 628 +- +-#define CMDQ_EVENT_VDO1_MDP_RDMA0_SOF 640 +-#define CMDQ_EVENT_VDO1_MDP_RDMA1_SOF 641 +-#define CMDQ_EVENT_VDO1_MDP_RDMA2_SOF 642 +-#define CMDQ_EVENT_VDO1_MDP_RDMA3_SOF 643 +-#define CMDQ_EVENT_VDO1_MDP_RDMA4_SOF 644 +-#define CMDQ_EVENT_VDO1_MDP_RDMA5_SOF 645 +-#define CMDQ_EVENT_VDO1_MDP_RDMA6_SOF 646 +-#define CMDQ_EVENT_VDO1_MDP_RDMA7_SOF 647 +-#define CMDQ_EVENT_VDO1_VPP_MERGE0_SOF 648 +-#define CMDQ_EVENT_VDO1_VPP_MERGE1_SOF 649 +-#define CMDQ_EVENT_VDO1_VPP_MERGE2_SOF 650 +-#define CMDQ_EVENT_VDO1_VPP_MERGE3_SOF 651 +-#define CMDQ_EVENT_VDO1_VPP_MERGE4_SOF 652 +-#define CMDQ_EVENT_VDO1_VPP2_DL_RELAY_SOF 653 +-#define CMDQ_EVENT_VDO1_VPP3_DL_RELAY_SOF 654 +-#define CMDQ_EVENT_VDO1_VDO0_DSC_DL_ASYNC_SOF 655 +-#define CMDQ_EVENT_VDO1_VDO0_MERGE_DL_ASYNC_SOF 656 +-#define CMDQ_EVENT_VDO1_OUT_DL_RELAY_SOF 657 +-#define CMDQ_EVENT_VDO1_DISP_MIXER_SOF 658 +-#define CMDQ_EVENT_VDO1_HDR_VDO_FE0_SOF 659 +-#define CMDQ_EVENT_VDO1_HDR_VDO_FE1_SOF 660 +-#define CMDQ_EVENT_VDO1_HDR_GFX_FE0_SOF 661 +-#define CMDQ_EVENT_VDO1_HDR_GFX_FE1_SOF 662 +-#define CMDQ_EVENT_VDO1_HDR_VDO_BE0_SOF 663 +-#define CMDQ_EVENT_VDO1_HDR_MLOAD_SOF 664 +- +-#define CMDQ_EVENT_VDO1_MDP_RDMA0_FRAME_DONE 672 +-#define CMDQ_EVENT_VDO1_MDP_RDMA1_FRAME_DONE 673 +-#define CMDQ_EVENT_VDO1_MDP_RDMA2_FRAME_DONE 674 +-#define CMDQ_EVENT_VDO1_MDP_RDMA3_FRAME_DONE 675 +-#define CMDQ_EVENT_VDO1_MDP_RDMA4_FRAME_DONE 676 +-#define CMDQ_EVENT_VDO1_MDP_RDMA5_FRAME_DONE 677 +-#define CMDQ_EVENT_VDO1_MDP_RDMA6_FRAME_DONE 678 +-#define CMDQ_EVENT_VDO1_MDP_RDMA7_FRAME_DONE 679 +-#define CMDQ_EVENT_VDO1_VPP_MERGE0_FRAME_DONE 680 +-#define CMDQ_EVENT_VDO1_VPP_MERGE1_FRAME_DONE 681 +-#define CMDQ_EVENT_VDO1_VPP_MERGE2_FRAME_DONE 682 +-#define CMDQ_EVENT_VDO1_VPP_MERGE3_FRAME_DONE 683 +-#define CMDQ_EVENT_VDO1_VPP_MERGE4_FRAME_DONE 684 +-#define CMDQ_EVENT_VDO1_DPI0_FRAME_DONE 685 +-#define CMDQ_EVENT_VDO1_DPI1_FRAME_DONE 686 +-#define CMDQ_EVENT_VDO1_DP_INTF0_FRAME_DONE 687 +-#define CMDQ_EVENT_VDO1_DISP_MIXER_FRAME_DONE_MM 688 +- +-#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0 704 +-#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_1 705 +-#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_2 706 +-#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_3 707 +-#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_4 708 +-#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_5 709 +-#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_6 710 +-#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_7 711 +-#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_8 712 +-#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_9 713 +-#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_10 714 +-#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_11 715 +-#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_12 716 +-#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_13 717 +-#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_14 718 +-#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_15 719 +-#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_0 720 +-#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_1 721 +-#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_2 722 +-#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_3 723 +-#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_4 724 +-#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_5 725 +-#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_6 726 +-#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_7 727 +-#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_8 728 +-#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_9 729 +-#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_10 730 +-#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_11 731 +-#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_12 732 +-#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_13 733 +-#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_14 734 +-#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_15 735 +-#define CMDQ_EVENT_VDO1_MDP_RDMA0_SW_RST_DONE 736 +-#define CMDQ_EVENT_VDO1_MDP_RDMA1_SW_RST_DONE 737 +-#define CMDQ_EVENT_VDO1_MDP_RDMA2_SW_RST_DONE 738 +-#define CMDQ_EVENT_VDO1_MDP_RDMA3_SW_RST_DONE 739 +-#define CMDQ_EVENT_VDO1_MDP_RDMA4_SW_RST_DONE 740 +-#define CMDQ_EVENT_VDO1_MDP_RDMA5_SW_RST_DONE 741 +-#define CMDQ_EVENT_VDO1_MDP_RDMA6_SW_RST_DONE 742 +-#define CMDQ_EVENT_VDO1_MDP_RDMA7_SW_RST_DONE 743 +- +-#define CMDQ_EVENT_VDO1_DP0_VDE_END_ENG_EVENT_MM 745 +-#define CMDQ_EVENT_VDO1_DP0_VDE_START_ENG_EVENT_MM 746 +-#define CMDQ_EVENT_VDO1_DP0_VSYNC_END_ENG_EVENT_MM 747 +-#define CMDQ_EVENT_VDO1_DP0_VSYNC_START_ENG_EVENT_MM 748 +-#define CMDQ_EVENT_VDO1_DP0_TARGET_LINE_ENG_EVENT_MM 749 +-#define CMDQ_EVENT_VDO1_VPP_MERGE0 750 +-#define CMDQ_EVENT_VDO1_VPP_MERGE1 751 +-#define CMDQ_EVENT_VDO1_VPP_MERGE2 752 +-#define CMDQ_EVENT_VDO1_VPP_MERGE3 753 +-#define CMDQ_EVENT_VDO1_VPP_MERGE4 754 +-#define CMDQ_EVENT_VDO1_HDMITX 755 +-#define CMDQ_EVENT_VDO1_HDR_VDO_BE0_ADL_TRIG_EVENT_MM 756 +-#define CMDQ_EVENT_VDO1_HDR_GFX_FE1_THDR_ADL_TRIG_EVENT_MM 757 +-#define CMDQ_EVENT_VDO1_HDR_GFX_FE1_DM_ADL_TRIG_EVENT_MM 758 +-#define CMDQ_EVENT_VDO1_HDR_GFX_FE0_THDR_ADL_TRIG_EVENT_MM 759 +-#define CMDQ_EVENT_VDO1_HDR_GFX_FE0_DM_ADL_TRIG_EVENT_MM 760 +-#define CMDQ_EVENT_VDO1_HDR_VDO_FE1_ADL_TRIG_EVENT_MM 761 +-#define CMDQ_EVENT_VDO1_HDR_VDO_FE1_AD0_TRIG_EVENT_MM 762 +- +-#define CMDQ_EVENT_CAM_A_PASS1_DONE 769 +-#define CMDQ_EVENT_CAM_B_PASS1_DONE 770 +-#define CMDQ_EVENT_GCAMSV_A_PASS1_DONE 771 +-#define CMDQ_EVENT_GCAMSV_B_PASS1_DONE 772 +-#define CMDQ_EVENT_MRAW_0_PASS1_DONE 773 +-#define CMDQ_EVENT_MRAW_1_PASS1_DONE 774 +-#define CMDQ_EVENT_MRAW_2_PASS1_DONE 775 +-#define CMDQ_EVENT_MRAW_3_PASS1_DONE 776 +-#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL_X 777 +-#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL_X 778 +-#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 779 +-#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 780 +-#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 781 +-#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 782 +-#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 783 +-#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 784 +-#define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL 785 +-#define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL 786 +-#define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL_X 787 +-#define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL_X 788 +-#define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL_X 789 +-#define CMDQ_EVENT_SENINF_CAM13_FIFO_FULL_X 790 +-#define CMDQ_EVENT_TG_OVRUN_MRAW0_INT_X0 791 +-#define CMDQ_EVENT_TG_OVRUN_MRAW1_INT_X0 792 +-#define CMDQ_EVENT_TG_OVRUN_MRAW2_INT 793 +-#define CMDQ_EVENT_TG_OVRUN_MRAW3_INT 794 +-#define CMDQ_EVENT_DMA_R1_ERROR_MRAW0_INT 795 +-#define CMDQ_EVENT_DMA_R1_ERROR_MRAW1_INT 796 +-#define CMDQ_EVENT_DMA_R1_ERROR_MRAW2_INT 797 +-#define CMDQ_EVENT_DMA_R1_ERROR_MRAW3_INT 798 +-#define CMDQ_EVENT_U_CAMSYS_PDA_IRQO_EVENT_DONE_D1 799 +-#define CMDQ_EVENT_SUBB_TG_INT4 800 +-#define CMDQ_EVENT_SUBB_TG_INT3 801 +-#define CMDQ_EVENT_SUBB_TG_INT2 802 +-#define CMDQ_EVENT_SUBB_TG_INT1 803 +-#define CMDQ_EVENT_SUBA_TG_INT4 804 +-#define CMDQ_EVENT_SUBA_TG_INT3 805 +-#define CMDQ_EVENT_SUBA_TG_INT2 806 +-#define CMDQ_EVENT_SUBA_TG_INT1 807 +-#define CMDQ_EVENT_SUBB_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 808 +-#define CMDQ_EVENT_SUBB_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 809 +-#define CMDQ_EVENT_SUBB_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 810 +-#define CMDQ_EVENT_SUBB_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 811 +-#define CMDQ_EVENT_SUBA_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 812 +-#define CMDQ_EVENT_SUBA_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 813 +-#define CMDQ_EVENT_SUBA_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 814 +-#define CMDQ_EVENT_SUBA_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 815 +-#define CMDQ_EVENT_GCE1_SOF_0 816 +-#define CMDQ_EVENT_GCE1_SOF_1 817 +-#define CMDQ_EVENT_GCE1_SOF_2 818 +-#define CMDQ_EVENT_GCE1_SOF_3 819 +-#define CMDQ_EVENT_GCE1_SOF_4 820 +-#define CMDQ_EVENT_GCE1_SOF_5 821 +-#define CMDQ_EVENT_GCE1_SOF_6 822 +-#define CMDQ_EVENT_GCE1_SOF_7 823 +-#define CMDQ_EVENT_GCE1_SOF_8 824 +-#define CMDQ_EVENT_GCE1_SOF_9 825 +-#define CMDQ_EVENT_GCE1_SOF_10 826 +-#define CMDQ_EVENT_GCE1_SOF_11 827 +-#define CMDQ_EVENT_GCE1_SOF_12 828 +-#define CMDQ_EVENT_GCE1_SOF_13 829 +-#define CMDQ_EVENT_GCE1_SOF_14 830 +-#define CMDQ_EVENT_GCE1_SOF_15 831 +- +-#define CMDQ_EVENT_VDEC_LAT_LINE_COUNT_THRESHOLD_INTERRUPT 832 +-#define CMDQ_EVENT_VDEC_LAT_VDEC_INT 833 +-#define CMDQ_EVENT_VDEC_LAT_VDEC_PAUSE 834 +-#define CMDQ_EVENT_VDEC_LAT_VDEC_DEC_ERROR 835 +-#define CMDQ_EVENT_VDEC_LAT_MC_BUSY_OVERFLOW_MDEC_TIMEOUT 836 +-#define CMDQ_EVENT_VDEC_LAT_VDEC_FRAME_DONE 837 +-#define CMDQ_EVENT_VDEC_LAT_INI_FETCH_RDY 838 +-#define CMDQ_EVENT_VDEC_LAT_PROCESS_FLAG 839 +-#define CMDQ_EVENT_VDEC_LAT_SEARCH_START_CODE_DONE 840 +-#define CMDQ_EVENT_VDEC_LAT_REF_REORDER_DONE 841 +-#define CMDQ_EVENT_VDEC_LAT_WP_TBLE_DONE 842 +-#define CMDQ_EVENT_VDEC_LAT_COUNT_SRAM_CLR_DONE_AND_CTX_SRAM_CLR_DONE 843 +-#define CMDQ_EVENT_VDEC_LAT_GCE_CNT_OP_THRESHOLD 847 +- +-#define CMDQ_EVENT_VDEC_LAT1_LINE_COUNT_THRESHOLD_INTERRUPT 848 +-#define CMDQ_EVENT_VDEC_LAT1_VDEC_INT 849 +-#define CMDQ_EVENT_VDEC_LAT1_VDEC_PAUSE 850 +-#define CMDQ_EVENT_VDEC_LAT1_VDEC_DEC_ERROR 851 +-#define CMDQ_EVENT_VDEC_LAT1_MC_BUSY_OVERFLOW_MDEC_TIMEOUT 852 +-#define CMDQ_EVENT_VDEC_LAT1_VDEC_FRAME_DONE 853 +-#define CMDQ_EVENT_VDEC_LAT1_INI_FETCH_RDY 854 +-#define CMDQ_EVENT_VDEC_LAT1_PROCESS_FLAG 855 +-#define CMDQ_EVENT_VDEC_LAT1_SEARCH_START_CODE_DONE 856 +-#define CMDQ_EVENT_VDEC_LAT1_REF_REORDER_DONE 857 +-#define CMDQ_EVENT_VDEC_LAT1_WP_TBLE_DONE 858 +-#define CMDQ_EVENT_VDEC_LAT1_COUNT_SRAM_CLR_DONE_AND_CTX_SRAM_CLR_DONE 859 +-#define CMDQ_EVENT_VDEC_LAT1_GCE_CNT_OP_THRESHOLD 863 +- +-#define CMDQ_EVENT_VDEC_SOC_GLOBAL_CON_250_0 864 +-#define CMDQ_EVENT_VDEC_SOC_GLOBAL_CON_250_1 865 +- +-#define CMDQ_EVENT_VDEC_SOC_GLOBAL_CON_250_8 872 +-#define CMDQ_EVENT_VDEC_SOC_GLOBAL_CON_250_9 873 +- +-#define CMDQ_EVENT_VDEC_CORE_LINE_COUNT_THRESHOLD_INTERRUPT 896 +-#define CMDQ_EVENT_VDEC_CORE_VDEC_INT 897 +-#define CMDQ_EVENT_VDEC_CORE_VDEC_PAUSE 898 +-#define CMDQ_EVENT_VDEC_CORE_VDEC_DEC_ERROR 899 +-#define CMDQ_EVENT_VDEC_CORE_MC_BUSY_OVERFLOW_MDEC_TIMEOUT 900 +-#define CMDQ_EVENT_VDEC_CORE_VDEC_FRAME_DONE 901 +-#define CMDQ_EVENT_VDEC_CORE_INI_FETCH_RDY 902 +-#define CMDQ_EVENT_VDEC_CORE_PROCESS_FLAG 903 +-#define CMDQ_EVENT_VDEC_CORE_SEARCH_START_CODE_DONE 904 +-#define CMDQ_EVENT_VDEC_CORE_REF_REORDER_DONE 905 +-#define CMDQ_EVENT_VDEC_CORE_WP_TBLE_DONE 906 +-#define CMDQ_EVENT_VDEC_CORE_COUNT_SRAM_CLR_DONE_AND_CTX_SRAM_CLR_DONE 907 +-#define CMDQ_EVENT_VDEC_CORE_GCE_CNT_OP_THRESHOLD 911 +- +-#define CMDQ_EVENT_VDEC_CORE1_LINE_COUNT_THRESHOLD_INTERRUPT 912 +-#define CMDQ_EVENT_VDEC_CORE1_VDEC_INT 913 +-#define CMDQ_EVENT_VDEC_CORE1_VDEC_PAUSE 914 +-#define CMDQ_EVENT_VDEC_CORE1_VDEC_DEC_ERROR 915 +-#define CMDQ_EVENT_VDEC_CORE1_MC_BUSY_OVERFLOW_MDEC_TIMEOUT 916 +-#define CMDQ_EVENT_VDEC_CORE1_VDEC_FRAME_DONE 917 +-#define CMDQ_EVENT_VDEC_CORE1_INI_FETCH_RDY 918 +-#define CMDQ_EVENT_VDEC_CORE1_PROCESS_FLAG 919 +-#define CMDQ_EVENT_VDEC_CORE1_SEARCH_START_CODE_DONE 920 +-#define CMDQ_EVENT_VDEC_CORE1_REF_REORDER_DONE 921 +-#define CMDQ_EVENT_VDEC_CORE1_WP_TBLE_DONE 922 +-#define CMDQ_EVENT_VDEC_CORE1_COUNT_SRAM_CLR_DONE_AND_CTX_SRAM_CLR_DONE 923 +-#define CMDQ_EVENT_VDEC_CORE1_CNT_OP_THRESHOLD 927 +- +-#define CMDQ_EVENT_VENC_TOP_FRAME_DONE 929 +-#define CMDQ_EVENT_VENC_TOP_PAUSE_DONE 930 +-#define CMDQ_EVENT_VENC_TOP_JPGENC_DONE 931 +-#define CMDQ_EVENT_VENC_TOP_MB_DONE 932 +-#define CMDQ_EVENT_VENC_TOP_128BYTE_DONE 933 +-#define CMDQ_EVENT_VENC_TOP_JPGDEC_DONE 934 +-#define CMDQ_EVENT_VENC_TOP_JPGDEC_C1_DONE 935 +-#define CMDQ_EVENT_VENC_TOP_JPGDEC_INSUFF_DONE 936 +-#define CMDQ_EVENT_VENC_TOP_JPGDEC_C1_INSUFF_DONE 937 +-#define CMDQ_EVENT_VENC_TOP_WP_2ND_STAGE_DONE 938 +-#define CMDQ_EVENT_VENC_TOP_WP_3RD_STAGE_DONE 939 +-#define CMDQ_EVENT_VENC_TOP_PPS_HEADER_DONE 940 +-#define CMDQ_EVENT_VENC_TOP_SPS_HEADER_DONE 941 +-#define CMDQ_EVENT_VENC_TOP_VPS_HEADER_DONE 942 +- +-#define CMDQ_EVENT_VENC_CORE1_TOP_FRAME_DONE 945 +-#define CMDQ_EVENT_VENC_CORE1_TOP_PAUSE_DONE 946 +-#define CMDQ_EVENT_VENC_CORE1_TOP_JPGENC_DONE 947 +-#define CMDQ_EVENT_VENC_CORE1_TOP_MB_DONE 948 +-#define CMDQ_EVENT_VENC_CORE1_TOP_128BYTE_DONE 949 +-#define CMDQ_EVENT_VENC_CORE1_TOP_JPGDEC_DONE 950 +-#define CMDQ_EVENT_VENC_CORE1_TOP_JPGDEC_C1_DONE 951 +-#define CMDQ_EVENT_VENC_CORE1_TOP_JPGDEC_INSUFF_DONE 952 +-#define CMDQ_EVENT_VENC_CORE1_TOP_JPGDEC_C1_INSUFF_DONE 953 +-#define CMDQ_EVENT_VENC_CORE1_TOP_WP_2ND_STAGE_DONE 954 +-#define CMDQ_EVENT_VENC_CORE1_TOP_WP_3RD_STAGE_DONE 955 +-#define CMDQ_EVENT_VENC_CORE1_TOP_PPS_HEADER_DONE 956 +-#define CMDQ_EVENT_VENC_CORE1_TOP_SPS_HEADER_DONE 957 +-#define CMDQ_EVENT_VENC_CORE1_TOP_VPS_HEADER_DONE 958 +- +-#define CMDQ_EVENT_WPE_VPP0_WPE_GCE_FRAME_DONE 962 +-#define CMDQ_EVENT_WPE_VPP0_WPE_DONE_SYNC_OUT 963 +- +-#define CMDQ_EVENT_WPE_VPP1_WPE_GCE_FRAME_DONE 969 +-#define CMDQ_EVENT_WPE_VPP1_WPE_DONE_SYNC_OUT 970 +- +-#define CMDQ_EVENT_DP_TX_VBLANK_FALLING 994 +-#define CMDQ_EVENT_DP_TX_VSC_FINISH 995 +- +-#define CMDQ_EVENT_OUTPIN_0 1018 +-#define CMDQ_EVENT_OUTPIN_1 1019 +- +-/* end of hw event */ +-#define CMDQ_MAX_HW_EVENT 1019 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/gpio/aspeed-gpio.h b/scripts/dtc/include-prefixes/dt-bindings/gpio/aspeed-gpio.h +deleted file mode 100644 +index 56fc4889b2c4..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/gpio/aspeed-gpio.h ++++ /dev/null +@@ -1,49 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * This header provides constants for binding aspeed,*-gpio. +- * +- * The first cell in Aspeed's GPIO specifier is the GPIO ID. The macros below +- * provide names for this. +- * +- * The second cell contains standard flag values specified in gpio.h. +- */ +- +-#ifndef _DT_BINDINGS_GPIO_ASPEED_GPIO_H +-#define _DT_BINDINGS_GPIO_ASPEED_GPIO_H +- +-#include +- +-#define ASPEED_GPIO_PORT_A 0 +-#define ASPEED_GPIO_PORT_B 1 +-#define ASPEED_GPIO_PORT_C 2 +-#define ASPEED_GPIO_PORT_D 3 +-#define ASPEED_GPIO_PORT_E 4 +-#define ASPEED_GPIO_PORT_F 5 +-#define ASPEED_GPIO_PORT_G 6 +-#define ASPEED_GPIO_PORT_H 7 +-#define ASPEED_GPIO_PORT_I 8 +-#define ASPEED_GPIO_PORT_J 9 +-#define ASPEED_GPIO_PORT_K 10 +-#define ASPEED_GPIO_PORT_L 11 +-#define ASPEED_GPIO_PORT_M 12 +-#define ASPEED_GPIO_PORT_N 13 +-#define ASPEED_GPIO_PORT_O 14 +-#define ASPEED_GPIO_PORT_P 15 +-#define ASPEED_GPIO_PORT_Q 16 +-#define ASPEED_GPIO_PORT_R 17 +-#define ASPEED_GPIO_PORT_S 18 +-#define ASPEED_GPIO_PORT_T 19 +-#define ASPEED_GPIO_PORT_U 20 +-#define ASPEED_GPIO_PORT_V 21 +-#define ASPEED_GPIO_PORT_W 22 +-#define ASPEED_GPIO_PORT_X 23 +-#define ASPEED_GPIO_PORT_Y 24 +-#define ASPEED_GPIO_PORT_Z 25 +-#define ASPEED_GPIO_PORT_AA 26 +-#define ASPEED_GPIO_PORT_AB 27 +-#define ASPEED_GPIO_PORT_AC 28 +- +-#define ASPEED_GPIO(port, offset) \ +- ((ASPEED_GPIO_PORT_##port * 8) + offset) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/gpio/gpio.h b/scripts/dtc/include-prefixes/dt-bindings/gpio/gpio.h +deleted file mode 100644 +index c029467e828b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/gpio/gpio.h ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for most GPIO bindings. +- * +- * Most GPIO bindings include a flags cell as part of the GPIO specifier. +- * In most cases, the format of the flags cell uses the standard values +- * defined in this header. +- */ +- +-#ifndef _DT_BINDINGS_GPIO_GPIO_H +-#define _DT_BINDINGS_GPIO_GPIO_H +- +-/* Bit 0 express polarity */ +-#define GPIO_ACTIVE_HIGH 0 +-#define GPIO_ACTIVE_LOW 1 +- +-/* Bit 1 express single-endedness */ +-#define GPIO_PUSH_PULL 0 +-#define GPIO_SINGLE_ENDED 2 +- +-/* Bit 2 express Open drain or open source */ +-#define GPIO_LINE_OPEN_SOURCE 0 +-#define GPIO_LINE_OPEN_DRAIN 4 +- +-/* +- * Open Drain/Collector is the combination of single-ended open drain interface. +- * Open Source/Emitter is the combination of single-ended open source interface. +- */ +-#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) +-#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) +- +-/* Bit 3 express GPIO suspend/resume and reset persistence */ +-#define GPIO_PERSISTENT 0 +-#define GPIO_TRANSITORY 8 +- +-/* Bit 4 express pull up */ +-#define GPIO_PULL_UP 16 +- +-/* Bit 5 express pull down */ +-#define GPIO_PULL_DOWN 32 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/gpio/meson-a1-gpio.h b/scripts/dtc/include-prefixes/dt-bindings/gpio/meson-a1-gpio.h +deleted file mode 100644 +index 40e57a5ff1db..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/gpio/meson-a1-gpio.h ++++ /dev/null +@@ -1,73 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +-/* +- * Copyright (c) 2019 Amlogic, Inc. All rights reserved. +- * Author: Qianggui Song +- */ +- +-#ifndef _DT_BINDINGS_MESON_A1_GPIO_H +-#define _DT_BINDINGS_MESON_A1_GPIO_H +- +-#define GPIOP_0 0 +-#define GPIOP_1 1 +-#define GPIOP_2 2 +-#define GPIOP_3 3 +-#define GPIOP_4 4 +-#define GPIOP_5 5 +-#define GPIOP_6 6 +-#define GPIOP_7 7 +-#define GPIOP_8 8 +-#define GPIOP_9 9 +-#define GPIOP_10 10 +-#define GPIOP_11 11 +-#define GPIOP_12 12 +-#define GPIOB_0 13 +-#define GPIOB_1 14 +-#define GPIOB_2 15 +-#define GPIOB_3 16 +-#define GPIOB_4 17 +-#define GPIOB_5 18 +-#define GPIOB_6 19 +-#define GPIOX_0 20 +-#define GPIOX_1 21 +-#define GPIOX_2 22 +-#define GPIOX_3 23 +-#define GPIOX_4 24 +-#define GPIOX_5 25 +-#define GPIOX_6 26 +-#define GPIOX_7 27 +-#define GPIOX_8 28 +-#define GPIOX_9 29 +-#define GPIOX_10 30 +-#define GPIOX_11 31 +-#define GPIOX_12 32 +-#define GPIOX_13 33 +-#define GPIOX_14 34 +-#define GPIOX_15 35 +-#define GPIOX_16 36 +-#define GPIOF_0 37 +-#define GPIOF_1 38 +-#define GPIOF_2 39 +-#define GPIOF_3 40 +-#define GPIOF_4 41 +-#define GPIOF_5 42 +-#define GPIOF_6 43 +-#define GPIOF_7 44 +-#define GPIOF_8 45 +-#define GPIOF_9 46 +-#define GPIOF_10 47 +-#define GPIOF_11 48 +-#define GPIOF_12 49 +-#define GPIOA_0 50 +-#define GPIOA_1 51 +-#define GPIOA_2 52 +-#define GPIOA_3 53 +-#define GPIOA_4 54 +-#define GPIOA_5 55 +-#define GPIOA_6 56 +-#define GPIOA_7 57 +-#define GPIOA_8 58 +-#define GPIOA_9 59 +-#define GPIOA_10 60 +-#define GPIOA_11 61 +- +-#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/gpio/meson-axg-gpio.h b/scripts/dtc/include-prefixes/dt-bindings/gpio/meson-axg-gpio.h +deleted file mode 100644 +index 25bb1fffa97a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/gpio/meson-axg-gpio.h ++++ /dev/null +@@ -1,116 +0,0 @@ +-/* +- * Copyright (c) 2017 Amlogic, Inc. All rights reserved. +- * Author: Xingyu Chen +- * +- * SPDX-License-Identifier: GPL-2.0+ +- */ +- +-#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H +-#define _DT_BINDINGS_MESON_AXG_GPIO_H +- +-/* First GPIO chip */ +-#define GPIOAO_0 0 +-#define GPIOAO_1 1 +-#define GPIOAO_2 2 +-#define GPIOAO_3 3 +-#define GPIOAO_4 4 +-#define GPIOAO_5 5 +-#define GPIOAO_6 6 +-#define GPIOAO_7 7 +-#define GPIOAO_8 8 +-#define GPIOAO_9 9 +-#define GPIOAO_10 10 +-#define GPIOAO_11 11 +-#define GPIOAO_12 12 +-#define GPIOAO_13 13 +-#define GPIO_TEST_N 14 +- +-/* Second GPIO chip */ +-#define GPIOZ_0 0 +-#define GPIOZ_1 1 +-#define GPIOZ_2 2 +-#define GPIOZ_3 3 +-#define GPIOZ_4 4 +-#define GPIOZ_5 5 +-#define GPIOZ_6 6 +-#define GPIOZ_7 7 +-#define GPIOZ_8 8 +-#define GPIOZ_9 9 +-#define GPIOZ_10 10 +-#define BOOT_0 11 +-#define BOOT_1 12 +-#define BOOT_2 13 +-#define BOOT_3 14 +-#define BOOT_4 15 +-#define BOOT_5 16 +-#define BOOT_6 17 +-#define BOOT_7 18 +-#define BOOT_8 19 +-#define BOOT_9 20 +-#define BOOT_10 21 +-#define BOOT_11 22 +-#define BOOT_12 23 +-#define BOOT_13 24 +-#define BOOT_14 25 +-#define GPIOA_0 26 +-#define GPIOA_1 27 +-#define GPIOA_2 28 +-#define GPIOA_3 29 +-#define GPIOA_4 30 +-#define GPIOA_5 31 +-#define GPIOA_6 32 +-#define GPIOA_7 33 +-#define GPIOA_8 34 +-#define GPIOA_9 35 +-#define GPIOA_10 36 +-#define GPIOA_11 37 +-#define GPIOA_12 38 +-#define GPIOA_13 39 +-#define GPIOA_14 40 +-#define GPIOA_15 41 +-#define GPIOA_16 42 +-#define GPIOA_17 43 +-#define GPIOA_18 44 +-#define GPIOA_19 45 +-#define GPIOA_20 46 +-#define GPIOX_0 47 +-#define GPIOX_1 48 +-#define GPIOX_2 49 +-#define GPIOX_3 50 +-#define GPIOX_4 51 +-#define GPIOX_5 52 +-#define GPIOX_6 53 +-#define GPIOX_7 54 +-#define GPIOX_8 55 +-#define GPIOX_9 56 +-#define GPIOX_10 57 +-#define GPIOX_11 58 +-#define GPIOX_12 59 +-#define GPIOX_13 60 +-#define GPIOX_14 61 +-#define GPIOX_15 62 +-#define GPIOX_16 63 +-#define GPIOX_17 64 +-#define GPIOX_18 65 +-#define GPIOX_19 66 +-#define GPIOX_20 67 +-#define GPIOX_21 68 +-#define GPIOX_22 69 +-#define GPIOY_0 70 +-#define GPIOY_1 71 +-#define GPIOY_2 72 +-#define GPIOY_3 73 +-#define GPIOY_4 74 +-#define GPIOY_5 75 +-#define GPIOY_6 76 +-#define GPIOY_7 77 +-#define GPIOY_8 78 +-#define GPIOY_9 79 +-#define GPIOY_10 80 +-#define GPIOY_11 81 +-#define GPIOY_12 82 +-#define GPIOY_13 83 +-#define GPIOY_14 84 +-#define GPIOY_15 85 +- +-#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/gpio/meson-g12a-gpio.h b/scripts/dtc/include-prefixes/dt-bindings/gpio/meson-g12a-gpio.h +deleted file mode 100644 +index f7bd69350d18..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/gpio/meson-g12a-gpio.h ++++ /dev/null +@@ -1,114 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +-/* +- * Copyright (c) 2018 Amlogic, Inc. All rights reserved. +- * Author: Xingyu Chen +- */ +- +-#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H +-#define _DT_BINDINGS_MESON_G12A_GPIO_H +- +-/* First GPIO chip */ +-#define GPIOAO_0 0 +-#define GPIOAO_1 1 +-#define GPIOAO_2 2 +-#define GPIOAO_3 3 +-#define GPIOAO_4 4 +-#define GPIOAO_5 5 +-#define GPIOAO_6 6 +-#define GPIOAO_7 7 +-#define GPIOAO_8 8 +-#define GPIOAO_9 9 +-#define GPIOAO_10 10 +-#define GPIOAO_11 11 +-#define GPIOE_0 12 +-#define GPIOE_1 13 +-#define GPIOE_2 14 +- +-/* Second GPIO chip */ +-#define GPIOZ_0 0 +-#define GPIOZ_1 1 +-#define GPIOZ_2 2 +-#define GPIOZ_3 3 +-#define GPIOZ_4 4 +-#define GPIOZ_5 5 +-#define GPIOZ_6 6 +-#define GPIOZ_7 7 +-#define GPIOZ_8 8 +-#define GPIOZ_9 9 +-#define GPIOZ_10 10 +-#define GPIOZ_11 11 +-#define GPIOZ_12 12 +-#define GPIOZ_13 13 +-#define GPIOZ_14 14 +-#define GPIOZ_15 15 +-#define GPIOH_0 16 +-#define GPIOH_1 17 +-#define GPIOH_2 18 +-#define GPIOH_3 19 +-#define GPIOH_4 20 +-#define GPIOH_5 21 +-#define GPIOH_6 22 +-#define GPIOH_7 23 +-#define GPIOH_8 24 +-#define BOOT_0 25 +-#define BOOT_1 26 +-#define BOOT_2 27 +-#define BOOT_3 28 +-#define BOOT_4 29 +-#define BOOT_5 30 +-#define BOOT_6 31 +-#define BOOT_7 32 +-#define BOOT_8 33 +-#define BOOT_9 34 +-#define BOOT_10 35 +-#define BOOT_11 36 +-#define BOOT_12 37 +-#define BOOT_13 38 +-#define BOOT_14 39 +-#define BOOT_15 40 +-#define GPIOC_0 41 +-#define GPIOC_1 42 +-#define GPIOC_2 43 +-#define GPIOC_3 44 +-#define GPIOC_4 45 +-#define GPIOC_5 46 +-#define GPIOC_6 47 +-#define GPIOC_7 48 +-#define GPIOA_0 49 +-#define GPIOA_1 50 +-#define GPIOA_2 51 +-#define GPIOA_3 52 +-#define GPIOA_4 53 +-#define GPIOA_5 54 +-#define GPIOA_6 55 +-#define GPIOA_7 56 +-#define GPIOA_8 57 +-#define GPIOA_9 58 +-#define GPIOA_10 59 +-#define GPIOA_11 60 +-#define GPIOA_12 61 +-#define GPIOA_13 62 +-#define GPIOA_14 63 +-#define GPIOA_15 64 +-#define GPIOX_0 65 +-#define GPIOX_1 66 +-#define GPIOX_2 67 +-#define GPIOX_3 68 +-#define GPIOX_4 69 +-#define GPIOX_5 70 +-#define GPIOX_6 71 +-#define GPIOX_7 72 +-#define GPIOX_8 73 +-#define GPIOX_9 74 +-#define GPIOX_10 75 +-#define GPIOX_11 76 +-#define GPIOX_12 77 +-#define GPIOX_13 78 +-#define GPIOX_14 79 +-#define GPIOX_15 80 +-#define GPIOX_16 81 +-#define GPIOX_17 82 +-#define GPIOX_18 83 +-#define GPIOX_19 84 +- +-#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/gpio/meson-gxbb-gpio.h b/scripts/dtc/include-prefixes/dt-bindings/gpio/meson-gxbb-gpio.h +deleted file mode 100644 +index 489c75b27645..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/gpio/meson-gxbb-gpio.h ++++ /dev/null +@@ -1,148 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * GPIO definitions for Amlogic Meson GXBB SoCs +- * +- * Copyright (C) 2016 Endless Mobile, Inc. +- * Author: Carlo Caione +- */ +- +-#ifndef _DT_BINDINGS_MESON_GXBB_GPIO_H +-#define _DT_BINDINGS_MESON_GXBB_GPIO_H +- +-#define GPIOAO_0 0 +-#define GPIOAO_1 1 +-#define GPIOAO_2 2 +-#define GPIOAO_3 3 +-#define GPIOAO_4 4 +-#define GPIOAO_5 5 +-#define GPIOAO_6 6 +-#define GPIOAO_7 7 +-#define GPIOAO_8 8 +-#define GPIOAO_9 9 +-#define GPIOAO_10 10 +-#define GPIOAO_11 11 +-#define GPIOAO_12 12 +-#define GPIOAO_13 13 +-#define GPIO_TEST_N 14 +- +-#define GPIOZ_0 0 +-#define GPIOZ_1 1 +-#define GPIOZ_2 2 +-#define GPIOZ_3 3 +-#define GPIOZ_4 4 +-#define GPIOZ_5 5 +-#define GPIOZ_6 6 +-#define GPIOZ_7 7 +-#define GPIOZ_8 8 +-#define GPIOZ_9 9 +-#define GPIOZ_10 10 +-#define GPIOZ_11 11 +-#define GPIOZ_12 12 +-#define GPIOZ_13 13 +-#define GPIOZ_14 14 +-#define GPIOZ_15 15 +-#define GPIOH_0 16 +-#define GPIOH_1 17 +-#define GPIOH_2 18 +-#define GPIOH_3 19 +-#define BOOT_0 20 +-#define BOOT_1 21 +-#define BOOT_2 22 +-#define BOOT_3 23 +-#define BOOT_4 24 +-#define BOOT_5 25 +-#define BOOT_6 26 +-#define BOOT_7 27 +-#define BOOT_8 28 +-#define BOOT_9 29 +-#define BOOT_10 30 +-#define BOOT_11 31 +-#define BOOT_12 32 +-#define BOOT_13 33 +-#define BOOT_14 34 +-#define BOOT_15 35 +-#define BOOT_16 36 +-#define BOOT_17 37 +-#define CARD_0 38 +-#define CARD_1 39 +-#define CARD_2 40 +-#define CARD_3 41 +-#define CARD_4 42 +-#define CARD_5 43 +-#define CARD_6 44 +-#define GPIODV_0 45 +-#define GPIODV_1 46 +-#define GPIODV_2 47 +-#define GPIODV_3 48 +-#define GPIODV_4 49 +-#define GPIODV_5 50 +-#define GPIODV_6 51 +-#define GPIODV_7 52 +-#define GPIODV_8 53 +-#define GPIODV_9 54 +-#define GPIODV_10 55 +-#define GPIODV_11 56 +-#define GPIODV_12 57 +-#define GPIODV_13 58 +-#define GPIODV_14 59 +-#define GPIODV_15 60 +-#define GPIODV_16 61 +-#define GPIODV_17 62 +-#define GPIODV_18 63 +-#define GPIODV_19 64 +-#define GPIODV_20 65 +-#define GPIODV_21 66 +-#define GPIODV_22 67 +-#define GPIODV_23 68 +-#define GPIODV_24 69 +-#define GPIODV_25 70 +-#define GPIODV_26 71 +-#define GPIODV_27 72 +-#define GPIODV_28 73 +-#define GPIODV_29 74 +-#define GPIOY_0 75 +-#define GPIOY_1 76 +-#define GPIOY_2 77 +-#define GPIOY_3 78 +-#define GPIOY_4 79 +-#define GPIOY_5 80 +-#define GPIOY_6 81 +-#define GPIOY_7 82 +-#define GPIOY_8 83 +-#define GPIOY_9 84 +-#define GPIOY_10 85 +-#define GPIOY_11 86 +-#define GPIOY_12 87 +-#define GPIOY_13 88 +-#define GPIOY_14 89 +-#define GPIOY_15 90 +-#define GPIOY_16 91 +-#define GPIOX_0 92 +-#define GPIOX_1 93 +-#define GPIOX_2 94 +-#define GPIOX_3 95 +-#define GPIOX_4 96 +-#define GPIOX_5 97 +-#define GPIOX_6 98 +-#define GPIOX_7 99 +-#define GPIOX_8 100 +-#define GPIOX_9 101 +-#define GPIOX_10 102 +-#define GPIOX_11 103 +-#define GPIOX_12 104 +-#define GPIOX_13 105 +-#define GPIOX_14 106 +-#define GPIOX_15 107 +-#define GPIOX_16 108 +-#define GPIOX_17 109 +-#define GPIOX_18 110 +-#define GPIOX_19 111 +-#define GPIOX_20 112 +-#define GPIOX_21 113 +-#define GPIOX_22 114 +-#define GPIOCLK_0 115 +-#define GPIOCLK_1 116 +-#define GPIOCLK_2 117 +-#define GPIOCLK_3 118 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/gpio/meson-gxl-gpio.h b/scripts/dtc/include-prefixes/dt-bindings/gpio/meson-gxl-gpio.h +deleted file mode 100644 +index 0a001ae48272..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/gpio/meson-gxl-gpio.h ++++ /dev/null +@@ -1,125 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * GPIO definitions for Amlogic Meson GXL SoCs +- * +- * Copyright (C) 2016 Endless Mobile, Inc. +- * Author: Carlo Caione +- */ +- +-#ifndef _DT_BINDINGS_MESON_GXL_GPIO_H +-#define _DT_BINDINGS_MESON_GXL_GPIO_H +- +-#define GPIOAO_0 0 +-#define GPIOAO_1 1 +-#define GPIOAO_2 2 +-#define GPIOAO_3 3 +-#define GPIOAO_4 4 +-#define GPIOAO_5 5 +-#define GPIOAO_6 6 +-#define GPIOAO_7 7 +-#define GPIOAO_8 8 +-#define GPIOAO_9 9 +-#define GPIO_TEST_N 10 +- +-#define GPIOZ_0 0 +-#define GPIOZ_1 1 +-#define GPIOZ_2 2 +-#define GPIOZ_3 3 +-#define GPIOZ_4 4 +-#define GPIOZ_5 5 +-#define GPIOZ_6 6 +-#define GPIOZ_7 7 +-#define GPIOZ_8 8 +-#define GPIOZ_9 9 +-#define GPIOZ_10 10 +-#define GPIOZ_11 11 +-#define GPIOZ_12 12 +-#define GPIOZ_13 13 +-#define GPIOZ_14 14 +-#define GPIOZ_15 15 +-#define GPIOH_0 16 +-#define GPIOH_1 17 +-#define GPIOH_2 18 +-#define GPIOH_3 19 +-#define GPIOH_4 20 +-#define GPIOH_5 21 +-#define GPIOH_6 22 +-#define GPIOH_7 23 +-#define GPIOH_8 24 +-#define GPIOH_9 25 +-#define BOOT_0 26 +-#define BOOT_1 27 +-#define BOOT_2 28 +-#define BOOT_3 29 +-#define BOOT_4 30 +-#define BOOT_5 31 +-#define BOOT_6 32 +-#define BOOT_7 33 +-#define BOOT_8 34 +-#define BOOT_9 35 +-#define BOOT_10 36 +-#define BOOT_11 37 +-#define BOOT_12 38 +-#define BOOT_13 39 +-#define BOOT_14 40 +-#define BOOT_15 41 +-#define CARD_0 42 +-#define CARD_1 43 +-#define CARD_2 44 +-#define CARD_3 45 +-#define CARD_4 46 +-#define CARD_5 47 +-#define CARD_6 48 +-#define GPIODV_0 49 +-#define GPIODV_1 50 +-#define GPIODV_2 51 +-#define GPIODV_3 52 +-#define GPIODV_4 53 +-#define GPIODV_5 54 +-#define GPIODV_6 55 +-#define GPIODV_7 56 +-#define GPIODV_8 57 +-#define GPIODV_9 58 +-#define GPIODV_10 59 +-#define GPIODV_11 60 +-#define GPIODV_12 61 +-#define GPIODV_13 62 +-#define GPIODV_14 63 +-#define GPIODV_15 64 +-#define GPIODV_16 65 +-#define GPIODV_17 66 +-#define GPIODV_18 67 +-#define GPIODV_19 68 +-#define GPIODV_20 69 +-#define GPIODV_21 70 +-#define GPIODV_22 71 +-#define GPIODV_23 72 +-#define GPIODV_24 73 +-#define GPIODV_25 74 +-#define GPIODV_26 75 +-#define GPIODV_27 76 +-#define GPIODV_28 77 +-#define GPIODV_29 78 +-#define GPIOX_0 79 +-#define GPIOX_1 80 +-#define GPIOX_2 81 +-#define GPIOX_3 82 +-#define GPIOX_4 83 +-#define GPIOX_5 84 +-#define GPIOX_6 85 +-#define GPIOX_7 86 +-#define GPIOX_8 87 +-#define GPIOX_9 88 +-#define GPIOX_10 89 +-#define GPIOX_11 90 +-#define GPIOX_12 91 +-#define GPIOX_13 92 +-#define GPIOX_14 93 +-#define GPIOX_15 94 +-#define GPIOX_16 95 +-#define GPIOX_17 96 +-#define GPIOX_18 97 +-#define GPIOCLK_0 98 +-#define GPIOCLK_1 99 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/gpio/meson8-gpio.h b/scripts/dtc/include-prefixes/dt-bindings/gpio/meson8-gpio.h +deleted file mode 100644 +index e2d083104dfd..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/gpio/meson8-gpio.h ++++ /dev/null +@@ -1,151 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * GPIO definitions for Amlogic Meson8 SoCs +- * +- * Copyright (C) 2014 Beniamino Galvani +- */ +- +-#ifndef _DT_BINDINGS_MESON8_GPIO_H +-#define _DT_BINDINGS_MESON8_GPIO_H +- +-/* First GPIO chip */ +-#define GPIOX_0 0 +-#define GPIOX_1 1 +-#define GPIOX_2 2 +-#define GPIOX_3 3 +-#define GPIOX_4 4 +-#define GPIOX_5 5 +-#define GPIOX_6 6 +-#define GPIOX_7 7 +-#define GPIOX_8 8 +-#define GPIOX_9 9 +-#define GPIOX_10 10 +-#define GPIOX_11 11 +-#define GPIOX_12 12 +-#define GPIOX_13 13 +-#define GPIOX_14 14 +-#define GPIOX_15 15 +-#define GPIOX_16 16 +-#define GPIOX_17 17 +-#define GPIOX_18 18 +-#define GPIOX_19 19 +-#define GPIOX_20 20 +-#define GPIOX_21 21 +-#define GPIOY_0 22 +-#define GPIOY_1 23 +-#define GPIOY_2 24 +-#define GPIOY_3 25 +-#define GPIOY_4 26 +-#define GPIOY_5 27 +-#define GPIOY_6 28 +-#define GPIOY_7 29 +-#define GPIOY_8 30 +-#define GPIOY_9 31 +-#define GPIOY_10 32 +-#define GPIOY_11 33 +-#define GPIOY_12 34 +-#define GPIOY_13 35 +-#define GPIOY_14 36 +-#define GPIOY_15 37 +-#define GPIOY_16 38 +-#define GPIODV_0 39 +-#define GPIODV_1 40 +-#define GPIODV_2 41 +-#define GPIODV_3 42 +-#define GPIODV_4 43 +-#define GPIODV_5 44 +-#define GPIODV_6 45 +-#define GPIODV_7 46 +-#define GPIODV_8 47 +-#define GPIODV_9 48 +-#define GPIODV_10 49 +-#define GPIODV_11 50 +-#define GPIODV_12 51 +-#define GPIODV_13 52 +-#define GPIODV_14 53 +-#define GPIODV_15 54 +-#define GPIODV_16 55 +-#define GPIODV_17 56 +-#define GPIODV_18 57 +-#define GPIODV_19 58 +-#define GPIODV_20 59 +-#define GPIODV_21 60 +-#define GPIODV_22 61 +-#define GPIODV_23 62 +-#define GPIODV_24 63 +-#define GPIODV_25 64 +-#define GPIODV_26 65 +-#define GPIODV_27 66 +-#define GPIODV_28 67 +-#define GPIODV_29 68 +-#define GPIOH_0 69 +-#define GPIOH_1 70 +-#define GPIOH_2 71 +-#define GPIOH_3 72 +-#define GPIOH_4 73 +-#define GPIOH_5 74 +-#define GPIOH_6 75 +-#define GPIOH_7 76 +-#define GPIOH_8 77 +-#define GPIOH_9 78 +-#define GPIOZ_0 79 +-#define GPIOZ_1 80 +-#define GPIOZ_2 81 +-#define GPIOZ_3 82 +-#define GPIOZ_4 83 +-#define GPIOZ_5 84 +-#define GPIOZ_6 85 +-#define GPIOZ_7 86 +-#define GPIOZ_8 87 +-#define GPIOZ_9 88 +-#define GPIOZ_10 89 +-#define GPIOZ_11 90 +-#define GPIOZ_12 91 +-#define GPIOZ_13 92 +-#define GPIOZ_14 93 +-#define CARD_0 94 +-#define CARD_1 95 +-#define CARD_2 96 +-#define CARD_3 97 +-#define CARD_4 98 +-#define CARD_5 99 +-#define CARD_6 100 +-#define BOOT_0 101 +-#define BOOT_1 102 +-#define BOOT_2 103 +-#define BOOT_3 104 +-#define BOOT_4 105 +-#define BOOT_5 106 +-#define BOOT_6 107 +-#define BOOT_7 108 +-#define BOOT_8 109 +-#define BOOT_9 110 +-#define BOOT_10 111 +-#define BOOT_11 112 +-#define BOOT_12 113 +-#define BOOT_13 114 +-#define BOOT_14 115 +-#define BOOT_15 116 +-#define BOOT_16 117 +-#define BOOT_17 118 +-#define BOOT_18 119 +- +-/* Second GPIO chip */ +-#define GPIOAO_0 0 +-#define GPIOAO_1 1 +-#define GPIOAO_2 2 +-#define GPIOAO_3 3 +-#define GPIOAO_4 4 +-#define GPIOAO_5 5 +-#define GPIOAO_6 6 +-#define GPIOAO_7 7 +-#define GPIOAO_8 8 +-#define GPIOAO_9 9 +-#define GPIOAO_10 10 +-#define GPIOAO_11 11 +-#define GPIOAO_12 12 +-#define GPIOAO_13 13 +-#define GPIO_BSD_EN 14 +-#define GPIO_TEST_N 15 +- +-#endif /* _DT_BINDINGS_MESON8_GPIO_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/gpio/meson8b-gpio.h b/scripts/dtc/include-prefixes/dt-bindings/gpio/meson8b-gpio.h +deleted file mode 100644 +index 7c3bc0782eca..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/gpio/meson8b-gpio.h ++++ /dev/null +@@ -1,121 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * GPIO definitions for Amlogic Meson8b SoCs +- * +- * Copyright (C) 2015 Endless Mobile, Inc. +- * Author: Carlo Caione +- */ +- +-#ifndef _DT_BINDINGS_MESON8B_GPIO_H +-#define _DT_BINDINGS_MESON8B_GPIO_H +- +-/* EE (CBUS) GPIO chip */ +-#define GPIOX_0 0 +-#define GPIOX_1 1 +-#define GPIOX_2 2 +-#define GPIOX_3 3 +-#define GPIOX_4 4 +-#define GPIOX_5 5 +-#define GPIOX_6 6 +-#define GPIOX_7 7 +-#define GPIOX_8 8 +-#define GPIOX_9 9 +-#define GPIOX_10 10 +-#define GPIOX_11 11 +-#define GPIOX_16 12 +-#define GPIOX_17 13 +-#define GPIOX_18 14 +-#define GPIOX_19 15 +-#define GPIOX_20 16 +-#define GPIOX_21 17 +- +-#define GPIOY_0 18 +-#define GPIOY_1 19 +-#define GPIOY_3 20 +-#define GPIOY_6 21 +-#define GPIOY_7 22 +-#define GPIOY_8 23 +-#define GPIOY_9 24 +-#define GPIOY_10 25 +-#define GPIOY_11 26 +-#define GPIOY_12 27 +-#define GPIOY_13 28 +-#define GPIOY_14 29 +- +-#define GPIODV_9 30 +-#define GPIODV_24 31 +-#define GPIODV_25 32 +-#define GPIODV_26 33 +-#define GPIODV_27 34 +-#define GPIODV_28 35 +-#define GPIODV_29 36 +- +-#define GPIOH_0 37 +-#define GPIOH_1 38 +-#define GPIOH_2 39 +-#define GPIOH_3 40 +-#define GPIOH_4 41 +-#define GPIOH_5 42 +-#define GPIOH_6 43 +-#define GPIOH_7 44 +-#define GPIOH_8 45 +-#define GPIOH_9 46 +- +-#define CARD_0 47 +-#define CARD_1 48 +-#define CARD_2 49 +-#define CARD_3 50 +-#define CARD_4 51 +-#define CARD_5 52 +-#define CARD_6 53 +- +-#define BOOT_0 54 +-#define BOOT_1 55 +-#define BOOT_2 56 +-#define BOOT_3 57 +-#define BOOT_4 58 +-#define BOOT_5 59 +-#define BOOT_6 60 +-#define BOOT_7 61 +-#define BOOT_8 62 +-#define BOOT_9 63 +-#define BOOT_10 64 +-#define BOOT_11 65 +-#define BOOT_12 66 +-#define BOOT_13 67 +-#define BOOT_14 68 +-#define BOOT_15 69 +-#define BOOT_16 70 +-#define BOOT_17 71 +-#define BOOT_18 72 +- +-#define DIF_0_P 73 +-#define DIF_0_N 74 +-#define DIF_1_P 75 +-#define DIF_1_N 76 +-#define DIF_2_P 77 +-#define DIF_2_N 78 +-#define DIF_3_P 79 +-#define DIF_3_N 80 +-#define DIF_4_P 81 +-#define DIF_4_N 82 +- +-/* AO GPIO chip */ +-#define GPIOAO_0 0 +-#define GPIOAO_1 1 +-#define GPIOAO_2 2 +-#define GPIOAO_3 3 +-#define GPIOAO_4 4 +-#define GPIOAO_5 5 +-#define GPIOAO_6 6 +-#define GPIOAO_7 7 +-#define GPIOAO_8 8 +-#define GPIOAO_9 9 +-#define GPIOAO_10 10 +-#define GPIOAO_11 11 +-#define GPIOAO_12 12 +-#define GPIOAO_13 13 +-#define GPIO_BSD_EN 14 +-#define GPIO_TEST_N 15 +- +-#endif /* _DT_BINDINGS_MESON8B_GPIO_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/gpio/msc313-gpio.h b/scripts/dtc/include-prefixes/dt-bindings/gpio/msc313-gpio.h +deleted file mode 100644 +index 2dd56683d3c1..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/gpio/msc313-gpio.h ++++ /dev/null +@@ -1,53 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +-/* +- * GPIO definitions for MStar/SigmaStar MSC313 and later SoCs +- * +- * Copyright (C) 2020 Daniel Palmer +- */ +- +-#ifndef _DT_BINDINGS_MSC313_GPIO_H +-#define _DT_BINDINGS_MSC313_GPIO_H +- +-#define MSC313_GPIO_FUART 0 +-#define MSC313_GPIO_FUART_RX (MSC313_GPIO_FUART + 0) +-#define MSC313_GPIO_FUART_TX (MSC313_GPIO_FUART + 1) +-#define MSC313_GPIO_FUART_CTS (MSC313_GPIO_FUART + 2) +-#define MSC313_GPIO_FUART_RTS (MSC313_GPIO_FUART + 3) +- +-#define MSC313_GPIO_SR (MSC313_GPIO_FUART_RTS + 1) +-#define MSC313_GPIO_SR_IO2 (MSC313_GPIO_SR + 0) +-#define MSC313_GPIO_SR_IO3 (MSC313_GPIO_SR + 1) +-#define MSC313_GPIO_SR_IO4 (MSC313_GPIO_SR + 2) +-#define MSC313_GPIO_SR_IO5 (MSC313_GPIO_SR + 3) +-#define MSC313_GPIO_SR_IO6 (MSC313_GPIO_SR + 4) +-#define MSC313_GPIO_SR_IO7 (MSC313_GPIO_SR + 5) +-#define MSC313_GPIO_SR_IO8 (MSC313_GPIO_SR + 6) +-#define MSC313_GPIO_SR_IO9 (MSC313_GPIO_SR + 7) +-#define MSC313_GPIO_SR_IO10 (MSC313_GPIO_SR + 8) +-#define MSC313_GPIO_SR_IO11 (MSC313_GPIO_SR + 9) +-#define MSC313_GPIO_SR_IO12 (MSC313_GPIO_SR + 10) +-#define MSC313_GPIO_SR_IO13 (MSC313_GPIO_SR + 11) +-#define MSC313_GPIO_SR_IO14 (MSC313_GPIO_SR + 12) +-#define MSC313_GPIO_SR_IO15 (MSC313_GPIO_SR + 13) +-#define MSC313_GPIO_SR_IO16 (MSC313_GPIO_SR + 14) +-#define MSC313_GPIO_SR_IO17 (MSC313_GPIO_SR + 15) +- +-#define MSC313_GPIO_SD (MSC313_GPIO_SR_IO17 + 1) +-#define MSC313_GPIO_SD_CLK (MSC313_GPIO_SD + 0) +-#define MSC313_GPIO_SD_CMD (MSC313_GPIO_SD + 1) +-#define MSC313_GPIO_SD_D0 (MSC313_GPIO_SD + 2) +-#define MSC313_GPIO_SD_D1 (MSC313_GPIO_SD + 3) +-#define MSC313_GPIO_SD_D2 (MSC313_GPIO_SD + 4) +-#define MSC313_GPIO_SD_D3 (MSC313_GPIO_SD + 5) +- +-#define MSC313_GPIO_I2C1 (MSC313_GPIO_SD_D3 + 1) +-#define MSC313_GPIO_I2C1_SCL (MSC313_GPIO_I2C1 + 0) +-#define MSC313_GPIO_I2C1_SDA (MSC313_GPIO_I2C1 + 1) +- +-#define MSC313_GPIO_SPI0 (MSC313_GPIO_I2C1_SDA + 1) +-#define MSC313_GPIO_SPI0_CZ (MSC313_GPIO_SPI0 + 0) +-#define MSC313_GPIO_SPI0_CK (MSC313_GPIO_SPI0 + 1) +-#define MSC313_GPIO_SPI0_DI (MSC313_GPIO_SPI0 + 2) +-#define MSC313_GPIO_SPI0_DO (MSC313_GPIO_SPI0 + 3) +- +-#endif /* _DT_BINDINGS_MSC313_GPIO_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/gpio/tegra-gpio.h b/scripts/dtc/include-prefixes/dt-bindings/gpio/tegra-gpio.h +deleted file mode 100644 +index 7625dbc577c2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/gpio/tegra-gpio.h ++++ /dev/null +@@ -1,52 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for binding nvidia,tegra*-gpio. +- * +- * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below +- * provide names for this. +- * +- * The second cell contains standard flag values specified in gpio.h. +- */ +- +-#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H +-#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H +- +-#include +- +-#define TEGRA_GPIO_PORT_A 0 +-#define TEGRA_GPIO_PORT_B 1 +-#define TEGRA_GPIO_PORT_C 2 +-#define TEGRA_GPIO_PORT_D 3 +-#define TEGRA_GPIO_PORT_E 4 +-#define TEGRA_GPIO_PORT_F 5 +-#define TEGRA_GPIO_PORT_G 6 +-#define TEGRA_GPIO_PORT_H 7 +-#define TEGRA_GPIO_PORT_I 8 +-#define TEGRA_GPIO_PORT_J 9 +-#define TEGRA_GPIO_PORT_K 10 +-#define TEGRA_GPIO_PORT_L 11 +-#define TEGRA_GPIO_PORT_M 12 +-#define TEGRA_GPIO_PORT_N 13 +-#define TEGRA_GPIO_PORT_O 14 +-#define TEGRA_GPIO_PORT_P 15 +-#define TEGRA_GPIO_PORT_Q 16 +-#define TEGRA_GPIO_PORT_R 17 +-#define TEGRA_GPIO_PORT_S 18 +-#define TEGRA_GPIO_PORT_T 19 +-#define TEGRA_GPIO_PORT_U 20 +-#define TEGRA_GPIO_PORT_V 21 +-#define TEGRA_GPIO_PORT_W 22 +-#define TEGRA_GPIO_PORT_X 23 +-#define TEGRA_GPIO_PORT_Y 24 +-#define TEGRA_GPIO_PORT_Z 25 +-#define TEGRA_GPIO_PORT_AA 26 +-#define TEGRA_GPIO_PORT_BB 27 +-#define TEGRA_GPIO_PORT_CC 28 +-#define TEGRA_GPIO_PORT_DD 29 +-#define TEGRA_GPIO_PORT_EE 30 +-#define TEGRA_GPIO_PORT_FF 31 +- +-#define TEGRA_GPIO(port, offset) \ +- ((TEGRA_GPIO_PORT_##port * 8) + offset) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/gpio/tegra186-gpio.h b/scripts/dtc/include-prefixes/dt-bindings/gpio/tegra186-gpio.h +deleted file mode 100644 +index af0d9583be70..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/gpio/tegra186-gpio.h ++++ /dev/null +@@ -1,57 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for binding nvidia,tegra186-gpio*. +- * +- * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below +- * provide names for this. +- * +- * The second cell contains standard flag values specified in gpio.h. +- */ +- +-#ifndef _DT_BINDINGS_GPIO_TEGRA186_GPIO_H +-#define _DT_BINDINGS_GPIO_TEGRA186_GPIO_H +- +-#include +- +-/* GPIOs implemented by main GPIO controller */ +-#define TEGRA186_MAIN_GPIO_PORT_A 0 +-#define TEGRA186_MAIN_GPIO_PORT_B 1 +-#define TEGRA186_MAIN_GPIO_PORT_C 2 +-#define TEGRA186_MAIN_GPIO_PORT_D 3 +-#define TEGRA186_MAIN_GPIO_PORT_E 4 +-#define TEGRA186_MAIN_GPIO_PORT_F 5 +-#define TEGRA186_MAIN_GPIO_PORT_G 6 +-#define TEGRA186_MAIN_GPIO_PORT_H 7 +-#define TEGRA186_MAIN_GPIO_PORT_I 8 +-#define TEGRA186_MAIN_GPIO_PORT_J 9 +-#define TEGRA186_MAIN_GPIO_PORT_K 10 +-#define TEGRA186_MAIN_GPIO_PORT_L 11 +-#define TEGRA186_MAIN_GPIO_PORT_M 12 +-#define TEGRA186_MAIN_GPIO_PORT_N 13 +-#define TEGRA186_MAIN_GPIO_PORT_O 14 +-#define TEGRA186_MAIN_GPIO_PORT_P 15 +-#define TEGRA186_MAIN_GPIO_PORT_Q 16 +-#define TEGRA186_MAIN_GPIO_PORT_R 17 +-#define TEGRA186_MAIN_GPIO_PORT_T 18 +-#define TEGRA186_MAIN_GPIO_PORT_X 19 +-#define TEGRA186_MAIN_GPIO_PORT_Y 20 +-#define TEGRA186_MAIN_GPIO_PORT_BB 21 +-#define TEGRA186_MAIN_GPIO_PORT_CC 22 +- +-#define TEGRA186_MAIN_GPIO(port, offset) \ +- ((TEGRA186_MAIN_GPIO_PORT_##port * 8) + offset) +- +-/* GPIOs implemented by AON GPIO controller */ +-#define TEGRA186_AON_GPIO_PORT_S 0 +-#define TEGRA186_AON_GPIO_PORT_U 1 +-#define TEGRA186_AON_GPIO_PORT_V 2 +-#define TEGRA186_AON_GPIO_PORT_W 3 +-#define TEGRA186_AON_GPIO_PORT_Z 4 +-#define TEGRA186_AON_GPIO_PORT_AA 5 +-#define TEGRA186_AON_GPIO_PORT_EE 6 +-#define TEGRA186_AON_GPIO_PORT_FF 7 +- +-#define TEGRA186_AON_GPIO(port, offset) \ +- ((TEGRA186_AON_GPIO_PORT_##port * 8) + offset) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/gpio/tegra194-gpio.h b/scripts/dtc/include-prefixes/dt-bindings/gpio/tegra194-gpio.h +deleted file mode 100644 +index ede860225f6b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/gpio/tegra194-gpio.h ++++ /dev/null +@@ -1,61 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ +- +-/* +- * This header provides constants for binding nvidia,tegra194-gpio*. +- * +- * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below +- * provide names for this. +- * +- * The second cell contains standard flag values specified in gpio.h. +- */ +- +-#ifndef _DT_BINDINGS_GPIO_TEGRA194_GPIO_H +-#define _DT_BINDINGS_GPIO_TEGRA194_GPIO_H +- +-#include +- +-/* GPIOs implemented by main GPIO controller */ +-#define TEGRA194_MAIN_GPIO_PORT_A 0 +-#define TEGRA194_MAIN_GPIO_PORT_B 1 +-#define TEGRA194_MAIN_GPIO_PORT_C 2 +-#define TEGRA194_MAIN_GPIO_PORT_D 3 +-#define TEGRA194_MAIN_GPIO_PORT_E 4 +-#define TEGRA194_MAIN_GPIO_PORT_F 5 +-#define TEGRA194_MAIN_GPIO_PORT_G 6 +-#define TEGRA194_MAIN_GPIO_PORT_H 7 +-#define TEGRA194_MAIN_GPIO_PORT_I 8 +-#define TEGRA194_MAIN_GPIO_PORT_J 9 +-#define TEGRA194_MAIN_GPIO_PORT_K 10 +-#define TEGRA194_MAIN_GPIO_PORT_L 11 +-#define TEGRA194_MAIN_GPIO_PORT_M 12 +-#define TEGRA194_MAIN_GPIO_PORT_N 13 +-#define TEGRA194_MAIN_GPIO_PORT_O 14 +-#define TEGRA194_MAIN_GPIO_PORT_P 15 +-#define TEGRA194_MAIN_GPIO_PORT_Q 16 +-#define TEGRA194_MAIN_GPIO_PORT_R 17 +-#define TEGRA194_MAIN_GPIO_PORT_S 18 +-#define TEGRA194_MAIN_GPIO_PORT_T 19 +-#define TEGRA194_MAIN_GPIO_PORT_U 20 +-#define TEGRA194_MAIN_GPIO_PORT_V 21 +-#define TEGRA194_MAIN_GPIO_PORT_W 22 +-#define TEGRA194_MAIN_GPIO_PORT_X 23 +-#define TEGRA194_MAIN_GPIO_PORT_Y 24 +-#define TEGRA194_MAIN_GPIO_PORT_Z 25 +-#define TEGRA194_MAIN_GPIO_PORT_FF 26 +-#define TEGRA194_MAIN_GPIO_PORT_GG 27 +- +-#define TEGRA194_MAIN_GPIO(port, offset) \ +- ((TEGRA194_MAIN_GPIO_PORT_##port * 8) + offset) +- +-/* GPIOs implemented by AON GPIO controller */ +-#define TEGRA194_AON_GPIO_PORT_AA 0 +-#define TEGRA194_AON_GPIO_PORT_BB 1 +-#define TEGRA194_AON_GPIO_PORT_CC 2 +-#define TEGRA194_AON_GPIO_PORT_DD 3 +-#define TEGRA194_AON_GPIO_PORT_EE 4 +- +-#define TEGRA194_AON_GPIO(port, offset) \ +- ((TEGRA194_AON_GPIO_PORT_##port * 8) + offset) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/gpio/uniphier-gpio.h b/scripts/dtc/include-prefixes/dt-bindings/gpio/uniphier-gpio.h +deleted file mode 100644 +index 9f0ad174f61c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/gpio/uniphier-gpio.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-/* +- * Copyright (C) 2017 Socionext Inc. +- * Author: Masahiro Yamada +- */ +- +-#ifndef _DT_BINDINGS_GPIO_UNIPHIER_H +-#define _DT_BINDINGS_GPIO_UNIPHIER_H +- +-#define UNIPHIER_GPIO_LINES_PER_BANK 8 +- +-#define UNIPHIER_GPIO_IRQ_OFFSET ((UNIPHIER_GPIO_LINES_PER_BANK) * 15) +- +-#define UNIPHIER_GPIO_PORT(bank, line) \ +- ((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line)) +- +-#define UNIPHIER_GPIO_IRQ(n) ((UNIPHIER_GPIO_IRQ_OFFSET) + (n)) +- +-#endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/i2c/i2c.h b/scripts/dtc/include-prefixes/dt-bindings/i2c/i2c.h +deleted file mode 100644 +index 0c12c38dfa2e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/i2c/i2c.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * This header provides constants for I2C bindings +- * +- * Copyright (C) 2015 by Sang Engineering +- * Copyright (C) 2015 by Renesas Electronics Corporation +- * +- * Wolfram Sang +- */ +- +-#ifndef _DT_BINDINGS_I2C_I2C_H +-#define _DT_BINDINGS_I2C_I2C_H +- +-#define I2C_TEN_BIT_ADDRESS (1 << 31) +-#define I2C_OWN_SLAVE_ADDRESS (1 << 30) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/iio/adc/at91-sama5d2_adc.h b/scripts/dtc/include-prefixes/dt-bindings/iio/adc/at91-sama5d2_adc.h +deleted file mode 100644 +index 70f99dbdbb42..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/iio/adc/at91-sama5d2_adc.h ++++ /dev/null +@@ -1,16 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for configuring the AT91 SAMA5D2 ADC +- */ +- +-#ifndef _DT_BINDINGS_IIO_ADC_AT91_SAMA5D2_ADC_H +-#define _DT_BINDINGS_IIO_ADC_AT91_SAMA5D2_ADC_H +- +-/* X relative position channel index */ +-#define AT91_SAMA5D2_ADC_X_CHANNEL 24 +-/* Y relative position channel index */ +-#define AT91_SAMA5D2_ADC_Y_CHANNEL 25 +-/* pressure channel index */ +-#define AT91_SAMA5D2_ADC_P_CHANNEL 26 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/iio/adc/fsl-imx25-gcq.h b/scripts/dtc/include-prefixes/dt-bindings/iio/adc/fsl-imx25-gcq.h +deleted file mode 100644 +index 08ef4d298b94..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/iio/adc/fsl-imx25-gcq.h ++++ /dev/null +@@ -1,19 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for configuring the I.MX25 ADC +- */ +- +-#ifndef _DT_BINDINGS_IIO_ADC_FS_IMX25_GCQ_H +-#define _DT_BINDINGS_IIO_ADC_FS_IMX25_GCQ_H +- +-#define MX25_ADC_REFP_YP 0 /* YP voltage reference */ +-#define MX25_ADC_REFP_XP 1 /* XP voltage reference */ +-#define MX25_ADC_REFP_EXT 2 /* External voltage reference */ +-#define MX25_ADC_REFP_INT 3 /* Internal voltage reference */ +- +-#define MX25_ADC_REFN_XN 0 /* XN ground reference */ +-#define MX25_ADC_REFN_YN 1 /* YN ground reference */ +-#define MX25_ADC_REFN_NGND 2 /* Internal ground reference */ +-#define MX25_ADC_REFN_NGND2 3 /* External ground reference */ +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/iio/adc/ingenic,adc.h b/scripts/dtc/include-prefixes/dt-bindings/iio/adc/ingenic,adc.h +deleted file mode 100644 +index a6ccc031635b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/iio/adc/ingenic,adc.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +- +-#ifndef _DT_BINDINGS_IIO_ADC_INGENIC_ADC_H +-#define _DT_BINDINGS_IIO_ADC_INGENIC_ADC_H +- +-/* ADC channel idx. */ +-#define INGENIC_ADC_AUX 0 +-#define INGENIC_ADC_BATTERY 1 +-#define INGENIC_ADC_AUX2 2 +-#define INGENIC_ADC_TOUCH_XP 3 +-#define INGENIC_ADC_TOUCH_YP 4 +-#define INGENIC_ADC_TOUCH_XN 5 +-#define INGENIC_ADC_TOUCH_YN 6 +-#define INGENIC_ADC_TOUCH_XD 7 +-#define INGENIC_ADC_TOUCH_YD 8 +-#define INGENIC_ADC_AUX0 9 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/iio/adi,ad5592r.h b/scripts/dtc/include-prefixes/dt-bindings/iio/adi,ad5592r.h +deleted file mode 100644 +index 9f8c7b808cd1..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/iio/adi,ad5592r.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +- +-#ifndef _DT_BINDINGS_ADI_AD5592R_H +-#define _DT_BINDINGS_ADI_AD5592R_H +- +-#define CH_MODE_UNUSED 0 +-#define CH_MODE_ADC 1 +-#define CH_MODE_DAC 2 +-#define CH_MODE_DAC_AND_ADC 3 +-#define CH_MODE_GPIO 8 +- +-#define CH_OFFSTATE_PULLDOWN 0 +-#define CH_OFFSTATE_OUT_LOW 1 +-#define CH_OFFSTATE_OUT_HIGH 2 +-#define CH_OFFSTATE_OUT_TRISTATE 3 +- +-#endif /* _DT_BINDINGS_ADI_AD5592R_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/iio/qcom,spmi-adc7-pm8350.h b/scripts/dtc/include-prefixes/dt-bindings/iio/qcom,spmi-adc7-pm8350.h +deleted file mode 100644 +index 9426f27a1946..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/iio/qcom,spmi-adc7-pm8350.h ++++ /dev/null +@@ -1,67 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H +-#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H +- +-#ifndef PM8350_SID +-#define PM8350_SID 1 +-#endif +- +-/* ADC channels for PM8350_ADC for PMIC7 */ +-#define PM8350_ADC7_REF_GND (PM8350_SID << 8 | 0x0) +-#define PM8350_ADC7_1P25VREF (PM8350_SID << 8 | 0x01) +-#define PM8350_ADC7_VREF_VADC (PM8350_SID << 8 | 0x02) +-#define PM8350_ADC7_DIE_TEMP (PM8350_SID << 8 | 0x03) +- +-#define PM8350_ADC7_AMUX_THM1 (PM8350_SID << 8 | 0x04) +-#define PM8350_ADC7_AMUX_THM2 (PM8350_SID << 8 | 0x05) +-#define PM8350_ADC7_AMUX_THM3 (PM8350_SID << 8 | 0x06) +-#define PM8350_ADC7_AMUX_THM4 (PM8350_SID << 8 | 0x07) +-#define PM8350_ADC7_AMUX_THM5 (PM8350_SID << 8 | 0x08) +-#define PM8350_ADC7_GPIO1 (PM8350_SID << 8 | 0x0a) +-#define PM8350_ADC7_GPIO2 (PM8350_SID << 8 | 0x0b) +-#define PM8350_ADC7_GPIO3 (PM8350_SID << 8 | 0x0c) +-#define PM8350_ADC7_GPIO4 (PM8350_SID << 8 | 0x0d) +- +-/* 30k pull-up1 */ +-#define PM8350_ADC7_AMUX_THM1_30K_PU (PM8350_SID << 8 | 0x24) +-#define PM8350_ADC7_AMUX_THM2_30K_PU (PM8350_SID << 8 | 0x25) +-#define PM8350_ADC7_AMUX_THM3_30K_PU (PM8350_SID << 8 | 0x26) +-#define PM8350_ADC7_AMUX_THM4_30K_PU (PM8350_SID << 8 | 0x27) +-#define PM8350_ADC7_AMUX_THM5_30K_PU (PM8350_SID << 8 | 0x28) +-#define PM8350_ADC7_GPIO1_30K_PU (PM8350_SID << 8 | 0x2a) +-#define PM8350_ADC7_GPIO2_30K_PU (PM8350_SID << 8 | 0x2b) +-#define PM8350_ADC7_GPIO3_30K_PU (PM8350_SID << 8 | 0x2c) +-#define PM8350_ADC7_GPIO4_30K_PU (PM8350_SID << 8 | 0x2d) +- +-/* 100k pull-up2 */ +-#define PM8350_ADC7_AMUX_THM1_100K_PU (PM8350_SID << 8 | 0x44) +-#define PM8350_ADC7_AMUX_THM2_100K_PU (PM8350_SID << 8 | 0x45) +-#define PM8350_ADC7_AMUX_THM3_100K_PU (PM8350_SID << 8 | 0x46) +-#define PM8350_ADC7_AMUX_THM4_100K_PU (PM8350_SID << 8 | 0x47) +-#define PM8350_ADC7_AMUX_THM5_100K_PU (PM8350_SID << 8 | 0x48) +-#define PM8350_ADC7_GPIO1_100K_PU (PM8350_SID << 8 | 0x4a) +-#define PM8350_ADC7_GPIO2_100K_PU (PM8350_SID << 8 | 0x4b) +-#define PM8350_ADC7_GPIO3_100K_PU (PM8350_SID << 8 | 0x4c) +-#define PM8350_ADC7_GPIO4_100K_PU (PM8350_SID << 8 | 0x4d) +- +-/* 400k pull-up3 */ +-#define PM8350_ADC7_AMUX_THM1_400K_PU (PM8350_SID << 8 | 0x64) +-#define PM8350_ADC7_AMUX_THM2_400K_PU (PM8350_SID << 8 | 0x65) +-#define PM8350_ADC7_AMUX_THM3_400K_PU (PM8350_SID << 8 | 0x66) +-#define PM8350_ADC7_AMUX_THM4_400K_PU (PM8350_SID << 8 | 0x67) +-#define PM8350_ADC7_AMUX_THM5_400K_PU (PM8350_SID << 8 | 0x68) +-#define PM8350_ADC7_GPIO1_400K_PU (PM8350_SID << 8 | 0x6a) +-#define PM8350_ADC7_GPIO2_400K_PU (PM8350_SID << 8 | 0x6b) +-#define PM8350_ADC7_GPIO3_400K_PU (PM8350_SID << 8 | 0x6c) +-#define PM8350_ADC7_GPIO4_400K_PU (PM8350_SID << 8 | 0x6d) +- +-/* 1/3 Divider */ +-#define PM8350_ADC7_GPIO4_DIV3 (PM8350_SID << 8 | 0x8d) +- +-#define PM8350_ADC7_VPH_PWR (PM8350_SID << 8 | 0x8e) +- +-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h b/scripts/dtc/include-prefixes/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h +deleted file mode 100644 +index dc2497c27e16..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h ++++ /dev/null +@@ -1,88 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2020 The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H +-#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H +- +-#ifndef PM8350B_SID +-#define PM8350B_SID 3 +-#endif +- +-/* ADC channels for PM8350B_ADC for PMIC7 */ +-#define PM8350B_ADC7_REF_GND (PM8350B_SID << 8 | 0x0) +-#define PM8350B_ADC7_1P25VREF (PM8350B_SID << 8 | 0x01) +-#define PM8350B_ADC7_VREF_VADC (PM8350B_SID << 8 | 0x02) +-#define PM8350B_ADC7_DIE_TEMP (PM8350B_SID << 8 | 0x03) +- +-#define PM8350B_ADC7_AMUX_THM1 (PM8350B_SID << 8 | 0x04) +-#define PM8350B_ADC7_AMUX_THM2 (PM8350B_SID << 8 | 0x05) +-#define PM8350B_ADC7_AMUX_THM3 (PM8350B_SID << 8 | 0x06) +-#define PM8350B_ADC7_AMUX_THM4 (PM8350B_SID << 8 | 0x07) +-#define PM8350B_ADC7_AMUX_THM5 (PM8350B_SID << 8 | 0x08) +-#define PM8350B_ADC7_AMUX_THM6 (PM8350B_SID << 8 | 0x09) +-#define PM8350B_ADC7_GPIO1 (PM8350B_SID << 8 | 0x0a) +-#define PM8350B_ADC7_GPIO2 (PM8350B_SID << 8 | 0x0b) +-#define PM8350B_ADC7_GPIO3 (PM8350B_SID << 8 | 0x0c) +-#define PM8350B_ADC7_GPIO4 (PM8350B_SID << 8 | 0x0d) +- +-#define PM8350B_ADC7_CHG_TEMP (PM8350B_SID << 8 | 0x10) +-#define PM8350B_ADC7_USB_IN_V_16 (PM8350B_SID << 8 | 0x11) +-#define PM8350B_ADC7_VDC_16 (PM8350B_SID << 8 | 0x12) +-#define PM8350B_ADC7_CC1_ID (PM8350B_SID << 8 | 0x13) +-#define PM8350B_ADC7_VREF_BAT_THERM (PM8350B_SID << 8 | 0x15) +-#define PM8350B_ADC7_IIN_FB (PM8350B_SID << 8 | 0x17) +- +-/* 30k pull-up1 */ +-#define PM8350B_ADC7_AMUX_THM1_30K_PU (PM8350B_SID << 8 | 0x24) +-#define PM8350B_ADC7_AMUX_THM2_30K_PU (PM8350B_SID << 8 | 0x25) +-#define PM8350B_ADC7_AMUX_THM3_30K_PU (PM8350B_SID << 8 | 0x26) +-#define PM8350B_ADC7_AMUX_THM4_30K_PU (PM8350B_SID << 8 | 0x27) +-#define PM8350B_ADC7_AMUX_THM5_30K_PU (PM8350B_SID << 8 | 0x28) +-#define PM8350B_ADC7_AMUX_THM6_30K_PU (PM8350B_SID << 8 | 0x29) +-#define PM8350B_ADC7_GPIO1_30K_PU (PM8350B_SID << 8 | 0x2a) +-#define PM8350B_ADC7_GPIO2_30K_PU (PM8350B_SID << 8 | 0x2b) +-#define PM8350B_ADC7_GPIO3_30K_PU (PM8350B_SID << 8 | 0x2c) +-#define PM8350B_ADC7_GPIO4_30K_PU (PM8350B_SID << 8 | 0x2d) +-#define PM8350B_ADC7_CC1_ID_30K_PU (PM8350B_SID << 8 | 0x33) +- +-/* 100k pull-up2 */ +-#define PM8350B_ADC7_AMUX_THM1_100K_PU (PM8350B_SID << 8 | 0x44) +-#define PM8350B_ADC7_AMUX_THM2_100K_PU (PM8350B_SID << 8 | 0x45) +-#define PM8350B_ADC7_AMUX_THM3_100K_PU (PM8350B_SID << 8 | 0x46) +-#define PM8350B_ADC7_AMUX_THM4_100K_PU (PM8350B_SID << 8 | 0x47) +-#define PM8350B_ADC7_AMUX_THM5_100K_PU (PM8350B_SID << 8 | 0x48) +-#define PM8350B_ADC7_AMUX_THM6_100K_PU (PM8350B_SID << 8 | 0x49) +-#define PM8350B_ADC7_GPIO1_100K_PU (PM8350B_SID << 8 | 0x4a) +-#define PM8350B_ADC7_GPIO2_100K_PU (PM8350B_SID << 8 | 0x4b) +-#define PM8350B_ADC7_GPIO3_100K_PU (PM8350B_SID << 8 | 0x4c) +-#define PM8350B_ADC7_GPIO4_100K_PU (PM8350B_SID << 8 | 0x4d) +-#define PM8350B_ADC7_CC1_ID_100K_PU (PM8350B_SID << 8 | 0x53) +- +-/* 400k pull-up3 */ +-#define PM8350B_ADC7_AMUX_THM1_400K_PU (PM8350B_SID << 8 | 0x64) +-#define PM8350B_ADC7_AMUX_THM2_400K_PU (PM8350B_SID << 8 | 0x65) +-#define PM8350B_ADC7_AMUX_THM3_400K_PU (PM8350B_SID << 8 | 0x66) +-#define PM8350B_ADC7_AMUX_THM4_400K_PU (PM8350B_SID << 8 | 0x67) +-#define PM8350B_ADC7_AMUX_THM5_400K_PU (PM8350B_SID << 8 | 0x68) +-#define PM8350B_ADC7_AMUX_THM6_400K_PU (PM8350B_SID << 8 | 0x69) +-#define PM8350B_ADC7_GPIO1_400K_PU (PM8350B_SID << 8 | 0x6a) +-#define PM8350B_ADC7_GPIO2_400K_PU (PM8350B_SID << 8 | 0x6b) +-#define PM8350B_ADC7_GPIO3_400K_PU (PM8350B_SID << 8 | 0x6c) +-#define PM8350B_ADC7_GPIO4_400K_PU (PM8350B_SID << 8 | 0x6d) +-#define PM8350B_ADC7_CC1_ID_400K_PU (PM8350B_SID << 8 | 0x73) +- +-/* 1/3 Divider */ +-#define PM8350B_ADC7_GPIO1_DIV3 (PM8350B_SID << 8 | 0x8a) +-#define PM8350B_ADC7_GPIO2_DIV3 (PM8350B_SID << 8 | 0x8b) +-#define PM8350B_ADC7_GPIO3_DIV3 (PM8350B_SID << 8 | 0x8c) +-#define PM8350B_ADC7_GPIO4_DIV3 (PM8350B_SID << 8 | 0x8d) +- +-#define PM8350B_ADC7_VPH_PWR (PM8350B_SID << 8 | 0x8e) +-#define PM8350B_ADC7_VBAT_SNS (PM8350B_SID << 8 | 0x8f) +- +-#define PM8350B_ADC7_SBUx (PM8350B_SID << 8 | 0x94) +-#define PM8350B_ADC7_VBAT_2S_MID (PM8350B_SID << 8 | 0x96) +- +-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h b/scripts/dtc/include-prefixes/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h +deleted file mode 100644 +index 6c296870e95b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h ++++ /dev/null +@@ -1,46 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2020 The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H +-#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H +- +-#ifndef PMK8350_SID +-#define PMK8350_SID 0 +-#endif +- +-/* ADC channels for PMK8350_ADC for PMIC7 */ +-#define PMK8350_ADC7_REF_GND (PMK8350_SID << 8 | 0x0) +-#define PMK8350_ADC7_1P25VREF (PMK8350_SID << 8 | 0x01) +-#define PMK8350_ADC7_VREF_VADC (PMK8350_SID << 8 | 0x02) +-#define PMK8350_ADC7_DIE_TEMP (PMK8350_SID << 8 | 0x03) +- +-#define PMK8350_ADC7_AMUX_THM1 (PMK8350_SID << 8 | 0x04) +-#define PMK8350_ADC7_AMUX_THM2 (PMK8350_SID << 8 | 0x05) +-#define PMK8350_ADC7_AMUX_THM3 (PMK8350_SID << 8 | 0x06) +-#define PMK8350_ADC7_AMUX_THM4 (PMK8350_SID << 8 | 0x07) +-#define PMK8350_ADC7_AMUX_THM5 (PMK8350_SID << 8 | 0x08) +- +-/* 30k pull-up1 */ +-#define PMK8350_ADC7_AMUX_THM1_30K_PU (PMK8350_SID << 8 | 0x24) +-#define PMK8350_ADC7_AMUX_THM2_30K_PU (PMK8350_SID << 8 | 0x25) +-#define PMK8350_ADC7_AMUX_THM3_30K_PU (PMK8350_SID << 8 | 0x26) +-#define PMK8350_ADC7_AMUX_THM4_30K_PU (PMK8350_SID << 8 | 0x27) +-#define PMK8350_ADC7_AMUX_THM5_30K_PU (PMK8350_SID << 8 | 0x28) +- +-/* 100k pull-up2 */ +-#define PMK8350_ADC7_AMUX_THM1_100K_PU (PMK8350_SID << 8 | 0x44) +-#define PMK8350_ADC7_AMUX_THM2_100K_PU (PMK8350_SID << 8 | 0x45) +-#define PMK8350_ADC7_AMUX_THM3_100K_PU (PMK8350_SID << 8 | 0x46) +-#define PMK8350_ADC7_AMUX_THM4_100K_PU (PMK8350_SID << 8 | 0x47) +-#define PMK8350_ADC7_AMUX_THM5_100K_PU (PMK8350_SID << 8 | 0x48) +- +-/* 400k pull-up3 */ +-#define PMK8350_ADC7_AMUX_THM1_400K_PU (PMK8350_SID << 8 | 0x64) +-#define PMK8350_ADC7_AMUX_THM2_400K_PU (PMK8350_SID << 8 | 0x65) +-#define PMK8350_ADC7_AMUX_THM3_400K_PU (PMK8350_SID << 8 | 0x66) +-#define PMK8350_ADC7_AMUX_THM4_400K_PU (PMK8350_SID << 8 | 0x67) +-#define PMK8350_ADC7_AMUX_THM5_400K_PU (PMK8350_SID << 8 | 0x68) +- +-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h b/scripts/dtc/include-prefixes/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h +deleted file mode 100644 +index d6df1b19e5ff..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h ++++ /dev/null +@@ -1,28 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2020 The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H +-#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H +- +-#ifndef PMR735A_SID +-#define PMR735A_SID 4 +-#endif +- +-/* ADC channels for PMR735A_ADC for PMIC7 */ +-#define PMR735A_ADC7_REF_GND (PMR735A_SID << 8 | 0x0) +-#define PMR735A_ADC7_1P25VREF (PMR735A_SID << 8 | 0x01) +-#define PMR735A_ADC7_VREF_VADC (PMR735A_SID << 8 | 0x02) +-#define PMR735A_ADC7_DIE_TEMP (PMR735A_SID << 8 | 0x03) +- +-#define PMR735A_ADC7_GPIO1 (PMR735A_SID << 8 | 0x0a) +-#define PMR735A_ADC7_GPIO2 (PMR735A_SID << 8 | 0x0b) +-#define PMR735A_ADC7_GPIO3 (PMR735A_SID << 8 | 0x0c) +- +-/* 100k pull-up2 */ +-#define PMR735A_ADC7_GPIO1_100K_PU (PMR735A_SID << 8 | 0x4a) +-#define PMR735A_ADC7_GPIO2_100K_PU (PMR735A_SID << 8 | 0x4b) +-#define PMR735A_ADC7_GPIO3_100K_PU (PMR735A_SID << 8 | 0x4c) +- +-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h b/scripts/dtc/include-prefixes/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h +deleted file mode 100644 +index 8da0e7dab315..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h ++++ /dev/null +@@ -1,28 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2020 The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H +-#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H +- +-#ifndef PMR735B_SID +-#define PMR735B_SID 5 +-#endif +- +-/* ADC channels for PMR735B_ADC for PMIC7 */ +-#define PMR735B_ADC7_REF_GND (PMR735B_SID << 8 | 0x0) +-#define PMR735B_ADC7_1P25VREF (PMR735B_SID << 8 | 0x01) +-#define PMR735B_ADC7_VREF_VADC (PMR735B_SID << 8 | 0x02) +-#define PMR735B_ADC7_DIE_TEMP (PMR735B_SID << 8 | 0x03) +- +-#define PMR735B_ADC7_GPIO1 (PMR735B_SID << 8 | 0x0a) +-#define PMR735B_ADC7_GPIO2 (PMR735B_SID << 8 | 0x0b) +-#define PMR735B_ADC7_GPIO3 (PMR735B_SID << 8 | 0x0c) +- +-/* 100k pull-up2 */ +-#define PMR735B_ADC7_GPIO1_100K_PU (PMR735B_SID << 8 | 0x4a) +-#define PMR735B_ADC7_GPIO2_100K_PU (PMR735B_SID << 8 | 0x4b) +-#define PMR735B_ADC7_GPIO3_100K_PU (PMR735B_SID << 8 | 0x4c) +- +-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/iio/qcom,spmi-vadc.h b/scripts/dtc/include-prefixes/dt-bindings/iio/qcom,spmi-vadc.h +deleted file mode 100644 +index 08adfe25964c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/iio/qcom,spmi-vadc.h ++++ /dev/null +@@ -1,300 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H +-#define _DT_BINDINGS_QCOM_SPMI_VADC_H +- +-/* Voltage ADC channels */ +-#define VADC_USBIN 0x00 +-#define VADC_DCIN 0x01 +-#define VADC_VCHG_SNS 0x02 +-#define VADC_SPARE1_03 0x03 +-#define VADC_USB_ID_MV 0x04 +-#define VADC_VCOIN 0x05 +-#define VADC_VBAT_SNS 0x06 +-#define VADC_VSYS 0x07 +-#define VADC_DIE_TEMP 0x08 +-#define VADC_REF_625MV 0x09 +-#define VADC_REF_1250MV 0x0a +-#define VADC_CHG_TEMP 0x0b +-#define VADC_SPARE1 0x0c +-#define VADC_SPARE2 0x0d +-#define VADC_GND_REF 0x0e +-#define VADC_VDD_VADC 0x0f +- +-#define VADC_P_MUX1_1_1 0x10 +-#define VADC_P_MUX2_1_1 0x11 +-#define VADC_P_MUX3_1_1 0x12 +-#define VADC_P_MUX4_1_1 0x13 +-#define VADC_P_MUX5_1_1 0x14 +-#define VADC_P_MUX6_1_1 0x15 +-#define VADC_P_MUX7_1_1 0x16 +-#define VADC_P_MUX8_1_1 0x17 +-#define VADC_P_MUX9_1_1 0x18 +-#define VADC_P_MUX10_1_1 0x19 +-#define VADC_P_MUX11_1_1 0x1a +-#define VADC_P_MUX12_1_1 0x1b +-#define VADC_P_MUX13_1_1 0x1c +-#define VADC_P_MUX14_1_1 0x1d +-#define VADC_P_MUX15_1_1 0x1e +-#define VADC_P_MUX16_1_1 0x1f +- +-#define VADC_P_MUX1_1_3 0x20 +-#define VADC_P_MUX2_1_3 0x21 +-#define VADC_P_MUX3_1_3 0x22 +-#define VADC_P_MUX4_1_3 0x23 +-#define VADC_P_MUX5_1_3 0x24 +-#define VADC_P_MUX6_1_3 0x25 +-#define VADC_P_MUX7_1_3 0x26 +-#define VADC_P_MUX8_1_3 0x27 +-#define VADC_P_MUX9_1_3 0x28 +-#define VADC_P_MUX10_1_3 0x29 +-#define VADC_P_MUX11_1_3 0x2a +-#define VADC_P_MUX12_1_3 0x2b +-#define VADC_P_MUX13_1_3 0x2c +-#define VADC_P_MUX14_1_3 0x2d +-#define VADC_P_MUX15_1_3 0x2e +-#define VADC_P_MUX16_1_3 0x2f +- +-#define VADC_LR_MUX1_BAT_THERM 0x30 +-#define VADC_LR_MUX2_BAT_ID 0x31 +-#define VADC_LR_MUX3_XO_THERM 0x32 +-#define VADC_LR_MUX4_AMUX_THM1 0x33 +-#define VADC_LR_MUX5_AMUX_THM2 0x34 +-#define VADC_LR_MUX6_AMUX_THM3 0x35 +-#define VADC_LR_MUX7_HW_ID 0x36 +-#define VADC_LR_MUX8_AMUX_THM4 0x37 +-#define VADC_LR_MUX9_AMUX_THM5 0x38 +-#define VADC_LR_MUX10_USB_ID 0x39 +-#define VADC_AMUX_PU1 0x3a +-#define VADC_AMUX_PU2 0x3b +-#define VADC_LR_MUX3_BUF_XO_THERM 0x3c +- +-#define VADC_LR_MUX1_PU1_BAT_THERM 0x70 +-#define VADC_LR_MUX2_PU1_BAT_ID 0x71 +-#define VADC_LR_MUX3_PU1_XO_THERM 0x72 +-#define VADC_LR_MUX4_PU1_AMUX_THM1 0x73 +-#define VADC_LR_MUX5_PU1_AMUX_THM2 0x74 +-#define VADC_LR_MUX6_PU1_AMUX_THM3 0x75 +-#define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76 +-#define VADC_LR_MUX8_PU1_AMUX_THM4 0x77 +-#define VADC_LR_MUX9_PU1_AMUX_THM5 0x78 +-#define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79 +-#define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c +- +-#define VADC_LR_MUX1_PU2_BAT_THERM 0xb0 +-#define VADC_LR_MUX2_PU2_BAT_ID 0xb1 +-#define VADC_LR_MUX3_PU2_XO_THERM 0xb2 +-#define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3 +-#define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4 +-#define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5 +-#define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6 +-#define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7 +-#define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8 +-#define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9 +-#define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc +- +-#define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0 +-#define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1 +-#define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2 +-#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3 +-#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4 +-#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5 +-#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6 +-#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7 +-#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8 +-#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9 +-#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc +- +-/* ADC channels for SPMI PMIC5 */ +- +-#define ADC5_REF_GND 0x00 +-#define ADC5_1P25VREF 0x01 +-#define ADC5_VREF_VADC 0x02 +-#define ADC5_VREF_VADC5_DIV_3 0x82 +-#define ADC5_VPH_PWR 0x83 +-#define ADC5_VBAT_SNS 0x84 +-#define ADC5_VCOIN 0x85 +-#define ADC5_DIE_TEMP 0x06 +-#define ADC5_USB_IN_I 0x07 +-#define ADC5_USB_IN_V_16 0x08 +-#define ADC5_CHG_TEMP 0x09 +-#define ADC5_BAT_THERM 0x0a +-#define ADC5_BAT_ID 0x0b +-#define ADC5_XO_THERM 0x0c +-#define ADC5_AMUX_THM1 0x0d +-#define ADC5_AMUX_THM2 0x0e +-#define ADC5_AMUX_THM3 0x0f +-#define ADC5_AMUX_THM4 0x10 +-#define ADC5_AMUX_THM5 0x11 +-#define ADC5_GPIO1 0x12 +-#define ADC5_GPIO2 0x13 +-#define ADC5_GPIO3 0x14 +-#define ADC5_GPIO4 0x15 +-#define ADC5_GPIO5 0x16 +-#define ADC5_GPIO6 0x17 +-#define ADC5_GPIO7 0x18 +-#define ADC5_SBUx 0x99 +-#define ADC5_MID_CHG_DIV6 0x1e +-#define ADC5_OFF 0xff +- +-/* 30k pull-up1 */ +-#define ADC5_BAT_THERM_30K_PU 0x2a +-#define ADC5_BAT_ID_30K_PU 0x2b +-#define ADC5_XO_THERM_30K_PU 0x2c +-#define ADC5_AMUX_THM1_30K_PU 0x2d +-#define ADC5_AMUX_THM2_30K_PU 0x2e +-#define ADC5_AMUX_THM3_30K_PU 0x2f +-#define ADC5_AMUX_THM4_30K_PU 0x30 +-#define ADC5_AMUX_THM5_30K_PU 0x31 +-#define ADC5_GPIO1_30K_PU 0x32 +-#define ADC5_GPIO2_30K_PU 0x33 +-#define ADC5_GPIO3_30K_PU 0x34 +-#define ADC5_GPIO4_30K_PU 0x35 +-#define ADC5_GPIO5_30K_PU 0x36 +-#define ADC5_GPIO6_30K_PU 0x37 +-#define ADC5_GPIO7_30K_PU 0x38 +-#define ADC5_SBUx_30K_PU 0x39 +- +-/* 100k pull-up2 */ +-#define ADC5_BAT_THERM_100K_PU 0x4a +-#define ADC5_BAT_ID_100K_PU 0x4b +-#define ADC5_XO_THERM_100K_PU 0x4c +-#define ADC5_AMUX_THM1_100K_PU 0x4d +-#define ADC5_AMUX_THM2_100K_PU 0x4e +-#define ADC5_AMUX_THM3_100K_PU 0x4f +-#define ADC5_AMUX_THM4_100K_PU 0x50 +-#define ADC5_AMUX_THM5_100K_PU 0x51 +-#define ADC5_GPIO1_100K_PU 0x52 +-#define ADC5_GPIO2_100K_PU 0x53 +-#define ADC5_GPIO3_100K_PU 0x54 +-#define ADC5_GPIO4_100K_PU 0x55 +-#define ADC5_GPIO5_100K_PU 0x56 +-#define ADC5_GPIO6_100K_PU 0x57 +-#define ADC5_GPIO7_100K_PU 0x58 +-#define ADC5_SBUx_100K_PU 0x59 +- +-/* 400k pull-up3 */ +-#define ADC5_BAT_THERM_400K_PU 0x6a +-#define ADC5_BAT_ID_400K_PU 0x6b +-#define ADC5_XO_THERM_400K_PU 0x6c +-#define ADC5_AMUX_THM1_400K_PU 0x6d +-#define ADC5_AMUX_THM2_400K_PU 0x6e +-#define ADC5_AMUX_THM3_400K_PU 0x6f +-#define ADC5_AMUX_THM4_400K_PU 0x70 +-#define ADC5_AMUX_THM5_400K_PU 0x71 +-#define ADC5_GPIO1_400K_PU 0x72 +-#define ADC5_GPIO2_400K_PU 0x73 +-#define ADC5_GPIO3_400K_PU 0x74 +-#define ADC5_GPIO4_400K_PU 0x75 +-#define ADC5_GPIO5_400K_PU 0x76 +-#define ADC5_GPIO6_400K_PU 0x77 +-#define ADC5_GPIO7_400K_PU 0x78 +-#define ADC5_SBUx_400K_PU 0x79 +- +-/* 1/3 Divider */ +-#define ADC5_GPIO1_DIV3 0x92 +-#define ADC5_GPIO2_DIV3 0x93 +-#define ADC5_GPIO3_DIV3 0x94 +-#define ADC5_GPIO4_DIV3 0x95 +-#define ADC5_GPIO5_DIV3 0x96 +-#define ADC5_GPIO6_DIV3 0x97 +-#define ADC5_GPIO7_DIV3 0x98 +-#define ADC5_SBUx_DIV3 0x99 +- +-/* Current and combined current/voltage channels */ +-#define ADC5_INT_EXT_ISENSE 0xa1 +-#define ADC5_PARALLEL_ISENSE 0xa5 +-#define ADC5_CUR_REPLICA_VDS 0xa7 +-#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9 +-#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab +-#define ADC5_EXT_SENS_OFFSET 0xad +- +-#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0 +-#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1 +-#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2 +-#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3 +-#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4 +-#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5 +- +-#define ADC5_MAX_CHANNEL 0xc0 +- +-/* ADC channels for ADC for PMIC7 */ +- +-#define ADC7_REF_GND 0x00 +-#define ADC7_1P25VREF 0x01 +-#define ADC7_VREF_VADC 0x02 +-#define ADC7_DIE_TEMP 0x03 +- +-#define ADC7_AMUX_THM1 0x04 +-#define ADC7_AMUX_THM2 0x05 +-#define ADC7_AMUX_THM3 0x06 +-#define ADC7_AMUX_THM4 0x07 +-#define ADC7_AMUX_THM5 0x08 +-#define ADC7_AMUX_THM6 0x09 +-#define ADC7_GPIO1 0x0a +-#define ADC7_GPIO2 0x0b +-#define ADC7_GPIO3 0x0c +-#define ADC7_GPIO4 0x0d +- +-#define ADC7_CHG_TEMP 0x10 +-#define ADC7_USB_IN_V_16 0x11 +-#define ADC7_VDC_16 0x12 +-#define ADC7_CC1_ID 0x13 +-#define ADC7_VREF_BAT_THERM 0x15 +-#define ADC7_IIN_FB 0x17 +- +-/* 30k pull-up1 */ +-#define ADC7_AMUX_THM1_30K_PU 0x24 +-#define ADC7_AMUX_THM2_30K_PU 0x25 +-#define ADC7_AMUX_THM3_30K_PU 0x26 +-#define ADC7_AMUX_THM4_30K_PU 0x27 +-#define ADC7_AMUX_THM5_30K_PU 0x28 +-#define ADC7_AMUX_THM6_30K_PU 0x29 +-#define ADC7_GPIO1_30K_PU 0x2a +-#define ADC7_GPIO2_30K_PU 0x2b +-#define ADC7_GPIO3_30K_PU 0x2c +-#define ADC7_GPIO4_30K_PU 0x2d +-#define ADC7_CC1_ID_30K_PU 0x33 +- +-/* 100k pull-up2 */ +-#define ADC7_AMUX_THM1_100K_PU 0x44 +-#define ADC7_AMUX_THM2_100K_PU 0x45 +-#define ADC7_AMUX_THM3_100K_PU 0x46 +-#define ADC7_AMUX_THM4_100K_PU 0x47 +-#define ADC7_AMUX_THM5_100K_PU 0x48 +-#define ADC7_AMUX_THM6_100K_PU 0x49 +-#define ADC7_GPIO1_100K_PU 0x4a +-#define ADC7_GPIO2_100K_PU 0x4b +-#define ADC7_GPIO3_100K_PU 0x4c +-#define ADC7_GPIO4_100K_PU 0x4d +-#define ADC7_CC1_ID_100K_PU 0x53 +- +-/* 400k pull-up3 */ +-#define ADC7_AMUX_THM1_400K_PU 0x64 +-#define ADC7_AMUX_THM2_400K_PU 0x65 +-#define ADC7_AMUX_THM3_400K_PU 0x66 +-#define ADC7_AMUX_THM4_400K_PU 0x67 +-#define ADC7_AMUX_THM5_400K_PU 0x68 +-#define ADC7_AMUX_THM6_400K_PU 0x69 +-#define ADC7_GPIO1_400K_PU 0x6a +-#define ADC7_GPIO2_400K_PU 0x6b +-#define ADC7_GPIO3_400K_PU 0x6c +-#define ADC7_GPIO4_400K_PU 0x6d +-#define ADC7_CC1_ID_400K_PU 0x73 +- +-/* 1/3 Divider */ +-#define ADC7_GPIO1_DIV3 0x8a +-#define ADC7_GPIO2_DIV3 0x8b +-#define ADC7_GPIO3_DIV3 0x8c +-#define ADC7_GPIO4_DIV3 0x8d +- +-#define ADC7_VPH_PWR 0x8e +-#define ADC7_VBAT_SNS 0x8f +- +-#define ADC7_SBUx 0x94 +-#define ADC7_VBAT_2S_MID 0x96 +- +-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/iio/temperature/thermocouple.h b/scripts/dtc/include-prefixes/dt-bindings/iio/temperature/thermocouple.h +deleted file mode 100644 +index ce037f5238ac..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/iio/temperature/thermocouple.h ++++ /dev/null +@@ -1,16 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +- +-#ifndef _DT_BINDINGS_TEMPERATURE_THERMOCOUPLE_H +-#define _DT_BINDINGS_TEMPERATURE_THERMOCOUPLE_H +- +- +-#define THERMOCOUPLE_TYPE_B 0x00 +-#define THERMOCOUPLE_TYPE_E 0x01 +-#define THERMOCOUPLE_TYPE_J 0x02 +-#define THERMOCOUPLE_TYPE_K 0x03 +-#define THERMOCOUPLE_TYPE_N 0x04 +-#define THERMOCOUPLE_TYPE_R 0x05 +-#define THERMOCOUPLE_TYPE_S 0x06 +-#define THERMOCOUPLE_TYPE_T 0x07 +- +-#endif /* _DT_BINDINGS_TEMPERATURE_THERMOCOUPLE_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/input/atmel-maxtouch.h b/scripts/dtc/include-prefixes/dt-bindings/input/atmel-maxtouch.h +deleted file mode 100644 +index 7345ab32224d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/input/atmel-maxtouch.h ++++ /dev/null +@@ -1,10 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef _DT_BINDINGS_ATMEL_MAXTOUCH_H +-#define _DT_BINDINGS_ATMEL_MAXTOUCH_H +- +-#define ATMEL_MXT_WAKEUP_NONE 0 +-#define ATMEL_MXT_WAKEUP_I2C_SCL 1 +-#define ATMEL_MXT_WAKEUP_GPIO 2 +- +-#endif /* _DT_BINDINGS_ATMEL_MAXTOUCH_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/input/cros-ec-keyboard.h b/scripts/dtc/include-prefixes/dt-bindings/input/cros-ec-keyboard.h +deleted file mode 100644 +index f0ae03634a96..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/input/cros-ec-keyboard.h ++++ /dev/null +@@ -1,103 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides the constants of the standard Chrome OS key matrix +- * for cros-ec keyboard-controller bindings. +- * +- * Copyright (c) 2021 Google, Inc +- */ +- +-#ifndef _CROS_EC_KEYBOARD_H +-#define _CROS_EC_KEYBOARD_H +- +-#define CROS_STD_TOP_ROW_KEYMAP \ +- MATRIX_KEY(0x00, 0x02, KEY_F1) \ +- MATRIX_KEY(0x03, 0x02, KEY_F2) \ +- MATRIX_KEY(0x02, 0x02, KEY_F3) \ +- MATRIX_KEY(0x01, 0x02, KEY_F4) \ +- MATRIX_KEY(0x03, 0x04, KEY_F5) \ +- MATRIX_KEY(0x02, 0x04, KEY_F6) \ +- MATRIX_KEY(0x01, 0x04, KEY_F7) \ +- MATRIX_KEY(0x02, 0x09, KEY_F8) \ +- MATRIX_KEY(0x01, 0x09, KEY_F9) \ +- MATRIX_KEY(0x00, 0x04, KEY_F10) +- +-#define CROS_STD_MAIN_KEYMAP \ +- MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) \ +- MATRIX_KEY(0x00, 0x03, KEY_B) \ +- MATRIX_KEY(0x00, 0x05, KEY_RO) \ +- MATRIX_KEY(0x00, 0x06, KEY_N) \ +- MATRIX_KEY(0x00, 0x08, KEY_EQUAL) \ +- MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) \ +- MATRIX_KEY(0x01, 0x01, KEY_ESC) \ +- MATRIX_KEY(0x01, 0x03, KEY_G) \ +- MATRIX_KEY(0x01, 0x06, KEY_H) \ +- MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) \ +- MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) \ +- MATRIX_KEY(0x01, 0x0c, KEY_HENKAN) \ +- \ +- MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) \ +- MATRIX_KEY(0x02, 0x01, KEY_TAB) \ +- MATRIX_KEY(0x02, 0x03, KEY_T) \ +- MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) \ +- MATRIX_KEY(0x02, 0x06, KEY_Y) \ +- MATRIX_KEY(0x02, 0x07, KEY_102ND) \ +- MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) \ +- MATRIX_KEY(0x02, 0x0a, KEY_YEN) \ +- \ +- MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA) \ +- MATRIX_KEY(0x03, 0x01, KEY_GRAVE) \ +- MATRIX_KEY(0x03, 0x03, KEY_5) \ +- MATRIX_KEY(0x03, 0x06, KEY_6) \ +- MATRIX_KEY(0x03, 0x08, KEY_MINUS) \ +- MATRIX_KEY(0x03, 0x09, KEY_SLEEP) \ +- MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) \ +- MATRIX_KEY(0x03, 0x0c, KEY_MUHENKAN) \ +- \ +- MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) \ +- MATRIX_KEY(0x04, 0x01, KEY_A) \ +- MATRIX_KEY(0x04, 0x02, KEY_D) \ +- MATRIX_KEY(0x04, 0x03, KEY_F) \ +- MATRIX_KEY(0x04, 0x04, KEY_S) \ +- MATRIX_KEY(0x04, 0x05, KEY_K) \ +- MATRIX_KEY(0x04, 0x06, KEY_J) \ +- MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) \ +- MATRIX_KEY(0x04, 0x09, KEY_L) \ +- MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH) \ +- MATRIX_KEY(0x04, 0x0b, KEY_ENTER) \ +- \ +- MATRIX_KEY(0x05, 0x01, KEY_Z) \ +- MATRIX_KEY(0x05, 0x02, KEY_C) \ +- MATRIX_KEY(0x05, 0x03, KEY_V) \ +- MATRIX_KEY(0x05, 0x04, KEY_X) \ +- MATRIX_KEY(0x05, 0x05, KEY_COMMA) \ +- MATRIX_KEY(0x05, 0x06, KEY_M) \ +- MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) \ +- MATRIX_KEY(0x05, 0x08, KEY_SLASH) \ +- MATRIX_KEY(0x05, 0x09, KEY_DOT) \ +- MATRIX_KEY(0x05, 0x0b, KEY_SPACE) \ +- \ +- MATRIX_KEY(0x06, 0x01, KEY_1) \ +- MATRIX_KEY(0x06, 0x02, KEY_3) \ +- MATRIX_KEY(0x06, 0x03, KEY_4) \ +- MATRIX_KEY(0x06, 0x04, KEY_2) \ +- MATRIX_KEY(0x06, 0x05, KEY_8) \ +- MATRIX_KEY(0x06, 0x06, KEY_7) \ +- MATRIX_KEY(0x06, 0x08, KEY_0) \ +- MATRIX_KEY(0x06, 0x09, KEY_9) \ +- MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT) \ +- MATRIX_KEY(0x06, 0x0b, KEY_DOWN) \ +- MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) \ +- \ +- MATRIX_KEY(0x07, 0x01, KEY_Q) \ +- MATRIX_KEY(0x07, 0x02, KEY_E) \ +- MATRIX_KEY(0x07, 0x03, KEY_R) \ +- MATRIX_KEY(0x07, 0x04, KEY_W) \ +- MATRIX_KEY(0x07, 0x05, KEY_I) \ +- MATRIX_KEY(0x07, 0x06, KEY_U) \ +- MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) \ +- MATRIX_KEY(0x07, 0x08, KEY_P) \ +- MATRIX_KEY(0x07, 0x09, KEY_O) \ +- MATRIX_KEY(0x07, 0x0b, KEY_UP) \ +- MATRIX_KEY(0x07, 0x0c, KEY_LEFT) +- +-#endif /* _CROS_EC_KEYBOARD_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/input/gpio-keys.h b/scripts/dtc/include-prefixes/dt-bindings/input/gpio-keys.h +deleted file mode 100644 +index 8962df79e753..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/input/gpio-keys.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for gpio keys bindings. +- */ +- +-#ifndef _DT_BINDINGS_GPIO_KEYS_H +-#define _DT_BINDINGS_GPIO_KEYS_H +- +-#define EV_ACT_ANY 0x00 /* asserted or deasserted */ +-#define EV_ACT_ASSERTED 0x01 /* asserted */ +-#define EV_ACT_DEASSERTED 0x02 /* deasserted */ +- +-#endif /* _DT_BINDINGS_GPIO_KEYS_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/input/input.h b/scripts/dtc/include-prefixes/dt-bindings/input/input.h +deleted file mode 100644 +index bcf0ae100f21..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/input/input.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for most input bindings. +- * +- * Most input bindings include key code, matrix key code format. +- * In most cases, key code and matrix key code format uses +- * the standard values/macro defined in this header. +- */ +- +-#ifndef _DT_BINDINGS_INPUT_INPUT_H +-#define _DT_BINDINGS_INPUT_INPUT_H +- +-#include "linux-event-codes.h" +- +-#define MATRIX_KEY(row, col, code) \ +- ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) +- +-#endif /* _DT_BINDINGS_INPUT_INPUT_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/input/linux-event-codes.h b/scripts/dtc/include-prefixes/dt-bindings/input/linux-event-codes.h +deleted file mode 100644 +index 7989d9483ea7..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/input/linux-event-codes.h ++++ /dev/null +@@ -1,952 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +-/* +- * Input event codes +- * +- * *** IMPORTANT *** +- * This file is not only included from C-code but also from devicetree source +- * files. As such this file MUST only contain comments and defines. +- * +- * Copyright (c) 1999-2002 Vojtech Pavlik +- * Copyright (c) 2015 Hans de Goede +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published by +- * the Free Software Foundation. +- */ +-#ifndef _UAPI_INPUT_EVENT_CODES_H +-#define _UAPI_INPUT_EVENT_CODES_H +- +-/* +- * Device properties and quirks +- */ +- +-#define INPUT_PROP_POINTER 0x00 /* needs a pointer */ +-#define INPUT_PROP_DIRECT 0x01 /* direct input devices */ +-#define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ +-#define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ +-#define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ +-#define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ +-#define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ +- +-#define INPUT_PROP_MAX 0x1f +-#define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) +- +-/* +- * Event types +- */ +- +-#define EV_SYN 0x00 +-#define EV_KEY 0x01 +-#define EV_REL 0x02 +-#define EV_ABS 0x03 +-#define EV_MSC 0x04 +-#define EV_SW 0x05 +-#define EV_LED 0x11 +-#define EV_SND 0x12 +-#define EV_REP 0x14 +-#define EV_FF 0x15 +-#define EV_PWR 0x16 +-#define EV_FF_STATUS 0x17 +-#define EV_MAX 0x1f +-#define EV_CNT (EV_MAX+1) +- +-/* +- * Synchronization events. +- */ +- +-#define SYN_REPORT 0 +-#define SYN_CONFIG 1 +-#define SYN_MT_REPORT 2 +-#define SYN_DROPPED 3 +-#define SYN_MAX 0xf +-#define SYN_CNT (SYN_MAX+1) +- +-/* +- * Keys and buttons +- * +- * Most of the keys/buttons are modeled after USB HUT 1.12 +- * (see http://www.usb.org/developers/hidpage). +- * Abbreviations in the comments: +- * AC - Application Control +- * AL - Application Launch Button +- * SC - System Control +- */ +- +-#define KEY_RESERVED 0 +-#define KEY_ESC 1 +-#define KEY_1 2 +-#define KEY_2 3 +-#define KEY_3 4 +-#define KEY_4 5 +-#define KEY_5 6 +-#define KEY_6 7 +-#define KEY_7 8 +-#define KEY_8 9 +-#define KEY_9 10 +-#define KEY_0 11 +-#define KEY_MINUS 12 +-#define KEY_EQUAL 13 +-#define KEY_BACKSPACE 14 +-#define KEY_TAB 15 +-#define KEY_Q 16 +-#define KEY_W 17 +-#define KEY_E 18 +-#define KEY_R 19 +-#define KEY_T 20 +-#define KEY_Y 21 +-#define KEY_U 22 +-#define KEY_I 23 +-#define KEY_O 24 +-#define KEY_P 25 +-#define KEY_LEFTBRACE 26 +-#define KEY_RIGHTBRACE 27 +-#define KEY_ENTER 28 +-#define KEY_LEFTCTRL 29 +-#define KEY_A 30 +-#define KEY_S 31 +-#define KEY_D 32 +-#define KEY_F 33 +-#define KEY_G 34 +-#define KEY_H 35 +-#define KEY_J 36 +-#define KEY_K 37 +-#define KEY_L 38 +-#define KEY_SEMICOLON 39 +-#define KEY_APOSTROPHE 40 +-#define KEY_GRAVE 41 +-#define KEY_LEFTSHIFT 42 +-#define KEY_BACKSLASH 43 +-#define KEY_Z 44 +-#define KEY_X 45 +-#define KEY_C 46 +-#define KEY_V 47 +-#define KEY_B 48 +-#define KEY_N 49 +-#define KEY_M 50 +-#define KEY_COMMA 51 +-#define KEY_DOT 52 +-#define KEY_SLASH 53 +-#define KEY_RIGHTSHIFT 54 +-#define KEY_KPASTERISK 55 +-#define KEY_LEFTALT 56 +-#define KEY_SPACE 57 +-#define KEY_CAPSLOCK 58 +-#define KEY_F1 59 +-#define KEY_F2 60 +-#define KEY_F3 61 +-#define KEY_F4 62 +-#define KEY_F5 63 +-#define KEY_F6 64 +-#define KEY_F7 65 +-#define KEY_F8 66 +-#define KEY_F9 67 +-#define KEY_F10 68 +-#define KEY_NUMLOCK 69 +-#define KEY_SCROLLLOCK 70 +-#define KEY_KP7 71 +-#define KEY_KP8 72 +-#define KEY_KP9 73 +-#define KEY_KPMINUS 74 +-#define KEY_KP4 75 +-#define KEY_KP5 76 +-#define KEY_KP6 77 +-#define KEY_KPPLUS 78 +-#define KEY_KP1 79 +-#define KEY_KP2 80 +-#define KEY_KP3 81 +-#define KEY_KP0 82 +-#define KEY_KPDOT 83 +- +-#define KEY_ZENKAKUHANKAKU 85 +-#define KEY_102ND 86 +-#define KEY_F11 87 +-#define KEY_F12 88 +-#define KEY_RO 89 +-#define KEY_KATAKANA 90 +-#define KEY_HIRAGANA 91 +-#define KEY_HENKAN 92 +-#define KEY_KATAKANAHIRAGANA 93 +-#define KEY_MUHENKAN 94 +-#define KEY_KPJPCOMMA 95 +-#define KEY_KPENTER 96 +-#define KEY_RIGHTCTRL 97 +-#define KEY_KPSLASH 98 +-#define KEY_SYSRQ 99 +-#define KEY_RIGHTALT 100 +-#define KEY_LINEFEED 101 +-#define KEY_HOME 102 +-#define KEY_UP 103 +-#define KEY_PAGEUP 104 +-#define KEY_LEFT 105 +-#define KEY_RIGHT 106 +-#define KEY_END 107 +-#define KEY_DOWN 108 +-#define KEY_PAGEDOWN 109 +-#define KEY_INSERT 110 +-#define KEY_DELETE 111 +-#define KEY_MACRO 112 +-#define KEY_MUTE 113 +-#define KEY_VOLUMEDOWN 114 +-#define KEY_VOLUMEUP 115 +-#define KEY_POWER 116 /* SC System Power Down */ +-#define KEY_KPEQUAL 117 +-#define KEY_KPPLUSMINUS 118 +-#define KEY_PAUSE 119 +-#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ +- +-#define KEY_KPCOMMA 121 +-#define KEY_HANGEUL 122 +-#define KEY_HANGUEL KEY_HANGEUL +-#define KEY_HANJA 123 +-#define KEY_YEN 124 +-#define KEY_LEFTMETA 125 +-#define KEY_RIGHTMETA 126 +-#define KEY_COMPOSE 127 +- +-#define KEY_STOP 128 /* AC Stop */ +-#define KEY_AGAIN 129 +-#define KEY_PROPS 130 /* AC Properties */ +-#define KEY_UNDO 131 /* AC Undo */ +-#define KEY_FRONT 132 +-#define KEY_COPY 133 /* AC Copy */ +-#define KEY_OPEN 134 /* AC Open */ +-#define KEY_PASTE 135 /* AC Paste */ +-#define KEY_FIND 136 /* AC Search */ +-#define KEY_CUT 137 /* AC Cut */ +-#define KEY_HELP 138 /* AL Integrated Help Center */ +-#define KEY_MENU 139 /* Menu (show menu) */ +-#define KEY_CALC 140 /* AL Calculator */ +-#define KEY_SETUP 141 +-#define KEY_SLEEP 142 /* SC System Sleep */ +-#define KEY_WAKEUP 143 /* System Wake Up */ +-#define KEY_FILE 144 /* AL Local Machine Browser */ +-#define KEY_SENDFILE 145 +-#define KEY_DELETEFILE 146 +-#define KEY_XFER 147 +-#define KEY_PROG1 148 +-#define KEY_PROG2 149 +-#define KEY_WWW 150 /* AL Internet Browser */ +-#define KEY_MSDOS 151 +-#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ +-#define KEY_SCREENLOCK KEY_COFFEE +-#define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */ +-#define KEY_DIRECTION KEY_ROTATE_DISPLAY +-#define KEY_CYCLEWINDOWS 154 +-#define KEY_MAIL 155 +-#define KEY_BOOKMARKS 156 /* AC Bookmarks */ +-#define KEY_COMPUTER 157 +-#define KEY_BACK 158 /* AC Back */ +-#define KEY_FORWARD 159 /* AC Forward */ +-#define KEY_CLOSECD 160 +-#define KEY_EJECTCD 161 +-#define KEY_EJECTCLOSECD 162 +-#define KEY_NEXTSONG 163 +-#define KEY_PLAYPAUSE 164 +-#define KEY_PREVIOUSSONG 165 +-#define KEY_STOPCD 166 +-#define KEY_RECORD 167 +-#define KEY_REWIND 168 +-#define KEY_PHONE 169 /* Media Select Telephone */ +-#define KEY_ISO 170 +-#define KEY_CONFIG 171 /* AL Consumer Control Configuration */ +-#define KEY_HOMEPAGE 172 /* AC Home */ +-#define KEY_REFRESH 173 /* AC Refresh */ +-#define KEY_EXIT 174 /* AC Exit */ +-#define KEY_MOVE 175 +-#define KEY_EDIT 176 +-#define KEY_SCROLLUP 177 +-#define KEY_SCROLLDOWN 178 +-#define KEY_KPLEFTPAREN 179 +-#define KEY_KPRIGHTPAREN 180 +-#define KEY_NEW 181 /* AC New */ +-#define KEY_REDO 182 /* AC Redo/Repeat */ +- +-#define KEY_F13 183 +-#define KEY_F14 184 +-#define KEY_F15 185 +-#define KEY_F16 186 +-#define KEY_F17 187 +-#define KEY_F18 188 +-#define KEY_F19 189 +-#define KEY_F20 190 +-#define KEY_F21 191 +-#define KEY_F22 192 +-#define KEY_F23 193 +-#define KEY_F24 194 +- +-#define KEY_PLAYCD 200 +-#define KEY_PAUSECD 201 +-#define KEY_PROG3 202 +-#define KEY_PROG4 203 +-#define KEY_ALL_APPLICATIONS 204 /* AC Desktop Show All Applications */ +-#define KEY_DASHBOARD KEY_ALL_APPLICATIONS +-#define KEY_SUSPEND 205 +-#define KEY_CLOSE 206 /* AC Close */ +-#define KEY_PLAY 207 +-#define KEY_FASTFORWARD 208 +-#define KEY_BASSBOOST 209 +-#define KEY_PRINT 210 /* AC Print */ +-#define KEY_HP 211 +-#define KEY_CAMERA 212 +-#define KEY_SOUND 213 +-#define KEY_QUESTION 214 +-#define KEY_EMAIL 215 +-#define KEY_CHAT 216 +-#define KEY_SEARCH 217 +-#define KEY_CONNECT 218 +-#define KEY_FINANCE 219 /* AL Checkbook/Finance */ +-#define KEY_SPORT 220 +-#define KEY_SHOP 221 +-#define KEY_ALTERASE 222 +-#define KEY_CANCEL 223 /* AC Cancel */ +-#define KEY_BRIGHTNESSDOWN 224 +-#define KEY_BRIGHTNESSUP 225 +-#define KEY_MEDIA 226 +- +-#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video +- outputs (Monitor/LCD/TV-out/etc) */ +-#define KEY_KBDILLUMTOGGLE 228 +-#define KEY_KBDILLUMDOWN 229 +-#define KEY_KBDILLUMUP 230 +- +-#define KEY_SEND 231 /* AC Send */ +-#define KEY_REPLY 232 /* AC Reply */ +-#define KEY_FORWARDMAIL 233 /* AC Forward Msg */ +-#define KEY_SAVE 234 /* AC Save */ +-#define KEY_DOCUMENTS 235 +- +-#define KEY_BATTERY 236 +- +-#define KEY_BLUETOOTH 237 +-#define KEY_WLAN 238 +-#define KEY_UWB 239 +- +-#define KEY_UNKNOWN 240 +- +-#define KEY_VIDEO_NEXT 241 /* drive next video source */ +-#define KEY_VIDEO_PREV 242 /* drive previous video source */ +-#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ +-#define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual +- brightness control is off, +- rely on ambient */ +-#define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO +-#define KEY_DISPLAY_OFF 245 /* display device to off state */ +- +-#define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ +-#define KEY_WIMAX KEY_WWAN +-#define KEY_RFKILL 247 /* Key that controls all radios */ +- +-#define KEY_MICMUTE 248 /* Mute / unmute the microphone */ +- +-/* Code 255 is reserved for special needs of AT keyboard driver */ +- +-#define BTN_MISC 0x100 +-#define BTN_0 0x100 +-#define BTN_1 0x101 +-#define BTN_2 0x102 +-#define BTN_3 0x103 +-#define BTN_4 0x104 +-#define BTN_5 0x105 +-#define BTN_6 0x106 +-#define BTN_7 0x107 +-#define BTN_8 0x108 +-#define BTN_9 0x109 +- +-#define BTN_MOUSE 0x110 +-#define BTN_LEFT 0x110 +-#define BTN_RIGHT 0x111 +-#define BTN_MIDDLE 0x112 +-#define BTN_SIDE 0x113 +-#define BTN_EXTRA 0x114 +-#define BTN_FORWARD 0x115 +-#define BTN_BACK 0x116 +-#define BTN_TASK 0x117 +- +-#define BTN_JOYSTICK 0x120 +-#define BTN_TRIGGER 0x120 +-#define BTN_THUMB 0x121 +-#define BTN_THUMB2 0x122 +-#define BTN_TOP 0x123 +-#define BTN_TOP2 0x124 +-#define BTN_PINKIE 0x125 +-#define BTN_BASE 0x126 +-#define BTN_BASE2 0x127 +-#define BTN_BASE3 0x128 +-#define BTN_BASE4 0x129 +-#define BTN_BASE5 0x12a +-#define BTN_BASE6 0x12b +-#define BTN_DEAD 0x12f +- +-#define BTN_GAMEPAD 0x130 +-#define BTN_SOUTH 0x130 +-#define BTN_A BTN_SOUTH +-#define BTN_EAST 0x131 +-#define BTN_B BTN_EAST +-#define BTN_C 0x132 +-#define BTN_NORTH 0x133 +-#define BTN_X BTN_NORTH +-#define BTN_WEST 0x134 +-#define BTN_Y BTN_WEST +-#define BTN_Z 0x135 +-#define BTN_TL 0x136 +-#define BTN_TR 0x137 +-#define BTN_TL2 0x138 +-#define BTN_TR2 0x139 +-#define BTN_SELECT 0x13a +-#define BTN_START 0x13b +-#define BTN_MODE 0x13c +-#define BTN_THUMBL 0x13d +-#define BTN_THUMBR 0x13e +- +-#define BTN_DIGI 0x140 +-#define BTN_TOOL_PEN 0x140 +-#define BTN_TOOL_RUBBER 0x141 +-#define BTN_TOOL_BRUSH 0x142 +-#define BTN_TOOL_PENCIL 0x143 +-#define BTN_TOOL_AIRBRUSH 0x144 +-#define BTN_TOOL_FINGER 0x145 +-#define BTN_TOOL_MOUSE 0x146 +-#define BTN_TOOL_LENS 0x147 +-#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ +-#define BTN_STYLUS3 0x149 +-#define BTN_TOUCH 0x14a +-#define BTN_STYLUS 0x14b +-#define BTN_STYLUS2 0x14c +-#define BTN_TOOL_DOUBLETAP 0x14d +-#define BTN_TOOL_TRIPLETAP 0x14e +-#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ +- +-#define BTN_WHEEL 0x150 +-#define BTN_GEAR_DOWN 0x150 +-#define BTN_GEAR_UP 0x151 +- +-#define KEY_OK 0x160 +-#define KEY_SELECT 0x161 +-#define KEY_GOTO 0x162 +-#define KEY_CLEAR 0x163 +-#define KEY_POWER2 0x164 +-#define KEY_OPTION 0x165 +-#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ +-#define KEY_TIME 0x167 +-#define KEY_VENDOR 0x168 +-#define KEY_ARCHIVE 0x169 +-#define KEY_PROGRAM 0x16a /* Media Select Program Guide */ +-#define KEY_CHANNEL 0x16b +-#define KEY_FAVORITES 0x16c +-#define KEY_EPG 0x16d +-#define KEY_PVR 0x16e /* Media Select Home */ +-#define KEY_MHP 0x16f +-#define KEY_LANGUAGE 0x170 +-#define KEY_TITLE 0x171 +-#define KEY_SUBTITLE 0x172 +-#define KEY_ANGLE 0x173 +-#define KEY_FULL_SCREEN 0x174 /* AC View Toggle */ +-#define KEY_ZOOM KEY_FULL_SCREEN +-#define KEY_MODE 0x175 +-#define KEY_KEYBOARD 0x176 +-#define KEY_ASPECT_RATIO 0x177 /* HUTRR37: Aspect */ +-#define KEY_SCREEN KEY_ASPECT_RATIO +-#define KEY_PC 0x178 /* Media Select Computer */ +-#define KEY_TV 0x179 /* Media Select TV */ +-#define KEY_TV2 0x17a /* Media Select Cable */ +-#define KEY_VCR 0x17b /* Media Select VCR */ +-#define KEY_VCR2 0x17c /* VCR Plus */ +-#define KEY_SAT 0x17d /* Media Select Satellite */ +-#define KEY_SAT2 0x17e +-#define KEY_CD 0x17f /* Media Select CD */ +-#define KEY_TAPE 0x180 /* Media Select Tape */ +-#define KEY_RADIO 0x181 +-#define KEY_TUNER 0x182 /* Media Select Tuner */ +-#define KEY_PLAYER 0x183 +-#define KEY_TEXT 0x184 +-#define KEY_DVD 0x185 /* Media Select DVD */ +-#define KEY_AUX 0x186 +-#define KEY_MP3 0x187 +-#define KEY_AUDIO 0x188 /* AL Audio Browser */ +-#define KEY_VIDEO 0x189 /* AL Movie Browser */ +-#define KEY_DIRECTORY 0x18a +-#define KEY_LIST 0x18b +-#define KEY_MEMO 0x18c /* Media Select Messages */ +-#define KEY_CALENDAR 0x18d +-#define KEY_RED 0x18e +-#define KEY_GREEN 0x18f +-#define KEY_YELLOW 0x190 +-#define KEY_BLUE 0x191 +-#define KEY_CHANNELUP 0x192 /* Channel Increment */ +-#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ +-#define KEY_FIRST 0x194 +-#define KEY_LAST 0x195 /* Recall Last */ +-#define KEY_AB 0x196 +-#define KEY_NEXT 0x197 +-#define KEY_RESTART 0x198 +-#define KEY_SLOW 0x199 +-#define KEY_SHUFFLE 0x19a +-#define KEY_BREAK 0x19b +-#define KEY_PREVIOUS 0x19c +-#define KEY_DIGITS 0x19d +-#define KEY_TEEN 0x19e +-#define KEY_TWEN 0x19f +-#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ +-#define KEY_GAMES 0x1a1 /* Media Select Games */ +-#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ +-#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ +-#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ +-#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ +-#define KEY_EDITOR 0x1a6 /* AL Text Editor */ +-#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ +-#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ +-#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ +-#define KEY_DATABASE 0x1aa /* AL Database App */ +-#define KEY_NEWS 0x1ab /* AL Newsreader */ +-#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ +-#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ +-#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ +-#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ +-#define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE +-#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ +-#define KEY_LOGOFF 0x1b1 /* AL Logoff */ +- +-#define KEY_DOLLAR 0x1b2 +-#define KEY_EURO 0x1b3 +- +-#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ +-#define KEY_FRAMEFORWARD 0x1b5 +-#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ +-#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ +-#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ +-#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ +-#define KEY_IMAGES 0x1ba /* AL Image Browser */ +-#define KEY_NOTIFICATION_CENTER 0x1bc /* Show/hide the notification center */ +-#define KEY_PICKUP_PHONE 0x1bd /* Answer incoming call */ +-#define KEY_HANGUP_PHONE 0x1be /* Decline incoming call */ +- +-#define KEY_DEL_EOL 0x1c0 +-#define KEY_DEL_EOS 0x1c1 +-#define KEY_INS_LINE 0x1c2 +-#define KEY_DEL_LINE 0x1c3 +- +-#define KEY_FN 0x1d0 +-#define KEY_FN_ESC 0x1d1 +-#define KEY_FN_F1 0x1d2 +-#define KEY_FN_F2 0x1d3 +-#define KEY_FN_F3 0x1d4 +-#define KEY_FN_F4 0x1d5 +-#define KEY_FN_F5 0x1d6 +-#define KEY_FN_F6 0x1d7 +-#define KEY_FN_F7 0x1d8 +-#define KEY_FN_F8 0x1d9 +-#define KEY_FN_F9 0x1da +-#define KEY_FN_F10 0x1db +-#define KEY_FN_F11 0x1dc +-#define KEY_FN_F12 0x1dd +-#define KEY_FN_1 0x1de +-#define KEY_FN_2 0x1df +-#define KEY_FN_D 0x1e0 +-#define KEY_FN_E 0x1e1 +-#define KEY_FN_F 0x1e2 +-#define KEY_FN_S 0x1e3 +-#define KEY_FN_B 0x1e4 +-#define KEY_FN_RIGHT_SHIFT 0x1e5 +- +-#define KEY_BRL_DOT1 0x1f1 +-#define KEY_BRL_DOT2 0x1f2 +-#define KEY_BRL_DOT3 0x1f3 +-#define KEY_BRL_DOT4 0x1f4 +-#define KEY_BRL_DOT5 0x1f5 +-#define KEY_BRL_DOT6 0x1f6 +-#define KEY_BRL_DOT7 0x1f7 +-#define KEY_BRL_DOT8 0x1f8 +-#define KEY_BRL_DOT9 0x1f9 +-#define KEY_BRL_DOT10 0x1fa +- +-#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ +-#define KEY_NUMERIC_1 0x201 /* and other keypads */ +-#define KEY_NUMERIC_2 0x202 +-#define KEY_NUMERIC_3 0x203 +-#define KEY_NUMERIC_4 0x204 +-#define KEY_NUMERIC_5 0x205 +-#define KEY_NUMERIC_6 0x206 +-#define KEY_NUMERIC_7 0x207 +-#define KEY_NUMERIC_8 0x208 +-#define KEY_NUMERIC_9 0x209 +-#define KEY_NUMERIC_STAR 0x20a +-#define KEY_NUMERIC_POUND 0x20b +-#define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */ +-#define KEY_NUMERIC_B 0x20d +-#define KEY_NUMERIC_C 0x20e +-#define KEY_NUMERIC_D 0x20f +- +-#define KEY_CAMERA_FOCUS 0x210 +-#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ +- +-#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ +-#define KEY_TOUCHPAD_ON 0x213 +-#define KEY_TOUCHPAD_OFF 0x214 +- +-#define KEY_CAMERA_ZOOMIN 0x215 +-#define KEY_CAMERA_ZOOMOUT 0x216 +-#define KEY_CAMERA_UP 0x217 +-#define KEY_CAMERA_DOWN 0x218 +-#define KEY_CAMERA_LEFT 0x219 +-#define KEY_CAMERA_RIGHT 0x21a +- +-#define KEY_ATTENDANT_ON 0x21b +-#define KEY_ATTENDANT_OFF 0x21c +-#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ +-#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ +- +-#define BTN_DPAD_UP 0x220 +-#define BTN_DPAD_DOWN 0x221 +-#define BTN_DPAD_LEFT 0x222 +-#define BTN_DPAD_RIGHT 0x223 +- +-#define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ +-#define KEY_ROTATE_LOCK_TOGGLE 0x231 /* Display rotation lock */ +- +-#define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ +-#define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ +-#define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ +-#define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ +-#define KEY_APPSELECT 0x244 /* AL Select Task/Application */ +-#define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ +-#define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ +-#define KEY_ASSISTANT 0x247 /* AL Context-aware desktop assistant */ +-#define KEY_KBD_LAYOUT_NEXT 0x248 /* AC Next Keyboard Layout Select */ +-#define KEY_EMOJI_PICKER 0x249 /* Show/hide emoji picker (HUTRR101) */ +-#define KEY_DICTATE 0x24a /* Start or Stop Voice Dictation Session (HUTRR99) */ +- +-#define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ +-#define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ +- +-#define KEY_KBDINPUTASSIST_PREV 0x260 +-#define KEY_KBDINPUTASSIST_NEXT 0x261 +-#define KEY_KBDINPUTASSIST_PREVGROUP 0x262 +-#define KEY_KBDINPUTASSIST_NEXTGROUP 0x263 +-#define KEY_KBDINPUTASSIST_ACCEPT 0x264 +-#define KEY_KBDINPUTASSIST_CANCEL 0x265 +- +-/* Diagonal movement keys */ +-#define KEY_RIGHT_UP 0x266 +-#define KEY_RIGHT_DOWN 0x267 +-#define KEY_LEFT_UP 0x268 +-#define KEY_LEFT_DOWN 0x269 +- +-#define KEY_ROOT_MENU 0x26a /* Show Device's Root Menu */ +-/* Show Top Menu of the Media (e.g. DVD) */ +-#define KEY_MEDIA_TOP_MENU 0x26b +-#define KEY_NUMERIC_11 0x26c +-#define KEY_NUMERIC_12 0x26d +-/* +- * Toggle Audio Description: refers to an audio service that helps blind and +- * visually impaired consumers understand the action in a program. Note: in +- * some countries this is referred to as "Video Description". +- */ +-#define KEY_AUDIO_DESC 0x26e +-#define KEY_3D_MODE 0x26f +-#define KEY_NEXT_FAVORITE 0x270 +-#define KEY_STOP_RECORD 0x271 +-#define KEY_PAUSE_RECORD 0x272 +-#define KEY_VOD 0x273 /* Video on Demand */ +-#define KEY_UNMUTE 0x274 +-#define KEY_FASTREVERSE 0x275 +-#define KEY_SLOWREVERSE 0x276 +-/* +- * Control a data application associated with the currently viewed channel, +- * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.) +- */ +-#define KEY_DATA 0x277 +-#define KEY_ONSCREEN_KEYBOARD 0x278 +-/* Electronic privacy screen control */ +-#define KEY_PRIVACY_SCREEN_TOGGLE 0x279 +- +-/* Select an area of screen to be copied */ +-#define KEY_SELECTIVE_SCREENSHOT 0x27a +- +-/* +- * Some keyboards have keys which do not have a defined meaning, these keys +- * are intended to be programmed / bound to macros by the user. For most +- * keyboards with these macro-keys the key-sequence to inject, or action to +- * take, is all handled by software on the host side. So from the kernel's +- * point of view these are just normal keys. +- * +- * The KEY_MACRO# codes below are intended for such keys, which may be labeled +- * e.g. G1-G18, or S1 - S30. The KEY_MACRO# codes MUST NOT be used for keys +- * where the marking on the key does indicate a defined meaning / purpose. +- * +- * The KEY_MACRO# codes MUST also NOT be used as fallback for when no existing +- * KEY_FOO define matches the marking / purpose. In this case a new KEY_FOO +- * define MUST be added. +- */ +-#define KEY_MACRO1 0x290 +-#define KEY_MACRO2 0x291 +-#define KEY_MACRO3 0x292 +-#define KEY_MACRO4 0x293 +-#define KEY_MACRO5 0x294 +-#define KEY_MACRO6 0x295 +-#define KEY_MACRO7 0x296 +-#define KEY_MACRO8 0x297 +-#define KEY_MACRO9 0x298 +-#define KEY_MACRO10 0x299 +-#define KEY_MACRO11 0x29a +-#define KEY_MACRO12 0x29b +-#define KEY_MACRO13 0x29c +-#define KEY_MACRO14 0x29d +-#define KEY_MACRO15 0x29e +-#define KEY_MACRO16 0x29f +-#define KEY_MACRO17 0x2a0 +-#define KEY_MACRO18 0x2a1 +-#define KEY_MACRO19 0x2a2 +-#define KEY_MACRO20 0x2a3 +-#define KEY_MACRO21 0x2a4 +-#define KEY_MACRO22 0x2a5 +-#define KEY_MACRO23 0x2a6 +-#define KEY_MACRO24 0x2a7 +-#define KEY_MACRO25 0x2a8 +-#define KEY_MACRO26 0x2a9 +-#define KEY_MACRO27 0x2aa +-#define KEY_MACRO28 0x2ab +-#define KEY_MACRO29 0x2ac +-#define KEY_MACRO30 0x2ad +- +-/* +- * Some keyboards with the macro-keys described above have some extra keys +- * for controlling the host-side software responsible for the macro handling: +- * -A macro recording start/stop key. Note that not all keyboards which emit +- * KEY_MACRO_RECORD_START will also emit KEY_MACRO_RECORD_STOP if +- * KEY_MACRO_RECORD_STOP is not advertised, then KEY_MACRO_RECORD_START +- * should be interpreted as a recording start/stop toggle; +- * -Keys for switching between different macro (pre)sets, either a key for +- * cycling through the configured presets or keys to directly select a preset. +- */ +-#define KEY_MACRO_RECORD_START 0x2b0 +-#define KEY_MACRO_RECORD_STOP 0x2b1 +-#define KEY_MACRO_PRESET_CYCLE 0x2b2 +-#define KEY_MACRO_PRESET1 0x2b3 +-#define KEY_MACRO_PRESET2 0x2b4 +-#define KEY_MACRO_PRESET3 0x2b5 +- +-/* +- * Some keyboards have a buildin LCD panel where the contents are controlled +- * by the host. Often these have a number of keys directly below the LCD +- * intended for controlling a menu shown on the LCD. These keys often don't +- * have any labeling so we just name them KEY_KBD_LCD_MENU# +- */ +-#define KEY_KBD_LCD_MENU1 0x2b8 +-#define KEY_KBD_LCD_MENU2 0x2b9 +-#define KEY_KBD_LCD_MENU3 0x2ba +-#define KEY_KBD_LCD_MENU4 0x2bb +-#define KEY_KBD_LCD_MENU5 0x2bc +- +-#define BTN_TRIGGER_HAPPY 0x2c0 +-#define BTN_TRIGGER_HAPPY1 0x2c0 +-#define BTN_TRIGGER_HAPPY2 0x2c1 +-#define BTN_TRIGGER_HAPPY3 0x2c2 +-#define BTN_TRIGGER_HAPPY4 0x2c3 +-#define BTN_TRIGGER_HAPPY5 0x2c4 +-#define BTN_TRIGGER_HAPPY6 0x2c5 +-#define BTN_TRIGGER_HAPPY7 0x2c6 +-#define BTN_TRIGGER_HAPPY8 0x2c7 +-#define BTN_TRIGGER_HAPPY9 0x2c8 +-#define BTN_TRIGGER_HAPPY10 0x2c9 +-#define BTN_TRIGGER_HAPPY11 0x2ca +-#define BTN_TRIGGER_HAPPY12 0x2cb +-#define BTN_TRIGGER_HAPPY13 0x2cc +-#define BTN_TRIGGER_HAPPY14 0x2cd +-#define BTN_TRIGGER_HAPPY15 0x2ce +-#define BTN_TRIGGER_HAPPY16 0x2cf +-#define BTN_TRIGGER_HAPPY17 0x2d0 +-#define BTN_TRIGGER_HAPPY18 0x2d1 +-#define BTN_TRIGGER_HAPPY19 0x2d2 +-#define BTN_TRIGGER_HAPPY20 0x2d3 +-#define BTN_TRIGGER_HAPPY21 0x2d4 +-#define BTN_TRIGGER_HAPPY22 0x2d5 +-#define BTN_TRIGGER_HAPPY23 0x2d6 +-#define BTN_TRIGGER_HAPPY24 0x2d7 +-#define BTN_TRIGGER_HAPPY25 0x2d8 +-#define BTN_TRIGGER_HAPPY26 0x2d9 +-#define BTN_TRIGGER_HAPPY27 0x2da +-#define BTN_TRIGGER_HAPPY28 0x2db +-#define BTN_TRIGGER_HAPPY29 0x2dc +-#define BTN_TRIGGER_HAPPY30 0x2dd +-#define BTN_TRIGGER_HAPPY31 0x2de +-#define BTN_TRIGGER_HAPPY32 0x2df +-#define BTN_TRIGGER_HAPPY33 0x2e0 +-#define BTN_TRIGGER_HAPPY34 0x2e1 +-#define BTN_TRIGGER_HAPPY35 0x2e2 +-#define BTN_TRIGGER_HAPPY36 0x2e3 +-#define BTN_TRIGGER_HAPPY37 0x2e4 +-#define BTN_TRIGGER_HAPPY38 0x2e5 +-#define BTN_TRIGGER_HAPPY39 0x2e6 +-#define BTN_TRIGGER_HAPPY40 0x2e7 +- +-/* We avoid low common keys in module aliases so they don't get huge. */ +-#define KEY_MIN_INTERESTING KEY_MUTE +-#define KEY_MAX 0x2ff +-#define KEY_CNT (KEY_MAX+1) +- +-/* +- * Relative axes +- */ +- +-#define REL_X 0x00 +-#define REL_Y 0x01 +-#define REL_Z 0x02 +-#define REL_RX 0x03 +-#define REL_RY 0x04 +-#define REL_RZ 0x05 +-#define REL_HWHEEL 0x06 +-#define REL_DIAL 0x07 +-#define REL_WHEEL 0x08 +-#define REL_MISC 0x09 +-/* +- * 0x0a is reserved and should not be used in input drivers. +- * It was used by HID as REL_MISC+1 and userspace needs to detect if +- * the next REL_* event is correct or is just REL_MISC + n. +- * We define here REL_RESERVED so userspace can rely on it and detect +- * the situation described above. +- */ +-#define REL_RESERVED 0x0a +-#define REL_WHEEL_HI_RES 0x0b +-#define REL_HWHEEL_HI_RES 0x0c +-#define REL_MAX 0x0f +-#define REL_CNT (REL_MAX+1) +- +-/* +- * Absolute axes +- */ +- +-#define ABS_X 0x00 +-#define ABS_Y 0x01 +-#define ABS_Z 0x02 +-#define ABS_RX 0x03 +-#define ABS_RY 0x04 +-#define ABS_RZ 0x05 +-#define ABS_THROTTLE 0x06 +-#define ABS_RUDDER 0x07 +-#define ABS_WHEEL 0x08 +-#define ABS_GAS 0x09 +-#define ABS_BRAKE 0x0a +-#define ABS_HAT0X 0x10 +-#define ABS_HAT0Y 0x11 +-#define ABS_HAT1X 0x12 +-#define ABS_HAT1Y 0x13 +-#define ABS_HAT2X 0x14 +-#define ABS_HAT2Y 0x15 +-#define ABS_HAT3X 0x16 +-#define ABS_HAT3Y 0x17 +-#define ABS_PRESSURE 0x18 +-#define ABS_DISTANCE 0x19 +-#define ABS_TILT_X 0x1a +-#define ABS_TILT_Y 0x1b +-#define ABS_TOOL_WIDTH 0x1c +- +-#define ABS_VOLUME 0x20 +- +-#define ABS_MISC 0x28 +- +-/* +- * 0x2e is reserved and should not be used in input drivers. +- * It was used by HID as ABS_MISC+6 and userspace needs to detect if +- * the next ABS_* event is correct or is just ABS_MISC + n. +- * We define here ABS_RESERVED so userspace can rely on it and detect +- * the situation described above. +- */ +-#define ABS_RESERVED 0x2e +- +-#define ABS_MT_SLOT 0x2f /* MT slot being modified */ +-#define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ +-#define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ +-#define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ +-#define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ +-#define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ +-#define ABS_MT_POSITION_X 0x35 /* Center X touch position */ +-#define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ +-#define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ +-#define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ +-#define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ +-#define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ +-#define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ +-#define ABS_MT_TOOL_X 0x3c /* Center X tool position */ +-#define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ +- +- +-#define ABS_MAX 0x3f +-#define ABS_CNT (ABS_MAX+1) +- +-/* +- * Switch events +- */ +- +-#define SW_LID 0x00 /* set = lid shut */ +-#define SW_TABLET_MODE 0x01 /* set = tablet mode */ +-#define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ +-#define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" +- set = radio enabled */ +-#define SW_RADIO SW_RFKILL_ALL /* deprecated */ +-#define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ +-#define SW_DOCK 0x05 /* set = plugged into dock */ +-#define SW_LINEOUT_INSERT 0x06 /* set = inserted */ +-#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ +-#define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ +-#define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ +-#define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ +-#define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ +-#define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ +-#define SW_LINEIN_INSERT 0x0d /* set = inserted */ +-#define SW_MUTE_DEVICE 0x0e /* set = device disabled */ +-#define SW_PEN_INSERTED 0x0f /* set = pen inserted */ +-#define SW_MACHINE_COVER 0x10 /* set = cover closed */ +-#define SW_MAX 0x10 +-#define SW_CNT (SW_MAX+1) +- +-/* +- * Misc events +- */ +- +-#define MSC_SERIAL 0x00 +-#define MSC_PULSELED 0x01 +-#define MSC_GESTURE 0x02 +-#define MSC_RAW 0x03 +-#define MSC_SCAN 0x04 +-#define MSC_TIMESTAMP 0x05 +-#define MSC_MAX 0x07 +-#define MSC_CNT (MSC_MAX+1) +- +-/* +- * LEDs +- */ +- +-#define LED_NUML 0x00 +-#define LED_CAPSL 0x01 +-#define LED_SCROLLL 0x02 +-#define LED_COMPOSE 0x03 +-#define LED_KANA 0x04 +-#define LED_SLEEP 0x05 +-#define LED_SUSPEND 0x06 +-#define LED_MUTE 0x07 +-#define LED_MISC 0x08 +-#define LED_MAIL 0x09 +-#define LED_CHARGING 0x0a +-#define LED_MAX 0x0f +-#define LED_CNT (LED_MAX+1) +- +-/* +- * Autorepeat values +- */ +- +-#define REP_DELAY 0x00 +-#define REP_PERIOD 0x01 +-#define REP_MAX 0x01 +-#define REP_CNT (REP_MAX+1) +- +-/* +- * Sounds +- */ +- +-#define SND_CLICK 0x00 +-#define SND_BELL 0x01 +-#define SND_TONE 0x02 +-#define SND_MAX 0x07 +-#define SND_CNT (SND_MAX+1) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/input/ti-drv260x.h b/scripts/dtc/include-prefixes/dt-bindings/input/ti-drv260x.h +deleted file mode 100644 +index af71082dd18c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/input/ti-drv260x.h ++++ /dev/null +@@ -1,28 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * DRV260X haptics driver family +- * +- * Author: Dan Murphy +- * +- * Copyright: (C) 2014 Texas Instruments, Inc. +- */ +- +-#ifndef _DT_BINDINGS_TI_DRV260X_H +-#define _DT_BINDINGS_TI_DRV260X_H +- +-/* Calibration Types */ +-#define DRV260X_LRA_MODE 0x00 +-#define DRV260X_LRA_NO_CAL_MODE 0x01 +-#define DRV260X_ERM_MODE 0x02 +- +-/* Library Selection */ +-#define DRV260X_LIB_EMPTY 0x00 +-#define DRV260X_ERM_LIB_A 0x01 +-#define DRV260X_ERM_LIB_B 0x02 +-#define DRV260X_ERM_LIB_C 0x03 +-#define DRV260X_ERM_LIB_D 0x04 +-#define DRV260X_ERM_LIB_E 0x05 +-#define DRV260X_LIB_LRA 0x06 +-#define DRV260X_ERM_LIB_F 0x07 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interconnect/imx8mm.h b/scripts/dtc/include-prefixes/dt-bindings/interconnect/imx8mm.h +deleted file mode 100644 +index 8f10bb06cb59..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interconnect/imx8mm.h ++++ /dev/null +@@ -1,50 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Interconnect framework driver for i.MX SoC +- * +- * Copyright (c) 2019, BayLibre +- * Copyright (c) 2019-2020, NXP +- * Author: Alexandre Bailon +- */ +- +-#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MM_H +-#define __DT_BINDINGS_INTERCONNECT_IMX8MM_H +- +-#define IMX8MM_ICN_NOC 1 +-#define IMX8MM_ICS_DRAM 2 +-#define IMX8MM_ICS_OCRAM 3 +-#define IMX8MM_ICM_A53 4 +- +-#define IMX8MM_ICM_VPU_H1 5 +-#define IMX8MM_ICM_VPU_G1 6 +-#define IMX8MM_ICM_VPU_G2 7 +-#define IMX8MM_ICN_VIDEO 8 +- +-#define IMX8MM_ICM_GPU2D 9 +-#define IMX8MM_ICM_GPU3D 10 +-#define IMX8MM_ICN_GPU 11 +- +-#define IMX8MM_ICM_CSI 12 +-#define IMX8MM_ICM_LCDIF 13 +-#define IMX8MM_ICN_MIPI 14 +- +-#define IMX8MM_ICM_USB1 15 +-#define IMX8MM_ICM_USB2 16 +-#define IMX8MM_ICM_PCIE 17 +-#define IMX8MM_ICN_HSIO 18 +- +-#define IMX8MM_ICM_SDMA2 19 +-#define IMX8MM_ICM_SDMA3 20 +-#define IMX8MM_ICN_AUDIO 21 +- +-#define IMX8MM_ICN_ENET 22 +-#define IMX8MM_ICM_ENET 23 +- +-#define IMX8MM_ICN_MAIN 24 +-#define IMX8MM_ICM_NAND 25 +-#define IMX8MM_ICM_SDMA1 26 +-#define IMX8MM_ICM_USDHC1 27 +-#define IMX8MM_ICM_USDHC2 28 +-#define IMX8MM_ICM_USDHC3 29 +- +-#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MM_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interconnect/imx8mn.h b/scripts/dtc/include-prefixes/dt-bindings/interconnect/imx8mn.h +deleted file mode 100644 +index 307b977100b6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interconnect/imx8mn.h ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Interconnect framework driver for i.MX SoC +- * +- * Copyright (c) 2019-2020, NXP +- */ +- +-#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MN_H +-#define __DT_BINDINGS_INTERCONNECT_IMX8MN_H +- +-#define IMX8MN_ICN_NOC 1 +-#define IMX8MN_ICS_DRAM 2 +-#define IMX8MN_ICS_OCRAM 3 +-#define IMX8MN_ICM_A53 4 +- +-#define IMX8MN_ICM_GPU 5 +-#define IMX8MN_ICN_GPU 6 +- +-#define IMX8MN_ICM_CSI1 7 +-#define IMX8MN_ICM_CSI2 8 +-#define IMX8MN_ICM_ISI 9 +-#define IMX8MN_ICM_LCDIF 10 +-#define IMX8MN_ICN_MIPI 11 +- +-#define IMX8MN_ICM_USB 12 +- +-#define IMX8MN_ICM_SDMA2 13 +-#define IMX8MN_ICM_SDMA3 14 +-#define IMX8MN_ICN_AUDIO 15 +- +-#define IMX8MN_ICN_ENET 16 +-#define IMX8MN_ICM_ENET 17 +- +-#define IMX8MN_ICM_NAND 18 +-#define IMX8MN_ICM_SDMA1 19 +-#define IMX8MN_ICM_USDHC1 20 +-#define IMX8MN_ICM_USDHC2 21 +-#define IMX8MN_ICM_USDHC3 22 +-#define IMX8MN_ICN_MAIN 23 +- +-#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MN_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interconnect/imx8mq.h b/scripts/dtc/include-prefixes/dt-bindings/interconnect/imx8mq.h +deleted file mode 100644 +index 1a4cae7f8be2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interconnect/imx8mq.h ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Interconnect framework driver for i.MX SoC +- * +- * Copyright (c) 2019-2020, NXP +- */ +- +-#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MQ_H +-#define __DT_BINDINGS_INTERCONNECT_IMX8MQ_H +- +-#define IMX8MQ_ICN_NOC 1 +-#define IMX8MQ_ICS_DRAM 2 +-#define IMX8MQ_ICS_OCRAM 3 +-#define IMX8MQ_ICM_A53 4 +- +-#define IMX8MQ_ICM_VPU 5 +-#define IMX8MQ_ICN_VIDEO 6 +- +-#define IMX8MQ_ICM_GPU 7 +-#define IMX8MQ_ICN_GPU 8 +- +-#define IMX8MQ_ICM_DCSS 9 +-#define IMX8MQ_ICN_DCSS 10 +- +-#define IMX8MQ_ICM_USB1 11 +-#define IMX8MQ_ICM_USB2 12 +-#define IMX8MQ_ICN_USB 13 +- +-#define IMX8MQ_ICM_CSI1 14 +-#define IMX8MQ_ICM_CSI2 15 +-#define IMX8MQ_ICM_LCDIF 16 +-#define IMX8MQ_ICN_DISPLAY 17 +- +-#define IMX8MQ_ICM_SDMA2 18 +-#define IMX8MQ_ICN_AUDIO 19 +- +-#define IMX8MQ_ICN_ENET 20 +-#define IMX8MQ_ICM_ENET 21 +- +-#define IMX8MQ_ICM_SDMA1 22 +-#define IMX8MQ_ICM_NAND 23 +-#define IMX8MQ_ICM_USDHC1 24 +-#define IMX8MQ_ICM_USDHC2 25 +-#define IMX8MQ_ICM_PCIE1 26 +-#define IMX8MQ_ICM_PCIE2 27 +-#define IMX8MQ_ICN_MAIN 28 +- +-#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MQ_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,icc.h b/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,icc.h +deleted file mode 100644 +index cd34f36daaaa..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,icc.h ++++ /dev/null +@@ -1,26 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_ICC_H +-#define __DT_BINDINGS_INTERCONNECT_QCOM_ICC_H +- +-/* +- * The AMC bucket denotes constraints that are applied to hardware when +- * icc_set_bw() completes, whereas the WAKE and SLEEP constraints are applied +- * when the execution environment transitions between active and low power mode. +- */ +-#define QCOM_ICC_BUCKET_AMC 0 +-#define QCOM_ICC_BUCKET_WAKE 1 +-#define QCOM_ICC_BUCKET_SLEEP 2 +-#define QCOM_ICC_NUM_BUCKETS 3 +- +-#define QCOM_ICC_TAG_AMC (1 << QCOM_ICC_BUCKET_AMC) +-#define QCOM_ICC_TAG_WAKE (1 << QCOM_ICC_BUCKET_WAKE) +-#define QCOM_ICC_TAG_SLEEP (1 << QCOM_ICC_BUCKET_SLEEP) +-#define QCOM_ICC_TAG_ACTIVE_ONLY (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE) +-#define QCOM_ICC_TAG_ALWAYS (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE |\ +- QCOM_ICC_TAG_SLEEP) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,msm8916.h b/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,msm8916.h +deleted file mode 100644 +index 359a75feb198..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,msm8916.h ++++ /dev/null +@@ -1,100 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Qualcomm interconnect IDs +- * +- * Copyright (c) 2019, Linaro Ltd. +- * Author: Georgi Djakov +- */ +- +-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H +-#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H +- +-#define BIMC_SNOC_SLV 0 +-#define MASTER_JPEG 1 +-#define MASTER_MDP_PORT0 2 +-#define MASTER_QDSS_BAM 3 +-#define MASTER_QDSS_ETR 4 +-#define MASTER_SNOC_CFG 5 +-#define MASTER_VFE 6 +-#define MASTER_VIDEO_P0 7 +-#define SNOC_MM_INT_0 8 +-#define SNOC_MM_INT_1 9 +-#define SNOC_MM_INT_2 10 +-#define SNOC_MM_INT_BIMC 11 +-#define PCNOC_SNOC_SLV 12 +-#define SLAVE_APSS 13 +-#define SLAVE_CATS_128 14 +-#define SLAVE_OCMEM_64 15 +-#define SLAVE_IMEM 16 +-#define SLAVE_QDSS_STM 17 +-#define SLAVE_SRVC_SNOC 18 +-#define SNOC_BIMC_0_MAS 19 +-#define SNOC_BIMC_1_MAS 20 +-#define SNOC_INT_0 21 +-#define SNOC_INT_1 22 +-#define SNOC_INT_BIMC 23 +-#define SNOC_PCNOC_MAS 24 +-#define SNOC_QDSS_INT 25 +- +-#define BIMC_SNOC_MAS 0 +-#define MASTER_AMPSS_M0 1 +-#define MASTER_GRAPHICS_3D 2 +-#define MASTER_TCU0 3 +-#define MASTER_TCU1 4 +-#define SLAVE_AMPSS_L2 5 +-#define SLAVE_EBI_CH0 6 +-#define SNOC_BIMC_0_SLV 7 +-#define SNOC_BIMC_1_SLV 8 +- +-#define MASTER_BLSP_1 0 +-#define MASTER_DEHR 1 +-#define MASTER_LPASS 2 +-#define MASTER_CRYPTO_CORE0 3 +-#define MASTER_SDCC_1 4 +-#define MASTER_SDCC_2 5 +-#define MASTER_SPDM 6 +-#define MASTER_USB_HS 7 +-#define PCNOC_INT_0 8 +-#define PCNOC_INT_1 9 +-#define PCNOC_MAS_0 10 +-#define PCNOC_MAS_1 11 +-#define PCNOC_SLV_0 12 +-#define PCNOC_SLV_1 13 +-#define PCNOC_SLV_2 14 +-#define PCNOC_SLV_3 15 +-#define PCNOC_SLV_4 16 +-#define PCNOC_SLV_8 17 +-#define PCNOC_SLV_9 18 +-#define PCNOC_SNOC_MAS 19 +-#define SLAVE_BIMC_CFG 20 +-#define SLAVE_BLSP_1 21 +-#define SLAVE_BOOT_ROM 22 +-#define SLAVE_CAMERA_CFG 23 +-#define SLAVE_CLK_CTL 24 +-#define SLAVE_CRYPTO_0_CFG 25 +-#define SLAVE_DEHR_CFG 26 +-#define SLAVE_DISPLAY_CFG 27 +-#define SLAVE_GRAPHICS_3D_CFG 28 +-#define SLAVE_IMEM_CFG 29 +-#define SLAVE_LPASS 30 +-#define SLAVE_MPM 31 +-#define SLAVE_MSG_RAM 32 +-#define SLAVE_MSS 33 +-#define SLAVE_PDM 34 +-#define SLAVE_PMIC_ARB 35 +-#define SLAVE_PCNOC_CFG 36 +-#define SLAVE_PRNG 37 +-#define SLAVE_QDSS_CFG 38 +-#define SLAVE_RBCPR_CFG 39 +-#define SLAVE_SDCC_1 40 +-#define SLAVE_SDCC_2 41 +-#define SLAVE_SECURITY 42 +-#define SLAVE_SNOC_CFG 43 +-#define SLAVE_SPDM 44 +-#define SLAVE_TCSR 45 +-#define SLAVE_TLMM 46 +-#define SLAVE_USB_HS 47 +-#define SLAVE_VENUS_CFG 48 +-#define SNOC_PCNOC_SLV 49 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,msm8939.h b/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,msm8939.h +deleted file mode 100644 +index c22369a4b9f5..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,msm8939.h ++++ /dev/null +@@ -1,105 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Qualcomm interconnect IDs +- * +- * Copyright (c) 2020, Linaro Ltd. +- * Author: Jun Nie +- */ +- +-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8939_H +-#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8939_H +- +-#define BIMC_SNOC_SLV 0 +-#define MASTER_QDSS_BAM 1 +-#define MASTER_QDSS_ETR 2 +-#define MASTER_SNOC_CFG 3 +-#define PCNOC_SNOC_SLV 4 +-#define SLAVE_APSS 5 +-#define SLAVE_CATS_128 6 +-#define SLAVE_OCMEM_64 7 +-#define SLAVE_IMEM 8 +-#define SLAVE_QDSS_STM 9 +-#define SLAVE_SRVC_SNOC 10 +-#define SNOC_BIMC_0_MAS 11 +-#define SNOC_BIMC_1_MAS 12 +-#define SNOC_BIMC_2_MAS 13 +-#define SNOC_INT_0 14 +-#define SNOC_INT_1 15 +-#define SNOC_INT_BIMC 16 +-#define SNOC_PCNOC_MAS 17 +-#define SNOC_QDSS_INT 18 +- +-#define MASTER_VIDEO_P0 0 +-#define MASTER_JPEG 1 +-#define MASTER_VFE 2 +-#define MASTER_MDP_PORT0 3 +-#define MASTER_MDP_PORT1 4 +-#define MASTER_CPP 5 +-#define SNOC_MM_INT_0 6 +-#define SNOC_MM_INT_1 7 +-#define SNOC_MM_INT_2 8 +- +-#define BIMC_SNOC_MAS 0 +-#define MASTER_AMPSS_M0 1 +-#define MASTER_GRAPHICS_3D 2 +-#define MASTER_TCU0 3 +-#define SLAVE_AMPSS_L2 4 +-#define SLAVE_EBI_CH0 5 +-#define SNOC_BIMC_0_SLV 6 +-#define SNOC_BIMC_1_SLV 7 +-#define SNOC_BIMC_2_SLV 8 +- +-#define MASTER_BLSP_1 0 +-#define MASTER_DEHR 1 +-#define MASTER_LPASS 2 +-#define MASTER_CRYPTO_CORE0 3 +-#define MASTER_SDCC_1 4 +-#define MASTER_SDCC_2 5 +-#define MASTER_SPDM 6 +-#define MASTER_USB_HS1 7 +-#define MASTER_USB_HS2 8 +-#define PCNOC_INT_0 9 +-#define PCNOC_INT_1 10 +-#define PCNOC_MAS_0 11 +-#define PCNOC_MAS_1 12 +-#define PCNOC_SLV_0 13 +-#define PCNOC_SLV_1 14 +-#define PCNOC_SLV_2 15 +-#define PCNOC_SLV_3 16 +-#define PCNOC_SLV_4 17 +-#define PCNOC_SLV_8 18 +-#define PCNOC_SLV_9 19 +-#define PCNOC_SNOC_MAS 20 +-#define SLAVE_BIMC_CFG 21 +-#define SLAVE_BLSP_1 22 +-#define SLAVE_BOOT_ROM 23 +-#define SLAVE_CAMERA_CFG 24 +-#define SLAVE_CLK_CTL 25 +-#define SLAVE_CRYPTO_0_CFG 26 +-#define SLAVE_DEHR_CFG 27 +-#define SLAVE_DISPLAY_CFG 28 +-#define SLAVE_GRAPHICS_3D_CFG 29 +-#define SLAVE_IMEM_CFG 30 +-#define SLAVE_LPASS 31 +-#define SLAVE_MPM 32 +-#define SLAVE_MSG_RAM 33 +-#define SLAVE_MSS 34 +-#define SLAVE_PDM 35 +-#define SLAVE_PMIC_ARB 36 +-#define SLAVE_PCNOC_CFG 37 +-#define SLAVE_PRNG 38 +-#define SLAVE_QDSS_CFG 39 +-#define SLAVE_RBCPR_CFG 40 +-#define SLAVE_SDCC_1 41 +-#define SLAVE_SDCC_2 42 +-#define SLAVE_SECURITY 43 +-#define SLAVE_SNOC_CFG 44 +-#define SLAVE_SPDM 45 +-#define SLAVE_TCSR 46 +-#define SLAVE_TLMM 47 +-#define SLAVE_USB_HS1 48 +-#define SLAVE_USB_HS2 49 +-#define SLAVE_VENUS_CFG 50 +-#define SNOC_PCNOC_SLV 51 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,msm8974.h b/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,msm8974.h +deleted file mode 100644 +index e65ae27ffff2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,msm8974.h ++++ /dev/null +@@ -1,146 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ +-/* +- * Qualcomm msm8974 interconnect IDs +- * +- * Copyright (c) 2019 Brian Masney +- */ +- +-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8974_H +-#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8974_H +- +-#define BIMC_MAS_AMPSS_M0 0 +-#define BIMC_MAS_AMPSS_M1 1 +-#define BIMC_MAS_MSS_PROC 2 +-#define BIMC_TO_MNOC 3 +-#define BIMC_TO_SNOC 4 +-#define BIMC_SLV_EBI_CH0 5 +-#define BIMC_SLV_AMPSS_L2 6 +- +-#define CNOC_MAS_RPM_INST 0 +-#define CNOC_MAS_RPM_DATA 1 +-#define CNOC_MAS_RPM_SYS 2 +-#define CNOC_MAS_DEHR 3 +-#define CNOC_MAS_QDSS_DAP 4 +-#define CNOC_MAS_SPDM 5 +-#define CNOC_MAS_TIC 6 +-#define CNOC_SLV_CLK_CTL 7 +-#define CNOC_SLV_CNOC_MSS 8 +-#define CNOC_SLV_SECURITY 9 +-#define CNOC_SLV_TCSR 10 +-#define CNOC_SLV_TLMM 11 +-#define CNOC_SLV_CRYPTO_0_CFG 12 +-#define CNOC_SLV_CRYPTO_1_CFG 13 +-#define CNOC_SLV_IMEM_CFG 14 +-#define CNOC_SLV_MESSAGE_RAM 15 +-#define CNOC_SLV_BIMC_CFG 16 +-#define CNOC_SLV_BOOT_ROM 17 +-#define CNOC_SLV_PMIC_ARB 18 +-#define CNOC_SLV_SPDM_WRAPPER 19 +-#define CNOC_SLV_DEHR_CFG 20 +-#define CNOC_SLV_MPM 21 +-#define CNOC_SLV_QDSS_CFG 22 +-#define CNOC_SLV_RBCPR_CFG 23 +-#define CNOC_SLV_RBCPR_QDSS_APU_CFG 24 +-#define CNOC_TO_SNOC 25 +-#define CNOC_SLV_CNOC_ONOC_CFG 26 +-#define CNOC_SLV_CNOC_MNOC_MMSS_CFG 27 +-#define CNOC_SLV_CNOC_MNOC_CFG 28 +-#define CNOC_SLV_PNOC_CFG 29 +-#define CNOC_SLV_SNOC_MPU_CFG 30 +-#define CNOC_SLV_SNOC_CFG 31 +-#define CNOC_SLV_EBI1_DLL_CFG 32 +-#define CNOC_SLV_PHY_APU_CFG 33 +-#define CNOC_SLV_EBI1_PHY_CFG 34 +-#define CNOC_SLV_RPM 35 +-#define CNOC_SLV_SERVICE_CNOC 36 +- +-#define MNOC_MAS_GRAPHICS_3D 0 +-#define MNOC_MAS_JPEG 1 +-#define MNOC_MAS_MDP_PORT0 2 +-#define MNOC_MAS_VIDEO_P0 3 +-#define MNOC_MAS_VIDEO_P1 4 +-#define MNOC_MAS_VFE 5 +-#define MNOC_TO_CNOC 6 +-#define MNOC_TO_BIMC 7 +-#define MNOC_SLV_CAMERA_CFG 8 +-#define MNOC_SLV_DISPLAY_CFG 9 +-#define MNOC_SLV_OCMEM_CFG 10 +-#define MNOC_SLV_CPR_CFG 11 +-#define MNOC_SLV_CPR_XPU_CFG 12 +-#define MNOC_SLV_MISC_CFG 13 +-#define MNOC_SLV_MISC_XPU_CFG 14 +-#define MNOC_SLV_VENUS_CFG 15 +-#define MNOC_SLV_GRAPHICS_3D_CFG 16 +-#define MNOC_SLV_MMSS_CLK_CFG 17 +-#define MNOC_SLV_MMSS_CLK_XPU_CFG 18 +-#define MNOC_SLV_MNOC_MPU_CFG 19 +-#define MNOC_SLV_ONOC_MPU_CFG 20 +-#define MNOC_SLV_SERVICE_MNOC 21 +- +-#define OCMEM_NOC_TO_OCMEM_VNOC 0 +-#define OCMEM_MAS_JPEG_OCMEM 1 +-#define OCMEM_MAS_MDP_OCMEM 2 +-#define OCMEM_MAS_VIDEO_P0_OCMEM 3 +-#define OCMEM_MAS_VIDEO_P1_OCMEM 4 +-#define OCMEM_MAS_VFE_OCMEM 5 +-#define OCMEM_MAS_CNOC_ONOC_CFG 6 +-#define OCMEM_SLV_SERVICE_ONOC 7 +-#define OCMEM_VNOC_TO_SNOC 8 +-#define OCMEM_VNOC_TO_OCMEM_NOC 9 +-#define OCMEM_VNOC_MAS_GFX3D 10 +-#define OCMEM_SLV_OCMEM 11 +- +-#define PNOC_MAS_PNOC_CFG 0 +-#define PNOC_MAS_SDCC_1 1 +-#define PNOC_MAS_SDCC_3 2 +-#define PNOC_MAS_SDCC_4 3 +-#define PNOC_MAS_SDCC_2 4 +-#define PNOC_MAS_TSIF 5 +-#define PNOC_MAS_BAM_DMA 6 +-#define PNOC_MAS_BLSP_2 7 +-#define PNOC_MAS_USB_HSIC 8 +-#define PNOC_MAS_BLSP_1 9 +-#define PNOC_MAS_USB_HS 10 +-#define PNOC_TO_SNOC 11 +-#define PNOC_SLV_SDCC_1 12 +-#define PNOC_SLV_SDCC_3 13 +-#define PNOC_SLV_SDCC_2 14 +-#define PNOC_SLV_SDCC_4 15 +-#define PNOC_SLV_TSIF 16 +-#define PNOC_SLV_BAM_DMA 17 +-#define PNOC_SLV_BLSP_2 18 +-#define PNOC_SLV_USB_HSIC 19 +-#define PNOC_SLV_BLSP_1 20 +-#define PNOC_SLV_USB_HS 21 +-#define PNOC_SLV_PDM 22 +-#define PNOC_SLV_PERIPH_APU_CFG 23 +-#define PNOC_SLV_PNOC_MPU_CFG 24 +-#define PNOC_SLV_PRNG 25 +-#define PNOC_SLV_SERVICE_PNOC 26 +- +-#define SNOC_MAS_LPASS_AHB 0 +-#define SNOC_MAS_QDSS_BAM 1 +-#define SNOC_MAS_SNOC_CFG 2 +-#define SNOC_TO_BIMC 3 +-#define SNOC_TO_CNOC 4 +-#define SNOC_TO_PNOC 5 +-#define SNOC_TO_OCMEM_VNOC 6 +-#define SNOC_MAS_CRYPTO_CORE0 7 +-#define SNOC_MAS_CRYPTO_CORE1 8 +-#define SNOC_MAS_LPASS_PROC 9 +-#define SNOC_MAS_MSS 10 +-#define SNOC_MAS_MSS_NAV 11 +-#define SNOC_MAS_OCMEM_DMA 12 +-#define SNOC_MAS_WCSS 13 +-#define SNOC_MAS_QDSS_ETR 14 +-#define SNOC_MAS_USB3 15 +-#define SNOC_SLV_AMPSS 16 +-#define SNOC_SLV_LPASS 17 +-#define SNOC_SLV_USB3 18 +-#define SNOC_SLV_WCSS 19 +-#define SNOC_SLV_OCIMEM 20 +-#define SNOC_SLV_SNOC_OCMEM 21 +-#define SNOC_SLV_SERVICE_SNOC 22 +-#define SNOC_SLV_QDSS_STM 23 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,osm-l3.h b/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,osm-l3.h +deleted file mode 100644 +index 61ef649ae565..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,osm-l3.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2019 The Linux Foundation. All rights reserved. +- */ +- +-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H +-#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H +- +-#define MASTER_OSM_L3_APPS 0 +-#define SLAVE_OSM_L3 1 +- +-#define MASTER_EPSS_L3_APPS 0 +-#define SLAVE_EPSS_L3_SHARED 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,qcs404.h b/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,qcs404.h +deleted file mode 100644 +index 960f6e39c5f2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,qcs404.h ++++ /dev/null +@@ -1,88 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Qualcomm interconnect IDs +- * +- * Copyright (c) 2019, Linaro Ltd. +- * Author: Georgi Djakov +- */ +- +-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H +-#define __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H +- +-#define MASTER_AMPSS_M0 0 +-#define MASTER_OXILI 1 +-#define MASTER_MDP_PORT0 2 +-#define MASTER_SNOC_BIMC_1 3 +-#define MASTER_TCU_0 4 +-#define SLAVE_EBI_CH0 5 +-#define SLAVE_BIMC_SNOC 6 +- +-#define MASTER_SPDM 0 +-#define MASTER_BLSP_1 1 +-#define MASTER_BLSP_2 2 +-#define MASTER_XI_USB_HS1 3 +-#define MASTER_CRYPT0 4 +-#define MASTER_SDCC_1 5 +-#define MASTER_SDCC_2 6 +-#define MASTER_SNOC_PCNOC 7 +-#define MASTER_QPIC 8 +-#define PCNOC_INT_0 9 +-#define PCNOC_INT_2 10 +-#define PCNOC_INT_3 11 +-#define PCNOC_S_0 12 +-#define PCNOC_S_1 13 +-#define PCNOC_S_2 14 +-#define PCNOC_S_3 15 +-#define PCNOC_S_4 16 +-#define PCNOC_S_6 17 +-#define PCNOC_S_7 18 +-#define PCNOC_S_8 19 +-#define PCNOC_S_9 20 +-#define PCNOC_S_10 21 +-#define PCNOC_S_11 22 +-#define SLAVE_SPDM 23 +-#define SLAVE_PDM 24 +-#define SLAVE_PRNG 25 +-#define SLAVE_TCSR 26 +-#define SLAVE_SNOC_CFG 27 +-#define SLAVE_MESSAGE_RAM 28 +-#define SLAVE_DISP_SS_CFG 29 +-#define SLAVE_GPU_CFG 30 +-#define SLAVE_BLSP_1 31 +-#define SLAVE_BLSP_2 32 +-#define SLAVE_TLMM_NORTH 33 +-#define SLAVE_PCIE 34 +-#define SLAVE_ETHERNET 35 +-#define SLAVE_TLMM_EAST 36 +-#define SLAVE_TCU 37 +-#define SLAVE_PMIC_ARB 38 +-#define SLAVE_SDCC_1 39 +-#define SLAVE_SDCC_2 40 +-#define SLAVE_TLMM_SOUTH 41 +-#define SLAVE_USB_HS 42 +-#define SLAVE_USB3 43 +-#define SLAVE_CRYPTO_0_CFG 44 +-#define SLAVE_PCNOC_SNOC 45 +- +-#define MASTER_QDSS_BAM 0 +-#define MASTER_BIMC_SNOC 1 +-#define MASTER_PCNOC_SNOC 2 +-#define MASTER_QDSS_ETR 3 +-#define MASTER_EMAC 4 +-#define MASTER_PCIE 5 +-#define MASTER_USB3 6 +-#define QDSS_INT 7 +-#define SNOC_INT_0 8 +-#define SNOC_INT_1 9 +-#define SNOC_INT_2 10 +-#define SLAVE_KPSS_AHB 11 +-#define SLAVE_WCSS 12 +-#define SLAVE_SNOC_BIMC_1 13 +-#define SLAVE_IMEM 14 +-#define SLAVE_SNOC_PCNOC 15 +-#define SLAVE_QDSS_STM 16 +-#define SLAVE_CATS_0 17 +-#define SLAVE_CATS_1 18 +-#define SLAVE_LPASS 19 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sc7180.h b/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sc7180.h +deleted file mode 100644 +index f9970f6032eb..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sc7180.h ++++ /dev/null +@@ -1,161 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Qualcomm SC7180 interconnect IDs +- * +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SC7180_H +-#define __DT_BINDINGS_INTERCONNECT_QCOM_SC7180_H +- +-#define MASTER_A1NOC_CFG 0 +-#define MASTER_QSPI 1 +-#define MASTER_QUP_0 2 +-#define MASTER_SDCC_2 3 +-#define MASTER_EMMC 4 +-#define MASTER_UFS_MEM 5 +-#define SLAVE_A1NOC_SNOC 6 +-#define SLAVE_SERVICE_A1NOC 7 +- +-#define MASTER_A2NOC_CFG 0 +-#define MASTER_QDSS_BAM 1 +-#define MASTER_QUP_1 2 +-#define MASTER_USB3 3 +-#define MASTER_CRYPTO 4 +-#define MASTER_IPA 5 +-#define MASTER_QDSS_ETR 6 +-#define SLAVE_A2NOC_SNOC 7 +-#define SLAVE_SERVICE_A2NOC 8 +- +-#define MASTER_CAMNOC_HF0_UNCOMP 0 +-#define MASTER_CAMNOC_HF1_UNCOMP 1 +-#define MASTER_CAMNOC_SF_UNCOMP 2 +-#define SLAVE_CAMNOC_UNCOMP 3 +- +-#define MASTER_NPU 0 +-#define MASTER_NPU_PROC 1 +-#define SLAVE_CDSP_GEM_NOC 2 +- +-#define MASTER_SNOC_CNOC 0 +-#define MASTER_QDSS_DAP 1 +-#define SLAVE_A1NOC_CFG 2 +-#define SLAVE_A2NOC_CFG 3 +-#define SLAVE_AHB2PHY_SOUTH 4 +-#define SLAVE_AHB2PHY_CENTER 5 +-#define SLAVE_AOP 6 +-#define SLAVE_AOSS 7 +-#define SLAVE_BOOT_ROM 8 +-#define SLAVE_CAMERA_CFG 9 +-#define SLAVE_CAMERA_NRT_THROTTLE_CFG 10 +-#define SLAVE_CAMERA_RT_THROTTLE_CFG 11 +-#define SLAVE_CLK_CTL 12 +-#define SLAVE_RBCPR_CX_CFG 13 +-#define SLAVE_RBCPR_MX_CFG 14 +-#define SLAVE_CRYPTO_0_CFG 15 +-#define SLAVE_DCC_CFG 16 +-#define SLAVE_CNOC_DDRSS 17 +-#define SLAVE_DISPLAY_CFG 18 +-#define SLAVE_DISPLAY_RT_THROTTLE_CFG 19 +-#define SLAVE_DISPLAY_THROTTLE_CFG 20 +-#define SLAVE_EMMC_CFG 21 +-#define SLAVE_GLM 22 +-#define SLAVE_GFX3D_CFG 23 +-#define SLAVE_IMEM_CFG 24 +-#define SLAVE_IPA_CFG 25 +-#define SLAVE_CNOC_MNOC_CFG 26 +-#define SLAVE_CNOC_MSS 27 +-#define SLAVE_NPU_CFG 28 +-#define SLAVE_NPU_DMA_BWMON_CFG 29 +-#define SLAVE_NPU_PROC_BWMON_CFG 30 +-#define SLAVE_PDM 31 +-#define SLAVE_PIMEM_CFG 32 +-#define SLAVE_PRNG 33 +-#define SLAVE_QDSS_CFG 34 +-#define SLAVE_QM_CFG 35 +-#define SLAVE_QM_MPU_CFG 36 +-#define SLAVE_QSPI_0 37 +-#define SLAVE_QUP_0 38 +-#define SLAVE_QUP_1 39 +-#define SLAVE_SDCC_2 40 +-#define SLAVE_SECURITY 41 +-#define SLAVE_SNOC_CFG 42 +-#define SLAVE_TCSR 43 +-#define SLAVE_TLMM_WEST 44 +-#define SLAVE_TLMM_NORTH 45 +-#define SLAVE_TLMM_SOUTH 46 +-#define SLAVE_UFS_MEM_CFG 47 +-#define SLAVE_USB3 48 +-#define SLAVE_VENUS_CFG 49 +-#define SLAVE_VENUS_THROTTLE_CFG 50 +-#define SLAVE_VSENSE_CTRL_CFG 51 +-#define SLAVE_SERVICE_CNOC 52 +- +-#define MASTER_CNOC_DC_NOC 0 +-#define SLAVE_GEM_NOC_CFG 1 +-#define SLAVE_LLCC_CFG 2 +- +-#define MASTER_APPSS_PROC 0 +-#define MASTER_SYS_TCU 1 +-#define MASTER_GEM_NOC_CFG 2 +-#define MASTER_COMPUTE_NOC 3 +-#define MASTER_MNOC_HF_MEM_NOC 4 +-#define MASTER_MNOC_SF_MEM_NOC 5 +-#define MASTER_SNOC_GC_MEM_NOC 6 +-#define MASTER_SNOC_SF_MEM_NOC 7 +-#define MASTER_GFX3D 8 +-#define SLAVE_MSS_PROC_MS_MPU_CFG 9 +-#define SLAVE_GEM_NOC_SNOC 10 +-#define SLAVE_LLCC 11 +-#define SLAVE_SERVICE_GEM_NOC 12 +- +-#define MASTER_IPA_CORE 0 +-#define SLAVE_IPA_CORE 1 +- +-#define MASTER_LLCC 0 +-#define SLAVE_EBI1 1 +- +-#define MASTER_CNOC_MNOC_CFG 0 +-#define MASTER_CAMNOC_HF0 1 +-#define MASTER_CAMNOC_HF1 2 +-#define MASTER_CAMNOC_SF 3 +-#define MASTER_MDP0 4 +-#define MASTER_ROTATOR 5 +-#define MASTER_VIDEO_P0 6 +-#define MASTER_VIDEO_PROC 7 +-#define SLAVE_MNOC_HF_MEM_NOC 8 +-#define SLAVE_MNOC_SF_MEM_NOC 9 +-#define SLAVE_SERVICE_MNOC 10 +- +-#define MASTER_NPU_SYS 0 +-#define MASTER_NPU_NOC_CFG 1 +-#define SLAVE_NPU_CAL_DP0 2 +-#define SLAVE_NPU_CP 3 +-#define SLAVE_NPU_INT_DMA_BWMON_CFG 4 +-#define SLAVE_NPU_DPM 5 +-#define SLAVE_ISENSE_CFG 6 +-#define SLAVE_NPU_LLM_CFG 7 +-#define SLAVE_NPU_TCM 8 +-#define SLAVE_NPU_COMPUTE_NOC 9 +-#define SLAVE_SERVICE_NPU_NOC 10 +- +-#define MASTER_QUP_CORE_0 0 +-#define MASTER_QUP_CORE_1 1 +-#define SLAVE_QUP_CORE_0 2 +-#define SLAVE_QUP_CORE_1 3 +- +-#define MASTER_SNOC_CFG 0 +-#define MASTER_A1NOC_SNOC 1 +-#define MASTER_A2NOC_SNOC 2 +-#define MASTER_GEM_NOC_SNOC 3 +-#define MASTER_PIMEM 4 +-#define SLAVE_APPSS 5 +-#define SLAVE_SNOC_CNOC 6 +-#define SLAVE_SNOC_GEM_NOC_GC 7 +-#define SLAVE_SNOC_GEM_NOC_SF 8 +-#define SLAVE_IMEM 9 +-#define SLAVE_PIMEM 10 +-#define SLAVE_SERVICE_SNOC 11 +-#define SLAVE_QDSS_STM 12 +-#define SLAVE_TCU 13 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sc7280.h b/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sc7280.h +deleted file mode 100644 +index 21b000443999..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sc7280.h ++++ /dev/null +@@ -1,165 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +-/* +- * Qualcomm SC7280 interconnect IDs +- * +- * Copyright (c) 2021, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SC7280_H +-#define __DT_BINDINGS_INTERCONNECT_QCOM_SC7280_H +- +-#define MASTER_QSPI_0 0 +-#define MASTER_QUP_0 1 +-#define MASTER_QUP_1 2 +-#define MASTER_A1NOC_CFG 3 +-#define MASTER_PCIE_0 4 +-#define MASTER_PCIE_1 5 +-#define MASTER_SDCC_1 6 +-#define MASTER_SDCC_2 7 +-#define MASTER_SDCC_4 8 +-#define MASTER_UFS_MEM 9 +-#define MASTER_USB2 10 +-#define MASTER_USB3_0 11 +-#define SLAVE_A1NOC_SNOC 12 +-#define SLAVE_ANOC_PCIE_GEM_NOC 13 +-#define SLAVE_SERVICE_A1NOC 14 +- +-#define MASTER_QDSS_BAM 0 +-#define MASTER_A2NOC_CFG 1 +-#define MASTER_CNOC_A2NOC 2 +-#define MASTER_CRYPTO 3 +-#define MASTER_IPA 4 +-#define MASTER_QDSS_ETR 5 +-#define SLAVE_A2NOC_SNOC 6 +-#define SLAVE_SERVICE_A2NOC 7 +- +-#define MASTER_QUP_CORE_0 0 +-#define MASTER_QUP_CORE_1 1 +-#define SLAVE_QUP_CORE_0 2 +-#define SLAVE_QUP_CORE_1 3 +- +-#define MASTER_CNOC3_CNOC2 0 +-#define MASTER_QDSS_DAP 1 +-#define SLAVE_AHB2PHY_SOUTH 2 +-#define SLAVE_AHB2PHY_NORTH 3 +-#define SLAVE_CAMERA_CFG 4 +-#define SLAVE_CLK_CTL 5 +-#define SLAVE_CDSP_CFG 6 +-#define SLAVE_RBCPR_CX_CFG 7 +-#define SLAVE_RBCPR_MX_CFG 8 +-#define SLAVE_CRYPTO_0_CFG 9 +-#define SLAVE_CX_RDPM 10 +-#define SLAVE_DCC_CFG 11 +-#define SLAVE_DISPLAY_CFG 12 +-#define SLAVE_GFX3D_CFG 13 +-#define SLAVE_HWKM 14 +-#define SLAVE_IMEM_CFG 15 +-#define SLAVE_IPA_CFG 16 +-#define SLAVE_IPC_ROUTER_CFG 17 +-#define SLAVE_LPASS 18 +-#define SLAVE_CNOC_MSS 19 +-#define SLAVE_MX_RDPM 20 +-#define SLAVE_PCIE_0_CFG 21 +-#define SLAVE_PCIE_1_CFG 22 +-#define SLAVE_PDM 23 +-#define SLAVE_PIMEM_CFG 24 +-#define SLAVE_PKA_WRAPPER_CFG 25 +-#define SLAVE_PMU_WRAPPER_CFG 26 +-#define SLAVE_QDSS_CFG 27 +-#define SLAVE_QSPI_0 28 +-#define SLAVE_QUP_0 29 +-#define SLAVE_QUP_1 30 +-#define SLAVE_SDCC_1 31 +-#define SLAVE_SDCC_2 32 +-#define SLAVE_SDCC_4 33 +-#define SLAVE_SECURITY 34 +-#define SLAVE_TCSR 35 +-#define SLAVE_TLMM 36 +-#define SLAVE_UFS_MEM_CFG 37 +-#define SLAVE_USB2 38 +-#define SLAVE_USB3_0 39 +-#define SLAVE_VENUS_CFG 40 +-#define SLAVE_VSENSE_CTRL_CFG 41 +-#define SLAVE_A1NOC_CFG 42 +-#define SLAVE_A2NOC_CFG 43 +-#define SLAVE_CNOC2_CNOC3 44 +-#define SLAVE_CNOC_MNOC_CFG 45 +-#define SLAVE_SNOC_CFG 46 +- +-#define MASTER_CNOC2_CNOC3 0 +-#define MASTER_GEM_NOC_CNOC 1 +-#define MASTER_GEM_NOC_PCIE_SNOC 2 +-#define SLAVE_AOSS 3 +-#define SLAVE_APPSS 4 +-#define SLAVE_CNOC3_CNOC2 5 +-#define SLAVE_CNOC_A2NOC 6 +-#define SLAVE_DDRSS_CFG 7 +-#define SLAVE_BOOT_IMEM 8 +-#define SLAVE_IMEM 9 +-#define SLAVE_PIMEM 10 +-#define SLAVE_PCIE_0 11 +-#define SLAVE_PCIE_1 12 +-#define SLAVE_QDSS_STM 13 +-#define SLAVE_TCU 14 +- +-#define MASTER_CNOC_DC_NOC 0 +-#define SLAVE_LLCC_CFG 1 +-#define SLAVE_GEM_NOC_CFG 2 +- +-#define MASTER_GPU_TCU 0 +-#define MASTER_SYS_TCU 1 +-#define MASTER_APPSS_PROC 2 +-#define MASTER_COMPUTE_NOC 3 +-#define MASTER_GEM_NOC_CFG 4 +-#define MASTER_GFX3D 5 +-#define MASTER_MNOC_HF_MEM_NOC 6 +-#define MASTER_MNOC_SF_MEM_NOC 7 +-#define MASTER_ANOC_PCIE_GEM_NOC 8 +-#define MASTER_SNOC_GC_MEM_NOC 9 +-#define MASTER_SNOC_SF_MEM_NOC 10 +-#define SLAVE_MSS_PROC_MS_MPU_CFG 11 +-#define SLAVE_MCDMA_MS_MPU_CFG 12 +-#define SLAVE_GEM_NOC_CNOC 13 +-#define SLAVE_LLCC 14 +-#define SLAVE_MEM_NOC_PCIE_SNOC 15 +-#define SLAVE_SERVICE_GEM_NOC_1 16 +-#define SLAVE_SERVICE_GEM_NOC_2 17 +-#define SLAVE_SERVICE_GEM_NOC 18 +- +-#define MASTER_CNOC_LPASS_AG_NOC 0 +-#define SLAVE_LPASS_CORE_CFG 1 +-#define SLAVE_LPASS_LPI_CFG 2 +-#define SLAVE_LPASS_MPU_CFG 3 +-#define SLAVE_LPASS_TOP_CFG 4 +-#define SLAVE_SERVICES_LPASS_AML_NOC 5 +-#define SLAVE_SERVICE_LPASS_AG_NOC 6 +- +-#define MASTER_LLCC 0 +-#define SLAVE_EBI1 1 +- +-#define MASTER_CNOC_MNOC_CFG 0 +-#define MASTER_VIDEO_P0 1 +-#define MASTER_VIDEO_PROC 2 +-#define MASTER_CAMNOC_HF 3 +-#define MASTER_CAMNOC_ICP 4 +-#define MASTER_CAMNOC_SF 5 +-#define MASTER_MDP0 6 +-#define SLAVE_MNOC_HF_MEM_NOC 7 +-#define SLAVE_MNOC_SF_MEM_NOC 8 +-#define SLAVE_SERVICE_MNOC 9 +- +-#define MASTER_CDSP_NOC_CFG 0 +-#define MASTER_CDSP_PROC 1 +-#define SLAVE_CDSP_MEM_NOC 2 +-#define SLAVE_SERVICE_NSP_NOC 3 +- +-#define MASTER_A1NOC_SNOC 0 +-#define MASTER_A2NOC_SNOC 1 +-#define MASTER_SNOC_CFG 2 +-#define MASTER_PIMEM 3 +-#define MASTER_GIC 4 +-#define SLAVE_SNOC_GEM_NOC_GC 5 +-#define SLAVE_SNOC_GEM_NOC_SF 6 +-#define SLAVE_SERVICE_SNOC 7 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sc8180x.h b/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sc8180x.h +deleted file mode 100644 +index 235b525d2803..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sc8180x.h ++++ /dev/null +@@ -1,185 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +-/* +- * Qualcomm SC8180x interconnect IDs +- * +- * Copyright (c) 2021, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SC8180X_H +-#define __DT_BINDINGS_INTERCONNECT_QCOM_SC8180X_H +- +-#define MASTER_A1NOC_CFG 0 +-#define MASTER_UFS_CARD 1 +-#define MASTER_UFS_GEN4 2 +-#define MASTER_UFS_MEM 3 +-#define MASTER_USB3 4 +-#define MASTER_USB3_1 5 +-#define MASTER_USB3_2 6 +-#define A1NOC_SNOC_SLV 7 +-#define SLAVE_SERVICE_A1NOC 8 +- +-#define MASTER_A2NOC_CFG 0 +-#define MASTER_QDSS_BAM 1 +-#define MASTER_QSPI_0 2 +-#define MASTER_QSPI_1 3 +-#define MASTER_QUP_0 4 +-#define MASTER_QUP_1 5 +-#define MASTER_QUP_2 6 +-#define MASTER_SENSORS_AHB 7 +-#define MASTER_CRYPTO_CORE_0 8 +-#define MASTER_IPA 9 +-#define MASTER_EMAC 10 +-#define MASTER_PCIE 11 +-#define MASTER_PCIE_1 12 +-#define MASTER_PCIE_2 13 +-#define MASTER_PCIE_3 14 +-#define MASTER_QDSS_ETR 15 +-#define MASTER_SDCC_2 16 +-#define MASTER_SDCC_4 17 +-#define A2NOC_SNOC_SLV 18 +-#define SLAVE_ANOC_PCIE_GEM_NOC 19 +-#define SLAVE_SERVICE_A2NOC 20 +- +-#define MASTER_CAMNOC_HF0_UNCOMP 0 +-#define MASTER_CAMNOC_HF1_UNCOMP 1 +-#define MASTER_CAMNOC_SF_UNCOMP 2 +-#define SLAVE_CAMNOC_UNCOMP 3 +- +-#define MASTER_NPU 0 +-#define SLAVE_CDSP_MEM_NOC 1 +- +-#define SNOC_CNOC_MAS 0 +-#define SLAVE_A1NOC_CFG 1 +-#define SLAVE_A2NOC_CFG 2 +-#define SLAVE_AHB2PHY_CENTER 3 +-#define SLAVE_AHB2PHY_EAST 4 +-#define SLAVE_AHB2PHY_WEST 5 +-#define SLAVE_AHB2PHY_SOUTH 6 +-#define SLAVE_AOP 7 +-#define SLAVE_AOSS 8 +-#define SLAVE_CAMERA_CFG 9 +-#define SLAVE_CLK_CTL 10 +-#define SLAVE_CDSP_CFG 11 +-#define SLAVE_RBCPR_CX_CFG 12 +-#define SLAVE_RBCPR_MMCX_CFG 13 +-#define SLAVE_RBCPR_MX_CFG 14 +-#define SLAVE_CRYPTO_0_CFG 15 +-#define SLAVE_CNOC_DDRSS 16 +-#define SLAVE_DISPLAY_CFG 17 +-#define SLAVE_EMAC_CFG 18 +-#define SLAVE_GLM 19 +-#define SLAVE_GRAPHICS_3D_CFG 20 +-#define SLAVE_IMEM_CFG 21 +-#define SLAVE_IPA_CFG 22 +-#define SLAVE_CNOC_MNOC_CFG 23 +-#define SLAVE_NPU_CFG 24 +-#define SLAVE_PCIE_0_CFG 25 +-#define SLAVE_PCIE_1_CFG 26 +-#define SLAVE_PCIE_2_CFG 27 +-#define SLAVE_PCIE_3_CFG 28 +-#define SLAVE_PDM 29 +-#define SLAVE_PIMEM_CFG 30 +-#define SLAVE_PRNG 31 +-#define SLAVE_QDSS_CFG 32 +-#define SLAVE_QSPI_0 33 +-#define SLAVE_QSPI_1 34 +-#define SLAVE_QUP_1 35 +-#define SLAVE_QUP_2 36 +-#define SLAVE_QUP_0 37 +-#define SLAVE_SDCC_2 38 +-#define SLAVE_SDCC_4 39 +-#define SLAVE_SECURITY 40 +-#define SLAVE_SNOC_CFG 41 +-#define SLAVE_SPSS_CFG 42 +-#define SLAVE_TCSR 43 +-#define SLAVE_TLMM_EAST 44 +-#define SLAVE_TLMM_SOUTH 45 +-#define SLAVE_TLMM_WEST 46 +-#define SLAVE_TSIF 47 +-#define SLAVE_UFS_CARD_CFG 48 +-#define SLAVE_UFS_MEM_0_CFG 49 +-#define SLAVE_UFS_MEM_1_CFG 50 +-#define SLAVE_USB3 51 +-#define SLAVE_USB3_1 52 +-#define SLAVE_USB3_2 53 +-#define SLAVE_VENUS_CFG 54 +-#define SLAVE_VSENSE_CTRL_CFG 55 +-#define SLAVE_SERVICE_CNOC 56 +- +-#define MASTER_CNOC_DC_NOC 0 +-#define SLAVE_GEM_NOC_CFG 1 +-#define SLAVE_LLCC_CFG 2 +- +-#define MASTER_AMPSS_M0 0 +-#define MASTER_GPU_TCU 1 +-#define MASTER_SYS_TCU 2 +-#define MASTER_GEM_NOC_CFG 3 +-#define MASTER_COMPUTE_NOC 4 +-#define MASTER_GRAPHICS_3D 5 +-#define MASTER_MNOC_HF_MEM_NOC 6 +-#define MASTER_MNOC_SF_MEM_NOC 7 +-#define MASTER_GEM_NOC_PCIE_SNOC 8 +-#define MASTER_SNOC_GC_MEM_NOC 9 +-#define MASTER_SNOC_SF_MEM_NOC 10 +-#define MASTER_ECC 11 +-#define SLAVE_MSS_PROC_MS_MPU_CFG 12 +-#define SLAVE_ECC 13 +-#define SLAVE_GEM_NOC_SNOC 14 +-#define SLAVE_LLCC 15 +-#define SLAVE_SERVICE_GEM_NOC 16 +-#define SLAVE_SERVICE_GEM_NOC_1 17 +- +-#define MASTER_IPA_CORE 0 +-#define SLAVE_IPA_CORE 1 +- +-#define MASTER_LLCC 0 +-#define SLAVE_EBI_CH0 1 +- +-#define MASTER_CNOC_MNOC_CFG 0 +-#define MASTER_CAMNOC_HF0 1 +-#define MASTER_CAMNOC_HF1 2 +-#define MASTER_CAMNOC_SF 3 +-#define MASTER_MDP_PORT0 4 +-#define MASTER_MDP_PORT1 5 +-#define MASTER_ROTATOR 6 +-#define MASTER_VIDEO_P0 7 +-#define MASTER_VIDEO_P1 8 +-#define MASTER_VIDEO_PROC 9 +-#define SLAVE_MNOC_SF_MEM_NOC 10 +-#define SLAVE_MNOC_HF_MEM_NOC 11 +-#define SLAVE_SERVICE_MNOC 12 +- +-#define MASTER_SNOC_CFG 0 +-#define A1NOC_SNOC_MAS 1 +-#define A2NOC_SNOC_MAS 2 +-#define MASTER_GEM_NOC_SNOC 3 +-#define MASTER_PIMEM 4 +-#define MASTER_GIC 5 +-#define SLAVE_APPSS 6 +-#define SNOC_CNOC_SLV 7 +-#define SLAVE_SNOC_GEM_NOC_GC 8 +-#define SLAVE_SNOC_GEM_NOC_SF 9 +-#define SLAVE_OCIMEM 10 +-#define SLAVE_PIMEM 11 +-#define SLAVE_SERVICE_SNOC 12 +-#define SLAVE_PCIE_0 13 +-#define SLAVE_PCIE_1 14 +-#define SLAVE_PCIE_2 15 +-#define SLAVE_PCIE_3 16 +-#define SLAVE_QDSS_STM 17 +-#define SLAVE_TCU 18 +- +-#define MASTER_MNOC_HF_MEM_NOC_DISPLAY 0 +-#define MASTER_MNOC_SF_MEM_NOC_DISPLAY 1 +-#define SLAVE_LLCC_DISPLAY 2 +- +-#define MASTER_LLCC_DISPLAY 0 +-#define SLAVE_EBI_CH0_DISPLAY 1 +- +-#define MASTER_MDP_PORT0_DISPLAY 0 +-#define MASTER_MDP_PORT1_DISPLAY 1 +-#define MASTER_ROTATOR_DISPLAY 2 +-#define SLAVE_MNOC_SF_MEM_NOC_DISPLAY 3 +-#define SLAVE_MNOC_HF_MEM_NOC_DISPLAY 4 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sdm660.h b/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sdm660.h +deleted file mode 100644 +index 62e8d8670d5e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sdm660.h ++++ /dev/null +@@ -1,116 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* SDM660 interconnect IDs */ +- +-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM660_H +-#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM660_H +- +-/* A2NOC */ +-#define MASTER_IPA 0 +-#define MASTER_CNOC_A2NOC 1 +-#define MASTER_SDCC_1 2 +-#define MASTER_SDCC_2 3 +-#define MASTER_BLSP_1 4 +-#define MASTER_BLSP_2 5 +-#define MASTER_UFS 6 +-#define MASTER_USB_HS 7 +-#define MASTER_USB3 8 +-#define MASTER_CRYPTO_C0 9 +-#define SLAVE_A2NOC_SNOC 10 +- +-/* BIMC */ +-#define MASTER_GNOC_BIMC 0 +-#define MASTER_OXILI 1 +-#define MASTER_MNOC_BIMC 2 +-#define MASTER_SNOC_BIMC 3 +-#define MASTER_PIMEM 4 +-#define SLAVE_EBI 5 +-#define SLAVE_HMSS_L3 6 +-#define SLAVE_BIMC_SNOC 7 +- +-/* CNOC */ +-#define MASTER_SNOC_CNOC 0 +-#define MASTER_QDSS_DAP 1 +-#define SLAVE_CNOC_A2NOC 2 +-#define SLAVE_MPM 3 +-#define SLAVE_PMIC_ARB 4 +-#define SLAVE_TLMM_NORTH 5 +-#define SLAVE_TCSR 6 +-#define SLAVE_PIMEM_CFG 7 +-#define SLAVE_IMEM_CFG 8 +-#define SLAVE_MESSAGE_RAM 9 +-#define SLAVE_GLM 10 +-#define SLAVE_BIMC_CFG 11 +-#define SLAVE_PRNG 12 +-#define SLAVE_SPDM 13 +-#define SLAVE_QDSS_CFG 14 +-#define SLAVE_CNOC_MNOC_CFG 15 +-#define SLAVE_SNOC_CFG 16 +-#define SLAVE_QM_CFG 17 +-#define SLAVE_CLK_CTL 18 +-#define SLAVE_MSS_CFG 19 +-#define SLAVE_TLMM_SOUTH 20 +-#define SLAVE_UFS_CFG 21 +-#define SLAVE_A2NOC_CFG 22 +-#define SLAVE_A2NOC_SMMU_CFG 23 +-#define SLAVE_GPUSS_CFG 24 +-#define SLAVE_AHB2PHY 25 +-#define SLAVE_BLSP_1 26 +-#define SLAVE_SDCC_1 27 +-#define SLAVE_SDCC_2 28 +-#define SLAVE_TLMM_CENTER 29 +-#define SLAVE_BLSP_2 30 +-#define SLAVE_PDM 31 +-#define SLAVE_CNOC_MNOC_MMSS_CFG 32 +-#define SLAVE_USB_HS 33 +-#define SLAVE_USB3_0 34 +-#define SLAVE_SRVC_CNOC 35 +- +-/* GNOC */ +-#define MASTER_APSS_PROC 0 +-#define SLAVE_GNOC_BIMC 1 +-#define SLAVE_GNOC_SNOC 2 +- +-/* MNOC */ +-#define MASTER_CPP 0 +-#define MASTER_JPEG 1 +-#define MASTER_MDP_P0 2 +-#define MASTER_MDP_P1 3 +-#define MASTER_VENUS 4 +-#define MASTER_VFE 5 +-#define SLAVE_MNOC_BIMC 6 +-#define MASTER_CNOC_MNOC_MMSS_CFG 7 +-#define MASTER_CNOC_MNOC_CFG 8 +-#define SLAVE_CAMERA_CFG 9 +-#define SLAVE_CAMERA_THROTTLE_CFG 10 +-#define SLAVE_MISC_CFG 11 +-#define SLAVE_VENUS_THROTTLE_CFG 12 +-#define SLAVE_VENUS_CFG 13 +-#define SLAVE_MMSS_CLK_XPU_CFG 14 +-#define SLAVE_MMSS_CLK_CFG 15 +-#define SLAVE_MNOC_MPU_CFG 16 +-#define SLAVE_DISPLAY_CFG 17 +-#define SLAVE_CSI_PHY_CFG 18 +-#define SLAVE_DISPLAY_THROTTLE_CFG 19 +-#define SLAVE_SMMU_CFG 20 +-#define SLAVE_SRVC_MNOC 21 +- +-/* SNOC */ +-#define MASTER_QDSS_ETR 0 +-#define MASTER_QDSS_BAM 1 +-#define MASTER_SNOC_CFG 2 +-#define MASTER_BIMC_SNOC 3 +-#define MASTER_A2NOC_SNOC 4 +-#define MASTER_GNOC_SNOC 5 +-#define SLAVE_HMSS 6 +-#define SLAVE_LPASS 7 +-#define SLAVE_WLAN 8 +-#define SLAVE_CDSP 9 +-#define SLAVE_IPA 10 +-#define SLAVE_SNOC_BIMC 11 +-#define SLAVE_SNOC_CNOC 12 +-#define SLAVE_IMEM 13 +-#define SLAVE_PIMEM 14 +-#define SLAVE_QDSS_STM 15 +-#define SLAVE_SRVC_SNOC 16 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sdm845.h b/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sdm845.h +deleted file mode 100644 +index 67b500e24915..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sdm845.h ++++ /dev/null +@@ -1,150 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Qualcomm SDM845 interconnect IDs +- * +- * Copyright (c) 2018, Linaro Ltd. +- * Author: Georgi Djakov +- */ +- +-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H +-#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H +- +-#define MASTER_A1NOC_CFG 0 +-#define MASTER_TSIF 1 +-#define MASTER_SDCC_2 2 +-#define MASTER_SDCC_4 3 +-#define MASTER_UFS_CARD 4 +-#define MASTER_UFS_MEM 5 +-#define MASTER_PCIE_0 6 +-#define SLAVE_A1NOC_SNOC 7 +-#define SLAVE_SERVICE_A1NOC 8 +-#define SLAVE_ANOC_PCIE_A1NOC_SNOC 9 +-#define MASTER_QUP_1 10 +- +-#define MASTER_A2NOC_CFG 0 +-#define MASTER_QDSS_BAM 1 +-#define MASTER_CNOC_A2NOC 2 +-#define MASTER_CRYPTO 3 +-#define MASTER_IPA 4 +-#define MASTER_PCIE_1 5 +-#define MASTER_QDSS_ETR 6 +-#define MASTER_USB3_0 7 +-#define MASTER_USB3_1 8 +-#define SLAVE_A2NOC_SNOC 9 +-#define SLAVE_ANOC_PCIE_SNOC 10 +-#define SLAVE_SERVICE_A2NOC 11 +-#define MASTER_QUP_2 12 +- +-#define MASTER_SPDM 0 +-#define MASTER_TIC 1 +-#define MASTER_SNOC_CNOC 2 +-#define MASTER_QDSS_DAP 3 +-#define SLAVE_A1NOC_CFG 4 +-#define SLAVE_A2NOC_CFG 5 +-#define SLAVE_AOP 6 +-#define SLAVE_AOSS 7 +-#define SLAVE_CAMERA_CFG 8 +-#define SLAVE_CLK_CTL 9 +-#define SLAVE_CDSP_CFG 10 +-#define SLAVE_RBCPR_CX_CFG 11 +-#define SLAVE_CRYPTO_0_CFG 12 +-#define SLAVE_DCC_CFG 13 +-#define SLAVE_CNOC_DDRSS 14 +-#define SLAVE_DISPLAY_CFG 15 +-#define SLAVE_GLM 16 +-#define SLAVE_GFX3D_CFG 17 +-#define SLAVE_IMEM_CFG 18 +-#define SLAVE_IPA_CFG 19 +-#define SLAVE_CNOC_MNOC_CFG 20 +-#define SLAVE_PCIE_0_CFG 21 +-#define SLAVE_PCIE_1_CFG 22 +-#define SLAVE_PDM 23 +-#define SLAVE_SOUTH_PHY_CFG 24 +-#define SLAVE_PIMEM_CFG 25 +-#define SLAVE_PRNG 26 +-#define SLAVE_QDSS_CFG 27 +-#define SLAVE_BLSP_2 28 +-#define SLAVE_BLSP_1 29 +-#define SLAVE_SDCC_2 30 +-#define SLAVE_SDCC_4 31 +-#define SLAVE_SNOC_CFG 32 +-#define SLAVE_SPDM_WRAPPER 33 +-#define SLAVE_SPSS_CFG 34 +-#define SLAVE_TCSR 35 +-#define SLAVE_TLMM_NORTH 36 +-#define SLAVE_TLMM_SOUTH 37 +-#define SLAVE_TSIF 38 +-#define SLAVE_UFS_CARD_CFG 39 +-#define SLAVE_UFS_MEM_CFG 40 +-#define SLAVE_USB3_0 41 +-#define SLAVE_USB3_1 42 +-#define SLAVE_VENUS_CFG 43 +-#define SLAVE_VSENSE_CTRL_CFG 44 +-#define SLAVE_CNOC_A2NOC 45 +-#define SLAVE_SERVICE_CNOC 46 +- +-#define MASTER_CNOC_DC_NOC 0 +-#define SLAVE_LLCC_CFG 1 +-#define SLAVE_MEM_NOC_CFG 2 +- +-#define MASTER_APPSS_PROC 0 +-#define MASTER_GNOC_CFG 1 +-#define SLAVE_GNOC_SNOC 2 +-#define SLAVE_GNOC_MEM_NOC 3 +-#define SLAVE_SERVICE_GNOC 4 +- +-#define MASTER_TCU_0 0 +-#define MASTER_MEM_NOC_CFG 1 +-#define MASTER_GNOC_MEM_NOC 2 +-#define MASTER_MNOC_HF_MEM_NOC 3 +-#define MASTER_MNOC_SF_MEM_NOC 4 +-#define MASTER_SNOC_GC_MEM_NOC 5 +-#define MASTER_SNOC_SF_MEM_NOC 6 +-#define MASTER_GFX3D 7 +-#define SLAVE_MSS_PROC_MS_MPU_CFG 8 +-#define SLAVE_MEM_NOC_GNOC 9 +-#define SLAVE_LLCC 10 +-#define SLAVE_MEM_NOC_SNOC 11 +-#define SLAVE_SERVICE_MEM_NOC 12 +-#define MASTER_LLCC 13 +-#define SLAVE_EBI1 14 +- +-#define MASTER_CNOC_MNOC_CFG 0 +-#define MASTER_CAMNOC_HF0 1 +-#define MASTER_CAMNOC_HF1 2 +-#define MASTER_CAMNOC_SF 3 +-#define MASTER_MDP0 4 +-#define MASTER_MDP1 5 +-#define MASTER_ROTATOR 6 +-#define MASTER_VIDEO_P0 7 +-#define MASTER_VIDEO_P1 8 +-#define MASTER_VIDEO_PROC 9 +-#define SLAVE_MNOC_SF_MEM_NOC 10 +-#define SLAVE_MNOC_HF_MEM_NOC 11 +-#define SLAVE_SERVICE_MNOC 12 +-#define MASTER_CAMNOC_HF0_UNCOMP 13 +-#define MASTER_CAMNOC_HF1_UNCOMP 14 +-#define MASTER_CAMNOC_SF_UNCOMP 15 +-#define SLAVE_CAMNOC_UNCOMP 16 +- +-#define MASTER_SNOC_CFG 0 +-#define MASTER_A1NOC_SNOC 1 +-#define MASTER_A2NOC_SNOC 2 +-#define MASTER_GNOC_SNOC 3 +-#define MASTER_MEM_NOC_SNOC 4 +-#define MASTER_ANOC_PCIE_SNOC 5 +-#define MASTER_PIMEM 6 +-#define MASTER_GIC 7 +-#define SLAVE_APPSS 8 +-#define SLAVE_SNOC_CNOC 9 +-#define SLAVE_SNOC_MEM_NOC_GC 10 +-#define SLAVE_SNOC_MEM_NOC_SF 11 +-#define SLAVE_IMEM 12 +-#define SLAVE_PCIE_0 13 +-#define SLAVE_PCIE_1 14 +-#define SLAVE_PIMEM 15 +-#define SLAVE_SERVICE_SNOC 16 +-#define SLAVE_QDSS_STM 17 +-#define SLAVE_TCU 18 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sdx55.h b/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sdx55.h +deleted file mode 100644 +index bfb6524a2d90..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sdx55.h ++++ /dev/null +@@ -1,76 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Qualcomm SDX55 interconnect IDs +- * +- * Copyright (c) 2021, Linaro Ltd. +- * Author: Manivannan Sadhasivam +- */ +- +-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX55_H +-#define __DT_BINDINGS_INTERCONNECT_QCOM_SDX55_H +- +-#define MASTER_LLCC 0 +-#define SLAVE_EBI_CH0 1 +- +-#define MASTER_TCU_0 0 +-#define MASTER_SNOC_GC_MEM_NOC 1 +-#define MASTER_AMPSS_M0 2 +-#define SLAVE_LLCC 3 +-#define SLAVE_MEM_NOC_SNOC 4 +-#define SLAVE_MEM_NOC_PCIE_SNOC 5 +- +-#define MASTER_AUDIO 0 +-#define MASTER_BLSP_1 1 +-#define MASTER_QDSS_BAM 2 +-#define MASTER_QPIC 3 +-#define MASTER_SNOC_CFG 4 +-#define MASTER_SPMI_FETCHER 5 +-#define MASTER_ANOC_SNOC 6 +-#define MASTER_IPA 7 +-#define MASTER_MEM_NOC_SNOC 8 +-#define MASTER_MEM_NOC_PCIE_SNOC 9 +-#define MASTER_CRYPTO_CORE_0 10 +-#define MASTER_EMAC 11 +-#define MASTER_IPA_PCIE 12 +-#define MASTER_PCIE 13 +-#define MASTER_QDSS_ETR 14 +-#define MASTER_SDCC_1 15 +-#define MASTER_USB3 16 +-#define SLAVE_AOP 17 +-#define SLAVE_AOSS 18 +-#define SLAVE_APPSS 19 +-#define SLAVE_AUDIO 20 +-#define SLAVE_BLSP_1 21 +-#define SLAVE_CLK_CTL 22 +-#define SLAVE_CRYPTO_0_CFG 23 +-#define SLAVE_CNOC_DDRSS 24 +-#define SLAVE_ECC_CFG 25 +-#define SLAVE_EMAC_CFG 26 +-#define SLAVE_IMEM_CFG 27 +-#define SLAVE_IPA_CFG 28 +-#define SLAVE_CNOC_MSS 29 +-#define SLAVE_PCIE_PARF 30 +-#define SLAVE_PDM 31 +-#define SLAVE_PRNG 32 +-#define SLAVE_QDSS_CFG 33 +-#define SLAVE_QPIC 34 +-#define SLAVE_SDCC_1 35 +-#define SLAVE_SNOC_CFG 36 +-#define SLAVE_SPMI_FETCHER 37 +-#define SLAVE_SPMI_VGI_COEX 38 +-#define SLAVE_TCSR 39 +-#define SLAVE_TLMM 40 +-#define SLAVE_USB3 41 +-#define SLAVE_USB3_PHY_CFG 42 +-#define SLAVE_ANOC_SNOC 43 +-#define SLAVE_SNOC_MEM_NOC_GC 44 +-#define SLAVE_OCIMEM 45 +-#define SLAVE_SERVICE_SNOC 46 +-#define SLAVE_PCIE_0 47 +-#define SLAVE_QDSS_STM 48 +-#define SLAVE_TCU 49 +- +-#define MASTER_IPA_CORE 0 +-#define SLAVE_IPA_CORE 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sm8150.h b/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sm8150.h +deleted file mode 100644 +index a25684680c42..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sm8150.h ++++ /dev/null +@@ -1,162 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Qualcomm SM8150 interconnect IDs +- * +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8150_H +-#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8150_H +- +-#define MASTER_A1NOC_CFG 0 +-#define MASTER_QUP_0 1 +-#define MASTER_EMAC 2 +-#define MASTER_UFS_MEM 3 +-#define MASTER_USB3 4 +-#define MASTER_USB3_1 5 +-#define A1NOC_SNOC_SLV 6 +-#define SLAVE_SERVICE_A1NOC 7 +- +-#define MASTER_A2NOC_CFG 0 +-#define MASTER_QDSS_BAM 1 +-#define MASTER_QSPI 2 +-#define MASTER_QUP_1 3 +-#define MASTER_QUP_2 4 +-#define MASTER_SENSORS_AHB 5 +-#define MASTER_TSIF 6 +-#define MASTER_CNOC_A2NOC 7 +-#define MASTER_CRYPTO_CORE_0 8 +-#define MASTER_IPA 9 +-#define MASTER_PCIE 10 +-#define MASTER_PCIE_1 11 +-#define MASTER_QDSS_ETR 12 +-#define MASTER_SDCC_2 13 +-#define MASTER_SDCC_4 14 +-#define A2NOC_SNOC_SLV 15 +-#define SLAVE_ANOC_PCIE_GEM_NOC 16 +-#define SLAVE_SERVICE_A2NOC 17 +- +-#define MASTER_CAMNOC_HF0_UNCOMP 0 +-#define MASTER_CAMNOC_HF1_UNCOMP 1 +-#define MASTER_CAMNOC_SF_UNCOMP 2 +-#define SLAVE_CAMNOC_UNCOMP 3 +- +-#define MASTER_NPU 0 +-#define SLAVE_CDSP_MEM_NOC 1 +- +-#define MASTER_SPDM 0 +-#define SNOC_CNOC_MAS 1 +-#define MASTER_QDSS_DAP 2 +-#define SLAVE_A1NOC_CFG 3 +-#define SLAVE_A2NOC_CFG 4 +-#define SLAVE_AHB2PHY_SOUTH 5 +-#define SLAVE_AOP 6 +-#define SLAVE_AOSS 7 +-#define SLAVE_CAMERA_CFG 8 +-#define SLAVE_CLK_CTL 9 +-#define SLAVE_CDSP_CFG 10 +-#define SLAVE_RBCPR_CX_CFG 11 +-#define SLAVE_RBCPR_MMCX_CFG 12 +-#define SLAVE_RBCPR_MX_CFG 13 +-#define SLAVE_CRYPTO_0_CFG 14 +-#define SLAVE_CNOC_DDRSS 15 +-#define SLAVE_DISPLAY_CFG 16 +-#define SLAVE_EMAC_CFG 17 +-#define SLAVE_GLM 18 +-#define SLAVE_GRAPHICS_3D_CFG 19 +-#define SLAVE_IMEM_CFG 20 +-#define SLAVE_IPA_CFG 21 +-#define SLAVE_CNOC_MNOC_CFG 22 +-#define SLAVE_NPU_CFG 23 +-#define SLAVE_PCIE_0_CFG 24 +-#define SLAVE_PCIE_1_CFG 25 +-#define SLAVE_NORTH_PHY_CFG 26 +-#define SLAVE_PIMEM_CFG 27 +-#define SLAVE_PRNG 28 +-#define SLAVE_QDSS_CFG 29 +-#define SLAVE_QSPI 30 +-#define SLAVE_QUP_2 31 +-#define SLAVE_QUP_1 32 +-#define SLAVE_QUP_0 33 +-#define SLAVE_SDCC_2 34 +-#define SLAVE_SDCC_4 35 +-#define SLAVE_SNOC_CFG 36 +-#define SLAVE_SPDM_WRAPPER 37 +-#define SLAVE_SPSS_CFG 38 +-#define SLAVE_SSC_CFG 39 +-#define SLAVE_TCSR 40 +-#define SLAVE_TLMM_EAST 41 +-#define SLAVE_TLMM_NORTH 42 +-#define SLAVE_TLMM_SOUTH 43 +-#define SLAVE_TLMM_WEST 44 +-#define SLAVE_TSIF 45 +-#define SLAVE_UFS_CARD_CFG 46 +-#define SLAVE_UFS_MEM_CFG 47 +-#define SLAVE_USB3 48 +-#define SLAVE_USB3_1 49 +-#define SLAVE_VENUS_CFG 50 +-#define SLAVE_VSENSE_CTRL_CFG 51 +-#define SLAVE_CNOC_A2NOC 52 +-#define SLAVE_SERVICE_CNOC 53 +- +-#define MASTER_CNOC_DC_NOC 0 +-#define SLAVE_LLCC_CFG 1 +-#define SLAVE_GEM_NOC_CFG 2 +- +-#define MASTER_AMPSS_M0 0 +-#define MASTER_GPU_TCU 1 +-#define MASTER_SYS_TCU 2 +-#define MASTER_GEM_NOC_CFG 3 +-#define MASTER_COMPUTE_NOC 4 +-#define MASTER_GRAPHICS_3D 5 +-#define MASTER_MNOC_HF_MEM_NOC 6 +-#define MASTER_MNOC_SF_MEM_NOC 7 +-#define MASTER_GEM_NOC_PCIE_SNOC 8 +-#define MASTER_SNOC_GC_MEM_NOC 9 +-#define MASTER_SNOC_SF_MEM_NOC 10 +-#define MASTER_ECC 11 +-#define SLAVE_MSS_PROC_MS_MPU_CFG 12 +-#define SLAVE_ECC 13 +-#define SLAVE_GEM_NOC_SNOC 14 +-#define SLAVE_LLCC 15 +-#define SLAVE_SERVICE_GEM_NOC 16 +- +-#define MASTER_IPA_CORE 0 +-#define SLAVE_IPA_CORE 1 +- +-#define MASTER_LLCC 0 +-#define SLAVE_EBI_CH0 1 +- +-#define MASTER_CNOC_MNOC_CFG 0 +-#define MASTER_CAMNOC_HF0 1 +-#define MASTER_CAMNOC_HF1 2 +-#define MASTER_CAMNOC_SF 3 +-#define MASTER_MDP_PORT0 4 +-#define MASTER_MDP_PORT1 5 +-#define MASTER_ROTATOR 6 +-#define MASTER_VIDEO_P0 7 +-#define MASTER_VIDEO_P1 8 +-#define MASTER_VIDEO_PROC 9 +-#define SLAVE_MNOC_SF_MEM_NOC 10 +-#define SLAVE_MNOC_HF_MEM_NOC 11 +-#define SLAVE_SERVICE_MNOC 12 +- +-#define MASTER_SNOC_CFG 0 +-#define A1NOC_SNOC_MAS 1 +-#define A2NOC_SNOC_MAS 2 +-#define MASTER_GEM_NOC_SNOC 3 +-#define MASTER_PIMEM 4 +-#define MASTER_GIC 5 +-#define SLAVE_APPSS 6 +-#define SNOC_CNOC_SLV 7 +-#define SLAVE_SNOC_GEM_NOC_GC 8 +-#define SLAVE_SNOC_GEM_NOC_SF 9 +-#define SLAVE_OCIMEM 10 +-#define SLAVE_PIMEM 11 +-#define SLAVE_SERVICE_SNOC 12 +-#define SLAVE_PCIE_0 13 +-#define SLAVE_PCIE_1 14 +-#define SLAVE_QDSS_STM 15 +-#define SLAVE_TCU 16 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sm8250.h b/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sm8250.h +deleted file mode 100644 +index 1b4d9fbe888d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sm8250.h ++++ /dev/null +@@ -1,172 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Qualcomm SM8250 interconnect IDs +- * +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8250_H +-#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8250_H +- +-#define MASTER_A1NOC_CFG 0 +-#define MASTER_QSPI_0 1 +-#define MASTER_QUP_1 2 +-#define MASTER_QUP_2 3 +-#define MASTER_TSIF 4 +-#define MASTER_PCIE_2 5 +-#define MASTER_SDCC_4 6 +-#define MASTER_UFS_MEM 7 +-#define MASTER_USB3 8 +-#define MASTER_USB3_1 9 +-#define A1NOC_SNOC_SLV 10 +-#define SLAVE_ANOC_PCIE_GEM_NOC_1 11 +-#define SLAVE_SERVICE_A1NOC 12 +- +-#define MASTER_A2NOC_CFG 0 +-#define MASTER_QDSS_BAM 1 +-#define MASTER_QUP_0 2 +-#define MASTER_CNOC_A2NOC 3 +-#define MASTER_CRYPTO_CORE_0 4 +-#define MASTER_IPA 5 +-#define MASTER_PCIE 6 +-#define MASTER_PCIE_1 7 +-#define MASTER_QDSS_ETR 8 +-#define MASTER_SDCC_2 9 +-#define MASTER_UFS_CARD 10 +-#define A2NOC_SNOC_SLV 11 +-#define SLAVE_ANOC_PCIE_GEM_NOC 12 +-#define SLAVE_SERVICE_A2NOC 13 +- +-#define MASTER_NPU 0 +-#define SLAVE_CDSP_MEM_NOC 1 +- +-#define SNOC_CNOC_MAS 0 +-#define MASTER_QDSS_DAP 1 +-#define SLAVE_A1NOC_CFG 2 +-#define SLAVE_A2NOC_CFG 3 +-#define SLAVE_AHB2PHY_SOUTH 4 +-#define SLAVE_AHB2PHY_NORTH 5 +-#define SLAVE_AOSS 6 +-#define SLAVE_CAMERA_CFG 7 +-#define SLAVE_CLK_CTL 8 +-#define SLAVE_CDSP_CFG 9 +-#define SLAVE_RBCPR_CX_CFG 10 +-#define SLAVE_RBCPR_MMCX_CFG 11 +-#define SLAVE_RBCPR_MX_CFG 12 +-#define SLAVE_CRYPTO_0_CFG 13 +-#define SLAVE_CX_RDPM 14 +-#define SLAVE_DCC_CFG 15 +-#define SLAVE_CNOC_DDRSS 16 +-#define SLAVE_DISPLAY_CFG 17 +-#define SLAVE_GRAPHICS_3D_CFG 18 +-#define SLAVE_IMEM_CFG 19 +-#define SLAVE_IPA_CFG 20 +-#define SLAVE_IPC_ROUTER_CFG 21 +-#define SLAVE_LPASS 22 +-#define SLAVE_CNOC_MNOC_CFG 23 +-#define SLAVE_NPU_CFG 24 +-#define SLAVE_PCIE_0_CFG 25 +-#define SLAVE_PCIE_1_CFG 26 +-#define SLAVE_PCIE_2_CFG 27 +-#define SLAVE_PDM 28 +-#define SLAVE_PIMEM_CFG 29 +-#define SLAVE_PRNG 30 +-#define SLAVE_QDSS_CFG 31 +-#define SLAVE_QSPI_0 32 +-#define SLAVE_QUP_0 33 +-#define SLAVE_QUP_1 34 +-#define SLAVE_QUP_2 35 +-#define SLAVE_SDCC_2 36 +-#define SLAVE_SDCC_4 37 +-#define SLAVE_SNOC_CFG 38 +-#define SLAVE_TCSR 39 +-#define SLAVE_TLMM_NORTH 40 +-#define SLAVE_TLMM_SOUTH 41 +-#define SLAVE_TLMM_WEST 42 +-#define SLAVE_TSIF 43 +-#define SLAVE_UFS_CARD_CFG 44 +-#define SLAVE_UFS_MEM_CFG 45 +-#define SLAVE_USB3 46 +-#define SLAVE_USB3_1 47 +-#define SLAVE_VENUS_CFG 48 +-#define SLAVE_VSENSE_CTRL_CFG 49 +-#define SLAVE_CNOC_A2NOC 50 +-#define SLAVE_SERVICE_CNOC 51 +- +-#define MASTER_CNOC_DC_NOC 0 +-#define SLAVE_LLCC_CFG 1 +-#define SLAVE_GEM_NOC_CFG 2 +- +-#define MASTER_GPU_TCU 0 +-#define MASTER_SYS_TCU 1 +-#define MASTER_AMPSS_M0 2 +-#define MASTER_GEM_NOC_CFG 3 +-#define MASTER_COMPUTE_NOC 4 +-#define MASTER_GRAPHICS_3D 5 +-#define MASTER_MNOC_HF_MEM_NOC 6 +-#define MASTER_MNOC_SF_MEM_NOC 7 +-#define MASTER_ANOC_PCIE_GEM_NOC 8 +-#define MASTER_SNOC_GC_MEM_NOC 9 +-#define MASTER_SNOC_SF_MEM_NOC 10 +-#define SLAVE_GEM_NOC_SNOC 11 +-#define SLAVE_LLCC 12 +-#define SLAVE_MEM_NOC_PCIE_SNOC 13 +-#define SLAVE_SERVICE_GEM_NOC_1 14 +-#define SLAVE_SERVICE_GEM_NOC_2 15 +-#define SLAVE_SERVICE_GEM_NOC 16 +- +-#define MASTER_IPA_CORE 0 +-#define SLAVE_IPA_CORE 1 +- +-#define MASTER_LLCC 0 +-#define SLAVE_EBI_CH0 1 +- +-#define MASTER_CNOC_MNOC_CFG 0 +-#define MASTER_CAMNOC_HF 1 +-#define MASTER_CAMNOC_ICP 2 +-#define MASTER_CAMNOC_SF 3 +-#define MASTER_VIDEO_P0 4 +-#define MASTER_VIDEO_P1 5 +-#define MASTER_VIDEO_PROC 6 +-#define MASTER_MDP_PORT0 7 +-#define MASTER_MDP_PORT1 8 +-#define MASTER_ROTATOR 9 +-#define SLAVE_MNOC_HF_MEM_NOC 10 +-#define SLAVE_MNOC_SF_MEM_NOC 11 +-#define SLAVE_SERVICE_MNOC 12 +- +-#define MASTER_NPU_SYS 0 +-#define MASTER_NPU_CDP 1 +-#define MASTER_NPU_NOC_CFG 2 +-#define SLAVE_NPU_CAL_DP0 3 +-#define SLAVE_NPU_CAL_DP1 4 +-#define SLAVE_NPU_CP 5 +-#define SLAVE_NPU_INT_DMA_BWMON_CFG 6 +-#define SLAVE_NPU_DPM 7 +-#define SLAVE_ISENSE_CFG 8 +-#define SLAVE_NPU_LLM_CFG 9 +-#define SLAVE_NPU_TCM 10 +-#define SLAVE_NPU_COMPUTE_NOC 11 +-#define SLAVE_SERVICE_NPU_NOC 12 +- +-#define MASTER_SNOC_CFG 0 +-#define A1NOC_SNOC_MAS 1 +-#define A2NOC_SNOC_MAS 2 +-#define MASTER_GEM_NOC_SNOC 3 +-#define MASTER_GEM_NOC_PCIE_SNOC 4 +-#define MASTER_PIMEM 5 +-#define MASTER_GIC 6 +-#define SLAVE_APPSS 7 +-#define SNOC_CNOC_SLV 8 +-#define SLAVE_SNOC_GEM_NOC_GC 9 +-#define SLAVE_SNOC_GEM_NOC_SF 10 +-#define SLAVE_OCIMEM 11 +-#define SLAVE_PIMEM 12 +-#define SLAVE_SERVICE_SNOC 13 +-#define SLAVE_PCIE_0 14 +-#define SLAVE_PCIE_1 15 +-#define SLAVE_PCIE_2 16 +-#define SLAVE_QDSS_STM 17 +-#define SLAVE_TCU 18 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sm8350.h b/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sm8350.h +deleted file mode 100644 +index c7f7ed315aeb..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,sm8350.h ++++ /dev/null +@@ -1,172 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +-/* +- * Qualcomm SM8350 interconnect IDs +- * +- * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. +- * Copyright (c) 2021, Linaro Limited +- */ +- +-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8350_H +-#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8350_H +- +-#define MASTER_QSPI_0 0 +-#define MASTER_QUP_1 1 +-#define MASTER_A1NOC_CFG 2 +-#define MASTER_SDCC_4 3 +-#define MASTER_UFS_MEM 4 +-#define MASTER_USB3_0 5 +-#define MASTER_USB3_1 6 +-#define SLAVE_A1NOC_SNOC 7 +-#define SLAVE_SERVICE_A1NOC 8 +- +-#define MASTER_QDSS_BAM 0 +-#define MASTER_QUP_0 1 +-#define MASTER_QUP_2 2 +-#define MASTER_A2NOC_CFG 3 +-#define MASTER_CRYPTO 4 +-#define MASTER_IPA 5 +-#define MASTER_PCIE_0 6 +-#define MASTER_PCIE_1 7 +-#define MASTER_QDSS_ETR 8 +-#define MASTER_SDCC_2 9 +-#define MASTER_UFS_CARD 10 +-#define SLAVE_A2NOC_SNOC 11 +-#define SLAVE_ANOC_PCIE_GEM_NOC 12 +-#define SLAVE_SERVICE_A2NOC 13 +- +-#define MASTER_GEM_NOC_CNOC 0 +-#define MASTER_GEM_NOC_PCIE_SNOC 1 +-#define MASTER_QDSS_DAP 2 +-#define SLAVE_AHB2PHY_SOUTH 3 +-#define SLAVE_AHB2PHY_NORTH 4 +-#define SLAVE_AOSS 5 +-#define SLAVE_APPSS 6 +-#define SLAVE_CAMERA_CFG 7 +-#define SLAVE_CLK_CTL 8 +-#define SLAVE_CDSP_CFG 9 +-#define SLAVE_RBCPR_CX_CFG 10 +-#define SLAVE_RBCPR_MMCX_CFG 11 +-#define SLAVE_RBCPR_MX_CFG 12 +-#define SLAVE_CRYPTO_0_CFG 13 +-#define SLAVE_CX_RDPM 14 +-#define SLAVE_DCC_CFG 15 +-#define SLAVE_DISPLAY_CFG 16 +-#define SLAVE_GFX3D_CFG 17 +-#define SLAVE_HWKM 18 +-#define SLAVE_IMEM_CFG 19 +-#define SLAVE_IPA_CFG 20 +-#define SLAVE_IPC_ROUTER_CFG 21 +-#define SLAVE_LPASS 22 +-#define SLAVE_CNOC_MSS 23 +-#define SLAVE_MX_RDPM 24 +-#define SLAVE_PCIE_0_CFG 25 +-#define SLAVE_PCIE_1_CFG 26 +-#define SLAVE_PDM 27 +-#define SLAVE_PIMEM_CFG 28 +-#define SLAVE_PKA_WRAPPER_CFG 29 +-#define SLAVE_PMU_WRAPPER_CFG 30 +-#define SLAVE_QDSS_CFG 31 +-#define SLAVE_QSPI_0 32 +-#define SLAVE_QUP_0 33 +-#define SLAVE_QUP_1 34 +-#define SLAVE_QUP_2 35 +-#define SLAVE_SDCC_2 36 +-#define SLAVE_SDCC_4 37 +-#define SLAVE_SECURITY 38 +-#define SLAVE_SPSS_CFG 39 +-#define SLAVE_TCSR 40 +-#define SLAVE_TLMM 41 +-#define SLAVE_UFS_CARD_CFG 42 +-#define SLAVE_UFS_MEM_CFG 43 +-#define SLAVE_USB3_0 44 +-#define SLAVE_USB3_1 45 +-#define SLAVE_VENUS_CFG 46 +-#define SLAVE_VSENSE_CTRL_CFG 47 +-#define SLAVE_A1NOC_CFG 48 +-#define SLAVE_A2NOC_CFG 49 +-#define SLAVE_DDRSS_CFG 50 +-#define SLAVE_CNOC_MNOC_CFG 51 +-#define SLAVE_SNOC_CFG 52 +-#define SLAVE_BOOT_IMEM 53 +-#define SLAVE_IMEM 54 +-#define SLAVE_PIMEM 55 +-#define SLAVE_SERVICE_CNOC 56 +-#define SLAVE_PCIE_0 57 +-#define SLAVE_PCIE_1 58 +-#define SLAVE_QDSS_STM 59 +-#define SLAVE_TCU 60 +- +-#define MASTER_CNOC_DC_NOC 0 +-#define SLAVE_LLCC_CFG 1 +-#define SLAVE_GEM_NOC_CFG 2 +- +-#define MASTER_GPU_TCU 0 +-#define MASTER_SYS_TCU 1 +-#define MASTER_APPSS_PROC 2 +-#define MASTER_COMPUTE_NOC 3 +-#define MASTER_GEM_NOC_CFG 4 +-#define MASTER_GFX3D 5 +-#define MASTER_MNOC_HF_MEM_NOC 6 +-#define MASTER_MNOC_SF_MEM_NOC 7 +-#define MASTER_ANOC_PCIE_GEM_NOC 8 +-#define MASTER_SNOC_GC_MEM_NOC 9 +-#define MASTER_SNOC_SF_MEM_NOC 10 +-#define SLAVE_MSS_PROC_MS_MPU_CFG 11 +-#define SLAVE_MCDMA_MS_MPU_CFG 12 +-#define SLAVE_GEM_NOC_CNOC 13 +-#define SLAVE_LLCC 14 +-#define SLAVE_MEM_NOC_PCIE_SNOC 15 +-#define SLAVE_SERVICE_GEM_NOC_1 16 +-#define SLAVE_SERVICE_GEM_NOC_2 17 +-#define SLAVE_SERVICE_GEM_NOC 18 +-#define MASTER_MNOC_HF_MEM_NOC_DISP 19 +-#define MASTER_MNOC_SF_MEM_NOC_DISP 20 +-#define SLAVE_LLCC_DISP 21 +- +-#define MASTER_CNOC_LPASS_AG_NOC 0 +-#define SLAVE_LPASS_CORE_CFG 1 +-#define SLAVE_LPASS_LPI_CFG 2 +-#define SLAVE_LPASS_MPU_CFG 3 +-#define SLAVE_LPASS_TOP_CFG 4 +-#define SLAVE_SERVICES_LPASS_AML_NOC 5 +-#define SLAVE_SERVICE_LPASS_AG_NOC 6 +- +-#define MASTER_LLCC 0 +-#define SLAVE_EBI1 1 +-#define MASTER_LLCC_DISP 2 +-#define SLAVE_EBI1_DISP 3 +- +-#define MASTER_CAMNOC_HF 0 +-#define MASTER_CAMNOC_ICP 1 +-#define MASTER_CAMNOC_SF 2 +-#define MASTER_CNOC_MNOC_CFG 3 +-#define MASTER_VIDEO_P0 4 +-#define MASTER_VIDEO_P1 5 +-#define MASTER_VIDEO_PROC 6 +-#define MASTER_MDP0 7 +-#define MASTER_MDP1 8 +-#define MASTER_ROTATOR 9 +-#define SLAVE_MNOC_HF_MEM_NOC 10 +-#define SLAVE_MNOC_SF_MEM_NOC 11 +-#define SLAVE_SERVICE_MNOC 12 +-#define MASTER_MDP0_DISP 13 +-#define MASTER_MDP1_DISP 14 +-#define MASTER_ROTATOR_DISP 15 +-#define SLAVE_MNOC_HF_MEM_NOC_DISP 16 +-#define SLAVE_MNOC_SF_MEM_NOC_DISP 17 +- +-#define MASTER_CDSP_NOC_CFG 0 +-#define MASTER_CDSP_PROC 1 +-#define SLAVE_CDSP_MEM_NOC 2 +-#define SLAVE_SERVICE_NSP_NOC 3 +- +-#define MASTER_A1NOC_SNOC 0 +-#define MASTER_A2NOC_SNOC 1 +-#define MASTER_SNOC_CFG 2 +-#define MASTER_PIMEM 3 +-#define MASTER_GIC 4 +-#define SLAVE_SNOC_GEM_NOC_GC 5 +-#define SLAVE_SNOC_GEM_NOC_SF 6 +-#define SLAVE_SERVICE_SNOC 7 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/apple-aic.h b/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/apple-aic.h +deleted file mode 100644 +index 604f2bb30ac0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/apple-aic.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ +-#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_APPLE_AIC_H +-#define _DT_BINDINGS_INTERRUPT_CONTROLLER_APPLE_AIC_H +- +-#include +- +-#define AIC_IRQ 0 +-#define AIC_FIQ 1 +- +-#define AIC_TMR_HV_PHYS 0 +-#define AIC_TMR_HV_VIRT 1 +-#define AIC_TMR_GUEST_PHYS 2 +-#define AIC_TMR_GUEST_VIRT 3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h b/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h +deleted file mode 100644 +index 35b6f69b7db6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +-/* +- * This header provides constants for the ARM GIC. +- */ +- +-#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H +-#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H +- +-#include +- +-/* interrupt specifier cell 0 */ +- +-#define GIC_SPI 0 +-#define GIC_PPI 1 +- +-/* +- * Interrupt specifier cell 2. +- * The flags in irq.h are valid, plus those below. +- */ +-#define GIC_CPU_MASK_RAW(x) ((x) << 8) +-#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/aspeed-scu-ic.h b/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/aspeed-scu-ic.h +deleted file mode 100644 +index f315d5a7f5ee..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/aspeed-scu-ic.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ +-#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ +- +-#define ASPEED_SCU_IC_VGA_CURSOR_CHANGE 0 +-#define ASPEED_SCU_IC_VGA_SCRATCH_REG_CHANGE 1 +- +-#define ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI 2 +-#define ASPEED_AST2500_SCU_IC_PCIE_RESET_HI_TO_LO 3 +-#define ASPEED_AST2500_SCU_IC_LPC_RESET_LO_TO_HI 4 +-#define ASPEED_AST2500_SCU_IC_LPC_RESET_HI_TO_LO 5 +-#define ASPEED_AST2500_SCU_IC_ISSUE_MSI 6 +- +-#define ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI 2 +-#define ASPEED_AST2600_SCU_IC0_PCIE_PERST_HI_TO_LO 3 +-#define ASPEED_AST2600_SCU_IC0_PCIE_RCRST_LO_TO_HI 4 +-#define ASPEED_AST2600_SCU_IC0_PCIE_RCRST_HI_TO_LO 5 +- +-#define ASPEED_AST2600_SCU_IC1_LPC_RESET_LO_TO_HI 0 +-#define ASPEED_AST2600_SCU_IC1_LPC_RESET_HI_TO_LO 1 +- +-#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq-st.h b/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq-st.h +deleted file mode 100644 +index 9c9c8e2b808a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq-st.h ++++ /dev/null +@@ -1,27 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * include/linux/irqchip/irq-st.h +- * +- * Copyright (C) 2014 STMicroelectronics – All Rights Reserved +- * +- * Author: Lee Jones +- */ +- +-#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H +-#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H +- +-#define ST_IRQ_SYSCFG_EXT_0 0 +-#define ST_IRQ_SYSCFG_EXT_1 1 +-#define ST_IRQ_SYSCFG_EXT_2 2 +-#define ST_IRQ_SYSCFG_CTI_0 3 +-#define ST_IRQ_SYSCFG_CTI_1 4 +-#define ST_IRQ_SYSCFG_PMU_0 5 +-#define ST_IRQ_SYSCFG_PMU_1 6 +-#define ST_IRQ_SYSCFG_pl310_L2 7 +-#define ST_IRQ_SYSCFG_DISABLED 0xFFFFFFFF +- +-#define ST_IRQ_SYSCFG_EXT_1_INV 0x1 +-#define ST_IRQ_SYSCFG_EXT_2_INV 0x2 +-#define ST_IRQ_SYSCFG_EXT_3_INV 0x4 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq.h b/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq.h +deleted file mode 100644 +index 9e3d183e1381..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq.h ++++ /dev/null +@@ -1,20 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +-/* +- * This header provides constants for most IRQ bindings. +- * +- * Most IRQ bindings include a flags cell as part of the IRQ specifier. +- * In most cases, the format of the flags cell uses the standard values +- * defined in this header. +- */ +- +-#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H +-#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H +- +-#define IRQ_TYPE_NONE 0 +-#define IRQ_TYPE_EDGE_RISING 1 +-#define IRQ_TYPE_EDGE_FALLING 2 +-#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) +-#define IRQ_TYPE_LEVEL_HIGH 4 +-#define IRQ_TYPE_LEVEL_LOW 8 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/mips-gic.h b/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/mips-gic.h +deleted file mode 100644 +index bd45cee0c3f0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/mips-gic.h ++++ /dev/null +@@ -1,10 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H +-#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H +- +-#include +- +-#define GIC_SHARED 0 +-#define GIC_LOCAL 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/mvebu-icu.h b/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/mvebu-icu.h +deleted file mode 100644 +index bb5217c64206..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/mvebu-icu.h ++++ /dev/null +@@ -1,16 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for the MVEBU ICU driver. +- */ +- +-#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H +-#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H +- +-/* interrupt specifier cell 0 */ +- +-#define ICU_GRP_NSR 0x0 +-#define ICU_GRP_SR 0x1 +-#define ICU_GRP_SEI 0x4 +-#define ICU_GRP_REI 0x5 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/leds/common.h b/scripts/dtc/include-prefixes/dt-bindings/leds/common.h +deleted file mode 100644 +index 52b619d44ba2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/leds/common.h ++++ /dev/null +@@ -1,94 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides macros for the common LEDs device tree bindings. +- * +- * Copyright (C) 2015, Samsung Electronics Co., Ltd. +- * Author: Jacek Anaszewski +- * +- * Copyright (C) 2019 Jacek Anaszewski +- * Copyright (C) 2020 Pavel Machek +- */ +- +-#ifndef __DT_BINDINGS_LEDS_H +-#define __DT_BINDINGS_LEDS_H +- +-/* External trigger type */ +-#define LEDS_TRIG_TYPE_EDGE 0 +-#define LEDS_TRIG_TYPE_LEVEL 1 +- +-/* Boost modes */ +-#define LEDS_BOOST_OFF 0 +-#define LEDS_BOOST_ADAPTIVE 1 +-#define LEDS_BOOST_FIXED 2 +- +-/* Standard LED colors */ +-#define LED_COLOR_ID_WHITE 0 +-#define LED_COLOR_ID_RED 1 +-#define LED_COLOR_ID_GREEN 2 +-#define LED_COLOR_ID_BLUE 3 +-#define LED_COLOR_ID_AMBER 4 +-#define LED_COLOR_ID_VIOLET 5 +-#define LED_COLOR_ID_YELLOW 6 +-#define LED_COLOR_ID_IR 7 +-#define LED_COLOR_ID_MULTI 8 /* For multicolor LEDs */ +-#define LED_COLOR_ID_RGB 9 /* For multicolor LEDs that can do arbitrary color, +- so this would include RGBW and similar */ +-#define LED_COLOR_ID_MAX 10 +- +-/* Standard LED functions */ +-/* Keyboard LEDs, usually it would be input4::capslock etc. */ +-/* Obsolete equivalent: "shift-key-light" */ +-#define LED_FUNCTION_CAPSLOCK "capslock" +-#define LED_FUNCTION_SCROLLLOCK "scrolllock" +-#define LED_FUNCTION_NUMLOCK "numlock" +-/* Obsolete equivalents: "tpacpi::thinklight" (IBM/Lenovo Thinkpads), +- "lp5523:kb{1,2,3,4,5,6}" (Nokia N900) */ +-#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight" +- +-/* System LEDs, usually found on system body. +- platform::mute (etc) is sometimes seen, :mute would be better */ +-#define LED_FUNCTION_POWER "power" +-#define LED_FUNCTION_DISK "disk" +- +-/* Obsolete: "platform:*:charging" (allwinner sun50i) */ +-#define LED_FUNCTION_CHARGING "charging" +-/* Used RGB notification LEDs common on phones. +- Obsolete equivalents: "status-led:{red,green,blue}" (Motorola Droid 4), +- "lp5523:{r,g,b}" (Nokia N900) */ +-#define LED_FUNCTION_STATUS "status" +- +-#define LED_FUNCTION_MICMUTE "micmute" +-#define LED_FUNCTION_MUTE "mute" +- +-/* Miscelleaus functions. Use functions above if you can. */ +-#define LED_FUNCTION_ACTIVITY "activity" +-#define LED_FUNCTION_ALARM "alarm" +-#define LED_FUNCTION_BACKLIGHT "backlight" +-#define LED_FUNCTION_BLUETOOTH "bluetooth" +-#define LED_FUNCTION_BOOT "boot" +-#define LED_FUNCTION_CPU "cpu" +-#define LED_FUNCTION_DEBUG "debug" +-#define LED_FUNCTION_DISK_ACTIVITY "disk-activity" +-#define LED_FUNCTION_DISK_ERR "disk-err" +-#define LED_FUNCTION_DISK_READ "disk-read" +-#define LED_FUNCTION_DISK_WRITE "disk-write" +-#define LED_FUNCTION_FAULT "fault" +-#define LED_FUNCTION_FLASH "flash" +-#define LED_FUNCTION_HEARTBEAT "heartbeat" +-#define LED_FUNCTION_INDICATOR "indicator" +-#define LED_FUNCTION_LAN "lan" +-#define LED_FUNCTION_MAIL "mail" +-#define LED_FUNCTION_MTD "mtd" +-#define LED_FUNCTION_PANIC "panic" +-#define LED_FUNCTION_PROGRAMMING "programming" +-#define LED_FUNCTION_RX "rx" +-#define LED_FUNCTION_SD "sd" +-#define LED_FUNCTION_STANDBY "standby" +-#define LED_FUNCTION_TORCH "torch" +-#define LED_FUNCTION_TX "tx" +-#define LED_FUNCTION_USB "usb" +-#define LED_FUNCTION_WAN "wan" +-#define LED_FUNCTION_WLAN "wlan" +-#define LED_FUNCTION_WPS "wps" +- +-#endif /* __DT_BINDINGS_LEDS_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/leds/leds-netxbig.h b/scripts/dtc/include-prefixes/dt-bindings/leds/leds-netxbig.h +deleted file mode 100644 +index 92658b0310b2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/leds/leds-netxbig.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-/* +- * This header provides constants for netxbig LED bindings. +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without any +- * warranty of any kind, whether express or implied. +- */ +- +-#ifndef _DT_BINDINGS_LEDS_NETXBIG_H +-#define _DT_BINDINGS_LEDS_NETXBIG_H +- +-#define NETXBIG_LED_OFF 0 +-#define NETXBIG_LED_ON 1 +-#define NETXBIG_LED_SATA 2 +-#define NETXBIG_LED_TIMER1 3 +-#define NETXBIG_LED_TIMER2 4 +- +-#endif /* _DT_BINDINGS_LEDS_NETXBIG_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/leds/leds-ns2.h b/scripts/dtc/include-prefixes/dt-bindings/leds/leds-ns2.h +deleted file mode 100644 +index fd615749e703..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/leds/leds-ns2.h ++++ /dev/null +@@ -1,9 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef _DT_BINDINGS_LEDS_NS2_H +-#define _DT_BINDINGS_LEDS_NS2_H +- +-#define NS_V2_LED_OFF 0 +-#define NS_V2_LED_ON 1 +-#define NS_V2_LED_SATA 2 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/leds/leds-pca9532.h b/scripts/dtc/include-prefixes/dt-bindings/leds/leds-pca9532.h +deleted file mode 100644 +index 4d917aab7e1e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/leds/leds-pca9532.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-/* +- * This header provides constants for pca9532 LED bindings. +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without any +- * warranty of any kind, whether express or implied. +- */ +- +-#ifndef _DT_BINDINGS_LEDS_PCA9532_H +-#define _DT_BINDINGS_LEDS_PCA9532_H +- +-#define PCA9532_TYPE_NONE 0 +-#define PCA9532_TYPE_LED 1 +-#define PCA9532_TYPE_N2100_BEEP 2 +-#define PCA9532_TYPE_GPIO 3 +-#define PCA9532_LED_TIMER2 4 +- +-#endif /* _DT_BINDINGS_LEDS_PCA9532_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/leds/leds-pca955x.h b/scripts/dtc/include-prefixes/dt-bindings/leds/leds-pca955x.h +deleted file mode 100644 +index 78cb7e979de7..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/leds/leds-pca955x.h ++++ /dev/null +@@ -1,16 +0,0 @@ +-/* +- * This header provides constants for pca955x LED bindings. +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without any +- * warranty of any kind, whether express or implied. +- */ +- +-#ifndef _DT_BINDINGS_LEDS_PCA955X_H +-#define _DT_BINDINGS_LEDS_PCA955X_H +- +-#define PCA955X_TYPE_NONE 0 +-#define PCA955X_TYPE_LED 1 +-#define PCA955X_TYPE_GPIO 2 +- +-#endif /* _DT_BINDINGS_LEDS_PCA955X_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/leds/rt4831-backlight.h b/scripts/dtc/include-prefixes/dt-bindings/leds/rt4831-backlight.h +deleted file mode 100644 +index 125c6351bba0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/leds/rt4831-backlight.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +-/* +- * This header provides constants for rt4831 backlight bindings. +- * +- * Copyright (C) 2020, Richtek Technology Corp. +- * Author: ChiYuan Huang +- */ +- +-#ifndef _DT_BINDINGS_RT4831_BACKLIGHT_H +-#define _DT_BINDINGS_RT4831_BACKLIGHT_H +- +-#define RT4831_BLOVPLVL_17V 0 +-#define RT4831_BLOVPLVL_21V 1 +-#define RT4831_BLOVPLVL_25V 2 +-#define RT4831_BLOVPLVL_29V 3 +- +-#define RT4831_BLED_CH1EN (1 << 0) +-#define RT4831_BLED_CH2EN (1 << 1) +-#define RT4831_BLED_CH3EN (1 << 2) +-#define RT4831_BLED_CH4EN (1 << 3) +-#define RT4831_BLED_ALLCHEN ((1 << 4) - 1) +- +-#endif /* _DT_BINDINGS_RT4831_BACKLIGHT_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mailbox/pl320-mailbox.h b/scripts/dtc/include-prefixes/dt-bindings/mailbox/pl320-mailbox.h +deleted file mode 100644 +index 6711938abaad..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mailbox/pl320-mailbox.h ++++ /dev/null +@@ -1,14 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2019-2023 Hailo Technologies Ltd. All rights reserved. +- * +- * Arm PL320 Mailbox Controller +- */ +- +-#ifndef __DT_BINDINGS_PL320_MAILBOX_H +-#define __DT_BINDINGS_PL320_MAILBOX_H +- +-#define PL320_MBOX_TXDONE_BY_IRQ (0) +-#define PL320_MBOX_TXDONE_BY_ACK (1) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mailbox/qcom-ipcc.h b/scripts/dtc/include-prefixes/dt-bindings/mailbox/qcom-ipcc.h +deleted file mode 100644 +index eb91a6c05b71..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mailbox/qcom-ipcc.h ++++ /dev/null +@@ -1,34 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +-/* +- * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef __DT_BINDINGS_MAILBOX_IPCC_H +-#define __DT_BINDINGS_MAILBOX_IPCC_H +- +-/* Signal IDs for MPROC protocol */ +-#define IPCC_MPROC_SIGNAL_GLINK_QMP 0 +-#define IPCC_MPROC_SIGNAL_SMP2P 2 +-#define IPCC_MPROC_SIGNAL_PING 3 +- +-/* Client IDs */ +-#define IPCC_CLIENT_AOP 0 +-#define IPCC_CLIENT_TZ 1 +-#define IPCC_CLIENT_MPSS 2 +-#define IPCC_CLIENT_LPASS 3 +-#define IPCC_CLIENT_SLPI 4 +-#define IPCC_CLIENT_SDC 5 +-#define IPCC_CLIENT_CDSP 6 +-#define IPCC_CLIENT_NPU 7 +-#define IPCC_CLIENT_APSS 8 +-#define IPCC_CLIENT_GPU 9 +-#define IPCC_CLIENT_CVP 10 +-#define IPCC_CLIENT_CAM 11 +-#define IPCC_CLIENT_VPU 12 +-#define IPCC_CLIENT_PCIE0 13 +-#define IPCC_CLIENT_PCIE1 14 +-#define IPCC_CLIENT_PCIE2 15 +-#define IPCC_CLIENT_SPSS 16 +-#define IPCC_CLIENT_WPSS 24 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mailbox/tegra186-hsp.h b/scripts/dtc/include-prefixes/dt-bindings/mailbox/tegra186-hsp.h +deleted file mode 100644 +index 3bdec7a84d35..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mailbox/tegra186-hsp.h ++++ /dev/null +@@ -1,36 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for binding nvidia,tegra186-hsp. +- */ +- +-#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H +-#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H +- +-/* +- * These define the type of mailbox that is to be used (doorbell, shared +- * mailbox, shared semaphore or arbitrated semaphore). +- */ +-#define TEGRA_HSP_MBOX_TYPE_DB 0x0 +-#define TEGRA_HSP_MBOX_TYPE_SM 0x1 +-#define TEGRA_HSP_MBOX_TYPE_SS 0x2 +-#define TEGRA_HSP_MBOX_TYPE_AS 0x3 +- +-/* +- * These defines represent the bit associated with the given master ID in the +- * doorbell registers. +- */ +-#define TEGRA_HSP_DB_MASTER_CCPLEX 17 +-#define TEGRA_HSP_DB_MASTER_BPMP 19 +- +-/* +- * Shared mailboxes are unidirectional, so the direction needs to be specified +- * in the device tree. +- */ +-#define TEGRA_HSP_SM_MASK 0x00ffffff +-#define TEGRA_HSP_SM_FLAG_RX (0 << 31) +-#define TEGRA_HSP_SM_FLAG_TX (1 << 31) +- +-#define TEGRA_HSP_SM_RX(x) (TEGRA_HSP_SM_FLAG_RX | ((x) & TEGRA_HSP_SM_MASK)) +-#define TEGRA_HSP_SM_TX(x) (TEGRA_HSP_SM_FLAG_TX | ((x) & TEGRA_HSP_SM_MASK)) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/media/c8sectpfe.h b/scripts/dtc/include-prefixes/dt-bindings/media/c8sectpfe.h +deleted file mode 100644 +index 6b1fb6f5413b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/media/c8sectpfe.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_C8SECTPFE_H +-#define __DT_C8SECTPFE_H +- +-#define STV0367_TDA18212_NIMA_1 0 +-#define STV0367_TDA18212_NIMA_2 1 +-#define STV0367_TDA18212_NIMB_1 2 +-#define STV0367_TDA18212_NIMB_2 3 +- +-#define STV0903_6110_LNB24_NIMA 4 +-#define STV0903_6110_LNB24_NIMB 5 +- +-#endif /* __DT_C8SECTPFE_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/media/omap3-isp.h b/scripts/dtc/include-prefixes/dt-bindings/media/omap3-isp.h +deleted file mode 100644 +index 436c71210e65..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/media/omap3-isp.h ++++ /dev/null +@@ -1,14 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * include/dt-bindings/media/omap3-isp.h +- * +- * Copyright (C) 2015 Sakari Ailus +- */ +- +-#ifndef __DT_BINDINGS_OMAP3_ISP_H__ +-#define __DT_BINDINGS_OMAP3_ISP_H__ +- +-#define OMAP3ISP_PHY_TYPE_COMPLEX_IO 0 +-#define OMAP3ISP_PHY_TYPE_CSIPHY 1 +- +-#endif /* __DT_BINDINGS_OMAP3_ISP_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/media/tda1997x.h b/scripts/dtc/include-prefixes/dt-bindings/media/tda1997x.h +deleted file mode 100644 +index bd9fbd718ec9..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/media/tda1997x.h ++++ /dev/null +@@ -1,74 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2017 Gateworks Corporation +- */ +-#ifndef _DT_BINDINGS_MEDIA_TDA1997X_H +-#define _DT_BINDINGS_MEDIA_TDA1997X_H +- +-/* TDA19973 36bit Video Port control registers */ +-#define TDA1997X_VP36_35_32 0 +-#define TDA1997X_VP36_31_28 1 +-#define TDA1997X_VP36_27_24 2 +-#define TDA1997X_VP36_23_20 3 +-#define TDA1997X_VP36_19_16 4 +-#define TDA1997X_VP36_15_12 5 +-#define TDA1997X_VP36_11_08 6 +-#define TDA1997X_VP36_07_04 7 +-#define TDA1997X_VP36_03_00 8 +- +-/* TDA19971 24bit Video Port control registers */ +-#define TDA1997X_VP24_V23_20 0 +-#define TDA1997X_VP24_V19_16 1 +-#define TDA1997X_VP24_V15_12 3 +-#define TDA1997X_VP24_V11_08 4 +-#define TDA1997X_VP24_V07_04 6 +-#define TDA1997X_VP24_V03_00 7 +- +-/* Pin groups */ +-#define TDA1997X_VP_OUT_EN 0x80 /* enable output group */ +-#define TDA1997X_VP_HIZ 0x40 /* hi-Z output group when not used */ +-#define TDA1997X_VP_SWP 0x10 /* pin-swap output group */ +-#define TDA1997X_R_CR_CBCR_3_0 (0 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +-#define TDA1997X_R_CR_CBCR_7_4 (1 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +-#define TDA1997X_R_CR_CBCR_11_8 (2 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +-#define TDA1997X_B_CB_3_0 (3 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +-#define TDA1997X_B_CB_7_4 (4 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +-#define TDA1997X_B_CB_11_8 (5 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +-#define TDA1997X_G_Y_3_0 (6 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +-#define TDA1997X_G_Y_7_4 (7 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +-#define TDA1997X_G_Y_11_8 (8 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +-/* pinswapped groups */ +-#define TDA1997X_R_CR_CBCR_3_0_S (TDA1997X_R_CR_CBCR_3_0 | TDA1997X_VP_SWAP) +-#define TDA1997X_R_CR_CBCR_7_4_S (TDA1997X_R_CR_CBCR_7_4 | TDA1997X_VP_SWAP) +-#define TDA1997X_R_CR_CBCR_11_8_S (TDA1997X_R_CR_CBCR_11_8 | TDA1997X_VP_SWAP) +-#define TDA1997X_B_CB_3_0_S (TDA1997X_B_CB_3_0 | TDA1997X_VP_SWAP) +-#define TDA1997X_B_CB_7_4_S (TDA1997X_B_CB_7_4 | TDA1997X_VP_SWAP) +-#define TDA1997X_B_CB_11_8_S (TDA1997X_B_CB_11_8 | TDA1997X_VP_SWAP) +-#define TDA1997X_G_Y_3_0_S (TDA1997X_G_Y_3_0 | TDA1997X_VP_SWAP) +-#define TDA1997X_G_Y_7_4_S (TDA1997X_G_Y_7_4 | TDA1997X_VP_SWAP) +-#define TDA1997X_G_Y_11_8_S (TDA1997X_G_Y_11_8 | TDA1997X_VP_SWAP) +- +-/* Audio bus DAI format */ +-#define TDA1997X_I2S16 1 /* I2S 16bit */ +-#define TDA1997X_I2S32 2 /* I2S 32bit */ +-#define TDA1997X_SPDIF 3 /* SPDIF */ +-#define TDA1997X_OBA 4 /* One Bit Audio */ +-#define TDA1997X_DST 5 /* Direct Stream Transfer */ +-#define TDA1997X_I2S16_HBR 6 /* HBR straight in I2S 16bit mode */ +-#define TDA1997X_I2S16_HBR_DEMUX 7 /* HBR demux in I2S 16bit mode */ +-#define TDA1997X_I2S32_HBR_DEMUX 8 /* HBR demux in I2S 32bit mode */ +-#define TDA1997X_SPDIF_HBR_DEMUX 9 /* HBR demux in SPDIF mode */ +- +-/* Audio bus channel layout */ +-#define TDA1997X_LAYOUT0 0 /* 2-channel */ +-#define TDA1997X_LAYOUT1 1 /* 8-channel */ +- +-/* Audio bus clock */ +-#define TDA1997X_ACLK_16FS 0 +-#define TDA1997X_ACLK_32FS 1 +-#define TDA1997X_ACLK_64FS 2 +-#define TDA1997X_ACLK_128FS 3 +-#define TDA1997X_ACLK_256FS 4 +-#define TDA1997X_ACLK_512FS 5 +- +-#endif /* _DT_BINDINGS_MEDIA_TDA1997X_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/media/tvp5150.h b/scripts/dtc/include-prefixes/dt-bindings/media/tvp5150.h +deleted file mode 100644 +index dda00c038530..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/media/tvp5150.h ++++ /dev/null +@@ -1,21 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- tvp5150.h - definition for tvp5150 inputs +- +- Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl) +- +-*/ +- +-#ifndef _DT_BINDINGS_MEDIA_TVP5150_H +-#define _DT_BINDINGS_MEDIA_TVP5150_H +- +-/* TVP5150 HW inputs */ +-#define TVP5150_COMPOSITE0 0 +-#define TVP5150_COMPOSITE1 1 +-#define TVP5150_SVIDEO 2 +- +-/* TVP5150 HW outputs */ +-#define TVP5150_NORMAL 0 +-#define TVP5150_BLACK_SCREEN 1 +- +-#endif /* _DT_BINDINGS_MEDIA_TVP5150_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/media/xilinx-vip.h b/scripts/dtc/include-prefixes/dt-bindings/media/xilinx-vip.h +deleted file mode 100644 +index 94ed3edfcc70..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/media/xilinx-vip.h ++++ /dev/null +@@ -1,36 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Xilinx Video IP Core +- * +- * Copyright (C) 2013-2015 Ideas on Board +- * Copyright (C) 2013-2015 Xilinx, Inc. +- * +- * Contacts: Hyun Kwon +- * Laurent Pinchart +- */ +- +-#ifndef __DT_BINDINGS_MEDIA_XILINX_VIP_H__ +-#define __DT_BINDINGS_MEDIA_XILINX_VIP_H__ +- +-/* +- * Video format codes as defined in "AXI4-Stream Video IP and System Design +- * Guide". +- */ +-#define XVIP_VF_YUV_422 0 +-#define XVIP_VF_YUV_444 1 +-#define XVIP_VF_RBG 2 +-#define XVIP_VF_YUV_420 3 +-#define XVIP_VF_YUVA_422 4 +-#define XVIP_VF_YUVA_444 5 +-#define XVIP_VF_RGBA 6 +-#define XVIP_VF_YUVA_420 7 +-#define XVIP_VF_YUVD_422 8 +-#define XVIP_VF_YUVD_444 9 +-#define XVIP_VF_RGBD 10 +-#define XVIP_VF_YUVD_420 11 +-#define XVIP_VF_MONO_SENSOR 12 +-#define XVIP_VF_CUSTOM2 13 +-#define XVIP_VF_CUSTOM3 14 +-#define XVIP_VF_CUSTOM4 15 +- +-#endif /* __DT_BINDINGS_MEDIA_XILINX_VIP_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/memory/mt2701-larb-port.h b/scripts/dtc/include-prefixes/dt-bindings/memory/mt2701-larb-port.h +deleted file mode 100644 +index 25d03526f142..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/memory/mt2701-larb-port.h ++++ /dev/null +@@ -1,77 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2015 MediaTek Inc. +- * Author: Honghui Zhang +- */ +- +-#ifndef _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_ +-#define _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_ +- +-/* +- * Mediatek m4u generation 1 such as mt2701 has flat m4u port numbers, +- * the first port's id for larb[N] would be the last port's id of larb[N - 1] +- * plus one while larb[0]'s first port number is 0. The definition of +- * MT2701_M4U_ID_LARBx is following HW register spec. +- * But m4u generation 2 like mt8173 have different port number, it use fixed +- * offset for each larb, the first port's id for larb[N] would be (N * 32). +- */ +-#define LARB0_PORT_OFFSET 0 +-#define LARB1_PORT_OFFSET 11 +-#define LARB2_PORT_OFFSET 21 +-#define LARB3_PORT_OFFSET 44 +- +-#define MT2701_M4U_ID_LARB0(port) ((port) + LARB0_PORT_OFFSET) +-#define MT2701_M4U_ID_LARB1(port) ((port) + LARB1_PORT_OFFSET) +-#define MT2701_M4U_ID_LARB2(port) ((port) + LARB2_PORT_OFFSET) +- +-/* Port define for larb0 */ +-#define MT2701_M4U_PORT_DISP_OVL_0 MT2701_M4U_ID_LARB0(0) +-#define MT2701_M4U_PORT_DISP_RDMA1 MT2701_M4U_ID_LARB0(1) +-#define MT2701_M4U_PORT_DISP_RDMA MT2701_M4U_ID_LARB0(2) +-#define MT2701_M4U_PORT_DISP_WDMA MT2701_M4U_ID_LARB0(3) +-#define MT2701_M4U_PORT_MM_CMDQ MT2701_M4U_ID_LARB0(4) +-#define MT2701_M4U_PORT_MDP_RDMA MT2701_M4U_ID_LARB0(5) +-#define MT2701_M4U_PORT_MDP_WDMA MT2701_M4U_ID_LARB0(6) +-#define MT2701_M4U_PORT_MDP_ROTO MT2701_M4U_ID_LARB0(7) +-#define MT2701_M4U_PORT_MDP_ROTCO MT2701_M4U_ID_LARB0(8) +-#define MT2701_M4U_PORT_MDP_ROTVO MT2701_M4U_ID_LARB0(9) +-#define MT2701_M4U_PORT_MDP_RDMA1 MT2701_M4U_ID_LARB0(10) +- +-/* Port define for larb1 */ +-#define MT2701_M4U_PORT_VDEC_MC_EXT MT2701_M4U_ID_LARB1(0) +-#define MT2701_M4U_PORT_VDEC_PP_EXT MT2701_M4U_ID_LARB1(1) +-#define MT2701_M4U_PORT_VDEC_PPWRAP_EXT MT2701_M4U_ID_LARB1(2) +-#define MT2701_M4U_PORT_VDEC_AVC_MV_EXT MT2701_M4U_ID_LARB1(3) +-#define MT2701_M4U_PORT_VDEC_PRED_RD_EXT MT2701_M4U_ID_LARB1(4) +-#define MT2701_M4U_PORT_VDEC_PRED_WR_EXT MT2701_M4U_ID_LARB1(5) +-#define MT2701_M4U_PORT_VDEC_VLD_EXT MT2701_M4U_ID_LARB1(6) +-#define MT2701_M4U_PORT_VDEC_VLD2_EXT MT2701_M4U_ID_LARB1(7) +-#define MT2701_M4U_PORT_VDEC_TILE_EXT MT2701_M4U_ID_LARB1(8) +-#define MT2701_M4U_PORT_VDEC_IMG_RESZ_EXT MT2701_M4U_ID_LARB1(9) +- +-/* Port define for larb2 */ +-#define MT2701_M4U_PORT_VENC_RCPU MT2701_M4U_ID_LARB2(0) +-#define MT2701_M4U_PORT_VENC_REC_FRM MT2701_M4U_ID_LARB2(1) +-#define MT2701_M4U_PORT_VENC_BSDMA MT2701_M4U_ID_LARB2(2) +-#define MT2701_M4U_PORT_JPGENC_RDMA MT2701_M4U_ID_LARB2(3) +-#define MT2701_M4U_PORT_VENC_LT_RCPU MT2701_M4U_ID_LARB2(4) +-#define MT2701_M4U_PORT_VENC_LT_REC_FRM MT2701_M4U_ID_LARB2(5) +-#define MT2701_M4U_PORT_VENC_LT_BSDMA MT2701_M4U_ID_LARB2(6) +-#define MT2701_M4U_PORT_JPGDEC_BSDMA MT2701_M4U_ID_LARB2(7) +-#define MT2701_M4U_PORT_VENC_SV_COMV MT2701_M4U_ID_LARB2(8) +-#define MT2701_M4U_PORT_VENC_RD_COMV MT2701_M4U_ID_LARB2(9) +-#define MT2701_M4U_PORT_JPGENC_BSDMA MT2701_M4U_ID_LARB2(10) +-#define MT2701_M4U_PORT_VENC_CUR_LUMA MT2701_M4U_ID_LARB2(11) +-#define MT2701_M4U_PORT_VENC_CUR_CHROMA MT2701_M4U_ID_LARB2(12) +-#define MT2701_M4U_PORT_VENC_REF_LUMA MT2701_M4U_ID_LARB2(13) +-#define MT2701_M4U_PORT_VENC_REF_CHROMA MT2701_M4U_ID_LARB2(14) +-#define MT2701_M4U_PORT_IMG_RESZ MT2701_M4U_ID_LARB2(15) +-#define MT2701_M4U_PORT_VENC_LT_SV_COMV MT2701_M4U_ID_LARB2(16) +-#define MT2701_M4U_PORT_VENC_LT_RD_COMV MT2701_M4U_ID_LARB2(17) +-#define MT2701_M4U_PORT_VENC_LT_CUR_LUMA MT2701_M4U_ID_LARB2(18) +-#define MT2701_M4U_PORT_VENC_LT_CUR_CHROMA MT2701_M4U_ID_LARB2(19) +-#define MT2701_M4U_PORT_VENC_LT_REF_LUMA MT2701_M4U_ID_LARB2(20) +-#define MT2701_M4U_PORT_VENC_LT_REF_CHROMA MT2701_M4U_ID_LARB2(21) +-#define MT2701_M4U_PORT_JPGDEC_WDMA MT2701_M4U_ID_LARB2(22) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/memory/mt2712-larb-port.h b/scripts/dtc/include-prefixes/dt-bindings/memory/mt2712-larb-port.h +deleted file mode 100644 +index e41a2841bcff..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/memory/mt2712-larb-port.h ++++ /dev/null +@@ -1,95 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2017 MediaTek Inc. +- * Author: Yong Wu +- */ +-#ifndef _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_ +-#define _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_ +- +-#include +- +-#define M4U_LARB0_ID 0 +-#define M4U_LARB1_ID 1 +-#define M4U_LARB2_ID 2 +-#define M4U_LARB3_ID 3 +-#define M4U_LARB4_ID 4 +-#define M4U_LARB5_ID 5 +-#define M4U_LARB6_ID 6 +-#define M4U_LARB7_ID 7 +-#define M4U_LARB8_ID 8 +-#define M4U_LARB9_ID 9 +- +-/* larb0 */ +-#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) +-#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) +-#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) +-#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3) +-#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4) +-#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) +-#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6) +-#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 7) +- +-/* larb1 */ +-#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) +-#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) +-#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) +-#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) +-#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) +-#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) +-#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) +-#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7) +-#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8) +-#define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9) +-#define M4U_PORT_HW_IMG_RESZ_EXT MTK_M4U_ID(M4U_LARB1_ID, 10) +- +-/* larb2 */ +-#define M4U_PORT_CAM_DMA0 MTK_M4U_ID(M4U_LARB2_ID, 0) +-#define M4U_PORT_CAM_DMA1 MTK_M4U_ID(M4U_LARB2_ID, 1) +-#define M4U_PORT_CAM_DMA2 MTK_M4U_ID(M4U_LARB2_ID, 2) +- +-/* larb3 */ +-#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) +-#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) +-#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) +-#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) +-#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) +-#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 5) +-#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 6) +-#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 7) +-#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 8) +- +-/* larb4 */ +-#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0) +-#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1) +-#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 2) +-#define M4U_PORT_DISP_OD1_R MTK_M4U_ID(M4U_LARB4_ID, 3) +-#define M4U_PORT_DISP_OD1_W MTK_M4U_ID(M4U_LARB4_ID, 4) +-#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 5) +-#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 6) +- +-/* larb5 */ +-#define M4U_PORT_DISP_OVL2 MTK_M4U_ID(M4U_LARB5_ID, 0) +-#define M4U_PORT_DISP_WDMA2 MTK_M4U_ID(M4U_LARB5_ID, 1) +-#define M4U_PORT_MDP_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 2) +-#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB5_ID, 3) +- +-/* larb6 */ +-#define M4U_PORT_JPGDEC_WDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 0) +-#define M4U_PORT_JPGDEC_WDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 1) +-#define M4U_PORT_JPGDEC_BSDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 2) +-#define M4U_PORT_JPGDEC_BSDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 3) +- +-/* larb7 */ +-#define M4U_PORT_MDP_RDMA3 MTK_M4U_ID(M4U_LARB7_ID, 0) +-#define M4U_PORT_MDP_WROT2 MTK_M4U_ID(M4U_LARB7_ID, 1) +- +-/* larb8 */ +-#define M4U_PORT_VDO MTK_M4U_ID(M4U_LARB8_ID, 0) +-#define M4U_PORT_NR MTK_M4U_ID(M4U_LARB8_ID, 1) +-#define M4U_PORT_WR_CHANNEL0 MTK_M4U_ID(M4U_LARB8_ID, 2) +- +-/* larb9 */ +-#define M4U_PORT_TVD MTK_M4U_ID(M4U_LARB9_ID, 0) +-#define M4U_PORT_WR_CHANNEL1 MTK_M4U_ID(M4U_LARB9_ID, 1) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/memory/mt6779-larb-port.h b/scripts/dtc/include-prefixes/dt-bindings/memory/mt6779-larb-port.h +deleted file mode 100644 +index 3fb438a96e35..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/memory/mt6779-larb-port.h ++++ /dev/null +@@ -1,206 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2019 MediaTek Inc. +- * Author: Chao Hao +- */ +- +-#ifndef _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_ +-#define _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_ +- +-#include +- +-#define M4U_LARB0_ID 0 +-#define M4U_LARB1_ID 1 +-#define M4U_LARB2_ID 2 +-#define M4U_LARB3_ID 3 +-#define M4U_LARB4_ID 4 +-#define M4U_LARB5_ID 5 +-#define M4U_LARB6_ID 6 +-#define M4U_LARB7_ID 7 +-#define M4U_LARB8_ID 8 +-#define M4U_LARB9_ID 9 +-#define M4U_LARB10_ID 10 +-#define M4U_LARB11_ID 11 +- +-/* larb0 */ +-#define M4U_PORT_DISP_POSTMASK0 MTK_M4U_ID(M4U_LARB0_ID, 0) +-#define M4U_PORT_DISP_OVL0_HDR MTK_M4U_ID(M4U_LARB0_ID, 1) +-#define M4U_PORT_DISP_OVL1_HDR MTK_M4U_ID(M4U_LARB0_ID, 2) +-#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 3) +-#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4) +-#define M4U_PORT_DISP_PVRIC0 MTK_M4U_ID(M4U_LARB0_ID, 5) +-#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) +-#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 7) +-#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 8) +- +-/* larb1 */ +-#define M4U_PORT_DISP_OVL0_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 0) +-#define M4U_PORT_DISP_OVL1_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 1) +-#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB1_ID, 2) +-#define M4U_PORT_DISP_OVL1_2L MTK_M4U_ID(M4U_LARB1_ID, 3) +-#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 4) +-#define M4U_PORT_MDP_PVRIC0 MTK_M4U_ID(M4U_LARB1_ID, 5) +-#define M4U_PORT_MDP_PVRIC1 MTK_M4U_ID(M4U_LARB1_ID, 6) +-#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB1_ID, 7) +-#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 8) +-#define M4U_PORT_MDP_WROT0_R MTK_M4U_ID(M4U_LARB1_ID, 9) +-#define M4U_PORT_MDP_WROT0_W MTK_M4U_ID(M4U_LARB1_ID, 10) +-#define M4U_PORT_MDP_WROT1_R MTK_M4U_ID(M4U_LARB1_ID, 11) +-#define M4U_PORT_MDP_WROT1_W MTK_M4U_ID(M4U_LARB1_ID, 12) +-#define M4U_PORT_DISP_FAKE1 MTK_M4U_ID(M4U_LARB1_ID, 13) +- +-/* larb2-VDEC */ +-#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) +-#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) +-#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) +-#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) +-#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) +-#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) +-#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) +-#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 7) +-#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB2_ID, 8) +-#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 9) +-#define M4U_PORT_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(M4U_LARB2_ID, 10) +-#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB2_ID, 11) +- +-/* larb3-VENC */ +-#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) +-#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) +-#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) +-#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) +-#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) +-#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) +-#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 6) +-#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB3_ID, 7) +-#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8) +-#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB3_ID, 9) +-#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 10) +-#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 11) +-#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 12) +-#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 13) +-#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 14) +-#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 15) +-#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 16) +-#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 17) +-#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 18) +- +-/* larb4-dummy */ +- +-/* larb5-IMG */ +-#define M4U_PORT_IMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 0) +-#define M4U_PORT_IMGBI_D1 MTK_M4U_ID(M4U_LARB5_ID, 1) +-#define M4U_PORT_DMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 2) +-#define M4U_PORT_DEPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 3) +-#define M4U_PORT_LCEI_D1 MTK_M4U_ID(M4U_LARB5_ID, 4) +-#define M4U_PORT_SMTI_D1 MTK_M4U_ID(M4U_LARB5_ID, 5) +-#define M4U_PORT_SMTO_D2 MTK_M4U_ID(M4U_LARB5_ID, 6) +-#define M4U_PORT_SMTO_D1 MTK_M4U_ID(M4U_LARB5_ID, 7) +-#define M4U_PORT_CRZO_D1 MTK_M4U_ID(M4U_LARB5_ID, 8) +-#define M4U_PORT_IMG3O_D1 MTK_M4U_ID(M4U_LARB5_ID, 9) +-#define M4U_PORT_VIPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 10) +-#define M4U_PORT_WPE_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 11) +-#define M4U_PORT_WPE_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 12) +-#define M4U_PORT_WPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 13) +-#define M4U_PORT_TIMGO_D1 MTK_M4U_ID(M4U_LARB5_ID, 14) +-#define M4U_PORT_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 15) +-#define M4U_PORT_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 16) +-#define M4U_PORT_MFB_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 17) +-#define M4U_PORT_MFB_RDMA3 MTK_M4U_ID(M4U_LARB5_ID, 18) +-#define M4U_PORT_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 19) +-#define M4U_PORT_RESERVE1 MTK_M4U_ID(M4U_LARB5_ID, 20) +-#define M4U_PORT_RESERVE2 MTK_M4U_ID(M4U_LARB5_ID, 21) +-#define M4U_PORT_RESERVE3 MTK_M4U_ID(M4U_LARB5_ID, 22) +-#define M4U_PORT_RESERVE4 MTK_M4U_ID(M4U_LARB5_ID, 23) +-#define M4U_PORT_RESERVE5 MTK_M4U_ID(M4U_LARB5_ID, 24) +-#define M4U_PORT_RESERVE6 MTK_M4U_ID(M4U_LARB5_ID, 25) +- +-/* larb6-IMG-VPU */ +-#define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB6_ID, 0) +-#define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB6_ID, 1) +-#define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB6_ID, 2) +- +-/* larb7-DVS */ +-#define M4U_PORT_DVS_RDMA MTK_M4U_ID(M4U_LARB7_ID, 0) +-#define M4U_PORT_DVS_WDMA MTK_M4U_ID(M4U_LARB7_ID, 1) +-#define M4U_PORT_DVP_RDMA MTK_M4U_ID(M4U_LARB7_ID, 2) +-#define M4U_PORT_DVP_WDMA MTK_M4U_ID(M4U_LARB7_ID, 3) +- +-/* larb8-IPESYS */ +-#define M4U_PORT_FDVT_RDA MTK_M4U_ID(M4U_LARB8_ID, 0) +-#define M4U_PORT_FDVT_RDB MTK_M4U_ID(M4U_LARB8_ID, 1) +-#define M4U_PORT_FDVT_WRA MTK_M4U_ID(M4U_LARB8_ID, 2) +-#define M4U_PORT_FDVT_WRB MTK_M4U_ID(M4U_LARB8_ID, 3) +-#define M4U_PORT_FE_RD0 MTK_M4U_ID(M4U_LARB8_ID, 4) +-#define M4U_PORT_FE_RD1 MTK_M4U_ID(M4U_LARB8_ID, 5) +-#define M4U_PORT_FE_WR0 MTK_M4U_ID(M4U_LARB8_ID, 6) +-#define M4U_PORT_FE_WR1 MTK_M4U_ID(M4U_LARB8_ID, 7) +-#define M4U_PORT_RSC_RDMA0 MTK_M4U_ID(M4U_LARB8_ID, 8) +-#define M4U_PORT_RSC_WDMA MTK_M4U_ID(M4U_LARB8_ID, 9) +- +-/* larb9-CAM */ +-#define M4U_PORT_CAM_IMGO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 0) +-#define M4U_PORT_CAM_RRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 1) +-#define M4U_PORT_CAM_LSCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 2) +-#define M4U_PORT_CAM_BPCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 3) +-#define M4U_PORT_CAM_YUVO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 4) +-#define M4U_PORT_CAM_UFDI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 5) +-#define M4U_PORT_CAM_RAWI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 6) +-#define M4U_PORT_CAM_RAWI_R5_C MTK_M4U_ID(M4U_LARB9_ID, 7) +-#define M4U_PORT_CAM_CAMSV_1 MTK_M4U_ID(M4U_LARB9_ID, 8) +-#define M4U_PORT_CAM_CAMSV_2 MTK_M4U_ID(M4U_LARB9_ID, 9) +-#define M4U_PORT_CAM_CAMSV_3 MTK_M4U_ID(M4U_LARB9_ID, 10) +-#define M4U_PORT_CAM_CAMSV_4 MTK_M4U_ID(M4U_LARB9_ID, 11) +-#define M4U_PORT_CAM_CAMSV_5 MTK_M4U_ID(M4U_LARB9_ID, 12) +-#define M4U_PORT_CAM_CAMSV_6 MTK_M4U_ID(M4U_LARB9_ID, 13) +-#define M4U_PORT_CAM_AAO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 14) +-#define M4U_PORT_CAM_AFO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 15) +-#define M4U_PORT_CAM_FLKO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 16) +-#define M4U_PORT_CAM_LCESO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 17) +-#define M4U_PORT_CAM_CRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 18) +-#define M4U_PORT_CAM_LTMSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 19) +-#define M4U_PORT_CAM_RSSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 20) +-#define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB9_ID, 21) +-#define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB9_ID, 22) +-#define M4U_PORT_CAM_FAKE MTK_M4U_ID(M4U_LARB9_ID, 23) +- +-/* larb10-CAM_A */ +-#define M4U_PORT_CAM_IMGO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 0) +-#define M4U_PORT_CAM_RRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 1) +-#define M4U_PORT_CAM_LSCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 2) +-#define M4U_PORT_CAM_BPCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 3) +-#define M4U_PORT_CAM_YUVO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 4) +-#define M4U_PORT_CAM_UFDI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 5) +-#define M4U_PORT_CAM_RAWI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 6) +-#define M4U_PORT_CAM_RAWI_R5_A MTK_M4U_ID(M4U_LARB10_ID, 7) +-#define M4U_PORT_CAM_IMGO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 8) +-#define M4U_PORT_CAM_RRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 9) +-#define M4U_PORT_CAM_LSCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 10) +-#define M4U_PORT_CAM_BPCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 11) +-#define M4U_PORT_CAM_YUVO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 12) +-#define M4U_PORT_CAM_UFDI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 13) +-#define M4U_PORT_CAM_RAWI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 14) +-#define M4U_PORT_CAM_RAWI_R5_B MTK_M4U_ID(M4U_LARB10_ID, 15) +-#define M4U_PORT_CAM_CAMSV_0 MTK_M4U_ID(M4U_LARB10_ID, 16) +-#define M4U_PORT_CAM_AAO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 17) +-#define M4U_PORT_CAM_AFO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 18) +-#define M4U_PORT_CAM_FLKO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 19) +-#define M4U_PORT_CAM_LCESO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 20) +-#define M4U_PORT_CAM_CRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 21) +-#define M4U_PORT_CAM_AAO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 22) +-#define M4U_PORT_CAM_AFO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 23) +-#define M4U_PORT_CAM_FLKO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 24) +-#define M4U_PORT_CAM_LCESO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 25) +-#define M4U_PORT_CAM_CRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 26) +-#define M4U_PORT_CAM_LTMSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 27) +-#define M4U_PORT_CAM_RSSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 28) +-#define M4U_PORT_CAM_LTMSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 29) +-#define M4U_PORT_CAM_RSSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 30) +- +-/* larb11-CAM-VPU */ +-#define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB11_ID, 0) +-#define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB11_ID, 1) +-#define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB11_ID, 2) +-#define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB11_ID, 3) +-#define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB11_ID, 4) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/memory/mt8167-larb-port.h b/scripts/dtc/include-prefixes/dt-bindings/memory/mt8167-larb-port.h +deleted file mode 100644 +index aae57d4824ca..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/memory/mt8167-larb-port.h ++++ /dev/null +@@ -1,51 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2020 MediaTek Inc. +- * Copyright (c) 2020 BayLibre, SAS +- * Author: Honghui Zhang +- * Author: Fabien Parent +- */ +-#ifndef _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_ +-#define _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_ +- +-#include +- +-#define M4U_LARB0_ID 0 +-#define M4U_LARB1_ID 1 +-#define M4U_LARB2_ID 2 +- +-/* larb0 */ +-#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) +-#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) +-#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) +-#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 3) +-#define M4U_PORT_MDP_RDMA MTK_M4U_ID(M4U_LARB0_ID, 4) +-#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 5) +-#define M4U_PORT_MDP_WROT MTK_M4U_ID(M4U_LARB0_ID, 6) +-#define M4U_PORT_DISP_FAKE MTK_M4U_ID(M4U_LARB0_ID, 7) +- +-/* larb1*/ +-#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB1_ID, 0) +-#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB1_ID, 1) +-#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB1_ID, 2) +-#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB1_ID, 3) +-#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB1_ID, 4) +-#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 5) +-#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 6) +-#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 7) +-#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB1_ID, 8) +-#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 9) +-#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 10) +-#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 11) +-#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 12) +- +-/* larb2*/ +-#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) +-#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) +-#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) +-#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) +-#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) +-#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) +-#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/memory/mt8173-larb-port.h b/scripts/dtc/include-prefixes/dt-bindings/memory/mt8173-larb-port.h +deleted file mode 100644 +index 167a7fc51868..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/memory/mt8173-larb-port.h ++++ /dev/null +@@ -1,99 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2015-2016 MediaTek Inc. +- * Author: Yong Wu +- */ +-#ifndef _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_ +-#define _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_ +- +-#include +- +-#define M4U_LARB0_ID 0 +-#define M4U_LARB1_ID 1 +-#define M4U_LARB2_ID 2 +-#define M4U_LARB3_ID 3 +-#define M4U_LARB4_ID 4 +-#define M4U_LARB5_ID 5 +- +-/* larb0 */ +-#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) +-#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) +-#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) +-#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3) +-#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4) +-#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) +-#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6) +-#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7) +- +-/* larb1 */ +-#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) +-#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) +-#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) +-#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) +-#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) +-#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) +-#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) +-#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7) +-#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8) +-#define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9) +- +-/* larb2 */ +-#define M4U_PORT_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0) +-#define M4U_PORT_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1) +-#define M4U_PORT_AAO MTK_M4U_ID(M4U_LARB2_ID, 2) +-#define M4U_PORT_LCSO MTK_M4U_ID(M4U_LARB2_ID, 3) +-#define M4U_PORT_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4) +-#define M4U_PORT_IMGO_D MTK_M4U_ID(M4U_LARB2_ID, 5) +-#define M4U_PORT_LSCI MTK_M4U_ID(M4U_LARB2_ID, 6) +-#define M4U_PORT_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 7) +-#define M4U_PORT_BPCI MTK_M4U_ID(M4U_LARB2_ID, 8) +-#define M4U_PORT_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 9) +-#define M4U_PORT_UFDI MTK_M4U_ID(M4U_LARB2_ID, 10) +-#define M4U_PORT_IMGI MTK_M4U_ID(M4U_LARB2_ID, 11) +-#define M4U_PORT_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 12) +-#define M4U_PORT_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 13) +-#define M4U_PORT_VIPI MTK_M4U_ID(M4U_LARB2_ID, 14) +-#define M4U_PORT_VIP2I MTK_M4U_ID(M4U_LARB2_ID, 15) +-#define M4U_PORT_VIP3I MTK_M4U_ID(M4U_LARB2_ID, 16) +-#define M4U_PORT_LCEI MTK_M4U_ID(M4U_LARB2_ID, 17) +-#define M4U_PORT_RB MTK_M4U_ID(M4U_LARB2_ID, 18) +-#define M4U_PORT_RP MTK_M4U_ID(M4U_LARB2_ID, 19) +-#define M4U_PORT_WR MTK_M4U_ID(M4U_LARB2_ID, 20) +- +-/* larb3 */ +-#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) +-#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) +-#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) +-#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) +-#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) +-#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) +-#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 6) +-#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 7) +-#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 8) +-#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 9) +-#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 10) +-#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 11) +-#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 12) +-#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 13) +-#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 14) +- +-/* larb4 */ +-#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0) +-#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1) +-#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB4_ID, 2) +-#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 3) +-#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 4) +-#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 5) +- +-/* larb5 */ +-#define M4U_PORT_VENC_RCPU_SET2 MTK_M4U_ID(M4U_LARB5_ID, 0) +-#define M4U_PORT_VENC_REC_FRM_SET2 MTK_M4U_ID(M4U_LARB5_ID, 1) +-#define M4U_PORT_VENC_REF_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 2) +-#define M4U_PORT_VENC_REC_CHROMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 3) +-#define M4U_PORT_VENC_BSDMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 4) +-#define M4U_PORT_VENC_CUR_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 5) +-#define M4U_PORT_VENC_CUR_CHROMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 6) +-#define M4U_PORT_VENC_RD_COMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 7) +-#define M4U_PORT_VENC_SV_COMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 8) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/memory/mt8183-larb-port.h b/scripts/dtc/include-prefixes/dt-bindings/memory/mt8183-larb-port.h +deleted file mode 100644 +index 36abdf0ce5a2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/memory/mt8183-larb-port.h ++++ /dev/null +@@ -1,130 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2018 MediaTek Inc. +- * Author: Yong Wu +- */ +-#ifndef _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_ +-#define _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_ +- +-#include +- +-#define M4U_LARB0_ID 0 +-#define M4U_LARB1_ID 1 +-#define M4U_LARB2_ID 2 +-#define M4U_LARB3_ID 3 +-#define M4U_LARB4_ID 4 +-#define M4U_LARB5_ID 5 +-#define M4U_LARB6_ID 6 +-#define M4U_LARB7_ID 7 +- +-/* larb0 */ +-#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) +-#define M4U_PORT_DISP_2L_OVL0_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 1) +-#define M4U_PORT_DISP_2L_OVL1_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 2) +-#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3) +-#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4) +-#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) +-#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) +-#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7) +-#define M4U_PORT_MDP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 8) +-#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9) +- +-/* larb1 */ +-#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) +-#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) +-#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) +-#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) +-#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) +-#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) +-#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) +- +-/* larb2 VPU0 */ +-#define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB2_ID, 0) +-#define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB2_ID, 1) +-#define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB2_ID, 2) +- +-/* larb3 VPU1 */ +-#define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB3_ID, 0) +-#define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB3_ID, 1) +-#define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB3_ID, 2) +-#define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB3_ID, 3) +-#define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB3_ID, 4) +- +-/* larb4 */ +-#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB4_ID, 0) +-#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB4_ID, 1) +-#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 2) +-#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB4_ID, 3) +-#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB4_ID, 4) +-#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB4_ID, 5) +-#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 6) +-#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB4_ID, 7) +-#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 8) +-#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB4_ID, 9) +-#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 10) +- +-/* larb5 */ +-#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB5_ID, 0) +-#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB5_ID, 1) +-#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB5_ID, 2) +-#define M4U_PORT_CAM_VIPI MTK_M4U_ID(M4U_LARB5_ID, 3) +-#define M4U_PORT_CAM_LCEI MTK_M4U_ID(M4U_LARB5_ID, 4) +-#define M4U_PORT_CAM_SMXI MTK_M4U_ID(M4U_LARB5_ID, 5) +-#define M4U_PORT_CAM_SMXO MTK_M4U_ID(M4U_LARB5_ID, 6) +-#define M4U_PORT_CAM_WPE0_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 7) +-#define M4U_PORT_CAM_WPE0_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 8) +-#define M4U_PORT_CAM_WPE0_WDMA MTK_M4U_ID(M4U_LARB5_ID, 9) +-#define M4U_PORT_CAM_FDVT_RP MTK_M4U_ID(M4U_LARB5_ID, 10) +-#define M4U_PORT_CAM_FDVT_WR MTK_M4U_ID(M4U_LARB5_ID, 11) +-#define M4U_PORT_CAM_FDVT_RB MTK_M4U_ID(M4U_LARB5_ID, 12) +-#define M4U_PORT_CAM_WPE1_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 13) +-#define M4U_PORT_CAM_WPE1_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 14) +-#define M4U_PORT_CAM_WPE1_WDMA MTK_M4U_ID(M4U_LARB5_ID, 15) +-#define M4U_PORT_CAM_DPE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 16) +-#define M4U_PORT_CAM_DPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 17) +-#define M4U_PORT_CAM_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 18) +-#define M4U_PORT_CAM_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 19) +-#define M4U_PORT_CAM_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 20) +-#define M4U_PORT_CAM_RSC_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 21) +-#define M4U_PORT_CAM_RSC_WDMA MTK_M4U_ID(M4U_LARB5_ID, 22) +-#define M4U_PORT_CAM_OWE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 23) +-#define M4U_PORT_CAM_OWE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 24) +- +-/* larb6 */ +-#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB6_ID, 0) +-#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB6_ID, 1) +-#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB6_ID, 2) +-#define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB6_ID, 3) +-#define M4U_PORT_CAM_LSCI0 MTK_M4U_ID(M4U_LARB6_ID, 4) +-#define M4U_PORT_CAM_LSCI1 MTK_M4U_ID(M4U_LARB6_ID, 5) +-#define M4U_PORT_CAM_PDO MTK_M4U_ID(M4U_LARB6_ID, 6) +-#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB6_ID, 7) +-#define M4U_PORT_CAM_LCSO MTK_M4U_ID(M4U_LARB6_ID, 8) +-#define M4U_PORT_CAM_CAM_RSSO_A MTK_M4U_ID(M4U_LARB6_ID, 9) +-#define M4U_PORT_CAM_UFEO MTK_M4U_ID(M4U_LARB6_ID, 10) +-#define M4U_PORT_CAM_SOCO MTK_M4U_ID(M4U_LARB6_ID, 11) +-#define M4U_PORT_CAM_SOC1 MTK_M4U_ID(M4U_LARB6_ID, 12) +-#define M4U_PORT_CAM_SOC2 MTK_M4U_ID(M4U_LARB6_ID, 13) +-#define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB6_ID, 14) +-#define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB6_ID, 15) +-#define M4U_PORT_CAM_RAWI_A MTK_M4U_ID(M4U_LARB6_ID, 16) +-#define M4U_PORT_CAM_CCUG MTK_M4U_ID(M4U_LARB6_ID, 17) +-#define M4U_PORT_CAM_PSO MTK_M4U_ID(M4U_LARB6_ID, 18) +-#define M4U_PORT_CAM_AFO_1 MTK_M4U_ID(M4U_LARB6_ID, 19) +-#define M4U_PORT_CAM_LSCI_2 MTK_M4U_ID(M4U_LARB6_ID, 20) +-#define M4U_PORT_CAM_PDI MTK_M4U_ID(M4U_LARB6_ID, 21) +-#define M4U_PORT_CAM_FLKO MTK_M4U_ID(M4U_LARB6_ID, 22) +-#define M4U_PORT_CAM_LMVO MTK_M4U_ID(M4U_LARB6_ID, 23) +-#define M4U_PORT_CAM_UFGO MTK_M4U_ID(M4U_LARB6_ID, 24) +-#define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB6_ID, 25) +-#define M4U_PORT_CAM_SPARE_2 MTK_M4U_ID(M4U_LARB6_ID, 26) +-#define M4U_PORT_CAM_SPARE_3 MTK_M4U_ID(M4U_LARB6_ID, 27) +-#define M4U_PORT_CAM_SPARE_4 MTK_M4U_ID(M4U_LARB6_ID, 28) +-#define M4U_PORT_CAM_SPARE_5 MTK_M4U_ID(M4U_LARB6_ID, 29) +-#define M4U_PORT_CAM_SPARE_6 MTK_M4U_ID(M4U_LARB6_ID, 30) +- +-/* CCU */ +-#define M4U_PORT_CCU0 MTK_M4U_ID(M4U_LARB7_ID, 0) +-#define M4U_PORT_CCU1 MTK_M4U_ID(M4U_LARB7_ID, 1) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/memory/mt8192-larb-port.h b/scripts/dtc/include-prefixes/dt-bindings/memory/mt8192-larb-port.h +deleted file mode 100644 +index 23035a52c675..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/memory/mt8192-larb-port.h ++++ /dev/null +@@ -1,243 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2020 MediaTek Inc. +- * +- * Author: Chao Hao +- * Author: Yong Wu +- */ +-#ifndef _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_ +-#define _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_ +- +-#include +- +-/* +- * MM IOMMU supports 16GB dma address. +- * +- * The address will preassign like this: +- * +- * modules dma-address-region larbs-ports +- * disp 0 ~ 4G larb0/1 +- * vcodec 4G ~ 8G larb4/5/7 +- * cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20 +- * CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10 +- * CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5 +- * +- * larb3/6/8/10/12/15 is null. +- */ +- +-/* larb0 */ +-#define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_ID(0, 0) +-#define M4U_PORT_L0_OVL_RDMA0_HDR MTK_M4U_ID(0, 1) +-#define M4U_PORT_L0_OVL_RDMA0 MTK_M4U_ID(0, 2) +-#define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 3) +-#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(0, 4) +-#define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 5) +- +-/* larb1 */ +-#define M4U_PORT_L1_OVL_2L_RDMA0_HDR MTK_M4U_ID(1, 0) +-#define M4U_PORT_L1_OVL_2L_RDMA2_HDR MTK_M4U_ID(1, 1) +-#define M4U_PORT_L1_OVL_2L_RDMA0 MTK_M4U_ID(1, 2) +-#define M4U_PORT_L1_OVL_2L_RDMA2 MTK_M4U_ID(1, 3) +-#define M4U_PORT_L1_DISP_MDP_RDMA4 MTK_M4U_ID(1, 4) +-#define M4U_PORT_L1_DISP_RDMA4 MTK_M4U_ID(1, 5) +-#define M4U_PORT_L1_DISP_UFBC_WDMA0 MTK_M4U_ID(1, 6) +-#define M4U_PORT_L1_DISP_FAKE1 MTK_M4U_ID(1, 7) +- +-/* larb2 */ +-#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0) +-#define M4U_PORT_L2_MDP_RDMA1 MTK_M4U_ID(2, 1) +-#define M4U_PORT_L2_MDP_WROT0 MTK_M4U_ID(2, 2) +-#define M4U_PORT_L2_MDP_WROT1 MTK_M4U_ID(2, 3) +-#define M4U_PORT_L2_MDP_DISP_FAKE0 MTK_M4U_ID(2, 4) +- +-/* larb3: null */ +- +-/* larb4 */ +-#define M4U_PORT_L4_VDEC_MC_EXT MTK_M4U_ID(4, 0) +-#define M4U_PORT_L4_VDEC_UFO_EXT MTK_M4U_ID(4, 1) +-#define M4U_PORT_L4_VDEC_PP_EXT MTK_M4U_ID(4, 2) +-#define M4U_PORT_L4_VDEC_PRED_RD_EXT MTK_M4U_ID(4, 3) +-#define M4U_PORT_L4_VDEC_PRED_WR_EXT MTK_M4U_ID(4, 4) +-#define M4U_PORT_L4_VDEC_PPWRAP_EXT MTK_M4U_ID(4, 5) +-#define M4U_PORT_L4_VDEC_TILE_EXT MTK_M4U_ID(4, 6) +-#define M4U_PORT_L4_VDEC_VLD_EXT MTK_M4U_ID(4, 7) +-#define M4U_PORT_L4_VDEC_VLD2_EXT MTK_M4U_ID(4, 8) +-#define M4U_PORT_L4_VDEC_AVC_MV_EXT MTK_M4U_ID(4, 9) +-#define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(4, 10) +- +-/* larb5 */ +-#define M4U_PORT_L5_VDEC_LAT0_VLD_EXT MTK_M4U_ID(5, 0) +-#define M4U_PORT_L5_VDEC_LAT0_VLD2_EXT MTK_M4U_ID(5, 1) +-#define M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT MTK_M4U_ID(5, 2) +-#define M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT MTK_M4U_ID(5, 3) +-#define M4U_PORT_L5_VDEC_LAT0_TILE_EXT MTK_M4U_ID(5, 4) +-#define M4U_PORT_L5_VDEC_LAT0_WDMA_EXT MTK_M4U_ID(5, 5) +-#define M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT MTK_M4U_ID(5, 6) +-#define M4U_PORT_L5_VDEC_UFO_ENC_EXT MTK_M4U_ID(5, 7) +- +-/* larb6: null */ +- +-/* larb7 */ +-#define M4U_PORT_L7_VENC_RCPU MTK_M4U_ID(7, 0) +-#define M4U_PORT_L7_VENC_REC MTK_M4U_ID(7, 1) +-#define M4U_PORT_L7_VENC_BSDMA MTK_M4U_ID(7, 2) +-#define M4U_PORT_L7_VENC_SV_COMV MTK_M4U_ID(7, 3) +-#define M4U_PORT_L7_VENC_RD_COMV MTK_M4U_ID(7, 4) +-#define M4U_PORT_L7_VENC_CUR_LUMA MTK_M4U_ID(7, 5) +-#define M4U_PORT_L7_VENC_CUR_CHROMA MTK_M4U_ID(7, 6) +-#define M4U_PORT_L7_VENC_REF_LUMA MTK_M4U_ID(7, 7) +-#define M4U_PORT_L7_VENC_REF_CHROMA MTK_M4U_ID(7, 8) +-#define M4U_PORT_L7_JPGENC_Y_RDMA MTK_M4U_ID(7, 9) +-#define M4U_PORT_L7_JPGENC_Q_RDMA MTK_M4U_ID(7, 10) +-#define M4U_PORT_L7_JPGENC_C_TABLE MTK_M4U_ID(7, 11) +-#define M4U_PORT_L7_JPGENC_BSDMA MTK_M4U_ID(7, 12) +-#define M4U_PORT_L7_VENC_SUB_R_LUMA MTK_M4U_ID(7, 13) +-#define M4U_PORT_L7_VENC_SUB_W_LUMA MTK_M4U_ID(7, 14) +- +-/* larb8: null */ +- +-/* larb9 */ +-#define M4U_PORT_L9_IMG_IMGI_D1 MTK_M4U_ID(9, 0) +-#define M4U_PORT_L9_IMG_IMGBI_D1 MTK_M4U_ID(9, 1) +-#define M4U_PORT_L9_IMG_DMGI_D1 MTK_M4U_ID(9, 2) +-#define M4U_PORT_L9_IMG_DEPI_D1 MTK_M4U_ID(9, 3) +-#define M4U_PORT_L9_IMG_ICE_D1 MTK_M4U_ID(9, 4) +-#define M4U_PORT_L9_IMG_SMTI_D1 MTK_M4U_ID(9, 5) +-#define M4U_PORT_L9_IMG_SMTO_D2 MTK_M4U_ID(9, 6) +-#define M4U_PORT_L9_IMG_SMTO_D1 MTK_M4U_ID(9, 7) +-#define M4U_PORT_L9_IMG_CRZO_D1 MTK_M4U_ID(9, 8) +-#define M4U_PORT_L9_IMG_IMG3O_D1 MTK_M4U_ID(9, 9) +-#define M4U_PORT_L9_IMG_VIPI_D1 MTK_M4U_ID(9, 10) +-#define M4U_PORT_L9_IMG_SMTI_D5 MTK_M4U_ID(9, 11) +-#define M4U_PORT_L9_IMG_TIMGO_D1 MTK_M4U_ID(9, 12) +-#define M4U_PORT_L9_IMG_UFBC_W0 MTK_M4U_ID(9, 13) +-#define M4U_PORT_L9_IMG_UFBC_R0 MTK_M4U_ID(9, 14) +- +-/* larb10: null */ +- +-/* larb11 */ +-#define M4U_PORT_L11_IMG_IMGI_D1 MTK_M4U_ID(11, 0) +-#define M4U_PORT_L11_IMG_IMGBI_D1 MTK_M4U_ID(11, 1) +-#define M4U_PORT_L11_IMG_DMGI_D1 MTK_M4U_ID(11, 2) +-#define M4U_PORT_L11_IMG_DEPI_D1 MTK_M4U_ID(11, 3) +-#define M4U_PORT_L11_IMG_ICE_D1 MTK_M4U_ID(11, 4) +-#define M4U_PORT_L11_IMG_SMTI_D1 MTK_M4U_ID(11, 5) +-#define M4U_PORT_L11_IMG_SMTO_D2 MTK_M4U_ID(11, 6) +-#define M4U_PORT_L11_IMG_SMTO_D1 MTK_M4U_ID(11, 7) +-#define M4U_PORT_L11_IMG_CRZO_D1 MTK_M4U_ID(11, 8) +-#define M4U_PORT_L11_IMG_IMG3O_D1 MTK_M4U_ID(11, 9) +-#define M4U_PORT_L11_IMG_VIPI_D1 MTK_M4U_ID(11, 10) +-#define M4U_PORT_L11_IMG_SMTI_D5 MTK_M4U_ID(11, 11) +-#define M4U_PORT_L11_IMG_TIMGO_D1 MTK_M4U_ID(11, 12) +-#define M4U_PORT_L11_IMG_UFBC_W0 MTK_M4U_ID(11, 13) +-#define M4U_PORT_L11_IMG_UFBC_R0 MTK_M4U_ID(11, 14) +-#define M4U_PORT_L11_IMG_WPE_RDMA1 MTK_M4U_ID(11, 15) +-#define M4U_PORT_L11_IMG_WPE_RDMA0 MTK_M4U_ID(11, 16) +-#define M4U_PORT_L11_IMG_WPE_WDMA MTK_M4U_ID(11, 17) +-#define M4U_PORT_L11_IMG_MFB_RDMA0 MTK_M4U_ID(11, 18) +-#define M4U_PORT_L11_IMG_MFB_RDMA1 MTK_M4U_ID(11, 19) +-#define M4U_PORT_L11_IMG_MFB_RDMA2 MTK_M4U_ID(11, 20) +-#define M4U_PORT_L11_IMG_MFB_RDMA3 MTK_M4U_ID(11, 21) +-#define M4U_PORT_L11_IMG_MFB_RDMA4 MTK_M4U_ID(11, 22) +-#define M4U_PORT_L11_IMG_MFB_RDMA5 MTK_M4U_ID(11, 23) +-#define M4U_PORT_L11_IMG_MFB_WDMA0 MTK_M4U_ID(11, 24) +-#define M4U_PORT_L11_IMG_MFB_WDMA1 MTK_M4U_ID(11, 25) +- +-/* larb12: null */ +- +-/* larb13 */ +-#define M4U_PORT_L13_CAM_MRAWI MTK_M4U_ID(13, 0) +-#define M4U_PORT_L13_CAM_MRAWO0 MTK_M4U_ID(13, 1) +-#define M4U_PORT_L13_CAM_MRAWO1 MTK_M4U_ID(13, 2) +-#define M4U_PORT_L13_CAM_CAMSV1 MTK_M4U_ID(13, 3) +-#define M4U_PORT_L13_CAM_CAMSV2 MTK_M4U_ID(13, 4) +-#define M4U_PORT_L13_CAM_CAMSV3 MTK_M4U_ID(13, 5) +-#define M4U_PORT_L13_CAM_CAMSV4 MTK_M4U_ID(13, 6) +-#define M4U_PORT_L13_CAM_CAMSV5 MTK_M4U_ID(13, 7) +-#define M4U_PORT_L13_CAM_CAMSV6 MTK_M4U_ID(13, 8) +-#define M4U_PORT_L13_CAM_CCUI MTK_M4U_ID(13, 9) +-#define M4U_PORT_L13_CAM_CCUO MTK_M4U_ID(13, 10) +-#define M4U_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 11) +- +-/* larb14 */ +-#define M4U_PORT_L14_CAM_RESERVE1 MTK_M4U_ID(14, 0) +-#define M4U_PORT_L14_CAM_RESERVE2 MTK_M4U_ID(14, 1) +-#define M4U_PORT_L14_CAM_RESERVE3 MTK_M4U_ID(14, 2) +-#define M4U_PORT_L14_CAM_CAMSV0 MTK_M4U_ID(14, 3) +-#define M4U_PORT_L14_CAM_CCUI MTK_M4U_ID(14, 4) +-#define M4U_PORT_L14_CAM_CCUO MTK_M4U_ID(14, 5) +- +-/* larb15: null */ +- +-/* larb16 */ +-#define M4U_PORT_L16_CAM_IMGO_R1_A MTK_M4U_ID(16, 0) +-#define M4U_PORT_L16_CAM_RRZO_R1_A MTK_M4U_ID(16, 1) +-#define M4U_PORT_L16_CAM_CQI_R1_A MTK_M4U_ID(16, 2) +-#define M4U_PORT_L16_CAM_BPCI_R1_A MTK_M4U_ID(16, 3) +-#define M4U_PORT_L16_CAM_YUVO_R1_A MTK_M4U_ID(16, 4) +-#define M4U_PORT_L16_CAM_UFDI_R2_A MTK_M4U_ID(16, 5) +-#define M4U_PORT_L16_CAM_RAWI_R2_A MTK_M4U_ID(16, 6) +-#define M4U_PORT_L16_CAM_RAWI_R3_A MTK_M4U_ID(16, 7) +-#define M4U_PORT_L16_CAM_AAO_R1_A MTK_M4U_ID(16, 8) +-#define M4U_PORT_L16_CAM_AFO_R1_A MTK_M4U_ID(16, 9) +-#define M4U_PORT_L16_CAM_FLKO_R1_A MTK_M4U_ID(16, 10) +-#define M4U_PORT_L16_CAM_LCESO_R1_A MTK_M4U_ID(16, 11) +-#define M4U_PORT_L16_CAM_CRZO_R1_A MTK_M4U_ID(16, 12) +-#define M4U_PORT_L16_CAM_LTMSO_R1_A MTK_M4U_ID(16, 13) +-#define M4U_PORT_L16_CAM_RSSO_R1_A MTK_M4U_ID(16, 14) +-#define M4U_PORT_L16_CAM_AAHO_R1_A MTK_M4U_ID(16, 15) +-#define M4U_PORT_L16_CAM_LSCI_R1_A MTK_M4U_ID(16, 16) +- +-/* larb17 */ +-#define M4U_PORT_L17_CAM_IMGO_R1_B MTK_M4U_ID(17, 0) +-#define M4U_PORT_L17_CAM_RRZO_R1_B MTK_M4U_ID(17, 1) +-#define M4U_PORT_L17_CAM_CQI_R1_B MTK_M4U_ID(17, 2) +-#define M4U_PORT_L17_CAM_BPCI_R1_B MTK_M4U_ID(17, 3) +-#define M4U_PORT_L17_CAM_YUVO_R1_B MTK_M4U_ID(17, 4) +-#define M4U_PORT_L17_CAM_UFDI_R2_B MTK_M4U_ID(17, 5) +-#define M4U_PORT_L17_CAM_RAWI_R2_B MTK_M4U_ID(17, 6) +-#define M4U_PORT_L17_CAM_RAWI_R3_B MTK_M4U_ID(17, 7) +-#define M4U_PORT_L17_CAM_AAO_R1_B MTK_M4U_ID(17, 8) +-#define M4U_PORT_L17_CAM_AFO_R1_B MTK_M4U_ID(17, 9) +-#define M4U_PORT_L17_CAM_FLKO_R1_B MTK_M4U_ID(17, 10) +-#define M4U_PORT_L17_CAM_LCESO_R1_B MTK_M4U_ID(17, 11) +-#define M4U_PORT_L17_CAM_CRZO_R1_B MTK_M4U_ID(17, 12) +-#define M4U_PORT_L17_CAM_LTMSO_R1_B MTK_M4U_ID(17, 13) +-#define M4U_PORT_L17_CAM_RSSO_R1_B MTK_M4U_ID(17, 14) +-#define M4U_PORT_L17_CAM_AAHO_R1_B MTK_M4U_ID(17, 15) +-#define M4U_PORT_L17_CAM_LSCI_R1_B MTK_M4U_ID(17, 16) +- +-/* larb18 */ +-#define M4U_PORT_L18_CAM_IMGO_R1_C MTK_M4U_ID(18, 0) +-#define M4U_PORT_L18_CAM_RRZO_R1_C MTK_M4U_ID(18, 1) +-#define M4U_PORT_L18_CAM_CQI_R1_C MTK_M4U_ID(18, 2) +-#define M4U_PORT_L18_CAM_BPCI_R1_C MTK_M4U_ID(18, 3) +-#define M4U_PORT_L18_CAM_YUVO_R1_C MTK_M4U_ID(18, 4) +-#define M4U_PORT_L18_CAM_UFDI_R2_C MTK_M4U_ID(18, 5) +-#define M4U_PORT_L18_CAM_RAWI_R2_C MTK_M4U_ID(18, 6) +-#define M4U_PORT_L18_CAM_RAWI_R3_C MTK_M4U_ID(18, 7) +-#define M4U_PORT_L18_CAM_AAO_R1_C MTK_M4U_ID(18, 8) +-#define M4U_PORT_L18_CAM_AFO_R1_C MTK_M4U_ID(18, 9) +-#define M4U_PORT_L18_CAM_FLKO_R1_C MTK_M4U_ID(18, 10) +-#define M4U_PORT_L18_CAM_LCESO_R1_C MTK_M4U_ID(18, 11) +-#define M4U_PORT_L18_CAM_CRZO_R1_C MTK_M4U_ID(18, 12) +-#define M4U_PORT_L18_CAM_LTMSO_R1_C MTK_M4U_ID(18, 13) +-#define M4U_PORT_L18_CAM_RSSO_R1_C MTK_M4U_ID(18, 14) +-#define M4U_PORT_L18_CAM_AAHO_R1_C MTK_M4U_ID(18, 15) +-#define M4U_PORT_L18_CAM_LSCI_R1_C MTK_M4U_ID(18, 16) +- +-/* larb19 */ +-#define M4U_PORT_L19_IPE_DVS_RDMA MTK_M4U_ID(19, 0) +-#define M4U_PORT_L19_IPE_DVS_WDMA MTK_M4U_ID(19, 1) +-#define M4U_PORT_L19_IPE_DVP_RDMA MTK_M4U_ID(19, 2) +-#define M4U_PORT_L19_IPE_DVP_WDMA MTK_M4U_ID(19, 3) +- +-/* larb20 */ +-#define M4U_PORT_L20_IPE_FDVT_RDA MTK_M4U_ID(20, 0) +-#define M4U_PORT_L20_IPE_FDVT_RDB MTK_M4U_ID(20, 1) +-#define M4U_PORT_L20_IPE_FDVT_WRA MTK_M4U_ID(20, 2) +-#define M4U_PORT_L20_IPE_FDVT_WRB MTK_M4U_ID(20, 3) +-#define M4U_PORT_L20_IPE_RSC_RDMA0 MTK_M4U_ID(20, 4) +-#define M4U_PORT_L20_IPE_RSC_WDMA MTK_M4U_ID(20, 5) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/memory/mtk-memory-port.h b/scripts/dtc/include-prefixes/dt-bindings/memory/mtk-memory-port.h +deleted file mode 100644 +index 7d64103209af..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/memory/mtk-memory-port.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2020 MediaTek Inc. +- * Author: Yong Wu +- */ +-#ifndef __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_ +-#define __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_ +- +-#define MTK_LARB_NR_MAX 32 +- +-#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) +-#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x1f) +-#define MTK_M4U_TO_PORT(id) ((id) & 0x1f) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/memory/tegra114-mc.h b/scripts/dtc/include-prefixes/dt-bindings/memory/tegra114-mc.h +deleted file mode 100644 +index dfe99c8a5ba5..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/memory/tegra114-mc.h ++++ /dev/null +@@ -1,43 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H +-#define DT_BINDINGS_MEMORY_TEGRA114_MC_H +- +-#define TEGRA_SWGROUP_PTC 0 +-#define TEGRA_SWGROUP_DC 1 +-#define TEGRA_SWGROUP_DCB 2 +-#define TEGRA_SWGROUP_EPP 3 +-#define TEGRA_SWGROUP_G2 4 +-#define TEGRA_SWGROUP_AVPC 5 +-#define TEGRA_SWGROUP_NV 6 +-#define TEGRA_SWGROUP_HDA 7 +-#define TEGRA_SWGROUP_HC 8 +-#define TEGRA_SWGROUP_MSENC 9 +-#define TEGRA_SWGROUP_PPCS 10 +-#define TEGRA_SWGROUP_VDE 11 +-#define TEGRA_SWGROUP_MPCORELP 12 +-#define TEGRA_SWGROUP_MPCORE 13 +-#define TEGRA_SWGROUP_VI 14 +-#define TEGRA_SWGROUP_ISP 15 +-#define TEGRA_SWGROUP_XUSB_HOST 16 +-#define TEGRA_SWGROUP_XUSB_DEV 17 +-#define TEGRA_SWGROUP_EMUCIF 18 +-#define TEGRA_SWGROUP_TSEC 19 +- +-#define TEGRA114_MC_RESET_AVPC 0 +-#define TEGRA114_MC_RESET_DC 1 +-#define TEGRA114_MC_RESET_DCB 2 +-#define TEGRA114_MC_RESET_EPP 3 +-#define TEGRA114_MC_RESET_2D 4 +-#define TEGRA114_MC_RESET_HC 5 +-#define TEGRA114_MC_RESET_HDA 6 +-#define TEGRA114_MC_RESET_ISP 7 +-#define TEGRA114_MC_RESET_MPCORE 8 +-#define TEGRA114_MC_RESET_MPCORELP 9 +-#define TEGRA114_MC_RESET_MPE 10 +-#define TEGRA114_MC_RESET_3D 11 +-#define TEGRA114_MC_RESET_3D2 12 +-#define TEGRA114_MC_RESET_PPCS 13 +-#define TEGRA114_MC_RESET_VDE 14 +-#define TEGRA114_MC_RESET_VI 15 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/memory/tegra124-mc.h b/scripts/dtc/include-prefixes/dt-bindings/memory/tegra124-mc.h +deleted file mode 100644 +index 7e73bb400eca..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/memory/tegra124-mc.h ++++ /dev/null +@@ -1,125 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H +-#define DT_BINDINGS_MEMORY_TEGRA124_MC_H +- +-#define TEGRA_SWGROUP_PTC 0 +-#define TEGRA_SWGROUP_DC 1 +-#define TEGRA_SWGROUP_DCB 2 +-#define TEGRA_SWGROUP_AFI 3 +-#define TEGRA_SWGROUP_AVPC 4 +-#define TEGRA_SWGROUP_HDA 5 +-#define TEGRA_SWGROUP_HC 6 +-#define TEGRA_SWGROUP_MSENC 7 +-#define TEGRA_SWGROUP_PPCS 8 +-#define TEGRA_SWGROUP_SATA 9 +-#define TEGRA_SWGROUP_VDE 10 +-#define TEGRA_SWGROUP_MPCORELP 11 +-#define TEGRA_SWGROUP_MPCORE 12 +-#define TEGRA_SWGROUP_ISP2 13 +-#define TEGRA_SWGROUP_XUSB_HOST 14 +-#define TEGRA_SWGROUP_XUSB_DEV 15 +-#define TEGRA_SWGROUP_ISP2B 16 +-#define TEGRA_SWGROUP_TSEC 17 +-#define TEGRA_SWGROUP_A9AVP 18 +-#define TEGRA_SWGROUP_GPU 19 +-#define TEGRA_SWGROUP_SDMMC1A 20 +-#define TEGRA_SWGROUP_SDMMC2A 21 +-#define TEGRA_SWGROUP_SDMMC3A 22 +-#define TEGRA_SWGROUP_SDMMC4A 23 +-#define TEGRA_SWGROUP_VIC 24 +-#define TEGRA_SWGROUP_VI 25 +- +-#define TEGRA124_MC_RESET_AFI 0 +-#define TEGRA124_MC_RESET_AVPC 1 +-#define TEGRA124_MC_RESET_DC 2 +-#define TEGRA124_MC_RESET_DCB 3 +-#define TEGRA124_MC_RESET_HC 4 +-#define TEGRA124_MC_RESET_HDA 5 +-#define TEGRA124_MC_RESET_ISP2 6 +-#define TEGRA124_MC_RESET_MPCORE 7 +-#define TEGRA124_MC_RESET_MPCORELP 8 +-#define TEGRA124_MC_RESET_MSENC 9 +-#define TEGRA124_MC_RESET_PPCS 10 +-#define TEGRA124_MC_RESET_SATA 11 +-#define TEGRA124_MC_RESET_VDE 12 +-#define TEGRA124_MC_RESET_VI 13 +-#define TEGRA124_MC_RESET_VIC 14 +-#define TEGRA124_MC_RESET_XUSB_HOST 15 +-#define TEGRA124_MC_RESET_XUSB_DEV 16 +-#define TEGRA124_MC_RESET_TSEC 17 +-#define TEGRA124_MC_RESET_SDMMC1 18 +-#define TEGRA124_MC_RESET_SDMMC2 19 +-#define TEGRA124_MC_RESET_SDMMC3 20 +-#define TEGRA124_MC_RESET_SDMMC4 21 +-#define TEGRA124_MC_RESET_ISP2B 22 +-#define TEGRA124_MC_RESET_GPU 23 +- +-#define TEGRA124_MC_PTCR 0 +-#define TEGRA124_MC_DISPLAY0A 1 +-#define TEGRA124_MC_DISPLAY0AB 2 +-#define TEGRA124_MC_DISPLAY0B 3 +-#define TEGRA124_MC_DISPLAY0BB 4 +-#define TEGRA124_MC_DISPLAY0C 5 +-#define TEGRA124_MC_DISPLAY0CB 6 +-#define TEGRA124_MC_AFIR 14 +-#define TEGRA124_MC_AVPCARM7R 15 +-#define TEGRA124_MC_DISPLAYHC 16 +-#define TEGRA124_MC_DISPLAYHCB 17 +-#define TEGRA124_MC_HDAR 21 +-#define TEGRA124_MC_HOST1XDMAR 22 +-#define TEGRA124_MC_HOST1XR 23 +-#define TEGRA124_MC_MSENCSRD 28 +-#define TEGRA124_MC_PPCSAHBDMAR 29 +-#define TEGRA124_MC_PPCSAHBSLVR 30 +-#define TEGRA124_MC_SATAR 31 +-#define TEGRA124_MC_VDEBSEVR 34 +-#define TEGRA124_MC_VDEMBER 35 +-#define TEGRA124_MC_VDEMCER 36 +-#define TEGRA124_MC_VDETPER 37 +-#define TEGRA124_MC_MPCORELPR 38 +-#define TEGRA124_MC_MPCORER 39 +-#define TEGRA124_MC_MSENCSWR 43 +-#define TEGRA124_MC_AFIW 49 +-#define TEGRA124_MC_AVPCARM7W 50 +-#define TEGRA124_MC_HDAW 53 +-#define TEGRA124_MC_HOST1XW 54 +-#define TEGRA124_MC_MPCORELPW 56 +-#define TEGRA124_MC_MPCOREW 57 +-#define TEGRA124_MC_PPCSAHBDMAW 59 +-#define TEGRA124_MC_PPCSAHBSLVW 60 +-#define TEGRA124_MC_SATAW 61 +-#define TEGRA124_MC_VDEBSEVW 62 +-#define TEGRA124_MC_VDEDBGW 63 +-#define TEGRA124_MC_VDEMBEW 64 +-#define TEGRA124_MC_VDETPMW 65 +-#define TEGRA124_MC_ISPRA 68 +-#define TEGRA124_MC_ISPWA 70 +-#define TEGRA124_MC_ISPWB 71 +-#define TEGRA124_MC_XUSB_HOSTR 74 +-#define TEGRA124_MC_XUSB_HOSTW 75 +-#define TEGRA124_MC_XUSB_DEVR 76 +-#define TEGRA124_MC_XUSB_DEVW 77 +-#define TEGRA124_MC_ISPRAB 78 +-#define TEGRA124_MC_ISPWAB 80 +-#define TEGRA124_MC_ISPWBB 81 +-#define TEGRA124_MC_TSECSRD 84 +-#define TEGRA124_MC_TSECSWR 85 +-#define TEGRA124_MC_A9AVPSCR 86 +-#define TEGRA124_MC_A9AVPSCW 87 +-#define TEGRA124_MC_GPUSRD 88 +-#define TEGRA124_MC_GPUSWR 89 +-#define TEGRA124_MC_DISPLAYT 90 +-#define TEGRA124_MC_SDMMCRA 96 +-#define TEGRA124_MC_SDMMCRAA 97 +-#define TEGRA124_MC_SDMMCR 98 +-#define TEGRA124_MC_SDMMCRAB 99 +-#define TEGRA124_MC_SDMMCWA 100 +-#define TEGRA124_MC_SDMMCWAA 101 +-#define TEGRA124_MC_SDMMCW 102 +-#define TEGRA124_MC_SDMMCWAB 103 +-#define TEGRA124_MC_VICSRD 108 +-#define TEGRA124_MC_VICSWR 109 +-#define TEGRA124_MC_VIW 114 +-#define TEGRA124_MC_DISPLAYD 115 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/memory/tegra186-mc.h b/scripts/dtc/include-prefixes/dt-bindings/memory/tegra186-mc.h +deleted file mode 100644 +index 82a1e27f7357..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/memory/tegra186-mc.h ++++ /dev/null +@@ -1,250 +0,0 @@ +-#ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H +-#define DT_BINDINGS_MEMORY_TEGRA186_MC_H +- +-/* special clients */ +-#define TEGRA186_SID_INVALID 0x00 +-#define TEGRA186_SID_PASSTHROUGH 0x7f +- +-/* host1x clients */ +-#define TEGRA186_SID_HOST1X 0x01 +-#define TEGRA186_SID_CSI 0x02 +-#define TEGRA186_SID_VIC 0x03 +-#define TEGRA186_SID_VI 0x04 +-#define TEGRA186_SID_ISP 0x05 +-#define TEGRA186_SID_NVDEC 0x06 +-#define TEGRA186_SID_NVENC 0x07 +-#define TEGRA186_SID_NVJPG 0x08 +-#define TEGRA186_SID_NVDISPLAY 0x09 +-#define TEGRA186_SID_TSEC 0x0a +-#define TEGRA186_SID_TSECB 0x0b +-#define TEGRA186_SID_SE 0x0c +-#define TEGRA186_SID_SE1 0x0d +-#define TEGRA186_SID_SE2 0x0e +-#define TEGRA186_SID_SE3 0x0f +- +-/* GPU clients */ +-#define TEGRA186_SID_GPU 0x10 +- +-/* other SoC clients */ +-#define TEGRA186_SID_AFI 0x11 +-#define TEGRA186_SID_HDA 0x12 +-#define TEGRA186_SID_ETR 0x13 +-#define TEGRA186_SID_EQOS 0x14 +-#define TEGRA186_SID_UFSHC 0x15 +-#define TEGRA186_SID_AON 0x16 +-#define TEGRA186_SID_SDMMC4 0x17 +-#define TEGRA186_SID_SDMMC3 0x18 +-#define TEGRA186_SID_SDMMC2 0x19 +-#define TEGRA186_SID_SDMMC1 0x1a +-#define TEGRA186_SID_XUSB_HOST 0x1b +-#define TEGRA186_SID_XUSB_DEV 0x1c +-#define TEGRA186_SID_SATA 0x1d +-#define TEGRA186_SID_APE 0x1e +-#define TEGRA186_SID_SCE 0x1f +- +-/* GPC DMA clients */ +-#define TEGRA186_SID_GPCDMA_0 0x20 +-#define TEGRA186_SID_GPCDMA_1 0x21 +-#define TEGRA186_SID_GPCDMA_2 0x22 +-#define TEGRA186_SID_GPCDMA_3 0x23 +-#define TEGRA186_SID_GPCDMA_4 0x24 +-#define TEGRA186_SID_GPCDMA_5 0x25 +-#define TEGRA186_SID_GPCDMA_6 0x26 +-#define TEGRA186_SID_GPCDMA_7 0x27 +- +-/* APE DMA clients */ +-#define TEGRA186_SID_APE_1 0x28 +-#define TEGRA186_SID_APE_2 0x29 +- +-/* camera RTCPU */ +-#define TEGRA186_SID_RCE 0x2a +- +-/* camera RTCPU on host1x address space */ +-#define TEGRA186_SID_RCE_1X 0x2b +- +-/* APE DMA clients */ +-#define TEGRA186_SID_APE_3 0x2c +- +-/* camera RTCPU running on APE */ +-#define TEGRA186_SID_APE_CAM 0x2d +-#define TEGRA186_SID_APE_CAM_1X 0x2e +- +-/* +- * The BPMP has its SID value hardcoded in the firmware. Changing it requires +- * considerable effort. +- */ +-#define TEGRA186_SID_BPMP 0x32 +- +-/* for SMMU tests */ +-#define TEGRA186_SID_SMMU_TEST 0x33 +- +-/* host1x virtualization channels */ +-#define TEGRA186_SID_HOST1X_CTX0 0x38 +-#define TEGRA186_SID_HOST1X_CTX1 0x39 +-#define TEGRA186_SID_HOST1X_CTX2 0x3a +-#define TEGRA186_SID_HOST1X_CTX3 0x3b +-#define TEGRA186_SID_HOST1X_CTX4 0x3c +-#define TEGRA186_SID_HOST1X_CTX5 0x3d +-#define TEGRA186_SID_HOST1X_CTX6 0x3e +-#define TEGRA186_SID_HOST1X_CTX7 0x3f +- +-/* host1x command buffers */ +-#define TEGRA186_SID_HOST1X_VM0 0x40 +-#define TEGRA186_SID_HOST1X_VM1 0x41 +-#define TEGRA186_SID_HOST1X_VM2 0x42 +-#define TEGRA186_SID_HOST1X_VM3 0x43 +-#define TEGRA186_SID_HOST1X_VM4 0x44 +-#define TEGRA186_SID_HOST1X_VM5 0x45 +-#define TEGRA186_SID_HOST1X_VM6 0x46 +-#define TEGRA186_SID_HOST1X_VM7 0x47 +- +-/* SE data buffers */ +-#define TEGRA186_SID_SE_VM0 0x48 +-#define TEGRA186_SID_SE_VM1 0x49 +-#define TEGRA186_SID_SE_VM2 0x4a +-#define TEGRA186_SID_SE_VM3 0x4b +-#define TEGRA186_SID_SE_VM4 0x4c +-#define TEGRA186_SID_SE_VM5 0x4d +-#define TEGRA186_SID_SE_VM6 0x4e +-#define TEGRA186_SID_SE_VM7 0x4f +- +-/* +- * memory client IDs +- */ +- +-/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ +-#define TEGRA186_MEMORY_CLIENT_PTCR 0x00 +-/* PCIE reads */ +-#define TEGRA186_MEMORY_CLIENT_AFIR 0x0e +-/* High-definition audio (HDA) reads */ +-#define TEGRA186_MEMORY_CLIENT_HDAR 0x15 +-/* Host channel data reads */ +-#define TEGRA186_MEMORY_CLIENT_HOST1XDMAR 0x16 +-#define TEGRA186_MEMORY_CLIENT_NVENCSRD 0x1c +-/* SATA reads */ +-#define TEGRA186_MEMORY_CLIENT_SATAR 0x1f +-/* Reads from Cortex-A9 4 CPU cores via the L2 cache */ +-#define TEGRA186_MEMORY_CLIENT_MPCORER 0x27 +-#define TEGRA186_MEMORY_CLIENT_NVENCSWR 0x2b +-/* PCIE writes */ +-#define TEGRA186_MEMORY_CLIENT_AFIW 0x31 +-/* High-definition audio (HDA) writes */ +-#define TEGRA186_MEMORY_CLIENT_HDAW 0x35 +-/* Writes from Cortex-A9 4 CPU cores via the L2 cache */ +-#define TEGRA186_MEMORY_CLIENT_MPCOREW 0x39 +-/* SATA writes */ +-#define TEGRA186_MEMORY_CLIENT_SATAW 0x3d +-/* ISP Read client for Crossbar A */ +-#define TEGRA186_MEMORY_CLIENT_ISPRA 0x44 +-/* ISP Write client for Crossbar A */ +-#define TEGRA186_MEMORY_CLIENT_ISPWA 0x46 +-/* ISP Write client Crossbar B */ +-#define TEGRA186_MEMORY_CLIENT_ISPWB 0x47 +-/* XUSB reads */ +-#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTR 0x4a +-/* XUSB_HOST writes */ +-#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTW 0x4b +-/* XUSB reads */ +-#define TEGRA186_MEMORY_CLIENT_XUSB_DEVR 0x4c +-/* XUSB_DEV writes */ +-#define TEGRA186_MEMORY_CLIENT_XUSB_DEVW 0x4d +-/* TSEC Memory Return Data Client Description */ +-#define TEGRA186_MEMORY_CLIENT_TSECSRD 0x54 +-/* TSEC Memory Write Client Description */ +-#define TEGRA186_MEMORY_CLIENT_TSECSWR 0x55 +-/* 3D, ltcx reads instance 0 */ +-#define TEGRA186_MEMORY_CLIENT_GPUSRD 0x58 +-/* 3D, ltcx writes instance 0 */ +-#define TEGRA186_MEMORY_CLIENT_GPUSWR 0x59 +-/* sdmmca memory read client */ +-#define TEGRA186_MEMORY_CLIENT_SDMMCRA 0x60 +-/* sdmmcbmemory read client */ +-#define TEGRA186_MEMORY_CLIENT_SDMMCRAA 0x61 +-/* sdmmc memory read client */ +-#define TEGRA186_MEMORY_CLIENT_SDMMCR 0x62 +-/* sdmmcd memory read client */ +-#define TEGRA186_MEMORY_CLIENT_SDMMCRAB 0x63 +-/* sdmmca memory write client */ +-#define TEGRA186_MEMORY_CLIENT_SDMMCWA 0x64 +-/* sdmmcb memory write client */ +-#define TEGRA186_MEMORY_CLIENT_SDMMCWAA 0x65 +-/* sdmmc memory write client */ +-#define TEGRA186_MEMORY_CLIENT_SDMMCW 0x66 +-/* sdmmcd memory write client */ +-#define TEGRA186_MEMORY_CLIENT_SDMMCWAB 0x67 +-#define TEGRA186_MEMORY_CLIENT_VICSRD 0x6c +-#define TEGRA186_MEMORY_CLIENT_VICSWR 0x6d +-/* VI Write client */ +-#define TEGRA186_MEMORY_CLIENT_VIW 0x72 +-#define TEGRA186_MEMORY_CLIENT_NVDECSRD 0x78 +-#define TEGRA186_MEMORY_CLIENT_NVDECSWR 0x79 +-/* Audio Processing (APE) engine reads */ +-#define TEGRA186_MEMORY_CLIENT_APER 0x7a +-/* Audio Processing (APE) engine writes */ +-#define TEGRA186_MEMORY_CLIENT_APEW 0x7b +-#define TEGRA186_MEMORY_CLIENT_NVJPGSRD 0x7e +-#define TEGRA186_MEMORY_CLIENT_NVJPGSWR 0x7f +-/* SE Memory Return Data Client Description */ +-#define TEGRA186_MEMORY_CLIENT_SESRD 0x80 +-/* SE Memory Write Client Description */ +-#define TEGRA186_MEMORY_CLIENT_SESWR 0x81 +-/* ETR reads */ +-#define TEGRA186_MEMORY_CLIENT_ETRR 0x84 +-/* ETR writes */ +-#define TEGRA186_MEMORY_CLIENT_ETRW 0x85 +-/* TSECB Memory Return Data Client Description */ +-#define TEGRA186_MEMORY_CLIENT_TSECSRDB 0x86 +-/* TSECB Memory Write Client Description */ +-#define TEGRA186_MEMORY_CLIENT_TSECSWRB 0x87 +-/* 3D, ltcx reads instance 1 */ +-#define TEGRA186_MEMORY_CLIENT_GPUSRD2 0x88 +-/* 3D, ltcx writes instance 1 */ +-#define TEGRA186_MEMORY_CLIENT_GPUSWR2 0x89 +-/* AXI Switch read client */ +-#define TEGRA186_MEMORY_CLIENT_AXISR 0x8c +-/* AXI Switch write client */ +-#define TEGRA186_MEMORY_CLIENT_AXISW 0x8d +-/* EQOS read client */ +-#define TEGRA186_MEMORY_CLIENT_EQOSR 0x8e +-/* EQOS write client */ +-#define TEGRA186_MEMORY_CLIENT_EQOSW 0x8f +-/* UFSHC read client */ +-#define TEGRA186_MEMORY_CLIENT_UFSHCR 0x90 +-/* UFSHC write client */ +-#define TEGRA186_MEMORY_CLIENT_UFSHCW 0x91 +-/* NVDISPLAY read client */ +-#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR 0x92 +-/* BPMP read client */ +-#define TEGRA186_MEMORY_CLIENT_BPMPR 0x93 +-/* BPMP write client */ +-#define TEGRA186_MEMORY_CLIENT_BPMPW 0x94 +-/* BPMPDMA read client */ +-#define TEGRA186_MEMORY_CLIENT_BPMPDMAR 0x95 +-/* BPMPDMA write client */ +-#define TEGRA186_MEMORY_CLIENT_BPMPDMAW 0x96 +-/* AON read client */ +-#define TEGRA186_MEMORY_CLIENT_AONR 0x97 +-/* AON write client */ +-#define TEGRA186_MEMORY_CLIENT_AONW 0x98 +-/* AONDMA read client */ +-#define TEGRA186_MEMORY_CLIENT_AONDMAR 0x99 +-/* AONDMA write client */ +-#define TEGRA186_MEMORY_CLIENT_AONDMAW 0x9a +-/* SCE read client */ +-#define TEGRA186_MEMORY_CLIENT_SCER 0x9b +-/* SCE write client */ +-#define TEGRA186_MEMORY_CLIENT_SCEW 0x9c +-/* SCEDMA read client */ +-#define TEGRA186_MEMORY_CLIENT_SCEDMAR 0x9d +-/* SCEDMA write client */ +-#define TEGRA186_MEMORY_CLIENT_SCEDMAW 0x9e +-/* APEDMA read client */ +-#define TEGRA186_MEMORY_CLIENT_APEDMAR 0x9f +-/* APEDMA write client */ +-#define TEGRA186_MEMORY_CLIENT_APEDMAW 0xa0 +-/* NVDISPLAY read client instance 2 */ +-#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 0xa1 +-#define TEGRA186_MEMORY_CLIENT_VICSRD1 0xa2 +-#define TEGRA186_MEMORY_CLIENT_NVDECSRD1 0xa3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/memory/tegra194-mc.h b/scripts/dtc/include-prefixes/dt-bindings/memory/tegra194-mc.h +deleted file mode 100644 +index eed48b746bc9..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/memory/tegra194-mc.h ++++ /dev/null +@@ -1,410 +0,0 @@ +-#ifndef DT_BINDINGS_MEMORY_TEGRA194_MC_H +-#define DT_BINDINGS_MEMORY_TEGRA194_MC_H +- +-/* special clients */ +-#define TEGRA194_SID_INVALID 0x00 +-#define TEGRA194_SID_PASSTHROUGH 0x7f +- +-/* host1x clients */ +-#define TEGRA194_SID_HOST1X 0x01 +-#define TEGRA194_SID_CSI 0x02 +-#define TEGRA194_SID_VIC 0x03 +-#define TEGRA194_SID_VI 0x04 +-#define TEGRA194_SID_ISP 0x05 +-#define TEGRA194_SID_NVDEC 0x06 +-#define TEGRA194_SID_NVENC 0x07 +-#define TEGRA194_SID_NVJPG 0x08 +-#define TEGRA194_SID_NVDISPLAY 0x09 +-#define TEGRA194_SID_TSEC 0x0a +-#define TEGRA194_SID_TSECB 0x0b +-#define TEGRA194_SID_SE 0x0c +-#define TEGRA194_SID_SE1 0x0d +-#define TEGRA194_SID_SE2 0x0e +-#define TEGRA194_SID_SE3 0x0f +- +-/* GPU clients */ +-#define TEGRA194_SID_GPU 0x10 +- +-/* other SoC clients */ +-#define TEGRA194_SID_AFI 0x11 +-#define TEGRA194_SID_HDA 0x12 +-#define TEGRA194_SID_ETR 0x13 +-#define TEGRA194_SID_EQOS 0x14 +-#define TEGRA194_SID_UFSHC 0x15 +-#define TEGRA194_SID_AON 0x16 +-#define TEGRA194_SID_SDMMC4 0x17 +-#define TEGRA194_SID_SDMMC3 0x18 +-#define TEGRA194_SID_SDMMC2 0x19 +-#define TEGRA194_SID_SDMMC1 0x1a +-#define TEGRA194_SID_XUSB_HOST 0x1b +-#define TEGRA194_SID_XUSB_DEV 0x1c +-#define TEGRA194_SID_SATA 0x1d +-#define TEGRA194_SID_APE 0x1e +-#define TEGRA194_SID_SCE 0x1f +- +-/* GPC DMA clients */ +-#define TEGRA194_SID_GPCDMA_0 0x20 +-#define TEGRA194_SID_GPCDMA_1 0x21 +-#define TEGRA194_SID_GPCDMA_2 0x22 +-#define TEGRA194_SID_GPCDMA_3 0x23 +-#define TEGRA194_SID_GPCDMA_4 0x24 +-#define TEGRA194_SID_GPCDMA_5 0x25 +-#define TEGRA194_SID_GPCDMA_6 0x26 +-#define TEGRA194_SID_GPCDMA_7 0x27 +- +-/* APE DMA clients */ +-#define TEGRA194_SID_APE_1 0x28 +-#define TEGRA194_SID_APE_2 0x29 +- +-/* camera RTCPU */ +-#define TEGRA194_SID_RCE 0x2a +- +-/* camera RTCPU on host1x address space */ +-#define TEGRA194_SID_RCE_1X 0x2b +- +-/* APE DMA clients */ +-#define TEGRA194_SID_APE_3 0x2c +- +-/* camera RTCPU running on APE */ +-#define TEGRA194_SID_APE_CAM 0x2d +-#define TEGRA194_SID_APE_CAM_1X 0x2e +- +-#define TEGRA194_SID_RCE_RM 0x2f +-#define TEGRA194_SID_VI_FALCON 0x30 +-#define TEGRA194_SID_ISP_FALCON 0x31 +- +-/* +- * The BPMP has its SID value hardcoded in the firmware. Changing it requires +- * considerable effort. +- */ +-#define TEGRA194_SID_BPMP 0x32 +- +-/* for SMMU tests */ +-#define TEGRA194_SID_SMMU_TEST 0x33 +- +-/* host1x virtualization channels */ +-#define TEGRA194_SID_HOST1X_CTX0 0x38 +-#define TEGRA194_SID_HOST1X_CTX1 0x39 +-#define TEGRA194_SID_HOST1X_CTX2 0x3a +-#define TEGRA194_SID_HOST1X_CTX3 0x3b +-#define TEGRA194_SID_HOST1X_CTX4 0x3c +-#define TEGRA194_SID_HOST1X_CTX5 0x3d +-#define TEGRA194_SID_HOST1X_CTX6 0x3e +-#define TEGRA194_SID_HOST1X_CTX7 0x3f +- +-/* host1x command buffers */ +-#define TEGRA194_SID_HOST1X_VM0 0x40 +-#define TEGRA194_SID_HOST1X_VM1 0x41 +-#define TEGRA194_SID_HOST1X_VM2 0x42 +-#define TEGRA194_SID_HOST1X_VM3 0x43 +-#define TEGRA194_SID_HOST1X_VM4 0x44 +-#define TEGRA194_SID_HOST1X_VM5 0x45 +-#define TEGRA194_SID_HOST1X_VM6 0x46 +-#define TEGRA194_SID_HOST1X_VM7 0x47 +- +-/* SE data buffers */ +-#define TEGRA194_SID_SE_VM0 0x48 +-#define TEGRA194_SID_SE_VM1 0x49 +-#define TEGRA194_SID_SE_VM2 0x4a +-#define TEGRA194_SID_SE_VM3 0x4b +-#define TEGRA194_SID_SE_VM4 0x4c +-#define TEGRA194_SID_SE_VM5 0x4d +-#define TEGRA194_SID_SE_VM6 0x4e +-#define TEGRA194_SID_SE_VM7 0x4f +- +-#define TEGRA194_SID_MIU 0x50 +- +-#define TEGRA194_SID_NVDLA0 0x51 +-#define TEGRA194_SID_NVDLA1 0x52 +- +-#define TEGRA194_SID_PVA0 0x53 +-#define TEGRA194_SID_PVA1 0x54 +-#define TEGRA194_SID_NVENC1 0x55 +-#define TEGRA194_SID_PCIE0 0x56 +-#define TEGRA194_SID_PCIE1 0x57 +-#define TEGRA194_SID_PCIE2 0x58 +-#define TEGRA194_SID_PCIE3 0x59 +-#define TEGRA194_SID_PCIE4 0x5a +-#define TEGRA194_SID_PCIE5 0x5b +-#define TEGRA194_SID_NVDEC1 0x5c +- +-#define TEGRA194_SID_XUSB_VF0 0x5d +-#define TEGRA194_SID_XUSB_VF1 0x5e +-#define TEGRA194_SID_XUSB_VF2 0x5f +-#define TEGRA194_SID_XUSB_VF3 0x60 +- +-#define TEGRA194_SID_RCE_VM3 0x61 +-#define TEGRA194_SID_VI_VM2 0x62 +-#define TEGRA194_SID_VI_VM3 0x63 +-#define TEGRA194_SID_RCE_SERVER 0x64 +- +-/* +- * memory client IDs +- */ +- +-/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ +-#define TEGRA194_MEMORY_CLIENT_PTCR 0x00 +-/* MSS internal memqual MIU7 read clients */ +-#define TEGRA194_MEMORY_CLIENT_MIU7R 0x01 +-/* MSS internal memqual MIU7 write clients */ +-#define TEGRA194_MEMORY_CLIENT_MIU7W 0x02 +-/* High-definition audio (HDA) read clients */ +-#define TEGRA194_MEMORY_CLIENT_HDAR 0x15 +-/* Host channel data read clients */ +-#define TEGRA194_MEMORY_CLIENT_HOST1XDMAR 0x16 +-#define TEGRA194_MEMORY_CLIENT_NVENCSRD 0x1c +-/* SATA read clients */ +-#define TEGRA194_MEMORY_CLIENT_SATAR 0x1f +-/* Reads from Cortex-A9 4 CPU cores via the L2 cache */ +-#define TEGRA194_MEMORY_CLIENT_MPCORER 0x27 +-#define TEGRA194_MEMORY_CLIENT_NVENCSWR 0x2b +-/* High-definition audio (HDA) write clients */ +-#define TEGRA194_MEMORY_CLIENT_HDAW 0x35 +-/* Writes from Cortex-A9 4 CPU cores via the L2 cache */ +-#define TEGRA194_MEMORY_CLIENT_MPCOREW 0x39 +-/* SATA write clients */ +-#define TEGRA194_MEMORY_CLIENT_SATAW 0x3d +-/* ISP read client for Crossbar A */ +-#define TEGRA194_MEMORY_CLIENT_ISPRA 0x44 +-/* ISP read client 1 for Crossbar A */ +-#define TEGRA194_MEMORY_CLIENT_ISPFALR 0x45 +-/* ISP Write client for Crossbar A */ +-#define TEGRA194_MEMORY_CLIENT_ISPWA 0x46 +-/* ISP Write client Crossbar B */ +-#define TEGRA194_MEMORY_CLIENT_ISPWB 0x47 +-/* XUSB_HOST read clients */ +-#define TEGRA194_MEMORY_CLIENT_XUSB_HOSTR 0x4a +-/* XUSB_HOST write clients */ +-#define TEGRA194_MEMORY_CLIENT_XUSB_HOSTW 0x4b +-/* XUSB read clients */ +-#define TEGRA194_MEMORY_CLIENT_XUSB_DEVR 0x4c +-/* XUSB_DEV write clients */ +-#define TEGRA194_MEMORY_CLIENT_XUSB_DEVW 0x4d +-/* sdmmca memory read client */ +-#define TEGRA194_MEMORY_CLIENT_SDMMCRA 0x60 +-/* sdmmc memory read client */ +-#define TEGRA194_MEMORY_CLIENT_SDMMCR 0x62 +-/* sdmmcd memory read client */ +-#define TEGRA194_MEMORY_CLIENT_SDMMCRAB 0x63 +-/* sdmmca memory write client */ +-#define TEGRA194_MEMORY_CLIENT_SDMMCWA 0x64 +-/* sdmmc memory write client */ +-#define TEGRA194_MEMORY_CLIENT_SDMMCW 0x66 +-/* sdmmcd memory write client */ +-#define TEGRA194_MEMORY_CLIENT_SDMMCWAB 0x67 +-#define TEGRA194_MEMORY_CLIENT_VICSRD 0x6c +-#define TEGRA194_MEMORY_CLIENT_VICSWR 0x6d +-/* VI Write client */ +-#define TEGRA194_MEMORY_CLIENT_VIW 0x72 +-#define TEGRA194_MEMORY_CLIENT_NVDECSRD 0x78 +-#define TEGRA194_MEMORY_CLIENT_NVDECSWR 0x79 +-/* Audio Processing (APE) engine read clients */ +-#define TEGRA194_MEMORY_CLIENT_APER 0x7a +-/* Audio Processing (APE) engine write clients */ +-#define TEGRA194_MEMORY_CLIENT_APEW 0x7b +-#define TEGRA194_MEMORY_CLIENT_NVJPGSRD 0x7e +-#define TEGRA194_MEMORY_CLIENT_NVJPGSWR 0x7f +-/* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */ +-#define TEGRA194_MEMORY_CLIENT_AXIAPR 0x82 +-/* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */ +-#define TEGRA194_MEMORY_CLIENT_AXIAPW 0x83 +-/* ETR read clients */ +-#define TEGRA194_MEMORY_CLIENT_ETRR 0x84 +-/* ETR write clients */ +-#define TEGRA194_MEMORY_CLIENT_ETRW 0x85 +-/* AXI Switch read client */ +-#define TEGRA194_MEMORY_CLIENT_AXISR 0x8c +-/* AXI Switch write client */ +-#define TEGRA194_MEMORY_CLIENT_AXISW 0x8d +-/* EQOS read client */ +-#define TEGRA194_MEMORY_CLIENT_EQOSR 0x8e +-/* EQOS write client */ +-#define TEGRA194_MEMORY_CLIENT_EQOSW 0x8f +-/* UFSHC read client */ +-#define TEGRA194_MEMORY_CLIENT_UFSHCR 0x90 +-/* UFSHC write client */ +-#define TEGRA194_MEMORY_CLIENT_UFSHCW 0x91 +-/* NVDISPLAY read client */ +-#define TEGRA194_MEMORY_CLIENT_NVDISPLAYR 0x92 +-/* BPMP read client */ +-#define TEGRA194_MEMORY_CLIENT_BPMPR 0x93 +-/* BPMP write client */ +-#define TEGRA194_MEMORY_CLIENT_BPMPW 0x94 +-/* BPMPDMA read client */ +-#define TEGRA194_MEMORY_CLIENT_BPMPDMAR 0x95 +-/* BPMPDMA write client */ +-#define TEGRA194_MEMORY_CLIENT_BPMPDMAW 0x96 +-/* AON read client */ +-#define TEGRA194_MEMORY_CLIENT_AONR 0x97 +-/* AON write client */ +-#define TEGRA194_MEMORY_CLIENT_AONW 0x98 +-/* AONDMA read client */ +-#define TEGRA194_MEMORY_CLIENT_AONDMAR 0x99 +-/* AONDMA write client */ +-#define TEGRA194_MEMORY_CLIENT_AONDMAW 0x9a +-/* SCE read client */ +-#define TEGRA194_MEMORY_CLIENT_SCER 0x9b +-/* SCE write client */ +-#define TEGRA194_MEMORY_CLIENT_SCEW 0x9c +-/* SCEDMA read client */ +-#define TEGRA194_MEMORY_CLIENT_SCEDMAR 0x9d +-/* SCEDMA write client */ +-#define TEGRA194_MEMORY_CLIENT_SCEDMAW 0x9e +-/* APEDMA read client */ +-#define TEGRA194_MEMORY_CLIENT_APEDMAR 0x9f +-/* APEDMA write client */ +-#define TEGRA194_MEMORY_CLIENT_APEDMAW 0xa0 +-/* NVDISPLAY read client instance 2 */ +-#define TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 0xa1 +-#define TEGRA194_MEMORY_CLIENT_VICSRD1 0xa2 +-#define TEGRA194_MEMORY_CLIENT_NVDECSRD1 0xa3 +-/* MSS internal memqual MIU0 read clients */ +-#define TEGRA194_MEMORY_CLIENT_MIU0R 0xa6 +-/* MSS internal memqual MIU0 write clients */ +-#define TEGRA194_MEMORY_CLIENT_MIU0W 0xa7 +-/* MSS internal memqual MIU1 read clients */ +-#define TEGRA194_MEMORY_CLIENT_MIU1R 0xa8 +-/* MSS internal memqual MIU1 write clients */ +-#define TEGRA194_MEMORY_CLIENT_MIU1W 0xa9 +-/* MSS internal memqual MIU2 read clients */ +-#define TEGRA194_MEMORY_CLIENT_MIU2R 0xae +-/* MSS internal memqual MIU2 write clients */ +-#define TEGRA194_MEMORY_CLIENT_MIU2W 0xaf +-/* MSS internal memqual MIU3 read clients */ +-#define TEGRA194_MEMORY_CLIENT_MIU3R 0xb0 +-/* MSS internal memqual MIU3 write clients */ +-#define TEGRA194_MEMORY_CLIENT_MIU3W 0xb1 +-/* MSS internal memqual MIU4 read clients */ +-#define TEGRA194_MEMORY_CLIENT_MIU4R 0xb2 +-/* MSS internal memqual MIU4 write clients */ +-#define TEGRA194_MEMORY_CLIENT_MIU4W 0xb3 +-#define TEGRA194_MEMORY_CLIENT_DPMUR 0xb4 +-#define TEGRA194_MEMORY_CLIENT_DPMUW 0xb5 +-#define TEGRA194_MEMORY_CLIENT_NVL0R 0xb6 +-#define TEGRA194_MEMORY_CLIENT_NVL0W 0xb7 +-#define TEGRA194_MEMORY_CLIENT_NVL1R 0xb8 +-#define TEGRA194_MEMORY_CLIENT_NVL1W 0xb9 +-#define TEGRA194_MEMORY_CLIENT_NVL2R 0xba +-#define TEGRA194_MEMORY_CLIENT_NVL2W 0xbb +-/* VI FLACON read clients */ +-#define TEGRA194_MEMORY_CLIENT_VIFALR 0xbc +-/* VIFAL write clients */ +-#define TEGRA194_MEMORY_CLIENT_VIFALW 0xbd +-/* DLA0ARDA read clients */ +-#define TEGRA194_MEMORY_CLIENT_DLA0RDA 0xbe +-/* DLA0 Falcon read clients */ +-#define TEGRA194_MEMORY_CLIENT_DLA0FALRDB 0xbf +-/* DLA0 write clients */ +-#define TEGRA194_MEMORY_CLIENT_DLA0WRA 0xc0 +-/* DLA0 write clients */ +-#define TEGRA194_MEMORY_CLIENT_DLA0FALWRB 0xc1 +-/* DLA1ARDA read clients */ +-#define TEGRA194_MEMORY_CLIENT_DLA1RDA 0xc2 +-/* DLA1 Falcon read clients */ +-#define TEGRA194_MEMORY_CLIENT_DLA1FALRDB 0xc3 +-/* DLA1 write clients */ +-#define TEGRA194_MEMORY_CLIENT_DLA1WRA 0xc4 +-/* DLA1 write clients */ +-#define TEGRA194_MEMORY_CLIENT_DLA1FALWRB 0xc5 +-/* PVA0RDA read clients */ +-#define TEGRA194_MEMORY_CLIENT_PVA0RDA 0xc6 +-/* PVA0RDB read clients */ +-#define TEGRA194_MEMORY_CLIENT_PVA0RDB 0xc7 +-/* PVA0RDC read clients */ +-#define TEGRA194_MEMORY_CLIENT_PVA0RDC 0xc8 +-/* PVA0WRA write clients */ +-#define TEGRA194_MEMORY_CLIENT_PVA0WRA 0xc9 +-/* PVA0WRB write clients */ +-#define TEGRA194_MEMORY_CLIENT_PVA0WRB 0xca +-/* PVA0WRC write clients */ +-#define TEGRA194_MEMORY_CLIENT_PVA0WRC 0xcb +-/* PVA1RDA read clients */ +-#define TEGRA194_MEMORY_CLIENT_PVA1RDA 0xcc +-/* PVA1RDB read clients */ +-#define TEGRA194_MEMORY_CLIENT_PVA1RDB 0xcd +-/* PVA1RDC read clients */ +-#define TEGRA194_MEMORY_CLIENT_PVA1RDC 0xce +-/* PVA1WRA write clients */ +-#define TEGRA194_MEMORY_CLIENT_PVA1WRA 0xcf +-/* PVA1WRB write clients */ +-#define TEGRA194_MEMORY_CLIENT_PVA1WRB 0xd0 +-/* PVA1WRC write clients */ +-#define TEGRA194_MEMORY_CLIENT_PVA1WRC 0xd1 +-/* RCE read client */ +-#define TEGRA194_MEMORY_CLIENT_RCER 0xd2 +-/* RCE write client */ +-#define TEGRA194_MEMORY_CLIENT_RCEW 0xd3 +-/* RCEDMA read client */ +-#define TEGRA194_MEMORY_CLIENT_RCEDMAR 0xd4 +-/* RCEDMA write client */ +-#define TEGRA194_MEMORY_CLIENT_RCEDMAW 0xd5 +-#define TEGRA194_MEMORY_CLIENT_NVENC1SRD 0xd6 +-#define TEGRA194_MEMORY_CLIENT_NVENC1SWR 0xd7 +-/* PCIE0 read clients */ +-#define TEGRA194_MEMORY_CLIENT_PCIE0R 0xd8 +-/* PCIE0 write clients */ +-#define TEGRA194_MEMORY_CLIENT_PCIE0W 0xd9 +-/* PCIE1 read clients */ +-#define TEGRA194_MEMORY_CLIENT_PCIE1R 0xda +-/* PCIE1 write clients */ +-#define TEGRA194_MEMORY_CLIENT_PCIE1W 0xdb +-/* PCIE2 read clients */ +-#define TEGRA194_MEMORY_CLIENT_PCIE2AR 0xdc +-/* PCIE2 write clients */ +-#define TEGRA194_MEMORY_CLIENT_PCIE2AW 0xdd +-/* PCIE3 read clients */ +-#define TEGRA194_MEMORY_CLIENT_PCIE3R 0xde +-/* PCIE3 write clients */ +-#define TEGRA194_MEMORY_CLIENT_PCIE3W 0xdf +-/* PCIE4 read clients */ +-#define TEGRA194_MEMORY_CLIENT_PCIE4R 0xe0 +-/* PCIE4 write clients */ +-#define TEGRA194_MEMORY_CLIENT_PCIE4W 0xe1 +-/* PCIE5 read clients */ +-#define TEGRA194_MEMORY_CLIENT_PCIE5R 0xe2 +-/* PCIE5 write clients */ +-#define TEGRA194_MEMORY_CLIENT_PCIE5W 0xe3 +-/* ISP read client 1 for Crossbar A */ +-#define TEGRA194_MEMORY_CLIENT_ISPFALW 0xe4 +-#define TEGRA194_MEMORY_CLIENT_NVL3R 0xe5 +-#define TEGRA194_MEMORY_CLIENT_NVL3W 0xe6 +-#define TEGRA194_MEMORY_CLIENT_NVL4R 0xe7 +-#define TEGRA194_MEMORY_CLIENT_NVL4W 0xe8 +-/* DLA0ARDA1 read clients */ +-#define TEGRA194_MEMORY_CLIENT_DLA0RDA1 0xe9 +-/* DLA1ARDA1 read clients */ +-#define TEGRA194_MEMORY_CLIENT_DLA1RDA1 0xea +-/* PVA0RDA1 read clients */ +-#define TEGRA194_MEMORY_CLIENT_PVA0RDA1 0xeb +-/* PVA0RDB1 read clients */ +-#define TEGRA194_MEMORY_CLIENT_PVA0RDB1 0xec +-/* PVA1RDA1 read clients */ +-#define TEGRA194_MEMORY_CLIENT_PVA1RDA1 0xed +-/* PVA1RDB1 read clients */ +-#define TEGRA194_MEMORY_CLIENT_PVA1RDB1 0xee +-/* PCIE5r1 read clients */ +-#define TEGRA194_MEMORY_CLIENT_PCIE5R1 0xef +-#define TEGRA194_MEMORY_CLIENT_NVENCSRD1 0xf0 +-#define TEGRA194_MEMORY_CLIENT_NVENC1SRD1 0xf1 +-/* ISP read client for Crossbar A */ +-#define TEGRA194_MEMORY_CLIENT_ISPRA1 0xf2 +-/* PCIE0 read clients */ +-#define TEGRA194_MEMORY_CLIENT_PCIE0R1 0xf3 +-#define TEGRA194_MEMORY_CLIENT_NVL0RHP 0xf4 +-#define TEGRA194_MEMORY_CLIENT_NVL1RHP 0xf5 +-#define TEGRA194_MEMORY_CLIENT_NVL2RHP 0xf6 +-#define TEGRA194_MEMORY_CLIENT_NVL3RHP 0xf7 +-#define TEGRA194_MEMORY_CLIENT_NVL4RHP 0xf8 +-#define TEGRA194_MEMORY_CLIENT_NVDEC1SRD 0xf9 +-#define TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 0xfa +-#define TEGRA194_MEMORY_CLIENT_NVDEC1SWR 0xfb +-/* MSS internal memqual MIU5 read clients */ +-#define TEGRA194_MEMORY_CLIENT_MIU5R 0xfc +-/* MSS internal memqual MIU5 write clients */ +-#define TEGRA194_MEMORY_CLIENT_MIU5W 0xfd +-/* MSS internal memqual MIU6 read clients */ +-#define TEGRA194_MEMORY_CLIENT_MIU6R 0xfe +-/* MSS internal memqual MIU6 write clients */ +-#define TEGRA194_MEMORY_CLIENT_MIU6W 0xff +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/memory/tegra20-mc.h b/scripts/dtc/include-prefixes/dt-bindings/memory/tegra20-mc.h +deleted file mode 100644 +index 6f8829508ad0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/memory/tegra20-mc.h ++++ /dev/null +@@ -1,74 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef DT_BINDINGS_MEMORY_TEGRA20_MC_H +-#define DT_BINDINGS_MEMORY_TEGRA20_MC_H +- +-#define TEGRA20_MC_RESET_AVPC 0 +-#define TEGRA20_MC_RESET_DC 1 +-#define TEGRA20_MC_RESET_DCB 2 +-#define TEGRA20_MC_RESET_EPP 3 +-#define TEGRA20_MC_RESET_2D 4 +-#define TEGRA20_MC_RESET_HC 5 +-#define TEGRA20_MC_RESET_ISP 6 +-#define TEGRA20_MC_RESET_MPCORE 7 +-#define TEGRA20_MC_RESET_MPEA 8 +-#define TEGRA20_MC_RESET_MPEB 9 +-#define TEGRA20_MC_RESET_MPEC 10 +-#define TEGRA20_MC_RESET_3D 11 +-#define TEGRA20_MC_RESET_PPCS 12 +-#define TEGRA20_MC_RESET_VDE 13 +-#define TEGRA20_MC_RESET_VI 14 +- +-#define TEGRA20_MC_DISPLAY0A 0 +-#define TEGRA20_MC_DISPLAY0AB 1 +-#define TEGRA20_MC_DISPLAY0B 2 +-#define TEGRA20_MC_DISPLAY0BB 3 +-#define TEGRA20_MC_DISPLAY0C 4 +-#define TEGRA20_MC_DISPLAY0CB 5 +-#define TEGRA20_MC_DISPLAY1B 6 +-#define TEGRA20_MC_DISPLAY1BB 7 +-#define TEGRA20_MC_EPPUP 8 +-#define TEGRA20_MC_G2PR 9 +-#define TEGRA20_MC_G2SR 10 +-#define TEGRA20_MC_MPEUNIFBR 11 +-#define TEGRA20_MC_VIRUV 12 +-#define TEGRA20_MC_AVPCARM7R 13 +-#define TEGRA20_MC_DISPLAYHC 14 +-#define TEGRA20_MC_DISPLAYHCB 15 +-#define TEGRA20_MC_FDCDRD 16 +-#define TEGRA20_MC_G2DR 17 +-#define TEGRA20_MC_HOST1XDMAR 18 +-#define TEGRA20_MC_HOST1XR 19 +-#define TEGRA20_MC_IDXSRD 20 +-#define TEGRA20_MC_MPCORER 21 +-#define TEGRA20_MC_MPE_IPRED 22 +-#define TEGRA20_MC_MPEAMEMRD 23 +-#define TEGRA20_MC_MPECSRD 24 +-#define TEGRA20_MC_PPCSAHBDMAR 25 +-#define TEGRA20_MC_PPCSAHBSLVR 26 +-#define TEGRA20_MC_TEXSRD 27 +-#define TEGRA20_MC_VDEBSEVR 28 +-#define TEGRA20_MC_VDEMBER 29 +-#define TEGRA20_MC_VDEMCER 30 +-#define TEGRA20_MC_VDETPER 31 +-#define TEGRA20_MC_EPPU 32 +-#define TEGRA20_MC_EPPV 33 +-#define TEGRA20_MC_EPPY 34 +-#define TEGRA20_MC_MPEUNIFBW 35 +-#define TEGRA20_MC_VIWSB 36 +-#define TEGRA20_MC_VIWU 37 +-#define TEGRA20_MC_VIWV 38 +-#define TEGRA20_MC_VIWY 39 +-#define TEGRA20_MC_G2DW 40 +-#define TEGRA20_MC_AVPCARM7W 41 +-#define TEGRA20_MC_FDCDWR 42 +-#define TEGRA20_MC_HOST1XW 43 +-#define TEGRA20_MC_ISPW 44 +-#define TEGRA20_MC_MPCOREW 45 +-#define TEGRA20_MC_MPECSWR 46 +-#define TEGRA20_MC_PPCSAHBDMAW 47 +-#define TEGRA20_MC_PPCSAHBSLVW 48 +-#define TEGRA20_MC_VDEBSEVW 49 +-#define TEGRA20_MC_VDEMBEW 50 +-#define TEGRA20_MC_VDETPMW 51 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/memory/tegra210-mc.h b/scripts/dtc/include-prefixes/dt-bindings/memory/tegra210-mc.h +deleted file mode 100644 +index 5e082547f179..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/memory/tegra210-mc.h ++++ /dev/null +@@ -1,78 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H +-#define DT_BINDINGS_MEMORY_TEGRA210_MC_H +- +-#define TEGRA_SWGROUP_PTC 0 +-#define TEGRA_SWGROUP_DC 1 +-#define TEGRA_SWGROUP_DCB 2 +-#define TEGRA_SWGROUP_AFI 3 +-#define TEGRA_SWGROUP_AVPC 4 +-#define TEGRA_SWGROUP_HDA 5 +-#define TEGRA_SWGROUP_HC 6 +-#define TEGRA_SWGROUP_NVENC 7 +-#define TEGRA_SWGROUP_PPCS 8 +-#define TEGRA_SWGROUP_SATA 9 +-#define TEGRA_SWGROUP_MPCORE 10 +-#define TEGRA_SWGROUP_ISP2 11 +-#define TEGRA_SWGROUP_XUSB_HOST 12 +-#define TEGRA_SWGROUP_XUSB_DEV 13 +-#define TEGRA_SWGROUP_ISP2B 14 +-#define TEGRA_SWGROUP_TSEC 15 +-#define TEGRA_SWGROUP_A9AVP 16 +-#define TEGRA_SWGROUP_GPU 17 +-#define TEGRA_SWGROUP_SDMMC1A 18 +-#define TEGRA_SWGROUP_SDMMC2A 19 +-#define TEGRA_SWGROUP_SDMMC3A 20 +-#define TEGRA_SWGROUP_SDMMC4A 21 +-#define TEGRA_SWGROUP_VIC 22 +-#define TEGRA_SWGROUP_VI 23 +-#define TEGRA_SWGROUP_NVDEC 24 +-#define TEGRA_SWGROUP_APE 25 +-#define TEGRA_SWGROUP_NVJPG 26 +-#define TEGRA_SWGROUP_SE 27 +-#define TEGRA_SWGROUP_AXIAP 28 +-#define TEGRA_SWGROUP_ETR 29 +-#define TEGRA_SWGROUP_TSECB 30 +-#define TEGRA_SWGROUP_NV 31 +-#define TEGRA_SWGROUP_NV2 32 +-#define TEGRA_SWGROUP_PPCS1 33 +-#define TEGRA_SWGROUP_DC1 34 +-#define TEGRA_SWGROUP_PPCS2 35 +-#define TEGRA_SWGROUP_HC1 36 +-#define TEGRA_SWGROUP_SE1 37 +-#define TEGRA_SWGROUP_TSEC1 38 +-#define TEGRA_SWGROUP_TSECB1 39 +-#define TEGRA_SWGROUP_NVDEC1 40 +- +-#define TEGRA210_MC_RESET_AFI 0 +-#define TEGRA210_MC_RESET_AVPC 1 +-#define TEGRA210_MC_RESET_DC 2 +-#define TEGRA210_MC_RESET_DCB 3 +-#define TEGRA210_MC_RESET_HC 4 +-#define TEGRA210_MC_RESET_HDA 5 +-#define TEGRA210_MC_RESET_ISP2 6 +-#define TEGRA210_MC_RESET_MPCORE 7 +-#define TEGRA210_MC_RESET_NVENC 8 +-#define TEGRA210_MC_RESET_PPCS 9 +-#define TEGRA210_MC_RESET_SATA 10 +-#define TEGRA210_MC_RESET_VI 11 +-#define TEGRA210_MC_RESET_VIC 12 +-#define TEGRA210_MC_RESET_XUSB_HOST 13 +-#define TEGRA210_MC_RESET_XUSB_DEV 14 +-#define TEGRA210_MC_RESET_A9AVP 15 +-#define TEGRA210_MC_RESET_TSEC 16 +-#define TEGRA210_MC_RESET_SDMMC1 17 +-#define TEGRA210_MC_RESET_SDMMC2 18 +-#define TEGRA210_MC_RESET_SDMMC3 19 +-#define TEGRA210_MC_RESET_SDMMC4 20 +-#define TEGRA210_MC_RESET_ISP2B 21 +-#define TEGRA210_MC_RESET_GPU 22 +-#define TEGRA210_MC_RESET_NVDEC 23 +-#define TEGRA210_MC_RESET_APE 24 +-#define TEGRA210_MC_RESET_SE 25 +-#define TEGRA210_MC_RESET_NVJPG 26 +-#define TEGRA210_MC_RESET_AXIAP 27 +-#define TEGRA210_MC_RESET_ETR 28 +-#define TEGRA210_MC_RESET_TSECB 29 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/memory/tegra30-mc.h b/scripts/dtc/include-prefixes/dt-bindings/memory/tegra30-mc.h +deleted file mode 100644 +index 930f708aca17..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/memory/tegra30-mc.h ++++ /dev/null +@@ -1,111 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H +-#define DT_BINDINGS_MEMORY_TEGRA30_MC_H +- +-#define TEGRA_SWGROUP_PTC 0 +-#define TEGRA_SWGROUP_DC 1 +-#define TEGRA_SWGROUP_DCB 2 +-#define TEGRA_SWGROUP_EPP 3 +-#define TEGRA_SWGROUP_G2 4 +-#define TEGRA_SWGROUP_MPE 5 +-#define TEGRA_SWGROUP_VI 6 +-#define TEGRA_SWGROUP_AFI 7 +-#define TEGRA_SWGROUP_AVPC 8 +-#define TEGRA_SWGROUP_NV 9 +-#define TEGRA_SWGROUP_NV2 10 +-#define TEGRA_SWGROUP_HDA 11 +-#define TEGRA_SWGROUP_HC 12 +-#define TEGRA_SWGROUP_PPCS 13 +-#define TEGRA_SWGROUP_SATA 14 +-#define TEGRA_SWGROUP_VDE 15 +-#define TEGRA_SWGROUP_MPCORELP 16 +-#define TEGRA_SWGROUP_MPCORE 17 +-#define TEGRA_SWGROUP_ISP 18 +- +-#define TEGRA30_MC_RESET_AFI 0 +-#define TEGRA30_MC_RESET_AVPC 1 +-#define TEGRA30_MC_RESET_DC 2 +-#define TEGRA30_MC_RESET_DCB 3 +-#define TEGRA30_MC_RESET_EPP 4 +-#define TEGRA30_MC_RESET_2D 5 +-#define TEGRA30_MC_RESET_HC 6 +-#define TEGRA30_MC_RESET_HDA 7 +-#define TEGRA30_MC_RESET_ISP 8 +-#define TEGRA30_MC_RESET_MPCORE 9 +-#define TEGRA30_MC_RESET_MPCORELP 10 +-#define TEGRA30_MC_RESET_MPE 11 +-#define TEGRA30_MC_RESET_3D 12 +-#define TEGRA30_MC_RESET_3D2 13 +-#define TEGRA30_MC_RESET_PPCS 14 +-#define TEGRA30_MC_RESET_SATA 15 +-#define TEGRA30_MC_RESET_VDE 16 +-#define TEGRA30_MC_RESET_VI 17 +- +-#define TEGRA30_MC_PTCR 0 +-#define TEGRA30_MC_DISPLAY0A 1 +-#define TEGRA30_MC_DISPLAY0AB 2 +-#define TEGRA30_MC_DISPLAY0B 3 +-#define TEGRA30_MC_DISPLAY0BB 4 +-#define TEGRA30_MC_DISPLAY0C 5 +-#define TEGRA30_MC_DISPLAY0CB 6 +-#define TEGRA30_MC_DISPLAY1B 7 +-#define TEGRA30_MC_DISPLAY1BB 8 +-#define TEGRA30_MC_EPPUP 9 +-#define TEGRA30_MC_G2PR 10 +-#define TEGRA30_MC_G2SR 11 +-#define TEGRA30_MC_MPEUNIFBR 12 +-#define TEGRA30_MC_VIRUV 13 +-#define TEGRA30_MC_AFIR 14 +-#define TEGRA30_MC_AVPCARM7R 15 +-#define TEGRA30_MC_DISPLAYHC 16 +-#define TEGRA30_MC_DISPLAYHCB 17 +-#define TEGRA30_MC_FDCDRD 18 +-#define TEGRA30_MC_FDCDRD2 19 +-#define TEGRA30_MC_G2DR 20 +-#define TEGRA30_MC_HDAR 21 +-#define TEGRA30_MC_HOST1XDMAR 22 +-#define TEGRA30_MC_HOST1XR 23 +-#define TEGRA30_MC_IDXSRD 24 +-#define TEGRA30_MC_IDXSRD2 25 +-#define TEGRA30_MC_MPE_IPRED 26 +-#define TEGRA30_MC_MPEAMEMRD 27 +-#define TEGRA30_MC_MPECSRD 28 +-#define TEGRA30_MC_PPCSAHBDMAR 29 +-#define TEGRA30_MC_PPCSAHBSLVR 30 +-#define TEGRA30_MC_SATAR 31 +-#define TEGRA30_MC_TEXSRD 32 +-#define TEGRA30_MC_TEXSRD2 33 +-#define TEGRA30_MC_VDEBSEVR 34 +-#define TEGRA30_MC_VDEMBER 35 +-#define TEGRA30_MC_VDEMCER 36 +-#define TEGRA30_MC_VDETPER 37 +-#define TEGRA30_MC_MPCORELPR 38 +-#define TEGRA30_MC_MPCORER 39 +-#define TEGRA30_MC_EPPU 40 +-#define TEGRA30_MC_EPPV 41 +-#define TEGRA30_MC_EPPY 42 +-#define TEGRA30_MC_MPEUNIFBW 43 +-#define TEGRA30_MC_VIWSB 44 +-#define TEGRA30_MC_VIWU 45 +-#define TEGRA30_MC_VIWV 46 +-#define TEGRA30_MC_VIWY 47 +-#define TEGRA30_MC_G2DW 48 +-#define TEGRA30_MC_AFIW 49 +-#define TEGRA30_MC_AVPCARM7W 50 +-#define TEGRA30_MC_FDCDWR 51 +-#define TEGRA30_MC_FDCDWR2 52 +-#define TEGRA30_MC_HDAW 53 +-#define TEGRA30_MC_HOST1XW 54 +-#define TEGRA30_MC_ISPW 55 +-#define TEGRA30_MC_MPCORELPW 56 +-#define TEGRA30_MC_MPCOREW 57 +-#define TEGRA30_MC_MPECSWR 58 +-#define TEGRA30_MC_PPCSAHBDMAW 59 +-#define TEGRA30_MC_PPCSAHBSLVW 60 +-#define TEGRA30_MC_SATAW 61 +-#define TEGRA30_MC_VDEBSEVW 62 +-#define TEGRA30_MC_VDEDBGW 63 +-#define TEGRA30_MC_VDEMBEW 64 +-#define TEGRA30_MC_VDETPMW 65 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mfd/arizona.h b/scripts/dtc/include-prefixes/dt-bindings/mfd/arizona.h +deleted file mode 100644 +index 1056108c9590..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mfd/arizona.h ++++ /dev/null +@@ -1,115 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Device Tree defines for Arizona devices +- * +- * Copyright 2015 Cirrus Logic Inc. +- * +- * Author: Charles Keepax +- */ +- +-#ifndef _DT_BINDINGS_MFD_ARIZONA_H +-#define _DT_BINDINGS_MFD_ARIZONA_H +- +-/* GPIO Function Definitions */ +-#define ARIZONA_GP_FN_TXLRCLK 0x00 +-#define ARIZONA_GP_FN_GPIO 0x01 +-#define ARIZONA_GP_FN_IRQ1 0x02 +-#define ARIZONA_GP_FN_IRQ2 0x03 +-#define ARIZONA_GP_FN_OPCLK 0x04 +-#define ARIZONA_GP_FN_FLL1_OUT 0x05 +-#define ARIZONA_GP_FN_FLL2_OUT 0x06 +-#define ARIZONA_GP_FN_PWM1 0x08 +-#define ARIZONA_GP_FN_PWM2 0x09 +-#define ARIZONA_GP_FN_SYSCLK_UNDERCLOCKED 0x0A +-#define ARIZONA_GP_FN_ASYNCCLK_UNDERCLOCKED 0x0B +-#define ARIZONA_GP_FN_FLL1_LOCK 0x0C +-#define ARIZONA_GP_FN_FLL2_LOCK 0x0D +-#define ARIZONA_GP_FN_FLL1_CLOCK_OK 0x0F +-#define ARIZONA_GP_FN_FLL2_CLOCK_OK 0x10 +-#define ARIZONA_GP_FN_HEADPHONE_DET 0x12 +-#define ARIZONA_GP_FN_MIC_DET 0x13 +-#define ARIZONA_GP_FN_WSEQ_STATUS 0x15 +-#define ARIZONA_GP_FN_CIF_ADDRESS_ERROR 0x16 +-#define ARIZONA_GP_FN_ASRC1_LOCK 0x1A +-#define ARIZONA_GP_FN_ASRC2_LOCK 0x1B +-#define ARIZONA_GP_FN_ASRC_CONFIG_ERROR 0x1C +-#define ARIZONA_GP_FN_DRC1_SIGNAL_DETECT 0x1D +-#define ARIZONA_GP_FN_DRC1_ANTICLIP 0x1E +-#define ARIZONA_GP_FN_DRC1_DECAY 0x1F +-#define ARIZONA_GP_FN_DRC1_NOISE 0x20 +-#define ARIZONA_GP_FN_DRC1_QUICK_RELEASE 0x21 +-#define ARIZONA_GP_FN_DRC2_SIGNAL_DETECT 0x22 +-#define ARIZONA_GP_FN_DRC2_ANTICLIP 0x23 +-#define ARIZONA_GP_FN_DRC2_DECAY 0x24 +-#define ARIZONA_GP_FN_DRC2_NOISE 0x25 +-#define ARIZONA_GP_FN_DRC2_QUICK_RELEASE 0x26 +-#define ARIZONA_GP_FN_MIXER_DROPPED_SAMPLE 0x27 +-#define ARIZONA_GP_FN_AIF1_CONFIG_ERROR 0x28 +-#define ARIZONA_GP_FN_AIF2_CONFIG_ERROR 0x29 +-#define ARIZONA_GP_FN_AIF3_CONFIG_ERROR 0x2A +-#define ARIZONA_GP_FN_SPK_TEMP_SHUTDOWN 0x2B +-#define ARIZONA_GP_FN_SPK_TEMP_WARNING 0x2C +-#define ARIZONA_GP_FN_UNDERCLOCKED 0x2D +-#define ARIZONA_GP_FN_OVERCLOCKED 0x2E +-#define ARIZONA_GP_FN_DSP_IRQ1 0x35 +-#define ARIZONA_GP_FN_DSP_IRQ2 0x36 +-#define ARIZONA_GP_FN_ASYNC_OPCLK 0x3D +-#define ARIZONA_GP_FN_BOOT_DONE 0x44 +-#define ARIZONA_GP_FN_DSP1_RAM_READY 0x45 +-#define ARIZONA_GP_FN_SYSCLK_ENA_STATUS 0x4B +-#define ARIZONA_GP_FN_ASYNCCLK_ENA_STATUS 0x4C +- +-/* GPIO Configuration Bits */ +-#define ARIZONA_GPN_DIR 0x8000 +-#define ARIZONA_GPN_PU 0x4000 +-#define ARIZONA_GPN_PD 0x2000 +-#define ARIZONA_GPN_LVL 0x0800 +-#define ARIZONA_GPN_POL 0x0400 +-#define ARIZONA_GPN_OP_CFG 0x0200 +-#define ARIZONA_GPN_DB 0x0100 +- +-/* Provide some defines for the most common configs */ +-#define ARIZONA_GP_DEFAULT 0xffffffff +-#define ARIZONA_GP_OUTPUT (ARIZONA_GP_FN_GPIO) +-#define ARIZONA_GP_INPUT (ARIZONA_GP_FN_GPIO | \ +- ARIZONA_GPN_DIR) +- +-#define ARIZONA_32KZ_MCLK1 1 +-#define ARIZONA_32KZ_MCLK2 2 +-#define ARIZONA_32KZ_NONE 3 +- +-#define ARIZONA_DMIC_MICVDD 0 +-#define ARIZONA_DMIC_MICBIAS1 1 +-#define ARIZONA_DMIC_MICBIAS2 2 +-#define ARIZONA_DMIC_MICBIAS3 3 +- +-#define ARIZONA_INMODE_DIFF 0 +-#define ARIZONA_INMODE_SE 1 +-#define ARIZONA_INMODE_DMIC 2 +- +-#define ARIZONA_MICD_TIME_CONTINUOUS 0 +-#define ARIZONA_MICD_TIME_250US 1 +-#define ARIZONA_MICD_TIME_500US 2 +-#define ARIZONA_MICD_TIME_1MS 3 +-#define ARIZONA_MICD_TIME_2MS 4 +-#define ARIZONA_MICD_TIME_4MS 5 +-#define ARIZONA_MICD_TIME_8MS 6 +-#define ARIZONA_MICD_TIME_16MS 7 +-#define ARIZONA_MICD_TIME_32MS 8 +-#define ARIZONA_MICD_TIME_64MS 9 +-#define ARIZONA_MICD_TIME_128MS 10 +-#define ARIZONA_MICD_TIME_256MS 11 +-#define ARIZONA_MICD_TIME_512MS 12 +- +-#define ARIZONA_ACCDET_MODE_MIC 0 +-#define ARIZONA_ACCDET_MODE_HPL 1 +-#define ARIZONA_ACCDET_MODE_HPR 2 +-#define ARIZONA_ACCDET_MODE_HPM 4 +-#define ARIZONA_ACCDET_MODE_ADC 7 +- +-#define ARIZONA_GPSW_OPEN 0 +-#define ARIZONA_GPSW_CLOSED 1 +-#define ARIZONA_GPSW_CLAMP_ENABLED 2 +-#define ARIZONA_GPSW_CLAMP_DISABLED 3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mfd/as3722.h b/scripts/dtc/include-prefixes/dt-bindings/mfd/as3722.h +deleted file mode 100644 +index 9ef0cba90407..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mfd/as3722.h ++++ /dev/null +@@ -1,53 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides macros for ams AS3722 device bindings. +- * +- * Copyright (c) 2013, NVIDIA Corporation. +- * +- * Author: Laxman Dewangan +- * +- */ +- +-#ifndef __DT_BINDINGS_AS3722_H__ +-#define __DT_BINDINGS_AS3722_H__ +- +-/* External control pins */ +-#define AS3722_EXT_CONTROL_PIN_ENABLE1 1 +-#define AS3722_EXT_CONTROL_PIN_ENABLE2 2 +-#define AS3722_EXT_CONTROL_PIN_ENABLE3 3 +- +-/* Interrupt numbers for AS3722 */ +-#define AS3722_IRQ_LID 0 +-#define AS3722_IRQ_ACOK 1 +-#define AS3722_IRQ_ENABLE1 2 +-#define AS3722_IRQ_OCCUR_ALARM_SD0 3 +-#define AS3722_IRQ_ONKEY_LONG_PRESS 4 +-#define AS3722_IRQ_ONKEY 5 +-#define AS3722_IRQ_OVTMP 6 +-#define AS3722_IRQ_LOWBAT 7 +-#define AS3722_IRQ_SD0_LV 8 +-#define AS3722_IRQ_SD1_LV 9 +-#define AS3722_IRQ_SD2_LV 10 +-#define AS3722_IRQ_PWM1_OV_PROT 11 +-#define AS3722_IRQ_PWM2_OV_PROT 12 +-#define AS3722_IRQ_ENABLE2 13 +-#define AS3722_IRQ_SD6_LV 14 +-#define AS3722_IRQ_RTC_REP 15 +-#define AS3722_IRQ_RTC_ALARM 16 +-#define AS3722_IRQ_GPIO1 17 +-#define AS3722_IRQ_GPIO2 18 +-#define AS3722_IRQ_GPIO3 19 +-#define AS3722_IRQ_GPIO4 20 +-#define AS3722_IRQ_GPIO5 21 +-#define AS3722_IRQ_WATCHDOG 22 +-#define AS3722_IRQ_ENABLE3 23 +-#define AS3722_IRQ_TEMP_SD0_SHUTDOWN 24 +-#define AS3722_IRQ_TEMP_SD1_SHUTDOWN 25 +-#define AS3722_IRQ_TEMP_SD2_SHUTDOWN 26 +-#define AS3722_IRQ_TEMP_SD0_ALARM 27 +-#define AS3722_IRQ_TEMP_SD1_ALARM 28 +-#define AS3722_IRQ_TEMP_SD6_ALARM 29 +-#define AS3722_IRQ_OCCUR_ALARM_SD6 30 +-#define AS3722_IRQ_ADC 31 +- +-#endif /* __DT_BINDINGS_AS3722_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mfd/at91-usart.h b/scripts/dtc/include-prefixes/dt-bindings/mfd/at91-usart.h +deleted file mode 100644 +index 2de5bc312e1e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mfd/at91-usart.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides macros for AT91 USART DT bindings. +- * +- * Copyright (C) 2018 Microchip Technology +- * +- * Author: Radu Pirea +- * +- */ +- +-#ifndef __DT_BINDINGS_AT91_USART_H__ +-#define __DT_BINDINGS_AT91_USART_H__ +- +-#define AT91_USART_MODE_SERIAL 0 +-#define AT91_USART_MODE_SPI 1 +- +-#endif /* __DT_BINDINGS_AT91_USART_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mfd/atmel-flexcom.h b/scripts/dtc/include-prefixes/dt-bindings/mfd/atmel-flexcom.h +deleted file mode 100644 +index 4e2fc3236394..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mfd/atmel-flexcom.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * This header provides macros for Atmel Flexcom DT bindings. +- * +- * Copyright (C) 2015 Cyrille Pitchen +- */ +- +-#ifndef __DT_BINDINGS_ATMEL_FLEXCOM_H__ +-#define __DT_BINDINGS_ATMEL_FLEXCOM_H__ +- +-#define ATMEL_FLEXCOM_MODE_USART 1 +-#define ATMEL_FLEXCOM_MODE_SPI 2 +-#define ATMEL_FLEXCOM_MODE_TWI 3 +- +-#endif /* __DT_BINDINGS_ATMEL_FLEXCOM_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mfd/dbx500-prcmu.h b/scripts/dtc/include-prefixes/dt-bindings/mfd/dbx500-prcmu.h +deleted file mode 100644 +index 0404bcc47dd4..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mfd/dbx500-prcmu.h ++++ /dev/null +@@ -1,84 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for the PRCMU bindings. +- * +- */ +- +-#ifndef _DT_BINDINGS_MFD_PRCMU_H +-#define _DT_BINDINGS_MFD_PRCMU_H +- +-/* +- * Clock identifiers. +- */ +-#define ARMCLK 0 +-#define PRCMU_ACLK 1 +-#define PRCMU_SVAMMCSPCLK 2 +-#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */ +-#define PRCMU_SIACLK 3 +-#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */ +-#define PRCMU_SGACLK 4 +-#define PRCMU_UARTCLK 5 +-#define PRCMU_MSP02CLK 6 +-#define PRCMU_MSP1CLK 7 +-#define PRCMU_I2CCLK 8 +-#define PRCMU_SDMMCCLK 9 +-#define PRCMU_SLIMCLK 10 +-#define PRCMU_CAMCLK 10 /* DBx540 only. */ +-#define PRCMU_PER1CLK 11 +-#define PRCMU_PER2CLK 12 +-#define PRCMU_PER3CLK 13 +-#define PRCMU_PER5CLK 14 +-#define PRCMU_PER6CLK 15 +-#define PRCMU_PER7CLK 16 +-#define PRCMU_LCDCLK 17 +-#define PRCMU_BMLCLK 18 +-#define PRCMU_HSITXCLK 19 +-#define PRCMU_HSIRXCLK 20 +-#define PRCMU_HDMICLK 21 +-#define PRCMU_APEATCLK 22 +-#define PRCMU_APETRACECLK 23 +-#define PRCMU_MCDECLK 24 +-#define PRCMU_IPI2CCLK 25 +-#define PRCMU_DSIALTCLK 26 +-#define PRCMU_DMACLK 27 +-#define PRCMU_B2R2CLK 28 +-#define PRCMU_TVCLK 29 +-#define SPARE_UNIPROCLK 30 +-#define PRCMU_SSPCLK 31 +-#define PRCMU_RNGCLK 32 +-#define PRCMU_UICCCLK 33 +-#define PRCMU_G1CLK 34 /* DBx540 only. */ +-#define PRCMU_HVACLK 35 /* DBx540 only. */ +-#define PRCMU_SPARE1CLK 36 +-#define PRCMU_SPARE2CLK 37 +- +-#define PRCMU_NUM_REG_CLOCKS 38 +- +-#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS +-#define PRCMU_SYSCLK 39 +-#define PRCMU_CDCLK 40 +-#define PRCMU_TIMCLK 41 +-#define PRCMU_PLLSOC0 42 +-#define PRCMU_PLLSOC1 43 +-#define PRCMU_ARMSS 44 +-#define PRCMU_PLLDDR 45 +- +-/* DSI Clocks */ +-#define PRCMU_PLLDSI 46 +-#define PRCMU_DSI0CLK 47 +-#define PRCMU_DSI1CLK 48 +-#define PRCMU_DSI0ESCCLK 49 +-#define PRCMU_DSI1ESCCLK 50 +-#define PRCMU_DSI2ESCCLK 51 +- +-/* LCD DSI PLL - Ux540 only */ +-#define PRCMU_PLLDSI_LCD 52 +-#define PRCMU_DSI0CLK_LCD 53 +-#define PRCMU_DSI1CLK_LCD 54 +-#define PRCMU_DSI0ESCCLK_LCD 55 +-#define PRCMU_DSI1ESCCLK_LCD 56 +-#define PRCMU_DSI2ESCCLK_LCD 57 +- +-#define PRCMU_NUM_CLKS 58 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mfd/max77620.h b/scripts/dtc/include-prefixes/dt-bindings/mfd/max77620.h +deleted file mode 100644 +index 1e19c5f908d7..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mfd/max77620.h ++++ /dev/null +@@ -1,40 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides macros for MAXIM MAX77620 device bindings. +- * +- * Copyright (c) 2016, NVIDIA Corporation. +- * Author: Laxman Dewangan +- */ +- +-#ifndef _DT_BINDINGS_MFD_MAX77620_H +-#define _DT_BINDINGS_MFD_MAX77620_H +- +-/* MAX77620 interrupts */ +-#define MAX77620_IRQ_TOP_GLBL 0 /* Low-Battery */ +-#define MAX77620_IRQ_TOP_SD 1 /* SD power fail */ +-#define MAX77620_IRQ_TOP_LDO 2 /* LDO power fail */ +-#define MAX77620_IRQ_TOP_GPIO 3 /* GPIO internal int to MAX77620 */ +-#define MAX77620_IRQ_TOP_RTC 4 /* RTC */ +-#define MAX77620_IRQ_TOP_32K 5 /* 32kHz oscillator */ +-#define MAX77620_IRQ_TOP_ONOFF 6 /* ON/OFF oscillator */ +-#define MAX77620_IRQ_LBT_MBATLOW 7 /* Thermal alarm status, > 120C */ +-#define MAX77620_IRQ_LBT_TJALRM1 8 /* Thermal alarm status, > 120C */ +-#define MAX77620_IRQ_LBT_TJALRM2 9 /* Thermal alarm status, > 140C */ +- +-/* FPS event source */ +-#define MAX77620_FPS_EVENT_SRC_EN0 0 +-#define MAX77620_FPS_EVENT_SRC_EN1 1 +-#define MAX77620_FPS_EVENT_SRC_SW 2 +- +-/* Device state when FPS event LOW */ +-#define MAX77620_FPS_INACTIVE_STATE_SLEEP 0 +-#define MAX77620_FPS_INACTIVE_STATE_LOW_POWER 1 +- +-/* FPS source */ +-#define MAX77620_FPS_SRC_0 0 +-#define MAX77620_FPS_SRC_1 1 +-#define MAX77620_FPS_SRC_2 2 +-#define MAX77620_FPS_SRC_NONE 3 +-#define MAX77620_FPS_SRC_DEF 4 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mfd/palmas.h b/scripts/dtc/include-prefixes/dt-bindings/mfd/palmas.h +deleted file mode 100644 +index c4f1d57ff4ff..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mfd/palmas.h ++++ /dev/null +@@ -1,19 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides macros for Palmas device bindings. +- * +- * Copyright (c) 2013, NVIDIA Corporation. +- * +- * Author: Laxman Dewangan +- * +- */ +- +-#ifndef __DT_BINDINGS_PALMAS_H +-#define __DT_BINDINGS_PALMAS_H +- +-/* External control pins */ +-#define PALMAS_EXT_CONTROL_PIN_ENABLE1 1 +-#define PALMAS_EXT_CONTROL_PIN_ENABLE2 2 +-#define PALMAS_EXT_CONTROL_PIN_NSLEEP 3 +- +-#endif /* __DT_BINDINGS_PALMAS_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mfd/qcom-pm8008.h b/scripts/dtc/include-prefixes/dt-bindings/mfd/qcom-pm8008.h +deleted file mode 100644 +index eca9448df228..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mfd/qcom-pm8008.h ++++ /dev/null +@@ -1,19 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2021 The Linux Foundation. All rights reserved. +- */ +- +-#ifndef __DT_BINDINGS_MFD_QCOM_PM8008_H +-#define __DT_BINDINGS_MFD_QCOM_PM8008_H +- +-/* PM8008 IRQ numbers */ +-#define PM8008_IRQ_MISC_UVLO 0 +-#define PM8008_IRQ_MISC_OVLO 1 +-#define PM8008_IRQ_MISC_OTST2 2 +-#define PM8008_IRQ_MISC_OTST3 3 +-#define PM8008_IRQ_MISC_LDO_OCP 4 +-#define PM8008_IRQ_TEMP_ALARM 5 +-#define PM8008_IRQ_GPIO1 6 +-#define PM8008_IRQ_GPIO2 7 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mfd/qcom-rpm.h b/scripts/dtc/include-prefixes/dt-bindings/mfd/qcom-rpm.h +deleted file mode 100644 +index c9204c4df520..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mfd/qcom-rpm.h ++++ /dev/null +@@ -1,183 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for the Qualcomm RPM bindings. +- */ +- +-#ifndef _DT_BINDINGS_MFD_QCOM_RPM_H +-#define _DT_BINDINGS_MFD_QCOM_RPM_H +- +-/* +- * Constants use to identify individual resources in the RPM. +- */ +-#define QCOM_RPM_APPS_FABRIC_ARB 1 +-#define QCOM_RPM_APPS_FABRIC_CLK 2 +-#define QCOM_RPM_APPS_FABRIC_HALT 3 +-#define QCOM_RPM_APPS_FABRIC_IOCTL 4 +-#define QCOM_RPM_APPS_FABRIC_MODE 5 +-#define QCOM_RPM_APPS_L2_CACHE_CTL 6 +-#define QCOM_RPM_CFPB_CLK 7 +-#define QCOM_RPM_CXO_BUFFERS 8 +-#define QCOM_RPM_CXO_CLK 9 +-#define QCOM_RPM_DAYTONA_FABRIC_CLK 10 +-#define QCOM_RPM_DDR_DMM 11 +-#define QCOM_RPM_EBI1_CLK 12 +-#define QCOM_RPM_HDMI_SWITCH 13 +-#define QCOM_RPM_MMFPB_CLK 14 +-#define QCOM_RPM_MM_FABRIC_ARB 15 +-#define QCOM_RPM_MM_FABRIC_CLK 16 +-#define QCOM_RPM_MM_FABRIC_HALT 17 +-#define QCOM_RPM_MM_FABRIC_IOCTL 18 +-#define QCOM_RPM_MM_FABRIC_MODE 19 +-#define QCOM_RPM_PLL_4 20 +-#define QCOM_RPM_PM8058_LDO0 21 +-#define QCOM_RPM_PM8058_LDO1 22 +-#define QCOM_RPM_PM8058_LDO2 23 +-#define QCOM_RPM_PM8058_LDO3 24 +-#define QCOM_RPM_PM8058_LDO4 25 +-#define QCOM_RPM_PM8058_LDO5 26 +-#define QCOM_RPM_PM8058_LDO6 27 +-#define QCOM_RPM_PM8058_LDO7 28 +-#define QCOM_RPM_PM8058_LDO8 29 +-#define QCOM_RPM_PM8058_LDO9 30 +-#define QCOM_RPM_PM8058_LDO10 31 +-#define QCOM_RPM_PM8058_LDO11 32 +-#define QCOM_RPM_PM8058_LDO12 33 +-#define QCOM_RPM_PM8058_LDO13 34 +-#define QCOM_RPM_PM8058_LDO14 35 +-#define QCOM_RPM_PM8058_LDO15 36 +-#define QCOM_RPM_PM8058_LDO16 37 +-#define QCOM_RPM_PM8058_LDO17 38 +-#define QCOM_RPM_PM8058_LDO18 39 +-#define QCOM_RPM_PM8058_LDO19 40 +-#define QCOM_RPM_PM8058_LDO20 41 +-#define QCOM_RPM_PM8058_LDO21 42 +-#define QCOM_RPM_PM8058_LDO22 43 +-#define QCOM_RPM_PM8058_LDO23 44 +-#define QCOM_RPM_PM8058_LDO24 45 +-#define QCOM_RPM_PM8058_LDO25 46 +-#define QCOM_RPM_PM8058_LVS0 47 +-#define QCOM_RPM_PM8058_LVS1 48 +-#define QCOM_RPM_PM8058_NCP 49 +-#define QCOM_RPM_PM8058_SMPS0 50 +-#define QCOM_RPM_PM8058_SMPS1 51 +-#define QCOM_RPM_PM8058_SMPS2 52 +-#define QCOM_RPM_PM8058_SMPS3 53 +-#define QCOM_RPM_PM8058_SMPS4 54 +-#define QCOM_RPM_PM8821_LDO1 55 +-#define QCOM_RPM_PM8821_SMPS1 56 +-#define QCOM_RPM_PM8821_SMPS2 57 +-#define QCOM_RPM_PM8901_LDO0 58 +-#define QCOM_RPM_PM8901_LDO1 59 +-#define QCOM_RPM_PM8901_LDO2 60 +-#define QCOM_RPM_PM8901_LDO3 61 +-#define QCOM_RPM_PM8901_LDO4 62 +-#define QCOM_RPM_PM8901_LDO5 63 +-#define QCOM_RPM_PM8901_LDO6 64 +-#define QCOM_RPM_PM8901_LVS0 65 +-#define QCOM_RPM_PM8901_LVS1 66 +-#define QCOM_RPM_PM8901_LVS2 67 +-#define QCOM_RPM_PM8901_LVS3 68 +-#define QCOM_RPM_PM8901_MVS 69 +-#define QCOM_RPM_PM8901_SMPS0 70 +-#define QCOM_RPM_PM8901_SMPS1 71 +-#define QCOM_RPM_PM8901_SMPS2 72 +-#define QCOM_RPM_PM8901_SMPS3 73 +-#define QCOM_RPM_PM8901_SMPS4 74 +-#define QCOM_RPM_PM8921_CLK1 75 +-#define QCOM_RPM_PM8921_CLK2 76 +-#define QCOM_RPM_PM8921_LDO1 77 +-#define QCOM_RPM_PM8921_LDO2 78 +-#define QCOM_RPM_PM8921_LDO3 79 +-#define QCOM_RPM_PM8921_LDO4 80 +-#define QCOM_RPM_PM8921_LDO5 81 +-#define QCOM_RPM_PM8921_LDO6 82 +-#define QCOM_RPM_PM8921_LDO7 83 +-#define QCOM_RPM_PM8921_LDO8 84 +-#define QCOM_RPM_PM8921_LDO9 85 +-#define QCOM_RPM_PM8921_LDO10 86 +-#define QCOM_RPM_PM8921_LDO11 87 +-#define QCOM_RPM_PM8921_LDO12 88 +-#define QCOM_RPM_PM8921_LDO13 89 +-#define QCOM_RPM_PM8921_LDO14 90 +-#define QCOM_RPM_PM8921_LDO15 91 +-#define QCOM_RPM_PM8921_LDO16 92 +-#define QCOM_RPM_PM8921_LDO17 93 +-#define QCOM_RPM_PM8921_LDO18 94 +-#define QCOM_RPM_PM8921_LDO19 95 +-#define QCOM_RPM_PM8921_LDO20 96 +-#define QCOM_RPM_PM8921_LDO21 97 +-#define QCOM_RPM_PM8921_LDO22 98 +-#define QCOM_RPM_PM8921_LDO23 99 +-#define QCOM_RPM_PM8921_LDO24 100 +-#define QCOM_RPM_PM8921_LDO25 101 +-#define QCOM_RPM_PM8921_LDO26 102 +-#define QCOM_RPM_PM8921_LDO27 103 +-#define QCOM_RPM_PM8921_LDO28 104 +-#define QCOM_RPM_PM8921_LDO29 105 +-#define QCOM_RPM_PM8921_LVS1 106 +-#define QCOM_RPM_PM8921_LVS2 107 +-#define QCOM_RPM_PM8921_LVS3 108 +-#define QCOM_RPM_PM8921_LVS4 109 +-#define QCOM_RPM_PM8921_LVS5 110 +-#define QCOM_RPM_PM8921_LVS6 111 +-#define QCOM_RPM_PM8921_LVS7 112 +-#define QCOM_RPM_PM8921_MVS 113 +-#define QCOM_RPM_PM8921_NCP 114 +-#define QCOM_RPM_PM8921_SMPS1 115 +-#define QCOM_RPM_PM8921_SMPS2 116 +-#define QCOM_RPM_PM8921_SMPS3 117 +-#define QCOM_RPM_PM8921_SMPS4 118 +-#define QCOM_RPM_PM8921_SMPS5 119 +-#define QCOM_RPM_PM8921_SMPS6 120 +-#define QCOM_RPM_PM8921_SMPS7 121 +-#define QCOM_RPM_PM8921_SMPS8 122 +-#define QCOM_RPM_PXO_CLK 123 +-#define QCOM_RPM_QDSS_CLK 124 +-#define QCOM_RPM_SFPB_CLK 125 +-#define QCOM_RPM_SMI_CLK 126 +-#define QCOM_RPM_SYS_FABRIC_ARB 127 +-#define QCOM_RPM_SYS_FABRIC_CLK 128 +-#define QCOM_RPM_SYS_FABRIC_HALT 129 +-#define QCOM_RPM_SYS_FABRIC_IOCTL 130 +-#define QCOM_RPM_SYS_FABRIC_MODE 131 +-#define QCOM_RPM_USB_OTG_SWITCH 132 +-#define QCOM_RPM_VDDMIN_GPIO 133 +-#define QCOM_RPM_NSS_FABRIC_0_CLK 134 +-#define QCOM_RPM_NSS_FABRIC_1_CLK 135 +-#define QCOM_RPM_SMB208_S1a 136 +-#define QCOM_RPM_SMB208_S1b 137 +-#define QCOM_RPM_SMB208_S2a 138 +-#define QCOM_RPM_SMB208_S2b 139 +-#define QCOM_RPM_PM8018_SMPS1 140 +-#define QCOM_RPM_PM8018_SMPS2 141 +-#define QCOM_RPM_PM8018_SMPS3 142 +-#define QCOM_RPM_PM8018_SMPS4 143 +-#define QCOM_RPM_PM8018_SMPS5 144 +-#define QCOM_RPM_PM8018_LDO1 145 +-#define QCOM_RPM_PM8018_LDO2 146 +-#define QCOM_RPM_PM8018_LDO3 147 +-#define QCOM_RPM_PM8018_LDO4 148 +-#define QCOM_RPM_PM8018_LDO5 149 +-#define QCOM_RPM_PM8018_LDO6 150 +-#define QCOM_RPM_PM8018_LDO7 151 +-#define QCOM_RPM_PM8018_LDO8 152 +-#define QCOM_RPM_PM8018_LDO9 153 +-#define QCOM_RPM_PM8018_LDO10 154 +-#define QCOM_RPM_PM8018_LDO11 155 +-#define QCOM_RPM_PM8018_LDO12 156 +-#define QCOM_RPM_PM8018_LDO13 157 +-#define QCOM_RPM_PM8018_LDO14 158 +-#define QCOM_RPM_PM8018_LVS1 159 +-#define QCOM_RPM_PM8018_NCP 160 +-#define QCOM_RPM_VOLTAGE_CORNER 161 +- +-/* +- * Constants used to select force mode for regulators. +- */ +-#define QCOM_RPM_FORCE_MODE_NONE 0 +-#define QCOM_RPM_FORCE_MODE_LPM 1 +-#define QCOM_RPM_FORCE_MODE_HPM 2 +-#define QCOM_RPM_FORCE_MODE_AUTO 3 +-#define QCOM_RPM_FORCE_MODE_BYPASS 4 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mfd/st,stpmic1.h b/scripts/dtc/include-prefixes/dt-bindings/mfd/st,stpmic1.h +deleted file mode 100644 +index 321cd08797d9..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mfd/st,stpmic1.h ++++ /dev/null +@@ -1,50 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) STMicroelectronics 2018 - All Rights Reserved +- * Author: Philippe Peurichard , +- * Pascal Paillet for STMicroelectronics. +- */ +- +-#ifndef __DT_BINDINGS_STPMIC1_H__ +-#define __DT_BINDINGS_STPMIC1_H__ +- +-/* IRQ definitions */ +-#define IT_PONKEY_F 0 +-#define IT_PONKEY_R 1 +-#define IT_WAKEUP_F 2 +-#define IT_WAKEUP_R 3 +-#define IT_VBUS_OTG_F 4 +-#define IT_VBUS_OTG_R 5 +-#define IT_SWOUT_F 6 +-#define IT_SWOUT_R 7 +- +-#define IT_CURLIM_BUCK1 8 +-#define IT_CURLIM_BUCK2 9 +-#define IT_CURLIM_BUCK3 10 +-#define IT_CURLIM_BUCK4 11 +-#define IT_OCP_OTG 12 +-#define IT_OCP_SWOUT 13 +-#define IT_OCP_BOOST 14 +-#define IT_OVP_BOOST 15 +- +-#define IT_CURLIM_LDO1 16 +-#define IT_CURLIM_LDO2 17 +-#define IT_CURLIM_LDO3 18 +-#define IT_CURLIM_LDO4 19 +-#define IT_CURLIM_LDO5 20 +-#define IT_CURLIM_LDO6 21 +-#define IT_SHORT_SWOTG 22 +-#define IT_SHORT_SWOUT 23 +- +-#define IT_TWARN_F 24 +-#define IT_TWARN_R 25 +-#define IT_VINLOW_F 26 +-#define IT_VINLOW_R 27 +-#define IT_SWIN_F 30 +-#define IT_SWIN_R 31 +- +-/* BUCK MODES definitions */ +-#define STPMIC1_BUCK_MODE_NORMAL 0 +-#define STPMIC1_BUCK_MODE_LP 2 +- +-#endif /* __DT_BINDINGS_STPMIC1_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mfd/st-lpc.h b/scripts/dtc/include-prefixes/dt-bindings/mfd/st-lpc.h +deleted file mode 100644 +index 88a7f56843bc..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mfd/st-lpc.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides shared DT/Driver defines for ST's LPC device +- * +- * Copyright (C) 2014 STMicroelectronics -- All Rights Reserved +- * +- * Author: Lee Jones for STMicroelectronics +- */ +- +-#ifndef __DT_BINDINGS_ST_LPC_H__ +-#define __DT_BINDINGS_ST_LPC_H__ +- +-#define ST_LPC_MODE_RTC 0 +-#define ST_LPC_MODE_WDT 1 +-#define ST_LPC_MODE_CLKSRC 2 +- +-#endif /* __DT_BINDINGS_ST_LPC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mfd/stm32f4-rcc.h b/scripts/dtc/include-prefixes/dt-bindings/mfd/stm32f4-rcc.h +deleted file mode 100644 +index 309e8c79f27b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mfd/stm32f4-rcc.h ++++ /dev/null +@@ -1,109 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for the STM32F4 RCC IP +- */ +- +-#ifndef _DT_BINDINGS_MFD_STM32F4_RCC_H +-#define _DT_BINDINGS_MFD_STM32F4_RCC_H +- +-/* AHB1 */ +-#define STM32F4_RCC_AHB1_GPIOA 0 +-#define STM32F4_RCC_AHB1_GPIOB 1 +-#define STM32F4_RCC_AHB1_GPIOC 2 +-#define STM32F4_RCC_AHB1_GPIOD 3 +-#define STM32F4_RCC_AHB1_GPIOE 4 +-#define STM32F4_RCC_AHB1_GPIOF 5 +-#define STM32F4_RCC_AHB1_GPIOG 6 +-#define STM32F4_RCC_AHB1_GPIOH 7 +-#define STM32F4_RCC_AHB1_GPIOI 8 +-#define STM32F4_RCC_AHB1_GPIOJ 9 +-#define STM32F4_RCC_AHB1_GPIOK 10 +-#define STM32F4_RCC_AHB1_CRC 12 +-#define STM32F4_RCC_AHB1_BKPSRAM 18 +-#define STM32F4_RCC_AHB1_CCMDATARAM 20 +-#define STM32F4_RCC_AHB1_DMA1 21 +-#define STM32F4_RCC_AHB1_DMA2 22 +-#define STM32F4_RCC_AHB1_DMA2D 23 +-#define STM32F4_RCC_AHB1_ETHMAC 25 +-#define STM32F4_RCC_AHB1_ETHMACTX 26 +-#define STM32F4_RCC_AHB1_ETHMACRX 27 +-#define STM32F4_RCC_AHB1_ETHMACPTP 28 +-#define STM32F4_RCC_AHB1_OTGHS 29 +-#define STM32F4_RCC_AHB1_OTGHSULPI 30 +- +-#define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) +-#define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) +- +- +-/* AHB2 */ +-#define STM32F4_RCC_AHB2_DCMI 0 +-#define STM32F4_RCC_AHB2_CRYP 4 +-#define STM32F4_RCC_AHB2_HASH 5 +-#define STM32F4_RCC_AHB2_RNG 6 +-#define STM32F4_RCC_AHB2_OTGFS 7 +- +-#define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) +-#define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) +- +-/* AHB3 */ +-#define STM32F4_RCC_AHB3_FMC 0 +-#define STM32F4_RCC_AHB3_QSPI 1 +- +-#define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) +-#define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) +- +-/* APB1 */ +-#define STM32F4_RCC_APB1_TIM2 0 +-#define STM32F4_RCC_APB1_TIM3 1 +-#define STM32F4_RCC_APB1_TIM4 2 +-#define STM32F4_RCC_APB1_TIM5 3 +-#define STM32F4_RCC_APB1_TIM6 4 +-#define STM32F4_RCC_APB1_TIM7 5 +-#define STM32F4_RCC_APB1_TIM12 6 +-#define STM32F4_RCC_APB1_TIM13 7 +-#define STM32F4_RCC_APB1_TIM14 8 +-#define STM32F4_RCC_APB1_WWDG 11 +-#define STM32F4_RCC_APB1_SPI2 14 +-#define STM32F4_RCC_APB1_SPI3 15 +-#define STM32F4_RCC_APB1_UART2 17 +-#define STM32F4_RCC_APB1_UART3 18 +-#define STM32F4_RCC_APB1_UART4 19 +-#define STM32F4_RCC_APB1_UART5 20 +-#define STM32F4_RCC_APB1_I2C1 21 +-#define STM32F4_RCC_APB1_I2C2 22 +-#define STM32F4_RCC_APB1_I2C3 23 +-#define STM32F4_RCC_APB1_CAN1 25 +-#define STM32F4_RCC_APB1_CAN2 26 +-#define STM32F4_RCC_APB1_PWR 28 +-#define STM32F4_RCC_APB1_DAC 29 +-#define STM32F4_RCC_APB1_UART7 30 +-#define STM32F4_RCC_APB1_UART8 31 +- +-#define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) +-#define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) +- +-/* APB2 */ +-#define STM32F4_RCC_APB2_TIM1 0 +-#define STM32F4_RCC_APB2_TIM8 1 +-#define STM32F4_RCC_APB2_USART1 4 +-#define STM32F4_RCC_APB2_USART6 5 +-#define STM32F4_RCC_APB2_ADC1 8 +-#define STM32F4_RCC_APB2_ADC2 9 +-#define STM32F4_RCC_APB2_ADC3 10 +-#define STM32F4_RCC_APB2_SDIO 11 +-#define STM32F4_RCC_APB2_SPI1 12 +-#define STM32F4_RCC_APB2_SPI4 13 +-#define STM32F4_RCC_APB2_SYSCFG 14 +-#define STM32F4_RCC_APB2_TIM9 16 +-#define STM32F4_RCC_APB2_TIM10 17 +-#define STM32F4_RCC_APB2_TIM11 18 +-#define STM32F4_RCC_APB2_SPI5 20 +-#define STM32F4_RCC_APB2_SPI6 21 +-#define STM32F4_RCC_APB2_SAI1 22 +-#define STM32F4_RCC_APB2_LTDC 26 +-#define STM32F4_RCC_APB2_DSI 27 +- +-#define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) +-#define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) +- +-#endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mfd/stm32f7-rcc.h b/scripts/dtc/include-prefixes/dt-bindings/mfd/stm32f7-rcc.h +deleted file mode 100644 +index a90f3613c584..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mfd/stm32f7-rcc.h ++++ /dev/null +@@ -1,114 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for the STM32F7 RCC IP +- */ +- +-#ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H +-#define _DT_BINDINGS_MFD_STM32F7_RCC_H +- +-/* AHB1 */ +-#define STM32F7_RCC_AHB1_GPIOA 0 +-#define STM32F7_RCC_AHB1_GPIOB 1 +-#define STM32F7_RCC_AHB1_GPIOC 2 +-#define STM32F7_RCC_AHB1_GPIOD 3 +-#define STM32F7_RCC_AHB1_GPIOE 4 +-#define STM32F7_RCC_AHB1_GPIOF 5 +-#define STM32F7_RCC_AHB1_GPIOG 6 +-#define STM32F7_RCC_AHB1_GPIOH 7 +-#define STM32F7_RCC_AHB1_GPIOI 8 +-#define STM32F7_RCC_AHB1_GPIOJ 9 +-#define STM32F7_RCC_AHB1_GPIOK 10 +-#define STM32F7_RCC_AHB1_CRC 12 +-#define STM32F7_RCC_AHB1_BKPSRAM 18 +-#define STM32F7_RCC_AHB1_DTCMRAM 20 +-#define STM32F7_RCC_AHB1_DMA1 21 +-#define STM32F7_RCC_AHB1_DMA2 22 +-#define STM32F7_RCC_AHB1_DMA2D 23 +-#define STM32F7_RCC_AHB1_ETHMAC 25 +-#define STM32F7_RCC_AHB1_ETHMACTX 26 +-#define STM32F7_RCC_AHB1_ETHMACRX 27 +-#define STM32FF_RCC_AHB1_ETHMACPTP 28 +-#define STM32F7_RCC_AHB1_OTGHS 29 +-#define STM32F7_RCC_AHB1_OTGHSULPI 30 +- +-#define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8)) +-#define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit) +- +- +-/* AHB2 */ +-#define STM32F7_RCC_AHB2_DCMI 0 +-#define STM32F7_RCC_AHB2_CRYP 4 +-#define STM32F7_RCC_AHB2_HASH 5 +-#define STM32F7_RCC_AHB2_RNG 6 +-#define STM32F7_RCC_AHB2_OTGFS 7 +- +-#define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8)) +-#define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20) +- +-/* AHB3 */ +-#define STM32F7_RCC_AHB3_FMC 0 +-#define STM32F7_RCC_AHB3_QSPI 1 +- +-#define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8)) +-#define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40) +- +-/* APB1 */ +-#define STM32F7_RCC_APB1_TIM2 0 +-#define STM32F7_RCC_APB1_TIM3 1 +-#define STM32F7_RCC_APB1_TIM4 2 +-#define STM32F7_RCC_APB1_TIM5 3 +-#define STM32F7_RCC_APB1_TIM6 4 +-#define STM32F7_RCC_APB1_TIM7 5 +-#define STM32F7_RCC_APB1_TIM12 6 +-#define STM32F7_RCC_APB1_TIM13 7 +-#define STM32F7_RCC_APB1_TIM14 8 +-#define STM32F7_RCC_APB1_LPTIM1 9 +-#define STM32F7_RCC_APB1_WWDG 11 +-#define STM32F7_RCC_APB1_SPI2 14 +-#define STM32F7_RCC_APB1_SPI3 15 +-#define STM32F7_RCC_APB1_SPDIFRX 16 +-#define STM32F7_RCC_APB1_UART2 17 +-#define STM32F7_RCC_APB1_UART3 18 +-#define STM32F7_RCC_APB1_UART4 19 +-#define STM32F7_RCC_APB1_UART5 20 +-#define STM32F7_RCC_APB1_I2C1 21 +-#define STM32F7_RCC_APB1_I2C2 22 +-#define STM32F7_RCC_APB1_I2C3 23 +-#define STM32F7_RCC_APB1_I2C4 24 +-#define STM32F7_RCC_APB1_CAN1 25 +-#define STM32F7_RCC_APB1_CAN2 26 +-#define STM32F7_RCC_APB1_CEC 27 +-#define STM32F7_RCC_APB1_PWR 28 +-#define STM32F7_RCC_APB1_DAC 29 +-#define STM32F7_RCC_APB1_UART7 30 +-#define STM32F7_RCC_APB1_UART8 31 +- +-#define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8)) +-#define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80) +- +-/* APB2 */ +-#define STM32F7_RCC_APB2_TIM1 0 +-#define STM32F7_RCC_APB2_TIM8 1 +-#define STM32F7_RCC_APB2_USART1 4 +-#define STM32F7_RCC_APB2_USART6 5 +-#define STM32F7_RCC_APB2_SDMMC2 7 +-#define STM32F7_RCC_APB2_ADC1 8 +-#define STM32F7_RCC_APB2_ADC2 9 +-#define STM32F7_RCC_APB2_ADC3 10 +-#define STM32F7_RCC_APB2_SDMMC1 11 +-#define STM32F7_RCC_APB2_SPI1 12 +-#define STM32F7_RCC_APB2_SPI4 13 +-#define STM32F7_RCC_APB2_SYSCFG 14 +-#define STM32F7_RCC_APB2_TIM9 16 +-#define STM32F7_RCC_APB2_TIM10 17 +-#define STM32F7_RCC_APB2_TIM11 18 +-#define STM32F7_RCC_APB2_SPI5 20 +-#define STM32F7_RCC_APB2_SPI6 21 +-#define STM32F7_RCC_APB2_SAI1 22 +-#define STM32F7_RCC_APB2_SAI2 23 +-#define STM32F7_RCC_APB2_LTDC 26 +- +-#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) +-#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) +- +-#endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mfd/stm32h7-rcc.h b/scripts/dtc/include-prefixes/dt-bindings/mfd/stm32h7-rcc.h +deleted file mode 100644 +index 461a8e04453a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mfd/stm32h7-rcc.h ++++ /dev/null +@@ -1,136 +0,0 @@ +-/* +- * This header provides constants for the STM32H7 RCC IP +- */ +- +-#ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H +-#define _DT_BINDINGS_MFD_STM32H7_RCC_H +- +-/* AHB3 */ +-#define STM32H7_RCC_AHB3_MDMA 0 +-#define STM32H7_RCC_AHB3_DMA2D 4 +-#define STM32H7_RCC_AHB3_JPGDEC 5 +-#define STM32H7_RCC_AHB3_FMC 12 +-#define STM32H7_RCC_AHB3_QUADSPI 14 +-#define STM32H7_RCC_AHB3_SDMMC1 16 +-#define STM32H7_RCC_AHB3_CPU 31 +- +-#define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8)) +- +-/* AHB1 */ +-#define STM32H7_RCC_AHB1_DMA1 0 +-#define STM32H7_RCC_AHB1_DMA2 1 +-#define STM32H7_RCC_AHB1_ADC12 5 +-#define STM32H7_RCC_AHB1_ART 14 +-#define STM32H7_RCC_AHB1_ETH1MAC 15 +-#define STM32H7_RCC_AHB1_USB1OTG 25 +-#define STM32H7_RCC_AHB1_USB2OTG 27 +- +-#define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8)) +- +-/* AHB2 */ +-#define STM32H7_RCC_AHB2_CAMITF 0 +-#define STM32H7_RCC_AHB2_CRYPT 4 +-#define STM32H7_RCC_AHB2_HASH 5 +-#define STM32H7_RCC_AHB2_RNG 6 +-#define STM32H7_RCC_AHB2_SDMMC2 9 +- +-#define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8)) +- +-/* AHB4 */ +-#define STM32H7_RCC_AHB4_GPIOA 0 +-#define STM32H7_RCC_AHB4_GPIOB 1 +-#define STM32H7_RCC_AHB4_GPIOC 2 +-#define STM32H7_RCC_AHB4_GPIOD 3 +-#define STM32H7_RCC_AHB4_GPIOE 4 +-#define STM32H7_RCC_AHB4_GPIOF 5 +-#define STM32H7_RCC_AHB4_GPIOG 6 +-#define STM32H7_RCC_AHB4_GPIOH 7 +-#define STM32H7_RCC_AHB4_GPIOI 8 +-#define STM32H7_RCC_AHB4_GPIOJ 9 +-#define STM32H7_RCC_AHB4_GPIOK 10 +-#define STM32H7_RCC_AHB4_CRC 19 +-#define STM32H7_RCC_AHB4_BDMA 21 +-#define STM32H7_RCC_AHB4_ADC3 24 +-#define STM32H7_RCC_AHB4_HSEM 25 +- +-#define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8)) +- +-/* APB3 */ +-#define STM32H7_RCC_APB3_LTDC 3 +-#define STM32H7_RCC_APB3_DSI 4 +- +-#define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8)) +- +-/* APB1L */ +-#define STM32H7_RCC_APB1L_TIM2 0 +-#define STM32H7_RCC_APB1L_TIM3 1 +-#define STM32H7_RCC_APB1L_TIM4 2 +-#define STM32H7_RCC_APB1L_TIM5 3 +-#define STM32H7_RCC_APB1L_TIM6 4 +-#define STM32H7_RCC_APB1L_TIM7 5 +-#define STM32H7_RCC_APB1L_TIM12 6 +-#define STM32H7_RCC_APB1L_TIM13 7 +-#define STM32H7_RCC_APB1L_TIM14 8 +-#define STM32H7_RCC_APB1L_LPTIM1 9 +-#define STM32H7_RCC_APB1L_SPI2 14 +-#define STM32H7_RCC_APB1L_SPI3 15 +-#define STM32H7_RCC_APB1L_SPDIF_RX 16 +-#define STM32H7_RCC_APB1L_USART2 17 +-#define STM32H7_RCC_APB1L_USART3 18 +-#define STM32H7_RCC_APB1L_UART4 19 +-#define STM32H7_RCC_APB1L_UART5 20 +-#define STM32H7_RCC_APB1L_I2C1 21 +-#define STM32H7_RCC_APB1L_I2C2 22 +-#define STM32H7_RCC_APB1L_I2C3 23 +-#define STM32H7_RCC_APB1L_HDMICEC 27 +-#define STM32H7_RCC_APB1L_DAC12 29 +-#define STM32H7_RCC_APB1L_USART7 30 +-#define STM32H7_RCC_APB1L_USART8 31 +- +-#define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8)) +- +-/* APB1H */ +-#define STM32H7_RCC_APB1H_CRS 1 +-#define STM32H7_RCC_APB1H_SWP 2 +-#define STM32H7_RCC_APB1H_OPAMP 4 +-#define STM32H7_RCC_APB1H_MDIOS 5 +-#define STM32H7_RCC_APB1H_FDCAN 8 +- +-#define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8)) +- +-/* APB2 */ +-#define STM32H7_RCC_APB2_TIM1 0 +-#define STM32H7_RCC_APB2_TIM8 1 +-#define STM32H7_RCC_APB2_USART1 4 +-#define STM32H7_RCC_APB2_USART6 5 +-#define STM32H7_RCC_APB2_SPI1 12 +-#define STM32H7_RCC_APB2_SPI4 13 +-#define STM32H7_RCC_APB2_TIM15 16 +-#define STM32H7_RCC_APB2_TIM16 17 +-#define STM32H7_RCC_APB2_TIM17 18 +-#define STM32H7_RCC_APB2_SPI5 20 +-#define STM32H7_RCC_APB2_SAI1 22 +-#define STM32H7_RCC_APB2_SAI2 23 +-#define STM32H7_RCC_APB2_SAI3 24 +-#define STM32H7_RCC_APB2_DFSDM1 28 +-#define STM32H7_RCC_APB2_HRTIM 29 +- +-#define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8)) +- +-/* APB4 */ +-#define STM32H7_RCC_APB4_SYSCFG 1 +-#define STM32H7_RCC_APB4_LPUART1 3 +-#define STM32H7_RCC_APB4_SPI6 5 +-#define STM32H7_RCC_APB4_I2C4 7 +-#define STM32H7_RCC_APB4_LPTIM2 9 +-#define STM32H7_RCC_APB4_LPTIM3 10 +-#define STM32H7_RCC_APB4_LPTIM4 11 +-#define STM32H7_RCC_APB4_LPTIM5 12 +-#define STM32H7_RCC_APB4_COMP12 14 +-#define STM32H7_RCC_APB4_VREF 15 +-#define STM32H7_RCC_APB4_SAI4 21 +-#define STM32H7_RCC_APB4_TMPSENS 26 +- +-#define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8)) +- +-#endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mips/lantiq_rcu_gphy.h b/scripts/dtc/include-prefixes/dt-bindings/mips/lantiq_rcu_gphy.h +deleted file mode 100644 +index 7756d66cc599..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mips/lantiq_rcu_gphy.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * +- * Copyright (C) 2016 Martin Blumenstingl +- * Copyright (C) 2017 Hauke Mehrtens +- */ +-#ifndef _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H +-#define _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H +- +-#define GPHY_MODE_GE 1 +-#define GPHY_MODE_FE 2 +- +-#endif /* _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mux/mux.h b/scripts/dtc/include-prefixes/dt-bindings/mux/mux.h +deleted file mode 100644 +index 0b9d654506ef..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mux/mux.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for most Multiplexer bindings. +- * +- * Most Multiplexer bindings specify an idle state. In most cases, the +- * multiplexer can be left as is when idle, and in some cases it can +- * disconnect the input/output and leave the multiplexer in a high +- * impedance state. +- */ +- +-#ifndef _DT_BINDINGS_MUX_MUX_H +-#define _DT_BINDINGS_MUX_MUX_H +- +-#define MUX_IDLE_AS_IS (-1) +-#define MUX_IDLE_DISCONNECT (-2) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/mux/ti-serdes.h b/scripts/dtc/include-prefixes/dt-bindings/mux/ti-serdes.h +deleted file mode 100644 +index d417b9268b16..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/mux/ti-serdes.h ++++ /dev/null +@@ -1,98 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for SERDES MUX for TI SoCs +- */ +- +-#ifndef _DT_BINDINGS_MUX_TI_SERDES +-#define _DT_BINDINGS_MUX_TI_SERDES +- +-/* J721E */ +- +-#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 +-#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1 +-#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2 +-#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3 +- +-#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0 +-#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1 +-#define J721E_SERDES0_LANE1_USB3_0 0x2 +-#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3 +- +-#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0 +-#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1 +-#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2 +-#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3 +- +-#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0 +-#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1 +-#define J721E_SERDES1_LANE1_USB3_1 0x2 +-#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3 +- +-#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0 +-#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1 +-#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2 +-#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3 +- +-#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0 +-#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1 +-#define J721E_SERDES2_LANE1_USB3_1 0x2 +-#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3 +- +-#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0 +-#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1 +-#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2 +-#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3 +- +-#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0 +-#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1 +-#define J721E_SERDES3_LANE1_USB3_0 0x2 +-#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3 +- +-#define J721E_SERDES4_LANE0_EDP_LANE0 0x0 +-#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1 +-#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2 +-#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3 +- +-#define J721E_SERDES4_LANE1_EDP_LANE1 0x0 +-#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1 +-#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2 +-#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3 +- +-#define J721E_SERDES4_LANE2_EDP_LANE2 0x0 +-#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1 +-#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2 +-#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3 +- +-#define J721E_SERDES4_LANE3_EDP_LANE3 0x0 +-#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1 +-#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2 +-#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3 +- +-/* J7200 */ +- +-#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0 +-#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1 +-#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2 +-#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3 +- +-#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0 +-#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1 +-#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2 +-#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3 +- +-#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0 +-#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1 +-#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2 +-#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3 +- +-#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0 +-#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1 +-#define J7200_SERDES0_LANE3_USB 0x2 +-#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 +- +-/* AM64 */ +- +-#define AM64_SERDES0_LANE0_PCIE0 0x0 +-#define AM64_SERDES0_LANE0_USB 0x1 +- +-#endif /* _DT_BINDINGS_MUX_TI_SERDES */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/net/microchip-lan78xx.h b/scripts/dtc/include-prefixes/dt-bindings/net/microchip-lan78xx.h +deleted file mode 100644 +index 0742ff075307..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/net/microchip-lan78xx.h ++++ /dev/null +@@ -1,21 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef _DT_BINDINGS_MICROCHIP_LAN78XX_H +-#define _DT_BINDINGS_MICROCHIP_LAN78XX_H +- +-/* LED modes for LAN7800/LAN7850 embedded PHY */ +- +-#define LAN78XX_LINK_ACTIVITY 0 +-#define LAN78XX_LINK_1000_ACTIVITY 1 +-#define LAN78XX_LINK_100_ACTIVITY 2 +-#define LAN78XX_LINK_10_ACTIVITY 3 +-#define LAN78XX_LINK_100_1000_ACTIVITY 4 +-#define LAN78XX_LINK_10_1000_ACTIVITY 5 +-#define LAN78XX_LINK_10_100_ACTIVITY 6 +-#define LAN78XX_DUPLEX_COLLISION 8 +-#define LAN78XX_COLLISION 9 +-#define LAN78XX_ACTIVITY 10 +-#define LAN78XX_AUTONEG_FAULT 12 +-#define LAN78XX_FORCE_LED_OFF 14 +-#define LAN78XX_FORCE_LED_ON 15 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/net/mscc-phy-vsc8531.h b/scripts/dtc/include-prefixes/dt-bindings/net/mscc-phy-vsc8531.h +deleted file mode 100644 +index 9eb2ec2b2ea9..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/net/mscc-phy-vsc8531.h ++++ /dev/null +@@ -1,31 +0,0 @@ +-/* +- * Device Tree constants for Microsemi VSC8531 PHY +- * +- * Author: Nagaraju Lakkaraju +- * +- * License: Dual MIT/GPL +- * Copyright (c) 2017 Microsemi Corporation +- */ +- +-#ifndef _DT_BINDINGS_MSCC_VSC8531_H +-#define _DT_BINDINGS_MSCC_VSC8531_H +- +-/* PHY LED Modes */ +-#define VSC8531_LINK_ACTIVITY 0 +-#define VSC8531_LINK_1000_ACTIVITY 1 +-#define VSC8531_LINK_100_ACTIVITY 2 +-#define VSC8531_LINK_10_ACTIVITY 3 +-#define VSC8531_LINK_100_1000_ACTIVITY 4 +-#define VSC8531_LINK_10_1000_ACTIVITY 5 +-#define VSC8531_LINK_10_100_ACTIVITY 6 +-#define VSC8584_LINK_100FX_1000X_ACTIVITY 7 +-#define VSC8531_DUPLEX_COLLISION 8 +-#define VSC8531_COLLISION 9 +-#define VSC8531_ACTIVITY 10 +-#define VSC8584_100FX_1000X_ACTIVITY 11 +-#define VSC8531_AUTONEG_FAULT 12 +-#define VSC8531_SERIAL_MODE 13 +-#define VSC8531_FORCE_LED_OFF 14 +-#define VSC8531_FORCE_LED_ON 15 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/net/qca-ar803x.h b/scripts/dtc/include-prefixes/dt-bindings/net/qca-ar803x.h +deleted file mode 100644 +index 9c046c7242ed..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/net/qca-ar803x.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Device Tree constants for the Qualcomm Atheros AR803x PHYs +- */ +- +-#ifndef _DT_BINDINGS_QCA_AR803X_H +-#define _DT_BINDINGS_QCA_AR803X_H +- +-#define AR803X_STRENGTH_FULL 0 +-#define AR803X_STRENGTH_HALF 1 +-#define AR803X_STRENGTH_QUARTER 2 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/net/ti-dp83867.h b/scripts/dtc/include-prefixes/dt-bindings/net/ti-dp83867.h +deleted file mode 100644 +index 6fc4b445d3a1..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/net/ti-dp83867.h ++++ /dev/null +@@ -1,53 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Device Tree constants for the Texas Instruments DP83867 PHY +- * +- * Author: Dan Murphy +- * +- * Copyright: (C) 2015 Texas Instruments, Inc. +- */ +- +-#ifndef _DT_BINDINGS_TI_DP83867_H +-#define _DT_BINDINGS_TI_DP83867_H +- +-/* PHY CTRL bits */ +-#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 +-#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 +-#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 +-#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 +- +-/* RGMIIDCTL internal delay for rx and tx */ +-#define DP83867_RGMIIDCTL_250_PS 0x0 +-#define DP83867_RGMIIDCTL_500_PS 0x1 +-#define DP83867_RGMIIDCTL_750_PS 0x2 +-#define DP83867_RGMIIDCTL_1_NS 0x3 +-#define DP83867_RGMIIDCTL_1_25_NS 0x4 +-#define DP83867_RGMIIDCTL_1_50_NS 0x5 +-#define DP83867_RGMIIDCTL_1_75_NS 0x6 +-#define DP83867_RGMIIDCTL_2_00_NS 0x7 +-#define DP83867_RGMIIDCTL_2_25_NS 0x8 +-#define DP83867_RGMIIDCTL_2_50_NS 0x9 +-#define DP83867_RGMIIDCTL_2_75_NS 0xa +-#define DP83867_RGMIIDCTL_3_00_NS 0xb +-#define DP83867_RGMIIDCTL_3_25_NS 0xc +-#define DP83867_RGMIIDCTL_3_50_NS 0xd +-#define DP83867_RGMIIDCTL_3_75_NS 0xe +-#define DP83867_RGMIIDCTL_4_00_NS 0xf +- +-/* IO_MUX_CFG - Clock output selection */ +-#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 +-#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 +-#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 +-#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 +-#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 +-#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 +-#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 +-#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 +-#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 +-#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 +-#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA +-#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB +-#define DP83867_CLK_O_SEL_REF_CLK 0xC +-/* Special flag to indicate clock should be off */ +-#define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/net/ti-dp83869.h b/scripts/dtc/include-prefixes/dt-bindings/net/ti-dp83869.h +deleted file mode 100644 +index 218b1a64e975..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/net/ti-dp83869.h ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Device Tree constants for the Texas Instruments DP83869 PHY +- * +- * Author: Dan Murphy +- * +- * Copyright: (C) 2019 Texas Instruments, Inc. +- */ +- +-#ifndef _DT_BINDINGS_TI_DP83869_H +-#define _DT_BINDINGS_TI_DP83869_H +- +-/* PHY CTRL bits */ +-#define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 +-#define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 +-#define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 +-#define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 +- +-/* IO_MUX_CFG - Clock output selection */ +-#define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0 +-#define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1 +-#define DP83869_CLK_O_SEL_CHN_C_RCLK 0x2 +-#define DP83869_CLK_O_SEL_CHN_D_RCLK 0x3 +-#define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 +-#define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 +-#define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 +-#define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 +-#define DP83869_CLK_O_SEL_CHN_A_TCLK 0x8 +-#define DP83869_CLK_O_SEL_CHN_B_TCLK 0x9 +-#define DP83869_CLK_O_SEL_CHN_C_TCLK 0xa +-#define DP83869_CLK_O_SEL_CHN_D_TCLK 0xb +-#define DP83869_CLK_O_SEL_REF_CLK 0xc +- +-#define DP83869_RGMII_COPPER_ETHERNET 0x00 +-#define DP83869_RGMII_1000_BASE 0x01 +-#define DP83869_RGMII_100_BASE 0x02 +-#define DP83869_RGMII_SGMII_BRIDGE 0x03 +-#define DP83869_1000M_MEDIA_CONVERT 0x04 +-#define DP83869_100M_MEDIA_CONVERT 0x05 +-#define DP83869_SGMII_COPPER_ETHERNET 0x06 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/phy/phy-am654-serdes.h b/scripts/dtc/include-prefixes/dt-bindings/phy/phy-am654-serdes.h +deleted file mode 100644 +index e8d901729ed9..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/phy/phy-am654-serdes.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for AM654 SERDES. +- */ +- +-#ifndef _DT_BINDINGS_AM654_SERDES +-#define _DT_BINDINGS_AM654_SERDES +- +-#define AM654_SERDES_CMU_REFCLK 0 +-#define AM654_SERDES_LO_REFCLK 1 +-#define AM654_SERDES_RO_REFCLK 2 +- +-#endif /* _DT_BINDINGS_AM654_SERDES */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/phy/phy-cadence.h b/scripts/dtc/include-prefixes/dt-bindings/phy/phy-cadence.h +deleted file mode 100644 +index 4652bcb86265..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/phy/phy-cadence.h ++++ /dev/null +@@ -1,20 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for Cadence SERDES. +- */ +- +-#ifndef _DT_BINDINGS_CADENCE_SERDES_H +-#define _DT_BINDINGS_CADENCE_SERDES_H +- +-/* Torrent */ +-#define TORRENT_SERDES_NO_SSC 0 +-#define TORRENT_SERDES_EXTERNAL_SSC 1 +-#define TORRENT_SERDES_INTERNAL_SSC 2 +- +-#define CDNS_TORRENT_REFCLK_DRIVER 0 +- +-/* Sierra */ +-#define CDNS_SIERRA_PLL_CMNLC 0 +-#define CDNS_SIERRA_PLL_CMNLC1 1 +- +-#endif /* _DT_BINDINGS_CADENCE_SERDES_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/phy/phy-lantiq-vrx200-pcie.h b/scripts/dtc/include-prefixes/dt-bindings/phy/phy-lantiq-vrx200-pcie.h +deleted file mode 100644 +index 95a7896356d6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/phy/phy-lantiq-vrx200-pcie.h ++++ /dev/null +@@ -1,11 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2019 Martin Blumenstingl +- */ +- +-#define LANTIQ_PCIE_PHY_MODE_25MHZ 0 +-#define LANTIQ_PCIE_PHY_MODE_25MHZ_SSC 1 +-#define LANTIQ_PCIE_PHY_MODE_36MHZ 2 +-#define LANTIQ_PCIE_PHY_MODE_36MHZ_SSC 3 +-#define LANTIQ_PCIE_PHY_MODE_100MHZ 4 +-#define LANTIQ_PCIE_PHY_MODE_100MHZ_SSC 5 +diff --git a/scripts/dtc/include-prefixes/dt-bindings/phy/phy-ocelot-serdes.h b/scripts/dtc/include-prefixes/dt-bindings/phy/phy-ocelot-serdes.h +deleted file mode 100644 +index fe70adaca68f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/phy/phy-ocelot-serdes.h ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +-/* Copyright (c) 2018 Microsemi Corporation */ +-#ifndef __PHY_OCELOT_SERDES_H__ +-#define __PHY_OCELOT_SERDES_H__ +- +-#define SERDES1G(x) (x) +-#define SERDES1G_MAX SERDES1G(5) +-#define SERDES6G(x) (SERDES1G_MAX + 1 + (x)) +-#define SERDES6G_MAX SERDES6G(2) +-#define SERDES_MAX (SERDES6G_MAX + 1) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/phy/phy-pistachio-usb.h b/scripts/dtc/include-prefixes/dt-bindings/phy/phy-pistachio-usb.h +deleted file mode 100644 +index 3542a67dafb5..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/phy/phy-pistachio-usb.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2015 Google, Inc. +- */ +- +-#ifndef _DT_BINDINGS_PHY_PISTACHIO +-#define _DT_BINDINGS_PHY_PISTACHIO +- +-#define REFCLK_XO_CRYSTAL 0x0 +-#define REFCLK_X0_EXT_CLK 0x1 +-#define REFCLK_CLK_CORE 0x2 +- +-#endif /* _DT_BINDINGS_PHY_PISTACHIO */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/phy/phy-qcom-qusb2.h b/scripts/dtc/include-prefixes/dt-bindings/phy/phy-qcom-qusb2.h +deleted file mode 100644 +index 5c5e4d800cac..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/phy/phy-qcom-qusb2.h ++++ /dev/null +@@ -1,37 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2018, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_QCOM_PHY_QUSB2_H_ +-#define _DT_BINDINGS_QCOM_PHY_QUSB2_H_ +- +-/* PHY HSTX TRIM bit values (24mA to 15mA) */ +-#define QUSB2_V2_HSTX_TRIM_24_0_MA 0x0 +-#define QUSB2_V2_HSTX_TRIM_23_4_MA 0x1 +-#define QUSB2_V2_HSTX_TRIM_22_8_MA 0x2 +-#define QUSB2_V2_HSTX_TRIM_22_2_MA 0x3 +-#define QUSB2_V2_HSTX_TRIM_21_6_MA 0x4 +-#define QUSB2_V2_HSTX_TRIM_21_0_MA 0x5 +-#define QUSB2_V2_HSTX_TRIM_20_4_MA 0x6 +-#define QUSB2_V2_HSTX_TRIM_19_8_MA 0x7 +-#define QUSB2_V2_HSTX_TRIM_19_2_MA 0x8 +-#define QUSB2_V2_HSTX_TRIM_18_6_MA 0x9 +-#define QUSB2_V2_HSTX_TRIM_18_0_MA 0xa +-#define QUSB2_V2_HSTX_TRIM_17_4_MA 0xb +-#define QUSB2_V2_HSTX_TRIM_16_8_MA 0xc +-#define QUSB2_V2_HSTX_TRIM_16_2_MA 0xd +-#define QUSB2_V2_HSTX_TRIM_15_6_MA 0xe +-#define QUSB2_V2_HSTX_TRIM_15_0_MA 0xf +- +-/* PHY PREEMPHASIS bit values */ +-#define QUSB2_V2_PREEMPHASIS_NONE 0 +-#define QUSB2_V2_PREEMPHASIS_5_PERCENT 1 +-#define QUSB2_V2_PREEMPHASIS_10_PERCENT 2 +-#define QUSB2_V2_PREEMPHASIS_15_PERCENT 3 +- +-/* PHY PREEMPHASIS-WIDTH bit values */ +-#define QUSB2_V2_PREEMPHASIS_WIDTH_FULL_BIT 0 +-#define QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/phy/phy-ti.h b/scripts/dtc/include-prefixes/dt-bindings/phy/phy-ti.h +deleted file mode 100644 +index ad955d3a56b4..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/phy/phy-ti.h ++++ /dev/null +@@ -1,21 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for TI SERDES. +- */ +- +-#ifndef _DT_BINDINGS_TI_SERDES +-#define _DT_BINDINGS_TI_SERDES +- +-/* Clock index for output clocks from WIZ */ +- +-/* MUX Clocks */ +-#define TI_WIZ_PLL0_REFCLK 0 +-#define TI_WIZ_PLL1_REFCLK 1 +-#define TI_WIZ_REFCLK_DIG 2 +- +-/* Reserve index here for future additions */ +- +-/* MISC Clocks */ +-#define TI_WIZ_PHY_EN_REFCLK 16 +- +-#endif /* _DT_BINDINGS_TI_SERDES */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/phy/phy.h b/scripts/dtc/include-prefixes/dt-bindings/phy/phy.h +deleted file mode 100644 +index f48c9acf251e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/phy/phy.h ++++ /dev/null +@@ -1,26 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * +- * This header provides constants for the phy framework +- * +- * Copyright (C) 2014 STMicroelectronics +- * Author: Gabriel Fernandez +- */ +- +-#ifndef _DT_BINDINGS_PHY +-#define _DT_BINDINGS_PHY +- +-#define PHY_NONE 0 +-#define PHY_TYPE_SATA 1 +-#define PHY_TYPE_PCIE 2 +-#define PHY_TYPE_USB2 3 +-#define PHY_TYPE_USB3 4 +-#define PHY_TYPE_UFS 5 +-#define PHY_TYPE_DP 6 +-#define PHY_TYPE_XPCS 7 +-#define PHY_TYPE_SGMII 8 +-#define PHY_TYPE_QSGMII 9 +-#define PHY_TYPE_DPHY 10 +-#define PHY_TYPE_CPHY 11 +- +-#endif /* _DT_BINDINGS_PHY */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/am33xx.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/am33xx.h +deleted file mode 100644 +index 17877e85980b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/am33xx.h ++++ /dev/null +@@ -1,172 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants specific to AM33XX pinctrl bindings. +- */ +- +-#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H +-#define _DT_BINDINGS_PINCTRL_AM33XX_H +- +-#include +- +-/* am33xx specific mux bit defines */ +-#undef PULL_ENA +-#undef INPUT_EN +- +-#define PULL_DISABLE (1 << 3) +-#define INPUT_EN (1 << 5) +-#define SLEWCTRL_SLOW (1 << 6) +-#define SLEWCTRL_FAST 0 +- +-/* update macro depending on INPUT_EN and PULL_ENA */ +-#undef PIN_OUTPUT +-#undef PIN_OUTPUT_PULLUP +-#undef PIN_OUTPUT_PULLDOWN +-#undef PIN_INPUT +-#undef PIN_INPUT_PULLUP +-#undef PIN_INPUT_PULLDOWN +- +-#define PIN_OUTPUT (PULL_DISABLE) +-#define PIN_OUTPUT_PULLUP (PULL_UP) +-#define PIN_OUTPUT_PULLDOWN 0 +-#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +-#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +-#define PIN_INPUT_PULLDOWN (INPUT_EN) +- +-/* undef non-existing modes */ +-#undef PIN_OFF_NONE +-#undef PIN_OFF_OUTPUT_HIGH +-#undef PIN_OFF_OUTPUT_LOW +-#undef PIN_OFF_INPUT_PULLUP +-#undef PIN_OFF_INPUT_PULLDOWN +-#undef PIN_OFF_WAKEUPENABLE +- +-#define AM335X_PIN_OFFSET_MIN 0x0800U +- +-#define AM335X_PIN_GPMC_AD0 0x800 +-#define AM335X_PIN_GPMC_AD1 0x804 +-#define AM335X_PIN_GPMC_AD2 0x808 +-#define AM335X_PIN_GPMC_AD3 0x80c +-#define AM335X_PIN_GPMC_AD4 0x810 +-#define AM335X_PIN_GPMC_AD5 0x814 +-#define AM335X_PIN_GPMC_AD6 0x818 +-#define AM335X_PIN_GPMC_AD7 0x81c +-#define AM335X_PIN_GPMC_AD8 0x820 +-#define AM335X_PIN_GPMC_AD9 0x824 +-#define AM335X_PIN_GPMC_AD10 0x828 +-#define AM335X_PIN_GPMC_AD11 0x82c +-#define AM335X_PIN_GPMC_AD12 0x830 +-#define AM335X_PIN_GPMC_AD13 0x834 +-#define AM335X_PIN_GPMC_AD14 0x838 +-#define AM335X_PIN_GPMC_AD15 0x83c +-#define AM335X_PIN_GPMC_A0 0x840 +-#define AM335X_PIN_GPMC_A1 0x844 +-#define AM335X_PIN_GPMC_A2 0x848 +-#define AM335X_PIN_GPMC_A3 0x84c +-#define AM335X_PIN_GPMC_A4 0x850 +-#define AM335X_PIN_GPMC_A5 0x854 +-#define AM335X_PIN_GPMC_A6 0x858 +-#define AM335X_PIN_GPMC_A7 0x85c +-#define AM335X_PIN_GPMC_A8 0x860 +-#define AM335X_PIN_GPMC_A9 0x864 +-#define AM335X_PIN_GPMC_A10 0x868 +-#define AM335X_PIN_GPMC_A11 0x86c +-#define AM335X_PIN_GPMC_WAIT0 0x870 +-#define AM335X_PIN_GPMC_WPN 0x874 +-#define AM335X_PIN_GPMC_BEN1 0x878 +-#define AM335X_PIN_GPMC_CSN0 0x87c +-#define AM335X_PIN_GPMC_CSN1 0x880 +-#define AM335X_PIN_GPMC_CSN2 0x884 +-#define AM335X_PIN_GPMC_CSN3 0x888 +-#define AM335X_PIN_GPMC_CLK 0x88c +-#define AM335X_PIN_GPMC_ADVN_ALE 0x890 +-#define AM335X_PIN_GPMC_OEN_REN 0x894 +-#define AM335X_PIN_GPMC_WEN 0x898 +-#define AM335X_PIN_GPMC_BEN0_CLE 0x89c +-#define AM335X_PIN_LCD_DATA0 0x8a0 +-#define AM335X_PIN_LCD_DATA1 0x8a4 +-#define AM335X_PIN_LCD_DATA2 0x8a8 +-#define AM335X_PIN_LCD_DATA3 0x8ac +-#define AM335X_PIN_LCD_DATA4 0x8b0 +-#define AM335X_PIN_LCD_DATA5 0x8b4 +-#define AM335X_PIN_LCD_DATA6 0x8b8 +-#define AM335X_PIN_LCD_DATA7 0x8bc +-#define AM335X_PIN_LCD_DATA8 0x8c0 +-#define AM335X_PIN_LCD_DATA9 0x8c4 +-#define AM335X_PIN_LCD_DATA10 0x8c8 +-#define AM335X_PIN_LCD_DATA11 0x8cc +-#define AM335X_PIN_LCD_DATA12 0x8d0 +-#define AM335X_PIN_LCD_DATA13 0x8d4 +-#define AM335X_PIN_LCD_DATA14 0x8d8 +-#define AM335X_PIN_LCD_DATA15 0x8dc +-#define AM335X_PIN_LCD_VSYNC 0x8e0 +-#define AM335X_PIN_LCD_HSYNC 0x8e4 +-#define AM335X_PIN_LCD_PCLK 0x8e8 +-#define AM335X_PIN_LCD_AC_BIAS_EN 0x8ec +-#define AM335X_PIN_MMC0_DAT3 0x8f0 +-#define AM335X_PIN_MMC0_DAT2 0x8f4 +-#define AM335X_PIN_MMC0_DAT1 0x8f8 +-#define AM335X_PIN_MMC0_DAT0 0x8fc +-#define AM335X_PIN_MMC0_CLK 0x900 +-#define AM335X_PIN_MMC0_CMD 0x904 +-#define AM335X_PIN_MII1_COL 0x908 +-#define AM335X_PIN_MII1_CRS 0x90c +-#define AM335X_PIN_MII1_RX_ER 0x910 +-#define AM335X_PIN_MII1_TX_EN 0x914 +-#define AM335X_PIN_MII1_RX_DV 0x918 +-#define AM335X_PIN_MII1_TXD3 0x91c +-#define AM335X_PIN_MII1_TXD2 0x920 +-#define AM335X_PIN_MII1_TXD1 0x924 +-#define AM335X_PIN_MII1_TXD0 0x928 +-#define AM335X_PIN_MII1_TX_CLK 0x92c +-#define AM335X_PIN_MII1_RX_CLK 0x930 +-#define AM335X_PIN_MII1_RXD3 0x934 +-#define AM335X_PIN_MII1_RXD2 0x938 +-#define AM335X_PIN_MII1_RXD1 0x93c +-#define AM335X_PIN_MII1_RXD0 0x940 +-#define AM335X_PIN_RMII1_REF_CLK 0x944 +-#define AM335X_PIN_MDIO 0x948 +-#define AM335X_PIN_MDC 0x94c +-#define AM335X_PIN_SPI0_SCLK 0x950 +-#define AM335X_PIN_SPI0_D0 0x954 +-#define AM335X_PIN_SPI0_D1 0x958 +-#define AM335X_PIN_SPI0_CS0 0x95c +-#define AM335X_PIN_SPI0_CS1 0x960 +-#define AM335X_PIN_ECAP0_IN_PWM0_OUT 0x964 +-#define AM335X_PIN_UART0_CTSN 0x968 +-#define AM335X_PIN_UART0_RTSN 0x96c +-#define AM335X_PIN_UART0_RXD 0x970 +-#define AM335X_PIN_UART0_TXD 0x974 +-#define AM335X_PIN_UART1_CTSN 0x978 +-#define AM335X_PIN_UART1_RTSN 0x97c +-#define AM335X_PIN_UART1_RXD 0x980 +-#define AM335X_PIN_UART1_TXD 0x984 +-#define AM335X_PIN_I2C0_SDA 0x988 +-#define AM335X_PIN_I2C0_SCL 0x98c +-#define AM335X_PIN_MCASP0_ACLKX 0x990 +-#define AM335X_PIN_MCASP0_FSX 0x994 +-#define AM335X_PIN_MCASP0_AXR0 0x998 +-#define AM335X_PIN_MCASP0_AHCLKR 0x99c +-#define AM335X_PIN_MCASP0_ACLKR 0x9a0 +-#define AM335X_PIN_MCASP0_FSR 0x9a4 +-#define AM335X_PIN_MCASP0_AXR1 0x9a8 +-#define AM335X_PIN_MCASP0_AHCLKX 0x9ac +-#define AM335X_PIN_XDMA_EVENT_INTR0 0x9b0 +-#define AM335X_PIN_XDMA_EVENT_INTR1 0x9b4 +-#define AM335X_PIN_WARMRSTN 0x9b8 +-#define AM335X_PIN_NNMI 0x9c0 +-#define AM335X_PIN_TMS 0x9d0 +-#define AM335X_PIN_TDI 0x9d4 +-#define AM335X_PIN_TDO 0x9d8 +-#define AM335X_PIN_TCK 0x9dc +-#define AM335X_PIN_TRSTN 0x9e0 +-#define AM335X_PIN_EMU0 0x9e4 +-#define AM335X_PIN_EMU1 0x9e8 +-#define AM335X_PIN_RTC_PWRONRSTN 0x9f8 +-#define AM335X_PIN_PMIC_POWER_EN 0x9fc +-#define AM335X_PIN_EXT_WAKEUP 0xa00 +-#define AM335X_PIN_USB0_DRVVBUS 0xa1c +-#define AM335X_PIN_USB1_DRVVBUS 0xa34 +- +-#define AM335X_PIN_OFFSET_MAX 0x0a34U +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/am43xx.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/am43xx.h +deleted file mode 100644 +index 6ce4a32f77d4..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/am43xx.h ++++ /dev/null +@@ -1,55 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants specific to AM43XX pinctrl bindings. +- */ +- +-#ifndef _DT_BINDINGS_PINCTRL_AM43XX_H +-#define _DT_BINDINGS_PINCTRL_AM43XX_H +- +-#define MUX_MODE0 0 +-#define MUX_MODE1 1 +-#define MUX_MODE2 2 +-#define MUX_MODE3 3 +-#define MUX_MODE4 4 +-#define MUX_MODE5 5 +-#define MUX_MODE6 6 +-#define MUX_MODE7 7 +-#define MUX_MODE8 8 +-#define MUX_MODE9 9 +- +-#define PULL_DISABLE (1 << 16) +-#define PULL_UP (1 << 17) +-#define INPUT_EN (1 << 18) +-#define SLEWCTRL_SLOW (1 << 19) +-#define SLEWCTRL_FAST 0 +-#define DS0_FORCE_OFF_MODE (1 << 24) +-#define DS0_INPUT (1 << 25) +-#define DS0_FORCE_OUT_HIGH (1 << 26) +-#define DS0_PULL_UP_DOWN_EN (0 << 27) +-#define DS0_PULL_UP_DOWN_DIS (1 << 27) +-#define DS0_PULL_UP_SEL (1 << 28) +-#define WAKEUP_ENABLE (1 << 29) +- +-#define DS0_PIN_OUTPUT (DS0_FORCE_OFF_MODE) +-#define DS0_PIN_OUTPUT_HIGH (DS0_FORCE_OFF_MODE | DS0_FORCE_OUT_HIGH) +-#define DS0_PIN_OUTPUT_PULLUP (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | DS0_PULL_UP_SEL) +-#define DS0_PIN_OUTPUT_PULLDOWN (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN) +-#define DS0_PIN_INPUT (DS0_FORCE_OFF_MODE | DS0_INPUT) +-#define DS0_PIN_INPUT_PULLUP (DS0_FORCE_OFF_MODE | DS0_INPUT | DS0_PULL_UP_DOWN_EN | DS0_PULL_UP_SEL) +-#define DS0_PIN_INPUT_PULLDOWN (DS0_FORCE_OFF_MODE | DS0_INPUT | DS0_PULL_UP_DOWN_EN) +- +-#define PIN_OUTPUT (PULL_DISABLE) +-#define PIN_OUTPUT_PULLUP (PULL_UP) +-#define PIN_OUTPUT_PULLDOWN 0 +-#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +-#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +-#define PIN_INPUT_PULLDOWN (INPUT_EN) +- +-/* +- * Macro to allow using the absolute physical address instead of the +- * padconf registers instead of the offset from padconf base. +- */ +-#define AM4372_IOPAD(pa, val) (((pa) & 0xffff) - 0x0800) (val) +- +-#endif +- +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/apple.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/apple.h +deleted file mode 100644 +index ea0a6f466592..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/apple.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ +-/* +- * This header provides constants for Apple pinctrl bindings. +- */ +- +-#ifndef _DT_BINDINGS_PINCTRL_APPLE_H +-#define _DT_BINDINGS_PINCTRL_APPLE_H +- +-#define APPLE_PINMUX(pin, func) ((pin) | ((func) << 16)) +-#define APPLE_PIN(pinmux) ((pinmux) & 0xffff) +-#define APPLE_FUNC(pinmux) ((pinmux) >> 16) +- +-#endif /* _DT_BINDINGS_PINCTRL_APPLE_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/at91.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/at91.h +deleted file mode 100644 +index e8e117306b1b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/at91.h ++++ /dev/null +@@ -1,49 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * This header provides constants for most at91 pinctrl bindings. +- * +- * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD +- */ +- +-#ifndef __DT_BINDINGS_AT91_PINCTRL_H__ +-#define __DT_BINDINGS_AT91_PINCTRL_H__ +- +-#define AT91_PINCTRL_NONE (0 << 0) +-#define AT91_PINCTRL_PULL_UP (1 << 0) +-#define AT91_PINCTRL_MULTI_DRIVE (1 << 1) +-#define AT91_PINCTRL_DEGLITCH (1 << 2) +-#define AT91_PINCTRL_PULL_DOWN (1 << 3) +-#define AT91_PINCTRL_DIS_SCHMIT (1 << 4) +-#define AT91_PINCTRL_OUTPUT (1 << 7) +-#define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8) +-#define AT91_PINCTRL_SLEWRATE (1 << 9) +-#define AT91_PINCTRL_DEBOUNCE (1 << 16) +-#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17) +- +-#define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH) +- +-#define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT (0x0 << 5) +-#define AT91_PINCTRL_DRIVE_STRENGTH_LOW (0x1 << 5) +-#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5) +-#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5) +- +-#define AT91_PINCTRL_SLEWRATE_ENA (0x0 << 9) +-#define AT91_PINCTRL_SLEWRATE_DIS (0x1 << 9) +- +-#define AT91_PIOA 0 +-#define AT91_PIOB 1 +-#define AT91_PIOC 2 +-#define AT91_PIOD 3 +-#define AT91_PIOE 4 +- +-#define AT91_PERIPH_GPIO 0 +-#define AT91_PERIPH_A 1 +-#define AT91_PERIPH_B 2 +-#define AT91_PERIPH_C 3 +-#define AT91_PERIPH_D 4 +- +-#define ATMEL_PIO_DRVSTR_LO 1 +-#define ATMEL_PIO_DRVSTR_ME 2 +-#define ATMEL_PIO_DRVSTR_HI 3 +- +-#endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/bcm2835.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/bcm2835.h +deleted file mode 100644 +index b5b2654a0e4d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/bcm2835.h ++++ /dev/null +@@ -1,26 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Header providing constants for bcm2835 pinctrl bindings. +- * +- * Copyright (C) 2015 Stefan Wahren +- */ +- +-#ifndef __DT_BINDINGS_PINCTRL_BCM2835_H__ +-#define __DT_BINDINGS_PINCTRL_BCM2835_H__ +- +-/* brcm,function property */ +-#define BCM2835_FSEL_GPIO_IN 0 +-#define BCM2835_FSEL_GPIO_OUT 1 +-#define BCM2835_FSEL_ALT5 2 +-#define BCM2835_FSEL_ALT4 3 +-#define BCM2835_FSEL_ALT0 4 +-#define BCM2835_FSEL_ALT1 5 +-#define BCM2835_FSEL_ALT2 6 +-#define BCM2835_FSEL_ALT3 7 +- +-/* brcm,pull property */ +-#define BCM2835_PUD_OFF 0 +-#define BCM2835_PUD_DOWN 1 +-#define BCM2835_PUD_UP 2 +- +-#endif /* __DT_BINDINGS_PINCTRL_BCM2835_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/brcm,pinctrl-stingray.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/brcm,pinctrl-stingray.h +deleted file mode 100644 +index caa6c664b4f6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/brcm,pinctrl-stingray.h ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2017 Broadcom Corporation. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#ifndef __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__ +-#define __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__ +- +-/* Alternate functions available in MUX controller */ +-#define MODE_NITRO 0 +-#define MODE_NAND 1 +-#define MODE_PNOR 2 +-#define MODE_GPIO 3 +- +-/* Pad configuration attribute */ +-#define PAD_SLEW_RATE_ENA (1 << 0) +-#define PAD_SLEW_RATE_ENA_MASK (1 << 0) +- +-#define PAD_DRIVE_STRENGTH_2_MA (0 << 1) +-#define PAD_DRIVE_STRENGTH_4_MA (1 << 1) +-#define PAD_DRIVE_STRENGTH_6_MA (2 << 1) +-#define PAD_DRIVE_STRENGTH_8_MA (3 << 1) +-#define PAD_DRIVE_STRENGTH_10_MA (4 << 1) +-#define PAD_DRIVE_STRENGTH_12_MA (5 << 1) +-#define PAD_DRIVE_STRENGTH_14_MA (6 << 1) +-#define PAD_DRIVE_STRENGTH_16_MA (7 << 1) +-#define PAD_DRIVE_STRENGTH_MASK (7 << 1) +- +-#define PAD_PULL_UP_ENA (1 << 4) +-#define PAD_PULL_UP_ENA_MASK (1 << 4) +- +-#define PAD_PULL_DOWN_ENA (1 << 5) +-#define PAD_PULL_DOWN_ENA_MASK (1 << 5) +- +-#define PAD_INPUT_PATH_DIS (1 << 6) +-#define PAD_INPUT_PATH_DIS_MASK (1 << 6) +- +-#define PAD_HYSTERESIS_ENA (1 << 7) +-#define PAD_HYSTERESIS_ENA_MASK (1 << 7) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/dm814x.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/dm814x.h +deleted file mode 100644 +index afbabbc4ddbb..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/dm814x.h ++++ /dev/null +@@ -1,49 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants specific to DM814X pinctrl bindings. +- */ +- +-#ifndef _DT_BINDINGS_PINCTRL_DM814X_H +-#define _DT_BINDINGS_PINCTRL_DM814X_H +- +-#include +- +-#undef INPUT_EN +-#undef PULL_UP +-#undef PULL_ENA +- +-/* +- * Note that dm814x silicon revision 2.1 and older require input enabled +- * (bit 18 set) for all 3.3V I/Os to avoid cumulative hardware damage. For +- * more info, see errata advisory 2.1.87. We leave bit 18 out of +- * function-mask in dm814x.h and rely on the bootloader for it. +- */ +-#define INPUT_EN (1 << 18) +-#define PULL_UP (1 << 17) +-#define PULL_DISABLE (1 << 16) +- +-/* update macro depending on INPUT_EN and PULL_ENA */ +-#undef PIN_OUTPUT +-#undef PIN_OUTPUT_PULLUP +-#undef PIN_OUTPUT_PULLDOWN +-#undef PIN_INPUT +-#undef PIN_INPUT_PULLUP +-#undef PIN_INPUT_PULLDOWN +- +-#define PIN_OUTPUT (PULL_DISABLE) +-#define PIN_OUTPUT_PULLUP (PULL_UP) +-#define PIN_OUTPUT_PULLDOWN 0 +-#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +-#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +-#define PIN_INPUT_PULLDOWN (INPUT_EN) +- +-/* undef non-existing modes */ +-#undef PIN_OFF_NONE +-#undef PIN_OFF_OUTPUT_HIGH +-#undef PIN_OFF_OUTPUT_LOW +-#undef PIN_OFF_INPUT_PULLUP +-#undef PIN_OFF_INPUT_PULLDOWN +-#undef PIN_OFF_WAKEUPENABLE +- +-#endif +- +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/dra.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/dra.h +deleted file mode 100644 +index 252cdfd0d83e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/dra.h ++++ /dev/null +@@ -1,77 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * This header provides constants for DRA pinctrl bindings. +- * +- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ +- * Author: Rajendra Nayak +- */ +- +-#ifndef _DT_BINDINGS_PINCTRL_DRA_H +-#define _DT_BINDINGS_PINCTRL_DRA_H +- +-/* DRA7 mux mode options for each pin. See TRM for options */ +-#define MUX_MODE0 0x0 +-#define MUX_MODE1 0x1 +-#define MUX_MODE2 0x2 +-#define MUX_MODE3 0x3 +-#define MUX_MODE4 0x4 +-#define MUX_MODE5 0x5 +-#define MUX_MODE6 0x6 +-#define MUX_MODE7 0x7 +-#define MUX_MODE8 0x8 +-#define MUX_MODE9 0x9 +-#define MUX_MODE10 0xa +-#define MUX_MODE11 0xb +-#define MUX_MODE12 0xc +-#define MUX_MODE13 0xd +-#define MUX_MODE14 0xe +-#define MUX_MODE15 0xf +- +-/* Certain pins need virtual mode, but note: they may glitch */ +-#define MUX_VIRTUAL_MODE0 (MODE_SELECT | (0x0 << 4)) +-#define MUX_VIRTUAL_MODE1 (MODE_SELECT | (0x1 << 4)) +-#define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4)) +-#define MUX_VIRTUAL_MODE3 (MODE_SELECT | (0x3 << 4)) +-#define MUX_VIRTUAL_MODE4 (MODE_SELECT | (0x4 << 4)) +-#define MUX_VIRTUAL_MODE5 (MODE_SELECT | (0x5 << 4)) +-#define MUX_VIRTUAL_MODE6 (MODE_SELECT | (0x6 << 4)) +-#define MUX_VIRTUAL_MODE7 (MODE_SELECT | (0x7 << 4)) +-#define MUX_VIRTUAL_MODE8 (MODE_SELECT | (0x8 << 4)) +-#define MUX_VIRTUAL_MODE9 (MODE_SELECT | (0x9 << 4)) +-#define MUX_VIRTUAL_MODE10 (MODE_SELECT | (0xa << 4)) +-#define MUX_VIRTUAL_MODE11 (MODE_SELECT | (0xb << 4)) +-#define MUX_VIRTUAL_MODE12 (MODE_SELECT | (0xc << 4)) +-#define MUX_VIRTUAL_MODE13 (MODE_SELECT | (0xd << 4)) +-#define MUX_VIRTUAL_MODE14 (MODE_SELECT | (0xe << 4)) +-#define MUX_VIRTUAL_MODE15 (MODE_SELECT | (0xf << 4)) +- +-#define MODE_SELECT (1 << 8) +- +-#define PULL_ENA (0 << 16) +-#define PULL_DIS (1 << 16) +-#define PULL_UP (1 << 17) +-#define INPUT_EN (1 << 18) +-#define SLEWCONTROL (1 << 19) +-#define WAKEUP_EN (1 << 24) +-#define WAKEUP_EVENT (1 << 25) +- +-/* Active pin states */ +-#define PIN_OUTPUT (0 | PULL_DIS) +-#define PIN_OUTPUT_PULLUP (PULL_UP) +-#define PIN_OUTPUT_PULLDOWN (0) +-#define PIN_INPUT (INPUT_EN | PULL_DIS) +-#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL) +-#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) +-#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) +- +-/* +- * Macro to allow using the absolute physical address instead of the +- * padconf registers instead of the offset from padconf base. +- */ +-#define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val) +- +-/* DRA7 IODELAY configuration parameters */ +-#define A_DELAY_PS(val) ((val) & 0xffff) +-#define G_DELAY_PS(val) ((val) & 0xffff) +-#endif +- +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/hailo15_cpld.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/hailo15_cpld.h +deleted file mode 100644 +index 17372748b17a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/hailo15_cpld.h ++++ /dev/null +@@ -1,25 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2019-2023 Hailo Technologies Ltd. All rights reserved. +- * +- * Header for Hailo15 CPLD-pinctrl device +- * The CPLD is only applicable for HAILO15-evb. +- * +- */ +- +-#ifndef _HAILO15_CPLD_H +-#define _HAILO15_CPLD_H +- +-#define H15_CPLD_BOARD_CONFIG__ONE_CAMERAS_VPU 0 +-#define H15_CPLD_BOARD_CONFIG__ACCELERATOR 0 +-#define H15_CPLD_BOARD_CONFIG__TWO_CAMERAS_VPU 1 +-#define H15_CPLD_BOARD_CONFIG__PARALLEL_CAMERA 2 +-#define H15_CPLD_BOARD_CONFIG__DEBUG_MODE 3 +-#define H15_CPLD_BOARD_CONFIG__DEBUG_BUS 4 +-#define H15_CPLD_BOARD_CONFIG__AUTOMOTIVE 5 +-#define H15_CPLD_BOARD_CONFIG__ALL_GPIO 6 +-#define H15_CPLD_BOARD_CONFIG__SOCS_DEFAULT 7 +-#define H15_CPLD_BOARD_CONFIG__SECURITY_CAMERA_OPTION_1 8 +-#define H15_CPLD_BOARD_CONFIG__SECURITY_CAMERA_OPTION_2 9 +- +-#endif /* _HAILO15_CPLD_H */ +\ No newline at end of file +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/hisi.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/hisi.h +deleted file mode 100644 +index 93064c750c8c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/hisi.h ++++ /dev/null +@@ -1,74 +0,0 @@ +-/* +- * This header provides constants for hisilicon pinctrl bindings. +- * +- * Copyright (c) 2015 HiSilicon Limited. +- * Copyright (c) 2015 Linaro Limited. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License version 2 as +- * published by the Free Software Foundation. +- * +- * This program is distributed "as is" WITHOUT ANY WARRANTY of any +- * kind, whether express or implied; without even the implied warranty +- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#ifndef _DT_BINDINGS_PINCTRL_HISI_H +-#define _DT_BINDINGS_PINCTRL_HISI_H +- +-/* iomg bit definition */ +-#define MUX_M0 0 +-#define MUX_M1 1 +-#define MUX_M2 2 +-#define MUX_M3 3 +-#define MUX_M4 4 +-#define MUX_M5 5 +-#define MUX_M6 6 +-#define MUX_M7 7 +- +-/* iocg bit definition */ +-#define PULL_MASK (3) +-#define PULL_DIS (0) +-#define PULL_UP (1 << 0) +-#define PULL_DOWN (1 << 1) +- +-/* drive strength definition */ +-#define DRIVE_MASK (7 << 4) +-#define DRIVE1_02MA (0 << 4) +-#define DRIVE1_04MA (1 << 4) +-#define DRIVE1_08MA (2 << 4) +-#define DRIVE1_10MA (3 << 4) +-#define DRIVE2_02MA (0 << 4) +-#define DRIVE2_04MA (1 << 4) +-#define DRIVE2_08MA (2 << 4) +-#define DRIVE2_10MA (3 << 4) +-#define DRIVE3_04MA (0 << 4) +-#define DRIVE3_08MA (1 << 4) +-#define DRIVE3_12MA (2 << 4) +-#define DRIVE3_16MA (3 << 4) +-#define DRIVE3_20MA (4 << 4) +-#define DRIVE3_24MA (5 << 4) +-#define DRIVE3_32MA (6 << 4) +-#define DRIVE3_40MA (7 << 4) +-#define DRIVE4_02MA (0 << 4) +-#define DRIVE4_04MA (2 << 4) +-#define DRIVE4_08MA (4 << 4) +-#define DRIVE4_10MA (6 << 4) +- +-/* drive strength definition for hi3660 */ +-#define DRIVE6_MASK (15 << 4) +-#define DRIVE6_04MA (0 << 4) +-#define DRIVE6_12MA (4 << 4) +-#define DRIVE6_19MA (8 << 4) +-#define DRIVE6_27MA (10 << 4) +-#define DRIVE6_32MA (15 << 4) +-#define DRIVE7_02MA (0 << 4) +-#define DRIVE7_04MA (1 << 4) +-#define DRIVE7_06MA (2 << 4) +-#define DRIVE7_08MA (3 << 4) +-#define DRIVE7_10MA (4 << 4) +-#define DRIVE7_12MA (5 << 4) +-#define DRIVE7_14MA (6 << 4) +-#define DRIVE7_16MA (7 << 4) +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/k210-fpioa.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/k210-fpioa.h +deleted file mode 100644 +index 314285eab3a1..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/k210-fpioa.h ++++ /dev/null +@@ -1,276 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright (C) 2020 Sean Anderson +- * Copyright (c) 2020 Western Digital Corporation or its affiliates. +- */ +-#ifndef PINCTRL_K210_FPIOA_H +-#define PINCTRL_K210_FPIOA_H +- +-/* +- * Full list of FPIOA functions from +- * kendryte-standalone-sdk/lib/drivers/include/fpioa.h +- */ +-#define K210_PCF_MASK GENMASK(7, 0) +-#define K210_PCF_JTAG_TCLK 0 /* JTAG Test Clock */ +-#define K210_PCF_JTAG_TDI 1 /* JTAG Test Data In */ +-#define K210_PCF_JTAG_TMS 2 /* JTAG Test Mode Select */ +-#define K210_PCF_JTAG_TDO 3 /* JTAG Test Data Out */ +-#define K210_PCF_SPI0_D0 4 /* SPI0 Data 0 */ +-#define K210_PCF_SPI0_D1 5 /* SPI0 Data 1 */ +-#define K210_PCF_SPI0_D2 6 /* SPI0 Data 2 */ +-#define K210_PCF_SPI0_D3 7 /* SPI0 Data 3 */ +-#define K210_PCF_SPI0_D4 8 /* SPI0 Data 4 */ +-#define K210_PCF_SPI0_D5 9 /* SPI0 Data 5 */ +-#define K210_PCF_SPI0_D6 10 /* SPI0 Data 6 */ +-#define K210_PCF_SPI0_D7 11 /* SPI0 Data 7 */ +-#define K210_PCF_SPI0_SS0 12 /* SPI0 Chip Select 0 */ +-#define K210_PCF_SPI0_SS1 13 /* SPI0 Chip Select 1 */ +-#define K210_PCF_SPI0_SS2 14 /* SPI0 Chip Select 2 */ +-#define K210_PCF_SPI0_SS3 15 /* SPI0 Chip Select 3 */ +-#define K210_PCF_SPI0_ARB 16 /* SPI0 Arbitration */ +-#define K210_PCF_SPI0_SCLK 17 /* SPI0 Serial Clock */ +-#define K210_PCF_UARTHS_RX 18 /* UART High speed Receiver */ +-#define K210_PCF_UARTHS_TX 19 /* UART High speed Transmitter */ +-#define K210_PCF_RESV6 20 /* Reserved function */ +-#define K210_PCF_RESV7 21 /* Reserved function */ +-#define K210_PCF_CLK_SPI1 22 /* Clock SPI1 */ +-#define K210_PCF_CLK_I2C1 23 /* Clock I2C1 */ +-#define K210_PCF_GPIOHS0 24 /* GPIO High speed 0 */ +-#define K210_PCF_GPIOHS1 25 /* GPIO High speed 1 */ +-#define K210_PCF_GPIOHS2 26 /* GPIO High speed 2 */ +-#define K210_PCF_GPIOHS3 27 /* GPIO High speed 3 */ +-#define K210_PCF_GPIOHS4 28 /* GPIO High speed 4 */ +-#define K210_PCF_GPIOHS5 29 /* GPIO High speed 5 */ +-#define K210_PCF_GPIOHS6 30 /* GPIO High speed 6 */ +-#define K210_PCF_GPIOHS7 31 /* GPIO High speed 7 */ +-#define K210_PCF_GPIOHS8 32 /* GPIO High speed 8 */ +-#define K210_PCF_GPIOHS9 33 /* GPIO High speed 9 */ +-#define K210_PCF_GPIOHS10 34 /* GPIO High speed 10 */ +-#define K210_PCF_GPIOHS11 35 /* GPIO High speed 11 */ +-#define K210_PCF_GPIOHS12 36 /* GPIO High speed 12 */ +-#define K210_PCF_GPIOHS13 37 /* GPIO High speed 13 */ +-#define K210_PCF_GPIOHS14 38 /* GPIO High speed 14 */ +-#define K210_PCF_GPIOHS15 39 /* GPIO High speed 15 */ +-#define K210_PCF_GPIOHS16 40 /* GPIO High speed 16 */ +-#define K210_PCF_GPIOHS17 41 /* GPIO High speed 17 */ +-#define K210_PCF_GPIOHS18 42 /* GPIO High speed 18 */ +-#define K210_PCF_GPIOHS19 43 /* GPIO High speed 19 */ +-#define K210_PCF_GPIOHS20 44 /* GPIO High speed 20 */ +-#define K210_PCF_GPIOHS21 45 /* GPIO High speed 21 */ +-#define K210_PCF_GPIOHS22 46 /* GPIO High speed 22 */ +-#define K210_PCF_GPIOHS23 47 /* GPIO High speed 23 */ +-#define K210_PCF_GPIOHS24 48 /* GPIO High speed 24 */ +-#define K210_PCF_GPIOHS25 49 /* GPIO High speed 25 */ +-#define K210_PCF_GPIOHS26 50 /* GPIO High speed 26 */ +-#define K210_PCF_GPIOHS27 51 /* GPIO High speed 27 */ +-#define K210_PCF_GPIOHS28 52 /* GPIO High speed 28 */ +-#define K210_PCF_GPIOHS29 53 /* GPIO High speed 29 */ +-#define K210_PCF_GPIOHS30 54 /* GPIO High speed 30 */ +-#define K210_PCF_GPIOHS31 55 /* GPIO High speed 31 */ +-#define K210_PCF_GPIO0 56 /* GPIO pin 0 */ +-#define K210_PCF_GPIO1 57 /* GPIO pin 1 */ +-#define K210_PCF_GPIO2 58 /* GPIO pin 2 */ +-#define K210_PCF_GPIO3 59 /* GPIO pin 3 */ +-#define K210_PCF_GPIO4 60 /* GPIO pin 4 */ +-#define K210_PCF_GPIO5 61 /* GPIO pin 5 */ +-#define K210_PCF_GPIO6 62 /* GPIO pin 6 */ +-#define K210_PCF_GPIO7 63 /* GPIO pin 7 */ +-#define K210_PCF_UART1_RX 64 /* UART1 Receiver */ +-#define K210_PCF_UART1_TX 65 /* UART1 Transmitter */ +-#define K210_PCF_UART2_RX 66 /* UART2 Receiver */ +-#define K210_PCF_UART2_TX 67 /* UART2 Transmitter */ +-#define K210_PCF_UART3_RX 68 /* UART3 Receiver */ +-#define K210_PCF_UART3_TX 69 /* UART3 Transmitter */ +-#define K210_PCF_SPI1_D0 70 /* SPI1 Data 0 */ +-#define K210_PCF_SPI1_D1 71 /* SPI1 Data 1 */ +-#define K210_PCF_SPI1_D2 72 /* SPI1 Data 2 */ +-#define K210_PCF_SPI1_D3 73 /* SPI1 Data 3 */ +-#define K210_PCF_SPI1_D4 74 /* SPI1 Data 4 */ +-#define K210_PCF_SPI1_D5 75 /* SPI1 Data 5 */ +-#define K210_PCF_SPI1_D6 76 /* SPI1 Data 6 */ +-#define K210_PCF_SPI1_D7 77 /* SPI1 Data 7 */ +-#define K210_PCF_SPI1_SS0 78 /* SPI1 Chip Select 0 */ +-#define K210_PCF_SPI1_SS1 79 /* SPI1 Chip Select 1 */ +-#define K210_PCF_SPI1_SS2 80 /* SPI1 Chip Select 2 */ +-#define K210_PCF_SPI1_SS3 81 /* SPI1 Chip Select 3 */ +-#define K210_PCF_SPI1_ARB 82 /* SPI1 Arbitration */ +-#define K210_PCF_SPI1_SCLK 83 /* SPI1 Serial Clock */ +-#define K210_PCF_SPI2_D0 84 /* SPI2 Data 0 */ +-#define K210_PCF_SPI2_SS 85 /* SPI2 Select */ +-#define K210_PCF_SPI2_SCLK 86 /* SPI2 Serial Clock */ +-#define K210_PCF_I2S0_MCLK 87 /* I2S0 Master Clock */ +-#define K210_PCF_I2S0_SCLK 88 /* I2S0 Serial Clock(BCLK) */ +-#define K210_PCF_I2S0_WS 89 /* I2S0 Word Select(LRCLK) */ +-#define K210_PCF_I2S0_IN_D0 90 /* I2S0 Serial Data Input 0 */ +-#define K210_PCF_I2S0_IN_D1 91 /* I2S0 Serial Data Input 1 */ +-#define K210_PCF_I2S0_IN_D2 92 /* I2S0 Serial Data Input 2 */ +-#define K210_PCF_I2S0_IN_D3 93 /* I2S0 Serial Data Input 3 */ +-#define K210_PCF_I2S0_OUT_D0 94 /* I2S0 Serial Data Output 0 */ +-#define K210_PCF_I2S0_OUT_D1 95 /* I2S0 Serial Data Output 1 */ +-#define K210_PCF_I2S0_OUT_D2 96 /* I2S0 Serial Data Output 2 */ +-#define K210_PCF_I2S0_OUT_D3 97 /* I2S0 Serial Data Output 3 */ +-#define K210_PCF_I2S1_MCLK 98 /* I2S1 Master Clock */ +-#define K210_PCF_I2S1_SCLK 99 /* I2S1 Serial Clock(BCLK) */ +-#define K210_PCF_I2S1_WS 100 /* I2S1 Word Select(LRCLK) */ +-#define K210_PCF_I2S1_IN_D0 101 /* I2S1 Serial Data Input 0 */ +-#define K210_PCF_I2S1_IN_D1 102 /* I2S1 Serial Data Input 1 */ +-#define K210_PCF_I2S1_IN_D2 103 /* I2S1 Serial Data Input 2 */ +-#define K210_PCF_I2S1_IN_D3 104 /* I2S1 Serial Data Input 3 */ +-#define K210_PCF_I2S1_OUT_D0 105 /* I2S1 Serial Data Output 0 */ +-#define K210_PCF_I2S1_OUT_D1 106 /* I2S1 Serial Data Output 1 */ +-#define K210_PCF_I2S1_OUT_D2 107 /* I2S1 Serial Data Output 2 */ +-#define K210_PCF_I2S1_OUT_D3 108 /* I2S1 Serial Data Output 3 */ +-#define K210_PCF_I2S2_MCLK 109 /* I2S2 Master Clock */ +-#define K210_PCF_I2S2_SCLK 110 /* I2S2 Serial Clock(BCLK) */ +-#define K210_PCF_I2S2_WS 111 /* I2S2 Word Select(LRCLK) */ +-#define K210_PCF_I2S2_IN_D0 112 /* I2S2 Serial Data Input 0 */ +-#define K210_PCF_I2S2_IN_D1 113 /* I2S2 Serial Data Input 1 */ +-#define K210_PCF_I2S2_IN_D2 114 /* I2S2 Serial Data Input 2 */ +-#define K210_PCF_I2S2_IN_D3 115 /* I2S2 Serial Data Input 3 */ +-#define K210_PCF_I2S2_OUT_D0 116 /* I2S2 Serial Data Output 0 */ +-#define K210_PCF_I2S2_OUT_D1 117 /* I2S2 Serial Data Output 1 */ +-#define K210_PCF_I2S2_OUT_D2 118 /* I2S2 Serial Data Output 2 */ +-#define K210_PCF_I2S2_OUT_D3 119 /* I2S2 Serial Data Output 3 */ +-#define K210_PCF_RESV0 120 /* Reserved function */ +-#define K210_PCF_RESV1 121 /* Reserved function */ +-#define K210_PCF_RESV2 122 /* Reserved function */ +-#define K210_PCF_RESV3 123 /* Reserved function */ +-#define K210_PCF_RESV4 124 /* Reserved function */ +-#define K210_PCF_RESV5 125 /* Reserved function */ +-#define K210_PCF_I2C0_SCLK 126 /* I2C0 Serial Clock */ +-#define K210_PCF_I2C0_SDA 127 /* I2C0 Serial Data */ +-#define K210_PCF_I2C1_SCLK 128 /* I2C1 Serial Clock */ +-#define K210_PCF_I2C1_SDA 129 /* I2C1 Serial Data */ +-#define K210_PCF_I2C2_SCLK 130 /* I2C2 Serial Clock */ +-#define K210_PCF_I2C2_SDA 131 /* I2C2 Serial Data */ +-#define K210_PCF_DVP_XCLK 132 /* DVP System Clock */ +-#define K210_PCF_DVP_RST 133 /* DVP System Reset */ +-#define K210_PCF_DVP_PWDN 134 /* DVP Power Down Mode */ +-#define K210_PCF_DVP_VSYNC 135 /* DVP Vertical Sync */ +-#define K210_PCF_DVP_HSYNC 136 /* DVP Horizontal Sync */ +-#define K210_PCF_DVP_PCLK 137 /* Pixel Clock */ +-#define K210_PCF_DVP_D0 138 /* Data Bit 0 */ +-#define K210_PCF_DVP_D1 139 /* Data Bit 1 */ +-#define K210_PCF_DVP_D2 140 /* Data Bit 2 */ +-#define K210_PCF_DVP_D3 141 /* Data Bit 3 */ +-#define K210_PCF_DVP_D4 142 /* Data Bit 4 */ +-#define K210_PCF_DVP_D5 143 /* Data Bit 5 */ +-#define K210_PCF_DVP_D6 144 /* Data Bit 6 */ +-#define K210_PCF_DVP_D7 145 /* Data Bit 7 */ +-#define K210_PCF_SCCB_SCLK 146 /* Serial Camera Control Bus Clock */ +-#define K210_PCF_SCCB_SDA 147 /* Serial Camera Control Bus Data */ +-#define K210_PCF_UART1_CTS 148 /* UART1 Clear To Send */ +-#define K210_PCF_UART1_DSR 149 /* UART1 Data Set Ready */ +-#define K210_PCF_UART1_DCD 150 /* UART1 Data Carrier Detect */ +-#define K210_PCF_UART1_RI 151 /* UART1 Ring Indicator */ +-#define K210_PCF_UART1_SIR_IN 152 /* UART1 Serial Infrared Input */ +-#define K210_PCF_UART1_DTR 153 /* UART1 Data Terminal Ready */ +-#define K210_PCF_UART1_RTS 154 /* UART1 Request To Send */ +-#define K210_PCF_UART1_OUT2 155 /* UART1 User-designated Output 2 */ +-#define K210_PCF_UART1_OUT1 156 /* UART1 User-designated Output 1 */ +-#define K210_PCF_UART1_SIR_OUT 157 /* UART1 Serial Infrared Output */ +-#define K210_PCF_UART1_BAUD 158 /* UART1 Transmit Clock Output */ +-#define K210_PCF_UART1_RE 159 /* UART1 Receiver Output Enable */ +-#define K210_PCF_UART1_DE 160 /* UART1 Driver Output Enable */ +-#define K210_PCF_UART1_RS485_EN 161 /* UART1 RS485 Enable */ +-#define K210_PCF_UART2_CTS 162 /* UART2 Clear To Send */ +-#define K210_PCF_UART2_DSR 163 /* UART2 Data Set Ready */ +-#define K210_PCF_UART2_DCD 164 /* UART2 Data Carrier Detect */ +-#define K210_PCF_UART2_RI 165 /* UART2 Ring Indicator */ +-#define K210_PCF_UART2_SIR_IN 166 /* UART2 Serial Infrared Input */ +-#define K210_PCF_UART2_DTR 167 /* UART2 Data Terminal Ready */ +-#define K210_PCF_UART2_RTS 168 /* UART2 Request To Send */ +-#define K210_PCF_UART2_OUT2 169 /* UART2 User-designated Output 2 */ +-#define K210_PCF_UART2_OUT1 170 /* UART2 User-designated Output 1 */ +-#define K210_PCF_UART2_SIR_OUT 171 /* UART2 Serial Infrared Output */ +-#define K210_PCF_UART2_BAUD 172 /* UART2 Transmit Clock Output */ +-#define K210_PCF_UART2_RE 173 /* UART2 Receiver Output Enable */ +-#define K210_PCF_UART2_DE 174 /* UART2 Driver Output Enable */ +-#define K210_PCF_UART2_RS485_EN 175 /* UART2 RS485 Enable */ +-#define K210_PCF_UART3_CTS 176 /* UART3 Clear To Send */ +-#define K210_PCF_UART3_DSR 177 /* UART3 Data Set Ready */ +-#define K210_PCF_UART3_DCD 178 /* UART3 Data Carrier Detect */ +-#define K210_PCF_UART3_RI 179 /* UART3 Ring Indicator */ +-#define K210_PCF_UART3_SIR_IN 180 /* UART3 Serial Infrared Input */ +-#define K210_PCF_UART3_DTR 181 /* UART3 Data Terminal Ready */ +-#define K210_PCF_UART3_RTS 182 /* UART3 Request To Send */ +-#define K210_PCF_UART3_OUT2 183 /* UART3 User-designated Output 2 */ +-#define K210_PCF_UART3_OUT1 184 /* UART3 User-designated Output 1 */ +-#define K210_PCF_UART3_SIR_OUT 185 /* UART3 Serial Infrared Output */ +-#define K210_PCF_UART3_BAUD 186 /* UART3 Transmit Clock Output */ +-#define K210_PCF_UART3_RE 187 /* UART3 Receiver Output Enable */ +-#define K210_PCF_UART3_DE 188 /* UART3 Driver Output Enable */ +-#define K210_PCF_UART3_RS485_EN 189 /* UART3 RS485 Enable */ +-#define K210_PCF_TIMER0_TOGGLE1 190 /* TIMER0 Toggle Output 1 */ +-#define K210_PCF_TIMER0_TOGGLE2 191 /* TIMER0 Toggle Output 2 */ +-#define K210_PCF_TIMER0_TOGGLE3 192 /* TIMER0 Toggle Output 3 */ +-#define K210_PCF_TIMER0_TOGGLE4 193 /* TIMER0 Toggle Output 4 */ +-#define K210_PCF_TIMER1_TOGGLE1 194 /* TIMER1 Toggle Output 1 */ +-#define K210_PCF_TIMER1_TOGGLE2 195 /* TIMER1 Toggle Output 2 */ +-#define K210_PCF_TIMER1_TOGGLE3 196 /* TIMER1 Toggle Output 3 */ +-#define K210_PCF_TIMER1_TOGGLE4 197 /* TIMER1 Toggle Output 4 */ +-#define K210_PCF_TIMER2_TOGGLE1 198 /* TIMER2 Toggle Output 1 */ +-#define K210_PCF_TIMER2_TOGGLE2 199 /* TIMER2 Toggle Output 2 */ +-#define K210_PCF_TIMER2_TOGGLE3 200 /* TIMER2 Toggle Output 3 */ +-#define K210_PCF_TIMER2_TOGGLE4 201 /* TIMER2 Toggle Output 4 */ +-#define K210_PCF_CLK_SPI2 202 /* Clock SPI2 */ +-#define K210_PCF_CLK_I2C2 203 /* Clock I2C2 */ +-#define K210_PCF_INTERNAL0 204 /* Internal function signal 0 */ +-#define K210_PCF_INTERNAL1 205 /* Internal function signal 1 */ +-#define K210_PCF_INTERNAL2 206 /* Internal function signal 2 */ +-#define K210_PCF_INTERNAL3 207 /* Internal function signal 3 */ +-#define K210_PCF_INTERNAL4 208 /* Internal function signal 4 */ +-#define K210_PCF_INTERNAL5 209 /* Internal function signal 5 */ +-#define K210_PCF_INTERNAL6 210 /* Internal function signal 6 */ +-#define K210_PCF_INTERNAL7 211 /* Internal function signal 7 */ +-#define K210_PCF_INTERNAL8 212 /* Internal function signal 8 */ +-#define K210_PCF_INTERNAL9 213 /* Internal function signal 9 */ +-#define K210_PCF_INTERNAL10 214 /* Internal function signal 10 */ +-#define K210_PCF_INTERNAL11 215 /* Internal function signal 11 */ +-#define K210_PCF_INTERNAL12 216 /* Internal function signal 12 */ +-#define K210_PCF_INTERNAL13 217 /* Internal function signal 13 */ +-#define K210_PCF_INTERNAL14 218 /* Internal function signal 14 */ +-#define K210_PCF_INTERNAL15 219 /* Internal function signal 15 */ +-#define K210_PCF_INTERNAL16 220 /* Internal function signal 16 */ +-#define K210_PCF_INTERNAL17 221 /* Internal function signal 17 */ +-#define K210_PCF_CONSTANT 222 /* Constant function */ +-#define K210_PCF_INTERNAL18 223 /* Internal function signal 18 */ +-#define K210_PCF_DEBUG0 224 /* Debug function 0 */ +-#define K210_PCF_DEBUG1 225 /* Debug function 1 */ +-#define K210_PCF_DEBUG2 226 /* Debug function 2 */ +-#define K210_PCF_DEBUG3 227 /* Debug function 3 */ +-#define K210_PCF_DEBUG4 228 /* Debug function 4 */ +-#define K210_PCF_DEBUG5 229 /* Debug function 5 */ +-#define K210_PCF_DEBUG6 230 /* Debug function 6 */ +-#define K210_PCF_DEBUG7 231 /* Debug function 7 */ +-#define K210_PCF_DEBUG8 232 /* Debug function 8 */ +-#define K210_PCF_DEBUG9 233 /* Debug function 9 */ +-#define K210_PCF_DEBUG10 234 /* Debug function 10 */ +-#define K210_PCF_DEBUG11 235 /* Debug function 11 */ +-#define K210_PCF_DEBUG12 236 /* Debug function 12 */ +-#define K210_PCF_DEBUG13 237 /* Debug function 13 */ +-#define K210_PCF_DEBUG14 238 /* Debug function 14 */ +-#define K210_PCF_DEBUG15 239 /* Debug function 15 */ +-#define K210_PCF_DEBUG16 240 /* Debug function 16 */ +-#define K210_PCF_DEBUG17 241 /* Debug function 17 */ +-#define K210_PCF_DEBUG18 242 /* Debug function 18 */ +-#define K210_PCF_DEBUG19 243 /* Debug function 19 */ +-#define K210_PCF_DEBUG20 244 /* Debug function 20 */ +-#define K210_PCF_DEBUG21 245 /* Debug function 21 */ +-#define K210_PCF_DEBUG22 246 /* Debug function 22 */ +-#define K210_PCF_DEBUG23 247 /* Debug function 23 */ +-#define K210_PCF_DEBUG24 248 /* Debug function 24 */ +-#define K210_PCF_DEBUG25 249 /* Debug function 25 */ +-#define K210_PCF_DEBUG26 250 /* Debug function 26 */ +-#define K210_PCF_DEBUG27 251 /* Debug function 27 */ +-#define K210_PCF_DEBUG28 252 /* Debug function 28 */ +-#define K210_PCF_DEBUG29 253 /* Debug function 29 */ +-#define K210_PCF_DEBUG30 254 /* Debug function 30 */ +-#define K210_PCF_DEBUG31 255 /* Debug function 31 */ +- +-#define K210_FPIOA(pin, func) (((pin) << 16) | (func)) +- +-#define K210_PC_POWER_3V3 0 +-#define K210_PC_POWER_1V8 1 +- +-#endif /* PINCTRL_K210_FPIOA_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/k3.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/k3.h +deleted file mode 100644 +index e085f102b283..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/k3.h ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for pinctrl bindings for TI's K3 SoC +- * family. +- * +- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ +- */ +-#ifndef _DT_BINDINGS_PINCTRL_TI_K3_H +-#define _DT_BINDINGS_PINCTRL_TI_K3_H +- +-#define PULLUDEN_SHIFT (16) +-#define PULLTYPESEL_SHIFT (17) +-#define RXACTIVE_SHIFT (18) +- +-#define PULL_DISABLE (1 << PULLUDEN_SHIFT) +-#define PULL_ENABLE (0 << PULLUDEN_SHIFT) +- +-#define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE) +-#define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE) +- +-#define INPUT_EN (1 << RXACTIVE_SHIFT) +-#define INPUT_DISABLE (0 << RXACTIVE_SHIFT) +- +-/* Only these macros are expected be used directly in device tree files */ +-#define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) +-#define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) +-#define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN) +-#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +-#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +-#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) +- +-#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +-#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +- +-#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +-#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +- +-#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +-#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/keystone.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/keystone.h +deleted file mode 100644 +index 7f97d776a8ff..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/keystone.h ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* +- * This header provides constants for Keystone pinctrl bindings. +- * +- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License version 2 as +- * published by the Free Software Foundation. +- * +- * This program is distributed "as is" WITHOUT ANY WARRANTY of any +- * kind, whether express or implied; without even the implied warranty +- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#ifndef _DT_BINDINGS_PINCTRL_KEYSTONE_H +-#define _DT_BINDINGS_PINCTRL_KEYSTONE_H +- +-#define MUX_MODE0 0 +-#define MUX_MODE1 1 +-#define MUX_MODE2 2 +-#define MUX_MODE3 3 +-#define MUX_MODE4 4 +-#define MUX_MODE5 5 +- +-#define BUFFER_CLASS_B (0 << 19) +-#define BUFFER_CLASS_C (1 << 19) +-#define BUFFER_CLASS_D (2 << 19) +-#define BUFFER_CLASS_E (3 << 19) +- +-#define PULL_DISABLE (1 << 16) +-#define PIN_PULLUP (1 << 17) +-#define PIN_PULLDOWN (0 << 17) +- +-#define KEYSTONE_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset)) +- +-#define K2G_CORE_IOPAD(pa) KEYSTONE_IOPAD_OFFSET((pa), 0x1000) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/lochnagar.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/lochnagar.h +deleted file mode 100644 +index 644760bf5725..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/lochnagar.h ++++ /dev/null +@@ -1,132 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Device Tree defines for Lochnagar pinctrl +- * +- * Copyright (c) 2018 Cirrus Logic, Inc. and +- * Cirrus Logic International Semiconductor Ltd. +- * +- * Author: Charles Keepax +- */ +- +-#ifndef DT_BINDINGS_PINCTRL_LOCHNAGAR_H +-#define DT_BINDINGS_PINCTRL_LOCHNAGAR_H +- +-#define LOCHNAGAR1_PIN_CDC_RESET 0 +-#define LOCHNAGAR1_PIN_DSP_RESET 1 +-#define LOCHNAGAR1_PIN_CDC_CIF1MODE 2 +-#define LOCHNAGAR1_PIN_NUM_GPIOS 3 +- +-#define LOCHNAGAR2_PIN_CDC_RESET 0 +-#define LOCHNAGAR2_PIN_DSP_RESET 1 +-#define LOCHNAGAR2_PIN_CDC_CIF1MODE 2 +-#define LOCHNAGAR2_PIN_CDC_LDOENA 3 +-#define LOCHNAGAR2_PIN_SPDIF_HWMODE 4 +-#define LOCHNAGAR2_PIN_SPDIF_RESET 5 +-#define LOCHNAGAR2_PIN_FPGA_GPIO1 6 +-#define LOCHNAGAR2_PIN_FPGA_GPIO2 7 +-#define LOCHNAGAR2_PIN_FPGA_GPIO3 8 +-#define LOCHNAGAR2_PIN_FPGA_GPIO4 9 +-#define LOCHNAGAR2_PIN_FPGA_GPIO5 10 +-#define LOCHNAGAR2_PIN_FPGA_GPIO6 11 +-#define LOCHNAGAR2_PIN_CDC_GPIO1 12 +-#define LOCHNAGAR2_PIN_CDC_GPIO2 13 +-#define LOCHNAGAR2_PIN_CDC_GPIO3 14 +-#define LOCHNAGAR2_PIN_CDC_GPIO4 15 +-#define LOCHNAGAR2_PIN_CDC_GPIO5 16 +-#define LOCHNAGAR2_PIN_CDC_GPIO6 17 +-#define LOCHNAGAR2_PIN_CDC_GPIO7 18 +-#define LOCHNAGAR2_PIN_CDC_GPIO8 19 +-#define LOCHNAGAR2_PIN_DSP_GPIO1 20 +-#define LOCHNAGAR2_PIN_DSP_GPIO2 21 +-#define LOCHNAGAR2_PIN_DSP_GPIO3 22 +-#define LOCHNAGAR2_PIN_DSP_GPIO4 23 +-#define LOCHNAGAR2_PIN_DSP_GPIO5 24 +-#define LOCHNAGAR2_PIN_DSP_GPIO6 25 +-#define LOCHNAGAR2_PIN_GF_GPIO2 26 +-#define LOCHNAGAR2_PIN_GF_GPIO3 27 +-#define LOCHNAGAR2_PIN_GF_GPIO7 28 +-#define LOCHNAGAR2_PIN_CDC_AIF1_BCLK 29 +-#define LOCHNAGAR2_PIN_CDC_AIF1_RXDAT 30 +-#define LOCHNAGAR2_PIN_CDC_AIF1_LRCLK 31 +-#define LOCHNAGAR2_PIN_CDC_AIF1_TXDAT 32 +-#define LOCHNAGAR2_PIN_CDC_AIF2_BCLK 33 +-#define LOCHNAGAR2_PIN_CDC_AIF2_RXDAT 34 +-#define LOCHNAGAR2_PIN_CDC_AIF2_LRCLK 35 +-#define LOCHNAGAR2_PIN_CDC_AIF2_TXDAT 36 +-#define LOCHNAGAR2_PIN_CDC_AIF3_BCLK 37 +-#define LOCHNAGAR2_PIN_CDC_AIF3_RXDAT 38 +-#define LOCHNAGAR2_PIN_CDC_AIF3_LRCLK 39 +-#define LOCHNAGAR2_PIN_CDC_AIF3_TXDAT 40 +-#define LOCHNAGAR2_PIN_DSP_AIF1_BCLK 41 +-#define LOCHNAGAR2_PIN_DSP_AIF1_RXDAT 42 +-#define LOCHNAGAR2_PIN_DSP_AIF1_LRCLK 43 +-#define LOCHNAGAR2_PIN_DSP_AIF1_TXDAT 44 +-#define LOCHNAGAR2_PIN_DSP_AIF2_BCLK 45 +-#define LOCHNAGAR2_PIN_DSP_AIF2_RXDAT 46 +-#define LOCHNAGAR2_PIN_DSP_AIF2_LRCLK 47 +-#define LOCHNAGAR2_PIN_DSP_AIF2_TXDAT 48 +-#define LOCHNAGAR2_PIN_PSIA1_BCLK 49 +-#define LOCHNAGAR2_PIN_PSIA1_RXDAT 50 +-#define LOCHNAGAR2_PIN_PSIA1_LRCLK 51 +-#define LOCHNAGAR2_PIN_PSIA1_TXDAT 52 +-#define LOCHNAGAR2_PIN_PSIA2_BCLK 53 +-#define LOCHNAGAR2_PIN_PSIA2_RXDAT 54 +-#define LOCHNAGAR2_PIN_PSIA2_LRCLK 55 +-#define LOCHNAGAR2_PIN_PSIA2_TXDAT 56 +-#define LOCHNAGAR2_PIN_GF_AIF3_BCLK 57 +-#define LOCHNAGAR2_PIN_GF_AIF3_RXDAT 58 +-#define LOCHNAGAR2_PIN_GF_AIF3_LRCLK 59 +-#define LOCHNAGAR2_PIN_GF_AIF3_TXDAT 60 +-#define LOCHNAGAR2_PIN_GF_AIF4_BCLK 61 +-#define LOCHNAGAR2_PIN_GF_AIF4_RXDAT 62 +-#define LOCHNAGAR2_PIN_GF_AIF4_LRCLK 63 +-#define LOCHNAGAR2_PIN_GF_AIF4_TXDAT 64 +-#define LOCHNAGAR2_PIN_GF_AIF1_BCLK 65 +-#define LOCHNAGAR2_PIN_GF_AIF1_RXDAT 66 +-#define LOCHNAGAR2_PIN_GF_AIF1_LRCLK 67 +-#define LOCHNAGAR2_PIN_GF_AIF1_TXDAT 68 +-#define LOCHNAGAR2_PIN_GF_AIF2_BCLK 69 +-#define LOCHNAGAR2_PIN_GF_AIF2_RXDAT 70 +-#define LOCHNAGAR2_PIN_GF_AIF2_LRCLK 71 +-#define LOCHNAGAR2_PIN_GF_AIF2_TXDAT 72 +-#define LOCHNAGAR2_PIN_DSP_UART1_RX 73 +-#define LOCHNAGAR2_PIN_DSP_UART1_TX 74 +-#define LOCHNAGAR2_PIN_DSP_UART2_RX 75 +-#define LOCHNAGAR2_PIN_DSP_UART2_TX 76 +-#define LOCHNAGAR2_PIN_GF_UART2_RX 77 +-#define LOCHNAGAR2_PIN_GF_UART2_TX 78 +-#define LOCHNAGAR2_PIN_USB_UART_RX 79 +-#define LOCHNAGAR2_PIN_CDC_PDMCLK1 80 +-#define LOCHNAGAR2_PIN_CDC_PDMDAT1 81 +-#define LOCHNAGAR2_PIN_CDC_PDMCLK2 82 +-#define LOCHNAGAR2_PIN_CDC_PDMDAT2 83 +-#define LOCHNAGAR2_PIN_CDC_DMICCLK1 84 +-#define LOCHNAGAR2_PIN_CDC_DMICDAT1 85 +-#define LOCHNAGAR2_PIN_CDC_DMICCLK2 86 +-#define LOCHNAGAR2_PIN_CDC_DMICDAT2 87 +-#define LOCHNAGAR2_PIN_CDC_DMICCLK3 88 +-#define LOCHNAGAR2_PIN_CDC_DMICDAT3 89 +-#define LOCHNAGAR2_PIN_CDC_DMICCLK4 90 +-#define LOCHNAGAR2_PIN_CDC_DMICDAT4 91 +-#define LOCHNAGAR2_PIN_DSP_DMICCLK1 92 +-#define LOCHNAGAR2_PIN_DSP_DMICDAT1 93 +-#define LOCHNAGAR2_PIN_DSP_DMICCLK2 94 +-#define LOCHNAGAR2_PIN_DSP_DMICDAT2 95 +-#define LOCHNAGAR2_PIN_I2C2_SCL 96 +-#define LOCHNAGAR2_PIN_I2C2_SDA 97 +-#define LOCHNAGAR2_PIN_I2C3_SCL 98 +-#define LOCHNAGAR2_PIN_I2C3_SDA 99 +-#define LOCHNAGAR2_PIN_I2C4_SCL 100 +-#define LOCHNAGAR2_PIN_I2C4_SDA 101 +-#define LOCHNAGAR2_PIN_DSP_STANDBY 102 +-#define LOCHNAGAR2_PIN_CDC_MCLK1 103 +-#define LOCHNAGAR2_PIN_CDC_MCLK2 104 +-#define LOCHNAGAR2_PIN_DSP_CLKIN 105 +-#define LOCHNAGAR2_PIN_PSIA1_MCLK 106 +-#define LOCHNAGAR2_PIN_PSIA2_MCLK 107 +-#define LOCHNAGAR2_PIN_GF_GPIO1 108 +-#define LOCHNAGAR2_PIN_GF_GPIO5 109 +-#define LOCHNAGAR2_PIN_DSP_GPIO20 110 +-#define LOCHNAGAR2_PIN_NUM_GPIOS 111 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt6397-pinfunc.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt6397-pinfunc.h +deleted file mode 100644 +index f393fbd68905..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt6397-pinfunc.h ++++ /dev/null +@@ -1,257 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DTS_MT6397_PINFUNC_H +-#define __DTS_MT6397_PINFUNC_H +- +-#include +- +-#define MT6397_PIN_0_INT__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +-#define MT6397_PIN_0_INT__FUNC_INT (MTK_PIN_NO(0) | 1) +- +-#define MT6397_PIN_1_SRCVOLTEN__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +-#define MT6397_PIN_1_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(1) | 1) +-#define MT6397_PIN_1_SRCVOLTEN__FUNC_TEST_CK1 (MTK_PIN_NO(1) | 6) +- +-#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +-#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_SRCLKEN_PERI (MTK_PIN_NO(2) | 1) +-#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_TEST_CK2 (MTK_PIN_NO(2) | 6) +- +-#define MT6397_PIN_3_RTC_32K1V8__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +-#define MT6397_PIN_3_RTC_32K1V8__FUNC_RTC_32K1V8 (MTK_PIN_NO(3) | 1) +-#define MT6397_PIN_3_RTC_32K1V8__FUNC_TEST_CK3 (MTK_PIN_NO(3) | 6) +- +-#define MT6397_PIN_4_WRAP_EVENT__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +-#define MT6397_PIN_4_WRAP_EVENT__FUNC_WRAP_EVENT (MTK_PIN_NO(4) | 1) +- +-#define MT6397_PIN_5_SPI_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +-#define MT6397_PIN_5_SPI_CLK__FUNC_SPI_CLK (MTK_PIN_NO(5) | 1) +- +-#define MT6397_PIN_6_SPI_CSN__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +-#define MT6397_PIN_6_SPI_CSN__FUNC_SPI_CSN (MTK_PIN_NO(6) | 1) +- +-#define MT6397_PIN_7_SPI_MOSI__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +-#define MT6397_PIN_7_SPI_MOSI__FUNC_SPI_MOSI (MTK_PIN_NO(7) | 1) +- +-#define MT6397_PIN_8_SPI_MISO__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +-#define MT6397_PIN_8_SPI_MISO__FUNC_SPI_MISO (MTK_PIN_NO(8) | 1) +- +-#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +-#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(9) | 1) +-#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_IN0 (MTK_PIN_NO(9) | 6) +-#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_OUT0 (MTK_PIN_NO(9) | 7) +- +-#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +-#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_AUD_MISO (MTK_PIN_NO(10) | 1) +-#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_IN1 (MTK_PIN_NO(10) | 6) +-#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_OUT1 (MTK_PIN_NO(10) | 7) +- +-#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +-#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_AUD_MOSI (MTK_PIN_NO(11) | 1) +-#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_IN2 (MTK_PIN_NO(11) | 6) +-#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_OUT2 (MTK_PIN_NO(11) | 7) +- +-#define MT6397_PIN_12_COL0__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +-#define MT6397_PIN_12_COL0__FUNC_COL0_USBDL (MTK_PIN_NO(12) | 1) +-#define MT6397_PIN_12_COL0__FUNC_EINT10_1X (MTK_PIN_NO(12) | 2) +-#define MT6397_PIN_12_COL0__FUNC_PWM1_3X (MTK_PIN_NO(12) | 3) +-#define MT6397_PIN_12_COL0__FUNC_TEST_IN3 (MTK_PIN_NO(12) | 6) +-#define MT6397_PIN_12_COL0__FUNC_TEST_OUT3 (MTK_PIN_NO(12) | 7) +- +-#define MT6397_PIN_13_COL1__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +-#define MT6397_PIN_13_COL1__FUNC_COL1 (MTK_PIN_NO(13) | 1) +-#define MT6397_PIN_13_COL1__FUNC_EINT11_1X (MTK_PIN_NO(13) | 2) +-#define MT6397_PIN_13_COL1__FUNC_SCL0_2X (MTK_PIN_NO(13) | 3) +-#define MT6397_PIN_13_COL1__FUNC_TEST_IN4 (MTK_PIN_NO(13) | 6) +-#define MT6397_PIN_13_COL1__FUNC_TEST_OUT4 (MTK_PIN_NO(13) | 7) +- +-#define MT6397_PIN_14_COL2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +-#define MT6397_PIN_14_COL2__FUNC_COL2 (MTK_PIN_NO(14) | 1) +-#define MT6397_PIN_14_COL2__FUNC_EINT12_1X (MTK_PIN_NO(14) | 2) +-#define MT6397_PIN_14_COL2__FUNC_SDA0_2X (MTK_PIN_NO(14) | 3) +-#define MT6397_PIN_14_COL2__FUNC_TEST_IN5 (MTK_PIN_NO(14) | 6) +-#define MT6397_PIN_14_COL2__FUNC_TEST_OUT5 (MTK_PIN_NO(14) | 7) +- +-#define MT6397_PIN_15_COL3__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +-#define MT6397_PIN_15_COL3__FUNC_COL3 (MTK_PIN_NO(15) | 1) +-#define MT6397_PIN_15_COL3__FUNC_EINT13_1X (MTK_PIN_NO(15) | 2) +-#define MT6397_PIN_15_COL3__FUNC_SCL1_2X (MTK_PIN_NO(15) | 3) +-#define MT6397_PIN_15_COL3__FUNC_TEST_IN6 (MTK_PIN_NO(15) | 6) +-#define MT6397_PIN_15_COL3__FUNC_TEST_OUT6 (MTK_PIN_NO(15) | 7) +- +-#define MT6397_PIN_16_COL4__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +-#define MT6397_PIN_16_COL4__FUNC_COL4 (MTK_PIN_NO(16) | 1) +-#define MT6397_PIN_16_COL4__FUNC_EINT14_1X (MTK_PIN_NO(16) | 2) +-#define MT6397_PIN_16_COL4__FUNC_SDA1_2X (MTK_PIN_NO(16) | 3) +-#define MT6397_PIN_16_COL4__FUNC_TEST_IN7 (MTK_PIN_NO(16) | 6) +-#define MT6397_PIN_16_COL4__FUNC_TEST_OUT7 (MTK_PIN_NO(16) | 7) +- +-#define MT6397_PIN_17_COL5__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +-#define MT6397_PIN_17_COL5__FUNC_COL5 (MTK_PIN_NO(17) | 1) +-#define MT6397_PIN_17_COL5__FUNC_EINT15_1X (MTK_PIN_NO(17) | 2) +-#define MT6397_PIN_17_COL5__FUNC_SCL2_2X (MTK_PIN_NO(17) | 3) +-#define MT6397_PIN_17_COL5__FUNC_TEST_IN8 (MTK_PIN_NO(17) | 6) +-#define MT6397_PIN_17_COL5__FUNC_TEST_OUT8 (MTK_PIN_NO(17) | 7) +- +-#define MT6397_PIN_18_COL6__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +-#define MT6397_PIN_18_COL6__FUNC_COL6 (MTK_PIN_NO(18) | 1) +-#define MT6397_PIN_18_COL6__FUNC_EINT16_1X (MTK_PIN_NO(18) | 2) +-#define MT6397_PIN_18_COL6__FUNC_SDA2_2X (MTK_PIN_NO(18) | 3) +-#define MT6397_PIN_18_COL6__FUNC_GPIO32K_0 (MTK_PIN_NO(18) | 4) +-#define MT6397_PIN_18_COL6__FUNC_GPIO26M_0 (MTK_PIN_NO(18) | 5) +-#define MT6397_PIN_18_COL6__FUNC_TEST_IN9 (MTK_PIN_NO(18) | 6) +-#define MT6397_PIN_18_COL6__FUNC_TEST_OUT9 (MTK_PIN_NO(18) | 7) +- +-#define MT6397_PIN_19_COL7__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +-#define MT6397_PIN_19_COL7__FUNC_COL7 (MTK_PIN_NO(19) | 1) +-#define MT6397_PIN_19_COL7__FUNC_EINT17_1X (MTK_PIN_NO(19) | 2) +-#define MT6397_PIN_19_COL7__FUNC_PWM2_3X (MTK_PIN_NO(19) | 3) +-#define MT6397_PIN_19_COL7__FUNC_GPIO32K_1 (MTK_PIN_NO(19) | 4) +-#define MT6397_PIN_19_COL7__FUNC_GPIO26M_1 (MTK_PIN_NO(19) | 5) +-#define MT6397_PIN_19_COL7__FUNC_TEST_IN10 (MTK_PIN_NO(19) | 6) +-#define MT6397_PIN_19_COL7__FUNC_TEST_OUT10 (MTK_PIN_NO(19) | 7) +- +-#define MT6397_PIN_20_ROW0__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +-#define MT6397_PIN_20_ROW0__FUNC_ROW0 (MTK_PIN_NO(20) | 1) +-#define MT6397_PIN_20_ROW0__FUNC_EINT18_1X (MTK_PIN_NO(20) | 2) +-#define MT6397_PIN_20_ROW0__FUNC_SCL0_3X (MTK_PIN_NO(20) | 3) +-#define MT6397_PIN_20_ROW0__FUNC_TEST_IN11 (MTK_PIN_NO(20) | 6) +-#define MT6397_PIN_20_ROW0__FUNC_TEST_OUT11 (MTK_PIN_NO(20) | 7) +- +-#define MT6397_PIN_21_ROW1__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +-#define MT6397_PIN_21_ROW1__FUNC_ROW1 (MTK_PIN_NO(21) | 1) +-#define MT6397_PIN_21_ROW1__FUNC_EINT19_1X (MTK_PIN_NO(21) | 2) +-#define MT6397_PIN_21_ROW1__FUNC_SDA0_3X (MTK_PIN_NO(21) | 3) +-#define MT6397_PIN_21_ROW1__FUNC_AUD_TSTCK (MTK_PIN_NO(21) | 4) +-#define MT6397_PIN_21_ROW1__FUNC_TEST_IN12 (MTK_PIN_NO(21) | 6) +-#define MT6397_PIN_21_ROW1__FUNC_TEST_OUT12 (MTK_PIN_NO(21) | 7) +- +-#define MT6397_PIN_22_ROW2__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +-#define MT6397_PIN_22_ROW2__FUNC_ROW2 (MTK_PIN_NO(22) | 1) +-#define MT6397_PIN_22_ROW2__FUNC_EINT20_1X (MTK_PIN_NO(22) | 2) +-#define MT6397_PIN_22_ROW2__FUNC_SCL1_3X (MTK_PIN_NO(22) | 3) +-#define MT6397_PIN_22_ROW2__FUNC_TEST_IN13 (MTK_PIN_NO(22) | 6) +-#define MT6397_PIN_22_ROW2__FUNC_TEST_OUT13 (MTK_PIN_NO(22) | 7) +- +-#define MT6397_PIN_23_ROW3__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +-#define MT6397_PIN_23_ROW3__FUNC_ROW3 (MTK_PIN_NO(23) | 1) +-#define MT6397_PIN_23_ROW3__FUNC_EINT21_1X (MTK_PIN_NO(23) | 2) +-#define MT6397_PIN_23_ROW3__FUNC_SDA1_3X (MTK_PIN_NO(23) | 3) +-#define MT6397_PIN_23_ROW3__FUNC_TEST_IN14 (MTK_PIN_NO(23) | 6) +-#define MT6397_PIN_23_ROW3__FUNC_TEST_OUT14 (MTK_PIN_NO(23) | 7) +- +-#define MT6397_PIN_24_ROW4__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +-#define MT6397_PIN_24_ROW4__FUNC_ROW4 (MTK_PIN_NO(24) | 1) +-#define MT6397_PIN_24_ROW4__FUNC_EINT22_1X (MTK_PIN_NO(24) | 2) +-#define MT6397_PIN_24_ROW4__FUNC_SCL2_3X (MTK_PIN_NO(24) | 3) +-#define MT6397_PIN_24_ROW4__FUNC_TEST_IN15 (MTK_PIN_NO(24) | 6) +-#define MT6397_PIN_24_ROW4__FUNC_TEST_OUT15 (MTK_PIN_NO(24) | 7) +- +-#define MT6397_PIN_25_ROW5__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +-#define MT6397_PIN_25_ROW5__FUNC_ROW5 (MTK_PIN_NO(25) | 1) +-#define MT6397_PIN_25_ROW5__FUNC_EINT23_1X (MTK_PIN_NO(25) | 2) +-#define MT6397_PIN_25_ROW5__FUNC_SDA2_3X (MTK_PIN_NO(25) | 3) +-#define MT6397_PIN_25_ROW5__FUNC_TEST_IN16 (MTK_PIN_NO(25) | 6) +-#define MT6397_PIN_25_ROW5__FUNC_TEST_OUT16 (MTK_PIN_NO(25) | 7) +- +-#define MT6397_PIN_26_ROW6__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +-#define MT6397_PIN_26_ROW6__FUNC_ROW6 (MTK_PIN_NO(26) | 1) +-#define MT6397_PIN_26_ROW6__FUNC_EINT24_1X (MTK_PIN_NO(26) | 2) +-#define MT6397_PIN_26_ROW6__FUNC_PWM3_3X (MTK_PIN_NO(26) | 3) +-#define MT6397_PIN_26_ROW6__FUNC_GPIO32K_2 (MTK_PIN_NO(26) | 4) +-#define MT6397_PIN_26_ROW6__FUNC_GPIO26M_2 (MTK_PIN_NO(26) | 5) +-#define MT6397_PIN_26_ROW6__FUNC_TEST_IN17 (MTK_PIN_NO(26) | 6) +-#define MT6397_PIN_26_ROW6__FUNC_TEST_OUT17 (MTK_PIN_NO(26) | 7) +- +-#define MT6397_PIN_27_ROW7__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +-#define MT6397_PIN_27_ROW7__FUNC_ROW7 (MTK_PIN_NO(27) | 1) +-#define MT6397_PIN_27_ROW7__FUNC_EINT3_1X (MTK_PIN_NO(27) | 2) +-#define MT6397_PIN_27_ROW7__FUNC_CBUS (MTK_PIN_NO(27) | 3) +-#define MT6397_PIN_27_ROW7__FUNC_GPIO32K_3 (MTK_PIN_NO(27) | 4) +-#define MT6397_PIN_27_ROW7__FUNC_GPIO26M_3 (MTK_PIN_NO(27) | 5) +-#define MT6397_PIN_27_ROW7__FUNC_TEST_IN18 (MTK_PIN_NO(27) | 6) +-#define MT6397_PIN_27_ROW7__FUNC_TEST_OUT18 (MTK_PIN_NO(27) | 7) +- +-#define MT6397_PIN_28_PWM1__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +-#define MT6397_PIN_28_PWM1__FUNC_PWM1 (MTK_PIN_NO(28) | 1) +-#define MT6397_PIN_28_PWM1__FUNC_EINT4_1X (MTK_PIN_NO(28) | 2) +-#define MT6397_PIN_28_PWM1__FUNC_GPIO32K_4 (MTK_PIN_NO(28) | 4) +-#define MT6397_PIN_28_PWM1__FUNC_GPIO26M_4 (MTK_PIN_NO(28) | 5) +-#define MT6397_PIN_28_PWM1__FUNC_TEST_IN19 (MTK_PIN_NO(28) | 6) +-#define MT6397_PIN_28_PWM1__FUNC_TEST_OUT19 (MTK_PIN_NO(28) | 7) +- +-#define MT6397_PIN_29_PWM2__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +-#define MT6397_PIN_29_PWM2__FUNC_PWM2 (MTK_PIN_NO(29) | 1) +-#define MT6397_PIN_29_PWM2__FUNC_EINT5_1X (MTK_PIN_NO(29) | 2) +-#define MT6397_PIN_29_PWM2__FUNC_GPIO32K_5 (MTK_PIN_NO(29) | 4) +-#define MT6397_PIN_29_PWM2__FUNC_GPIO26M_5 (MTK_PIN_NO(29) | 5) +-#define MT6397_PIN_29_PWM2__FUNC_TEST_IN20 (MTK_PIN_NO(29) | 6) +-#define MT6397_PIN_29_PWM2__FUNC_TEST_OUT20 (MTK_PIN_NO(29) | 7) +- +-#define MT6397_PIN_30_PWM3__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +-#define MT6397_PIN_30_PWM3__FUNC_PWM3 (MTK_PIN_NO(30) | 1) +-#define MT6397_PIN_30_PWM3__FUNC_EINT6_1X (MTK_PIN_NO(30) | 2) +-#define MT6397_PIN_30_PWM3__FUNC_COL0 (MTK_PIN_NO(30) | 3) +-#define MT6397_PIN_30_PWM3__FUNC_GPIO32K_6 (MTK_PIN_NO(30) | 4) +-#define MT6397_PIN_30_PWM3__FUNC_GPIO26M_6 (MTK_PIN_NO(30) | 5) +-#define MT6397_PIN_30_PWM3__FUNC_TEST_IN21 (MTK_PIN_NO(30) | 6) +-#define MT6397_PIN_30_PWM3__FUNC_TEST_OUT21 (MTK_PIN_NO(30) | 7) +- +-#define MT6397_PIN_31_SCL0__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +-#define MT6397_PIN_31_SCL0__FUNC_SCL0 (MTK_PIN_NO(31) | 1) +-#define MT6397_PIN_31_SCL0__FUNC_EINT7_1X (MTK_PIN_NO(31) | 2) +-#define MT6397_PIN_31_SCL0__FUNC_PWM1_2X (MTK_PIN_NO(31) | 3) +-#define MT6397_PIN_31_SCL0__FUNC_TEST_IN22 (MTK_PIN_NO(31) | 6) +-#define MT6397_PIN_31_SCL0__FUNC_TEST_OUT22 (MTK_PIN_NO(31) | 7) +- +-#define MT6397_PIN_32_SDA0__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +-#define MT6397_PIN_32_SDA0__FUNC_SDA0 (MTK_PIN_NO(32) | 1) +-#define MT6397_PIN_32_SDA0__FUNC_EINT8_1X (MTK_PIN_NO(32) | 2) +-#define MT6397_PIN_32_SDA0__FUNC_TEST_IN23 (MTK_PIN_NO(32) | 6) +-#define MT6397_PIN_32_SDA0__FUNC_TEST_OUT23 (MTK_PIN_NO(32) | 7) +- +-#define MT6397_PIN_33_SCL1__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +-#define MT6397_PIN_33_SCL1__FUNC_SCL1 (MTK_PIN_NO(33) | 1) +-#define MT6397_PIN_33_SCL1__FUNC_EINT9_1X (MTK_PIN_NO(33) | 2) +-#define MT6397_PIN_33_SCL1__FUNC_PWM2_2X (MTK_PIN_NO(33) | 3) +-#define MT6397_PIN_33_SCL1__FUNC_TEST_IN24 (MTK_PIN_NO(33) | 6) +-#define MT6397_PIN_33_SCL1__FUNC_TEST_OUT24 (MTK_PIN_NO(33) | 7) +- +-#define MT6397_PIN_34_SDA1__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +-#define MT6397_PIN_34_SDA1__FUNC_SDA1 (MTK_PIN_NO(34) | 1) +-#define MT6397_PIN_34_SDA1__FUNC_EINT0_1X (MTK_PIN_NO(34) | 2) +-#define MT6397_PIN_34_SDA1__FUNC_TEST_IN25 (MTK_PIN_NO(34) | 6) +-#define MT6397_PIN_34_SDA1__FUNC_TEST_OUT25 (MTK_PIN_NO(34) | 7) +- +-#define MT6397_PIN_35_SCL2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +-#define MT6397_PIN_35_SCL2__FUNC_SCL2 (MTK_PIN_NO(35) | 1) +-#define MT6397_PIN_35_SCL2__FUNC_EINT1_1X (MTK_PIN_NO(35) | 2) +-#define MT6397_PIN_35_SCL2__FUNC_PWM3_2X (MTK_PIN_NO(35) | 3) +-#define MT6397_PIN_35_SCL2__FUNC_TEST_IN26 (MTK_PIN_NO(35) | 6) +-#define MT6397_PIN_35_SCL2__FUNC_TEST_OUT26 (MTK_PIN_NO(35) | 7) +- +-#define MT6397_PIN_36_SDA2__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +-#define MT6397_PIN_36_SDA2__FUNC_SDA2 (MTK_PIN_NO(36) | 1) +-#define MT6397_PIN_36_SDA2__FUNC_EINT2_1X (MTK_PIN_NO(36) | 2) +-#define MT6397_PIN_36_SDA2__FUNC_TEST_IN27 (MTK_PIN_NO(36) | 6) +-#define MT6397_PIN_36_SDA2__FUNC_TEST_OUT27 (MTK_PIN_NO(36) | 7) +- +-#define MT6397_PIN_37_HDMISD__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +-#define MT6397_PIN_37_HDMISD__FUNC_HDMISD (MTK_PIN_NO(37) | 1) +-#define MT6397_PIN_37_HDMISD__FUNC_TEST_IN28 (MTK_PIN_NO(37) | 6) +-#define MT6397_PIN_37_HDMISD__FUNC_TEST_OUT28 (MTK_PIN_NO(37) | 7) +- +-#define MT6397_PIN_38_HDMISCK__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +-#define MT6397_PIN_38_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(38) | 1) +-#define MT6397_PIN_38_HDMISCK__FUNC_TEST_IN29 (MTK_PIN_NO(38) | 6) +-#define MT6397_PIN_38_HDMISCK__FUNC_TEST_OUT29 (MTK_PIN_NO(38) | 7) +- +-#define MT6397_PIN_39_HTPLG__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +-#define MT6397_PIN_39_HTPLG__FUNC_HTPLG (MTK_PIN_NO(39) | 1) +-#define MT6397_PIN_39_HTPLG__FUNC_TEST_IN30 (MTK_PIN_NO(39) | 6) +-#define MT6397_PIN_39_HTPLG__FUNC_TEST_OUT30 (MTK_PIN_NO(39) | 7) +- +-#define MT6397_PIN_40_CEC__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +-#define MT6397_PIN_40_CEC__FUNC_CEC (MTK_PIN_NO(40) | 1) +-#define MT6397_PIN_40_CEC__FUNC_TEST_IN31 (MTK_PIN_NO(40) | 6) +-#define MT6397_PIN_40_CEC__FUNC_TEST_OUT31 (MTK_PIN_NO(40) | 7) +- +-#endif /* __DTS_MT6397_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt65xx.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt65xx.h +deleted file mode 100644 +index 7e16e58fe1f7..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt65xx.h ++++ /dev/null +@@ -1,32 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014 MediaTek Inc. +- * Author: Hongzhou.Yang +- */ +- +-#ifndef _DT_BINDINGS_PINCTRL_MT65XX_H +-#define _DT_BINDINGS_PINCTRL_MT65XX_H +- +-#define MTK_PIN_NO(x) ((x) << 8) +-#define MTK_GET_PIN_NO(x) ((x) >> 8) +-#define MTK_GET_PIN_FUNC(x) ((x) & 0xf) +- +-#define MTK_PUPD_SET_R1R0_00 100 +-#define MTK_PUPD_SET_R1R0_01 101 +-#define MTK_PUPD_SET_R1R0_10 102 +-#define MTK_PUPD_SET_R1R0_11 103 +- +-#define MTK_DRIVE_2mA 2 +-#define MTK_DRIVE_4mA 4 +-#define MTK_DRIVE_6mA 6 +-#define MTK_DRIVE_8mA 8 +-#define MTK_DRIVE_10mA 10 +-#define MTK_DRIVE_12mA 12 +-#define MTK_DRIVE_14mA 14 +-#define MTK_DRIVE_16mA 16 +-#define MTK_DRIVE_20mA 20 +-#define MTK_DRIVE_24mA 24 +-#define MTK_DRIVE_28mA 28 +-#define MTK_DRIVE_32mA 32 +- +-#endif /* _DT_BINDINGS_PINCTRL_MT65XX_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt6779-pinfunc.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt6779-pinfunc.h +deleted file mode 100644 +index 87fdc4310936..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt6779-pinfunc.h ++++ /dev/null +@@ -1,1242 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2019 MediaTek Inc. +- * Author: Andy Teng +- * +- */ +- +-#ifndef __MT6779_PINFUNC_H +-#define __MT6779_PINFUNC_H +- +-#include +- +-#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +-#define PINMUX_GPIO0__FUNC_SPI6_MI (MTK_PIN_NO(0) | 1) +-#define PINMUX_GPIO0__FUNC_I2S5_LRCK (MTK_PIN_NO(0) | 2) +-#define PINMUX_GPIO0__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(0) | 3) +-#define PINMUX_GPIO0__FUNC_PCM1_SYNC (MTK_PIN_NO(0) | 4) +-#define PINMUX_GPIO0__FUNC_SCL_6306 (MTK_PIN_NO(0) | 5) +-#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 6) +-#define PINMUX_GPIO0__FUNC_PTA_RXD (MTK_PIN_NO(0) | 7) +- +-#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +-#define PINMUX_GPIO1__FUNC_SPI6_CSB (MTK_PIN_NO(1) | 1) +-#define PINMUX_GPIO1__FUNC_I2S5_DO (MTK_PIN_NO(1) | 2) +-#define PINMUX_GPIO1__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(1) | 3) +-#define PINMUX_GPIO1__FUNC_PCM1_DO0 (MTK_PIN_NO(1) | 4) +-#define PINMUX_GPIO1__FUNC_SDA_6306 (MTK_PIN_NO(1) | 5) +-#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 6) +-#define PINMUX_GPIO1__FUNC_PTA_TXD (MTK_PIN_NO(1) | 7) +- +-#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +-#define PINMUX_GPIO2__FUNC_SPI6_MO (MTK_PIN_NO(2) | 1) +-#define PINMUX_GPIO2__FUNC_I2S5_BCK (MTK_PIN_NO(2) | 2) +-#define PINMUX_GPIO2__FUNC_TDM_BCK_2ND (MTK_PIN_NO(2) | 3) +-#define PINMUX_GPIO2__FUNC_PCM1_CLK (MTK_PIN_NO(2) | 4) +-#define PINMUX_GPIO2__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(2) | 5) +-#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 6) +- +-#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +-#define PINMUX_GPIO3__FUNC_SPI6_CLK (MTK_PIN_NO(3) | 1) +-#define PINMUX_GPIO3__FUNC_I2S5_MCK (MTK_PIN_NO(3) | 2) +-#define PINMUX_GPIO3__FUNC_TDM_MCK_2ND (MTK_PIN_NO(3) | 3) +-#define PINMUX_GPIO3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(3) | 4) +-#define PINMUX_GPIO3__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(3) | 5) +-#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 6) +- +-#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +-#define PINMUX_GPIO4__FUNC_SPI7_MI (MTK_PIN_NO(4) | 1) +-#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2) +-#define PINMUX_GPIO4__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(4) | 3) +-#define PINMUX_GPIO4__FUNC_PCM1_DO1 (MTK_PIN_NO(4) | 4) +-#define PINMUX_GPIO4__FUNC_DMIC1_CLK (MTK_PIN_NO(4) | 5) +-#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6) +-#define PINMUX_GPIO4__FUNC_SCL8 (MTK_PIN_NO(4) | 7) +- +-#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +-#define PINMUX_GPIO5__FUNC_SPI7_CSB (MTK_PIN_NO(5) | 1) +-#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2) +-#define PINMUX_GPIO5__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(5) | 3) +-#define PINMUX_GPIO5__FUNC_PCM1_DO2 (MTK_PIN_NO(5) | 4) +-#define PINMUX_GPIO5__FUNC_DMIC1_DAT (MTK_PIN_NO(5) | 5) +-#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6) +-#define PINMUX_GPIO5__FUNC_SDA8 (MTK_PIN_NO(5) | 7) +- +-#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +-#define PINMUX_GPIO6__FUNC_SPI7_MO (MTK_PIN_NO(6) | 1) +-#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2) +-#define PINMUX_GPIO6__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(6) | 3) +-#define PINMUX_GPIO6__FUNC_PCM1_DI (MTK_PIN_NO(6) | 4) +-#define PINMUX_GPIO6__FUNC_DMIC_CLK (MTK_PIN_NO(6) | 5) +-#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6) +-#define PINMUX_GPIO6__FUNC_SCL9 (MTK_PIN_NO(6) | 7) +- +-#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +-#define PINMUX_GPIO7__FUNC_SPI7_CLK (MTK_PIN_NO(7) | 1) +-#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2) +-#define PINMUX_GPIO7__FUNC_SRCLKENAI1 (MTK_PIN_NO(7) | 3) +-#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 4) +-#define PINMUX_GPIO7__FUNC_DMIC_DAT (MTK_PIN_NO(7) | 5) +-#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6) +-#define PINMUX_GPIO7__FUNC_SDA9 (MTK_PIN_NO(7) | 7) +- +-#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +-#define PINMUX_GPIO8__FUNC_PWM_0 (MTK_PIN_NO(8) | 1) +-#define PINMUX_GPIO8__FUNC_I2S2_DI2 (MTK_PIN_NO(8) | 2) +-#define PINMUX_GPIO8__FUNC_SRCLKENAI0 (MTK_PIN_NO(8) | 3) +-#define PINMUX_GPIO8__FUNC_URXD1 (MTK_PIN_NO(8) | 4) +-#define PINMUX_GPIO8__FUNC_I2S0_MCK (MTK_PIN_NO(8) | 5) +-#define PINMUX_GPIO8__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(8) | 6) +-#define PINMUX_GPIO8__FUNC_IDDIG (MTK_PIN_NO(8) | 7) +- +-#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +-#define PINMUX_GPIO9__FUNC_PWM_3 (MTK_PIN_NO(9) | 1) +-#define PINMUX_GPIO9__FUNC_MD_INT0 (MTK_PIN_NO(9) | 2) +-#define PINMUX_GPIO9__FUNC_SRCLKENAI1 (MTK_PIN_NO(9) | 3) +-#define PINMUX_GPIO9__FUNC_UTXD1 (MTK_PIN_NO(9) | 4) +-#define PINMUX_GPIO9__FUNC_I2S0_BCK (MTK_PIN_NO(9) | 5) +-#define PINMUX_GPIO9__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(9) | 6) +-#define PINMUX_GPIO9__FUNC_USB_DRVVBUS (MTK_PIN_NO(9) | 7) +- +-#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +-#define PINMUX_GPIO10__FUNC_MSDC1_CLK_A (MTK_PIN_NO(10) | 1) +-#define PINMUX_GPIO10__FUNC_TP_URXD1_AO (MTK_PIN_NO(10) | 2) +-#define PINMUX_GPIO10__FUNC_I2S1_LRCK (MTK_PIN_NO(10) | 3) +-#define PINMUX_GPIO10__FUNC_UCTS0 (MTK_PIN_NO(10) | 4) +-#define PINMUX_GPIO10__FUNC_DMIC1_CLK (MTK_PIN_NO(10) | 5) +-#define PINMUX_GPIO10__FUNC_KPCOL2 (MTK_PIN_NO(10) | 6) +-#define PINMUX_GPIO10__FUNC_SCL8 (MTK_PIN_NO(10) | 7) +- +-#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +-#define PINMUX_GPIO11__FUNC_MSDC1_CMD_A (MTK_PIN_NO(11) | 1) +-#define PINMUX_GPIO11__FUNC_TP_UTXD1_AO (MTK_PIN_NO(11) | 2) +-#define PINMUX_GPIO11__FUNC_I2S1_DO (MTK_PIN_NO(11) | 3) +-#define PINMUX_GPIO11__FUNC_URTS0 (MTK_PIN_NO(11) | 4) +-#define PINMUX_GPIO11__FUNC_DMIC1_DAT (MTK_PIN_NO(11) | 5) +-#define PINMUX_GPIO11__FUNC_KPROW2 (MTK_PIN_NO(11) | 6) +-#define PINMUX_GPIO11__FUNC_SDA8 (MTK_PIN_NO(11) | 7) +- +-#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +-#define PINMUX_GPIO12__FUNC_MSDC1_DAT3_A (MTK_PIN_NO(12) | 1) +-#define PINMUX_GPIO12__FUNC_TP_URXD2_AO (MTK_PIN_NO(12) | 2) +-#define PINMUX_GPIO12__FUNC_I2S1_MCK (MTK_PIN_NO(12) | 3) +-#define PINMUX_GPIO12__FUNC_UCTS1 (MTK_PIN_NO(12) | 4) +-#define PINMUX_GPIO12__FUNC_DMIC_CLK (MTK_PIN_NO(12) | 5) +-#define PINMUX_GPIO12__FUNC_ANT_SEL9 (MTK_PIN_NO(12) | 6) +-#define PINMUX_GPIO12__FUNC_SCL9 (MTK_PIN_NO(12) | 7) +- +-#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +-#define PINMUX_GPIO13__FUNC_MSDC1_DAT0_A (MTK_PIN_NO(13) | 1) +-#define PINMUX_GPIO13__FUNC_TP_UTXD2_AO (MTK_PIN_NO(13) | 2) +-#define PINMUX_GPIO13__FUNC_I2S1_BCK (MTK_PIN_NO(13) | 3) +-#define PINMUX_GPIO13__FUNC_URTS1 (MTK_PIN_NO(13) | 4) +-#define PINMUX_GPIO13__FUNC_DMIC_DAT (MTK_PIN_NO(13) | 5) +-#define PINMUX_GPIO13__FUNC_ANT_SEL10 (MTK_PIN_NO(13) | 6) +-#define PINMUX_GPIO13__FUNC_SDA9 (MTK_PIN_NO(13) | 7) +- +-#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +-#define PINMUX_GPIO14__FUNC_MSDC1_DAT2_A (MTK_PIN_NO(14) | 1) +-#define PINMUX_GPIO14__FUNC_PWM_3 (MTK_PIN_NO(14) | 2) +-#define PINMUX_GPIO14__FUNC_IDDIG (MTK_PIN_NO(14) | 3) +-#define PINMUX_GPIO14__FUNC_MD_INT0 (MTK_PIN_NO(14) | 4) +-#define PINMUX_GPIO14__FUNC_PTA_RXD (MTK_PIN_NO(14) | 5) +-#define PINMUX_GPIO14__FUNC_ANT_SEL11 (MTK_PIN_NO(14) | 6) +- +-#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +-#define PINMUX_GPIO15__FUNC_MSDC1_DAT1_A (MTK_PIN_NO(15) | 1) +-#define PINMUX_GPIO15__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(15) | 2) +-#define PINMUX_GPIO15__FUNC_USB_DRVVBUS (MTK_PIN_NO(15) | 3) +-#define PINMUX_GPIO15__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(15) | 4) +-#define PINMUX_GPIO15__FUNC_PTA_TXD (MTK_PIN_NO(15) | 5) +-#define PINMUX_GPIO15__FUNC_ANT_SEL12 (MTK_PIN_NO(15) | 6) +- +-#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +-#define PINMUX_GPIO16__FUNC_SRCLKENAI0 (MTK_PIN_NO(16) | 1) +-#define PINMUX_GPIO16__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(16) | 2) +-#define PINMUX_GPIO16__FUNC_MFG_EJTAG_TRSTN (MTK_PIN_NO(16) | 3) +-#define PINMUX_GPIO16__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(16) | 4) +-#define PINMUX_GPIO16__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(16) | 5) +-#define PINMUX_GPIO16__FUNC_PWM_2 (MTK_PIN_NO(16) | 6) +-#define PINMUX_GPIO16__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(16) | 7) +- +-#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +-#define PINMUX_GPIO17__FUNC_SPI0_A_MI (MTK_PIN_NO(17) | 1) +-#define PINMUX_GPIO17__FUNC_SCP_SPI0_MI (MTK_PIN_NO(17) | 2) +-#define PINMUX_GPIO17__FUNC_MFG_EJTAG_TDO (MTK_PIN_NO(17) | 3) +-#define PINMUX_GPIO17__FUNC_DPI_HSYNC (MTK_PIN_NO(17) | 4) +-#define PINMUX_GPIO17__FUNC_MFG_DFD_JTAG_TDO (MTK_PIN_NO(17) | 5) +-#define PINMUX_GPIO17__FUNC_DFD_TDO (MTK_PIN_NO(17) | 6) +-#define PINMUX_GPIO17__FUNC_JTDO_SEL1 (MTK_PIN_NO(17) | 7) +- +-#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +-#define PINMUX_GPIO18__FUNC_SPI0_A_MO (MTK_PIN_NO(18) | 1) +-#define PINMUX_GPIO18__FUNC_SCP_SPI0_MO (MTK_PIN_NO(18) | 2) +-#define PINMUX_GPIO18__FUNC_MFG_EJTAG_TDI (MTK_PIN_NO(18) | 3) +-#define PINMUX_GPIO18__FUNC_DPI_VSYNC (MTK_PIN_NO(18) | 4) +-#define PINMUX_GPIO18__FUNC_MFG_DFD_JTAG_TDI (MTK_PIN_NO(18) | 5) +-#define PINMUX_GPIO18__FUNC_DFD_TDI (MTK_PIN_NO(18) | 6) +-#define PINMUX_GPIO18__FUNC_JTDI_SEL1 (MTK_PIN_NO(18) | 7) +- +-#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +-#define PINMUX_GPIO19__FUNC_SPI0_A_CSB (MTK_PIN_NO(19) | 1) +-#define PINMUX_GPIO19__FUNC_SCP_SPI0_CS (MTK_PIN_NO(19) | 2) +-#define PINMUX_GPIO19__FUNC_MFG_EJTAG_TMS (MTK_PIN_NO(19) | 3) +-#define PINMUX_GPIO19__FUNC_DPI_DE (MTK_PIN_NO(19) | 4) +-#define PINMUX_GPIO19__FUNC_MFG_DFD_JTAG_TMS (MTK_PIN_NO(19) | 5) +-#define PINMUX_GPIO19__FUNC_DFD_TMS (MTK_PIN_NO(19) | 6) +-#define PINMUX_GPIO19__FUNC_JTMS_SEL1 (MTK_PIN_NO(19) | 7) +- +-#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +-#define PINMUX_GPIO20__FUNC_SPI0_A_CLK (MTK_PIN_NO(20) | 1) +-#define PINMUX_GPIO20__FUNC_SCP_SPI0_CK (MTK_PIN_NO(20) | 2) +-#define PINMUX_GPIO20__FUNC_MFG_EJTAG_TCK (MTK_PIN_NO(20) | 3) +-#define PINMUX_GPIO20__FUNC_DPI_CK (MTK_PIN_NO(20) | 4) +-#define PINMUX_GPIO20__FUNC_MFG_DFD_JTAG_TCK (MTK_PIN_NO(20) | 5) +-#define PINMUX_GPIO20__FUNC_DFD_TCK_XI (MTK_PIN_NO(20) | 6) +-#define PINMUX_GPIO20__FUNC_JTCK_SEL1 (MTK_PIN_NO(20) | 7) +- +-#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +-#define PINMUX_GPIO21__FUNC_PWM_0 (MTK_PIN_NO(21) | 1) +-#define PINMUX_GPIO21__FUNC_CMFLASH0 (MTK_PIN_NO(21) | 2) +-#define PINMUX_GPIO21__FUNC_CMVREF2 (MTK_PIN_NO(21) | 3) +-#define PINMUX_GPIO21__FUNC_CLKM0 (MTK_PIN_NO(21) | 4) +-#define PINMUX_GPIO21__FUNC_ANT_SEL9 (MTK_PIN_NO(21) | 5) +-#define PINMUX_GPIO21__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(21) | 6) +-#define PINMUX_GPIO21__FUNC_DBG_MON_A27 (MTK_PIN_NO(21) | 7) +- +-#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +-#define PINMUX_GPIO22__FUNC_PWM_1 (MTK_PIN_NO(22) | 1) +-#define PINMUX_GPIO22__FUNC_CMFLASH1 (MTK_PIN_NO(22) | 2) +-#define PINMUX_GPIO22__FUNC_CMVREF3 (MTK_PIN_NO(22) | 3) +-#define PINMUX_GPIO22__FUNC_CLKM1 (MTK_PIN_NO(22) | 4) +-#define PINMUX_GPIO22__FUNC_ANT_SEL10 (MTK_PIN_NO(22) | 5) +-#define PINMUX_GPIO22__FUNC_DBG_MON_A28 (MTK_PIN_NO(22) | 7) +- +-#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +-#define PINMUX_GPIO23__FUNC_PWM_2 (MTK_PIN_NO(23) | 1) +-#define PINMUX_GPIO23__FUNC_CMFLASH2 (MTK_PIN_NO(23) | 2) +-#define PINMUX_GPIO23__FUNC_CMVREF0 (MTK_PIN_NO(23) | 3) +-#define PINMUX_GPIO23__FUNC_CLKM2 (MTK_PIN_NO(23) | 4) +-#define PINMUX_GPIO23__FUNC_ANT_SEL11 (MTK_PIN_NO(23) | 5) +-#define PINMUX_GPIO23__FUNC_DBG_MON_A29 (MTK_PIN_NO(23) | 7) +- +-#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +-#define PINMUX_GPIO24__FUNC_PWM_0 (MTK_PIN_NO(24) | 1) +-#define PINMUX_GPIO24__FUNC_CMFLASH3 (MTK_PIN_NO(24) | 2) +-#define PINMUX_GPIO24__FUNC_CMVREF1 (MTK_PIN_NO(24) | 3) +-#define PINMUX_GPIO24__FUNC_CLKM3 (MTK_PIN_NO(24) | 4) +-#define PINMUX_GPIO24__FUNC_ANT_SEL12 (MTK_PIN_NO(24) | 5) +-#define PINMUX_GPIO24__FUNC_DBG_MON_A30 (MTK_PIN_NO(24) | 7) +- +-#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +-#define PINMUX_GPIO25__FUNC_SRCLKENAI0 (MTK_PIN_NO(25) | 1) +-#define PINMUX_GPIO25__FUNC_UCTS0 (MTK_PIN_NO(25) | 2) +-#define PINMUX_GPIO25__FUNC_SCL8 (MTK_PIN_NO(25) | 3) +-#define PINMUX_GPIO25__FUNC_CMVREF4 (MTK_PIN_NO(25) | 4) +-#define PINMUX_GPIO25__FUNC_I2S0_LRCK (MTK_PIN_NO(25) | 5) +-#define PINMUX_GPIO25__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(25) | 6) +-#define PINMUX_GPIO25__FUNC_DBG_MON_A31 (MTK_PIN_NO(25) | 7) +- +-#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +-#define PINMUX_GPIO26__FUNC_PWM_0 (MTK_PIN_NO(26) | 1) +-#define PINMUX_GPIO26__FUNC_URTS0 (MTK_PIN_NO(26) | 2) +-#define PINMUX_GPIO26__FUNC_SDA8 (MTK_PIN_NO(26) | 3) +-#define PINMUX_GPIO26__FUNC_CLKM0 (MTK_PIN_NO(26) | 4) +-#define PINMUX_GPIO26__FUNC_I2S0_DI (MTK_PIN_NO(26) | 5) +-#define PINMUX_GPIO26__FUNC_AGPS_SYNC (MTK_PIN_NO(26) | 6) +-#define PINMUX_GPIO26__FUNC_DBG_MON_A32 (MTK_PIN_NO(26) | 7) +- +-#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +-#define PINMUX_GPIO27__FUNC_AP_GOOD (MTK_PIN_NO(27) | 1) +- +-#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +-#define PINMUX_GPIO28__FUNC_SCL5 (MTK_PIN_NO(28) | 1) +- +-#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +-#define PINMUX_GPIO29__FUNC_SDA5 (MTK_PIN_NO(29) | 1) +- +-#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +-#define PINMUX_GPIO30__FUNC_I2S1_MCK (MTK_PIN_NO(30) | 1) +-#define PINMUX_GPIO30__FUNC_I2S3_MCK (MTK_PIN_NO(30) | 2) +-#define PINMUX_GPIO30__FUNC_I2S2_MCK (MTK_PIN_NO(30) | 3) +-#define PINMUX_GPIO30__FUNC_DPI_D0 (MTK_PIN_NO(30) | 4) +-#define PINMUX_GPIO30__FUNC_SPI4_MI (MTK_PIN_NO(30) | 5) +-#define PINMUX_GPIO30__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(30) | 6) +- +-#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +-#define PINMUX_GPIO31__FUNC_I2S1_BCK (MTK_PIN_NO(31) | 1) +-#define PINMUX_GPIO31__FUNC_I2S3_BCK (MTK_PIN_NO(31) | 2) +-#define PINMUX_GPIO31__FUNC_I2S2_BCK (MTK_PIN_NO(31) | 3) +-#define PINMUX_GPIO31__FUNC_DPI_D1 (MTK_PIN_NO(31) | 4) +-#define PINMUX_GPIO31__FUNC_SPI4_CSB (MTK_PIN_NO(31) | 5) +-#define PINMUX_GPIO31__FUNC_CONN_MCU_TDO (MTK_PIN_NO(31) | 6) +- +-#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +-#define PINMUX_GPIO32__FUNC_I2S1_LRCK (MTK_PIN_NO(32) | 1) +-#define PINMUX_GPIO32__FUNC_I2S3_LRCK (MTK_PIN_NO(32) | 2) +-#define PINMUX_GPIO32__FUNC_I2S2_LRCK (MTK_PIN_NO(32) | 3) +-#define PINMUX_GPIO32__FUNC_DPI_D2 (MTK_PIN_NO(32) | 4) +-#define PINMUX_GPIO32__FUNC_SPI4_MO (MTK_PIN_NO(32) | 5) +-#define PINMUX_GPIO32__FUNC_CONN_MCU_TDI (MTK_PIN_NO(32) | 6) +- +-#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +-#define PINMUX_GPIO33__FUNC_I2S2_DI (MTK_PIN_NO(33) | 1) +-#define PINMUX_GPIO33__FUNC_I2S0_DI (MTK_PIN_NO(33) | 2) +-#define PINMUX_GPIO33__FUNC_I2S5_DO (MTK_PIN_NO(33) | 3) +-#define PINMUX_GPIO33__FUNC_DPI_D3 (MTK_PIN_NO(33) | 4) +-#define PINMUX_GPIO33__FUNC_SPI4_CLK (MTK_PIN_NO(33) | 5) +-#define PINMUX_GPIO33__FUNC_CONN_MCU_TMS (MTK_PIN_NO(33) | 6) +- +-#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +-#define PINMUX_GPIO34__FUNC_I2S1_DO (MTK_PIN_NO(34) | 1) +-#define PINMUX_GPIO34__FUNC_I2S3_DO (MTK_PIN_NO(34) | 2) +-#define PINMUX_GPIO34__FUNC_I2S2_DI2 (MTK_PIN_NO(34) | 3) +-#define PINMUX_GPIO34__FUNC_DPI_D4 (MTK_PIN_NO(34) | 4) +-#define PINMUX_GPIO34__FUNC_AGPS_SYNC (MTK_PIN_NO(34) | 5) +-#define PINMUX_GPIO34__FUNC_CONN_MCU_TCK (MTK_PIN_NO(34) | 6) +- +-#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +-#define PINMUX_GPIO35__FUNC_TDM_LRCK (MTK_PIN_NO(35) | 1) +-#define PINMUX_GPIO35__FUNC_I2S1_LRCK (MTK_PIN_NO(35) | 2) +-#define PINMUX_GPIO35__FUNC_I2S5_LRCK (MTK_PIN_NO(35) | 3) +-#define PINMUX_GPIO35__FUNC_DPI_D5 (MTK_PIN_NO(35) | 4) +-#define PINMUX_GPIO35__FUNC_SPI5_A_MO (MTK_PIN_NO(35) | 5) +-#define PINMUX_GPIO35__FUNC_IO_JTAG_TDI (MTK_PIN_NO(35) | 6) +-#define PINMUX_GPIO35__FUNC_PWM_2 (MTK_PIN_NO(35) | 7) +- +-#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +-#define PINMUX_GPIO36__FUNC_TDM_BCK (MTK_PIN_NO(36) | 1) +-#define PINMUX_GPIO36__FUNC_I2S1_BCK (MTK_PIN_NO(36) | 2) +-#define PINMUX_GPIO36__FUNC_I2S5_BCK (MTK_PIN_NO(36) | 3) +-#define PINMUX_GPIO36__FUNC_DPI_D6 (MTK_PIN_NO(36) | 4) +-#define PINMUX_GPIO36__FUNC_SPI5_A_CSB (MTK_PIN_NO(36) | 5) +-#define PINMUX_GPIO36__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(36) | 6) +-#define PINMUX_GPIO36__FUNC_SRCLKENAI1 (MTK_PIN_NO(36) | 7) +- +-#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +-#define PINMUX_GPIO37__FUNC_TDM_MCK (MTK_PIN_NO(37) | 1) +-#define PINMUX_GPIO37__FUNC_I2S1_MCK (MTK_PIN_NO(37) | 2) +-#define PINMUX_GPIO37__FUNC_I2S5_MCK (MTK_PIN_NO(37) | 3) +-#define PINMUX_GPIO37__FUNC_DPI_D7 (MTK_PIN_NO(37) | 4) +-#define PINMUX_GPIO37__FUNC_SPI5_A_MI (MTK_PIN_NO(37) | 5) +-#define PINMUX_GPIO37__FUNC_IO_JTAG_TCK (MTK_PIN_NO(37) | 6) +-#define PINMUX_GPIO37__FUNC_SRCLKENAI0 (MTK_PIN_NO(37) | 7) +- +-#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +-#define PINMUX_GPIO38__FUNC_TDM_DATA0 (MTK_PIN_NO(38) | 1) +-#define PINMUX_GPIO38__FUNC_I2S2_DI (MTK_PIN_NO(38) | 2) +-#define PINMUX_GPIO38__FUNC_I2S5_DO (MTK_PIN_NO(38) | 3) +-#define PINMUX_GPIO38__FUNC_DPI_D8 (MTK_PIN_NO(38) | 4) +-#define PINMUX_GPIO38__FUNC_SPI5_A_CLK (MTK_PIN_NO(38) | 5) +-#define PINMUX_GPIO38__FUNC_IO_JTAG_TDO (MTK_PIN_NO(38) | 6) +-#define PINMUX_GPIO38__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(38) | 7) +- +-#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +-#define PINMUX_GPIO39__FUNC_TDM_DATA1 (MTK_PIN_NO(39) | 1) +-#define PINMUX_GPIO39__FUNC_I2S1_DO (MTK_PIN_NO(39) | 2) +-#define PINMUX_GPIO39__FUNC_I2S2_DI2 (MTK_PIN_NO(39) | 3) +-#define PINMUX_GPIO39__FUNC_DPI_D9 (MTK_PIN_NO(39) | 4) +-#define PINMUX_GPIO39__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(39) | 5) +-#define PINMUX_GPIO39__FUNC_IO_JTAG_TMS (MTK_PIN_NO(39) | 6) +-#define PINMUX_GPIO39__FUNC_IDDIG (MTK_PIN_NO(39) | 7) +- +-#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +-#define PINMUX_GPIO40__FUNC_TDM_DATA2 (MTK_PIN_NO(40) | 1) +-#define PINMUX_GPIO40__FUNC_SCL9 (MTK_PIN_NO(40) | 2) +-#define PINMUX_GPIO40__FUNC_PWM_3 (MTK_PIN_NO(40) | 3) +-#define PINMUX_GPIO40__FUNC_DPI_D10 (MTK_PIN_NO(40) | 4) +-#define PINMUX_GPIO40__FUNC_SRCLKENAI0 (MTK_PIN_NO(40) | 5) +-#define PINMUX_GPIO40__FUNC_DAP_MD32_SWD (MTK_PIN_NO(40) | 6) +-#define PINMUX_GPIO40__FUNC_USB_DRVVBUS (MTK_PIN_NO(40) | 7) +- +-#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +-#define PINMUX_GPIO41__FUNC_TDM_DATA3 (MTK_PIN_NO(41) | 1) +-#define PINMUX_GPIO41__FUNC_SDA9 (MTK_PIN_NO(41) | 2) +-#define PINMUX_GPIO41__FUNC_PWM_1 (MTK_PIN_NO(41) | 3) +-#define PINMUX_GPIO41__FUNC_DPI_D11 (MTK_PIN_NO(41) | 4) +-#define PINMUX_GPIO41__FUNC_CLKM1 (MTK_PIN_NO(41) | 5) +-#define PINMUX_GPIO41__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(41) | 6) +- +-#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +-#define PINMUX_GPIO42__FUNC_DISP_PWM (MTK_PIN_NO(42) | 1) +- +-#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +-#define PINMUX_GPIO43__FUNC_DSI_TE (MTK_PIN_NO(43) | 1) +- +-#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +-#define PINMUX_GPIO44__FUNC_LCM_RST (MTK_PIN_NO(44) | 1) +- +-#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +-#define PINMUX_GPIO45__FUNC_SCL6 (MTK_PIN_NO(45) | 1) +-#define PINMUX_GPIO45__FUNC_SCP_SCL0 (MTK_PIN_NO(45) | 2) +-#define PINMUX_GPIO45__FUNC_SCP_SCL1 (MTK_PIN_NO(45) | 3) +-#define PINMUX_GPIO45__FUNC_SCL_6306 (MTK_PIN_NO(45) | 4) +- +-#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +-#define PINMUX_GPIO46__FUNC_SDA6 (MTK_PIN_NO(46) | 1) +-#define PINMUX_GPIO46__FUNC_SCP_SDA0 (MTK_PIN_NO(46) | 2) +-#define PINMUX_GPIO46__FUNC_SCP_SDA1 (MTK_PIN_NO(46) | 3) +-#define PINMUX_GPIO46__FUNC_SDA_6306 (MTK_PIN_NO(46) | 4) +- +-#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +-#define PINMUX_GPIO47__FUNC_SPI1_A_MI (MTK_PIN_NO(47) | 1) +-#define PINMUX_GPIO47__FUNC_SCP_SPI1_A_MI (MTK_PIN_NO(47) | 2) +-#define PINMUX_GPIO47__FUNC_KPCOL2 (MTK_PIN_NO(47) | 3) +-#define PINMUX_GPIO47__FUNC_MD_URXD0 (MTK_PIN_NO(47) | 4) +-#define PINMUX_GPIO47__FUNC_CONN_UART0_RXD (MTK_PIN_NO(47) | 5) +-#define PINMUX_GPIO47__FUNC_SSPM_URXD_AO (MTK_PIN_NO(47) | 6) +-#define PINMUX_GPIO47__FUNC_DBG_MON_B32 (MTK_PIN_NO(47) | 7) +- +-#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +-#define PINMUX_GPIO48__FUNC_SPI1_A_CSB (MTK_PIN_NO(48) | 1) +-#define PINMUX_GPIO48__FUNC_SCP_SPI1_A_CS (MTK_PIN_NO(48) | 2) +-#define PINMUX_GPIO48__FUNC_KPROW2 (MTK_PIN_NO(48) | 3) +-#define PINMUX_GPIO48__FUNC_MD_UTXD0 (MTK_PIN_NO(48) | 4) +-#define PINMUX_GPIO48__FUNC_CONN_UART0_TXD (MTK_PIN_NO(48) | 5) +-#define PINMUX_GPIO48__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(48) | 6) +-#define PINMUX_GPIO48__FUNC_DBG_MON_B31 (MTK_PIN_NO(48) | 7) +- +-#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +-#define PINMUX_GPIO49__FUNC_SPI1_A_MO (MTK_PIN_NO(49) | 1) +-#define PINMUX_GPIO49__FUNC_SCP_SPI1_A_MO (MTK_PIN_NO(49) | 2) +-#define PINMUX_GPIO49__FUNC_UCTS0 (MTK_PIN_NO(49) | 3) +-#define PINMUX_GPIO49__FUNC_MD_URXD1 (MTK_PIN_NO(49) | 4) +-#define PINMUX_GPIO49__FUNC_PWM_1 (MTK_PIN_NO(49) | 5) +-#define PINMUX_GPIO49__FUNC_TP_URXD2_AO (MTK_PIN_NO(49) | 6) +-#define PINMUX_GPIO49__FUNC_DBG_MON_B30 (MTK_PIN_NO(49) | 7) +- +-#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +-#define PINMUX_GPIO50__FUNC_SPI1_A_CLK (MTK_PIN_NO(50) | 1) +-#define PINMUX_GPIO50__FUNC_SCP_SPI1_A_CK (MTK_PIN_NO(50) | 2) +-#define PINMUX_GPIO50__FUNC_URTS0 (MTK_PIN_NO(50) | 3) +-#define PINMUX_GPIO50__FUNC_MD_UTXD1 (MTK_PIN_NO(50) | 4) +-#define PINMUX_GPIO50__FUNC_WIFI_TXD (MTK_PIN_NO(50) | 5) +-#define PINMUX_GPIO50__FUNC_TP_UTXD2_AO (MTK_PIN_NO(50) | 6) +-#define PINMUX_GPIO50__FUNC_DBG_MON_B29 (MTK_PIN_NO(50) | 7) +- +-#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +-#define PINMUX_GPIO51__FUNC_SCL0 (MTK_PIN_NO(51) | 1) +- +-#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +-#define PINMUX_GPIO52__FUNC_SDA0 (MTK_PIN_NO(52) | 1) +- +-#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +-#define PINMUX_GPIO53__FUNC_URXD0 (MTK_PIN_NO(53) | 1) +-#define PINMUX_GPIO53__FUNC_UTXD0 (MTK_PIN_NO(53) | 2) +-#define PINMUX_GPIO53__FUNC_MD_URXD0 (MTK_PIN_NO(53) | 3) +-#define PINMUX_GPIO53__FUNC_MD_URXD1 (MTK_PIN_NO(53) | 4) +-#define PINMUX_GPIO53__FUNC_SSPM_URXD_AO (MTK_PIN_NO(53) | 5) +-#define PINMUX_GPIO53__FUNC_CONN_UART0_RXD (MTK_PIN_NO(53) | 7) +- +-#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +-#define PINMUX_GPIO54__FUNC_UTXD0 (MTK_PIN_NO(54) | 1) +-#define PINMUX_GPIO54__FUNC_URXD0 (MTK_PIN_NO(54) | 2) +-#define PINMUX_GPIO54__FUNC_MD_UTXD0 (MTK_PIN_NO(54) | 3) +-#define PINMUX_GPIO54__FUNC_MD_UTXD1 (MTK_PIN_NO(54) | 4) +-#define PINMUX_GPIO54__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(54) | 5) +-#define PINMUX_GPIO54__FUNC_WIFI_TXD (MTK_PIN_NO(54) | 6) +-#define PINMUX_GPIO54__FUNC_CONN_UART0_TXD (MTK_PIN_NO(54) | 7) +- +-#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +-#define PINMUX_GPIO55__FUNC_SCL3 (MTK_PIN_NO(55) | 1) +-#define PINMUX_GPIO55__FUNC_SCP_SCL0 (MTK_PIN_NO(55) | 2) +-#define PINMUX_GPIO55__FUNC_SCP_SCL1 (MTK_PIN_NO(55) | 3) +-#define PINMUX_GPIO55__FUNC_SCL_6306 (MTK_PIN_NO(55) | 4) +- +-#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +-#define PINMUX_GPIO56__FUNC_SDA3 (MTK_PIN_NO(56) | 1) +-#define PINMUX_GPIO56__FUNC_SCP_SDA0 (MTK_PIN_NO(56) | 2) +-#define PINMUX_GPIO56__FUNC_SCP_SDA1 (MTK_PIN_NO(56) | 3) +-#define PINMUX_GPIO56__FUNC_SDA_6306 (MTK_PIN_NO(56) | 4) +- +-#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +-#define PINMUX_GPIO57__FUNC_KPROW1 (MTK_PIN_NO(57) | 1) +-#define PINMUX_GPIO57__FUNC_PWM_1 (MTK_PIN_NO(57) | 2) +-#define PINMUX_GPIO57__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(57) | 3) +-#define PINMUX_GPIO57__FUNC_CLKM1 (MTK_PIN_NO(57) | 4) +-#define PINMUX_GPIO57__FUNC_IDDIG (MTK_PIN_NO(57) | 5) +-#define PINMUX_GPIO57__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(57) | 6) +-#define PINMUX_GPIO57__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(57) | 7) +- +-#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +-#define PINMUX_GPIO58__FUNC_KPROW0 (MTK_PIN_NO(58) | 1) +-#define PINMUX_GPIO58__FUNC_DBG_MON_B28 (MTK_PIN_NO(58) | 7) +- +-#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +-#define PINMUX_GPIO59__FUNC_KPCOL0 (MTK_PIN_NO(59) | 1) +-#define PINMUX_GPIO59__FUNC_DBG_MON_B27 (MTK_PIN_NO(59) | 7) +- +-#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +-#define PINMUX_GPIO60__FUNC_KPCOL1 (MTK_PIN_NO(60) | 1) +-#define PINMUX_GPIO60__FUNC_PWM_2 (MTK_PIN_NO(60) | 2) +-#define PINMUX_GPIO60__FUNC_UCTS1 (MTK_PIN_NO(60) | 3) +-#define PINMUX_GPIO60__FUNC_CLKM2 (MTK_PIN_NO(60) | 4) +-#define PINMUX_GPIO60__FUNC_USB_DRVVBUS (MTK_PIN_NO(60) | 5) +-#define PINMUX_GPIO60__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(60) | 7) +- +-#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +-#define PINMUX_GPIO61__FUNC_SCL1 (MTK_PIN_NO(61) | 1) +-#define PINMUX_GPIO61__FUNC_SCP_SCL0 (MTK_PIN_NO(61) | 2) +-#define PINMUX_GPIO61__FUNC_SCP_SCL1 (MTK_PIN_NO(61) | 3) +- +-#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +-#define PINMUX_GPIO62__FUNC_SDA1 (MTK_PIN_NO(62) | 1) +-#define PINMUX_GPIO62__FUNC_SCP_SDA0 (MTK_PIN_NO(62) | 2) +-#define PINMUX_GPIO62__FUNC_SCP_SDA1 (MTK_PIN_NO(62) | 3) +- +-#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +-#define PINMUX_GPIO63__FUNC_SPI2_MI (MTK_PIN_NO(63) | 1) +-#define PINMUX_GPIO63__FUNC_SCP_SPI2_MI (MTK_PIN_NO(63) | 2) +-#define PINMUX_GPIO63__FUNC_KPCOL2 (MTK_PIN_NO(63) | 3) +-#define PINMUX_GPIO63__FUNC_MRG_DI (MTK_PIN_NO(63) | 4) +-#define PINMUX_GPIO63__FUNC_MD_URXD0 (MTK_PIN_NO(63) | 5) +-#define PINMUX_GPIO63__FUNC_CONN_UART0_RXD (MTK_PIN_NO(63) | 6) +-#define PINMUX_GPIO63__FUNC_DBG_MON_B26 (MTK_PIN_NO(63) | 7) +- +-#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +-#define PINMUX_GPIO64__FUNC_SPI2_CSB (MTK_PIN_NO(64) | 1) +-#define PINMUX_GPIO64__FUNC_SCP_SPI2_CS (MTK_PIN_NO(64) | 2) +-#define PINMUX_GPIO64__FUNC_KPROW2 (MTK_PIN_NO(64) | 3) +-#define PINMUX_GPIO64__FUNC_MRG_SYNC (MTK_PIN_NO(64) | 4) +-#define PINMUX_GPIO64__FUNC_MD_UTXD0 (MTK_PIN_NO(64) | 5) +-#define PINMUX_GPIO64__FUNC_CONN_UART0_TXD (MTK_PIN_NO(64) | 6) +-#define PINMUX_GPIO64__FUNC_DBG_MON_B25 (MTK_PIN_NO(64) | 7) +- +-#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +-#define PINMUX_GPIO65__FUNC_SPI2_MO (MTK_PIN_NO(65) | 1) +-#define PINMUX_GPIO65__FUNC_SCP_SPI2_MO (MTK_PIN_NO(65) | 2) +-#define PINMUX_GPIO65__FUNC_SCP_SDA1 (MTK_PIN_NO(65) | 3) +-#define PINMUX_GPIO65__FUNC_MRG_DO (MTK_PIN_NO(65) | 4) +-#define PINMUX_GPIO65__FUNC_MD_URXD1 (MTK_PIN_NO(65) | 5) +-#define PINMUX_GPIO65__FUNC_PWM_3 (MTK_PIN_NO(65) | 6) +- +-#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +-#define PINMUX_GPIO66__FUNC_SPI2_CLK (MTK_PIN_NO(66) | 1) +-#define PINMUX_GPIO66__FUNC_SCP_SPI2_CK (MTK_PIN_NO(66) | 2) +-#define PINMUX_GPIO66__FUNC_SCP_SCL1 (MTK_PIN_NO(66) | 3) +-#define PINMUX_GPIO66__FUNC_MRG_CLK (MTK_PIN_NO(66) | 4) +-#define PINMUX_GPIO66__FUNC_MD_UTXD1 (MTK_PIN_NO(66) | 5) +-#define PINMUX_GPIO66__FUNC_WIFI_TXD (MTK_PIN_NO(66) | 6) +- +-#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +-#define PINMUX_GPIO67__FUNC_I2S3_LRCK (MTK_PIN_NO(67) | 1) +-#define PINMUX_GPIO67__FUNC_I2S1_LRCK (MTK_PIN_NO(67) | 2) +-#define PINMUX_GPIO67__FUNC_URXD1 (MTK_PIN_NO(67) | 3) +-#define PINMUX_GPIO67__FUNC_PCM0_SYNC (MTK_PIN_NO(67) | 4) +-#define PINMUX_GPIO67__FUNC_I2S5_LRCK (MTK_PIN_NO(67) | 5) +-#define PINMUX_GPIO67__FUNC_ANT_SEL9 (MTK_PIN_NO(67) | 6) +-#define PINMUX_GPIO67__FUNC_DBG_MON_B10 (MTK_PIN_NO(67) | 7) +- +-#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +-#define PINMUX_GPIO68__FUNC_I2S3_DO (MTK_PIN_NO(68) | 1) +-#define PINMUX_GPIO68__FUNC_I2S1_DO (MTK_PIN_NO(68) | 2) +-#define PINMUX_GPIO68__FUNC_UTXD1 (MTK_PIN_NO(68) | 3) +-#define PINMUX_GPIO68__FUNC_PCM0_DO (MTK_PIN_NO(68) | 4) +-#define PINMUX_GPIO68__FUNC_I2S5_DO (MTK_PIN_NO(68) | 5) +-#define PINMUX_GPIO68__FUNC_ANT_SEL10 (MTK_PIN_NO(68) | 6) +-#define PINMUX_GPIO68__FUNC_DBG_MON_B9 (MTK_PIN_NO(68) | 7) +- +-#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +-#define PINMUX_GPIO69__FUNC_I2S3_MCK (MTK_PIN_NO(69) | 1) +-#define PINMUX_GPIO69__FUNC_I2S1_MCK (MTK_PIN_NO(69) | 2) +-#define PINMUX_GPIO69__FUNC_URTS1 (MTK_PIN_NO(69) | 3) +-#define PINMUX_GPIO69__FUNC_AGPS_SYNC (MTK_PIN_NO(69) | 4) +-#define PINMUX_GPIO69__FUNC_I2S5_MCK (MTK_PIN_NO(69) | 5) +-#define PINMUX_GPIO69__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(69) | 6) +-#define PINMUX_GPIO69__FUNC_DBG_MON_B8 (MTK_PIN_NO(69) | 7) +- +-#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +-#define PINMUX_GPIO70__FUNC_I2S0_DI (MTK_PIN_NO(70) | 1) +-#define PINMUX_GPIO70__FUNC_I2S2_DI (MTK_PIN_NO(70) | 2) +-#define PINMUX_GPIO70__FUNC_KPCOL2 (MTK_PIN_NO(70) | 3) +-#define PINMUX_GPIO70__FUNC_PCM0_DI (MTK_PIN_NO(70) | 4) +-#define PINMUX_GPIO70__FUNC_I2S2_DI2 (MTK_PIN_NO(70) | 5) +-#define PINMUX_GPIO70__FUNC_ANT_SEL11 (MTK_PIN_NO(70) | 6) +-#define PINMUX_GPIO70__FUNC_DBG_MON_B7 (MTK_PIN_NO(70) | 7) +- +-#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +-#define PINMUX_GPIO71__FUNC_I2S3_BCK (MTK_PIN_NO(71) | 1) +-#define PINMUX_GPIO71__FUNC_I2S1_BCK (MTK_PIN_NO(71) | 2) +-#define PINMUX_GPIO71__FUNC_KPROW2 (MTK_PIN_NO(71) | 3) +-#define PINMUX_GPIO71__FUNC_PCM0_CLK (MTK_PIN_NO(71) | 4) +-#define PINMUX_GPIO71__FUNC_I2S5_BCK (MTK_PIN_NO(71) | 5) +-#define PINMUX_GPIO71__FUNC_ANT_SEL12 (MTK_PIN_NO(71) | 6) +-#define PINMUX_GPIO71__FUNC_DBG_MON_B6 (MTK_PIN_NO(71) | 7) +- +-#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +-#define PINMUX_GPIO72__FUNC_BPI_BUS19_OLAT0 (MTK_PIN_NO(72) | 1) +-#define PINMUX_GPIO72__FUNC_CONN_BPI_BUS19_OLAT0 (MTK_PIN_NO(72) | 2) +- +-#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +-#define PINMUX_GPIO73__FUNC_BPI_BUS18_PA_VM1 (MTK_PIN_NO(73) | 1) +-#define PINMUX_GPIO73__FUNC_CONN_MIPI5_SCLK (MTK_PIN_NO(73) | 2) +-#define PINMUX_GPIO73__FUNC_MIPI5_SCLK (MTK_PIN_NO(73) | 3) +- +-#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +-#define PINMUX_GPIO74__FUNC_BPI_BUS17_PA_VM0 (MTK_PIN_NO(74) | 1) +-#define PINMUX_GPIO74__FUNC_CONN_MIPI5_SDATA (MTK_PIN_NO(74) | 2) +-#define PINMUX_GPIO74__FUNC_MIPI5_SDATA (MTK_PIN_NO(74) | 3) +- +-#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +-#define PINMUX_GPIO75__FUNC_BPI_BUS20_OLAT1 (MTK_PIN_NO(75) | 1) +-#define PINMUX_GPIO75__FUNC_CONN_BPI_BUS20_OLAT1 (MTK_PIN_NO(75) | 2) +-#define PINMUX_GPIO75__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(75) | 3) +- +-#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +-#define PINMUX_GPIO76__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(76) | 1) +- +-#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +-#define PINMUX_GPIO77__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(77) | 1) +- +-#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +-#define PINMUX_GPIO78__FUNC_BPI_BUS7 (MTK_PIN_NO(78) | 1) +-#define PINMUX_GPIO78__FUNC_DBG_MON_B24 (MTK_PIN_NO(78) | 7) +- +-#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +-#define PINMUX_GPIO79__FUNC_BPI_BUS6 (MTK_PIN_NO(79) | 1) +-#define PINMUX_GPIO79__FUNC_DBG_MON_B23 (MTK_PIN_NO(79) | 7) +- +-#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +-#define PINMUX_GPIO80__FUNC_BPI_BUS8 (MTK_PIN_NO(80) | 1) +-#define PINMUX_GPIO80__FUNC_DBG_MON_B22 (MTK_PIN_NO(80) | 7) +- +-#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +-#define PINMUX_GPIO81__FUNC_BPI_BUS9 (MTK_PIN_NO(81) | 1) +-#define PINMUX_GPIO81__FUNC_DBG_MON_B21 (MTK_PIN_NO(81) | 7) +- +-#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +-#define PINMUX_GPIO82__FUNC_BPI_BUS10 (MTK_PIN_NO(82) | 1) +-#define PINMUX_GPIO82__FUNC_DBG_MON_B20 (MTK_PIN_NO(82) | 7) +- +-#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +-#define PINMUX_GPIO83__FUNC_BPI_BUS11 (MTK_PIN_NO(83) | 1) +-#define PINMUX_GPIO83__FUNC_DBG_MON_B19 (MTK_PIN_NO(83) | 7) +- +-#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +-#define PINMUX_GPIO84__FUNC_BPI_BUS12 (MTK_PIN_NO(84) | 1) +-#define PINMUX_GPIO84__FUNC_CONN_BPI_BUS12 (MTK_PIN_NO(84) | 2) +- +-#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +-#define PINMUX_GPIO85__FUNC_BPI_BUS13 (MTK_PIN_NO(85) | 1) +-#define PINMUX_GPIO85__FUNC_CONN_BPI_BUS13 (MTK_PIN_NO(85) | 2) +- +-#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +-#define PINMUX_GPIO86__FUNC_BPI_BUS14 (MTK_PIN_NO(86) | 1) +-#define PINMUX_GPIO86__FUNC_CONN_BPI_BUS14 (MTK_PIN_NO(86) | 2) +- +-#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +-#define PINMUX_GPIO87__FUNC_BPI_BUS15 (MTK_PIN_NO(87) | 1) +-#define PINMUX_GPIO87__FUNC_CONN_BPI_BUS15 (MTK_PIN_NO(87) | 2) +- +-#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +-#define PINMUX_GPIO88__FUNC_BPI_BUS16 (MTK_PIN_NO(88) | 1) +-#define PINMUX_GPIO88__FUNC_CONN_BPI_BUS16 (MTK_PIN_NO(88) | 2) +- +-#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +-#define PINMUX_GPIO89__FUNC_BPI_BUS5 (MTK_PIN_NO(89) | 1) +-#define PINMUX_GPIO89__FUNC_DBG_MON_B18 (MTK_PIN_NO(89) | 7) +- +-#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +-#define PINMUX_GPIO90__FUNC_BPI_BUS4 (MTK_PIN_NO(90) | 1) +-#define PINMUX_GPIO90__FUNC_DBG_MON_B17 (MTK_PIN_NO(90) | 7) +- +-#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +-#define PINMUX_GPIO91__FUNC_BPI_BUS3 (MTK_PIN_NO(91) | 1) +- +-#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +-#define PINMUX_GPIO92__FUNC_BPI_BUS2 (MTK_PIN_NO(92) | 1) +-#define PINMUX_GPIO92__FUNC_DBG_MON_B16 (MTK_PIN_NO(92) | 7) +- +-#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +-#define PINMUX_GPIO93__FUNC_BPI_BUS1 (MTK_PIN_NO(93) | 1) +- +-#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +-#define PINMUX_GPIO94__FUNC_BPI_BUS0 (MTK_PIN_NO(94) | 1) +-#define PINMUX_GPIO94__FUNC_DBG_MON_B15 (MTK_PIN_NO(94) | 7) +- +-#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +-#define PINMUX_GPIO95__FUNC_MIPI0_SDATA (MTK_PIN_NO(95) | 1) +- +-#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +-#define PINMUX_GPIO96__FUNC_MIPI0_SCLK (MTK_PIN_NO(96) | 1) +- +-#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +-#define PINMUX_GPIO97__FUNC_MIPI1_SDATA (MTK_PIN_NO(97) | 1) +- +-#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +-#define PINMUX_GPIO98__FUNC_MIPI1_SCLK (MTK_PIN_NO(98) | 1) +- +-#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +-#define PINMUX_GPIO99__FUNC_MIPI2_SCLK (MTK_PIN_NO(99) | 1) +-#define PINMUX_GPIO99__FUNC_DBG_MON_B14 (MTK_PIN_NO(99) | 7) +- +-#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +-#define PINMUX_GPIO100__FUNC_MIPI2_SDATA (MTK_PIN_NO(100) | 1) +-#define PINMUX_GPIO100__FUNC_DBG_MON_B13 (MTK_PIN_NO(100) | 7) +- +-#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +-#define PINMUX_GPIO101__FUNC_MIPI3_SCLK (MTK_PIN_NO(101) | 1) +-#define PINMUX_GPIO101__FUNC_DBG_MON_B12 (MTK_PIN_NO(101) | 7) +- +-#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +-#define PINMUX_GPIO102__FUNC_MIPI3_SDATA (MTK_PIN_NO(102) | 1) +-#define PINMUX_GPIO102__FUNC_DBG_MON_B11 (MTK_PIN_NO(102) | 7) +- +-#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +-#define PINMUX_GPIO103__FUNC_MIPI4_SCLK (MTK_PIN_NO(103) | 1) +-#define PINMUX_GPIO103__FUNC_CONN_MIPI4_SCLK (MTK_PIN_NO(103) | 2) +- +-#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +-#define PINMUX_GPIO104__FUNC_MIPI4_SDATA (MTK_PIN_NO(104) | 1) +-#define PINMUX_GPIO104__FUNC_CONN_MIPI4_SDATA (MTK_PIN_NO(104) | 2) +- +-#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +-#define PINMUX_GPIO105__FUNC_BPI_BUS22_OLAT3 (MTK_PIN_NO(105) | 1) +-#define PINMUX_GPIO105__FUNC_CONN_BPI_BUS22_OLAT3 (MTK_PIN_NO(105) | 2) +- +-#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +-#define PINMUX_GPIO106__FUNC_BPI_BUS21_OLAT2 (MTK_PIN_NO(106) | 1) +-#define PINMUX_GPIO106__FUNC_CONN_BPI_BUS21_OLAT2 (MTK_PIN_NO(106) | 2) +- +-#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +-#define PINMUX_GPIO107__FUNC_BPI_BUS24_ANT1 (MTK_PIN_NO(107) | 1) +-#define PINMUX_GPIO107__FUNC_CONN_BPI_BUS24_ANT1 (MTK_PIN_NO(107) | 2) +- +-#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +-#define PINMUX_GPIO108__FUNC_BPI_BUS25_ANT2 (MTK_PIN_NO(108) | 1) +-#define PINMUX_GPIO108__FUNC_CONN_BPI_BUS25_ANT2 (MTK_PIN_NO(108) | 2) +- +-#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +-#define PINMUX_GPIO109__FUNC_BPI_BUS23_ANT0 (MTK_PIN_NO(109) | 1) +-#define PINMUX_GPIO109__FUNC_CONN_BPI_BUS23_ANT0 (MTK_PIN_NO(109) | 2) +- +-#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +-#define PINMUX_GPIO110__FUNC_SCL4 (MTK_PIN_NO(110) | 1) +- +-#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +-#define PINMUX_GPIO111__FUNC_SDA4 (MTK_PIN_NO(111) | 1) +- +-#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +-#define PINMUX_GPIO112__FUNC_SCL2 (MTK_PIN_NO(112) | 1) +- +-#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +-#define PINMUX_GPIO113__FUNC_SDA2 (MTK_PIN_NO(113) | 1) +- +-#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +-#define PINMUX_GPIO114__FUNC_CLKM0 (MTK_PIN_NO(114) | 1) +-#define PINMUX_GPIO114__FUNC_SPI3_MI (MTK_PIN_NO(114) | 2) +-#define PINMUX_GPIO114__FUNC_DBG_MON_B5 (MTK_PIN_NO(114) | 7) +- +-#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +-#define PINMUX_GPIO115__FUNC_CLKM1 (MTK_PIN_NO(115) | 1) +-#define PINMUX_GPIO115__FUNC_SPI3_CSB (MTK_PIN_NO(115) | 2) +-#define PINMUX_GPIO115__FUNC_DBG_MON_B4 (MTK_PIN_NO(115) | 7) +- +-#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +-#define PINMUX_GPIO116__FUNC_CMMCLK0 (MTK_PIN_NO(116) | 1) +-#define PINMUX_GPIO116__FUNC_DBG_MON_B3 (MTK_PIN_NO(116) | 7) +- +-#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +-#define PINMUX_GPIO117__FUNC_CMMCLK1 (MTK_PIN_NO(117) | 1) +-#define PINMUX_GPIO117__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(117) | 2) +-#define PINMUX_GPIO117__FUNC_DBG_MON_B2 (MTK_PIN_NO(117) | 7) +- +-#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +-#define PINMUX_GPIO118__FUNC_CLKM2 (MTK_PIN_NO(118) | 1) +-#define PINMUX_GPIO118__FUNC_SPI3_MO (MTK_PIN_NO(118) | 2) +-#define PINMUX_GPIO118__FUNC_DBG_MON_B1 (MTK_PIN_NO(118) | 7) +- +-#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +-#define PINMUX_GPIO119__FUNC_CLKM3 (MTK_PIN_NO(119) | 1) +-#define PINMUX_GPIO119__FUNC_SPI3_CLK (MTK_PIN_NO(119) | 2) +-#define PINMUX_GPIO119__FUNC_DBG_MON_B0 (MTK_PIN_NO(119) | 7) +- +-#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +-#define PINMUX_GPIO120__FUNC_CMMCLK2 (MTK_PIN_NO(120) | 1) +-#define PINMUX_GPIO120__FUNC_CLKM2 (MTK_PIN_NO(120) | 2) +-#define PINMUX_GPIO120__FUNC_ANT_SEL12 (MTK_PIN_NO(120) | 6) +-#define PINMUX_GPIO120__FUNC_TP_UCTS2_AO (MTK_PIN_NO(120) | 7) +- +-#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +-#define PINMUX_GPIO121__FUNC_CMMCLK3 (MTK_PIN_NO(121) | 1) +-#define PINMUX_GPIO121__FUNC_CLKM3 (MTK_PIN_NO(121) | 2) +-#define PINMUX_GPIO121__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(121) | 3) +-#define PINMUX_GPIO121__FUNC_ANT_SEL11 (MTK_PIN_NO(121) | 6) +-#define PINMUX_GPIO121__FUNC_TP_URTS2_AO (MTK_PIN_NO(121) | 7) +- +-#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +-#define PINMUX_GPIO122__FUNC_CMVREF1 (MTK_PIN_NO(122) | 1) +-#define PINMUX_GPIO122__FUNC_PCM0_SYNC (MTK_PIN_NO(122) | 2) +-#define PINMUX_GPIO122__FUNC_SRCLKENAI1 (MTK_PIN_NO(122) | 3) +-#define PINMUX_GPIO122__FUNC_AGPS_SYNC (MTK_PIN_NO(122) | 4) +-#define PINMUX_GPIO122__FUNC_PWM_1 (MTK_PIN_NO(122) | 5) +-#define PINMUX_GPIO122__FUNC_ANT_SEL9 (MTK_PIN_NO(122) | 6) +-#define PINMUX_GPIO122__FUNC_TP_UCTS1_AO (MTK_PIN_NO(122) | 7) +- +-#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +-#define PINMUX_GPIO123__FUNC_PCM0_DI (MTK_PIN_NO(123) | 2) +-#define PINMUX_GPIO123__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(123) | 3) +-#define PINMUX_GPIO123__FUNC_VPU_UDI_NTRST (MTK_PIN_NO(123) | 4) +-#define PINMUX_GPIO123__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(123) | 5) +-#define PINMUX_GPIO123__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(123) | 6) +- +-#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +-#define PINMUX_GPIO124__FUNC_CMVREF2 (MTK_PIN_NO(124) | 1) +-#define PINMUX_GPIO124__FUNC_PCM0_CLK (MTK_PIN_NO(124) | 2) +-#define PINMUX_GPIO124__FUNC_MD_INT0 (MTK_PIN_NO(124) | 3) +-#define PINMUX_GPIO124__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(124) | 4) +-#define PINMUX_GPIO124__FUNC_PWM_2 (MTK_PIN_NO(124) | 5) +-#define PINMUX_GPIO124__FUNC_ANT_SEL10 (MTK_PIN_NO(124) | 6) +-#define PINMUX_GPIO124__FUNC_TP_URTS1_AO (MTK_PIN_NO(124) | 7) +- +-#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +-#define PINMUX_GPIO125__FUNC_CMVREF3 (MTK_PIN_NO(125) | 1) +-#define PINMUX_GPIO125__FUNC_PCM0_DO (MTK_PIN_NO(125) | 2) +-#define PINMUX_GPIO125__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(125) | 3) +-#define PINMUX_GPIO125__FUNC_VPU_UDI_TMS (MTK_PIN_NO(125) | 4) +-#define PINMUX_GPIO125__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(125) | 5) +-#define PINMUX_GPIO125__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(125) | 6) +- +-#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +-#define PINMUX_GPIO126__FUNC_CMVREF4 (MTK_PIN_NO(126) | 1) +-#define PINMUX_GPIO126__FUNC_CMFLASH0 (MTK_PIN_NO(126) | 2) +-#define PINMUX_GPIO126__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(126) | 6) +- +-#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +-#define PINMUX_GPIO127__FUNC_CMVREF0 (MTK_PIN_NO(127) | 1) +-#define PINMUX_GPIO127__FUNC_CMFLASH1 (MTK_PIN_NO(127) | 2) +-#define PINMUX_GPIO127__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(127) | 6) +- +-#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +-#define PINMUX_GPIO128__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(128) | 1) +-#define PINMUX_GPIO128__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(128) | 2) +-#define PINMUX_GPIO128__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(128) | 3) +-#define PINMUX_GPIO128__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(128) | 4) +-#define PINMUX_GPIO128__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(128) | 5) +-#define PINMUX_GPIO128__FUNC_LVTS_FOUT (MTK_PIN_NO(128) | 6) +-#define PINMUX_GPIO128__FUNC_DBG_MON_A3 (MTK_PIN_NO(128) | 7) +- +-#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +-#define PINMUX_GPIO129__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(129) | 1) +-#define PINMUX_GPIO129__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(129) | 2) +-#define PINMUX_GPIO129__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(129) | 3) +-#define PINMUX_GPIO129__FUNC_CONN_DSP_JCK (MTK_PIN_NO(129) | 4) +-#define PINMUX_GPIO129__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(129) | 5) +-#define PINMUX_GPIO129__FUNC_LVTS_SDO (MTK_PIN_NO(129) | 6) +-#define PINMUX_GPIO129__FUNC_DBG_MON_A4 (MTK_PIN_NO(129) | 7) +- +-#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +-#define PINMUX_GPIO130__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(130) | 1) +-#define PINMUX_GPIO130__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(130) | 2) +-#define PINMUX_GPIO130__FUNC_LVTS_26M (MTK_PIN_NO(130) | 6) +-#define PINMUX_GPIO130__FUNC_DBG_MON_A5 (MTK_PIN_NO(130) | 7) +- +-#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +-#define PINMUX_GPIO131__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(131) | 1) +-#define PINMUX_GPIO131__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(131) | 2) +-#define PINMUX_GPIO131__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(131) | 3) +-#define PINMUX_GPIO131__FUNC_CONN_DSP_JDI (MTK_PIN_NO(131) | 4) +-#define PINMUX_GPIO131__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(131) | 5) +-#define PINMUX_GPIO131__FUNC_LVTS_SCK (MTK_PIN_NO(131) | 6) +-#define PINMUX_GPIO131__FUNC_DBG_MON_A0 (MTK_PIN_NO(131) | 7) +- +-#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +-#define PINMUX_GPIO132__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(132) | 1) +-#define PINMUX_GPIO132__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(132) | 2) +-#define PINMUX_GPIO132__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(132) | 3) +-#define PINMUX_GPIO132__FUNC_CONN_DSP_JMS (MTK_PIN_NO(132) | 4) +-#define PINMUX_GPIO132__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(132) | 5) +-#define PINMUX_GPIO132__FUNC_LVTS_SDI (MTK_PIN_NO(132) | 6) +-#define PINMUX_GPIO132__FUNC_DBG_MON_A1 (MTK_PIN_NO(132) | 7) +- +-#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +-#define PINMUX_GPIO133__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(133) | 1) +-#define PINMUX_GPIO133__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(133) | 2) +-#define PINMUX_GPIO133__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(133) | 3) +-#define PINMUX_GPIO133__FUNC_CONN_DSP_JDO (MTK_PIN_NO(133) | 4) +-#define PINMUX_GPIO133__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(133) | 5) +-#define PINMUX_GPIO133__FUNC_LVTS_SCF (MTK_PIN_NO(133) | 6) +-#define PINMUX_GPIO133__FUNC_DBG_MON_A2 (MTK_PIN_NO(133) | 7) +- +-#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +-#define PINMUX_GPIO134__FUNC_MSDC1_CLK (MTK_PIN_NO(134) | 1) +-#define PINMUX_GPIO134__FUNC_PCM1_CLK (MTK_PIN_NO(134) | 2) +-#define PINMUX_GPIO134__FUNC_SPI5_B_MI (MTK_PIN_NO(134) | 3) +-#define PINMUX_GPIO134__FUNC_UDI_TCK (MTK_PIN_NO(134) | 4) +-#define PINMUX_GPIO134__FUNC_CONN_DSP_JCK (MTK_PIN_NO(134) | 5) +-#define PINMUX_GPIO134__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(134) | 6) +-#define PINMUX_GPIO134__FUNC_JTCK_SEL3 (MTK_PIN_NO(134) | 7) +- +-#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +-#define PINMUX_GPIO135__FUNC_MSDC1_CMD (MTK_PIN_NO(135) | 1) +-#define PINMUX_GPIO135__FUNC_PCM1_SYNC (MTK_PIN_NO(135) | 2) +-#define PINMUX_GPIO135__FUNC_SPI5_B_CSB (MTK_PIN_NO(135) | 3) +-#define PINMUX_GPIO135__FUNC_UDI_TMS (MTK_PIN_NO(135) | 4) +-#define PINMUX_GPIO135__FUNC_CONN_DSP_JMS (MTK_PIN_NO(135) | 5) +-#define PINMUX_GPIO135__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(135) | 6) +-#define PINMUX_GPIO135__FUNC_JTMS_SEL3 (MTK_PIN_NO(135) | 7) +- +-#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +-#define PINMUX_GPIO136__FUNC_MSDC1_DAT3 (MTK_PIN_NO(136) | 1) +-#define PINMUX_GPIO136__FUNC_PCM1_DI (MTK_PIN_NO(136) | 2) +-#define PINMUX_GPIO136__FUNC_SPI5_B_MO (MTK_PIN_NO(136) | 3) +-#define PINMUX_GPIO136__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(136) | 4) +-#define PINMUX_GPIO136__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(136) | 5) +-#define PINMUX_GPIO136__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(136) | 6) +- +-#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +-#define PINMUX_GPIO137__FUNC_MSDC1_DAT0 (MTK_PIN_NO(137) | 1) +-#define PINMUX_GPIO137__FUNC_PCM1_DO0 (MTK_PIN_NO(137) | 2) +-#define PINMUX_GPIO137__FUNC_SPI5_B_CLK (MTK_PIN_NO(137) | 3) +-#define PINMUX_GPIO137__FUNC_UDI_TDI (MTK_PIN_NO(137) | 4) +-#define PINMUX_GPIO137__FUNC_CONN_DSP_JDI (MTK_PIN_NO(137) | 5) +-#define PINMUX_GPIO137__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(137) | 6) +-#define PINMUX_GPIO137__FUNC_JTDI_SEL3 (MTK_PIN_NO(137) | 7) +- +-#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +-#define PINMUX_GPIO138__FUNC_MSDC1_DAT2 (MTK_PIN_NO(138) | 1) +-#define PINMUX_GPIO138__FUNC_PCM1_DO2 (MTK_PIN_NO(138) | 2) +-#define PINMUX_GPIO138__FUNC_ANT_SEL11 (MTK_PIN_NO(138) | 3) +-#define PINMUX_GPIO138__FUNC_UDI_NTRST (MTK_PIN_NO(138) | 4) +-#define PINMUX_GPIO138__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(138) | 5) +-#define PINMUX_GPIO138__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(138) | 6) +-#define PINMUX_GPIO138__FUNC_JTRSTN_SEL3 (MTK_PIN_NO(138) | 7) +- +-#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +-#define PINMUX_GPIO139__FUNC_MSDC1_DAT1 (MTK_PIN_NO(139) | 1) +-#define PINMUX_GPIO139__FUNC_PCM1_DO1 (MTK_PIN_NO(139) | 2) +-#define PINMUX_GPIO139__FUNC_ANT_SEL12 (MTK_PIN_NO(139) | 3) +-#define PINMUX_GPIO139__FUNC_UDI_TDO (MTK_PIN_NO(139) | 4) +-#define PINMUX_GPIO139__FUNC_CONN_DSP_JDO (MTK_PIN_NO(139) | 5) +-#define PINMUX_GPIO139__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(139) | 6) +-#define PINMUX_GPIO139__FUNC_JTDO_SEL3 (MTK_PIN_NO(139) | 7) +- +-#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +-#define PINMUX_GPIO140__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(140) | 1) +-#define PINMUX_GPIO140__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(140) | 2) +-#define PINMUX_GPIO140__FUNC_ADSP_URXD0 (MTK_PIN_NO(140) | 3) +-#define PINMUX_GPIO140__FUNC_SCL_6306 (MTK_PIN_NO(140) | 4) +-#define PINMUX_GPIO140__FUNC_PTA_RXD (MTK_PIN_NO(140) | 5) +-#define PINMUX_GPIO140__FUNC_SSPM_URXD_AO (MTK_PIN_NO(140) | 6) +- +-#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +-#define PINMUX_GPIO141__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(141) | 1) +-#define PINMUX_GPIO141__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(141) | 2) +-#define PINMUX_GPIO141__FUNC_ADSP_UTXD0 (MTK_PIN_NO(141) | 3) +-#define PINMUX_GPIO141__FUNC_SDA_6306 (MTK_PIN_NO(141) | 4) +-#define PINMUX_GPIO141__FUNC_PTA_TXD (MTK_PIN_NO(141) | 5) +-#define PINMUX_GPIO141__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(141) | 6) +- +-#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +-#define PINMUX_GPIO142__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(142) | 1) +-#define PINMUX_GPIO142__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(142) | 2) +- +-#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +-#define PINMUX_GPIO143__FUNC_AUD_DAT_MOSI2 (MTK_PIN_NO(143) | 1) +-#define PINMUX_GPIO143__FUNC_DBG_MON_A9 (MTK_PIN_NO(143) | 7) +- +-#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +-#define PINMUX_GPIO144__FUNC_AUD_NLE_MOSI1 (MTK_PIN_NO(144) | 1) +-#define PINMUX_GPIO144__FUNC_AUD_CLK_MISO (MTK_PIN_NO(144) | 2) +-#define PINMUX_GPIO144__FUNC_I2S2_MCK (MTK_PIN_NO(144) | 3) +-#define PINMUX_GPIO144__FUNC_UDI_TCK (MTK_PIN_NO(144) | 5) +-#define PINMUX_GPIO144__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(144) | 6) +-#define PINMUX_GPIO144__FUNC_DBG_MON_A10 (MTK_PIN_NO(144) | 7) +- +-#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +-#define PINMUX_GPIO145__FUNC_AUD_NLE_MOSI0 (MTK_PIN_NO(145) | 1) +-#define PINMUX_GPIO145__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(145) | 2) +-#define PINMUX_GPIO145__FUNC_I2S2_BCK (MTK_PIN_NO(145) | 3) +-#define PINMUX_GPIO145__FUNC_UDI_TMS (MTK_PIN_NO(145) | 5) +-#define PINMUX_GPIO145__FUNC_DBG_MON_A11 (MTK_PIN_NO(145) | 7) +- +-#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +-#define PINMUX_GPIO146__FUNC_AUD_DAT_MISO2 (MTK_PIN_NO(146) | 1) +-#define PINMUX_GPIO146__FUNC_I2S2_DI2 (MTK_PIN_NO(146) | 3) +-#define PINMUX_GPIO146__FUNC_UDI_TDO (MTK_PIN_NO(146) | 5) +-#define PINMUX_GPIO146__FUNC_DBG_MON_A14 (MTK_PIN_NO(146) | 7) +- +-#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +-#define PINMUX_GPIO147__FUNC_ANT_SEL0 (MTK_PIN_NO(147) | 1) +-#define PINMUX_GPIO147__FUNC_PWM_3 (MTK_PIN_NO(147) | 2) +- +-#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +-#define PINMUX_GPIO148__FUNC_ANT_SEL1 (MTK_PIN_NO(148) | 1) +-#define PINMUX_GPIO148__FUNC_SPI0_B_MI (MTK_PIN_NO(148) | 2) +-#define PINMUX_GPIO148__FUNC_SSPM_URXD_AO (MTK_PIN_NO(148) | 3) +-#define PINMUX_GPIO148__FUNC_TP_UCTS2_AO (MTK_PIN_NO(148) | 5) +-#define PINMUX_GPIO148__FUNC_CLKM0 (MTK_PIN_NO(148) | 6) +- +-#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +-#define PINMUX_GPIO149__FUNC_ANT_SEL2 (MTK_PIN_NO(149) | 1) +-#define PINMUX_GPIO149__FUNC_SPI0_B_CSB (MTK_PIN_NO(149) | 2) +-#define PINMUX_GPIO149__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(149) | 3) +-#define PINMUX_GPIO149__FUNC_TP_URTS2_AO (MTK_PIN_NO(149) | 5) +-#define PINMUX_GPIO149__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(149) | 6) +- +-#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +-#define PINMUX_GPIO150__FUNC_ANT_SEL3 (MTK_PIN_NO(150) | 1) +-#define PINMUX_GPIO150__FUNC_SPI0_B_MO (MTK_PIN_NO(150) | 2) +-#define PINMUX_GPIO150__FUNC_UCTS1 (MTK_PIN_NO(150) | 3) +-#define PINMUX_GPIO150__FUNC_TP_UCTS1_AO (MTK_PIN_NO(150) | 5) +-#define PINMUX_GPIO150__FUNC_IDDIG (MTK_PIN_NO(150) | 6) +-#define PINMUX_GPIO150__FUNC_SCL9 (MTK_PIN_NO(150) | 7) +- +-#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +-#define PINMUX_GPIO151__FUNC_ANT_SEL4 (MTK_PIN_NO(151) | 1) +-#define PINMUX_GPIO151__FUNC_SPI0_B_CLK (MTK_PIN_NO(151) | 2) +-#define PINMUX_GPIO151__FUNC_URTS1 (MTK_PIN_NO(151) | 3) +-#define PINMUX_GPIO151__FUNC_TP_URTS1_AO (MTK_PIN_NO(151) | 5) +-#define PINMUX_GPIO151__FUNC_USB_DRVVBUS (MTK_PIN_NO(151) | 6) +-#define PINMUX_GPIO151__FUNC_SDA9 (MTK_PIN_NO(151) | 7) +- +-#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +-#define PINMUX_GPIO152__FUNC_ANT_SEL5 (MTK_PIN_NO(152) | 1) +-#define PINMUX_GPIO152__FUNC_SPI1_B_MI (MTK_PIN_NO(152) | 2) +-#define PINMUX_GPIO152__FUNC_CLKM3 (MTK_PIN_NO(152) | 3) +-#define PINMUX_GPIO152__FUNC_TP_URXD1_AO (MTK_PIN_NO(152) | 5) +-#define PINMUX_GPIO152__FUNC_SCP_SPI1_B_MI (MTK_PIN_NO(152) | 6) +-#define PINMUX_GPIO152__FUNC_SCL8 (MTK_PIN_NO(152) | 7) +- +-#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +-#define PINMUX_GPIO153__FUNC_ANT_SEL6 (MTK_PIN_NO(153) | 1) +-#define PINMUX_GPIO153__FUNC_SPI1_B_CSB (MTK_PIN_NO(153) | 2) +-#define PINMUX_GPIO153__FUNC_SRCLKENAI0 (MTK_PIN_NO(153) | 3) +-#define PINMUX_GPIO153__FUNC_PWM_0 (MTK_PIN_NO(153) | 4) +-#define PINMUX_GPIO153__FUNC_TP_UTXD1_AO (MTK_PIN_NO(153) | 5) +-#define PINMUX_GPIO153__FUNC_SCP_SPI1_B_CS (MTK_PIN_NO(153) | 6) +-#define PINMUX_GPIO153__FUNC_SDA8 (MTK_PIN_NO(153) | 7) +- +-#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +-#define PINMUX_GPIO154__FUNC_ANT_SEL7 (MTK_PIN_NO(154) | 1) +-#define PINMUX_GPIO154__FUNC_SPI1_B_MO (MTK_PIN_NO(154) | 2) +-#define PINMUX_GPIO154__FUNC_SRCLKENAI1 (MTK_PIN_NO(154) | 3) +-#define PINMUX_GPIO154__FUNC_TP_URXD2_AO (MTK_PIN_NO(154) | 5) +-#define PINMUX_GPIO154__FUNC_SCP_SPI1_B_MO (MTK_PIN_NO(154) | 6) +- +-#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +-#define PINMUX_GPIO155__FUNC_ANT_SEL8 (MTK_PIN_NO(155) | 1) +-#define PINMUX_GPIO155__FUNC_SPI1_B_CLK (MTK_PIN_NO(155) | 2) +-#define PINMUX_GPIO155__FUNC_MD_INT0 (MTK_PIN_NO(155) | 3) +-#define PINMUX_GPIO155__FUNC_TP_UTXD2_AO (MTK_PIN_NO(155) | 5) +-#define PINMUX_GPIO155__FUNC_SCP_SPI1_B_CK (MTK_PIN_NO(155) | 6) +-#define PINMUX_GPIO155__FUNC_DBG_MON_A15 (MTK_PIN_NO(155) | 7) +- +-#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +-#define PINMUX_GPIO156__FUNC_CONN_TOP_CLK (MTK_PIN_NO(156) | 1) +-#define PINMUX_GPIO156__FUNC_AUXIF_CLK0 (MTK_PIN_NO(156) | 2) +-#define PINMUX_GPIO156__FUNC_DBG_MON_A16 (MTK_PIN_NO(156) | 7) +- +-#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +-#define PINMUX_GPIO157__FUNC_CONN_TOP_DATA (MTK_PIN_NO(157) | 1) +-#define PINMUX_GPIO157__FUNC_AUXIF_ST0 (MTK_PIN_NO(157) | 2) +-#define PINMUX_GPIO157__FUNC_DBG_MON_A17 (MTK_PIN_NO(157) | 7) +- +-#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +-#define PINMUX_GPIO158__FUNC_CONN_HRST_B (MTK_PIN_NO(158) | 1) +-#define PINMUX_GPIO158__FUNC_DBG_MON_A18 (MTK_PIN_NO(158) | 7) +- +-#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +-#define PINMUX_GPIO159__FUNC_CONN_WB_PTA (MTK_PIN_NO(159) | 1) +-#define PINMUX_GPIO159__FUNC_DBG_MON_A19 (MTK_PIN_NO(159) | 7) +- +-#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +-#define PINMUX_GPIO160__FUNC_CONN_BT_CLK (MTK_PIN_NO(160) | 1) +-#define PINMUX_GPIO160__FUNC_AUXIF_CLK1 (MTK_PIN_NO(160) | 2) +-#define PINMUX_GPIO160__FUNC_DBG_MON_A20 (MTK_PIN_NO(160) | 7) +- +-#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +-#define PINMUX_GPIO161__FUNC_CONN_BT_DATA (MTK_PIN_NO(161) | 1) +-#define PINMUX_GPIO161__FUNC_AUXIF_ST1 (MTK_PIN_NO(161) | 2) +-#define PINMUX_GPIO161__FUNC_DBG_MON_A21 (MTK_PIN_NO(161) | 7) +- +-#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +-#define PINMUX_GPIO162__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(162) | 1) +-#define PINMUX_GPIO162__FUNC_DBG_MON_A22 (MTK_PIN_NO(162) | 7) +- +-#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +-#define PINMUX_GPIO163__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(163) | 1) +-#define PINMUX_GPIO163__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(163) | 2) +-#define PINMUX_GPIO163__FUNC_DBG_MON_A23 (MTK_PIN_NO(163) | 7) +- +-#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +-#define PINMUX_GPIO164__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(164) | 1) +-#define PINMUX_GPIO164__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(164) | 2) +-#define PINMUX_GPIO164__FUNC_DBG_MON_A24 (MTK_PIN_NO(164) | 7) +- +-#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +-#define PINMUX_GPIO165__FUNC_CONN_WF_CTRL3 (MTK_PIN_NO(165) | 1) +-#define PINMUX_GPIO165__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(165) | 2) +-#define PINMUX_GPIO165__FUNC_DBG_MON_A25 (MTK_PIN_NO(165) | 7) +- +-#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +-#define PINMUX_GPIO166__FUNC_CONN_WF_CTRL4 (MTK_PIN_NO(166) | 1) +-#define PINMUX_GPIO166__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(166) | 2) +-#define PINMUX_GPIO166__FUNC_DBG_MON_A26 (MTK_PIN_NO(166) | 7) +- +-#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +-#define PINMUX_GPIO167__FUNC_MSDC0_CMD (MTK_PIN_NO(167) | 1) +- +-#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +-#define PINMUX_GPIO168__FUNC_MSDC0_DAT0 (MTK_PIN_NO(168) | 1) +- +-#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +-#define PINMUX_GPIO169__FUNC_MSDC0_DAT2 (MTK_PIN_NO(169) | 1) +- +-#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +-#define PINMUX_GPIO170__FUNC_MSDC0_DAT4 (MTK_PIN_NO(170) | 1) +- +-#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +-#define PINMUX_GPIO171__FUNC_MSDC0_DAT6 (MTK_PIN_NO(171) | 1) +- +-#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +-#define PINMUX_GPIO172__FUNC_MSDC0_DAT1 (MTK_PIN_NO(172) | 1) +- +-#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +-#define PINMUX_GPIO173__FUNC_MSDC0_DAT5 (MTK_PIN_NO(173) | 1) +- +-#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +-#define PINMUX_GPIO174__FUNC_MSDC0_DAT7 (MTK_PIN_NO(174) | 1) +- +-#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +-#define PINMUX_GPIO175__FUNC_MSDC0_DSL (MTK_PIN_NO(175) | 1) +-#define PINMUX_GPIO175__FUNC_ANT_SEL9 (MTK_PIN_NO(175) | 2) +- +-#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +-#define PINMUX_GPIO176__FUNC_MSDC0_CLK (MTK_PIN_NO(176) | 1) +-#define PINMUX_GPIO176__FUNC_ANT_SEL10 (MTK_PIN_NO(176) | 2) +- +-#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +-#define PINMUX_GPIO177__FUNC_MSDC0_DAT3 (MTK_PIN_NO(177) | 1) +- +-#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +-#define PINMUX_GPIO178__FUNC_MSDC0_RSTB (MTK_PIN_NO(178) | 1) +- +-#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +-#define PINMUX_GPIO179__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(179) | 1) +- +-#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +-#define PINMUX_GPIO180__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(180) | 1) +- +-#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +-#define PINMUX_GPIO181__FUNC_SRCLKENA0 (MTK_PIN_NO(181) | 1) +- +-#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +-#define PINMUX_GPIO182__FUNC_SRCLKENA1 (MTK_PIN_NO(182) | 1) +- +-#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +-#define PINMUX_GPIO183__FUNC_WATCHDOG (MTK_PIN_NO(183) | 1) +- +-#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +-#define PINMUX_GPIO184__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(184) | 1) +-#define PINMUX_GPIO184__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(184) | 2) +- +-#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +-#define PINMUX_GPIO185__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(185) | 1) +- +-#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +-#define PINMUX_GPIO186__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(186) | 1) +-#define PINMUX_GPIO186__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(186) | 2) +- +-#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +-#define PINMUX_GPIO187__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(187) | 1) +- +-#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +-#define PINMUX_GPIO188__FUNC_RTC32K_CK (MTK_PIN_NO(188) | 1) +- +-#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +-#define PINMUX_GPIO189__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(189) | 1) +-#define PINMUX_GPIO189__FUNC_I2S1_MCK (MTK_PIN_NO(189) | 3) +-#define PINMUX_GPIO189__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(189) | 6) +- +-#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +-#define PINMUX_GPIO190__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(190) | 1) +-#define PINMUX_GPIO190__FUNC_I2S1_BCK (MTK_PIN_NO(190) | 3) +-#define PINMUX_GPIO190__FUNC_DBG_MON_A6 (MTK_PIN_NO(190) | 7) +- +-#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +-#define PINMUX_GPIO191__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(191) | 1) +-#define PINMUX_GPIO191__FUNC_I2S1_LRCK (MTK_PIN_NO(191) | 3) +-#define PINMUX_GPIO191__FUNC_DBG_MON_A7 (MTK_PIN_NO(191) | 7) +- +-#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +-#define PINMUX_GPIO192__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(192) | 1) +-#define PINMUX_GPIO192__FUNC_I2S1_DO (MTK_PIN_NO(192) | 3) +-#define PINMUX_GPIO192__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(192) | 6) +-#define PINMUX_GPIO192__FUNC_DBG_MON_A8 (MTK_PIN_NO(192) | 7) +- +-#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +-#define PINMUX_GPIO193__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(193) | 1) +-#define PINMUX_GPIO193__FUNC_VOW_DAT_MISO (MTK_PIN_NO(193) | 2) +-#define PINMUX_GPIO193__FUNC_I2S2_LRCK (MTK_PIN_NO(193) | 3) +-#define PINMUX_GPIO193__FUNC_UDI_TDI (MTK_PIN_NO(193) | 5) +-#define PINMUX_GPIO193__FUNC_DBG_MON_A12 (MTK_PIN_NO(193) | 7) +- +-#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +-#define PINMUX_GPIO194__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(194) | 1) +-#define PINMUX_GPIO194__FUNC_VOW_CLK_MISO (MTK_PIN_NO(194) | 2) +-#define PINMUX_GPIO194__FUNC_I2S2_DI (MTK_PIN_NO(194) | 3) +-#define PINMUX_GPIO194__FUNC_UDI_NTRST (MTK_PIN_NO(194) | 5) +-#define PINMUX_GPIO194__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(194) | 6) +-#define PINMUX_GPIO194__FUNC_DBG_MON_A13 (MTK_PIN_NO(194) | 7) +- +-#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +-#define PINMUX_GPIO195__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(195) | 3) +-#define PINMUX_GPIO195__FUNC_VPU_UDI_TCK (MTK_PIN_NO(195) | 4) +-#define PINMUX_GPIO195__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(195) | 5) +-#define PINMUX_GPIO195__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(195) | 6) +- +-#define PINMUX_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +-#define PINMUX_GPIO196__FUNC_CMMCLK4 (MTK_PIN_NO(196) | 1) +-#define PINMUX_GPIO196__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(196) | 3) +-#define PINMUX_GPIO196__FUNC_VPU_UDI_TDI (MTK_PIN_NO(196) | 4) +-#define PINMUX_GPIO196__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(196) | 5) +-#define PINMUX_GPIO196__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(196) | 6) +- +-#define PINMUX_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +-#define PINMUX_GPIO197__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(197) | 3) +-#define PINMUX_GPIO197__FUNC_VPU_UDI_TDO (MTK_PIN_NO(197) | 4) +-#define PINMUX_GPIO197__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(197) | 5) +-#define PINMUX_GPIO197__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(197) | 6) +- +-#define PINMUX_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +-#define PINMUX_GPIO198__FUNC_SCL7 (MTK_PIN_NO(198) | 1) +- +-#define PINMUX_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +-#define PINMUX_GPIO199__FUNC_SDA7 (MTK_PIN_NO(199) | 1) +- +-#define PINMUX_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +-#define PINMUX_GPIO200__FUNC_URXD1 (MTK_PIN_NO(200) | 1) +-#define PINMUX_GPIO200__FUNC_ADSP_URXD0 (MTK_PIN_NO(200) | 2) +-#define PINMUX_GPIO200__FUNC_TP_URXD1_AO (MTK_PIN_NO(200) | 3) +-#define PINMUX_GPIO200__FUNC_SSPM_URXD_AO (MTK_PIN_NO(200) | 4) +-#define PINMUX_GPIO200__FUNC_TP_URXD2_AO (MTK_PIN_NO(200) | 5) +-#define PINMUX_GPIO200__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(200) | 6) +- +-#define PINMUX_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +-#define PINMUX_GPIO201__FUNC_UTXD1 (MTK_PIN_NO(201) | 1) +-#define PINMUX_GPIO201__FUNC_ADSP_UTXD0 (MTK_PIN_NO(201) | 2) +-#define PINMUX_GPIO201__FUNC_TP_UTXD1_AO (MTK_PIN_NO(201) | 3) +-#define PINMUX_GPIO201__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(201) | 4) +-#define PINMUX_GPIO201__FUNC_TP_UTXD2_AO (MTK_PIN_NO(201) | 5) +-#define PINMUX_GPIO201__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(201) | 6) +- +-#define PINMUX_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +-#define PINMUX_GPIO202__FUNC_PWM_3 (MTK_PIN_NO(202) | 1) +-#define PINMUX_GPIO202__FUNC_CLKM3 (MTK_PIN_NO(202) | 2) +- +-#define PINMUX_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) +- +-#define PINMUX_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) +- +-#define PINMUX_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) +- +-#define PINMUX_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) +- +-#define PINMUX_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) +- +-#define PINMUX_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) +- +-#define PINMUX_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) +- +-#endif /* __MT6779-PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt6797-pinfunc.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt6797-pinfunc.h +deleted file mode 100644 +index e9813361b27c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt6797-pinfunc.h ++++ /dev/null +@@ -1,1368 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DTS_MT6797_PINFUNC_H +-#define __DTS_MT6797_PINFUNC_H +- +-#include +- +-#define MT6797_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +-#define MT6797_GPIO0__FUNC_CSI0A_L0P_T0A (MTK_PIN_NO(0) | 1) +- +-#define MT6797_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +-#define MT6797_GPIO1__FUNC_CSI0A_L0N_T0B (MTK_PIN_NO(1) | 1) +- +-#define MT6797_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +-#define MT6797_GPIO2__FUNC_CSI0A_L1P_T0C (MTK_PIN_NO(2) | 1) +- +-#define MT6797_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +-#define MT6797_GPIO3__FUNC_CSI0A_L1N_T1A (MTK_PIN_NO(3) | 1) +- +-#define MT6797_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +-#define MT6797_GPIO4__FUNC_CSI0A_L2P_T1B (MTK_PIN_NO(4) | 1) +- +-#define MT6797_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +-#define MT6797_GPIO5__FUNC_CSI0A_L2N_T1C (MTK_PIN_NO(5) | 1) +- +-#define MT6797_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +-#define MT6797_GPIO6__FUNC_CSI0B_L0P_T0A (MTK_PIN_NO(6) | 1) +- +-#define MT6797_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +-#define MT6797_GPIO7__FUNC_CSI0B_L0N_T0B (MTK_PIN_NO(7) | 1) +- +-#define MT6797_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +-#define MT6797_GPIO8__FUNC_CSI0B_L1P_T0C (MTK_PIN_NO(8) | 1) +- +-#define MT6797_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +-#define MT6797_GPIO9__FUNC_CSI0B_L1N_T1A (MTK_PIN_NO(9) | 1) +- +-#define MT6797_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +-#define MT6797_GPIO10__FUNC_CSI1A_L0P_T0A (MTK_PIN_NO(10) | 1) +- +-#define MT6797_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +-#define MT6797_GPIO11__FUNC_CSI1A_L0N_T0B (MTK_PIN_NO(11) | 1) +- +-#define MT6797_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +-#define MT6797_GPIO12__FUNC_CSI1A_L1P_T0C (MTK_PIN_NO(12) | 1) +- +-#define MT6797_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +-#define MT6797_GPIO13__FUNC_CSI1A_L1N_T1A (MTK_PIN_NO(13) | 1) +- +-#define MT6797_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +-#define MT6797_GPIO14__FUNC_CSI1A_L2P_T1B (MTK_PIN_NO(14) | 1) +- +-#define MT6797_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +-#define MT6797_GPIO15__FUNC_CSI1A_L2N_T1C (MTK_PIN_NO(15) | 1) +- +-#define MT6797_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +-#define MT6797_GPIO16__FUNC_CSI1B_L0P_T0A (MTK_PIN_NO(16) | 1) +- +-#define MT6797_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +-#define MT6797_GPIO17__FUNC_CSI1B_L0N_T0B (MTK_PIN_NO(17) | 1) +- +-#define MT6797_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +-#define MT6797_GPIO18__FUNC_CSI1B_L1P_T0C (MTK_PIN_NO(18) | 1) +- +-#define MT6797_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +-#define MT6797_GPIO19__FUNC_CSI1B_L1N_T1A (MTK_PIN_NO(19) | 1) +- +-#define MT6797_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +-#define MT6797_GPIO20__FUNC_CSI1B_L2P_T1B (MTK_PIN_NO(20) | 1) +- +-#define MT6797_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +-#define MT6797_GPIO21__FUNC_CSI1B_L2N_T1C (MTK_PIN_NO(21) | 1) +- +-#define MT6797_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +-#define MT6797_GPIO22__FUNC_CSI2_L0P_T0A (MTK_PIN_NO(22) | 1) +- +-#define MT6797_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +-#define MT6797_GPIO23__FUNC_CSI2_L0N_T0B (MTK_PIN_NO(23) | 1) +- +-#define MT6797_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +-#define MT6797_GPIO24__FUNC_CSI2_L1P_T0C (MTK_PIN_NO(24) | 1) +- +-#define MT6797_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +-#define MT6797_GPIO25__FUNC_CSI2_L1N_T1A (MTK_PIN_NO(25) | 1) +- +-#define MT6797_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +-#define MT6797_GPIO26__FUNC_CSI2_L2P_T1B (MTK_PIN_NO(26) | 1) +- +-#define MT6797_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +-#define MT6797_GPIO27__FUNC_CSI2_L2N_T1C (MTK_PIN_NO(27) | 1) +- +-#define MT6797_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +-#define MT6797_GPIO28__FUNC_SPI5_CLK_A (MTK_PIN_NO(28) | 1) +-#define MT6797_GPIO28__FUNC_IRTX_OUT (MTK_PIN_NO(28) | 2) +-#define MT6797_GPIO28__FUNC_UDI_TDO (MTK_PIN_NO(28) | 3) +-#define MT6797_GPIO28__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(28) | 4) +-#define MT6797_GPIO28__FUNC_CONN_MCU_TDO (MTK_PIN_NO(28) | 5) +-#define MT6797_GPIO28__FUNC_PWM_A (MTK_PIN_NO(28) | 6) +-#define MT6797_GPIO28__FUNC_C2K_DM_OTDO (MTK_PIN_NO(28) | 7) +- +-#define MT6797_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +-#define MT6797_GPIO29__FUNC_SPI5_MI_A (MTK_PIN_NO(29) | 1) +-#define MT6797_GPIO29__FUNC_DAP_SIB1_SWD (MTK_PIN_NO(29) | 2) +-#define MT6797_GPIO29__FUNC_UDI_TMS (MTK_PIN_NO(29) | 3) +-#define MT6797_GPIO29__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(29) | 4) +-#define MT6797_GPIO29__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 5) +-#define MT6797_GPIO29__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(29) | 6) +-#define MT6797_GPIO29__FUNC_C2K_DM_OTMS (MTK_PIN_NO(29) | 7) +- +-#define MT6797_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +-#define MT6797_GPIO30__FUNC_CMMCLK0 (MTK_PIN_NO(30) | 1) +-#define MT6797_GPIO30__FUNC_MD_CLKM0 (MTK_PIN_NO(30) | 7) +- +-#define MT6797_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +-#define MT6797_GPIO31__FUNC_CMMCLK1 (MTK_PIN_NO(31) | 1) +-#define MT6797_GPIO31__FUNC_MD_CLKM1 (MTK_PIN_NO(31) | 7) +- +-#define MT6797_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +-#define MT6797_GPIO32__FUNC_SPI5_CS_A (MTK_PIN_NO(32) | 1) +-#define MT6797_GPIO32__FUNC_DAP_SIB1_SWCK (MTK_PIN_NO(32) | 2) +-#define MT6797_GPIO32__FUNC_UDI_TCK_XI (MTK_PIN_NO(32) | 3) +-#define MT6797_GPIO32__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(32) | 4) +-#define MT6797_GPIO32__FUNC_CONN_MCU_TCK (MTK_PIN_NO(32) | 5) +-#define MT6797_GPIO32__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(32) | 6) +-#define MT6797_GPIO32__FUNC_C2K_DM_OTCK (MTK_PIN_NO(32) | 7) +- +-#define MT6797_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +-#define MT6797_GPIO33__FUNC_SPI5_MO_A (MTK_PIN_NO(33) | 1) +-#define MT6797_GPIO33__FUNC_CMFLASH (MTK_PIN_NO(33) | 2) +-#define MT6797_GPIO33__FUNC_UDI_TDI (MTK_PIN_NO(33) | 3) +-#define MT6797_GPIO33__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(33) | 4) +-#define MT6797_GPIO33__FUNC_CONN_MCU_TDI (MTK_PIN_NO(33) | 5) +-#define MT6797_GPIO33__FUNC_MD_URXD0 (MTK_PIN_NO(33) | 6) +-#define MT6797_GPIO33__FUNC_C2K_DM_OTDI (MTK_PIN_NO(33) | 7) +- +-#define MT6797_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +-#define MT6797_GPIO34__FUNC_CMFLASH (MTK_PIN_NO(34) | 1) +-#define MT6797_GPIO34__FUNC_CLKM0 (MTK_PIN_NO(34) | 2) +-#define MT6797_GPIO34__FUNC_UDI_NTRST (MTK_PIN_NO(34) | 3) +-#define MT6797_GPIO34__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(34) | 4) +-#define MT6797_GPIO34__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(34) | 5) +-#define MT6797_GPIO34__FUNC_MD_UTXD0 (MTK_PIN_NO(34) | 6) +-#define MT6797_GPIO34__FUNC_C2K_DM_JTINTP (MTK_PIN_NO(34) | 7) +- +-#define MT6797_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +-#define MT6797_GPIO35__FUNC_CMMCLK3 (MTK_PIN_NO(35) | 1) +-#define MT6797_GPIO35__FUNC_CLKM1 (MTK_PIN_NO(35) | 2) +-#define MT6797_GPIO35__FUNC_MD_URXD1 (MTK_PIN_NO(35) | 3) +-#define MT6797_GPIO35__FUNC_PTA_RXD (MTK_PIN_NO(35) | 4) +-#define MT6797_GPIO35__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(35) | 5) +-#define MT6797_GPIO35__FUNC_PWM_B (MTK_PIN_NO(35) | 6) +-#define MT6797_GPIO35__FUNC_PCC_PPC_IO (MTK_PIN_NO(35) | 7) +- +-#define MT6797_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +-#define MT6797_GPIO36__FUNC_CMMCLK2 (MTK_PIN_NO(36) | 1) +-#define MT6797_GPIO36__FUNC_CLKM2 (MTK_PIN_NO(36) | 2) +-#define MT6797_GPIO36__FUNC_MD_UTXD1 (MTK_PIN_NO(36) | 3) +-#define MT6797_GPIO36__FUNC_PTA_TXD (MTK_PIN_NO(36) | 4) +-#define MT6797_GPIO36__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(36) | 5) +-#define MT6797_GPIO36__FUNC_PWM_C (MTK_PIN_NO(36) | 6) +-#define MT6797_GPIO36__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(36) | 7) +- +-#define MT6797_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +-#define MT6797_GPIO37__FUNC_SCL0_0 (MTK_PIN_NO(37) | 1) +- +-#define MT6797_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +-#define MT6797_GPIO38__FUNC_SDA0_0 (MTK_PIN_NO(38) | 1) +- +-#define MT6797_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +-#define MT6797_GPIO39__FUNC_DPI_D0 (MTK_PIN_NO(39) | 1) +-#define MT6797_GPIO39__FUNC_SPI1_CLK_A (MTK_PIN_NO(39) | 2) +-#define MT6797_GPIO39__FUNC_PCM0_SYNC (MTK_PIN_NO(39) | 3) +-#define MT6797_GPIO39__FUNC_I2S0_LRCK (MTK_PIN_NO(39) | 4) +-#define MT6797_GPIO39__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(39) | 5) +-#define MT6797_GPIO39__FUNC_URXD3 (MTK_PIN_NO(39) | 6) +-#define MT6797_GPIO39__FUNC_C2K_NTRST (MTK_PIN_NO(39) | 7) +- +-#define MT6797_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +-#define MT6797_GPIO40__FUNC_DPI_D1 (MTK_PIN_NO(40) | 1) +-#define MT6797_GPIO40__FUNC_SPI1_MI_A (MTK_PIN_NO(40) | 2) +-#define MT6797_GPIO40__FUNC_PCM0_CLK (MTK_PIN_NO(40) | 3) +-#define MT6797_GPIO40__FUNC_I2S0_BCK (MTK_PIN_NO(40) | 4) +-#define MT6797_GPIO40__FUNC_CONN_MCU_TDO (MTK_PIN_NO(40) | 5) +-#define MT6797_GPIO40__FUNC_UTXD3 (MTK_PIN_NO(40) | 6) +-#define MT6797_GPIO40__FUNC_C2K_TCK (MTK_PIN_NO(40) | 7) +- +-#define MT6797_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +-#define MT6797_GPIO41__FUNC_DPI_D2 (MTK_PIN_NO(41) | 1) +-#define MT6797_GPIO41__FUNC_SPI1_CS_A (MTK_PIN_NO(41) | 2) +-#define MT6797_GPIO41__FUNC_PCM0_DO (MTK_PIN_NO(41) | 3) +-#define MT6797_GPIO41__FUNC_I2S3_DO (MTK_PIN_NO(41) | 4) +-#define MT6797_GPIO41__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(41) | 5) +-#define MT6797_GPIO41__FUNC_URTS3 (MTK_PIN_NO(41) | 6) +-#define MT6797_GPIO41__FUNC_C2K_TDI (MTK_PIN_NO(41) | 7) +- +-#define MT6797_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +-#define MT6797_GPIO42__FUNC_DPI_D3 (MTK_PIN_NO(42) | 1) +-#define MT6797_GPIO42__FUNC_SPI1_MO_A (MTK_PIN_NO(42) | 2) +-#define MT6797_GPIO42__FUNC_PCM0_DI (MTK_PIN_NO(42) | 3) +-#define MT6797_GPIO42__FUNC_I2S0_DI (MTK_PIN_NO(42) | 4) +-#define MT6797_GPIO42__FUNC_CONN_MCU_TDI (MTK_PIN_NO(42) | 5) +-#define MT6797_GPIO42__FUNC_UCTS3 (MTK_PIN_NO(42) | 6) +-#define MT6797_GPIO42__FUNC_C2K_TMS (MTK_PIN_NO(42) | 7) +- +-#define MT6797_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +-#define MT6797_GPIO43__FUNC_DPI_D4 (MTK_PIN_NO(43) | 1) +-#define MT6797_GPIO43__FUNC_SPI2_CLK_A (MTK_PIN_NO(43) | 2) +-#define MT6797_GPIO43__FUNC_PCM1_SYNC (MTK_PIN_NO(43) | 3) +-#define MT6797_GPIO43__FUNC_I2S2_LRCK (MTK_PIN_NO(43) | 4) +-#define MT6797_GPIO43__FUNC_CONN_MCU_TMS (MTK_PIN_NO(43) | 5) +-#define MT6797_GPIO43__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(43) | 6) +-#define MT6797_GPIO43__FUNC_C2K_TDO (MTK_PIN_NO(43) | 7) +- +-#define MT6797_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +-#define MT6797_GPIO44__FUNC_DPI_D5 (MTK_PIN_NO(44) | 1) +-#define MT6797_GPIO44__FUNC_SPI2_MI_A (MTK_PIN_NO(44) | 2) +-#define MT6797_GPIO44__FUNC_PCM1_CLK (MTK_PIN_NO(44) | 3) +-#define MT6797_GPIO44__FUNC_I2S2_BCK (MTK_PIN_NO(44) | 4) +-#define MT6797_GPIO44__FUNC_CONN_MCU_TCK (MTK_PIN_NO(44) | 5) +-#define MT6797_GPIO44__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(44) | 6) +-#define MT6797_GPIO44__FUNC_C2K_RTCK (MTK_PIN_NO(44) | 7) +- +-#define MT6797_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +-#define MT6797_GPIO45__FUNC_DPI_D6 (MTK_PIN_NO(45) | 1) +-#define MT6797_GPIO45__FUNC_SPI2_CS_A (MTK_PIN_NO(45) | 2) +-#define MT6797_GPIO45__FUNC_PCM1_DI (MTK_PIN_NO(45) | 3) +-#define MT6797_GPIO45__FUNC_I2S2_DI (MTK_PIN_NO(45) | 4) +-#define MT6797_GPIO45__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(45) | 5) +-#define MT6797_GPIO45__FUNC_MD_URXD0 (MTK_PIN_NO(45) | 6) +- +-#define MT6797_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +-#define MT6797_GPIO46__FUNC_DPI_D7 (MTK_PIN_NO(46) | 1) +-#define MT6797_GPIO46__FUNC_SPI2_MO_A (MTK_PIN_NO(46) | 2) +-#define MT6797_GPIO46__FUNC_PCM1_DO0 (MTK_PIN_NO(46) | 3) +-#define MT6797_GPIO46__FUNC_I2S1_DO (MTK_PIN_NO(46) | 4) +-#define MT6797_GPIO46__FUNC_ANT_SEL0 (MTK_PIN_NO(46) | 5) +-#define MT6797_GPIO46__FUNC_MD_UTXD0 (MTK_PIN_NO(46) | 6) +- +-#define MT6797_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +-#define MT6797_GPIO47__FUNC_DPI_D8 (MTK_PIN_NO(47) | 1) +-#define MT6797_GPIO47__FUNC_CLKM0 (MTK_PIN_NO(47) | 2) +-#define MT6797_GPIO47__FUNC_PCM1_DO1 (MTK_PIN_NO(47) | 3) +-#define MT6797_GPIO47__FUNC_I2S0_MCK (MTK_PIN_NO(47) | 4) +-#define MT6797_GPIO47__FUNC_ANT_SEL1 (MTK_PIN_NO(47) | 5) +-#define MT6797_GPIO47__FUNC_PTA_RXD (MTK_PIN_NO(47) | 6) +-#define MT6797_GPIO47__FUNC_C2K_URXD0 (MTK_PIN_NO(47) | 7) +- +-#define MT6797_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +-#define MT6797_GPIO48__FUNC_DPI_D9 (MTK_PIN_NO(48) | 1) +-#define MT6797_GPIO48__FUNC_CLKM1 (MTK_PIN_NO(48) | 2) +-#define MT6797_GPIO48__FUNC_CMFLASH (MTK_PIN_NO(48) | 3) +-#define MT6797_GPIO48__FUNC_I2S2_MCK (MTK_PIN_NO(48) | 4) +-#define MT6797_GPIO48__FUNC_ANT_SEL2 (MTK_PIN_NO(48) | 5) +-#define MT6797_GPIO48__FUNC_PTA_TXD (MTK_PIN_NO(48) | 6) +-#define MT6797_GPIO48__FUNC_C2K_UTXD0 (MTK_PIN_NO(48) | 7) +- +-#define MT6797_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +-#define MT6797_GPIO49__FUNC_DPI_D10 (MTK_PIN_NO(49) | 1) +-#define MT6797_GPIO49__FUNC_MD_INT1_C2K_UIM1_HOT_PLUG_IN (MTK_PIN_NO(49) | 2) +-#define MT6797_GPIO49__FUNC_PWM_C (MTK_PIN_NO(49) | 3) +-#define MT6797_GPIO49__FUNC_IRTX_OUT (MTK_PIN_NO(49) | 4) +-#define MT6797_GPIO49__FUNC_ANT_SEL3 (MTK_PIN_NO(49) | 5) +-#define MT6797_GPIO49__FUNC_MD_URXD1 (MTK_PIN_NO(49) | 6) +- +-#define MT6797_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +-#define MT6797_GPIO50__FUNC_DPI_D11 (MTK_PIN_NO(50) | 1) +-#define MT6797_GPIO50__FUNC_MD_INT2 (MTK_PIN_NO(50) | 2) +-#define MT6797_GPIO50__FUNC_PWM_D (MTK_PIN_NO(50) | 3) +-#define MT6797_GPIO50__FUNC_CLKM2 (MTK_PIN_NO(50) | 4) +-#define MT6797_GPIO50__FUNC_ANT_SEL4 (MTK_PIN_NO(50) | 5) +-#define MT6797_GPIO50__FUNC_MD_UTXD1 (MTK_PIN_NO(50) | 6) +- +-#define MT6797_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +-#define MT6797_GPIO51__FUNC_DPI_DE (MTK_PIN_NO(51) | 1) +-#define MT6797_GPIO51__FUNC_SPI4_CLK_A (MTK_PIN_NO(51) | 2) +-#define MT6797_GPIO51__FUNC_IRTX_OUT (MTK_PIN_NO(51) | 3) +-#define MT6797_GPIO51__FUNC_SCL0_1 (MTK_PIN_NO(51) | 4) +-#define MT6797_GPIO51__FUNC_ANT_SEL5 (MTK_PIN_NO(51) | 5) +-#define MT6797_GPIO51__FUNC_C2K_UTXD1 (MTK_PIN_NO(51) | 7) +- +-#define MT6797_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +-#define MT6797_GPIO52__FUNC_DPI_CK (MTK_PIN_NO(52) | 1) +-#define MT6797_GPIO52__FUNC_SPI4_MI_A (MTK_PIN_NO(52) | 2) +-#define MT6797_GPIO52__FUNC_SPI4_MO_A (MTK_PIN_NO(52) | 3) +-#define MT6797_GPIO52__FUNC_SDA0_1 (MTK_PIN_NO(52) | 4) +-#define MT6797_GPIO52__FUNC_ANT_SEL6 (MTK_PIN_NO(52) | 5) +-#define MT6797_GPIO52__FUNC_C2K_URXD1 (MTK_PIN_NO(52) | 7) +- +-#define MT6797_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +-#define MT6797_GPIO53__FUNC_DPI_HSYNC (MTK_PIN_NO(53) | 1) +-#define MT6797_GPIO53__FUNC_SPI4_CS_A (MTK_PIN_NO(53) | 2) +-#define MT6797_GPIO53__FUNC_CMFLASH (MTK_PIN_NO(53) | 3) +-#define MT6797_GPIO53__FUNC_SCL1_1 (MTK_PIN_NO(53) | 4) +-#define MT6797_GPIO53__FUNC_ANT_SEL7 (MTK_PIN_NO(53) | 5) +-#define MT6797_GPIO53__FUNC_MD_URXD2 (MTK_PIN_NO(53) | 6) +-#define MT6797_GPIO53__FUNC_PCC_PPC_IO (MTK_PIN_NO(53) | 7) +- +-#define MT6797_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +-#define MT6797_GPIO54__FUNC_DPI_VSYNC (MTK_PIN_NO(54) | 1) +-#define MT6797_GPIO54__FUNC_SPI4_MO_A (MTK_PIN_NO(54) | 2) +-#define MT6797_GPIO54__FUNC_SPI4_MI_A (MTK_PIN_NO(54) | 3) +-#define MT6797_GPIO54__FUNC_SDA1_1 (MTK_PIN_NO(54) | 4) +-#define MT6797_GPIO54__FUNC_PWM_A (MTK_PIN_NO(54) | 5) +-#define MT6797_GPIO54__FUNC_MD_UTXD2 (MTK_PIN_NO(54) | 6) +-#define MT6797_GPIO54__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(54) | 7) +- +-#define MT6797_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +-#define MT6797_GPIO55__FUNC_SCL1_0 (MTK_PIN_NO(55) | 1) +- +-#define MT6797_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +-#define MT6797_GPIO56__FUNC_SDA1_0 (MTK_PIN_NO(56) | 1) +- +-#define MT6797_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +-#define MT6797_GPIO57__FUNC_SPI0_CLK (MTK_PIN_NO(57) | 1) +-#define MT6797_GPIO57__FUNC_SCL0_2 (MTK_PIN_NO(57) | 2) +-#define MT6797_GPIO57__FUNC_PWM_B (MTK_PIN_NO(57) | 3) +-#define MT6797_GPIO57__FUNC_UTXD3 (MTK_PIN_NO(57) | 4) +-#define MT6797_GPIO57__FUNC_PCM0_SYNC (MTK_PIN_NO(57) | 5) +- +-#define MT6797_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +-#define MT6797_GPIO58__FUNC_SPI0_MI (MTK_PIN_NO(58) | 1) +-#define MT6797_GPIO58__FUNC_SPI0_MO (MTK_PIN_NO(58) | 2) +-#define MT6797_GPIO58__FUNC_SDA1_2 (MTK_PIN_NO(58) | 3) +-#define MT6797_GPIO58__FUNC_URXD3 (MTK_PIN_NO(58) | 4) +-#define MT6797_GPIO58__FUNC_PCM0_CLK (MTK_PIN_NO(58) | 5) +- +-#define MT6797_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +-#define MT6797_GPIO59__FUNC_SPI0_MO (MTK_PIN_NO(59) | 1) +-#define MT6797_GPIO59__FUNC_SPI0_MI (MTK_PIN_NO(59) | 2) +-#define MT6797_GPIO59__FUNC_PWM_C (MTK_PIN_NO(59) | 3) +-#define MT6797_GPIO59__FUNC_URTS3 (MTK_PIN_NO(59) | 4) +-#define MT6797_GPIO59__FUNC_PCM0_DO (MTK_PIN_NO(59) | 5) +- +-#define MT6797_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +-#define MT6797_GPIO60__FUNC_SPI0_CS (MTK_PIN_NO(60) | 1) +-#define MT6797_GPIO60__FUNC_SDA0_2 (MTK_PIN_NO(60) | 2) +-#define MT6797_GPIO60__FUNC_SCL1_2 (MTK_PIN_NO(60) | 3) +-#define MT6797_GPIO60__FUNC_UCTS3 (MTK_PIN_NO(60) | 4) +-#define MT6797_GPIO60__FUNC_PCM0_DI (MTK_PIN_NO(60) | 5) +- +-#define MT6797_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +-#define MT6797_GPIO61__FUNC_EINT0 (MTK_PIN_NO(61) | 1) +-#define MT6797_GPIO61__FUNC_IDDIG (MTK_PIN_NO(61) | 2) +-#define MT6797_GPIO61__FUNC_SPI4_CLK_B (MTK_PIN_NO(61) | 3) +-#define MT6797_GPIO61__FUNC_I2S0_LRCK (MTK_PIN_NO(61) | 4) +-#define MT6797_GPIO61__FUNC_PCM0_SYNC (MTK_PIN_NO(61) | 5) +-#define MT6797_GPIO61__FUNC_C2K_EINT0 (MTK_PIN_NO(61) | 7) +- +-#define MT6797_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +-#define MT6797_GPIO62__FUNC_EINT1 (MTK_PIN_NO(62) | 1) +-#define MT6797_GPIO62__FUNC_USB_DRVVBUS (MTK_PIN_NO(62) | 2) +-#define MT6797_GPIO62__FUNC_SPI4_MI_B (MTK_PIN_NO(62) | 3) +-#define MT6797_GPIO62__FUNC_I2S0_BCK (MTK_PIN_NO(62) | 4) +-#define MT6797_GPIO62__FUNC_PCM0_CLK (MTK_PIN_NO(62) | 5) +-#define MT6797_GPIO62__FUNC_C2K_EINT1 (MTK_PIN_NO(62) | 7) +- +-#define MT6797_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +-#define MT6797_GPIO63__FUNC_EINT2 (MTK_PIN_NO(63) | 1) +-#define MT6797_GPIO63__FUNC_IRTX_OUT (MTK_PIN_NO(63) | 2) +-#define MT6797_GPIO63__FUNC_SPI4_MO_B (MTK_PIN_NO(63) | 3) +-#define MT6797_GPIO63__FUNC_I2S0_MCK (MTK_PIN_NO(63) | 4) +-#define MT6797_GPIO63__FUNC_PCM0_DI (MTK_PIN_NO(63) | 5) +-#define MT6797_GPIO63__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(63) | 7) +- +-#define MT6797_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +-#define MT6797_GPIO64__FUNC_EINT3 (MTK_PIN_NO(64) | 1) +-#define MT6797_GPIO64__FUNC_CMFLASH (MTK_PIN_NO(64) | 2) +-#define MT6797_GPIO64__FUNC_SPI4_CS_B (MTK_PIN_NO(64) | 3) +-#define MT6797_GPIO64__FUNC_I2S0_DI (MTK_PIN_NO(64) | 4) +-#define MT6797_GPIO64__FUNC_PCM0_DO (MTK_PIN_NO(64) | 5) +-#define MT6797_GPIO64__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(64) | 7) +- +-#define MT6797_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +-#define MT6797_GPIO65__FUNC_EINT4 (MTK_PIN_NO(65) | 1) +-#define MT6797_GPIO65__FUNC_CLKM0 (MTK_PIN_NO(65) | 2) +-#define MT6797_GPIO65__FUNC_SPI5_CLK_B (MTK_PIN_NO(65) | 3) +-#define MT6797_GPIO65__FUNC_I2S1_LRCK (MTK_PIN_NO(65) | 4) +-#define MT6797_GPIO65__FUNC_PWM_A (MTK_PIN_NO(65) | 5) +-#define MT6797_GPIO65__FUNC_C2K_DM_EINT2 (MTK_PIN_NO(65) | 7) +- +-#define MT6797_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +-#define MT6797_GPIO66__FUNC_EINT5 (MTK_PIN_NO(66) | 1) +-#define MT6797_GPIO66__FUNC_CLKM1 (MTK_PIN_NO(66) | 2) +-#define MT6797_GPIO66__FUNC_SPI5_MI_B (MTK_PIN_NO(66) | 3) +-#define MT6797_GPIO66__FUNC_I2S1_BCK (MTK_PIN_NO(66) | 4) +-#define MT6797_GPIO66__FUNC_PWM_B (MTK_PIN_NO(66) | 5) +-#define MT6797_GPIO66__FUNC_C2K_DM_EINT3 (MTK_PIN_NO(66) | 7) +- +-#define MT6797_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +-#define MT6797_GPIO67__FUNC_EINT6 (MTK_PIN_NO(67) | 1) +-#define MT6797_GPIO67__FUNC_CLKM2 (MTK_PIN_NO(67) | 2) +-#define MT6797_GPIO67__FUNC_SPI5_MO_B (MTK_PIN_NO(67) | 3) +-#define MT6797_GPIO67__FUNC_I2S1_MCK (MTK_PIN_NO(67) | 4) +-#define MT6797_GPIO67__FUNC_PWM_C (MTK_PIN_NO(67) | 5) +-#define MT6797_GPIO67__FUNC_DBG_MON_A0 (MTK_PIN_NO(67) | 7) +- +-#define MT6797_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +-#define MT6797_GPIO68__FUNC_EINT7 (MTK_PIN_NO(68) | 1) +-#define MT6797_GPIO68__FUNC_CLKM3 (MTK_PIN_NO(68) | 2) +-#define MT6797_GPIO68__FUNC_SPI5_CS_B (MTK_PIN_NO(68) | 3) +-#define MT6797_GPIO68__FUNC_I2S1_DO (MTK_PIN_NO(68) | 4) +-#define MT6797_GPIO68__FUNC_PWM_D (MTK_PIN_NO(68) | 5) +-#define MT6797_GPIO68__FUNC_DBG_MON_A1 (MTK_PIN_NO(68) | 7) +- +-#define MT6797_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +-#define MT6797_GPIO69__FUNC_I2S0_LRCK (MTK_PIN_NO(69) | 1) +-#define MT6797_GPIO69__FUNC_I2S3_LRCK (MTK_PIN_NO(69) | 2) +-#define MT6797_GPIO69__FUNC_I2S1_LRCK (MTK_PIN_NO(69) | 3) +-#define MT6797_GPIO69__FUNC_I2S2_LRCK (MTK_PIN_NO(69) | 4) +-#define MT6797_GPIO69__FUNC_DBG_MON_A2 (MTK_PIN_NO(69) | 7) +- +-#define MT6797_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +-#define MT6797_GPIO70__FUNC_I2S0_BCK (MTK_PIN_NO(70) | 1) +-#define MT6797_GPIO70__FUNC_I2S3_BCK (MTK_PIN_NO(70) | 2) +-#define MT6797_GPIO70__FUNC_I2S1_BCK (MTK_PIN_NO(70) | 3) +-#define MT6797_GPIO70__FUNC_I2S2_BCK (MTK_PIN_NO(70) | 4) +-#define MT6797_GPIO70__FUNC_DBG_MON_A3 (MTK_PIN_NO(70) | 7) +- +-#define MT6797_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +-#define MT6797_GPIO71__FUNC_I2S0_MCK (MTK_PIN_NO(71) | 1) +-#define MT6797_GPIO71__FUNC_I2S3_MCK (MTK_PIN_NO(71) | 2) +-#define MT6797_GPIO71__FUNC_I2S1_MCK (MTK_PIN_NO(71) | 3) +-#define MT6797_GPIO71__FUNC_I2S2_MCK (MTK_PIN_NO(71) | 4) +-#define MT6797_GPIO71__FUNC_DBG_MON_A4 (MTK_PIN_NO(71) | 7) +- +-#define MT6797_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +-/* #define MT6797_GPIO72__FUNC_I2S0_DI (MTK_PIN_NO(72) | 1) */ +-#define MT6797_GPIO72__FUNC_I2S0_DI (MTK_PIN_NO(72) | 2) +-/* #define MT6797_GPIO72__FUNC_I2S2_DI (MTK_PIN_NO(72) | 3) */ +-#define MT6797_GPIO72__FUNC_I2S2_DI (MTK_PIN_NO(72) | 4) +-#define MT6797_GPIO72__FUNC_DBG_MON_A5 (MTK_PIN_NO(72) | 7) +- +-#define MT6797_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +-/* #define MT6797_GPIO73__FUNC_I2S3_DO (MTK_PIN_NO(73) | 1) */ +-#define MT6797_GPIO73__FUNC_I2S3_DO (MTK_PIN_NO(73) | 2) +-/* #define MT6797_GPIO73__FUNC_I2S1_DO (MTK_PIN_NO(73) | 3) */ +-#define MT6797_GPIO73__FUNC_I2S1_DO (MTK_PIN_NO(73) | 4) +-#define MT6797_GPIO73__FUNC_DBG_MON_A6 (MTK_PIN_NO(73) | 7) +- +-#define MT6797_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +-#define MT6797_GPIO74__FUNC_SCL3_0 (MTK_PIN_NO(74) | 1) +-#define MT6797_GPIO74__FUNC_AUXIF_CLK1 (MTK_PIN_NO(74) | 7) +- +-#define MT6797_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +-#define MT6797_GPIO75__FUNC_SDA3_0 (MTK_PIN_NO(75) | 1) +-#define MT6797_GPIO75__FUNC_AUXIF_ST1 (MTK_PIN_NO(75) | 7) +- +-#define MT6797_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +-#define MT6797_GPIO76__FUNC_CONN_HRST_B (MTK_PIN_NO(76) | 1) +-#define MT6797_GPIO76__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(76) | 7) +- +-#define MT6797_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +-#define MT6797_GPIO77__FUNC_CONN_TOP_CLK (MTK_PIN_NO(77) | 1) +-#define MT6797_GPIO77__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(77) | 7) +- +-#define MT6797_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +-#define MT6797_GPIO78__FUNC_CONN_TOP_DATA (MTK_PIN_NO(78) | 1) +-#define MT6797_GPIO78__FUNC_C2K_DM_EINT2 (MTK_PIN_NO(78) | 7) +- +-#define MT6797_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +-#define MT6797_GPIO79__FUNC_CONN_WB_PTA (MTK_PIN_NO(79) | 1) +-#define MT6797_GPIO79__FUNC_C2K_DM_EINT3 (MTK_PIN_NO(79) | 7) +- +-#define MT6797_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +-#define MT6797_GPIO80__FUNC_CONN_WF_HB0 (MTK_PIN_NO(80) | 1) +-#define MT6797_GPIO80__FUNC_C2K_EINT0 (MTK_PIN_NO(80) | 7) +- +-#define MT6797_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +-#define MT6797_GPIO81__FUNC_CONN_WF_HB1 (MTK_PIN_NO(81) | 1) +-#define MT6797_GPIO81__FUNC_C2K_EINT1 (MTK_PIN_NO(81) | 7) +- +-#define MT6797_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +-#define MT6797_GPIO82__FUNC_CONN_WF_HB2 (MTK_PIN_NO(82) | 1) +-#define MT6797_GPIO82__FUNC_MD_CLKM0 (MTK_PIN_NO(82) | 7) +- +-#define MT6797_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +-#define MT6797_GPIO83__FUNC_CONN_BT_CLK (MTK_PIN_NO(83) | 1) +-#define MT6797_GPIO83__FUNC_MD_CLKM1 (MTK_PIN_NO(83) | 7) +- +-#define MT6797_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +-#define MT6797_GPIO84__FUNC_CONN_BT_DATA (MTK_PIN_NO(84) | 1) +- +-#define MT6797_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +-#define MT6797_GPIO85__FUNC_EINT8 (MTK_PIN_NO(85) | 1) +-#define MT6797_GPIO85__FUNC_I2S1_LRCK (MTK_PIN_NO(85) | 2) +-#define MT6797_GPIO85__FUNC_I2S2_LRCK (MTK_PIN_NO(85) | 3) +-#define MT6797_GPIO85__FUNC_URXD1 (MTK_PIN_NO(85) | 4) +-#define MT6797_GPIO85__FUNC_MD_URXD0 (MTK_PIN_NO(85) | 5) +-#define MT6797_GPIO85__FUNC_DBG_MON_A7 (MTK_PIN_NO(85) | 7) +- +-#define MT6797_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +-#define MT6797_GPIO86__FUNC_EINT9 (MTK_PIN_NO(86) | 1) +-#define MT6797_GPIO86__FUNC_I2S1_BCK (MTK_PIN_NO(86) | 2) +-#define MT6797_GPIO86__FUNC_I2S2_BCK (MTK_PIN_NO(86) | 3) +-#define MT6797_GPIO86__FUNC_UTXD1 (MTK_PIN_NO(86) | 4) +-#define MT6797_GPIO86__FUNC_MD_UTXD0 (MTK_PIN_NO(86) | 5) +-#define MT6797_GPIO86__FUNC_DBG_MON_A8 (MTK_PIN_NO(86) | 7) +- +-#define MT6797_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +-#define MT6797_GPIO87__FUNC_EINT10 (MTK_PIN_NO(87) | 1) +-#define MT6797_GPIO87__FUNC_I2S1_MCK (MTK_PIN_NO(87) | 2) +-#define MT6797_GPIO87__FUNC_I2S2_MCK (MTK_PIN_NO(87) | 3) +-#define MT6797_GPIO87__FUNC_URTS1 (MTK_PIN_NO(87) | 4) +-#define MT6797_GPIO87__FUNC_MD_URXD1 (MTK_PIN_NO(87) | 5) +-#define MT6797_GPIO87__FUNC_DBG_MON_A9 (MTK_PIN_NO(87) | 7) +- +-#define MT6797_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +-#define MT6797_GPIO88__FUNC_EINT11 (MTK_PIN_NO(88) | 1) +-#define MT6797_GPIO88__FUNC_I2S1_DO (MTK_PIN_NO(88) | 2) +-#define MT6797_GPIO88__FUNC_I2S2_DI (MTK_PIN_NO(88) | 3) +-#define MT6797_GPIO88__FUNC_UCTS1 (MTK_PIN_NO(88) | 4) +-#define MT6797_GPIO88__FUNC_MD_UTXD1 (MTK_PIN_NO(88) | 5) +-#define MT6797_GPIO88__FUNC_DBG_MON_A10 (MTK_PIN_NO(88) | 7) +- +-#define MT6797_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +-#define MT6797_GPIO89__FUNC_EINT12 (MTK_PIN_NO(89) | 1) +-#define MT6797_GPIO89__FUNC_IRTX_OUT (MTK_PIN_NO(89) | 2) +-#define MT6797_GPIO89__FUNC_CLKM0 (MTK_PIN_NO(89) | 3) +-#define MT6797_GPIO89__FUNC_PCM1_SYNC (MTK_PIN_NO(89) | 4) +-#define MT6797_GPIO89__FUNC_URTS0 (MTK_PIN_NO(89) | 5) +-#define MT6797_GPIO89__FUNC_DBG_MON_A11 (MTK_PIN_NO(89) | 7) +- +-#define MT6797_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +-#define MT6797_GPIO90__FUNC_EINT13 (MTK_PIN_NO(90) | 1) +-#define MT6797_GPIO90__FUNC_CMFLASH (MTK_PIN_NO(90) | 2) +-#define MT6797_GPIO90__FUNC_CLKM1 (MTK_PIN_NO(90) | 3) +-#define MT6797_GPIO90__FUNC_PCM1_CLK (MTK_PIN_NO(90) | 4) +-#define MT6797_GPIO90__FUNC_UCTS0 (MTK_PIN_NO(90) | 5) +-#define MT6797_GPIO90__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(90) | 7) +- +-#define MT6797_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +-#define MT6797_GPIO91__FUNC_EINT14 (MTK_PIN_NO(91) | 1) +-#define MT6797_GPIO91__FUNC_PWM_A (MTK_PIN_NO(91) | 2) +-#define MT6797_GPIO91__FUNC_CLKM2 (MTK_PIN_NO(91) | 3) +-#define MT6797_GPIO91__FUNC_PCM1_DI (MTK_PIN_NO(91) | 4) +-#define MT6797_GPIO91__FUNC_SDA0_3 (MTK_PIN_NO(91) | 5) +-#define MT6797_GPIO91__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(91) | 7) +- +-#define MT6797_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +-#define MT6797_GPIO92__FUNC_EINT15 (MTK_PIN_NO(92) | 1) +-#define MT6797_GPIO92__FUNC_PWM_B (MTK_PIN_NO(92) | 2) +-#define MT6797_GPIO92__FUNC_CLKM3 (MTK_PIN_NO(92) | 3) +-#define MT6797_GPIO92__FUNC_PCM1_DO0 (MTK_PIN_NO(92) | 4) +-#define MT6797_GPIO92__FUNC_SCL0_3 (MTK_PIN_NO(92) | 5) +- +-#define MT6797_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +-#define MT6797_GPIO93__FUNC_EINT16 (MTK_PIN_NO(93) | 1) +-#define MT6797_GPIO93__FUNC_IDDIG (MTK_PIN_NO(93) | 2) +-#define MT6797_GPIO93__FUNC_CLKM4 (MTK_PIN_NO(93) | 3) +-#define MT6797_GPIO93__FUNC_PCM1_DO1 (MTK_PIN_NO(93) | 4) +-#define MT6797_GPIO93__FUNC_MD_INT2 (MTK_PIN_NO(93) | 5) +-#define MT6797_GPIO93__FUNC_DROP_ZONE (MTK_PIN_NO(93) | 7) +- +-#define MT6797_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +-#define MT6797_GPIO94__FUNC_USB_DRVVBUS (MTK_PIN_NO(94) | 1) +-#define MT6797_GPIO94__FUNC_PWM_C (MTK_PIN_NO(94) | 2) +-#define MT6797_GPIO94__FUNC_CLKM5 (MTK_PIN_NO(94) | 3) +- +-#define MT6797_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +-#define MT6797_GPIO95__FUNC_SDA2_0 (MTK_PIN_NO(95) | 1) +-#define MT6797_GPIO95__FUNC_AUXIF_ST0 (MTK_PIN_NO(95) | 7) +- +-#define MT6797_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +-#define MT6797_GPIO96__FUNC_SCL2_0 (MTK_PIN_NO(96) | 1) +-#define MT6797_GPIO96__FUNC_AUXIF_CLK0 (MTK_PIN_NO(96) | 7) +- +-#define MT6797_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +-#define MT6797_GPIO97__FUNC_URXD0 (MTK_PIN_NO(97) | 1) +-#define MT6797_GPIO97__FUNC_UTXD0 (MTK_PIN_NO(97) | 2) +-#define MT6797_GPIO97__FUNC_MD_URXD0 (MTK_PIN_NO(97) | 3) +-#define MT6797_GPIO97__FUNC_MD_URXD1 (MTK_PIN_NO(97) | 4) +-#define MT6797_GPIO97__FUNC_MD_URXD2 (MTK_PIN_NO(97) | 5) +-#define MT6797_GPIO97__FUNC_C2K_URXD0 (MTK_PIN_NO(97) | 6) +-#define MT6797_GPIO97__FUNC_C2K_URXD1 (MTK_PIN_NO(97) | 7) +- +-#define MT6797_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +-#define MT6797_GPIO98__FUNC_UTXD0 (MTK_PIN_NO(98) | 1) +-#define MT6797_GPIO98__FUNC_URXD0 (MTK_PIN_NO(98) | 2) +-#define MT6797_GPIO98__FUNC_MD_UTXD0 (MTK_PIN_NO(98) | 3) +-#define MT6797_GPIO98__FUNC_MD_UTXD1 (MTK_PIN_NO(98) | 4) +-#define MT6797_GPIO98__FUNC_MD_UTXD2 (MTK_PIN_NO(98) | 5) +-#define MT6797_GPIO98__FUNC_C2K_UTXD0 (MTK_PIN_NO(98) | 6) +-#define MT6797_GPIO98__FUNC_C2K_UTXD1 (MTK_PIN_NO(98) | 7) +- +-#define MT6797_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +-#define MT6797_GPIO99__FUNC_RTC32K_CK (MTK_PIN_NO(99) | 1) +- +-#define MT6797_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +-#define MT6797_GPIO100__FUNC_SRCLKENAI0 (MTK_PIN_NO(100) | 1) +- +-#define MT6797_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +-#define MT6797_GPIO101__FUNC_SRCLKENAI1 (MTK_PIN_NO(101) | 1) +- +-#define MT6797_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +-#define MT6797_GPIO102__FUNC_SRCLKENA0 (MTK_PIN_NO(102) | 1) +- +-#define MT6797_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +-#define MT6797_GPIO103__FUNC_SRCLKENA1 (MTK_PIN_NO(103) | 1) +- +-#define MT6797_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +-#define MT6797_GPIO104__FUNC_SYSRSTB (MTK_PIN_NO(104) | 1) +- +-#define MT6797_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +-#define MT6797_GPIO105__FUNC_WATCHDOG (MTK_PIN_NO(105) | 1) +- +-#define MT6797_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +-#define MT6797_GPIO106__FUNC_KPROW0 (MTK_PIN_NO(106) | 1) +-#define MT6797_GPIO106__FUNC_CMFLASH (MTK_PIN_NO(106) | 2) +-#define MT6797_GPIO106__FUNC_CLKM4 (MTK_PIN_NO(106) | 3) +-#define MT6797_GPIO106__FUNC_TP_GPIO0_AO (MTK_PIN_NO(106) | 4) +-#define MT6797_GPIO106__FUNC_IRTX_OUT (MTK_PIN_NO(106) | 5) +- +-#define MT6797_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +-#define MT6797_GPIO107__FUNC_KPROW1 (MTK_PIN_NO(107) | 1) +-#define MT6797_GPIO107__FUNC_IDDIG (MTK_PIN_NO(107) | 2) +-#define MT6797_GPIO107__FUNC_CLKM5 (MTK_PIN_NO(107) | 3) +-#define MT6797_GPIO107__FUNC_TP_GPIO1_AO (MTK_PIN_NO(107) | 4) +-#define MT6797_GPIO107__FUNC_I2S1_BCK (MTK_PIN_NO(107) | 5) +-#define MT6797_GPIO107__FUNC_DAP_SIB1_SWD (MTK_PIN_NO(107) | 7) +- +-#define MT6797_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +-#define MT6797_GPIO108__FUNC_KPROW2 (MTK_PIN_NO(108) | 1) +-#define MT6797_GPIO108__FUNC_USB_DRVVBUS (MTK_PIN_NO(108) | 2) +-#define MT6797_GPIO108__FUNC_PWM_A (MTK_PIN_NO(108) | 3) +-#define MT6797_GPIO108__FUNC_CMFLASH (MTK_PIN_NO(108) | 4) +-#define MT6797_GPIO108__FUNC_I2S1_LRCK (MTK_PIN_NO(108) | 5) +-#define MT6797_GPIO108__FUNC_DAP_SIB1_SWCK (MTK_PIN_NO(108) | 7) +- +-#define MT6797_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +-#define MT6797_GPIO109__FUNC_KPCOL0 (MTK_PIN_NO(109) | 1) +- +-#define MT6797_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +-#define MT6797_GPIO110__FUNC_KPCOL1 (MTK_PIN_NO(110) | 1) +-#define MT6797_GPIO110__FUNC_SDA1_3 (MTK_PIN_NO(110) | 2) +-#define MT6797_GPIO110__FUNC_PWM_B (MTK_PIN_NO(110) | 3) +-#define MT6797_GPIO110__FUNC_CLKM0 (MTK_PIN_NO(110) | 4) +-#define MT6797_GPIO110__FUNC_I2S1_DO (MTK_PIN_NO(110) | 5) +-#define MT6797_GPIO110__FUNC_C2K_DM_EINT3 (MTK_PIN_NO(110) | 7) +- +-#define MT6797_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +-#define MT6797_GPIO111__FUNC_KPCOL2 (MTK_PIN_NO(111) | 1) +-#define MT6797_GPIO111__FUNC_SCL1_3 (MTK_PIN_NO(111) | 2) +-#define MT6797_GPIO111__FUNC_PWM_C (MTK_PIN_NO(111) | 3) +-#define MT6797_GPIO111__FUNC_DISP_PWM (MTK_PIN_NO(111) | 4) +-#define MT6797_GPIO111__FUNC_I2S1_MCK (MTK_PIN_NO(111) | 5) +-#define MT6797_GPIO111__FUNC_C2K_DM_EINT2 (MTK_PIN_NO(111) | 7) +- +-#define MT6797_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +-#define MT6797_GPIO112__FUNC_MD_INT1_C2K_UIM1_HOT_PLUG_IN (MTK_PIN_NO(112) | 1) +-#define MT6797_GPIO112__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(112) | 7) +- +-#define MT6797_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +-#define MT6797_GPIO113__FUNC_MD_INT0_C2K_UIM0_HOT_PLUG_IN (MTK_PIN_NO(113) | 1) +-#define MT6797_GPIO113__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(113) | 7) +- +-#define MT6797_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +-#define MT6797_GPIO114__FUNC_MSDC0_DAT0 (MTK_PIN_NO(114) | 1) +- +-#define MT6797_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +-#define MT6797_GPIO115__FUNC_MSDC0_DAT1 (MTK_PIN_NO(115) | 1) +- +-#define MT6797_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +-#define MT6797_GPIO116__FUNC_MSDC0_DAT2 (MTK_PIN_NO(116) | 1) +- +-#define MT6797_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +-#define MT6797_GPIO117__FUNC_MSDC0_DAT3 (MTK_PIN_NO(117) | 1) +- +-#define MT6797_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +-#define MT6797_GPIO118__FUNC_MSDC0_DAT4 (MTK_PIN_NO(118) | 1) +- +-#define MT6797_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +-#define MT6797_GPIO119__FUNC_MSDC0_DAT5 (MTK_PIN_NO(119) | 1) +- +-#define MT6797_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +-#define MT6797_GPIO120__FUNC_MSDC0_DAT6 (MTK_PIN_NO(120) | 1) +- +-#define MT6797_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +-#define MT6797_GPIO121__FUNC_MSDC0_DAT7 (MTK_PIN_NO(121) | 1) +- +-#define MT6797_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +-#define MT6797_GPIO122__FUNC_MSDC0_CMD (MTK_PIN_NO(122) | 1) +- +-#define MT6797_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +-#define MT6797_GPIO123__FUNC_MSDC0_CLK (MTK_PIN_NO(123) | 1) +- +-#define MT6797_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +-#define MT6797_GPIO124__FUNC_MSDC0_DSL (MTK_PIN_NO(124) | 1) +- +-#define MT6797_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +-#define MT6797_GPIO125__FUNC_MSDC0_RSTB (MTK_PIN_NO(125) | 1) +- +-#define MT6797_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +-#define MT6797_GPIO126__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(126) | 1) +-#define MT6797_GPIO126__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(126) | 2) +-#define MT6797_GPIO126__FUNC_C2K_UIM0_CLK (MTK_PIN_NO(126) | 3) +-#define MT6797_GPIO126__FUNC_C2K_UIM1_CLK (MTK_PIN_NO(126) | 4) +- +-#define MT6797_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +-#define MT6797_GPIO127__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(127) | 1) +-#define MT6797_GPIO127__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(127) | 2) +-#define MT6797_GPIO127__FUNC_C2K_UIM0_RST (MTK_PIN_NO(127) | 3) +-#define MT6797_GPIO127__FUNC_C2K_UIM1_RST (MTK_PIN_NO(127) | 4) +- +-#define MT6797_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +-#define MT6797_GPIO128__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(128) | 1) +-#define MT6797_GPIO128__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(128) | 2) +-#define MT6797_GPIO128__FUNC_C2K_UIM0_IO (MTK_PIN_NO(128) | 3) +-#define MT6797_GPIO128__FUNC_C2K_UIM1_IO (MTK_PIN_NO(128) | 4) +- +-#define MT6797_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +-#define MT6797_GPIO129__FUNC_MSDC1_CMD (MTK_PIN_NO(129) | 1) +-#define MT6797_GPIO129__FUNC_CONN_DSP_JMS (MTK_PIN_NO(129) | 2) +-#define MT6797_GPIO129__FUNC_LTE_JTAG_TMS (MTK_PIN_NO(129) | 3) +-#define MT6797_GPIO129__FUNC_UDI_TMS (MTK_PIN_NO(129) | 4) +-#define MT6797_GPIO129__FUNC_C2K_TMS (MTK_PIN_NO(129) | 5) +- +-#define MT6797_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +-#define MT6797_GPIO130__FUNC_MSDC1_DAT0 (MTK_PIN_NO(130) | 1) +-#define MT6797_GPIO130__FUNC_CONN_DSP_JDI (MTK_PIN_NO(130) | 2) +-#define MT6797_GPIO130__FUNC_LTE_JTAG_TDI (MTK_PIN_NO(130) | 3) +-#define MT6797_GPIO130__FUNC_UDI_TDI (MTK_PIN_NO(130) | 4) +-#define MT6797_GPIO130__FUNC_C2K_TDI (MTK_PIN_NO(130) | 5) +- +-#define MT6797_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +-#define MT6797_GPIO131__FUNC_MSDC1_DAT1 (MTK_PIN_NO(131) | 1) +-#define MT6797_GPIO131__FUNC_CONN_DSP_JDO (MTK_PIN_NO(131) | 2) +-#define MT6797_GPIO131__FUNC_LTE_JTAG_TDO (MTK_PIN_NO(131) | 3) +-#define MT6797_GPIO131__FUNC_UDI_TDO (MTK_PIN_NO(131) | 4) +-#define MT6797_GPIO131__FUNC_C2K_TDO (MTK_PIN_NO(131) | 5) +- +-#define MT6797_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +-#define MT6797_GPIO132__FUNC_MSDC1_DAT2 (MTK_PIN_NO(132) | 1) +-#define MT6797_GPIO132__FUNC_C2K_RTCK (MTK_PIN_NO(132) | 5) +- +-#define MT6797_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +-#define MT6797_GPIO133__FUNC_MSDC1_DAT3 (MTK_PIN_NO(133) | 1) +-#define MT6797_GPIO133__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(133) | 2) +-#define MT6797_GPIO133__FUNC_LTE_JTAG_TRSTN (MTK_PIN_NO(133) | 3) +-#define MT6797_GPIO133__FUNC_UDI_NTRST (MTK_PIN_NO(133) | 4) +-#define MT6797_GPIO133__FUNC_C2K_NTRST (MTK_PIN_NO(133) | 5) +- +-#define MT6797_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +-#define MT6797_GPIO134__FUNC_MSDC1_CLK (MTK_PIN_NO(134) | 1) +-#define MT6797_GPIO134__FUNC_CONN_DSP_JCK (MTK_PIN_NO(134) | 2) +-#define MT6797_GPIO134__FUNC_LTE_JTAG_TCK (MTK_PIN_NO(134) | 3) +-#define MT6797_GPIO134__FUNC_UDI_TCK_XI (MTK_PIN_NO(134) | 4) +-#define MT6797_GPIO134__FUNC_C2K_TCK (MTK_PIN_NO(134) | 5) +- +-#define MT6797_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +-#define MT6797_GPIO135__FUNC_TDM_LRCK (MTK_PIN_NO(135) | 1) +-#define MT6797_GPIO135__FUNC_I2S0_LRCK (MTK_PIN_NO(135) | 2) +-#define MT6797_GPIO135__FUNC_CLKM0 (MTK_PIN_NO(135) | 3) +-#define MT6797_GPIO135__FUNC_PCM1_SYNC (MTK_PIN_NO(135) | 4) +-#define MT6797_GPIO135__FUNC_PWM_A (MTK_PIN_NO(135) | 5) +-#define MT6797_GPIO135__FUNC_DBG_MON_A12 (MTK_PIN_NO(135) | 7) +- +-#define MT6797_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +-#define MT6797_GPIO136__FUNC_TDM_BCK (MTK_PIN_NO(136) | 1) +-#define MT6797_GPIO136__FUNC_I2S0_BCK (MTK_PIN_NO(136) | 2) +-#define MT6797_GPIO136__FUNC_CLKM1 (MTK_PIN_NO(136) | 3) +-#define MT6797_GPIO136__FUNC_PCM1_CLK (MTK_PIN_NO(136) | 4) +-#define MT6797_GPIO136__FUNC_PWM_B (MTK_PIN_NO(136) | 5) +-#define MT6797_GPIO136__FUNC_DBG_MON_A13 (MTK_PIN_NO(136) | 7) +- +-#define MT6797_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +-#define MT6797_GPIO137__FUNC_TDM_MCK (MTK_PIN_NO(137) | 1) +-#define MT6797_GPIO137__FUNC_I2S0_MCK (MTK_PIN_NO(137) | 2) +-#define MT6797_GPIO137__FUNC_CLKM2 (MTK_PIN_NO(137) | 3) +-#define MT6797_GPIO137__FUNC_PCM1_DI (MTK_PIN_NO(137) | 4) +-#define MT6797_GPIO137__FUNC_IRTX_OUT (MTK_PIN_NO(137) | 5) +-#define MT6797_GPIO137__FUNC_DBG_MON_A14 (MTK_PIN_NO(137) | 7) +- +-#define MT6797_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +-#define MT6797_GPIO138__FUNC_TDM_DATA0 (MTK_PIN_NO(138) | 1) +-#define MT6797_GPIO138__FUNC_I2S0_DI (MTK_PIN_NO(138) | 2) +-#define MT6797_GPIO138__FUNC_CLKM3 (MTK_PIN_NO(138) | 3) +-#define MT6797_GPIO138__FUNC_PCM1_DO0 (MTK_PIN_NO(138) | 4) +-#define MT6797_GPIO138__FUNC_PWM_C (MTK_PIN_NO(138) | 5) +-#define MT6797_GPIO138__FUNC_SDA3_1 (MTK_PIN_NO(138) | 6) +-#define MT6797_GPIO138__FUNC_DBG_MON_A15 (MTK_PIN_NO(138) | 7) +- +-#define MT6797_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +-#define MT6797_GPIO139__FUNC_TDM_DATA1 (MTK_PIN_NO(139) | 1) +-#define MT6797_GPIO139__FUNC_I2S3_DO (MTK_PIN_NO(139) | 2) +-#define MT6797_GPIO139__FUNC_CLKM4 (MTK_PIN_NO(139) | 3) +-#define MT6797_GPIO139__FUNC_PCM1_DO1 (MTK_PIN_NO(139) | 4) +-#define MT6797_GPIO139__FUNC_ANT_SEL2 (MTK_PIN_NO(139) | 5) +-#define MT6797_GPIO139__FUNC_SCL3_1 (MTK_PIN_NO(139) | 6) +-#define MT6797_GPIO139__FUNC_DBG_MON_A16 (MTK_PIN_NO(139) | 7) +- +-#define MT6797_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +-#define MT6797_GPIO140__FUNC_TDM_DATA2 (MTK_PIN_NO(140) | 1) +-#define MT6797_GPIO140__FUNC_DISP_PWM (MTK_PIN_NO(140) | 2) +-#define MT6797_GPIO140__FUNC_CLKM5 (MTK_PIN_NO(140) | 3) +-#define MT6797_GPIO140__FUNC_SDA1_4 (MTK_PIN_NO(140) | 4) +-#define MT6797_GPIO140__FUNC_ANT_SEL1 (MTK_PIN_NO(140) | 5) +-#define MT6797_GPIO140__FUNC_URXD3 (MTK_PIN_NO(140) | 6) +-#define MT6797_GPIO140__FUNC_DBG_MON_A17 (MTK_PIN_NO(140) | 7) +- +-#define MT6797_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +-#define MT6797_GPIO141__FUNC_TDM_DATA3 (MTK_PIN_NO(141) | 1) +-#define MT6797_GPIO141__FUNC_CMFLASH (MTK_PIN_NO(141) | 2) +-#define MT6797_GPIO141__FUNC_IRTX_OUT (MTK_PIN_NO(141) | 3) +-#define MT6797_GPIO141__FUNC_SCL1_4 (MTK_PIN_NO(141) | 4) +-#define MT6797_GPIO141__FUNC_ANT_SEL0 (MTK_PIN_NO(141) | 5) +-#define MT6797_GPIO141__FUNC_UTXD3 (MTK_PIN_NO(141) | 6) +-#define MT6797_GPIO141__FUNC_DBG_MON_A18 (MTK_PIN_NO(141) | 7) +- +-#define MT6797_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +-#define MT6797_GPIO142__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(142) | 1) +-#define MT6797_GPIO142__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(142) | 2) +- +-#define MT6797_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +-#define MT6797_GPIO143__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(143) | 1) +-#define MT6797_GPIO143__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(143) | 2) +- +-#define MT6797_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +-#define MT6797_GPIO144__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(144) | 1) +- +-#define MT6797_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +-#define MT6797_GPIO145__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(145) | 1) +- +-#define MT6797_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +-#define MT6797_GPIO146__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(146) | 1) +- +-#define MT6797_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +-#define MT6797_GPIO147__FUNC_AUD_DAT_MISO (MTK_PIN_NO(147) | 1) +-#define MT6797_GPIO147__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(147) | 2) +-#define MT6797_GPIO147__FUNC_VOW_DAT_MISO (MTK_PIN_NO(147) | 3) +- +-#define MT6797_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +-#define MT6797_GPIO148__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(148) | 1) +-#define MT6797_GPIO148__FUNC_AUD_DAT_MISO (MTK_PIN_NO(148) | 2) +- +-#define MT6797_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +-#define MT6797_GPIO149__FUNC_VOW_CLK_MISO (MTK_PIN_NO(149) | 1) +- +-#define MT6797_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +-#define MT6797_GPIO150__FUNC_ANC_DAT_MOSI (MTK_PIN_NO(150) | 1) +- +-#define MT6797_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +-#define MT6797_GPIO151__FUNC_SCL6_0 (MTK_PIN_NO(151) | 1) +- +-#define MT6797_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +-#define MT6797_GPIO152__FUNC_SDA6_0 (MTK_PIN_NO(152) | 1) +- +-#define MT6797_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +-#define MT6797_GPIO153__FUNC_SCL7_0 (MTK_PIN_NO(153) | 1) +- +-#define MT6797_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +-#define MT6797_GPIO154__FUNC_SDA7_0 (MTK_PIN_NO(154) | 1) +- +-#define MT6797_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +-#define MT6797_GPIO155__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(155) | 1) +-#define MT6797_GPIO155__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(155) | 2) +-#define MT6797_GPIO155__FUNC_C2K_UIM0_CLK (MTK_PIN_NO(155) | 3) +-#define MT6797_GPIO155__FUNC_C2K_UIM1_CLK (MTK_PIN_NO(155) | 4) +- +-#define MT6797_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +-#define MT6797_GPIO156__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(156) | 1) +-#define MT6797_GPIO156__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(156) | 2) +-#define MT6797_GPIO156__FUNC_C2K_UIM0_RST (MTK_PIN_NO(156) | 3) +-#define MT6797_GPIO156__FUNC_C2K_UIM1_RST (MTK_PIN_NO(156) | 4) +- +-#define MT6797_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +-#define MT6797_GPIO157__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(157) | 1) +-#define MT6797_GPIO157__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(157) | 2) +-#define MT6797_GPIO157__FUNC_C2K_UIM0_IO (MTK_PIN_NO(157) | 3) +-#define MT6797_GPIO157__FUNC_C2K_UIM1_IO (MTK_PIN_NO(157) | 4) +- +-#define MT6797_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +-#define MT6797_GPIO158__FUNC_MIPI_TDP0 (MTK_PIN_NO(158) | 1) +- +-#define MT6797_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +-#define MT6797_GPIO159__FUNC_MIPI_TDN0 (MTK_PIN_NO(159) | 1) +- +-#define MT6797_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +-#define MT6797_GPIO160__FUNC_MIPI_TDP1 (MTK_PIN_NO(160) | 1) +- +-#define MT6797_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +-#define MT6797_GPIO161__FUNC_MIPI_TDN1 (MTK_PIN_NO(161) | 1) +- +-#define MT6797_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +-#define MT6797_GPIO162__FUNC_MIPI_TCP (MTK_PIN_NO(162) | 1) +- +-#define MT6797_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +-#define MT6797_GPIO163__FUNC_MIPI_TCN (MTK_PIN_NO(163) | 1) +- +-#define MT6797_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +-#define MT6797_GPIO164__FUNC_MIPI_TDP2 (MTK_PIN_NO(164) | 1) +- +-#define MT6797_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +-#define MT6797_GPIO165__FUNC_MIPI_TDN2 (MTK_PIN_NO(165) | 1) +- +-#define MT6797_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +-#define MT6797_GPIO166__FUNC_MIPI_TDP3 (MTK_PIN_NO(166) | 1) +- +-#define MT6797_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +-#define MT6797_GPIO167__FUNC_MIPI_TDN3 (MTK_PIN_NO(167) | 1) +- +-#define MT6797_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +-#define MT6797_GPIO168__FUNC_MIPI_TDP0_A (MTK_PIN_NO(168) | 1) +- +-#define MT6797_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +-#define MT6797_GPIO169__FUNC_MIPI_TDN0_A (MTK_PIN_NO(169) | 1) +- +-#define MT6797_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +-#define MT6797_GPIO170__FUNC_MIPI_TDP1_A (MTK_PIN_NO(170) | 1) +- +-#define MT6797_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +-#define MT6797_GPIO171__FUNC_MIPI_TDN1_A (MTK_PIN_NO(171) | 1) +- +-#define MT6797_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +-#define MT6797_GPIO172__FUNC_MIPI_TCP_A (MTK_PIN_NO(172) | 1) +- +-#define MT6797_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +-#define MT6797_GPIO173__FUNC_MIPI_TCN_A (MTK_PIN_NO(173) | 1) +- +-#define MT6797_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +-#define MT6797_GPIO174__FUNC_MIPI_TDP2_A (MTK_PIN_NO(174) | 1) +- +-#define MT6797_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +-#define MT6797_GPIO175__FUNC_MIPI_TDN2_A (MTK_PIN_NO(175) | 1) +- +-#define MT6797_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +-#define MT6797_GPIO176__FUNC_MIPI_TDP3_A (MTK_PIN_NO(176) | 1) +- +-#define MT6797_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +-#define MT6797_GPIO177__FUNC_MIPI_TDN3_A (MTK_PIN_NO(177) | 1) +- +-#define MT6797_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +-#define MT6797_GPIO178__FUNC_DISP_PWM (MTK_PIN_NO(178) | 1) +-#define MT6797_GPIO178__FUNC_PWM_D (MTK_PIN_NO(178) | 2) +-#define MT6797_GPIO178__FUNC_CLKM5 (MTK_PIN_NO(178) | 3) +-#define MT6797_GPIO178__FUNC_DBG_MON_A19 (MTK_PIN_NO(178) | 7) +- +-#define MT6797_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +-#define MT6797_GPIO179__FUNC_DSI_TE0 (MTK_PIN_NO(179) | 1) +-#define MT6797_GPIO179__FUNC_DBG_MON_A20 (MTK_PIN_NO(179) | 7) +- +-#define MT6797_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +-#define MT6797_GPIO180__FUNC_LCM_RST (MTK_PIN_NO(180) | 1) +-#define MT6797_GPIO180__FUNC_DSI_TE1 (MTK_PIN_NO(180) | 2) +-#define MT6797_GPIO180__FUNC_DBG_MON_A21 (MTK_PIN_NO(180) | 7) +- +-#define MT6797_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +-#define MT6797_GPIO181__FUNC_IDDIG (MTK_PIN_NO(181) | 1) +-#define MT6797_GPIO181__FUNC_DSI_TE1 (MTK_PIN_NO(181) | 2) +-#define MT6797_GPIO181__FUNC_DBG_MON_A22 (MTK_PIN_NO(181) | 7) +- +-#define MT6797_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +-#define MT6797_GPIO182__FUNC_TESTMODE (MTK_PIN_NO(182) | 1) +- +-#define MT6797_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +-#define MT6797_GPIO183__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(183) | 1) +-#define MT6797_GPIO183__FUNC_SPM_BSI_CK (MTK_PIN_NO(183) | 2) +-#define MT6797_GPIO183__FUNC_DBG_MON_B27 (MTK_PIN_NO(183) | 7) +- +-#define MT6797_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +-#define MT6797_GPIO184__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(184) | 1) +-#define MT6797_GPIO184__FUNC_SPM_BSI_EN (MTK_PIN_NO(184) | 2) +-#define MT6797_GPIO184__FUNC_DBG_MON_B28 (MTK_PIN_NO(184) | 7) +- +-#define MT6797_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +-#define MT6797_GPIO185__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(185) | 1) +-#define MT6797_GPIO185__FUNC_SPM_BSI_D0 (MTK_PIN_NO(185) | 2) +-#define MT6797_GPIO185__FUNC_DBG_MON_B29 (MTK_PIN_NO(185) | 7) +- +-#define MT6797_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +-#define MT6797_GPIO186__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(186) | 1) +-#define MT6797_GPIO186__FUNC_SPM_BSI_D1 (MTK_PIN_NO(186) | 2) +-#define MT6797_GPIO186__FUNC_DBG_MON_B30 (MTK_PIN_NO(186) | 7) +- +-#define MT6797_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +-#define MT6797_GPIO187__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(187) | 1) +-#define MT6797_GPIO187__FUNC_SPM_BSI_D2 (MTK_PIN_NO(187) | 2) +-#define MT6797_GPIO187__FUNC_DBG_MON_B31 (MTK_PIN_NO(187) | 7) +- +-#define MT6797_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +-#define MT6797_GPIO188__FUNC_MIPI0_SCLK (MTK_PIN_NO(188) | 1) +-#define MT6797_GPIO188__FUNC_DBG_MON_B32 (MTK_PIN_NO(188) | 7) +- +-#define MT6797_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +-#define MT6797_GPIO189__FUNC_MIPI0_SDATA (MTK_PIN_NO(189) | 1) +- +-#define MT6797_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +-#define MT6797_GPIO190__FUNC_MIPI1_SCLK (MTK_PIN_NO(190) | 1) +- +-#define MT6797_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +-#define MT6797_GPIO191__FUNC_MIPI1_SDATA (MTK_PIN_NO(191) | 1) +- +-#define MT6797_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +-#define MT6797_GPIO192__FUNC_BPI_BUS4 (MTK_PIN_NO(192) | 1) +- +-#define MT6797_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +-#define MT6797_GPIO193__FUNC_BPI_BUS5 (MTK_PIN_NO(193) | 1) +-#define MT6797_GPIO193__FUNC_DBG_MON_B0 (MTK_PIN_NO(193) | 7) +- +-#define MT6797_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +-#define MT6797_GPIO194__FUNC_BPI_BUS6 (MTK_PIN_NO(194) | 1) +-#define MT6797_GPIO194__FUNC_DBG_MON_B1 (MTK_PIN_NO(194) | 7) +- +-#define MT6797_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +-#define MT6797_GPIO195__FUNC_BPI_BUS7 (MTK_PIN_NO(195) | 1) +-#define MT6797_GPIO195__FUNC_DBG_MON_B2 (MTK_PIN_NO(195) | 7) +- +-#define MT6797_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +-#define MT6797_GPIO196__FUNC_BPI_BUS8 (MTK_PIN_NO(196) | 1) +-#define MT6797_GPIO196__FUNC_DBG_MON_B3 (MTK_PIN_NO(196) | 7) +- +-#define MT6797_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +-#define MT6797_GPIO197__FUNC_BPI_BUS9 (MTK_PIN_NO(197) | 1) +-#define MT6797_GPIO197__FUNC_DBG_MON_B4 (MTK_PIN_NO(197) | 7) +- +-#define MT6797_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +-#define MT6797_GPIO198__FUNC_BPI_BUS10 (MTK_PIN_NO(198) | 1) +-#define MT6797_GPIO198__FUNC_DBG_MON_B5 (MTK_PIN_NO(198) | 7) +- +-#define MT6797_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +-#define MT6797_GPIO199__FUNC_BPI_BUS11 (MTK_PIN_NO(199) | 1) +-#define MT6797_GPIO199__FUNC_DBG_MON_B6 (MTK_PIN_NO(199) | 7) +- +-#define MT6797_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +-#define MT6797_GPIO200__FUNC_BPI_BUS12 (MTK_PIN_NO(200) | 1) +-#define MT6797_GPIO200__FUNC_DBG_MON_B7 (MTK_PIN_NO(200) | 7) +- +-#define MT6797_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +-#define MT6797_GPIO201__FUNC_BPI_BUS13 (MTK_PIN_NO(201) | 1) +-#define MT6797_GPIO201__FUNC_DBG_MON_B8 (MTK_PIN_NO(201) | 7) +- +-#define MT6797_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +-#define MT6797_GPIO202__FUNC_BPI_BUS14 (MTK_PIN_NO(202) | 1) +-#define MT6797_GPIO202__FUNC_DBG_MON_B9 (MTK_PIN_NO(202) | 7) +- +-#define MT6797_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) +-#define MT6797_GPIO203__FUNC_BPI_BUS15 (MTK_PIN_NO(203) | 1) +-#define MT6797_GPIO203__FUNC_DBG_MON_B10 (MTK_PIN_NO(203) | 7) +- +-#define MT6797_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) +-#define MT6797_GPIO204__FUNC_BPI_BUS16 (MTK_PIN_NO(204) | 1) +-#define MT6797_GPIO204__FUNC_PA_VM0 (MTK_PIN_NO(204) | 2) +-#define MT6797_GPIO204__FUNC_DBG_MON_B11 (MTK_PIN_NO(204) | 7) +- +-#define MT6797_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) +-#define MT6797_GPIO205__FUNC_BPI_BUS17 (MTK_PIN_NO(205) | 1) +-#define MT6797_GPIO205__FUNC_PA_VM1 (MTK_PIN_NO(205) | 2) +-#define MT6797_GPIO205__FUNC_DBG_MON_B12 (MTK_PIN_NO(205) | 7) +- +-#define MT6797_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) +-#define MT6797_GPIO206__FUNC_BPI_BUS18 (MTK_PIN_NO(206) | 1) +-#define MT6797_GPIO206__FUNC_TX_SWAP0 (MTK_PIN_NO(206) | 2) +-#define MT6797_GPIO206__FUNC_DBG_MON_B13 (MTK_PIN_NO(206) | 7) +- +-#define MT6797_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) +-#define MT6797_GPIO207__FUNC_BPI_BUS19 (MTK_PIN_NO(207) | 1) +-#define MT6797_GPIO207__FUNC_TX_SWAP1 (MTK_PIN_NO(207) | 2) +-#define MT6797_GPIO207__FUNC_DBG_MON_B14 (MTK_PIN_NO(207) | 7) +- +-#define MT6797_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) +-#define MT6797_GPIO208__FUNC_BPI_BUS20 (MTK_PIN_NO(208) | 1) +-#define MT6797_GPIO208__FUNC_TX_SWAP2 (MTK_PIN_NO(208) | 2) +-#define MT6797_GPIO208__FUNC_DBG_MON_B15 (MTK_PIN_NO(208) | 7) +- +-#define MT6797_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) +-#define MT6797_GPIO209__FUNC_BPI_BUS21 (MTK_PIN_NO(209) | 1) +-#define MT6797_GPIO209__FUNC_TX_SWAP3 (MTK_PIN_NO(209) | 2) +-#define MT6797_GPIO209__FUNC_DBG_MON_B16 (MTK_PIN_NO(209) | 7) +- +-#define MT6797_GPIO210__FUNC_GPIO210 (MTK_PIN_NO(210) | 0) +-#define MT6797_GPIO210__FUNC_BPI_BUS22 (MTK_PIN_NO(210) | 1) +-#define MT6797_GPIO210__FUNC_DET_BPI0 (MTK_PIN_NO(210) | 2) +-#define MT6797_GPIO210__FUNC_DBG_MON_B17 (MTK_PIN_NO(210) | 7) +- +-#define MT6797_GPIO211__FUNC_GPIO211 (MTK_PIN_NO(211) | 0) +-#define MT6797_GPIO211__FUNC_BPI_BUS23 (MTK_PIN_NO(211) | 1) +-#define MT6797_GPIO211__FUNC_DET_BPI1 (MTK_PIN_NO(211) | 2) +-#define MT6797_GPIO211__FUNC_DBG_MON_B18 (MTK_PIN_NO(211) | 7) +- +-#define MT6797_GPIO212__FUNC_GPIO212 (MTK_PIN_NO(212) | 0) +-#define MT6797_GPIO212__FUNC_BPI_BUS0 (MTK_PIN_NO(212) | 1) +-#define MT6797_GPIO212__FUNC_DBG_MON_B19 (MTK_PIN_NO(212) | 7) +- +-#define MT6797_GPIO213__FUNC_GPIO213 (MTK_PIN_NO(213) | 0) +-#define MT6797_GPIO213__FUNC_BPI_BUS1 (MTK_PIN_NO(213) | 1) +-#define MT6797_GPIO213__FUNC_DBG_MON_B20 (MTK_PIN_NO(213) | 7) +- +-#define MT6797_GPIO214__FUNC_GPIO214 (MTK_PIN_NO(214) | 0) +-#define MT6797_GPIO214__FUNC_BPI_BUS2 (MTK_PIN_NO(214) | 1) +-#define MT6797_GPIO214__FUNC_DBG_MON_B21 (MTK_PIN_NO(214) | 7) +- +-#define MT6797_GPIO215__FUNC_GPIO215 (MTK_PIN_NO(215) | 0) +-#define MT6797_GPIO215__FUNC_BPI_BUS3 (MTK_PIN_NO(215) | 1) +-#define MT6797_GPIO215__FUNC_DBG_MON_B22 (MTK_PIN_NO(215) | 7) +- +-#define MT6797_GPIO216__FUNC_GPIO216 (MTK_PIN_NO(216) | 0) +-#define MT6797_GPIO216__FUNC_MIPI2_SCLK (MTK_PIN_NO(216) | 1) +-#define MT6797_GPIO216__FUNC_DBG_MON_B23 (MTK_PIN_NO(216) | 7) +- +-#define MT6797_GPIO217__FUNC_GPIO217 (MTK_PIN_NO(217) | 0) +-#define MT6797_GPIO217__FUNC_MIPI2_SDATA (MTK_PIN_NO(217) | 1) +-#define MT6797_GPIO217__FUNC_DBG_MON_B24 (MTK_PIN_NO(217) | 7) +- +-#define MT6797_GPIO218__FUNC_GPIO218 (MTK_PIN_NO(218) | 0) +-#define MT6797_GPIO218__FUNC_MIPI3_SCLK (MTK_PIN_NO(218) | 1) +-#define MT6797_GPIO218__FUNC_DBG_MON_B25 (MTK_PIN_NO(218) | 7) +- +-#define MT6797_GPIO219__FUNC_GPIO219 (MTK_PIN_NO(219) | 0) +-#define MT6797_GPIO219__FUNC_MIPI3_SDATA (MTK_PIN_NO(219) | 1) +-#define MT6797_GPIO219__FUNC_DBG_MON_B26 (MTK_PIN_NO(219) | 7) +- +-#define MT6797_GPIO220__FUNC_GPIO220 (MTK_PIN_NO(220) | 0) +-#define MT6797_GPIO220__FUNC_CONN_WF_IP (MTK_PIN_NO(220) | 1) +- +-#define MT6797_GPIO221__FUNC_GPIO221 (MTK_PIN_NO(221) | 0) +-#define MT6797_GPIO221__FUNC_CONN_WF_IN (MTK_PIN_NO(221) | 1) +- +-#define MT6797_GPIO222__FUNC_GPIO222 (MTK_PIN_NO(222) | 0) +-#define MT6797_GPIO222__FUNC_CONN_WF_QP (MTK_PIN_NO(222) | 1) +- +-#define MT6797_GPIO223__FUNC_GPIO223 (MTK_PIN_NO(223) | 0) +-#define MT6797_GPIO223__FUNC_CONN_WF_QN (MTK_PIN_NO(223) | 1) +- +-#define MT6797_GPIO224__FUNC_GPIO224 (MTK_PIN_NO(224) | 0) +-#define MT6797_GPIO224__FUNC_CONN_BT_IP (MTK_PIN_NO(224) | 1) +- +-#define MT6797_GPIO225__FUNC_GPIO225 (MTK_PIN_NO(225) | 0) +-#define MT6797_GPIO225__FUNC_CONN_BT_IN (MTK_PIN_NO(225) | 1) +- +-#define MT6797_GPIO226__FUNC_GPIO226 (MTK_PIN_NO(226) | 0) +-#define MT6797_GPIO226__FUNC_CONN_BT_QP (MTK_PIN_NO(226) | 1) +- +-#define MT6797_GPIO227__FUNC_GPIO227 (MTK_PIN_NO(227) | 0) +-#define MT6797_GPIO227__FUNC_CONN_BT_QN (MTK_PIN_NO(227) | 1) +- +-#define MT6797_GPIO228__FUNC_GPIO228 (MTK_PIN_NO(228) | 0) +-#define MT6797_GPIO228__FUNC_CONN_GPS_IP (MTK_PIN_NO(228) | 1) +- +-#define MT6797_GPIO229__FUNC_GPIO229 (MTK_PIN_NO(229) | 0) +-#define MT6797_GPIO229__FUNC_CONN_GPS_IN (MTK_PIN_NO(229) | 1) +- +-#define MT6797_GPIO230__FUNC_GPIO230 (MTK_PIN_NO(230) | 0) +-#define MT6797_GPIO230__FUNC_CONN_GPS_QP (MTK_PIN_NO(230) | 1) +- +-#define MT6797_GPIO231__FUNC_GPIO231 (MTK_PIN_NO(231) | 0) +-#define MT6797_GPIO231__FUNC_CONN_GPS_QN (MTK_PIN_NO(231) | 1) +- +-#define MT6797_GPIO232__FUNC_GPIO232 (MTK_PIN_NO(232) | 0) +-#define MT6797_GPIO232__FUNC_URXD1 (MTK_PIN_NO(232) | 1) +-#define MT6797_GPIO232__FUNC_UTXD1 (MTK_PIN_NO(232) | 2) +-#define MT6797_GPIO232__FUNC_MD_URXD0 (MTK_PIN_NO(232) | 3) +-#define MT6797_GPIO232__FUNC_MD_URXD1 (MTK_PIN_NO(232) | 4) +-#define MT6797_GPIO232__FUNC_MD_URXD2 (MTK_PIN_NO(232) | 5) +-#define MT6797_GPIO232__FUNC_C2K_URXD0 (MTK_PIN_NO(232) | 6) +-#define MT6797_GPIO232__FUNC_C2K_URXD1 (MTK_PIN_NO(232) | 7) +- +-#define MT6797_GPIO233__FUNC_GPIO233 (MTK_PIN_NO(233) | 0) +-#define MT6797_GPIO233__FUNC_UTXD1 (MTK_PIN_NO(233) | 1) +-#define MT6797_GPIO233__FUNC_URXD1 (MTK_PIN_NO(233) | 2) +-#define MT6797_GPIO233__FUNC_MD_UTXD0 (MTK_PIN_NO(233) | 3) +-#define MT6797_GPIO233__FUNC_MD_UTXD1 (MTK_PIN_NO(233) | 4) +-#define MT6797_GPIO233__FUNC_MD_UTXD2 (MTK_PIN_NO(233) | 5) +-#define MT6797_GPIO233__FUNC_C2K_UTXD0 (MTK_PIN_NO(233) | 6) +-#define MT6797_GPIO233__FUNC_C2K_UTXD1 (MTK_PIN_NO(233) | 7) +- +-#define MT6797_GPIO234__FUNC_GPIO234 (MTK_PIN_NO(234) | 0) +-#define MT6797_GPIO234__FUNC_SPI1_CLK_B (MTK_PIN_NO(234) | 1) +-#define MT6797_GPIO234__FUNC_TP_UTXD1_AO (MTK_PIN_NO(234) | 2) +-#define MT6797_GPIO234__FUNC_SCL4_1 (MTK_PIN_NO(234) | 3) +-#define MT6797_GPIO234__FUNC_UTXD0 (MTK_PIN_NO(234) | 4) +-#define MT6797_GPIO234__FUNC_PWM_A (MTK_PIN_NO(234) | 6) +-#define MT6797_GPIO234__FUNC_DBG_MON_A23 (MTK_PIN_NO(234) | 7) +- +-#define MT6797_GPIO235__FUNC_GPIO235 (MTK_PIN_NO(235) | 0) +-#define MT6797_GPIO235__FUNC_SPI1_MI_B (MTK_PIN_NO(235) | 1) +-#define MT6797_GPIO235__FUNC_SPI1_MO_B (MTK_PIN_NO(235) | 2) +-#define MT6797_GPIO235__FUNC_SDA4_1 (MTK_PIN_NO(235) | 3) +-#define MT6797_GPIO235__FUNC_URXD0 (MTK_PIN_NO(235) | 4) +-#define MT6797_GPIO235__FUNC_CLKM0 (MTK_PIN_NO(235) | 6) +-#define MT6797_GPIO235__FUNC_DBG_MON_A24 (MTK_PIN_NO(235) | 7) +- +-#define MT6797_GPIO236__FUNC_GPIO236 (MTK_PIN_NO(236) | 0) +-#define MT6797_GPIO236__FUNC_SPI1_MO_B (MTK_PIN_NO(236) | 1) +-#define MT6797_GPIO236__FUNC_SPI1_MI_B (MTK_PIN_NO(236) | 2) +-#define MT6797_GPIO236__FUNC_SCL5_1 (MTK_PIN_NO(236) | 3) +-#define MT6797_GPIO236__FUNC_URTS0 (MTK_PIN_NO(236) | 4) +-#define MT6797_GPIO236__FUNC_PWM_B (MTK_PIN_NO(236) | 6) +-#define MT6797_GPIO236__FUNC_DBG_MON_A25 (MTK_PIN_NO(236) | 7) +- +-#define MT6797_GPIO237__FUNC_GPIO237 (MTK_PIN_NO(237) | 0) +-#define MT6797_GPIO237__FUNC_SPI1_CS_B (MTK_PIN_NO(237) | 1) +-#define MT6797_GPIO237__FUNC_TP_URXD1_AO (MTK_PIN_NO(237) | 2) +-#define MT6797_GPIO237__FUNC_SDA5_1 (MTK_PIN_NO(237) | 3) +-#define MT6797_GPIO237__FUNC_UCTS0 (MTK_PIN_NO(237) | 4) +-#define MT6797_GPIO237__FUNC_CLKM1 (MTK_PIN_NO(237) | 6) +-#define MT6797_GPIO237__FUNC_DBG_MON_A26 (MTK_PIN_NO(237) | 7) +- +-#define MT6797_GPIO238__FUNC_GPIO238 (MTK_PIN_NO(238) | 0) +-#define MT6797_GPIO238__FUNC_SDA4_0 (MTK_PIN_NO(238) | 1) +- +-#define MT6797_GPIO239__FUNC_GPIO239 (MTK_PIN_NO(239) | 0) +-#define MT6797_GPIO239__FUNC_SCL4_0 (MTK_PIN_NO(239) | 1) +- +-#define MT6797_GPIO240__FUNC_GPIO240 (MTK_PIN_NO(240) | 0) +-#define MT6797_GPIO240__FUNC_SDA5_0 (MTK_PIN_NO(240) | 1) +- +-#define MT6797_GPIO241__FUNC_GPIO241 (MTK_PIN_NO(241) | 0) +-#define MT6797_GPIO241__FUNC_SCL5_0 (MTK_PIN_NO(241) | 1) +- +-#define MT6797_GPIO242__FUNC_GPIO242 (MTK_PIN_NO(242) | 0) +-#define MT6797_GPIO242__FUNC_SPI2_CLK_B (MTK_PIN_NO(242) | 1) +-#define MT6797_GPIO242__FUNC_TP_UTXD2_AO (MTK_PIN_NO(242) | 2) +-#define MT6797_GPIO242__FUNC_SCL4_2 (MTK_PIN_NO(242) | 3) +-#define MT6797_GPIO242__FUNC_UTXD1 (MTK_PIN_NO(242) | 4) +-#define MT6797_GPIO242__FUNC_URTS3 (MTK_PIN_NO(242) | 5) +-#define MT6797_GPIO242__FUNC_PWM_C (MTK_PIN_NO(242) | 6) +-#define MT6797_GPIO242__FUNC_DBG_MON_A27 (MTK_PIN_NO(242) | 7) +- +-#define MT6797_GPIO243__FUNC_GPIO243 (MTK_PIN_NO(243) | 0) +-#define MT6797_GPIO243__FUNC_SPI2_MI_B (MTK_PIN_NO(243) | 1) +-#define MT6797_GPIO243__FUNC_SPI2_MO_B (MTK_PIN_NO(243) | 2) +-#define MT6797_GPIO243__FUNC_SDA4_2 (MTK_PIN_NO(243) | 3) +-#define MT6797_GPIO243__FUNC_URXD1 (MTK_PIN_NO(243) | 4) +-#define MT6797_GPIO243__FUNC_UCTS3 (MTK_PIN_NO(243) | 5) +-#define MT6797_GPIO243__FUNC_CLKM2 (MTK_PIN_NO(243) | 6) +-#define MT6797_GPIO243__FUNC_DBG_MON_A28 (MTK_PIN_NO(243) | 7) +- +-#define MT6797_GPIO244__FUNC_GPIO244 (MTK_PIN_NO(244) | 0) +-#define MT6797_GPIO244__FUNC_SPI2_MO_B (MTK_PIN_NO(244) | 1) +-#define MT6797_GPIO244__FUNC_SPI2_MI_B (MTK_PIN_NO(244) | 2) +-#define MT6797_GPIO244__FUNC_SCL5_2 (MTK_PIN_NO(244) | 3) +-#define MT6797_GPIO244__FUNC_URTS1 (MTK_PIN_NO(244) | 4) +-#define MT6797_GPIO244__FUNC_UTXD3 (MTK_PIN_NO(244) | 5) +-#define MT6797_GPIO244__FUNC_PWM_D (MTK_PIN_NO(244) | 6) +-#define MT6797_GPIO244__FUNC_DBG_MON_A29 (MTK_PIN_NO(244) | 7) +- +-#define MT6797_GPIO245__FUNC_GPIO245 (MTK_PIN_NO(245) | 0) +-#define MT6797_GPIO245__FUNC_SPI2_CS_B (MTK_PIN_NO(245) | 1) +-#define MT6797_GPIO245__FUNC_TP_URXD2_AO (MTK_PIN_NO(245) | 2) +-#define MT6797_GPIO245__FUNC_SDA5_2 (MTK_PIN_NO(245) | 3) +-#define MT6797_GPIO245__FUNC_UCTS1 (MTK_PIN_NO(245) | 4) +-#define MT6797_GPIO245__FUNC_URXD3 (MTK_PIN_NO(245) | 5) +-#define MT6797_GPIO245__FUNC_CLKM3 (MTK_PIN_NO(245) | 6) +-#define MT6797_GPIO245__FUNC_DBG_MON_A30 (MTK_PIN_NO(245) | 7) +- +-#define MT6797_GPIO246__FUNC_GPIO246 (MTK_PIN_NO(246) | 0) +-#define MT6797_GPIO246__FUNC_I2S1_LRCK (MTK_PIN_NO(246) | 1) +-#define MT6797_GPIO246__FUNC_I2S2_LRCK (MTK_PIN_NO(246) | 2) +-#define MT6797_GPIO246__FUNC_I2S0_LRCK (MTK_PIN_NO(246) | 3) +-#define MT6797_GPIO246__FUNC_I2S3_LRCK (MTK_PIN_NO(246) | 4) +-#define MT6797_GPIO246__FUNC_PCM0_SYNC (MTK_PIN_NO(246) | 5) +-#define MT6797_GPIO246__FUNC_SPI5_CLK_C (MTK_PIN_NO(246) | 6) +-#define MT6797_GPIO246__FUNC_DBG_MON_A31 (MTK_PIN_NO(246) | 7) +- +-#define MT6797_GPIO247__FUNC_GPIO247 (MTK_PIN_NO(247) | 0) +-#define MT6797_GPIO247__FUNC_I2S1_BCK (MTK_PIN_NO(247) | 1) +-#define MT6797_GPIO247__FUNC_I2S2_BCK (MTK_PIN_NO(247) | 2) +-#define MT6797_GPIO247__FUNC_I2S0_BCK (MTK_PIN_NO(247) | 3) +-#define MT6797_GPIO247__FUNC_I2S3_BCK (MTK_PIN_NO(247) | 4) +-#define MT6797_GPIO247__FUNC_PCM0_CLK (MTK_PIN_NO(247) | 5) +-#define MT6797_GPIO247__FUNC_SPI5_MI_C (MTK_PIN_NO(247) | 6) +-#define MT6797_GPIO247__FUNC_DBG_MON_A32 (MTK_PIN_NO(247) | 7) +- +-#define MT6797_GPIO248__FUNC_GPIO248 (MTK_PIN_NO(248) | 0) +-/* #define MT6797_GPIO248__FUNC_I2S2_DI (MTK_PIN_NO(248) | 1) */ +-#define MT6797_GPIO248__FUNC_I2S2_DI (MTK_PIN_NO(248) | 2) +-/* #define MT6797_GPIO248__FUNC_I2S0_DI (MTK_PIN_NO(248) | 3) */ +-#define MT6797_GPIO248__FUNC_I2S0_DI (MTK_PIN_NO(248) | 4) +-#define MT6797_GPIO248__FUNC_PCM0_DI (MTK_PIN_NO(248) | 5) +-#define MT6797_GPIO248__FUNC_SPI5_CS_C (MTK_PIN_NO(248) | 6) +- +-#define MT6797_GPIO249__FUNC_GPIO249 (MTK_PIN_NO(249) | 0) +-/* #define MT6797_GPIO249__FUNC_I2S1_DO (MTK_PIN_NO(249) | 1) */ +-#define MT6797_GPIO249__FUNC_I2S1_DO (MTK_PIN_NO(249) | 2) +-/* #define MT6797_GPIO249__FUNC_I2S3_DO (MTK_PIN_NO(249) | 3) */ +-#define MT6797_GPIO249__FUNC_I2S3_DO (MTK_PIN_NO(249) | 4) +-#define MT6797_GPIO249__FUNC_PCM0_DO (MTK_PIN_NO(249) | 5) +-#define MT6797_GPIO249__FUNC_SPI5_MO_C (MTK_PIN_NO(249) | 6) +-#define MT6797_GPIO249__FUNC_TRAP_SRAM_PWR_BYPASS (MTK_PIN_NO(249) | 7) +- +-#define MT6797_GPIO250__FUNC_GPIO250 (MTK_PIN_NO(250) | 0) +-#define MT6797_GPIO250__FUNC_SPI3_MI (MTK_PIN_NO(250) | 1) +-#define MT6797_GPIO250__FUNC_SPI3_MO (MTK_PIN_NO(250) | 2) +-#define MT6797_GPIO250__FUNC_IRTX_OUT (MTK_PIN_NO(250) | 3) +-#define MT6797_GPIO250__FUNC_TP_URXD1_AO (MTK_PIN_NO(250) | 6) +-#define MT6797_GPIO250__FUNC_DROP_ZONE (MTK_PIN_NO(250) | 7) +- +-#define MT6797_GPIO251__FUNC_GPIO251 (MTK_PIN_NO(251) | 0) +-#define MT6797_GPIO251__FUNC_SPI3_MO (MTK_PIN_NO(251) | 1) +-#define MT6797_GPIO251__FUNC_SPI3_MI (MTK_PIN_NO(251) | 2) +-#define MT6797_GPIO251__FUNC_CMFLASH (MTK_PIN_NO(251) | 3) +-#define MT6797_GPIO251__FUNC_TP_UTXD1_AO (MTK_PIN_NO(251) | 6) +-#define MT6797_GPIO251__FUNC_C2K_RTCK (MTK_PIN_NO(251) | 7) +- +-#define MT6797_GPIO252__FUNC_GPIO252 (MTK_PIN_NO(252) | 0) +-#define MT6797_GPIO252__FUNC_SPI3_CLK (MTK_PIN_NO(252) | 1) +-#define MT6797_GPIO252__FUNC_SCL0_4 (MTK_PIN_NO(252) | 2) +-#define MT6797_GPIO252__FUNC_PWM_D (MTK_PIN_NO(252) | 3) +-#define MT6797_GPIO252__FUNC_C2K_TMS (MTK_PIN_NO(252) | 7) +- +-#define MT6797_GPIO253__FUNC_GPIO253 (MTK_PIN_NO(253) | 0) +-#define MT6797_GPIO253__FUNC_SPI3_CS (MTK_PIN_NO(253) | 1) +-#define MT6797_GPIO253__FUNC_SDA0_4 (MTK_PIN_NO(253) | 2) +-#define MT6797_GPIO253__FUNC_PWM_A (MTK_PIN_NO(253) | 3) +-#define MT6797_GPIO253__FUNC_C2K_TCK (MTK_PIN_NO(253) | 7) +- +-#define MT6797_GPIO254__FUNC_GPIO254 (MTK_PIN_NO(254) | 0) +-#define MT6797_GPIO254__FUNC_I2S1_MCK (MTK_PIN_NO(254) | 1) +-#define MT6797_GPIO254__FUNC_I2S2_MCK (MTK_PIN_NO(254) | 2) +-#define MT6797_GPIO254__FUNC_I2S0_MCK (MTK_PIN_NO(254) | 3) +-#define MT6797_GPIO254__FUNC_I2S3_MCK (MTK_PIN_NO(254) | 4) +-#define MT6797_GPIO254__FUNC_CLKM0 (MTK_PIN_NO(254) | 5) +-#define MT6797_GPIO254__FUNC_C2K_TDI (MTK_PIN_NO(254) | 7) +- +-#define MT6797_GPIO255__FUNC_GPIO255 (MTK_PIN_NO(255) | 0) +-#define MT6797_GPIO255__FUNC_CLKM1 (MTK_PIN_NO(255) | 1) +-#define MT6797_GPIO255__FUNC_DISP_PWM (MTK_PIN_NO(255) | 2) +-#define MT6797_GPIO255__FUNC_PWM_B (MTK_PIN_NO(255) | 3) +-#define MT6797_GPIO255__FUNC_TP_GPIO1_AO (MTK_PIN_NO(255) | 6) +-#define MT6797_GPIO255__FUNC_C2K_TDO (MTK_PIN_NO(255) | 7) +- +-#define MT6797_GPIO256__FUNC_GPIO256 (MTK_PIN_NO(256) | 0) +-#define MT6797_GPIO256__FUNC_CLKM2 (MTK_PIN_NO(256) | 1) +-#define MT6797_GPIO256__FUNC_IRTX_OUT (MTK_PIN_NO(256) | 2) +-#define MT6797_GPIO256__FUNC_PWM_C (MTK_PIN_NO(256) | 3) +-#define MT6797_GPIO256__FUNC_TP_GPIO0_AO (MTK_PIN_NO(256) | 6) +-#define MT6797_GPIO256__FUNC_C2K_NTRST (MTK_PIN_NO(256) | 7) +- +-#define MT6797_GPIO257__FUNC_GPIO257 (MTK_PIN_NO(257) | 0) +-#define MT6797_GPIO257__FUNC_IO_JTAG_TMS (MTK_PIN_NO(257) | 1) +-#define MT6797_GPIO257__FUNC_LTE_JTAG_TMS (MTK_PIN_NO(257) | 2) +-#define MT6797_GPIO257__FUNC_DFD_TMS (MTK_PIN_NO(257) | 3) +-#define MT6797_GPIO257__FUNC_DAP_SIB1_SWD (MTK_PIN_NO(257) | 4) +-#define MT6797_GPIO257__FUNC_ANC_JTAG_TMS (MTK_PIN_NO(257) | 5) +-#define MT6797_GPIO257__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(257) | 6) +-#define MT6797_GPIO257__FUNC_C2K_DM_OTMS (MTK_PIN_NO(257) | 7) +- +-#define MT6797_GPIO258__FUNC_GPIO258 (MTK_PIN_NO(258) | 0) +-#define MT6797_GPIO258__FUNC_IO_JTAG_TCK (MTK_PIN_NO(258) | 1) +-#define MT6797_GPIO258__FUNC_LTE_JTAG_TCK (MTK_PIN_NO(258) | 2) +-#define MT6797_GPIO258__FUNC_DFD_TCK_XI (MTK_PIN_NO(258) | 3) +-#define MT6797_GPIO258__FUNC_DAP_SIB1_SWCK (MTK_PIN_NO(258) | 4) +-#define MT6797_GPIO258__FUNC_ANC_JTAG_TCK (MTK_PIN_NO(258) | 5) +-#define MT6797_GPIO258__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(258) | 6) +-#define MT6797_GPIO258__FUNC_C2K_DM_OTCK (MTK_PIN_NO(258) | 7) +- +-#define MT6797_GPIO259__FUNC_GPIO259 (MTK_PIN_NO(259) | 0) +-#define MT6797_GPIO259__FUNC_IO_JTAG_TDI (MTK_PIN_NO(259) | 1) +-#define MT6797_GPIO259__FUNC_LTE_JTAG_TDI (MTK_PIN_NO(259) | 2) +-#define MT6797_GPIO259__FUNC_DFD_TDI (MTK_PIN_NO(259) | 3) +-#define MT6797_GPIO259__FUNC_ANC_JTAG_TDI (MTK_PIN_NO(259) | 5) +-#define MT6797_GPIO259__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(259) | 6) +-#define MT6797_GPIO259__FUNC_C2K_DM_OTDI (MTK_PIN_NO(259) | 7) +- +-#define MT6797_GPIO260__FUNC_GPIO260 (MTK_PIN_NO(260) | 0) +-#define MT6797_GPIO260__FUNC_IO_JTAG_TDO (MTK_PIN_NO(260) | 1) +-#define MT6797_GPIO260__FUNC_LTE_JTAG_TDO (MTK_PIN_NO(260) | 2) +-#define MT6797_GPIO260__FUNC_DFD_TDO (MTK_PIN_NO(260) | 3) +-#define MT6797_GPIO260__FUNC_ANC_JTAG_TDO (MTK_PIN_NO(260) | 5) +-#define MT6797_GPIO260__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(260) | 6) +-#define MT6797_GPIO260__FUNC_C2K_DM_OTDO (MTK_PIN_NO(260) | 7) +- +-#define MT6797_GPIO261__FUNC_GPIO261 (MTK_PIN_NO(261) | 0) +-#define MT6797_GPIO261__FUNC_LTE_JTAG_TRSTN (MTK_PIN_NO(261) | 2) +-#define MT6797_GPIO261__FUNC_DFD_NTRST (MTK_PIN_NO(261) | 3) +-#define MT6797_GPIO261__FUNC_ANC_JTAG_TRSTN (MTK_PIN_NO(261) | 5) +-#define MT6797_GPIO261__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(261) | 6) +-#define MT6797_GPIO261__FUNC_C2K_DM_JTINTP (MTK_PIN_NO(261) | 7) +- +-#endif /* __DTS_MT6797_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt7623-pinfunc.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt7623-pinfunc.h +deleted file mode 100644 +index 604fe781c465..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt7623-pinfunc.h ++++ /dev/null +@@ -1,651 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DTS_MT7623_PINFUNC_H +-#define __DTS_MT7623_PINFUNC_H +- +-#include +- +-#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +-#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1) +-#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2) +- +-#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +-#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1) +-#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2) +- +-#define MT7623_PIN_2_PWRAP_INT_FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +-#define MT7623_PIN_2_PWRAP_INT_FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1) +- +-#define MT7623_PIN_3_PWRAP_SPI0_CK_FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +-#define MT7623_PIN_3_PWRAP_SPI0_CK_FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1) +- +-#define MT7623_PIN_4_PWRAP_SPI0_CSN_FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +-#define MT7623_PIN_4_PWRAP_SPI0_CSN_FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1) +- +-#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +-#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1) +-#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 5) +- +-#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +-#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1) +-#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 5) +- +-#define MT7623_PIN_7_SPI1_CSN_FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +-#define MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS (MTK_PIN_NO(7) | 1) +-#define MT7623_PIN_7_SPI1_CSN_FUNC_KCOL0 (MTK_PIN_NO(7) | 4) +- +-#define MT7623_PIN_8_SPI1_MI_FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +-#define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI (MTK_PIN_NO(8) | 1) +-#define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MO (MTK_PIN_NO(8) | 2) +-#define MT7623_PIN_8_SPI1_MI_FUNC_KCOL1 (MTK_PIN_NO(8) | 4) +- +-#define MT7623_PIN_9_SPI1_MO_FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +-#define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO (MTK_PIN_NO(9) | 1) +-#define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MI (MTK_PIN_NO(9) | 2) +-#define MT7623_PIN_9_SPI1_MO_FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3) +-#define MT7623_PIN_9_SPI1_MO_FUNC_KCOL2 (MTK_PIN_NO(9) | 4) +- +-#define MT7623_PIN_10_RTC32K_CK_FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +-#define MT7623_PIN_10_RTC32K_CK_FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1) +- +-#define MT7623_PIN_11_WATCHDOG_FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +-#define MT7623_PIN_11_WATCHDOG_FUNC_WATCHDOG (MTK_PIN_NO(11) | 1) +- +-#define MT7623_PIN_12_SRCLKENA_FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +-#define MT7623_PIN_12_SRCLKENA_FUNC_SRCLKENA (MTK_PIN_NO(12) | 1) +- +-#define MT7623_PIN_13_SRCLKENAI_FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +-#define MT7623_PIN_13_SRCLKENAI_FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1) +- +-#define MT7623_PIN_14_GPIO14_FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +-#define MT7623_PIN_14_GPIO14_FUNC_URXD2 (MTK_PIN_NO(14) | 1) +-#define MT7623_PIN_14_GPIO14_FUNC_UTXD2 (MTK_PIN_NO(14) | 2) +-#define MT7623_PIN_14_GPIO14_FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5) +- +-#define MT7623_PIN_15_GPIO15_FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +-#define MT7623_PIN_15_GPIO15_FUNC_UTXD2 (MTK_PIN_NO(15) | 1) +-#define MT7623_PIN_15_GPIO15_FUNC_URXD2 (MTK_PIN_NO(15) | 2) +- +-#define MT7623_PIN_18_PCM_CLK_FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +-#define MT7623_PIN_18_PCM_CLK_FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1) +-#define MT7623_PIN_18_PCM_CLK_FUNC_MRG_CLK (MTK_PIN_NO(18) | 2) +-#define MT7623_PIN_18_PCM_CLK_FUNC_MM_TEST_CK (MTK_PIN_NO(18) | 4) +-#define MT7623_PIN_18_PCM_CLK_FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5) +-#define MT7623_PIN_18_PCM_CLK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(18) | 6) +- +-#define MT7623_PIN_19_PCM_SYNC_FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +-#define MT7623_PIN_19_PCM_SYNC_FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1) +-#define MT7623_PIN_19_PCM_SYNC_FUNC_MRG_SYNC (MTK_PIN_NO(19) | 2) +-#define MT7623_PIN_19_PCM_SYNC_FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5) +-#define MT7623_PIN_19_PCM_SYNC_FUNC_AP_PCM_SYNC (MTK_PIN_NO(19) | 6) +- +-#define MT7623_PIN_20_PCM_RX_FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +-#define MT7623_PIN_20_PCM_RX_FUNC_PCM_RX (MTK_PIN_NO(20) | 1) +-#define MT7623_PIN_20_PCM_RX_FUNC_MRG_RX (MTK_PIN_NO(20) | 2) +-#define MT7623_PIN_20_PCM_RX_FUNC_MRG_TX (MTK_PIN_NO(20) | 3) +-#define MT7623_PIN_20_PCM_RX_FUNC_PCM_TX (MTK_PIN_NO(20) | 4) +-#define MT7623_PIN_20_PCM_RX_FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5) +-#define MT7623_PIN_20_PCM_RX_FUNC_AP_PCM_RX (MTK_PIN_NO(20) | 6) +- +-#define MT7623_PIN_21_PCM_TX_FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +-#define MT7623_PIN_21_PCM_TX_FUNC_PCM_TX (MTK_PIN_NO(21) | 1) +-#define MT7623_PIN_21_PCM_TX_FUNC_MRG_TX (MTK_PIN_NO(21) | 2) +-#define MT7623_PIN_21_PCM_TX_FUNC_MRG_RX (MTK_PIN_NO(21) | 3) +-#define MT7623_PIN_21_PCM_TX_FUNC_PCM_RX (MTK_PIN_NO(21) | 4) +-#define MT7623_PIN_21_PCM_TX_FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5) +-#define MT7623_PIN_21_PCM_TX_FUNC_AP_PCM_TX (MTK_PIN_NO(21) | 6) +- +-#define MT7623_PIN_22_EINT0_FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +-#define MT7623_PIN_22_EINT0_FUNC_UCTS0 (MTK_PIN_NO(22) | 1) +-#define MT7623_PIN_22_EINT0_FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 2) +-#define MT7623_PIN_22_EINT0_FUNC_KCOL3 (MTK_PIN_NO(22) | 3) +-#define MT7623_PIN_22_EINT0_FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 4) +-#define MT7623_PIN_22_EINT0_FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 5) +- +-#define MT7623_PIN_23_EINT1_FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +-#define MT7623_PIN_23_EINT1_FUNC_URTS0 (MTK_PIN_NO(23) | 1) +-#define MT7623_PIN_23_EINT1_FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 2) +-#define MT7623_PIN_23_EINT1_FUNC_KCOL2 (MTK_PIN_NO(23) | 3) +-#define MT7623_PIN_23_EINT1_FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 4) +-#define MT7623_PIN_23_EINT1_FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5) +- +-#define MT7623_PIN_24_EINT2_FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +-#define MT7623_PIN_24_EINT2_FUNC_UCTS1 (MTK_PIN_NO(24) | 1) +-#define MT7623_PIN_24_EINT2_FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 2) +-#define MT7623_PIN_24_EINT2_FUNC_KCOL1 (MTK_PIN_NO(24) | 3) +-#define MT7623_PIN_24_EINT2_FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 4) +- +-#define MT7623_PIN_25_EINT3_FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +-#define MT7623_PIN_25_EINT3_FUNC_URTS1 (MTK_PIN_NO(25) | 1) +-#define MT7623_PIN_25_EINT3_FUNC_KCOL0 (MTK_PIN_NO(25) | 3) +-#define MT7623_PIN_25_EINT3_FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 4) +- +-#define MT7623_PIN_26_EINT4_FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +-#define MT7623_PIN_26_EINT4_FUNC_UCTS3 (MTK_PIN_NO(26) | 1) +-#define MT7623_PIN_26_EINT4_FUNC_DRV_VBUS_P1 (MTK_PIN_NO(26) | 2) +-#define MT7623_PIN_26_EINT4_FUNC_KROW3 (MTK_PIN_NO(26) | 3) +-#define MT7623_PIN_26_EINT4_FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 4) +-#define MT7623_PIN_26_EINT4_FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 5) +-#define MT7623_PIN_26_EINT4_FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6) +- +-#define MT7623_PIN_27_EINT5_FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +-#define MT7623_PIN_27_EINT5_FUNC_URTS3 (MTK_PIN_NO(27) | 1) +-#define MT7623_PIN_27_EINT5_FUNC_IDDIG_P1 (MTK_PIN_NO(27) | 2) +-#define MT7623_PIN_27_EINT5_FUNC_KROW2 (MTK_PIN_NO(27) | 3) +-#define MT7623_PIN_27_EINT5_FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 4) +-#define MT7623_PIN_27_EINT5_FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6) +- +-#define MT7623_PIN_28_EINT6_FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +-#define MT7623_PIN_28_EINT6_FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1) +-#define MT7623_PIN_28_EINT6_FUNC_KROW1 (MTK_PIN_NO(28) | 3) +-#define MT7623_PIN_28_EINT6_FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 4) +-#define MT7623_PIN_28_EINT6_FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6) +- +-#define MT7623_PIN_29_EINT7_FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +-#define MT7623_PIN_29_EINT7_FUNC_IDDIG (MTK_PIN_NO(29) | 1) +-#define MT7623_PIN_29_EINT7_FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2) +-#define MT7623_PIN_29_EINT7_FUNC_KROW0 (MTK_PIN_NO(29) | 3) +-#define MT7623_PIN_29_EINT7_FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 4) +-#define MT7623_PIN_29_EINT7_FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 5) +-#define MT7623_PIN_29_EINT7_FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 6) +- +-#define MT7623_PIN_33_I2S1_DATA_FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +-#define MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1) +-#define MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA_BYPS (MTK_PIN_NO(33) | 2) +-#define MT7623_PIN_33_I2S1_DATA_FUNC_PCM_TX (MTK_PIN_NO(33) | 3) +-#define MT7623_PIN_33_I2S1_DATA_FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4) +-#define MT7623_PIN_33_I2S1_DATA_FUNC_G1_RXD0 (MTK_PIN_NO(33) | 5) +-#define MT7623_PIN_33_I2S1_DATA_FUNC_AP_PCM_TX (MTK_PIN_NO(33) | 6) +- +-#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +-#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1) +-#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_PCM_RX (MTK_PIN_NO(34) | 3) +-#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_VDEC_TEST_CK (MTK_PIN_NO(34) | 4) +-#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_G1_RXD1 (MTK_PIN_NO(34) | 5) +-#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_AP_PCM_RX (MTK_PIN_NO(34) | 6) +- +-#define MT7623_PIN_35_I2S1_BCK_FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +-#define MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1) +-#define MT7623_PIN_35_I2S1_BCK_FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3) +-#define MT7623_PIN_35_I2S1_BCK_FUNC_G1_RXD2 (MTK_PIN_NO(35) | 5) +-#define MT7623_PIN_35_I2S1_BCK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(35) | 6) +- +-#define MT7623_PIN_36_I2S1_LRCK_FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +-#define MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1) +-#define MT7623_PIN_36_I2S1_LRCK_FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3) +-#define MT7623_PIN_36_I2S1_LRCK_FUNC_G1_RXD3 (MTK_PIN_NO(36) | 5) +-#define MT7623_PIN_36_I2S1_LRCK_FUNC_AP_PCM_SYNC (MTK_PIN_NO(36) | 6) +- +-#define MT7623_PIN_37_I2S1_MCLK_FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +-#define MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1) +-#define MT7623_PIN_37_I2S1_MCLK_FUNC_G1_RXDV (MTK_PIN_NO(37) | 5) +- +-#define MT7623_PIN_39_JTMS_FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +-#define MT7623_PIN_39_JTMS_FUNC_JTMS (MTK_PIN_NO(39) | 1) +-#define MT7623_PIN_39_JTMS_FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2) +-#define MT7623_PIN_39_JTMS_FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3) +-#define MT7623_PIN_39_JTMS_FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 4) +- +-#define MT7623_PIN_40_JTCK_FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +-#define MT7623_PIN_40_JTCK_FUNC_JTCK (MTK_PIN_NO(40) | 1) +-#define MT7623_PIN_40_JTCK_FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2) +-#define MT7623_PIN_40_JTCK_FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3) +-#define MT7623_PIN_40_JTCK_FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 4) +- +-#define MT7623_PIN_41_JTDI_FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +-#define MT7623_PIN_41_JTDI_FUNC_JTDI (MTK_PIN_NO(41) | 1) +-#define MT7623_PIN_41_JTDI_FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2) +-#define MT7623_PIN_41_JTDI_FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 4) +- +-#define MT7623_PIN_42_JTDO_FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +-#define MT7623_PIN_42_JTDO_FUNC_JTDO (MTK_PIN_NO(42) | 1) +-#define MT7623_PIN_42_JTDO_FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2) +-#define MT7623_PIN_42_JTDO_FUNC_DFD_TDO (MTK_PIN_NO(42) | 4) +- +-#define MT7623_PIN_43_NCLE_FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +-#define MT7623_PIN_43_NCLE_FUNC_NCLE (MTK_PIN_NO(43) | 1) +-#define MT7623_PIN_43_NCLE_FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2) +- +-#define MT7623_PIN_44_NCEB1_FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +-#define MT7623_PIN_44_NCEB1_FUNC_NCEB1 (MTK_PIN_NO(44) | 1) +-#define MT7623_PIN_44_NCEB1_FUNC_IDDIG (MTK_PIN_NO(44) | 2) +- +-#define MT7623_PIN_45_NCEB0_FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +-#define MT7623_PIN_45_NCEB0_FUNC_NCEB0 (MTK_PIN_NO(45) | 1) +-#define MT7623_PIN_45_NCEB0_FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2) +- +-#define MT7623_PIN_46_IR_FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +-#define MT7623_PIN_46_IR_FUNC_IR (MTK_PIN_NO(46) | 1) +- +-#define MT7623_PIN_47_NREB_FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +-#define MT7623_PIN_47_NREB_FUNC_NREB (MTK_PIN_NO(47) | 1) +-#define MT7623_PIN_47_NREB_FUNC_IDDIG_P1 (MTK_PIN_NO(47) | 2) +- +-#define MT7623_PIN_48_NRNB_FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +-#define MT7623_PIN_48_NRNB_FUNC_NRNB (MTK_PIN_NO(48) | 1) +-#define MT7623_PIN_48_NRNB_FUNC_DRV_VBUS_P1 (MTK_PIN_NO(48) | 2) +- +-#define MT7623_PIN_49_I2S0_DATA_FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +-#define MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1) +-#define MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA_BYPS (MTK_PIN_NO(49) | 2) +-#define MT7623_PIN_49_I2S0_DATA_FUNC_PCM_TX (MTK_PIN_NO(49) | 3) +-#define MT7623_PIN_49_I2S0_DATA_FUNC_AP_I2S_DO (MTK_PIN_NO(49) | 6) +- +-#define MT7623_PIN_53_SPI0_CSN_FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +-#define MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS (MTK_PIN_NO(53) | 1) +-#define MT7623_PIN_53_SPI0_CSN_FUNC_SPDIF (MTK_PIN_NO(53) | 3) +-#define MT7623_PIN_53_SPI0_CSN_FUNC_ADC_CK (MTK_PIN_NO(53) | 4) +-#define MT7623_PIN_53_SPI0_CSN_FUNC_PWM1 (MTK_PIN_NO(53) | 5) +- +-#define MT7623_PIN_54_SPI0_CK_FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +-#define MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK (MTK_PIN_NO(54) | 1) +-#define MT7623_PIN_54_SPI0_CK_FUNC_SPDIF_IN1 (MTK_PIN_NO(54) | 3) +-#define MT7623_PIN_54_SPI0_CK_FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4) +- +-#define MT7623_PIN_55_SPI0_MI_FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +-#define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI (MTK_PIN_NO(55) | 1) +-#define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MO (MTK_PIN_NO(55) | 2) +-#define MT7623_PIN_55_SPI0_MI_FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3) +-#define MT7623_PIN_55_SPI0_MI_FUNC_ADC_WS (MTK_PIN_NO(55) | 4) +-#define MT7623_PIN_55_SPI0_MI_FUNC_PWM2 (MTK_PIN_NO(55) | 5) +- +-#define MT7623_PIN_56_SPI0_MO_FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +-#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO (MTK_PIN_NO(56) | 1) +-#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MI (MTK_PIN_NO(56) | 2) +-#define MT7623_PIN_56_SPI0_MO_FUNC_SPDIF_IN0 (MTK_PIN_NO(56) | 3) +- +-#define MT7623_PIN_57_SDA1_FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +-#define MT7623_PIN_57_SDA1_FUNC_SDA1 (MTK_PIN_NO(57) | 1) +- +-#define MT7623_PIN_58_SCL1_FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +-#define MT7623_PIN_58_SCL1_FUNC_SCL1 (MTK_PIN_NO(58) | 1) +- +-#define MT7623_PIN_60_WB_RSTB_FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +-#define MT7623_PIN_60_WB_RSTB_FUNC_WB_RSTB (MTK_PIN_NO(60) | 1) +- +-#define MT7623_PIN_61_GPIO61_FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +-#define MT7623_PIN_61_GPIO61_FUNC_TEST_FD (MTK_PIN_NO(61) | 1) +- +-#define MT7623_PIN_62_GPIO62_FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +-#define MT7623_PIN_62_GPIO62_FUNC_TEST_FC (MTK_PIN_NO(62) | 1) +- +-#define MT7623_PIN_63_WB_SCLK_FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +-#define MT7623_PIN_63_WB_SCLK_FUNC_WB_SCLK (MTK_PIN_NO(63) | 1) +- +-#define MT7623_PIN_64_WB_SDATA_FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +-#define MT7623_PIN_64_WB_SDATA_FUNC_WB_SDATA (MTK_PIN_NO(64) | 1) +- +-#define MT7623_PIN_65_WB_SEN_FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +-#define MT7623_PIN_65_WB_SEN_FUNC_WB_SEN (MTK_PIN_NO(65) | 1) +- +-#define MT7623_PIN_66_WB_CRTL0_FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +-#define MT7623_PIN_66_WB_CRTL0_FUNC_WB_CRTL0 (MTK_PIN_NO(66) | 1) +- +-#define MT7623_PIN_67_WB_CRTL1_FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +-#define MT7623_PIN_67_WB_CRTL1_FUNC_WB_CRTL1 (MTK_PIN_NO(67) | 1) +- +-#define MT7623_PIN_68_WB_CRTL2_FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +-#define MT7623_PIN_68_WB_CRTL2_FUNC_WB_CRTL2 (MTK_PIN_NO(68) | 1) +- +-#define MT7623_PIN_69_WB_CRTL3_FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +-#define MT7623_PIN_69_WB_CRTL3_FUNC_WB_CRTL3 (MTK_PIN_NO(69) | 1) +- +-#define MT7623_PIN_70_WB_CRTL4_FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +-#define MT7623_PIN_70_WB_CRTL4_FUNC_WB_CRTL4 (MTK_PIN_NO(70) | 1) +- +-#define MT7623_PIN_71_WB_CRTL5_FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +-#define MT7623_PIN_71_WB_CRTL5_FUNC_WB_CRTL5 (MTK_PIN_NO(71) | 1) +- +-#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +-#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1) +-#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_PCM_RX (MTK_PIN_NO(72) | 3) +-#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_PWM0 (MTK_PIN_NO(72) | 4) +-#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_DISP_PWM (MTK_PIN_NO(72) | 5) +-#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_AP_I2S_DI (MTK_PIN_NO(72) | 6) +- +-#define MT7623_PIN_73_I2S0_LRCK_FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +-#define MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1) +-#define MT7623_PIN_73_I2S0_LRCK_FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3) +-#define MT7623_PIN_73_I2S0_LRCK_FUNC_AP_I2S_LRCK (MTK_PIN_NO(73) | 6) +- +-#define MT7623_PIN_74_I2S0_BCK_FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +-#define MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1) +-#define MT7623_PIN_74_I2S0_BCK_FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3) +-#define MT7623_PIN_74_I2S0_BCK_FUNC_AP_I2S_BCK (MTK_PIN_NO(74) | 6) +- +-#define MT7623_PIN_75_SDA0_FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +-#define MT7623_PIN_75_SDA0_FUNC_SDA0 (MTK_PIN_NO(75) | 1) +- +-#define MT7623_PIN_76_SCL0_FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +-#define MT7623_PIN_76_SCL0_FUNC_SCL0 (MTK_PIN_NO(76) | 1) +- +-#define MT7623_PIN_77_SDA2_FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +-#define MT7623_PIN_77_SDA2_FUNC_SDA2 (MTK_PIN_NO(77) | 1) +- +-#define MT7623_PIN_78_SCL2_FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +-#define MT7623_PIN_78_SCL2_FUNC_SCL2 (MTK_PIN_NO(78) | 1) +- +-#define MT7623_PIN_79_URXD0_FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +-#define MT7623_PIN_79_URXD0_FUNC_URXD0 (MTK_PIN_NO(79) | 1) +-#define MT7623_PIN_79_URXD0_FUNC_UTXD0 (MTK_PIN_NO(79) | 2) +- +-#define MT7623_PIN_80_UTXD0_FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +-#define MT7623_PIN_80_UTXD0_FUNC_UTXD0 (MTK_PIN_NO(80) | 1) +-#define MT7623_PIN_80_UTXD0_FUNC_URXD0 (MTK_PIN_NO(80) | 2) +- +-#define MT7623_PIN_81_URXD1_FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +-#define MT7623_PIN_81_URXD1_FUNC_URXD1 (MTK_PIN_NO(81) | 1) +-#define MT7623_PIN_81_URXD1_FUNC_UTXD1 (MTK_PIN_NO(81) | 2) +- +-#define MT7623_PIN_82_UTXD1_FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +-#define MT7623_PIN_82_UTXD1_FUNC_UTXD1 (MTK_PIN_NO(82) | 1) +-#define MT7623_PIN_82_UTXD1_FUNC_URXD1 (MTK_PIN_NO(82) | 2) +- +-#define MT7623_PIN_83_LCM_RST_FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +-#define MT7623_PIN_83_LCM_RST_FUNC_LCM_RST (MTK_PIN_NO(83) | 1) +-#define MT7623_PIN_83_LCM_RST_FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2) +- +-#define MT7623_PIN_84_DSI_TE_FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +-#define MT7623_PIN_84_DSI_TE_FUNC_DSI_TE (MTK_PIN_NO(84) | 1) +- +-#define MT7623_PIN_91_MIPI_TDN3_FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +-#define MT7623_PIN_91_MIPI_TDN3_FUNC_TDN3 (MTK_PIN_NO(91) | 1) +- +-#define MT7623_PIN_92_MIPI_TDP3_FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +-#define MT7623_PIN_92_MIPI_TDP3_FUNC_TDP3 (MTK_PIN_NO(92) | 1) +- +-#define MT7623_PIN_93_MIPI_TDN2_FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +-#define MT7623_PIN_93_MIPI_TDN2_FUNC_TDN2 (MTK_PIN_NO(93) | 1) +- +-#define MT7623_PIN_94_MIPI_TDP2_FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +-#define MT7623_PIN_94_MIPI_TDP2_FUNC_TDP2 (MTK_PIN_NO(94) | 1) +- +-#define MT7623_PIN_95_MIPI_TCN_FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +-#define MT7623_PIN_95_MIPI_TCN_FUNC_TCN (MTK_PIN_NO(95) | 1) +- +-#define MT7623_PIN_96_MIPI_TCP_FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +-#define MT7623_PIN_96_MIPI_TCP_FUNC_TCP (MTK_PIN_NO(96) | 1) +- +-#define MT7623_PIN_97_MIPI_TDN1_FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +-#define MT7623_PIN_97_MIPI_TDN1_FUNC_TDN1 (MTK_PIN_NO(97) | 1) +- +-#define MT7623_PIN_98_MIPI_TDP1_FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +-#define MT7623_PIN_98_MIPI_TDP1_FUNC_TDP1 (MTK_PIN_NO(98) | 1) +- +-#define MT7623_PIN_99_MIPI_TDN0_FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +-#define MT7623_PIN_99_MIPI_TDN0_FUNC_TDN0 (MTK_PIN_NO(99) | 1) +- +-#define MT7623_PIN_100_MIPI_TDP0_FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +-#define MT7623_PIN_100_MIPI_TDP0_FUNC_TDP0 (MTK_PIN_NO(100) | 1) +- +-#define MT7623_PIN_101_SPI2_CSN_FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +-#define MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS (MTK_PIN_NO(101) | 1) +-#define MT7623_PIN_101_SPI2_CSN_FUNC_SCL3 (MTK_PIN_NO(101) | 3) +-#define MT7623_PIN_101_SPI2_CSN_FUNC_KROW0 (MTK_PIN_NO(101) | 4) +- +-#define MT7623_PIN_102_SPI2_MI_FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +-#define MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI (MTK_PIN_NO(102) | 1) +-#define MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MO (MTK_PIN_NO(102) | 2) +-#define MT7623_PIN_102_SPI2_MI_FUNC_SDA3 (MTK_PIN_NO(102) | 3) +-#define MT7623_PIN_102_SPI2_MI_FUNC_KROW1 (MTK_PIN_NO(102) | 4) +- +-#define MT7623_PIN_103_SPI2_MO_FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +-#define MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO (MTK_PIN_NO(103) | 1) +-#define MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MI (MTK_PIN_NO(103) | 2) +-#define MT7623_PIN_103_SPI2_MO_FUNC_SCL3 (MTK_PIN_NO(103) | 3) +-#define MT7623_PIN_103_SPI2_MO_FUNC_KROW2 (MTK_PIN_NO(103) | 4) +- +-#define MT7623_PIN_104_SPI2_CK_FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +-#define MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK (MTK_PIN_NO(104) | 1) +-#define MT7623_PIN_104_SPI2_CK_FUNC_SDA3 (MTK_PIN_NO(104) | 3) +-#define MT7623_PIN_104_SPI2_CK_FUNC_KROW3 (MTK_PIN_NO(104) | 4) +- +-#define MT7623_PIN_105_MSDC1_CMD_FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +-#define MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1) +-#define MT7623_PIN_105_MSDC1_CMD_FUNC_SDA1 (MTK_PIN_NO(105) | 3) +-#define MT7623_PIN_105_MSDC1_CMD_FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6) +- +-#define MT7623_PIN_106_MSDC1_CLK_FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +-#define MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1) +-#define MT7623_PIN_106_MSDC1_CLK_FUNC_SCL1 (MTK_PIN_NO(106) | 3) +-#define MT7623_PIN_106_MSDC1_CLK_FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6) +- +-#define MT7623_PIN_107_MSDC1_DAT0_FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +-#define MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1) +-#define MT7623_PIN_107_MSDC1_DAT0_FUNC_UTXD0 (MTK_PIN_NO(107) | 5) +-#define MT7623_PIN_107_MSDC1_DAT0_FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6) +- +-#define MT7623_PIN_108_MSDC1_DAT1_FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +-#define MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1) +-#define MT7623_PIN_108_MSDC1_DAT1_FUNC_PWM0 (MTK_PIN_NO(108) | 3) +-#define MT7623_PIN_108_MSDC1_DAT1_FUNC_URXD0 (MTK_PIN_NO(108) | 5) +-#define MT7623_PIN_108_MSDC1_DAT1_FUNC_PWM1 (MTK_PIN_NO(108) | 6) +- +-#define MT7623_PIN_109_MSDC1_DAT2_FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +-#define MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1) +-#define MT7623_PIN_109_MSDC1_DAT2_FUNC_SDA2 (MTK_PIN_NO(109) | 3) +-#define MT7623_PIN_109_MSDC1_DAT2_FUNC_UTXD1 (MTK_PIN_NO(109) | 5) +-#define MT7623_PIN_109_MSDC1_DAT2_FUNC_PWM2 (MTK_PIN_NO(109) | 6) +- +-#define MT7623_PIN_110_MSDC1_DAT3_FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +-#define MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1) +-#define MT7623_PIN_110_MSDC1_DAT3_FUNC_SCL2 (MTK_PIN_NO(110) | 3) +-#define MT7623_PIN_110_MSDC1_DAT3_FUNC_URXD1 (MTK_PIN_NO(110) | 5) +-#define MT7623_PIN_110_MSDC1_DAT3_FUNC_PWM3 (MTK_PIN_NO(110) | 6) +- +-#define MT7623_PIN_111_MSDC0_DAT7_FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +-#define MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1) +-#define MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7 (MTK_PIN_NO(111) | 4) +- +-#define MT7623_PIN_112_MSDC0_DAT6_FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +-#define MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1) +-#define MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6 (MTK_PIN_NO(112) | 4) +- +-#define MT7623_PIN_113_MSDC0_DAT5_FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +-#define MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1) +-#define MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5 (MTK_PIN_NO(113) | 4) +- +-#define MT7623_PIN_114_MSDC0_DAT4_FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +-#define MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1) +-#define MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4 (MTK_PIN_NO(114) | 4) +- +-#define MT7623_PIN_115_MSDC0_RSTB_FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +-#define MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1) +-#define MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8 (MTK_PIN_NO(115) | 4) +- +-#define MT7623_PIN_116_MSDC0_CMD_FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +-#define MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1) +-#define MT7623_PIN_116_MSDC0_CMD_FUNC_NALE (MTK_PIN_NO(116) | 4) +- +-#define MT7623_PIN_117_MSDC0_CLK_FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +-#define MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1) +-#define MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB (MTK_PIN_NO(117) | 4) +- +-#define MT7623_PIN_118_MSDC0_DAT3_FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +-#define MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1) +-#define MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3 (MTK_PIN_NO(118) | 4) +- +-#define MT7623_PIN_119_MSDC0_DAT2_FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +-#define MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1) +-#define MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2 (MTK_PIN_NO(119) | 4) +- +-#define MT7623_PIN_120_MSDC0_DAT1_FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +-#define MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1) +-#define MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1 (MTK_PIN_NO(120) | 4) +- +-#define MT7623_PIN_121_MSDC0_DAT0_FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +-#define MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1) +-#define MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0 (MTK_PIN_NO(121) | 4) +-#define MT7623_PIN_121_MSDC0_DAT0_FUNC_WATCHDOG (MTK_PIN_NO(121) | 5) +- +-#define MT7623_PIN_122_GPIO122_FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +-#define MT7623_PIN_122_GPIO122_FUNC_CEC (MTK_PIN_NO(122) | 1) +-#define MT7623_PIN_122_GPIO122_FUNC_SDA2 (MTK_PIN_NO(122) | 4) +-#define MT7623_PIN_122_GPIO122_FUNC_URXD0 (MTK_PIN_NO(122) | 5) +- +-#define MT7623_PIN_123_HTPLG_FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +-#define MT7623_PIN_123_HTPLG_FUNC_HTPLG (MTK_PIN_NO(123) | 1) +-#define MT7623_PIN_123_HTPLG_FUNC_SCL2 (MTK_PIN_NO(123) | 4) +-#define MT7623_PIN_123_HTPLG_FUNC_UTXD0 (MTK_PIN_NO(123) | 5) +- +-#define MT7623_PIN_124_GPIO124_FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +-#define MT7623_PIN_124_GPIO124_FUNC_HDMISCK (MTK_PIN_NO(124) | 1) +-#define MT7623_PIN_124_GPIO124_FUNC_SDA1 (MTK_PIN_NO(124) | 4) +-#define MT7623_PIN_124_GPIO124_FUNC_PWM3 (MTK_PIN_NO(124) | 5) +- +-#define MT7623_PIN_125_GPIO125_FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +-#define MT7623_PIN_125_GPIO125_FUNC_HDMISD (MTK_PIN_NO(125) | 1) +-#define MT7623_PIN_125_GPIO125_FUNC_SCL1 (MTK_PIN_NO(125) | 4) +-#define MT7623_PIN_125_GPIO125_FUNC_PWM4 (MTK_PIN_NO(125) | 5) +- +-#define MT7623_PIN_126_I2S0_MCLK_FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +-#define MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1) +-#define MT7623_PIN_126_I2S0_MCLK_FUNC_AP_I2S_MCLK (MTK_PIN_NO(126) | 6) +- +-#define MT7623_PIN_199_SPI1_CK_FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +-#define MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK (MTK_PIN_NO(199) | 1) +- +-#define MT7623_PIN_200_URXD2_FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +-#define MT7623_PIN_200_URXD2_FUNC_URXD2 (MTK_PIN_NO(200) | 6) +- +-#define MT7623_PIN_201_UTXD2_FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +-#define MT7623_PIN_201_UTXD2_FUNC_UTXD2 (MTK_PIN_NO(201) | 6) +- +-#define MT7623_PIN_203_PWM0_FUNC_GPIO203 (MTK_PIN_NO(203) | 0) +-#define MT7623_PIN_203_PWM0_FUNC_PWM0 (MTK_PIN_NO(203) | 1) +-#define MT7623_PIN_203_PWM0_FUNC_DISP_PWM (MTK_PIN_NO(203) | 2) +- +-#define MT7623_PIN_204_PWM1_FUNC_GPIO204 (MTK_PIN_NO(204) | 0) +-#define MT7623_PIN_204_PWM1_FUNC_PWM1 (MTK_PIN_NO(204) | 1) +- +-#define MT7623_PIN_205_PWM2_FUNC_GPIO205 (MTK_PIN_NO(205) | 0) +-#define MT7623_PIN_205_PWM2_FUNC_PWM2 (MTK_PIN_NO(205) | 1) +- +-#define MT7623_PIN_206_PWM3_FUNC_GPIO206 (MTK_PIN_NO(206) | 0) +-#define MT7623_PIN_206_PWM3_FUNC_PWM3 (MTK_PIN_NO(206) | 1) +- +-#define MT7623_PIN_207_PWM4_FUNC_GPIO207 (MTK_PIN_NO(207) | 0) +-#define MT7623_PIN_207_PWM4_FUNC_PWM4 (MTK_PIN_NO(207) | 1) +- +-#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_GPIO208 (MTK_PIN_NO(208) | 0) +-#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1) +-#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_PWM0 (MTK_PIN_NO(208) | 2) +-#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 3) +-#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_DISP_PWM (MTK_PIN_NO(208) | 5) +- +-#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_GPIO209 (MTK_PIN_NO(209) | 0) +-#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1) +-#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2) +-#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 3) +-#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_PWM1 (MTK_PIN_NO(209) | 5) +- +-#define MT7623_PIN_236_EXT_SDIO3_FUNC_GPIO236 (MTK_PIN_NO(236) | 0) +-#define MT7623_PIN_236_EXT_SDIO3_FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1) +-#define MT7623_PIN_236_EXT_SDIO3_FUNC_IDDIG (MTK_PIN_NO(236) | 2) +- +-#define MT7623_PIN_237_EXT_SDIO2_FUNC_GPIO237 (MTK_PIN_NO(237) | 0) +-#define MT7623_PIN_237_EXT_SDIO2_FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1) +-#define MT7623_PIN_237_EXT_SDIO2_FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2) +- +-#define MT7623_PIN_238_EXT_SDIO1_FUNC_GPIO238 (MTK_PIN_NO(238) | 0) +-#define MT7623_PIN_238_EXT_SDIO1_FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1) +- +-#define MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239 (MTK_PIN_NO(239) | 0) +-#define MT7623_PIN_239_EXT_SDIO0_FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1) +- +-#define MT7623_PIN_240_EXT_XCS_FUNC_GPIO240 (MTK_PIN_NO(240) | 0) +-#define MT7623_PIN_240_EXT_XCS_FUNC_EXT_XCS (MTK_PIN_NO(240) | 1) +- +-#define MT7623_PIN_241_EXT_SCK_FUNC_GPIO241 (MTK_PIN_NO(241) | 0) +-#define MT7623_PIN_241_EXT_SCK_FUNC_EXT_SCK (MTK_PIN_NO(241) | 1) +- +-#define MT7623_PIN_242_URTS2_FUNC_GPIO242 (MTK_PIN_NO(242) | 0) +-#define MT7623_PIN_242_URTS2_FUNC_URTS2 (MTK_PIN_NO(242) | 1) +-#define MT7623_PIN_242_URTS2_FUNC_UTXD3 (MTK_PIN_NO(242) | 2) +-#define MT7623_PIN_242_URTS2_FUNC_URXD3 (MTK_PIN_NO(242) | 3) +-#define MT7623_PIN_242_URTS2_FUNC_SCL1 (MTK_PIN_NO(242) | 4) +- +-#define MT7623_PIN_243_UCTS2_FUNC_GPIO243 (MTK_PIN_NO(243) | 0) +-#define MT7623_PIN_243_UCTS2_FUNC_UCTS2 (MTK_PIN_NO(243) | 1) +-#define MT7623_PIN_243_UCTS2_FUNC_URXD3 (MTK_PIN_NO(243) | 2) +-#define MT7623_PIN_243_UCTS2_FUNC_UTXD3 (MTK_PIN_NO(243) | 3) +-#define MT7623_PIN_243_UCTS2_FUNC_SDA1 (MTK_PIN_NO(243) | 4) +- +-#define MT7623_PIN_250_GPIO250_FUNC_GPIO250 (MTK_PIN_NO(250) | 0) +-#define MT7623_PIN_250_GPIO250_FUNC_TEST_MD7 (MTK_PIN_NO(250) | 1) +-#define MT7623_PIN_250_GPIO250_FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 6) +- +-#define MT7623_PIN_251_GPIO251_FUNC_GPIO251 (MTK_PIN_NO(251) | 0) +-#define MT7623_PIN_251_GPIO251_FUNC_TEST_MD6 (MTK_PIN_NO(251) | 1) +-#define MT7623_PIN_251_GPIO251_FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 6) +- +-#define MT7623_PIN_252_GPIO252_FUNC_GPIO252 (MTK_PIN_NO(252) | 0) +-#define MT7623_PIN_252_GPIO252_FUNC_TEST_MD5 (MTK_PIN_NO(252) | 1) +-#define MT7623_PIN_252_GPIO252_FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 6) +- +-#define MT7623_PIN_253_GPIO253_FUNC_GPIO253 (MTK_PIN_NO(253) | 0) +-#define MT7623_PIN_253_GPIO253_FUNC_TEST_MD4 (MTK_PIN_NO(253) | 1) +-#define MT7623_PIN_253_GPIO253_FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 6) +- +-#define MT7623_PIN_254_GPIO254_FUNC_GPIO254 (MTK_PIN_NO(254) | 0) +-#define MT7623_PIN_254_GPIO254_FUNC_TEST_MD3 (MTK_PIN_NO(254) | 1) +-#define MT7623_PIN_254_GPIO254_FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 6) +- +-#define MT7623_PIN_255_GPIO255_FUNC_GPIO255 (MTK_PIN_NO(255) | 0) +-#define MT7623_PIN_255_GPIO255_FUNC_TEST_MD2 (MTK_PIN_NO(255) | 1) +-#define MT7623_PIN_255_GPIO255_FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 6) +- +-#define MT7623_PIN_256_GPIO256_FUNC_GPIO256 (MTK_PIN_NO(256) | 0) +-#define MT7623_PIN_256_GPIO256_FUNC_TEST_MD1 (MTK_PIN_NO(256) | 1) +- +-#define MT7623_PIN_257_GPIO257_FUNC_GPIO257 (MTK_PIN_NO(257) | 0) +-#define MT7623_PIN_257_GPIO257_FUNC_TEST_MD0 (MTK_PIN_NO(257) | 1) +- +-#define MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261 (MTK_PIN_NO(261) | 0) +-#define MT7623_PIN_261_MSDC1_INS_FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1) +- +-#define MT7623_PIN_262_G2_TXEN_FUNC_GPIO262 (MTK_PIN_NO(262) | 0) +-#define MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN (MTK_PIN_NO(262) | 1) +- +-#define MT7623_PIN_263_G2_TXD3_FUNC_GPIO263 (MTK_PIN_NO(263) | 0) +-#define MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1) +- +-#define MT7623_PIN_264_G2_TXD2_FUNC_GPIO264 (MTK_PIN_NO(264) | 0) +-#define MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1) +- +-#define MT7623_PIN_265_G2_TXD1_FUNC_GPIO265 (MTK_PIN_NO(265) | 0) +-#define MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1) +- +-#define MT7623_PIN_266_G2_TXD0_FUNC_GPIO266 (MTK_PIN_NO(266) | 0) +-#define MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1) +- +-#define MT7623_PIN_267_G2_TXCLK_FUNC_GPIO267 (MTK_PIN_NO(267) | 0) +-#define MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC (MTK_PIN_NO(267) | 1) +- +-#define MT7623_PIN_268_G2_RXCLK_FUNC_GPIO268 (MTK_PIN_NO(268) | 0) +-#define MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC (MTK_PIN_NO(268) | 1) +- +-#define MT7623_PIN_269_G2_RXD0_FUNC_GPIO269 (MTK_PIN_NO(269) | 0) +-#define MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1) +- +-#define MT7623_PIN_270_G2_RXD1_FUNC_GPIO270 (MTK_PIN_NO(270) | 0) +-#define MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1) +- +-#define MT7623_PIN_271_G2_RXD2_FUNC_GPIO271 (MTK_PIN_NO(271) | 0) +-#define MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1) +- +-#define MT7623_PIN_272_G2_RXD3_FUNC_GPIO272 (MTK_PIN_NO(272) | 0) +-#define MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1) +- +-#define MT7623_PIN_274_G2_RXDV_FUNC_GPIO274 (MTK_PIN_NO(274) | 0) +-#define MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV (MTK_PIN_NO(274) | 1) +- +-#define MT7623_PIN_275_G2_MDC_FUNC_GPIO275 (MTK_PIN_NO(275) | 0) +-#define MT7623_PIN_275_G2_MDC_FUNC_MDC (MTK_PIN_NO(275) | 1) +- +-#define MT7623_PIN_276_G2_MDIO_FUNC_GPIO276 (MTK_PIN_NO(276) | 0) +-#define MT7623_PIN_276_G2_MDIO_FUNC_MDIO (MTK_PIN_NO(276) | 1) +- +-#define MT7623_PIN_278_JTAG_RESET_FUNC_GPIO278 (MTK_PIN_NO(278) | 0) +-#define MT7623_PIN_278_JTAG_RESET_FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1) +- +-#endif /* __DTS_MT7623_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt8135-pinfunc.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt8135-pinfunc.h +deleted file mode 100644 +index ce0cb5a440eb..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt8135-pinfunc.h ++++ /dev/null +@@ -1,1294 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014 MediaTek Inc. +- * Author: Hongzhou.Yang +- */ +- +-#ifndef __DTS_MT8135_PINFUNC_H +-#define __DTS_MT8135_PINFUNC_H +- +-#include +- +-#define MT8135_PIN_0_MSDC0_DAT7__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +-#define MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(0) | 1) +-#define MT8135_PIN_0_MSDC0_DAT7__FUNC_EINT49 (MTK_PIN_NO(0) | 2) +-#define MT8135_PIN_0_MSDC0_DAT7__FUNC_I2SOUT_DAT (MTK_PIN_NO(0) | 3) +-#define MT8135_PIN_0_MSDC0_DAT7__FUNC_DAC_DAT_OUT (MTK_PIN_NO(0) | 4) +-#define MT8135_PIN_0_MSDC0_DAT7__FUNC_PCM1_DO (MTK_PIN_NO(0) | 5) +-#define MT8135_PIN_0_MSDC0_DAT7__FUNC_SPI1_MO (MTK_PIN_NO(0) | 6) +-#define MT8135_PIN_0_MSDC0_DAT7__FUNC_NALE (MTK_PIN_NO(0) | 7) +- +-#define MT8135_PIN_1_MSDC0_DAT6__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +-#define MT8135_PIN_1_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(1) | 1) +-#define MT8135_PIN_1_MSDC0_DAT6__FUNC_EINT48 (MTK_PIN_NO(1) | 2) +-#define MT8135_PIN_1_MSDC0_DAT6__FUNC_I2SIN_WS (MTK_PIN_NO(1) | 3) +-#define MT8135_PIN_1_MSDC0_DAT6__FUNC_DAC_WS (MTK_PIN_NO(1) | 4) +-#define MT8135_PIN_1_MSDC0_DAT6__FUNC_PCM1_WS (MTK_PIN_NO(1) | 5) +-#define MT8135_PIN_1_MSDC0_DAT6__FUNC_SPI1_CSN (MTK_PIN_NO(1) | 6) +-#define MT8135_PIN_1_MSDC0_DAT6__FUNC_NCLE (MTK_PIN_NO(1) | 7) +- +-#define MT8135_PIN_2_MSDC0_DAT5__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +-#define MT8135_PIN_2_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(2) | 1) +-#define MT8135_PIN_2_MSDC0_DAT5__FUNC_EINT47 (MTK_PIN_NO(2) | 2) +-#define MT8135_PIN_2_MSDC0_DAT5__FUNC_I2SIN_CK (MTK_PIN_NO(2) | 3) +-#define MT8135_PIN_2_MSDC0_DAT5__FUNC_DAC_CK (MTK_PIN_NO(2) | 4) +-#define MT8135_PIN_2_MSDC0_DAT5__FUNC_PCM1_CK (MTK_PIN_NO(2) | 5) +-#define MT8135_PIN_2_MSDC0_DAT5__FUNC_SPI1_CLK (MTK_PIN_NO(2) | 6) +-#define MT8135_PIN_2_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(2) | 7) +- +-#define MT8135_PIN_3_MSDC0_DAT4__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +-#define MT8135_PIN_3_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(3) | 1) +-#define MT8135_PIN_3_MSDC0_DAT4__FUNC_EINT46 (MTK_PIN_NO(3) | 2) +-#define MT8135_PIN_3_MSDC0_DAT4__FUNC_A_FUNC_CK (MTK_PIN_NO(3) | 3) +-#define MT8135_PIN_3_MSDC0_DAT4__FUNC_LSCE1B_2X (MTK_PIN_NO(3) | 6) +-#define MT8135_PIN_3_MSDC0_DAT4__FUNC_NLD5 (MTK_PIN_NO(3) | 7) +- +-#define MT8135_PIN_4_MSDC0_CMD__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +-#define MT8135_PIN_4_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(4) | 1) +-#define MT8135_PIN_4_MSDC0_CMD__FUNC_EINT41 (MTK_PIN_NO(4) | 2) +-#define MT8135_PIN_4_MSDC0_CMD__FUNC_A_FUNC_DOUT_0 (MTK_PIN_NO(4) | 3) +-#define MT8135_PIN_4_MSDC0_CMD__FUNC_USB_TEST_IO_0 (MTK_PIN_NO(4) | 5) +-#define MT8135_PIN_4_MSDC0_CMD__FUNC_LRSTB_2X (MTK_PIN_NO(4) | 6) +-#define MT8135_PIN_4_MSDC0_CMD__FUNC_NRNB (MTK_PIN_NO(4) | 7) +- +-#define MT8135_PIN_5_MSDC0_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +-#define MT8135_PIN_5_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(5) | 1) +-#define MT8135_PIN_5_MSDC0_CLK__FUNC_EINT40 (MTK_PIN_NO(5) | 2) +-#define MT8135_PIN_5_MSDC0_CLK__FUNC_A_FUNC_DOUT_1 (MTK_PIN_NO(5) | 3) +-#define MT8135_PIN_5_MSDC0_CLK__FUNC_USB_TEST_IO_1 (MTK_PIN_NO(5) | 5) +-#define MT8135_PIN_5_MSDC0_CLK__FUNC_LPTE (MTK_PIN_NO(5) | 6) +-#define MT8135_PIN_5_MSDC0_CLK__FUNC_NREB (MTK_PIN_NO(5) | 7) +- +-#define MT8135_PIN_6_MSDC0_DAT3__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +-#define MT8135_PIN_6_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(6) | 1) +-#define MT8135_PIN_6_MSDC0_DAT3__FUNC_EINT45 (MTK_PIN_NO(6) | 2) +-#define MT8135_PIN_6_MSDC0_DAT3__FUNC_A_FUNC_DOUT_2 (MTK_PIN_NO(6) | 3) +-#define MT8135_PIN_6_MSDC0_DAT3__FUNC_USB_TEST_IO_2 (MTK_PIN_NO(6) | 5) +-#define MT8135_PIN_6_MSDC0_DAT3__FUNC_LSCE0B_2X (MTK_PIN_NO(6) | 6) +-#define MT8135_PIN_6_MSDC0_DAT3__FUNC_NLD7 (MTK_PIN_NO(6) | 7) +- +-#define MT8135_PIN_7_MSDC0_DAT2__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +-#define MT8135_PIN_7_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(7) | 1) +-#define MT8135_PIN_7_MSDC0_DAT2__FUNC_EINT44 (MTK_PIN_NO(7) | 2) +-#define MT8135_PIN_7_MSDC0_DAT2__FUNC_A_FUNC_DOUT_3 (MTK_PIN_NO(7) | 3) +-#define MT8135_PIN_7_MSDC0_DAT2__FUNC_USB_TEST_IO_3 (MTK_PIN_NO(7) | 5) +-#define MT8135_PIN_7_MSDC0_DAT2__FUNC_LSA0_2X (MTK_PIN_NO(7) | 6) +-#define MT8135_PIN_7_MSDC0_DAT2__FUNC_NLD14 (MTK_PIN_NO(7) | 7) +- +-#define MT8135_PIN_8_MSDC0_DAT1__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +-#define MT8135_PIN_8_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(8) | 1) +-#define MT8135_PIN_8_MSDC0_DAT1__FUNC_EINT43 (MTK_PIN_NO(8) | 2) +-#define MT8135_PIN_8_MSDC0_DAT1__FUNC_USB_TEST_IO_4 (MTK_PIN_NO(8) | 5) +-#define MT8135_PIN_8_MSDC0_DAT1__FUNC_LSCK_2X (MTK_PIN_NO(8) | 6) +-#define MT8135_PIN_8_MSDC0_DAT1__FUNC_NLD11 (MTK_PIN_NO(8) | 7) +- +-#define MT8135_PIN_9_MSDC0_DAT0__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +-#define MT8135_PIN_9_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(9) | 1) +-#define MT8135_PIN_9_MSDC0_DAT0__FUNC_EINT42 (MTK_PIN_NO(9) | 2) +-#define MT8135_PIN_9_MSDC0_DAT0__FUNC_USB_TEST_IO_5 (MTK_PIN_NO(9) | 5) +-#define MT8135_PIN_9_MSDC0_DAT0__FUNC_LSDA_2X (MTK_PIN_NO(9) | 6) +- +-#define MT8135_PIN_10_NCEB0__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +-#define MT8135_PIN_10_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(10) | 1) +-#define MT8135_PIN_10_NCEB0__FUNC_EINT139 (MTK_PIN_NO(10) | 2) +-#define MT8135_PIN_10_NCEB0__FUNC_TESTA_OUT4 (MTK_PIN_NO(10) | 7) +- +-#define MT8135_PIN_11_NCEB1__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +-#define MT8135_PIN_11_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(11) | 1) +-#define MT8135_PIN_11_NCEB1__FUNC_EINT140 (MTK_PIN_NO(11) | 2) +-#define MT8135_PIN_11_NCEB1__FUNC_USB_DRVVBUS (MTK_PIN_NO(11) | 6) +-#define MT8135_PIN_11_NCEB1__FUNC_TESTA_OUT5 (MTK_PIN_NO(11) | 7) +- +-#define MT8135_PIN_12_NRNB__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +-#define MT8135_PIN_12_NRNB__FUNC_NRNB (MTK_PIN_NO(12) | 1) +-#define MT8135_PIN_12_NRNB__FUNC_EINT141 (MTK_PIN_NO(12) | 2) +-#define MT8135_PIN_12_NRNB__FUNC_A_FUNC_DOUT_4 (MTK_PIN_NO(12) | 3) +-#define MT8135_PIN_12_NRNB__FUNC_TESTA_OUT6 (MTK_PIN_NO(12) | 7) +- +-#define MT8135_PIN_13_NCLE__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +-#define MT8135_PIN_13_NCLE__FUNC_NCLE (MTK_PIN_NO(13) | 1) +-#define MT8135_PIN_13_NCLE__FUNC_EINT142 (MTK_PIN_NO(13) | 2) +-#define MT8135_PIN_13_NCLE__FUNC_A_FUNC_DOUT_5 (MTK_PIN_NO(13) | 3) +-#define MT8135_PIN_13_NCLE__FUNC_CM2PDN_1X (MTK_PIN_NO(13) | 4) +-#define MT8135_PIN_13_NCLE__FUNC_NALE (MTK_PIN_NO(13) | 6) +-#define MT8135_PIN_13_NCLE__FUNC_TESTA_OUT7 (MTK_PIN_NO(13) | 7) +- +-#define MT8135_PIN_14_NALE__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +-#define MT8135_PIN_14_NALE__FUNC_NALE (MTK_PIN_NO(14) | 1) +-#define MT8135_PIN_14_NALE__FUNC_EINT143 (MTK_PIN_NO(14) | 2) +-#define MT8135_PIN_14_NALE__FUNC_A_FUNC_DOUT_6 (MTK_PIN_NO(14) | 3) +-#define MT8135_PIN_14_NALE__FUNC_CM2MCLK_1X (MTK_PIN_NO(14) | 4) +-#define MT8135_PIN_14_NALE__FUNC_IRDA_RXD (MTK_PIN_NO(14) | 5) +-#define MT8135_PIN_14_NALE__FUNC_NCLE (MTK_PIN_NO(14) | 6) +-#define MT8135_PIN_14_NALE__FUNC_TESTA_OUT8 (MTK_PIN_NO(14) | 7) +- +-#define MT8135_PIN_15_NREB__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +-#define MT8135_PIN_15_NREB__FUNC_NREB (MTK_PIN_NO(15) | 1) +-#define MT8135_PIN_15_NREB__FUNC_EINT144 (MTK_PIN_NO(15) | 2) +-#define MT8135_PIN_15_NREB__FUNC_A_FUNC_DOUT_7 (MTK_PIN_NO(15) | 3) +-#define MT8135_PIN_15_NREB__FUNC_CM2RST_1X (MTK_PIN_NO(15) | 4) +-#define MT8135_PIN_15_NREB__FUNC_IRDA_TXD (MTK_PIN_NO(15) | 5) +-#define MT8135_PIN_15_NREB__FUNC_TESTA_OUT9 (MTK_PIN_NO(15) | 7) +- +-#define MT8135_PIN_16_NWEB__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +-#define MT8135_PIN_16_NWEB__FUNC_NWEB (MTK_PIN_NO(16) | 1) +-#define MT8135_PIN_16_NWEB__FUNC_EINT145 (MTK_PIN_NO(16) | 2) +-#define MT8135_PIN_16_NWEB__FUNC_A_FUNC_DIN_0 (MTK_PIN_NO(16) | 3) +-#define MT8135_PIN_16_NWEB__FUNC_CM2PCLK_1X (MTK_PIN_NO(16) | 4) +-#define MT8135_PIN_16_NWEB__FUNC_IRDA_PDN (MTK_PIN_NO(16) | 5) +-#define MT8135_PIN_16_NWEB__FUNC_TESTA_OUT10 (MTK_PIN_NO(16) | 7) +- +-#define MT8135_PIN_17_NLD0__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +-#define MT8135_PIN_17_NLD0__FUNC_NLD0 (MTK_PIN_NO(17) | 1) +-#define MT8135_PIN_17_NLD0__FUNC_EINT146 (MTK_PIN_NO(17) | 2) +-#define MT8135_PIN_17_NLD0__FUNC_A_FUNC_DIN_1 (MTK_PIN_NO(17) | 3) +-#define MT8135_PIN_17_NLD0__FUNC_CM2DAT_1X_0 (MTK_PIN_NO(17) | 4) +-#define MT8135_PIN_17_NLD0__FUNC_I2SIN_CK (MTK_PIN_NO(17) | 5) +-#define MT8135_PIN_17_NLD0__FUNC_DAC_CK (MTK_PIN_NO(17) | 6) +-#define MT8135_PIN_17_NLD0__FUNC_TESTA_OUT11 (MTK_PIN_NO(17) | 7) +- +-#define MT8135_PIN_18_NLD1__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +-#define MT8135_PIN_18_NLD1__FUNC_NLD1 (MTK_PIN_NO(18) | 1) +-#define MT8135_PIN_18_NLD1__FUNC_EINT147 (MTK_PIN_NO(18) | 2) +-#define MT8135_PIN_18_NLD1__FUNC_A_FUNC_DIN_2 (MTK_PIN_NO(18) | 3) +-#define MT8135_PIN_18_NLD1__FUNC_CM2DAT_1X_1 (MTK_PIN_NO(18) | 4) +-#define MT8135_PIN_18_NLD1__FUNC_I2SIN_WS (MTK_PIN_NO(18) | 5) +-#define MT8135_PIN_18_NLD1__FUNC_DAC_WS (MTK_PIN_NO(18) | 6) +-#define MT8135_PIN_18_NLD1__FUNC_TESTA_OUT12 (MTK_PIN_NO(18) | 7) +- +-#define MT8135_PIN_19_NLD2__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +-#define MT8135_PIN_19_NLD2__FUNC_NLD2 (MTK_PIN_NO(19) | 1) +-#define MT8135_PIN_19_NLD2__FUNC_EINT148 (MTK_PIN_NO(19) | 2) +-#define MT8135_PIN_19_NLD2__FUNC_A_FUNC_DIN_3 (MTK_PIN_NO(19) | 3) +-#define MT8135_PIN_19_NLD2__FUNC_CM2DAT_1X_2 (MTK_PIN_NO(19) | 4) +-#define MT8135_PIN_19_NLD2__FUNC_I2SOUT_DAT (MTK_PIN_NO(19) | 5) +-#define MT8135_PIN_19_NLD2__FUNC_DAC_DAT_OUT (MTK_PIN_NO(19) | 6) +-#define MT8135_PIN_19_NLD2__FUNC_TESTA_OUT13 (MTK_PIN_NO(19) | 7) +- +-#define MT8135_PIN_20_NLD3__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +-#define MT8135_PIN_20_NLD3__FUNC_NLD3 (MTK_PIN_NO(20) | 1) +-#define MT8135_PIN_20_NLD3__FUNC_EINT149 (MTK_PIN_NO(20) | 2) +-#define MT8135_PIN_20_NLD3__FUNC_A_FUNC_DIN_4 (MTK_PIN_NO(20) | 3) +-#define MT8135_PIN_20_NLD3__FUNC_CM2DAT_1X_3 (MTK_PIN_NO(20) | 4) +-#define MT8135_PIN_20_NLD3__FUNC_TESTA_OUT14 (MTK_PIN_NO(20) | 7) +- +-#define MT8135_PIN_21_NLD4__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +-#define MT8135_PIN_21_NLD4__FUNC_NLD4 (MTK_PIN_NO(21) | 1) +-#define MT8135_PIN_21_NLD4__FUNC_EINT150 (MTK_PIN_NO(21) | 2) +-#define MT8135_PIN_21_NLD4__FUNC_A_FUNC_DIN_5 (MTK_PIN_NO(21) | 3) +-#define MT8135_PIN_21_NLD4__FUNC_CM2DAT_1X_4 (MTK_PIN_NO(21) | 4) +-#define MT8135_PIN_21_NLD4__FUNC_TESTA_OUT15 (MTK_PIN_NO(21) | 7) +- +-#define MT8135_PIN_22_NLD5__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +-#define MT8135_PIN_22_NLD5__FUNC_NLD5 (MTK_PIN_NO(22) | 1) +-#define MT8135_PIN_22_NLD5__FUNC_EINT151 (MTK_PIN_NO(22) | 2) +-#define MT8135_PIN_22_NLD5__FUNC_A_FUNC_DIN_6 (MTK_PIN_NO(22) | 3) +-#define MT8135_PIN_22_NLD5__FUNC_CM2DAT_1X_5 (MTK_PIN_NO(22) | 4) +-#define MT8135_PIN_22_NLD5__FUNC_TESTA_OUT16 (MTK_PIN_NO(22) | 7) +- +-#define MT8135_PIN_23_NLD6__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +-#define MT8135_PIN_23_NLD6__FUNC_NLD6 (MTK_PIN_NO(23) | 1) +-#define MT8135_PIN_23_NLD6__FUNC_EINT152 (MTK_PIN_NO(23) | 2) +-#define MT8135_PIN_23_NLD6__FUNC_A_FUNC_DIN_7 (MTK_PIN_NO(23) | 3) +-#define MT8135_PIN_23_NLD6__FUNC_CM2DAT_1X_6 (MTK_PIN_NO(23) | 4) +-#define MT8135_PIN_23_NLD6__FUNC_TESTA_OUT17 (MTK_PIN_NO(23) | 7) +- +-#define MT8135_PIN_24_NLD7__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +-#define MT8135_PIN_24_NLD7__FUNC_NLD7 (MTK_PIN_NO(24) | 1) +-#define MT8135_PIN_24_NLD7__FUNC_EINT153 (MTK_PIN_NO(24) | 2) +-#define MT8135_PIN_24_NLD7__FUNC_A_FUNC_DIN_8 (MTK_PIN_NO(24) | 3) +-#define MT8135_PIN_24_NLD7__FUNC_CM2DAT_1X_7 (MTK_PIN_NO(24) | 4) +-#define MT8135_PIN_24_NLD7__FUNC_TESTA_OUT18 (MTK_PIN_NO(24) | 7) +- +-#define MT8135_PIN_25_NLD8__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +-#define MT8135_PIN_25_NLD8__FUNC_NLD8 (MTK_PIN_NO(25) | 1) +-#define MT8135_PIN_25_NLD8__FUNC_EINT154 (MTK_PIN_NO(25) | 2) +-#define MT8135_PIN_25_NLD8__FUNC_CM2DAT_1X_8 (MTK_PIN_NO(25) | 4) +- +-#define MT8135_PIN_26_NLD9__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +-#define MT8135_PIN_26_NLD9__FUNC_NLD9 (MTK_PIN_NO(26) | 1) +-#define MT8135_PIN_26_NLD9__FUNC_EINT155 (MTK_PIN_NO(26) | 2) +-#define MT8135_PIN_26_NLD9__FUNC_CM2DAT_1X_9 (MTK_PIN_NO(26) | 4) +-#define MT8135_PIN_26_NLD9__FUNC_PWM1 (MTK_PIN_NO(26) | 5) +- +-#define MT8135_PIN_27_NLD10__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +-#define MT8135_PIN_27_NLD10__FUNC_NLD10 (MTK_PIN_NO(27) | 1) +-#define MT8135_PIN_27_NLD10__FUNC_EINT156 (MTK_PIN_NO(27) | 2) +-#define MT8135_PIN_27_NLD10__FUNC_CM2VSYNC_1X (MTK_PIN_NO(27) | 4) +-#define MT8135_PIN_27_NLD10__FUNC_PWM2 (MTK_PIN_NO(27) | 5) +- +-#define MT8135_PIN_28_NLD11__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +-#define MT8135_PIN_28_NLD11__FUNC_NLD11 (MTK_PIN_NO(28) | 1) +-#define MT8135_PIN_28_NLD11__FUNC_EINT157 (MTK_PIN_NO(28) | 2) +-#define MT8135_PIN_28_NLD11__FUNC_CM2HSYNC_1X (MTK_PIN_NO(28) | 4) +-#define MT8135_PIN_28_NLD11__FUNC_PWM3 (MTK_PIN_NO(28) | 5) +- +-#define MT8135_PIN_29_NLD12__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +-#define MT8135_PIN_29_NLD12__FUNC_NLD12 (MTK_PIN_NO(29) | 1) +-#define MT8135_PIN_29_NLD12__FUNC_EINT158 (MTK_PIN_NO(29) | 2) +-#define MT8135_PIN_29_NLD12__FUNC_I2SIN_CK (MTK_PIN_NO(29) | 3) +-#define MT8135_PIN_29_NLD12__FUNC_DAC_CK (MTK_PIN_NO(29) | 4) +-#define MT8135_PIN_29_NLD12__FUNC_PCM1_CK (MTK_PIN_NO(29) | 5) +- +-#define MT8135_PIN_30_NLD13__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +-#define MT8135_PIN_30_NLD13__FUNC_NLD13 (MTK_PIN_NO(30) | 1) +-#define MT8135_PIN_30_NLD13__FUNC_EINT159 (MTK_PIN_NO(30) | 2) +-#define MT8135_PIN_30_NLD13__FUNC_I2SIN_WS (MTK_PIN_NO(30) | 3) +-#define MT8135_PIN_30_NLD13__FUNC_DAC_WS (MTK_PIN_NO(30) | 4) +-#define MT8135_PIN_30_NLD13__FUNC_PCM1_WS (MTK_PIN_NO(30) | 5) +- +-#define MT8135_PIN_31_NLD14__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +-#define MT8135_PIN_31_NLD14__FUNC_NLD14 (MTK_PIN_NO(31) | 1) +-#define MT8135_PIN_31_NLD14__FUNC_EINT160 (MTK_PIN_NO(31) | 2) +-#define MT8135_PIN_31_NLD14__FUNC_I2SOUT_DAT (MTK_PIN_NO(31) | 3) +-#define MT8135_PIN_31_NLD14__FUNC_DAC_DAT_OUT (MTK_PIN_NO(31) | 4) +-#define MT8135_PIN_31_NLD14__FUNC_PCM1_DO (MTK_PIN_NO(31) | 5) +- +-#define MT8135_PIN_32_NLD15__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +-#define MT8135_PIN_32_NLD15__FUNC_NLD15 (MTK_PIN_NO(32) | 1) +-#define MT8135_PIN_32_NLD15__FUNC_EINT161 (MTK_PIN_NO(32) | 2) +-#define MT8135_PIN_32_NLD15__FUNC_DISP_PWM (MTK_PIN_NO(32) | 3) +-#define MT8135_PIN_32_NLD15__FUNC_PWM4 (MTK_PIN_NO(32) | 4) +-#define MT8135_PIN_32_NLD15__FUNC_PCM1_DI (MTK_PIN_NO(32) | 5) +- +-#define MT8135_PIN_33_MSDC0_RSTB__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +-#define MT8135_PIN_33_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(33) | 1) +-#define MT8135_PIN_33_MSDC0_RSTB__FUNC_EINT50 (MTK_PIN_NO(33) | 2) +-#define MT8135_PIN_33_MSDC0_RSTB__FUNC_I2SIN_DAT (MTK_PIN_NO(33) | 3) +-#define MT8135_PIN_33_MSDC0_RSTB__FUNC_PCM1_DI (MTK_PIN_NO(33) | 5) +-#define MT8135_PIN_33_MSDC0_RSTB__FUNC_SPI1_MI (MTK_PIN_NO(33) | 6) +-#define MT8135_PIN_33_MSDC0_RSTB__FUNC_NLD10 (MTK_PIN_NO(33) | 7) +- +-#define MT8135_PIN_34_IDDIG__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +-#define MT8135_PIN_34_IDDIG__FUNC_IDDIG (MTK_PIN_NO(34) | 1) +-#define MT8135_PIN_34_IDDIG__FUNC_EINT34 (MTK_PIN_NO(34) | 2) +- +-#define MT8135_PIN_35_SCL3__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +-#define MT8135_PIN_35_SCL3__FUNC_SCL3 (MTK_PIN_NO(35) | 1) +-#define MT8135_PIN_35_SCL3__FUNC_EINT96 (MTK_PIN_NO(35) | 2) +-#define MT8135_PIN_35_SCL3__FUNC_CLKM6 (MTK_PIN_NO(35) | 3) +-#define MT8135_PIN_35_SCL3__FUNC_PWM6 (MTK_PIN_NO(35) | 4) +- +-#define MT8135_PIN_36_SDA3__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +-#define MT8135_PIN_36_SDA3__FUNC_SDA3 (MTK_PIN_NO(36) | 1) +-#define MT8135_PIN_36_SDA3__FUNC_EINT97 (MTK_PIN_NO(36) | 2) +- +-#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +-#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(37) | 1) +-#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_ADC_CK (MTK_PIN_NO(37) | 2) +-#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_HDMI_SDATA0 (MTK_PIN_NO(37) | 3) +-#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_EINT19 (MTK_PIN_NO(37) | 4) +-#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_USB_TEST_IO_6 (MTK_PIN_NO(37) | 5) +-#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_TESTA_OUT19 (MTK_PIN_NO(37) | 7) +- +-#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +-#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(38) | 1) +-#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_ADC_WS (MTK_PIN_NO(38) | 2) +-#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MISO (MTK_PIN_NO(38) | 3) +-#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_EINT21 (MTK_PIN_NO(38) | 4) +-#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_USB_TEST_IO_7 (MTK_PIN_NO(38) | 5) +-#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_TESTA_OUT20 (MTK_PIN_NO(38) | 7) +- +-#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +-#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MISO (MTK_PIN_NO(39) | 1) +-#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_ADC_DAT_IN (MTK_PIN_NO(39) | 2) +-#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(39) | 3) +-#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_EINT20 (MTK_PIN_NO(39) | 4) +-#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_USB_TEST_IO_8 (MTK_PIN_NO(39) | 5) +-#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_TESTA_OUT21 (MTK_PIN_NO(39) | 7) +- +-#define MT8135_PIN_40_DAC_CLK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +-#define MT8135_PIN_40_DAC_CLK__FUNC_DAC_CK (MTK_PIN_NO(40) | 1) +-#define MT8135_PIN_40_DAC_CLK__FUNC_EINT22 (MTK_PIN_NO(40) | 2) +-#define MT8135_PIN_40_DAC_CLK__FUNC_HDMI_SDATA1 (MTK_PIN_NO(40) | 3) +-#define MT8135_PIN_40_DAC_CLK__FUNC_USB_TEST_IO_9 (MTK_PIN_NO(40) | 5) +-#define MT8135_PIN_40_DAC_CLK__FUNC_TESTA_OUT22 (MTK_PIN_NO(40) | 7) +- +-#define MT8135_PIN_41_DAC_WS__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +-#define MT8135_PIN_41_DAC_WS__FUNC_DAC_WS (MTK_PIN_NO(41) | 1) +-#define MT8135_PIN_41_DAC_WS__FUNC_EINT24 (MTK_PIN_NO(41) | 2) +-#define MT8135_PIN_41_DAC_WS__FUNC_HDMI_SDATA2 (MTK_PIN_NO(41) | 3) +-#define MT8135_PIN_41_DAC_WS__FUNC_USB_TEST_IO_10 (MTK_PIN_NO(41) | 5) +-#define MT8135_PIN_41_DAC_WS__FUNC_TESTA_OUT23 (MTK_PIN_NO(41) | 7) +- +-#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +-#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(42) | 1) +-#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_EINT23 (MTK_PIN_NO(42) | 2) +-#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_HDMI_SDATA3 (MTK_PIN_NO(42) | 3) +-#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_USB_TEST_IO_11 (MTK_PIN_NO(42) | 5) +-#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_TESTA_OUT24 (MTK_PIN_NO(42) | 7) +- +-#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +-#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(43) | 1) +-#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_EINT29 (MTK_PIN_NO(43) | 2) +- +-#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +-#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(44) | 1) +-#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_EINT28 (MTK_PIN_NO(44) | 2) +- +-#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +-#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(45) | 1) +-#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_EINT27 (MTK_PIN_NO(45) | 2) +- +-#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +-#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(46) | 1) +-#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_EINT26 (MTK_PIN_NO(46) | 2) +- +-#define MT8135_PIN_47_PWRAP_EVENT__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +-#define MT8135_PIN_47_PWRAP_EVENT__FUNC_PWRAP_EVENT_IN (MTK_PIN_NO(47) | 1) +-#define MT8135_PIN_47_PWRAP_EVENT__FUNC_EINT25 (MTK_PIN_NO(47) | 2) +-#define MT8135_PIN_47_PWRAP_EVENT__FUNC_TESTA_OUT2 (MTK_PIN_NO(47) | 7) +- +-#define MT8135_PIN_48_RTC32K_CK__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +-#define MT8135_PIN_48_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(48) | 1) +- +-#define MT8135_PIN_49_WATCHDOG__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +-#define MT8135_PIN_49_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(49) | 1) +-#define MT8135_PIN_49_WATCHDOG__FUNC_EINT36 (MTK_PIN_NO(49) | 2) +- +-#define MT8135_PIN_50_SRCLKENA__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +-#define MT8135_PIN_50_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(50) | 1) +-#define MT8135_PIN_50_SRCLKENA__FUNC_EINT38 (MTK_PIN_NO(50) | 2) +- +-#define MT8135_PIN_51_SRCVOLTEN__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +-#define MT8135_PIN_51_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(51) | 1) +-#define MT8135_PIN_51_SRCVOLTEN__FUNC_EINT37 (MTK_PIN_NO(51) | 2) +- +-#define MT8135_PIN_52_EINT0__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +-#define MT8135_PIN_52_EINT0__FUNC_EINT0 (MTK_PIN_NO(52) | 1) +-#define MT8135_PIN_52_EINT0__FUNC_PWM1 (MTK_PIN_NO(52) | 2) +-#define MT8135_PIN_52_EINT0__FUNC_CLKM0 (MTK_PIN_NO(52) | 3) +-#define MT8135_PIN_52_EINT0__FUNC_SPDIF_OUT (MTK_PIN_NO(52) | 4) +-#define MT8135_PIN_52_EINT0__FUNC_USB_TEST_IO_12 (MTK_PIN_NO(52) | 5) +-#define MT8135_PIN_52_EINT0__FUNC_USB_SCL (MTK_PIN_NO(52) | 7) +- +-#define MT8135_PIN_53_URXD2__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +-#define MT8135_PIN_53_URXD2__FUNC_URXD2 (MTK_PIN_NO(53) | 1) +-#define MT8135_PIN_53_URXD2__FUNC_EINT83 (MTK_PIN_NO(53) | 2) +-#define MT8135_PIN_53_URXD2__FUNC_HDMI_LRCK (MTK_PIN_NO(53) | 4) +-#define MT8135_PIN_53_URXD2__FUNC_CLKM3 (MTK_PIN_NO(53) | 5) +-#define MT8135_PIN_53_URXD2__FUNC_UTXD2 (MTK_PIN_NO(53) | 7) +- +-#define MT8135_PIN_54_UTXD2__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +-#define MT8135_PIN_54_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(54) | 1) +-#define MT8135_PIN_54_UTXD2__FUNC_EINT82 (MTK_PIN_NO(54) | 2) +-#define MT8135_PIN_54_UTXD2__FUNC_HDMI_BCK_OUT (MTK_PIN_NO(54) | 4) +-#define MT8135_PIN_54_UTXD2__FUNC_CLKM2 (MTK_PIN_NO(54) | 5) +-#define MT8135_PIN_54_UTXD2__FUNC_URXD2 (MTK_PIN_NO(54) | 7) +- +-#define MT8135_PIN_55_UCTS2__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +-#define MT8135_PIN_55_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(55) | 1) +-#define MT8135_PIN_55_UCTS2__FUNC_EINT84 (MTK_PIN_NO(55) | 2) +-#define MT8135_PIN_55_UCTS2__FUNC_PWM1 (MTK_PIN_NO(55) | 5) +-#define MT8135_PIN_55_UCTS2__FUNC_URTS2 (MTK_PIN_NO(55) | 7) +- +-#define MT8135_PIN_56_URTS2__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +-#define MT8135_PIN_56_URTS2__FUNC_URTS2 (MTK_PIN_NO(56) | 1) +-#define MT8135_PIN_56_URTS2__FUNC_EINT85 (MTK_PIN_NO(56) | 2) +-#define MT8135_PIN_56_URTS2__FUNC_PWM2 (MTK_PIN_NO(56) | 5) +-#define MT8135_PIN_56_URTS2__FUNC_UCTS2 (MTK_PIN_NO(56) | 7) +- +-#define MT8135_PIN_57_JTCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +-#define MT8135_PIN_57_JTCK__FUNC_JTCK (MTK_PIN_NO(57) | 1) +-#define MT8135_PIN_57_JTCK__FUNC_EINT188 (MTK_PIN_NO(57) | 2) +-#define MT8135_PIN_57_JTCK__FUNC_DSP1_ICK (MTK_PIN_NO(57) | 3) +- +-#define MT8135_PIN_58_JTDO__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +-#define MT8135_PIN_58_JTDO__FUNC_JTDO (MTK_PIN_NO(58) | 1) +-#define MT8135_PIN_58_JTDO__FUNC_EINT190 (MTK_PIN_NO(58) | 2) +-#define MT8135_PIN_58_JTDO__FUNC_DSP2_IMS (MTK_PIN_NO(58) | 3) +- +-#define MT8135_PIN_59_JTRST_B__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +-#define MT8135_PIN_59_JTRST_B__FUNC_JTRST_B (MTK_PIN_NO(59) | 1) +-#define MT8135_PIN_59_JTRST_B__FUNC_EINT0 (MTK_PIN_NO(59) | 2) +-#define MT8135_PIN_59_JTRST_B__FUNC_DSP2_ICK (MTK_PIN_NO(59) | 3) +- +-#define MT8135_PIN_60_JTDI__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +-#define MT8135_PIN_60_JTDI__FUNC_JTDI (MTK_PIN_NO(60) | 1) +-#define MT8135_PIN_60_JTDI__FUNC_EINT189 (MTK_PIN_NO(60) | 2) +-#define MT8135_PIN_60_JTDI__FUNC_DSP1_IMS (MTK_PIN_NO(60) | 3) +- +-#define MT8135_PIN_61_JRTCK__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +-#define MT8135_PIN_61_JRTCK__FUNC_JRTCK (MTK_PIN_NO(61) | 1) +-#define MT8135_PIN_61_JRTCK__FUNC_EINT187 (MTK_PIN_NO(61) | 2) +-#define MT8135_PIN_61_JRTCK__FUNC_DSP1_ID (MTK_PIN_NO(61) | 3) +- +-#define MT8135_PIN_62_JTMS__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +-#define MT8135_PIN_62_JTMS__FUNC_JTMS (MTK_PIN_NO(62) | 1) +-#define MT8135_PIN_62_JTMS__FUNC_EINT191 (MTK_PIN_NO(62) | 2) +-#define MT8135_PIN_62_JTMS__FUNC_DSP2_ID (MTK_PIN_NO(62) | 3) +- +-#define MT8135_PIN_63_MSDC1_INSI__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +-#define MT8135_PIN_63_MSDC1_INSI__FUNC_MSDC1_INSI (MTK_PIN_NO(63) | 1) +-#define MT8135_PIN_63_MSDC1_INSI__FUNC_SCL5 (MTK_PIN_NO(63) | 3) +-#define MT8135_PIN_63_MSDC1_INSI__FUNC_PWM6 (MTK_PIN_NO(63) | 4) +-#define MT8135_PIN_63_MSDC1_INSI__FUNC_CLKM5 (MTK_PIN_NO(63) | 5) +-#define MT8135_PIN_63_MSDC1_INSI__FUNC_TESTB_OUT6 (MTK_PIN_NO(63) | 7) +- +-#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +-#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_MSDC1_SDWPI (MTK_PIN_NO(64) | 1) +-#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_EINT58 (MTK_PIN_NO(64) | 2) +-#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_SDA5 (MTK_PIN_NO(64) | 3) +-#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_PWM7 (MTK_PIN_NO(64) | 4) +-#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_CLKM6 (MTK_PIN_NO(64) | 5) +-#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_TESTB_OUT7 (MTK_PIN_NO(64) | 7) +- +-#define MT8135_PIN_65_MSDC2_INSI__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +-#define MT8135_PIN_65_MSDC2_INSI__FUNC_MSDC2_INSI (MTK_PIN_NO(65) | 1) +-#define MT8135_PIN_65_MSDC2_INSI__FUNC_USB_TEST_IO_27 (MTK_PIN_NO(65) | 5) +-#define MT8135_PIN_65_MSDC2_INSI__FUNC_TESTA_OUT3 (MTK_PIN_NO(65) | 7) +- +-#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +-#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_MSDC2_SDWPI (MTK_PIN_NO(66) | 1) +-#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_EINT66 (MTK_PIN_NO(66) | 2) +-#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_USB_TEST_IO_28 (MTK_PIN_NO(66) | 5) +- +-#define MT8135_PIN_67_URXD4__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +-#define MT8135_PIN_67_URXD4__FUNC_URXD4 (MTK_PIN_NO(67) | 1) +-#define MT8135_PIN_67_URXD4__FUNC_EINT89 (MTK_PIN_NO(67) | 2) +-#define MT8135_PIN_67_URXD4__FUNC_URXD1 (MTK_PIN_NO(67) | 3) +-#define MT8135_PIN_67_URXD4__FUNC_UTXD4 (MTK_PIN_NO(67) | 6) +-#define MT8135_PIN_67_URXD4__FUNC_TESTB_OUT10 (MTK_PIN_NO(67) | 7) +- +-#define MT8135_PIN_68_UTXD4__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +-#define MT8135_PIN_68_UTXD4__FUNC_UTXD4 (MTK_PIN_NO(68) | 1) +-#define MT8135_PIN_68_UTXD4__FUNC_EINT88 (MTK_PIN_NO(68) | 2) +-#define MT8135_PIN_68_UTXD4__FUNC_UTXD1 (MTK_PIN_NO(68) | 3) +-#define MT8135_PIN_68_UTXD4__FUNC_URXD4 (MTK_PIN_NO(68) | 6) +-#define MT8135_PIN_68_UTXD4__FUNC_TESTB_OUT11 (MTK_PIN_NO(68) | 7) +- +-#define MT8135_PIN_69_URXD1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +-#define MT8135_PIN_69_URXD1__FUNC_URXD1 (MTK_PIN_NO(69) | 1) +-#define MT8135_PIN_69_URXD1__FUNC_EINT79 (MTK_PIN_NO(69) | 2) +-#define MT8135_PIN_69_URXD1__FUNC_URXD4 (MTK_PIN_NO(69) | 3) +-#define MT8135_PIN_69_URXD1__FUNC_UTXD1 (MTK_PIN_NO(69) | 6) +-#define MT8135_PIN_69_URXD1__FUNC_TESTB_OUT24 (MTK_PIN_NO(69) | 7) +- +-#define MT8135_PIN_70_UTXD1__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +-#define MT8135_PIN_70_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(70) | 1) +-#define MT8135_PIN_70_UTXD1__FUNC_EINT78 (MTK_PIN_NO(70) | 2) +-#define MT8135_PIN_70_UTXD1__FUNC_UTXD4 (MTK_PIN_NO(70) | 3) +-#define MT8135_PIN_70_UTXD1__FUNC_URXD1 (MTK_PIN_NO(70) | 6) +-#define MT8135_PIN_70_UTXD1__FUNC_TESTB_OUT25 (MTK_PIN_NO(70) | 7) +- +-#define MT8135_PIN_71_UCTS1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +-#define MT8135_PIN_71_UCTS1__FUNC_UCTS1 (MTK_PIN_NO(71) | 1) +-#define MT8135_PIN_71_UCTS1__FUNC_EINT80 (MTK_PIN_NO(71) | 2) +-#define MT8135_PIN_71_UCTS1__FUNC_CLKM0 (MTK_PIN_NO(71) | 5) +-#define MT8135_PIN_71_UCTS1__FUNC_URTS1 (MTK_PIN_NO(71) | 6) +-#define MT8135_PIN_71_UCTS1__FUNC_TESTB_OUT31 (MTK_PIN_NO(71) | 7) +- +-#define MT8135_PIN_72_URTS1__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +-#define MT8135_PIN_72_URTS1__FUNC_URTS1 (MTK_PIN_NO(72) | 1) +-#define MT8135_PIN_72_URTS1__FUNC_EINT81 (MTK_PIN_NO(72) | 2) +-#define MT8135_PIN_72_URTS1__FUNC_CLKM1 (MTK_PIN_NO(72) | 5) +-#define MT8135_PIN_72_URTS1__FUNC_UCTS1 (MTK_PIN_NO(72) | 6) +-#define MT8135_PIN_72_URTS1__FUNC_TESTB_OUT21 (MTK_PIN_NO(72) | 7) +- +-#define MT8135_PIN_73_PWM1__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +-#define MT8135_PIN_73_PWM1__FUNC_PWM1 (MTK_PIN_NO(73) | 1) +-#define MT8135_PIN_73_PWM1__FUNC_EINT73 (MTK_PIN_NO(73) | 2) +-#define MT8135_PIN_73_PWM1__FUNC_USB_DRVVBUS (MTK_PIN_NO(73) | 5) +-#define MT8135_PIN_73_PWM1__FUNC_DISP_PWM (MTK_PIN_NO(73) | 6) +-#define MT8135_PIN_73_PWM1__FUNC_TESTB_OUT8 (MTK_PIN_NO(73) | 7) +- +-#define MT8135_PIN_74_PWM2__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +-#define MT8135_PIN_74_PWM2__FUNC_PWM2 (MTK_PIN_NO(74) | 1) +-#define MT8135_PIN_74_PWM2__FUNC_EINT74 (MTK_PIN_NO(74) | 2) +-#define MT8135_PIN_74_PWM2__FUNC_DPI33_CK (MTK_PIN_NO(74) | 3) +-#define MT8135_PIN_74_PWM2__FUNC_PWM5 (MTK_PIN_NO(74) | 4) +-#define MT8135_PIN_74_PWM2__FUNC_URXD2 (MTK_PIN_NO(74) | 5) +-#define MT8135_PIN_74_PWM2__FUNC_DISP_PWM (MTK_PIN_NO(74) | 6) +-#define MT8135_PIN_74_PWM2__FUNC_TESTB_OUT9 (MTK_PIN_NO(74) | 7) +- +-#define MT8135_PIN_75_PWM3__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +-#define MT8135_PIN_75_PWM3__FUNC_PWM3 (MTK_PIN_NO(75) | 1) +-#define MT8135_PIN_75_PWM3__FUNC_EINT75 (MTK_PIN_NO(75) | 2) +-#define MT8135_PIN_75_PWM3__FUNC_DPI33_D0 (MTK_PIN_NO(75) | 3) +-#define MT8135_PIN_75_PWM3__FUNC_PWM6 (MTK_PIN_NO(75) | 4) +-#define MT8135_PIN_75_PWM3__FUNC_UTXD2 (MTK_PIN_NO(75) | 5) +-#define MT8135_PIN_75_PWM3__FUNC_DISP_PWM (MTK_PIN_NO(75) | 6) +-#define MT8135_PIN_75_PWM3__FUNC_TESTB_OUT12 (MTK_PIN_NO(75) | 7) +- +-#define MT8135_PIN_76_PWM4__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +-#define MT8135_PIN_76_PWM4__FUNC_PWM4 (MTK_PIN_NO(76) | 1) +-#define MT8135_PIN_76_PWM4__FUNC_EINT76 (MTK_PIN_NO(76) | 2) +-#define MT8135_PIN_76_PWM4__FUNC_DPI33_D1 (MTK_PIN_NO(76) | 3) +-#define MT8135_PIN_76_PWM4__FUNC_PWM7 (MTK_PIN_NO(76) | 4) +-#define MT8135_PIN_76_PWM4__FUNC_DISP_PWM (MTK_PIN_NO(76) | 6) +-#define MT8135_PIN_76_PWM4__FUNC_TESTB_OUT13 (MTK_PIN_NO(76) | 7) +- +-#define MT8135_PIN_77_MSDC2_DAT2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +-#define MT8135_PIN_77_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(77) | 1) +-#define MT8135_PIN_77_MSDC2_DAT2__FUNC_EINT63 (MTK_PIN_NO(77) | 2) +-#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DSP2_IMS (MTK_PIN_NO(77) | 4) +-#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DPI33_D6 (MTK_PIN_NO(77) | 6) +-#define MT8135_PIN_77_MSDC2_DAT2__FUNC_TESTA_OUT25 (MTK_PIN_NO(77) | 7) +- +-#define MT8135_PIN_78_MSDC2_DAT3__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +-#define MT8135_PIN_78_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(78) | 1) +-#define MT8135_PIN_78_MSDC2_DAT3__FUNC_EINT64 (MTK_PIN_NO(78) | 2) +-#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DSP2_ID (MTK_PIN_NO(78) | 4) +-#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DPI33_D7 (MTK_PIN_NO(78) | 6) +-#define MT8135_PIN_78_MSDC2_DAT3__FUNC_TESTA_OUT26 (MTK_PIN_NO(78) | 7) +- +-#define MT8135_PIN_79_MSDC2_CMD__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +-#define MT8135_PIN_79_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(79) | 1) +-#define MT8135_PIN_79_MSDC2_CMD__FUNC_EINT60 (MTK_PIN_NO(79) | 2) +-#define MT8135_PIN_79_MSDC2_CMD__FUNC_DSP1_IMS (MTK_PIN_NO(79) | 4) +-#define MT8135_PIN_79_MSDC2_CMD__FUNC_PCM1_WS (MTK_PIN_NO(79) | 5) +-#define MT8135_PIN_79_MSDC2_CMD__FUNC_DPI33_D3 (MTK_PIN_NO(79) | 6) +-#define MT8135_PIN_79_MSDC2_CMD__FUNC_TESTA_OUT0 (MTK_PIN_NO(79) | 7) +- +-#define MT8135_PIN_80_MSDC2_CLK__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +-#define MT8135_PIN_80_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(80) | 1) +-#define MT8135_PIN_80_MSDC2_CLK__FUNC_EINT59 (MTK_PIN_NO(80) | 2) +-#define MT8135_PIN_80_MSDC2_CLK__FUNC_DSP1_ICK (MTK_PIN_NO(80) | 4) +-#define MT8135_PIN_80_MSDC2_CLK__FUNC_PCM1_CK (MTK_PIN_NO(80) | 5) +-#define MT8135_PIN_80_MSDC2_CLK__FUNC_DPI33_D2 (MTK_PIN_NO(80) | 6) +-#define MT8135_PIN_80_MSDC2_CLK__FUNC_TESTA_OUT1 (MTK_PIN_NO(80) | 7) +- +-#define MT8135_PIN_81_MSDC2_DAT1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +-#define MT8135_PIN_81_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(81) | 1) +-#define MT8135_PIN_81_MSDC2_DAT1__FUNC_EINT62 (MTK_PIN_NO(81) | 2) +-#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DSP2_ICK (MTK_PIN_NO(81) | 4) +-#define MT8135_PIN_81_MSDC2_DAT1__FUNC_PCM1_DO (MTK_PIN_NO(81) | 5) +-#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DPI33_D5 (MTK_PIN_NO(81) | 6) +- +-#define MT8135_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +-#define MT8135_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1) +-#define MT8135_PIN_82_MSDC2_DAT0__FUNC_EINT61 (MTK_PIN_NO(82) | 2) +-#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DSP1_ID (MTK_PIN_NO(82) | 4) +-#define MT8135_PIN_82_MSDC2_DAT0__FUNC_PCM1_DI (MTK_PIN_NO(82) | 5) +-#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DPI33_D4 (MTK_PIN_NO(82) | 6) +- +-#define MT8135_PIN_83_MSDC1_DAT0__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +-#define MT8135_PIN_83_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(83) | 1) +-#define MT8135_PIN_83_MSDC1_DAT0__FUNC_EINT53 (MTK_PIN_NO(83) | 2) +-#define MT8135_PIN_83_MSDC1_DAT0__FUNC_SCL1 (MTK_PIN_NO(83) | 3) +-#define MT8135_PIN_83_MSDC1_DAT0__FUNC_PWM2 (MTK_PIN_NO(83) | 4) +-#define MT8135_PIN_83_MSDC1_DAT0__FUNC_CLKM1 (MTK_PIN_NO(83) | 5) +-#define MT8135_PIN_83_MSDC1_DAT0__FUNC_TESTB_OUT2 (MTK_PIN_NO(83) | 7) +- +-#define MT8135_PIN_84_MSDC1_DAT1__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +-#define MT8135_PIN_84_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(84) | 1) +-#define MT8135_PIN_84_MSDC1_DAT1__FUNC_EINT54 (MTK_PIN_NO(84) | 2) +-#define MT8135_PIN_84_MSDC1_DAT1__FUNC_SDA1 (MTK_PIN_NO(84) | 3) +-#define MT8135_PIN_84_MSDC1_DAT1__FUNC_PWM3 (MTK_PIN_NO(84) | 4) +-#define MT8135_PIN_84_MSDC1_DAT1__FUNC_CLKM2 (MTK_PIN_NO(84) | 5) +-#define MT8135_PIN_84_MSDC1_DAT1__FUNC_TESTB_OUT3 (MTK_PIN_NO(84) | 7) +- +-#define MT8135_PIN_85_MSDC1_CMD__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +-#define MT8135_PIN_85_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(85) | 1) +-#define MT8135_PIN_85_MSDC1_CMD__FUNC_EINT52 (MTK_PIN_NO(85) | 2) +-#define MT8135_PIN_85_MSDC1_CMD__FUNC_SDA0 (MTK_PIN_NO(85) | 3) +-#define MT8135_PIN_85_MSDC1_CMD__FUNC_PWM1 (MTK_PIN_NO(85) | 4) +-#define MT8135_PIN_85_MSDC1_CMD__FUNC_CLKM0 (MTK_PIN_NO(85) | 5) +-#define MT8135_PIN_85_MSDC1_CMD__FUNC_TESTB_OUT1 (MTK_PIN_NO(85) | 7) +- +-#define MT8135_PIN_86_MSDC1_CLK__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +-#define MT8135_PIN_86_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(86) | 1) +-#define MT8135_PIN_86_MSDC1_CLK__FUNC_EINT51 (MTK_PIN_NO(86) | 2) +-#define MT8135_PIN_86_MSDC1_CLK__FUNC_SCL0 (MTK_PIN_NO(86) | 3) +-#define MT8135_PIN_86_MSDC1_CLK__FUNC_DISP_PWM (MTK_PIN_NO(86) | 4) +-#define MT8135_PIN_86_MSDC1_CLK__FUNC_TESTB_OUT0 (MTK_PIN_NO(86) | 7) +- +-#define MT8135_PIN_87_MSDC1_DAT2__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +-#define MT8135_PIN_87_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(87) | 1) +-#define MT8135_PIN_87_MSDC1_DAT2__FUNC_EINT55 (MTK_PIN_NO(87) | 2) +-#define MT8135_PIN_87_MSDC1_DAT2__FUNC_SCL4 (MTK_PIN_NO(87) | 3) +-#define MT8135_PIN_87_MSDC1_DAT2__FUNC_PWM4 (MTK_PIN_NO(87) | 4) +-#define MT8135_PIN_87_MSDC1_DAT2__FUNC_CLKM3 (MTK_PIN_NO(87) | 5) +-#define MT8135_PIN_87_MSDC1_DAT2__FUNC_TESTB_OUT4 (MTK_PIN_NO(87) | 7) +- +-#define MT8135_PIN_88_MSDC1_DAT3__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +-#define MT8135_PIN_88_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(88) | 1) +-#define MT8135_PIN_88_MSDC1_DAT3__FUNC_EINT56 (MTK_PIN_NO(88) | 2) +-#define MT8135_PIN_88_MSDC1_DAT3__FUNC_SDA4 (MTK_PIN_NO(88) | 3) +-#define MT8135_PIN_88_MSDC1_DAT3__FUNC_PWM5 (MTK_PIN_NO(88) | 4) +-#define MT8135_PIN_88_MSDC1_DAT3__FUNC_CLKM4 (MTK_PIN_NO(88) | 5) +-#define MT8135_PIN_88_MSDC1_DAT3__FUNC_TESTB_OUT5 (MTK_PIN_NO(88) | 7) +- +-#define MT8135_PIN_89_MSDC4_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +-#define MT8135_PIN_89_MSDC4_DAT0__FUNC_MSDC4_DAT0 (MTK_PIN_NO(89) | 1) +-#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EINT133 (MTK_PIN_NO(89) | 2) +-#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(89) | 4) +-#define MT8135_PIN_89_MSDC4_DAT0__FUNC_USB_DRVVBUS (MTK_PIN_NO(89) | 5) +-#define MT8135_PIN_89_MSDC4_DAT0__FUNC_A_FUNC_DIN_9 (MTK_PIN_NO(89) | 6) +-#define MT8135_PIN_89_MSDC4_DAT0__FUNC_LPTE (MTK_PIN_NO(89) | 7) +- +-#define MT8135_PIN_90_MSDC4_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +-#define MT8135_PIN_90_MSDC4_DAT1__FUNC_MSDC4_DAT1 (MTK_PIN_NO(90) | 1) +-#define MT8135_PIN_90_MSDC4_DAT1__FUNC_EINT134 (MTK_PIN_NO(90) | 2) +-#define MT8135_PIN_90_MSDC4_DAT1__FUNC_A_FUNC_DIN_10 (MTK_PIN_NO(90) | 6) +-#define MT8135_PIN_90_MSDC4_DAT1__FUNC_LRSTB_1X (MTK_PIN_NO(90) | 7) +- +-#define MT8135_PIN_91_MSDC4_DAT5__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +-#define MT8135_PIN_91_MSDC4_DAT5__FUNC_MSDC4_DAT5 (MTK_PIN_NO(91) | 1) +-#define MT8135_PIN_91_MSDC4_DAT5__FUNC_EINT136 (MTK_PIN_NO(91) | 2) +-#define MT8135_PIN_91_MSDC4_DAT5__FUNC_I2SIN_WS (MTK_PIN_NO(91) | 3) +-#define MT8135_PIN_91_MSDC4_DAT5__FUNC_DAC_WS (MTK_PIN_NO(91) | 4) +-#define MT8135_PIN_91_MSDC4_DAT5__FUNC_PCM1_WS (MTK_PIN_NO(91) | 5) +-#define MT8135_PIN_91_MSDC4_DAT5__FUNC_A_FUNC_DIN_11 (MTK_PIN_NO(91) | 6) +-#define MT8135_PIN_91_MSDC4_DAT5__FUNC_SPI1_CSN (MTK_PIN_NO(91) | 7) +- +-#define MT8135_PIN_92_MSDC4_DAT6__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +-#define MT8135_PIN_92_MSDC4_DAT6__FUNC_MSDC4_DAT6 (MTK_PIN_NO(92) | 1) +-#define MT8135_PIN_92_MSDC4_DAT6__FUNC_EINT137 (MTK_PIN_NO(92) | 2) +-#define MT8135_PIN_92_MSDC4_DAT6__FUNC_I2SOUT_DAT (MTK_PIN_NO(92) | 3) +-#define MT8135_PIN_92_MSDC4_DAT6__FUNC_DAC_DAT_OUT (MTK_PIN_NO(92) | 4) +-#define MT8135_PIN_92_MSDC4_DAT6__FUNC_PCM1_DO (MTK_PIN_NO(92) | 5) +-#define MT8135_PIN_92_MSDC4_DAT6__FUNC_A_FUNC_DIN_12 (MTK_PIN_NO(92) | 6) +-#define MT8135_PIN_92_MSDC4_DAT6__FUNC_SPI1_MO (MTK_PIN_NO(92) | 7) +- +-#define MT8135_PIN_93_MSDC4_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +-#define MT8135_PIN_93_MSDC4_DAT7__FUNC_MSDC4_DAT7 (MTK_PIN_NO(93) | 1) +-#define MT8135_PIN_93_MSDC4_DAT7__FUNC_EINT138 (MTK_PIN_NO(93) | 2) +-#define MT8135_PIN_93_MSDC4_DAT7__FUNC_I2SIN_DAT (MTK_PIN_NO(93) | 3) +-#define MT8135_PIN_93_MSDC4_DAT7__FUNC_PCM1_DI (MTK_PIN_NO(93) | 5) +-#define MT8135_PIN_93_MSDC4_DAT7__FUNC_A_FUNC_DIN_13 (MTK_PIN_NO(93) | 6) +-#define MT8135_PIN_93_MSDC4_DAT7__FUNC_SPI1_MI (MTK_PIN_NO(93) | 7) +- +-#define MT8135_PIN_94_MSDC4_DAT4__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +-#define MT8135_PIN_94_MSDC4_DAT4__FUNC_MSDC4_DAT4 (MTK_PIN_NO(94) | 1) +-#define MT8135_PIN_94_MSDC4_DAT4__FUNC_EINT135 (MTK_PIN_NO(94) | 2) +-#define MT8135_PIN_94_MSDC4_DAT4__FUNC_I2SIN_CK (MTK_PIN_NO(94) | 3) +-#define MT8135_PIN_94_MSDC4_DAT4__FUNC_DAC_CK (MTK_PIN_NO(94) | 4) +-#define MT8135_PIN_94_MSDC4_DAT4__FUNC_PCM1_CK (MTK_PIN_NO(94) | 5) +-#define MT8135_PIN_94_MSDC4_DAT4__FUNC_A_FUNC_DIN_14 (MTK_PIN_NO(94) | 6) +-#define MT8135_PIN_94_MSDC4_DAT4__FUNC_SPI1_CLK (MTK_PIN_NO(94) | 7) +- +-#define MT8135_PIN_95_MSDC4_DAT2__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +-#define MT8135_PIN_95_MSDC4_DAT2__FUNC_MSDC4_DAT2 (MTK_PIN_NO(95) | 1) +-#define MT8135_PIN_95_MSDC4_DAT2__FUNC_EINT131 (MTK_PIN_NO(95) | 2) +-#define MT8135_PIN_95_MSDC4_DAT2__FUNC_I2SIN_WS (MTK_PIN_NO(95) | 3) +-#define MT8135_PIN_95_MSDC4_DAT2__FUNC_CM2PDN_2X (MTK_PIN_NO(95) | 4) +-#define MT8135_PIN_95_MSDC4_DAT2__FUNC_DAC_WS (MTK_PIN_NO(95) | 5) +-#define MT8135_PIN_95_MSDC4_DAT2__FUNC_PCM1_WS (MTK_PIN_NO(95) | 6) +-#define MT8135_PIN_95_MSDC4_DAT2__FUNC_LSCE0B_1X (MTK_PIN_NO(95) | 7) +- +-#define MT8135_PIN_96_MSDC4_CLK__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +-#define MT8135_PIN_96_MSDC4_CLK__FUNC_MSDC4_CLK (MTK_PIN_NO(96) | 1) +-#define MT8135_PIN_96_MSDC4_CLK__FUNC_EINT129 (MTK_PIN_NO(96) | 2) +-#define MT8135_PIN_96_MSDC4_CLK__FUNC_DPI1_CK_2X (MTK_PIN_NO(96) | 3) +-#define MT8135_PIN_96_MSDC4_CLK__FUNC_CM2PCLK_2X (MTK_PIN_NO(96) | 4) +-#define MT8135_PIN_96_MSDC4_CLK__FUNC_PWM4 (MTK_PIN_NO(96) | 5) +-#define MT8135_PIN_96_MSDC4_CLK__FUNC_PCM1_DI (MTK_PIN_NO(96) | 6) +-#define MT8135_PIN_96_MSDC4_CLK__FUNC_LSCK_1X (MTK_PIN_NO(96) | 7) +- +-#define MT8135_PIN_97_MSDC4_DAT3__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +-#define MT8135_PIN_97_MSDC4_DAT3__FUNC_MSDC4_DAT3 (MTK_PIN_NO(97) | 1) +-#define MT8135_PIN_97_MSDC4_DAT3__FUNC_EINT132 (MTK_PIN_NO(97) | 2) +-#define MT8135_PIN_97_MSDC4_DAT3__FUNC_I2SOUT_DAT (MTK_PIN_NO(97) | 3) +-#define MT8135_PIN_97_MSDC4_DAT3__FUNC_CM2RST_2X (MTK_PIN_NO(97) | 4) +-#define MT8135_PIN_97_MSDC4_DAT3__FUNC_DAC_DAT_OUT (MTK_PIN_NO(97) | 5) +-#define MT8135_PIN_97_MSDC4_DAT3__FUNC_PCM1_DO (MTK_PIN_NO(97) | 6) +-#define MT8135_PIN_97_MSDC4_DAT3__FUNC_LSCE1B_1X (MTK_PIN_NO(97) | 7) +- +-#define MT8135_PIN_98_MSDC4_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +-#define MT8135_PIN_98_MSDC4_CMD__FUNC_MSDC4_CMD (MTK_PIN_NO(98) | 1) +-#define MT8135_PIN_98_MSDC4_CMD__FUNC_EINT128 (MTK_PIN_NO(98) | 2) +-#define MT8135_PIN_98_MSDC4_CMD__FUNC_DPI1_DE_2X (MTK_PIN_NO(98) | 3) +-#define MT8135_PIN_98_MSDC4_CMD__FUNC_PWM3 (MTK_PIN_NO(98) | 5) +-#define MT8135_PIN_98_MSDC4_CMD__FUNC_LSDA_1X (MTK_PIN_NO(98) | 7) +- +-#define MT8135_PIN_99_MSDC4_RSTB__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +-#define MT8135_PIN_99_MSDC4_RSTB__FUNC_MSDC4_RSTB (MTK_PIN_NO(99) | 1) +-#define MT8135_PIN_99_MSDC4_RSTB__FUNC_EINT130 (MTK_PIN_NO(99) | 2) +-#define MT8135_PIN_99_MSDC4_RSTB__FUNC_I2SIN_CK (MTK_PIN_NO(99) | 3) +-#define MT8135_PIN_99_MSDC4_RSTB__FUNC_CM2MCLK_2X (MTK_PIN_NO(99) | 4) +-#define MT8135_PIN_99_MSDC4_RSTB__FUNC_DAC_CK (MTK_PIN_NO(99) | 5) +-#define MT8135_PIN_99_MSDC4_RSTB__FUNC_PCM1_CK (MTK_PIN_NO(99) | 6) +-#define MT8135_PIN_99_MSDC4_RSTB__FUNC_LSA0_1X (MTK_PIN_NO(99) | 7) +- +-#define MT8135_PIN_100_SDA0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +-#define MT8135_PIN_100_SDA0__FUNC_SDA0 (MTK_PIN_NO(100) | 1) +-#define MT8135_PIN_100_SDA0__FUNC_EINT91 (MTK_PIN_NO(100) | 2) +-#define MT8135_PIN_100_SDA0__FUNC_CLKM1 (MTK_PIN_NO(100) | 3) +-#define MT8135_PIN_100_SDA0__FUNC_PWM1 (MTK_PIN_NO(100) | 4) +-#define MT8135_PIN_100_SDA0__FUNC_A_FUNC_DIN_15 (MTK_PIN_NO(100) | 7) +- +-#define MT8135_PIN_101_SCL0__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +-#define MT8135_PIN_101_SCL0__FUNC_SCL0 (MTK_PIN_NO(101) | 1) +-#define MT8135_PIN_101_SCL0__FUNC_EINT90 (MTK_PIN_NO(101) | 2) +-#define MT8135_PIN_101_SCL0__FUNC_CLKM0 (MTK_PIN_NO(101) | 3) +-#define MT8135_PIN_101_SCL0__FUNC_DISP_PWM (MTK_PIN_NO(101) | 4) +-#define MT8135_PIN_101_SCL0__FUNC_A_FUNC_DIN_16 (MTK_PIN_NO(101) | 7) +- +-#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +-#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_EINT10 (MTK_PIN_NO(102) | 1) +-#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_USB_TEST_IO_16 (MTK_PIN_NO(102) | 5) +-#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_TESTB_OUT16 (MTK_PIN_NO(102) | 6) +-#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_A_FUNC_DIN_17 (MTK_PIN_NO(102) | 7) +- +-#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +-#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_EINT11 (MTK_PIN_NO(103) | 1) +-#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_USB_TEST_IO_17 (MTK_PIN_NO(103) | 5) +-#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_TESTB_OUT17 (MTK_PIN_NO(103) | 6) +-#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_A_FUNC_DIN_18 (MTK_PIN_NO(103) | 7) +- +-#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +-#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_EINT16 (MTK_PIN_NO(104) | 1) +-#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_USB_TEST_IO_18 (MTK_PIN_NO(104) | 5) +-#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_TESTB_OUT18 (MTK_PIN_NO(104) | 6) +-#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_A_FUNC_DIN_19 (MTK_PIN_NO(104) | 7) +- +-#define MT8135_PIN_105_I2S_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +-#define MT8135_PIN_105_I2S_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(105) | 1) +-#define MT8135_PIN_105_I2S_CLK__FUNC_EINT10 (MTK_PIN_NO(105) | 2) +-#define MT8135_PIN_105_I2S_CLK__FUNC_DAC_CK (MTK_PIN_NO(105) | 3) +-#define MT8135_PIN_105_I2S_CLK__FUNC_PCM1_CK (MTK_PIN_NO(105) | 4) +-#define MT8135_PIN_105_I2S_CLK__FUNC_USB_TEST_IO_19 (MTK_PIN_NO(105) | 5) +-#define MT8135_PIN_105_I2S_CLK__FUNC_TESTB_OUT19 (MTK_PIN_NO(105) | 6) +-#define MT8135_PIN_105_I2S_CLK__FUNC_A_FUNC_DIN_20 (MTK_PIN_NO(105) | 7) +- +-#define MT8135_PIN_106_I2S_WS__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +-#define MT8135_PIN_106_I2S_WS__FUNC_I2SIN_WS (MTK_PIN_NO(106) | 1) +-#define MT8135_PIN_106_I2S_WS__FUNC_EINT13 (MTK_PIN_NO(106) | 2) +-#define MT8135_PIN_106_I2S_WS__FUNC_DAC_WS (MTK_PIN_NO(106) | 3) +-#define MT8135_PIN_106_I2S_WS__FUNC_PCM1_WS (MTK_PIN_NO(106) | 4) +-#define MT8135_PIN_106_I2S_WS__FUNC_USB_TEST_IO_20 (MTK_PIN_NO(106) | 5) +-#define MT8135_PIN_106_I2S_WS__FUNC_TESTB_OUT20 (MTK_PIN_NO(106) | 6) +-#define MT8135_PIN_106_I2S_WS__FUNC_A_FUNC_DIN_21 (MTK_PIN_NO(106) | 7) +- +-#define MT8135_PIN_107_I2S_DATA_IN__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +-#define MT8135_PIN_107_I2S_DATA_IN__FUNC_I2SIN_DAT (MTK_PIN_NO(107) | 1) +-#define MT8135_PIN_107_I2S_DATA_IN__FUNC_EINT11 (MTK_PIN_NO(107) | 2) +-#define MT8135_PIN_107_I2S_DATA_IN__FUNC_PCM1_DI (MTK_PIN_NO(107) | 4) +-#define MT8135_PIN_107_I2S_DATA_IN__FUNC_USB_TEST_IO_21 (MTK_PIN_NO(107) | 5) +-#define MT8135_PIN_107_I2S_DATA_IN__FUNC_TESTB_OUT22 (MTK_PIN_NO(107) | 6) +-#define MT8135_PIN_107_I2S_DATA_IN__FUNC_A_FUNC_DIN_22 (MTK_PIN_NO(107) | 7) +- +-#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +-#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_I2SOUT_DAT (MTK_PIN_NO(108) | 1) +-#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_EINT12 (MTK_PIN_NO(108) | 2) +-#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(108) | 3) +-#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_PCM1_DO (MTK_PIN_NO(108) | 4) +-#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_USB_TEST_IO_22 (MTK_PIN_NO(108) | 5) +-#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_TESTB_OUT23 (MTK_PIN_NO(108) | 6) +-#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_A_FUNC_DIN_23 (MTK_PIN_NO(108) | 7) +- +-#define MT8135_PIN_109_EINT5__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +-#define MT8135_PIN_109_EINT5__FUNC_EINT5 (MTK_PIN_NO(109) | 1) +-#define MT8135_PIN_109_EINT5__FUNC_PWM5 (MTK_PIN_NO(109) | 2) +-#define MT8135_PIN_109_EINT5__FUNC_CLKM3 (MTK_PIN_NO(109) | 3) +-#define MT8135_PIN_109_EINT5__FUNC_GPU_JTRSTB (MTK_PIN_NO(109) | 4) +-#define MT8135_PIN_109_EINT5__FUNC_USB_TEST_IO_23 (MTK_PIN_NO(109) | 5) +-#define MT8135_PIN_109_EINT5__FUNC_TESTB_OUT26 (MTK_PIN_NO(109) | 6) +-#define MT8135_PIN_109_EINT5__FUNC_A_FUNC_DIN_24 (MTK_PIN_NO(109) | 7) +- +-#define MT8135_PIN_110_EINT6__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +-#define MT8135_PIN_110_EINT6__FUNC_EINT6 (MTK_PIN_NO(110) | 1) +-#define MT8135_PIN_110_EINT6__FUNC_PWM6 (MTK_PIN_NO(110) | 2) +-#define MT8135_PIN_110_EINT6__FUNC_CLKM4 (MTK_PIN_NO(110) | 3) +-#define MT8135_PIN_110_EINT6__FUNC_GPU_JTMS (MTK_PIN_NO(110) | 4) +-#define MT8135_PIN_110_EINT6__FUNC_USB_TEST_IO_24 (MTK_PIN_NO(110) | 5) +-#define MT8135_PIN_110_EINT6__FUNC_TESTB_OUT27 (MTK_PIN_NO(110) | 6) +-#define MT8135_PIN_110_EINT6__FUNC_A_FUNC_DIN_25 (MTK_PIN_NO(110) | 7) +- +-#define MT8135_PIN_111_EINT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +-#define MT8135_PIN_111_EINT7__FUNC_EINT7 (MTK_PIN_NO(111) | 1) +-#define MT8135_PIN_111_EINT7__FUNC_PWM7 (MTK_PIN_NO(111) | 2) +-#define MT8135_PIN_111_EINT7__FUNC_CLKM5 (MTK_PIN_NO(111) | 3) +-#define MT8135_PIN_111_EINT7__FUNC_GPU_JTDO (MTK_PIN_NO(111) | 4) +-#define MT8135_PIN_111_EINT7__FUNC_USB_TEST_IO_25 (MTK_PIN_NO(111) | 5) +-#define MT8135_PIN_111_EINT7__FUNC_TESTB_OUT28 (MTK_PIN_NO(111) | 6) +-#define MT8135_PIN_111_EINT7__FUNC_A_FUNC_DIN_26 (MTK_PIN_NO(111) | 7) +- +-#define MT8135_PIN_112_EINT8__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +-#define MT8135_PIN_112_EINT8__FUNC_EINT8 (MTK_PIN_NO(112) | 1) +-#define MT8135_PIN_112_EINT8__FUNC_DISP_PWM (MTK_PIN_NO(112) | 2) +-#define MT8135_PIN_112_EINT8__FUNC_CLKM6 (MTK_PIN_NO(112) | 3) +-#define MT8135_PIN_112_EINT8__FUNC_GPU_JTDI (MTK_PIN_NO(112) | 4) +-#define MT8135_PIN_112_EINT8__FUNC_USB_TEST_IO_26 (MTK_PIN_NO(112) | 5) +-#define MT8135_PIN_112_EINT8__FUNC_TESTB_OUT29 (MTK_PIN_NO(112) | 6) +-#define MT8135_PIN_112_EINT8__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(112) | 7) +- +-#define MT8135_PIN_113_EINT9__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +-#define MT8135_PIN_113_EINT9__FUNC_EINT9 (MTK_PIN_NO(113) | 1) +-#define MT8135_PIN_113_EINT9__FUNC_GPU_JTCK (MTK_PIN_NO(113) | 4) +-#define MT8135_PIN_113_EINT9__FUNC_USB_DRVVBUS (MTK_PIN_NO(113) | 5) +-#define MT8135_PIN_113_EINT9__FUNC_TESTB_OUT30 (MTK_PIN_NO(113) | 6) +-#define MT8135_PIN_113_EINT9__FUNC_A_FUNC_DIN_27 (MTK_PIN_NO(113) | 7) +- +-#define MT8135_PIN_114_LPCE1B__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +-#define MT8135_PIN_114_LPCE1B__FUNC_LPCE1B (MTK_PIN_NO(114) | 1) +-#define MT8135_PIN_114_LPCE1B__FUNC_EINT127 (MTK_PIN_NO(114) | 2) +-#define MT8135_PIN_114_LPCE1B__FUNC_PWM2 (MTK_PIN_NO(114) | 5) +-#define MT8135_PIN_114_LPCE1B__FUNC_TESTB_OUT14 (MTK_PIN_NO(114) | 6) +-#define MT8135_PIN_114_LPCE1B__FUNC_A_FUNC_DIN_28 (MTK_PIN_NO(114) | 7) +- +-#define MT8135_PIN_115_LPCE0B__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +-#define MT8135_PIN_115_LPCE0B__FUNC_LPCE0B (MTK_PIN_NO(115) | 1) +-#define MT8135_PIN_115_LPCE0B__FUNC_EINT126 (MTK_PIN_NO(115) | 2) +-#define MT8135_PIN_115_LPCE0B__FUNC_PWM1 (MTK_PIN_NO(115) | 5) +-#define MT8135_PIN_115_LPCE0B__FUNC_TESTB_OUT15 (MTK_PIN_NO(115) | 6) +-#define MT8135_PIN_115_LPCE0B__FUNC_A_FUNC_DIN_29 (MTK_PIN_NO(115) | 7) +- +-#define MT8135_PIN_116_DISP_PWM__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +-#define MT8135_PIN_116_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(116) | 1) +-#define MT8135_PIN_116_DISP_PWM__FUNC_EINT77 (MTK_PIN_NO(116) | 2) +-#define MT8135_PIN_116_DISP_PWM__FUNC_LSDI (MTK_PIN_NO(116) | 3) +-#define MT8135_PIN_116_DISP_PWM__FUNC_PWM1 (MTK_PIN_NO(116) | 4) +-#define MT8135_PIN_116_DISP_PWM__FUNC_PWM2 (MTK_PIN_NO(116) | 5) +-#define MT8135_PIN_116_DISP_PWM__FUNC_PWM3 (MTK_PIN_NO(116) | 7) +- +-#define MT8135_PIN_117_EINT1__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +-#define MT8135_PIN_117_EINT1__FUNC_EINT1 (MTK_PIN_NO(117) | 1) +-#define MT8135_PIN_117_EINT1__FUNC_PWM2 (MTK_PIN_NO(117) | 2) +-#define MT8135_PIN_117_EINT1__FUNC_CLKM1 (MTK_PIN_NO(117) | 3) +-#define MT8135_PIN_117_EINT1__FUNC_USB_TEST_IO_13 (MTK_PIN_NO(117) | 5) +-#define MT8135_PIN_117_EINT1__FUNC_USB_SDA (MTK_PIN_NO(117) | 7) +- +-#define MT8135_PIN_118_EINT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +-#define MT8135_PIN_118_EINT2__FUNC_EINT2 (MTK_PIN_NO(118) | 1) +-#define MT8135_PIN_118_EINT2__FUNC_PWM3 (MTK_PIN_NO(118) | 2) +-#define MT8135_PIN_118_EINT2__FUNC_CLKM2 (MTK_PIN_NO(118) | 3) +-#define MT8135_PIN_118_EINT2__FUNC_USB_TEST_IO_14 (MTK_PIN_NO(118) | 5) +-#define MT8135_PIN_118_EINT2__FUNC_SRCLKENAI2 (MTK_PIN_NO(118) | 6) +-#define MT8135_PIN_118_EINT2__FUNC_A_FUNC_DIN_30 (MTK_PIN_NO(118) | 7) +- +-#define MT8135_PIN_119_EINT3__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +-#define MT8135_PIN_119_EINT3__FUNC_EINT3 (MTK_PIN_NO(119) | 1) +-#define MT8135_PIN_119_EINT3__FUNC_USB_TEST_IO_15 (MTK_PIN_NO(119) | 5) +-#define MT8135_PIN_119_EINT3__FUNC_SRCLKENAI1 (MTK_PIN_NO(119) | 6) +-#define MT8135_PIN_119_EINT3__FUNC_EXT_26M_CK (MTK_PIN_NO(119) | 7) +- +-#define MT8135_PIN_120_EINT4__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +-#define MT8135_PIN_120_EINT4__FUNC_EINT4 (MTK_PIN_NO(120) | 1) +-#define MT8135_PIN_120_EINT4__FUNC_PWM4 (MTK_PIN_NO(120) | 2) +-#define MT8135_PIN_120_EINT4__FUNC_USB_DRVVBUS (MTK_PIN_NO(120) | 5) +-#define MT8135_PIN_120_EINT4__FUNC_A_FUNC_DIN_31 (MTK_PIN_NO(120) | 7) +- +-#define MT8135_PIN_121_DPIDE__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +-#define MT8135_PIN_121_DPIDE__FUNC_DPI0_DE (MTK_PIN_NO(121) | 1) +-#define MT8135_PIN_121_DPIDE__FUNC_EINT100 (MTK_PIN_NO(121) | 2) +-#define MT8135_PIN_121_DPIDE__FUNC_I2SOUT_DAT (MTK_PIN_NO(121) | 3) +-#define MT8135_PIN_121_DPIDE__FUNC_DAC_DAT_OUT (MTK_PIN_NO(121) | 4) +-#define MT8135_PIN_121_DPIDE__FUNC_PCM1_DO (MTK_PIN_NO(121) | 5) +-#define MT8135_PIN_121_DPIDE__FUNC_IRDA_TXD (MTK_PIN_NO(121) | 6) +- +-#define MT8135_PIN_122_DPICK__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +-#define MT8135_PIN_122_DPICK__FUNC_DPI0_CK (MTK_PIN_NO(122) | 1) +-#define MT8135_PIN_122_DPICK__FUNC_EINT101 (MTK_PIN_NO(122) | 2) +-#define MT8135_PIN_122_DPICK__FUNC_I2SIN_DAT (MTK_PIN_NO(122) | 3) +-#define MT8135_PIN_122_DPICK__FUNC_PCM1_DI (MTK_PIN_NO(122) | 5) +-#define MT8135_PIN_122_DPICK__FUNC_IRDA_PDN (MTK_PIN_NO(122) | 6) +- +-#define MT8135_PIN_123_DPIG4__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +-#define MT8135_PIN_123_DPIG4__FUNC_DPI0_G4 (MTK_PIN_NO(123) | 1) +-#define MT8135_PIN_123_DPIG4__FUNC_EINT114 (MTK_PIN_NO(123) | 2) +-#define MT8135_PIN_123_DPIG4__FUNC_CM2DAT_2X_0 (MTK_PIN_NO(123) | 4) +-#define MT8135_PIN_123_DPIG4__FUNC_DSP2_ID (MTK_PIN_NO(123) | 5) +- +-#define MT8135_PIN_124_DPIG5__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +-#define MT8135_PIN_124_DPIG5__FUNC_DPI0_G5 (MTK_PIN_NO(124) | 1) +-#define MT8135_PIN_124_DPIG5__FUNC_EINT115 (MTK_PIN_NO(124) | 2) +-#define MT8135_PIN_124_DPIG5__FUNC_CM2DAT_2X_1 (MTK_PIN_NO(124) | 4) +-#define MT8135_PIN_124_DPIG5__FUNC_DSP2_ICK (MTK_PIN_NO(124) | 5) +- +-#define MT8135_PIN_125_DPIR3__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +-#define MT8135_PIN_125_DPIR3__FUNC_DPI0_R3 (MTK_PIN_NO(125) | 1) +-#define MT8135_PIN_125_DPIR3__FUNC_EINT121 (MTK_PIN_NO(125) | 2) +-#define MT8135_PIN_125_DPIR3__FUNC_CM2DAT_2X_7 (MTK_PIN_NO(125) | 4) +- +-#define MT8135_PIN_126_DPIG1__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +-#define MT8135_PIN_126_DPIG1__FUNC_DPI0_G1 (MTK_PIN_NO(126) | 1) +-#define MT8135_PIN_126_DPIG1__FUNC_EINT111 (MTK_PIN_NO(126) | 2) +-#define MT8135_PIN_126_DPIG1__FUNC_DSP1_ICK (MTK_PIN_NO(126) | 5) +- +-#define MT8135_PIN_127_DPIVSYNC__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +-#define MT8135_PIN_127_DPIVSYNC__FUNC_DPI0_VSYNC (MTK_PIN_NO(127) | 1) +-#define MT8135_PIN_127_DPIVSYNC__FUNC_EINT98 (MTK_PIN_NO(127) | 2) +-#define MT8135_PIN_127_DPIVSYNC__FUNC_I2SIN_CK (MTK_PIN_NO(127) | 3) +-#define MT8135_PIN_127_DPIVSYNC__FUNC_DAC_CK (MTK_PIN_NO(127) | 4) +-#define MT8135_PIN_127_DPIVSYNC__FUNC_PCM1_CK (MTK_PIN_NO(127) | 5) +- +-#define MT8135_PIN_128_DPIHSYNC__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +-#define MT8135_PIN_128_DPIHSYNC__FUNC_DPI0_HSYNC (MTK_PIN_NO(128) | 1) +-#define MT8135_PIN_128_DPIHSYNC__FUNC_EINT99 (MTK_PIN_NO(128) | 2) +-#define MT8135_PIN_128_DPIHSYNC__FUNC_I2SIN_WS (MTK_PIN_NO(128) | 3) +-#define MT8135_PIN_128_DPIHSYNC__FUNC_DAC_WS (MTK_PIN_NO(128) | 4) +-#define MT8135_PIN_128_DPIHSYNC__FUNC_PCM1_WS (MTK_PIN_NO(128) | 5) +-#define MT8135_PIN_128_DPIHSYNC__FUNC_IRDA_RXD (MTK_PIN_NO(128) | 6) +- +-#define MT8135_PIN_129_DPIB0__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +-#define MT8135_PIN_129_DPIB0__FUNC_DPI0_B0 (MTK_PIN_NO(129) | 1) +-#define MT8135_PIN_129_DPIB0__FUNC_EINT102 (MTK_PIN_NO(129) | 2) +-#define MT8135_PIN_129_DPIB0__FUNC_SCL0 (MTK_PIN_NO(129) | 4) +-#define MT8135_PIN_129_DPIB0__FUNC_DISP_PWM (MTK_PIN_NO(129) | 5) +- +-#define MT8135_PIN_130_DPIB1__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +-#define MT8135_PIN_130_DPIB1__FUNC_DPI0_B1 (MTK_PIN_NO(130) | 1) +-#define MT8135_PIN_130_DPIB1__FUNC_EINT103 (MTK_PIN_NO(130) | 2) +-#define MT8135_PIN_130_DPIB1__FUNC_CLKM0 (MTK_PIN_NO(130) | 3) +-#define MT8135_PIN_130_DPIB1__FUNC_SDA0 (MTK_PIN_NO(130) | 4) +-#define MT8135_PIN_130_DPIB1__FUNC_PWM1 (MTK_PIN_NO(130) | 5) +- +-#define MT8135_PIN_131_DPIB2__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +-#define MT8135_PIN_131_DPIB2__FUNC_DPI0_B2 (MTK_PIN_NO(131) | 1) +-#define MT8135_PIN_131_DPIB2__FUNC_EINT104 (MTK_PIN_NO(131) | 2) +-#define MT8135_PIN_131_DPIB2__FUNC_CLKM1 (MTK_PIN_NO(131) | 3) +-#define MT8135_PIN_131_DPIB2__FUNC_SCL1 (MTK_PIN_NO(131) | 4) +-#define MT8135_PIN_131_DPIB2__FUNC_PWM2 (MTK_PIN_NO(131) | 5) +- +-#define MT8135_PIN_132_DPIB3__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +-#define MT8135_PIN_132_DPIB3__FUNC_DPI0_B3 (MTK_PIN_NO(132) | 1) +-#define MT8135_PIN_132_DPIB3__FUNC_EINT105 (MTK_PIN_NO(132) | 2) +-#define MT8135_PIN_132_DPIB3__FUNC_CLKM2 (MTK_PIN_NO(132) | 3) +-#define MT8135_PIN_132_DPIB3__FUNC_SDA1 (MTK_PIN_NO(132) | 4) +-#define MT8135_PIN_132_DPIB3__FUNC_PWM3 (MTK_PIN_NO(132) | 5) +- +-#define MT8135_PIN_133_DPIB4__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +-#define MT8135_PIN_133_DPIB4__FUNC_DPI0_B4 (MTK_PIN_NO(133) | 1) +-#define MT8135_PIN_133_DPIB4__FUNC_EINT106 (MTK_PIN_NO(133) | 2) +-#define MT8135_PIN_133_DPIB4__FUNC_CLKM3 (MTK_PIN_NO(133) | 3) +-#define MT8135_PIN_133_DPIB4__FUNC_SCL2 (MTK_PIN_NO(133) | 4) +-#define MT8135_PIN_133_DPIB4__FUNC_PWM4 (MTK_PIN_NO(133) | 5) +- +-#define MT8135_PIN_134_DPIB5__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +-#define MT8135_PIN_134_DPIB5__FUNC_DPI0_B5 (MTK_PIN_NO(134) | 1) +-#define MT8135_PIN_134_DPIB5__FUNC_EINT107 (MTK_PIN_NO(134) | 2) +-#define MT8135_PIN_134_DPIB5__FUNC_CLKM4 (MTK_PIN_NO(134) | 3) +-#define MT8135_PIN_134_DPIB5__FUNC_SDA2 (MTK_PIN_NO(134) | 4) +-#define MT8135_PIN_134_DPIB5__FUNC_PWM5 (MTK_PIN_NO(134) | 5) +- +-#define MT8135_PIN_135_DPIB6__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +-#define MT8135_PIN_135_DPIB6__FUNC_DPI0_B6 (MTK_PIN_NO(135) | 1) +-#define MT8135_PIN_135_DPIB6__FUNC_EINT108 (MTK_PIN_NO(135) | 2) +-#define MT8135_PIN_135_DPIB6__FUNC_CLKM5 (MTK_PIN_NO(135) | 3) +-#define MT8135_PIN_135_DPIB6__FUNC_SCL3 (MTK_PIN_NO(135) | 4) +-#define MT8135_PIN_135_DPIB6__FUNC_PWM6 (MTK_PIN_NO(135) | 5) +- +-#define MT8135_PIN_136_DPIB7__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +-#define MT8135_PIN_136_DPIB7__FUNC_DPI0_B7 (MTK_PIN_NO(136) | 1) +-#define MT8135_PIN_136_DPIB7__FUNC_EINT109 (MTK_PIN_NO(136) | 2) +-#define MT8135_PIN_136_DPIB7__FUNC_CLKM6 (MTK_PIN_NO(136) | 3) +-#define MT8135_PIN_136_DPIB7__FUNC_SDA3 (MTK_PIN_NO(136) | 4) +-#define MT8135_PIN_136_DPIB7__FUNC_PWM7 (MTK_PIN_NO(136) | 5) +- +-#define MT8135_PIN_137_DPIG0__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +-#define MT8135_PIN_137_DPIG0__FUNC_DPI0_G0 (MTK_PIN_NO(137) | 1) +-#define MT8135_PIN_137_DPIG0__FUNC_EINT110 (MTK_PIN_NO(137) | 2) +-#define MT8135_PIN_137_DPIG0__FUNC_DSP1_ID (MTK_PIN_NO(137) | 5) +- +-#define MT8135_PIN_138_DPIG2__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +-#define MT8135_PIN_138_DPIG2__FUNC_DPI0_G2 (MTK_PIN_NO(138) | 1) +-#define MT8135_PIN_138_DPIG2__FUNC_EINT112 (MTK_PIN_NO(138) | 2) +-#define MT8135_PIN_138_DPIG2__FUNC_DSP1_IMS (MTK_PIN_NO(138) | 5) +- +-#define MT8135_PIN_139_DPIG3__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +-#define MT8135_PIN_139_DPIG3__FUNC_DPI0_G3 (MTK_PIN_NO(139) | 1) +-#define MT8135_PIN_139_DPIG3__FUNC_EINT113 (MTK_PIN_NO(139) | 2) +-#define MT8135_PIN_139_DPIG3__FUNC_DSP2_IMS (MTK_PIN_NO(139) | 5) +- +-#define MT8135_PIN_140_DPIG6__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +-#define MT8135_PIN_140_DPIG6__FUNC_DPI0_G6 (MTK_PIN_NO(140) | 1) +-#define MT8135_PIN_140_DPIG6__FUNC_EINT116 (MTK_PIN_NO(140) | 2) +-#define MT8135_PIN_140_DPIG6__FUNC_CM2DAT_2X_2 (MTK_PIN_NO(140) | 4) +- +-#define MT8135_PIN_141_DPIG7__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +-#define MT8135_PIN_141_DPIG7__FUNC_DPI0_G7 (MTK_PIN_NO(141) | 1) +-#define MT8135_PIN_141_DPIG7__FUNC_EINT117 (MTK_PIN_NO(141) | 2) +-#define MT8135_PIN_141_DPIG7__FUNC_CM2DAT_2X_3 (MTK_PIN_NO(141) | 4) +- +-#define MT8135_PIN_142_DPIR0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +-#define MT8135_PIN_142_DPIR0__FUNC_DPI0_R0 (MTK_PIN_NO(142) | 1) +-#define MT8135_PIN_142_DPIR0__FUNC_EINT118 (MTK_PIN_NO(142) | 2) +-#define MT8135_PIN_142_DPIR0__FUNC_CM2DAT_2X_4 (MTK_PIN_NO(142) | 4) +- +-#define MT8135_PIN_143_DPIR1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +-#define MT8135_PIN_143_DPIR1__FUNC_DPI0_R1 (MTK_PIN_NO(143) | 1) +-#define MT8135_PIN_143_DPIR1__FUNC_EINT119 (MTK_PIN_NO(143) | 2) +-#define MT8135_PIN_143_DPIR1__FUNC_CM2DAT_2X_5 (MTK_PIN_NO(143) | 4) +- +-#define MT8135_PIN_144_DPIR2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +-#define MT8135_PIN_144_DPIR2__FUNC_DPI0_R2 (MTK_PIN_NO(144) | 1) +-#define MT8135_PIN_144_DPIR2__FUNC_EINT120 (MTK_PIN_NO(144) | 2) +-#define MT8135_PIN_144_DPIR2__FUNC_CM2DAT_2X_6 (MTK_PIN_NO(144) | 4) +- +-#define MT8135_PIN_145_DPIR4__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +-#define MT8135_PIN_145_DPIR4__FUNC_DPI0_R4 (MTK_PIN_NO(145) | 1) +-#define MT8135_PIN_145_DPIR4__FUNC_EINT122 (MTK_PIN_NO(145) | 2) +-#define MT8135_PIN_145_DPIR4__FUNC_CM2DAT_2X_8 (MTK_PIN_NO(145) | 4) +- +-#define MT8135_PIN_146_DPIR5__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +-#define MT8135_PIN_146_DPIR5__FUNC_DPI0_R5 (MTK_PIN_NO(146) | 1) +-#define MT8135_PIN_146_DPIR5__FUNC_EINT123 (MTK_PIN_NO(146) | 2) +-#define MT8135_PIN_146_DPIR5__FUNC_CM2DAT_2X_9 (MTK_PIN_NO(146) | 4) +- +-#define MT8135_PIN_147_DPIR6__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +-#define MT8135_PIN_147_DPIR6__FUNC_DPI0_R6 (MTK_PIN_NO(147) | 1) +-#define MT8135_PIN_147_DPIR6__FUNC_EINT124 (MTK_PIN_NO(147) | 2) +-#define MT8135_PIN_147_DPIR6__FUNC_CM2VSYNC_2X (MTK_PIN_NO(147) | 4) +- +-#define MT8135_PIN_148_DPIR7__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +-#define MT8135_PIN_148_DPIR7__FUNC_DPI0_R7 (MTK_PIN_NO(148) | 1) +-#define MT8135_PIN_148_DPIR7__FUNC_EINT125 (MTK_PIN_NO(148) | 2) +-#define MT8135_PIN_148_DPIR7__FUNC_CM2HSYNC_2X (MTK_PIN_NO(148) | 4) +- +-#define MT8135_PIN_149_TDN3__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +-#define MT8135_PIN_149_TDN3__FUNC_EINT36 (MTK_PIN_NO(149) | 2) +- +-#define MT8135_PIN_150_TDP3__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +-#define MT8135_PIN_150_TDP3__FUNC_EINT35 (MTK_PIN_NO(150) | 2) +- +-#define MT8135_PIN_151_TDN2__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +-#define MT8135_PIN_151_TDN2__FUNC_EINT169 (MTK_PIN_NO(151) | 2) +- +-#define MT8135_PIN_152_TDP2__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +-#define MT8135_PIN_152_TDP2__FUNC_EINT168 (MTK_PIN_NO(152) | 2) +- +-#define MT8135_PIN_153_TCN__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +-#define MT8135_PIN_153_TCN__FUNC_EINT163 (MTK_PIN_NO(153) | 2) +- +-#define MT8135_PIN_154_TCP__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +-#define MT8135_PIN_154_TCP__FUNC_EINT162 (MTK_PIN_NO(154) | 2) +- +-#define MT8135_PIN_155_TDN1__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +-#define MT8135_PIN_155_TDN1__FUNC_EINT167 (MTK_PIN_NO(155) | 2) +- +-#define MT8135_PIN_156_TDP1__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +-#define MT8135_PIN_156_TDP1__FUNC_EINT166 (MTK_PIN_NO(156) | 2) +- +-#define MT8135_PIN_157_TDN0__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +-#define MT8135_PIN_157_TDN0__FUNC_EINT165 (MTK_PIN_NO(157) | 2) +- +-#define MT8135_PIN_158_TDP0__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +-#define MT8135_PIN_158_TDP0__FUNC_EINT164 (MTK_PIN_NO(158) | 2) +- +-#define MT8135_PIN_159_RDN3__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +-#define MT8135_PIN_159_RDN3__FUNC_EINT18 (MTK_PIN_NO(159) | 2) +- +-#define MT8135_PIN_160_RDP3__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +-#define MT8135_PIN_160_RDP3__FUNC_EINT30 (MTK_PIN_NO(160) | 2) +- +-#define MT8135_PIN_161_RDN2__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +-#define MT8135_PIN_161_RDN2__FUNC_EINT31 (MTK_PIN_NO(161) | 2) +- +-#define MT8135_PIN_162_RDP2__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +-#define MT8135_PIN_162_RDP2__FUNC_EINT32 (MTK_PIN_NO(162) | 2) +- +-#define MT8135_PIN_163_RCN__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +-#define MT8135_PIN_163_RCN__FUNC_EINT33 (MTK_PIN_NO(163) | 2) +- +-#define MT8135_PIN_164_RCP__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +-#define MT8135_PIN_164_RCP__FUNC_EINT39 (MTK_PIN_NO(164) | 2) +- +-#define MT8135_PIN_165_RDN1__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +- +-#define MT8135_PIN_166_RDP1__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +- +-#define MT8135_PIN_167_RDN0__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +- +-#define MT8135_PIN_168_RDP0__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +- +-#define MT8135_PIN_169_RDN1_A__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +-#define MT8135_PIN_169_RDN1_A__FUNC_CMDAT6 (MTK_PIN_NO(169) | 1) +-#define MT8135_PIN_169_RDN1_A__FUNC_EINT175 (MTK_PIN_NO(169) | 2) +- +-#define MT8135_PIN_170_RDP1_A__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +-#define MT8135_PIN_170_RDP1_A__FUNC_CMDAT7 (MTK_PIN_NO(170) | 1) +-#define MT8135_PIN_170_RDP1_A__FUNC_EINT174 (MTK_PIN_NO(170) | 2) +- +-#define MT8135_PIN_171_RCN_A__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +-#define MT8135_PIN_171_RCN_A__FUNC_CMDAT8 (MTK_PIN_NO(171) | 1) +-#define MT8135_PIN_171_RCN_A__FUNC_EINT171 (MTK_PIN_NO(171) | 2) +- +-#define MT8135_PIN_172_RCP_A__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +-#define MT8135_PIN_172_RCP_A__FUNC_CMDAT9 (MTK_PIN_NO(172) | 1) +-#define MT8135_PIN_172_RCP_A__FUNC_EINT170 (MTK_PIN_NO(172) | 2) +- +-#define MT8135_PIN_173_RDN0_A__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +-#define MT8135_PIN_173_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(173) | 1) +-#define MT8135_PIN_173_RDN0_A__FUNC_EINT173 (MTK_PIN_NO(173) | 2) +- +-#define MT8135_PIN_174_RDP0_A__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +-#define MT8135_PIN_174_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(174) | 1) +-#define MT8135_PIN_174_RDP0_A__FUNC_EINT172 (MTK_PIN_NO(174) | 2) +- +-#define MT8135_PIN_175_RDN1_B__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +-#define MT8135_PIN_175_RDN1_B__FUNC_CMDAT2 (MTK_PIN_NO(175) | 1) +-#define MT8135_PIN_175_RDN1_B__FUNC_EINT181 (MTK_PIN_NO(175) | 2) +-#define MT8135_PIN_175_RDN1_B__FUNC_CMCSD2 (MTK_PIN_NO(175) | 3) +- +-#define MT8135_PIN_176_RDP1_B__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +-#define MT8135_PIN_176_RDP1_B__FUNC_CMDAT3 (MTK_PIN_NO(176) | 1) +-#define MT8135_PIN_176_RDP1_B__FUNC_EINT180 (MTK_PIN_NO(176) | 2) +-#define MT8135_PIN_176_RDP1_B__FUNC_CMCSD3 (MTK_PIN_NO(176) | 3) +- +-#define MT8135_PIN_177_RCN_B__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +-#define MT8135_PIN_177_RCN_B__FUNC_CMDAT4 (MTK_PIN_NO(177) | 1) +-#define MT8135_PIN_177_RCN_B__FUNC_EINT177 (MTK_PIN_NO(177) | 2) +- +-#define MT8135_PIN_178_RCP_B__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +-#define MT8135_PIN_178_RCP_B__FUNC_CMDAT5 (MTK_PIN_NO(178) | 1) +-#define MT8135_PIN_178_RCP_B__FUNC_EINT176 (MTK_PIN_NO(178) | 2) +- +-#define MT8135_PIN_179_RDN0_B__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +-#define MT8135_PIN_179_RDN0_B__FUNC_CMDAT0 (MTK_PIN_NO(179) | 1) +-#define MT8135_PIN_179_RDN0_B__FUNC_EINT179 (MTK_PIN_NO(179) | 2) +-#define MT8135_PIN_179_RDN0_B__FUNC_CMCSD0 (MTK_PIN_NO(179) | 3) +- +-#define MT8135_PIN_180_RDP0_B__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +-#define MT8135_PIN_180_RDP0_B__FUNC_CMDAT1 (MTK_PIN_NO(180) | 1) +-#define MT8135_PIN_180_RDP0_B__FUNC_EINT178 (MTK_PIN_NO(180) | 2) +-#define MT8135_PIN_180_RDP0_B__FUNC_CMCSD1 (MTK_PIN_NO(180) | 3) +- +-#define MT8135_PIN_181_CMPCLK__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +-#define MT8135_PIN_181_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(181) | 1) +-#define MT8135_PIN_181_CMPCLK__FUNC_EINT182 (MTK_PIN_NO(181) | 2) +-#define MT8135_PIN_181_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(181) | 3) +-#define MT8135_PIN_181_CMPCLK__FUNC_CM2MCLK_4X (MTK_PIN_NO(181) | 4) +-#define MT8135_PIN_181_CMPCLK__FUNC_TS_AUXADC_SEL_3 (MTK_PIN_NO(181) | 5) +-#define MT8135_PIN_181_CMPCLK__FUNC_VENC_TEST_CK (MTK_PIN_NO(181) | 6) +-#define MT8135_PIN_181_CMPCLK__FUNC_TESTA_OUT27 (MTK_PIN_NO(181) | 7) +- +-#define MT8135_PIN_182_CMMCLK__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +-#define MT8135_PIN_182_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(182) | 1) +-#define MT8135_PIN_182_CMMCLK__FUNC_EINT183 (MTK_PIN_NO(182) | 2) +-#define MT8135_PIN_182_CMMCLK__FUNC_TS_AUXADC_SEL_2 (MTK_PIN_NO(182) | 5) +-#define MT8135_PIN_182_CMMCLK__FUNC_TESTA_OUT28 (MTK_PIN_NO(182) | 7) +- +-#define MT8135_PIN_183_CMRST__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +-#define MT8135_PIN_183_CMRST__FUNC_CMRST (MTK_PIN_NO(183) | 1) +-#define MT8135_PIN_183_CMRST__FUNC_EINT185 (MTK_PIN_NO(183) | 2) +-#define MT8135_PIN_183_CMRST__FUNC_TS_AUXADC_SEL_1 (MTK_PIN_NO(183) | 5) +-#define MT8135_PIN_183_CMRST__FUNC_TESTA_OUT30 (MTK_PIN_NO(183) | 7) +- +-#define MT8135_PIN_184_CMPDN__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +-#define MT8135_PIN_184_CMPDN__FUNC_CMPDN (MTK_PIN_NO(184) | 1) +-#define MT8135_PIN_184_CMPDN__FUNC_EINT184 (MTK_PIN_NO(184) | 2) +-#define MT8135_PIN_184_CMPDN__FUNC_TS_AUXADC_SEL_0 (MTK_PIN_NO(184) | 5) +-#define MT8135_PIN_184_CMPDN__FUNC_TESTA_OUT29 (MTK_PIN_NO(184) | 7) +- +-#define MT8135_PIN_185_CMFLASH__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +-#define MT8135_PIN_185_CMFLASH__FUNC_CMFLASH (MTK_PIN_NO(185) | 1) +-#define MT8135_PIN_185_CMFLASH__FUNC_EINT186 (MTK_PIN_NO(185) | 2) +-#define MT8135_PIN_185_CMFLASH__FUNC_CM2MCLK_3X (MTK_PIN_NO(185) | 3) +-#define MT8135_PIN_185_CMFLASH__FUNC_MFG_TEST_CK_1 (MTK_PIN_NO(185) | 6) +-#define MT8135_PIN_185_CMFLASH__FUNC_TESTA_OUT31 (MTK_PIN_NO(185) | 7) +- +-#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +-#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_MRG_I2S_P_CLK (MTK_PIN_NO(186) | 1) +-#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_EINT14 (MTK_PIN_NO(186) | 2) +-#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(186) | 3) +-#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_PCM0_CK (MTK_PIN_NO(186) | 4) +-#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_DSP2_ICK (MTK_PIN_NO(186) | 5) +-#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_IMG_TEST_CK (MTK_PIN_NO(186) | 6) +-#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_USB_SCL (MTK_PIN_NO(186) | 7) +- +-#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +-#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_MRG_I2S_SYNC (MTK_PIN_NO(187) | 1) +-#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_EINT16 (MTK_PIN_NO(187) | 2) +-#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_I2SIN_WS (MTK_PIN_NO(187) | 3) +-#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_PCM0_WS (MTK_PIN_NO(187) | 4) +-#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_DISP_TEST_CK (MTK_PIN_NO(187) | 6) +- +-#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +-#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MRG_I2S_PCM_RX (MTK_PIN_NO(188) | 1) +-#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_EINT15 (MTK_PIN_NO(188) | 2) +-#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_I2SIN_DAT (MTK_PIN_NO(188) | 3) +-#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_PCM0_DI (MTK_PIN_NO(188) | 4) +-#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_DSP2_ID (MTK_PIN_NO(188) | 5) +-#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MFG_TEST_CK (MTK_PIN_NO(188) | 6) +-#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_USB_SDA (MTK_PIN_NO(188) | 7) +- +-#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +-#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_MRG_I2S_PCM_TX (MTK_PIN_NO(189) | 1) +-#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_EINT17 (MTK_PIN_NO(189) | 2) +-#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_I2SOUT_DAT (MTK_PIN_NO(189) | 3) +-#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_PCM0_DO (MTK_PIN_NO(189) | 4) +-#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_VDEC_TEST_CK (MTK_PIN_NO(189) | 6) +- +-#define MT8135_PIN_190_SRCLKENAI__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +-#define MT8135_PIN_190_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(190) | 1) +- +-#define MT8135_PIN_191_URXD3__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +-#define MT8135_PIN_191_URXD3__FUNC_URXD3 (MTK_PIN_NO(191) | 1) +-#define MT8135_PIN_191_URXD3__FUNC_EINT87 (MTK_PIN_NO(191) | 2) +-#define MT8135_PIN_191_URXD3__FUNC_UTXD3 (MTK_PIN_NO(191) | 3) +-#define MT8135_PIN_191_URXD3__FUNC_TS_AUX_ST (MTK_PIN_NO(191) | 5) +-#define MT8135_PIN_191_URXD3__FUNC_PWM4 (MTK_PIN_NO(191) | 6) +- +-#define MT8135_PIN_192_UTXD3__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +-#define MT8135_PIN_192_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(192) | 1) +-#define MT8135_PIN_192_UTXD3__FUNC_EINT86 (MTK_PIN_NO(192) | 2) +-#define MT8135_PIN_192_UTXD3__FUNC_URXD3 (MTK_PIN_NO(192) | 3) +-#define MT8135_PIN_192_UTXD3__FUNC_TS_AUX_CS_B (MTK_PIN_NO(192) | 5) +-#define MT8135_PIN_192_UTXD3__FUNC_PWM3 (MTK_PIN_NO(192) | 6) +- +-#define MT8135_PIN_193_SDA2__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +-#define MT8135_PIN_193_SDA2__FUNC_SDA2 (MTK_PIN_NO(193) | 1) +-#define MT8135_PIN_193_SDA2__FUNC_EINT95 (MTK_PIN_NO(193) | 2) +-#define MT8135_PIN_193_SDA2__FUNC_CLKM5 (MTK_PIN_NO(193) | 3) +-#define MT8135_PIN_193_SDA2__FUNC_PWM5 (MTK_PIN_NO(193) | 4) +-#define MT8135_PIN_193_SDA2__FUNC_TS_AUX_PWDB (MTK_PIN_NO(193) | 5) +- +-#define MT8135_PIN_194_SCL2__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +-#define MT8135_PIN_194_SCL2__FUNC_SCL2 (MTK_PIN_NO(194) | 1) +-#define MT8135_PIN_194_SCL2__FUNC_EINT94 (MTK_PIN_NO(194) | 2) +-#define MT8135_PIN_194_SCL2__FUNC_CLKM4 (MTK_PIN_NO(194) | 3) +-#define MT8135_PIN_194_SCL2__FUNC_PWM4 (MTK_PIN_NO(194) | 4) +-#define MT8135_PIN_194_SCL2__FUNC_TS_AUXADC_TEST_CK (MTK_PIN_NO(194) | 5) +- +-#define MT8135_PIN_195_SDA1__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +-#define MT8135_PIN_195_SDA1__FUNC_SDA1 (MTK_PIN_NO(195) | 1) +-#define MT8135_PIN_195_SDA1__FUNC_EINT93 (MTK_PIN_NO(195) | 2) +-#define MT8135_PIN_195_SDA1__FUNC_CLKM3 (MTK_PIN_NO(195) | 3) +-#define MT8135_PIN_195_SDA1__FUNC_PWM3 (MTK_PIN_NO(195) | 4) +-#define MT8135_PIN_195_SDA1__FUNC_TS_AUX_SCLK_PWDB (MTK_PIN_NO(195) | 5) +- +-#define MT8135_PIN_196_SCL1__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +-#define MT8135_PIN_196_SCL1__FUNC_SCL1 (MTK_PIN_NO(196) | 1) +-#define MT8135_PIN_196_SCL1__FUNC_EINT92 (MTK_PIN_NO(196) | 2) +-#define MT8135_PIN_196_SCL1__FUNC_CLKM2 (MTK_PIN_NO(196) | 3) +-#define MT8135_PIN_196_SCL1__FUNC_PWM2 (MTK_PIN_NO(196) | 4) +-#define MT8135_PIN_196_SCL1__FUNC_TS_AUX_DIN (MTK_PIN_NO(196) | 5) +- +-#define MT8135_PIN_197_MSDC3_DAT2__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +-#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(197) | 1) +-#define MT8135_PIN_197_MSDC3_DAT2__FUNC_EINT71 (MTK_PIN_NO(197) | 2) +-#define MT8135_PIN_197_MSDC3_DAT2__FUNC_SCL6 (MTK_PIN_NO(197) | 3) +-#define MT8135_PIN_197_MSDC3_DAT2__FUNC_PWM5 (MTK_PIN_NO(197) | 4) +-#define MT8135_PIN_197_MSDC3_DAT2__FUNC_CLKM4 (MTK_PIN_NO(197) | 5) +-#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MFG_TEST_CK_2 (MTK_PIN_NO(197) | 6) +- +-#define MT8135_PIN_198_MSDC3_DAT3__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +-#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(198) | 1) +-#define MT8135_PIN_198_MSDC3_DAT3__FUNC_EINT72 (MTK_PIN_NO(198) | 2) +-#define MT8135_PIN_198_MSDC3_DAT3__FUNC_SDA6 (MTK_PIN_NO(198) | 3) +-#define MT8135_PIN_198_MSDC3_DAT3__FUNC_PWM6 (MTK_PIN_NO(198) | 4) +-#define MT8135_PIN_198_MSDC3_DAT3__FUNC_CLKM5 (MTK_PIN_NO(198) | 5) +-#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MFG_TEST_CK_3 (MTK_PIN_NO(198) | 6) +- +-#define MT8135_PIN_199_MSDC3_CMD__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +-#define MT8135_PIN_199_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(199) | 1) +-#define MT8135_PIN_199_MSDC3_CMD__FUNC_EINT68 (MTK_PIN_NO(199) | 2) +-#define MT8135_PIN_199_MSDC3_CMD__FUNC_SDA2 (MTK_PIN_NO(199) | 3) +-#define MT8135_PIN_199_MSDC3_CMD__FUNC_PWM2 (MTK_PIN_NO(199) | 4) +-#define MT8135_PIN_199_MSDC3_CMD__FUNC_CLKM1 (MTK_PIN_NO(199) | 5) +-#define MT8135_PIN_199_MSDC3_CMD__FUNC_MFG_TEST_CK_4 (MTK_PIN_NO(199) | 6) +- +-#define MT8135_PIN_200_MSDC3_CLK__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +-#define MT8135_PIN_200_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(200) | 1) +-#define MT8135_PIN_200_MSDC3_CLK__FUNC_EINT67 (MTK_PIN_NO(200) | 2) +-#define MT8135_PIN_200_MSDC3_CLK__FUNC_SCL2 (MTK_PIN_NO(200) | 3) +-#define MT8135_PIN_200_MSDC3_CLK__FUNC_PWM1 (MTK_PIN_NO(200) | 4) +-#define MT8135_PIN_200_MSDC3_CLK__FUNC_CLKM0 (MTK_PIN_NO(200) | 5) +- +-#define MT8135_PIN_201_MSDC3_DAT1__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +-#define MT8135_PIN_201_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(201) | 1) +-#define MT8135_PIN_201_MSDC3_DAT1__FUNC_EINT70 (MTK_PIN_NO(201) | 2) +-#define MT8135_PIN_201_MSDC3_DAT1__FUNC_SDA3 (MTK_PIN_NO(201) | 3) +-#define MT8135_PIN_201_MSDC3_DAT1__FUNC_PWM4 (MTK_PIN_NO(201) | 4) +-#define MT8135_PIN_201_MSDC3_DAT1__FUNC_CLKM3 (MTK_PIN_NO(201) | 5) +- +-#define MT8135_PIN_202_MSDC3_DAT0__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +-#define MT8135_PIN_202_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(202) | 1) +-#define MT8135_PIN_202_MSDC3_DAT0__FUNC_EINT69 (MTK_PIN_NO(202) | 2) +-#define MT8135_PIN_202_MSDC3_DAT0__FUNC_SCL3 (MTK_PIN_NO(202) | 3) +-#define MT8135_PIN_202_MSDC3_DAT0__FUNC_PWM3 (MTK_PIN_NO(202) | 4) +-#define MT8135_PIN_202_MSDC3_DAT0__FUNC_CLKM2 (MTK_PIN_NO(202) | 5) +- +-#endif /* __DTS_MT8135_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt8183-pinfunc.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt8183-pinfunc.h +deleted file mode 100644 +index 6221cd712718..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt8183-pinfunc.h ++++ /dev/null +@@ -1,1120 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2018 MediaTek Inc. +- * Author: Zhiyong Tao +- * +- */ +- +-#ifndef __MT8183_PINFUNC_H +-#define __MT8183_PINFUNC_H +- +-#include +- +-#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +-#define PINMUX_GPIO0__FUNC_MRG_SYNC (MTK_PIN_NO(0) | 1) +-#define PINMUX_GPIO0__FUNC_PCM0_SYNC (MTK_PIN_NO(0) | 2) +-#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 3) +-#define PINMUX_GPIO0__FUNC_SRCLKENAI0 (MTK_PIN_NO(0) | 4) +-#define PINMUX_GPIO0__FUNC_SCP_SPI2_CS (MTK_PIN_NO(0) | 5) +-#define PINMUX_GPIO0__FUNC_I2S3_MCK (MTK_PIN_NO(0) | 6) +-#define PINMUX_GPIO0__FUNC_SPI2_CSB (MTK_PIN_NO(0) | 7) +- +-#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +-#define PINMUX_GPIO1__FUNC_MRG_CLK (MTK_PIN_NO(1) | 1) +-#define PINMUX_GPIO1__FUNC_PCM0_CLK (MTK_PIN_NO(1) | 2) +-#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 3) +-#define PINMUX_GPIO1__FUNC_CLKM3 (MTK_PIN_NO(1) | 4) +-#define PINMUX_GPIO1__FUNC_SCP_SPI2_MO (MTK_PIN_NO(1) | 5) +-#define PINMUX_GPIO1__FUNC_I2S3_BCK (MTK_PIN_NO(1) | 6) +-#define PINMUX_GPIO1__FUNC_SPI2_MO (MTK_PIN_NO(1) | 7) +- +-#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +-#define PINMUX_GPIO2__FUNC_MRG_DO (MTK_PIN_NO(2) | 1) +-#define PINMUX_GPIO2__FUNC_PCM0_DO (MTK_PIN_NO(2) | 2) +-#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 3) +-#define PINMUX_GPIO2__FUNC_SCL6 (MTK_PIN_NO(2) | 4) +-#define PINMUX_GPIO2__FUNC_SCP_SPI2_CK (MTK_PIN_NO(2) | 5) +-#define PINMUX_GPIO2__FUNC_I2S3_LRCK (MTK_PIN_NO(2) | 6) +-#define PINMUX_GPIO2__FUNC_SPI2_CLK (MTK_PIN_NO(2) | 7) +- +-#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +-#define PINMUX_GPIO3__FUNC_MRG_DI (MTK_PIN_NO(3) | 1) +-#define PINMUX_GPIO3__FUNC_PCM0_DI (MTK_PIN_NO(3) | 2) +-#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 3) +-#define PINMUX_GPIO3__FUNC_SDA6 (MTK_PIN_NO(3) | 4) +-#define PINMUX_GPIO3__FUNC_TDM_MCK (MTK_PIN_NO(3) | 5) +-#define PINMUX_GPIO3__FUNC_I2S3_DO (MTK_PIN_NO(3) | 6) +-#define PINMUX_GPIO3__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(3) | 7) +- +-#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +-#define PINMUX_GPIO4__FUNC_PWM_B (MTK_PIN_NO(4) | 1) +-#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2) +-#define PINMUX_GPIO4__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(4) | 3) +-#define PINMUX_GPIO4__FUNC_MD_URXD1 (MTK_PIN_NO(4) | 4) +-#define PINMUX_GPIO4__FUNC_TDM_BCK (MTK_PIN_NO(4) | 5) +-#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6) +-#define PINMUX_GPIO4__FUNC_DAP_MD32_SWD (MTK_PIN_NO(4) | 7) +- +-#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +-#define PINMUX_GPIO5__FUNC_PWM_C (MTK_PIN_NO(5) | 1) +-#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2) +-#define PINMUX_GPIO5__FUNC_SSPM_URXD_AO (MTK_PIN_NO(5) | 3) +-#define PINMUX_GPIO5__FUNC_MD_UTXD1 (MTK_PIN_NO(5) | 4) +-#define PINMUX_GPIO5__FUNC_TDM_LRCK (MTK_PIN_NO(5) | 5) +-#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6) +-#define PINMUX_GPIO5__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(5) | 7) +- +-#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +-#define PINMUX_GPIO6__FUNC_PWM_A (MTK_PIN_NO(6) | 1) +-#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2) +-#define PINMUX_GPIO6__FUNC_IDDIG (MTK_PIN_NO(6) | 3) +-#define PINMUX_GPIO6__FUNC_MD_URXD0 (MTK_PIN_NO(6) | 4) +-#define PINMUX_GPIO6__FUNC_TDM_DATA0 (MTK_PIN_NO(6) | 5) +-#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6) +-#define PINMUX_GPIO6__FUNC_CMFLASH (MTK_PIN_NO(6) | 7) +- +-#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +-#define PINMUX_GPIO7__FUNC_SPI1_B_MI (MTK_PIN_NO(7) | 1) +-#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2) +-#define PINMUX_GPIO7__FUNC_USB_DRVVBUS (MTK_PIN_NO(7) | 3) +-#define PINMUX_GPIO7__FUNC_MD_UTXD0 (MTK_PIN_NO(7) | 4) +-#define PINMUX_GPIO7__FUNC_TDM_DATA1 (MTK_PIN_NO(7) | 5) +-#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6) +-#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 7) +- +-#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +-#define PINMUX_GPIO8__FUNC_SPI1_B_CSB (MTK_PIN_NO(8) | 1) +-#define PINMUX_GPIO8__FUNC_ANT_SEL3 (MTK_PIN_NO(8) | 2) +-#define PINMUX_GPIO8__FUNC_SCL7 (MTK_PIN_NO(8) | 3) +-#define PINMUX_GPIO8__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(8) | 4) +-#define PINMUX_GPIO8__FUNC_TDM_DATA2 (MTK_PIN_NO(8) | 5) +-#define PINMUX_GPIO8__FUNC_MD_INT0 (MTK_PIN_NO(8) | 6) +-#define PINMUX_GPIO8__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(8) | 7) +- +-#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +-#define PINMUX_GPIO9__FUNC_SPI1_B_MO (MTK_PIN_NO(9) | 1) +-#define PINMUX_GPIO9__FUNC_ANT_SEL4 (MTK_PIN_NO(9) | 2) +-#define PINMUX_GPIO9__FUNC_CMMCLK2 (MTK_PIN_NO(9) | 3) +-#define PINMUX_GPIO9__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(9) | 4) +-#define PINMUX_GPIO9__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(9) | 5) +-#define PINMUX_GPIO9__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(9) | 6) +-#define PINMUX_GPIO9__FUNC_DBG_MON_B10 (MTK_PIN_NO(9) | 7) +- +-#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +-#define PINMUX_GPIO10__FUNC_SPI1_B_CLK (MTK_PIN_NO(10) | 1) +-#define PINMUX_GPIO10__FUNC_ANT_SEL5 (MTK_PIN_NO(10) | 2) +-#define PINMUX_GPIO10__FUNC_CMMCLK3 (MTK_PIN_NO(10) | 3) +-#define PINMUX_GPIO10__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(10) | 4) +-#define PINMUX_GPIO10__FUNC_TDM_DATA3 (MTK_PIN_NO(10) | 5) +-#define PINMUX_GPIO10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 6) +-#define PINMUX_GPIO10__FUNC_DBG_MON_B11 (MTK_PIN_NO(10) | 7) +- +-#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +-#define PINMUX_GPIO11__FUNC_TP_URXD1_AO (MTK_PIN_NO(11) | 1) +-#define PINMUX_GPIO11__FUNC_IDDIG (MTK_PIN_NO(11) | 2) +-#define PINMUX_GPIO11__FUNC_SCL6 (MTK_PIN_NO(11) | 3) +-#define PINMUX_GPIO11__FUNC_UCTS1 (MTK_PIN_NO(11) | 4) +-#define PINMUX_GPIO11__FUNC_UCTS0 (MTK_PIN_NO(11) | 5) +-#define PINMUX_GPIO11__FUNC_SRCLKENAI1 (MTK_PIN_NO(11) | 6) +-#define PINMUX_GPIO11__FUNC_I2S5_MCK (MTK_PIN_NO(11) | 7) +- +-#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +-#define PINMUX_GPIO12__FUNC_TP_UTXD1_AO (MTK_PIN_NO(12) | 1) +-#define PINMUX_GPIO12__FUNC_USB_DRVVBUS (MTK_PIN_NO(12) | 2) +-#define PINMUX_GPIO12__FUNC_SDA6 (MTK_PIN_NO(12) | 3) +-#define PINMUX_GPIO12__FUNC_URTS1 (MTK_PIN_NO(12) | 4) +-#define PINMUX_GPIO12__FUNC_URTS0 (MTK_PIN_NO(12) | 5) +-#define PINMUX_GPIO12__FUNC_I2S2_DI2 (MTK_PIN_NO(12) | 6) +-#define PINMUX_GPIO12__FUNC_I2S5_BCK (MTK_PIN_NO(12) | 7) +- +-#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +-#define PINMUX_GPIO13__FUNC_DBPI_D0 (MTK_PIN_NO(13) | 1) +-#define PINMUX_GPIO13__FUNC_SPI5_MI (MTK_PIN_NO(13) | 2) +-#define PINMUX_GPIO13__FUNC_PCM0_SYNC (MTK_PIN_NO(13) | 3) +-#define PINMUX_GPIO13__FUNC_MD_URXD0 (MTK_PIN_NO(13) | 4) +-#define PINMUX_GPIO13__FUNC_ANT_SEL3 (MTK_PIN_NO(13) | 5) +-#define PINMUX_GPIO13__FUNC_I2S0_MCK (MTK_PIN_NO(13) | 6) +-#define PINMUX_GPIO13__FUNC_DBG_MON_B15 (MTK_PIN_NO(13) | 7) +- +-#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +-#define PINMUX_GPIO14__FUNC_DBPI_D1 (MTK_PIN_NO(14) | 1) +-#define PINMUX_GPIO14__FUNC_SPI5_CSB (MTK_PIN_NO(14) | 2) +-#define PINMUX_GPIO14__FUNC_PCM0_CLK (MTK_PIN_NO(14) | 3) +-#define PINMUX_GPIO14__FUNC_MD_UTXD0 (MTK_PIN_NO(14) | 4) +-#define PINMUX_GPIO14__FUNC_ANT_SEL4 (MTK_PIN_NO(14) | 5) +-#define PINMUX_GPIO14__FUNC_I2S0_BCK (MTK_PIN_NO(14) | 6) +-#define PINMUX_GPIO14__FUNC_DBG_MON_B16 (MTK_PIN_NO(14) | 7) +- +-#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +-#define PINMUX_GPIO15__FUNC_DBPI_D2 (MTK_PIN_NO(15) | 1) +-#define PINMUX_GPIO15__FUNC_SPI5_MO (MTK_PIN_NO(15) | 2) +-#define PINMUX_GPIO15__FUNC_PCM0_DO (MTK_PIN_NO(15) | 3) +-#define PINMUX_GPIO15__FUNC_MD_URXD1 (MTK_PIN_NO(15) | 4) +-#define PINMUX_GPIO15__FUNC_ANT_SEL5 (MTK_PIN_NO(15) | 5) +-#define PINMUX_GPIO15__FUNC_I2S0_LRCK (MTK_PIN_NO(15) | 6) +-#define PINMUX_GPIO15__FUNC_DBG_MON_B17 (MTK_PIN_NO(15) | 7) +- +-#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +-#define PINMUX_GPIO16__FUNC_DBPI_D3 (MTK_PIN_NO(16) | 1) +-#define PINMUX_GPIO16__FUNC_SPI5_CLK (MTK_PIN_NO(16) | 2) +-#define PINMUX_GPIO16__FUNC_PCM0_DI (MTK_PIN_NO(16) | 3) +-#define PINMUX_GPIO16__FUNC_MD_UTXD1 (MTK_PIN_NO(16) | 4) +-#define PINMUX_GPIO16__FUNC_ANT_SEL6 (MTK_PIN_NO(16) | 5) +-#define PINMUX_GPIO16__FUNC_I2S0_DI (MTK_PIN_NO(16) | 6) +-#define PINMUX_GPIO16__FUNC_DBG_MON_B23 (MTK_PIN_NO(16) | 7) +- +-#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +-#define PINMUX_GPIO17__FUNC_DBPI_D4 (MTK_PIN_NO(17) | 1) +-#define PINMUX_GPIO17__FUNC_SPI4_MI (MTK_PIN_NO(17) | 2) +-#define PINMUX_GPIO17__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(17) | 3) +-#define PINMUX_GPIO17__FUNC_MD_INT0 (MTK_PIN_NO(17) | 4) +-#define PINMUX_GPIO17__FUNC_ANT_SEL7 (MTK_PIN_NO(17) | 5) +-#define PINMUX_GPIO17__FUNC_I2S3_MCK (MTK_PIN_NO(17) | 6) +-#define PINMUX_GPIO17__FUNC_DBG_MON_A1 (MTK_PIN_NO(17) | 7) +- +-#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +-#define PINMUX_GPIO18__FUNC_DBPI_D5 (MTK_PIN_NO(18) | 1) +-#define PINMUX_GPIO18__FUNC_SPI4_CSB (MTK_PIN_NO(18) | 2) +-#define PINMUX_GPIO18__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(18) | 3) +-#define PINMUX_GPIO18__FUNC_MD_INT0 (MTK_PIN_NO(18) | 4) +-#define PINMUX_GPIO18__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(18) | 5) +-#define PINMUX_GPIO18__FUNC_I2S3_BCK (MTK_PIN_NO(18) | 6) +-#define PINMUX_GPIO18__FUNC_DBG_MON_A2 (MTK_PIN_NO(18) | 7) +- +-#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +-#define PINMUX_GPIO19__FUNC_DBPI_D6 (MTK_PIN_NO(19) | 1) +-#define PINMUX_GPIO19__FUNC_SPI4_MO (MTK_PIN_NO(19) | 2) +-#define PINMUX_GPIO19__FUNC_CONN_MCU_TDO (MTK_PIN_NO(19) | 3) +-#define PINMUX_GPIO19__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(19) | 4) +-#define PINMUX_GPIO19__FUNC_URXD1 (MTK_PIN_NO(19) | 5) +-#define PINMUX_GPIO19__FUNC_I2S3_LRCK (MTK_PIN_NO(19) | 6) +-#define PINMUX_GPIO19__FUNC_DBG_MON_A3 (MTK_PIN_NO(19) | 7) +- +-#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +-#define PINMUX_GPIO20__FUNC_DBPI_D7 (MTK_PIN_NO(20) | 1) +-#define PINMUX_GPIO20__FUNC_SPI4_CLK (MTK_PIN_NO(20) | 2) +-#define PINMUX_GPIO20__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(20) | 3) +-#define PINMUX_GPIO20__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(20) | 4) +-#define PINMUX_GPIO20__FUNC_UTXD1 (MTK_PIN_NO(20) | 5) +-#define PINMUX_GPIO20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 6) +-#define PINMUX_GPIO20__FUNC_DBG_MON_A19 (MTK_PIN_NO(20) | 7) +- +-#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +-#define PINMUX_GPIO21__FUNC_DBPI_D8 (MTK_PIN_NO(21) | 1) +-#define PINMUX_GPIO21__FUNC_SPI3_MI (MTK_PIN_NO(21) | 2) +-#define PINMUX_GPIO21__FUNC_CONN_MCU_TMS (MTK_PIN_NO(21) | 3) +-#define PINMUX_GPIO21__FUNC_DAP_MD32_SWD (MTK_PIN_NO(21) | 4) +-#define PINMUX_GPIO21__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(21) | 5) +-#define PINMUX_GPIO21__FUNC_I2S2_MCK (MTK_PIN_NO(21) | 6) +-#define PINMUX_GPIO21__FUNC_DBG_MON_B5 (MTK_PIN_NO(21) | 7) +- +-#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +-#define PINMUX_GPIO22__FUNC_DBPI_D9 (MTK_PIN_NO(22) | 1) +-#define PINMUX_GPIO22__FUNC_SPI3_CSB (MTK_PIN_NO(22) | 2) +-#define PINMUX_GPIO22__FUNC_CONN_MCU_TCK (MTK_PIN_NO(22) | 3) +-#define PINMUX_GPIO22__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(22) | 4) +-#define PINMUX_GPIO22__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(22) | 5) +-#define PINMUX_GPIO22__FUNC_I2S2_BCK (MTK_PIN_NO(22) | 6) +-#define PINMUX_GPIO22__FUNC_DBG_MON_B6 (MTK_PIN_NO(22) | 7) +- +-#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +-#define PINMUX_GPIO23__FUNC_DBPI_D10 (MTK_PIN_NO(23) | 1) +-#define PINMUX_GPIO23__FUNC_SPI3_MO (MTK_PIN_NO(23) | 2) +-#define PINMUX_GPIO23__FUNC_CONN_MCU_TDI (MTK_PIN_NO(23) | 3) +-#define PINMUX_GPIO23__FUNC_UCTS1 (MTK_PIN_NO(23) | 4) +-#define PINMUX_GPIO23__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5) +-#define PINMUX_GPIO23__FUNC_I2S2_LRCK (MTK_PIN_NO(23) | 6) +-#define PINMUX_GPIO23__FUNC_DBG_MON_B7 (MTK_PIN_NO(23) | 7) +- +-#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +-#define PINMUX_GPIO24__FUNC_DBPI_D11 (MTK_PIN_NO(24) | 1) +-#define PINMUX_GPIO24__FUNC_SPI3_CLK (MTK_PIN_NO(24) | 2) +-#define PINMUX_GPIO24__FUNC_SRCLKENAI0 (MTK_PIN_NO(24) | 3) +-#define PINMUX_GPIO24__FUNC_URTS1 (MTK_PIN_NO(24) | 4) +-#define PINMUX_GPIO24__FUNC_IO_JTAG_TCK (MTK_PIN_NO(24) | 5) +-#define PINMUX_GPIO24__FUNC_I2S2_DI (MTK_PIN_NO(24) | 6) +-#define PINMUX_GPIO24__FUNC_DBG_MON_B31 (MTK_PIN_NO(24) | 7) +- +-#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +-#define PINMUX_GPIO25__FUNC_DBPI_HSYNC (MTK_PIN_NO(25) | 1) +-#define PINMUX_GPIO25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 2) +-#define PINMUX_GPIO25__FUNC_SCL6 (MTK_PIN_NO(25) | 3) +-#define PINMUX_GPIO25__FUNC_KPCOL2 (MTK_PIN_NO(25) | 4) +-#define PINMUX_GPIO25__FUNC_IO_JTAG_TMS (MTK_PIN_NO(25) | 5) +-#define PINMUX_GPIO25__FUNC_I2S1_MCK (MTK_PIN_NO(25) | 6) +-#define PINMUX_GPIO25__FUNC_DBG_MON_B0 (MTK_PIN_NO(25) | 7) +- +-#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +-#define PINMUX_GPIO26__FUNC_DBPI_VSYNC (MTK_PIN_NO(26) | 1) +-#define PINMUX_GPIO26__FUNC_ANT_SEL1 (MTK_PIN_NO(26) | 2) +-#define PINMUX_GPIO26__FUNC_SDA6 (MTK_PIN_NO(26) | 3) +-#define PINMUX_GPIO26__FUNC_KPROW2 (MTK_PIN_NO(26) | 4) +-#define PINMUX_GPIO26__FUNC_IO_JTAG_TDI (MTK_PIN_NO(26) | 5) +-#define PINMUX_GPIO26__FUNC_I2S1_BCK (MTK_PIN_NO(26) | 6) +-#define PINMUX_GPIO26__FUNC_DBG_MON_B1 (MTK_PIN_NO(26) | 7) +- +-#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +-#define PINMUX_GPIO27__FUNC_DBPI_DE (MTK_PIN_NO(27) | 1) +-#define PINMUX_GPIO27__FUNC_ANT_SEL2 (MTK_PIN_NO(27) | 2) +-#define PINMUX_GPIO27__FUNC_SCL7 (MTK_PIN_NO(27) | 3) +-#define PINMUX_GPIO27__FUNC_DMIC_CLK (MTK_PIN_NO(27) | 4) +-#define PINMUX_GPIO27__FUNC_IO_JTAG_TDO (MTK_PIN_NO(27) | 5) +-#define PINMUX_GPIO27__FUNC_I2S1_LRCK (MTK_PIN_NO(27) | 6) +-#define PINMUX_GPIO27__FUNC_DBG_MON_B9 (MTK_PIN_NO(27) | 7) +- +-#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +-#define PINMUX_GPIO28__FUNC_DBPI_CK (MTK_PIN_NO(28) | 1) +-#define PINMUX_GPIO28__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(28) | 2) +-#define PINMUX_GPIO28__FUNC_SDA7 (MTK_PIN_NO(28) | 3) +-#define PINMUX_GPIO28__FUNC_DMIC_DAT (MTK_PIN_NO(28) | 4) +-#define PINMUX_GPIO28__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(28) | 5) +-#define PINMUX_GPIO28__FUNC_I2S1_DO (MTK_PIN_NO(28) | 6) +-#define PINMUX_GPIO28__FUNC_DBG_MON_B32 (MTK_PIN_NO(28) | 7) +- +-#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +-#define PINMUX_GPIO29__FUNC_MSDC1_CLK (MTK_PIN_NO(29) | 1) +-#define PINMUX_GPIO29__FUNC_IO_JTAG_TCK (MTK_PIN_NO(29) | 2) +-#define PINMUX_GPIO29__FUNC_UDI_TCK (MTK_PIN_NO(29) | 3) +-#define PINMUX_GPIO29__FUNC_CONN_DSP_JCK (MTK_PIN_NO(29) | 4) +-#define PINMUX_GPIO29__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(29) | 5) +-#define PINMUX_GPIO29__FUNC_PCM1_CLK (MTK_PIN_NO(29) | 6) +-#define PINMUX_GPIO29__FUNC_DBG_MON_A6 (MTK_PIN_NO(29) | 7) +- +-#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +-#define PINMUX_GPIO30__FUNC_MSDC1_DAT3 (MTK_PIN_NO(30) | 1) +-#define PINMUX_GPIO30__FUNC_DAP_MD32_SWD (MTK_PIN_NO(30) | 2) +-#define PINMUX_GPIO30__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 3) +-#define PINMUX_GPIO30__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(30) | 4) +-#define PINMUX_GPIO30__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(30) | 5) +-#define PINMUX_GPIO30__FUNC_PCM1_DI (MTK_PIN_NO(30) | 6) +-#define PINMUX_GPIO30__FUNC_DBG_MON_A7 (MTK_PIN_NO(30) | 7) +- +-#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +-#define PINMUX_GPIO31__FUNC_MSDC1_CMD (MTK_PIN_NO(31) | 1) +-#define PINMUX_GPIO31__FUNC_IO_JTAG_TMS (MTK_PIN_NO(31) | 2) +-#define PINMUX_GPIO31__FUNC_UDI_TMS (MTK_PIN_NO(31) | 3) +-#define PINMUX_GPIO31__FUNC_CONN_DSP_JMS (MTK_PIN_NO(31) | 4) +-#define PINMUX_GPIO31__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(31) | 5) +-#define PINMUX_GPIO31__FUNC_PCM1_SYNC (MTK_PIN_NO(31) | 6) +-#define PINMUX_GPIO31__FUNC_DBG_MON_A8 (MTK_PIN_NO(31) | 7) +- +-#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +-#define PINMUX_GPIO32__FUNC_MSDC1_DAT0 (MTK_PIN_NO(32) | 1) +-#define PINMUX_GPIO32__FUNC_IO_JTAG_TDI (MTK_PIN_NO(32) | 2) +-#define PINMUX_GPIO32__FUNC_UDI_TDI (MTK_PIN_NO(32) | 3) +-#define PINMUX_GPIO32__FUNC_CONN_DSP_JDI (MTK_PIN_NO(32) | 4) +-#define PINMUX_GPIO32__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(32) | 5) +-#define PINMUX_GPIO32__FUNC_PCM1_DO0 (MTK_PIN_NO(32) | 6) +-#define PINMUX_GPIO32__FUNC_DBG_MON_A9 (MTK_PIN_NO(32) | 7) +- +-#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +-#define PINMUX_GPIO33__FUNC_MSDC1_DAT2 (MTK_PIN_NO(33) | 1) +-#define PINMUX_GPIO33__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(33) | 2) +-#define PINMUX_GPIO33__FUNC_UDI_NTRST (MTK_PIN_NO(33) | 3) +-#define PINMUX_GPIO33__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(33) | 4) +-#define PINMUX_GPIO33__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(33) | 5) +-#define PINMUX_GPIO33__FUNC_PCM1_DO2 (MTK_PIN_NO(33) | 6) +-#define PINMUX_GPIO33__FUNC_DBG_MON_A10 (MTK_PIN_NO(33) | 7) +- +-#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +-#define PINMUX_GPIO34__FUNC_MSDC1_DAT1 (MTK_PIN_NO(34) | 1) +-#define PINMUX_GPIO34__FUNC_IO_JTAG_TDO (MTK_PIN_NO(34) | 2) +-#define PINMUX_GPIO34__FUNC_UDI_TDO (MTK_PIN_NO(34) | 3) +-#define PINMUX_GPIO34__FUNC_CONN_DSP_JDO (MTK_PIN_NO(34) | 4) +-#define PINMUX_GPIO34__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(34) | 5) +-#define PINMUX_GPIO34__FUNC_PCM1_DO1 (MTK_PIN_NO(34) | 6) +-#define PINMUX_GPIO34__FUNC_DBG_MON_A11 (MTK_PIN_NO(34) | 7) +- +-#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +-#define PINMUX_GPIO35__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(35) | 1) +-#define PINMUX_GPIO35__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(35) | 2) +-#define PINMUX_GPIO35__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(35) | 3) +-#define PINMUX_GPIO35__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(35) | 5) +-#define PINMUX_GPIO35__FUNC_CONN_DSP_JMS (MTK_PIN_NO(35) | 6) +-#define PINMUX_GPIO35__FUNC_DBG_MON_A28 (MTK_PIN_NO(35) | 7) +- +-#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +-#define PINMUX_GPIO36__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(36) | 1) +-#define PINMUX_GPIO36__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(36) | 2) +-#define PINMUX_GPIO36__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(36) | 3) +-#define PINMUX_GPIO36__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(36) | 4) +-#define PINMUX_GPIO36__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(36) | 5) +-#define PINMUX_GPIO36__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(36) | 6) +-#define PINMUX_GPIO36__FUNC_DBG_MON_A29 (MTK_PIN_NO(36) | 7) +- +-#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +-#define PINMUX_GPIO37__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(37) | 1) +-#define PINMUX_GPIO37__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(37) | 2) +-#define PINMUX_GPIO37__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(37) | 3) +-#define PINMUX_GPIO37__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(37) | 5) +-#define PINMUX_GPIO37__FUNC_CONN_DSP_JDO (MTK_PIN_NO(37) | 6) +-#define PINMUX_GPIO37__FUNC_DBG_MON_A30 (MTK_PIN_NO(37) | 7) +- +-#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +-#define PINMUX_GPIO38__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(38) | 1) +-#define PINMUX_GPIO38__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(38) | 3) +-#define PINMUX_GPIO38__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(38) | 4) +-#define PINMUX_GPIO38__FUNC_DBG_MON_A20 (MTK_PIN_NO(38) | 7) +- +-#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +-#define PINMUX_GPIO39__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(39) | 1) +-#define PINMUX_GPIO39__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(39) | 2) +-#define PINMUX_GPIO39__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(39) | 3) +-#define PINMUX_GPIO39__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(39) | 5) +-#define PINMUX_GPIO39__FUNC_CONN_DSP_JCK (MTK_PIN_NO(39) | 6) +-#define PINMUX_GPIO39__FUNC_DBG_MON_A31 (MTK_PIN_NO(39) | 7) +- +-#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +-#define PINMUX_GPIO40__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(40) | 1) +-#define PINMUX_GPIO40__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(40) | 2) +-#define PINMUX_GPIO40__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(40) | 3) +-#define PINMUX_GPIO40__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(40) | 5) +-#define PINMUX_GPIO40__FUNC_CONN_DSP_JDI (MTK_PIN_NO(40) | 6) +-#define PINMUX_GPIO40__FUNC_DBG_MON_A32 (MTK_PIN_NO(40) | 7) +- +-#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +-#define PINMUX_GPIO41__FUNC_IDDIG (MTK_PIN_NO(41) | 1) +-#define PINMUX_GPIO41__FUNC_URXD1 (MTK_PIN_NO(41) | 2) +-#define PINMUX_GPIO41__FUNC_UCTS0 (MTK_PIN_NO(41) | 3) +-#define PINMUX_GPIO41__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(41) | 4) +-#define PINMUX_GPIO41__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 5) +-#define PINMUX_GPIO41__FUNC_DMIC_CLK (MTK_PIN_NO(41) | 6) +- +-#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +-#define PINMUX_GPIO42__FUNC_USB_DRVVBUS (MTK_PIN_NO(42) | 1) +-#define PINMUX_GPIO42__FUNC_UTXD1 (MTK_PIN_NO(42) | 2) +-#define PINMUX_GPIO42__FUNC_URTS0 (MTK_PIN_NO(42) | 3) +-#define PINMUX_GPIO42__FUNC_SSPM_URXD_AO (MTK_PIN_NO(42) | 4) +-#define PINMUX_GPIO42__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(42) | 5) +-#define PINMUX_GPIO42__FUNC_DMIC_DAT (MTK_PIN_NO(42) | 6) +- +-#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +-#define PINMUX_GPIO43__FUNC_DISP_PWM (MTK_PIN_NO(43) | 1) +- +-#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +-#define PINMUX_GPIO44__FUNC_DSI_TE (MTK_PIN_NO(44) | 1) +- +-#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +-#define PINMUX_GPIO45__FUNC_LCM_RST (MTK_PIN_NO(45) | 1) +- +-#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +-#define PINMUX_GPIO46__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(46) | 1) +-#define PINMUX_GPIO46__FUNC_URXD1 (MTK_PIN_NO(46) | 2) +-#define PINMUX_GPIO46__FUNC_UCTS1 (MTK_PIN_NO(46) | 3) +-#define PINMUX_GPIO46__FUNC_CCU_UTXD_AO (MTK_PIN_NO(46) | 4) +-#define PINMUX_GPIO46__FUNC_TP_UCTS1_AO (MTK_PIN_NO(46) | 5) +-#define PINMUX_GPIO46__FUNC_IDDIG (MTK_PIN_NO(46) | 6) +-#define PINMUX_GPIO46__FUNC_I2S5_LRCK (MTK_PIN_NO(46) | 7) +- +-#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +-#define PINMUX_GPIO47__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(47) | 1) +-#define PINMUX_GPIO47__FUNC_UTXD1 (MTK_PIN_NO(47) | 2) +-#define PINMUX_GPIO47__FUNC_URTS1 (MTK_PIN_NO(47) | 3) +-#define PINMUX_GPIO47__FUNC_CCU_URXD_AO (MTK_PIN_NO(47) | 4) +-#define PINMUX_GPIO47__FUNC_TP_URTS1_AO (MTK_PIN_NO(47) | 5) +-#define PINMUX_GPIO47__FUNC_USB_DRVVBUS (MTK_PIN_NO(47) | 6) +-#define PINMUX_GPIO47__FUNC_I2S5_DO (MTK_PIN_NO(47) | 7) +- +-#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +-#define PINMUX_GPIO48__FUNC_SCL5 (MTK_PIN_NO(48) | 1) +- +-#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +-#define PINMUX_GPIO49__FUNC_SDA5 (MTK_PIN_NO(49) | 1) +- +-#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +-#define PINMUX_GPIO50__FUNC_SCL3 (MTK_PIN_NO(50) | 1) +- +-#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +-#define PINMUX_GPIO51__FUNC_SDA3 (MTK_PIN_NO(51) | 1) +- +-#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +-#define PINMUX_GPIO52__FUNC_BPI_ANT2 (MTK_PIN_NO(52) | 1) +- +-#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +-#define PINMUX_GPIO53__FUNC_BPI_ANT0 (MTK_PIN_NO(53) | 1) +- +-#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +-#define PINMUX_GPIO54__FUNC_BPI_OLAT1 (MTK_PIN_NO(54) | 1) +- +-#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +-#define PINMUX_GPIO55__FUNC_BPI_BUS8 (MTK_PIN_NO(55) | 1) +- +-#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +-#define PINMUX_GPIO56__FUNC_BPI_BUS9 (MTK_PIN_NO(56) | 1) +-#define PINMUX_GPIO56__FUNC_SCL_6306 (MTK_PIN_NO(56) | 2) +- +-#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +-#define PINMUX_GPIO57__FUNC_BPI_BUS10 (MTK_PIN_NO(57) | 1) +-#define PINMUX_GPIO57__FUNC_SDA_6306 (MTK_PIN_NO(57) | 2) +- +-#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +-#define PINMUX_GPIO58__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(58) | 1) +-#define PINMUX_GPIO58__FUNC_SPM_BSI_D2 (MTK_PIN_NO(58) | 2) +-#define PINMUX_GPIO58__FUNC_PWM_B (MTK_PIN_NO(58) | 3) +- +-#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +-#define PINMUX_GPIO59__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(59) | 1) +-#define PINMUX_GPIO59__FUNC_SPM_BSI_D1 (MTK_PIN_NO(59) | 2) +- +-#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +-#define PINMUX_GPIO60__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(60) | 1) +-#define PINMUX_GPIO60__FUNC_SPM_BSI_D0 (MTK_PIN_NO(60) | 2) +- +-#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +-#define PINMUX_GPIO61__FUNC_MIPI1_SDATA (MTK_PIN_NO(61) | 1) +- +-#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +-#define PINMUX_GPIO62__FUNC_MIPI1_SCLK (MTK_PIN_NO(62) | 1) +- +-#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +-#define PINMUX_GPIO63__FUNC_MIPI0_SDATA (MTK_PIN_NO(63) | 1) +- +-#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +-#define PINMUX_GPIO64__FUNC_MIPI0_SCLK (MTK_PIN_NO(64) | 1) +- +-#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +-#define PINMUX_GPIO65__FUNC_MIPI3_SDATA (MTK_PIN_NO(65) | 1) +-#define PINMUX_GPIO65__FUNC_BPI_OLAT2 (MTK_PIN_NO(65) | 2) +- +-#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +-#define PINMUX_GPIO66__FUNC_MIPI3_SCLK (MTK_PIN_NO(66) | 1) +-#define PINMUX_GPIO66__FUNC_BPI_OLAT3 (MTK_PIN_NO(66) | 2) +- +-#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +-#define PINMUX_GPIO67__FUNC_MIPI2_SDATA (MTK_PIN_NO(67) | 1) +- +-#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +-#define PINMUX_GPIO68__FUNC_MIPI2_SCLK (MTK_PIN_NO(68) | 1) +- +-#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +-#define PINMUX_GPIO69__FUNC_BPI_BUS7 (MTK_PIN_NO(69) | 1) +- +-#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +-#define PINMUX_GPIO70__FUNC_BPI_BUS6 (MTK_PIN_NO(70) | 1) +- +-#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +-#define PINMUX_GPIO71__FUNC_BPI_BUS5 (MTK_PIN_NO(71) | 1) +- +-#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +-#define PINMUX_GPIO72__FUNC_BPI_BUS4 (MTK_PIN_NO(72) | 1) +- +-#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +-#define PINMUX_GPIO73__FUNC_BPI_BUS3 (MTK_PIN_NO(73) | 1) +- +-#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +-#define PINMUX_GPIO74__FUNC_BPI_BUS2 (MTK_PIN_NO(74) | 1) +- +-#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +-#define PINMUX_GPIO75__FUNC_BPI_BUS1 (MTK_PIN_NO(75) | 1) +- +-#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +-#define PINMUX_GPIO76__FUNC_BPI_BUS0 (MTK_PIN_NO(76) | 1) +- +-#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +-#define PINMUX_GPIO77__FUNC_BPI_ANT1 (MTK_PIN_NO(77) | 1) +- +-#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +-#define PINMUX_GPIO78__FUNC_BPI_OLAT0 (MTK_PIN_NO(78) | 1) +- +-#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +-#define PINMUX_GPIO79__FUNC_BPI_PA_VM1 (MTK_PIN_NO(79) | 1) +-#define PINMUX_GPIO79__FUNC_MIPI4_SDATA (MTK_PIN_NO(79) | 2) +- +-#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +-#define PINMUX_GPIO80__FUNC_BPI_PA_VM0 (MTK_PIN_NO(80) | 1) +-#define PINMUX_GPIO80__FUNC_MIPI4_SCLK (MTK_PIN_NO(80) | 2) +- +-#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +-#define PINMUX_GPIO81__FUNC_SDA1 (MTK_PIN_NO(81) | 1) +- +-#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +-#define PINMUX_GPIO82__FUNC_SDA0 (MTK_PIN_NO(82) | 1) +- +-#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +-#define PINMUX_GPIO83__FUNC_SCL0 (MTK_PIN_NO(83) | 1) +- +-#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +-#define PINMUX_GPIO84__FUNC_SCL1 (MTK_PIN_NO(84) | 1) +- +-#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +-#define PINMUX_GPIO85__FUNC_SPI0_MI (MTK_PIN_NO(85) | 1) +-#define PINMUX_GPIO85__FUNC_SCP_SPI0_MI (MTK_PIN_NO(85) | 2) +-#define PINMUX_GPIO85__FUNC_CLKM3 (MTK_PIN_NO(85) | 3) +-#define PINMUX_GPIO85__FUNC_I2S1_BCK (MTK_PIN_NO(85) | 4) +-#define PINMUX_GPIO85__FUNC_MFG_DFD_JTAG_TDO (MTK_PIN_NO(85) | 5) +-#define PINMUX_GPIO85__FUNC_DFD_TDO (MTK_PIN_NO(85) | 6) +-#define PINMUX_GPIO85__FUNC_JTDO_SEL1 (MTK_PIN_NO(85) | 7) +- +-#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +-#define PINMUX_GPIO86__FUNC_SPI0_CSB (MTK_PIN_NO(86) | 1) +-#define PINMUX_GPIO86__FUNC_SCP_SPI0_CS (MTK_PIN_NO(86) | 2) +-#define PINMUX_GPIO86__FUNC_CLKM0 (MTK_PIN_NO(86) | 3) +-#define PINMUX_GPIO86__FUNC_I2S1_LRCK (MTK_PIN_NO(86) | 4) +-#define PINMUX_GPIO86__FUNC_MFG_DFD_JTAG_TMS (MTK_PIN_NO(86) | 5) +-#define PINMUX_GPIO86__FUNC_DFD_TMS (MTK_PIN_NO(86) | 6) +-#define PINMUX_GPIO86__FUNC_JTMS_SEL1 (MTK_PIN_NO(86) | 7) +- +-#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +-#define PINMUX_GPIO87__FUNC_SPI0_MO (MTK_PIN_NO(87) | 1) +-#define PINMUX_GPIO87__FUNC_SCP_SPI0_MO (MTK_PIN_NO(87) | 2) +-#define PINMUX_GPIO87__FUNC_SDA1 (MTK_PIN_NO(87) | 3) +-#define PINMUX_GPIO87__FUNC_I2S1_DO (MTK_PIN_NO(87) | 4) +-#define PINMUX_GPIO87__FUNC_MFG_DFD_JTAG_TDI (MTK_PIN_NO(87) | 5) +-#define PINMUX_GPIO87__FUNC_DFD_TDI (MTK_PIN_NO(87) | 6) +-#define PINMUX_GPIO87__FUNC_JTDI_SEL1 (MTK_PIN_NO(87) | 7) +- +-#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +-#define PINMUX_GPIO88__FUNC_SPI0_CLK (MTK_PIN_NO(88) | 1) +-#define PINMUX_GPIO88__FUNC_SCP_SPI0_CK (MTK_PIN_NO(88) | 2) +-#define PINMUX_GPIO88__FUNC_SCL1 (MTK_PIN_NO(88) | 3) +-#define PINMUX_GPIO88__FUNC_I2S1_MCK (MTK_PIN_NO(88) | 4) +-#define PINMUX_GPIO88__FUNC_MFG_DFD_JTAG_TCK (MTK_PIN_NO(88) | 5) +-#define PINMUX_GPIO88__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 6) +-#define PINMUX_GPIO88__FUNC_JTCK_SEL1 (MTK_PIN_NO(88) | 7) +- +-#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +-#define PINMUX_GPIO89__FUNC_SRCLKENAI0 (MTK_PIN_NO(89) | 1) +-#define PINMUX_GPIO89__FUNC_PWM_C (MTK_PIN_NO(89) | 2) +-#define PINMUX_GPIO89__FUNC_I2S5_BCK (MTK_PIN_NO(89) | 3) +-#define PINMUX_GPIO89__FUNC_ANT_SEL6 (MTK_PIN_NO(89) | 4) +-#define PINMUX_GPIO89__FUNC_SDA8 (MTK_PIN_NO(89) | 5) +-#define PINMUX_GPIO89__FUNC_CMVREF0 (MTK_PIN_NO(89) | 6) +-#define PINMUX_GPIO89__FUNC_DBG_MON_A21 (MTK_PIN_NO(89) | 7) +- +-#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +-#define PINMUX_GPIO90__FUNC_PWM_A (MTK_PIN_NO(90) | 1) +-#define PINMUX_GPIO90__FUNC_CMMCLK2 (MTK_PIN_NO(90) | 2) +-#define PINMUX_GPIO90__FUNC_I2S5_LRCK (MTK_PIN_NO(90) | 3) +-#define PINMUX_GPIO90__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(90) | 4) +-#define PINMUX_GPIO90__FUNC_SCL8 (MTK_PIN_NO(90) | 5) +-#define PINMUX_GPIO90__FUNC_PTA_RXD (MTK_PIN_NO(90) | 6) +-#define PINMUX_GPIO90__FUNC_DBG_MON_A22 (MTK_PIN_NO(90) | 7) +- +-#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +-#define PINMUX_GPIO91__FUNC_KPROW1 (MTK_PIN_NO(91) | 1) +-#define PINMUX_GPIO91__FUNC_PWM_B (MTK_PIN_NO(91) | 2) +-#define PINMUX_GPIO91__FUNC_I2S5_DO (MTK_PIN_NO(91) | 3) +-#define PINMUX_GPIO91__FUNC_ANT_SEL7 (MTK_PIN_NO(91) | 4) +-#define PINMUX_GPIO91__FUNC_CMMCLK3 (MTK_PIN_NO(91) | 5) +-#define PINMUX_GPIO91__FUNC_PTA_TXD (MTK_PIN_NO(91) | 6) +- +-#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +-#define PINMUX_GPIO92__FUNC_KPROW0 (MTK_PIN_NO(92) | 1) +- +-#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +-#define PINMUX_GPIO93__FUNC_KPCOL0 (MTK_PIN_NO(93) | 1) +-#define PINMUX_GPIO93__FUNC_DBG_MON_B27 (MTK_PIN_NO(93) | 7) +- +-#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +-#define PINMUX_GPIO94__FUNC_KPCOL1 (MTK_PIN_NO(94) | 1) +-#define PINMUX_GPIO94__FUNC_I2S2_DI2 (MTK_PIN_NO(94) | 2) +-#define PINMUX_GPIO94__FUNC_I2S5_MCK (MTK_PIN_NO(94) | 3) +-#define PINMUX_GPIO94__FUNC_CMMCLK2 (MTK_PIN_NO(94) | 4) +-#define PINMUX_GPIO94__FUNC_SCP_SPI2_MI (MTK_PIN_NO(94) | 5) +-#define PINMUX_GPIO94__FUNC_SRCLKENAI1 (MTK_PIN_NO(94) | 6) +-#define PINMUX_GPIO94__FUNC_SPI2_MI (MTK_PIN_NO(94) | 7) +- +-#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +-#define PINMUX_GPIO95__FUNC_URXD0 (MTK_PIN_NO(95) | 1) +-#define PINMUX_GPIO95__FUNC_UTXD0 (MTK_PIN_NO(95) | 2) +-#define PINMUX_GPIO95__FUNC_MD_URXD0 (MTK_PIN_NO(95) | 3) +-#define PINMUX_GPIO95__FUNC_MD_URXD1 (MTK_PIN_NO(95) | 4) +-#define PINMUX_GPIO95__FUNC_SSPM_URXD_AO (MTK_PIN_NO(95) | 5) +-#define PINMUX_GPIO95__FUNC_CCU_URXD_AO (MTK_PIN_NO(95) | 6) +- +-#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +-#define PINMUX_GPIO96__FUNC_UTXD0 (MTK_PIN_NO(96) | 1) +-#define PINMUX_GPIO96__FUNC_URXD0 (MTK_PIN_NO(96) | 2) +-#define PINMUX_GPIO96__FUNC_MD_UTXD0 (MTK_PIN_NO(96) | 3) +-#define PINMUX_GPIO96__FUNC_MD_UTXD1 (MTK_PIN_NO(96) | 4) +-#define PINMUX_GPIO96__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(96) | 5) +-#define PINMUX_GPIO96__FUNC_CCU_UTXD_AO (MTK_PIN_NO(96) | 6) +-#define PINMUX_GPIO96__FUNC_DBG_MON_B2 (MTK_PIN_NO(96) | 7) +- +-#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +-#define PINMUX_GPIO97__FUNC_UCTS0 (MTK_PIN_NO(97) | 1) +-#define PINMUX_GPIO97__FUNC_I2S2_MCK (MTK_PIN_NO(97) | 2) +-#define PINMUX_GPIO97__FUNC_IDDIG (MTK_PIN_NO(97) | 3) +-#define PINMUX_GPIO97__FUNC_CONN_MCU_TDO (MTK_PIN_NO(97) | 4) +-#define PINMUX_GPIO97__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(97) | 5) +-#define PINMUX_GPIO97__FUNC_IO_JTAG_TDO (MTK_PIN_NO(97) | 6) +-#define PINMUX_GPIO97__FUNC_DBG_MON_B3 (MTK_PIN_NO(97) | 7) +- +-#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +-#define PINMUX_GPIO98__FUNC_URTS0 (MTK_PIN_NO(98) | 1) +-#define PINMUX_GPIO98__FUNC_I2S2_BCK (MTK_PIN_NO(98) | 2) +-#define PINMUX_GPIO98__FUNC_USB_DRVVBUS (MTK_PIN_NO(98) | 3) +-#define PINMUX_GPIO98__FUNC_CONN_MCU_TMS (MTK_PIN_NO(98) | 4) +-#define PINMUX_GPIO98__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(98) | 5) +-#define PINMUX_GPIO98__FUNC_IO_JTAG_TMS (MTK_PIN_NO(98) | 6) +-#define PINMUX_GPIO98__FUNC_DBG_MON_B4 (MTK_PIN_NO(98) | 7) +- +-#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +-#define PINMUX_GPIO99__FUNC_CMMCLK0 (MTK_PIN_NO(99) | 1) +-#define PINMUX_GPIO99__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(99) | 4) +-#define PINMUX_GPIO99__FUNC_DBG_MON_B28 (MTK_PIN_NO(99) | 7) +- +-#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +-#define PINMUX_GPIO100__FUNC_CMMCLK1 (MTK_PIN_NO(100) | 1) +-#define PINMUX_GPIO100__FUNC_PWM_C (MTK_PIN_NO(100) | 2) +-#define PINMUX_GPIO100__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(100) | 3) +-#define PINMUX_GPIO100__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(100) | 4) +-#define PINMUX_GPIO100__FUNC_DBG_MON_B29 (MTK_PIN_NO(100) | 7) +- +-#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +-#define PINMUX_GPIO101__FUNC_CLKM2 (MTK_PIN_NO(101) | 1) +-#define PINMUX_GPIO101__FUNC_I2S2_LRCK (MTK_PIN_NO(101) | 2) +-#define PINMUX_GPIO101__FUNC_CMVREF1 (MTK_PIN_NO(101) | 3) +-#define PINMUX_GPIO101__FUNC_CONN_MCU_TCK (MTK_PIN_NO(101) | 4) +-#define PINMUX_GPIO101__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(101) | 5) +-#define PINMUX_GPIO101__FUNC_IO_JTAG_TCK (MTK_PIN_NO(101) | 6) +- +-#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +-#define PINMUX_GPIO102__FUNC_CLKM1 (MTK_PIN_NO(102) | 1) +-#define PINMUX_GPIO102__FUNC_I2S2_DI (MTK_PIN_NO(102) | 2) +-#define PINMUX_GPIO102__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(102) | 3) +-#define PINMUX_GPIO102__FUNC_CONN_MCU_TDI (MTK_PIN_NO(102) | 4) +-#define PINMUX_GPIO102__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(102) | 5) +-#define PINMUX_GPIO102__FUNC_IO_JTAG_TDI (MTK_PIN_NO(102) | 6) +-#define PINMUX_GPIO102__FUNC_DBG_MON_B8 (MTK_PIN_NO(102) | 7) +- +-#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +-#define PINMUX_GPIO103__FUNC_SCL2 (MTK_PIN_NO(103) | 1) +- +-#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +-#define PINMUX_GPIO104__FUNC_SDA2 (MTK_PIN_NO(104) | 1) +- +-#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +-#define PINMUX_GPIO105__FUNC_SCL4 (MTK_PIN_NO(105) | 1) +- +-#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +-#define PINMUX_GPIO106__FUNC_SDA4 (MTK_PIN_NO(106) | 1) +- +-#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +-#define PINMUX_GPIO107__FUNC_DMIC_CLK (MTK_PIN_NO(107) | 1) +-#define PINMUX_GPIO107__FUNC_ANT_SEL0 (MTK_PIN_NO(107) | 2) +-#define PINMUX_GPIO107__FUNC_CLKM0 (MTK_PIN_NO(107) | 3) +-#define PINMUX_GPIO107__FUNC_SDA7 (MTK_PIN_NO(107) | 4) +-#define PINMUX_GPIO107__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(107) | 5) +-#define PINMUX_GPIO107__FUNC_PWM_A (MTK_PIN_NO(107) | 6) +-#define PINMUX_GPIO107__FUNC_DBG_MON_B12 (MTK_PIN_NO(107) | 7) +- +-#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +-#define PINMUX_GPIO108__FUNC_CMMCLK2 (MTK_PIN_NO(108) | 1) +-#define PINMUX_GPIO108__FUNC_ANT_SEL1 (MTK_PIN_NO(108) | 2) +-#define PINMUX_GPIO108__FUNC_CLKM1 (MTK_PIN_NO(108) | 3) +-#define PINMUX_GPIO108__FUNC_SCL8 (MTK_PIN_NO(108) | 4) +-#define PINMUX_GPIO108__FUNC_DAP_MD32_SWD (MTK_PIN_NO(108) | 5) +-#define PINMUX_GPIO108__FUNC_PWM_B (MTK_PIN_NO(108) | 6) +-#define PINMUX_GPIO108__FUNC_DBG_MON_B13 (MTK_PIN_NO(108) | 7) +- +-#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +-#define PINMUX_GPIO109__FUNC_DMIC_DAT (MTK_PIN_NO(109) | 1) +-#define PINMUX_GPIO109__FUNC_ANT_SEL2 (MTK_PIN_NO(109) | 2) +-#define PINMUX_GPIO109__FUNC_CLKM2 (MTK_PIN_NO(109) | 3) +-#define PINMUX_GPIO109__FUNC_SDA8 (MTK_PIN_NO(109) | 4) +-#define PINMUX_GPIO109__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(109) | 5) +-#define PINMUX_GPIO109__FUNC_PWM_C (MTK_PIN_NO(109) | 6) +-#define PINMUX_GPIO109__FUNC_DBG_MON_B14 (MTK_PIN_NO(109) | 7) +- +-#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +-#define PINMUX_GPIO110__FUNC_SCL7 (MTK_PIN_NO(110) | 1) +-#define PINMUX_GPIO110__FUNC_ANT_SEL0 (MTK_PIN_NO(110) | 2) +-#define PINMUX_GPIO110__FUNC_TP_URXD1_AO (MTK_PIN_NO(110) | 3) +-#define PINMUX_GPIO110__FUNC_USB_DRVVBUS (MTK_PIN_NO(110) | 4) +-#define PINMUX_GPIO110__FUNC_SRCLKENAI1 (MTK_PIN_NO(110) | 5) +-#define PINMUX_GPIO110__FUNC_KPCOL2 (MTK_PIN_NO(110) | 6) +-#define PINMUX_GPIO110__FUNC_URXD1 (MTK_PIN_NO(110) | 7) +- +-#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +-#define PINMUX_GPIO111__FUNC_CMMCLK3 (MTK_PIN_NO(111) | 1) +-#define PINMUX_GPIO111__FUNC_ANT_SEL1 (MTK_PIN_NO(111) | 2) +-#define PINMUX_GPIO111__FUNC_SRCLKENAI0 (MTK_PIN_NO(111) | 3) +-#define PINMUX_GPIO111__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(111) | 4) +-#define PINMUX_GPIO111__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(111) | 5) +-#define PINMUX_GPIO111__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(111) | 7) +- +-#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +-#define PINMUX_GPIO112__FUNC_SDA7 (MTK_PIN_NO(112) | 1) +-#define PINMUX_GPIO112__FUNC_ANT_SEL2 (MTK_PIN_NO(112) | 2) +-#define PINMUX_GPIO112__FUNC_TP_UTXD1_AO (MTK_PIN_NO(112) | 3) +-#define PINMUX_GPIO112__FUNC_IDDIG (MTK_PIN_NO(112) | 4) +-#define PINMUX_GPIO112__FUNC_AGPS_SYNC (MTK_PIN_NO(112) | 5) +-#define PINMUX_GPIO112__FUNC_KPROW2 (MTK_PIN_NO(112) | 6) +-#define PINMUX_GPIO112__FUNC_UTXD1 (MTK_PIN_NO(112) | 7) +- +-#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +-#define PINMUX_GPIO113__FUNC_CONN_TOP_CLK (MTK_PIN_NO(113) | 1) +-#define PINMUX_GPIO113__FUNC_SCL6 (MTK_PIN_NO(113) | 3) +-#define PINMUX_GPIO113__FUNC_AUXIF_CLK0 (MTK_PIN_NO(113) | 4) +-#define PINMUX_GPIO113__FUNC_TP_UCTS1_AO (MTK_PIN_NO(113) | 6) +- +-#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +-#define PINMUX_GPIO114__FUNC_CONN_TOP_DATA (MTK_PIN_NO(114) | 1) +-#define PINMUX_GPIO114__FUNC_SDA6 (MTK_PIN_NO(114) | 3) +-#define PINMUX_GPIO114__FUNC_AUXIF_ST0 (MTK_PIN_NO(114) | 4) +-#define PINMUX_GPIO114__FUNC_TP_URTS1_AO (MTK_PIN_NO(114) | 6) +- +-#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +-#define PINMUX_GPIO115__FUNC_CONN_BT_CLK (MTK_PIN_NO(115) | 1) +-#define PINMUX_GPIO115__FUNC_UTXD1 (MTK_PIN_NO(115) | 2) +-#define PINMUX_GPIO115__FUNC_PTA_TXD (MTK_PIN_NO(115) | 3) +-#define PINMUX_GPIO115__FUNC_AUXIF_CLK1 (MTK_PIN_NO(115) | 4) +-#define PINMUX_GPIO115__FUNC_DAP_MD32_SWD (MTK_PIN_NO(115) | 5) +-#define PINMUX_GPIO115__FUNC_TP_UTXD1_AO (MTK_PIN_NO(115) | 6) +- +-#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +-#define PINMUX_GPIO116__FUNC_CONN_BT_DATA (MTK_PIN_NO(116) | 1) +-#define PINMUX_GPIO116__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(116) | 2) +-#define PINMUX_GPIO116__FUNC_AUXIF_ST1 (MTK_PIN_NO(116) | 4) +-#define PINMUX_GPIO116__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(116) | 5) +-#define PINMUX_GPIO116__FUNC_TP_URXD2_AO (MTK_PIN_NO(116) | 6) +-#define PINMUX_GPIO116__FUNC_DBG_MON_A0 (MTK_PIN_NO(116) | 7) +- +-#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +-#define PINMUX_GPIO117__FUNC_CONN_WF_HB0 (MTK_PIN_NO(117) | 1) +-#define PINMUX_GPIO117__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(117) | 2) +-#define PINMUX_GPIO117__FUNC_TP_UTXD2_AO (MTK_PIN_NO(117) | 6) +-#define PINMUX_GPIO117__FUNC_DBG_MON_A4 (MTK_PIN_NO(117) | 7) +- +-#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +-#define PINMUX_GPIO118__FUNC_CONN_WF_HB1 (MTK_PIN_NO(118) | 1) +-#define PINMUX_GPIO118__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(118) | 2) +-#define PINMUX_GPIO118__FUNC_SSPM_URXD_AO (MTK_PIN_NO(118) | 5) +-#define PINMUX_GPIO118__FUNC_TP_UCTS2_AO (MTK_PIN_NO(118) | 6) +-#define PINMUX_GPIO118__FUNC_DBG_MON_A5 (MTK_PIN_NO(118) | 7) +- +-#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +-#define PINMUX_GPIO119__FUNC_CONN_WF_HB2 (MTK_PIN_NO(119) | 1) +-#define PINMUX_GPIO119__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(119) | 2) +-#define PINMUX_GPIO119__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(119) | 5) +-#define PINMUX_GPIO119__FUNC_TP_URTS2_AO (MTK_PIN_NO(119) | 6) +- +-#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +-#define PINMUX_GPIO120__FUNC_CONN_WB_PTA (MTK_PIN_NO(120) | 1) +-#define PINMUX_GPIO120__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(120) | 2) +-#define PINMUX_GPIO120__FUNC_CCU_URXD_AO (MTK_PIN_NO(120) | 5) +- +-#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +-#define PINMUX_GPIO121__FUNC_CONN_HRST_B (MTK_PIN_NO(121) | 1) +-#define PINMUX_GPIO121__FUNC_URXD1 (MTK_PIN_NO(121) | 2) +-#define PINMUX_GPIO121__FUNC_PTA_RXD (MTK_PIN_NO(121) | 3) +-#define PINMUX_GPIO121__FUNC_CCU_UTXD_AO (MTK_PIN_NO(121) | 5) +-#define PINMUX_GPIO121__FUNC_TP_URXD1_AO (MTK_PIN_NO(121) | 6) +- +-#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +-#define PINMUX_GPIO122__FUNC_MSDC0_CMD (MTK_PIN_NO(122) | 1) +-#define PINMUX_GPIO122__FUNC_SSPM_URXD2_AO (MTK_PIN_NO(122) | 2) +-#define PINMUX_GPIO122__FUNC_ANT_SEL1 (MTK_PIN_NO(122) | 3) +-#define PINMUX_GPIO122__FUNC_DBG_MON_A12 (MTK_PIN_NO(122) | 7) +- +-#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +-#define PINMUX_GPIO123__FUNC_MSDC0_DAT0 (MTK_PIN_NO(123) | 1) +-#define PINMUX_GPIO123__FUNC_ANT_SEL0 (MTK_PIN_NO(123) | 3) +-#define PINMUX_GPIO123__FUNC_DBG_MON_A13 (MTK_PIN_NO(123) | 7) +- +-#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +-#define PINMUX_GPIO124__FUNC_MSDC0_CLK (MTK_PIN_NO(124) | 1) +-#define PINMUX_GPIO124__FUNC_DBG_MON_A14 (MTK_PIN_NO(124) | 7) +- +-#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +-#define PINMUX_GPIO125__FUNC_MSDC0_DAT2 (MTK_PIN_NO(125) | 1) +-#define PINMUX_GPIO125__FUNC_MRG_CLK (MTK_PIN_NO(125) | 3) +-#define PINMUX_GPIO125__FUNC_DBG_MON_A15 (MTK_PIN_NO(125) | 7) +- +-#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +-#define PINMUX_GPIO126__FUNC_MSDC0_DAT4 (MTK_PIN_NO(126) | 1) +-#define PINMUX_GPIO126__FUNC_ANT_SEL5 (MTK_PIN_NO(126) | 3) +-#define PINMUX_GPIO126__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(126) | 6) +-#define PINMUX_GPIO126__FUNC_DBG_MON_A16 (MTK_PIN_NO(126) | 7) +- +-#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +-#define PINMUX_GPIO127__FUNC_MSDC0_DAT6 (MTK_PIN_NO(127) | 1) +-#define PINMUX_GPIO127__FUNC_ANT_SEL4 (MTK_PIN_NO(127) | 3) +-#define PINMUX_GPIO127__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(127) | 6) +-#define PINMUX_GPIO127__FUNC_DBG_MON_A17 (MTK_PIN_NO(127) | 7) +- +-#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +-#define PINMUX_GPIO128__FUNC_MSDC0_DAT1 (MTK_PIN_NO(128) | 1) +-#define PINMUX_GPIO128__FUNC_ANT_SEL2 (MTK_PIN_NO(128) | 3) +-#define PINMUX_GPIO128__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(128) | 6) +-#define PINMUX_GPIO128__FUNC_DBG_MON_A18 (MTK_PIN_NO(128) | 7) +- +-#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +-#define PINMUX_GPIO129__FUNC_MSDC0_DAT5 (MTK_PIN_NO(129) | 1) +-#define PINMUX_GPIO129__FUNC_ANT_SEL3 (MTK_PIN_NO(129) | 3) +-#define PINMUX_GPIO129__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(129) | 6) +-#define PINMUX_GPIO129__FUNC_DBG_MON_A23 (MTK_PIN_NO(129) | 7) +- +-#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +-#define PINMUX_GPIO130__FUNC_MSDC0_DAT7 (MTK_PIN_NO(130) | 1) +-#define PINMUX_GPIO130__FUNC_MRG_DO (MTK_PIN_NO(130) | 3) +-#define PINMUX_GPIO130__FUNC_DBG_MON_A24 (MTK_PIN_NO(130) | 7) +- +-#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +-#define PINMUX_GPIO131__FUNC_MSDC0_DSL (MTK_PIN_NO(131) | 1) +-#define PINMUX_GPIO131__FUNC_MRG_SYNC (MTK_PIN_NO(131) | 3) +-#define PINMUX_GPIO131__FUNC_DBG_MON_A25 (MTK_PIN_NO(131) | 7) +- +-#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +-#define PINMUX_GPIO132__FUNC_MSDC0_DAT3 (MTK_PIN_NO(132) | 1) +-#define PINMUX_GPIO132__FUNC_MRG_DI (MTK_PIN_NO(132) | 3) +-#define PINMUX_GPIO132__FUNC_DBG_MON_A26 (MTK_PIN_NO(132) | 7) +- +-#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +-#define PINMUX_GPIO133__FUNC_MSDC0_RSTB (MTK_PIN_NO(133) | 1) +-#define PINMUX_GPIO133__FUNC_AGPS_SYNC (MTK_PIN_NO(133) | 3) +-#define PINMUX_GPIO133__FUNC_DBG_MON_A27 (MTK_PIN_NO(133) | 7) +- +-#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +-#define PINMUX_GPIO134__FUNC_RTC32K_CK (MTK_PIN_NO(134) | 1) +- +-#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +-#define PINMUX_GPIO135__FUNC_WATCHDOG (MTK_PIN_NO(135) | 1) +- +-#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +-#define PINMUX_GPIO136__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(136) | 1) +-#define PINMUX_GPIO136__FUNC_AUD_CLK_MISO (MTK_PIN_NO(136) | 2) +-#define PINMUX_GPIO136__FUNC_I2S1_MCK (MTK_PIN_NO(136) | 3) +-#define PINMUX_GPIO136__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(136) | 6) +- +-#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +-#define PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(137) | 1) +-#define PINMUX_GPIO137__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(137) | 2) +-#define PINMUX_GPIO137__FUNC_I2S1_BCK (MTK_PIN_NO(137) | 3) +- +-#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +-#define PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(138) | 1) +-#define PINMUX_GPIO138__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(138) | 2) +-#define PINMUX_GPIO138__FUNC_I2S1_LRCK (MTK_PIN_NO(138) | 3) +-#define PINMUX_GPIO138__FUNC_DBG_MON_B24 (MTK_PIN_NO(138) | 7) +- +-#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +-#define PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(139) | 1) +-#define PINMUX_GPIO139__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(139) | 2) +-#define PINMUX_GPIO139__FUNC_I2S1_DO (MTK_PIN_NO(139) | 3) +-#define PINMUX_GPIO139__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(139) | 6) +- +-#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +-#define PINMUX_GPIO140__FUNC_AUD_CLK_MISO (MTK_PIN_NO(140) | 1) +-#define PINMUX_GPIO140__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(140) | 2) +-#define PINMUX_GPIO140__FUNC_I2S0_MCK (MTK_PIN_NO(140) | 3) +-#define PINMUX_GPIO140__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(140) | 6) +- +-#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +-#define PINMUX_GPIO141__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(141) | 1) +-#define PINMUX_GPIO141__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(141) | 2) +-#define PINMUX_GPIO141__FUNC_I2S0_BCK (MTK_PIN_NO(141) | 3) +- +-#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +-#define PINMUX_GPIO142__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(142) | 1) +-#define PINMUX_GPIO142__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(142) | 2) +-#define PINMUX_GPIO142__FUNC_I2S0_LRCK (MTK_PIN_NO(142) | 3) +-#define PINMUX_GPIO142__FUNC_VOW_DAT_MISO (MTK_PIN_NO(142) | 4) +-#define PINMUX_GPIO142__FUNC_DBG_MON_B25 (MTK_PIN_NO(142) | 7) +- +-#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +-#define PINMUX_GPIO143__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(143) | 1) +-#define PINMUX_GPIO143__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(143) | 2) +-#define PINMUX_GPIO143__FUNC_I2S0_DI (MTK_PIN_NO(143) | 3) +-#define PINMUX_GPIO143__FUNC_VOW_CLK_MISO (MTK_PIN_NO(143) | 4) +-#define PINMUX_GPIO143__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(143) | 6) +-#define PINMUX_GPIO143__FUNC_DBG_MON_B26 (MTK_PIN_NO(143) | 7) +- +-#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +-#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(144) | 1) +-#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(144) | 2) +- +-#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +-#define PINMUX_GPIO145__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(145) | 1) +- +-#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +-#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(146) | 1) +-#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(146) | 2) +- +-#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +-#define PINMUX_GPIO147__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(147) | 1) +- +-#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +-#define PINMUX_GPIO148__FUNC_SRCLKENA0 (MTK_PIN_NO(148) | 1) +- +-#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +-#define PINMUX_GPIO149__FUNC_SRCLKENA1 (MTK_PIN_NO(149) | 1) +- +-#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +-#define PINMUX_GPIO150__FUNC_PWM_A (MTK_PIN_NO(150) | 1) +-#define PINMUX_GPIO150__FUNC_CMFLASH (MTK_PIN_NO(150) | 2) +-#define PINMUX_GPIO150__FUNC_CLKM0 (MTK_PIN_NO(150) | 3) +-#define PINMUX_GPIO150__FUNC_DBG_MON_B30 (MTK_PIN_NO(150) | 7) +- +-#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +-#define PINMUX_GPIO151__FUNC_PWM_B (MTK_PIN_NO(151) | 1) +-#define PINMUX_GPIO151__FUNC_CMVREF0 (MTK_PIN_NO(151) | 2) +-#define PINMUX_GPIO151__FUNC_CLKM1 (MTK_PIN_NO(151) | 3) +-#define PINMUX_GPIO151__FUNC_DBG_MON_B20 (MTK_PIN_NO(151) | 7) +- +-#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +-#define PINMUX_GPIO152__FUNC_PWM_C (MTK_PIN_NO(152) | 1) +-#define PINMUX_GPIO152__FUNC_CMFLASH (MTK_PIN_NO(152) | 2) +-#define PINMUX_GPIO152__FUNC_CLKM2 (MTK_PIN_NO(152) | 3) +-#define PINMUX_GPIO152__FUNC_DBG_MON_B21 (MTK_PIN_NO(152) | 7) +- +-#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +-#define PINMUX_GPIO153__FUNC_PWM_A (MTK_PIN_NO(153) | 1) +-#define PINMUX_GPIO153__FUNC_CMVREF0 (MTK_PIN_NO(153) | 2) +-#define PINMUX_GPIO153__FUNC_CLKM3 (MTK_PIN_NO(153) | 3) +-#define PINMUX_GPIO153__FUNC_DBG_MON_B22 (MTK_PIN_NO(153) | 7) +- +-#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +-#define PINMUX_GPIO154__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(154) | 1) +-#define PINMUX_GPIO154__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(154) | 2) +-#define PINMUX_GPIO154__FUNC_DBG_MON_B18 (MTK_PIN_NO(154) | 7) +- +-#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +-#define PINMUX_GPIO155__FUNC_ANT_SEL0 (MTK_PIN_NO(155) | 1) +-#define PINMUX_GPIO155__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(155) | 2) +-#define PINMUX_GPIO155__FUNC_CMVREF1 (MTK_PIN_NO(155) | 3) +-#define PINMUX_GPIO155__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(155) | 7) +- +-#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +-#define PINMUX_GPIO156__FUNC_ANT_SEL1 (MTK_PIN_NO(156) | 1) +-#define PINMUX_GPIO156__FUNC_SRCLKENAI0 (MTK_PIN_NO(156) | 2) +-#define PINMUX_GPIO156__FUNC_SCL6 (MTK_PIN_NO(156) | 3) +-#define PINMUX_GPIO156__FUNC_KPCOL2 (MTK_PIN_NO(156) | 4) +-#define PINMUX_GPIO156__FUNC_IDDIG (MTK_PIN_NO(156) | 5) +-#define PINMUX_GPIO156__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(156) | 7) +- +-#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +-#define PINMUX_GPIO157__FUNC_ANT_SEL2 (MTK_PIN_NO(157) | 1) +-#define PINMUX_GPIO157__FUNC_SRCLKENAI1 (MTK_PIN_NO(157) | 2) +-#define PINMUX_GPIO157__FUNC_SDA6 (MTK_PIN_NO(157) | 3) +-#define PINMUX_GPIO157__FUNC_KPROW2 (MTK_PIN_NO(157) | 4) +-#define PINMUX_GPIO157__FUNC_USB_DRVVBUS (MTK_PIN_NO(157) | 5) +-#define PINMUX_GPIO157__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(157) | 7) +- +-#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +-#define PINMUX_GPIO158__FUNC_ANT_SEL3 (MTK_PIN_NO(158) | 1) +- +-#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +-#define PINMUX_GPIO159__FUNC_ANT_SEL4 (MTK_PIN_NO(159) | 1) +- +-#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +-#define PINMUX_GPIO160__FUNC_ANT_SEL5 (MTK_PIN_NO(160) | 1) +- +-#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +-#define PINMUX_GPIO161__FUNC_SPI1_A_MI (MTK_PIN_NO(161) | 1) +-#define PINMUX_GPIO161__FUNC_SCP_SPI1_MI (MTK_PIN_NO(161) | 2) +-#define PINMUX_GPIO161__FUNC_IDDIG (MTK_PIN_NO(161) | 3) +-#define PINMUX_GPIO161__FUNC_ANT_SEL6 (MTK_PIN_NO(161) | 4) +-#define PINMUX_GPIO161__FUNC_KPCOL2 (MTK_PIN_NO(161) | 5) +-#define PINMUX_GPIO161__FUNC_PTA_RXD (MTK_PIN_NO(161) | 6) +-#define PINMUX_GPIO161__FUNC_DBG_MON_B19 (MTK_PIN_NO(161) | 7) +- +-#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +-#define PINMUX_GPIO162__FUNC_SPI1_A_CSB (MTK_PIN_NO(162) | 1) +-#define PINMUX_GPIO162__FUNC_SCP_SPI1_CS (MTK_PIN_NO(162) | 2) +-#define PINMUX_GPIO162__FUNC_USB_DRVVBUS (MTK_PIN_NO(162) | 3) +-#define PINMUX_GPIO162__FUNC_ANT_SEL5 (MTK_PIN_NO(162) | 4) +-#define PINMUX_GPIO162__FUNC_KPROW2 (MTK_PIN_NO(162) | 5) +-#define PINMUX_GPIO162__FUNC_PTA_TXD (MTK_PIN_NO(162) | 6) +- +-#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +-#define PINMUX_GPIO163__FUNC_SPI1_A_MO (MTK_PIN_NO(163) | 1) +-#define PINMUX_GPIO163__FUNC_SCP_SPI1_MO (MTK_PIN_NO(163) | 2) +-#define PINMUX_GPIO163__FUNC_SDA1 (MTK_PIN_NO(163) | 3) +-#define PINMUX_GPIO163__FUNC_ANT_SEL4 (MTK_PIN_NO(163) | 4) +-#define PINMUX_GPIO163__FUNC_CMMCLK2 (MTK_PIN_NO(163) | 5) +-#define PINMUX_GPIO163__FUNC_DMIC_CLK (MTK_PIN_NO(163) | 6) +- +-#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +-#define PINMUX_GPIO164__FUNC_SPI1_A_CLK (MTK_PIN_NO(164) | 1) +-#define PINMUX_GPIO164__FUNC_SCP_SPI1_CK (MTK_PIN_NO(164) | 2) +-#define PINMUX_GPIO164__FUNC_SCL1 (MTK_PIN_NO(164) | 3) +-#define PINMUX_GPIO164__FUNC_ANT_SEL3 (MTK_PIN_NO(164) | 4) +-#define PINMUX_GPIO164__FUNC_CMMCLK3 (MTK_PIN_NO(164) | 5) +-#define PINMUX_GPIO164__FUNC_DMIC_DAT (MTK_PIN_NO(164) | 6) +- +-#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +-#define PINMUX_GPIO165__FUNC_PWM_B (MTK_PIN_NO(165) | 1) +-#define PINMUX_GPIO165__FUNC_CMMCLK2 (MTK_PIN_NO(165) | 2) +-#define PINMUX_GPIO165__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(165) | 3) +-#define PINMUX_GPIO165__FUNC_TDM_MCK_2ND (MTK_PIN_NO(165) | 6) +-#define PINMUX_GPIO165__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(165) | 7) +- +-#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +-#define PINMUX_GPIO166__FUNC_ANT_SEL6 (MTK_PIN_NO(166) | 1) +- +-#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +-#define PINMUX_GPIO167__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(167) | 1) +-#define PINMUX_GPIO167__FUNC_SPM_BSI_EN (MTK_PIN_NO(167) | 2) +- +-#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +-#define PINMUX_GPIO168__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(168) | 1) +-#define PINMUX_GPIO168__FUNC_SPM_BSI_CK (MTK_PIN_NO(168) | 2) +- +-#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +-#define PINMUX_GPIO169__FUNC_PWM_C (MTK_PIN_NO(169) | 1) +-#define PINMUX_GPIO169__FUNC_CMMCLK3 (MTK_PIN_NO(169) | 2) +-#define PINMUX_GPIO169__FUNC_CMVREF1 (MTK_PIN_NO(169) | 3) +-#define PINMUX_GPIO169__FUNC_ANT_SEL7 (MTK_PIN_NO(169) | 4) +-#define PINMUX_GPIO169__FUNC_AGPS_SYNC (MTK_PIN_NO(169) | 5) +-#define PINMUX_GPIO169__FUNC_TDM_BCK_2ND (MTK_PIN_NO(169) | 6) +-#define PINMUX_GPIO169__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(169) | 7) +- +-#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +-#define PINMUX_GPIO170__FUNC_I2S1_BCK (MTK_PIN_NO(170) | 1) +-#define PINMUX_GPIO170__FUNC_I2S3_BCK (MTK_PIN_NO(170) | 2) +-#define PINMUX_GPIO170__FUNC_SCL7 (MTK_PIN_NO(170) | 3) +-#define PINMUX_GPIO170__FUNC_I2S5_BCK (MTK_PIN_NO(170) | 4) +-#define PINMUX_GPIO170__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(170) | 5) +-#define PINMUX_GPIO170__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(170) | 6) +-#define PINMUX_GPIO170__FUNC_ANT_SEL3 (MTK_PIN_NO(170) | 7) +- +-#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +-#define PINMUX_GPIO171__FUNC_I2S1_LRCK (MTK_PIN_NO(171) | 1) +-#define PINMUX_GPIO171__FUNC_I2S3_LRCK (MTK_PIN_NO(171) | 2) +-#define PINMUX_GPIO171__FUNC_SDA7 (MTK_PIN_NO(171) | 3) +-#define PINMUX_GPIO171__FUNC_I2S5_LRCK (MTK_PIN_NO(171) | 4) +-#define PINMUX_GPIO171__FUNC_URXD1 (MTK_PIN_NO(171) | 5) +-#define PINMUX_GPIO171__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(171) | 6) +-#define PINMUX_GPIO171__FUNC_ANT_SEL4 (MTK_PIN_NO(171) | 7) +- +-#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +-#define PINMUX_GPIO172__FUNC_I2S1_DO (MTK_PIN_NO(172) | 1) +-#define PINMUX_GPIO172__FUNC_I2S3_DO (MTK_PIN_NO(172) | 2) +-#define PINMUX_GPIO172__FUNC_SCL8 (MTK_PIN_NO(172) | 3) +-#define PINMUX_GPIO172__FUNC_I2S5_DO (MTK_PIN_NO(172) | 4) +-#define PINMUX_GPIO172__FUNC_UTXD1 (MTK_PIN_NO(172) | 5) +-#define PINMUX_GPIO172__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(172) | 6) +-#define PINMUX_GPIO172__FUNC_ANT_SEL5 (MTK_PIN_NO(172) | 7) +- +-#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +-#define PINMUX_GPIO173__FUNC_I2S1_MCK (MTK_PIN_NO(173) | 1) +-#define PINMUX_GPIO173__FUNC_I2S3_MCK (MTK_PIN_NO(173) | 2) +-#define PINMUX_GPIO173__FUNC_SDA8 (MTK_PIN_NO(173) | 3) +-#define PINMUX_GPIO173__FUNC_I2S5_MCK (MTK_PIN_NO(173) | 4) +-#define PINMUX_GPIO173__FUNC_UCTS0 (MTK_PIN_NO(173) | 5) +-#define PINMUX_GPIO173__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(173) | 6) +-#define PINMUX_GPIO173__FUNC_ANT_SEL6 (MTK_PIN_NO(173) | 7) +- +-#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +-#define PINMUX_GPIO174__FUNC_I2S2_DI (MTK_PIN_NO(174) | 1) +-#define PINMUX_GPIO174__FUNC_I2S0_DI (MTK_PIN_NO(174) | 2) +-#define PINMUX_GPIO174__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(174) | 3) +-#define PINMUX_GPIO174__FUNC_I2S2_DI2 (MTK_PIN_NO(174) | 4) +-#define PINMUX_GPIO174__FUNC_URTS0 (MTK_PIN_NO(174) | 5) +-#define PINMUX_GPIO174__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(174) | 6) +-#define PINMUX_GPIO174__FUNC_ANT_SEL7 (MTK_PIN_NO(174) | 7) +- +-#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +-#define PINMUX_GPIO175__FUNC_ANT_SEL7 (MTK_PIN_NO(175) | 1) +- +-#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +- +-#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +- +-#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +- +-#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +- +-#endif /* __MT8183-PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt8192-pinfunc.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt8192-pinfunc.h +deleted file mode 100644 +index 71ffe3a52578..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt8192-pinfunc.h ++++ /dev/null +@@ -1,1344 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2019 MediaTek Inc. +- * Author: Zhiyong Tao +- * +- */ +- +-#ifndef __MT8192_PINFUNC_H +-#define __MT8192_PINFUNC_H +- +-#include "mt65xx.h" +- +-#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +-#define PINMUX_GPIO0__FUNC_SPI6_CLK (MTK_PIN_NO(0) | 1) +-#define PINMUX_GPIO0__FUNC_I2S5_MCK (MTK_PIN_NO(0) | 2) +-#define PINMUX_GPIO0__FUNC_PWM_0 (MTK_PIN_NO(0) | 3) +-#define PINMUX_GPIO0__FUNC_TDM_LRCK (MTK_PIN_NO(0) | 4) +-#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 5) +-#define PINMUX_GPIO0__FUNC_MD_INT0 (MTK_PIN_NO(0) | 6) +- +-#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +-#define PINMUX_GPIO1__FUNC_SPI6_CSB (MTK_PIN_NO(1) | 1) +-#define PINMUX_GPIO1__FUNC_I2S5_BCK (MTK_PIN_NO(1) | 2) +-#define PINMUX_GPIO1__FUNC_PWM_1 (MTK_PIN_NO(1) | 3) +-#define PINMUX_GPIO1__FUNC_TDM_BCK (MTK_PIN_NO(1) | 4) +-#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 5) +-#define PINMUX_GPIO1__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(1) | 6) +-#define PINMUX_GPIO1__FUNC_DBG_MON_A9 (MTK_PIN_NO(1) | 7) +- +-#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +-#define PINMUX_GPIO2__FUNC_SPI6_MI (MTK_PIN_NO(2) | 1) +-#define PINMUX_GPIO2__FUNC_I2S5_LRCK (MTK_PIN_NO(2) | 2) +-#define PINMUX_GPIO2__FUNC_PWM_2 (MTK_PIN_NO(2) | 3) +-#define PINMUX_GPIO2__FUNC_TDM_MCK (MTK_PIN_NO(2) | 4) +-#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 5) +-#define PINMUX_GPIO2__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(2) | 6) +-#define PINMUX_GPIO2__FUNC_DBG_MON_A10 (MTK_PIN_NO(2) | 7) +- +-#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +-#define PINMUX_GPIO3__FUNC_SPI6_MO (MTK_PIN_NO(3) | 1) +-#define PINMUX_GPIO3__FUNC_I2S5_DO (MTK_PIN_NO(3) | 2) +-#define PINMUX_GPIO3__FUNC_PWM_3 (MTK_PIN_NO(3) | 3) +-#define PINMUX_GPIO3__FUNC_TDM_DATA0 (MTK_PIN_NO(3) | 4) +-#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 5) +-#define PINMUX_GPIO3__FUNC_CLKM0 (MTK_PIN_NO(3) | 6) +-#define PINMUX_GPIO3__FUNC_DBG_MON_A11 (MTK_PIN_NO(3) | 7) +- +-#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +-#define PINMUX_GPIO4__FUNC_SPI4_A_CLK (MTK_PIN_NO(4) | 1) +-#define PINMUX_GPIO4__FUNC_I2S2_MCK (MTK_PIN_NO(4) | 2) +-#define PINMUX_GPIO4__FUNC_DMIC1_CLK (MTK_PIN_NO(4) | 3) +-#define PINMUX_GPIO4__FUNC_TDM_DATA1 (MTK_PIN_NO(4) | 4) +-#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 5) +-#define PINMUX_GPIO4__FUNC_PCM1_DI (MTK_PIN_NO(4) | 6) +-#define PINMUX_GPIO4__FUNC_IDDIG (MTK_PIN_NO(4) | 7) +- +-#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +-#define PINMUX_GPIO5__FUNC_SPI4_A_CSB (MTK_PIN_NO(5) | 1) +-#define PINMUX_GPIO5__FUNC_I2S2_BCK (MTK_PIN_NO(5) | 2) +-#define PINMUX_GPIO5__FUNC_DMIC1_DAT (MTK_PIN_NO(5) | 3) +-#define PINMUX_GPIO5__FUNC_TDM_DATA2 (MTK_PIN_NO(5) | 4) +-#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 5) +-#define PINMUX_GPIO5__FUNC_PCM1_CLK (MTK_PIN_NO(5) | 6) +-#define PINMUX_GPIO5__FUNC_USB_DRVVBUS (MTK_PIN_NO(5) | 7) +- +-#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +-#define PINMUX_GPIO6__FUNC_SPI4_A_MI (MTK_PIN_NO(6) | 1) +-#define PINMUX_GPIO6__FUNC_I2S2_LRCK (MTK_PIN_NO(6) | 2) +-#define PINMUX_GPIO6__FUNC_DMIC_CLK (MTK_PIN_NO(6) | 3) +-#define PINMUX_GPIO6__FUNC_TDM_DATA3 (MTK_PIN_NO(6) | 4) +-#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 5) +-#define PINMUX_GPIO6__FUNC_PCM1_SYNC (MTK_PIN_NO(6) | 6) +- +-#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +-#define PINMUX_GPIO7__FUNC_SPI4_A_MO (MTK_PIN_NO(7) | 1) +-#define PINMUX_GPIO7__FUNC_I2S2_DI (MTK_PIN_NO(7) | 2) +-#define PINMUX_GPIO7__FUNC_DMIC_DAT (MTK_PIN_NO(7) | 3) +-#define PINMUX_GPIO7__FUNC_WIFI_TXD (MTK_PIN_NO(7) | 4) +-#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 5) +-#define PINMUX_GPIO7__FUNC_PCM1_DO0 (MTK_PIN_NO(7) | 6) +- +-#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +-#define PINMUX_GPIO8__FUNC_SRCLKENAI1 (MTK_PIN_NO(8) | 1) +-#define PINMUX_GPIO8__FUNC_I2S2_DI2 (MTK_PIN_NO(8) | 2) +-#define PINMUX_GPIO8__FUNC_KPCOL2 (MTK_PIN_NO(8) | 3) +-#define PINMUX_GPIO8__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(8) | 4) +-#define PINMUX_GPIO8__FUNC_CLKM1 (MTK_PIN_NO(8) | 5) +-#define PINMUX_GPIO8__FUNC_PCM1_DO1 (MTK_PIN_NO(8) | 6) +-#define PINMUX_GPIO8__FUNC_DBG_MON_A12 (MTK_PIN_NO(8) | 7) +- +-#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +-#define PINMUX_GPIO9__FUNC_SRCLKENAI0 (MTK_PIN_NO(9) | 1) +-#define PINMUX_GPIO9__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(9) | 2) +-#define PINMUX_GPIO9__FUNC_KPROW2 (MTK_PIN_NO(9) | 3) +-#define PINMUX_GPIO9__FUNC_CMMCLK4 (MTK_PIN_NO(9) | 4) +-#define PINMUX_GPIO9__FUNC_CLKM3 (MTK_PIN_NO(9) | 5) +-#define PINMUX_GPIO9__FUNC_PCM1_DO2 (MTK_PIN_NO(9) | 6) +-#define PINMUX_GPIO9__FUNC_DBG_MON_A13 (MTK_PIN_NO(9) | 7) +- +-#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +-#define PINMUX_GPIO10__FUNC_MSDC2_CLK (MTK_PIN_NO(10) | 1) +-#define PINMUX_GPIO10__FUNC_SPI4_B_CLK (MTK_PIN_NO(10) | 2) +-#define PINMUX_GPIO10__FUNC_I2S8_MCK (MTK_PIN_NO(10) | 3) +-#define PINMUX_GPIO10__FUNC_MD_INT0 (MTK_PIN_NO(10) | 5) +-#define PINMUX_GPIO10__FUNC_TP_GPIO8_AO (MTK_PIN_NO(10) | 6) +- +-#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +-#define PINMUX_GPIO11__FUNC_MSDC2_CMD (MTK_PIN_NO(11) | 1) +-#define PINMUX_GPIO11__FUNC_SPI4_B_CSB (MTK_PIN_NO(11) | 2) +-#define PINMUX_GPIO11__FUNC_I2S8_BCK (MTK_PIN_NO(11) | 3) +-#define PINMUX_GPIO11__FUNC_PCIE_CLKREQ_N (MTK_PIN_NO(11) | 4) +-#define PINMUX_GPIO11__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(11) | 5) +-#define PINMUX_GPIO11__FUNC_TP_GPIO9_AO (MTK_PIN_NO(11) | 6) +- +-#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +-#define PINMUX_GPIO12__FUNC_MSDC2_DAT3 (MTK_PIN_NO(12) | 1) +-#define PINMUX_GPIO12__FUNC_SPI4_B_MI (MTK_PIN_NO(12) | 2) +-#define PINMUX_GPIO12__FUNC_I2S8_LRCK (MTK_PIN_NO(12) | 3) +-#define PINMUX_GPIO12__FUNC_DMIC1_CLK (MTK_PIN_NO(12) | 4) +-#define PINMUX_GPIO12__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(12) | 5) +-#define PINMUX_GPIO12__FUNC_TP_GPIO10_AO (MTK_PIN_NO(12) | 6) +- +-#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +-#define PINMUX_GPIO13__FUNC_MSDC2_DAT0 (MTK_PIN_NO(13) | 1) +-#define PINMUX_GPIO13__FUNC_SPI4_B_MO (MTK_PIN_NO(13) | 2) +-#define PINMUX_GPIO13__FUNC_I2S8_DI (MTK_PIN_NO(13) | 3) +-#define PINMUX_GPIO13__FUNC_DMIC1_DAT (MTK_PIN_NO(13) | 4) +-#define PINMUX_GPIO13__FUNC_ANT_SEL10 (MTK_PIN_NO(13) | 5) +-#define PINMUX_GPIO13__FUNC_TP_GPIO11_AO (MTK_PIN_NO(13) | 6) +- +-#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +-#define PINMUX_GPIO14__FUNC_MSDC2_DAT2 (MTK_PIN_NO(14) | 1) +-#define PINMUX_GPIO14__FUNC_IDDIG (MTK_PIN_NO(14) | 2) +-#define PINMUX_GPIO14__FUNC_SCL_6306 (MTK_PIN_NO(14) | 3) +-#define PINMUX_GPIO14__FUNC_PCIE_PERESET_N (MTK_PIN_NO(14) | 4) +-#define PINMUX_GPIO14__FUNC_ANT_SEL11 (MTK_PIN_NO(14) | 5) +-#define PINMUX_GPIO14__FUNC_TP_GPIO12_AO (MTK_PIN_NO(14) | 6) +- +-#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +-#define PINMUX_GPIO15__FUNC_MSDC2_DAT1 (MTK_PIN_NO(15) | 1) +-#define PINMUX_GPIO15__FUNC_USB_DRVVBUS (MTK_PIN_NO(15) | 2) +-#define PINMUX_GPIO15__FUNC_SDA_6306 (MTK_PIN_NO(15) | 3) +-#define PINMUX_GPIO15__FUNC_PCIE_WAKE_N (MTK_PIN_NO(15) | 4) +-#define PINMUX_GPIO15__FUNC_ANT_SEL12 (MTK_PIN_NO(15) | 5) +-#define PINMUX_GPIO15__FUNC_TP_GPIO13_AO (MTK_PIN_NO(15) | 6) +- +-#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +-#define PINMUX_GPIO16__FUNC_SRCLKENAI1 (MTK_PIN_NO(16) | 1) +-#define PINMUX_GPIO16__FUNC_IDDIG (MTK_PIN_NO(16) | 2) +-#define PINMUX_GPIO16__FUNC_TP_GPIO14_AO (MTK_PIN_NO(16) | 3) +-#define PINMUX_GPIO16__FUNC_KPCOL2 (MTK_PIN_NO(16) | 4) +-#define PINMUX_GPIO16__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(16) | 5) +-#define PINMUX_GPIO16__FUNC_SPI7_A_MI (MTK_PIN_NO(16) | 6) +-#define PINMUX_GPIO16__FUNC_DBG_MON_A0 (MTK_PIN_NO(16) | 7) +- +-#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +-#define PINMUX_GPIO17__FUNC_SRCLKENAI0 (MTK_PIN_NO(17) | 1) +-#define PINMUX_GPIO17__FUNC_USB_DRVVBUS (MTK_PIN_NO(17) | 2) +-#define PINMUX_GPIO17__FUNC_TP_GPIO15_AO (MTK_PIN_NO(17) | 3) +-#define PINMUX_GPIO17__FUNC_KPROW2 (MTK_PIN_NO(17) | 4) +-#define PINMUX_GPIO17__FUNC_SPI7_A_MO (MTK_PIN_NO(17) | 6) +-#define PINMUX_GPIO17__FUNC_DBG_MON_A1 (MTK_PIN_NO(17) | 7) +- +-#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +-#define PINMUX_GPIO18__FUNC_SRCLKENAI0 (MTK_PIN_NO(18) | 1) +-#define PINMUX_GPIO18__FUNC_SPI4_C_MI (MTK_PIN_NO(18) | 2) +-#define PINMUX_GPIO18__FUNC_SPI1_B_MI (MTK_PIN_NO(18) | 3) +-#define PINMUX_GPIO18__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(18) | 4) +-#define PINMUX_GPIO18__FUNC_ANT_SEL10 (MTK_PIN_NO(18) | 5) +-#define PINMUX_GPIO18__FUNC_MD_INT0 (MTK_PIN_NO(18) | 6) +-#define PINMUX_GPIO18__FUNC_DBG_MON_B2 (MTK_PIN_NO(18) | 7) +- +-#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +-#define PINMUX_GPIO19__FUNC_SRCLKENAI1 (MTK_PIN_NO(19) | 1) +-#define PINMUX_GPIO19__FUNC_SPI4_C_MO (MTK_PIN_NO(19) | 2) +-#define PINMUX_GPIO19__FUNC_SPI1_B_MO (MTK_PIN_NO(19) | 3) +-#define PINMUX_GPIO19__FUNC_ANT_SEL11 (MTK_PIN_NO(19) | 5) +-#define PINMUX_GPIO19__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(19) | 6) +-#define PINMUX_GPIO19__FUNC_DBG_MON_B3 (MTK_PIN_NO(19) | 7) +- +-#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +-#define PINMUX_GPIO20__FUNC_SRCLKENAI0 (MTK_PIN_NO(20) | 1) +-#define PINMUX_GPIO20__FUNC_SPI4_C_CLK (MTK_PIN_NO(20) | 2) +-#define PINMUX_GPIO20__FUNC_SPI1_B_CLK (MTK_PIN_NO(20) | 3) +-#define PINMUX_GPIO20__FUNC_PWM_3 (MTK_PIN_NO(20) | 4) +-#define PINMUX_GPIO20__FUNC_ANT_SEL12 (MTK_PIN_NO(20) | 5) +-#define PINMUX_GPIO20__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(20) | 6) +-#define PINMUX_GPIO20__FUNC_DBG_MON_B4 (MTK_PIN_NO(20) | 7) +- +-#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +-#define PINMUX_GPIO21__FUNC_SPI4_C_CSB (MTK_PIN_NO(21) | 2) +-#define PINMUX_GPIO21__FUNC_SPI1_B_CSB (MTK_PIN_NO(21) | 3) +-#define PINMUX_GPIO21__FUNC_IDDIG (MTK_PIN_NO(21) | 6) +-#define PINMUX_GPIO21__FUNC_DBG_MON_B5 (MTK_PIN_NO(21) | 7) +- +-#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +-#define PINMUX_GPIO22__FUNC_SPI0_C_CLK (MTK_PIN_NO(22) | 2) +-#define PINMUX_GPIO22__FUNC_SPI7_B_CLK (MTK_PIN_NO(22) | 3) +-#define PINMUX_GPIO22__FUNC_I2S7_BCK (MTK_PIN_NO(22) | 4) +-#define PINMUX_GPIO22__FUNC_I2S9_BCK (MTK_PIN_NO(22) | 5) +-#define PINMUX_GPIO22__FUNC_SCL_6306 (MTK_PIN_NO(22) | 6) +- +-#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +-#define PINMUX_GPIO23__FUNC_SPI0_C_CSB (MTK_PIN_NO(23) | 2) +-#define PINMUX_GPIO23__FUNC_SPI7_B_CSB (MTK_PIN_NO(23) | 3) +-#define PINMUX_GPIO23__FUNC_I2S7_LRCK (MTK_PIN_NO(23) | 4) +-#define PINMUX_GPIO23__FUNC_I2S9_LRCK (MTK_PIN_NO(23) | 5) +-#define PINMUX_GPIO23__FUNC_SDA_6306 (MTK_PIN_NO(23) | 6) +- +-#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +-#define PINMUX_GPIO24__FUNC_SRCLKENAI1 (MTK_PIN_NO(24) | 1) +-#define PINMUX_GPIO24__FUNC_SPI0_C_MI (MTK_PIN_NO(24) | 2) +-#define PINMUX_GPIO24__FUNC_SPI7_B_MI (MTK_PIN_NO(24) | 3) +-#define PINMUX_GPIO24__FUNC_I2S6_DI (MTK_PIN_NO(24) | 4) +-#define PINMUX_GPIO24__FUNC_I2S8_DI (MTK_PIN_NO(24) | 5) +-#define PINMUX_GPIO24__FUNC_SPINOR_CS (MTK_PIN_NO(24) | 6) +- +-#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +-#define PINMUX_GPIO25__FUNC_SRCLKENAI0 (MTK_PIN_NO(25) | 1) +-#define PINMUX_GPIO25__FUNC_SPI0_C_MO (MTK_PIN_NO(25) | 2) +-#define PINMUX_GPIO25__FUNC_SPI7_B_MO (MTK_PIN_NO(25) | 3) +-#define PINMUX_GPIO25__FUNC_I2S7_DO (MTK_PIN_NO(25) | 4) +-#define PINMUX_GPIO25__FUNC_I2S9_DO (MTK_PIN_NO(25) | 5) +-#define PINMUX_GPIO25__FUNC_SPINOR_CK (MTK_PIN_NO(25) | 6) +- +-#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +-#define PINMUX_GPIO26__FUNC_PWM_2 (MTK_PIN_NO(26) | 1) +-#define PINMUX_GPIO26__FUNC_CLKM0 (MTK_PIN_NO(26) | 2) +-#define PINMUX_GPIO26__FUNC_USB_DRVVBUS (MTK_PIN_NO(26) | 3) +-#define PINMUX_GPIO26__FUNC_SPI5_C_MI (MTK_PIN_NO(26) | 4) +-#define PINMUX_GPIO26__FUNC_I2S9_BCK (MTK_PIN_NO(26) | 5) +- +-#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +-#define PINMUX_GPIO27__FUNC_PWM_3 (MTK_PIN_NO(27) | 1) +-#define PINMUX_GPIO27__FUNC_CLKM1 (MTK_PIN_NO(27) | 2) +-#define PINMUX_GPIO27__FUNC_SPI5_C_MO (MTK_PIN_NO(27) | 4) +-#define PINMUX_GPIO27__FUNC_I2S9_LRCK (MTK_PIN_NO(27) | 5) +-#define PINMUX_GPIO27__FUNC_SPINOR_IO0 (MTK_PIN_NO(27) | 6) +- +-#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +-#define PINMUX_GPIO28__FUNC_PWM_0 (MTK_PIN_NO(28) | 1) +-#define PINMUX_GPIO28__FUNC_CLKM2 (MTK_PIN_NO(28) | 2) +-#define PINMUX_GPIO28__FUNC_SPI5_C_CSB (MTK_PIN_NO(28) | 4) +-#define PINMUX_GPIO28__FUNC_I2S9_MCK (MTK_PIN_NO(28) | 5) +-#define PINMUX_GPIO28__FUNC_SPINOR_IO1 (MTK_PIN_NO(28) | 6) +- +-#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +-#define PINMUX_GPIO29__FUNC_PWM_1 (MTK_PIN_NO(29) | 1) +-#define PINMUX_GPIO29__FUNC_CLKM3 (MTK_PIN_NO(29) | 2) +-#define PINMUX_GPIO29__FUNC_SPI5_C_CLK (MTK_PIN_NO(29) | 4) +-#define PINMUX_GPIO29__FUNC_I2S9_DO (MTK_PIN_NO(29) | 5) +-#define PINMUX_GPIO29__FUNC_SPINOR_IO2 (MTK_PIN_NO(29) | 6) +- +-#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +-#define PINMUX_GPIO30__FUNC_PWM_2 (MTK_PIN_NO(30) | 1) +-#define PINMUX_GPIO30__FUNC_CLKM0 (MTK_PIN_NO(30) | 2) +-#define PINMUX_GPIO30__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(30) | 3) +-#define PINMUX_GPIO30__FUNC_I2S7_MCK (MTK_PIN_NO(30) | 4) +-#define PINMUX_GPIO30__FUNC_I2S9_MCK (MTK_PIN_NO(30) | 5) +-#define PINMUX_GPIO30__FUNC_SPINOR_IO3 (MTK_PIN_NO(30) | 6) +- +-#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +-#define PINMUX_GPIO31__FUNC_I2S3_MCK (MTK_PIN_NO(31) | 1) +-#define PINMUX_GPIO31__FUNC_I2S1_MCK (MTK_PIN_NO(31) | 2) +-#define PINMUX_GPIO31__FUNC_I2S5_MCK (MTK_PIN_NO(31) | 3) +-#define PINMUX_GPIO31__FUNC_SRCLKENAI0 (MTK_PIN_NO(31) | 4) +-#define PINMUX_GPIO31__FUNC_I2S0_MCK (MTK_PIN_NO(31) | 5) +- +-#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +-#define PINMUX_GPIO32__FUNC_I2S3_BCK (MTK_PIN_NO(32) | 1) +-#define PINMUX_GPIO32__FUNC_I2S1_BCK (MTK_PIN_NO(32) | 2) +-#define PINMUX_GPIO32__FUNC_I2S5_BCK (MTK_PIN_NO(32) | 3) +-#define PINMUX_GPIO32__FUNC_PCM0_CLK (MTK_PIN_NO(32) | 4) +-#define PINMUX_GPIO32__FUNC_I2S0_BCK (MTK_PIN_NO(32) | 5) +- +-#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +-#define PINMUX_GPIO33__FUNC_I2S3_LRCK (MTK_PIN_NO(33) | 1) +-#define PINMUX_GPIO33__FUNC_I2S1_LRCK (MTK_PIN_NO(33) | 2) +-#define PINMUX_GPIO33__FUNC_I2S5_LRCK (MTK_PIN_NO(33) | 3) +-#define PINMUX_GPIO33__FUNC_PCM0_SYNC (MTK_PIN_NO(33) | 4) +-#define PINMUX_GPIO33__FUNC_I2S0_LRCK (MTK_PIN_NO(33) | 5) +- +-#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +-#define PINMUX_GPIO34__FUNC_I2S0_DI (MTK_PIN_NO(34) | 1) +-#define PINMUX_GPIO34__FUNC_I2S2_DI (MTK_PIN_NO(34) | 2) +-#define PINMUX_GPIO34__FUNC_I2S2_DI2 (MTK_PIN_NO(34) | 3) +-#define PINMUX_GPIO34__FUNC_PCM0_DI (MTK_PIN_NO(34) | 4) +-#define PINMUX_GPIO34__FUNC_I2S0_DI_A (MTK_PIN_NO(34) | 5) +- +-#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +-#define PINMUX_GPIO35__FUNC_I2S3_DO (MTK_PIN_NO(35) | 1) +-#define PINMUX_GPIO35__FUNC_I2S1_DO (MTK_PIN_NO(35) | 2) +-#define PINMUX_GPIO35__FUNC_I2S5_DO (MTK_PIN_NO(35) | 3) +-#define PINMUX_GPIO35__FUNC_PCM0_DO (MTK_PIN_NO(35) | 4) +- +-#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +-#define PINMUX_GPIO36__FUNC_SPI5_A_CLK (MTK_PIN_NO(36) | 1) +-#define PINMUX_GPIO36__FUNC_DMIC1_CLK (MTK_PIN_NO(36) | 2) +-#define PINMUX_GPIO36__FUNC_MD_URXD0 (MTK_PIN_NO(36) | 4) +-#define PINMUX_GPIO36__FUNC_UCTS0 (MTK_PIN_NO(36) | 5) +-#define PINMUX_GPIO36__FUNC_URXD1 (MTK_PIN_NO(36) | 6) +- +-#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +-#define PINMUX_GPIO37__FUNC_SPI5_A_CSB (MTK_PIN_NO(37) | 1) +-#define PINMUX_GPIO37__FUNC_DMIC1_DAT (MTK_PIN_NO(37) | 2) +-#define PINMUX_GPIO37__FUNC_MD_UTXD0 (MTK_PIN_NO(37) | 4) +-#define PINMUX_GPIO37__FUNC_URTS0 (MTK_PIN_NO(37) | 5) +-#define PINMUX_GPIO37__FUNC_UTXD1 (MTK_PIN_NO(37) | 6) +- +-#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +-#define PINMUX_GPIO38__FUNC_SPI5_A_MI (MTK_PIN_NO(38) | 1) +-#define PINMUX_GPIO38__FUNC_DMIC_CLK (MTK_PIN_NO(38) | 2) +-#define PINMUX_GPIO38__FUNC_MD_URXD1 (MTK_PIN_NO(38) | 4) +-#define PINMUX_GPIO38__FUNC_URXD0 (MTK_PIN_NO(38) | 5) +-#define PINMUX_GPIO38__FUNC_UCTS1 (MTK_PIN_NO(38) | 6) +- +-#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +-#define PINMUX_GPIO39__FUNC_SPI5_A_MO (MTK_PIN_NO(39) | 1) +-#define PINMUX_GPIO39__FUNC_DMIC_DAT (MTK_PIN_NO(39) | 2) +-#define PINMUX_GPIO39__FUNC_MD_UTXD1 (MTK_PIN_NO(39) | 4) +-#define PINMUX_GPIO39__FUNC_UTXD0 (MTK_PIN_NO(39) | 5) +-#define PINMUX_GPIO39__FUNC_URTS1 (MTK_PIN_NO(39) | 6) +- +-#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +-#define PINMUX_GPIO40__FUNC_DISP_PWM (MTK_PIN_NO(40) | 1) +-#define PINMUX_GPIO40__FUNC_DBG_MON_A6 (MTK_PIN_NO(40) | 7) +- +-#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +-#define PINMUX_GPIO41__FUNC_DSI_TE (MTK_PIN_NO(41) | 1) +-#define PINMUX_GPIO41__FUNC_DBG_MON_A7 (MTK_PIN_NO(41) | 7) +- +-#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +-#define PINMUX_GPIO42__FUNC_LCM_RST (MTK_PIN_NO(42) | 1) +-#define PINMUX_GPIO42__FUNC_DBG_MON_A8 (MTK_PIN_NO(42) | 7) +- +-#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +-#define PINMUX_GPIO43__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(43) | 1) +-#define PINMUX_GPIO43__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(43) | 2) +-#define PINMUX_GPIO43__FUNC_SCL_6306 (MTK_PIN_NO(43) | 3) +-#define PINMUX_GPIO43__FUNC_ADSP_URXD0 (MTK_PIN_NO(43) | 4) +-#define PINMUX_GPIO43__FUNC_PTA_RXD (MTK_PIN_NO(43) | 5) +-#define PINMUX_GPIO43__FUNC_SSPM_URXD_AO (MTK_PIN_NO(43) | 6) +-#define PINMUX_GPIO43__FUNC_DBG_MON_B0 (MTK_PIN_NO(43) | 7) +- +-#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +-#define PINMUX_GPIO44__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(44) | 1) +-#define PINMUX_GPIO44__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(44) | 2) +-#define PINMUX_GPIO44__FUNC_SDA_6306 (MTK_PIN_NO(44) | 3) +-#define PINMUX_GPIO44__FUNC_ADSP_UTXD0 (MTK_PIN_NO(44) | 4) +-#define PINMUX_GPIO44__FUNC_PTA_TXD (MTK_PIN_NO(44) | 5) +-#define PINMUX_GPIO44__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(44) | 6) +-#define PINMUX_GPIO44__FUNC_DBG_MON_B1 (MTK_PIN_NO(44) | 7) +- +-#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +-#define PINMUX_GPIO45__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(45) | 1) +-#define PINMUX_GPIO45__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(45) | 2) +-#define PINMUX_GPIO45__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(45) | 3) +-#define PINMUX_GPIO45__FUNC_APU_JTAG_TDI (MTK_PIN_NO(45) | 4) +-#define PINMUX_GPIO45__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(45) | 5) +-#define PINMUX_GPIO45__FUNC_LVTS_SCK (MTK_PIN_NO(45) | 6) +-#define PINMUX_GPIO45__FUNC_CONN_DSP_JDI (MTK_PIN_NO(45) | 7) +- +-#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +-#define PINMUX_GPIO46__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(46) | 1) +-#define PINMUX_GPIO46__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(46) | 2) +-#define PINMUX_GPIO46__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(46) | 3) +-#define PINMUX_GPIO46__FUNC_APU_JTAG_TMS (MTK_PIN_NO(46) | 4) +-#define PINMUX_GPIO46__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(46) | 5) +-#define PINMUX_GPIO46__FUNC_LVTS_SDI (MTK_PIN_NO(46) | 6) +-#define PINMUX_GPIO46__FUNC_CONN_DSP_JMS (MTK_PIN_NO(46) | 7) +- +-#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +-#define PINMUX_GPIO47__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(47) | 1) +-#define PINMUX_GPIO47__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(47) | 2) +-#define PINMUX_GPIO47__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(47) | 3) +-#define PINMUX_GPIO47__FUNC_APU_JTAG_TDO (MTK_PIN_NO(47) | 4) +-#define PINMUX_GPIO47__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(47) | 5) +-#define PINMUX_GPIO47__FUNC_LVTS_SCF (MTK_PIN_NO(47) | 6) +-#define PINMUX_GPIO47__FUNC_CONN_DSP_JDO (MTK_PIN_NO(47) | 7) +- +-#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +-#define PINMUX_GPIO48__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(48) | 1) +-#define PINMUX_GPIO48__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(48) | 2) +-#define PINMUX_GPIO48__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(48) | 3) +-#define PINMUX_GPIO48__FUNC_APU_JTAG_TRST (MTK_PIN_NO(48) | 4) +-#define PINMUX_GPIO48__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(48) | 5) +-#define PINMUX_GPIO48__FUNC_LVTS_FOUT (MTK_PIN_NO(48) | 6) +-#define PINMUX_GPIO48__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(48) | 7) +- +-#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +-#define PINMUX_GPIO49__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(49) | 1) +-#define PINMUX_GPIO49__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(49) | 2) +-#define PINMUX_GPIO49__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(49) | 3) +-#define PINMUX_GPIO49__FUNC_APU_JTAG_TCK (MTK_PIN_NO(49) | 4) +-#define PINMUX_GPIO49__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(49) | 5) +-#define PINMUX_GPIO49__FUNC_LVTS_SDO (MTK_PIN_NO(49) | 6) +-#define PINMUX_GPIO49__FUNC_CONN_DSP_JCK (MTK_PIN_NO(49) | 7) +- +-#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +-#define PINMUX_GPIO50__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(50) | 1) +-#define PINMUX_GPIO50__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(50) | 2) +-#define PINMUX_GPIO50__FUNC_LVTS_26M (MTK_PIN_NO(50) | 6) +- +-#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +-#define PINMUX_GPIO51__FUNC_MSDC1_CLK (MTK_PIN_NO(51) | 1) +-#define PINMUX_GPIO51__FUNC_PCM1_CLK (MTK_PIN_NO(51) | 2) +-#define PINMUX_GPIO51__FUNC_CONN_DSP_JCK (MTK_PIN_NO(51) | 3) +-#define PINMUX_GPIO51__FUNC_UDI_TCK (MTK_PIN_NO(51) | 4) +-#define PINMUX_GPIO51__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(51) | 5) +-#define PINMUX_GPIO51__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(51) | 6) +-#define PINMUX_GPIO51__FUNC_JTCK_SEL3 (MTK_PIN_NO(51) | 7) +- +-#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +-#define PINMUX_GPIO52__FUNC_MSDC1_CMD (MTK_PIN_NO(52) | 1) +-#define PINMUX_GPIO52__FUNC_PCM1_SYNC (MTK_PIN_NO(52) | 2) +-#define PINMUX_GPIO52__FUNC_CONN_DSP_JMS (MTK_PIN_NO(52) | 3) +-#define PINMUX_GPIO52__FUNC_UDI_TMS (MTK_PIN_NO(52) | 4) +-#define PINMUX_GPIO52__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(52) | 5) +-#define PINMUX_GPIO52__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(52) | 6) +-#define PINMUX_GPIO52__FUNC_JTMS_SEL3 (MTK_PIN_NO(52) | 7) +- +-#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +-#define PINMUX_GPIO53__FUNC_MSDC1_DAT3 (MTK_PIN_NO(53) | 1) +-#define PINMUX_GPIO53__FUNC_PCM1_DI (MTK_PIN_NO(53) | 2) +-#define PINMUX_GPIO53__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(53) | 3) +-#define PINMUX_GPIO53__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(53) | 4) +- +-#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +-#define PINMUX_GPIO54__FUNC_MSDC1_DAT0 (MTK_PIN_NO(54) | 1) +-#define PINMUX_GPIO54__FUNC_PCM1_DO0 (MTK_PIN_NO(54) | 2) +-#define PINMUX_GPIO54__FUNC_CONN_DSP_JDI (MTK_PIN_NO(54) | 3) +-#define PINMUX_GPIO54__FUNC_UDI_TDI (MTK_PIN_NO(54) | 4) +-#define PINMUX_GPIO54__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(54) | 5) +-#define PINMUX_GPIO54__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(54) | 6) +-#define PINMUX_GPIO54__FUNC_JTDI_SEL3 (MTK_PIN_NO(54) | 7) +- +-#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +-#define PINMUX_GPIO55__FUNC_MSDC1_DAT2 (MTK_PIN_NO(55) | 1) +-#define PINMUX_GPIO55__FUNC_PCM1_DO2 (MTK_PIN_NO(55) | 2) +-#define PINMUX_GPIO55__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(55) | 3) +-#define PINMUX_GPIO55__FUNC_UDI_NTRST (MTK_PIN_NO(55) | 4) +-#define PINMUX_GPIO55__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(55) | 5) +-#define PINMUX_GPIO55__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(55) | 6) +-#define PINMUX_GPIO55__FUNC_JTRSTN_SEL3 (MTK_PIN_NO(55) | 7) +- +-#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +-#define PINMUX_GPIO56__FUNC_MSDC1_DAT1 (MTK_PIN_NO(56) | 1) +-#define PINMUX_GPIO56__FUNC_PCM1_DO1 (MTK_PIN_NO(56) | 2) +-#define PINMUX_GPIO56__FUNC_CONN_DSP_JDO (MTK_PIN_NO(56) | 3) +-#define PINMUX_GPIO56__FUNC_UDI_TDO (MTK_PIN_NO(56) | 4) +-#define PINMUX_GPIO56__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(56) | 5) +-#define PINMUX_GPIO56__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(56) | 6) +-#define PINMUX_GPIO56__FUNC_JTDO_SEL3 (MTK_PIN_NO(56) | 7) +- +-#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +-#define PINMUX_GPIO57__FUNC_MIPI2_D_SCLK (MTK_PIN_NO(57) | 1) +- +-#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +-#define PINMUX_GPIO58__FUNC_MIPI2_D_SDATA (MTK_PIN_NO(58) | 1) +- +-#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +-#define PINMUX_GPIO59__FUNC_MIPI_M_SCLK (MTK_PIN_NO(59) | 1) +- +-#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +-#define PINMUX_GPIO60__FUNC_MIPI_M_SDATA (MTK_PIN_NO(60) | 1) +- +-#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +-#define PINMUX_GPIO61__FUNC_MD_UCNT_A_TGL (MTK_PIN_NO(61) | 1) +- +-#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +-#define PINMUX_GPIO62__FUNC_DIGRF_IRQ (MTK_PIN_NO(62) | 1) +- +-#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +-#define PINMUX_GPIO63__FUNC_BPI_BUS0 (MTK_PIN_NO(63) | 1) +-#define PINMUX_GPIO63__FUNC_PCIE_WAKE_N (MTK_PIN_NO(63) | 3) +- +-#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +-#define PINMUX_GPIO64__FUNC_BPI_BUS1 (MTK_PIN_NO(64) | 1) +-#define PINMUX_GPIO64__FUNC_PCIE_PERESET_N (MTK_PIN_NO(64) | 3) +- +-#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +-#define PINMUX_GPIO65__FUNC_BPI_BUS2 (MTK_PIN_NO(65) | 1) +-#define PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N (MTK_PIN_NO(65) | 3) +- +-#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +-#define PINMUX_GPIO66__FUNC_BPI_BUS3 (MTK_PIN_NO(66) | 1) +- +-#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +-#define PINMUX_GPIO67__FUNC_BPI_BUS4 (MTK_PIN_NO(67) | 1) +- +-#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +-#define PINMUX_GPIO68__FUNC_BPI_BUS5 (MTK_PIN_NO(68) | 1) +- +-#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +-#define PINMUX_GPIO69__FUNC_BPI_BUS6 (MTK_PIN_NO(69) | 1) +-#define PINMUX_GPIO69__FUNC_CONN_BPI_BUS6 (MTK_PIN_NO(69) | 2) +- +-#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +-#define PINMUX_GPIO70__FUNC_BPI_BUS7 (MTK_PIN_NO(70) | 1) +-#define PINMUX_GPIO70__FUNC_CONN_BPI_BUS7 (MTK_PIN_NO(70) | 2) +- +-#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +-#define PINMUX_GPIO71__FUNC_BPI_BUS8 (MTK_PIN_NO(71) | 1) +-#define PINMUX_GPIO71__FUNC_CONN_BPI_BUS8 (MTK_PIN_NO(71) | 2) +- +-#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +-#define PINMUX_GPIO72__FUNC_BPI_BUS9 (MTK_PIN_NO(72) | 1) +-#define PINMUX_GPIO72__FUNC_CONN_BPI_BUS9 (MTK_PIN_NO(72) | 2) +- +-#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +-#define PINMUX_GPIO73__FUNC_BPI_BUS10 (MTK_PIN_NO(73) | 1) +-#define PINMUX_GPIO73__FUNC_CONN_BPI_BUS10 (MTK_PIN_NO(73) | 2) +- +-#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +-#define PINMUX_GPIO74__FUNC_BPI_BUS11_OLAT0 (MTK_PIN_NO(74) | 1) +-#define PINMUX_GPIO74__FUNC_CONN_BPI_BUS11_OLAT0 (MTK_PIN_NO(74) | 2) +- +-#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +-#define PINMUX_GPIO75__FUNC_BPI_BUS12_OLAT1 (MTK_PIN_NO(75) | 1) +-#define PINMUX_GPIO75__FUNC_CONN_BPI_BUS12_OLAT1 (MTK_PIN_NO(75) | 2) +- +-#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +-#define PINMUX_GPIO76__FUNC_BPI_BUS13_OLAT2 (MTK_PIN_NO(76) | 1) +-#define PINMUX_GPIO76__FUNC_CONN_BPI_BUS13_OLAT2 (MTK_PIN_NO(76) | 2) +- +-#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +-#define PINMUX_GPIO77__FUNC_BPI_BUS14_OLAT3 (MTK_PIN_NO(77) | 1) +-#define PINMUX_GPIO77__FUNC_CONN_BPI_BUS14_OLAT3 (MTK_PIN_NO(77) | 2) +- +-#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +-#define PINMUX_GPIO78__FUNC_BPI_BUS15_OLAT4 (MTK_PIN_NO(78) | 1) +-#define PINMUX_GPIO78__FUNC_CONN_BPI_BUS15_OLAT4 (MTK_PIN_NO(78) | 2) +- +-#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +-#define PINMUX_GPIO79__FUNC_BPI_BUS16_OLAT5 (MTK_PIN_NO(79) | 1) +-#define PINMUX_GPIO79__FUNC_CONN_BPI_BUS16_OLAT5 (MTK_PIN_NO(79) | 2) +- +-#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +-#define PINMUX_GPIO80__FUNC_BPI_BUS17_ANT0 (MTK_PIN_NO(80) | 1) +-#define PINMUX_GPIO80__FUNC_CONN_BPI_BUS17_ANT0 (MTK_PIN_NO(80) | 2) +-#define PINMUX_GPIO80__FUNC_PCIE_WAKE_N (MTK_PIN_NO(80) | 3) +- +-#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +-#define PINMUX_GPIO81__FUNC_BPI_BUS18_ANT1 (MTK_PIN_NO(81) | 1) +-#define PINMUX_GPIO81__FUNC_CONN_BPI_BUS18_ANT1 (MTK_PIN_NO(81) | 2) +-#define PINMUX_GPIO81__FUNC_PCIE_PERESET_N (MTK_PIN_NO(81) | 3) +- +-#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +-#define PINMUX_GPIO82__FUNC_BPI_BUS19_ANT2 (MTK_PIN_NO(82) | 1) +-#define PINMUX_GPIO82__FUNC_CONN_BPI_BUS19_ANT2 (MTK_PIN_NO(82) | 2) +-#define PINMUX_GPIO82__FUNC_PCIE_CLKREQ_N (MTK_PIN_NO(82) | 3) +- +-#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +-#define PINMUX_GPIO83__FUNC_BPI_BUS20_ANT3 (MTK_PIN_NO(83) | 1) +-#define PINMUX_GPIO83__FUNC_CONN_BPI_BUS20_ANT3 (MTK_PIN_NO(83) | 2) +- +-#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +-#define PINMUX_GPIO84__FUNC_BPI_BUS21_ANT4 (MTK_PIN_NO(84) | 1) +-#define PINMUX_GPIO84__FUNC_CONN_BPI_BUS21_ANT4 (MTK_PIN_NO(84) | 2) +- +-#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +-#define PINMUX_GPIO85__FUNC_MIPI1_D_SCLK (MTK_PIN_NO(85) | 1) +-#define PINMUX_GPIO85__FUNC_CONN_MIPI1_SCLK (MTK_PIN_NO(85) | 2) +- +-#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +-#define PINMUX_GPIO86__FUNC_MIPI1_D_SDATA (MTK_PIN_NO(86) | 1) +-#define PINMUX_GPIO86__FUNC_CONN_MIPI1_SDATA (MTK_PIN_NO(86) | 2) +- +-#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +-#define PINMUX_GPIO87__FUNC_MIPI0_D_SCLK (MTK_PIN_NO(87) | 1) +-#define PINMUX_GPIO87__FUNC_CONN_MIPI0_SCLK (MTK_PIN_NO(87) | 2) +- +-#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +-#define PINMUX_GPIO88__FUNC_MIPI0_D_SDATA (MTK_PIN_NO(88) | 1) +-#define PINMUX_GPIO88__FUNC_CONN_MIPI0_SDATA (MTK_PIN_NO(88) | 2) +- +-#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +-#define PINMUX_GPIO89__FUNC_SPMI_SCL (MTK_PIN_NO(89) | 1) +-#define PINMUX_GPIO89__FUNC_SCL10 (MTK_PIN_NO(89) | 2) +- +-#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +-#define PINMUX_GPIO90__FUNC_SPMI_SDA (MTK_PIN_NO(90) | 1) +-#define PINMUX_GPIO90__FUNC_SDA10 (MTK_PIN_NO(90) | 2) +- +-#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +-#define PINMUX_GPIO91__FUNC_AP_GOOD (MTK_PIN_NO(91) | 1) +- +-#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +-#define PINMUX_GPIO92__FUNC_URXD0 (MTK_PIN_NO(92) | 1) +-#define PINMUX_GPIO92__FUNC_MD_URXD0 (MTK_PIN_NO(92) | 2) +-#define PINMUX_GPIO92__FUNC_MD_URXD1 (MTK_PIN_NO(92) | 3) +-#define PINMUX_GPIO92__FUNC_SSPM_URXD_AO (MTK_PIN_NO(92) | 4) +-#define PINMUX_GPIO92__FUNC_CONN_UART0_RXD (MTK_PIN_NO(92) | 5) +- +-#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +-#define PINMUX_GPIO93__FUNC_UTXD0 (MTK_PIN_NO(93) | 1) +-#define PINMUX_GPIO93__FUNC_MD_UTXD0 (MTK_PIN_NO(93) | 2) +-#define PINMUX_GPIO93__FUNC_MD_UTXD1 (MTK_PIN_NO(93) | 3) +-#define PINMUX_GPIO93__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(93) | 4) +-#define PINMUX_GPIO93__FUNC_CONN_UART0_TXD (MTK_PIN_NO(93) | 5) +-#define PINMUX_GPIO93__FUNC_WIFI_TXD (MTK_PIN_NO(93) | 6) +- +-#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +-#define PINMUX_GPIO94__FUNC_URXD1 (MTK_PIN_NO(94) | 1) +-#define PINMUX_GPIO94__FUNC_ADSP_URXD0 (MTK_PIN_NO(94) | 2) +-#define PINMUX_GPIO94__FUNC_MD32_0_RXD (MTK_PIN_NO(94) | 3) +-#define PINMUX_GPIO94__FUNC_SSPM_URXD_AO (MTK_PIN_NO(94) | 4) +-#define PINMUX_GPIO94__FUNC_TP_URXD1_AO (MTK_PIN_NO(94) | 5) +-#define PINMUX_GPIO94__FUNC_TP_URXD2_AO (MTK_PIN_NO(94) | 6) +-#define PINMUX_GPIO94__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(94) | 7) +- +-#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +-#define PINMUX_GPIO95__FUNC_UTXD1 (MTK_PIN_NO(95) | 1) +-#define PINMUX_GPIO95__FUNC_ADSP_UTXD0 (MTK_PIN_NO(95) | 2) +-#define PINMUX_GPIO95__FUNC_MD32_0_TXD (MTK_PIN_NO(95) | 3) +-#define PINMUX_GPIO95__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(95) | 4) +-#define PINMUX_GPIO95__FUNC_TP_UTXD1_AO (MTK_PIN_NO(95) | 5) +-#define PINMUX_GPIO95__FUNC_TP_UTXD2_AO (MTK_PIN_NO(95) | 6) +-#define PINMUX_GPIO95__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(95) | 7) +- +-#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +-#define PINMUX_GPIO96__FUNC_TDM_LRCK (MTK_PIN_NO(96) | 1) +-#define PINMUX_GPIO96__FUNC_I2S7_LRCK (MTK_PIN_NO(96) | 2) +-#define PINMUX_GPIO96__FUNC_I2S9_LRCK (MTK_PIN_NO(96) | 3) +-#define PINMUX_GPIO96__FUNC_DPI_D0 (MTK_PIN_NO(96) | 4) +-#define PINMUX_GPIO96__FUNC_ADSP_JTAG0_TDI (MTK_PIN_NO(96) | 5) +-#define PINMUX_GPIO96__FUNC_IO_JTAG_TDI (MTK_PIN_NO(96) | 7) +- +-#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +-#define PINMUX_GPIO97__FUNC_TDM_BCK (MTK_PIN_NO(97) | 1) +-#define PINMUX_GPIO97__FUNC_I2S7_BCK (MTK_PIN_NO(97) | 2) +-#define PINMUX_GPIO97__FUNC_I2S9_BCK (MTK_PIN_NO(97) | 3) +-#define PINMUX_GPIO97__FUNC_DPI_D1 (MTK_PIN_NO(97) | 4) +-#define PINMUX_GPIO97__FUNC_ADSP_JTAG0_TRSTN (MTK_PIN_NO(97) | 5) +-#define PINMUX_GPIO97__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(97) | 7) +- +-#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +-#define PINMUX_GPIO98__FUNC_TDM_MCK (MTK_PIN_NO(98) | 1) +-#define PINMUX_GPIO98__FUNC_I2S7_MCK (MTK_PIN_NO(98) | 2) +-#define PINMUX_GPIO98__FUNC_I2S9_MCK (MTK_PIN_NO(98) | 3) +-#define PINMUX_GPIO98__FUNC_DPI_D2 (MTK_PIN_NO(98) | 4) +-#define PINMUX_GPIO98__FUNC_ADSP_JTAG0_TCK (MTK_PIN_NO(98) | 5) +-#define PINMUX_GPIO98__FUNC_IO_JTAG_TCK (MTK_PIN_NO(98) | 7) +- +-#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +-#define PINMUX_GPIO99__FUNC_TDM_DATA0 (MTK_PIN_NO(99) | 1) +-#define PINMUX_GPIO99__FUNC_I2S6_DI (MTK_PIN_NO(99) | 2) +-#define PINMUX_GPIO99__FUNC_I2S8_DI (MTK_PIN_NO(99) | 3) +-#define PINMUX_GPIO99__FUNC_DPI_D3 (MTK_PIN_NO(99) | 4) +-#define PINMUX_GPIO99__FUNC_ADSP_JTAG0_TDO (MTK_PIN_NO(99) | 5) +-#define PINMUX_GPIO99__FUNC_IO_JTAG_TDO (MTK_PIN_NO(99) | 7) +- +-#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +-#define PINMUX_GPIO100__FUNC_TDM_DATA1 (MTK_PIN_NO(100) | 1) +-#define PINMUX_GPIO100__FUNC_I2S7_DO (MTK_PIN_NO(100) | 2) +-#define PINMUX_GPIO100__FUNC_I2S9_DO (MTK_PIN_NO(100) | 3) +-#define PINMUX_GPIO100__FUNC_DPI_D4 (MTK_PIN_NO(100) | 4) +-#define PINMUX_GPIO100__FUNC_ADSP_JTAG0_TMS (MTK_PIN_NO(100) | 5) +-#define PINMUX_GPIO100__FUNC_IO_JTAG_TMS (MTK_PIN_NO(100) | 7) +- +-#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +-#define PINMUX_GPIO101__FUNC_TDM_DATA2 (MTK_PIN_NO(101) | 1) +-#define PINMUX_GPIO101__FUNC_DMIC1_CLK (MTK_PIN_NO(101) | 2) +-#define PINMUX_GPIO101__FUNC_SRCLKENAI0 (MTK_PIN_NO(101) | 3) +-#define PINMUX_GPIO101__FUNC_DPI_D5 (MTK_PIN_NO(101) | 4) +-#define PINMUX_GPIO101__FUNC_CLKM0 (MTK_PIN_NO(101) | 5) +-#define PINMUX_GPIO101__FUNC_DAP_MD32_SWD (MTK_PIN_NO(101) | 7) +- +-#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +-#define PINMUX_GPIO102__FUNC_TDM_DATA3 (MTK_PIN_NO(102) | 1) +-#define PINMUX_GPIO102__FUNC_DMIC1_DAT (MTK_PIN_NO(102) | 2) +-#define PINMUX_GPIO102__FUNC_SRCLKENAI1 (MTK_PIN_NO(102) | 3) +-#define PINMUX_GPIO102__FUNC_DPI_D6 (MTK_PIN_NO(102) | 4) +-#define PINMUX_GPIO102__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(102) | 6) +-#define PINMUX_GPIO102__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(102) | 7) +- +-#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +-#define PINMUX_GPIO103__FUNC_SPI0_A_MI (MTK_PIN_NO(103) | 1) +-#define PINMUX_GPIO103__FUNC_SCP_SPI0_MI (MTK_PIN_NO(103) | 2) +-#define PINMUX_GPIO103__FUNC_DPI_D7 (MTK_PIN_NO(103) | 4) +-#define PINMUX_GPIO103__FUNC_DFD_TDO (MTK_PIN_NO(103) | 5) +-#define PINMUX_GPIO103__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(103) | 6) +-#define PINMUX_GPIO103__FUNC_JTDO_SEL1 (MTK_PIN_NO(103) | 7) +- +-#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +-#define PINMUX_GPIO104__FUNC_SPI0_A_CSB (MTK_PIN_NO(104) | 1) +-#define PINMUX_GPIO104__FUNC_SCP_SPI0_CS (MTK_PIN_NO(104) | 2) +-#define PINMUX_GPIO104__FUNC_DPI_D8 (MTK_PIN_NO(104) | 4) +-#define PINMUX_GPIO104__FUNC_DFD_TMS (MTK_PIN_NO(104) | 5) +-#define PINMUX_GPIO104__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(104) | 6) +-#define PINMUX_GPIO104__FUNC_JTMS_SEL1 (MTK_PIN_NO(104) | 7) +- +-#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +-#define PINMUX_GPIO105__FUNC_SPI0_A_MO (MTK_PIN_NO(105) | 1) +-#define PINMUX_GPIO105__FUNC_SCP_SPI0_MO (MTK_PIN_NO(105) | 2) +-#define PINMUX_GPIO105__FUNC_SCP_SDA0 (MTK_PIN_NO(105) | 3) +-#define PINMUX_GPIO105__FUNC_DPI_D9 (MTK_PIN_NO(105) | 4) +-#define PINMUX_GPIO105__FUNC_DFD_TDI (MTK_PIN_NO(105) | 5) +-#define PINMUX_GPIO105__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(105) | 6) +-#define PINMUX_GPIO105__FUNC_JTDI_SEL1 (MTK_PIN_NO(105) | 7) +- +-#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +-#define PINMUX_GPIO106__FUNC_SPI0_A_CLK (MTK_PIN_NO(106) | 1) +-#define PINMUX_GPIO106__FUNC_SCP_SPI0_CK (MTK_PIN_NO(106) | 2) +-#define PINMUX_GPIO106__FUNC_SCP_SCL0 (MTK_PIN_NO(106) | 3) +-#define PINMUX_GPIO106__FUNC_DPI_D10 (MTK_PIN_NO(106) | 4) +-#define PINMUX_GPIO106__FUNC_DFD_TCK_XI (MTK_PIN_NO(106) | 5) +-#define PINMUX_GPIO106__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(106) | 6) +-#define PINMUX_GPIO106__FUNC_JTCK_SEL1 (MTK_PIN_NO(106) | 7) +- +-#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +-#define PINMUX_GPIO107__FUNC_DMIC_CLK (MTK_PIN_NO(107) | 1) +-#define PINMUX_GPIO107__FUNC_PWM_0 (MTK_PIN_NO(107) | 2) +-#define PINMUX_GPIO107__FUNC_CLKM2 (MTK_PIN_NO(107) | 3) +-#define PINMUX_GPIO107__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(107) | 6) +-#define PINMUX_GPIO107__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(107) | 7) +- +-#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +-#define PINMUX_GPIO108__FUNC_DMIC_DAT (MTK_PIN_NO(108) | 1) +-#define PINMUX_GPIO108__FUNC_PWM_1 (MTK_PIN_NO(108) | 2) +-#define PINMUX_GPIO108__FUNC_CLKM3 (MTK_PIN_NO(108) | 3) +-#define PINMUX_GPIO108__FUNC_DAP_SONIC_SWD (MTK_PIN_NO(108) | 7) +- +-#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +-#define PINMUX_GPIO109__FUNC_I2S1_MCK (MTK_PIN_NO(109) | 1) +-#define PINMUX_GPIO109__FUNC_I2S3_MCK (MTK_PIN_NO(109) | 2) +-#define PINMUX_GPIO109__FUNC_I2S2_MCK (MTK_PIN_NO(109) | 3) +-#define PINMUX_GPIO109__FUNC_DPI_DE (MTK_PIN_NO(109) | 4) +-#define PINMUX_GPIO109__FUNC_I2S2_MCK_A (MTK_PIN_NO(109) | 5) +-#define PINMUX_GPIO109__FUNC_SRCLKENAI0 (MTK_PIN_NO(109) | 6) +-#define PINMUX_GPIO109__FUNC_DAP_SONIC_SWCK (MTK_PIN_NO(109) | 7) +- +-#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +-#define PINMUX_GPIO110__FUNC_I2S1_BCK (MTK_PIN_NO(110) | 1) +-#define PINMUX_GPIO110__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 2) +-#define PINMUX_GPIO110__FUNC_I2S2_BCK (MTK_PIN_NO(110) | 3) +-#define PINMUX_GPIO110__FUNC_DPI_D11 (MTK_PIN_NO(110) | 4) +-#define PINMUX_GPIO110__FUNC_I2S2_BCK_A (MTK_PIN_NO(110) | 5) +-#define PINMUX_GPIO110__FUNC_CONN_MCU_TDO (MTK_PIN_NO(110) | 6) +- +-#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +-#define PINMUX_GPIO111__FUNC_I2S1_LRCK (MTK_PIN_NO(111) | 1) +-#define PINMUX_GPIO111__FUNC_I2S3_LRCK (MTK_PIN_NO(111) | 2) +-#define PINMUX_GPIO111__FUNC_I2S2_LRCK (MTK_PIN_NO(111) | 3) +-#define PINMUX_GPIO111__FUNC_DPI_VSYNC (MTK_PIN_NO(111) | 4) +-#define PINMUX_GPIO111__FUNC_I2S2_LRCK_A (MTK_PIN_NO(111) | 5) +-#define PINMUX_GPIO111__FUNC_CONN_MCU_TDI (MTK_PIN_NO(111) | 6) +- +-#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +-#define PINMUX_GPIO112__FUNC_I2S2_DI (MTK_PIN_NO(112) | 1) +-#define PINMUX_GPIO112__FUNC_I2S0_DI (MTK_PIN_NO(112) | 2) +-#define PINMUX_GPIO112__FUNC_I2S2_DI2 (MTK_PIN_NO(112) | 3) +-#define PINMUX_GPIO112__FUNC_DPI_CK (MTK_PIN_NO(112) | 4) +-#define PINMUX_GPIO112__FUNC_I2S2_DI_A (MTK_PIN_NO(112) | 5) +-#define PINMUX_GPIO112__FUNC_CONN_MCU_TMS (MTK_PIN_NO(112) | 6) +- +-#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +-#define PINMUX_GPIO113__FUNC_I2S1_DO (MTK_PIN_NO(113) | 1) +-#define PINMUX_GPIO113__FUNC_I2S3_DO (MTK_PIN_NO(113) | 2) +-#define PINMUX_GPIO113__FUNC_I2S5_DO (MTK_PIN_NO(113) | 3) +-#define PINMUX_GPIO113__FUNC_DPI_HSYNC (MTK_PIN_NO(113) | 4) +-#define PINMUX_GPIO113__FUNC_I2S2_DI2 (MTK_PIN_NO(113) | 5) +-#define PINMUX_GPIO113__FUNC_CONN_MCU_TCK (MTK_PIN_NO(113) | 6) +- +-#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +-#define PINMUX_GPIO114__FUNC_SPI2_MI (MTK_PIN_NO(114) | 1) +-#define PINMUX_GPIO114__FUNC_SCP_SPI2_MI (MTK_PIN_NO(114) | 2) +-#define PINMUX_GPIO114__FUNC_PCM0_DI (MTK_PIN_NO(114) | 4) +-#define PINMUX_GPIO114__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(114) | 6) +- +-#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +-#define PINMUX_GPIO115__FUNC_SPI2_CSB (MTK_PIN_NO(115) | 1) +-#define PINMUX_GPIO115__FUNC_SCP_SPI2_CS (MTK_PIN_NO(115) | 2) +-#define PINMUX_GPIO115__FUNC_PCM0_SYNC (MTK_PIN_NO(115) | 4) +-#define PINMUX_GPIO115__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(115) | 6) +- +-#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +-#define PINMUX_GPIO116__FUNC_SPI2_MO (MTK_PIN_NO(116) | 1) +-#define PINMUX_GPIO116__FUNC_SCP_SPI2_MO (MTK_PIN_NO(116) | 2) +-#define PINMUX_GPIO116__FUNC_SCP_SDA1 (MTK_PIN_NO(116) | 3) +-#define PINMUX_GPIO116__FUNC_PCM0_DO (MTK_PIN_NO(116) | 4) +-#define PINMUX_GPIO116__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(116) | 6) +- +-#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +-#define PINMUX_GPIO117__FUNC_SPI2_CLK (MTK_PIN_NO(117) | 1) +-#define PINMUX_GPIO117__FUNC_SCP_SPI2_CK (MTK_PIN_NO(117) | 2) +-#define PINMUX_GPIO117__FUNC_SCP_SCL1 (MTK_PIN_NO(117) | 3) +-#define PINMUX_GPIO117__FUNC_PCM0_CLK (MTK_PIN_NO(117) | 4) +- +-#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +-#define PINMUX_GPIO118__FUNC_SCL1 (MTK_PIN_NO(118) | 1) +-#define PINMUX_GPIO118__FUNC_SCP_SCL0 (MTK_PIN_NO(118) | 2) +-#define PINMUX_GPIO118__FUNC_SCP_SCL1 (MTK_PIN_NO(118) | 3) +- +-#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +-#define PINMUX_GPIO119__FUNC_SDA1 (MTK_PIN_NO(119) | 1) +-#define PINMUX_GPIO119__FUNC_SCP_SDA0 (MTK_PIN_NO(119) | 2) +-#define PINMUX_GPIO119__FUNC_SCP_SDA1 (MTK_PIN_NO(119) | 3) +- +-#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +-#define PINMUX_GPIO120__FUNC_SCL9 (MTK_PIN_NO(120) | 1) +-#define PINMUX_GPIO120__FUNC_SCP_SCL0 (MTK_PIN_NO(120) | 2) +- +-#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +-#define PINMUX_GPIO121__FUNC_SDA9 (MTK_PIN_NO(121) | 1) +-#define PINMUX_GPIO121__FUNC_SCP_SDA0 (MTK_PIN_NO(121) | 2) +- +-#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +-#define PINMUX_GPIO122__FUNC_SCL8 (MTK_PIN_NO(122) | 1) +-#define PINMUX_GPIO122__FUNC_SCP_SDA0 (MTK_PIN_NO(122) | 2) +- +-#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +-#define PINMUX_GPIO123__FUNC_SDA8 (MTK_PIN_NO(123) | 1) +-#define PINMUX_GPIO123__FUNC_SCP_SCL0 (MTK_PIN_NO(123) | 2) +- +-#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +-#define PINMUX_GPIO124__FUNC_SCL7 (MTK_PIN_NO(124) | 1) +-#define PINMUX_GPIO124__FUNC_DMIC1_CLK (MTK_PIN_NO(124) | 2) +- +-#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +-#define PINMUX_GPIO125__FUNC_SDA7 (MTK_PIN_NO(125) | 1) +-#define PINMUX_GPIO125__FUNC_DMIC1_DAT (MTK_PIN_NO(125) | 2) +- +-#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +-#define PINMUX_GPIO126__FUNC_CMFLASH0 (MTK_PIN_NO(126) | 1) +-#define PINMUX_GPIO126__FUNC_PWM_2 (MTK_PIN_NO(126) | 2) +-#define PINMUX_GPIO126__FUNC_TP_UCTS1_AO (MTK_PIN_NO(126) | 3) +-#define PINMUX_GPIO126__FUNC_UCTS0 (MTK_PIN_NO(126) | 4) +-#define PINMUX_GPIO126__FUNC_SCL11 (MTK_PIN_NO(126) | 5) +-#define PINMUX_GPIO126__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(126) | 6) +-#define PINMUX_GPIO126__FUNC_DBG_MON_A14 (MTK_PIN_NO(126) | 7) +- +-#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +-#define PINMUX_GPIO127__FUNC_CMFLASH1 (MTK_PIN_NO(127) | 1) +-#define PINMUX_GPIO127__FUNC_PWM_3 (MTK_PIN_NO(127) | 2) +-#define PINMUX_GPIO127__FUNC_TP_URTS1_AO (MTK_PIN_NO(127) | 3) +-#define PINMUX_GPIO127__FUNC_URTS0 (MTK_PIN_NO(127) | 4) +-#define PINMUX_GPIO127__FUNC_SDA11 (MTK_PIN_NO(127) | 5) +-#define PINMUX_GPIO127__FUNC_DBG_MON_A15 (MTK_PIN_NO(127) | 7) +- +-#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +-#define PINMUX_GPIO128__FUNC_CMFLASH2 (MTK_PIN_NO(128) | 1) +-#define PINMUX_GPIO128__FUNC_PWM_0 (MTK_PIN_NO(128) | 2) +-#define PINMUX_GPIO128__FUNC_TP_UCTS2_AO (MTK_PIN_NO(128) | 3) +-#define PINMUX_GPIO128__FUNC_UCTS1 (MTK_PIN_NO(128) | 4) +-#define PINMUX_GPIO128__FUNC_SCL_6306 (MTK_PIN_NO(128) | 5) +-#define PINMUX_GPIO128__FUNC_DBG_MON_A16 (MTK_PIN_NO(128) | 7) +- +-#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +-#define PINMUX_GPIO129__FUNC_CMFLASH3 (MTK_PIN_NO(129) | 1) +-#define PINMUX_GPIO129__FUNC_PWM_1 (MTK_PIN_NO(129) | 2) +-#define PINMUX_GPIO129__FUNC_TP_URTS2_AO (MTK_PIN_NO(129) | 3) +-#define PINMUX_GPIO129__FUNC_URTS1 (MTK_PIN_NO(129) | 4) +-#define PINMUX_GPIO129__FUNC_SDA_6306 (MTK_PIN_NO(129) | 5) +-#define PINMUX_GPIO129__FUNC_DBG_MON_A17 (MTK_PIN_NO(129) | 7) +- +-#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +-#define PINMUX_GPIO130__FUNC_CMVREF0 (MTK_PIN_NO(130) | 1) +-#define PINMUX_GPIO130__FUNC_ANT_SEL10 (MTK_PIN_NO(130) | 2) +-#define PINMUX_GPIO130__FUNC_SCP_JTAG0_TDO (MTK_PIN_NO(130) | 3) +-#define PINMUX_GPIO130__FUNC_MD32_0_JTAG_TDO (MTK_PIN_NO(130) | 4) +-#define PINMUX_GPIO130__FUNC_SCL11 (MTK_PIN_NO(130) | 5) +-#define PINMUX_GPIO130__FUNC_SPI5_B_CLK (MTK_PIN_NO(130) | 6) +-#define PINMUX_GPIO130__FUNC_DBG_MON_A22 (MTK_PIN_NO(130) | 7) +- +-#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +-#define PINMUX_GPIO131__FUNC_CMVREF1 (MTK_PIN_NO(131) | 1) +-#define PINMUX_GPIO131__FUNC_ANT_SEL11 (MTK_PIN_NO(131) | 2) +-#define PINMUX_GPIO131__FUNC_SCP_JTAG0_TDI (MTK_PIN_NO(131) | 3) +-#define PINMUX_GPIO131__FUNC_MD32_0_JTAG_TDI (MTK_PIN_NO(131) | 4) +-#define PINMUX_GPIO131__FUNC_SDA11 (MTK_PIN_NO(131) | 5) +-#define PINMUX_GPIO131__FUNC_SPI5_B_MO (MTK_PIN_NO(131) | 6) +-#define PINMUX_GPIO131__FUNC_DBG_MON_A25 (MTK_PIN_NO(131) | 7) +- +-#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +-#define PINMUX_GPIO132__FUNC_CMVREF2 (MTK_PIN_NO(132) | 1) +-#define PINMUX_GPIO132__FUNC_ANT_SEL12 (MTK_PIN_NO(132) | 2) +-#define PINMUX_GPIO132__FUNC_SCP_JTAG0_TMS (MTK_PIN_NO(132) | 3) +-#define PINMUX_GPIO132__FUNC_MD32_0_JTAG_TMS (MTK_PIN_NO(132) | 4) +-#define PINMUX_GPIO132__FUNC_DBG_MON_A28 (MTK_PIN_NO(132) | 7) +- +-#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +-#define PINMUX_GPIO133__FUNC_CMVREF3 (MTK_PIN_NO(133) | 1) +-#define PINMUX_GPIO133__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(133) | 2) +-#define PINMUX_GPIO133__FUNC_SCP_JTAG0_TCK (MTK_PIN_NO(133) | 3) +-#define PINMUX_GPIO133__FUNC_MD32_0_JTAG_TCK (MTK_PIN_NO(133) | 4) +-#define PINMUX_GPIO133__FUNC_SPI5_B_CSB (MTK_PIN_NO(133) | 6) +-#define PINMUX_GPIO133__FUNC_DBG_MON_A23 (MTK_PIN_NO(133) | 7) +- +-#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +-#define PINMUX_GPIO134__FUNC_CMVREF4 (MTK_PIN_NO(134) | 1) +-#define PINMUX_GPIO134__FUNC_SCP_JTAG0_TRSTN (MTK_PIN_NO(134) | 3) +-#define PINMUX_GPIO134__FUNC_MD32_0_JTAG_TRST (MTK_PIN_NO(134) | 4) +-#define PINMUX_GPIO134__FUNC_DBG_MON_A26 (MTK_PIN_NO(134) | 7) +- +-#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +-#define PINMUX_GPIO135__FUNC_PWM_0 (MTK_PIN_NO(135) | 1) +-#define PINMUX_GPIO135__FUNC_SRCLKENAI1 (MTK_PIN_NO(135) | 2) +-#define PINMUX_GPIO135__FUNC_MD_URXD0 (MTK_PIN_NO(135) | 3) +-#define PINMUX_GPIO135__FUNC_MD32_0_RXD (MTK_PIN_NO(135) | 4) +-#define PINMUX_GPIO135__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(135) | 5) +-#define PINMUX_GPIO135__FUNC_DBG_MON_A29 (MTK_PIN_NO(135) | 7) +- +-#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +-#define PINMUX_GPIO136__FUNC_CMMCLK3 (MTK_PIN_NO(136) | 1) +-#define PINMUX_GPIO136__FUNC_CLKM1 (MTK_PIN_NO(136) | 2) +-#define PINMUX_GPIO136__FUNC_MD_UTXD0 (MTK_PIN_NO(136) | 3) +-#define PINMUX_GPIO136__FUNC_MD32_0_TXD (MTK_PIN_NO(136) | 4) +-#define PINMUX_GPIO136__FUNC_SPI5_B_MI (MTK_PIN_NO(136) | 6) +-#define PINMUX_GPIO136__FUNC_DBG_MON_A24 (MTK_PIN_NO(136) | 7) +- +-#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +-#define PINMUX_GPIO137__FUNC_CMMCLK4 (MTK_PIN_NO(137) | 1) +-#define PINMUX_GPIO137__FUNC_CLKM2 (MTK_PIN_NO(137) | 2) +-#define PINMUX_GPIO137__FUNC_MD_URXD1 (MTK_PIN_NO(137) | 3) +-#define PINMUX_GPIO137__FUNC_CONN_UART0_RXD (MTK_PIN_NO(137) | 6) +-#define PINMUX_GPIO137__FUNC_DBG_MON_A27 (MTK_PIN_NO(137) | 7) +- +-#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +-#define PINMUX_GPIO138__FUNC_CMMCLK5 (MTK_PIN_NO(138) | 1) +-#define PINMUX_GPIO138__FUNC_CLKM3 (MTK_PIN_NO(138) | 2) +-#define PINMUX_GPIO138__FUNC_MD_UTXD1 (MTK_PIN_NO(138) | 3) +-#define PINMUX_GPIO138__FUNC_CONN_UART0_TXD (MTK_PIN_NO(138) | 6) +-#define PINMUX_GPIO138__FUNC_DBG_MON_A30 (MTK_PIN_NO(138) | 7) +- +-#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +-#define PINMUX_GPIO139__FUNC_SCL4 (MTK_PIN_NO(139) | 1) +-#define PINMUX_GPIO139__FUNC_DBG_MON_A21 (MTK_PIN_NO(139) | 7) +- +-#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +-#define PINMUX_GPIO140__FUNC_SDA4 (MTK_PIN_NO(140) | 1) +-#define PINMUX_GPIO140__FUNC_DBG_MON_A20 (MTK_PIN_NO(140) | 7) +- +-#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +-#define PINMUX_GPIO141__FUNC_SCL2 (MTK_PIN_NO(141) | 1) +-#define PINMUX_GPIO141__FUNC_DBG_MON_A18 (MTK_PIN_NO(141) | 7) +- +-#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +-#define PINMUX_GPIO142__FUNC_SDA2 (MTK_PIN_NO(142) | 1) +-#define PINMUX_GPIO142__FUNC_DBG_MON_A19 (MTK_PIN_NO(142) | 7) +- +-#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +-#define PINMUX_GPIO143__FUNC_CMVREF0 (MTK_PIN_NO(143) | 1) +-#define PINMUX_GPIO143__FUNC_SPI3_CLK (MTK_PIN_NO(143) | 2) +-#define PINMUX_GPIO143__FUNC_ADSP_JTAG1_TDO (MTK_PIN_NO(143) | 3) +-#define PINMUX_GPIO143__FUNC_SCP_JTAG1_TDO (MTK_PIN_NO(143) | 4) +-#define PINMUX_GPIO143__FUNC_DBG_MON_A31 (MTK_PIN_NO(143) | 7) +- +-#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +-#define PINMUX_GPIO144__FUNC_CMVREF1 (MTK_PIN_NO(144) | 1) +-#define PINMUX_GPIO144__FUNC_SPI3_CSB (MTK_PIN_NO(144) | 2) +-#define PINMUX_GPIO144__FUNC_ADSP_JTAG1_TDI (MTK_PIN_NO(144) | 3) +-#define PINMUX_GPIO144__FUNC_SCP_JTAG1_TDI (MTK_PIN_NO(144) | 4) +- +-#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +-#define PINMUX_GPIO145__FUNC_CMVREF2 (MTK_PIN_NO(145) | 1) +-#define PINMUX_GPIO145__FUNC_SPI3_MI (MTK_PIN_NO(145) | 2) +-#define PINMUX_GPIO145__FUNC_ADSP_JTAG1_TMS (MTK_PIN_NO(145) | 3) +-#define PINMUX_GPIO145__FUNC_SCP_JTAG1_TMS (MTK_PIN_NO(145) | 4) +- +-#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +-#define PINMUX_GPIO146__FUNC_CMVREF3 (MTK_PIN_NO(146) | 1) +-#define PINMUX_GPIO146__FUNC_SPI3_MO (MTK_PIN_NO(146) | 2) +-#define PINMUX_GPIO146__FUNC_ADSP_JTAG1_TCK (MTK_PIN_NO(146) | 3) +-#define PINMUX_GPIO146__FUNC_SCP_JTAG1_TCK (MTK_PIN_NO(146) | 4) +-#define PINMUX_GPIO146__FUNC_DBG_MON_A32 (MTK_PIN_NO(146) | 7) +- +-#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +-#define PINMUX_GPIO147__FUNC_CMVREF4 (MTK_PIN_NO(147) | 1) +-#define PINMUX_GPIO147__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(147) | 2) +-#define PINMUX_GPIO147__FUNC_ADSP_JTAG1_TRSTN (MTK_PIN_NO(147) | 3) +-#define PINMUX_GPIO147__FUNC_SCP_JTAG1_TRSTN (MTK_PIN_NO(147) | 4) +- +-#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +-#define PINMUX_GPIO148__FUNC_PWM_1 (MTK_PIN_NO(148) | 1) +-#define PINMUX_GPIO148__FUNC_AGPS_SYNC (MTK_PIN_NO(148) | 2) +-#define PINMUX_GPIO148__FUNC_CMMCLK5 (MTK_PIN_NO(148) | 3) +- +-#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +-#define PINMUX_GPIO149__FUNC_CMMCLK0 (MTK_PIN_NO(149) | 1) +-#define PINMUX_GPIO149__FUNC_CLKM0 (MTK_PIN_NO(149) | 2) +-#define PINMUX_GPIO149__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(149) | 3) +- +-#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +-#define PINMUX_GPIO150__FUNC_CMMCLK1 (MTK_PIN_NO(150) | 1) +-#define PINMUX_GPIO150__FUNC_CLKM1 (MTK_PIN_NO(150) | 2) +-#define PINMUX_GPIO150__FUNC_MD32_0_GPIO1 (MTK_PIN_NO(150) | 3) +-#define PINMUX_GPIO150__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(150) | 7) +- +-#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +-#define PINMUX_GPIO151__FUNC_CMMCLK2 (MTK_PIN_NO(151) | 1) +-#define PINMUX_GPIO151__FUNC_CLKM2 (MTK_PIN_NO(151) | 2) +-#define PINMUX_GPIO151__FUNC_MD32_0_GPIO2 (MTK_PIN_NO(151) | 3) +-#define PINMUX_GPIO151__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(151) | 7) +- +-#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +-#define PINMUX_GPIO152__FUNC_KPROW1 (MTK_PIN_NO(152) | 1) +-#define PINMUX_GPIO152__FUNC_PWM_2 (MTK_PIN_NO(152) | 2) +-#define PINMUX_GPIO152__FUNC_IDDIG (MTK_PIN_NO(152) | 3) +-#define PINMUX_GPIO152__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(152) | 6) +-#define PINMUX_GPIO152__FUNC_DBG_MON_B9 (MTK_PIN_NO(152) | 7) +- +-#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +-#define PINMUX_GPIO153__FUNC_KPROW0 (MTK_PIN_NO(153) | 1) +-#define PINMUX_GPIO153__FUNC_DBG_MON_B8 (MTK_PIN_NO(153) | 7) +- +-#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +-#define PINMUX_GPIO154__FUNC_KPCOL0 (MTK_PIN_NO(154) | 1) +-#define PINMUX_GPIO154__FUNC_DBG_MON_B6 (MTK_PIN_NO(154) | 7) +- +-#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +-#define PINMUX_GPIO155__FUNC_KPCOL1 (MTK_PIN_NO(155) | 1) +-#define PINMUX_GPIO155__FUNC_PWM_3 (MTK_PIN_NO(155) | 2) +-#define PINMUX_GPIO155__FUNC_USB_DRVVBUS (MTK_PIN_NO(155) | 3) +-#define PINMUX_GPIO155__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(155) | 4) +-#define PINMUX_GPIO155__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(155) | 6) +-#define PINMUX_GPIO155__FUNC_DBG_MON_B7 (MTK_PIN_NO(155) | 7) +- +-#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +-#define PINMUX_GPIO156__FUNC_SPI1_A_CLK (MTK_PIN_NO(156) | 1) +-#define PINMUX_GPIO156__FUNC_SCP_SPI1_A_CK (MTK_PIN_NO(156) | 2) +-#define PINMUX_GPIO156__FUNC_MRG_CLK (MTK_PIN_NO(156) | 3) +-#define PINMUX_GPIO156__FUNC_AGPS_SYNC (MTK_PIN_NO(156) | 4) +-#define PINMUX_GPIO156__FUNC_MD_URXD0 (MTK_PIN_NO(156) | 5) +-#define PINMUX_GPIO156__FUNC_UDI_TMS (MTK_PIN_NO(156) | 6) +-#define PINMUX_GPIO156__FUNC_DBG_MON_B10 (MTK_PIN_NO(156) | 7) +- +-#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +-#define PINMUX_GPIO157__FUNC_SPI1_A_CSB (MTK_PIN_NO(157) | 1) +-#define PINMUX_GPIO157__FUNC_SCP_SPI1_A_CS (MTK_PIN_NO(157) | 2) +-#define PINMUX_GPIO157__FUNC_MRG_SYNC (MTK_PIN_NO(157) | 3) +-#define PINMUX_GPIO157__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(157) | 4) +-#define PINMUX_GPIO157__FUNC_MD_UTXD0 (MTK_PIN_NO(157) | 5) +-#define PINMUX_GPIO157__FUNC_UDI_TCK (MTK_PIN_NO(157) | 6) +-#define PINMUX_GPIO157__FUNC_DBG_MON_B11 (MTK_PIN_NO(157) | 7) +- +-#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +-#define PINMUX_GPIO158__FUNC_SPI1_A_MI (MTK_PIN_NO(158) | 1) +-#define PINMUX_GPIO158__FUNC_SCP_SPI1_A_MI (MTK_PIN_NO(158) | 2) +-#define PINMUX_GPIO158__FUNC_MRG_DI (MTK_PIN_NO(158) | 3) +-#define PINMUX_GPIO158__FUNC_PTA_RXD (MTK_PIN_NO(158) | 4) +-#define PINMUX_GPIO158__FUNC_MD_URXD1 (MTK_PIN_NO(158) | 5) +-#define PINMUX_GPIO158__FUNC_UDI_TDO (MTK_PIN_NO(158) | 6) +-#define PINMUX_GPIO158__FUNC_DBG_MON_B12 (MTK_PIN_NO(158) | 7) +- +-#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +-#define PINMUX_GPIO159__FUNC_SPI1_A_MO (MTK_PIN_NO(159) | 1) +-#define PINMUX_GPIO159__FUNC_SCP_SPI1_A_MO (MTK_PIN_NO(159) | 2) +-#define PINMUX_GPIO159__FUNC_MRG_DO (MTK_PIN_NO(159) | 3) +-#define PINMUX_GPIO159__FUNC_PTA_TXD (MTK_PIN_NO(159) | 4) +-#define PINMUX_GPIO159__FUNC_MD_UTXD1 (MTK_PIN_NO(159) | 5) +-#define PINMUX_GPIO159__FUNC_UDI_NTRST (MTK_PIN_NO(159) | 6) +-#define PINMUX_GPIO159__FUNC_DBG_MON_B13 (MTK_PIN_NO(159) | 7) +- +-#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +-#define PINMUX_GPIO160__FUNC_SCL3 (MTK_PIN_NO(160) | 1) +-#define PINMUX_GPIO160__FUNC_SCP_SCL1 (MTK_PIN_NO(160) | 3) +-#define PINMUX_GPIO160__FUNC_DBG_MON_B14 (MTK_PIN_NO(160) | 7) +- +-#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +-#define PINMUX_GPIO161__FUNC_SDA3 (MTK_PIN_NO(161) | 1) +-#define PINMUX_GPIO161__FUNC_SCP_SDA1 (MTK_PIN_NO(161) | 3) +-#define PINMUX_GPIO161__FUNC_DBG_MON_B15 (MTK_PIN_NO(161) | 7) +- +-#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +-#define PINMUX_GPIO162__FUNC_ANT_SEL0 (MTK_PIN_NO(162) | 1) +-#define PINMUX_GPIO162__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(162) | 2) +-#define PINMUX_GPIO162__FUNC_UDI_TDI (MTK_PIN_NO(162) | 6) +-#define PINMUX_GPIO162__FUNC_DBG_MON_B16 (MTK_PIN_NO(162) | 7) +- +-#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +-#define PINMUX_GPIO163__FUNC_ANT_SEL1 (MTK_PIN_NO(163) | 1) +-#define PINMUX_GPIO163__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(163) | 2) +-#define PINMUX_GPIO163__FUNC_DBG_MON_B17 (MTK_PIN_NO(163) | 7) +- +-#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +-#define PINMUX_GPIO164__FUNC_ANT_SEL2 (MTK_PIN_NO(164) | 1) +-#define PINMUX_GPIO164__FUNC_SCP_SPI1_B_CK (MTK_PIN_NO(164) | 2) +-#define PINMUX_GPIO164__FUNC_TP_URXD1_AO (MTK_PIN_NO(164) | 3) +-#define PINMUX_GPIO164__FUNC_UCTS0 (MTK_PIN_NO(164) | 5) +-#define PINMUX_GPIO164__FUNC_DBG_MON_B18 (MTK_PIN_NO(164) | 7) +- +-#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +-#define PINMUX_GPIO165__FUNC_ANT_SEL3 (MTK_PIN_NO(165) | 1) +-#define PINMUX_GPIO165__FUNC_SCP_SPI1_B_CS (MTK_PIN_NO(165) | 2) +-#define PINMUX_GPIO165__FUNC_TP_UTXD1_AO (MTK_PIN_NO(165) | 3) +-#define PINMUX_GPIO165__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(165) | 4) +-#define PINMUX_GPIO165__FUNC_URTS0 (MTK_PIN_NO(165) | 5) +-#define PINMUX_GPIO165__FUNC_DBG_MON_B19 (MTK_PIN_NO(165) | 7) +- +-#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +-#define PINMUX_GPIO166__FUNC_ANT_SEL4 (MTK_PIN_NO(166) | 1) +-#define PINMUX_GPIO166__FUNC_SCP_SPI1_B_MI (MTK_PIN_NO(166) | 2) +-#define PINMUX_GPIO166__FUNC_TP_URXD2_AO (MTK_PIN_NO(166) | 3) +-#define PINMUX_GPIO166__FUNC_SRCLKENAI1 (MTK_PIN_NO(166) | 4) +-#define PINMUX_GPIO166__FUNC_UCTS1 (MTK_PIN_NO(166) | 5) +-#define PINMUX_GPIO166__FUNC_DBG_MON_B20 (MTK_PIN_NO(166) | 7) +- +-#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +-#define PINMUX_GPIO167__FUNC_ANT_SEL5 (MTK_PIN_NO(167) | 1) +-#define PINMUX_GPIO167__FUNC_SCP_SPI1_B_MO (MTK_PIN_NO(167) | 2) +-#define PINMUX_GPIO167__FUNC_TP_UTXD2_AO (MTK_PIN_NO(167) | 3) +-#define PINMUX_GPIO167__FUNC_SRCLKENAI0 (MTK_PIN_NO(167) | 4) +-#define PINMUX_GPIO167__FUNC_URTS1 (MTK_PIN_NO(167) | 5) +-#define PINMUX_GPIO167__FUNC_DBG_MON_B21 (MTK_PIN_NO(167) | 7) +- +-#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +-#define PINMUX_GPIO168__FUNC_ANT_SEL6 (MTK_PIN_NO(168) | 1) +-#define PINMUX_GPIO168__FUNC_SPI0_B_CLK (MTK_PIN_NO(168) | 2) +-#define PINMUX_GPIO168__FUNC_TP_UCTS1_AO (MTK_PIN_NO(168) | 3) +-#define PINMUX_GPIO168__FUNC_KPCOL2 (MTK_PIN_NO(168) | 4) +-#define PINMUX_GPIO168__FUNC_MD_UCTS0 (MTK_PIN_NO(168) | 5) +-#define PINMUX_GPIO168__FUNC_SCL11 (MTK_PIN_NO(168) | 6) +-#define PINMUX_GPIO168__FUNC_DBG_MON_B22 (MTK_PIN_NO(168) | 7) +- +-#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +-#define PINMUX_GPIO169__FUNC_ANT_SEL7 (MTK_PIN_NO(169) | 1) +-#define PINMUX_GPIO169__FUNC_SPI0_B_CSB (MTK_PIN_NO(169) | 2) +-#define PINMUX_GPIO169__FUNC_TP_URTS1_AO (MTK_PIN_NO(169) | 3) +-#define PINMUX_GPIO169__FUNC_KPROW2 (MTK_PIN_NO(169) | 4) +-#define PINMUX_GPIO169__FUNC_MD_URTS0 (MTK_PIN_NO(169) | 5) +-#define PINMUX_GPIO169__FUNC_SDA11 (MTK_PIN_NO(169) | 6) +-#define PINMUX_GPIO169__FUNC_DBG_MON_B23 (MTK_PIN_NO(169) | 7) +- +-#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +-#define PINMUX_GPIO170__FUNC_ANT_SEL8 (MTK_PIN_NO(170) | 1) +-#define PINMUX_GPIO170__FUNC_SPI0_B_MI (MTK_PIN_NO(170) | 2) +-#define PINMUX_GPIO170__FUNC_TP_UCTS2_AO (MTK_PIN_NO(170) | 3) +-#define PINMUX_GPIO170__FUNC_SRCLKENAI1 (MTK_PIN_NO(170) | 4) +-#define PINMUX_GPIO170__FUNC_MD_UCTS1 (MTK_PIN_NO(170) | 5) +-#define PINMUX_GPIO170__FUNC_DBG_MON_B24 (MTK_PIN_NO(170) | 7) +- +-#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +-#define PINMUX_GPIO171__FUNC_ANT_SEL9 (MTK_PIN_NO(171) | 1) +-#define PINMUX_GPIO171__FUNC_SPI0_B_MO (MTK_PIN_NO(171) | 2) +-#define PINMUX_GPIO171__FUNC_TP_URTS2_AO (MTK_PIN_NO(171) | 3) +-#define PINMUX_GPIO171__FUNC_SRCLKENAI0 (MTK_PIN_NO(171) | 4) +-#define PINMUX_GPIO171__FUNC_MD_URTS1 (MTK_PIN_NO(171) | 5) +-#define PINMUX_GPIO171__FUNC_DBG_MON_B25 (MTK_PIN_NO(171) | 7) +- +-#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +-#define PINMUX_GPIO172__FUNC_CONN_TOP_CLK (MTK_PIN_NO(172) | 1) +-#define PINMUX_GPIO172__FUNC_AUXIF_CLK0 (MTK_PIN_NO(172) | 2) +-#define PINMUX_GPIO172__FUNC_DBG_MON_B29 (MTK_PIN_NO(172) | 7) +- +-#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +-#define PINMUX_GPIO173__FUNC_CONN_TOP_DATA (MTK_PIN_NO(173) | 1) +-#define PINMUX_GPIO173__FUNC_AUXIF_ST0 (MTK_PIN_NO(173) | 2) +-#define PINMUX_GPIO173__FUNC_DBG_MON_B30 (MTK_PIN_NO(173) | 7) +- +-#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +-#define PINMUX_GPIO174__FUNC_CONN_HRST_B (MTK_PIN_NO(174) | 1) +-#define PINMUX_GPIO174__FUNC_DBG_MON_B28 (MTK_PIN_NO(174) | 7) +- +-#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +-#define PINMUX_GPIO175__FUNC_CONN_WB_PTA (MTK_PIN_NO(175) | 1) +-#define PINMUX_GPIO175__FUNC_DBG_MON_B31 (MTK_PIN_NO(175) | 7) +- +-#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +-#define PINMUX_GPIO176__FUNC_CONN_BT_CLK (MTK_PIN_NO(176) | 1) +-#define PINMUX_GPIO176__FUNC_AUXIF_CLK1 (MTK_PIN_NO(176) | 2) +-#define PINMUX_GPIO176__FUNC_DBG_MON_B26 (MTK_PIN_NO(176) | 7) +- +-#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +-#define PINMUX_GPIO177__FUNC_CONN_BT_DATA (MTK_PIN_NO(177) | 1) +-#define PINMUX_GPIO177__FUNC_AUXIF_ST1 (MTK_PIN_NO(177) | 2) +-#define PINMUX_GPIO177__FUNC_DBG_MON_B27 (MTK_PIN_NO(177) | 7) +- +-#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +-#define PINMUX_GPIO178__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(178) | 1) +- +-#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +-#define PINMUX_GPIO179__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(179) | 1) +-#define PINMUX_GPIO179__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(179) | 2) +- +-#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +-#define PINMUX_GPIO180__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(180) | 1) +-#define PINMUX_GPIO180__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(180) | 2) +- +-#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +-#define PINMUX_GPIO181__FUNC_CONN_WF_CTRL3 (MTK_PIN_NO(181) | 1) +- +-#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +-#define PINMUX_GPIO182__FUNC_CONN_WF_CTRL4 (MTK_PIN_NO(182) | 1) +- +-#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +-#define PINMUX_GPIO183__FUNC_MSDC0_CMD (MTK_PIN_NO(183) | 1) +- +-#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +-#define PINMUX_GPIO184__FUNC_MSDC0_DAT0 (MTK_PIN_NO(184) | 1) +- +-#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +-#define PINMUX_GPIO185__FUNC_MSDC0_DAT2 (MTK_PIN_NO(185) | 1) +- +-#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +-#define PINMUX_GPIO186__FUNC_MSDC0_DAT4 (MTK_PIN_NO(186) | 1) +- +-#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +-#define PINMUX_GPIO187__FUNC_MSDC0_DAT6 (MTK_PIN_NO(187) | 1) +- +-#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +-#define PINMUX_GPIO188__FUNC_MSDC0_DAT1 (MTK_PIN_NO(188) | 1) +- +-#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +-#define PINMUX_GPIO189__FUNC_MSDC0_DAT5 (MTK_PIN_NO(189) | 1) +- +-#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +-#define PINMUX_GPIO190__FUNC_MSDC0_DAT7 (MTK_PIN_NO(190) | 1) +- +-#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +-#define PINMUX_GPIO191__FUNC_MSDC0_DSL (MTK_PIN_NO(191) | 1) +-#define PINMUX_GPIO191__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(191) | 2) +-#define PINMUX_GPIO191__FUNC_IDDIG (MTK_PIN_NO(191) | 3) +-#define PINMUX_GPIO191__FUNC_DMIC_CLK (MTK_PIN_NO(191) | 4) +- +-#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +-#define PINMUX_GPIO192__FUNC_MSDC0_CLK (MTK_PIN_NO(192) | 1) +-#define PINMUX_GPIO192__FUNC_USB_DRVVBUS (MTK_PIN_NO(192) | 3) +-#define PINMUX_GPIO192__FUNC_DMIC_DAT (MTK_PIN_NO(192) | 4) +- +-#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +-#define PINMUX_GPIO193__FUNC_MSDC0_DAT3 (MTK_PIN_NO(193) | 1) +- +-#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +-#define PINMUX_GPIO194__FUNC_MSDC0_RSTB (MTK_PIN_NO(194) | 1) +- +-#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +-#define PINMUX_GPIO195__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(195) | 1) +-#define PINMUX_GPIO195__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(195) | 2) +- +-#define PINMUX_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +-#define PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2 (MTK_PIN_NO(196) | 1) +- +-#define PINMUX_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +-#define PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1 (MTK_PIN_NO(197) | 1) +-#define PINMUX_GPIO197__FUNC_AUD_CLK_MISO (MTK_PIN_NO(197) | 2) +-#define PINMUX_GPIO197__FUNC_I2S2_MCK (MTK_PIN_NO(197) | 3) +-#define PINMUX_GPIO197__FUNC_I2S6_MCK (MTK_PIN_NO(197) | 4) +-#define PINMUX_GPIO197__FUNC_I2S8_MCK (MTK_PIN_NO(197) | 5) +- +-#define PINMUX_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +-#define PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0 (MTK_PIN_NO(198) | 1) +-#define PINMUX_GPIO198__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(198) | 2) +-#define PINMUX_GPIO198__FUNC_I2S2_BCK (MTK_PIN_NO(198) | 3) +-#define PINMUX_GPIO198__FUNC_I2S6_BCK (MTK_PIN_NO(198) | 4) +-#define PINMUX_GPIO198__FUNC_I2S8_BCK (MTK_PIN_NO(198) | 5) +- +-#define PINMUX_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +-#define PINMUX_GPIO199__FUNC_AUD_DAT_MISO2 (MTK_PIN_NO(199) | 1) +-#define PINMUX_GPIO199__FUNC_I2S2_DI2 (MTK_PIN_NO(199) | 3) +- +-#define PINMUX_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +-#define PINMUX_GPIO200__FUNC_SCL6 (MTK_PIN_NO(200) | 1) +-#define PINMUX_GPIO200__FUNC_SCP_SCL1 (MTK_PIN_NO(200) | 3) +-#define PINMUX_GPIO200__FUNC_SCL_6306 (MTK_PIN_NO(200) | 4) +-#define PINMUX_GPIO200__FUNC_DBG_MON_A4 (MTK_PIN_NO(200) | 7) +- +-#define PINMUX_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +-#define PINMUX_GPIO201__FUNC_SDA6 (MTK_PIN_NO(201) | 1) +-#define PINMUX_GPIO201__FUNC_SCP_SDA1 (MTK_PIN_NO(201) | 3) +-#define PINMUX_GPIO201__FUNC_SDA_6306 (MTK_PIN_NO(201) | 4) +-#define PINMUX_GPIO201__FUNC_DBG_MON_A5 (MTK_PIN_NO(201) | 7) +- +-#define PINMUX_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +-#define PINMUX_GPIO202__FUNC_SCL5 (MTK_PIN_NO(202) | 1) +- +-#define PINMUX_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) +-#define PINMUX_GPIO203__FUNC_SDA5 (MTK_PIN_NO(203) | 1) +- +-#define PINMUX_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) +-#define PINMUX_GPIO204__FUNC_SCL0 (MTK_PIN_NO(204) | 1) +-#define PINMUX_GPIO204__FUNC_SPI7_A_CLK (MTK_PIN_NO(204) | 6) +-#define PINMUX_GPIO204__FUNC_DBG_MON_A2 (MTK_PIN_NO(204) | 7) +- +-#define PINMUX_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) +-#define PINMUX_GPIO205__FUNC_SDA0 (MTK_PIN_NO(205) | 1) +-#define PINMUX_GPIO205__FUNC_SPI7_A_CSB (MTK_PIN_NO(205) | 6) +-#define PINMUX_GPIO205__FUNC_DBG_MON_A3 (MTK_PIN_NO(205) | 7) +- +-#define PINMUX_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) +-#define PINMUX_GPIO206__FUNC_SRCLKENA0 (MTK_PIN_NO(206) | 1) +- +-#define PINMUX_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) +-#define PINMUX_GPIO207__FUNC_SRCLKENA1 (MTK_PIN_NO(207) | 1) +- +-#define PINMUX_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) +-#define PINMUX_GPIO208__FUNC_WATCHDOG (MTK_PIN_NO(208) | 1) +- +-#define PINMUX_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) +-#define PINMUX_GPIO209__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(209) | 1) +-#define PINMUX_GPIO209__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(209) | 2) +- +-#define PINMUX_GPIO210__FUNC_GPIO210 (MTK_PIN_NO(210) | 0) +-#define PINMUX_GPIO210__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(210) | 1) +- +-#define PINMUX_GPIO211__FUNC_GPIO211 (MTK_PIN_NO(211) | 0) +-#define PINMUX_GPIO211__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(211) | 1) +-#define PINMUX_GPIO211__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(211) | 2) +- +-#define PINMUX_GPIO212__FUNC_GPIO212 (MTK_PIN_NO(212) | 0) +-#define PINMUX_GPIO212__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(212) | 1) +- +-#define PINMUX_GPIO213__FUNC_GPIO213 (MTK_PIN_NO(213) | 0) +-#define PINMUX_GPIO213__FUNC_RTC32K_CK (MTK_PIN_NO(213) | 1) +- +-#define PINMUX_GPIO214__FUNC_GPIO214 (MTK_PIN_NO(214) | 0) +-#define PINMUX_GPIO214__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(214) | 1) +-#define PINMUX_GPIO214__FUNC_I2S1_MCK (MTK_PIN_NO(214) | 3) +-#define PINMUX_GPIO214__FUNC_I2S7_MCK (MTK_PIN_NO(214) | 4) +-#define PINMUX_GPIO214__FUNC_I2S9_MCK (MTK_PIN_NO(214) | 5) +- +-#define PINMUX_GPIO215__FUNC_GPIO215 (MTK_PIN_NO(215) | 0) +-#define PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(215) | 1) +-#define PINMUX_GPIO215__FUNC_I2S1_BCK (MTK_PIN_NO(215) | 3) +-#define PINMUX_GPIO215__FUNC_I2S7_BCK (MTK_PIN_NO(215) | 4) +-#define PINMUX_GPIO215__FUNC_I2S9_BCK (MTK_PIN_NO(215) | 5) +- +-#define PINMUX_GPIO216__FUNC_GPIO216 (MTK_PIN_NO(216) | 0) +-#define PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(216) | 1) +-#define PINMUX_GPIO216__FUNC_I2S1_LRCK (MTK_PIN_NO(216) | 3) +-#define PINMUX_GPIO216__FUNC_I2S7_LRCK (MTK_PIN_NO(216) | 4) +-#define PINMUX_GPIO216__FUNC_I2S9_LRCK (MTK_PIN_NO(216) | 5) +- +-#define PINMUX_GPIO217__FUNC_GPIO217 (MTK_PIN_NO(217) | 0) +-#define PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(217) | 1) +-#define PINMUX_GPIO217__FUNC_I2S1_DO (MTK_PIN_NO(217) | 3) +-#define PINMUX_GPIO217__FUNC_I2S7_DO (MTK_PIN_NO(217) | 4) +-#define PINMUX_GPIO217__FUNC_I2S9_DO (MTK_PIN_NO(217) | 5) +- +-#define PINMUX_GPIO218__FUNC_GPIO218 (MTK_PIN_NO(218) | 0) +-#define PINMUX_GPIO218__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(218) | 1) +-#define PINMUX_GPIO218__FUNC_VOW_DAT_MISO (MTK_PIN_NO(218) | 2) +-#define PINMUX_GPIO218__FUNC_I2S2_LRCK (MTK_PIN_NO(218) | 3) +-#define PINMUX_GPIO218__FUNC_I2S6_LRCK (MTK_PIN_NO(218) | 4) +-#define PINMUX_GPIO218__FUNC_I2S8_LRCK (MTK_PIN_NO(218) | 5) +- +-#define PINMUX_GPIO219__FUNC_GPIO219 (MTK_PIN_NO(219) | 0) +-#define PINMUX_GPIO219__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(219) | 1) +-#define PINMUX_GPIO219__FUNC_VOW_CLK_MISO (MTK_PIN_NO(219) | 2) +-#define PINMUX_GPIO219__FUNC_I2S2_DI (MTK_PIN_NO(219) | 3) +-#define PINMUX_GPIO219__FUNC_I2S6_DI (MTK_PIN_NO(219) | 4) +-#define PINMUX_GPIO219__FUNC_I2S8_DI (MTK_PIN_NO(219) | 5) +- +-#endif /* __MT8192_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt8195-pinfunc.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt8195-pinfunc.h +deleted file mode 100644 +index 666331bb9b40..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt8195-pinfunc.h ++++ /dev/null +@@ -1,962 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2020 MediaTek Inc. +- * Author: Zhiyong Tao +- */ +- +-#ifndef __MT8195_PINFUNC_H +-#define __MT8195_PINFUNC_H +- +-#include "mt65xx.h" +- +-#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +-#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 1) +-#define PINMUX_GPIO0__FUNC_MSDC2_CMD (MTK_PIN_NO(0) | 2) +-#define PINMUX_GPIO0__FUNC_TDMIN_MCK (MTK_PIN_NO(0) | 3) +-#define PINMUX_GPIO0__FUNC_CLKM0 (MTK_PIN_NO(0) | 4) +-#define PINMUX_GPIO0__FUNC_PERSTN_1 (MTK_PIN_NO(0) | 5) +-#define PINMUX_GPIO0__FUNC_IDDIG_1P (MTK_PIN_NO(0) | 6) +-#define PINMUX_GPIO0__FUNC_DMIC4_CLK (MTK_PIN_NO(0) | 7) +- +-#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +-#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 1) +-#define PINMUX_GPIO1__FUNC_MSDC2_CLK (MTK_PIN_NO(1) | 2) +-#define PINMUX_GPIO1__FUNC_TDMIN_DI (MTK_PIN_NO(1) | 3) +-#define PINMUX_GPIO1__FUNC_CLKM1 (MTK_PIN_NO(1) | 4) +-#define PINMUX_GPIO1__FUNC_CLKREQN_1 (MTK_PIN_NO(1) | 5) +-#define PINMUX_GPIO1__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(1) | 6) +-#define PINMUX_GPIO1__FUNC_DMIC4_DAT (MTK_PIN_NO(1) | 7) +- +-#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +-#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 1) +-#define PINMUX_GPIO2__FUNC_MSDC2_DAT3 (MTK_PIN_NO(2) | 2) +-#define PINMUX_GPIO2__FUNC_TDMIN_LRCK (MTK_PIN_NO(2) | 3) +-#define PINMUX_GPIO2__FUNC_CLKM2 (MTK_PIN_NO(2) | 4) +-#define PINMUX_GPIO2__FUNC_WAKEN_1 (MTK_PIN_NO(2) | 5) +-#define PINMUX_GPIO2__FUNC_DMIC2_CLK (MTK_PIN_NO(2) | 7) +- +-#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +-#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 1) +-#define PINMUX_GPIO3__FUNC_MSDC2_DAT0 (MTK_PIN_NO(3) | 2) +-#define PINMUX_GPIO3__FUNC_TDMIN_BCK (MTK_PIN_NO(3) | 3) +-#define PINMUX_GPIO3__FUNC_CLKM3 (MTK_PIN_NO(3) | 4) +-#define PINMUX_GPIO3__FUNC_DMIC2_DAT (MTK_PIN_NO(3) | 7) +- +-#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +-#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 1) +-#define PINMUX_GPIO4__FUNC_MSDC2_DAT2 (MTK_PIN_NO(4) | 2) +-#define PINMUX_GPIO4__FUNC_SPDIF_IN1 (MTK_PIN_NO(4) | 3) +-#define PINMUX_GPIO4__FUNC_UTXD3 (MTK_PIN_NO(4) | 4) +-#define PINMUX_GPIO4__FUNC_SDA2 (MTK_PIN_NO(4) | 5) +-#define PINMUX_GPIO4__FUNC_IDDIG_2P (MTK_PIN_NO(4) | 7) +- +-#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +-#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 1) +-#define PINMUX_GPIO5__FUNC_MSDC2_DAT1 (MTK_PIN_NO(5) | 2) +-#define PINMUX_GPIO5__FUNC_SPDIF_IN0 (MTK_PIN_NO(5) | 3) +-#define PINMUX_GPIO5__FUNC_URXD3 (MTK_PIN_NO(5) | 4) +-#define PINMUX_GPIO5__FUNC_SCL2 (MTK_PIN_NO(5) | 5) +-#define PINMUX_GPIO5__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(5) | 7) +- +-#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +-#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 1) +-#define PINMUX_GPIO6__FUNC_DP_TX_HPD (MTK_PIN_NO(6) | 2) +-#define PINMUX_GPIO6__FUNC_I2SO1_D4 (MTK_PIN_NO(6) | 3) +-#define PINMUX_GPIO6__FUNC_UTXD4 (MTK_PIN_NO(6) | 4) +-#define PINMUX_GPIO6__FUNC_CMVREF3 (MTK_PIN_NO(6) | 5) +-#define PINMUX_GPIO6__FUNC_DMIC3_CLK (MTK_PIN_NO(6) | 7) +- +-#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +-#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 1) +-#define PINMUX_GPIO7__FUNC_EDP_TX_HPD (MTK_PIN_NO(7) | 2) +-#define PINMUX_GPIO7__FUNC_I2SO1_D5 (MTK_PIN_NO(7) | 3) +-#define PINMUX_GPIO7__FUNC_URXD4 (MTK_PIN_NO(7) | 4) +-#define PINMUX_GPIO7__FUNC_CMVREF4 (MTK_PIN_NO(7) | 5) +-#define PINMUX_GPIO7__FUNC_DMIC3_DAT (MTK_PIN_NO(7) | 7) +- +-#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +-#define PINMUX_GPIO8__FUNC_SDA0 (MTK_PIN_NO(8) | 1) +-#define PINMUX_GPIO8__FUNC_PWM_0 (MTK_PIN_NO(8) | 2) +-#define PINMUX_GPIO8__FUNC_SPDIF_OUT (MTK_PIN_NO(8) | 4) +-#define PINMUX_GPIO8__FUNC_LVTS_FOUT (MTK_PIN_NO(8) | 6) +-#define PINMUX_GPIO8__FUNC_DBG_MON_A0 (MTK_PIN_NO(8) | 7) +- +-#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +-#define PINMUX_GPIO9__FUNC_SCL0 (MTK_PIN_NO(9) | 1) +-#define PINMUX_GPIO9__FUNC_PWM_1 (MTK_PIN_NO(9) | 2) +-#define PINMUX_GPIO9__FUNC_IR_IN (MTK_PIN_NO(9) | 4) +-#define PINMUX_GPIO9__FUNC_LVTS_SDO (MTK_PIN_NO(9) | 6) +-#define PINMUX_GPIO9__FUNC_DBG_MON_A1 (MTK_PIN_NO(9) | 7) +- +-#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +-#define PINMUX_GPIO10__FUNC_SDA1 (MTK_PIN_NO(10) | 1) +-#define PINMUX_GPIO10__FUNC_PWM_2 (MTK_PIN_NO(10) | 2) +-#define PINMUX_GPIO10__FUNC_ADSP_URXD0 (MTK_PIN_NO(10) | 3) +-#define PINMUX_GPIO10__FUNC_SPDIF_IN1 (MTK_PIN_NO(10) | 4) +-#define PINMUX_GPIO10__FUNC_LVTS_SCF (MTK_PIN_NO(10) | 6) +-#define PINMUX_GPIO10__FUNC_DBG_MON_A2 (MTK_PIN_NO(10) | 7) +- +-#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +-#define PINMUX_GPIO11__FUNC_SCL1 (MTK_PIN_NO(11) | 1) +-#define PINMUX_GPIO11__FUNC_PWM_3 (MTK_PIN_NO(11) | 2) +-#define PINMUX_GPIO11__FUNC_ADSP_UTXD0 (MTK_PIN_NO(11) | 3) +-#define PINMUX_GPIO11__FUNC_SPDIF_IN0 (MTK_PIN_NO(11) | 4) +-#define PINMUX_GPIO11__FUNC_LVTS_SCK (MTK_PIN_NO(11) | 6) +-#define PINMUX_GPIO11__FUNC_DBG_MON_A3 (MTK_PIN_NO(11) | 7) +- +-#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +-#define PINMUX_GPIO12__FUNC_SDA2 (MTK_PIN_NO(12) | 1) +-#define PINMUX_GPIO12__FUNC_DMIC3_DAT_R (MTK_PIN_NO(12) | 2) +-#define PINMUX_GPIO12__FUNC_I2SO1_D6 (MTK_PIN_NO(12) | 3) +-#define PINMUX_GPIO12__FUNC_LVTS_SDI (MTK_PIN_NO(12) | 6) +-#define PINMUX_GPIO12__FUNC_DBG_MON_A4 (MTK_PIN_NO(12) | 7) +- +-#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +-#define PINMUX_GPIO13__FUNC_SCL2 (MTK_PIN_NO(13) | 1) +-#define PINMUX_GPIO13__FUNC_DMIC4_DAT_R (MTK_PIN_NO(13) | 2) +-#define PINMUX_GPIO13__FUNC_I2SO1_D7 (MTK_PIN_NO(13) | 3) +-#define PINMUX_GPIO13__FUNC_DBG_MON_A5 (MTK_PIN_NO(13) | 7) +- +-#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +-#define PINMUX_GPIO14__FUNC_SDA3 (MTK_PIN_NO(14) | 1) +-#define PINMUX_GPIO14__FUNC_DMIC3_DAT (MTK_PIN_NO(14) | 2) +-#define PINMUX_GPIO14__FUNC_TDMIN_MCK (MTK_PIN_NO(14) | 3) +-#define PINMUX_GPIO14__FUNC_DBG_MON_A6 (MTK_PIN_NO(14) | 7) +- +-#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +-#define PINMUX_GPIO15__FUNC_SCL3 (MTK_PIN_NO(15) | 1) +-#define PINMUX_GPIO15__FUNC_DMIC3_CLK (MTK_PIN_NO(15) | 2) +-#define PINMUX_GPIO15__FUNC_TDMIN_DI (MTK_PIN_NO(15) | 3) +-#define PINMUX_GPIO15__FUNC_DBG_MON_A7 (MTK_PIN_NO(15) | 7) +- +-#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +-#define PINMUX_GPIO16__FUNC_SDA4 (MTK_PIN_NO(16) | 1) +-#define PINMUX_GPIO16__FUNC_DMIC4_DAT (MTK_PIN_NO(16) | 2) +-#define PINMUX_GPIO16__FUNC_TDMIN_LRCK (MTK_PIN_NO(16) | 3) +-#define PINMUX_GPIO16__FUNC_DBG_MON_A8 (MTK_PIN_NO(16) | 7) +- +-#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +-#define PINMUX_GPIO17__FUNC_SCL4 (MTK_PIN_NO(17) | 1) +-#define PINMUX_GPIO17__FUNC_DMIC4_CLK (MTK_PIN_NO(17) | 2) +-#define PINMUX_GPIO17__FUNC_TDMIN_BCK (MTK_PIN_NO(17) | 3) +-#define PINMUX_GPIO17__FUNC_DBG_MON_A9 (MTK_PIN_NO(17) | 7) +- +-#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +-#define PINMUX_GPIO18__FUNC_DP_TX_HPD (MTK_PIN_NO(18) | 1) +- +-#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +-#define PINMUX_GPIO19__FUNC_WAKEN (MTK_PIN_NO(19) | 1) +-#define PINMUX_GPIO19__FUNC_SCP_SDA1 (MTK_PIN_NO(19) | 2) +-#define PINMUX_GPIO19__FUNC_MD32_0_JTAG_TCK (MTK_PIN_NO(19) | 3) +-#define PINMUX_GPIO19__FUNC_ADSP_JTAG0_TCK (MTK_PIN_NO(19) | 4) +-#define PINMUX_GPIO19__FUNC_SDA6 (MTK_PIN_NO(19) | 5) +- +-#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +-#define PINMUX_GPIO20__FUNC_PERSTN (MTK_PIN_NO(20) | 1) +-#define PINMUX_GPIO20__FUNC_SCP_SCL1 (MTK_PIN_NO(20) | 2) +-#define PINMUX_GPIO20__FUNC_MD32_0_JTAG_TMS (MTK_PIN_NO(20) | 3) +-#define PINMUX_GPIO20__FUNC_ADSP_JTAG0_TMS (MTK_PIN_NO(20) | 4) +-#define PINMUX_GPIO20__FUNC_SCL6 (MTK_PIN_NO(20) | 5) +- +-#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +-#define PINMUX_GPIO21__FUNC_CLKREQN (MTK_PIN_NO(21) | 1) +-#define PINMUX_GPIO21__FUNC_MD32_0_JTAG_TDI (MTK_PIN_NO(21) | 3) +-#define PINMUX_GPIO21__FUNC_ADSP_JTAG0_TDI (MTK_PIN_NO(21) | 4) +-#define PINMUX_GPIO21__FUNC_SCP_SDA1 (MTK_PIN_NO(21) | 5) +- +-#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +-#define PINMUX_GPIO22__FUNC_CMMCLK0 (MTK_PIN_NO(22) | 1) +-#define PINMUX_GPIO22__FUNC_PERSTN_1 (MTK_PIN_NO(22) | 2) +-#define PINMUX_GPIO22__FUNC_SCP_SCL1 (MTK_PIN_NO(22) | 5) +-#define PINMUX_GPIO22__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(22) | 7) +- +-#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +-#define PINMUX_GPIO23__FUNC_CMMCLK1 (MTK_PIN_NO(23) | 1) +-#define PINMUX_GPIO23__FUNC_CLKREQN_1 (MTK_PIN_NO(23) | 2) +-#define PINMUX_GPIO23__FUNC_SDA4 (MTK_PIN_NO(23) | 3) +-#define PINMUX_GPIO23__FUNC_DMIC1_CLK (MTK_PIN_NO(23) | 4) +-#define PINMUX_GPIO23__FUNC_SCP_SDA0 (MTK_PIN_NO(23) | 5) +-#define PINMUX_GPIO23__FUNC_MD32_0_GPIO1 (MTK_PIN_NO(23) | 7) +- +-#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +-#define PINMUX_GPIO24__FUNC_CMMCLK2 (MTK_PIN_NO(24) | 1) +-#define PINMUX_GPIO24__FUNC_WAKEN_1 (MTK_PIN_NO(24) | 2) +-#define PINMUX_GPIO24__FUNC_SCL4 (MTK_PIN_NO(24) | 3) +-#define PINMUX_GPIO24__FUNC_DMIC1_DAT (MTK_PIN_NO(24) | 4) +-#define PINMUX_GPIO24__FUNC_SCP_SCL0 (MTK_PIN_NO(24) | 5) +-#define PINMUX_GPIO24__FUNC_LVTS_26M (MTK_PIN_NO(24) | 6) +-#define PINMUX_GPIO24__FUNC_MD32_0_GPIO2 (MTK_PIN_NO(24) | 7) +- +-#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +-#define PINMUX_GPIO25__FUNC_CMMRST (MTK_PIN_NO(25) | 1) +-#define PINMUX_GPIO25__FUNC_CMMCLK3 (MTK_PIN_NO(25) | 2) +-#define PINMUX_GPIO25__FUNC_SPDIF_OUT (MTK_PIN_NO(25) | 3) +-#define PINMUX_GPIO25__FUNC_SDA6 (MTK_PIN_NO(25) | 4) +-#define PINMUX_GPIO25__FUNC_ADSP_JTAG0_TRSTN (MTK_PIN_NO(25) | 5) +-#define PINMUX_GPIO25__FUNC_MD32_0_JTAG_TRST (MTK_PIN_NO(25) | 6) +- +-#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +-#define PINMUX_GPIO26__FUNC_CMMPDN (MTK_PIN_NO(26) | 1) +-#define PINMUX_GPIO26__FUNC_CMMCLK4 (MTK_PIN_NO(26) | 2) +-#define PINMUX_GPIO26__FUNC_IR_IN (MTK_PIN_NO(26) | 3) +-#define PINMUX_GPIO26__FUNC_SCL6 (MTK_PIN_NO(26) | 4) +-#define PINMUX_GPIO26__FUNC_ADSP_JTAG0_TDO (MTK_PIN_NO(26) | 5) +-#define PINMUX_GPIO26__FUNC_MD32_0_JTAG_TDO (MTK_PIN_NO(26) | 6) +- +-#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +-#define PINMUX_GPIO27__FUNC_HDMIRX20_HTPLG (MTK_PIN_NO(27) | 1) +-#define PINMUX_GPIO27__FUNC_CMFLASH0 (MTK_PIN_NO(27) | 2) +-#define PINMUX_GPIO27__FUNC_MD32_0_TXD (MTK_PIN_NO(27) | 3) +-#define PINMUX_GPIO27__FUNC_TP_UTXD2_AO (MTK_PIN_NO(27) | 4) +-#define PINMUX_GPIO27__FUNC_SCL7 (MTK_PIN_NO(27) | 5) +-#define PINMUX_GPIO27__FUNC_UCTS2 (MTK_PIN_NO(27) | 6) +-#define PINMUX_GPIO27__FUNC_DBG_MON_A18 (MTK_PIN_NO(27) | 7) +- +-#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +-#define PINMUX_GPIO28__FUNC_HDMIRX20_PWR5V (MTK_PIN_NO(28) | 1) +-#define PINMUX_GPIO28__FUNC_CMFLASH1 (MTK_PIN_NO(28) | 2) +-#define PINMUX_GPIO28__FUNC_MD32_0_RXD (MTK_PIN_NO(28) | 3) +-#define PINMUX_GPIO28__FUNC_TP_URXD2_AO (MTK_PIN_NO(28) | 4) +-#define PINMUX_GPIO28__FUNC_SDA7 (MTK_PIN_NO(28) | 5) +-#define PINMUX_GPIO28__FUNC_URTS2 (MTK_PIN_NO(28) | 6) +-#define PINMUX_GPIO28__FUNC_DBG_MON_A19 (MTK_PIN_NO(28) | 7) +- +-#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +-#define PINMUX_GPIO29__FUNC_HDMIRX20_SCL (MTK_PIN_NO(29) | 1) +-#define PINMUX_GPIO29__FUNC_CMFLASH2 (MTK_PIN_NO(29) | 2) +-#define PINMUX_GPIO29__FUNC_SCL5 (MTK_PIN_NO(29) | 3) +-#define PINMUX_GPIO29__FUNC_TP_URTS2_AO (MTK_PIN_NO(29) | 4) +-#define PINMUX_GPIO29__FUNC_UTXD2 (MTK_PIN_NO(29) | 6) +-#define PINMUX_GPIO29__FUNC_DBG_MON_A20 (MTK_PIN_NO(29) | 7) +- +-#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +-#define PINMUX_GPIO30__FUNC_HDMIRX20_SDA (MTK_PIN_NO(30) | 1) +-#define PINMUX_GPIO30__FUNC_CMFLASH3 (MTK_PIN_NO(30) | 2) +-#define PINMUX_GPIO30__FUNC_SDA5 (MTK_PIN_NO(30) | 3) +-#define PINMUX_GPIO30__FUNC_TP_UCTS2_AO (MTK_PIN_NO(30) | 4) +-#define PINMUX_GPIO30__FUNC_URXD2 (MTK_PIN_NO(30) | 6) +-#define PINMUX_GPIO30__FUNC_DBG_MON_A21 (MTK_PIN_NO(30) | 7) +- +-#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +-#define PINMUX_GPIO31__FUNC_HDMITX20_PWR5V (MTK_PIN_NO(31) | 1) +-#define PINMUX_GPIO31__FUNC_DMIC1_DAT_R (MTK_PIN_NO(31) | 2) +-#define PINMUX_GPIO31__FUNC_PERSTN (MTK_PIN_NO(31) | 3) +-#define PINMUX_GPIO31__FUNC_DBG_MON_A22 (MTK_PIN_NO(31) | 7) +- +-#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +-#define PINMUX_GPIO32__FUNC_HDMITX20_HTPLG (MTK_PIN_NO(32) | 1) +-#define PINMUX_GPIO32__FUNC_CLKREQN (MTK_PIN_NO(32) | 3) +-#define PINMUX_GPIO32__FUNC_DBG_MON_A23 (MTK_PIN_NO(32) | 7) +- +-#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +-#define PINMUX_GPIO33__FUNC_HDMITX20_CEC (MTK_PIN_NO(33) | 1) +-#define PINMUX_GPIO33__FUNC_CMVREF0 (MTK_PIN_NO(33) | 2) +-#define PINMUX_GPIO33__FUNC_WAKEN (MTK_PIN_NO(33) | 3) +- +-#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +-#define PINMUX_GPIO34__FUNC_HDMITX20_SCL (MTK_PIN_NO(34) | 1) +-#define PINMUX_GPIO34__FUNC_CMVREF1 (MTK_PIN_NO(34) | 2) +-#define PINMUX_GPIO34__FUNC_SCL7 (MTK_PIN_NO(34) | 3) +-#define PINMUX_GPIO34__FUNC_SCL6 (MTK_PIN_NO(34) | 4) +-#define PINMUX_GPIO34__FUNC_DBG_MON_A24 (MTK_PIN_NO(34) | 7) +- +-#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +-#define PINMUX_GPIO35__FUNC_HDMITX20_SDA (MTK_PIN_NO(35) | 1) +-#define PINMUX_GPIO35__FUNC_CMVREF2 (MTK_PIN_NO(35) | 2) +-#define PINMUX_GPIO35__FUNC_SDA7 (MTK_PIN_NO(35) | 3) +-#define PINMUX_GPIO35__FUNC_SDA6 (MTK_PIN_NO(35) | 4) +-#define PINMUX_GPIO35__FUNC_DBG_MON_A25 (MTK_PIN_NO(35) | 7) +- +-#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +-#define PINMUX_GPIO36__FUNC_RTC32K_CK (MTK_PIN_NO(36) | 1) +-#define PINMUX_GPIO36__FUNC_DBG_MON_A27 (MTK_PIN_NO(36) | 7) +- +-#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +-#define PINMUX_GPIO37__FUNC_WATCHDOG (MTK_PIN_NO(37) | 1) +-#define PINMUX_GPIO37__FUNC_DBG_MON_A28 (MTK_PIN_NO(37) | 7) +- +-#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +-#define PINMUX_GPIO38__FUNC_SRCLKENA0 (MTK_PIN_NO(38) | 1) +-#define PINMUX_GPIO38__FUNC_DBG_MON_A29 (MTK_PIN_NO(38) | 7) +- +-#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +-#define PINMUX_GPIO39__FUNC_SRCLKENA1 (MTK_PIN_NO(39) | 1) +-#define PINMUX_GPIO39__FUNC_DMIC2_DAT_R (MTK_PIN_NO(39) | 2) +-#define PINMUX_GPIO39__FUNC_DBG_MON_A30 (MTK_PIN_NO(39) | 7) +- +-#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +-#define PINMUX_GPIO40__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(40) | 1) +-#define PINMUX_GPIO40__FUNC_SPIM3_CSB (MTK_PIN_NO(40) | 3) +-#define PINMUX_GPIO40__FUNC_DBG_MON_A31 (MTK_PIN_NO(40) | 7) +- +-#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +-#define PINMUX_GPIO41__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(41) | 1) +-#define PINMUX_GPIO41__FUNC_SPIM3_CLK (MTK_PIN_NO(41) | 3) +-#define PINMUX_GPIO41__FUNC_DBG_MON_A32 (MTK_PIN_NO(41) | 7) +- +-#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +-#define PINMUX_GPIO42__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(42) | 1) +-#define PINMUX_GPIO42__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(42) | 2) +-#define PINMUX_GPIO42__FUNC_SPIM3_MO (MTK_PIN_NO(42) | 3) +-#define PINMUX_GPIO42__FUNC_DBG_MON_B0 (MTK_PIN_NO(42) | 7) +- +-#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +-#define PINMUX_GPIO43__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(43) | 1) +-#define PINMUX_GPIO43__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(43) | 2) +-#define PINMUX_GPIO43__FUNC_SPIM3_MI (MTK_PIN_NO(43) | 3) +-#define PINMUX_GPIO43__FUNC_DBG_MON_B1 (MTK_PIN_NO(43) | 7) +- +-#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +-#define PINMUX_GPIO44__FUNC_SPMI_M_SCL (MTK_PIN_NO(44) | 1) +-#define PINMUX_GPIO44__FUNC_I2SI00_DATA1 (MTK_PIN_NO(44) | 2) +-#define PINMUX_GPIO44__FUNC_SCL5 (MTK_PIN_NO(44) | 3) +-#define PINMUX_GPIO44__FUNC_UTXD5 (MTK_PIN_NO(44) | 4) +-#define PINMUX_GPIO44__FUNC_DBG_MON_B2 (MTK_PIN_NO(44) | 7) +- +-#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +-#define PINMUX_GPIO45__FUNC_SPMI_M_SDA (MTK_PIN_NO(45) | 1) +-#define PINMUX_GPIO45__FUNC_I2SI00_DATA2 (MTK_PIN_NO(45) | 2) +-#define PINMUX_GPIO45__FUNC_SDA5 (MTK_PIN_NO(45) | 3) +-#define PINMUX_GPIO45__FUNC_URXD5 (MTK_PIN_NO(45) | 4) +-#define PINMUX_GPIO45__FUNC_DBG_MON_B3 (MTK_PIN_NO(45) | 7) +- +-#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +-#define PINMUX_GPIO46__FUNC_I2SIN_MCK (MTK_PIN_NO(46) | 1) +-#define PINMUX_GPIO46__FUNC_I2SI00_DATA3 (MTK_PIN_NO(46) | 2) +-#define PINMUX_GPIO46__FUNC_SPLIN_MCK (MTK_PIN_NO(46) | 3) +-#define PINMUX_GPIO46__FUNC_DBG_MON_B4 (MTK_PIN_NO(46) | 7) +- +-#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +-#define PINMUX_GPIO47__FUNC_I2SIN_BCK (MTK_PIN_NO(47) | 1) +-#define PINMUX_GPIO47__FUNC_I2SIN0_BCK (MTK_PIN_NO(47) | 2) +-#define PINMUX_GPIO47__FUNC_SPLIN_LRCK (MTK_PIN_NO(47) | 3) +-#define PINMUX_GPIO47__FUNC_DBG_MON_B5 (MTK_PIN_NO(47) | 7) +- +-#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +-#define PINMUX_GPIO48__FUNC_I2SIN_WS (MTK_PIN_NO(48) | 1) +-#define PINMUX_GPIO48__FUNC_I2SIN0_LRCK (MTK_PIN_NO(48) | 2) +-#define PINMUX_GPIO48__FUNC_SPLIN_BCK (MTK_PIN_NO(48) | 3) +-#define PINMUX_GPIO48__FUNC_DBG_MON_B6 (MTK_PIN_NO(48) | 7) +- +-#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +-#define PINMUX_GPIO49__FUNC_I2SIN_D0 (MTK_PIN_NO(49) | 1) +-#define PINMUX_GPIO49__FUNC_I2SI00_DATA0 (MTK_PIN_NO(49) | 2) +-#define PINMUX_GPIO49__FUNC_SPLIN_D0 (MTK_PIN_NO(49) | 3) +-#define PINMUX_GPIO49__FUNC_DBG_MON_B7 (MTK_PIN_NO(49) | 7) +- +-#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +-#define PINMUX_GPIO50__FUNC_I2SO1_MCK (MTK_PIN_NO(50) | 1) +-#define PINMUX_GPIO50__FUNC_I2SI5_D0 (MTK_PIN_NO(50) | 2) +-#define PINMUX_GPIO50__FUNC_I2SO4_MCK (MTK_PIN_NO(50) | 4) +-#define PINMUX_GPIO50__FUNC_DBG_MON_B8 (MTK_PIN_NO(50) | 7) +- +-#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +-#define PINMUX_GPIO51__FUNC_I2SO1_BCK (MTK_PIN_NO(51) | 1) +-#define PINMUX_GPIO51__FUNC_I2SI5_BCK (MTK_PIN_NO(51) | 2) +-#define PINMUX_GPIO51__FUNC_DBG_MON_B9 (MTK_PIN_NO(51) | 7) +- +-#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +-#define PINMUX_GPIO52__FUNC_I2SO1_WS (MTK_PIN_NO(52) | 1) +-#define PINMUX_GPIO52__FUNC_I2SI5_WS (MTK_PIN_NO(52) | 2) +-#define PINMUX_GPIO52__FUNC_DBG_MON_B10 (MTK_PIN_NO(52) | 7) +- +-#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +-#define PINMUX_GPIO53__FUNC_I2SO1_D0 (MTK_PIN_NO(53) | 1) +-#define PINMUX_GPIO53__FUNC_I2SI5_MCK (MTK_PIN_NO(53) | 2) +-#define PINMUX_GPIO53__FUNC_DBG_MON_B11 (MTK_PIN_NO(53) | 7) +- +-#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +-#define PINMUX_GPIO54__FUNC_I2SO1_D1 (MTK_PIN_NO(54) | 1) +-#define PINMUX_GPIO54__FUNC_I2SI01_DATA1 (MTK_PIN_NO(54) | 2) +-#define PINMUX_GPIO54__FUNC_SPLIN_D1 (MTK_PIN_NO(54) | 3) +-#define PINMUX_GPIO54__FUNC_I2SO4_BCK (MTK_PIN_NO(54) | 4) +-#define PINMUX_GPIO54__FUNC_DBG_MON_B12 (MTK_PIN_NO(54) | 7) +- +-#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +-#define PINMUX_GPIO55__FUNC_I2SO1_D2 (MTK_PIN_NO(55) | 1) +-#define PINMUX_GPIO55__FUNC_I2SI01_DATA2 (MTK_PIN_NO(55) | 2) +-#define PINMUX_GPIO55__FUNC_SPLIN_D2 (MTK_PIN_NO(55) | 3) +-#define PINMUX_GPIO55__FUNC_I2SO4_WS (MTK_PIN_NO(55) | 4) +-#define PINMUX_GPIO55__FUNC_DBG_MON_B13 (MTK_PIN_NO(55) | 7) +- +-#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +-#define PINMUX_GPIO56__FUNC_I2SO1_D3 (MTK_PIN_NO(56) | 1) +-#define PINMUX_GPIO56__FUNC_I2SI01_DATA3 (MTK_PIN_NO(56) | 2) +-#define PINMUX_GPIO56__FUNC_SPLIN_D3 (MTK_PIN_NO(56) | 3) +-#define PINMUX_GPIO56__FUNC_I2SO4_D0 (MTK_PIN_NO(56) | 4) +-#define PINMUX_GPIO56__FUNC_DBG_MON_B14 (MTK_PIN_NO(56) | 7) +- +-#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +-#define PINMUX_GPIO57__FUNC_I2SO2_MCK (MTK_PIN_NO(57) | 1) +-#define PINMUX_GPIO57__FUNC_I2SO1_D12 (MTK_PIN_NO(57) | 2) +-#define PINMUX_GPIO57__FUNC_LCM1_RST (MTK_PIN_NO(57) | 3) +-#define PINMUX_GPIO57__FUNC_DBG_MON_B15 (MTK_PIN_NO(57) | 7) +- +-#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +-#define PINMUX_GPIO58__FUNC_I2SO2_BCK (MTK_PIN_NO(58) | 1) +-#define PINMUX_GPIO58__FUNC_I2SO1_D13 (MTK_PIN_NO(58) | 2) +-#define PINMUX_GPIO58__FUNC_I2SIN1_BCK (MTK_PIN_NO(58) | 3) +-#define PINMUX_GPIO58__FUNC_DBG_MON_B16 (MTK_PIN_NO(58) | 7) +- +-#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +-#define PINMUX_GPIO59__FUNC_I2SO2_WS (MTK_PIN_NO(59) | 1) +-#define PINMUX_GPIO59__FUNC_I2SO1_D14 (MTK_PIN_NO(59) | 2) +-#define PINMUX_GPIO59__FUNC_I2SIN1_LRCK (MTK_PIN_NO(59) | 3) +-#define PINMUX_GPIO59__FUNC_DBG_MON_B17 (MTK_PIN_NO(59) | 7) +- +-#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +-#define PINMUX_GPIO60__FUNC_I2SO2_D0 (MTK_PIN_NO(60) | 1) +-#define PINMUX_GPIO60__FUNC_I2SO1_D15 (MTK_PIN_NO(60) | 2) +-#define PINMUX_GPIO60__FUNC_I2SI01_DATA0 (MTK_PIN_NO(60) | 3) +-#define PINMUX_GPIO60__FUNC_DBG_MON_B18 (MTK_PIN_NO(60) | 7) +- +-#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +-#define PINMUX_GPIO61__FUNC_DMIC1_CLK (MTK_PIN_NO(61) | 1) +-#define PINMUX_GPIO61__FUNC_I2SO2_BCK (MTK_PIN_NO(61) | 2) +-#define PINMUX_GPIO61__FUNC_SCP_SPI2_CK (MTK_PIN_NO(61) | 3) +-#define PINMUX_GPIO61__FUNC_DBG_MON_B19 (MTK_PIN_NO(61) | 7) +- +-#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +-#define PINMUX_GPIO62__FUNC_DMIC1_DAT (MTK_PIN_NO(62) | 1) +-#define PINMUX_GPIO62__FUNC_I2SO2_WS (MTK_PIN_NO(62) | 2) +-#define PINMUX_GPIO62__FUNC_SCP_SPI2_MI (MTK_PIN_NO(62) | 3) +-#define PINMUX_GPIO62__FUNC_DBG_MON_B20 (MTK_PIN_NO(62) | 7) +- +-#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +-#define PINMUX_GPIO63__FUNC_DMIC2_CLK (MTK_PIN_NO(63) | 1) +-#define PINMUX_GPIO63__FUNC_VBUSVALID (MTK_PIN_NO(63) | 2) +-#define PINMUX_GPIO63__FUNC_SCP_SPI2_MO (MTK_PIN_NO(63) | 3) +-#define PINMUX_GPIO63__FUNC_SCP_SCL2 (MTK_PIN_NO(63) | 4) +-#define PINMUX_GPIO63__FUNC_SCP_JTAG1_TDO (MTK_PIN_NO(63) | 5) +-#define PINMUX_GPIO63__FUNC_JTDO_SEL1 (MTK_PIN_NO(63) | 6) +-#define PINMUX_GPIO63__FUNC_DBG_MON_B21 (MTK_PIN_NO(63) | 7) +- +-#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +-#define PINMUX_GPIO64__FUNC_DMIC2_DAT (MTK_PIN_NO(64) | 1) +-#define PINMUX_GPIO64__FUNC_VBUSVALID_1P (MTK_PIN_NO(64) | 2) +-#define PINMUX_GPIO64__FUNC_SCP_SPI2_CS (MTK_PIN_NO(64) | 3) +-#define PINMUX_GPIO64__FUNC_SCP_SDA2 (MTK_PIN_NO(64) | 4) +-#define PINMUX_GPIO64__FUNC_DBG_MON_B22 (MTK_PIN_NO(64) | 7) +- +-#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +-#define PINMUX_GPIO65__FUNC_PCM_DO (MTK_PIN_NO(65) | 1) +-#define PINMUX_GPIO65__FUNC_AUXIF_ST0 (MTK_PIN_NO(65) | 2) +-#define PINMUX_GPIO65__FUNC_UCTS2 (MTK_PIN_NO(65) | 3) +-#define PINMUX_GPIO65__FUNC_SCP_JTAG1_TMS (MTK_PIN_NO(65) | 5) +-#define PINMUX_GPIO65__FUNC_JTMS_SEL1 (MTK_PIN_NO(65) | 6) +-#define PINMUX_GPIO65__FUNC_DBG_MON_B23 (MTK_PIN_NO(65) | 7) +- +-#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +-#define PINMUX_GPIO66__FUNC_PCM_CLK (MTK_PIN_NO(66) | 1) +-#define PINMUX_GPIO66__FUNC_AUXIF_CLK0 (MTK_PIN_NO(66) | 2) +-#define PINMUX_GPIO66__FUNC_URTS2 (MTK_PIN_NO(66) | 3) +-#define PINMUX_GPIO66__FUNC_SCP_JTAG1_TCK (MTK_PIN_NO(66) | 5) +-#define PINMUX_GPIO66__FUNC_JTCK_SEL1 (MTK_PIN_NO(66) | 6) +-#define PINMUX_GPIO66__FUNC_DBG_MON_B24 (MTK_PIN_NO(66) | 7) +- +-#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +-#define PINMUX_GPIO67__FUNC_PCM_DI (MTK_PIN_NO(67) | 1) +-#define PINMUX_GPIO67__FUNC_AUXIF_ST1 (MTK_PIN_NO(67) | 2) +-#define PINMUX_GPIO67__FUNC_UTXD2 (MTK_PIN_NO(67) | 3) +-#define PINMUX_GPIO67__FUNC_SCP_JTAG1_TRSTN (MTK_PIN_NO(67) | 5) +-#define PINMUX_GPIO67__FUNC_JTRSTn_SEL1 (MTK_PIN_NO(67) | 6) +-#define PINMUX_GPIO67__FUNC_DBG_MON_B25 (MTK_PIN_NO(67) | 7) +- +-#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +-#define PINMUX_GPIO68__FUNC_PCM_SYNC (MTK_PIN_NO(68) | 1) +-#define PINMUX_GPIO68__FUNC_AUXIF_CLK1 (MTK_PIN_NO(68) | 2) +-#define PINMUX_GPIO68__FUNC_URXD2 (MTK_PIN_NO(68) | 3) +-#define PINMUX_GPIO68__FUNC_SCP_JTAG1_TDI (MTK_PIN_NO(68) | 5) +-#define PINMUX_GPIO68__FUNC_JTDI_SEL1 (MTK_PIN_NO(68) | 6) +-#define PINMUX_GPIO68__FUNC_DBG_MON_B26 (MTK_PIN_NO(68) | 7) +- +-#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +-#define PINMUX_GPIO69__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(69) | 1) +-#define PINMUX_GPIO69__FUNC_I2SIN2_BCK (MTK_PIN_NO(69) | 2) +-#define PINMUX_GPIO69__FUNC_PWM_0 (MTK_PIN_NO(69) | 3) +-#define PINMUX_GPIO69__FUNC_WAKEN (MTK_PIN_NO(69) | 4) +-#define PINMUX_GPIO69__FUNC_DBG_MON_B27 (MTK_PIN_NO(69) | 7) +- +-#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +-#define PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(70) | 1) +-#define PINMUX_GPIO70__FUNC_I2SIN2_LRCK (MTK_PIN_NO(70) | 2) +-#define PINMUX_GPIO70__FUNC_PWM_1 (MTK_PIN_NO(70) | 3) +-#define PINMUX_GPIO70__FUNC_PERSTN (MTK_PIN_NO(70) | 4) +-#define PINMUX_GPIO70__FUNC_DBG_MON_B28 (MTK_PIN_NO(70) | 7) +- +-#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +-#define PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(71) | 1) +-#define PINMUX_GPIO71__FUNC_IDDIG_2P (MTK_PIN_NO(71) | 2) +-#define PINMUX_GPIO71__FUNC_PWM_2 (MTK_PIN_NO(71) | 3) +-#define PINMUX_GPIO71__FUNC_CLKREQN (MTK_PIN_NO(71) | 4) +-#define PINMUX_GPIO71__FUNC_DBG_MON_B29 (MTK_PIN_NO(71) | 7) +- +-#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +-#define PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(72) | 1) +-#define PINMUX_GPIO72__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(72) | 2) +-#define PINMUX_GPIO72__FUNC_PWM_3 (MTK_PIN_NO(72) | 3) +-#define PINMUX_GPIO72__FUNC_PERSTN_1 (MTK_PIN_NO(72) | 4) +-#define PINMUX_GPIO72__FUNC_DBG_MON_B30 (MTK_PIN_NO(72) | 7) +- +-#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +-#define PINMUX_GPIO73__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(73) | 1) +-#define PINMUX_GPIO73__FUNC_I2SI02_DATA0 (MTK_PIN_NO(73) | 2) +-#define PINMUX_GPIO73__FUNC_CLKREQN_1 (MTK_PIN_NO(73) | 4) +-#define PINMUX_GPIO73__FUNC_VOW_DAT_MISO (MTK_PIN_NO(73) | 5) +-#define PINMUX_GPIO73__FUNC_DBG_MON_B31 (MTK_PIN_NO(73) | 7) +- +-#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +-#define PINMUX_GPIO74__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(74) | 1) +-#define PINMUX_GPIO74__FUNC_I2SI02_DATA1 (MTK_PIN_NO(74) | 2) +-#define PINMUX_GPIO74__FUNC_WAKEN_1 (MTK_PIN_NO(74) | 4) +-#define PINMUX_GPIO74__FUNC_VOW_CLK_MISO (MTK_PIN_NO(74) | 5) +-#define PINMUX_GPIO74__FUNC_DBG_MON_B32 (MTK_PIN_NO(74) | 7) +- +-#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +-#define PINMUX_GPIO75__FUNC_AUD_DAT_MISO2 (MTK_PIN_NO(75) | 1) +-#define PINMUX_GPIO75__FUNC_I2SI02_DATA2 (MTK_PIN_NO(75) | 2) +- +-#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +-#define PINMUX_GPIO76__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(76) | 1) +-#define PINMUX_GPIO76__FUNC_I2SI02_DATA3 (MTK_PIN_NO(76) | 2) +-#define PINMUX_GPIO76__FUNC_DBG_MON_A26 (MTK_PIN_NO(76) | 7) +- +-#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +-#define PINMUX_GPIO77__FUNC_DGI_D0 (MTK_PIN_NO(77) | 1) +-#define PINMUX_GPIO77__FUNC_DPI_D0 (MTK_PIN_NO(77) | 2) +-#define PINMUX_GPIO77__FUNC_I2SI4_MCK (MTK_PIN_NO(77) | 3) +-#define PINMUX_GPIO77__FUNC_SPIM4_CLK (MTK_PIN_NO(77) | 4) +-#define PINMUX_GPIO77__FUNC_GBE_TXD3 (MTK_PIN_NO(77) | 5) +-#define PINMUX_GPIO77__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(77) | 6) +- +-#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +-#define PINMUX_GPIO78__FUNC_DGI_D1 (MTK_PIN_NO(78) | 1) +-#define PINMUX_GPIO78__FUNC_DPI_D1 (MTK_PIN_NO(78) | 2) +-#define PINMUX_GPIO78__FUNC_I2SI4_BCK (MTK_PIN_NO(78) | 3) +-#define PINMUX_GPIO78__FUNC_SPIM4_MO (MTK_PIN_NO(78) | 4) +-#define PINMUX_GPIO78__FUNC_GBE_TXD2 (MTK_PIN_NO(78) | 5) +-#define PINMUX_GPIO78__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(78) | 6) +- +-#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +-#define PINMUX_GPIO79__FUNC_DGI_D2 (MTK_PIN_NO(79) | 1) +-#define PINMUX_GPIO79__FUNC_DPI_D2 (MTK_PIN_NO(79) | 2) +-#define PINMUX_GPIO79__FUNC_I2SI4_WS (MTK_PIN_NO(79) | 3) +-#define PINMUX_GPIO79__FUNC_SPIM4_CSB (MTK_PIN_NO(79) | 4) +-#define PINMUX_GPIO79__FUNC_GBE_TXD1 (MTK_PIN_NO(79) | 5) +-#define PINMUX_GPIO79__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(79) | 6) +- +-#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +-#define PINMUX_GPIO80__FUNC_DGI_D3 (MTK_PIN_NO(80) | 1) +-#define PINMUX_GPIO80__FUNC_DPI_D3 (MTK_PIN_NO(80) | 2) +-#define PINMUX_GPIO80__FUNC_I2SI4_D0 (MTK_PIN_NO(80) | 3) +-#define PINMUX_GPIO80__FUNC_SPIM4_MI (MTK_PIN_NO(80) | 4) +-#define PINMUX_GPIO80__FUNC_GBE_TXD0 (MTK_PIN_NO(80) | 5) +-#define PINMUX_GPIO80__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(80) | 6) +- +-#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +-#define PINMUX_GPIO81__FUNC_DGI_D4 (MTK_PIN_NO(81) | 1) +-#define PINMUX_GPIO81__FUNC_DPI_D4 (MTK_PIN_NO(81) | 2) +-#define PINMUX_GPIO81__FUNC_I2SI5_MCK (MTK_PIN_NO(81) | 3) +-#define PINMUX_GPIO81__FUNC_SPIM5_CLK (MTK_PIN_NO(81) | 4) +-#define PINMUX_GPIO81__FUNC_GBE_RXD3 (MTK_PIN_NO(81) | 5) +-#define PINMUX_GPIO81__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(81) | 6) +- +-#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +-#define PINMUX_GPIO82__FUNC_DGI_D5 (MTK_PIN_NO(82) | 1) +-#define PINMUX_GPIO82__FUNC_DPI_D5 (MTK_PIN_NO(82) | 2) +-#define PINMUX_GPIO82__FUNC_I2SI5_BCK (MTK_PIN_NO(82) | 3) +-#define PINMUX_GPIO82__FUNC_SPIM5_MO (MTK_PIN_NO(82) | 4) +-#define PINMUX_GPIO82__FUNC_GBE_RXD2 (MTK_PIN_NO(82) | 5) +-#define PINMUX_GPIO82__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(82) | 6) +- +-#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +-#define PINMUX_GPIO83__FUNC_DGI_D6 (MTK_PIN_NO(83) | 1) +-#define PINMUX_GPIO83__FUNC_DPI_D6 (MTK_PIN_NO(83) | 2) +-#define PINMUX_GPIO83__FUNC_I2SI5_WS (MTK_PIN_NO(83) | 3) +-#define PINMUX_GPIO83__FUNC_SPIM5_CSB (MTK_PIN_NO(83) | 4) +-#define PINMUX_GPIO83__FUNC_GBE_RXD1 (MTK_PIN_NO(83) | 5) +-#define PINMUX_GPIO83__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(83) | 6) +- +-#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +-#define PINMUX_GPIO84__FUNC_DGI_D7 (MTK_PIN_NO(84) | 1) +-#define PINMUX_GPIO84__FUNC_DPI_D7 (MTK_PIN_NO(84) | 2) +-#define PINMUX_GPIO84__FUNC_I2SI5_D0 (MTK_PIN_NO(84) | 3) +-#define PINMUX_GPIO84__FUNC_SPIM5_MI (MTK_PIN_NO(84) | 4) +-#define PINMUX_GPIO84__FUNC_GBE_RXD0 (MTK_PIN_NO(84) | 5) +-#define PINMUX_GPIO84__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(84) | 6) +- +-#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +-#define PINMUX_GPIO85__FUNC_DGI_D8 (MTK_PIN_NO(85) | 1) +-#define PINMUX_GPIO85__FUNC_DPI_D8 (MTK_PIN_NO(85) | 2) +-#define PINMUX_GPIO85__FUNC_I2SO4_MCK (MTK_PIN_NO(85) | 3) +-#define PINMUX_GPIO85__FUNC_SCP_SPI1_B_CK (MTK_PIN_NO(85) | 4) +-#define PINMUX_GPIO85__FUNC_GBE_TXC (MTK_PIN_NO(85) | 5) +-#define PINMUX_GPIO85__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(85) | 6) +- +-#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +-#define PINMUX_GPIO86__FUNC_DGI_D9 (MTK_PIN_NO(86) | 1) +-#define PINMUX_GPIO86__FUNC_DPI_D9 (MTK_PIN_NO(86) | 2) +-#define PINMUX_GPIO86__FUNC_I2SO4_BCK (MTK_PIN_NO(86) | 3) +-#define PINMUX_GPIO86__FUNC_SCP_SPI1_B_MI (MTK_PIN_NO(86) | 4) +-#define PINMUX_GPIO86__FUNC_GBE_RXC (MTK_PIN_NO(86) | 5) +-#define PINMUX_GPIO86__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(86) | 6) +- +-#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +-#define PINMUX_GPIO87__FUNC_DGI_D10 (MTK_PIN_NO(87) | 1) +-#define PINMUX_GPIO87__FUNC_DPI_D10 (MTK_PIN_NO(87) | 2) +-#define PINMUX_GPIO87__FUNC_I2SO4_WS (MTK_PIN_NO(87) | 3) +-#define PINMUX_GPIO87__FUNC_SCP_SPI1_B_CS (MTK_PIN_NO(87) | 4) +-#define PINMUX_GPIO87__FUNC_GBE_RXDV (MTK_PIN_NO(87) | 5) +-#define PINMUX_GPIO87__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(87) | 6) +- +-#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +-#define PINMUX_GPIO88__FUNC_DGI_D11 (MTK_PIN_NO(88) | 1) +-#define PINMUX_GPIO88__FUNC_DPI_D11 (MTK_PIN_NO(88) | 2) +-#define PINMUX_GPIO88__FUNC_I2SO4_D0 (MTK_PIN_NO(88) | 3) +-#define PINMUX_GPIO88__FUNC_SCP_SPI1_B_MO (MTK_PIN_NO(88) | 4) +-#define PINMUX_GPIO88__FUNC_GBE_TXEN (MTK_PIN_NO(88) | 5) +-#define PINMUX_GPIO88__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(88) | 6) +- +-#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +-#define PINMUX_GPIO89__FUNC_DGI_D12 (MTK_PIN_NO(89) | 1) +-#define PINMUX_GPIO89__FUNC_DPI_D12 (MTK_PIN_NO(89) | 2) +-#define PINMUX_GPIO89__FUNC_MSDC2_CMD_A (MTK_PIN_NO(89) | 3) +-#define PINMUX_GPIO89__FUNC_I2SO5_BCK (MTK_PIN_NO(89) | 4) +-#define PINMUX_GPIO89__FUNC_GBE_MDC (MTK_PIN_NO(89) | 5) +-#define PINMUX_GPIO89__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(89) | 6) +- +-#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +-#define PINMUX_GPIO90__FUNC_DGI_D13 (MTK_PIN_NO(90) | 1) +-#define PINMUX_GPIO90__FUNC_DPI_D13 (MTK_PIN_NO(90) | 2) +-#define PINMUX_GPIO90__FUNC_MSDC2_CLK_A (MTK_PIN_NO(90) | 3) +-#define PINMUX_GPIO90__FUNC_I2SO5_WS (MTK_PIN_NO(90) | 4) +-#define PINMUX_GPIO90__FUNC_GBE_MDIO (MTK_PIN_NO(90) | 5) +-#define PINMUX_GPIO90__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(90) | 6) +- +-#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +-#define PINMUX_GPIO91__FUNC_DGI_D14 (MTK_PIN_NO(91) | 1) +-#define PINMUX_GPIO91__FUNC_DPI_D14 (MTK_PIN_NO(91) | 2) +-#define PINMUX_GPIO91__FUNC_MSDC2_DAT3_A (MTK_PIN_NO(91) | 3) +-#define PINMUX_GPIO91__FUNC_I2SO5_D0 (MTK_PIN_NO(91) | 4) +-#define PINMUX_GPIO91__FUNC_GBE_TXER (MTK_PIN_NO(91) | 5) +-#define PINMUX_GPIO91__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(91) | 6) +- +-#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +-#define PINMUX_GPIO92__FUNC_DGI_D15 (MTK_PIN_NO(92) | 1) +-#define PINMUX_GPIO92__FUNC_DPI_D15 (MTK_PIN_NO(92) | 2) +-#define PINMUX_GPIO92__FUNC_MSDC2_DAT0_A (MTK_PIN_NO(92) | 3) +-#define PINMUX_GPIO92__FUNC_I2SO2_D1 (MTK_PIN_NO(92) | 4) +-#define PINMUX_GPIO92__FUNC_GBE_RXER (MTK_PIN_NO(92) | 5) +-#define PINMUX_GPIO92__FUNC_CCU0_JTAG_TDO (MTK_PIN_NO(92) | 6) +- +-#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +-#define PINMUX_GPIO93__FUNC_DGI_HSYNC (MTK_PIN_NO(93) | 1) +-#define PINMUX_GPIO93__FUNC_DPI_HSYNC (MTK_PIN_NO(93) | 2) +-#define PINMUX_GPIO93__FUNC_MSDC2_DAT2_A (MTK_PIN_NO(93) | 3) +-#define PINMUX_GPIO93__FUNC_I2SO2_D2 (MTK_PIN_NO(93) | 4) +-#define PINMUX_GPIO93__FUNC_GBE_COL (MTK_PIN_NO(93) | 5) +-#define PINMUX_GPIO93__FUNC_CCU0_JTAG_TMS (MTK_PIN_NO(93) | 6) +- +-#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +-#define PINMUX_GPIO94__FUNC_DGI_VSYNC (MTK_PIN_NO(94) | 1) +-#define PINMUX_GPIO94__FUNC_DPI_VSYNC (MTK_PIN_NO(94) | 2) +-#define PINMUX_GPIO94__FUNC_MSDC2_DAT1_A (MTK_PIN_NO(94) | 3) +-#define PINMUX_GPIO94__FUNC_I2SO2_D3 (MTK_PIN_NO(94) | 4) +-#define PINMUX_GPIO94__FUNC_GBE_INTR (MTK_PIN_NO(94) | 5) +-#define PINMUX_GPIO94__FUNC_CCU0_JTAG_TDI (MTK_PIN_NO(94) | 6) +- +-#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +-#define PINMUX_GPIO95__FUNC_DGI_DE (MTK_PIN_NO(95) | 1) +-#define PINMUX_GPIO95__FUNC_DPI_DE (MTK_PIN_NO(95) | 2) +-#define PINMUX_GPIO95__FUNC_UTXD2 (MTK_PIN_NO(95) | 3) +-#define PINMUX_GPIO95__FUNC_I2SIN_D1 (MTK_PIN_NO(95) | 5) +-#define PINMUX_GPIO95__FUNC_CCU0_JTAG_TCK (MTK_PIN_NO(95) | 6) +- +-#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +-#define PINMUX_GPIO96__FUNC_DGI_CK (MTK_PIN_NO(96) | 1) +-#define PINMUX_GPIO96__FUNC_DPI_CK (MTK_PIN_NO(96) | 2) +-#define PINMUX_GPIO96__FUNC_URXD2 (MTK_PIN_NO(96) | 3) +-#define PINMUX_GPIO96__FUNC_I2SO5_MCK (MTK_PIN_NO(96) | 4) +-#define PINMUX_GPIO96__FUNC_I2SIN_D2 (MTK_PIN_NO(96) | 5) +-#define PINMUX_GPIO96__FUNC_CCU0_JTAG_TRST (MTK_PIN_NO(96) | 6) +- +-#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +-#define PINMUX_GPIO97__FUNC_DISP_PWM0 (MTK_PIN_NO(97) | 1) +-#define PINMUX_GPIO97__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(97) | 2) +- +-#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +-#define PINMUX_GPIO98__FUNC_UTXD0 (MTK_PIN_NO(98) | 1) +- +-#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +-#define PINMUX_GPIO99__FUNC_URXD0 (MTK_PIN_NO(99) | 1) +- +-#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +-#define PINMUX_GPIO100__FUNC_URTS1 (MTK_PIN_NO(100) | 1) +-#define PINMUX_GPIO100__FUNC_DSI_TE (MTK_PIN_NO(100) | 2) +-#define PINMUX_GPIO100__FUNC_I2SO1_D8 (MTK_PIN_NO(100) | 3) +-#define PINMUX_GPIO100__FUNC_KPROW2 (MTK_PIN_NO(100) | 4) +-#define PINMUX_GPIO100__FUNC_PWM_0 (MTK_PIN_NO(100) | 5) +-#define PINMUX_GPIO100__FUNC_TP_URTS1_AO (MTK_PIN_NO(100) | 6) +-#define PINMUX_GPIO100__FUNC_I2SIN_D0 (MTK_PIN_NO(100) | 7) +- +-#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +-#define PINMUX_GPIO101__FUNC_UCTS1 (MTK_PIN_NO(101) | 1) +-#define PINMUX_GPIO101__FUNC_DSI1_TE (MTK_PIN_NO(101) | 2) +-#define PINMUX_GPIO101__FUNC_I2SO1_D9 (MTK_PIN_NO(101) | 3) +-#define PINMUX_GPIO101__FUNC_KPCOL2 (MTK_PIN_NO(101) | 4) +-#define PINMUX_GPIO101__FUNC_PWM_1 (MTK_PIN_NO(101) | 5) +-#define PINMUX_GPIO101__FUNC_TP_UCTS1_AO (MTK_PIN_NO(101) | 6) +-#define PINMUX_GPIO101__FUNC_I2SIN_D1 (MTK_PIN_NO(101) | 7) +- +-#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +-#define PINMUX_GPIO102__FUNC_UTXD1 (MTK_PIN_NO(102) | 1) +-#define PINMUX_GPIO102__FUNC_VBUSVALID_2P (MTK_PIN_NO(102) | 2) +-#define PINMUX_GPIO102__FUNC_I2SO1_D10 (MTK_PIN_NO(102) | 3) +-#define PINMUX_GPIO102__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(102) | 4) +-#define PINMUX_GPIO102__FUNC_TP_UTXD1_AO (MTK_PIN_NO(102) | 5) +-#define PINMUX_GPIO102__FUNC_MD32_1_TXD (MTK_PIN_NO(102) | 6) +-#define PINMUX_GPIO102__FUNC_I2SIN_D2 (MTK_PIN_NO(102) | 7) +- +-#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +-#define PINMUX_GPIO103__FUNC_URXD1 (MTK_PIN_NO(103) | 1) +-#define PINMUX_GPIO103__FUNC_VBUSVALID_3P (MTK_PIN_NO(103) | 2) +-#define PINMUX_GPIO103__FUNC_I2SO1_D11 (MTK_PIN_NO(103) | 3) +-#define PINMUX_GPIO103__FUNC_SSPM_URXD_AO (MTK_PIN_NO(103) | 4) +-#define PINMUX_GPIO103__FUNC_TP_URXD1_AO (MTK_PIN_NO(103) | 5) +-#define PINMUX_GPIO103__FUNC_MD32_1_RXD (MTK_PIN_NO(103) | 6) +-#define PINMUX_GPIO103__FUNC_I2SIN_D3 (MTK_PIN_NO(103) | 7) +- +-#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +-#define PINMUX_GPIO104__FUNC_KPROW0 (MTK_PIN_NO(104) | 1) +-#define PINMUX_GPIO104__FUNC_DISP_PWM1 (MTK_PIN_NO(104) | 2) +- +-#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +-#define PINMUX_GPIO105__FUNC_KPROW1 (MTK_PIN_NO(105) | 1) +-#define PINMUX_GPIO105__FUNC_EDP_TX_HPD (MTK_PIN_NO(105) | 2) +-#define PINMUX_GPIO105__FUNC_PWM_2 (MTK_PIN_NO(105) | 3) +- +-#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +-#define PINMUX_GPIO106__FUNC_KPCOL0 (MTK_PIN_NO(106) | 1) +- +-#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +-#define PINMUX_GPIO107__FUNC_KPCOL1 (MTK_PIN_NO(107) | 1) +-#define PINMUX_GPIO107__FUNC_DSI1_TE (MTK_PIN_NO(107) | 2) +-#define PINMUX_GPIO107__FUNC_PWM_3 (MTK_PIN_NO(107) | 3) +-#define PINMUX_GPIO107__FUNC_SCP_SCL3 (MTK_PIN_NO(107) | 4) +-#define PINMUX_GPIO107__FUNC_I2SIN_MCK (MTK_PIN_NO(107) | 5) +- +-#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +-#define PINMUX_GPIO108__FUNC_LCM_RST (MTK_PIN_NO(108) | 1) +-#define PINMUX_GPIO108__FUNC_KPCOL1 (MTK_PIN_NO(108) | 2) +-#define PINMUX_GPIO108__FUNC_SCP_SDA3 (MTK_PIN_NO(108) | 4) +-#define PINMUX_GPIO108__FUNC_I2SIN_BCK (MTK_PIN_NO(108) | 5) +- +-#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +-#define PINMUX_GPIO109__FUNC_DSI_TE (MTK_PIN_NO(109) | 1) +-#define PINMUX_GPIO109__FUNC_I2SIN_D3 (MTK_PIN_NO(109) | 2) +-#define PINMUX_GPIO109__FUNC_I2SIN_WS (MTK_PIN_NO(109) | 5) +- +-#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +-#define PINMUX_GPIO110__FUNC_MSDC1_CMD (MTK_PIN_NO(110) | 1) +-#define PINMUX_GPIO110__FUNC_JTMS_SEL3 (MTK_PIN_NO(110) | 2) +-#define PINMUX_GPIO110__FUNC_UDI_TMS (MTK_PIN_NO(110) | 3) +-#define PINMUX_GPIO110__FUNC_CCU1_JTAG_TMS (MTK_PIN_NO(110) | 5) +-#define PINMUX_GPIO110__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(110) | 6) +- +-#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +-#define PINMUX_GPIO111__FUNC_MSDC1_CLK (MTK_PIN_NO(111) | 1) +-#define PINMUX_GPIO111__FUNC_JTCK_SEL3 (MTK_PIN_NO(111) | 2) +-#define PINMUX_GPIO111__FUNC_UDI_TCK (MTK_PIN_NO(111) | 3) +-#define PINMUX_GPIO111__FUNC_CCU1_JTAG_TCK (MTK_PIN_NO(111) | 5) +-#define PINMUX_GPIO111__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(111) | 6) +- +-#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +-#define PINMUX_GPIO112__FUNC_MSDC1_DAT0 (MTK_PIN_NO(112) | 1) +-#define PINMUX_GPIO112__FUNC_JTDI_SEL3 (MTK_PIN_NO(112) | 2) +-#define PINMUX_GPIO112__FUNC_UDI_TDI (MTK_PIN_NO(112) | 3) +-#define PINMUX_GPIO112__FUNC_I2SO2_D0 (MTK_PIN_NO(112) | 4) +-#define PINMUX_GPIO112__FUNC_CCU1_JTAG_TDI (MTK_PIN_NO(112) | 5) +-#define PINMUX_GPIO112__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(112) | 6) +- +-#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +-#define PINMUX_GPIO113__FUNC_MSDC1_DAT1 (MTK_PIN_NO(113) | 1) +-#define PINMUX_GPIO113__FUNC_JTDO_SEL3 (MTK_PIN_NO(113) | 2) +-#define PINMUX_GPIO113__FUNC_UDI_TDO (MTK_PIN_NO(113) | 3) +-#define PINMUX_GPIO113__FUNC_I2SO2_D1 (MTK_PIN_NO(113) | 4) +-#define PINMUX_GPIO113__FUNC_CCU1_JTAG_TDO (MTK_PIN_NO(113) | 5) +-#define PINMUX_GPIO113__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(113) | 6) +- +-#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +-#define PINMUX_GPIO114__FUNC_MSDC1_DAT2 (MTK_PIN_NO(114) | 1) +-#define PINMUX_GPIO114__FUNC_JTRSTn_SEL3 (MTK_PIN_NO(114) | 2) +-#define PINMUX_GPIO114__FUNC_UDI_NTRST (MTK_PIN_NO(114) | 3) +-#define PINMUX_GPIO114__FUNC_I2SO2_D2 (MTK_PIN_NO(114) | 4) +-#define PINMUX_GPIO114__FUNC_CCU1_JTAG_TRST (MTK_PIN_NO(114) | 5) +-#define PINMUX_GPIO114__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(114) | 6) +- +-#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +-#define PINMUX_GPIO115__FUNC_MSDC1_DAT3 (MTK_PIN_NO(115) | 1) +-#define PINMUX_GPIO115__FUNC_I2SO2_D3 (MTK_PIN_NO(115) | 4) +-#define PINMUX_GPIO115__FUNC_MD32_1_GPIO2 (MTK_PIN_NO(115) | 6) +- +-#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +-#define PINMUX_GPIO116__FUNC_MSDC0_DAT7 (MTK_PIN_NO(116) | 1) +- +-#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +-#define PINMUX_GPIO117__FUNC_MSDC0_DAT6 (MTK_PIN_NO(117) | 1) +- +-#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +-#define PINMUX_GPIO118__FUNC_MSDC0_DAT5 (MTK_PIN_NO(118) | 1) +- +-#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +-#define PINMUX_GPIO119__FUNC_MSDC0_DAT4 (MTK_PIN_NO(119) | 1) +- +-#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +-#define PINMUX_GPIO120__FUNC_MSDC0_RSTB (MTK_PIN_NO(120) | 1) +- +-#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +-#define PINMUX_GPIO121__FUNC_MSDC0_CMD (MTK_PIN_NO(121) | 1) +- +-#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +-#define PINMUX_GPIO122__FUNC_MSDC0_CLK (MTK_PIN_NO(122) | 1) +- +-#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +-#define PINMUX_GPIO123__FUNC_MSDC0_DAT3 (MTK_PIN_NO(123) | 1) +- +-#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +-#define PINMUX_GPIO124__FUNC_MSDC0_DAT2 (MTK_PIN_NO(124) | 1) +- +-#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +-#define PINMUX_GPIO125__FUNC_MSDC0_DAT1 (MTK_PIN_NO(125) | 1) +- +-#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +-#define PINMUX_GPIO126__FUNC_MSDC0_DAT0 (MTK_PIN_NO(126) | 1) +- +-#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +-#define PINMUX_GPIO127__FUNC_MSDC0_DSL (MTK_PIN_NO(127) | 1) +- +-#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +-#define PINMUX_GPIO128__FUNC_IDDIG (MTK_PIN_NO(128) | 1) +-#define PINMUX_GPIO128__FUNC_UCTS2 (MTK_PIN_NO(128) | 2) +-#define PINMUX_GPIO128__FUNC_UTXD5 (MTK_PIN_NO(128) | 3) +-#define PINMUX_GPIO128__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(128) | 4) +-#define PINMUX_GPIO128__FUNC_mbistreaden_trigger (MTK_PIN_NO(128) | 5) +-#define PINMUX_GPIO128__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(128) | 6) +-#define PINMUX_GPIO128__FUNC_SCP_SCL2 (MTK_PIN_NO(128) | 7) +- +-#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +-#define PINMUX_GPIO129__FUNC_USB_DRVVBUS (MTK_PIN_NO(129) | 1) +-#define PINMUX_GPIO129__FUNC_URTS2 (MTK_PIN_NO(129) | 2) +-#define PINMUX_GPIO129__FUNC_URXD5 (MTK_PIN_NO(129) | 3) +-#define PINMUX_GPIO129__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(129) | 4) +-#define PINMUX_GPIO129__FUNC_mbistwriteen_trigger (MTK_PIN_NO(129) | 5) +-#define PINMUX_GPIO129__FUNC_MD32_1_GPIO1 (MTK_PIN_NO(129) | 6) +-#define PINMUX_GPIO129__FUNC_SCP_SDA2 (MTK_PIN_NO(129) | 7) +- +-#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +-#define PINMUX_GPIO130__FUNC_IDDIG_1P (MTK_PIN_NO(130) | 1) +-#define PINMUX_GPIO130__FUNC_SPINOR_IO2 (MTK_PIN_NO(130) | 2) +-#define PINMUX_GPIO130__FUNC_SNFI_WP (MTK_PIN_NO(130) | 3) +-#define PINMUX_GPIO130__FUNC_VPU_UDI_NTRST (MTK_PIN_NO(130) | 4) +- +-#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +-#define PINMUX_GPIO131__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(131) | 1) +-#define PINMUX_GPIO131__FUNC_SPINOR_IO3 (MTK_PIN_NO(131) | 2) +-#define PINMUX_GPIO131__FUNC_SNFI_HOLD (MTK_PIN_NO(131) | 3) +-#define PINMUX_GPIO131__FUNC_MD32_1_JTAG_TRST (MTK_PIN_NO(131) | 4) +-#define PINMUX_GPIO131__FUNC_SCP_JTAG0_TRSTN (MTK_PIN_NO(131) | 5) +-#define PINMUX_GPIO131__FUNC_APU_JTAG_TRST (MTK_PIN_NO(131) | 6) +- +-#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +-#define PINMUX_GPIO132__FUNC_SPIM0_CSB (MTK_PIN_NO(132) | 1) +-#define PINMUX_GPIO132__FUNC_SCP_SPI0_CS (MTK_PIN_NO(132) | 2) +-#define PINMUX_GPIO132__FUNC_SPIS0_CSB (MTK_PIN_NO(132) | 3) +-#define PINMUX_GPIO132__FUNC_VPU_UDI_TMS (MTK_PIN_NO(132) | 4) +-#define PINMUX_GPIO132__FUNC_I2SO5_D0 (MTK_PIN_NO(132) | 6) +- +-#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +-#define PINMUX_GPIO133__FUNC_SPIM0_CLK (MTK_PIN_NO(133) | 1) +-#define PINMUX_GPIO133__FUNC_SCP_SPI0_CK (MTK_PIN_NO(133) | 2) +-#define PINMUX_GPIO133__FUNC_SPIS0_CLK (MTK_PIN_NO(133) | 3) +-#define PINMUX_GPIO133__FUNC_VPU_UDI_TCK (MTK_PIN_NO(133) | 4) +-#define PINMUX_GPIO133__FUNC_I2SO5_BCK (MTK_PIN_NO(133) | 6) +- +-#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +-#define PINMUX_GPIO134__FUNC_SPIM0_MO (MTK_PIN_NO(134) | 1) +-#define PINMUX_GPIO134__FUNC_SCP_SPI0_MO (MTK_PIN_NO(134) | 2) +-#define PINMUX_GPIO134__FUNC_SPIS0_SI (MTK_PIN_NO(134) | 3) +-#define PINMUX_GPIO134__FUNC_VPU_UDI_TDO (MTK_PIN_NO(134) | 4) +-#define PINMUX_GPIO134__FUNC_I2SO5_WS (MTK_PIN_NO(134) | 6) +- +-#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +-#define PINMUX_GPIO135__FUNC_SPIM0_MI (MTK_PIN_NO(135) | 1) +-#define PINMUX_GPIO135__FUNC_SCP_SPI0_MI (MTK_PIN_NO(135) | 2) +-#define PINMUX_GPIO135__FUNC_SPIS0_SO (MTK_PIN_NO(135) | 3) +-#define PINMUX_GPIO135__FUNC_VPU_UDI_TDI (MTK_PIN_NO(135) | 4) +-#define PINMUX_GPIO135__FUNC_I2SO5_MCK (MTK_PIN_NO(135) | 6) +- +-#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +-#define PINMUX_GPIO136__FUNC_SPIM1_CSB (MTK_PIN_NO(136) | 1) +-#define PINMUX_GPIO136__FUNC_SCP_SPI1_A_CS (MTK_PIN_NO(136) | 2) +-#define PINMUX_GPIO136__FUNC_SPIS1_CSB (MTK_PIN_NO(136) | 3) +-#define PINMUX_GPIO136__FUNC_MD32_1_JTAG_TMS (MTK_PIN_NO(136) | 4) +-#define PINMUX_GPIO136__FUNC_SCP_JTAG0_TMS (MTK_PIN_NO(136) | 5) +-#define PINMUX_GPIO136__FUNC_APU_JTAG_TMS (MTK_PIN_NO(136) | 6) +-#define PINMUX_GPIO136__FUNC_DBG_MON_A15 (MTK_PIN_NO(136) | 7) +- +-#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +-#define PINMUX_GPIO137__FUNC_SPIM1_CLK (MTK_PIN_NO(137) | 1) +-#define PINMUX_GPIO137__FUNC_SCP_SPI1_A_CK (MTK_PIN_NO(137) | 2) +-#define PINMUX_GPIO137__FUNC_SPIS1_CLK (MTK_PIN_NO(137) | 3) +-#define PINMUX_GPIO137__FUNC_MD32_1_JTAG_TCK (MTK_PIN_NO(137) | 4) +-#define PINMUX_GPIO137__FUNC_SCP_JTAG0_TCK (MTK_PIN_NO(137) | 5) +-#define PINMUX_GPIO137__FUNC_APU_JTAG_TCK (MTK_PIN_NO(137) | 6) +-#define PINMUX_GPIO137__FUNC_DBG_MON_A14 (MTK_PIN_NO(137) | 7) +- +-#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +-#define PINMUX_GPIO138__FUNC_SPIM1_MO (MTK_PIN_NO(138) | 1) +-#define PINMUX_GPIO138__FUNC_SCP_SPI1_A_MO (MTK_PIN_NO(138) | 2) +-#define PINMUX_GPIO138__FUNC_SPIS1_SI (MTK_PIN_NO(138) | 3) +-#define PINMUX_GPIO138__FUNC_MD32_1_JTAG_TDO (MTK_PIN_NO(138) | 4) +-#define PINMUX_GPIO138__FUNC_SCP_JTAG0_TDO (MTK_PIN_NO(138) | 5) +-#define PINMUX_GPIO138__FUNC_APU_JTAG_TDO (MTK_PIN_NO(138) | 6) +-#define PINMUX_GPIO138__FUNC_DBG_MON_A16 (MTK_PIN_NO(138) | 7) +- +-#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +-#define PINMUX_GPIO139__FUNC_SPIM1_MI (MTK_PIN_NO(139) | 1) +-#define PINMUX_GPIO139__FUNC_SCP_SPI1_A_MI (MTK_PIN_NO(139) | 2) +-#define PINMUX_GPIO139__FUNC_SPIS1_SO (MTK_PIN_NO(139) | 3) +-#define PINMUX_GPIO139__FUNC_MD32_1_JTAG_TDI (MTK_PIN_NO(139) | 4) +-#define PINMUX_GPIO139__FUNC_SCP_JTAG0_TDI (MTK_PIN_NO(139) | 5) +-#define PINMUX_GPIO139__FUNC_APU_JTAG_TDI (MTK_PIN_NO(139) | 6) +-#define PINMUX_GPIO139__FUNC_DBG_MON_A17 (MTK_PIN_NO(139) | 7) +- +-#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +-#define PINMUX_GPIO140__FUNC_SPIM2_CSB (MTK_PIN_NO(140) | 1) +-#define PINMUX_GPIO140__FUNC_SPINOR_CS (MTK_PIN_NO(140) | 2) +-#define PINMUX_GPIO140__FUNC_SNFI_CS (MTK_PIN_NO(140) | 3) +-#define PINMUX_GPIO140__FUNC_DMIC3_DAT (MTK_PIN_NO(140) | 4) +-#define PINMUX_GPIO140__FUNC_DBG_MON_A11 (MTK_PIN_NO(140) | 7) +- +-#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +-#define PINMUX_GPIO141__FUNC_SPIM2_CLK (MTK_PIN_NO(141) | 1) +-#define PINMUX_GPIO141__FUNC_SPINOR_CK (MTK_PIN_NO(141) | 2) +-#define PINMUX_GPIO141__FUNC_SNFI_CLK (MTK_PIN_NO(141) | 3) +-#define PINMUX_GPIO141__FUNC_DMIC3_CLK (MTK_PIN_NO(141) | 4) +-#define PINMUX_GPIO141__FUNC_DBG_MON_A10 (MTK_PIN_NO(141) | 7) +- +-#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +-#define PINMUX_GPIO142__FUNC_SPIM2_MO (MTK_PIN_NO(142) | 1) +-#define PINMUX_GPIO142__FUNC_SPINOR_IO0 (MTK_PIN_NO(142) | 2) +-#define PINMUX_GPIO142__FUNC_SNFI_MOSI (MTK_PIN_NO(142) | 3) +-#define PINMUX_GPIO142__FUNC_DMIC4_DAT (MTK_PIN_NO(142) | 4) +-#define PINMUX_GPIO142__FUNC_DBG_MON_A12 (MTK_PIN_NO(142) | 7) +- +-#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +-#define PINMUX_GPIO143__FUNC_SPIM2_MI (MTK_PIN_NO(143) | 1) +-#define PINMUX_GPIO143__FUNC_SPINOR_IO1 (MTK_PIN_NO(143) | 2) +-#define PINMUX_GPIO143__FUNC_SNFI_MISO (MTK_PIN_NO(143) | 3) +-#define PINMUX_GPIO143__FUNC_DMIC4_CLK (MTK_PIN_NO(143) | 4) +-#define PINMUX_GPIO143__FUNC_DBG_MON_A13 (MTK_PIN_NO(143) | 7) +- +-#endif /* __MT8195-PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt8365-pinfunc.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt8365-pinfunc.h +deleted file mode 100644 +index e2ec8af57dcf..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/mt8365-pinfunc.h ++++ /dev/null +@@ -1,858 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2021 MediaTek Inc. +- */ +-#ifndef __MT8365_PINFUNC_H +-#define __MT8365_PINFUNC_H +- +-#include +- +-#define MT8365_PIN_0_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +-#define MT8365_PIN_0_GPIO0__FUNC_DPI_D0 (MTK_PIN_NO(0) | 1) +-#define MT8365_PIN_0_GPIO0__FUNC_PWM_A (MTK_PIN_NO(0) | 2) +-#define MT8365_PIN_0_GPIO0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3) +-#define MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4) +-#define MT8365_PIN_0_GPIO0__FUNC_CONN_MCU_TDO (MTK_PIN_NO(0) | 5) +-#define MT8365_PIN_0_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7) +- +-#define MT8365_PIN_1_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +-#define MT8365_PIN_1_GPIO1__FUNC_DPI_D1 (MTK_PIN_NO(1) | 1) +-#define MT8365_PIN_1_GPIO1__FUNC_PWM_B (MTK_PIN_NO(1) | 2) +-#define MT8365_PIN_1_GPIO1__FUNC_I2S2_LRCK (MTK_PIN_NO(1) | 3) +-#define MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4) +-#define MT8365_PIN_1_GPIO1__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(1) | 5) +-#define MT8365_PIN_1_GPIO1__FUNC_DBG_MON_A1 (MTK_PIN_NO(1) | 7) +- +-#define MT8365_PIN_2_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +-#define MT8365_PIN_2_GPIO2__FUNC_DPI_D2 (MTK_PIN_NO(2) | 1) +-#define MT8365_PIN_2_GPIO2__FUNC_PWM_C (MTK_PIN_NO(2) | 2) +-#define MT8365_PIN_2_GPIO2__FUNC_I2S2_MCK (MTK_PIN_NO(2) | 3) +-#define MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4) +-#define MT8365_PIN_2_GPIO2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(2) | 5) +-#define MT8365_PIN_2_GPIO2__FUNC_DBG_MON_A2 (MTK_PIN_NO(2) | 7) +- +-#define MT8365_PIN_3_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +-#define MT8365_PIN_3_GPIO3__FUNC_DPI_D3 (MTK_PIN_NO(3) | 1) +-#define MT8365_PIN_3_GPIO3__FUNC_CLKM0 (MTK_PIN_NO(3) | 2) +-#define MT8365_PIN_3_GPIO3__FUNC_I2S2_DI (MTK_PIN_NO(3) | 3) +-#define MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4) +-#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_TCK (MTK_PIN_NO(3) | 5) +-#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(3) | 6) +-#define MT8365_PIN_3_GPIO3__FUNC_DBG_MON_A3 (MTK_PIN_NO(3) | 7) +- +-#define MT8365_PIN_4_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +-#define MT8365_PIN_4_GPIO4__FUNC_DPI_D4 (MTK_PIN_NO(4) | 1) +-#define MT8365_PIN_4_GPIO4__FUNC_CLKM1 (MTK_PIN_NO(4) | 2) +-#define MT8365_PIN_4_GPIO4__FUNC_I2S1_BCK (MTK_PIN_NO(4) | 3) +-#define MT8365_PIN_4_GPIO4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4) +-#define MT8365_PIN_4_GPIO4__FUNC_CONN_MCU_TDI (MTK_PIN_NO(4) | 5) +-#define MT8365_PIN_4_GPIO4__FUNC_VDEC_TEST_CK (MTK_PIN_NO(4) | 6) +-#define MT8365_PIN_4_GPIO4__FUNC_DBG_MON_A4 (MTK_PIN_NO(4) | 7) +- +-#define MT8365_PIN_5_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +-#define MT8365_PIN_5_GPIO5__FUNC_DPI_D5 (MTK_PIN_NO(5) | 1) +-#define MT8365_PIN_5_GPIO5__FUNC_CLKM2 (MTK_PIN_NO(5) | 2) +-#define MT8365_PIN_5_GPIO5__FUNC_I2S1_LRCK (MTK_PIN_NO(5) | 3) +-#define MT8365_PIN_5_GPIO5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4) +-#define MT8365_PIN_5_GPIO5__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(5) | 5) +-#define MT8365_PIN_5_GPIO5__FUNC_MM_TEST_CK (MTK_PIN_NO(5) | 6) +-#define MT8365_PIN_5_GPIO5__FUNC_DBG_MON_A5 (MTK_PIN_NO(5) | 7) +- +-#define MT8365_PIN_6_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +-#define MT8365_PIN_6_GPIO6__FUNC_DPI_D6 (MTK_PIN_NO(6) | 1) +-#define MT8365_PIN_6_GPIO6__FUNC_CLKM3 (MTK_PIN_NO(6) | 2) +-#define MT8365_PIN_6_GPIO6__FUNC_I2S1_MCK (MTK_PIN_NO(6) | 3) +-#define MT8365_PIN_6_GPIO6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4) +-#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_TMS (MTK_PIN_NO(6) | 5) +-#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(6) | 6) +-#define MT8365_PIN_6_GPIO6__FUNC_DBG_MON_A6 (MTK_PIN_NO(6) | 7) +- +-#define MT8365_PIN_7_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +-#define MT8365_PIN_7_GPIO7__FUNC_DPI_D7 (MTK_PIN_NO(7) | 1) +-#define MT8365_PIN_7_GPIO7__FUNC_I2S1_DO (MTK_PIN_NO(7) | 3) +-#define MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4) +-#define MT8365_PIN_7_GPIO7__FUNC_CONN_DSP_JCK (MTK_PIN_NO(7) | 5) +-#define MT8365_PIN_7_GPIO7__FUNC_DBG_MON_A7 (MTK_PIN_NO(7) | 7) +- +-#define MT8365_PIN_8_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +-#define MT8365_PIN_8_GPIO8__FUNC_DPI_D8 (MTK_PIN_NO(8) | 1) +-#define MT8365_PIN_8_GPIO8__FUNC_SPI_CLK (MTK_PIN_NO(8) | 2) +-#define MT8365_PIN_8_GPIO8__FUNC_I2S0_BCK (MTK_PIN_NO(8) | 3) +-#define MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4) +-#define MT8365_PIN_8_GPIO8__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(8) | 5) +-#define MT8365_PIN_8_GPIO8__FUNC_DBG_MON_A8 (MTK_PIN_NO(8) | 7) +- +-#define MT8365_PIN_9_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +-#define MT8365_PIN_9_GPIO9__FUNC_DPI_D9 (MTK_PIN_NO(9) | 1) +-#define MT8365_PIN_9_GPIO9__FUNC_SPI_CSB (MTK_PIN_NO(9) | 2) +-#define MT8365_PIN_9_GPIO9__FUNC_I2S0_LRCK (MTK_PIN_NO(9) | 3) +-#define MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4) +-#define MT8365_PIN_9_GPIO9__FUNC_CONN_DSP_JDI (MTK_PIN_NO(9) | 5) +-#define MT8365_PIN_9_GPIO9__FUNC_DBG_MON_A9 (MTK_PIN_NO(9) | 7) +- +-#define MT8365_PIN_10_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +-#define MT8365_PIN_10_GPIO10__FUNC_DPI_D10 (MTK_PIN_NO(10) | 1) +-#define MT8365_PIN_10_GPIO10__FUNC_SPI_MI (MTK_PIN_NO(10) | 2) +-#define MT8365_PIN_10_GPIO10__FUNC_I2S0_MCK (MTK_PIN_NO(10) | 3) +-#define MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4) +-#define MT8365_PIN_10_GPIO10__FUNC_CONN_DSP_JMS (MTK_PIN_NO(10) | 5) +-#define MT8365_PIN_10_GPIO10__FUNC_DBG_MON_A10 (MTK_PIN_NO(10) | 7) +- +-#define MT8365_PIN_11_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +-#define MT8365_PIN_11_GPIO11__FUNC_DPI_D11 (MTK_PIN_NO(11) | 1) +-#define MT8365_PIN_11_GPIO11__FUNC_SPI_MO (MTK_PIN_NO(11) | 2) +-#define MT8365_PIN_11_GPIO11__FUNC_I2S0_DI (MTK_PIN_NO(11) | 3) +-#define MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 4) +-#define MT8365_PIN_11_GPIO11__FUNC_CONN_DSP_JDO (MTK_PIN_NO(11) | 5) +-#define MT8365_PIN_11_GPIO11__FUNC_DBG_MON_A11 (MTK_PIN_NO(11) | 7) +- +-#define MT8365_PIN_12_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +-#define MT8365_PIN_12_GPIO12__FUNC_DPI_DE (MTK_PIN_NO(12) | 1) +-#define MT8365_PIN_12_GPIO12__FUNC_UCTS1 (MTK_PIN_NO(12) | 2) +-#define MT8365_PIN_12_GPIO12__FUNC_I2S3_BCK (MTK_PIN_NO(12) | 3) +-#define MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 4) +-#define MT8365_PIN_12_GPIO12__FUNC_O_WIFI_TXD (MTK_PIN_NO(12) | 5) +-#define MT8365_PIN_12_GPIO12__FUNC_DBG_MON_A12 (MTK_PIN_NO(12) | 7) +- +-#define MT8365_PIN_13_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +-#define MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC (MTK_PIN_NO(13) | 1) +-#define MT8365_PIN_13_GPIO13__FUNC_URTS1 (MTK_PIN_NO(13) | 2) +-#define MT8365_PIN_13_GPIO13__FUNC_I2S3_LRCK (MTK_PIN_NO(13) | 3) +-#define MT8365_PIN_13_GPIO13__FUNC_EXT_COL (MTK_PIN_NO(13) | 4) +-#define MT8365_PIN_13_GPIO13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 5) +-#define MT8365_PIN_13_GPIO13__FUNC_DBG_MON_A13 (MTK_PIN_NO(13) | 7) +- +-#define MT8365_PIN_14_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +-#define MT8365_PIN_14_GPIO14__FUNC_DPI_CK (MTK_PIN_NO(14) | 1) +-#define MT8365_PIN_14_GPIO14__FUNC_UCTS2 (MTK_PIN_NO(14) | 2) +-#define MT8365_PIN_14_GPIO14__FUNC_I2S3_MCK (MTK_PIN_NO(14) | 3) +-#define MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO (MTK_PIN_NO(14) | 4) +-#define MT8365_PIN_14_GPIO14__FUNC_SPDIF_OUT (MTK_PIN_NO(14) | 5) +-#define MT8365_PIN_14_GPIO14__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(14) | 6) +-#define MT8365_PIN_14_GPIO14__FUNC_DBG_MON_A14 (MTK_PIN_NO(14) | 7) +- +-#define MT8365_PIN_15_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +-#define MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC (MTK_PIN_NO(15) | 1) +-#define MT8365_PIN_15_GPIO15__FUNC_URTS2 (MTK_PIN_NO(15) | 2) +-#define MT8365_PIN_15_GPIO15__FUNC_I2S3_DO (MTK_PIN_NO(15) | 3) +-#define MT8365_PIN_15_GPIO15__FUNC_EXT_MDC (MTK_PIN_NO(15) | 4) +-#define MT8365_PIN_15_GPIO15__FUNC_IRRX (MTK_PIN_NO(15) | 5) +-#define MT8365_PIN_15_GPIO15__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(15) | 6) +-#define MT8365_PIN_15_GPIO15__FUNC_DBG_MON_A15 (MTK_PIN_NO(15) | 7) +- +-#define MT8365_PIN_16_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +-#define MT8365_PIN_16_GPIO16__FUNC_DPI_D12 (MTK_PIN_NO(16) | 1) +-#define MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS (MTK_PIN_NO(16) | 2) +-#define MT8365_PIN_16_GPIO16__FUNC_PWM_A (MTK_PIN_NO(16) | 3) +-#define MT8365_PIN_16_GPIO16__FUNC_CLKM0 (MTK_PIN_NO(16) | 4) +-#define MT8365_PIN_16_GPIO16__FUNC_ANT_SEL0 (MTK_PIN_NO(16) | 5) +-#define MT8365_PIN_16_GPIO16__FUNC_TSF_IN (MTK_PIN_NO(16) | 6) +-#define MT8365_PIN_16_GPIO16__FUNC_DBG_MON_A16 (MTK_PIN_NO(16) | 7) +- +-#define MT8365_PIN_17_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +-#define MT8365_PIN_17_GPIO17__FUNC_DPI_D13 (MTK_PIN_NO(17) | 1) +-#define MT8365_PIN_17_GPIO17__FUNC_IDDIG (MTK_PIN_NO(17) | 2) +-#define MT8365_PIN_17_GPIO17__FUNC_PWM_B (MTK_PIN_NO(17) | 3) +-#define MT8365_PIN_17_GPIO17__FUNC_CLKM1 (MTK_PIN_NO(17) | 4) +-#define MT8365_PIN_17_GPIO17__FUNC_ANT_SEL1 (MTK_PIN_NO(17) | 5) +-#define MT8365_PIN_17_GPIO17__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(17) | 6) +-#define MT8365_PIN_17_GPIO17__FUNC_DBG_MON_A17 (MTK_PIN_NO(17) | 7) +- +-#define MT8365_PIN_18_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +-#define MT8365_PIN_18_GPIO18__FUNC_DPI_D14 (MTK_PIN_NO(18) | 1) +-#define MT8365_PIN_18_GPIO18__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(18) | 2) +-#define MT8365_PIN_18_GPIO18__FUNC_PWM_C (MTK_PIN_NO(18) | 3) +-#define MT8365_PIN_18_GPIO18__FUNC_CLKM2 (MTK_PIN_NO(18) | 4) +-#define MT8365_PIN_18_GPIO18__FUNC_ANT_SEL2 (MTK_PIN_NO(18) | 5) +-#define MT8365_PIN_18_GPIO18__FUNC_MFG_TEST_CK (MTK_PIN_NO(18) | 6) +-#define MT8365_PIN_18_GPIO18__FUNC_DBG_MON_A18 (MTK_PIN_NO(18) | 7) +- +-#define MT8365_PIN_19_DISP_PWM__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +-#define MT8365_PIN_19_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(19) | 1) +-#define MT8365_PIN_19_DISP_PWM__FUNC_PWM_A (MTK_PIN_NO(19) | 2) +-#define MT8365_PIN_19_DISP_PWM__FUNC_DBG_MON_A19 (MTK_PIN_NO(19) | 7) +- +-#define MT8365_PIN_20_LCM_RST__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +-#define MT8365_PIN_20_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(20) | 1) +-#define MT8365_PIN_20_LCM_RST__FUNC_PWM_B (MTK_PIN_NO(20) | 2) +-#define MT8365_PIN_20_LCM_RST__FUNC_DBG_MON_A20 (MTK_PIN_NO(20) | 7) +- +-#define MT8365_PIN_21_DSI_TE__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +-#define MT8365_PIN_21_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(21) | 1) +-#define MT8365_PIN_21_DSI_TE__FUNC_PWM_C (MTK_PIN_NO(21) | 2) +-#define MT8365_PIN_21_DSI_TE__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 3) +-#define MT8365_PIN_21_DSI_TE__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(21) | 4) +-#define MT8365_PIN_21_DSI_TE__FUNC_DBG_MON_A21 (MTK_PIN_NO(21) | 7) +- +-#define MT8365_PIN_22_KPROW0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +-#define MT8365_PIN_22_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(22) | 1) +-#define MT8365_PIN_22_KPROW0__FUNC_DBG_MON_A22 (MTK_PIN_NO(22) | 7) +- +-#define MT8365_PIN_23_KPROW1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +-#define MT8365_PIN_23_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(23) | 1) +-#define MT8365_PIN_23_KPROW1__FUNC_IDDIG (MTK_PIN_NO(23) | 2) +-#define MT8365_PIN_23_KPROW1__FUNC_WIFI_TXD (MTK_PIN_NO(23) | 3) +-#define MT8365_PIN_23_KPROW1__FUNC_CLKM3 (MTK_PIN_NO(23) | 4) +-#define MT8365_PIN_23_KPROW1__FUNC_ANT_SEL1 (MTK_PIN_NO(23) | 5) +-#define MT8365_PIN_23_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 6) +-#define MT8365_PIN_23_KPROW1__FUNC_DBG_MON_B0 (MTK_PIN_NO(23) | 7) +- +-#define MT8365_PIN_24_KPCOL0__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +-#define MT8365_PIN_24_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(24) | 1) +-#define MT8365_PIN_24_KPCOL0__FUNC_DBG_MON_A23 (MTK_PIN_NO(24) | 7) +- +-#define MT8365_PIN_25_KPCOL1__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +-#define MT8365_PIN_25_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(25) | 1) +-#define MT8365_PIN_25_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(25) | 2) +-#define MT8365_PIN_25_KPCOL1__FUNC_APU_JTAG_TRST (MTK_PIN_NO(25) | 3) +-#define MT8365_PIN_25_KPCOL1__FUNC_UDI_NTRST_XI (MTK_PIN_NO(25) | 4) +-#define MT8365_PIN_25_KPCOL1__FUNC_DFD_NTRST_XI (MTK_PIN_NO(25) | 5) +-#define MT8365_PIN_25_KPCOL1__FUNC_CONN_TEST_CK (MTK_PIN_NO(25) | 6) +-#define MT8365_PIN_25_KPCOL1__FUNC_DBG_MON_B1 (MTK_PIN_NO(25) | 7) +- +-#define MT8365_PIN_26_SPI_CS__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +-#define MT8365_PIN_26_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(26) | 1) +-#define MT8365_PIN_26_SPI_CS__FUNC_APU_JTAG_TMS (MTK_PIN_NO(26) | 3) +-#define MT8365_PIN_26_SPI_CS__FUNC_UDI_TMS_XI (MTK_PIN_NO(26) | 4) +-#define MT8365_PIN_26_SPI_CS__FUNC_DFD_TMS_XI (MTK_PIN_NO(26) | 5) +-#define MT8365_PIN_26_SPI_CS__FUNC_CONN_TEST_CK (MTK_PIN_NO(26) | 6) +-#define MT8365_PIN_26_SPI_CS__FUNC_DBG_MON_A24 (MTK_PIN_NO(26) | 7) +- +-#define MT8365_PIN_27_SPI_CK__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +-#define MT8365_PIN_27_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(27) | 1) +-#define MT8365_PIN_27_SPI_CK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(27) | 3) +-#define MT8365_PIN_27_SPI_CK__FUNC_UDI_TCK_XI (MTK_PIN_NO(27) | 4) +-#define MT8365_PIN_27_SPI_CK__FUNC_DFD_TCK_XI (MTK_PIN_NO(27) | 5) +-#define MT8365_PIN_27_SPI_CK__FUNC_APU_TEST_CK (MTK_PIN_NO(27) | 6) +-#define MT8365_PIN_27_SPI_CK__FUNC_DBG_MON_A25 (MTK_PIN_NO(27) | 7) +- +-#define MT8365_PIN_28_SPI_MI__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +-#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(28) | 1) +-#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(28) | 2) +-#define MT8365_PIN_28_SPI_MI__FUNC_APU_JTAG_TDI (MTK_PIN_NO(28) | 3) +-#define MT8365_PIN_28_SPI_MI__FUNC_UDI_TDI_XI (MTK_PIN_NO(28) | 4) +-#define MT8365_PIN_28_SPI_MI__FUNC_DFD_TDI_XI (MTK_PIN_NO(28) | 5) +-#define MT8365_PIN_28_SPI_MI__FUNC_DSP_TEST_CK (MTK_PIN_NO(28) | 6) +-#define MT8365_PIN_28_SPI_MI__FUNC_DBG_MON_A26 (MTK_PIN_NO(28) | 7) +- +-#define MT8365_PIN_29_SPI_MO__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +-#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(29) | 1) +-#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(29) | 2) +-#define MT8365_PIN_29_SPI_MO__FUNC_APU_JTAG_TDO (MTK_PIN_NO(29) | 3) +-#define MT8365_PIN_29_SPI_MO__FUNC_UDI_TDO (MTK_PIN_NO(29) | 4) +-#define MT8365_PIN_29_SPI_MO__FUNC_DFD_TDO (MTK_PIN_NO(29) | 5) +-#define MT8365_PIN_29_SPI_MO__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(29) | 6) +-#define MT8365_PIN_29_SPI_MO__FUNC_DBG_MON_A27 (MTK_PIN_NO(29) | 7) +- +-#define MT8365_PIN_30_JTMS__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +-#define MT8365_PIN_30_JTMS__FUNC_JTMS (MTK_PIN_NO(30) | 1) +-#define MT8365_PIN_30_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(30) | 2) +-#define MT8365_PIN_30_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(30) | 3) +-#define MT8365_PIN_30_JTMS__FUNC_MCU_SPM_TMS (MTK_PIN_NO(30) | 4) +-#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(30) | 5) +-#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 6) +- +-#define MT8365_PIN_31_JTCK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +-#define MT8365_PIN_31_JTCK__FUNC_JTCK (MTK_PIN_NO(31) | 1) +-#define MT8365_PIN_31_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(31) | 2) +-#define MT8365_PIN_31_JTCK__FUNC_UDI_TCK_XI (MTK_PIN_NO(31) | 3) +-#define MT8365_PIN_31_JTCK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(31) | 4) +-#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(31) | 5) +-#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(31) | 6) +- +-#define MT8365_PIN_32_JTDI__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +-#define MT8365_PIN_32_JTDI__FUNC_JTDI (MTK_PIN_NO(32) | 1) +-#define MT8365_PIN_32_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(32) | 2) +-#define MT8365_PIN_32_JTDI__FUNC_UDI_TDI_XI (MTK_PIN_NO(32) | 3) +-#define MT8365_PIN_32_JTDI__FUNC_MCU_SPM_TDI (MTK_PIN_NO(32) | 4) +-#define MT8365_PIN_32_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(32) | 5) +- +-#define MT8365_PIN_33_JTDO__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +-#define MT8365_PIN_33_JTDO__FUNC_JTDO (MTK_PIN_NO(33) | 1) +-#define MT8365_PIN_33_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(33) | 2) +-#define MT8365_PIN_33_JTDO__FUNC_UDI_TDO (MTK_PIN_NO(33) | 3) +-#define MT8365_PIN_33_JTDO__FUNC_MCU_SPM_TDO (MTK_PIN_NO(33) | 4) +-#define MT8365_PIN_33_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(33) | 5) +- +-#define MT8365_PIN_34_JTRST__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +-#define MT8365_PIN_34_JTRST__FUNC_JTRST (MTK_PIN_NO(34) | 1) +-#define MT8365_PIN_34_JTRST__FUNC_DFD_NTRST_XI (MTK_PIN_NO(34) | 2) +-#define MT8365_PIN_34_JTRST__FUNC_UDI_NTRST_XI (MTK_PIN_NO(34) | 3) +-#define MT8365_PIN_34_JTRST__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(34) | 4) +-#define MT8365_PIN_34_JTRST__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(34) | 5) +- +-#define MT8365_PIN_35_URXD0__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +-#define MT8365_PIN_35_URXD0__FUNC_URXD0 (MTK_PIN_NO(35) | 1) +-#define MT8365_PIN_35_URXD0__FUNC_UTXD0 (MTK_PIN_NO(35) | 2) +-#define MT8365_PIN_35_URXD0__FUNC_DSP_URXD0 (MTK_PIN_NO(35) | 7) +- +-#define MT8365_PIN_36_UTXD0__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +-#define MT8365_PIN_36_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(36) | 1) +-#define MT8365_PIN_36_UTXD0__FUNC_URXD0 (MTK_PIN_NO(36) | 2) +-#define MT8365_PIN_36_UTXD0__FUNC_DSP_UTXD0 (MTK_PIN_NO(36) | 7) +- +-#define MT8365_PIN_37_URXD1__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +-#define MT8365_PIN_37_URXD1__FUNC_URXD1 (MTK_PIN_NO(37) | 1) +-#define MT8365_PIN_37_URXD1__FUNC_UTXD1 (MTK_PIN_NO(37) | 2) +-#define MT8365_PIN_37_URXD1__FUNC_UCTS2 (MTK_PIN_NO(37) | 3) +-#define MT8365_PIN_37_URXD1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(37) | 4) +-#define MT8365_PIN_37_URXD1__FUNC_CONN_UART0_RXD (MTK_PIN_NO(37) | 5) +-#define MT8365_PIN_37_URXD1__FUNC_I2S0_MCK (MTK_PIN_NO(37) | 6) +-#define MT8365_PIN_37_URXD1__FUNC_DSP_URXD0 (MTK_PIN_NO(37) | 7) +- +-#define MT8365_PIN_38_UTXD1__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +-#define MT8365_PIN_38_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(38) | 1) +-#define MT8365_PIN_38_UTXD1__FUNC_URXD1 (MTK_PIN_NO(38) | 2) +-#define MT8365_PIN_38_UTXD1__FUNC_URTS2 (MTK_PIN_NO(38) | 3) +-#define MT8365_PIN_38_UTXD1__FUNC_ANT_SEL2 (MTK_PIN_NO(38) | 4) +-#define MT8365_PIN_38_UTXD1__FUNC_CONN_UART0_TXD (MTK_PIN_NO(38) | 5) +-#define MT8365_PIN_38_UTXD1__FUNC_I2S1_MCK (MTK_PIN_NO(38) | 6) +-#define MT8365_PIN_38_UTXD1__FUNC_DSP_UTXD0 (MTK_PIN_NO(38) | 7) +- +-#define MT8365_PIN_39_URXD2__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +-#define MT8365_PIN_39_URXD2__FUNC_URXD2 (MTK_PIN_NO(39) | 1) +-#define MT8365_PIN_39_URXD2__FUNC_UTXD2 (MTK_PIN_NO(39) | 2) +-#define MT8365_PIN_39_URXD2__FUNC_UCTS1 (MTK_PIN_NO(39) | 3) +-#define MT8365_PIN_39_URXD2__FUNC_IDDIG (MTK_PIN_NO(39) | 4) +-#define MT8365_PIN_39_URXD2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(39) | 5) +-#define MT8365_PIN_39_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(39) | 6) +-#define MT8365_PIN_39_URXD2__FUNC_DSP_URXD0 (MTK_PIN_NO(39) | 7) +- +-#define MT8365_PIN_40_UTXD2__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +-#define MT8365_PIN_40_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(40) | 1) +-#define MT8365_PIN_40_UTXD2__FUNC_URXD2 (MTK_PIN_NO(40) | 2) +-#define MT8365_PIN_40_UTXD2__FUNC_URTS1 (MTK_PIN_NO(40) | 3) +-#define MT8365_PIN_40_UTXD2__FUNC_USB_DRVVBUS (MTK_PIN_NO(40) | 4) +-#define MT8365_PIN_40_UTXD2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(40) | 5) +-#define MT8365_PIN_40_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(40) | 6) +-#define MT8365_PIN_40_UTXD2__FUNC_DSP_UTXD0 (MTK_PIN_NO(40) | 7) +- +-#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +-#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(41) | 1) +-#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(41) | 2) +- +-#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +-#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(42) | 1) +-#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(42) | 2) +- +-#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +-#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(43) | 1) +- +-#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +-#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(44) | 1) +- +-#define MT8365_PIN_45_RTC32K_CK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +-#define MT8365_PIN_45_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(45) | 1) +- +-#define MT8365_PIN_46_WATCHDOG__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +-#define MT8365_PIN_46_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(46) | 1) +- +-#define MT8365_PIN_47_SRCLKENA0__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +-#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA0 (MTK_PIN_NO(47) | 1) +-#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA1 (MTK_PIN_NO(47) | 2) +- +-#define MT8365_PIN_48_SRCLKENA1__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +-#define MT8365_PIN_48_SRCLKENA1__FUNC_SRCLKENA1 (MTK_PIN_NO(48) | 1) +- +-#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +-#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(49) | 1) +-#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MISO (MTK_PIN_NO(49) | 2) +-#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_I2S1_MCK (MTK_PIN_NO(49) | 3) +- +-#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +-#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(50) | 1) +-#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(50) | 2) +-#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_I2S1_BCK (MTK_PIN_NO(50) | 3) +- +-#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +-#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(51) | 1) +-#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(51) | 2) +-#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_I2S1_LRCK (MTK_PIN_NO(51) | 3) +- +-#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +-#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(52) | 1) +-#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(52) | 2) +-#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_I2S1_DO (MTK_PIN_NO(52) | 3) +- +-#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +-#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO (MTK_PIN_NO(53) | 1) +-#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(53) | 2) +-#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_I2S2_MCK (MTK_PIN_NO(53) | 3) +- +-#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +-#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(54) | 1) +-#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(54) | 2) +-#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_I2S2_BCK (MTK_PIN_NO(54) | 3) +- +-#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +-#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(55) | 1) +-#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(55) | 2) +-#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_I2S2_LRCK (MTK_PIN_NO(55) | 3) +- +-#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +-#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(56) | 1) +-#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(56) | 2) +-#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_I2S2_DI (MTK_PIN_NO(56) | 3) +- +-#define MT8365_PIN_57_SDA0__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +-#define MT8365_PIN_57_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(57) | 1) +- +-#define MT8365_PIN_58_SCL0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +-#define MT8365_PIN_58_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(58) | 1) +- +-#define MT8365_PIN_59_SDA1__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +-#define MT8365_PIN_59_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(59) | 1) +-#define MT8365_PIN_59_SDA1__FUNC_USB_SDA (MTK_PIN_NO(59) | 6) +-#define MT8365_PIN_59_SDA1__FUNC_DBG_SDA (MTK_PIN_NO(59) | 7) +- +-#define MT8365_PIN_60_SCL1__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +-#define MT8365_PIN_60_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(60) | 1) +-#define MT8365_PIN_60_SCL1__FUNC_USB_SCL (MTK_PIN_NO(60) | 6) +-#define MT8365_PIN_60_SCL1__FUNC_DBG_SCL (MTK_PIN_NO(60) | 7) +- +-#define MT8365_PIN_61_SDA2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +-#define MT8365_PIN_61_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(61) | 1) +- +-#define MT8365_PIN_62_SCL2__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +-#define MT8365_PIN_62_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(62) | 1) +- +-#define MT8365_PIN_63_SDA3__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +-#define MT8365_PIN_63_SDA3__FUNC_SDA3_0 (MTK_PIN_NO(63) | 1) +- +-#define MT8365_PIN_64_SCL3__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +-#define MT8365_PIN_64_SCL3__FUNC_SCL3_0 (MTK_PIN_NO(64) | 1) +- +-#define MT8365_PIN_65_CMMCLK0__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +-#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK0 (MTK_PIN_NO(65) | 1) +-#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK1 (MTK_PIN_NO(65) | 2) +-#define MT8365_PIN_65_CMMCLK0__FUNC_DBG_MON_A28 (MTK_PIN_NO(65) | 7) +- +-#define MT8365_PIN_66_CMMCLK1__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +-#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK1 (MTK_PIN_NO(66) | 1) +-#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK0 (MTK_PIN_NO(66) | 2) +-#define MT8365_PIN_66_CMMCLK1__FUNC_DBG_MON_B2 (MTK_PIN_NO(66) | 7) +- +-#define MT8365_PIN_67_CMPCLK__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +-#define MT8365_PIN_67_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(67) | 1) +-#define MT8365_PIN_67_CMPCLK__FUNC_ANT_SEL0 (MTK_PIN_NO(67) | 2) +-#define MT8365_PIN_67_CMPCLK__FUNC_TDM_RX_BCK (MTK_PIN_NO(67) | 4) +-#define MT8365_PIN_67_CMPCLK__FUNC_I2S0_BCK (MTK_PIN_NO(67) | 5) +-#define MT8365_PIN_67_CMPCLK__FUNC_DBG_MON_B3 (MTK_PIN_NO(67) | 7) +- +-#define MT8365_PIN_68_CMDAT0__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +-#define MT8365_PIN_68_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(68) | 1) +-#define MT8365_PIN_68_CMDAT0__FUNC_ANT_SEL1 (MTK_PIN_NO(68) | 2) +-#define MT8365_PIN_68_CMDAT0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(68) | 4) +-#define MT8365_PIN_68_CMDAT0__FUNC_I2S0_LRCK (MTK_PIN_NO(68) | 5) +-#define MT8365_PIN_68_CMDAT0__FUNC_DBG_MON_B4 (MTK_PIN_NO(68) | 7) +- +-#define MT8365_PIN_69_CMDAT1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +-#define MT8365_PIN_69_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(69) | 1) +-#define MT8365_PIN_69_CMDAT1__FUNC_ANT_SEL2 (MTK_PIN_NO(69) | 2) +-#define MT8365_PIN_69_CMDAT1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(69) | 3) +-#define MT8365_PIN_69_CMDAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(69) | 4) +-#define MT8365_PIN_69_CMDAT1__FUNC_I2S0_MCK (MTK_PIN_NO(69) | 5) +-#define MT8365_PIN_69_CMDAT1__FUNC_DBG_MON_B5 (MTK_PIN_NO(69) | 7) +- +-#define MT8365_PIN_70_CMDAT2__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +-#define MT8365_PIN_70_CMDAT2__FUNC_CMDAT2 (MTK_PIN_NO(70) | 1) +-#define MT8365_PIN_70_CMDAT2__FUNC_ANT_SEL3 (MTK_PIN_NO(70) | 2) +-#define MT8365_PIN_70_CMDAT2__FUNC_TDM_RX_DI (MTK_PIN_NO(70) | 4) +-#define MT8365_PIN_70_CMDAT2__FUNC_I2S0_DI (MTK_PIN_NO(70) | 5) +-#define MT8365_PIN_70_CMDAT2__FUNC_DBG_MON_B6 (MTK_PIN_NO(70) | 7) +- +-#define MT8365_PIN_71_CMDAT3__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +-#define MT8365_PIN_71_CMDAT3__FUNC_CMDAT3 (MTK_PIN_NO(71) | 1) +-#define MT8365_PIN_71_CMDAT3__FUNC_ANT_SEL4 (MTK_PIN_NO(71) | 2) +-#define MT8365_PIN_71_CMDAT3__FUNC_DBG_MON_B7 (MTK_PIN_NO(71) | 7) +- +-#define MT8365_PIN_72_CMDAT4__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +-#define MT8365_PIN_72_CMDAT4__FUNC_CMDAT4 (MTK_PIN_NO(72) | 1) +-#define MT8365_PIN_72_CMDAT4__FUNC_ANT_SEL5 (MTK_PIN_NO(72) | 2) +-#define MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK (MTK_PIN_NO(72) | 5) +-#define MT8365_PIN_72_CMDAT4__FUNC_DBG_MON_B8 (MTK_PIN_NO(72) | 7) +- +-#define MT8365_PIN_73_CMDAT5__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +-#define MT8365_PIN_73_CMDAT5__FUNC_CMDAT5 (MTK_PIN_NO(73) | 1) +-#define MT8365_PIN_73_CMDAT5__FUNC_ANT_SEL6 (MTK_PIN_NO(73) | 2) +-#define MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK (MTK_PIN_NO(73) | 5) +-#define MT8365_PIN_73_CMDAT5__FUNC_DBG_MON_B9 (MTK_PIN_NO(73) | 7) +- +-#define MT8365_PIN_74_CMDAT6__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +-#define MT8365_PIN_74_CMDAT6__FUNC_CMDAT6 (MTK_PIN_NO(74) | 1) +-#define MT8365_PIN_74_CMDAT6__FUNC_ANT_SEL7 (MTK_PIN_NO(74) | 2) +-#define MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK (MTK_PIN_NO(74) | 5) +-#define MT8365_PIN_74_CMDAT6__FUNC_DBG_MON_B10 (MTK_PIN_NO(74) | 7) +- +-#define MT8365_PIN_75_CMDAT7__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +-#define MT8365_PIN_75_CMDAT7__FUNC_CMDAT7 (MTK_PIN_NO(75) | 1) +-#define MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO (MTK_PIN_NO(75) | 5) +-#define MT8365_PIN_75_CMDAT7__FUNC_DBG_MON_B11 (MTK_PIN_NO(75) | 7) +- +-#define MT8365_PIN_76_CMDAT8__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +-#define MT8365_PIN_76_CMDAT8__FUNC_CMDAT8 (MTK_PIN_NO(76) | 1) +-#define MT8365_PIN_76_CMDAT8__FUNC_PCM_CLK (MTK_PIN_NO(76) | 5) +-#define MT8365_PIN_76_CMDAT8__FUNC_DBG_MON_A29 (MTK_PIN_NO(76) | 7) +- +-#define MT8365_PIN_77_CMDAT9__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +-#define MT8365_PIN_77_CMDAT9__FUNC_CMDAT9 (MTK_PIN_NO(77) | 1) +-#define MT8365_PIN_77_CMDAT9__FUNC_PCM_SYNC (MTK_PIN_NO(77) | 5) +-#define MT8365_PIN_77_CMDAT9__FUNC_DBG_MON_A30 (MTK_PIN_NO(77) | 7) +- +-#define MT8365_PIN_78_CMHSYNC__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +-#define MT8365_PIN_78_CMHSYNC__FUNC_CMHSYNC (MTK_PIN_NO(78) | 1) +-#define MT8365_PIN_78_CMHSYNC__FUNC_PCM_RX (MTK_PIN_NO(78) | 5) +-#define MT8365_PIN_78_CMHSYNC__FUNC_DBG_MON_A31 (MTK_PIN_NO(78) | 7) +- +-#define MT8365_PIN_79_CMVSYNC__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +-#define MT8365_PIN_79_CMVSYNC__FUNC_CMVSYNC (MTK_PIN_NO(79) | 1) +-#define MT8365_PIN_79_CMVSYNC__FUNC_PCM_TX (MTK_PIN_NO(79) | 5) +-#define MT8365_PIN_79_CMVSYNC__FUNC_DBG_MON_A32 (MTK_PIN_NO(79) | 7) +- +-#define MT8365_PIN_80_MSDC2_CMD__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +-#define MT8365_PIN_80_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(80) | 1) +-#define MT8365_PIN_80_MSDC2_CMD__FUNC_TDM_TX_LRCK (MTK_PIN_NO(80) | 2) +-#define MT8365_PIN_80_MSDC2_CMD__FUNC_UTXD1 (MTK_PIN_NO(80) | 3) +-#define MT8365_PIN_80_MSDC2_CMD__FUNC_DPI_D19 (MTK_PIN_NO(80) | 4) +-#define MT8365_PIN_80_MSDC2_CMD__FUNC_UDI_TMS_XI (MTK_PIN_NO(80) | 5) +-#define MT8365_PIN_80_MSDC2_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(80) | 6) +- +-#define MT8365_PIN_81_MSDC2_CLK__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +-#define MT8365_PIN_81_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(81) | 1) +-#define MT8365_PIN_81_MSDC2_CLK__FUNC_TDM_TX_BCK (MTK_PIN_NO(81) | 2) +-#define MT8365_PIN_81_MSDC2_CLK__FUNC_URXD1 (MTK_PIN_NO(81) | 3) +-#define MT8365_PIN_81_MSDC2_CLK__FUNC_DPI_D20 (MTK_PIN_NO(81) | 4) +-#define MT8365_PIN_81_MSDC2_CLK__FUNC_UDI_TCK_XI (MTK_PIN_NO(81) | 5) +-#define MT8365_PIN_81_MSDC2_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(81) | 6) +- +-#define MT8365_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +-#define MT8365_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1) +-#define MT8365_PIN_82_MSDC2_DAT0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(82) | 2) +-#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UTXD2 (MTK_PIN_NO(82) | 3) +-#define MT8365_PIN_82_MSDC2_DAT0__FUNC_DPI_D21 (MTK_PIN_NO(82) | 4) +-#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UDI_TDI_XI (MTK_PIN_NO(82) | 5) +-#define MT8365_PIN_82_MSDC2_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(82) | 6) +- +-#define MT8365_PIN_83_MSDC2_DAT1__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +-#define MT8365_PIN_83_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(83) | 1) +-#define MT8365_PIN_83_MSDC2_DAT1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(83) | 2) +-#define MT8365_PIN_83_MSDC2_DAT1__FUNC_URXD2 (MTK_PIN_NO(83) | 3) +-#define MT8365_PIN_83_MSDC2_DAT1__FUNC_DPI_D22 (MTK_PIN_NO(83) | 4) +-#define MT8365_PIN_83_MSDC2_DAT1__FUNC_UDI_TDO (MTK_PIN_NO(83) | 5) +-#define MT8365_PIN_83_MSDC2_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(83) | 6) +- +-#define MT8365_PIN_84_MSDC2_DAT2__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +-#define MT8365_PIN_84_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(84) | 1) +-#define MT8365_PIN_84_MSDC2_DAT2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(84) | 2) +-#define MT8365_PIN_84_MSDC2_DAT2__FUNC_PWM_A (MTK_PIN_NO(84) | 3) +-#define MT8365_PIN_84_MSDC2_DAT2__FUNC_DPI_D23 (MTK_PIN_NO(84) | 4) +-#define MT8365_PIN_84_MSDC2_DAT2__FUNC_UDI_NTRST_XI (MTK_PIN_NO(84) | 5) +-#define MT8365_PIN_84_MSDC2_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(84) | 6) +- +-#define MT8365_PIN_85_MSDC2_DAT3__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +-#define MT8365_PIN_85_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(85) | 1) +-#define MT8365_PIN_85_MSDC2_DAT3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(85) | 2) +-#define MT8365_PIN_85_MSDC2_DAT3__FUNC_PWM_B (MTK_PIN_NO(85) | 3) +-#define MT8365_PIN_85_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(85) | 5) +- +-#define MT8365_PIN_86_MSDC2_DSL__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +-#define MT8365_PIN_86_MSDC2_DSL__FUNC_MSDC2_DSL (MTK_PIN_NO(86) | 1) +-#define MT8365_PIN_86_MSDC2_DSL__FUNC_TDM_TX_MCK (MTK_PIN_NO(86) | 2) +-#define MT8365_PIN_86_MSDC2_DSL__FUNC_PWM_C (MTK_PIN_NO(86) | 3) +- +-#define MT8365_PIN_87_MSDC1_CMD__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +-#define MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(87) | 1) +-#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(87) | 2) +-#define MT8365_PIN_87_MSDC1_CMD__FUNC_DFD_TMS_XI (MTK_PIN_NO(87) | 3) +-#define MT8365_PIN_87_MSDC1_CMD__FUNC_APU_JTAG_TMS (MTK_PIN_NO(87) | 4) +-#define MT8365_PIN_87_MSDC1_CMD__FUNC_MCU_SPM_TMS (MTK_PIN_NO(87) | 5) +-#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_DSP_JMS (MTK_PIN_NO(87) | 6) +-#define MT8365_PIN_87_MSDC1_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(87) | 7) +- +-#define MT8365_PIN_88_MSDC1_CLK__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +-#define MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(88) | 1) +-#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(88) | 2) +-#define MT8365_PIN_88_MSDC1_CLK__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 3) +-#define MT8365_PIN_88_MSDC1_CLK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(88) | 4) +-#define MT8365_PIN_88_MSDC1_CLK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(88) | 5) +-#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(88) | 6) +-#define MT8365_PIN_88_MSDC1_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(88) | 7) +- +-#define MT8365_PIN_89_MSDC1_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +-#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(89) | 1) +-#define MT8365_PIN_89_MSDC1_DAT0__FUNC_PWM_C (MTK_PIN_NO(89) | 2) +-#define MT8365_PIN_89_MSDC1_DAT0__FUNC_DFD_TDI_XI (MTK_PIN_NO(89) | 3) +-#define MT8365_PIN_89_MSDC1_DAT0__FUNC_APU_JTAG_TDI (MTK_PIN_NO(89) | 4) +-#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MCU_SPM_TDI (MTK_PIN_NO(89) | 5) +-#define MT8365_PIN_89_MSDC1_DAT0__FUNC_CONN_DSP_JDI (MTK_PIN_NO(89) | 6) +-#define MT8365_PIN_89_MSDC1_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(89) | 7) +- +-#define MT8365_PIN_90_MSDC1_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +-#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(90) | 1) +-#define MT8365_PIN_90_MSDC1_DAT1__FUNC_SPDIF_IN (MTK_PIN_NO(90) | 2) +-#define MT8365_PIN_90_MSDC1_DAT1__FUNC_DFD_TDO (MTK_PIN_NO(90) | 3) +-#define MT8365_PIN_90_MSDC1_DAT1__FUNC_APU_JTAG_TDO (MTK_PIN_NO(90) | 4) +-#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MCU_SPM_TDO (MTK_PIN_NO(90) | 5) +-#define MT8365_PIN_90_MSDC1_DAT1__FUNC_CONN_DSP_JDO (MTK_PIN_NO(90) | 6) +-#define MT8365_PIN_90_MSDC1_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(90) | 7) +- +-#define MT8365_PIN_91_MSDC1_DAT2__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +-#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(91) | 1) +-#define MT8365_PIN_91_MSDC1_DAT2__FUNC_SPDIF_OUT (MTK_PIN_NO(91) | 2) +-#define MT8365_PIN_91_MSDC1_DAT2__FUNC_DFD_NTRST_XI (MTK_PIN_NO(91) | 3) +-#define MT8365_PIN_91_MSDC1_DAT2__FUNC_APU_JTAG_TRST (MTK_PIN_NO(91) | 4) +-#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(91) | 5) +-#define MT8365_PIN_91_MSDC1_DAT2__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(91) | 6) +-#define MT8365_PIN_91_MSDC1_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(91) | 7) +- +-#define MT8365_PIN_92_MSDC1_DAT3__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +-#define MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(92) | 1) +-#define MT8365_PIN_92_MSDC1_DAT3__FUNC_IRRX (MTK_PIN_NO(92) | 2) +-#define MT8365_PIN_92_MSDC1_DAT3__FUNC_PWM_A (MTK_PIN_NO(92) | 3) +- +-#define MT8365_PIN_93_MSDC0_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +-#define MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(93) | 1) +-#define MT8365_PIN_93_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(93) | 2) +- +-#define MT8365_PIN_94_MSDC0_DAT6__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +-#define MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(94) | 1) +-#define MT8365_PIN_94_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(94) | 2) +- +-#define MT8365_PIN_95_MSDC0_DAT5__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +-#define MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(95) | 1) +-#define MT8365_PIN_95_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(95) | 2) +- +-#define MT8365_PIN_96_MSDC0_DAT4__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +-#define MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(96) | 1) +-#define MT8365_PIN_96_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(96) | 2) +- +-#define MT8365_PIN_97_MSDC0_RSTB__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +-#define MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(97) | 1) +-#define MT8365_PIN_97_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(97) | 2) +- +-#define MT8365_PIN_98_MSDC0_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +-#define MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(98) | 1) +-#define MT8365_PIN_98_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(98) | 2) +- +-#define MT8365_PIN_99_MSDC0_CLK__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +-#define MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(99) | 1) +-#define MT8365_PIN_99_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(99) | 2) +- +-#define MT8365_PIN_100_MSDC0_DAT3__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +-#define MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(100) | 1) +-#define MT8365_PIN_100_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(100) | 2) +- +-#define MT8365_PIN_101_MSDC0_DAT2__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +-#define MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(101) | 1) +-#define MT8365_PIN_101_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(101) | 2) +- +-#define MT8365_PIN_102_MSDC0_DAT1__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +-#define MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(102) | 1) +-#define MT8365_PIN_102_MSDC0_DAT1__FUNC_NDQS (MTK_PIN_NO(102) | 2) +- +-#define MT8365_PIN_103_MSDC0_DAT0__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +-#define MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(103) | 1) +-#define MT8365_PIN_103_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(103) | 2) +- +-#define MT8365_PIN_104_MSDC0_DSL__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +-#define MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(104) | 1) +- +-#define MT8365_PIN_105_NCLE__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +-#define MT8365_PIN_105_NCLE__FUNC_NCLE (MTK_PIN_NO(105) | 1) +-#define MT8365_PIN_105_NCLE__FUNC_TDM_RX_MCK (MTK_PIN_NO(105) | 2) +-#define MT8365_PIN_105_NCLE__FUNC_DBG_MON_B12 (MTK_PIN_NO(105) | 7) +- +-#define MT8365_PIN_106_NCEB1__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +-#define MT8365_PIN_106_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(106) | 1) +-#define MT8365_PIN_106_NCEB1__FUNC_TDM_RX_BCK (MTK_PIN_NO(106) | 2) +-#define MT8365_PIN_106_NCEB1__FUNC_DBG_MON_B13 (MTK_PIN_NO(106) | 7) +- +-#define MT8365_PIN_107_NCEB0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +-#define MT8365_PIN_107_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(107) | 1) +-#define MT8365_PIN_107_NCEB0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(107) | 2) +-#define MT8365_PIN_107_NCEB0__FUNC_DBG_MON_B14 (MTK_PIN_NO(107) | 7) +- +-#define MT8365_PIN_108_NREB__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +-#define MT8365_PIN_108_NREB__FUNC_NREB (MTK_PIN_NO(108) | 1) +-#define MT8365_PIN_108_NREB__FUNC_TDM_RX_DI (MTK_PIN_NO(108) | 2) +-#define MT8365_PIN_108_NREB__FUNC_DBG_MON_B15 (MTK_PIN_NO(108) | 7) +- +-#define MT8365_PIN_109_NRNB__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +-#define MT8365_PIN_109_NRNB__FUNC_NRNB (MTK_PIN_NO(109) | 1) +-#define MT8365_PIN_109_NRNB__FUNC_TSF_IN (MTK_PIN_NO(109) | 2) +-#define MT8365_PIN_109_NRNB__FUNC_DBG_MON_B16 (MTK_PIN_NO(109) | 7) +- +-#define MT8365_PIN_110_PCM_CLK__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +-#define MT8365_PIN_110_PCM_CLK__FUNC_PCM_CLK (MTK_PIN_NO(110) | 1) +-#define MT8365_PIN_110_PCM_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(110) | 2) +-#define MT8365_PIN_110_PCM_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 3) +-#define MT8365_PIN_110_PCM_CLK__FUNC_SPDIF_IN (MTK_PIN_NO(110) | 4) +-#define MT8365_PIN_110_PCM_CLK__FUNC_DPI_D15 (MTK_PIN_NO(110) | 5) +- +-#define MT8365_PIN_111_PCM_SYNC__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +-#define MT8365_PIN_111_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(111) | 1) +-#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(111) | 2) +-#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(111) | 3) +-#define MT8365_PIN_111_PCM_SYNC__FUNC_SPDIF_OUT (MTK_PIN_NO(111) | 4) +-#define MT8365_PIN_111_PCM_SYNC__FUNC_DPI_D16 (MTK_PIN_NO(111) | 5) +- +-#define MT8365_PIN_112_PCM_RX__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +-#define MT8365_PIN_112_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(112) | 1) +-#define MT8365_PIN_112_PCM_RX__FUNC_I2S0_DI (MTK_PIN_NO(112) | 2) +-#define MT8365_PIN_112_PCM_RX__FUNC_I2S3_MCK (MTK_PIN_NO(112) | 3) +-#define MT8365_PIN_112_PCM_RX__FUNC_IRRX (MTK_PIN_NO(112) | 4) +-#define MT8365_PIN_112_PCM_RX__FUNC_DPI_D17 (MTK_PIN_NO(112) | 5) +- +-#define MT8365_PIN_113_PCM_TX__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +-#define MT8365_PIN_113_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(113) | 1) +-#define MT8365_PIN_113_PCM_TX__FUNC_I2S0_MCK (MTK_PIN_NO(113) | 2) +-#define MT8365_PIN_113_PCM_TX__FUNC_I2S3_DO (MTK_PIN_NO(113) | 3) +-#define MT8365_PIN_113_PCM_TX__FUNC_PWM_B (MTK_PIN_NO(113) | 4) +-#define MT8365_PIN_113_PCM_TX__FUNC_DPI_D18 (MTK_PIN_NO(113) | 5) +- +-#define MT8365_PIN_114_I2S_DATA_IN__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +-#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(114) | 1) +-#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S1_DO (MTK_PIN_NO(114) | 2) +-#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S2_DI (MTK_PIN_NO(114) | 3) +-#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(114) | 4) +-#define MT8365_PIN_114_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(114) | 5) +-#define MT8365_PIN_114_I2S_DATA_IN__FUNC_SPDIF_IN (MTK_PIN_NO(114) | 6) +-#define MT8365_PIN_114_I2S_DATA_IN__FUNC_DBG_MON_B17 (MTK_PIN_NO(114) | 7) +- +-#define MT8365_PIN_115_I2S_LRCK__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +-#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(115) | 1) +-#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(115) | 2) +-#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S2_LRCK (MTK_PIN_NO(115) | 3) +-#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(115) | 4) +-#define MT8365_PIN_115_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(115) | 5) +-#define MT8365_PIN_115_I2S_LRCK__FUNC_SPDIF_OUT (MTK_PIN_NO(115) | 6) +-#define MT8365_PIN_115_I2S_LRCK__FUNC_DBG_MON_B18 (MTK_PIN_NO(115) | 7) +- +-#define MT8365_PIN_116_I2S_BCK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +-#define MT8365_PIN_116_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(116) | 1) +-#define MT8365_PIN_116_I2S_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(116) | 2) +-#define MT8365_PIN_116_I2S_BCK__FUNC_I2S2_BCK (MTK_PIN_NO(116) | 3) +-#define MT8365_PIN_116_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(116) | 4) +-#define MT8365_PIN_116_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(116) | 5) +-#define MT8365_PIN_116_I2S_BCK__FUNC_IRRX (MTK_PIN_NO(116) | 6) +-#define MT8365_PIN_116_I2S_BCK__FUNC_DBG_MON_B19 (MTK_PIN_NO(116) | 7) +- +-#define MT8365_PIN_117_DMIC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +-#define MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK (MTK_PIN_NO(117) | 1) +-#define MT8365_PIN_117_DMIC0_CLK__FUNC_I2S2_BCK (MTK_PIN_NO(117) | 2) +-#define MT8365_PIN_117_DMIC0_CLK__FUNC_DBG_MON_B20 (MTK_PIN_NO(117) | 7) +- +-#define MT8365_PIN_118_DMIC0_DAT0__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +-#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DMIC0_DAT0 (MTK_PIN_NO(118) | 1) +-#define MT8365_PIN_118_DMIC0_DAT0__FUNC_I2S2_DI (MTK_PIN_NO(118) | 2) +-#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DBG_MON_B21 (MTK_PIN_NO(118) | 7) +- +-#define MT8365_PIN_119_DMIC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +-#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DMIC0_DAT1 (MTK_PIN_NO(119) | 1) +-#define MT8365_PIN_119_DMIC0_DAT1__FUNC_I2S2_LRCK (MTK_PIN_NO(119) | 2) +-#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DBG_MON_B22 (MTK_PIN_NO(119) | 7) +- +-#define MT8365_PIN_120_DMIC1_CLK__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +-#define MT8365_PIN_120_DMIC1_CLK__FUNC_DMIC1_CLK (MTK_PIN_NO(120) | 1) +-#define MT8365_PIN_120_DMIC1_CLK__FUNC_I2S2_MCK (MTK_PIN_NO(120) | 2) +-#define MT8365_PIN_120_DMIC1_CLK__FUNC_DBG_MON_B23 (MTK_PIN_NO(120) | 7) +- +-#define MT8365_PIN_121_DMIC1_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +-#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DMIC1_DAT0 (MTK_PIN_NO(121) | 1) +-#define MT8365_PIN_121_DMIC1_DAT0__FUNC_I2S1_BCK (MTK_PIN_NO(121) | 2) +-#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DBG_MON_B24 (MTK_PIN_NO(121) | 7) +- +-#define MT8365_PIN_122_DMIC1_DAT1__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +-#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DMIC1_DAT1 (MTK_PIN_NO(122) | 1) +-#define MT8365_PIN_122_DMIC1_DAT1__FUNC_I2S1_LRCK (MTK_PIN_NO(122) | 2) +-#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DBG_MON_B25 (MTK_PIN_NO(122) | 7) +- +-#define MT8365_PIN_123_DMIC2_CLK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +-#define MT8365_PIN_123_DMIC2_CLK__FUNC_DMIC2_CLK (MTK_PIN_NO(123) | 1) +-#define MT8365_PIN_123_DMIC2_CLK__FUNC_I2S1_MCK (MTK_PIN_NO(123) | 2) +-#define MT8365_PIN_123_DMIC2_CLK__FUNC_DBG_MON_B26 (MTK_PIN_NO(123) | 7) +- +-#define MT8365_PIN_124_DMIC2_DAT0__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +-#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DMIC2_DAT0 (MTK_PIN_NO(124) | 1) +-#define MT8365_PIN_124_DMIC2_DAT0__FUNC_I2S1_DO (MTK_PIN_NO(124) | 2) +-#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DBG_MON_B27 (MTK_PIN_NO(124) | 7) +- +-#define MT8365_PIN_125_DMIC2_DAT1__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +-#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DMIC2_DAT1 (MTK_PIN_NO(125) | 1) +-#define MT8365_PIN_125_DMIC2_DAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(125) | 2) +-#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DBG_MON_B28 (MTK_PIN_NO(125) | 7) +- +-#define MT8365_PIN_126_DMIC3_CLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +-#define MT8365_PIN_126_DMIC3_CLK__FUNC_DMIC3_CLK (MTK_PIN_NO(126) | 1) +-#define MT8365_PIN_126_DMIC3_CLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(126) | 2) +- +-#define MT8365_PIN_127_DMIC3_DAT0__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +-#define MT8365_PIN_127_DMIC3_DAT0__FUNC_DMIC3_DAT0 (MTK_PIN_NO(127) | 1) +-#define MT8365_PIN_127_DMIC3_DAT0__FUNC_TDM_RX_DI (MTK_PIN_NO(127) | 2) +- +-#define MT8365_PIN_128_DMIC3_DAT1__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +-#define MT8365_PIN_128_DMIC3_DAT1__FUNC_DMIC3_DAT1 (MTK_PIN_NO(128) | 1) +-#define MT8365_PIN_128_DMIC3_DAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(128) | 2) +-#define MT8365_PIN_128_DMIC3_DAT1__FUNC_VAD_CLK (MTK_PIN_NO(128) | 3) +- +-#define MT8365_PIN_129_TDM_TX_BCK__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +-#define MT8365_PIN_129_TDM_TX_BCK__FUNC_TDM_TX_BCK (MTK_PIN_NO(129) | 1) +-#define MT8365_PIN_129_TDM_TX_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(129) | 2) +-#define MT8365_PIN_129_TDM_TX_BCK__FUNC_ckmon1_ck (MTK_PIN_NO(129) | 3) +- +-#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +-#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_TDM_TX_LRCK (MTK_PIN_NO(130) | 1) +-#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(130) | 2) +-#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_ckmon2_ck (MTK_PIN_NO(130) | 3) +- +-#define MT8365_PIN_131_TDM_TX_MCK__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +-#define MT8365_PIN_131_TDM_TX_MCK__FUNC_TDM_TX_MCK (MTK_PIN_NO(131) | 1) +-#define MT8365_PIN_131_TDM_TX_MCK__FUNC_I2S3_MCK (MTK_PIN_NO(131) | 2) +-#define MT8365_PIN_131_TDM_TX_MCK__FUNC_ckmon3_ck (MTK_PIN_NO(131) | 3) +- +-#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +-#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(132) | 1) +-#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_I2S3_DO (MTK_PIN_NO(132) | 2) +-#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_ckmon4_ck (MTK_PIN_NO(132) | 3) +-#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_DBG_MON_B29 (MTK_PIN_NO(132) | 7) +- +-#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +-#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(133) | 1) +-#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_DBG_MON_B30 (MTK_PIN_NO(133) | 7) +- +-#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +-#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(134) | 1) +-#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_DBG_MON_B31 (MTK_PIN_NO(134) | 7) +- +-#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +-#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(135) | 1) +-#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_DBG_MON_B32 (MTK_PIN_NO(135) | 7) +- +-#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +-#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_CONN_TOP_CLK (MTK_PIN_NO(136) | 1) +- +-#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +-#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_CONN_TOP_DATA (MTK_PIN_NO(137) | 1) +- +-#define MT8365_PIN_138_CONN_HRST_B__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +-#define MT8365_PIN_138_CONN_HRST_B__FUNC_CONN_HRST_B (MTK_PIN_NO(138) | 1) +- +-#define MT8365_PIN_139_CONN_WB_PTA__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +-#define MT8365_PIN_139_CONN_WB_PTA__FUNC_CONN_WB_PTA (MTK_PIN_NO(139) | 1) +- +-#define MT8365_PIN_140_CONN_BT_CLK__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +-#define MT8365_PIN_140_CONN_BT_CLK__FUNC_CONN_BT_CLK (MTK_PIN_NO(140) | 1) +- +-#define MT8365_PIN_141_CONN_BT_DATA__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +-#define MT8365_PIN_141_CONN_BT_DATA__FUNC_CONN_BT_DATA (MTK_PIN_NO(141) | 1) +- +-#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +-#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(142) | 1) +- +-#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +-#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(143) | 1) +- +-#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +-#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(144) | 1) +- +-#endif /* __MT8365_PINFUNC_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/nomadik.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/nomadik.h +deleted file mode 100644 +index fa24565e0009..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/nomadik.h ++++ /dev/null +@@ -1,36 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * nomadik.h +- * +- * Copyright (C) ST-Ericsson SA 2013 +- * Author: Gabriel Fernandez for ST-Ericsson. +- */ +- +-#define INPUT_NOPULL 0 +-#define INPUT_PULLUP 1 +-#define INPUT_PULLDOWN 2 +- +-#define OUTPUT_LOW 0 +-#define OUTPUT_HIGH 1 +-#define DIR_OUTPUT 2 +- +-#define SLPM_DISABLED 0 +-#define SLPM_ENABLED 1 +- +-#define SLPM_INPUT_NOPULL 0 +-#define SLPM_INPUT_PULLUP 1 +-#define SLPM_INPUT_PULLDOWN 2 +-#define SLPM_DIR_INPUT 3 +- +-#define SLPM_OUTPUT_LOW 0 +-#define SLPM_OUTPUT_HIGH 1 +-#define SLPM_DIR_OUTPUT 2 +- +-#define SLPM_WAKEUP_DISABLE 0 +-#define SLPM_WAKEUP_ENABLE 1 +- +-#define GPIOMODE_DISABLED 0 +-#define GPIOMODE_ENABLED 1 +- +-#define SLPM_PDIS_DISABLED 0 +-#define SLPM_PDIS_ENABLED 1 +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/omap.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/omap.h +deleted file mode 100644 +index f48245ff87e5..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/omap.h ++++ /dev/null +@@ -1,92 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for OMAP pinctrl bindings. +- * +- * Copyright (C) 2009 Nokia +- * Copyright (C) 2009-2010 Texas Instruments +- */ +- +-#ifndef _DT_BINDINGS_PINCTRL_OMAP_H +-#define _DT_BINDINGS_PINCTRL_OMAP_H +- +-/* 34xx mux mode options for each pin. See TRM for options */ +-#define MUX_MODE0 0 +-#define MUX_MODE1 1 +-#define MUX_MODE2 2 +-#define MUX_MODE3 3 +-#define MUX_MODE4 4 +-#define MUX_MODE5 5 +-#define MUX_MODE6 6 +-#define MUX_MODE7 7 +- +-/* 24xx/34xx mux bit defines */ +-#define PULL_ENA (1 << 3) +-#define PULL_UP (1 << 4) +-#define ALTELECTRICALSEL (1 << 5) +- +-/* omap3/4/5 specific mux bit defines */ +-#define INPUT_EN (1 << 8) +-#define OFF_EN (1 << 9) +-#define OFFOUT_EN (1 << 10) +-#define OFFOUT_VAL (1 << 11) +-#define OFF_PULL_EN (1 << 12) +-#define OFF_PULL_UP (1 << 13) +-#define WAKEUP_EN (1 << 14) +-#define WAKEUP_EVENT (1 << 15) +- +-/* Active pin states */ +-#define PIN_OUTPUT 0 +-#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) +-#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA) +-#define PIN_INPUT INPUT_EN +-#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) +-#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) +- +-/* Off mode states */ +-#define PIN_OFF_NONE 0 +-#define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL) +-#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN) +-#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFFOUT_EN | OFF_PULL_EN | OFF_PULL_UP) +-#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFFOUT_EN | OFF_PULL_EN) +-#define PIN_OFF_WAKEUPENABLE WAKEUP_EN +- +-/* +- * Macros to allow using the absolute physical address instead of the +- * padconf registers instead of the offset from padconf base. +- */ +-#define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset)) +- +-#define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) +-#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) +-#define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) +-#define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) +-#define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) +-#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) +-#define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) +-#define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) +-#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) (0) +-#define AM33XX_PADCONF(pa, conf, mux) OMAP_IOPAD_OFFSET((pa), 0x0800) (conf) (mux) +- +-/* +- * Macros to allow using the offset from the padconf physical address +- * instead of the offset from padconf base. +- */ +-#define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset)) +- +-#define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) +-#define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) +- +-/* +- * Define some commonly used pins configured by the boards. +- * Note that some boards use alternative pins, so check +- * the schematics before using these. +- */ +-#define OMAP3_UART1_RX 0x152 +-#define OMAP3_UART2_RX 0x14a +-#define OMAP3_UART3_RX 0x16e +-#define OMAP4_UART2_RX 0xdc +-#define OMAP4_UART3_RX 0x104 +-#define OMAP4_UART4_RX 0x11c +- +-#endif +- +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pads-imx8dxl.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pads-imx8dxl.h +deleted file mode 100644 +index b1d7b84c3e0a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pads-imx8dxl.h ++++ /dev/null +@@ -1,639 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright 2019~2020 NXP +- */ +- +-#ifndef _IMX8DXL_PADS_H +-#define _IMX8DXL_PADS_H +- +-/* pin id */ +-#define IMX8DXL_PCIE_CTRL0_PERST_B 0 +-#define IMX8DXL_PCIE_CTRL0_CLKREQ_B 1 +-#define IMX8DXL_PCIE_CTRL0_WAKE_B 2 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 +-#define IMX8DXL_USB_SS3_TC0 4 +-#define IMX8DXL_USB_SS3_TC1 5 +-#define IMX8DXL_USB_SS3_TC2 6 +-#define IMX8DXL_USB_SS3_TC3 7 +-#define IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO 8 +-#define IMX8DXL_EMMC0_CLK 9 +-#define IMX8DXL_EMMC0_CMD 10 +-#define IMX8DXL_EMMC0_DATA0 11 +-#define IMX8DXL_EMMC0_DATA1 12 +-#define IMX8DXL_EMMC0_DATA2 13 +-#define IMX8DXL_EMMC0_DATA3 14 +-#define IMX8DXL_EMMC0_DATA4 15 +-#define IMX8DXL_EMMC0_DATA5 16 +-#define IMX8DXL_EMMC0_DATA6 17 +-#define IMX8DXL_EMMC0_DATA7 18 +-#define IMX8DXL_EMMC0_STROBE 19 +-#define IMX8DXL_EMMC0_RESET_B 20 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 21 +-#define IMX8DXL_USDHC1_RESET_B 22 +-#define IMX8DXL_USDHC1_VSELECT 23 +-#define IMX8DXL_CTL_NAND_RE_P_N 24 +-#define IMX8DXL_USDHC1_WP 25 +-#define IMX8DXL_USDHC1_CD_B 26 +-#define IMX8DXL_CTL_NAND_DQS_P_N 27 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP 28 +-#define IMX8DXL_ENET0_RGMII_TXC 29 +-#define IMX8DXL_ENET0_RGMII_TX_CTL 30 +-#define IMX8DXL_ENET0_RGMII_TXD0 31 +-#define IMX8DXL_ENET0_RGMII_TXD1 32 +-#define IMX8DXL_ENET0_RGMII_TXD2 33 +-#define IMX8DXL_ENET0_RGMII_TXD3 34 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 35 +-#define IMX8DXL_ENET0_RGMII_RXC 36 +-#define IMX8DXL_ENET0_RGMII_RX_CTL 37 +-#define IMX8DXL_ENET0_RGMII_RXD0 38 +-#define IMX8DXL_ENET0_RGMII_RXD1 39 +-#define IMX8DXL_ENET0_RGMII_RXD2 40 +-#define IMX8DXL_ENET0_RGMII_RXD3 41 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 42 +-#define IMX8DXL_ENET0_REFCLK_125M_25M 43 +-#define IMX8DXL_ENET0_MDIO 44 +-#define IMX8DXL_ENET0_MDC 45 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT 46 +-#define IMX8DXL_ENET1_RGMII_TXC 47 +-#define IMX8DXL_ENET1_RGMII_TXD2 48 +-#define IMX8DXL_ENET1_RGMII_TX_CTL 49 +-#define IMX8DXL_ENET1_RGMII_TXD3 50 +-#define IMX8DXL_ENET1_RGMII_RXC 51 +-#define IMX8DXL_ENET1_RGMII_RXD3 52 +-#define IMX8DXL_ENET1_RGMII_RXD2 53 +-#define IMX8DXL_ENET1_RGMII_RXD1 54 +-#define IMX8DXL_ENET1_RGMII_TXD0 55 +-#define IMX8DXL_ENET1_RGMII_TXD1 56 +-#define IMX8DXL_ENET1_RGMII_RXD0 57 +-#define IMX8DXL_ENET1_RGMII_RX_CTL 58 +-#define IMX8DXL_ENET1_REFCLK_125M_25M 59 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB 60 +-#define IMX8DXL_SPI3_SCK 61 +-#define IMX8DXL_SPI3_SDO 62 +-#define IMX8DXL_SPI3_SDI 63 +-#define IMX8DXL_SPI3_CS0 64 +-#define IMX8DXL_SPI3_CS1 65 +-#define IMX8DXL_MCLK_IN1 66 +-#define IMX8DXL_MCLK_IN0 67 +-#define IMX8DXL_MCLK_OUT0 68 +-#define IMX8DXL_UART1_TX 69 +-#define IMX8DXL_UART1_RX 70 +-#define IMX8DXL_UART1_RTS_B 71 +-#define IMX8DXL_UART1_CTS_B 72 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK 73 +-#define IMX8DXL_SPI0_SCK 74 +-#define IMX8DXL_SPI0_SDI 75 +-#define IMX8DXL_SPI0_SDO 76 +-#define IMX8DXL_SPI0_CS1 77 +-#define IMX8DXL_SPI0_CS0 78 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT 79 +-#define IMX8DXL_ADC_IN1 80 +-#define IMX8DXL_ADC_IN0 81 +-#define IMX8DXL_ADC_IN3 82 +-#define IMX8DXL_ADC_IN2 83 +-#define IMX8DXL_ADC_IN5 84 +-#define IMX8DXL_ADC_IN4 85 +-#define IMX8DXL_FLEXCAN0_RX 86 +-#define IMX8DXL_FLEXCAN0_TX 87 +-#define IMX8DXL_FLEXCAN1_RX 88 +-#define IMX8DXL_FLEXCAN1_TX 89 +-#define IMX8DXL_FLEXCAN2_RX 90 +-#define IMX8DXL_FLEXCAN2_TX 91 +-#define IMX8DXL_UART0_RX 92 +-#define IMX8DXL_UART0_TX 93 +-#define IMX8DXL_UART2_TX 94 +-#define IMX8DXL_UART2_RX 95 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH 96 +-#define IMX8DXL_JTAG_TRST_B 97 +-#define IMX8DXL_PMIC_I2C_SCL 98 +-#define IMX8DXL_PMIC_I2C_SDA 99 +-#define IMX8DXL_PMIC_INT_B 100 +-#define IMX8DXL_SCU_GPIO0_00 101 +-#define IMX8DXL_SCU_GPIO0_01 102 +-#define IMX8DXL_SCU_PMIC_STANDBY 103 +-#define IMX8DXL_SCU_BOOT_MODE1 104 +-#define IMX8DXL_SCU_BOOT_MODE0 105 +-#define IMX8DXL_SCU_BOOT_MODE2 106 +-#define IMX8DXL_SNVS_TAMPER_OUT1 107 +-#define IMX8DXL_SNVS_TAMPER_OUT2 108 +-#define IMX8DXL_SNVS_TAMPER_OUT3 109 +-#define IMX8DXL_SNVS_TAMPER_OUT4 110 +-#define IMX8DXL_SNVS_TAMPER_IN0 111 +-#define IMX8DXL_SNVS_TAMPER_IN1 112 +-#define IMX8DXL_SNVS_TAMPER_IN2 113 +-#define IMX8DXL_SNVS_TAMPER_IN3 114 +-#define IMX8DXL_SPI1_SCK 115 +-#define IMX8DXL_SPI1_SDO 116 +-#define IMX8DXL_SPI1_SDI 117 +-#define IMX8DXL_SPI1_CS0 118 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD 119 +-#define IMX8DXL_QSPI0A_DATA1 120 +-#define IMX8DXL_QSPI0A_DATA0 121 +-#define IMX8DXL_QSPI0A_DATA3 122 +-#define IMX8DXL_QSPI0A_DATA2 123 +-#define IMX8DXL_QSPI0A_SS0_B 124 +-#define IMX8DXL_QSPI0A_DQS 125 +-#define IMX8DXL_QSPI0A_SCLK 126 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A 127 +-#define IMX8DXL_QSPI0B_SCLK 128 +-#define IMX8DXL_QSPI0B_DQS 129 +-#define IMX8DXL_QSPI0B_DATA1 130 +-#define IMX8DXL_QSPI0B_DATA0 131 +-#define IMX8DXL_QSPI0B_DATA3 132 +-#define IMX8DXL_QSPI0B_DATA2 133 +-#define IMX8DXL_QSPI0B_SS0_B 134 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B 135 +- +-/* format: */ +-#define IMX8DXL_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8DXL_PCIE_CTRL0_PERST_B 0 +-#define IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8DXL_PCIE_CTRL0_PERST_B 4 +-#define IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO7_IO00 IMX8DXL_PCIE_CTRL0_PERST_B 5 +-#define IMX8DXL_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8DXL_PCIE_CTRL0_CLKREQ_B 0 +-#define IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8DXL_PCIE_CTRL0_CLKREQ_B 4 +-#define IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO7_IO01 IMX8DXL_PCIE_CTRL0_CLKREQ_B 5 +-#define IMX8DXL_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8DXL_PCIE_CTRL0_WAKE_B 0 +-#define IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8DXL_PCIE_CTRL0_WAKE_B 4 +-#define IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO7_IO02 IMX8DXL_PCIE_CTRL0_WAKE_B 5 +-#define IMX8DXL_USB_SS3_TC0_ADMA_I2C1_SCL IMX8DXL_USB_SS3_TC0 0 +-#define IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8DXL_USB_SS3_TC0 1 +-#define IMX8DXL_USB_SS3_TC0_CONN_USB_OTG2_PWR IMX8DXL_USB_SS3_TC0 2 +-#define IMX8DXL_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8DXL_USB_SS3_TC0 4 +-#define IMX8DXL_USB_SS3_TC0_LSIO_GPIO7_IO03 IMX8DXL_USB_SS3_TC0 5 +-#define IMX8DXL_USB_SS3_TC1_ADMA_I2C1_SCL IMX8DXL_USB_SS3_TC1 0 +-#define IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8DXL_USB_SS3_TC1 1 +-#define IMX8DXL_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8DXL_USB_SS3_TC1 4 +-#define IMX8DXL_USB_SS3_TC1_LSIO_GPIO7_IO04 IMX8DXL_USB_SS3_TC1 5 +-#define IMX8DXL_USB_SS3_TC2_ADMA_I2C1_SDA IMX8DXL_USB_SS3_TC2 0 +-#define IMX8DXL_USB_SS3_TC2_CONN_USB_OTG1_OC IMX8DXL_USB_SS3_TC2 1 +-#define IMX8DXL_USB_SS3_TC2_CONN_USB_OTG2_OC IMX8DXL_USB_SS3_TC2 2 +-#define IMX8DXL_USB_SS3_TC2_LSIO_GPIO4_IO05 IMX8DXL_USB_SS3_TC2 4 +-#define IMX8DXL_USB_SS3_TC2_LSIO_GPIO7_IO05 IMX8DXL_USB_SS3_TC2 5 +-#define IMX8DXL_USB_SS3_TC3_ADMA_I2C1_SDA IMX8DXL_USB_SS3_TC3 0 +-#define IMX8DXL_USB_SS3_TC3_CONN_USB_OTG2_OC IMX8DXL_USB_SS3_TC3 1 +-#define IMX8DXL_USB_SS3_TC3_LSIO_GPIO4_IO06 IMX8DXL_USB_SS3_TC3 4 +-#define IMX8DXL_USB_SS3_TC3_LSIO_GPIO7_IO06 IMX8DXL_USB_SS3_TC3 5 +-#define IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK IMX8DXL_EMMC0_CLK 0 +-#define IMX8DXL_EMMC0_CLK_CONN_NAND_READY_B IMX8DXL_EMMC0_CLK 1 +-#define IMX8DXL_EMMC0_CLK_LSIO_GPIO4_IO07 IMX8DXL_EMMC0_CLK 4 +-#define IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD IMX8DXL_EMMC0_CMD 0 +-#define IMX8DXL_EMMC0_CMD_CONN_NAND_DQS IMX8DXL_EMMC0_CMD 1 +-#define IMX8DXL_EMMC0_CMD_LSIO_GPIO4_IO08 IMX8DXL_EMMC0_CMD 4 +-#define IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 IMX8DXL_EMMC0_DATA0 0 +-#define IMX8DXL_EMMC0_DATA0_CONN_NAND_DATA00 IMX8DXL_EMMC0_DATA0 1 +-#define IMX8DXL_EMMC0_DATA0_LSIO_GPIO4_IO09 IMX8DXL_EMMC0_DATA0 4 +-#define IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 IMX8DXL_EMMC0_DATA1 0 +-#define IMX8DXL_EMMC0_DATA1_CONN_NAND_DATA01 IMX8DXL_EMMC0_DATA1 1 +-#define IMX8DXL_EMMC0_DATA1_LSIO_GPIO4_IO10 IMX8DXL_EMMC0_DATA1 4 +-#define IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 IMX8DXL_EMMC0_DATA2 0 +-#define IMX8DXL_EMMC0_DATA2_CONN_NAND_DATA02 IMX8DXL_EMMC0_DATA2 1 +-#define IMX8DXL_EMMC0_DATA2_LSIO_GPIO4_IO11 IMX8DXL_EMMC0_DATA2 4 +-#define IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 IMX8DXL_EMMC0_DATA3 0 +-#define IMX8DXL_EMMC0_DATA3_CONN_NAND_DATA03 IMX8DXL_EMMC0_DATA3 1 +-#define IMX8DXL_EMMC0_DATA3_LSIO_GPIO4_IO12 IMX8DXL_EMMC0_DATA3 4 +-#define IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 IMX8DXL_EMMC0_DATA4 0 +-#define IMX8DXL_EMMC0_DATA4_CONN_NAND_DATA04 IMX8DXL_EMMC0_DATA4 1 +-#define IMX8DXL_EMMC0_DATA4_LSIO_GPIO4_IO13 IMX8DXL_EMMC0_DATA4 4 +-#define IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 IMX8DXL_EMMC0_DATA5 0 +-#define IMX8DXL_EMMC0_DATA5_CONN_NAND_DATA05 IMX8DXL_EMMC0_DATA5 1 +-#define IMX8DXL_EMMC0_DATA5_LSIO_GPIO4_IO14 IMX8DXL_EMMC0_DATA5 4 +-#define IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 IMX8DXL_EMMC0_DATA6 0 +-#define IMX8DXL_EMMC0_DATA6_CONN_NAND_DATA06 IMX8DXL_EMMC0_DATA6 1 +-#define IMX8DXL_EMMC0_DATA6_LSIO_GPIO4_IO15 IMX8DXL_EMMC0_DATA6 4 +-#define IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 IMX8DXL_EMMC0_DATA7 0 +-#define IMX8DXL_EMMC0_DATA7_CONN_NAND_DATA07 IMX8DXL_EMMC0_DATA7 1 +-#define IMX8DXL_EMMC0_DATA7_LSIO_GPIO4_IO16 IMX8DXL_EMMC0_DATA7 4 +-#define IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE IMX8DXL_EMMC0_STROBE 0 +-#define IMX8DXL_EMMC0_STROBE_CONN_NAND_CLE IMX8DXL_EMMC0_STROBE 1 +-#define IMX8DXL_EMMC0_STROBE_LSIO_GPIO4_IO17 IMX8DXL_EMMC0_STROBE 4 +-#define IMX8DXL_EMMC0_RESET_B_CONN_EMMC0_RESET_B IMX8DXL_EMMC0_RESET_B 0 +-#define IMX8DXL_EMMC0_RESET_B_CONN_NAND_WP_B IMX8DXL_EMMC0_RESET_B 1 +-#define IMX8DXL_EMMC0_RESET_B_LSIO_GPIO4_IO18 IMX8DXL_EMMC0_RESET_B 4 +-#define IMX8DXL_USDHC1_RESET_B_CONN_USDHC1_RESET_B IMX8DXL_USDHC1_RESET_B 0 +-#define IMX8DXL_USDHC1_RESET_B_CONN_NAND_RE_N IMX8DXL_USDHC1_RESET_B 1 +-#define IMX8DXL_USDHC1_RESET_B_ADMA_SPI2_SCK IMX8DXL_USDHC1_RESET_B 2 +-#define IMX8DXL_USDHC1_RESET_B_CONN_NAND_WE_B IMX8DXL_USDHC1_RESET_B 3 +-#define IMX8DXL_USDHC1_RESET_B_LSIO_GPIO4_IO19 IMX8DXL_USDHC1_RESET_B 4 +-#define IMX8DXL_USDHC1_RESET_B_LSIO_GPIO7_IO08 IMX8DXL_USDHC1_RESET_B 5 +-#define IMX8DXL_USDHC1_VSELECT_CONN_USDHC1_VSELECT IMX8DXL_USDHC1_VSELECT 0 +-#define IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_P IMX8DXL_USDHC1_VSELECT 1 +-#define IMX8DXL_USDHC1_VSELECT_ADMA_SPI2_SDO IMX8DXL_USDHC1_VSELECT 2 +-#define IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_B IMX8DXL_USDHC1_VSELECT 3 +-#define IMX8DXL_USDHC1_VSELECT_LSIO_GPIO4_IO20 IMX8DXL_USDHC1_VSELECT 4 +-#define IMX8DXL_USDHC1_VSELECT_LSIO_GPIO7_IO09 IMX8DXL_USDHC1_VSELECT 5 +-#define IMX8DXL_USDHC1_WP_CONN_USDHC1_WP IMX8DXL_USDHC1_WP 0 +-#define IMX8DXL_USDHC1_WP_CONN_NAND_DQS_N IMX8DXL_USDHC1_WP 1 +-#define IMX8DXL_USDHC1_WP_ADMA_SPI2_SDI IMX8DXL_USDHC1_WP 2 +-#define IMX8DXL_USDHC1_WP_CONN_NAND_ALE IMX8DXL_USDHC1_WP 3 +-#define IMX8DXL_USDHC1_WP_LSIO_GPIO4_IO21 IMX8DXL_USDHC1_WP 4 +-#define IMX8DXL_USDHC1_WP_LSIO_GPIO7_IO10 IMX8DXL_USDHC1_WP 5 +-#define IMX8DXL_USDHC1_CD_B_CONN_USDHC1_CD_B IMX8DXL_USDHC1_CD_B 0 +-#define IMX8DXL_USDHC1_CD_B_CONN_NAND_DQS_P IMX8DXL_USDHC1_CD_B 1 +-#define IMX8DXL_USDHC1_CD_B_ADMA_SPI2_CS0 IMX8DXL_USDHC1_CD_B 2 +-#define IMX8DXL_USDHC1_CD_B_CONN_NAND_DQS IMX8DXL_USDHC1_CD_B 3 +-#define IMX8DXL_USDHC1_CD_B_LSIO_GPIO4_IO22 IMX8DXL_USDHC1_CD_B 4 +-#define IMX8DXL_USDHC1_CD_B_LSIO_GPIO7_IO11 IMX8DXL_USDHC1_CD_B 5 +-#define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC IMX8DXL_ENET0_RGMII_TXC 0 +-#define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT IMX8DXL_ENET0_RGMII_TXC 1 +-#define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN IMX8DXL_ENET0_RGMII_TXC 2 +-#define IMX8DXL_ENET0_RGMII_TXC_CONN_NAND_CE1_B IMX8DXL_ENET0_RGMII_TXC 3 +-#define IMX8DXL_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 IMX8DXL_ENET0_RGMII_TXC 4 +-#define IMX8DXL_ENET0_RGMII_TXC_CONN_USDHC2_CLK IMX8DXL_ENET0_RGMII_TXC 5 +-#define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL IMX8DXL_ENET0_RGMII_TX_CTL 0 +-#define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B IMX8DXL_ENET0_RGMII_TX_CTL 3 +-#define IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 IMX8DXL_ENET0_RGMII_TX_CTL 4 +-#define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC2_CMD IMX8DXL_ENET0_RGMII_TX_CTL 5 +-#define IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 IMX8DXL_ENET0_RGMII_TXD0 0 +-#define IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT IMX8DXL_ENET0_RGMII_TXD0 3 +-#define IMX8DXL_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 IMX8DXL_ENET0_RGMII_TXD0 4 +-#define IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC2_DATA0 IMX8DXL_ENET0_RGMII_TXD0 5 +-#define IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 IMX8DXL_ENET0_RGMII_TXD1 0 +-#define IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC1_WP IMX8DXL_ENET0_RGMII_TXD1 3 +-#define IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 IMX8DXL_ENET0_RGMII_TXD1 4 +-#define IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC2_DATA1 IMX8DXL_ENET0_RGMII_TXD1 5 +-#define IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 IMX8DXL_ENET0_RGMII_TXD2 0 +-#define IMX8DXL_ENET0_RGMII_TXD2_CONN_NAND_CE0_B IMX8DXL_ENET0_RGMII_TXD2 2 +-#define IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B IMX8DXL_ENET0_RGMII_TXD2 3 +-#define IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 IMX8DXL_ENET0_RGMII_TXD2 4 +-#define IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC2_DATA2 IMX8DXL_ENET0_RGMII_TXD2 5 +-#define IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 IMX8DXL_ENET0_RGMII_TXD3 0 +-#define IMX8DXL_ENET0_RGMII_TXD3_CONN_NAND_RE_B IMX8DXL_ENET0_RGMII_TXD3 2 +-#define IMX8DXL_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 IMX8DXL_ENET0_RGMII_TXD3 4 +-#define IMX8DXL_ENET0_RGMII_TXD3_CONN_USDHC2_DATA3 IMX8DXL_ENET0_RGMII_TXD3 5 +-#define IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC IMX8DXL_ENET0_RGMII_RXC 0 +-#define IMX8DXL_ENET0_RGMII_RXC_CONN_NAND_WE_B IMX8DXL_ENET0_RGMII_RXC 2 +-#define IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK IMX8DXL_ENET0_RGMII_RXC 3 +-#define IMX8DXL_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 IMX8DXL_ENET0_RGMII_RXC 4 +-#define IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL IMX8DXL_ENET0_RGMII_RX_CTL 0 +-#define IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD IMX8DXL_ENET0_RGMII_RX_CTL 3 +-#define IMX8DXL_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 IMX8DXL_ENET0_RGMII_RX_CTL 4 +-#define IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 IMX8DXL_ENET0_RGMII_RXD0 0 +-#define IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 IMX8DXL_ENET0_RGMII_RXD0 3 +-#define IMX8DXL_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 IMX8DXL_ENET0_RGMII_RXD0 4 +-#define IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 IMX8DXL_ENET0_RGMII_RXD1 0 +-#define IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 IMX8DXL_ENET0_RGMII_RXD1 3 +-#define IMX8DXL_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 IMX8DXL_ENET0_RGMII_RXD1 4 +-#define IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 IMX8DXL_ENET0_RGMII_RXD2 0 +-#define IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER IMX8DXL_ENET0_RGMII_RXD2 1 +-#define IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 IMX8DXL_ENET0_RGMII_RXD2 3 +-#define IMX8DXL_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 IMX8DXL_ENET0_RGMII_RXD2 4 +-#define IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 IMX8DXL_ENET0_RGMII_RXD3 0 +-#define IMX8DXL_ENET0_RGMII_RXD3_CONN_NAND_ALE IMX8DXL_ENET0_RGMII_RXD3 2 +-#define IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 IMX8DXL_ENET0_RGMII_RXD3 3 +-#define IMX8DXL_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 IMX8DXL_ENET0_RGMII_RXD3 4 +-#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M IMX8DXL_ENET0_REFCLK_125M_25M 0 +-#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS IMX8DXL_ENET0_REFCLK_125M_25M 1 +-#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_EQOS_PPS_IN IMX8DXL_ENET0_REFCLK_125M_25M 2 +-#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_EQOS_PPS_OUT IMX8DXL_ENET0_REFCLK_125M_25M 3 +-#define IMX8DXL_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 IMX8DXL_ENET0_REFCLK_125M_25M 4 +-#define IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO IMX8DXL_ENET0_MDIO 0 +-#define IMX8DXL_ENET0_MDIO_ADMA_I2C3_SDA IMX8DXL_ENET0_MDIO 1 +-#define IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO IMX8DXL_ENET0_MDIO 2 +-#define IMX8DXL_ENET0_MDIO_LSIO_GPIO5_IO10 IMX8DXL_ENET0_MDIO 4 +-#define IMX8DXL_ENET0_MDIO_LSIO_GPIO7_IO16 IMX8DXL_ENET0_MDIO 5 +-#define IMX8DXL_ENET0_MDC_CONN_ENET0_MDC IMX8DXL_ENET0_MDC 0 +-#define IMX8DXL_ENET0_MDC_ADMA_I2C3_SCL IMX8DXL_ENET0_MDC 1 +-#define IMX8DXL_ENET0_MDC_CONN_EQOS_MDC IMX8DXL_ENET0_MDC 2 +-#define IMX8DXL_ENET0_MDC_LSIO_GPIO5_IO11 IMX8DXL_ENET0_MDC 4 +-#define IMX8DXL_ENET0_MDC_LSIO_GPIO7_IO17 IMX8DXL_ENET0_MDC 5 +-#define IMX8DXL_ENET1_RGMII_TXC_LSIO_GPIO0_IO00 IMX8DXL_ENET1_RGMII_TXC 0 +-#define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RCLK50M_OUT IMX8DXL_ENET1_RGMII_TXC 1 +-#define IMX8DXL_ENET1_RGMII_TXC_ADMA_LCDIF_D00 IMX8DXL_ENET1_RGMII_TXC 2 +-#define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC IMX8DXL_ENET1_RGMII_TXC 3 +-#define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RCLK50M_IN IMX8DXL_ENET1_RGMII_TXC 4 +-#define IMX8DXL_ENET1_RGMII_TXD2_ADMA_LCDIF_D01 IMX8DXL_ENET1_RGMII_TXD2 2 +-#define IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 IMX8DXL_ENET1_RGMII_TXD2 3 +-#define IMX8DXL_ENET1_RGMII_TXD2_LSIO_GPIO0_IO01 IMX8DXL_ENET1_RGMII_TXD2 4 +-#define IMX8DXL_ENET1_RGMII_TX_CTL_ADMA_LCDIF_D02 IMX8DXL_ENET1_RGMII_TX_CTL 2 +-#define IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL IMX8DXL_ENET1_RGMII_TX_CTL 3 +-#define IMX8DXL_ENET1_RGMII_TX_CTL_LSIO_GPIO0_IO02 IMX8DXL_ENET1_RGMII_TX_CTL 4 +-#define IMX8DXL_ENET1_RGMII_TXD3_ADMA_LCDIF_D03 IMX8DXL_ENET1_RGMII_TXD3 2 +-#define IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 IMX8DXL_ENET1_RGMII_TXD3 3 +-#define IMX8DXL_ENET1_RGMII_TXD3_LSIO_GPIO0_IO03 IMX8DXL_ENET1_RGMII_TXD3 4 +-#define IMX8DXL_ENET1_RGMII_RXC_ADMA_LCDIF_D04 IMX8DXL_ENET1_RGMII_RXC 2 +-#define IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC IMX8DXL_ENET1_RGMII_RXC 3 +-#define IMX8DXL_ENET1_RGMII_RXC_LSIO_GPIO0_IO04 IMX8DXL_ENET1_RGMII_RXC 4 +-#define IMX8DXL_ENET1_RGMII_RXD3_ADMA_LCDIF_D05 IMX8DXL_ENET1_RGMII_RXD3 2 +-#define IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 IMX8DXL_ENET1_RGMII_RXD3 3 +-#define IMX8DXL_ENET1_RGMII_RXD3_LSIO_GPIO0_IO05 IMX8DXL_ENET1_RGMII_RXD3 4 +-#define IMX8DXL_ENET1_RGMII_RXD2_ADMA_LCDIF_D06 IMX8DXL_ENET1_RGMII_RXD2 2 +-#define IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 IMX8DXL_ENET1_RGMII_RXD2 3 +-#define IMX8DXL_ENET1_RGMII_RXD2_LSIO_GPIO0_IO06 IMX8DXL_ENET1_RGMII_RXD2 4 +-#define IMX8DXL_ENET1_RGMII_RXD2_LSIO_GPIO6_IO00 IMX8DXL_ENET1_RGMII_RXD2 5 +-#define IMX8DXL_ENET1_RGMII_RXD1_ADMA_LCDIF_D07 IMX8DXL_ENET1_RGMII_RXD1 2 +-#define IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 IMX8DXL_ENET1_RGMII_RXD1 3 +-#define IMX8DXL_ENET1_RGMII_RXD1_LSIO_GPIO0_IO07 IMX8DXL_ENET1_RGMII_RXD1 4 +-#define IMX8DXL_ENET1_RGMII_RXD1_LSIO_GPIO6_IO01 IMX8DXL_ENET1_RGMII_RXD1 5 +-#define IMX8DXL_ENET1_RGMII_TXD0_ADMA_LCDIF_D08 IMX8DXL_ENET1_RGMII_TXD0 2 +-#define IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 IMX8DXL_ENET1_RGMII_TXD0 3 +-#define IMX8DXL_ENET1_RGMII_TXD0_LSIO_GPIO0_IO08 IMX8DXL_ENET1_RGMII_TXD0 4 +-#define IMX8DXL_ENET1_RGMII_TXD0_LSIO_GPIO6_IO02 IMX8DXL_ENET1_RGMII_TXD0 5 +-#define IMX8DXL_ENET1_RGMII_TXD1_ADMA_LCDIF_D09 IMX8DXL_ENET1_RGMII_TXD1 2 +-#define IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 IMX8DXL_ENET1_RGMII_TXD1 3 +-#define IMX8DXL_ENET1_RGMII_TXD1_LSIO_GPIO0_IO09 IMX8DXL_ENET1_RGMII_TXD1 4 +-#define IMX8DXL_ENET1_RGMII_TXD1_LSIO_GPIO6_IO03 IMX8DXL_ENET1_RGMII_TXD1 5 +-#define IMX8DXL_ENET1_RGMII_RXD0_ADMA_SPDIF0_RX IMX8DXL_ENET1_RGMII_RXD0 0 +-#define IMX8DXL_ENET1_RGMII_RXD0_ADMA_MQS_R IMX8DXL_ENET1_RGMII_RXD0 1 +-#define IMX8DXL_ENET1_RGMII_RXD0_ADMA_LCDIF_D10 IMX8DXL_ENET1_RGMII_RXD0 2 +-#define IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 IMX8DXL_ENET1_RGMII_RXD0 3 +-#define IMX8DXL_ENET1_RGMII_RXD0_LSIO_GPIO0_IO10 IMX8DXL_ENET1_RGMII_RXD0 4 +-#define IMX8DXL_ENET1_RGMII_RXD0_LSIO_GPIO6_IO04 IMX8DXL_ENET1_RGMII_RXD0 5 +-#define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_SPDIF0_TX IMX8DXL_ENET1_RGMII_RX_CTL 0 +-#define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_MQS_L IMX8DXL_ENET1_RGMII_RX_CTL 1 +-#define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_LCDIF_D11 IMX8DXL_ENET1_RGMII_RX_CTL 2 +-#define IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL IMX8DXL_ENET1_RGMII_RX_CTL 3 +-#define IMX8DXL_ENET1_RGMII_RX_CTL_LSIO_GPIO0_IO11 IMX8DXL_ENET1_RGMII_RX_CTL 4 +-#define IMX8DXL_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO05 IMX8DXL_ENET1_RGMII_RX_CTL 5 +-#define IMX8DXL_ENET1_REFCLK_125M_25M_ADMA_SPDIF0_EXT_CLK IMX8DXL_ENET1_REFCLK_125M_25M 0 +-#define IMX8DXL_ENET1_REFCLK_125M_25M_ADMA_LCDIF_D12 IMX8DXL_ENET1_REFCLK_125M_25M 2 +-#define IMX8DXL_ENET1_REFCLK_125M_25M_CONN_EQOS_REFCLK_125M_25M IMX8DXL_ENET1_REFCLK_125M_25M 3 +-#define IMX8DXL_ENET1_REFCLK_125M_25M_LSIO_GPIO0_IO12 IMX8DXL_ENET1_REFCLK_125M_25M 4 +-#define IMX8DXL_ENET1_REFCLK_125M_25M_LSIO_GPIO6_IO06 IMX8DXL_ENET1_REFCLK_125M_25M 5 +-#define IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK IMX8DXL_SPI3_SCK 0 +-#define IMX8DXL_SPI3_SCK_ADMA_LCDIF_D13 IMX8DXL_SPI3_SCK 2 +-#define IMX8DXL_SPI3_SCK_LSIO_GPIO0_IO13 IMX8DXL_SPI3_SCK 4 +-#define IMX8DXL_SPI3_SCK_ADMA_LCDIF_D00 IMX8DXL_SPI3_SCK 5 +-#define IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO IMX8DXL_SPI3_SDO 0 +-#define IMX8DXL_SPI3_SDO_ADMA_LCDIF_D14 IMX8DXL_SPI3_SDO 2 +-#define IMX8DXL_SPI3_SDO_LSIO_GPIO0_IO14 IMX8DXL_SPI3_SDO 4 +-#define IMX8DXL_SPI3_SDO_ADMA_LCDIF_D01 IMX8DXL_SPI3_SDO 5 +-#define IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI IMX8DXL_SPI3_SDI 0 +-#define IMX8DXL_SPI3_SDI_ADMA_LCDIF_D15 IMX8DXL_SPI3_SDI 2 +-#define IMX8DXL_SPI3_SDI_LSIO_GPIO0_IO15 IMX8DXL_SPI3_SDI 4 +-#define IMX8DXL_SPI3_SDI_ADMA_LCDIF_D02 IMX8DXL_SPI3_SDI 5 +-#define IMX8DXL_SPI3_CS0_ADMA_SPI3_CS0 IMX8DXL_SPI3_CS0 0 +-#define IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 IMX8DXL_SPI3_CS0 1 +-#define IMX8DXL_SPI3_CS0_ADMA_LCDIF_HSYNC IMX8DXL_SPI3_CS0 2 +-#define IMX8DXL_SPI3_CS0_LSIO_GPIO0_IO16 IMX8DXL_SPI3_CS0 4 +-#define IMX8DXL_SPI3_CS0_ADMA_LCDIF_CS IMX8DXL_SPI3_CS0 5 +-#define IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 IMX8DXL_SPI3_CS1 0 +-#define IMX8DXL_SPI3_CS1_ADMA_I2C3_SCL IMX8DXL_SPI3_CS1 1 +-#define IMX8DXL_SPI3_CS1_ADMA_LCDIF_RESET IMX8DXL_SPI3_CS1 2 +-#define IMX8DXL_SPI3_CS1_ADMA_SPI2_CS0 IMX8DXL_SPI3_CS1 3 +-#define IMX8DXL_SPI3_CS1_ADMA_LCDIF_D16 IMX8DXL_SPI3_CS1 4 +-#define IMX8DXL_SPI3_CS1_ADMA_LCDIF_RD_E IMX8DXL_SPI3_CS1 5 +-#define IMX8DXL_MCLK_IN1_ADMA_ACM_MCLK_IN1 IMX8DXL_MCLK_IN1 0 +-#define IMX8DXL_MCLK_IN1_ADMA_I2C3_SDA IMX8DXL_MCLK_IN1 1 +-#define IMX8DXL_MCLK_IN1_ADMA_LCDIF_EN IMX8DXL_MCLK_IN1 2 +-#define IMX8DXL_MCLK_IN1_ADMA_SPI2_SCK IMX8DXL_MCLK_IN1 3 +-#define IMX8DXL_MCLK_IN1_ADMA_LCDIF_D17 IMX8DXL_MCLK_IN1 4 +-#define IMX8DXL_MCLK_IN1_ADMA_LCDIF_D03 IMX8DXL_MCLK_IN1 5 +-#define IMX8DXL_MCLK_IN0_ADMA_ACM_MCLK_IN0 IMX8DXL_MCLK_IN0 0 +-#define IMX8DXL_MCLK_IN0_ADMA_LCDIF_VSYNC IMX8DXL_MCLK_IN0 2 +-#define IMX8DXL_MCLK_IN0_ADMA_SPI2_SDI IMX8DXL_MCLK_IN0 3 +-#define IMX8DXL_MCLK_IN0_LSIO_GPIO0_IO19 IMX8DXL_MCLK_IN0 4 +-#define IMX8DXL_MCLK_IN0_ADMA_LCDIF_RS IMX8DXL_MCLK_IN0 5 +-#define IMX8DXL_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 IMX8DXL_MCLK_OUT0 0 +-#define IMX8DXL_MCLK_OUT0_ADMA_LCDIF_CLK IMX8DXL_MCLK_OUT0 2 +-#define IMX8DXL_MCLK_OUT0_ADMA_SPI2_SDO IMX8DXL_MCLK_OUT0 3 +-#define IMX8DXL_MCLK_OUT0_LSIO_GPIO0_IO20 IMX8DXL_MCLK_OUT0 4 +-#define IMX8DXL_MCLK_OUT0_ADMA_LCDIF_WR_RWN IMX8DXL_MCLK_OUT0 5 +-#define IMX8DXL_UART1_TX_ADMA_UART1_TX IMX8DXL_UART1_TX 0 +-#define IMX8DXL_UART1_TX_LSIO_PWM0_OUT IMX8DXL_UART1_TX 1 +-#define IMX8DXL_UART1_TX_LSIO_GPT0_CAPTURE IMX8DXL_UART1_TX 2 +-#define IMX8DXL_UART1_TX_LSIO_GPIO0_IO21 IMX8DXL_UART1_TX 4 +-#define IMX8DXL_UART1_TX_ADMA_LCDIF_D04 IMX8DXL_UART1_TX 5 +-#define IMX8DXL_UART1_RX_ADMA_UART1_RX IMX8DXL_UART1_RX 0 +-#define IMX8DXL_UART1_RX_LSIO_PWM1_OUT IMX8DXL_UART1_RX 1 +-#define IMX8DXL_UART1_RX_LSIO_GPT0_COMPARE IMX8DXL_UART1_RX 2 +-#define IMX8DXL_UART1_RX_LSIO_GPT1_CLK IMX8DXL_UART1_RX 3 +-#define IMX8DXL_UART1_RX_LSIO_GPIO0_IO22 IMX8DXL_UART1_RX 4 +-#define IMX8DXL_UART1_RX_ADMA_LCDIF_D05 IMX8DXL_UART1_RX 5 +-#define IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B IMX8DXL_UART1_RTS_B 0 +-#define IMX8DXL_UART1_RTS_B_LSIO_PWM2_OUT IMX8DXL_UART1_RTS_B 1 +-#define IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D16 IMX8DXL_UART1_RTS_B 2 +-#define IMX8DXL_UART1_RTS_B_LSIO_GPT1_CAPTURE IMX8DXL_UART1_RTS_B 3 +-#define IMX8DXL_UART1_RTS_B_LSIO_GPT0_CLK IMX8DXL_UART1_RTS_B 4 +-#define IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D06 IMX8DXL_UART1_RTS_B 5 +-#define IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B IMX8DXL_UART1_CTS_B 0 +-#define IMX8DXL_UART1_CTS_B_LSIO_PWM3_OUT IMX8DXL_UART1_CTS_B 1 +-#define IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D17 IMX8DXL_UART1_CTS_B 2 +-#define IMX8DXL_UART1_CTS_B_LSIO_GPT1_COMPARE IMX8DXL_UART1_CTS_B 3 +-#define IMX8DXL_UART1_CTS_B_LSIO_GPIO0_IO24 IMX8DXL_UART1_CTS_B 4 +-#define IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D07 IMX8DXL_UART1_CTS_B 5 +-#define IMX8DXL_SPI0_SCK_ADMA_SPI0_SCK IMX8DXL_SPI0_SCK 0 +-#define IMX8DXL_SPI0_SCK_ADMA_SAI0_TXC IMX8DXL_SPI0_SCK 1 +-#define IMX8DXL_SPI0_SCK_M40_I2C0_SCL IMX8DXL_SPI0_SCK 2 +-#define IMX8DXL_SPI0_SCK_M40_GPIO0_IO00 IMX8DXL_SPI0_SCK 3 +-#define IMX8DXL_SPI0_SCK_LSIO_GPIO1_IO04 IMX8DXL_SPI0_SCK 4 +-#define IMX8DXL_SPI0_SCK_ADMA_LCDIF_D08 IMX8DXL_SPI0_SCK 5 +-#define IMX8DXL_SPI0_SDI_ADMA_SPI0_SDI IMX8DXL_SPI0_SDI 0 +-#define IMX8DXL_SPI0_SDI_ADMA_SAI0_TXD IMX8DXL_SPI0_SDI 1 +-#define IMX8DXL_SPI0_SDI_M40_TPM0_CH0 IMX8DXL_SPI0_SDI 2 +-#define IMX8DXL_SPI0_SDI_M40_GPIO0_IO02 IMX8DXL_SPI0_SDI 3 +-#define IMX8DXL_SPI0_SDI_LSIO_GPIO1_IO05 IMX8DXL_SPI0_SDI 4 +-#define IMX8DXL_SPI0_SDI_ADMA_LCDIF_D09 IMX8DXL_SPI0_SDI 5 +-#define IMX8DXL_SPI0_SDO_ADMA_SPI0_SDO IMX8DXL_SPI0_SDO 0 +-#define IMX8DXL_SPI0_SDO_ADMA_SAI0_TXFS IMX8DXL_SPI0_SDO 1 +-#define IMX8DXL_SPI0_SDO_M40_I2C0_SDA IMX8DXL_SPI0_SDO 2 +-#define IMX8DXL_SPI0_SDO_M40_GPIO0_IO01 IMX8DXL_SPI0_SDO 3 +-#define IMX8DXL_SPI0_SDO_LSIO_GPIO1_IO06 IMX8DXL_SPI0_SDO 4 +-#define IMX8DXL_SPI0_SDO_ADMA_LCDIF_D10 IMX8DXL_SPI0_SDO 5 +-#define IMX8DXL_SPI0_CS1_ADMA_SPI0_CS1 IMX8DXL_SPI0_CS1 0 +-#define IMX8DXL_SPI0_CS1_ADMA_SAI0_RXC IMX8DXL_SPI0_CS1 1 +-#define IMX8DXL_SPI0_CS1_ADMA_SAI1_TXD IMX8DXL_SPI0_CS1 2 +-#define IMX8DXL_SPI0_CS1_ADMA_LCD_PWM0_OUT IMX8DXL_SPI0_CS1 3 +-#define IMX8DXL_SPI0_CS1_LSIO_GPIO1_IO07 IMX8DXL_SPI0_CS1 4 +-#define IMX8DXL_SPI0_CS1_ADMA_LCDIF_D11 IMX8DXL_SPI0_CS1 5 +-#define IMX8DXL_SPI0_CS0_ADMA_SPI0_CS0 IMX8DXL_SPI0_CS0 0 +-#define IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD IMX8DXL_SPI0_CS0 1 +-#define IMX8DXL_SPI0_CS0_M40_TPM0_CH1 IMX8DXL_SPI0_CS0 2 +-#define IMX8DXL_SPI0_CS0_M40_GPIO0_IO03 IMX8DXL_SPI0_CS0 3 +-#define IMX8DXL_SPI0_CS0_LSIO_GPIO1_IO08 IMX8DXL_SPI0_CS0 4 +-#define IMX8DXL_SPI0_CS0_ADMA_LCDIF_D12 IMX8DXL_SPI0_CS0 5 +-#define IMX8DXL_ADC_IN1_ADMA_ADC_IN1 IMX8DXL_ADC_IN1 0 +-#define IMX8DXL_ADC_IN1_M40_I2C0_SDA IMX8DXL_ADC_IN1 1 +-#define IMX8DXL_ADC_IN1_M40_GPIO0_IO01 IMX8DXL_ADC_IN1 2 +-#define IMX8DXL_ADC_IN1_ADMA_I2C0_SDA IMX8DXL_ADC_IN1 3 +-#define IMX8DXL_ADC_IN1_LSIO_GPIO1_IO09 IMX8DXL_ADC_IN1 4 +-#define IMX8DXL_ADC_IN1_ADMA_LCDIF_D13 IMX8DXL_ADC_IN1 5 +-#define IMX8DXL_ADC_IN0_ADMA_ADC_IN0 IMX8DXL_ADC_IN0 0 +-#define IMX8DXL_ADC_IN0_M40_I2C0_SCL IMX8DXL_ADC_IN0 1 +-#define IMX8DXL_ADC_IN0_M40_GPIO0_IO00 IMX8DXL_ADC_IN0 2 +-#define IMX8DXL_ADC_IN0_ADMA_I2C0_SCL IMX8DXL_ADC_IN0 3 +-#define IMX8DXL_ADC_IN0_LSIO_GPIO1_IO10 IMX8DXL_ADC_IN0 4 +-#define IMX8DXL_ADC_IN0_ADMA_LCDIF_D14 IMX8DXL_ADC_IN0 5 +-#define IMX8DXL_ADC_IN3_ADMA_ADC_IN3 IMX8DXL_ADC_IN3 0 +-#define IMX8DXL_ADC_IN3_M40_UART0_TX IMX8DXL_ADC_IN3 1 +-#define IMX8DXL_ADC_IN3_M40_GPIO0_IO03 IMX8DXL_ADC_IN3 2 +-#define IMX8DXL_ADC_IN3_ADMA_ACM_MCLK_OUT0 IMX8DXL_ADC_IN3 3 +-#define IMX8DXL_ADC_IN3_LSIO_GPIO1_IO11 IMX8DXL_ADC_IN3 4 +-#define IMX8DXL_ADC_IN3_ADMA_LCDIF_D15 IMX8DXL_ADC_IN3 5 +-#define IMX8DXL_ADC_IN2_ADMA_ADC_IN2 IMX8DXL_ADC_IN2 0 +-#define IMX8DXL_ADC_IN2_M40_UART0_RX IMX8DXL_ADC_IN2 1 +-#define IMX8DXL_ADC_IN2_M40_GPIO0_IO02 IMX8DXL_ADC_IN2 2 +-#define IMX8DXL_ADC_IN2_ADMA_ACM_MCLK_IN0 IMX8DXL_ADC_IN2 3 +-#define IMX8DXL_ADC_IN2_LSIO_GPIO1_IO12 IMX8DXL_ADC_IN2 4 +-#define IMX8DXL_ADC_IN2_ADMA_LCDIF_D16 IMX8DXL_ADC_IN2 5 +-#define IMX8DXL_ADC_IN5_ADMA_ADC_IN5 IMX8DXL_ADC_IN5 0 +-#define IMX8DXL_ADC_IN5_M40_TPM0_CH1 IMX8DXL_ADC_IN5 1 +-#define IMX8DXL_ADC_IN5_M40_GPIO0_IO05 IMX8DXL_ADC_IN5 2 +-#define IMX8DXL_ADC_IN5_ADMA_LCDIF_LCDBUSY IMX8DXL_ADC_IN5 3 +-#define IMX8DXL_ADC_IN5_LSIO_GPIO1_IO13 IMX8DXL_ADC_IN5 4 +-#define IMX8DXL_ADC_IN5_ADMA_LCDIF_D17 IMX8DXL_ADC_IN5 5 +-#define IMX8DXL_ADC_IN4_ADMA_ADC_IN4 IMX8DXL_ADC_IN4 0 +-#define IMX8DXL_ADC_IN4_M40_TPM0_CH0 IMX8DXL_ADC_IN4 1 +-#define IMX8DXL_ADC_IN4_M40_GPIO0_IO04 IMX8DXL_ADC_IN4 2 +-#define IMX8DXL_ADC_IN4_ADMA_LCDIF_LCDRESET IMX8DXL_ADC_IN4 3 +-#define IMX8DXL_ADC_IN4_LSIO_GPIO1_IO14 IMX8DXL_ADC_IN4 4 +-#define IMX8DXL_FLEXCAN0_RX_ADMA_FLEXCAN0_RX IMX8DXL_FLEXCAN0_RX 0 +-#define IMX8DXL_FLEXCAN0_RX_ADMA_SAI2_RXC IMX8DXL_FLEXCAN0_RX 1 +-#define IMX8DXL_FLEXCAN0_RX_ADMA_UART0_RTS_B IMX8DXL_FLEXCAN0_RX 2 +-#define IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC IMX8DXL_FLEXCAN0_RX 3 +-#define IMX8DXL_FLEXCAN0_RX_LSIO_GPIO1_IO15 IMX8DXL_FLEXCAN0_RX 4 +-#define IMX8DXL_FLEXCAN0_RX_LSIO_GPIO6_IO08 IMX8DXL_FLEXCAN0_RX 5 +-#define IMX8DXL_FLEXCAN0_TX_ADMA_FLEXCAN0_TX IMX8DXL_FLEXCAN0_TX 0 +-#define IMX8DXL_FLEXCAN0_TX_ADMA_SAI2_RXD IMX8DXL_FLEXCAN0_TX 1 +-#define IMX8DXL_FLEXCAN0_TX_ADMA_UART0_CTS_B IMX8DXL_FLEXCAN0_TX 2 +-#define IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS IMX8DXL_FLEXCAN0_TX 3 +-#define IMX8DXL_FLEXCAN0_TX_LSIO_GPIO1_IO16 IMX8DXL_FLEXCAN0_TX 4 +-#define IMX8DXL_FLEXCAN0_TX_LSIO_GPIO6_IO09 IMX8DXL_FLEXCAN0_TX 5 +-#define IMX8DXL_FLEXCAN1_RX_ADMA_FLEXCAN1_RX IMX8DXL_FLEXCAN1_RX 0 +-#define IMX8DXL_FLEXCAN1_RX_ADMA_SAI2_RXFS IMX8DXL_FLEXCAN1_RX 1 +-#define IMX8DXL_FLEXCAN1_RX_ADMA_FTM_CH2 IMX8DXL_FLEXCAN1_RX 2 +-#define IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD IMX8DXL_FLEXCAN1_RX 3 +-#define IMX8DXL_FLEXCAN1_RX_LSIO_GPIO1_IO17 IMX8DXL_FLEXCAN1_RX 4 +-#define IMX8DXL_FLEXCAN1_RX_LSIO_GPIO6_IO10 IMX8DXL_FLEXCAN1_RX 5 +-#define IMX8DXL_FLEXCAN1_TX_ADMA_FLEXCAN1_TX IMX8DXL_FLEXCAN1_TX 0 +-#define IMX8DXL_FLEXCAN1_TX_ADMA_SAI3_RXC IMX8DXL_FLEXCAN1_TX 1 +-#define IMX8DXL_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 IMX8DXL_FLEXCAN1_TX 2 +-#define IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD IMX8DXL_FLEXCAN1_TX 3 +-#define IMX8DXL_FLEXCAN1_TX_LSIO_GPIO1_IO18 IMX8DXL_FLEXCAN1_TX 4 +-#define IMX8DXL_FLEXCAN1_TX_LSIO_GPIO6_IO11 IMX8DXL_FLEXCAN1_TX 5 +-#define IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX IMX8DXL_FLEXCAN2_RX 0 +-#define IMX8DXL_FLEXCAN2_RX_ADMA_SAI3_RXD IMX8DXL_FLEXCAN2_RX 1 +-#define IMX8DXL_FLEXCAN2_RX_ADMA_UART3_RX IMX8DXL_FLEXCAN2_RX 2 +-#define IMX8DXL_FLEXCAN2_RX_ADMA_SAI1_RXFS IMX8DXL_FLEXCAN2_RX 3 +-#define IMX8DXL_FLEXCAN2_RX_LSIO_GPIO1_IO19 IMX8DXL_FLEXCAN2_RX 4 +-#define IMX8DXL_FLEXCAN2_RX_LSIO_GPIO6_IO12 IMX8DXL_FLEXCAN2_RX 5 +-#define IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX IMX8DXL_FLEXCAN2_TX 0 +-#define IMX8DXL_FLEXCAN2_TX_ADMA_SAI3_RXFS IMX8DXL_FLEXCAN2_TX 1 +-#define IMX8DXL_FLEXCAN2_TX_ADMA_UART3_TX IMX8DXL_FLEXCAN2_TX 2 +-#define IMX8DXL_FLEXCAN2_TX_ADMA_SAI1_RXC IMX8DXL_FLEXCAN2_TX 3 +-#define IMX8DXL_FLEXCAN2_TX_LSIO_GPIO1_IO20 IMX8DXL_FLEXCAN2_TX 4 +-#define IMX8DXL_FLEXCAN2_TX_LSIO_GPIO6_IO13 IMX8DXL_FLEXCAN2_TX 5 +-#define IMX8DXL_UART0_RX_ADMA_UART0_RX IMX8DXL_UART0_RX 0 +-#define IMX8DXL_UART0_RX_ADMA_MQS_R IMX8DXL_UART0_RX 1 +-#define IMX8DXL_UART0_RX_ADMA_FLEXCAN0_RX IMX8DXL_UART0_RX 2 +-#define IMX8DXL_UART0_RX_SCU_UART0_RX IMX8DXL_UART0_RX 3 +-#define IMX8DXL_UART0_RX_LSIO_GPIO1_IO21 IMX8DXL_UART0_RX 4 +-#define IMX8DXL_UART0_RX_LSIO_GPIO6_IO14 IMX8DXL_UART0_RX 5 +-#define IMX8DXL_UART0_TX_ADMA_UART0_TX IMX8DXL_UART0_TX 0 +-#define IMX8DXL_UART0_TX_ADMA_MQS_L IMX8DXL_UART0_TX 1 +-#define IMX8DXL_UART0_TX_ADMA_FLEXCAN0_TX IMX8DXL_UART0_TX 2 +-#define IMX8DXL_UART0_TX_SCU_UART0_TX IMX8DXL_UART0_TX 3 +-#define IMX8DXL_UART0_TX_LSIO_GPIO1_IO22 IMX8DXL_UART0_TX 4 +-#define IMX8DXL_UART0_TX_LSIO_GPIO6_IO15 IMX8DXL_UART0_TX 5 +-#define IMX8DXL_UART2_TX_ADMA_UART2_TX IMX8DXL_UART2_TX 0 +-#define IMX8DXL_UART2_TX_ADMA_FTM_CH1 IMX8DXL_UART2_TX 1 +-#define IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX IMX8DXL_UART2_TX 2 +-#define IMX8DXL_UART2_TX_LSIO_GPIO1_IO23 IMX8DXL_UART2_TX 4 +-#define IMX8DXL_UART2_TX_LSIO_GPIO6_IO16 IMX8DXL_UART2_TX 5 +-#define IMX8DXL_UART2_RX_ADMA_UART2_RX IMX8DXL_UART2_RX 0 +-#define IMX8DXL_UART2_RX_ADMA_FTM_CH0 IMX8DXL_UART2_RX 1 +-#define IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX IMX8DXL_UART2_RX 2 +-#define IMX8DXL_UART2_RX_LSIO_GPIO1_IO24 IMX8DXL_UART2_RX 4 +-#define IMX8DXL_UART2_RX_LSIO_GPIO6_IO17 IMX8DXL_UART2_RX 5 +-#define IMX8DXL_JTAG_TRST_B_SCU_JTAG_TRST_B IMX8DXL_JTAG_TRST_B 0 +-#define IMX8DXL_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT IMX8DXL_JTAG_TRST_B 1 +-#define IMX8DXL_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL IMX8DXL_PMIC_I2C_SCL 0 +-#define IMX8DXL_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON IMX8DXL_PMIC_I2C_SCL 1 +-#define IMX8DXL_PMIC_I2C_SCL_LSIO_GPIO2_IO01 IMX8DXL_PMIC_I2C_SCL 4 +-#define IMX8DXL_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA IMX8DXL_PMIC_I2C_SDA 0 +-#define IMX8DXL_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON IMX8DXL_PMIC_I2C_SDA 1 +-#define IMX8DXL_PMIC_I2C_SDA_LSIO_GPIO2_IO02 IMX8DXL_PMIC_I2C_SDA 4 +-#define IMX8DXL_PMIC_INT_B_SCU_DSC_PMIC_INT_B IMX8DXL_PMIC_INT_B 0 +-#define IMX8DXL_SCU_GPIO0_00_SCU_GPIO0_IO00 IMX8DXL_SCU_GPIO0_00 0 +-#define IMX8DXL_SCU_GPIO0_00_SCU_UART0_RX IMX8DXL_SCU_GPIO0_00 1 +-#define IMX8DXL_SCU_GPIO0_00_M40_UART0_RX IMX8DXL_SCU_GPIO0_00 2 +-#define IMX8DXL_SCU_GPIO0_00_ADMA_UART3_RX IMX8DXL_SCU_GPIO0_00 3 +-#define IMX8DXL_SCU_GPIO0_00_LSIO_GPIO2_IO03 IMX8DXL_SCU_GPIO0_00 4 +-#define IMX8DXL_SCU_GPIO0_01_SCU_GPIO0_IO01 IMX8DXL_SCU_GPIO0_01 0 +-#define IMX8DXL_SCU_GPIO0_01_SCU_UART0_TX IMX8DXL_SCU_GPIO0_01 1 +-#define IMX8DXL_SCU_GPIO0_01_M40_UART0_TX IMX8DXL_SCU_GPIO0_01 2 +-#define IMX8DXL_SCU_GPIO0_01_ADMA_UART3_TX IMX8DXL_SCU_GPIO0_01 3 +-#define IMX8DXL_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT IMX8DXL_SCU_GPIO0_01 4 +-#define IMX8DXL_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY IMX8DXL_SCU_PMIC_STANDBY 0 +-#define IMX8DXL_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 IMX8DXL_SCU_BOOT_MODE1 0 +-#define IMX8DXL_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 IMX8DXL_SCU_BOOT_MODE0 0 +-#define IMX8DXL_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 IMX8DXL_SCU_BOOT_MODE2 0 +-#define IMX8DXL_SCU_BOOT_MODE2_SCU_DSC_RTC_CLOCK_OUTPUT_32K IMX8DXL_SCU_BOOT_MODE2 1 +-#define IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN IMX8DXL_SNVS_TAMPER_OUT1 4 +-#define IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO6_IO19_IN IMX8DXL_SNVS_TAMPER_OUT1 5 +-#define IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO2_IO06_IN IMX8DXL_SNVS_TAMPER_OUT2 4 +-#define IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO6_IO20_IN IMX8DXL_SNVS_TAMPER_OUT2 5 +-#define IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC IMX8DXL_SNVS_TAMPER_OUT3 2 +-#define IMX8DXL_SNVS_TAMPER_OUT3_LSIO_GPIO2_IO07_IN IMX8DXL_SNVS_TAMPER_OUT3 4 +-#define IMX8DXL_SNVS_TAMPER_OUT3_LSIO_GPIO6_IO21_IN IMX8DXL_SNVS_TAMPER_OUT3 5 +-#define IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD IMX8DXL_SNVS_TAMPER_OUT4 2 +-#define IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO2_IO08_IN IMX8DXL_SNVS_TAMPER_OUT4 4 +-#define IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO6_IO22_IN IMX8DXL_SNVS_TAMPER_OUT4 5 +-#define IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS IMX8DXL_SNVS_TAMPER_IN0 2 +-#define IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO2_IO09_IN IMX8DXL_SNVS_TAMPER_IN0 4 +-#define IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO6_IO23_IN IMX8DXL_SNVS_TAMPER_IN0 5 +-#define IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC IMX8DXL_SNVS_TAMPER_IN1 2 +-#define IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO2_IO10_IN IMX8DXL_SNVS_TAMPER_IN1 4 +-#define IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO6_IO24_IN IMX8DXL_SNVS_TAMPER_IN1 5 +-#define IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD IMX8DXL_SNVS_TAMPER_IN2 2 +-#define IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO2_IO11_IN IMX8DXL_SNVS_TAMPER_IN2 4 +-#define IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO6_IO25_IN IMX8DXL_SNVS_TAMPER_IN2 5 +-#define IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS IMX8DXL_SNVS_TAMPER_IN3 2 +-#define IMX8DXL_SNVS_TAMPER_IN3_LSIO_GPIO2_IO12_IN IMX8DXL_SNVS_TAMPER_IN3 4 +-#define IMX8DXL_SNVS_TAMPER_IN3_LSIO_GPIO6_IO26_IN IMX8DXL_SNVS_TAMPER_IN3 5 +-#define IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA IMX8DXL_SPI1_SCK 2 +-#define IMX8DXL_SPI1_SCK_ADMA_SPI1_SCK IMX8DXL_SPI1_SCK 3 +-#define IMX8DXL_SPI1_SCK_LSIO_GPIO3_IO00 IMX8DXL_SPI1_SCK 4 +-#define IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL IMX8DXL_SPI1_SDO 2 +-#define IMX8DXL_SPI1_SDO_ADMA_SPI1_SDO IMX8DXL_SPI1_SDO 3 +-#define IMX8DXL_SPI1_SDO_LSIO_GPIO3_IO01 IMX8DXL_SPI1_SDO 4 +-#define IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL IMX8DXL_SPI1_SDI 2 +-#define IMX8DXL_SPI1_SDI_ADMA_SPI1_SDI IMX8DXL_SPI1_SDI 3 +-#define IMX8DXL_SPI1_SDI_LSIO_GPIO3_IO02 IMX8DXL_SPI1_SDI 4 +-#define IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA IMX8DXL_SPI1_CS0 2 +-#define IMX8DXL_SPI1_CS0_ADMA_SPI1_CS0 IMX8DXL_SPI1_CS0 3 +-#define IMX8DXL_SPI1_CS0_LSIO_GPIO3_IO03 IMX8DXL_SPI1_CS0 4 +-#define IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 IMX8DXL_QSPI0A_DATA1 0 +-#define IMX8DXL_QSPI0A_DATA1_LSIO_GPIO3_IO10 IMX8DXL_QSPI0A_DATA1 4 +-#define IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 IMX8DXL_QSPI0A_DATA0 0 +-#define IMX8DXL_QSPI0A_DATA0_LSIO_GPIO3_IO09 IMX8DXL_QSPI0A_DATA0 4 +-#define IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 IMX8DXL_QSPI0A_DATA3 0 +-#define IMX8DXL_QSPI0A_DATA3_LSIO_GPIO3_IO12 IMX8DXL_QSPI0A_DATA3 4 +-#define IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 IMX8DXL_QSPI0A_DATA2 0 +-#define IMX8DXL_QSPI0A_DATA2_LSIO_GPIO3_IO11 IMX8DXL_QSPI0A_DATA2 4 +-#define IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B IMX8DXL_QSPI0A_SS0_B 0 +-#define IMX8DXL_QSPI0A_SS0_B_LSIO_GPIO3_IO14 IMX8DXL_QSPI0A_SS0_B 4 +-#define IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS IMX8DXL_QSPI0A_DQS 0 +-#define IMX8DXL_QSPI0A_DQS_LSIO_GPIO3_IO13 IMX8DXL_QSPI0A_DQS 4 +-#define IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK IMX8DXL_QSPI0A_SCLK 0 +-#define IMX8DXL_QSPI0A_SCLK_LSIO_GPIO3_IO16 IMX8DXL_QSPI0A_SCLK 4 +-#define IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK IMX8DXL_QSPI0B_SCLK 0 +-#define IMX8DXL_QSPI0B_SCLK_LSIO_GPIO3_IO17 IMX8DXL_QSPI0B_SCLK 4 +-#define IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS IMX8DXL_QSPI0B_DQS 0 +-#define IMX8DXL_QSPI0B_DQS_LSIO_GPIO3_IO22 IMX8DXL_QSPI0B_DQS 4 +-#define IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 IMX8DXL_QSPI0B_DATA1 0 +-#define IMX8DXL_QSPI0B_DATA1_LSIO_GPIO3_IO19 IMX8DXL_QSPI0B_DATA1 4 +-#define IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 IMX8DXL_QSPI0B_DATA0 0 +-#define IMX8DXL_QSPI0B_DATA0_LSIO_GPIO3_IO18 IMX8DXL_QSPI0B_DATA0 4 +-#define IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 IMX8DXL_QSPI0B_DATA3 0 +-#define IMX8DXL_QSPI0B_DATA3_LSIO_GPIO3_IO21 IMX8DXL_QSPI0B_DATA3 4 +-#define IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 IMX8DXL_QSPI0B_DATA2 0 +-#define IMX8DXL_QSPI0B_DATA2_LSIO_GPIO3_IO20 IMX8DXL_QSPI0B_DATA2 4 +-#define IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B IMX8DXL_QSPI0B_SS0_B 0 +-#define IMX8DXL_QSPI0B_SS0_B_LSIO_GPIO3_IO23 IMX8DXL_QSPI0B_SS0_B 4 +-#define IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0A_SS1_B IMX8DXL_QSPI0B_SS0_B 5 +- +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0 +-#define IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO_PAD IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO 0 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 0 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK 0 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD 0 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A 0 +-#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B 0 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pads-imx8qm.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pads-imx8qm.h +deleted file mode 100644 +index ae7b2942da69..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pads-imx8qm.h ++++ /dev/null +@@ -1,960 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright (C) 2016 Freescale Semiconductor, Inc. +- * Copyright 2017~2018 NXP +- */ +- +-#ifndef _IMX8QM_PADS_H +-#define _IMX8QM_PADS_H +- +-/* pin id */ +-#define IMX8QM_SIM0_CLK 0 +-#define IMX8QM_SIM0_RST 1 +-#define IMX8QM_SIM0_IO 2 +-#define IMX8QM_SIM0_PD 3 +-#define IMX8QM_SIM0_POWER_EN 4 +-#define IMX8QM_SIM0_GPIO0_00 5 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_SIM 6 +-#define IMX8QM_M40_I2C0_SCL 7 +-#define IMX8QM_M40_I2C0_SDA 8 +-#define IMX8QM_M40_GPIO0_00 9 +-#define IMX8QM_M40_GPIO0_01 10 +-#define IMX8QM_M41_I2C0_SCL 11 +-#define IMX8QM_M41_I2C0_SDA 12 +-#define IMX8QM_M41_GPIO0_00 13 +-#define IMX8QM_M41_GPIO0_01 14 +-#define IMX8QM_GPT0_CLK 15 +-#define IMX8QM_GPT0_CAPTURE 16 +-#define IMX8QM_GPT0_COMPARE 17 +-#define IMX8QM_GPT1_CLK 18 +-#define IMX8QM_GPT1_CAPTURE 19 +-#define IMX8QM_GPT1_COMPARE 20 +-#define IMX8QM_UART0_RX 21 +-#define IMX8QM_UART0_TX 22 +-#define IMX8QM_UART0_RTS_B 23 +-#define IMX8QM_UART0_CTS_B 24 +-#define IMX8QM_UART1_TX 25 +-#define IMX8QM_UART1_RX 26 +-#define IMX8QM_UART1_RTS_B 27 +-#define IMX8QM_UART1_CTS_B 28 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 +-#define IMX8QM_SCU_PMIC_MEMC_ON 30 +-#define IMX8QM_SCU_WDOG_OUT 31 +-#define IMX8QM_PMIC_I2C_SDA 32 +-#define IMX8QM_PMIC_I2C_SCL 33 +-#define IMX8QM_PMIC_EARLY_WARNING 34 +-#define IMX8QM_PMIC_INT_B 35 +-#define IMX8QM_SCU_GPIO0_00 36 +-#define IMX8QM_SCU_GPIO0_01 37 +-#define IMX8QM_SCU_GPIO0_02 38 +-#define IMX8QM_SCU_GPIO0_03 39 +-#define IMX8QM_SCU_GPIO0_04 40 +-#define IMX8QM_SCU_GPIO0_05 41 +-#define IMX8QM_SCU_GPIO0_06 42 +-#define IMX8QM_SCU_GPIO0_07 43 +-#define IMX8QM_SCU_BOOT_MODE0 44 +-#define IMX8QM_SCU_BOOT_MODE1 45 +-#define IMX8QM_SCU_BOOT_MODE2 46 +-#define IMX8QM_SCU_BOOT_MODE3 47 +-#define IMX8QM_SCU_BOOT_MODE4 48 +-#define IMX8QM_SCU_BOOT_MODE5 49 +-#define IMX8QM_LVDS0_GPIO00 50 +-#define IMX8QM_LVDS0_GPIO01 51 +-#define IMX8QM_LVDS0_I2C0_SCL 52 +-#define IMX8QM_LVDS0_I2C0_SDA 53 +-#define IMX8QM_LVDS0_I2C1_SCL 54 +-#define IMX8QM_LVDS0_I2C1_SDA 55 +-#define IMX8QM_LVDS1_GPIO00 56 +-#define IMX8QM_LVDS1_GPIO01 57 +-#define IMX8QM_LVDS1_I2C0_SCL 58 +-#define IMX8QM_LVDS1_I2C0_SDA 59 +-#define IMX8QM_LVDS1_I2C1_SCL 60 +-#define IMX8QM_LVDS1_I2C1_SDA 61 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 +-#define IMX8QM_MIPI_DSI0_I2C0_SCL 63 +-#define IMX8QM_MIPI_DSI0_I2C0_SDA 64 +-#define IMX8QM_MIPI_DSI0_GPIO0_00 65 +-#define IMX8QM_MIPI_DSI0_GPIO0_01 66 +-#define IMX8QM_MIPI_DSI1_I2C0_SCL 67 +-#define IMX8QM_MIPI_DSI1_I2C0_SDA 68 +-#define IMX8QM_MIPI_DSI1_GPIO0_00 69 +-#define IMX8QM_MIPI_DSI1_GPIO0_01 70 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 +-#define IMX8QM_MIPI_CSI0_MCLK_OUT 72 +-#define IMX8QM_MIPI_CSI0_I2C0_SCL 73 +-#define IMX8QM_MIPI_CSI0_I2C0_SDA 74 +-#define IMX8QM_MIPI_CSI0_GPIO0_00 75 +-#define IMX8QM_MIPI_CSI0_GPIO0_01 76 +-#define IMX8QM_MIPI_CSI1_MCLK_OUT 77 +-#define IMX8QM_MIPI_CSI1_GPIO0_00 78 +-#define IMX8QM_MIPI_CSI1_GPIO0_01 79 +-#define IMX8QM_MIPI_CSI1_I2C0_SCL 80 +-#define IMX8QM_MIPI_CSI1_I2C0_SDA 81 +-#define IMX8QM_HDMI_TX0_TS_SCL 82 +-#define IMX8QM_HDMI_TX0_TS_SDA 83 +-#define IMX8QM_COMP_CTL_GPIO_3V3_HDMIGPIO 84 +-#define IMX8QM_ESAI1_FSR 85 +-#define IMX8QM_ESAI1_FST 86 +-#define IMX8QM_ESAI1_SCKR 87 +-#define IMX8QM_ESAI1_SCKT 88 +-#define IMX8QM_ESAI1_TX0 89 +-#define IMX8QM_ESAI1_TX1 90 +-#define IMX8QM_ESAI1_TX2_RX3 91 +-#define IMX8QM_ESAI1_TX3_RX2 92 +-#define IMX8QM_ESAI1_TX4_RX1 93 +-#define IMX8QM_ESAI1_TX5_RX0 94 +-#define IMX8QM_SPDIF0_RX 95 +-#define IMX8QM_SPDIF0_TX 96 +-#define IMX8QM_SPDIF0_EXT_CLK 97 +-#define IMX8QM_SPI3_SCK 98 +-#define IMX8QM_SPI3_SDO 99 +-#define IMX8QM_SPI3_SDI 100 +-#define IMX8QM_SPI3_CS0 101 +-#define IMX8QM_SPI3_CS1 102 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 +-#define IMX8QM_ESAI0_FSR 104 +-#define IMX8QM_ESAI0_FST 105 +-#define IMX8QM_ESAI0_SCKR 106 +-#define IMX8QM_ESAI0_SCKT 107 +-#define IMX8QM_ESAI0_TX0 108 +-#define IMX8QM_ESAI0_TX1 109 +-#define IMX8QM_ESAI0_TX2_RX3 110 +-#define IMX8QM_ESAI0_TX3_RX2 111 +-#define IMX8QM_ESAI0_TX4_RX1 112 +-#define IMX8QM_ESAI0_TX5_RX0 113 +-#define IMX8QM_MCLK_IN0 114 +-#define IMX8QM_MCLK_OUT0 115 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 +-#define IMX8QM_SPI0_SCK 117 +-#define IMX8QM_SPI0_SDO 118 +-#define IMX8QM_SPI0_SDI 119 +-#define IMX8QM_SPI0_CS0 120 +-#define IMX8QM_SPI0_CS1 121 +-#define IMX8QM_SPI2_SCK 122 +-#define IMX8QM_SPI2_SDO 123 +-#define IMX8QM_SPI2_SDI 124 +-#define IMX8QM_SPI2_CS0 125 +-#define IMX8QM_SPI2_CS1 126 +-#define IMX8QM_SAI1_RXC 127 +-#define IMX8QM_SAI1_RXD 128 +-#define IMX8QM_SAI1_RXFS 129 +-#define IMX8QM_SAI1_TXC 130 +-#define IMX8QM_SAI1_TXD 131 +-#define IMX8QM_SAI1_TXFS 132 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 +-#define IMX8QM_ADC_IN7 134 +-#define IMX8QM_ADC_IN6 135 +-#define IMX8QM_ADC_IN5 136 +-#define IMX8QM_ADC_IN4 137 +-#define IMX8QM_ADC_IN3 138 +-#define IMX8QM_ADC_IN2 139 +-#define IMX8QM_ADC_IN1 140 +-#define IMX8QM_ADC_IN0 141 +-#define IMX8QM_MLB_SIG 142 +-#define IMX8QM_MLB_CLK 143 +-#define IMX8QM_MLB_DATA 144 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 +-#define IMX8QM_FLEXCAN0_RX 146 +-#define IMX8QM_FLEXCAN0_TX 147 +-#define IMX8QM_FLEXCAN1_RX 148 +-#define IMX8QM_FLEXCAN1_TX 149 +-#define IMX8QM_FLEXCAN2_RX 150 +-#define IMX8QM_FLEXCAN2_TX 151 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 +-#define IMX8QM_USB_SS3_TC0 153 +-#define IMX8QM_USB_SS3_TC1 154 +-#define IMX8QM_USB_SS3_TC2 155 +-#define IMX8QM_USB_SS3_TC3 156 +-#define IMX8QM_COMP_CTL_GPIO_3V3_USB3IO 157 +-#define IMX8QM_USDHC1_RESET_B 158 +-#define IMX8QM_USDHC1_VSELECT 159 +-#define IMX8QM_USDHC2_RESET_B 160 +-#define IMX8QM_USDHC2_VSELECT 161 +-#define IMX8QM_USDHC2_WP 162 +-#define IMX8QM_USDHC2_CD_B 163 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 +-#define IMX8QM_ENET0_MDIO 165 +-#define IMX8QM_ENET0_MDC 166 +-#define IMX8QM_ENET0_REFCLK_125M_25M 167 +-#define IMX8QM_ENET1_REFCLK_125M_25M 168 +-#define IMX8QM_ENET1_MDIO 169 +-#define IMX8QM_ENET1_MDC 170 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 +-#define IMX8QM_QSPI1A_SS0_B 172 +-#define IMX8QM_QSPI1A_SS1_B 173 +-#define IMX8QM_QSPI1A_SCLK 174 +-#define IMX8QM_QSPI1A_DQS 175 +-#define IMX8QM_QSPI1A_DATA3 176 +-#define IMX8QM_QSPI1A_DATA2 177 +-#define IMX8QM_QSPI1A_DATA1 178 +-#define IMX8QM_QSPI1A_DATA0 179 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 +-#define IMX8QM_QSPI0A_DATA0 181 +-#define IMX8QM_QSPI0A_DATA1 182 +-#define IMX8QM_QSPI0A_DATA2 183 +-#define IMX8QM_QSPI0A_DATA3 184 +-#define IMX8QM_QSPI0A_DQS 185 +-#define IMX8QM_QSPI0A_SS0_B 186 +-#define IMX8QM_QSPI0A_SS1_B 187 +-#define IMX8QM_QSPI0A_SCLK 188 +-#define IMX8QM_QSPI0B_SCLK 189 +-#define IMX8QM_QSPI0B_DATA0 190 +-#define IMX8QM_QSPI0B_DATA1 191 +-#define IMX8QM_QSPI0B_DATA2 192 +-#define IMX8QM_QSPI0B_DATA3 193 +-#define IMX8QM_QSPI0B_DQS 194 +-#define IMX8QM_QSPI0B_SS0_B 195 +-#define IMX8QM_QSPI0B_SS1_B 196 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 +-#define IMX8QM_PCIE_CTRL0_CLKREQ_B 198 +-#define IMX8QM_PCIE_CTRL0_WAKE_B 199 +-#define IMX8QM_PCIE_CTRL0_PERST_B 200 +-#define IMX8QM_PCIE_CTRL1_CLKREQ_B 201 +-#define IMX8QM_PCIE_CTRL1_WAKE_B 202 +-#define IMX8QM_PCIE_CTRL1_PERST_B 203 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 +-#define IMX8QM_USB_HSIC0_DATA 205 +-#define IMX8QM_USB_HSIC0_STROBE 206 +-#define IMX8QM_CALIBRATION_0_HSIC 207 +-#define IMX8QM_CALIBRATION_1_HSIC 208 +-#define IMX8QM_EMMC0_CLK 209 +-#define IMX8QM_EMMC0_CMD 210 +-#define IMX8QM_EMMC0_DATA0 211 +-#define IMX8QM_EMMC0_DATA1 212 +-#define IMX8QM_EMMC0_DATA2 213 +-#define IMX8QM_EMMC0_DATA3 214 +-#define IMX8QM_EMMC0_DATA4 215 +-#define IMX8QM_EMMC0_DATA5 216 +-#define IMX8QM_EMMC0_DATA6 217 +-#define IMX8QM_EMMC0_DATA7 218 +-#define IMX8QM_EMMC0_STROBE 219 +-#define IMX8QM_EMMC0_RESET_B 220 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 +-#define IMX8QM_USDHC1_CLK 222 +-#define IMX8QM_USDHC1_CMD 223 +-#define IMX8QM_USDHC1_DATA0 224 +-#define IMX8QM_USDHC1_DATA1 225 +-#define IMX8QM_CTL_NAND_RE_P_N 226 +-#define IMX8QM_USDHC1_DATA2 227 +-#define IMX8QM_USDHC1_DATA3 228 +-#define IMX8QM_CTL_NAND_DQS_P_N 229 +-#define IMX8QM_USDHC1_DATA4 230 +-#define IMX8QM_USDHC1_DATA5 231 +-#define IMX8QM_USDHC1_DATA6 232 +-#define IMX8QM_USDHC1_DATA7 233 +-#define IMX8QM_USDHC1_STROBE 234 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 +-#define IMX8QM_USDHC2_CLK 236 +-#define IMX8QM_USDHC2_CMD 237 +-#define IMX8QM_USDHC2_DATA0 238 +-#define IMX8QM_USDHC2_DATA1 239 +-#define IMX8QM_USDHC2_DATA2 240 +-#define IMX8QM_USDHC2_DATA3 241 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 +-#define IMX8QM_ENET0_RGMII_TXC 243 +-#define IMX8QM_ENET0_RGMII_TX_CTL 244 +-#define IMX8QM_ENET0_RGMII_TXD0 245 +-#define IMX8QM_ENET0_RGMII_TXD1 246 +-#define IMX8QM_ENET0_RGMII_TXD2 247 +-#define IMX8QM_ENET0_RGMII_TXD3 248 +-#define IMX8QM_ENET0_RGMII_RXC 249 +-#define IMX8QM_ENET0_RGMII_RX_CTL 250 +-#define IMX8QM_ENET0_RGMII_RXD0 251 +-#define IMX8QM_ENET0_RGMII_RXD1 252 +-#define IMX8QM_ENET0_RGMII_RXD2 253 +-#define IMX8QM_ENET0_RGMII_RXD3 254 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 +-#define IMX8QM_ENET1_RGMII_TXC 256 +-#define IMX8QM_ENET1_RGMII_TX_CTL 257 +-#define IMX8QM_ENET1_RGMII_TXD0 258 +-#define IMX8QM_ENET1_RGMII_TXD1 259 +-#define IMX8QM_ENET1_RGMII_TXD2 260 +-#define IMX8QM_ENET1_RGMII_TXD3 261 +-#define IMX8QM_ENET1_RGMII_RXC 262 +-#define IMX8QM_ENET1_RGMII_RX_CTL 263 +-#define IMX8QM_ENET1_RGMII_RXD0 264 +-#define IMX8QM_ENET1_RGMII_RXD1 265 +-#define IMX8QM_ENET1_RGMII_RXD2 266 +-#define IMX8QM_ENET1_RGMII_RXD3 267 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 +- +-/* +- * format: +- */ +-#define IMX8QM_SIM0_CLK_DMA_SIM0_CLK IMX8QM_SIM0_CLK 0 +-#define IMX8QM_SIM0_CLK_LSIO_GPIO0_IO00 IMX8QM_SIM0_CLK 3 +-#define IMX8QM_SIM0_RST_DMA_SIM0_RST IMX8QM_SIM0_RST 0 +-#define IMX8QM_SIM0_RST_LSIO_GPIO0_IO01 IMX8QM_SIM0_RST 3 +-#define IMX8QM_SIM0_IO_DMA_SIM0_IO IMX8QM_SIM0_IO 0 +-#define IMX8QM_SIM0_IO_LSIO_GPIO0_IO02 IMX8QM_SIM0_IO 3 +-#define IMX8QM_SIM0_PD_DMA_SIM0_PD IMX8QM_SIM0_PD 0 +-#define IMX8QM_SIM0_PD_DMA_I2C3_SCL IMX8QM_SIM0_PD 1 +-#define IMX8QM_SIM0_PD_LSIO_GPIO0_IO03 IMX8QM_SIM0_PD 3 +-#define IMX8QM_SIM0_POWER_EN_DMA_SIM0_POWER_EN IMX8QM_SIM0_POWER_EN 0 +-#define IMX8QM_SIM0_POWER_EN_DMA_I2C3_SDA IMX8QM_SIM0_POWER_EN 1 +-#define IMX8QM_SIM0_POWER_EN_LSIO_GPIO0_IO04 IMX8QM_SIM0_POWER_EN 3 +-#define IMX8QM_SIM0_GPIO0_00_DMA_SIM0_POWER_EN IMX8QM_SIM0_GPIO0_00 0 +-#define IMX8QM_SIM0_GPIO0_00_LSIO_GPIO0_IO05 IMX8QM_SIM0_GPIO0_00 3 +-#define IMX8QM_M40_I2C0_SCL_M40_I2C0_SCL IMX8QM_M40_I2C0_SCL 0 +-#define IMX8QM_M40_I2C0_SCL_M40_UART0_RX IMX8QM_M40_I2C0_SCL 1 +-#define IMX8QM_M40_I2C0_SCL_M40_GPIO0_IO02 IMX8QM_M40_I2C0_SCL 2 +-#define IMX8QM_M40_I2C0_SCL_LSIO_GPIO0_IO06 IMX8QM_M40_I2C0_SCL 3 +-#define IMX8QM_M40_I2C0_SDA_M40_I2C0_SDA IMX8QM_M40_I2C0_SDA 0 +-#define IMX8QM_M40_I2C0_SDA_M40_UART0_TX IMX8QM_M40_I2C0_SDA 1 +-#define IMX8QM_M40_I2C0_SDA_M40_GPIO0_IO03 IMX8QM_M40_I2C0_SDA 2 +-#define IMX8QM_M40_I2C0_SDA_LSIO_GPIO0_IO07 IMX8QM_M40_I2C0_SDA 3 +-#define IMX8QM_M40_GPIO0_00_M40_GPIO0_IO00 IMX8QM_M40_GPIO0_00 0 +-#define IMX8QM_M40_GPIO0_00_M40_TPM0_CH0 IMX8QM_M40_GPIO0_00 1 +-#define IMX8QM_M40_GPIO0_00_DMA_UART4_RX IMX8QM_M40_GPIO0_00 2 +-#define IMX8QM_M40_GPIO0_00_LSIO_GPIO0_IO08 IMX8QM_M40_GPIO0_00 3 +-#define IMX8QM_M40_GPIO0_01_M40_GPIO0_IO01 IMX8QM_M40_GPIO0_01 0 +-#define IMX8QM_M40_GPIO0_01_M40_TPM0_CH1 IMX8QM_M40_GPIO0_01 1 +-#define IMX8QM_M40_GPIO0_01_DMA_UART4_TX IMX8QM_M40_GPIO0_01 2 +-#define IMX8QM_M40_GPIO0_01_LSIO_GPIO0_IO09 IMX8QM_M40_GPIO0_01 3 +-#define IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL IMX8QM_M41_I2C0_SCL 0 +-#define IMX8QM_M41_I2C0_SCL_M41_UART0_RX IMX8QM_M41_I2C0_SCL 1 +-#define IMX8QM_M41_I2C0_SCL_M41_GPIO0_IO02 IMX8QM_M41_I2C0_SCL 2 +-#define IMX8QM_M41_I2C0_SCL_LSIO_GPIO0_IO10 IMX8QM_M41_I2C0_SCL 3 +-#define IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA IMX8QM_M41_I2C0_SDA 0 +-#define IMX8QM_M41_I2C0_SDA_M41_UART0_TX IMX8QM_M41_I2C0_SDA 1 +-#define IMX8QM_M41_I2C0_SDA_M41_GPIO0_IO03 IMX8QM_M41_I2C0_SDA 2 +-#define IMX8QM_M41_I2C0_SDA_LSIO_GPIO0_IO11 IMX8QM_M41_I2C0_SDA 3 +-#define IMX8QM_M41_GPIO0_00_M41_GPIO0_IO00 IMX8QM_M41_GPIO0_00 0 +-#define IMX8QM_M41_GPIO0_00_M41_TPM0_CH0 IMX8QM_M41_GPIO0_00 1 +-#define IMX8QM_M41_GPIO0_00_DMA_UART3_RX IMX8QM_M41_GPIO0_00 2 +-#define IMX8QM_M41_GPIO0_00_LSIO_GPIO0_IO12 IMX8QM_M41_GPIO0_00 3 +-#define IMX8QM_M41_GPIO0_01_M41_GPIO0_IO01 IMX8QM_M41_GPIO0_01 0 +-#define IMX8QM_M41_GPIO0_01_M41_TPM0_CH1 IMX8QM_M41_GPIO0_01 1 +-#define IMX8QM_M41_GPIO0_01_DMA_UART3_TX IMX8QM_M41_GPIO0_01 2 +-#define IMX8QM_M41_GPIO0_01_LSIO_GPIO0_IO13 IMX8QM_M41_GPIO0_01 3 +-#define IMX8QM_GPT0_CLK_LSIO_GPT0_CLK IMX8QM_GPT0_CLK 0 +-#define IMX8QM_GPT0_CLK_DMA_I2C1_SCL IMX8QM_GPT0_CLK 1 +-#define IMX8QM_GPT0_CLK_LSIO_KPP0_COL4 IMX8QM_GPT0_CLK 2 +-#define IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 IMX8QM_GPT0_CLK 3 +-#define IMX8QM_GPT0_CAPTURE_LSIO_GPT0_CAPTURE IMX8QM_GPT0_CAPTURE 0 +-#define IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA IMX8QM_GPT0_CAPTURE 1 +-#define IMX8QM_GPT0_CAPTURE_LSIO_KPP0_COL5 IMX8QM_GPT0_CAPTURE 2 +-#define IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 IMX8QM_GPT0_CAPTURE 3 +-#define IMX8QM_GPT0_COMPARE_LSIO_GPT0_COMPARE IMX8QM_GPT0_COMPARE 0 +-#define IMX8QM_GPT0_COMPARE_LSIO_PWM3_OUT IMX8QM_GPT0_COMPARE 1 +-#define IMX8QM_GPT0_COMPARE_LSIO_KPP0_COL6 IMX8QM_GPT0_COMPARE 2 +-#define IMX8QM_GPT0_COMPARE_LSIO_GPIO0_IO16 IMX8QM_GPT0_COMPARE 3 +-#define IMX8QM_GPT1_CLK_LSIO_GPT1_CLK IMX8QM_GPT1_CLK 0 +-#define IMX8QM_GPT1_CLK_DMA_I2C2_SCL IMX8QM_GPT1_CLK 1 +-#define IMX8QM_GPT1_CLK_LSIO_KPP0_COL7 IMX8QM_GPT1_CLK 2 +-#define IMX8QM_GPT1_CLK_LSIO_GPIO0_IO17 IMX8QM_GPT1_CLK 3 +-#define IMX8QM_GPT1_CAPTURE_LSIO_GPT1_CAPTURE IMX8QM_GPT1_CAPTURE 0 +-#define IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA IMX8QM_GPT1_CAPTURE 1 +-#define IMX8QM_GPT1_CAPTURE_LSIO_KPP0_ROW4 IMX8QM_GPT1_CAPTURE 2 +-#define IMX8QM_GPT1_CAPTURE_LSIO_GPIO0_IO18 IMX8QM_GPT1_CAPTURE 3 +-#define IMX8QM_GPT1_COMPARE_LSIO_GPT1_COMPARE IMX8QM_GPT1_COMPARE 0 +-#define IMX8QM_GPT1_COMPARE_LSIO_PWM2_OUT IMX8QM_GPT1_COMPARE 1 +-#define IMX8QM_GPT1_COMPARE_LSIO_KPP0_ROW5 IMX8QM_GPT1_COMPARE 2 +-#define IMX8QM_GPT1_COMPARE_LSIO_GPIO0_IO19 IMX8QM_GPT1_COMPARE 3 +-#define IMX8QM_UART0_RX_DMA_UART0_RX IMX8QM_UART0_RX 0 +-#define IMX8QM_UART0_RX_SCU_UART0_RX IMX8QM_UART0_RX 1 +-#define IMX8QM_UART0_RX_LSIO_GPIO0_IO20 IMX8QM_UART0_RX 3 +-#define IMX8QM_UART0_TX_DMA_UART0_TX IMX8QM_UART0_TX 0 +-#define IMX8QM_UART0_TX_SCU_UART0_TX IMX8QM_UART0_TX 1 +-#define IMX8QM_UART0_TX_LSIO_GPIO0_IO21 IMX8QM_UART0_TX 3 +-#define IMX8QM_UART0_RTS_B_DMA_UART0_RTS_B IMX8QM_UART0_RTS_B 0 +-#define IMX8QM_UART0_RTS_B_LSIO_PWM0_OUT IMX8QM_UART0_RTS_B 1 +-#define IMX8QM_UART0_RTS_B_DMA_UART2_RX IMX8QM_UART0_RTS_B 2 +-#define IMX8QM_UART0_RTS_B_LSIO_GPIO0_IO22 IMX8QM_UART0_RTS_B 3 +-#define IMX8QM_UART0_CTS_B_DMA_UART0_CTS_B IMX8QM_UART0_CTS_B 0 +-#define IMX8QM_UART0_CTS_B_LSIO_PWM1_OUT IMX8QM_UART0_CTS_B 1 +-#define IMX8QM_UART0_CTS_B_DMA_UART2_TX IMX8QM_UART0_CTS_B 2 +-#define IMX8QM_UART0_CTS_B_LSIO_GPIO0_IO23 IMX8QM_UART0_CTS_B 3 +-#define IMX8QM_UART1_TX_DMA_UART1_TX IMX8QM_UART1_TX 0 +-#define IMX8QM_UART1_TX_DMA_SPI3_SCK IMX8QM_UART1_TX 1 +-#define IMX8QM_UART1_TX_LSIO_GPIO0_IO24 IMX8QM_UART1_TX 3 +-#define IMX8QM_UART1_RX_DMA_UART1_RX IMX8QM_UART1_RX 0 +-#define IMX8QM_UART1_RX_DMA_SPI3_SDO IMX8QM_UART1_RX 1 +-#define IMX8QM_UART1_RX_LSIO_GPIO0_IO25 IMX8QM_UART1_RX 3 +-#define IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B IMX8QM_UART1_RTS_B 0 +-#define IMX8QM_UART1_RTS_B_DMA_SPI3_SDI IMX8QM_UART1_RTS_B 1 +-#define IMX8QM_UART1_RTS_B_DMA_UART1_CTS_B IMX8QM_UART1_RTS_B 2 +-#define IMX8QM_UART1_RTS_B_LSIO_GPIO0_IO26 IMX8QM_UART1_RTS_B 3 +-#define IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B IMX8QM_UART1_CTS_B 0 +-#define IMX8QM_UART1_CTS_B_DMA_SPI3_CS0 IMX8QM_UART1_CTS_B 1 +-#define IMX8QM_UART1_CTS_B_DMA_UART1_RTS_B IMX8QM_UART1_CTS_B 2 +-#define IMX8QM_UART1_CTS_B_LSIO_GPIO0_IO27 IMX8QM_UART1_CTS_B 3 +-#define IMX8QM_SCU_PMIC_MEMC_ON_SCU_GPIO0_IOXX_PMIC_MEMC_ON IMX8QM_SCU_PMIC_MEMC_ON 0 +-#define IMX8QM_SCU_WDOG_OUT_SCU_WDOG0_WDOG_OUT IMX8QM_SCU_WDOG_OUT 0 +-#define IMX8QM_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA IMX8QM_PMIC_I2C_SDA 0 +-#define IMX8QM_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL IMX8QM_PMIC_I2C_SCL 0 +-#define IMX8QM_PMIC_EARLY_WARNING_SCU_PMIC_EARLY_WARNING IMX8QM_PMIC_EARLY_WARNING 0 +-#define IMX8QM_PMIC_INT_B_SCU_DIMX8QMMIC_INT_B IMX8QM_PMIC_INT_B 0 +-#define IMX8QM_SCU_GPIO0_00_SCU_GPIO0_IO00 IMX8QM_SCU_GPIO0_00 0 +-#define IMX8QM_SCU_GPIO0_00_SCU_UART0_RX IMX8QM_SCU_GPIO0_00 1 +-#define IMX8QM_SCU_GPIO0_00_LSIO_GPIO0_IO28 IMX8QM_SCU_GPIO0_00 3 +-#define IMX8QM_SCU_GPIO0_01_SCU_GPIO0_IO01 IMX8QM_SCU_GPIO0_01 0 +-#define IMX8QM_SCU_GPIO0_01_SCU_UART0_TX IMX8QM_SCU_GPIO0_01 1 +-#define IMX8QM_SCU_GPIO0_01_LSIO_GPIO0_IO29 IMX8QM_SCU_GPIO0_01 3 +-#define IMX8QM_SCU_GPIO0_02_SCU_GPIO0_IO02 IMX8QM_SCU_GPIO0_02 0 +-#define IMX8QM_SCU_GPIO0_02_SCU_GPIO0_IOXX_PMIC_GPU0_ON IMX8QM_SCU_GPIO0_02 1 +-#define IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30 IMX8QM_SCU_GPIO0_02 3 +-#define IMX8QM_SCU_GPIO0_03_SCU_GPIO0_IO03 IMX8QM_SCU_GPIO0_03 0 +-#define IMX8QM_SCU_GPIO0_03_SCU_GPIO0_IOXX_PMIC_GPU1_ON IMX8QM_SCU_GPIO0_03 1 +-#define IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 IMX8QM_SCU_GPIO0_03 3 +-#define IMX8QM_SCU_GPIO0_04_SCU_GPIO0_IO04 IMX8QM_SCU_GPIO0_04 0 +-#define IMX8QM_SCU_GPIO0_04_SCU_GPIO0_IOXX_PMIC_A72_ON IMX8QM_SCU_GPIO0_04 1 +-#define IMX8QM_SCU_GPIO0_04_LSIO_GPIO1_IO00 IMX8QM_SCU_GPIO0_04 3 +-#define IMX8QM_SCU_GPIO0_05_SCU_GPIO0_IO05 IMX8QM_SCU_GPIO0_05 0 +-#define IMX8QM_SCU_GPIO0_05_SCU_GPIO0_IOXX_PMIC_A53_ON IMX8QM_SCU_GPIO0_05 1 +-#define IMX8QM_SCU_GPIO0_05_LSIO_GPIO1_IO01 IMX8QM_SCU_GPIO0_05 3 +-#define IMX8QM_SCU_GPIO0_06_SCU_GPIO0_IO06 IMX8QM_SCU_GPIO0_06 0 +-#define IMX8QM_SCU_GPIO0_06_SCU_TPM0_CH0 IMX8QM_SCU_GPIO0_06 1 +-#define IMX8QM_SCU_GPIO0_06_LSIO_GPIO1_IO02 IMX8QM_SCU_GPIO0_06 3 +-#define IMX8QM_SCU_GPIO0_07_SCU_GPIO0_IO07 IMX8QM_SCU_GPIO0_07 0 +-#define IMX8QM_SCU_GPIO0_07_SCU_TPM0_CH1 IMX8QM_SCU_GPIO0_07 1 +-#define IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K IMX8QM_SCU_GPIO0_07 2 +-#define IMX8QM_SCU_GPIO0_07_LSIO_GPIO1_IO03 IMX8QM_SCU_GPIO0_07 3 +-#define IMX8QM_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 IMX8QM_SCU_BOOT_MODE0 0 +-#define IMX8QM_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 IMX8QM_SCU_BOOT_MODE1 0 +-#define IMX8QM_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 IMX8QM_SCU_BOOT_MODE2 0 +-#define IMX8QM_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 IMX8QM_SCU_BOOT_MODE3 0 +-#define IMX8QM_SCU_BOOT_MODE4_SCU_DSC_BOOT_MODE4 IMX8QM_SCU_BOOT_MODE4 0 +-#define IMX8QM_SCU_BOOT_MODE4_SCU_PMIC_I2C_SCL IMX8QM_SCU_BOOT_MODE4 1 +-#define IMX8QM_SCU_BOOT_MODE5_SCU_DSC_BOOT_MODE5 IMX8QM_SCU_BOOT_MODE5 0 +-#define IMX8QM_SCU_BOOT_MODE5_SCU_PMIC_I2C_SDA IMX8QM_SCU_BOOT_MODE5 1 +-#define IMX8QM_LVDS0_GPIO00_LVDS0_GPIO0_IO00 IMX8QM_LVDS0_GPIO00 0 +-#define IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT IMX8QM_LVDS0_GPIO00 1 +-#define IMX8QM_LVDS0_GPIO00_LSIO_GPIO1_IO04 IMX8QM_LVDS0_GPIO00 3 +-#define IMX8QM_LVDS0_GPIO01_LVDS0_GPIO0_IO01 IMX8QM_LVDS0_GPIO01 0 +-#define IMX8QM_LVDS0_GPIO01_LSIO_GPIO1_IO05 IMX8QM_LVDS0_GPIO01 3 +-#define IMX8QM_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL IMX8QM_LVDS0_I2C0_SCL 0 +-#define IMX8QM_LVDS0_I2C0_SCL_LVDS0_GPIO0_IO02 IMX8QM_LVDS0_I2C0_SCL 1 +-#define IMX8QM_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 IMX8QM_LVDS0_I2C0_SCL 3 +-#define IMX8QM_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA IMX8QM_LVDS0_I2C0_SDA 0 +-#define IMX8QM_LVDS0_I2C0_SDA_LVDS0_GPIO0_IO03 IMX8QM_LVDS0_I2C0_SDA 1 +-#define IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 IMX8QM_LVDS0_I2C0_SDA 3 +-#define IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL IMX8QM_LVDS0_I2C1_SCL 0 +-#define IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX IMX8QM_LVDS0_I2C1_SCL 1 +-#define IMX8QM_LVDS0_I2C1_SCL_LSIO_GPIO1_IO08 IMX8QM_LVDS0_I2C1_SCL 3 +-#define IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA IMX8QM_LVDS0_I2C1_SDA 0 +-#define IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX IMX8QM_LVDS0_I2C1_SDA 1 +-#define IMX8QM_LVDS0_I2C1_SDA_LSIO_GPIO1_IO09 IMX8QM_LVDS0_I2C1_SDA 3 +-#define IMX8QM_LVDS1_GPIO00_LVDS1_GPIO0_IO00 IMX8QM_LVDS1_GPIO00 0 +-#define IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT IMX8QM_LVDS1_GPIO00 1 +-#define IMX8QM_LVDS1_GPIO00_LSIO_GPIO1_IO10 IMX8QM_LVDS1_GPIO00 3 +-#define IMX8QM_LVDS1_GPIO01_LVDS1_GPIO0_IO01 IMX8QM_LVDS1_GPIO01 0 +-#define IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 IMX8QM_LVDS1_GPIO01 3 +-#define IMX8QM_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL IMX8QM_LVDS1_I2C0_SCL 0 +-#define IMX8QM_LVDS1_I2C0_SCL_LVDS1_GPIO0_IO02 IMX8QM_LVDS1_I2C0_SCL 1 +-#define IMX8QM_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 IMX8QM_LVDS1_I2C0_SCL 3 +-#define IMX8QM_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA IMX8QM_LVDS1_I2C0_SDA 0 +-#define IMX8QM_LVDS1_I2C0_SDA_LVDS1_GPIO0_IO03 IMX8QM_LVDS1_I2C0_SDA 1 +-#define IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 IMX8QM_LVDS1_I2C0_SDA 3 +-#define IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL IMX8QM_LVDS1_I2C1_SCL 0 +-#define IMX8QM_LVDS1_I2C1_SCL_DMA_UART3_TX IMX8QM_LVDS1_I2C1_SCL 1 +-#define IMX8QM_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14 IMX8QM_LVDS1_I2C1_SCL 3 +-#define IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA IMX8QM_LVDS1_I2C1_SDA 0 +-#define IMX8QM_LVDS1_I2C1_SDA_DMA_UART3_RX IMX8QM_LVDS1_I2C1_SDA 1 +-#define IMX8QM_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15 IMX8QM_LVDS1_I2C1_SDA 3 +-#define IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL IMX8QM_MIPI_DSI0_I2C0_SCL 0 +-#define IMX8QM_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO16 IMX8QM_MIPI_DSI0_I2C0_SCL 3 +-#define IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA IMX8QM_MIPI_DSI0_I2C0_SDA 0 +-#define IMX8QM_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO17 IMX8QM_MIPI_DSI0_I2C0_SDA 3 +-#define IMX8QM_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 IMX8QM_MIPI_DSI0_GPIO0_00 0 +-#define IMX8QM_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT IMX8QM_MIPI_DSI0_GPIO0_00 1 +-#define IMX8QM_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO18 IMX8QM_MIPI_DSI0_GPIO0_00 3 +-#define IMX8QM_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 IMX8QM_MIPI_DSI0_GPIO0_01 0 +-#define IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 IMX8QM_MIPI_DSI0_GPIO0_01 3 +-#define IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL IMX8QM_MIPI_DSI1_I2C0_SCL 0 +-#define IMX8QM_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 IMX8QM_MIPI_DSI1_I2C0_SCL 3 +-#define IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA IMX8QM_MIPI_DSI1_I2C0_SDA 0 +-#define IMX8QM_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 IMX8QM_MIPI_DSI1_I2C0_SDA 3 +-#define IMX8QM_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 IMX8QM_MIPI_DSI1_GPIO0_00 0 +-#define IMX8QM_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT IMX8QM_MIPI_DSI1_GPIO0_00 1 +-#define IMX8QM_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 IMX8QM_MIPI_DSI1_GPIO0_00 3 +-#define IMX8QM_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 IMX8QM_MIPI_DSI1_GPIO0_01 0 +-#define IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 IMX8QM_MIPI_DSI1_GPIO0_01 3 +-#define IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT IMX8QM_MIPI_CSI0_MCLK_OUT 0 +-#define IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 IMX8QM_MIPI_CSI0_MCLK_OUT 3 +-#define IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL IMX8QM_MIPI_CSI0_I2C0_SCL 0 +-#define IMX8QM_MIPI_CSI0_I2C0_SCL_LSIO_GPIO1_IO25 IMX8QM_MIPI_CSI0_I2C0_SCL 3 +-#define IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA IMX8QM_MIPI_CSI0_I2C0_SDA 0 +-#define IMX8QM_MIPI_CSI0_I2C0_SDA_LSIO_GPIO1_IO26 IMX8QM_MIPI_CSI0_I2C0_SDA 3 +-#define IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 IMX8QM_MIPI_CSI0_GPIO0_00 0 +-#define IMX8QM_MIPI_CSI0_GPIO0_00_DMA_I2C0_SCL IMX8QM_MIPI_CSI0_GPIO0_00 1 +-#define IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI1_I2C0_SCL IMX8QM_MIPI_CSI0_GPIO0_00 2 +-#define IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 IMX8QM_MIPI_CSI0_GPIO0_00 3 +-#define IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 IMX8QM_MIPI_CSI0_GPIO0_01 0 +-#define IMX8QM_MIPI_CSI0_GPIO0_01_DMA_I2C0_SDA IMX8QM_MIPI_CSI0_GPIO0_01 1 +-#define IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI1_I2C0_SDA IMX8QM_MIPI_CSI0_GPIO0_01 2 +-#define IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 IMX8QM_MIPI_CSI0_GPIO0_01 3 +-#define IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT IMX8QM_MIPI_CSI1_MCLK_OUT 0 +-#define IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 IMX8QM_MIPI_CSI1_MCLK_OUT 3 +-#define IMX8QM_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 IMX8QM_MIPI_CSI1_GPIO0_00 0 +-#define IMX8QM_MIPI_CSI1_GPIO0_00_DMA_UART4_RX IMX8QM_MIPI_CSI1_GPIO0_00 1 +-#define IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 IMX8QM_MIPI_CSI1_GPIO0_00 3 +-#define IMX8QM_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 IMX8QM_MIPI_CSI1_GPIO0_01 0 +-#define IMX8QM_MIPI_CSI1_GPIO0_01_DMA_UART4_TX IMX8QM_MIPI_CSI1_GPIO0_01 1 +-#define IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 IMX8QM_MIPI_CSI1_GPIO0_01 3 +-#define IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL IMX8QM_MIPI_CSI1_I2C0_SCL 0 +-#define IMX8QM_MIPI_CSI1_I2C0_SCL_LSIO_GPIO2_IO00 IMX8QM_MIPI_CSI1_I2C0_SCL 3 +-#define IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA IMX8QM_MIPI_CSI1_I2C0_SDA 0 +-#define IMX8QM_MIPI_CSI1_I2C0_SDA_LSIO_GPIO2_IO01 IMX8QM_MIPI_CSI1_I2C0_SDA 3 +-#define IMX8QM_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL IMX8QM_HDMI_TX0_TS_SCL 0 +-#define IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL IMX8QM_HDMI_TX0_TS_SCL 1 +-#define IMX8QM_HDMI_TX0_TS_SCL_LSIO_GPIO2_IO02 IMX8QM_HDMI_TX0_TS_SCL 3 +-#define IMX8QM_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA IMX8QM_HDMI_TX0_TS_SDA 0 +-#define IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA IMX8QM_HDMI_TX0_TS_SDA 1 +-#define IMX8QM_HDMI_TX0_TS_SDA_LSIO_GPIO2_IO03 IMX8QM_HDMI_TX0_TS_SDA 3 +-#define IMX8QM_ESAI1_FSR_AUD_ESAI1_FSR IMX8QM_ESAI1_FSR 0 +-#define IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04 IMX8QM_ESAI1_FSR 3 +-#define IMX8QM_ESAI1_FST_AUD_ESAI1_FST IMX8QM_ESAI1_FST 0 +-#define IMX8QM_ESAI1_FST_AUD_SPDIF0_EXT_CLK IMX8QM_ESAI1_FST 1 +-#define IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05 IMX8QM_ESAI1_FST 3 +-#define IMX8QM_ESAI1_SCKR_AUD_ESAI1_SCKR IMX8QM_ESAI1_SCKR 0 +-#define IMX8QM_ESAI1_SCKR_LSIO_GPIO2_IO06 IMX8QM_ESAI1_SCKR 3 +-#define IMX8QM_ESAI1_SCKT_AUD_ESAI1_SCKT IMX8QM_ESAI1_SCKT 0 +-#define IMX8QM_ESAI1_SCKT_AUD_SAI2_RXC IMX8QM_ESAI1_SCKT 1 +-#define IMX8QM_ESAI1_SCKT_AUD_SPDIF0_EXT_CLK IMX8QM_ESAI1_SCKT 2 +-#define IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07 IMX8QM_ESAI1_SCKT 3 +-#define IMX8QM_ESAI1_TX0_AUD_ESAI1_TX0 IMX8QM_ESAI1_TX0 0 +-#define IMX8QM_ESAI1_TX0_AUD_SAI2_RXD IMX8QM_ESAI1_TX0 1 +-#define IMX8QM_ESAI1_TX0_AUD_SPDIF0_RX IMX8QM_ESAI1_TX0 2 +-#define IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08 IMX8QM_ESAI1_TX0 3 +-#define IMX8QM_ESAI1_TX1_AUD_ESAI1_TX1 IMX8QM_ESAI1_TX1 0 +-#define IMX8QM_ESAI1_TX1_AUD_SAI2_RXFS IMX8QM_ESAI1_TX1 1 +-#define IMX8QM_ESAI1_TX1_AUD_SPDIF0_TX IMX8QM_ESAI1_TX1 2 +-#define IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09 IMX8QM_ESAI1_TX1 3 +-#define IMX8QM_ESAI1_TX2_RX3_AUD_ESAI1_TX2_RX3 IMX8QM_ESAI1_TX2_RX3 0 +-#define IMX8QM_ESAI1_TX2_RX3_AUD_SPDIF0_RX IMX8QM_ESAI1_TX2_RX3 1 +-#define IMX8QM_ESAI1_TX2_RX3_LSIO_GPIO2_IO10 IMX8QM_ESAI1_TX2_RX3 3 +-#define IMX8QM_ESAI1_TX3_RX2_AUD_ESAI1_TX3_RX2 IMX8QM_ESAI1_TX3_RX2 0 +-#define IMX8QM_ESAI1_TX3_RX2_AUD_SPDIF0_TX IMX8QM_ESAI1_TX3_RX2 1 +-#define IMX8QM_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 IMX8QM_ESAI1_TX3_RX2 3 +-#define IMX8QM_ESAI1_TX4_RX1_AUD_ESAI1_TX4_RX1 IMX8QM_ESAI1_TX4_RX1 0 +-#define IMX8QM_ESAI1_TX4_RX1_LSIO_GPIO2_IO12 IMX8QM_ESAI1_TX4_RX1 3 +-#define IMX8QM_ESAI1_TX5_RX0_AUD_ESAI1_TX5_RX0 IMX8QM_ESAI1_TX5_RX0 0 +-#define IMX8QM_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 IMX8QM_ESAI1_TX5_RX0 3 +-#define IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX IMX8QM_SPDIF0_RX 0 +-#define IMX8QM_SPDIF0_RX_AUD_MQS_R IMX8QM_SPDIF0_RX 1 +-#define IMX8QM_SPDIF0_RX_AUD_ACM_MCLK_IN1 IMX8QM_SPDIF0_RX 2 +-#define IMX8QM_SPDIF0_RX_LSIO_GPIO2_IO14 IMX8QM_SPDIF0_RX 3 +-#define IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX IMX8QM_SPDIF0_TX 0 +-#define IMX8QM_SPDIF0_TX_AUD_MQS_L IMX8QM_SPDIF0_TX 1 +-#define IMX8QM_SPDIF0_TX_AUD_ACM_MCLK_OUT1 IMX8QM_SPDIF0_TX 2 +-#define IMX8QM_SPDIF0_TX_LSIO_GPIO2_IO15 IMX8QM_SPDIF0_TX 3 +-#define IMX8QM_SPDIF0_EXT_CLK_AUD_SPDIF0_EXT_CLK IMX8QM_SPDIF0_EXT_CLK 0 +-#define IMX8QM_SPDIF0_EXT_CLK_DMA_DMA0_REQ_IN0 IMX8QM_SPDIF0_EXT_CLK 1 +-#define IMX8QM_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 IMX8QM_SPDIF0_EXT_CLK 3 +-#define IMX8QM_SPI3_SCK_DMA_SPI3_SCK IMX8QM_SPI3_SCK 0 +-#define IMX8QM_SPI3_SCK_LSIO_GPIO2_IO17 IMX8QM_SPI3_SCK 3 +-#define IMX8QM_SPI3_SDO_DMA_SPI3_SDO IMX8QM_SPI3_SDO 0 +-#define IMX8QM_SPI3_SDO_DMA_FTM_CH0 IMX8QM_SPI3_SDO 1 +-#define IMX8QM_SPI3_SDO_LSIO_GPIO2_IO18 IMX8QM_SPI3_SDO 3 +-#define IMX8QM_SPI3_SDI_DMA_SPI3_SDI IMX8QM_SPI3_SDI 0 +-#define IMX8QM_SPI3_SDI_DMA_FTM_CH1 IMX8QM_SPI3_SDI 1 +-#define IMX8QM_SPI3_SDI_LSIO_GPIO2_IO19 IMX8QM_SPI3_SDI 3 +-#define IMX8QM_SPI3_CS0_DMA_SPI3_CS0 IMX8QM_SPI3_CS0 0 +-#define IMX8QM_SPI3_CS0_DMA_FTM_CH2 IMX8QM_SPI3_CS0 1 +-#define IMX8QM_SPI3_CS0_LSIO_GPIO2_IO20 IMX8QM_SPI3_CS0 3 +-#define IMX8QM_SPI3_CS1_DMA_SPI3_CS1 IMX8QM_SPI3_CS1 0 +-#define IMX8QM_SPI3_CS1_LSIO_GPIO2_IO21 IMX8QM_SPI3_CS1 3 +-#define IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR IMX8QM_ESAI0_FSR 0 +-#define IMX8QM_ESAI0_FSR_LSIO_GPIO2_IO22 IMX8QM_ESAI0_FSR 3 +-#define IMX8QM_ESAI0_FST_AUD_ESAI0_FST IMX8QM_ESAI0_FST 0 +-#define IMX8QM_ESAI0_FST_LSIO_GPIO2_IO23 IMX8QM_ESAI0_FST 3 +-#define IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR IMX8QM_ESAI0_SCKR 0 +-#define IMX8QM_ESAI0_SCKR_LSIO_GPIO2_IO24 IMX8QM_ESAI0_SCKR 3 +-#define IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT IMX8QM_ESAI0_SCKT 0 +-#define IMX8QM_ESAI0_SCKT_LSIO_GPIO2_IO25 IMX8QM_ESAI0_SCKT 3 +-#define IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 IMX8QM_ESAI0_TX0 0 +-#define IMX8QM_ESAI0_TX0_LSIO_GPIO2_IO26 IMX8QM_ESAI0_TX0 3 +-#define IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 IMX8QM_ESAI0_TX1 0 +-#define IMX8QM_ESAI0_TX1_LSIO_GPIO2_IO27 IMX8QM_ESAI0_TX1 3 +-#define IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 IMX8QM_ESAI0_TX2_RX3 0 +-#define IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 IMX8QM_ESAI0_TX2_RX3 3 +-#define IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 IMX8QM_ESAI0_TX3_RX2 0 +-#define IMX8QM_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 IMX8QM_ESAI0_TX3_RX2 3 +-#define IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 IMX8QM_ESAI0_TX4_RX1 0 +-#define IMX8QM_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 IMX8QM_ESAI0_TX4_RX1 3 +-#define IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 IMX8QM_ESAI0_TX5_RX0 0 +-#define IMX8QM_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 IMX8QM_ESAI0_TX5_RX0 3 +-#define IMX8QM_MCLK_IN0_AUD_ACM_MCLK_IN0 IMX8QM_MCLK_IN0 0 +-#define IMX8QM_MCLK_IN0_AUD_ESAI0_RX_HF_CLK IMX8QM_MCLK_IN0 1 +-#define IMX8QM_MCLK_IN0_AUD_ESAI1_RX_HF_CLK IMX8QM_MCLK_IN0 2 +-#define IMX8QM_MCLK_IN0_LSIO_GPIO3_IO00 IMX8QM_MCLK_IN0 3 +-#define IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 IMX8QM_MCLK_OUT0 0 +-#define IMX8QM_MCLK_OUT0_AUD_ESAI0_TX_HF_CLK IMX8QM_MCLK_OUT0 1 +-#define IMX8QM_MCLK_OUT0_AUD_ESAI1_TX_HF_CLK IMX8QM_MCLK_OUT0 2 +-#define IMX8QM_MCLK_OUT0_LSIO_GPIO3_IO01 IMX8QM_MCLK_OUT0 3 +-#define IMX8QM_SPI0_SCK_DMA_SPI0_SCK IMX8QM_SPI0_SCK 0 +-#define IMX8QM_SPI0_SCK_AUD_SAI0_RXC IMX8QM_SPI0_SCK 1 +-#define IMX8QM_SPI0_SCK_LSIO_GPIO3_IO02 IMX8QM_SPI0_SCK 3 +-#define IMX8QM_SPI0_SDO_DMA_SPI0_SDO IMX8QM_SPI0_SDO 0 +-#define IMX8QM_SPI0_SDO_AUD_SAI0_TXD IMX8QM_SPI0_SDO 1 +-#define IMX8QM_SPI0_SDO_LSIO_GPIO3_IO03 IMX8QM_SPI0_SDO 3 +-#define IMX8QM_SPI0_SDI_DMA_SPI0_SDI IMX8QM_SPI0_SDI 0 +-#define IMX8QM_SPI0_SDI_AUD_SAI0_RXD IMX8QM_SPI0_SDI 1 +-#define IMX8QM_SPI0_SDI_LSIO_GPIO3_IO04 IMX8QM_SPI0_SDI 3 +-#define IMX8QM_SPI0_CS0_DMA_SPI0_CS0 IMX8QM_SPI0_CS0 0 +-#define IMX8QM_SPI0_CS0_AUD_SAI0_RXFS IMX8QM_SPI0_CS0 1 +-#define IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05 IMX8QM_SPI0_CS0 3 +-#define IMX8QM_SPI0_CS1_DMA_SPI0_CS1 IMX8QM_SPI0_CS1 0 +-#define IMX8QM_SPI0_CS1_AUD_SAI0_TXC IMX8QM_SPI0_CS1 1 +-#define IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06 IMX8QM_SPI0_CS1 3 +-#define IMX8QM_SPI2_SCK_DMA_SPI2_SCK IMX8QM_SPI2_SCK 0 +-#define IMX8QM_SPI2_SCK_LSIO_GPIO3_IO07 IMX8QM_SPI2_SCK 3 +-#define IMX8QM_SPI2_SDO_DMA_SPI2_SDO IMX8QM_SPI2_SDO 0 +-#define IMX8QM_SPI2_SDO_LSIO_GPIO3_IO08 IMX8QM_SPI2_SDO 3 +-#define IMX8QM_SPI2_SDI_DMA_SPI2_SDI IMX8QM_SPI2_SDI 0 +-#define IMX8QM_SPI2_SDI_LSIO_GPIO3_IO09 IMX8QM_SPI2_SDI 3 +-#define IMX8QM_SPI2_CS0_DMA_SPI2_CS0 IMX8QM_SPI2_CS0 0 +-#define IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 IMX8QM_SPI2_CS0 3 +-#define IMX8QM_SPI2_CS1_DMA_SPI2_CS1 IMX8QM_SPI2_CS1 0 +-#define IMX8QM_SPI2_CS1_AUD_SAI0_TXFS IMX8QM_SPI2_CS1 1 +-#define IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11 IMX8QM_SPI2_CS1 3 +-#define IMX8QM_SAI1_RXC_AUD_SAI1_RXC IMX8QM_SAI1_RXC 0 +-#define IMX8QM_SAI1_RXC_AUD_SAI0_TXD IMX8QM_SAI1_RXC 1 +-#define IMX8QM_SAI1_RXC_LSIO_GPIO3_IO12 IMX8QM_SAI1_RXC 3 +-#define IMX8QM_SAI1_RXD_AUD_SAI1_RXD IMX8QM_SAI1_RXD 0 +-#define IMX8QM_SAI1_RXD_AUD_SAI0_TXFS IMX8QM_SAI1_RXD 1 +-#define IMX8QM_SAI1_RXD_LSIO_GPIO3_IO13 IMX8QM_SAI1_RXD 3 +-#define IMX8QM_SAI1_RXFS_AUD_SAI1_RXFS IMX8QM_SAI1_RXFS 0 +-#define IMX8QM_SAI1_RXFS_AUD_SAI0_RXD IMX8QM_SAI1_RXFS 1 +-#define IMX8QM_SAI1_RXFS_LSIO_GPIO3_IO14 IMX8QM_SAI1_RXFS 3 +-#define IMX8QM_SAI1_TXC_AUD_SAI1_TXC IMX8QM_SAI1_TXC 0 +-#define IMX8QM_SAI1_TXC_AUD_SAI0_TXC IMX8QM_SAI1_TXC 1 +-#define IMX8QM_SAI1_TXC_LSIO_GPIO3_IO15 IMX8QM_SAI1_TXC 3 +-#define IMX8QM_SAI1_TXD_AUD_SAI1_TXD IMX8QM_SAI1_TXD 0 +-#define IMX8QM_SAI1_TXD_AUD_SAI1_RXC IMX8QM_SAI1_TXD 1 +-#define IMX8QM_SAI1_TXD_LSIO_GPIO3_IO16 IMX8QM_SAI1_TXD 3 +-#define IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS IMX8QM_SAI1_TXFS 0 +-#define IMX8QM_SAI1_TXFS_AUD_SAI1_RXFS IMX8QM_SAI1_TXFS 1 +-#define IMX8QM_SAI1_TXFS_LSIO_GPIO3_IO17 IMX8QM_SAI1_TXFS 3 +-#define IMX8QM_ADC_IN7_DMA_ADC1_IN3 IMX8QM_ADC_IN7 0 +-#define IMX8QM_ADC_IN7_DMA_SPI1_CS1 IMX8QM_ADC_IN7 1 +-#define IMX8QM_ADC_IN7_LSIO_KPP0_ROW3 IMX8QM_ADC_IN7 2 +-#define IMX8QM_ADC_IN7_LSIO_GPIO3_IO25 IMX8QM_ADC_IN7 3 +-#define IMX8QM_ADC_IN6_DMA_ADC1_IN2 IMX8QM_ADC_IN6 0 +-#define IMX8QM_ADC_IN6_DMA_SPI1_CS0 IMX8QM_ADC_IN6 1 +-#define IMX8QM_ADC_IN6_LSIO_KPP0_ROW2 IMX8QM_ADC_IN6 2 +-#define IMX8QM_ADC_IN6_LSIO_GPIO3_IO24 IMX8QM_ADC_IN6 3 +-#define IMX8QM_ADC_IN5_DMA_ADC1_IN1 IMX8QM_ADC_IN5 0 +-#define IMX8QM_ADC_IN5_DMA_SPI1_SDI IMX8QM_ADC_IN5 1 +-#define IMX8QM_ADC_IN5_LSIO_KPP0_ROW1 IMX8QM_ADC_IN5 2 +-#define IMX8QM_ADC_IN5_LSIO_GPIO3_IO23 IMX8QM_ADC_IN5 3 +-#define IMX8QM_ADC_IN4_DMA_ADC1_IN0 IMX8QM_ADC_IN4 0 +-#define IMX8QM_ADC_IN4_DMA_SPI1_SDO IMX8QM_ADC_IN4 1 +-#define IMX8QM_ADC_IN4_LSIO_KPP0_ROW0 IMX8QM_ADC_IN4 2 +-#define IMX8QM_ADC_IN4_LSIO_GPIO3_IO22 IMX8QM_ADC_IN4 3 +-#define IMX8QM_ADC_IN3_DMA_ADC0_IN3 IMX8QM_ADC_IN3 0 +-#define IMX8QM_ADC_IN3_DMA_SPI1_SCK IMX8QM_ADC_IN3 1 +-#define IMX8QM_ADC_IN3_LSIO_KPP0_COL3 IMX8QM_ADC_IN3 2 +-#define IMX8QM_ADC_IN3_LSIO_GPIO3_IO21 IMX8QM_ADC_IN3 3 +-#define IMX8QM_ADC_IN2_DMA_ADC0_IN2 IMX8QM_ADC_IN2 0 +-#define IMX8QM_ADC_IN2_LSIO_KPP0_COL2 IMX8QM_ADC_IN2 2 +-#define IMX8QM_ADC_IN2_LSIO_GPIO3_IO20 IMX8QM_ADC_IN2 3 +-#define IMX8QM_ADC_IN1_DMA_ADC0_IN1 IMX8QM_ADC_IN1 0 +-#define IMX8QM_ADC_IN1_LSIO_KPP0_COL1 IMX8QM_ADC_IN1 2 +-#define IMX8QM_ADC_IN1_LSIO_GPIO3_IO19 IMX8QM_ADC_IN1 3 +-#define IMX8QM_ADC_IN0_DMA_ADC0_IN0 IMX8QM_ADC_IN0 0 +-#define IMX8QM_ADC_IN0_LSIO_KPP0_COL0 IMX8QM_ADC_IN0 2 +-#define IMX8QM_ADC_IN0_LSIO_GPIO3_IO18 IMX8QM_ADC_IN0 3 +-#define IMX8QM_MLB_SIG_CONN_MLB_SIG IMX8QM_MLB_SIG 0 +-#define IMX8QM_MLB_SIG_AUD_SAI3_RXC IMX8QM_MLB_SIG 1 +-#define IMX8QM_MLB_SIG_LSIO_GPIO3_IO26 IMX8QM_MLB_SIG 3 +-#define IMX8QM_MLB_CLK_CONN_MLB_CLK IMX8QM_MLB_CLK 0 +-#define IMX8QM_MLB_CLK_AUD_SAI3_RXFS IMX8QM_MLB_CLK 1 +-#define IMX8QM_MLB_CLK_LSIO_GPIO3_IO27 IMX8QM_MLB_CLK 3 +-#define IMX8QM_MLB_DATA_CONN_MLB_DATA IMX8QM_MLB_DATA 0 +-#define IMX8QM_MLB_DATA_AUD_SAI3_RXD IMX8QM_MLB_DATA 1 +-#define IMX8QM_MLB_DATA_LSIO_GPIO3_IO28 IMX8QM_MLB_DATA 3 +-#define IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX IMX8QM_FLEXCAN0_RX 0 +-#define IMX8QM_FLEXCAN0_RX_LSIO_GPIO3_IO29 IMX8QM_FLEXCAN0_RX 3 +-#define IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX IMX8QM_FLEXCAN0_TX 0 +-#define IMX8QM_FLEXCAN0_TX_LSIO_GPIO3_IO30 IMX8QM_FLEXCAN0_TX 3 +-#define IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX IMX8QM_FLEXCAN1_RX 0 +-#define IMX8QM_FLEXCAN1_RX_LSIO_GPIO3_IO31 IMX8QM_FLEXCAN1_RX 3 +-#define IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX IMX8QM_FLEXCAN1_TX 0 +-#define IMX8QM_FLEXCAN1_TX_LSIO_GPIO4_IO00 IMX8QM_FLEXCAN1_TX 3 +-#define IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX IMX8QM_FLEXCAN2_RX 0 +-#define IMX8QM_FLEXCAN2_RX_LSIO_GPIO4_IO01 IMX8QM_FLEXCAN2_RX 3 +-#define IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX IMX8QM_FLEXCAN2_TX 0 +-#define IMX8QM_FLEXCAN2_TX_LSIO_GPIO4_IO02 IMX8QM_FLEXCAN2_TX 3 +-#define IMX8QM_USB_SS3_TC0_DMA_I2C1_SCL IMX8QM_USB_SS3_TC0 0 +-#define IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8QM_USB_SS3_TC0 1 +-#define IMX8QM_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8QM_USB_SS3_TC0 3 +-#define IMX8QM_USB_SS3_TC1_DMA_I2C1_SCL IMX8QM_USB_SS3_TC1 0 +-#define IMX8QM_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8QM_USB_SS3_TC1 1 +-#define IMX8QM_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8QM_USB_SS3_TC1 3 +-#define IMX8QM_USB_SS3_TC2_DMA_I2C1_SDA IMX8QM_USB_SS3_TC2 0 +-#define IMX8QM_USB_SS3_TC2_CONN_USB_OTG1_OC IMX8QM_USB_SS3_TC2 1 +-#define IMX8QM_USB_SS3_TC2_LSIO_GPIO4_IO05 IMX8QM_USB_SS3_TC2 3 +-#define IMX8QM_USB_SS3_TC3_DMA_I2C1_SDA IMX8QM_USB_SS3_TC3 0 +-#define IMX8QM_USB_SS3_TC3_CONN_USB_OTG2_OC IMX8QM_USB_SS3_TC3 1 +-#define IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 IMX8QM_USB_SS3_TC3 3 +-#define IMX8QM_USDHC1_RESET_B_CONN_USDHC1_RESET_B IMX8QM_USDHC1_RESET_B 0 +-#define IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 IMX8QM_USDHC1_RESET_B 3 +-#define IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT IMX8QM_USDHC1_VSELECT 0 +-#define IMX8QM_USDHC1_VSELECT_LSIO_GPIO4_IO08 IMX8QM_USDHC1_VSELECT 3 +-#define IMX8QM_USDHC2_RESET_B_CONN_USDHC2_RESET_B IMX8QM_USDHC2_RESET_B 0 +-#define IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 IMX8QM_USDHC2_RESET_B 3 +-#define IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT IMX8QM_USDHC2_VSELECT 0 +-#define IMX8QM_USDHC2_VSELECT_LSIO_GPIO4_IO10 IMX8QM_USDHC2_VSELECT 3 +-#define IMX8QM_USDHC2_WP_CONN_USDHC2_WP IMX8QM_USDHC2_WP 0 +-#define IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 IMX8QM_USDHC2_WP 3 +-#define IMX8QM_USDHC2_CD_B_CONN_USDHC2_CD_B IMX8QM_USDHC2_CD_B 0 +-#define IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 IMX8QM_USDHC2_CD_B 3 +-#define IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO IMX8QM_ENET0_MDIO 0 +-#define IMX8QM_ENET0_MDIO_DMA_I2C4_SDA IMX8QM_ENET0_MDIO 1 +-#define IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13 IMX8QM_ENET0_MDIO 3 +-#define IMX8QM_ENET0_MDC_CONN_ENET0_MDC IMX8QM_ENET0_MDC 0 +-#define IMX8QM_ENET0_MDC_DMA_I2C4_SCL IMX8QM_ENET0_MDC 1 +-#define IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14 IMX8QM_ENET0_MDC 3 +-#define IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M IMX8QM_ENET0_REFCLK_125M_25M 0 +-#define IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS IMX8QM_ENET0_REFCLK_125M_25M 1 +-#define IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 IMX8QM_ENET0_REFCLK_125M_25M 3 +-#define IMX8QM_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M IMX8QM_ENET1_REFCLK_125M_25M 0 +-#define IMX8QM_ENET1_REFCLK_125M_25M_CONN_ENET1_PPS IMX8QM_ENET1_REFCLK_125M_25M 1 +-#define IMX8QM_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 IMX8QM_ENET1_REFCLK_125M_25M 3 +-#define IMX8QM_ENET1_MDIO_CONN_ENET1_MDIO IMX8QM_ENET1_MDIO 0 +-#define IMX8QM_ENET1_MDIO_DMA_I2C4_SDA IMX8QM_ENET1_MDIO 1 +-#define IMX8QM_ENET1_MDIO_LSIO_GPIO4_IO17 IMX8QM_ENET1_MDIO 3 +-#define IMX8QM_ENET1_MDC_CONN_ENET1_MDC IMX8QM_ENET1_MDC 0 +-#define IMX8QM_ENET1_MDC_DMA_I2C4_SCL IMX8QM_ENET1_MDC 1 +-#define IMX8QM_ENET1_MDC_LSIO_GPIO4_IO18 IMX8QM_ENET1_MDC 3 +-#define IMX8QM_QSPI1A_SS0_B_LSIO_QSPI1A_SS0_B IMX8QM_QSPI1A_SS0_B 0 +-#define IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 IMX8QM_QSPI1A_SS0_B 3 +-#define IMX8QM_QSPI1A_SS1_B_LSIO_QSPI1A_SS1_B IMX8QM_QSPI1A_SS1_B 0 +-#define IMX8QM_QSPI1A_SS1_B_LSIO_QSPI1A_SCLK2 IMX8QM_QSPI1A_SS1_B 1 +-#define IMX8QM_QSPI1A_SS1_B_LSIO_GPIO4_IO20 IMX8QM_QSPI1A_SS1_B 3 +-#define IMX8QM_QSPI1A_SCLK_LSIO_QSPI1A_SCLK IMX8QM_QSPI1A_SCLK 0 +-#define IMX8QM_QSPI1A_SCLK_LSIO_GPIO4_IO21 IMX8QM_QSPI1A_SCLK 3 +-#define IMX8QM_QSPI1A_DQS_LSIO_QSPI1A_DQS IMX8QM_QSPI1A_DQS 0 +-#define IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 IMX8QM_QSPI1A_DQS 3 +-#define IMX8QM_QSPI1A_DATA3_LSIO_QSPI1A_DATA3 IMX8QM_QSPI1A_DATA3 0 +-#define IMX8QM_QSPI1A_DATA3_DMA_I2C1_SDA IMX8QM_QSPI1A_DATA3 1 +-#define IMX8QM_QSPI1A_DATA3_CONN_USB_OTG1_OC IMX8QM_QSPI1A_DATA3 2 +-#define IMX8QM_QSPI1A_DATA3_LSIO_GPIO4_IO23 IMX8QM_QSPI1A_DATA3 3 +-#define IMX8QM_QSPI1A_DATA2_LSIO_QSPI1A_DATA2 IMX8QM_QSPI1A_DATA2 0 +-#define IMX8QM_QSPI1A_DATA2_DMA_I2C1_SCL IMX8QM_QSPI1A_DATA2 1 +-#define IMX8QM_QSPI1A_DATA2_CONN_USB_OTG2_PWR IMX8QM_QSPI1A_DATA2 2 +-#define IMX8QM_QSPI1A_DATA2_LSIO_GPIO4_IO24 IMX8QM_QSPI1A_DATA2 3 +-#define IMX8QM_QSPI1A_DATA1_LSIO_QSPI1A_DATA1 IMX8QM_QSPI1A_DATA1 0 +-#define IMX8QM_QSPI1A_DATA1_DMA_I2C1_SDA IMX8QM_QSPI1A_DATA1 1 +-#define IMX8QM_QSPI1A_DATA1_CONN_USB_OTG2_OC IMX8QM_QSPI1A_DATA1 2 +-#define IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 IMX8QM_QSPI1A_DATA1 3 +-#define IMX8QM_QSPI1A_DATA0_LSIO_QSPI1A_DATA0 IMX8QM_QSPI1A_DATA0 0 +-#define IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 IMX8QM_QSPI1A_DATA0 3 +-#define IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 IMX8QM_QSPI0A_DATA0 0 +-#define IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 IMX8QM_QSPI0A_DATA1 0 +-#define IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 IMX8QM_QSPI0A_DATA2 0 +-#define IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 IMX8QM_QSPI0A_DATA3 0 +-#define IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS IMX8QM_QSPI0A_DQS 0 +-#define IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B IMX8QM_QSPI0A_SS0_B 0 +-#define IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B IMX8QM_QSPI0A_SS1_B 0 +-#define IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SCLK2 IMX8QM_QSPI0A_SS1_B 1 +-#define IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK IMX8QM_QSPI0A_SCLK 0 +-#define IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK IMX8QM_QSPI0B_SCLK 0 +-#define IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 IMX8QM_QSPI0B_DATA0 0 +-#define IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 IMX8QM_QSPI0B_DATA1 0 +-#define IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 IMX8QM_QSPI0B_DATA2 0 +-#define IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 IMX8QM_QSPI0B_DATA3 0 +-#define IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS IMX8QM_QSPI0B_DQS 0 +-#define IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B IMX8QM_QSPI0B_SS0_B 0 +-#define IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B IMX8QM_QSPI0B_SS1_B 0 +-#define IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SCLK2 IMX8QM_QSPI0B_SS1_B 1 +-#define IMX8QM_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8QM_PCIE_CTRL0_CLKREQ_B 0 +-#define IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 IMX8QM_PCIE_CTRL0_CLKREQ_B 3 +-#define IMX8QM_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8QM_PCIE_CTRL0_WAKE_B 0 +-#define IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 IMX8QM_PCIE_CTRL0_WAKE_B 3 +-#define IMX8QM_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8QM_PCIE_CTRL0_PERST_B 0 +-#define IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 IMX8QM_PCIE_CTRL0_PERST_B 3 +-#define IMX8QM_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B IMX8QM_PCIE_CTRL1_CLKREQ_B 0 +-#define IMX8QM_PCIE_CTRL1_CLKREQ_B_DMA_I2C1_SDA IMX8QM_PCIE_CTRL1_CLKREQ_B 1 +-#define IMX8QM_PCIE_CTRL1_CLKREQ_B_CONN_USB_OTG2_OC IMX8QM_PCIE_CTRL1_CLKREQ_B 2 +-#define IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 IMX8QM_PCIE_CTRL1_CLKREQ_B 3 +-#define IMX8QM_PCIE_CTRL1_WAKE_B_HSIO_PCIE1_WAKE_B IMX8QM_PCIE_CTRL1_WAKE_B 0 +-#define IMX8QM_PCIE_CTRL1_WAKE_B_DMA_I2C1_SCL IMX8QM_PCIE_CTRL1_WAKE_B 1 +-#define IMX8QM_PCIE_CTRL1_WAKE_B_CONN_USB_OTG2_PWR IMX8QM_PCIE_CTRL1_WAKE_B 2 +-#define IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 IMX8QM_PCIE_CTRL1_WAKE_B 3 +-#define IMX8QM_PCIE_CTRL1_PERST_B_HSIO_PCIE1_PERST_B IMX8QM_PCIE_CTRL1_PERST_B 0 +-#define IMX8QM_PCIE_CTRL1_PERST_B_DMA_I2C1_SCL IMX8QM_PCIE_CTRL1_PERST_B 1 +-#define IMX8QM_PCIE_CTRL1_PERST_B_CONN_USB_OTG1_PWR IMX8QM_PCIE_CTRL1_PERST_B 2 +-#define IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 IMX8QM_PCIE_CTRL1_PERST_B 3 +-#define IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA IMX8QM_USB_HSIC0_DATA 0 +-#define IMX8QM_USB_HSIC0_DATA_DMA_I2C1_SDA IMX8QM_USB_HSIC0_DATA 1 +-#define IMX8QM_USB_HSIC0_DATA_LSIO_GPIO5_IO01 IMX8QM_USB_HSIC0_DATA 3 +-#define IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE IMX8QM_USB_HSIC0_STROBE 0 +-#define IMX8QM_USB_HSIC0_STROBE_DMA_I2C1_SCL IMX8QM_USB_HSIC0_STROBE 1 +-#define IMX8QM_USB_HSIC0_STROBE_LSIO_GPIO5_IO02 IMX8QM_USB_HSIC0_STROBE 3 +-#define IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK IMX8QM_EMMC0_CLK 0 +-#define IMX8QM_EMMC0_CLK_CONN_NAND_READY_B IMX8QM_EMMC0_CLK 1 +-#define IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD IMX8QM_EMMC0_CMD 0 +-#define IMX8QM_EMMC0_CMD_CONN_NAND_DQS IMX8QM_EMMC0_CMD 1 +-#define IMX8QM_EMMC0_CMD_AUD_MQS_R IMX8QM_EMMC0_CMD 2 +-#define IMX8QM_EMMC0_CMD_LSIO_GPIO5_IO03 IMX8QM_EMMC0_CMD 3 +-#define IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 IMX8QM_EMMC0_DATA0 0 +-#define IMX8QM_EMMC0_DATA0_CONN_NAND_DATA00 IMX8QM_EMMC0_DATA0 1 +-#define IMX8QM_EMMC0_DATA0_LSIO_GPIO5_IO04 IMX8QM_EMMC0_DATA0 3 +-#define IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 IMX8QM_EMMC0_DATA1 0 +-#define IMX8QM_EMMC0_DATA1_CONN_NAND_DATA01 IMX8QM_EMMC0_DATA1 1 +-#define IMX8QM_EMMC0_DATA1_LSIO_GPIO5_IO05 IMX8QM_EMMC0_DATA1 3 +-#define IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 IMX8QM_EMMC0_DATA2 0 +-#define IMX8QM_EMMC0_DATA2_CONN_NAND_DATA02 IMX8QM_EMMC0_DATA2 1 +-#define IMX8QM_EMMC0_DATA2_LSIO_GPIO5_IO06 IMX8QM_EMMC0_DATA2 3 +-#define IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 IMX8QM_EMMC0_DATA3 0 +-#define IMX8QM_EMMC0_DATA3_CONN_NAND_DATA03 IMX8QM_EMMC0_DATA3 1 +-#define IMX8QM_EMMC0_DATA3_LSIO_GPIO5_IO07 IMX8QM_EMMC0_DATA3 3 +-#define IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 IMX8QM_EMMC0_DATA4 0 +-#define IMX8QM_EMMC0_DATA4_CONN_NAND_DATA04 IMX8QM_EMMC0_DATA4 1 +-#define IMX8QM_EMMC0_DATA4_LSIO_GPIO5_IO08 IMX8QM_EMMC0_DATA4 3 +-#define IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 IMX8QM_EMMC0_DATA5 0 +-#define IMX8QM_EMMC0_DATA5_CONN_NAND_DATA05 IMX8QM_EMMC0_DATA5 1 +-#define IMX8QM_EMMC0_DATA5_LSIO_GPIO5_IO09 IMX8QM_EMMC0_DATA5 3 +-#define IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 IMX8QM_EMMC0_DATA6 0 +-#define IMX8QM_EMMC0_DATA6_CONN_NAND_DATA06 IMX8QM_EMMC0_DATA6 1 +-#define IMX8QM_EMMC0_DATA6_LSIO_GPIO5_IO10 IMX8QM_EMMC0_DATA6 3 +-#define IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 IMX8QM_EMMC0_DATA7 0 +-#define IMX8QM_EMMC0_DATA7_CONN_NAND_DATA07 IMX8QM_EMMC0_DATA7 1 +-#define IMX8QM_EMMC0_DATA7_LSIO_GPIO5_IO11 IMX8QM_EMMC0_DATA7 3 +-#define IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE IMX8QM_EMMC0_STROBE 0 +-#define IMX8QM_EMMC0_STROBE_CONN_NAND_CLE IMX8QM_EMMC0_STROBE 1 +-#define IMX8QM_EMMC0_STROBE_LSIO_GPIO5_IO12 IMX8QM_EMMC0_STROBE 3 +-#define IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B IMX8QM_EMMC0_RESET_B 0 +-#define IMX8QM_EMMC0_RESET_B_CONN_NAND_WP_B IMX8QM_EMMC0_RESET_B 1 +-#define IMX8QM_EMMC0_RESET_B_CONN_USDHC1_VSELECT IMX8QM_EMMC0_RESET_B 2 +-#define IMX8QM_EMMC0_RESET_B_LSIO_GPIO5_IO13 IMX8QM_EMMC0_RESET_B 3 +-#define IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK IMX8QM_USDHC1_CLK 0 +-#define IMX8QM_USDHC1_CLK_AUD_MQS_R IMX8QM_USDHC1_CLK 1 +-#define IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD IMX8QM_USDHC1_CMD 0 +-#define IMX8QM_USDHC1_CMD_AUD_MQS_L IMX8QM_USDHC1_CMD 1 +-#define IMX8QM_USDHC1_CMD_LSIO_GPIO5_IO14 IMX8QM_USDHC1_CMD 3 +-#define IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 IMX8QM_USDHC1_DATA0 0 +-#define IMX8QM_USDHC1_DATA0_CONN_NAND_RE_N IMX8QM_USDHC1_DATA0 1 +-#define IMX8QM_USDHC1_DATA0_LSIO_GPIO5_IO15 IMX8QM_USDHC1_DATA0 3 +-#define IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 IMX8QM_USDHC1_DATA1 0 +-#define IMX8QM_USDHC1_DATA1_CONN_NAND_RE_P IMX8QM_USDHC1_DATA1 1 +-#define IMX8QM_USDHC1_DATA1_LSIO_GPIO5_IO16 IMX8QM_USDHC1_DATA1 3 +-#define IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 IMX8QM_USDHC1_DATA2 0 +-#define IMX8QM_USDHC1_DATA2_CONN_NAND_DQS_N IMX8QM_USDHC1_DATA2 1 +-#define IMX8QM_USDHC1_DATA2_LSIO_GPIO5_IO17 IMX8QM_USDHC1_DATA2 3 +-#define IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 IMX8QM_USDHC1_DATA3 0 +-#define IMX8QM_USDHC1_DATA3_CONN_NAND_DQS_P IMX8QM_USDHC1_DATA3 1 +-#define IMX8QM_USDHC1_DATA3_LSIO_GPIO5_IO18 IMX8QM_USDHC1_DATA3 3 +-#define IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 IMX8QM_USDHC1_DATA4 0 +-#define IMX8QM_USDHC1_DATA4_CONN_NAND_CE0_B IMX8QM_USDHC1_DATA4 1 +-#define IMX8QM_USDHC1_DATA4_AUD_MQS_R IMX8QM_USDHC1_DATA4 2 +-#define IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19 IMX8QM_USDHC1_DATA4 3 +-#define IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 IMX8QM_USDHC1_DATA5 0 +-#define IMX8QM_USDHC1_DATA5_CONN_NAND_RE_B IMX8QM_USDHC1_DATA5 1 +-#define IMX8QM_USDHC1_DATA5_AUD_MQS_L IMX8QM_USDHC1_DATA5 2 +-#define IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20 IMX8QM_USDHC1_DATA5 3 +-#define IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 IMX8QM_USDHC1_DATA6 0 +-#define IMX8QM_USDHC1_DATA6_CONN_NAND_WE_B IMX8QM_USDHC1_DATA6 1 +-#define IMX8QM_USDHC1_DATA6_CONN_USDHC1_WP IMX8QM_USDHC1_DATA6 2 +-#define IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 IMX8QM_USDHC1_DATA6 3 +-#define IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 IMX8QM_USDHC1_DATA7 0 +-#define IMX8QM_USDHC1_DATA7_CONN_NAND_ALE IMX8QM_USDHC1_DATA7 1 +-#define IMX8QM_USDHC1_DATA7_CONN_USDHC1_CD_B IMX8QM_USDHC1_DATA7 2 +-#define IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 IMX8QM_USDHC1_DATA7 3 +-#define IMX8QM_USDHC1_STROBE_CONN_USDHC1_STROBE IMX8QM_USDHC1_STROBE 0 +-#define IMX8QM_USDHC1_STROBE_CONN_NAND_CE1_B IMX8QM_USDHC1_STROBE 1 +-#define IMX8QM_USDHC1_STROBE_CONN_USDHC1_RESET_B IMX8QM_USDHC1_STROBE 2 +-#define IMX8QM_USDHC1_STROBE_LSIO_GPIO5_IO23 IMX8QM_USDHC1_STROBE 3 +-#define IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK IMX8QM_USDHC2_CLK 0 +-#define IMX8QM_USDHC2_CLK_AUD_MQS_R IMX8QM_USDHC2_CLK 1 +-#define IMX8QM_USDHC2_CLK_LSIO_GPIO5_IO24 IMX8QM_USDHC2_CLK 3 +-#define IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD IMX8QM_USDHC2_CMD 0 +-#define IMX8QM_USDHC2_CMD_AUD_MQS_L IMX8QM_USDHC2_CMD 1 +-#define IMX8QM_USDHC2_CMD_LSIO_GPIO5_IO25 IMX8QM_USDHC2_CMD 3 +-#define IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 IMX8QM_USDHC2_DATA0 0 +-#define IMX8QM_USDHC2_DATA0_DMA_UART4_RX IMX8QM_USDHC2_DATA0 1 +-#define IMX8QM_USDHC2_DATA0_LSIO_GPIO5_IO26 IMX8QM_USDHC2_DATA0 3 +-#define IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 IMX8QM_USDHC2_DATA1 0 +-#define IMX8QM_USDHC2_DATA1_DMA_UART4_TX IMX8QM_USDHC2_DATA1 1 +-#define IMX8QM_USDHC2_DATA1_LSIO_GPIO5_IO27 IMX8QM_USDHC2_DATA1 3 +-#define IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 IMX8QM_USDHC2_DATA2 0 +-#define IMX8QM_USDHC2_DATA2_DMA_UART4_CTS_B IMX8QM_USDHC2_DATA2 1 +-#define IMX8QM_USDHC2_DATA2_LSIO_GPIO5_IO28 IMX8QM_USDHC2_DATA2 3 +-#define IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 IMX8QM_USDHC2_DATA3 0 +-#define IMX8QM_USDHC2_DATA3_DMA_UART4_RTS_B IMX8QM_USDHC2_DATA3 1 +-#define IMX8QM_USDHC2_DATA3_LSIO_GPIO5_IO29 IMX8QM_USDHC2_DATA3 3 +-#define IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC IMX8QM_ENET0_RGMII_TXC 0 +-#define IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT IMX8QM_ENET0_RGMII_TXC 1 +-#define IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN IMX8QM_ENET0_RGMII_TXC 2 +-#define IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 IMX8QM_ENET0_RGMII_TXC 3 +-#define IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL IMX8QM_ENET0_RGMII_TX_CTL 0 +-#define IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 IMX8QM_ENET0_RGMII_TX_CTL 3 +-#define IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 IMX8QM_ENET0_RGMII_TXD0 0 +-#define IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 IMX8QM_ENET0_RGMII_TXD0 3 +-#define IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 IMX8QM_ENET0_RGMII_TXD1 0 +-#define IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 IMX8QM_ENET0_RGMII_TXD1 3 +-#define IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 IMX8QM_ENET0_RGMII_TXD2 0 +-#define IMX8QM_ENET0_RGMII_TXD2_DMA_UART3_TX IMX8QM_ENET0_RGMII_TXD2 1 +-#define IMX8QM_ENET0_RGMII_TXD2_VPU_TSI_S1_VID IMX8QM_ENET0_RGMII_TXD2 2 +-#define IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 IMX8QM_ENET0_RGMII_TXD2 3 +-#define IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 IMX8QM_ENET0_RGMII_TXD3 0 +-#define IMX8QM_ENET0_RGMII_TXD3_DMA_UART3_RTS_B IMX8QM_ENET0_RGMII_TXD3 1 +-#define IMX8QM_ENET0_RGMII_TXD3_VPU_TSI_S1_SYNC IMX8QM_ENET0_RGMII_TXD3 2 +-#define IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 IMX8QM_ENET0_RGMII_TXD3 3 +-#define IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC IMX8QM_ENET0_RGMII_RXC 0 +-#define IMX8QM_ENET0_RGMII_RXC_DMA_UART3_CTS_B IMX8QM_ENET0_RGMII_RXC 1 +-#define IMX8QM_ENET0_RGMII_RXC_VPU_TSI_S1_DATA IMX8QM_ENET0_RGMII_RXC 2 +-#define IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 IMX8QM_ENET0_RGMII_RXC 3 +-#define IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL IMX8QM_ENET0_RGMII_RX_CTL 0 +-#define IMX8QM_ENET0_RGMII_RX_CTL_VPU_TSI_S0_VID IMX8QM_ENET0_RGMII_RX_CTL 2 +-#define IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 IMX8QM_ENET0_RGMII_RX_CTL 3 +-#define IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 IMX8QM_ENET0_RGMII_RXD0 0 +-#define IMX8QM_ENET0_RGMII_RXD0_VPU_TSI_S0_SYNC IMX8QM_ENET0_RGMII_RXD0 2 +-#define IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 IMX8QM_ENET0_RGMII_RXD0 3 +-#define IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 IMX8QM_ENET0_RGMII_RXD1 0 +-#define IMX8QM_ENET0_RGMII_RXD1_VPU_TSI_S0_DATA IMX8QM_ENET0_RGMII_RXD1 2 +-#define IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 IMX8QM_ENET0_RGMII_RXD1 3 +-#define IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 IMX8QM_ENET0_RGMII_RXD2 0 +-#define IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER IMX8QM_ENET0_RGMII_RXD2 1 +-#define IMX8QM_ENET0_RGMII_RXD2_VPU_TSI_S0_CLK IMX8QM_ENET0_RGMII_RXD2 2 +-#define IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 IMX8QM_ENET0_RGMII_RXD2 3 +-#define IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 IMX8QM_ENET0_RGMII_RXD3 0 +-#define IMX8QM_ENET0_RGMII_RXD3_DMA_UART3_RX IMX8QM_ENET0_RGMII_RXD3 1 +-#define IMX8QM_ENET0_RGMII_RXD3_VPU_TSI_S1_CLK IMX8QM_ENET0_RGMII_RXD3 2 +-#define IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 IMX8QM_ENET0_RGMII_RXD3 3 +-#define IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC IMX8QM_ENET1_RGMII_TXC 0 +-#define IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT IMX8QM_ENET1_RGMII_TXC 1 +-#define IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_IN IMX8QM_ENET1_RGMII_TXC 2 +-#define IMX8QM_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 IMX8QM_ENET1_RGMII_TXC 3 +-#define IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL IMX8QM_ENET1_RGMII_TX_CTL 0 +-#define IMX8QM_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 IMX8QM_ENET1_RGMII_TX_CTL 3 +-#define IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 IMX8QM_ENET1_RGMII_TXD0 0 +-#define IMX8QM_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 IMX8QM_ENET1_RGMII_TXD0 3 +-#define IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 IMX8QM_ENET1_RGMII_TXD1 0 +-#define IMX8QM_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 IMX8QM_ENET1_RGMII_TXD1 3 +-#define IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 IMX8QM_ENET1_RGMII_TXD2 0 +-#define IMX8QM_ENET1_RGMII_TXD2_DMA_UART3_TX IMX8QM_ENET1_RGMII_TXD2 1 +-#define IMX8QM_ENET1_RGMII_TXD2_VPU_TSI_S1_VID IMX8QM_ENET1_RGMII_TXD2 2 +-#define IMX8QM_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 IMX8QM_ENET1_RGMII_TXD2 3 +-#define IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 IMX8QM_ENET1_RGMII_TXD3 0 +-#define IMX8QM_ENET1_RGMII_TXD3_DMA_UART3_RTS_B IMX8QM_ENET1_RGMII_TXD3 1 +-#define IMX8QM_ENET1_RGMII_TXD3_VPU_TSI_S1_SYNC IMX8QM_ENET1_RGMII_TXD3 2 +-#define IMX8QM_ENET1_RGMII_TXD3_LSIO_GPIO6_IO15 IMX8QM_ENET1_RGMII_TXD3 3 +-#define IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC IMX8QM_ENET1_RGMII_RXC 0 +-#define IMX8QM_ENET1_RGMII_RXC_DMA_UART3_CTS_B IMX8QM_ENET1_RGMII_RXC 1 +-#define IMX8QM_ENET1_RGMII_RXC_VPU_TSI_S1_DATA IMX8QM_ENET1_RGMII_RXC 2 +-#define IMX8QM_ENET1_RGMII_RXC_LSIO_GPIO6_IO16 IMX8QM_ENET1_RGMII_RXC 3 +-#define IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL IMX8QM_ENET1_RGMII_RX_CTL 0 +-#define IMX8QM_ENET1_RGMII_RX_CTL_VPU_TSI_S0_VID IMX8QM_ENET1_RGMII_RX_CTL 2 +-#define IMX8QM_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 IMX8QM_ENET1_RGMII_RX_CTL 3 +-#define IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 IMX8QM_ENET1_RGMII_RXD0 0 +-#define IMX8QM_ENET1_RGMII_RXD0_VPU_TSI_S0_SYNC IMX8QM_ENET1_RGMII_RXD0 2 +-#define IMX8QM_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 IMX8QM_ENET1_RGMII_RXD0 3 +-#define IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 IMX8QM_ENET1_RGMII_RXD1 0 +-#define IMX8QM_ENET1_RGMII_RXD1_VPU_TSI_S0_DATA IMX8QM_ENET1_RGMII_RXD1 2 +-#define IMX8QM_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 IMX8QM_ENET1_RGMII_RXD1 3 +-#define IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 IMX8QM_ENET1_RGMII_RXD2 0 +-#define IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER IMX8QM_ENET1_RGMII_RXD2 1 +-#define IMX8QM_ENET1_RGMII_RXD2_VPU_TSI_S0_CLK IMX8QM_ENET1_RGMII_RXD2 2 +-#define IMX8QM_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 IMX8QM_ENET1_RGMII_RXD2 3 +-#define IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 IMX8QM_ENET1_RGMII_RXD3 0 +-#define IMX8QM_ENET1_RGMII_RXD3_DMA_UART3_RX IMX8QM_ENET1_RGMII_RXD3 1 +-#define IMX8QM_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK IMX8QM_ENET1_RGMII_RXD3 2 +-#define IMX8QM_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 IMX8QM_ENET1_RGMII_RXD3 3 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0 +-#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0 +- +-#endif /* _IMX8QM_PADS_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pads-imx8qxp.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pads-imx8qxp.h +deleted file mode 100644 +index fbfee7ecf844..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pads-imx8qxp.h ++++ /dev/null +@@ -1,751 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright (C) 2016 Freescale Semiconductor, Inc. +- * Copyright 2017~2018 NXP +- */ +- +-#ifndef _IMX8QXP_PADS_H +-#define _IMX8QXP_PADS_H +- +-/* pin id */ +-#define IMX8QXP_PCIE_CTRL0_PERST_B 0 +-#define IMX8QXP_PCIE_CTRL0_CLKREQ_B 1 +-#define IMX8QXP_PCIE_CTRL0_WAKE_B 2 +-#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 +-#define IMX8QXP_USB_SS3_TC0 4 +-#define IMX8QXP_USB_SS3_TC1 5 +-#define IMX8QXP_USB_SS3_TC2 6 +-#define IMX8QXP_USB_SS3_TC3 7 +-#define IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO 8 +-#define IMX8QXP_EMMC0_CLK 9 +-#define IMX8QXP_EMMC0_CMD 10 +-#define IMX8QXP_EMMC0_DATA0 11 +-#define IMX8QXP_EMMC0_DATA1 12 +-#define IMX8QXP_EMMC0_DATA2 13 +-#define IMX8QXP_EMMC0_DATA3 14 +-#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 +-#define IMX8QXP_EMMC0_DATA4 16 +-#define IMX8QXP_EMMC0_DATA5 17 +-#define IMX8QXP_EMMC0_DATA6 18 +-#define IMX8QXP_EMMC0_DATA7 19 +-#define IMX8QXP_EMMC0_STROBE 20 +-#define IMX8QXP_EMMC0_RESET_B 21 +-#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 +-#define IMX8QXP_USDHC1_RESET_B 23 +-#define IMX8QXP_USDHC1_VSELECT 24 +-#define IMX8QXP_CTL_NAND_RE_P_N 25 +-#define IMX8QXP_USDHC1_WP 26 +-#define IMX8QXP_USDHC1_CD_B 27 +-#define IMX8QXP_CTL_NAND_DQS_P_N 28 +-#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 +-#define IMX8QXP_USDHC1_CLK 30 +-#define IMX8QXP_USDHC1_CMD 31 +-#define IMX8QXP_USDHC1_DATA0 32 +-#define IMX8QXP_USDHC1_DATA1 33 +-#define IMX8QXP_USDHC1_DATA2 34 +-#define IMX8QXP_USDHC1_DATA3 35 +-#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 +-#define IMX8QXP_ENET0_RGMII_TXC 37 +-#define IMX8QXP_ENET0_RGMII_TX_CTL 38 +-#define IMX8QXP_ENET0_RGMII_TXD0 39 +-#define IMX8QXP_ENET0_RGMII_TXD1 40 +-#define IMX8QXP_ENET0_RGMII_TXD2 41 +-#define IMX8QXP_ENET0_RGMII_TXD3 42 +-#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 +-#define IMX8QXP_ENET0_RGMII_RXC 44 +-#define IMX8QXP_ENET0_RGMII_RX_CTL 45 +-#define IMX8QXP_ENET0_RGMII_RXD0 46 +-#define IMX8QXP_ENET0_RGMII_RXD1 47 +-#define IMX8QXP_ENET0_RGMII_RXD2 48 +-#define IMX8QXP_ENET0_RGMII_RXD3 49 +-#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 +-#define IMX8QXP_ENET0_REFCLK_125M_25M 51 +-#define IMX8QXP_ENET0_MDIO 52 +-#define IMX8QXP_ENET0_MDC 53 +-#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 +-#define IMX8QXP_ESAI0_FSR 55 +-#define IMX8QXP_ESAI0_FST 56 +-#define IMX8QXP_ESAI0_SCKR 57 +-#define IMX8QXP_ESAI0_SCKT 58 +-#define IMX8QXP_ESAI0_TX0 59 +-#define IMX8QXP_ESAI0_TX1 60 +-#define IMX8QXP_ESAI0_TX2_RX3 61 +-#define IMX8QXP_ESAI0_TX3_RX2 62 +-#define IMX8QXP_ESAI0_TX4_RX1 63 +-#define IMX8QXP_ESAI0_TX5_RX0 64 +-#define IMX8QXP_SPDIF0_RX 65 +-#define IMX8QXP_SPDIF0_TX 66 +-#define IMX8QXP_SPDIF0_EXT_CLK 67 +-#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 +-#define IMX8QXP_SPI3_SCK 69 +-#define IMX8QXP_SPI3_SDO 70 +-#define IMX8QXP_SPI3_SDI 71 +-#define IMX8QXP_SPI3_CS0 72 +-#define IMX8QXP_SPI3_CS1 73 +-#define IMX8QXP_MCLK_IN1 74 +-#define IMX8QXP_MCLK_IN0 75 +-#define IMX8QXP_MCLK_OUT0 76 +-#define IMX8QXP_UART1_TX 77 +-#define IMX8QXP_UART1_RX 78 +-#define IMX8QXP_UART1_RTS_B 79 +-#define IMX8QXP_UART1_CTS_B 80 +-#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 +-#define IMX8QXP_SAI0_TXD 82 +-#define IMX8QXP_SAI0_TXC 83 +-#define IMX8QXP_SAI0_RXD 84 +-#define IMX8QXP_SAI0_TXFS 85 +-#define IMX8QXP_SAI1_RXD 86 +-#define IMX8QXP_SAI1_RXC 87 +-#define IMX8QXP_SAI1_RXFS 88 +-#define IMX8QXP_SPI2_CS0 89 +-#define IMX8QXP_SPI2_SDO 90 +-#define IMX8QXP_SPI2_SDI 91 +-#define IMX8QXP_SPI2_SCK 92 +-#define IMX8QXP_SPI0_SCK 93 +-#define IMX8QXP_SPI0_SDI 94 +-#define IMX8QXP_SPI0_SDO 95 +-#define IMX8QXP_SPI0_CS1 96 +-#define IMX8QXP_SPI0_CS0 97 +-#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 +-#define IMX8QXP_ADC_IN1 99 +-#define IMX8QXP_ADC_IN0 100 +-#define IMX8QXP_ADC_IN3 101 +-#define IMX8QXP_ADC_IN2 102 +-#define IMX8QXP_ADC_IN5 103 +-#define IMX8QXP_ADC_IN4 104 +-#define IMX8QXP_FLEXCAN0_RX 105 +-#define IMX8QXP_FLEXCAN0_TX 106 +-#define IMX8QXP_FLEXCAN1_RX 107 +-#define IMX8QXP_FLEXCAN1_TX 108 +-#define IMX8QXP_FLEXCAN2_RX 109 +-#define IMX8QXP_FLEXCAN2_TX 110 +-#define IMX8QXP_UART0_RX 111 +-#define IMX8QXP_UART0_TX 112 +-#define IMX8QXP_UART2_TX 113 +-#define IMX8QXP_UART2_RX 114 +-#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 +-#define IMX8QXP_MIPI_DSI0_I2C0_SCL 116 +-#define IMX8QXP_MIPI_DSI0_I2C0_SDA 117 +-#define IMX8QXP_MIPI_DSI0_GPIO0_00 118 +-#define IMX8QXP_MIPI_DSI0_GPIO0_01 119 +-#define IMX8QXP_MIPI_DSI1_I2C0_SCL 120 +-#define IMX8QXP_MIPI_DSI1_I2C0_SDA 121 +-#define IMX8QXP_MIPI_DSI1_GPIO0_00 122 +-#define IMX8QXP_MIPI_DSI1_GPIO0_01 123 +-#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 +-#define IMX8QXP_JTAG_TRST_B 125 +-#define IMX8QXP_PMIC_I2C_SCL 126 +-#define IMX8QXP_PMIC_I2C_SDA 127 +-#define IMX8QXP_PMIC_INT_B 128 +-#define IMX8QXP_SCU_GPIO0_00 129 +-#define IMX8QXP_SCU_GPIO0_01 130 +-#define IMX8QXP_SCU_PMIC_STANDBY 131 +-#define IMX8QXP_SCU_BOOT_MODE0 132 +-#define IMX8QXP_SCU_BOOT_MODE1 133 +-#define IMX8QXP_SCU_BOOT_MODE2 134 +-#define IMX8QXP_SCU_BOOT_MODE3 135 +-#define IMX8QXP_CSI_D00 136 +-#define IMX8QXP_CSI_D01 137 +-#define IMX8QXP_CSI_D02 138 +-#define IMX8QXP_CSI_D03 139 +-#define IMX8QXP_CSI_D04 140 +-#define IMX8QXP_CSI_D05 141 +-#define IMX8QXP_CSI_D06 142 +-#define IMX8QXP_CSI_D07 143 +-#define IMX8QXP_CSI_HSYNC 144 +-#define IMX8QXP_CSI_VSYNC 145 +-#define IMX8QXP_CSI_PCLK 146 +-#define IMX8QXP_CSI_MCLK 147 +-#define IMX8QXP_CSI_EN 148 +-#define IMX8QXP_CSI_RESET 149 +-#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 +-#define IMX8QXP_MIPI_CSI0_MCLK_OUT 151 +-#define IMX8QXP_MIPI_CSI0_I2C0_SCL 152 +-#define IMX8QXP_MIPI_CSI0_I2C0_SDA 153 +-#define IMX8QXP_MIPI_CSI0_GPIO0_01 154 +-#define IMX8QXP_MIPI_CSI0_GPIO0_00 155 +-#define IMX8QXP_QSPI0A_DATA0 156 +-#define IMX8QXP_QSPI0A_DATA1 157 +-#define IMX8QXP_QSPI0A_DATA2 158 +-#define IMX8QXP_QSPI0A_DATA3 159 +-#define IMX8QXP_QSPI0A_DQS 160 +-#define IMX8QXP_QSPI0A_SS0_B 161 +-#define IMX8QXP_QSPI0A_SS1_B 162 +-#define IMX8QXP_QSPI0A_SCLK 163 +-#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 +-#define IMX8QXP_QSPI0B_SCLK 165 +-#define IMX8QXP_QSPI0B_DATA0 166 +-#define IMX8QXP_QSPI0B_DATA1 167 +-#define IMX8QXP_QSPI0B_DATA2 168 +-#define IMX8QXP_QSPI0B_DATA3 169 +-#define IMX8QXP_QSPI0B_DQS 170 +-#define IMX8QXP_QSPI0B_SS0_B 171 +-#define IMX8QXP_QSPI0B_SS1_B 172 +-#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 +- +-/* +- * format: +- */ +-#define IMX8QXP_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8QXP_PCIE_CTRL0_PERST_B 0 +-#define IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8QXP_PCIE_CTRL0_PERST_B 4 +-#define IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8QXP_PCIE_CTRL0_CLKREQ_B 0 +-#define IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8QXP_PCIE_CTRL0_CLKREQ_B 4 +-#define IMX8QXP_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8QXP_PCIE_CTRL0_WAKE_B 0 +-#define IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8QXP_PCIE_CTRL0_WAKE_B 4 +-#define IMX8QXP_USB_SS3_TC0_ADMA_I2C1_SCL IMX8QXP_USB_SS3_TC0 0 +-#define IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8QXP_USB_SS3_TC0 1 +-#define IMX8QXP_USB_SS3_TC0_CONN_USB_OTG2_PWR IMX8QXP_USB_SS3_TC0 2 +-#define IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8QXP_USB_SS3_TC0 4 +-#define IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL IMX8QXP_USB_SS3_TC1 0 +-#define IMX8QXP_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8QXP_USB_SS3_TC1 1 +-#define IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8QXP_USB_SS3_TC1 4 +-#define IMX8QXP_USB_SS3_TC2_ADMA_I2C1_SDA IMX8QXP_USB_SS3_TC2 0 +-#define IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC IMX8QXP_USB_SS3_TC2 1 +-#define IMX8QXP_USB_SS3_TC2_CONN_USB_OTG2_OC IMX8QXP_USB_SS3_TC2 2 +-#define IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 IMX8QXP_USB_SS3_TC2 4 +-#define IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA IMX8QXP_USB_SS3_TC3 0 +-#define IMX8QXP_USB_SS3_TC3_CONN_USB_OTG2_OC IMX8QXP_USB_SS3_TC3 1 +-#define IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 IMX8QXP_USB_SS3_TC3 4 +-#define IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK IMX8QXP_EMMC0_CLK 0 +-#define IMX8QXP_EMMC0_CLK_CONN_NAND_READY_B IMX8QXP_EMMC0_CLK 1 +-#define IMX8QXP_EMMC0_CLK_LSIO_GPIO4_IO07 IMX8QXP_EMMC0_CLK 4 +-#define IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD IMX8QXP_EMMC0_CMD 0 +-#define IMX8QXP_EMMC0_CMD_CONN_NAND_DQS IMX8QXP_EMMC0_CMD 1 +-#define IMX8QXP_EMMC0_CMD_LSIO_GPIO4_IO08 IMX8QXP_EMMC0_CMD 4 +-#define IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 IMX8QXP_EMMC0_DATA0 0 +-#define IMX8QXP_EMMC0_DATA0_CONN_NAND_DATA00 IMX8QXP_EMMC0_DATA0 1 +-#define IMX8QXP_EMMC0_DATA0_LSIO_GPIO4_IO09 IMX8QXP_EMMC0_DATA0 4 +-#define IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 IMX8QXP_EMMC0_DATA1 0 +-#define IMX8QXP_EMMC0_DATA1_CONN_NAND_DATA01 IMX8QXP_EMMC0_DATA1 1 +-#define IMX8QXP_EMMC0_DATA1_LSIO_GPIO4_IO10 IMX8QXP_EMMC0_DATA1 4 +-#define IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 IMX8QXP_EMMC0_DATA2 0 +-#define IMX8QXP_EMMC0_DATA2_CONN_NAND_DATA02 IMX8QXP_EMMC0_DATA2 1 +-#define IMX8QXP_EMMC0_DATA2_LSIO_GPIO4_IO11 IMX8QXP_EMMC0_DATA2 4 +-#define IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 IMX8QXP_EMMC0_DATA3 0 +-#define IMX8QXP_EMMC0_DATA3_CONN_NAND_DATA03 IMX8QXP_EMMC0_DATA3 1 +-#define IMX8QXP_EMMC0_DATA3_LSIO_GPIO4_IO12 IMX8QXP_EMMC0_DATA3 4 +-#define IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 IMX8QXP_EMMC0_DATA4 0 +-#define IMX8QXP_EMMC0_DATA4_CONN_NAND_DATA04 IMX8QXP_EMMC0_DATA4 1 +-#define IMX8QXP_EMMC0_DATA4_CONN_EMMC0_WP IMX8QXP_EMMC0_DATA4 3 +-#define IMX8QXP_EMMC0_DATA4_LSIO_GPIO4_IO13 IMX8QXP_EMMC0_DATA4 4 +-#define IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 IMX8QXP_EMMC0_DATA5 0 +-#define IMX8QXP_EMMC0_DATA5_CONN_NAND_DATA05 IMX8QXP_EMMC0_DATA5 1 +-#define IMX8QXP_EMMC0_DATA5_CONN_EMMC0_VSELECT IMX8QXP_EMMC0_DATA5 3 +-#define IMX8QXP_EMMC0_DATA5_LSIO_GPIO4_IO14 IMX8QXP_EMMC0_DATA5 4 +-#define IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 IMX8QXP_EMMC0_DATA6 0 +-#define IMX8QXP_EMMC0_DATA6_CONN_NAND_DATA06 IMX8QXP_EMMC0_DATA6 1 +-#define IMX8QXP_EMMC0_DATA6_CONN_MLB_CLK IMX8QXP_EMMC0_DATA6 3 +-#define IMX8QXP_EMMC0_DATA6_LSIO_GPIO4_IO15 IMX8QXP_EMMC0_DATA6 4 +-#define IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 IMX8QXP_EMMC0_DATA7 0 +-#define IMX8QXP_EMMC0_DATA7_CONN_NAND_DATA07 IMX8QXP_EMMC0_DATA7 1 +-#define IMX8QXP_EMMC0_DATA7_CONN_MLB_SIG IMX8QXP_EMMC0_DATA7 3 +-#define IMX8QXP_EMMC0_DATA7_LSIO_GPIO4_IO16 IMX8QXP_EMMC0_DATA7 4 +-#define IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE IMX8QXP_EMMC0_STROBE 0 +-#define IMX8QXP_EMMC0_STROBE_CONN_NAND_CLE IMX8QXP_EMMC0_STROBE 1 +-#define IMX8QXP_EMMC0_STROBE_CONN_MLB_DATA IMX8QXP_EMMC0_STROBE 3 +-#define IMX8QXP_EMMC0_STROBE_LSIO_GPIO4_IO17 IMX8QXP_EMMC0_STROBE 4 +-#define IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B IMX8QXP_EMMC0_RESET_B 0 +-#define IMX8QXP_EMMC0_RESET_B_CONN_NAND_WP_B IMX8QXP_EMMC0_RESET_B 1 +-#define IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18 IMX8QXP_EMMC0_RESET_B 4 +-#define IMX8QXP_USDHC1_RESET_B_CONN_USDHC1_RESET_B IMX8QXP_USDHC1_RESET_B 0 +-#define IMX8QXP_USDHC1_RESET_B_CONN_NAND_RE_N IMX8QXP_USDHC1_RESET_B 1 +-#define IMX8QXP_USDHC1_RESET_B_ADMA_SPI2_SCK IMX8QXP_USDHC1_RESET_B 2 +-#define IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 IMX8QXP_USDHC1_RESET_B 4 +-#define IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT IMX8QXP_USDHC1_VSELECT 0 +-#define IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_P IMX8QXP_USDHC1_VSELECT 1 +-#define IMX8QXP_USDHC1_VSELECT_ADMA_SPI2_SDO IMX8QXP_USDHC1_VSELECT 2 +-#define IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_B IMX8QXP_USDHC1_VSELECT 3 +-#define IMX8QXP_USDHC1_VSELECT_LSIO_GPIO4_IO20 IMX8QXP_USDHC1_VSELECT 4 +-#define IMX8QXP_USDHC1_WP_CONN_USDHC1_WP IMX8QXP_USDHC1_WP 0 +-#define IMX8QXP_USDHC1_WP_CONN_NAND_DQS_N IMX8QXP_USDHC1_WP 1 +-#define IMX8QXP_USDHC1_WP_ADMA_SPI2_SDI IMX8QXP_USDHC1_WP 2 +-#define IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 IMX8QXP_USDHC1_WP 4 +-#define IMX8QXP_USDHC1_CD_B_CONN_USDHC1_CD_B IMX8QXP_USDHC1_CD_B 0 +-#define IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS_P IMX8QXP_USDHC1_CD_B 1 +-#define IMX8QXP_USDHC1_CD_B_ADMA_SPI2_CS0 IMX8QXP_USDHC1_CD_B 2 +-#define IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS IMX8QXP_USDHC1_CD_B 3 +-#define IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 IMX8QXP_USDHC1_CD_B 4 +-#define IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK IMX8QXP_USDHC1_CLK 0 +-#define IMX8QXP_USDHC1_CLK_ADMA_UART3_RX IMX8QXP_USDHC1_CLK 2 +-#define IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 IMX8QXP_USDHC1_CLK 4 +-#define IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD IMX8QXP_USDHC1_CMD 0 +-#define IMX8QXP_USDHC1_CMD_CONN_NAND_CE0_B IMX8QXP_USDHC1_CMD 1 +-#define IMX8QXP_USDHC1_CMD_ADMA_MQS_R IMX8QXP_USDHC1_CMD 2 +-#define IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 IMX8QXP_USDHC1_CMD 4 +-#define IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 IMX8QXP_USDHC1_DATA0 0 +-#define IMX8QXP_USDHC1_DATA0_CONN_NAND_CE1_B IMX8QXP_USDHC1_DATA0 1 +-#define IMX8QXP_USDHC1_DATA0_ADMA_MQS_L IMX8QXP_USDHC1_DATA0 2 +-#define IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 IMX8QXP_USDHC1_DATA0 4 +-#define IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 IMX8QXP_USDHC1_DATA1 0 +-#define IMX8QXP_USDHC1_DATA1_CONN_NAND_RE_B IMX8QXP_USDHC1_DATA1 1 +-#define IMX8QXP_USDHC1_DATA1_ADMA_UART3_TX IMX8QXP_USDHC1_DATA1 2 +-#define IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 IMX8QXP_USDHC1_DATA1 4 +-#define IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 IMX8QXP_USDHC1_DATA2 0 +-#define IMX8QXP_USDHC1_DATA2_CONN_NAND_WE_B IMX8QXP_USDHC1_DATA2 1 +-#define IMX8QXP_USDHC1_DATA2_ADMA_UART3_CTS_B IMX8QXP_USDHC1_DATA2 2 +-#define IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 IMX8QXP_USDHC1_DATA2 4 +-#define IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 IMX8QXP_USDHC1_DATA3 0 +-#define IMX8QXP_USDHC1_DATA3_CONN_NAND_ALE IMX8QXP_USDHC1_DATA3 1 +-#define IMX8QXP_USDHC1_DATA3_ADMA_UART3_RTS_B IMX8QXP_USDHC1_DATA3 2 +-#define IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 IMX8QXP_USDHC1_DATA3 4 +-#define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC IMX8QXP_ENET0_RGMII_TXC 0 +-#define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT IMX8QXP_ENET0_RGMII_TXC 1 +-#define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN IMX8QXP_ENET0_RGMII_TXC 2 +-#define IMX8QXP_ENET0_RGMII_TXC_CONN_NAND_CE1_B IMX8QXP_ENET0_RGMII_TXC 3 +-#define IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 IMX8QXP_ENET0_RGMII_TXC 4 +-#define IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL IMX8QXP_ENET0_RGMII_TX_CTL 0 +-#define IMX8QXP_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B IMX8QXP_ENET0_RGMII_TX_CTL 3 +-#define IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 IMX8QXP_ENET0_RGMII_TX_CTL 4 +-#define IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 IMX8QXP_ENET0_RGMII_TXD0 0 +-#define IMX8QXP_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT IMX8QXP_ENET0_RGMII_TXD0 3 +-#define IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 IMX8QXP_ENET0_RGMII_TXD0 4 +-#define IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 IMX8QXP_ENET0_RGMII_TXD1 0 +-#define IMX8QXP_ENET0_RGMII_TXD1_CONN_USDHC1_WP IMX8QXP_ENET0_RGMII_TXD1 3 +-#define IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 IMX8QXP_ENET0_RGMII_TXD1 4 +-#define IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 IMX8QXP_ENET0_RGMII_TXD2 0 +-#define IMX8QXP_ENET0_RGMII_TXD2_CONN_MLB_CLK IMX8QXP_ENET0_RGMII_TXD2 1 +-#define IMX8QXP_ENET0_RGMII_TXD2_CONN_NAND_CE0_B IMX8QXP_ENET0_RGMII_TXD2 2 +-#define IMX8QXP_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B IMX8QXP_ENET0_RGMII_TXD2 3 +-#define IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 IMX8QXP_ENET0_RGMII_TXD2 4 +-#define IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 IMX8QXP_ENET0_RGMII_TXD3 0 +-#define IMX8QXP_ENET0_RGMII_TXD3_CONN_MLB_SIG IMX8QXP_ENET0_RGMII_TXD3 1 +-#define IMX8QXP_ENET0_RGMII_TXD3_CONN_NAND_RE_B IMX8QXP_ENET0_RGMII_TXD3 2 +-#define IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 IMX8QXP_ENET0_RGMII_TXD3 4 +-#define IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC IMX8QXP_ENET0_RGMII_RXC 0 +-#define IMX8QXP_ENET0_RGMII_RXC_CONN_MLB_DATA IMX8QXP_ENET0_RGMII_RXC 1 +-#define IMX8QXP_ENET0_RGMII_RXC_CONN_NAND_WE_B IMX8QXP_ENET0_RGMII_RXC 2 +-#define IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK IMX8QXP_ENET0_RGMII_RXC 3 +-#define IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 IMX8QXP_ENET0_RGMII_RXC 4 +-#define IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL IMX8QXP_ENET0_RGMII_RX_CTL 0 +-#define IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD IMX8QXP_ENET0_RGMII_RX_CTL 3 +-#define IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 IMX8QXP_ENET0_RGMII_RX_CTL 4 +-#define IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 IMX8QXP_ENET0_RGMII_RXD0 0 +-#define IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 IMX8QXP_ENET0_RGMII_RXD0 3 +-#define IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 IMX8QXP_ENET0_RGMII_RXD0 4 +-#define IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 IMX8QXP_ENET0_RGMII_RXD1 0 +-#define IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 IMX8QXP_ENET0_RGMII_RXD1 3 +-#define IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 IMX8QXP_ENET0_RGMII_RXD1 4 +-#define IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 IMX8QXP_ENET0_RGMII_RXD2 0 +-#define IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER IMX8QXP_ENET0_RGMII_RXD2 1 +-#define IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 IMX8QXP_ENET0_RGMII_RXD2 3 +-#define IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 IMX8QXP_ENET0_RGMII_RXD2 4 +-#define IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 IMX8QXP_ENET0_RGMII_RXD3 0 +-#define IMX8QXP_ENET0_RGMII_RXD3_CONN_NAND_ALE IMX8QXP_ENET0_RGMII_RXD3 2 +-#define IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 IMX8QXP_ENET0_RGMII_RXD3 3 +-#define IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 IMX8QXP_ENET0_RGMII_RXD3 4 +-#define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M IMX8QXP_ENET0_REFCLK_125M_25M 0 +-#define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS IMX8QXP_ENET0_REFCLK_125M_25M 1 +-#define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS IMX8QXP_ENET0_REFCLK_125M_25M 2 +-#define IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 IMX8QXP_ENET0_REFCLK_125M_25M 4 +-#define IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO IMX8QXP_ENET0_MDIO 0 +-#define IMX8QXP_ENET0_MDIO_ADMA_I2C3_SDA IMX8QXP_ENET0_MDIO 1 +-#define IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO IMX8QXP_ENET0_MDIO 2 +-#define IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 IMX8QXP_ENET0_MDIO 4 +-#define IMX8QXP_ENET0_MDC_CONN_ENET0_MDC IMX8QXP_ENET0_MDC 0 +-#define IMX8QXP_ENET0_MDC_ADMA_I2C3_SCL IMX8QXP_ENET0_MDC 1 +-#define IMX8QXP_ENET0_MDC_CONN_ENET1_MDC IMX8QXP_ENET0_MDC 2 +-#define IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 IMX8QXP_ENET0_MDC 4 +-#define IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR IMX8QXP_ESAI0_FSR 0 +-#define IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT IMX8QXP_ESAI0_FSR 1 +-#define IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 IMX8QXP_ESAI0_FSR 2 +-#define IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC IMX8QXP_ESAI0_FSR 3 +-#define IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_IN IMX8QXP_ESAI0_FSR 4 +-#define IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST IMX8QXP_ESAI0_FST 0 +-#define IMX8QXP_ESAI0_FST_CONN_MLB_CLK IMX8QXP_ESAI0_FST 1 +-#define IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 IMX8QXP_ESAI0_FST 2 +-#define IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 IMX8QXP_ESAI0_FST 3 +-#define IMX8QXP_ESAI0_FST_LSIO_GPIO0_IO01 IMX8QXP_ESAI0_FST 4 +-#define IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR IMX8QXP_ESAI0_SCKR 0 +-#define IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 IMX8QXP_ESAI0_SCKR 2 +-#define IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL IMX8QXP_ESAI0_SCKR 3 +-#define IMX8QXP_ESAI0_SCKR_LSIO_GPIO0_IO02 IMX8QXP_ESAI0_SCKR 4 +-#define IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT IMX8QXP_ESAI0_SCKT 0 +-#define IMX8QXP_ESAI0_SCKT_CONN_MLB_SIG IMX8QXP_ESAI0_SCKT 1 +-#define IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 IMX8QXP_ESAI0_SCKT 2 +-#define IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 IMX8QXP_ESAI0_SCKT 3 +-#define IMX8QXP_ESAI0_SCKT_LSIO_GPIO0_IO03 IMX8QXP_ESAI0_SCKT 4 +-#define IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 IMX8QXP_ESAI0_TX0 0 +-#define IMX8QXP_ESAI0_TX0_CONN_MLB_DATA IMX8QXP_ESAI0_TX0 1 +-#define IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 IMX8QXP_ESAI0_TX0 2 +-#define IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC IMX8QXP_ESAI0_TX0 3 +-#define IMX8QXP_ESAI0_TX0_LSIO_GPIO0_IO04 IMX8QXP_ESAI0_TX0 4 +-#define IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 IMX8QXP_ESAI0_TX1 0 +-#define IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 IMX8QXP_ESAI0_TX1 2 +-#define IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 IMX8QXP_ESAI0_TX1 3 +-#define IMX8QXP_ESAI0_TX1_LSIO_GPIO0_IO05 IMX8QXP_ESAI0_TX1 4 +-#define IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 IMX8QXP_ESAI0_TX2_RX3 0 +-#define IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER IMX8QXP_ESAI0_TX2_RX3 1 +-#define IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 IMX8QXP_ESAI0_TX2_RX3 2 +-#define IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 IMX8QXP_ESAI0_TX2_RX3 3 +-#define IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 IMX8QXP_ESAI0_TX2_RX3 4 +-#define IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 IMX8QXP_ESAI0_TX3_RX2 0 +-#define IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 IMX8QXP_ESAI0_TX3_RX2 2 +-#define IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 IMX8QXP_ESAI0_TX3_RX2 3 +-#define IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 IMX8QXP_ESAI0_TX3_RX2 4 +-#define IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 IMX8QXP_ESAI0_TX4_RX1 0 +-#define IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 IMX8QXP_ESAI0_TX4_RX1 2 +-#define IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 IMX8QXP_ESAI0_TX4_RX1 3 +-#define IMX8QXP_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 IMX8QXP_ESAI0_TX4_RX1 4 +-#define IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 IMX8QXP_ESAI0_TX5_RX0 0 +-#define IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 IMX8QXP_ESAI0_TX5_RX0 2 +-#define IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 IMX8QXP_ESAI0_TX5_RX0 3 +-#define IMX8QXP_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 IMX8QXP_ESAI0_TX5_RX0 4 +-#define IMX8QXP_SPDIF0_RX_ADMA_SPDIF0_RX IMX8QXP_SPDIF0_RX 0 +-#define IMX8QXP_SPDIF0_RX_ADMA_MQS_R IMX8QXP_SPDIF0_RX 1 +-#define IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 IMX8QXP_SPDIF0_RX 2 +-#define IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 IMX8QXP_SPDIF0_RX 3 +-#define IMX8QXP_SPDIF0_RX_LSIO_GPIO0_IO10 IMX8QXP_SPDIF0_RX 4 +-#define IMX8QXP_SPDIF0_TX_ADMA_SPDIF0_TX IMX8QXP_SPDIF0_TX 0 +-#define IMX8QXP_SPDIF0_TX_ADMA_MQS_L IMX8QXP_SPDIF0_TX 1 +-#define IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 IMX8QXP_SPDIF0_TX 2 +-#define IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL IMX8QXP_SPDIF0_TX 3 +-#define IMX8QXP_SPDIF0_TX_LSIO_GPIO0_IO11 IMX8QXP_SPDIF0_TX 4 +-#define IMX8QXP_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK IMX8QXP_SPDIF0_EXT_CLK 0 +-#define IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 IMX8QXP_SPDIF0_EXT_CLK 2 +-#define IMX8QXP_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M IMX8QXP_SPDIF0_EXT_CLK 3 +-#define IMX8QXP_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 IMX8QXP_SPDIF0_EXT_CLK 4 +-#define IMX8QXP_SPI3_SCK_ADMA_SPI3_SCK IMX8QXP_SPI3_SCK 0 +-#define IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 IMX8QXP_SPI3_SCK 2 +-#define IMX8QXP_SPI3_SCK_LSIO_GPIO0_IO13 IMX8QXP_SPI3_SCK 4 +-#define IMX8QXP_SPI3_SDO_ADMA_SPI3_SDO IMX8QXP_SPI3_SDO 0 +-#define IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 IMX8QXP_SPI3_SDO 2 +-#define IMX8QXP_SPI3_SDO_LSIO_GPIO0_IO14 IMX8QXP_SPI3_SDO 4 +-#define IMX8QXP_SPI3_SDI_ADMA_SPI3_SDI IMX8QXP_SPI3_SDI 0 +-#define IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 IMX8QXP_SPI3_SDI 2 +-#define IMX8QXP_SPI3_SDI_LSIO_GPIO0_IO15 IMX8QXP_SPI3_SDI 4 +-#define IMX8QXP_SPI3_CS0_ADMA_SPI3_CS0 IMX8QXP_SPI3_CS0 0 +-#define IMX8QXP_SPI3_CS0_ADMA_ACM_MCLK_OUT1 IMX8QXP_SPI3_CS0 1 +-#define IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC IMX8QXP_SPI3_CS0 2 +-#define IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16 IMX8QXP_SPI3_CS0 4 +-#define IMX8QXP_SPI3_CS1_ADMA_SPI3_CS1 IMX8QXP_SPI3_CS1 0 +-#define IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL IMX8QXP_SPI3_CS1 1 +-#define IMX8QXP_SPI3_CS1_ADMA_LCDIF_RESET IMX8QXP_SPI3_CS1 2 +-#define IMX8QXP_SPI3_CS1_ADMA_SPI2_CS0 IMX8QXP_SPI3_CS1 3 +-#define IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 IMX8QXP_SPI3_CS1 4 +-#define IMX8QXP_MCLK_IN1_ADMA_ACM_MCLK_IN1 IMX8QXP_MCLK_IN1 0 +-#define IMX8QXP_MCLK_IN1_ADMA_I2C3_SDA IMX8QXP_MCLK_IN1 1 +-#define IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN IMX8QXP_MCLK_IN1 2 +-#define IMX8QXP_MCLK_IN1_ADMA_SPI2_SCK IMX8QXP_MCLK_IN1 3 +-#define IMX8QXP_MCLK_IN1_ADMA_LCDIF_D17 IMX8QXP_MCLK_IN1 4 +-#define IMX8QXP_MCLK_IN0_ADMA_ACM_MCLK_IN0 IMX8QXP_MCLK_IN0 0 +-#define IMX8QXP_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK IMX8QXP_MCLK_IN0 1 +-#define IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC IMX8QXP_MCLK_IN0 2 +-#define IMX8QXP_MCLK_IN0_ADMA_SPI2_SDI IMX8QXP_MCLK_IN0 3 +-#define IMX8QXP_MCLK_IN0_LSIO_GPIO0_IO19 IMX8QXP_MCLK_IN0 4 +-#define IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 IMX8QXP_MCLK_OUT0 0 +-#define IMX8QXP_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK IMX8QXP_MCLK_OUT0 1 +-#define IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK IMX8QXP_MCLK_OUT0 2 +-#define IMX8QXP_MCLK_OUT0_ADMA_SPI2_SDO IMX8QXP_MCLK_OUT0 3 +-#define IMX8QXP_MCLK_OUT0_LSIO_GPIO0_IO20 IMX8QXP_MCLK_OUT0 4 +-#define IMX8QXP_UART1_TX_ADMA_UART1_TX IMX8QXP_UART1_TX 0 +-#define IMX8QXP_UART1_TX_LSIO_PWM0_OUT IMX8QXP_UART1_TX 1 +-#define IMX8QXP_UART1_TX_LSIO_GPT0_CAPTURE IMX8QXP_UART1_TX 2 +-#define IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 IMX8QXP_UART1_TX 4 +-#define IMX8QXP_UART1_RX_ADMA_UART1_RX IMX8QXP_UART1_RX 0 +-#define IMX8QXP_UART1_RX_LSIO_PWM1_OUT IMX8QXP_UART1_RX 1 +-#define IMX8QXP_UART1_RX_LSIO_GPT0_COMPARE IMX8QXP_UART1_RX 2 +-#define IMX8QXP_UART1_RX_LSIO_GPT1_CLK IMX8QXP_UART1_RX 3 +-#define IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 IMX8QXP_UART1_RX 4 +-#define IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B IMX8QXP_UART1_RTS_B 0 +-#define IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT IMX8QXP_UART1_RTS_B 1 +-#define IMX8QXP_UART1_RTS_B_ADMA_LCDIF_D16 IMX8QXP_UART1_RTS_B 2 +-#define IMX8QXP_UART1_RTS_B_LSIO_GPT1_CAPTURE IMX8QXP_UART1_RTS_B 3 +-#define IMX8QXP_UART1_RTS_B_LSIO_GPT0_CLK IMX8QXP_UART1_RTS_B 4 +-#define IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B IMX8QXP_UART1_CTS_B 0 +-#define IMX8QXP_UART1_CTS_B_LSIO_PWM3_OUT IMX8QXP_UART1_CTS_B 1 +-#define IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 IMX8QXP_UART1_CTS_B 2 +-#define IMX8QXP_UART1_CTS_B_LSIO_GPT1_COMPARE IMX8QXP_UART1_CTS_B 3 +-#define IMX8QXP_UART1_CTS_B_LSIO_GPIO0_IO24 IMX8QXP_UART1_CTS_B 4 +-#define IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD IMX8QXP_SAI0_TXD 0 +-#define IMX8QXP_SAI0_TXD_ADMA_SAI1_RXC IMX8QXP_SAI0_TXD 1 +-#define IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO IMX8QXP_SAI0_TXD 2 +-#define IMX8QXP_SAI0_TXD_ADMA_LCDIF_D18 IMX8QXP_SAI0_TXD 3 +-#define IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 IMX8QXP_SAI0_TXD 4 +-#define IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC IMX8QXP_SAI0_TXC 0 +-#define IMX8QXP_SAI0_TXC_ADMA_SAI1_TXD IMX8QXP_SAI0_TXC 1 +-#define IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI IMX8QXP_SAI0_TXC 2 +-#define IMX8QXP_SAI0_TXC_ADMA_LCDIF_D19 IMX8QXP_SAI0_TXC 3 +-#define IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 IMX8QXP_SAI0_TXC 4 +-#define IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD IMX8QXP_SAI0_RXD 0 +-#define IMX8QXP_SAI0_RXD_ADMA_SAI1_RXFS IMX8QXP_SAI0_RXD 1 +-#define IMX8QXP_SAI0_RXD_ADMA_SPI1_CS0 IMX8QXP_SAI0_RXD 2 +-#define IMX8QXP_SAI0_RXD_ADMA_LCDIF_D20 IMX8QXP_SAI0_RXD 3 +-#define IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 IMX8QXP_SAI0_RXD 4 +-#define IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS IMX8QXP_SAI0_TXFS 0 +-#define IMX8QXP_SAI0_TXFS_ADMA_SPI2_CS1 IMX8QXP_SAI0_TXFS 1 +-#define IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK IMX8QXP_SAI0_TXFS 2 +-#define IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 IMX8QXP_SAI0_TXFS 4 +-#define IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD IMX8QXP_SAI1_RXD 0 +-#define IMX8QXP_SAI1_RXD_ADMA_SAI0_RXFS IMX8QXP_SAI1_RXD 1 +-#define IMX8QXP_SAI1_RXD_ADMA_SPI1_CS1 IMX8QXP_SAI1_RXD 2 +-#define IMX8QXP_SAI1_RXD_ADMA_LCDIF_D21 IMX8QXP_SAI1_RXD 3 +-#define IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 IMX8QXP_SAI1_RXD 4 +-#define IMX8QXP_SAI1_RXC_ADMA_SAI1_RXC IMX8QXP_SAI1_RXC 0 +-#define IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC IMX8QXP_SAI1_RXC 1 +-#define IMX8QXP_SAI1_RXC_ADMA_LCDIF_D22 IMX8QXP_SAI1_RXC 3 +-#define IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 IMX8QXP_SAI1_RXC 4 +-#define IMX8QXP_SAI1_RXFS_ADMA_SAI1_RXFS IMX8QXP_SAI1_RXFS 0 +-#define IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS IMX8QXP_SAI1_RXFS 1 +-#define IMX8QXP_SAI1_RXFS_ADMA_LCDIF_D23 IMX8QXP_SAI1_RXFS 3 +-#define IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 IMX8QXP_SAI1_RXFS 4 +-#define IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 IMX8QXP_SPI2_CS0 0 +-#define IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 IMX8QXP_SPI2_CS0 4 +-#define IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO IMX8QXP_SPI2_SDO 0 +-#define IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 IMX8QXP_SPI2_SDO 4 +-#define IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI IMX8QXP_SPI2_SDI 0 +-#define IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 IMX8QXP_SPI2_SDI 4 +-#define IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK IMX8QXP_SPI2_SCK 0 +-#define IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 IMX8QXP_SPI2_SCK 4 +-#define IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK IMX8QXP_SPI0_SCK 0 +-#define IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC IMX8QXP_SPI0_SCK 1 +-#define IMX8QXP_SPI0_SCK_M40_I2C0_SCL IMX8QXP_SPI0_SCK 2 +-#define IMX8QXP_SPI0_SCK_M40_GPIO0_IO00 IMX8QXP_SPI0_SCK 3 +-#define IMX8QXP_SPI0_SCK_LSIO_GPIO1_IO04 IMX8QXP_SPI0_SCK 4 +-#define IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI IMX8QXP_SPI0_SDI 0 +-#define IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD IMX8QXP_SPI0_SDI 1 +-#define IMX8QXP_SPI0_SDI_M40_TPM0_CH0 IMX8QXP_SPI0_SDI 2 +-#define IMX8QXP_SPI0_SDI_M40_GPIO0_IO02 IMX8QXP_SPI0_SDI 3 +-#define IMX8QXP_SPI0_SDI_LSIO_GPIO1_IO05 IMX8QXP_SPI0_SDI 4 +-#define IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO IMX8QXP_SPI0_SDO 0 +-#define IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS IMX8QXP_SPI0_SDO 1 +-#define IMX8QXP_SPI0_SDO_M40_I2C0_SDA IMX8QXP_SPI0_SDO 2 +-#define IMX8QXP_SPI0_SDO_M40_GPIO0_IO01 IMX8QXP_SPI0_SDO 3 +-#define IMX8QXP_SPI0_SDO_LSIO_GPIO1_IO06 IMX8QXP_SPI0_SDO 4 +-#define IMX8QXP_SPI0_CS1_ADMA_SPI0_CS1 IMX8QXP_SPI0_CS1 0 +-#define IMX8QXP_SPI0_CS1_ADMA_SAI0_RXC IMX8QXP_SPI0_CS1 1 +-#define IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD IMX8QXP_SPI0_CS1 2 +-#define IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT IMX8QXP_SPI0_CS1 3 +-#define IMX8QXP_SPI0_CS1_LSIO_GPIO1_IO07 IMX8QXP_SPI0_CS1 4 +-#define IMX8QXP_SPI0_CS0_ADMA_SPI0_CS0 IMX8QXP_SPI0_CS0 0 +-#define IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD IMX8QXP_SPI0_CS0 1 +-#define IMX8QXP_SPI0_CS0_M40_TPM0_CH1 IMX8QXP_SPI0_CS0 2 +-#define IMX8QXP_SPI0_CS0_M40_GPIO0_IO03 IMX8QXP_SPI0_CS0 3 +-#define IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08 IMX8QXP_SPI0_CS0 4 +-#define IMX8QXP_ADC_IN1_ADMA_ADC_IN1 IMX8QXP_ADC_IN1 0 +-#define IMX8QXP_ADC_IN1_M40_I2C0_SDA IMX8QXP_ADC_IN1 1 +-#define IMX8QXP_ADC_IN1_M40_GPIO0_IO01 IMX8QXP_ADC_IN1 2 +-#define IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 IMX8QXP_ADC_IN1 4 +-#define IMX8QXP_ADC_IN0_ADMA_ADC_IN0 IMX8QXP_ADC_IN0 0 +-#define IMX8QXP_ADC_IN0_M40_I2C0_SCL IMX8QXP_ADC_IN0 1 +-#define IMX8QXP_ADC_IN0_M40_GPIO0_IO00 IMX8QXP_ADC_IN0 2 +-#define IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 IMX8QXP_ADC_IN0 4 +-#define IMX8QXP_ADC_IN3_ADMA_ADC_IN3 IMX8QXP_ADC_IN3 0 +-#define IMX8QXP_ADC_IN3_M40_UART0_TX IMX8QXP_ADC_IN3 1 +-#define IMX8QXP_ADC_IN3_M40_GPIO0_IO03 IMX8QXP_ADC_IN3 2 +-#define IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 IMX8QXP_ADC_IN3 3 +-#define IMX8QXP_ADC_IN3_LSIO_GPIO1_IO11 IMX8QXP_ADC_IN3 4 +-#define IMX8QXP_ADC_IN2_ADMA_ADC_IN2 IMX8QXP_ADC_IN2 0 +-#define IMX8QXP_ADC_IN2_M40_UART0_RX IMX8QXP_ADC_IN2 1 +-#define IMX8QXP_ADC_IN2_M40_GPIO0_IO02 IMX8QXP_ADC_IN2 2 +-#define IMX8QXP_ADC_IN2_ADMA_ACM_MCLK_IN0 IMX8QXP_ADC_IN2 3 +-#define IMX8QXP_ADC_IN2_LSIO_GPIO1_IO12 IMX8QXP_ADC_IN2 4 +-#define IMX8QXP_ADC_IN5_ADMA_ADC_IN5 IMX8QXP_ADC_IN5 0 +-#define IMX8QXP_ADC_IN5_M40_TPM0_CH1 IMX8QXP_ADC_IN5 1 +-#define IMX8QXP_ADC_IN5_M40_GPIO0_IO05 IMX8QXP_ADC_IN5 2 +-#define IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13 IMX8QXP_ADC_IN5 4 +-#define IMX8QXP_ADC_IN4_ADMA_ADC_IN4 IMX8QXP_ADC_IN4 0 +-#define IMX8QXP_ADC_IN4_M40_TPM0_CH0 IMX8QXP_ADC_IN4 1 +-#define IMX8QXP_ADC_IN4_M40_GPIO0_IO04 IMX8QXP_ADC_IN4 2 +-#define IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14 IMX8QXP_ADC_IN4 4 +-#define IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX IMX8QXP_FLEXCAN0_RX 0 +-#define IMX8QXP_FLEXCAN0_RX_ADMA_SAI2_RXC IMX8QXP_FLEXCAN0_RX 1 +-#define IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B IMX8QXP_FLEXCAN0_RX 2 +-#define IMX8QXP_FLEXCAN0_RX_ADMA_SAI1_TXC IMX8QXP_FLEXCAN0_RX 3 +-#define IMX8QXP_FLEXCAN0_RX_LSIO_GPIO1_IO15 IMX8QXP_FLEXCAN0_RX 4 +-#define IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX IMX8QXP_FLEXCAN0_TX 0 +-#define IMX8QXP_FLEXCAN0_TX_ADMA_SAI2_RXD IMX8QXP_FLEXCAN0_TX 1 +-#define IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B IMX8QXP_FLEXCAN0_TX 2 +-#define IMX8QXP_FLEXCAN0_TX_ADMA_SAI1_TXFS IMX8QXP_FLEXCAN0_TX 3 +-#define IMX8QXP_FLEXCAN0_TX_LSIO_GPIO1_IO16 IMX8QXP_FLEXCAN0_TX 4 +-#define IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX IMX8QXP_FLEXCAN1_RX 0 +-#define IMX8QXP_FLEXCAN1_RX_ADMA_SAI2_RXFS IMX8QXP_FLEXCAN1_RX 1 +-#define IMX8QXP_FLEXCAN1_RX_ADMA_FTM_CH2 IMX8QXP_FLEXCAN1_RX 2 +-#define IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD IMX8QXP_FLEXCAN1_RX 3 +-#define IMX8QXP_FLEXCAN1_RX_LSIO_GPIO1_IO17 IMX8QXP_FLEXCAN1_RX 4 +-#define IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX IMX8QXP_FLEXCAN1_TX 0 +-#define IMX8QXP_FLEXCAN1_TX_ADMA_SAI3_RXC IMX8QXP_FLEXCAN1_TX 1 +-#define IMX8QXP_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 IMX8QXP_FLEXCAN1_TX 2 +-#define IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD IMX8QXP_FLEXCAN1_TX 3 +-#define IMX8QXP_FLEXCAN1_TX_LSIO_GPIO1_IO18 IMX8QXP_FLEXCAN1_TX 4 +-#define IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX IMX8QXP_FLEXCAN2_RX 0 +-#define IMX8QXP_FLEXCAN2_RX_ADMA_SAI3_RXD IMX8QXP_FLEXCAN2_RX 1 +-#define IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX IMX8QXP_FLEXCAN2_RX 2 +-#define IMX8QXP_FLEXCAN2_RX_ADMA_SAI1_RXFS IMX8QXP_FLEXCAN2_RX 3 +-#define IMX8QXP_FLEXCAN2_RX_LSIO_GPIO1_IO19 IMX8QXP_FLEXCAN2_RX 4 +-#define IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX IMX8QXP_FLEXCAN2_TX 0 +-#define IMX8QXP_FLEXCAN2_TX_ADMA_SAI3_RXFS IMX8QXP_FLEXCAN2_TX 1 +-#define IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX IMX8QXP_FLEXCAN2_TX 2 +-#define IMX8QXP_FLEXCAN2_TX_ADMA_SAI1_RXC IMX8QXP_FLEXCAN2_TX 3 +-#define IMX8QXP_FLEXCAN2_TX_LSIO_GPIO1_IO20 IMX8QXP_FLEXCAN2_TX 4 +-#define IMX8QXP_UART0_RX_ADMA_UART0_RX IMX8QXP_UART0_RX 0 +-#define IMX8QXP_UART0_RX_ADMA_MQS_R IMX8QXP_UART0_RX 1 +-#define IMX8QXP_UART0_RX_ADMA_FLEXCAN0_RX IMX8QXP_UART0_RX 2 +-#define IMX8QXP_UART0_RX_LSIO_GPIO1_IO21 IMX8QXP_UART0_RX 4 +-#define IMX8QXP_UART0_TX_ADMA_UART0_TX IMX8QXP_UART0_TX 0 +-#define IMX8QXP_UART0_TX_ADMA_MQS_L IMX8QXP_UART0_TX 1 +-#define IMX8QXP_UART0_TX_ADMA_FLEXCAN0_TX IMX8QXP_UART0_TX 2 +-#define IMX8QXP_UART0_TX_LSIO_GPIO1_IO22 IMX8QXP_UART0_TX 4 +-#define IMX8QXP_UART2_TX_ADMA_UART2_TX IMX8QXP_UART2_TX 0 +-#define IMX8QXP_UART2_TX_ADMA_FTM_CH1 IMX8QXP_UART2_TX 1 +-#define IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX IMX8QXP_UART2_TX 2 +-#define IMX8QXP_UART2_TX_LSIO_GPIO1_IO23 IMX8QXP_UART2_TX 4 +-#define IMX8QXP_UART2_RX_ADMA_UART2_RX IMX8QXP_UART2_RX 0 +-#define IMX8QXP_UART2_RX_ADMA_FTM_CH0 IMX8QXP_UART2_RX 1 +-#define IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX IMX8QXP_UART2_RX 2 +-#define IMX8QXP_UART2_RX_LSIO_GPIO1_IO24 IMX8QXP_UART2_RX 4 +-#define IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL IMX8QXP_MIPI_DSI0_I2C0_SCL 0 +-#define IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 IMX8QXP_MIPI_DSI0_I2C0_SCL 1 +-#define IMX8QXP_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 IMX8QXP_MIPI_DSI0_I2C0_SCL 4 +-#define IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA IMX8QXP_MIPI_DSI0_I2C0_SDA 0 +-#define IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 IMX8QXP_MIPI_DSI0_I2C0_SDA 1 +-#define IMX8QXP_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 IMX8QXP_MIPI_DSI0_I2C0_SDA 4 +-#define IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 IMX8QXP_MIPI_DSI0_GPIO0_00 0 +-#define IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL IMX8QXP_MIPI_DSI0_GPIO0_00 1 +-#define IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT IMX8QXP_MIPI_DSI0_GPIO0_00 2 +-#define IMX8QXP_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 IMX8QXP_MIPI_DSI0_GPIO0_00 4 +-#define IMX8QXP_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 IMX8QXP_MIPI_DSI0_GPIO0_01 0 +-#define IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA IMX8QXP_MIPI_DSI0_GPIO0_01 1 +-#define IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 IMX8QXP_MIPI_DSI0_GPIO0_01 4 +-#define IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL IMX8QXP_MIPI_DSI1_I2C0_SCL 0 +-#define IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 IMX8QXP_MIPI_DSI1_I2C0_SCL 1 +-#define IMX8QXP_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 IMX8QXP_MIPI_DSI1_I2C0_SCL 4 +-#define IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA IMX8QXP_MIPI_DSI1_I2C0_SDA 0 +-#define IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 IMX8QXP_MIPI_DSI1_I2C0_SDA 1 +-#define IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 IMX8QXP_MIPI_DSI1_I2C0_SDA 4 +-#define IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 IMX8QXP_MIPI_DSI1_GPIO0_00 0 +-#define IMX8QXP_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL IMX8QXP_MIPI_DSI1_GPIO0_00 1 +-#define IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT IMX8QXP_MIPI_DSI1_GPIO0_00 2 +-#define IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 IMX8QXP_MIPI_DSI1_GPIO0_00 4 +-#define IMX8QXP_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 IMX8QXP_MIPI_DSI1_GPIO0_01 0 +-#define IMX8QXP_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA IMX8QXP_MIPI_DSI1_GPIO0_01 1 +-#define IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 IMX8QXP_MIPI_DSI1_GPIO0_01 4 +-#define IMX8QXP_JTAG_TRST_B_SCU_JTAG_TRST_B IMX8QXP_JTAG_TRST_B 0 +-#define IMX8QXP_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT IMX8QXP_JTAG_TRST_B 1 +-#define IMX8QXP_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL IMX8QXP_PMIC_I2C_SCL 0 +-#define IMX8QXP_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON IMX8QXP_PMIC_I2C_SCL 1 +-#define IMX8QXP_PMIC_I2C_SCL_LSIO_GPIO2_IO01 IMX8QXP_PMIC_I2C_SCL 4 +-#define IMX8QXP_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA IMX8QXP_PMIC_I2C_SDA 0 +-#define IMX8QXP_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON IMX8QXP_PMIC_I2C_SDA 1 +-#define IMX8QXP_PMIC_I2C_SDA_LSIO_GPIO2_IO02 IMX8QXP_PMIC_I2C_SDA 4 +-#define IMX8QXP_PMIC_INT_B_SCU_DIMX8QXPMIC_INT_B IMX8QXP_PMIC_INT_B 0 +-#define IMX8QXP_SCU_GPIO0_00_SCU_GPIO0_IO00 IMX8QXP_SCU_GPIO0_00 0 +-#define IMX8QXP_SCU_GPIO0_00_SCU_UART0_RX IMX8QXP_SCU_GPIO0_00 1 +-#define IMX8QXP_SCU_GPIO0_00_M40_UART0_RX IMX8QXP_SCU_GPIO0_00 2 +-#define IMX8QXP_SCU_GPIO0_00_ADMA_UART3_RX IMX8QXP_SCU_GPIO0_00 3 +-#define IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 IMX8QXP_SCU_GPIO0_00 4 +-#define IMX8QXP_SCU_GPIO0_01_SCU_GPIO0_IO01 IMX8QXP_SCU_GPIO0_01 0 +-#define IMX8QXP_SCU_GPIO0_01_SCU_UART0_TX IMX8QXP_SCU_GPIO0_01 1 +-#define IMX8QXP_SCU_GPIO0_01_M40_UART0_TX IMX8QXP_SCU_GPIO0_01 2 +-#define IMX8QXP_SCU_GPIO0_01_ADMA_UART3_TX IMX8QXP_SCU_GPIO0_01 3 +-#define IMX8QXP_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT IMX8QXP_SCU_GPIO0_01 4 +-#define IMX8QXP_SCU_PMIC_STANDBY_SCU_DIMX8QXPMIC_STANDBY IMX8QXP_SCU_PMIC_STANDBY 0 +-#define IMX8QXP_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 IMX8QXP_SCU_BOOT_MODE0 0 +-#define IMX8QXP_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 IMX8QXP_SCU_BOOT_MODE1 0 +-#define IMX8QXP_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 IMX8QXP_SCU_BOOT_MODE2 0 +-#define IMX8QXP_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA IMX8QXP_SCU_BOOT_MODE2 1 +-#define IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 IMX8QXP_SCU_BOOT_MODE3 0 +-#define IMX8QXP_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL IMX8QXP_SCU_BOOT_MODE3 1 +-#define IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K IMX8QXP_SCU_BOOT_MODE3 3 +-#define IMX8QXP_CSI_D00_CI_PI_D02 IMX8QXP_CSI_D00 0 +-#define IMX8QXP_CSI_D00_ADMA_SAI0_RXC IMX8QXP_CSI_D00 2 +-#define IMX8QXP_CSI_D01_CI_PI_D03 IMX8QXP_CSI_D01 0 +-#define IMX8QXP_CSI_D01_ADMA_SAI0_RXD IMX8QXP_CSI_D01 2 +-#define IMX8QXP_CSI_D02_CI_PI_D04 IMX8QXP_CSI_D02 0 +-#define IMX8QXP_CSI_D02_ADMA_SAI0_RXFS IMX8QXP_CSI_D02 2 +-#define IMX8QXP_CSI_D03_CI_PI_D05 IMX8QXP_CSI_D03 0 +-#define IMX8QXP_CSI_D03_ADMA_SAI2_RXC IMX8QXP_CSI_D03 2 +-#define IMX8QXP_CSI_D04_CI_PI_D06 IMX8QXP_CSI_D04 0 +-#define IMX8QXP_CSI_D04_ADMA_SAI2_RXD IMX8QXP_CSI_D04 2 +-#define IMX8QXP_CSI_D05_CI_PI_D07 IMX8QXP_CSI_D05 0 +-#define IMX8QXP_CSI_D05_ADMA_SAI2_RXFS IMX8QXP_CSI_D05 2 +-#define IMX8QXP_CSI_D06_CI_PI_D08 IMX8QXP_CSI_D06 0 +-#define IMX8QXP_CSI_D06_ADMA_SAI3_RXC IMX8QXP_CSI_D06 2 +-#define IMX8QXP_CSI_D07_CI_PI_D09 IMX8QXP_CSI_D07 0 +-#define IMX8QXP_CSI_D07_ADMA_SAI3_RXD IMX8QXP_CSI_D07 2 +-#define IMX8QXP_CSI_HSYNC_CI_PI_HSYNC IMX8QXP_CSI_HSYNC 0 +-#define IMX8QXP_CSI_HSYNC_CI_PI_D00 IMX8QXP_CSI_HSYNC 1 +-#define IMX8QXP_CSI_HSYNC_ADMA_SAI3_RXFS IMX8QXP_CSI_HSYNC 2 +-#define IMX8QXP_CSI_VSYNC_CI_PI_VSYNC IMX8QXP_CSI_VSYNC 0 +-#define IMX8QXP_CSI_VSYNC_CI_PI_D01 IMX8QXP_CSI_VSYNC 1 +-#define IMX8QXP_CSI_PCLK_CI_PI_PCLK IMX8QXP_CSI_PCLK 0 +-#define IMX8QXP_CSI_PCLK_MIPI_CSI0_I2C0_SCL IMX8QXP_CSI_PCLK 1 +-#define IMX8QXP_CSI_PCLK_ADMA_SPI1_SCK IMX8QXP_CSI_PCLK 3 +-#define IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 IMX8QXP_CSI_PCLK 4 +-#define IMX8QXP_CSI_MCLK_CI_PI_MCLK IMX8QXP_CSI_MCLK 0 +-#define IMX8QXP_CSI_MCLK_MIPI_CSI0_I2C0_SDA IMX8QXP_CSI_MCLK 1 +-#define IMX8QXP_CSI_MCLK_ADMA_SPI1_SDO IMX8QXP_CSI_MCLK 3 +-#define IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 IMX8QXP_CSI_MCLK 4 +-#define IMX8QXP_CSI_EN_CI_PI_EN IMX8QXP_CSI_EN 0 +-#define IMX8QXP_CSI_EN_CI_PI_I2C_SCL IMX8QXP_CSI_EN 1 +-#define IMX8QXP_CSI_EN_ADMA_I2C3_SCL IMX8QXP_CSI_EN 2 +-#define IMX8QXP_CSI_EN_ADMA_SPI1_SDI IMX8QXP_CSI_EN 3 +-#define IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 IMX8QXP_CSI_EN 4 +-#define IMX8QXP_CSI_RESET_CI_PI_RESET IMX8QXP_CSI_RESET 0 +-#define IMX8QXP_CSI_RESET_CI_PI_I2C_SDA IMX8QXP_CSI_RESET 1 +-#define IMX8QXP_CSI_RESET_ADMA_I2C3_SDA IMX8QXP_CSI_RESET 2 +-#define IMX8QXP_CSI_RESET_ADMA_SPI1_CS0 IMX8QXP_CSI_RESET 3 +-#define IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 IMX8QXP_CSI_RESET 4 +-#define IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT IMX8QXP_MIPI_CSI0_MCLK_OUT 0 +-#define IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 IMX8QXP_MIPI_CSI0_MCLK_OUT 4 +-#define IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL IMX8QXP_MIPI_CSI0_I2C0_SCL 0 +-#define IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 IMX8QXP_MIPI_CSI0_I2C0_SCL 1 +-#define IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 IMX8QXP_MIPI_CSI0_I2C0_SCL 4 +-#define IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA IMX8QXP_MIPI_CSI0_I2C0_SDA 0 +-#define IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 IMX8QXP_MIPI_CSI0_I2C0_SDA 1 +-#define IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 IMX8QXP_MIPI_CSI0_I2C0_SDA 4 +-#define IMX8QXP_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 IMX8QXP_MIPI_CSI0_GPIO0_01 0 +-#define IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA IMX8QXP_MIPI_CSI0_GPIO0_01 1 +-#define IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 IMX8QXP_MIPI_CSI0_GPIO0_01 4 +-#define IMX8QXP_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 IMX8QXP_MIPI_CSI0_GPIO0_00 0 +-#define IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL IMX8QXP_MIPI_CSI0_GPIO0_00 1 +-#define IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 IMX8QXP_MIPI_CSI0_GPIO0_00 4 +-#define IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 IMX8QXP_QSPI0A_DATA0 0 +-#define IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 IMX8QXP_QSPI0A_DATA0 4 +-#define IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 IMX8QXP_QSPI0A_DATA1 0 +-#define IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 IMX8QXP_QSPI0A_DATA1 4 +-#define IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 IMX8QXP_QSPI0A_DATA2 0 +-#define IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 IMX8QXP_QSPI0A_DATA2 4 +-#define IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 IMX8QXP_QSPI0A_DATA3 0 +-#define IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 IMX8QXP_QSPI0A_DATA3 4 +-#define IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS IMX8QXP_QSPI0A_DQS 0 +-#define IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 IMX8QXP_QSPI0A_DQS 4 +-#define IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B IMX8QXP_QSPI0A_SS0_B 0 +-#define IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 IMX8QXP_QSPI0A_SS0_B 4 +-#define IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B IMX8QXP_QSPI0A_SS1_B 0 +-#define IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 IMX8QXP_QSPI0A_SS1_B 4 +-#define IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK IMX8QXP_QSPI0A_SCLK 0 +-#define IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 IMX8QXP_QSPI0A_SCLK 4 +-#define IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK IMX8QXP_QSPI0B_SCLK 0 +-#define IMX8QXP_QSPI0B_SCLK_LSIO_QSPI1A_SCLK IMX8QXP_QSPI0B_SCLK 1 +-#define IMX8QXP_QSPI0B_SCLK_LSIO_KPP0_COL0 IMX8QXP_QSPI0B_SCLK 2 +-#define IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 IMX8QXP_QSPI0B_SCLK 4 +-#define IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 IMX8QXP_QSPI0B_DATA0 0 +-#define IMX8QXP_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 IMX8QXP_QSPI0B_DATA0 1 +-#define IMX8QXP_QSPI0B_DATA0_LSIO_KPP0_COL1 IMX8QXP_QSPI0B_DATA0 2 +-#define IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 IMX8QXP_QSPI0B_DATA0 4 +-#define IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 IMX8QXP_QSPI0B_DATA1 0 +-#define IMX8QXP_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 IMX8QXP_QSPI0B_DATA1 1 +-#define IMX8QXP_QSPI0B_DATA1_LSIO_KPP0_COL2 IMX8QXP_QSPI0B_DATA1 2 +-#define IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 IMX8QXP_QSPI0B_DATA1 4 +-#define IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 IMX8QXP_QSPI0B_DATA2 0 +-#define IMX8QXP_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 IMX8QXP_QSPI0B_DATA2 1 +-#define IMX8QXP_QSPI0B_DATA2_LSIO_KPP0_COL3 IMX8QXP_QSPI0B_DATA2 2 +-#define IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 IMX8QXP_QSPI0B_DATA2 4 +-#define IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 IMX8QXP_QSPI0B_DATA3 0 +-#define IMX8QXP_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 IMX8QXP_QSPI0B_DATA3 1 +-#define IMX8QXP_QSPI0B_DATA3_LSIO_KPP0_ROW0 IMX8QXP_QSPI0B_DATA3 2 +-#define IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 IMX8QXP_QSPI0B_DATA3 4 +-#define IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS IMX8QXP_QSPI0B_DQS 0 +-#define IMX8QXP_QSPI0B_DQS_LSIO_QSPI1A_DQS IMX8QXP_QSPI0B_DQS 1 +-#define IMX8QXP_QSPI0B_DQS_LSIO_KPP0_ROW1 IMX8QXP_QSPI0B_DQS 2 +-#define IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 IMX8QXP_QSPI0B_DQS 4 +-#define IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B IMX8QXP_QSPI0B_SS0_B 0 +-#define IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B IMX8QXP_QSPI0B_SS0_B 1 +-#define IMX8QXP_QSPI0B_SS0_B_LSIO_KPP0_ROW2 IMX8QXP_QSPI0B_SS0_B 2 +-#define IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 IMX8QXP_QSPI0B_SS0_B 4 +-#define IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B IMX8QXP_QSPI0B_SS1_B 0 +-#define IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B IMX8QXP_QSPI0B_SS1_B 1 +-#define IMX8QXP_QSPI0B_SS1_B_LSIO_KPP0_ROW3 IMX8QXP_QSPI0B_SS1_B 2 +-#define IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 IMX8QXP_QSPI0B_SS1_B 4 +- +-#endif /* _IMX8QXP_PADS_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h +deleted file mode 100644 +index 20f43404cac0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * pinctrl-tegra-io-pad.h: Tegra I/O pad source voltage configuration constants +- * pinctrl bindings. +- * +- * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. +- * +- * Author: Aapo Vienamo +- */ +- +-#ifndef _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H +-#define _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H +- +-/* Voltage levels of the I/O pad's source rail */ +-#define TEGRA_IO_PAD_VOLTAGE_1V8 0 +-#define TEGRA_IO_PAD_VOLTAGE_3V3 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pinctrl-tegra-xusb.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pinctrl-tegra-xusb.h +deleted file mode 100644 +index ac63c399b4b6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pinctrl-tegra-xusb.h ++++ /dev/null +@@ -1,8 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H +-#define _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 1 +- +-#define TEGRA_XUSB_PADCTL_PCIE 0 +-#define TEGRA_XUSB_PADCTL_SATA 1 +- +-#endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pinctrl-tegra.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pinctrl-tegra.h +deleted file mode 100644 +index d9b18bf26496..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pinctrl-tegra.h ++++ /dev/null +@@ -1,37 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * This header provides constants for Tegra pinctrl bindings. +- * +- * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. +- * +- * Author: Laxman Dewangan +- */ +- +-#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H +-#define _DT_BINDINGS_PINCTRL_TEGRA_H +- +-/* +- * Enable/disable for diffeent dt properties. This is applicable for +- * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, +- * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. +- */ +-#define TEGRA_PIN_DISABLE 0 +-#define TEGRA_PIN_ENABLE 1 +- +-#define TEGRA_PIN_PULL_NONE 0 +-#define TEGRA_PIN_PULL_DOWN 1 +-#define TEGRA_PIN_PULL_UP 2 +- +-/* Low power mode driver */ +-#define TEGRA_PIN_LP_DRIVE_DIV_8 0 +-#define TEGRA_PIN_LP_DRIVE_DIV_4 1 +-#define TEGRA_PIN_LP_DRIVE_DIV_2 2 +-#define TEGRA_PIN_LP_DRIVE_DIV_1 3 +- +-/* Rising/Falling slew rate */ +-#define TEGRA_PIN_SLEW_RATE_FASTEST 0 +-#define TEGRA_PIN_SLEW_RATE_FAST 1 +-#define TEGRA_PIN_SLEW_RATE_SLOW 2 +-#define TEGRA_PIN_SLEW_RATE_SLOWEST 3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pinctrl-zynq.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pinctrl-zynq.h +deleted file mode 100644 +index bbfc345f017d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pinctrl-zynq.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * MIO pin configuration defines for Xilinx Zynq +- * +- * Copyright (C) 2021 Xilinx, Inc. +- */ +- +-#ifndef _DT_BINDINGS_PINCTRL_ZYNQ_H +-#define _DT_BINDINGS_PINCTRL_ZYNQ_H +- +-/* Configuration options for different power supplies */ +-#define IO_STANDARD_LVCMOS18 1 +-#define IO_STANDARD_LVCMOS25 2 +-#define IO_STANDARD_LVCMOS33 3 +-#define IO_STANDARD_HSTL 4 +- +-#endif /* _DT_BINDINGS_PINCTRL_ZYNQ_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pinctrl-zynqmp.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pinctrl-zynqmp.h +deleted file mode 100644 +index cdb215734bdf..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/pinctrl-zynqmp.h ++++ /dev/null +@@ -1,19 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * MIO pin configuration defines for Xilinx ZynqMP +- * +- * Copyright (C) 2020 Xilinx, Inc. +- */ +- +-#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H +-#define _DT_BINDINGS_PINCTRL_ZYNQMP_H +- +-/* Bit value for different voltage levels */ +-#define IO_STANDARD_LVCMOS33 0 +-#define IO_STANDARD_LVCMOS18 1 +- +-/* Bit values for Slew Rates */ +-#define SLEW_RATE_FAST 0 +-#define SLEW_RATE_SLOW 1 +- +-#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/qcom,pmic-gpio.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/qcom,pmic-gpio.h +deleted file mode 100644 +index e5df5ce45a0f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/qcom,pmic-gpio.h ++++ /dev/null +@@ -1,164 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for the Qualcomm PMIC GPIO binding. +- */ +- +-#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H +-#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H +- +-#define PMIC_GPIO_PULL_UP_30 0 +-#define PMIC_GPIO_PULL_UP_1P5 1 +-#define PMIC_GPIO_PULL_UP_31P5 2 +-#define PMIC_GPIO_PULL_UP_1P5_30 3 +- +-#define PMIC_GPIO_STRENGTH_NO 0 +-#define PMIC_GPIO_STRENGTH_HIGH 1 +-#define PMIC_GPIO_STRENGTH_MED 2 +-#define PMIC_GPIO_STRENGTH_LOW 3 +- +-/* +- * Note: PM8018 GPIO3 and GPIO4 are supporting +- * only S3 and L2 options (1.8V) +- */ +-#define PM8018_GPIO_L6 0 +-#define PM8018_GPIO_L5 1 +-#define PM8018_GPIO_S3 2 +-#define PM8018_GPIO_L14 3 +-#define PM8018_GPIO_L2 4 +-#define PM8018_GPIO_L4 5 +-#define PM8018_GPIO_VDD 6 +- +-/* +- * Note: PM8038 GPIO7 and GPIO8 are supporting +- * only L11 and L4 options (1.8V) +- */ +-#define PM8038_GPIO_VPH 0 +-#define PM8038_GPIO_BB 1 +-#define PM8038_GPIO_L11 2 +-#define PM8038_GPIO_L15 3 +-#define PM8038_GPIO_L4 4 +-#define PM8038_GPIO_L3 5 +-#define PM8038_GPIO_L17 6 +- +-#define PM8058_GPIO_VPH 0 +-#define PM8058_GPIO_BB 1 +-#define PM8058_GPIO_S3 2 +-#define PM8058_GPIO_L3 3 +-#define PM8058_GPIO_L7 4 +-#define PM8058_GPIO_L6 5 +-#define PM8058_GPIO_L5 6 +-#define PM8058_GPIO_L2 7 +- +-/* +- * Note: PM8916 GPIO1 and GPIO2 are supporting +- * only L2(1.15V) and L5(1.8V) options +- */ +-#define PM8916_GPIO_VPH 0 +-#define PM8916_GPIO_L2 2 +-#define PM8916_GPIO_L5 3 +- +-#define PM8917_GPIO_VPH 0 +-#define PM8917_GPIO_S4 2 +-#define PM8917_GPIO_L15 3 +-#define PM8917_GPIO_L4 4 +-#define PM8917_GPIO_L3 5 +-#define PM8917_GPIO_L17 6 +- +-#define PM8921_GPIO_VPH 0 +-#define PM8921_GPIO_BB 1 +-#define PM8921_GPIO_S4 2 +-#define PM8921_GPIO_L15 3 +-#define PM8921_GPIO_L4 4 +-#define PM8921_GPIO_L3 5 +-#define PM8921_GPIO_L17 6 +- +-/* +- * Note: PM8941 gpios from 15 to 18 are supporting +- * only S3 and L6 options (1.8V) +- */ +-#define PM8941_GPIO_VPH 0 +-#define PM8941_GPIO_L1 1 +-#define PM8941_GPIO_S3 2 +-#define PM8941_GPIO_L6 3 +- +-/* +- * Note: PMA8084 gpios from 15 to 18 are supporting +- * only S4 and L6 options (1.8V) +- */ +-#define PMA8084_GPIO_VPH 0 +-#define PMA8084_GPIO_L1 1 +-#define PMA8084_GPIO_S4 2 +-#define PMA8084_GPIO_L6 3 +- +-#define PM8994_GPIO_VPH 0 +-#define PM8994_GPIO_S4 2 +-#define PM8994_GPIO_L12 3 +- +-/* To be used with "function" */ +-#define PMIC_GPIO_FUNC_NORMAL "normal" +-#define PMIC_GPIO_FUNC_PAIRED "paired" +-#define PMIC_GPIO_FUNC_FUNC1 "func1" +-#define PMIC_GPIO_FUNC_FUNC2 "func2" +-#define PMIC_GPIO_FUNC_FUNC3 "func3" +-#define PMIC_GPIO_FUNC_FUNC4 "func4" +-#define PMIC_GPIO_FUNC_DTEST1 "dtest1" +-#define PMIC_GPIO_FUNC_DTEST2 "dtest2" +-#define PMIC_GPIO_FUNC_DTEST3 "dtest3" +-#define PMIC_GPIO_FUNC_DTEST4 "dtest4" +- +-#define PM8038_GPIO1_2_LPG_DRV PMIC_GPIO_FUNC_FUNC1 +-#define PM8038_GPIO3_5V_BOOST_EN PMIC_GPIO_FUNC_FUNC1 +-#define PM8038_GPIO4_SSBI_ALT_CLK PMIC_GPIO_FUNC_FUNC1 +-#define PM8038_GPIO5_6_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 +-#define PM8038_GPIO10_11_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 +-#define PM8038_GPIO6_7_CLK PMIC_GPIO_FUNC_FUNC1 +-#define PM8038_GPIO9_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 +-#define PM8038_GPIO6_12_KYPD_DRV PMIC_GPIO_FUNC_FUNC2 +- +-#define PM8058_GPIO7_8_MP3_CLK PMIC_GPIO_FUNC_FUNC1 +-#define PM8058_GPIO7_8_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC2 +-#define PM8058_GPIO9_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 +-#define PM8058_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2 +-#define PM8058_GPIO24_26_LPG_DRV PMIC_GPIO_FUNC_FUNC2 +-#define PM8058_GPIO33_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1 +-#define PM8058_GPIO34_35_MP3_CLK PMIC_GPIO_FUNC_FUNC1 +-#define PM8058_GPIO36_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1 +-#define PM8058_GPIO37_UPL_OUT PMIC_GPIO_FUNC_FUNC1 +-#define PM8058_GPIO37_UART_M_RX PMIC_GPIO_FUNC_FUNC2 +-#define PM8058_GPIO38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1 +-#define PM8058_GPIO38_39_CLK_32KHZ PMIC_GPIO_FUNC_FUNC2 +-#define PM8058_GPIO39_MP3_CLK PMIC_GPIO_FUNC_FUNC1 +-#define PM8058_GPIO40_EXT_BB_EN PMIC_GPIO_FUNC_FUNC1 +- +-#define PM8916_GPIO1_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 +-#define PM8916_GPIO1_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 +-#define PM8916_GPIO2_DIV_CLK PMIC_GPIO_FUNC_FUNC1 +-#define PM8916_GPIO2_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 +-#define PM8916_GPIO3_KEYP_DRV PMIC_GPIO_FUNC_FUNC1 +-#define PM8916_GPIO4_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 +- +-#define PM8917_GPIO9_18_KEYP_DRV PMIC_GPIO_FUNC_FUNC1 +-#define PM8917_GPIO20_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 +-#define PM8917_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2 +-#define PM8917_GPIO25_26_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 +-#define PM8917_GPIO37_38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1 +-#define PM8917_GPIO37_38_MP3_CLK PMIC_GPIO_FUNC_FUNC2 +- +-#define PM8941_GPIO9_14_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 +-#define PM8941_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1 +-#define PM8941_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 +-#define PM8941_GPIO23_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 +-#define PM8941_GPIO23_26_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2 +-#define PM8941_GPIO31_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 +-#define PM8941_GPIO33_36_LPG_DRV_3D PMIC_GPIO_FUNC_FUNC1 +-#define PM8941_GPIO33_36_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2 +- +-#define PMA8084_GPIO4_5_LPG_DRV PMIC_GPIO_FUNC_FUNC1 +-#define PMA8084_GPIO7_10_LPG_DRV PMIC_GPIO_FUNC_FUNC1 +-#define PMA8084_GPIO5_14_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 +-#define PMA8084_GPIO19_21_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 +-#define PMA8084_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1 +-#define PMA8084_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 +-#define PMA8084_GPIO22_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/qcom,pmic-mpp.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/qcom,pmic-mpp.h +deleted file mode 100644 +index 32e66ee7e830..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/qcom,pmic-mpp.h ++++ /dev/null +@@ -1,106 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for the Qualcomm PMIC's +- * Multi-Purpose Pin binding. +- */ +- +-#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H +-#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H +- +-/* power-source */ +- +-/* Digital Input/Output: level [PM8058] */ +-#define PM8058_MPP_VPH 0 +-#define PM8058_MPP_S3 1 +-#define PM8058_MPP_L2 2 +-#define PM8058_MPP_L3 3 +- +-/* Digital Input/Output: level [PM8901] */ +-#define PM8901_MPP_MSMIO 0 +-#define PM8901_MPP_DIG 1 +-#define PM8901_MPP_L5 2 +-#define PM8901_MPP_S4 3 +-#define PM8901_MPP_VPH 4 +- +-/* Digital Input/Output: level [PM8921] */ +-#define PM8921_MPP_S4 1 +-#define PM8921_MPP_L15 3 +-#define PM8921_MPP_L17 4 +-#define PM8921_MPP_VPH 7 +- +-/* Digital Input/Output: level [PM8821] */ +-#define PM8821_MPP_1P8 0 +-#define PM8821_MPP_VPH 7 +- +-/* Digital Input/Output: level [PM8018] */ +-#define PM8018_MPP_L4 0 +-#define PM8018_MPP_L14 1 +-#define PM8018_MPP_S3 2 +-#define PM8018_MPP_L6 3 +-#define PM8018_MPP_L2 4 +-#define PM8018_MPP_L5 5 +-#define PM8018_MPP_VPH 7 +- +-/* Digital Input/Output: level [PM8038] */ +-#define PM8038_MPP_L20 0 +-#define PM8038_MPP_L11 1 +-#define PM8038_MPP_L5 2 +-#define PM8038_MPP_L15 3 +-#define PM8038_MPP_L17 4 +-#define PM8038_MPP_VPH 7 +- +-#define PM8841_MPP_VPH 0 +-#define PM8841_MPP_S3 2 +- +-#define PM8916_MPP_VPH 0 +-#define PM8916_MPP_L2 2 +-#define PM8916_MPP_L5 3 +- +-#define PM8941_MPP_VPH 0 +-#define PM8941_MPP_L1 1 +-#define PM8941_MPP_S3 2 +-#define PM8941_MPP_L6 3 +- +-#define PMA8084_MPP_VPH 0 +-#define PMA8084_MPP_L1 1 +-#define PMA8084_MPP_S4 2 +-#define PMA8084_MPP_L6 3 +- +-#define PM8994_MPP_VPH 0 +-/* Only supported for MPP_05-MPP_08 */ +-#define PM8994_MPP_L19 1 +-#define PM8994_MPP_S4 2 +-#define PM8994_MPP_L12 3 +- +-/* +- * Analog Input - Set the source for analog input. +- * To be used with "qcom,amux-route" property +- */ +-#define PMIC_MPP_AMUX_ROUTE_CH5 0 +-#define PMIC_MPP_AMUX_ROUTE_CH6 1 +-#define PMIC_MPP_AMUX_ROUTE_CH7 2 +-#define PMIC_MPP_AMUX_ROUTE_CH8 3 +-#define PMIC_MPP_AMUX_ROUTE_ABUS1 4 +-#define PMIC_MPP_AMUX_ROUTE_ABUS2 5 +-#define PMIC_MPP_AMUX_ROUTE_ABUS3 6 +-#define PMIC_MPP_AMUX_ROUTE_ABUS4 7 +- +-/* Analog Output: level */ +-#define PMIC_MPP_AOUT_LVL_1V25 0 +-#define PMIC_MPP_AOUT_LVL_1V25_2 1 +-#define PMIC_MPP_AOUT_LVL_0V625 2 +-#define PMIC_MPP_AOUT_LVL_0V3125 3 +-#define PMIC_MPP_AOUT_LVL_MPP 4 +-#define PMIC_MPP_AOUT_LVL_ABUS1 5 +-#define PMIC_MPP_AOUT_LVL_ABUS2 6 +-#define PMIC_MPP_AOUT_LVL_ABUS3 7 +- +-/* To be used with "function" */ +-#define PMIC_MPP_FUNC_NORMAL "normal" +-#define PMIC_MPP_FUNC_PAIRED "paired" +-#define PMIC_MPP_FUNC_DTEST1 "dtest1" +-#define PMIC_MPP_FUNC_DTEST2 "dtest2" +-#define PMIC_MPP_FUNC_DTEST3 "dtest3" +-#define PMIC_MPP_FUNC_DTEST4 "dtest4" +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/r7s72100-pinctrl.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/r7s72100-pinctrl.h +deleted file mode 100644 +index cdb950246880..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/r7s72100-pinctrl.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Defines macros and constants for Renesas RZ/A1 pin controller pin +- * muxing functions. +- */ +-#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H +-#define __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H +- +-#define RZA1_PINS_PER_PORT 16 +- +-/* +- * Create the pin index from its bank and position numbers and store in +- * the upper 16 bits the alternate function identifier +- */ +-#define RZA1_PINMUX(b, p, f) ((b) * RZA1_PINS_PER_PORT + (p) | (f << 16)) +- +-#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/r7s9210-pinctrl.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/r7s9210-pinctrl.h +deleted file mode 100644 +index 2d0c23e5d3a7..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/r7s9210-pinctrl.h ++++ /dev/null +@@ -1,47 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Defines macros and constants for Renesas RZ/A2 pin controller pin +- * muxing functions. +- */ +-#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H +-#define __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H +- +-#define RZA2_PINS_PER_PORT 8 +- +-/* Port names as labeled in the Hardware Manual */ +-#define PORT0 0 +-#define PORT1 1 +-#define PORT2 2 +-#define PORT3 3 +-#define PORT4 4 +-#define PORT5 5 +-#define PORT6 6 +-#define PORT7 7 +-#define PORT8 8 +-#define PORT9 9 +-#define PORTA 10 +-#define PORTB 11 +-#define PORTC 12 +-#define PORTD 13 +-#define PORTE 14 +-#define PORTF 15 +-#define PORTG 16 +-#define PORTH 17 +-/* No I */ +-#define PORTJ 18 +-#define PORTK 19 +-#define PORTL 20 +-#define PORTM 21 /* Pins PM_0/1 are labeled JP_0/1 in HW manual */ +- +-/* +- * Create the pin index from its bank and position numbers and store in +- * the upper 16 bits the alternate function identifier +- */ +-#define RZA2_PINMUX(b, p, f) ((b) * RZA2_PINS_PER_PORT + (p) | (f << 16)) +- +-/* +- * Convert a port and pin label to its global pin index +- */ +- #define RZA2_PIN(port, pin) ((port) * RZA2_PINS_PER_PORT + (pin)) +- +-#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/rockchip.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/rockchip.h +deleted file mode 100644 +index 5f291045e8fd..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/rockchip.h ++++ /dev/null +@@ -1,47 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Header providing constants for Rockchip pinctrl bindings. +- * +- * Copyright (c) 2013 MundoReader S.L. +- * Author: Heiko Stuebner +- */ +- +-#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ +-#define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ +- +-#define RK_PA0 0 +-#define RK_PA1 1 +-#define RK_PA2 2 +-#define RK_PA3 3 +-#define RK_PA4 4 +-#define RK_PA5 5 +-#define RK_PA6 6 +-#define RK_PA7 7 +-#define RK_PB0 8 +-#define RK_PB1 9 +-#define RK_PB2 10 +-#define RK_PB3 11 +-#define RK_PB4 12 +-#define RK_PB5 13 +-#define RK_PB6 14 +-#define RK_PB7 15 +-#define RK_PC0 16 +-#define RK_PC1 17 +-#define RK_PC2 18 +-#define RK_PC3 19 +-#define RK_PC4 20 +-#define RK_PC5 21 +-#define RK_PC6 22 +-#define RK_PC7 23 +-#define RK_PD0 24 +-#define RK_PD1 25 +-#define RK_PD2 26 +-#define RK_PD3 27 +-#define RK_PD4 28 +-#define RK_PD5 29 +-#define RK_PD6 30 +-#define RK_PD7 31 +- +-#define RK_FUNC_GPIO 0 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/rzg2l-pinctrl.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/rzg2l-pinctrl.h +deleted file mode 100644 +index b48f8c7a5556..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/rzg2l-pinctrl.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +-/* +- * This header provides constants for Renesas RZ/G2L family pinctrl bindings. +- * +- * Copyright (C) 2021 Renesas Electronics Corp. +- * +- */ +- +-#ifndef __DT_BINDINGS_RZG2L_PINCTRL_H +-#define __DT_BINDINGS_RZG2L_PINCTRL_H +- +-#define RZG2L_PINS_PER_PORT 8 +- +-/* +- * Create the pin index from its bank and position numbers and store in +- * the upper 16 bits the alternate function identifier +- */ +-#define RZG2L_PORT_PINMUX(b, p, f) ((b) * RZG2L_PINS_PER_PORT + (p) | ((f) << 16)) +- +-/* Convert a port and pin label to its global pin index */ +- #define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin)) +- +-#endif /* __DT_BINDINGS_RZG2L_PINCTRL_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/rzn1-pinctrl.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/rzn1-pinctrl.h +deleted file mode 100644 +index 21d6cc4d59f5..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/rzn1-pinctrl.h ++++ /dev/null +@@ -1,141 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Defines macros and constants for Renesas RZ/N1 pin controller pin +- * muxing functions. +- */ +-#ifndef __DT_BINDINGS_RZN1_PINCTRL_H +-#define __DT_BINDINGS_RZN1_PINCTRL_H +- +-#define RZN1_PINMUX(_gpio, _func) \ +- (((_func) << 8) | (_gpio)) +- +-/* +- * Given the different levels of muxing on the SoC, it was decided to +- * 'linearize' them into one numerical space. So mux level 1, 2 and the MDIO +- * muxes are all represented by one single value. +- * +- * You can derive the hardware value pretty easily too, as +- * 0...9 are Level 1 +- * 10...71 are Level 2. The Level 2 mux will be set to this +- * value - RZN1_FUNC_L2_OFFSET, and the Level 1 mux will be +- * set accordingly. +- * 72...103 are for the 2 MDIO muxes. +- */ +-#define RZN1_FUNC_HIGHZ 0 +-#define RZN1_FUNC_0L 1 +-#define RZN1_FUNC_CLK_ETH_MII_RGMII_RMII 2 +-#define RZN1_FUNC_CLK_ETH_NAND 3 +-#define RZN1_FUNC_QSPI 4 +-#define RZN1_FUNC_SDIO 5 +-#define RZN1_FUNC_LCD 6 +-#define RZN1_FUNC_LCD_E 7 +-#define RZN1_FUNC_MSEBIM 8 +-#define RZN1_FUNC_MSEBIS 9 +-#define RZN1_FUNC_L2_OFFSET 10 /* I'm Special */ +- +-#define RZN1_FUNC_HIGHZ1 (RZN1_FUNC_L2_OFFSET + 0) +-#define RZN1_FUNC_ETHERCAT (RZN1_FUNC_L2_OFFSET + 1) +-#define RZN1_FUNC_SERCOS3 (RZN1_FUNC_L2_OFFSET + 2) +-#define RZN1_FUNC_SDIO_E (RZN1_FUNC_L2_OFFSET + 3) +-#define RZN1_FUNC_ETH_MDIO (RZN1_FUNC_L2_OFFSET + 4) +-#define RZN1_FUNC_ETH_MDIO_E1 (RZN1_FUNC_L2_OFFSET + 5) +-#define RZN1_FUNC_USB (RZN1_FUNC_L2_OFFSET + 6) +-#define RZN1_FUNC_MSEBIM_E (RZN1_FUNC_L2_OFFSET + 7) +-#define RZN1_FUNC_MSEBIS_E (RZN1_FUNC_L2_OFFSET + 8) +-#define RZN1_FUNC_RSV (RZN1_FUNC_L2_OFFSET + 9) +-#define RZN1_FUNC_RSV_E (RZN1_FUNC_L2_OFFSET + 10) +-#define RZN1_FUNC_RSV_E1 (RZN1_FUNC_L2_OFFSET + 11) +-#define RZN1_FUNC_UART0_I (RZN1_FUNC_L2_OFFSET + 12) +-#define RZN1_FUNC_UART0_I_E (RZN1_FUNC_L2_OFFSET + 13) +-#define RZN1_FUNC_UART1_I (RZN1_FUNC_L2_OFFSET + 14) +-#define RZN1_FUNC_UART1_I_E (RZN1_FUNC_L2_OFFSET + 15) +-#define RZN1_FUNC_UART2_I (RZN1_FUNC_L2_OFFSET + 16) +-#define RZN1_FUNC_UART2_I_E (RZN1_FUNC_L2_OFFSET + 17) +-#define RZN1_FUNC_UART0 (RZN1_FUNC_L2_OFFSET + 18) +-#define RZN1_FUNC_UART0_E (RZN1_FUNC_L2_OFFSET + 19) +-#define RZN1_FUNC_UART1 (RZN1_FUNC_L2_OFFSET + 20) +-#define RZN1_FUNC_UART1_E (RZN1_FUNC_L2_OFFSET + 21) +-#define RZN1_FUNC_UART2 (RZN1_FUNC_L2_OFFSET + 22) +-#define RZN1_FUNC_UART2_E (RZN1_FUNC_L2_OFFSET + 23) +-#define RZN1_FUNC_UART3 (RZN1_FUNC_L2_OFFSET + 24) +-#define RZN1_FUNC_UART3_E (RZN1_FUNC_L2_OFFSET + 25) +-#define RZN1_FUNC_UART4 (RZN1_FUNC_L2_OFFSET + 26) +-#define RZN1_FUNC_UART4_E (RZN1_FUNC_L2_OFFSET + 27) +-#define RZN1_FUNC_UART5 (RZN1_FUNC_L2_OFFSET + 28) +-#define RZN1_FUNC_UART5_E (RZN1_FUNC_L2_OFFSET + 29) +-#define RZN1_FUNC_UART6 (RZN1_FUNC_L2_OFFSET + 30) +-#define RZN1_FUNC_UART6_E (RZN1_FUNC_L2_OFFSET + 31) +-#define RZN1_FUNC_UART7 (RZN1_FUNC_L2_OFFSET + 32) +-#define RZN1_FUNC_UART7_E (RZN1_FUNC_L2_OFFSET + 33) +-#define RZN1_FUNC_SPI0_M (RZN1_FUNC_L2_OFFSET + 34) +-#define RZN1_FUNC_SPI0_M_E (RZN1_FUNC_L2_OFFSET + 35) +-#define RZN1_FUNC_SPI1_M (RZN1_FUNC_L2_OFFSET + 36) +-#define RZN1_FUNC_SPI1_M_E (RZN1_FUNC_L2_OFFSET + 37) +-#define RZN1_FUNC_SPI2_M (RZN1_FUNC_L2_OFFSET + 38) +-#define RZN1_FUNC_SPI2_M_E (RZN1_FUNC_L2_OFFSET + 39) +-#define RZN1_FUNC_SPI3_M (RZN1_FUNC_L2_OFFSET + 40) +-#define RZN1_FUNC_SPI3_M_E (RZN1_FUNC_L2_OFFSET + 41) +-#define RZN1_FUNC_SPI4_S (RZN1_FUNC_L2_OFFSET + 42) +-#define RZN1_FUNC_SPI4_S_E (RZN1_FUNC_L2_OFFSET + 43) +-#define RZN1_FUNC_SPI5_S (RZN1_FUNC_L2_OFFSET + 44) +-#define RZN1_FUNC_SPI5_S_E (RZN1_FUNC_L2_OFFSET + 45) +-#define RZN1_FUNC_SGPIO0_M (RZN1_FUNC_L2_OFFSET + 46) +-#define RZN1_FUNC_SGPIO1_M (RZN1_FUNC_L2_OFFSET + 47) +-#define RZN1_FUNC_GPIO (RZN1_FUNC_L2_OFFSET + 48) +-#define RZN1_FUNC_CAN (RZN1_FUNC_L2_OFFSET + 49) +-#define RZN1_FUNC_I2C (RZN1_FUNC_L2_OFFSET + 50) +-#define RZN1_FUNC_SAFE (RZN1_FUNC_L2_OFFSET + 51) +-#define RZN1_FUNC_PTO_PWM (RZN1_FUNC_L2_OFFSET + 52) +-#define RZN1_FUNC_PTO_PWM1 (RZN1_FUNC_L2_OFFSET + 53) +-#define RZN1_FUNC_PTO_PWM2 (RZN1_FUNC_L2_OFFSET + 54) +-#define RZN1_FUNC_PTO_PWM3 (RZN1_FUNC_L2_OFFSET + 55) +-#define RZN1_FUNC_PTO_PWM4 (RZN1_FUNC_L2_OFFSET + 56) +-#define RZN1_FUNC_DELTA_SIGMA (RZN1_FUNC_L2_OFFSET + 57) +-#define RZN1_FUNC_SGPIO2_M (RZN1_FUNC_L2_OFFSET + 58) +-#define RZN1_FUNC_SGPIO3_M (RZN1_FUNC_L2_OFFSET + 59) +-#define RZN1_FUNC_SGPIO4_S (RZN1_FUNC_L2_OFFSET + 60) +-#define RZN1_FUNC_MAC_MTIP_SWITCH (RZN1_FUNC_L2_OFFSET + 61) +- +-#define RZN1_FUNC_MDIO_OFFSET (RZN1_FUNC_L2_OFFSET + 62) +- +-/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO function */ +-#define RZN1_FUNC_MDIO0_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 0) +-#define RZN1_FUNC_MDIO0_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 1) +-#define RZN1_FUNC_MDIO0_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 2) +-#define RZN1_FUNC_MDIO0_ECAT (RZN1_FUNC_MDIO_OFFSET + 3) +-#define RZN1_FUNC_MDIO0_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 4) +-#define RZN1_FUNC_MDIO0_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 5) +-#define RZN1_FUNC_MDIO0_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 6) +-#define RZN1_FUNC_MDIO0_SWITCH (RZN1_FUNC_MDIO_OFFSET + 7) +-/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ +-#define RZN1_FUNC_MDIO0_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 8) +-#define RZN1_FUNC_MDIO0_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 9) +-#define RZN1_FUNC_MDIO0_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 10) +-#define RZN1_FUNC_MDIO0_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 11) +-#define RZN1_FUNC_MDIO0_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 12) +-#define RZN1_FUNC_MDIO0_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 13) +-#define RZN1_FUNC_MDIO0_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 14) +-#define RZN1_FUNC_MDIO0_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 15) +- +-/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO function */ +-#define RZN1_FUNC_MDIO1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 16) +-#define RZN1_FUNC_MDIO1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 17) +-#define RZN1_FUNC_MDIO1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 18) +-#define RZN1_FUNC_MDIO1_ECAT (RZN1_FUNC_MDIO_OFFSET + 19) +-#define RZN1_FUNC_MDIO1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 20) +-#define RZN1_FUNC_MDIO1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 21) +-#define RZN1_FUNC_MDIO1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 22) +-#define RZN1_FUNC_MDIO1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 23) +-/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ +-#define RZN1_FUNC_MDIO1_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 24) +-#define RZN1_FUNC_MDIO1_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 25) +-#define RZN1_FUNC_MDIO1_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 26) +-#define RZN1_FUNC_MDIO1_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 27) +-#define RZN1_FUNC_MDIO1_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 28) +-#define RZN1_FUNC_MDIO1_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 29) +-#define RZN1_FUNC_MDIO1_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 30) +-#define RZN1_FUNC_MDIO1_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 31) +- +-#define RZN1_FUNC_MAX (RZN1_FUNC_MDIO_OFFSET + 32) +- +-#endif /* __DT_BINDINGS_RZN1_PINCTRL_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/samsung.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/samsung.h +deleted file mode 100644 +index b1832506b923..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/samsung.h ++++ /dev/null +@@ -1,77 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Samsung's Exynos pinctrl bindings +- * +- * Copyright (c) 2016 Samsung Electronics Co., Ltd. +- * http://www.samsung.com +- * Author: Krzysztof Kozlowski +- */ +- +-#ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__ +-#define __DT_BINDINGS_PINCTRL_SAMSUNG_H__ +- +-#define EXYNOS_PIN_PULL_NONE 0 +-#define EXYNOS_PIN_PULL_DOWN 1 +-#define EXYNOS_PIN_PULL_UP 3 +- +-#define S3C64XX_PIN_PULL_NONE 0 +-#define S3C64XX_PIN_PULL_DOWN 1 +-#define S3C64XX_PIN_PULL_UP 2 +- +-/* Pin function in power down mode */ +-#define EXYNOS_PIN_PDN_OUT0 0 +-#define EXYNOS_PIN_PDN_OUT1 1 +-#define EXYNOS_PIN_PDN_INPUT 2 +-#define EXYNOS_PIN_PDN_PREV 3 +- +-/* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */ +-#define EXYNOS4_PIN_DRV_LV1 0 +-#define EXYNOS4_PIN_DRV_LV2 2 +-#define EXYNOS4_PIN_DRV_LV3 1 +-#define EXYNOS4_PIN_DRV_LV4 3 +- +-/* Drive strengths for Exynos5260 */ +-#define EXYNOS5260_PIN_DRV_LV1 0 +-#define EXYNOS5260_PIN_DRV_LV2 1 +-#define EXYNOS5260_PIN_DRV_LV4 2 +-#define EXYNOS5260_PIN_DRV_LV6 3 +- +-/* Drive strengths for Exynos5410, Exynos542x and Exynos5800 */ +-#define EXYNOS5420_PIN_DRV_LV1 0 +-#define EXYNOS5420_PIN_DRV_LV2 1 +-#define EXYNOS5420_PIN_DRV_LV3 2 +-#define EXYNOS5420_PIN_DRV_LV4 3 +- +-/* Drive strengths for Exynos5433 */ +-#define EXYNOS5433_PIN_DRV_FAST_SR1 0 +-#define EXYNOS5433_PIN_DRV_FAST_SR2 1 +-#define EXYNOS5433_PIN_DRV_FAST_SR3 2 +-#define EXYNOS5433_PIN_DRV_FAST_SR4 3 +-#define EXYNOS5433_PIN_DRV_FAST_SR5 4 +-#define EXYNOS5433_PIN_DRV_FAST_SR6 5 +-#define EXYNOS5433_PIN_DRV_SLOW_SR1 8 +-#define EXYNOS5433_PIN_DRV_SLOW_SR2 9 +-#define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa +-#define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb +-#define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc +-#define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf +- +-#define EXYNOS_PIN_FUNC_INPUT 0 +-#define EXYNOS_PIN_FUNC_OUTPUT 1 +-#define EXYNOS_PIN_FUNC_2 2 +-#define EXYNOS_PIN_FUNC_3 3 +-#define EXYNOS_PIN_FUNC_4 4 +-#define EXYNOS_PIN_FUNC_5 5 +-#define EXYNOS_PIN_FUNC_6 6 +-#define EXYNOS_PIN_FUNC_EINT 0xf +-#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT +- +-/* Drive strengths for Exynos7 FSYS1 block */ +-#define EXYNOS7_FSYS1_PIN_DRV_LV1 0 +-#define EXYNOS7_FSYS1_PIN_DRV_LV2 4 +-#define EXYNOS7_FSYS1_PIN_DRV_LV3 2 +-#define EXYNOS7_FSYS1_PIN_DRV_LV4 6 +-#define EXYNOS7_FSYS1_PIN_DRV_LV5 1 +-#define EXYNOS7_FSYS1_PIN_DRV_LV6 5 +- +-#endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/stm32-pinfunc.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/stm32-pinfunc.h +deleted file mode 100644 +index e6fb8ada3f4d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/stm32-pinfunc.h ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +-/* +- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved +- * Author: Torgue Alexandre for STMicroelectronics. +- */ +- +-#ifndef _DT_BINDINGS_STM32_PINFUNC_H +-#define _DT_BINDINGS_STM32_PINFUNC_H +- +-/* define PIN modes */ +-#define GPIO 0x0 +-#define AF0 0x1 +-#define AF1 0x2 +-#define AF2 0x3 +-#define AF3 0x4 +-#define AF4 0x5 +-#define AF5 0x6 +-#define AF6 0x7 +-#define AF7 0x8 +-#define AF8 0x9 +-#define AF9 0xa +-#define AF10 0xb +-#define AF11 0xc +-#define AF12 0xd +-#define AF13 0xe +-#define AF14 0xf +-#define AF15 0x10 +-#define ANALOG 0x11 +- +-/* define Pins number*/ +-#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line)) +- +-#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode)) +- +-/* package information */ +-#define STM32MP_PKG_AA 0x1 +-#define STM32MP_PKG_AB 0x2 +-#define STM32MP_PKG_AC 0x4 +-#define STM32MP_PKG_AD 0x8 +- +-#endif /* _DT_BINDINGS_STM32_PINFUNC_H */ +- +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/sun4i-a10.h b/scripts/dtc/include-prefixes/dt-bindings/pinctrl/sun4i-a10.h +deleted file mode 100644 +index f7553c143b40..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pinctrl/sun4i-a10.h ++++ /dev/null +@@ -1,62 +0,0 @@ +-/* +- * Copyright 2014 Maxime Ripard +- * +- * Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this file; if not, write to the Free +- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +- * MA 02110-1301 USA +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ +-#define __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ +- +-#define SUN4I_PINCTRL_10_MA 0 +-#define SUN4I_PINCTRL_20_MA 1 +-#define SUN4I_PINCTRL_30_MA 2 +-#define SUN4I_PINCTRL_40_MA 3 +- +-#define SUN4I_PINCTRL_NO_PULL 0 +-#define SUN4I_PINCTRL_PULL_UP 1 +-#define SUN4I_PINCTRL_PULL_DOWN 2 +- +-#endif /* __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pmu/exynos_ppmu.h b/scripts/dtc/include-prefixes/dt-bindings/pmu/exynos_ppmu.h +deleted file mode 100644 +index 8724abe130f3..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pmu/exynos_ppmu.h ++++ /dev/null +@@ -1,25 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Samsung Exynos PPMU event types for counting in regs +- * +- * Copyright (c) 2019, Samsung Electronics +- * Author: Lukasz Luba +- */ +- +-#ifndef __DT_BINDINGS_PMU_EXYNOS_PPMU_H +-#define __DT_BINDINGS_PMU_EXYNOS_PPMU_H +- +-#define PPMU_RO_BUSY_CYCLE_CNT 0x0 +-#define PPMU_WO_BUSY_CYCLE_CNT 0x1 +-#define PPMU_RW_BUSY_CYCLE_CNT 0x2 +-#define PPMU_RO_REQUEST_CNT 0x3 +-#define PPMU_WO_REQUEST_CNT 0x4 +-#define PPMU_RO_DATA_CNT 0x5 +-#define PPMU_WO_DATA_CNT 0x6 +-#define PPMU_RO_LATENCY 0x12 +-#define PPMU_WO_LATENCY 0x16 +-#define PPMU_V2_RO_DATA_CNT 0x4 +-#define PPMU_V2_WO_DATA_CNT 0x5 +-#define PPMU_V2_EVT3_RW_DATA_CNT 0x22 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/imx7-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/imx7-power.h +deleted file mode 100644 +index 597c1aa06ae5..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/imx7-power.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2017 Impinj +- */ +- +-#ifndef __DT_BINDINGS_IMX7_POWER_H__ +-#define __DT_BINDINGS_IMX7_POWER_H__ +- +-#define IMX7_POWER_DOMAIN_MIPI_PHY 0 +-#define IMX7_POWER_DOMAIN_PCIE_PHY 1 +-#define IMX7_POWER_DOMAIN_USB_HSIC_PHY 2 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/imx8mm-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/imx8mm-power.h +deleted file mode 100644 +index fc9c2e16aadc..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/imx8mm-power.h ++++ /dev/null +@@ -1,22 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +-/* +- * Copyright (C) 2020 Pengutronix, Lucas Stach +- */ +- +-#ifndef __DT_BINDINGS_IMX8MM_POWER_H__ +-#define __DT_BINDINGS_IMX8MM_POWER_H__ +- +-#define IMX8MM_POWER_DOMAIN_HSIOMIX 0 +-#define IMX8MM_POWER_DOMAIN_PCIE 1 +-#define IMX8MM_POWER_DOMAIN_OTG1 2 +-#define IMX8MM_POWER_DOMAIN_OTG2 3 +-#define IMX8MM_POWER_DOMAIN_GPUMIX 4 +-#define IMX8MM_POWER_DOMAIN_GPU 5 +-#define IMX8MM_POWER_DOMAIN_VPUMIX 6 +-#define IMX8MM_POWER_DOMAIN_VPUG1 7 +-#define IMX8MM_POWER_DOMAIN_VPUG2 8 +-#define IMX8MM_POWER_DOMAIN_VPUH1 9 +-#define IMX8MM_POWER_DOMAIN_DISPMIX 10 +-#define IMX8MM_POWER_DOMAIN_MIPI 11 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/imx8mn-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/imx8mn-power.h +deleted file mode 100644 +index 102ee85a9b62..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/imx8mn-power.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +-/* +- * Copyright (C) 2020 Compass Electronics Group, LLC +- */ +- +-#ifndef __DT_BINDINGS_IMX8MN_POWER_H__ +-#define __DT_BINDINGS_IMX8MN_POWER_H__ +- +-#define IMX8MN_POWER_DOMAIN_HSIOMIX 0 +-#define IMX8MN_POWER_DOMAIN_OTG1 1 +-#define IMX8MN_POWER_DOMAIN_GPUMIX 2 +-#define IMX8MN_POWER_DOMAIN_DISPMIX 3 +-#define IMX8MN_POWER_DOMAIN_MIPI 4 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/imx8mq-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/imx8mq-power.h +deleted file mode 100644 +index 8a513bd9166e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/imx8mq-power.h ++++ /dev/null +@@ -1,21 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +-/* +- * Copyright (C) 2018 Pengutronix, Lucas Stach +- */ +- +-#ifndef __DT_BINDINGS_IMX8MQ_POWER_H__ +-#define __DT_BINDINGS_IMX8MQ_POWER_H__ +- +-#define IMX8M_POWER_DOMAIN_MIPI 0 +-#define IMX8M_POWER_DOMAIN_PCIE1 1 +-#define IMX8M_POWER_DOMAIN_USB_OTG1 2 +-#define IMX8M_POWER_DOMAIN_USB_OTG2 3 +-#define IMX8M_POWER_DOMAIN_DDR1 4 +-#define IMX8M_POWER_DOMAIN_GPU 5 +-#define IMX8M_POWER_DOMAIN_VPU 6 +-#define IMX8M_POWER_DOMAIN_DISP 7 +-#define IMX8M_POWER_DOMAIN_MIPI_CSI1 8 +-#define IMX8M_POWER_DOMAIN_MIPI_CSI2 9 +-#define IMX8M_POWER_DOMAIN_PCIE2 10 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/marvell,mmp2.h b/scripts/dtc/include-prefixes/dt-bindings/power/marvell,mmp2.h +deleted file mode 100644 +index c53d2b3e1057..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/marvell,mmp2.h ++++ /dev/null +@@ -1,11 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DTS_MARVELL_MMP2_POWER_H +-#define __DTS_MARVELL_MMP2_POWER_H +- +-#define MMP2_POWER_DOMAIN_GPU 0 +-#define MMP2_POWER_DOMAIN_AUDIO 1 +-#define MMP3_POWER_DOMAIN_CAMERA 2 +- +-#define MMP2_NR_POWER_DOMAINS 3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/meson-a1-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/meson-a1-power.h +deleted file mode 100644 +index 6cf50bfb8ccf..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/meson-a1-power.h ++++ /dev/null +@@ -1,32 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +-/* +- * Copyright (c) 2019 Amlogic, Inc. +- * Author: Jianxin Pan +- */ +- +-#ifndef _DT_BINDINGS_MESON_A1_POWER_H +-#define _DT_BINDINGS_MESON_A1_POWER_H +- +-#define PWRC_DSPA_ID 8 +-#define PWRC_DSPB_ID 9 +-#define PWRC_UART_ID 10 +-#define PWRC_DMC_ID 11 +-#define PWRC_I2C_ID 12 +-#define PWRC_PSRAM_ID 13 +-#define PWRC_ACODEC_ID 14 +-#define PWRC_AUDIO_ID 15 +-#define PWRC_OTP_ID 16 +-#define PWRC_DMA_ID 17 +-#define PWRC_SD_EMMC_ID 18 +-#define PWRC_RAMA_ID 19 +-#define PWRC_RAMB_ID 20 +-#define PWRC_IR_ID 21 +-#define PWRC_SPICC_ID 22 +-#define PWRC_SPIFC_ID 23 +-#define PWRC_USB_ID 24 +-#define PWRC_NIC_ID 25 +-#define PWRC_PDMIN_ID 26 +-#define PWRC_RSA_ID 27 +-#define PWRC_MAX_ID 28 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/meson-axg-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/meson-axg-power.h +deleted file mode 100644 +index e5243884b249..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/meson-axg-power.h ++++ /dev/null +@@ -1,14 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +-/* +- * Copyright (c) 2020 BayLibre, SAS +- * Author: Neil Armstrong +- */ +- +-#ifndef _DT_BINDINGS_MESON_AXG_POWER_H +-#define _DT_BINDINGS_MESON_AXG_POWER_H +- +-#define PWRC_AXG_VPU_ID 0 +-#define PWRC_AXG_ETHERNET_MEM_ID 1 +-#define PWRC_AXG_AUDIO_ID 2 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/meson-g12a-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/meson-g12a-power.h +deleted file mode 100644 +index bb5e67a842de..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/meson-g12a-power.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- */ +- +-#ifndef _DT_BINDINGS_MESON_G12A_POWER_H +-#define _DT_BINDINGS_MESON_G12A_POWER_H +- +-#define PWRC_G12A_VPU_ID 0 +-#define PWRC_G12A_ETH_ID 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/meson-gxbb-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/meson-gxbb-power.h +deleted file mode 100644 +index 1262dac696c0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/meson-gxbb-power.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- */ +- +-#ifndef _DT_BINDINGS_MESON_GXBB_POWER_H +-#define _DT_BINDINGS_MESON_GXBB_POWER_H +- +-#define PWRC_GXBB_VPU_ID 0 +-#define PWRC_GXBB_ETHERNET_MEM_ID 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/meson-sm1-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/meson-sm1-power.h +deleted file mode 100644 +index a020ab00c134..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/meson-sm1-power.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +-/* +- * Copyright (c) 2019 BayLibre, SAS +- * Author: Neil Armstrong +- */ +- +-#ifndef _DT_BINDINGS_MESON_SM1_POWER_H +-#define _DT_BINDINGS_MESON_SM1_POWER_H +- +-#define PWRC_SM1_VPU_ID 0 +-#define PWRC_SM1_NNA_ID 1 +-#define PWRC_SM1_USB_ID 2 +-#define PWRC_SM1_PCIE_ID 3 +-#define PWRC_SM1_GE2D_ID 4 +-#define PWRC_SM1_AUDIO_ID 5 +-#define PWRC_SM1_ETH_ID 6 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/meson8-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/meson8-power.h +deleted file mode 100644 +index dd8b2ddb82a7..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/meson8-power.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +-/* +- * Copyright (c) 2019 Martin Blumenstingl +- */ +- +-#ifndef _DT_BINDINGS_MESON8_POWER_H +-#define _DT_BINDINGS_MESON8_POWER_H +- +-#define PWRC_MESON8_VPU_ID 0 +-#define PWRC_MESON8_ETHERNET_MEM_ID 1 +-#define PWRC_MESON8_AUDIO_DSP_MEM_ID 2 +- +-#endif /* _DT_BINDINGS_MESON8_POWER_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/mt2701-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/mt2701-power.h +deleted file mode 100644 +index 09e16f895761..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/mt2701-power.h ++++ /dev/null +@@ -1,19 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2015 MediaTek Inc. +- */ +- +-#ifndef _DT_BINDINGS_POWER_MT2701_POWER_H +-#define _DT_BINDINGS_POWER_MT2701_POWER_H +- +-#define MT2701_POWER_DOMAIN_CONN 0 +-#define MT2701_POWER_DOMAIN_DISP 1 +-#define MT2701_POWER_DOMAIN_MFG 2 +-#define MT2701_POWER_DOMAIN_VDEC 3 +-#define MT2701_POWER_DOMAIN_ISP 4 +-#define MT2701_POWER_DOMAIN_BDP 5 +-#define MT2701_POWER_DOMAIN_ETH 6 +-#define MT2701_POWER_DOMAIN_HIF 7 +-#define MT2701_POWER_DOMAIN_IFR_MSC 8 +- +-#endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/mt2712-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/mt2712-power.h +deleted file mode 100644 +index 95bdb1c20f71..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/mt2712-power.h ++++ /dev/null +@@ -1,21 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2017 MediaTek Inc. +- */ +- +-#ifndef _DT_BINDINGS_POWER_MT2712_POWER_H +-#define _DT_BINDINGS_POWER_MT2712_POWER_H +- +-#define MT2712_POWER_DOMAIN_MM 0 +-#define MT2712_POWER_DOMAIN_VDEC 1 +-#define MT2712_POWER_DOMAIN_VENC 2 +-#define MT2712_POWER_DOMAIN_ISP 3 +-#define MT2712_POWER_DOMAIN_AUDIO 4 +-#define MT2712_POWER_DOMAIN_USB 5 +-#define MT2712_POWER_DOMAIN_USB2 6 +-#define MT2712_POWER_DOMAIN_MFG 7 +-#define MT2712_POWER_DOMAIN_MFG_SC1 8 +-#define MT2712_POWER_DOMAIN_MFG_SC2 9 +-#define MT2712_POWER_DOMAIN_MFG_SC3 10 +- +-#endif /* _DT_BINDINGS_POWER_MT2712_POWER_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/mt6765-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/mt6765-power.h +deleted file mode 100644 +index d347b4ee9eed..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/mt6765-power.h ++++ /dev/null +@@ -1,14 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef _DT_BINDINGS_POWER_MT6765_POWER_H +-#define _DT_BINDINGS_POWER_MT6765_POWER_H +- +-#define MT6765_POWER_DOMAIN_CONN 0 +-#define MT6765_POWER_DOMAIN_MM 1 +-#define MT6765_POWER_DOMAIN_MFG_ASYNC 2 +-#define MT6765_POWER_DOMAIN_ISP 3 +-#define MT6765_POWER_DOMAIN_MFG 4 +-#define MT6765_POWER_DOMAIN_MFG_CORE0 5 +-#define MT6765_POWER_DOMAIN_CAM 6 +-#define MT6765_POWER_DOMAIN_VCODEC 7 +- +-#endif /* _DT_BINDINGS_POWER_MT6765_POWER_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/mt6797-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/mt6797-power.h +deleted file mode 100644 +index a60c1d81cf75..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/mt6797-power.h ++++ /dev/null +@@ -1,30 +0,0 @@ +-/* +- * Copyright (c) 2017 MediaTek Inc. +- * Author: Mars.C +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License version 2 as +- * published by the Free Software Foundation. +- * +- * This program is distributed in the hope that it will be useful, +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#ifndef _DT_BINDINGS_POWER_MT6797_POWER_H +-#define _DT_BINDINGS_POWER_MT6797_POWER_H +- +-#define MT6797_POWER_DOMAIN_VDEC 0 +-#define MT6797_POWER_DOMAIN_VENC 1 +-#define MT6797_POWER_DOMAIN_ISP 2 +-#define MT6797_POWER_DOMAIN_MM 3 +-#define MT6797_POWER_DOMAIN_AUDIO 4 +-#define MT6797_POWER_DOMAIN_MFG_ASYNC 5 +-#define MT6797_POWER_DOMAIN_MFG 6 +-#define MT6797_POWER_DOMAIN_MFG_CORE0 7 +-#define MT6797_POWER_DOMAIN_MFG_CORE1 8 +-#define MT6797_POWER_DOMAIN_MFG_CORE2 9 +-#define MT6797_POWER_DOMAIN_MFG_CORE3 10 +-#define MT6797_POWER_DOMAIN_MJC 11 +- +-#endif /* _DT_BINDINGS_POWER_MT6797_POWER_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/mt7622-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/mt7622-power.h +deleted file mode 100644 +index ffad81ad3d46..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/mt7622-power.h ++++ /dev/null +@@ -1,14 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2017 MediaTek Inc. +- */ +- +-#ifndef _DT_BINDINGS_POWER_MT7622_POWER_H +-#define _DT_BINDINGS_POWER_MT7622_POWER_H +- +-#define MT7622_POWER_DOMAIN_ETHSYS 0 +-#define MT7622_POWER_DOMAIN_HIF0 1 +-#define MT7622_POWER_DOMAIN_HIF1 2 +-#define MT7622_POWER_DOMAIN_WB 3 +- +-#endif /* _DT_BINDINGS_POWER_MT7622_POWER_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/mt7623a-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/mt7623a-power.h +deleted file mode 100644 +index 2544822aa76b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/mt7623a-power.h ++++ /dev/null +@@ -1,10 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef _DT_BINDINGS_POWER_MT7623A_POWER_H +-#define _DT_BINDINGS_POWER_MT7623A_POWER_H +- +-#define MT7623A_POWER_DOMAIN_CONN 0 +-#define MT7623A_POWER_DOMAIN_ETH 1 +-#define MT7623A_POWER_DOMAIN_HIF 2 +-#define MT7623A_POWER_DOMAIN_IFR_MSC 3 +- +-#endif /* _DT_BINDINGS_POWER_MT7623A_POWER_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/mt8167-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/mt8167-power.h +deleted file mode 100644 +index c8ec9983a4bc..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/mt8167-power.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 +- * +- * Copyright (c) 2020 MediaTek Inc. +- */ +- +-#ifndef _DT_BINDINGS_POWER_MT8167_POWER_H +-#define _DT_BINDINGS_POWER_MT8167_POWER_H +- +-#define MT8167_POWER_DOMAIN_MM 0 +-#define MT8167_POWER_DOMAIN_VDEC 1 +-#define MT8167_POWER_DOMAIN_ISP 2 +-#define MT8167_POWER_DOMAIN_CONN 3 +-#define MT8167_POWER_DOMAIN_MFG_ASYNC 4 +-#define MT8167_POWER_DOMAIN_MFG_2D 5 +-#define MT8167_POWER_DOMAIN_MFG 6 +- +-#endif /* _DT_BINDINGS_POWER_MT8167_POWER_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/mt8173-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/mt8173-power.h +deleted file mode 100644 +index ef4a7f944848..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/mt8173-power.h ++++ /dev/null +@@ -1,16 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef _DT_BINDINGS_POWER_MT8173_POWER_H +-#define _DT_BINDINGS_POWER_MT8173_POWER_H +- +-#define MT8173_POWER_DOMAIN_VDEC 0 +-#define MT8173_POWER_DOMAIN_VENC 1 +-#define MT8173_POWER_DOMAIN_ISP 2 +-#define MT8173_POWER_DOMAIN_MM 3 +-#define MT8173_POWER_DOMAIN_VENC_LT 4 +-#define MT8173_POWER_DOMAIN_AUDIO 5 +-#define MT8173_POWER_DOMAIN_USB 6 +-#define MT8173_POWER_DOMAIN_MFG_ASYNC 7 +-#define MT8173_POWER_DOMAIN_MFG_2D 8 +-#define MT8173_POWER_DOMAIN_MFG 9 +- +-#endif /* _DT_BINDINGS_POWER_MT8173_POWER_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/mt8183-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/mt8183-power.h +deleted file mode 100644 +index d1ab387ba8c7..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/mt8183-power.h ++++ /dev/null +@@ -1,26 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2020 MediaTek Inc. +- * Author: Weiyi Lu +- */ +- +-#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H +-#define _DT_BINDINGS_POWER_MT8183_POWER_H +- +-#define MT8183_POWER_DOMAIN_AUDIO 0 +-#define MT8183_POWER_DOMAIN_CONN 1 +-#define MT8183_POWER_DOMAIN_MFG_ASYNC 2 +-#define MT8183_POWER_DOMAIN_MFG 3 +-#define MT8183_POWER_DOMAIN_MFG_CORE0 4 +-#define MT8183_POWER_DOMAIN_MFG_CORE1 5 +-#define MT8183_POWER_DOMAIN_MFG_2D 6 +-#define MT8183_POWER_DOMAIN_DISP 7 +-#define MT8183_POWER_DOMAIN_CAM 8 +-#define MT8183_POWER_DOMAIN_ISP 9 +-#define MT8183_POWER_DOMAIN_VDEC 10 +-#define MT8183_POWER_DOMAIN_VENC 11 +-#define MT8183_POWER_DOMAIN_VPU_TOP 12 +-#define MT8183_POWER_DOMAIN_VPU_CORE0 13 +-#define MT8183_POWER_DOMAIN_VPU_CORE1 14 +- +-#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/mt8192-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/mt8192-power.h +deleted file mode 100644 +index 4eaa53d7270a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/mt8192-power.h ++++ /dev/null +@@ -1,32 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 +- * +- * Copyright (c) 2020 MediaTek Inc. +- * Author: Weiyi Lu +- */ +- +-#ifndef _DT_BINDINGS_POWER_MT8192_POWER_H +-#define _DT_BINDINGS_POWER_MT8192_POWER_H +- +-#define MT8192_POWER_DOMAIN_AUDIO 0 +-#define MT8192_POWER_DOMAIN_CONN 1 +-#define MT8192_POWER_DOMAIN_MFG0 2 +-#define MT8192_POWER_DOMAIN_MFG1 3 +-#define MT8192_POWER_DOMAIN_MFG2 4 +-#define MT8192_POWER_DOMAIN_MFG3 5 +-#define MT8192_POWER_DOMAIN_MFG4 6 +-#define MT8192_POWER_DOMAIN_MFG5 7 +-#define MT8192_POWER_DOMAIN_MFG6 8 +-#define MT8192_POWER_DOMAIN_DISP 9 +-#define MT8192_POWER_DOMAIN_IPE 10 +-#define MT8192_POWER_DOMAIN_ISP 11 +-#define MT8192_POWER_DOMAIN_ISP2 12 +-#define MT8192_POWER_DOMAIN_MDP 13 +-#define MT8192_POWER_DOMAIN_VENC 14 +-#define MT8192_POWER_DOMAIN_VDEC 15 +-#define MT8192_POWER_DOMAIN_VDEC2 16 +-#define MT8192_POWER_DOMAIN_CAM 17 +-#define MT8192_POWER_DOMAIN_CAM_RAWA 18 +-#define MT8192_POWER_DOMAIN_CAM_RAWB 19 +-#define MT8192_POWER_DOMAIN_CAM_RAWC 20 +- +-#endif /* _DT_BINDINGS_POWER_MT8192_POWER_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/owl-s500-powergate.h b/scripts/dtc/include-prefixes/dt-bindings/power/owl-s500-powergate.h +deleted file mode 100644 +index 0a1c451865ea..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/owl-s500-powergate.h ++++ /dev/null +@@ -1,19 +0,0 @@ +-/* +- * Copyright (c) 2017 Andreas Färber +- * +- * SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- */ +-#ifndef DT_BINDINGS_POWER_OWL_S500_POWERGATE_H +-#define DT_BINDINGS_POWER_OWL_S500_POWERGATE_H +- +-#define S500_PD_VDE 0 +-#define S500_PD_VCE_SI 1 +-#define S500_PD_USB2_1 2 +-#define S500_PD_CPU2 3 +-#define S500_PD_CPU3 4 +-#define S500_PD_DMA 5 +-#define S500_PD_DS 6 +-#define S500_PD_USB3 7 +-#define S500_PD_USB2_0 8 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/owl-s700-powergate.h b/scripts/dtc/include-prefixes/dt-bindings/power/owl-s700-powergate.h +deleted file mode 100644 +index 4cf1aefbf09c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/owl-s700-powergate.h ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Actions Semi S700 SPS +- * +- * Copyright (c) 2017 Andreas Färber +- */ +-#ifndef DT_BINDINGS_POWER_OWL_S700_POWERGATE_H +-#define DT_BINDINGS_POWER_OWL_S700_POWERGATE_H +- +-#define S700_PD_VDE 0 +-#define S700_PD_VCE_SI 1 +-#define S700_PD_USB2_1 2 +-#define S700_PD_HDE 3 +-#define S700_PD_DMA 4 +-#define S700_PD_DS 5 +-#define S700_PD_USB3 6 +-#define S700_PD_USB2_0 7 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/owl-s900-powergate.h b/scripts/dtc/include-prefixes/dt-bindings/power/owl-s900-powergate.h +deleted file mode 100644 +index d939bd964657..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/owl-s900-powergate.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */ +-/* +- * Actions Semi S900 SPS +- * +- * Copyright (c) 2018 Linaro Ltd. +- */ +-#ifndef DT_BINDINGS_POWER_OWL_S900_POWERGATE_H +-#define DT_BINDINGS_POWER_OWL_S900_POWERGATE_H +- +-#define S900_PD_GPU_B 0 +-#define S900_PD_VCE 1 +-#define S900_PD_SENSOR 2 +-#define S900_PD_VDE 3 +-#define S900_PD_HDE 4 +-#define S900_PD_USB3 5 +-#define S900_PD_DDR0 6 +-#define S900_PD_DDR1 7 +-#define S900_PD_DE 8 +-#define S900_PD_NAND 9 +-#define S900_PD_USB2_H0 10 +-#define S900_PD_USB2_H1 11 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/px30-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/px30-power.h +deleted file mode 100644 +index 30917a99ad20..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/px30-power.h ++++ /dev/null +@@ -1,27 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_BINDINGS_POWER_PX30_POWER_H__ +-#define __DT_BINDINGS_POWER_PX30_POWER_H__ +- +-/* VD_CORE */ +-#define PX30_PD_A35_0 0 +-#define PX30_PD_A35_1 1 +-#define PX30_PD_A35_2 2 +-#define PX30_PD_A35_3 3 +-#define PX30_PD_SCU 4 +- +-/* VD_LOGIC */ +-#define PX30_PD_USB 5 +-#define PX30_PD_DDR 6 +-#define PX30_PD_SDCARD 7 +-#define PX30_PD_CRYPTO 8 +-#define PX30_PD_GMAC 9 +-#define PX30_PD_MMC_NAND 10 +-#define PX30_PD_VPU 11 +-#define PX30_PD_VO 12 +-#define PX30_PD_VI 13 +-#define PX30_PD_GPU 14 +- +-/* VD_PMU */ +-#define PX30_PD_PMU 15 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/qcom-aoss-qmp.h b/scripts/dtc/include-prefixes/dt-bindings/power/qcom-aoss-qmp.h +deleted file mode 100644 +index ec336d31dee4..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/qcom-aoss-qmp.h ++++ /dev/null +@@ -1,14 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* Copyright (c) 2018, Linaro Ltd. */ +- +-#ifndef __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H +-#define __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H +- +-#define AOSS_QMP_LS_CDSP 0 +-#define AOSS_QMP_LS_LPASS 1 +-#define AOSS_QMP_LS_MODEM 2 +-#define AOSS_QMP_LS_SLPI 3 +-#define AOSS_QMP_LS_SPSS 4 +-#define AOSS_QMP_LS_VENUS 5 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/qcom-rpmpd.h b/scripts/dtc/include-prefixes/dt-bindings/power/qcom-rpmpd.h +deleted file mode 100644 +index 4533dbbf9937..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/qcom-rpmpd.h ++++ /dev/null +@@ -1,219 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ +- +-#ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H +-#define _DT_BINDINGS_POWER_QCOM_RPMPD_H +- +-/* SDM845 Power Domain Indexes */ +-#define SDM845_EBI 0 +-#define SDM845_MX 1 +-#define SDM845_MX_AO 2 +-#define SDM845_CX 3 +-#define SDM845_CX_AO 4 +-#define SDM845_LMX 5 +-#define SDM845_LCX 6 +-#define SDM845_GFX 7 +-#define SDM845_MSS 8 +- +-/* SDX55 Power Domain Indexes */ +-#define SDX55_MSS 0 +-#define SDX55_MX 1 +-#define SDX55_CX 2 +- +-/* SM8150 Power Domain Indexes */ +-#define SM8150_MSS 0 +-#define SM8150_EBI 1 +-#define SM8150_LMX 2 +-#define SM8150_LCX 3 +-#define SM8150_GFX 4 +-#define SM8150_MX 5 +-#define SM8150_MX_AO 6 +-#define SM8150_CX 7 +-#define SM8150_CX_AO 8 +-#define SM8150_MMCX 9 +-#define SM8150_MMCX_AO 10 +- +-/* SM8250 Power Domain Indexes */ +-#define SM8250_CX 0 +-#define SM8250_CX_AO 1 +-#define SM8250_EBI 2 +-#define SM8250_GFX 3 +-#define SM8250_LCX 4 +-#define SM8250_LMX 5 +-#define SM8250_MMCX 6 +-#define SM8250_MMCX_AO 7 +-#define SM8250_MX 8 +-#define SM8250_MX_AO 9 +- +-/* SM8350 Power Domain Indexes */ +-#define SM8350_CX 0 +-#define SM8350_CX_AO 1 +-#define SM8350_EBI 2 +-#define SM8350_GFX 3 +-#define SM8350_LCX 4 +-#define SM8350_LMX 5 +-#define SM8350_MMCX 6 +-#define SM8350_MMCX_AO 7 +-#define SM8350_MX 8 +-#define SM8350_MX_AO 9 +-#define SM8350_MXC 10 +-#define SM8350_MXC_AO 11 +-#define SM8350_MSS 12 +- +-/* SC7180 Power Domain Indexes */ +-#define SC7180_CX 0 +-#define SC7180_CX_AO 1 +-#define SC7180_GFX 2 +-#define SC7180_MX 3 +-#define SC7180_MX_AO 4 +-#define SC7180_LMX 5 +-#define SC7180_LCX 6 +-#define SC7180_MSS 7 +- +-/* SC7280 Power Domain Indexes */ +-#define SC7280_CX 0 +-#define SC7280_CX_AO 1 +-#define SC7280_EBI 2 +-#define SC7280_GFX 3 +-#define SC7280_MX 4 +-#define SC7280_MX_AO 5 +-#define SC7280_LMX 6 +-#define SC7280_LCX 7 +-#define SC7280_MSS 8 +- +-/* SC8180X Power Domain Indexes */ +-#define SC8180X_CX 0 +-#define SC8180X_CX_AO 1 +-#define SC8180X_EBI 2 +-#define SC8180X_GFX 3 +-#define SC8180X_LCX 4 +-#define SC8180X_LMX 5 +-#define SC8180X_MMCX 6 +-#define SC8180X_MMCX_AO 7 +-#define SC8180X_MSS 8 +-#define SC8180X_MX 9 +-#define SC8180X_MX_AO 10 +- +-/* SDM845 Power Domain performance levels */ +-#define RPMH_REGULATOR_LEVEL_RETENTION 16 +-#define RPMH_REGULATOR_LEVEL_MIN_SVS 48 +-#define RPMH_REGULATOR_LEVEL_LOW_SVS 64 +-#define RPMH_REGULATOR_LEVEL_SVS 128 +-#define RPMH_REGULATOR_LEVEL_SVS_L0 144 +-#define RPMH_REGULATOR_LEVEL_SVS_L1 192 +-#define RPMH_REGULATOR_LEVEL_SVS_L2 224 +-#define RPMH_REGULATOR_LEVEL_NOM 256 +-#define RPMH_REGULATOR_LEVEL_NOM_L1 320 +-#define RPMH_REGULATOR_LEVEL_NOM_L2 336 +-#define RPMH_REGULATOR_LEVEL_TURBO 384 +-#define RPMH_REGULATOR_LEVEL_TURBO_L1 416 +- +-/* MDM9607 Power Domains */ +-#define MDM9607_VDDCX 0 +-#define MDM9607_VDDCX_AO 1 +-#define MDM9607_VDDCX_VFL 2 +-#define MDM9607_VDDMX 3 +-#define MDM9607_VDDMX_AO 4 +-#define MDM9607_VDDMX_VFL 5 +- +-/* MSM8939 Power Domains */ +-#define MSM8939_VDDMDCX 0 +-#define MSM8939_VDDMDCX_AO 1 +-#define MSM8939_VDDMDCX_VFC 2 +-#define MSM8939_VDDCX 3 +-#define MSM8939_VDDCX_AO 4 +-#define MSM8939_VDDCX_VFC 5 +-#define MSM8939_VDDMX 6 +-#define MSM8939_VDDMX_AO 7 +- +-/* MSM8916 Power Domain Indexes */ +-#define MSM8916_VDDCX 0 +-#define MSM8916_VDDCX_AO 1 +-#define MSM8916_VDDCX_VFC 2 +-#define MSM8916_VDDMX 3 +-#define MSM8916_VDDMX_AO 4 +- +-/* MSM8976 Power Domain Indexes */ +-#define MSM8976_VDDCX 0 +-#define MSM8976_VDDCX_AO 1 +-#define MSM8976_VDDCX_VFL 2 +-#define MSM8976_VDDMX 3 +-#define MSM8976_VDDMX_AO 4 +-#define MSM8976_VDDMX_VFL 5 +- +-/* MSM8994 Power Domain Indexes */ +-#define MSM8994_VDDCX 0 +-#define MSM8994_VDDCX_AO 1 +-#define MSM8994_VDDCX_VFC 2 +-#define MSM8994_VDDMX 3 +-#define MSM8994_VDDMX_AO 4 +-#define MSM8994_VDDGFX 5 +-#define MSM8994_VDDGFX_VFC 6 +- +-/* MSM8996 Power Domain Indexes */ +-#define MSM8996_VDDCX 0 +-#define MSM8996_VDDCX_AO 1 +-#define MSM8996_VDDCX_VFC 2 +-#define MSM8996_VDDMX 3 +-#define MSM8996_VDDMX_AO 4 +-#define MSM8996_VDDSSCX 5 +-#define MSM8996_VDDSSCX_VFC 6 +- +-/* MSM8998 Power Domain Indexes */ +-#define MSM8998_VDDCX 0 +-#define MSM8998_VDDCX_AO 1 +-#define MSM8998_VDDCX_VFL 2 +-#define MSM8998_VDDMX 3 +-#define MSM8998_VDDMX_AO 4 +-#define MSM8998_VDDMX_VFL 5 +-#define MSM8998_SSCCX 6 +-#define MSM8998_SSCCX_VFL 7 +-#define MSM8998_SSCMX 8 +-#define MSM8998_SSCMX_VFL 9 +- +-/* QCS404 Power Domains */ +-#define QCS404_VDDMX 0 +-#define QCS404_VDDMX_AO 1 +-#define QCS404_VDDMX_VFL 2 +-#define QCS404_LPICX 3 +-#define QCS404_LPICX_VFL 4 +-#define QCS404_LPIMX 5 +-#define QCS404_LPIMX_VFL 6 +- +-/* SDM660 Power Domains */ +-#define SDM660_VDDCX 0 +-#define SDM660_VDDCX_AO 1 +-#define SDM660_VDDCX_VFL 2 +-#define SDM660_VDDMX 3 +-#define SDM660_VDDMX_AO 4 +-#define SDM660_VDDMX_VFL 5 +-#define SDM660_SSCCX 6 +-#define SDM660_SSCCX_VFL 7 +-#define SDM660_SSCMX 8 +-#define SDM660_SSCMX_VFL 9 +- +-/* SM6115 Power Domains */ +-#define SM6115_VDDCX 0 +-#define SM6115_VDDCX_AO 1 +-#define SM6115_VDDCX_VFL 2 +-#define SM6115_VDDMX 3 +-#define SM6115_VDDMX_AO 4 +-#define SM6115_VDDMX_VFL 5 +-#define SM6115_VDD_LPI_CX 6 +-#define SM6115_VDD_LPI_MX 7 +- +-/* RPM SMD Power Domain performance levels */ +-#define RPM_SMD_LEVEL_RETENTION 16 +-#define RPM_SMD_LEVEL_RETENTION_PLUS 32 +-#define RPM_SMD_LEVEL_MIN_SVS 48 +-#define RPM_SMD_LEVEL_LOW_SVS 64 +-#define RPM_SMD_LEVEL_SVS 128 +-#define RPM_SMD_LEVEL_SVS_PLUS 192 +-#define RPM_SMD_LEVEL_NOM 256 +-#define RPM_SMD_LEVEL_NOM_PLUS 320 +-#define RPM_SMD_LEVEL_TURBO 384 +-#define RPM_SMD_LEVEL_TURBO_NO_CPR 416 +-#define RPM_SMD_LEVEL_TURBO_HIGH 448 +-#define RPM_SMD_LEVEL_BINNING 512 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7742-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a7742-sysc.h +deleted file mode 100644 +index 1b1bd3cf95db..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7742-sysc.h ++++ /dev/null +@@ -1,29 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_POWER_R8A7742_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A7742_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A7742_PD_CA15_CPU0 0 +-#define R8A7742_PD_CA15_CPU1 1 +-#define R8A7742_PD_CA15_CPU2 2 +-#define R8A7742_PD_CA15_CPU3 3 +-#define R8A7742_PD_CA7_CPU0 5 +-#define R8A7742_PD_CA7_CPU1 6 +-#define R8A7742_PD_CA7_CPU2 7 +-#define R8A7742_PD_CA7_CPU3 8 +-#define R8A7742_PD_CA15_SCU 12 +-#define R8A7742_PD_RGX 20 +-#define R8A7742_PD_CA7_SCU 21 +- +-/* Always-on power area */ +-#define R8A7742_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A7742_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7743-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a7743-sysc.h +deleted file mode 100644 +index 1b863932da17..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7743-sysc.h ++++ /dev/null +@@ -1,22 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2016 Cogent Embedded Inc. +- */ +-#ifndef __DT_BINDINGS_POWER_R8A7743_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A7743_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A7743_PD_CA15_CPU0 0 +-#define R8A7743_PD_CA15_CPU1 1 +-#define R8A7743_PD_CA15_SCU 12 +-#define R8A7743_PD_SGX 20 +- +-/* Always-on power area */ +-#define R8A7743_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A7743_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7744-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a7744-sysc.h +deleted file mode 100644 +index 8b6529778f98..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7744-sysc.h ++++ /dev/null +@@ -1,24 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_POWER_R8A7744_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A7744_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- * +- * Note that RZ/G1N is identical to RZ/G2M w.r.t. power domains. +- */ +- +-#define R8A7744_PD_CA15_CPU0 0 +-#define R8A7744_PD_CA15_CPU1 1 +-#define R8A7744_PD_CA15_SCU 12 +-#define R8A7744_PD_SGX 20 +- +-/* Always-on power area */ +-#define R8A7744_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A7744_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7745-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a7745-sysc.h +deleted file mode 100644 +index 725ad3504d66..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7745-sysc.h ++++ /dev/null +@@ -1,22 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2016 Cogent Embedded Inc. +- */ +-#ifndef __DT_BINDINGS_POWER_R8A7745_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A7745_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A7745_PD_CA7_CPU0 5 +-#define R8A7745_PD_CA7_CPU1 6 +-#define R8A7745_PD_SGX 20 +-#define R8A7745_PD_CA7_SCU 21 +- +-/* Always-on power area */ +-#define R8A7745_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A7745_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a77470-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a77470-sysc.h +deleted file mode 100644 +index 8bf4db187c31..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a77470-sysc.h ++++ /dev/null +@@ -1,22 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_POWER_R8A77470_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A77470_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A77470_PD_CA7_CPU0 5 +-#define R8A77470_PD_CA7_CPU1 6 +-#define R8A77470_PD_SGX 20 +-#define R8A77470_PD_CA7_SCU 21 +- +-/* Always-on power area */ +-#define R8A77470_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A77470_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a774a1-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a774a1-sysc.h +deleted file mode 100644 +index 580f431cd32e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a774a1-sysc.h ++++ /dev/null +@@ -1,31 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A774A1_PD_CA57_CPU0 0 +-#define R8A774A1_PD_CA57_CPU1 1 +-#define R8A774A1_PD_CA53_CPU0 5 +-#define R8A774A1_PD_CA53_CPU1 6 +-#define R8A774A1_PD_CA53_CPU2 7 +-#define R8A774A1_PD_CA53_CPU3 8 +-#define R8A774A1_PD_CA57_SCU 12 +-#define R8A774A1_PD_A3VC 14 +-#define R8A774A1_PD_3DG_A 17 +-#define R8A774A1_PD_3DG_B 18 +-#define R8A774A1_PD_CA53_SCU 21 +-#define R8A774A1_PD_A2VC0 25 +-#define R8A774A1_PD_A2VC1 26 +- +-/* Always-on power area */ +-#define R8A774A1_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a774b1-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a774b1-sysc.h +deleted file mode 100644 +index 373736402f04..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a774b1-sysc.h ++++ /dev/null +@@ -1,26 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 +- * +- * Copyright (C) 2019 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A774B1_PD_CA57_CPU0 0 +-#define R8A774B1_PD_CA57_CPU1 1 +-#define R8A774B1_PD_A3VP 9 +-#define R8A774B1_PD_CA57_SCU 12 +-#define R8A774B1_PD_A3VC 14 +-#define R8A774B1_PD_3DG_A 17 +-#define R8A774B1_PD_3DG_B 18 +-#define R8A774B1_PD_A2VC1 26 +- +-/* Always-on power area */ +-#define R8A774B1_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a774c0-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a774c0-sysc.h +deleted file mode 100644 +index 9922d4c6f87d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a774c0-sysc.h ++++ /dev/null +@@ -1,25 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A774C0_PD_CA53_CPU0 5 +-#define R8A774C0_PD_CA53_CPU1 6 +-#define R8A774C0_PD_A3VC 14 +-#define R8A774C0_PD_3DG_A 17 +-#define R8A774C0_PD_3DG_B 18 +-#define R8A774C0_PD_CA53_SCU 21 +-#define R8A774C0_PD_A2VC1 26 +- +-/* Always-on power area */ +-#define R8A774C0_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a774e1-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a774e1-sysc.h +deleted file mode 100644 +index 7edb8161db36..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a774e1-sysc.h ++++ /dev/null +@@ -1,36 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 +- * +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A774E1_PD_CA57_CPU0 0 +-#define R8A774E1_PD_CA57_CPU1 1 +-#define R8A774E1_PD_CA57_CPU2 2 +-#define R8A774E1_PD_CA57_CPU3 3 +-#define R8A774E1_PD_CA53_CPU0 5 +-#define R8A774E1_PD_CA53_CPU1 6 +-#define R8A774E1_PD_CA53_CPU2 7 +-#define R8A774E1_PD_CA53_CPU3 8 +-#define R8A774E1_PD_A3VP 9 +-#define R8A774E1_PD_CA57_SCU 12 +-#define R8A774E1_PD_A3VC 14 +-#define R8A774E1_PD_3DG_A 17 +-#define R8A774E1_PD_3DG_B 18 +-#define R8A774E1_PD_3DG_C 19 +-#define R8A774E1_PD_3DG_D 20 +-#define R8A774E1_PD_CA53_SCU 21 +-#define R8A774E1_PD_3DG_E 22 +-#define R8A774E1_PD_A2VC1 26 +- +-/* Always-on power area */ +-#define R8A774E1_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7779-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a7779-sysc.h +deleted file mode 100644 +index c4f528b6cc1e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7779-sysc.h ++++ /dev/null +@@ -1,24 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2016 Glider bvba +- */ +-#ifndef __DT_BINDINGS_POWER_R8A7779_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A7779_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A7779_PD_ARM1 1 +-#define R8A7779_PD_ARM2 2 +-#define R8A7779_PD_ARM3 3 +-#define R8A7779_PD_SGX 20 +-#define R8A7779_PD_VDP 21 +-#define R8A7779_PD_IMP 24 +- +-/* Always-on power area */ +-#define R8A7779_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A7779_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7790-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a7790-sysc.h +deleted file mode 100644 +index bcb490570606..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7790-sysc.h ++++ /dev/null +@@ -1,31 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2016 Glider bvba +- */ +-#ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A7790_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A7790_PD_CA15_CPU0 0 +-#define R8A7790_PD_CA15_CPU1 1 +-#define R8A7790_PD_CA15_CPU2 2 +-#define R8A7790_PD_CA15_CPU3 3 +-#define R8A7790_PD_CA7_CPU0 5 +-#define R8A7790_PD_CA7_CPU1 6 +-#define R8A7790_PD_CA7_CPU2 7 +-#define R8A7790_PD_CA7_CPU3 8 +-#define R8A7790_PD_CA15_SCU 12 +-#define R8A7790_PD_SH_4A 16 +-#define R8A7790_PD_RGX 20 +-#define R8A7790_PD_CA7_SCU 21 +-#define R8A7790_PD_IMP 24 +- +-/* Always-on power area */ +-#define R8A7790_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A7790_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7791-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a7791-sysc.h +deleted file mode 100644 +index 1d20fae42420..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7791-sysc.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2016 Glider bvba +- */ +-#ifndef __DT_BINDINGS_POWER_R8A7791_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A7791_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A7791_PD_CA15_CPU0 0 +-#define R8A7791_PD_CA15_CPU1 1 +-#define R8A7791_PD_CA15_SCU 12 +-#define R8A7791_PD_SH_4A 16 +-#define R8A7791_PD_SGX 20 +- +-/* Always-on power area */ +-#define R8A7791_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A7791_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7792-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a7792-sysc.h +deleted file mode 100644 +index dd3a4667ca19..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7792-sysc.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2016 Cogent Embedded Inc. +- */ +-#ifndef __DT_BINDINGS_POWER_R8A7792_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A7792_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A7792_PD_CA15_CPU0 0 +-#define R8A7792_PD_CA15_CPU1 1 +-#define R8A7792_PD_CA15_SCU 12 +-#define R8A7792_PD_SGX 20 +-#define R8A7792_PD_IMP 24 +- +-/* Always-on power area */ +-#define R8A7792_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A7792_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7793-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a7793-sysc.h +deleted file mode 100644 +index 056998c635a9..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7793-sysc.h ++++ /dev/null +@@ -1,25 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2016 Glider bvba +- */ +-#ifndef __DT_BINDINGS_POWER_R8A7793_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A7793_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- * +- * Note that R-Car M2-N is identical to R-Car M2-W w.r.t. power domains. +- */ +- +-#define R8A7793_PD_CA15_CPU0 0 +-#define R8A7793_PD_CA15_CPU1 1 +-#define R8A7793_PD_CA15_SCU 12 +-#define R8A7793_PD_SH_4A 16 +-#define R8A7793_PD_SGX 20 +- +-/* Always-on power area */ +-#define R8A7793_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A7793_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7794-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a7794-sysc.h +deleted file mode 100644 +index 4d6c708e6f32..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7794-sysc.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2016 Glider bvba +- */ +-#ifndef __DT_BINDINGS_POWER_R8A7794_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A7794_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A7794_PD_CA7_CPU0 5 +-#define R8A7794_PD_CA7_CPU1 6 +-#define R8A7794_PD_SH_4A 16 +-#define R8A7794_PD_SGX 20 +-#define R8A7794_PD_CA7_SCU 21 +- +-/* Always-on power area */ +-#define R8A7794_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A7794_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7795-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a7795-sysc.h +deleted file mode 100644 +index eea6ad69f0b0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7795-sysc.h ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2016 Glider bvba +- */ +-#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A7795_PD_CA57_CPU0 0 +-#define R8A7795_PD_CA57_CPU1 1 +-#define R8A7795_PD_CA57_CPU2 2 +-#define R8A7795_PD_CA57_CPU3 3 +-#define R8A7795_PD_CA53_CPU0 5 +-#define R8A7795_PD_CA53_CPU1 6 +-#define R8A7795_PD_CA53_CPU2 7 +-#define R8A7795_PD_CA53_CPU3 8 +-#define R8A7795_PD_A3VP 9 +-#define R8A7795_PD_CA57_SCU 12 +-#define R8A7795_PD_CR7 13 +-#define R8A7795_PD_A3VC 14 +-#define R8A7795_PD_3DG_A 17 +-#define R8A7795_PD_3DG_B 18 +-#define R8A7795_PD_3DG_C 19 +-#define R8A7795_PD_3DG_D 20 +-#define R8A7795_PD_CA53_SCU 21 +-#define R8A7795_PD_3DG_E 22 +-#define R8A7795_PD_A3IR 24 +-#define R8A7795_PD_A2VC0 25 /* ES1.x only */ +-#define R8A7795_PD_A2VC1 26 +- +-/* Always-on power area */ +-#define R8A7795_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7796-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a7796-sysc.h +deleted file mode 100644 +index 7e6fc06ebff2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a7796-sysc.h ++++ /dev/null +@@ -1,33 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2016 Glider bvba +- */ +-#ifndef __DT_BINDINGS_POWER_R8A7796_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A7796_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A7796_PD_CA57_CPU0 0 +-#define R8A7796_PD_CA57_CPU1 1 +-#define R8A7796_PD_CA53_CPU0 5 +-#define R8A7796_PD_CA53_CPU1 6 +-#define R8A7796_PD_CA53_CPU2 7 +-#define R8A7796_PD_CA53_CPU3 8 +-#define R8A7796_PD_CA57_SCU 12 +-#define R8A7796_PD_CR7 13 +-#define R8A7796_PD_A3VC 14 +-#define R8A7796_PD_3DG_A 17 +-#define R8A7796_PD_3DG_B 18 +-#define R8A7796_PD_CA53_SCU 21 +-#define R8A7796_PD_A3IR 24 +-#define R8A7796_PD_A2VC0 25 +-#define R8A7796_PD_A2VC1 26 +- +-/* Always-on power area */ +-#define R8A7796_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A7796_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a77961-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a77961-sysc.h +deleted file mode 100644 +index 7a3800996f7c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a77961-sysc.h ++++ /dev/null +@@ -1,32 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2019 Glider bvba +- */ +-#ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A77961_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A77961_PD_CA57_CPU0 0 +-#define R8A77961_PD_CA57_CPU1 1 +-#define R8A77961_PD_CA53_CPU0 5 +-#define R8A77961_PD_CA53_CPU1 6 +-#define R8A77961_PD_CA53_CPU2 7 +-#define R8A77961_PD_CA53_CPU3 8 +-#define R8A77961_PD_CA57_SCU 12 +-#define R8A77961_PD_CR7 13 +-#define R8A77961_PD_A3VC 14 +-#define R8A77961_PD_3DG_A 17 +-#define R8A77961_PD_3DG_B 18 +-#define R8A77961_PD_CA53_SCU 21 +-#define R8A77961_PD_A3IR 24 +-#define R8A77961_PD_A2VC1 26 +- +-/* Always-on power area */ +-#define R8A77961_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a77965-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a77965-sysc.h +deleted file mode 100644 +index de82d8a15ea1..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a77965-sysc.h ++++ /dev/null +@@ -1,29 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2018 Jacopo Mondi +- * Copyright (C) 2016 Glider bvba +- */ +- +-#ifndef __DT_BINDINGS_POWER_R8A77965_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A77965_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A77965_PD_CA57_CPU0 0 +-#define R8A77965_PD_CA57_CPU1 1 +-#define R8A77965_PD_A3VP 9 +-#define R8A77965_PD_CA57_SCU 12 +-#define R8A77965_PD_CR7 13 +-#define R8A77965_PD_A3VC 14 +-#define R8A77965_PD_3DG_A 17 +-#define R8A77965_PD_3DG_B 18 +-#define R8A77965_PD_A2VC1 26 +- +-/* Always-on power area */ +-#define R8A77965_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A77965_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a77970-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a77970-sysc.h +deleted file mode 100644 +index 9dcdbd5a9304..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a77970-sysc.h ++++ /dev/null +@@ -1,28 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2017 Cogent Embedded Inc. +- */ +-#ifndef __DT_BINDINGS_POWER_R8A77970_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A77970_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A77970_PD_CA53_CPU0 5 +-#define R8A77970_PD_CA53_CPU1 6 +-#define R8A77970_PD_CA53_SCU 21 +-#define R8A77970_PD_A2IR0 23 +-#define R8A77970_PD_A3IR 24 +-#define R8A77970_PD_A2IR1 27 +-#define R8A77970_PD_A2DP 28 +-#define R8A77970_PD_A2CN 29 +-#define R8A77970_PD_A2SC0 30 +-#define R8A77970_PD_A2SC1 31 +- +-/* Always-on power area */ +-#define R8A77970_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A77970_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a77980-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a77980-sysc.h +deleted file mode 100644 +index e12c8587b87e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a77980-sysc.h ++++ /dev/null +@@ -1,43 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 +- * +- * Copyright (C) 2018 Renesas Electronics Corp. +- * Copyright (C) 2018 Cogent Embedded, Inc. +- */ +-#ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A77980_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A77980_PD_A2SC2 0 +-#define R8A77980_PD_A2SC3 1 +-#define R8A77980_PD_A2SC4 2 +-#define R8A77980_PD_A2DP0 3 +-#define R8A77980_PD_A2DP1 4 +-#define R8A77980_PD_CA53_CPU0 5 +-#define R8A77980_PD_CA53_CPU1 6 +-#define R8A77980_PD_CA53_CPU2 7 +-#define R8A77980_PD_CA53_CPU3 8 +-#define R8A77980_PD_A2CN 10 +-#define R8A77980_PD_A3VIP0 11 +-#define R8A77980_PD_A2IR5 12 +-#define R8A77980_PD_CR7 13 +-#define R8A77980_PD_A2IR4 15 +-#define R8A77980_PD_CA53_SCU 21 +-#define R8A77980_PD_A2IR0 23 +-#define R8A77980_PD_A3IR 24 +-#define R8A77980_PD_A3VIP1 25 +-#define R8A77980_PD_A3VIP2 26 +-#define R8A77980_PD_A2IR1 27 +-#define R8A77980_PD_A2IR2 28 +-#define R8A77980_PD_A2IR3 29 +-#define R8A77980_PD_A2SC0 30 +-#define R8A77980_PD_A2SC1 31 +- +-/* Always-on power area */ +-#define R8A77980_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a77990-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a77990-sysc.h +deleted file mode 100644 +index 944d85beec15..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a77990-sysc.h ++++ /dev/null +@@ -1,26 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2018 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_POWER_R8A77990_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A77990_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A77990_PD_CA53_CPU0 5 +-#define R8A77990_PD_CA53_CPU1 6 +-#define R8A77990_PD_CR7 13 +-#define R8A77990_PD_A3VC 14 +-#define R8A77990_PD_3DG_A 17 +-#define R8A77990_PD_3DG_B 18 +-#define R8A77990_PD_CA53_SCU 21 +-#define R8A77990_PD_A2VC1 26 +- +-/* Always-on power area */ +-#define R8A77990_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A77990_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a77995-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a77995-sysc.h +deleted file mode 100644 +index f2b35502f2be..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a77995-sysc.h ++++ /dev/null +@@ -1,20 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2017 Glider bvba +- */ +-#ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A77995_SYSC_H__ +- +-/* +- * These power domain indices match the numbers of the interrupt bits +- * representing the power areas in the various Interrupt Registers +- * (e.g. SYSCISR, Interrupt Status Register) +- */ +- +-#define R8A77995_PD_CA53_CPU0 5 +-#define R8A77995_PD_CA53_SCU 21 +- +-/* Always-on power area */ +-#define R8A77995_PD_ALWAYS_ON 32 +- +-#endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/r8a779a0-sysc.h b/scripts/dtc/include-prefixes/dt-bindings/power/r8a779a0-sysc.h +deleted file mode 100644 +index 57929e459a67..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/r8a779a0-sysc.h ++++ /dev/null +@@ -1,59 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2020 Renesas Electronics Corp. +- */ +-#ifndef __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ +-#define __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ +- +-/* +- * These power domain indices match the Power Domain Register Numbers (PDR) +- */ +- +-#define R8A779A0_PD_A1E0D0C0 0 +-#define R8A779A0_PD_A1E0D0C1 1 +-#define R8A779A0_PD_A1E0D1C0 2 +-#define R8A779A0_PD_A1E0D1C1 3 +-#define R8A779A0_PD_A1E1D0C0 4 +-#define R8A779A0_PD_A1E1D0C1 5 +-#define R8A779A0_PD_A1E1D1C0 6 +-#define R8A779A0_PD_A1E1D1C1 7 +-#define R8A779A0_PD_A2E0D0 16 +-#define R8A779A0_PD_A2E0D1 17 +-#define R8A779A0_PD_A2E1D0 18 +-#define R8A779A0_PD_A2E1D1 19 +-#define R8A779A0_PD_A3E0 20 +-#define R8A779A0_PD_A3E1 21 +-#define R8A779A0_PD_3DG_A 24 +-#define R8A779A0_PD_3DG_B 25 +-#define R8A779A0_PD_A1CNN2 32 +-#define R8A779A0_PD_A1DSP0 33 +-#define R8A779A0_PD_A2IMP01 34 +-#define R8A779A0_PD_A2DP0 35 +-#define R8A779A0_PD_A2CV0 36 +-#define R8A779A0_PD_A2CV1 37 +-#define R8A779A0_PD_A2CV4 38 +-#define R8A779A0_PD_A2CV6 39 +-#define R8A779A0_PD_A2CN2 40 +-#define R8A779A0_PD_A1CNN0 41 +-#define R8A779A0_PD_A2CN0 42 +-#define R8A779A0_PD_A3IR 43 +-#define R8A779A0_PD_A1CNN1 44 +-#define R8A779A0_PD_A1DSP1 45 +-#define R8A779A0_PD_A2IMP23 46 +-#define R8A779A0_PD_A2DP1 47 +-#define R8A779A0_PD_A2CV2 48 +-#define R8A779A0_PD_A2CV3 49 +-#define R8A779A0_PD_A2CV5 50 +-#define R8A779A0_PD_A2CV7 51 +-#define R8A779A0_PD_A2CN1 52 +-#define R8A779A0_PD_A3VIP0 56 +-#define R8A779A0_PD_A3VIP1 57 +-#define R8A779A0_PD_A3VIP2 58 +-#define R8A779A0_PD_A3VIP3 59 +-#define R8A779A0_PD_A3ISP01 60 +-#define R8A779A0_PD_A3ISP23 61 +- +-/* Always-on power area */ +-#define R8A779A0_PD_ALWAYS_ON 64 +- +-#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/raspberrypi-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/raspberrypi-power.h +deleted file mode 100644 +index 3575f9f4b0bd..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/raspberrypi-power.h ++++ /dev/null +@@ -1,38 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright © 2015 Broadcom +- */ +- +-#ifndef _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H +-#define _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H +- +-/* These power domain indices are the firmware interface's indices +- * minus one. +- */ +-#define RPI_POWER_DOMAIN_I2C0 0 +-#define RPI_POWER_DOMAIN_I2C1 1 +-#define RPI_POWER_DOMAIN_I2C2 2 +-#define RPI_POWER_DOMAIN_VIDEO_SCALER 3 +-#define RPI_POWER_DOMAIN_VPU1 4 +-#define RPI_POWER_DOMAIN_HDMI 5 +-#define RPI_POWER_DOMAIN_USB 6 +-#define RPI_POWER_DOMAIN_VEC 7 +-#define RPI_POWER_DOMAIN_JPEG 8 +-#define RPI_POWER_DOMAIN_H264 9 +-#define RPI_POWER_DOMAIN_V3D 10 +-#define RPI_POWER_DOMAIN_ISP 11 +-#define RPI_POWER_DOMAIN_UNICAM0 12 +-#define RPI_POWER_DOMAIN_UNICAM1 13 +-#define RPI_POWER_DOMAIN_CCP2RX 14 +-#define RPI_POWER_DOMAIN_CSI2 15 +-#define RPI_POWER_DOMAIN_CPI 16 +-#define RPI_POWER_DOMAIN_DSI0 17 +-#define RPI_POWER_DOMAIN_DSI1 18 +-#define RPI_POWER_DOMAIN_TRANSPOSER 19 +-#define RPI_POWER_DOMAIN_CCP2TX 20 +-#define RPI_POWER_DOMAIN_CDP 21 +-#define RPI_POWER_DOMAIN_ARM 22 +- +-#define RPI_POWER_DOMAIN_COUNT 23 +- +-#endif /* _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/rk3036-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/rk3036-power.h +deleted file mode 100644 +index 0bc6b5d5075e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/rk3036-power.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_BINDINGS_POWER_RK3036_POWER_H__ +-#define __DT_BINDINGS_POWER_RK3036_POWER_H__ +- +-#define RK3036_PD_MSCH 0 +-#define RK3036_PD_CORE 1 +-#define RK3036_PD_PERI 2 +-#define RK3036_PD_VIO 3 +-#define RK3036_PD_VPU 4 +-#define RK3036_PD_GPU 5 +-#define RK3036_PD_SYS 6 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/rk3066-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/rk3066-power.h +deleted file mode 100644 +index acf9f310ac53..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/rk3066-power.h ++++ /dev/null +@@ -1,22 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_BINDINGS_POWER_RK3066_POWER_H__ +-#define __DT_BINDINGS_POWER_RK3066_POWER_H__ +- +-/* VD_CORE */ +-#define RK3066_PD_A9_0 0 +-#define RK3066_PD_A9_1 1 +-#define RK3066_PD_DBG 4 +-#define RK3066_PD_SCU 5 +- +-/* VD_LOGIC */ +-#define RK3066_PD_VIDEO 6 +-#define RK3066_PD_VIO 7 +-#define RK3066_PD_GPU 8 +-#define RK3066_PD_PERI 9 +-#define RK3066_PD_CPU 10 +-#define RK3066_PD_ALIVE 11 +- +-/* VD_PMU */ +-#define RK3066_PD_RTC 12 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/rk3128-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/rk3128-power.h +deleted file mode 100644 +index c051dc3108db..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/rk3128-power.h ++++ /dev/null +@@ -1,14 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_BINDINGS_POWER_RK3128_POWER_H__ +-#define __DT_BINDINGS_POWER_RK3128_POWER_H__ +- +-/* VD_CORE */ +-#define RK3128_PD_CORE 0 +- +-/* VD_LOGIC */ +-#define RK3128_PD_VIO 1 +-#define RK3128_PD_VIDEO 2 +-#define RK3128_PD_GPU 3 +-#define RK3128_PD_MSCH 4 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/rk3188-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/rk3188-power.h +deleted file mode 100644 +index 93d23dfba33f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/rk3188-power.h ++++ /dev/null +@@ -1,24 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_BINDINGS_POWER_RK3188_POWER_H__ +-#define __DT_BINDINGS_POWER_RK3188_POWER_H__ +- +-/* VD_CORE */ +-#define RK3188_PD_A9_0 0 +-#define RK3188_PD_A9_1 1 +-#define RK3188_PD_A9_2 2 +-#define RK3188_PD_A9_3 3 +-#define RK3188_PD_DBG 4 +-#define RK3188_PD_SCU 5 +- +-/* VD_LOGIC */ +-#define RK3188_PD_VIDEO 6 +-#define RK3188_PD_VIO 7 +-#define RK3188_PD_GPU 8 +-#define RK3188_PD_PERI 9 +-#define RK3188_PD_CPU 10 +-#define RK3188_PD_ALIVE 11 +- +-/* VD_PMU */ +-#define RK3188_PD_RTC 12 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/rk3228-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/rk3228-power.h +deleted file mode 100644 +index 6a8dc1bf76ce..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/rk3228-power.h ++++ /dev/null +@@ -1,21 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_BINDINGS_POWER_RK3228_POWER_H__ +-#define __DT_BINDINGS_POWER_RK3228_POWER_H__ +- +-/** +- * RK3228 idle id Summary. +- */ +- +-#define RK3228_PD_CORE 0 +-#define RK3228_PD_MSCH 1 +-#define RK3228_PD_BUS 2 +-#define RK3228_PD_SYS 3 +-#define RK3228_PD_VIO 4 +-#define RK3228_PD_VOP 5 +-#define RK3228_PD_VPU 6 +-#define RK3228_PD_RKVDEC 7 +-#define RK3228_PD_GPU 8 +-#define RK3228_PD_PERI 9 +-#define RK3228_PD_GMAC 10 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/rk3288-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/rk3288-power.h +deleted file mode 100644 +index f710b56ccd81..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/rk3288-power.h ++++ /dev/null +@@ -1,32 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_BINDINGS_POWER_RK3288_POWER_H__ +-#define __DT_BINDINGS_POWER_RK3288_POWER_H__ +- +-/** +- * RK3288 Power Domain and Voltage Domain Summary. +- */ +- +-/* VD_CORE */ +-#define RK3288_PD_A17_0 0 +-#define RK3288_PD_A17_1 1 +-#define RK3288_PD_A17_2 2 +-#define RK3288_PD_A17_3 3 +-#define RK3288_PD_SCU 4 +-#define RK3288_PD_DEBUG 5 +-#define RK3288_PD_MEM 6 +- +-/* VD_LOGIC */ +-#define RK3288_PD_BUS 7 +-#define RK3288_PD_PERI 8 +-#define RK3288_PD_VIO 9 +-#define RK3288_PD_ALIVE 10 +-#define RK3288_PD_HEVC 11 +-#define RK3288_PD_VIDEO 12 +- +-/* VD_GPU */ +-#define RK3288_PD_GPU 13 +- +-/* VD_PMU */ +-#define RK3288_PD_PMU 14 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/rk3328-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/rk3328-power.h +deleted file mode 100644 +index 02e3d7fc1cce..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/rk3328-power.h ++++ /dev/null +@@ -1,19 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_BINDINGS_POWER_RK3328_POWER_H__ +-#define __DT_BINDINGS_POWER_RK3328_POWER_H__ +- +-/** +- * RK3328 idle id Summary. +- */ +-#define RK3328_PD_CORE 0 +-#define RK3328_PD_GPU 1 +-#define RK3328_PD_BUS 2 +-#define RK3328_PD_MSCH 3 +-#define RK3328_PD_PERI 4 +-#define RK3328_PD_VIDEO 5 +-#define RK3328_PD_HEVC 6 +-#define RK3328_PD_SYS 7 +-#define RK3328_PD_VPU 8 +-#define RK3328_PD_VIO 9 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/rk3366-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/rk3366-power.h +deleted file mode 100644 +index 223a3dce049a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/rk3366-power.h ++++ /dev/null +@@ -1,24 +0,0 @@ +-#ifndef __DT_BINDINGS_POWER_RK3366_POWER_H__ +-#define __DT_BINDINGS_POWER_RK3366_POWER_H__ +- +-/* VD_CORE */ +-#define RK3366_PD_A53_0 0 +-#define RK3366_PD_A53_1 1 +-#define RK3366_PD_A53_2 2 +-#define RK3366_PD_A53_3 3 +- +-/* VD_LOGIC */ +-#define RK3366_PD_BUS 4 +-#define RK3366_PD_PERI 5 +-#define RK3366_PD_VIO 6 +-#define RK3366_PD_VIDEO 7 +-#define RK3366_PD_RKVDEC 8 +-#define RK3366_PD_WIFIBT 9 +-#define RK3366_PD_VPU 10 +-#define RK3366_PD_GPU 11 +-#define RK3366_PD_ALIVE 12 +- +-/* VD_PMU */ +-#define RK3366_PD_PMU 13 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/rk3368-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/rk3368-power.h +deleted file mode 100644 +index 5e602dbd64ec..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/rk3368-power.h ++++ /dev/null +@@ -1,29 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_BINDINGS_POWER_RK3368_POWER_H__ +-#define __DT_BINDINGS_POWER_RK3368_POWER_H__ +- +-/* VD_CORE */ +-#define RK3368_PD_A53_L0 0 +-#define RK3368_PD_A53_L1 1 +-#define RK3368_PD_A53_L2 2 +-#define RK3368_PD_A53_L3 3 +-#define RK3368_PD_SCU_L 4 +-#define RK3368_PD_A53_B0 5 +-#define RK3368_PD_A53_B1 6 +-#define RK3368_PD_A53_B2 7 +-#define RK3368_PD_A53_B3 8 +-#define RK3368_PD_SCU_B 9 +- +-/* VD_LOGIC */ +-#define RK3368_PD_BUS 10 +-#define RK3368_PD_PERI 11 +-#define RK3368_PD_VIO 12 +-#define RK3368_PD_ALIVE 13 +-#define RK3368_PD_VIDEO 14 +-#define RK3368_PD_GPU_0 15 +-#define RK3368_PD_GPU_1 16 +- +-/* VD_PMU */ +-#define RK3368_PD_PMU 17 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/rk3399-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/rk3399-power.h +deleted file mode 100644 +index aedd8b180fe4..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/rk3399-power.h ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__ +-#define __DT_BINDINGS_POWER_RK3399_POWER_H__ +- +-/* VD_CORE_L */ +-#define RK3399_PD_A53_L0 0 +-#define RK3399_PD_A53_L1 1 +-#define RK3399_PD_A53_L2 2 +-#define RK3399_PD_A53_L3 3 +-#define RK3399_PD_SCU_L 4 +- +-/* VD_CORE_B */ +-#define RK3399_PD_A72_B0 5 +-#define RK3399_PD_A72_B1 6 +-#define RK3399_PD_SCU_B 7 +- +-/* VD_LOGIC */ +-#define RK3399_PD_TCPD0 8 +-#define RK3399_PD_TCPD1 9 +-#define RK3399_PD_CCI 10 +-#define RK3399_PD_CCI0 11 +-#define RK3399_PD_CCI1 12 +-#define RK3399_PD_PERILP 13 +-#define RK3399_PD_PERIHP 14 +-#define RK3399_PD_VIO 15 +-#define RK3399_PD_VO 16 +-#define RK3399_PD_VOPB 17 +-#define RK3399_PD_VOPL 18 +-#define RK3399_PD_ISP0 19 +-#define RK3399_PD_ISP1 20 +-#define RK3399_PD_HDCP 21 +-#define RK3399_PD_GMAC 22 +-#define RK3399_PD_EMMC 23 +-#define RK3399_PD_USB3 24 +-#define RK3399_PD_EDP 25 +-#define RK3399_PD_GIC 26 +-#define RK3399_PD_SD 27 +-#define RK3399_PD_SDIOAUDIO 28 +-#define RK3399_PD_ALIVE 29 +- +-/* VD_CENTER */ +-#define RK3399_PD_CENTER 30 +-#define RK3399_PD_VCODEC 31 +-#define RK3399_PD_VDU 32 +-#define RK3399_PD_RGA 33 +-#define RK3399_PD_IEP 34 +- +-/* VD_GPU */ +-#define RK3399_PD_GPU 35 +- +-/* VD_PMU */ +-#define RK3399_PD_PMU 36 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/rk3568-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/rk3568-power.h +deleted file mode 100644 +index 6cc1af1a9d26..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/rk3568-power.h ++++ /dev/null +@@ -1,32 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ +-#define __DT_BINDINGS_POWER_RK3568_POWER_H__ +- +-/* VD_CORE */ +-#define RK3568_PD_CPU_0 0 +-#define RK3568_PD_CPU_1 1 +-#define RK3568_PD_CPU_2 2 +-#define RK3568_PD_CPU_3 3 +-#define RK3568_PD_CORE_ALIVE 4 +- +-/* VD_PMU */ +-#define RK3568_PD_PMU 5 +- +-/* VD_NPU */ +-#define RK3568_PD_NPU 6 +- +-/* VD_GPU */ +-#define RK3568_PD_GPU 7 +- +-/* VD_LOGIC */ +-#define RK3568_PD_VI 8 +-#define RK3568_PD_VO 9 +-#define RK3568_PD_RGA 10 +-#define RK3568_PD_VPU 11 +-#define RK3568_PD_CENTER 12 +-#define RK3568_PD_RKVDEC 13 +-#define RK3568_PD_RKVENC 14 +-#define RK3568_PD_PIPE 15 +-#define RK3568_PD_LOGIC_ALIVE 16 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/summit,smb347-charger.h b/scripts/dtc/include-prefixes/dt-bindings/power/summit,smb347-charger.h +deleted file mode 100644 +index 3205699b5e41..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/summit,smb347-charger.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-or-later or MIT) */ +-/* +- * Author: David Heidelberg +- */ +- +-#ifndef _DT_BINDINGS_SMB347_CHARGER_H +-#define _DT_BINDINGS_SMB347_CHARGER_H +- +-/* Charging compensation method */ +-#define SMB3XX_SOFT_TEMP_COMPENSATE_NONE 0 +-#define SMB3XX_SOFT_TEMP_COMPENSATE_CURRENT 1 +-#define SMB3XX_SOFT_TEMP_COMPENSATE_VOLTAGE 2 +- +-/* Charging enable control */ +-#define SMB3XX_CHG_ENABLE_SW 0 +-#define SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW 1 +-#define SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH 2 +- +-/* Polarity of INOK signal */ +-#define SMB3XX_SYSOK_INOK_ACTIVE_LOW 0 +-#define SMB3XX_SYSOK_INOK_ACTIVE_HIGH 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/tegra186-powergate.h b/scripts/dtc/include-prefixes/dt-bindings/power/tegra186-powergate.h +deleted file mode 100644 +index 31fd3f90018d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/tegra186-powergate.h ++++ /dev/null +@@ -1,28 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H +-#define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H +- +-#define TEGRA186_POWER_DOMAIN_AUD 0 +-#define TEGRA186_POWER_DOMAIN_DFD 1 +-#define TEGRA186_POWER_DOMAIN_DISP 2 +-#define TEGRA186_POWER_DOMAIN_DISPB 3 +-#define TEGRA186_POWER_DOMAIN_DISPC 4 +-#define TEGRA186_POWER_DOMAIN_ISPA 5 +-#define TEGRA186_POWER_DOMAIN_NVDEC 6 +-#define TEGRA186_POWER_DOMAIN_NVJPG 7 +-#define TEGRA186_POWER_DOMAIN_MPE 8 +-#define TEGRA186_POWER_DOMAIN_PCX 9 +-#define TEGRA186_POWER_DOMAIN_SAX 10 +-#define TEGRA186_POWER_DOMAIN_VE 11 +-#define TEGRA186_POWER_DOMAIN_VIC 12 +-#define TEGRA186_POWER_DOMAIN_XUSBA 13 +-#define TEGRA186_POWER_DOMAIN_XUSBB 14 +-#define TEGRA186_POWER_DOMAIN_XUSBC 15 +-#define TEGRA186_POWER_DOMAIN_GPU 43 +-#define TEGRA186_POWER_DOMAIN_MAX 44 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/tegra194-powergate.h b/scripts/dtc/include-prefixes/dt-bindings/power/tegra194-powergate.h +deleted file mode 100644 +index 82253742a493..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/tegra194-powergate.h ++++ /dev/null +@@ -1,35 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ +- +-#ifndef __ABI_MACH_T194_POWERGATE_T194_H_ +-#define __ABI_MACH_T194_POWERGATE_T194_H_ +- +-#define TEGRA194_POWER_DOMAIN_AUD 1 +-#define TEGRA194_POWER_DOMAIN_DISP 2 +-#define TEGRA194_POWER_DOMAIN_DISPB 3 +-#define TEGRA194_POWER_DOMAIN_DISPC 4 +-#define TEGRA194_POWER_DOMAIN_ISPA 5 +-#define TEGRA194_POWER_DOMAIN_NVDECA 6 +-#define TEGRA194_POWER_DOMAIN_NVJPG 7 +-#define TEGRA194_POWER_DOMAIN_NVENCA 8 +-#define TEGRA194_POWER_DOMAIN_NVENCB 9 +-#define TEGRA194_POWER_DOMAIN_NVDECB 10 +-#define TEGRA194_POWER_DOMAIN_SAX 11 +-#define TEGRA194_POWER_DOMAIN_VE 12 +-#define TEGRA194_POWER_DOMAIN_VIC 13 +-#define TEGRA194_POWER_DOMAIN_XUSBA 14 +-#define TEGRA194_POWER_DOMAIN_XUSBB 15 +-#define TEGRA194_POWER_DOMAIN_XUSBC 16 +-#define TEGRA194_POWER_DOMAIN_PCIEX8A 17 +-#define TEGRA194_POWER_DOMAIN_PCIEX4A 18 +-#define TEGRA194_POWER_DOMAIN_PCIEX1A 19 +-#define TEGRA194_POWER_DOMAIN_PCIEX8B 21 +-#define TEGRA194_POWER_DOMAIN_PVAA 22 +-#define TEGRA194_POWER_DOMAIN_PVAB 23 +-#define TEGRA194_POWER_DOMAIN_DLAA 24 +-#define TEGRA194_POWER_DOMAIN_DLAB 25 +-#define TEGRA194_POWER_DOMAIN_CV 26 +-#define TEGRA194_POWER_DOMAIN_GPU 27 +-#define TEGRA194_POWER_DOMAIN_MAX 27 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/power/xlnx-zynqmp-power.h b/scripts/dtc/include-prefixes/dt-bindings/power/xlnx-zynqmp-power.h +deleted file mode 100644 +index 0d9a412fd5e0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/power/xlnx-zynqmp-power.h ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2018 Xilinx, Inc. +- */ +- +-#ifndef _DT_BINDINGS_ZYNQMP_POWER_H +-#define _DT_BINDINGS_ZYNQMP_POWER_H +- +-#define PD_USB_0 22 +-#define PD_USB_1 23 +-#define PD_TTC_0 24 +-#define PD_TTC_1 25 +-#define PD_TTC_2 26 +-#define PD_TTC_3 27 +-#define PD_SATA 28 +-#define PD_ETH_0 29 +-#define PD_ETH_1 30 +-#define PD_ETH_2 31 +-#define PD_ETH_3 32 +-#define PD_UART_0 33 +-#define PD_UART_1 34 +-#define PD_SPI_0 35 +-#define PD_SPI_1 36 +-#define PD_I2C_0 37 +-#define PD_I2C_1 38 +-#define PD_SD_0 39 +-#define PD_SD_1 40 +-#define PD_DP 41 +-#define PD_GDMA 42 +-#define PD_ADMA 43 +-#define PD_NAND 44 +-#define PD_QSPI 45 +-#define PD_GPIO 46 +-#define PD_CAN_0 47 +-#define PD_CAN_1 48 +-#define PD_GPU 58 +-#define PD_PCIE 59 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pwm/pwm.h b/scripts/dtc/include-prefixes/dt-bindings/pwm/pwm.h +deleted file mode 100644 +index ab9a077e3c7d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pwm/pwm.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for most PWM bindings. +- * +- * Most PWM bindings can include a flags cell as part of the PWM specifier. +- * In most cases, the format of the flags cell uses the standard values +- * defined in this header. +- */ +- +-#ifndef _DT_BINDINGS_PWM_PWM_H +-#define _DT_BINDINGS_PWM_PWM_H +- +-#define PWM_POLARITY_INVERTED (1 << 0) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/pwm/raspberrypi,firmware-poe-pwm.h b/scripts/dtc/include-prefixes/dt-bindings/pwm/raspberrypi,firmware-poe-pwm.h +deleted file mode 100644 +index 27c5ce68847b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/pwm/raspberrypi,firmware-poe-pwm.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2020 Nicolas Saenz Julienne +- * Author: Nicolas Saenz Julienne +- */ +- +-#ifndef _DT_BINDINGS_RASPBERRYPI_FIRMWARE_PWM_H +-#define _DT_BINDINGS_RASPBERRYPI_FIRMWARE_PWM_H +- +-#define RASPBERRYPI_FIRMWARE_PWM_POE 0 +-#define RASPBERRYPI_FIRMWARE_PWM_NUM 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/regulator/active-semi,8865-regulator.h b/scripts/dtc/include-prefixes/dt-bindings/regulator/active-semi,8865-regulator.h +deleted file mode 100644 +index 15473dbeaf38..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/regulator/active-semi,8865-regulator.h ++++ /dev/null +@@ -1,28 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Device Tree binding constants for the ACT8865 PMIC regulators +- */ +- +-#ifndef _DT_BINDINGS_REGULATOR_ACT8865_H +-#define _DT_BINDINGS_REGULATOR_ACT8865_H +- +-/* +- * These constants should be used to specify regulator modes in device tree for +- * ACT8865 regulators as follows: +- * ACT8865_REGULATOR_MODE_FIXED: It is specific to DCDC regulators and it +- * specifies the usage of fixed-frequency +- * PWM. +- * +- * ACT8865_REGULATOR_MODE_NORMAL: It is specific to LDO regulators and it +- * specifies the usage of normal mode. +- * +- * ACT8865_REGULATOR_MODE_LOWPOWER: For DCDC and LDO regulators; it specify +- * the usage of proprietary power-saving +- * mode. +- */ +- +-#define ACT8865_REGULATOR_MODE_FIXED 1 +-#define ACT8865_REGULATOR_MODE_NORMAL 2 +-#define ACT8865_REGULATOR_MODE_LOWPOWER 3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/regulator/active-semi,8945a-regulator.h b/scripts/dtc/include-prefixes/dt-bindings/regulator/active-semi,8945a-regulator.h +deleted file mode 100644 +index 9bdba5e3141a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/regulator/active-semi,8945a-regulator.h ++++ /dev/null +@@ -1,30 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2018 Microchip Technology, Inc. All rights reserved. +- * +- * Device Tree binding constants for the ACT8945A PMIC regulators +- */ +- +-#ifndef _DT_BINDINGS_REGULATOR_ACT8945A_H +-#define _DT_BINDINGS_REGULATOR_ACT8945A_H +- +-/* +- * These constants should be used to specify regulator modes in device tree for +- * ACT8945A regulators as follows: +- * ACT8945A_REGULATOR_MODE_FIXED: It is specific to DCDC regulators and it +- * specifies the usage of fixed-frequency +- * PWM. +- * +- * ACT8945A_REGULATOR_MODE_NORMAL: It is specific to LDO regulators and it +- * specifies the usage of normal mode. +- * +- * ACT8945A_REGULATOR_MODE_LOWPOWER: For DCDC and LDO regulators; it specify +- * the usage of proprietary power-saving +- * mode. +- */ +- +-#define ACT8945A_REGULATOR_MODE_FIXED 1 +-#define ACT8945A_REGULATOR_MODE_NORMAL 2 +-#define ACT8945A_REGULATOR_MODE_LOWPOWER 3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/regulator/dlg,da9063-regulator.h b/scripts/dtc/include-prefixes/dt-bindings/regulator/dlg,da9063-regulator.h +deleted file mode 100644 +index 1de710dd0899..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/regulator/dlg,da9063-regulator.h ++++ /dev/null +@@ -1,16 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +- +-#ifndef _DT_BINDINGS_REGULATOR_DLG_DA9063_H +-#define _DT_BINDINGS_REGULATOR_DLG_DA9063_H +- +-/* +- * These buck mode constants may be used to specify values in device tree +- * properties (e.g. regulator-initial-mode). +- * A description of the following modes is in the manufacturers datasheet. +- */ +- +-#define DA9063_BUCK_MODE_SLEEP 1 +-#define DA9063_BUCK_MODE_SYNC 2 +-#define DA9063_BUCK_MODE_AUTO 3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/regulator/dlg,da9121-regulator.h b/scripts/dtc/include-prefixes/dt-bindings/regulator/dlg,da9121-regulator.h +deleted file mode 100644 +index 954edf633ce7..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/regulator/dlg,da9121-regulator.h ++++ /dev/null +@@ -1,22 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef _DT_BINDINGS_REGULATOR_DLG_DA9121_H +-#define _DT_BINDINGS_REGULATOR_DLG_DA9121_H +- +-/* +- * These buck mode constants may be used to specify values in device tree +- * properties (e.g. regulator-initial-mode). +- * A description of the following modes is in the manufacturers datasheet. +- */ +- +-#define DA9121_BUCK_MODE_FORCE_PFM 0 +-#define DA9121_BUCK_MODE_FORCE_PWM 1 +-#define DA9121_BUCK_MODE_FORCE_PWM_SHEDDING 2 +-#define DA9121_BUCK_MODE_AUTO 3 +- +-#define DA9121_BUCK_RIPPLE_CANCEL_NONE 0 +-#define DA9121_BUCK_RIPPLE_CANCEL_SMALL 1 +-#define DA9121_BUCK_RIPPLE_CANCEL_MID 2 +-#define DA9121_BUCK_RIPPLE_CANCEL_LARGE 3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/regulator/dlg,da9211-regulator.h b/scripts/dtc/include-prefixes/dt-bindings/regulator/dlg,da9211-regulator.h +deleted file mode 100644 +index cdce2d54c8ba..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/regulator/dlg,da9211-regulator.h ++++ /dev/null +@@ -1,16 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +- +-#ifndef _DT_BINDINGS_REGULATOR_DLG_DA9211_H +-#define _DT_BINDINGS_REGULATOR_DLG_DA9211_H +- +-/* +- * These buck mode constants may be used to specify values in device tree +- * properties (e.g. regulator-initial-mode, regulator-allowed-modes). +- * A description of the following modes is in the manufacturers datasheet. +- */ +- +-#define DA9211_BUCK_MODE_SLEEP 1 +-#define DA9211_BUCK_MODE_SYNC 2 +-#define DA9211_BUCK_MODE_AUTO 3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/regulator/maxim,max77802.h b/scripts/dtc/include-prefixes/dt-bindings/regulator/maxim,max77802.h +deleted file mode 100644 +index d0baba1973d4..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/regulator/maxim,max77802.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2014 Google, Inc +- * +- * Device Tree binding constants for the Maxim 77802 PMIC regulators +- */ +- +-#ifndef _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H +-#define _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H +- +-/* Regulator operating modes */ +-#define MAX77802_OPMODE_LP 1 +-#define MAX77802_OPMODE_NORMAL 3 +- +-#endif /* _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/regulator/mediatek,mt6360-regulator.h b/scripts/dtc/include-prefixes/dt-bindings/regulator/mediatek,mt6360-regulator.h +deleted file mode 100644 +index 21c75de700c0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/regulator/mediatek,mt6360-regulator.h ++++ /dev/null +@@ -1,16 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +- +-#ifndef __DT_BINDINGS_MEDIATEK_MT6360_REGULATOR_H__ +-#define __DT_BINDINGS_MEDIATEK_MT6360_REGULATOR_H__ +- +-/* +- * BUCK/LDO mode constants which may be used in devicetree properties +- * (eg. regulator-allowed-modes). +- * See the manufacturer's datasheet for more information on these modes. +- */ +- +-#define MT6360_OPMODE_LP 2 +-#define MT6360_OPMODE_ULP 3 +-#define MT6360_OPMODE_NORMAL 0 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/regulator/mediatek,mt6397-regulator.h b/scripts/dtc/include-prefixes/dt-bindings/regulator/mediatek,mt6397-regulator.h +deleted file mode 100644 +index 99869a8665cf..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/regulator/mediatek,mt6397-regulator.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +- +-#ifndef _DT_BINDINGS_REGULATOR_MEDIATEK_MT6397_H_ +-#define _DT_BINDINGS_REGULATOR_MEDIATEK_MT6397_H_ +- +-/* +- * Buck mode constants which may be used in devicetree properties (eg. +- * regulator-initial-mode, regulator-allowed-modes). +- * See the manufacturer's datasheet for more information on these modes. +- */ +- +-#define MT6397_BUCK_MODE_AUTO 0 +-#define MT6397_BUCK_MODE_FORCE_PWM 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/regulator/qcom,rpmh-regulator.h b/scripts/dtc/include-prefixes/dt-bindings/regulator/qcom,rpmh-regulator.h +deleted file mode 100644 +index 86713dcf9e02..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/regulator/qcom,rpmh-regulator.h ++++ /dev/null +@@ -1,36 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ +- +-#ifndef __QCOM_RPMH_REGULATOR_H +-#define __QCOM_RPMH_REGULATOR_H +- +-/* +- * These mode constants may be used to specify modes for various RPMh regulator +- * device tree properties (e.g. regulator-initial-mode). Each type of regulator +- * supports a subset of the possible modes. +- * +- * %RPMH_REGULATOR_MODE_RET: Retention mode in which only an extremely small +- * load current is allowed. This mode is supported +- * by LDO and SMPS type regulators. +- * %RPMH_REGULATOR_MODE_LPM: Low power mode in which a small load current is +- * allowed. This mode corresponds to PFM for SMPS +- * and BOB type regulators. This mode is supported +- * by LDO, HFSMPS, BOB, and PMIC4 FTSMPS type +- * regulators. +- * %RPMH_REGULATOR_MODE_AUTO: Auto mode in which the regulator hardware +- * automatically switches between LPM and HPM based +- * upon the real-time load current. This mode is +- * supported by HFSMPS, BOB, and PMIC4 FTSMPS type +- * regulators. +- * %RPMH_REGULATOR_MODE_HPM: High power mode in which the full rated current +- * of the regulator is allowed. This mode +- * corresponds to PWM for SMPS and BOB type +- * regulators. This mode is supported by all types +- * of regulators. +- */ +-#define RPMH_REGULATOR_MODE_RET 0 +-#define RPMH_REGULATOR_MODE_LPM 1 +-#define RPMH_REGULATOR_MODE_AUTO 2 +-#define RPMH_REGULATOR_MODE_HPM 3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset-controller/mt2712-resets.h b/scripts/dtc/include-prefixes/dt-bindings/reset-controller/mt2712-resets.h +deleted file mode 100644 +index 9e7ee762f076..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset-controller/mt2712-resets.h ++++ /dev/null +@@ -1,22 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2019 MediaTek Inc. +- * Author: Yong Liang +- */ +- +-#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712 +-#define _DT_BINDINGS_RESET_CONTROLLER_MT2712 +- +-#define MT2712_TOPRGU_INFRA_SW_RST 0 +-#define MT2712_TOPRGU_MM_SW_RST 1 +-#define MT2712_TOPRGU_MFG_SW_RST 2 +-#define MT2712_TOPRGU_VENC_SW_RST 3 +-#define MT2712_TOPRGU_VDEC_SW_RST 4 +-#define MT2712_TOPRGU_IMG_SW_RST 5 +-#define MT2712_TOPRGU_INFRA_AO_SW_RST 8 +-#define MT2712_TOPRGU_USB_SW_RST 9 +-#define MT2712_TOPRGU_APMIXED_SW_RST 10 +- +-#define MT2712_TOPRGU_SW_RST_NUM 11 +- +-#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset-controller/mt8183-resets.h b/scripts/dtc/include-prefixes/dt-bindings/reset-controller/mt8183-resets.h +deleted file mode 100644 +index a1bbd41e0d12..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset-controller/mt8183-resets.h ++++ /dev/null +@@ -1,98 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2019 MediaTek Inc. +- * Author: Yong Liang +- */ +- +-#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8183 +-#define _DT_BINDINGS_RESET_CONTROLLER_MT8183 +- +-/* INFRACFG AO resets */ +-#define MT8183_INFRACFG_AO_THERM_SW_RST 0 +-#define MT8183_INFRACFG_AO_USB_TOP_SW_RST 1 +-#define MT8183_INFRACFG_AO_MM_IOMMU_SW_RST 3 +-#define MT8183_INFRACFG_AO_MSDC3_SW_RST 4 +-#define MT8183_INFRACFG_AO_MSDC2_SW_RST 5 +-#define MT8183_INFRACFG_AO_MSDC1_SW_RST 6 +-#define MT8183_INFRACFG_AO_MSDC0_SW_RST 7 +-#define MT8183_INFRACFG_AO_APDMA_SW_RST 9 +-#define MT8183_INFRACFG_AO_MIMP_D_SW_RST 10 +-#define MT8183_INFRACFG_AO_BTIF_SW_RST 12 +-#define MT8183_INFRACFG_AO_DISP_PWM_SW_RST 14 +-#define MT8183_INFRACFG_AO_AUXADC_SW_RST 15 +- +-#define MT8183_INFRACFG_AO_IRTX_SW_RST 32 +-#define MT8183_INFRACFG_AO_SPI0_SW_RST 33 +-#define MT8183_INFRACFG_AO_I2C0_SW_RST 34 +-#define MT8183_INFRACFG_AO_I2C1_SW_RST 35 +-#define MT8183_INFRACFG_AO_I2C2_SW_RST 36 +-#define MT8183_INFRACFG_AO_I2C3_SW_RST 37 +-#define MT8183_INFRACFG_AO_UART0_SW_RST 38 +-#define MT8183_INFRACFG_AO_UART1_SW_RST 39 +-#define MT8183_INFRACFG_AO_UART2_SW_RST 40 +-#define MT8183_INFRACFG_AO_PWM_SW_RST 41 +-#define MT8183_INFRACFG_AO_SPI1_SW_RST 42 +-#define MT8183_INFRACFG_AO_I2C4_SW_RST 43 +-#define MT8183_INFRACFG_AO_DVFSP_SW_RST 44 +-#define MT8183_INFRACFG_AO_SPI2_SW_RST 45 +-#define MT8183_INFRACFG_AO_SPI3_SW_RST 46 +-#define MT8183_INFRACFG_AO_UFSHCI_SW_RST 47 +- +-#define MT8183_INFRACFG_AO_PMIC_WRAP_SW_RST 64 +-#define MT8183_INFRACFG_AO_SPM_SW_RST 65 +-#define MT8183_INFRACFG_AO_USBSIF_SW_RST 66 +-#define MT8183_INFRACFG_AO_KP_SW_RST 68 +-#define MT8183_INFRACFG_AO_APXGPT_SW_RST 69 +-#define MT8183_INFRACFG_AO_CLDMA_AO_SW_RST 70 +-#define MT8183_INFRACFG_AO_UNIPRO_UFS_SW_RST 71 +-#define MT8183_INFRACFG_AO_DX_CC_SW_RST 72 +-#define MT8183_INFRACFG_AO_UFSPHY_SW_RST 73 +- +-#define MT8183_INFRACFG_AO_DX_CC_SEC_SW_RST 96 +-#define MT8183_INFRACFG_AO_GCE_SW_RST 97 +-#define MT8183_INFRACFG_AO_CLDMA_SW_RST 98 +-#define MT8183_INFRACFG_AO_TRNG_SW_RST 99 +-#define MT8183_INFRACFG_AO_AP_MD_CCIF_1_SW_RST 103 +-#define MT8183_INFRACFG_AO_AP_MD_CCIF_SW_RST 104 +-#define MT8183_INFRACFG_AO_I2C1_IMM_SW_RST 105 +-#define MT8183_INFRACFG_AO_I2C1_ARB_SW_RST 106 +-#define MT8183_INFRACFG_AO_I2C2_IMM_SW_RST 107 +-#define MT8183_INFRACFG_AO_I2C2_ARB_SW_RST 108 +-#define MT8183_INFRACFG_AO_I2C5_SW_RST 109 +-#define MT8183_INFRACFG_AO_I2C5_IMM_SW_RST 110 +-#define MT8183_INFRACFG_AO_I2C5_ARB_SW_RST 111 +-#define MT8183_INFRACFG_AO_SPI4_SW_RST 112 +-#define MT8183_INFRACFG_AO_SPI5_SW_RST 113 +-#define MT8183_INFRACFG_AO_INFRA2MFGAXI_CBIP_CLAS_SW_RST 114 +-#define MT8183_INFRACFG_AO_MFGAXI2INFRA_M0_CBIP_GLAS_OUT_SW_RST 115 +-#define MT8183_INFRACFG_AO_MFGAXI2INFRA_M1_CBIP_GLAS_OUT_SW_RST 116 +-#define MT8183_INFRACFG_AO_UFS_AES_SW_RST 117 +-#define MT8183_INFRACFG_AO_CCU_I2C_IRQ_SW_RST 118 +-#define MT8183_INFRACFG_AO_CCU_I2C_DMA_SW_RST 119 +-#define MT8183_INFRACFG_AO_I2C6_SW_RST 120 +-#define MT8183_INFRACFG_AO_CCU_GALS_SW_RST 121 +-#define MT8183_INFRACFG_AO_IPU_GALS_SW_RST 122 +-#define MT8183_INFRACFG_AO_CONN2AP_GALS_SW_RST 123 +-#define MT8183_INFRACFG_AO_AP_MD_CCIF2_SW_RST 124 +-#define MT8183_INFRACFG_AO_AP_MD_CCIF3_SW_RST 125 +-#define MT8183_INFRACFG_AO_I2C7_SW_RST 126 +-#define MT8183_INFRACFG_AO_I2C8_SW_RST 127 +- +-#define MT8183_INFRACFG_SW_RST_NUM 128 +- +-#define MT8183_TOPRGU_MM_SW_RST 1 +-#define MT8183_TOPRGU_MFG_SW_RST 2 +-#define MT8183_TOPRGU_VENC_SW_RST 3 +-#define MT8183_TOPRGU_VDEC_SW_RST 4 +-#define MT8183_TOPRGU_IMG_SW_RST 5 +-#define MT8183_TOPRGU_MD_SW_RST 7 +-#define MT8183_TOPRGU_CONN_SW_RST 9 +-#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 +-#define MT8183_TOPRGU_IPU0_SW_RST 14 +-#define MT8183_TOPRGU_IPU1_SW_RST 15 +-#define MT8183_TOPRGU_AUDIO_SW_RST 17 +-#define MT8183_TOPRGU_CAMSYS_SW_RST 18 +- +-#define MT8183_TOPRGU_SW_RST_NUM 19 +- +-#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset-controller/mt8192-resets.h b/scripts/dtc/include-prefixes/dt-bindings/reset-controller/mt8192-resets.h +deleted file mode 100644 +index be9a7ca245b9..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset-controller/mt8192-resets.h ++++ /dev/null +@@ -1,30 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2020 MediaTek Inc. +- * Author: Yong Liang +- */ +- +-#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 +-#define _DT_BINDINGS_RESET_CONTROLLER_MT8192 +- +-#define MT8192_TOPRGU_MM_SW_RST 1 +-#define MT8192_TOPRGU_MFG_SW_RST 2 +-#define MT8192_TOPRGU_VENC_SW_RST 3 +-#define MT8192_TOPRGU_VDEC_SW_RST 4 +-#define MT8192_TOPRGU_IMG_SW_RST 5 +-#define MT8192_TOPRGU_MD_SW_RST 7 +-#define MT8192_TOPRGU_CONN_SW_RST 9 +-#define MT8192_TOPRGU_CONN_MCU_SW_RST 12 +-#define MT8192_TOPRGU_IPU0_SW_RST 14 +-#define MT8192_TOPRGU_IPU1_SW_RST 15 +-#define MT8192_TOPRGU_AUDIO_SW_RST 17 +-#define MT8192_TOPRGU_CAMSYS_SW_RST 18 +-#define MT8192_TOPRGU_MJC_SW_RST 19 +-#define MT8192_TOPRGU_C2K_S2_SW_RST 20 +-#define MT8192_TOPRGU_C2K_SW_RST 21 +-#define MT8192_TOPRGU_PERI_SW_RST 22 +-#define MT8192_TOPRGU_PERI_AO_SW_RST 23 +- +-#define MT8192_TOPRGU_SW_RST_NUM 23 +- +-#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/actions,s500-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/actions,s500-reset.h +deleted file mode 100644 +index f5d94176d10b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/actions,s500-reset.h ++++ /dev/null +@@ -1,67 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Device Tree binding constants for Actions Semi S500 Reset Management Unit +- * +- * Copyright (c) 2014 Actions Semi Inc. +- * Copyright (c) 2020 Cristian Ciocaltea +- */ +- +-#ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H +-#define __DT_BINDINGS_ACTIONS_S500_RESET_H +- +-#define RESET_DMAC 0 +-#define RESET_NORIF 1 +-#define RESET_DDR 2 +-#define RESET_NANDC 3 +-#define RESET_SD0 4 +-#define RESET_SD1 5 +-#define RESET_PCM1 6 +-#define RESET_DE 7 +-#define RESET_LCD 8 +-#define RESET_SD2 9 +-#define RESET_DSI 10 +-#define RESET_CSI 11 +-#define RESET_BISP 12 +-#define RESET_KEY 13 +-#define RESET_GPIO 14 +-#define RESET_AUDIO 15 +-#define RESET_PCM0 16 +-#define RESET_VDE 17 +-#define RESET_VCE 18 +-#define RESET_GPU3D 19 +-#define RESET_NIC301 20 +-#define RESET_LENS 21 +-#define RESET_PERIPHRESET 22 +-#define RESET_USB2_0 23 +-#define RESET_TVOUT 24 +-#define RESET_HDMI 25 +-#define RESET_HDCP2TX 26 +-#define RESET_UART6 27 +-#define RESET_UART0 28 +-#define RESET_UART1 29 +-#define RESET_UART2 30 +-#define RESET_SPI0 31 +-#define RESET_SPI1 32 +-#define RESET_SPI2 33 +-#define RESET_SPI3 34 +-#define RESET_I2C0 35 +-#define RESET_I2C1 36 +-#define RESET_USB3 37 +-#define RESET_UART3 38 +-#define RESET_UART4 39 +-#define RESET_UART5 40 +-#define RESET_I2C2 41 +-#define RESET_I2C3 42 +-#define RESET_ETHERNET 43 +-#define RESET_CHIPID 44 +-#define RESET_USB2_1 45 +-#define RESET_WD0RESET 46 +-#define RESET_WD1RESET 47 +-#define RESET_WD2RESET 48 +-#define RESET_WD3RESET 49 +-#define RESET_DBG0RESET 50 +-#define RESET_DBG1RESET 51 +-#define RESET_DBG2RESET 52 +-#define RESET_DBG3RESET 53 +- +-#endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/actions,s700-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/actions,s700-reset.h +deleted file mode 100644 +index 5e3b16b8ef53..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/actions,s700-reset.h ++++ /dev/null +@@ -1,34 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +-// +-// Device Tree binding constants for Actions Semi S700 Reset Management Unit +-// +-// Copyright (c) 2018 Linaro Ltd. +- +-#ifndef __DT_BINDINGS_ACTIONS_S700_RESET_H +-#define __DT_BINDINGS_ACTIONS_S700_RESET_H +- +-#define RESET_AUDIO 0 +-#define RESET_CSI 1 +-#define RESET_DE 2 +-#define RESET_DSI 3 +-#define RESET_GPIO 4 +-#define RESET_I2C0 5 +-#define RESET_I2C1 6 +-#define RESET_I2C2 7 +-#define RESET_I2C3 8 +-#define RESET_KEY 9 +-#define RESET_LCD0 10 +-#define RESET_SI 11 +-#define RESET_SPI0 12 +-#define RESET_SPI1 13 +-#define RESET_SPI2 14 +-#define RESET_SPI3 15 +-#define RESET_UART0 16 +-#define RESET_UART1 17 +-#define RESET_UART2 18 +-#define RESET_UART3 19 +-#define RESET_UART4 20 +-#define RESET_UART5 21 +-#define RESET_UART6 22 +- +-#endif /* __DT_BINDINGS_ACTIONS_S700_RESET_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/actions,s900-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/actions,s900-reset.h +deleted file mode 100644 +index 42c19d02e43b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/actions,s900-reset.h ++++ /dev/null +@@ -1,65 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +-// +-// Device Tree binding constants for Actions Semi S900 Reset Management Unit +-// +-// Copyright (c) 2018 Linaro Ltd. +- +-#ifndef __DT_BINDINGS_ACTIONS_S900_RESET_H +-#define __DT_BINDINGS_ACTIONS_S900_RESET_H +- +-#define RESET_CHIPID 0 +-#define RESET_CPU_SCNT 1 +-#define RESET_SRAMI 2 +-#define RESET_DDR_CTL_PHY 3 +-#define RESET_DMAC 4 +-#define RESET_GPIO 5 +-#define RESET_BISP_AXI 6 +-#define RESET_CSI0 7 +-#define RESET_CSI1 8 +-#define RESET_DE 9 +-#define RESET_DSI 10 +-#define RESET_GPU3D_PA 11 +-#define RESET_GPU3D_PB 12 +-#define RESET_HDE 13 +-#define RESET_I2C0 14 +-#define RESET_I2C1 15 +-#define RESET_I2C2 16 +-#define RESET_I2C3 17 +-#define RESET_I2C4 18 +-#define RESET_I2C5 19 +-#define RESET_IMX 20 +-#define RESET_NANDC0 21 +-#define RESET_NANDC1 22 +-#define RESET_SD0 23 +-#define RESET_SD1 24 +-#define RESET_SD2 25 +-#define RESET_SD3 26 +-#define RESET_SPI0 27 +-#define RESET_SPI1 28 +-#define RESET_SPI2 29 +-#define RESET_SPI3 30 +-#define RESET_UART0 31 +-#define RESET_UART1 32 +-#define RESET_UART2 33 +-#define RESET_UART3 34 +-#define RESET_UART4 35 +-#define RESET_UART5 36 +-#define RESET_UART6 37 +-#define RESET_HDMI 38 +-#define RESET_LVDS 39 +-#define RESET_EDP 40 +-#define RESET_USB2HUB 41 +-#define RESET_USB2HSIC 42 +-#define RESET_USB3 43 +-#define RESET_PCM1 44 +-#define RESET_AUDIO 45 +-#define RESET_PCM0 46 +-#define RESET_SE 47 +-#define RESET_GIC 48 +-#define RESET_DDR_CTL_PHY_AXI 49 +-#define RESET_CMU_DDR 50 +-#define RESET_DMM 51 +-#define RESET_HDCP2TX 52 +-#define RESET_ETHERNET 53 +- +-#endif /* __DT_BINDINGS_ACTIONS_S900_RESET_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/altr,rst-mgr-a10.h b/scripts/dtc/include-prefixes/dt-bindings/reset/altr,rst-mgr-a10.h +deleted file mode 100644 +index 5d8a494c98d0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/altr,rst-mgr-a10.h ++++ /dev/null +@@ -1,102 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014, Steffen Trumtrar +- */ +- +-#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H +-#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H +- +-/* MPUMODRST */ +-#define CPU0_RESET 0 +-#define CPU1_RESET 1 +-#define WDS_RESET 2 +-#define SCUPER_RESET 3 +- +-/* PER0MODRST */ +-#define EMAC0_RESET 32 +-#define EMAC1_RESET 33 +-#define EMAC2_RESET 34 +-#define USB0_RESET 35 +-#define USB1_RESET 36 +-#define NAND_RESET 37 +-#define QSPI_RESET 38 +-#define SDMMC_RESET 39 +-#define EMAC0_OCP_RESET 40 +-#define EMAC1_OCP_RESET 41 +-#define EMAC2_OCP_RESET 42 +-#define USB0_OCP_RESET 43 +-#define USB1_OCP_RESET 44 +-#define NAND_OCP_RESET 45 +-#define QSPI_OCP_RESET 46 +-#define SDMMC_OCP_RESET 47 +-#define DMA_RESET 48 +-#define SPIM0_RESET 49 +-#define SPIM1_RESET 50 +-#define SPIS0_RESET 51 +-#define SPIS1_RESET 52 +-#define DMA_OCP_RESET 53 +-#define EMAC_PTP_RESET 54 +-/* 55 is empty*/ +-#define DMAIF0_RESET 56 +-#define DMAIF1_RESET 57 +-#define DMAIF2_RESET 58 +-#define DMAIF3_RESET 59 +-#define DMAIF4_RESET 60 +-#define DMAIF5_RESET 61 +-#define DMAIF6_RESET 62 +-#define DMAIF7_RESET 63 +- +-/* PER1MODRST */ +-#define L4WD0_RESET 64 +-#define L4WD1_RESET 65 +-#define L4SYSTIMER0_RESET 66 +-#define L4SYSTIMER1_RESET 67 +-#define SPTIMER0_RESET 68 +-#define SPTIMER1_RESET 69 +-/* 70-71 is reserved */ +-#define I2C0_RESET 72 +-#define I2C1_RESET 73 +-#define I2C2_RESET 74 +-#define I2C3_RESET 75 +-#define I2C4_RESET 76 +-/* 77-79 is reserved */ +-#define UART0_RESET 80 +-#define UART1_RESET 81 +-/* 82-87 is reserved */ +-#define GPIO0_RESET 88 +-#define GPIO1_RESET 89 +-#define GPIO2_RESET 90 +- +-/* BRGMODRST */ +-#define HPS2FPGA_RESET 96 +-#define LWHPS2FPGA_RESET 97 +-#define FPGA2HPS_RESET 98 +-#define F2SSDRAM0_RESET 99 +-#define F2SSDRAM1_RESET 100 +-#define F2SSDRAM2_RESET 101 +-#define DDRSCH_RESET 102 +- +-/* SYSMODRST*/ +-#define ROM_RESET 128 +-#define OCRAM_RESET 129 +-/* 130 is reserved */ +-#define FPGAMGR_RESET 131 +-#define S2F_RESET 132 +-#define SYSDBG_RESET 133 +-#define OCRAM_OCP_RESET 134 +- +-/* COLDMODRST */ +-#define CLKMGRCOLD_RESET 160 +-/* 161-162 is reserved */ +-#define S2FCOLD_RESET 163 +-#define TIMESTAMPCOLD_RESET 164 +-#define TAPCOLD_RESET 165 +-#define HMCCOLD_RESET 166 +-#define IOMGRCOLD_RESET 167 +- +-/* NRSTMODRST */ +-#define NRSTPINOE_RESET 192 +- +-/* DBGMODRST */ +-#define DBG_RESET 224 +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/altr,rst-mgr-a10sr.h b/scripts/dtc/include-prefixes/dt-bindings/reset/altr,rst-mgr-a10sr.h +deleted file mode 100644 +index 09a15ea58182..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/altr,rst-mgr-a10sr.h ++++ /dev/null +@@ -1,22 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright Intel Corporation (C) 2017. All Rights Reserved +- * +- * Reset binding definitions for Altera Arria10 MAX5 System Resource Chip +- * +- * Adapted from altr,rst-mgr-a10.h +- */ +- +-#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H +-#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H +- +-/* Peripheral PHY resets */ +-#define A10SR_RESET_ENET_HPS 0 +-#define A10SR_RESET_PCIE 1 +-#define A10SR_RESET_FILE 2 +-#define A10SR_RESET_BQSPI 3 +-#define A10SR_RESET_USB 4 +- +-#define A10SR_RESET_NUM 5 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/altr,rst-mgr-s10.h b/scripts/dtc/include-prefixes/dt-bindings/reset/altr,rst-mgr-s10.h +deleted file mode 100644 +index 70ea3a09dbe1..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/altr,rst-mgr-s10.h ++++ /dev/null +@@ -1,97 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2016 Intel Corporation. All rights reserved +- * Copyright (C) 2016 Altera Corporation. All rights reserved +- * +- * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h" +- */ +- +-#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H +-#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H +- +-/* MPUMODRST */ +-#define CPU0_RESET 0 +-#define CPU1_RESET 1 +-#define CPU2_RESET 2 +-#define CPU3_RESET 3 +- +-/* PER0MODRST */ +-#define EMAC0_RESET 32 +-#define EMAC1_RESET 33 +-#define EMAC2_RESET 34 +-#define USB0_RESET 35 +-#define USB1_RESET 36 +-#define NAND_RESET 37 +-/* 38 is empty */ +-#define SDMMC_RESET 39 +-#define EMAC0_OCP_RESET 40 +-#define EMAC1_OCP_RESET 41 +-#define EMAC2_OCP_RESET 42 +-#define USB0_OCP_RESET 43 +-#define USB1_OCP_RESET 44 +-#define NAND_OCP_RESET 45 +-/* 46 is empty */ +-#define SDMMC_OCP_RESET 47 +-#define DMA_RESET 48 +-#define SPIM0_RESET 49 +-#define SPIM1_RESET 50 +-#define SPIS0_RESET 51 +-#define SPIS1_RESET 52 +-#define DMA_OCP_RESET 53 +-#define EMAC_PTP_RESET 54 +-/* 55 is empty*/ +-#define DMAIF0_RESET 56 +-#define DMAIF1_RESET 57 +-#define DMAIF2_RESET 58 +-#define DMAIF3_RESET 59 +-#define DMAIF4_RESET 60 +-#define DMAIF5_RESET 61 +-#define DMAIF6_RESET 62 +-#define DMAIF7_RESET 63 +- +-/* PER1MODRST */ +-#define WATCHDOG0_RESET 64 +-#define WATCHDOG1_RESET 65 +-#define WATCHDOG2_RESET 66 +-#define WATCHDOG3_RESET 67 +-#define L4SYSTIMER0_RESET 68 +-#define L4SYSTIMER1_RESET 69 +-#define SPTIMER0_RESET 70 +-#define SPTIMER1_RESET 71 +-#define I2C0_RESET 72 +-#define I2C1_RESET 73 +-#define I2C2_RESET 74 +-#define I2C3_RESET 75 +-#define I2C4_RESET 76 +-/* 77-79 is empty */ +-#define UART0_RESET 80 +-#define UART1_RESET 81 +-/* 82-87 is empty */ +-#define GPIO0_RESET 88 +-#define GPIO1_RESET 89 +- +-/* BRGMODRST */ +-#define SOC2FPGA_RESET 96 +-#define LWHPS2FPGA_RESET 97 +-#define FPGA2SOC_RESET 98 +-#define F2SSDRAM0_RESET 99 +-#define F2SSDRAM1_RESET 100 +-#define F2SSDRAM2_RESET 101 +-#define DDRSCH_RESET 102 +- +-/* COLDMODRST */ +-#define CPUPO0_RESET 160 +-#define CPUPO1_RESET 161 +-#define CPUPO2_RESET 162 +-#define CPUPO3_RESET 163 +-/* 164-167 is empty */ +-#define L2_RESET 168 +- +-/* DBGMODRST */ +-#define DBG_RESET 224 +-#define CSDAP_RESET 225 +- +-/* TAPMODRST */ +-#define TAP_RESET 256 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/altr,rst-mgr.h b/scripts/dtc/include-prefixes/dt-bindings/reset/altr,rst-mgr.h +deleted file mode 100644 +index 9b6ce14f62c1..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/altr,rst-mgr.h ++++ /dev/null +@@ -1,82 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014, Steffen Trumtrar +- */ +- +-#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H +-#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H +- +-/* MPUMODRST */ +-#define CPU0_RESET 0 +-#define CPU1_RESET 1 +-#define WDS_RESET 2 +-#define SCUPER_RESET 3 +-#define L2_RESET 4 +- +-/* PERMODRST */ +-#define EMAC0_RESET 32 +-#define EMAC1_RESET 33 +-#define USB0_RESET 34 +-#define USB1_RESET 35 +-#define NAND_RESET 36 +-#define QSPI_RESET 37 +-#define L4WD0_RESET 38 +-#define L4WD1_RESET 39 +-#define OSC1TIMER0_RESET 40 +-#define OSC1TIMER1_RESET 41 +-#define SPTIMER0_RESET 42 +-#define SPTIMER1_RESET 43 +-#define I2C0_RESET 44 +-#define I2C1_RESET 45 +-#define I2C2_RESET 46 +-#define I2C3_RESET 47 +-#define UART0_RESET 48 +-#define UART1_RESET 49 +-#define SPIM0_RESET 50 +-#define SPIM1_RESET 51 +-#define SPIS0_RESET 52 +-#define SPIS1_RESET 53 +-#define SDMMC_RESET 54 +-#define CAN0_RESET 55 +-#define CAN1_RESET 56 +-#define GPIO0_RESET 57 +-#define GPIO1_RESET 58 +-#define GPIO2_RESET 59 +-#define DMA_RESET 60 +-#define SDR_RESET 61 +- +-/* PER2MODRST */ +-#define DMAIF0_RESET 64 +-#define DMAIF1_RESET 65 +-#define DMAIF2_RESET 66 +-#define DMAIF3_RESET 67 +-#define DMAIF4_RESET 68 +-#define DMAIF5_RESET 69 +-#define DMAIF6_RESET 70 +-#define DMAIF7_RESET 71 +- +-/* BRGMODRST */ +-#define HPS2FPGA_RESET 96 +-#define LWHPS2FPGA_RESET 97 +-#define FPGA2HPS_RESET 98 +- +-/* MISCMODRST*/ +-#define ROM_RESET 128 +-#define OCRAM_RESET 129 +-#define SYSMGR_RESET 130 +-#define SYSMGRCOLD_RESET 131 +-#define FPGAMGR_RESET 132 +-#define ACPIDMAP_RESET 133 +-#define S2F_RESET 134 +-#define S2FCOLD_RESET 135 +-#define NRSTPIN_RESET 136 +-#define TIMESTAMPCOLD_RESET 137 +-#define CLKMGRCOLD_RESET 138 +-#define SCANMGR_RESET 139 +-#define FRZCTRLCOLD_RESET 140 +-#define SYSDBG_RESET 141 +-#define DBG_RESET 142 +-#define TAPCOLD_RESET 143 +-#define SDRCOLD_RESET 144 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson-a1-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson-a1-reset.h +deleted file mode 100644 +index f1a3a797540d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson-a1-reset.h ++++ /dev/null +@@ -1,74 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- * +- * Copyright (c) 2019 Amlogic, Inc. All rights reserved. +- * Author: Xingyu Chen +- * +- */ +- +-#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H +-#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H +- +-/* RESET0 */ +-/* 0 */ +-#define RESET_AM2AXI_VAD 1 +-/* 2-3 */ +-#define RESET_PSRAM 4 +-#define RESET_PAD_CTRL 5 +-/* 6 */ +-#define RESET_TEMP_SENSOR 7 +-#define RESET_AM2AXI_DEV 8 +-/* 9 */ +-#define RESET_SPICC_A 10 +-#define RESET_MSR_CLK 11 +-#define RESET_AUDIO 12 +-#define RESET_ANALOG_CTRL 13 +-#define RESET_SAR_ADC 14 +-#define RESET_AUDIO_VAD 15 +-#define RESET_CEC 16 +-#define RESET_PWM_EF 17 +-#define RESET_PWM_CD 18 +-#define RESET_PWM_AB 19 +-/* 20 */ +-#define RESET_IR_CTRL 21 +-#define RESET_I2C_S_A 22 +-/* 23 */ +-#define RESET_I2C_M_D 24 +-#define RESET_I2C_M_C 25 +-#define RESET_I2C_M_B 26 +-#define RESET_I2C_M_A 27 +-#define RESET_I2C_PROD_AHB 28 +-#define RESET_I2C_PROD 29 +-/* 30-31 */ +- +-/* RESET1 */ +-#define RESET_ACODEC 32 +-#define RESET_DMA 33 +-#define RESET_SD_EMMC_A 34 +-/* 35 */ +-#define RESET_USBCTRL 36 +-/* 37 */ +-#define RESET_USBPHY 38 +-/* 39-41 */ +-#define RESET_RSA 42 +-#define RESET_DMC 43 +-/* 44 */ +-#define RESET_IRQ_CTRL 45 +-/* 46 */ +-#define RESET_NIC_VAD 47 +-#define RESET_NIC_AXI 48 +-#define RESET_RAMA 49 +-#define RESET_RAMB 50 +-/* 51-52 */ +-#define RESET_ROM 53 +-#define RESET_SPIFC 54 +-#define RESET_GIC 55 +-#define RESET_UART_C 56 +-#define RESET_UART_B 57 +-#define RESET_UART_A 58 +-#define RESET_OSC_RING 59 +-/* 60-63 */ +- +-/* RESET2 */ +-/* 64-95 */ +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson-axg-audio-arb.h b/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson-axg-audio-arb.h +deleted file mode 100644 +index 1ef807856cb8..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson-axg-audio-arb.h ++++ /dev/null +@@ -1,19 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) +- * +- * Copyright (c) 2018 Baylibre SAS. +- * Author: Jerome Brunet +- */ +- +-#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H +-#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H +- +-#define AXG_ARB_TODDR_A 0 +-#define AXG_ARB_TODDR_B 1 +-#define AXG_ARB_TODDR_C 2 +-#define AXG_ARB_FRDDR_A 3 +-#define AXG_ARB_FRDDR_B 4 +-#define AXG_ARB_FRDDR_C 5 +-#define AXG_ARB_TODDR_D 6 +-#define AXG_ARB_FRDDR_D 7 +- +-#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson-axg-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson-axg-reset.h +deleted file mode 100644 +index 0f2e0fe45ca4..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson-axg-reset.h ++++ /dev/null +@@ -1,123 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +-/* +- * Copyright (c) 2016 BayLibre, SAS. +- * Author: Neil Armstrong +- * +- * Copyright (c) 2017 Amlogic, inc. +- * Author: Yixun Lan +- * +- */ +- +-#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H +-#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H +- +-/* RESET0 */ +-#define RESET_HIU 0 +-#define RESET_PCIE_A 1 +-#define RESET_PCIE_B 2 +-#define RESET_DDR_TOP 3 +-/* 4 */ +-#define RESET_VIU 5 +-#define RESET_PCIE_PHY 6 +-#define RESET_PCIE_APB 7 +-/* 8 */ +-/* 9 */ +-#define RESET_VENC 10 +-#define RESET_ASSIST 11 +-/* 12 */ +-#define RESET_VCBUS 13 +-/* 14 */ +-/* 15 */ +-#define RESET_GIC 16 +-#define RESET_CAPB3_DECODE 17 +-/* 18-21 */ +-#define RESET_SYS_CPU_CAPB3 22 +-#define RESET_CBUS_CAPB3 23 +-#define RESET_AHB_CNTL 24 +-#define RESET_AHB_DATA 25 +-#define RESET_VCBUS_CLK81 26 +-#define RESET_MMC 27 +-/* 28-31 */ +-/* RESET1 */ +-/* 32 */ +-/* 33 */ +-#define RESET_USB_OTG 34 +-#define RESET_DDR 35 +-#define RESET_AO_RESET 36 +-/* 37 */ +-#define RESET_AHB_SRAM 38 +-/* 39 */ +-/* 40 */ +-#define RESET_DMA 41 +-#define RESET_ISA 42 +-#define RESET_ETHERNET 43 +-/* 44 */ +-#define RESET_SD_EMMC_B 45 +-#define RESET_SD_EMMC_C 46 +-#define RESET_ROM_BOOT 47 +-#define RESET_SYS_CPU_0 48 +-#define RESET_SYS_CPU_1 49 +-#define RESET_SYS_CPU_2 50 +-#define RESET_SYS_CPU_3 51 +-#define RESET_SYS_CPU_CORE_0 52 +-#define RESET_SYS_CPU_CORE_1 53 +-#define RESET_SYS_CPU_CORE_2 54 +-#define RESET_SYS_CPU_CORE_3 55 +-#define RESET_SYS_PLL_DIV 56 +-#define RESET_SYS_CPU_AXI 57 +-#define RESET_SYS_CPU_L2 58 +-#define RESET_SYS_CPU_P 59 +-#define RESET_SYS_CPU_MBIST 60 +-/* 61-63 */ +-/* RESET2 */ +-/* 64 */ +-/* 65 */ +-#define RESET_AUDIO 66 +-/* 67 */ +-#define RESET_MIPI_HOST 68 +-#define RESET_AUDIO_LOCKER 69 +-#define RESET_GE2D 70 +-/* 71-76 */ +-#define RESET_AO_CPU_RESET 77 +-/* 78-95 */ +-/* RESET3 */ +-#define RESET_RING_OSCILLATOR 96 +-/* 97-127 */ +-/* RESET4 */ +-/* 128 */ +-/* 129 */ +-#define RESET_MIPI_PHY 130 +-/* 131-140 */ +-#define RESET_VENCL 141 +-#define RESET_I2C_MASTER_2 142 +-#define RESET_I2C_MASTER_1 143 +-/* 144-159 */ +-/* RESET5 */ +-/* 160-191 */ +-/* RESET6 */ +-#define RESET_PERIPHS_GENERAL 192 +-#define RESET_PERIPHS_SPICC 193 +-/* 194 */ +-/* 195 */ +-#define RESET_PERIPHS_I2C_MASTER_0 196 +-/* 197-200 */ +-#define RESET_PERIPHS_UART_0 201 +-#define RESET_PERIPHS_UART_1 202 +-/* 203-204 */ +-#define RESET_PERIPHS_SPI_0 205 +-#define RESET_PERIPHS_I2C_MASTER_3 206 +-/* 207-223 */ +-/* RESET7 */ +-#define RESET_USB_DDR_0 224 +-#define RESET_USB_DDR_1 225 +-#define RESET_USB_DDR_2 226 +-#define RESET_USB_DDR_3 227 +-/* 228 */ +-#define RESET_DEVICE_MMC_ARB 229 +-/* 230 */ +-#define RESET_VID_LOCK 231 +-#define RESET_A9_DMC_PIPEL 232 +-#define RESET_DMC_VPU_PIPEL 233 +-/* 234-255 */ +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h +deleted file mode 100644 +index f805129ca7af..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h ++++ /dev/null +@@ -1,53 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2019 BayLibre, SAS. +- * Author: Jerome Brunet +- * +- */ +- +-#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H +-#define _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H +- +-#define AUD_RESET_PDM 0 +-#define AUD_RESET_TDMIN_A 1 +-#define AUD_RESET_TDMIN_B 2 +-#define AUD_RESET_TDMIN_C 3 +-#define AUD_RESET_TDMIN_LB 4 +-#define AUD_RESET_LOOPBACK 5 +-#define AUD_RESET_TODDR_A 6 +-#define AUD_RESET_TODDR_B 7 +-#define AUD_RESET_TODDR_C 8 +-#define AUD_RESET_FRDDR_A 9 +-#define AUD_RESET_FRDDR_B 10 +-#define AUD_RESET_FRDDR_C 11 +-#define AUD_RESET_TDMOUT_A 12 +-#define AUD_RESET_TDMOUT_B 13 +-#define AUD_RESET_TDMOUT_C 14 +-#define AUD_RESET_SPDIFOUT 15 +-#define AUD_RESET_SPDIFOUT_B 16 +-#define AUD_RESET_SPDIFIN 17 +-#define AUD_RESET_EQDRC 18 +-#define AUD_RESET_RESAMPLE 19 +-#define AUD_RESET_DDRARB 20 +-#define AUD_RESET_POWDET 21 +-#define AUD_RESET_TORAM 22 +-#define AUD_RESET_TOACODEC 23 +-#define AUD_RESET_TOHDMITX 24 +-#define AUD_RESET_CLKTREE 25 +- +-/* SM1 added resets */ +-#define AUD_RESET_RESAMPLE_B 26 +-#define AUD_RESET_TOVAD 27 +-#define AUD_RESET_LOCKER 28 +-#define AUD_RESET_SPDIFIN_LB 29 +-#define AUD_RESET_FRATV 30 +-#define AUD_RESET_FRHDMIRX 31 +-#define AUD_RESET_FRDDR_D 32 +-#define AUD_RESET_TODDR_D 33 +-#define AUD_RESET_LOOPBACK_B 34 +-#define AUD_RESET_EARCTX 35 +-#define AUD_RESET_EARCRX 36 +-#define AUD_RESET_FRDDR_E 37 +-#define AUD_RESET_TODDR_E 38 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson-g12a-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson-g12a-reset.h +deleted file mode 100644 +index 6d487c5eba2c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson-g12a-reset.h ++++ /dev/null +@@ -1,137 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +-/* +- * Copyright (c) 2019 BayLibre, SAS. +- * Author: Jerome Brunet +- * +- */ +- +-#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H +-#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H +- +-/* RESET0 */ +-#define RESET_HIU 0 +-/* 1 */ +-#define RESET_DOS 2 +-/* 3-4 */ +-#define RESET_VIU 5 +-#define RESET_AFIFO 6 +-#define RESET_VID_PLL_DIV 7 +-/* 8-9 */ +-#define RESET_VENC 10 +-#define RESET_ASSIST 11 +-#define RESET_PCIE_CTRL_A 12 +-#define RESET_VCBUS 13 +-#define RESET_PCIE_PHY 14 +-#define RESET_PCIE_APB 15 +-#define RESET_GIC 16 +-#define RESET_CAPB3_DECODE 17 +-/* 18 */ +-#define RESET_HDMITX_CAPB3 19 +-#define RESET_DVALIN_CAPB3 20 +-#define RESET_DOS_CAPB3 21 +-/* 22 */ +-#define RESET_CBUS_CAPB3 23 +-#define RESET_AHB_CNTL 24 +-#define RESET_AHB_DATA 25 +-#define RESET_VCBUS_CLK81 26 +-/* 27-31 */ +-/* RESET1 */ +-/* 32 */ +-#define RESET_DEMUX 33 +-#define RESET_USB 34 +-#define RESET_DDR 35 +-/* 36 */ +-#define RESET_BT656 37 +-#define RESET_AHB_SRAM 38 +-/* 39 */ +-#define RESET_PARSER 40 +-/* 41 */ +-#define RESET_ISA 42 +-#define RESET_ETHERNET 43 +-#define RESET_SD_EMMC_A 44 +-#define RESET_SD_EMMC_B 45 +-#define RESET_SD_EMMC_C 46 +-/* 47 */ +-#define RESET_USB_PHY20 48 +-#define RESET_USB_PHY21 49 +-/* 50-60 */ +-#define RESET_AUDIO_CODEC 61 +-/* 62-63 */ +-/* RESET2 */ +-/* 64 */ +-#define RESET_AUDIO 65 +-#define RESET_HDMITX_PHY 66 +-/* 67 */ +-#define RESET_MIPI_DSI_HOST 68 +-#define RESET_ALOCKER 69 +-#define RESET_GE2D 70 +-#define RESET_PARSER_REG 71 +-#define RESET_PARSER_FETCH 72 +-#define RESET_CTL 73 +-#define RESET_PARSER_TOP 74 +-/* 75-77 */ +-#define RESET_DVALIN 78 +-#define RESET_HDMITX 79 +-/* 80-95 */ +-/* RESET3 */ +-/* 96-95 */ +-#define RESET_DEMUX_TOP 105 +-#define RESET_DEMUX_DES_PL 106 +-#define RESET_DEMUX_S2P_0 107 +-#define RESET_DEMUX_S2P_1 108 +-#define RESET_DEMUX_0 109 +-#define RESET_DEMUX_1 110 +-#define RESET_DEMUX_2 111 +-/* 112-127 */ +-/* RESET4 */ +-/* 128-129 */ +-#define RESET_MIPI_DSI_PHY 130 +-/* 131-132 */ +-#define RESET_RDMA 133 +-#define RESET_VENCI 134 +-#define RESET_VENCP 135 +-/* 136 */ +-#define RESET_VDAC 137 +-/* 138-139 */ +-#define RESET_VDI6 140 +-#define RESET_VENCL 141 +-#define RESET_I2C_M1 142 +-#define RESET_I2C_M2 143 +-/* 144-159 */ +-/* RESET5 */ +-/* 160-191 */ +-/* RESET6 */ +-#define RESET_GEN 192 +-#define RESET_SPICC0 193 +-#define RESET_SC 194 +-#define RESET_SANA_3 195 +-#define RESET_I2C_M0 196 +-#define RESET_TS_PLL 197 +-#define RESET_SPICC1 198 +-#define RESET_STREAM 199 +-#define RESET_TS_CPU 200 +-#define RESET_UART0 201 +-#define RESET_UART1_2 202 +-#define RESET_ASYNC0 203 +-#define RESET_ASYNC1 204 +-#define RESET_SPIFC0 205 +-#define RESET_I2C_M3 206 +-/* 207-223 */ +-/* RESET7 */ +-#define RESET_USB_DDR_0 224 +-#define RESET_USB_DDR_1 225 +-#define RESET_USB_DDR_2 226 +-#define RESET_USB_DDR_3 227 +-#define RESET_TS_GPU 228 +-#define RESET_DEVICE_MMC_ARB 229 +-#define RESET_DVALIN_DMC_PIPL 230 +-#define RESET_VID_LOCK 231 +-#define RESET_NIC_DMC_PIPL 232 +-#define RESET_DMC_VPU_PIPL 233 +-#define RESET_GE2D_DMC_PIPL 234 +-#define RESET_HCODEC_DMC_PIPL 235 +-#define RESET_WAVE420_DMC_PIPL 236 +-#define RESET_HEVCF_DMC_PIPL 237 +-/* 238-255 */ +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson-gxbb-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson-gxbb-reset.h +deleted file mode 100644 +index 883bfd3bcbad..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson-gxbb-reset.h ++++ /dev/null +@@ -1,161 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +-/* +- * Copyright (c) 2016 BayLibre, SAS. +- * Author: Neil Armstrong +- */ +-#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H +-#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H +- +-/* RESET0 */ +-#define RESET_HIU 0 +-/* 1 */ +-#define RESET_DOS_RESET 2 +-#define RESET_DDR_TOP 3 +-#define RESET_DCU_RESET 4 +-#define RESET_VIU 5 +-#define RESET_AIU 6 +-#define RESET_VID_PLL_DIV 7 +-/* 8 */ +-#define RESET_PMUX 9 +-#define RESET_VENC 10 +-#define RESET_ASSIST 11 +-#define RESET_AFIFO2 12 +-#define RESET_VCBUS 13 +-/* 14 */ +-/* 15 */ +-#define RESET_GIC 16 +-#define RESET_CAPB3_DECODE 17 +-#define RESET_NAND_CAPB3 18 +-#define RESET_HDMITX_CAPB3 19 +-#define RESET_MALI_CAPB3 20 +-#define RESET_DOS_CAPB3 21 +-#define RESET_SYS_CPU_CAPB3 22 +-#define RESET_CBUS_CAPB3 23 +-#define RESET_AHB_CNTL 24 +-#define RESET_AHB_DATA 25 +-#define RESET_VCBUS_CLK81 26 +-#define RESET_MMC 27 +-#define RESET_MIPI_0 28 +-#define RESET_MIPI_1 29 +-#define RESET_MIPI_2 30 +-#define RESET_MIPI_3 31 +-/* RESET1 */ +-#define RESET_CPPM 32 +-#define RESET_DEMUX 33 +-#define RESET_USB_OTG 34 +-#define RESET_DDR 35 +-#define RESET_AO_RESET 36 +-#define RESET_BT656 37 +-#define RESET_AHB_SRAM 38 +-/* 39 */ +-#define RESET_PARSER 40 +-#define RESET_BLKMV 41 +-#define RESET_ISA 42 +-#define RESET_ETHERNET 43 +-#define RESET_SD_EMMC_A 44 +-#define RESET_SD_EMMC_B 45 +-#define RESET_SD_EMMC_C 46 +-#define RESET_ROM_BOOT 47 +-#define RESET_SYS_CPU_0 48 +-#define RESET_SYS_CPU_1 49 +-#define RESET_SYS_CPU_2 50 +-#define RESET_SYS_CPU_3 51 +-#define RESET_SYS_CPU_CORE_0 52 +-#define RESET_SYS_CPU_CORE_1 53 +-#define RESET_SYS_CPU_CORE_2 54 +-#define RESET_SYS_CPU_CORE_3 55 +-#define RESET_SYS_PLL_DIV 56 +-#define RESET_SYS_CPU_AXI 57 +-#define RESET_SYS_CPU_L2 58 +-#define RESET_SYS_CPU_P 59 +-#define RESET_SYS_CPU_MBIST 60 +-#define RESET_ACODEC 61 +-/* 62 */ +-/* 63 */ +-/* RESET2 */ +-#define RESET_VD_RMEM 64 +-#define RESET_AUDIN 65 +-#define RESET_HDMI_TX 66 +-/* 67 */ +-/* 68 */ +-/* 69 */ +-#define RESET_GE2D 70 +-#define RESET_PARSER_REG 71 +-#define RESET_PARSER_FETCH 72 +-#define RESET_PARSER_CTL 73 +-#define RESET_PARSER_TOP 74 +-/* 75 */ +-/* 76 */ +-#define RESET_AO_CPU_RESET 77 +-#define RESET_MALI 78 +-#define RESET_HDMI_SYSTEM_RESET 79 +-/* 80-95 */ +-/* RESET3 */ +-#define RESET_RING_OSCILLATOR 96 +-#define RESET_SYS_CPU 97 +-#define RESET_EFUSE 98 +-#define RESET_SYS_CPU_BVCI 99 +-#define RESET_AIFIFO 100 +-#define RESET_TVFE 101 +-#define RESET_AHB_BRIDGE_CNTL 102 +-/* 103 */ +-#define RESET_AUDIO_DAC 104 +-#define RESET_DEMUX_TOP 105 +-#define RESET_DEMUX_DES 106 +-#define RESET_DEMUX_S2P_0 107 +-#define RESET_DEMUX_S2P_1 108 +-#define RESET_DEMUX_RESET_0 109 +-#define RESET_DEMUX_RESET_1 110 +-#define RESET_DEMUX_RESET_2 111 +-/* 112-127 */ +-/* RESET4 */ +-/* 128 */ +-/* 129 */ +-/* 130 */ +-/* 131 */ +-#define RESET_DVIN_RESET 132 +-#define RESET_RDMA 133 +-#define RESET_VENCI 134 +-#define RESET_VENCP 135 +-/* 136 */ +-#define RESET_VDAC 137 +-#define RESET_RTC 138 +-/* 139 */ +-#define RESET_VDI6 140 +-#define RESET_VENCL 141 +-#define RESET_I2C_MASTER_2 142 +-#define RESET_I2C_MASTER_1 143 +-/* 144-159 */ +-/* RESET5 */ +-/* 160-191 */ +-/* RESET6 */ +-#define RESET_PERIPHS_GENERAL 192 +-#define RESET_PERIPHS_SPICC 193 +-#define RESET_PERIPHS_SMART_CARD 194 +-#define RESET_PERIPHS_SAR_ADC 195 +-#define RESET_PERIPHS_I2C_MASTER_0 196 +-#define RESET_SANA 197 +-/* 198 */ +-#define RESET_PERIPHS_STREAM_INTERFACE 199 +-#define RESET_PERIPHS_SDIO 200 +-#define RESET_PERIPHS_UART_0 201 +-#define RESET_PERIPHS_UART_1_2 202 +-#define RESET_PERIPHS_ASYNC_0 203 +-#define RESET_PERIPHS_ASYNC_1 204 +-#define RESET_PERIPHS_SPI_0 205 +-#define RESET_PERIPHS_SDHC 206 +-#define RESET_UART_SLIP 207 +-/* 208-223 */ +-/* RESET7 */ +-#define RESET_USB_DDR_0 224 +-#define RESET_USB_DDR_1 225 +-#define RESET_USB_DDR_2 226 +-#define RESET_USB_DDR_3 227 +-/* 228 */ +-#define RESET_DEVICE_MMC_ARB 229 +-/* 230 */ +-#define RESET_VID_LOCK 231 +-#define RESET_A9_DMC_PIPEL 232 +-/* 233-255 */ +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson8b-clkc-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson8b-clkc-reset.h +deleted file mode 100644 +index 1f1b56e57346..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson8b-clkc-reset.h ++++ /dev/null +@@ -1,27 +0,0 @@ +-/* +- * Copyright (c) 2017 Martin Blumenstingl . +- * +- * SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- */ +- +-#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H +-#define _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H +- +-#define CLKC_RESET_L2_CACHE_SOFT_RESET 0 +-#define CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET 1 +-#define CLKC_RESET_SCU_SOFT_RESET 2 +-#define CLKC_RESET_CPU0_SOFT_RESET 3 +-#define CLKC_RESET_CPU1_SOFT_RESET 4 +-#define CLKC_RESET_CPU2_SOFT_RESET 5 +-#define CLKC_RESET_CPU3_SOFT_RESET 6 +-#define CLKC_RESET_A5_GLOBAL_RESET 7 +-#define CLKC_RESET_A5_AXI_SOFT_RESET 8 +-#define CLKC_RESET_A5_ABP_SOFT_RESET 9 +-#define CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET 10 +-#define CLKC_RESET_VID_CLK_CNTL_SOFT_RESET 11 +-#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST 12 +-#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE 13 +-#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST 14 +-#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE 15 +- +-#endif /* _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson8b-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson8b-reset.h +deleted file mode 100644 +index fbc524a900da..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/amlogic,meson8b-reset.h ++++ /dev/null +@@ -1,126 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +-/* +- * Copyright (c) 2016 BayLibre, SAS. +- * Author: Neil Armstrong +- */ +-#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H +-#define _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H +- +-/* RESET0 */ +-#define RESET_HIU 0 +-#define RESET_VLD 1 +-#define RESET_IQIDCT 2 +-#define RESET_MC 3 +-/* 8 */ +-#define RESET_VIU 5 +-#define RESET_AIU 6 +-#define RESET_MCPU 7 +-#define RESET_CCPU 8 +-#define RESET_PMUX 9 +-#define RESET_VENC 10 +-#define RESET_ASSIST 11 +-#define RESET_AFIFO2 12 +-#define RESET_MDEC 13 +-#define RESET_VLD_PART 14 +-#define RESET_VIFIFO 15 +-/* 16-31 */ +-/* RESET1 */ +-/* 32 */ +-#define RESET_DEMUX 33 +-#define RESET_USB_OTG 34 +-#define RESET_DDR 35 +-#define RESET_VDAC_1 36 +-#define RESET_BT656 37 +-#define RESET_AHB_SRAM 38 +-#define RESET_AHB_BRIDGE 39 +-#define RESET_PARSER 40 +-#define RESET_BLKMV 41 +-#define RESET_ISA 42 +-#define RESET_ETHERNET 43 +-#define RESET_ABUF 44 +-#define RESET_AHB_DATA 45 +-#define RESET_AHB_CNTL 46 +-#define RESET_ROM_BOOT 47 +-/* 48-63 */ +-/* RESET2 */ +-#define RESET_VD_RMEM 64 +-#define RESET_AUDIN 65 +-#define RESET_DBLK 66 +-#define RESET_PIC_DC 67 +-#define RESET_PSC 68 +-#define RESET_NAND 69 +-#define RESET_GE2D 70 +-#define RESET_PARSER_REG 71 +-#define RESET_PARSER_FETCH 72 +-#define RESET_PARSER_CTL 73 +-#define RESET_PARSER_TOP 74 +-#define RESET_HDMI_APB 75 +-#define RESET_AUDIO_APB 76 +-#define RESET_MEDIA_CPU 77 +-#define RESET_MALI 78 +-#define RESET_HDMI_SYSTEM_RESET 79 +-/* 80-95 */ +-/* RESET3 */ +-#define RESET_RING_OSCILLATOR 96 +-#define RESET_SYS_CPU_0 97 +-#define RESET_EFUSE 98 +-#define RESET_SYS_CPU_BVCI 99 +-#define RESET_AIFIFO 100 +-#define RESET_AUDIO_PLL_MODULATOR 101 +-#define RESET_AHB_BRIDGE_CNTL 102 +-#define RESET_SYS_CPU_1 103 +-#define RESET_AUDIO_DAC 104 +-#define RESET_DEMUX_TOP 105 +-#define RESET_DEMUX_DES 106 +-#define RESET_DEMUX_S2P_0 107 +-#define RESET_DEMUX_S2P_1 108 +-#define RESET_DEMUX_RESET_0 109 +-#define RESET_DEMUX_RESET_1 110 +-#define RESET_DEMUX_RESET_2 111 +-/* 112-127 */ +-/* RESET4 */ +-#define RESET_PL310 128 +-#define RESET_A5_APB 129 +-#define RESET_A5_AXI 130 +-#define RESET_A5 131 +-#define RESET_DVIN 132 +-#define RESET_RDMA 133 +-#define RESET_VENCI 134 +-#define RESET_VENCP 135 +-#define RESET_VENCT 136 +-#define RESET_VDAC_4 137 +-#define RESET_RTC 138 +-#define RESET_A5_DEBUG 139 +-#define RESET_VDI6 140 +-#define RESET_VENCL 141 +-/* 142-159 */ +-/* RESET5 */ +-#define RESET_DDR_PLL 160 +-#define RESET_MISC_PLL 161 +-#define RESET_SYS_PLL 162 +-#define RESET_HPLL_PLL 163 +-#define RESET_AUDIO_PLL 164 +-#define RESET_VID2_PLL 165 +-/* 166-191 */ +-/* RESET6 */ +-#define RESET_PERIPHS_GENERAL 192 +-#define RESET_PERIPHS_IR_REMOTE 193 +-#define RESET_PERIPHS_SMART_CARD 194 +-#define RESET_PERIPHS_SAR_ADC 195 +-#define RESET_PERIPHS_I2C_MASTER_0 196 +-#define RESET_PERIPHS_I2C_MASTER_1 197 +-#define RESET_PERIPHS_I2C_SLAVE 198 +-#define RESET_PERIPHS_STREAM_INTERFACE 199 +-#define RESET_PERIPHS_SDIO 200 +-#define RESET_PERIPHS_UART_0 201 +-#define RESET_PERIPHS_UART_1 202 +-#define RESET_PERIPHS_ASYNC_0 203 +-#define RESET_PERIPHS_ASYNC_1 204 +-#define RESET_PERIPHS_SPI_0 205 +-#define RESET_PERIPHS_SPI_1 206 +-#define RESET_PERIPHS_LED_PWM 207 +-/* 208-223 */ +-/* RESET7 */ +-/* 224-255 */ +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/axg-aoclkc.h b/scripts/dtc/include-prefixes/dt-bindings/reset/axg-aoclkc.h +deleted file mode 100644 +index d342c0b6b2a7..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/axg-aoclkc.h ++++ /dev/null +@@ -1,20 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +-/* +- * Copyright (c) 2016 BayLibre, SAS +- * Author: Neil Armstrong +- * +- * Copyright (c) 2018 Amlogic, inc. +- * Author: Qiufang Dai +- */ +- +-#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK +-#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK +- +-#define RESET_AO_REMOTE 0 +-#define RESET_AO_I2C_MASTER 1 +-#define RESET_AO_I2C_SLAVE 2 +-#define RESET_AO_UART1 3 +-#define RESET_AO_UART2 4 +-#define RESET_AO_IR_BLASTER 5 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/bcm6318-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/bcm6318-reset.h +deleted file mode 100644 +index f882662505ea..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/bcm6318-reset.h ++++ /dev/null +@@ -1,20 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef __DT_BINDINGS_RESET_BCM6318_H +-#define __DT_BINDINGS_RESET_BCM6318_H +- +-#define BCM6318_RST_SPI 0 +-#define BCM6318_RST_EPHY 1 +-#define BCM6318_RST_SAR 2 +-#define BCM6318_RST_ENETSW 3 +-#define BCM6318_RST_USBD 4 +-#define BCM6318_RST_USBH 5 +-#define BCM6318_RST_PCIE_CORE 6 +-#define BCM6318_RST_PCIE 7 +-#define BCM6318_RST_PCIE_EXT 8 +-#define BCM6318_RST_PCIE_HARD 9 +-#define BCM6318_RST_ADSL 10 +-#define BCM6318_RST_PHYMIPS 11 +-#define BCM6318_RST_HOSTMIPS 12 +- +-#endif /* __DT_BINDINGS_RESET_BCM6318_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/bcm63268-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/bcm63268-reset.h +deleted file mode 100644 +index 6a6403a4c2d5..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/bcm63268-reset.h ++++ /dev/null +@@ -1,26 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef __DT_BINDINGS_RESET_BCM63268_H +-#define __DT_BINDINGS_RESET_BCM63268_H +- +-#define BCM63268_RST_SPI 0 +-#define BCM63268_RST_IPSEC 1 +-#define BCM63268_RST_EPHY 2 +-#define BCM63268_RST_SAR 3 +-#define BCM63268_RST_ENETSW 4 +-#define BCM63268_RST_USBS 5 +-#define BCM63268_RST_USBH 6 +-#define BCM63268_RST_PCM 7 +-#define BCM63268_RST_PCIE_CORE 8 +-#define BCM63268_RST_PCIE 9 +-#define BCM63268_RST_PCIE_EXT 10 +-#define BCM63268_RST_WLAN_SHIM 11 +-#define BCM63268_RST_DDR_PHY 12 +-#define BCM63268_RST_FAP0 13 +-#define BCM63268_RST_WLAN_UBUS 14 +-#define BCM63268_RST_DECT 15 +-#define BCM63268_RST_FAP1 16 +-#define BCM63268_RST_PCIE_HARD 17 +-#define BCM63268_RST_GPHY 18 +- +-#endif /* __DT_BINDINGS_RESET_BCM63268_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/bcm6328-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/bcm6328-reset.h +deleted file mode 100644 +index 0f3df87d47af..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/bcm6328-reset.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef __DT_BINDINGS_RESET_BCM6328_H +-#define __DT_BINDINGS_RESET_BCM6328_H +- +-#define BCM6328_RST_SPI 0 +-#define BCM6328_RST_EPHY 1 +-#define BCM6328_RST_SAR 2 +-#define BCM6328_RST_ENETSW 3 +-#define BCM6328_RST_USBS 4 +-#define BCM6328_RST_USBH 5 +-#define BCM6328_RST_PCM 6 +-#define BCM6328_RST_PCIE_CORE 7 +-#define BCM6328_RST_PCIE 8 +-#define BCM6328_RST_PCIE_EXT 9 +-#define BCM6328_RST_PCIE_HARD 10 +- +-#endif /* __DT_BINDINGS_RESET_BCM6328_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/bcm6358-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/bcm6358-reset.h +deleted file mode 100644 +index bda62ef84f5a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/bcm6358-reset.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef __DT_BINDINGS_RESET_BCM6358_H +-#define __DT_BINDINGS_RESET_BCM6358_H +- +-#define BCM6358_RST_SPI 0 +-#define BCM6358_RST_ENET 2 +-#define BCM6358_RST_MPI 3 +-#define BCM6358_RST_EPHY 6 +-#define BCM6358_RST_SAR 7 +-#define BCM6358_RST_USBH 12 +-#define BCM6358_RST_PCM 13 +-#define BCM6358_RST_ADSL 14 +- +-#endif /* __DT_BINDINGS_RESET_BCM6358_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/bcm6362-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/bcm6362-reset.h +deleted file mode 100644 +index 7ebb0546e0ab..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/bcm6362-reset.h ++++ /dev/null +@@ -1,22 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef __DT_BINDINGS_RESET_BCM6362_H +-#define __DT_BINDINGS_RESET_BCM6362_H +- +-#define BCM6362_RST_SPI 0 +-#define BCM6362_RST_IPSEC 1 +-#define BCM6362_RST_EPHY 2 +-#define BCM6362_RST_SAR 3 +-#define BCM6362_RST_ENETSW 4 +-#define BCM6362_RST_USBD 5 +-#define BCM6362_RST_USBH 6 +-#define BCM6362_RST_PCM 7 +-#define BCM6362_RST_PCIE_CORE 8 +-#define BCM6362_RST_PCIE 9 +-#define BCM6362_RST_PCIE_EXT 10 +-#define BCM6362_RST_WLAN_SHIM 11 +-#define BCM6362_RST_DDR_PHY 12 +-#define BCM6362_RST_FAP 13 +-#define BCM6362_RST_WLAN_UBUS 14 +- +-#endif /* __DT_BINDINGS_RESET_BCM6362_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/bcm6368-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/bcm6368-reset.h +deleted file mode 100644 +index c81d8eb6d173..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/bcm6368-reset.h ++++ /dev/null +@@ -1,16 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef __DT_BINDINGS_RESET_BCM6368_H +-#define __DT_BINDINGS_RESET_BCM6368_H +- +-#define BCM6368_RST_SPI 0 +-#define BCM6368_RST_MPI 3 +-#define BCM6368_RST_IPSEC 4 +-#define BCM6368_RST_EPHY 6 +-#define BCM6368_RST_SAR 7 +-#define BCM6368_RST_SWITCH 10 +-#define BCM6368_RST_USBD 11 +-#define BCM6368_RST_USBH 12 +-#define BCM6368_RST_PCM 13 +- +-#endif /* __DT_BINDINGS_RESET_BCM6368_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/bitmain,bm1880-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/bitmain,bm1880-reset.h +deleted file mode 100644 +index 4c0de5223773..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/bitmain,bm1880-reset.h ++++ /dev/null +@@ -1,51 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright (c) 2018 Bitmain Ltd. +- * Copyright (c) 2019 Linaro Ltd. +- */ +- +-#ifndef _DT_BINDINGS_BM1880_RESET_H +-#define _DT_BINDINGS_BM1880_RESET_H +- +-#define BM1880_RST_MAIN_AP 0 +-#define BM1880_RST_SECOND_AP 1 +-#define BM1880_RST_DDR 2 +-#define BM1880_RST_VIDEO 3 +-#define BM1880_RST_JPEG 4 +-#define BM1880_RST_VPP 5 +-#define BM1880_RST_GDMA 6 +-#define BM1880_RST_AXI_SRAM 7 +-#define BM1880_RST_TPU 8 +-#define BM1880_RST_USB 9 +-#define BM1880_RST_ETH0 10 +-#define BM1880_RST_ETH1 11 +-#define BM1880_RST_NAND 12 +-#define BM1880_RST_EMMC 13 +-#define BM1880_RST_SD 14 +-#define BM1880_RST_SDMA 15 +-#define BM1880_RST_I2S0 16 +-#define BM1880_RST_I2S1 17 +-#define BM1880_RST_UART0_1_CLK 18 +-#define BM1880_RST_UART0_1_ACLK 19 +-#define BM1880_RST_UART2_3_CLK 20 +-#define BM1880_RST_UART2_3_ACLK 21 +-#define BM1880_RST_MINER 22 +-#define BM1880_RST_I2C0 23 +-#define BM1880_RST_I2C1 24 +-#define BM1880_RST_I2C2 25 +-#define BM1880_RST_I2C3 26 +-#define BM1880_RST_I2C4 27 +-#define BM1880_RST_PWM0 28 +-#define BM1880_RST_PWM1 29 +-#define BM1880_RST_PWM2 30 +-#define BM1880_RST_PWM3 31 +-#define BM1880_RST_SPI 32 +-#define BM1880_RST_GPIO0 33 +-#define BM1880_RST_GPIO1 34 +-#define BM1880_RST_GPIO2 35 +-#define BM1880_RST_EFUSE 36 +-#define BM1880_RST_WDT 37 +-#define BM1880_RST_AHB_ROM 38 +-#define BM1880_RST_SPIC 39 +- +-#endif /* _DT_BINDINGS_BM1880_RESET_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/bt1-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/reset/bt1-ccu.h +deleted file mode 100644 +index 3578e83026bc..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/bt1-ccu.h ++++ /dev/null +@@ -1,25 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC +- * +- * Baikal-T1 CCU reset indices +- */ +-#ifndef __DT_BINDINGS_RESET_BT1_CCU_H +-#define __DT_BINDINGS_RESET_BT1_CCU_H +- +-#define CCU_AXI_MAIN_RST 0 +-#define CCU_AXI_DDR_RST 1 +-#define CCU_AXI_SATA_RST 2 +-#define CCU_AXI_GMAC0_RST 3 +-#define CCU_AXI_GMAC1_RST 4 +-#define CCU_AXI_XGMAC_RST 5 +-#define CCU_AXI_PCIE_M_RST 6 +-#define CCU_AXI_PCIE_S_RST 7 +-#define CCU_AXI_USB_RST 8 +-#define CCU_AXI_HWA_RST 9 +-#define CCU_AXI_SRAM_RST 10 +- +-#define CCU_SYS_SATA_REF_RST 0 +-#define CCU_SYS_APB_RST 1 +- +-#endif /* __DT_BINDINGS_RESET_BT1_CCU_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/cortina,gemini-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/cortina,gemini-reset.h +deleted file mode 100644 +index f48aff23847a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/cortina,gemini-reset.h ++++ /dev/null +@@ -1,37 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef _DT_BINDINGS_RESET_CORTINA_GEMINI_H +-#define _DT_BINDINGS_RESET_CORTINA_GEMINI_H +- +-#define GEMINI_RESET_DRAM 0 +-#define GEMINI_RESET_FLASH 1 +-#define GEMINI_RESET_IDE 2 +-#define GEMINI_RESET_RAID 3 +-#define GEMINI_RESET_SECURITY 4 +-#define GEMINI_RESET_GMAC0 5 +-#define GEMINI_RESET_GMAC1 6 +-#define GEMINI_RESET_PCI 7 +-#define GEMINI_RESET_USB0 8 +-#define GEMINI_RESET_USB1 9 +-#define GEMINI_RESET_DMAC 10 +-#define GEMINI_RESET_APB 11 +-#define GEMINI_RESET_LPC 12 +-#define GEMINI_RESET_LCD 13 +-#define GEMINI_RESET_INTCON0 14 +-#define GEMINI_RESET_INTCON1 15 +-#define GEMINI_RESET_RTC 16 +-#define GEMINI_RESET_TIMER 17 +-#define GEMINI_RESET_UART 18 +-#define GEMINI_RESET_SSP 19 +-#define GEMINI_RESET_GPIO0 20 +-#define GEMINI_RESET_GPIO1 21 +-#define GEMINI_RESET_GPIO2 22 +-#define GEMINI_RESET_WDOG 23 +-#define GEMINI_RESET_EXTERN 24 +-#define GEMINI_RESET_CIR 25 +-#define GEMINI_RESET_SATA0 26 +-#define GEMINI_RESET_SATA1 27 +-#define GEMINI_RESET_TVC 28 +-#define GEMINI_RESET_CPU1 30 +-#define GEMINI_RESET_GLOBAL 31 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/g12a-aoclkc.h b/scripts/dtc/include-prefixes/dt-bindings/reset/g12a-aoclkc.h +deleted file mode 100644 +index bd2e2337135c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/g12a-aoclkc.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +-/* +- * Copyright (c) 2016 BayLibre, SAS +- * Author: Neil Armstrong +- */ +- +-#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK +-#define DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK +- +-#define RESET_AO_IR_IN 0 +-#define RESET_AO_UART 1 +-#define RESET_AO_I2C_M 2 +-#define RESET_AO_I2C_S 3 +-#define RESET_AO_SAR_ADC 4 +-#define RESET_AO_UART2 5 +-#define RESET_AO_IR_OUT 6 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/gxbb-aoclkc.h b/scripts/dtc/include-prefixes/dt-bindings/reset/gxbb-aoclkc.h +deleted file mode 100644 +index 9e3fd60c309c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/gxbb-aoclkc.h ++++ /dev/null +@@ -1,66 +0,0 @@ +-/* +- * This file is provided under a dual BSD/GPLv2 license. When using or +- * redistributing this file, you may do so under either license. +- * +- * GPL LICENSE SUMMARY +- * +- * Copyright (c) 2016 BayLibre, SAS. +- * Author: Neil Armstrong +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of version 2 of the GNU General Public License as +- * published by the Free Software Foundation. +- * +- * This program is distributed in the hope that it will be useful, but +- * WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +- * General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, see . +- * The full GNU General Public License is included in this distribution +- * in the file called COPYING. +- * +- * BSD LICENSE +- * +- * Copyright (c) 2016 BayLibre, SAS. +- * Author: Neil Armstrong +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Intel Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK +-#define DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK +- +-#define RESET_AO_REMOTE 0 +-#define RESET_AO_I2C_MASTER 1 +-#define RESET_AO_I2C_SLAVE 2 +-#define RESET_AO_UART1 3 +-#define RESET_AO_UART2 4 +-#define RESET_AO_IR_BLASTER 5 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/hisi,hi6220-resets.h b/scripts/dtc/include-prefixes/dt-bindings/reset/hisi,hi6220-resets.h +deleted file mode 100644 +index 63aff7d8aa45..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/hisi,hi6220-resets.h ++++ /dev/null +@@ -1,83 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/** +- * This header provides index for the reset controller +- * based on hi6220 SoC. +- */ +-#ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220 +-#define _DT_BINDINGS_RESET_CONTROLLER_HI6220 +- +-#define PERIPH_RSTDIS0_MMC0 0x000 +-#define PERIPH_RSTDIS0_MMC1 0x001 +-#define PERIPH_RSTDIS0_MMC2 0x002 +-#define PERIPH_RSTDIS0_NANDC 0x003 +-#define PERIPH_RSTDIS0_USBOTG_BUS 0x004 +-#define PERIPH_RSTDIS0_POR_PICOPHY 0x005 +-#define PERIPH_RSTDIS0_USBOTG 0x006 +-#define PERIPH_RSTDIS0_USBOTG_32K 0x007 +-#define PERIPH_RSTDIS1_HIFI 0x100 +-#define PERIPH_RSTDIS1_DIGACODEC 0x105 +-#define PERIPH_RSTEN2_IPF 0x200 +-#define PERIPH_RSTEN2_SOCP 0x201 +-#define PERIPH_RSTEN2_DMAC 0x202 +-#define PERIPH_RSTEN2_SECENG 0x203 +-#define PERIPH_RSTEN2_ABB 0x204 +-#define PERIPH_RSTEN2_HPM0 0x205 +-#define PERIPH_RSTEN2_HPM1 0x206 +-#define PERIPH_RSTEN2_HPM2 0x207 +-#define PERIPH_RSTEN2_HPM3 0x208 +-#define PERIPH_RSTEN3_CSSYS 0x300 +-#define PERIPH_RSTEN3_I2C0 0x301 +-#define PERIPH_RSTEN3_I2C1 0x302 +-#define PERIPH_RSTEN3_I2C2 0x303 +-#define PERIPH_RSTEN3_I2C3 0x304 +-#define PERIPH_RSTEN3_UART1 0x305 +-#define PERIPH_RSTEN3_UART2 0x306 +-#define PERIPH_RSTEN3_UART3 0x307 +-#define PERIPH_RSTEN3_UART4 0x308 +-#define PERIPH_RSTEN3_SSP 0x309 +-#define PERIPH_RSTEN3_PWM 0x30a +-#define PERIPH_RSTEN3_BLPWM 0x30b +-#define PERIPH_RSTEN3_TSENSOR 0x30c +-#define PERIPH_RSTEN3_DAPB 0x312 +-#define PERIPH_RSTEN3_HKADC 0x313 +-#define PERIPH_RSTEN3_CODEC_SSI 0x314 +-#define PERIPH_RSTEN3_PMUSSI1 0x316 +-#define PERIPH_RSTEN8_RS0 0x400 +-#define PERIPH_RSTEN8_RS2 0x401 +-#define PERIPH_RSTEN8_RS3 0x402 +-#define PERIPH_RSTEN8_MS0 0x403 +-#define PERIPH_RSTEN8_MS2 0x405 +-#define PERIPH_RSTEN8_XG2RAM0 0x406 +-#define PERIPH_RSTEN8_X2SRAM_TZMA 0x407 +-#define PERIPH_RSTEN8_SRAM 0x408 +-#define PERIPH_RSTEN8_HARQ 0x40a +-#define PERIPH_RSTEN8_DDRC 0x40c +-#define PERIPH_RSTEN8_DDRC_APB 0x40d +-#define PERIPH_RSTEN8_DDRPACK_APB 0x40e +-#define PERIPH_RSTEN8_DDRT 0x411 +-#define PERIPH_RSDIST9_CARM_DAP 0x500 +-#define PERIPH_RSDIST9_CARM_ATB 0x501 +-#define PERIPH_RSDIST9_CARM_LBUS 0x502 +-#define PERIPH_RSDIST9_CARM_POR 0x503 +-#define PERIPH_RSDIST9_CARM_CORE 0x504 +-#define PERIPH_RSDIST9_CARM_DBG 0x505 +-#define PERIPH_RSDIST9_CARM_L2 0x506 +-#define PERIPH_RSDIST9_CARM_SOCDBG 0x507 +-#define PERIPH_RSDIST9_CARM_ETM 0x508 +- +-#define MEDIA_G3D 0 +-#define MEDIA_CODEC_VPU 2 +-#define MEDIA_CODEC_JPEG 3 +-#define MEDIA_ISP 4 +-#define MEDIA_ADE 5 +-#define MEDIA_MMU 6 +-#define MEDIA_XG2RAM1 7 +- +-#define AO_G3D 1 +-#define AO_CODECISP 2 +-#define AO_MCPU 4 +-#define AO_BBPHARQMEM 5 +-#define AO_HIFI 8 +-#define AO_ACPUSCUL2C 12 +- +-#endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/imx7-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/imx7-reset.h +deleted file mode 100644 +index a5b35b4754d0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/imx7-reset.h ++++ /dev/null +@@ -1,53 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2017 Impinj, Inc. +- * +- * Author: Andrey Smirnov +- */ +- +-#ifndef DT_BINDING_RESET_IMX7_H +-#define DT_BINDING_RESET_IMX7_H +- +-#define IMX7_RESET_A7_CORE_POR_RESET0 0 +-#define IMX7_RESET_A7_CORE_POR_RESET1 1 +-#define IMX7_RESET_A7_CORE_RESET0 2 +-#define IMX7_RESET_A7_CORE_RESET1 3 +-#define IMX7_RESET_A7_DBG_RESET0 4 +-#define IMX7_RESET_A7_DBG_RESET1 5 +-#define IMX7_RESET_A7_ETM_RESET0 6 +-#define IMX7_RESET_A7_ETM_RESET1 7 +-#define IMX7_RESET_A7_SOC_DBG_RESET 8 +-#define IMX7_RESET_A7_L2RESET 9 +-#define IMX7_RESET_SW_M4C_RST 10 +-#define IMX7_RESET_SW_M4P_RST 11 +-#define IMX7_RESET_EIM_RST 12 +-#define IMX7_RESET_HSICPHY_PORT_RST 13 +-#define IMX7_RESET_USBPHY1_POR 14 +-#define IMX7_RESET_USBPHY1_PORT_RST 15 +-#define IMX7_RESET_USBPHY2_POR 16 +-#define IMX7_RESET_USBPHY2_PORT_RST 17 +-#define IMX7_RESET_MIPI_PHY_MRST 18 +-#define IMX7_RESET_MIPI_PHY_SRST 19 +- +-/* +- * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN +- * and PCIEPHY_G_RST +- */ +-#define IMX7_RESET_PCIEPHY 20 +-#define IMX7_RESET_PCIEPHY_PERST 21 +- +-/* +- * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it +- * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht +- * of as one +- */ +-#define IMX7_RESET_PCIE_CTRL_APPS_EN 22 +-#define IMX7_RESET_DDRC_PRST 23 +-#define IMX7_RESET_DDRC_CORE_RST 24 +- +-#define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25 +- +-#define IMX7_RESET_NUM 26 +- +-#endif +- +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/imx8mp-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/imx8mp-reset.h +deleted file mode 100644 +index 2e8c9104b666..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/imx8mp-reset.h ++++ /dev/null +@@ -1,50 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2020 NXP +- */ +- +-#ifndef DT_BINDING_RESET_IMX8MP_H +-#define DT_BINDING_RESET_IMX8MP_H +- +-#define IMX8MP_RESET_A53_CORE_POR_RESET0 0 +-#define IMX8MP_RESET_A53_CORE_POR_RESET1 1 +-#define IMX8MP_RESET_A53_CORE_POR_RESET2 2 +-#define IMX8MP_RESET_A53_CORE_POR_RESET3 3 +-#define IMX8MP_RESET_A53_CORE_RESET0 4 +-#define IMX8MP_RESET_A53_CORE_RESET1 5 +-#define IMX8MP_RESET_A53_CORE_RESET2 6 +-#define IMX8MP_RESET_A53_CORE_RESET3 7 +-#define IMX8MP_RESET_A53_DBG_RESET0 8 +-#define IMX8MP_RESET_A53_DBG_RESET1 9 +-#define IMX8MP_RESET_A53_DBG_RESET2 10 +-#define IMX8MP_RESET_A53_DBG_RESET3 11 +-#define IMX8MP_RESET_A53_ETM_RESET0 12 +-#define IMX8MP_RESET_A53_ETM_RESET1 13 +-#define IMX8MP_RESET_A53_ETM_RESET2 14 +-#define IMX8MP_RESET_A53_ETM_RESET3 15 +-#define IMX8MP_RESET_A53_SOC_DBG_RESET 16 +-#define IMX8MP_RESET_A53_L2RESET 17 +-#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST 18 +-#define IMX8MP_RESET_OTG1_PHY_RESET 19 +-#define IMX8MP_RESET_OTG2_PHY_RESET 20 +-#define IMX8MP_RESET_SUPERMIX_RESET 21 +-#define IMX8MP_RESET_AUDIOMIX_RESET 22 +-#define IMX8MP_RESET_MLMIX_RESET 23 +-#define IMX8MP_RESET_PCIEPHY 24 +-#define IMX8MP_RESET_PCIEPHY_PERST 25 +-#define IMX8MP_RESET_PCIE_CTRL_APPS_EN 26 +-#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF 27 +-#define IMX8MP_RESET_HDMI_PHY_APB_RESET 28 +-#define IMX8MP_RESET_MEDIA_RESET 29 +-#define IMX8MP_RESET_GPU2D_RESET 30 +-#define IMX8MP_RESET_GPU3D_RESET 31 +-#define IMX8MP_RESET_GPU_RESET 32 +-#define IMX8MP_RESET_VPU_RESET 33 +-#define IMX8MP_RESET_VPU_G1_RESET 34 +-#define IMX8MP_RESET_VPU_G2_RESET 35 +-#define IMX8MP_RESET_VPUVC8KE_RESET 36 +-#define IMX8MP_RESET_NOC_RESET 37 +- +-#define IMX8MP_RESET_NUM 38 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/imx8mq-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/imx8mq-reset.h +deleted file mode 100644 +index 705870693ec2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/imx8mq-reset.h ++++ /dev/null +@@ -1,67 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2018 Zodiac Inflight Innovations +- * +- * Author: Andrey Smirnov +- */ +- +-#ifndef DT_BINDING_RESET_IMX8MQ_H +-#define DT_BINDING_RESET_IMX8MQ_H +- +-#define IMX8MQ_RESET_A53_CORE_POR_RESET0 0 +-#define IMX8MQ_RESET_A53_CORE_POR_RESET1 1 +-#define IMX8MQ_RESET_A53_CORE_POR_RESET2 2 +-#define IMX8MQ_RESET_A53_CORE_POR_RESET3 3 +-#define IMX8MQ_RESET_A53_CORE_RESET0 4 +-#define IMX8MQ_RESET_A53_CORE_RESET1 5 +-#define IMX8MQ_RESET_A53_CORE_RESET2 6 +-#define IMX8MQ_RESET_A53_CORE_RESET3 7 +-#define IMX8MQ_RESET_A53_DBG_RESET0 8 +-#define IMX8MQ_RESET_A53_DBG_RESET1 9 +-#define IMX8MQ_RESET_A53_DBG_RESET2 10 +-#define IMX8MQ_RESET_A53_DBG_RESET3 11 +-#define IMX8MQ_RESET_A53_ETM_RESET0 12 +-#define IMX8MQ_RESET_A53_ETM_RESET1 13 +-#define IMX8MQ_RESET_A53_ETM_RESET2 14 +-#define IMX8MQ_RESET_A53_ETM_RESET3 15 +-#define IMX8MQ_RESET_A53_SOC_DBG_RESET 16 +-#define IMX8MQ_RESET_A53_L2RESET 17 +-#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18 +-#define IMX8MQ_RESET_OTG1_PHY_RESET 19 +-#define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM/i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_DISP_RESET 31 +-#define IMX8MQ_RESET_GPU_RESET 32 +-#define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM/i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does NOT support */ +-#define IMX8MQ_RESET_SW_M4C_RST 50 +-#define IMX8MQ_RESET_SW_M4P_RST 51 +-#define IMX8MQ_RESET_M4_ENABLE 52 +- +-#define IMX8MQ_RESET_NUM 53 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/k210-rst.h b/scripts/dtc/include-prefixes/dt-bindings/reset/k210-rst.h +deleted file mode 100644 +index 883c1aed50e8..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/k210-rst.h ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright (C) 2019 Sean Anderson +- * Copyright (c) 2020 Western Digital Corporation or its affiliates. +- */ +-#ifndef RESET_K210_SYSCTL_H +-#define RESET_K210_SYSCTL_H +- +-/* +- * Kendryte K210 SoC system controller K210_SYSCTL_SOFT_RESET register bits. +- * Taken from Kendryte SDK (kendryte-standalone-sdk). +- */ +-#define K210_RST_ROM 0 +-#define K210_RST_DMA 1 +-#define K210_RST_AI 2 +-#define K210_RST_DVP 3 +-#define K210_RST_FFT 4 +-#define K210_RST_GPIO 5 +-#define K210_RST_SPI0 6 +-#define K210_RST_SPI1 7 +-#define K210_RST_SPI2 8 +-#define K210_RST_SPI3 9 +-#define K210_RST_I2S0 10 +-#define K210_RST_I2S1 11 +-#define K210_RST_I2S2 12 +-#define K210_RST_I2C0 13 +-#define K210_RST_I2C1 14 +-#define K210_RST_I2C2 15 +-#define K210_RST_UART1 16 +-#define K210_RST_UART2 17 +-#define K210_RST_UART3 18 +-#define K210_RST_AES 19 +-#define K210_RST_FPIOA 20 +-#define K210_RST_TIMER0 21 +-#define K210_RST_TIMER1 22 +-#define K210_RST_TIMER2 23 +-#define K210_RST_WDT0 24 +-#define K210_RST_WDT1 25 +-#define K210_RST_SHA 26 +-#define K210_RST_RTC 29 +- +-#endif /* RESET_K210_SYSCTL_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/mt2701-resets.h b/scripts/dtc/include-prefixes/dt-bindings/reset/mt2701-resets.h +deleted file mode 100644 +index 91e4200fd74c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/mt2701-resets.h ++++ /dev/null +@@ -1,85 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2015 MediaTek, Shunli Wang +- */ +- +-#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2701 +-#define _DT_BINDINGS_RESET_CONTROLLER_MT2701 +- +-/* INFRACFG resets */ +-#define MT2701_INFRA_EMI_REG_RST 0 +-#define MT2701_INFRA_DRAMC0_A0_RST 1 +-#define MT2701_INFRA_FHCTL_RST 2 +-#define MT2701_INFRA_APCIRQ_EINT_RST 3 +-#define MT2701_INFRA_APXGPT_RST 4 +-#define MT2701_INFRA_SCPSYS_RST 5 +-#define MT2701_INFRA_KP_RST 6 +-#define MT2701_INFRA_PMIC_WRAP_RST 7 +-#define MT2701_INFRA_MIPI_RST 8 +-#define MT2701_INFRA_IRRX_RST 9 +-#define MT2701_INFRA_CEC_RST 10 +-#define MT2701_INFRA_EMI_RST 32 +-#define MT2701_INFRA_DRAMC0_RST 34 +-#define MT2701_INFRA_TRNG_RST 37 +-#define MT2701_INFRA_SYSIRQ_RST 38 +- +-/* PERICFG resets */ +-#define MT2701_PERI_UART0_SW_RST 0 +-#define MT2701_PERI_UART1_SW_RST 1 +-#define MT2701_PERI_UART2_SW_RST 2 +-#define MT2701_PERI_UART3_SW_RST 3 +-#define MT2701_PERI_GCPU_SW_RST 5 +-#define MT2701_PERI_BTIF_SW_RST 6 +-#define MT2701_PERI_PWM_SW_RST 8 +-#define MT2701_PERI_AUXADC_SW_RST 10 +-#define MT2701_PERI_DMA_SW_RST 11 +-#define MT2701_PERI_NFI_SW_RST 14 +-#define MT2701_PERI_NLI_SW_RST 15 +-#define MT2701_PERI_THERM_SW_RST 16 +-#define MT2701_PERI_MSDC2_SW_RST 17 +-#define MT2701_PERI_MSDC0_SW_RST 19 +-#define MT2701_PERI_MSDC1_SW_RST 20 +-#define MT2701_PERI_I2C0_SW_RST 22 +-#define MT2701_PERI_I2C1_SW_RST 23 +-#define MT2701_PERI_I2C2_SW_RST 24 +-#define MT2701_PERI_I2C3_SW_RST 25 +-#define MT2701_PERI_USB_SW_RST 28 +-#define MT2701_PERI_ETH_SW_RST 29 +-#define MT2701_PERI_SPI0_SW_RST 33 +- +-/* TOPRGU resets */ +-#define MT2701_TOPRGU_INFRA_RST 0 +-#define MT2701_TOPRGU_MM_RST 1 +-#define MT2701_TOPRGU_MFG_RST 2 +-#define MT2701_TOPRGU_ETHDMA_RST 3 +-#define MT2701_TOPRGU_VDEC_RST 4 +-#define MT2701_TOPRGU_VENC_IMG_RST 5 +-#define MT2701_TOPRGU_DDRPHY_RST 6 +-#define MT2701_TOPRGU_MD_RST 7 +-#define MT2701_TOPRGU_INFRA_AO_RST 8 +-#define MT2701_TOPRGU_CONN_RST 9 +-#define MT2701_TOPRGU_APMIXED_RST 10 +-#define MT2701_TOPRGU_HIFSYS_RST 11 +-#define MT2701_TOPRGU_CONN_MCU_RST 12 +-#define MT2701_TOPRGU_BDP_DISP_RST 13 +- +-/* HIFSYS resets */ +-#define MT2701_HIFSYS_UHOST0_RST 3 +-#define MT2701_HIFSYS_UHOST1_RST 4 +-#define MT2701_HIFSYS_UPHY0_RST 21 +-#define MT2701_HIFSYS_UPHY1_RST 22 +-#define MT2701_HIFSYS_PCIE0_RST 24 +-#define MT2701_HIFSYS_PCIE1_RST 25 +-#define MT2701_HIFSYS_PCIE2_RST 26 +- +-/* ETHSYS resets */ +-#define MT2701_ETHSYS_SYS_RST 0 +-#define MT2701_ETHSYS_MCM_RST 2 +-#define MT2701_ETHSYS_FE_RST 6 +-#define MT2701_ETHSYS_GMAC_RST 23 +-#define MT2701_ETHSYS_PPE_RST 31 +- +-/* G3DSYS resets */ +-#define MT2701_G3DSYS_CORE_RST 0 +- +-#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/mt7622-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/mt7622-reset.h +deleted file mode 100644 +index da0d1ae81cb5..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/mt7622-reset.h ++++ /dev/null +@@ -1,86 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2017 MediaTek Inc. +- * Author: Sean Wang +- */ +- +-#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7622 +-#define _DT_BINDINGS_RESET_CONTROLLER_MT7622 +- +-/* INFRACFG resets */ +-#define MT7622_INFRA_EMI_REG_RST 0 +-#define MT7622_INFRA_DRAMC0_A0_RST 1 +-#define MT7622_INFRA_APCIRQ_EINT_RST 3 +-#define MT7622_INFRA_APXGPT_RST 4 +-#define MT7622_INFRA_SCPSYS_RST 5 +-#define MT7622_INFRA_PMIC_WRAP_RST 7 +-#define MT7622_INFRA_IRRX_RST 9 +-#define MT7622_INFRA_EMI_RST 16 +-#define MT7622_INFRA_WED0_RST 17 +-#define MT7622_INFRA_DRAMC_RST 18 +-#define MT7622_INFRA_CCI_INTF_RST 19 +-#define MT7622_INFRA_TRNG_RST 21 +-#define MT7622_INFRA_SYSIRQ_RST 22 +-#define MT7622_INFRA_WED1_RST 25 +- +-/* PERICFG Subsystem resets */ +-#define MT7622_PERI_UART0_SW_RST 0 +-#define MT7622_PERI_UART1_SW_RST 1 +-#define MT7622_PERI_UART2_SW_RST 2 +-#define MT7622_PERI_UART3_SW_RST 3 +-#define MT7622_PERI_UART4_SW_RST 4 +-#define MT7622_PERI_BTIF_SW_RST 6 +-#define MT7622_PERI_PWM_SW_RST 8 +-#define MT7622_PERI_AUXADC_SW_RST 10 +-#define MT7622_PERI_DMA_SW_RST 11 +-#define MT7622_PERI_IRTX_SW_RST 13 +-#define MT7622_PERI_NFI_SW_RST 14 +-#define MT7622_PERI_THERM_SW_RST 16 +-#define MT7622_PERI_MSDC0_SW_RST 19 +-#define MT7622_PERI_MSDC1_SW_RST 20 +-#define MT7622_PERI_I2C0_SW_RST 22 +-#define MT7622_PERI_I2C1_SW_RST 23 +-#define MT7622_PERI_I2C2_SW_RST 24 +-#define MT7622_PERI_SPI0_SW_RST 33 +-#define MT7622_PERI_SPI1_SW_RST 34 +-#define MT7622_PERI_FLASHIF_SW_RST 36 +- +-/* TOPRGU resets */ +-#define MT7622_TOPRGU_INFRA_RST 0 +-#define MT7622_TOPRGU_ETHDMA_RST 1 +-#define MT7622_TOPRGU_DDRPHY_RST 6 +-#define MT7622_TOPRGU_INFRA_AO_RST 8 +-#define MT7622_TOPRGU_CONN_RST 9 +-#define MT7622_TOPRGU_APMIXED_RST 10 +-#define MT7622_TOPRGU_CONN_MCU_RST 12 +- +-/* PCIe/SATA Subsystem resets */ +-#define MT7622_SATA_PHY_REG_RST 12 +-#define MT7622_SATA_PHY_SW_RST 13 +-#define MT7622_SATA_AXI_BUS_RST 15 +-#define MT7622_PCIE1_CORE_RST 19 +-#define MT7622_PCIE1_MMIO_RST 20 +-#define MT7622_PCIE1_HRST 21 +-#define MT7622_PCIE1_USER_RST 22 +-#define MT7622_PCIE1_PIPE_RST 23 +-#define MT7622_PCIE0_CORE_RST 27 +-#define MT7622_PCIE0_MMIO_RST 28 +-#define MT7622_PCIE0_HRST 29 +-#define MT7622_PCIE0_USER_RST 30 +-#define MT7622_PCIE0_PIPE_RST 31 +- +-/* SSUSB Subsystem resets */ +-#define MT7622_SSUSB_PHY_PWR_RST 3 +-#define MT7622_SSUSB_MAC_PWR_RST 4 +- +-/* ETHSYS Subsystem resets */ +-#define MT7622_ETHSYS_SYS_RST 0 +-#define MT7622_ETHSYS_MCM_RST 2 +-#define MT7622_ETHSYS_HSDMA_RST 5 +-#define MT7622_ETHSYS_FE_RST 6 +-#define MT7622_ETHSYS_GMAC_RST 23 +-#define MT7622_ETHSYS_EPHY_RST 24 +-#define MT7622_ETHSYS_CRYPTO_RST 29 +-#define MT7622_ETHSYS_PPE_RST 31 +- +-#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7622 */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/mt7629-resets.h b/scripts/dtc/include-prefixes/dt-bindings/reset/mt7629-resets.h +deleted file mode 100644 +index 6bb85734f68d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/mt7629-resets.h ++++ /dev/null +@@ -1,71 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2019 MediaTek Inc. +- */ +- +-#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7629 +-#define _DT_BINDINGS_RESET_CONTROLLER_MT7629 +- +-/* INFRACFG resets */ +-#define MT7629_INFRA_EMI_MPU_RST 0 +-#define MT7629_INFRA_UART5_RST 2 +-#define MT7629_INFRA_CIRQ_EINT_RST 3 +-#define MT7629_INFRA_APXGPT_RST 4 +-#define MT7629_INFRA_SCPSYS_RST 5 +-#define MT7629_INFRA_KP_RST 6 +-#define MT7629_INFRA_SPI1_RST 7 +-#define MT7629_INFRA_SPI4_RST 8 +-#define MT7629_INFRA_SYSTIMER_RST 9 +-#define MT7629_INFRA_IRRX_RST 10 +-#define MT7629_INFRA_AO_BUS_RST 16 +-#define MT7629_INFRA_EMI_RST 32 +-#define MT7629_INFRA_APMIXED_RST 35 +-#define MT7629_INFRA_MIPI_RST 36 +-#define MT7629_INFRA_TRNG_RST 37 +-#define MT7629_INFRA_SYSCIRQ_RST 38 +-#define MT7629_INFRA_MIPI_CSI_RST 39 +-#define MT7629_INFRA_GCE_FAXI_RST 40 +-#define MT7629_INFRA_I2C_SRAM_RST 41 +-#define MT7629_INFRA_IOMMU_RST 47 +- +-/* PERICFG resets */ +-#define MT7629_PERI_UART0_SW_RST 0 +-#define MT7629_PERI_UART1_SW_RST 1 +-#define MT7629_PERI_UART2_SW_RST 2 +-#define MT7629_PERI_BTIF_SW_RST 6 +-#define MT7629_PERI_PWN_SW_RST 8 +-#define MT7629_PERI_DMA_SW_RST 11 +-#define MT7629_PERI_NFI_SW_RST 14 +-#define MT7629_PERI_I2C0_SW_RST 22 +-#define MT7629_PERI_SPI0_SW_RST 33 +-#define MT7629_PERI_SPI1_SW_RST 34 +-#define MT7629_PERI_FLASHIF_SW_RST 36 +- +-/* PCIe Subsystem resets */ +-#define MT7629_PCIE1_CORE_RST 19 +-#define MT7629_PCIE1_MMIO_RST 20 +-#define MT7629_PCIE1_HRST 21 +-#define MT7629_PCIE1_USER_RST 22 +-#define MT7629_PCIE1_PIPE_RST 23 +-#define MT7629_PCIE0_CORE_RST 27 +-#define MT7629_PCIE0_MMIO_RST 28 +-#define MT7629_PCIE0_HRST 29 +-#define MT7629_PCIE0_USER_RST 30 +-#define MT7629_PCIE0_PIPE_RST 31 +- +-/* SSUSB Subsystem resets */ +-#define MT7629_SSUSB_PHY_PWR_RST 3 +-#define MT7629_SSUSB_MAC_PWR_RST 4 +- +-/* ETH Subsystem resets */ +-#define MT7629_ETHSYS_SYS_RST 0 +-#define MT7629_ETHSYS_MCM_RST 2 +-#define MT7629_ETHSYS_HSDMA_RST 5 +-#define MT7629_ETHSYS_FE_RST 6 +-#define MT7629_ETHSYS_ESW_RST 16 +-#define MT7629_ETHSYS_GMAC_RST 23 +-#define MT7629_ETHSYS_EPHY_RST 24 +-#define MT7629_ETHSYS_CRYPTO_RST 29 +-#define MT7629_ETHSYS_PPE_RST 31 +- +-#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7629 */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/mt8135-resets.h b/scripts/dtc/include-prefixes/dt-bindings/reset/mt8135-resets.h +deleted file mode 100644 +index 8c060d08716b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/mt8135-resets.h ++++ /dev/null +@@ -1,56 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014 MediaTek Inc. +- * Author: Flora Fu, MediaTek +- */ +- +-#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135 +-#define _DT_BINDINGS_RESET_CONTROLLER_MT8135 +- +-/* INFRACFG resets */ +-#define MT8135_INFRA_EMI_REG_RST 0 +-#define MT8135_INFRA_DRAMC0_A0_RST 1 +-#define MT8135_INFRA_CCIF0_RST 2 +-#define MT8135_INFRA_APCIRQ_EINT_RST 3 +-#define MT8135_INFRA_APXGPT_RST 4 +-#define MT8135_INFRA_SCPSYS_RST 5 +-#define MT8135_INFRA_CCIF1_RST 6 +-#define MT8135_INFRA_PMIC_WRAP_RST 7 +-#define MT8135_INFRA_KP_RST 8 +-#define MT8135_INFRA_EMI_RST 32 +-#define MT8135_INFRA_DRAMC0_RST 34 +-#define MT8135_INFRA_SMI_RST 35 +-#define MT8135_INFRA_M4U_RST 36 +- +-/* PERICFG resets */ +-#define MT8135_PERI_UART0_SW_RST 0 +-#define MT8135_PERI_UART1_SW_RST 1 +-#define MT8135_PERI_UART2_SW_RST 2 +-#define MT8135_PERI_UART3_SW_RST 3 +-#define MT8135_PERI_IRDA_SW_RST 4 +-#define MT8135_PERI_PTP_SW_RST 5 +-#define MT8135_PERI_AP_HIF_SW_RST 6 +-#define MT8135_PERI_GPCU_SW_RST 7 +-#define MT8135_PERI_MD_HIF_SW_RST 8 +-#define MT8135_PERI_NLI_SW_RST 9 +-#define MT8135_PERI_AUXADC_SW_RST 10 +-#define MT8135_PERI_DMA_SW_RST 11 +-#define MT8135_PERI_NFI_SW_RST 14 +-#define MT8135_PERI_PWM_SW_RST 15 +-#define MT8135_PERI_THERM_SW_RST 16 +-#define MT8135_PERI_MSDC0_SW_RST 17 +-#define MT8135_PERI_MSDC1_SW_RST 18 +-#define MT8135_PERI_MSDC2_SW_RST 19 +-#define MT8135_PERI_MSDC3_SW_RST 20 +-#define MT8135_PERI_I2C0_SW_RST 22 +-#define MT8135_PERI_I2C1_SW_RST 23 +-#define MT8135_PERI_I2C2_SW_RST 24 +-#define MT8135_PERI_I2C3_SW_RST 25 +-#define MT8135_PERI_I2C4_SW_RST 26 +-#define MT8135_PERI_I2C5_SW_RST 27 +-#define MT8135_PERI_I2C6_SW_RST 28 +-#define MT8135_PERI_USB_SW_RST 29 +-#define MT8135_PERI_SPI1_SW_RST 33 +-#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34 +- +-#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/mt8173-resets.h b/scripts/dtc/include-prefixes/dt-bindings/reset/mt8173-resets.h +deleted file mode 100644 +index ba8636eda5ae..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/mt8173-resets.h ++++ /dev/null +@@ -1,55 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014 MediaTek Inc. +- * Author: Flora Fu, MediaTek +- */ +- +-#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173 +-#define _DT_BINDINGS_RESET_CONTROLLER_MT8173 +- +-/* INFRACFG resets */ +-#define MT8173_INFRA_EMI_REG_RST 0 +-#define MT8173_INFRA_DRAMC0_A0_RST 1 +-#define MT8173_INFRA_APCIRQ_EINT_RST 3 +-#define MT8173_INFRA_APXGPT_RST 4 +-#define MT8173_INFRA_SCPSYS_RST 5 +-#define MT8173_INFRA_KP_RST 6 +-#define MT8173_INFRA_PMIC_WRAP_RST 7 +-#define MT8173_INFRA_MPIP_RST 8 +-#define MT8173_INFRA_CEC_RST 9 +-#define MT8173_INFRA_EMI_RST 32 +-#define MT8173_INFRA_DRAMC0_RST 34 +-#define MT8173_INFRA_APMIXEDSYS_RST 35 +-#define MT8173_INFRA_MIPI_DSI_RST 36 +-#define MT8173_INFRA_TRNG_RST 37 +-#define MT8173_INFRA_SYSIRQ_RST 38 +-#define MT8173_INFRA_MIPI_CSI_RST 39 +-#define MT8173_INFRA_GCE_FAXI_RST 40 +-#define MT8173_INFRA_MMIOMMURST 47 +- +- +-/* PERICFG resets */ +-#define MT8173_PERI_UART0_SW_RST 0 +-#define MT8173_PERI_UART1_SW_RST 1 +-#define MT8173_PERI_UART2_SW_RST 2 +-#define MT8173_PERI_UART3_SW_RST 3 +-#define MT8173_PERI_IRRX_SW_RST 4 +-#define MT8173_PERI_PWM_SW_RST 8 +-#define MT8173_PERI_AUXADC_SW_RST 10 +-#define MT8173_PERI_DMA_SW_RST 11 +-#define MT8173_PERI_I2C6_SW_RST 13 +-#define MT8173_PERI_NFI_SW_RST 14 +-#define MT8173_PERI_THERM_SW_RST 16 +-#define MT8173_PERI_MSDC2_SW_RST 17 +-#define MT8173_PERI_MSDC3_SW_RST 18 +-#define MT8173_PERI_MSDC0_SW_RST 19 +-#define MT8173_PERI_MSDC1_SW_RST 20 +-#define MT8173_PERI_I2C0_SW_RST 22 +-#define MT8173_PERI_I2C1_SW_RST 23 +-#define MT8173_PERI_I2C2_SW_RST 24 +-#define MT8173_PERI_I2C3_SW_RST 25 +-#define MT8173_PERI_I2C4_SW_RST 26 +-#define MT8173_PERI_HDMI_SW_RST 29 +-#define MT8173_PERI_SPI0_SW_RST 33 +- +-#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/mt8195-resets.h b/scripts/dtc/include-prefixes/dt-bindings/reset/mt8195-resets.h +deleted file mode 100644 +index a26bccc8b957..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/mt8195-resets.h ++++ /dev/null +@@ -1,29 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/ +-/* +- * Copyright (c) 2021 MediaTek Inc. +- * Author: Christine Zhu +- */ +- +-#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 +-#define _DT_BINDINGS_RESET_CONTROLLER_MT8195 +- +-#define MT8195_TOPRGU_CONN_MCU_SW_RST 0 +-#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 +-#define MT8195_TOPRGU_APU_SW_RST 2 +-#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6 +-#define MT8195_TOPRGU_MMSYS_SW_RST 7 +-#define MT8195_TOPRGU_MFG_SW_RST 8 +-#define MT8195_TOPRGU_VENC_SW_RST 9 +-#define MT8195_TOPRGU_VDEC_SW_RST 10 +-#define MT8195_TOPRGU_IMG_SW_RST 11 +-#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13 +-#define MT8195_TOPRGU_AUDIO_SW_RST 14 +-#define MT8195_TOPRGU_CAMSYS_SW_RST 15 +-#define MT8195_TOPRGU_EDPTX_SW_RST 16 +-#define MT8195_TOPRGU_ADSPSYS_SW_RST 21 +-#define MT8195_TOPRGU_DPTX_SW_RST 22 +-#define MT8195_TOPRGU_SPMI_MST_SW_RST 23 +- +-#define MT8195_TOPRGU_SW_RST_NUM 16 +- +-#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/nuvoton,npcm7xx-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/nuvoton,npcm7xx-reset.h +deleted file mode 100644 +index df088e68a9ba..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/nuvoton,npcm7xx-reset.h ++++ /dev/null +@@ -1,91 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-// Copyright (c) 2019 Nuvoton Technology corporation. +- +-#ifndef _DT_BINDINGS_NPCM7XX_RESET_H +-#define _DT_BINDINGS_NPCM7XX_RESET_H +- +-#define NPCM7XX_RESET_IPSRST1 0x20 +-#define NPCM7XX_RESET_IPSRST2 0x24 +-#define NPCM7XX_RESET_IPSRST3 0x34 +- +-/* Reset lines on IP1 reset module (NPCM7XX_RESET_IPSRST1) */ +-#define NPCM7XX_RESET_FIU3 1 +-#define NPCM7XX_RESET_UDC1 5 +-#define NPCM7XX_RESET_EMC1 6 +-#define NPCM7XX_RESET_UART_2_3 7 +-#define NPCM7XX_RESET_UDC2 8 +-#define NPCM7XX_RESET_PECI 9 +-#define NPCM7XX_RESET_AES 10 +-#define NPCM7XX_RESET_UART_0_1 11 +-#define NPCM7XX_RESET_MC 12 +-#define NPCM7XX_RESET_SMB2 13 +-#define NPCM7XX_RESET_SMB3 14 +-#define NPCM7XX_RESET_SMB4 15 +-#define NPCM7XX_RESET_SMB5 16 +-#define NPCM7XX_RESET_PWM_M0 18 +-#define NPCM7XX_RESET_TIMER_0_4 19 +-#define NPCM7XX_RESET_TIMER_5_9 20 +-#define NPCM7XX_RESET_EMC2 21 +-#define NPCM7XX_RESET_UDC4 22 +-#define NPCM7XX_RESET_UDC5 23 +-#define NPCM7XX_RESET_UDC6 24 +-#define NPCM7XX_RESET_UDC3 25 +-#define NPCM7XX_RESET_ADC 27 +-#define NPCM7XX_RESET_SMB6 28 +-#define NPCM7XX_RESET_SMB7 29 +-#define NPCM7XX_RESET_SMB0 30 +-#define NPCM7XX_RESET_SMB1 31 +- +-/* Reset lines on IP2 reset module (NPCM7XX_RESET_IPSRST2) */ +-#define NPCM7XX_RESET_MFT0 0 +-#define NPCM7XX_RESET_MFT1 1 +-#define NPCM7XX_RESET_MFT2 2 +-#define NPCM7XX_RESET_MFT3 3 +-#define NPCM7XX_RESET_MFT4 4 +-#define NPCM7XX_RESET_MFT5 5 +-#define NPCM7XX_RESET_MFT6 6 +-#define NPCM7XX_RESET_MFT7 7 +-#define NPCM7XX_RESET_MMC 8 +-#define NPCM7XX_RESET_SDHC 9 +-#define NPCM7XX_RESET_GFX_SYS 10 +-#define NPCM7XX_RESET_AHB_PCIBRG 11 +-#define NPCM7XX_RESET_VDMA 12 +-#define NPCM7XX_RESET_ECE 13 +-#define NPCM7XX_RESET_VCD 14 +-#define NPCM7XX_RESET_OTP 16 +-#define NPCM7XX_RESET_SIOX1 18 +-#define NPCM7XX_RESET_SIOX2 19 +-#define NPCM7XX_RESET_3DES 21 +-#define NPCM7XX_RESET_PSPI1 22 +-#define NPCM7XX_RESET_PSPI2 23 +-#define NPCM7XX_RESET_GMAC2 25 +-#define NPCM7XX_RESET_USB_HOST 26 +-#define NPCM7XX_RESET_GMAC1 28 +-#define NPCM7XX_RESET_CP 31 +- +-/* Reset lines on IP3 reset module (NPCM7XX_RESET_IPSRST3) */ +-#define NPCM7XX_RESET_PWM_M1 0 +-#define NPCM7XX_RESET_SMB12 1 +-#define NPCM7XX_RESET_SPIX 2 +-#define NPCM7XX_RESET_SMB13 3 +-#define NPCM7XX_RESET_UDC0 4 +-#define NPCM7XX_RESET_UDC7 5 +-#define NPCM7XX_RESET_UDC8 6 +-#define NPCM7XX_RESET_UDC9 7 +-#define NPCM7XX_RESET_PCI_MAILBOX 9 +-#define NPCM7XX_RESET_SMB14 12 +-#define NPCM7XX_RESET_SHA 13 +-#define NPCM7XX_RESET_SEC_ECC 14 +-#define NPCM7XX_RESET_PCIE_RC 15 +-#define NPCM7XX_RESET_TIMER_10_14 16 +-#define NPCM7XX_RESET_RNG 17 +-#define NPCM7XX_RESET_SMB15 18 +-#define NPCM7XX_RESET_SMB8 19 +-#define NPCM7XX_RESET_SMB9 20 +-#define NPCM7XX_RESET_SMB10 21 +-#define NPCM7XX_RESET_SMB11 22 +-#define NPCM7XX_RESET_ESPI 23 +-#define NPCM7XX_RESET_USB_PHY_1 24 +-#define NPCM7XX_RESET_USB_PHY_2 25 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/oxsemi,ox810se.h b/scripts/dtc/include-prefixes/dt-bindings/reset/oxsemi,ox810se.h +deleted file mode 100644 +index e943187e6527..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/oxsemi,ox810se.h ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2016 Neil Armstrong +- */ +- +-#ifndef DT_RESET_OXSEMI_OX810SE_H +-#define DT_RESET_OXSEMI_OX810SE_H +- +-#define RESET_ARM 0 +-#define RESET_COPRO 1 +-/* Reserved 2 */ +-/* Reserved 3 */ +-#define RESET_USBHS 4 +-#define RESET_USBHSPHY 5 +-#define RESET_MAC 6 +-#define RESET_PCI 7 +-#define RESET_DMA 8 +-#define RESET_DPE 9 +-#define RESET_DDR 10 +-#define RESET_SATA 11 +-#define RESET_SATA_LINK 12 +-#define RESET_SATA_PHY 13 +- /* Reserved 14 */ +-#define RESET_NAND 15 +-#define RESET_GPIO 16 +-#define RESET_UART1 17 +-#define RESET_UART2 18 +-#define RESET_MISC 19 +-#define RESET_I2S 20 +-#define RESET_AHB_MON 21 +-#define RESET_UART3 22 +-#define RESET_UART4 23 +-#define RESET_SGDMA 24 +-/* Reserved 25 */ +-/* Reserved 26 */ +-/* Reserved 27 */ +-/* Reserved 28 */ +-/* Reserved 29 */ +-/* Reserved 30 */ +-#define RESET_BUS 31 +- +-#endif /* DT_RESET_OXSEMI_OX810SE_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/oxsemi,ox820.h b/scripts/dtc/include-prefixes/dt-bindings/reset/oxsemi,ox820.h +deleted file mode 100644 +index 54b58e09c1c0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/oxsemi,ox820.h ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (C) 2016 Neil Armstrong +- */ +- +-#ifndef DT_RESET_OXSEMI_OX820_H +-#define DT_RESET_OXSEMI_OX820_H +- +-#define RESET_SCU 0 +-#define RESET_LEON 1 +-#define RESET_ARM0 2 +-#define RESET_ARM1 3 +-#define RESET_USBHS 4 +-#define RESET_USBPHYA 5 +-#define RESET_MAC 6 +-#define RESET_PCIEA 7 +-#define RESET_SGDMA 8 +-#define RESET_CIPHER 9 +-#define RESET_DDR 10 +-#define RESET_SATA 11 +-#define RESET_SATA_LINK 12 +-#define RESET_SATA_PHY 13 +-#define RESET_PCIEPHY 14 +-#define RESET_NAND 15 +-#define RESET_GPIO 16 +-#define RESET_UART1 17 +-#define RESET_UART2 18 +-#define RESET_MISC 19 +-#define RESET_I2S 20 +-#define RESET_SD 21 +-#define RESET_MAC_2 22 +-#define RESET_PCIEB 23 +-#define RESET_VIDEO 24 +-#define RESET_DDR_PHY 25 +-#define RESET_USBPHYB 26 +-#define RESET_USBDEV 27 +-/* Reserved 29 */ +-#define RESET_ARMDBG 29 +-#define RESET_PLLA 30 +-#define RESET_PLLB 31 +- +-#endif /* DT_RESET_OXSEMI_OX820_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/pistachio-resets.h b/scripts/dtc/include-prefixes/dt-bindings/reset/pistachio-resets.h +deleted file mode 100644 +index 5bb4dd0d6377..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/pistachio-resets.h ++++ /dev/null +@@ -1,37 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for the reset controller +- * present in the Pistachio SoC +- */ +- +-#ifndef _PISTACHIO_RESETS_H +-#define _PISTACHIO_RESETS_H +- +-#define PISTACHIO_RESET_I2C0 0 +-#define PISTACHIO_RESET_I2C1 1 +-#define PISTACHIO_RESET_I2C2 2 +-#define PISTACHIO_RESET_I2C3 3 +-#define PISTACHIO_RESET_I2S_IN 4 +-#define PISTACHIO_RESET_PRL_OUT 5 +-#define PISTACHIO_RESET_SPDIF_OUT 6 +-#define PISTACHIO_RESET_SPI 7 +-#define PISTACHIO_RESET_PWM_PDM 8 +-#define PISTACHIO_RESET_UART0 9 +-#define PISTACHIO_RESET_UART1 10 +-#define PISTACHIO_RESET_QSPI 11 +-#define PISTACHIO_RESET_MDC 12 +-#define PISTACHIO_RESET_SDHOST 13 +-#define PISTACHIO_RESET_ETHERNET 14 +-#define PISTACHIO_RESET_IR 15 +-#define PISTACHIO_RESET_HASH 16 +-#define PISTACHIO_RESET_TIMER 17 +-#define PISTACHIO_RESET_I2S_OUT 18 +-#define PISTACHIO_RESET_SPDIF_IN 19 +-#define PISTACHIO_RESET_EVT 20 +-#define PISTACHIO_RESET_USB_H 21 +-#define PISTACHIO_RESET_USB_PR 22 +-#define PISTACHIO_RESET_USB_PHY_PR 23 +-#define PISTACHIO_RESET_USB_PHY_PON 24 +-#define PISTACHIO_RESET_MAX 24 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-apq8084.h b/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-apq8084.h +deleted file mode 100644 +index e76be38342c9..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-apq8084.h ++++ /dev/null +@@ -1,101 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_RESET_APQ_GCC_8084_H +-#define _DT_BINDINGS_RESET_APQ_GCC_8084_H +- +-#define GCC_SYSTEM_NOC_BCR 0 +-#define GCC_CONFIG_NOC_BCR 1 +-#define GCC_PERIPH_NOC_BCR 2 +-#define GCC_IMEM_BCR 3 +-#define GCC_MMSS_BCR 4 +-#define GCC_QDSS_BCR 5 +-#define GCC_USB_30_BCR 6 +-#define GCC_USB3_PHY_BCR 7 +-#define GCC_USB_HS_HSIC_BCR 8 +-#define GCC_USB_HS_BCR 9 +-#define GCC_USB2A_PHY_BCR 10 +-#define GCC_USB2B_PHY_BCR 11 +-#define GCC_SDCC1_BCR 12 +-#define GCC_SDCC2_BCR 13 +-#define GCC_SDCC3_BCR 14 +-#define GCC_SDCC4_BCR 15 +-#define GCC_BLSP1_BCR 16 +-#define GCC_BLSP1_QUP1_BCR 17 +-#define GCC_BLSP1_UART1_BCR 18 +-#define GCC_BLSP1_QUP2_BCR 19 +-#define GCC_BLSP1_UART2_BCR 20 +-#define GCC_BLSP1_QUP3_BCR 21 +-#define GCC_BLSP1_UART3_BCR 22 +-#define GCC_BLSP1_QUP4_BCR 23 +-#define GCC_BLSP1_UART4_BCR 24 +-#define GCC_BLSP1_QUP5_BCR 25 +-#define GCC_BLSP1_UART5_BCR 26 +-#define GCC_BLSP1_QUP6_BCR 27 +-#define GCC_BLSP1_UART6_BCR 28 +-#define GCC_BLSP2_BCR 29 +-#define GCC_BLSP2_QUP1_BCR 30 +-#define GCC_BLSP2_UART1_BCR 31 +-#define GCC_BLSP2_QUP2_BCR 32 +-#define GCC_BLSP2_UART2_BCR 33 +-#define GCC_BLSP2_QUP3_BCR 34 +-#define GCC_BLSP2_UART3_BCR 35 +-#define GCC_BLSP2_QUP4_BCR 36 +-#define GCC_BLSP2_UART4_BCR 37 +-#define GCC_BLSP2_QUP5_BCR 38 +-#define GCC_BLSP2_UART5_BCR 39 +-#define GCC_BLSP2_QUP6_BCR 40 +-#define GCC_BLSP2_UART6_BCR 41 +-#define GCC_PDM_BCR 42 +-#define GCC_PRNG_BCR 43 +-#define GCC_BAM_DMA_BCR 44 +-#define GCC_TSIF_BCR 45 +-#define GCC_TCSR_BCR 46 +-#define GCC_BOOT_ROM_BCR 47 +-#define GCC_MSG_RAM_BCR 48 +-#define GCC_TLMM_BCR 49 +-#define GCC_MPM_BCR 50 +-#define GCC_MPM_AHB_RESET 51 +-#define GCC_MPM_NON_AHB_RESET 52 +-#define GCC_SEC_CTRL_BCR 53 +-#define GCC_SPMI_BCR 54 +-#define GCC_SPDM_BCR 55 +-#define GCC_CE1_BCR 56 +-#define GCC_CE2_BCR 57 +-#define GCC_BIMC_BCR 58 +-#define GCC_SNOC_BUS_TIMEOUT0_BCR 59 +-#define GCC_SNOC_BUS_TIMEOUT2_BCR 60 +-#define GCC_PNOC_BUS_TIMEOUT0_BCR 61 +-#define GCC_PNOC_BUS_TIMEOUT1_BCR 62 +-#define GCC_PNOC_BUS_TIMEOUT2_BCR 63 +-#define GCC_PNOC_BUS_TIMEOUT3_BCR 64 +-#define GCC_PNOC_BUS_TIMEOUT4_BCR 65 +-#define GCC_CNOC_BUS_TIMEOUT0_BCR 66 +-#define GCC_CNOC_BUS_TIMEOUT1_BCR 67 +-#define GCC_CNOC_BUS_TIMEOUT2_BCR 68 +-#define GCC_CNOC_BUS_TIMEOUT3_BCR 69 +-#define GCC_CNOC_BUS_TIMEOUT4_BCR 70 +-#define GCC_CNOC_BUS_TIMEOUT5_BCR 71 +-#define GCC_CNOC_BUS_TIMEOUT6_BCR 72 +-#define GCC_DEHR_BCR 73 +-#define GCC_RBCPR_BCR 74 +-#define GCC_MSS_RESTART 75 +-#define GCC_LPASS_RESTART 76 +-#define GCC_WCSS_RESTART 77 +-#define GCC_VENUS_RESTART 78 +-#define GCC_COPSS_SMMU_BCR 79 +-#define GCC_SPSS_BCR 80 +-#define GCC_PCIE_0_BCR 81 +-#define GCC_PCIE_0_PHY_BCR 82 +-#define GCC_PCIE_1_BCR 83 +-#define GCC_PCIE_1_PHY_BCR 84 +-#define GCC_USB_30_SEC_BCR 85 +-#define GCC_USB3_SEC_PHY_BCR 86 +-#define GCC_SATA_BCR 87 +-#define GCC_CE3_BCR 88 +-#define GCC_UFS_BCR 89 +-#define GCC_USB30_PHY_COM_BCR 90 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-ipq6018.h b/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-ipq6018.h +deleted file mode 100644 +index 02a220ad0105..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-ipq6018.h ++++ /dev/null +@@ -1,157 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2018, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_RESET_IPQ_GCC_6018_H +-#define _DT_BINDINGS_RESET_IPQ_GCC_6018_H +- +-#define GCC_BLSP1_BCR 0 +-#define GCC_BLSP1_QUP1_BCR 1 +-#define GCC_BLSP1_UART1_BCR 2 +-#define GCC_BLSP1_QUP2_BCR 3 +-#define GCC_BLSP1_UART2_BCR 4 +-#define GCC_BLSP1_QUP3_BCR 5 +-#define GCC_BLSP1_UART3_BCR 6 +-#define GCC_BLSP1_QUP4_BCR 7 +-#define GCC_BLSP1_UART4_BCR 8 +-#define GCC_BLSP1_QUP5_BCR 9 +-#define GCC_BLSP1_UART5_BCR 10 +-#define GCC_BLSP1_QUP6_BCR 11 +-#define GCC_BLSP1_UART6_BCR 12 +-#define GCC_IMEM_BCR 13 +-#define GCC_SMMU_BCR 14 +-#define GCC_APSS_TCU_BCR 15 +-#define GCC_SMMU_XPU_BCR 16 +-#define GCC_PCNOC_TBU_BCR 17 +-#define GCC_SMMU_CFG_BCR 18 +-#define GCC_PRNG_BCR 19 +-#define GCC_BOOT_ROM_BCR 20 +-#define GCC_CRYPTO_BCR 21 +-#define GCC_WCSS_BCR 22 +-#define GCC_WCSS_Q6_BCR 23 +-#define GCC_NSS_BCR 24 +-#define GCC_SEC_CTRL_BCR 25 +-#define GCC_DDRSS_BCR 26 +-#define GCC_SYSTEM_NOC_BCR 27 +-#define GCC_PCNOC_BCR 28 +-#define GCC_TCSR_BCR 29 +-#define GCC_QDSS_BCR 30 +-#define GCC_DCD_BCR 31 +-#define GCC_MSG_RAM_BCR 32 +-#define GCC_MPM_BCR 33 +-#define GCC_SPDM_BCR 34 +-#define GCC_RBCPR_BCR 35 +-#define GCC_RBCPR_MX_BCR 36 +-#define GCC_TLMM_BCR 37 +-#define GCC_RBCPR_WCSS_BCR 38 +-#define GCC_USB0_PHY_BCR 39 +-#define GCC_USB3PHY_0_PHY_BCR 40 +-#define GCC_USB0_BCR 41 +-#define GCC_USB1_BCR 42 +-#define GCC_QUSB2_0_PHY_BCR 43 +-#define GCC_QUSB2_1_PHY_BCR 44 +-#define GCC_SDCC1_BCR 45 +-#define GCC_SNOC_BUS_TIMEOUT0_BCR 46 +-#define GCC_SNOC_BUS_TIMEOUT1_BCR 47 +-#define GCC_SNOC_BUS_TIMEOUT2_BCR 48 +-#define GCC_PCNOC_BUS_TIMEOUT0_BCR 49 +-#define GCC_PCNOC_BUS_TIMEOUT1_BCR 50 +-#define GCC_PCNOC_BUS_TIMEOUT2_BCR 51 +-#define GCC_PCNOC_BUS_TIMEOUT3_BCR 52 +-#define GCC_PCNOC_BUS_TIMEOUT4_BCR 53 +-#define GCC_PCNOC_BUS_TIMEOUT5_BCR 54 +-#define GCC_PCNOC_BUS_TIMEOUT6_BCR 55 +-#define GCC_PCNOC_BUS_TIMEOUT7_BCR 56 +-#define GCC_PCNOC_BUS_TIMEOUT8_BCR 57 +-#define GCC_PCNOC_BUS_TIMEOUT9_BCR 58 +-#define GCC_UNIPHY0_BCR 59 +-#define GCC_UNIPHY1_BCR 60 +-#define GCC_CMN_12GPLL_BCR 61 +-#define GCC_QPIC_BCR 62 +-#define GCC_MDIO_BCR 63 +-#define GCC_WCSS_CORE_TBU_BCR 64 +-#define GCC_WCSS_Q6_TBU_BCR 65 +-#define GCC_USB0_TBU_BCR 66 +-#define GCC_PCIE0_TBU_BCR 67 +-#define GCC_PCIE0_BCR 68 +-#define GCC_PCIE0_PHY_BCR 69 +-#define GCC_PCIE0PHY_PHY_BCR 70 +-#define GCC_PCIE0_LINK_DOWN_BCR 71 +-#define GCC_DCC_BCR 72 +-#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 73 +-#define GCC_SMMU_CATS_BCR 74 +-#define GCC_UBI0_AXI_ARES 75 +-#define GCC_UBI0_AHB_ARES 76 +-#define GCC_UBI0_NC_AXI_ARES 77 +-#define GCC_UBI0_DBG_ARES 78 +-#define GCC_UBI0_CORE_CLAMP_ENABLE 79 +-#define GCC_UBI0_CLKRST_CLAMP_ENABLE 80 +-#define GCC_UBI0_UTCM_ARES 81 +-#define GCC_NSS_CFG_ARES 82 +-#define GCC_NSS_NOC_ARES 83 +-#define GCC_NSS_CRYPTO_ARES 84 +-#define GCC_NSS_CSR_ARES 85 +-#define GCC_NSS_CE_APB_ARES 86 +-#define GCC_NSS_CE_AXI_ARES 87 +-#define GCC_NSSNOC_CE_APB_ARES 88 +-#define GCC_NSSNOC_CE_AXI_ARES 89 +-#define GCC_NSSNOC_UBI0_AHB_ARES 90 +-#define GCC_NSSNOC_SNOC_ARES 91 +-#define GCC_NSSNOC_CRYPTO_ARES 92 +-#define GCC_NSSNOC_ATB_ARES 93 +-#define GCC_NSSNOC_QOSGEN_REF_ARES 94 +-#define GCC_NSSNOC_TIMEOUT_REF_ARES 95 +-#define GCC_PCIE0_PIPE_ARES 96 +-#define GCC_PCIE0_SLEEP_ARES 97 +-#define GCC_PCIE0_CORE_STICKY_ARES 98 +-#define GCC_PCIE0_AXI_MASTER_ARES 99 +-#define GCC_PCIE0_AXI_SLAVE_ARES 100 +-#define GCC_PCIE0_AHB_ARES 101 +-#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 102 +-#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 103 +-#define GCC_PPE_FULL_RESET 104 +-#define GCC_UNIPHY0_SOFT_RESET 105 +-#define GCC_UNIPHY0_XPCS_RESET 106 +-#define GCC_UNIPHY1_SOFT_RESET 107 +-#define GCC_UNIPHY1_XPCS_RESET 108 +-#define GCC_EDMA_HW_RESET 109 +-#define GCC_ADSS_BCR 110 +-#define GCC_NSS_NOC_TBU_BCR 111 +-#define GCC_NSSPORT1_RESET 112 +-#define GCC_NSSPORT2_RESET 113 +-#define GCC_NSSPORT3_RESET 114 +-#define GCC_NSSPORT4_RESET 115 +-#define GCC_NSSPORT5_RESET 116 +-#define GCC_UNIPHY0_PORT1_ARES 117 +-#define GCC_UNIPHY0_PORT2_ARES 118 +-#define GCC_UNIPHY0_PORT3_ARES 119 +-#define GCC_UNIPHY0_PORT4_ARES 120 +-#define GCC_UNIPHY0_PORT5_ARES 121 +-#define GCC_UNIPHY0_PORT_4_5_RESET 122 +-#define GCC_UNIPHY0_PORT_4_RESET 123 +-#define GCC_LPASS_BCR 124 +-#define GCC_UBI32_TBU_BCR 125 +-#define GCC_LPASS_TBU_BCR 126 +-#define GCC_WCSSAON_RESET 127 +-#define GCC_LPASS_Q6_AXIM_ARES 128 +-#define GCC_LPASS_Q6SS_TSCTR_1TO2_ARES 129 +-#define GCC_LPASS_Q6SS_TRIG_ARES 130 +-#define GCC_LPASS_Q6_ATBM_AT_ARES 131 +-#define GCC_LPASS_Q6_PCLKDBG_ARES 132 +-#define GCC_LPASS_CORE_AXIM_ARES 133 +-#define GCC_LPASS_SNOC_CFG_ARES 134 +-#define GCC_WCSS_DBG_ARES 135 +-#define GCC_WCSS_ECAHB_ARES 136 +-#define GCC_WCSS_ACMT_ARES 137 +-#define GCC_WCSS_DBG_BDG_ARES 138 +-#define GCC_WCSS_AHB_S_ARES 139 +-#define GCC_WCSS_AXI_M_ARES 140 +-#define GCC_Q6SS_DBG_ARES 141 +-#define GCC_Q6_AHB_S_ARES 142 +-#define GCC_Q6_AHB_ARES 143 +-#define GCC_Q6_AXIM2_ARES 144 +-#define GCC_Q6_AXIM_ARES 145 +-#define GCC_UBI0_CORE_ARES 146 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-ipq806x.h b/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-ipq806x.h +deleted file mode 100644 +index 26b6f9200620..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-ipq806x.h ++++ /dev/null +@@ -1,167 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_RESET_IPQ_806X_H +-#define _DT_BINDINGS_RESET_IPQ_806X_H +- +-#define QDSS_STM_RESET 0 +-#define AFAB_SMPSS_S_RESET 1 +-#define AFAB_SMPSS_M1_RESET 2 +-#define AFAB_SMPSS_M0_RESET 3 +-#define AFAB_EBI1_CH0_RESET 4 +-#define AFAB_EBI1_CH1_RESET 5 +-#define SFAB_ADM0_M0_RESET 6 +-#define SFAB_ADM0_M1_RESET 7 +-#define SFAB_ADM0_M2_RESET 8 +-#define ADM0_C2_RESET 9 +-#define ADM0_C1_RESET 10 +-#define ADM0_C0_RESET 11 +-#define ADM0_PBUS_RESET 12 +-#define ADM0_RESET 13 +-#define QDSS_CLKS_SW_RESET 14 +-#define QDSS_POR_RESET 15 +-#define QDSS_TSCTR_RESET 16 +-#define QDSS_HRESET_RESET 17 +-#define QDSS_AXI_RESET 18 +-#define QDSS_DBG_RESET 19 +-#define SFAB_PCIE_M_RESET 20 +-#define SFAB_PCIE_S_RESET 21 +-#define PCIE_EXT_RESET 22 +-#define PCIE_PHY_RESET 23 +-#define PCIE_PCI_RESET 24 +-#define PCIE_POR_RESET 25 +-#define PCIE_HCLK_RESET 26 +-#define PCIE_ACLK_RESET 27 +-#define SFAB_LPASS_RESET 28 +-#define SFAB_AFAB_M_RESET 29 +-#define AFAB_SFAB_M0_RESET 30 +-#define AFAB_SFAB_M1_RESET 31 +-#define SFAB_SATA_S_RESET 32 +-#define SFAB_DFAB_M_RESET 33 +-#define DFAB_SFAB_M_RESET 34 +-#define DFAB_SWAY0_RESET 35 +-#define DFAB_SWAY1_RESET 36 +-#define DFAB_ARB0_RESET 37 +-#define DFAB_ARB1_RESET 38 +-#define PPSS_PROC_RESET 39 +-#define PPSS_RESET 40 +-#define DMA_BAM_RESET 41 +-#define SPS_TIC_H_RESET 42 +-#define SFAB_CFPB_M_RESET 43 +-#define SFAB_CFPB_S_RESET 44 +-#define TSIF_H_RESET 45 +-#define CE1_H_RESET 46 +-#define CE1_CORE_RESET 47 +-#define CE1_SLEEP_RESET 48 +-#define CE2_H_RESET 49 +-#define CE2_CORE_RESET 50 +-#define SFAB_SFPB_M_RESET 51 +-#define SFAB_SFPB_S_RESET 52 +-#define RPM_PROC_RESET 53 +-#define PMIC_SSBI2_RESET 54 +-#define SDC1_RESET 55 +-#define SDC2_RESET 56 +-#define SDC3_RESET 57 +-#define SDC4_RESET 58 +-#define USB_HS1_RESET 59 +-#define USB_HSIC_RESET 60 +-#define USB_FS1_XCVR_RESET 61 +-#define USB_FS1_RESET 62 +-#define GSBI1_RESET 63 +-#define GSBI2_RESET 64 +-#define GSBI3_RESET 65 +-#define GSBI4_RESET 66 +-#define GSBI5_RESET 67 +-#define GSBI6_RESET 68 +-#define GSBI7_RESET 69 +-#define SPDM_RESET 70 +-#define SEC_CTRL_RESET 71 +-#define TLMM_H_RESET 72 +-#define SFAB_SATA_M_RESET 73 +-#define SATA_RESET 74 +-#define TSSC_RESET 75 +-#define PDM_RESET 76 +-#define MPM_H_RESET 77 +-#define MPM_RESET 78 +-#define SFAB_SMPSS_S_RESET 79 +-#define PRNG_RESET 80 +-#define SFAB_CE3_M_RESET 81 +-#define SFAB_CE3_S_RESET 82 +-#define CE3_SLEEP_RESET 83 +-#define PCIE_1_M_RESET 84 +-#define PCIE_1_S_RESET 85 +-#define PCIE_1_EXT_RESET 86 +-#define PCIE_1_PHY_RESET 87 +-#define PCIE_1_PCI_RESET 88 +-#define PCIE_1_POR_RESET 89 +-#define PCIE_1_HCLK_RESET 90 +-#define PCIE_1_ACLK_RESET 91 +-#define PCIE_2_M_RESET 92 +-#define PCIE_2_S_RESET 93 +-#define PCIE_2_EXT_RESET 94 +-#define PCIE_2_PHY_RESET 95 +-#define PCIE_2_PCI_RESET 96 +-#define PCIE_2_POR_RESET 97 +-#define PCIE_2_HCLK_RESET 98 +-#define PCIE_2_ACLK_RESET 99 +-#define SFAB_USB30_S_RESET 100 +-#define SFAB_USB30_M_RESET 101 +-#define USB30_0_PORT2_HS_PHY_RESET 102 +-#define USB30_0_MASTER_RESET 103 +-#define USB30_0_SLEEP_RESET 104 +-#define USB30_0_UTMI_PHY_RESET 105 +-#define USB30_0_POWERON_RESET 106 +-#define USB30_0_PHY_RESET 107 +-#define USB30_1_MASTER_RESET 108 +-#define USB30_1_SLEEP_RESET 109 +-#define USB30_1_UTMI_PHY_RESET 110 +-#define USB30_1_POWERON_RESET 111 +-#define USB30_1_PHY_RESET 112 +-#define NSSFB0_RESET 113 +-#define NSSFB1_RESET 114 +-#define UBI32_CORE1_CLKRST_CLAMP_RESET 115 +-#define UBI32_CORE1_CLAMP_RESET 116 +-#define UBI32_CORE1_AHB_RESET 117 +-#define UBI32_CORE1_AXI_RESET 118 +-#define UBI32_CORE2_CLKRST_CLAMP_RESET 119 +-#define UBI32_CORE2_CLAMP_RESET 120 +-#define UBI32_CORE2_AHB_RESET 121 +-#define UBI32_CORE2_AXI_RESET 122 +-#define GMAC_CORE1_RESET 123 +-#define GMAC_CORE2_RESET 124 +-#define GMAC_CORE3_RESET 125 +-#define GMAC_CORE4_RESET 126 +-#define GMAC_AHB_RESET 127 +-#define NSS_CH0_RST_RX_CLK_N_RESET 128 +-#define NSS_CH0_RST_TX_CLK_N_RESET 129 +-#define NSS_CH0_RST_RX_125M_N_RESET 130 +-#define NSS_CH0_HW_RST_RX_125M_N_RESET 131 +-#define NSS_CH0_RST_TX_125M_N_RESET 132 +-#define NSS_CH1_RST_RX_CLK_N_RESET 133 +-#define NSS_CH1_RST_TX_CLK_N_RESET 134 +-#define NSS_CH1_RST_RX_125M_N_RESET 135 +-#define NSS_CH1_HW_RST_RX_125M_N_RESET 136 +-#define NSS_CH1_RST_TX_125M_N_RESET 137 +-#define NSS_CH2_RST_RX_CLK_N_RESET 138 +-#define NSS_CH2_RST_TX_CLK_N_RESET 139 +-#define NSS_CH2_RST_RX_125M_N_RESET 140 +-#define NSS_CH2_HW_RST_RX_125M_N_RESET 141 +-#define NSS_CH2_RST_TX_125M_N_RESET 142 +-#define NSS_CH3_RST_RX_CLK_N_RESET 143 +-#define NSS_CH3_RST_TX_CLK_N_RESET 144 +-#define NSS_CH3_RST_RX_125M_N_RESET 145 +-#define NSS_CH3_HW_RST_RX_125M_N_RESET 146 +-#define NSS_CH3_RST_TX_125M_N_RESET 147 +-#define NSS_RST_RX_250M_125M_N_RESET 148 +-#define NSS_RST_TX_250M_125M_N_RESET 149 +-#define NSS_QSGMII_TXPI_RST_N_RESET 150 +-#define NSS_QSGMII_CDR_RST_N_RESET 151 +-#define NSS_SGMII2_CDR_RST_N_RESET 152 +-#define NSS_SGMII3_CDR_RST_N_RESET 153 +-#define NSS_CAL_PRBS_RST_N_RESET 154 +-#define NSS_LCKDT_RST_N_RESET 155 +-#define NSS_SRDS_N_RESET 156 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-mdm9615.h b/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-mdm9615.h +deleted file mode 100644 +index 5faf02d7e289..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-mdm9615.h ++++ /dev/null +@@ -1,128 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2013, The Linux Foundation. All rights reserved. +- * Copyright (c) BayLibre, SAS. +- * Author : Neil Armstrong +- */ +- +-#ifndef _DT_BINDINGS_RESET_GCC_MDM9615_H +-#define _DT_BINDINGS_RESET_GCC_MDM9615_H +- +-#define SFAB_MSS_Q6_SW_RESET 0 +-#define SFAB_MSS_Q6_FW_RESET 1 +-#define QDSS_STM_RESET 2 +-#define AFAB_SMPSS_S_RESET 3 +-#define AFAB_SMPSS_M1_RESET 4 +-#define AFAB_SMPSS_M0_RESET 5 +-#define AFAB_EBI1_CH0_RESET 6 +-#define AFAB_EBI1_CH1_RESET 7 +-#define SFAB_ADM0_M0_RESET 8 +-#define SFAB_ADM0_M1_RESET 9 +-#define SFAB_ADM0_M2_RESET 10 +-#define ADM0_C2_RESET 11 +-#define ADM0_C1_RESET 12 +-#define ADM0_C0_RESET 13 +-#define ADM0_PBUS_RESET 14 +-#define ADM0_RESET 15 +-#define QDSS_CLKS_SW_RESET 16 +-#define QDSS_POR_RESET 17 +-#define QDSS_TSCTR_RESET 18 +-#define QDSS_HRESET_RESET 19 +-#define QDSS_AXI_RESET 20 +-#define QDSS_DBG_RESET 21 +-#define PCIE_A_RESET 22 +-#define PCIE_AUX_RESET 23 +-#define PCIE_H_RESET 24 +-#define SFAB_PCIE_M_RESET 25 +-#define SFAB_PCIE_S_RESET 26 +-#define SFAB_MSS_M_RESET 27 +-#define SFAB_USB3_M_RESET 28 +-#define SFAB_RIVA_M_RESET 29 +-#define SFAB_LPASS_RESET 30 +-#define SFAB_AFAB_M_RESET 31 +-#define AFAB_SFAB_M0_RESET 32 +-#define AFAB_SFAB_M1_RESET 33 +-#define SFAB_SATA_S_RESET 34 +-#define SFAB_DFAB_M_RESET 35 +-#define DFAB_SFAB_M_RESET 36 +-#define DFAB_SWAY0_RESET 37 +-#define DFAB_SWAY1_RESET 38 +-#define DFAB_ARB0_RESET 39 +-#define DFAB_ARB1_RESET 40 +-#define PPSS_PROC_RESET 41 +-#define PPSS_RESET 42 +-#define DMA_BAM_RESET 43 +-#define SPS_TIC_H_RESET 44 +-#define SLIMBUS_H_RESET 45 +-#define SFAB_CFPB_M_RESET 46 +-#define SFAB_CFPB_S_RESET 47 +-#define TSIF_H_RESET 48 +-#define CE1_H_RESET 49 +-#define CE1_CORE_RESET 50 +-#define CE1_SLEEP_RESET 51 +-#define CE2_H_RESET 52 +-#define CE2_CORE_RESET 53 +-#define SFAB_SFPB_M_RESET 54 +-#define SFAB_SFPB_S_RESET 55 +-#define RPM_PROC_RESET 56 +-#define PMIC_SSBI2_RESET 57 +-#define SDC1_RESET 58 +-#define SDC2_RESET 59 +-#define SDC3_RESET 60 +-#define SDC4_RESET 61 +-#define SDC5_RESET 62 +-#define DFAB_A2_RESET 63 +-#define USB_HS1_RESET 64 +-#define USB_HSIC_RESET 65 +-#define USB_FS1_XCVR_RESET 66 +-#define USB_FS1_RESET 67 +-#define USB_FS2_XCVR_RESET 68 +-#define USB_FS2_RESET 69 +-#define GSBI1_RESET 70 +-#define GSBI2_RESET 71 +-#define GSBI3_RESET 72 +-#define GSBI4_RESET 73 +-#define GSBI5_RESET 74 +-#define GSBI6_RESET 75 +-#define GSBI7_RESET 76 +-#define GSBI8_RESET 77 +-#define GSBI9_RESET 78 +-#define GSBI10_RESET 79 +-#define GSBI11_RESET 80 +-#define GSBI12_RESET 81 +-#define SPDM_RESET 82 +-#define TLMM_H_RESET 83 +-#define SFAB_MSS_S_RESET 84 +-#define MSS_SLP_RESET 85 +-#define MSS_Q6SW_JTAG_RESET 86 +-#define MSS_Q6FW_JTAG_RESET 87 +-#define MSS_RESET 88 +-#define SATA_H_RESET 89 +-#define SATA_RXOOB_RESE 90 +-#define SATA_PMALIVE_RESET 91 +-#define SATA_SFAB_M_RESET 92 +-#define TSSC_RESET 93 +-#define PDM_RESET 94 +-#define MPM_H_RESET 95 +-#define MPM_RESET 96 +-#define SFAB_SMPSS_S_RESET 97 +-#define PRNG_RESET 98 +-#define RIVA_RESET 99 +-#define USB_HS3_RESET 100 +-#define USB_HS4_RESET 101 +-#define CE3_RESET 102 +-#define PCIE_EXT_PCI_RESET 103 +-#define PCIE_PHY_RESET 104 +-#define PCIE_PCI_RESET 105 +-#define PCIE_POR_RESET 106 +-#define PCIE_HCLK_RESET 107 +-#define PCIE_ACLK_RESET 108 +-#define CE3_H_RESET 109 +-#define SFAB_CE3_M_RESET 110 +-#define SFAB_CE3_S_RESET 111 +-#define SATA_RESET 112 +-#define CE3_SLEEP_RESET 113 +-#define GSS_SLP_RESET 114 +-#define GSS_RESET 115 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-msm8660.h b/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-msm8660.h +deleted file mode 100644 +index f6d2b3cbe7b0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-msm8660.h ++++ /dev/null +@@ -1,126 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2013, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_RESET_MSM_GCC_8660_H +-#define _DT_BINDINGS_RESET_MSM_GCC_8660_H +- +-#define AFAB_CORE_RESET 0 +-#define SCSS_SYS_RESET 1 +-#define SCSS_SYS_POR_RESET 2 +-#define AFAB_SMPSS_S_RESET 3 +-#define AFAB_SMPSS_M1_RESET 4 +-#define AFAB_SMPSS_M0_RESET 5 +-#define AFAB_EBI1_S_RESET 6 +-#define SFAB_CORE_RESET 7 +-#define SFAB_ADM0_M0_RESET 8 +-#define SFAB_ADM0_M1_RESET 9 +-#define SFAB_ADM0_M2_RESET 10 +-#define ADM0_C2_RESET 11 +-#define ADM0_C1_RESET 12 +-#define ADM0_C0_RESET 13 +-#define ADM0_PBUS_RESET 14 +-#define ADM0_RESET 15 +-#define SFAB_ADM1_M0_RESET 16 +-#define SFAB_ADM1_M1_RESET 17 +-#define SFAB_ADM1_M2_RESET 18 +-#define MMFAB_ADM1_M3_RESET 19 +-#define ADM1_C3_RESET 20 +-#define ADM1_C2_RESET 21 +-#define ADM1_C1_RESET 22 +-#define ADM1_C0_RESET 23 +-#define ADM1_PBUS_RESET 24 +-#define ADM1_RESET 25 +-#define IMEM0_RESET 26 +-#define SFAB_LPASS_Q6_RESET 27 +-#define SFAB_AFAB_M_RESET 28 +-#define AFAB_SFAB_M0_RESET 29 +-#define AFAB_SFAB_M1_RESET 30 +-#define DFAB_CORE_RESET 31 +-#define SFAB_DFAB_M_RESET 32 +-#define DFAB_SFAB_M_RESET 33 +-#define DFAB_SWAY0_RESET 34 +-#define DFAB_SWAY1_RESET 35 +-#define DFAB_ARB0_RESET 36 +-#define DFAB_ARB1_RESET 37 +-#define PPSS_PROC_RESET 38 +-#define PPSS_RESET 39 +-#define PMEM_RESET 40 +-#define DMA_BAM_RESET 41 +-#define SIC_RESET 42 +-#define SPS_TIC_RESET 43 +-#define CFBP0_RESET 44 +-#define CFBP1_RESET 45 +-#define CFBP2_RESET 46 +-#define EBI2_RESET 47 +-#define SFAB_CFPB_M_RESET 48 +-#define CFPB_MASTER_RESET 49 +-#define SFAB_CFPB_S_RESET 50 +-#define CFPB_SPLITTER_RESET 51 +-#define TSIF_RESET 52 +-#define CE1_RESET 53 +-#define CE2_RESET 54 +-#define SFAB_SFPB_M_RESET 55 +-#define SFAB_SFPB_S_RESET 56 +-#define RPM_PROC_RESET 57 +-#define RPM_BUS_RESET 58 +-#define RPM_MSG_RAM_RESET 59 +-#define PMIC_ARB0_RESET 60 +-#define PMIC_ARB1_RESET 61 +-#define PMIC_SSBI2_RESET 62 +-#define SDC1_RESET 63 +-#define SDC2_RESET 64 +-#define SDC3_RESET 65 +-#define SDC4_RESET 66 +-#define SDC5_RESET 67 +-#define USB_HS1_RESET 68 +-#define USB_HS2_XCVR_RESET 69 +-#define USB_HS2_RESET 70 +-#define USB_FS1_XCVR_RESET 71 +-#define USB_FS1_RESET 72 +-#define USB_FS2_XCVR_RESET 73 +-#define USB_FS2_RESET 74 +-#define GSBI1_RESET 75 +-#define GSBI2_RESET 76 +-#define GSBI3_RESET 77 +-#define GSBI4_RESET 78 +-#define GSBI5_RESET 79 +-#define GSBI6_RESET 80 +-#define GSBI7_RESET 81 +-#define GSBI8_RESET 82 +-#define GSBI9_RESET 83 +-#define GSBI10_RESET 84 +-#define GSBI11_RESET 85 +-#define GSBI12_RESET 86 +-#define SPDM_RESET 87 +-#define SEC_CTRL_RESET 88 +-#define TLMM_H_RESET 89 +-#define TLMM_RESET 90 +-#define MARRM_PWRON_RESET 91 +-#define MARM_RESET 92 +-#define MAHB1_RESET 93 +-#define SFAB_MSS_S_RESET 94 +-#define MAHB2_RESET 95 +-#define MODEM_SW_AHB_RESET 96 +-#define MODEM_RESET 97 +-#define SFAB_MSS_MDM1_RESET 98 +-#define SFAB_MSS_MDM0_RESET 99 +-#define MSS_SLP_RESET 100 +-#define MSS_MARM_SAW_RESET 101 +-#define MSS_WDOG_RESET 102 +-#define TSSC_RESET 103 +-#define PDM_RESET 104 +-#define SCSS_CORE0_RESET 105 +-#define SCSS_CORE0_POR_RESET 106 +-#define SCSS_CORE1_RESET 107 +-#define SCSS_CORE1_POR_RESET 108 +-#define MPM_RESET 109 +-#define EBI1_1X_DIV_RESET 110 +-#define EBI1_RESET 111 +-#define SFAB_SMPSS_S_RESET 112 +-#define USB_PHY0_RESET 113 +-#define USB_PHY1_RESET 114 +-#define PRNG_RESET 115 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-msm8916.h b/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-msm8916.h +deleted file mode 100644 +index 1f9be10872df..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-msm8916.h ++++ /dev/null +@@ -1,100 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2015 Linaro Limited +- */ +- +-#ifndef _DT_BINDINGS_RESET_MSM_GCC_8916_H +-#define _DT_BINDINGS_RESET_MSM_GCC_8916_H +- +-#define GCC_BLSP1_BCR 0 +-#define GCC_BLSP1_QUP1_BCR 1 +-#define GCC_BLSP1_UART1_BCR 2 +-#define GCC_BLSP1_QUP2_BCR 3 +-#define GCC_BLSP1_UART2_BCR 4 +-#define GCC_BLSP1_QUP3_BCR 5 +-#define GCC_BLSP1_QUP4_BCR 6 +-#define GCC_BLSP1_QUP5_BCR 7 +-#define GCC_BLSP1_QUP6_BCR 8 +-#define GCC_IMEM_BCR 9 +-#define GCC_SMMU_BCR 10 +-#define GCC_APSS_TCU_BCR 11 +-#define GCC_SMMU_XPU_BCR 12 +-#define GCC_PCNOC_TBU_BCR 13 +-#define GCC_PRNG_BCR 14 +-#define GCC_BOOT_ROM_BCR 15 +-#define GCC_CRYPTO_BCR 16 +-#define GCC_SEC_CTRL_BCR 17 +-#define GCC_AUDIO_CORE_BCR 18 +-#define GCC_ULT_AUDIO_BCR 19 +-#define GCC_DEHR_BCR 20 +-#define GCC_SYSTEM_NOC_BCR 21 +-#define GCC_PCNOC_BCR 22 +-#define GCC_TCSR_BCR 23 +-#define GCC_QDSS_BCR 24 +-#define GCC_DCD_BCR 25 +-#define GCC_MSG_RAM_BCR 26 +-#define GCC_MPM_BCR 27 +-#define GCC_SPMI_BCR 28 +-#define GCC_SPDM_BCR 29 +-#define GCC_MM_SPDM_BCR 30 +-#define GCC_BIMC_BCR 31 +-#define GCC_RBCPR_BCR 32 +-#define GCC_TLMM_BCR 33 +-#define GCC_USB_HS_BCR 34 +-#define GCC_USB2A_PHY_BCR 35 +-#define GCC_SDCC1_BCR 36 +-#define GCC_SDCC2_BCR 37 +-#define GCC_PDM_BCR 38 +-#define GCC_SNOC_BUS_TIMEOUT0_BCR 39 +-#define GCC_PCNOC_BUS_TIMEOUT0_BCR 40 +-#define GCC_PCNOC_BUS_TIMEOUT1_BCR 41 +-#define GCC_PCNOC_BUS_TIMEOUT2_BCR 42 +-#define GCC_PCNOC_BUS_TIMEOUT3_BCR 43 +-#define GCC_PCNOC_BUS_TIMEOUT4_BCR 44 +-#define GCC_PCNOC_BUS_TIMEOUT5_BCR 45 +-#define GCC_PCNOC_BUS_TIMEOUT6_BCR 46 +-#define GCC_PCNOC_BUS_TIMEOUT7_BCR 47 +-#define GCC_PCNOC_BUS_TIMEOUT8_BCR 48 +-#define GCC_PCNOC_BUS_TIMEOUT9_BCR 49 +-#define GCC_MMSS_BCR 50 +-#define GCC_VENUS0_BCR 51 +-#define GCC_MDSS_BCR 52 +-#define GCC_CAMSS_PHY0_BCR 53 +-#define GCC_CAMSS_CSI0_BCR 54 +-#define GCC_CAMSS_CSI0PHY_BCR 55 +-#define GCC_CAMSS_CSI0RDI_BCR 56 +-#define GCC_CAMSS_CSI0PIX_BCR 57 +-#define GCC_CAMSS_PHY1_BCR 58 +-#define GCC_CAMSS_CSI1_BCR 59 +-#define GCC_CAMSS_CSI1PHY_BCR 60 +-#define GCC_CAMSS_CSI1RDI_BCR 61 +-#define GCC_CAMSS_CSI1PIX_BCR 62 +-#define GCC_CAMSS_ISPIF_BCR 63 +-#define GCC_CAMSS_CCI_BCR 64 +-#define GCC_CAMSS_MCLK0_BCR 65 +-#define GCC_CAMSS_MCLK1_BCR 66 +-#define GCC_CAMSS_GP0_BCR 67 +-#define GCC_CAMSS_GP1_BCR 68 +-#define GCC_CAMSS_TOP_BCR 69 +-#define GCC_CAMSS_MICRO_BCR 70 +-#define GCC_CAMSS_JPEG_BCR 71 +-#define GCC_CAMSS_VFE_BCR 72 +-#define GCC_CAMSS_CSI_VFE0_BCR 73 +-#define GCC_OXILI_BCR 74 +-#define GCC_GMEM_BCR 75 +-#define GCC_CAMSS_AHB_BCR 76 +-#define GCC_MDP_TBU_BCR 77 +-#define GCC_GFX_TBU_BCR 78 +-#define GCC_GFX_TCU_BCR 79 +-#define GCC_MSS_TBU_AXI_BCR 80 +-#define GCC_MSS_TBU_GSS_AXI_BCR 81 +-#define GCC_MSS_TBU_Q6_AXI_BCR 82 +-#define GCC_GTCU_AHB_BCR 83 +-#define GCC_SMMU_CFG_BCR 84 +-#define GCC_VFE_TBU_BCR 85 +-#define GCC_VENUS_TBU_BCR 86 +-#define GCC_JPEG_TBU_BCR 87 +-#define GCC_PRONTO_TBU_BCR 88 +-#define GCC_SMMU_CATS_BCR 89 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-msm8939.h b/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-msm8939.h +deleted file mode 100644 +index fa41ffeae7a2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-msm8939.h ++++ /dev/null +@@ -1,110 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright 2020 Linaro Limited +- */ +- +-#ifndef _DT_BINDINGS_RESET_MSM_GCC_8939_H +-#define _DT_BINDINGS_RESET_MSM_GCC_8939_H +- +-#define GCC_BLSP1_BCR 0 +-#define GCC_BLSP1_QUP1_BCR 1 +-#define GCC_BLSP1_UART1_BCR 2 +-#define GCC_BLSP1_QUP2_BCR 3 +-#define GCC_BLSP1_UART2_BCR 4 +-#define GCC_BLSP1_QUP3_BCR 5 +-#define GCC_BLSP1_QUP4_BCR 6 +-#define GCC_BLSP1_QUP5_BCR 7 +-#define GCC_BLSP1_QUP6_BCR 8 +-#define GCC_IMEM_BCR 9 +-#define GCC_SMMU_BCR 10 +-#define GCC_APSS_TCU_BCR 11 +-#define GCC_SMMU_XPU_BCR 12 +-#define GCC_PCNOC_TBU_BCR 13 +-#define GCC_PRNG_BCR 14 +-#define GCC_BOOT_ROM_BCR 15 +-#define GCC_CRYPTO_BCR 16 +-#define GCC_SEC_CTRL_BCR 17 +-#define GCC_AUDIO_CORE_BCR 18 +-#define GCC_ULT_AUDIO_BCR 19 +-#define GCC_DEHR_BCR 20 +-#define GCC_SYSTEM_NOC_BCR 21 +-#define GCC_PCNOC_BCR 22 +-#define GCC_TCSR_BCR 23 +-#define GCC_QDSS_BCR 24 +-#define GCC_DCD_BCR 25 +-#define GCC_MSG_RAM_BCR 26 +-#define GCC_MPM_BCR 27 +-#define GCC_SPMI_BCR 28 +-#define GCC_SPDM_BCR 29 +-#define GCC_MM_SPDM_BCR 30 +-#define GCC_BIMC_BCR 31 +-#define GCC_RBCPR_BCR 32 +-#define GCC_TLMM_BCR 33 +-#define GCC_USB_HS_BCR 34 +-#define GCC_USB2A_PHY_BCR 35 +-#define GCC_SDCC1_BCR 36 +-#define GCC_SDCC2_BCR 37 +-#define GCC_PDM_BCR 38 +-#define GCC_SNOC_BUS_TIMEOUT0_BCR 39 +-#define GCC_PCNOC_BUS_TIMEOUT0_BCR 40 +-#define GCC_PCNOC_BUS_TIMEOUT1_BCR 41 +-#define GCC_PCNOC_BUS_TIMEOUT2_BCR 42 +-#define GCC_PCNOC_BUS_TIMEOUT3_BCR 43 +-#define GCC_PCNOC_BUS_TIMEOUT4_BCR 44 +-#define GCC_PCNOC_BUS_TIMEOUT5_BCR 45 +-#define GCC_PCNOC_BUS_TIMEOUT6_BCR 46 +-#define GCC_PCNOC_BUS_TIMEOUT7_BCR 47 +-#define GCC_PCNOC_BUS_TIMEOUT8_BCR 48 +-#define GCC_PCNOC_BUS_TIMEOUT9_BCR 49 +-#define GCC_MMSS_BCR 50 +-#define GCC_VENUS0_BCR 51 +-#define GCC_MDSS_BCR 52 +-#define GCC_CAMSS_PHY0_BCR 53 +-#define GCC_CAMSS_CSI0_BCR 54 +-#define GCC_CAMSS_CSI0PHY_BCR 55 +-#define GCC_CAMSS_CSI0RDI_BCR 56 +-#define GCC_CAMSS_CSI0PIX_BCR 57 +-#define GCC_CAMSS_PHY1_BCR 58 +-#define GCC_CAMSS_CSI1_BCR 59 +-#define GCC_CAMSS_CSI1PHY_BCR 60 +-#define GCC_CAMSS_CSI1RDI_BCR 61 +-#define GCC_CAMSS_CSI1PIX_BCR 62 +-#define GCC_CAMSS_ISPIF_BCR 63 +-#define GCC_CAMSS_CCI_BCR 64 +-#define GCC_CAMSS_MCLK0_BCR 65 +-#define GCC_CAMSS_MCLK1_BCR 66 +-#define GCC_CAMSS_GP0_BCR 67 +-#define GCC_CAMSS_GP1_BCR 68 +-#define GCC_CAMSS_TOP_BCR 69 +-#define GCC_CAMSS_MICRO_BCR 70 +-#define GCC_CAMSS_JPEG_BCR 71 +-#define GCC_CAMSS_VFE_BCR 72 +-#define GCC_CAMSS_CSI_VFE0_BCR 73 +-#define GCC_OXILI_BCR 74 +-#define GCC_GMEM_BCR 75 +-#define GCC_CAMSS_AHB_BCR 76 +-#define GCC_MDP_TBU_BCR 77 +-#define GCC_GFX_TBU_BCR 78 +-#define GCC_GFX_TCU_BCR 79 +-#define GCC_MSS_TBU_AXI_BCR 80 +-#define GCC_MSS_TBU_GSS_AXI_BCR 81 +-#define GCC_MSS_TBU_Q6_AXI_BCR 82 +-#define GCC_GTCU_AHB_BCR 83 +-#define GCC_SMMU_CFG_BCR 84 +-#define GCC_VFE_TBU_BCR 85 +-#define GCC_VENUS_TBU_BCR 86 +-#define GCC_JPEG_TBU_BCR 87 +-#define GCC_PRONTO_TBU_BCR 88 +-#define GCC_SMMU_CATS_BCR 89 +-#define GCC_BLSP1_UART3_BCR 90 +-#define GCC_CAMSS_CSI2_BCR 91 +-#define GCC_CAMSS_CSI2PHY_BCR 92 +-#define GCC_CAMSS_CSI2RDI_BCR 93 +-#define GCC_CAMSS_CSI2PIX_BCR 94 +-#define GCC_USB_FS_BCR 95 +-#define GCC_BLSP1_QUP4_SPI_APPS_CBCR 96 +-#define GCC_CAMSS_MCLK2_BCR 97 +-#define GCC_CPP_TBU_BCR 98 +-#define GCC_MDP_RT_TBU_BCR 99 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-msm8960.h b/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-msm8960.h +deleted file mode 100644 +index c7ebae7bb256..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-msm8960.h ++++ /dev/null +@@ -1,126 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2013, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_RESET_MSM_GCC_8960_H +-#define _DT_BINDINGS_RESET_MSM_GCC_8960_H +- +-#define SFAB_MSS_Q6_SW_RESET 0 +-#define SFAB_MSS_Q6_FW_RESET 1 +-#define QDSS_STM_RESET 2 +-#define AFAB_SMPSS_S_RESET 3 +-#define AFAB_SMPSS_M1_RESET 4 +-#define AFAB_SMPSS_M0_RESET 5 +-#define AFAB_EBI1_CH0_RESET 6 +-#define AFAB_EBI1_CH1_RESET 7 +-#define SFAB_ADM0_M0_RESET 8 +-#define SFAB_ADM0_M1_RESET 9 +-#define SFAB_ADM0_M2_RESET 10 +-#define ADM0_C2_RESET 11 +-#define ADM0_C1_RESET 12 +-#define ADM0_C0_RESET 13 +-#define ADM0_PBUS_RESET 14 +-#define ADM0_RESET 15 +-#define QDSS_CLKS_SW_RESET 16 +-#define QDSS_POR_RESET 17 +-#define QDSS_TSCTR_RESET 18 +-#define QDSS_HRESET_RESET 19 +-#define QDSS_AXI_RESET 20 +-#define QDSS_DBG_RESET 21 +-#define PCIE_A_RESET 22 +-#define PCIE_AUX_RESET 23 +-#define PCIE_H_RESET 24 +-#define SFAB_PCIE_M_RESET 25 +-#define SFAB_PCIE_S_RESET 26 +-#define SFAB_MSS_M_RESET 27 +-#define SFAB_USB3_M_RESET 28 +-#define SFAB_RIVA_M_RESET 29 +-#define SFAB_LPASS_RESET 30 +-#define SFAB_AFAB_M_RESET 31 +-#define AFAB_SFAB_M0_RESET 32 +-#define AFAB_SFAB_M1_RESET 33 +-#define SFAB_SATA_S_RESET 34 +-#define SFAB_DFAB_M_RESET 35 +-#define DFAB_SFAB_M_RESET 36 +-#define DFAB_SWAY0_RESET 37 +-#define DFAB_SWAY1_RESET 38 +-#define DFAB_ARB0_RESET 39 +-#define DFAB_ARB1_RESET 40 +-#define PPSS_PROC_RESET 41 +-#define PPSS_RESET 42 +-#define DMA_BAM_RESET 43 +-#define SPS_TIC_H_RESET 44 +-#define SLIMBUS_H_RESET 45 +-#define SFAB_CFPB_M_RESET 46 +-#define SFAB_CFPB_S_RESET 47 +-#define TSIF_H_RESET 48 +-#define CE1_H_RESET 49 +-#define CE1_CORE_RESET 50 +-#define CE1_SLEEP_RESET 51 +-#define CE2_H_RESET 52 +-#define CE2_CORE_RESET 53 +-#define SFAB_SFPB_M_RESET 54 +-#define SFAB_SFPB_S_RESET 55 +-#define RPM_PROC_RESET 56 +-#define PMIC_SSBI2_RESET 57 +-#define SDC1_RESET 58 +-#define SDC2_RESET 59 +-#define SDC3_RESET 60 +-#define SDC4_RESET 61 +-#define SDC5_RESET 62 +-#define DFAB_A2_RESET 63 +-#define USB_HS1_RESET 64 +-#define USB_HSIC_RESET 65 +-#define USB_FS1_XCVR_RESET 66 +-#define USB_FS1_RESET 67 +-#define USB_FS2_XCVR_RESET 68 +-#define USB_FS2_RESET 69 +-#define GSBI1_RESET 70 +-#define GSBI2_RESET 71 +-#define GSBI3_RESET 72 +-#define GSBI4_RESET 73 +-#define GSBI5_RESET 74 +-#define GSBI6_RESET 75 +-#define GSBI7_RESET 76 +-#define GSBI8_RESET 77 +-#define GSBI9_RESET 78 +-#define GSBI10_RESET 79 +-#define GSBI11_RESET 80 +-#define GSBI12_RESET 81 +-#define SPDM_RESET 82 +-#define TLMM_H_RESET 83 +-#define SFAB_MSS_S_RESET 84 +-#define MSS_SLP_RESET 85 +-#define MSS_Q6SW_JTAG_RESET 86 +-#define MSS_Q6FW_JTAG_RESET 87 +-#define MSS_RESET 88 +-#define SATA_H_RESET 89 +-#define SATA_RXOOB_RESE 90 +-#define SATA_PMALIVE_RESET 91 +-#define SATA_SFAB_M_RESET 92 +-#define TSSC_RESET 93 +-#define PDM_RESET 94 +-#define MPM_H_RESET 95 +-#define MPM_RESET 96 +-#define SFAB_SMPSS_S_RESET 97 +-#define PRNG_RESET 98 +-#define RIVA_RESET 99 +-#define USB_HS3_RESET 100 +-#define USB_HS4_RESET 101 +-#define CE3_RESET 102 +-#define PCIE_EXT_PCI_RESET 103 +-#define PCIE_PHY_RESET 104 +-#define PCIE_PCI_RESET 105 +-#define PCIE_POR_RESET 106 +-#define PCIE_HCLK_RESET 107 +-#define PCIE_ACLK_RESET 108 +-#define CE3_H_RESET 109 +-#define SFAB_CE3_M_RESET 110 +-#define SFAB_CE3_S_RESET 111 +-#define SATA_RESET 112 +-#define CE3_SLEEP_RESET 113 +-#define GSS_SLP_RESET 114 +-#define GSS_RESET 115 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-msm8974.h b/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-msm8974.h +deleted file mode 100644 +index 23777e5ca4eb..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,gcc-msm8974.h ++++ /dev/null +@@ -1,88 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2013, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_RESET_MSM_GCC_8974_H +-#define _DT_BINDINGS_RESET_MSM_GCC_8974_H +- +-#define GCC_SYSTEM_NOC_BCR 0 +-#define GCC_CONFIG_NOC_BCR 1 +-#define GCC_PERIPH_NOC_BCR 2 +-#define GCC_IMEM_BCR 3 +-#define GCC_MMSS_BCR 4 +-#define GCC_QDSS_BCR 5 +-#define GCC_USB_30_BCR 6 +-#define GCC_USB3_PHY_BCR 7 +-#define GCC_USB_HS_HSIC_BCR 8 +-#define GCC_USB_HS_BCR 9 +-#define GCC_USB2A_PHY_BCR 10 +-#define GCC_USB2B_PHY_BCR 11 +-#define GCC_SDCC1_BCR 12 +-#define GCC_SDCC2_BCR 13 +-#define GCC_SDCC3_BCR 14 +-#define GCC_SDCC4_BCR 15 +-#define GCC_BLSP1_BCR 16 +-#define GCC_BLSP1_QUP1_BCR 17 +-#define GCC_BLSP1_UART1_BCR 18 +-#define GCC_BLSP1_QUP2_BCR 19 +-#define GCC_BLSP1_UART2_BCR 20 +-#define GCC_BLSP1_QUP3_BCR 21 +-#define GCC_BLSP1_UART3_BCR 22 +-#define GCC_BLSP1_QUP4_BCR 23 +-#define GCC_BLSP1_UART4_BCR 24 +-#define GCC_BLSP1_QUP5_BCR 25 +-#define GCC_BLSP1_UART5_BCR 26 +-#define GCC_BLSP1_QUP6_BCR 27 +-#define GCC_BLSP1_UART6_BCR 28 +-#define GCC_BLSP2_BCR 29 +-#define GCC_BLSP2_QUP1_BCR 30 +-#define GCC_BLSP2_UART1_BCR 31 +-#define GCC_BLSP2_QUP2_BCR 32 +-#define GCC_BLSP2_UART2_BCR 33 +-#define GCC_BLSP2_QUP3_BCR 34 +-#define GCC_BLSP2_UART3_BCR 35 +-#define GCC_BLSP2_QUP4_BCR 36 +-#define GCC_BLSP2_UART4_BCR 37 +-#define GCC_BLSP2_QUP5_BCR 38 +-#define GCC_BLSP2_UART5_BCR 39 +-#define GCC_BLSP2_QUP6_BCR 40 +-#define GCC_BLSP2_UART6_BCR 41 +-#define GCC_PDM_BCR 42 +-#define GCC_BAM_DMA_BCR 43 +-#define GCC_TSIF_BCR 44 +-#define GCC_TCSR_BCR 45 +-#define GCC_BOOT_ROM_BCR 46 +-#define GCC_MSG_RAM_BCR 47 +-#define GCC_TLMM_BCR 48 +-#define GCC_MPM_BCR 49 +-#define GCC_SEC_CTRL_BCR 50 +-#define GCC_SPMI_BCR 51 +-#define GCC_SPDM_BCR 52 +-#define GCC_CE1_BCR 53 +-#define GCC_CE2_BCR 54 +-#define GCC_BIMC_BCR 55 +-#define GCC_MPM_NON_AHB_RESET 56 +-#define GCC_MPM_AHB_RESET 57 +-#define GCC_SNOC_BUS_TIMEOUT0_BCR 58 +-#define GCC_SNOC_BUS_TIMEOUT2_BCR 59 +-#define GCC_PNOC_BUS_TIMEOUT0_BCR 60 +-#define GCC_PNOC_BUS_TIMEOUT1_BCR 61 +-#define GCC_PNOC_BUS_TIMEOUT2_BCR 62 +-#define GCC_PNOC_BUS_TIMEOUT3_BCR 63 +-#define GCC_PNOC_BUS_TIMEOUT4_BCR 64 +-#define GCC_CNOC_BUS_TIMEOUT0_BCR 65 +-#define GCC_CNOC_BUS_TIMEOUT1_BCR 66 +-#define GCC_CNOC_BUS_TIMEOUT2_BCR 67 +-#define GCC_CNOC_BUS_TIMEOUT3_BCR 68 +-#define GCC_CNOC_BUS_TIMEOUT4_BCR 69 +-#define GCC_CNOC_BUS_TIMEOUT5_BCR 70 +-#define GCC_CNOC_BUS_TIMEOUT6_BCR 71 +-#define GCC_DEHR_BCR 72 +-#define GCC_RBCPR_BCR 73 +-#define GCC_MSS_RESTART 74 +-#define GCC_LPASS_RESTART 75 +-#define GCC_WCSS_RESTART 76 +-#define GCC_VENUS_RESTART 77 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,mmcc-apq8084.h b/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,mmcc-apq8084.h +deleted file mode 100644 +index faaeb40959f8..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,mmcc-apq8084.h ++++ /dev/null +@@ -1,56 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2014, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_RESET_APQ_MMCC_8084_H +-#define _DT_BINDINGS_RESET_APQ_MMCC_8084_H +- +-#define MMSS_SPDM_RESET 0 +-#define MMSS_SPDM_RM_RESET 1 +-#define VENUS0_RESET 2 +-#define VPU_RESET 3 +-#define MDSS_RESET 4 +-#define AVSYNC_RESET 5 +-#define CAMSS_PHY0_RESET 6 +-#define CAMSS_PHY1_RESET 7 +-#define CAMSS_PHY2_RESET 8 +-#define CAMSS_CSI0_RESET 9 +-#define CAMSS_CSI0PHY_RESET 10 +-#define CAMSS_CSI0RDI_RESET 11 +-#define CAMSS_CSI0PIX_RESET 12 +-#define CAMSS_CSI1_RESET 13 +-#define CAMSS_CSI1PHY_RESET 14 +-#define CAMSS_CSI1RDI_RESET 15 +-#define CAMSS_CSI1PIX_RESET 16 +-#define CAMSS_CSI2_RESET 17 +-#define CAMSS_CSI2PHY_RESET 18 +-#define CAMSS_CSI2RDI_RESET 19 +-#define CAMSS_CSI2PIX_RESET 20 +-#define CAMSS_CSI3_RESET 21 +-#define CAMSS_CSI3PHY_RESET 22 +-#define CAMSS_CSI3RDI_RESET 23 +-#define CAMSS_CSI3PIX_RESET 24 +-#define CAMSS_ISPIF_RESET 25 +-#define CAMSS_CCI_RESET 26 +-#define CAMSS_MCLK0_RESET 27 +-#define CAMSS_MCLK1_RESET 28 +-#define CAMSS_MCLK2_RESET 29 +-#define CAMSS_MCLK3_RESET 30 +-#define CAMSS_GP0_RESET 31 +-#define CAMSS_GP1_RESET 32 +-#define CAMSS_TOP_RESET 33 +-#define CAMSS_AHB_RESET 34 +-#define CAMSS_MICRO_RESET 35 +-#define CAMSS_JPEG_RESET 36 +-#define CAMSS_VFE_RESET 37 +-#define CAMSS_CSI_VFE0_RESET 38 +-#define CAMSS_CSI_VFE1_RESET 39 +-#define OXILI_RESET 40 +-#define OXILICX_RESET 41 +-#define OCMEMCX_RESET 42 +-#define MMSS_RBCRP_RESET 43 +-#define MMSSNOCAHB_RESET 44 +-#define MMSSNOCAXI_RESET 45 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,mmcc-msm8960.h b/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,mmcc-msm8960.h +deleted file mode 100644 +index eb4186aa2c0c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,mmcc-msm8960.h ++++ /dev/null +@@ -1,93 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2013, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_RESET_MSM_MMCC_8960_H +-#define _DT_BINDINGS_RESET_MSM_MMCC_8960_H +- +-#define VPE_AXI_RESET 0 +-#define IJPEG_AXI_RESET 1 +-#define MPD_AXI_RESET 2 +-#define VFE_AXI_RESET 3 +-#define SP_AXI_RESET 4 +-#define VCODEC_AXI_RESET 5 +-#define ROT_AXI_RESET 6 +-#define VCODEC_AXI_A_RESET 7 +-#define VCODEC_AXI_B_RESET 8 +-#define FAB_S3_AXI_RESET 9 +-#define FAB_S2_AXI_RESET 10 +-#define FAB_S1_AXI_RESET 11 +-#define FAB_S0_AXI_RESET 12 +-#define SMMU_GFX3D_ABH_RESET 13 +-#define SMMU_VPE_AHB_RESET 14 +-#define SMMU_VFE_AHB_RESET 15 +-#define SMMU_ROT_AHB_RESET 16 +-#define SMMU_VCODEC_B_AHB_RESET 17 +-#define SMMU_VCODEC_A_AHB_RESET 18 +-#define SMMU_MDP1_AHB_RESET 19 +-#define SMMU_MDP0_AHB_RESET 20 +-#define SMMU_JPEGD_AHB_RESET 21 +-#define SMMU_IJPEG_AHB_RESET 22 +-#define SMMU_GFX2D0_AHB_RESET 23 +-#define SMMU_GFX2D1_AHB_RESET 24 +-#define APU_AHB_RESET 25 +-#define CSI_AHB_RESET 26 +-#define TV_ENC_AHB_RESET 27 +-#define VPE_AHB_RESET 28 +-#define FABRIC_AHB_RESET 29 +-#define GFX2D0_AHB_RESET 30 +-#define GFX2D1_AHB_RESET 31 +-#define GFX3D_AHB_RESET 32 +-#define HDMI_AHB_RESET 33 +-#define MSSS_IMEM_AHB_RESET 34 +-#define IJPEG_AHB_RESET 35 +-#define DSI_M_AHB_RESET 36 +-#define DSI_S_AHB_RESET 37 +-#define JPEGD_AHB_RESET 38 +-#define MDP_AHB_RESET 39 +-#define ROT_AHB_RESET 40 +-#define VCODEC_AHB_RESET 41 +-#define VFE_AHB_RESET 42 +-#define DSI2_M_AHB_RESET 43 +-#define DSI2_S_AHB_RESET 44 +-#define CSIPHY2_RESET 45 +-#define CSI_PIX1_RESET 46 +-#define CSIPHY0_RESET 47 +-#define CSIPHY1_RESET 48 +-#define DSI2_RESET 49 +-#define VFE_CSI_RESET 50 +-#define MDP_RESET 51 +-#define AMP_RESET 52 +-#define JPEGD_RESET 53 +-#define CSI1_RESET 54 +-#define VPE_RESET 55 +-#define MMSS_FABRIC_RESET 56 +-#define VFE_RESET 57 +-#define GFX2D0_RESET 58 +-#define GFX2D1_RESET 59 +-#define GFX3D_RESET 60 +-#define HDMI_RESET 61 +-#define MMSS_IMEM_RESET 62 +-#define IJPEG_RESET 63 +-#define CSI0_RESET 64 +-#define DSI_RESET 65 +-#define VCODEC_RESET 66 +-#define MDP_TV_RESET 67 +-#define MDP_VSYNC_RESET 68 +-#define ROT_RESET 69 +-#define TV_HDMI_RESET 70 +-#define TV_ENC_RESET 71 +-#define CSI2_RESET 72 +-#define CSI_RDI1_RESET 73 +-#define CSI_RDI2_RESET 74 +-#define GFX3D_AXI_RESET 75 +-#define VCAP_AXI_RESET 76 +-#define SMMU_VCAP_AHB_RESET 77 +-#define VCAP_AHB_RESET 78 +-#define CSI_RDI_RESET 79 +-#define CSI_PIX_RESET 80 +-#define VCAP_NPL_RESET 81 +-#define VCAP_RESET 82 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,mmcc-msm8974.h b/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,mmcc-msm8974.h +deleted file mode 100644 +index d61b077e911a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,mmcc-msm8974.h ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2013, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_RESET_MSM_MMCC_8974_H +-#define _DT_BINDINGS_RESET_MSM_MMCC_8974_H +- +-#define SPDM_RESET 0 +-#define SPDM_RM_RESET 1 +-#define VENUS0_RESET 2 +-#define MDSS_RESET 3 +-#define CAMSS_PHY0_RESET 4 +-#define CAMSS_PHY1_RESET 5 +-#define CAMSS_PHY2_RESET 6 +-#define CAMSS_CSI0_RESET 7 +-#define CAMSS_CSI0PHY_RESET 8 +-#define CAMSS_CSI0RDI_RESET 9 +-#define CAMSS_CSI0PIX_RESET 10 +-#define CAMSS_CSI1_RESET 11 +-#define CAMSS_CSI1PHY_RESET 12 +-#define CAMSS_CSI1RDI_RESET 13 +-#define CAMSS_CSI1PIX_RESET 14 +-#define CAMSS_CSI2_RESET 15 +-#define CAMSS_CSI2PHY_RESET 16 +-#define CAMSS_CSI2RDI_RESET 17 +-#define CAMSS_CSI2PIX_RESET 18 +-#define CAMSS_CSI3_RESET 19 +-#define CAMSS_CSI3PHY_RESET 20 +-#define CAMSS_CSI3RDI_RESET 21 +-#define CAMSS_CSI3PIX_RESET 22 +-#define CAMSS_ISPIF_RESET 23 +-#define CAMSS_CCI_RESET 24 +-#define CAMSS_MCLK0_RESET 25 +-#define CAMSS_MCLK1_RESET 26 +-#define CAMSS_MCLK2_RESET 27 +-#define CAMSS_MCLK3_RESET 28 +-#define CAMSS_GP0_RESET 29 +-#define CAMSS_GP1_RESET 30 +-#define CAMSS_TOP_RESET 31 +-#define CAMSS_MICRO_RESET 32 +-#define CAMSS_JPEG_RESET 33 +-#define CAMSS_VFE_RESET 34 +-#define CAMSS_CSI_VFE0_RESET 35 +-#define CAMSS_CSI_VFE1_RESET 36 +-#define OXILI_RESET 37 +-#define OXILICX_RESET 38 +-#define OCMEMCX_RESET 39 +-#define MMSS_RBCRP_RESET 40 +-#define MMSSNOCAHB_RESET 41 +-#define MMSSNOCAXI_RESET 42 +-#define OCMEMNOC_RESET 43 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,sdm845-aoss.h b/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,sdm845-aoss.h +deleted file mode 100644 +index 476c5fc873b6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,sdm845-aoss.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2018 The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H +-#define _DT_BINDINGS_RESET_AOSS_SDM_845_H +- +-#define AOSS_CC_MSS_RESTART 0 +-#define AOSS_CC_CAMSS_RESTART 1 +-#define AOSS_CC_VENUS_RESTART 2 +-#define AOSS_CC_GPU_RESTART 3 +-#define AOSS_CC_DISPSS_RESTART 4 +-#define AOSS_CC_WCSS_RESTART 5 +-#define AOSS_CC_LPASS_RESTART 6 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,sdm845-pdc.h b/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,sdm845-pdc.h +deleted file mode 100644 +index 03a0c0eb8147..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,sdm845-pdc.h ++++ /dev/null +@@ -1,22 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2018 The Linux Foundation. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_RESET_PDC_SDM_845_H +-#define _DT_BINDINGS_RESET_PDC_SDM_845_H +- +-#define PDC_APPS_SYNC_RESET 0 +-#define PDC_SP_SYNC_RESET 1 +-#define PDC_AUDIO_SYNC_RESET 2 +-#define PDC_SENSORS_SYNC_RESET 3 +-#define PDC_AOP_SYNC_RESET 4 +-#define PDC_DEBUG_SYNC_RESET 5 +-#define PDC_GPU_SYNC_RESET 6 +-#define PDC_DISPLAY_SYNC_RESET 7 +-#define PDC_COMPUTE_SYNC_RESET 8 +-#define PDC_MODEM_SYNC_RESET 9 +-#define PDC_WLAN_RF_SYNC_RESET 10 +-#define PDC_WPSS_SYNC_RESET 11 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/raspberrypi,firmware-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/raspberrypi,firmware-reset.h +deleted file mode 100644 +index 1a4f4c792723..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/raspberrypi,firmware-reset.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2020 Nicolas Saenz Julienne +- * Author: Nicolas Saenz Julienne +- */ +- +-#ifndef _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H +-#define _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H +- +-#define RASPBERRYPI_FIRMWARE_RESET_ID_USB 0 +-#define RASPBERRYPI_FIRMWARE_RESET_NUM_IDS 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/realtek,rtd1195.h b/scripts/dtc/include-prefixes/dt-bindings/reset/realtek,rtd1195.h +deleted file mode 100644 +index 27902abf935b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/realtek,rtd1195.h ++++ /dev/null +@@ -1,74 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ +-/* +- * Realtek RTD1195 reset controllers +- * +- * Copyright (c) 2017 Andreas Färber +- */ +-#ifndef DT_BINDINGS_RESET_RTD1195_H +-#define DT_BINDINGS_RESET_RTD1195_H +- +-/* soft reset 1 */ +-#define RTD1195_RSTN_MISC 0 +-#define RTD1195_RSTN_RNG 1 +-#define RTD1195_RSTN_USB3_POW 2 +-#define RTD1195_RSTN_GSPI 3 +-#define RTD1195_RSTN_USB3_P0_MDIO 4 +-#define RTD1195_RSTN_VE_H265 5 +-#define RTD1195_RSTN_USB 6 +-#define RTD1195_RSTN_USB_PHY0 8 +-#define RTD1195_RSTN_USB_PHY1 9 +-#define RTD1195_RSTN_HDMIRX 11 +-#define RTD1195_RSTN_HDMI 12 +-#define RTD1195_RSTN_ETN 14 +-#define RTD1195_RSTN_AIO 15 +-#define RTD1195_RSTN_GPU 16 +-#define RTD1195_RSTN_VE_H264 17 +-#define RTD1195_RSTN_VE_JPEG 18 +-#define RTD1195_RSTN_TVE 19 +-#define RTD1195_RSTN_VO 20 +-#define RTD1195_RSTN_LVDS 21 +-#define RTD1195_RSTN_SE 22 +-#define RTD1195_RSTN_DCU 23 +-#define RTD1195_RSTN_DC_PHY 24 +-#define RTD1195_RSTN_CP 25 +-#define RTD1195_RSTN_MD 26 +-#define RTD1195_RSTN_TP 27 +-#define RTD1195_RSTN_AE 28 +-#define RTD1195_RSTN_NF 29 +-#define RTD1195_RSTN_MIPI 30 +- +-/* soft reset 2 */ +-#define RTD1195_RSTN_ACPU 0 +-#define RTD1195_RSTN_VCPU 1 +-#define RTD1195_RSTN_PCR 9 +-#define RTD1195_RSTN_CR 10 +-#define RTD1195_RSTN_EMMC 11 +-#define RTD1195_RSTN_SDIO 12 +-#define RTD1195_RSTN_I2C_5 18 +-#define RTD1195_RSTN_RTC 20 +-#define RTD1195_RSTN_I2C_4 23 +-#define RTD1195_RSTN_I2C_3 24 +-#define RTD1195_RSTN_I2C_2 25 +-#define RTD1195_RSTN_I2C_1 26 +-#define RTD1195_RSTN_UR1 28 +- +-/* soft reset 3 */ +-#define RTD1195_RSTN_SB2 0 +- +-/* iso soft reset */ +-#define RTD1195_ISO_RSTN_VFD 0 +-#define RTD1195_ISO_RSTN_IR 1 +-#define RTD1195_ISO_RSTN_CEC0 2 +-#define RTD1195_ISO_RSTN_CEC1 3 +-#define RTD1195_ISO_RSTN_DP 4 +-#define RTD1195_ISO_RSTN_CBUSTX 5 +-#define RTD1195_ISO_RSTN_CBUSRX 6 +-#define RTD1195_ISO_RSTN_EFUSE 7 +-#define RTD1195_ISO_RSTN_UR0 8 +-#define RTD1195_ISO_RSTN_GMAC 9 +-#define RTD1195_ISO_RSTN_GPHY 10 +-#define RTD1195_ISO_RSTN_I2C_0 11 +-#define RTD1195_ISO_RSTN_I2C_6 12 +-#define RTD1195_ISO_RSTN_CBUS 13 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/realtek,rtd1295.h b/scripts/dtc/include-prefixes/dt-bindings/reset/realtek,rtd1295.h +deleted file mode 100644 +index dd89e4c80264..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/realtek,rtd1295.h ++++ /dev/null +@@ -1,114 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ +-/* +- * Realtek RTD1295 reset controllers +- * +- * Copyright (c) 2017 Andreas Färber +- */ +-#ifndef DT_BINDINGS_RESET_RTD1295_H +-#define DT_BINDINGS_RESET_RTD1295_H +- +-/* soft reset 1 */ +-#define RTD1295_RSTN_MISC 0 +-#define RTD1295_RSTN_NAT 1 +-#define RTD1295_RSTN_USB3_PHY0_POW 2 +-#define RTD1295_RSTN_GSPI 3 +-#define RTD1295_RSTN_USB3_P0_MDIO 4 +-#define RTD1295_RSTN_SATA_0 5 +-#define RTD1295_RSTN_USB 6 +-#define RTD1295_RSTN_SATA_PHY_0 7 +-#define RTD1295_RSTN_USB_PHY0 8 +-#define RTD1295_RSTN_USB_PHY1 9 +-#define RTD1295_RSTN_SATA_PHY_POW_0 10 +-#define RTD1295_RSTN_SATA_FUNC_EXIST_0 11 +-#define RTD1295_RSTN_HDMI 12 +-#define RTD1295_RSTN_VE1 13 +-#define RTD1295_RSTN_VE2 14 +-#define RTD1295_RSTN_VE3 15 +-#define RTD1295_RSTN_ETN 16 +-#define RTD1295_RSTN_AIO 17 +-#define RTD1295_RSTN_GPU 18 +-#define RTD1295_RSTN_TVE 19 +-#define RTD1295_RSTN_VO 20 +-#define RTD1295_RSTN_LVDS 21 +-#define RTD1295_RSTN_SE 22 +-#define RTD1295_RSTN_DCU 23 +-#define RTD1295_RSTN_DC_PHY 24 +-#define RTD1295_RSTN_CP 25 +-#define RTD1295_RSTN_MD 26 +-#define RTD1295_RSTN_TP 27 +-#define RTD1295_RSTN_AE 28 +-#define RTD1295_RSTN_NF 29 +-#define RTD1295_RSTN_MIPI 30 +-#define RTD1295_RSTN_RSA 31 +- +-/* soft reset 2 */ +-#define RTD1295_RSTN_ACPU 0 +-#define RTD1295_RSTN_JPEG 1 +-#define RTD1295_RSTN_USB_PHY3 2 +-#define RTD1295_RSTN_USB_PHY2 3 +-#define RTD1295_RSTN_USB3_PHY1_POW 4 +-#define RTD1295_RSTN_USB3_P1_MDIO 5 +-#define RTD1295_RSTN_PCIE0_STITCH 6 +-#define RTD1295_RSTN_PCIE0_PHY 7 +-#define RTD1295_RSTN_PCIE0 8 +-#define RTD1295_RSTN_PCR_CNT 9 +-#define RTD1295_RSTN_CR 10 +-#define RTD1295_RSTN_EMMC 11 +-#define RTD1295_RSTN_SDIO 12 +-#define RTD1295_RSTN_PCIE0_CORE 13 +-#define RTD1295_RSTN_PCIE0_POWER 14 +-#define RTD1295_RSTN_PCIE0_NONSTICH 15 +-#define RTD1295_RSTN_PCIE1_PHY 16 +-#define RTD1295_RSTN_PCIE1 17 +-#define RTD1295_RSTN_I2C_5 18 +-#define RTD1295_RSTN_PCIE1_STITCH 19 +-#define RTD1295_RSTN_PCIE1_CORE 20 +-#define RTD1295_RSTN_PCIE1_POWER 21 +-#define RTD1295_RSTN_PCIE1_NONSTICH 22 +-#define RTD1295_RSTN_I2C_4 23 +-#define RTD1295_RSTN_I2C_3 24 +-#define RTD1295_RSTN_I2C_2 25 +-#define RTD1295_RSTN_I2C_1 26 +-#define RTD1295_RSTN_UR2 27 +-#define RTD1295_RSTN_UR1 28 +-#define RTD1295_RSTN_MISC_SC 29 +-#define RTD1295_RSTN_CBUS_TX 30 +-#define RTD1295_RSTN_SDS_PHY 31 +- +-/* soft reset 3 */ +-#define RTD1295_RSTN_SB2 0 +- +-/* soft reset 4 */ +-#define RTD1295_RSTN_DCPHY_CRT 0 +-#define RTD1295_RSTN_DCPHY_ALERT_RX 1 +-#define RTD1295_RSTN_DCPHY_PTR 2 +-#define RTD1295_RSTN_DCPHY_LDO 3 +-#define RTD1295_RSTN_DCPHY_SSC_DIG 4 +-#define RTD1295_RSTN_HDMIRX 5 +-#define RTD1295_RSTN_CBUSRX 6 +-#define RTD1295_RSTN_SATA_PHY_POW_1 7 +-#define RTD1295_RSTN_SATA_FUNC_EXIST_1 8 +-#define RTD1295_RSTN_SATA_PHY_1 9 +-#define RTD1295_RSTN_SATA_1 10 +-#define RTD1295_RSTN_FAN 11 +-#define RTD1295_RSTN_HDMIRX_WRAP 12 +-#define RTD1295_RSTN_PCIE0_PHY_MDIO 13 +-#define RTD1295_RSTN_PCIE1_PHY_MDIO 14 +-#define RTD1295_RSTN_DISP 15 +- +-/* iso reset */ +-#define RTD1295_ISO_RSTN_IR 1 +-#define RTD1295_ISO_RSTN_CEC0 2 +-#define RTD1295_ISO_RSTN_CEC1 3 +-#define RTD1295_ISO_RSTN_DP 4 +-#define RTD1295_ISO_RSTN_CBUSTX 5 +-#define RTD1295_ISO_RSTN_CBUSRX 6 +-#define RTD1295_ISO_RSTN_EFUSE 7 +-#define RTD1295_ISO_RSTN_UR0 8 +-#define RTD1295_ISO_RSTN_GMAC 9 +-#define RTD1295_ISO_RSTN_GPHY 10 +-#define RTD1295_ISO_RSTN_I2C_0 11 +-#define RTD1295_ISO_RSTN_I2C_1 12 +-#define RTD1295_ISO_RSTN_CBUS 13 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/snps,hsdk-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/snps,hsdk-reset.h +deleted file mode 100644 +index e1a643e4bc91..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/snps,hsdk-reset.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-/** +- * This header provides index for the HSDK reset controller. +- */ +-#ifndef _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK +-#define _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK +- +-#define HSDK_APB_RESET 0 +-#define HSDK_AXI_RESET 1 +-#define HSDK_ETH_RESET 2 +-#define HSDK_USB_RESET 3 +-#define HSDK_SDIO_RESET 4 +-#define HSDK_HDMI_RESET 5 +-#define HSDK_GFX_RESET 6 +-#define HSDK_DMAC_RESET 7 +-#define HSDK_EBI_RESET 8 +- +-#endif /*_DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK*/ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/stih407-resets.h b/scripts/dtc/include-prefixes/dt-bindings/reset/stih407-resets.h +deleted file mode 100644 +index f2a2c4f7f06a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/stih407-resets.h ++++ /dev/null +@@ -1,66 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for the reset controller +- * based peripheral powerdown requests on the STMicroelectronics +- * STiH407 SoC. +- */ +-#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407 +-#define _DT_BINDINGS_RESET_CONTROLLER_STIH407 +- +-/* Powerdown requests control 0 */ +-#define STIH407_EMISS_POWERDOWN 0 +-#define STIH407_NAND_POWERDOWN 1 +- +-/* Synp GMAC PowerDown */ +-#define STIH407_ETH1_POWERDOWN 2 +- +-/* Powerdown requests control 1 */ +-#define STIH407_USB3_POWERDOWN 3 +-#define STIH407_USB2_PORT1_POWERDOWN 4 +-#define STIH407_USB2_PORT0_POWERDOWN 5 +-#define STIH407_PCIE1_POWERDOWN 6 +-#define STIH407_PCIE0_POWERDOWN 7 +-#define STIH407_SATA1_POWERDOWN 8 +-#define STIH407_SATA0_POWERDOWN 9 +- +-/* Reset defines */ +-#define STIH407_ETH1_SOFTRESET 0 +-#define STIH407_MMC1_SOFTRESET 1 +-#define STIH407_PICOPHY_SOFTRESET 2 +-#define STIH407_IRB_SOFTRESET 3 +-#define STIH407_PCIE0_SOFTRESET 4 +-#define STIH407_PCIE1_SOFTRESET 5 +-#define STIH407_SATA0_SOFTRESET 6 +-#define STIH407_SATA1_SOFTRESET 7 +-#define STIH407_MIPHY0_SOFTRESET 8 +-#define STIH407_MIPHY1_SOFTRESET 9 +-#define STIH407_MIPHY2_SOFTRESET 10 +-#define STIH407_SATA0_PWR_SOFTRESET 11 +-#define STIH407_SATA1_PWR_SOFTRESET 12 +-#define STIH407_DELTA_SOFTRESET 13 +-#define STIH407_BLITTER_SOFTRESET 14 +-#define STIH407_HDTVOUT_SOFTRESET 15 +-#define STIH407_HDQVDP_SOFTRESET 16 +-#define STIH407_VDP_AUX_SOFTRESET 17 +-#define STIH407_COMPO_SOFTRESET 18 +-#define STIH407_HDMI_TX_PHY_SOFTRESET 19 +-#define STIH407_JPEG_DEC_SOFTRESET 20 +-#define STIH407_VP8_DEC_SOFTRESET 21 +-#define STIH407_GPU_SOFTRESET 22 +-#define STIH407_HVA_SOFTRESET 23 +-#define STIH407_ERAM_HVA_SOFTRESET 24 +-#define STIH407_LPM_SOFTRESET 25 +-#define STIH407_KEYSCAN_SOFTRESET 26 +-#define STIH407_USB2_PORT0_SOFTRESET 27 +-#define STIH407_USB2_PORT1_SOFTRESET 28 +-#define STIH407_ST231_AUD_SOFTRESET 29 +-#define STIH407_ST231_DMU_SOFTRESET 30 +-#define STIH407_ST231_GP0_SOFTRESET 31 +-#define STIH407_ST231_GP1_SOFTRESET 32 +- +-/* Picophy reset defines */ +-#define STIH407_PICOPHY0_RESET 0 +-#define STIH407_PICOPHY1_RESET 1 +-#define STIH407_PICOPHY2_RESET 2 +- +-#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/stih415-resets.h b/scripts/dtc/include-prefixes/dt-bindings/reset/stih415-resets.h +deleted file mode 100644 +index 96f7831a1db0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/stih415-resets.h ++++ /dev/null +@@ -1,28 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for the reset controller +- * based peripheral powerdown requests on the STMicroelectronics +- * STiH415 SoC. +- */ +-#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH415 +-#define _DT_BINDINGS_RESET_CONTROLLER_STIH415 +- +-#define STIH415_EMISS_POWERDOWN 0 +-#define STIH415_NAND_POWERDOWN 1 +-#define STIH415_KEYSCAN_POWERDOWN 2 +-#define STIH415_USB0_POWERDOWN 3 +-#define STIH415_USB1_POWERDOWN 4 +-#define STIH415_USB2_POWERDOWN 5 +-#define STIH415_SATA0_POWERDOWN 6 +-#define STIH415_SATA1_POWERDOWN 7 +-#define STIH415_PCIE_POWERDOWN 8 +- +-#define STIH415_ETH0_SOFTRESET 0 +-#define STIH415_ETH1_SOFTRESET 1 +-#define STIH415_IRB_SOFTRESET 2 +-#define STIH415_USB0_SOFTRESET 3 +-#define STIH415_USB1_SOFTRESET 4 +-#define STIH415_USB2_SOFTRESET 5 +-#define STIH415_KEYSCAN_SOFTRESET 6 +- +-#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH415 */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/stih416-resets.h b/scripts/dtc/include-prefixes/dt-bindings/reset/stih416-resets.h +deleted file mode 100644 +index f682c906ed5a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/stih416-resets.h ++++ /dev/null +@@ -1,52 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for the reset controller +- * based peripheral powerdown requests on the STMicroelectronics +- * STiH416 SoC. +- */ +-#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH416 +-#define _DT_BINDINGS_RESET_CONTROLLER_STIH416 +- +-#define STIH416_EMISS_POWERDOWN 0 +-#define STIH416_NAND_POWERDOWN 1 +-#define STIH416_KEYSCAN_POWERDOWN 2 +-#define STIH416_USB0_POWERDOWN 3 +-#define STIH416_USB1_POWERDOWN 4 +-#define STIH416_USB2_POWERDOWN 5 +-#define STIH416_USB3_POWERDOWN 6 +-#define STIH416_SATA0_POWERDOWN 7 +-#define STIH416_SATA1_POWERDOWN 8 +-#define STIH416_PCIE0_POWERDOWN 9 +-#define STIH416_PCIE1_POWERDOWN 10 +- +-#define STIH416_ETH0_SOFTRESET 0 +-#define STIH416_ETH1_SOFTRESET 1 +-#define STIH416_IRB_SOFTRESET 2 +-#define STIH416_USB0_SOFTRESET 3 +-#define STIH416_USB1_SOFTRESET 4 +-#define STIH416_USB2_SOFTRESET 5 +-#define STIH416_USB3_SOFTRESET 6 +-#define STIH416_SATA0_SOFTRESET 7 +-#define STIH416_SATA1_SOFTRESET 8 +-#define STIH416_PCIE0_SOFTRESET 9 +-#define STIH416_PCIE1_SOFTRESET 10 +-#define STIH416_AUD_DAC_SOFTRESET 11 +-#define STIH416_HDTVOUT_SOFTRESET 12 +-#define STIH416_VTAC_M_RX_SOFTRESET 13 +-#define STIH416_VTAC_A_RX_SOFTRESET 14 +-#define STIH416_SYNC_HD_SOFTRESET 15 +-#define STIH416_SYNC_SD_SOFTRESET 16 +-#define STIH416_BLITTER_SOFTRESET 17 +-#define STIH416_GPU_SOFTRESET 18 +-#define STIH416_VTAC_M_TX_SOFTRESET 19 +-#define STIH416_VTAC_A_TX_SOFTRESET 20 +-#define STIH416_VTG_AUX_SOFTRESET 21 +-#define STIH416_JPEG_DEC_SOFTRESET 22 +-#define STIH416_HVA_SOFTRESET 23 +-#define STIH416_COMPO_M_SOFTRESET 24 +-#define STIH416_COMPO_A_SOFTRESET 25 +-#define STIH416_VP8_DEC_SOFTRESET 26 +-#define STIH416_VTG_MAIN_SOFTRESET 27 +-#define STIH416_KEYSCAN_SOFTRESET 28 +- +-#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/stm32mp1-resets.h b/scripts/dtc/include-prefixes/dt-bindings/reset/stm32mp1-resets.h +deleted file mode 100644 +index f3a0ed317835..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/stm32mp1-resets.h ++++ /dev/null +@@ -1,123 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +-/* +- * Copyright (C) STMicroelectronics 2018 - All Rights Reserved +- * Author: Gabriel Fernandez for STMicroelectronics. +- */ +- +-#ifndef _DT_BINDINGS_STM32MP1_RESET_H_ +-#define _DT_BINDINGS_STM32MP1_RESET_H_ +- +-#define MCU_HOLD_BOOT_R 2144 +-#define LTDC_R 3072 +-#define DSI_R 3076 +-#define DDRPERFM_R 3080 +-#define USBPHY_R 3088 +-#define SPI6_R 3136 +-#define I2C4_R 3138 +-#define I2C6_R 3139 +-#define USART1_R 3140 +-#define STGEN_R 3156 +-#define GPIOZ_R 3200 +-#define CRYP1_R 3204 +-#define HASH1_R 3205 +-#define RNG1_R 3206 +-#define AXIM_R 3216 +-#define GPU_R 3269 +-#define ETHMAC_R 3274 +-#define FMC_R 3276 +-#define QSPI_R 3278 +-#define SDMMC1_R 3280 +-#define SDMMC2_R 3281 +-#define CRC1_R 3284 +-#define USBH_R 3288 +-#define MDMA_R 3328 +-#define MCU_R 8225 +-#define TIM2_R 19456 +-#define TIM3_R 19457 +-#define TIM4_R 19458 +-#define TIM5_R 19459 +-#define TIM6_R 19460 +-#define TIM7_R 19461 +-#define TIM12_R 16462 +-#define TIM13_R 16463 +-#define TIM14_R 16464 +-#define LPTIM1_R 19465 +-#define SPI2_R 19467 +-#define SPI3_R 19468 +-#define USART2_R 19470 +-#define USART3_R 19471 +-#define UART4_R 19472 +-#define UART5_R 19473 +-#define UART7_R 19474 +-#define UART8_R 19475 +-#define I2C1_R 19477 +-#define I2C2_R 19478 +-#define I2C3_R 19479 +-#define I2C5_R 19480 +-#define SPDIF_R 19482 +-#define CEC_R 19483 +-#define DAC12_R 19485 +-#define MDIO_R 19847 +-#define TIM1_R 19520 +-#define TIM8_R 19521 +-#define TIM15_R 19522 +-#define TIM16_R 19523 +-#define TIM17_R 19524 +-#define SPI1_R 19528 +-#define SPI4_R 19529 +-#define SPI5_R 19530 +-#define USART6_R 19533 +-#define SAI1_R 19536 +-#define SAI2_R 19537 +-#define SAI3_R 19538 +-#define DFSDM_R 19540 +-#define FDCAN_R 19544 +-#define LPTIM2_R 19584 +-#define LPTIM3_R 19585 +-#define LPTIM4_R 19586 +-#define LPTIM5_R 19587 +-#define SAI4_R 19592 +-#define SYSCFG_R 19595 +-#define VREF_R 19597 +-#define TMPSENS_R 19600 +-#define PMBCTRL_R 19601 +-#define DMA1_R 19648 +-#define DMA2_R 19649 +-#define DMAMUX_R 19650 +-#define ADC12_R 19653 +-#define USBO_R 19656 +-#define SDMMC3_R 19664 +-#define CAMITF_R 19712 +-#define CRYP2_R 19716 +-#define HASH2_R 19717 +-#define RNG2_R 19718 +-#define CRC2_R 19719 +-#define HSEM_R 19723 +-#define MBOX_R 19724 +-#define GPIOA_R 19776 +-#define GPIOB_R 19777 +-#define GPIOC_R 19778 +-#define GPIOD_R 19779 +-#define GPIOE_R 19780 +-#define GPIOF_R 19781 +-#define GPIOG_R 19782 +-#define GPIOH_R 19783 +-#define GPIOI_R 19784 +-#define GPIOJ_R 19785 +-#define GPIOK_R 19786 +- +-/* SCMI reset domain identifiers */ +-#define RST_SCMI0_SPI6 0 +-#define RST_SCMI0_I2C4 1 +-#define RST_SCMI0_I2C6 2 +-#define RST_SCMI0_USART1 3 +-#define RST_SCMI0_STGEN 4 +-#define RST_SCMI0_GPIOZ 5 +-#define RST_SCMI0_CRYP1 6 +-#define RST_SCMI0_HASH1 7 +-#define RST_SCMI0_RNG1 8 +-#define RST_SCMI0_MDMA 9 +-#define RST_SCMI0_MCU 10 +-#define RST_SCMI0_MCU_HOLD_BOOT 11 +- +-#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/sun4i-a10-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/reset/sun4i-a10-ccu.h +deleted file mode 100644 +index 5f4480bedc8a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/sun4i-a10-ccu.h ++++ /dev/null +@@ -1,69 +0,0 @@ +-/* +- * Copyright (C) 2017 Priit Laes +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_RST_SUN4I_A10_H +-#define _DT_BINDINGS_RST_SUN4I_A10_H +- +-#define RST_USB_PHY0 1 +-#define RST_USB_PHY1 2 +-#define RST_USB_PHY2 3 +-#define RST_GPS 4 +-#define RST_DE_BE0 5 +-#define RST_DE_BE1 6 +-#define RST_DE_FE0 7 +-#define RST_DE_FE1 8 +-#define RST_DE_MP 9 +-#define RST_TVE0 10 +-#define RST_TCON0 11 +-#define RST_TVE1 12 +-#define RST_TCON1 13 +-#define RST_CSI0 14 +-#define RST_CSI1 15 +-#define RST_VE 16 +-#define RST_ACE 17 +-#define RST_LVDS 18 +-#define RST_GPU 19 +-#define RST_HDMI_H 20 +-#define RST_HDMI_SYS 21 +-#define RST_HDMI_AUDIO_DMA 22 +- +-#endif /* DT_BINDINGS_RST_SUN4I_A10_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/sun50i-a100-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/reset/sun50i-a100-ccu.h +deleted file mode 100644 +index 55c0ada99885..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/sun50i-a100-ccu.h ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +-/* +- * Copyright (c) 2020 Yangtao Li +- */ +- +-#ifndef _DT_BINDINGS_RESET_SUN50I_A100_H_ +-#define _DT_BINDINGS_RESET_SUN50I_A100_H_ +- +-#define RST_MBUS 0 +-#define RST_BUS_DE 1 +-#define RST_BUS_G2D 2 +-#define RST_BUS_GPU 3 +-#define RST_BUS_CE 4 +-#define RST_BUS_VE 5 +-#define RST_BUS_DMA 6 +-#define RST_BUS_MSGBOX 7 +-#define RST_BUS_SPINLOCK 8 +-#define RST_BUS_HSTIMER 9 +-#define RST_BUS_DBG 10 +-#define RST_BUS_PSI 11 +-#define RST_BUS_PWM 12 +-#define RST_BUS_DRAM 13 +-#define RST_BUS_NAND 14 +-#define RST_BUS_MMC0 15 +-#define RST_BUS_MMC1 16 +-#define RST_BUS_MMC2 17 +-#define RST_BUS_UART0 18 +-#define RST_BUS_UART1 19 +-#define RST_BUS_UART2 20 +-#define RST_BUS_UART3 21 +-#define RST_BUS_UART4 22 +-#define RST_BUS_I2C0 23 +-#define RST_BUS_I2C1 24 +-#define RST_BUS_I2C2 25 +-#define RST_BUS_I2C3 26 +-#define RST_BUS_SPI0 27 +-#define RST_BUS_SPI1 28 +-#define RST_BUS_SPI2 29 +-#define RST_BUS_EMAC 30 +-#define RST_BUS_IR_RX 31 +-#define RST_BUS_IR_TX 32 +-#define RST_BUS_GPADC 33 +-#define RST_BUS_THS 34 +-#define RST_BUS_I2S0 35 +-#define RST_BUS_I2S1 36 +-#define RST_BUS_I2S2 37 +-#define RST_BUS_I2S3 38 +-#define RST_BUS_SPDIF 39 +-#define RST_BUS_DMIC 40 +-#define RST_BUS_AUDIO_CODEC 41 +-#define RST_USB_PHY0 42 +-#define RST_USB_PHY1 43 +-#define RST_BUS_OHCI0 44 +-#define RST_BUS_OHCI1 45 +-#define RST_BUS_EHCI0 46 +-#define RST_BUS_EHCI1 47 +-#define RST_BUS_OTG 48 +-#define RST_BUS_LRADC 49 +-#define RST_BUS_DPSS_TOP0 50 +-#define RST_BUS_DPSS_TOP1 51 +-#define RST_BUS_MIPI_DSI 52 +-#define RST_BUS_TCON_LCD 53 +-#define RST_BUS_LVDS 54 +-#define RST_BUS_LEDC 55 +-#define RST_BUS_CSI 56 +-#define RST_BUS_CSI_ISP 57 +- +-#endif /* _DT_BINDINGS_RESET_SUN50I_A100_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/sun50i-a100-r-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/reset/sun50i-a100-r-ccu.h +deleted file mode 100644 +index 737bf6f66626..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/sun50i-a100-r-ccu.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +-/* +- * Copyright (c) 2020 Yangtao Li +- */ +- +-#ifndef _DT_BINDINGS_RST_SUN50I_A100_R_CCU_H_ +-#define _DT_BINDINGS_RST_SUN50I_A100_R_CCU_H_ +- +-#define RST_R_APB1_TIMER 0 +-#define RST_R_APB1_BUS_PWM 1 +-#define RST_R_APB1_PPU 2 +-#define RST_R_APB2_UART 3 +-#define RST_R_APB2_I2C0 4 +-#define RST_R_APB2_I2C1 5 +-#define RST_R_APB1_BUS_IR 6 +-#define RST_R_AHB_BUS_RTC 7 +- +-#endif /* _DT_BINDINGS_RST_SUN50I_A100_R_CCU_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/sun50i-a64-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/reset/sun50i-a64-ccu.h +deleted file mode 100644 +index db60b29ddb11..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/sun50i-a64-ccu.h ++++ /dev/null +@@ -1,98 +0,0 @@ +-/* +- * Copyright (C) 2016 Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_ +-#define _DT_BINDINGS_RST_SUN50I_A64_H_ +- +-#define RST_USB_PHY0 0 +-#define RST_USB_PHY1 1 +-#define RST_USB_HSIC 2 +-#define RST_DRAM 3 +-#define RST_MBUS 4 +-#define RST_BUS_MIPI_DSI 5 +-#define RST_BUS_CE 6 +-#define RST_BUS_DMA 7 +-#define RST_BUS_MMC0 8 +-#define RST_BUS_MMC1 9 +-#define RST_BUS_MMC2 10 +-#define RST_BUS_NAND 11 +-#define RST_BUS_DRAM 12 +-#define RST_BUS_EMAC 13 +-#define RST_BUS_TS 14 +-#define RST_BUS_HSTIMER 15 +-#define RST_BUS_SPI0 16 +-#define RST_BUS_SPI1 17 +-#define RST_BUS_OTG 18 +-#define RST_BUS_EHCI0 19 +-#define RST_BUS_EHCI1 20 +-#define RST_BUS_OHCI0 21 +-#define RST_BUS_OHCI1 22 +-#define RST_BUS_VE 23 +-#define RST_BUS_TCON0 24 +-#define RST_BUS_TCON1 25 +-#define RST_BUS_DEINTERLACE 26 +-#define RST_BUS_CSI 27 +-#define RST_BUS_HDMI0 28 +-#define RST_BUS_HDMI1 29 +-#define RST_BUS_DE 30 +-#define RST_BUS_GPU 31 +-#define RST_BUS_MSGBOX 32 +-#define RST_BUS_SPINLOCK 33 +-#define RST_BUS_DBG 34 +-#define RST_BUS_LVDS 35 +-#define RST_BUS_CODEC 36 +-#define RST_BUS_SPDIF 37 +-#define RST_BUS_THS 38 +-#define RST_BUS_I2S0 39 +-#define RST_BUS_I2S1 40 +-#define RST_BUS_I2S2 41 +-#define RST_BUS_I2C0 42 +-#define RST_BUS_I2C1 43 +-#define RST_BUS_I2C2 44 +-#define RST_BUS_SCR 45 +-#define RST_BUS_UART0 46 +-#define RST_BUS_UART1 47 +-#define RST_BUS_UART2 48 +-#define RST_BUS_UART3 49 +-#define RST_BUS_UART4 50 +- +-#endif /* _DT_BINDINGS_RST_SUN50I_A64_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/sun50i-h6-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/reset/sun50i-h6-ccu.h +deleted file mode 100644 +index 81106f455097..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/sun50i-h6-ccu.h ++++ /dev/null +@@ -1,73 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ or MIT) +-/* +- * Copyright (C) 2017 Icenowy Zheng +- */ +- +-#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_ +-#define _DT_BINDINGS_RESET_SUN50I_H6_H_ +- +-#define RST_MBUS 0 +-#define RST_BUS_DE 1 +-#define RST_BUS_DEINTERLACE 2 +-#define RST_BUS_GPU 3 +-#define RST_BUS_CE 4 +-#define RST_BUS_VE 5 +-#define RST_BUS_EMCE 6 +-#define RST_BUS_VP9 7 +-#define RST_BUS_DMA 8 +-#define RST_BUS_MSGBOX 9 +-#define RST_BUS_SPINLOCK 10 +-#define RST_BUS_HSTIMER 11 +-#define RST_BUS_DBG 12 +-#define RST_BUS_PSI 13 +-#define RST_BUS_PWM 14 +-#define RST_BUS_IOMMU 15 +-#define RST_BUS_DRAM 16 +-#define RST_BUS_NAND 17 +-#define RST_BUS_MMC0 18 +-#define RST_BUS_MMC1 19 +-#define RST_BUS_MMC2 20 +-#define RST_BUS_UART0 21 +-#define RST_BUS_UART1 22 +-#define RST_BUS_UART2 23 +-#define RST_BUS_UART3 24 +-#define RST_BUS_I2C0 25 +-#define RST_BUS_I2C1 26 +-#define RST_BUS_I2C2 27 +-#define RST_BUS_I2C3 28 +-#define RST_BUS_SCR0 29 +-#define RST_BUS_SCR1 30 +-#define RST_BUS_SPI0 31 +-#define RST_BUS_SPI1 32 +-#define RST_BUS_EMAC 33 +-#define RST_BUS_TS 34 +-#define RST_BUS_IR_TX 35 +-#define RST_BUS_THS 36 +-#define RST_BUS_I2S0 37 +-#define RST_BUS_I2S1 38 +-#define RST_BUS_I2S2 39 +-#define RST_BUS_I2S3 40 +-#define RST_BUS_SPDIF 41 +-#define RST_BUS_DMIC 42 +-#define RST_BUS_AUDIO_HUB 43 +-#define RST_USB_PHY0 44 +-#define RST_USB_PHY1 45 +-#define RST_USB_PHY3 46 +-#define RST_USB_HSIC 47 +-#define RST_BUS_OHCI0 48 +-#define RST_BUS_OHCI3 49 +-#define RST_BUS_EHCI0 50 +-#define RST_BUS_XHCI 51 +-#define RST_BUS_EHCI3 52 +-#define RST_BUS_OTG 53 +-#define RST_BUS_PCIE 54 +-#define RST_PCIE_POWERUP 55 +-#define RST_BUS_HDMI 56 +-#define RST_BUS_HDMI_SUB 57 +-#define RST_BUS_TCON_TOP 58 +-#define RST_BUS_TCON_LCD0 59 +-#define RST_BUS_TCON_TV0 60 +-#define RST_BUS_CSI 61 +-#define RST_BUS_HDCP 62 +- +-#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/sun50i-h6-r-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/reset/sun50i-h6-r-ccu.h +deleted file mode 100644 +index 7950e799c76d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/sun50i-h6-r-ccu.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +-/* +- * Copyright (C) 2016 Icenowy Zheng +- */ +- +-#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ +-#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ +- +-#define RST_R_APB1_TIMER 0 +-#define RST_R_APB1_TWD 1 +-#define RST_R_APB1_PWM 2 +-#define RST_R_APB2_UART 3 +-#define RST_R_APB2_I2C 4 +-#define RST_R_APB1_IR 5 +-#define RST_R_APB1_W1 6 +-#define RST_R_APB2_RSB 7 +- +-#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/sun50i-h616-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/reset/sun50i-h616-ccu.h +deleted file mode 100644 +index cb6285a8d128..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/sun50i-h616-ccu.h ++++ /dev/null +@@ -1,70 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +-/* +- * Copyright (C) 2020 Arm Ltd. +- */ +- +-#ifndef _DT_BINDINGS_RESET_SUN50I_H616_H_ +-#define _DT_BINDINGS_RESET_SUN50I_H616_H_ +- +-#define RST_MBUS 0 +-#define RST_BUS_DE 1 +-#define RST_BUS_DEINTERLACE 2 +-#define RST_BUS_GPU 3 +-#define RST_BUS_CE 4 +-#define RST_BUS_VE 5 +-#define RST_BUS_DMA 6 +-#define RST_BUS_HSTIMER 7 +-#define RST_BUS_DBG 8 +-#define RST_BUS_PSI 9 +-#define RST_BUS_PWM 10 +-#define RST_BUS_IOMMU 11 +-#define RST_BUS_DRAM 12 +-#define RST_BUS_NAND 13 +-#define RST_BUS_MMC0 14 +-#define RST_BUS_MMC1 15 +-#define RST_BUS_MMC2 16 +-#define RST_BUS_UART0 17 +-#define RST_BUS_UART1 18 +-#define RST_BUS_UART2 19 +-#define RST_BUS_UART3 20 +-#define RST_BUS_UART4 21 +-#define RST_BUS_UART5 22 +-#define RST_BUS_I2C0 23 +-#define RST_BUS_I2C1 24 +-#define RST_BUS_I2C2 25 +-#define RST_BUS_I2C3 26 +-#define RST_BUS_I2C4 27 +-#define RST_BUS_SPI0 28 +-#define RST_BUS_SPI1 29 +-#define RST_BUS_EMAC0 30 +-#define RST_BUS_EMAC1 31 +-#define RST_BUS_TS 32 +-#define RST_BUS_THS 33 +-#define RST_BUS_SPDIF 34 +-#define RST_BUS_DMIC 35 +-#define RST_BUS_AUDIO_CODEC 36 +-#define RST_BUS_AUDIO_HUB 37 +-#define RST_USB_PHY0 38 +-#define RST_USB_PHY1 39 +-#define RST_USB_PHY2 40 +-#define RST_USB_PHY3 41 +-#define RST_BUS_OHCI0 42 +-#define RST_BUS_OHCI1 43 +-#define RST_BUS_OHCI2 44 +-#define RST_BUS_OHCI3 45 +-#define RST_BUS_EHCI0 46 +-#define RST_BUS_EHCI1 47 +-#define RST_BUS_EHCI2 48 +-#define RST_BUS_EHCI3 49 +-#define RST_BUS_OTG 50 +-#define RST_BUS_HDMI 51 +-#define RST_BUS_HDMI_SUB 52 +-#define RST_BUS_TCON_TOP 53 +-#define RST_BUS_TCON_TV0 54 +-#define RST_BUS_TCON_TV1 55 +-#define RST_BUS_TVE_TOP 56 +-#define RST_BUS_TVE0 57 +-#define RST_BUS_HDCP 58 +-#define RST_BUS_KEYADC 59 +- +-#endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/sun5i-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/reset/sun5i-ccu.h +deleted file mode 100644 +index 40cc22ae7630..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/sun5i-ccu.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * Copyright 2016 Maxime Ripard +- * +- * Maxime Ripard +- */ +- +-#ifndef _RST_SUN5I_H_ +-#define _RST_SUN5I_H_ +- +-#define RST_USB_PHY0 0 +-#define RST_USB_PHY1 1 +-#define RST_GPS 2 +-#define RST_DE_BE 3 +-#define RST_DE_FE 4 +-#define RST_TVE 5 +-#define RST_LCD 6 +-#define RST_CSI 7 +-#define RST_VE 8 +-#define RST_GPU 9 +-#define RST_IEP 10 +- +-#endif /* _RST_SUN5I_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/sun6i-a31-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/reset/sun6i-a31-ccu.h +deleted file mode 100644 +index fbff365ed6e1..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/sun6i-a31-ccu.h ++++ /dev/null +@@ -1,106 +0,0 @@ +-/* +- * Copyright (C) 2016 Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_RST_SUN6I_A31_H_ +-#define _DT_BINDINGS_RST_SUN6I_A31_H_ +- +-#define RST_USB_PHY0 0 +-#define RST_USB_PHY1 1 +-#define RST_USB_PHY2 2 +- +-#define RST_AHB1_MIPI_DSI 3 +-#define RST_AHB1_SS 4 +-#define RST_AHB1_DMA 5 +-#define RST_AHB1_MMC0 6 +-#define RST_AHB1_MMC1 7 +-#define RST_AHB1_MMC2 8 +-#define RST_AHB1_MMC3 9 +-#define RST_AHB1_NAND1 10 +-#define RST_AHB1_NAND0 11 +-#define RST_AHB1_SDRAM 12 +-#define RST_AHB1_EMAC 13 +-#define RST_AHB1_TS 14 +-#define RST_AHB1_HSTIMER 15 +-#define RST_AHB1_SPI0 16 +-#define RST_AHB1_SPI1 17 +-#define RST_AHB1_SPI2 18 +-#define RST_AHB1_SPI3 19 +-#define RST_AHB1_OTG 20 +-#define RST_AHB1_EHCI0 21 +-#define RST_AHB1_EHCI1 22 +-#define RST_AHB1_OHCI0 23 +-#define RST_AHB1_OHCI1 24 +-#define RST_AHB1_OHCI2 25 +-#define RST_AHB1_VE 26 +-#define RST_AHB1_LCD0 27 +-#define RST_AHB1_LCD1 28 +-#define RST_AHB1_CSI 29 +-#define RST_AHB1_HDMI 30 +-#define RST_AHB1_BE0 31 +-#define RST_AHB1_BE1 32 +-#define RST_AHB1_FE0 33 +-#define RST_AHB1_FE1 34 +-#define RST_AHB1_MP 35 +-#define RST_AHB1_GPU 36 +-#define RST_AHB1_DEU0 37 +-#define RST_AHB1_DEU1 38 +-#define RST_AHB1_DRC0 39 +-#define RST_AHB1_DRC1 40 +-#define RST_AHB1_LVDS 41 +- +-#define RST_APB1_CODEC 42 +-#define RST_APB1_SPDIF 43 +-#define RST_APB1_DIGITAL_MIC 44 +-#define RST_APB1_DAUDIO0 45 +-#define RST_APB1_DAUDIO1 46 +-#define RST_APB2_I2C0 47 +-#define RST_APB2_I2C1 48 +-#define RST_APB2_I2C2 49 +-#define RST_APB2_I2C3 50 +-#define RST_APB2_UART0 51 +-#define RST_APB2_UART1 52 +-#define RST_APB2_UART2 53 +-#define RST_APB2_UART3 54 +-#define RST_APB2_UART4 55 +-#define RST_APB2_UART5 56 +- +-#endif /* _DT_BINDINGS_RST_SUN6I_A31_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-a23-a33-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-a23-a33-ccu.h +deleted file mode 100644 +index 6121f2b0cd0a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-a23-a33-ccu.h ++++ /dev/null +@@ -1,87 +0,0 @@ +-/* +- * Copyright (C) 2016 Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_RST_SUN8I_A23_A33_H_ +-#define _DT_BINDINGS_RST_SUN8I_A23_A33_H_ +- +-#define RST_USB_PHY0 0 +-#define RST_USB_PHY1 1 +-#define RST_USB_HSIC 2 +-#define RST_MBUS 3 +-#define RST_BUS_MIPI_DSI 4 +-#define RST_BUS_SS 5 +-#define RST_BUS_DMA 6 +-#define RST_BUS_MMC0 7 +-#define RST_BUS_MMC1 8 +-#define RST_BUS_MMC2 9 +-#define RST_BUS_NAND 10 +-#define RST_BUS_DRAM 11 +-#define RST_BUS_HSTIMER 12 +-#define RST_BUS_SPI0 13 +-#define RST_BUS_SPI1 14 +-#define RST_BUS_OTG 15 +-#define RST_BUS_EHCI 16 +-#define RST_BUS_OHCI 17 +-#define RST_BUS_VE 18 +-#define RST_BUS_LCD 19 +-#define RST_BUS_CSI 20 +-#define RST_BUS_DE_BE 21 +-#define RST_BUS_DE_FE 22 +-#define RST_BUS_GPU 23 +-#define RST_BUS_MSGBOX 24 +-#define RST_BUS_SPINLOCK 25 +-#define RST_BUS_DRC 26 +-#define RST_BUS_SAT 27 +-#define RST_BUS_LVDS 28 +-#define RST_BUS_CODEC 29 +-#define RST_BUS_I2S0 30 +-#define RST_BUS_I2S1 31 +-#define RST_BUS_I2C0 32 +-#define RST_BUS_I2C1 33 +-#define RST_BUS_I2C2 34 +-#define RST_BUS_UART0 35 +-#define RST_BUS_UART1 36 +-#define RST_BUS_UART2 37 +-#define RST_BUS_UART3 38 +-#define RST_BUS_UART4 39 +- +-#endif /* _DT_BINDINGS_RST_SUN8I_A23_A33_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-a83t-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-a83t-ccu.h +deleted file mode 100644 +index 784f6e11664e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-a83t-ccu.h ++++ /dev/null +@@ -1,98 +0,0 @@ +-/* +- * Copyright (C) 2017 Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ +-#define _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ +- +-#define RST_USB_PHY0 0 +-#define RST_USB_PHY1 1 +-#define RST_USB_HSIC 2 +- +-#define RST_DRAM 3 +-#define RST_MBUS 4 +- +-#define RST_BUS_MIPI_DSI 5 +-#define RST_BUS_SS 6 +-#define RST_BUS_DMA 7 +-#define RST_BUS_MMC0 8 +-#define RST_BUS_MMC1 9 +-#define RST_BUS_MMC2 10 +-#define RST_BUS_NAND 11 +-#define RST_BUS_DRAM 12 +-#define RST_BUS_EMAC 13 +-#define RST_BUS_HSTIMER 14 +-#define RST_BUS_SPI0 15 +-#define RST_BUS_SPI1 16 +-#define RST_BUS_OTG 17 +-#define RST_BUS_EHCI0 18 +-#define RST_BUS_EHCI1 19 +-#define RST_BUS_OHCI0 20 +- +-#define RST_BUS_VE 21 +-#define RST_BUS_TCON0 22 +-#define RST_BUS_TCON1 23 +-#define RST_BUS_CSI 24 +-#define RST_BUS_HDMI0 25 +-#define RST_BUS_HDMI1 26 +-#define RST_BUS_DE 27 +-#define RST_BUS_GPU 28 +-#define RST_BUS_MSGBOX 29 +-#define RST_BUS_SPINLOCK 30 +- +-#define RST_BUS_LVDS 31 +- +-#define RST_BUS_SPDIF 32 +-#define RST_BUS_I2S0 33 +-#define RST_BUS_I2S1 34 +-#define RST_BUS_I2S2 35 +-#define RST_BUS_TDM 36 +- +-#define RST_BUS_I2C0 37 +-#define RST_BUS_I2C1 38 +-#define RST_BUS_I2C2 39 +-#define RST_BUS_UART0 40 +-#define RST_BUS_UART1 41 +-#define RST_BUS_UART2 42 +-#define RST_BUS_UART3 43 +-#define RST_BUS_UART4 44 +- +-#endif /* _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-de2.h b/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-de2.h +deleted file mode 100644 +index 1c36a6ac86d6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-de2.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* +- * Copyright (C) 2016 Icenowy Zheng +- * +- * SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- */ +- +-#ifndef _DT_BINDINGS_RESET_SUN8I_DE2_H_ +-#define _DT_BINDINGS_RESET_SUN8I_DE2_H_ +- +-#define RST_MIXER0 0 +-#define RST_MIXER1 1 +-#define RST_WB 2 +-#define RST_ROT 3 +- +-#endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-h3-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-h3-ccu.h +deleted file mode 100644 +index 484c2a22919d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-h3-ccu.h ++++ /dev/null +@@ -1,106 +0,0 @@ +-/* +- * Copyright (C) 2016 Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_RST_SUN8I_H3_H_ +-#define _DT_BINDINGS_RST_SUN8I_H3_H_ +- +-#define RST_USB_PHY0 0 +-#define RST_USB_PHY1 1 +-#define RST_USB_PHY2 2 +-#define RST_USB_PHY3 3 +- +-#define RST_MBUS 4 +- +-#define RST_BUS_CE 5 +-#define RST_BUS_DMA 6 +-#define RST_BUS_MMC0 7 +-#define RST_BUS_MMC1 8 +-#define RST_BUS_MMC2 9 +-#define RST_BUS_NAND 10 +-#define RST_BUS_DRAM 11 +-#define RST_BUS_EMAC 12 +-#define RST_BUS_TS 13 +-#define RST_BUS_HSTIMER 14 +-#define RST_BUS_SPI0 15 +-#define RST_BUS_SPI1 16 +-#define RST_BUS_OTG 17 +-#define RST_BUS_EHCI0 18 +-#define RST_BUS_EHCI1 19 +-#define RST_BUS_EHCI2 20 +-#define RST_BUS_EHCI3 21 +-#define RST_BUS_OHCI0 22 +-#define RST_BUS_OHCI1 23 +-#define RST_BUS_OHCI2 24 +-#define RST_BUS_OHCI3 25 +-#define RST_BUS_VE 26 +-#define RST_BUS_TCON0 27 +-#define RST_BUS_TCON1 28 +-#define RST_BUS_DEINTERLACE 29 +-#define RST_BUS_CSI 30 +-#define RST_BUS_TVE 31 +-#define RST_BUS_HDMI0 32 +-#define RST_BUS_HDMI1 33 +-#define RST_BUS_DE 34 +-#define RST_BUS_GPU 35 +-#define RST_BUS_MSGBOX 36 +-#define RST_BUS_SPINLOCK 37 +-#define RST_BUS_DBG 38 +-#define RST_BUS_EPHY 39 +-#define RST_BUS_CODEC 40 +-#define RST_BUS_SPDIF 41 +-#define RST_BUS_THS 42 +-#define RST_BUS_I2S0 43 +-#define RST_BUS_I2S1 44 +-#define RST_BUS_I2S2 45 +-#define RST_BUS_I2C0 46 +-#define RST_BUS_I2C1 47 +-#define RST_BUS_I2C2 48 +-#define RST_BUS_UART0 49 +-#define RST_BUS_UART1 50 +-#define RST_BUS_UART2 51 +-#define RST_BUS_UART3 52 +-#define RST_BUS_SCR0 53 +- +-/* New resets imported in H5 */ +-#define RST_BUS_SCR1 54 +- +-#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-r-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-r-ccu.h +deleted file mode 100644 +index 4ba64f3d6fc9..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-r-ccu.h ++++ /dev/null +@@ -1,53 +0,0 @@ +-/* +- * Copyright (C) 2016 Icenowy Zheng +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_RST_SUN8I_R_CCU_H_ +-#define _DT_BINDINGS_RST_SUN8I_R_CCU_H_ +- +-#define RST_APB0_IR 0 +-#define RST_APB0_TIMER 1 +-#define RST_APB0_RSB 2 +-#define RST_APB0_UART 3 +-/* 4 is reserved for RST_APB0_W1 on A31 */ +-#define RST_APB0_I2C 5 +- +-#endif /* _DT_BINDINGS_RST_SUN8I_R_CCU_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-r40-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-r40-ccu.h +deleted file mode 100644 +index c5ebcf6672e4..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-r40-ccu.h ++++ /dev/null +@@ -1,130 +0,0 @@ +-/* +- * Copyright (C) 2017 Icenowy Zheng +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_RST_SUN8I_R40_H_ +-#define _DT_BINDINGS_RST_SUN8I_R40_H_ +- +-#define RST_USB_PHY0 0 +-#define RST_USB_PHY1 1 +-#define RST_USB_PHY2 2 +- +-#define RST_DRAM 3 +-#define RST_MBUS 4 +- +-#define RST_BUS_MIPI_DSI 5 +-#define RST_BUS_CE 6 +-#define RST_BUS_DMA 7 +-#define RST_BUS_MMC0 8 +-#define RST_BUS_MMC1 9 +-#define RST_BUS_MMC2 10 +-#define RST_BUS_MMC3 11 +-#define RST_BUS_NAND 12 +-#define RST_BUS_DRAM 13 +-#define RST_BUS_EMAC 14 +-#define RST_BUS_TS 15 +-#define RST_BUS_HSTIMER 16 +-#define RST_BUS_SPI0 17 +-#define RST_BUS_SPI1 18 +-#define RST_BUS_SPI2 19 +-#define RST_BUS_SPI3 20 +-#define RST_BUS_SATA 21 +-#define RST_BUS_OTG 22 +-#define RST_BUS_EHCI0 23 +-#define RST_BUS_EHCI1 24 +-#define RST_BUS_EHCI2 25 +-#define RST_BUS_OHCI0 26 +-#define RST_BUS_OHCI1 27 +-#define RST_BUS_OHCI2 28 +-#define RST_BUS_VE 29 +-#define RST_BUS_MP 30 +-#define RST_BUS_DEINTERLACE 31 +-#define RST_BUS_CSI0 32 +-#define RST_BUS_CSI1 33 +-#define RST_BUS_HDMI0 34 +-#define RST_BUS_HDMI1 35 +-#define RST_BUS_DE 36 +-#define RST_BUS_TVE0 37 +-#define RST_BUS_TVE1 38 +-#define RST_BUS_TVE_TOP 39 +-#define RST_BUS_GMAC 40 +-#define RST_BUS_GPU 41 +-#define RST_BUS_TVD0 42 +-#define RST_BUS_TVD1 43 +-#define RST_BUS_TVD2 44 +-#define RST_BUS_TVD3 45 +-#define RST_BUS_TVD_TOP 46 +-#define RST_BUS_TCON_LCD0 47 +-#define RST_BUS_TCON_LCD1 48 +-#define RST_BUS_TCON_TV0 49 +-#define RST_BUS_TCON_TV1 50 +-#define RST_BUS_TCON_TOP 51 +-#define RST_BUS_DBG 52 +-#define RST_BUS_LVDS 53 +-#define RST_BUS_CODEC 54 +-#define RST_BUS_SPDIF 55 +-#define RST_BUS_AC97 56 +-#define RST_BUS_IR0 57 +-#define RST_BUS_IR1 58 +-#define RST_BUS_THS 59 +-#define RST_BUS_KEYPAD 60 +-#define RST_BUS_I2S0 61 +-#define RST_BUS_I2S1 62 +-#define RST_BUS_I2S2 63 +-#define RST_BUS_I2C0 64 +-#define RST_BUS_I2C1 65 +-#define RST_BUS_I2C2 66 +-#define RST_BUS_I2C3 67 +-#define RST_BUS_CAN 68 +-#define RST_BUS_SCR 69 +-#define RST_BUS_PS20 70 +-#define RST_BUS_PS21 71 +-#define RST_BUS_I2C4 72 +-#define RST_BUS_UART0 73 +-#define RST_BUS_UART1 74 +-#define RST_BUS_UART2 75 +-#define RST_BUS_UART3 76 +-#define RST_BUS_UART4 77 +-#define RST_BUS_UART5 78 +-#define RST_BUS_UART6 79 +-#define RST_BUS_UART7 80 +- +-#endif /* _DT_BINDINGS_RST_SUN8I_R40_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-v3s-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-v3s-ccu.h +deleted file mode 100644 +index b6790173afd6..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/sun8i-v3s-ccu.h ++++ /dev/null +@@ -1,81 +0,0 @@ +-/* +- * Copyright (C) 2016 Icenowy Zheng +- * +- * Based on sun8i-v3s-ccu.h, which is +- * Copyright (C) 2016 Maxime Ripard +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_RST_SUN8I_V3S_H_ +-#define _DT_BINDINGS_RST_SUN8I_V3S_H_ +- +-#define RST_USB_PHY0 0 +- +-#define RST_MBUS 1 +- +-#define RST_BUS_CE 5 +-#define RST_BUS_DMA 6 +-#define RST_BUS_MMC0 7 +-#define RST_BUS_MMC1 8 +-#define RST_BUS_MMC2 9 +-#define RST_BUS_DRAM 11 +-#define RST_BUS_EMAC 12 +-#define RST_BUS_HSTIMER 14 +-#define RST_BUS_SPI0 15 +-#define RST_BUS_OTG 17 +-#define RST_BUS_EHCI0 18 +-#define RST_BUS_OHCI0 22 +-#define RST_BUS_VE 26 +-#define RST_BUS_TCON0 27 +-#define RST_BUS_CSI 30 +-#define RST_BUS_DE 34 +-#define RST_BUS_DBG 38 +-#define RST_BUS_EPHY 39 +-#define RST_BUS_CODEC 40 +-#define RST_BUS_I2C0 46 +-#define RST_BUS_I2C1 47 +-#define RST_BUS_UART0 49 +-#define RST_BUS_UART1 50 +-#define RST_BUS_UART2 51 +- +-/* Reset lines not available on V3s */ +-#define RST_BUS_I2S0 52 +- +-#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/sun9i-a80-ccu.h b/scripts/dtc/include-prefixes/dt-bindings/reset/sun9i-a80-ccu.h +deleted file mode 100644 +index 4b8df4b36788..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/sun9i-a80-ccu.h ++++ /dev/null +@@ -1,102 +0,0 @@ +-/* +- * Copyright (C) 2016 Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ +-#define _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ +- +-#define RST_BUS_FD 0 +-#define RST_BUS_VE 1 +-#define RST_BUS_GPU_CTRL 2 +-#define RST_BUS_SS 3 +-#define RST_BUS_MMC 4 +-#define RST_BUS_NAND0 5 +-#define RST_BUS_NAND1 6 +-#define RST_BUS_SDRAM 7 +-#define RST_BUS_SATA 8 +-#define RST_BUS_TS 9 +-#define RST_BUS_SPI0 10 +-#define RST_BUS_SPI1 11 +-#define RST_BUS_SPI2 12 +-#define RST_BUS_SPI3 13 +- +-#define RST_BUS_OTG 14 +-#define RST_BUS_OTG_PHY 15 +-#define RST_BUS_MIPI_HSI 16 +-#define RST_BUS_GMAC 17 +-#define RST_BUS_MSGBOX 18 +-#define RST_BUS_SPINLOCK 19 +-#define RST_BUS_HSTIMER 20 +-#define RST_BUS_DMA 21 +- +-#define RST_BUS_LCD0 22 +-#define RST_BUS_LCD1 23 +-#define RST_BUS_EDP 24 +-#define RST_BUS_LVDS 25 +-#define RST_BUS_CSI 26 +-#define RST_BUS_HDMI0 27 +-#define RST_BUS_HDMI1 28 +-#define RST_BUS_DE 29 +-#define RST_BUS_MP 30 +-#define RST_BUS_GPU 31 +-#define RST_BUS_MIPI_DSI 32 +- +-#define RST_BUS_SPDIF 33 +-#define RST_BUS_AC97 34 +-#define RST_BUS_I2S0 35 +-#define RST_BUS_I2S1 36 +-#define RST_BUS_LRADC 37 +-#define RST_BUS_GPADC 38 +-#define RST_BUS_CIR_TX 39 +- +-#define RST_BUS_I2C0 40 +-#define RST_BUS_I2C1 41 +-#define RST_BUS_I2C2 42 +-#define RST_BUS_I2C3 43 +-#define RST_BUS_I2C4 44 +-#define RST_BUS_UART0 45 +-#define RST_BUS_UART1 46 +-#define RST_BUS_UART2 47 +-#define RST_BUS_UART3 48 +-#define RST_BUS_UART4 49 +-#define RST_BUS_UART5 50 +- +-#endif /* _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/sun9i-a80-de.h b/scripts/dtc/include-prefixes/dt-bindings/reset/sun9i-a80-de.h +deleted file mode 100644 +index 205072770171..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/sun9i-a80-de.h ++++ /dev/null +@@ -1,58 +0,0 @@ +-/* +- * Copyright (C) 2016 Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ +-#define _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ +- +-#define RST_FE0 0 +-#define RST_FE1 1 +-#define RST_FE2 2 +-#define RST_DEU0 3 +-#define RST_DEU1 4 +-#define RST_BE0 5 +-#define RST_BE1 6 +-#define RST_BE2 7 +-#define RST_DRC0 8 +-#define RST_DRC1 9 +-#define RST_MERGE 10 +- +-#endif /* _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/sun9i-a80-usb.h b/scripts/dtc/include-prefixes/dt-bindings/reset/sun9i-a80-usb.h +deleted file mode 100644 +index ee492864c2aa..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/sun9i-a80-usb.h ++++ /dev/null +@@ -1,56 +0,0 @@ +-/* +- * Copyright (C) 2016 Chen-Yu Tsai +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ +-#define _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ +- +-#define RST_USB0_HCI 0 +-#define RST_USB1_HCI 1 +-#define RST_USB2_HCI 2 +- +-#define RST_USB0_PHY 3 +-#define RST_USB1_HSIC 4 +-#define RST_USB1_PHY 5 +-#define RST_USB2_HSIC 6 +-#define RST_USB2_PHY 7 +- +-#endif /* _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/suniv-ccu-f1c100s.h b/scripts/dtc/include-prefixes/dt-bindings/reset/suniv-ccu-f1c100s.h +deleted file mode 100644 +index 6a4b4385fe5a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/suniv-ccu-f1c100s.h ++++ /dev/null +@@ -1,38 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- * +- * Copyright (C) 2018 Icenowy Zheng +- * +- */ +- +-#ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_ +-#define _DT_BINDINGS_RST_SUNIV_F1C100S_H_ +- +-#define RST_USB_PHY0 0 +-#define RST_BUS_DMA 1 +-#define RST_BUS_MMC0 2 +-#define RST_BUS_MMC1 3 +-#define RST_BUS_DRAM 4 +-#define RST_BUS_SPI0 5 +-#define RST_BUS_SPI1 6 +-#define RST_BUS_OTG 7 +-#define RST_BUS_VE 8 +-#define RST_BUS_LCD 9 +-#define RST_BUS_DEINTERLACE 10 +-#define RST_BUS_CSI 11 +-#define RST_BUS_TVD 12 +-#define RST_BUS_TVE 13 +-#define RST_BUS_DE_BE 14 +-#define RST_BUS_DE_FE 15 +-#define RST_BUS_CODEC 16 +-#define RST_BUS_SPDIF 17 +-#define RST_BUS_IR 18 +-#define RST_BUS_RSB 19 +-#define RST_BUS_I2S0 20 +-#define RST_BUS_I2C0 21 +-#define RST_BUS_I2C1 22 +-#define RST_BUS_I2C2 23 +-#define RST_BUS_UART0 24 +-#define RST_BUS_UART1 25 +-#define RST_BUS_UART2 26 +- +-#endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/tegra124-car.h b/scripts/dtc/include-prefixes/dt-bindings/reset/tegra124-car.h +deleted file mode 100644 +index 97d2f3db82bf..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/tegra124-car.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides Tegra124-specific constants for binding +- * nvidia,tegra124-car. +- */ +- +-#ifndef _DT_BINDINGS_RESET_TEGRA124_CAR_H +-#define _DT_BINDINGS_RESET_TEGRA124_CAR_H +- +-#define TEGRA124_RESET(x) (6 * 32 + (x)) +-#define TEGRA124_RST_DFLL_DVCO TEGRA124_RESET(0) +- +-#endif /* _DT_BINDINGS_RESET_TEGRA124_CAR_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/tegra186-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/tegra186-reset.h +deleted file mode 100644 +index 3c60e3e03eb5..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/tegra186-reset.h ++++ /dev/null +@@ -1,206 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. +- */ +- +-#ifndef _ABI_MACH_T186_RESET_T186_H_ +-#define _ABI_MACH_T186_RESET_T186_H_ +- +- +-#define TEGRA186_RESET_ACTMON 0 +-#define TEGRA186_RESET_AFI 1 +-#define TEGRA186_RESET_CEC 2 +-#define TEGRA186_RESET_CSITE 3 +-#define TEGRA186_RESET_DP2 4 +-#define TEGRA186_RESET_DPAUX 5 +-#define TEGRA186_RESET_DSI 6 +-#define TEGRA186_RESET_DSIB 7 +-#define TEGRA186_RESET_DTV 8 +-#define TEGRA186_RESET_DVFS 9 +-#define TEGRA186_RESET_ENTROPY 10 +-#define TEGRA186_RESET_EXTPERIPH1 11 +-#define TEGRA186_RESET_EXTPERIPH2 12 +-#define TEGRA186_RESET_EXTPERIPH3 13 +-#define TEGRA186_RESET_GPU 14 +-#define TEGRA186_RESET_HDA 15 +-#define TEGRA186_RESET_HDA2CODEC_2X 16 +-#define TEGRA186_RESET_HDA2HDMICODEC 17 +-#define TEGRA186_RESET_HOST1X 18 +-#define TEGRA186_RESET_I2C1 19 +-#define TEGRA186_RESET_I2C2 20 +-#define TEGRA186_RESET_I2C3 21 +-#define TEGRA186_RESET_I2C4 22 +-#define TEGRA186_RESET_I2C5 23 +-#define TEGRA186_RESET_I2C6 24 +-#define TEGRA186_RESET_ISP 25 +-#define TEGRA186_RESET_KFUSE 26 +-#define TEGRA186_RESET_LA 27 +-#define TEGRA186_RESET_MIPI_CAL 28 +-#define TEGRA186_RESET_PCIE 29 +-#define TEGRA186_RESET_PCIEXCLK 30 +-#define TEGRA186_RESET_SATA 31 +-#define TEGRA186_RESET_SATACOLD 32 +-#define TEGRA186_RESET_SDMMC1 33 +-#define TEGRA186_RESET_SDMMC2 34 +-#define TEGRA186_RESET_SDMMC3 35 +-#define TEGRA186_RESET_SDMMC4 36 +-#define TEGRA186_RESET_SE 37 +-#define TEGRA186_RESET_SOC_THERM 38 +-#define TEGRA186_RESET_SOR0 39 +-#define TEGRA186_RESET_SPI1 40 +-#define TEGRA186_RESET_SPI2 41 +-#define TEGRA186_RESET_SPI3 42 +-#define TEGRA186_RESET_SPI4 43 +-#define TEGRA186_RESET_TMR 44 +-#define TEGRA186_RESET_TRIG_SYS 45 +-#define TEGRA186_RESET_TSEC 46 +-#define TEGRA186_RESET_UARTA 47 +-#define TEGRA186_RESET_UARTB 48 +-#define TEGRA186_RESET_UARTC 49 +-#define TEGRA186_RESET_UARTD 50 +-#define TEGRA186_RESET_VI 51 +-#define TEGRA186_RESET_VIC 52 +-#define TEGRA186_RESET_XUSB_DEV 53 +-#define TEGRA186_RESET_XUSB_HOST 54 +-#define TEGRA186_RESET_XUSB_PADCTL 55 +-#define TEGRA186_RESET_XUSB_SS 56 +-#define TEGRA186_RESET_AON_APB 57 +-#define TEGRA186_RESET_AXI_CBB 58 +-#define TEGRA186_RESET_BPMP_APB 59 +-#define TEGRA186_RESET_CAN1 60 +-#define TEGRA186_RESET_CAN2 61 +-#define TEGRA186_RESET_DMIC5 62 +-#define TEGRA186_RESET_DSIC 63 +-#define TEGRA186_RESET_DSID 64 +-#define TEGRA186_RESET_EMC_EMC 65 +-#define TEGRA186_RESET_EMC_MEM 66 +-#define TEGRA186_RESET_EMCSB_EMC 67 +-#define TEGRA186_RESET_EMCSB_MEM 68 +-#define TEGRA186_RESET_EQOS 69 +-#define TEGRA186_RESET_GPCDMA 70 +-#define TEGRA186_RESET_GPIO_CTL0 71 +-#define TEGRA186_RESET_GPIO_CTL1 72 +-#define TEGRA186_RESET_GPIO_CTL2 73 +-#define TEGRA186_RESET_GPIO_CTL3 74 +-#define TEGRA186_RESET_GPIO_CTL4 75 +-#define TEGRA186_RESET_GPIO_CTL5 76 +-#define TEGRA186_RESET_I2C10 77 +-#define TEGRA186_RESET_I2C12 78 +-#define TEGRA186_RESET_I2C13 79 +-#define TEGRA186_RESET_I2C14 80 +-#define TEGRA186_RESET_I2C7 81 +-#define TEGRA186_RESET_I2C8 82 +-#define TEGRA186_RESET_I2C9 83 +-#define TEGRA186_RESET_JTAG2AXI 84 +-#define TEGRA186_RESET_MPHY_IOBIST 85 +-#define TEGRA186_RESET_MPHY_L0_RX 86 +-#define TEGRA186_RESET_MPHY_L0_TX 87 +-#define TEGRA186_RESET_NVCSI 88 +-#define TEGRA186_RESET_NVDISPLAY0_HEAD0 89 +-#define TEGRA186_RESET_NVDISPLAY0_HEAD1 90 +-#define TEGRA186_RESET_NVDISPLAY0_HEAD2 91 +-#define TEGRA186_RESET_NVDISPLAY0_MISC 92 +-#define TEGRA186_RESET_NVDISPLAY0_WGRP0 93 +-#define TEGRA186_RESET_NVDISPLAY0_WGRP1 94 +-#define TEGRA186_RESET_NVDISPLAY0_WGRP2 95 +-#define TEGRA186_RESET_NVDISPLAY0_WGRP3 96 +-#define TEGRA186_RESET_NVDISPLAY0_WGRP4 97 +-#define TEGRA186_RESET_NVDISPLAY0_WGRP5 98 +-#define TEGRA186_RESET_PWM1 99 +-#define TEGRA186_RESET_PWM2 100 +-#define TEGRA186_RESET_PWM3 101 +-#define TEGRA186_RESET_PWM4 102 +-#define TEGRA186_RESET_PWM5 103 +-#define TEGRA186_RESET_PWM6 104 +-#define TEGRA186_RESET_PWM7 105 +-#define TEGRA186_RESET_PWM8 106 +-#define TEGRA186_RESET_SCE_APB 107 +-#define TEGRA186_RESET_SOR1 108 +-#define TEGRA186_RESET_TACH 109 +-#define TEGRA186_RESET_TSC 110 +-#define TEGRA186_RESET_UARTF 111 +-#define TEGRA186_RESET_UARTG 112 +-#define TEGRA186_RESET_UFSHC 113 +-#define TEGRA186_RESET_UFSHC_AXI_M 114 +-#define TEGRA186_RESET_UPHY 115 +-#define TEGRA186_RESET_ADSP 116 +-#define TEGRA186_RESET_ADSPDBG 117 +-#define TEGRA186_RESET_ADSPINTF 118 +-#define TEGRA186_RESET_ADSPNEON 119 +-#define TEGRA186_RESET_ADSPPERIPH 120 +-#define TEGRA186_RESET_ADSPSCU 121 +-#define TEGRA186_RESET_ADSPWDT 122 +-#define TEGRA186_RESET_APE 123 +-#define TEGRA186_RESET_DPAUX1 124 +-#define TEGRA186_RESET_NVDEC 125 +-#define TEGRA186_RESET_NVENC 126 +-#define TEGRA186_RESET_NVJPG 127 +-#define TEGRA186_RESET_PEX_USB_UPHY 128 +-#define TEGRA186_RESET_QSPI 129 +-#define TEGRA186_RESET_TSECB 130 +-#define TEGRA186_RESET_VI_I2C 131 +-#define TEGRA186_RESET_UARTE 132 +-#define TEGRA186_RESET_TOP_GTE 133 +-#define TEGRA186_RESET_SHSP 134 +-#define TEGRA186_RESET_PEX_USB_UPHY_L5 135 +-#define TEGRA186_RESET_PEX_USB_UPHY_L4 136 +-#define TEGRA186_RESET_PEX_USB_UPHY_L3 137 +-#define TEGRA186_RESET_PEX_USB_UPHY_L2 138 +-#define TEGRA186_RESET_PEX_USB_UPHY_L1 139 +-#define TEGRA186_RESET_PEX_USB_UPHY_L0 140 +-#define TEGRA186_RESET_PEX_USB_UPHY_PLL1 141 +-#define TEGRA186_RESET_PEX_USB_UPHY_PLL0 142 +-#define TEGRA186_RESET_TSCTNVI 143 +-#define TEGRA186_RESET_EXTPERIPH4 144 +-#define TEGRA186_RESET_DSIPADCTL 145 +-#define TEGRA186_RESET_AUD_MCLK 146 +-#define TEGRA186_RESET_MPHY_CLK_CTL 147 +-#define TEGRA186_RESET_MPHY_L1_RX 148 +-#define TEGRA186_RESET_MPHY_L1_TX 149 +-#define TEGRA186_RESET_UFSHC_LP 150 +-#define TEGRA186_RESET_BPMP_NIC 151 +-#define TEGRA186_RESET_BPMP_NSYSPORESET 152 +-#define TEGRA186_RESET_BPMP_NRESET 153 +-#define TEGRA186_RESET_BPMP_DBGRESETN 154 +-#define TEGRA186_RESET_BPMP_PRESETDBGN 155 +-#define TEGRA186_RESET_BPMP_PM 156 +-#define TEGRA186_RESET_BPMP_CVC 157 +-#define TEGRA186_RESET_BPMP_DMA 158 +-#define TEGRA186_RESET_BPMP_HSP 159 +-#define TEGRA186_RESET_TSCTNBPMP 160 +-#define TEGRA186_RESET_BPMP_TKE 161 +-#define TEGRA186_RESET_BPMP_GTE 162 +-#define TEGRA186_RESET_BPMP_PM_ACTMON 163 +-#define TEGRA186_RESET_AON_NIC 164 +-#define TEGRA186_RESET_AON_NSYSPORESET 165 +-#define TEGRA186_RESET_AON_NRESET 166 +-#define TEGRA186_RESET_AON_DBGRESETN 167 +-#define TEGRA186_RESET_AON_PRESETDBGN 168 +-#define TEGRA186_RESET_AON_ACTMON 169 +-#define TEGRA186_RESET_AOPM 170 +-#define TEGRA186_RESET_AOVC 171 +-#define TEGRA186_RESET_AON_DMA 172 +-#define TEGRA186_RESET_AON_GPIO 173 +-#define TEGRA186_RESET_AON_HSP 174 +-#define TEGRA186_RESET_TSCTNAON 175 +-#define TEGRA186_RESET_AON_TKE 176 +-#define TEGRA186_RESET_AON_GTE 177 +-#define TEGRA186_RESET_SCE_NIC 178 +-#define TEGRA186_RESET_SCE_NSYSPORESET 179 +-#define TEGRA186_RESET_SCE_NRESET 180 +-#define TEGRA186_RESET_SCE_DBGRESETN 181 +-#define TEGRA186_RESET_SCE_PRESETDBGN 182 +-#define TEGRA186_RESET_SCE_ACTMON 183 +-#define TEGRA186_RESET_SCE_PM 184 +-#define TEGRA186_RESET_SCE_DMA 185 +-#define TEGRA186_RESET_SCE_HSP 186 +-#define TEGRA186_RESET_TSCTNSCE 187 +-#define TEGRA186_RESET_SCE_TKE 188 +-#define TEGRA186_RESET_SCE_GTE 189 +-#define TEGRA186_RESET_SCE_CFG 190 +-#define TEGRA186_RESET_ADSP_ALL 191 +-/** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */ +-#define TEGRA186_RESET_UFSHC_LP_SEQ 192 +-#define TEGRA186_RESET_SIZE 193 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/tegra194-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/tegra194-reset.h +deleted file mode 100644 +index 473afaa25bfb..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/tegra194-reset.h ++++ /dev/null +@@ -1,152 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ +- +-#ifndef __ABI_MACH_T194_RESET_H +-#define __ABI_MACH_T194_RESET_H +- +-#define TEGRA194_RESET_ACTMON 1 +-#define TEGRA194_RESET_ADSP_ALL 2 +-#define TEGRA194_RESET_AFI 3 +-#define TEGRA194_RESET_CAN1 4 +-#define TEGRA194_RESET_CAN2 5 +-#define TEGRA194_RESET_DLA0 6 +-#define TEGRA194_RESET_DLA1 7 +-#define TEGRA194_RESET_DPAUX 8 +-#define TEGRA194_RESET_DPAUX1 9 +-#define TEGRA194_RESET_DPAUX2 10 +-#define TEGRA194_RESET_DPAUX3 11 +-#define TEGRA194_RESET_EQOS 17 +-#define TEGRA194_RESET_GPCDMA 18 +-#define TEGRA194_RESET_GPU 19 +-#define TEGRA194_RESET_HDA 20 +-#define TEGRA194_RESET_HDA2CODEC_2X 21 +-#define TEGRA194_RESET_HDA2HDMICODEC 22 +-#define TEGRA194_RESET_HOST1X 23 +-#define TEGRA194_RESET_I2C1 24 +-#define TEGRA194_RESET_I2C10 25 +-#define TEGRA194_RESET_RSVD_26 26 +-#define TEGRA194_RESET_RSVD_27 27 +-#define TEGRA194_RESET_RSVD_28 28 +-#define TEGRA194_RESET_I2C2 29 +-#define TEGRA194_RESET_I2C3 30 +-#define TEGRA194_RESET_I2C4 31 +-#define TEGRA194_RESET_I2C6 32 +-#define TEGRA194_RESET_I2C7 33 +-#define TEGRA194_RESET_I2C8 34 +-#define TEGRA194_RESET_I2C9 35 +-#define TEGRA194_RESET_ISP 36 +-#define TEGRA194_RESET_MIPI_CAL 37 +-#define TEGRA194_RESET_MPHY_CLK_CTL 38 +-#define TEGRA194_RESET_MPHY_L0_RX 39 +-#define TEGRA194_RESET_MPHY_L0_TX 40 +-#define TEGRA194_RESET_MPHY_L1_RX 41 +-#define TEGRA194_RESET_MPHY_L1_TX 42 +-#define TEGRA194_RESET_NVCSI 43 +-#define TEGRA194_RESET_NVDEC 44 +-#define TEGRA194_RESET_NVDISPLAY0_HEAD0 45 +-#define TEGRA194_RESET_NVDISPLAY0_HEAD1 46 +-#define TEGRA194_RESET_NVDISPLAY0_HEAD2 47 +-#define TEGRA194_RESET_NVDISPLAY0_HEAD3 48 +-#define TEGRA194_RESET_NVDISPLAY0_MISC 49 +-#define TEGRA194_RESET_NVDISPLAY0_WGRP0 50 +-#define TEGRA194_RESET_NVDISPLAY0_WGRP1 51 +-#define TEGRA194_RESET_NVDISPLAY0_WGRP2 52 +-#define TEGRA194_RESET_NVDISPLAY0_WGRP3 53 +-#define TEGRA194_RESET_NVDISPLAY0_WGRP4 54 +-#define TEGRA194_RESET_NVDISPLAY0_WGRP5 55 +-#define TEGRA194_RESET_RSVD_56 56 +-#define TEGRA194_RESET_RSVD_57 57 +-#define TEGRA194_RESET_RSVD_58 58 +-#define TEGRA194_RESET_NVENC 59 +-#define TEGRA194_RESET_NVENC1 60 +-#define TEGRA194_RESET_NVJPG 61 +-#define TEGRA194_RESET_PCIE 62 +-#define TEGRA194_RESET_PCIEXCLK 63 +-#define TEGRA194_RESET_RSVD_64 64 +-#define TEGRA194_RESET_RSVD_65 65 +-#define TEGRA194_RESET_PVA0_ALL 66 +-#define TEGRA194_RESET_PVA1_ALL 67 +-#define TEGRA194_RESET_PWM1 68 +-#define TEGRA194_RESET_PWM2 69 +-#define TEGRA194_RESET_PWM3 70 +-#define TEGRA194_RESET_PWM4 71 +-#define TEGRA194_RESET_PWM5 72 +-#define TEGRA194_RESET_PWM6 73 +-#define TEGRA194_RESET_PWM7 74 +-#define TEGRA194_RESET_PWM8 75 +-#define TEGRA194_RESET_QSPI0 76 +-#define TEGRA194_RESET_QSPI1 77 +-#define TEGRA194_RESET_SATA 78 +-#define TEGRA194_RESET_SATACOLD 79 +-#define TEGRA194_RESET_SCE_ALL 80 +-#define TEGRA194_RESET_RCE_ALL 81 +-#define TEGRA194_RESET_SDMMC1 82 +-#define TEGRA194_RESET_RSVD_83 83 +-#define TEGRA194_RESET_SDMMC3 84 +-#define TEGRA194_RESET_SDMMC4 85 +-#define TEGRA194_RESET_SE 86 +-#define TEGRA194_RESET_SOR0 87 +-#define TEGRA194_RESET_SOR1 88 +-#define TEGRA194_RESET_SOR2 89 +-#define TEGRA194_RESET_SOR3 90 +-#define TEGRA194_RESET_SPI1 91 +-#define TEGRA194_RESET_SPI2 92 +-#define TEGRA194_RESET_SPI3 93 +-#define TEGRA194_RESET_SPI4 94 +-#define TEGRA194_RESET_TACH 95 +-#define TEGRA194_RESET_RSVD_96 96 +-#define TEGRA194_RESET_TSCTNVI 97 +-#define TEGRA194_RESET_TSEC 98 +-#define TEGRA194_RESET_TSECB 99 +-#define TEGRA194_RESET_UARTA 100 +-#define TEGRA194_RESET_UARTB 101 +-#define TEGRA194_RESET_UARTC 102 +-#define TEGRA194_RESET_UARTD 103 +-#define TEGRA194_RESET_UARTE 104 +-#define TEGRA194_RESET_UARTF 105 +-#define TEGRA194_RESET_UARTG 106 +-#define TEGRA194_RESET_UARTH 107 +-#define TEGRA194_RESET_UFSHC 108 +-#define TEGRA194_RESET_UFSHC_AXI_M 109 +-#define TEGRA194_RESET_UFSHC_LP_SEQ 110 +-#define TEGRA194_RESET_RSVD_111 111 +-#define TEGRA194_RESET_VI 112 +-#define TEGRA194_RESET_VIC 113 +-#define TEGRA194_RESET_XUSB_PADCTL 114 +-#define TEGRA194_RESET_NVDEC1 115 +-#define TEGRA194_RESET_PEX0_CORE_0 116 +-#define TEGRA194_RESET_PEX0_CORE_1 117 +-#define TEGRA194_RESET_PEX0_CORE_2 118 +-#define TEGRA194_RESET_PEX0_CORE_3 119 +-#define TEGRA194_RESET_PEX0_CORE_4 120 +-#define TEGRA194_RESET_PEX0_CORE_0_APB 121 +-#define TEGRA194_RESET_PEX0_CORE_1_APB 122 +-#define TEGRA194_RESET_PEX0_CORE_2_APB 123 +-#define TEGRA194_RESET_PEX0_CORE_3_APB 124 +-#define TEGRA194_RESET_PEX0_CORE_4_APB 125 +-#define TEGRA194_RESET_PEX0_COMMON_APB 126 +-#define TEGRA194_RESET_PEX1_CORE_5 129 +-#define TEGRA194_RESET_PEX1_CORE_5_APB 130 +-#define TEGRA194_RESET_CVNAS 131 +-#define TEGRA194_RESET_CVNAS_FCM 132 +-#define TEGRA194_RESET_DMIC5 144 +-#define TEGRA194_RESET_APE 145 +-#define TEGRA194_RESET_PEX_USB_UPHY 146 +-#define TEGRA194_RESET_PEX_USB_UPHY_L0 147 +-#define TEGRA194_RESET_PEX_USB_UPHY_L1 148 +-#define TEGRA194_RESET_PEX_USB_UPHY_L2 149 +-#define TEGRA194_RESET_PEX_USB_UPHY_L3 150 +-#define TEGRA194_RESET_PEX_USB_UPHY_L4 151 +-#define TEGRA194_RESET_PEX_USB_UPHY_L5 152 +-#define TEGRA194_RESET_PEX_USB_UPHY_L6 153 +-#define TEGRA194_RESET_PEX_USB_UPHY_L7 154 +-#define TEGRA194_RESET_PEX_USB_UPHY_L8 155 +-#define TEGRA194_RESET_PEX_USB_UPHY_L9 156 +-#define TEGRA194_RESET_PEX_USB_UPHY_L10 157 +-#define TEGRA194_RESET_PEX_USB_UPHY_L11 158 +-#define TEGRA194_RESET_PEX_USB_UPHY_PLL0 159 +-#define TEGRA194_RESET_PEX_USB_UPHY_PLL1 160 +-#define TEGRA194_RESET_PEX_USB_UPHY_PLL2 161 +-#define TEGRA194_RESET_PEX_USB_UPHY_PLL3 162 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/tegra210-car.h b/scripts/dtc/include-prefixes/dt-bindings/reset/tegra210-car.h +deleted file mode 100644 +index 9dc84ec76301..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/tegra210-car.h ++++ /dev/null +@@ -1,14 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides Tegra210-specific constants for binding +- * nvidia,tegra210-car. +- */ +- +-#ifndef _DT_BINDINGS_RESET_TEGRA210_CAR_H +-#define _DT_BINDINGS_RESET_TEGRA210_CAR_H +- +-#define TEGRA210_RESET(x) (7 * 32 + (x)) +-#define TEGRA210_RST_DFLL_DVCO TEGRA210_RESET(0) +-#define TEGRA210_RST_ADSP TEGRA210_RESET(1) +- +-#endif /* _DT_BINDINGS_RESET_TEGRA210_CAR_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/tegra234-reset.h b/scripts/dtc/include-prefixes/dt-bindings/reset/tegra234-reset.h +deleted file mode 100644 +index b3c63be06d2d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/tegra234-reset.h ++++ /dev/null +@@ -1,10 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. */ +- +-#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H +-#define DT_BINDINGS_RESET_TEGRA234_RESET_H +- +-#define TEGRA234_RESET_SDMMC4 85 +-#define TEGRA234_RESET_UARTA 100 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/ti-syscon.h b/scripts/dtc/include-prefixes/dt-bindings/reset/ti-syscon.h +deleted file mode 100644 +index eacc0f18083e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/ti-syscon.h ++++ /dev/null +@@ -1,29 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later */ +-/* +- * TI Syscon Reset definitions +- * +- * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ +- */ +- +-#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__ +-#define __DT_BINDINGS_RESET_TI_SYSCON_H__ +- +-/* +- * The reset does not support the feature and corresponding +- * values are not valid +- */ +-#define ASSERT_NONE (1 << 0) +-#define DEASSERT_NONE (1 << 1) +-#define STATUS_NONE (1 << 2) +- +-/* When set this function is activated by setting(vs clearing) this bit */ +-#define ASSERT_SET (1 << 3) +-#define DEASSERT_SET (1 << 4) +-#define STATUS_SET (1 << 5) +- +-/* The following are the inverse of the above and are added for consistency */ +-#define ASSERT_CLEAR (0 << 3) +-#define DEASSERT_CLEAR (0 << 4) +-#define STATUS_CLEAR (0 << 5) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/xlnx-versal-resets.h b/scripts/dtc/include-prefixes/dt-bindings/reset/xlnx-versal-resets.h +deleted file mode 100644 +index 895424e9b0e5..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/xlnx-versal-resets.h ++++ /dev/null +@@ -1,105 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2020 Xilinx, Inc. +- */ +- +-#ifndef _DT_BINDINGS_VERSAL_RESETS_H +-#define _DT_BINDINGS_VERSAL_RESETS_H +- +-#define VERSAL_RST_PMC_POR (0xc30c001U) +-#define VERSAL_RST_PMC (0xc410002U) +-#define VERSAL_RST_PS_POR (0xc30c003U) +-#define VERSAL_RST_PL_POR (0xc30c004U) +-#define VERSAL_RST_NOC_POR (0xc30c005U) +-#define VERSAL_RST_FPD_POR (0xc30c006U) +-#define VERSAL_RST_ACPU_0_POR (0xc30c007U) +-#define VERSAL_RST_ACPU_1_POR (0xc30c008U) +-#define VERSAL_RST_OCM2_POR (0xc30c009U) +-#define VERSAL_RST_PS_SRST (0xc41000aU) +-#define VERSAL_RST_PL_SRST (0xc41000bU) +-#define VERSAL_RST_NOC (0xc41000cU) +-#define VERSAL_RST_NPI (0xc41000dU) +-#define VERSAL_RST_SYS_RST_1 (0xc41000eU) +-#define VERSAL_RST_SYS_RST_2 (0xc41000fU) +-#define VERSAL_RST_SYS_RST_3 (0xc410010U) +-#define VERSAL_RST_FPD (0xc410011U) +-#define VERSAL_RST_PL0 (0xc410012U) +-#define VERSAL_RST_PL1 (0xc410013U) +-#define VERSAL_RST_PL2 (0xc410014U) +-#define VERSAL_RST_PL3 (0xc410015U) +-#define VERSAL_RST_APU (0xc410016U) +-#define VERSAL_RST_ACPU_0 (0xc410017U) +-#define VERSAL_RST_ACPU_1 (0xc410018U) +-#define VERSAL_RST_ACPU_L2 (0xc410019U) +-#define VERSAL_RST_ACPU_GIC (0xc41001aU) +-#define VERSAL_RST_RPU_ISLAND (0xc41001bU) +-#define VERSAL_RST_RPU_AMBA (0xc41001cU) +-#define VERSAL_RST_R5_0 (0xc41001dU) +-#define VERSAL_RST_R5_1 (0xc41001eU) +-#define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU) +-#define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U) +-#define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U) +-#define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U) +-#define VERSAL_RST_SYSMON_LPD (0xc410023U) +-#define VERSAL_RST_PDMA_RST1 (0xc410024U) +-#define VERSAL_RST_PDMA_RST0 (0xc410025U) +-#define VERSAL_RST_ADMA (0xc410026U) +-#define VERSAL_RST_TIMESTAMP (0xc410027U) +-#define VERSAL_RST_OCM (0xc410028U) +-#define VERSAL_RST_OCM2_RST (0xc410029U) +-#define VERSAL_RST_IPI (0xc41002aU) +-#define VERSAL_RST_SBI (0xc41002bU) +-#define VERSAL_RST_LPD (0xc41002cU) +-#define VERSAL_RST_QSPI (0xc10402dU) +-#define VERSAL_RST_OSPI (0xc10402eU) +-#define VERSAL_RST_SDIO_0 (0xc10402fU) +-#define VERSAL_RST_SDIO_1 (0xc104030U) +-#define VERSAL_RST_I2C_PMC (0xc104031U) +-#define VERSAL_RST_GPIO_PMC (0xc104032U) +-#define VERSAL_RST_GEM_0 (0xc104033U) +-#define VERSAL_RST_GEM_1 (0xc104034U) +-#define VERSAL_RST_SPARE (0xc104035U) +-#define VERSAL_RST_USB_0 (0xc104036U) +-#define VERSAL_RST_UART_0 (0xc104037U) +-#define VERSAL_RST_UART_1 (0xc104038U) +-#define VERSAL_RST_SPI_0 (0xc104039U) +-#define VERSAL_RST_SPI_1 (0xc10403aU) +-#define VERSAL_RST_CAN_FD_0 (0xc10403bU) +-#define VERSAL_RST_CAN_FD_1 (0xc10403cU) +-#define VERSAL_RST_I2C_0 (0xc10403dU) +-#define VERSAL_RST_I2C_1 (0xc10403eU) +-#define VERSAL_RST_GPIO_LPD (0xc10403fU) +-#define VERSAL_RST_TTC_0 (0xc104040U) +-#define VERSAL_RST_TTC_1 (0xc104041U) +-#define VERSAL_RST_TTC_2 (0xc104042U) +-#define VERSAL_RST_TTC_3 (0xc104043U) +-#define VERSAL_RST_SWDT_FPD (0xc104044U) +-#define VERSAL_RST_SWDT_LPD (0xc104045U) +-#define VERSAL_RST_USB (0xc104046U) +-#define VERSAL_RST_DPC (0xc208047U) +-#define VERSAL_RST_PMCDBG (0xc208048U) +-#define VERSAL_RST_DBG_TRACE (0xc208049U) +-#define VERSAL_RST_DBG_FPD (0xc20804aU) +-#define VERSAL_RST_DBG_TSTMP (0xc20804bU) +-#define VERSAL_RST_RPU0_DBG (0xc20804cU) +-#define VERSAL_RST_RPU1_DBG (0xc20804dU) +-#define VERSAL_RST_HSDP (0xc20804eU) +-#define VERSAL_RST_DBG_LPD (0xc20804fU) +-#define VERSAL_RST_CPM_POR (0xc30c050U) +-#define VERSAL_RST_CPM (0xc410051U) +-#define VERSAL_RST_CPMDBG (0xc208052U) +-#define VERSAL_RST_PCIE_CFG (0xc410053U) +-#define VERSAL_RST_PCIE_CORE0 (0xc410054U) +-#define VERSAL_RST_PCIE_CORE1 (0xc410055U) +-#define VERSAL_RST_PCIE_DMA (0xc410056U) +-#define VERSAL_RST_CMN (0xc410057U) +-#define VERSAL_RST_L2_0 (0xc410058U) +-#define VERSAL_RST_L2_1 (0xc410059U) +-#define VERSAL_RST_ADDR_REMAP (0xc41005aU) +-#define VERSAL_RST_CPI0 (0xc41005bU) +-#define VERSAL_RST_CPI1 (0xc41005cU) +-#define VERSAL_RST_XRAM (0xc30c05dU) +-#define VERSAL_RST_AIE_ARRAY (0xc10405eU) +-#define VERSAL_RST_AIE_SHIM (0xc10405fU) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/reset/xlnx-zynqmp-resets.h b/scripts/dtc/include-prefixes/dt-bindings/reset/xlnx-zynqmp-resets.h +deleted file mode 100644 +index d44525b9f8db..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/reset/xlnx-zynqmp-resets.h ++++ /dev/null +@@ -1,130 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2018 Xilinx, Inc. +- */ +- +-#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H +-#define _DT_BINDINGS_ZYNQMP_RESETS_H +- +-#define ZYNQMP_RESET_PCIE_CFG 0 +-#define ZYNQMP_RESET_PCIE_BRIDGE 1 +-#define ZYNQMP_RESET_PCIE_CTRL 2 +-#define ZYNQMP_RESET_DP 3 +-#define ZYNQMP_RESET_SWDT_CRF 4 +-#define ZYNQMP_RESET_AFI_FM5 5 +-#define ZYNQMP_RESET_AFI_FM4 6 +-#define ZYNQMP_RESET_AFI_FM3 7 +-#define ZYNQMP_RESET_AFI_FM2 8 +-#define ZYNQMP_RESET_AFI_FM1 9 +-#define ZYNQMP_RESET_AFI_FM0 10 +-#define ZYNQMP_RESET_GDMA 11 +-#define ZYNQMP_RESET_GPU_PP1 12 +-#define ZYNQMP_RESET_GPU_PP0 13 +-#define ZYNQMP_RESET_GPU 14 +-#define ZYNQMP_RESET_GT 15 +-#define ZYNQMP_RESET_SATA 16 +-#define ZYNQMP_RESET_ACPU3_PWRON 17 +-#define ZYNQMP_RESET_ACPU2_PWRON 18 +-#define ZYNQMP_RESET_ACPU1_PWRON 19 +-#define ZYNQMP_RESET_ACPU0_PWRON 20 +-#define ZYNQMP_RESET_APU_L2 21 +-#define ZYNQMP_RESET_ACPU3 22 +-#define ZYNQMP_RESET_ACPU2 23 +-#define ZYNQMP_RESET_ACPU1 24 +-#define ZYNQMP_RESET_ACPU0 25 +-#define ZYNQMP_RESET_DDR 26 +-#define ZYNQMP_RESET_APM_FPD 27 +-#define ZYNQMP_RESET_SOFT 28 +-#define ZYNQMP_RESET_GEM0 29 +-#define ZYNQMP_RESET_GEM1 30 +-#define ZYNQMP_RESET_GEM2 31 +-#define ZYNQMP_RESET_GEM3 32 +-#define ZYNQMP_RESET_QSPI 33 +-#define ZYNQMP_RESET_UART0 34 +-#define ZYNQMP_RESET_UART1 35 +-#define ZYNQMP_RESET_SPI0 36 +-#define ZYNQMP_RESET_SPI1 37 +-#define ZYNQMP_RESET_SDIO0 38 +-#define ZYNQMP_RESET_SDIO1 39 +-#define ZYNQMP_RESET_CAN0 40 +-#define ZYNQMP_RESET_CAN1 41 +-#define ZYNQMP_RESET_I2C0 42 +-#define ZYNQMP_RESET_I2C1 43 +-#define ZYNQMP_RESET_TTC0 44 +-#define ZYNQMP_RESET_TTC1 45 +-#define ZYNQMP_RESET_TTC2 46 +-#define ZYNQMP_RESET_TTC3 47 +-#define ZYNQMP_RESET_SWDT_CRL 48 +-#define ZYNQMP_RESET_NAND 49 +-#define ZYNQMP_RESET_ADMA 50 +-#define ZYNQMP_RESET_GPIO 51 +-#define ZYNQMP_RESET_IOU_CC 52 +-#define ZYNQMP_RESET_TIMESTAMP 53 +-#define ZYNQMP_RESET_RPU_R50 54 +-#define ZYNQMP_RESET_RPU_R51 55 +-#define ZYNQMP_RESET_RPU_AMBA 56 +-#define ZYNQMP_RESET_OCM 57 +-#define ZYNQMP_RESET_RPU_PGE 58 +-#define ZYNQMP_RESET_USB0_CORERESET 59 +-#define ZYNQMP_RESET_USB1_CORERESET 60 +-#define ZYNQMP_RESET_USB0_HIBERRESET 61 +-#define ZYNQMP_RESET_USB1_HIBERRESET 62 +-#define ZYNQMP_RESET_USB0_APB 63 +-#define ZYNQMP_RESET_USB1_APB 64 +-#define ZYNQMP_RESET_IPI 65 +-#define ZYNQMP_RESET_APM_LPD 66 +-#define ZYNQMP_RESET_RTC 67 +-#define ZYNQMP_RESET_SYSMON 68 +-#define ZYNQMP_RESET_AFI_FM6 69 +-#define ZYNQMP_RESET_LPD_SWDT 70 +-#define ZYNQMP_RESET_FPD 71 +-#define ZYNQMP_RESET_RPU_DBG1 72 +-#define ZYNQMP_RESET_RPU_DBG0 73 +-#define ZYNQMP_RESET_DBG_LPD 74 +-#define ZYNQMP_RESET_DBG_FPD 75 +-#define ZYNQMP_RESET_APLL 76 +-#define ZYNQMP_RESET_DPLL 77 +-#define ZYNQMP_RESET_VPLL 78 +-#define ZYNQMP_RESET_IOPLL 79 +-#define ZYNQMP_RESET_RPLL 80 +-#define ZYNQMP_RESET_GPO3_PL_0 81 +-#define ZYNQMP_RESET_GPO3_PL_1 82 +-#define ZYNQMP_RESET_GPO3_PL_2 83 +-#define ZYNQMP_RESET_GPO3_PL_3 84 +-#define ZYNQMP_RESET_GPO3_PL_4 85 +-#define ZYNQMP_RESET_GPO3_PL_5 86 +-#define ZYNQMP_RESET_GPO3_PL_6 87 +-#define ZYNQMP_RESET_GPO3_PL_7 88 +-#define ZYNQMP_RESET_GPO3_PL_8 89 +-#define ZYNQMP_RESET_GPO3_PL_9 90 +-#define ZYNQMP_RESET_GPO3_PL_10 91 +-#define ZYNQMP_RESET_GPO3_PL_11 92 +-#define ZYNQMP_RESET_GPO3_PL_12 93 +-#define ZYNQMP_RESET_GPO3_PL_13 94 +-#define ZYNQMP_RESET_GPO3_PL_14 95 +-#define ZYNQMP_RESET_GPO3_PL_15 96 +-#define ZYNQMP_RESET_GPO3_PL_16 97 +-#define ZYNQMP_RESET_GPO3_PL_17 98 +-#define ZYNQMP_RESET_GPO3_PL_18 99 +-#define ZYNQMP_RESET_GPO3_PL_19 100 +-#define ZYNQMP_RESET_GPO3_PL_20 101 +-#define ZYNQMP_RESET_GPO3_PL_21 102 +-#define ZYNQMP_RESET_GPO3_PL_22 103 +-#define ZYNQMP_RESET_GPO3_PL_23 104 +-#define ZYNQMP_RESET_GPO3_PL_24 105 +-#define ZYNQMP_RESET_GPO3_PL_25 106 +-#define ZYNQMP_RESET_GPO3_PL_26 107 +-#define ZYNQMP_RESET_GPO3_PL_27 108 +-#define ZYNQMP_RESET_GPO3_PL_28 109 +-#define ZYNQMP_RESET_GPO3_PL_29 110 +-#define ZYNQMP_RESET_GPO3_PL_30 111 +-#define ZYNQMP_RESET_GPO3_PL_31 112 +-#define ZYNQMP_RESET_RPU_LS 113 +-#define ZYNQMP_RESET_PS_ONLY 114 +-#define ZYNQMP_RESET_PL 115 +-#define ZYNQMP_RESET_PS_PL0 116 +-#define ZYNQMP_RESET_PS_PL1 117 +-#define ZYNQMP_RESET_PS_PL2 118 +-#define ZYNQMP_RESET_PS_PL3 119 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/soc/bcm-pmb.h b/scripts/dtc/include-prefixes/dt-bindings/soc/bcm-pmb.h +deleted file mode 100644 +index 385884468007..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/soc/bcm-pmb.h ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */ +- +-#ifndef __DT_BINDINGS_SOC_BCM_PMB_H +-#define __DT_BINDINGS_SOC_BCM_PMB_H +- +-#define BCM_PMB_PCIE0 0x01 +-#define BCM_PMB_PCIE1 0x02 +-#define BCM_PMB_PCIE2 0x03 +-#define BCM_PMB_HOST_USB 0x04 +-#define BCM_PMB_SATA 0x05 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/soc/bcm2835-pm.h b/scripts/dtc/include-prefixes/dt-bindings/soc/bcm2835-pm.h +deleted file mode 100644 +index 153d75b8d99f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/soc/bcm2835-pm.h ++++ /dev/null +@@ -1,28 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +- +-#ifndef _DT_BINDINGS_ARM_BCM2835_PM_H +-#define _DT_BINDINGS_ARM_BCM2835_PM_H +- +-#define BCM2835_POWER_DOMAIN_GRAFX 0 +-#define BCM2835_POWER_DOMAIN_GRAFX_V3D 1 +-#define BCM2835_POWER_DOMAIN_IMAGE 2 +-#define BCM2835_POWER_DOMAIN_IMAGE_PERI 3 +-#define BCM2835_POWER_DOMAIN_IMAGE_ISP 4 +-#define BCM2835_POWER_DOMAIN_IMAGE_H264 5 +-#define BCM2835_POWER_DOMAIN_USB 6 +-#define BCM2835_POWER_DOMAIN_DSI0 7 +-#define BCM2835_POWER_DOMAIN_DSI1 8 +-#define BCM2835_POWER_DOMAIN_CAM0 9 +-#define BCM2835_POWER_DOMAIN_CAM1 10 +-#define BCM2835_POWER_DOMAIN_CCP2TX 11 +-#define BCM2835_POWER_DOMAIN_HDMI 12 +- +-#define BCM2835_POWER_DOMAIN_COUNT 13 +- +-#define BCM2835_RESET_V3D 0 +-#define BCM2835_RESET_ISP 1 +-#define BCM2835_RESET_H264 2 +- +-#define BCM2835_RESET_COUNT 3 +- +-#endif /* _DT_BINDINGS_ARM_BCM2835_PM_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/soc/bcm6318-pm.h b/scripts/dtc/include-prefixes/dt-bindings/soc/bcm6318-pm.h +deleted file mode 100644 +index 05931dce8333..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/soc/bcm6318-pm.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef __DT_BINDINGS_BMIPS_BCM6318_PM_H +-#define __DT_BINDINGS_BMIPS_BCM6318_PM_H +- +-#define BCM6318_POWER_DOMAIN_PCIE 0 +-#define BCM6318_POWER_DOMAIN_USB 1 +-#define BCM6318_POWER_DOMAIN_EPHY0 2 +-#define BCM6318_POWER_DOMAIN_EPHY1 3 +-#define BCM6318_POWER_DOMAIN_EPHY2 4 +-#define BCM6318_POWER_DOMAIN_EPHY3 5 +-#define BCM6318_POWER_DOMAIN_LDO2P5 6 +-#define BCM6318_POWER_DOMAIN_LDO2P9 7 +-#define BCM6318_POWER_DOMAIN_SW1P0 8 +-#define BCM6318_POWER_DOMAIN_PAD 9 +- +-#endif /* __DT_BINDINGS_BMIPS_BCM6318_PM_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/soc/bcm63268-pm.h b/scripts/dtc/include-prefixes/dt-bindings/soc/bcm63268-pm.h +deleted file mode 100644 +index 84ded53a732f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/soc/bcm63268-pm.h ++++ /dev/null +@@ -1,21 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef __DT_BINDINGS_BMIPS_BCM63268_PM_H +-#define __DT_BINDINGS_BMIPS_BCM63268_PM_H +- +-#define BCM63268_POWER_DOMAIN_SAR 0 +-#define BCM63268_POWER_DOMAIN_IPSEC 1 +-#define BCM63268_POWER_DOMAIN_MIPS 2 +-#define BCM63268_POWER_DOMAIN_DECT 3 +-#define BCM63268_POWER_DOMAIN_USBH 4 +-#define BCM63268_POWER_DOMAIN_USBD 5 +-#define BCM63268_POWER_DOMAIN_ROBOSW 6 +-#define BCM63268_POWER_DOMAIN_PCM 7 +-#define BCM63268_POWER_DOMAIN_PERIPH 8 +-#define BCM63268_POWER_DOMAIN_VDSL_PHY 9 +-#define BCM63268_POWER_DOMAIN_VDSL_MIPS 10 +-#define BCM63268_POWER_DOMAIN_FAP 11 +-#define BCM63268_POWER_DOMAIN_PCIE 12 +-#define BCM63268_POWER_DOMAIN_WLAN_PADS 13 +- +-#endif /* __DT_BINDINGS_BMIPS_BCM63268_PM_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/soc/bcm6328-pm.h b/scripts/dtc/include-prefixes/dt-bindings/soc/bcm6328-pm.h +deleted file mode 100644 +index 557e1a69b7f7..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/soc/bcm6328-pm.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef __DT_BINDINGS_BMIPS_BCM6328_PM_H +-#define __DT_BINDINGS_BMIPS_BCM6328_PM_H +- +-#define BCM6328_POWER_DOMAIN_ADSL2_MIPS 0 +-#define BCM6328_POWER_DOMAIN_ADSL2_PHY 1 +-#define BCM6328_POWER_DOMAIN_ADSL2_AFE 2 +-#define BCM6328_POWER_DOMAIN_SAR 3 +-#define BCM6328_POWER_DOMAIN_PCM 4 +-#define BCM6328_POWER_DOMAIN_USBD 5 +-#define BCM6328_POWER_DOMAIN_USBH 6 +-#define BCM6328_POWER_DOMAIN_PCIE 7 +-#define BCM6328_POWER_DOMAIN_ROBOSW 8 +-#define BCM6328_POWER_DOMAIN_EPHY 9 +- +-#endif /* __DT_BINDINGS_BMIPS_BCM6328_PM_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/soc/bcm6362-pm.h b/scripts/dtc/include-prefixes/dt-bindings/soc/bcm6362-pm.h +deleted file mode 100644 +index d087ba63c7a1..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/soc/bcm6362-pm.h ++++ /dev/null +@@ -1,21 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +- +-#ifndef __DT_BINDINGS_BMIPS_BCM6362_PM_H +-#define __DT_BINDINGS_BMIPS_BCM6362_PM_H +- +-#define BCM6362_POWER_DOMAIN_SAR 0 +-#define BCM6362_POWER_DOMAIN_IPSEC 1 +-#define BCM6362_POWER_DOMAIN_MIPS 2 +-#define BCM6362_POWER_DOMAIN_DECT 3 +-#define BCM6362_POWER_DOMAIN_USBH 4 +-#define BCM6362_POWER_DOMAIN_USBD 5 +-#define BCM6362_POWER_DOMAIN_ROBOSW 6 +-#define BCM6362_POWER_DOMAIN_PCM 7 +-#define BCM6362_POWER_DOMAIN_PERIPH 8 +-#define BCM6362_POWER_DOMAIN_ADSL_PHY 9 +-#define BCM6362_POWER_DOMAIN_GMII_PADS 10 +-#define BCM6362_POWER_DOMAIN_FAP 11 +-#define BCM6362_POWER_DOMAIN_PCIE 12 +-#define BCM6362_POWER_DOMAIN_WLAN_PADS 13 +- +-#endif /* __DT_BINDINGS_BMIPS_BCM6362_PM_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/soc/hailo15_interrupts.h b/scripts/dtc/include-prefixes/dt-bindings/soc/hailo15_interrupts.h +deleted file mode 100644 +index 379e71616975..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/soc/hailo15_interrupts.h ++++ /dev/null +@@ -1,120 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2019-2023 Hailo Technologies Ltd. All rights reserved. +- * +- */ +- +-#ifndef _DT_BINDINGS_HAILO15_INTERRUPTS +-#define _DT_BINDINGS_HAILO15_INTERRUPTS +- +- +-#define HW_INTERRUPTS__AP_ERROR_INTR_IRQ (122) +-#define HW_INTERRUPTS__AP_FUNC_INTR_IRQ (123) +-#define HW_INTERRUPTS__ARM_MAILBOX_A53_INTR_0_IRQ (103) +-#define HW_INTERRUPTS__ARM_MAILBOX_A53_INTR_1_IRQ (104) +-#define HW_INTERRUPTS__ARM_MAILBOX_A53_INTR_2_IRQ (105) +-#define HW_INTERRUPTS__ARM_MAILBOX_A53_INTR_3_IRQ (116) +-#define HW_INTERRUPTS__ARM_MAILBOX_M4_INTR_0_IRQ ( 57) +-#define HW_INTERRUPTS__ARM_MAILBOX_M4_INTR_1_IRQ ( 58) +-#define HW_INTERRUPTS__CC_HOST_IRQ (117) +-#define HW_INTERRUPTS__CPU0_FLOATING_POINT_IRQ ( 63) +-#define HW_INTERRUPTS__CPU0_MAILBOX_IRQ ( 61) +-#define HW_INTERRUPTS__CPU0_SEMAPHORE_IRQ ( 59) +-#define HW_INTERRUPTS__CPU1_FLOATING_POINT_IRQ ( 64) +-#define HW_INTERRUPTS__CPU1_MAILBOX_IRQ ( 62) +-#define HW_INTERRUPTS__CPU1_SEMAPHORE_IRQ ( 60) +-#define HW_INTERRUPTS__CPU_SUBSYS_ERROR_INT_IRQ (120) +-#define HW_INTERRUPTS__CSI_RX0_IRQ ( 36) +-#define HW_INTERRUPTS__CSI_RX1_IRQ ( 37) +-#define HW_INTERRUPTS__CSI_TX0_IRQ ( 40) +-#define HW_INTERRUPTS__CSI_TX0_DSI_IRQ ( 73) +-#define HW_INTERRUPTS__CSI_TX0_WRAPPER_FUNCTIONAL_INT_IRQ ( 39) +-#define HW_INTERRUPTS__DDR_CONTROLLER_INT_IRQ ( 42) +-#define HW_INTERRUPTS__DDR_SUBSYS_ERR_INT_IRQ ( 92) +-#define HW_INTERRUPTS__DDR_SUBSYS_FUNC_INT_IRQ ( 95) +-#define HW_INTERRUPTS__DEBUG_TOP_ERROR_STATUS_OUT_IRQ ( 69) +-#define HW_INTERRUPTS__DEBUG_TRIGGER_IRQ ( 34) +-#define HW_INTERRUPTS__DMA0_IRQ ( 35) +-#define HW_INTERRUPTS__DRAM_DMA_AP0_INT_IRQ ( 50) +-#define HW_INTERRUPTS__DRAM_DMA_AP1_INT_IRQ ( 51) +-#define HW_INTERRUPTS__DRAM_DMA_AP2_INT_IRQ ( 52) +-#define HW_INTERRUPTS__DRAM_DMA_CS0_IRQ_FUNC_IRQ ( 44) +-#define HW_INTERRUPTS__DRAM_DMA_CS1_IRQ_FUNC_IRQ ( 45) +-#define HW_INTERRUPTS__DRAM_DMA_CS2_IRQ_FUNC_IRQ ( 46) +-#define HW_INTERRUPTS__DRAM_DMA_ENGINE0_IRQ_ERR_IRQ ( 47) +-#define HW_INTERRUPTS__DRAM_DMA_ENGINE1_IRQ_ERR_IRQ ( 48) +-#define HW_INTERRUPTS__DRAM_DMA_ENGINE2_IRQ_ERR_IRQ ( 49) +-#define HW_INTERRUPTS__DRAM_DMA_WRAPPER_ERR_INT_IRQ (121) +-#define HW_INTERRUPTS__DSP_ERR_IRQ_IRQ ( 72) +-#define HW_INTERRUPTS__DSP_PWAITMODE_INTERRUPT_IRQ ( 71) +-#define HW_INTERRUPTS__DSP_VIRT_CH_DONE_INTERRUPT_IRQ ( 70) +-#define HW_INTERRUPTS__ETHERNET_0_IRQ ( 75) +-#define HW_INTERRUPTS__ETHERNET_1_IRQ ( 76) +-#define HW_INTERRUPTS__ETHERNET_10_IRQ ( 85) +-#define HW_INTERRUPTS__ETHERNET_11_IRQ ( 86) +-#define HW_INTERRUPTS__ETHERNET_12_IRQ ( 87) +-#define HW_INTERRUPTS__ETHERNET_13_IRQ ( 88) +-#define HW_INTERRUPTS__ETHERNET_14_IRQ ( 89) +-#define HW_INTERRUPTS__ETHERNET_15_IRQ ( 90) +-#define HW_INTERRUPTS__ETHERNET_2_IRQ ( 77) +-#define HW_INTERRUPTS__ETHERNET_3_IRQ ( 78) +-#define HW_INTERRUPTS__ETHERNET_4_IRQ ( 79) +-#define HW_INTERRUPTS__ETHERNET_5_IRQ ( 80) +-#define HW_INTERRUPTS__ETHERNET_6_IRQ ( 81) +-#define HW_INTERRUPTS__ETHERNET_7_IRQ ( 82) +-#define HW_INTERRUPTS__ETHERNET_8_IRQ ( 83) +-#define HW_INTERRUPTS__ETHERNET_9_IRQ ( 84) +-#define HW_INTERRUPTS__ETHERNET_ERR_INT_IRQ ( 91) +-#define HW_INTERRUPTS__FASTBUS_INTR_STATUS_OUT_IRQ (106) +-#define HW_INTERRUPTS__FLASH_CACHE_IRQ (119) +-#define HW_INTERRUPTS__GPIO_IRQ ( 43) +-#define HW_INTERRUPTS__H265_INT_IRQ (109) +-#define HW_INTERRUPTS__I2C0_IRQ ( 9) +-#define HW_INTERRUPTS__I2C1_IRQ ( 10) +-#define HW_INTERRUPTS__I2C2_IRQ ( 11) +-#define HW_INTERRUPTS__I2C3_IRQ ( 12) +-#define HW_INTERRUPTS__I2S_IRQ ( 15) +-#define HW_INTERRUPTS__ISP_FUNC_INTERRUPT_IRQ (118) +-#define HW_INTERRUPTS__NN_CORE_CLUSTER_BREAKPOINT_IRQ ( 93) +-#define HW_INTERRUPTS__NN_CORE_CONTEXT_SW_INTR_IRQ ( 94) +-#define HW_INTERRUPTS__NN_CORE_ERROR_IRQ ( 97) +-#define HW_INTERRUPTS__NN_CORE_INBOUND_DATA_IRQ ( 98) +-#define HW_INTERRUPTS__NN_CORE_INFO_IRQ ( 96) +-#define HW_INTERRUPTS__NN_CORE_OUTBOUND_DATA_INTR_IRQ (102) +-#define HW_INTERRUPTS__PCIE_ERROR_IRQ ( 99) +-#define HW_INTERRUPTS__PCIE_FUNC_IRQ (127) +-#define HW_INTERRUPTS__PVT_IRQ (126) +-#define HW_INTERRUPTS__QSPI_FLASH_IRQ ( 33) +-#define HW_INTERRUPTS__SAFETY_AGGREGATOR_FATAL_INTR_IRQ (100) +-#define HW_INTERRUPTS__SAFETY_AGGREGATOR_NONFATAL_INTR_IRQ (101) +-#define HW_INTERRUPTS__SDIO0_IRQ (115) +-#define HW_INTERRUPTS__SDIO0_GP_IN_IRQ ( 67) +-#define HW_INTERRUPTS__SDIO0_LED_CONTROL_IRQ (114) +-#define HW_INTERRUPTS__SDIO0_WAKEUP_IRQ (113) +-#define HW_INTERRUPTS__SDIO1_IRQ (112) +-#define HW_INTERRUPTS__SDIO1_GP_IN_IRQ ( 68) +-#define HW_INTERRUPTS__SDIO1_LED_CONTROL_IRQ (111) +-#define HW_INTERRUPTS__SDIO1_WAKEUP_IRQ (110) +-#define HW_INTERRUPTS__SW_DMA_AP_INT_0_IRQ ( 53) +-#define HW_INTERRUPTS__SW_DMA_AP_INT_1_IRQ ( 54) +-#define HW_INTERRUPTS__SW_DMA_AP_INT_2_IRQ (124) +-#define HW_INTERRUPTS__SW_DMA_AP_INT_3_IRQ (125) +-#define HW_INTERRUPTS__SW_DMA_ERR_INT_IRQ ( 74) +-#define HW_INTERRUPTS__TIMEOUT_MONITOR_TIMEOUT_REACHED_FAST_BUS_IRQ ( 66) +-#define HW_INTERRUPTS__TIMEOUT_MONITOR_TIMEOUT_REACHED_TOP_AHB_BUS_IRQ ( 65) +-#define HW_INTERRUPTS__TIMER0_IRQ ( 28) +-#define HW_INTERRUPTS__TIMER1_IRQ ( 29) +-#define HW_INTERRUPTS__TIMER2_IRQ ( 30) +-#define HW_INTERRUPTS__TIMER3_IRQ ( 31) +-#define HW_INTERRUPTS__UART0_IRQ_IRQ ( 1) +-#define HW_INTERRUPTS__UART1_IRQ_IRQ ( 2) +-#define HW_INTERRUPTS__UART2_IRQ_IRQ ( 3) +-#define HW_INTERRUPTS__UART3_IRQ_IRQ ( 4) +-#define HW_INTERRUPTS__USB_ERROR_INTR_IRQ ( 56) +-#define HW_INTERRUPTS__USB_INFO_INTR_IRQ ( 55) +-#define HW_INTERRUPTS__VISION_BUFFER_READY_AP_INT_IRQ ( 41) +-#define HW_INTERRUPTS__VISION_SUBSYS_ERR_INT_IRQ ( 38) +-#define HW_INTERRUPTS__WATCHDOG0_IRQ (107) +-#define HW_INTERRUPTS__WATCHDOG1_IRQ (108) +- +-#endif /* _DT_BINDINGS_HAILO15_INTERRUPTS */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/soc/hailo15_scmi_api.h b/scripts/dtc/include-prefixes/dt-bindings/soc/hailo15_scmi_api.h +deleted file mode 100644 +index 2b76b3cfdf6f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/soc/hailo15_scmi_api.h ++++ /dev/null +@@ -1,72 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2019-2024 Hailo Technologies Ltd. All rights reserved. +- */ +- +-#ifndef HAILO15_SCMI_API_H +-#define HAILO15_SCMI_API_H +- +-#define HAILO_SOC_HAILO15 1 +-#define HAILO_SOC_HAILO15L 2 +- +-#ifndef HAILO_SOC_TYPE +-# error "HAILO_SOC_TYPE is not defined" +-#endif +- +-#define HAILO15_SCMI_SENSOR_IDX_PVT_TEMPERATURE_SENSOR_0 0 +-#define HAILO15_SCMI_SENSOR_IDX_PVT_TEMPERATURE_SENSOR_1 1 +- +-/* Clocks IDs */ +-#define HAILO15_SCMI_CLOCK_IDX_HCLK 0 +-#define HAILO15_SCMI_CLOCK_IDX_SDIO_0_M_HCLK 1 +-#define HAILO15_SCMI_CLOCK_IDX_SDIO_1_M_HCLK 2 +-#define HAILO15_SCMI_CLOCK_IDX_DSP_CONFIG 3 +-#define HAILO15_SCMI_CLOCK_IDX_DSP_PLL 4 +-#define HAILO15_SCMI_CLOCK_IDX_DSP 5 +-#define HAILO15_SCMI_CLOCK_IDX_ETHERNET_PCLK 6 +-#define HAILO15_SCMI_CLOCK_IDX_ETHERNET_ACLK 7 +-#define HAILO15_SCMI_CLOCK_IDX_SDIO_0_CARD_CLK 8 +-#define HAILO15_SCMI_CLOCK_IDX_SDIO_1_CARD_CLK 9 +-#define HAILO15_SCMI_CLOCK_IDX_VISION_HCLK 10 +-#define HAILO15_SCMI_CLOCK_IDX_ISP_WRAPPER_PCLK 11 +-#define HAILO15_SCMI_CLOCK_IDX_CSI_RX0_PCLK 12 +-#define HAILO15_SCMI_CLOCK_IDX_CSI_RX1_PCLK 13 +-#define HAILO15_SCMI_CLOCK_IDX_CSI_TX0_PCLK 14 +-#define HAILO15_SCMI_CLOCK_IDX_VISION_CLK 15 +-#define HAILO15_SCMI_CLOCK_IDX_ISP_WRAPPER_CLK 16 +-#define HAILO15_SCMI_CLOCK_IDX_CSI_RX0_CLK 17 +-#define HAILO15_SCMI_CLOCK_IDX_CSI_RX1_CLK 18 +-#define HAILO15_SCMI_CLOCK_IDX_CSI_TX0_CLK 19 +-#define HAILO15_SCMI_CLOCK_IDX_CSI_RX0_XTAL_CLK 20 +-#define HAILO15_SCMI_CLOCK_IDX_CSI_RX1_XTAL_CLK 21 +-#define HAILO15_SCMI_CLOCK_IDX_CSI_TX0_XTAL_CLK 22 +-#define HAILO15_SCMI_CLOCK_IDX_MIPI_REF_CLK 23 +-#define HAILO15_SCMI_CLOCK_IDX_MIPI_ESC_CLK 24 +-#define HAILO15_SCMI_CLOCK_IDX_SDIO_0_CLK_DIV_BYPASS 25 +-#define HAILO15_SCMI_CLOCK_IDX_SDIO_1_CLK_DIV_BYPASS 26 +-#define HAILO15_SCMI_CLOCK_IDX_PCIE_REFCLK 27 +-#define HAILO15_SCMI_CLOCK_IDX_H265_HCLK 28 +-#define HAILO15_SCMI_CLOCK_IDX_H265_CLK 29 +-#if HAILO_SOC_TYPE == HAILO_SOC_HAILO15 +-# define HAILO15_SCMI_CLOCK_IDX_I2S_CLK_DIV 30 +-#endif /* HAILO_SOC_HAILO15 */ +- +-/* Resets IDs */ +-#define HAILO15_SCMI_RESET_IDX_CORE_CPU 0 +-#define HAILO15_SCMI_RESET_IDX_NN_CORE 1 +-#define HAILO15_SCMI_RESET_IDX_SDIO1_8BIT_MUX 2 +-#define HAILO15_SCMI_RESET_IDX_DSP 3 +-#define HAILO15_SCMI_RESET_IDX_SDIO_0_CD_FROM_PINMUX 4 +-#define HAILO15_SCMI_RESET_IDX_SDIO_1_CD_FROM_PINMUX 5 +-#define HAILO15_SCMI_RESET_IDX_PCIE_PHY_LANE_0 6 +-#define HAILO15_SCMI_RESET_IDX_PCIE_PHY_LANE_1 7 +-#define HAILO15_SCMI_RESET_IDX_PCIE_PHY_LANE_2 8 +-#define HAILO15_SCMI_RESET_IDX_PCIE_PHY_LANE_3 9 +-#define HAILO15_SCMI_RESET_IDX_PCIE_PHY 10 +- +-/* power domain IDs */ +-#define HAILO15_SCMI_POWER_DOMAIN_IDX_VISION_SUBSYS 0 +-#define HAILO15_SCMI_POWER_DOMAIN_IDX_SYSTOP 1 +-#define HAILO15_SCMI_POWER_DOMAIN_COUNT 2 +- +-#endif /* HAILO15_SCMI_API_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/soc/hailo15_scu_fw_version.h b/scripts/dtc/include-prefixes/dt-bindings/soc/hailo15_scu_fw_version.h +deleted file mode 100644 +index 901135dcc856..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/soc/hailo15_scu_fw_version.h ++++ /dev/null +@@ -1,14 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2019-2024 Hailo Technologies Ltd. All rights reserved. +- */ +- +-#ifndef HAILO15_SCU_FW_VERSION_H +-#define HAILO15_SCU_FW_VERSION_H +- +-#define SCU_FW_MAJOR 0 +-#define SCU_FW_MINOR 42 +-#define SCU_FW_REVISION 1 +-#define SCU_FW_BUILD_VERSION (((SCU_FW_MAJOR) << 24) | ((SCU_FW_MINOR) << 16) | (SCU_FW_REVISION)) +- +-#endif /* HAILO15_SCU_FW_VERSION_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/soc/qcom,apr.h b/scripts/dtc/include-prefixes/dt-bindings/soc/qcom,apr.h +deleted file mode 100644 +index 006362400c0f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/soc/qcom,apr.h ++++ /dev/null +@@ -1,28 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_BINDINGS_QCOM_APR_H +-#define __DT_BINDINGS_QCOM_APR_H +- +-/* Domain IDs */ +-#define APR_DOMAIN_SIM 0x1 +-#define APR_DOMAIN_PC 0x2 +-#define APR_DOMAIN_MODEM 0x3 +-#define APR_DOMAIN_ADSP 0x4 +-#define APR_DOMAIN_APPS 0x5 +-#define APR_DOMAIN_MAX 0x6 +- +-/* ADSP service IDs */ +-#define APR_SVC_ADSP_CORE 0x3 +-#define APR_SVC_AFE 0x4 +-#define APR_SVC_VSM 0x5 +-#define APR_SVC_VPM 0x6 +-#define APR_SVC_ASM 0x7 +-#define APR_SVC_ADM 0x8 +-#define APR_SVC_ADSP_MVM 0x09 +-#define APR_SVC_ADSP_CVS 0x0A +-#define APR_SVC_ADSP_CVP 0x0B +-#define APR_SVC_USM 0x0C +-#define APR_SVC_LSM 0x0D +-#define APR_SVC_VIDC 0x16 +-#define APR_SVC_MAX 0x17 +- +-#endif /* __DT_BINDINGS_QCOM_APR_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/soc/qcom,gsbi.h b/scripts/dtc/include-prefixes/dt-bindings/soc/qcom,gsbi.h +deleted file mode 100644 +index c00ab8c5f3bc..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/soc/qcom,gsbi.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* Copyright (c) 2013, The Linux Foundation. All rights reserved. +- */ +-#ifndef __DT_BINDINGS_QCOM_GSBI_H +-#define __DT_BINDINGS_QCOM_GSBI_H +- +-#define GSBI_PROT_IDLE 0 +-#define GSBI_PROT_I2C_UIM 1 +-#define GSBI_PROT_I2C 2 +-#define GSBI_PROT_SPI 3 +-#define GSBI_PROT_UART_W_FC 4 +-#define GSBI_PROT_UIM 5 +-#define GSBI_PROT_I2C_UART 6 +- +-#define GSBI_CRCI_QUP 0 +-#define GSBI_CRCI_UART 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/soc/qcom,rpmh-rsc.h b/scripts/dtc/include-prefixes/dt-bindings/soc/qcom,rpmh-rsc.h +deleted file mode 100644 +index 868f998ea998..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/soc/qcom,rpmh-rsc.h ++++ /dev/null +@@ -1,14 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +- */ +- +-#ifndef __DT_QCOM_RPMH_RSC_H__ +-#define __DT_QCOM_RPMH_RSC_H__ +- +-#define SLEEP_TCS 0 +-#define WAKE_TCS 1 +-#define ACTIVE_TCS 2 +-#define CONTROL_TCS 3 +- +-#endif /* __DT_QCOM_RPMH_RSC_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/soc/rockchip,boot-mode.h b/scripts/dtc/include-prefixes/dt-bindings/soc/rockchip,boot-mode.h +deleted file mode 100644 +index 4b0914c0989d..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/soc/rockchip,boot-mode.h ++++ /dev/null +@@ -1,16 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __ROCKCHIP_BOOT_MODE_H +-#define __ROCKCHIP_BOOT_MODE_H +- +-/*high 24 bits is tag, low 8 bits is type*/ +-#define REBOOT_FLAG 0x5242C300 +-/* normal boot */ +-#define BOOT_NORMAL (REBOOT_FLAG + 0) +-/* enter bootloader rockusb mode */ +-#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1) +-/* enter recovery */ +-#define BOOT_RECOVERY (REBOOT_FLAG + 3) +- /* enter fastboot mode */ +-#define BOOT_FASTBOOT (REBOOT_FLAG + 9) +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/soc/tegra-pmc.h b/scripts/dtc/include-prefixes/dt-bindings/soc/tegra-pmc.h +deleted file mode 100644 +index a99a457471ee..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/soc/tegra-pmc.h ++++ /dev/null +@@ -1,16 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. +- */ +- +-#ifndef _DT_BINDINGS_SOC_TEGRA_PMC_H +-#define _DT_BINDINGS_SOC_TEGRA_PMC_H +- +-#define TEGRA_PMC_CLK_OUT_1 0 +-#define TEGRA_PMC_CLK_OUT_2 1 +-#define TEGRA_PMC_CLK_OUT_3 2 +-#define TEGRA_PMC_CLK_BLINK 3 +- +-#define TEGRA_PMC_CLK_MAX 4 +- +-#endif /* _DT_BINDINGS_SOC_TEGRA_PMC_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/soc/ti,sci_pm_domain.h b/scripts/dtc/include-prefixes/dt-bindings/soc/ti,sci_pm_domain.h +deleted file mode 100644 +index 8f2a7360b65e..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/soc/ti,sci_pm_domain.h ++++ /dev/null +@@ -1,9 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +- +-#ifndef __DT_BINDINGS_TI_SCI_PM_DOMAIN_H +-#define __DT_BINDINGS_TI_SCI_PM_DOMAIN_H +- +-#define TI_SCI_PD_EXCLUSIVE 1 +-#define TI_SCI_PD_SHARED 0 +- +-#endif /* __DT_BINDINGS_TI_SCI_PM_DOMAIN_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/sound/adi,adau1977.h b/scripts/dtc/include-prefixes/dt-bindings/sound/adi,adau1977.h +deleted file mode 100644 +index 8eebec6570f2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/sound/adi,adau1977.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-#ifndef __DT_BINDINGS_ADI_ADAU1977_H__ +-#define __DT_BINDINGS_ADI_ADAU1977_H__ +- +-#define ADAU1977_MICBIAS_5V0 0x0 +-#define ADAU1977_MICBIAS_5V5 0x1 +-#define ADAU1977_MICBIAS_6V0 0x2 +-#define ADAU1977_MICBIAS_6V5 0x3 +-#define ADAU1977_MICBIAS_7V0 0x4 +-#define ADAU1977_MICBIAS_7V5 0x5 +-#define ADAU1977_MICBIAS_8V0 0x6 +-#define ADAU1977_MICBIAS_8V5 0x7 +-#define ADAU1977_MICBIAS_9V0 0x8 +- +-#endif /* __DT_BINDINGS_ADI_ADAU1977_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/sound/apq8016-lpass.h b/scripts/dtc/include-prefixes/dt-bindings/sound/apq8016-lpass.h +deleted file mode 100644 +index dc605c4bc224..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/sound/apq8016-lpass.h ++++ /dev/null +@@ -1,9 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_APQ8016_LPASS_H +-#define __DT_APQ8016_LPASS_H +- +-#include +- +-/* NOTE: Use qcom,lpass.h to define any AIF ID's for LPASS */ +- +-#endif /* __DT_APQ8016_LPASS_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/sound/audio-jack-events.h b/scripts/dtc/include-prefixes/dt-bindings/sound/audio-jack-events.h +deleted file mode 100644 +index 1b29b295126a..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/sound/audio-jack-events.h ++++ /dev/null +@@ -1,10 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __AUDIO_JACK_EVENTS_H +-#define __AUDIO_JACK_EVENTS_H +- +-#define JACK_HEADPHONE 1 +-#define JACK_MICROPHONE 2 +-#define JACK_LINEOUT 3 +-#define JACK_LINEIN 4 +- +-#endif /* __AUDIO_JACK_EVENTS_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/sound/cs35l32.h b/scripts/dtc/include-prefixes/dt-bindings/sound/cs35l32.h +deleted file mode 100644 +index 7549d5019e8b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/sound/cs35l32.h ++++ /dev/null +@@ -1,27 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_CS35L32_H +-#define __DT_CS35L32_H +- +-#define CS35L32_BOOST_MGR_AUTO 0 +-#define CS35L32_BOOST_MGR_AUTO_AUDIO 1 +-#define CS35L32_BOOST_MGR_BYPASS 2 +-#define CS35L32_BOOST_MGR_FIXED 3 +- +-#define CS35L32_DATA_CFG_LR_VP 0 +-#define CS35L32_DATA_CFG_LR_STAT 1 +-#define CS35L32_DATA_CFG_LR 2 +-#define CS35L32_DATA_CFG_LR_VPSTAT 3 +- +-#define CS35L32_BATT_THRESH_3_1V 0 +-#define CS35L32_BATT_THRESH_3_2V 1 +-#define CS35L32_BATT_THRESH_3_3V 2 +-#define CS35L32_BATT_THRESH_3_4V 3 +- +-#define CS35L32_BATT_RECOV_3_1V 0 +-#define CS35L32_BATT_RECOV_3_2V 1 +-#define CS35L32_BATT_RECOV_3_3V 2 +-#define CS35L32_BATT_RECOV_3_4V 3 +-#define CS35L32_BATT_RECOV_3_5V 4 +-#define CS35L32_BATT_RECOV_3_6V 5 +- +-#endif /* __DT_CS35L32_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/sound/cs42l42.h b/scripts/dtc/include-prefixes/dt-bindings/sound/cs42l42.h +deleted file mode 100644 +index f25d83c6188b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/sound/cs42l42.h ++++ /dev/null +@@ -1,69 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * cs42l42.h -- CS42L42 ALSA SoC audio driver DT bindings header +- * +- * Copyright 2016 Cirrus Logic, Inc. +- * +- * Author: James Schulman +- * Author: Brian Austin +- * Author: Michael White +- */ +- +-#ifndef __DT_CS42L42_H +-#define __DT_CS42L42_H +- +-/* HPOUT Load Capacity */ +-#define CS42L42_HPOUT_LOAD_1NF 0 +-#define CS42L42_HPOUT_LOAD_10NF 1 +- +-/* HPOUT Clamp to GND Override */ +-#define CS42L42_HPOUT_CLAMP_EN 0 +-#define CS42L42_HPOUT_CLAMP_DIS 1 +- +-/* Tip Sense Inversion */ +-#define CS42L42_TS_INV_DIS 0 +-#define CS42L42_TS_INV_EN 1 +- +-/* Tip Sense Debounce */ +-#define CS42L42_TS_DBNCE_0 0 +-#define CS42L42_TS_DBNCE_125 1 +-#define CS42L42_TS_DBNCE_250 2 +-#define CS42L42_TS_DBNCE_500 3 +-#define CS42L42_TS_DBNCE_750 4 +-#define CS42L42_TS_DBNCE_1000 5 +-#define CS42L42_TS_DBNCE_1250 6 +-#define CS42L42_TS_DBNCE_1500 7 +- +-/* Button Press Software Debounce Times */ +-#define CS42L42_BTN_DET_INIT_DBNCE_MIN 0 +-#define CS42L42_BTN_DET_INIT_DBNCE_DEFAULT 100 +-#define CS42L42_BTN_DET_INIT_DBNCE_MAX 200 +- +-#define CS42L42_BTN_DET_EVENT_DBNCE_MIN 0 +-#define CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT 10 +-#define CS42L42_BTN_DET_EVENT_DBNCE_MAX 20 +- +-/* Button Detect Level Sensitivities */ +-#define CS42L42_NUM_BIASES 4 +- +-#define CS42L42_HS_DET_LEVEL_15 0x0F +-#define CS42L42_HS_DET_LEVEL_8 0x08 +-#define CS42L42_HS_DET_LEVEL_4 0x04 +-#define CS42L42_HS_DET_LEVEL_1 0x01 +- +-#define CS42L42_HS_DET_LEVEL_MIN 0 +-#define CS42L42_HS_DET_LEVEL_MAX 0x3F +- +-/* HS Bias Ramp Rate */ +- +-#define CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL 0 +-#define CS42L42_HSBIAS_RAMP_FAST 1 +-#define CS42L42_HSBIAS_RAMP_SLOW 2 +-#define CS42L42_HSBIAS_RAMP_SLOWEST 3 +- +-#define CS42L42_HSBIAS_RAMP_TIME0 10 +-#define CS42L42_HSBIAS_RAMP_TIME1 40 +-#define CS42L42_HSBIAS_RAMP_TIME2 90 +-#define CS42L42_HSBIAS_RAMP_TIME3 170 +- +-#endif /* __DT_CS42L42_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/sound/fsl-imx-audmux.h b/scripts/dtc/include-prefixes/dt-bindings/sound/fsl-imx-audmux.h +deleted file mode 100644 +index 15f138bebe16..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/sound/fsl-imx-audmux.h ++++ /dev/null +@@ -1,64 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_FSL_IMX_AUDMUX_H +-#define __DT_FSL_IMX_AUDMUX_H +- +-#define MX27_AUDMUX_HPCR1_SSI0 0 +-#define MX27_AUDMUX_HPCR2_SSI1 1 +-#define MX27_AUDMUX_HPCR3_SSI_PINS_4 2 +-#define MX27_AUDMUX_PPCR1_SSI_PINS_1 3 +-#define MX27_AUDMUX_PPCR2_SSI_PINS_2 4 +-#define MX27_AUDMUX_PPCR3_SSI_PINS_3 5 +- +-#define MX31_AUDMUX_PORT1_SSI0 0 +-#define MX31_AUDMUX_PORT2_SSI1 1 +-#define MX31_AUDMUX_PORT3_SSI_PINS_3 2 +-#define MX31_AUDMUX_PORT4_SSI_PINS_4 3 +-#define MX31_AUDMUX_PORT5_SSI_PINS_5 4 +-#define MX31_AUDMUX_PORT6_SSI_PINS_6 5 +-#define MX31_AUDMUX_PORT7_SSI_PINS_7 6 +- +-#define MX51_AUDMUX_PORT1_SSI0 0 +-#define MX51_AUDMUX_PORT2_SSI1 1 +-#define MX51_AUDMUX_PORT3 2 +-#define MX51_AUDMUX_PORT4 3 +-#define MX51_AUDMUX_PORT5 4 +-#define MX51_AUDMUX_PORT6 5 +-#define MX51_AUDMUX_PORT7 6 +- +-/* +- * TFCSEL/RFCSEL (i.MX27) or TFSEL/TCSEL/RFSEL/RCSEL (i.MX31/51/53/6Q) +- * can be sourced from Rx/Tx. +- */ +-#define IMX_AUDMUX_RXFS 0x8 +-#define IMX_AUDMUX_RXCLK 0x8 +- +-/* Register definitions for the i.MX21/27 Digital Audio Multiplexer */ +-#define IMX_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff) +-#define IMX_AUDMUX_V1_PCR_INMEN (1 << 8) +-#define IMX_AUDMUX_V1_PCR_TXRXEN (1 << 10) +-#define IMX_AUDMUX_V1_PCR_SYN (1 << 12) +-#define IMX_AUDMUX_V1_PCR_RXDSEL(x) (((x) & 0x7) << 13) +-#define IMX_AUDMUX_V1_PCR_RFCSEL(x) (((x) & 0xf) << 20) +-#define IMX_AUDMUX_V1_PCR_RCLKDIR (1 << 24) +-#define IMX_AUDMUX_V1_PCR_RFSDIR (1 << 25) +-#define IMX_AUDMUX_V1_PCR_TFCSEL(x) (((x) & 0xf) << 26) +-#define IMX_AUDMUX_V1_PCR_TCLKDIR (1 << 30) +-#define IMX_AUDMUX_V1_PCR_TFSDIR (1 << 31) +- +-/* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */ +-#define IMX_AUDMUX_V2_PTCR_TFSDIR (1 << 31) +-#define IMX_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27) +-#define IMX_AUDMUX_V2_PTCR_TCLKDIR (1 << 26) +-#define IMX_AUDMUX_V2_PTCR_TCSEL(x) (((x) & 0xf) << 22) +-#define IMX_AUDMUX_V2_PTCR_RFSDIR (1 << 21) +-#define IMX_AUDMUX_V2_PTCR_RFSEL(x) (((x) & 0xf) << 17) +-#define IMX_AUDMUX_V2_PTCR_RCLKDIR (1 << 16) +-#define IMX_AUDMUX_V2_PTCR_RCSEL(x) (((x) & 0xf) << 12) +-#define IMX_AUDMUX_V2_PTCR_SYN (1 << 11) +- +-#define IMX_AUDMUX_V2_PDCR_RXDSEL(x) (((x) & 0x7) << 13) +-#define IMX_AUDMUX_V2_PDCR_TXRXEN (1 << 12) +-#define IMX_AUDMUX_V2_PDCR_MODE(x) (((x) & 0x3) << 8) +-#define IMX_AUDMUX_V2_PDCR_INMMASK(x) ((x) & 0xff) +- +-#endif /* __DT_FSL_IMX_AUDMUX_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/sound/madera.h b/scripts/dtc/include-prefixes/dt-bindings/sound/madera.h +deleted file mode 100644 +index d0096d5eb0da..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/sound/madera.h ++++ /dev/null +@@ -1,25 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Device Tree defines for Madera codecs +- * +- * Copyright (C) 2016-2017 Cirrus Logic, Inc. and +- * Cirrus Logic International Semiconductor Ltd. +- */ +- +-#ifndef DT_BINDINGS_SOUND_MADERA_H +-#define DT_BINDINGS_SOUND_MADERA_H +- +-#define MADERA_INMODE_DIFF 0 +-#define MADERA_INMODE_SE 1 +-#define MADERA_INMODE_DMIC 2 +- +-#define MADERA_DMIC_REF_MICVDD 0 +-#define MADERA_DMIC_REF_MICBIAS1 1 +-#define MADERA_DMIC_REF_MICBIAS2 2 +-#define MADERA_DMIC_REF_MICBIAS3 3 +- +-#define CS47L35_DMIC_REF_MICBIAS1B 1 +-#define CS47L35_DMIC_REF_MICBIAS2A 2 +-#define CS47L35_DMIC_REF_MICBIAS2B 3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/sound/meson-aiu.h b/scripts/dtc/include-prefixes/dt-bindings/sound/meson-aiu.h +deleted file mode 100644 +index 1051b8af298b..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/sound/meson-aiu.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_MESON_AIU_H +-#define __DT_MESON_AIU_H +- +-#define AIU_CPU 0 +-#define AIU_HDMI 1 +-#define AIU_ACODEC 2 +- +-#define CPU_I2S_FIFO 0 +-#define CPU_SPDIF_FIFO 1 +-#define CPU_I2S_ENCODER 2 +-#define CPU_SPDIF_ENCODER 3 +- +-#define CTRL_I2S 0 +-#define CTRL_PCM 1 +-#define CTRL_OUT 2 +- +-#endif /* __DT_MESON_AIU_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/sound/meson-g12a-toacodec.h b/scripts/dtc/include-prefixes/dt-bindings/sound/meson-g12a-toacodec.h +deleted file mode 100644 +index 69d7a75592a2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/sound/meson-g12a-toacodec.h ++++ /dev/null +@@ -1,10 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_MESON_G12A_TOACODEC_H +-#define __DT_MESON_G12A_TOACODEC_H +- +-#define TOACODEC_IN_A 0 +-#define TOACODEC_IN_B 1 +-#define TOACODEC_IN_C 2 +-#define TOACODEC_OUT 3 +- +-#endif /* __DT_MESON_G12A_TOACODEC_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/sound/meson-g12a-tohdmitx.h b/scripts/dtc/include-prefixes/dt-bindings/sound/meson-g12a-tohdmitx.h +deleted file mode 100644 +index c5e1f48d30d0..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/sound/meson-g12a-tohdmitx.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_MESON_G12A_TOHDMITX_H +-#define __DT_MESON_G12A_TOHDMITX_H +- +-#define TOHDMITX_I2S_IN_A 0 +-#define TOHDMITX_I2S_IN_B 1 +-#define TOHDMITX_I2S_IN_C 2 +-#define TOHDMITX_I2S_OUT 3 +-#define TOHDMITX_SPDIF_IN_A 4 +-#define TOHDMITX_SPDIF_IN_B 5 +-#define TOHDMITX_SPDIF_OUT 6 +- +-#endif /* __DT_MESON_G12A_TOHDMITX_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/sound/qcom,lpass.h b/scripts/dtc/include-prefixes/dt-bindings/sound/qcom,lpass.h +deleted file mode 100644 +index 7b0b80b38699..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/sound/qcom,lpass.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_QCOM_LPASS_H +-#define __DT_QCOM_LPASS_H +- +-#define MI2S_PRIMARY 0 +-#define MI2S_SECONDARY 1 +-#define MI2S_TERTIARY 2 +-#define MI2S_QUATERNARY 3 +-#define MI2S_QUINARY 4 +- +-#define LPASS_DP_RX 5 +- +-#define LPASS_MCLK0 0 +- +-#endif /* __DT_QCOM_LPASS_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/sound/qcom,q6afe.h b/scripts/dtc/include-prefixes/dt-bindings/sound/qcom,q6afe.h +deleted file mode 100644 +index 66c21ab03eef..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/sound/qcom,q6afe.h ++++ /dev/null +@@ -1,208 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_BINDINGS_Q6_AFE_H__ +-#define __DT_BINDINGS_Q6_AFE_H__ +- +-/* Audio Front End (AFE) virtual ports IDs */ +-#define HDMI_RX 1 +-#define SLIMBUS_0_RX 2 +-#define SLIMBUS_0_TX 3 +-#define SLIMBUS_1_RX 4 +-#define SLIMBUS_1_TX 5 +-#define SLIMBUS_2_RX 6 +-#define SLIMBUS_2_TX 7 +-#define SLIMBUS_3_RX 8 +-#define SLIMBUS_3_TX 9 +-#define SLIMBUS_4_RX 10 +-#define SLIMBUS_4_TX 11 +-#define SLIMBUS_5_RX 12 +-#define SLIMBUS_5_TX 13 +-#define SLIMBUS_6_RX 14 +-#define SLIMBUS_6_TX 15 +-#define PRIMARY_MI2S_RX 16 +-#define PRIMARY_MI2S_TX 17 +-#define SECONDARY_MI2S_RX 18 +-#define SECONDARY_MI2S_TX 19 +-#define TERTIARY_MI2S_RX 20 +-#define TERTIARY_MI2S_TX 21 +-#define QUATERNARY_MI2S_RX 22 +-#define QUATERNARY_MI2S_TX 23 +-#define PRIMARY_TDM_RX_0 24 +-#define PRIMARY_TDM_TX_0 25 +-#define PRIMARY_TDM_RX_1 26 +-#define PRIMARY_TDM_TX_1 27 +-#define PRIMARY_TDM_RX_2 28 +-#define PRIMARY_TDM_TX_2 29 +-#define PRIMARY_TDM_RX_3 30 +-#define PRIMARY_TDM_TX_3 31 +-#define PRIMARY_TDM_RX_4 32 +-#define PRIMARY_TDM_TX_4 33 +-#define PRIMARY_TDM_RX_5 34 +-#define PRIMARY_TDM_TX_5 35 +-#define PRIMARY_TDM_RX_6 36 +-#define PRIMARY_TDM_TX_6 37 +-#define PRIMARY_TDM_RX_7 38 +-#define PRIMARY_TDM_TX_7 39 +-#define SECONDARY_TDM_RX_0 40 +-#define SECONDARY_TDM_TX_0 41 +-#define SECONDARY_TDM_RX_1 42 +-#define SECONDARY_TDM_TX_1 43 +-#define SECONDARY_TDM_RX_2 44 +-#define SECONDARY_TDM_TX_2 45 +-#define SECONDARY_TDM_RX_3 46 +-#define SECONDARY_TDM_TX_3 47 +-#define SECONDARY_TDM_RX_4 48 +-#define SECONDARY_TDM_TX_4 49 +-#define SECONDARY_TDM_RX_5 50 +-#define SECONDARY_TDM_TX_5 51 +-#define SECONDARY_TDM_RX_6 52 +-#define SECONDARY_TDM_TX_6 53 +-#define SECONDARY_TDM_RX_7 54 +-#define SECONDARY_TDM_TX_7 55 +-#define TERTIARY_TDM_RX_0 56 +-#define TERTIARY_TDM_TX_0 57 +-#define TERTIARY_TDM_RX_1 58 +-#define TERTIARY_TDM_TX_1 59 +-#define TERTIARY_TDM_RX_2 60 +-#define TERTIARY_TDM_TX_2 61 +-#define TERTIARY_TDM_RX_3 62 +-#define TERTIARY_TDM_TX_3 63 +-#define TERTIARY_TDM_RX_4 64 +-#define TERTIARY_TDM_TX_4 65 +-#define TERTIARY_TDM_RX_5 66 +-#define TERTIARY_TDM_TX_5 67 +-#define TERTIARY_TDM_RX_6 68 +-#define TERTIARY_TDM_TX_6 69 +-#define TERTIARY_TDM_RX_7 70 +-#define TERTIARY_TDM_TX_7 71 +-#define QUATERNARY_TDM_RX_0 72 +-#define QUATERNARY_TDM_TX_0 73 +-#define QUATERNARY_TDM_RX_1 74 +-#define QUATERNARY_TDM_TX_1 75 +-#define QUATERNARY_TDM_RX_2 76 +-#define QUATERNARY_TDM_TX_2 77 +-#define QUATERNARY_TDM_RX_3 78 +-#define QUATERNARY_TDM_TX_3 79 +-#define QUATERNARY_TDM_RX_4 80 +-#define QUATERNARY_TDM_TX_4 81 +-#define QUATERNARY_TDM_RX_5 82 +-#define QUATERNARY_TDM_TX_5 83 +-#define QUATERNARY_TDM_RX_6 84 +-#define QUATERNARY_TDM_TX_6 85 +-#define QUATERNARY_TDM_RX_7 86 +-#define QUATERNARY_TDM_TX_7 87 +-#define QUINARY_TDM_RX_0 88 +-#define QUINARY_TDM_TX_0 89 +-#define QUINARY_TDM_RX_1 90 +-#define QUINARY_TDM_TX_1 91 +-#define QUINARY_TDM_RX_2 92 +-#define QUINARY_TDM_TX_2 93 +-#define QUINARY_TDM_RX_3 94 +-#define QUINARY_TDM_TX_3 95 +-#define QUINARY_TDM_RX_4 96 +-#define QUINARY_TDM_TX_4 97 +-#define QUINARY_TDM_RX_5 98 +-#define QUINARY_TDM_TX_5 99 +-#define QUINARY_TDM_RX_6 100 +-#define QUINARY_TDM_TX_6 101 +-#define QUINARY_TDM_RX_7 102 +-#define QUINARY_TDM_TX_7 103 +-#define DISPLAY_PORT_RX 104 +-#define WSA_CODEC_DMA_RX_0 105 +-#define WSA_CODEC_DMA_TX_0 106 +-#define WSA_CODEC_DMA_RX_1 107 +-#define WSA_CODEC_DMA_TX_1 108 +-#define WSA_CODEC_DMA_TX_2 109 +-#define VA_CODEC_DMA_TX_0 110 +-#define VA_CODEC_DMA_TX_1 111 +-#define VA_CODEC_DMA_TX_2 112 +-#define RX_CODEC_DMA_RX_0 113 +-#define TX_CODEC_DMA_TX_0 114 +-#define RX_CODEC_DMA_RX_1 115 +-#define TX_CODEC_DMA_TX_1 116 +-#define RX_CODEC_DMA_RX_2 117 +-#define TX_CODEC_DMA_TX_2 118 +-#define RX_CODEC_DMA_RX_3 119 +-#define TX_CODEC_DMA_TX_3 120 +-#define RX_CODEC_DMA_RX_4 121 +-#define TX_CODEC_DMA_TX_4 122 +-#define RX_CODEC_DMA_RX_5 123 +-#define TX_CODEC_DMA_TX_5 124 +-#define RX_CODEC_DMA_RX_6 125 +-#define RX_CODEC_DMA_RX_7 126 +-#define QUINARY_MI2S_RX 127 +-#define QUINARY_MI2S_TX 128 +- +-#define LPASS_CLK_ID_PRI_MI2S_IBIT 1 +-#define LPASS_CLK_ID_PRI_MI2S_EBIT 2 +-#define LPASS_CLK_ID_SEC_MI2S_IBIT 3 +-#define LPASS_CLK_ID_SEC_MI2S_EBIT 4 +-#define LPASS_CLK_ID_TER_MI2S_IBIT 5 +-#define LPASS_CLK_ID_TER_MI2S_EBIT 6 +-#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7 +-#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8 +-#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9 +-#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10 +-#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11 +-#define LPASS_CLK_ID_QUI_MI2S_IBIT 12 +-#define LPASS_CLK_ID_QUI_MI2S_EBIT 13 +-#define LPASS_CLK_ID_SEN_MI2S_IBIT 14 +-#define LPASS_CLK_ID_SEN_MI2S_EBIT 15 +-#define LPASS_CLK_ID_INT0_MI2S_IBIT 16 +-#define LPASS_CLK_ID_INT1_MI2S_IBIT 17 +-#define LPASS_CLK_ID_INT2_MI2S_IBIT 18 +-#define LPASS_CLK_ID_INT3_MI2S_IBIT 19 +-#define LPASS_CLK_ID_INT4_MI2S_IBIT 20 +-#define LPASS_CLK_ID_INT5_MI2S_IBIT 21 +-#define LPASS_CLK_ID_INT6_MI2S_IBIT 22 +-#define LPASS_CLK_ID_QUI_MI2S_OSR 23 +-#define LPASS_CLK_ID_PRI_PCM_IBIT 24 +-#define LPASS_CLK_ID_PRI_PCM_EBIT 25 +-#define LPASS_CLK_ID_SEC_PCM_IBIT 26 +-#define LPASS_CLK_ID_SEC_PCM_EBIT 27 +-#define LPASS_CLK_ID_TER_PCM_IBIT 28 +-#define LPASS_CLK_ID_TER_PCM_EBIT 29 +-#define LPASS_CLK_ID_QUAD_PCM_IBIT 30 +-#define LPASS_CLK_ID_QUAD_PCM_EBIT 31 +-#define LPASS_CLK_ID_QUIN_PCM_IBIT 32 +-#define LPASS_CLK_ID_QUIN_PCM_EBIT 33 +-#define LPASS_CLK_ID_QUI_PCM_OSR 34 +-#define LPASS_CLK_ID_PRI_TDM_IBIT 35 +-#define LPASS_CLK_ID_PRI_TDM_EBIT 36 +-#define LPASS_CLK_ID_SEC_TDM_IBIT 37 +-#define LPASS_CLK_ID_SEC_TDM_EBIT 38 +-#define LPASS_CLK_ID_TER_TDM_IBIT 39 +-#define LPASS_CLK_ID_TER_TDM_EBIT 40 +-#define LPASS_CLK_ID_QUAD_TDM_IBIT 41 +-#define LPASS_CLK_ID_QUAD_TDM_EBIT 42 +-#define LPASS_CLK_ID_QUIN_TDM_IBIT 43 +-#define LPASS_CLK_ID_QUIN_TDM_EBIT 44 +-#define LPASS_CLK_ID_QUIN_TDM_OSR 45 +-#define LPASS_CLK_ID_MCLK_1 46 +-#define LPASS_CLK_ID_MCLK_2 47 +-#define LPASS_CLK_ID_MCLK_3 48 +-#define LPASS_CLK_ID_MCLK_4 49 +-#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50 +-#define LPASS_CLK_ID_INT_MCLK_0 51 +-#define LPASS_CLK_ID_INT_MCLK_1 52 +-#define LPASS_CLK_ID_MCLK_5 53 +-#define LPASS_CLK_ID_WSA_CORE_MCLK 54 +-#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55 +-#define LPASS_CLK_ID_VA_CORE_MCLK 56 +-#define LPASS_CLK_ID_TX_CORE_MCLK 57 +-#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58 +-#define LPASS_CLK_ID_RX_CORE_MCLK 59 +-#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60 +-#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61 +- +-#define LPASS_HW_AVTIMER_VOTE 101 +-#define LPASS_HW_MACRO_VOTE 102 +-#define LPASS_HW_DCODEC_VOTE 103 +- +-#define Q6AFE_MAX_CLK_ID 104 +- +-#define LPASS_CLK_ATTRIBUTE_INVALID 0x0 +-#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 +-#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 +-#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 +- +-#endif /* __DT_BINDINGS_Q6_AFE_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/sound/qcom,q6asm.h b/scripts/dtc/include-prefixes/dt-bindings/sound/qcom,q6asm.h +deleted file mode 100644 +index f59d74f14395..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/sound/qcom,q6asm.h ++++ /dev/null +@@ -1,26 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_BINDINGS_Q6_ASM_H__ +-#define __DT_BINDINGS_Q6_ASM_H__ +- +-#define MSM_FRONTEND_DAI_MULTIMEDIA1 0 +-#define MSM_FRONTEND_DAI_MULTIMEDIA2 1 +-#define MSM_FRONTEND_DAI_MULTIMEDIA3 2 +-#define MSM_FRONTEND_DAI_MULTIMEDIA4 3 +-#define MSM_FRONTEND_DAI_MULTIMEDIA5 4 +-#define MSM_FRONTEND_DAI_MULTIMEDIA6 5 +-#define MSM_FRONTEND_DAI_MULTIMEDIA7 6 +-#define MSM_FRONTEND_DAI_MULTIMEDIA8 7 +-#define MSM_FRONTEND_DAI_MULTIMEDIA9 8 +-#define MSM_FRONTEND_DAI_MULTIMEDIA10 9 +-#define MSM_FRONTEND_DAI_MULTIMEDIA11 10 +-#define MSM_FRONTEND_DAI_MULTIMEDIA12 11 +-#define MSM_FRONTEND_DAI_MULTIMEDIA13 12 +-#define MSM_FRONTEND_DAI_MULTIMEDIA14 13 +-#define MSM_FRONTEND_DAI_MULTIMEDIA15 14 +-#define MSM_FRONTEND_DAI_MULTIMEDIA16 15 +- +-#define Q6ASM_DAI_TX_RX 0 +-#define Q6ASM_DAI_TX 1 +-#define Q6ASM_DAI_RX 2 +- +-#endif /* __DT_BINDINGS_Q6_ASM_H__ */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/sound/rt5640.h b/scripts/dtc/include-prefixes/dt-bindings/sound/rt5640.h +deleted file mode 100644 +index 154c9b4414f2..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/sound/rt5640.h ++++ /dev/null +@@ -1,25 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_RT5640_H +-#define __DT_RT5640_H +- +-#define RT5640_DMIC1_DATA_PIN_NONE 0 +-#define RT5640_DMIC1_DATA_PIN_IN1P 1 +-#define RT5640_DMIC1_DATA_PIN_GPIO3 2 +- +-#define RT5640_DMIC2_DATA_PIN_NONE 0 +-#define RT5640_DMIC2_DATA_PIN_IN1N 1 +-#define RT5640_DMIC2_DATA_PIN_GPIO4 2 +- +-#define RT5640_JD_SRC_GPIO1 1 +-#define RT5640_JD_SRC_JD1_IN4P 2 +-#define RT5640_JD_SRC_JD2_IN4N 3 +-#define RT5640_JD_SRC_GPIO2 4 +-#define RT5640_JD_SRC_GPIO3 5 +-#define RT5640_JD_SRC_GPIO4 6 +- +-#define RT5640_OVCD_SF_0P5 0 +-#define RT5640_OVCD_SF_0P75 1 +-#define RT5640_OVCD_SF_1P0 2 +-#define RT5640_OVCD_SF_1P5 3 +- +-#endif /* __DT_RT5640_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/sound/rt5651.h b/scripts/dtc/include-prefixes/dt-bindings/sound/rt5651.h +deleted file mode 100644 +index 2f2dac915168..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/sound/rt5651.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_RT5651_H +-#define __DT_RT5651_H +- +-#define RT5651_JD_NULL 0 +-#define RT5651_JD1_1 1 +-#define RT5651_JD1_2 2 +-#define RT5651_JD2 3 +- +-#define RT5651_OVCD_SF_0P5 0 +-#define RT5651_OVCD_SF_0P75 1 +-#define RT5651_OVCD_SF_1P0 2 +-#define RT5651_OVCD_SF_1P5 3 +- +-#endif /* __DT_RT5651_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/sound/samsung-i2s.h b/scripts/dtc/include-prefixes/dt-bindings/sound/samsung-i2s.h +deleted file mode 100644 +index 250de0d6c734..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/sound/samsung-i2s.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef _DT_BINDINGS_SAMSUNG_I2S_H +-#define _DT_BINDINGS_SAMSUNG_I2S_H +- +-#define CLK_I2S_CDCLK 0 /* the CDCLK (CODECLKO) gate clock */ +- +-#define CLK_I2S_RCLK_SRC 1 /* the RCLKSRC mux clock (corresponding to +- * RCLKSRC bit in IISMOD register) +- */ +- +-#define CLK_I2S_RCLK_PSR 2 /* the RCLK prescaler divider clock +- * (corresponding to the IISPSR register) +- */ +- +-#endif /* _DT_BINDINGS_SAMSUNG_I2S_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/sound/sc7180-lpass.h b/scripts/dtc/include-prefixes/dt-bindings/sound/sc7180-lpass.h +deleted file mode 100644 +index 5c1ee8b36b19..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/sound/sc7180-lpass.h ++++ /dev/null +@@ -1,9 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_SC7180_LPASS_H +-#define __DT_SC7180_LPASS_H +- +-#include +- +-/* NOTE: Use qcom,lpass.h to define any AIF ID's for LPASS */ +- +-#endif /* __DT_APQ8016_LPASS_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/sound/tas2552.h b/scripts/dtc/include-prefixes/dt-bindings/sound/tas2552.h +deleted file mode 100644 +index 0daeb8385837..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/sound/tas2552.h ++++ /dev/null +@@ -1,19 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_TAS2552_H +-#define __DT_TAS2552_H +- +-#define TAS2552_PLL_CLKIN (0) +-#define TAS2552_PDM_CLK (1) +-#define TAS2552_CLK_TARGET_MASK (1) +- +-#define TAS2552_PLL_CLKIN_MCLK ((0 << 1) | TAS2552_PLL_CLKIN) +-#define TAS2552_PLL_CLKIN_BCLK ((1 << 1) | TAS2552_PLL_CLKIN) +-#define TAS2552_PLL_CLKIN_IVCLKIN ((2 << 1) | TAS2552_PLL_CLKIN) +-#define TAS2552_PLL_CLKIN_1_8_FIXED ((3 << 1) | TAS2552_PLL_CLKIN) +- +-#define TAS2552_PDM_CLK_PLL ((0 << 1) | TAS2552_PDM_CLK) +-#define TAS2552_PDM_CLK_IVCLKIN ((1 << 1) | TAS2552_PDM_CLK) +-#define TAS2552_PDM_CLK_BCLK ((2 << 1) | TAS2552_PDM_CLK) +-#define TAS2552_PDM_CLK_MCLK ((3 << 1) | TAS2552_PDM_CLK) +- +-#endif /* __DT_TAS2552_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/sound/tlv320aic31xx-micbias.h b/scripts/dtc/include-prefixes/dt-bindings/sound/tlv320aic31xx-micbias.h +deleted file mode 100644 +index c6895a18a455..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/sound/tlv320aic31xx-micbias.h ++++ /dev/null +@@ -1,9 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_TLV320AIC31XX_MICBIAS_H +-#define __DT_TLV320AIC31XX_MICBIAS_H +- +-#define MICBIAS_2_0V 1 +-#define MICBIAS_2_5V 2 +-#define MICBIAS_AVDDV 3 +- +-#endif /* __DT_TLV320AIC31XX_MICBIAS_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/spmi/spmi.h b/scripts/dtc/include-prefixes/dt-bindings/spmi/spmi.h +deleted file mode 100644 +index ad4a43481de4..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/spmi/spmi.h ++++ /dev/null +@@ -1,10 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* Copyright (c) 2013, The Linux Foundation. All rights reserved. +- */ +-#ifndef __DT_BINDINGS_SPMI_H +-#define __DT_BINDINGS_SPMI_H +- +-#define SPMI_USID 0 +-#define SPMI_GSID 1 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/thermal/lm90.h b/scripts/dtc/include-prefixes/dt-bindings/thermal/lm90.h +deleted file mode 100644 +index eed91a16c32f..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/thermal/lm90.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for the LM90 thermal bindings. +- */ +- +-#ifndef _DT_BINDINGS_THERMAL_LM90_H_ +-#define _DT_BINDINGS_THERMAL_LM90_H_ +- +-#define LM90_LOCAL_TEMPERATURE 0 +-#define LM90_REMOTE_TEMPERATURE 1 +-#define LM90_REMOTE2_TEMPERATURE 2 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/thermal/tegra124-soctherm.h b/scripts/dtc/include-prefixes/dt-bindings/thermal/tegra124-soctherm.h +deleted file mode 100644 +index 444c7bdde146..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/thermal/tegra124-soctherm.h ++++ /dev/null +@@ -1,20 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This header provides constants for binding nvidia,tegra124-soctherm. +- */ +- +-#ifndef _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H +-#define _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H +- +-#define TEGRA124_SOCTHERM_SENSOR_CPU 0 +-#define TEGRA124_SOCTHERM_SENSOR_MEM 1 +-#define TEGRA124_SOCTHERM_SENSOR_GPU 2 +-#define TEGRA124_SOCTHERM_SENSOR_PLLX 3 +-#define TEGRA124_SOCTHERM_SENSOR_NUM 4 +- +-#define TEGRA_SOCTHERM_THROT_LEVEL_NONE 0 +-#define TEGRA_SOCTHERM_THROT_LEVEL_LOW 1 +-#define TEGRA_SOCTHERM_THROT_LEVEL_MED 2 +-#define TEGRA_SOCTHERM_THROT_LEVEL_HIGH 3 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/thermal/tegra186-bpmp-thermal.h b/scripts/dtc/include-prefixes/dt-bindings/thermal/tegra186-bpmp-thermal.h +deleted file mode 100644 +index a96b8fa31aab..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/thermal/tegra186-bpmp-thermal.h ++++ /dev/null +@@ -1,14 +0,0 @@ +-/* +- * This header provides constants for binding nvidia,tegra186-bpmp-thermal. +- */ +- +-#ifndef _DT_BINDINGS_THERMAL_TEGRA186_BPMP_THERMAL_H +-#define _DT_BINDINGS_THERMAL_TEGRA186_BPMP_THERMAL_H +- +-#define TEGRA186_BPMP_THERMAL_ZONE_CPU 2 +-#define TEGRA186_BPMP_THERMAL_ZONE_GPU 3 +-#define TEGRA186_BPMP_THERMAL_ZONE_AUX 4 +-#define TEGRA186_BPMP_THERMAL_ZONE_PLLX 5 +-#define TEGRA186_BPMP_THERMAL_ZONE_AO 6 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/thermal/tegra194-bpmp-thermal.h b/scripts/dtc/include-prefixes/dt-bindings/thermal/tegra194-bpmp-thermal.h +deleted file mode 100644 +index aa7fb08135ca..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/thermal/tegra194-bpmp-thermal.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* +- * This header provides constants for binding nvidia,tegra194-bpmp-thermal. +- */ +- +-#ifndef _DT_BINDINGS_THERMAL_TEGRA194_BPMP_THERMAL_H +-#define _DT_BINDINGS_THERMAL_TEGRA194_BPMP_THERMAL_H +- +-#define TEGRA194_BPMP_THERMAL_ZONE_CPU 2 +-#define TEGRA194_BPMP_THERMAL_ZONE_GPU 3 +-#define TEGRA194_BPMP_THERMAL_ZONE_AUX 4 +-#define TEGRA194_BPMP_THERMAL_ZONE_PLLX 5 +-#define TEGRA194_BPMP_THERMAL_ZONE_AO 6 +-#define TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX 7 +- +-#endif +diff --git a/scripts/dtc/include-prefixes/dt-bindings/thermal/thermal.h b/scripts/dtc/include-prefixes/dt-bindings/thermal/thermal.h +deleted file mode 100644 +index bc7babb1a67c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/thermal/thermal.h ++++ /dev/null +@@ -1,16 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * This header provides constants for most thermal bindings. +- * +- * Copyright (C) 2013 Texas Instruments +- * Eduardo Valentin +- */ +- +-#ifndef _DT_BINDINGS_THERMAL_THERMAL_H +-#define _DT_BINDINGS_THERMAL_THERMAL_H +- +-/* On cooling devices upper and lower limits */ +-#define THERMAL_NO_LIMIT (~0) +- +-#endif +- +diff --git a/scripts/dtc/include-prefixes/dt-bindings/thermal/thermal_exynos.h b/scripts/dtc/include-prefixes/dt-bindings/thermal/thermal_exynos.h +deleted file mode 100644 +index 52fcb51dda3c..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/thermal/thermal_exynos.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * thermal_exynos.h - Samsung Exynos TMU device tree definitions +- * +- * Copyright (C) 2014 Samsung Electronics +- * Lukasz Majewski +- */ +- +-#ifndef _EXYNOS_THERMAL_TMU_DT_H +-#define _EXYNOS_THERMAL_TMU_DT_H +- +-#define TYPE_ONE_POINT_TRIMMING 0 +-#define TYPE_ONE_POINT_TRIMMING_25 1 +-#define TYPE_ONE_POINT_TRIMMING_85 2 +-#define TYPE_TWO_POINT_TRIMMING 3 +-#define TYPE_NONE 4 +- +-#endif /* _EXYNOS_THERMAL_TMU_DT_H */ +diff --git a/scripts/dtc/include-prefixes/dt-bindings/usb/pd.h b/scripts/dtc/include-prefixes/dt-bindings/usb/pd.h +deleted file mode 100644 +index e6526b138174..000000000000 +--- a/scripts/dtc/include-prefixes/dt-bindings/usb/pd.h ++++ /dev/null +@@ -1,468 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __DT_POWER_DELIVERY_H +-#define __DT_POWER_DELIVERY_H +- +-/* Power delivery Power Data Object definitions */ +-#define PDO_TYPE_FIXED 0 +-#define PDO_TYPE_BATT 1 +-#define PDO_TYPE_VAR 2 +-#define PDO_TYPE_APDO 3 +- +-#define PDO_TYPE_SHIFT 30 +-#define PDO_TYPE_MASK 0x3 +- +-#define PDO_TYPE(t) ((t) << PDO_TYPE_SHIFT) +- +-#define PDO_VOLT_MASK 0x3ff +-#define PDO_CURR_MASK 0x3ff +-#define PDO_PWR_MASK 0x3ff +- +-#define PDO_FIXED_DUAL_ROLE (1 << 29) /* Power role swap supported */ +-#define PDO_FIXED_SUSPEND (1 << 28) /* USB Suspend supported (Source) */ +-#define PDO_FIXED_HIGHER_CAP (1 << 28) /* Requires more than vSafe5V (Sink) */ +-#define PDO_FIXED_EXTPOWER (1 << 27) /* Externally powered */ +-#define PDO_FIXED_USB_COMM (1 << 26) /* USB communications capable */ +-#define PDO_FIXED_DATA_SWAP (1 << 25) /* Data role swap supported */ +-#define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */ +-#define PDO_FIXED_CURR_SHIFT 0 /* 10mA units */ +- +-#define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) +-#define PDO_FIXED_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT) +- +-#define PDO_FIXED(mv, ma, flags) \ +- (PDO_TYPE(PDO_TYPE_FIXED) | (flags) | \ +- PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma)) +- +-#define VSAFE5V 5000 /* mv units */ +- +-#define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */ +-#define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */ +-#define PDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */ +- +-#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT) +-#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT) +-#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT) +- +-#define PDO_BATT(min_mv, max_mv, max_mw) \ +- (PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) | \ +- PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw)) +- +-#define PDO_VAR_MAX_VOLT_SHIFT 20 /* 50mV units */ +-#define PDO_VAR_MIN_VOLT_SHIFT 10 /* 50mV units */ +-#define PDO_VAR_MAX_CURR_SHIFT 0 /* 10mA units */ +- +-#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT) +-#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT) +-#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT) +- +-#define PDO_VAR(min_mv, max_mv, max_ma) \ +- (PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) | \ +- PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma)) +- +-#define APDO_TYPE_PPS 0 +- +-#define PDO_APDO_TYPE_SHIFT 28 /* Only valid value currently is 0x0 - PPS */ +-#define PDO_APDO_TYPE_MASK 0x3 +- +-#define PDO_APDO_TYPE(t) ((t) << PDO_APDO_TYPE_SHIFT) +- +-#define PDO_PPS_APDO_MAX_VOLT_SHIFT 17 /* 100mV units */ +-#define PDO_PPS_APDO_MIN_VOLT_SHIFT 8 /* 100mV units */ +-#define PDO_PPS_APDO_MAX_CURR_SHIFT 0 /* 50mA units */ +- +-#define PDO_PPS_APDO_VOLT_MASK 0xff +-#define PDO_PPS_APDO_CURR_MASK 0x7f +- +-#define PDO_PPS_APDO_MIN_VOLT(mv) \ +- ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MIN_VOLT_SHIFT) +-#define PDO_PPS_APDO_MAX_VOLT(mv) \ +- ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MAX_VOLT_SHIFT) +-#define PDO_PPS_APDO_MAX_CURR(ma) \ +- ((((ma) / 50) & PDO_PPS_APDO_CURR_MASK) << PDO_PPS_APDO_MAX_CURR_SHIFT) +- +-#define PDO_PPS_APDO(min_mv, max_mv, max_ma) \ +- (PDO_TYPE(PDO_TYPE_APDO) | PDO_APDO_TYPE(APDO_TYPE_PPS) | \ +- PDO_PPS_APDO_MIN_VOLT(min_mv) | PDO_PPS_APDO_MAX_VOLT(max_mv) | \ +- PDO_PPS_APDO_MAX_CURR(max_ma)) +- +- /* +- * Based on "Table 6-14 Fixed Supply PDO - Sink" of "USB Power Delivery Specification Revision 3.0, +- * Version 1.2" +- * Initial current capability of the new source when vSafe5V is applied. +- */ +-#define FRS_DEFAULT_POWER 1 +-#define FRS_5V_1P5A 2 +-#define FRS_5V_3A 3 +- +-/* +- * SVDM Identity Header +- * -------------------- +- * <31> :: data capable as a USB host +- * <30> :: data capable as a USB device +- * <29:27> :: product type (UFP / Cable / VPD) +- * <26> :: modal operation supported (1b == yes) +- * <25:23> :: product type (DFP) (SVDM version 2.0+ only; set to zero in version 1.0) +- * <22:21> :: connector type (SVDM version 2.0+ only; set to zero in version 1.0) +- * <20:16> :: Reserved, Shall be set to zero +- * <15:0> :: USB-IF assigned VID for this cable vendor +- */ +- +-/* PD Rev2.0 definition */ +-#define IDH_PTYPE_UNDEF 0 +- +-/* SOP Product Type (UFP) */ +-#define IDH_PTYPE_NOT_UFP 0 +-#define IDH_PTYPE_HUB 1 +-#define IDH_PTYPE_PERIPH 2 +-#define IDH_PTYPE_PSD 3 +-#define IDH_PTYPE_AMA 5 +- +-/* SOP' Product Type (Cable Plug / VPD) */ +-#define IDH_PTYPE_NOT_CABLE 0 +-#define IDH_PTYPE_PCABLE 3 +-#define IDH_PTYPE_ACABLE 4 +-#define IDH_PTYPE_VPD 6 +- +-/* SOP Product Type (DFP) */ +-#define IDH_PTYPE_NOT_DFP 0 +-#define IDH_PTYPE_DFP_HUB 1 +-#define IDH_PTYPE_DFP_HOST 2 +-#define IDH_PTYPE_DFP_PB 3 +- +-#define VDO_IDH(usbh, usbd, ufp_cable, is_modal, dfp, conn, vid) \ +- ((usbh) << 31 | (usbd) << 30 | ((ufp_cable) & 0x7) << 27 \ +- | (is_modal) << 26 | ((dfp) & 0x7) << 23 | ((conn) & 0x3) << 21 \ +- | ((vid) & 0xffff)) +- +-/* +- * Cert Stat VDO +- * ------------- +- * <31:0> : USB-IF assigned XID for this cable +- */ +-#define VDO_CERT(xid) ((xid) & 0xffffffff) +- +-/* +- * Product VDO +- * ----------- +- * <31:16> : USB Product ID +- * <15:0> : USB bcdDevice +- */ +-#define VDO_PRODUCT(pid, bcd) (((pid) & 0xffff) << 16 | ((bcd) & 0xffff)) +- +-/* +- * UFP VDO (PD Revision 3.0+ only) +- * -------- +- * <31:29> :: UFP VDO version +- * <28> :: Reserved +- * <27:24> :: Device capability +- * <23:22> :: Connector type (10b == receptacle, 11b == captive plug) +- * <21:11> :: Reserved +- * <10:8> :: Vconn power (AMA only) +- * <7> :: Vconn required (AMA only, 0b == no, 1b == yes) +- * <6> :: Vbus required (AMA only, 0b == yes, 1b == no) +- * <5:3> :: Alternate modes +- * <2:0> :: USB highest speed +- */ +-/* UFP VDO Version */ +-#define UFP_VDO_VER1_2 2 +- +-/* Device Capability */ +-#define DEV_USB2_CAPABLE (1 << 0) +-#define DEV_USB2_BILLBOARD (1 << 1) +-#define DEV_USB3_CAPABLE (1 << 2) +-#define DEV_USB4_CAPABLE (1 << 3) +- +-/* Connector Type */ +-#define UFP_RECEPTACLE 2 +-#define UFP_CAPTIVE 3 +- +-/* Vconn Power (AMA only, set to AMA_VCONN_NOT_REQ if Vconn is not required) */ +-#define AMA_VCONN_PWR_1W 0 +-#define AMA_VCONN_PWR_1W5 1 +-#define AMA_VCONN_PWR_2W 2 +-#define AMA_VCONN_PWR_3W 3 +-#define AMA_VCONN_PWR_4W 4 +-#define AMA_VCONN_PWR_5W 5 +-#define AMA_VCONN_PWR_6W 6 +- +-/* Vconn Required (AMA only) */ +-#define AMA_VCONN_NOT_REQ 0 +-#define AMA_VCONN_REQ 1 +- +-/* Vbus Required (AMA only) */ +-#define AMA_VBUS_REQ 0 +-#define AMA_VBUS_NOT_REQ 1 +- +-/* Alternate Modes */ +-#define UFP_ALTMODE_NOT_SUPP 0 +-#define UFP_ALTMODE_TBT3 (1 << 0) +-#define UFP_ALTMODE_RECFG (1 << 1) +-#define UFP_ALTMODE_NO_RECFG (1 << 2) +- +-/* USB Highest Speed */ +-#define UFP_USB2_ONLY 0 +-#define UFP_USB32_GEN1 1 +-#define UFP_USB32_4_GEN2 2 +-#define UFP_USB4_GEN3 3 +- +-#define VDO_UFP(ver, cap, conn, vcpwr, vcr, vbr, alt, spd) \ +- (((ver) & 0x7) << 29 | ((cap) & 0xf) << 24 | ((conn) & 0x3) << 22 \ +- | ((vcpwr) & 0x7) << 8 | (vcr) << 7 | (vbr) << 6 | ((alt) & 0x7) << 3 \ +- | ((spd) & 0x7)) +- +-/* +- * DFP VDO (PD Revision 3.0+ only) +- * -------- +- * <31:29> :: DFP VDO version +- * <28:27> :: Reserved +- * <26:24> :: Host capability +- * <23:22> :: Connector type (10b == receptacle, 11b == captive plug) +- * <21:5> :: Reserved +- * <4:0> :: Port number +- */ +-#define DFP_VDO_VER1_1 1 +-#define HOST_USB2_CAPABLE (1 << 0) +-#define HOST_USB3_CAPABLE (1 << 1) +-#define HOST_USB4_CAPABLE (1 << 2) +-#define DFP_RECEPTACLE 2 +-#define DFP_CAPTIVE 3 +- +-#define VDO_DFP(ver, cap, conn, pnum) \ +- (((ver) & 0x7) << 29 | ((cap) & 0x7) << 24 | ((conn) & 0x3) << 22 \ +- | ((pnum) & 0x1f)) +- +-/* +- * Cable VDO (for both Passive and Active Cable VDO in PD Rev2.0) +- * --------- +- * <31:28> :: Cable HW version +- * <27:24> :: Cable FW version +- * <23:20> :: Reserved, Shall be set to zero +- * <19:18> :: type-C to Type-A/B/C/Captive (00b == A, 01 == B, 10 == C, 11 == Captive) +- * <17> :: Reserved, Shall be set to zero +- * <16:13> :: cable latency (0001 == <10ns(~1m length)) +- * <12:11> :: cable termination type (11b == both ends active VCONN req) +- * <10> :: SSTX1 Directionality support (0b == fixed, 1b == cfgable) +- * <9> :: SSTX2 Directionality support +- * <8> :: SSRX1 Directionality support +- * <7> :: SSRX2 Directionality support +- * <6:5> :: Vbus current handling capability (01b == 3A, 10b == 5A) +- * <4> :: Vbus through cable (0b == no, 1b == yes) +- * <3> :: SOP" controller present? (0b == no, 1b == yes) +- * <2:0> :: USB SS Signaling support +- * +- * Passive Cable VDO (PD Rev3.0+) +- * --------- +- * <31:28> :: Cable HW version +- * <27:24> :: Cable FW version +- * <23:21> :: VDO version +- * <20> :: Reserved, Shall be set to zero +- * <19:18> :: Type-C to Type-C/Captive (10b == C, 11b == Captive) +- * <17> :: Reserved, Shall be set to zero +- * <16:13> :: cable latency (0001 == <10ns(~1m length)) +- * <12:11> :: cable termination type (10b == Vconn not req, 01b == Vconn req) +- * <10:9> :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V) +- * <8:7> :: Reserved, Shall be set to zero +- * <6:5> :: Vbus current handling capability (01b == 3A, 10b == 5A) +- * <4:3> :: Reserved, Shall be set to zero +- * <2:0> :: USB highest speed +- * +- * Active Cable VDO 1 (PD Rev3.0+) +- * --------- +- * <31:28> :: Cable HW version +- * <27:24> :: Cable FW version +- * <23:21> :: VDO version +- * <20> :: Reserved, Shall be set to zero +- * <19:18> :: Connector type (10b == C, 11b == Captive) +- * <17> :: Reserved, Shall be set to zero +- * <16:13> :: cable latency (0001 == <10ns(~1m length)) +- * <12:11> :: cable termination type (10b == one end active, 11b == both ends active VCONN req) +- * <10:9> :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V) +- * <8> :: SBU supported (0b == supported, 1b == not supported) +- * <7> :: SBU type (0b == passive, 1b == active) +- * <6:5> :: Vbus current handling capability (01b == 3A, 10b == 5A) +- * <4> :: Vbus through cable (0b == no, 1b == yes) +- * <3> :: SOP" controller present? (0b == no, 1b == yes) +- * <2:0> :: USB highest speed +- */ +-/* Cable VDO Version */ +-#define CABLE_VDO_VER1_0 0 +-#define CABLE_VDO_VER1_3 3 +- +-/* Connector Type (_ATYPE and _BTYPE are for PD Rev2.0 only) */ +-#define CABLE_ATYPE 0 +-#define CABLE_BTYPE 1 +-#define CABLE_CTYPE 2 +-#define CABLE_CAPTIVE 3 +- +-/* Cable Latency */ +-#define CABLE_LATENCY_1M 1 +-#define CABLE_LATENCY_2M 2 +-#define CABLE_LATENCY_3M 3 +-#define CABLE_LATENCY_4M 4 +-#define CABLE_LATENCY_5M 5 +-#define CABLE_LATENCY_6M 6 +-#define CABLE_LATENCY_7M 7 +-#define CABLE_LATENCY_7M_PLUS 8 +- +-/* Cable Termination Type */ +-#define PCABLE_VCONN_NOT_REQ 0 +-#define PCABLE_VCONN_REQ 1 +-#define ACABLE_ONE_END 2 +-#define ACABLE_BOTH_END 3 +- +-/* Maximum Vbus Voltage */ +-#define CABLE_MAX_VBUS_20V 0 +-#define CABLE_MAX_VBUS_30V 1 +-#define CABLE_MAX_VBUS_40V 2 +-#define CABLE_MAX_VBUS_50V 3 +- +-/* Active Cable SBU Supported/Type */ +-#define ACABLE_SBU_SUPP 0 +-#define ACABLE_SBU_NOT_SUPP 1 +-#define ACABLE_SBU_PASSIVE 0 +-#define ACABLE_SBU_ACTIVE 1 +- +-/* Vbus Current Handling Capability */ +-#define CABLE_CURR_DEF 0 +-#define CABLE_CURR_3A 1 +-#define CABLE_CURR_5A 2 +- +-/* USB SuperSpeed Signaling Support (PD Rev2.0) */ +-#define CABLE_USBSS_U2_ONLY 0 +-#define CABLE_USBSS_U31_GEN1 1 +-#define CABLE_USBSS_U31_GEN2 2 +- +-/* USB Highest Speed */ +-#define CABLE_USB2_ONLY 0 +-#define CABLE_USB32_GEN1 1 +-#define CABLE_USB32_4_GEN2 2 +-#define CABLE_USB4_GEN3 3 +- +-#define VDO_CABLE(hw, fw, cbl, lat, term, tx1d, tx2d, rx1d, rx2d, cur, vps, sopp, usbss) \ +- (((hw) & 0x7) << 28 | ((fw) & 0x7) << 24 | ((cbl) & 0x3) << 18 \ +- | ((lat) & 0x7) << 13 | ((term) & 0x3) << 11 | (tx1d) << 10 \ +- | (tx2d) << 9 | (rx1d) << 8 | (rx2d) << 7 | ((cur) & 0x3) << 5 \ +- | (vps) << 4 | (sopp) << 3 | ((usbss) & 0x7)) +-#define VDO_PCABLE(hw, fw, ver, conn, lat, term, vbm, cur, spd) \ +- (((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 | ((ver) & 0x7) << 21 \ +- | ((conn) & 0x3) << 18 | ((lat) & 0xf) << 13 | ((term) & 0x3) << 11 \ +- | ((vbm) & 0x3) << 9 | ((cur) & 0x3) << 5 | ((spd) & 0x7)) +-#define VDO_ACABLE1(hw, fw, ver, conn, lat, term, vbm, sbu, sbut, cur, vbt, sopp, spd) \ +- (((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 | ((ver) & 0x7) << 21 \ +- | ((conn) & 0x3) << 18 | ((lat) & 0xf) << 13 | ((term) & 0x3) << 11 \ +- | ((vbm) & 0x3) << 9 | (sbu) << 8 | (sbut) << 7 | ((cur) & 0x3) << 5 \ +- | (vbt) << 4 | (sopp) << 3 | ((spd) & 0x7)) +- +-/* +- * Active Cable VDO 2 +- * --------- +- * <31:24> :: Maximum operating temperature +- * <23:16> :: Shutdown temperature +- * <15> :: Reserved, Shall be set to zero +- * <14:12> :: U3/CLd power +- * <11> :: U3 to U0 transition mode (0b == direct, 1b == through U3S) +- * <10> :: Physical connection (0b == copper, 1b == optical) +- * <9> :: Active element (0b == redriver, 1b == retimer) +- * <8> :: USB4 supported (0b == yes, 1b == no) +- * <7:6> :: USB2 hub hops consumed +- * <5> :: USB2 supported (0b == yes, 1b == no) +- * <4> :: USB3.2 supported (0b == yes, 1b == no) +- * <3> :: USB lanes supported (0b == one lane, 1b == two lanes) +- * <2> :: Optically isolated active cable (0b == no, 1b == yes) +- * <1> :: Reserved, Shall be set to zero +- * <0> :: USB gen (0b == gen1, 1b == gen2+) +- */ +-/* U3/CLd Power*/ +-#define ACAB2_U3_CLD_10MW_PLUS 0 +-#define ACAB2_U3_CLD_10MW 1 +-#define ACAB2_U3_CLD_5MW 2 +-#define ACAB2_U3_CLD_1MW 3 +-#define ACAB2_U3_CLD_500UW 4 +-#define ACAB2_U3_CLD_200UW 5 +-#define ACAB2_U3_CLD_50UW 6 +- +-/* Other Active Cable VDO 2 Fields */ +-#define ACAB2_U3U0_DIRECT 0 +-#define ACAB2_U3U0_U3S 1 +-#define ACAB2_PHY_COPPER 0 +-#define ACAB2_PHY_OPTICAL 1 +-#define ACAB2_REDRIVER 0 +-#define ACAB2_RETIMER 1 +-#define ACAB2_USB4_SUPP 0 +-#define ACAB2_USB4_NOT_SUPP 1 +-#define ACAB2_USB2_SUPP 0 +-#define ACAB2_USB2_NOT_SUPP 1 +-#define ACAB2_USB32_SUPP 0 +-#define ACAB2_USB32_NOT_SUPP 1 +-#define ACAB2_LANES_ONE 0 +-#define ACAB2_LANES_TWO 1 +-#define ACAB2_OPT_ISO_NO 0 +-#define ACAB2_OPT_ISO_YES 1 +-#define ACAB2_GEN_1 0 +-#define ACAB2_GEN_2_PLUS 1 +- +-#define VDO_ACABLE2(mtemp, stemp, u3p, trans, phy, ele, u4, hops, u2, u32, lane, iso, gen) \ +- (((mtemp) & 0xff) << 24 | ((stemp) & 0xff) << 16 | ((u3p) & 0x7) << 12 \ +- | (trans) << 11 | (phy) << 10 | (ele) << 9 | (u4) << 8 \ +- | ((hops) & 0x3) << 6 | (u2) << 5 | (u32) << 4 | (lane) << 3 \ +- | (iso) << 2 | (gen)) +- +-/* +- * AMA VDO (PD Rev2.0) +- * --------- +- * <31:28> :: Cable HW version +- * <27:24> :: Cable FW version +- * <23:12> :: Reserved, Shall be set to zero +- * <11> :: SSTX1 Directionality support (0b == fixed, 1b == cfgable) +- * <10> :: SSTX2 Directionality support +- * <9> :: SSRX1 Directionality support +- * <8> :: SSRX2 Directionality support +- * <7:5> :: Vconn power +- * <4> :: Vconn power required +- * <3> :: Vbus power required +- * <2:0> :: USB SS Signaling support +- */ +-#define VDO_AMA(hw, fw, tx1d, tx2d, rx1d, rx2d, vcpwr, vcr, vbr, usbss) \ +- (((hw) & 0x7) << 28 | ((fw) & 0x7) << 24 \ +- | (tx1d) << 11 | (tx2d) << 10 | (rx1d) << 9 | (rx2d) << 8 \ +- | ((vcpwr) & 0x7) << 5 | (vcr) << 4 | (vbr) << 3 \ +- | ((usbss) & 0x7)) +- +-#define PD_VDO_AMA_VCONN_REQ(vdo) (((vdo) >> 4) & 1) +-#define PD_VDO_AMA_VBUS_REQ(vdo) (((vdo) >> 3) & 1) +- +-#define AMA_USBSS_U2_ONLY 0 +-#define AMA_USBSS_U31_GEN1 1 +-#define AMA_USBSS_U31_GEN2 2 +-#define AMA_USBSS_BBONLY 3 +- +-/* +- * VPD VDO +- * --------- +- * <31:28> :: HW version +- * <27:24> :: FW version +- * <23:21> :: VDO version +- * <20:17> :: Reserved, Shall be set to zero +- * <16:15> :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V) +- * <14> :: Charge through current support (0b == 3A, 1b == 5A) +- * <13> :: Reserved, Shall be set to zero +- * <12:7> :: Vbus impedance +- * <6:1> :: Ground impedance +- * <0> :: Charge through support (0b == no, 1b == yes) +- */ +-#define VPD_VDO_VER1_0 0 +-#define VPD_MAX_VBUS_20V 0 +-#define VPD_MAX_VBUS_30V 1 +-#define VPD_MAX_VBUS_40V 2 +-#define VPD_MAX_VBUS_50V 3 +-#define VPDCT_CURR_3A 0 +-#define VPDCT_CURR_5A 1 +-#define VPDCT_NOT_SUPP 0 +-#define VPDCT_SUPP 1 +- +-#define VDO_VPD(hw, fw, ver, vbm, curr, vbi, gi, ct) \ +- (((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 | ((ver) & 0x7) << 21 \ +- | ((vbm) & 0x3) << 15 | (curr) << 14 | ((vbi) & 0x3f) << 7 \ +- | ((gi) & 0x3f) << 1 | (ct)) +- +-#endif /* __DT_POWER_DELIVERY_H */ +diff --git a/scripts/dtc/include-prefixes/h8300 b/scripts/dtc/include-prefixes/h8300 +new file mode 120000 +index 000000000000..3bdaa332c54c +--- /dev/null ++++ b/scripts/dtc/include-prefixes/h8300 +@@ -0,0 +1 @@ ++../../../arch/h8300/boot/dts +\ No newline at end of file +diff --git a/scripts/dtc/include-prefixes/h8300/Makefile b/scripts/dtc/include-prefixes/h8300/Makefile +deleted file mode 100644 +index 69fcd817892c..000000000000 +--- a/scripts/dtc/include-prefixes/h8300/Makefile ++++ /dev/null +@@ -1,10 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-ifneq '$(CONFIG_H8300_BUILTIN_DTB)' '""' +-BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_H8300_BUILTIN_DTB)).dtb.o +-endif +- +-obj-y += $(BUILTIN_DTB) +- +-dtb-$(CONFIG_H8300H_SIM) := h8300h_sim.dtb +-dtb-$(CONFIG_H8S_SIM) := h8s_sim.dtb +-dtb-$(CONFIG_H8S_EDOSK2674) := edosk2674.dtb +diff --git a/scripts/dtc/include-prefixes/h8300/edosk2674.dts b/scripts/dtc/include-prefixes/h8300/edosk2674.dts +deleted file mode 100644 +index d1733805ea67..000000000000 +--- a/scripts/dtc/include-prefixes/h8300/edosk2674.dts ++++ /dev/null +@@ -1,108 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-/ { +- compatible = "renesas,edosk2674"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&h8intc>; +- +- chosen { +- bootargs = "console=ttySC2,38400"; +- stdout-path = &sci2; +- }; +- aliases { +- serial0 = &sci0; +- serial1 = &sci1; +- serial2 = &sci2; +- }; +- +- xclk: oscillator { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <33333333>; +- clock-output-names = "xtal"; +- }; +- pllclk: pllclk { +- compatible = "renesas,h8s2678-pll-clock"; +- clocks = <&xclk>; +- #clock-cells = <0>; +- reg = <0xffff3b 1>, <0xffff45 1>; +- }; +- core_clk: core_clk { +- compatible = "renesas,h8300-div-clock"; +- clocks = <&pllclk>; +- #clock-cells = <0>; +- reg = <0xffff3b 1>; +- renesas,width = <3>; +- }; +- fclk: fclk { +- compatible = "fixed-factor-clock"; +- clocks = <&core_clk>; +- #clock-cells = <0>; +- clock-div = <1>; +- clock-mult = <1>; +- }; +- +- memory@400000 { +- device_type = "memory"; +- reg = <0x400000 0x800000>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- compatible = "renesas,h8300"; +- clock-frequency = <33333333>; +- }; +- }; +- +- h8intc: interrupt-controller@fffe00 { +- compatible = "renesas,h8s-intc", "renesas,h8300-intc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0xfffe00 24>; +- }; +- +- bsc: memory-controller@fffec0 { +- compatible = "renesas,h8s-bsc", "renesas,h8300-bsc"; +- reg = <0xfffec0 24>; +- }; +- +- tpu: timer@ffffe0 { +- compatible = "renesas,tpu"; +- reg = <0xffffe0 16>, <0xfffff0 12>; +- clocks = <&fclk>; +- clock-names = "fck"; +- }; +- +- timer8: timer@ffffb0 { +- compatible = "renesas,8bit-timer"; +- reg = <0xffffb0 10>; +- interrupts = <72 0>; +- clocks = <&fclk>; +- clock-names = "fck"; +- }; +- +- sci0: serial@ffff78 { +- compatible = "renesas,sci"; +- reg = <0xffff78 8>; +- interrupts = <88 0>, <89 0>, <90 0>, <91 0>; +- clocks = <&fclk>; +- clock-names = "fck"; +- }; +- sci1: serial@ffff80 { +- compatible = "renesas,sci"; +- reg = <0xffff80 8>; +- interrupts = <92 0>, <93 0>, <94 0>, <95 0>; +- clocks = <&fclk>; +- clock-names = "fck"; +- }; +- sci2: serial@ffff88 { +- compatible = "renesas,sci"; +- reg = <0xffff88 8>; +- interrupts = <96 0>, <97 0>, <98 0>, <99 0>; +- clocks = <&fclk>; +- clock-names = "fck"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/h8300/h8300h_sim.dts b/scripts/dtc/include-prefixes/h8300/h8300h_sim.dts +deleted file mode 100644 +index 595398b9d018..000000000000 +--- a/scripts/dtc/include-prefixes/h8300/h8300h_sim.dts ++++ /dev/null +@@ -1,97 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-/ { +- compatible = "gnu,gdbsim"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&h8intc>; +- +- chosen { +- bootargs = "earlyprintk=h8300-sim"; +- stdout-path = <&sci0>; +- }; +- aliases { +- serial0 = &sci0; +- serial1 = &sci1; +- }; +- +- xclk: oscillator { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <20000000>; +- clock-output-names = "xtal"; +- }; +- core_clk: core_clk { +- compatible = "renesas,h8300-div-clock"; +- clocks = <&xclk>; +- #clock-cells = <0>; +- reg = <0xfee01b 2>; +- renesas,width = <2>; +- }; +- fclk: fclk { +- compatible = "fixed-factor-clock"; +- clocks = <&core_clk>; +- #clock-cells = <0>; +- clock-div = <1>; +- clock-mult = <1>; +- }; +- +- memory@400000 { +- device_type = "memory"; +- reg = <0x400000 0x400000>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- compatible = "renesas,h8300"; +- clock-frequency = <20000000>; +- }; +- }; +- +- h8intc: interrupt-controller@fee012 { +- compatible = "renesas,h8300h-intc", "renesas,h8300-intc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0xfee012 7>; +- }; +- +- bsc: memory-controller@fee01e { +- compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc"; +- reg = <0xfee01e 8>; +- }; +- +- timer8: timer@ffff80 { +- compatible = "renesas,8bit-timer"; +- reg = <0xffff80 10>; +- interrupts = <36 0>; +- clocks = <&fclk>; +- clock-names = "fck"; +- }; +- +- timer16: timer@ffff68 { +- compatible = "renesas,16bit-timer"; +- reg = <0xffff68 8>, <0xffff60 8>; +- interrupts = <26 0>; +- renesas,channel = <0>; +- clocks = <&fclk>; +- clock-names = "fck"; +- }; +- +- sci0: serial@ffffb0 { +- compatible = "renesas,sci"; +- reg = <0xffffb0 8>; +- interrupts = <52 0>, <53 0>, <54 0>, <55 0>; +- clocks = <&fclk>; +- clock-names = "fck"; +- }; +- +- sci1: serial@ffffb8 { +- compatible = "renesas,sci"; +- reg = <0xffffb8 8>; +- interrupts = <56 0>, <57 0>, <58 0>, <59 0>; +- clocks = <&fclk>; +- clock-names = "fck"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/h8300/h8s_sim.dts b/scripts/dtc/include-prefixes/h8300/h8s_sim.dts +deleted file mode 100644 +index 932cc3c5a81b..000000000000 +--- a/scripts/dtc/include-prefixes/h8300/h8s_sim.dts ++++ /dev/null +@@ -1,100 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-/ { +- compatible = "gnu,gdbsim"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&h8intc>; +- +- chosen { +- bootargs = "earlyprintk=h8300-sim"; +- stdout-path = <&sci0>; +- }; +- aliases { +- serial0 = &sci0; +- serial1 = &sci1; +- }; +- +- xclk: oscillator { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <33333333>; +- clock-output-names = "xtal"; +- }; +- pllclk: pllclk { +- compatible = "renesas,h8s2678-pll-clock"; +- clocks = <&xclk>; +- #clock-cells = <0>; +- reg = <0xfee03b 2>, <0xfee045 2>; +- }; +- core_clk: core_clk { +- compatible = "renesas,h8300-div-clock"; +- clocks = <&pllclk>; +- #clock-cells = <0>; +- reg = <0xfee03b 2>; +- renesas,width = <3>; +- }; +- fclk: fclk { +- compatible = "fixed-factor-clock"; +- clocks = <&core_clk>; +- #clock-cells = <0>; +- clock-div = <1>; +- clock-mult = <1>; +- }; +- +- memory@400000 { +- device_type = "memory"; +- reg = <0x400000 0x800000>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- compatible = "renesas,h8300"; +- clock-frequency = <33333333>; +- }; +- }; +- +- h8intc: interrupt-controller@fffe00 { +- compatible = "renesas,h8s-intc", "renesas,h8300-intc"; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0xfffe00 24>; +- }; +- +- bsc: memory-controller@fffec0 { +- compatible = "renesas,h8s-bsc", "renesas,h8300-bsc"; +- reg = <0xfffec0 24>; +- }; +- +- tpu: timer@ffffe0 { +- compatible = "renesas,tpu"; +- reg = <0xffffe0 16>, <0xfffff0 12>; +- clocks = <&fclk>; +- clock-names = "fck"; +- }; +- +- timer8: timer@ffffb0 { +- compatible = "renesas,8bit-timer"; +- reg = <0xffffb0 10>; +- interrupts = <72 0>; +- clocks = <&fclk>; +- clock-names = "fck"; +- }; +- +- sci0: serial@ffff78 { +- compatible = "renesas,sci"; +- reg = <0xffff78 8>; +- interrupts = <88 0>, <89 0>, <90 0>, <91 0>; +- clocks = <&fclk>; +- clock-names = "fck"; +- }; +- sci1: serial@ffff80 { +- compatible = "renesas,sci"; +- reg = <0xffff80 8>; +- interrupts = <92 0>, <93 0>, <94 0>, <95 0>; +- clocks = <&fclk>; +- clock-names = "fck"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/microblaze b/scripts/dtc/include-prefixes/microblaze +new file mode 120000 +index 000000000000..d9830330a21d +--- /dev/null ++++ b/scripts/dtc/include-prefixes/microblaze +@@ -0,0 +1 @@ ++../../../arch/microblaze/boot/dts +\ No newline at end of file +diff --git a/scripts/dtc/include-prefixes/microblaze/Makefile b/scripts/dtc/include-prefixes/microblaze/Makefile +deleted file mode 100644 +index ef00dd30d19a..000000000000 +--- a/scripts/dtc/include-prefixes/microblaze/Makefile ++++ /dev/null +@@ -1,20 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-# +- +-dtb-y := system.dtb +- +-ifneq ($(DTB),) +-obj-y += linked_dtb.o +- +-# Ensure system.dtb exists +-$(obj)/linked_dtb.o: $(obj)/system.dtb +- +-# Generate system.dtb from $(DTB).dtb +-ifneq ($(DTB),system) +-$(obj)/system.dtb: $(obj)/$(DTB).dtb +- $(call if_changed,shipped) +-endif +-endif +- +-# Rule to build device tree blobs +-DTC_FLAGS := -p 1024 +diff --git a/scripts/dtc/include-prefixes/microblaze/linked_dtb.S b/scripts/dtc/include-prefixes/microblaze/linked_dtb.S +deleted file mode 100644 +index 23345af3721f..000000000000 +--- a/scripts/dtc/include-prefixes/microblaze/linked_dtb.S ++++ /dev/null +@@ -1,2 +0,0 @@ +-.section __fdt_blob,"a" +-.incbin "arch/microblaze/boot/dts/system.dtb" +diff --git a/scripts/dtc/include-prefixes/microblaze/system.dts b/scripts/dtc/include-prefixes/microblaze/system.dts +deleted file mode 100644 +index b7ee1056779e..000000000000 +--- a/scripts/dtc/include-prefixes/microblaze/system.dts ++++ /dev/null +@@ -1,358 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Device Tree Generator version: 1.1 +- * +- * (C) Copyright 2007-2008 Xilinx, Inc. +- * (C) Copyright 2007-2009 Michal Simek +- * +- * Michal SIMEK +- * +- * CAUTION: This file is automatically generated by libgen. +- * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6 +- * +- * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101 +- */ +- +-/dts-v1/; +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "xlnx,microblaze"; +- model = "testing"; +- DDR2_SDRAM: memory@90000000 { +- device_type = "memory"; +- reg = < 0x90000000 0x10000000 >; +- } ; +- aliases { +- ethernet0 = &Hard_Ethernet_MAC; +- serial0 = &RS232_Uart_1; +- } ; +- chosen { +- bootargs = "console=ttyUL0,115200 highres=on"; +- stdout-path = "/plb@0/serial@84000000"; +- } ; +- cpus { +- #address-cells = <1>; +- #cpus = <0x1>; +- #size-cells = <0>; +- microblaze_0: cpu@0 { +- clock-frequency = <125000000>; +- compatible = "xlnx,microblaze-7.10.d"; +- d-cache-baseaddr = <0x90000000>; +- d-cache-highaddr = <0x9fffffff>; +- d-cache-line-size = <0x10>; +- d-cache-size = <0x2000>; +- device_type = "cpu"; +- i-cache-baseaddr = <0x90000000>; +- i-cache-highaddr = <0x9fffffff>; +- i-cache-line-size = <0x10>; +- i-cache-size = <0x2000>; +- model = "microblaze,7.10.d"; +- reg = <0>; +- timebase-frequency = <125000000>; +- xlnx,addr-tag-bits = <0xf>; +- xlnx,allow-dcache-wr = <0x1>; +- xlnx,allow-icache-wr = <0x1>; +- xlnx,area-optimized = <0x0>; +- xlnx,cache-byte-size = <0x2000>; +- xlnx,d-lmb = <0x1>; +- xlnx,d-opb = <0x0>; +- xlnx,d-plb = <0x1>; +- xlnx,data-size = <0x20>; +- xlnx,dcache-addr-tag = <0xf>; +- xlnx,dcache-always-used = <0x1>; +- xlnx,dcache-byte-size = <0x2000>; +- xlnx,dcache-line-len = <0x4>; +- xlnx,dcache-use-fsl = <0x1>; +- xlnx,debug-enabled = <0x1>; +- xlnx,div-zero-exception = <0x1>; +- xlnx,dopb-bus-exception = <0x0>; +- xlnx,dynamic-bus-sizing = <0x1>; +- xlnx,edge-is-positive = <0x1>; +- xlnx,family = "virtex5"; +- xlnx,endianness = <0x1>; +- xlnx,fpu-exception = <0x1>; +- xlnx,fsl-data-size = <0x20>; +- xlnx,fsl-exception = <0x0>; +- xlnx,fsl-links = <0x0>; +- xlnx,i-lmb = <0x1>; +- xlnx,i-opb = <0x0>; +- xlnx,i-plb = <0x1>; +- xlnx,icache-always-used = <0x1>; +- xlnx,icache-line-len = <0x4>; +- xlnx,icache-use-fsl = <0x1>; +- xlnx,ill-opcode-exception = <0x1>; +- xlnx,instance = "microblaze_0"; +- xlnx,interconnect = <0x1>; +- xlnx,interrupt-is-edge = <0x0>; +- xlnx,iopb-bus-exception = <0x0>; +- xlnx,mmu-dtlb-size = <0x4>; +- xlnx,mmu-itlb-size = <0x2>; +- xlnx,mmu-tlb-access = <0x3>; +- xlnx,mmu-zones = <0x10>; +- xlnx,number-of-pc-brk = <0x1>; +- xlnx,number-of-rd-addr-brk = <0x0>; +- xlnx,number-of-wr-addr-brk = <0x0>; +- xlnx,opcode-0x0-illegal = <0x1>; +- xlnx,pvr = <0x2>; +- xlnx,pvr-user1 = <0x0>; +- xlnx,pvr-user2 = <0x0>; +- xlnx,reset-msr = <0x0>; +- xlnx,sco = <0x0>; +- xlnx,unaligned-exceptions = <0x1>; +- xlnx,use-barrel = <0x1>; +- xlnx,use-dcache = <0x1>; +- xlnx,use-div = <0x1>; +- xlnx,use-ext-brk = <0x1>; +- xlnx,use-ext-nm-brk = <0x1>; +- xlnx,use-extended-fsl-instr = <0x0>; +- xlnx,use-fpu = <0x2>; +- xlnx,use-hw-mul = <0x2>; +- xlnx,use-icache = <0x1>; +- xlnx,use-interrupt = <0x1>; +- xlnx,use-mmu = <0x3>; +- xlnx,use-msr-instr = <0x1>; +- xlnx,use-pcmp-instr = <0x1>; +- } ; +- } ; +- mb_plb: plb@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus"; +- ranges ; +- FLASH: flash@a0000000 { +- bank-width = <2>; +- compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash"; +- reg = < 0xa0000000 0x2000000 >; +- xlnx,family = "virtex5"; +- xlnx,include-datawidth-matching-0 = <0x1>; +- xlnx,include-datawidth-matching-1 = <0x0>; +- xlnx,include-datawidth-matching-2 = <0x0>; +- xlnx,include-datawidth-matching-3 = <0x0>; +- xlnx,include-negedge-ioregs = <0x0>; +- xlnx,include-plb-ipif = <0x1>; +- xlnx,include-wrbuf = <0x1>; +- xlnx,max-mem-width = <0x10>; +- xlnx,mch-native-dwidth = <0x20>; +- xlnx,mch-plb-clk-period-ps = <0x1f40>; +- xlnx,mch-splb-awidth = <0x20>; +- xlnx,mch0-accessbuf-depth = <0x10>; +- xlnx,mch0-protocol = <0x0>; +- xlnx,mch0-rddatabuf-depth = <0x10>; +- xlnx,mch1-accessbuf-depth = <0x10>; +- xlnx,mch1-protocol = <0x0>; +- xlnx,mch1-rddatabuf-depth = <0x10>; +- xlnx,mch2-accessbuf-depth = <0x10>; +- xlnx,mch2-protocol = <0x0>; +- xlnx,mch2-rddatabuf-depth = <0x10>; +- xlnx,mch3-accessbuf-depth = <0x10>; +- xlnx,mch3-protocol = <0x0>; +- xlnx,mch3-rddatabuf-depth = <0x10>; +- xlnx,mem0-width = <0x10>; +- xlnx,mem1-width = <0x20>; +- xlnx,mem2-width = <0x20>; +- xlnx,mem3-width = <0x20>; +- xlnx,num-banks-mem = <0x1>; +- xlnx,num-channels = <0x0>; +- xlnx,priority-mode = <0x0>; +- xlnx,synch-mem-0 = <0x0>; +- xlnx,synch-mem-1 = <0x0>; +- xlnx,synch-mem-2 = <0x0>; +- xlnx,synch-mem-3 = <0x0>; +- xlnx,synch-pipedelay-0 = <0x2>; +- xlnx,synch-pipedelay-1 = <0x2>; +- xlnx,synch-pipedelay-2 = <0x2>; +- xlnx,synch-pipedelay-3 = <0x2>; +- xlnx,tavdv-ps-mem-0 = <0x1adb0>; +- xlnx,tavdv-ps-mem-1 = <0x3a98>; +- xlnx,tavdv-ps-mem-2 = <0x3a98>; +- xlnx,tavdv-ps-mem-3 = <0x3a98>; +- xlnx,tcedv-ps-mem-0 = <0x1adb0>; +- xlnx,tcedv-ps-mem-1 = <0x3a98>; +- xlnx,tcedv-ps-mem-2 = <0x3a98>; +- xlnx,tcedv-ps-mem-3 = <0x3a98>; +- xlnx,thzce-ps-mem-0 = <0x88b8>; +- xlnx,thzce-ps-mem-1 = <0x1b58>; +- xlnx,thzce-ps-mem-2 = <0x1b58>; +- xlnx,thzce-ps-mem-3 = <0x1b58>; +- xlnx,thzoe-ps-mem-0 = <0x1b58>; +- xlnx,thzoe-ps-mem-1 = <0x1b58>; +- xlnx,thzoe-ps-mem-2 = <0x1b58>; +- xlnx,thzoe-ps-mem-3 = <0x1b58>; +- xlnx,tlzwe-ps-mem-0 = <0x88b8>; +- xlnx,tlzwe-ps-mem-1 = <0x0>; +- xlnx,tlzwe-ps-mem-2 = <0x0>; +- xlnx,tlzwe-ps-mem-3 = <0x0>; +- xlnx,twc-ps-mem-0 = <0x2af8>; +- xlnx,twc-ps-mem-1 = <0x3a98>; +- xlnx,twc-ps-mem-2 = <0x3a98>; +- xlnx,twc-ps-mem-3 = <0x3a98>; +- xlnx,twp-ps-mem-0 = <0x11170>; +- xlnx,twp-ps-mem-1 = <0x2ee0>; +- xlnx,twp-ps-mem-2 = <0x2ee0>; +- xlnx,twp-ps-mem-3 = <0x2ee0>; +- xlnx,xcl0-linesize = <0x4>; +- xlnx,xcl0-writexfer = <0x1>; +- xlnx,xcl1-linesize = <0x4>; +- xlnx,xcl1-writexfer = <0x1>; +- xlnx,xcl2-linesize = <0x4>; +- xlnx,xcl2-writexfer = <0x1>; +- xlnx,xcl3-linesize = <0x4>; +- xlnx,xcl3-writexfer = <0x1>; +- } ; +- Hard_Ethernet_MAC: xps-ll-temac@81c00000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "xlnx,compound"; +- ranges ; +- ethernet@81c00000 { +- compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a"; +- interrupt-parent = <&xps_intc_0>; +- interrupts = < 5 2 >; +- llink-connected = <&PIM3>; +- local-mac-address = [ 00 0a 35 00 00 00 ]; +- reg = < 0x81c00000 0x40 >; +- xlnx,bus2core-clk-ratio = <0x1>; +- xlnx,phy-type = <0x1>; +- xlnx,phyaddr = <0x1>; +- xlnx,rxcsum = <0x0>; +- xlnx,rxfifo = <0x1000>; +- xlnx,temac-type = <0x0>; +- xlnx,txcsum = <0x0>; +- xlnx,txfifo = <0x1000>; +- } ; +- } ; +- IIC_EEPROM: i2c@81600000 { +- compatible = "xlnx,xps-iic-2.00.a"; +- interrupt-parent = <&xps_intc_0>; +- interrupts = < 6 2 >; +- reg = < 0x81600000 0x10000 >; +- xlnx,clk-freq = <0x7735940>; +- xlnx,family = "virtex5"; +- xlnx,gpo-width = <0x1>; +- xlnx,iic-freq = <0x186a0>; +- xlnx,scl-inertial-delay = <0x0>; +- xlnx,sda-inertial-delay = <0x0>; +- xlnx,ten-bit-adr = <0x0>; +- } ; +- LEDs_8Bit: gpio@81400000 { +- compatible = "xlnx,xps-gpio-1.00.a"; +- interrupt-parent = <&xps_intc_0>; +- interrupts = < 7 2 >; +- reg = < 0x81400000 0x10000 >; +- xlnx,all-inputs = <0x0>; +- xlnx,all-inputs-2 = <0x0>; +- xlnx,dout-default = <0x0>; +- xlnx,dout-default-2 = <0x0>; +- xlnx,family = "virtex5"; +- xlnx,gpio-width = <0x8>; +- xlnx,interrupt-present = <0x1>; +- xlnx,is-bidir = <0x1>; +- xlnx,is-bidir-2 = <0x1>; +- xlnx,is-dual = <0x0>; +- xlnx,tri-default = <0xffffffff>; +- xlnx,tri-default-2 = <0xffffffff>; +- #gpio-cells = <2>; +- gpio-controller; +- } ; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- heartbeat { +- label = "Heartbeat"; +- gpios = <&LEDs_8Bit 4 1>; +- linux,default-trigger = "heartbeat"; +- }; +- +- yellow { +- label = "Yellow"; +- gpios = <&LEDs_8Bit 5 1>; +- }; +- +- red { +- label = "Red"; +- gpios = <&LEDs_8Bit 6 1>; +- }; +- +- green { +- label = "Green"; +- gpios = <&LEDs_8Bit 7 1>; +- }; +- } ; +- +- gpio-restart { +- compatible = "gpio-restart"; +- /* +- * FIXME: is this active low or active high? +- * the current flag (1) indicates active low. +- * delay measures are templates, should be adjusted +- * to datasheet or trial-and-error with real hardware. +- */ +- gpios = <&LEDs_8Bit 2 1>; +- active-delay = <100>; +- inactive-delay = <10>; +- wait-delay = <100>; +- }; +- +- RS232_Uart_1: serial@84000000 { +- clock-frequency = <125000000>; +- compatible = "xlnx,xps-uartlite-1.00.a"; +- current-speed = <115200>; +- device_type = "serial"; +- interrupt-parent = <&xps_intc_0>; +- interrupts = < 8 0 >; +- port-number = <0>; +- reg = < 0x84000000 0x10000 >; +- xlnx,baudrate = <0x1c200>; +- xlnx,data-bits = <0x8>; +- xlnx,family = "virtex5"; +- xlnx,odd-parity = <0x0>; +- xlnx,use-parity = <0x0>; +- } ; +- debug_module: debug@84400000 { +- compatible = "xlnx,mdm-1.00.d"; +- reg = < 0x84400000 0x10000 >; +- xlnx,family = "virtex5"; +- xlnx,interconnect = <0x1>; +- xlnx,jtag-chain = <0x2>; +- xlnx,mb-dbg-ports = <0x1>; +- xlnx,uart-width = <0x8>; +- xlnx,use-uart = <0x1>; +- xlnx,write-fsl-ports = <0x0>; +- } ; +- mpmc@90000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "xlnx,mpmc-4.02.a"; +- ranges ; +- PIM3: sdma@84600180 { +- compatible = "xlnx,ll-dma-1.00.a"; +- interrupt-parent = <&xps_intc_0>; +- interrupts = < 2 2 1 2 >; +- reg = < 0x84600180 0x80 >; +- } ; +- } ; +- xps_intc_0: interrupt-controller@81800000 { +- #interrupt-cells = <0x2>; +- compatible = "xlnx,xps-intc-1.00.a"; +- interrupt-controller ; +- reg = < 0x81800000 0x10000 >; +- xlnx,kind-of-intr = <0x100>; +- xlnx,num-intr-inputs = <0x9>; +- } ; +- xps_timer_1: timer@83c00000 { +- compatible = "xlnx,xps-timer-1.00.a"; +- interrupt-parent = <&xps_intc_0>; +- interrupts = < 3 2 >; +- reg = < 0x83c00000 0x10000 >; +- xlnx,count-width = <0x20>; +- xlnx,family = "virtex5"; +- xlnx,gen0-assert = <0x1>; +- xlnx,gen1-assert = <0x1>; +- xlnx,one-timer-only = <0x0>; +- xlnx,trig0-assert = <0x1>; +- xlnx,trig1-assert = <0x1>; +- } ; +- } ; +-} ; +diff --git a/scripts/dtc/include-prefixes/mips b/scripts/dtc/include-prefixes/mips +new file mode 120000 +index 000000000000..ae8d4948dc8d +--- /dev/null ++++ b/scripts/dtc/include-prefixes/mips +@@ -0,0 +1 @@ ++../../../arch/mips/boot/dts +\ No newline at end of file +diff --git a/scripts/dtc/include-prefixes/mips/Makefile b/scripts/dtc/include-prefixes/mips/Makefile +deleted file mode 100644 +index be96d35eb582..000000000000 +--- a/scripts/dtc/include-prefixes/mips/Makefile ++++ /dev/null +@@ -1,20 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-subdir-$(CONFIG_BMIPS_GENERIC) += brcm +-subdir-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon +-subdir-$(CONFIG_FIT_IMAGE_FDT_MARDUK) += img +-subdir-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += img +-subdir-$(CONFIG_MACH_INGENIC) += ingenic +-subdir-$(CONFIG_LANTIQ) += lantiq +-subdir-$(CONFIG_MACH_LOONGSON64) += loongson +-subdir-$(CONFIG_SOC_VCOREIII) += mscc +-subdir-$(CONFIG_MIPS_MALTA) += mti +-subdir-$(CONFIG_LEGACY_BOARD_SEAD3) += mti +-subdir-$(CONFIG_NLM_XLP_BOARD) += netlogic +-subdir-$(CONFIG_FIT_IMAGE_FDT_NI169445) += ni +-subdir-$(CONFIG_MACH_PIC32) += pic32 +-subdir-$(CONFIG_ATH79) += qca +-subdir-$(CONFIG_RALINK) += ralink +-subdir-$(CONFIG_MACH_REALTEK_RTL) += realtek +-subdir-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += xilfpga +- +-obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) +diff --git a/scripts/dtc/include-prefixes/mips/brcm/Makefile b/scripts/dtc/include-prefixes/mips/brcm/Makefile +deleted file mode 100644 +index d85f446cc0ce..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/Makefile ++++ /dev/null +@@ -1,37 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_DT_BCM93384WVG) += bcm93384wvg.dtb +-dtb-$(CONFIG_DT_BCM93384WVG_VIPER) += bcm93384wvg_viper.dtb +-dtb-$(CONFIG_DT_BCM96368MVWG) += bcm96368mvwg.dtb +-dtb-$(CONFIG_DT_BCM9EJTAGPRB) += bcm9ejtagprb.dtb +-dtb-$(CONFIG_DT_BCM97125CBMB) += bcm97125cbmb.dtb +-dtb-$(CONFIG_DT_BCM97346DBSMB) += bcm97346dbsmb.dtb +-dtb-$(CONFIG_DT_BCM97358SVMB) += bcm97358svmb.dtb +-dtb-$(CONFIG_DT_BCM97360SVMB) += bcm97360svmb.dtb +-dtb-$(CONFIG_DT_BCM97362SVMB) += bcm97362svmb.dtb +-dtb-$(CONFIG_DT_BCM97420C) += bcm97420c.dtb +-dtb-$(CONFIG_DT_BCM97425SVMB) += bcm97425svmb.dtb +-dtb-$(CONFIG_DT_BCM97435SVMB) += bcm97435svmb.dtb +-dtb-$(CONFIG_DT_COMTREND_VR3032U) += bcm63268-comtrend-vr-3032u.dtb +-dtb-$(CONFIG_DT_NETGEAR_CVG834G) += bcm3368-netgear-cvg834g.dtb +-dtb-$(CONFIG_DT_SFR_NEUFBOX4_SERCOMM) += bcm6358-neufbox4-sercomm.dtb +-dtb-$(CONFIG_DT_SFR_NEUFBOX6_SERCOMM) += bcm6362-neufbox6-sercomm.dtb +- +-dtb-$(CONFIG_DT_NONE) += \ +- bcm3368-netgear-cvg834g.dtb \ +- bcm6358-neufbox4-sercomm.dtb \ +- bcm6362-neufbox6-sercomm.dtb \ +- bcm63268-comtrend-vr-3032u.dtb \ +- bcm93384wvg.dtb \ +- bcm93384wvg_viper.dtb \ +- bcm96368mvwg.dtb \ +- bcm9ejtagprb.dtb \ +- bcm97125cbmb.dtb \ +- bcm97346dbsmb.dtb \ +- bcm97358svmb.dtb \ +- bcm97360svmb.dtb \ +- bcm97362svmb.dtb \ +- bcm97420c.dtb \ +- bcm97425svmb.dtb \ +- bcm97435svmb.dtb +- +-obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm3368-netgear-cvg834g.dts b/scripts/dtc/include-prefixes/mips/brcm/bcm3368-netgear-cvg834g.dts +deleted file mode 100644 +index d702a843c74a..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm3368-netgear-cvg834g.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "bcm3368.dtsi" +- +-/ { +- compatible = "netgear,cvg834g", "brcm,bcm3368"; +- model = "NETGEAR CVG834G"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x02000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm3368.dtsi b/scripts/dtc/include-prefixes/mips/brcm/bcm3368.dtsi +deleted file mode 100644 +index 883ca8bed8e7..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm3368.dtsi ++++ /dev/null +@@ -1,113 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include "dt-bindings/clock/bcm3368-clock.h" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "brcm,bcm3368"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mips-hpt-frequency = <150000000>; +- +- cpu@0 { +- compatible = "brcm,bmips4350"; +- device_type = "cpu"; +- reg = <0>; +- }; +- +- cpu@1 { +- compatible = "brcm,bmips4350"; +- device_type = "cpu"; +- reg = <1>; +- }; +- }; +- +- clocks { +- periph_clk: periph-clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- }; +- }; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- cpu_intc: interrupt-controller { +- #address-cells = <0>; +- compatible = "mti,cpu-interrupt-controller"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- ubus { +- #address-cells = <1>; +- #size-cells = <1>; +- +- compatible = "simple-bus"; +- ranges; +- +- clkctl: clock-controller@fff8c004 { +- compatible = "brcm,bcm3368-clocks"; +- reg = <0xfff8c004 0x4>; +- #clock-cells = <1>; +- }; +- +- periph_cntl: syscon@fff8c008 { +- compatible = "syscon"; +- reg = <0xfff8c008 0x4>; +- native-endian; +- }; +- +- reboot: syscon-reboot@fff8c008 { +- compatible = "syscon-reboot"; +- regmap = <&periph_cntl>; +- offset = <0x0>; +- mask = <0x1>; +- }; +- +- periph_intc: interrupt-controller@fff8c00c { +- compatible = "brcm,bcm6345-l1-intc"; +- reg = <0xfff8c00c 0x8>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpu_intc>; +- interrupts = <2>; +- }; +- +- uart0: serial@fff8c100 { +- compatible = "brcm,bcm6345-uart"; +- reg = <0xfff8c100 0x18>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <2>; +- +- clocks = <&periph_clk>; +- clock-names = "refclk"; +- +- status = "disabled"; +- }; +- +- uart1: serial@fff8c120 { +- compatible = "brcm,bcm6345-uart"; +- reg = <0xfff8c120 0x18>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <3>; +- +- clocks = <&periph_clk>; +- clock-names = "refclk"; +- +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm3384_viper.dtsi b/scripts/dtc/include-prefixes/mips/brcm/bcm3384_viper.dtsi +deleted file mode 100644 +index eb2a9c6ed604..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm3384_viper.dtsi ++++ /dev/null +@@ -1,109 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "brcm,bcm3384-viper", "brcm,bcm33843-viper"; +- +- memory@0 { +- device_type = "memory"; +- +- /* Typical ranges. The bootloader should fill these in. */ +- reg = <0x06000000 0x02000000>, +- <0x0e000000 0x02000000>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* 1/2 of the CPU core clock (standard MIPS behavior) */ +- mips-hpt-frequency = <300000000>; +- +- cpu@0 { +- compatible = "brcm,bmips4350"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- cpu_intc: cpu_intc { +- #address-cells = <0>; +- compatible = "mti,cpu-interrupt-controller"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- clocks { +- periph_clk: periph_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <54000000>; +- }; +- }; +- +- aliases { +- uart0 = &uart0; +- }; +- +- ubus { +- #address-cells = <1>; +- #size-cells = <1>; +- +- compatible = "brcm,ubus", "simple-bus"; +- ranges; +- /* No dma-ranges on Viper. */ +- +- periph_intc: periph_intc@14e00048 { +- compatible = "brcm,bcm3380-l2-intc"; +- reg = <0x14e00048 0x4 0x14e0004c 0x4>, +- <0x14e00350 0x4 0x14e00354 0x4>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpu_intc>; +- interrupts = <4>; +- }; +- +- cmips_intc: cmips_intc@151f8048 { +- compatible = "brcm,bcm3380-l2-intc"; +- reg = <0x151f8048 0x4 0x151f804c 0x4>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <30>; +- brcm,int-map-mask = <0xffffffff>; +- }; +- +- uart0: serial@14e00520 { +- compatible = "brcm,bcm6345-uart"; +- reg = <0x14e00520 0x18>; +- interrupt-parent = <&periph_intc>; +- interrupts = <2>; +- clocks = <&periph_clk>; +- status = "disabled"; +- }; +- +- ehci0: usb@15400300 { +- compatible = "brcm,bcm3384-ehci", "generic-ehci"; +- reg = <0x15400300 0x100>; +- big-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <41>; +- status = "disabled"; +- }; +- +- ohci0: usb@15400400 { +- compatible = "brcm,bcm3384-ohci", "generic-ohci"; +- reg = <0x15400400 0x100>; +- big-endian; +- no-big-frame-no; +- interrupt-parent = <&periph_intc>; +- interrupts = <40>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm3384_zephyr.dtsi b/scripts/dtc/include-prefixes/mips/brcm/bcm3384_zephyr.dtsi +deleted file mode 100644 +index d7ad769a42fc..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm3384_zephyr.dtsi ++++ /dev/null +@@ -1,127 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "brcm,bcm3384", "brcm,bcm33843"; +- +- memory@0 { +- device_type = "memory"; +- +- /* Typical range. The bootloader should fill this in. */ +- reg = <0x0 0x08000000>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* On BMIPS5000 this is 1/8th of the CPU core clock */ +- mips-hpt-frequency = <100000000>; +- +- cpu@0 { +- compatible = "brcm,bmips5000"; +- device_type = "cpu"; +- reg = <0>; +- }; +- +- cpu@1 { +- compatible = "brcm,bmips5000"; +- device_type = "cpu"; +- reg = <1>; +- }; +- }; +- +- cpu_intc: cpu_intc { +- #address-cells = <0>; +- compatible = "mti,cpu-interrupt-controller"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- clocks { +- periph_clk: periph_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <54000000>; +- }; +- }; +- +- aliases { +- uart0 = &uart0; +- }; +- +- ubus { +- #address-cells = <1>; +- #size-cells = <1>; +- +- compatible = "brcm,ubus", "simple-bus"; +- ranges; +- dma-ranges = <0x00000000 0x08000000 0x08000000>, +- <0x08000000 0x00000000 0x08000000>; +- +- periph_intc: periph_intc@14e00038 { +- compatible = "brcm,bcm3380-l2-intc"; +- reg = <0x14e00038 0x4 0x14e0003c 0x4>, +- <0x14e00340 0x4 0x14e00344 0x4>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpu_intc>; +- interrupts = <4>; +- }; +- +- zmips_intc: zmips_intc@104b0060 { +- compatible = "brcm,bcm3380-l2-intc"; +- reg = <0x104b0060 0x4 0x104b0064 0x4>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <29>; +- brcm,int-map-mask = <0xffffffff>; +- }; +- +- iop_intc: iop_intc@14e00058 { +- compatible = "brcm,bcm3380-l2-intc"; +- reg = <0x14e00058 0x4 0x14e0005c 0x4>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpu_intc>; +- interrupts = <6>; +- brcm,int-map-mask = <0xffffffff>; +- }; +- +- uart0: serial@14e00520 { +- compatible = "brcm,bcm6345-uart"; +- reg = <0x14e00520 0x18>; +- interrupt-parent = <&periph_intc>; +- interrupts = <2>; +- clocks = <&periph_clk>; +- status = "disabled"; +- }; +- +- ehci0: usb@15400300 { +- compatible = "brcm,bcm3384-ehci", "generic-ehci"; +- reg = <0x15400300 0x100>; +- big-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <41>; +- status = "disabled"; +- }; +- +- ohci0: usb@15400400 { +- compatible = "brcm,bcm3384-ohci", "generic-ohci"; +- reg = <0x15400400 0x100>; +- big-endian; +- no-big-frame-no; +- interrupt-parent = <&periph_intc>; +- interrupts = <40>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm63268-comtrend-vr-3032u.dts b/scripts/dtc/include-prefixes/mips/brcm/bcm63268-comtrend-vr-3032u.dts +deleted file mode 100644 +index b511bc7125d5..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm63268-comtrend-vr-3032u.dts ++++ /dev/null +@@ -1,109 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "bcm63268.dtsi" +- +-/ { +- compatible = "comtrend,vr-3032u", "brcm,bcm63268"; +- model = "Comtrend VR-3032u"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x04000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +-}; +- +-&leds0 { +- status = "okay"; +- brcm,serial-leds; +- brcm,serial-dat-low; +- brcm,serial-shift-inv; +- +- led@0 { +- reg = <0>; +- brcm,hardware-controlled; +- brcm,link-signal-sources = <0>; +- /* GPHY0 Speed 0 */ +- }; +- led@1 { +- reg = <1>; +- brcm,hardware-controlled; +- brcm,link-signal-sources = <1>; +- /* GPHY0 Speed 1 */ +- }; +- led@2 { +- reg = <2>; +- active-low; +- label = "vr-3032u:red:inet"; +- }; +- led@3 { +- reg = <3>; +- active-low; +- label = "vr-3032u:green:dsl"; +- }; +- led@4 { +- reg = <4>; +- active-low; +- label = "vr-3032u:green:usb"; +- }; +- led@7 { +- reg = <7>; +- active-low; +- label = "vr-3032u:green:wps"; +- }; +- led@8 { +- reg = <8>; +- active-low; +- label = "vr-3032u:green:inet"; +- }; +- led@9 { +- reg = <9>; +- brcm,hardware-controlled; +- /* EPHY0 Activity */ +- }; +- led@10 { +- reg = <10>; +- brcm,hardware-controlled; +- /* EPHY1 Activity */ +- }; +- led@11 { +- reg = <11>; +- brcm,hardware-controlled; +- /* EPHY2 Activity */ +- }; +- led@12 { +- reg = <12>; +- brcm,hardware-controlled; +- /* GPHY0 Activity */ +- }; +- led@13 { +- reg = <13>; +- brcm,hardware-controlled; +- /* EPHY0 Speed */ +- }; +- led@14 { +- reg = <14>; +- brcm,hardware-controlled; +- /* EPHY1 Speed */ +- }; +- led@15 { +- reg = <15>; +- brcm,hardware-controlled; +- /* EPHY2 Speed */ +- }; +- led@20 { +- reg = <20>; +- active-low; +- label = "vr-3032u:green:power"; +- default-state = "on"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm63268.dtsi b/scripts/dtc/include-prefixes/mips/brcm/bcm63268.dtsi +deleted file mode 100644 +index c3ce49ec675f..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm63268.dtsi ++++ /dev/null +@@ -1,262 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include "dt-bindings/clock/bcm63268-clock.h" +-#include "dt-bindings/reset/bcm63268-reset.h" +-#include "dt-bindings/soc/bcm63268-pm.h" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "brcm,bcm63268"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mips-hpt-frequency = <200000000>; +- +- cpu@0 { +- compatible = "brcm,bmips4350"; +- device_type = "cpu"; +- reg = <0>; +- }; +- +- cpu@1 { +- compatible = "brcm,bmips4350"; +- device_type = "cpu"; +- reg = <1>; +- }; +- }; +- +- clocks { +- periph_osc: periph-osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- clock-output-names = "periph"; +- }; +- +- hsspi_osc: hsspi-osc { +- compatible = "fixed-clock"; +- +- #clock-cells = <0>; +- +- clock-frequency = <400000000>; +- clock-output-names = "hsspi_osc"; +- }; +- }; +- +- aliases { +- nflash = &nflash; +- serial0 = &uart0; +- serial1 = &uart1; +- spi0 = &lsspi; +- spi1 = &hsspi; +- }; +- +- cpu_intc: interrupt-controller { +- #address-cells = <0>; +- compatible = "mti,cpu-interrupt-controller"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- ubus { +- #address-cells = <1>; +- #size-cells = <1>; +- +- compatible = "simple-bus"; +- ranges; +- +- periph_clk: clock-controller@10000004 { +- compatible = "brcm,bcm63268-clocks"; +- reg = <0x10000004 0x4>; +- #clock-cells = <1>; +- }; +- +- pll_cntl: syscon@10000008 { +- compatible = "syscon"; +- reg = <0x10000008 0x4>; +- native-endian; +- +- reboot { +- compatible = "syscon-reboot"; +- offset = <0x0>; +- mask = <0x1>; +- }; +- }; +- +- periph_rst: reset-controller@10000010 { +- compatible = "brcm,bcm6345-reset"; +- reg = <0x10000010 0x4>; +- #reset-cells = <1>; +- }; +- +- periph_intc: interrupt-controller@10000020 { +- compatible = "brcm,bcm6345-l1-intc"; +- reg = <0x10000020 0x20>, +- <0x10000040 0x20>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpu_intc>; +- interrupts = <2>, <3>; +- }; +- +- wdt: watchdog@1000009c { +- compatible = "brcm,bcm7038-wdt"; +- reg = <0x1000009c 0xc>; +- +- clocks = <&periph_osc>; +- clock-names = "refclk"; +- +- timeout-sec = <30>; +- }; +- +- uart0: serial@10000180 { +- compatible = "brcm,bcm6345-uart"; +- reg = <0x10000180 0x18>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <5>; +- +- clocks = <&periph_osc>; +- clock-names = "refclk"; +- +- status = "disabled"; +- }; +- +- nflash: nand@10000200 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,nand-bcm6368", +- "brcm,brcmnand-v4.0", +- "brcm,brcmnand"; +- reg = <0x10000200 0x180>, +- <0x10000600 0x200>, +- <0x100000b0 0x10>; +- reg-names = "nand", +- "nand-cache", +- "nand-int-base"; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <50>; +- +- clocks = <&periph_clk BCM63268_CLK_NAND>; +- clock-names = "nand"; +- +- status = "disabled"; +- }; +- +- uart1: serial@100001a0 { +- compatible = "brcm,bcm6345-uart"; +- reg = <0x100001a0 0x18>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <34>; +- +- clocks = <&periph_osc>; +- clock-names = "refclk"; +- +- status = "disabled"; +- }; +- +- lsspi: spi@10000800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,bcm6358-spi"; +- reg = <0x10000800 0x70c>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <80>; +- +- clocks = <&periph_clk BCM63268_CLK_SPI>; +- clock-names = "spi"; +- +- resets = <&periph_rst BCM63268_RST_SPI>; +- +- status = "disabled"; +- }; +- +- hsspi: spi@10001000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,bcm6328-hsspi"; +- reg = <0x10001000 0x600>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <6>; +- +- clocks = <&periph_clk BCM63268_CLK_HSSPI>, +- <&hsspi_osc>; +- clock-names = "hsspi", +- "pll"; +- +- resets = <&periph_rst BCM63268_RST_SPI>; +- +- status = "disabled"; +- }; +- +- periph_pwr: power-controller@1000184c { +- compatible = "brcm,bcm6328-power-controller"; +- reg = <0x1000184c 0x4>; +- #power-domain-cells = <1>; +- }; +- +- leds0: led-controller@10001900 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,bcm6328-leds"; +- reg = <0x10001900 0x24>; +- +- status = "disabled"; +- }; +- +- ehci: usb@10002500 { +- compatible = "brcm,bcm63268-ehci", "generic-ehci"; +- reg = <0x10002500 0x100>; +- big-endian; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <10>; +- +- phys = <&usbh 0>; +- phy-names = "usb"; +- +- status = "disabled"; +- }; +- +- ohci: usb@10002600 { +- compatible = "brcm,bcm63268-ohci", "generic-ohci"; +- reg = <0x10002600 0x100>; +- big-endian; +- no-big-frame-no; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <9>; +- +- phys = <&usbh 0>; +- phy-names = "usb"; +- +- status = "disabled"; +- }; +- +- usbh: usb-phy@10002700 { +- compatible = "brcm,bcm63268-usbh-phy"; +- reg = <0x10002700 0x38>; +- #phy-cells = <1>; +- +- clocks = <&periph_clk BCM63268_CLK_USBH>; +- clock-names = "usbh"; +- +- power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_USBH>; +- +- resets = <&periph_rst BCM63268_RST_USBH>; +- reset-names = "usbh"; +- +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm6328.dtsi b/scripts/dtc/include-prefixes/mips/brcm/bcm6328.dtsi +deleted file mode 100644 +index 634618d4377e..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm6328.dtsi ++++ /dev/null +@@ -1,240 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include "dt-bindings/clock/bcm6328-clock.h" +-#include "dt-bindings/reset/bcm6328-reset.h" +-#include "dt-bindings/soc/bcm6328-pm.h" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "brcm,bcm6328"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mips-hpt-frequency = <160000000>; +- +- cpu@0 { +- compatible = "brcm,bmips4350"; +- device_type = "cpu"; +- reg = <0>; +- }; +- +- cpu@1 { +- compatible = "brcm,bmips4350"; +- device_type = "cpu"; +- reg = <1>; +- }; +- }; +- +- clocks { +- periph_osc: periph-osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- clock-output-names = "periph"; +- }; +- +- hsspi_osc: hsspi-osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <133333333>; +- clock-output-names = "hsspi_osc"; +- }; +- }; +- +- aliases { +- nflash = &nflash; +- serial0 = &uart0; +- serial1 = &uart1; +- spi1 = &hsspi; +- }; +- +- cpu_intc: interrupt-controller { +- #address-cells = <0>; +- compatible = "mti,cpu-interrupt-controller"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- ubus { +- #address-cells = <1>; +- #size-cells = <1>; +- +- compatible = "simple-bus"; +- ranges; +- +- periph_clk: clock-controller@10000004 { +- compatible = "brcm,bcm6328-clocks"; +- reg = <0x10000004 0x4>; +- #clock-cells = <1>; +- }; +- +- periph_rst: reset-controller@10000010 { +- compatible = "brcm,bcm6345-reset"; +- reg = <0x10000010 0x4>; +- #reset-cells = <1>; +- }; +- +- periph_intc: interrupt-controller@10000020 { +- compatible = "brcm,bcm6345-l1-intc"; +- reg = <0x10000020 0x10>, +- <0x10000030 0x10>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpu_intc>; +- interrupts = <2>, <3>; +- }; +- +- wdt: watchdog@1000005c { +- compatible = "brcm,bcm7038-wdt"; +- reg = <0x1000005c 0xc>; +- +- clocks = <&periph_osc>; +- clock-names = "refclk"; +- +- timeout-sec = <30>; +- }; +- +- soft_reset: syscon@10000068 { +- compatible = "syscon"; +- reg = <0x10000068 0x4>; +- native-endian; +- +- reboot { +- compatible = "syscon-reboot"; +- offset = <0x0>; +- mask = <0x1>; +- }; +- }; +- +- uart0: serial@10000100 { +- compatible = "brcm,bcm6345-uart"; +- reg = <0x10000100 0x18>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <28>; +- +- clocks = <&periph_osc>; +- clock-names = "refclk"; +- +- status = "disabled"; +- }; +- +- uart1: serial@10000120 { +- compatible = "brcm,bcm6345-uart"; +- reg = <0x10000120 0x18>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <39>; +- +- clocks = <&periph_osc>; +- clock-names = "refclk"; +- +- status = "disabled"; +- }; +- +- nflash: nand@10000200 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,nand-bcm6368", +- "brcm,brcmnand-v2.2", +- "brcm,brcmnand"; +- reg = <0x10000200 0x180>, +- <0x10000400 0x200>, +- <0x10000070 0x10>; +- reg-names = "nand", +- "nand-cache", +- "nand-int-base"; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <0>; +- +- status = "disabled"; +- }; +- +- leds0: led-controller@10000800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,bcm6328-leds"; +- reg = <0x10000800 0x24>; +- +- status = "disabled"; +- }; +- +- hsspi: spi@10001000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,bcm6328-hsspi"; +- reg = <0x10001000 0x600>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <29>; +- +- clocks = <&periph_clk BCM6328_CLK_HSSPI>, +- <&hsspi_osc>; +- clock-names = "hsspi", +- "pll"; +- +- resets = <&periph_rst BCM6328_RST_SPI>; +- reset-names = "hsspi"; +- +- status = "disabled"; +- }; +- +- periph_pwr: power-controller@10001848 { +- compatible = "brcm,bcm6328-power-controller"; +- reg = <0x10001848 0x4>; +- #power-domain-cells = <1>; +- }; +- +- ehci: usb@10002500 { +- compatible = "brcm,bcm6328-ehci", "generic-ehci"; +- reg = <0x10002500 0x100>; +- big-endian; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <42>; +- +- phys = <&usbh 0>; +- phy-names = "usb"; +- +- status = "disabled"; +- }; +- +- ohci: usb@10002600 { +- compatible = "brcm,bcm6328-ohci", "generic-ohci"; +- reg = <0x10002600 0x100>; +- big-endian; +- no-big-frame-no; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <41>; +- +- phys = <&usbh 0>; +- phy-names = "usb"; +- +- status = "disabled"; +- }; +- +- usbh: usb-phy@10002700 { +- compatible = "brcm,bcm6328-usbh-phy"; +- reg = <0x10002700 0x38>; +- #phy-cells = <1>; +- +- clocks = <&periph_clk BCM6328_CLK_USBH>; +- clock-names = "usbh"; +- +- power-domains = <&periph_pwr BCM6328_POWER_DOMAIN_USBH>; +- +- resets = <&periph_rst BCM6328_RST_USBH>; +- reset-names = "usbh"; +- +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm6358-neufbox4-sercomm.dts b/scripts/dtc/include-prefixes/mips/brcm/bcm6358-neufbox4-sercomm.dts +deleted file mode 100644 +index c646690ee3df..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm6358-neufbox4-sercomm.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "bcm6358.dtsi" +- +-/ { +- compatible = "sfr,nb4-ser", "brcm,bcm6358"; +- model = "SFR Neufbox 4 (Sercomm)"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x02000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +-}; +- +-&leds0 { +- status = "okay"; +- +- led@0 { +- reg = <0>; +- active-low; +- label = "nb4-ser:white:alarm"; +- }; +- led@2 { +- reg = <2>; +- active-low; +- label = "nb4-ser:white:tv"; +- }; +- led@3 { +- reg = <3>; +- active-low; +- label = "nb4-ser:white:tel"; +- }; +- led@4 { +- reg = <4>; +- active-low; +- label = "nb4-ser:white:adsl"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm6358.dtsi b/scripts/dtc/include-prefixes/mips/brcm/bcm6358.dtsi +deleted file mode 100644 +index 777c4379ed03..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm6358.dtsi ++++ /dev/null +@@ -1,210 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include "dt-bindings/clock/bcm6358-clock.h" +-#include "dt-bindings/reset/bcm6358-reset.h" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "brcm,bcm6358"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mips-hpt-frequency = <150000000>; +- +- cpu@0 { +- compatible = "brcm,bmips4350"; +- device_type = "cpu"; +- reg = <0>; +- }; +- +- cpu@1 { +- compatible = "brcm,bmips4350"; +- device_type = "cpu"; +- reg = <1>; +- }; +- }; +- +- clocks { +- periph_osc: periph-osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- clock-output-names = "periph"; +- }; +- }; +- +- aliases { +- pflash = &pflash; +- serial0 = &uart0; +- serial1 = &uart1; +- spi0 = &lsspi; +- }; +- +- cpu_intc: interrupt-controller { +- #address-cells = <0>; +- compatible = "mti,cpu-interrupt-controller"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- ubus { +- #address-cells = <1>; +- #size-cells = <1>; +- +- compatible = "simple-bus"; +- ranges; +- +- periph_clk: clock-controller@fffe0004 { +- compatible = "brcm,bcm6358-clocks"; +- reg = <0xfffe0004 0x4>; +- #clock-cells = <1>; +- }; +- +- pll_cntl: syscon@fffe0008 { +- compatible = "syscon"; +- reg = <0xfffe0008 0x4>; +- native-endian; +- +- reboot { +- compatible = "syscon-reboot"; +- offset = <0x0>; +- mask = <0x1>; +- }; +- }; +- +- periph_intc: interrupt-controller@fffe000c { +- compatible = "brcm,bcm6345-l1-intc"; +- reg = <0xfffe000c 0x8>, +- <0xfffe0038 0x8>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpu_intc>; +- interrupts = <2>, <3>; +- }; +- +- periph_rst: reset-controller@fffe0034 { +- compatible = "brcm,bcm6345-reset"; +- reg = <0xfffe0034 0x4>; +- #reset-cells = <1>; +- }; +- +- wdt: watchdog@fffe005c { +- compatible = "brcm,bcm7038-wdt"; +- reg = <0xfffe005c 0xc>; +- +- clocks = <&periph_osc>; +- clock-names = "refclk"; +- +- timeout-sec = <30>; +- }; +- +- leds0: led-controller@fffe00d0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,bcm6358-leds"; +- reg = <0xfffe00d0 0x8>; +- +- status = "disabled"; +- }; +- +- uart0: serial@fffe0100 { +- compatible = "brcm,bcm6345-uart"; +- reg = <0xfffe0100 0x18>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <2>; +- +- clocks = <&periph_osc>; +- clock-names = "refclk"; +- +- status = "disabled"; +- }; +- +- uart1: serial@fffe0120 { +- compatible = "brcm,bcm6345-uart"; +- reg = <0xfffe0120 0x18>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <3>; +- +- clocks = <&periph_osc>; +- clock-names = "refclk"; +- +- status = "disabled"; +- }; +- +- lsspi: spi@fffe0800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,bcm6358-spi"; +- reg = <0xfffe0800 0x70c>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <1>; +- +- clocks = <&periph_clk BCM6358_CLK_SPI>; +- clock-names = "spi"; +- +- resets = <&periph_rst BCM6358_RST_SPI>; +- reset-names = "spi"; +- +- status = "disabled"; +- }; +- +- ehci: usb@fffe1300 { +- compatible = "brcm,bcm6358-ehci", "generic-ehci"; +- reg = <0xfffe1300 0x100>; +- big-endian; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <10>; +- +- phys = <&usbh 0>; +- phy-names = "usb"; +- +- status = "disabled"; +- }; +- +- ohci: usb@fffe1400 { +- compatible = "brcm,bcm6358-ohci", "generic-ohci"; +- reg = <0xfffe1400 0x100>; +- big-endian; +- no-big-frame-no; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <5>; +- +- phys = <&usbh 0>; +- phy-names = "usb"; +- +- status = "disabled"; +- }; +- +- usbh: usb-phy@fffe1500 { +- compatible = "brcm,bcm6358-usbh-phy"; +- reg = <0xfffe1500 0x38>; +- #phy-cells = <1>; +- +- resets = <&periph_rst BCM6358_RST_USBH>; +- reset-names = "usbh"; +- +- status = "disabled"; +- }; +- }; +- +- pflash: nor@1e000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x1e000000 0x2000000>; +- bank-width = <2>; +- +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm6362-neufbox6-sercomm.dts b/scripts/dtc/include-prefixes/mips/brcm/bcm6362-neufbox6-sercomm.dts +deleted file mode 100644 +index f83d95ca0514..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm6362-neufbox6-sercomm.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "bcm6362.dtsi" +- +-/ { +- compatible = "sfr,nb6-ser", "brcm,bcm6362"; +- model = "SFR NeufBox 6 (Sercomm)"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm6362.dtsi b/scripts/dtc/include-prefixes/mips/brcm/bcm6362.dtsi +deleted file mode 100644 +index d74021925c53..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm6362.dtsi ++++ /dev/null +@@ -1,265 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include "dt-bindings/clock/bcm6362-clock.h" +-#include "dt-bindings/reset/bcm6362-reset.h" +-#include "dt-bindings/soc/bcm6362-pm.h" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "brcm,bcm6362"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mips-hpt-frequency = <200000000>; +- +- cpu@0 { +- compatible = "brcm,bmips4350"; +- device_type = "cpu"; +- reg = <0>; +- }; +- +- cpu@1 { +- compatible = "brcm,bmips4350"; +- device_type = "cpu"; +- reg = <1>; +- }; +- }; +- +- clocks { +- periph_osc: periph-osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- clock-output-names = "periph"; +- }; +- +- hsspi_osc: hsspi-osc { +- compatible = "fixed-clock"; +- +- #clock-cells = <0>; +- +- clock-frequency = <400000000>; +- clock-output-names = "hsspi_osc"; +- }; +- }; +- +- aliases { +- nflash = &nflash; +- serial0 = &uart0; +- serial1 = &uart1; +- spi0 = &lsspi; +- spi1 = &hsspi; +- }; +- +- cpu_intc: interrupt-controller { +- #address-cells = <0>; +- compatible = "mti,cpu-interrupt-controller"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- ubus { +- #address-cells = <1>; +- #size-cells = <1>; +- +- compatible = "simple-bus"; +- ranges; +- +- periph_clk: clock-controller@10000004 { +- compatible = "brcm,bcm6362-clocks"; +- reg = <0x10000004 0x4>; +- #clock-cells = <1>; +- }; +- +- pll_cntl: syscon@10000008 { +- compatible = "syscon"; +- reg = <0x10000008 0x4>; +- native-endian; +- +- reboot { +- compatible = "syscon-reboot"; +- offset = <0x0>; +- mask = <0x1>; +- }; +- }; +- +- periph_rst: reset-controller@10000010 { +- compatible = "brcm,bcm6345-reset"; +- reg = <0x10000010 0x4>; +- #reset-cells = <1>; +- }; +- +- periph_intc: interrupt-controller@10000020 { +- compatible = "brcm,bcm6345-l1-intc"; +- reg = <0x10000020 0x10>, +- <0x10000030 0x10>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpu_intc>; +- interrupts = <2>, <3>; +- }; +- +- wdt: watchdog@1000005c { +- compatible = "brcm,bcm7038-wdt"; +- reg = <0x1000005c 0xc>; +- +- clocks = <&periph_osc>; +- clock-names = "refclk"; +- +- timeout-sec = <30>; +- }; +- +- uart0: serial@10000100 { +- compatible = "brcm,bcm6345-uart"; +- reg = <0x10000100 0x18>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <3>; +- +- clocks = <&periph_osc>; +- clock-names = "refclk"; +- +- status = "disabled"; +- }; +- +- uart1: serial@10000120 { +- compatible = "brcm,bcm6345-uart"; +- reg = <0x10000120 0x18>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <4>; +- +- clocks = <&periph_osc>; +- clock-names = "refclk"; +- +- status = "disabled"; +- }; +- +- nflash: nand@10000200 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,nand-bcm6368", +- "brcm,brcmnand-v2.2", +- "brcm,brcmnand"; +- reg = <0x10000200 0x180>, +- <0x10000600 0x200>, +- <0x10000070 0x10>; +- reg-names = "nand", +- "nand-cache", +- "nand-int-base"; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <12>; +- +- clocks = <&periph_clk BCM6362_CLK_NAND>; +- clock-names = "nand"; +- +- status = "disabled"; +- }; +- +- lsspi: spi@10000800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,bcm6358-spi"; +- reg = <0x10000800 0x70c>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <2>; +- +- clocks = <&periph_clk BCM6362_CLK_SPI>; +- clock-names = "spi"; +- +- resets = <&periph_rst BCM6362_RST_SPI>; +- reset-names = "spi"; +- +- status = "disabled"; +- }; +- +- hsspi: spi@10001000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,bcm6328-hsspi"; +- reg = <0x10001000 0x600>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <5>; +- +- clocks = <&periph_clk BCM6362_CLK_HSSPI>, +- <&hsspi_osc>; +- clock-names = "hsspi", +- "pll"; +- +- resets = <&periph_rst BCM6362_RST_SPI>; +- reset-names = "hsspi"; +- +- status = "disabled"; +- }; +- +- periph_pwr: power-controller@10001848 { +- compatible = "brcm,bcm6362-power-controller"; +- reg = <0x10001848 0x4>; +- #power-domain-cells = <1>; +- }; +- +- leds0: led-controller@10001900 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,bcm6328-leds"; +- reg = <0x10001900 0x24>; +- +- status = "disabled"; +- }; +- +- ehci: usb@10002500 { +- compatible = "brcm,bcm6362-ehci", "generic-ehci"; +- reg = <0x10002500 0x100>; +- big-endian; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <10>; +- +- phys = <&usbh 0>; +- phy-names = "usb"; +- +- status = "disabled"; +- }; +- +- ohci: usb@10002600 { +- compatible = "brcm,bcm6362-ohci", "generic-ohci"; +- reg = <0x10002600 0x100>; +- big-endian; +- no-big-frame-no; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <9>; +- +- phys = <&usbh 0>; +- phy-names = "usb"; +- +- status = "disabled"; +- }; +- +- usbh: usb-phy@10002700 { +- compatible = "brcm,bcm6362-usbh-phy"; +- reg = <0x10002700 0x38>; +- +- #phy-cells = <1>; +- +- clocks = <&periph_clk BCM6362_CLK_USBH>; +- clock-names = "usbh"; +- +- power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_USBH>; +- +- resets = <&periph_rst BCM6362_RST_USBH>; +- reset-names = "usbh"; +- +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm6368.dtsi b/scripts/dtc/include-prefixes/mips/brcm/bcm6368.dtsi +deleted file mode 100644 +index fc15e200877d..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm6368.dtsi ++++ /dev/null +@@ -1,247 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include "dt-bindings/clock/bcm6368-clock.h" +-#include "dt-bindings/reset/bcm6368-reset.h" +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "brcm,bcm6368"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mips-hpt-frequency = <200000000>; +- +- cpu@0 { +- compatible = "brcm,bmips4350"; +- device_type = "cpu"; +- reg = <0>; +- }; +- +- cpu@1 { +- compatible = "brcm,bmips4350"; +- device_type = "cpu"; +- reg = <1>; +- }; +- }; +- +- clocks { +- periph_osc: periph-osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- clock-output-names = "periph"; +- }; +- }; +- +- aliases { +- nflash = &nflash; +- pflash = &pflash; +- serial0 = &uart0; +- serial1 = &uart1; +- spi0 = &lsspi; +- }; +- +- cpu_intc: interrupt-controller { +- #address-cells = <0>; +- compatible = "mti,cpu-interrupt-controller"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- ubus { +- #address-cells = <1>; +- #size-cells = <1>; +- +- compatible = "simple-bus"; +- ranges; +- +- periph_clk: clock-controller@10000004 { +- compatible = "brcm,bcm6368-clocks"; +- reg = <0x10000004 0x4>; +- #clock-cells = <1>; +- }; +- +- pll_cntl: syscon@100000008 { +- compatible = "syscon"; +- reg = <0x10000008 0x4>; +- native-endian; +- +- reboot { +- compatible = "syscon-reboot"; +- offset = <0x0>; +- mask = <0x1>; +- }; +- }; +- +- periph_rst: reset-controller@10000010 { +- compatible = "brcm,bcm6345-reset"; +- reg = <0x10000010 0x4>; +- #reset-cells = <1>; +- }; +- +- periph_intc: interrupt-controller@10000020 { +- compatible = "brcm,bcm6345-l1-intc"; +- reg = <0x10000020 0x10>, +- <0x10000030 0x10>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpu_intc>; +- interrupts = <2>, <3>; +- }; +- +- wdt: watchdog@1000005c { +- compatible = "brcm,bcm7038-wdt"; +- reg = <0x1000005c 0xc>; +- +- clocks = <&periph_osc>; +- clock-names = "refclk"; +- +- timeout-sec = <30>; +- }; +- +- leds0: led-controller@100000d0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,bcm6358-leds"; +- reg = <0x100000d0 0x8>; +- +- status = "disabled"; +- }; +- +- uart0: serial@10000100 { +- compatible = "brcm,bcm6345-uart"; +- reg = <0x10000100 0x18>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <2>; +- +- clocks = <&periph_osc>; +- clock-names = "refclk"; +- +- status = "disabled"; +- }; +- +- uart1: serial@10000120 { +- compatible = "brcm,bcm6345-uart"; +- reg = <0x10000120 0x18>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <3>; +- +- clocks = <&periph_osc>; +- clock-names = "refclk"; +- +- status = "disabled"; +- }; +- +- nflash: nand@10000200 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,nand-bcm6368", +- "brcm,brcmnand-v2.1", +- "brcm,brcmnand"; +- reg = <0x10000200 0x180>, +- <0x10000600 0x200>, +- <0x10000070 0x10>; +- reg-names = "nand", +- "nand-cache", +- "nand-int-base"; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <10>; +- +- clocks = <&periph_clk BCM6368_CLK_NAND>; +- clock-names = "nand"; +- +- status = "disabled"; +- }; +- +- lsspi: spi@10000800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,bcm6358-spi"; +- reg = <0x10000800 0x70c>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <1>; +- +- clocks = <&periph_clk BCM6368_CLK_SPI>; +- clock-names = "spi"; +- +- resets = <&periph_rst BCM6368_RST_SPI>; +- reset-names = "spi"; +- +- status = "disabled"; +- }; +- +- ehci: usb@10001500 { +- compatible = "brcm,bcm6368-ehci", "generic-ehci"; +- reg = <0x10001500 0x100>; +- big-endian; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <7>; +- +- phys = <&usbh 0>; +- phy-names = "usb"; +- +- status = "disabled"; +- }; +- +- ohci: usb@10001600 { +- compatible = "brcm,bcm6368-ohci", "generic-ohci"; +- reg = <0x10001600 0x100>; +- big-endian; +- no-big-frame-no; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <5>; +- +- phys = <&usbh 0>; +- phy-names = "usb"; +- +- status = "disabled"; +- }; +- +- usbh: usb-phy@10001700 { +- compatible = "brcm,bcm6368-usbh-phy"; +- reg = <0x10001700 0x38>; +- #phy-cells = <1>; +- +- clocks = <&periph_clk BCM6368_CLK_USBH>; +- clock-names = "usbh"; +- +- resets = <&periph_rst BCM6368_RST_USBH>; +- reset-names = "usbh"; +- +- status = "disabled"; +- }; +- +- random: rng@10004180 { +- compatible = "brcm,bcm6368-rng"; +- reg = <0x10004180 0x14>; +- +- clocks = <&periph_clk BCM6368_CLK_IPSEC>; +- clock-names = "ipsec"; +- +- resets = <&periph_rst BCM6368_RST_IPSEC>; +- reset-names = "ipsec"; +- }; +- }; +- +- pflash: nor@18000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x18000000 0x2000000>; +- bank-width = <2>; +- +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm7125.dtsi b/scripts/dtc/include-prefixes/mips/brcm/bcm7125.dtsi +deleted file mode 100644 +index 5bf77b6fcceb..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm7125.dtsi ++++ /dev/null +@@ -1,281 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "brcm,bcm7125"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mips-hpt-frequency = <202500000>; +- +- cpu@0 { +- compatible = "brcm,bmips4380"; +- device_type = "cpu"; +- reg = <0>; +- }; +- +- cpu@1 { +- compatible = "brcm,bmips4380"; +- device_type = "cpu"; +- reg = <1>; +- }; +- }; +- +- aliases { +- uart0 = &uart0; +- }; +- +- cpu_intc: interrupt-controller { +- #address-cells = <0>; +- compatible = "mti,cpu-interrupt-controller"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- clocks { +- uart_clk: uart_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <81000000>; +- }; +- +- upg_clk: upg_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- }; +- }; +- +- rdb { +- #address-cells = <1>; +- #size-cells = <1>; +- +- compatible = "simple-bus"; +- ranges = <0 0x10000000 0x01000000>; +- +- periph_intc: interrupt-controller@441400 { +- compatible = "brcm,bcm7038-l1-intc"; +- reg = <0x441400 0x30>, <0x441600 0x30>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpu_intc>; +- interrupts = <2>, <3>; +- }; +- +- sun_l2_intc: interrupt-controller@401800 { +- compatible = "brcm,l2-intc"; +- reg = <0x401800 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <23>; +- }; +- +- gisb-arb@400000 { +- compatible = "brcm,bcm7400-gisb-arb"; +- reg = <0x400000 0xdc>; +- native-endian; +- interrupt-parent = <&sun_l2_intc>; +- interrupts = <0>, <2>; +- brcm,gisb-arb-master-mask = <0x2f7>; +- brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0", +- "bsp_0", "rdc_0", "rptd_0", +- "avd_0", "jtag_0"; +- }; +- +- upg_irq0_intc: interrupt-controller@406780 { +- compatible = "brcm,bcm7120-l2-intc"; +- reg = <0x406780 0x8>; +- +- brcm,int-map-mask = <0x44>, <0xf000000>, <0x100000>; +- brcm,int-fwd-mask = <0x70000>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <18>, <19>, <20>; +- interrupt-names = "upg_main", "upg_bsc", "upg_spi"; +- }; +- +- sun_top_ctrl: syscon@404000 { +- compatible = "brcm,bcm7125-sun-top-ctrl", "syscon"; +- reg = <0x404000 0x60c>; +- native-endian; +- }; +- +- reboot { +- compatible = "brcm,bcm7038-reboot"; +- syscon = <&sun_top_ctrl 0x8 0x14>; +- }; +- +- uart0: serial@406b00 { +- compatible = "ns16550a"; +- reg = <0x406b00 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <21>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart1: serial@406b40 { +- compatible = "ns16550a"; +- reg = <0x406b40 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <64>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart2: serial@406b80 { +- compatible = "ns16550a"; +- reg = <0x406b80 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <65>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- bsca: i2c@406200 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406200 0x58>; +- interrupts = <24>; +- interrupt-names = "upg_bsca"; +- status = "disabled"; +- }; +- +- bscb: i2c@406280 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406280 0x58>; +- interrupts = <25>; +- interrupt-names = "upg_bscb"; +- status = "disabled"; +- }; +- +- bscc: i2c@406300 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406300 0x58>; +- interrupts = <26>; +- interrupt-names = "upg_bscc"; +- status = "disabled"; +- }; +- +- bscd: i2c@406380 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406380 0x58>; +- interrupts = <27>; +- interrupt-names = "upg_bscd"; +- status = "disabled"; +- }; +- +- pwma: pwm@406580 { +- compatible = "brcm,bcm7038-pwm"; +- reg = <0x406580 0x28>; +- #pwm-cells = <2>; +- clocks = <&upg_clk>; +- status = "disabled"; +- }; +- +- watchdog: watchdog@4067e8 { +- clocks = <&upg_clk>; +- compatible = "brcm,bcm7038-wdt"; +- reg = <0x4067e8 0x14>; +- status = "disabled"; +- }; +- +- upg_gio: gpio@406700 { +- compatible = "brcm,brcmstb-gpio"; +- reg = <0x406700 0x80>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupt-parent = <&upg_irq0_intc>; +- interrupts = <6>; +- brcm,gpio-bank-widths = <32 32 32 18>; +- }; +- +- ehci0: usb@488300 { +- compatible = "brcm,bcm7125-ehci", "generic-ehci"; +- reg = <0x488300 0x100>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <60>; +- status = "disabled"; +- }; +- +- ohci0: usb@488400 { +- compatible = "brcm,bcm7125-ohci", "generic-ohci"; +- reg = <0x488400 0x100>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <61>; +- status = "disabled"; +- }; +- +- spi_l2_intc: interrupt-controller@411d00 { +- compatible = "brcm,l2-intc"; +- reg = <0x411d00 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <79>; +- }; +- +- qspi: spi@443000 { +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- compatible = "brcm,spi-bcm-qspi", +- "brcm,spi-brcmstb-qspi"; +- clocks = <&upg_clk>; +- reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>; +- reg-names = "cs_reg", "hif_mspi", "bspi"; +- interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>; +- interrupt-parent = <&spi_l2_intc>; +- interrupt-names = "spi_lr_fullness_reached", +- "spi_lr_session_aborted", +- "spi_lr_impatient", +- "spi_lr_session_done", +- "spi_lr_overread", +- "mspi_done", +- "mspi_halted"; +- status = "disabled"; +- }; +- +- mspi: spi@406400 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,spi-bcm-qspi", +- "brcm,spi-brcmstb-mspi"; +- clocks = <&upg_clk>; +- reg = <0x406400 0x180>; +- reg-names = "mspi"; +- interrupts = <0x14>; +- interrupt-parent = <&upg_irq0_intc>; +- interrupt-names = "mspi_done"; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm7346.dtsi b/scripts/dtc/include-prefixes/mips/brcm/bcm7346.dtsi +deleted file mode 100644 +index 2afa0dada575..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm7346.dtsi ++++ /dev/null +@@ -1,549 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "brcm,bcm7346"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mips-hpt-frequency = <163125000>; +- +- cpu@0 { +- compatible = "brcm,bmips5000"; +- device_type = "cpu"; +- reg = <0>; +- }; +- +- cpu@1 { +- compatible = "brcm,bmips5000"; +- device_type = "cpu"; +- reg = <1>; +- }; +- }; +- +- aliases { +- uart0 = &uart0; +- }; +- +- cpu_intc: interrupt-controller { +- #address-cells = <0>; +- compatible = "mti,cpu-interrupt-controller"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- clocks { +- uart_clk: uart_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <81000000>; +- }; +- +- upg_clk: upg_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- }; +- }; +- +- rdb { +- #address-cells = <1>; +- #size-cells = <1>; +- +- compatible = "simple-bus"; +- ranges = <0 0x10000000 0x01000000>; +- +- periph_intc: interrupt-controller@411400 { +- compatible = "brcm,bcm7038-l1-intc"; +- reg = <0x411400 0x30>, <0x411600 0x30>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpu_intc>; +- interrupts = <2>, <3>; +- }; +- +- sun_l2_intc: interrupt-controller@403000 { +- compatible = "brcm,l2-intc"; +- reg = <0x403000 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <51>; +- }; +- +- gisb-arb@400000 { +- compatible = "brcm,bcm7400-gisb-arb"; +- reg = <0x400000 0xdc>; +- native-endian; +- interrupt-parent = <&sun_l2_intc>; +- interrupts = <0>, <2>; +- brcm,gisb-arb-master-mask = <0x673>; +- brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0", +- "rdc_0", "raaga_0", +- "jtag_0", "svd_0"; +- }; +- +- upg_irq0_intc: interrupt-controller@406780 { +- compatible = "brcm,bcm7120-l2-intc"; +- reg = <0x406780 0x8>; +- +- brcm,int-map-mask = <0x44>, <0xf000000>; +- brcm,int-fwd-mask = <0x70000>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <59>, <57>; +- interrupt-names = "upg_main", "upg_bsc"; +- }; +- +- upg_aon_irq0_intc: interrupt-controller@408b80 { +- compatible = "brcm,bcm7120-l2-intc"; +- reg = <0x408b80 0x8>; +- +- brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>; +- brcm,int-fwd-mask = <0>; +- brcm,irq-can-wake; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <60>, <58>, <62>; +- interrupt-names = "upg_main_aon", "upg_bsc_aon", +- "upg_spi"; +- }; +- +- sun_top_ctrl: syscon@404000 { +- compatible = "brcm,bcm7346-sun-top-ctrl", "syscon"; +- reg = <0x404000 0x51c>; +- native-endian; +- }; +- +- reboot { +- compatible = "brcm,brcmstb-reboot"; +- syscon = <&sun_top_ctrl 0x304 0x308>; +- }; +- +- uart0: serial@406900 { +- compatible = "ns16550a"; +- reg = <0x406900 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <64>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart1: serial@406940 { +- compatible = "ns16550a"; +- reg = <0x406940 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <65>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart2: serial@406980 { +- compatible = "ns16550a"; +- reg = <0x406980 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <66>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- bsca: i2c@406200 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406200 0x58>; +- interrupts = <24>; +- interrupt-names = "upg_bsca"; +- status = "disabled"; +- }; +- +- bscb: i2c@406280 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406280 0x58>; +- interrupts = <25>; +- interrupt-names = "upg_bscb"; +- status = "disabled"; +- }; +- +- bscc: i2c@406300 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406300 0x58>; +- interrupts = <26>; +- interrupt-names = "upg_bscc"; +- status = "disabled"; +- }; +- +- bscd: i2c@406380 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406380 0x58>; +- interrupts = <27>; +- interrupt-names = "upg_bscd"; +- status = "disabled"; +- }; +- +- bsce: i2c@408980 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_aon_irq0_intc>; +- reg = <0x408980 0x58>; +- interrupts = <27>; +- interrupt-names = "upg_bsce"; +- status = "disabled"; +- }; +- +- pwma: pwm@406580 { +- compatible = "brcm,bcm7038-pwm"; +- reg = <0x406580 0x28>; +- #pwm-cells = <2>; +- clocks = <&upg_clk>; +- status = "disabled"; +- }; +- +- pwmb: pwm@406800 { +- compatible = "brcm,bcm7038-pwm"; +- reg = <0x406800 0x28>; +- #pwm-cells = <2>; +- clocks = <&upg_clk>; +- status = "disabled"; +- }; +- +- watchdog: watchdog@4067e8 { +- clocks = <&upg_clk>; +- compatible = "brcm,bcm7038-wdt"; +- reg = <0x4067e8 0x14>; +- status = "disabled"; +- }; +- +- aon_pm_l2_intc: interrupt-controller@408440 { +- compatible = "brcm,l2-intc"; +- reg = <0x408440 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <53>; +- brcm,irq-can-wake; +- }; +- +- aon_ctrl: syscon@408000 { +- compatible = "brcm,brcmstb-aon-ctrl"; +- reg = <0x408000 0x100>, <0x408200 0x200>; +- reg-names = "aon-ctrl", "aon-sram"; +- }; +- +- timers: timer@4067c0 { +- compatible = "brcm,brcmstb-timers"; +- reg = <0x4067c0 0x40>; +- }; +- +- upg_gio: gpio@406700 { +- compatible = "brcm,brcmstb-gpio"; +- reg = <0x406700 0x60>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupt-parent = <&upg_irq0_intc>; +- interrupts = <6>; +- brcm,gpio-bank-widths = <32 32 16>; +- }; +- +- upg_gio_aon: gpio@408c00 { +- compatible = "brcm,brcmstb-gpio"; +- reg = <0x408c00 0x60>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupt-parent = <&upg_aon_irq0_intc>; +- interrupts = <6>; +- interrupts-extended = <&upg_aon_irq0_intc 6>, +- <&aon_pm_l2_intc 5>; +- wakeup-source; +- brcm,gpio-bank-widths = <27 32 2>; +- }; +- +- enet0: ethernet@430000 { +- phy-mode = "internal"; +- phy-handle = <&phy1>; +- mac-address = [ 00 10 18 36 23 1a ]; +- compatible = "brcm,genet-v2"; +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- reg = <0x430000 0x4c8c>; +- interrupts = <24>, <25>; +- interrupt-parent = <&periph_intc>; +- status = "disabled"; +- +- mdio@e14 { +- compatible = "brcm,genet-mdio-v2"; +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- reg = <0xe14 0x8>; +- +- phy1: ethernet-phy@1 { +- max-speed = <100>; +- reg = <0x1>; +- compatible = "brcm,40nm-ephy", +- "ethernet-phy-ieee802.3-c22"; +- }; +- }; +- }; +- +- ehci0: usb@480300 { +- compatible = "brcm,bcm7346-ehci", "generic-ehci"; +- reg = <0x480300 0x100>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <68>; +- status = "disabled"; +- }; +- +- ohci0: usb@480400 { +- compatible = "brcm,bcm7346-ohci", "generic-ohci"; +- reg = <0x480400 0x100>; +- native-endian; +- no-big-frame-no; +- interrupt-parent = <&periph_intc>; +- interrupts = <70>; +- status = "disabled"; +- }; +- +- ehci1: usb@480500 { +- compatible = "brcm,bcm7346-ehci", "generic-ehci"; +- reg = <0x480500 0x100>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <69>; +- status = "disabled"; +- }; +- +- ohci1: usb@480600 { +- compatible = "brcm,bcm7346-ohci", "generic-ohci"; +- reg = <0x480600 0x100>; +- native-endian; +- no-big-frame-no; +- interrupt-parent = <&periph_intc>; +- interrupts = <71>; +- status = "disabled"; +- }; +- +- ehci2: usb@490300 { +- compatible = "brcm,bcm7346-ehci", "generic-ehci"; +- reg = <0x490300 0x100>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <73>; +- status = "disabled"; +- }; +- +- ohci2: usb@490400 { +- compatible = "brcm,bcm7346-ohci", "generic-ohci"; +- reg = <0x490400 0x100>; +- native-endian; +- no-big-frame-no; +- interrupt-parent = <&periph_intc>; +- interrupts = <75>; +- status = "disabled"; +- }; +- +- ehci3: usb@490500 { +- compatible = "brcm,bcm7346-ehci", "generic-ehci"; +- reg = <0x490500 0x100>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <74>; +- status = "disabled"; +- }; +- +- ohci3: usb@490600 { +- compatible = "brcm,bcm7346-ohci", "generic-ohci"; +- reg = <0x490600 0x100>; +- native-endian; +- no-big-frame-no; +- interrupt-parent = <&periph_intc>; +- interrupts = <76>; +- status = "disabled"; +- }; +- +- hif_l2_intc: interrupt-controller@411000 { +- compatible = "brcm,l2-intc"; +- reg = <0x411000 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <30>; +- }; +- +- nand: nand@412800 { +- compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg-names = "nand"; +- reg = <0x412800 0x400>; +- interrupt-parent = <&hif_l2_intc>; +- interrupts = <24>; +- status = "disabled"; +- }; +- +- sata: sata@181000 { +- compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; +- reg-names = "ahci", "top-ctrl"; +- reg = <0x181000 0xa9c>, <0x180020 0x1c>; +- interrupt-parent = <&periph_intc>; +- interrupts = <40>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- sata0: sata-port@0 { +- reg = <0>; +- phys = <&sata_phy0>; +- }; +- +- sata1: sata-port@1 { +- reg = <1>; +- phys = <&sata_phy1>; +- }; +- }; +- +- sata_phy: sata-phy@180100 { +- compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3"; +- reg = <0x180100 0x0eff>; +- reg-names = "phy"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- sata_phy0: sata-phy@0 { +- reg = <0>; +- #phy-cells = <0>; +- }; +- +- sata_phy1: sata-phy@1 { +- reg = <1>; +- #phy-cells = <0>; +- }; +- }; +- +- sdhci0: sdhci@413500 { +- compatible = "brcm,bcm7425-sdhci"; +- reg = <0x413500 0x100>; +- interrupt-parent = <&periph_intc>; +- interrupts = <85>; +- status = "disabled"; +- }; +- +- spi_l2_intc: interrupt-controller@411d00 { +- compatible = "brcm,l2-intc"; +- reg = <0x411d00 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <31>; +- }; +- +- qspi: spi@413000 { +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- compatible = "brcm,spi-bcm-qspi", +- "brcm,spi-brcmstb-qspi"; +- clocks = <&upg_clk>; +- reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>; +- reg-names = "cs_reg", "hif_mspi", "bspi"; +- interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>; +- interrupt-parent = <&spi_l2_intc>; +- interrupt-names = "spi_lr_fullness_reached", +- "spi_lr_session_aborted", +- "spi_lr_impatient", +- "spi_lr_session_done", +- "spi_lr_overread", +- "mspi_done", +- "mspi_halted"; +- status = "disabled"; +- }; +- +- mspi: spi@408a00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,spi-bcm-qspi", +- "brcm,spi-brcmstb-mspi"; +- clocks = <&upg_clk>; +- reg = <0x408a00 0x180>; +- reg-names = "mspi"; +- interrupts = <0x14>; +- interrupt-parent = <&upg_aon_irq0_intc>; +- interrupt-names = "mspi_done"; +- status = "disabled"; +- }; +- +- waketimer: waketimer@408e80 { +- compatible = "brcm,brcmstb-waketimer"; +- reg = <0x408e80 0x14>; +- interrupts = <0x3>; +- interrupt-parent = <&aon_pm_l2_intc>; +- interrupt-names = "timer"; +- clocks = <&upg_clk>; +- status = "disabled"; +- }; +- }; +- +- memory_controllers { +- compatible = "simple-bus"; +- ranges = <0x0 0x103b0000 0xa000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory-controller@0 { +- compatible = "brcm,brcmstb-memc", "simple-bus"; +- ranges = <0x0 0x0 0xa000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memc-arb@1000 { +- compatible = "brcm,brcmstb-memc-arb"; +- reg = <0x1000 0x248>; +- }; +- +- memc-ddr@2000 { +- compatible = "brcm,brcmstb-memc-ddr"; +- reg = <0x2000 0x300>; +- }; +- +- ddr-phy@6000 { +- compatible = "brcm,brcmstb-ddr-phy"; +- reg = <0x6000 0xc8>; +- }; +- +- shimphy@8000 { +- compatible = "brcm,brcmstb-ddr-shimphy"; +- reg = <0x8000 0x13c>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm7358.dtsi b/scripts/dtc/include-prefixes/mips/brcm/bcm7358.dtsi +deleted file mode 100644 +index 6375fc77f389..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm7358.dtsi ++++ /dev/null +@@ -1,383 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "brcm,bcm7358"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mips-hpt-frequency = <375000000>; +- +- cpu@0 { +- compatible = "brcm,bmips3300"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- aliases { +- uart0 = &uart0; +- }; +- +- cpu_intc: interrupt-controller { +- #address-cells = <0>; +- compatible = "mti,cpu-interrupt-controller"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- clocks { +- uart_clk: uart_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <81000000>; +- }; +- +- upg_clk: upg_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- }; +- }; +- +- rdb { +- #address-cells = <1>; +- #size-cells = <1>; +- +- compatible = "simple-bus"; +- ranges = <0 0x10000000 0x01000000>; +- +- periph_intc: interrupt-controller@411400 { +- compatible = "brcm,bcm7038-l1-intc"; +- reg = <0x411400 0x30>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpu_intc>; +- interrupts = <2>; +- }; +- +- sun_l2_intc: interrupt-controller@403000 { +- compatible = "brcm,l2-intc"; +- reg = <0x403000 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <48>; +- }; +- +- gisb-arb@400000 { +- compatible = "brcm,bcm7400-gisb-arb"; +- reg = <0x400000 0xdc>; +- native-endian; +- interrupt-parent = <&sun_l2_intc>; +- interrupts = <0>, <2>; +- brcm,gisb-arb-master-mask = <0x2f3>; +- brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0", +- "rdc_0", "raaga_0", +- "avd_0", "jtag_0"; +- }; +- +- upg_irq0_intc: interrupt-controller@406600 { +- compatible = "brcm,bcm7120-l2-intc"; +- reg = <0x406600 0x8>; +- +- brcm,int-map-mask = <0x44>, <0x7000000>; +- brcm,int-fwd-mask = <0x70000>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <56>, <54>; +- interrupt-names = "upg_main", "upg_bsc"; +- }; +- +- upg_aon_irq0_intc: interrupt-controller@408b80 { +- compatible = "brcm,bcm7120-l2-intc"; +- reg = <0x408b80 0x8>; +- +- brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>; +- brcm,int-fwd-mask = <0>; +- brcm,irq-can-wake; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <57>, <55>, <59>; +- interrupt-names = "upg_main_aon", "upg_bsc_aon", +- "upg_spi"; +- }; +- +- sun_top_ctrl: syscon@404000 { +- compatible = "brcm,bcm7358-sun-top-ctrl", "syscon"; +- reg = <0x404000 0x51c>; +- native-endian; +- }; +- +- reboot { +- compatible = "brcm,brcmstb-reboot"; +- syscon = <&sun_top_ctrl 0x304 0x308>; +- }; +- +- uart0: serial@406800 { +- compatible = "ns16550a"; +- reg = <0x406800 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <61>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart1: serial@406840 { +- compatible = "ns16550a"; +- reg = <0x406840 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <62>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart2: serial@406880 { +- compatible = "ns16550a"; +- reg = <0x406880 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <63>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- bsca: i2c@406200 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406200 0x58>; +- interrupts = <24>; +- interrupt-names = "upg_bsca"; +- status = "disabled"; +- }; +- +- bscb: i2c@406280 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406280 0x58>; +- interrupts = <25>; +- interrupt-names = "upg_bscb"; +- status = "disabled"; +- }; +- +- bscc: i2c@406300 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406300 0x58>; +- interrupts = <26>; +- interrupt-names = "upg_bscc"; +- status = "disabled"; +- }; +- +- bscd: i2c@408980 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_aon_irq0_intc>; +- reg = <0x408980 0x58>; +- interrupts = <27>; +- interrupt-names = "upg_bscd"; +- status = "disabled"; +- }; +- +- pwma: pwm@406400 { +- compatible = "brcm,bcm7038-pwm"; +- reg = <0x406400 0x28>; +- #pwm-cells = <2>; +- clocks = <&upg_clk>; +- status = "disabled"; +- }; +- +- pwmb: pwm@406700 { +- compatible = "brcm,bcm7038-pwm"; +- reg = <0x406700 0x28>; +- #pwm-cells = <2>; +- clocks = <&upg_clk>; +- status = "disabled"; +- }; +- +- watchdog: watchdog@4066a8 { +- clocks = <&upg_clk>; +- compatible = "brcm,bcm7038-wdt"; +- reg = <0x4066a8 0x14>; +- status = "disabled"; +- }; +- +- aon_pm_l2_intc: interrupt-controller@408240 { +- compatible = "brcm,l2-intc"; +- reg = <0x408240 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <50>; +- brcm,irq-can-wake; +- }; +- +- upg_gio: gpio@406500 { +- compatible = "brcm,brcmstb-gpio"; +- reg = <0x406500 0xa0>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupt-parent = <&upg_irq0_intc>; +- interrupts = <6>; +- brcm,gpio-bank-widths = <32 32 32 29 4>; +- }; +- +- upg_gio_aon: gpio@408c00 { +- compatible = "brcm,brcmstb-gpio"; +- reg = <0x408c00 0x60>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupt-parent = <&upg_aon_irq0_intc>; +- interrupts = <6>; +- interrupts-extended = <&upg_aon_irq0_intc 6>, +- <&aon_pm_l2_intc 5>; +- wakeup-source; +- brcm,gpio-bank-widths = <21 32 2>; +- }; +- +- enet0: ethernet@430000 { +- phy-mode = "internal"; +- phy-handle = <&phy1>; +- mac-address = [ 00 10 18 36 23 1a ]; +- compatible = "brcm,genet-v2"; +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- reg = <0x430000 0x4c8c>; +- interrupts = <24>, <25>; +- interrupt-parent = <&periph_intc>; +- status = "disabled"; +- +- mdio@e14 { +- compatible = "brcm,genet-mdio-v2"; +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- reg = <0xe14 0x8>; +- +- phy1: ethernet-phy@1 { +- max-speed = <100>; +- reg = <0x1>; +- compatible = "brcm,40nm-ephy", +- "ethernet-phy-ieee802.3-c22"; +- }; +- }; +- }; +- +- ehci0: usb@480300 { +- compatible = "brcm,bcm7358-ehci", "generic-ehci"; +- reg = <0x480300 0x100>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <65>; +- status = "disabled"; +- }; +- +- ohci0: usb@480400 { +- compatible = "brcm,bcm7358-ohci", "generic-ohci"; +- reg = <0x480400 0x100>; +- native-endian; +- no-big-frame-no; +- interrupt-parent = <&periph_intc>; +- interrupts = <66>; +- status = "disabled"; +- }; +- +- hif_l2_intc: interrupt-controller@411000 { +- compatible = "brcm,l2-intc"; +- reg = <0x411000 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <30>; +- }; +- +- nand: nand@412800 { +- compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg-names = "nand"; +- reg = <0x412800 0x400>; +- interrupt-parent = <&hif_l2_intc>; +- interrupts = <24>; +- status = "disabled"; +- }; +- +- spi_l2_intc: interrupt-controller@411d00 { +- compatible = "brcm,l2-intc"; +- reg = <0x411d00 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <31>; +- }; +- +- qspi: spi@413000 { +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- compatible = "brcm,spi-bcm-qspi", +- "brcm,spi-brcmstb-qspi"; +- clocks = <&upg_clk>; +- reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>; +- reg-names = "cs_reg", "hif_mspi", "bspi"; +- interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>; +- interrupt-parent = <&spi_l2_intc>; +- interrupt-names = "spi_lr_fullness_reached", +- "spi_lr_session_aborted", +- "spi_lr_impatient", +- "spi_lr_session_done", +- "spi_lr_overread", +- "mspi_done", +- "mspi_halted"; +- status = "disabled"; +- }; +- +- mspi: spi@408a00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,spi-bcm-qspi", +- "brcm,spi-brcmstb-mspi"; +- clocks = <&upg_clk>; +- reg = <0x408a00 0x180>; +- reg-names = "mspi"; +- interrupts = <0x14>; +- interrupt-parent = <&upg_aon_irq0_intc>; +- interrupt-names = "mspi_done"; +- status = "disabled"; +- }; +- +- waketimer: waketimer@408e80 { +- compatible = "brcm,brcmstb-waketimer"; +- reg = <0x408e80 0x14>; +- interrupts = <0x3>; +- interrupt-parent = <&aon_pm_l2_intc>; +- interrupt-names = "timer"; +- clocks = <&upg_clk>; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm7360.dtsi b/scripts/dtc/include-prefixes/mips/brcm/bcm7360.dtsi +deleted file mode 100644 +index a57cacea91cf..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm7360.dtsi ++++ /dev/null +@@ -1,468 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "brcm,bcm7360"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mips-hpt-frequency = <375000000>; +- +- cpu@0 { +- compatible = "brcm,bmips3300"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- aliases { +- uart0 = &uart0; +- }; +- +- cpu_intc: interrupt-controller { +- #address-cells = <0>; +- compatible = "mti,cpu-interrupt-controller"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- clocks { +- uart_clk: uart_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <81000000>; +- }; +- +- upg_clk: upg_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- }; +- }; +- +- rdb { +- #address-cells = <1>; +- #size-cells = <1>; +- +- compatible = "simple-bus"; +- ranges = <0 0x10000000 0x01000000>; +- +- periph_intc: interrupt-controller@411400 { +- compatible = "brcm,bcm7038-l1-intc"; +- reg = <0x411400 0x30>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpu_intc>; +- interrupts = <2>; +- }; +- +- sun_l2_intc: interrupt-controller@403000 { +- compatible = "brcm,l2-intc"; +- reg = <0x403000 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <48>; +- }; +- +- gisb-arb@400000 { +- compatible = "brcm,bcm7400-gisb-arb"; +- reg = <0x400000 0xdc>; +- native-endian; +- interrupt-parent = <&sun_l2_intc>; +- interrupts = <0>, <2>; +- brcm,gisb-arb-master-mask = <0x2f3>; +- brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0", +- "rdc_0", "raaga_0", +- "avd_0", "jtag_0"; +- }; +- +- upg_irq0_intc: interrupt-controller@406600 { +- compatible = "brcm,bcm7120-l2-intc"; +- reg = <0x406600 0x8>; +- +- brcm,int-map-mask = <0x44>, <0x7000000>; +- brcm,int-fwd-mask = <0x70000>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <56>, <54>; +- interrupt-names = "upg_main", "upg_bsc"; +- }; +- +- upg_aon_irq0_intc: interrupt-controller@408b80 { +- compatible = "brcm,bcm7120-l2-intc"; +- reg = <0x408b80 0x8>; +- +- brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>; +- brcm,int-fwd-mask = <0>; +- brcm,irq-can-wake; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <57>, <55>, <59>; +- interrupt-names = "upg_main_aon", "upg_bsc_aon", +- "upg_spi"; +- }; +- +- sun_top_ctrl: syscon@404000 { +- compatible = "brcm,bcm7360-sun-top-ctrl", "syscon"; +- reg = <0x404000 0x51c>; +- native-endian; +- }; +- +- reboot { +- compatible = "brcm,brcmstb-reboot"; +- syscon = <&sun_top_ctrl 0x304 0x308>; +- }; +- +- uart0: serial@406800 { +- compatible = "ns16550a"; +- reg = <0x406800 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <61>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart1: serial@406840 { +- compatible = "ns16550a"; +- reg = <0x406840 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <62>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart2: serial@406880 { +- compatible = "ns16550a"; +- reg = <0x406880 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <63>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- bsca: i2c@406200 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406200 0x58>; +- interrupts = <24>; +- interrupt-names = "upg_bsca"; +- status = "disabled"; +- }; +- +- bscb: i2c@406280 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406280 0x58>; +- interrupts = <25>; +- interrupt-names = "upg_bscb"; +- status = "disabled"; +- }; +- +- bscc: i2c@406300 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406300 0x58>; +- interrupts = <26>; +- interrupt-names = "upg_bscc"; +- status = "disabled"; +- }; +- +- bscd: i2c@408980 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_aon_irq0_intc>; +- reg = <0x408980 0x58>; +- interrupts = <27>; +- interrupt-names = "upg_bscd"; +- status = "disabled"; +- }; +- +- pwma: pwm@406400 { +- compatible = "brcm,bcm7038-pwm"; +- reg = <0x406400 0x28>; +- #pwm-cells = <2>; +- clocks = <&upg_clk>; +- status = "disabled"; +- }; +- +- watchdog: watchdog@4066a8 { +- clocks = <&upg_clk>; +- compatible = "brcm,bcm7038-wdt"; +- reg = <0x4066a8 0x14>; +- status = "disabled"; +- }; +- +- aon_pm_l2_intc: interrupt-controller@408440 { +- compatible = "brcm,l2-intc"; +- reg = <0x408440 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <50>; +- brcm,irq-can-wake; +- }; +- +- aon_ctrl: syscon@408000 { +- compatible = "brcm,brcmstb-aon-ctrl"; +- reg = <0x408000 0x100>, <0x408200 0x200>; +- reg-names = "aon-ctrl", "aon-sram"; +- }; +- +- timers: timer@406680 { +- compatible = "brcm,brcmstb-timers"; +- reg = <0x406680 0x40>; +- }; +- +- upg_gio: gpio@406500 { +- compatible = "brcm,brcmstb-gpio"; +- reg = <0x406500 0xa0>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupt-parent = <&upg_irq0_intc>; +- interrupts = <6>; +- brcm,gpio-bank-widths = <32 32 32 29 4>; +- }; +- +- upg_gio_aon: gpio@408c00 { +- compatible = "brcm,brcmstb-gpio"; +- reg = <0x408c00 0x60>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupt-parent = <&upg_aon_irq0_intc>; +- interrupts = <6>; +- interrupts-extended = <&upg_aon_irq0_intc 6>, +- <&aon_pm_l2_intc 5>; +- wakeup-source; +- brcm,gpio-bank-widths = <21 32 2>; +- }; +- +- enet0: ethernet@430000 { +- phy-mode = "internal"; +- phy-handle = <&phy1>; +- mac-address = [ 00 10 18 36 23 1a ]; +- compatible = "brcm,genet-v2"; +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- reg = <0x430000 0x4c8c>; +- interrupts = <24>, <25>; +- interrupt-parent = <&periph_intc>; +- status = "disabled"; +- +- mdio@e14 { +- compatible = "brcm,genet-mdio-v2"; +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- reg = <0xe14 0x8>; +- +- phy1: ethernet-phy@1 { +- max-speed = <100>; +- reg = <0x1>; +- compatible = "brcm,40nm-ephy", +- "ethernet-phy-ieee802.3-c22"; +- }; +- }; +- }; +- +- ehci0: usb@480300 { +- compatible = "brcm,bcm7360-ehci", "generic-ehci"; +- reg = <0x480300 0x100>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <65>; +- status = "disabled"; +- }; +- +- ohci0: usb@480400 { +- compatible = "brcm,bcm7360-ohci", "generic-ohci"; +- reg = <0x480400 0x100>; +- native-endian; +- no-big-frame-no; +- interrupt-parent = <&periph_intc>; +- interrupts = <66>; +- status = "disabled"; +- }; +- +- hif_l2_intc: interrupt-controller@411000 { +- compatible = "brcm,l2-intc"; +- reg = <0x411000 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <30>; +- }; +- +- nand: nand@412800 { +- compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg-names = "nand"; +- reg = <0x412800 0x400>; +- interrupt-parent = <&hif_l2_intc>; +- interrupts = <24>; +- status = "disabled"; +- }; +- +- sata: sata@181000 { +- compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; +- reg-names = "ahci", "top-ctrl"; +- reg = <0x181000 0xa9c>, <0x180020 0x1c>; +- interrupt-parent = <&periph_intc>; +- interrupts = <86>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- sata0: sata-port@0 { +- reg = <0>; +- phys = <&sata_phy0>; +- }; +- +- sata1: sata-port@1 { +- reg = <1>; +- phys = <&sata_phy1>; +- }; +- }; +- +- sata_phy: sata-phy@180100 { +- compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3"; +- reg = <0x180100 0x0eff>; +- reg-names = "phy"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- sata_phy0: sata-phy@0 { +- reg = <0>; +- #phy-cells = <0>; +- }; +- +- sata_phy1: sata-phy@1 { +- reg = <1>; +- #phy-cells = <0>; +- }; +- }; +- +- sdhci0: sdhci@410000 { +- compatible = "brcm,bcm7425-sdhci"; +- reg = <0x410000 0x100>; +- interrupt-parent = <&periph_intc>; +- interrupts = <82>; +- status = "disabled"; +- }; +- +- spi_l2_intc: interrupt-controller@411d00 { +- compatible = "brcm,l2-intc"; +- reg = <0x411d00 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <31>; +- }; +- +- qspi: spi@413000 { +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- compatible = "brcm,spi-bcm-qspi", +- "brcm,spi-brcmstb-qspi"; +- clocks = <&upg_clk>; +- reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>; +- reg-names = "cs_reg", "hif_mspi", "bspi"; +- interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>; +- interrupt-parent = <&spi_l2_intc>; +- interrupt-names = "spi_lr_fullness_reached", +- "spi_lr_session_aborted", +- "spi_lr_impatient", +- "spi_lr_session_done", +- "spi_lr_overread", +- "mspi_done", +- "mspi_halted"; +- status = "disabled"; +- }; +- +- mspi: spi@408a00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,spi-bcm-qspi", +- "brcm,spi-brcmstb-mspi"; +- clocks = <&upg_clk>; +- reg = <0x408a00 0x180>; +- reg-names = "mspi"; +- interrupts = <0x14>; +- interrupt-parent = <&upg_aon_irq0_intc>; +- interrupt-names = "mspi_done"; +- status = "disabled"; +- }; +- +- waketimer: waketimer@408e80 { +- compatible = "brcm,brcmstb-waketimer"; +- reg = <0x408e80 0x14>; +- interrupts = <0x3>; +- interrupt-parent = <&aon_pm_l2_intc>; +- interrupt-names = "timer"; +- clocks = <&upg_clk>; +- status = "disabled"; +- }; +- }; +- +- memory_controllers { +- compatible = "simple-bus"; +- ranges = <0x0 0x103b0000 0xa000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory-controller@0 { +- compatible = "brcm,brcmstb-memc", "simple-bus"; +- ranges = <0x0 0x0 0xa000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memc-arb@1000 { +- compatible = "brcm,brcmstb-memc-arb"; +- reg = <0x1000 0x248>; +- }; +- +- memc-ddr@2000 { +- compatible = "brcm,brcmstb-memc-ddr"; +- reg = <0x2000 0x300>; +- }; +- +- ddr-phy@6000 { +- compatible = "brcm,brcmstb-ddr-phy"; +- reg = <0x6000 0xc8>; +- }; +- +- shimphy@8000 { +- compatible = "brcm,brcmstb-ddr-shimphy"; +- reg = <0x8000 0x13c>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm7362.dtsi b/scripts/dtc/include-prefixes/mips/brcm/bcm7362.dtsi +deleted file mode 100644 +index 728b9e9f84b8..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm7362.dtsi ++++ /dev/null +@@ -1,464 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "brcm,bcm7362"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mips-hpt-frequency = <375000000>; +- +- cpu@0 { +- compatible = "brcm,bmips4380"; +- device_type = "cpu"; +- reg = <0>; +- }; +- +- cpu@1 { +- compatible = "brcm,bmips4380"; +- device_type = "cpu"; +- reg = <1>; +- }; +- }; +- +- aliases { +- uart0 = &uart0; +- }; +- +- cpu_intc: interrupt-controller { +- #address-cells = <0>; +- compatible = "mti,cpu-interrupt-controller"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- clocks { +- uart_clk: uart_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <81000000>; +- }; +- +- upg_clk: upg_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- }; +- }; +- +- rdb { +- #address-cells = <1>; +- #size-cells = <1>; +- +- compatible = "simple-bus"; +- ranges = <0 0x10000000 0x01000000>; +- +- periph_intc: interrupt-controller@411400 { +- compatible = "brcm,bcm7038-l1-intc"; +- reg = <0x411400 0x30>, <0x411600 0x30>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpu_intc>; +- interrupts = <2>, <3>; +- }; +- +- sun_l2_intc: interrupt-controller@403000 { +- compatible = "brcm,l2-intc"; +- reg = <0x403000 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <48>; +- }; +- +- gisb-arb@400000 { +- compatible = "brcm,bcm7400-gisb-arb"; +- reg = <0x400000 0xdc>; +- native-endian; +- interrupt-parent = <&sun_l2_intc>; +- interrupts = <0>, <2>; +- brcm,gisb-arb-master-mask = <0x2f3>; +- brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0", +- "rdc_0", "raaga_0", +- "avd_0", "jtag_0"; +- }; +- +- upg_irq0_intc: interrupt-controller@406600 { +- compatible = "brcm,bcm7120-l2-intc"; +- reg = <0x406600 0x8>; +- +- brcm,int-map-mask = <0x44>, <0x7000000>; +- brcm,int-fwd-mask = <0x70000>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <56>, <54>; +- interrupt-names = "upg_main", "upg_bsc"; +- }; +- +- upg_aon_irq0_intc: interrupt-controller@408b80 { +- compatible = "brcm,bcm7120-l2-intc"; +- reg = <0x408b80 0x8>; +- +- brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>; +- brcm,int-fwd-mask = <0>; +- brcm,irq-can-wake; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <57>, <55>, <59>; +- interrupt-names = "upg_main_aon", "upg_bsc_aon", +- "upg_spi"; +- }; +- +- sun_top_ctrl: syscon@404000 { +- compatible = "brcm,bcm7362-sun-top-ctrl", "syscon"; +- reg = <0x404000 0x51c>; +- native-endian; +- }; +- +- reboot { +- compatible = "brcm,brcmstb-reboot"; +- syscon = <&sun_top_ctrl 0x304 0x308>; +- }; +- +- uart0: serial@406800 { +- compatible = "ns16550a"; +- reg = <0x406800 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <61>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart1: serial@406840 { +- compatible = "ns16550a"; +- reg = <0x406840 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <62>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart2: serial@406880 { +- compatible = "ns16550a"; +- reg = <0x406880 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <63>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- bsca: i2c@406200 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406200 0x58>; +- interrupts = <24>; +- interrupt-names = "upg_bsca"; +- status = "disabled"; +- }; +- +- bscb: i2c@406280 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406280 0x58>; +- interrupts = <25>; +- interrupt-names = "upg_bscb"; +- status = "disabled"; +- }; +- +- bscd: i2c@408980 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_aon_irq0_intc>; +- reg = <0x408980 0x58>; +- interrupts = <27>; +- interrupt-names = "upg_bscd"; +- status = "disabled"; +- }; +- +- pwma: pwm@406400 { +- compatible = "brcm,bcm7038-pwm"; +- reg = <0x406400 0x28>; +- #pwm-cells = <2>; +- clocks = <&upg_clk>; +- status = "disabled"; +- }; +- +- watchdog: watchdog@4066a8 { +- clocks = <&upg_clk>; +- compatible = "brcm,bcm7038-wdt"; +- reg = <0x4066a8 0x14>; +- status = "disabled"; +- }; +- +- aon_pm_l2_intc: interrupt-controller@408440 { +- compatible = "brcm,l2-intc"; +- reg = <0x408440 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <50>; +- brcm,irq-can-wake; +- }; +- +- aon_ctrl: syscon@408000 { +- compatible = "brcm,brcmstb-aon-ctrl"; +- reg = <0x408000 0x100>, <0x408200 0x200>; +- reg-names = "aon-ctrl", "aon-sram"; +- }; +- +- timers: timer@406680 { +- compatible = "brcm,brcmstb-timers"; +- reg = <0x406680 0x40>; +- }; +- +- upg_gio: gpio@406500 { +- compatible = "brcm,brcmstb-gpio"; +- reg = <0x406500 0xa0>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupt-parent = <&upg_irq0_intc>; +- interrupts = <6>; +- brcm,gpio-bank-widths = <32 32 32 29 4>; +- }; +- +- upg_gio_aon: gpio@408c00 { +- compatible = "brcm,brcmstb-gpio"; +- reg = <0x408c00 0x60>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupt-parent = <&upg_aon_irq0_intc>; +- interrupts = <6>; +- interrupts-extended = <&upg_aon_irq0_intc 6>, +- <&aon_pm_l2_intc 5>; +- wakeup-source; +- brcm,gpio-bank-widths = <21 32 2>; +- }; +- +- enet0: ethernet@430000 { +- phy-mode = "internal"; +- phy-handle = <&phy1>; +- mac-address = [ 00 10 18 36 23 1a ]; +- compatible = "brcm,genet-v2"; +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- reg = <0x430000 0x4c8c>; +- interrupts = <24>, <25>; +- interrupt-parent = <&periph_intc>; +- status = "disabled"; +- +- mdio@e14 { +- compatible = "brcm,genet-mdio-v2"; +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- reg = <0xe14 0x8>; +- +- phy1: ethernet-phy@1 { +- max-speed = <100>; +- reg = <0x1>; +- compatible = "brcm,40nm-ephy", +- "ethernet-phy-ieee802.3-c22"; +- }; +- }; +- }; +- +- ehci0: usb@480300 { +- compatible = "brcm,bcm7362-ehci", "generic-ehci"; +- reg = <0x480300 0x100>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <65>; +- status = "disabled"; +- }; +- +- ohci0: usb@480400 { +- compatible = "brcm,bcm7362-ohci", "generic-ohci"; +- reg = <0x480400 0x100>; +- native-endian; +- no-big-frame-no; +- interrupt-parent = <&periph_intc>; +- interrupts = <66>; +- status = "disabled"; +- }; +- +- hif_l2_intc: interrupt-controller@411000 { +- compatible = "brcm,l2-intc"; +- reg = <0x411000 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <30>; +- }; +- +- nand: nand@412800 { +- compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg-names = "nand"; +- reg = <0x412800 0x400>; +- interrupt-parent = <&hif_l2_intc>; +- interrupts = <24>; +- status = "disabled"; +- }; +- +- sata: sata@181000 { +- compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; +- reg-names = "ahci", "top-ctrl"; +- reg = <0x181000 0xa9c>, <0x180020 0x1c>; +- interrupt-parent = <&periph_intc>; +- interrupts = <86>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- sata0: sata-port@0 { +- reg = <0>; +- phys = <&sata_phy0>; +- }; +- +- sata1: sata-port@1 { +- reg = <1>; +- phys = <&sata_phy1>; +- }; +- }; +- +- sata_phy: sata-phy@180100 { +- compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3"; +- reg = <0x180100 0x0eff>; +- reg-names = "phy"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- sata_phy0: sata-phy@0 { +- reg = <0>; +- #phy-cells = <0>; +- }; +- +- sata_phy1: sata-phy@1 { +- reg = <1>; +- #phy-cells = <0>; +- }; +- }; +- +- sdhci0: sdhci@410000 { +- compatible = "brcm,bcm7425-sdhci"; +- reg = <0x410000 0x100>; +- interrupt-parent = <&periph_intc>; +- interrupts = <82>; +- status = "disabled"; +- }; +- +- spi_l2_intc: interrupt-controller@411d00 { +- compatible = "brcm,l2-intc"; +- reg = <0x411d00 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <31>; +- }; +- +- qspi: spi@413000 { +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- compatible = "brcm,spi-bcm-qspi", +- "brcm,spi-brcmstb-qspi"; +- clocks = <&upg_clk>; +- reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>; +- reg-names = "cs_reg", "hif_mspi", "bspi"; +- interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>; +- interrupt-parent = <&spi_l2_intc>; +- interrupt-names = "spi_lr_fullness_reached", +- "spi_lr_session_aborted", +- "spi_lr_impatient", +- "spi_lr_session_done", +- "spi_lr_overread", +- "mspi_done", +- "mspi_halted"; +- status = "disabled"; +- }; +- +- mspi: spi@408a00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,spi-bcm-qspi", +- "brcm,spi-brcmstb-mspi"; +- clocks = <&upg_clk>; +- reg = <0x408a00 0x180>; +- reg-names = "mspi"; +- interrupts = <0x14>; +- interrupt-parent = <&upg_aon_irq0_intc>; +- interrupt-names = "mspi_done"; +- status = "disabled"; +- }; +- +- waketimer: waketimer@408e80 { +- compatible = "brcm,brcmstb-waketimer"; +- reg = <0x408e80 0x14>; +- interrupts = <0x3>; +- interrupt-parent = <&aon_pm_l2_intc>; +- interrupt-names = "timer"; +- clocks = <&upg_clk>; +- status = "disabled"; +- }; +- }; +- +- memory_controllers { +- compatible = "simple-bus"; +- ranges = <0x0 0x103b0000 0xa000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory-controller@0 { +- compatible = "brcm,brcmstb-memc", "simple-bus"; +- ranges = <0x0 0x0 0xa000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memc-arb@1000 { +- compatible = "brcm,brcmstb-memc-arb"; +- reg = <0x1000 0x248>; +- }; +- +- memc-ddr@2000 { +- compatible = "brcm,brcmstb-memc-ddr"; +- reg = <0x2000 0x300>; +- }; +- +- ddr-phy@6000 { +- compatible = "brcm,brcmstb-ddr-phy"; +- reg = <0x6000 0xc8>; +- }; +- +- shimphy@8000 { +- compatible = "brcm,brcmstb-ddr-shimphy"; +- reg = <0x8000 0x13c>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm7420.dtsi b/scripts/dtc/include-prefixes/mips/brcm/bcm7420.dtsi +deleted file mode 100644 +index 9540c27f12e7..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm7420.dtsi ++++ /dev/null +@@ -1,342 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "brcm,bcm7420"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mips-hpt-frequency = <93750000>; +- +- cpu@0 { +- compatible = "brcm,bmips5000"; +- device_type = "cpu"; +- reg = <0>; +- }; +- +- cpu@1 { +- compatible = "brcm,bmips5000"; +- device_type = "cpu"; +- reg = <1>; +- }; +- }; +- +- aliases { +- uart0 = &uart0; +- }; +- +- cpu_intc: interrupt-controller { +- #address-cells = <0>; +- compatible = "mti,cpu-interrupt-controller"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- clocks { +- uart_clk: uart_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <81000000>; +- }; +- +- upg_clk: upg_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- }; +- }; +- +- rdb { +- #address-cells = <1>; +- #size-cells = <1>; +- +- compatible = "simple-bus"; +- ranges = <0 0x10000000 0x01000000>; +- +- periph_intc: interrupt-controller@441400 { +- compatible = "brcm,bcm7038-l1-intc"; +- reg = <0x441400 0x30>, <0x441600 0x30>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpu_intc>; +- interrupts = <2>, <3>; +- }; +- +- sun_l2_intc: interrupt-controller@401800 { +- compatible = "brcm,l2-intc"; +- reg = <0x401800 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <23>; +- }; +- +- gisb-arb@400000 { +- compatible = "brcm,bcm7400-gisb-arb"; +- reg = <0x400000 0xdc>; +- native-endian; +- interrupt-parent = <&sun_l2_intc>; +- interrupts = <0>, <2>; +- brcm,gisb-arb-master-mask = <0x3ff>; +- brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0", +- "pcie_0", "bsp_0", "rdc_0", +- "rptd_0", "avd_0", "avd_1", +- "jtag_0"; +- }; +- +- upg_irq0_intc: interrupt-controller@406780 { +- compatible = "brcm,bcm7120-l2-intc"; +- reg = <0x406780 0x8>; +- +- brcm,int-map-mask = <0x44>, <0x1f000000>, <0x100000>; +- brcm,int-fwd-mask = <0x70000>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <18>, <19>, <20>; +- interrupt-names = "upg_main", "upg_bsc", "upg_spi"; +- }; +- +- sun_top_ctrl: syscon@404000 { +- compatible = "brcm,bcm7420-sun-top-ctrl", "syscon"; +- reg = <0x404000 0x60c>; +- native-endian; +- }; +- +- reboot { +- compatible = "brcm,bcm7038-reboot"; +- syscon = <&sun_top_ctrl 0x8 0x14>; +- }; +- +- uart0: serial@406b00 { +- compatible = "ns16550a"; +- reg = <0x406b00 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- interrupt-parent = <&periph_intc>; +- interrupts = <21>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart1: serial@406b40 { +- compatible = "ns16550a"; +- reg = <0x406b40 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- interrupt-parent = <&periph_intc>; +- interrupts = <64>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart2: serial@406b80 { +- compatible = "ns16550a"; +- reg = <0x406b80 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- interrupt-parent = <&periph_intc>; +- interrupts = <65>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- bsca: i2c@406200 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406200 0x58>; +- interrupts = <24>; +- interrupt-names = "upg_bsca"; +- status = "disabled"; +- }; +- +- bscb: i2c@406280 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406280 0x58>; +- interrupts = <25>; +- interrupt-names = "upg_bscb"; +- status = "disabled"; +- }; +- +- bscc: i2c@406300 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406300 0x58>; +- interrupts = <26>; +- interrupt-names = "upg_bscc"; +- status = "disabled"; +- }; +- +- bscd: i2c@406380 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406380 0x58>; +- interrupts = <27>; +- interrupt-names = "upg_bscd"; +- status = "disabled"; +- }; +- +- bsce: i2c@406800 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406800 0x58>; +- interrupts = <28>; +- interrupt-names = "upg_bsce"; +- status = "disabled"; +- }; +- +- pwma: pwm@406580 { +- compatible = "brcm,bcm7038-pwm"; +- reg = <0x406580 0x28>; +- #pwm-cells = <2>; +- clocks = <&upg_clk>; +- status = "disabled"; +- }; +- +- pwmb: pwm@406880 { +- compatible = "brcm,bcm7038-pwm"; +- reg = <0x406880 0x28>; +- #pwm-cells = <2>; +- clocks = <&upg_clk>; +- status = "disabled"; +- }; +- +- watchdog: watchdog@4067e8 { +- clocks = <&upg_clk>; +- compatible = "brcm,bcm7038-wdt"; +- reg = <0x4067e8 0x14>; +- status = "disabled"; +- }; +- +- upg_gio: gpio@406700 { +- compatible = "brcm,brcmstb-gpio"; +- reg = <0x406700 0x80>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupt-parent = <&upg_irq0_intc>; +- interrupts = <6>; +- brcm,gpio-bank-widths = <32 32 32 27>; +- }; +- +- enet0: ethernet@468000 { +- phy-mode = "internal"; +- phy-handle = <&phy1>; +- mac-address = [ 00 10 18 36 23 1a ]; +- compatible = "brcm,genet-v1"; +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- reg = <0x468000 0x3c8c>; +- interrupts = <69>, <79>; +- interrupt-parent = <&periph_intc>; +- status = "disabled"; +- +- mdio@e14 { +- compatible = "brcm,genet-mdio-v1"; +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- reg = <0xe14 0x8>; +- +- phy1: ethernet-phy@1 { +- max-speed = <100>; +- reg = <0x1>; +- compatible = "brcm,65nm-ephy", +- "ethernet-phy-ieee802.3-c22"; +- }; +- }; +- }; +- +- ehci0: usb@488300 { +- compatible = "brcm,bcm7420-ehci", "generic-ehci"; +- reg = <0x488300 0x100>; +- interrupt-parent = <&periph_intc>; +- interrupts = <60>; +- status = "disabled"; +- }; +- +- ohci0: usb@488400 { +- compatible = "brcm,bcm7420-ohci", "generic-ohci"; +- reg = <0x488400 0x100>; +- native-endian; +- no-big-frame-no; +- interrupt-parent = <&periph_intc>; +- interrupts = <61>; +- status = "disabled"; +- }; +- +- ehci1: usb@488500 { +- compatible = "brcm,bcm7420-ehci", "generic-ehci"; +- reg = <0x488500 0x100>; +- interrupt-parent = <&periph_intc>; +- interrupts = <55>; +- status = "disabled"; +- }; +- +- ohci1: usb@488600 { +- compatible = "brcm,bcm7420-ohci", "generic-ohci"; +- reg = <0x488600 0x100>; +- native-endian; +- no-big-frame-no; +- interrupt-parent = <&periph_intc>; +- interrupts = <62>; +- status = "disabled"; +- }; +- +- spi_l2_intc: interrupt-controller@411d00 { +- compatible = "brcm,l2-intc"; +- reg = <0x411d00 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <78>; +- }; +- +- qspi: spi@443000 { +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- compatible = "brcm,spi-bcm-qspi", +- "brcm,spi-brcmstb-qspi"; +- clocks = <&upg_clk>; +- reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>; +- reg-names = "cs_reg", "hif_mspi", "bspi"; +- interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>; +- interrupt-parent = <&spi_l2_intc>; +- interrupt-names = "spi_lr_fullness_reached", +- "spi_lr_session_aborted", +- "spi_lr_impatient", +- "spi_lr_session_done", +- "spi_lr_overread", +- "mspi_done", +- "mspi_halted"; +- status = "disabled"; +- }; +- +- mspi: spi@406400 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,spi-bcm-qspi", +- "brcm,spi-brcmstb-mspi"; +- clocks = <&upg_clk>; +- reg = <0x406400 0x180>; +- reg-names = "mspi"; +- interrupts = <0x14>; +- interrupt-parent = <&upg_irq0_intc>; +- interrupt-names = "mspi_done"; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm7425.dtsi b/scripts/dtc/include-prefixes/mips/brcm/bcm7425.dtsi +deleted file mode 100644 +index aa0b2d39c902..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm7425.dtsi ++++ /dev/null +@@ -1,587 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "brcm,bcm7425"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mips-hpt-frequency = <163125000>; +- +- cpu@0 { +- compatible = "brcm,bmips5000"; +- device_type = "cpu"; +- reg = <0>; +- }; +- +- cpu@1 { +- compatible = "brcm,bmips5000"; +- device_type = "cpu"; +- reg = <1>; +- }; +- }; +- +- aliases { +- uart0 = &uart0; +- }; +- +- cpu_intc: interrupt-controller { +- #address-cells = <0>; +- compatible = "mti,cpu-interrupt-controller"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- clocks { +- uart_clk: uart_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <81000000>; +- }; +- +- upg_clk: upg_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- }; +- }; +- +- rdb { +- #address-cells = <1>; +- #size-cells = <1>; +- +- compatible = "simple-bus"; +- ranges = <0 0x10000000 0x01000000>; +- +- periph_intc: interrupt-controller@41a400 { +- compatible = "brcm,bcm7038-l1-intc"; +- reg = <0x41a400 0x30>, <0x41a600 0x30>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpu_intc>; +- interrupts = <2>, <3>; +- }; +- +- sun_l2_intc: interrupt-controller@403000 { +- compatible = "brcm,l2-intc"; +- reg = <0x403000 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <47>; +- }; +- +- gisb-arb@400000 { +- compatible = "brcm,bcm7400-gisb-arb"; +- reg = <0x400000 0xdc>; +- native-endian; +- interrupt-parent = <&sun_l2_intc>; +- interrupts = <0>, <2>; +- brcm,gisb-arb-master-mask = <0x177b>; +- brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pcie_0", +- "bsp_0", "rdc_0", +- "raaga_0", "avd_1", +- "jtag_0", "svd_0", +- "vice_0"; +- }; +- +- upg_irq0_intc: interrupt-controller@406780 { +- compatible = "brcm,bcm7120-l2-intc"; +- reg = <0x406780 0x8>; +- +- brcm,int-map-mask = <0x44>, <0x7000000>; +- brcm,int-fwd-mask = <0x70000>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <55>, <53>; +- interrupt-names = "upg_main", "upg_bsc"; +- }; +- +- upg_aon_irq0_intc: interrupt-controller@409480 { +- compatible = "brcm,bcm7120-l2-intc"; +- reg = <0x409480 0x8>; +- +- brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>; +- brcm,int-fwd-mask = <0>; +- brcm,irq-can-wake; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <56>, <54>, <59>; +- interrupt-names = "upg_main_aon", "upg_bsc_aon", +- "upg_spi"; +- }; +- +- sun_top_ctrl: syscon@404000 { +- compatible = "brcm,bcm7425-sun-top-ctrl", "syscon"; +- reg = <0x404000 0x51c>; +- native-endian; +- }; +- +- reboot { +- compatible = "brcm,brcmstb-reboot"; +- syscon = <&sun_top_ctrl 0x304 0x308>; +- }; +- +- uart0: serial@406b00 { +- compatible = "ns16550a"; +- reg = <0x406b00 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- interrupt-parent = <&periph_intc>; +- interrupts = <61>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart1: serial@406b40 { +- compatible = "ns16550a"; +- reg = <0x406b40 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- interrupt-parent = <&periph_intc>; +- interrupts = <62>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart2: serial@406b80 { +- compatible = "ns16550a"; +- reg = <0x406b80 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- interrupt-parent = <&periph_intc>; +- interrupts = <63>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- bsca: i2c@409180 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_aon_irq0_intc>; +- reg = <0x409180 0x58>; +- interrupts = <27>; +- interrupt-names = "upg_bsca"; +- status = "disabled"; +- }; +- +- bscb: i2c@409400 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_aon_irq0_intc>; +- reg = <0x409400 0x58>; +- interrupts = <28>; +- interrupt-names = "upg_bscb"; +- status = "disabled"; +- }; +- +- bscc: i2c@406200 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406200 0x58>; +- interrupts = <24>; +- interrupt-names = "upg_bscc"; +- status = "disabled"; +- }; +- +- bscd: i2c@406280 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406280 0x58>; +- interrupts = <25>; +- interrupt-names = "upg_bscd"; +- status = "disabled"; +- }; +- +- bsce: i2c@406300 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406300 0x58>; +- interrupts = <26>; +- interrupt-names = "upg_bsce"; +- status = "disabled"; +- }; +- +- pwma: pwm@406580 { +- compatible = "brcm,bcm7038-pwm"; +- reg = <0x406580 0x28>; +- #pwm-cells = <2>; +- clocks = <&upg_clk>; +- status = "disabled"; +- }; +- +- pwmb: pwm@406800 { +- compatible = "brcm,bcm7038-pwm"; +- reg = <0x406800 0x28>; +- #pwm-cells = <2>; +- clocks = <&upg_clk>; +- status = "disabled"; +- }; +- +- watchdog: watchdog@4067e8 { +- clocks = <&upg_clk>; +- compatible = "brcm,bcm7038-wdt"; +- reg = <0x4067e8 0x14>; +- status = "disabled"; +- }; +- +- aon_pm_l2_intc: interrupt-controller@408440 { +- compatible = "brcm,l2-intc"; +- reg = <0x408440 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <49>; +- brcm,irq-can-wake; +- }; +- +- aon_ctrl: syscon@408000 { +- compatible = "brcm,brcmstb-aon-ctrl"; +- reg = <0x408000 0x100>, <0x408200 0x200>; +- reg-names = "aon-ctrl", "aon-sram"; +- }; +- +- timers: timer@4067c0 { +- compatible = "brcm,brcmstb-timers"; +- reg = <0x4067c0 0x40>; +- }; +- +- upg_gio: gpio@406700 { +- compatible = "brcm,brcmstb-gpio"; +- reg = <0x406700 0x80>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupt-parent = <&upg_irq0_intc>; +- interrupts = <6>; +- brcm,gpio-bank-widths = <32 32 32 21>; +- }; +- +- upg_gio_aon: gpio@4094c0 { +- compatible = "brcm,brcmstb-gpio"; +- reg = <0x4094c0 0x40>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupt-parent = <&upg_aon_irq0_intc>; +- interrupts = <6>; +- interrupts-extended = <&upg_aon_irq0_intc 6>, +- <&aon_pm_l2_intc 5>; +- wakeup-source; +- brcm,gpio-bank-widths = <18 4>; +- }; +- +- enet0: ethernet@b80000 { +- phy-mode = "internal"; +- phy-handle = <&phy1>; +- mac-address = [ 00 10 18 36 23 1a ]; +- compatible = "brcm,genet-v3"; +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- reg = <0xb80000 0x11c88>; +- interrupts = <17>, <18>; +- interrupt-parent = <&periph_intc>; +- status = "disabled"; +- +- mdio@e14 { +- compatible = "brcm,genet-mdio-v3"; +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- reg = <0xe14 0x8>; +- +- phy1: ethernet-phy@1 { +- max-speed = <100>; +- reg = <0x1>; +- compatible = "brcm,40nm-ephy", +- "ethernet-phy-ieee802.3-c22"; +- }; +- }; +- }; +- +- ehci0: usb@480300 { +- compatible = "brcm,bcm7425-ehci", "generic-ehci"; +- reg = <0x480300 0x100>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <65>; +- status = "disabled"; +- }; +- +- ohci0: usb@480400 { +- compatible = "brcm,bcm7425-ohci", "generic-ohci"; +- reg = <0x480400 0x100>; +- native-endian; +- no-big-frame-no; +- interrupt-parent = <&periph_intc>; +- interrupts = <67>; +- status = "disabled"; +- }; +- +- ehci1: usb@480500 { +- compatible = "brcm,bcm7425-ehci", "generic-ehci"; +- reg = <0x480500 0x100>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <66>; +- status = "disabled"; +- }; +- +- ohci1: usb@480600 { +- compatible = "brcm,bcm7425-ohci", "generic-ohci"; +- reg = <0x480600 0x100>; +- native-endian; +- no-big-frame-no; +- interrupt-parent = <&periph_intc>; +- interrupts = <68>; +- status = "disabled"; +- }; +- +- ehci2: usb@490300 { +- compatible = "brcm,bcm7425-ehci", "generic-ehci"; +- reg = <0x490300 0x100>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <70>; +- status = "disabled"; +- }; +- +- ohci2: usb@490400 { +- compatible = "brcm,bcm7425-ohci", "generic-ohci"; +- reg = <0x490400 0x100>; +- native-endian; +- no-big-frame-no; +- interrupt-parent = <&periph_intc>; +- interrupts = <72>; +- status = "disabled"; +- }; +- +- ehci3: usb@490500 { +- compatible = "brcm,bcm7425-ehci", "generic-ehci"; +- reg = <0x490500 0x100>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <71>; +- status = "disabled"; +- }; +- +- ohci3: usb@490600 { +- compatible = "brcm,bcm7425-ohci", "generic-ohci"; +- reg = <0x490600 0x100>; +- native-endian; +- no-big-frame-no; +- interrupt-parent = <&periph_intc>; +- interrupts = <73>; +- status = "disabled"; +- }; +- +- hif_l2_intc: interrupt-controller@41a000 { +- compatible = "brcm,l2-intc"; +- reg = <0x41a000 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <24>; +- }; +- +- nand: nand@41b800 { +- compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg-names = "nand", "flash-edu"; +- reg = <0x41b800 0x400>, <0x41bc00 0x24>; +- interrupt-parent = <&hif_l2_intc>; +- interrupts = <24>; +- status = "disabled"; +- }; +- +- sata: sata@181000 { +- compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; +- reg-names = "ahci", "top-ctrl"; +- reg = <0x181000 0xa9c>, <0x180020 0x1c>; +- interrupt-parent = <&periph_intc>; +- interrupts = <41>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- sata0: sata-port@0 { +- reg = <0>; +- phys = <&sata_phy0>; +- }; +- +- sata1: sata-port@1 { +- reg = <1>; +- phys = <&sata_phy1>; +- }; +- }; +- +- sata_phy: sata-phy@180100 { +- compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3"; +- reg = <0x180100 0x0eff>; +- reg-names = "phy"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- sata_phy0: sata-phy@0 { +- reg = <0>; +- #phy-cells = <0>; +- }; +- +- sata_phy1: sata-phy@1 { +- reg = <1>; +- #phy-cells = <0>; +- }; +- }; +- +- sdhci0: sdhci@419000 { +- compatible = "brcm,bcm7425-sdhci"; +- reg = <0x419000 0x100>; +- interrupt-parent = <&periph_intc>; +- interrupts = <43>; +- sd-uhs-sdr50; +- mmc-hs200-1_8v; +- status = "disabled"; +- }; +- +- sdhci1: sdhci@419200 { +- compatible = "brcm,bcm7425-sdhci"; +- reg = <0x419200 0x100>; +- interrupt-parent = <&periph_intc>; +- interrupts = <44>; +- sd-uhs-sdr50; +- mmc-hs200-1_8v; +- status = "disabled"; +- }; +- +- spi_l2_intc: interrupt-controller@41ad00 { +- compatible = "brcm,l2-intc"; +- reg = <0x41ad00 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <25>; +- }; +- +- qspi: spi@41c000 { +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- compatible = "brcm,spi-bcm-qspi", +- "brcm,spi-brcmstb-qspi"; +- clocks = <&upg_clk>; +- reg = <0x419920 0x4 0x41c200 0x188 0x41c000 0x50>; +- reg-names = "cs_reg", "hif_mspi", "bspi"; +- interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>; +- interrupt-parent = <&spi_l2_intc>; +- interrupt-names = "spi_lr_fullness_reached", +- "spi_lr_session_aborted", +- "spi_lr_impatient", +- "spi_lr_session_done", +- "spi_lr_overread", +- "mspi_done", +- "mspi_halted"; +- status = "disabled"; +- }; +- +- mspi: spi@409200 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,spi-bcm-qspi", +- "brcm,spi-brcmstb-mspi"; +- clocks = <&upg_clk>; +- reg = <0x409200 0x180>; +- reg-names = "mspi"; +- interrupts = <0x14>; +- interrupt-parent = <&upg_aon_irq0_intc>; +- interrupt-names = "mspi_done"; +- status = "disabled"; +- }; +- +- waketimer: waketimer@409580 { +- compatible = "brcm,brcmstb-waketimer"; +- reg = <0x409580 0x14>; +- interrupts = <0x3>; +- interrupt-parent = <&aon_pm_l2_intc>; +- interrupt-names = "timer"; +- clocks = <&upg_clk>; +- status = "disabled"; +- }; +- }; +- +- memory_controllers { +- compatible = "simple-bus"; +- ranges = <0x0 0x103b0000 0x1a000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory-controller@0 { +- compatible = "brcm,brcmstb-memc", "simple-bus"; +- ranges = <0x0 0x0 0xa000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memc-arb@1000 { +- compatible = "brcm,brcmstb-memc-arb"; +- reg = <0x1000 0x248>; +- }; +- +- memc-ddr@2000 { +- compatible = "brcm,brcmstb-memc-ddr"; +- reg = <0x2000 0x300>; +- }; +- +- ddr-phy@6000 { +- compatible = "brcm,brcmstb-ddr-phy"; +- reg = <0x6000 0xc8>; +- }; +- +- shimphy@8000 { +- compatible = "brcm,brcmstb-ddr-shimphy"; +- reg = <0x8000 0x13c>; +- }; +- }; +- +- memory-controller@1 { +- compatible = "brcm,brcmstb-memc", "simple-bus"; +- ranges = <0x0 0x10000 0xa000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memc-arb@1000 { +- compatible = "brcm,brcmstb-memc-arb"; +- reg = <0x1000 0x248>; +- }; +- +- memc-ddr@2000 { +- compatible = "brcm,brcmstb-memc-ddr"; +- reg = <0x2000 0x300>; +- }; +- +- ddr-phy@6000 { +- compatible = "brcm,brcmstb-ddr-phy"; +- reg = <0x6000 0xc8>; +- }; +- +- shimphy@8000 { +- compatible = "brcm,brcmstb-ddr-shimphy"; +- reg = <0x8000 0x13c>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm7435.dtsi b/scripts/dtc/include-prefixes/mips/brcm/bcm7435.dtsi +deleted file mode 100644 +index 8398b7f68bf4..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm7435.dtsi ++++ /dev/null +@@ -1,602 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "brcm,bcm7435"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- mips-hpt-frequency = <175625000>; +- +- cpu@0 { +- compatible = "brcm,bmips5200"; +- device_type = "cpu"; +- reg = <0>; +- }; +- +- cpu@1 { +- compatible = "brcm,bmips5200"; +- device_type = "cpu"; +- reg = <1>; +- }; +- +- cpu@2 { +- compatible = "brcm,bmips5200"; +- device_type = "cpu"; +- reg = <2>; +- }; +- +- cpu@3 { +- compatible = "brcm,bmips5200"; +- device_type = "cpu"; +- reg = <3>; +- }; +- }; +- +- aliases { +- uart0 = &uart0; +- }; +- +- cpu_intc: interrupt-controller { +- #address-cells = <0>; +- compatible = "mti,cpu-interrupt-controller"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- clocks { +- uart_clk: uart_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <81000000>; +- }; +- +- upg_clk: upg_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <27000000>; +- }; +- }; +- +- rdb { +- #address-cells = <1>; +- #size-cells = <1>; +- +- compatible = "simple-bus"; +- ranges = <0 0x10000000 0x01000000>; +- +- periph_intc: interrupt-controller@41b500 { +- compatible = "brcm,bcm7038-l1-intc"; +- reg = <0x41b500 0x40>, <0x41b600 0x40>, +- <0x41b700 0x40>, <0x41b800 0x40>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpu_intc>; +- interrupts = <2>, <3>, <2>, <3>; +- }; +- +- sun_l2_intc: interrupt-controller@403000 { +- compatible = "brcm,l2-intc"; +- reg = <0x403000 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <52>; +- }; +- +- gisb-arb@400000 { +- compatible = "brcm,bcm7435-gisb-arb"; +- reg = <0x400000 0xdc>; +- native-endian; +- interrupt-parent = <&sun_l2_intc>; +- interrupts = <0>, <2>; +- brcm,gisb-arb-master-mask = <0xf77f>; +- brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "webcpu_0", +- "pcie_0", "bsp_0", +- "rdc_0", "raaga_0", +- "avd_1", "jtag_0", +- "svd_0", "vice_0", +- "vice_1", "raaga_1", +- "scpu"; +- }; +- +- upg_irq0_intc: interrupt-controller@406780 { +- compatible = "brcm,bcm7120-l2-intc"; +- reg = <0x406780 0x8>; +- +- brcm,int-map-mask = <0x44>, <0x7000000>; +- brcm,int-fwd-mask = <0x70000>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <60>, <58>; +- interrupt-names = "upg_main", "upg_bsc"; +- }; +- +- upg_aon_irq0_intc: interrupt-controller@409480 { +- compatible = "brcm,bcm7120-l2-intc"; +- reg = <0x409480 0x8>; +- +- brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>; +- brcm,int-fwd-mask = <0>; +- brcm,irq-can-wake; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&periph_intc>; +- interrupts = <61>, <59>, <64>; +- interrupt-names = "upg_main_aon", "upg_bsc_aon", +- "upg_spi"; +- }; +- +- sun_top_ctrl: syscon@404000 { +- compatible = "brcm,bcm7425-sun-top-ctrl", "syscon"; +- reg = <0x404000 0x51c>; +- native-endian; +- }; +- +- reboot { +- compatible = "brcm,brcmstb-reboot"; +- syscon = <&sun_top_ctrl 0x304 0x308>; +- }; +- +- uart0: serial@406b00 { +- compatible = "ns16550a"; +- reg = <0x406b00 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- interrupt-parent = <&periph_intc>; +- interrupts = <66>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart1: serial@406b40 { +- compatible = "ns16550a"; +- reg = <0x406b40 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- interrupt-parent = <&periph_intc>; +- interrupts = <67>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart2: serial@406b80 { +- compatible = "ns16550a"; +- reg = <0x406b80 0x20>; +- reg-io-width = <0x4>; +- reg-shift = <0x2>; +- interrupt-parent = <&periph_intc>; +- interrupts = <68>; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- bsca: i2c@406300 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406300 0x58>; +- interrupts = <26>; +- interrupt-names = "upg_bsca"; +- status = "disabled"; +- }; +- +- bscb: i2c@409400 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_aon_irq0_intc>; +- reg = <0x409400 0x58>; +- interrupts = <28>; +- interrupt-names = "upg_bscb"; +- status = "disabled"; +- }; +- +- bscc: i2c@406200 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406200 0x58>; +- interrupts = <24>; +- interrupt-names = "upg_bscc"; +- status = "disabled"; +- }; +- +- bscd: i2c@406280 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_irq0_intc>; +- reg = <0x406280 0x58>; +- interrupts = <25>; +- interrupt-names = "upg_bscd"; +- status = "disabled"; +- }; +- +- bsce: i2c@409180 { +- clock-frequency = <390000>; +- compatible = "brcm,brcmstb-i2c"; +- interrupt-parent = <&upg_aon_irq0_intc>; +- reg = <0x409180 0x58>; +- interrupts = <27>; +- interrupt-names = "upg_bsce"; +- status = "disabled"; +- }; +- +- pwma: pwm@406580 { +- compatible = "brcm,bcm7038-pwm"; +- reg = <0x406580 0x28>; +- #pwm-cells = <2>; +- clocks = <&upg_clk>; +- status = "disabled"; +- }; +- +- pwmb: pwm@406800 { +- compatible = "brcm,bcm7038-pwm"; +- reg = <0x406800 0x28>; +- #pwm-cells = <2>; +- clocks = <&upg_clk>; +- status = "disabled"; +- }; +- +- watchdog: watchdog@4067e8 { +- clocks = <&upg_clk>; +- compatible = "brcm,bcm7038-wdt"; +- reg = <0x4067e8 0x14>; +- status = "disabled"; +- }; +- +- aon_pm_l2_intc: interrupt-controller@408440 { +- compatible = "brcm,l2-intc"; +- reg = <0x408440 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <54>; +- brcm,irq-can-wake; +- }; +- +- aon_ctrl: syscon@408000 { +- compatible = "brcm,brcmstb-aon-ctrl"; +- reg = <0x408000 0x100>, <0x408200 0x200>; +- reg-names = "aon-ctrl", "aon-sram"; +- }; +- +- timers: timer@4067c0 { +- compatible = "brcm,brcmstb-timers"; +- reg = <0x4067c0 0x40>; +- }; +- +- upg_gio: gpio@406700 { +- compatible = "brcm,brcmstb-gpio"; +- reg = <0x406700 0x80>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupt-parent = <&upg_irq0_intc>; +- interrupts = <6>; +- brcm,gpio-bank-widths = <32 32 32 21>; +- }; +- +- upg_gio_aon: gpio@4094c0 { +- compatible = "brcm,brcmstb-gpio"; +- reg = <0x4094c0 0x40>; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupt-parent = <&upg_aon_irq0_intc>; +- interrupts = <6>; +- interrupts-extended = <&upg_aon_irq0_intc 6>, +- <&aon_pm_l2_intc 5>; +- wakeup-source; +- brcm,gpio-bank-widths = <18 4>; +- }; +- +- enet0: ethernet@b80000 { +- phy-mode = "internal"; +- phy-handle = <&phy1>; +- mac-address = [ 00 10 18 36 23 1a ]; +- compatible = "brcm,genet-v3"; +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- reg = <0xb80000 0x11c88>; +- interrupts = <17>, <18>; +- interrupt-parent = <&periph_intc>; +- status = "disabled"; +- +- mdio@e14 { +- compatible = "brcm,genet-mdio-v3"; +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- reg = <0xe14 0x8>; +- +- phy1: ethernet-phy@1 { +- max-speed = <100>; +- reg = <0x1>; +- compatible = "brcm,40nm-ephy", +- "ethernet-phy-ieee802.3-c22"; +- }; +- }; +- }; +- +- ehci0: usb@480300 { +- compatible = "brcm,bcm7435-ehci", "generic-ehci"; +- reg = <0x480300 0x100>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <70>; +- status = "disabled"; +- }; +- +- ohci0: usb@480400 { +- compatible = "brcm,bcm7435-ohci", "generic-ohci"; +- reg = <0x480400 0x100>; +- native-endian; +- no-big-frame-no; +- interrupt-parent = <&periph_intc>; +- interrupts = <72>; +- status = "disabled"; +- }; +- +- ehci1: usb@480500 { +- compatible = "brcm,bcm7435-ehci", "generic-ehci"; +- reg = <0x480500 0x100>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <71>; +- status = "disabled"; +- }; +- +- ohci1: usb@480600 { +- compatible = "brcm,bcm7435-ohci", "generic-ohci"; +- reg = <0x480600 0x100>; +- native-endian; +- no-big-frame-no; +- interrupt-parent = <&periph_intc>; +- interrupts = <73>; +- status = "disabled"; +- }; +- +- ehci2: usb@490300 { +- compatible = "brcm,bcm7435-ehci", "generic-ehci"; +- reg = <0x490300 0x100>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <75>; +- status = "disabled"; +- }; +- +- ohci2: usb@490400 { +- compatible = "brcm,bcm7435-ohci", "generic-ohci"; +- reg = <0x490400 0x100>; +- native-endian; +- no-big-frame-no; +- interrupt-parent = <&periph_intc>; +- interrupts = <77>; +- status = "disabled"; +- }; +- +- ehci3: usb@490500 { +- compatible = "brcm,bcm7435-ehci", "generic-ehci"; +- reg = <0x490500 0x100>; +- native-endian; +- interrupt-parent = <&periph_intc>; +- interrupts = <76>; +- status = "disabled"; +- }; +- +- ohci3: usb@490600 { +- compatible = "brcm,bcm7435-ohci", "generic-ohci"; +- reg = <0x490600 0x100>; +- native-endian; +- no-big-frame-no; +- interrupt-parent = <&periph_intc>; +- interrupts = <78>; +- status = "disabled"; +- }; +- +- hif_l2_intc: interrupt-controller@41b000 { +- compatible = "brcm,l2-intc"; +- reg = <0x41b000 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <24>; +- }; +- +- nand: nand@41c800 { +- compatible = "brcm,brcmnand-v6.2", "brcm,brcmnand"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg-names = "nand", "flash-dma"; +- reg = <0x41c800 0x600>, <0x41d000 0x100>; +- interrupt-parent = <&hif_l2_intc>; +- interrupts = <24>, <4>; +- status = "disabled"; +- }; +- +- sata: sata@181000 { +- compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; +- reg-names = "ahci", "top-ctrl"; +- reg = <0x181000 0xa9c>, <0x180020 0x1c>; +- interrupt-parent = <&periph_intc>; +- interrupts = <45>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- sata0: sata-port@0 { +- reg = <0>; +- phys = <&sata_phy0>; +- }; +- +- sata1: sata-port@1 { +- reg = <1>; +- phys = <&sata_phy1>; +- }; +- }; +- +- sata_phy: sata-phy@180100 { +- compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3"; +- reg = <0x180100 0x0eff>; +- reg-names = "phy"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- sata_phy0: sata-phy@0 { +- reg = <0>; +- #phy-cells = <0>; +- }; +- +- sata_phy1: sata-phy@1 { +- reg = <1>; +- #phy-cells = <0>; +- }; +- }; +- +- sdhci0: sdhci@41a000 { +- compatible = "brcm,bcm7425-sdhci"; +- reg = <0x41a000 0x100>; +- interrupt-parent = <&periph_intc>; +- interrupts = <47>; +- sd-uhs-sdr50; +- mmc-hs200-1_8v; +- status = "disabled"; +- }; +- +- sdhci1: sdhci@41a200 { +- compatible = "brcm,bcm7425-sdhci"; +- reg = <0x41a200 0x100>; +- interrupt-parent = <&periph_intc>; +- interrupts = <48>; +- sd-uhs-sdr50; +- mmc-hs200-1_8v; +- status = "disabled"; +- }; +- +- spi_l2_intc: interrupt-controller@41bd00 { +- compatible = "brcm,l2-intc"; +- reg = <0x41bd00 0x30>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&periph_intc>; +- interrupts = <25>; +- }; +- +- qspi: spi@41d200 { +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- compatible = "brcm,spi-bcm-qspi", +- "brcm,spi-brcmstb-qspi"; +- clocks = <&upg_clk>; +- reg = <0x41a920 0x4 0x41d400 0x188 0x41d200 0x50>; +- reg-names = "cs_reg", "hif_mspi", "bspi"; +- interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>; +- interrupt-parent = <&spi_l2_intc>; +- interrupt-names = "spi_lr_fullness_reached", +- "spi_lr_session_aborted", +- "spi_lr_impatient", +- "spi_lr_session_done", +- "spi_lr_overread", +- "mspi_done", +- "mspi_halted"; +- status = "disabled"; +- }; +- +- mspi: spi@409200 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "brcm,spi-bcm-qspi", +- "brcm,spi-brcmstb-mspi"; +- clocks = <&upg_clk>; +- reg = <0x409200 0x180>; +- reg-names = "mspi"; +- interrupts = <0x14>; +- interrupt-parent = <&upg_aon_irq0_intc>; +- interrupt-names = "mspi_done"; +- status = "disabled"; +- }; +- +- waketimer: waketimer@409580 { +- compatible = "brcm,brcmstb-waketimer"; +- reg = <0x409580 0x14>; +- interrupts = <0x3>; +- interrupt-parent = <&aon_pm_l2_intc>; +- interrupt-names = "timer"; +- clocks = <&upg_clk>; +- status = "disabled"; +- }; +- }; +- +- memory_controllers { +- compatible = "simple-bus"; +- ranges = <0x0 0x103b0000 0x1a000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memory-controller@0 { +- compatible = "brcm,brcmstb-memc", "simple-bus"; +- ranges = <0x0 0x0 0xa000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memc-arb@1000 { +- compatible = "brcm,brcmstb-memc-arb"; +- reg = <0x1000 0x248>; +- }; +- +- memc-ddr@2000 { +- compatible = "brcm,brcmstb-memc-ddr"; +- reg = <0x2000 0x300>; +- }; +- +- ddr-phy@6000 { +- compatible = "brcm,brcmstb-ddr-phy"; +- reg = <0x6000 0xc8>; +- }; +- +- shimphy@8000 { +- compatible = "brcm,brcmstb-ddr-shimphy"; +- reg = <0x8000 0x13c>; +- }; +- }; +- +- memory-controller@1 { +- compatible = "brcm,brcmstb-memc", "simple-bus"; +- ranges = <0x0 0x10000 0xa000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- memc-arb@1000 { +- compatible = "brcm,brcmstb-memc-arb"; +- reg = <0x1000 0x248>; +- }; +- +- memc-ddr@2000 { +- compatible = "brcm,brcmstb-memc-ddr"; +- reg = <0x2000 0x300>; +- }; +- +- ddr-phy@6000 { +- compatible = "brcm,brcmstb-ddr-phy"; +- reg = <0x6000 0xc8>; +- }; +- +- shimphy@8000 { +- compatible = "brcm,brcmstb-ddr-shimphy"; +- reg = <0x8000 0x13c>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm93384wvg.dts b/scripts/dtc/include-prefixes/mips/brcm/bcm93384wvg.dts +deleted file mode 100644 +index 7d3f181b8980..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm93384wvg.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "bcm3384_zephyr.dtsi" +- +-/ { +- compatible = "brcm,bcm93384wvg", "brcm,bcm3384"; +- model = "Broadcom BCM93384WVG"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm93384wvg_viper.dts b/scripts/dtc/include-prefixes/mips/brcm/bcm93384wvg_viper.dts +deleted file mode 100644 +index f845faa0d682..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm93384wvg_viper.dts ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "bcm3384_viper.dtsi" +- +-/ { +- compatible = "brcm,bcm93384wvg-viper", "brcm,bcm3384-viper"; +- model = "Broadcom BCM93384WVG-viper"; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm96368mvwg.dts b/scripts/dtc/include-prefixes/mips/brcm/bcm96368mvwg.dts +deleted file mode 100644 +index f5e955085308..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm96368mvwg.dts ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "bcm6368.dtsi" +- +-/ { +- compatible = "brcm,bcm96368mvwg", "brcm,bcm6368"; +- model = "Broadcom BCM96368MVWG"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x04000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-/* FIXME: need to set up USB_CTRL registers first */ +-&ehci { +- status = "disabled"; +-}; +- +-&ohci { +- status = "disabled"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm97125cbmb.dts b/scripts/dtc/include-prefixes/mips/brcm/bcm97125cbmb.dts +deleted file mode 100644 +index bda5f796251a..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm97125cbmb.dts ++++ /dev/null +@@ -1,68 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "bcm7125.dtsi" +- +-/ { +- compatible = "brcm,bcm97125cbmb", "brcm,bcm7125"; +- model = "Broadcom BCM97125CBMB"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&bsca { +- status = "okay"; +-}; +- +-&bscb { +- status = "okay"; +-}; +- +-&bscc { +- status = "okay"; +-}; +- +-&bscd { +- status = "okay"; +-}; +- +-&pwma { +- status = "okay"; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-/* FIXME: USB is wonky; disable it for now */ +-&ehci0 { +- status = "disabled"; +-}; +- +-&ohci0 { +- status = "disabled"; +-}; +- +-&mspi { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm97346dbsmb.dts b/scripts/dtc/include-prefixes/mips/brcm/bcm97346dbsmb.dts +deleted file mode 100644 +index 9f73735e815c..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm97346dbsmb.dts ++++ /dev/null +@@ -1,124 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "bcm7346.dtsi" +-#include "bcm97xxx-nand-cs1-bch24.dtsi" +- +-/ { +- compatible = "brcm,bcm97346dbsmb", "brcm,bcm7346"; +- model = "Broadcom BCM97346DBSMB"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>, <0x20000000 0x30000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&bsca { +- status = "okay"; +-}; +- +-&bscb { +- status = "okay"; +-}; +- +-&bscc { +- status = "okay"; +-}; +- +-&bscd { +- status = "okay"; +-}; +- +-&bsce { +- status = "okay"; +-}; +- +-&pwma { +- status = "okay"; +-}; +- +-&pwmb { +- status = "okay"; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-&enet0 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-&ehci3 { +- status = "okay"; +-}; +- +-&ohci3 { +- status = "okay"; +-}; +- +-&nand { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&sata_phy { +- status = "okay"; +-}; +- +-&sdhci0 { +- status = "okay"; +-}; +- +-&mspi { +- status = "okay"; +-}; +- +-&waketimer { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm97358svmb.dts b/scripts/dtc/include-prefixes/mips/brcm/bcm97358svmb.dts +deleted file mode 100644 +index 522f2c40d6e6..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm97358svmb.dts ++++ /dev/null +@@ -1,116 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "bcm7358.dtsi" +-#include "bcm97xxx-nand-cs1-bch4.dtsi" +- +-/ { +- compatible = "brcm,bcm97358svmb", "brcm,bcm7358"; +- model = "Broadcom BCM97358SVMB"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&bsca { +- status = "okay"; +-}; +- +-&bscb { +- status = "okay"; +-}; +- +-&bscc { +- status = "okay"; +-}; +- +-&bscd { +- status = "okay"; +-}; +- +-&pwma { +- status = "okay"; +-}; +- +-&pwmb { +- status = "okay"; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-&enet0 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&nand { +- status = "okay"; +-}; +- +-&qspi { +- status = "okay"; +- +- m25p80@0 { +- compatible = "m25p80"; +- reg = <0>; +- spi-max-frequency = <40000000>; +- spi-cpol; +- spi-cpha; +- use-bspi; +- m25p,fast-read; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- flash0.cfe@0 { +- reg = <0x0 0x200000>; +- }; +- +- flash0.mac@200000 { +- reg = <0x200000 0x40000>; +- }; +- +- flash0.nvram@240000 { +- reg = <0x240000 0x10000>; +- }; +- }; +- }; +-}; +- +-&mspi { +- status = "okay"; +-}; +- +-&waketimer { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm97360svmb.dts b/scripts/dtc/include-prefixes/mips/brcm/bcm97360svmb.dts +deleted file mode 100644 +index 01f215b08dba..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm97360svmb.dts ++++ /dev/null +@@ -1,119 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "bcm7360.dtsi" +- +-/ { +- compatible = "brcm,bcm97360svmb", "brcm,bcm7360"; +- model = "Broadcom BCM97360SVMB"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&bsca { +- status = "okay"; +-}; +- +-&bscb { +- status = "okay"; +-}; +- +-&bscc { +- status = "okay"; +-}; +- +-&bscd { +- status = "okay"; +-}; +- +-&pwma { +- status = "okay"; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-&enet0 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&sata_phy { +- status = "okay"; +-}; +- +-&sdhci0 { +- status = "okay"; +-}; +- +-&qspi { +- status = "okay"; +- +- m25p80@0 { +- compatible = "m25p80"; +- reg = <0>; +- spi-max-frequency = <40000000>; +- spi-cpol; +- spi-cpha; +- use-bspi; +- m25p,fast-read; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- flash0.cfe@0 { +- reg = <0x0 0x200000>; +- }; +- +- flash0.mac@200000 { +- reg = <0x200000 0x40000>; +- }; +- +- flash0.nvram@240000 { +- reg = <0x240000 0x10000>; +- }; +- }; +- }; +-}; +- +-&mspi { +- status = "okay"; +-}; +- +-&waketimer { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm97362svmb.dts b/scripts/dtc/include-prefixes/mips/brcm/bcm97362svmb.dts +deleted file mode 100644 +index 97aeb51b6831..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm97362svmb.dts ++++ /dev/null +@@ -1,88 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "bcm7362.dtsi" +-#include "bcm97xxx-nand-cs1-bch4.dtsi" +- +-/ { +- compatible = "brcm,bcm97362svmb", "brcm,bcm7362"; +- model = "Broadcom BCM97362SVMB"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>, <0x20000000 0x30000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&bsca { +- status = "okay"; +-}; +- +-&bscb { +- status = "okay"; +-}; +- +-&bscd { +- status = "okay"; +-}; +- +-&pwma { +- status = "okay"; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-&enet0 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&nand { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&sata_phy { +- status = "okay"; +-}; +- +-&sdhci0 { +- status = "okay"; +-}; +- +-&mspi { +- status = "okay"; +-}; +- +-&waketimer { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm97420c.dts b/scripts/dtc/include-prefixes/mips/brcm/bcm97420c.dts +deleted file mode 100644 +index cc70c2dd4d85..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm97420c.dts ++++ /dev/null +@@ -1,90 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "bcm7420.dtsi" +- +-/ { +- compatible = "brcm,bcm97420c", "brcm,bcm7420"; +- model = "Broadcom BCM97420C"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>, +- <0x20000000 0x30000000>, +- <0x60000000 0x10000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&bsca { +- status = "okay"; +-}; +- +-&bscb { +- status = "okay"; +-}; +- +-&bscc { +- status = "okay"; +-}; +- +-&bscd { +- status = "okay"; +-}; +- +-&bsce { +- status = "okay"; +-}; +- +-&pwma { +- status = "okay"; +-}; +- +-&pwmb { +- status = "okay"; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-/* FIXME: MAC driver comes up but cannot attach to PHY */ +-&enet0 { +- status = "disabled"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&mspi { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm97425svmb.dts b/scripts/dtc/include-prefixes/mips/brcm/bcm97425svmb.dts +deleted file mode 100644 +index 9efecfe1e05c..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm97425svmb.dts ++++ /dev/null +@@ -1,154 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "bcm7425.dtsi" +-#include "bcm97xxx-nand-cs1-bch24.dtsi" +- +-/ { +- compatible = "brcm,bcm97425svmb", "brcm,bcm7425"; +- model = "Broadcom BCM97425SVMB"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>, +- <0x20000000 0x30000000>, +- <0x90000000 0x40000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&bsca { +- status = "okay"; +-}; +- +-&bscb { +- status = "okay"; +-}; +- +-&bscc { +- status = "okay"; +-}; +- +-&bscd { +- status = "okay"; +-}; +- +-&bsce { +- status = "okay"; +-}; +- +-&pwma { +- status = "okay"; +-}; +- +-&pwmb { +- status = "okay"; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-&enet0 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-&ehci3 { +- status = "okay"; +-}; +- +-&ohci3 { +- status = "okay"; +-}; +- +-&nand { +- status = "okay"; +-}; +- +-&sdhci0 { +- status = "okay"; +-}; +- +-&sdhci1 { +- status = "okay"; +-}; +- +-&qspi { +- status = "okay"; +- +- m25p80@0 { +- compatible = "m25p80"; +- reg = <0>; +- spi-max-frequency = <40000000>; +- spi-cpol; +- spi-cpha; +- use-bspi; +- m25p,fast-read; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- flash0.cfe@0 { +- reg = <0x0 0x200000>; +- }; +- +- flash0.mac@200000 { +- reg = <0x200000 0x40000>; +- }; +- +- flash0.nvram@240000 { +- reg = <0x240000 0x10000>; +- }; +- }; +- }; +-}; +- +-&mspi { +- status = "okay"; +-}; +- +-&waketimer { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm97435svmb.dts b/scripts/dtc/include-prefixes/mips/brcm/bcm97435svmb.dts +deleted file mode 100644 +index b653c6ff74b5..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm97435svmb.dts ++++ /dev/null +@@ -1,130 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "bcm7435.dtsi" +-#include "bcm97xxx-nand-cs1-bch24.dtsi" +- +-/ { +- compatible = "brcm,bcm97435svmb", "brcm,bcm7435"; +- model = "Broadcom BCM97435SVMB"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>, +- <0x20000000 0x30000000>, +- <0x90000000 0x40000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&bsca { +- status = "okay"; +-}; +- +-&bscb { +- status = "okay"; +-}; +- +-&bscc { +- status = "okay"; +-}; +- +-&bscd { +- status = "okay"; +-}; +- +-&bsce { +- status = "okay"; +-}; +- +-&pwma { +- status = "okay"; +-}; +- +-&pwmb { +- status = "okay"; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-&enet0 { +- status = "okay"; +-}; +- +-&ehci0 { +- status = "okay"; +-}; +- +-&ohci0 { +- status = "okay"; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-&ehci3 { +- status = "okay"; +-}; +- +-&ohci3 { +- status = "okay"; +-}; +- +-&nand { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&sata_phy { +- status = "okay"; +-}; +- +-&sdhci0 { +- status = "okay"; +-}; +- +-&sdhci1 { +- status = "okay"; +-}; +- +-&mspi { +- status = "okay"; +-}; +- +-&waketimer { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm97xxx-nand-cs1-bch24.dtsi b/scripts/dtc/include-prefixes/mips/brcm/bcm97xxx-nand-cs1-bch24.dtsi +deleted file mode 100644 +index 96c30d857be4..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm97xxx-nand-cs1-bch24.dtsi ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-&nand { +- nandcs@1 { +- compatible = "brcm,nandcs"; +- reg = <1>; +- nand-on-flash-bbt; +- +- nand-ecc-strength = <24>; +- nand-ecc-step-size = <1024>; +- brcm,nand-oob-sector-size = <27>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- flash1.rootfs@0 { +- reg = <0x0 0x10000000>; +- }; +- +- flash1.kernel@10000000 { +- reg = <0x10000000 0x400000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm97xxx-nand-cs1-bch4.dtsi b/scripts/dtc/include-prefixes/mips/brcm/bcm97xxx-nand-cs1-bch4.dtsi +deleted file mode 100644 +index 7b5afefbbfab..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm97xxx-nand-cs1-bch4.dtsi ++++ /dev/null +@@ -1,26 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-&nand { +- nandcs@1 { +- compatible = "brcm,nandcs"; +- reg = <1>; +- nand-on-flash-bbt; +- +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- brcm,nand-oob-sector-size = <16>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- flash1.rootfs@0 { +- reg = <0x0 0x10000000>; +- }; +- +- flash1.kernel@10000000 { +- reg = <0x10000000 0x400000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/brcm/bcm9ejtagprb.dts b/scripts/dtc/include-prefixes/mips/brcm/bcm9ejtagprb.dts +deleted file mode 100644 +index 615d2b97770e..000000000000 +--- a/scripts/dtc/include-prefixes/mips/brcm/bcm9ejtagprb.dts ++++ /dev/null +@@ -1,23 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "bcm6328.dtsi" +- +-/ { +- compatible = "brcm,bcm9ejtagprb", "brcm,bcm6328"; +- model = "Broadcom BCM9EJTAGPRB"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/cavium-octeon/Makefile b/scripts/dtc/include-prefixes/mips/cavium-octeon/Makefile +deleted file mode 100644 +index 17aef35f311b..000000000000 +--- a/scripts/dtc/include-prefixes/mips/cavium-octeon/Makefile ++++ /dev/null +@@ -1,4 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_CAVIUM_OCTEON_SOC) += octeon_3xxx.dtb octeon_68xx.dtb +- +-obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) +diff --git a/scripts/dtc/include-prefixes/mips/cavium-octeon/dlink_dsr-1000n.dts b/scripts/dtc/include-prefixes/mips/cavium-octeon/dlink_dsr-1000n.dts +deleted file mode 100644 +index 2fdb4baad19c..000000000000 +--- a/scripts/dtc/include-prefixes/mips/cavium-octeon/dlink_dsr-1000n.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device tree source for D-Link DSR-1000N. +- * +- * Written by: Aaro Koskinen +- */ +- +-/include/ "dlink_dsr-500n-1000n.dtsi" +-#include +- +-/ { +- model = "dlink,dsr-1000n"; +- +- soc@0 { +- uart0: serial@1180000000800 { +- clock-frequency = <500000000>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- usb1 { +- label = "usb1"; +- gpios = <&gpio 9 GPIO_ACTIVE_LOW>; +- }; +- +- usb2 { +- label = "usb2"; +- gpios = <&gpio 10 GPIO_ACTIVE_LOW>; +- }; +- +- wps { +- label = "wps"; +- gpios = <&gpio 11 GPIO_ACTIVE_LOW>; +- }; +- +- wireless1 { +- label = "5g"; +- gpios = <&gpio 17 GPIO_ACTIVE_LOW>; +- }; +- +- wireless2 { +- label = "2.4g"; +- gpios = <&gpio 18 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/cavium-octeon/dlink_dsr-500n-1000n.dtsi b/scripts/dtc/include-prefixes/mips/cavium-octeon/dlink_dsr-500n-1000n.dtsi +deleted file mode 100644 +index b4acdb26a667..000000000000 +--- a/scripts/dtc/include-prefixes/mips/cavium-octeon/dlink_dsr-500n-1000n.dtsi ++++ /dev/null +@@ -1,55 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device tree source for D-Link DSR-500N/1000N (common parts). +- * +- * Written by: Aaro Koskinen +- */ +- +-/include/ "octeon_3xxx.dtsi" +- +-/ { +- soc@0 { +- smi0: mdio@1180000001800 { +- phy8: ethernet-phy@8 { +- reg = <8>; +- compatible = "ethernet-phy-ieee802.3-c22"; +- }; +- }; +- +- pip: pip@11800a0000000 { +- interface@0 { +- ethernet@0 { +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- ethernet@1 { +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- ethernet@2 { +- phy-handle = <&phy8>; +- }; +- }; +- }; +- +- twsi0: i2c@1180000001000 { +- rtc@68 { +- compatible = "dallas,ds1337"; +- reg = <0x68>; +- }; +- }; +- +- usbn: usbn@1180068000000 { +- refclk-frequency = <12000000>; +- refclk-type = "crystal"; +- }; +- }; +- +- aliases { +- pip = &pip; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/cavium-octeon/dlink_dsr-500n.dts b/scripts/dtc/include-prefixes/mips/cavium-octeon/dlink_dsr-500n.dts +deleted file mode 100644 +index e04237281b41..000000000000 +--- a/scripts/dtc/include-prefixes/mips/cavium-octeon/dlink_dsr-500n.dts ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device tree source for D-Link DSR-500N. +- * +- * Written by: Aaro Koskinen +- */ +- +-/include/ "dlink_dsr-500n-1000n.dtsi" +-#include +- +-/ { +- model = "dlink,dsr-500n"; +- compatible = "dlink,dsr-500n", "cavium,octeon-3860"; +- +- soc@0 { +- uart0: serial@1180000000800 { +- clock-frequency = <300000000>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- usb { +- gpios = <&gpio 9 GPIO_ACTIVE_LOW>; +- }; +- +- wps { +- gpios = <&gpio 11 GPIO_ACTIVE_LOW>; +- }; +- +- wireless { +- label = "2.4g"; +- gpios = <&gpio 18 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/cavium-octeon/octeon_3xxx.dts b/scripts/dtc/include-prefixes/mips/cavium-octeon/octeon_3xxx.dts +deleted file mode 100644 +index dda0559cef50..000000000000 +--- a/scripts/dtc/include-prefixes/mips/cavium-octeon/octeon_3xxx.dts ++++ /dev/null +@@ -1,406 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * OCTEON 3XXX, 5XXX, 63XX device tree skeleton. +- * +- * This device tree is pruned and patched by early boot code before +- * use. Because of this, it contains a super-set of the available +- * devices and properties. +- */ +- +-/include/ "octeon_3xxx.dtsi" +- +-/ { +- soc@0 { +- smi0: mdio@1180000001800 { +- phy0: ethernet-phy@0 { +- compatible = "marvell,88e1118"; +- marvell,reg-init = +- /* Fix rx and tx clock transition timing */ +- <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ +- /* Adjust LED drive. */ +- <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ +- /* irq, blink-activity, blink-link */ +- <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ +- reg = <0>; +- }; +- +- phy1: ethernet-phy@1 { +- compatible = "marvell,88e1118"; +- marvell,reg-init = +- /* Fix rx and tx clock transition timing */ +- <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ +- /* Adjust LED drive. */ +- <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ +- /* irq, blink-activity, blink-link */ +- <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ +- reg = <1>; +- }; +- +- phy2: ethernet-phy@2 { +- reg = <2>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- phy3: ethernet-phy@3 { +- reg = <3>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- phy4: ethernet-phy@4 { +- reg = <4>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- phy5: ethernet-phy@5 { +- reg = <5>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- +- phy6: ethernet-phy@6 { +- reg = <6>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- phy7: ethernet-phy@7 { +- reg = <7>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- phy8: ethernet-phy@8 { +- reg = <8>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- phy9: ethernet-phy@9 { +- reg = <9>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- }; +- +- smi1: mdio@1180000001900 { +- compatible = "cavium,octeon-3860-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x11800 0x00001900 0x0 0x40>; +- +- phy100: ethernet-phy@1 { +- reg = <1>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- interrupt-parent = <&gpio>; +- interrupts = <12 8>; /* Pin 12, active low */ +- }; +- phy101: ethernet-phy@2 { +- reg = <2>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- interrupt-parent = <&gpio>; +- interrupts = <12 8>; /* Pin 12, active low */ +- }; +- phy102: ethernet-phy@3 { +- reg = <3>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- interrupt-parent = <&gpio>; +- interrupts = <12 8>; /* Pin 12, active low */ +- }; +- phy103: ethernet-phy@4 { +- reg = <4>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- interrupt-parent = <&gpio>; +- interrupts = <12 8>; /* Pin 12, active low */ +- }; +- }; +- +- mix0: ethernet@1070000100000 { +- compatible = "cavium,octeon-5750-mix"; +- reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ +- <0x11800 0xE0000000 0x0 0x300>, /* AGL */ +- <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ +- <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ +- cell-index = <0>; +- interrupts = <0 62>, <1 46>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy0>; +- }; +- +- mix1: ethernet@1070000100800 { +- compatible = "cavium,octeon-5750-mix"; +- reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ +- <0x11800 0xE0000800 0x0 0x300>, /* AGL */ +- <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ +- <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ +- cell-index = <1>; +- interrupts = <1 18>, < 1 46>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy1>; +- }; +- +- pip: pip@11800a0000000 { +- interface@0 { +- ethernet@0 { +- phy-handle = <&phy2>; +- cavium,alt-phy-handle = <&phy100>; +- rx-delay = <0>; +- tx-delay = <0>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- ethernet@1 { +- phy-handle = <&phy3>; +- cavium,alt-phy-handle = <&phy101>; +- rx-delay = <0>; +- tx-delay = <0>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- ethernet@2 { +- phy-handle = <&phy4>; +- cavium,alt-phy-handle = <&phy102>; +- rx-delay = <0>; +- tx-delay = <0>; +- }; +- ethernet@3 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x3>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy5>; +- cavium,alt-phy-handle = <&phy103>; +- }; +- ethernet@4 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x4>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- ethernet@5 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x5>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- ethernet@6 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x6>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- ethernet@7 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x7>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- ethernet@8 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x8>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- ethernet@9 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x9>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- ethernet@a { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0xa>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- ethernet@b { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0xb>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- ethernet@c { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0xc>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- ethernet@d { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0xd>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- ethernet@e { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0xe>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- ethernet@f { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0xf>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- }; +- +- interface@1 { +- ethernet@0 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x0>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy6>; +- }; +- ethernet@1 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x1>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy7>; +- }; +- ethernet@2 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x2>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy8>; +- }; +- ethernet@3 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x3>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy9>; +- }; +- }; +- }; +- +- twsi0: i2c@1180000001000 { +- rtc@68 { +- compatible = "dallas,ds1337"; +- reg = <0x68>; +- }; +- tmp@4c { +- compatible = "ti,tmp421"; +- reg = <0x4c>; +- }; +- }; +- +- twsi1: i2c@1180000001200 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "cavium,octeon-3860-twsi"; +- reg = <0x11800 0x00001200 0x0 0x200>; +- interrupts = <0 59>; +- clock-frequency = <100000>; +- }; +- +- uart1: serial@1180000000c00 { +- compatible = "cavium,octeon-3860-uart","ns16550"; +- reg = <0x11800 0x00000c00 0x0 0x400>; +- clock-frequency = <0>; +- current-speed = <115200>; +- reg-shift = <3>; +- interrupts = <0 35>; +- }; +- +- uart2: serial@1180000000400 { +- compatible = "cavium,octeon-3860-uart","ns16550"; +- reg = <0x11800 0x00000400 0x0 0x400>; +- clock-frequency = <0>; +- current-speed = <115200>; +- reg-shift = <3>; +- interrupts = <1 16>; +- }; +- +- bootbus: bootbus@1180000000000 { +- led0: led-display@4,0 { +- compatible = "avago,hdsp-253x"; +- reg = <4 0x20 0x20>, <4 0 0x20>; +- }; +- +- cf0: compact-flash@5,0 { +- compatible = "cavium,ebt3000-compact-flash"; +- reg = <5 0 0x10000>, <6 0 0x10000>; +- cavium,bus-width = <16>; +- cavium,true-ide; +- cavium,dma-engine-handle = <&dma0>; +- }; +- }; +- +- uctl: uctl@118006f000000 { +- compatible = "cavium,octeon-6335-uctl"; +- reg = <0x11800 0x6f000000 0x0 0x100>; +- ranges; /* Direct mapping */ +- #address-cells = <2>; +- #size-cells = <2>; +- /* 12MHz, 24MHz and 48MHz allowed */ +- refclk-frequency = <12000000>; +- /* Either "crystal" or "external" */ +- refclk-type = "crystal"; +- +- ehci@16f0000000000 { +- compatible = "cavium,octeon-6335-ehci","usb-ehci"; +- reg = <0x16f00 0x00000000 0x0 0x100>; +- interrupts = <0 56>; +- big-endian-regs; +- }; +- ohci@16f0000000400 { +- compatible = "cavium,octeon-6335-ohci","usb-ohci"; +- reg = <0x16f00 0x00000400 0x0 0x100>; +- interrupts = <0 56>; +- big-endian-regs; +- }; +- }; +- +- usbn: usbn@1180068000000 { +- /* 12MHz, 24MHz and 48MHz allowed */ +- refclk-frequency = <12000000>; +- /* Either "crystal" or "external" */ +- refclk-type = "crystal"; +- }; +- }; +- +- aliases { +- mix0 = &mix0; +- mix1 = &mix1; +- pip = &pip; +- smi0 = &smi0; +- smi1 = &smi1; +- twsi0 = &twsi0; +- twsi1 = &twsi1; +- uart0 = &uart0; +- uart1 = &uart1; +- uart2 = &uart2; +- flash0 = &flash0; +- cf0 = &cf0; +- uctl = &uctl; +- usbn = &usbn; +- led0 = &led0; +- }; +- }; +diff --git a/scripts/dtc/include-prefixes/mips/cavium-octeon/octeon_3xxx.dtsi b/scripts/dtc/include-prefixes/mips/cavium-octeon/octeon_3xxx.dtsi +deleted file mode 100644 +index 3c296623d870..000000000000 +--- a/scripts/dtc/include-prefixes/mips/cavium-octeon/octeon_3xxx.dtsi ++++ /dev/null +@@ -1,232 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* OCTEON 3XXX DTS common parts. */ +- +-/dts-v1/; +- +-/ { +- compatible = "cavium,octeon-3860"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&ciu>; +- +- soc@0 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; /* Direct mapping */ +- +- ciu: interrupt-controller@1070000000000 { +- compatible = "cavium,octeon-3860-ciu"; +- interrupt-controller; +- /* Interrupts are specified by two parts: +- * 1) Controller register (0 or 1) +- * 2) Bit within the register (0..63) +- */ +- #interrupt-cells = <2>; +- reg = <0x10700 0x00000000 0x0 0x7000>; +- }; +- +- gpio: gpio-controller@1070000000800 { +- #gpio-cells = <2>; +- compatible = "cavium,octeon-3860-gpio"; +- reg = <0x10700 0x00000800 0x0 0x100>; +- gpio-controller; +- /* Interrupts are specified by two parts: +- * 1) GPIO pin number (0..15) +- * 2) Triggering (1 - edge rising +- * 2 - edge falling +- * 4 - level active high +- * 8 - level active low) +- */ +- interrupt-controller; +- #interrupt-cells = <2>; +- /* The GPIO pin connect to 16 consecutive CUI bits */ +- interrupts = <0 16>, <0 17>, <0 18>, <0 19>, +- <0 20>, <0 21>, <0 22>, <0 23>, +- <0 24>, <0 25>, <0 26>, <0 27>, +- <0 28>, <0 29>, <0 30>, <0 31>; +- }; +- +- smi0: mdio@1180000001800 { +- compatible = "cavium,octeon-3860-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x11800 0x00001800 0x0 0x40>; +- }; +- +- pip: pip@11800a0000000 { +- compatible = "cavium,octeon-3860-pip"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x11800 0xa0000000 0x0 0x2000>; +- +- interface@0 { +- compatible = "cavium,octeon-3860-pip-interface"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; /* interface */ +- +- ethernet@0 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x0>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- ethernet@1 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x1>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- ethernet@2 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x2>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- }; +- +- interface@1 { +- compatible = "cavium,octeon-3860-pip-interface"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; /* interface */ +- }; +- }; +- +- twsi0: i2c@1180000001000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "cavium,octeon-3860-twsi"; +- reg = <0x11800 0x00001000 0x0 0x200>; +- interrupts = <0 45>; +- clock-frequency = <100000>; +- }; +- +- uart0: serial@1180000000800 { +- compatible = "cavium,octeon-3860-uart","ns16550"; +- reg = <0x11800 0x00000800 0x0 0x400>; +- clock-frequency = <0>; +- current-speed = <115200>; +- reg-shift = <3>; +- interrupts = <0 34>; +- }; +- +- bootbus: bootbus@1180000000000 { +- compatible = "cavium,octeon-3860-bootbus"; +- reg = <0x11800 0x00000000 0x0 0x200>; +- /* The chip select number and offset */ +- #address-cells = <2>; +- /* The size of the chip select region */ +- #size-cells = <1>; +- ranges = <0 0 0x0 0x1f400000 0xc00000>, +- <1 0 0x10000 0x30000000 0>, +- <2 0 0x10000 0x40000000 0>, +- <3 0 0x10000 0x50000000 0>, +- <4 0 0x0 0x1d020000 0x10000>, +- <5 0 0x0 0x1d040000 0x10000>, +- <6 0 0x0 0x1d050000 0x10000>, +- <7 0 0x10000 0x90000000 0>; +- +- cavium,cs-config@0 { +- compatible = "cavium,octeon-3860-bootbus-config"; +- cavium,cs-index = <0>; +- cavium,t-adr = <20>; +- cavium,t-ce = <60>; +- cavium,t-oe = <60>; +- cavium,t-we = <45>; +- cavium,t-rd-hld = <35>; +- cavium,t-wr-hld = <45>; +- cavium,t-pause = <0>; +- cavium,t-wait = <0>; +- cavium,t-page = <35>; +- cavium,t-rd-dly = <0>; +- +- cavium,pages = <0>; +- cavium,bus-width = <8>; +- }; +- cavium,cs-config@4 { +- compatible = "cavium,octeon-3860-bootbus-config"; +- cavium,cs-index = <4>; +- cavium,t-adr = <320>; +- cavium,t-ce = <320>; +- cavium,t-oe = <320>; +- cavium,t-we = <320>; +- cavium,t-rd-hld = <320>; +- cavium,t-wr-hld = <320>; +- cavium,t-pause = <320>; +- cavium,t-wait = <320>; +- cavium,t-page = <320>; +- cavium,t-rd-dly = <0>; +- +- cavium,pages = <0>; +- cavium,bus-width = <8>; +- }; +- cavium,cs-config@5 { +- compatible = "cavium,octeon-3860-bootbus-config"; +- cavium,cs-index = <5>; +- cavium,t-adr = <5>; +- cavium,t-ce = <300>; +- cavium,t-oe = <125>; +- cavium,t-we = <150>; +- cavium,t-rd-hld = <100>; +- cavium,t-wr-hld = <30>; +- cavium,t-pause = <0>; +- cavium,t-wait = <30>; +- cavium,t-page = <320>; +- cavium,t-rd-dly = <0>; +- +- cavium,pages = <0>; +- cavium,bus-width = <16>; +- }; +- cavium,cs-config@6 { +- compatible = "cavium,octeon-3860-bootbus-config"; +- cavium,cs-index = <6>; +- cavium,t-adr = <5>; +- cavium,t-ce = <300>; +- cavium,t-oe = <270>; +- cavium,t-we = <150>; +- cavium,t-rd-hld = <100>; +- cavium,t-wr-hld = <70>; +- cavium,t-pause = <0>; +- cavium,t-wait = <0>; +- cavium,t-page = <320>; +- cavium,t-rd-dly = <0>; +- +- cavium,pages = <0>; +- cavium,wait-mode; +- cavium,bus-width = <16>; +- }; +- +- flash0: nor@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x800000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- }; +- +- dma0: dma-engine@1180000000100 { +- compatible = "cavium,octeon-5750-bootbus-dma"; +- reg = <0x11800 0x00000100 0x0 0x8>; +- interrupts = <0 63>; +- }; +- +- dma1: dma-engine@1180000000108 { +- compatible = "cavium,octeon-5750-bootbus-dma"; +- reg = <0x11800 0x00000108 0x0 0x8>; +- interrupts = <0 63>; +- }; +- +- usbn: usbn@1180068000000 { +- compatible = "cavium,octeon-5750-usbn"; +- reg = <0x11800 0x68000000 0x0 0x1000>; +- ranges; /* Direct mapping */ +- #address-cells = <2>; +- #size-cells = <2>; +- +- usbc@16f0010000000 { +- compatible = "cavium,octeon-5750-usbc"; +- reg = <0x16f00 0x10000000 0x0 0x80000>; +- interrupts = <0 56>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/cavium-octeon/octeon_68xx.dts b/scripts/dtc/include-prefixes/mips/cavium-octeon/octeon_68xx.dts +deleted file mode 100644 +index 3d0acbb2e15f..000000000000 +--- a/scripts/dtc/include-prefixes/mips/cavium-octeon/octeon_68xx.dts ++++ /dev/null +@@ -1,626 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-/* +- * OCTEON 68XX device tree skeleton. +- * +- * This device tree is pruned and patched by early boot code before +- * use. Because of this, it contains a super-set of the available +- * devices and properties. +- */ +-/ { +- compatible = "cavium,octeon-6880"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&ciu2>; +- +- soc@0 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; /* Direct mapping */ +- +- ciu2: interrupt-controller@1070100000000 { +- compatible = "cavium,octeon-6880-ciu2"; +- interrupt-controller; +- /* Interrupts are specified by two parts: +- * 1) Controller register (0 or 7) +- * 2) Bit within the register (0..63) +- */ +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x10701 0x00000000 0x0 0x4000000>; +- }; +- +- gpio: gpio-controller@1070000000800 { +- #gpio-cells = <2>; +- compatible = "cavium,octeon-3860-gpio"; +- reg = <0x10700 0x00000800 0x0 0x100>; +- gpio-controller; +- /* Interrupts are specified by two parts: +- * 1) GPIO pin number (0..15) +- * 2) Triggering (1 - edge rising +- * 2 - edge falling +- * 4 - level active high +- * 8 - level active low) +- */ +- interrupt-controller; +- #interrupt-cells = <2>; +- /* The GPIO pins connect to 16 consecutive CUI bits */ +- interrupts = <7 0>, <7 1>, <7 2>, <7 3>, +- <7 4>, <7 5>, <7 6>, <7 7>, +- <7 8>, <7 9>, <7 10>, <7 11>, +- <7 12>, <7 13>, <7 14>, <7 15>; +- }; +- +- smi0: mdio@1180000003800 { +- compatible = "cavium,octeon-3860-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x11800 0x00003800 0x0 0x40>; +- +- phy0: ethernet-phy@6 { +- compatible = "marvell,88e1118"; +- marvell,reg-init = +- /* Fix rx and tx clock transition timing */ +- <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ +- /* Adjust LED drive. */ +- <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ +- /* irq, blink-activity, blink-link */ +- <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ +- reg = <6>; +- }; +- +- phy1: ethernet-phy@1 { +- cavium,qlm-trim = "4,sgmii"; +- reg = <1>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- phy2: ethernet-phy@2 { +- cavium,qlm-trim = "4,sgmii"; +- reg = <2>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- phy3: ethernet-phy@3 { +- cavium,qlm-trim = "4,sgmii"; +- reg = <3>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- phy4: ethernet-phy@4 { +- cavium,qlm-trim = "4,sgmii"; +- reg = <4>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- }; +- +- smi1: mdio@1180000003880 { +- compatible = "cavium,octeon-3860-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x11800 0x00003880 0x0 0x40>; +- +- phy41: ethernet-phy@1 { +- cavium,qlm-trim = "0,sgmii"; +- reg = <1>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- phy42: ethernet-phy@2 { +- cavium,qlm-trim = "0,sgmii"; +- reg = <2>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- phy43: ethernet-phy@3 { +- cavium,qlm-trim = "0,sgmii"; +- reg = <3>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- phy44: ethernet-phy@4 { +- cavium,qlm-trim = "0,sgmii"; +- reg = <4>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- }; +- +- smi2: mdio@1180000003900 { +- compatible = "cavium,octeon-3860-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x11800 0x00003900 0x0 0x40>; +- +- phy21: ethernet-phy@1 { +- cavium,qlm-trim = "2,sgmii"; +- reg = <1>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- phy22: ethernet-phy@2 { +- cavium,qlm-trim = "2,sgmii"; +- reg = <2>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- phy23: ethernet-phy@3 { +- cavium,qlm-trim = "2,sgmii"; +- reg = <3>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- phy24: ethernet-phy@4 { +- cavium,qlm-trim = "2,sgmii"; +- reg = <4>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- }; +- +- smi3: mdio@1180000003980 { +- compatible = "cavium,octeon-3860-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x11800 0x00003980 0x0 0x40>; +- +- phy11: ethernet-phy@1 { +- cavium,qlm-trim = "3,sgmii"; +- reg = <1>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- phy12: ethernet-phy@2 { +- cavium,qlm-trim = "3,sgmii"; +- reg = <2>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- phy13: ethernet-phy@3 { +- cavium,qlm-trim = "3,sgmii"; +- reg = <3>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- phy14: ethernet-phy@4 { +- cavium,qlm-trim = "3,sgmii"; +- reg = <4>; +- compatible = "marvell,88e1149r"; +- marvell,reg-init = <3 0x10 0 0x5777>, +- <3 0x11 0 0x00aa>, +- <3 0x12 0 0x4105>, +- <3 0x13 0 0x0a60>; +- }; +- }; +- +- mix0: ethernet@1070000100000 { +- compatible = "cavium,octeon-5750-mix"; +- reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ +- <0x11800 0xE0000000 0x0 0x300>, /* AGL */ +- <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ +- <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ +- cell-index = <0>; +- interrupts = <6 40>, <6 32>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy0>; +- }; +- +- pip: pip@11800a0000000 { +- compatible = "cavium,octeon-3860-pip"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x11800 0xa0000000 0x0 0x2000>; +- +- interface@4 { +- compatible = "cavium,octeon-3860-pip-interface"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x4>; /* interface */ +- +- ethernet@0 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x0>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy1>; +- }; +- ethernet@1 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x1>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy2>; +- }; +- ethernet@2 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x2>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy3>; +- }; +- ethernet@3 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x3>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy4>; +- }; +- }; +- +- interface@3 { +- compatible = "cavium,octeon-3860-pip-interface"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3>; /* interface */ +- +- ethernet@0 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x0>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy11>; +- }; +- ethernet@1 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x1>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy12>; +- }; +- ethernet@2 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x2>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy13>; +- }; +- ethernet@3 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x3>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy14>; +- }; +- }; +- +- interface@2 { +- compatible = "cavium,octeon-3860-pip-interface"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; /* interface */ +- +- ethernet@0 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x0>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy21>; +- }; +- ethernet@1 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x1>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy22>; +- }; +- ethernet@2 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x2>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy23>; +- }; +- ethernet@3 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x3>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy24>; +- }; +- }; +- +- interface@1 { +- compatible = "cavium,octeon-3860-pip-interface"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x1>; /* interface */ +- +- ethernet@0 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x0>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- }; +- +- interface@0 { +- compatible = "cavium,octeon-3860-pip-interface"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0>; /* interface */ +- +- ethernet@0 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x0>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy41>; +- }; +- ethernet@1 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x1>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy42>; +- }; +- ethernet@2 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x2>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy43>; +- }; +- ethernet@3 { +- compatible = "cavium,octeon-3860-pip-port"; +- reg = <0x3>; /* Port */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-handle = <&phy44>; +- }; +- }; +- }; +- +- twsi0: i2c@1180000001000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "cavium,octeon-3860-twsi"; +- reg = <0x11800 0x00001000 0x0 0x200>; +- interrupts = <3 32>; +- clock-frequency = <100000>; +- +- rtc@68 { +- compatible = "dallas,ds1337"; +- reg = <0x68>; +- }; +- tmp@4c { +- compatible = "ti,tmp421"; +- reg = <0x4c>; +- }; +- }; +- +- twsi1: i2c@1180000001200 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "cavium,octeon-3860-twsi"; +- reg = <0x11800 0x00001200 0x0 0x200>; +- interrupts = <3 33>; +- clock-frequency = <100000>; +- }; +- +- uart0: serial@1180000000800 { +- compatible = "cavium,octeon-3860-uart","ns16550"; +- reg = <0x11800 0x00000800 0x0 0x400>; +- clock-frequency = <0>; +- current-speed = <115200>; +- reg-shift = <3>; +- interrupts = <3 36>; +- }; +- +- uart1: serial@1180000000c00 { +- compatible = "cavium,octeon-3860-uart","ns16550"; +- reg = <0x11800 0x00000c00 0x0 0x400>; +- clock-frequency = <0>; +- current-speed = <115200>; +- reg-shift = <3>; +- interrupts = <3 37>; +- }; +- +- bootbus: bootbus@1180000000000 { +- compatible = "cavium,octeon-3860-bootbus"; +- reg = <0x11800 0x00000000 0x0 0x200>; +- /* The chip select number and offset */ +- #address-cells = <2>; +- /* The size of the chip select region */ +- #size-cells = <1>; +- ranges = <0 0 0 0x1f400000 0xc00000>, +- <1 0 0x10000 0x30000000 0>, +- <2 0 0x10000 0x40000000 0>, +- <3 0 0x10000 0x50000000 0>, +- <4 0 0 0x1d020000 0x10000>, +- <5 0 0 0x1d040000 0x10000>, +- <6 0 0 0x1d050000 0x10000>, +- <7 0 0x10000 0x90000000 0>; +- +- cavium,cs-config@0 { +- compatible = "cavium,octeon-3860-bootbus-config"; +- cavium,cs-index = <0>; +- cavium,t-adr = <10>; +- cavium,t-ce = <50>; +- cavium,t-oe = <50>; +- cavium,t-we = <35>; +- cavium,t-rd-hld = <25>; +- cavium,t-wr-hld = <35>; +- cavium,t-pause = <0>; +- cavium,t-wait = <300>; +- cavium,t-page = <25>; +- cavium,t-rd-dly = <0>; +- +- cavium,pages = <0>; +- cavium,bus-width = <8>; +- }; +- cavium,cs-config@4 { +- compatible = "cavium,octeon-3860-bootbus-config"; +- cavium,cs-index = <4>; +- cavium,t-adr = <320>; +- cavium,t-ce = <320>; +- cavium,t-oe = <320>; +- cavium,t-we = <320>; +- cavium,t-rd-hld = <320>; +- cavium,t-wr-hld = <320>; +- cavium,t-pause = <320>; +- cavium,t-wait = <320>; +- cavium,t-page = <320>; +- cavium,t-rd-dly = <0>; +- +- cavium,pages = <0>; +- cavium,bus-width = <8>; +- }; +- cavium,cs-config@5 { +- compatible = "cavium,octeon-3860-bootbus-config"; +- cavium,cs-index = <5>; +- cavium,t-adr = <0>; +- cavium,t-ce = <300>; +- cavium,t-oe = <125>; +- cavium,t-we = <150>; +- cavium,t-rd-hld = <100>; +- cavium,t-wr-hld = <300>; +- cavium,t-pause = <0>; +- cavium,t-wait = <300>; +- cavium,t-page = <310>; +- cavium,t-rd-dly = <0>; +- +- cavium,pages = <0>; +- cavium,bus-width = <16>; +- }; +- cavium,cs-config@6 { +- compatible = "cavium,octeon-3860-bootbus-config"; +- cavium,cs-index = <6>; +- cavium,t-adr = <0>; +- cavium,t-ce = <30>; +- cavium,t-oe = <125>; +- cavium,t-we = <150>; +- cavium,t-rd-hld = <100>; +- cavium,t-wr-hld = <30>; +- cavium,t-pause = <0>; +- cavium,t-wait = <30>; +- cavium,t-page = <310>; +- cavium,t-rd-dly = <0>; +- +- cavium,pages = <0>; +- cavium,wait-mode; +- cavium,bus-width = <16>; +- }; +- +- flash0: nor@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x800000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "bootloader"; +- reg = <0 0x200000>; +- read-only; +- }; +- partition@200000 { +- label = "kernel"; +- reg = <0x200000 0x200000>; +- }; +- partition@400000 { +- label = "cramfs"; +- reg = <0x400000 0x3fe000>; +- }; +- partition@7fe000 { +- label = "environment"; +- reg = <0x7fe000 0x2000>; +- read-only; +- }; +- }; +- +- led0: led-display@4,0 { +- compatible = "avago,hdsp-253x"; +- reg = <4 0x20 0x20>, <4 0 0x20>; +- }; +- +- compact-flash@5,0 { +- compatible = "cavium,ebt3000-compact-flash"; +- reg = <5 0 0x10000>, <6 0 0x10000>; +- cavium,bus-width = <16>; +- cavium,true-ide; +- cavium,dma-engine-handle = <&dma0>; +- }; +- }; +- +- dma0: dma-engine@1180000000100 { +- compatible = "cavium,octeon-5750-bootbus-dma"; +- reg = <0x11800 0x00000100 0x0 0x8>; +- interrupts = <0 63>; +- }; +- dma1: dma-engine@1180000000108 { +- compatible = "cavium,octeon-5750-bootbus-dma"; +- reg = <0x11800 0x00000108 0x0 0x8>; +- interrupts = <0 63>; +- }; +- +- uctl: uctl@118006f000000 { +- compatible = "cavium,octeon-6335-uctl"; +- reg = <0x11800 0x6f000000 0x0 0x100>; +- ranges; /* Direct mapping */ +- #address-cells = <2>; +- #size-cells = <2>; +- /* 12MHz, 24MHz and 48MHz allowed */ +- refclk-frequency = <12000000>; +- /* Either "crystal" or "external" */ +- refclk-type = "crystal"; +- +- ehci@16f0000000000 { +- compatible = "cavium,octeon-6335-ehci","usb-ehci"; +- reg = <0x16f00 0x00000000 0x0 0x100>; +- interrupts = <3 44>; +- big-endian-regs; +- }; +- ohci@16f0000000400 { +- compatible = "cavium,octeon-6335-ohci","usb-ohci"; +- reg = <0x16f00 0x00000400 0x0 0x100>; +- interrupts = <3 44>; +- big-endian-regs; +- }; +- }; +- }; +- +- aliases { +- mix0 = &mix0; +- pip = &pip; +- smi0 = &smi0; +- smi1 = &smi1; +- smi2 = &smi2; +- smi3 = &smi3; +- twsi0 = &twsi0; +- twsi1 = &twsi1; +- uart0 = &uart0; +- uart1 = &uart1; +- uctl = &uctl; +- led0 = &led0; +- flash0 = &flash0; +- }; +- }; +diff --git a/scripts/dtc/include-prefixes/mips/cavium-octeon/ubnt_e100.dts b/scripts/dtc/include-prefixes/mips/cavium-octeon/ubnt_e100.dts +deleted file mode 100644 +index cb219b730c57..000000000000 +--- a/scripts/dtc/include-prefixes/mips/cavium-octeon/ubnt_e100.dts ++++ /dev/null +@@ -1,62 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Device tree source for EdgeRouter Lite. +- * +- * Written by: Aaro Koskinen +- */ +- +-/include/ "octeon_3xxx.dtsi" +- +-/ { +- model = "ubnt,e100"; +- +- soc@0 { +- smi0: mdio@1180000001800 { +- phy5: ethernet-phy@5 { +- reg = <5>; +- compatible = "ethernet-phy-ieee802.3-c22"; +- }; +- phy6: ethernet-phy@6 { +- reg = <6>; +- compatible = "ethernet-phy-ieee802.3-c22"; +- }; +- phy7: ethernet-phy@7 { +- reg = <7>; +- compatible = "ethernet-phy-ieee802.3-c22"; +- }; +- }; +- +- pip: pip@11800a0000000 { +- interface@0 { +- ethernet@0 { +- phy-handle = <&phy7>; +- rx-delay = <0>; +- tx-delay = <0x10>; +- }; +- ethernet@1 { +- phy-handle = <&phy6>; +- rx-delay = <0>; +- tx-delay = <0x10>; +- }; +- ethernet@2 { +- phy-handle = <&phy5>; +- rx-delay = <0>; +- tx-delay = <0x10>; +- }; +- }; +- }; +- +- uart0: serial@1180000000800 { +- clock-frequency = <500000000>; +- }; +- +- usbn: usbn@1180068000000 { +- refclk-frequency = <12000000>; +- refclk-type = "crystal"; +- }; +- }; +- +- aliases { +- pip = &pip; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/img/Makefile b/scripts/dtc/include-prefixes/mips/img/Makefile +deleted file mode 100644 +index ebb47490b04b..000000000000 +--- a/scripts/dtc/include-prefixes/mips/img/Makefile ++++ /dev/null +@@ -1,4 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += boston.dtb +- +-dtb-$(CONFIG_FIT_IMAGE_FDT_MARDUK) += pistachio_marduk.dtb +diff --git a/scripts/dtc/include-prefixes/mips/img/boston.dts b/scripts/dtc/include-prefixes/mips/img/boston.dts +deleted file mode 100644 +index 84328afa3a55..000000000000 +--- a/scripts/dtc/include-prefixes/mips/img/boston.dts ++++ /dev/null +@@ -1,237 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "img,boston"; +- +- chosen { +- stdout-path = "uart0:115200"; +- }; +- +- aliases { +- uart0 = &uart0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "img,mips"; +- reg = <0>; +- clocks = <&clk_boston BOSTON_CLK_CPU>; +- }; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- pci0: pci@10000000 { +- compatible = "xlnx,axi-pcie-host-1.00.a"; +- device_type = "pci"; +- reg = <0x10000000 0x2000000>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&gic>; +- interrupts = ; +- +- ranges = <0x02000000 0 0x40000000 +- 0x40000000 0 0x40000000>; +- +- bus-range = <0x00 0xff>; +- +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pci0_intc 1>, +- <0 0 0 2 &pci0_intc 2>, +- <0 0 0 3 &pci0_intc 3>, +- <0 0 0 4 &pci0_intc 4>; +- +- pci0_intc: interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- }; +- }; +- +- pci1: pci@12000000 { +- compatible = "xlnx,axi-pcie-host-1.00.a"; +- device_type = "pci"; +- reg = <0x12000000 0x2000000>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&gic>; +- interrupts = ; +- +- ranges = <0x02000000 0 0x20000000 +- 0x20000000 0 0x20000000>; +- +- bus-range = <0x00 0xff>; +- +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pci1_intc 1>, +- <0 0 0 2 &pci1_intc 2>, +- <0 0 0 3 &pci1_intc 3>, +- <0 0 0 4 &pci1_intc 4>; +- +- pci1_intc: interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- }; +- }; +- +- pci2: pci@14000000 { +- compatible = "xlnx,axi-pcie-host-1.00.a"; +- device_type = "pci"; +- reg = <0x14000000 0x2000000>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&gic>; +- interrupts = ; +- +- ranges = <0x02000000 0 0x16000000 +- 0x16000000 0 0x100000>; +- +- bus-range = <0x00 0xff>; +- +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pci2_intc 1>, +- <0 0 0 2 &pci2_intc 2>, +- <0 0 0 3 &pci2_intc 3>, +- <0 0 0 4 &pci2_intc 4>; +- +- pci2_intc: interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- }; +- +- pci2_root@0,0,0 { +- compatible = "pci10ee,7021"; +- reg = <0x00000000 0 0 0 0>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- +- eg20t_bridge@1,0,0 { +- compatible = "pci8086,8800"; +- reg = <0x00010000 0 0 0 0>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- +- eg20t_phub@2,0,0 { +- compatible = "pci8086,8801"; +- reg = <0x00020000 0 0 0 0>; +- intel,eg20t-prefetch = <0>; +- }; +- +- eg20t_mac@2,0,1 { +- compatible = "pci8086,8802"; +- reg = <0x00020100 0 0 0 0>; +- phy-reset-gpios = <&eg20t_gpio 6 +- GPIO_ACTIVE_LOW>; +- }; +- +- eg20t_gpio: eg20t_gpio@2,0,2 { +- compatible = "pci8086,8803"; +- reg = <0x00020200 0 0 0 0>; +- +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- eg20t_i2c@2,12,2 { +- compatible = "pci8086,8817"; +- reg = <0x00026200 0 0 0 0>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtc@68 { +- compatible = "st,m41t81s"; +- reg = <0x68>; +- }; +- }; +- }; +- }; +- }; +- +- gic: interrupt-controller@16120000 { +- compatible = "mti,gic"; +- reg = <0x16120000 0x20000>; +- +- interrupt-controller; +- #interrupt-cells = <3>; +- +- timer { +- compatible = "mti,gic-timer"; +- interrupts = ; +- clocks = <&clk_boston BOSTON_CLK_CPU>; +- }; +- }; +- +- cdmm@16140000 { +- compatible = "mti,mips-cdmm"; +- reg = <0x16140000 0x8000>; +- }; +- +- cpc@16200000 { +- compatible = "mti,mips-cpc"; +- reg = <0x16200000 0x8000>; +- }; +- +- plat_regs: system-controller@17ffd000 { +- compatible = "img,boston-platform-regs", "syscon"; +- reg = <0x17ffd000 0x1000>; +- +- clk_boston: clock { +- compatible = "img,boston-clock"; +- #clock-cells = <1>; +- }; +- }; +- +- reboot: syscon-reboot { +- compatible = "syscon-reboot"; +- regmap = <&plat_regs>; +- offset = <0x10>; +- mask = <0x10>; +- }; +- +- uart0: uart@17ffe000 { +- compatible = "ns16550a"; +- reg = <0x17ffe000 0x1000>; +- reg-shift = <2>; +- +- interrupt-parent = <&gic>; +- interrupts = ; +- +- clocks = <&clk_boston BOSTON_CLK_SYS>; +- }; +- +- lcd: lcd@17fff000 { +- compatible = "img,boston-lcd"; +- reg = <0x17fff000 0x8>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/img/pistachio.dtsi b/scripts/dtc/include-prefixes/mips/img/pistachio.dtsi +deleted file mode 100644 +index b1db8b8f446f..000000000000 +--- a/scripts/dtc/include-prefixes/mips/img/pistachio.dtsi ++++ /dev/null +@@ -1,930 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015, 2016 Imagination Technologies Ltd. +- * Copyright (C) 2015 Google, Inc. +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "img,pistachio"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- interrupt-parent = <&gic>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "mti,interaptiv"; +- reg = <0>; +- clocks = <&clk_core CLK_MIPS_PLL>; +- clock-names = "cpu"; +- clock-latency = <1000>; +- operating-points = < +- /* kHz uV(dummy) */ +- 546000 1150000 +- 520000 1100000 +- 494000 1000000 +- 468000 950000 +- 442000 900000 +- 416000 800000 +- >; +- }; +- }; +- +- i2c0: i2c@18100000 { +- compatible = "img,scb-i2c"; +- reg = <0x18100000 0x200>; +- interrupts = ; +- clocks = <&clk_periph PERIPH_CLK_I2C0>, +- <&cr_periph SYS_CLK_I2C0>; +- clock-names = "scb", "sys"; +- assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>, +- <&clk_periph PERIPH_CLK_I2C0_DIV>; +- assigned-clock-rates = <100000000>, <33333334>; +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c1: i2c@18100200 { +- compatible = "img,scb-i2c"; +- reg = <0x18100200 0x200>; +- interrupts = ; +- clocks = <&clk_periph PERIPH_CLK_I2C1>, +- <&cr_periph SYS_CLK_I2C1>; +- clock-names = "scb", "sys"; +- assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>, +- <&clk_periph PERIPH_CLK_I2C1_DIV>; +- assigned-clock-rates = <100000000>, <33333334>; +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c2: i2c@18100400 { +- compatible = "img,scb-i2c"; +- reg = <0x18100400 0x200>; +- interrupts = ; +- clocks = <&clk_periph PERIPH_CLK_I2C2>, +- <&cr_periph SYS_CLK_I2C2>; +- clock-names = "scb", "sys"; +- assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>, +- <&clk_periph PERIPH_CLK_I2C2_DIV>; +- assigned-clock-rates = <100000000>, <33333334>; +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2c3: i2c@18100600 { +- compatible = "img,scb-i2c"; +- reg = <0x18100600 0x200>; +- interrupts = ; +- clocks = <&clk_periph PERIPH_CLK_I2C3>, +- <&cr_periph SYS_CLK_I2C3>; +- clock-names = "scb", "sys"; +- assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>, +- <&clk_periph PERIPH_CLK_I2C3_DIV>; +- assigned-clock-rates = <100000000>, <33333334>; +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c3_pins>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- i2s_in: i2s-in@18100800 { +- compatible = "img,i2s-in"; +- reg = <0x18100800 0x200>; +- interrupts = ; +- dmas = <&mdc 30 0xffffffff 0>; +- dma-names = "rx"; +- clocks = <&cr_periph SYS_CLK_I2S_IN>; +- clock-names = "sys"; +- img,i2s-channels = <6>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s_in_pins>; +- status = "disabled"; +- +- #sound-dai-cells = <0>; +- }; +- +- i2s_out: i2s-out@18100a00 { +- compatible = "img,i2s-out"; +- reg = <0x18100a00 0x200>; +- interrupts = ; +- dmas = <&mdc 23 0xffffffff 0>; +- dma-names = "tx"; +- clocks = <&cr_periph SYS_CLK_I2S_OUT>, +- <&clk_core CLK_I2S>; +- clock-names = "sys", "ref"; +- assigned-clocks = <&clk_core CLK_I2S_DIV>; +- assigned-clock-rates = <12288000>; +- img,i2s-channels = <6>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s_out_pins>; +- status = "disabled"; +- resets = <&pistachio_reset PISTACHIO_RESET_I2S_OUT>; +- reset-names = "rst"; +- #sound-dai-cells = <0>; +- }; +- +- parallel_out: parallel-audio-out@18100c00 { +- compatible = "img,parallel-out"; +- reg = <0x18100c00 0x100>; +- interrupts = ; +- dmas = <&mdc 16 0xffffffff 0>; +- dma-names = "tx"; +- clocks = <&cr_periph SYS_CLK_PAUD_OUT>, +- <&clk_core CLK_AUDIO_DAC>; +- clock-names = "sys", "ref"; +- assigned-clocks = <&clk_core CLK_AUDIO_DAC_DIV>; +- assigned-clock-rates = <12288000>; +- status = "disabled"; +- resets = <&pistachio_reset PISTACHIO_RESET_PRL_OUT>; +- reset-names = "rst"; +- #sound-dai-cells = <0>; +- }; +- +- spdif_out: spdif-out@18100d00 { +- compatible = "img,spdif-out"; +- reg = <0x18100d00 0x100>; +- interrupts = ; +- dmas = <&mdc 14 0xffffffff 0>; +- dma-names = "tx"; +- clocks = <&cr_periph SYS_CLK_SPDIF_OUT>, +- <&clk_core CLK_SPDIF>; +- clock-names = "sys", "ref"; +- assigned-clocks = <&clk_core CLK_SPDIF_DIV>; +- assigned-clock-rates = <12288000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&spdif_out_pin>; +- status = "disabled"; +- resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>; +- reset-names = "rst"; +- #sound-dai-cells = <0>; +- }; +- +- spdif_in: spdif-in@18100e00 { +- compatible = "img,spdif-in"; +- reg = <0x18100e00 0x100>; +- interrupts = ; +- dmas = <&mdc 15 0xffffffff 0>; +- dma-names = "rx"; +- clocks = <&cr_periph SYS_CLK_SPDIF_IN>; +- clock-names = "sys"; +- pinctrl-names = "default"; +- pinctrl-0 = <&spdif_in_pin>; +- status = "disabled"; +- +- #sound-dai-cells = <0>; +- }; +- +- internal_dac: internal-dac { +- compatible = "img,pistachio-internal-dac"; +- img,cr-top = <&cr_top>; +- img,voltage-select = <1>; +- +- #sound-dai-cells = <0>; +- }; +- +- spfi0: spi@18100f00 { +- compatible = "img,spfi"; +- reg = <0x18100f00 0x100>; +- interrupts = ; +- clocks = <&clk_core CLK_SPI0>, <&cr_periph SYS_CLK_SPI0_MASTER>; +- clock-names = "sys", "spfi"; +- dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>; +- dma-names = "rx", "tx"; +- spfi-max-frequency = <50000000>; +- status = "disabled"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- spfi1: spi@18101000 { +- compatible = "img,spfi"; +- reg = <0x18101000 0x100>; +- interrupts = ; +- clocks = <&clk_core CLK_SPI1>, <&cr_periph SYS_CLK_SPI1>; +- clock-names = "sys", "spfi"; +- dmas = <&mdc 1 0xffffffff 0>, <&mdc 2 0xffffffff 0>; +- dma-names = "rx", "tx"; +- img,supports-quad-mode; +- spfi-max-frequency = <50000000>; +- status = "disabled"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- pwm: pwm@18101300 { +- compatible = "img,pistachio-pwm"; +- reg = <0x18101300 0x100>; +- clocks = <&clk_periph PERIPH_CLK_PWM>, +- <&cr_periph SYS_CLK_PWM>; +- clock-names = "pwm", "sys"; +- img,cr-periph = <&cr_periph>; +- #pwm-cells = <2>; +- status = "disabled"; +- }; +- +- uart0: uart@18101400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x18101400 0x100>; +- interrupts = ; +- clocks = <&clk_core CLK_UART0>, <&cr_periph SYS_CLK_UART0>; +- clock-names = "baudclk", "apb_pclk"; +- assigned-clocks = <&clk_core CLK_UART0_INTERNAL_DIV>, +- <&clk_core CLK_UART0_DIV>; +- reg-shift = <2>; +- reg-io-width = <4>; +- pinctrl-0 = <&uart0_pins>, <&uart0_rts_cts_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- uart1: uart@18101500 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x18101500 0x100>; +- interrupts = ; +- clocks = <&clk_core CLK_UART1>, <&cr_periph SYS_CLK_UART1>; +- clock-names = "baudclk", "apb_pclk"; +- assigned-clocks = <&clk_core CLK_UART1_INTERNAL_DIV>, +- <&clk_core CLK_UART1_DIV>; +- assigned-clock-rates = <114278400>, <1843200>; +- reg-shift = <2>; +- reg-io-width = <4>; +- pinctrl-0 = <&uart1_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- adc: adc@18101600 { +- compatible = "cosmic,10001-adc"; +- reg = <0x18101600 0x24>; +- adc-reserved-channels = <0x30>; +- clocks = <&clk_core CLK_AUX_ADC>; +- clock-names = "adc"; +- assigned-clocks = <&clk_core CLK_AUX_ADC_INTERNAL_DIV>, +- <&clk_core CLK_AUX_ADC_DIV>; +- assigned-clock-rates = <100000000>, <1000000>; +- status = "disabled"; +- +- #io-channel-cells = <1>; +- }; +- +- pinctrl: pinctrl@18101c00 { +- compatible = "img,pistachio-system-pinctrl"; +- reg = <0x18101c00 0x400>; +- +- gpio0: gpio0 { +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 0 16>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio1 { +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 16 16>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio2 { +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 32 16>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio3 { +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 48 16>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio4: gpio4 { +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 64 16>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio5: gpio5 { +- interrupts = ; +- +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pinctrl 0 80 10>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- i2c0_pins: i2c0-pins { +- pin_i2c0: i2c0 { +- pins = "mfio28", "mfio29"; +- function = "i2c0"; +- drive-strength = <4>; +- }; +- }; +- +- i2c1_pins: i2c1-pins { +- pin_i2c1: i2c1 { +- pins = "mfio30", "mfio31"; +- function = "i2c1"; +- drive-strength = <4>; +- }; +- }; +- +- i2c2_pins: i2c2-pins { +- pin_i2c2: i2c2 { +- pins = "mfio32", "mfio33"; +- function = "i2c2"; +- drive-strength = <4>; +- }; +- }; +- +- i2c3_pins: i2c3-pins { +- pin_i2c3: i2c3 { +- pins = "mfio34", "mfio35"; +- function = "i2c3"; +- drive-strength = <4>; +- }; +- }; +- +- spim0_pins: spim0-pins { +- pin_spim0: spim0 { +- pins = "mfio9", "mfio10"; +- function = "spim0"; +- drive-strength = <4>; +- }; +- spim0_clk: spim0-clk { +- pins = "mfio8"; +- function = "spim0"; +- drive-strength = <4>; +- }; +- }; +- +- spim0_cs0_alt_pin: spim0-cs0-alt-pin { +- spim0-cs0 { +- pins = "mfio2"; +- drive-strength = <2>; +- }; +- }; +- +- spim0_cs1_pin: spim0-cs1-pin { +- spim0-cs1 { +- pins = "mfio1"; +- drive-strength = <2>; +- }; +- }; +- +- spim0_cs2_pin: spim0-cs2-pin { +- spim0-cs2 { +- pins = "mfio55"; +- drive-strength = <2>; +- }; +- }; +- +- spim0_cs2_alt_pin: spim0-cs2-alt-pin { +- spim0-cs2 { +- pins = "mfio28"; +- drive-strength = <2>; +- }; +- }; +- +- spim0_cs3_pin: spim0-cs3-pin { +- spim0-cs3 { +- pins = "mfio56"; +- drive-strength = <2>; +- }; +- }; +- +- spim0_cs3_alt_pin: spim0-cs3-alt-pin { +- spim0-cs3 { +- pins = "mfio29"; +- drive-strength = <2>; +- }; +- }; +- +- spim0_cs4_pin: spim0-cs4-pin { +- spim0-cs4 { +- pins = "mfio57"; +- drive-strength = <2>; +- }; +- }; +- +- spim0_cs4_alt_pin: spim0-cs4-alt-pin { +- spim0-cs4 { +- pins = "mfio30"; +- drive-strength = <2>; +- }; +- }; +- +- spim1_pins: spim1-pins { +- spim1 { +- pins = "mfio3", "mfio4", "mfio5"; +- function = "spim1"; +- drive-strength = <2>; +- }; +- }; +- +- spim1_quad_pins: spim1-quad-pins { +- spim1-quad { +- pins = "mfio6", "mfio7"; +- function = "spim1"; +- drive-strength = <2>; +- }; +- }; +- +- spim1_cs0_pin: spim1-cs0-pins { +- spim1-cs0 { +- pins = "mfio0"; +- function = "spim1"; +- drive-strength = <2>; +- }; +- }; +- +- spim1_cs1_pin: spim1-cs1-pin { +- spim1-cs1 { +- pins = "mfio1"; +- function = "spim1"; +- drive-strength = <2>; +- }; +- }; +- +- spim1_cs1_alt_pin: spim1-cs1-alt-pin { +- spim1-cs1 { +- pins = "mfio58"; +- function = "spim1"; +- drive-strength = <2>; +- }; +- }; +- +- spim1_cs2_pin: spim1-cs2-pin { +- spim1-cs2 { +- pins = "mfio2"; +- function = "spim1"; +- drive-strength = <2>; +- }; +- }; +- +- spim1_cs2_alt0_pin: spim1-cs2-alt0-pin { +- spim1-cs2 { +- pins = "mfio31"; +- function = "spim1"; +- drive-strength = <2>; +- }; +- }; +- +- spim1_cs2_alt1_pin: spim1-cs2-alt1-pin { +- spim1-cs2 { +- pins = "mfio55"; +- function = "spim1"; +- drive-strength = <2>; +- }; +- }; +- +- spim1_cs3_pin: spim1-cs3-pin { +- spim1-cs3 { +- pins = "mfio56"; +- function = "spim1"; +- drive-strength = <2>; +- }; +- }; +- +- spim1_cs4_pin: spim1-cs4-pin { +- spim1-cs4 { +- pins = "mfio57"; +- function = "spim1"; +- drive-strength = <2>; +- }; +- }; +- +- uart0_pins: uart0-pins { +- uart0 { +- pins = "mfio55", "mfio56"; +- function = "uart0"; +- drive-strength = <2>; +- }; +- }; +- +- uart0_rts_cts_pins: uart0-rts-cts-pins { +- uart0-rts-cts { +- pins = "mfio57", "mfio58"; +- function = "uart0"; +- drive-strength = <2>; +- }; +- }; +- +- uart1_pins: uart1-pins { +- uart1 { +- pins = "mfio59", "mfio60"; +- function = "uart1"; +- drive-strength = <2>; +- }; +- }; +- +- uart1_rts_cts_pins: uart1-rts-cts-pins { +- uart1-rts-cts { +- pins = "mfio1", "mfio2"; +- function = "uart1"; +- drive-strength = <2>; +- }; +- }; +- +- enet_pins: enet-pins { +- pin_enet: enet { +- pins = "mfio63", "mfio64", "mfio65", "mfio66", +- "mfio67", "mfio68", "mfio69", "mfio70"; +- function = "eth"; +- slew-rate = <1>; +- drive-strength = <4>; +- }; +- pin_enet_phy_clk: enet-phy-clk { +- pins = "mfio71"; +- function = "eth"; +- slew-rate = <1>; +- drive-strength = <8>; +- }; +- }; +- +- sdhost_pins: sdhost-pins { +- pin_sdhost_clk: sdhost-clk { +- pins = "mfio15"; +- function = "sdhost"; +- slew-rate = <1>; +- drive-strength = <4>; +- }; +- pin_sdhost_cmd: sdhost-cmd { +- pins = "mfio16"; +- function = "sdhost"; +- slew-rate = <1>; +- drive-strength = <4>; +- }; +- pin_sdhost_data: sdhost-data { +- pins = "mfio17", "mfio18", "mfio19", "mfio20", +- "mfio21", "mfio22", "mfio23", "mfio24"; +- function = "sdhost"; +- slew-rate = <1>; +- drive-strength = <4>; +- }; +- pin_sdhost_power_select: sdhost-power-select { +- pins = "mfio25"; +- function = "sdhost"; +- slew-rate = <1>; +- drive-strength = <2>; +- }; +- pin_sdhost_card_detect: sdhost-card-detect { +- pins = "mfio26"; +- function = "sdhost"; +- drive-strength = <2>; +- }; +- pin_sdhost_write_protect: sdhost-write-protect { +- pins = "mfio27"; +- function = "sdhost"; +- drive-strength = <2>; +- }; +- }; +- +- ir_pin: ir-pin { +- ir-data { +- pins = "mfio72"; +- function = "ir"; +- drive-strength = <2>; +- }; +- }; +- +- pwmpdm0_pin: pwmpdm0-pin { +- pwmpdm0 { +- pins = "mfio73"; +- function = "pwmpdm"; +- drive-strength = <2>; +- }; +- }; +- +- pwmpdm1_pin: pwmpdm1-pin { +- pwmpdm1 { +- pins = "mfio74"; +- function = "pwmpdm"; +- drive-strength = <2>; +- }; +- }; +- +- pwmpdm2_pin: pwmpdm2-pin { +- pwmpdm2 { +- pins = "mfio75"; +- function = "pwmpdm"; +- drive-strength = <2>; +- }; +- }; +- +- pwmpdm3_pin: pwmpdm3-pin { +- pwmpdm3 { +- pins = "mfio76"; +- function = "pwmpdm"; +- drive-strength = <2>; +- }; +- }; +- +- dac_clk_pin: dac-clk-pin { +- pin_dac_clk: dac-clk { +- pins = "mfio45"; +- function = "i2s_dac_clk"; +- drive-strength = <4>; +- }; +- }; +- +- i2s_mclk_pin: i2s-mclk-pin { +- pin_i2s_mclk: i2s-mclk { +- pins = "mfio36"; +- function = "i2s_out"; +- drive-strength = <4>; +- }; +- }; +- +- spdif_out_pin: spdif-out-pin { +- spdif-out { +- pins = "mfio61"; +- function = "spdif_out"; +- slew-rate = <1>; +- drive-strength = <2>; +- }; +- }; +- +- spdif_in_pin: spdif-in-pin { +- spdif-in { +- pins = "mfio62"; +- function = "spdif_in"; +- drive-strength = <2>; +- }; +- }; +- +- i2s_out_pins: i2s-out-pins { +- pins_i2s_out_clk: i2s-out-clk { +- pins = "mfio37", "mfio38"; +- function = "i2s_out"; +- drive-strength = <4>; +- }; +- pins_i2s_out: i2s-out { +- pins = "mfio39", "mfio40", +- "mfio41", "mfio42", +- "mfio43", "mfio44"; +- function = "i2s_out"; +- drive-strength = <2>; +- }; +- }; +- +- i2s_in_pins: i2s-in-pins { +- i2s-in { +- pins = "mfio47", "mfio48", "mfio49", +- "mfio50", "mfio51", "mfio52", +- "mfio53", "mfio54"; +- function = "i2s_in"; +- drive-strength = <2>; +- }; +- }; +- }; +- +- timer: timer@18102000 { +- compatible = "img,pistachio-gptimer"; +- reg = <0x18102000 0x100>; +- interrupts = ; +- clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>, +- <&cr_periph SYS_CLK_TIMER>; +- clock-names = "fast", "sys"; +- img,cr-periph = <&cr_periph>; +- }; +- +- wdt: watchdog@18102100 { +- compatible = "img,pdc-wdt"; +- reg = <0x18102100 0x100>; +- interrupts = ; +- clocks = <&clk_periph PERIPH_CLK_WD>, <&cr_periph SYS_CLK_WD>; +- clock-names = "wdt", "sys"; +- assigned-clocks = <&clk_periph PERIPH_CLK_WD_PRE_DIV>, +- <&clk_periph PERIPH_CLK_WD_DIV>; +- assigned-clock-rates = <4000000>, <32768>; +- }; +- +- ir: ir@18102200 { +- compatible = "img,ir-rev1"; +- reg = <0x18102200 0x100>; +- interrupts = ; +- clocks = <&clk_periph PERIPH_CLK_IR>, <&cr_periph SYS_CLK_IR>; +- clock-names = "core", "sys"; +- assigned-clocks = <&clk_periph PERIPH_CLK_IR_PRE_DIV>, +- <&clk_periph PERIPH_CLK_IR_DIV>; +- assigned-clock-rates = <4000000>, <32768>; +- pinctrl-0 = <&ir_pin>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- +- usb: usb@18120000 { +- compatible = "snps,dwc2"; +- reg = <0x18120000 0x1c000>; +- interrupts = ; +- phys = <&usb_phy>; +- phy-names = "usb2-phy"; +- g-tx-fifo-size = <256 256 256 256>; +- status = "disabled"; +- }; +- +- enet: ethernet@18140000 { +- compatible = "snps,dwmac"; +- reg = <0x18140000 0x2000>; +- interrupts = ; +- interrupt-names = "macirq"; +- clocks = <&clk_core CLK_ENET>, <&cr_periph SYS_CLK_ENET>; +- clock-names = "stmmaceth", "pclk"; +- assigned-clocks = <&clk_core CLK_ENET_MUX>, +- <&clk_core CLK_ENET_DIV>; +- assigned-clock-parents = <&clk_core CLK_SYS_INTERNAL_DIV>; +- assigned-clock-rates = <0>, <50000000>; +- pinctrl-0 = <&enet_pins>; +- pinctrl-names = "default"; +- phy-mode = "rmii"; +- status = "disabled"; +- }; +- +- sdhost: mmc@18142000 { +- compatible = "img,pistachio-dw-mshc"; +- reg = <0x18142000 0x400>; +- interrupts = ; +- clocks = <&clk_core CLK_SD_HOST>, <&cr_periph SYS_CLK_SD_HOST>; +- clock-names = "ciu", "biu"; +- pinctrl-0 = <&sdhost_pins>; +- pinctrl-names = "default"; +- fifo-depth = <0x20>; +- clock-frequency = <50000000>; +- bus-width = <8>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- status = "disabled"; +- }; +- +- sram: sram@1b000000 { +- compatible = "mmio-sram"; +- reg = <0x1b000000 0x10000>; +- }; +- +- mdc: dma-controller@18143000 { +- compatible = "img,pistachio-mdc-dma"; +- reg = <0x18143000 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&cr_periph SYS_CLK_MDC>; +- clock-names = "sys"; +- +- img,max-burst-multiplier = <16>; +- img,cr-periph = <&cr_periph>; +- +- #dma-cells = <3>; +- }; +- +- clk_core: clk@18144000 { +- compatible = "img,pistachio-clk", "syscon"; +- clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>, +- <&cr_top EXT_CLK_ENET_IN>; +- clock-names = "xtal", "audio_refclk_ext_gate", +- "ext_enet_in_gate"; +- reg = <0x18144000 0x800>; +- #clock-cells = <1>; +- }; +- +- clk_periph: clk@18144800 { +- compatible = "img,pistachio-clk-periph"; +- reg = <0x18144800 0x1000>; +- clocks = <&clk_core CLK_PERIPH_SYS>; +- clock-names = "periph_sys_core"; +- #clock-cells = <1>; +- }; +- +- cr_periph: clk@18148000 { +- compatible = "img,pistachio-cr-periph", "syscon", "simple-bus"; +- reg = <0x18148000 0x1000>; +- clocks = <&clk_periph PERIPH_CLK_SYS>; +- clock-names = "sys"; +- #clock-cells = <1>; +- +- pistachio_reset: reset-controller { +- compatible = "img,pistachio-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- cr_top: clk@18149000 { +- compatible = "img,pistachio-cr-top", "syscon"; +- reg = <0x18149000 0x200>; +- #clock-cells = <1>; +- }; +- +- hash: hash@18149600 { +- compatible = "img,hash-accelerator"; +- reg = <0x18149600 0x100>, <0x18101100 0x4>; +- interrupts = ; +- dmas = <&mdc 8 0xffffffff 0>; +- dma-names = "tx"; +- clocks = <&cr_periph SYS_CLK_HASH>, +- <&clk_periph PERIPH_CLK_ROM>; +- clock-names = "sys", "hash"; +- }; +- +- gic: interrupt-controller@1bdc0000 { +- compatible = "mti,gic"; +- reg = <0x1bdc0000 0x20000>; +- +- interrupt-controller; +- #interrupt-cells = <3>; +- +- timer { +- compatible = "mti,gic-timer"; +- interrupts = ; +- clocks = <&clk_core CLK_MIPS>; +- }; +- }; +- +- cpc: cpc@1bde0000 { +- compatible = "mti,mips-cpc"; +- reg = <0x1bde0000 0x10000>; +- }; +- +- cdmm: cdmm@1bdf0000 { +- compatible = "mti,mips-cdmm"; +- reg = <0x1bdf0000 0x10000>; +- }; +- +- usb_phy: usb-phy { +- compatible = "img,pistachio-usb-phy"; +- clocks = <&clk_core CLK_USB_PHY>; +- clock-names = "usb_phy"; +- assigned-clocks = <&clk_core CLK_USB_PHY_DIV>; +- assigned-clock-rates = <50000000>; +- img,refclk = <0x2>; +- img,cr-top = <&cr_top>; +- #phy-cells = <0>; +- }; +- +- xtal: xtal { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <52000000>; +- clock-output-names = "xtal"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/img/pistachio_marduk.dts b/scripts/dtc/include-prefixes/mips/img/pistachio_marduk.dts +deleted file mode 100644 +index a8708783f04b..000000000000 +--- a/scripts/dtc/include-prefixes/mips/img/pistachio_marduk.dts ++++ /dev/null +@@ -1,161 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015, 2016 Imagination Technologies Ltd. +- * +- * IMG Marduk board is also known as Creator Ci40. +- */ +- +-/dts-v1/; +- +-#include "pistachio.dtsi" +- +-/ { +- model = "IMG Marduk (Creator Ci40)"; +- compatible = "img,pistachio-marduk", "img,pistachio"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- ethernet0 = &enet; +- spi0 = &spfi0; +- spi1 = &spfi1; +- }; +- +- chosen { +- bootargs = "root=/dev/sda1 rootwait ro lpj=723968"; +- stdout-path = "serial1:115200"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- reg_1v8: fixed-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "aux_adc_vref"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- }; +- +- internal_dac_supply: internal-dac-supply { +- compatible = "regulator-fixed"; +- regulator-name = "internal_dac_supply"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; +- +- led-controller { +- compatible = "pwm-leds"; +- +- led-1 { +- label = "marduk:red:heartbeat"; +- pwms = <&pwm 3 300000>; +- max-brightness = <255>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- keys { +- compatible = "gpio-keys"; +- button@1 { +- label = "Button 1"; +- linux,code = <0x101>; /* BTN_1 */ +- gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; +- }; +- button@2 { +- label = "Button 2"; +- linux,code = <0x102>; /* BTN_2 */ +- gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&internal_dac { +- VDD-supply = <&internal_dac_supply>; +-}; +- +-&spfi1 { +- status = "okay"; +- +- pinctrl-0 = <&spim1_pins>, <&spim1_quad_pins>, <&spim1_cs0_pin>, +- <&spim1_cs1_pin>; +- pinctrl-names = "default"; +- cs-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>, <&gpio0 1 GPIO_ACTIVE_HIGH>; +- +- flash@0 { +- compatible = "spansion,s25fl016k", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +- assigned-clock-rates = <114278400>, <1843200>; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&usb { +- status = "okay"; +-}; +- +-&enet { +- status = "okay"; +-}; +- +-&pin_enet { +- drive-strength = <2>; +-}; +- +-&pin_enet_phy_clk { +- drive-strength = <2>; +-}; +- +-&sdhost { +- status = "okay"; +- bus-width = <4>; +- disable-wp; +-}; +- +-&pin_sdhost_cmd { +- drive-strength = <2>; +-}; +- +-&pin_sdhost_data { +- drive-strength = <2>; +-}; +- +-&pwm { +- status = "okay"; +- +- pinctrl-0 = <&pwmpdm0_pin>, <&pwmpdm1_pin>, <&pwmpdm2_pin>, +- <&pwmpdm3_pin>; +- pinctrl-names = "default"; +-}; +- +-&adc { +- status = "okay"; +- vref-supply = <®_1v8>; +- adc-reserved-channels = <0x10>; +-}; +- +-&i2c2 { +- status = "okay"; +- clock-frequency = <400000>; +- +- tpm@20 { +- compatible = "infineon,slb9645tt"; +- reg = <0x20>; +- }; +- +-}; +- +-&i2c3 { +- status = "okay"; +- clock-frequency = <400000>; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ingenic/Makefile b/scripts/dtc/include-prefixes/mips/ingenic/Makefile +deleted file mode 100644 +index 54aa0c4e6091..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ingenic/Makefile ++++ /dev/null +@@ -1,9 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_JZ4740_QI_LB60) += qi_lb60.dtb +-dtb-$(CONFIG_JZ4740_RS90) += rs90.dtb +-dtb-$(CONFIG_JZ4770_GCW0) += gcw0.dtb +-dtb-$(CONFIG_JZ4780_CI20) += ci20.dtb +-dtb-$(CONFIG_X1000_CU1000_NEO) += cu1000-neo.dtb +-dtb-$(CONFIG_X1830_CU1830_NEO) += cu1830-neo.dtb +- +-obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) +diff --git a/scripts/dtc/include-prefixes/mips/ingenic/ci20.dts b/scripts/dtc/include-prefixes/mips/ingenic/ci20.dts +deleted file mode 100644 +index a688809beebc..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ingenic/ci20.dts ++++ /dev/null +@@ -1,538 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "jz4780.dtsi" +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "img,ci20", "ingenic,jz4780"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial3 = &uart3; +- serial4 = &uart4; +- }; +- +- chosen { +- stdout-path = &uart4; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x10000000 +- 0x30000000 0x30000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- sw1 { +- label = "ci20:sw1"; +- linux,code = ; +- gpios = <&gpd 17 GPIO_ACTIVE_HIGH>; +- wakeup-source; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led0 { +- label = "ci20:red:led0"; +- gpios = <&gpc 3 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "none"; +- }; +- +- led1 { +- label = "ci20:red:led1"; +- gpios = <&gpc 2 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "nand-disk"; +- }; +- +- led2 { +- label = "ci20:red:led2"; +- gpios = <&gpc 1 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "cpu1"; +- }; +- +- led3 { +- label = "ci20:red:led3"; +- gpios = <&gpc 0 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "cpu0"; +- }; +- }; +- +- eth0_power: fixedregulator@0 { +- compatible = "regulator-fixed"; +- +- regulator-name = "eth0_power"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpb 25 GPIO_ACTIVE_LOW>; +- enable-active-high; +- }; +- +- ir: ir { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpe 3 GPIO_ACTIVE_LOW>; +- }; +- +- wlan0_power: fixedregulator@1 { +- compatible = "regulator-fixed"; +- +- regulator-name = "wlan0_power"; +- +- gpio = <&gpb 19 GPIO_ACTIVE_LOW>; +- enable-active-high; +- }; +- +- otg_power: fixedregulator@2 { +- compatible = "regulator-fixed"; +- +- regulator-name = "otg_power"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- +- gpio = <&gpf 14 GPIO_ACTIVE_LOW>; +- enable-active-high; +- }; +-}; +- +-&ext { +- clock-frequency = <48000000>; +-}; +- +-&cgu { +- /* +- * Use the 32.768 kHz oscillator as the parent of the RTC for a higher +- * precision. +- */ +- assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>; +- assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>; +- assigned-clock-rates = <48000000>; +-}; +- +-&tcu { +- /* +- * 750 kHz for the system timers and clocksource, +- * use channel #0 and #1 for the per cpu system timers, +- * and use channel #2 for the clocksource. +- * +- * 3000 kHz for the OST timer to provide a higher +- * precision clocksource. +- */ +- assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, +- <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>; +- assigned-clock-rates = <750000>, <750000>, <750000>, <3000000>; +-}; +- +-&mmc0 { +- status = "okay"; +- +- bus-width = <4>; +- max-frequency = <50000000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_mmc0>; +- +- cd-gpios = <&gpf 20 GPIO_ACTIVE_LOW>; +-}; +- +-&mmc1 { +- status = "okay"; +- +- bus-width = <4>; +- max-frequency = <50000000>; +- non-removable; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_mmc1>; +- +- brcmf: wifi@1 { +-/* reg = <4>;*/ +- compatible = "brcm,bcm4330-fmac"; +- vcc-supply = <&wlan0_power>; +- device-wakeup-gpios = <&gpd 9 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpf 7 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_uart0>; +-}; +- +-&uart1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_uart1>; +-}; +- +-&uart2 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_uart2>; +- uart-has-rtscts; +- +- bluetooth { +- compatible = "brcm,bcm4330-bt"; +- reset-gpios = <&gpf 8 GPIO_ACTIVE_HIGH>; +- vcc-supply = <&wlan0_power>; +- device-wakeup-gpios = <&gpf 5 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpf 6 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpf 4 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&uart3 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_uart3>; +-}; +- +-&uart4 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_uart4>; +-}; +- +-&i2c0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_i2c0>; +- +- clock-frequency = <400000>; +- +- act8600: act8600@5a { +- compatible = "active-semi,act8600"; +- reg = <0x5a>; +- status = "okay"; +- +- regulators { +- vddcore: SUDCDC1 { +- regulator-name = "DCDC_REG1"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- regulator-always-on; +- }; +- vddmem: SUDCDC2 { +- regulator-name = "DCDC_REG2"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- vcc_33: SUDCDC3 { +- regulator-name = "DCDC_REG3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- vcc_50: SUDCDC4 { +- regulator-name = "SUDCDC_REG4"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- vcc_25: LDO_REG5 { +- regulator-name = "LDO_REG5"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- wifi_io: LDO_REG6 { +- regulator-name = "LDO_REG6"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- regulator-always-on; +- }; +- vcc_28: LDO_REG7 { +- regulator-name = "LDO_REG7"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- regulator-always-on; +- }; +- vcc_15: LDO_REG8 { +- regulator-name = "LDO_REG8"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- }; +- vrtc_18: LDO_REG9 { +- regulator-name = "LDO_REG9"; +- /* Despite the datasheet stating 3.3V +- * for REG9 and the driver expecting that, +- * REG9 outputs 1.8V. +- * Likely the CI20 uses a proprietary +- * factory programmed chip variant. +- * Since this is a simple on/off LDO the +- * exact values do not matter. +- */ +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- vcc_11: LDO_REG10 { +- regulator-name = "LDO_REG10"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_i2c1>; +- +-}; +- +-&i2c2 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_i2c2>; +- +-}; +- +-&i2c3 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_i2c3>; +- +-}; +- +-&i2c4 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_i2c4>; +- +- clock-frequency = <400000>; +- +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- +- interrupt-parent = <&gpf>; +- interrupts = <30 IRQ_TYPE_LEVEL_LOW>; +- }; +-}; +- +-&nemc { +- status = "okay"; +- +- nandc: nand-controller@1 { +- compatible = "ingenic,jz4780-nand"; +- reg = <1 0 0x1000000>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- ingenic,bch-controller = <&bch>; +- +- ingenic,nemc-tAS = <10>; +- ingenic,nemc-tAH = <5>; +- ingenic,nemc-tBP = <10>; +- ingenic,nemc-tAW = <15>; +- ingenic,nemc-tSTRV = <100>; +- +- /* +- * Only CLE/ALE are needed for the devices that are connected, rather +- * than the full address line set. +- */ +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_nemc>; +- +- nand@1 { +- reg = <1>; +- +- nand-ecc-step-size = <1024>; +- nand-ecc-strength = <24>; +- nand-ecc-mode = "hw"; +- nand-on-flash-bbt; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_nemc_cs1>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- partition@0 { +- label = "u-boot-spl"; +- reg = <0x0 0x0 0x0 0x800000>; +- }; +- +- partition@800000 { +- label = "u-boot"; +- reg = <0x0 0x800000 0x0 0x200000>; +- }; +- +- partition@a00000 { +- label = "u-boot-env"; +- reg = <0x0 0xa00000 0x0 0x200000>; +- }; +- +- partition@c00000 { +- label = "boot"; +- reg = <0x0 0xc00000 0x0 0x4000000>; +- }; +- +- partition@4c00000 { +- label = "system"; +- reg = <0x0 0x4c00000 0x1 0xfb400000>; +- }; +- }; +- }; +- }; +- +- dm9000@6 { +- compatible = "davicom,dm9000"; +- davicom,no-eeprom; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_nemc_cs6>; +- +- reg = <6 0 1 /* addr */ +- 6 2 1>; /* data */ +- +- ingenic,nemc-tAS = <15>; +- ingenic,nemc-tAH = <10>; +- ingenic,nemc-tBP = <20>; +- ingenic,nemc-tAW = <50>; +- ingenic,nemc-tSTRV = <100>; +- +- reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>; +- vcc-supply = <ð0_power>; +- +- interrupt-parent = <&gpe>; +- interrupts = <19 4>; +- +- nvmem-cells = <ð0_addr>; +- nvmem-cell-names = "mac-address"; +- }; +-}; +- +-&bch { +- status = "okay"; +-}; +- +-&otg_phy { +- status = "okay"; +- +- vcc-supply = <&otg_power>; +-}; +- +-&otg { +- status = "okay"; +-}; +- +-&pinctrl { +- pins_uart0: uart0 { +- function = "uart0"; +- groups = "uart0-data"; +- bias-disable; +- }; +- +- pins_uart1: uart1 { +- function = "uart1"; +- groups = "uart1-data"; +- bias-disable; +- }; +- +- pins_uart2: uart2 { +- function = "uart2"; +- groups = "uart2-data", "uart2-hwflow"; +- bias-disable; +- }; +- +- pins_uart3: uart3 { +- function = "uart3"; +- groups = "uart3-data", "uart3-hwflow"; +- bias-disable; +- }; +- +- pins_uart4: uart4 { +- function = "uart4"; +- groups = "uart4-data"; +- bias-disable; +- }; +- +- pins_i2c0: i2c0 { +- function = "i2c0"; +- groups = "i2c0-data"; +- bias-disable; +- }; +- +- pins_i2c1: i2c1 { +- function = "i2c1"; +- groups = "i2c1-data"; +- bias-disable; +- }; +- +- pins_i2c2: i2c2 { +- function = "i2c2"; +- groups = "i2c2-data"; +- bias-disable; +- }; +- +- pins_i2c3: i2c3 { +- function = "i2c3"; +- groups = "i2c3-data"; +- bias-disable; +- }; +- +- pins_i2c4: i2c4 { +- function = "i2c4"; +- groups = "i2c4-data-e"; +- bias-disable; +- }; +- +- pins_nemc: nemc { +- function = "nemc"; +- groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we", "nemc-frd-fwe"; +- bias-disable; +- }; +- +- pins_nemc_cs1: nemc-cs1 { +- function = "nemc-cs1"; +- groups = "nemc-cs1"; +- bias-disable; +- }; +- +- pins_nemc_cs6: nemc-cs6 { +- function = "nemc-cs6"; +- groups = "nemc-cs6"; +- bias-disable; +- }; +- +- pins_mmc0: mmc0 { +- function = "mmc0"; +- groups = "mmc0-1bit-e", "mmc0-4bit-e"; +- bias-disable; +- }; +- +- pins_mmc1: mmc1 { +- function = "mmc1"; +- groups = "mmc1-1bit-d", "mmc1-4bit-d"; +- bias-disable; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ingenic/cu1000-neo.dts b/scripts/dtc/include-prefixes/mips/ingenic/cu1000-neo.dts +deleted file mode 100644 +index f98cf029efc3..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ingenic/cu1000-neo.dts ++++ /dev/null +@@ -1,218 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "x1000.dtsi" +-#include +-#include +-#include +- +-/ { +- compatible = "yna,cu1000-neo", "ingenic,x1000e"; +- model = "YSH & ATIL General Board CU1000-Neo"; +- +- aliases { +- serial2 = &uart2; +- }; +- +- chosen { +- stdout-path = "serial2:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x04000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-0 { +- gpios = <&gpb 21 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- }; +- }; +- +- ssi: spi-gpio { +- compatible = "spi-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- num-chipselects = <1>; +- +- mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>; +- miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>; +- sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>; +- +- status = "okay"; +- +- spi-max-frequency = <50000000>; +- +- sc16is752: expander@0 { +- compatible = "nxp,sc16is752"; +- reg = <0>; /* CE0 */ +- spi-max-frequency = <4000000>; +- +- clocks = <&exclk_sc16is752>; +- +- interrupt-parent = <&gpc>; +- interrupts = <6 IRQ_TYPE_EDGE_FALLING>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- exclk_sc16is752: sc16is752 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <48000000>; +- }; +- }; +- }; +- +- wlan_pwrseq: msc1-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- +- reset-gpios = <&gpc 17 GPIO_ACTIVE_LOW>; +- post-power-on-delay-ms = <200>; +- }; +-}; +- +-&exclk { +- clock-frequency = <24000000>; +-}; +- +-&cgu { +- /* +- * Use the 32.768 kHz oscillator as the parent of the RTC for a higher +- * precision. +- */ +- assigned-clocks = <&cgu X1000_CLK_RTC>; +- assigned-clock-parents = <&cgu X1000_CLK_RTCLK>; +-}; +- +-&ost { +- /* 1500 kHz for the system timer and clocksource */ +- assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>; +- assigned-clock-rates = <1500000>, <1500000>; +-}; +- +-&uart2 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_uart2>; +-}; +- +-&i2c0 { +- status = "okay"; +- +- clock-frequency = <400000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_i2c0>; +- +- ads7830: adc@48 { +- compatible = "ti,ads7830"; +- reg = <0x48>; +- }; +-}; +- +-&msc0 { +- status = "okay"; +- +- bus-width = <8>; +- max-frequency = <50000000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_msc0>; +- +- non-removable; +-}; +- +-&msc1 { +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- bus-width = <4>; +- max-frequency = <50000000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_msc1>; +- +- non-removable; +- +- mmc-pwrseq = <&wlan_pwrseq>; +- +- ap6212a: wifi@1 { +- compatible = "brcm,bcm4329-fmac"; +- reg = <1>; +- +- interrupt-parent = <&gpc>; +- interrupts = <16 IRQ_TYPE_EDGE_FALLING>; +- interrupt-names = "host-wake"; +- +- brcm,drive-strength = <10>; +- }; +-}; +- +-&mac { +- status = "okay"; +- +- phy-mode = "rmii"; +- phy-handle = <&lan8720a>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_mac>; +- +- snps,reset-gpio = <&gpc 23 GPIO_ACTIVE_LOW>; /* PC23 */ +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 30000>; +-}; +- +-&mdio { +- status = "okay"; +- +- lan8720a: ethernet-phy@0 { +- compatible = "ethernet-phy-id0007.c0f0", "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +-}; +- +-&otg_phy { +- status = "okay"; +-}; +- +-&otg { +- status = "okay"; +-}; +- +-&pinctrl { +- pins_uart2: uart2 { +- function = "uart2"; +- groups = "uart2-data-d"; +- bias-pull-up; +- }; +- +- pins_i2c0: i2c0 { +- function = "i2c0"; +- groups = "i2c0-data"; +- bias-pull-up; +- }; +- +- pins_msc0: msc0 { +- function = "mmc0"; +- groups = "mmc0-1bit", "mmc0-4bit", "mmc0-8bit"; +- bias-disable; +- }; +- +- pins_msc1: msc1 { +- function = "mmc1"; +- groups = "mmc1-1bit", "mmc1-4bit"; +- bias-disable; +- }; +- +- pins_mac: mac { +- function = "mac"; +- groups = "mac"; +- bias-disable; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ingenic/cu1830-neo.dts b/scripts/dtc/include-prefixes/mips/ingenic/cu1830-neo.dts +deleted file mode 100644 +index cfcb40edb7d9..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ingenic/cu1830-neo.dts ++++ /dev/null +@@ -1,222 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "x1830.dtsi" +-#include +-#include +-#include +- +-/ { +- compatible = "yna,cu1830-neo", "ingenic,x1830"; +- model = "YSH & ATIL General Board CU1830-Neo"; +- +- aliases { +- serial1 = &uart1; +- }; +- +- chosen { +- stdout-path = "serial1:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x08000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led-0 { +- gpios = <&gpc 17 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- }; +- }; +- +- ssi0: spi-gpio { +- compatible = "spi-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- num-chipselects = <1>; +- +- mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>; +- miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>; +- sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>; +- +- status = "okay"; +- +- spi-max-frequency = <50000000>; +- +- sc16is752: expander@0 { +- compatible = "nxp,sc16is752"; +- reg = <0>; /* CE0 */ +- spi-max-frequency = <4000000>; +- +- clocks = <&exclk_sc16is752>; +- +- interrupt-parent = <&gpb>; +- interrupts = <18 IRQ_TYPE_EDGE_FALLING>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- exclk_sc16is752: sc16is752 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <48000000>; +- }; +- }; +- }; +- +- wlan_pwrseq: msc1-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- +- reset-gpios = <&gpc 13 GPIO_ACTIVE_LOW>; +- post-power-on-delay-ms = <200>; +- }; +-}; +- +-&exclk { +- clock-frequency = <24000000>; +-}; +- +-&cgu { +- /* +- * Use the 32.768 kHz oscillator as the parent of the RTC for a higher +- * precision. +- */ +- assigned-clocks = <&cgu X1830_CLK_RTC>; +- assigned-clock-parents = <&cgu X1830_CLK_RTCLK>; +-}; +- +-&ost { +- /* 1500 kHz for the system timer and clocksource */ +- assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>; +- assigned-clock-rates = <1500000>, <1500000>; +-}; +- +-&uart1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_uart1>; +-}; +- +-&i2c0 { +- status = "okay"; +- +- clock-frequency = <400000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_i2c0>; +- +- ads7830: adc@48 { +- compatible = "ti,ads7830"; +- reg = <0x48>; +- }; +-}; +- +-&dtrng { +- status = "okay"; +-}; +- +-&msc0 { +- status = "okay"; +- +- bus-width = <4>; +- max-frequency = <50000000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_msc0>; +- +- non-removable; +-}; +- +-&msc1 { +- status = "okay"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- bus-width = <4>; +- max-frequency = <50000000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_msc1>; +- +- non-removable; +- +- mmc-pwrseq = <&wlan_pwrseq>; +- +- ap6212a: wifi@1 { +- compatible = "brcm,bcm4329-fmac"; +- reg = <1>; +- +- interrupt-parent = <&gpc>; +- interrupts = <25 IRQ_TYPE_EDGE_FALLING>; +- interrupt-names = "host-wake"; +- +- brcm,drive-strength = <10>; +- }; +-}; +- +-&mac { +- status = "okay"; +- +- phy-mode = "rmii"; +- phy-handle = <&ip101gr>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_mac>; +- +- snps,reset-gpio = <&gpb 28 GPIO_ACTIVE_LOW>; /* PB28 */ +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 30000>; +-}; +- +-&mdio { +- status = "okay"; +- +- ip101gr: ethernet-phy@0 { +- compatible = "ethernet-phy-id0243.0c54", "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +-}; +- +-&otg_phy { +- status = "okay"; +-}; +- +-&otg { +- status = "okay"; +-}; +- +-&pinctrl { +- pins_uart1: uart1 { +- function = "uart1"; +- groups = "uart1-data"; +- bias-pull-up; +- }; +- +- pins_i2c0: i2c0 { +- function = "i2c0"; +- groups = "i2c0-data"; +- bias-pull-up; +- }; +- +- pins_msc0: msc0 { +- function = "mmc0"; +- groups = "mmc0-1bit", "mmc0-4bit"; +- bias-disable; +- }; +- +- pins_msc1: msc1 { +- function = "mmc1"; +- groups = "mmc1-1bit", "mmc1-4bit"; +- bias-disable; +- }; +- +- pins_mac: mac { +- function = "mac"; +- groups = "mac"; +- bias-disable; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ingenic/gcw0.dts b/scripts/dtc/include-prefixes/mips/ingenic/gcw0.dts +deleted file mode 100644 +index 4abb0318416c..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ingenic/gcw0.dts ++++ /dev/null +@@ -1,545 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "jz4770.dtsi" +-#include +- +-#include +-#include +-#include +- +-/ { +- compatible = "gcw,zero", "ingenic,jz4770"; +- model = "GCW Zero"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- }; +- +- memory: memory { +- device_type = "memory"; +- reg = <0x0 0x10000000>, +- <0x30000000 0x10000000>; +- }; +- +- chosen { +- stdout-path = "serial2:57600n8"; +- }; +- +- vcc: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc"; +- +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- mmc1_power: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "mmc1_vcc"; +- gpio = <&gpe 9 0>; +- +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc>; +- }; +- +- headphones_amp: analog-amplifier@0 { +- compatible = "simple-audio-amplifier"; +- enable-gpios = <&gpf 3 GPIO_ACTIVE_LOW>; +- enable-delay-ms = <50>; +- +- VCC-supply = <&ldo5>; +- sound-name-prefix = "Headphones Amp"; +- }; +- +- speaker_amp: analog-amplifier@1 { +- compatible = "simple-audio-amplifier"; +- enable-gpios = <&gpf 20 GPIO_ACTIVE_HIGH>; +- +- VCC-supply = <&ldo5>; +- sound-name-prefix = "Speaker Amp"; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- +- simple-audio-card,name = "gcw0-audio"; +- simple-audio-card,format = "i2s"; +- +- simple-audio-card,widgets = +- "Speaker", "Speaker", +- "Headphone", "Headphones", +- "Microphone", "Built-in Mic"; +- simple-audio-card,routing = +- "Headphones Amp INL", "LHPOUT", +- "Headphones Amp INR", "RHPOUT", +- "Headphones", "Headphones Amp OUTL", +- "Headphones", "Headphones Amp OUTR", +- "Speaker Amp INL", "LOUT", +- "Speaker Amp INR", "ROUT", +- "Speaker", "Speaker Amp OUTL", +- "Speaker", "Speaker Amp OUTR", +- "LLINEIN", "Cap-less", +- "RLINEIN", "Cap-less", +- "Built-in Mic", "MICBIAS", +- "MIC1P", "Built-in Mic", +- "MIC1N", "Built-in Mic"; +- simple-audio-card,pin-switches = "Speaker", "Headphones"; +- +- simple-audio-card,hp-det-gpio = <&gpf 21 GPIO_ACTIVE_LOW>; +- simple-audio-card,aux-devs = <&speaker_amp>, <&headphones_amp>; +- +- simple-audio-card,bitclock-master = <&dai_codec>; +- simple-audio-card,frame-master = <&dai_codec>; +- +- dai_cpu: simple-audio-card,cpu { +- sound-dai = <&aic>; +- }; +- +- dai_codec: simple-audio-card,codec { +- sound-dai = <&codec>; +- }; +- }; +- +- rumble { +- compatible = "pwm-vibrator"; +- pwms = <&pwm 4 2000000 0>; +- pwm-names = "enable"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_pwm4>; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 1 40000 0>; +- power-supply = <&vcc>; +- +- brightness-levels = <0 16 32 48 64 80 96 112 128 +- 144 160 176 192 208 224 240 255>; +- default-brightness-level = <12>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_pwm1>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- autorepeat; +- +- button@0 { +- label = "D-pad up"; +- linux,code = ; +- linux,can-disable; +- gpios = <&gpe 21 GPIO_ACTIVE_LOW>; +- }; +- +- button@1 { +- label = "D-pad down"; +- linux,code = ; +- linux,can-disable; +- gpios = <&gpe 25 GPIO_ACTIVE_LOW>; +- }; +- +- button@2 { +- label = "D-pad left"; +- linux,code = ; +- linux,can-disable; +- gpios = <&gpe 23 GPIO_ACTIVE_LOW>; +- }; +- +- button@3 { +- label = "D-pad right"; +- linux,code = ; +- linux,can-disable; +- gpios = <&gpe 24 GPIO_ACTIVE_LOW>; +- }; +- +- button@4 { +- label = "Button A"; +- linux,code = ; +- linux,can-disable; +- gpios = <&gpe 29 GPIO_ACTIVE_LOW>; +- }; +- +- button@5 { +- label = "Button B"; +- linux,code = ; +- linux,can-disable; +- gpios = <&gpe 20 GPIO_ACTIVE_LOW>; +- }; +- +- button@6 { +- label = "Button Y"; +- linux,code = ; +- linux,can-disable; +- gpios = <&gpe 27 GPIO_ACTIVE_LOW>; +- }; +- +- button@7 { +- label = "Button X"; +- linux,code = ; +- linux,can-disable; +- gpios = <&gpe 28 GPIO_ACTIVE_LOW>; +- }; +- +- button@8 { +- label = "Left shoulder button"; +- linux,code = ; +- linux,can-disable; +- gpios = <&gpb 20 GPIO_ACTIVE_LOW>; +- }; +- +- button@9 { +- label = "Right shoulder button"; +- linux,code = ; +- linux,can-disable; +- gpios = <&gpe 26 GPIO_ACTIVE_LOW>; +- }; +- +- button@10 { +- label = "Start button"; +- linux,code = ; +- linux,can-disable; +- gpios = <&gpb 21 GPIO_ACTIVE_LOW>; +- }; +- +- button@11 { +- label = "Select button"; +- linux,code = ; +- linux,can-disable; +- /* +- * This is the only button that is active high, +- * since it doubles as BOOT_SEL1. +- */ +- gpios = <&gpd 18 GPIO_ACTIVE_HIGH>; +- }; +- +- button@12 { +- label = "Power slider"; +- linux,code = ; +- linux,can-disable; +- gpios = <&gpa 30 GPIO_ACTIVE_LOW>; +- wakeup-source; +- }; +- +- button@13 { +- label = "Power hold"; +- linux,code = ; +- linux,can-disable; +- gpios = <&gpf 11 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- i2c3: i2c-controller@3 { +- compatible = "i2c-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- sda-gpios = <&gpd 5 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&gpd 4 GPIO_ACTIVE_HIGH>; +- i2c-gpio,delay-us = <2>; /* 250 kHz */ +- +- act8600: pmic@5a { +- compatible = "active-semi,act8600"; +- reg = <0x5a>; +- +- regulators { +- /* USB OTG */ +- otg_vbus: SUDCDC_REG4 { +- /* +- * 5.3V instead of 5.0V to compensate +- * for the voltage drop of a diode +- * between the regulator and the +- * connector. +- */ +- regulator-min-microvolt = <5300000>; +- regulator-max-microvolt = <5300000>; +- inl-supply = <&vcc>; +- }; +- +- /* +- * When this is off, there is no sound, but also +- * no USB networking. +- */ +- ldo5: LDO5 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2500000>; +- inl-supply = <&vcc>; +- }; +- +- /* LCD panel and FM radio */ +- ldo6: LDO6 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- inl-supply = <&vcc>; +- }; +- +- /* ??? */ +- LDO7 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- /*regulator-always-on;*/ +- inl-supply = <&vcc>; +- }; +- +- /* +- * The colors on the LCD are wrong when this is +- * off. Which is strange, since the LCD panel +- * data sheet only mentions a 3.3V input. +- */ +- LDO8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- inl-supply = <&vcc>; +- }; +- +- /* RTC fixed 3.3V */ +- LDO_REG9 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- inl-supply = <&vcc>; +- }; +- +- /* Unused fixed 1.2V */ +- LDO_REG10 { +- inl-supply = <&vcc>; +- }; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led { +- gpios = <&gpb 30 GPIO_ACTIVE_LOW>; +- default-state = "on"; +- }; +- }; +- +- spi { +- compatible = "spi-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- sck-gpios = <&gpe 15 GPIO_ACTIVE_HIGH>; +- mosi-gpios = <&gpe 17 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&gpe 16 GPIO_ACTIVE_HIGH>; +- num-chipselects = <1>; +- +- nt39016@0 { +- compatible = "kingdisplay,kd035g6-54nt"; +- reg = <0>; +- +- spi-max-frequency = <3125000>; +- spi-3wire; +- +- reset-gpios = <&gpe 2 GPIO_ACTIVE_LOW>; +- +- backlight = <&backlight>; +- power-supply = <&ldo6>; +- +- port { +- panel_input: endpoint { +- remote-endpoint = <&panel_output>; +- }; +- }; +- }; +- }; +- +- connector { +- compatible = "gpio-usb-b-connector", "usb-b-connector"; +- label = "mini-USB"; +- type = "mini"; +- +- /* +- * USB OTG is not yet working reliably, the ID detection +- * mechanism tends to fry easily for unknown reasons. +- * Until this is fixed, disable OTG by not providing the +- * ID GPIO to the driver. +- */ +- //id-gpios = <&gpf 18 GPIO_ACTIVE_LOW>; +- +- vbus-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; +- vbus-supply = <&otg_vbus>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_otg>; +- +- port { +- usb_ep: endpoint { +- remote-endpoint = <&usb_otg_ep>; +- }; +- }; +- }; +-}; +- +-&ext { +- clock-frequency = <12000000>; +-}; +- +-&pinctrl { +- pins_lcd: lcd { +- function = "lcd"; +- groups = "lcd-24bit"; +- }; +- +- pins_uart2: uart2 { +- function = "uart2"; +- groups = "uart2-data"; +- }; +- +- pins_mmc0: mmc0 { +- function = "mmc0"; +- groups = "mmc0-1bit-a", "mmc0-4bit-a"; +- }; +- +- pins_mmc1: mmc1 { +- function = "mmc1"; +- groups = "mmc1-1bit-d", "mmc1-4bit-d"; +- }; +- +- pins_otg: otg { +- otg-vbus-pin { +- function = "otg"; +- groups = "otg-vbus"; +- }; +- +- vbus-pin { +- pins = "PB5"; +- bias-disable; +- }; +- }; +- +- pins_pwm1: pwm1 { +- function = "pwm1"; +- groups = "pwm1"; +- }; +- +- pins_pwm4: pwm4 { +- function = "pwm4"; +- groups = "pwm4"; +- }; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_uart2>; +- +- status = "okay"; +-}; +- +-&cgu { +- /* +- * Put high-speed peripherals under PLL1, such that we can change the +- * PLL0 frequency on demand without having to suspend peripherals. +- * We use a rate of 432 MHz, which is the least common multiple of +- * 27 MHz (required by TV encoder) and 48 MHz (required by USB host). +- * Put the GPU under PLL0 since we want a higher frequency. +- * Use the 32 kHz oscillator as the parent of the RTC for a higher +- * precision. +- */ +- assigned-clocks = +- <&cgu JZ4770_CLK_PLL1>, +- <&cgu JZ4770_CLK_GPU>, +- <&cgu JZ4770_CLK_RTC>, +- <&cgu JZ4770_CLK_UHC>, +- <&cgu JZ4770_CLK_LPCLK_MUX>, +- <&cgu JZ4770_CLK_MMC0_MUX>, +- <&cgu JZ4770_CLK_MMC1_MUX>; +- assigned-clock-parents = +- <0>, +- <&cgu JZ4770_CLK_PLL0>, +- <&cgu JZ4770_CLK_OSC32K>, +- <&cgu JZ4770_CLK_PLL1>, +- <&cgu JZ4770_CLK_PLL1>, +- <&cgu JZ4770_CLK_PLL1>, +- <&cgu JZ4770_CLK_PLL1>; +- assigned-clock-rates = +- <432000000>, +- <600000000>; +-}; +- +-&uhc { +- /* The WiFi module is connected to the UHC. */ +- status = "okay"; +-}; +- +-&tcu { +- /* +- * 750 kHz for the system timer and clocksource, 12 MHz for the OST, +- * and use RTC as the parent for the watchdog clock +- */ +- assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>, +- <&tcu TCU_CLK_OST>, <&tcu TCU_CLK_WDT>; +- assigned-clock-parents = <0>, <0>, <0>, <&cgu JZ4770_CLK_RTC>; +- assigned-clock-rates = <750000>, <750000>, <12000000>; +- +- /* PWM1 is in use, so use channel #2 for the clocksource */ +- ingenic,pwm-channels-mask = <0xfa>; +-}; +- +-&usb_otg { +- port { +- usb_otg_ep: endpoint { +- remote-endpoint = <&usb_ep>; +- }; +- }; +-}; +- +-&otg_phy { +- vcc-supply = <&ldo5>; +-}; +- +-&rtc { +- clocks = <&cgu JZ4770_CLK_RTC>; +- clock-names = "rtc"; +- +- system-power-controller; +-}; +- +-&mmc0 { +- status = "okay"; +- +- bus-width = <4>; +- max-frequency = <48000000>; +- vmmc-supply = <&vcc>; +- non-removable; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_mmc0>; +-}; +- +-&mmc1 { +- status = "okay"; +- +- bus-width = <4>; +- max-frequency = <48000000>; +- cd-gpios = <&gpb 2 GPIO_ACTIVE_LOW>; +- vmmc-supply = <&mmc1_power>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_mmc1>; +-}; +- +-&lcd { +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_lcd>; +- +- port { +- panel_output: endpoint { +- remote-endpoint = <&panel_input>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ingenic/gcw0_proto.dts b/scripts/dtc/include-prefixes/mips/ingenic/gcw0_proto.dts +deleted file mode 100644 +index 02df22f8ae0f..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ingenic/gcw0_proto.dts ++++ /dev/null +@@ -1,13 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "gcw0.dts" +- +-/ { +- model = "GCW Zero Prototype"; +-}; +- +-&memory { +- /* Prototype has only 256 MiB of RAM */ +- reg = <0x0 0x10000000>; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ingenic/jz4725b.dtsi b/scripts/dtc/include-prefixes/mips/ingenic/jz4725b.dtsi +deleted file mode 100644 +index a1f0b71c9223..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ingenic/jz4725b.dtsi ++++ /dev/null +@@ -1,378 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ingenic,jz4725b"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "ingenic,xburst-mxu1.0"; +- reg = <0>; +- +- clocks = <&cgu JZ4725B_CLK_CCLK>; +- clock-names = "cpu"; +- }; +- }; +- +- cpuintc: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- intc: interrupt-controller@10001000 { +- compatible = "ingenic,jz4725b-intc", "ingenic,jz4740-intc"; +- reg = <0x10001000 0x14>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <2>; +- }; +- +- ext: ext { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- }; +- +- osc32k: osc32k { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- cgu: clock-controller@10000000 { +- compatible = "ingenic,jz4725b-cgu"; +- reg = <0x10000000 0x100>; +- +- clocks = <&ext>, <&osc32k>; +- clock-names = "ext", "osc32k"; +- +- #clock-cells = <1>; +- }; +- +- tcu: timer@10002000 { +- compatible = "ingenic,jz4725b-tcu", "simple-mfd"; +- reg = <0x10002000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10002000 0x1000>; +- +- #clock-cells = <1>; +- +- clocks = <&cgu JZ4725B_CLK_RTC>, +- <&cgu JZ4725B_CLK_EXT>, +- <&cgu JZ4725B_CLK_PCLK>, +- <&cgu JZ4725B_CLK_TCU>; +- clock-names = "rtc", "ext", "pclk", "tcu"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&intc>; +- interrupts = <23>, <22>, <21>; +- +- watchdog: watchdog@0 { +- compatible = "ingenic,jz4725b-watchdog", "ingenic,jz4740-watchdog"; +- reg = <0x0 0xc>; +- +- clocks = <&tcu TCU_CLK_WDT>; +- clock-names = "wdt"; +- }; +- +- pwm: pwm@60 { +- compatible = "ingenic,jz4725b-pwm"; +- reg = <0x60 0x40>; +- +- #pwm-cells = <3>; +- +- clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, +- <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>, +- <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>; +- clock-names = "timer0", "timer1", "timer2", +- "timer3", "timer4", "timer5"; +- }; +- +- ost: timer@e0 { +- compatible = "ingenic,jz4725b-ost"; +- reg = <0xe0 0x20>; +- +- clocks = <&tcu TCU_CLK_OST>; +- clock-names = "ost"; +- +- interrupts = <15>; +- }; +- }; +- +- rtc_dev: rtc@10003000 { +- compatible = "ingenic,jz4725b-rtc", "ingenic,jz4740-rtc"; +- reg = <0x10003000 0x40>; +- +- interrupt-parent = <&intc>; +- interrupts = <6>; +- +- clocks = <&cgu JZ4725B_CLK_RTC>; +- clock-names = "rtc"; +- }; +- +- pinctrl: pinctrl@10010000 { +- compatible = "ingenic,jz4725b-pinctrl"; +- reg = <0x10010000 0x400>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpa: gpio@0 { +- compatible = "ingenic,jz4725b-gpio"; +- reg = <0>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 0 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <16>; +- }; +- +- gpb: gpio@1 { +- compatible = "ingenic,jz4725b-gpio"; +- reg = <1>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 32 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <15>; +- }; +- +- gpc: gpio@2 { +- compatible = "ingenic,jz4725b-gpio"; +- reg = <2>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 64 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <14>; +- }; +- +- gpd: gpio@3 { +- compatible = "ingenic,jz4725b-gpio"; +- reg = <3>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 96 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <13>; +- }; +- }; +- +- aic: audio-controller@10020000 { +- compatible = "ingenic,jz4725b-i2s", "ingenic,jz4740-i2s"; +- reg = <0x10020000 0x38>; +- +- #sound-dai-cells = <0>; +- +- clocks = <&cgu JZ4725B_CLK_AIC>, +- <&cgu JZ4725B_CLK_I2S>, +- <&cgu JZ4725B_CLK_EXT>, +- <&cgu JZ4725B_CLK_PLL_HALF>; +- clock-names = "aic", "i2s", "ext", "pll half"; +- +- interrupt-parent = <&intc>; +- interrupts = <10>; +- +- dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>; +- dma-names = "rx", "tx"; +- }; +- +- codec: audio-codec@100200a4 { +- compatible = "ingenic,jz4725b-codec"; +- reg = <0x100200a4 0x8>; +- +- #sound-dai-cells = <0>; +- +- clocks = <&cgu JZ4725B_CLK_AIC>; +- clock-names = "aic"; +- }; +- +- mmc0: mmc@10021000 { +- compatible = "ingenic,jz4725b-mmc"; +- reg = <0x10021000 0x1000>; +- +- clocks = <&cgu JZ4725B_CLK_MMC0>; +- clock-names = "mmc"; +- +- interrupt-parent = <&intc>; +- interrupts = <25>; +- +- dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>; +- dma-names = "rx", "tx"; +- +- cap-sd-highspeed; +- cap-mmc-highspeed; +- cap-sdio-irq; +- }; +- +- mmc1: mmc@10022000 { +- compatible = "ingenic,jz4725b-mmc"; +- reg = <0x10022000 0x1000>; +- +- clocks = <&cgu JZ4725B_CLK_MMC1>; +- clock-names = "mmc"; +- +- interrupt-parent = <&intc>; +- interrupts = <24>; +- +- dmas = <&dmac 31 0xffffffff>, <&dmac 30 0xffffffff>; +- dma-names = "rx", "tx"; +- +- cap-sd-highspeed; +- cap-mmc-highspeed; +- cap-sdio-irq; +- }; +- +- uart: serial@10030000 { +- compatible = "ingenic,jz4725b-uart", "ingenic,jz4740-uart"; +- reg = <0x10030000 0x100>; +- +- interrupt-parent = <&intc>; +- interrupts = <9>; +- +- clocks = <&ext>, <&cgu JZ4725B_CLK_UART>; +- clock-names = "baud", "module"; +- }; +- +- adc: adc@10070000 { +- compatible = "ingenic,jz4725b-adc"; +- #io-channel-cells = <1>; +- +- reg = <0x10070000 0x30>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10070000 0x30>; +- +- clocks = <&cgu JZ4725B_CLK_ADC>; +- clock-names = "adc"; +- +- interrupt-parent = <&intc>; +- interrupts = <18>; +- }; +- +- nemc: memory-controller@13010000 { +- compatible = "ingenic,jz4725b-nemc", "ingenic,jz4740-nemc"; +- reg = <0x13010000 0x10000>; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <1 0 0x18000000 0x4000000>, <2 0 0x14000000 0x4000000>, +- <3 0 0x0c000000 0x4000000>, <4 0 0x08000000 0x4000000>; +- +- clocks = <&cgu JZ4725B_CLK_MCLK>; +- }; +- +- dmac: dma-controller@13020000 { +- compatible = "ingenic,jz4725b-dma"; +- reg = <0x13020000 0xd8>, <0x13020300 0x14>; +- +- #dma-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <29>; +- +- clocks = <&cgu JZ4725B_CLK_DMA>; +- }; +- +- udc: usb@13040000 { +- compatible = "ingenic,jz4725b-musb", "ingenic,jz4740-musb"; +- reg = <0x13040000 0x10000>; +- +- interrupt-parent = <&intc>; +- interrupts = <27>; +- interrupt-names = "mc"; +- +- clocks = <&cgu JZ4725B_CLK_UDC>; +- clock-names = "udc"; +- }; +- +- lcd: lcd-controller@13050000 { +- compatible = "ingenic,jz4725b-lcd"; +- reg = <0x13050000 0x1000>; +- +- interrupt-parent = <&intc>; +- interrupts = <31>; +- +- clocks = <&cgu JZ4725B_CLK_LCD>; +- clock-names = "lcd_pclk"; +- +- lcd_ports: ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@8 { +- reg = <8>; +- +- ipu_output: endpoint { +- remote-endpoint = <&ipu_input>; +- }; +- }; +- }; +- }; +- +- ipu: ipu@13080000 { +- compatible = "ingenic,jz4725b-ipu"; +- reg = <0x13080000 0x64>; +- +- interrupt-parent = <&intc>; +- interrupts = <30>; +- +- clocks = <&cgu JZ4725B_CLK_IPU>; +- clock-names = "ipu"; +- +- port { +- ipu_input: endpoint { +- remote-endpoint = <&ipu_output>; +- }; +- }; +- }; +- +- bch: ecc-controller@130d0000 { +- compatible = "ingenic,jz4725b-bch"; +- reg = <0x130d0000 0x44>; +- +- clocks = <&cgu JZ4725B_CLK_BCH>; +- }; +- +- rom: memory@1fc00000 { +- compatible = "mtd-rom"; +- probe-type = "map_rom"; +- reg = <0x1fc00000 0x2000>; +- +- bank-width = <4>; +- device-width = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ingenic/jz4740.dtsi b/scripts/dtc/include-prefixes/mips/ingenic/jz4740.dtsi +deleted file mode 100644 +index c1afdfdaa8a3..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ingenic/jz4740.dtsi ++++ /dev/null +@@ -1,334 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ingenic,jz4740"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "ingenic,xburst-mxu1.0"; +- reg = <0>; +- +- clocks = <&cgu JZ4740_CLK_CCLK>; +- clock-names = "cpu"; +- }; +- }; +- +- cpuintc: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- intc: interrupt-controller@10001000 { +- compatible = "ingenic,jz4740-intc"; +- reg = <0x10001000 0x14>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <2>; +- }; +- +- ext: ext { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- }; +- +- rtc: rtc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- cgu: jz4740-cgu@10000000 { +- compatible = "ingenic,jz4740-cgu"; +- reg = <0x10000000 0x100>; +- +- clocks = <&ext>, <&rtc>; +- clock-names = "ext", "rtc"; +- +- #clock-cells = <1>; +- }; +- +- tcu: timer@10002000 { +- compatible = "ingenic,jz4740-tcu", "simple-mfd"; +- reg = <0x10002000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10002000 0x1000>; +- +- #clock-cells = <1>; +- +- clocks = <&cgu JZ4740_CLK_RTC>, +- <&cgu JZ4740_CLK_EXT>, +- <&cgu JZ4740_CLK_PCLK>, +- <&cgu JZ4740_CLK_TCU>; +- clock-names = "rtc", "ext", "pclk", "tcu"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&intc>; +- interrupts = <23 22 21>; +- +- watchdog: watchdog@0 { +- compatible = "ingenic,jz4740-watchdog"; +- reg = <0x0 0xc>; +- +- clocks = <&tcu TCU_CLK_WDT>; +- clock-names = "wdt"; +- }; +- +- pwm: pwm@40 { +- compatible = "ingenic,jz4740-pwm"; +- reg = <0x40 0x80>; +- +- #pwm-cells = <3>; +- +- clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, +- <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>, +- <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>, +- <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>; +- clock-names = "timer0", "timer1", "timer2", "timer3", +- "timer4", "timer5", "timer6", "timer7"; +- }; +- }; +- +- rtc_dev: rtc@10003000 { +- compatible = "ingenic,jz4740-rtc"; +- reg = <0x10003000 0x40>; +- +- interrupt-parent = <&intc>; +- interrupts = <15>; +- +- clocks = <&cgu JZ4740_CLK_RTC>; +- clock-names = "rtc"; +- }; +- +- pinctrl: pin-controller@10010000 { +- compatible = "ingenic,jz4740-pinctrl"; +- reg = <0x10010000 0x400>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpa: gpio@0 { +- compatible = "ingenic,jz4740-gpio"; +- reg = <0>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 0 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <28>; +- }; +- +- gpb: gpio@1 { +- compatible = "ingenic,jz4740-gpio"; +- reg = <1>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 32 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <27>; +- }; +- +- gpc: gpio@2 { +- compatible = "ingenic,jz4740-gpio"; +- reg = <2>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 64 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <26>; +- }; +- +- gpd: gpio@3 { +- compatible = "ingenic,jz4740-gpio"; +- reg = <3>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 96 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <25>; +- }; +- }; +- +- aic: audio-controller@10020000 { +- compatible = "ingenic,jz4740-i2s"; +- reg = <0x10020000 0x38>; +- +- #sound-dai-cells = <0>; +- +- interrupt-parent = <&intc>; +- interrupts = <18>; +- +- clocks = <&cgu JZ4740_CLK_AIC>, +- <&cgu JZ4740_CLK_I2S>, +- <&cgu JZ4740_CLK_EXT>, +- <&cgu JZ4740_CLK_PLL_HALF>; +- clock-names = "aic", "i2s", "ext", "pll half"; +- +- dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>; +- dma-names = "rx", "tx"; +- }; +- +- codec: audio-codec@100200a4 { +- compatible = "ingenic,jz4740-codec"; +- reg = <0x10020080 0x8>; +- +- #sound-dai-cells = <0>; +- +- clocks = <&cgu JZ4740_CLK_AIC>; +- clock-names = "aic"; +- }; +- +- mmc: mmc@10021000 { +- compatible = "ingenic,jz4740-mmc"; +- reg = <0x10021000 0x1000>; +- +- clocks = <&cgu JZ4740_CLK_MMC>; +- clock-names = "mmc"; +- +- interrupt-parent = <&intc>; +- interrupts = <14>; +- +- dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>; +- dma-names = "rx", "tx"; +- +- cap-sd-highspeed; +- cap-mmc-highspeed; +- cap-sdio-irq; +- }; +- +- uart0: serial@10030000 { +- compatible = "ingenic,jz4740-uart"; +- reg = <0x10030000 0x100>; +- +- interrupt-parent = <&intc>; +- interrupts = <9>; +- +- clocks = <&ext>, <&cgu JZ4740_CLK_UART0>; +- clock-names = "baud", "module"; +- }; +- +- uart1: serial@10031000 { +- compatible = "ingenic,jz4740-uart"; +- reg = <0x10031000 0x100>; +- +- interrupt-parent = <&intc>; +- interrupts = <8>; +- +- clocks = <&ext>, <&cgu JZ4740_CLK_UART1>; +- clock-names = "baud", "module"; +- }; +- +- adc: adc@10070000 { +- compatible = "ingenic,jz4740-adc"; +- reg = <0x10070000 0x30>; +- #io-channel-cells = <1>; +- +- clocks = <&cgu JZ4740_CLK_ADC>; +- clock-names = "adc"; +- +- interrupt-parent = <&intc>; +- interrupts = <12>; +- }; +- +- nemc: memory-controller@13010000 { +- compatible = "ingenic,jz4740-nemc"; +- reg = <0x13010000 0x54>; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <1 0 0x18000000 0x4000000>, +- <2 0 0x14000000 0x4000000>, +- <3 0 0x0c000000 0x4000000>, +- <4 0 0x08000000 0x4000000>; +- +- clocks = <&cgu JZ4740_CLK_MCLK>; +- }; +- +- ecc: ecc-controller@13010100 { +- compatible = "ingenic,jz4740-ecc"; +- reg = <0x13010100 0x2C>; +- +- clocks = <&cgu JZ4740_CLK_MCLK>; +- }; +- +- dmac: dma-controller@13020000 { +- compatible = "ingenic,jz4740-dma"; +- reg = <0x13020000 0xbc>, <0x13020300 0x14>; +- #dma-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <20>; +- +- clocks = <&cgu JZ4740_CLK_DMA>; +- }; +- +- uhc: usb@13030000 { +- compatible = "ingenic,jz4740-ohci", "generic-ohci"; +- reg = <0x13030000 0x1000>; +- +- clocks = <&cgu JZ4740_CLK_UHC>; +- assigned-clocks = <&cgu JZ4740_CLK_UHC>; +- assigned-clock-rates = <48000000>; +- +- interrupt-parent = <&intc>; +- interrupts = <3>; +- +- status = "disabled"; +- }; +- +- udc: usb@13040000 { +- compatible = "ingenic,jz4740-musb"; +- reg = <0x13040000 0x10000>; +- +- interrupt-parent = <&intc>; +- interrupts = <24>; +- interrupt-names = "mc"; +- +- clocks = <&cgu JZ4740_CLK_UDC>; +- clock-names = "udc"; +- }; +- +- lcd: lcd-controller@13050000 { +- compatible = "ingenic,jz4740-lcd"; +- reg = <0x13050000 0x1000>; +- +- interrupt-parent = <&intc>; +- interrupts = <30>; +- +- clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>; +- clock-names = "lcd_pclk", "lcd"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ingenic/jz4770.dtsi b/scripts/dtc/include-prefixes/mips/ingenic/jz4770.dtsi +deleted file mode 100644 +index 05c00b93088e..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ingenic/jz4770.dtsi ++++ /dev/null +@@ -1,471 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ingenic,jz4770"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "ingenic,xburst-fpu1.0-mxu1.1"; +- reg = <0>; +- +- clocks = <&cgu JZ4770_CLK_CCLK>; +- clock-names = "cpu"; +- }; +- }; +- +- cpuintc: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- intc: interrupt-controller@10001000 { +- compatible = "ingenic,jz4770-intc"; +- reg = <0x10001000 0x40>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <2>; +- }; +- +- ext: ext { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- }; +- +- osc32k: osc32k { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- cgu: jz4770-cgu@10000000 { +- compatible = "ingenic,jz4770-cgu", "simple-mfd"; +- reg = <0x10000000 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10000000 0x100>; +- +- clocks = <&ext>, <&osc32k>; +- clock-names = "ext", "osc32k"; +- +- #clock-cells = <1>; +- +- otg_phy: usb-phy@3c { +- compatible = "ingenic,jz4770-phy"; +- reg = <0x3c 0x10>; +- +- clocks = <&cgu JZ4770_CLK_OTG_PHY>; +- +- #phy-cells = <0>; +- }; +- }; +- +- tcu: timer@10002000 { +- compatible = "ingenic,jz4770-tcu", "simple-mfd"; +- reg = <0x10002000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10002000 0x1000>; +- +- #clock-cells = <1>; +- +- clocks = <&cgu JZ4770_CLK_RTC>, +- <&cgu JZ4770_CLK_EXT>, +- <&cgu JZ4770_CLK_PCLK>; +- clock-names = "rtc", "ext", "pclk"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&intc>; +- interrupts = <27 26 25>; +- +- watchdog: watchdog@0 { +- compatible = "ingenic,jz4770-watchdog", +- "ingenic,jz4740-watchdog"; +- reg = <0x0 0xc>; +- +- clocks = <&tcu TCU_CLK_WDT>; +- clock-names = "wdt"; +- }; +- +- pwm: pwm@40 { +- compatible = "ingenic,jz4770-pwm", "ingenic,jz4740-pwm"; +- reg = <0x40 0x80>; +- +- #pwm-cells = <3>; +- +- clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, +- <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>, +- <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>, +- <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>; +- clock-names = "timer0", "timer1", "timer2", "timer3", +- "timer4", "timer5", "timer6", "timer7"; +- }; +- +- ost: timer@e0 { +- compatible = "ingenic,jz4770-ost"; +- reg = <0xe0 0x20>; +- +- clocks = <&tcu TCU_CLK_OST>; +- clock-names = "ost"; +- +- interrupts = <15>; +- }; +- }; +- +- rtc: rtc@10003000 { +- compatible = "ingenic,jz4770-rtc", "ingenic,jz4760-rtc"; +- reg = <0x10003000 0x40>; +- +- interrupt-parent = <&intc>; +- interrupts = <32>; +- }; +- +- pinctrl: pin-controller@10010000 { +- compatible = "ingenic,jz4770-pinctrl"; +- reg = <0x10010000 0x600>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpa: gpio@0 { +- compatible = "ingenic,jz4770-gpio"; +- reg = <0>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 0 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <17>; +- }; +- +- gpb: gpio@1 { +- compatible = "ingenic,jz4770-gpio"; +- reg = <1>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 32 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <16>; +- }; +- +- gpc: gpio@2 { +- compatible = "ingenic,jz4770-gpio"; +- reg = <2>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 64 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <15>; +- }; +- +- gpd: gpio@3 { +- compatible = "ingenic,jz4770-gpio"; +- reg = <3>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 96 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <14>; +- }; +- +- gpe: gpio@4 { +- compatible = "ingenic,jz4770-gpio"; +- reg = <4>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 128 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <13>; +- }; +- +- gpf: gpio@5 { +- compatible = "ingenic,jz4770-gpio"; +- reg = <5>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 160 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <12>; +- }; +- }; +- +- aic: audio-controller@10020000 { +- compatible = "ingenic,jz4770-i2s"; +- reg = <0x10020000 0x94>; +- +- #sound-dai-cells = <0>; +- +- clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>, +- <&cgu JZ4770_CLK_EXT>, <&cgu JZ4770_CLK_PLL0>; +- clock-names = "aic", "i2s", "ext", "pll half"; +- +- interrupt-parent = <&intc>; +- interrupts = <34>; +- +- dmas = <&dmac0 25 0xffffffff>, <&dmac0 24 0xffffffff>; +- dma-names = "rx", "tx"; +- }; +- +- codec: audio-codec@100200a0 { +- compatible = "ingenic,jz4770-codec"; +- reg = <0x100200a4 0x8>; +- +- #sound-dai-cells = <0>; +- +- clocks = <&cgu JZ4770_CLK_AIC>; +- clock-names = "aic"; +- }; +- +- mmc0: mmc@10021000 { +- compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc"; +- reg = <0x10021000 0x1000>; +- +- clocks = <&cgu JZ4770_CLK_MMC0>; +- clock-names = "mmc"; +- +- interrupt-parent = <&intc>; +- interrupts = <37>; +- +- dmas = <&dmac1 27 0xffffffff>, <&dmac1 26 0xffffffff>; +- dma-names = "rx", "tx"; +- +- cap-sd-highspeed; +- cap-mmc-highspeed; +- cap-sdio-irq; +- +- status = "disabled"; +- }; +- +- mmc1: mmc@10022000 { +- compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc"; +- reg = <0x10022000 0x1000>; +- +- clocks = <&cgu JZ4770_CLK_MMC1>; +- clock-names = "mmc"; +- +- interrupt-parent = <&intc>; +- interrupts = <36>; +- +- dmas = <&dmac1 31 0xffffffff>, <&dmac1 30 0xffffffff>; +- dma-names = "rx", "tx"; +- +- cap-sd-highspeed; +- cap-mmc-highspeed; +- cap-sdio-irq; +- +- status = "disabled"; +- }; +- +- mmc2: mmc@10023000 { +- compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc"; +- reg = <0x10023000 0x1000>; +- +- clocks = <&cgu JZ4770_CLK_MMC2>; +- clock-names = "mmc"; +- +- interrupt-parent = <&intc>; +- interrupts = <35>; +- +- dmas = <&dmac1 37 0xffffffff>, <&dmac1 36 0xffffffff>; +- dma-names = "rx", "tx"; +- +- cap-sd-highspeed; +- cap-mmc-highspeed; +- cap-sdio-irq; +- +- status = "disabled"; +- }; +- +- uart0: serial@10030000 { +- compatible = "ingenic,jz4770-uart"; +- reg = <0x10030000 0x100>; +- +- clocks = <&ext>, <&cgu JZ4770_CLK_UART0>; +- clock-names = "baud", "module"; +- +- interrupt-parent = <&intc>; +- interrupts = <5>; +- +- status = "disabled"; +- }; +- +- uart1: serial@10031000 { +- compatible = "ingenic,jz4770-uart"; +- reg = <0x10031000 0x100>; +- +- clocks = <&ext>, <&cgu JZ4770_CLK_UART1>; +- clock-names = "baud", "module"; +- +- interrupt-parent = <&intc>; +- interrupts = <4>; +- +- status = "disabled"; +- }; +- +- uart2: serial@10032000 { +- compatible = "ingenic,jz4770-uart"; +- reg = <0x10032000 0x100>; +- +- clocks = <&ext>, <&cgu JZ4770_CLK_UART2>; +- clock-names = "baud", "module"; +- +- interrupt-parent = <&intc>; +- interrupts = <3>; +- +- status = "disabled"; +- }; +- +- uart3: serial@10033000 { +- compatible = "ingenic,jz4770-uart"; +- reg = <0x10033000 0x100>; +- +- clocks = <&ext>, <&cgu JZ4770_CLK_UART3>; +- clock-names = "baud", "module"; +- +- interrupt-parent = <&intc>; +- interrupts = <2>; +- +- status = "disabled"; +- }; +- +- adc: adc@10070000 { +- compatible = "ingenic,jz4770-adc"; +- reg = <0x10070000 0x30>; +- +- #io-channel-cells = <1>; +- +- clocks = <&cgu JZ4770_CLK_ADC>; +- clock-names = "adc"; +- +- interrupt-parent = <&intc>; +- interrupts = <18>; +- }; +- +- gpu: gpu@13040000 { +- compatible = "vivante,gc"; +- reg = <0x13040000 0x10000>; +- +- clocks = <&cgu JZ4770_CLK_GPU>, +- <&cgu JZ4770_CLK_GPU>, +- <&cgu JZ4770_CLK_GPU>; +- clock-names = "bus", "core", "shader"; +- +- interrupt-parent = <&intc>; +- interrupts = <6>; +- }; +- +- lcd: lcd-controller@13050000 { +- compatible = "ingenic,jz4770-lcd"; +- reg = <0x13050000 0x300>; +- +- interrupt-parent = <&intc>; +- interrupts = <31>; +- +- clocks = <&cgu JZ4770_CLK_LPCLK_MUX>; +- clock-names = "lcd_pclk"; +- }; +- +- dmac0: dma-controller@13420000 { +- compatible = "ingenic,jz4770-dma"; +- reg = <0x13420000 0xC0>, <0x13420300 0x20>; +- +- #dma-cells = <2>; +- +- clocks = <&cgu JZ4770_CLK_DMA>; +- interrupt-parent = <&intc>; +- interrupts = <24>; +- }; +- +- dmac1: dma-controller@13420100 { +- compatible = "ingenic,jz4770-dma"; +- reg = <0x13420100 0xC0>, <0x13420400 0x20>; +- +- #dma-cells = <2>; +- +- clocks = <&cgu JZ4770_CLK_DMA>; +- interrupt-parent = <&intc>; +- interrupts = <23>; +- }; +- +- uhc: usb@13430000 { +- compatible = "generic-ohci"; +- reg = <0x13430000 0x1000>; +- +- clocks = <&cgu JZ4770_CLK_UHC>, <&cgu JZ4770_CLK_UHC_PHY>; +- assigned-clocks = <&cgu JZ4770_CLK_UHC>; +- assigned-clock-rates = <48000000>; +- +- interrupt-parent = <&intc>; +- interrupts = <20>; +- +- status = "disabled"; +- }; +- +- usb_otg: usb@13440000 { +- compatible = "ingenic,jz4770-musb"; +- reg = <0x13440000 0x10000>; +- +- clocks = <&cgu JZ4770_CLK_OTG>; +- clock-names = "udc"; +- +- interrupt-parent = <&intc>; +- interrupts = <21>; +- interrupt-names = "mc"; +- +- phys = <&otg_phy>; +- +- usb-role-switch; +- }; +- +- rom: memory@1fc00000 { +- compatible = "mtd-rom"; +- probe-type = "map_rom"; +- reg = <0x1fc00000 0x2000>; +- +- bank-width = <4>; +- device-width = <1>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ingenic/jz4780.dtsi b/scripts/dtc/include-prefixes/mips/ingenic/jz4780.dtsi +deleted file mode 100644 +index 9e34f433b9b5..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ingenic/jz4780.dtsi ++++ /dev/null +@@ -1,538 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ingenic,jz4780"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "ingenic,xburst-fpu1.0-mxu1.1"; +- reg = <0>; +- +- clocks = <&cgu JZ4780_CLK_CPU>; +- clock-names = "cpu"; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "ingenic,xburst-fpu1.0-mxu1.1"; +- reg = <1>; +- +- clocks = <&cgu JZ4780_CLK_CORE1>; +- clock-names = "cpu"; +- }; +- }; +- +- cpuintc: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- intc: interrupt-controller@10001000 { +- compatible = "ingenic,jz4780-intc"; +- reg = <0x10001000 0x50>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <2>; +- }; +- +- ext: ext { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- }; +- +- rtc: rtc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- cgu: jz4780-cgu@10000000 { +- compatible = "ingenic,jz4780-cgu", "simple-mfd"; +- reg = <0x10000000 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10000000 0x100>; +- +- #clock-cells = <1>; +- +- clocks = <&ext>, <&rtc>; +- clock-names = "ext", "rtc"; +- +- otg_phy: usb-phy@3c { +- compatible = "ingenic,jz4780-phy"; +- reg = <0x3c 0x10>; +- +- clocks = <&cgu JZ4780_CLK_OTG1>; +- +- #phy-cells = <0>; +- +- status = "disabled"; +- }; +- +- rng: rng@d8 { +- compatible = "ingenic,jz4780-rng"; +- reg = <0xd8 0x8>; +- +- status = "disabled"; +- }; +- }; +- +- tcu: timer@10002000 { +- compatible = "ingenic,jz4780-tcu", +- "ingenic,jz4770-tcu", +- "simple-mfd"; +- reg = <0x10002000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10002000 0x1000>; +- +- #clock-cells = <1>; +- +- clocks = <&cgu JZ4780_CLK_RTCLK>, +- <&cgu JZ4780_CLK_EXCLK>, +- <&cgu JZ4780_CLK_PCLK>; +- clock-names = "rtc", "ext", "pclk"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&intc>; +- interrupts = <27 26 25>; +- +- watchdog: watchdog@0 { +- compatible = "ingenic,jz4780-watchdog"; +- reg = <0x0 0xc>; +- +- clocks = <&tcu TCU_CLK_WDT>; +- clock-names = "wdt"; +- }; +- +- pwm: pwm@40 { +- compatible = "ingenic,jz4780-pwm", "ingenic,jz4740-pwm"; +- reg = <0x40 0x80>; +- +- #pwm-cells = <3>; +- +- clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, +- <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>, +- <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>, +- <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>; +- clock-names = "timer0", "timer1", "timer2", "timer3", +- "timer4", "timer5", "timer6", "timer7"; +- }; +- +- ost: timer@e0 { +- compatible = "ingenic,jz4780-ost", "ingenic,jz4770-ost"; +- reg = <0xe0 0x20>; +- +- clocks = <&tcu TCU_CLK_OST>; +- clock-names = "ost"; +- +- interrupts = <15>; +- }; +- }; +- +- rtc_dev: rtc@10003000 { +- compatible = "ingenic,jz4780-rtc"; +- reg = <0x10003000 0x4c>; +- +- interrupt-parent = <&intc>; +- interrupts = <32>; +- +- clocks = <&cgu JZ4780_CLK_RTCLK>; +- clock-names = "rtc"; +- }; +- +- pinctrl: pin-controller@10010000 { +- compatible = "ingenic,jz4780-pinctrl"; +- reg = <0x10010000 0x600>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpa: gpio@0 { +- compatible = "ingenic,jz4780-gpio"; +- reg = <0>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 0 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <17>; +- }; +- +- gpb: gpio@1 { +- compatible = "ingenic,jz4780-gpio"; +- reg = <1>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 32 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <16>; +- }; +- +- gpc: gpio@2 { +- compatible = "ingenic,jz4780-gpio"; +- reg = <2>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 64 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <15>; +- }; +- +- gpd: gpio@3 { +- compatible = "ingenic,jz4780-gpio"; +- reg = <3>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 96 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <14>; +- }; +- +- gpe: gpio@4 { +- compatible = "ingenic,jz4780-gpio"; +- reg = <4>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 128 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <13>; +- }; +- +- gpf: gpio@5 { +- compatible = "ingenic,jz4780-gpio"; +- reg = <5>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 160 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <12>; +- }; +- }; +- +- spi_gpio { +- compatible = "spi-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- num-chipselects = <2>; +- +- gpio-miso = <&gpe 14 0>; +- gpio-sck = <&gpe 15 0>; +- gpio-mosi = <&gpe 17 0>; +- cs-gpios = <&gpe 16 0>, <&gpe 18 0>; +- +- spidev@0 { +- compatible = "spidev"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- uart0: serial@10030000 { +- compatible = "ingenic,jz4780-uart"; +- reg = <0x10030000 0x100>; +- +- interrupt-parent = <&intc>; +- interrupts = <51>; +- +- clocks = <&ext>, <&cgu JZ4780_CLK_UART0>; +- clock-names = "baud", "module"; +- +- status = "disabled"; +- }; +- +- uart1: serial@10031000 { +- compatible = "ingenic,jz4780-uart"; +- reg = <0x10031000 0x100>; +- +- interrupt-parent = <&intc>; +- interrupts = <50>; +- +- clocks = <&ext>, <&cgu JZ4780_CLK_UART1>; +- clock-names = "baud", "module"; +- +- status = "disabled"; +- }; +- +- uart2: serial@10032000 { +- compatible = "ingenic,jz4780-uart"; +- reg = <0x10032000 0x100>; +- +- interrupt-parent = <&intc>; +- interrupts = <49>; +- +- clocks = <&ext>, <&cgu JZ4780_CLK_UART2>; +- clock-names = "baud", "module"; +- +- status = "disabled"; +- }; +- +- uart3: serial@10033000 { +- compatible = "ingenic,jz4780-uart"; +- reg = <0x10033000 0x100>; +- +- interrupt-parent = <&intc>; +- interrupts = <48>; +- +- clocks = <&ext>, <&cgu JZ4780_CLK_UART3>; +- clock-names = "baud", "module"; +- +- status = "disabled"; +- }; +- +- uart4: serial@10034000 { +- compatible = "ingenic,jz4780-uart"; +- reg = <0x10034000 0x100>; +- +- interrupt-parent = <&intc>; +- interrupts = <34>; +- +- clocks = <&ext>, <&cgu JZ4780_CLK_UART4>; +- clock-names = "baud", "module"; +- +- status = "disabled"; +- }; +- +- i2c0: i2c@10050000 { +- compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- reg = <0x10050000 0x1000>; +- +- interrupt-parent = <&intc>; +- interrupts = <60>; +- +- clocks = <&cgu JZ4780_CLK_SMB0>; +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_i2c0_data>; +- +- status = "disabled"; +- }; +- +- i2c1: i2c@10051000 { +- compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x10051000 0x1000>; +- +- interrupt-parent = <&intc>; +- interrupts = <59>; +- +- clocks = <&cgu JZ4780_CLK_SMB1>; +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_i2c1_data>; +- +- status = "disabled"; +- }; +- +- i2c2: i2c@10052000 { +- compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x10052000 0x1000>; +- +- interrupt-parent = <&intc>; +- interrupts = <58>; +- +- clocks = <&cgu JZ4780_CLK_SMB2>; +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_i2c2_data>; +- +- status = "disabled"; +- }; +- +- i2c3: i2c@10053000 { +- compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x10053000 0x1000>; +- +- interrupt-parent = <&intc>; +- interrupts = <57>; +- +- clocks = <&cgu JZ4780_CLK_SMB3>; +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_i2c3_data>; +- +- status = "disabled"; +- }; +- +- i2c4: i2c@10054000 { +- compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x10054000 0x1000>; +- +- interrupt-parent = <&intc>; +- interrupts = <56>; +- +- clocks = <&cgu JZ4780_CLK_SMB4>; +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_i2c4_data>; +- +- status = "disabled"; +- }; +- +- nemc: nemc@13410000 { +- compatible = "ingenic,jz4780-nemc", "simple-mfd"; +- reg = <0x13410000 0x10000>; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0 0x13410000 0x10000>, +- <1 0 0x1b000000 0x1000000>, +- <2 0 0x1a000000 0x1000000>, +- <3 0 0x19000000 0x1000000>, +- <4 0 0x18000000 0x1000000>, +- <5 0 0x17000000 0x1000000>, +- <6 0 0x16000000 0x1000000>; +- +- clocks = <&cgu JZ4780_CLK_NEMC>; +- +- status = "disabled"; +- +- efuse: efuse@d0 { +- reg = <0 0xd0 0x30>; +- compatible = "ingenic,jz4780-efuse"; +- +- clocks = <&cgu JZ4780_CLK_AHB2>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- eth0_addr: eth-mac-addr@0x22 { +- reg = <0x22 0x6>; +- }; +- }; +- }; +- +- dma: dma@13420000 { +- compatible = "ingenic,jz4780-dma"; +- reg = <0x13420000 0x400>, <0x13421000 0x40>; +- #dma-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <10>; +- +- clocks = <&cgu JZ4780_CLK_PDMA>; +- }; +- +- mmc0: mmc@13450000 { +- compatible = "ingenic,jz4780-mmc"; +- reg = <0x13450000 0x1000>; +- +- interrupt-parent = <&intc>; +- interrupts = <37>; +- +- clocks = <&cgu JZ4780_CLK_MSC0>; +- clock-names = "mmc"; +- +- cap-sd-highspeed; +- cap-mmc-highspeed; +- cap-sdio-irq; +- dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>, +- <&dma JZ4780_DMA_MSC0_TX 0xffffffff>; +- dma-names = "rx", "tx"; +- +- status = "disabled"; +- }; +- +- mmc1: mmc@13460000 { +- compatible = "ingenic,jz4780-mmc"; +- reg = <0x13460000 0x1000>; +- +- interrupt-parent = <&intc>; +- interrupts = <36>; +- +- clocks = <&cgu JZ4780_CLK_MSC1>; +- clock-names = "mmc"; +- +- cap-sd-highspeed; +- cap-mmc-highspeed; +- cap-sdio-irq; +- dmas = <&dma JZ4780_DMA_MSC1_RX 0xffffffff>, +- <&dma JZ4780_DMA_MSC1_TX 0xffffffff>; +- dma-names = "rx", "tx"; +- +- status = "disabled"; +- }; +- +- bch: bch@134d0000 { +- compatible = "ingenic,jz4780-bch"; +- reg = <0x134d0000 0x10000>; +- +- clocks = <&cgu JZ4780_CLK_BCH>; +- +- status = "disabled"; +- }; +- +- otg: usb@13500000 { +- compatible = "ingenic,jz4780-otg", "snps,dwc2"; +- reg = <0x13500000 0x40000>; +- +- interrupt-parent = <&intc>; +- interrupts = <21>; +- +- clocks = <&cgu JZ4780_CLK_UHC>; +- clock-names = "otg"; +- +- phys = <&otg_phy>; +- phy-names = "usb2-phy"; +- +- g-rx-fifo-size = <768>; +- g-np-tx-fifo-size = <256>; +- g-tx-fifo-size = <256 256 256 256 256 256 256 512>; +- +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ingenic/qi_lb60.dts b/scripts/dtc/include-prefixes/mips/ingenic/qi_lb60.dts +deleted file mode 100644 +index ba0218971572..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ingenic/qi_lb60.dts ++++ /dev/null +@@ -1,363 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "jz4740.dtsi" +- +-#include +-#include +-#include +-#include +- +-#define KEY_QI_QI KEY_F13 +-#define KEY_QI_UPRED KEY_RIGHTALT +-#define KEY_QI_VOLUP KEY_VOLUMEUP +-#define KEY_QI_VOLDOWN KEY_VOLUMEDOWN +-#define KEY_QI_FN KEY_LEFTCTRL +- +-/ { +- compatible = "qi,lb60", "ingenic,jz4740"; +- model = "Ben Nanonote"; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x2000000>; +- }; +- +- chosen { +- stdout-path = &uart0; +- }; +- +- vcc: regulator@0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc"; +- +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- mmc_power: regulator@1 { +- compatible = "regulator-fixed"; +- regulator-name = "mmc_vcc"; +- gpio = <&gpd 2 0>; +- +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- amp_supply: regulator@2 { +- compatible = "regulator-fixed"; +- regulator-name = "amp_supply"; +- gpio = <&gpd 4 0>; +- enable-active-high; +- +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- +- amp: analog-amplifier { +- compatible = "simple-audio-amplifier"; +- enable-gpios = <&gpb 29 GPIO_ACTIVE_HIGH>; +- VCC-supply = <&_supply>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- +- simple-audio-card,name = "QI LB60"; +- simple-audio-card,format = "i2s"; +- +- simple-audio-card,widgets = +- "Speaker", "Speaker", +- "Microphone", "Mic"; +- simple-audio-card,routing = +- "MIC", "Mic", +- "Speaker", "OUTL", +- "Speaker", "OUTR", +- "INL", "LOUT", +- "INR", "ROUT"; +- +- simple-audio-card,aux-devs = <&>; +- +- simple-audio-card,bitclock-master = <&dai_codec>; +- simple-audio-card,frame-master = <&dai_codec>; +- +- dai_cpu: simple-audio-card,cpu { +- sound-dai = <&aic>; +- }; +- +- dai_codec: simple-audio-card,codec { +- sound-dai = <&codec>; +- }; +- }; +- +- keys { +- compatible = "gpio-keys"; +- +- key { +- label = "Power"; +- wakeup-source; +- linux,code = ; +- gpios = <&gpd 29 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- keyboard { +- compatible = "gpio-matrix-keypad"; +- +- col-scan-delay-us = <10>; +- debounce-delay-ms = <10>; +- wakeup-source; +- +- row-gpios = <&gpd 18 0>, <&gpd 19 0>, <&gpd 20 0>, <&gpd 21 0>, +- <&gpd 22 0>, <&gpd 23 0>, <&gpd 24 0>, <&gpd 26 0>; +- col-gpios = <&gpc 10 0>, <&gpc 11 0>, <&gpc 12 0>, <&gpc 13 0>, +- <&gpc 14 0>, <&gpc 15 0>, <&gpc 16 0>, <&gpc 17 0>; +- gpio-activelow; +- +- linux,keymap = +- , /* S2 */ +- , /* S3 */ +- , /* S4 */ +- , /* S5 */ +- , /* S6 */ +- , /* S7 */ +- , /* S8 */ +- +- , /* S10 */ +- , /* S11 */ +- , /* S12 */ +- , /* S13 */ +- , /* S14 */ +- , /* S15 */ +- , /* S16 */ +- , /* S17 */ +- , /* S18 */ +- , /* S19 */ +- , /* S20 */ +- , /* S21 */ +- , /* S22 */ +- , /* S23 */ +- , /* S24 */ +- , /* S25 */ +- , /* S26 */ +- , /* S27 */ +- , /* S28 */ +- , /* S29 */ +- , /* S30 */ +- , /* S31 */ +- , /* S32 */ +- , /* S33 */ +- , /* S34 */ +- , /* S35 */ +- , /* S36 */ +- , /* S37 */ +- , /* S38 */ +- , /* S39 */ +- , /* S40 */ +- , /* S41 */ +- , /* S42 */ +- , /* S43 */ +- , /* S44 */ +- , /* S45 */ +- , /* S46 */ +- , /* S47 */ +- , /* S48 */ +- , /* S49 */ +- , /* S50 */ +- , /* S51 */ +- ,/* S52 */ +- , /* S53 */ +- , /* S54 */ +- , /* S55 */ +- , /* S56 */ +- , /* S57 */ +- +- , /* S58 */ +- , /* S59 */ +- ; /* S60 */ +- }; +- +- spi { +- compatible = "spi-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- sck-gpios = <&gpc 23 GPIO_ACTIVE_HIGH>; +- mosi-gpios = <&gpc 22 GPIO_ACTIVE_HIGH>; +- cs-gpios = <&gpc 21 GPIO_ACTIVE_LOW>; +- num-chipselects = <1>; +- }; +- +- usb_charger: charger { +- compatible = "gpio-charger"; +- charger-type = "usb-sdp"; +- gpios = <&gpd 28 GPIO_ACTIVE_LOW>; +- status-gpios = <&gpc 27 GPIO_ACTIVE_LOW>; +- }; +- +- simple_battery: battery { +- compatible = "simple-battery"; +- voltage-min-design-microvolt = <3600000>; +- voltage-max-design-microvolt = <4200000>; +- }; +- +- pmu { +- compatible = "ingenic,jz4740-battery"; +- io-channels = <&adc INGENIC_ADC_BATTERY>; +- io-channel-names = "battery"; +- power-supplies = <&usb_charger>; +- monitored-battery = <&simple_battery>; +- }; +- +- hwmon { +- compatible = "iio-hwmon"; +- io-channels = <&adc INGENIC_ADC_AUX>; +- }; +- +- panel: panel { +- compatible = "giantplus,gpm940b0"; +- +- power-supply = <&vcc>; +- +- port { +- panel_input: endpoint { +- remote-endpoint = <&panel_output>; +- }; +- }; +- }; +- +- usb_phy: usb-phy { +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- +- vcc-supply = <&vcc>; +- }; +-}; +- +-&ext { +- clock-frequency = <12000000>; +-}; +- +-&rtc_dev { +- system-power-controller; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_uart0>; +-}; +- +-&uart1 { +- status = "disabled"; +-}; +- +-&nemc { +- nandc: nand-controller@1 { +- compatible = "ingenic,jz4740-nand"; +- reg = <1 0 0x4000000>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- ecc-engine = <&ecc>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_nemc>; +- +- rb-gpios = <&gpc 30 GPIO_ACTIVE_HIGH>; +- +- nand@1 { +- reg = <1>; +- +- nand-ecc-step-size = <512>; +- nand-ecc-strength = <4>; +- nand-ecc-mode = "hw"; +- nand-is-boot-medium; +- nand-on-flash-bbt; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "boot"; +- reg = <0x0 0x400000>; +- }; +- +- partition@400000 { +- label = "kernel"; +- reg = <0x400000 0x400000>; +- }; +- +- partition@800000 { +- label = "rootfs"; +- reg = <0x800000 0x0>; +- }; +- }; +- }; +- }; +-}; +- +-&lcd { +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_lcd>; +- +- port { +- panel_output: endpoint { +- remote-endpoint = <&panel_input>; +- }; +- }; +-}; +- +-&udc { +- phys = <&usb_phy>; +-}; +- +-&pinctrl { +- pins_lcd: lcd { +- function = "lcd"; +- groups = "lcd-8bit"; +- }; +- +- pins_nemc: nemc { +- function = "nand"; +- groups = "nand-fre-fwe", "nand-cs1"; +- }; +- +- pins_uart0: uart0 { +- function = "uart0"; +- groups = "uart0-data"; +- bias-disable; +- }; +- +- pins_mmc: mmc { +- mmc { +- function = "mmc"; +- groups = "mmc-1bit", "mmc-4bit"; +- bias-disable; +- }; +- +- mmc-gpios { +- pins = "PD0", "PD2"; +- bias-disable; +- }; +- }; +-}; +- +-&mmc { +- bus-width = <4>; +- max-frequency = <24000000>; +- cd-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>; +- vmmc-supply = <&mmc_power>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_mmc>; +-}; +- +-&tcu { +- /* 750 kHz for the system timer and clocksource */ +- assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>; +- assigned-clock-rates = <750000>, <750000>; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ingenic/rs90.dts b/scripts/dtc/include-prefixes/mips/ingenic/rs90.dts +deleted file mode 100644 +index 74fee7f01352..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ingenic/rs90.dts ++++ /dev/null +@@ -1,329 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "jz4725b.dtsi" +- +-#include +-#include +-#include +- +-/ { +- compatible = "ylm,rs90", "ingenic,jz4725b"; +- model = "RS-90"; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x2000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- vmem: video-memory@1f00000 { +- compatible = "shared-dma-pool"; +- reg = <0x1f00000 0x100000>; +- reusable; +- }; +- }; +- +- vcc: regulator { +- compatible = "regulator-fixed"; +- +- regulator-name = "vcc"; +- regulaor-min-microvolt = <3300000>; +- regulaor-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- backlight: backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm 3 40000 0>; +- +- brightness-levels = <0 16 32 48 64 80 112 144 192 255>; +- default-brightness-level = <8>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_pwm3>; +- +- power-supply = <&vcc>; +- }; +- +- keys@0 { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- key@0 { +- label = "D-pad up"; +- linux,code = ; +- gpios = <&gpc 10 GPIO_ACTIVE_LOW>; +- }; +- +- key@1 { +- label = "D-pad down"; +- linux,code = ; +- gpios = <&gpc 11 GPIO_ACTIVE_LOW>; +- }; +- +- key@2 { +- label = "D-pad left"; +- linux,code = ; +- gpios = <&gpb 31 GPIO_ACTIVE_LOW>; +- }; +- +- key@3 { +- label = "D-pad right"; +- linux,code = ; +- gpios = <&gpd 21 GPIO_ACTIVE_LOW>; +- }; +- +- key@4 { +- label = "Button A"; +- linux,code = ; +- gpios = <&gpc 31 GPIO_ACTIVE_LOW>; +- }; +- +- key@5 { +- label = "Button B"; +- linux,code = ; +- gpios = <&gpc 30 GPIO_ACTIVE_LOW>; +- }; +- +- key@6 { +- label = "Right shoulder button"; +- linux,code = ; +- gpios = <&gpc 12 GPIO_ACTIVE_LOW>; +- debounce-interval = <10>; +- }; +- +- key@7 { +- label = "Start button"; +- linux,code = ; +- gpios = <&gpd 17 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- keys@1 { +- compatible = "adc-keys"; +- io-channels = <&adc INGENIC_ADC_AUX>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1400000>; +- poll-interval = <30>; +- +- key@0 { +- label = "Left shoulder button"; +- linux,code = ; +- press-threshold-microvolt = <800000>; +- }; +- +- key@1 { +- label = "Select button"; +- linux,code = ; +- press-threshold-microvolt = <1100000>; +- }; +- }; +- +- amp: analog-amplifier { +- compatible = "simple-audio-amplifier"; +- enable-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>; +- +- VCC-supply = <&vcc>; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- +- simple-audio-card,name = "rs90-audio"; +- simple-audio-card,format = "i2s"; +- +- simple-audio-card,widgets = +- "Speaker", "Speaker", +- "Headphone", "Headphones"; +- simple-audio-card,routing = +- "INL", "LHPOUT", +- "INR", "RHPOUT", +- "Headphones", "LHPOUT", +- "Headphones", "RHPOUT", +- "Speaker", "OUTL", +- "Speaker", "OUTR"; +- simple-audio-card,pin-switches = "Speaker"; +- +- simple-audio-card,hp-det-gpio = <&gpd 16 GPIO_ACTIVE_LOW>; +- simple-audio-card,aux-devs = <&>; +- +- simple-audio-card,bitclock-master = <&dai_codec>; +- simple-audio-card,frame-master = <&dai_codec>; +- +- dai_cpu: simple-audio-card,cpu { +- sound-dai = <&aic>; +- }; +- +- dai_codec: simple-audio-card,codec { +- sound-dai = <&codec>; +- }; +- +- }; +- +- usb_phy: usb-phy { +- compatible = "usb-nop-xceiv"; +- #phy-cells = <0>; +- +- clocks = <&cgu JZ4725B_CLK_UDC_PHY>; +- clock-names = "main_clk"; +- vcc-supply = <&vcc>; +- }; +- +- panel { +- compatible = "sharp,ls020b1dd01d"; +- +- backlight = <&backlight>; +- power-supply = <&vcc>; +- +- port { +- panel_input: endpoint { +- remote-endpoint = <&panel_output>; +- }; +- }; +- }; +-}; +- +-&ext { +- clock-frequency = <12000000>; +-}; +- +-&rtc_dev { +- system-power-controller; +-}; +- +-&udc { +- phys = <&usb_phy>; +-}; +- +-&pinctrl { +- pins_mmc1: mmc1 { +- function = "mmc1"; +- groups = "mmc1-1bit"; +- }; +- +- pins_nemc: nemc { +- function = "nand"; +- groups = "nand-cs1", "nand-cle-ale", "nand-fre-fwe"; +- }; +- +- pins_pwm3: pwm3 { +- function = "pwm3"; +- groups = "pwm3"; +- bias-disable; +- }; +- +- pins_lcd: lcd { +- function = "lcd"; +- groups = "lcd-8bit", "lcd-16bit", "lcd-special"; +- }; +-}; +- +-&mmc0 { +- status = "disabled"; +-}; +- +-&mmc1 { +- bus-width = <1>; +- max-frequency = <48000000>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_mmc1>; +- +- cd-gpios = <&gpc 20 GPIO_ACTIVE_LOW>; +-}; +- +-&uart { +- /* +- * The pins for RX/TX are used for the right shoulder button and +- * backlight PWM. +- */ +- status = "disabled"; +-}; +- +-&nemc { +- nandc: nand-controller@1 { +- compatible = "ingenic,jz4725b-nand"; +- reg = <1 0 0x4000000>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- ecc-engine = <&bch>; +- +- ingenic,nemc-tAS = <10>; +- ingenic,nemc-tAH = <5>; +- ingenic,nemc-tBP = <10>; +- ingenic,nemc-tAW = <15>; +- ingenic,nemc-tSTRV = <100>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_nemc>; +- +- rb-gpios = <&gpc 27 GPIO_ACTIVE_HIGH>; +- +- nand@1 { +- reg = <1>; +- +- nand-ecc-step-size = <512>; +- nand-ecc-strength = <8>; +- nand-ecc-mode = "hw"; +- nand-is-boot-medium; +- nand-on-flash-bbt; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "bootloader"; +- reg = <0x0 0x20000>; +- }; +- +- partition@20000 { +- label = "system"; +- reg = <0x20000 0x0>; +- }; +- }; +- }; +- }; +-}; +- +-&cgu { +- /* Use 32kHz oscillator as the parent of the RTC clock */ +- assigned-clocks = <&cgu JZ4725B_CLK_RTC>; +- assigned-clock-parents = <&cgu JZ4725B_CLK_OSC32K>; +-}; +- +-&tcu { +- /* +- * 750 kHz for the system timer and clocksource, and use RTC as the +- * parent for the watchdog clock. +- */ +- assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, <&tcu TCU_CLK_WDT>; +- assigned-clock-parents = <0>, <0>, <&cgu JZ4725B_CLK_RTC>; +- assigned-clock-rates = <750000>, <750000>; +-}; +- +-&lcd { +- memory-region = <&vmem>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pins_lcd>; +-}; +- +-&lcd_ports { +- port@0 { +- reg = <0>; +- +- panel_output: endpoint { +- remote-endpoint = <&panel_input>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ingenic/x1000.dtsi b/scripts/dtc/include-prefixes/mips/ingenic/x1000.dtsi +deleted file mode 100644 +index dec7909d4baa..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ingenic/x1000.dtsi ++++ /dev/null +@@ -1,387 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ingenic,x1000", "ingenic,x1000e"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "ingenic,xburst-fpu1.0-mxu1.1"; +- reg = <0>; +- +- clocks = <&cgu X1000_CLK_CPU>; +- clock-names = "cpu"; +- }; +- }; +- +- cpuintc: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- intc: interrupt-controller@10001000 { +- compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc"; +- reg = <0x10001000 0x50>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <2>; +- }; +- +- exclk: ext { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- }; +- +- rtclk: rtc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- cgu: x1000-cgu@10000000 { +- compatible = "ingenic,x1000-cgu", "simple-mfd"; +- reg = <0x10000000 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10000000 0x100>; +- +- #clock-cells = <1>; +- +- clocks = <&exclk>, <&rtclk>; +- clock-names = "ext", "rtc"; +- +- otg_phy: usb-phy@3c { +- compatible = "ingenic,x1000-phy"; +- reg = <0x3c 0x10>; +- +- clocks = <&cgu X1000_CLK_OTGPHY>; +- +- #phy-cells = <0>; +- +- status = "disabled"; +- }; +- +- rng: rng@d8 { +- compatible = "ingenic,x1000-rng"; +- reg = <0xd8 0x8>; +- +- status = "disabled"; +- }; +- +- mac_phy_ctrl: mac-phy-ctrl@e8 { +- compatible = "syscon"; +- reg = <0xe8 0x4>; +- }; +- }; +- +- ost: timer@12000000 { +- compatible = "ingenic,x1000-ost"; +- reg = <0x12000000 0x3c>; +- +- #clock-cells = <1>; +- +- clocks = <&cgu X1000_CLK_OST>; +- clock-names = "ost"; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <3>; +- }; +- +- tcu: timer@10002000 { +- compatible = "ingenic,x1000-tcu", "simple-mfd"; +- reg = <0x10002000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10002000 0x1000>; +- +- #clock-cells = <1>; +- +- clocks = <&cgu X1000_CLK_RTCLK>, +- <&cgu X1000_CLK_EXCLK>, +- <&cgu X1000_CLK_PCLK>; +- clock-names = "rtc", "ext", "pclk"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&intc>; +- interrupts = <27 26 25>; +- +- wdt: watchdog@0 { +- compatible = "ingenic,x1000-watchdog", "ingenic,jz4780-watchdog"; +- reg = <0x0 0x10>; +- +- clocks = <&tcu TCU_CLK_WDT>; +- clock-names = "wdt"; +- }; +- }; +- +- rtc: rtc@10003000 { +- compatible = "ingenic,x1000-rtc", "ingenic,jz4780-rtc"; +- reg = <0x10003000 0x4c>; +- +- interrupt-parent = <&intc>; +- interrupts = <32>; +- +- clocks = <&cgu X1000_CLK_RTCLK>; +- clock-names = "rtc"; +- }; +- +- pinctrl: pin-controller@10010000 { +- compatible = "ingenic,x1000-pinctrl"; +- reg = <0x10010000 0x800>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpa: gpio@0 { +- compatible = "ingenic,x1000-gpio"; +- reg = <0>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 0 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <17>; +- }; +- +- gpb: gpio@1 { +- compatible = "ingenic,x1000-gpio"; +- reg = <1>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 32 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <16>; +- }; +- +- gpc: gpio@2 { +- compatible = "ingenic,x1000-gpio"; +- reg = <2>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 64 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <15>; +- }; +- +- gpd: gpio@3 { +- compatible = "ingenic,x1000-gpio"; +- reg = <3>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 96 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <14>; +- }; +- }; +- +- uart0: serial@10030000 { +- compatible = "ingenic,x1000-uart"; +- reg = <0x10030000 0x100>; +- +- interrupt-parent = <&intc>; +- interrupts = <51>; +- +- clocks = <&exclk>, <&cgu X1000_CLK_UART0>; +- clock-names = "baud", "module"; +- +- status = "disabled"; +- }; +- +- uart1: serial@10031000 { +- compatible = "ingenic,x1000-uart"; +- reg = <0x10031000 0x100>; +- +- interrupt-parent = <&intc>; +- interrupts = <50>; +- +- clocks = <&exclk>, <&cgu X1000_CLK_UART1>; +- clock-names = "baud", "module"; +- +- status = "disabled"; +- }; +- +- uart2: serial@10032000 { +- compatible = "ingenic,x1000-uart"; +- reg = <0x10032000 0x100>; +- +- interrupt-parent = <&intc>; +- interrupts = <49>; +- +- clocks = <&exclk>, <&cgu X1000_CLK_UART2>; +- clock-names = "baud", "module"; +- +- status = "disabled"; +- }; +- +- i2c0: i2c-controller@10050000 { +- compatible = "ingenic,x1000-i2c"; +- reg = <0x10050000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- interrupt-parent = <&intc>; +- interrupts = <60>; +- +- clocks = <&cgu X1000_CLK_I2C0>; +- +- status = "disabled"; +- }; +- +- i2c1: i2c-controller@10051000 { +- compatible = "ingenic,x1000-i2c"; +- reg = <0x10051000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- interrupt-parent = <&intc>; +- interrupts = <59>; +- +- clocks = <&cgu X1000_CLK_I2C1>; +- +- status = "disabled"; +- }; +- +- i2c2: i2c-controller@10052000 { +- compatible = "ingenic,x1000-i2c"; +- reg = <0x10052000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- interrupt-parent = <&intc>; +- interrupts = <58>; +- +- clocks = <&cgu X1000_CLK_I2C2>; +- +- status = "disabled"; +- }; +- +- pdma: dma-controller@13420000 { +- compatible = "ingenic,x1000-dma"; +- reg = <0x13420000 0x400>, <0x13421000 0x40>; +- #dma-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <10>; +- +- clocks = <&cgu X1000_CLK_PDMA>; +- }; +- +- msc0: mmc@13450000 { +- compatible = "ingenic,x1000-mmc"; +- reg = <0x13450000 0x1000>; +- +- interrupt-parent = <&intc>; +- interrupts = <37>; +- +- clocks = <&cgu X1000_CLK_MSC0>; +- clock-names = "mmc"; +- +- cap-sd-highspeed; +- cap-mmc-highspeed; +- cap-sdio-irq; +- +- dmas = <&pdma X1000_DMA_MSC0_RX 0xffffffff>, +- <&pdma X1000_DMA_MSC0_TX 0xffffffff>; +- dma-names = "rx", "tx"; +- +- status = "disabled"; +- }; +- +- msc1: mmc@13460000 { +- compatible = "ingenic,x1000-mmc"; +- reg = <0x13460000 0x1000>; +- +- interrupt-parent = <&intc>; +- interrupts = <36>; +- +- clocks = <&cgu X1000_CLK_MSC1>; +- clock-names = "mmc"; +- +- cap-sd-highspeed; +- cap-mmc-highspeed; +- cap-sdio-irq; +- +- dmas = <&pdma X1000_DMA_MSC1_RX 0xffffffff>, +- <&pdma X1000_DMA_MSC1_TX 0xffffffff>; +- dma-names = "rx", "tx"; +- +- status = "disabled"; +- }; +- +- mac: ethernet@134b0000 { +- compatible = "ingenic,x1000-mac", "snps,dwmac"; +- reg = <0x134b0000 0x2000>; +- +- interrupt-parent = <&intc>; +- interrupts = <55>; +- interrupt-names = "macirq"; +- +- clocks = <&cgu X1000_CLK_MAC>; +- clock-names = "stmmaceth"; +- +- mode-reg = <&mac_phy_ctrl>; +- +- status = "disabled"; +- +- mdio: mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- }; +- +- otg: usb@13500000 { +- compatible = "ingenic,x1000-otg", "snps,dwc2"; +- reg = <0x13500000 0x40000>; +- +- interrupt-parent = <&intc>; +- interrupts = <21>; +- +- clocks = <&cgu X1000_CLK_OTG>; +- clock-names = "otg"; +- +- phys = <&otg_phy>; +- phy-names = "usb2-phy"; +- +- g-rx-fifo-size = <768>; +- g-np-tx-fifo-size = <256>; +- g-tx-fifo-size = <256 256 256 256 256 256 256 512>; +- +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ingenic/x1830.dtsi b/scripts/dtc/include-prefixes/mips/ingenic/x1830.dtsi +deleted file mode 100644 +index 215257f8bb1a..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ingenic/x1830.dtsi ++++ /dev/null +@@ -1,376 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ingenic,x1830"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "ingenic,xburst-fpu2.0-mxu2.0"; +- reg = <0>; +- +- clocks = <&cgu X1830_CLK_CPU>; +- clock-names = "cpu"; +- }; +- }; +- +- cpuintc: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- intc: interrupt-controller@10001000 { +- compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc"; +- reg = <0x10001000 0x50>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <2>; +- }; +- +- exclk: ext { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- }; +- +- rtclk: rtc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; +- +- cgu: x1830-cgu@10000000 { +- compatible = "ingenic,x1830-cgu", "simple-mfd"; +- reg = <0x10000000 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10000000 0x100>; +- +- #clock-cells = <1>; +- +- clocks = <&exclk>, <&rtclk>; +- clock-names = "ext", "rtc"; +- +- otg_phy: usb-phy@3c { +- compatible = "ingenic,x1830-phy"; +- reg = <0x3c 0x10>; +- +- clocks = <&cgu X1830_CLK_OTGPHY>; +- +- #phy-cells = <0>; +- +- status = "disabled"; +- }; +- +- mac_phy_ctrl: mac-phy-ctrl@e8 { +- compatible = "syscon"; +- reg = <0xe8 0x4>; +- }; +- }; +- +- ost: timer@12000000 { +- compatible = "ingenic,x1830-ost", "ingenic,x1000-ost"; +- reg = <0x12000000 0x3c>; +- +- #clock-cells = <1>; +- +- clocks = <&cgu X1830_CLK_OST>; +- clock-names = "ost"; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <4>; +- }; +- +- tcu: timer@10002000 { +- compatible = "ingenic,x1830-tcu", "ingenic,x1000-tcu", "simple-mfd"; +- reg = <0x10002000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x10002000 0x1000>; +- +- #clock-cells = <1>; +- +- clocks = <&cgu X1830_CLK_RTCLK>, +- <&cgu X1830_CLK_EXCLK>, +- <&cgu X1830_CLK_PCLK>; +- clock-names = "rtc", "ext", "pclk"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&intc>; +- interrupts = <27 26 25>; +- +- wdt: watchdog@0 { +- compatible = "ingenic,x1830-watchdog", "ingenic,jz4780-watchdog"; +- reg = <0x0 0x10>; +- +- clocks = <&tcu TCU_CLK_WDT>; +- clock-names = "wdt"; +- }; +- }; +- +- rtc: rtc@10003000 { +- compatible = "ingenic,x1830-rtc", "ingenic,jz4780-rtc"; +- reg = <0x10003000 0x4c>; +- +- interrupt-parent = <&intc>; +- interrupts = <32>; +- +- clocks = <&cgu X1830_CLK_RTCLK>; +- clock-names = "rtc"; +- }; +- +- pinctrl: pin-controller@10010000 { +- compatible = "ingenic,x1830-pinctrl"; +- reg = <0x10010000 0x800>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- gpa: gpio@0 { +- compatible = "ingenic,x1830-gpio"; +- reg = <0>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 0 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <17>; +- }; +- +- gpb: gpio@1 { +- compatible = "ingenic,x1830-gpio"; +- reg = <1>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 32 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <16>; +- }; +- +- gpc: gpio@2 { +- compatible = "ingenic,x1830-gpio"; +- reg = <2>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 64 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <15>; +- }; +- +- gpd: gpio@3 { +- compatible = "ingenic,x1830-gpio"; +- reg = <3>; +- +- gpio-controller; +- gpio-ranges = <&pinctrl 0 96 32>; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <14>; +- }; +- }; +- +- uart0: serial@10030000 { +- compatible = "ingenic,x1830-uart", "ingenic,x1000-uart"; +- reg = <0x10030000 0x100>; +- +- interrupt-parent = <&intc>; +- interrupts = <51>; +- +- clocks = <&exclk>, <&cgu X1830_CLK_UART0>; +- clock-names = "baud", "module"; +- +- status = "disabled"; +- }; +- +- uart1: serial@10031000 { +- compatible = "ingenic,x1830-uart", "ingenic,x1000-uart"; +- reg = <0x10031000 0x100>; +- +- interrupt-parent = <&intc>; +- interrupts = <50>; +- +- clocks = <&exclk>, <&cgu X1830_CLK_UART1>; +- clock-names = "baud", "module"; +- +- status = "disabled"; +- }; +- +- i2c0: i2c-controller@10050000 { +- compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c"; +- reg = <0x10050000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- interrupt-parent = <&intc>; +- interrupts = <60>; +- +- clocks = <&cgu X1830_CLK_SMB0>; +- +- status = "disabled"; +- }; +- +- i2c1: i2c-controller@10051000 { +- compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c"; +- reg = <0x10051000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- interrupt-parent = <&intc>; +- interrupts = <59>; +- +- clocks = <&cgu X1830_CLK_SMB1>; +- +- status = "disabled"; +- }; +- +- i2c2: i2c-controller@10052000 { +- compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c"; +- reg = <0x10052000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- interrupt-parent = <&intc>; +- interrupts = <58>; +- +- clocks = <&cgu X1830_CLK_SMB2>; +- +- status = "disabled"; +- }; +- +- dtrng: trng@10072000 { +- compatible = "ingenic,x1830-dtrng"; +- reg = <0x10072000 0xc>; +- +- clocks = <&cgu X1830_CLK_DTRNG>; +- +- status = "disabled"; +- }; +- +- pdma: dma-controller@13420000 { +- compatible = "ingenic,x1830-dma"; +- reg = <0x13420000 0x400>, <0x13421000 0x40>; +- #dma-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <10>; +- +- clocks = <&cgu X1830_CLK_PDMA>; +- }; +- +- msc0: mmc@13450000 { +- compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc"; +- reg = <0x13450000 0x1000>; +- +- interrupt-parent = <&intc>; +- interrupts = <37>; +- +- clocks = <&cgu X1830_CLK_MSC0>; +- clock-names = "mmc"; +- +- cap-sd-highspeed; +- cap-mmc-highspeed; +- cap-sdio-irq; +- +- dmas = <&pdma X1830_DMA_MSC0_RX 0xffffffff>, +- <&pdma X1830_DMA_MSC0_TX 0xffffffff>; +- dma-names = "rx", "tx"; +- +- status = "disabled"; +- }; +- +- msc1: mmc@13460000 { +- compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc"; +- reg = <0x13460000 0x1000>; +- +- interrupt-parent = <&intc>; +- interrupts = <36>; +- +- clocks = <&cgu X1830_CLK_MSC1>; +- clock-names = "mmc"; +- +- cap-sd-highspeed; +- cap-mmc-highspeed; +- cap-sdio-irq; +- +- dmas = <&pdma X1830_DMA_MSC1_RX 0xffffffff>, +- <&pdma X1830_DMA_MSC1_TX 0xffffffff>; +- dma-names = "rx", "tx"; +- +- status = "disabled"; +- }; +- +- mac: ethernet@134b0000 { +- compatible = "ingenic,x1830-mac", "snps,dwmac"; +- reg = <0x134b0000 0x2000>; +- +- interrupt-parent = <&intc>; +- interrupts = <55>; +- interrupt-names = "macirq"; +- +- clocks = <&cgu X1830_CLK_MAC>; +- clock-names = "stmmaceth"; +- +- mode-reg = <&mac_phy_ctrl>; +- +- status = "disabled"; +- +- mdio: mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- }; +- +- otg: usb@13500000 { +- compatible = "ingenic,x1830-otg", "snps,dwc2"; +- reg = <0x13500000 0x40000>; +- +- interrupt-parent = <&intc>; +- interrupts = <21>; +- +- clocks = <&cgu X1830_CLK_OTG>; +- clock-names = "otg"; +- +- phys = <&otg_phy>; +- phy-names = "usb2-phy"; +- +- g-rx-fifo-size = <768>; +- g-np-tx-fifo-size = <256>; +- g-tx-fifo-size = <256 256 256 256 256 256 256 512>; +- +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/lantiq/Makefile b/scripts/dtc/include-prefixes/mips/lantiq/Makefile +deleted file mode 100644 +index f5dfc06242b9..000000000000 +--- a/scripts/dtc/include-prefixes/mips/lantiq/Makefile ++++ /dev/null +@@ -1,4 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_DT_EASY50712) += easy50712.dtb +- +-obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) +diff --git a/scripts/dtc/include-prefixes/mips/lantiq/danube.dtsi b/scripts/dtc/include-prefixes/mips/lantiq/danube.dtsi +deleted file mode 100644 +index 510be63c8bdf..000000000000 +--- a/scripts/dtc/include-prefixes/mips/lantiq/danube.dtsi ++++ /dev/null +@@ -1,106 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "lantiq,xway", "lantiq,danube"; +- +- cpus { +- cpu@0 { +- compatible = "mips,mips24Kc"; +- }; +- }; +- +- biu@1f800000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "lantiq,biu", "simple-bus"; +- reg = <0x1f800000 0x800000>; +- ranges = <0x0 0x1f800000 0x7fffff>; +- +- icu0: icu@80200 { +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "lantiq,icu"; +- reg = <0x80200 0x120>; +- }; +- +- watchdog@803f0 { +- compatible = "lantiq,wdt"; +- reg = <0x803f0 0x10>; +- }; +- }; +- +- sram@1f000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "lantiq,sram"; +- reg = <0x1f000000 0x800000>; +- ranges = <0x0 0x1f000000 0x7fffff>; +- +- eiu0: eiu@101000 { +- #interrupt-cells = <1>; +- interrupt-controller; +- interrupt-parent; +- compatible = "lantiq,eiu-xway"; +- reg = <0x101000 0x1000>; +- }; +- +- pmu0: pmu@102000 { +- compatible = "lantiq,pmu-xway"; +- reg = <0x102000 0x1000>; +- }; +- +- cgu0: cgu@103000 { +- compatible = "lantiq,cgu-xway"; +- reg = <0x103000 0x1000>; +- #clock-cells = <1>; +- }; +- +- rcu0: rcu@203000 { +- compatible = "lantiq,rcu-xway"; +- reg = <0x203000 0x1000>; +- }; +- }; +- +- fpi@10000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "lantiq,fpi", "simple-bus"; +- ranges = <0x0 0x10000000 0xeefffff>; +- reg = <0x10000000 0xef00000>; +- +- gptu@e100a00 { +- compatible = "lantiq,gptu-xway"; +- reg = <0xe100a00 0x100>; +- }; +- +- serial@e100c00 { +- compatible = "lantiq,asc"; +- reg = <0xe100c00 0x400>; +- interrupt-parent = <&icu0>; +- interrupts = <112 113 114>; +- }; +- +- dma0: dma@e104100 { +- compatible = "lantiq,dma-xway"; +- reg = <0xe104100 0x800>; +- }; +- +- ebu0: ebu@e105300 { +- compatible = "lantiq,ebu-xway"; +- reg = <0xe105300 0x100>; +- }; +- +- pci0: pci@e105400 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- compatible = "lantiq,pci-xway"; +- bus-range = <0x0 0x0>; +- ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ +- 0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */ +- reg = <0x7000000 0x8000 /* config space */ +- 0xe105400 0x400>; /* pci bridge */ +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/lantiq/easy50712.dts b/scripts/dtc/include-prefixes/mips/lantiq/easy50712.dts +deleted file mode 100644 +index 1ce20b7d05cb..000000000000 +--- a/scripts/dtc/include-prefixes/mips/lantiq/easy50712.dts ++++ /dev/null +@@ -1,115 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-/include/ "danube.dtsi" +- +-/ { +- chosen { +- bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x2000000>; +- }; +- +- fpi@10000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- localbus@0 { +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ +- 1 0 0x4000000 0x4000010>; /* addsel1 */ +- compatible = "lantiq,localbus", "simple-bus"; +- +- nor-boot@0 { +- compatible = "lantiq,nor"; +- bank-width = <2>; +- reg = <0 0x0 0x2000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "uboot"; +- reg = <0x00000 0x10000>; /* 64 KB */ +- }; +- +- partition@10000 { +- label = "uboot_env"; +- reg = <0x10000 0x10000>; /* 64 KB */ +- }; +- +- partition@20000 { +- label = "linux"; +- reg = <0x20000 0x3d0000>; +- }; +- +- partition@400000 { +- label = "rootfs"; +- reg = <0x400000 0x400000>; +- }; +- }; +- }; +- +- gpio: pinmux@e100b10 { +- compatible = "lantiq,danube-pinctrl"; +- pinctrl-names = "default"; +- pinctrl-0 = <&state_default>; +- +- #gpio-cells = <2>; +- gpio-controller; +- reg = <0xe100b10 0xa0>; +- +- state_default: pinmux { +- stp { +- lantiq,groups = "stp"; +- lantiq,function = "stp"; +- }; +- exin { +- lantiq,groups = "exin1"; +- lantiq,function = "exin"; +- }; +- pci { +- lantiq,groups = "gnt1"; +- lantiq,function = "pci"; +- }; +- conf_out { +- lantiq,pins = "io4", "io5", "io6"; /* stp */ +- lantiq,open-drain; +- lantiq,pull = <0>; +- }; +- }; +- }; +- +- etop@e180000 { +- compatible = "lantiq,etop-xway"; +- reg = <0xe180000 0x40000>; +- interrupt-parent = <&icu0>; +- interrupts = <73 78>; +- phy-mode = "rmii"; +- mac-address = [ 00 11 22 33 44 55 ]; +- }; +- +- stp0: stp@e100bb0 { +- #gpio-cells = <2>; +- compatible = "lantiq,gpio-stp-xway"; +- gpio-controller; +- reg = <0xe100bb0 0x40>; +- +- lantiq,shadow = <0xfff>; +- lantiq,groups = <0x3>; +- }; +- +- pci@e105400 { +- lantiq,bus-clock = <33333333>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- 0x7000 0 0 1 &icu0 29 1 // slot 14, irq 29 +- >; +- gpios-reset = <&gpio 21 0>; +- req-mask = <0x1>; /* GNT1 */ +- }; +- +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/loongson/Makefile b/scripts/dtc/include-prefixes/mips/loongson/Makefile +deleted file mode 100644 +index 5c6433e441ee..000000000000 +--- a/scripts/dtc/include-prefixes/mips/loongson/Makefile ++++ /dev/null +@@ -1,9 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_MACH_LOONGSON64) += loongson64_2core_2k1000.dtb +-dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_ls7a.dtb +-dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_rs780e.dtb +-dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_8core_rs780e.dtb +-dtb-$(CONFIG_MACH_LOONGSON64) += loongson64g_4core_ls7a.dtb +-dtb-$(CONFIG_MACH_LOONGSON64) += loongson64v_4core_virtio.dtb +- +-obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) +diff --git a/scripts/dtc/include-prefixes/mips/loongson/loongson64-2k1000.dtsi b/scripts/dtc/include-prefixes/mips/loongson/loongson64-2k1000.dtsi +deleted file mode 100644 +index bfc3d3243ee7..000000000000 +--- a/scripts/dtc/include-prefixes/mips/loongson/loongson64-2k1000.dtsi ++++ /dev/null +@@ -1,289 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/dts-v1/; +- +-#include +- +-/ { +- compatible = "loongson,loongson2k1000"; +- +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "loongson,gs264"; +- reg = <0x0>; +- #clock-cells = <1>; +- clocks = <&cpu_clk>; +- }; +- }; +- +- memory@200000 { +- compatible = "memory"; +- device_type = "memory"; +- reg = <0x00000000 0x00200000 0x00000000 0x0ee00000>, /* 238 MB at 2 MB */ +- <0x00000000 0x20000000 0x00000000 0x1f000000>, /* 496 MB at 512 MB */ +- <0x00000001 0x10000000 0x00000001 0xb0000000>; /* 6912 MB at 4352MB */ +- }; +- +- cpu_clk: cpu_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <800000000>; +- }; +- +- cpuintc: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- package0: bus@10000000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* ioports */ +- 0 0x40000000 0 0x40000000 0 0x40000000 +- 0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>; +- +- liointc0: interrupt-controller@1fe11400 { +- compatible = "loongson,liointc-2.0"; +- reg = <0 0x1fe11400 0 0x40>, +- <0 0x1fe11040 0 0x8>, +- <0 0x1fe11140 0 0x8>; +- reg-names = "main", "isr0", "isr1"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <2>; +- interrupt-names = "int0"; +- +- loongson,parent_int_map = <0xffffffff>, /* int0 */ +- <0x00000000>, /* int1 */ +- <0x00000000>, /* int2 */ +- <0x00000000>; /* int3 */ +- }; +- +- liointc1: interrupt-controller@1fe11440 { +- compatible = "loongson,liointc-2.0"; +- reg = <0 0x1fe11440 0 0x40>, +- <0 0x1fe11048 0 0x8>, +- <0 0x1fe11148 0 0x8>; +- reg-names = "main", "isr0", "isr1"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <3>; +- interrupt-names = "int1"; +- +- loongson,parent_int_map = <0x00000000>, /* int0 */ +- <0xffffffff>, /* int1 */ +- <0x00000000>, /* int2 */ +- <0x00000000>; /* int3 */ +- }; +- +- uart0: serial@1fe00000 { +- compatible = "ns16550a"; +- reg = <0 0x1fe00000 0 0x8>; +- clock-frequency = <125000000>; +- interrupt-parent = <&liointc0>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- no-loopback-test; +- }; +- +- pci@1a000000 { +- compatible = "loongson,ls2k-pci"; +- device_type = "pci"; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <2>; +- +- reg = <0 0x1a000000 0 0x02000000>, +- <0xfe 0x00000000 0 0x20000000>; +- +- ranges = <0x01000000 0x0 0x00000000 0x0 0x18000000 0x0 0x00010000>, +- <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; +- +- gmac@3,0 { +- compatible = "pci0014,7a03.0", +- "pci0014,7a03", +- "pciclass0c0320", +- "pciclass0c03", +- "loongson, pci-gmac"; +- +- reg = <0x1800 0x0 0x0 0x0 0x0>; +- interrupts = <12 IRQ_TYPE_LEVEL_LOW>, +- <13 IRQ_TYPE_LEVEL_LOW>; +- interrupt-names = "macirq", "eth_lpi"; +- interrupt-parent = <&liointc0>; +- phy-mode = "rgmii"; +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- }; +- +- gmac@3,1 { +- compatible = "pci0014,7a03.0", +- "pci0014,7a03", +- "pciclass0c0320", +- "pciclass0c03", +- "loongson, pci-gmac"; +- +- reg = <0x1900 0x0 0x0 0x0 0x0>; +- interrupts = <14 IRQ_TYPE_LEVEL_LOW>, +- <15 IRQ_TYPE_LEVEL_LOW>; +- interrupt-names = "macirq", "eth_lpi"; +- interrupt-parent = <&liointc0>; +- phy-mode = "rgmii"; +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy1: ethernet-phy@1 { +- reg = <0>; +- }; +- }; +- }; +- +- ehci@4,1 { +- compatible = "pci0014,7a14.0", +- "pci0014,7a14", +- "pciclass0c0320", +- "pciclass0c03"; +- +- reg = <0x2100 0x0 0x0 0x0 0x0>; +- interrupts = <18 IRQ_TYPE_LEVEL_LOW>; +- interrupt-parent = <&liointc1>; +- }; +- +- ohci@4,2 { +- compatible = "pci0014,7a24.0", +- "pci0014,7a24", +- "pciclass0c0310", +- "pciclass0c03"; +- +- reg = <0x2200 0x0 0x0 0x0 0x0>; +- interrupts = <19 IRQ_TYPE_LEVEL_LOW>; +- interrupt-parent = <&liointc1>; +- }; +- +- sata@8,0 { +- compatible = "pci0014,7a08.0", +- "pci0014,7a08", +- "pciclass010601", +- "pciclass0106"; +- +- reg = <0x4000 0x0 0x0 0x0 0x0>; +- interrupts = <19 IRQ_TYPE_LEVEL_LOW>; +- interrupt-parent = <&liointc0>; +- }; +- +- pci_bridge@9,0 { +- compatible = "pci0014,7a19.0", +- "pci0014,7a19", +- "pciclass060400", +- "pciclass0604"; +- +- reg = <0x4800 0x0 0x0 0x0 0x0>; +- #interrupt-cells = <1>; +- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +- interrupt-parent = <&liointc1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_LOW>; +- external-facing; +- }; +- +- pci_bridge@a,0 { +- compatible = "pci0014,7a09.0", +- "pci0014,7a09", +- "pciclass060400", +- "pciclass0604"; +- +- reg = <0x5000 0x0 0x0 0x0 0x0>; +- #interrupt-cells = <1>; +- interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +- interrupt-parent = <&liointc1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_LOW>; +- external-facing; +- }; +- +- pci_bridge@b,0 { +- compatible = "pci0014,7a09.0", +- "pci0014,7a09", +- "pciclass060400", +- "pciclass0604"; +- +- reg = <0x5800 0x0 0x0 0x0 0x0>; +- #interrupt-cells = <1>; +- interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +- interrupt-parent = <&liointc1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_LOW>; +- external-facing; +- }; +- +- pci_bridge@c,0 { +- compatible = "pci0014,7a09.0", +- "pci0014,7a09", +- "pciclass060400", +- "pciclass0604"; +- +- reg = <0x6000 0x0 0x0 0x0 0x0>; +- #interrupt-cells = <1>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; +- interrupt-parent = <&liointc1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_LOW>; +- external-facing; +- }; +- +- pci_bridge@d,0 { +- compatible = "pci0014,7a19.0", +- "pci0014,7a19", +- "pciclass060400", +- "pciclass0604"; +- +- reg = <0x6800 0x0 0x0 0x0 0x0>; +- #interrupt-cells = <1>; +- interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +- interrupt-parent = <&liointc1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_LOW>; +- external-facing; +- }; +- +- pci_bridge@e,0 { +- compatible = "pci0014,7a09.0", +- "pci0014,7a09", +- "pciclass060400", +- "pciclass0604"; +- +- reg = <0x7000 0x0 0x0 0x0 0x0>; +- #interrupt-cells = <1>; +- interrupts = <5 IRQ_TYPE_LEVEL_LOW>; +- interrupt-parent = <&liointc1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_LOW>; +- external-facing; +- }; +- +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/mips/loongson/loongson64_2core_2k1000.dts b/scripts/dtc/include-prefixes/mips/loongson/loongson64_2core_2k1000.dts +deleted file mode 100644 +index e31d2ee65cd5..000000000000 +--- a/scripts/dtc/include-prefixes/mips/loongson/loongson64_2core_2k1000.dts ++++ /dev/null +@@ -1,10 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/dts-v1/; +- +-#include "loongson64-2k1000.dtsi" +- +-/ { +- compatible = "loongson,loongson64-2core-2k1000"; +-}; +- +diff --git a/scripts/dtc/include-prefixes/mips/loongson/loongson64c-package.dtsi b/scripts/dtc/include-prefixes/mips/loongson/loongson64c-package.dtsi +deleted file mode 100644 +index 5bb876a4de52..000000000000 +--- a/scripts/dtc/include-prefixes/mips/loongson/loongson64c-package.dtsi ++++ /dev/null +@@ -1,64 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpuintc: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- package0: bus@1fe00000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0x1fe00000 0 0x1fe00000 0x100000 +- 0 0x3ff00000 0 0x3ff00000 0x100000 +- /* 3A HT Config Space */ +- 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000 +- /* 3B HT Config Space */ +- 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000>; +- +- liointc: interrupt-controller@3ff01400 { +- compatible = "loongson,liointc-1.0"; +- reg = <0 0x3ff01400 0x64>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <2>, <3>; +- interrupt-names = "int0", "int1"; +- +- loongson,parent_int_map = <0xf0ffffff>, /* int0 */ +- <0x0f000000>, /* int1 */ +- <0x00000000>, /* int2 */ +- <0x00000000>; /* int3 */ +- +- }; +- +- cpu_uart0: serial@1fe001e0 { +- compatible = "ns16550a"; +- reg = <0 0x1fe001e0 0x8>; +- clock-frequency = <33000000>; +- interrupt-parent = <&liointc>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; +- no-loopback-test; +- }; +- +- cpu_uart1: serial@1fe001e8 { +- status = "disabled"; +- compatible = "ns16550a"; +- reg = <0 0x1fe001e8 0x8>; +- clock-frequency = <33000000>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&liointc>; +- no-loopback-test; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/loongson/loongson64c_4core_ls7a.dts b/scripts/dtc/include-prefixes/mips/loongson/loongson64c_4core_ls7a.dts +deleted file mode 100644 +index c7ea4f1c0bb2..000000000000 +--- a/scripts/dtc/include-prefixes/mips/loongson/loongson64c_4core_ls7a.dts ++++ /dev/null +@@ -1,37 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/dts-v1/; +- +-#include "loongson64c-package.dtsi" +-#include "ls7a-pch.dtsi" +- +-/ { +- compatible = "loongson,loongson64c-4core-ls7a"; +-}; +- +-&package0 { +- htvec: interrupt-controller@efdfb000080 { +- compatible = "loongson,htvec-1.0"; +- reg = <0xefd 0xfb000080 0x40>; +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&liointc>; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, +- <25 IRQ_TYPE_LEVEL_HIGH>, +- <26 IRQ_TYPE_LEVEL_HIGH>, +- <27 IRQ_TYPE_LEVEL_HIGH>; +- }; +-}; +- +-&pch { +- msi: msi-controller@2ff00000 { +- compatible = "loongson,pch-msi-1.0"; +- reg = <0 0x2ff00000 0 0x8>; +- interrupt-controller; +- msi-controller; +- loongson,msi-base-vec = <64>; +- loongson,msi-num-vecs = <64>; +- interrupt-parent = <&htvec>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/loongson/loongson64c_4core_rs780e.dts b/scripts/dtc/include-prefixes/mips/loongson/loongson64c_4core_rs780e.dts +deleted file mode 100644 +index d681a295df4f..000000000000 +--- a/scripts/dtc/include-prefixes/mips/loongson/loongson64c_4core_rs780e.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/dts-v1/; +- +-#include "loongson64c-package.dtsi" +-#include "rs780e-pch.dtsi" +- +-/ { +- compatible = "loongson,loongson64c-4core-rs780e"; +-}; +- +-&package0 { +- htpic: interrupt-controller@efdfb000080 { +- compatible = "loongson,htpic-1.0"; +- reg = <0xefd 0xfb000080 0x40>; +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&liointc>; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, +- <25 IRQ_TYPE_LEVEL_HIGH>, +- <26 IRQ_TYPE_LEVEL_HIGH>, +- <27 IRQ_TYPE_LEVEL_HIGH>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/loongson/loongson64c_8core_rs780e.dts b/scripts/dtc/include-prefixes/mips/loongson/loongson64c_8core_rs780e.dts +deleted file mode 100644 +index 3c2044142ce8..000000000000 +--- a/scripts/dtc/include-prefixes/mips/loongson/loongson64c_8core_rs780e.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/dts-v1/; +- +-#include "loongson64c-package.dtsi" +-#include "rs780e-pch.dtsi" +- +-/ { +- compatible = "loongson,loongson64c-8core-rs780e"; +-}; +- +-&package0 { +- htpic: interrupt-controller@1efdfb000080 { +- compatible = "loongson,htpic-1.0"; +- reg = <0x1efd 0xfb000080 0x40>; +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&liointc>; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, +- <25 IRQ_TYPE_LEVEL_HIGH>, +- <26 IRQ_TYPE_LEVEL_HIGH>, +- <27 IRQ_TYPE_LEVEL_HIGH>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/loongson/loongson64g-package.dtsi b/scripts/dtc/include-prefixes/mips/loongson/loongson64g-package.dtsi +deleted file mode 100644 +index d4314f62ccc2..000000000000 +--- a/scripts/dtc/include-prefixes/mips/loongson/loongson64g-package.dtsi ++++ /dev/null +@@ -1,61 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpuintc: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- package0: bus@1fe00000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0x1fe00000 0 0x1fe00000 0x100000 +- 0 0x3ff00000 0 0x3ff00000 0x100000 +- 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>; +- +- liointc: interrupt-controller@3ff01400 { +- compatible = "loongson,liointc-1.0"; +- reg = <0 0x3ff01400 0x64>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <2>, <3>; +- interrupt-names = "int0", "int1"; +- +- loongson,parent_int_map = <0x00ffffff>, /* int0 */ +- <0xff000000>, /* int1 */ +- <0x00000000>, /* int2 */ +- <0x00000000>; /* int3 */ +- +- }; +- +- cpu_uart0: serial@1fe00100 { +- compatible = "ns16550a"; +- reg = <0 0x1fe00100 0x10>; +- clock-frequency = <100000000>; +- interrupt-parent = <&liointc>; +- interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; +- no-loopback-test; +- }; +- +- cpu_uart1: serial@1fe00110 { +- status = "disabled"; +- compatible = "ns16550a"; +- reg = <0 0x1fe00110 0x10>; +- clock-frequency = <100000000>; +- interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&liointc>; +- no-loopback-test; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/loongson/loongson64g_4core_ls7a.dts b/scripts/dtc/include-prefixes/mips/loongson/loongson64g_4core_ls7a.dts +deleted file mode 100644 +index c945f8565d54..000000000000 +--- a/scripts/dtc/include-prefixes/mips/loongson/loongson64g_4core_ls7a.dts ++++ /dev/null +@@ -1,41 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/dts-v1/; +- +-#include "loongson64g-package.dtsi" +-#include "ls7a-pch.dtsi" +- +-/ { +- compatible = "loongson,loongson64g-4core-ls7a"; +-}; +- +-&package0 { +- htvec: interrupt-controller@efdfb000080 { +- compatible = "loongson,htvec-1.0"; +- reg = <0xefd 0xfb000080 0x40>; +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&liointc>; +- interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, +- <25 IRQ_TYPE_LEVEL_HIGH>, +- <26 IRQ_TYPE_LEVEL_HIGH>, +- <27 IRQ_TYPE_LEVEL_HIGH>, +- <28 IRQ_TYPE_LEVEL_HIGH>, +- <29 IRQ_TYPE_LEVEL_HIGH>, +- <30 IRQ_TYPE_LEVEL_HIGH>, +- <31 IRQ_TYPE_LEVEL_HIGH>; +- }; +-}; +- +-&pch { +- msi: msi-controller@2ff00000 { +- compatible = "loongson,pch-msi-1.0"; +- reg = <0 0x2ff00000 0 0x8>; +- interrupt-controller; +- msi-controller; +- loongson,msi-base-vec = <64>; +- loongson,msi-num-vecs = <192>; +- interrupt-parent = <&htvec>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/loongson/loongson64v_4core_virtio.dts b/scripts/dtc/include-prefixes/mips/loongson/loongson64v_4core_virtio.dts +deleted file mode 100644 +index d0588d81e0c2..000000000000 +--- a/scripts/dtc/include-prefixes/mips/loongson/loongson64v_4core_virtio.dts ++++ /dev/null +@@ -1,102 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-#include +- +-/dts-v1/; +-/ { +- compatible = "loongson,loongson64v-4core-virtio"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpuintc: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- package0: bus@1fe00000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0x1fe00000 0 0x1fe00000 0x100000 +- 0 0x3ff00000 0 0x3ff00000 0x100000 +- 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>; +- +- liointc: interrupt-controller@3ff01400 { +- compatible = "loongson,liointc-1.0"; +- reg = <0 0x3ff01400 0x64>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <2>, <3>; +- interrupt-names = "int0", "int1"; +- +- loongson,parent_int_map = <0x00000001>, /* int0 */ +- <0xfffffffe>, /* int1 */ +- <0x00000000>, /* int2 */ +- <0x00000000>; /* int3 */ +- +- }; +- +- cpu_uart0: serial@1fe001e0 { +- compatible = "ns16550a"; +- reg = <0 0x1fe001e0 0x8>; +- clock-frequency = <33000000>; +- interrupt-parent = <&liointc>; +- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; +- no-loopback-test; +- }; +- }; +- +- bus@10000000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */ +- 0 0x40000000 0 0x40000000 0 0x40000000>; /* PCI MEM */ +- +- rtc0: rtc@10081000 { +- compatible = "google,goldfish-rtc"; +- reg = <0 0x10081000 0 0x1000>; +- interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&liointc>; +- }; +- +- pci@1a000000 { +- compatible = "pci-host-ecam-generic"; +- device_type = "pci"; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- +- bus-range = <0x0 0x1f>; +- reg = <0 0x1a000000 0 0x02000000>; +- +- ranges = <0x01000000 0x0 0x00004000 0x0 0x18004000 0x0 0x0000c000>, +- <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; +- +- interrupt-map = < +- 0x0000 0x0 0x0 0x1 &liointc 0x2 IRQ_TYPE_LEVEL_HIGH +- 0x0800 0x0 0x0 0x1 &liointc 0x3 IRQ_TYPE_LEVEL_HIGH +- 0x1000 0x0 0x0 0x1 &liointc 0x4 IRQ_TYPE_LEVEL_HIGH +- 0x1800 0x0 0x0 0x1 &liointc 0x5 IRQ_TYPE_LEVEL_HIGH +- >; +- +- interrupt-map-mask = <0x1800 0x0 0x0 0x7>; +- }; +- +- isa@18000000 { +- compatible = "isa"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <1 0 0 0x18000000 0x4000>; +- }; +- }; +- +- hypervisor { +- compatible = "linux,kvm"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/loongson/ls7a-pch.dtsi b/scripts/dtc/include-prefixes/mips/loongson/ls7a-pch.dtsi +deleted file mode 100644 +index 2f45fce2cdc4..000000000000 +--- a/scripts/dtc/include-prefixes/mips/loongson/ls7a-pch.dtsi ++++ /dev/null +@@ -1,419 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/ { +- pch: bus@10000000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */ +- 0 0x20000000 0 0x20000000 0 0x10000000 +- 0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */ +- 0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>; +- +- pic: interrupt-controller@10000000 { +- compatible = "loongson,pch-pic-1.0"; +- reg = <0 0x10000000 0 0x400>; +- interrupt-controller; +- interrupt-parent = <&htvec>; +- loongson,pic-base-vec = <0>; +- #interrupt-cells = <2>; +- }; +- +- ls7a_uart0: serial@10080000 { +- compatible = "ns16550a"; +- reg = <0 0x10080000 0 0x100>; +- clock-frequency = <50000000>; +- interrupt-parent = <&pic>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; +- no-loopback-test; +- }; +- +- ls7a_uart1: serial@10080100 { +- status = "disabled"; +- compatible = "ns16550a"; +- reg = <0 0x10080100 0 0x100>; +- clock-frequency = <50000000>; +- interrupt-parent = <&pic>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; +- no-loopback-test; +- }; +- +- ls7a_uart2: serial@10080200 { +- status = "disabled"; +- compatible = "ns16550a"; +- reg = <0 0x10080200 0 0x100>; +- clock-frequency = <50000000>; +- interrupt-parent = <&pic>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; +- no-loopback-test; +- }; +- +- ls7a_uart3: serial@10080300 { +- status = "disabled"; +- compatible = "ns16550a"; +- reg = <0 0x10080300 0 0x100>; +- clock-frequency = <50000000>; +- interrupt-parent = <&pic>; +- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; +- no-loopback-test; +- }; +- +- pci@1a000000 { +- compatible = "loongson,ls7a-pci"; +- device_type = "pci"; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <2>; +- msi-parent = <&msi>; +- +- reg = <0 0x1a000000 0 0x02000000>, +- <0xefe 0x00000000 0 0x20000000>; +- +- ranges = <0x01000000 0x0 0x00020000 0x0 0x18020000 0x0 0x00020000>, +- <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; +- +- ohci@4,0 { +- compatible = "pci0014,7a24.0", +- "pci0014,7a24", +- "pciclass0c0310", +- "pciclass0c03"; +- +- reg = <0x2000 0x0 0x0 0x0 0x0>; +- interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- }; +- +- ehci@4,1 { +- compatible = "pci0014,7a14.0", +- "pci0014,7a14", +- "pciclass0c0320", +- "pciclass0c03"; +- +- reg = <0x2100 0x0 0x0 0x0 0x0>; +- interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- }; +- +- ohci@5,0 { +- compatible = "pci0014,7a24.0", +- "pci0014,7a24", +- "pciclass0c0310", +- "pciclass0c03"; +- +- reg = <0x2800 0x0 0x0 0x0 0x0>; +- interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- }; +- +- ehci@5,1 { +- compatible = "pci0014,7a14.0", +- "pci0014,7a14", +- "pciclass0c0320", +- "pciclass0c03"; +- +- reg = <0x2900 0x0 0x0 0x0 0x0>; +- interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- }; +- +- sata@8,0 { +- compatible = "pci0014,7a08.0", +- "pci0014,7a08", +- "pciclass010601", +- "pciclass0106"; +- +- reg = <0x4000 0x0 0x0 0x0 0x0>; +- interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- }; +- +- sata@8,1 { +- compatible = "pci0014,7a08.0", +- "pci0014,7a08", +- "pciclass010601", +- "pciclass0106"; +- +- reg = <0x4100 0x0 0x0 0x0 0x0>; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- }; +- +- sata@8,2 { +- compatible = "pci0014,7a08.0", +- "pci0014,7a08", +- "pciclass010601", +- "pciclass0106"; +- +- reg = <0x4200 0x0 0x0 0x0 0x0>; +- interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- }; +- +- gpu@6,0 { +- compatible = "pci0014,7a15.0", +- "pci0014,7a15", +- "pciclass030200", +- "pciclass0302"; +- +- reg = <0x3000 0x0 0x0 0x0 0x0>; +- interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- }; +- +- dc@6,1 { +- compatible = "pci0014,7a06.0", +- "pci0014,7a06", +- "pciclass030000", +- "pciclass0300"; +- +- reg = <0x3100 0x0 0x0 0x0 0x0>; +- interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- }; +- +- hda@7,0 { +- compatible = "pci0014,7a07.0", +- "pci0014,7a07", +- "pciclass040300", +- "pciclass0403"; +- +- reg = <0x3800 0x0 0x0 0x0 0x0>; +- interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- }; +- +- gmac@3,0 { +- compatible = "pci0014,7a03.0", +- "pci0014,7a03", +- "pciclass020000", +- "pciclass0200", +- "loongson, pci-gmac"; +- +- reg = <0x1800 0x0 0x0 0x0 0x0>; +- interrupts = <12 IRQ_TYPE_LEVEL_HIGH>, +- <13 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "macirq", "eth_lpi"; +- interrupt-parent = <&pic>; +- phy-mode = "rgmii"; +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- }; +- +- gmac@3,1 { +- compatible = "pci0014,7a03.0", +- "pci0014,7a03", +- "pciclass020000", +- "pciclass0200", +- "loongson, pci-gmac"; +- +- reg = <0x1900 0x0 0x0 0x0 0x0>; +- interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, +- <15 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "macirq", "eth_lpi"; +- interrupt-parent = <&pic>; +- phy-mode = "rgmii"; +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy1: ethernet-phy@1 { +- reg = <0>; +- }; +- }; +- }; +- +- pci_bridge@9,0 { +- compatible = "pci0014,7a19.1", +- "pci0014,7a19", +- "pciclass060400", +- "pciclass0604"; +- +- reg = <0x4800 0x0 0x0 0x0 0x0>; +- interrupts = <32 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- pci_bridge@a,0 { +- compatible = "pci0014,7a09.1", +- "pci0014,7a09", +- "pciclass060400", +- "pciclass0604"; +- +- reg = <0x5000 0x0 0x0 0x0 0x0>; +- interrupts = <33 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- pci_bridge@b,0 { +- compatible = "pci0014,7a09.1", +- "pci0014,7a09", +- "pciclass060400", +- "pciclass0604"; +- +- reg = <0x5800 0x0 0x0 0x0 0x0>; +- interrupts = <34 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- pci_bridge@c,0 { +- compatible = "pci0014,7a09.1", +- "pci0014,7a09", +- "pciclass060400", +- "pciclass0604"; +- +- reg = <0x6000 0x0 0x0 0x0 0x0>; +- interrupts = <35 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- pci_bridge@d,0 { +- compatible = "pci0014,7a19.1", +- "pci0014,7a19", +- "pciclass060400", +- "pciclass0604"; +- +- reg = <0x6800 0x0 0x0 0x0 0x0>; +- interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- pci_bridge@e,0 { +- compatible = "pci0014,7a09.1", +- "pci0014,7a09", +- "pciclass060400", +- "pciclass0604"; +- +- reg = <0x7000 0x0 0x0 0x0 0x0>; +- interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- pci_bridge@f,0 { +- compatible = "pci0014,7a29.1", +- "pci0014,7a29", +- "pciclass060400", +- "pciclass0604"; +- +- reg = <0x7800 0x0 0x0 0x0 0x0>; +- interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- pci_bridge@10,0 { +- compatible = "pci0014,7a19.1", +- "pci0014,7a19", +- "pciclass060400", +- "pciclass0604"; +- +- reg = <0x8000 0x0 0x0 0x0 0x0>; +- interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- pci_bridge@11,0 { +- compatible = "pci0014,7a29.1", +- "pci0014,7a29", +- "pciclass060400", +- "pciclass0604"; +- +- reg = <0x8800 0x0 0x0 0x0 0x0>; +- interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- pci_bridge@12,0 { +- compatible = "pci0014,7a19.1", +- "pci0014,7a19", +- "pciclass060400", +- "pciclass0604"; +- +- reg = <0x9000 0x0 0x0 0x0 0x0>; +- interrupts = <43 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &pic 43 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- pci_bridge@13,0 { +- compatible = "pci0014,7a29.1", +- "pci0014,7a29", +- "pciclass060400", +- "pciclass0604"; +- +- reg = <0x9800 0x0 0x0 0x0 0x0>; +- interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &pic 38 IRQ_TYPE_LEVEL_HIGH>; +- }; +- +- pci_bridge@14,0 { +- compatible = "pci0014,7a19.1", +- "pci0014,7a19", +- "pciclass060400", +- "pciclass0604"; +- +- reg = <0xa000 0x0 0x0 0x0 0x0>; +- interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&pic>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>; +- }; +- }; +- +- isa@18000000 { +- compatible = "isa"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <1 0 0 0x18000000 0x20000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/loongson/rs780e-pch.dtsi b/scripts/dtc/include-prefixes/mips/loongson/rs780e-pch.dtsi +deleted file mode 100644 +index 6f459511e6c9..000000000000 +--- a/scripts/dtc/include-prefixes/mips/loongson/rs780e-pch.dtsi ++++ /dev/null +@@ -1,43 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/ { +- bus@10000000 { +- compatible = "simple-bus"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges = <0 0x10000000 0 0x10000000 0 0x10000000 +- 0 0x40000000 0 0x40000000 0 0x40000000 +- 0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>; +- +- pci@1a000000 { +- compatible = "loongson,rs780e-pci"; +- device_type = "pci"; +- #address-cells = <3>; +- #size-cells = <2>; +- +- reg = <0 0x1a000000 0 0x02000000>; +- +- ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x0000c000>, +- <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>; +- }; +- +- isa@18000000 { +- compatible = "isa"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <1 0 0 0x18000000 0x4000>; +- +- rtc0: rtc@70 { +- compatible = "motorola,mc146818"; +- reg = <1 0x70 0x8>; +- interrupts = <8>; +- interrupt-parent = <&htpic>; +- }; +- +- acpi@800 { +- compatible = "loongson,rs780e-acpi"; +- reg = <1 0x800 0x100>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/mscc/Makefile b/scripts/dtc/include-prefixes/mips/mscc/Makefile +deleted file mode 100644 +index eeb6b7aae83b..000000000000 +--- a/scripts/dtc/include-prefixes/mips/mscc/Makefile ++++ /dev/null +@@ -1,13 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0-only +-dtb-$(CONFIG_SOC_VCOREIII) += \ +- jaguar2_pcb110.dtb \ +- jaguar2_pcb111.dtb \ +- jaguar2_pcb118.dtb \ +- luton_pcb091.dtb \ +- ocelot_pcb120.dtb \ +- ocelot_pcb123.dtb \ +- serval_pcb105.dtb \ +- serval_pcb106.dtb +- +- +-obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) +diff --git a/scripts/dtc/include-prefixes/mips/mscc/jaguar2.dtsi b/scripts/dtc/include-prefixes/mips/mscc/jaguar2.dtsi +deleted file mode 100644 +index 42b2b0a51ddc..000000000000 +--- a/scripts/dtc/include-prefixes/mips/mscc/jaguar2.dtsi ++++ /dev/null +@@ -1,167 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Microsemi Corporation +- */ +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mscc,jr2"; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart2; +- gpio0 = &gpio; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "mips,mips24KEc"; +- device_type = "cpu"; +- clocks = <&cpu_clk>; +- reg = <0>; +- }; +- }; +- +- cpuintc: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- cpu_clk: cpu-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <500000000>; +- }; +- +- ahb_clk: ahb-clk { +- compatible = "fixed-factor-clock"; +- #clock-cells = <0>; +- clocks = <&cpu_clk>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- ahb: ahb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- interrupt-parent = <&intc>; +- +- cpu_ctrl: syscon@70000000 { +- compatible = "mscc,ocelot-cpu-syscon", "syscon"; +- reg = <0x70000000 0x2c>; +- }; +- +- intc: interrupt-controller@70000070 { +- compatible = "mscc,jaguar2-icpu-intr"; +- reg = <0x70000070 0x94>; +- #interrupt-cells = <1>; +- interrupt-controller; +- interrupt-parent = <&cpuintc>; +- interrupts = <2>; +- }; +- +- uart0: serial@70100000 { +- pinctrl-0 = <&uart_pins>; +- pinctrl-names = "default"; +- compatible = "ns16550a"; +- reg = <0x70100000 0x20>; +- interrupts = <6>; +- clocks = <&ahb_clk>; +- reg-io-width = <4>; +- reg-shift = <2>; +- +- status = "disabled"; +- }; +- +- uart2: serial@70100800 { +- pinctrl-0 = <&uart2_pins>; +- pinctrl-names = "default"; +- compatible = "ns16550a"; +- reg = <0x70100800 0x20>; +- interrupts = <7>; +- clocks = <&ahb_clk>; +- reg-io-width = <4>; +- reg-shift = <2>; +- +- status = "disabled"; +- }; +- +- gpio: pinctrl@71010038 { +- compatible = "mscc,jaguar2-pinctrl"; +- reg = <0x71010038 0x90>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&gpio 0 0 64>; +- +- uart_pins: uart-pins { +- pins = "GPIO_10", "GPIO_11"; +- function = "uart"; +- }; +- +- uart2_pins: uart2-pins { +- pins = "GPIO_24", "GPIO_25"; +- function = "uart2"; +- }; +- +- cs1_pins: cs1-pins { +- pins = "GPIO_16"; +- function = "si"; +- }; +- +- cs2_pins: cs2-pins { +- pins = "GPIO_17"; +- function = "si"; +- }; +- +- cs3_pins: cs3-pins { +- pins = "GPIO_18"; +- function = "si"; +- }; +- +- i2c_pins: i2c-pins { +- pins = "GPIO_14", "GPIO_15"; +- function = "twi"; +- }; +- +- i2c2_pins: i2c2-pins { +- pins = "GPIO_28", "GPIO_29"; +- function = "twi2"; +- }; +- }; +- +- i2c0: i2c@70100400 { +- compatible = "mscc,ocelot-i2c", "snps,designware-i2c"; +- status = "disabled"; +- pinctrl-0 = <&i2c_pins>; +- pinctrl-names = "default"; +- reg = <0x70100400 0x100>, <0x700001b8 0x8>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <8>; +- clock-frequency = <100000>; +- clocks = <&ahb_clk>; +- }; +- +- i2c2: i2c@70100c00 { +- compatible = "mscc,ocelot-i2c", "snps,designware-i2c"; +- status = "disabled"; +- pinctrl-0 = <&i2c2_pins>; +- pinctrl-names = "default"; +- reg = <0x70100c00 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <8>; +- clock-frequency = <100000>; +- clocks = <&ahb_clk>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/mscc/jaguar2_common.dtsi b/scripts/dtc/include-prefixes/mips/mscc/jaguar2_common.dtsi +deleted file mode 100644 +index 679ff0d8eda8..000000000000 +--- a/scripts/dtc/include-prefixes/mips/mscc/jaguar2_common.dtsi ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Microsemi Corporation +- */ +- +-#include "jaguar2.dtsi" +- +-/ { +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- i2c-sda-hold-time-ns = <300>; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/mscc/jaguar2_pcb110.dts b/scripts/dtc/include-prefixes/mips/mscc/jaguar2_pcb110.dts +deleted file mode 100644 +index d80cd6842b2a..000000000000 +--- a/scripts/dtc/include-prefixes/mips/mscc/jaguar2_pcb110.dts ++++ /dev/null +@@ -1,267 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Microsemi Corporation +- */ +- +-/dts-v1/; +-#include "jaguar2_common.dtsi" +-#include +- +-/ { +- model = "Jaguar2 Cu8-Sfp16 PCB110 Reference Board"; +- compatible = "mscc,jr2-pcb110", "mscc,jr2"; +- +- aliases { +- i2c0 = &i2c0; +- i2c108 = &i2c108; +- i2c109 = &i2c109; +- i2c110 = &i2c110; +- i2c111 = &i2c111; +- i2c112 = &i2c112; +- i2c113 = &i2c113; +- i2c114 = &i2c114; +- i2c115 = &i2c115; +- i2c116 = &i2c116; +- i2c117 = &i2c117; +- i2c118 = &i2c118; +- i2c119 = &i2c119; +- i2c120 = &i2c120; +- i2c121 = &i2c121; +- i2c122 = &i2c122; +- i2c123 = &i2c123; +- i2c124 = &i2c124; +- i2c125 = &i2c125; +- i2c126 = &i2c126; +- i2c127 = &i2c127; +- i2c128 = &i2c128; +- i2c129 = &i2c129; +- i2c130 = &i2c130; +- i2c131 = &i2c131; +- i2c149 = &i2c149; +- i2c150 = &i2c150; +- i2c151 = &i2c151; +- i2c152 = &i2c152; +- }; +- i2c0_imux: i2c0-imux { +- compatible = "i2c-mux-pinctrl"; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-parent = <&i2c0>; +- pinctrl-names = +- "i2c149", "i2c150", "i2c151", "i2c152", "idle"; +- pinctrl-0 = <&i2cmux_0>; +- pinctrl-1 = <&i2cmux_1>; +- pinctrl-2 = <&i2cmux_2>; +- pinctrl-3 = <&i2cmux_3>; +- pinctrl-4 = <&i2cmux_pins_i>; +- i2c149: i2c@0 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c150: i2c@1 { +- reg = <0x1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c151: i2c@2 { +- reg = <0x2>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c152: i2c@3 { +- reg = <0x3>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- i2c0_emux: i2c0-emux { +- compatible = "i2c-mux-gpio"; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-parent = <&i2c0>; +- mux-gpios = <&gpio 51 GPIO_ACTIVE_HIGH +- &gpio 52 GPIO_ACTIVE_HIGH +- &gpio 53 GPIO_ACTIVE_HIGH +- &gpio 58 GPIO_ACTIVE_HIGH +- &gpio 59 GPIO_ACTIVE_HIGH>; +- idle-state = <0x0>; +- i2c108: i2c@10 { +- reg = <0x10>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c109: i2c@11 { +- reg = <0x11>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c110: i2c@12 { +- reg = <0x12>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c111: i2c@13 { +- reg = <0x13>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c112: i2c@14 { +- reg = <0x14>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c113: i2c@15 { +- reg = <0x15>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c114: i2c@16 { +- reg = <0x16>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c115: i2c@17 { +- reg = <0x17>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c116: i2c@8 { +- reg = <0x8>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c117: i2c@9 { +- reg = <0x9>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c118: i2c@a { +- reg = <0xa>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c119: i2c@b { +- reg = <0xb>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c120: i2c@c { +- reg = <0xc>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c121: i2c@d { +- reg = <0xd>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c122: i2c@e { +- reg = <0xe>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c123: i2c@f { +- reg = <0xf>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +-}; +- +-&gpio { +- synce_pins: synce-pins { +- // GPIO 16 == SI_nCS1 +- pins = "GPIO_16"; +- function = "si"; +- }; +- synce_builtin_pins: synce-builtin-pins { +- // GPIO 49 == SI_nCS13 +- pins = "GPIO_49"; +- function = "si"; +- }; +- i2cmux_pins_i: i2cmux-pins-i { +- pins = "GPIO_17", "GPIO_18", "GPIO_20", "GPIO_21"; +- function = "twi_scl_m"; +- output-low; +- }; +- i2cmux_0: i2cmux-0 { +- pins = "GPIO_17"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_1: i2cmux-1 { +- pins = "GPIO_18"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_2: i2cmux-2 { +- pins = "GPIO_20"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_3: i2cmux-3 { +- pins = "GPIO_21"; +- function = "twi_scl_m"; +- output-high; +- }; +-}; +- +-&i2c0 { +- pca9545@70 { +- compatible = "nxp,pca9545"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-mux-idle-disconnect; +- i2c124: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- i2c125: i2c@1 { +- /* FMC B */ +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- i2c126: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- i2c127: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +- pca9545@71 { +- compatible = "nxp,pca9545"; +- reg = <0x71>; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-mux-idle-disconnect; +- i2c128: i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- i2c129: i2c@1 { +- /* FMC B */ +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- i2c130: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- i2c131: i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/mscc/jaguar2_pcb111.dts b/scripts/dtc/include-prefixes/mips/mscc/jaguar2_pcb111.dts +deleted file mode 100644 +index 813c5e16013c..000000000000 +--- a/scripts/dtc/include-prefixes/mips/mscc/jaguar2_pcb111.dts ++++ /dev/null +@@ -1,107 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Microsemi Corporation +- */ +- +-/dts-v1/; +-#include "jaguar2_common.dtsi" +- +-/ { +- model = "Jaguar2 Cu48 PCB111 Reference Board"; +- compatible = "mscc,jr2-pcb111", "mscc,jr2"; +- +- aliases { +- i2c0 = &i2c0; +- i2c149 = &i2c149; +- i2c150 = &i2c150; +- i2c151 = &i2c151; +- i2c152 = &i2c152; +- i2c203 = &i2c203; +- }; +- +- i2c0_imux: i2c0-imux { +- compatible = "i2c-mux-pinctrl"; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-parent = <&i2c0>; +- pinctrl-names = +- "i2c149", "i2c150", "i2c151", "i2c152", "i2c203", "idle"; +- pinctrl-0 = <&i2cmux_0>; +- pinctrl-1 = <&i2cmux_1>; +- pinctrl-2 = <&i2cmux_2>; +- pinctrl-3 = <&i2cmux_3>; +- pinctrl-4 = <&i2cmux_pins_i>; // Added by convention for PoE +- pinctrl-5 = <&i2cmux_pins_i>; +- i2c149: i2c@0 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c150: i2c@1 { +- reg = <0x1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c151: i2c@2 { +- reg = <0x2>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c152: i2c@3 { +- reg = <0x3>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c203: i2c@4 { +- reg = <0x4>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +-}; +- +-&gpio { +- synce_builtin_pins: synce-builtin-pins { +- // GPIO 49 == SI_nCS13 +- pins = "GPIO_49"; +- function = "si"; +- }; +- cpld_pins: cpld-pins { +- // GPIO 50 == SI_nCS14 +- pins = "GPIO_50"; +- function = "si"; +- }; +- cpld_fifo_pins: synce-builtin-pins { +- // GPIO 51 == SI_nCS15 +- pins = "GPIO_51"; +- function = "si"; +- }; +-}; +- +-&gpio { +- i2cmux_pins_i: i2cmux-pins-i { +- pins = "GPIO_17", "GPIO_18"; +- function = "twi_scl_m"; +- output-low; +- }; +- i2cmux_0: i2cmux-0 { +- pins = "GPIO_17"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_1: i2cmux-1 { +- pins = "GPIO_18"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_2: i2cmux-2 { +- pins = "GPIO_20"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_3: i2cmux-3 { +- pins = "GPIO_21"; +- function = "twi_scl_m"; +- output-high; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/mscc/jaguar2_pcb118.dts b/scripts/dtc/include-prefixes/mips/mscc/jaguar2_pcb118.dts +deleted file mode 100644 +index 27c644f2d17f..000000000000 +--- a/scripts/dtc/include-prefixes/mips/mscc/jaguar2_pcb118.dts ++++ /dev/null +@@ -1,57 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Microsemi Corporation +- */ +- +-/dts-v1/; +-#include "jaguar2_common.dtsi" +- +-/ { +- model = "Jaguar2/Aquantia PCB118 Reference Board"; +- compatible = "mscc,jr2-pcb118", "mscc,jr2"; +- +- aliases { +- i2c150 = &i2c150; +- i2c151 = &i2c151; +- }; +- +- i2c0_imux: i2c0-imux { +- compatible = "i2c-mux-pinctrl"; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-parent = <&i2c0>; +- pinctrl-names = +- "i2c150", "i2c151", "idle"; +- pinctrl-0 = <&i2cmux_0>; +- pinctrl-1 = <&i2cmux_1>; +- pinctrl-2 = <&i2cmux_pins_i>; +- i2c150: i2c@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c151: i2c@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +-}; +- +-&gpio { +- i2cmux_pins_i: i2cmux-pins-i { +- pins = "GPIO_17", "GPIO_16"; +- function = "twi_scl_m"; +- output-low; +- }; +- i2cmux_0: i2cmux-0 { +- pins = "GPIO_17"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_1: i2cmux-1 { +- pins = "GPIO_16"; +- function = "twi_scl_m"; +- output-high; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/mscc/luton.dtsi b/scripts/dtc/include-prefixes/mips/mscc/luton.dtsi +deleted file mode 100644 +index 2a170b84c5a9..000000000000 +--- a/scripts/dtc/include-prefixes/mips/mscc/luton.dtsi ++++ /dev/null +@@ -1,116 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* Copyright (c) 2020 Microsemi Corporation */ +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mscc,luton"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "mips,mips24KEc"; +- device_type = "cpu"; +- clocks = <&cpu_clk>; +- reg = <0>; +- }; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- cpuintc: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- cpu_clk: cpu-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <416666666>; +- }; +- +- ahb_clk: ahb-clk { +- compatible = "fixed-factor-clock"; +- #clock-cells = <0>; +- clocks = <&cpu_clk>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- ahb@60000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x60000000 0x20000000>; +- +- interrupt-parent = <&intc>; +- +- cpu_ctrl: syscon@10000000 { +- compatible = "mscc,ocelot-cpu-syscon", "syscon"; +- reg = <0x10000000 0x2c>; +- }; +- +- intc: interrupt-controller@10000084 { +- compatible = "mscc,luton-icpu-intr"; +- reg = <0x10000084 0x70>; +- #interrupt-cells = <1>; +- interrupt-controller; +- interrupt-parent = <&cpuintc>; +- interrupts = <2>; +- }; +- +- uart0: serial@10100000 { +- pinctrl-0 = <&uart_pins>; +- pinctrl-names = "default"; +- compatible = "ns16550a"; +- reg = <0x10100000 0x20>; +- interrupts = <6>; +- clocks = <&ahb_clk>; +- reg-io-width = <4>; +- reg-shift = <2>; +- +- status = "disabled"; +- }; +- +- i2c0: i2c@10100400 { +- compatible = "mscc,ocelot-i2c", "snps,designware-i2c"; +- pinctrl-0 = <&i2c_pins>; +- pinctrl-names = "default"; +- reg = <0x10100400 0x100>, <0x100002a4 0x8>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <11>; +- clocks = <&ahb_clk>; +- +- status = "disabled"; +- }; +- +- gpio: pinctrl@70068 { +- compatible = "mscc,luton-pinctrl"; +- reg = <0x70068 0x28>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&gpio 0 0 32>; +- interrupt-controller; +- interrupts = <13>; +- #interrupt-cells = <2>; +- +- i2c_pins: i2c-pins { +- pins = "GPIO_5", "GPIO_6"; +- function = "twi"; +- }; +- +- uart_pins: uart-pins { +- pins = "GPIO_30", "GPIO_31"; +- function = "uart"; +- }; +- +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/mscc/luton_pcb091.dts b/scripts/dtc/include-prefixes/mips/mscc/luton_pcb091.dts +deleted file mode 100644 +index 26ef6285d71d..000000000000 +--- a/scripts/dtc/include-prefixes/mips/mscc/luton_pcb091.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Microsemi Corporation +- */ +- +-/dts-v1/; +- +-#include "luton.dtsi" +- +-/ { +- model = "Luton10 PCB091 Reference Board"; +- compatible = "mscc,luton-pcb091", "mscc,luton"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- i2c-sda-hold-time-ns = <300>; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/mscc/ocelot.dtsi b/scripts/dtc/include-prefixes/mips/mscc/ocelot.dtsi +deleted file mode 100644 +index e51db651af13..000000000000 +--- a/scripts/dtc/include-prefixes/mips/mscc/ocelot.dtsi ++++ /dev/null +@@ -1,278 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* Copyright (c) 2017 Microsemi Corporation */ +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mscc,ocelot"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "mips,mips24KEc"; +- device_type = "cpu"; +- clocks = <&cpu_clk>; +- reg = <0>; +- }; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +- +- cpuintc: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- cpu_clk: cpu-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <500000000>; +- }; +- +- ahb_clk: ahb-clk { +- compatible = "fixed-factor-clock"; +- #clock-cells = <0>; +- clocks = <&cpu_clk>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- ahb@70000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x70000000 0x2000000>; +- +- interrupt-parent = <&intc>; +- +- cpu_ctrl: syscon@0 { +- compatible = "mscc,ocelot-cpu-syscon", "syscon"; +- reg = <0x0 0x2c>; +- }; +- +- intc: interrupt-controller@70 { +- compatible = "mscc,ocelot-icpu-intr"; +- reg = <0x70 0x70>; +- #interrupt-cells = <1>; +- interrupt-controller; +- interrupt-parent = <&cpuintc>; +- interrupts = <2>; +- }; +- +- uart0: serial@100000 { +- pinctrl-0 = <&uart_pins>; +- pinctrl-names = "default"; +- compatible = "ns16550a"; +- reg = <0x100000 0x20>; +- interrupts = <6>; +- clocks = <&ahb_clk>; +- reg-io-width = <4>; +- reg-shift = <2>; +- +- status = "disabled"; +- }; +- +- i2c: i2c@100400 { +- compatible = "mscc,ocelot-i2c", "snps,designware-i2c"; +- pinctrl-0 = <&i2c_pins>; +- pinctrl-names = "default"; +- reg = <0x100400 0x100>, <0x198 0x8>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <8>; +- clocks = <&ahb_clk>; +- +- status = "disabled"; +- }; +- +- uart2: serial@100800 { +- pinctrl-0 = <&uart2_pins>; +- pinctrl-names = "default"; +- compatible = "ns16550a"; +- reg = <0x100800 0x20>; +- interrupts = <7>; +- clocks = <&ahb_clk>; +- reg-io-width = <4>; +- reg-shift = <2>; +- +- status = "disabled"; +- }; +- +- spi: spi@101000 { +- compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x101000 0x100>, <0x3c 0x18>; +- interrupts = <9>; +- clocks = <&ahb_clk>; +- +- status = "disabled"; +- }; +- +- switch@1010000 { +- compatible = "mscc,vsc7514-switch"; +- reg = <0x1010000 0x10000>, +- <0x1030000 0x10000>, +- <0x1080000 0x100>, +- <0x10e0000 0x10000>, +- <0x11e0000 0x100>, +- <0x11f0000 0x100>, +- <0x1200000 0x100>, +- <0x1210000 0x100>, +- <0x1220000 0x100>, +- <0x1230000 0x100>, +- <0x1240000 0x100>, +- <0x1250000 0x100>, +- <0x1260000 0x100>, +- <0x1270000 0x100>, +- <0x1280000 0x100>, +- <0x1800000 0x80000>, +- <0x1880000 0x10000>, +- <0x1040000 0x10000>, +- <0x1050000 0x10000>, +- <0x1060000 0x10000>; +- reg-names = "sys", "rew", "qs", "ptp", "port0", "port1", +- "port2", "port3", "port4", "port5", "port6", +- "port7", "port8", "port9", "port10", "qsys", +- "ana", "s0", "s1", "s2"; +- interrupts = <18 21 22>; +- interrupt-names = "ptp_rdy", "xtr", "inj"; +- +- ethernet-ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port0: port@0 { +- reg = <0>; +- status = "disabled"; +- }; +- port1: port@1 { +- reg = <1>; +- status = "disabled"; +- }; +- port2: port@2 { +- reg = <2>; +- status = "disabled"; +- }; +- port3: port@3 { +- reg = <3>; +- status = "disabled"; +- }; +- port4: port@4 { +- reg = <4>; +- status = "disabled"; +- }; +- port5: port@5 { +- reg = <5>; +- status = "disabled"; +- }; +- port6: port@6 { +- reg = <6>; +- status = "disabled"; +- }; +- port7: port@7 { +- reg = <7>; +- status = "disabled"; +- }; +- port8: port@8 { +- reg = <8>; +- status = "disabled"; +- }; +- port9: port@9 { +- reg = <9>; +- status = "disabled"; +- }; +- port10: port@10 { +- reg = <10>; +- status = "disabled"; +- }; +- }; +- }; +- +- reset@1070008 { +- compatible = "mscc,ocelot-chip-reset"; +- reg = <0x1070008 0x4>; +- }; +- +- gpio: pinctrl@1070034 { +- compatible = "mscc,ocelot-pinctrl"; +- reg = <0x1070034 0x68>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&gpio 0 0 22>; +- interrupt-controller; +- interrupts = <13>; +- #interrupt-cells = <2>; +- +- i2c_pins: i2c-pins { +- pins = "GPIO_16", "GPIO_17"; +- function = "twi"; +- }; +- +- uart_pins: uart-pins { +- pins = "GPIO_6", "GPIO_7"; +- function = "uart"; +- }; +- +- uart2_pins: uart2-pins { +- pins = "GPIO_12", "GPIO_13"; +- function = "uart2"; +- }; +- +- miim1: miim1 { +- pins = "GPIO_14", "GPIO_15"; +- function = "miim"; +- }; +- +- }; +- +- mdio0: mdio@107009c { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "mscc,ocelot-miim"; +- reg = <0x107009c 0x24>, <0x10700f0 0x8>; +- interrupts = <14>; +- status = "disabled"; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- phy1: ethernet-phy@1 { +- reg = <1>; +- }; +- phy2: ethernet-phy@2 { +- reg = <2>; +- }; +- phy3: ethernet-phy@3 { +- reg = <3>; +- }; +- }; +- +- mdio1: mdio@10700c0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "mscc,ocelot-miim"; +- reg = <0x10700c0 0x24>; +- interrupts = <15>; +- pinctrl-names = "default"; +- pinctrl-0 = <&miim1>; +- status = "disabled"; +- }; +- +- hsio: syscon@10d0000 { +- compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd"; +- reg = <0x10d0000 0x10000>; +- +- serdes: serdes { +- compatible = "mscc,vsc7514-serdes"; +- #phy-cells = <2>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/mscc/ocelot_pcb120.dts b/scripts/dtc/include-prefixes/mips/mscc/ocelot_pcb120.dts +deleted file mode 100644 +index bd240690cb37..000000000000 +--- a/scripts/dtc/include-prefixes/mips/mscc/ocelot_pcb120.dts ++++ /dev/null +@@ -1,129 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* Copyright (c) 2017 Microsemi Corporation */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include "ocelot.dtsi" +- +-/ { +- compatible = "mscc,ocelot-pcb120", "mscc,ocelot"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0e000000>; +- }; +-}; +- +-&gpio { +- phy_int_pins: phy_int_pins { +- pins = "GPIO_4"; +- function = "gpio"; +- }; +- +- phy_load_save_pins: phy_load_save_pins { +- pins = "GPIO_10"; +- function = "ptp2"; +- }; +-}; +- +-&mdio0 { +- status = "okay"; +-}; +- +-&mdio1 { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&miim1>, <&phy_int_pins>, <&phy_load_save_pins>; +- +- phy7: ethernet-phy@0 { +- reg = <0>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&gpio>; +- load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; +- }; +- phy6: ethernet-phy@1 { +- reg = <1>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&gpio>; +- load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; +- }; +- phy5: ethernet-phy@2 { +- reg = <2>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&gpio>; +- load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; +- }; +- phy4: ethernet-phy@3 { +- reg = <3>; +- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-parent = <&gpio>; +- load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&port0 { +- status = "okay"; +- phy-handle = <&phy0>; +- phy-mode = "internal"; +-}; +- +-&port1 { +- status = "okay"; +- phy-handle = <&phy1>; +- phy-mode = "internal"; +-}; +- +-&port2 { +- status = "okay"; +- phy-handle = <&phy2>; +- phy-mode = "internal"; +-}; +- +-&port3 { +- status = "okay"; +- phy-handle = <&phy3>; +- phy-mode = "internal"; +-}; +- +-&port4 { +- status = "okay"; +- phy-handle = <&phy7>; +- phy-mode = "sgmii"; +- phys = <&serdes 4 SERDES1G(2)>; +-}; +- +-&port5 { +- status = "okay"; +- phy-handle = <&phy4>; +- phy-mode = "sgmii"; +- phys = <&serdes 5 SERDES1G(5)>; +-}; +- +-&port6 { +- status = "okay"; +- phy-handle = <&phy6>; +- phy-mode = "sgmii"; +- phys = <&serdes 6 SERDES1G(3)>; +-}; +- +-&port9 { +- status = "okay"; +- phy-handle = <&phy5>; +- phy-mode = "sgmii"; +- phys = <&serdes 9 SERDES1G(4)>; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/mscc/ocelot_pcb123.dts b/scripts/dtc/include-prefixes/mips/mscc/ocelot_pcb123.dts +deleted file mode 100644 +index 0185045c7630..000000000000 +--- a/scripts/dtc/include-prefixes/mips/mscc/ocelot_pcb123.dts ++++ /dev/null +@@ -1,71 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* Copyright (c) 2017 Microsemi Corporation */ +- +-/dts-v1/; +- +-#include "ocelot.dtsi" +- +-/ { +- compatible = "mscc,ocelot-pcb123", "mscc,ocelot"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0e000000>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&spi { +- status = "okay"; +- +- flash@0 { +- compatible = "macronix,mx25l25635f", "jedec,spi-nor"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- }; +-}; +- +-&i2c { +- clock-frequency = <100000>; +- i2c-sda-hold-time-ns = <300>; +- status = "okay"; +-}; +- +-&mdio0 { +- status = "okay"; +-}; +- +-&port0 { +- status = "okay"; +- phy-handle = <&phy0>; +- phy-mode = "internal"; +-}; +- +-&port1 { +- status = "okay"; +- phy-handle = <&phy1>; +- phy-mode = "internal"; +-}; +- +-&port2 { +- status = "okay"; +- phy-handle = <&phy2>; +- phy-mode = "internal"; +-}; +- +-&port3 { +- status = "okay"; +- phy-handle = <&phy3>; +- phy-mode = "internal"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/mscc/serval.dtsi b/scripts/dtc/include-prefixes/mips/mscc/serval.dtsi +deleted file mode 100644 +index 089ce89df190..000000000000 +--- a/scripts/dtc/include-prefixes/mips/mscc/serval.dtsi ++++ /dev/null +@@ -1,153 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Microsemi Corporation +- */ +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mscc,serval"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "mips,mips24KEc"; +- device_type = "cpu"; +- clocks = <&cpu_clk>; +- reg = <0>; +- }; +- }; +- +- aliases { +- serial0 = &uart0; +- gpio0 = &gpio; +- }; +- +- cpuintc: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- cpu_clk: cpu-clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <416666666>; +- }; +- +- ahb_clk: ahb-clk { +- compatible = "fixed-factor-clock"; +- #clock-cells = <0>; +- clocks = <&cpu_clk>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- ahb: ahb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- interrupt-parent = <&intc>; +- +- cpu_ctrl: syscon@70000000 { +- compatible = "mscc,ocelot-cpu-syscon", "syscon"; +- reg = <0x70000000 0x2c>; +- }; +- +- intc: interrupt-controller@70000070 { +- compatible = "mscc,serval-icpu-intr"; +- reg = <0x70000070 0x70>; +- #interrupt-cells = <1>; +- interrupt-controller; +- interrupt-parent = <&cpuintc>; +- interrupts = <2>; +- }; +- +- uart0: serial@70100000 { +- pinctrl-0 = <&uart_pins>; +- pinctrl-names = "default"; +- compatible = "ns16550a"; +- reg = <0x70100000 0x20>; +- interrupts = <6>; +- clocks = <&ahb_clk>; +- reg-io-width = <4>; +- reg-shift = <2>; +- +- status = "disabled"; +- }; +- +- uart2: serial@70100800 { +- pinctrl-0 = <&uart2_pins>; +- pinctrl-names = "default"; +- compatible = "ns16550a"; +- reg = <0x70100800 0x20>; +- interrupts = <7>; +- clocks = <&ahb_clk>; +- reg-io-width = <4>; +- reg-shift = <2>; +- +- status = "disabled"; +- }; +- +- gpio: pinctrl@71070034 { +- compatible = "mscc,serval-pinctrl"; +- reg = <0x71070034 0x28>; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&gpio 0 0 22>; +- +- sgpio_pins: sgpio-pins { +- pins = "GPIO_0", "GPIO_2", "GPIO_3", "GPIO_1"; +- function = "sg0"; +- }; +- +- i2c_pins: i2c-pins { +- pins = "GPIO_6", "GPIO_7"; +- function = "twi"; +- }; +- +- uart_pins: uart-pins { +- pins = "GPIO_26", "GPIO_27"; +- function = "uart"; +- }; +- +- uart2_pins: uart2-pins { +- pins = "GPIO_13", "GPIO_14"; +- function = "uart2"; +- }; +- +- cs1_pins: cs1-pins { +- pins = "GPIO_8"; +- function = "si"; +- }; +- +- irqext0_pins: irqext0-pins { +- pins = "GPIO_28"; +- function = "irq0"; +- }; +- +- irqext1_pins: irqext1-pins { +- pins = "GPIO_29"; +- function = "irq1"; +- }; +- }; +- +- i2c0: i2c@70100400 { +- compatible = "mscc,ocelot-i2c", "snps,designware-i2c"; +- status = "disabled"; +- pinctrl-0 = <&i2c_pins>; +- pinctrl-names = "default"; +- reg = <0x70100400 0x100>, <0x70000190 0x8>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <8>; +- clock-frequency = <100000>; +- clocks = <&ahb_clk>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/mscc/serval_common.dtsi b/scripts/dtc/include-prefixes/mips/mscc/serval_common.dtsi +deleted file mode 100644 +index 5b404836db5e..000000000000 +--- a/scripts/dtc/include-prefixes/mips/mscc/serval_common.dtsi ++++ /dev/null +@@ -1,127 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 Microsemi Corporation +- */ +- +-#include "serval.dtsi" +- +-/ { +- aliases { +- serial0 = &uart0; +- i2c104 = &i2c104; +- i2c105 = &i2c105; +- i2c106 = &i2c106; +- i2c107 = &i2c107; +- i2c108 = &i2c108; +- i2c109 = &i2c109; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- i2c0_imux: i2c0-imux{ +- compatible = "i2c-mux-pinctrl"; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-parent = <&i2c0>; +- pinctrl-names = +- "i2c104", "i2c105", "i2c106", "i2c107", +- "i2c108", "i2c109", "idle"; +- pinctrl-0 = <&i2cmux_0>; +- pinctrl-1 = <&i2cmux_1>; +- pinctrl-2 = <&i2cmux_2>; +- pinctrl-3 = <&i2cmux_3>; +- pinctrl-4 = <&i2cmux_4>; +- pinctrl-5 = <&i2cmux_5>; +- pinctrl-6 = <&i2cmux_pins_i>; +- i2c104: i2c_sfp0@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c105: i2c_sfp1@1 { +- reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c106: i2c_sfp2@2 { +- reg = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c107: i2c_sfp3@3 { +- reg = <3>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c108: i2c_sfp4@4 { +- reg = <4>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- i2c109: i2c_sfp5@5 { +- reg = <5>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +- +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&gpio { +- i2c_pins: i2c-pins { +- pins = "GPIO_7"; /* No "default" scl for i2c0 */ +- function = "twi"; +- }; +- i2cmux_pins_i: i2cmux-pins-i { +- pins = "GPIO_11", "GPIO_12", "GPIO_18", "GPIO_19", +- "GPIO_20", "GPIO_21"; +- function = "twi_scl_m"; +- output-low; +- }; +- i2cmux_0: i2cmux-0 { +- pins = "GPIO_11"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_1: i2cmux-1 { +- pins = "GPIO_12"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_2: i2cmux-2 { +- pins = "GPIO_18"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_3: i2cmux-3 { +- pins = "GPIO_19"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_4: i2cmux-4 { +- pins = "GPIO_20"; +- function = "twi_scl_m"; +- output-high; +- }; +- i2cmux_5: i2cmux-5 { +- pins = "GPIO_21"; +- function = "twi_scl_m"; +- output-high; +- }; +-}; +- +-&i2c0 { +- status = "okay"; +- i2c-sda-hold-time-ns = <300>; +-}; +- +diff --git a/scripts/dtc/include-prefixes/mips/mscc/serval_pcb105.dts b/scripts/dtc/include-prefixes/mips/mscc/serval_pcb105.dts +deleted file mode 100644 +index a1b0012b79d3..000000000000 +--- a/scripts/dtc/include-prefixes/mips/mscc/serval_pcb105.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Microsemi Corporation +- */ +- +-/dts-v1/; +-#include "serval_common.dtsi" +- +-/ { +- model = "Serval PCB105 Reference Board"; +- compatible = "mscc,serval-pcb105", "mscc,serval"; +- +- aliases { +- }; +- +-}; +- +diff --git a/scripts/dtc/include-prefixes/mips/mscc/serval_pcb106.dts b/scripts/dtc/include-prefixes/mips/mscc/serval_pcb106.dts +deleted file mode 100644 +index 237be7c8da57..000000000000 +--- a/scripts/dtc/include-prefixes/mips/mscc/serval_pcb106.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2018 Microsemi Corporation +- */ +- +-/dts-v1/; +-#include "serval_common.dtsi" +- +-/ { +- model = "Serval PCB106 Reference Board"; +- compatible = "mscc,serval-pcb106", "mscc,serval"; +- +- aliases { +- }; +- +-}; +- +diff --git a/scripts/dtc/include-prefixes/mips/mti/Makefile b/scripts/dtc/include-prefixes/mips/mti/Makefile +deleted file mode 100644 +index b5f7426998b1..000000000000 +--- a/scripts/dtc/include-prefixes/mips/mti/Makefile ++++ /dev/null +@@ -1,5 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_MIPS_MALTA) += malta.dtb +-dtb-$(CONFIG_LEGACY_BOARD_SEAD3) += sead3.dtb +- +-obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) +diff --git a/scripts/dtc/include-prefixes/mips/mti/malta.dts b/scripts/dtc/include-prefixes/mips/mti/malta.dts +deleted file mode 100644 +index f03279b1cde7..000000000000 +--- a/scripts/dtc/include-prefixes/mips/mti/malta.dts ++++ /dev/null +@@ -1,117 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +- +-/memreserve/ 0x00000000 0x00001000; /* YAMON exception vectors */ +-/memreserve/ 0x00001000 0x000ef000; /* YAMON */ +-/memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */ +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mti,malta"; +- +- cpu_intc: interrupt-controller { +- compatible = "mti,cpu-interrupt-controller"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- gic: interrupt-controller@1bdc0000 { +- compatible = "mti,gic"; +- reg = <0x1bdc0000 0x20000>; +- +- interrupt-controller; +- #interrupt-cells = <3>; +- +- /* +- * Declare the interrupt-parent even though the mti,gic +- * binding doesn't require it, such that the kernel can +- * figure out that cpu_intc is the root interrupt +- * controller & should be probed first. +- */ +- interrupt-parent = <&cpu_intc>; +- +- timer { +- compatible = "mti,gic-timer"; +- interrupts = ; +- }; +- }; +- +- i8259: interrupt-controller@20 { +- compatible = "intel,i8259"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- +- flash@1e000000 { +- compatible = "intel,dt28f160", "cfi-flash"; +- reg = <0x1e000000 0x400000>; +- bank-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- yamon@0 { +- label = "YAMON"; +- reg = <0x0 0x100000>; +- read-only; +- }; +- +- user-fs@100000 { +- label = "User FS"; +- reg = <0x100000 0x2e0000>; +- }; +- +- board-config@3e0000 { +- label = "Board Config"; +- reg = <0x3e0000 0x20000>; +- read-only; +- }; +- }; +- }; +- +- fpga_regs: system-controller@1f000000 { +- compatible = "mti,malta-fpga", "syscon", "simple-mfd"; +- reg = <0x1f000000 0x1000>; +- native-endian; +- +- lcd@410 { +- compatible = "mti,malta-lcd"; +- offset = <0x410>; +- }; +- +- reboot { +- compatible = "syscon-reboot"; +- regmap = <&fpga_regs>; +- offset = <0x500>; +- mask = <0x42>; +- }; +- }; +- +- isa { +- compatible = "isa"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <1 0 0 0x1000>; +- +- rtc@70 { +- compatible = "motorola,mc146818"; +- reg = <1 0x70 0x8>; +- +- interrupt-parent = <&i8259>; +- interrupts = <8>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/mti/sead3.dts b/scripts/dtc/include-prefixes/mips/mti/sead3.dts +deleted file mode 100644 +index 046c97a29710..000000000000 +--- a/scripts/dtc/include-prefixes/mips/mti/sead3.dts ++++ /dev/null +@@ -1,259 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-/memreserve/ 0x00000000 0x00001000; // reserved +-/memreserve/ 0x00001000 0x000ef000; // ROM data +-/memreserve/ 0x000f0000 0x004cc000; // reserved +- +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mti,sead-3"; +- model = "MIPS SEAD-3"; +- +- chosen { +- stdout-path = "serial1:115200"; +- }; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- cpus { +- cpu@0 { +- compatible = "mti,mips14KEc", "mti,mips14Kc"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x08000000>; +- }; +- +- cpu_intc: interrupt-controller { +- compatible = "mti,cpu-interrupt-controller"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- gic: interrupt-controller@1b1c0000 { +- compatible = "mti,gic"; +- reg = <0x1b1c0000 0x20000>; +- +- interrupt-controller; +- #interrupt-cells = <3>; +- +- /* +- * Declare the interrupt-parent even though the mti,gic +- * binding doesn't require it, such that the kernel can +- * figure out that cpu_intc is the root interrupt +- * controller & should be probed first. +- */ +- interrupt-parent = <&cpu_intc>; +- }; +- +- usb@1b200000 { +- compatible = "generic-ehci"; +- reg = <0x1b200000 0x1000>; +- +- interrupt-parent = <&gic>; +- interrupts = ; /* GIC 0 or CPU 6 */ +- +- has-transaction-translator; +- }; +- +- flash@1c000000 { +- compatible = "intel,28f128j3", "cfi-flash"; +- reg = <0x1c000000 0x2000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- bank-width = <4>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- user-fs@0 { +- label = "User FS"; +- reg = <0x0 0x1fc0000>; +- }; +- +- board-config@3e0000 { +- label = "Board Config"; +- reg = <0x1fc0000 0x40000>; +- }; +- }; +- }; +- +- fpga_regs: system-controller@1f000000 { +- compatible = "mti,sead3-fpga", "syscon", "simple-mfd"; +- reg = <0x1f000000 0x200>; +- +- reboot { +- compatible = "syscon-reboot"; +- regmap = <&fpga_regs>; +- offset = <0x50>; +- mask = <0x4d>; +- }; +- +- poweroff { +- compatible = "restart-poweroff"; +- }; +- }; +- +- system-controller@1f000200 { +- compatible = "mti,sead3-cpld", "syscon", "simple-mfd"; +- reg = <0x1f000200 0x300>; +- +- led@10.0 { +- compatible = "register-bit-led"; +- offset = <0x10>; +- mask = <0x1>; +- label = "pled0"; +- }; +- led@10.1 { +- compatible = "register-bit-led"; +- offset = <0x10>; +- mask = <0x2>; +- label = "pled1"; +- }; +- led@10.2 { +- compatible = "register-bit-led"; +- offset = <0x10>; +- mask = <0x4>; +- label = "pled2"; +- }; +- led@10.3 { +- compatible = "register-bit-led"; +- offset = <0x10>; +- mask = <0x8>; +- label = "pled3"; +- }; +- led@10.4 { +- compatible = "register-bit-led"; +- offset = <0x10>; +- mask = <0x10>; +- label = "pled4"; +- }; +- led@10.5 { +- compatible = "register-bit-led"; +- offset = <0x10>; +- mask = <0x20>; +- label = "pled5"; +- }; +- led@10.6 { +- compatible = "register-bit-led"; +- offset = <0x10>; +- mask = <0x40>; +- label = "pled6"; +- }; +- led@10.7 { +- compatible = "register-bit-led"; +- offset = <0x10>; +- mask = <0x80>; +- label = "pled7"; +- }; +- +- led@18.0 { +- compatible = "register-bit-led"; +- offset = <0x18>; +- mask = <0x1>; +- label = "fled0"; +- }; +- led@18.1 { +- compatible = "register-bit-led"; +- offset = <0x18>; +- mask = <0x2>; +- label = "fled1"; +- }; +- led@18.2 { +- compatible = "register-bit-led"; +- offset = <0x18>; +- mask = <0x4>; +- label = "fled2"; +- }; +- led@18.3 { +- compatible = "register-bit-led"; +- offset = <0x18>; +- mask = <0x8>; +- label = "fled3"; +- }; +- led@18.4 { +- compatible = "register-bit-led"; +- offset = <0x18>; +- mask = <0x10>; +- label = "fled4"; +- }; +- led@18.5 { +- compatible = "register-bit-led"; +- offset = <0x18>; +- mask = <0x20>; +- label = "fled5"; +- }; +- led@18.6 { +- compatible = "register-bit-led"; +- offset = <0x18>; +- mask = <0x40>; +- label = "fled6"; +- }; +- led@18.7 { +- compatible = "register-bit-led"; +- offset = <0x18>; +- mask = <0x80>; +- label = "fled7"; +- }; +- +- lcd@200 { +- compatible = "mti,sead3-lcd"; +- offset = <0x200>; +- }; +- }; +- +- /* UART connected to FTDI & miniUSB socket */ +- uart0: uart@1f000900 { +- compatible = "ns16550a"; +- reg = <0x1f000900 0x20>; +- reg-io-width = <4>; +- reg-shift = <2>; +- +- clock-frequency = <14745600>; +- +- interrupt-parent = <&gic>; +- interrupts = ; /* GIC 3 or CPU 4 */ +- +- no-loopback-test; +- }; +- +- /* UART connected to RS232 socket */ +- uart1: uart@1f000800 { +- compatible = "ns16550a"; +- reg = <0x1f000800 0x20>; +- reg-io-width = <4>; +- reg-shift = <2>; +- +- clock-frequency = <14745600>; +- +- interrupt-parent = <&gic>; +- interrupts = ; /* GIC 2 or CPU 4 */ +- +- no-loopback-test; +- }; +- +- ethernet@1f010000 { +- compatible = "smsc,lan9115"; +- reg = <0x1f010000 0x10000>; +- reg-io-width = <4>; +- +- interrupt-parent = <&gic>; +- interrupts = ; /* GIC 0 or CPU 6 */ +- +- phy-mode = "mii"; +- smsc,irq-push-pull; +- smsc,save-mac-address; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/netlogic/Makefile b/scripts/dtc/include-prefixes/mips/netlogic/Makefile +deleted file mode 100644 +index 45af4224494f..000000000000 +--- a/scripts/dtc/include-prefixes/mips/netlogic/Makefile ++++ /dev/null +@@ -1,8 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_DT_XLP_EVP) += xlp_evp.dtb +-dtb-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb +-dtb-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb +-dtb-$(CONFIG_DT_XLP_GVP) += xlp_gvp.dtb +-dtb-$(CONFIG_DT_XLP_RVP) += xlp_rvp.dtb +- +-obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) +diff --git a/scripts/dtc/include-prefixes/mips/netlogic/xlp_evp.dts b/scripts/dtc/include-prefixes/mips/netlogic/xlp_evp.dts +deleted file mode 100644 +index e63e55926e04..000000000000 +--- a/scripts/dtc/include-prefixes/mips/netlogic/xlp_evp.dts ++++ /dev/null +@@ -1,131 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * XLP8XX Device Tree Source for EVP boards +- */ +- +-/dts-v1/; +-/ { +- model = "netlogic,XLP-EVP"; +- compatible = "netlogic,xlp"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- soc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG +- 1 0 0 0x16000000 0x02000000>; // GBU chipselects +- +- serial0: serial@30000 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0 0x30100 0xa00>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <133333333>; +- interrupt-parent = <&pic>; +- interrupts = <17>; +- }; +- serial1: serial@31000 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0 0x31100 0xa00>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <133333333>; +- interrupt-parent = <&pic>; +- interrupts = <18>; +- }; +- i2c0: ocores@32000 { +- compatible = "opencores,i2c-ocores"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x32100 0xa00>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <32000000>; +- interrupt-parent = <&pic>; +- interrupts = <30>; +- }; +- i2c1: ocores@33000 { +- compatible = "opencores,i2c-ocores"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x33100 0xa00>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <32000000>; +- interrupt-parent = <&pic>; +- interrupts = <31>; +- +- rtc@68 { +- compatible = "dallas,ds1374"; +- reg = <0x68>; +- }; +- +- dtt@4c { +- compatible = "national,lm90"; +- reg = <0x4c>; +- }; +- }; +- pic: pic@4000 { +- compatible = "netlogic,xlp-pic"; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0 0x4000 0x200>; +- interrupt-controller; +- }; +- +- nor_flash@1,0 { +- compatible = "cfi-flash"; +- #address-cells = <1>; +- #size-cells = <1>; +- bank-width = <2>; +- reg = <1 0 0x1000000>; +- +- partition@0 { +- label = "x-loader"; +- reg = <0x0 0x100000>; /* 1M */ +- read-only; +- }; +- +- partition@100000 { +- label = "u-boot"; +- reg = <0x100000 0x100000>; /* 1M */ +- }; +- +- partition@200000 { +- label = "kernel"; +- reg = <0x200000 0x500000>; /* 5M */ +- }; +- +- partition@700000 { +- label = "rootfs"; +- reg = <0x700000 0x800000>; /* 8M */ +- }; +- +- partition@f00000 { +- label = "env"; +- reg = <0xf00000 0x100000>; /* 1M */ +- read-only; +- }; +- }; +- +- gpio: xlp_gpio@34100 { +- compatible = "netlogic,xlp832-gpio"; +- reg = <0 0x34100 0x1000>; +- #gpio-cells = <2>; +- gpio-controller; +- +- #interrupt-cells = <2>; +- interrupt-parent = <&pic>; +- interrupts = <39>; +- interrupt-controller; +- }; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/netlogic/xlp_fvp.dts b/scripts/dtc/include-prefixes/mips/netlogic/xlp_fvp.dts +deleted file mode 100644 +index d05abf13fb7d..000000000000 +--- a/scripts/dtc/include-prefixes/mips/netlogic/xlp_fvp.dts ++++ /dev/null +@@ -1,131 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * XLP2XX Device Tree Source for FVP boards +- */ +- +-/dts-v1/; +-/ { +- model = "netlogic,XLP-FVP"; +- compatible = "netlogic,xlp"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- soc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG +- 1 0 0 0x16000000 0x02000000>; // GBU chipselects +- +- serial0: serial@30000 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0 0x30100 0xa00>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <133333333>; +- interrupt-parent = <&pic>; +- interrupts = <17>; +- }; +- serial1: serial@31000 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0 0x31100 0xa00>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <133333333>; +- interrupt-parent = <&pic>; +- interrupts = <18>; +- }; +- i2c0: ocores@37100 { +- compatible = "opencores,i2c-ocores"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x37100 0x20>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <32000000>; +- interrupt-parent = <&pic>; +- interrupts = <30>; +- }; +- i2c1: ocores@37120 { +- compatible = "opencores,i2c-ocores"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x37120 0x20>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <32000000>; +- interrupt-parent = <&pic>; +- interrupts = <31>; +- +- rtc@68 { +- compatible = "dallas,ds1374"; +- reg = <0x68>; +- }; +- +- dtt@4c { +- compatible = "national,lm90"; +- reg = <0x4c>; +- }; +- }; +- pic: pic@4000 { +- compatible = "netlogic,xlp-pic"; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0 0x4000 0x200>; +- interrupt-controller; +- }; +- +- nor_flash@1,0 { +- compatible = "cfi-flash"; +- #address-cells = <1>; +- #size-cells = <1>; +- bank-width = <2>; +- reg = <1 0 0x1000000>; +- +- partition@0 { +- label = "x-loader"; +- reg = <0x0 0x100000>; /* 1M */ +- read-only; +- }; +- +- partition@100000 { +- label = "u-boot"; +- reg = <0x100000 0x100000>; /* 1M */ +- }; +- +- partition@200000 { +- label = "kernel"; +- reg = <0x200000 0x500000>; /* 5M */ +- }; +- +- partition@700000 { +- label = "rootfs"; +- reg = <0x700000 0x800000>; /* 8M */ +- }; +- +- partition@f00000 { +- label = "env"; +- reg = <0xf00000 0x100000>; /* 1M */ +- read-only; +- }; +- }; +- +- gpio: xlp_gpio@34100 { +- compatible = "netlogic,xlp208-gpio"; +- reg = <0 0x34100 0x1000>; +- #gpio-cells = <2>; +- gpio-controller; +- +- #interrupt-cells = <2>; +- interrupt-parent = <&pic>; +- interrupts = <39>; +- interrupt-controller; +- }; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/netlogic/xlp_gvp.dts b/scripts/dtc/include-prefixes/mips/netlogic/xlp_gvp.dts +deleted file mode 100644 +index d47de4851786..000000000000 +--- a/scripts/dtc/include-prefixes/mips/netlogic/xlp_gvp.dts ++++ /dev/null +@@ -1,89 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * XLP9XX Device Tree Source for GVP boards +- */ +- +-/dts-v1/; +-/ { +- model = "netlogic,XLP-GVP"; +- compatible = "netlogic,xlp"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- soc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG +- 1 0 0 0x16000000 0x02000000>; // GBU chipselects +- +- serial0: serial@30000 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0 0x112100 0xa00>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <125000000>; +- interrupt-parent = <&pic>; +- interrupts = <17>; +- }; +- pic: pic@110000 { +- compatible = "netlogic,xlp-pic"; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0 0x110000 0x200>; +- interrupt-controller; +- }; +- +- nor_flash@1,0 { +- compatible = "cfi-flash"; +- #address-cells = <1>; +- #size-cells = <1>; +- bank-width = <2>; +- reg = <1 0 0x1000000>; +- +- partition@0 { +- label = "x-loader"; +- reg = <0x0 0x100000>; /* 1M */ +- read-only; +- }; +- +- partition@100000 { +- label = "u-boot"; +- reg = <0x100000 0x100000>; /* 1M */ +- }; +- +- partition@200000 { +- label = "kernel"; +- reg = <0x200000 0x500000>; /* 5M */ +- }; +- +- partition@700000 { +- label = "rootfs"; +- reg = <0x700000 0x800000>; /* 8M */ +- }; +- +- partition@f00000 { +- label = "env"; +- reg = <0xf00000 0x100000>; /* 1M */ +- read-only; +- }; +- }; +- +- gpio: xlp_gpio@114100 { +- compatible = "netlogic,xlp980-gpio"; +- reg = <0 0x114100 0x1000>; +- #gpio-cells = <2>; +- gpio-controller; +- +- #interrupt-cells = <2>; +- interrupt-parent = <&pic>; +- interrupts = <39>; +- interrupt-controller; +- }; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/netlogic/xlp_rvp.dts b/scripts/dtc/include-prefixes/mips/netlogic/xlp_rvp.dts +deleted file mode 100644 +index aa0faee194ec..000000000000 +--- a/scripts/dtc/include-prefixes/mips/netlogic/xlp_rvp.dts ++++ /dev/null +@@ -1,89 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * XLP5XX Device Tree Source for RVP boards +- */ +- +-/dts-v1/; +-/ { +- model = "netlogic,XLP-RVP"; +- compatible = "netlogic,xlp"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- soc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG +- 1 0 0 0x16000000 0x02000000>; // GBU chipselects +- +- serial0: serial@30000 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0 0x112100 0xa00>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <125000000>; +- interrupt-parent = <&pic>; +- interrupts = <17>; +- }; +- pic: pic@110000 { +- compatible = "netlogic,xlp-pic"; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0 0x110000 0x200>; +- interrupt-controller; +- }; +- +- nor_flash@1,0 { +- compatible = "cfi-flash"; +- #address-cells = <1>; +- #size-cells = <1>; +- bank-width = <2>; +- reg = <1 0 0x1000000>; +- +- partition@0 { +- label = "x-loader"; +- reg = <0x0 0x100000>; /* 1M */ +- read-only; +- }; +- +- partition@100000 { +- label = "u-boot"; +- reg = <0x100000 0x100000>; /* 1M */ +- }; +- +- partition@200000 { +- label = "kernel"; +- reg = <0x200000 0x500000>; /* 5M */ +- }; +- +- partition@700000 { +- label = "rootfs"; +- reg = <0x700000 0x800000>; /* 8M */ +- }; +- +- partition@f00000 { +- label = "env"; +- reg = <0xf00000 0x100000>; /* 1M */ +- read-only; +- }; +- }; +- +- gpio: xlp_gpio@114100 { +- compatible = "netlogic,xlp532-gpio"; +- reg = <0 0x114100 0x1000>; +- #gpio-cells = <2>; +- gpio-controller; +- +- #interrupt-cells = <2>; +- interrupt-parent = <&pic>; +- interrupts = <39>; +- interrupt-controller; +- }; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/netlogic/xlp_svp.dts b/scripts/dtc/include-prefixes/mips/netlogic/xlp_svp.dts +deleted file mode 100644 +index 3bb0b2e08e4a..000000000000 +--- a/scripts/dtc/include-prefixes/mips/netlogic/xlp_svp.dts ++++ /dev/null +@@ -1,131 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * XLP3XX Device Tree Source for SVP boards +- */ +- +-/dts-v1/; +-/ { +- model = "netlogic,XLP-SVP"; +- compatible = "netlogic,xlp"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- soc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG +- 1 0 0 0x16000000 0x02000000>; // GBU chipselects +- +- serial0: serial@30000 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0 0x30100 0xa00>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <133333333>; +- interrupt-parent = <&pic>; +- interrupts = <17>; +- }; +- serial1: serial@31000 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0 0x31100 0xa00>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <133333333>; +- interrupt-parent = <&pic>; +- interrupts = <18>; +- }; +- i2c0: ocores@32000 { +- compatible = "opencores,i2c-ocores"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x32100 0xa00>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <32000000>; +- interrupt-parent = <&pic>; +- interrupts = <30>; +- }; +- i2c1: ocores@33000 { +- compatible = "opencores,i2c-ocores"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0 0x33100 0xa00>; +- reg-shift = <2>; +- reg-io-width = <4>; +- clock-frequency = <32000000>; +- interrupt-parent = <&pic>; +- interrupts = <31>; +- +- rtc@68 { +- compatible = "dallas,ds1374"; +- reg = <0x68>; +- }; +- +- dtt@4c { +- compatible = "national,lm90"; +- reg = <0x4c>; +- }; +- }; +- pic: pic@4000 { +- compatible = "netlogic,xlp-pic"; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0 0x4000 0x200>; +- interrupt-controller; +- }; +- +- nor_flash@1,0 { +- compatible = "cfi-flash"; +- #address-cells = <1>; +- #size-cells = <1>; +- bank-width = <2>; +- reg = <1 0 0x1000000>; +- +- partition@0 { +- label = "x-loader"; +- reg = <0x0 0x100000>; /* 1M */ +- read-only; +- }; +- +- partition@100000 { +- label = "u-boot"; +- reg = <0x100000 0x100000>; /* 1M */ +- }; +- +- partition@200000 { +- label = "kernel"; +- reg = <0x200000 0x500000>; /* 5M */ +- }; +- +- partition@700000 { +- label = "rootfs"; +- reg = <0x700000 0x800000>; /* 8M */ +- }; +- +- partition@f00000 { +- label = "env"; +- reg = <0xf00000 0x100000>; /* 1M */ +- read-only; +- }; +- }; +- +- gpio: xlp_gpio@34100 { +- compatible = "netlogic,xlp316-gpio"; +- reg = <0 0x34100 0x1000>; +- #gpio-cells = <2>; +- gpio-controller; +- +- #interrupt-cells = <2>; +- interrupt-parent = <&pic>; +- interrupts = <39>; +- interrupt-controller; +- }; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ni/169445.dts b/scripts/dtc/include-prefixes/mips/ni/169445.dts +deleted file mode 100644 +index 5389ef46c480..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ni/169445.dts ++++ /dev/null +@@ -1,100 +0,0 @@ +-/dts-v1/; +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ni,169445"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- device_type = "cpu"; +- compatible = "mti,mips14KEc"; +- clocks = <&baseclk>; +- reg = <0>; +- }; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x10000000>; +- }; +- +- baseclk: baseclock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- }; +- +- cpu_intc: interrupt-controller { +- #address-cells = <0>; +- compatible = "mti,cpu-interrupt-controller"; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- ahb@1f300000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x1f300000 0x80FFF>; +- +- gpio1: gpio@10 { +- compatible = "ni,169445-nand-gpio"; +- reg = <0x10 0x4>; +- reg-names = "dat"; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpio2: gpio@14 { +- compatible = "ni,169445-nand-gpio"; +- reg = <0x14 0x4>; +- reg-names = "dat"; +- gpio-controller; +- #gpio-cells = <2>; +- no-output; +- }; +- +- nand@0 { +- compatible = "gpio-control-nand"; +- nand-on-flash-bbt; +- nand-ecc-mode = "soft_bch"; +- nand-ecc-step-size = <512>; +- nand-ecc-strength = <4>; +- reg = <0x0 4>; +- gpios = <&gpio2 0 0>, /* rdy */ +- <&gpio1 1 0>, /* nce */ +- <&gpio1 2 0>, /* ale */ +- <&gpio1 3 0>, /* cle */ +- <&gpio1 4 0>; /* nwp */ +- }; +- +- serial@80000 { +- compatible = "ns16550a"; +- reg = <0x80000 0x1000>; +- interrupt-parent = <&cpu_intc>; +- interrupts = <6>; +- clocks = <&baseclk>; +- reg-shift = <0>; +- }; +- +- ethernet@40000 { +- compatible = "snps,dwmac-4.10a"; +- interrupt-parent = <&cpu_intc>; +- interrupts = <5>; +- interrupt-names = "macirq"; +- reg = <0x40000 0x2000>; +- clock-names = "stmmaceth", "pclk"; +- clocks = <&baseclk>, <&baseclk>; +- +- phy-mode = "rgmii"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ni/Makefile b/scripts/dtc/include-prefixes/mips/ni/Makefile +deleted file mode 100644 +index 93867e1a5279..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ni/Makefile ++++ /dev/null +@@ -1,2 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0-only +-dtb-$(CONFIG_FIT_IMAGE_FDT_NI169445) += 169445.dtb +diff --git a/scripts/dtc/include-prefixes/mips/pic32/Makefile b/scripts/dtc/include-prefixes/mips/pic32/Makefile +deleted file mode 100644 +index fb57f36324db..000000000000 +--- a/scripts/dtc/include-prefixes/mips/pic32/Makefile ++++ /dev/null +@@ -1,7 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_DTB_PIC32_MZDA_SK) += pic32mzda_sk.dtb +- +-dtb-$(CONFIG_DTB_PIC32_NONE) += \ +- pic32mzda_sk.dtb +- +-obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) +diff --git a/scripts/dtc/include-prefixes/mips/pic32/pic32mzda.dtsi b/scripts/dtc/include-prefixes/mips/pic32/pic32mzda.dtsi +deleted file mode 100644 +index f1e3dad6bead..000000000000 +--- a/scripts/dtc/include-prefixes/mips/pic32/pic32mzda.dtsi ++++ /dev/null +@@ -1,298 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. +- */ +-#include +-#include +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&evic>; +- +- aliases { +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- gpio2 = &gpio2; +- gpio3 = &gpio3; +- gpio4 = &gpio4; +- gpio5 = &gpio5; +- gpio6 = &gpio6; +- gpio7 = &gpio7; +- gpio8 = &gpio8; +- gpio9 = &gpio9; +- serial0 = &uart1; +- serial1 = &uart2; +- serial2 = &uart3; +- serial3 = &uart4; +- serial4 = &uart5; +- serial5 = &uart6; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "mti,mips14KEc"; +- device_type = "cpu"; +- }; +- }; +- +- soc { +- compatible = "microchip,pic32mzda-infra"; +- interrupts = <0 IRQ_TYPE_EDGE_RISING>; +- }; +- +- /* external clock input on TxCLKI pin */ +- txcki: txcki_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <4000000>; +- status = "disabled"; +- }; +- +- /* external input on REFCLKIx pin */ +- refix: refix_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- status = "disabled"; +- }; +- +- rootclk: clock-controller@1f801200 { +- compatible = "microchip,pic32mzda-clk"; +- reg = <0x1f801200 0x200>; +- #clock-cells = <1>; +- microchip,pic32mzda-sosc; +- }; +- +- evic: interrupt-controller@1f810000 { +- compatible = "microchip,pic32mzda-evic"; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x1f810000 0x1000>; +- microchip,external-irqs = <3 8 13 18 23>; +- }; +- +- pic32_pinctrl: pinctrl@1f801400{ +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "microchip,pic32mzda-pinctrl"; +- reg = <0x1f801400 0x400>; +- clocks = <&rootclk PB1CLK>; +- }; +- +- /* PORTA */ +- gpio0: gpio0@1f860000 { +- compatible = "microchip,pic32mzda-gpio"; +- reg = <0x1f860000 0x100>; +- interrupts = <118 IRQ_TYPE_LEVEL_HIGH>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&rootclk PB4CLK>; +- microchip,gpio-bank = <0>; +- gpio-ranges = <&pic32_pinctrl 0 0 16>; +- }; +- +- /* PORTB */ +- gpio1: gpio1@1f860100 { +- compatible = "microchip,pic32mzda-gpio"; +- reg = <0x1f860100 0x100>; +- interrupts = <119 IRQ_TYPE_LEVEL_HIGH>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&rootclk PB4CLK>; +- microchip,gpio-bank = <1>; +- gpio-ranges = <&pic32_pinctrl 0 16 16>; +- }; +- +- /* PORTC */ +- gpio2: gpio2@1f860200 { +- compatible = "microchip,pic32mzda-gpio"; +- reg = <0x1f860200 0x100>; +- interrupts = <120 IRQ_TYPE_LEVEL_HIGH>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&rootclk PB4CLK>; +- microchip,gpio-bank = <2>; +- gpio-ranges = <&pic32_pinctrl 0 32 16>; +- }; +- +- /* PORTD */ +- gpio3: gpio3@1f860300 { +- compatible = "microchip,pic32mzda-gpio"; +- reg = <0x1f860300 0x100>; +- interrupts = <121 IRQ_TYPE_LEVEL_HIGH>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&rootclk PB4CLK>; +- microchip,gpio-bank = <3>; +- gpio-ranges = <&pic32_pinctrl 0 48 16>; +- }; +- +- /* PORTE */ +- gpio4: gpio4@1f860400 { +- compatible = "microchip,pic32mzda-gpio"; +- reg = <0x1f860400 0x100>; +- interrupts = <122 IRQ_TYPE_LEVEL_HIGH>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&rootclk PB4CLK>; +- microchip,gpio-bank = <4>; +- gpio-ranges = <&pic32_pinctrl 0 64 16>; +- }; +- +- /* PORTF */ +- gpio5: gpio5@1f860500 { +- compatible = "microchip,pic32mzda-gpio"; +- reg = <0x1f860500 0x100>; +- interrupts = <123 IRQ_TYPE_LEVEL_HIGH>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&rootclk PB4CLK>; +- microchip,gpio-bank = <5>; +- gpio-ranges = <&pic32_pinctrl 0 80 16>; +- }; +- +- /* PORTG */ +- gpio6: gpio6@1f860600 { +- compatible = "microchip,pic32mzda-gpio"; +- reg = <0x1f860600 0x100>; +- interrupts = <124 IRQ_TYPE_LEVEL_HIGH>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&rootclk PB4CLK>; +- microchip,gpio-bank = <6>; +- gpio-ranges = <&pic32_pinctrl 0 96 16>; +- }; +- +- /* PORTH */ +- gpio7: gpio7@1f860700 { +- compatible = "microchip,pic32mzda-gpio"; +- reg = <0x1f860700 0x100>; +- interrupts = <125 IRQ_TYPE_LEVEL_HIGH>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&rootclk PB4CLK>; +- microchip,gpio-bank = <7>; +- gpio-ranges = <&pic32_pinctrl 0 112 16>; +- }; +- +- /* PORTI does not exist */ +- +- /* PORTJ */ +- gpio8: gpio8@1f860800 { +- compatible = "microchip,pic32mzda-gpio"; +- reg = <0x1f860800 0x100>; +- interrupts = <126 IRQ_TYPE_LEVEL_HIGH>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&rootclk PB4CLK>; +- microchip,gpio-bank = <8>; +- gpio-ranges = <&pic32_pinctrl 0 128 16>; +- }; +- +- /* PORTK */ +- gpio9: gpio9@1f860900 { +- compatible = "microchip,pic32mzda-gpio"; +- reg = <0x1f860900 0x100>; +- interrupts = <127 IRQ_TYPE_LEVEL_HIGH>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- #interrupt-cells = <2>; +- clocks = <&rootclk PB4CLK>; +- microchip,gpio-bank = <9>; +- gpio-ranges = <&pic32_pinctrl 0 144 16>; +- }; +- +- sdhci: sdhci@1f8ec000 { +- compatible = "microchip,pic32mzda-sdhci"; +- reg = <0x1f8ec000 0x100>; +- interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>; +- clock-names = "base_clk", "sys_clk"; +- bus-width = <4>; +- cap-sd-highspeed; +- status = "disabled"; +- }; +- +- uart1: serial@1f822000 { +- compatible = "microchip,pic32mzda-uart"; +- reg = <0x1f822000 0x50>; +- interrupts = <112 IRQ_TYPE_LEVEL_HIGH>, +- <113 IRQ_TYPE_LEVEL_HIGH>, +- <114 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rootclk PB2CLK>; +- status = "disabled"; +- }; +- +- uart2: serial@1f822200 { +- compatible = "microchip,pic32mzda-uart"; +- reg = <0x1f822200 0x50>; +- interrupts = <145 IRQ_TYPE_LEVEL_HIGH>, +- <146 IRQ_TYPE_LEVEL_HIGH>, +- <147 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rootclk PB2CLK>; +- status = "disabled"; +- }; +- +- uart3: serial@1f822400 { +- compatible = "microchip,pic32mzda-uart"; +- reg = <0x1f822400 0x50>; +- interrupts = <157 IRQ_TYPE_LEVEL_HIGH>, +- <158 IRQ_TYPE_LEVEL_HIGH>, +- <159 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rootclk PB2CLK>; +- status = "disabled"; +- }; +- +- uart4: serial@1f822600 { +- compatible = "microchip,pic32mzda-uart"; +- reg = <0x1f822600 0x50>; +- interrupts = <170 IRQ_TYPE_LEVEL_HIGH>, +- <171 IRQ_TYPE_LEVEL_HIGH>, +- <172 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rootclk PB2CLK>; +- status = "disabled"; +- }; +- +- uart5: serial@1f822800 { +- compatible = "microchip,pic32mzda-uart"; +- reg = <0x1f822800 0x50>; +- interrupts = <179 IRQ_TYPE_LEVEL_HIGH>, +- <180 IRQ_TYPE_LEVEL_HIGH>, +- <181 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rootclk PB2CLK>; +- status = "disabled"; +- }; +- +- uart6: serial@1f822A00 { +- compatible = "microchip,pic32mzda-uart"; +- reg = <0x1f822A00 0x50>; +- interrupts = <188 IRQ_TYPE_LEVEL_HIGH>, +- <189 IRQ_TYPE_LEVEL_HIGH>, +- <190 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rootclk PB2CLK>; +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/pic32/pic32mzda_sk.dts b/scripts/dtc/include-prefixes/mips/pic32/pic32mzda_sk.dts +deleted file mode 100644 +index d7fa5d55dbf3..000000000000 +--- a/scripts/dtc/include-prefixes/mips/pic32/pic32mzda_sk.dts ++++ /dev/null +@@ -1,148 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include +-#include +- +-#include "pic32mzda.dtsi" +- +-/ { +- compatible = "microchip,pic32mzda-sk", "microchip,pic32mzda"; +- model = "Microchip PIC32MZDA Starter Kit"; +- +- memory { +- device_type = "memory"; +- reg = <0x08000000 0x08000000>; +- }; +- +- chosen { +- bootargs = "earlyprintk=ttyPIC1,115200n8r console=ttyPIC1,115200n8"; +- }; +- +- leds0 { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&user_leds_s0>; +- +- led@1 { +- label = "pic32mzda_sk:red:led1"; +- gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led@2 { +- label = "pic32mzda_sk:yellow:led2"; +- gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- }; +- +- led@3 { +- label = "pic32mzda_sk:green:led3"; +- gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- keys0 { +- compatible = "gpio-keys"; +- pinctrl-0 = <&user_buttons_s0>; +- pinctrl-names = "default"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- button@sw1 { +- label = "ESC"; +- linux,code = <1>; +- gpios = <&gpio1 12 0>; +- }; +- +- button@sw2 { +- label = "Home"; +- linux,code = <102>; +- gpios = <&gpio1 13 0>; +- }; +- +- button@sw3 { +- label = "Menu"; +- linux,code = <139>; +- gpios = <&gpio1 14 0>; +- }; +- }; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart4>; +- status = "okay"; +-}; +- +-&sdhci { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sdhc1>; +- status = "okay"; +- assigned-clocks = <&rootclk REF2CLK>, <&rootclk REF4CLK>, +- <&rootclk REF5CLK>; +- assigned-clock-rates = <50000000>, <25000000>, <40000000>; +-}; +- +-&pic32_pinctrl { +- +- pinctrl_sdhc1: sdhc1_pins0 { +- pins = "A6", "D4", "G13", "G12", "G14", "A7", "A0"; +- microchip,digital; +- }; +- +- user_leds_s0: user_leds_s0 { +- pins = "H0", "H1", "H2"; +- output-low; +- microchip,digital; +- }; +- +- user_buttons_s0: user_buttons_s0 { +- pins = "B12", "B13", "B14"; +- microchip,digital; +- input-enable; +- bias-pull-up; +- }; +- +- pinctrl_uart2: pinctrl_uart2 { +- uart2-tx { +- pins = "G9"; +- function = "U2TX"; +- microchip,digital; +- output-high; +- }; +- uart2-rx { +- pins = "B0"; +- function = "U2RX"; +- microchip,digital; +- input-enable; +- }; +- }; +- +- pinctrl_uart4: uart4-0 { +- uart4-tx { +- pins = "C3"; +- function = "U4TX"; +- microchip,digital; +- output-high; +- }; +- uart4-rx { +- pins = "E8"; +- function = "U4RX"; +- microchip,digital; +- input-enable; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/qca/Makefile b/scripts/dtc/include-prefixes/mips/qca/Makefile +deleted file mode 100644 +index 6749f77068a8..000000000000 +--- a/scripts/dtc/include-prefixes/mips/qca/Makefile ++++ /dev/null +@@ -1,8 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-# All DTBs +-dtb-$(CONFIG_ATH79) += ar9132_tl_wr1043nd_v1.dtb +-dtb-$(CONFIG_ATH79) += ar9331_dpt_module.dtb +-dtb-$(CONFIG_ATH79) += ar9331_dragino_ms14.dtb +-dtb-$(CONFIG_ATH79) += ar9331_omega.dtb +-dtb-$(CONFIG_ATH79) += ar9331_openembed_som9331_board.dtb +-dtb-$(CONFIG_ATH79) += ar9331_tl_mr3020.dtb +diff --git a/scripts/dtc/include-prefixes/mips/qca/ar9132.dtsi b/scripts/dtc/include-prefixes/mips/qca/ar9132.dtsi +deleted file mode 100644 +index 61dcfa5b6ca7..000000000000 +--- a/scripts/dtc/include-prefixes/mips/qca/ar9132.dtsi ++++ /dev/null +@@ -1,171 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +- +-/ { +- compatible = "qca,ar9132"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "mips,mips24Kc"; +- clocks = <&pll ATH79_CLK_CPU>; +- reg = <0>; +- }; +- }; +- +- cpuintc: interrupt-controller { +- compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; +- qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, +- <&ddr_ctrl 0>, <&ddr_ctrl 1>; +- }; +- +- ahb { +- compatible = "simple-bus"; +- ranges; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- interrupt-parent = <&cpuintc>; +- +- apb { +- compatible = "simple-bus"; +- ranges; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- interrupt-parent = <&miscintc>; +- +- ddr_ctrl: memory-controller@18000000 { +- compatible = "qca,ar9132-ddr-controller", +- "qca,ar7240-ddr-controller"; +- reg = <0x18000000 0x100>; +- +- #qca,ddr-wb-channel-cells = <1>; +- }; +- +- uart: uart@18020000 { +- compatible = "ns8250"; +- reg = <0x18020000 0x20>; +- interrupts = <3>; +- +- clocks = <&pll ATH79_CLK_AHB>; +- clock-names = "uart"; +- +- reg-io-width = <4>; +- reg-shift = <2>; +- no-loopback-test; +- +- status = "disabled"; +- }; +- +- gpio: gpio@18040000 { +- compatible = "qca,ar9132-gpio", +- "qca,ar7100-gpio"; +- reg = <0x18040000 0x30>; +- interrupts = <2>; +- +- ngpios = <22>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- pll: pll-controller@18050000 { +- compatible = "qca,ar9132-pll", +- "qca,ar9130-pll"; +- reg = <0x18050000 0x20>; +- +- clock-names = "ref"; +- /* The board must provides the ref clock */ +- +- #clock-cells = <1>; +- clock-output-names = "cpu", "ddr", "ahb"; +- }; +- +- wdt: wdt@18060008 { +- compatible = "qca,ar7130-wdt"; +- reg = <0x18060008 0x8>; +- +- interrupts = <4>; +- +- clocks = <&pll ATH79_CLK_AHB>; +- clock-names = "wdt"; +- }; +- +- miscintc: interrupt-controller@18060010 { +- compatible = "qca,ar9132-misc-intc", +- "qca,ar7100-misc-intc"; +- reg = <0x18060010 0x8>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <6>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- rst: reset-controller@1806001c { +- compatible = "qca,ar9132-reset", +- "qca,ar7100-reset"; +- reg = <0x1806001c 0x4>; +- +- #reset-cells = <1>; +- }; +- }; +- +- usb: usb@1b000100 { +- compatible = "qca,ar7100-ehci", "generic-ehci"; +- reg = <0x1b000100 0x100>; +- +- interrupts = <3>; +- resets = <&rst 5>; +- +- has-transaction-translator; +- +- phy-names = "usb"; +- phys = <&usb_phy>; +- +- status = "disabled"; +- }; +- +- spi: spi@1f000000 { +- compatible = "qca,ar9132-spi", "qca,ar7100-spi"; +- reg = <0x1f000000 0x10>; +- +- clocks = <&pll ATH79_CLK_AHB>; +- clock-names = "ahb"; +- +- status = "disabled"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- usb_phy: usb-phy { +- compatible = "qca,ar7100-usb-phy"; +- +- reset-names = "phy", "suspend-override"; +- resets = <&rst 4>, <&rst 3>; +- +- #phy-cells = <0>; +- +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/qca/ar9132_tl_wr1043nd_v1.dts b/scripts/dtc/include-prefixes/mips/qca/ar9132_tl_wr1043nd_v1.dts +deleted file mode 100644 +index 7fccf6357225..000000000000 +--- a/scripts/dtc/include-prefixes/mips/qca/ar9132_tl_wr1043nd_v1.dts ++++ /dev/null +@@ -1,112 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +- +-#include "ar9132.dtsi" +- +-/ { +- compatible = "tplink,tl-wr1043nd-v1", "qca,ar9132"; +- model = "TP-Link TL-WR1043ND Version 1"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x2000000>; +- }; +- +- extosc: ref { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <40000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- button@0 { +- label = "reset"; +- linux,code = ; +- gpios = <&gpio 3 GPIO_ACTIVE_LOW>; +- debounce-interval = <60>; +- }; +- +- button@1 { +- label = "qss"; +- linux,code = ; +- gpios = <&gpio 7 GPIO_ACTIVE_LOW>; +- debounce-interval = <60>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led@0 { +- label = "tp-link:green:usb"; +- gpios = <&gpio 1 GPIO_ACTIVE_LOW>; +- }; +- +- led@1 { +- label = "tp-link:green:system"; +- gpios = <&gpio 2 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- }; +- +- led@2 { +- label = "tp-link:green:qss"; +- gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; +- }; +- +- led@3 { +- label = "tp-link:green:wlan"; +- gpios = <&gpio 9 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&uart { +- status = "okay"; +-}; +- +-&pll { +- clocks = <&extosc>; +-}; +- +-&usb { +- status = "okay"; +-}; +- +-&usb_phy { +- status = "okay"; +-}; +- +-&spi { +- status = "okay"; +- num-cs = <1>; +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "s25sl064a"; +- reg = <0>; +- spi-max-frequency = <25000000>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x000000 0x020000>; +- }; +- +- partition@1 { +- label = "firmware"; +- reg = <0x020000 0x7D0000>; +- }; +- +- partition@2 { +- label = "art"; +- reg = <0x7F0000 0x010000>; +- read-only; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/qca/ar9331.dtsi b/scripts/dtc/include-prefixes/mips/qca/ar9331.dtsi +deleted file mode 100644 +index c4102b280b47..000000000000 +--- a/scripts/dtc/include-prefixes/mips/qca/ar9331.dtsi ++++ /dev/null +@@ -1,301 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-#include +- +-/ { +- compatible = "qca,ar9331"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "mips,mips24Kc"; +- clocks = <&pll ATH79_CLK_CPU>; +- reg = <0>; +- }; +- }; +- +- cpuintc: interrupt-controller { +- compatible = "qca,ar7100-cpu-intc"; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- qca,ddr-wb-channel-interrupts = <2>, <3>; +- qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>; +- }; +- +- ref: ref { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- }; +- +- ahb { +- compatible = "simple-bus"; +- ranges; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- interrupt-parent = <&cpuintc>; +- +- apb { +- compatible = "simple-bus"; +- ranges; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- interrupt-parent = <&miscintc>; +- +- ddr_ctrl: memory-controller@18000000 { +- compatible = "qca,ar7240-ddr-controller"; +- reg = <0x18000000 0x100>; +- +- #qca,ddr-wb-channel-cells = <1>; +- }; +- +- uart: serial@18020000 { +- compatible = "qca,ar9330-uart"; +- reg = <0x18020000 0x14>; +- +- interrupts = <3>; +- +- clocks = <&ref>; +- clock-names = "uart"; +- +- status = "disabled"; +- }; +- +- gpio: gpio@18040000 { +- compatible = "qca,ar7100-gpio"; +- reg = <0x18040000 0x34>; +- interrupts = <2>; +- +- ngpios = <30>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- +- status = "disabled"; +- }; +- +- pll: pll-controller@18050000 { +- compatible = "qca,ar9330-pll"; +- reg = <0x18050000 0x100>; +- +- clocks = <&ref>; +- clock-names = "ref"; +- +- #clock-cells = <1>; +- }; +- +- miscintc: interrupt-controller@18060010 { +- compatible = "qca,ar7240-misc-intc"; +- reg = <0x18060010 0x8>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <6>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- rst: reset-controller@1806001c { +- compatible = "qca,ar7100-reset"; +- reg = <0x1806001c 0x4>; +- +- #reset-cells = <1>; +- }; +- }; +- +- eth0: ethernet@19000000 { +- compatible = "qca,ar9330-eth"; +- reg = <0x19000000 0x200>; +- interrupts = <4>; +- +- resets = <&rst 9>, <&rst 22>; +- reset-names = "mac", "mdio"; +- clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; +- clock-names = "eth", "mdio"; +- +- phy-mode = "mii"; +- phy-handle = <&phy_port4>; +- +- status = "disabled"; +- }; +- +- eth1: ethernet@1a000000 { +- compatible = "qca,ar9330-eth"; +- reg = <0x1a000000 0x200>; +- interrupts = <5>; +- resets = <&rst 13>, <&rst 23>; +- reset-names = "mac", "mdio"; +- clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; +- clock-names = "eth", "mdio"; +- +- phy-mode = "gmii"; +- +- status = "disabled"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- pause; +- }; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch10: switch@10 { +- #address-cells = <1>; +- #size-cells = <0>; +- +- compatible = "qca,ar9331-switch"; +- reg = <0x10>; +- resets = <&rst 8>; +- reset-names = "switch"; +- +- interrupt-parent = <&miscintc>; +- interrupts = <12>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch_port0: port@0 { +- reg = <0x0>; +- label = "cpu"; +- ethernet = <ð1>; +- +- phy-mode = "gmii"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- pause; +- }; +- }; +- +- switch_port1: port@1 { +- reg = <0x1>; +- phy-handle = <&phy_port0>; +- phy-mode = "internal"; +- +- status = "disabled"; +- }; +- +- switch_port2: port@2 { +- reg = <0x2>; +- phy-handle = <&phy_port1>; +- phy-mode = "internal"; +- +- status = "disabled"; +- }; +- +- switch_port3: port@3 { +- reg = <0x3>; +- phy-handle = <&phy_port2>; +- phy-mode = "internal"; +- +- status = "disabled"; +- }; +- +- switch_port4: port@4 { +- reg = <0x4>; +- phy-handle = <&phy_port3>; +- phy-mode = "internal"; +- +- status = "disabled"; +- }; +- }; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- interrupt-parent = <&switch10>; +- +- phy_port0: phy@0 { +- reg = <0x0>; +- interrupts = <0>; +- status = "disabled"; +- }; +- +- phy_port1: phy@1 { +- reg = <0x1>; +- interrupts = <0>; +- status = "disabled"; +- }; +- +- phy_port2: phy@2 { +- reg = <0x2>; +- interrupts = <0>; +- status = "disabled"; +- }; +- +- phy_port3: phy@3 { +- reg = <0x3>; +- interrupts = <0>; +- status = "disabled"; +- }; +- +- phy_port4: phy@4 { +- reg = <0x4>; +- interrupts = <0>; +- status = "disabled"; +- }; +- }; +- }; +- }; +- }; +- +- usb: usb@1b000100 { +- compatible = "chipidea,usb2"; +- reg = <0x1b000000 0x200>; +- +- interrupts = <3>; +- resets = <&rst 5>; +- +- phy-names = "usb-phy"; +- phys = <&usb_phy>; +- +- status = "disabled"; +- }; +- +- spi: spi@1f000000 { +- compatible = "qca,ar7100-spi"; +- reg = <0x1f000000 0x10>; +- +- clocks = <&pll ATH79_CLK_AHB>; +- clock-names = "ahb"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- }; +- +- usb_phy: usb-phy { +- compatible = "qca,ar7100-usb-phy"; +- +- reset-names = "phy", "suspend-override"; +- resets = <&rst 4>, <&rst 3>; +- +- #phy-cells = <0>; +- +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/qca/ar9331_dpt_module.dts b/scripts/dtc/include-prefixes/mips/qca/ar9331_dpt_module.dts +deleted file mode 100644 +index 7695d326df11..000000000000 +--- a/scripts/dtc/include-prefixes/mips/qca/ar9331_dpt_module.dts ++++ /dev/null +@@ -1,101 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +-#include +- +-#include "ar9331.dtsi" +- +-/ { +- model = "DPTechnics DPT-Module"; +- compatible = "dptechnics,dpt-module"; +- +- aliases { +- serial0 = &uart; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x4000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- function = LED_FUNCTION_STATUS; +- color = ; +- gpios = <&gpio 27 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- button@0 { +- label = "reset"; +- linux,code = ; +- gpios = <&gpio 11 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&ref { +- clock-frequency = <25000000>; +-}; +- +-&uart { +- status = "okay"; +-}; +- +-&gpio { +- status = "okay"; +-}; +- +-&usb { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb_phy { +- status = "okay"; +-}; +- +-&spi { +- num-chipselects = <1>; +- status = "okay"; +- +- /* Winbond 25Q128FVSG SPI flash */ +- spiflash: w25q128@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "winbond,w25q128", "jedec,spi-nor"; +- spi-max-frequency = <104000000>; +- reg = <0>; +- }; +-}; +- +-ð0 { +- status = "okay"; +-}; +- +-ð1 { +- status = "okay"; +-}; +- +-&switch_port1 { +- label = "lan0"; +- status = "okay"; +-}; +- +-&phy_port0 { +- status = "okay"; +-}; +- +-&phy_port4 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/qca/ar9331_dragino_ms14.dts b/scripts/dtc/include-prefixes/mips/qca/ar9331_dragino_ms14.dts +deleted file mode 100644 +index d38aa73f1a2e..000000000000 +--- a/scripts/dtc/include-prefixes/mips/qca/ar9331_dragino_ms14.dts ++++ /dev/null +@@ -1,102 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +- +-#include "ar9331.dtsi" +- +-/ { +- model = "Dragino MS14 (Dragino 2)"; +- compatible = "dragino,ms14"; +- +- aliases { +- serial0 = &uart; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x4000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- wlan { +- label = "dragino2:red:wlan"; +- gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- lan { +- label = "dragino2:red:lan"; +- gpios = <&gpio 13 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- wan { +- label = "dragino2:red:wan"; +- gpios = <&gpio 17 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- system { +- label = "dragino2:red:system"; +- gpios = <&gpio 28 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- button@0 { +- label = "jumpstart"; +- linux,code = ; +- gpios = <&gpio 11 GPIO_ACTIVE_LOW>; +- }; +- +- button@1 { +- label = "reset"; +- linux,code = ; +- gpios = <&gpio 12 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-&ref { +- clock-frequency = <25000000>; +-}; +- +-&uart { +- status = "okay"; +-}; +- +-&gpio { +- status = "okay"; +-}; +- +-&usb { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb_phy { +- status = "okay"; +-}; +- +-&spi { +- num-chipselects = <1>; +- status = "okay"; +- +- /* Winbond 25Q128BVFG SPI flash */ +- spiflash: w25q128@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "winbond,w25q128", "jedec,spi-nor"; +- spi-max-frequency = <104000000>; +- reg = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/qca/ar9331_omega.dts b/scripts/dtc/include-prefixes/mips/qca/ar9331_omega.dts +deleted file mode 100644 +index 11778abacf66..000000000000 +--- a/scripts/dtc/include-prefixes/mips/qca/ar9331_omega.dts ++++ /dev/null +@@ -1,78 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +- +-#include "ar9331.dtsi" +- +-/ { +- model = "Onion Omega"; +- compatible = "onion,omega"; +- +- aliases { +- serial0 = &uart; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x4000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- system { +- label = "onion:amber:system"; +- gpios = <&gpio 27 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- button@0 { +- label = "reset"; +- linux,code = ; +- gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&ref { +- clock-frequency = <25000000>; +-}; +- +-&uart { +- status = "okay"; +-}; +- +-&gpio { +- status = "okay"; +-}; +- +-&usb { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb_phy { +- status = "okay"; +-}; +- +-&spi { +- num-chipselects = <1>; +- status = "okay"; +- +- /* Winbond 25Q128FVSG SPI flash */ +- spiflash: w25q128@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "winbond,w25q128", "jedec,spi-nor"; +- spi-max-frequency = <104000000>; +- reg = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/qca/ar9331_openembed_som9331_board.dts b/scripts/dtc/include-prefixes/mips/qca/ar9331_openembed_som9331_board.dts +deleted file mode 100644 +index e6622f8e8c2b..000000000000 +--- a/scripts/dtc/include-prefixes/mips/qca/ar9331_openembed_som9331_board.dts ++++ /dev/null +@@ -1,110 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/dts-v1/; +- +-#include +-#include +-#include +- +-#include "ar9331.dtsi" +- +-/ { +- model = "OpenEmbed SOM9331 Board"; +- compatible = "openembed,som9331"; +- +- aliases { +- serial0 = &uart; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x4000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-0 { +- function = LED_FUNCTION_STATUS; +- color = ; +- gpios = <&gpio 27 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- button@0 { +- label = "reset"; +- linux,code = ; +- gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; +- }; +- }; +-}; +- +-&ref { +- clock-frequency = <25000000>; +-}; +- +-&uart { +- status = "okay"; +-}; +- +-&gpio { +- status = "okay"; +-}; +- +-&usb { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb_phy { +- status = "okay"; +-}; +- +-&spi { +- num-chipselects = <1>; +- status = "okay"; +- +- /* Winbond 25Q64FVSIG SPI flash */ +- spiflash: w25q64@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "winbond,w25q64", "jedec,spi-nor"; +- spi-max-frequency = <104000000>; +- reg = <0>; +- }; +-}; +- +-ð0 { +- status = "okay"; +-}; +- +-ð1 { +- status = "okay"; +-}; +- +-&switch_port1 { +- label = "lan0"; +- status = "okay"; +-}; +- +-&switch_port3 { +- label = "lan1"; +- status = "okay"; +-}; +- +-&phy_port0 { +- status = "okay"; +-}; +- +-&phy_port2 { +- status = "okay"; +-}; +- +-&phy_port4 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/qca/ar9331_tl_mr3020.dts b/scripts/dtc/include-prefixes/mips/qca/ar9331_tl_mr3020.dts +deleted file mode 100644 +index c8290d36cfbe..000000000000 +--- a/scripts/dtc/include-prefixes/mips/qca/ar9331_tl_mr3020.dts ++++ /dev/null +@@ -1,118 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include +-#include +- +-#include "ar9331.dtsi" +- +-/ { +- model = "TP-Link TL-MR3020"; +- compatible = "tplink,tl-mr3020"; +- +- aliases { +- serial0 = &uart; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x2000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- wlan { +- label = "tp-link:green:wlan"; +- gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- lan { +- label = "tp-link:green:lan"; +- gpios = <&gpio 17 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- wps { +- label = "tp-link:green:wps"; +- gpios = <&gpio 26 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led3g { +- label = "tp-link:green:3g"; +- gpios = <&gpio 27 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- button@0 { +- label = "wps"; +- linux,code = ; +- gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; +- }; +- +- button@1 { +- label = "sw1"; +- linux,code = ; +- gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; +- }; +- +- button@2 { +- label = "sw2"; +- linux,code = ; +- gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- reg_usb_vbus: reg_usb_vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio 8 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +-}; +- +-&ref { +- clock-frequency = <25000000>; +-}; +- +-&uart { +- status = "okay"; +-}; +- +-&gpio { +- status = "okay"; +-}; +- +-&usb { +- dr_mode = "host"; +- vbus-supply = <®_usb_vbus>; +- status = "okay"; +-}; +- +-&usb_phy { +- status = "okay"; +-}; +- +-&spi { +- num-chipselects = <1>; +- status = "okay"; +- +- /* Spansion S25FL032PIF SPI flash */ +- spiflash: s25sl032p@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25sl032p", "jedec,spi-nor"; +- spi-max-frequency = <104000000>; +- reg = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ralink/Makefile b/scripts/dtc/include-prefixes/mips/ralink/Makefile +deleted file mode 100644 +index 6c26dfa0a903..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ralink/Makefile ++++ /dev/null +@@ -1,9 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_DTB_RT2880_EVAL) += rt2880_eval.dtb +-dtb-$(CONFIG_DTB_RT305X_EVAL) += rt3052_eval.dtb +-dtb-$(CONFIG_DTB_RT3883_EVAL) += rt3883_eval.dtb +-dtb-$(CONFIG_DTB_MT7620A_EVAL) += mt7620a_eval.dtb +-dtb-$(CONFIG_DTB_OMEGA2P) += omega2p.dtb +-dtb-$(CONFIG_DTB_VOCORE2) += vocore2.dtb +- +-obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) +diff --git a/scripts/dtc/include-prefixes/mips/ralink/gardena_smart_gateway_mt7688.dts b/scripts/dtc/include-prefixes/mips/ralink/gardena_smart_gateway_mt7688.dts +deleted file mode 100644 +index 6069b33cf09f..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ralink/gardena_smart_gateway_mt7688.dts ++++ /dev/null +@@ -1,205 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (c) 2019 Stefan Roese +- */ +- +-/dts-v1/; +- +-/include/ "mt7628a.dtsi" +- +-#include +-#include +- +-/ { +- compatible = "gardena,smart-gateway-mt7688", "ralink,mt7688a-soc", +- "ralink,mt7628a-soc"; +- model = "GARDENA smart Gateway (MT7688)"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x8000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinmux_gpio_gpio>; /* GPIO11 */ +- +- user_btn1 { +- label = "USER_BTN1"; +- gpios = <&gpio 11 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinmux_pwm0_gpio>, /* GPIO18 */ +- <&pinmux_pwm1_gpio>, /* GPIO19 */ +- <&pinmux_sdmode_gpio>, /* GPIO22..29 */ +- <&pinmux_p0led_an_gpio>; /* GPIO43 */ +- /* +- * <&pinmux_i2s_gpio> (covers GPIO0..3) is needed here as +- * well for GPIO3. But this is already claimed for uart1 +- * (see below). So we can't include it in this LED node. +- */ +- +- power_blue { +- label = "smartgw:power:blue"; +- gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- power_green { +- label = "smartgw:power:green"; +- gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- power_red { +- label = "smartgw:power:red"; +- gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- radio_blue { +- label = "smartgw:radio:blue"; +- gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- radio_green { +- label = "smartgw:radio:green"; +- gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- radio_red { +- label = "smartgw:radio:red"; +- gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- internet_blue { +- label = "smartgw:internet:blue"; +- gpios = <&gpio 26 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- internet_green { +- label = "smartgw:internet:green"; +- gpios = <&gpio 27 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- internet_red { +- label = "smartgw:internet:red"; +- gpios = <&gpio 28 GPIO_ACTIVE_HIGH>; +- default-state = "off"; +- }; +- +- ethernet_link { +- label = "smartgw:eth:link"; +- gpios = <&gpio 3 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "netdev"; +- }; +- +- ethernet_activity { +- label = "smartgw:eth:act"; +- gpios = <&gpio 43 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "netdev"; +- }; +- }; +- +- aliases { +- serial0 = &uart0; +- }; +-}; +- +-&i2c { +- status = "okay"; +-}; +- +-&spi { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinmux_spi_spi>, <&pinmux_spi_cs1_cs>; +- +- m25p80@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "uboot"; +- reg = <0x0 0xa0000>; +- read-only; +- }; +- +- partition@a0000 { +- label = "uboot_env0"; +- reg = <0xa0000 0x10000>; +- }; +- +- partition@b0000 { +- label = "uboot_env1"; +- reg = <0xb0000 0x10000>; +- }; +- +- factory: partition@c0000 { +- label = "factory"; +- reg = <0xc0000 0x10000>; +- read-only; +- }; +- }; +- }; +- +- nand_flash@1 { +- compatible = "spi-nand"; +- linux,mtd-name = "gd5f"; +- reg = <1>; +- spi-max-frequency = <40000000>; +- }; +-}; +- +-&uart1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinmux_i2s_gpio>; /* GPIO0..3 */ +- +- fifo-size = <8>; +- tx-threshold = <8>; +- +- rts-gpios = <&gpio 1 GPIO_ACTIVE_LOW>; +- cts-gpios = <&gpio 2 GPIO_ACTIVE_LOW>; +-}; +- +-&uart2 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinmux_p2led_an_gpio>, /* GPIO41 */ +- <&pinmux_p3led_an_gpio>; /* GPIO40 */ +- +- rts-gpios = <&gpio 40 GPIO_ACTIVE_LOW>; +- cts-gpios = <&gpio 41 GPIO_ACTIVE_LOW>; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-&wmac { +- status = "okay"; +- mediatek,mtd-eeprom = <&factory 0x0000>; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ralink/mt7620a.dtsi b/scripts/dtc/include-prefixes/mips/ralink/mt7620a.dtsi +deleted file mode 100644 +index 1f6e5320f486..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ralink/mt7620a.dtsi ++++ /dev/null +@@ -1,59 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ralink,mtk7620a-soc"; +- +- cpus { +- cpu@0 { +- compatible = "mips,mips24KEc"; +- }; +- }; +- +- cpuintc: cpuintc { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- palmbus@10000000 { +- compatible = "palmbus"; +- reg = <0x10000000 0x200000>; +- ranges = <0x0 0x10000000 0x1FFFFF>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- sysc@0 { +- compatible = "ralink,mt7620a-sysc"; +- reg = <0x0 0x100>; +- }; +- +- intc: intc@200 { +- compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc"; +- reg = <0x200 0x100>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <2>; +- }; +- +- memc@300 { +- compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc"; +- reg = <0x300 0x100>; +- }; +- +- uartlite@c00 { +- compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; +- reg = <0xc00 0x100>; +- +- interrupt-parent = <&intc>; +- interrupts = <12>; +- +- reg-shift = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ralink/mt7620a_eval.dts b/scripts/dtc/include-prefixes/mips/ralink/mt7620a_eval.dts +deleted file mode 100644 +index 8de8f89f31b8..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ralink/mt7620a_eval.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-/include/ "mt7620a.dtsi" +- +-/ { +- compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc"; +- model = "Ralink MT7620A evaluation board"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x2000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,57600"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ralink/mt7628a.dtsi b/scripts/dtc/include-prefixes/mips/ralink/mt7628a.dtsi +deleted file mode 100644 +index 45bf96a3d17a..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ralink/mt7628a.dtsi ++++ /dev/null +@@ -1,298 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ralink,mt7628a-soc"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "mti,mips24KEc"; +- device_type = "cpu"; +- reg = <0>; +- }; +- }; +- +- resetc: reset-controller { +- compatible = "ralink,rt2880-reset"; +- #reset-cells = <1>; +- }; +- +- cpuintc: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- palmbus@10000000 { +- compatible = "palmbus"; +- reg = <0x10000000 0x200000>; +- ranges = <0x0 0x10000000 0x1FFFFF>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- sysc: system-controller@0 { +- compatible = "ralink,mt7620a-sysc", "syscon"; +- reg = <0x0 0x60>; +- }; +- +- pinmux: pinmux@60 { +- compatible = "pinctrl-single"; +- reg = <0x60 0x8>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <2>; +- pinctrl-single,bit-per-mux; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0x1>; +- +- pinmux_gpio_gpio: pinmux_gpio_gpio { +- pinctrl-single,bits = <0x0 0x0 0x3>; +- }; +- +- pinmux_spi_cs1_cs: pinmux_spi_cs1_cs { +- pinctrl-single,bits = <0x0 0x0 0x30>; +- }; +- +- pinmux_i2s_gpio: pinmux_i2s_gpio { +- pinctrl-single,bits = <0x0 0x40 0xc0>; +- }; +- +- pinmux_uart0_uart: pinmux_uart0_uart0 { +- pinctrl-single,bits = <0x0 0x0 0x300>; +- }; +- +- pinmux_sdmode_sdxc: pinmux_sdmode_sdxc { +- pinctrl-single,bits = <0x0 0x0 0xc00>; +- }; +- +- pinmux_sdmode_gpio: pinmux_sdmode_gpio { +- pinctrl-single,bits = <0x0 0x400 0xc00>; +- }; +- +- pinmux_spi_spi: pinmux_spi_spi { +- pinctrl-single,bits = <0x0 0x0 0x1000>; +- }; +- +- pinmux_refclk_gpio: pinmux_refclk_gpio { +- pinctrl-single,bits = <0x0 0x40000 0x40000>; +- }; +- +- pinmux_i2c_i2c: pinmux_i2c_i2c { +- pinctrl-single,bits = <0x0 0x0 0x300000>; +- }; +- +- pinmux_uart1_uart: pinmux_uart1_uart1 { +- pinctrl-single,bits = <0x0 0x0 0x3000000>; +- }; +- +- pinmux_uart2_uart: pinmux_uart2_uart { +- pinctrl-single,bits = <0x0 0x0 0xc000000>; +- }; +- +- pinmux_pwm0_pwm: pinmux_pwm0_pwm { +- pinctrl-single,bits = <0x0 0x0 0x30000000>; +- }; +- +- pinmux_pwm0_gpio: pinmux_pwm0_gpio { +- pinctrl-single,bits = <0x0 0x10000000 +- 0x30000000>; +- }; +- +- pinmux_pwm1_pwm: pinmux_pwm1_pwm { +- pinctrl-single,bits = <0x0 0x0 0xc0000000>; +- }; +- +- pinmux_pwm1_gpio: pinmux_pwm1_gpio { +- pinctrl-single,bits = <0x0 0x40000000 +- 0xc0000000>; +- }; +- +- pinmux_p0led_an_gpio: pinmux_p0led_an_gpio { +- pinctrl-single,bits = <0x4 0x4 0xc>; +- }; +- +- pinmux_p1led_an_gpio: pinmux_p1led_an_gpio { +- pinctrl-single,bits = <0x4 0x10 0x30>; +- }; +- +- pinmux_p2led_an_gpio: pinmux_p2led_an_gpio { +- pinctrl-single,bits = <0x4 0x40 0xc0>; +- }; +- +- pinmux_p3led_an_gpio: pinmux_p3led_an_gpio { +- pinctrl-single,bits = <0x4 0x100 0x300>; +- }; +- +- pinmux_p4led_an_gpio: pinmux_p4led_an_gpio { +- pinctrl-single,bits = <0x4 0x400 0xc00>; +- }; +- }; +- +- watchdog: watchdog@100 { +- compatible = "mediatek,mt7621-wdt"; +- reg = <0x100 0x30>; +- +- resets = <&resetc 8>; +- reset-names = "wdt"; +- +- interrupt-parent = <&intc>; +- interrupts = <24>; +- +- status = "disabled"; +- }; +- +- intc: interrupt-controller@200 { +- compatible = "ralink,rt2880-intc"; +- reg = <0x200 0x100>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- resets = <&resetc 9>; +- reset-names = "intc"; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <2>; +- +- ralink,intc-registers = <0x9c 0xa0 +- 0x6c 0xa4 +- 0x80 0x78>; +- }; +- +- memory-controller@300 { +- compatible = "ralink,mt7620a-memc"; +- reg = <0x300 0x100>; +- }; +- +- gpio: gpio@600 { +- compatible = "mediatek,mt7621-gpio"; +- reg = <0x600 0x100>; +- +- gpio-controller; +- interrupt-controller; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- +- interrupt-parent = <&intc>; +- interrupts = <6>; +- }; +- +- spi: spi@b00 { +- compatible = "ralink,mt7621-spi"; +- reg = <0xb00 0x100>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinmux_spi_spi>; +- +- resets = <&resetc 18>; +- reset-names = "spi"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- +- i2c: i2c@900 { +- compatible = "mediatek,mt7621-i2c"; +- reg = <0x900 0x100>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinmux_i2c_i2c>; +- +- resets = <&resetc 16>; +- reset-names = "i2c"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- status = "disabled"; +- }; +- +- uart0: uartlite@c00 { +- compatible = "ns16550a"; +- reg = <0xc00 0x100>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinmux_uart0_uart>; +- +- resets = <&resetc 12>; +- reset-names = "uart0"; +- +- interrupt-parent = <&intc>; +- interrupts = <20>; +- +- reg-shift = <2>; +- }; +- +- uart1: uart1@d00 { +- compatible = "ns16550a"; +- reg = <0xd00 0x100>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinmux_uart1_uart>; +- +- resets = <&resetc 19>; +- reset-names = "uart1"; +- +- interrupt-parent = <&intc>; +- interrupts = <21>; +- +- reg-shift = <2>; +- }; +- +- uart2: uart2@e00 { +- compatible = "ns16550a"; +- reg = <0xe00 0x100>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinmux_uart2_uart>; +- +- resets = <&resetc 20>; +- reset-names = "uart2"; +- +- interrupt-parent = <&intc>; +- interrupts = <22>; +- +- reg-shift = <2>; +- }; +- }; +- +- usb_phy: usb-phy@10120000 { +- compatible = "mediatek,mt7628-usbphy"; +- reg = <0x10120000 0x1000>; +- +- #phy-cells = <0>; +- +- ralink,sysctl = <&sysc>; +- resets = <&resetc 22 &resetc 25>; +- reset-names = "host", "device"; +- }; +- +- usb@101c0000 { +- compatible = "generic-ehci"; +- reg = <0x101c0000 0x1000>; +- +- phys = <&usb_phy>; +- phy-names = "usb"; +- +- interrupt-parent = <&intc>; +- interrupts = <18>; +- }; +- +- wmac: wmac@10300000 { +- compatible = "mediatek,mt7628-wmac"; +- reg = <0x10300000 0x100000>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <6>; +- +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ralink/omega2p.dts b/scripts/dtc/include-prefixes/mips/ralink/omega2p.dts +deleted file mode 100644 +index 5884fd48f59a..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ralink/omega2p.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-/dts-v1/; +- +-/include/ "mt7628a.dtsi" +- +-/ { +- compatible = "onion,omega2+", "ralink,mt7688a-soc", "ralink,mt7628a-soc"; +- model = "Onion Omega2+"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = &uart0; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ralink/rt2880.dtsi b/scripts/dtc/include-prefixes/mips/ralink/rt2880.dtsi +deleted file mode 100644 +index 8fc1987d9063..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ralink/rt2880.dtsi ++++ /dev/null +@@ -1,59 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ralink,rt2880-soc"; +- +- cpus { +- cpu@0 { +- compatible = "mips,mips4KEc"; +- }; +- }; +- +- cpuintc: cpuintc { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- palmbus@300000 { +- compatible = "palmbus"; +- reg = <0x300000 0x200000>; +- ranges = <0x0 0x300000 0x1FFFFF>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- sysc@0 { +- compatible = "ralink,rt2880-sysc"; +- reg = <0x0 0x100>; +- }; +- +- intc: intc@200 { +- compatible = "ralink,rt2880-intc"; +- reg = <0x200 0x100>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <2>; +- }; +- +- memc@300 { +- compatible = "ralink,rt2880-memc"; +- reg = <0x300 0x100>; +- }; +- +- uartlite@c00 { +- compatible = "ralink,rt2880-uart", "ns16550a"; +- reg = <0xc00 0x100>; +- +- interrupt-parent = <&intc>; +- interrupts = <8>; +- +- reg-shift = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ralink/rt2880_eval.dts b/scripts/dtc/include-prefixes/mips/ralink/rt2880_eval.dts +deleted file mode 100644 +index 759bc1dd5b83..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ralink/rt2880_eval.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-/include/ "rt2880.dtsi" +- +-/ { +- compatible = "ralink,rt2880-eval-board", "ralink,rt2880-soc"; +- model = "Ralink RT2880 evaluation board"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x8000000 0x2000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,57600"; +- }; +- +- cfi@1f000000 { +- compatible = "cfi-flash"; +- reg = <0x1f000000 0x400000>; +- +- bank-width = <2>; +- device-width = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "uboot"; +- reg = <0x0 0x30000>; +- read-only; +- }; +- partition@30000 { +- label = "uboot-env"; +- reg = <0x30000 0x10000>; +- read-only; +- }; +- partition@40000 { +- label = "calibration"; +- reg = <0x40000 0x10000>; +- read-only; +- }; +- partition@50000 { +- label = "linux"; +- reg = <0x50000 0x3b0000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ralink/rt3050.dtsi b/scripts/dtc/include-prefixes/mips/ralink/rt3050.dtsi +deleted file mode 100644 +index 23062333a76d..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ralink/rt3050.dtsi ++++ /dev/null +@@ -1,69 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc"; +- +- cpus { +- cpu@0 { +- compatible = "mips,mips24KEc"; +- }; +- }; +- +- cpuintc: cpuintc { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- palmbus@10000000 { +- compatible = "palmbus"; +- reg = <0x10000000 0x200000>; +- ranges = <0x0 0x10000000 0x1FFFFF>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- sysc@0 { +- compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc"; +- reg = <0x0 0x100>; +- }; +- +- intc: intc@200 { +- compatible = "ralink,rt3052-intc", "ralink,rt2880-intc"; +- reg = <0x200 0x100>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <2>; +- }; +- +- memc@300 { +- compatible = "ralink,rt3052-memc", "ralink,rt3050-memc"; +- reg = <0x300 0x100>; +- }; +- +- uartlite@c00 { +- compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a"; +- reg = <0xc00 0x100>; +- +- interrupt-parent = <&intc>; +- interrupts = <12>; +- +- reg-shift = <2>; +- }; +- }; +- +- usb@101c0000 { +- compatible = "ralink,rt3050-usb", "snps,dwc2"; +- reg = <0x101c0000 40000>; +- +- interrupt-parent = <&intc>; +- interrupts = <18>; +- +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ralink/rt3052_eval.dts b/scripts/dtc/include-prefixes/mips/ralink/rt3052_eval.dts +deleted file mode 100644 +index 6408ff629d5a..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ralink/rt3052_eval.dts ++++ /dev/null +@@ -1,52 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "rt3050.dtsi" +- +-/ { +- compatible = "ralink,rt3052-eval-board", "ralink,rt3052-soc"; +- model = "Ralink RT3052 evaluation board"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x2000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,57600"; +- }; +- +- cfi@1f000000 { +- compatible = "cfi-flash"; +- reg = <0x1f000000 0x800000>; +- +- bank-width = <2>; +- device-width = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "uboot"; +- reg = <0x0 0x30000>; +- read-only; +- }; +- partition@30000 { +- label = "uboot-env"; +- reg = <0x30000 0x10000>; +- read-only; +- }; +- partition@40000 { +- label = "calibration"; +- reg = <0x40000 0x10000>; +- read-only; +- }; +- partition@50000 { +- label = "linux"; +- reg = <0x50000 0x7b0000>; +- }; +- }; +- +- usb@101c0000 { +- status = "okay"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ralink/rt3883.dtsi b/scripts/dtc/include-prefixes/mips/ralink/rt3883.dtsi +deleted file mode 100644 +index 61132cf157e5..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ralink/rt3883.dtsi ++++ /dev/null +@@ -1,59 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ralink,rt3883-soc"; +- +- cpus { +- cpu@0 { +- compatible = "mips,mips74Kc"; +- }; +- }; +- +- cpuintc: cpuintc { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- palmbus@10000000 { +- compatible = "palmbus"; +- reg = <0x10000000 0x200000>; +- ranges = <0x0 0x10000000 0x1FFFFF>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- sysc@0 { +- compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc"; +- reg = <0x0 0x100>; +- }; +- +- intc: intc@200 { +- compatible = "ralink,rt3883-intc", "ralink,rt2880-intc"; +- reg = <0x200 0x100>; +- +- interrupt-controller; +- #interrupt-cells = <1>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <2>; +- }; +- +- memc@300 { +- compatible = "ralink,rt3883-memc", "ralink,rt3050-memc"; +- reg = <0x300 0x100>; +- }; +- +- uartlite@c00 { +- compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a"; +- reg = <0xc00 0x100>; +- +- interrupt-parent = <&intc>; +- interrupts = <12>; +- +- reg-shift = <2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ralink/rt3883_eval.dts b/scripts/dtc/include-prefixes/mips/ralink/rt3883_eval.dts +deleted file mode 100644 +index c22bc84df219..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ralink/rt3883_eval.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-/include/ "rt3883.dtsi" +- +-/ { +- compatible = "ralink,rt3883-eval-board", "ralink,rt3883-soc"; +- model = "Ralink RT3883 evaluation board"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x2000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS0,57600"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/ralink/vocore2.dts b/scripts/dtc/include-prefixes/mips/ralink/vocore2.dts +deleted file mode 100644 +index fa8a5f8f236a..000000000000 +--- a/scripts/dtc/include-prefixes/mips/ralink/vocore2.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-/dts-v1/; +- +-#include "mt7628a.dtsi" +- +-/ { +- compatible = "vocore,vocore2", "ralink,mt7628a-soc"; +- model = "VoCore2"; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x8000000>; +- }; +- +- chosen { +- bootargs = "console=ttyS2,115200"; +- stdout-path = &uart2; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/realtek/Makefile b/scripts/dtc/include-prefixes/mips/realtek/Makefile +deleted file mode 100644 +index fba4e93187a6..000000000000 +--- a/scripts/dtc/include-prefixes/mips/realtek/Makefile ++++ /dev/null +@@ -1,2 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-y += cisco_sg220-26.dtb +diff --git a/scripts/dtc/include-prefixes/mips/realtek/cisco_sg220-26.dts b/scripts/dtc/include-prefixes/mips/realtek/cisco_sg220-26.dts +deleted file mode 100644 +index 1cdbb09297ef..000000000000 +--- a/scripts/dtc/include-prefixes/mips/realtek/cisco_sg220-26.dts ++++ /dev/null +@@ -1,25 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause +- +-/dts-v1/; +- +-#include "rtl83xx.dtsi" +-#include "rtl838x.dtsi" +- +-/ { +- model = "Cisco SG220-26"; +- compatible = "cisco,sg220-26", "realtek,rtl8382-soc"; +- +- chosen { +- stdout-path = "serial0:9600n8"; +- bootargs = "earlycon console=ttyS0,9600"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x8000000>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/realtek/rtl838x.dtsi b/scripts/dtc/include-prefixes/mips/realtek/rtl838x.dtsi +deleted file mode 100644 +index 6cc4ff5c0d19..000000000000 +--- a/scripts/dtc/include-prefixes/mips/realtek/rtl838x.dtsi ++++ /dev/null +@@ -1,21 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause +- +-/ { +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "mips,mips4KEc"; +- reg = <0>; +- clocks = <&baseclk 0>; +- clock-names = "cpu"; +- }; +- }; +- +- baseclk: baseclk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <500000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/realtek/rtl83xx.dtsi b/scripts/dtc/include-prefixes/mips/realtek/rtl83xx.dtsi +deleted file mode 100644 +index de65a111b626..000000000000 +--- a/scripts/dtc/include-prefixes/mips/realtek/rtl83xx.dtsi ++++ /dev/null +@@ -1,59 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- }; +- +- cpuintc: cpuintc { +- compatible = "mti,cpu-interrupt-controller"; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- }; +- +- soc: soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x18000000 0x10000>; +- +- uart0: uart@2000 { +- compatible = "ns16550a"; +- reg = <0x2000 0x100>; +- +- clock-frequency = <200000000>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <31>; +- +- reg-io-width = <1>; +- reg-shift = <2>; +- fifo-size = <1>; +- no-loopback-test; +- +- status = "disabled"; +- }; +- +- uart1: uart@2100 { +- compatible = "ns16550a"; +- reg = <0x2100 0x100>; +- +- clock-frequency = <200000000>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <30>; +- +- reg-io-width = <1>; +- reg-shift = <2>; +- fifo-size = <1>; +- no-loopback-test; +- +- status = "disabled"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/xilfpga/Makefile b/scripts/dtc/include-prefixes/mips/xilfpga/Makefile +deleted file mode 100644 +index 69ca00590b8d..000000000000 +--- a/scripts/dtc/include-prefixes/mips/xilfpga/Makefile ++++ /dev/null +@@ -1,2 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += nexys4ddr.dtb +diff --git a/scripts/dtc/include-prefixes/mips/xilfpga/microAptiv.dtsi b/scripts/dtc/include-prefixes/mips/xilfpga/microAptiv.dtsi +deleted file mode 100644 +index 87b2b1f9a1b0..000000000000 +--- a/scripts/dtc/include-prefixes/mips/xilfpga/microAptiv.dtsi ++++ /dev/null +@@ -1,22 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "img,xilfpga"; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- device_type = "cpu"; +- compatible = "mips,m14Kc"; +- clocks = <&ext>; +- reg = <0>; +- }; +- }; +- +- ext: ext { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/mips/xilfpga/nexys4ddr.dts b/scripts/dtc/include-prefixes/mips/xilfpga/nexys4ddr.dts +deleted file mode 100644 +index cc8dbea0911f..000000000000 +--- a/scripts/dtc/include-prefixes/mips/xilfpga/nexys4ddr.dts ++++ /dev/null +@@ -1,118 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-#include "microAptiv.dtsi" +- +-/ { +- compatible = "digilent,nexys4ddr"; +- +- aliases { +- serial0 = &axi_uart16550; +- }; +- chosen { +- bootargs = "console=ttyS0,115200"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x08000000>; +- }; +- +- cpuintc: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "mti,cpu-interrupt-controller"; +- }; +- +- axi_intc: interrupt-controller@10200000 { +- #interrupt-cells = <1>; +- compatible = "xlnx,xps-intc-1.00.a"; +- interrupt-controller; +- reg = <0x10200000 0x10000>; +- xlnx,kind-of-intr = <0x0>; +- xlnx,num-intr-inputs = <0x6>; +- +- interrupt-parent = <&cpuintc>; +- interrupts = <6>; +- }; +- +- axi_gpio: gpio@10600000 { +- #gpio-cells = <1>; +- compatible = "xlnx,xps-gpio-1.00.a"; +- gpio-controller; +- reg = <0x10600000 0x10000>; +- xlnx,all-inputs = <0x0>; +- xlnx,dout-default = <0x0>; +- xlnx,gpio-width = <0x16>; +- xlnx,interrupt-present = <0x0>; +- xlnx,is-dual = <0x0>; +- xlnx,tri-default = <0xffffffff>; +- } ; +- +- axi_ethernetlite: ethernet@10e00000 { +- compatible = "xlnx,xps-ethernetlite-3.00.a"; +- device_type = "network"; +- interrupt-parent = <&axi_intc>; +- interrupts = <1>; +- phy-handle = <&phy0>; +- reg = <0x10e00000 0x10000>; +- xlnx,duplex = <0x1>; +- xlnx,include-global-buffers = <0x1>; +- xlnx,include-internal-loopback = <0x0>; +- xlnx,include-mdio = <0x1>; +- xlnx,instance = "axi_ethernetlite_inst"; +- xlnx,rx-ping-pong = <0x1>; +- xlnx,s-axi-id-width = <0x1>; +- xlnx,tx-ping-pong = <0x1>; +- xlnx,use-internal = <0x0>; +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- phy0: phy@1 { +- device_type = "ethernet-phy"; +- reg = <1>; +- }; +- }; +- }; +- +- axi_uart16550: serial@10400000 { +- compatible = "ns16550a"; +- reg = <0x10400000 0x10000>; +- +- reg-shift = <2>; +- reg-offset = <0x1000>; +- +- clocks = <&ext>; +- +- interrupt-parent = <&axi_intc>; +- interrupts = <0>; +- }; +- +- axi_i2c: i2c@10a00000 { +- compatible = "xlnx,xps-iic-2.00.a"; +- interrupt-parent = <&axi_intc>; +- interrupts = <4>; +- reg = < 0x10a00000 0x10000 >; +- clocks = <&ext>; +- xlnx,clk-freq = <0x5f5e100>; +- xlnx,family = "Artix7"; +- xlnx,gpo-width = <0x1>; +- xlnx,iic-freq = <0x186a0>; +- xlnx,scl-inertial-delay = <0x0>; +- xlnx,sda-inertial-delay = <0x0>; +- xlnx,ten-bit-adr = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ad7420@4b { +- compatible = "adi,adt7420"; +- reg = <0x4b>; +- }; +- } ; +-}; +- +-&ext { +- clock-frequency = <50000000>; +-}; +diff --git a/scripts/dtc/include-prefixes/nios2 b/scripts/dtc/include-prefixes/nios2 +new file mode 120000 +index 000000000000..51772336d13f +--- /dev/null ++++ b/scripts/dtc/include-prefixes/nios2 +@@ -0,0 +1 @@ ++../../../arch/nios2/boot/dts +\ No newline at end of file +diff --git a/scripts/dtc/include-prefixes/nios2/10m50_devboard.dts b/scripts/dtc/include-prefixes/nios2/10m50_devboard.dts +deleted file mode 100644 +index 56339bef3247..000000000000 +--- a/scripts/dtc/include-prefixes/nios2/10m50_devboard.dts ++++ /dev/null +@@ -1,237 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2015 Altera Corporation. All rights reserved. +- */ +- +-/dts-v1/; +- +-/ { +- model = "Altera NiosII Max10"; +- compatible = "altr,niosii-max10"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu: cpu@0 { +- device_type = "cpu"; +- compatible = "altr,nios2-1.1"; +- reg = <0x00000000>; +- interrupt-controller; +- #interrupt-cells = <1>; +- altr,exception-addr = <0xc8000120>; +- altr,fast-tlb-miss-addr = <0xc0000100>; +- altr,has-div = <1>; +- altr,has-initda = <1>; +- altr,has-mmu = <1>; +- altr,has-mul = <1>; +- altr,implementation = "fast"; +- altr,pid-num-bits = <8>; +- altr,reset-addr = <0xd4000000>; +- altr,tlb-num-entries = <256>; +- altr,tlb-num-ways = <16>; +- altr,tlb-ptr-sz = <8>; +- clock-frequency = <75000000>; +- dcache-line-size = <32>; +- dcache-size = <32768>; +- icache-line-size = <32>; +- icache-size = <32768>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x08000000 0x08000000>, +- <0x00000000 0x00000400>; +- }; +- +- sopc0: sopc@0 { +- device_type = "soc"; +- ranges; +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "altr,avalon", "simple-bus"; +- bus-frequency = <75000000>; +- +- jtag_uart: serial@18001530 { +- compatible = "altr,juart-1.0"; +- reg = <0x18001530 0x00000008>; +- interrupt-parent = <&cpu>; +- interrupts = <7>; +- }; +- +- a_16550_uart_0: serial@18001600 { +- compatible = "altr,16550-FIFO32", "ns16550a"; +- reg = <0x18001600 0x00000200>; +- interrupt-parent = <&cpu>; +- interrupts = <1>; +- auto-flow-control = <1>; +- clock-frequency = <50000000>; +- fifo-size = <32>; +- reg-io-width = <4>; +- reg-shift = <2>; +- tx-threshold = <16>; +- }; +- +- sysid: sysid@18001528 { +- compatible = "altr,sysid-1.0"; +- reg = <0x18001528 0x00000008>; +- id = <4207856382>; +- timestamp = <1431309290>; +- }; +- +- rgmii_0_eth_tse_0: ethernet@400 { +- compatible = "altr,tse-msgdma-1.0", "altr,tse-1.0"; +- reg = <0x00000400 0x00000400>, +- <0x00000820 0x00000020>, +- <0x00000800 0x00000020>, +- <0x000008c0 0x00000008>, +- <0x00000840 0x00000020>, +- <0x00000860 0x00000020>; +- reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc"; +- interrupt-parent = <&cpu>; +- interrupts = <2 3>; +- interrupt-names = "rx_irq", "tx_irq"; +- rx-fifo-depth = <8192>; +- tx-fifo-depth = <8192>; +- address-bits = <48>; +- max-frame-size = <1518>; +- local-mac-address = [00 00 00 00 00 00]; +- altr,has-supplementary-unicast; +- altr,enable-sup-addr = <1>; +- altr,has-hash-multicast-filter; +- altr,enable-hash = <1>; +- phy-mode = "rgmii-id"; +- phy-handle = <&phy0>; +- rgmii_0_eth_tse_0_mdio: mdio { +- compatible = "altr,tse-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- phy0: ethernet-phy@0 { +- reg = <0>; +- device_type = "ethernet-phy"; +- }; +- }; +- }; +- +- enet_pll: clock@0 { +- compatible = "altr,pll-1.0"; +- #clock-cells = <1>; +- +- enet_pll_c0: enet_pll_c0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <125000000>; +- clock-output-names = "enet_pll-c0"; +- }; +- +- enet_pll_c1: enet_pll_c1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- clock-output-names = "enet_pll-c1"; +- }; +- +- enet_pll_c2: enet_pll_c2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <2500000>; +- clock-output-names = "enet_pll-c2"; +- }; +- }; +- +- sys_pll: clock@1 { +- compatible = "altr,pll-1.0"; +- #clock-cells = <1>; +- +- sys_pll_c0: sys_pll_c0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <100000000>; +- clock-output-names = "sys_pll-c0"; +- }; +- +- sys_pll_c1: sys_pll_c1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- clock-output-names = "sys_pll-c1"; +- }; +- +- sys_pll_c2: sys_pll_c2 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <75000000>; +- clock-output-names = "sys_pll-c2"; +- }; +- }; +- +- sys_clk_timer: timer@18001440 { +- compatible = "altr,timer-1.0"; +- reg = <0x18001440 0x00000020>; +- interrupt-parent = <&cpu>; +- interrupts = <0>; +- clock-frequency = <75000000>; +- }; +- +- led_pio: gpio@180014d0 { +- compatible = "altr,pio-1.0"; +- reg = <0x180014d0 0x00000010>; +- altr,ngpio = <4>; +- #gpio-cells = <2>; +- gpio-controller; +- }; +- +- button_pio: gpio@180014c0 { +- compatible = "altr,pio-1.0"; +- reg = <0x180014c0 0x00000010>; +- interrupt-parent = <&cpu>; +- interrupts = <6>; +- altr,ngpio = <3>; +- altr,interrupt-type = <2>; +- edge_type = <1>; +- level_trigger = <0>; +- #gpio-cells = <2>; +- gpio-controller; +- }; +- +- sys_clk_timer_1: timer@880 { +- compatible = "altr,timer-1.0"; +- reg = <0x00000880 0x00000020>; +- interrupt-parent = <&cpu>; +- interrupts = <5>; +- clock-frequency = <75000000>; +- }; +- +- fpga_leds: leds { +- compatible = "gpio-leds"; +- +- led_fpga0: fpga0 { +- label = "fpga_led0"; +- gpios = <&led_pio 0 1>; +- }; +- +- led_fpga1: fpga1 { +- label = "fpga_led1"; +- gpios = <&led_pio 1 1>; +- }; +- +- led_fpga2: fpga2 { +- label = "fpga_led2"; +- gpios = <&led_pio 2 1>; +- }; +- +- led_fpga3: fpga3 { +- label = "fpga_led3"; +- gpios = <&led_pio 3 1>; +- }; +- }; +- }; +- +- chosen { +- bootargs = "debug earlycon console=ttyS0,115200"; +- stdout-path = &a_16550_uart_0; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/nios2/3c120_devboard.dts b/scripts/dtc/include-prefixes/nios2/3c120_devboard.dts +deleted file mode 100644 +index d10fb81686c7..000000000000 +--- a/scripts/dtc/include-prefixes/nios2/3c120_devboard.dts ++++ /dev/null +@@ -1,153 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Copyright (C) 2013 Altera Corporation +- * +- * This file is generated by sopc2dts. +- */ +- +-/dts-v1/; +- +-/ { +- model = "altr,qsys_ghrd_3c120"; +- compatible = "altr,qsys_ghrd_3c120"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu: cpu@0 { +- device_type = "cpu"; +- compatible = "altr,nios2-1.0"; +- reg = <0x00000000>; +- interrupt-controller; +- #interrupt-cells = <1>; +- clock-frequency = <125000000>; +- dcache-line-size = <32>; +- icache-line-size = <32>; +- dcache-size = <32768>; +- icache-size = <32768>; +- altr,implementation = "fast"; +- altr,pid-num-bits = <8>; +- altr,tlb-num-ways = <16>; +- altr,tlb-num-entries = <128>; +- altr,tlb-ptr-sz = <7>; +- altr,has-div = <1>; +- altr,has-mul = <1>; +- altr,reset-addr = <0xc2800000>; +- altr,fast-tlb-miss-addr = <0xc7fff400>; +- altr,exception-addr = <0xd0000020>; +- altr,has-initda = <1>; +- altr,has-mmu = <1>; +- }; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x10000000 0x08000000>, +- <0x07fff400 0x00000400>; +- }; +- +- sopc@0 { +- device_type = "soc"; +- ranges; +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "altr,avalon", "simple-bus"; +- bus-frequency = <125000000>; +- +- pb_cpu_to_io: bridge@8000000 { +- compatible = "simple-bus"; +- reg = <0x08000000 0x00800000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00002000 0x08002000 0x00002000>, +- <0x00004000 0x08004000 0x00000400>, +- <0x00004400 0x08004400 0x00000040>, +- <0x00004800 0x08004800 0x00000040>, +- <0x00004c80 0x08004c80 0x00000020>, +- <0x00004d50 0x08004d50 0x00000008>, +- <0x00008000 0x08008000 0x00000020>, +- <0x00400000 0x08400000 0x00000020>; +- +- timer_1ms: timer@400000 { +- compatible = "altr,timer-1.0"; +- reg = <0x00400000 0x00000020>; +- interrupt-parent = <&cpu>; +- interrupts = <11>; +- clock-frequency = <125000000>; +- }; +- +- timer_0: timer@8000 { +- compatible = "altr,timer-1.0"; +- reg = < 0x00008000 0x00000020 >; +- interrupt-parent = < &cpu >; +- interrupts = < 5 >; +- clock-frequency = < 125000000 >; +- }; +- +- jtag_uart: serial@4d50 { +- compatible = "altr,juart-1.0"; +- reg = <0x00004d50 0x00000008>; +- interrupt-parent = <&cpu>; +- interrupts = <1>; +- }; +- +- tse_mac: ethernet@4000 { +- compatible = "altr,tse-1.0"; +- reg = <0x00004000 0x00000400>, +- <0x00004400 0x00000040>, +- <0x00004800 0x00000040>, +- <0x00002000 0x00002000>; +- reg-names = "control_port", "rx_csr", "tx_csr", "s1"; +- interrupt-parent = <&cpu>; +- interrupts = <2 3>; +- interrupt-names = "rx_irq", "tx_irq"; +- rx-fifo-depth = <8192>; +- tx-fifo-depth = <8192>; +- max-frame-size = <1518>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- phy-mode = "rgmii-id"; +- phy-handle = <&phy0>; +- tse_mac_mdio: mdio { +- compatible = "altr,tse-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- phy0: ethernet-phy@18 { +- reg = <18>; +- device_type = "ethernet-phy"; +- }; +- }; +- }; +- +- uart: serial@4c80 { +- compatible = "altr,uart-1.0"; +- reg = <0x00004c80 0x00000020>; +- interrupt-parent = <&cpu>; +- interrupts = <10>; +- current-speed = <115200>; +- clock-frequency = <62500000>; +- }; +- }; +- +- cfi_flash_64m: flash@0 { +- compatible = "cfi-flash"; +- reg = <0x00000000 0x04000000>; +- bank-width = <2>; +- device-width = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@800000 { +- reg = <0x00800000 0x01e00000>; +- label = "JFFS2 Filesystem"; +- }; +- }; +- }; +- +- chosen { +- bootargs = "debug earlycon console=ttyJ0,115200"; +- stdout-path = &jtag_uart; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/nios2/Makefile b/scripts/dtc/include-prefixes/nios2/Makefile +deleted file mode 100644 +index a91a0b09be63..000000000000 +--- a/scripts/dtc/include-prefixes/nios2/Makefile ++++ /dev/null +@@ -1,6 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +- +-obj-y := $(patsubst "%.dts",%.dtb.o,$(CONFIG_NIOS2_DTB_SOURCE)) +- +-dtstree := $(srctree)/$(src) +-dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts)) +diff --git a/scripts/dtc/include-prefixes/openrisc b/scripts/dtc/include-prefixes/openrisc +new file mode 120000 +index 000000000000..71c3bc75c560 +--- /dev/null ++++ b/scripts/dtc/include-prefixes/openrisc +@@ -0,0 +1 @@ ++../../../arch/openrisc/boot/dts +\ No newline at end of file +diff --git a/scripts/dtc/include-prefixes/openrisc/Makefile b/scripts/dtc/include-prefixes/openrisc/Makefile +deleted file mode 100644 +index 17dd791a833f..000000000000 +--- a/scripts/dtc/include-prefixes/openrisc/Makefile ++++ /dev/null +@@ -1,9 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-ifneq '$(CONFIG_OPENRISC_BUILTIN_DTB)' '""' +-BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_OPENRISC_BUILTIN_DTB)).dtb.o +-else +-BUILTIN_DTB := +-endif +-obj-y += $(BUILTIN_DTB) +- +-#DTC_FLAGS ?= -p 1024 +diff --git a/scripts/dtc/include-prefixes/openrisc/or1klitex.dts b/scripts/dtc/include-prefixes/openrisc/or1klitex.dts +deleted file mode 100644 +index 91c7173c50e6..000000000000 +--- a/scripts/dtc/include-prefixes/openrisc/or1klitex.dts ++++ /dev/null +@@ -1,64 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * LiteX-based System on Chip +- * +- * Copyright (C) 2019 Antmicro +- */ +- +-/dts-v1/; +-/ { +- compatible = "opencores,or1ksim"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&pic>; +- +- aliases { +- serial0 = &serial0; +- }; +- +- chosen { +- bootargs = "console=liteuart"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- compatible = "opencores,or1200-rtlsvn481"; +- reg = <0>; +- clock-frequency = <100000000>; +- }; +- }; +- +- pic: pic { +- compatible = "opencores,or1k-pic"; +- #interrupt-cells = <1>; +- interrupt-controller; +- }; +- +- serial0: serial@e0006800 { +- device_type = "serial"; +- compatible = "litex,liteuart"; +- reg = <0xe0006800 0x100>; +- }; +- +- soc_ctrl0: soc_controller@e0000000 { +- compatible = "litex,soc-controller"; +- reg = <0xe0000000 0xc>; +- status = "okay"; +- }; +- +- ethernet@e0001000 { +- compatible = "litex,liteeth"; +- reg = <0xe0001000 0x7c>, +- <0xe0001800 0x0a>, +- <0x80000000 0x2000>; +- reg-names = "mac", "mdio", "buffer"; +- interrupts = <2>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/openrisc/or1ksim.dts b/scripts/dtc/include-prefixes/openrisc/or1ksim.dts +deleted file mode 100644 +index c0cb74e52f95..000000000000 +--- a/scripts/dtc/include-prefixes/openrisc/or1ksim.dts ++++ /dev/null +@@ -1,57 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-/ { +- compatible = "opencores,or1ksim"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&pic>; +- +- aliases { +- uart0 = &serial0; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "uart0:115200"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x02000000>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- compatible = "opencores,or1200-rtlsvn481"; +- reg = <0>; +- clock-frequency = <20000000>; +- }; +- }; +- +- /* +- * OR1K PIC is built into CPU and accessed via special purpose +- * registers. It is not addressable and, hence, has no 'reg' +- * property. +- */ +- pic: pic { +- compatible = "opencores,or1k-pic"; +- #interrupt-cells = <1>; +- interrupt-controller; +- }; +- +- serial0: serial@90000000 { +- compatible = "opencores,uart16550-rtlsvn105", "ns16550a"; +- reg = <0x90000000 0x100>; +- interrupts = <2>; +- clock-frequency = <20000000>; +- }; +- +- enet0: ethoc@92000000 { +- compatible = "opencores,ethoc"; +- reg = <0x92000000 0x800>; +- interrupts = <4>; +- big-endian; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/openrisc/simple_smp.dts b/scripts/dtc/include-prefixes/openrisc/simple_smp.dts +deleted file mode 100644 +index 71af0e117bfe..000000000000 +--- a/scripts/dtc/include-prefixes/openrisc/simple_smp.dts ++++ /dev/null +@@ -1,69 +0,0 @@ +-/dts-v1/; +-/ { +- compatible = "opencores,or1ksim"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&pic>; +- +- aliases { +- uart0 = &serial0; +- }; +- +- chosen { +- bootargs = "earlycon"; +- stdout-path = "uart0:115200"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x02000000>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- compatible = "opencores,or1200-rtlsvn481"; +- reg = <0>; +- clock-frequency = <20000000>; +- }; +- cpu@1 { +- compatible = "opencores,or1200-rtlsvn481"; +- reg = <1>; +- clock-frequency = <20000000>; +- }; +- }; +- +- ompic: ompic@98000000 { +- compatible = "openrisc,ompic"; +- reg = <0x98000000 16>; +- interrupt-controller; +- #interrupt-cells = <0>; +- interrupts = <1>; +- }; +- +- /* +- * OR1K PIC is built into CPU and accessed via special purpose +- * registers. It is not addressable and, hence, has no 'reg' +- * property. +- */ +- pic: pic { +- compatible = "opencores,or1k-pic-level"; +- #interrupt-cells = <1>; +- interrupt-controller; +- }; +- +- serial0: serial@90000000 { +- compatible = "opencores,uart16550-rtlsvn105", "ns16550a"; +- reg = <0x90000000 0x100>; +- interrupts = <2>; +- clock-frequency = <20000000>; +- }; +- +- enet0: ethoc@92000000 { +- compatible = "opencores,ethoc"; +- reg = <0x92000000 0x800>; +- interrupts = <4>; +- big-endian; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc b/scripts/dtc/include-prefixes/powerpc +new file mode 120000 +index 000000000000..7cd6ec16e899 +--- /dev/null ++++ b/scripts/dtc/include-prefixes/powerpc +@@ -0,0 +1 @@ ++../../../arch/powerpc/boot/dts +\ No newline at end of file +diff --git a/scripts/dtc/include-prefixes/powerpc/Makefile b/scripts/dtc/include-prefixes/powerpc/Makefile +deleted file mode 100644 +index fb335d05aae8..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/Makefile ++++ /dev/null +@@ -1,6 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +- +-subdir-y += fsl +- +-dtstree := $(srctree)/$(src) +-dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts)) +diff --git a/scripts/dtc/include-prefixes/powerpc/a3m071.dts b/scripts/dtc/include-prefixes/powerpc/a3m071.dts +deleted file mode 100644 +index 034cfd8aa95b..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/a3m071.dts ++++ /dev/null +@@ -1,138 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * a3m071 board Device Tree Source +- * +- * Copyright 2012 Stefan Roese +- * +- * Copyright (C) 2011 DENX Software Engineering GmbH +- * Heiko Schocher +- * +- * Copyright (C) 2007 Semihalf +- * Marian Balakowicz +- */ +- +-/include/ "mpc5200b.dtsi" +- +-&gpt0 { fsl,has-wdt; }; +- +-/ { +- model = "anonymous,a3m071"; +- compatible = "anonymous,a3m071"; +- +- soc5200@f0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc5200b-immr"; +- ranges = <0 0xf0000000 0x0000c000>; +- reg = <0xf0000000 0x00000100>; +- bus-frequency = <0>; /* From boot loader */ +- system-frequency = <0>; /* From boot loader */ +- +- spi@f00 { +- status = "disabled"; +- }; +- +- usb: usb@1000 { +- status = "disabled"; +- }; +- +- psc@2000 { +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- reg = <0x2000 0x100>; +- interrupts = <2 1 0>; +- }; +- +- psc@2200 { +- status = "disabled"; +- }; +- +- psc@2400 { +- status = "disabled"; +- }; +- +- psc@2600 { +- status = "disabled"; +- }; +- +- psc@2800 { +- status = "disabled"; +- }; +- +- psc@2c00 { // PSC6 +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- reg = <0x2c00 0x100>; +- interrupts = <2 4 0>; +- }; +- +- ethernet@3000 { +- phy-handle = <&phy0>; +- }; +- +- mdio@3000 { +- phy0: ethernet-phy@3 { +- reg = <0x03>; +- }; +- }; +- +- ata@3a00 { +- status = "disabled"; +- }; +- +- i2c@3d00 { +- status = "disabled"; +- }; +- +- i2c@3d40 { +- status = "disabled"; +- }; +- }; +- +- localbus { +- compatible = "fsl,mpc5200b-lpb","simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0 0xfc000000 0x02000000 +- 3 0 0xe9000000 0x00080000 +- 5 0 0xe8000000 0x00010000>; +- +- flash@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0 0x0 0x02000000>; +- compatible = "cfi-flash"; +- bank-width = <2>; +- partition@0 { +- label = "u-boot"; +- reg = <0x00000000 0x00040000>; +- read-only; +- }; +- partition@40000 { +- label = "env"; +- reg = <0x00040000 0x00020000>; +- }; +- partition@60000 { +- label = "dtb"; +- reg = <0x00060000 0x00020000>; +- }; +- partition@80000 { +- label = "kernel"; +- reg = <0x00080000 0x00500000>; +- }; +- partition@580000 { +- label = "root"; +- reg = <0x00580000 0x00A80000>; +- }; +- }; +- +- fpga@3,0 { +- compatible = "anonymous,a3m071-fpga"; +- reg = <3 0x0 0x00080000 +- 5 0x0 0x00010000>; +- interrupts = <0 0 3>; /* level low */ +- }; +- }; +- +- pci@f0000d00 { +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/a4m072.dts b/scripts/dtc/include-prefixes/powerpc/a4m072.dts +deleted file mode 100644 +index a9cef5726422..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/a4m072.dts ++++ /dev/null +@@ -1,147 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * a4m072 board Device Tree Source +- * +- * Copyright (C) 2011 DENX Software Engineering GmbH +- * Heiko Schocher +- * +- * Copyright (C) 2007 Semihalf +- * Marian Balakowicz +- */ +- +-/include/ "mpc5200b.dtsi" +- +-&gpt0 { fsl,has-wdt; }; +-&gpt3 { gpio-controller; }; +-&gpt4 { gpio-controller; }; +-&gpt5 { gpio-controller; }; +- +-/ { +- model = "anonymous,a4m072"; +- compatible = "anonymous,a4m072"; +- +- soc5200@f0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc5200b-immr"; +- ranges = <0 0xf0000000 0x0000c000>; +- reg = <0xf0000000 0x00000100>; +- bus-frequency = <0>; /* From boot loader */ +- system-frequency = <0>; /* From boot loader */ +- +- cdm@200 { +- fsl,init-ext-48mhz-en = <0x0>; +- fsl,init-fd-enable = <0x01>; +- fsl,init-fd-counters = <0x3333>; +- }; +- +- spi@f00 { +- status = "disabled"; +- }; +- +- psc@2000 { +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- reg = <0x2000 0x100>; +- interrupts = <2 1 0>; +- }; +- +- psc@2200 { +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- reg = <0x2200 0x100>; +- interrupts = <2 2 0>; +- }; +- +- psc@2400 { +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- reg = <0x2400 0x100>; +- interrupts = <2 3 0>; +- }; +- +- psc@2600 { +- status = "disabled"; +- }; +- +- psc@2800 { +- status = "disabled"; +- }; +- +- psc@2c00 { +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- reg = <0x2c00 0x100>; +- interrupts = <2 4 0>; +- }; +- +- ethernet@3000 { +- phy-handle = <&phy0>; +- }; +- +- mdio@3000 { +- phy0: ethernet-phy@1f { +- reg = <0x1f>; +- interrupts = <1 2 0>; /* IRQ 2 active low */ +- }; +- }; +- +- i2c@3d00 { +- status = "disabled"; +- }; +- +- i2c@3d40 { +- hwmon@2e { +- compatible = "nsc,lm87"; +- reg = <0x2e>; +- }; +- rtc@51 { +- compatible = "nxp,rtc8564"; +- reg = <0x51>; +- }; +- }; +- }; +- +- localbus { +- compatible = "fsl,mpc5200b-lpb","simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0 0xfe000000 0x02000000 +- 1 0 0x62000000 0x00400000 +- 2 0 0x64000000 0x00200000 +- 3 0 0x66000000 0x01000000 +- 6 0 0x68000000 0x01000000 +- 7 0 0x6a000000 0x00000004>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x02000000>; +- bank-width = <2>; +- #size-cells = <1>; +- #address-cells = <1>; +- }; +- sram0@1,0 { +- compatible = "mtd-ram"; +- reg = <1 0x00000 0x00400000>; +- bank-width = <2>; +- }; +- }; +- +- pci@f0000d00 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- compatible = "fsl,mpc5200-pci"; +- reg = <0xf0000d00 0x100>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x16 */ +- 0xc000 0 0 1 &mpc5200_pic 1 3 3 +- 0xc000 0 0 2 &mpc5200_pic 1 3 3 +- 0xc000 0 0 3 &mpc5200_pic 1 3 3 +- 0xc000 0 0 4 &mpc5200_pic 1 3 3>; +- clock-frequency = <0>; /* From boot loader */ +- interrupts = <2 8 0 2 9 0 2 10 0>; +- bus-range = <0 0>; +- ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000 +- 0x02000000 0 0x90000000 0x90000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/ac14xx.dts b/scripts/dtc/include-prefixes/powerpc/ac14xx.dts +deleted file mode 100644 +index 5d8877e1f4ad..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/ac14xx.dts ++++ /dev/null +@@ -1,395 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Device Tree Source for the MPC5121e based ac14xx board +- * +- * Copyright 2012 Anatolij Gustschin +- */ +- +- +-#include "mpc5121.dtsi" +- +-/ { +- model = "ac14xx"; +- compatible = "ifm,ac14xx", "fsl,mpc5121"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial7; +- spi4 = &spi4; +- spi5 = &spi5; +- }; +- +- cpus { +- PowerPC,5121@0 { +- timebase-frequency = <40000000>; /* 40 MHz (csb/4) */ +- bus-frequency = <160000000>; /* 160 MHz csb bus */ +- clock-frequency = <400000000>; /* 400 MHz ppc core */ +- }; +- }; +- +- memory { +- reg = <0x00000000 0x10000000>; /* 256MB at 0 */ +- }; +- +- nfc@40000000 { +- status = "disabled"; +- }; +- +- localbus@80000020 { +- ranges = <0x0 0x0 0xfc000000 0x04000000 /* CS0: NOR flash */ +- 0x1 0x0 0xe0000000 0x00010000 /* CS1: FRAM */ +- 0x2 0x0 0xe0100000 0x00080000 /* CS2: asi1 */ +- 0x3 0x0 0xe0300000 0x00020000 /* CS3: comm */ +- 0x5 0x0 0xe0400000 0x00010000 /* CS5: safety */ +- 0x6 0x0 0xe0200000 0x00080000>; /* CS6: asi2 */ +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0x00000000 0x04000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- bank-width = <2>; +- device-width = <2>; +- +- partition@0 { +- label = "dtb-kernel-production"; +- reg = <0x00000000 0x00400000>; +- }; +- partition@1 { +- label = "filesystem-production"; +- reg = <0x00400000 0x03400000>; +- }; +- +- partition@2 { +- label = "recovery"; +- reg = <0x03800000 0x00700000>; +- }; +- +- partition@3 { +- label = "uboot-code"; +- reg = <0x03f00000 0x00040000>; +- }; +- partition@4 { +- label = "uboot-env1"; +- reg = <0x03f40000 0x00020000>; +- }; +- partition@5 { +- label = "uboot-env2"; +- reg = <0x03f60000 0x00020000>; +- }; +- }; +- +- fram@1,0 { +- compatible = "ifm,ac14xx-fram", "linux,uio-pdrv-genirq"; +- reg = <1 0x00000000 0x00010000>; +- }; +- +- asi@2,0 { +- /* masters mapping: CS, CS offset, size */ +- reg = <2 0x00000000 0x00080000 +- 6 0x00000000 0x00080000>; +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ifm,ac14xx-asi-fpga"; +- gpios = < +- &gpio_pic 26 0 /* prog */ +- &gpio_pic 27 0 /* done */ +- &gpio_pic 10 0 /* reset */ +- >; +- +- master@1 { +- interrupts = <20 0x2>; +- interrupt-parent = <&gpio_pic>; +- chipselect = <2 0x00009000 0x00009100>; +- label = "AS-i master 1"; +- }; +- +- master@2 { +- interrupts = <21 0x2>; +- interrupt-parent = <&gpio_pic>; +- chipselect = <6 0x00009000 0x00009100>; +- label = "AS-i master 2"; +- }; +- }; +- +- netx@3,0 { +- compatible = "ifm,netx"; +- reg = <0x3 0x00000000 0x00020000>; +- chipselect = <3 0x00101140 0x00203100>; +- interrupts = <17 0x8>; +- gpios = <&gpio_pic 15 0>; +- }; +- +- safety@5,0 { +- compatible = "ifm,safety"; +- reg = <0x5 0x00000000 0x00010000>; +- chipselect = <5 0x00009000 0x00009100>; +- interrupts = <22 0x2>; +- interrupt-parent = <&gpio_pic>; +- gpios = < +- &gpio_pic 12 0 /* prog */ +- &gpio_pic 11 0 /* done */ +- >; +- }; +- }; +- +- clocks { +- osc { +- clock-frequency = <25000000>; +- }; +- }; +- +- soc@80000000 { +- bus-frequency = <80000000>; /* 80 MHz ips bus */ +- +- clock@f00 { +- compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock"; +- }; +- +- /* +- * GPIO PIC: +- * interrupts cell = +- * sense == 8: Level, low assertion +- * sense == 2: Edge, high-to-low change +- */ +- gpio_pic: gpio@1100 { +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- sdhc@1500 { +- cd-gpios = <&gpio_pic 23 0>; /* card detect */ +- wp-gpios = <&gpio_pic 24 0>; /* write protect */ +- wp-inverted; /* WP active high */ +- }; +- +- i2c@1700 { +- /* use Fast-mode */ +- clock-frequency = <400000>; +- +- at24@30 { +- compatible = "atmel,24c01"; +- reg = <0x30>; +- }; +- +- at24@31 { +- compatible = "atmel,24c01"; +- reg = <0x31>; +- }; +- +- temp@48 { +- compatible = "ad,ad7414"; +- reg = <0x48>; +- }; +- +- at24@50 { +- compatible = "atmel,24c01"; +- reg = <0x50>; +- }; +- +- at24@51 { +- compatible = "atmel,24c01"; +- reg = <0x51>; +- }; +- +- at24@52 { +- compatible = "atmel,24c01"; +- reg = <0x52>; +- }; +- +- at24@53 { +- compatible = "atmel,24c01"; +- reg = <0x53>; +- }; +- +- at24@54 { +- compatible = "atmel,24c01"; +- reg = <0x54>; +- }; +- +- at24@55 { +- compatible = "atmel,24c01"; +- reg = <0x55>; +- }; +- +- at24@56 { +- compatible = "atmel,24c01"; +- reg = <0x56>; +- }; +- +- at24@57 { +- compatible = "atmel,24c01"; +- reg = <0x57>; +- }; +- +- rtc@68 { +- compatible = "st,m41t00"; +- reg = <0x68>; +- }; +- }; +- +- axe_pic: axe-base@2000 { +- compatible = "fsl,mpc5121-axe-base"; +- reg = <0x2000 0x100>; +- interrupts = <42 0x8>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- axe-app { +- compatible = "fsl,mpc5121-axe-app"; +- interrupt-parent = <&axe_pic>; +- interrupts = < +- /* soft interrupts */ +- 0 0x0 1 0x0 2 0x0 3 0x0 +- 4 0x0 5 0x0 6 0x0 7 0x0 +- /* fifo interrupts */ +- 8 0x0 9 0x0 10 0x0 11 0x0 +- >; +- }; +- +- display@2100 { +- edid = [00 FF FF FF FF FF FF 00 14 94 00 00 00 00 00 00 +- 0A 12 01 03 80 1C 23 78 CA 88 FF 94 52 54 8E 27 +- 1E 4C 50 00 00 00 01 01 01 01 01 01 01 01 01 01 +- 01 01 01 01 01 01 FB 00 B0 14 00 DC 05 00 08 04 +- 21 00 1C 23 00 00 00 18 00 00 00 FD 00 38 3C 1F +- 3C 01 0A 20 20 20 20 20 20 20 00 00 00 FC 00 45 +- 54 30 31 38 30 30 33 44 4D 55 0A 0A 00 00 00 10 +- 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D5]; +- }; +- +- can@2300 { +- status = "disabled"; +- }; +- +- can@2380 { +- status = "disabled"; +- }; +- +- viu@2400 { +- status = "disabled"; +- }; +- +- mdio@2800 { +- phy0: ethernet-phy@1f { +- compatible = "smsc,lan8700"; +- reg = <0x1f>; +- }; +- }; +- +- enet: ethernet@2800 { +- phy-handle = <&phy0>; +- }; +- +- usb@3000 { +- status = "disabled"; +- }; +- +- usb@4000 { +- status = "disabled"; +- }; +- +- /* PSC3 serial port A, aka ttyPSC0 */ +- serial0: psc@11300 { +- compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; +- fsl,rx-fifo-size = <512>; +- fsl,tx-fifo-size = <512>; +- }; +- +- /* PSC4 in SPI mode */ +- spi4: psc@11400 { +- compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc"; +- fsl,rx-fifo-size = <768>; +- fsl,tx-fifo-size = <768>; +- #address-cells = <1>; +- #size-cells = <0>; +- num-cs = <1>; +- cs-gpios = <&gpio_pic 25 0>; +- +- flash: m25p128@0 { +- compatible = "st,m25p128"; +- spi-max-frequency = <20000000>; +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "spi-flash0"; +- reg = <0x00000000 0x01000000>; +- }; +- }; +- }; +- +- /* PSC5 in SPI mode */ +- spi5: psc@11500 { +- compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc"; +- fsl,mode = "spi-master"; +- fsl,rx-fifo-size = <128>; +- fsl,tx-fifo-size = <128>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- lcd@0 { +- compatible = "ilitek,ili922x"; +- reg = <0>; +- spi-max-frequency = <100000>; +- spi-cpol; +- spi-cpha; +- }; +- }; +- +- /* PSC7 serial port C, aka ttyPSC2 */ +- serial7: psc@11700 { +- compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; +- fsl,rx-fifo-size = <512>; +- fsl,tx-fifo-size = <512>; +- }; +- +- matrix_keypad@0 { +- compatible = "gpio-matrix-keypad"; +- debounce-delay-ms = <5>; +- col-scan-delay-us = <1>; +- gpio-activelow; +- col-gpios-binary; +- col-switch-delay-ms = <200>; +- +- col-gpios = <&gpio_pic 1 0>; /* pin1 */ +- +- row-gpios = <&gpio_pic 2 0 /* pin2 */ +- &gpio_pic 3 0 /* pin3 */ +- &gpio_pic 4 0>; /* pin4 */ +- +- linux,keymap = <0x0000006e /* FN LEFT */ +- 0x01000067 /* UP */ +- 0x02000066 /* FN RIGHT */ +- 0x00010069 /* LEFT */ +- 0x0101006a /* DOWN */ +- 0x0201006c>; /* RIGHT */ +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- backlight { +- label = "backlight"; +- gpios = <&gpio_pic 0 0>; +- default-state = "keep"; +- }; +- green { +- label = "green"; +- gpios = <&gpio_pic 18 0>; +- default-state = "keep"; +- }; +- red { +- label = "red"; +- gpios = <&gpio_pic 19 0>; +- default-state = "keep"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/acadia.dts b/scripts/dtc/include-prefixes/powerpc/acadia.dts +deleted file mode 100644 +index deb52e41ab84..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/acadia.dts ++++ /dev/null +@@ -1,224 +0,0 @@ +-/* +- * Device Tree Source for AMCC Acadia (405EZ) +- * +- * Copyright IBM Corp. 2008 +- * +- * This file is licensed under the terms of the GNU General Public License +- * version 2. This program is licensed "as is" without any warranty of any +- * kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "amcc,acadia"; +- compatible = "amcc,acadia"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- serial0 = &UART0; +- serial1 = &UART1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,405EZ"; +- reg = <0x0>; +- clock-frequency = <0>; /* Filled in by wrapper */ +- timebase-frequency = <0>; /* Filled in by wrapper */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <16384>; +- d-cache-size = <16384>; +- dcr-controller; +- dcr-access-method = "native"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; /* Filled in by wrapper */ +- }; +- +- UIC0: interrupt-controller { +- compatible = "ibm,uic-405ez", "ibm,uic"; +- interrupt-controller; +- dcr-reg = <0x0c0 0x009>; +- cell-index = <0>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- plb { +- compatible = "ibm,plb-405ez", "ibm,plb3"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; /* Filled in by wrapper */ +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-405ez", "ibm,mcmal"; +- dcr-reg = <0x380 0x62>; +- num-tx-chans = <1>; +- num-rx-chans = <1>; +- interrupt-parent = <&UIC0>; +- /* 405EZ has only 3 interrupts to the UIC, as +- * SERR, TXDE, and RXDE are or'd together into +- * one UIC bit +- */ +- interrupts = < +- 0x13 0x4 /* TXEOB */ +- 0x15 0x4 /* RXEOB */ +- 0x12 0x4 /* SERR, TXDE, RXDE */>; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-405ez", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- dcr-reg = <0x0a 0x05>; +- clock-frequency = <0>; /* Filled in by wrapper */ +- +- UART0: serial@ef600300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600300 0x8>; +- virtual-reg = <0xef600300>; +- clock-frequency = <0>; /* Filled in by wrapper */ +- current-speed = <115200>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x5 0x4>; +- }; +- +- UART1: serial@ef600400 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600400 0x8>; +- clock-frequency = <0>; /* Filled in by wrapper */ +- current-speed = <115200>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x6 0x4>; +- }; +- +- IIC: i2c@ef600500 { +- compatible = "ibm,iic-405ez", "ibm,iic"; +- reg = <0xef600500 0x11>; +- interrupt-parent = <&UIC0>; +- interrupts = <0xa 0x4>; +- }; +- +- GPIO0: gpio@ef600700 { +- compatible = "ibm,gpio-405ez"; +- reg = <0xef600700 0x20>; +- }; +- +- GPIO1: gpio@ef600800 { +- compatible = "ibm,gpio-405ez"; +- reg = <0xef600800 0x20>; +- }; +- +- EMAC0: ethernet@ef600900 { +- device_type = "network"; +- compatible = "ibm,emac-405ez", "ibm,emac"; +- interrupt-parent = <&UIC0>; +- interrupts = < +- 0x10 0x4 /* Ethernet */ +- 0x11 0x4 /* Ethernet Wake up */>; +- local-mac-address = [000000000000]; /* Filled in by wrapper */ +- reg = <0xef600900 0x70>; +- mal-device = <&MAL0>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <1500>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "mii"; +- phy-map = <0x0>; +- }; +- +- CAN0: can@ef601000 { +- compatible = "amcc,can-405ez"; +- reg = <0xef601000 0x620>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x7 0x4>; +- }; +- +- CAN1: can@ef601800 { +- compatible = "amcc,can-405ez"; +- reg = <0xef601800 0x620>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x8 0x4>; +- }; +- +- cameleon@ef602000 { +- compatible = "amcc,cameleon-405ez"; +- reg = <0xef602000 0x800>; +- interrupt-parent = <&UIC0>; +- interrupts = <0xb 0x4 0xc 0x4>; +- }; +- +- ieee1588@ef602800 { +- compatible = "amcc,ieee1588-405ez"; +- reg = <0xef602800 0x60>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x4 0x4>; +- /* This thing is a bit weird. It has it's own UIC +- * that it uses to generate snapshot triggers. We +- * don't really support this device yet, and it needs +- * work to figure this out. +- */ +- dcr-reg = <0xe0 0x9>; +- }; +- +- usb@ef603000 { +- compatible = "ohci-be"; +- reg = <0xef603000 0x80>; +- interrupt-parent = <&UIC0>; +- interrupts = <0xd 0x4 0xe 0x4>; +- }; +- +- dac@ef603300 { +- compatible = "amcc,dac-405ez"; +- reg = <0xef603300 0x40>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x18 0x4>; +- }; +- +- adc@ef603400 { +- compatible = "amcc,adc-405ez"; +- reg = <0xef603400 0x40>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x17 0x4>; +- }; +- +- spi@ef603500 { +- compatible = "amcc,spi-405ez"; +- reg = <0xef603500 0x100>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x9 0x4>; +- }; +- }; +- +- EBC0: ebc { +- compatible = "ibm,ebc-405ez", "ibm,ebc"; +- dcr-reg = <0x12 0x2>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; /* Filled in by wrapper */ +- }; +- }; +- +- chosen { +- stdout-path = "/plb/opb/serial@ef600300"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/adder875-redboot.dts b/scripts/dtc/include-prefixes/powerpc/adder875-redboot.dts +deleted file mode 100644 +index b51c97abface..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/adder875-redboot.dts ++++ /dev/null +@@ -1,179 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Device Tree Source for MPC885 ADS running RedBoot +- * +- * Copyright 2006 MontaVista Software, Inc. +- * Copyright 2007 Freescale Semiconductor, Inc. +- */ +- +-/dts-v1/; +-/ { +- model = "Analogue & Micro Adder MPC875"; +- compatible = "analogue-and-micro,adder875"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- console = &console; +- ethernet0 = ð0; +- ethernet1 = ð1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,875@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <16>; +- i-cache-line-size = <16>; +- d-cache-size = <8192>; +- i-cache-size = <8192>; +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- interrupts = <15 2>; // decrementer interrupt +- interrupt-parent = <&PIC>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0 0x01000000>; +- }; +- +- localbus@fa200100 { +- compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus", +- "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- reg = <0xfa200100 0x40>; +- +- ranges = < +- 0 0 0xfe000000 0x00800000 +- 2 0 0xfa100000 0x00008000 +- >; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x800000>; +- bank-width = <2>; +- device-width = <2>; +- }; +- }; +- +- soc@fa200000 { +- compatible = "fsl,mpc875-immr", "fsl,pq1-soc", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xfa200000 0x00004000>; +- +- // Temporary until code stops depending on it. +- device_type = "soc"; +- +- // Temporary until get_immrbase() is fixed. +- reg = <0xfa200000 0x4000>; +- +- mdio@e00 { +- compatible = "fsl,mpc875-fec-mdio", "fsl,pq1-fec-mdio"; +- reg = <0xe00 0x188>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- PHY0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- PHY1: ethernet-phy@1 { +- reg = <1>; +- }; +- }; +- +- eth0: ethernet@e00 { +- device_type = "network"; +- compatible = "fsl,mpc875-fec-enet", +- "fsl,pq1-fec-enet"; +- reg = <0xe00 0x188>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <3 1>; +- interrupt-parent = <&PIC>; +- phy-handle = <&PHY0>; +- linux,network-index = <0>; +- }; +- +- eth1: ethernet@1e00 { +- device_type = "network"; +- compatible = "fsl,mpc875-fec-enet", +- "fsl,pq1-fec-enet"; +- reg = <0x1e00 0x188>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <7 1>; +- interrupt-parent = <&PIC>; +- phy-handle = <&PHY1>; +- linux,network-index = <1>; +- }; +- +- PIC: interrupt-controller@0 { +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0 0x24>; +- compatible = "fsl,mpc875-pic", "fsl,pq1-pic"; +- }; +- +- cpm@9c0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc875-cpm", "fsl,cpm1", "simple-bus"; +- interrupts = <0>; // cpm error interrupt +- interrupt-parent = <&CPM_PIC>; +- reg = <0x9c0 0x40>; +- ranges; +- +- muram { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x2000 0x2000>; +- +- data@0 { +- compatible = "fsl,cpm-muram-data"; +- reg = <0 0x1c00>; +- }; +- }; +- +- brg@9f0 { +- compatible = "fsl,mpc875-brg", +- "fsl,cpm1-brg", +- "fsl,cpm-brg"; +- clock-frequency = <50000000>; +- reg = <0x9f0 0x10>; +- }; +- +- CPM_PIC: interrupt-controller@930 { +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupts = <5 2 0 2>; +- interrupt-parent = <&PIC>; +- reg = <0x930 0x20>; +- compatible = "fsl,mpc875-cpm-pic", +- "fsl,cpm1-pic"; +- }; +- +- console: serial@a80 { +- device_type = "serial"; +- compatible = "fsl,mpc875-smc-uart", +- "fsl,cpm1-smc-uart"; +- reg = <0xa80 0x10 0x3e80 0x40>; +- interrupts = <4>; +- interrupt-parent = <&CPM_PIC>; +- fsl,cpm-brg = <1>; +- fsl,cpm-command = <0x0090>; +- current-speed = <115200>; +- }; +- }; +- }; +- +- chosen { +- stdout-path = &console; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/adder875-uboot.dts b/scripts/dtc/include-prefixes/powerpc/adder875-uboot.dts +deleted file mode 100644 +index ec776103f540..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/adder875-uboot.dts ++++ /dev/null +@@ -1,178 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Device Tree Source for MPC885 ADS running U-Boot +- * +- * Copyright 2006 MontaVista Software, Inc. +- * Copyright 2007 Freescale Semiconductor, Inc. +- */ +- +-/dts-v1/; +-/ { +- model = "Analogue & Micro Adder MPC875"; +- compatible = "analogue-and-micro,adder875"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- console = &console; +- ethernet0 = ð0; +- ethernet1 = ð1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,875@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <16>; +- i-cache-line-size = <16>; +- d-cache-size = <8192>; +- i-cache-size = <8192>; +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- interrupts = <15 2>; // decrementer interrupt +- interrupt-parent = <&PIC>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0 0x01000000>; +- }; +- +- localbus@ff000100 { +- compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus", +- "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- reg = <0xff000100 0x40>; +- +- ranges = < +- 0 0 0xfe000000 0x01000000 +- >; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x800000>; +- bank-width = <2>; +- device-width = <2>; +- }; +- }; +- +- soc@ff000000 { +- compatible = "fsl,mpc875-immr", "fsl,pq1-soc", "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0xff000000 0x00004000>; +- +- // Temporary until code stops depending on it. +- device_type = "soc"; +- +- // Temporary until get_immrbase() is fixed. +- reg = <0xff000000 0x4000>; +- +- mdio@e00 { +- compatible = "fsl,mpc875-fec-mdio", "fsl,pq1-fec-mdio"; +- reg = <0xe00 0x188>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- PHY0: ethernet-phy@0 { +- reg = <0>; +- }; +- +- PHY1: ethernet-phy@1 { +- reg = <1>; +- }; +- }; +- +- eth0: ethernet@e00 { +- device_type = "network"; +- compatible = "fsl,mpc875-fec-enet", +- "fsl,pq1-fec-enet"; +- reg = <0xe00 0x188>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <3 1>; +- interrupt-parent = <&PIC>; +- phy-handle = <&PHY0>; +- linux,network-index = <0>; +- }; +- +- eth1: ethernet@1e00 { +- device_type = "network"; +- compatible = "fsl,mpc875-fec-enet", +- "fsl,pq1-fec-enet"; +- reg = <0x1e00 0x188>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <7 1>; +- interrupt-parent = <&PIC>; +- phy-handle = <&PHY1>; +- linux,network-index = <1>; +- }; +- +- PIC: interrupt-controller@0 { +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0 0x24>; +- compatible = "fsl,mpc875-pic", "fsl,pq1-pic"; +- }; +- +- cpm@9c0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc875-cpm", "fsl,cpm1", "simple-bus"; +- interrupts = <0>; // cpm error interrupt +- interrupt-parent = <&CPM_PIC>; +- reg = <0x9c0 0x40>; +- ranges; +- +- muram { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x2000 0x2000>; +- +- data@0 { +- compatible = "fsl,cpm-muram-data"; +- reg = <0 0x1c00>; +- }; +- }; +- +- brg@9f0 { +- compatible = "fsl,mpc875-brg", +- "fsl,cpm1-brg", +- "fsl,cpm-brg"; +- clock-frequency = <50000000>; +- reg = <0x9f0 0x10>; +- }; +- +- CPM_PIC: interrupt-controller@930 { +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupts = <5 2 0 2>; +- interrupt-parent = <&PIC>; +- reg = <0x930 0x20>; +- compatible = "fsl,mpc875-cpm-pic", +- "fsl,cpm1-pic"; +- }; +- +- console: serial@a80 { +- device_type = "serial"; +- compatible = "fsl,mpc875-smc-uart", +- "fsl,cpm1-smc-uart"; +- reg = <0xa80 0x10 0x3e80 0x40>; +- interrupts = <4>; +- interrupt-parent = <&CPM_PIC>; +- fsl,cpm-brg = <1>; +- fsl,cpm-command = <0x0090>; +- current-speed = <115200>; +- }; +- }; +- }; +- +- chosen { +- stdout-path = &console; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/akebono.dts b/scripts/dtc/include-prefixes/powerpc/akebono.dts +deleted file mode 100644 +index df18f8dc4642..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/akebono.dts ++++ /dev/null +@@ -1,415 +0,0 @@ +-/* +- * Device Tree Source for IBM Embedded PPC 476 Platform +- * +- * Copyright © 2013 Tony Breeds IBM Corporation +- * Copyright © 2013 Alistair Popple IBM Corporation +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/memreserve/ 0x01f00000 0x00100000; // spin table +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- model = "ibm,akebono"; +- compatible = "ibm,akebono", "ibm,476gtr"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- serial0 = &UART0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,476"; +- reg = <0>; +- clock-frequency = <1600000000>; // 1.6 GHz +- timebase-frequency = <100000000>; // 100Mhz +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- status = "okay"; +- }; +- cpu@1 { +- device_type = "cpu"; +- model = "PowerPC,476"; +- reg = <1>; +- clock-frequency = <1600000000>; // 1.6 GHz +- timebase-frequency = <100000000>; // 100Mhz +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- status = "disabled"; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x01f00000>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x0>; // filled in by zImage +- }; +- +- MPIC: interrupt-controller { +- compatible = "chrp,open-pic"; +- interrupt-controller; +- dcr-reg = <0xffc00000 0x00040000>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- single-cpu-affinity; +- }; +- +- plb { +- compatible = "ibm,plb6"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- clock-frequency = <200000000>; // 200Mhz +- +- HSTA0: hsta@310000e0000 { +- compatible = "ibm,476gtr-hsta-msi", "ibm,hsta-msi"; +- reg = <0x310 0x000e0000 0x0 0xf0>; +- interrupt-parent = <&MPIC>; +- interrupts = <108 0 +- 109 0 +- 110 0 +- 111 0 +- 112 0 +- 113 0 +- 114 0 +- 115 0 +- 116 0 +- 117 0 +- 118 0 +- 119 0 +- 120 0 +- 121 0 +- 122 0 +- 123 0>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-476gtr", "ibm,mcmal2"; +- dcr-reg = <0xc0000000 0x062>; +- num-tx-chans = <1>; +- num-rx-chans = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-parent = <&MPIC>; +- interrupts = < /*TXEOB*/ 77 0x4 +- /*RXEOB*/ 78 0x4 +- /*SERR*/ 76 0x4 +- /*TXDE*/ 79 0x4 +- /*RXDE*/ 80 0x4>; +- }; +- +- SATA0: sata@30000010000 { +- compatible = "ibm,476gtr-ahci"; +- reg = <0x300 0x00010000 0x0 0x10000>; +- interrupt-parent = <&MPIC>; +- interrupts = <93 2>; +- }; +- +- EHCI0: ehci@30010000000 { +- compatible = "ibm,476gtr-ehci", "generic-ehci"; +- reg = <0x300 0x10000000 0x0 0x10000>; +- interrupt-parent = <&MPIC>; +- interrupts = <85 2>; +- }; +- +- SD0: sd@30000000000 { +- compatible = "ibm,476gtr-sdhci", "generic-sdhci"; +- reg = <0x300 0x00000000 0x0 0x10000>; +- interrupts = <91 2>; +- interrupt-parent = <&MPIC>; +- }; +- +- OHCI0: ohci@30010010000 { +- compatible = "ibm,476gtr-ohci", "generic-ohci"; +- reg = <0x300 0x10010000 0x0 0x10000>; +- interrupt-parent = <&MPIC>; +- interrupts = <89 1>; +- }; +- +- OHCI1: ohci@30010020000 { +- compatible = "ibm,476gtr-ohci", "generic-ohci"; +- reg = <0x300 0x10020000 0x0 0x10000>; +- interrupt-parent = <&MPIC>; +- interrupts = <88 1>; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-4xx", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- /* Wish there was a nicer way of specifying a full +- * 32-bit range +- */ +- ranges = <0x00000000 0x0000033f 0x00000000 0x80000000 +- 0x80000000 0x0000033f 0x80000000 0x80000000>; +- clock-frequency = <100000000>; +- +- RGMII0: emac-rgmii-wol@50004 { +- compatible = "ibm,rgmii-wol-476gtr", "ibm,rgmii-wol"; +- reg = <0x50004 0x00000008>; +- has-mdio; +- }; +- +- EMAC0: ethernet@30000 { +- device_type = "network"; +- compatible = "ibm,emac-476gtr", "ibm,emac4sync"; +- interrupt-parent = <&EMAC0>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0x30000 0x78>; +- +- /* local-mac-address will normally be added by +- * the wrapper. If your device doesn't support +- * passing data to the wrapper (in the form +- * local-mac-addr=) then you will need +- * to set it manually here. */ +- //local-mac-address = [000000000000]; +- +- mal-device = <&MAL0>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- rgmii-wol-device = <&RGMII0>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- +- UART0: serial@10000 { +- device_type = "serial"; +- compatible = "ns16750", "ns16550"; +- reg = <0x10000 0x00000008>; +- virtual-reg = <0xe8010000>; +- clock-frequency = <1851851>; +- current-speed = <38400>; +- interrupt-parent = <&MPIC>; +- interrupts = <39 2>; +- }; +- +- IIC0: i2c@0 { +- compatible = "ibm,iic-476gtr", "ibm,iic"; +- reg = <0x0 0x00000020>; +- interrupt-parent = <&MPIC>; +- interrupts = <37 2>; +- #address-cells = <1>; +- #size-cells = <0>; +- rtc@68 { +- compatible = "st,m41t80", "m41st85"; +- reg = <0x68>; +- }; +- }; +- +- IIC1: i2c@100 { +- compatible = "ibm,iic-476gtr", "ibm,iic"; +- reg = <0x100 0x00000020>; +- interrupt-parent = <&MPIC>; +- interrupts = <38 2>; +- #address-cells = <1>; +- #size-cells = <0>; +- avr@58 { +- compatible = "ibm,akebono-avr"; +- reg = <0x58>; +- }; +- }; +- +- FPGA0: fpga@ebc00000 { +- compatible = "ibm,akebono-fpga"; +- reg = <0xebc00000 0x8>; +- }; +- }; +- +- PCIE0: pcie@10100000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex"; +- primary; +- port = <0x0>; /* port number */ +- reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */ +- 0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */ +- dcr-reg = <0xc0 0x20>; +- +-// pci_space < pci_addr > < cpu_addr > < size > +- ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000 +- 0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>; +- +- /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI +- * PCI devices must be able to write to the HSTA module. +- */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>; +- +- /* This drives busses 0 to 0xf */ +- bus-range = <0x0 0xf>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &MPIC 45 0x2 /* int A */ +- 0x0 0x0 0x0 0x2 &MPIC 46 0x2 /* int B */ +- 0x0 0x0 0x0 0x3 &MPIC 47 0x2 /* int C */ +- 0x0 0x0 0x0 0x4 &MPIC 48 0x2 /* int D */>; +- }; +- +- PCIE1: pcie@20100000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex"; +- primary; +- port = <0x1>; /* port number */ +- reg = <0x00000201 0x00000000 0x0 0x10000000 /* Config space access */ +- 0x00000200 0x00000000 0x0 0x00001000>; /* UTL Registers space access */ +- dcr-reg = <0x100 0x20>; +- +-// pci_space < pci_addr > < cpu_addr > < size > +- ranges = <0x02000000 0x00000000 0x80000000 0x00000210 0x80000000 0x0 0x80000000 +- 0x01000000 0x0 0x0 0x00000240 0x0 0x0 0x00010000>; +- +- /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI +- * PCI devices must be able to write to the HSTA module. +- */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>; +- +- /* This drives busses 0 to 0xf */ +- bus-range = <0x0 0xf>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &MPIC 53 0x2 /* int A */ +- 0x0 0x0 0x0 0x2 &MPIC 54 0x2 /* int B */ +- 0x0 0x0 0x0 0x3 &MPIC 55 0x2 /* int C */ +- 0x0 0x0 0x0 0x4 &MPIC 56 0x2 /* int D */>; +- }; +- +- PCIE2: pcie@18100000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex"; +- primary; +- port = <0x2>; /* port number */ +- reg = <0x00000181 0x00000000 0x0 0x10000000 /* Config space access */ +- 0x00000180 0x00000000 0x0 0x00001000>; /* UTL Registers space access */ +- dcr-reg = <0xe0 0x20>; +- +-// pci_space < pci_addr > < cpu_addr > < size > +- ranges = <0x02000000 0x00000000 0x80000000 0x00000190 0x80000000 0x0 0x80000000 +- 0x01000000 0x0 0x0 0x000001c0 0x0 0x0 0x00010000>; +- +- /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI +- * PCI devices must be able to write to the HSTA module. +- */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>; +- +- /* This drives busses 0 to 0xf */ +- bus-range = <0x0 0xf>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &MPIC 61 0x2 /* int A */ +- 0x0 0x0 0x0 0x2 &MPIC 62 0x2 /* int B */ +- 0x0 0x0 0x0 0x3 &MPIC 63 0x2 /* int C */ +- 0x0 0x0 0x0 0x4 &MPIC 64 0x2 /* int D */>; +- }; +- +- PCIE3: pcie@28100000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex"; +- primary; +- port = <0x3>; /* port number */ +- reg = <0x00000281 0x00000000 0x0 0x10000000 /* Config space access */ +- 0x00000280 0x00000000 0x0 0x00001000>; /* UTL Registers space access */ +- dcr-reg = <0x120 0x20>; +- +-// pci_space < pci_addr > < cpu_addr > < size > +- ranges = <0x02000000 0x00000000 0x80000000 0x00000290 0x80000000 0x0 0x80000000 +- 0x01000000 0x0 0x0 0x000002c0 0x0 0x0 0x00010000>; +- +- /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI +- * PCI devices must be able to write to the HSTA module. +- */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>; +- +- /* This drives busses 0 to 0xf */ +- bus-range = <0x0 0xf>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &MPIC 69 0x2 /* int A */ +- 0x0 0x0 0x0 0x2 &MPIC 70 0x2 /* int B */ +- 0x0 0x0 0x0 0x3 &MPIC 71 0x2 /* int C */ +- 0x0 0x0 0x0 0x4 &MPIC 72 0x2 /* int D */>; +- }; +- }; +- +- chosen { +- stdout-path = &UART0; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/amigaone.dts b/scripts/dtc/include-prefixes/powerpc/amigaone.dts +deleted file mode 100644 +index 5c68db36d83b..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/amigaone.dts ++++ /dev/null +@@ -1,169 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * AmigaOne Device Tree Source +- * +- * Copyright 2008 Gerhard Pircher (gerhard_pircher@gmx.net) +- */ +- +-/dts-v1/; +- +-/ { +- model = "AmigaOne"; +- compatible = "eyetech,amigaone"; +- coherency-off; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #cpus = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <32768>; // L1, 32K +- i-cache-size = <32768>; // L1, 32K +- timebase-frequency = <0>; // 33.3 MHz, from U-boot +- clock-frequency = <0>; // From U-boot +- bus-frequency = <0>; // From U-boot +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0 0>; // From U-boot +- }; +- +- pci@80000000 { +- device_type = "pci"; +- compatible = "mai-logic,articia-s"; +- bus-frequency = <33333333>; +- bus-range = <0 0xff>; +- ranges = <0x01000000 0 0x00000000 0xfe000000 0 0x00c00000 // PCI I/O +- 0x02000000 0 0x80000000 0x80000000 0 0x7d000000 // PCI memory +- 0x02000000 0 0x00000000 0xfd000000 0 0x01000000>; // PCI alias memory (ISA) +- // Configuration address and data register. +- reg = <0xfec00cf8 4 +- 0xfee00cfc 4>; +- 8259-interrupt-acknowledge = <0xfef00000>; +- // Do not define a interrupt-parent here, if there is no +- // interrupt-map property. +- #address-cells = <3>; +- #size-cells = <2>; +- +- isa@7 { +- device_type = "isa"; +- compatible = "pciclass,0601"; +- vendor-id = <0x00001106>; +- device-id = <0x00000686>; +- revision-id = <0x00000010>; +- class-code = <0x00060100>; +- subsystem-id = <0>; +- subsystem-vendor-id = <0>; +- devsel-speed = <0x00000001>; +- min-grant = <0>; +- max-latency = <0>; +- /* First 4k for I/O at 0x0 on PCI mapped to 0x0 on ISA. */ +- ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00001000>; +- interrupt-parent = <&i8259>; +- #interrupt-cells = <2>; +- #address-cells = <2>; +- #size-cells = <1>; +- +- dma-controller@0 { +- compatible = "pnpPNP,200"; +- reg = <1 0x00000000 0x00000020 +- 1 0x00000080 0x00000010 +- 1 0x000000c0 0x00000020>; +- }; +- +- i8259: interrupt-controller@20 { +- device_type = "interrupt-controller"; +- compatible = "pnpPNP,000"; +- interrupt-controller; +- reg = <1 0x00000020 0x00000002 +- 1 0x000000a0 0x00000002 +- 1 0x000004d0 0x00000002>; +- reserved-interrupts = <2>; +- #interrupt-cells = <2>; +- }; +- +- timer@40 { +- // Also adds pcspkr to platform devices. +- compatible = "pnpPNP,100"; +- reg = <1 0x00000040 0x00000020>; +- }; +- +- 8042@60 { +- device_type = "8042"; +- reg = <1 0x00000060 0x00000001 +- 1 0x00000064 0x00000001>; +- interrupts = <1 3 12 3>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- keyboard@0 { +- compatible = "pnpPNP,303"; +- reg = <0>; +- }; +- +- mouse@1 { +- compatible = "pnpPNP,f03"; +- reg = <1>; +- }; +- }; +- +- rtc@70 { +- compatible = "pnpPNP,b00"; +- reg = <1 0x00000070 0x00000002>; +- interrupts = <8 3>; +- }; +- +- serial@3f8 { +- device_type = "serial"; +- compatible = "pnpPNP,501","pnpPNP,500"; +- reg = <1 0x000003f8 0x00000008>; +- interrupts = <4 3>; +- clock-frequency = <1843200>; +- current-speed = <115200>; +- }; +- +- serial@2f8 { +- device_type = "serial"; +- compatible = "pnpPNP,501","pnpPNP,500"; +- reg = <1 0x000002f8 0x00000008>; +- interrupts = <3 3>; +- clock-frequency = <1843200>; +- current-speed = <115200>; +- }; +- +- parallel@378 { +- device_type = "parallel"; +- // No ECP support for now, otherwise add "pnpPNP,401". +- compatible = "pnpPNP,400"; +- reg = <1 0x00000378 0x00000003 +- 1 0x00000778 0x00000003>; +- }; +- +- fdc@3f0 { +- device_type = "fdc"; +- compatible = "pnpPNP,700"; +- reg = <1 0x000003f0 0x00000008>; +- interrupts = <6 3>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- disk@0 { +- reg = <0>; +- }; +- }; +- }; +- }; +- +- chosen { +- stdout-path = "/pci@80000000/isa@7/serial@3f8"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/arches.dts b/scripts/dtc/include-prefixes/powerpc/arches.dts +deleted file mode 100644 +index 75a376a99892..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/arches.dts ++++ /dev/null +@@ -1,341 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Device Tree Source for AMCC Arches (dual 460GT board) +- * +- * (C) Copyright 2008 Applied Micro Circuits Corporation +- * Victor Gallardo +- * Adam Graham +- * +- * Based on the glacier.dts file +- * Stefan Roese +- * Copyright 2008 DENX Software Engineering +- * +- * See file CREDITS for list of people who contributed to this +- * project. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <2>; +- #size-cells = <1>; +- model = "amcc,arches"; +- compatible = "amcc,arches"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- ethernet1 = &EMAC1; +- ethernet2 = &EMAC2; +- serial0 = &UART0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,460GT"; +- reg = <0x00000000>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- timebase-frequency = <0>; /* Filled in by U-Boot */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- next-level-cache = <&L2C0>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ +- }; +- +- UIC0: interrupt-controller0 { +- compatible = "ibm,uic-460gt","ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-460gt","ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC2: interrupt-controller2 { +- compatible = "ibm,uic-460gt","ibm,uic"; +- interrupt-controller; +- cell-index = <2>; +- dcr-reg = <0x0e0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC3: interrupt-controller3 { +- compatible = "ibm,uic-460gt","ibm,uic"; +- interrupt-controller; +- cell-index = <3>; +- dcr-reg = <0x0f0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- SDR0: sdr { +- compatible = "ibm,sdr-460gt"; +- dcr-reg = <0x00e 0x002>; +- }; +- +- CPR0: cpr { +- compatible = "ibm,cpr-460gt"; +- dcr-reg = <0x00c 0x002>; +- }; +- +- L2C0: l2c { +- compatible = "ibm,l2-cache-460gt", "ibm,l2-cache"; +- dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ +- 0x030 0x008>; /* L2 cache DCR's */ +- cache-line-size = <32>; /* 32 bytes */ +- cache-size = <262144>; /* L2, 256K */ +- interrupt-parent = <&UIC1>; +- interrupts = <11 1>; +- }; +- +- plb { +- compatible = "ibm,plb-460gt", "ibm,plb4"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- SDRAM0: sdram { +- compatible = "ibm,sdram-460gt", "ibm,sdram-405gp"; +- dcr-reg = <0x010 0x002>; +- }; +- +- CRYPTO: crypto@180000 { +- compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto"; +- reg = <4 0x00180000 0x80400>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1d 0x4>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <3>; +- num-rx-chans = <24>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-parent = <&UIC2>; +- interrupts = < /*TXEOB*/ 0x6 0x4 +- /*RXEOB*/ 0x7 0x4 +- /*SERR*/ 0x3 0x4 +- /*TXDE*/ 0x4 0x4 +- /*RXDE*/ 0x5 0x4>; +- desc-base-addr-high = <0x8>; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-460gt", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- EBC0: ebc { +- compatible = "ibm,ebc-460gt", "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- /* ranges property is supplied by U-Boot */ +- interrupts = <0x6 0x4>; +- interrupt-parent = <&UIC1>; +- +- nor_flash@0,0 { +- compatible = "amd,s29gl256n", "cfi-flash"; +- bank-width = <2>; +- reg = <0x00000000 0x00000000 0x02000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x001e0000>; +- }; +- partition@1e0000 { +- label = "dtb"; +- reg = <0x001e0000 0x00020000>; +- }; +- partition@200000 { +- label = "root"; +- reg = <0x00200000 0x00200000>; +- }; +- partition@400000 { +- label = "user"; +- reg = <0x00400000 0x01b60000>; +- }; +- partition@1f60000 { +- label = "env"; +- reg = <0x01f60000 0x00040000>; +- }; +- partition@1fa0000 { +- label = "u-boot"; +- reg = <0x01fa0000 0x00060000>; +- }; +- }; +- }; +- +- UART0: serial@ef600300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600300 0x00000008>; +- virtual-reg = <0xef600300>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; /* Filled in by U-Boot */ +- interrupt-parent = <&UIC1>; +- interrupts = <0x1 0x4>; +- }; +- +- IIC0: i2c@ef600700 { +- compatible = "ibm,iic-460gt", "ibm,iic"; +- reg = <0xef600700 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x2 0x4>; +- #address-cells = <1>; +- #size-cells = <0>; +- sttm@4a { +- compatible = "ad,ad7414"; +- reg = <0x4a>; +- interrupt-parent = <&UIC1>; +- interrupts = <0x0 0x8>; +- }; +- }; +- +- IIC1: i2c@ef600800 { +- compatible = "ibm,iic-460gt", "ibm,iic"; +- reg = <0xef600800 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x3 0x4>; +- }; +- +- TAH0: emac-tah@ef601350 { +- compatible = "ibm,tah-460gt", "ibm,tah"; +- reg = <0xef601350 0x00000030>; +- }; +- +- TAH1: emac-tah@ef601450 { +- compatible = "ibm,tah-460gt", "ibm,tah"; +- reg = <0xef601450 0x00000030>; +- }; +- +- EMAC0: ethernet@ef600e00 { +- device_type = "network"; +- compatible = "ibm,emac-460gt", "ibm,emac4sync"; +- interrupt-parent = <&EMAC0>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600e00 0x000000c4>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- phy-mode = "sgmii"; +- phy-map = <0xffffffff>; +- gpcs-address = <0x0000000a>; +- tah-device = <&TAH0>; +- tah-channel = <0>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- +- EMAC1: ethernet@ef600f00 { +- device_type = "network"; +- compatible = "ibm,emac-460gt", "ibm,emac4sync"; +- interrupt-parent = <&EMAC1>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600f00 0x000000c4>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <1>; +- mal-rx-channel = <8>; +- cell-index = <1>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- phy-mode = "sgmii"; +- phy-map = <0x00000000>; +- gpcs-address = <0x0000000b>; +- tah-device = <&TAH1>; +- tah-channel = <1>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- mdio-device = <&EMAC0>; +- }; +- +- EMAC2: ethernet@ef601100 { +- device_type = "network"; +- compatible = "ibm,emac-460gt", "ibm,emac4sync"; +- interrupt-parent = <&EMAC2>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef601100 0x000000c4>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <2>; +- mal-rx-channel = <16>; +- cell-index = <2>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- tx-fifo-size-gige = <16384>; /* emac2&3 only */ +- phy-mode = "sgmii"; +- phy-map = <0x00000001>; +- gpcs-address = <0x0000000C>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- mdio-device = <&EMAC0>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/asp834x-redboot.dts b/scripts/dtc/include-prefixes/powerpc/asp834x-redboot.dts +deleted file mode 100644 +index 52a84561c4f0..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/asp834x-redboot.dts ++++ /dev/null +@@ -1,306 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Analogue & Micro ASP8347 Device Tree Source +- * +- * Copyright 2008 Codehermit +- */ +- +-/dts-v1/; +- +-/ { +- model = "Analogue & Micro ASP8347E"; +- compatible = "analogue-and-micro,asp8347e"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8347@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- timebase-frequency = <0>; // from bootloader +- bus-frequency = <0>; // from bootloader +- clock-frequency = <0>; // from bootloader +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x8000000>; // 128MB at 0 +- }; +- +- localbus@ff005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8347e-localbus", +- "fsl,pq2pro-localbus", +- "simple-bus"; +- reg = <0xff005000 0x1000>; +- interrupts = <77 0x8>; +- interrupt-parent = <&ipic>; +- +- ranges = < +- 0 0 0xf0000000 0x02000000 +- >; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x02000000>; +- bank-width = <2>; +- device-width = <2>; +- }; +- }; +- +- soc8349@ff000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- ranges = <0x0 0xff000000 0x00100000>; +- reg = <0xff000000 0x00000200>; +- bus-frequency = <0>; +- +- wdt@200 { +- device_type = "watchdog"; +- compatible = "mpc83xx_wdt"; +- reg = <0x200 0x100>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- +- rtc@68 { +- compatible = "dallas,ds1374"; +- reg = <0x68>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <15 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- }; +- +- spi@7000 { +- cell-index = <0>; +- compatible = "fsl,spi"; +- reg = <0x7000 0x1000>; +- interrupts = <16 0x8>; +- interrupt-parent = <&ipic>; +- mode = "cpu"; +- }; +- +- dma@82a8 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8347-dma", "fsl,elo-dma"; +- reg = <0x82a8 4>; +- ranges = <0 0x8100 0x1a8>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel"; +- reg = <0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x180 0x28>; +- cell-index = <3>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- }; +- +- /* phy type (ULPI or SERIAL) are only types supported for MPH */ +- /* port = 0 or 1 */ +- usb@22000 { +- compatible = "fsl-usb2-mph"; +- reg = <0x22000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <39 0x8>; +- phy_type = "ulpi"; +- port0; +- }; +- /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ +- usb@23000 { +- compatible = "fsl-usb2-dr"; +- reg = <0x23000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <38 0x8>; +- dr_mode = "otg"; +- phy_type = "ulpi"; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 08 e5 11 32 33 ]; +- interrupts = <32 0x8 33 0x8 34 0x8>; +- interrupt-parent = <&ipic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- linux,network-index = <0>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy0: ethernet-phy@0 { +- interrupt-parent = <&ipic>; +- interrupts = <17 0x8>; +- reg = <0x1>; +- }; +- +- phy1: ethernet-phy@1 { +- interrupt-parent = <&ipic>; +- interrupts = <18 0x8>; +- reg = <0x2>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 08 e5 11 32 34 ]; +- interrupts = <35 0x8 36 0x8 37 0x8>; +- interrupt-parent = <&ipic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- linux,network-index = <1>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <400000000>; +- interrupts = <9 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <400000000>; +- interrupts = <10 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- /* May need to remove if on a part without crypto engine */ +- crypto@30000 { +- device_type = "crypto"; +- model = "SEC2"; +- compatible = "talitos"; +- reg = <0x30000 0x10000>; +- interrupts = <11 0x8>; +- interrupt-parent = <&ipic>; +- num-channels = <4>; +- channel-fifo-len = <24>; +- exec-units-mask = <0x0000007e>; +- /* desc mask is for rev2.0, +- * we need runtime fixup for >2.0 */ +- descriptor-types-mask = <0x01010ebf>; +- }; +- +- /* IPIC +- * interrupts cell = +- * sense values match linux IORESOURCE_IRQ_* defines: +- * sense == 8: Level, low assertion +- * sense == 2: Edge, high-to-low change +- */ +- ipic: pic@700 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x700 0x100>; +- device_type = "ipic"; +- }; +- }; +- +- chosen { +- bootargs = "console=ttyS0,38400 root=/dev/mtdblock3 rootfstype=jffs2"; +- stdout-path = &serial0; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/bamboo.dts b/scripts/dtc/include-prefixes/powerpc/bamboo.dts +deleted file mode 100644 +index b5861fa3836c..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/bamboo.dts ++++ /dev/null +@@ -1,302 +0,0 @@ +-/* +- * Device Tree Source for AMCC Bamboo +- * +- * Copyright (c) 2006, 2007 IBM Corp. +- * Josh Boyer +- * +- * FIXME: Draft only! +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <2>; +- #size-cells = <1>; +- model = "amcc,bamboo"; +- compatible = "amcc,bamboo"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- ethernet1 = &EMAC1; +- serial0 = &UART0; +- serial1 = &UART1; +- serial2 = &UART2; +- serial3 = &UART3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,440EP"; +- reg = <0x00000000>; +- clock-frequency = <0>; /* Filled in by zImage */ +- timebase-frequency = <0>; /* Filled in by zImage */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */ +- }; +- +- UIC0: interrupt-controller0 { +- compatible = "ibm,uic-440ep","ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-440ep","ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- SDR0: sdr { +- compatible = "ibm,sdr-440ep"; +- dcr-reg = <0x00e 0x002>; +- }; +- +- CPR0: cpr { +- compatible = "ibm,cpr-440ep"; +- dcr-reg = <0x00c 0x002>; +- }; +- +- plb { +- compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; /* Filled in by zImage */ +- +- SDRAM0: sdram { +- compatible = "ibm,sdram-440ep", "ibm,sdram-405gp"; +- dcr-reg = <0x010 0x002>; +- }; +- +- DMA0: dma { +- compatible = "ibm,dma-440ep", "ibm,dma-440gp"; +- dcr-reg = <0x100 0x027>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <4>; +- num-rx-chans = <2>; +- interrupt-parent = <&MAL0>; +- interrupts = <0x0 0x1 0x2 0x3 0x4>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- /* Bamboo is oddball in the 44x world and doesn't use the ERPN +- * bits. +- */ +- ranges = <0x00000000 0x00000000 0x00000000 0x80000000 +- 0x80000000 0x00000000 0x80000000 0x80000000>; +- interrupt-parent = <&UIC1>; +- interrupts = <0x7 0x4>; +- clock-frequency = <0>; /* Filled in by zImage */ +- +- EBC0: ebc { +- compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; /* Filled in by zImage */ +- interrupts = <0x5 0x1>; +- interrupt-parent = <&UIC1>; +- }; +- +- UART0: serial@ef600300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600300 0x00000008>; +- virtual-reg = <0xef600300>; +- clock-frequency = <0>; /* Filled in by zImage */ +- current-speed = <115200>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x0 0x4>; +- }; +- +- UART1: serial@ef600400 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600400 0x00000008>; +- virtual-reg = <0xef600400>; +- clock-frequency = <0>; +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1 0x4>; +- }; +- +- UART2: serial@ef600500 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600500 0x00000008>; +- virtual-reg = <0xef600500>; +- clock-frequency = <0>; +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x3 0x4>; +- }; +- +- UART3: serial@ef600600 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600600 0x00000008>; +- virtual-reg = <0xef600600>; +- clock-frequency = <0>; +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x4 0x4>; +- }; +- +- IIC0: i2c@ef600700 { +- compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; +- reg = <0xef600700 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x2 0x4>; +- }; +- +- IIC1: i2c@ef600800 { +- compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; +- reg = <0xef600800 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x7 0x4>; +- }; +- +- ZMII0: emac-zmii@ef600d00 { +- compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii"; +- reg = <0xef600d00 0x0000000c>; +- }; +- +- EMAC0: ethernet@ef600e00 { +- device_type = "network"; +- compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; +- interrupt-parent = <&UIC1>; +- interrupts = <0x1c 0x4 0x1d 0x4>; +- reg = <0xef600e00 0x00000070>; +- local-mac-address = [000000000000]; +- mal-device = <&MAL0>; +- mal-tx-channel = <0 1>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <1500>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "rmii"; +- phy-map = <0x00000000>; +- zmii-device = <&ZMII0>; +- zmii-channel = <0>; +- }; +- +- EMAC1: ethernet@ef600f00 { +- device_type = "network"; +- compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; +- interrupt-parent = <&UIC1>; +- interrupts = <0x1e 0x4 0x1f 0x4>; +- reg = <0xef600f00 0x00000070>; +- local-mac-address = [000000000000]; +- mal-device = <&MAL0>; +- mal-tx-channel = <2 3>; +- mal-rx-channel = <1>; +- cell-index = <1>; +- max-frame-size = <1500>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "rmii"; +- phy-map = <0x00000000>; +- zmii-device = <&ZMII0>; +- zmii-channel = <1>; +- }; +- +- usb@ef601000 { +- compatible = "ohci-be"; +- reg = <0xef601000 0x00000080>; +- interrupts = <0x8 0x1 0x9 0x1>; +- interrupt-parent = < &UIC1 >; +- }; +- }; +- +- PCI0: pci@ec000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb440ep-pci", "ibm,plb-pci"; +- primary; +- reg = <0x00000000 0xeec00000 0x00000008 /* Config space access */ +- 0x00000000 0xeed00000 0x00000004 /* IACK */ +- 0x00000000 0xeed00000 0x00000004 /* Special cycle */ +- 0x00000000 0xef400000 0x00000040>; /* Internal registers */ +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed. Chip supports a second +- * IO range but we don't use it for now +- * The chip also supports a larger memory range but +- * it's not naturally aligned, so our code will break +- */ +- ranges = <0x02000000 0x00000000 0xa0000000 0x00000000 0xa0000000 0x00000000 0x20000000 +- 0x02000000 0x00000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00100000 +- 0x01000000 0x00000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; +- +- /* Bamboo has all 4 IRQ pins tied together per slot */ +- interrupt-map-mask = <0xf800 0x0 0x0 0x0>; +- interrupt-map = < +- /* IDSEL 1 */ +- 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8 +- +- /* IDSEL 2 */ +- 0x1000 0x0 0x0 0x0 &UIC0 0x1b 0x8 +- +- /* IDSEL 3 */ +- 0x1800 0x0 0x0 0x0 &UIC0 0x1a 0x8 +- +- /* IDSEL 4 */ +- 0x2000 0x0 0x0 0x0 &UIC0 0x19 0x8 +- >; +- }; +- }; +- +- chosen { +- stdout-path = "/plb/opb/serial@ef600300"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/bluestone.dts b/scripts/dtc/include-prefixes/powerpc/bluestone.dts +deleted file mode 100644 +index aa1ae94cd776..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/bluestone.dts ++++ /dev/null +@@ -1,395 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Device Tree for Bluestone (APM821xx) board. +- * +- * Copyright (c) 2010, Applied Micro Circuits Corporation +- * Author: Tirumala R Marri +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <2>; +- #size-cells = <1>; +- model = "apm,bluestone"; +- compatible = "apm,bluestone"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- serial0 = &UART0; +- serial1 = &UART1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,apm821xx"; +- reg = <0x00000000>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- timebase-frequency = <0>; /* Filled in by U-Boot */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- next-level-cache = <&L2C0>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ +- }; +- +- UIC0: interrupt-controller0 { +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC2: interrupt-controller2 { +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <2>; +- dcr-reg = <0x0e0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC3: interrupt-controller3 { +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <3>; +- dcr-reg = <0x0f0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- OCM: ocm@400040000 { +- compatible = "ibm,ocm"; +- status = "okay"; +- cell-index = <1>; +- /* configured in U-Boot */ +- reg = <4 0x00040000 0x8000>; /* 32K */ +- }; +- +- SDR0: sdr { +- compatible = "ibm,sdr-apm821xx"; +- dcr-reg = <0x00e 0x002>; +- }; +- +- CPR0: cpr { +- compatible = "ibm,cpr-apm821xx"; +- dcr-reg = <0x00c 0x002>; +- }; +- +- L2C0: l2c { +- compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache"; +- dcr-reg = <0x020 0x008 +- 0x030 0x008>; +- cache-line-size = <32>; +- cache-size = <262144>; +- interrupt-parent = <&UIC1>; +- interrupts = <11 1>; +- }; +- +- plb { +- compatible = "ibm,plb4"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- SDRAM0: sdram { +- compatible = "ibm,sdram-apm821xx"; +- dcr-reg = <0x010 0x002>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal2"; +- descriptor-memory = "ocm"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <1>; +- num-rx-chans = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-parent = <&UIC2>; +- interrupts = < /*TXEOB*/ 0x6 0x4 +- /*RXEOB*/ 0x7 0x4 +- /*SERR*/ 0x3 0x4 +- /*TXDE*/ 0x4 0x4 +- /*RXDE*/ 0x5 0x4>; +- }; +- +- POB0: opb { +- compatible = "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- EBC0: ebc { +- compatible = "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- /* ranges property is supplied by U-Boot */ +- ranges = < 0x00000003 0x00000000 0xe0000000 0x8000000>; +- interrupts = <0x6 0x4>; +- interrupt-parent = <&UIC1>; +- +- nor_flash@0,0 { +- compatible = "amd,s29gl512n", "cfi-flash"; +- bank-width = <2>; +- reg = <0x00000000 0x00000000 0x00400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x00180000>; +- }; +- partition@180000 { +- label = "env"; +- reg = <0x00180000 0x00020000>; +- }; +- partition@1a0000 { +- label = "u-boot"; +- reg = <0x001a0000 0x00060000>; +- }; +- }; +- +- ndfc@1,0 { +- compatible = "ibm,ndfc"; +- reg = <0x00000003 0x00000000 0x00002000>; +- ccr = <0x00001000>; +- bank-settings = <0x80002222>; +- #address-cells = <1>; +- #size-cells = <1>; +- /* 2Gb Nand Flash */ +- nand { +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "firmware"; +- reg = <0x00000000 0x00C00000>; +- }; +- partition@c00000 { +- label = "environment"; +- reg = <0x00C00000 0x00B00000>; +- }; +- partition@1700000 { +- label = "kernel"; +- reg = <0x01700000 0x00E00000>; +- }; +- partition@2500000 { +- label = "root"; +- reg = <0x02500000 0x08200000>; +- }; +- partition@a700000 { +- label = "device-tree"; +- reg = <0x0A700000 0x00B00000>; +- }; +- partition@b200000 { +- label = "config"; +- reg = <0x0B200000 0x00D00000>; +- }; +- partition@bf00000 { +- label = "diag"; +- reg = <0x0BF00000 0x00C00000>; +- }; +- partition@cb00000 { +- label = "vendor"; +- reg = <0x0CB00000 0x3500000>; +- }; +- }; +- }; +- }; +- +- UART0: serial@ef600300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600300 0x00000008>; +- virtual-reg = <0xef600300>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; /* Filled in by U-Boot */ +- interrupt-parent = <&UIC1>; +- interrupts = <0x1 0x4>; +- }; +- +- UART1: serial@ef600400 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600400 0x00000008>; +- virtual-reg = <0xef600400>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; /* Filled in by U-Boot */ +- interrupt-parent = <&UIC0>; +- interrupts = <0x1 0x4>; +- }; +- +- IIC0: i2c@ef600700 { +- compatible = "ibm,iic"; +- reg = <0xef600700 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x2 0x4>; +- #address-cells = <1>; +- #size-cells = <0>; +- rtc@68 { +- compatible = "st,m41t80"; +- reg = <0x68>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x9 0x8>; +- }; +- sttm@4C { +- compatible = "adm,adm1032"; +- reg = <0x4C>; +- interrupt-parent = <&UIC1>; +- interrupts = <0x1E 0x8>; /* CPU_THERNAL_L */ +- }; +- }; +- +- IIC1: i2c@ef600800 { +- compatible = "ibm,iic"; +- reg = <0xef600800 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x3 0x4>; +- }; +- +- RGMII0: emac-rgmii@ef601500 { +- compatible = "ibm,rgmii"; +- reg = <0xef601500 0x00000008>; +- has-mdio; +- }; +- +- TAH0: emac-tah@ef601350 { +- compatible = "ibm,tah"; +- reg = <0xef601350 0x00000030>; +- }; +- +- EMAC0: ethernet@ef600c00 { +- device_type = "network"; +- compatible = "ibm,emac-apm821xx", "ibm,emac4sync"; +- interrupt-parent = <&EMAC0>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600c00 0x000000c4>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <9000>; +- rx-fifo-size = <16384>; +- tx-fifo-size = <2048>; +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <0>; +- tah-device = <&TAH0>; +- tah-channel = <0>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- }; +- +- PCIE0: pcie@d00000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex"; +- primary; +- port = <0x0>; /* port number */ +- reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ +- 0x0000000c 0x08010000 0x00001000>; /* Registers */ +- dcr-reg = <0x100 0x020>; +- sdr-base = <0x300>; +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 +- 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 +- 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; +- +- /* This drives busses 40 to 0x7f */ +- bus-range = <0x40 0x7f>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ +- 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ +- 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ +- 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; +- }; +- +- MSI: ppc4xx-msi@C10000000 { +- compatible = "amcc,ppc4xx-msi", "ppc4xx-msi"; +- reg = < 0xC 0x10000000 0x100 +- 0xC 0x10000000 0x100>; +- sdr-base = <0x36C>; +- msi-data = <0x00004440>; +- msi-mask = <0x0000ffe0>; +- interrupts =<0 1 2 3 4 5 6 7>; +- interrupt-parent = <&MSI>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- msi-available-ranges = <0x0 0x100>; +- interrupt-map = < +- 0 &UIC3 0x18 1 +- 1 &UIC3 0x19 1 +- 2 &UIC3 0x1A 1 +- 3 &UIC3 0x1B 1 +- 4 &UIC3 0x1C 1 +- 5 &UIC3 0x1D 1 +- 6 &UIC3 0x1E 1 +- 7 &UIC3 0x1F 1 +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/canyonlands.dts b/scripts/dtc/include-prefixes/powerpc/canyonlands.dts +deleted file mode 100644 +index c5fbb08e0a6e..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/canyonlands.dts ++++ /dev/null +@@ -1,566 +0,0 @@ +-/* +- * Device Tree Source for AMCC Canyonlands (460EX) +- * +- * Copyright 2008-2009 DENX Software Engineering, Stefan Roese +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <2>; +- #size-cells = <1>; +- model = "amcc,canyonlands"; +- compatible = "amcc,canyonlands"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- ethernet1 = &EMAC1; +- serial0 = &UART0; +- serial1 = &UART1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,460EX"; +- reg = <0x00000000>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- timebase-frequency = <0>; /* Filled in by U-Boot */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- next-level-cache = <&L2C0>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ +- }; +- +- UIC0: interrupt-controller0 { +- compatible = "ibm,uic-460ex","ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-460ex","ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC2: interrupt-controller2 { +- compatible = "ibm,uic-460ex","ibm,uic"; +- interrupt-controller; +- cell-index = <2>; +- dcr-reg = <0x0e0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC3: interrupt-controller3 { +- compatible = "ibm,uic-460ex","ibm,uic"; +- interrupt-controller; +- cell-index = <3>; +- dcr-reg = <0x0f0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- SDR0: sdr { +- compatible = "ibm,sdr-460ex"; +- dcr-reg = <0x00e 0x002>; +- }; +- +- CPR0: cpr { +- compatible = "ibm,cpr-460ex"; +- dcr-reg = <0x00c 0x002>; +- }; +- +- CPM0: cpm { +- compatible = "ibm,cpm"; +- dcr-access-method = "native"; +- dcr-reg = <0x160 0x003>; +- unused-units = <0x00000100>; +- idle-doze = <0x02000000>; +- standby = <0xfeff791d>; +- }; +- +- L2C0: l2c { +- compatible = "ibm,l2-cache-460ex", "ibm,l2-cache"; +- dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ +- 0x030 0x008>; /* L2 cache DCR's */ +- cache-line-size = <32>; /* 32 bytes */ +- cache-size = <262144>; /* L2, 256K */ +- interrupt-parent = <&UIC1>; +- interrupts = <11 1>; +- }; +- +- plb { +- compatible = "ibm,plb-460ex", "ibm,plb4"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- SDRAM0: sdram { +- compatible = "ibm,sdram-460ex", "ibm,sdram-405gp"; +- dcr-reg = <0x010 0x002>; +- }; +- +- CRYPTO: crypto@180000 { +- compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto"; +- reg = <4 0x00180000 0x80400>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1d 0x4>; +- }; +- +- HWRNG: hwrng@110000 { +- compatible = "amcc,ppc460ex-rng", "ppc4xx-rng"; +- reg = <4 0x00110000 0x50>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <2>; +- num-rx-chans = <16>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-parent = <&UIC2>; +- interrupts = < /*TXEOB*/ 0x6 0x4 +- /*RXEOB*/ 0x7 0x4 +- /*SERR*/ 0x3 0x4 +- /*TXDE*/ 0x4 0x4 +- /*RXDE*/ 0x5 0x4>; +- }; +- +- USB0: ehci@bffd0400 { +- compatible = "ibm,usb-ehci-460ex", "usb-ehci"; +- interrupt-parent = <&UIC2>; +- interrupts = <0x1d 4>; +- reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>; +- }; +- +- USB1: usb@bffd0000 { +- compatible = "ohci-le"; +- reg = <4 0xbffd0000 0x60>; +- interrupt-parent = <&UIC2>; +- interrupts = <0x1e 4>; +- }; +- +- USBOTG0: usbotg@bff80000 { +- compatible = "amcc,dwc-otg"; +- reg = <0x4 0xbff80000 0x10000>; +- interrupt-parent = <&USBOTG0>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupts = <0x0 0x1 0x2>; +- interrupt-map = ; +- }; +- +- AHBDMA: dma@bffd0800 { +- compatible = "snps,dma-spear1340"; +- reg = <4 0xbffd0800 0x400>; +- interrupt-parent = <&UIC3>; +- interrupts = <0x5 0x4>; +- #dma-cells = <3>; +- }; +- +- SATA0: sata@bffd1000 { +- compatible = "amcc,sata-460ex"; +- reg = <4 0xbffd1000 0x800>; +- interrupt-parent = <&UIC3>; +- interrupts = <0x0 0x4>; +- dmas = <&AHBDMA 0 1 0>; +- dma-names = "sata-dma"; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-460ex", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- EBC0: ebc { +- compatible = "ibm,ebc-460ex", "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- /* ranges property is supplied by U-Boot */ +- interrupts = <0x6 0x4>; +- interrupt-parent = <&UIC1>; +- +- nor_flash@0,0 { +- compatible = "amd,s29gl512n", "cfi-flash"; +- bank-width = <2>; +- reg = <0x00000000 0x00000000 0x04000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x001e0000>; +- }; +- partition@1e0000 { +- label = "dtb"; +- reg = <0x001e0000 0x00020000>; +- }; +- partition@200000 { +- label = "ramdisk"; +- reg = <0x00200000 0x01400000>; +- }; +- partition@1600000 { +- label = "jffs2"; +- reg = <0x01600000 0x00400000>; +- }; +- partition@1a00000 { +- label = "user"; +- reg = <0x01a00000 0x02560000>; +- }; +- partition@3f60000 { +- label = "env"; +- reg = <0x03f60000 0x00040000>; +- }; +- partition@3fa0000 { +- label = "u-boot"; +- reg = <0x03fa0000 0x00060000>; +- }; +- }; +- +- cpld@2,0 { +- compatible = "amcc,ppc460ex-bcsr"; +- reg = <2 0x0 0x9>; +- }; +- +- ndfc@3,0 { +- compatible = "ibm,ndfc"; +- reg = <0x00000003 0x00000000 0x00002000>; +- ccr = <0x00001000>; +- bank-settings = <0x80002222>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- nand { +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x00000000 0x00100000>; +- }; +- partition@100000 { +- label = "user"; +- reg = <0x00000000 0x03f00000>; +- }; +- }; +- }; +- }; +- +- UART0: serial@ef600300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600300 0x00000008>; +- virtual-reg = <0xef600300>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; /* Filled in by U-Boot */ +- interrupt-parent = <&UIC1>; +- interrupts = <0x1 0x4>; +- }; +- +- UART1: serial@ef600400 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600400 0x00000008>; +- virtual-reg = <0xef600400>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; /* Filled in by U-Boot */ +- interrupt-parent = <&UIC0>; +- interrupts = <0x1 0x4>; +- }; +- +- IIC0: i2c@ef600700 { +- compatible = "ibm,iic-460ex", "ibm,iic"; +- reg = <0xef600700 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x2 0x4>; +- #address-cells = <1>; +- #size-cells = <0>; +- rtc@68 { +- compatible = "st,m41t80"; +- reg = <0x68>; +- interrupt-parent = <&UIC2>; +- interrupts = <0x19 0x8>; +- }; +- sttm@48 { +- compatible = "ad,ad7414"; +- reg = <0x48>; +- interrupt-parent = <&UIC1>; +- interrupts = <0x14 0x8>; +- }; +- }; +- +- IIC1: i2c@ef600800 { +- compatible = "ibm,iic-460ex", "ibm,iic"; +- reg = <0xef600800 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x3 0x4>; +- }; +- +- GPIO0: gpio@ef600b00 { +- compatible = "ibm,ppc4xx-gpio"; +- reg = <0xef600b00 0x00000048>; +- gpio-controller; +- }; +- +- ZMII0: emac-zmii@ef600d00 { +- compatible = "ibm,zmii-460ex", "ibm,zmii"; +- reg = <0xef600d00 0x0000000c>; +- }; +- +- RGMII0: emac-rgmii@ef601500 { +- compatible = "ibm,rgmii-460ex", "ibm,rgmii"; +- reg = <0xef601500 0x00000008>; +- has-mdio; +- }; +- +- TAH0: emac-tah@ef601350 { +- compatible = "ibm,tah-460ex", "ibm,tah"; +- reg = <0xef601350 0x00000030>; +- }; +- +- TAH1: emac-tah@ef601450 { +- compatible = "ibm,tah-460ex", "ibm,tah"; +- reg = <0xef601450 0x00000030>; +- }; +- +- EMAC0: ethernet@ef600e00 { +- device_type = "network"; +- compatible = "ibm,emac-460ex", "ibm,emac4sync"; +- interrupt-parent = <&EMAC0>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600e00 0x000000c4>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <0>; +- tah-device = <&TAH0>; +- tah-channel = <0>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- +- EMAC1: ethernet@ef600f00 { +- device_type = "network"; +- compatible = "ibm,emac-460ex", "ibm,emac4sync"; +- interrupt-parent = <&EMAC1>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600f00 0x000000c4>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <1>; +- mal-rx-channel = <8>; +- cell-index = <1>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <1>; +- tah-device = <&TAH1>; +- tah-channel = <1>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- mdio-device = <&EMAC0>; +- }; +- }; +- +- PCIX0: pci@c0ec00000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix"; +- primary; +- large-inbound-windows; +- enable-msi-hole; +- reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ +- 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ +- 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ +- 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ +- 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 +- 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000 +- 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; +- +- /* This drives busses 0 to 0x3f */ +- bus-range = <0x0 0x3f>; +- +- /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ +- interrupt-map-mask = <0x0 0x0 0x0 0x0>; +- interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; +- }; +- +- PCIE0: pcie@d00000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; +- primary; +- port = <0x0>; /* port number */ +- reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ +- 0x0000000c 0x08010000 0x00001000>; /* Registers */ +- dcr-reg = <0x100 0x020>; +- sdr-base = <0x300>; +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 +- 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 +- 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; +- +- /* This drives busses 40 to 0x7f */ +- bus-range = <0x40 0x7f>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ +- 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ +- 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ +- 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; +- }; +- +- PCIE1: pcie@d20000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; +- primary; +- port = <0x1>; /* port number */ +- reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ +- 0x0000000c 0x08011000 0x00001000>; /* Registers */ +- dcr-reg = <0x120 0x020>; +- sdr-base = <0x340>; +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 +- 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000 +- 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; +- +- /* This drives busses 80 to 0xbf */ +- bus-range = <0x80 0xbf>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ +- 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ +- 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ +- 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; +- }; +- +- MSI: ppc4xx-msi@C10000000 { +- compatible = "amcc,ppc4xx-msi", "ppc4xx-msi"; +- reg = < 0xC 0x10000000 0x100>; +- sdr-base = <0x36C>; +- msi-data = <0x00000000>; +- msi-mask = <0x44440000>; +- interrupt-count = <3>; +- interrupts = <0 1 2 3>; +- interrupt-parent = <&UIC3>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = <0 &UIC3 0x18 1 +- 1 &UIC3 0x19 1 +- 2 &UIC3 0x1A 1 +- 3 &UIC3 0x1B 1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/charon.dts b/scripts/dtc/include-prefixes/powerpc/charon.dts +deleted file mode 100644 +index cd589539f313..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/charon.dts ++++ /dev/null +@@ -1,232 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * charon board Device Tree Source +- * +- * Copyright (C) 2007 Semihalf +- * Marian Balakowicz +- * +- * Copyright (C) 2010 DENX Software Engineering GmbH +- * Heiko Schocher +- */ +- +-/dts-v1/; +- +-/ { +- model = "anon,charon"; +- compatible = "anon,charon"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&mpc5200_pic>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,5200@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <0x4000>; // L1, 16K +- i-cache-size = <0x4000>; // L1, 16K +- timebase-frequency = <0>; // from bootloader +- bus-frequency = <0>; // from bootloader +- clock-frequency = <0>; // from bootloader +- }; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; // 128MB +- }; +- +- soc5200@f0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc5200-immr"; +- ranges = <0 0xf0000000 0x0000c000>; +- reg = <0xf0000000 0x00000100>; +- bus-frequency = <0>; // from bootloader +- system-frequency = <0>; // from bootloader +- +- cdm@200 { +- compatible = "fsl,mpc5200-cdm"; +- reg = <0x200 0x38>; +- }; +- +- mpc5200_pic: interrupt-controller@500 { +- // 5200 interrupts are encoded into two levels; +- interrupt-controller; +- #interrupt-cells = <3>; +- compatible = "fsl,mpc5200-pic"; +- reg = <0x500 0x80>; +- }; +- +- timer@600 { // General Purpose Timer +- compatible = "fsl,mpc5200-gpt"; +- reg = <0x600 0x10>; +- interrupts = <1 9 0>; +- fsl,has-wdt; +- }; +- +- can@900 { +- compatible = "fsl,mpc5200-mscan"; +- interrupts = <2 17 0>; +- reg = <0x900 0x80>; +- }; +- +- can@980 { +- compatible = "fsl,mpc5200-mscan"; +- interrupts = <2 18 0>; +- reg = <0x980 0x80>; +- }; +- +- gpio_simple: gpio@b00 { +- compatible = "fsl,mpc5200-gpio"; +- reg = <0xb00 0x40>; +- interrupts = <1 7 0>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- usb@1000 { +- compatible = "fsl,mpc5200-ohci","ohci-be"; +- reg = <0x1000 0xff>; +- interrupts = <2 6 0>; +- }; +- +- dma-controller@1200 { +- device_type = "dma-controller"; +- compatible = "fsl,mpc5200-bestcomm"; +- reg = <0x1200 0x80>; +- interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 +- 3 4 0 3 5 0 3 6 0 3 7 0 +- 3 8 0 3 9 0 3 10 0 3 11 0 +- 3 12 0 3 13 0 3 14 0 3 15 0>; +- }; +- +- xlb@1f00 { +- compatible = "fsl,mpc5200-xlb"; +- reg = <0x1f00 0x100>; +- }; +- +- serial@2000 { // PSC1 +- compatible = "fsl,mpc5200-psc-uart"; +- reg = <0x2000 0x100>; +- interrupts = <2 1 0>; +- }; +- +- serial@2400 { // PSC3 +- compatible = "fsl,mpc5200-psc-uart"; +- reg = <0x2400 0x100>; +- interrupts = <2 3 0>; +- }; +- +- ethernet@3000 { +- compatible = "fsl,mpc5200-fec"; +- reg = <0x3000 0x400>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <2 5 0>; +- fixed-link = <1 1 100 0 0>; +- }; +- +- mdio@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc5200-mdio"; +- reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts +- interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. +- }; +- +- ata@3a00 { +- compatible = "fsl,mpc5200-ata"; +- reg = <0x3a00 0x100>; +- interrupts = <2 7 0>; +- }; +- +- i2c@3d00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc5200-i2c","fsl-i2c"; +- reg = <0x3d00 0x40>; +- interrupts = <2 15 0>; +- }; +- +- +- i2c@3d40 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc5200-i2c","fsl-i2c"; +- reg = <0x3d40 0x40>; +- interrupts = <2 16 0>; +- +- dtt@28 { +- compatible = "national,lm80"; +- reg = <0x28>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1374"; +- reg = <0x68>; +- }; +- }; +- +- sram@8000 { +- compatible = "fsl,mpc5200-sram"; +- reg = <0x8000 0x4000>; +- }; +- }; +- +- localbus { +- compatible = "fsl,mpc5200-lpb","simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = < 0 0 0xfc000000 0x02000000 +- 1 0 0xe0000000 0x04000000 // CS1 range, SM501 +- 3 0 0xe8000000 0x00080000>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x02000000>; +- bank-width = <4>; +- device-width = <2>; +- #size-cells = <1>; +- #address-cells = <1>; +- }; +- +- display@1,0 { +- compatible = "smi,sm501"; +- reg = <1 0x00000000 0x00800000 +- 1 0x03e00000 0x00200000>; +- mode = "640x480-32@60"; +- interrupts = <1 1 3>; +- little-endian; +- }; +- +- mram0@3,0 { +- compatible = "mtd-ram"; +- reg = <3 0x00000 0x80000>; +- bank-width = <1>; +- }; +- }; +- +- pci@f0000d00 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- compatible = "fsl,mpc5200-pci"; +- reg = <0xf0000d00 0x100>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 +- 0xc000 0 0 2 &mpc5200_pic 0 0 3 +- 0xc000 0 0 3 &mpc5200_pic 0 0 3 +- 0xc000 0 0 4 &mpc5200_pic 0 0 3>; +- clock-frequency = <0>; // From boot loader +- interrupts = <2 8 0 2 9 0 2 10 0>; +- bus-range = <0 0>; +- ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000 +- 0x02000000 0 0x90000000 0x90000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/cm5200.dts b/scripts/dtc/include-prefixes/powerpc/cm5200.dts +deleted file mode 100644 +index 66cae7be60c4..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/cm5200.dts ++++ /dev/null +@@ -1,85 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * CM5200 board Device Tree Source +- * +- * Copyright (C) 2007 Semihalf +- * Marian Balakowicz +- */ +- +-/include/ "mpc5200b.dtsi" +- +-&gpt0 { fsl,has-wdt; }; +- +-/ { +- model = "schindler,cm5200"; +- compatible = "schindler,cm5200"; +- +- soc5200@f0000000 { +- can@900 { +- status = "disabled"; +- }; +- +- can@980 { +- status = "disabled"; +- }; +- +- psc@2000 { // PSC1 +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- psc@2200 { // PSC2 +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- psc@2400 { // PSC3 +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- psc@2600 { // PSC4 +- status = "disabled"; +- }; +- +- psc@2800 { // PSC5 +- status = "disabled"; +- }; +- +- psc@2c00 { // PSC6 +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- ethernet@3000 { +- phy-handle = <&phy0>; +- }; +- +- mdio@3000 { +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- ata@3a00 { +- status = "disabled"; +- }; +- +- i2c@3d00 { +- status = "disabled"; +- }; +- +- }; +- +- pci@f0000d00 { +- status = "disabled"; +- }; +- +- localbus { +- // 16-bit flash device at LocalPlus Bus CS0 +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x2000000>; +- bank-width = <2>; +- device-width = <2>; +- #size-cells = <1>; +- #address-cells = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/currituck.dts b/scripts/dtc/include-prefixes/powerpc/currituck.dts +deleted file mode 100644 +index aea8af810106..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/currituck.dts ++++ /dev/null +@@ -1,242 +0,0 @@ +-/* +- * Device Tree Source for IBM Embedded PPC 476 Platform +- * +- * Copyright © 2011 Tony Breeds IBM Corporation +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/memreserve/ 0x01f00000 0x00100000; // spin table +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- model = "ibm,currituck"; +- compatible = "ibm,currituck"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- serial0 = &UART0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,476"; +- reg = <0>; +- clock-frequency = <1600000000>; // 1.6 GHz +- timebase-frequency = <100000000>; // 100Mhz +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- status = "okay"; +- }; +- cpu@1 { +- device_type = "cpu"; +- model = "PowerPC,476"; +- reg = <1>; +- clock-frequency = <1600000000>; // 1.6 GHz +- timebase-frequency = <100000000>; // 100Mhz +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- status = "disabled"; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x01f00000>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x0>; // filled in by zImage +- }; +- +- MPIC: interrupt-controller { +- compatible = "chrp,open-pic"; +- interrupt-controller; +- dcr-reg = <0xffc00000 0x00040000>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- }; +- +- plb { +- compatible = "ibm,plb6"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- clock-frequency = <200000000>; // 200Mhz +- +- POB0: opb { +- compatible = "ibm,opb-4xx", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- /* Wish there was a nicer way of specifying a full +- * 32-bit range +- */ +- ranges = <0x00000000 0x00000200 0x00000000 0x80000000 +- 0x80000000 0x00000200 0x80000000 0x80000000>; +- clock-frequency = <100000000>; +- +- UART0: serial@10000000 { +- device_type = "serial"; +- compatible = "ns16750", "ns16550"; +- reg = <0x10000000 0x00000008>; +- virtual-reg = <0xe1000000>; +- clock-frequency = <1851851>; // PCIe refclk/MCGC0_CTL[UART] +- current-speed = <115200>; +- interrupt-parent = <&MPIC>; +- interrupts = <34 2>; +- }; +- +- FPGA0: fpga@50000000 { +- compatible = "ibm,currituck-fpga"; +- reg = <0x50000000 0x4>; +- }; +- +- IIC0: i2c@0 { +- compatible = "ibm,iic-currituck", "ibm,iic"; +- reg = <0x0 0x00000014>; +- interrupt-parent = <&MPIC>; +- interrupts = <79 2>; +- #address-cells = <1>; +- #size-cells = <0>; +- rtc@68 { +- compatible = "st,m41t80", "m41st85"; +- reg = <0x68>; +- }; +- }; +- }; +- +- PCIE0: pcie@10100000000 { // 4xGBIF1 +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex"; +- primary; +- port = <0x0>; /* port number */ +- reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */ +- 0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */ +- dcr-reg = <0x80 0x20>; +- +-// pci_space < pci_addr > < cpu_addr > < size > +- ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000 +- 0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>; +- +- /* Inbound starting at 0 to memsize filled in by zImage */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>; +- +- /* This drives busses 0 to 0xf */ +- bus-range = <0x0 0xf>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &MPIC 46 0x2 /* int A */ +- 0x0 0x0 0x0 0x2 &MPIC 47 0x2 /* int B */ +- 0x0 0x0 0x0 0x3 &MPIC 48 0x2 /* int C */ +- 0x0 0x0 0x0 0x4 &MPIC 49 0x2 /* int D */>; +- }; +- +- PCIE1: pcie@30100000000 { // 4xGBIF0 +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex"; +- primary; +- port = <0x1>; /* port number */ +- reg = <0x00000301 0x00000000 0x0 0x10000000 /* Config space access */ +- 0x00000300 0x00000000 0x0 0x00001000>; /* UTL Registers space access */ +- dcr-reg = <0x60 0x20>; +- +- ranges = <0x02000000 0x00000000 0x80000000 0x00000310 0x80000000 0x0 0x80000000 +- 0x01000000 0x0 0x0 0x00000340 0x0 0x0 0x00010000>; +- +- /* Inbound starting at 0 to memsize filled in by zImage */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>; +- +- /* This drives busses 0 to 0xf */ +- bus-range = <0x0 0xf>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &MPIC 38 0x2 /* int A */ +- 0x0 0x0 0x0 0x2 &MPIC 39 0x2 /* int B */ +- 0x0 0x0 0x0 0x3 &MPIC 40 0x2 /* int C */ +- 0x0 0x0 0x0 0x4 &MPIC 41 0x2 /* int D */>; +- }; +- +- PCIE2: pcie@38100000000 { // 2xGBIF0 +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex"; +- primary; +- port = <0x2>; /* port number */ +- reg = <0x00000381 0x00000000 0x0 0x10000000 /* Config space access */ +- 0x00000380 0x00000000 0x0 0x00001000>; /* UTL Registers space access */ +- dcr-reg = <0xA0 0x20>; +- +- ranges = <0x02000000 0x00000000 0x80000000 0x00000390 0x80000000 0x0 0x80000000 +- 0x01000000 0x0 0x0 0x000003C0 0x0 0x0 0x00010000>; +- +- /* Inbound starting at 0 to memsize filled in by zImage */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>; +- +- /* This drives busses 0 to 0xf */ +- bus-range = <0x0 0xf>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &MPIC 54 0x2 /* int A */ +- 0x0 0x0 0x0 0x2 &MPIC 55 0x2 /* int B */ +- 0x0 0x0 0x0 0x3 &MPIC 56 0x2 /* int C */ +- 0x0 0x0 0x0 0x4 &MPIC 57 0x2 /* int D */>; +- }; +- +- }; +- +- chosen { +- stdout-path = &UART0; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/digsy_mtc.dts b/scripts/dtc/include-prefixes/powerpc/digsy_mtc.dts +deleted file mode 100644 +index 19a14e62e65f..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/digsy_mtc.dts ++++ /dev/null +@@ -1,157 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Digsy MTC board Device Tree Source +- * +- * Copyright (C) 2009 Semihalf +- * +- * Based on the CM5200 by M. Balakowicz +- */ +- +-/include/ "mpc5200b.dtsi" +- +-&gpt0 { gpio-controller; fsl,has-wdt; }; +-&gpt1 { gpio-controller; }; +- +-/ { +- model = "intercontrol,digsy-mtc"; +- compatible = "intercontrol,digsy-mtc"; +- +- memory@0 { +- reg = <0x00000000 0x02000000>; // 32MB +- }; +- +- soc5200@f0000000 { +- rtc@800 { +- status = "disabled"; +- }; +- +- spi@f00 { +- msp430@0 { +- compatible = "spidev"; +- spi-max-frequency = <32000>; +- reg = <0>; +- }; +- }; +- +- psc@2000 { // PSC1 +- status = "disabled"; +- }; +- +- psc@2200 { // PSC2 +- status = "disabled"; +- }; +- +- psc@2400 { // PSC3 +- status = "disabled"; +- }; +- +- psc@2600 { // PSC4 +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- psc@2800 { // PSC5 +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- psc@2c00 { // PSC6 +- status = "disabled"; +- }; +- +- ethernet@3000 { +- phy-handle = <&phy0>; +- }; +- +- mdio@3000 { +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- i2c@3d00 { +- eeprom@50 { +- compatible = "atmel,24c08"; +- reg = <0x50>; +- }; +- +- rtc@56 { +- compatible = "microcrystal,rv3029"; +- reg = <0x56>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +- }; +- +- i2c@3d40 { +- status = "disabled"; +- }; +- }; +- +- pci@f0000d00 { +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 +- 0xc000 0 0 2 &mpc5200_pic 0 0 3 +- 0xc000 0 0 3 &mpc5200_pic 0 0 3 +- 0xc000 0 0 4 &mpc5200_pic 0 0 3>; +- clock-frequency = <0>; // From boot loader +- interrupts = <2 8 0 2 9 0 2 10 0>; +- bus-range = <0 0>; +- ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000 +- 0x02000000 0 0x90000000 0x90000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>; +- }; +- +- localbus { +- ranges = <0 0 0xff000000 0x1000000 +- 4 0 0x60000000 0x0001000>; +- +- // 16-bit flash device at LocalPlus Bus CS0 +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x1000000>; +- bank-width = <2>; +- device-width = <2>; +- #size-cells = <1>; +- #address-cells = <1>; +- +- partition@0 { +- label = "kernel"; +- reg = <0x0 0x00200000>; +- }; +- partition@200000 { +- label = "root"; +- reg = <0x00200000 0x00300000>; +- }; +- partition@500000 { +- label = "user"; +- reg = <0x00500000 0x00a00000>; +- }; +- partition@f00000 { +- label = "u-boot"; +- reg = <0x00f00000 0x100000>; +- }; +- }; +- +- can@4,0 { +- compatible = "nxp,sja1000"; +- reg = <4 0x000 0x80>; +- nxp,external-clock-frequency = <24000000>; +- interrupts = <1 2 3>; // Level-low +- }; +- +- can@4,100 { +- compatible = "nxp,sja1000"; +- reg = <4 0x100 0x80>; +- nxp,external-clock-frequency = <24000000>; +- interrupts = <1 2 3>; // Level-low +- }; +- +- serial@4,200 { +- compatible = "nxp,sc28l92"; +- reg = <4 0x200 0x10>; +- interrupts = <1 3 3>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/ebony.dts b/scripts/dtc/include-prefixes/powerpc/ebony.dts +deleted file mode 100644 +index 5d11e6ea7405..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/ebony.dts ++++ /dev/null +@@ -1,337 +0,0 @@ +-/* +- * Device Tree Source for IBM Ebony +- * +- * Copyright (c) 2006, 2007 IBM Corp. +- * Josh Boyer , David Gibson +- * +- * FIXME: Draft only! +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <2>; +- #size-cells = <1>; +- model = "ibm,ebony"; +- compatible = "ibm,ebony"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- ethernet1 = &EMAC1; +- serial0 = &UART0; +- serial1 = &UART1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,440GP"; +- reg = <0x00000000>; +- clock-frequency = <0>; // Filled in by zImage +- timebase-frequency = <0>; // Filled in by zImage +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; /* 32 kB */ +- d-cache-size = <32768>; /* 32 kB */ +- dcr-controller; +- dcr-access-method = "native"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage +- }; +- +- UIC0: interrupt-controller0 { +- compatible = "ibm,uic-440gp", "ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-440gp", "ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- CPC0: cpc { +- compatible = "ibm,cpc-440gp"; +- dcr-reg = <0x0b0 0x003 0x0e0 0x010>; +- // FIXME: anything else? +- }; +- +- plb { +- compatible = "ibm,plb-440gp", "ibm,plb4"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; // Filled in by zImage +- +- SDRAM0: memory-controller { +- compatible = "ibm,sdram-440gp"; +- dcr-reg = <0x010 0x002>; +- // FIXME: anything else? +- }; +- +- SRAM0: sram { +- compatible = "ibm,sram-440gp"; +- dcr-reg = <0x020 0x008 0x00a 0x001>; +- }; +- +- DMA0: dma { +- // FIXME: ??? +- compatible = "ibm,dma-440gp"; +- dcr-reg = <0x100 0x027>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-440gp", "ibm,mcmal"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <4>; +- num-rx-chans = <4>; +- interrupt-parent = <&MAL0>; +- interrupts = <0x0 0x1 0x2 0x3 0x4>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- interrupt-map-mask = <0xffffffff>; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-440gp", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- /* Wish there was a nicer way of specifying a full 32-bit +- range */ +- ranges = <0x00000000 0x00000001 0x00000000 0x80000000 +- 0x80000000 0x00000001 0x80000000 0x80000000>; +- dcr-reg = <0x090 0x00b>; +- interrupt-parent = <&UIC1>; +- interrupts = <0x7 0x4>; +- clock-frequency = <0>; // Filled in by zImage +- +- EBC0: ebc { +- compatible = "ibm,ebc-440gp", "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; // Filled in by zImage +- // ranges property is supplied by zImage +- // based on firmware's configuration of the +- // EBC bridge +- interrupts = <0x5 0x4>; +- interrupt-parent = <&UIC1>; +- +- small-flash@0,80000 { +- compatible = "jedec-flash"; +- bank-width = <1>; +- reg = <0x00000000 0x00080000 0x00080000>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "OpenBIOS"; +- reg = <0x00000000 0x00080000>; +- read-only; +- }; +- }; +- +- nvram@1,0 { +- /* NVRAM & RTC */ +- compatible = "ds1743-nvram"; +- #bytes = <0x2000>; +- reg = <0x00000001 0x00000000 0x00002000>; +- }; +- +- large-flash@2,0 { +- compatible = "jedec-flash"; +- bank-width = <1>; +- reg = <0x00000002 0x00000000 0x00400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "fs"; +- reg = <0x00000000 0x00380000>; +- }; +- partition@380000 { +- label = "firmware"; +- reg = <0x00380000 0x00080000>; +- }; +- }; +- +- ir@3,0 { +- reg = <0x00000003 0x00000000 0x00000010>; +- }; +- +- fpga@7,0 { +- compatible = "Ebony-FPGA"; +- reg = <0x00000007 0x00000000 0x00000010>; +- virtual-reg = <0xe8300000>; +- }; +- }; +- +- UART0: serial@40000200 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0x40000200 0x00000008>; +- virtual-reg = <0xe0000200>; +- clock-frequency = <11059200>; +- current-speed = <9600>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x0 0x4>; +- }; +- +- UART1: serial@40000300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0x40000300 0x00000008>; +- virtual-reg = <0xe0000300>; +- clock-frequency = <11059200>; +- current-speed = <9600>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1 0x4>; +- }; +- +- IIC0: i2c@40000400 { +- /* FIXME */ +- compatible = "ibm,iic-440gp", "ibm,iic"; +- reg = <0x40000400 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x2 0x4>; +- }; +- IIC1: i2c@40000500 { +- /* FIXME */ +- compatible = "ibm,iic-440gp", "ibm,iic"; +- reg = <0x40000500 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x3 0x4>; +- }; +- +- GPIO0: gpio@40000700 { +- /* FIXME */ +- compatible = "ibm,gpio-440gp"; +- reg = <0x40000700 0x00000020>; +- }; +- +- ZMII0: emac-zmii@40000780 { +- compatible = "ibm,zmii-440gp", "ibm,zmii"; +- reg = <0x40000780 0x0000000c>; +- }; +- +- EMAC0: ethernet@40000800 { +- device_type = "network"; +- compatible = "ibm,emac-440gp", "ibm,emac"; +- interrupt-parent = <&UIC1>; +- interrupts = <0x1c 0x4 0x1d 0x4>; +- reg = <0x40000800 0x00000070>; +- local-mac-address = [000000000000]; // Filled in by zImage +- mal-device = <&MAL0>; +- mal-tx-channel = <0 1>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <1500>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "rmii"; +- phy-map = <0x00000001>; +- zmii-device = <&ZMII0>; +- zmii-channel = <0>; +- }; +- EMAC1: ethernet@40000900 { +- device_type = "network"; +- compatible = "ibm,emac-440gp", "ibm,emac"; +- interrupt-parent = <&UIC1>; +- interrupts = <0x1e 0x4 0x1f 0x4>; +- reg = <0x40000900 0x00000070>; +- local-mac-address = [000000000000]; // Filled in by zImage +- mal-device = <&MAL0>; +- mal-tx-channel = <2 3>; +- mal-rx-channel = <1>; +- cell-index = <1>; +- max-frame-size = <1500>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "rmii"; +- phy-map = <0x00000001>; +- zmii-device = <&ZMII0>; +- zmii-channel = <1>; +- }; +- +- +- GPT0: gpt@40000a00 { +- /* FIXME */ +- reg = <0x40000a00 0x000000d4>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>; +- }; +- +- }; +- +- PCIX0: pci@20ec00000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix"; +- primary; +- reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */ +- 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ +- 0x00000002 0x0ed00000 0x00000004 /* Special cycles */ +- 0x00000002 0x0ec80000 0x000000f0 /* Internal registers */ +- 0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */ +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000 +- 0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; +- +- /* Ebony has all 4 IRQ pins tied together per slot */ +- interrupt-map-mask = <0xf800 0x0 0x0 0x0>; +- interrupt-map = < +- /* IDSEL 1 */ +- 0x800 0x0 0x0 0x0 &UIC0 0x17 0x8 +- +- /* IDSEL 2 */ +- 0x1000 0x0 0x0 0x0 &UIC0 0x18 0x8 +- +- /* IDSEL 3 */ +- 0x1800 0x0 0x0 0x0 &UIC0 0x19 0x8 +- +- /* IDSEL 4 */ +- 0x2000 0x0 0x0 0x0 &UIC0 0x1a 0x8 +- >; +- }; +- }; +- +- chosen { +- stdout-path = "/plb/opb/serial@40000200"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/eiger.dts b/scripts/dtc/include-prefixes/powerpc/eiger.dts +deleted file mode 100644 +index 7a1231d9d6f0..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/eiger.dts ++++ /dev/null +@@ -1,427 +0,0 @@ +-/* +- * Device Tree Source for AMCC (AppliedMicro) Eiger(460SX) +- * +- * Copyright 2009 AMCC (AppliedMicro) +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <2>; +- #size-cells = <1>; +- model = "amcc,eiger"; +- compatible = "amcc,eiger"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- ethernet1 = &EMAC1; +- ethernet2 = &EMAC2; +- ethernet3 = &EMAC3; +- serial0 = &UART0; +- serial1 = &UART1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,460SX"; +- reg = <0x00000000>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- timebase-frequency = <0>; /* Filled in by U-Boot */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ +- }; +- +- UIC0: interrupt-controller0 { +- compatible = "ibm,uic-460sx","ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-460sx","ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC2: interrupt-controller2 { +- compatible = "ibm,uic-460sx","ibm,uic"; +- interrupt-controller; +- cell-index = <2>; +- dcr-reg = <0x0e0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC3: interrupt-controller3 { +- compatible = "ibm,uic-460sx","ibm,uic"; +- interrupt-controller; +- cell-index = <3>; +- dcr-reg = <0x0f0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- SDR0: sdr { +- compatible = "ibm,sdr-460sx"; +- dcr-reg = <0x00e 0x002>; +- }; +- +- CPR0: cpr { +- compatible = "ibm,cpr-460sx"; +- dcr-reg = <0x00c 0x002>; +- }; +- +- plb { +- compatible = "ibm,plb-460sx", "ibm,plb4"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- SDRAM0: sdram { +- compatible = "ibm,sdram-460sx", "ibm,sdram-405gp"; +- dcr-reg = <0x010 0x002>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-460sx", "ibm,mcmal2"; +- dcr-reg = <0x180 0x62>; +- num-tx-chans = <4>; +- num-rx-chans = <32>; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&UIC1>; +- interrupts = < /*TXEOB*/ 0x6 0x4 +- /*RXEOB*/ 0x7 0x4 +- /*SERR*/ 0x1 0x4 +- /*TXDE*/ 0x2 0x4 +- /*RXDE*/ 0x3 0x4 +- /*COAL TX0*/ 0x18 0x2 +- /*COAL TX1*/ 0x19 0x2 +- /*COAL TX2*/ 0x1a 0x2 +- /*COAL TX3*/ 0x1b 0x2 +- /*COAL RX0*/ 0x1c 0x2 +- /*COAL RX1*/ 0x1d 0x2 +- /*COAL RX2*/ 0x1e 0x2 +- /*COAL RX3*/ 0x1f 0x2>; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-460sx", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- EBC0: ebc { +- compatible = "ibm,ebc-460sx", "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- /* ranges property is supplied by U-Boot */ +- interrupts = <0x6 0x4>; +- interrupt-parent = <&UIC1>; +- +- nor_flash@0,0 { +- compatible = "amd,s29gl512n", "cfi-flash"; +- bank-width = <2>; +- /* reg property is supplied in by U-Boot */ +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x001e0000>; +- }; +- partition@1e0000 { +- label = "dtb"; +- reg = <0x001e0000 0x00020000>; +- }; +- partition@200000 { +- label = "ramdisk"; +- reg = <0x00200000 0x01400000>; +- }; +- partition@1600000 { +- label = "jffs2"; +- reg = <0x01600000 0x00400000>; +- }; +- partition@1a00000 { +- label = "user"; +- reg = <0x01a00000 0x02560000>; +- }; +- partition@3f60000 { +- label = "env"; +- reg = <0x03f60000 0x00040000>; +- }; +- partition@3fa0000 { +- label = "u-boot"; +- reg = <0x03fa0000 0x00060000>; +- }; +- }; +- +- ndfc@1,0 { +- compatible = "ibm,ndfc"; +- /* reg property is supplied by U-boot */ +- ccr = <0x00003000>; +- bank-settings = <0x80002222>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- nand { +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "uboot"; +- reg = <0x00000000 0x00200000>; +- }; +- partition@200000 { +- label = "uboot-environment"; +- reg = <0x00200000 0x00100000>; +- }; +- partition@300000 { +- label = "linux"; +- reg = <0x00300000 0x00300000>; +- }; +- partition@600000 { +- label = "root-file-system"; +- reg = <0x00600000 0x01900000>; +- }; +- partition@1f00000 { +- label = "device-tree"; +- reg = <0x01f00000 0x00020000>; +- }; +- partition@1f20000 { +- label = "data"; +- reg = <0x01f20000 0x060E0000>; +- }; +- }; +- }; +- }; +- +- UART0: serial@ef600200 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600200 0x00000008>; +- virtual-reg = <0xef600200>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; /* Filled in by U-Boot */ +- interrupt-parent = <&UIC0>; +- interrupts = <0x0 0x4>; +- }; +- +- UART1: serial@ef600300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600300 0x00000008>; +- virtual-reg = <0xef600300>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; /* Filled in by U-Boot */ +- interrupt-parent = <&UIC0>; +- interrupts = <0x1 0x4>; +- }; +- +- IIC0: i2c@ef600400 { +- compatible = "ibm,iic-460sx", "ibm,iic"; +- reg = <0xef600400 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x2 0x4>; +- #address-cells = <1>; +- #size-cells = <0>; +- index = <0>; +- }; +- +- IIC1: i2c@ef600500 { +- compatible = "ibm,iic-460sx", "ibm,iic"; +- reg = <0xef600500 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x3 0x4>; +- #address-cells = <1>; +- #size-cells = <0>; +- index = <1>; +- }; +- +- RGMII0: emac-rgmii@ef600900 { +- compatible = "ibm,rgmii-460sx", "ibm,rgmii"; +- reg = <0xef600900 0x00000008>; +- has-mdio; +- }; +- +- RGMII1: emac-rgmii@ef600920 { +- compatible = "ibm,rgmii-460sx", "ibm,rgmii"; +- reg = <0xef600920 0x00000008>; +- has-mdio; +- }; +- +- TAH0: emac-tah@ef600e50 { +- compatible = "ibm,tah-460sx", "ibm,tah"; +- reg = <0xef600e50 0x00000030>; +- }; +- +- TAH1: emac-tah@ef600f50 { +- compatible = "ibm,tah-460sx", "ibm,tah"; +- reg = <0xef600f50 0x00000030>; +- }; +- +- EMAC0: ethernet@ef600a00 { +- device_type = "network"; +- compatible = "ibm,emac-460sx", "ibm,emac4"; +- interrupt-parent = <&EMAC0>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600a00 0x00000070>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <0>; +- tah-device = <&TAH0>; +- tah-channel = <0>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- +- EMAC1: ethernet@ef600b00 { +- device_type = "network"; +- compatible = "ibm,emac-460sx", "ibm,emac4"; +- interrupt-parent = <&EMAC1>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600b00 0x00000070>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <1>; +- mal-rx-channel = <8>; +- cell-index = <1>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <1>; +- tah-device = <&TAH1>; +- tah-channel = <1>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- mdio-device = <&EMAC0>; +- }; +- +- EMAC2: ethernet@ef600c00 { +- device_type = "network"; +- compatible = "ibm,emac-460sx", "ibm,emac4"; +- interrupt-parent = <&EMAC2>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600c00 0x00000070>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <2>; +- mal-rx-channel = <16>; +- cell-index = <2>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- tx-fifo-size-gige = <16384>; /* emac2&3 only */ +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII1>; +- rgmii-channel = <0>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- mdio-device = <&EMAC0>; +- }; +- +- EMAC3: ethernet@ef600d00 { +- device_type = "network"; +- compatible = "ibm,emac-460sx", "ibm,emac4"; +- interrupt-parent = <&EMAC3>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600d00 0x00000070>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <3>; +- mal-rx-channel = <24>; +- cell-index = <3>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- tx-fifo-size-gige = <16384>; /* emac2&3 only */ +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII1>; +- rgmii-channel = <1>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- mdio-device = <&EMAC0>; +- }; +- }; +- +- }; +- chosen { +- stdout-path = "/plb/opb/serial@ef600200"; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/ep8248e.dts b/scripts/dtc/include-prefixes/powerpc/ep8248e.dts +deleted file mode 100644 +index 9ae2d92f54f0..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/ep8248e.dts ++++ /dev/null +@@ -1,199 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Device Tree for the Embedded Planet EP8248E board running PlanetCore. +- * +- * Copyright 2007 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +-/ { +- model = "EP8248E"; +- compatible = "fsl,ep8248e"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- planetcore-SMC1 = &smc1; +- planetcore-SCC1 = &scc1; +- ethernet0 = ð0; +- ethernet1 = ð1; +- serial0 = &smc1; +- serial1 = &scc1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8248@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <16384>; +- i-cache-size = <16384>; +- timebase-frequency = <0>; +- clock-frequency = <0>; +- }; +- }; +- +- localbus@f0010100 { +- compatible = "fsl,mpc8248-localbus", +- "fsl,pq2-localbus", +- "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- reg = <0xf0010100 0x40>; +- +- ranges = <0 0 0xfc000000 0x04000000 +- 1 0 0xfa000000 0x00008000>; +- +- flash@0,3800000 { +- compatible = "cfi-flash"; +- reg = <0 0x3800000 0x800000>; +- bank-width = <4>; +- device-width = <2>; +- }; +- +- bcsr@1,0 { +- #address-cells = <2>; +- #size-cells = <1>; +- reg = <1 0 0x10>; +- compatible = "fsl,ep8248e-bcsr"; +- ranges; +- +- mdio { +- compatible = "fsl,ep8248e-mdio-bitbang"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1 8 1>; +- +- PHY0: ethernet-phy@0 { +- interrupt-parent = <&PIC>; +- reg = <0>; +- }; +- +- PHY1: ethernet-phy@1 { +- interrupt-parent = <&PIC>; +- reg = <1>; +- }; +- }; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0 0>; +- }; +- +- soc@f0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8248-immr", "fsl,pq2-soc", "simple-bus"; +- ranges = <0x00000000 0xf0000000 0x00053000>; +- +- // Temporary until code stops depending on it. +- device_type = "soc"; +- +- // Temporary -- will go away once kernel uses ranges for get_immrbase(). +- reg = <0xf0000000 0x00053000>; +- +- cpm@119c0 { +- #address-cells = <1>; +- #size-cells = <1>; +- #interrupt-cells = <2>; +- compatible = "fsl,mpc8248-cpm", "fsl,cpm2", +- "simple-bus"; +- reg = <0x119c0 0x30>; +- ranges; +- +- muram { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x10000>; +- +- data@0 { +- compatible = "fsl,cpm-muram-data"; +- reg = <0 0x2000 0x9800 0x800>; +- }; +- }; +- +- brg@119f0 { +- compatible = "fsl,mpc8248-brg", +- "fsl,cpm2-brg", +- "fsl,cpm-brg"; +- reg = <0x119f0 0x10 0x115f0 0x10>; +- }; +- +- /* Monitor port/SMC1 */ +- smc1: serial@11a80 { +- device_type = "serial"; +- compatible = "fsl,mpc8248-smc-uart", +- "fsl,cpm2-smc-uart"; +- reg = <0x11a80 0x20 0x87fc 2>; +- interrupts = <4 8>; +- interrupt-parent = <&PIC>; +- fsl,cpm-brg = <7>; +- fsl,cpm-command = <0x1d000000>; +- linux,planetcore-label = "SMC1"; +- }; +- +- /* "Serial" port/SCC1 */ +- scc1: serial@11a00 { +- device_type = "serial"; +- compatible = "fsl,mpc8248-scc-uart", +- "fsl,cpm2-scc-uart"; +- reg = <0x11a00 0x20 0x8000 0x100>; +- interrupts = <40 8>; +- interrupt-parent = <&PIC>; +- fsl,cpm-brg = <1>; +- fsl,cpm-command = <0x00800000>; +- linux,planetcore-label = "SCC1"; +- }; +- +- eth0: ethernet@11300 { +- device_type = "network"; +- compatible = "fsl,mpc8248-fcc-enet", +- "fsl,cpm2-fcc-enet"; +- reg = <0x11300 0x20 0x8400 0x100 0x11390 1>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <32 8>; +- interrupt-parent = <&PIC>; +- phy-handle = <&PHY0>; +- linux,network-index = <0>; +- fsl,cpm-command = <0x12000300>; +- }; +- +- eth1: ethernet@11320 { +- device_type = "network"; +- compatible = "fsl,mpc8248-fcc-enet", +- "fsl,cpm2-fcc-enet"; +- reg = <0x11320 0x20 0x8500 0x100 0x113b0 1>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <33 8>; +- interrupt-parent = <&PIC>; +- phy-handle = <&PHY1>; +- linux,network-index = <1>; +- fsl,cpm-command = <0x16200300>; +- }; +- +- usb@11b60 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc8248-usb", +- "fsl,cpm2-usb"; +- reg = <0x11b60 0x18 0x8b00 0x100>; +- interrupt-parent = <&PIC>; +- interrupts = <11 8>; +- fsl,cpm-command = <0x2e600000>; +- }; +- }; +- +- PIC: interrupt-controller@10c00 { +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0x10c00 0x80>; +- compatible = "fsl,mpc8248-pic", "fsl,pq2-pic"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/ep88xc.dts b/scripts/dtc/include-prefixes/powerpc/ep88xc.dts +deleted file mode 100644 +index b6b7e97876ad..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/ep88xc.dts ++++ /dev/null +@@ -1,209 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * EP88xC Device Tree Source +- * +- * Copyright 2006 MontaVista Software, Inc. +- * Copyright 2007,2008 Freescale Semiconductor, Inc. +- */ +- +-/dts-v1/; +- +-/ { +- model = "EP88xC"; +- compatible = "fsl,ep88xc"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,885@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <16>; +- i-cache-line-size = <16>; +- d-cache-size = <8192>; +- i-cache-size = <8192>; +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- interrupts = <15 2>; // decrementer interrupt +- interrupt-parent = <&PIC>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; +- }; +- +- localbus@fa200100 { +- compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus"; +- #address-cells = <2>; +- #size-cells = <1>; +- reg = <0xfa200100 0x40>; +- +- ranges = < +- 0x0 0x0 0xfc000000 0x4000000 +- 0x3 0x0 0xfa000000 0x1000000 +- >; +- +- flash@0,2000000 { +- compatible = "cfi-flash"; +- reg = <0x0 0x2000000 0x2000000>; +- bank-width = <4>; +- device-width = <2>; +- }; +- +- board-control@3,400000 { +- reg = <0x3 0x400000 0x10>; +- compatible = "fsl,ep88xc-bcsr"; +- }; +- }; +- +- soc@fa200000 { +- compatible = "fsl,mpc885", "fsl,pq1-soc"; +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- ranges = <0x0 0xfa200000 0x4000>; +- bus-frequency = <0>; +- +- // Temporary -- will go away once kernel uses ranges for get_immrbase(). +- reg = <0xfa200000 0x4000>; +- +- mdio@e00 { +- compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio"; +- reg = <0xe00 0x188>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- PHY0: ethernet-phy@0 { +- reg = <0x0>; +- }; +- +- PHY1: ethernet-phy@1 { +- reg = <0x1>; +- }; +- }; +- +- ethernet@e00 { +- device_type = "network"; +- compatible = "fsl,mpc885-fec-enet", +- "fsl,pq1-fec-enet"; +- reg = <0xe00 0x188>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <3 1>; +- interrupt-parent = <&PIC>; +- phy-handle = <&PHY0>; +- linux,network-index = <0>; +- }; +- +- ethernet@1e00 { +- device_type = "network"; +- compatible = "fsl,mpc885-fec-enet", +- "fsl,pq1-fec-enet"; +- reg = <0x1e00 0x188>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <7 1>; +- interrupt-parent = <&PIC>; +- phy-handle = <&PHY1>; +- linux,network-index = <1>; +- }; +- +- PIC: interrupt-controller@0 { +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x0 0x24>; +- compatible = "fsl,mpc885-pic", "fsl,pq1-pic"; +- }; +- +- pcmcia@80 { +- #address-cells = <3>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- compatible = "fsl,pq-pcmcia"; +- device_type = "pcmcia"; +- reg = <0x80 0x80>; +- interrupt-parent = <&PIC>; +- interrupts = <13 1>; +- }; +- +- cpm@9c0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc885-cpm", "fsl,cpm1"; +- command-proc = <0x9c0>; +- interrupts = <0>; // cpm error interrupt +- interrupt-parent = <&CPM_PIC>; +- reg = <0x9c0 0x40>; +- ranges; +- +- muram@2000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2000 0x2000>; +- +- data@0 { +- compatible = "fsl,cpm-muram-data"; +- reg = <0x0 0x1c00>; +- }; +- }; +- +- brg@9f0 { +- compatible = "fsl,mpc885-brg", +- "fsl,cpm1-brg", +- "fsl,cpm-brg"; +- reg = <0x9f0 0x10>; +- }; +- +- CPM_PIC: interrupt-controller@930 { +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupts = <5 2 0 2>; +- interrupt-parent = <&PIC>; +- reg = <0x930 0x20>; +- compatible = "fsl,mpc885-cpm-pic", +- "fsl,cpm1-pic"; +- }; +- +- // MON-1 +- serial@a80 { +- device_type = "serial"; +- compatible = "fsl,mpc885-smc-uart", +- "fsl,cpm1-smc-uart"; +- reg = <0xa80 0x10 0x3e80 0x40>; +- interrupts = <4>; +- interrupt-parent = <&CPM_PIC>; +- fsl,cpm-brg = <1>; +- fsl,cpm-command = <0x90>; +- linux,planetcore-label = "SMC1"; +- }; +- +- // SER-1 +- serial@a20 { +- device_type = "serial"; +- compatible = "fsl,mpc885-scc-uart", +- "fsl,cpm1-scc-uart"; +- reg = <0xa20 0x20 0x3d00 0x80>; +- interrupts = <29>; +- interrupt-parent = <&CPM_PIC>; +- fsl,cpm-brg = <2>; +- fsl,cpm-command = <0x40>; +- linux,planetcore-label = "SCC2"; +- }; +- +- usb@a00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc885-usb", +- "fsl,cpm1-usb"; +- reg = <0xa00 0x18 0x1c00 0x80>; +- interrupt-parent = <&CPM_PIC>; +- interrupts = <30>; +- fsl,cpm-command = <0000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/Makefile b/scripts/dtc/include-prefixes/powerpc/fsl/Makefile +deleted file mode 100644 +index 3bae982641e9..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/Makefile ++++ /dev/null +@@ -1,4 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +- +-dtstree := $(srctree)/$(src) +-dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts)) +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/b4420qds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/b4420qds.dts +deleted file mode 100644 +index cd9203ceedc0..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/b4420qds.dts ++++ /dev/null +@@ -1,50 +0,0 @@ +-/* +- * B4420DS Device Tree Source +- * +- * Copyright 2012 Freescale Semiconductor, Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * This software is provided by Freescale Semiconductor "as is" and any +- * express or implied warranties, including, but not limited to, the implied +- * warranties of merchantability and fitness for a particular purpose are +- * disclaimed. In no event shall Freescale Semiconductor be liable for any +- * direct, indirect, incidental, special, exemplary, or consequential damages +- * (including, but not limited to, procurement of substitute goods or services; +- * loss of use, data, or profits; or business interruption) however caused and +- * on any theory of liability, whether in contract, strict liability, or tort +- * (including negligence or otherwise) arising in any way out of the use of +- * this software, even if advised of the possibility of such damage. +- */ +- +-/include/ "b4420si-pre.dtsi" +-/include/ "b4qds.dtsi" +- +-/ { +- model = "fsl,B4420QDS"; +- compatible = "fsl,B4420QDS"; +- +- ifc: localbus@ffe124000 { +- board-control@3,0 { +- compatible = "fsl,b4420qds-fpga", "fsl,fpga-qixis"; +- }; +- }; +- +-}; +- +-/include/ "b4420si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/b4420si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/b4420si-post.dtsi +deleted file mode 100644 +index f996cced45e0..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/b4420si-post.dtsi ++++ /dev/null +@@ -1,97 +0,0 @@ +-/* +- * B4420 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2012 Freescale Semiconductor, Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * This software is provided by Freescale Semiconductor "as is" and any +- * express or implied warranties, including, but not limited to, the implied +- * warranties of merchantability and fitness for a particular purpose are +- * disclaimed. In no event shall Freescale Semiconductor be liable for any +- * direct, indirect, incidental, special, exemplary, or consequential damages +- * (including, but not limited to, procurement of substitute goods or services; +- * loss of use, data, or profits; or business interruption) however caused and +- * on any theory of liability, whether in contract, strict liability, or tort +- * (including negligence or otherwise) arising in any way out of the use of +- * this software, even if advised of the possibility of such damage. +- */ +- +-/include/ "b4si-post.dtsi" +- +-/* controller at 0x200000 */ +-&pci0 { +- compatible = "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4"; +-}; +- +-&dcsr { +- dcsr-epu@0 { +- compatible = "fsl,b4420-dcsr-epu", "fsl,dcsr-epu"; +- }; +- dcsr-npc { +- compatible = "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc"; +- }; +- dcsr-dpaa@9000 { +- compatible = "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa"; +- }; +- dcsr-ocn@11000 { +- compatible = "fsl,b4420-dcsr-ocn", "fsl,dcsr-ocn"; +- }; +- dcsr-nal@18000 { +- compatible = "fsl,b4420-dcsr-nal", "fsl,dcsr-nal"; +- }; +- dcsr-rcpm@22000 { +- compatible = "fsl,b4420-dcsr-rcpm", "fsl,dcsr-rcpm"; +- }; +- dcsr-snpc@30000 { +- compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc"; +- }; +- dcsr-snpc@31000 { +- compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc"; +- }; +- dcsr-cpu-sb-proxy@108000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu1>; +- reg = <0x108000 0x1000 0x109000 0x1000>; +- }; +-}; +- +-&soc { +- cpc: l3-cache-controller@10000 { +- compatible = "fsl,b4420-l3-cache-controller", "cache"; +- }; +- +- guts: global-utilities@e0000 { +- compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0"; +- }; +- +- global-utilities@e1000 { +- compatible = "fsl,b4420-clockgen", "fsl,b4-clockgen", +- "fsl,qoriq-clockgen-2.0"; +- }; +- +- rcpm: global-utilities@e2000 { +- compatible = "fsl,b4420-rcpm", "fsl,qoriq-rcpm-2.0"; +- }; +- +- L2_1: l2-cache-controller@c20000 { +- compatible = "fsl,b4420-l2-cache-controller"; +- reg = <0xc20000 0x40000>; +- next-level-cache = <&cpc>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/b4420si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/b4420si-pre.dtsi +deleted file mode 100644 +index bb7b9b9f3f5f..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/b4420si-pre.dtsi ++++ /dev/null +@@ -1,85 +0,0 @@ +-/* +- * B4420 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2012 - 2015 Freescale Semiconductor, Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * This software is provided by Freescale Semiconductor "as is" and any +- * express or implied warranties, including, but not limited to, the implied +- * warranties of merchantability and fitness for a particular purpose are +- * disclaimed. In no event shall Freescale Semiconductor be liable for any +- * direct, indirect, incidental, special, exemplary, or consequential damages +- * (including, but not limited to, procurement of substitute goods or services; +- * loss of use, data, or profits; or business interruption) however caused and +- * on any theory of liability, whether in contract, strict liability, or tort +- * (including negligence or otherwise) arising in any way out of the use of +- * this software, even if advised of the possibility of such damage. +- */ +- +-/dts-v1/; +- +-/include/ "e6500_power_isa.dtsi" +- +-/ { +- compatible = "fsl,B4420"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- ccsr = &soc; +- dcsr = &dcsr; +- +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- pci0 = &pci0; +- usb0 = &usb0; +- dma0 = &dma0; +- dma1 = &dma1; +- sdhc = &sdhc; +- +- fman0 = &fman0; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: PowerPC,e6500@0 { +- device_type = "cpu"; +- reg = <0 1>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_1>; +- fsl,portid-mapping = <0x80000000>; +- }; +- cpu1: PowerPC,e6500@2 { +- device_type = "cpu"; +- reg = <2 3>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_1>; +- fsl,portid-mapping = <0x80000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/b4860qds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/b4860qds.dts +deleted file mode 100644 +index a8bc419959ca..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/b4860qds.dts ++++ /dev/null +@@ -1,117 +0,0 @@ +-/* +- * B4860DS Device Tree Source +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "b4860si-pre.dtsi" +-/include/ "b4qds.dtsi" +- +-/ { +- model = "fsl,B4860QDS"; +- compatible = "fsl,B4860QDS"; +- +- aliases { +- phy_sgmii_1e = &phy_sgmii_1e; +- phy_sgmii_1f = &phy_sgmii_1f; +- phy_xaui_slot1 = &phy_xaui_slot1; +- phy_xaui_slot2 = &phy_xaui_slot2; +- }; +- +- ifc: localbus@ffe124000 { +- board-control@3,0 { +- compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis"; +- }; +- }; +- +- soc@ffe000000 { +- fman@400000 { +- ethernet@e8000 { +- phy-handle = <&phy_sgmii_1e>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@ea000 { +- phy-handle = <&phy_sgmii_1f>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@f0000 { +- phy-handle = <&phy_xaui_slot1>; +- phy-connection-type = "xgmii"; +- }; +- +- ethernet@f2000 { +- phy-handle = <&phy_xaui_slot2>; +- phy-connection-type = "xgmii"; +- }; +- +- mdio@fc000 { +- phy_sgmii_1e: ethernet-phy@1e { +- reg = <0x1e>; +- status = "disabled"; +- }; +- +- phy_sgmii_1f: ethernet-phy@1f { +- reg = <0x1f>; +- status = "disabled"; +- }; +- }; +- +- mdio@fd000 { +- phy_xaui_slot1: xaui-phy@slot1 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x7>; +- status = "disabled"; +- }; +- +- phy_xaui_slot2: xaui-phy@slot2 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x6>; +- status = "disabled"; +- }; +- }; +- }; +- }; +- +- rio: rapidio@ffe0c0000 { +- reg = <0xf 0xfe0c0000 0 0x11000>; +- +- port1 { +- ranges = <0 0 0xc 0x20000000 0 0x10000000>; +- }; +- port2 { +- ranges = <0 0 0xc 0x30000000 0 0x10000000>; +- }; +- }; +-}; +- +-/include/ "b4860si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/b4860si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/b4860si-post.dtsi +deleted file mode 100644 +index 868719821106..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/b4860si-post.dtsi ++++ /dev/null +@@ -1,284 +0,0 @@ +-/* +- * B4860 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "b4si-post.dtsi" +- +-/* controller at 0x200000 */ +-&pci0 { +- compatible = "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4"; +-}; +- +-&rio { +- compatible = "fsl,srio"; +- interrupts = <16 2 1 20>; +- #address-cells = <2>; +- #size-cells = <2>; +- fsl,iommu-parent = <&pamu0>; +- ranges; +- +- port1 { +- #address-cells = <2>; +- #size-cells = <2>; +- cell-index = <1>; +- }; +- +- port2 { +- #address-cells = <2>; +- #size-cells = <2>; +- cell-index = <2>; +- }; +-}; +- +-&dcsr { +- dcsr-epu@0 { +- compatible = "fsl,b4860-dcsr-epu", "fsl,dcsr-epu"; +- }; +- dcsr-npc { +- compatible = "fsl,b4860-dcsr-cnpc", "fsl,dcsr-cnpc"; +- }; +- dcsr-dpaa@9000 { +- compatible = "fsl,b4860-dcsr-dpaa", "fsl,dcsr-dpaa"; +- }; +- dcsr-ocn@11000 { +- compatible = "fsl,b4860-dcsr-ocn", "fsl,dcsr-ocn"; +- }; +- dcsr-ddr@13000 { +- compatible = "fsl,dcsr-ddr"; +- dev-handle = <&ddr2>; +- reg = <0x13000 0x1000>; +- }; +- dcsr-nal@18000 { +- compatible = "fsl,b4860-dcsr-nal", "fsl,dcsr-nal"; +- }; +- dcsr-rcpm@22000 { +- compatible = "fsl,b4860-dcsr-rcpm", "fsl,dcsr-rcpm"; +- }; +- dcsr-snpc@30000 { +- compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc"; +- }; +- dcsr-snpc@31000 { +- compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc"; +- }; +- dcsr-cpu-sb-proxy@108000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu1>; +- reg = <0x108000 0x1000 0x109000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@110000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu2>; +- reg = <0x110000 0x1000 0x111000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@118000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu3>; +- reg = <0x118000 0x1000 0x119000 0x1000>; +- }; +-}; +- +-&bportals { +- bman-portal@38000 { +- compatible = "fsl,bman-portal"; +- reg = <0x38000 0x4000>, <0x100e000 0x1000>; +- interrupts = <133 2 0 0>; +- }; +- bman-portal@3c000 { +- compatible = "fsl,bman-portal"; +- reg = <0x3c000 0x4000>, <0x100f000 0x1000>; +- interrupts = <135 2 0 0>; +- }; +- bman-portal@40000 { +- compatible = "fsl,bman-portal"; +- reg = <0x40000 0x4000>, <0x1010000 0x1000>; +- interrupts = <137 2 0 0>; +- }; +- bman-portal@44000 { +- compatible = "fsl,bman-portal"; +- reg = <0x44000 0x4000>, <0x1011000 0x1000>; +- interrupts = <139 2 0 0>; +- }; +- bman-portal@48000 { +- compatible = "fsl,bman-portal"; +- reg = <0x48000 0x4000>, <0x1012000 0x1000>; +- interrupts = <141 2 0 0>; +- }; +- bman-portal@4c000 { +- compatible = "fsl,bman-portal"; +- reg = <0x4c000 0x4000>, <0x1013000 0x1000>; +- interrupts = <143 2 0 0>; +- }; +- bman-portal@50000 { +- compatible = "fsl,bman-portal"; +- reg = <0x50000 0x4000>, <0x1014000 0x1000>; +- interrupts = <145 2 0 0>; +- }; +- bman-portal@54000 { +- compatible = "fsl,bman-portal"; +- reg = <0x54000 0x4000>, <0x1015000 0x1000>; +- interrupts = <147 2 0 0>; +- }; +- bman-portal@58000 { +- compatible = "fsl,bman-portal"; +- reg = <0x58000 0x4000>, <0x1016000 0x1000>; +- interrupts = <149 2 0 0>; +- }; +- bman-portal@5c000 { +- compatible = "fsl,bman-portal"; +- reg = <0x5c000 0x4000>, <0x1017000 0x1000>; +- interrupts = <151 2 0 0>; +- }; +- bman-portal@60000 { +- compatible = "fsl,bman-portal"; +- reg = <0x60000 0x4000>, <0x1018000 0x1000>; +- interrupts = <153 2 0 0>; +- }; +-}; +- +-&qportals { +- qportal14: qman-portal@38000 { +- compatible = "fsl,qman-portal"; +- reg = <0x38000 0x4000>, <0x100e000 0x1000>; +- interrupts = <132 0x2 0 0>; +- cell-index = <0xe>; +- }; +- qportal15: qman-portal@3c000 { +- compatible = "fsl,qman-portal"; +- reg = <0x3c000 0x4000>, <0x100f000 0x1000>; +- interrupts = <134 0x2 0 0>; +- cell-index = <0xf>; +- }; +- qportal16: qman-portal@40000 { +- compatible = "fsl,qman-portal"; +- reg = <0x40000 0x4000>, <0x1010000 0x1000>; +- interrupts = <136 0x2 0 0>; +- cell-index = <0x10>; +- }; +- qportal17: qman-portal@44000 { +- compatible = "fsl,qman-portal"; +- reg = <0x44000 0x4000>, <0x1011000 0x1000>; +- interrupts = <138 0x2 0 0>; +- cell-index = <0x11>; +- }; +- qportal18: qman-portal@48000 { +- compatible = "fsl,qman-portal"; +- reg = <0x48000 0x4000>, <0x1012000 0x1000>; +- interrupts = <140 0x2 0 0>; +- cell-index = <0x12>; +- }; +- qportal19: qman-portal@4c000 { +- compatible = "fsl,qman-portal"; +- reg = <0x4c000 0x4000>, <0x1013000 0x1000>; +- interrupts = <142 0x2 0 0>; +- cell-index = <0x13>; +- }; +- qportal20: qman-portal@50000 { +- compatible = "fsl,qman-portal"; +- reg = <0x50000 0x4000>, <0x1014000 0x1000>; +- interrupts = <144 0x2 0 0>; +- cell-index = <0x14>; +- }; +- qportal21: qman-portal@54000 { +- compatible = "fsl,qman-portal"; +- reg = <0x54000 0x4000>, <0x1015000 0x1000>; +- interrupts = <146 0x2 0 0>; +- cell-index = <0x15>; +- }; +- qportal22: qman-portal@58000 { +- compatible = "fsl,qman-portal"; +- reg = <0x58000 0x4000>, <0x1016000 0x1000>; +- interrupts = <148 0x2 0 0>; +- cell-index = <0x16>; +- }; +- qportal23: qman-portal@5c000 { +- compatible = "fsl,qman-portal"; +- reg = <0x5c000 0x4000>, <0x1017000 0x1000>; +- interrupts = <150 0x2 0 0>; +- cell-index = <0x17>; +- }; +- qportal24: qman-portal@60000 { +- compatible = "fsl,qman-portal"; +- reg = <0x60000 0x4000>, <0x1018000 0x1000>; +- interrupts = <152 0x2 0 0>; +- cell-index = <0x18>; +- }; +-}; +- +-&soc { +- ddr2: memory-controller@9000 { +- compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; +- reg = <0x9000 0x1000>; +- interrupts = <16 2 1 9>; +- }; +- +- cpc: l3-cache-controller@10000 { +- compatible = "fsl,b4860-l3-cache-controller", "cache"; +- }; +- +- guts: global-utilities@e0000 { +- compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0"; +- }; +- +- global-utilities@e1000 { +- compatible = "fsl,b4860-clockgen", "fsl,b4-clockgen", +- "fsl,qoriq-clockgen-2.0"; +- }; +- +- rcpm: global-utilities@e2000 { +- compatible = "fsl,b4860-rcpm", "fsl,qoriq-rcpm-2.0"; +- }; +- +-/include/ "qoriq-fman3-0-1g-4.dtsi" +-/include/ "qoriq-fman3-0-1g-5.dtsi" +-/include/ "qoriq-fman3-0-10g-0.dtsi" +-/include/ "qoriq-fman3-0-10g-1.dtsi" +- fman@400000 { +- enet4: ethernet@e8000 { +- }; +- +- enet5: ethernet@ea000 { +- }; +- +- enet6: ethernet@f0000 { +- }; +- +- enet7: ethernet@f2000 { +- }; +- }; +- +- L2_1: l2-cache-controller@c20000 { +- compatible = "fsl,b4860-l2-cache-controller"; +- reg = <0xc20000 0x40000>; +- next-level-cache = <&cpc>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/b4860si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/b4860si-pre.dtsi +deleted file mode 100644 +index 388ba1b15f8c..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/b4860si-pre.dtsi ++++ /dev/null +@@ -1,104 +0,0 @@ +-/* +- * B4860 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e6500_power_isa.dtsi" +- +-/ { +- compatible = "fsl,B4860"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- ccsr = &soc; +- dcsr = &dcsr; +- +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- pci0 = &pci0; +- usb0 = &usb0; +- dma0 = &dma0; +- dma1 = &dma1; +- sdhc = &sdhc; +- +- fman0 = &fman0; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- ethernet4 = &enet4; +- ethernet5 = &enet5; +- ethernet6 = &enet6; +- ethernet7 = &enet7; +- }; +- +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: PowerPC,e6500@0 { +- device_type = "cpu"; +- reg = <0 1>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_1>; +- fsl,portid-mapping = <0x80000000>; +- }; +- cpu1: PowerPC,e6500@2 { +- device_type = "cpu"; +- reg = <2 3>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_1>; +- fsl,portid-mapping = <0x80000000>; +- }; +- cpu2: PowerPC,e6500@4 { +- device_type = "cpu"; +- reg = <4 5>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_1>; +- fsl,portid-mapping = <0x80000000>; +- }; +- cpu3: PowerPC,e6500@6 { +- device_type = "cpu"; +- reg = <6 7>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_1>; +- fsl,portid-mapping = <0x80000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/b4qds.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/b4qds.dtsi +deleted file mode 100644 +index 05be919f3545..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/b4qds.dtsi ++++ /dev/null +@@ -1,280 +0,0 @@ +-/* +- * B4420DS Device Tree Source +- * +- * Copyright 2012 - 2015 Freescale Semiconductor, Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * This software is provided by Freescale Semiconductor "as is" and any +- * express or implied warranties, including, but not limited to, the implied +- * warranties of merchantability and fitness for a particular purpose are +- * disclaimed. In no event shall Freescale Semiconductor be liable for any +- * direct, indirect, incidental, special, exemplary, or consequential damages +- * (including, but not limited to, procurement of substitute goods or services; +- * loss of use, data, or profits; or business interruption) however caused and +- * on any theory of liability, whether in contract, strict liability, or tort +- * (including negligence or otherwise) arising in any way out of the use of +- * this software, even if advised of the possibility of such damage. +- */ +- +-/ { +- model = "fsl,B4QDS"; +- compatible = "fsl,B4QDS"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- crypto = &crypto; +- phy_sgmii_10 = &phy_sgmii_10; +- phy_sgmii_11 = &phy_sgmii_11; +- phy_sgmii_1c = &phy_sgmii_1c; +- phy_sgmii_1d = &phy_sgmii_1d; +- }; +- +- ifc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x2000>; +- ranges = <0 0 0xf 0xe8000000 0x08000000 +- 2 0 0xf 0xff800000 0x00010000 +- 3 0 0xf 0xffdf0000 0x00008000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,ifc-nand"; +- reg = <0x2 0x0 0x10000>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 1MB for u-boot Bootloader Image */ +- reg = <0x0 0x00100000>; +- label = "NAND U-Boot Image"; +- read-only; +- }; +- +- partition@100000 { +- /* 1MB for DTB Image */ +- reg = <0x00100000 0x00100000>; +- label = "NAND DTB Image"; +- }; +- +- partition@200000 { +- /* 10MB for Linux Kernel Image */ +- reg = <0x00200000 0x00A00000>; +- label = "NAND Linux Kernel Image"; +- }; +- +- partition@c00000 { +- /* 500MB for Root file System Image */ +- reg = <0x00c00000 0x1F400000>; +- label = "NAND RFS Image"; +- }; +- }; +- +- board-control@3,0 { +- compatible = "fsl,b4qds-fpga", "fsl,fpga-qixis"; +- reg = <3 0 0x300>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01052000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x2000000>; +- }; +- +- qportals: qman-portals@ff6000000 { +- ranges = <0x0 0xf 0xf6000000 0x2000000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- spi@110000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "sst,sst25wf040", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; /* input clock */ +- }; +- }; +- +- sdhc@114000 { +- /*Disabled as there is no sdhc connector on B4420QDS board*/ +- status = "disabled"; +- }; +- +- i2c@118000 { +- mux@77 { +- compatible = "nxp,pca9547"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- eeprom@51 { +- compatible = "atmel,24c256"; +- reg = <0x51>; +- }; +- eeprom@53 { +- compatible = "atmel,24c256"; +- reg = <0x53>; +- }; +- eeprom@57 { +- compatible = "atmel,24c256"; +- reg = <0x57>; +- }; +- rtc@68 { +- compatible = "dallas,ds3232"; +- reg = <0x68>; +- }; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; +- +- ina220@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <1000>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3>; +- +- adt7461@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- }; +- }; +- }; +- +- usb@210000 { +- dr_mode = "host"; +- phy_type = "ulpi"; +- }; +- +- fman@400000 { +- ethernet@e0000 { +- phy-handle = <&phy_sgmii_10>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e2000 { +- phy-handle = <&phy_sgmii_11>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e4000 { +- phy-handle = <&phy_sgmii_1c>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e6000 { +- phy-handle = <&phy_sgmii_1d>; +- phy-connection-type = "sgmii"; +- }; +- +- mdio@fc000 { +- phy_sgmii_10: ethernet-phy@10 { +- reg = <0x10>; +- }; +- +- phy_sgmii_11: ethernet-phy@11 { +- reg = <0x11>; +- }; +- +- phy_sgmii_1c: ethernet-phy@1c { +- reg = <0x1c>; +- status = "disabled"; +- }; +- +- phy_sgmii_1d: ethernet-phy@1d { +- reg = <0x1d>; +- status = "disabled"; +- }; +- }; +- }; +- }; +- +- pci0: pcie@ffe200000 { +- reg = <0xf 0xfe200000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +-}; +- +-/include/ "b4si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/b4si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/b4si-post.dtsi +deleted file mode 100644 +index 4f044b41a776..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/b4si-post.dtsi ++++ /dev/null +@@ -1,487 +0,0 @@ +-/* +- * B4420 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2012 - 2015 Freescale Semiconductor, Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * This software is provided by Freescale Semiconductor "as is" and any +- * express or implied warranties, including, but not limited to, the implied +- * warranties of merchantability and fitness for a particular purpose are +- * disclaimed. In no event shall Freescale Semiconductor be liable for any +- * direct, indirect, incidental, special, exemplary, or consequential damages +- * (including, but not limited to, procurement of substitute goods or services; +- * loss of use, data, or profits; or business interruption) however caused and +- * on any theory of liability, whether in contract, strict liability, or tort +- * (including negligence or otherwise) arising in any way out of the use of +- * this software, even if advised of the possibility of such damage. +- */ +- +-&bman_fbpr { +- compatible = "fsl,bman-fbpr"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&qman_fqd { +- compatible = "fsl,qman-fqd"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&qman_pfdr { +- compatible = "fsl,qman-pfdr"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&ifc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,ifc", "simple-bus"; +- interrupts = <25 2 0 0>; +-}; +- +-/* controller at 0x200000 */ +-&pci0 { +- compatible = "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- interrupts = <20 2 0 0>; +- fsl,iommu-parent = <&pamu0>; +- pcie@0 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- reg = <0 0 0 0 0>; +- interrupts = <20 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 40 1 0 0 +- 0000 0 0 2 &mpic 1 1 0 0 +- 0000 0 0 3 &mpic 2 1 0 0 +- 0000 0 0 4 &mpic 3 1 0 0 +- >; +- }; +-}; +- +-&dcsr { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,dcsr", "simple-bus"; +- +- dcsr-epu@0 { +- compatible = "fsl,b4-dcsr-epu", "fsl,dcsr-epu"; +- interrupts = <52 2 0 0 +- 84 2 0 0 +- 85 2 0 0 +- 94 2 0 0 +- 95 2 0 0>; +- reg = <0x0 0x1000>; +- }; +- dcsr-npc { +- compatible = "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc"; +- reg = <0x1000 0x1000 0x1002000 0x10000>; +- }; +- dcsr-nxc@2000 { +- compatible = "fsl,dcsr-nxc"; +- reg = <0x2000 0x1000>; +- }; +- dcsr-corenet { +- compatible = "fsl,dcsr-corenet"; +- reg = <0x8000 0x1000 0x1A000 0x1000>; +- }; +- dcsr-dpaa@9000 { +- compatible = "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa"; +- reg = <0x9000 0x1000>; +- }; +- dcsr-ocn@11000 { +- compatible = "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn"; +- reg = <0x11000 0x1000>; +- }; +- dcsr-ddr@12000 { +- compatible = "fsl,dcsr-ddr"; +- dev-handle = <&ddr1>; +- reg = <0x12000 0x1000>; +- }; +- dcsr-nal@18000 { +- compatible = "fsl,b4-dcsr-nal", "fsl,dcsr-nal"; +- reg = <0x18000 0x1000>; +- }; +- dcsr-rcpm@22000 { +- compatible = "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm"; +- reg = <0x22000 0x1000>; +- }; +- dcsr-snpc@30000 { +- compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc"; +- reg = <0x30000 0x1000 0x1022000 0x10000>; +- }; +- dcsr-snpc@31000 { +- compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc"; +- reg = <0x31000 0x1000 0x1042000 0x10000>; +- }; +- dcsr-cpu-sb-proxy@100000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu0>; +- reg = <0x100000 0x1000 0x101000 0x1000>; +- }; +-}; +- +-&bportals { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- compatible = "simple-bus"; +- +- bman-portal@0 { +- compatible = "fsl,bman-portal"; +- reg = <0x0 0x4000>, <0x1000000 0x1000>; +- interrupts = <105 2 0 0>; +- }; +- bman-portal@4000 { +- compatible = "fsl,bman-portal"; +- reg = <0x4000 0x4000>, <0x1001000 0x1000>; +- interrupts = <107 2 0 0>; +- }; +- bman-portal@8000 { +- compatible = "fsl,bman-portal"; +- reg = <0x8000 0x4000>, <0x1002000 0x1000>; +- interrupts = <109 2 0 0>; +- }; +- bman-portal@c000 { +- compatible = "fsl,bman-portal"; +- reg = <0xc000 0x4000>, <0x1003000 0x1000>; +- interrupts = <111 2 0 0>; +- }; +- bman-portal@10000 { +- compatible = "fsl,bman-portal"; +- reg = <0x10000 0x4000>, <0x1004000 0x1000>; +- interrupts = <113 2 0 0>; +- }; +- bman-portal@14000 { +- compatible = "fsl,bman-portal"; +- reg = <0x14000 0x4000>, <0x1005000 0x1000>; +- interrupts = <115 2 0 0>; +- }; +- bman-portal@18000 { +- compatible = "fsl,bman-portal"; +- reg = <0x18000 0x4000>, <0x1006000 0x1000>; +- interrupts = <117 2 0 0>; +- }; +- bman-portal@1c000 { +- compatible = "fsl,bman-portal"; +- reg = <0x1c000 0x4000>, <0x1007000 0x1000>; +- interrupts = <119 2 0 0>; +- }; +- bman-portal@20000 { +- compatible = "fsl,bman-portal"; +- reg = <0x20000 0x4000>, <0x1008000 0x1000>; +- interrupts = <121 2 0 0>; +- }; +- bman-portal@24000 { +- compatible = "fsl,bman-portal"; +- reg = <0x24000 0x4000>, <0x1009000 0x1000>; +- interrupts = <123 2 0 0>; +- }; +- bman-portal@28000 { +- compatible = "fsl,bman-portal"; +- reg = <0x28000 0x4000>, <0x100a000 0x1000>; +- interrupts = <125 2 0 0>; +- }; +- bman-portal@2c000 { +- compatible = "fsl,bman-portal"; +- reg = <0x2c000 0x4000>, <0x100b000 0x1000>; +- interrupts = <127 2 0 0>; +- }; +- bman-portal@30000 { +- compatible = "fsl,bman-portal"; +- reg = <0x30000 0x4000>, <0x100c000 0x1000>; +- interrupts = <129 2 0 0>; +- }; +- bman-portal@34000 { +- compatible = "fsl,bman-portal"; +- reg = <0x34000 0x4000>, <0x100d000 0x1000>; +- interrupts = <131 2 0 0>; +- }; +-}; +- +-&qportals { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- compatible = "simple-bus"; +- +- qportal0: qman-portal@0 { +- compatible = "fsl,qman-portal"; +- reg = <0x0 0x4000>, <0x1000000 0x1000>; +- interrupts = <104 0x2 0 0>; +- cell-index = <0x0>; +- }; +- qportal1: qman-portal@4000 { +- compatible = "fsl,qman-portal"; +- reg = <0x4000 0x4000>, <0x1001000 0x1000>; +- interrupts = <106 0x2 0 0>; +- cell-index = <0x1>; +- }; +- qportal2: qman-portal@8000 { +- compatible = "fsl,qman-portal"; +- reg = <0x8000 0x4000>, <0x1002000 0x1000>; +- interrupts = <108 0x2 0 0>; +- cell-index = <0x2>; +- }; +- qportal3: qman-portal@c000 { +- compatible = "fsl,qman-portal"; +- reg = <0xc000 0x4000>, <0x1003000 0x1000>; +- interrupts = <110 0x2 0 0>; +- cell-index = <0x3>; +- }; +- qportal4: qman-portal@10000 { +- compatible = "fsl,qman-portal"; +- reg = <0x10000 0x4000>, <0x1004000 0x1000>; +- interrupts = <112 0x2 0 0>; +- cell-index = <0x4>; +- }; +- qportal5: qman-portal@14000 { +- compatible = "fsl,qman-portal"; +- reg = <0x14000 0x4000>, <0x1005000 0x1000>; +- interrupts = <114 0x2 0 0>; +- cell-index = <0x5>; +- }; +- qportal6: qman-portal@18000 { +- compatible = "fsl,qman-portal"; +- reg = <0x18000 0x4000>, <0x1006000 0x1000>; +- interrupts = <116 0x2 0 0>; +- cell-index = <0x6>; +- }; +- qportal7: qman-portal@1c000 { +- compatible = "fsl,qman-portal"; +- reg = <0x1c000 0x4000>, <0x1007000 0x1000>; +- interrupts = <118 0x2 0 0>; +- cell-index = <0x7>; +- }; +- qportal8: qman-portal@20000 { +- compatible = "fsl,qman-portal"; +- reg = <0x20000 0x4000>, <0x1008000 0x1000>; +- interrupts = <120 0x2 0 0>; +- cell-index = <0x8>; +- }; +- qportal9: qman-portal@24000 { +- compatible = "fsl,qman-portal"; +- reg = <0x24000 0x4000>, <0x1009000 0x1000>; +- interrupts = <122 0x2 0 0>; +- cell-index = <0x9>; +- }; +- qportal10: qman-portal@28000 { +- compatible = "fsl,qman-portal"; +- reg = <0x28000 0x4000>, <0x100a000 0x1000>; +- interrupts = <124 0x2 0 0>; +- cell-index = <0xa>; +- }; +- qportal11: qman-portal@2c000 { +- compatible = "fsl,qman-portal"; +- reg = <0x2c000 0x4000>, <0x100b000 0x1000>; +- interrupts = <126 0x2 0 0>; +- cell-index = <0xb>; +- }; +- qportal12: qman-portal@30000 { +- compatible = "fsl,qman-portal"; +- reg = <0x30000 0x4000>, <0x100c000 0x1000>; +- interrupts = <128 0x2 0 0>; +- cell-index = <0xc>; +- }; +- qportal13: qman-portal@34000 { +- compatible = "fsl,qman-portal"; +- reg = <0x34000 0x4000>, <0x100d000 0x1000>; +- interrupts = <130 0x2 0 0>; +- cell-index = <0xd>; +- }; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- +- soc-sram-error { +- compatible = "fsl,soc-sram-error"; +- interrupts = <16 2 1 2>; +- }; +- +- corenet-law@0 { +- compatible = "fsl,corenet-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <32>; +- }; +- +- ddr1: memory-controller@8000 { +- compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; +- reg = <0x8000 0x1000>; +- interrupts = <16 2 1 8>; +- }; +- +- cpc: l3-cache-controller@10000 { +- compatible = "fsl,b4-l3-cache-controller", "cache"; +- reg = <0x10000 0x1000>; +- interrupts = <16 2 1 4>; +- }; +- +- corenet-cf@18000 { +- compatible = "fsl,corenet2-cf", "fsl,corenet-cf"; +- reg = <0x18000 0x1000>; +- interrupts = <16 2 1 0>; +- fsl,ccf-num-csdids = <32>; +- fsl,ccf-num-snoopids = <32>; +- }; +- +- iommu@20000 { +- compatible = "fsl,pamu-v1.0", "fsl,pamu"; +- reg = <0x20000 0x4000>; +- fsl,portid-mapping = <0x8000>; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupts = < +- 24 2 0 0 +- 16 2 1 1>; +- +- +- /* PCIe, DMA, SRIO */ +- pamu0: pamu@0 { +- reg = <0 0x1000>; +- fsl,primary-cache-geometry = <8 1>; +- fsl,secondary-cache-geometry = <32 2>; +- }; +- +- /* AXI2, Maple */ +- pamu1: pamu@1000 { +- reg = <0x1000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <32 2>; +- }; +- +- /* Q/BMan */ +- pamu2: pamu@2000 { +- reg = <0x2000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <32 2>; +- }; +- +- /* AXI1, FMAN */ +- pamu3: pamu@3000 { +- reg = <0x3000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <32 2>; +- }; +- }; +- +-/include/ "qoriq-mpic4.3.dtsi" +- +- guts: global-utilities@e0000 { +- compatible = "fsl,b4-device-config"; +- reg = <0xe0000 0xe00>; +- fsl,has-rstcr; +- fsl,liodn-bits = <12>; +- }; +- +-/include/ "qoriq-clockgen2.dtsi" +- +- rcpm: global-utilities@e2000 { +- compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0"; +- reg = <0xe2000 0x1000>; +- }; +- +-/include/ "elo3-dma-0.dtsi" +- dma@100300 { +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ +- }; +- +-/include/ "elo3-dma-1.dtsi" +- dma@101300 { +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ +- }; +- +-/include/ "qonverge-usb2-dr-0.dtsi" +- usb0: usb@210000 { +- compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr"; +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ +- }; +- +-/include/ "qoriq-espi-0.dtsi" +- spi@110000 { +- fsl,espi-num-chipselects = <4>; +- }; +- +-/include/ "qoriq-esdhc-0.dtsi" +- sdhc@114000 { +- sdhci,auto-cmd12; +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ +- }; +- +-/include/ "qoriq-i2c-0.dtsi" +-/include/ "qoriq-i2c-1.dtsi" +-/include/ "qoriq-duart-0.dtsi" +-/include/ "qoriq-duart-1.dtsi" +-/include/ "qoriq-sec5.3-0.dtsi" +- +-/include/ "qoriq-qman3.dtsi" +- qman: qman@318000 { +- interrupts = <16 2 1 28>; +- }; +- +-/include/ "qoriq-bman1.dtsi" +- bman: bman@31a000 { +- interrupts = <16 2 1 29>; +- }; +- +-/include/ "qoriq-fman3-0.dtsi" +-/include/ "qoriq-fman3-0-1g-0.dtsi" +-/include/ "qoriq-fman3-0-1g-1.dtsi" +-/include/ "qoriq-fman3-0-1g-2.dtsi" +-/include/ "qoriq-fman3-0-1g-3.dtsi" +- fman@400000 { +- interrupts = <96 2 0 0>, <16 2 1 30>; +- +- muram@0 { +- compatible = "fsl,fman-muram"; +- reg = <0x0 0x80000>; +- }; +- +- enet0: ethernet@e0000 { +- }; +- +- enet1: ethernet@e2000 { +- }; +- +- enet2: ethernet@e4000 { +- }; +- +- enet3: ethernet@e6000 { +- }; +- +- mdio@fc000 { +- interrupts = <100 1 0 0>; +- }; +- +- mdio@fd000 { +- interrupts = <101 1 0 0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/bsc9131rdb.dts b/scripts/dtc/include-prefixes/powerpc/fsl/bsc9131rdb.dts +deleted file mode 100644 +index 8da984251abc..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/bsc9131rdb.dts ++++ /dev/null +@@ -1,30 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * BSC9131 RDB Device Tree Source +- * +- * Copyright 2011-2012 Freescale Semiconductor Inc. +- */ +- +-/include/ "bsc9131si-pre.dtsi" +- +-/ { +- model = "fsl,bsc9131rdb"; +- compatible = "fsl,bsc9131rdb"; +- +- memory { +- device_type = "memory"; +- }; +- +- board_ifc: ifc: ifc@ff71e000 { +- /* NAND Flash on board */ +- ranges = <0x0 0x0 0x0 0xff800000 0x00004000>; +- reg = <0x0 0xff71e000 0x0 0x2000>; +- }; +- +- board_soc: soc: soc@ff700000 { +- ranges = <0x0 0x0 0xff700000 0x100000>; +- }; +-}; +- +-/include/ "bsc9131rdb.dtsi" +-/include/ "bsc9131si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/bsc9131rdb.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/bsc9131rdb.dtsi +deleted file mode 100644 +index 53f8b956340f..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/bsc9131rdb.dtsi ++++ /dev/null +@@ -1,104 +0,0 @@ +-/* +- * BSC9131 RDB Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2011-2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&board_ifc { +- +- nand@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,ifc-nand"; +- reg = <0x0 0x0 0x4000>; +- +- }; +-}; +- +-&board_soc { +- /* BSC9131RDB does not have any device on i2c@3100 */ +- i2c@3100 { +- status = "disabled"; +- }; +- +- spi@7000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- +- }; +- }; +- +- usb@22000 { +- phy_type = "ulpi"; +- }; +- +- mdio@24000 { +- phy0: ethernet-phy@0 { +- interrupts = <3 1 0 0>; +- reg = <0x0>; +- }; +- +- phy1: ethernet-phy@1 { +- interrupts = <2 1 0 0>; +- reg = <0x3>; +- }; +- }; +- +- sdhc@2e000 { +- status = "disabled"; +- }; +- +- ptp_clock@b0e00 { +- compatible = "fsl,etsec-ptp"; +- reg = <0xb0e00 0xb0>; +- interrupts = <68 2 0 0 69 2 0 0>; +- fsl,tclk-period = <5>; +- fsl,tmr-prsc = <2>; +- fsl,tmr-add = <0xcccccccd>; +- fsl,tmr-fiper1 = <999999995>; +- fsl,tmr-fiper2 = <99990>; +- fsl,max-adj = <249999999>; +- }; +- +- enet0: ethernet@b0000 { +- phy-handle = <&phy0>; +- phy-connection-type = "rgmii-id"; +- }; +- +- enet1: ethernet@b1000 { +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/bsc9131si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/bsc9131si-post.dtsi +deleted file mode 100644 +index 2a677fd323eb..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/bsc9131si-post.dtsi ++++ /dev/null +@@ -1,189 +0,0 @@ +-/* +- * BSC9131 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2011-2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&ifc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,ifc", "simple-bus"; +- interrupts = <16 2 0 0 20 2 0 0>; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,bsc9131-immr", "simple-bus"; +- bus-frequency = <0>; // Filled out by uboot. +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <12>; +- }; +- +- ecm@1000 { +- compatible = "fsl,bsc9131-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <16 2 0 0>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,bsc9131-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-i2c-0.dtsi" +- i2c@3000 { +- interrupts = <17 2 0 0>; +- }; +- +-/include/ "pq3-i2c-1.dtsi" +- i2c@3100 { +- interrupts = <17 2 0 0>; +- }; +- +-/include/ "pq3-duart-0.dtsi" +- serial0: serial@4500 { +- interrupts = <18 2 0 0>; +- }; +- +- serial1: serial@4600 { +- interrupts = <18 2 0 0 >; +- }; +-/include/ "pq3-espi-0.dtsi" +- spi0: spi@7000 { +- fsl,espi-num-chipselects = <1>; +- interrupts = <22 0x2 0 0>; +- }; +- +-/include/ "pq3-gpio-0.dtsi" +- gpio-controller@f000 { +- interrupts = <19 0x2 0 0>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,bsc9131-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x40000>; // L2,256K +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-dma-0.dtsi" +- +-dma@21300 { +- +- dma-channel@0 { +- interrupts = <62 2 0 0>; +- }; +- +- dma-channel@80 { +- interrupts = <63 2 0 0>; +- }; +- +- dma-channel@100 { +- interrupts = <64 2 0 0>; +- }; +- +- dma-channel@180 { +- interrupts = <65 2 0 0>; +- }; +-}; +- +-/include/ "pq3-usb2-dr-0.dtsi" +-usb@22000 { +- compatible = "fsl-usb2-dr","fsl-usb2-dr-v2.2"; +- interrupts = <40 0x2 0 0>; +-}; +- +-/include/ "pq3-esdhc-0.dtsi" +- sdhc@2e000 { +- sdhci,auto-cmd12; +- interrupts = <41 0x2 0 0>; +- }; +- +-/include/ "pq3-sec4.4-0.dtsi" +-crypto@30000 { +- interrupts = <57 2 0 0>; +- +- sec_jr0: jr@1000 { +- interrupts = <58 2 0 0>; +- }; +- +- sec_jr1: jr@2000 { +- interrupts = <59 2 0 0>; +- }; +- +- sec_jr2: jr@3000 { +- interrupts = <60 2 0 0>; +- }; +- +- sec_jr3: jr@4000 { +- interrupts = <61 2 0 0>; +- }; +-}; +- +-/include/ "pq3-mpic.dtsi" +- +-timer@41100 { +- compatible = "fsl,mpic-v1.2-msgr", "fsl,mpic-msg"; +- reg = <0x41400 0x200>; +- interrupts = < +- 0xb0 2 +- 0xb1 2 +- 0xb2 2 +- 0xb3 2>; +-}; +- +-/include/ "pq3-etsec2-0.dtsi" +-enet0: ethernet@b0000 { +- queue-group@b0000 { +- interrupts = <26 2 0 0 27 2 0 0 28 2 0 0>; +- }; +-}; +- +-/include/ "pq3-etsec2-1.dtsi" +-enet1: ethernet@b1000 { +- queue-group@b1000 { +- interrupts = <33 2 0 0 34 2 0 0 35 2 0 0>; +- }; +-}; +- +-global-utilities@e0000 { +- compatible = "fsl,bsc9131-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/bsc9131si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/bsc9131si-pre.dtsi +deleted file mode 100644 +index f6ec4a67560c..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/bsc9131si-pre.dtsi ++++ /dev/null +@@ -1,62 +0,0 @@ +-/* +- * BSC9131 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2011-2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e500v2_power_isa.dtsi" +- +-/ { +- compatible = "fsl,BSC9131"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- serial0 = &serial0; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,BSC9131@0 { +- device_type = "cpu"; +- compatible = "fsl,e500v2"; +- reg = <0x0>; +- next-level-cache = <&L2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/bsc9132qds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/bsc9132qds.dts +deleted file mode 100644 +index 7cb2158dfe58..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/bsc9132qds.dts ++++ /dev/null +@@ -1,46 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * BSC9132 QDS Device Tree Source +- * +- * Copyright 2014 Freescale Semiconductor Inc. +- */ +- +-/include/ "bsc9132si-pre.dtsi" +- +-/ { +- model = "fsl,bsc9132qds"; +- compatible = "fsl,bsc9132qds"; +- +- memory { +- device_type = "memory"; +- }; +- +- ifc: ifc@ff71e000 { +- /* NOR, NAND Flash on board */ +- ranges = <0x0 0x0 0x0 0x88000000 0x08000000 +- 0x1 0x0 0x0 0xff800000 0x00010000>; +- reg = <0x0 0xff71e000 0x0 0x2000>; +- }; +- +- soc: soc@ff700000 { +- ranges = <0x0 0x0 0xff700000 0x100000>; +- }; +- +- pci0: pcie@ff70a000 { +- reg = <0 0xff70a000 0 0x1000>; +- ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xc0010000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0x90000000 +- 0x2000000 0x0 0x90000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/include/ "bsc9132qds.dtsi" +-/include/ "bsc9132si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/bsc9132qds.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/bsc9132qds.dtsi +deleted file mode 100644 +index fead484a8180..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/bsc9132qds.dtsi ++++ /dev/null +@@ -1,113 +0,0 @@ +-/* +- * BSC9132 QDS Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&ifc { +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,ifc-nand"; +- reg = <0x1 0x0 0x4000>; +- }; +-}; +- +-&soc { +- spi@7000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <30000000>; +- }; +- }; +- +- i2c@3000 { +- fpga: fpga@66 { +- compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c"; +- reg = <0x66>; +- }; +- }; +- +- usb@22000 { +- phy_type = "ulpi"; +- }; +- +- mdio@24000 { +- phy0: ethernet-phy@0 { +- reg = <0x0>; +- }; +- +- phy1: ethernet-phy@1 { +- reg = <0x1>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x1f>; +- device_type = "tbi-phy"; +- }; +- }; +- +- ptp_clock@b0e00 { +- compatible = "fsl,etsec-ptp"; +- reg = <0xb0e00 0xb0>; +- interrupts = <68 2 0 0 69 2 0 0>; +- fsl,tclk-period = <5>; +- fsl,tmr-prsc = <2>; +- fsl,tmr-add = <0xcccccccd>; +- fsl,tmr-fiper1 = <999999995>; +- fsl,tmr-fiper2 = <99990>; +- fsl,max-adj = <249999999>; +- }; +- +- enet0: ethernet@b0000 { +- phy-handle = <&phy0>; +- tbi-handle = <&tbi0>; +- phy-connection-type = "sgmii"; +- }; +- +- enet1: ethernet@b1000 { +- phy-handle = <&phy1>; +- tbi-handle = <&tbi0>; +- phy-connection-type = "sgmii"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/bsc9132si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/bsc9132si-post.dtsi +deleted file mode 100644 +index b8e0edd1ac69..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/bsc9132si-post.dtsi ++++ /dev/null +@@ -1,209 +0,0 @@ +-/* +- * BSC9132 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&ifc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,ifc", "simple-bus"; +- /* FIXME: Test whether interrupts are split */ +- interrupts = <16 2 0 0 20 2 0 0>; +-}; +- +-/* controller at 0xa000 */ +-&pci0 { +- compatible = "fsl,bsc9132-pcie", "fsl,qoriq-pcie-v2.2"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- interrupts = <16 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x0 0x2 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x1 0x2 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x2 0x2 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x3 0x2 0x0 0x0 +- >; +- }; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,bsc9132-immr", "simple-bus"; +- bus-frequency = <0>; // Filled out by uboot. +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <12>; +- }; +- +- ecm@1000 { +- compatible = "fsl,bsc9132-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <16 2 0 0>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,bsc9132-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupts = <16 2 1 8>; +- }; +- +-/include/ "pq3-i2c-0.dtsi" +- i2c@3000 { +- interrupts = <17 2 0 0>; +- }; +- +-/include/ "pq3-i2c-1.dtsi" +- i2c@3100 { +- interrupts = <17 2 0 0>; +- }; +- +-/include/ "pq3-duart-0.dtsi" +- serial0: serial@4500 { +- interrupts = <18 2 0 0>; +- }; +- +- serial1: serial@4600 { +- interrupts = <18 2 0 0 >; +- }; +-/include/ "pq3-espi-0.dtsi" +- spi0: spi@7000 { +- fsl,espi-num-chipselects = <1>; +- interrupts = <22 0x2 0 0>; +- }; +- +-/include/ "pq3-gpio-0.dtsi" +- gpio-controller@f000 { +- interrupts = <19 0x2 0 0>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,bsc9132-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x40000>; // L2,256K +- interrupts = <16 2 1 0>; +- }; +- +-/include/ "pq3-dma-0.dtsi" +- +-dma@21300 { +- +- dma-channel@0 { +- interrupts = <62 2 0 0>; +- }; +- +- dma-channel@80 { +- interrupts = <63 2 0 0>; +- }; +- +- dma-channel@100 { +- interrupts = <64 2 0 0>; +- }; +- +- dma-channel@180 { +- interrupts = <65 2 0 0>; +- }; +-}; +- +-/include/ "pq3-usb2-dr-0.dtsi" +-usb@22000 { +- compatible = "fsl-usb2-dr","fsl-usb2-dr-v2.2"; +- interrupts = <40 0x2 0 0>; +-}; +- +-/include/ "pq3-esdhc-0.dtsi" +- sdhc@2e000 { +- fsl,sdhci-auto-cmd12; +- interrupts = <41 0x2 0 0>; +- }; +- +-/include/ "pq3-sec4.4-0.dtsi" +-crypto@30000 { +- interrupts = <57 2 0 0>; +- +- sec_jr0: jr@1000 { +- interrupts = <58 2 0 0>; +- }; +- +- sec_jr1: jr@2000 { +- interrupts = <59 2 0 0>; +- }; +- +- sec_jr2: jr@3000 { +- interrupts = <60 2 0 0>; +- }; +- +- sec_jr3: jr@4000 { +- interrupts = <61 2 0 0>; +- }; +-}; +- +-/include/ "pq3-mpic.dtsi" +-/include/ "pq3-mpic-timer-B.dtsi" +- +-/include/ "pq3-etsec2-0.dtsi" +-enet0: ethernet@b0000 { +- queue-group@b0000 { +- interrupts = <26 2 0 0 27 2 0 0 28 2 0 0>; +- }; +-}; +- +-/include/ "pq3-etsec2-1.dtsi" +-enet1: ethernet@b1000 { +- queue-group@b1000 { +- interrupts = <33 2 0 0 34 2 0 0 35 2 0 0>; +- }; +-}; +- +-global-utilities@e0000 { +- compatible = "fsl,bsc9132-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/bsc9132si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/bsc9132si-pre.dtsi +deleted file mode 100644 +index 90f7949fe312..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/bsc9132si-pre.dtsi ++++ /dev/null +@@ -1,67 +0,0 @@ +-/* +- * BSC9132 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e500v2_power_isa.dtsi" +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- serial0 = &serial0; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: PowerPC,e500v2@0 { +- device_type = "cpu"; +- reg = <0x0>; +- next-level-cache = <&L2>; +- }; +- +- cpu1: PowerPC,e500v2@1 { +- device_type = "cpu"; +- reg = <0x1>; +- next-level-cache = <&L2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/c293pcie.dts b/scripts/dtc/include-prefixes/powerpc/fsl/c293pcie.dts +deleted file mode 100644 +index 5e905e0857cf..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/c293pcie.dts ++++ /dev/null +@@ -1,224 +0,0 @@ +-/* +- * C293 PCIE Device Tree Source +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "c293si-pre.dtsi" +- +-/ { +- model = "fsl,C293PCIE"; +- compatible = "fsl,C293PCIE"; +- +- memory { +- device_type = "memory"; +- }; +- +- ifc: ifc@fffe1e000 { +- reg = <0xf 0xffe1e000 0 0x2000>; +- ranges = <0x0 0x0 0xf 0xec000000 0x04000000 +- 0x1 0x0 0xf 0xff800000 0x00010000 +- 0x2 0x0 0xf 0xffdf0000 0x00010000>; +- +- }; +- +- soc: soc@fffe00000 { +- ranges = <0x0 0xf 0xffe00000 0x100000>; +- }; +- +- pci0: pcie@fffe0a000 { +- reg = <0xf 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-&ifc { +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x4000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- /* 1MB for DTB Image */ +- reg = <0x0 0x00100000>; +- label = "NOR DTB Image"; +- }; +- +- partition@100000 { +- /* 8 MB for Linux Kernel Image */ +- reg = <0x00100000 0x00800000>; +- label = "NOR Linux Kernel Image"; +- }; +- +- partition@900000 { +- /* 53MB for rootfs */ +- reg = <0x00900000 0x03500000>; +- label = "NOR Rootfs Image"; +- }; +- +- partition@3e00000 { +- /* 1MB for blob encrypted key */ +- reg = <0x03e00000 0x00100000>; +- label = "NOR blob encrypted key"; +- }; +- +- partition@3f00000 { +- /* 512KB for u-boot Bootloader Image and evn */ +- reg = <0x03f00000 0x00100000>; +- label = "NOR U-Boot Image"; +- read-only; +- }; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,ifc-nand"; +- reg = <0x1 0x0 0x10000>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 1MB for u-boot Bootloader Image */ +- reg = <0x0 0x00100000>; +- label = "NAND U-Boot Image"; +- read-only; +- }; +- +- partition@100000 { +- /* 1MB for DTB Image */ +- reg = <0x00100000 0x00100000>; +- label = "NAND DTB Image"; +- }; +- +- partition@200000 { +- /* 16MB for Linux Kernel Image */ +- reg = <0x00200000 0x01000000>; +- label = "NAND Linux Kernel Image"; +- }; +- +- partition@1200000 { +- /* 4078MB for Root file System Image */ +- reg = <0x00600000 0xfee00000>; +- label = "NAND RFS Image"; +- }; +- }; +- +- cpld@2,0 { +- compatible = "fsl,c293pcie-cpld"; +- reg = <0x2 0x0 0x20>; +- }; +-}; +- +-&soc { +- i2c@3000 { +- eeprom@50 { +- compatible = "st,24c1024", "atmel,24c1024"; +- reg = <0x50>; +- }; +- +- adt7461@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- }; +- +- spi@7000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- +- partition@0 { +- /* 1MB for u-boot Bootloader Image */ +- /* 1MB for Environment */ +- reg = <0x0 0x00100000>; +- label = "SPI Flash U-Boot Image"; +- read-only; +- }; +- +- partition@100000 { +- /* 512KB for DTB Image */ +- reg = <0x00100000 0x00080000>; +- label = "SPI Flash DTB Image"; +- }; +- +- partition@180000 { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00180000 0x00400000>; +- label = "SPI Flash Linux Kernel Image"; +- }; +- +- partition@580000 { +- /* 10.5MB for RFS Image */ +- reg = <0x00580000 0x00a80000>; +- label = "SPI Flash RFS Image"; +- }; +- }; +- }; +- +- mdio@24000 { +- phy0: ethernet-phy@0 { +- interrupts = <2 1 0 0>; +- reg = <0x0>; +- }; +- +- phy1: ethernet-phy@1 { +- interrupts = <2 1 0 0>; +- reg = <0x2>; +- }; +- }; +- +- enet0: ethernet@b0000 { +- phy-handle = <&phy0>; +- phy-connection-type = "rgmii-id"; +- }; +- +- enet1: ethernet@b1000 { +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +-}; +-/include/ "c293si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/c293si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/c293si-post.dtsi +deleted file mode 100644 +index bec0fc36849d..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/c293si-post.dtsi ++++ /dev/null +@@ -1,189 +0,0 @@ +-/* +- * C293 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&ifc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,ifc", "simple-bus"; +- interrupts = <19 2 0 0>; +-}; +- +-/* controller at 0xa000 */ +-&pci0 { +- compatible = "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <16 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 +- >; +- }; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- bus-frequency = <0>; // Filled out by uboot. +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <12>; +- }; +- +- ecm@1000 { +- compatible = "fsl,c293-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <16 2 0 0>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,c293-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-i2c-0.dtsi" +-/include/ "pq3-i2c-1.dtsi" +-/include/ "pq3-duart-0.dtsi" +-/include/ "pq3-espi-0.dtsi" +- spi0: spi@7000 { +- fsl,espi-num-chipselects = <1>; +- }; +- +-/include/ "pq3-gpio-0.dtsi" +- L2: l2-cache-controller@20000 { +- compatible = "fsl,c293-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x80000>; // L2,512K +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-dma-0.dtsi" +-/include/ "pq3-esdhc-0.dtsi" +- sdhc@2e000 { +- compatible = "fsl,c293-esdhc", "fsl,esdhc"; +- sdhci,auto-cmd12; +- }; +- +- crypto@80000 { +-/include/ "qoriq-sec6.0-0.dtsi" +- }; +- +- crypto@80000 { +- reg = <0x80000 0x20000>; +- ranges = <0x0 0x80000 0x20000>; +- +- jr@1000{ +- interrupts = <45 2 0 0>; +- }; +- jr@2000{ +- interrupts = <57 2 0 0>; +- }; +- }; +- +- crypto@a0000 { +-/include/ "qoriq-sec6.0-0.dtsi" +- }; +- +- crypto@a0000 { +- reg = <0xa0000 0x20000>; +- ranges = <0x0 0xa0000 0x20000>; +- +- jr@1000{ +- interrupts = <49 2 0 0>; +- }; +- jr@2000{ +- interrupts = <50 2 0 0>; +- }; +- }; +- +- crypto@c0000 { +-/include/ "qoriq-sec6.0-0.dtsi" +- }; +- +- crypto@c0000 { +- reg = <0xc0000 0x20000>; +- ranges = <0x0 0xc0000 0x20000>; +- +- jr@1000{ +- interrupts = <55 2 0 0>; +- }; +- jr@2000{ +- interrupts = <56 2 0 0>; +- }; +- }; +- +-/include/ "pq3-mpic.dtsi" +-/include/ "pq3-mpic-timer-B.dtsi" +- +-/include/ "pq3-etsec2-0.dtsi" +- enet0: ethernet@b0000 { +- queue-group@b0000 { +- reg = <0x10000 0x1000>; +- }; +- }; +- +-/include/ "pq3-etsec2-1.dtsi" +- enet1: ethernet@b1000 { +- queue-group@b1000 { +- reg = <0x11000 0x1000>; +- }; +- }; +- +- global-utilities@e0000 { +- compatible = "fsl,c293-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/c293si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/c293si-pre.dtsi +deleted file mode 100644 +index 065049d76245..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/c293si-pre.dtsi ++++ /dev/null +@@ -1,63 +0,0 @@ +-/* +- * C293 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e500v2_power_isa.dtsi" +- +-/ { +- compatible = "fsl,C293"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,e500v2@0 { +- device_type = "cpu"; +- reg = <0x0>; +- next-level-cache = <&L2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/cyrus_p5020.dts b/scripts/dtc/include-prefixes/powerpc/fsl/cyrus_p5020.dts +deleted file mode 100644 +index 40ba0606ec55..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/cyrus_p5020.dts ++++ /dev/null +@@ -1,151 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Cyrus 5020 Device Tree Source, based on p5020ds.dts +- * +- * Copyright 2015 Andy Fleming +- * +- * p5020ds.dts copyright: +- * Copyright 2010 - 2014 Freescale Semiconductor Inc. +- */ +- +-/include/ "p5020si-pre.dtsi" +- +-/ { +- model = "varisys,CYRUS"; +- compatible = "varisys,CYRUS"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- memory { +- device_type = "memory"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01008000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x200000>; +- }; +- +- qportals: qman-portals@ff4200000 { +- ranges = <0x0 0xf 0xf4200000 0x200000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- spi@110000 { +- }; +- +- i2c@118100 { +- }; +- +- i2c@119100 { +- rtc@6f { +- compatible = "microchip,mcp7941x"; +- reg = <0x6f>; +- }; +- }; +- }; +- +- rio: rapidio@ffe0c0000 { +- reg = <0xf 0xfe0c0000 0 0x11000>; +- +- port1 { +- ranges = <0 0 0xc 0x20000000 0 0x10000000>; +- }; +- port2 { +- ranges = <0 0 0xc 0x30000000 0 0x10000000>; +- }; +- }; +- +- lbc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x1000>; +- ranges = <0 0 0xf 0xe8000000 0x08000000 +- 2 0 0xf 0xffa00000 0x00040000 +- 3 0 0xf 0xffdf0000 0x00008000>; +- }; +- +- pci0: pcie@ffe200000 { +- reg = <0xf 0xfe200000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci1: pcie@ffe201000 { +- reg = <0xf 0xfe201000 0 0x1000>; +- ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 +- 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci2: pcie@ffe202000 { +- reg = <0xf 0xfe202000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci3: pcie@ffe203000 { +- reg = <0xf 0xfe203000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +-}; +- +-/include/ "p5020si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/e500mc_power_isa.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/e500mc_power_isa.dtsi +deleted file mode 100644 +index ea145c91cfbd..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/e500mc_power_isa.dtsi ++++ /dev/null +@@ -1,59 +0,0 @@ +-/* +- * e500mc Power ISA Device Tree Source (include) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/ { +- cpus { +- power-isa-version = "2.06"; +- power-isa-b; // Base +- power-isa-e; // Embedded +- power-isa-atb; // Alternate Time Base +- power-isa-cs; // Cache Specification +- power-isa-ds; // Decorated Storage +- power-isa-e.ed; // Embedded.Enhanced Debug +- power-isa-e.pd; // Embedded.External PID +- power-isa-e.hv; // Embedded.Hypervisor +- power-isa-e.le; // Embedded.Little-Endian +- power-isa-e.pm; // Embedded.Performance Monitor +- power-isa-e.pc; // Embedded.Processor Control +- power-isa-ecl; // Embedded Cache Locking +- power-isa-exp; // External Proxy +- power-isa-fp; // Floating Point +- power-isa-fp.r; // Floating Point.Record +- power-isa-mmc; // Memory Coherence +- power-isa-scpm; // Store Conditional Page Mobility +- power-isa-wt; // Wait +- fsl,eref-deo; // Data Cache Extended Operations +- mmu-type = "power-embedded"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/e500v2_power_isa.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/e500v2_power_isa.dtsi +deleted file mode 100644 +index f4928144d2c8..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/e500v2_power_isa.dtsi ++++ /dev/null +@@ -1,52 +0,0 @@ +-/* +- * e500v2 Power ISA Device Tree Source (include) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/ { +- cpus { +- power-isa-version = "2.03"; +- power-isa-b; // Base +- power-isa-e; // Embedded +- power-isa-atb; // Alternate Time Base +- power-isa-cs; // Cache Specification +- power-isa-e.le; // Embedded.Little-Endian +- power-isa-e.pm; // Embedded.Performance Monitor +- power-isa-ecl; // Embedded Cache Locking +- power-isa-mmc; // Memory Coherence +- power-isa-sp; // Signal Processing Engine +- power-isa-sp.fd; // SPE.Embedded Float Scalar Double +- power-isa-sp.fs; // SPE.Embedded Float Scalar Single +- power-isa-sp.fv; // SPE.Embedded Float Vector +- mmu-type = "power-embedded"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/e5500_power_isa.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/e5500_power_isa.dtsi +deleted file mode 100644 +index c254c981ae87..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/e5500_power_isa.dtsi ++++ /dev/null +@@ -1,60 +0,0 @@ +-/* +- * e5500 Power ISA Device Tree Source (include) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/ { +- cpus { +- power-isa-version = "2.06"; +- power-isa-b; // Base +- power-isa-e; // Embedded +- power-isa-atb; // Alternate Time Base +- power-isa-cs; // Cache Specification +- power-isa-ds; // Decorated Storage +- power-isa-e.ed; // Embedded.Enhanced Debug +- power-isa-e.pd; // Embedded.External PID +- power-isa-e.hv; // Embedded.Hypervisor +- power-isa-e.le; // Embedded.Little-Endian +- power-isa-e.pm; // Embedded.Performance Monitor +- power-isa-e.pc; // Embedded.Processor Control +- power-isa-ecl; // Embedded Cache Locking +- power-isa-exp; // External Proxy +- power-isa-fp; // Floating Point +- power-isa-fp.r; // Floating Point.Record +- power-isa-mmc; // Memory Coherence +- power-isa-scpm; // Store Conditional Page Mobility +- power-isa-wt; // Wait +- power-isa-64; // 64-bit +- fsl,eref-deo; // Data Cache Extended Operations +- mmu-type = "power-embedded"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/e6500_power_isa.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/e6500_power_isa.dtsi +deleted file mode 100644 +index a912dbeff359..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/e6500_power_isa.dtsi ++++ /dev/null +@@ -1,65 +0,0 @@ +-/* +- * e6500 Power ISA Device Tree Source (include) +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/ { +- cpus { +- power-isa-version = "2.06"; +- power-isa-b; // Base +- power-isa-e; // Embedded +- power-isa-atb; // Alternate Time Base +- power-isa-cs; // Cache Specification +- power-isa-ds; // Decorated Storage +- power-isa-e.ed; // Embedded.Enhanced Debug +- power-isa-e.pd; // Embedded.External PID +- power-isa-e.hv; // Embedded.Hypervisor +- power-isa-e.le; // Embedded.Little-Endian +- power-isa-e.pm; // Embedded.Performance Monitor +- power-isa-e.pc; // Embedded.Processor Control +- power-isa-ecl; // Embedded Cache Locking +- power-isa-exp; // External Proxy +- power-isa-fp; // Floating Point +- power-isa-fp.r; // Floating Point.Record +- power-isa-mmc; // Memory Coherence +- power-isa-scpm; // Store Conditional Page Mobility +- power-isa-wt; // Wait +- power-isa-64; // 64-bit +- power-isa-e.pt; // Embedded.Page Table +- power-isa-e.hv.lrat; // Embedded.Hypervisor.LRAT +- power-isa-e.em; // Embedded Multi-Threading +- power-isa-v; // Vector (AltiVec) +- fsl,eref-er; // Enhanced Reservations (Load and Reserve and Store Cond.) +- fsl,eref-deo; // Data Cache Extended Operations +- mmu-type = "power-embedded"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/elo3-dma-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/elo3-dma-0.dtsi +deleted file mode 100644 +index 3c210e0d5201..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/elo3-dma-0.dtsi ++++ /dev/null +@@ -1,82 +0,0 @@ +-/* +- * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x100000 ] +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-dma0: dma@100300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,elo3-dma"; +- reg = <0x100300 0x4>, +- <0x100600 0x4>; +- ranges = <0x0 0x100100 0x500>; +- dma-channel@0 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- interrupts = <28 2 0 0>; +- }; +- dma-channel@80 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- interrupts = <29 2 0 0>; +- }; +- dma-channel@100 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- interrupts = <30 2 0 0>; +- }; +- dma-channel@180 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- interrupts = <31 2 0 0>; +- }; +- dma-channel@300 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x300 0x80>; +- interrupts = <76 2 0 0>; +- }; +- dma-channel@380 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x380 0x80>; +- interrupts = <77 2 0 0>; +- }; +- dma-channel@400 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x400 0x80>; +- interrupts = <78 2 0 0>; +- }; +- dma-channel@480 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x480 0x80>; +- interrupts = <79 2 0 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/elo3-dma-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/elo3-dma-1.dtsi +deleted file mode 100644 +index cccf3bb38224..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/elo3-dma-1.dtsi ++++ /dev/null +@@ -1,82 +0,0 @@ +-/* +- * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x101000 ] +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-dma1: dma@101300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,elo3-dma"; +- reg = <0x101300 0x4>, +- <0x101600 0x4>; +- ranges = <0x0 0x101100 0x500>; +- dma-channel@0 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- interrupts = <32 2 0 0>; +- }; +- dma-channel@80 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- interrupts = <33 2 0 0>; +- }; +- dma-channel@100 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- interrupts = <34 2 0 0>; +- }; +- dma-channel@180 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- interrupts = <35 2 0 0>; +- }; +- dma-channel@300 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x300 0x80>; +- interrupts = <80 2 0 0>; +- }; +- dma-channel@380 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x380 0x80>; +- interrupts = <81 2 0 0>; +- }; +- dma-channel@400 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x400 0x80>; +- interrupts = <82 2 0 0>; +- }; +- dma-channel@480 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x480 0x80>; +- interrupts = <83 2 0 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/elo3-dma-2.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/elo3-dma-2.dtsi +deleted file mode 100644 +index d3cc8d0f7c25..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/elo3-dma-2.dtsi ++++ /dev/null +@@ -1,82 +0,0 @@ +-/* +- * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x102300 ] +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-dma2: dma@102300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,elo3-dma"; +- reg = <0x102300 0x4>, +- <0x102600 0x4>; +- ranges = <0x0 0x102100 0x500>; +- dma-channel@0 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- interrupts = <464 2 0 0>; +- }; +- dma-channel@80 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- interrupts = <465 2 0 0>; +- }; +- dma-channel@100 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- interrupts = <466 2 0 0>; +- }; +- dma-channel@180 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- interrupts = <467 2 0 0>; +- }; +- dma-channel@300 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x300 0x80>; +- interrupts = <468 2 0 0>; +- }; +- dma-channel@380 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x380 0x80>; +- interrupts = <469 2 0 0>; +- }; +- dma-channel@400 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x400 0x80>; +- interrupts = <470 2 0 0>; +- }; +- dma-channel@480 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x480 0x80>; +- interrupts = <471 2 0 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/ge_imp3a.dts b/scripts/dtc/include-prefixes/powerpc/fsl/ge_imp3a.dts +deleted file mode 100644 +index da3de8e2b7d2..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/ge_imp3a.dts ++++ /dev/null +@@ -1,251 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * GE IMP3A Device Tree Source +- * +- * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc. +- * +- * Based on: P2020 DS Device Tree Source +- * Copyright 2009 Freescale Semiconductor Inc. +- */ +- +-/include/ "p2020si-pre.dtsi" +- +-/ { +- model = "GE_IMP3A"; +- compatible = "ge,imp3a"; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@fef05000 { +- reg = <0 0xfef05000 0 0x1000>; +- +- ranges = <0x0 0x0 0x0 0xff000000 0x01000000 +- 0x1 0x0 0x0 0xe0000000 0x08000000 +- 0x2 0x0 0x0 0xe8000000 0x08000000 +- 0x3 0x0 0x0 0xfc100000 0x00020000 +- 0x4 0x0 0x0 0xfc000000 0x00008000 +- 0x5 0x0 0x0 0xfc008000 0x00008000 +- 0x6 0x0 0x0 0xfee00000 0x00040000 +- 0x7 0x0 0x0 0xfee80000 0x00040000>; +- +- /* nor@0,0 is a mirror of part of the memory in nor@1,0 +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ge,imp3a-firmware-mirror", "cfi-flash"; +- reg = <0x0 0x0 0x1000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- label = "firmware"; +- reg = <0x0 0x1000000>; +- read-only; +- }; +- }; +- */ +- +- nor@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "ge,imp3a-paged-flash", "cfi-flash"; +- reg = <0x1 0x0 0x8000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- label = "user"; +- reg = <0x0 0x7800000>; +- }; +- +- partition@7800000 { +- label = "firmware"; +- reg = <0x7800000 0x800000>; +- read-only; +- }; +- }; +- +- nvram@3,0 { +- device_type = "nvram"; +- compatible = "simtek,stk14ca8"; +- reg = <0x3 0x0 0x20000>; +- }; +- +- fpga@4,0 { +- compatible = "ge,imp3a-fpga-regs"; +- reg = <0x4 0x0 0x20>; +- }; +- +- gef_pic: pic@4,20 { +- #interrupt-cells = <1>; +- interrupt-controller; +- device_type = "interrupt-controller"; +- compatible = "ge,imp3a-fpga-pic", "gef,fpga-pic-1.00"; +- reg = <0x4 0x20 0x20>; +- interrupts = <6 7 0 0>; +- }; +- +- gef_gpio: gpio@4,400 { +- #gpio-cells = <2>; +- compatible = "ge,imp3a-gpio"; +- reg = <0x4 0x400 0x24>; +- gpio-controller; +- }; +- +- wdt@4,800 { +- compatible = "ge,imp3a-fpga-wdt", "gef,fpga-wdt-1.00", +- "gef,fpga-wdt"; +- reg = <0x4 0x800 0x8>; +- interrupts = <10 4>; +- interrupt-parent = <&gef_pic>; +- }; +- +- /* Second watchdog available, driver currently supports one. +- wdt@4,808 { +- compatible = "gef,imp3a-fpga-wdt", "gef,fpga-wdt-1.00", +- "gef,fpga-wdt"; +- reg = <0x4 0x808 0x8>; +- interrupts = <9 4>; +- interrupt-parent = <&gef_pic>; +- }; +- */ +- +- nand@6,0 { +- compatible = "fsl,elbc-fcm-nand"; +- reg = <0x6 0x0 0x40000>; +- }; +- +- nand@7,0 { +- compatible = "fsl,elbc-fcm-nand"; +- reg = <0x7 0x0 0x40000>; +- }; +- }; +- +- soc: soc@fef00000 { +- ranges = <0x0 0 0xfef00000 0x100000>; +- +- i2c@3000 { +- hwmon@48 { +- compatible = "national,lm92"; +- reg = <0x48>; +- }; +- +- hwmon@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- +- rtc@51 { +- compatible = "epson,rx8581"; +- reg = <0x51>; +- }; +- +- eti@6b { +- compatible = "dallas,ds1682"; +- reg = <0x6b>; +- }; +- }; +- +- usb@22000 { +- phy_type = "ulpi"; +- dr_mode = "host"; +- }; +- +- mdio@24520 { +- phy0: ethernet-phy@0 { +- interrupt-parent = <&gef_pic>; +- interrupts = <0xc 0x4>; +- reg = <0x1>; +- }; +- phy1: ethernet-phy@1 { +- interrupt-parent = <&gef_pic>; +- interrupts = <0xb 0x4>; +- reg = <0x2>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- mdio@25520 { +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- mdio@26520 { +- status = "disabled"; +- }; +- +- enet0: ethernet@24000 { +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- phy-connection-type = "gmii"; +- }; +- +- enet1: ethernet@25000 { +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- phy-connection-type = "gmii"; +- }; +- +- enet2: ethernet@26000 { +- status = "disabled"; +- }; +- }; +- +- pci0: pcie@fef08000 { +- ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xfe020000 0x0 0x10000>; +- reg = <0 0xfef08000 0 0x1000>; +- +- pcie@0 { +- ranges = <0x2000000 0x0 0xc0000000 +- 0x2000000 0x0 0xc0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x10000>; +- }; +- }; +- +- pci1: pcie@fef09000 { +- reg = <0 0xfef09000 0 0x1000>; +- ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xfe010000 0x0 0x10000>; +- +- pcie@0 { +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x10000>; +- }; +- +- }; +- +- pci2: pcie@fef0a000 { +- reg = <0 0xfef0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xfe000000 0x0 0x10000>; +- +- pcie@0 { +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x10000>; +- }; +- }; +-}; +- +-/include/ "p2020si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/gef_ppc9a.dts b/scripts/dtc/include-prefixes/powerpc/fsl/gef_ppc9a.dts +deleted file mode 100644 +index fc92bb032c51..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/gef_ppc9a.dts ++++ /dev/null +@@ -1,216 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * GE PPC9A Device Tree Source +- * +- * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. +- * +- * Based on: SBS CM6 Device Tree Source +- * Copyright 2007 SBS Technologies GmbH & Co. KG +- * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source) +- * Copyright 2006 Freescale Semiconductor Inc. +- */ +- +-/* +- * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts +- */ +- +-/include/ "mpc8641si-pre.dtsi" +- +-/ { +- model = "GEF_PPC9A"; +- compatible = "gef,ppc9a"; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x40000000>; // set by uboot +- }; +- +- lbc: localbus@fef05000 { +- reg = <0xfef05000 0x1000>; +- +- ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash +- 1 0 0xe8000000 0x08000000 // Paged Flash 0 +- 2 0 0xe0000000 0x08000000 // Paged Flash 1 +- 3 0 0xfc100000 0x00020000 // NVRAM +- 4 0 0xfc000000 0x00008000 // FPGA +- 5 0 0xfc008000 0x00008000 // AFIX FPGA +- 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit) +- 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit) +- +- /* flash@0,0 is a mirror of part of the memory in flash@1,0 +- flash@0,0 { +- compatible = "gef,ppc9a-firmware-mirror", "cfi-flash"; +- reg = <0x0 0x0 0x1000000>; +- bank-width = <4>; +- device-width = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "firmware"; +- reg = <0x0 0x1000000>; +- read-only; +- }; +- }; +- */ +- +- flash@1,0 { +- compatible = "gef,ppc9a-paged-flash", "cfi-flash"; +- reg = <0x1 0x0 0x8000000>; +- bank-width = <4>; +- device-width = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "user"; +- reg = <0x0 0x7800000>; +- }; +- partition@7800000 { +- label = "firmware"; +- reg = <0x7800000 0x800000>; +- read-only; +- }; +- }; +- +- nvram@3,0 { +- device_type = "nvram"; +- compatible = "simtek,stk14ca8"; +- reg = <0x3 0x0 0x20000>; +- }; +- +- fpga@4,0 { +- compatible = "gef,ppc9a-fpga-regs"; +- reg = <0x4 0x0 0x40>; +- }; +- +- wdt@4,2000 { +- compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00", +- "gef,fpga-wdt"; +- reg = <0x4 0x2000 0x8>; +- interrupts = <0x1a 0x4>; +- interrupt-parent = <&gef_pic>; +- }; +- /* Second watchdog available, driver currently supports one. +- wdt@4,2010 { +- compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00", +- "gef,fpga-wdt"; +- reg = <0x4 0x2010 0x8>; +- interrupts = <0x1b 0x4>; +- interrupt-parent = <&gef_pic>; +- }; +- */ +- gef_pic: pic@4,4000 { +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "gef,ppc9a-fpga-pic", "gef,fpga-pic-1.00"; +- reg = <0x4 0x4000 0x20>; +- interrupts = <0x8 0x9 0 0>; +- +- }; +- gef_gpio: gpio@7,14000 { +- #gpio-cells = <2>; +- compatible = "gef,ppc9a-gpio", "gef,sbc610-gpio"; +- reg = <0x7 0x14000 0x24>; +- gpio-controller; +- }; +- }; +- +- soc: soc@fef00000 { +- ranges = <0x0 0xfef00000 0x00100000>; +- +- i2c@3000 { +- hwmon@48 { +- compatible = "national,lm92"; +- reg = <0x48>; +- }; +- +- hwmon@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- +- rtc@51 { +- compatible = "epson,rx8581"; +- reg = <0x00000051>; +- }; +- +- eti@6b { +- compatible = "dallas,ds1682"; +- reg = <0x6b>; +- }; +- }; +- +- enet0: ethernet@24000 { +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- phy-connection-type = "gmii"; +- }; +- +- mdio@24520 { +- phy0: ethernet-phy@0 { +- interrupt-parent = <&gef_pic>; +- interrupts = <0x9 0x4>; +- reg = <1>; +- }; +- phy2: ethernet-phy@2 { +- interrupt-parent = <&gef_pic>; +- interrupts = <0x8 0x4>; +- reg = <3>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet1: ethernet@26000 { +- tbi-handle = <&tbi2>; +- phy-handle = <&phy2>; +- phy-connection-type = "gmii"; +- }; +- +- mdio@26520 { +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet2: ethernet@25000 { +- status = "disabled"; +- }; +- +- mdio@25520 { +- status = "disabled"; +- }; +- +- enet3: ethernet@27000 { +- status = "disabled"; +- }; +- +- mdio@27520 { +- status = "disabled"; +- }; +- }; +- +- pci0: pcie@fef08000 { +- reg = <0xfef08000 0x1000>; +- ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000 +- 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>; +- +- pcie@0 { +- ranges = <0x02000000 0x0 0x80000000 +- 0x02000000 0x0 0x80000000 +- 0x0 0x40000000 +- +- 0x01000000 0x0 0x00000000 +- 0x01000000 0x0 0x00000000 +- 0x0 0x00400000>; +- }; +- }; +- +- pci1: pcie@fef09000 { +- status = "disabled"; +- }; +-}; +- +-/include/ "mpc8641si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/gef_sbc310.dts b/scripts/dtc/include-prefixes/powerpc/fsl/gef_sbc310.dts +deleted file mode 100644 +index 47ae85c34635..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/gef_sbc310.dts ++++ /dev/null +@@ -1,234 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * GE SBC310 Device Tree Source +- * +- * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. +- * +- * Based on: SBS CM6 Device Tree Source +- * Copyright 2007 SBS Technologies GmbH & Co. KG +- * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source) +- * Copyright 2006 Freescale Semiconductor Inc. +- */ +- +-/* +- * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts +- */ +- +-/include/ "mpc8641si-pre.dtsi" +- +-/ { +- model = "GEF_SBC310"; +- compatible = "gef,sbc310"; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x40000000>; // set by uboot +- }; +- +- lbc: localbus@fef05000 { +- reg = <0xfef05000 0x1000>; +- +- ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash +- 1 0 0xe0000000 0x08000000 // Paged Flash 0 +- 2 0 0xe8000000 0x08000000 // Paged Flash 1 +- 3 0 0xfc100000 0x00020000 // NVRAM +- 4 0 0xfc000000 0x00010000>; // FPGA +- +- /* flash@0,0 is a mirror of part of the memory in flash@1,0 +- flash@0,0 { +- compatible = "gef,sbc310-firmware-mirror", "cfi-flash"; +- reg = <0x0 0x0 0x01000000>; +- bank-width = <2>; +- device-width = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "firmware"; +- reg = <0x0 0x01000000>; +- read-only; +- }; +- }; +- */ +- +- flash@1,0 { +- compatible = "gef,sbc310-paged-flash", "cfi-flash"; +- reg = <0x1 0x0 0x8000000>; +- bank-width = <2>; +- device-width = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "user"; +- reg = <0x0 0x7800000>; +- }; +- partition@7800000 { +- label = "firmware"; +- reg = <0x7800000 0x800000>; +- read-only; +- }; +- }; +- +- nvram@3,0 { +- device_type = "nvram"; +- compatible = "simtek,stk14ca8"; +- reg = <0x3 0x0 0x20000>; +- }; +- +- fpga@4,0 { +- compatible = "gef,fpga-regs"; +- reg = <0x4 0x0 0x40>; +- }; +- +- wdt@4,2000 { +- compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00", +- "gef,fpga-wdt"; +- reg = <0x4 0x2000 0x8>; +- interrupts = <0x1a 0x4>; +- interrupt-parent = <&gef_pic>; +- }; +-/* +- wdt@4,2010 { +- compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00", +- "gef,fpga-wdt"; +- reg = <0x4 0x2010 0x8>; +- interrupts = <0x1b 0x4>; +- interrupt-parent = <&gef_pic>; +- }; +-*/ +- gef_pic: pic@4,4000 { +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic"; +- reg = <0x4 0x4000 0x20>; +- interrupts = <0x8 0x9 0 0>; +- +- }; +- gef_gpio: gpio@4,8000 { +- #gpio-cells = <2>; +- compatible = "gef,sbc310-gpio"; +- reg = <0x4 0x8000 0x24>; +- gpio-controller; +- }; +- }; +- +- soc: soc@fef00000 { +- ranges = <0x0 0xfef00000 0x00100000>; +- +- i2c@3000 { +- rtc@51 { +- compatible = "epson,rx8581"; +- reg = <0x00000051>; +- }; +- }; +- +- i2c@3100 { +- hwmon@48 { +- compatible = "national,lm92"; +- reg = <0x48>; +- }; +- +- hwmon@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- +- eti@6b { +- compatible = "dallas,ds1682"; +- reg = <0x6b>; +- }; +- }; +- +- enet0: ethernet@24000 { +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- phy-connection-type = "gmii"; +- }; +- +- mdio@24520 { +- phy0: ethernet-phy@0 { +- interrupt-parent = <&gef_pic>; +- interrupts = <0x9 0x4>; +- reg = <1>; +- }; +- phy2: ethernet-phy@2 { +- interrupt-parent = <&gef_pic>; +- interrupts = <0x8 0x4>; +- reg = <3>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet1: ethernet@26000 { +- tbi-handle = <&tbi2>; +- phy-handle = <&phy2>; +- phy-connection-type = "gmii"; +- }; +- +- mdio@26520 { +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet2: ethernet@25000 { +- status = "disabled"; +- }; +- +- mdio@25520 { +- status = "disabled"; +- }; +- +- enet3: ethernet@27000 { +- status = "disabled"; +- }; +- +- mdio@27520 { +- status = "disabled"; +- }; +- }; +- +- pci0: pcie@fef08000 { +- reg = <0xfef08000 0x1000>; +- ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000 +- 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>; +- interrupt-map-mask = <0xff00 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2 +- 0x0000 0x0 0x0 0x2 &mpic 0x1 0x2 +- 0x0000 0x0 0x0 0x3 &mpic 0x2 0x2 +- 0x0000 0x0 0x0 0x4 &mpic 0x3 0x2 +- >; +- +- pcie@0 { +- ranges = <0x02000000 0x0 0x80000000 +- 0x02000000 0x0 0x80000000 +- 0x0 0x40000000 +- +- 0x01000000 0x0 0x00000000 +- 0x01000000 0x0 0x00000000 +- 0x0 0x00400000>; +- }; +- }; +- +- pci1: pcie@fef09000 { +- reg = <0xfef09000 0x1000>; +- ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000 +- 0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>; +- +- pcie@0 { +- ranges = <0x02000000 0x0 0xc0000000 +- 0x02000000 0x0 0xc0000000 +- 0x0 0x20000000 +- +- 0x01000000 0x0 0x00000000 +- 0x01000000 0x0 0x00000000 +- 0x0 0x00400000>; +- }; +- }; +-}; +- +-/include/ "mpc8641si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/gef_sbc610.dts b/scripts/dtc/include-prefixes/powerpc/fsl/gef_sbc610.dts +deleted file mode 100644 +index 5322be44b62e..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/gef_sbc610.dts ++++ /dev/null +@@ -1,214 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * GE SBC610 Device Tree Source +- * +- * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. +- * +- * Based on: SBS CM6 Device Tree Source +- * Copyright 2007 SBS Technologies GmbH & Co. KG +- * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source) +- * Copyright 2006 Freescale Semiconductor Inc. +- */ +- +-/* +- * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts +- */ +- +-/include/ "mpc8641si-pre.dtsi" +- +-/ { +- model = "GEF_SBC610"; +- compatible = "gef,sbc610"; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x40000000>; // set by uboot +- }; +- +- lbc: localbus@fef05000 { +- reg = <0xfef05000 0x1000>; +- +- ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash +- 1 0 0xe8000000 0x08000000 // Paged Flash 0 +- 2 0 0xe0000000 0x08000000 // Paged Flash 1 +- 3 0 0xfc100000 0x00020000 // NVRAM +- 4 0 0xfc000000 0x00008000 // FPGA +- 5 0 0xfc008000 0x00008000 // AFIX FPGA +- 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit) +- 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit) +- +- /* flash@0,0 is a mirror of part of the memory in flash@1,0 +- flash@0,0 { +- compatible = "gef,sbc610-firmware-mirror", "cfi-flash"; +- reg = <0x0 0x0 0x1000000>; +- bank-width = <4>; +- device-width = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "firmware"; +- reg = <0x0 0x1000000>; +- read-only; +- }; +- }; +- */ +- +- flash@1,0 { +- compatible = "gef,sbc610-paged-flash", "cfi-flash"; +- reg = <0x1 0x0 0x8000000>; +- bank-width = <4>; +- device-width = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "user"; +- reg = <0x0 0x7800000>; +- }; +- partition@7800000 { +- label = "firmware"; +- reg = <0x7800000 0x800000>; +- read-only; +- }; +- }; +- +- nvram@3,0 { +- device_type = "nvram"; +- compatible = "simtek,stk14ca8"; +- reg = <0x3 0x0 0x20000>; +- }; +- +- fpga@4,0 { +- compatible = "gef,fpga-regs"; +- reg = <0x4 0x0 0x40>; +- }; +- +- wdt@4,2000 { +- compatible = "gef,fpga-wdt"; +- reg = <0x4 0x2000 0x8>; +- interrupts = <0x1a 0x4>; +- interrupt-parent = <&gef_pic>; +- }; +- /* Second watchdog available, driver currently supports one. +- wdt@4,2010 { +- compatible = "gef,fpga-wdt"; +- reg = <0x4 0x2010 0x8>; +- interrupts = <0x1b 0x4>; +- interrupt-parent = <&gef_pic>; +- }; +- */ +- gef_pic: pic@4,4000 { +- #interrupt-cells = <1>; +- interrupt-controller; +- compatible = "gef,fpga-pic"; +- reg = <0x4 0x4000 0x20>; +- interrupts = <0x8 0x9 0 0>; +- +- }; +- gef_gpio: gpio@7,14000 { +- #gpio-cells = <2>; +- compatible = "gef,sbc610-gpio"; +- reg = <0x7 0x14000 0x24>; +- gpio-controller; +- }; +- }; +- +- soc: soc@fef00000 { +- ranges = <0x0 0xfef00000 0x00100000>; +- +- i2c@3000 { +- hwmon@48 { +- compatible = "national,lm92"; +- reg = <0x48>; +- }; +- +- hwmon@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- +- rtc@51 { +- compatible = "epson,rx8581"; +- reg = <0x00000051>; +- }; +- +- eti@6b { +- compatible = "dallas,ds1682"; +- reg = <0x6b>; +- }; +- }; +- +- enet0: ethernet@24000 { +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- phy-connection-type = "gmii"; +- }; +- +- mdio@24520 { +- phy0: ethernet-phy@0 { +- interrupt-parent = <&gef_pic>; +- interrupts = <0x9 0x4>; +- reg = <1>; +- }; +- phy2: ethernet-phy@2 { +- interrupt-parent = <&gef_pic>; +- interrupts = <0x8 0x4>; +- reg = <3>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet1: ethernet@26000 { +- tbi-handle = <&tbi2>; +- phy-handle = <&phy2>; +- phy-connection-type = "gmii"; +- }; +- +- mdio@26520 { +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet2: ethernet@25000 { +- status = "disabled"; +- }; +- +- mdio@25520 { +- status = "disabled"; +- }; +- +- enet3: ethernet@27000 { +- status = "disabled"; +- }; +- +- mdio@27520 { +- status = "disabled"; +- }; +- }; +- +- pci0: pcie@fef08000 { +- reg = <0xfef08000 0x1000>; +- ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000 +- 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>; +- +- pcie@0 { +- ranges = <0x02000000 0x0 0x80000000 +- 0x02000000 0x0 0x80000000 +- 0x0 0x40000000 +- +- 0x01000000 0x0 0x00000000 +- 0x01000000 0x0 0x00000000 +- 0x0 0x00400000>; +- }; +- }; +- +- pci1: pcie@fef09000 { +- status = "disabled"; +- }; +-}; +- +-/include/ "mpc8641si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/interlaken-lac-portals.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/interlaken-lac-portals.dtsi +deleted file mode 100644 +index 9cffccf4e07e..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/interlaken-lac-portals.dtsi ++++ /dev/null +@@ -1,156 +0,0 @@ +-/* T4240 Interlaken LAC Portal device tree stub with 24 portals. +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#address-cells = <0x1>; +-#size-cells = <0x1>; +-compatible = "fsl,interlaken-lac-portals"; +- +-lportal0: lac-portal@0 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0x0 0x1000>; +-}; +- +-lportal1: lac-portal@1000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0x1000 0x1000>; +-}; +- +-lportal2: lac-portal@2000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0x2000 0x1000>; +-}; +- +-lportal3: lac-portal@3000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0x3000 0x1000>; +-}; +- +-lportal4: lac-portal@4000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0x4000 0x1000>; +-}; +- +-lportal5: lac-portal@5000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0x5000 0x1000>; +-}; +- +-lportal6: lac-portal@6000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0x6000 0x1000>; +-}; +- +-lportal7: lac-portal@7000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0x7000 0x1000>; +-}; +- +-lportal8: lac-portal@8000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0x8000 0x1000>; +-}; +- +-lportal9: lac-portal@9000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0x9000 0x1000>; +-}; +- +-lportal10: lac-portal@A000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0xA000 0x1000>; +-}; +- +-lportal11: lac-portal@B000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0xB000 0x1000>; +-}; +- +-lportal12: lac-portal@C000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0xC000 0x1000>; +-}; +- +-lportal13: lac-portal@D000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0xD000 0x1000>; +-}; +- +-lportal14: lac-portal@E000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0xE000 0x1000>; +-}; +- +-lportal15: lac-portal@F000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0xF000 0x1000>; +-}; +- +-lportal16: lac-portal@10000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0x10000 0x1000>; +-}; +- +-lportal17: lac-portal@11000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0x11000 0x1000>; +-}; +- +-lportal18: lac-portal@1200 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0x12000 0x1000>; +-}; +- +-lportal19: lac-portal@13000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0x13000 0x1000>; +-}; +- +-lportal20: lac-portal@14000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0x14000 0x1000>; +-}; +- +-lportal21: lac-portal@15000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0x15000 0x1000>; +-}; +- +-lportal22: lac-portal@16000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0x16000 0x1000>; +-}; +- +-lportal23: lac-portal@17000 { +- compatible = "fsl,interlaken-lac-portal-v1.0"; +- reg = <0x17000 0x1000>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/interlaken-lac.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/interlaken-lac.dtsi +deleted file mode 100644 +index e8208720ac0e..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/interlaken-lac.dtsi ++++ /dev/null +@@ -1,45 +0,0 @@ +-/* +- * T4 Interlaken Look-aside Controller (LAC) device tree stub +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-lac: lac@229000 { +- compatible = "fsl,interlaken-lac"; +- reg = <0x229000 0x1000>; +- interrupts = <16 2 1 18>; +-}; +- +-lac-hv@228000 { +- compatible = "fsl,interlaken-lac-hv"; +- reg = <0x228000 0x1000>; +- fsl,non-hv-node = <&lac>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/kmcent2.dts b/scripts/dtc/include-prefixes/powerpc/fsl/kmcent2.dts +deleted file mode 100644 +index 8e7f0828af29..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/kmcent2.dts ++++ /dev/null +@@ -1,339 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Keymile kmcent2 Device Tree Source, based on T1040RDB DTS +- * +- * (C) Copyright 2016 +- * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com +- * +- * Copyright 2014 - 2015 Freescale Semiconductor Inc. +- */ +- +-/include/ "t104xsi-pre.dtsi" +- +-/ { +- model = "keymile,kmcent2"; +- compatible = "keymile,kmcent2"; +- +- aliases { +- front_phy = &front_phy; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- ifc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x2000>; +- ranges = <0 0 0xf 0xe8000000 0x04000000 +- 1 0 0xf 0xfa000000 0x00010000 +- 2 0 0xf 0xfb000000 0x00010000 +- 4 0 0xf 0xc0000000 0x08000000 +- 6 0 0xf 0xd0000000 0x08000000 +- 7 0 0xf 0xd8000000 0x08000000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x04000000>; +- bank-width = <2>; +- device-width = <2>; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,ifc-nand"; +- reg = <0x1 0x0 0x10000>; +- }; +- +- board-control@2,0 { +- compatible = "keymile,qriox"; +- reg = <0x2 0x0 0x80>; +- }; +- +- chassis-mgmt@6,0 { +- compatible = "keymile,bfticu"; +- reg = <6 0 0x100>; +- interrupt-controller; +- interrupt-parent = <&mpic>; +- interrupts = <11 1 0 0>; +- #interrupt-cells = <1>; +- }; +- +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01072000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x2000000>; +- }; +- +- qportals: qman-portals@ff6000000 { +- ranges = <0x0 0xf 0xf6000000 0x2000000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- +- spi@110000 { +- network-clock@1 { +- compatible = "zarlink,zl30364"; +- reg = <1>; +- spi-max-frequency = <1000000>; +- }; +- }; +- +- sdhc@114000 { +- status = "disabled"; +- }; +- +- i2c@118000 { +- clock-frequency = <100000>; +- +- mux@70 { +- compatible = "nxp,pca9547"; +- reg = <0x70>; +- #address-cells = <1>; +- #size-cells = <0>; +- i2c-mux-idle-disconnect; +- +- i2c@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- eeprom@54 { +- compatible = "atmel,24c02"; +- reg = <0x54>; +- pagesize = <2>; +- read-only; +- label = "ddr3-spd"; +- }; +- }; +- +- i2c@7 { +- reg = <7>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- temp-sensor@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- label = "SENSOR_0"; +- }; +- temp-sensor@4a { +- compatible = "national,lm75"; +- reg = <0x4a>; +- label = "SENSOR_2"; +- }; +- temp-sensor@4b { +- compatible = "national,lm75"; +- reg = <0x4b>; +- label = "SENSOR_3"; +- }; +- }; +- }; +- }; +- +- i2c@118100 { +- clock-frequency = <100000>; +- +- eeprom@50 { +- compatible = "atmel,24c08"; +- reg = <0x50>; +- pagesize = <16>; +- }; +- +- eeprom@54 { +- compatible = "atmel,24c08"; +- reg = <0x54>; +- pagesize = <16>; +- }; +- }; +- +- i2c@119000 { +- status = "disabled"; +- }; +- +- i2c@119100 { +- status = "disabled"; +- }; +- +- serial2: serial@11d500 { +- status = "disabled"; +- }; +- +- serial3: serial@11d600 { +- status = "disabled"; +- }; +- +- usb0: usb@210000 { +- status = "disabled"; +- }; +- usb1: usb@211000 { +- status = "disabled"; +- }; +- +- display@180000 { +- status = "disabled"; +- }; +- +- sata@220000 { +- status = "disabled"; +- }; +- sata@221000 { +- status = "disabled"; +- }; +- +- fman@400000 { +- ethernet@e0000 { +- phy-mode = "sgmii"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- ethernet@e2000 { +- phy-mode = "sgmii"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- ethernet@e4000 { +- status = "disabled"; +- }; +- +- ethernet@e6000 { +- status = "disabled"; +- }; +- +- ethernet@e8000 { +- phy-handle = <&front_phy>; +- phy-mode = "rgmii-id"; +- }; +- +- mdio0: mdio@fc000 { +- front_phy: ethernet-phy@11 { +- reg = <0x11>; +- }; +- }; +- }; +- }; +- +- +- pci0: pcie@ffe240000 { +- reg = <0xf 0xfe240000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci1: pcie@ffe250000 { +- status = "disabled"; +- reg = <0xf 0xfe250000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000 +- 0x01000000 0 0 0xf 0xf8010000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci2: pcie@ffe260000 { +- status = "disabled"; +- reg = <0xf 0xfe260000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci3: pcie@ffe270000 { +- status = "disabled"; +- reg = <0xf 0xfe270000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- qe: qe@ffe140000 { +- ranges = <0x0 0xf 0xfe140000 0x40000>; +- reg = <0xf 0xfe140000 0 0x480>; +- brg-frequency = <0>; +- bus-frequency = <0>; +- +- si1: si@700 { +- compatible = "fsl,t1040-qe-si"; +- reg = <0x700 0x80>; +- }; +- +- siram1: siram@1000 { +- compatible = "fsl,t1040-qe-siram"; +- reg = <0x1000 0x800>; +- }; +- +- ucc_hdlc: ucc@2000 { +- device_type = "hdlc"; +- compatible = "fsl,ucc-hdlc"; +- rx-clock-name = "clk9"; +- tx-clock-name = "clk9"; +- fsl,hdlc-bus; +- }; +- }; +-}; +- +-#include "t1040si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/kmcoge4.dts b/scripts/dtc/include-prefixes/powerpc/fsl/kmcoge4.dts +deleted file mode 100644 +index 1c5f942311ee..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/kmcoge4.dts ++++ /dev/null +@@ -1,216 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Keymile kmcoge4 Device Tree Source, based on the P2041RDB DTS +- * +- * (C) Copyright 2014 +- * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- */ +- +-/include/ "p2041si-pre.dtsi" +- +-/ { +- model = "keymile,kmcoge4"; +- compatible = "keymile,kmcoge4", "keymile,kmp204x"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- memory { +- device_type = "memory"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01008000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x200000>; +- }; +- +- qportals: qman-portals@ff4200000 { +- ranges = <0x0 0xf 0xf4200000 0x200000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- spi@110000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25fl256s1", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <20000000>; /* input clock */ +- }; +- +- network_clock@1 { +- compatible = "zarlink,zl30343"; +- reg = <1>; +- spi-max-frequency = <8000000>; +- }; +- +- flash@2 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,m25p32", "jedec,spi-nor"; +- reg = <2>; +- spi-max-frequency = <15000000>; +- }; +- }; +- +- sdhc@114000 { +- status = "disabled"; +- }; +- +- i2c@119000 { +- status = "disabled"; +- }; +- +- i2c@119100 { +- status = "disabled"; +- }; +- +- usb0: usb@210000 { +- status = "disabled"; +- }; +- +- usb1: usb@211000 { +- status = "disabled"; +- }; +- +- sata@220000 { +- status = "disabled"; +- }; +- +- sata@221000 { +- status = "disabled"; +- }; +- +- fman0: fman@400000 { +- enet0: ethernet@e0000 { +- phy-connection-type = "sgmii"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- mdio0: mdio@e1120 { +- front_phy: ethernet-phy@11 { +- reg = <0x11>; +- }; +- }; +- +- enet1: ethernet@e2000 { +- phy-connection-type = "sgmii"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- enet2: ethernet@e4000 { +- status = "disabled"; +- }; +- +- enet3: ethernet@e6000 { +- status = "disabled"; +- }; +- enet4: ethernet@e8000 { +- phy-handle = <&front_phy>; +- phy-connection-type = "rgmii"; +- }; +- enet5: ethernet@f0000 { +- status = "disabled"; +- }; +- }; +- }; +- +- rio: rapidio@ffe0c0000 { +- status = "disabled"; +- }; +- +- lbc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x1000>; +- ranges = <0 0 0xf 0xffa00000 0x00040000 /* LB 0 */ +- 1 0 0xf 0xfb000000 0x00010000 /* LB 1 */ +- 2 0 0xf 0xd0000000 0x10000000 /* LB 2 */ +- 3 0 0xf 0xe0000000 0x10000000>; /* LB 3 */ +- +- nand@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,elbc-fcm-nand"; +- reg = <0 0 0x40000>; +- }; +- +- board-control@1,0 { +- compatible = "keymile,qriox"; +- reg = <1 0 0x80>; +- }; +- +- chassis-mgmt@3,0 { +- compatible = "keymile,bfticu"; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <3 0 0x100>; +- interrupt-parent = <&mpic>; +- interrupts = <6 1 0 0>; +- }; +- }; +- +- pci0: pcie@ffe200000 { +- reg = <0xf 0xfe200000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci1: pcie@ffe201000 { +- status = "disabled"; +- }; +- +- pci2: pcie@ffe202000 { +- reg = <0xf 0xfe202000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +-}; +- +-/include/ "p2041si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8536ds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8536ds.dts +deleted file mode 100644 +index ab6997a0fd1b..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8536ds.dts ++++ /dev/null +@@ -1,105 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8536 DS Device Tree Source +- * +- * Copyright 2008, 2011 Freescale Semiconductor, Inc. +- */ +- +-/include/ "mpc8536si-pre.dtsi" +- +-/ { +- model = "fsl,mpc8536ds"; +- compatible = "fsl,mpc8536ds"; +- +- cpus { +- #cpus = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8536@0 { +- device_type = "cpu"; +- reg = <0>; +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0 0 0 0>; // Filled by U-Boot +- }; +- +- lbc: localbus@ffe05000 { +- reg = <0 0xffe05000 0 0x1000>; +- +- ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 +- 0x2 0x0 0x0 0xffa00000 0x00040000 +- 0x3 0x0 0x0 0xffdf0000 0x00008000>; +- }; +- +- board_soc: soc: soc@ffe00000 { +- ranges = <0x0 0 0xffe00000 0x100000>; +- }; +- +- pci0: pci@ffe08000 { +- reg = <0 0xffe08000 0 0x1000>; +- ranges = <0x02000000 0 0x80000000 0 0x80000000 0 0x10000000 +- 0x01000000 0 0x00000000 0 0xffc00000 0 0x00010000>; +- clock-frequency = <66666666>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x11 J17 Slot 1 */ +- 0x8800 0 0 1 &mpic 1 1 0 0 +- 0x8800 0 0 2 &mpic 2 1 0 0 +- 0x8800 0 0 3 &mpic 3 1 0 0 +- 0x8800 0 0 4 &mpic 4 1 0 0>; +- }; +- +- pci1: pcie@ffe09000 { +- reg = <0 0xffe09000 0 0x1000>; +- ranges = <0x02000000 0 0x98000000 0 0x98000000 0 0x08000000 +- 0x01000000 0 0x00000000 0 0xffc20000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0x98000000 +- 0x02000000 0 0x98000000 +- 0 0x08000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci2: pcie@ffe0a000 { +- reg = <0 0xffe0a000 0 0x1000>; +- ranges = <0x02000000 0 0x90000000 0 0x90000000 0 0x08000000 +- 0x01000000 0 0x00000000 0 0xffc10000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0x90000000 +- 0x02000000 0 0x90000000 +- 0 0x08000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci3: pcie@ffe0b000 { +- reg = <0 0xffe0b000 0 0x1000>; +- ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000 +- 0x01000000 0 0x00000000 0 0xffc30000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xa0000000 +- 0x02000000 0 0xa0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00100000>; +- }; +- }; +-}; +- +-/include/ "mpc8536si-post.dtsi" +-/include/ "mpc8536ds.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8536ds.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8536ds.dtsi +deleted file mode 100644 +index a925fe49a73e..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8536ds.dtsi ++++ /dev/null +@@ -1,244 +0,0 @@ +-/* +- * MPC8536DS Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&lbc { +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- reg = <0x0 0x03000000>; +- label = "ramdisk-nor"; +- }; +- +- partition@3000000 { +- reg = <0x03000000 0x00e00000>; +- label = "diagnostic-nor"; +- read-only; +- }; +- +- partition@3e00000 { +- reg = <0x03e00000 0x00200000>; +- label = "dink-nor"; +- read-only; +- }; +- +- partition@4000000 { +- reg = <0x04000000 0x00400000>; +- label = "kernel-nor"; +- }; +- +- partition@4400000 { +- reg = <0x04400000 0x03b00000>; +- label = "fs-nor"; +- }; +- +- partition@7f00000 { +- reg = <0x07f00000 0x00080000>; +- label = "dtb-nor"; +- }; +- +- partition@7f80000 { +- reg = <0x07f80000 0x00080000>; +- label = "u-boot-nor"; +- read-only; +- }; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8536-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x2 0x0 0x40000>; +- +- partition@0 { +- reg = <0x0 0x02000000>; +- label = "u-boot-nand"; +- read-only; +- }; +- +- partition@2000000 { +- reg = <0x02000000 0x10000000>; +- label = "fs-nand"; +- }; +- +- partition@12000000 { +- reg = <0x12000000 0x08000000>; +- label = "ramdisk-nand"; +- }; +- +- partition@1a000000 { +- reg = <0x1a000000 0x04000000>; +- label = "kernel-nand"; +- }; +- +- partition@1e000000 { +- reg = <0x1e000000 0x01000000>; +- label = "dtb-nand"; +- }; +- +- partition@1f000000 { +- reg = <0x1f000000 0x21000000>; +- label = "empty-nand"; +- }; +- }; +- +- board-control@3,0 { +- compatible = "fsl,mpc8536ds-fpga-pixis"; +- reg = <0x3 0x0 0x8000>; +- }; +-}; +- +-&board_soc { +- i2c@3100 { +- rtc@68 { +- compatible = "dallas,ds3232"; +- reg = <0x68>; +- interrupts = <0 0x1 0 0>; +- }; +- adt7461@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- }; +- +- spi@7000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; +- partition@u-boot { +- label = "u-boot"; +- reg = <0x00000000 0x00100000>; +- read-only; +- }; +- partition@kernel { +- label = "kernel"; +- reg = <0x00100000 0x00500000>; +- read-only; +- }; +- partition@dtb { +- label = "dtb"; +- reg = <0x00600000 0x00100000>; +- read-only; +- }; +- partition@fs { +- label = "file system"; +- reg = <0x00700000 0x00900000>; +- }; +- }; +- flash@1 { +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <1>; +- spi-max-frequency = <40000000>; +- }; +- flash@2 { +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <2>; +- spi-max-frequency = <40000000>; +- }; +- flash@3 { +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <3>; +- spi-max-frequency = <40000000>; +- }; +- }; +- +- usb@22000 { +- phy_type = "ulpi"; +- }; +- +- usb@23000 { +- phy_type = "ulpi"; +- }; +- +- enet0: ethernet@24000 { +- tbi-handle = <&tbi0>; +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@24520 { +- phy0: ethernet-phy@0 { +- interrupts = <10 0x1 0 0>; +- reg = <0>; +- }; +- phy1: ethernet-phy@1 { +- interrupts = <10 0x1 0 0>; +- reg = <1>; +- }; +- sgmii_phy0: sgmii-phy@0 { +- interrupts = <6 1 0 0>; +- reg = <0x1d>; +- }; +- sgmii_phy1: sgmii-phy@1 { +- interrupts = <6 1 0 0>; +- reg = <0x1c>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet2: ethernet@26000 { +- tbi-handle = <&tbi1>; +- phy-handle = <&phy0>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@26520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x26520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- usb@2b000 { +- dr_mode = "peripheral"; +- phy_type = "ulpi"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8536ds_36b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8536ds_36b.dts +deleted file mode 100644 +index 1b799741cd46..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8536ds_36b.dts ++++ /dev/null +@@ -1,105 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8536DS Device Tree Source (36-bit address map) +- * +- * Copyright 2008-2009, 2011 Freescale Semiconductor, Inc. +- */ +- +-/include/ "mpc8536si-pre.dtsi" +- +-/ { +- model = "fsl,mpc8536ds"; +- compatible = "fsl,mpc8536ds"; +- +- cpus { +- #cpus = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8536@0 { +- device_type = "cpu"; +- reg = <0>; +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0 0 0 0>; // Filled by U-Boot +- }; +- +- lbc: localbus@fffe05000 { +- reg = <0xf 0xffe05000 0 0x1000>; +- +- ranges = <0x0 0x0 0xf 0xe8000000 0x08000000 +- 0x2 0x0 0xf 0xffa00000 0x00040000 +- 0x3 0x0 0xf 0xffdf0000 0x00008000>; +- }; +- +- board_soc: soc: soc@fffe00000 { +- ranges = <0x0 0xf 0xffe00000 0x100000>; +- }; +- +- pci0: pci@fffe08000 { +- reg = <0xf 0xffe08000 0 0x1000>; +- ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>; +- clock-frequency = <66666666>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x11 J17 Slot 1 */ +- 0x8800 0 0 1 &mpic 1 1 0 0 +- 0x8800 0 0 2 &mpic 2 1 0 0 +- 0x8800 0 0 3 &mpic 3 1 0 0 +- 0x8800 0 0 4 &mpic 4 1 0 0>; +- }; +- +- pci1: pcie@fffe09000 { +- reg = <0xf 0xffe09000 0 0x1000>; +- ranges = <0x02000000 0 0xf8000000 0xc 0x18000000 0 0x08000000 +- 0x01000000 0 0x00000000 0xf 0xffc20000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xf8000000 +- 0x02000000 0 0xf8000000 +- 0 0x08000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci2: pcie@fffe0a000 { +- reg = <0xf 0xffe0a000 0 0x1000>; +- ranges = <0x02000000 0 0xf8000000 0xc 0x10000000 0 0x08000000 +- 0x01000000 0 0x00000000 0xf 0xffc10000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xf8000000 +- 0x02000000 0 0xf8000000 +- 0 0x08000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci3: pcie@fffe0b000 { +- reg = <0xf 0xffe0b000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xffc30000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00100000>; +- }; +- }; +-}; +- +-/include/ "mpc8536si-post.dtsi" +-/include/ "mpc8536ds.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8536si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8536si-post.dtsi +deleted file mode 100644 +index 41935709ebe8..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8536si-post.dtsi ++++ /dev/null +@@ -1,252 +0,0 @@ +-/* +- * MPC8536 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&lbc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8536-elbc", "fsl,elbc", "simple-bus"; +- interrupts = <19 2 0 0>; +-}; +- +-/* controller at 0x8000 */ +-&pci0 { +- compatible = "fsl,mpc8540-pci"; +- device_type = "pci"; +- interrupts = <24 0x2 0 0>; +- bus-range = <0 0xff>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +-}; +- +-/* controller at 0x9000 */ +-&pci1 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <25 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <25 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 +- >; +- }; +-}; +- +-/* controller at 0xa000 */ +-&pci2 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <26 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <26 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 +- >; +- }; +-}; +- +-/* controller at 0xb000 */ +-&pci3 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <27 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <27 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0 +- >; +- }; +-}; +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,mpc8536-immr", "simple-bus"; +- bus-frequency = <0>; // Filled out by uboot. +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <12>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8536-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2 0 0>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8536-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupts = <18 2 0 0>; +- }; +- +-/include/ "pq3-i2c-0.dtsi" +-/include/ "pq3-i2c-1.dtsi" +-/include/ "pq3-duart-0.dtsi" +- +-/include/ "pq3-espi-0.dtsi" +- spi@7000 { +- fsl,espi-num-chipselects = <4>; +- }; +- +-/include/ "pq3-gpio-0.dtsi" +- +- /* mark compat w/8572 to get some erratum treatment */ +- gpio-controller@f000 { +- compatible = "fsl,mpc8572-gpio"; +- }; +- +- sata@18000 { +- compatible = "fsl,mpc8536-sata", "fsl,pq-sata"; +- reg = <0x18000 0x1000>; +- cell-index = <1>; +- interrupts = <74 0x2 0 0>; +- }; +- +- sata@19000 { +- compatible = "fsl,mpc8536-sata", "fsl,pq-sata"; +- reg = <0x19000 0x1000>; +- cell-index = <2>; +- interrupts = <41 0x2 0 0>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8536-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x80000>; // L2, 512K +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-dma-0.dtsi" +-/include/ "pq3-etsec1-0.dtsi" +-/include/ "pq3-etsec1-timer-0.dtsi" +- +- usb@22000 { +- compatible = "fsl-usb2-mph-v1.2", "fsl,mpc8536-usb2-mph", "fsl-usb2-mph"; +- reg = <0x22000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <28 0x2 0 0>; +- }; +- +- usb@23000 { +- compatible = "fsl-usb2-mph-v1.2", "fsl,mpc8536-usb2-mph", "fsl-usb2-mph"; +- reg = <0x23000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <46 0x2 0 0>; +- }; +- +- ptp_clock@24e00 { +- interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>; +- }; +- +-/include/ "pq3-etsec1-2.dtsi" +- +- ethernet@26000 { +- cell-index = <1>; +- }; +- +- usb@2b000 { +- compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr"; +- reg = <0x2b000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <60 0x2 0 0>; +- }; +- +-/include/ "pq3-esdhc-0.dtsi" +- sdhc@2e000 { +- compatible = "fsl,mpc8536-esdhc", "fsl,esdhc"; +- }; +- +-/include/ "pq3-sec3.0-0.dtsi" +-/include/ "pq3-mpic.dtsi" +-/include/ "pq3-mpic-timer-B.dtsi" +- +- global-utilities@e0000 { +- compatible = "fsl,mpc8536-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8536si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8536si-pre.dtsi +deleted file mode 100644 +index 152906f98a0f..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8536si-pre.dtsi ++++ /dev/null +@@ -1,66 +0,0 @@ +-/* +- * MPC8536 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e500v2_power_isa.dtsi" +- +-/ { +- compatible = "fsl,MPC8536"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- ethernet0 = &enet0; +- ethernet1 = &enet2; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- pci3 = &pci3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8536@0 { +- device_type = "cpu"; +- reg = <0x0>; +- next-level-cache = <&L2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8540ads.dts b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8540ads.dts +deleted file mode 100644 +index 18a885130538..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8540ads.dts ++++ /dev/null +@@ -1,355 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8540 ADS Device Tree Source +- * +- * Copyright 2006, 2008 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/include/ "e500v2_power_isa.dtsi" +- +-/ { +- model = "MPC8540ADS"; +- compatible = "MPC8540ADS", "MPC85xxADS"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8540@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <0x8000>; // L1, 32K +- i-cache-size = <0x8000>; // L1, 32K +- timebase-frequency = <0>; // 33 MHz, from uboot +- bus-frequency = <0>; // 166 MHz +- clock-frequency = <0>; // 825 MHz, from uboot +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x8000000>; // 128M at 0x0 +- }; +- +- soc8540@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- ranges = <0x0 0xe0000000 0x100000>; +- bus-frequency = <0>; +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <8>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8540-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8540-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8540-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x40000>; // L2, 256K +- interrupt-parent = <&mpic>; +- interrupts = <16 2>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8540-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8540-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8540-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8540-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 30 2 34 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy0: ethernet-phy@0 { +- interrupt-parent = <&mpic>; +- interrupts = <5 1>; +- reg = <0x0>; +- }; +- phy1: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <5 1>; +- reg = <0x1>; +- }; +- phy3: ethernet-phy@3 { +- interrupt-parent = <&mpic>; +- interrupts = <7 1>; +- reg = <0x3>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 2 36 2 40 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet2: ethernet@26000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <2>; +- device_type = "network"; +- model = "FEC"; +- compatible = "gianfar"; +- reg = <0x26000 0x1000>; +- ranges = <0x0 0x26000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <41 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi2>; +- phy-handle = <&phy3>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; // reg base, size +- clock-frequency = <0>; // should we fill in in uboot? +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; // reg base, size +- clock-frequency = <0>; // should we fill in in uboot? +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- compatible = "chrp,open-pic"; +- device_type = "open-pic"; +- }; +- }; +- +- pci0: pci@e0008000 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x02 */ +- 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1 +- 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1 +- 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1 +- 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1 +- +- /* IDSEL 0x03 */ +- 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1 +- 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1 +- +- /* IDSEL 0x04 */ +- 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1 +- 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1 +- 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1 +- 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1 +- +- /* IDSEL 0x05 */ +- 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1 +- 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1 +- 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1 +- 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1 +- +- /* IDSEL 0x0c */ +- 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1 +- 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1 +- 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1 +- 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1 +- +- /* IDSEL 0x0d */ +- 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1 +- 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1 +- +- /* IDSEL 0x0e */ +- 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1 +- 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1 +- 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1 +- 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1 +- +- /* IDSEL 0x0f */ +- 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1 +- 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1 +- 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1 +- 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1 +- +- /* IDSEL 0x12 */ +- 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1 +- 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1 +- 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1 +- 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 +- +- /* IDSEL 0x13 */ +- 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1 +- 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1 +- +- /* IDSEL 0x14 */ +- 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1 +- 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1 +- 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1 +- 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1 +- +- /* IDSEL 0x15 */ +- 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1 +- 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1 +- 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1 +- 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>; +- interrupt-parent = <&mpic>; +- interrupts = <24 2>; +- bus-range = <0 0>; +- ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008000 0x1000>; +- compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; +- device_type = "pci"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8541cds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8541cds.dts +deleted file mode 100644 +index ac381e7b1c60..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8541cds.dts ++++ /dev/null +@@ -1,375 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8541 CDS Device Tree Source +- * +- * Copyright 2006, 2008 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/include/ "e500v2_power_isa.dtsi" +- +-/ { +- model = "MPC8541CDS"; +- compatible = "MPC8541CDS", "MPC85xxCDS"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- pci1 = &pci1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8541@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <0x8000>; // L1, 32K +- i-cache-size = <0x8000>; // L1, 32K +- timebase-frequency = <0>; // 33 MHz, from uboot +- bus-frequency = <0>; // 166 MHz +- clock-frequency = <0>; // 825 MHz, from uboot +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x8000000>; // 128M at 0x0 +- }; +- +- soc8541@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- ranges = <0x0 0xe0000000 0x100000>; +- bus-frequency = <0>; +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <8>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8541-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8541-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8541-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x40000>; // L2, 256K +- interrupt-parent = <&mpic>; +- interrupts = <16 2>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8541-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8541-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8541-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8541-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 30 2 34 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy0: ethernet-phy@0 { +- interrupt-parent = <&mpic>; +- interrupts = <5 1>; +- reg = <0x0>; +- }; +- phy1: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <5 1>; +- reg = <0x1>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 2 36 2 40 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; // reg base, size +- clock-frequency = <0>; // should we fill in in uboot? +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; // reg base, size +- clock-frequency = <0>; // should we fill in in uboot? +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <45 2>; +- interrupt-parent = <&mpic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x7e>; +- fsl,descriptor-types-mask = <0x01010ebf>; +- }; +- +- mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- compatible = "chrp,open-pic"; +- device_type = "open-pic"; +- }; +- +- cpm@919c0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8541-cpm", "fsl,cpm2"; +- reg = <0x919c0 0x30>; +- ranges; +- +- muram@80000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x80000 0x10000>; +- +- data@0 { +- compatible = "fsl,cpm-muram-data"; +- reg = <0x0 0x2000 0x9000 0x1000>; +- }; +- }; +- +- brg@919f0 { +- compatible = "fsl,mpc8541-brg", +- "fsl,cpm2-brg", +- "fsl,cpm-brg"; +- reg = <0x919f0 0x10 0x915f0 0x10>; +- }; +- +- cpmpic: pic@90c00 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <46 2>; +- interrupt-parent = <&mpic>; +- reg = <0x90c00 0x80>; +- compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; +- }; +- }; +- }; +- +- pci0: pci@e0008000 { +- interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x10 */ +- 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1 +- 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1 +- +- /* IDSEL 0x11 */ +- 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1 +- 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1 +- +- /* IDSEL 0x12 (Slot 1) */ +- 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1 +- 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1 +- +- /* IDSEL 0x13 (Slot 2) */ +- 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1 +- 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1 +- 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1 +- 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1 +- +- /* IDSEL 0x14 (Slot 3) */ +- 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1 +- 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1 +- 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1 +- 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1 +- +- /* IDSEL 0x15 (Slot 4) */ +- 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1 +- 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1 +- 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1 +- 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1 +- +- /* Bus 1 (Tundra Bridge) */ +- /* IDSEL 0x12 (ISA bridge) */ +- 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1 +- 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>; +- interrupt-parent = <&mpic>; +- interrupts = <24 2>; +- bus-range = <0 0>; +- ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008000 0x1000>; +- compatible = "fsl,mpc8540-pci"; +- device_type = "pci"; +- +- i8259@19000 { +- interrupt-controller; +- device_type = "interrupt-controller"; +- reg = <0x19000 0x0 0x0 0x0 0x1>; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- compatible = "chrp,iic"; +- interrupts = <1>; +- interrupt-parent = <&pci0>; +- }; +- }; +- +- pci1: pci@e0009000 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x15 */ +- 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 +- 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1 +- 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1 +- 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>; +- interrupt-parent = <&mpic>; +- interrupts = <25 2>; +- bus-range = <0 0>; +- ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0009000 0x1000>; +- compatible = "fsl,mpc8540-pci"; +- device_type = "pci"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8544ds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8544ds.dts +deleted file mode 100644 +index f4a8b71396a5..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8544ds.dts ++++ /dev/null +@@ -1,103 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8544 DS Device Tree Source +- * +- * Copyright 2007, 2008 Freescale Semiconductor Inc. +- */ +- +-/include/ "mpc8544si-pre.dtsi" +- +-/ { +- model = "MPC8544DS"; +- compatible = "MPC8544DS", "MPC85xxDS"; +- +- memory { +- device_type = "memory"; +- reg = <0 0 0 0>; // Filled by U-Boot +- }; +- +- board_lbc: lbc: localbus@e0005000 { +- reg = <0 0xe0005000 0 0x1000>; +- +- ranges = <0x0 0x0 0x0 0xff800000 0x800000>; +- }; +- +- board_soc: soc: soc8544@e0000000 { +- ranges = <0x0 0x0 0xe0000000 0x100000>; +- }; +- +- pci0: pci@e0008000 { +- reg = <0 0xe0008000 0 0x1000>; +- ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>; +- clock-frequency = <66666666>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x11 J17 Slot 1 */ +- 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 +- 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 +- 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0 +- 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 +- +- /* IDSEL 0x12 J16 Slot 2 */ +- +- 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0 +- 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0 +- 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 +- 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0>; +- }; +- +- pci1: pcie@e0009000 { +- reg = <0x0 0xe0009000 0x0 0x1000>; +- ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xe1010000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x10000>; +- }; +- }; +- +- pci2: pcie@e000a000 { +- reg = <0x0 0xe000a000 0x0 0x1000>; +- ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000 +- 0x1000000 0x0 0x00000000 0 0xe1020000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x10000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x10000>; +- }; +- }; +- +- board_pci3: pci3: pcie@e000b000 { +- reg = <0x0 0xe000b000 0x0 0x1000>; +- ranges = <0x2000000 0x0 0xb0000000 0 0xb0000000 0x0 0x100000 +- 0x1000000 0x0 0x00000000 0 0xb0100000 0x0 0x100000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xb0000000 +- 0x2000000 0x0 0xb0000000 +- 0x0 0x100000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/* +- * mpc8544ds.dtsi must be last to ensure board_pci3 overrides pci3 settings +- * for interrupt-map & interrupt-map-mask +- */ +- +-/include/ "mpc8544si-post.dtsi" +-/include/ "mpc8544ds.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8544ds.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8544ds.dtsi +deleted file mode 100644 +index 47d986b041f6..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8544ds.dtsi ++++ /dev/null +@@ -1,207 +0,0 @@ +-/* +- * MPC8544DS Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&board_lbc { +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x800000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- reg = <0x0 0x10000>; +- label = "dtb-nor"; +- }; +- +- partition@20000 { +- reg = <0x20000 0x30000>; +- label = "diagnostic-nor"; +- read-only; +- }; +- +- partition@200000 { +- reg = <0x200000 0x200000>; +- label = "dink-nor"; +- read-only; +- }; +- +- partition@400000 { +- reg = <0x400000 0x380000>; +- label = "kernel-nor"; +- }; +- +- partition@780000 { +- reg = <0x780000 0x80000>; +- label = "u-boot-nor"; +- read-only; +- }; +- }; +-}; +- +-&board_soc { +- enet0: ethernet@24000 { +- phy-handle = <&phy0>; +- tbi-handle = <&tbi0>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@24520 { +- phy0: ethernet-phy@0 { +- interrupts = <10 1 0 0>; +- reg = <0x0>; +- }; +- phy1: ethernet-phy@1 { +- interrupts = <10 1 0 0>; +- reg = <0x1>; +- }; +- +- sgmii_phy0: sgmii-phy@0 { +- interrupts = <6 1 0 0>; +- reg = <0x1c>; +- }; +- sgmii_phy1: sgmii-phy@1 { +- interrupts = <6 1 0 0>; +- reg = <0x1d>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet2: ethernet@26000 { +- phy-handle = <&phy1>; +- tbi-handle = <&tbi1>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@26520 { +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +-}; +- +-&board_pci3 { +- pcie@0 { +- interrupt-map-mask = <0xff00 0x0 0x0 0x7>; +- interrupt-map = < +- // IDSEL 0x1c USB +- 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2 +- 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2 +- 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2 +- 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2 +- +- // IDSEL 0x1d Audio +- 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2 +- +- // IDSEL 0x1e Legacy +- 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2 +- 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2 +- +- // IDSEL 0x1f IDE/SATA +- 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2 +- 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2 +- >; +- +- +- uli1575@0 { +- reg = <0x0 0x0 0x0 0x0 0x0>; +- #size-cells = <2>; +- #address-cells = <3>; +- ranges = <0x2000000 0x0 0xb0000000 +- 0x2000000 0x0 0xb0000000 +- 0x0 0x100000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- isa@1e { +- device_type = "isa"; +- #interrupt-cells = <2>; +- #size-cells = <1>; +- #address-cells = <2>; +- reg = <0xf000 0x0 0x0 0x0 0x0>; +- ranges = <0x1 0x0 0x1000000 0x0 0x0 +- 0x1000>; +- interrupt-parent = <&i8259>; +- +- i8259: interrupt-controller@20 { +- reg = <0x1 0x20 0x2 +- 0x1 0xa0 0x2 +- 0x1 0x4d0 0x2>; +- interrupt-controller; +- device_type = "interrupt-controller"; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- compatible = "chrp,iic"; +- interrupts = <9 2 0 0>; +- interrupt-parent = <&mpic>; +- }; +- +- i8042@60 { +- #size-cells = <0>; +- #address-cells = <1>; +- reg = <0x1 0x60 0x1 0x1 0x64 0x1>; +- interrupts = <1 3 12 3>; +- interrupt-parent = +- <&i8259>; +- +- keyboard@0 { +- reg = <0x0>; +- compatible = "pnpPNP,303"; +- }; +- +- mouse@1 { +- reg = <0x1>; +- compatible = "pnpPNP,f03"; +- }; +- }; +- +- rtc@70 { +- compatible = "pnpPNP,b00"; +- reg = <0x1 0x70 0x2>; +- }; +- +- gpio@400 { +- reg = <0x1 0x400 0x80>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8544si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8544si-post.dtsi +deleted file mode 100644 +index b68eb119faef..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8544si-post.dtsi ++++ /dev/null +@@ -1,191 +0,0 @@ +-/* +- * MPC8544 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&lbc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8544-lbc", "fsl,pq3-localbus", "simple-bus"; +- interrupts = <19 2 0 0>; +-}; +- +-/* controller at 0x8000 */ +-&pci0 { +- compatible = "fsl,mpc8540-pci"; +- device_type = "pci"; +- interrupts = <24 0x2 0 0>; +- bus-range = <0 0xff>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +-}; +- +-/* controller at 0x9000 */ +-&pci1 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <25 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <25 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 +- >; +- }; +-}; +- +-/* controller at 0xa000 */ +-&pci2 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <26 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <26 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 +- >; +- }; +-}; +- +-/* controller at 0xb000 */ +-&pci3 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <27 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <27 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0 +- >; +- }; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,mpc8544-immr", "simple-bus"; +- bus-frequency = <0>; // Filled out by uboot. +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <10>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8544-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2 0 0>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8544-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupts = <18 2 0 0>; +- }; +- +-/include/ "pq3-i2c-0.dtsi" +-/include/ "pq3-i2c-1.dtsi" +-/include/ "pq3-duart-0.dtsi" +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8544-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x40000>; // L2, 256K +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-dma-0.dtsi" +-/include/ "pq3-etsec1-0.dtsi" +-/include/ "pq3-etsec1-2.dtsi" +- +- ethernet@26000 { +- cell-index = <1>; +- }; +- +-/include/ "pq3-sec2.1-0.dtsi" +-/include/ "pq3-mpic.dtsi" +- +- global-utilities@e0000 { +- compatible = "fsl,mpc8544-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8544si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8544si-pre.dtsi +deleted file mode 100644 +index 5a69bafb652a..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8544si-pre.dtsi ++++ /dev/null +@@ -1,66 +0,0 @@ +-/* +- * MPC8544 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e500v2_power_isa.dtsi" +- +-/ { +- compatible = "fsl,MPC8544"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- ethernet0 = &enet0; +- ethernet1 = &enet2; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- pci3 = &pci3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8544@0 { +- device_type = "cpu"; +- reg = <0x0>; +- next-level-cache = <&L2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8548cds.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8548cds.dtsi +deleted file mode 100644 +index 3bc7d4711220..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8548cds.dtsi ++++ /dev/null +@@ -1,302 +0,0 @@ +-/* +- * MPC8548CDS Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&board_lbc { +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x01000000>; +- bank-width = <2>; +- device-width = <2>; +- +- partition@0 { +- reg = <0x0 0x0b00000>; +- label = "ramdisk-nor"; +- }; +- +- partition@300000 { +- reg = <0x0b00000 0x0400000>; +- label = "kernel-nor"; +- }; +- +- partition@700000 { +- reg = <0x0f00000 0x060000>; +- label = "dtb-nor"; +- }; +- +- partition@760000 { +- reg = <0x0f60000 0x020000>; +- label = "env-nor"; +- read-only; +- }; +- +- partition@780000 { +- reg = <0x0f80000 0x080000>; +- label = "u-boot-nor"; +- read-only; +- }; +- }; +- +- board-control@1,0 { +- compatible = "fsl,mpc8548cds-fpga"; +- reg = <0x1 0x0 0x1000>; +- }; +-}; +- +-&board_soc { +- i2c@3000 { +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- +- eeprom@56 { +- compatible = "atmel,24c64"; +- reg = <0x56>; +- }; +- +- eeprom@57 { +- compatible = "atmel,24c64"; +- reg = <0x57>; +- }; +- }; +- +- i2c@3100 { +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- }; +- +- enet0: ethernet@24000 { +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- }; +- +- mdio@24520 { +- phy0: ethernet-phy@0 { +- interrupts = <5 1 0 0>; +- reg = <0x0>; +- }; +- phy1: ethernet-phy@1 { +- interrupts = <5 1 0 0>; +- reg = <0x1>; +- }; +- phy2: ethernet-phy@2 { +- interrupts = <5 1 0 0>; +- reg = <0x2>; +- }; +- phy3: ethernet-phy@3 { +- interrupts = <5 1 0 0>; +- reg = <0x3>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet1: ethernet@25000 { +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- }; +- +- mdio@25520 { +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet2: ethernet@26000 { +- tbi-handle = <&tbi2>; +- phy-handle = <&phy2>; +- }; +- +- mdio@26520 { +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet3: ethernet@27000 { +- tbi-handle = <&tbi3>; +- phy-handle = <&phy3>; +- }; +- +- mdio@27520 { +- tbi3: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +-}; +- +-&board_pci0 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x4 (PCIX Slot 2) */ +- 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 +- 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 +- 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 +- 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 +- +- /* IDSEL 0x5 (PCIX Slot 3) */ +- 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0 +- 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0 +- 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0 +- 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0 +- +- /* IDSEL 0x6 (PCIX Slot 4) */ +- 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 +- 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 +- 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0 +- 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 +- +- /* IDSEL 0x8 (PCIX Slot 5) */ +- 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 +- 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 +- 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 +- 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 +- +- /* IDSEL 0xC (Tsi310 bridge) */ +- 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 +- 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 +- 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 +- 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 +- +- /* IDSEL 0x14 (Slot 2) */ +- 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 +- 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 +- 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 +- 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 +- +- /* IDSEL 0x15 (Slot 3) */ +- 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0 +- 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0 +- 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0 +- 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0 +- +- /* IDSEL 0x16 (Slot 4) */ +- 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 +- 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 +- 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0 +- 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 +- +- /* IDSEL 0x18 (Slot 5) */ +- 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 +- 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 +- 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 +- 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 +- +- /* IDSEL 0x1C (Tsi310 bridge PCI primary) */ +- 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 +- 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 +- 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 +- 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>; +- +- pci_bridge@1c { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x00 (PrPMC Site) */ +- 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 +- 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 +- 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 +- 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 +- +- /* IDSEL 0x04 (VIA chip) */ +- 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 +- 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 +- 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 +- 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 +- +- /* IDSEL 0x05 (8139) */ +- 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0 +- +- /* IDSEL 0x06 (Slot 6) */ +- 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 +- 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 +- 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0 +- 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 +- +- /* IDESL 0x07 (Slot 7) */ +- 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0 +- 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0 +- 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0 +- 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>; +- +- reg = <0xe000 0x0 0x0 0x0 0x0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x20000000 +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x80000>; +- clock-frequency = <33333333>; +- +- isa@4 { +- device_type = "isa"; +- #interrupt-cells = <2>; +- #size-cells = <1>; +- #address-cells = <2>; +- reg = <0x2000 0x0 0x0 0x0 0x0>; +- ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>; +- interrupt-parent = <&i8259>; +- +- i8259: interrupt-controller@20 { +- interrupt-controller; +- device_type = "interrupt-controller"; +- reg = <0x1 0x20 0x2 +- 0x1 0xa0 0x2 +- 0x1 0x4d0 0x2>; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- compatible = "chrp,iic"; +- interrupts = <0 1 0 0>; +- interrupt-parent = <&mpic>; +- }; +- +- rtc@70 { +- compatible = "pnpPNP,b00"; +- reg = <0x1 0x70 0x2>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8548cds_32b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8548cds_32b.dts +deleted file mode 100644 +index f6ba4a982766..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8548cds_32b.dts ++++ /dev/null +@@ -1,82 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8548 CDS Device Tree Source (32-bit address map) +- * +- * Copyright 2006, 2008, 2011-2012 Freescale Semiconductor Inc. +- */ +- +-/include/ "mpc8548si-pre.dtsi" +- +-/ { +- model = "MPC8548CDS"; +- compatible = "MPC8548CDS", "MPC85xxCDS"; +- +- memory { +- device_type = "memory"; +- reg = <0 0 0x0 0x8000000>; // 128M at 0x0 +- }; +- +- board_lbc: lbc: localbus@e0005000 { +- reg = <0 0xe0005000 0 0x1000>; +- +- ranges = <0x0 0x0 0x0 0xff000000 0x01000000 +- 0x1 0x0 0x0 0xf8004000 0x00001000>; +- +- }; +- +- board_soc: soc: soc8548@e0000000 { +- ranges = <0 0x0 0xe0000000 0x100000>; +- }; +- +- board_pci0: pci0: pci@e0008000 { +- reg = <0 0xe0008000 0 0x1000>; +- ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000 +- 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>; +- clock-frequency = <66666666>; +- }; +- +- pci1: pci@e0009000 { +- reg = <0 0xe0009000 0 0x1000>; +- ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000 +- 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>; +- clock-frequency = <66666666>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x15 */ +- 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0 +- 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 +- 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 +- 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>; +- }; +- +- pci2: pcie@e000a000 { +- reg = <0 0xe000a000 0 0x1000>; +- ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- rio: rapidio@e00c0000 { +- reg = <0x0 0xe00c0000 0x0 0x20000>; +- port1 { +- ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>; +- }; +- }; +-}; +- +-/* +- * mpc8548cds.dtsi must be last to ensure board_pci0 overrides pci0 settings +- * for interrupt-map & interrupt-map-mask. +- */ +- +-/include/ "mpc8548si-post.dtsi" +-/include/ "mpc8548cds.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8548cds_36b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8548cds_36b.dts +deleted file mode 100644 +index 32e9076375ae..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8548cds_36b.dts ++++ /dev/null +@@ -1,82 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8548 CDS Device Tree Source (36-bit address map) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- */ +- +-/include/ "mpc8548si-pre.dtsi" +- +-/ { +- model = "MPC8548CDS"; +- compatible = "MPC8548CDS", "MPC85xxCDS"; +- +- memory { +- device_type = "memory"; +- reg = <0 0 0x0 0x8000000>; // 128M at 0x0 +- }; +- +- board_lbc: lbc: localbus@fe0005000 { +- reg = <0xf 0xe0005000 0 0x1000>; +- +- ranges = <0x0 0x0 0xf 0xff000000 0x01000000 +- 0x1 0x0 0xf 0xf8004000 0x00001000>; +- +- }; +- +- board_soc: soc: soc8548@fe0000000 { +- ranges = <0 0xf 0xe0000000 0x100000>; +- }; +- +- board_pci0: pci0: pci@fe0008000 { +- reg = <0xf 0xe0008000 0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000 +- 0x1000000 0x0 0x00000000 0xf 0xe2000000 0x0 0x800000>; +- clock-frequency = <66666666>; +- }; +- +- pci1: pci@fe0009000 { +- reg = <0xf 0xe0009000 0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000 +- 0x1000000 0x0 0x00000000 0xf 0xe2800000 0x0 0x800000>; +- clock-frequency = <66666666>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x15 */ +- 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0 +- 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 +- 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 +- 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>; +- }; +- +- pci2: pcie@fe000a000 { +- reg = <0xf 0xe000a000 0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x100000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- rio: rapidio@fe00c0000 { +- reg = <0xf 0xe00c0000 0x0 0x20000>; +- port1 { +- ranges = <0x0 0x0 0xc 0x40000000 0x0 0x20000000>; +- }; +- }; +-}; +- +-/* +- * mpc8548cds.dtsi must be last to ensure board_pci0 overrides pci0 settings +- * for interrupt-map & interrupt-map-mask. +- */ +- +-/include/ "mpc8548si-post.dtsi" +-/include/ "mpc8548cds.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8548si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8548si-post.dtsi +deleted file mode 100644 +index 579d76cb8e32..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8548si-post.dtsi ++++ /dev/null +@@ -1,159 +0,0 @@ +-/* +- * MPC8548 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&lbc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8548-lbc", "fsl,pq3-localbus", "simple-bus"; +- interrupts = <19 2 0 0>; +-}; +- +-/* controller at 0x8000 */ +-&pci0 { +- compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; +- device_type = "pci"; +- interrupts = <24 0x2 0 0>; +- bus-range = <0 0xff>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +-}; +- +-/* controller at 0x9000 */ +-&pci1 { +- compatible = "fsl,mpc8540-pci"; +- device_type = "pci"; +- interrupts = <25 0x2 0 0>; +- bus-range = <0 0xff>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +-}; +- +-/* controller at 0xa000 */ +-&pci2 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <26 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <26 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 +- >; +- }; +-}; +- +-&rio { +- compatible = "fsl,srio"; +- interrupts = <48 2 0 0>; +- #address-cells = <2>; +- #size-cells = <2>; +- fsl,srio-rmu-handle = <&rmu>; +- ranges; +- +- port1 { +- #address-cells = <2>; +- #size-cells = <2>; +- cell-index = <1>; +- }; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,mpc8548-immr", "simple-bus"; +- bus-frequency = <0>; // Filled out by uboot. +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <10>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8548-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2 0 0>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8548-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupts = <18 2 0 0>; +- }; +- +-/include/ "pq3-i2c-0.dtsi" +-/include/ "pq3-i2c-1.dtsi" +-/include/ "pq3-duart-0.dtsi" +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8548-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x80000>; // L2, 512K +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-dma-0.dtsi" +-/include/ "pq3-etsec1-0.dtsi" +-/include/ "pq3-etsec1-1.dtsi" +-/include/ "pq3-etsec1-2.dtsi" +-/include/ "pq3-etsec1-3.dtsi" +- +-/include/ "pq3-sec2.1-0.dtsi" +-/include/ "pq3-mpic.dtsi" +-/include/ "pq3-rmu-0.dtsi" +- +- global-utilities@e0000 { +- compatible = "fsl,mpc8548-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8548si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8548si-pre.dtsi +deleted file mode 100644 +index fc1ce977422b..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8548si-pre.dtsi ++++ /dev/null +@@ -1,67 +0,0 @@ +-/* +- * MPC8548 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e500v2_power_isa.dtsi" +- +-/ { +- compatible = "fsl,MPC8548"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8548@0 { +- device_type = "cpu"; +- reg = <0x0>; +- next-level-cache = <&L2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8555cds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8555cds.dts +deleted file mode 100644 +index 9f58db2a7e66..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8555cds.dts ++++ /dev/null +@@ -1,375 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8555 CDS Device Tree Source +- * +- * Copyright 2006, 2008 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/include/ "e500v2_power_isa.dtsi" +- +-/ { +- model = "MPC8555CDS"; +- compatible = "MPC8555CDS", "MPC85xxCDS"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- pci1 = &pci1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8555@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <0x8000>; // L1, 32K +- i-cache-size = <0x8000>; // L1, 32K +- timebase-frequency = <0>; // 33 MHz, from uboot +- bus-frequency = <0>; // 166 MHz +- clock-frequency = <0>; // 825 MHz, from uboot +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x8000000>; // 128M at 0x0 +- }; +- +- soc8555@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- ranges = <0x0 0xe0000000 0x100000>; +- bus-frequency = <0>; +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <8>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8555-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8555-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8555-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x40000>; // L2, 256K +- interrupt-parent = <&mpic>; +- interrupts = <16 2>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8555-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8555-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8555-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8555-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 30 2 34 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy0: ethernet-phy@0 { +- interrupt-parent = <&mpic>; +- interrupts = <5 1>; +- reg = <0x0>; +- }; +- phy1: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <5 1>; +- reg = <0x1>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 2 36 2 40 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; // reg base, size +- clock-frequency = <0>; // should we fill in in uboot? +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; // reg base, size +- clock-frequency = <0>; // should we fill in in uboot? +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <45 2>; +- interrupt-parent = <&mpic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x7e>; +- fsl,descriptor-types-mask = <0x01010ebf>; +- }; +- +- mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- compatible = "chrp,open-pic"; +- device_type = "open-pic"; +- }; +- +- cpm@919c0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8555-cpm", "fsl,cpm2"; +- reg = <0x919c0 0x30>; +- ranges; +- +- muram@80000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x80000 0x10000>; +- +- data@0 { +- compatible = "fsl,cpm-muram-data"; +- reg = <0x0 0x2000 0x9000 0x1000>; +- }; +- }; +- +- brg@919f0 { +- compatible = "fsl,mpc8555-brg", +- "fsl,cpm2-brg", +- "fsl,cpm-brg"; +- reg = <0x919f0 0x10 0x915f0 0x10>; +- }; +- +- cpmpic: pic@90c00 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <46 2>; +- interrupt-parent = <&mpic>; +- reg = <0x90c00 0x80>; +- compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic"; +- }; +- }; +- }; +- +- pci0: pci@e0008000 { +- interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x10 */ +- 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1 +- 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1 +- +- /* IDSEL 0x11 */ +- 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1 +- 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1 +- +- /* IDSEL 0x12 (Slot 1) */ +- 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1 +- 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1 +- +- /* IDSEL 0x13 (Slot 2) */ +- 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1 +- 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1 +- 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1 +- 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1 +- +- /* IDSEL 0x14 (Slot 3) */ +- 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1 +- 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1 +- 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1 +- 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1 +- +- /* IDSEL 0x15 (Slot 4) */ +- 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1 +- 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1 +- 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1 +- 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1 +- +- /* Bus 1 (Tundra Bridge) */ +- /* IDSEL 0x12 (ISA bridge) */ +- 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1 +- 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>; +- interrupt-parent = <&mpic>; +- interrupts = <24 2>; +- bus-range = <0 0>; +- ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008000 0x1000>; +- compatible = "fsl,mpc8540-pci"; +- device_type = "pci"; +- +- i8259@19000 { +- interrupt-controller; +- device_type = "interrupt-controller"; +- reg = <0x19000 0x0 0x0 0x0 0x1>; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- compatible = "chrp,iic"; +- interrupts = <1>; +- interrupt-parent = <&pci0>; +- }; +- }; +- +- pci1: pci@e0009000 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x15 */ +- 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 +- 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1 +- 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1 +- 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>; +- interrupt-parent = <&mpic>; +- interrupts = <25 2>; +- bus-range = <0 0>; +- ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0009000 0x1000>; +- compatible = "fsl,mpc8540-pci"; +- device_type = "pci"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8560ads.dts b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8560ads.dts +deleted file mode 100644 +index a24722ccaebf..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8560ads.dts ++++ /dev/null +@@ -1,388 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8560 ADS Device Tree Source +- * +- * Copyright 2006, 2008 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/include/ "e500v2_power_isa.dtsi" +- +-/ { +- model = "MPC8560ADS"; +- compatible = "MPC8560ADS", "MPC85xxADS"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8560@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <0x8000>; // L1, 32K +- i-cache-size = <0x8000>; // L1, 32K +- timebase-frequency = <82500000>; +- bus-frequency = <330000000>; +- clock-frequency = <825000000>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x10000000>; +- }; +- +- soc8560@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- ranges = <0x0 0xe0000000 0x100000>; +- bus-frequency = <330000000>; +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <8>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8560-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8540-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8540-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x40000>; // L2, 256K +- interrupt-parent = <&mpic>; +- interrupts = <16 2>; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8560-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8560-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8560-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8560-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 30 2 34 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy0: ethernet-phy@0 { +- interrupt-parent = <&mpic>; +- interrupts = <5 1>; +- reg = <0x0>; +- }; +- phy1: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <5 1>; +- reg = <0x1>; +- }; +- phy2: ethernet-phy@2 { +- interrupt-parent = <&mpic>; +- interrupts = <7 1>; +- reg = <0x2>; +- }; +- phy3: ethernet-phy@3 { +- interrupt-parent = <&mpic>; +- interrupts = <7 1>; +- reg = <0x3>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 2 36 2 40 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- compatible = "chrp,open-pic"; +- device_type = "open-pic"; +- }; +- +- cpm@919c0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8560-cpm", "fsl,cpm2"; +- reg = <0x919c0 0x30>; +- ranges; +- +- muram@80000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x80000 0x10000>; +- +- data@0 { +- compatible = "fsl,cpm-muram-data"; +- reg = <0x0 0x4000 0x9000 0x2000>; +- }; +- }; +- +- brg@919f0 { +- compatible = "fsl,mpc8560-brg", +- "fsl,cpm2-brg", +- "fsl,cpm-brg"; +- reg = <0x919f0 0x10 0x915f0 0x10>; +- clock-frequency = <165000000>; +- }; +- +- cpmpic: pic@90c00 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <46 2>; +- interrupt-parent = <&mpic>; +- reg = <0x90c00 0x80>; +- compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic"; +- }; +- +- serial0: serial@91a00 { +- device_type = "serial"; +- compatible = "fsl,mpc8560-scc-uart", +- "fsl,cpm2-scc-uart"; +- reg = <0x91a00 0x20 0x88000 0x100>; +- fsl,cpm-brg = <1>; +- fsl,cpm-command = <0x800000>; +- current-speed = <115200>; +- interrupts = <40 8>; +- interrupt-parent = <&cpmpic>; +- }; +- +- serial1: serial@91a20 { +- device_type = "serial"; +- compatible = "fsl,mpc8560-scc-uart", +- "fsl,cpm2-scc-uart"; +- reg = <0x91a20 0x20 0x88100 0x100>; +- fsl,cpm-brg = <2>; +- fsl,cpm-command = <0x4a00000>; +- current-speed = <115200>; +- interrupts = <41 8>; +- interrupt-parent = <&cpmpic>; +- }; +- +- enet2: ethernet@91320 { +- device_type = "network"; +- compatible = "fsl,mpc8560-fcc-enet", +- "fsl,cpm2-fcc-enet"; +- reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- fsl,cpm-command = <0x16200300>; +- interrupts = <33 8>; +- interrupt-parent = <&cpmpic>; +- phy-handle = <&phy2>; +- }; +- +- enet3: ethernet@91340 { +- device_type = "network"; +- compatible = "fsl,mpc8560-fcc-enet", +- "fsl,cpm2-fcc-enet"; +- reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- fsl,cpm-command = <0x1a400300>; +- interrupts = <34 8>; +- interrupt-parent = <&cpmpic>; +- phy-handle = <&phy3>; +- }; +- }; +- }; +- +- pci0: pci@e0008000 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; +- device_type = "pci"; +- reg = <0xe0008000 0x1000>; +- clock-frequency = <66666666>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x2 */ +- 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1 +- 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1 +- 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1 +- 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1 +- +- /* IDSEL 0x3 */ +- 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1 +- 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1 +- +- /* IDSEL 0x4 */ +- 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1 +- 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1 +- 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1 +- 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1 +- +- /* IDSEL 0x5 */ +- 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1 +- 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1 +- 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1 +- 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1 +- +- /* IDSEL 12 */ +- 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1 +- 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1 +- 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1 +- 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1 +- +- /* IDSEL 13 */ +- 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1 +- 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1 +- +- /* IDSEL 14*/ +- 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1 +- 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1 +- 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1 +- 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1 +- +- /* IDSEL 15 */ +- 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1 +- 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1 +- 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1 +- 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1 +- +- /* IDSEL 18 */ +- 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1 +- 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1 +- 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1 +- 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 +- +- /* IDSEL 19 */ +- 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1 +- 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1 +- +- /* IDSEL 20 */ +- 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1 +- 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1 +- 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1 +- 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1 +- +- /* IDSEL 21 */ +- 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1 +- 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1 +- 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1 +- 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>; +- +- interrupt-parent = <&mpic>; +- interrupts = <24 2>; +- bus-range = <0 0>; +- ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x0 0xe2000000 0x0 0x1000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8568mds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8568mds.dts +deleted file mode 100644 +index 3603b5ae1230..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8568mds.dts ++++ /dev/null +@@ -1,310 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8568E MDS Device Tree Source +- * +- * Copyright 2007, 2008 Freescale Semiconductor Inc. +- */ +- +-/include/ "mpc8568si-pre.dtsi" +- +-/ { +- model = "MPC8568EMDS"; +- compatible = "MPC8568EMDS", "MPC85xxMDS"; +- +- aliases { +- pci0 = &pci0; +- pci1 = &pci1; +- rapidio0 = &rio; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x0>; +- }; +- +- lbc: localbus@e0005000 { +- reg = <0x0 0xe0005000 0x0 0x1000>; +- ranges = <0x0 0x0 0xfe000000 0x02000000 +- 0x1 0x0 0xf8000000 0x00008000 +- 0x2 0x0 0xf0000000 0x04000000 +- 0x4 0x0 0xf8008000 0x00008000 +- 0x5 0x0 0xf8010000 0x00008000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x02000000>; +- bank-width = <2>; +- device-width = <2>; +- }; +- +- bcsr@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8568mds-bcsr"; +- reg = <1 0 0x8000>; +- ranges = <0 1 0 0x8000>; +- +- bcsr5: gpio-controller@11 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8568mds-bcsr-gpio"; +- reg = <0x5 0x1>; +- gpio-controller; +- }; +- }; +- +- pib@4,0 { +- compatible = "fsl,mpc8568mds-pib"; +- reg = <4 0 0x8000>; +- }; +- +- pib@5,0 { +- compatible = "fsl,mpc8568mds-pib"; +- reg = <5 0 0x8000>; +- }; +- }; +- +- soc: soc8568@e0000000 { +- ranges = <0x0 0x0 0xe0000000 0x100000>; +- +- i2c-sleep-nexus { +- i2c@3000 { +- rtc@68 { +- compatible = "dallas,ds1374"; +- reg = <0x68>; +- interrupts = <3 1 0 0>; +- }; +- }; +- }; +- +- enet0: ethernet@24000 { +- tbi-handle = <&tbi0>; +- phy-handle = <&phy2>; +- }; +- +- mdio@24520 { +- phy0: ethernet-phy@7 { +- interrupts = <1 1 0 0>; +- reg = <0x7>; +- }; +- phy1: ethernet-phy@1 { +- interrupts = <2 1 0 0>; +- reg = <0x1>; +- }; +- phy2: ethernet-phy@2 { +- interrupts = <1 1 0 0>; +- reg = <0x2>; +- }; +- phy3: ethernet-phy@3 { +- interrupts = <2 1 0 0>; +- reg = <0x3>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet1: ethernet@25000 { +- tbi-handle = <&tbi1>; +- phy-handle = <&phy3>; +- sleep = <&pmc 0x00000040>; +- }; +- +- mdio@25520 { +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- par_io@e0100 { +- num-ports = <7>; +- +- pio1: ucc_pin@1 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */ +- 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */ +- 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */ +- 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */ +- 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */ +- 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */ +- 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */ +- 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */ +- 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */ +- 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */ +- 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */ +- 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */ +- 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */ +- 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */ +- 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */ +- 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */ +- 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */ +- 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */ +- 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */ +- 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */ +- 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */ +- 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */ +- 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */ +- }; +- +- pio2: ucc_pin@2 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */ +- 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */ +- 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */ +- 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */ +- 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */ +- 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */ +- 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */ +- 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */ +- 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */ +- 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */ +- 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */ +- 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */ +- 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */ +- 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */ +- 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */ +- 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */ +- 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */ +- 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */ +- 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */ +- 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */ +- 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */ +- 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */ +- 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */ +- 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */ +- 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */ +- }; +- }; +- }; +- +- qe: qe@e0080000 { +- ranges = <0x0 0x0 0xe0080000 0x40000>; +- reg = <0x0 0xe0080000 0x0 0x480>; +- +- spi@4c0 { +- mode = "cpu"; +- }; +- +- spi@500 { +- mode = "cpu"; +- }; +- +- enet2: ucc@2000 { +- device_type = "network"; +- compatible = "ucc_geth"; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "none"; +- tx-clock-name = "clk16"; +- pio-handle = <&pio1>; +- phy-handle = <&phy0>; +- phy-connection-type = "rgmii-id"; +- }; +- +- enet3: ucc@3000 { +- device_type = "network"; +- compatible = "ucc_geth"; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "none"; +- tx-clock-name = "clk16"; +- pio-handle = <&pio2>; +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@2120 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2120 0x18>; +- compatible = "fsl,ucc-mdio"; +- +- /* These are the same PHYs as on +- * gianfar's MDIO bus */ +- qe_phy0: ethernet-phy@7 { +- interrupt-parent = <&mpic>; +- interrupts = <1 1 0 0>; +- reg = <0x7>; +- }; +- qe_phy1: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <2 1 0 0>; +- reg = <0x1>; +- }; +- qe_phy2: ethernet-phy@2 { +- interrupt-parent = <&mpic>; +- interrupts = <1 1 0 0>; +- reg = <0x2>; +- }; +- qe_phy3: ethernet-phy@3 { +- interrupt-parent = <&mpic>; +- interrupts = <2 1 0 0>; +- reg = <0x3>; +- }; +- }; +- }; +- +- pci0: pci@e0008000 { +- reg = <0x0 0xe0008000 0x0 0x1000>; +- ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0x0 0xe2000000 0x0 0x800000>; +- clock-frequency = <66666666>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x12 AD18 */ +- 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1 0 0 +- 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1 0 0 +- 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1 0 0 +- 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 0 0 +- +- /* IDSEL 0x13 AD19 */ +- 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1 0 0 +- 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1 0 0 +- 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0 +- 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1 0 0>; +- }; +- +- /* PCI Express */ +- pci1: pcie@e000a000 { +- ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000 +- 0x1000000 0x0 0x00000000 0x0 0xe2800000 0x0 0x800000>; +- reg = <0x0 0xe000a000 0x0 0x1000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x10000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x800000>; +- }; +- }; +- +- rio: rapidio@e00c00000 { +- reg = <0x0 0xe00c0000 0x0 0x20000>; +- port1 { +- ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- green { +- gpios = <&bcsr5 1 0>; +- }; +- +- amber { +- gpios = <&bcsr5 2 0>; +- }; +- +- red { +- gpios = <&bcsr5 3 0>; +- }; +- }; +-}; +- +-/include/ "mpc8568si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8568si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8568si-post.dtsi +deleted file mode 100644 +index 64e7075a9cd4..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8568si-post.dtsi ++++ /dev/null +@@ -1,270 +0,0 @@ +-/* +- * MPC8568 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&lbc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus", "simple-bus"; +- interrupts = <19 2 0 0>; +- sleep = <&pmc 0x08000000>; +-}; +- +-/* controller at 0x8000 */ +-&pci0 { +- compatible = "fsl,mpc8540-pci"; +- device_type = "pci"; +- interrupts = <24 0x2 0 0>; +- bus-range = <0 0xff>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- sleep = <&pmc 0x80000000>; +-}; +- +-/* controller at 0xa000 */ +-&pci1 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <26 2 0 0>; +- sleep = <&pmc 0x20000000>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <26 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 +- >; +- }; +-}; +- +-&rio { +- compatible = "fsl,srio"; +- interrupts = <48 2 0 0>; +- #address-cells = <2>; +- #size-cells = <2>; +- fsl,srio-rmu-handle = <&rmu>; +- sleep = <&pmc 0x00080000>; +- ranges; +- +- port1 { +- #address-cells = <2>; +- #size-cells = <2>; +- cell-index = <1>; +- }; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,mpc8568-immr", "simple-bus"; +- bus-frequency = <0>; // Filled out by uboot. +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <10>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8568-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2 0 0>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8568-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupts = <18 2 0 0>; +- }; +- +- i2c-sleep-nexus { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- sleep = <&pmc 0x00000004>; +- ranges; +- +-/include/ "pq3-i2c-0.dtsi" +-/include/ "pq3-i2c-1.dtsi" +- +- }; +- +- duart-sleep-nexus { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- sleep = <&pmc 0x00000002>; +- ranges; +- +-/include/ "pq3-duart-0.dtsi" +- +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8568-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x80000>; // L2, 512K +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-dma-0.dtsi" +- dma@21300 { +- sleep = <&pmc 0x00000400>; +- }; +- +-/include/ "pq3-etsec1-0.dtsi" +- ethernet@24000 { +- sleep = <&pmc 0x00000080>; +- }; +- +-/include/ "pq3-etsec1-1.dtsi" +- ethernet@25000 { +- sleep = <&pmc 0x00000040>; +- }; +- +- par_io@e0100 { +- reg = <0xe0100 0x100>; +- device_type = "par_io"; +- }; +- +-/include/ "pq3-sec2.1-0.dtsi" +- crypto@30000 { +- sleep = <&pmc 0x01000000>; +- }; +- +-/include/ "pq3-mpic.dtsi" +-/include/ "pq3-rmu-0.dtsi" +- rmu@d3000 { +- sleep = <&pmc 0x00040000>; +- }; +- +- global-utilities@e0000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8568-guts", "fsl,mpc8548-guts"; +- reg = <0xe0000 0x1000>; +- ranges = <0 0xe0000 0x1000>; +- fsl,has-rstcr; +- +- pmc: power@70 { +- compatible = "fsl,mpc8568-pmc", +- "fsl,mpc8548-pmc"; +- reg = <0x70 0x20>; +- }; +- }; +-}; +- +-&qe { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "qe"; +- compatible = "fsl,qe"; +- sleep = <&pmc 0x00000800>; +- brg-frequency = <0>; +- bus-frequency = <396000000>; +- fsl,qe-num-riscs = <2>; +- fsl,qe-num-snums = <28>; +- +- qeic: interrupt-controller@80 { +- interrupt-controller; +- compatible = "fsl,qe-ic"; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x80 0x80>; +- interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30 +- interrupt-parent = <&mpic>; +- }; +- +- spi@4c0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,spi"; +- reg = <0x4c0 0x40>; +- cell-index = <0>; +- interrupts = <2>; +- interrupt-parent = <&qeic>; +- }; +- +- spi@500 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl,spi"; +- reg = <0x500 0x40>; +- interrupts = <1>; +- interrupt-parent = <&qeic>; +- }; +- +- ucc@2000 { +- cell-index = <1>; +- reg = <0x2000 0x200>; +- interrupts = <32>; +- interrupt-parent = <&qeic>; +- }; +- +- ucc@3000 { +- cell-index = <2>; +- reg = <0x3000 0x200>; +- interrupts = <33>; +- interrupt-parent = <&qeic>; +- }; +- +- muram@10000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,qe-muram", "fsl,cpm-muram"; +- ranges = <0x0 0x10000 0x10000>; +- +- data-only@0 { +- compatible = "fsl,qe-muram-data", +- "fsl,cpm-muram-data"; +- reg = <0x0 0x10000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8568si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8568si-pre.dtsi +deleted file mode 100644 +index 122ca3bd0b03..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8568si-pre.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * MPC8568 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e500v2_power_isa.dtsi" +- +-/ { +- compatible = "fsl,MPC8568"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- pci0 = &pci0; +- pci1 = &pci1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8568@0 { +- device_type = "cpu"; +- reg = <0x0>; +- next-level-cache = <&L2>; +- sleep = <&pmc 0x00008000 // core +- &pmc 0x00004000>; // timebase +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8569mds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8569mds.dts +deleted file mode 100644 +index 206614ea2269..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8569mds.dts ++++ /dev/null +@@ -1,443 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8569E MDS Device Tree Source +- * +- * Copyright (C) 2009 Freescale Semiconductor Inc. +- */ +- +-/include/ "mpc8569si-pre.dtsi" +- +-/ { +- model = "MPC8569EMDS"; +- compatible = "fsl,MPC8569EMDS"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- ethernet5 = &enet5; +- ethernet7 = &enet7; +- rapidio0 = &rio; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@e0005000 { +- reg = <0x0 0xe0005000 0x0 0x1000>; +- +- ranges = <0x0 0x0 0x0 0xfe000000 0x02000000 +- 0x1 0x0 0x0 0xf8000000 0x00008000 +- 0x2 0x0 0x0 0xf0000000 0x04000000 +- 0x3 0x0 0x0 0xfc000000 0x00008000 +- 0x4 0x0 0x0 0xf8008000 0x00008000 +- 0x5 0x0 0x0 0xf8010000 0x00008000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x02000000>; +- bank-width = <1>; +- device-width = <1>; +- partition@0 { +- label = "ramdisk"; +- reg = <0x00000000 0x01c00000>; +- }; +- partition@1c00000 { +- label = "kernel"; +- reg = <0x01c00000 0x002e0000>; +- }; +- partition@1ee0000 { +- label = "dtb"; +- reg = <0x01ee0000 0x00020000>; +- }; +- partition@1f00000 { +- label = "firmware"; +- reg = <0x01f00000 0x00080000>; +- read-only; +- }; +- partition@1f80000 { +- label = "u-boot"; +- reg = <0x01f80000 0x00080000>; +- read-only; +- }; +- }; +- +- bcsr@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8569mds-bcsr"; +- reg = <1 0 0x8000>; +- ranges = <0 1 0 0x8000>; +- +- bcsr17: gpio-controller@11 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8569mds-bcsr-gpio"; +- reg = <0x11 0x1>; +- gpio-controller; +- }; +- }; +- +- nand@3,0 { +- compatible = "fsl,mpc8569-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <3 0 0x8000>; +- }; +- +- pib@4,0 { +- compatible = "fsl,mpc8569mds-pib"; +- reg = <4 0 0x8000>; +- }; +- +- pib@5,0 { +- compatible = "fsl,mpc8569mds-pib"; +- reg = <5 0 0x8000>; +- }; +- }; +- +- soc: soc@e0000000 { +- ranges = <0x0 0x0 0xe0000000 0x100000>; +- +- i2c-sleep-nexus { +- i2c@3000 { +- rtc@68 { +- compatible = "dallas,ds1374"; +- reg = <0x68>; +- interrupts = <3 1 0 0>; +- }; +- }; +- }; +- +- sdhc@2e000 { +- status = "disabled"; +- sdhci,1-bit-only; +- bus-width = <1>; +- }; +- +- par_io@e0100 { +- num-ports = <7>; +- +- qe_pio_e: gpio-controller@80 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8569-qe-pario-bank", +- "fsl,mpc8323-qe-pario-bank"; +- reg = <0x80 0x18>; +- gpio-controller; +- }; +- +- qe_pio_f: gpio-controller@a0 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8569-qe-pario-bank", +- "fsl,mpc8323-qe-pario-bank"; +- reg = <0xa0 0x18>; +- gpio-controller; +- }; +- +- pio1: ucc_pin@1 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ +- 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ +- 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/ +- 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */ +- 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */ +- 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */ +- 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */ +- 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */ +- 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */ +- 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */ +- 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */ +- 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */ +- 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */ +- 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */ +- 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */ +- }; +- +- pio2: ucc_pin@2 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ +- 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ +- 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */ +- 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */ +- 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */ +- 0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */ +- 0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */ +- 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */ +- 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */ +- 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */ +- 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */ +- 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */ +- 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */ +- 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */ +- 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */ +- }; +- +- pio3: ucc_pin@3 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ +- 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ +- 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/ +- 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */ +- 0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */ +- 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */ +- 0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */ +- 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */ +- 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */ +- 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */ +- 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */ +- 0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */ +- 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */ +- 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */ +- 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */ +- }; +- +- pio4: ucc_pin@4 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ +- 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ +- 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */ +- 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */ +- 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */ +- 0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */ +- 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */ +- 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */ +- 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */ +- 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */ +- 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */ +- 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */ +- 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */ +- 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */ +- 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */ +- }; +- }; +- }; +- +- qe: qe@e0080000 { +- ranges = <0x0 0x0 0xe0080000 0x40000>; +- reg = <0x0 0xe0080000 0x0 0x480>; +- +- spi@4c0 { +- gpios = <&qe_pio_e 30 0>; +- mode = "cpu-qe"; +- +- serial-flash@0 { +- compatible = "st,m25p40"; +- reg = <0>; +- spi-max-frequency = <25000000>; +- }; +- }; +- +- spi@500 { +- mode = "cpu"; +- }; +- +- usb@6c0 { +- fsl,fullspeed-clock = "clk5"; +- fsl,lowspeed-clock = "brg10"; +- gpios = <&qe_pio_f 3 0 /* USBOE */ +- &qe_pio_f 4 0 /* USBTP */ +- &qe_pio_f 5 0 /* USBTN */ +- &qe_pio_f 6 0 /* USBRP */ +- &qe_pio_f 8 0 /* USBRN */ +- &bcsr17 1 0 /* SPEED */ +- &bcsr17 2 0>; /* POWER */ +- }; +- +- enet0: ucc@2000 { +- device_type = "network"; +- compatible = "ucc_geth"; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "none"; +- tx-clock-name = "clk12"; +- pio-handle = <&pio1>; +- tbi-handle = <&tbi1>; +- phy-handle = <&qe_phy0>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@2120 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2120 0x18>; +- compatible = "fsl,ucc-mdio"; +- +- qe_phy0: ethernet-phy@7 { +- interrupt-parent = <&mpic>; +- interrupts = <1 1 0 0>; +- reg = <0x7>; +- }; +- qe_phy1: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <2 1 0 0>; +- reg = <0x1>; +- }; +- qe_phy2: ethernet-phy@2 { +- interrupt-parent = <&mpic>; +- interrupts = <3 1 0 0>; +- reg = <0x2>; +- }; +- qe_phy3: ethernet-phy@3 { +- interrupt-parent = <&mpic>; +- interrupts = <4 1 0 0>; +- reg = <0x3>; +- }; +- qe_phy5: ethernet-phy@4 { +- reg = <0x04>; +- }; +- qe_phy7: ethernet-phy@6 { +- reg = <0x6>; +- }; +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- mdio@3520 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3520 0x18>; +- compatible = "fsl,ucc-mdio"; +- +- tbi6: tbi-phy@15 { +- reg = <0x15>; +- device_type = "tbi-phy"; +- }; +- }; +- mdio@3720 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3720 0x38>; +- compatible = "fsl,ucc-mdio"; +- tbi8: tbi-phy@17 { +- reg = <0x17>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet2: ucc@2200 { +- device_type = "network"; +- compatible = "ucc_geth"; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "none"; +- tx-clock-name = "clk12"; +- pio-handle = <&pio3>; +- tbi-handle = <&tbi3>; +- phy-handle = <&qe_phy2>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@2320 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2320 0x18>; +- compatible = "fsl,ucc-mdio"; +- tbi3: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet1: ucc@3000 { +- device_type = "network"; +- compatible = "ucc_geth"; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "none"; +- tx-clock-name = "clk17"; +- pio-handle = <&pio2>; +- tbi-handle = <&tbi2>; +- phy-handle = <&qe_phy1>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@3120 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3120 0x18>; +- compatible = "fsl,ucc-mdio"; +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet3: ucc@3200 { +- device_type = "network"; +- compatible = "ucc_geth"; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "none"; +- tx-clock-name = "clk17"; +- pio-handle = <&pio4>; +- tbi-handle = <&tbi4>; +- phy-handle = <&qe_phy3>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@3320 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3320 0x18>; +- compatible = "fsl,ucc-mdio"; +- tbi4: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet5: ucc@3400 { +- device_type = "network"; +- compatible = "ucc_geth"; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "none"; +- tx-clock-name = "none"; +- tbi-handle = <&tbi6>; +- phy-handle = <&qe_phy5>; +- phy-connection-type = "sgmii"; +- }; +- +- enet7: ucc@3600 { +- device_type = "network"; +- compatible = "ucc_geth"; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "none"; +- tx-clock-name = "none"; +- tbi-handle = <&tbi8>; +- phy-handle = <&qe_phy7>; +- phy-connection-type = "sgmii"; +- }; +- }; +- +- /* PCI Express */ +- pci1: pcie@e000a000 { +- reg = <0x0 0xe000a000 0x0 0x1000>; +- ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000 +- 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x00800000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x10000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x800000>; +- }; +- }; +- +- rio: rapidio@e00c00000 { +- reg = <0x0 0xe00c0000 0x0 0x20000>; +- port1 { +- ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>; +- }; +- port2 { +- status = "disabled"; +- }; +- }; +-}; +- +-/include/ "mpc8569si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8569si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8569si-post.dtsi +deleted file mode 100644 +index 3e6346a4a183..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8569si-post.dtsi ++++ /dev/null +@@ -1,304 +0,0 @@ +-/* +- * MPC8569 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&lbc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus"; +- interrupts = <19 2 0 0>; +- sleep = <&pmc 0x08000000>; +-}; +- +-/* controller at 0xa000 */ +-&pci1 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <26 2 0 0>; +- sleep = <&pmc 0x20000000>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <26 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 +- >; +- }; +-}; +- +-&rio { +- compatible = "fsl,srio"; +- interrupts = <48 2 0 0>; +- #address-cells = <2>; +- #size-cells = <2>; +- fsl,srio-rmu-handle = <&rmu>; +- sleep = <&pmc 0x00080000>; +- ranges; +- +- port1 { +- #address-cells = <2>; +- #size-cells = <2>; +- cell-index = <1>; +- }; +- +- port2 { +- #address-cells = <2>; +- #size-cells = <2>; +- cell-index = <2>; +- }; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,mpc8569-immr", "simple-bus"; +- bus-frequency = <0>; // Filled out by uboot. +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <10>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8569-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2 0 0>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8569-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupts = <18 2 0 0>; +- }; +- +- i2c-sleep-nexus { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- sleep = <&pmc 0x00000004>; +- ranges; +- +-/include/ "pq3-i2c-0.dtsi" +-/include/ "pq3-i2c-1.dtsi" +- +- }; +- +- duart-sleep-nexus { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- sleep = <&pmc 0x00000002>; +- ranges; +- +-/include/ "pq3-duart-0.dtsi" +- +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8569-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x80000>; // L2, 512K +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-dma-0.dtsi" +-/include/ "pq3-esdhc-0.dtsi" +- sdhc@2e000 { +- sleep = <&pmc 0x00200000>; +- }; +- +- par_io@e0100 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xe0100 0x100>; +- ranges = <0x0 0xe0100 0x100>; +- device_type = "par_io"; +- }; +- +-/include/ "pq3-sec3.1-0.dtsi" +- crypto@30000 { +- sleep = <&pmc 0x01000000>; +- }; +- +-/include/ "pq3-mpic.dtsi" +-/include/ "pq3-rmu-0.dtsi" +- rmu@d3000 { +- sleep = <&pmc 0x00040000>; +- }; +- +- global-utilities@e0000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts"; +- reg = <0xe0000 0x1000>; +- ranges = <0 0xe0000 0x1000>; +- fsl,has-rstcr; +- +- pmc: power@70 { +- compatible = "fsl,mpc8569-pmc", +- "fsl,mpc8548-pmc"; +- reg = <0x70 0x20>; +- }; +- }; +-}; +- +-&qe { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "qe"; +- compatible = "fsl,qe"; +- sleep = <&pmc 0x00000800>; +- brg-frequency = <0>; +- bus-frequency = <0>; +- fsl,qe-num-riscs = <4>; +- fsl,qe-num-snums = <46>; +- +- qeic: interrupt-controller@80 { +- interrupt-controller; +- compatible = "fsl,qe-ic"; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x80 0x80>; +- interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30 +- interrupt-parent = <&mpic>; +- }; +- +- timer@440 { +- compatible = "fsl,mpc8569-qe-gtm", +- "fsl,qe-gtm", "fsl,gtm"; +- reg = <0x440 0x40>; +- interrupts = <12 13 14 15>; +- interrupt-parent = <&qeic>; +- /* Filled in by U-Boot */ +- clock-frequency = <0>; +- }; +- +- spi@4c0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc8569-qe-spi", "fsl,spi"; +- reg = <0x4c0 0x40>; +- cell-index = <0>; +- interrupts = <2>; +- interrupt-parent = <&qeic>; +- }; +- +- spi@500 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl,spi"; +- reg = <0x500 0x40>; +- interrupts = <1>; +- interrupt-parent = <&qeic>; +- }; +- +- usb@6c0 { +- compatible = "fsl,mpc8569-qe-usb", +- "fsl,mpc8323-qe-usb"; +- reg = <0x6c0 0x40 0x8b00 0x100>; +- interrupts = <11>; +- interrupt-parent = <&qeic>; +- }; +- +- ucc@2000 { +- cell-index = <1>; +- reg = <0x2000 0x200>; +- interrupts = <32>; +- interrupt-parent = <&qeic>; +- }; +- +- ucc@2200 { +- cell-index = <3>; +- reg = <0x2200 0x200>; +- interrupts = <34>; +- interrupt-parent = <&qeic>; +- }; +- +- ucc@3000 { +- cell-index = <2>; +- reg = <0x3000 0x200>; +- interrupts = <33>; +- interrupt-parent = <&qeic>; +- }; +- +- ucc@3200 { +- cell-index = <4>; +- reg = <0x3200 0x200>; +- interrupts = <35>; +- interrupt-parent = <&qeic>; +- }; +- +- ucc@3400 { +- cell-index = <6>; +- reg = <0x3400 0x200>; +- interrupts = <41>; +- interrupt-parent = <&qeic>; +- }; +- +- ucc@3600 { +- cell-index = <8>; +- reg = <0x3600 0x200>; +- interrupts = <43>; +- interrupt-parent = <&qeic>; +- }; +- +- muram@10000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,qe-muram", "fsl,cpm-muram"; +- ranges = <0x0 0x10000 0x20000>; +- +- data-only@0 { +- compatible = "fsl,qe-muram-data", +- "fsl,cpm-muram-data"; +- reg = <0x0 0x20000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8569si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8569si-pre.dtsi +deleted file mode 100644 +index 2cd15a2a0422..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8569si-pre.dtsi ++++ /dev/null +@@ -1,67 +0,0 @@ +-/* +- * MPC8569 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e500v2_power_isa.dtsi" +- +-/ { +- compatible = "fsl,MPC8569"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- pci1 = &pci1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8569@0 { +- device_type = "cpu"; +- reg = <0x0>; +- next-level-cache = <&L2>; +- sleep = <&pmc 0x00008000 // core +- &pmc 0x00004000>; // timebase +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572ds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572ds.dts +deleted file mode 100644 +index 679d53c4a946..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572ds.dts ++++ /dev/null +@@ -1,86 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8572 DS Device Tree Source +- * +- * Copyright 2007-2009 Freescale Semiconductor Inc. +- */ +- +-/include/ "mpc8572si-pre.dtsi" +- +-/ { +- model = "fsl,MPC8572DS"; +- compatible = "fsl,MPC8572DS"; +- +- memory { +- device_type = "memory"; +- }; +- +- board_lbc: lbc: localbus@ffe05000 { +- reg = <0 0xffe05000 0 0x1000>; +- +- ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 +- 0x1 0x0 0x0 0xe0000000 0x08000000 +- 0x2 0x0 0x0 0xffa00000 0x00040000 +- 0x3 0x0 0x0 0xffdf0000 0x00008000 +- 0x4 0x0 0x0 0xffa40000 0x00040000 +- 0x5 0x0 0x0 0xffa80000 0x00040000 +- 0x6 0x0 0x0 0xffac0000 0x00040000>; +- }; +- +- board_soc: soc: soc8572@ffe00000 { +- ranges = <0x0 0 0xffe00000 0x100000>; +- }; +- +- board_pci0: pci0: pcie@ffe08000 { +- reg = <0 0xffe08000 0 0x1000>; +- ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x10000>; +- }; +- }; +- +- pci1: pcie@ffe09000 { +- reg = <0 0xffe09000 0 0x1000>; +- ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x10000>; +- }; +- }; +- +- pci2: pcie@ffe0a000 { +- reg = <0 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xc0000000 +- 0x2000000 0x0 0xc0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x10000>; +- }; +- }; +-}; +- +-/* +- * mpc8572ds.dtsi must be last to ensure board_pci0 overrides pci0 settings +- * for interrupt-map & interrupt-map-mask +- */ +- +-/include/ "mpc8572si-post.dtsi" +-/include/ "mpc8572ds.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572ds.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572ds.dtsi +deleted file mode 100644 +index 357490bb84da..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572ds.dtsi ++++ /dev/null +@@ -1,428 +0,0 @@ +-/* +- * MPC8572DS Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&board_lbc { +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- reg = <0x0 0x03000000>; +- label = "ramdisk-nor"; +- }; +- +- partition@3000000 { +- reg = <0x03000000 0x00e00000>; +- label = "diagnostic-nor"; +- read-only; +- }; +- +- partition@3e00000 { +- reg = <0x03e00000 0x00200000>; +- label = "dink-nor"; +- read-only; +- }; +- +- partition@4000000 { +- reg = <0x04000000 0x00400000>; +- label = "kernel-nor"; +- }; +- +- partition@4400000 { +- reg = <0x04400000 0x03b00000>; +- label = "fs-nor"; +- }; +- +- partition@7f00000 { +- reg = <0x07f00000 0x00060000>; +- label = "dtb-nor"; +- }; +- +- partition@7f60000 { +- reg = <0x07f60000 0x00020000>; +- label = "env-nor"; +- read-only; +- }; +- +- partition@7f80000 { +- reg = <0x07f80000 0x00080000>; +- label = "u-boot-nor"; +- read-only; +- }; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8572-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x2 0x0 0x40000>; +- +- partition@0 { +- reg = <0x0 0x02000000>; +- label = "u-boot-nand"; +- read-only; +- }; +- +- partition@2000000 { +- reg = <0x02000000 0x10000000>; +- label = "fs-nand"; +- }; +- +- partition@12000000 { +- reg = <0x12000000 0x08000000>; +- label = "ramdisk-nand"; +- }; +- +- partition@1a000000 { +- reg = <0x1a000000 0x04000000>; +- label = "kernel-nand"; +- }; +- +- partition@1e000000 { +- reg = <0x1e000000 0x01000000>; +- label = "dtb-nand"; +- }; +- +- partition@1f000000 { +- reg = <0x1f000000 0x21000000>; +- label = "empty-nand"; +- }; +- }; +- +- nand@4,0 { +- compatible = "fsl,mpc8572-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x4 0x0 0x40000>; +- }; +- +- nand@5,0 { +- compatible = "fsl,mpc8572-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x5 0x0 0x40000>; +- }; +- +- nand@6,0 { +- compatible = "fsl,mpc8572-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x6 0x0 0x40000>; +- }; +-}; +- +-&board_soc { +- enet0: ethernet@24000 { +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@24520 { +- phy0: ethernet-phy@0 { +- interrupts = <10 1 0 0>; +- reg = <0x0>; +- }; +- phy1: ethernet-phy@1 { +- interrupts = <10 1 0 0>; +- reg = <0x1>; +- }; +- phy2: ethernet-phy@2 { +- interrupts = <10 1 0 0>; +- reg = <0x2>; +- }; +- phy3: ethernet-phy@3 { +- interrupts = <10 1 0 0>; +- reg = <0x3>; +- }; +- +- sgmii_phy0: sgmii-phy@0 { +- interrupts = <6 1 0 0>; +- reg = <0x1c>; +- }; +- sgmii_phy1: sgmii-phy@1 { +- interrupts = <6 1 0 0>; +- reg = <0x1d>; +- }; +- sgmii_phy2: sgmii-phy@2 { +- interrupts = <7 1 0 0>; +- reg = <0x1e>; +- }; +- sgmii_phy3: sgmii-phy@3 { +- interrupts = <7 1 0 0>; +- reg = <0x1f>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- ptp_clock@24e00 { +- fsl,tclk-period = <5>; +- fsl,tmr-prsc = <200>; +- fsl,tmr-add = <0xAAAAAAAB>; +- fsl,tmr-fiper1 = <0x3B9AC9FB>; +- fsl,tmr-fiper2 = <0x3B9AC9FB>; +- fsl,max-adj = <499999999>; +- }; +- +- enet1: ethernet@25000 { +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- +- }; +- +- mdio@25520 { +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet2: ethernet@26000 { +- tbi-handle = <&tbi2>; +- phy-handle = <&phy2>; +- phy-connection-type = "rgmii-id"; +- +- }; +- mdio@26520 { +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet3: ethernet@27000 { +- tbi-handle = <&tbi3>; +- phy-handle = <&phy3>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@27520 { +- tbi3: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +-}; +- +-&board_pci0 { +- pcie@0 { +- interrupt-map-mask = <0xff00 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x11 func 0 - PCI slot 1 */ +- 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 +- 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 +- 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0 +- 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 +- +- /* IDSEL 0x11 func 1 - PCI slot 1 */ +- 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 +- 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 +- 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1 0 0 +- 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 +- +- /* IDSEL 0x11 func 2 - PCI slot 1 */ +- 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 +- 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 +- 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0 +- 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 +- +- /* IDSEL 0x11 func 3 - PCI slot 1 */ +- 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 +- 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 +- 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0 +- 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 +- +- /* IDSEL 0x11 func 4 - PCI slot 1 */ +- 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 +- 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 +- 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0 +- 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 +- +- /* IDSEL 0x11 func 5 - PCI slot 1 */ +- 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 +- 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 +- 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0 +- 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 +- +- /* IDSEL 0x11 func 6 - PCI slot 1 */ +- 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 +- 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 +- 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0 +- 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 +- +- /* IDSEL 0x11 func 7 - PCI slot 1 */ +- 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 +- 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 +- 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0 +- 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 +- +- /* IDSEL 0x12 func 0 - PCI slot 2 */ +- 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0 +- 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0 +- 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1 0 0 +- 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1 0 0 +- +- /* IDSEL 0x12 func 1 - PCI slot 2 */ +- 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1 0 0 +- 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1 0 0 +- 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1 0 0 +- 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1 0 0 +- +- /* IDSEL 0x12 func 2 - PCI slot 2 */ +- 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1 0 0 +- 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1 0 0 +- 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1 0 0 +- 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1 0 0 +- +- /* IDSEL 0x12 func 3 - PCI slot 2 */ +- 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1 0 0 +- 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1 0 0 +- 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1 0 0 +- 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1 0 0 +- +- /* IDSEL 0x12 func 4 - PCI slot 2 */ +- 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1 0 0 +- 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1 0 0 +- 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1 0 0 +- 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1 0 0 +- +- /* IDSEL 0x12 func 5 - PCI slot 2 */ +- 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1 0 0 +- 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1 0 0 +- 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1 0 0 +- 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1 0 0 +- +- /* IDSEL 0x12 func 6 - PCI slot 2 */ +- 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1 0 0 +- 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1 0 0 +- 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1 0 0 +- 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1 0 0 +- +- /* IDSEL 0x12 func 7 - PCI slot 2 */ +- 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1 0 0 +- 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1 0 0 +- 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1 0 0 +- 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1 0 0 +- +- // IDSEL 0x1c USB +- 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2 +- 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2 +- 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2 +- 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2 +- +- // IDSEL 0x1d Audio +- 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2 +- +- // IDSEL 0x1e Legacy +- 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2 +- 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2 +- +- // IDSEL 0x1f IDE/SATA +- 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2 +- 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2 +- >; +- +- +- uli1575@0 { +- reg = <0x0 0x0 0x0 0x0 0x0>; +- #size-cells = <2>; +- #address-cells = <3>; +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x10000>; +- isa@1e { +- device_type = "isa"; +- #interrupt-cells = <2>; +- #size-cells = <1>; +- #address-cells = <2>; +- reg = <0xf000 0x0 0x0 0x0 0x0>; +- ranges = <0x1 0x0 0x1000000 0x0 0x0 +- 0x1000>; +- interrupt-parent = <&i8259>; +- +- i8259: interrupt-controller@20 { +- reg = <0x1 0x20 0x2 +- 0x1 0xa0 0x2 +- 0x1 0x4d0 0x2>; +- interrupt-controller; +- device_type = "interrupt-controller"; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- compatible = "chrp,iic"; +- interrupts = <9 2 0 0>; +- interrupt-parent = <&mpic>; +- }; +- +- i8042@60 { +- #size-cells = <0>; +- #address-cells = <1>; +- reg = <0x1 0x60 0x1 0x1 0x64 0x1>; +- interrupts = <1 3 12 3>; +- interrupt-parent = +- <&i8259>; +- +- keyboard@0 { +- reg = <0x0>; +- compatible = "pnpPNP,303"; +- }; +- +- mouse@1 { +- reg = <0x1>; +- compatible = "pnpPNP,f03"; +- }; +- }; +- +- rtc@70 { +- compatible = "pnpPNP,b00"; +- reg = <0x1 0x70 0x2>; +- }; +- +- gpio@400 { +- reg = <0x1 0x400 0x80>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572ds_36b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572ds_36b.dts +deleted file mode 100644 +index f2abce2bb201..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572ds_36b.dts ++++ /dev/null +@@ -1,86 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8572DS Device Tree Source (36-bit address map) +- * +- * Copyright 2007-2009 Freescale Semiconductor Inc. +- */ +- +-/include/ "mpc8572si-pre.dtsi" +- +-/ { +- model = "fsl,MPC8572DS"; +- compatible = "fsl,MPC8572DS"; +- +- memory { +- device_type = "memory"; +- }; +- +- board_lbc: lbc: localbus@fffe05000 { +- reg = <0xf 0xffe05000 0 0x1000>; +- +- ranges = <0x0 0x0 0xf 0xe8000000 0x08000000 +- 0x1 0x0 0xf 0xe0000000 0x08000000 +- 0x2 0x0 0xf 0xffa00000 0x00040000 +- 0x3 0x0 0xf 0xffdf0000 0x00008000 +- 0x4 0x0 0xf 0xffa40000 0x00040000 +- 0x5 0x0 0xf 0xffa80000 0x00040000 +- 0x6 0x0 0xf 0xffac0000 0x00040000>; +- }; +- +- board_soc: soc: soc8572@fffe00000 { +- ranges = <0x0 0xf 0xffe00000 0x100000>; +- }; +- +- board_pci0: pci0: pcie@fffe08000 { +- reg = <0xf 0xffe08000 0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x10000>; +- }; +- }; +- +- pci1: pcie@fffe09000 { +- reg = <0xf 0xffe09000 0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x10000>; +- }; +- }; +- +- pci2: pcie@fffe0a000 { +- reg = <0xf 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x10000>; +- }; +- }; +-}; +- +-/* +- * mpc8572ds.dtsi must be last to ensure board_pci0 overrides pci0 settings +- * for interrupt-map & interrupt-map-mask +- */ +- +-/include/ "mpc8572si-post.dtsi" +-/include/ "mpc8572ds.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572ds_camp_core0.dts b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572ds_camp_core0.dts +deleted file mode 100644 +index d1a4993caf55..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572ds_camp_core0.dts ++++ /dev/null +@@ -1,78 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8572 DS Core0 Device Tree Source in CAMP mode. +- * +- * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache +- * can be shared, all the other devices must be assigned to one core only. +- * This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0, +- * eth1, crypto, pci0, pci1. +- * +- * Copyright 2007-2009 Freescale Semiconductor Inc. +- */ +- +-/include/ "mpc8572ds.dts" +- +-/ { +- model = "fsl,MPC8572DS"; +- compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP"; +- +- cpus { +- PowerPC,8572@0 { +- }; +- PowerPC,8572@1 { +- status = "disabled"; +- }; +- }; +- +- localbus@ffe05000 { +- status = "disabled"; +- }; +- +- soc8572@ffe00000 { +- serial@4600 { +- status = "disabled"; +- }; +- dma@c300 { +- status = "disabled"; +- }; +- gpio-controller@f000 { +- }; +- l2-cache-controller@20000 { +- cache-size = <0x80000>; // L2, 512K +- }; +- ethernet@26000 { +- status = "disabled"; +- }; +- mdio@26520 { +- status = "disabled"; +- }; +- ethernet@27000 { +- status = "disabled"; +- }; +- mdio@27520 { +- status = "disabled"; +- }; +- pic@40000 { +- protected-sources = < +- 31 32 33 37 38 39 /* enet2 enet3 */ +- 76 77 78 79 26 42 /* dma2 pci2 serial*/ +- 0xe4 0xe5 0xe6 0xe7 /* msi */ +- >; +- }; +- +- msi@41600 { +- msi-available-ranges = <0 0x80>; +- interrupts = < +- 0xe0 0 0 0 +- 0xe1 0 0 0 +- 0xe2 0 0 0 +- 0xe3 0 0 0>; +- }; +- timer@42100 { +- status = "disabled"; +- }; +- }; +- pcie@ffe0a000 { +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572ds_camp_core1.dts b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572ds_camp_core1.dts +deleted file mode 100644 +index 63e8243ff349..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572ds_camp_core1.dts ++++ /dev/null +@@ -1,111 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8572 DS Core1 Device Tree Source in CAMP mode. +- * +- * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache +- * can be shared, all the other devices must be assigned to one core only. +- * This dts allows core1 to have l2, dma2, eth2, eth3, pci2, msi. +- * +- * Please note to add "-b 1" for core1's dts compiling. +- * +- * Copyright 2007-2009 Freescale Semiconductor Inc. +- */ +- +-/include/ "mpc8572ds.dts" +- +-/ { +- model = "fsl,MPC8572DS"; +- compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP"; +- +- cpus { +- PowerPC,8572@0 { +- status = "disabled"; +- }; +- PowerPC,8572@1 { +- }; +- }; +- +- localbus@ffe05000 { +- status = "disabled"; +- }; +- +- soc8572@ffe00000 { +- ecm-law@0 { +- status = "disabled"; +- }; +- ecm@1000 { +- status = "disabled"; +- }; +- memory-controller@2000 { +- status = "disabled"; +- }; +- memory-controller@6000 { +- status = "disabled"; +- }; +- i2c@3000 { +- status = "disabled"; +- }; +- i2c@3100 { +- status = "disabled"; +- }; +- serial@4500 { +- status = "disabled"; +- }; +- gpio-controller@f000 { +- status = "disabled"; +- }; +- l2-cache-controller@20000 { +- cache-size = <0x80000>; // L2, 512K +- }; +- dma@21300 { +- status = "disabled"; +- }; +- ethernet@24000 { +- status = "disabled"; +- }; +- ptp_clock@24e00 { +- status = "disabled"; +- }; +- ethernet@25000 { +- status = "disabled"; +- }; +- mdio@25520 { +- status = "disabled"; +- }; +- crypto@30000 { +- status = "disabled"; +- }; +- pic@40000 { +- protected-sources = < +- 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */ +- 29 30 34 35 36 40 /* enet0 enet1 */ +- 24 25 20 21 22 23 /* pci0 pci1 dma1 */ +- 43 /* i2c */ +- 0x1 0x2 0x3 0x4 /* pci slot */ +- 0x9 0xa 0xb 0xc /* usb */ +- 0x6 0x7 0xe 0x5 /* Audio elgacy SATA */ +- 0xe0 0xe1 0xe2 0xe3 /* msi */ +- >; +- }; +- timer@41100 { +- status = "disabled"; +- }; +- msi@41600 { +- msi-available-ranges = <0x80 0x80>; +- interrupts = < +- 0xe4 0 0 0 +- 0xe5 0 0 0 +- 0xe6 0 0 0 +- 0xe7 0 0 0>; +- }; +- global-utilities@e0000 { +- status = "disabled"; +- }; +- }; +- pcie@ffe08000 { +- status = "disabled"; +- }; +- pcie@ffe09000 { +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572si-post.dtsi +deleted file mode 100644 +index 49294cf36b4e..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572si-post.dtsi ++++ /dev/null +@@ -1,196 +0,0 @@ +-/* +- * MPC8572 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&lbc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; +- interrupts = <19 2 0 0>; +-}; +- +-/* controller at 0x8000 */ +-&pci0 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <24 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <24 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0 +- >; +- }; +-}; +- +-/* controller at 0x9000 */ +-&pci1 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <25 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <25 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 +- >; +- }; +-}; +- +-/* controller at 0xa000 */ +-&pci2 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <26 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <26 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 +- >; +- }; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,mpc8572-immr", "simple-bus"; +- bus-frequency = <0>; // Filled out by uboot. +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <12>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8572-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2 0 0>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8572-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupts = <18 2 0 0>; +- }; +- +- memory-controller@6000 { +- compatible = "fsl,mpc8572-memory-controller"; +- reg = <0x6000 0x1000>; +- interrupts = <18 2 0 0>; +- }; +- +-/include/ "pq3-i2c-0.dtsi" +-/include/ "pq3-i2c-1.dtsi" +-/include/ "pq3-duart-0.dtsi" +-/include/ "pq3-dma-1.dtsi" +-/include/ "pq3-gpio-0.dtsi" +- gpio-controller@f000 { +- compatible = "fsl,mpc8572-gpio"; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8572-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x100000>; // L2,1M +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-dma-0.dtsi" +-/include/ "pq3-etsec1-0.dtsi" +-/include/ "pq3-etsec1-timer-0.dtsi" +- +- ptp_clock@24e00 { +- interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>; +- }; +- +-/include/ "pq3-etsec1-1.dtsi" +-/include/ "pq3-etsec1-2.dtsi" +-/include/ "pq3-etsec1-3.dtsi" +-/include/ "pq3-sec3.0-0.dtsi" +-/include/ "pq3-mpic.dtsi" +-/include/ "pq3-mpic-timer-B.dtsi" +- +- global-utilities@e0000 { +- compatible = "fsl,mpc8572-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572si-pre.dtsi +deleted file mode 100644 +index 28c2a862be96..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572si-pre.dtsi ++++ /dev/null +@@ -1,73 +0,0 @@ +-/* +- * MPC8572 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e500v2_power_isa.dtsi" +- +-/ { +- compatible = "fsl,MPC8572"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8572@0 { +- device_type = "cpu"; +- reg = <0x0>; +- next-level-cache = <&L2>; +- }; +- +- PowerPC,8572@1 { +- device_type = "cpu"; +- reg = <0x1>; +- next-level-cache = <&L2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8641_hpcn.dts b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8641_hpcn.dts +deleted file mode 100644 +index f7a2430d6629..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8641_hpcn.dts ++++ /dev/null +@@ -1,394 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8641 HPCN Device Tree Source +- * +- * Copyright 2006 Freescale Semiconductor Inc. +- */ +- +-/include/ "mpc8641si-pre.dtsi" +- +-/ { +- model = "MPC8641HPCN"; +- compatible = "fsl,mpc8641hpcn"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x40000000>; // 1G at 0x0 +- }; +- +- lbc: localbus@ffe05000 { +- reg = <0xffe05000 0x1000>; +- +- ranges = <0 0 0xef800000 0x00800000 +- 2 0 0xffdf8000 0x00008000 +- 3 0 0xffdf0000 0x00008000>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x00800000>; +- bank-width = <2>; +- device-width = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x00300000>; +- }; +- partition@300000 { +- label = "firmware b"; +- reg = <0x00300000 0x00100000>; +- read-only; +- }; +- partition@400000 { +- label = "fs"; +- reg = <0x00400000 0x00300000>; +- }; +- partition@700000 { +- label = "firmware a"; +- reg = <0x00700000 0x00100000>; +- read-only; +- }; +- }; +- }; +- +- soc: soc8641@ffe00000 { +- ranges = <0x00000000 0xffe00000 0x00100000>; +- +- enet0: ethernet@24000 { +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@24520 { +- phy0: ethernet-phy@0 { +- interrupts = <10 1 0 0>; +- reg = <0>; +- }; +- phy1: ethernet-phy@1 { +- interrupts = <10 1 0 0>; +- reg = <1>; +- }; +- phy2: ethernet-phy@2 { +- interrupts = <10 1 0 0>; +- reg = <2>; +- }; +- phy3: ethernet-phy@3 { +- interrupts = <10 1 0 0>; +- reg = <3>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet1: ethernet@25000 { +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@25520 { +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet2: ethernet@26000 { +- tbi-handle = <&tbi2>; +- phy-handle = <&phy2>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@26520 { +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet3: ethernet@27000 { +- tbi-handle = <&tbi3>; +- phy-handle = <&phy3>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@27520 { +- tbi3: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- rmu: rmu@d3000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,srio-rmu"; +- reg = <0xd3000 0x500>; +- ranges = <0x0 0xd3000 0x500>; +- +- message-unit@0 { +- compatible = "fsl,srio-msg-unit"; +- reg = <0x0 0x100>; +- interrupts = < +- 53 2 0 0 /* msg1_tx_irq */ +- 54 2 0 0>;/* msg1_rx_irq */ +- }; +- message-unit@100 { +- compatible = "fsl,srio-msg-unit"; +- reg = <0x100 0x100>; +- interrupts = < +- 55 2 0 0 /* msg2_tx_irq */ +- 56 2 0 0>;/* msg2_rx_irq */ +- }; +- doorbell-unit@400 { +- compatible = "fsl,srio-dbell-unit"; +- reg = <0x400 0x80>; +- interrupts = < +- 49 2 0 0 /* bell_outb_irq */ +- 50 2 0 0>;/* bell_inb_irq */ +- }; +- port-write-unit@4e0 { +- compatible = "fsl,srio-port-write-unit"; +- reg = <0x4e0 0x20>; +- interrupts = <48 2 0 0>; +- }; +- }; +- }; +- +- pci0: pcie@ffe08000 { +- reg = <0xffe08000 0x1000>; +- ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000 +- 0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>; +- interrupt-map-mask = <0xff00 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x11 func 0 - PCI slot 1 */ +- 0x8800 0 0 1 &mpic 2 1 0 0 +- 0x8800 0 0 2 &mpic 3 1 0 0 +- 0x8800 0 0 3 &mpic 4 1 0 0 +- 0x8800 0 0 4 &mpic 1 1 0 0 +- +- /* IDSEL 0x11 func 1 - PCI slot 1 */ +- 0x8900 0 0 1 &mpic 2 1 0 0 +- 0x8900 0 0 2 &mpic 3 1 0 0 +- 0x8900 0 0 3 &mpic 4 1 0 0 +- 0x8900 0 0 4 &mpic 1 1 0 0 +- +- /* IDSEL 0x11 func 2 - PCI slot 1 */ +- 0x8a00 0 0 1 &mpic 2 1 0 0 +- 0x8a00 0 0 2 &mpic 3 1 0 0 +- 0x8a00 0 0 3 &mpic 4 1 0 0 +- 0x8a00 0 0 4 &mpic 1 1 0 0 +- +- /* IDSEL 0x11 func 3 - PCI slot 1 */ +- 0x8b00 0 0 1 &mpic 2 1 0 0 +- 0x8b00 0 0 2 &mpic 3 1 0 0 +- 0x8b00 0 0 3 &mpic 4 1 0 0 +- 0x8b00 0 0 4 &mpic 1 1 0 0 +- +- /* IDSEL 0x11 func 4 - PCI slot 1 */ +- 0x8c00 0 0 1 &mpic 2 1 0 0 +- 0x8c00 0 0 2 &mpic 3 1 0 0 +- 0x8c00 0 0 3 &mpic 4 1 0 0 +- 0x8c00 0 0 4 &mpic 1 1 0 0 +- +- /* IDSEL 0x11 func 5 - PCI slot 1 */ +- 0x8d00 0 0 1 &mpic 2 1 0 0 +- 0x8d00 0 0 2 &mpic 3 1 0 0 +- 0x8d00 0 0 3 &mpic 4 1 0 0 +- 0x8d00 0 0 4 &mpic 1 1 0 0 +- +- /* IDSEL 0x11 func 6 - PCI slot 1 */ +- 0x8e00 0 0 1 &mpic 2 1 0 0 +- 0x8e00 0 0 2 &mpic 3 1 0 0 +- 0x8e00 0 0 3 &mpic 4 1 0 0 +- 0x8e00 0 0 4 &mpic 1 1 0 0 +- +- /* IDSEL 0x11 func 7 - PCI slot 1 */ +- 0x8f00 0 0 1 &mpic 2 1 0 0 +- 0x8f00 0 0 2 &mpic 3 1 0 0 +- 0x8f00 0 0 3 &mpic 4 1 0 0 +- 0x8f00 0 0 4 &mpic 1 1 0 0 +- +- /* IDSEL 0x12 func 0 - PCI slot 2 */ +- 0x9000 0 0 1 &mpic 3 1 0 0 +- 0x9000 0 0 2 &mpic 4 1 0 0 +- 0x9000 0 0 3 &mpic 1 1 0 0 +- 0x9000 0 0 4 &mpic 2 1 0 0 +- +- /* IDSEL 0x12 func 1 - PCI slot 2 */ +- 0x9100 0 0 1 &mpic 3 1 0 0 +- 0x9100 0 0 2 &mpic 4 1 0 0 +- 0x9100 0 0 3 &mpic 1 1 0 0 +- 0x9100 0 0 4 &mpic 2 1 0 0 +- +- /* IDSEL 0x12 func 2 - PCI slot 2 */ +- 0x9200 0 0 1 &mpic 3 1 0 0 +- 0x9200 0 0 2 &mpic 4 1 0 0 +- 0x9200 0 0 3 &mpic 1 1 0 0 +- 0x9200 0 0 4 &mpic 2 1 0 0 +- +- /* IDSEL 0x12 func 3 - PCI slot 2 */ +- 0x9300 0 0 1 &mpic 3 1 0 0 +- 0x9300 0 0 2 &mpic 4 1 0 0 +- 0x9300 0 0 3 &mpic 1 1 0 0 +- 0x9300 0 0 4 &mpic 2 1 0 0 +- +- /* IDSEL 0x12 func 4 - PCI slot 2 */ +- 0x9400 0 0 1 &mpic 3 1 0 0 +- 0x9400 0 0 2 &mpic 4 1 0 0 +- 0x9400 0 0 3 &mpic 1 1 0 0 +- 0x9400 0 0 4 &mpic 2 1 0 0 +- +- /* IDSEL 0x12 func 5 - PCI slot 2 */ +- 0x9500 0 0 1 &mpic 3 1 0 0 +- 0x9500 0 0 2 &mpic 4 1 0 0 +- 0x9500 0 0 3 &mpic 1 1 0 0 +- 0x9500 0 0 4 &mpic 2 1 0 0 +- +- /* IDSEL 0x12 func 6 - PCI slot 2 */ +- 0x9600 0 0 1 &mpic 3 1 0 0 +- 0x9600 0 0 2 &mpic 4 1 0 0 +- 0x9600 0 0 3 &mpic 1 1 0 0 +- 0x9600 0 0 4 &mpic 2 1 0 0 +- +- /* IDSEL 0x12 func 7 - PCI slot 2 */ +- 0x9700 0 0 1 &mpic 3 1 0 0 +- 0x9700 0 0 2 &mpic 4 1 0 0 +- 0x9700 0 0 3 &mpic 1 1 0 0 +- 0x9700 0 0 4 &mpic 2 1 0 0 +- +- // IDSEL 0x1c USB +- 0xe000 0 0 1 &i8259 12 2 +- 0xe100 0 0 2 &i8259 9 2 +- 0xe200 0 0 3 &i8259 10 2 +- 0xe300 0 0 4 &i8259 11 2 +- +- // IDSEL 0x1d Audio +- 0xe800 0 0 1 &i8259 6 2 +- +- // IDSEL 0x1e Legacy +- 0xf000 0 0 1 &i8259 7 2 +- 0xf100 0 0 1 &i8259 7 2 +- +- // IDSEL 0x1f IDE/SATA +- 0xf800 0 0 1 &i8259 14 2 +- 0xf900 0 0 1 &i8259 5 2 +- >; +- +- pcie@0 { +- ranges = <0x02000000 0x0 0x80000000 +- 0x02000000 0x0 0x80000000 +- 0x0 0x20000000 +- +- 0x01000000 0x0 0x00000000 +- 0x01000000 0x0 0x00000000 +- 0x0 0x00010000>; +- uli1575@0 { +- reg = <0 0 0 0 0>; +- #size-cells = <2>; +- #address-cells = <3>; +- ranges = <0x02000000 0x0 0x80000000 +- 0x02000000 0x0 0x80000000 +- 0x0 0x20000000 +- 0x01000000 0x0 0x00000000 +- 0x01000000 0x0 0x00000000 +- 0x0 0x00010000>; +- isa@1e { +- device_type = "isa"; +- #size-cells = <1>; +- #address-cells = <2>; +- reg = <0xf000 0 0 0 0>; +- ranges = <1 0 0x01000000 0 0 +- 0x00001000>; +- interrupt-parent = <&i8259>; +- +- i8259: interrupt-controller@20 { +- reg = <1 0x20 2 +- 1 0xa0 2 +- 1 0x4d0 2>; +- interrupt-controller; +- device_type = "interrupt-controller"; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- compatible = "chrp,iic"; +- interrupts = <9 2 0 0>; +- }; +- +- i8042@60 { +- #size-cells = <0>; +- #address-cells = <1>; +- reg = <1 0x60 1 1 0x64 1>; +- interrupts = <1 3 12 3>; +- interrupt-parent = <&i8259>; +- +- keyboard@0 { +- reg = <0>; +- compatible = "pnpPNP,303"; +- }; +- +- mouse@1 { +- reg = <1>; +- compatible = "pnpPNP,f03"; +- }; +- }; +- +- rtc@70 { +- compatible = +- "pnpPNP,b00"; +- reg = <1 0x70 2>; +- }; +- +- gpio@400 { +- reg = <1 0x400 0x80>; +- }; +- }; +- }; +- }; +- +- }; +- +- pci1: pcie@ffe09000 { +- reg = <0xffe09000 0x1000>; +- ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 +- 0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>; +- +- pcie@0 { +- ranges = <0x02000000 0x0 0xa0000000 +- 0x02000000 0x0 0xa0000000 +- 0x0 0x20000000 +- +- 0x01000000 0x0 0x00000000 +- 0x01000000 0x0 0x00000000 +- 0x0 0x00010000>; +- }; +- }; +-/* +- * Only one of Rapid IO or PCI can be present due to HW limitations and +- * due to the fact that the 2 now share address space in the new memory +- * map. The most likely case is that we have PCI, so comment out the +- * rapidio node. Leave it here for reference. +- +- rapidio@ffec0000 { +- reg = <0xffec0000 0x11000>; +- compatible = "fsl,srio"; +- interrupts = <48 2 0 0>; +- #address-cells = <2>; +- #size-cells = <2>; +- fsl,srio-rmu-handle = <&rmu>; +- ranges; +- +- port1 { +- #address-cells = <2>; +- #size-cells = <2>; +- cell-index = <1>; +- ranges = <0 0 0x80000000 0 0x20000000>; +- }; +- }; +-*/ +- +-}; +- +-/include/ "mpc8641si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8641_hpcn_36b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8641_hpcn_36b.dts +deleted file mode 100644 +index 3f5f7a99b9ea..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8641_hpcn_36b.dts ++++ /dev/null +@@ -1,337 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8641 HPCN Device Tree Source +- * +- * Copyright 2008-2009 Freescale Semiconductor Inc. +- */ +- +-/include/ "mpc8641si-pre.dtsi" +- +-/ { +- model = "MPC8641HPCN"; +- compatible = "fsl,mpc8641hpcn"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0 +- }; +- +- lbc: localbus@fffe05000 { +- reg = <0x0f 0xffe05000 0x0 0x1000>; +- +- ranges = <0 0 0xf 0xef800000 0x00800000 +- 2 0 0xf 0xffdf8000 0x00008000 +- 3 0 0xf 0xffdf0000 0x00008000>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x00800000>; +- bank-width = <2>; +- device-width = <2>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x00300000>; +- }; +- partition@300000 { +- label = "firmware b"; +- reg = <0x00300000 0x00100000>; +- read-only; +- }; +- partition@400000 { +- label = "fs"; +- reg = <0x00400000 0x00300000>; +- }; +- partition@700000 { +- label = "firmware a"; +- reg = <0x00700000 0x00100000>; +- read-only; +- }; +- }; +- }; +- +- soc: soc8641@fffe00000 { +- ranges = <0x00000000 0x0f 0xffe00000 0x00100000>; +- +- enet0: ethernet@24000 { +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@24520 { +- phy0: ethernet-phy@0 { +- interrupts = <10 1 0 0>; +- reg = <0>; +- }; +- phy1: ethernet-phy@1 { +- interrupts = <10 1 0 0>; +- reg = <1>; +- }; +- phy2: ethernet-phy@2 { +- interrupts = <10 1 0 0>; +- reg = <2>; +- }; +- phy3: ethernet-phy@3 { +- interrupts = <10 1 0 0>; +- reg = <3>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet1: ethernet@25000 { +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@25520 { +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet2: ethernet@26000 { +- tbi-handle = <&tbi2>; +- phy-handle = <&phy2>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@26520 { +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet3: ethernet@27000 { +- tbi-handle = <&tbi3>; +- phy-handle = <&phy3>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@27520 { +- tbi3: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- pci0: pcie@fffe08000 { +- reg = <0x0f 0xffe08000 0x0 0x1000>; +- ranges = <0x02000000 0x0 0xe0000000 0x0c 0x00000000 0x0 0x20000000 +- 0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>; +- interrupt-map-mask = <0xff00 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x11 func 0 - PCI slot 1 */ +- 0x8800 0 0 1 &mpic 2 1 0 0 +- 0x8800 0 0 2 &mpic 3 1 0 0 +- 0x8800 0 0 3 &mpic 4 1 0 0 +- 0x8800 0 0 4 &mpic 1 1 0 0 +- +- /* IDSEL 0x11 func 1 - PCI slot 1 */ +- 0x8900 0 0 1 &mpic 2 1 0 0 +- 0x8900 0 0 2 &mpic 3 1 0 0 +- 0x8900 0 0 3 &mpic 4 1 0 0 +- 0x8900 0 0 4 &mpic 1 1 0 0 +- +- /* IDSEL 0x11 func 2 - PCI slot 1 */ +- 0x8a00 0 0 1 &mpic 2 1 0 0 +- 0x8a00 0 0 2 &mpic 3 1 0 0 +- 0x8a00 0 0 3 &mpic 4 1 0 0 +- 0x8a00 0 0 4 &mpic 1 1 0 0 +- +- /* IDSEL 0x11 func 3 - PCI slot 1 */ +- 0x8b00 0 0 1 &mpic 2 1 0 0 +- 0x8b00 0 0 2 &mpic 3 1 0 0 +- 0x8b00 0 0 3 &mpic 4 1 0 0 +- 0x8b00 0 0 4 &mpic 1 1 0 0 +- +- /* IDSEL 0x11 func 4 - PCI slot 1 */ +- 0x8c00 0 0 1 &mpic 2 1 0 0 +- 0x8c00 0 0 2 &mpic 3 1 0 0 +- 0x8c00 0 0 3 &mpic 4 1 0 0 +- 0x8c00 0 0 4 &mpic 1 1 0 0 +- +- /* IDSEL 0x11 func 5 - PCI slot 1 */ +- 0x8d00 0 0 1 &mpic 2 1 0 0 +- 0x8d00 0 0 2 &mpic 3 1 0 0 +- 0x8d00 0 0 3 &mpic 4 1 0 0 +- 0x8d00 0 0 4 &mpic 1 1 0 0 +- +- /* IDSEL 0x11 func 6 - PCI slot 1 */ +- 0x8e00 0 0 1 &mpic 2 1 0 0 +- 0x8e00 0 0 2 &mpic 3 1 0 0 +- 0x8e00 0 0 3 &mpic 4 1 0 0 +- 0x8e00 0 0 4 &mpic 1 1 0 0 +- +- /* IDSEL 0x11 func 7 - PCI slot 1 */ +- 0x8f00 0 0 1 &mpic 2 1 0 0 +- 0x8f00 0 0 2 &mpic 3 1 0 0 +- 0x8f00 0 0 3 &mpic 4 1 0 0 +- 0x8f00 0 0 4 &mpic 1 1 0 0 +- +- /* IDSEL 0x12 func 0 - PCI slot 2 */ +- 0x9000 0 0 1 &mpic 3 1 0 0 +- 0x9000 0 0 2 &mpic 4 1 0 0 +- 0x9000 0 0 3 &mpic 1 1 0 0 +- 0x9000 0 0 4 &mpic 2 1 0 0 +- +- /* IDSEL 0x12 func 1 - PCI slot 2 */ +- 0x9100 0 0 1 &mpic 3 1 0 0 +- 0x9100 0 0 2 &mpic 4 1 0 0 +- 0x9100 0 0 3 &mpic 1 1 0 0 +- 0x9100 0 0 4 &mpic 2 1 0 0 +- +- /* IDSEL 0x12 func 2 - PCI slot 2 */ +- 0x9200 0 0 1 &mpic 3 1 0 0 +- 0x9200 0 0 2 &mpic 4 1 0 0 +- 0x9200 0 0 3 &mpic 1 1 0 0 +- 0x9200 0 0 4 &mpic 2 1 0 0 +- +- /* IDSEL 0x12 func 3 - PCI slot 2 */ +- 0x9300 0 0 1 &mpic 3 1 0 0 +- 0x9300 0 0 2 &mpic 4 1 0 0 +- 0x9300 0 0 3 &mpic 1 1 0 0 +- 0x9300 0 0 4 &mpic 2 1 0 0 +- +- /* IDSEL 0x12 func 4 - PCI slot 2 */ +- 0x9400 0 0 1 &mpic 3 1 0 0 +- 0x9400 0 0 2 &mpic 4 1 0 0 +- 0x9400 0 0 3 &mpic 1 1 0 0 +- 0x9400 0 0 4 &mpic 2 1 0 0 +- +- /* IDSEL 0x12 func 5 - PCI slot 2 */ +- 0x9500 0 0 1 &mpic 3 1 0 0 +- 0x9500 0 0 2 &mpic 4 1 0 0 +- 0x9500 0 0 3 &mpic 1 1 0 0 +- 0x9500 0 0 4 &mpic 2 1 0 0 +- +- /* IDSEL 0x12 func 6 - PCI slot 2 */ +- 0x9600 0 0 1 &mpic 3 1 0 0 +- 0x9600 0 0 2 &mpic 4 1 0 0 +- 0x9600 0 0 3 &mpic 1 1 0 0 +- 0x9600 0 0 4 &mpic 2 1 0 0 +- +- /* IDSEL 0x12 func 7 - PCI slot 2 */ +- 0x9700 0 0 1 &mpic 3 1 0 0 +- 0x9700 0 0 2 &mpic 4 1 0 0 +- 0x9700 0 0 3 &mpic 1 1 0 0 +- 0x9700 0 0 4 &mpic 2 1 0 0 +- +- // IDSEL 0x1c USB +- 0xe000 0 0 1 &i8259 12 2 +- 0xe100 0 0 2 &i8259 9 2 +- 0xe200 0 0 3 &i8259 10 2 +- 0xe300 0 0 4 &i8259 11 2 +- +- // IDSEL 0x1d Audio +- 0xe800 0 0 1 &i8259 6 2 +- +- // IDSEL 0x1e Legacy +- 0xf000 0 0 1 &i8259 7 2 +- 0xf100 0 0 1 &i8259 7 2 +- +- // IDSEL 0x1f IDE/SATA +- 0xf800 0 0 1 &i8259 14 2 +- 0xf900 0 0 1 &i8259 5 2 +- >; +- +- pcie@0 { +- ranges = <0x02000000 0x0 0xe0000000 +- 0x02000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x01000000 0x0 0x00000000 +- 0x01000000 0x0 0x00000000 +- 0x0 0x00010000>; +- uli1575@0 { +- reg = <0 0 0 0 0>; +- #size-cells = <2>; +- #address-cells = <3>; +- ranges = <0x02000000 0x0 0xe0000000 +- 0x02000000 0x0 0xe0000000 +- 0x0 0x20000000 +- 0x01000000 0x0 0x00000000 +- 0x01000000 0x0 0x00000000 +- 0x0 0x00010000>; +- isa@1e { +- device_type = "isa"; +- #size-cells = <1>; +- #address-cells = <2>; +- reg = <0xf000 0 0 0 0>; +- ranges = <1 0 0x01000000 0 0 +- 0x00001000>; +- interrupt-parent = <&i8259>; +- +- i8259: interrupt-controller@20 { +- reg = <1 0x20 2 +- 1 0xa0 2 +- 1 0x4d0 2>; +- interrupt-controller; +- device_type = "interrupt-controller"; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- compatible = "chrp,iic"; +- interrupts = <9 2 0 0>; +- }; +- +- i8042@60 { +- #size-cells = <0>; +- #address-cells = <1>; +- reg = <1 0x60 1 1 0x64 1>; +- interrupts = <1 3 12 3>; +- interrupt-parent = <&i8259>; +- +- keyboard@0 { +- reg = <0>; +- compatible = "pnpPNP,303"; +- }; +- +- mouse@1 { +- reg = <1>; +- compatible = "pnpPNP,f03"; +- }; +- }; +- +- rtc@70 { +- compatible = +- "pnpPNP,b00"; +- reg = <1 0x70 2>; +- }; +- +- gpio@400 { +- reg = <1 0x400 0x80>; +- }; +- }; +- }; +- }; +- +- }; +- +- pci1: pcie@fffe09000 { +- reg = <0x0f 0xffe09000 0x0 0x1000>; +- ranges = <0x02000000 0x0 0xe0000000 0x0c 0x20000000 0x0 0x20000000 +- 0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>; +- +- pcie@0 { +- ranges = <0x02000000 0x0 0xe0000000 +- 0x02000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x01000000 0x0 0x00000000 +- 0x01000000 0x0 0x00000000 +- 0x0 0x00010000>; +- }; +- }; +-}; +- +-/include/ "mpc8641si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8641si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8641si-post.dtsi +deleted file mode 100644 +index 77900b924151..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8641si-post.dtsi ++++ /dev/null +@@ -1,144 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8641 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A. +- */ +- +-&lbc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8641-localbus", "simple-bus"; +- interrupts = <19 2 0 0>; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,mpc8641-soc", "simple-bus"; +- bus-frequency = <0>; +- +- mcm-law@0 { +- compatible = "fsl,mcm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <10>; +- }; +- +- mcm@1000 { +- compatible = "fsl,mpc8641-mcm", "fsl,mcm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2 0 0>; +- }; +- +-/include/ "pq3-i2c-0.dtsi" +-/include/ "pq3-i2c-1.dtsi" +-/include/ "pq3-duart-0.dtsi" +- serial@4600 { +- interrupts = <28 2 0 0>; +- }; +-/include/ "pq3-dma-0.dtsi" +- dma@21300 { +- compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; +- }; +- dma-channel@0 { +- compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; +- }; +- +-/include/ "pq3-etsec1-0.dtsi" +- ethernet@24000 { +- model = "TSEC"; +- }; +-/include/ "pq3-etsec1-1.dtsi" +- ethernet@25000 { +- model = "TSEC"; +- }; +-/include/ "pq3-etsec1-2.dtsi" +- ethernet@26000 { +- model = "TSEC"; +- }; +-/include/ "pq3-etsec1-3.dtsi" +- ethernet@27000 { +- model = "TSEC"; +- }; +- +-/include/ "qoriq-mpic.dtsi" +- msi@41600 { +- compatible = "fsl,mpc8641-msi", "fsl,mpic-msi"; +- }; +- msi@41800 { +- compatible = "fsl,mpc8641-msi", "fsl,mpic-msi"; +- }; +- msi@41a00 { +- compatible = "fsl,mpc8641-msi", "fsl,mpic-msi"; +- }; +- +- global-utilities@e0000 { +- compatible = "fsl,mpc8641-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +-}; +- +-&pci0 { +- compatible = "fsl,mpc8641-pcie"; +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- clock-frequency = <100000000>; +- interrupts = <24 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <24 2 0 0>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 +- 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 +- 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 +- 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 +- >; +- }; +-}; +- +-&pci1 { +- compatible = "fsl,mpc8641-pcie"; +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- clock-frequency = <100000000>; +- interrupts = <25 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <25 2 0 0>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 +- 0x0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 +- 0x0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 +- 0x0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8641si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/mpc8641si-pre.dtsi +deleted file mode 100644 +index a9f7e79d3364..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mpc8641si-pre.dtsi ++++ /dev/null +@@ -1,54 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8641 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&mpic>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- pci1 = &pci1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8641@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- }; +- +- PowerPC,8641@1 { +- device_type = "cpu"; +- reg = <1>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mvme2500.dts b/scripts/dtc/include-prefixes/powerpc/fsl/mvme2500.dts +deleted file mode 100644 +index e0f048a03956..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mvme2500.dts ++++ /dev/null +@@ -1,276 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Device tree source for the Emerson/Artesyn MVME2500 +- * +- * Copyright 2014 Elettra-Sincrotrone Trieste S.C.p.A. +- * +- * Based on: P2020 DS Device Tree Source +- * Copyright 2009 Freescale Semiconductor Inc. +- */ +- +-/include/ "p2020si-pre.dtsi" +- +-/ { +- model = "MVME2500"; +- compatible = "artesyn,MVME2500"; +- +- aliases { +- serial2 = &serial2; +- serial3 = &serial3; +- serial4 = &serial4; +- serial5 = &serial5; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- soc: soc@ffe00000 { +- ranges = <0x0 0 0xffe00000 0x100000>; +- +- i2c@3000 { +- hwmon@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1337"; +- reg = <0x68>; +- interrupts = <8 1 0 0>; +- }; +- +- eeprom@54 { +- compatible = "atmel,24c64"; +- reg = <0x54>; +- }; +- +- eeprom@52 { +- compatible = "atmel,24c512"; +- reg = <0x52>; +- }; +- +- eeprom@53 { +- compatible = "atmel,24c512"; +- reg = <0x53>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- }; +- +- }; +- +- spi0: spi@7000 { +- fsl,espi-num-chipselects = <2>; +- +- flash@0 { +- compatible = "atmel,at25df641", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <10000000>; +- }; +- flash@1 { +- compatible = "atmel,at25df641", "jedec,spi-nor"; +- reg = <1>; +- spi-max-frequency = <10000000>; +- }; +- }; +- +- usb@22000 { +- dr_mode = "host"; +- phy_type = "ulpi"; +- }; +- +- enet0: ethernet@24000 { +- tbi-handle = <&tbi0>; +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@24520 { +- phy1: ethernet-phy@1 { +- compatible = "brcm,bcm54616S"; +- interrupts = <6 1 0 0>; +- reg = <0x1>; +- }; +- +- phy2: ethernet-phy@2 { +- compatible = "brcm,bcm54616S"; +- interrupts = <6 1 0 0>; +- reg = <0x2>; +- }; +- +- phy3: ethernet-phy@3 { +- compatible = "brcm,bcm54616S"; +- interrupts = <5 1 0 0>; +- reg = <0x3>; +- }; +- +- phy7: ethernet-phy@7 { +- compatible = "brcm,bcm54616S"; +- interrupts = <7 1 0 0>; +- reg = <0x7>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet1: ethernet@25000 { +- tbi-handle = <&tbi1>; +- phy-handle = <&phy7>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@25520 { +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet2: ethernet@26000 { +- tbi-handle = <&tbi2>; +- phy-handle = <&phy3>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@26520 { +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- lbc: localbus@ffe05000 { +- reg = <0 0xffe05000 0 0x1000>; +- +- ranges = <0x0 0x0 0x0 0xfff00000 0x00080000 +- 0x1 0x0 0x0 0xffc40000 0x00010000 +- 0x2 0x0 0x0 0xffc50000 0x00010000 +- 0x3 0x0 0x0 0xffc60000 0x00010000 +- 0x4 0x0 0x0 0xffc70000 0x00010000 +- 0x6 0x0 0x0 0xffc80000 0x00010000 +- 0x5 0x0 0x0 0xffdf0000 0x00008000>; +- +- serial2: serial@1,0 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0x1 0x0 0x100>; +- clock-frequency = <1843200>; +- interrupts = <11 2 0 0>; +- }; +- +- serial3: serial@2,0 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0x2 0x0 0x100>; +- clock-frequency = <1843200>; +- interrupts = <1 2 0 0>; +- }; +- +- serial4: serial@3,0 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0x3 0x0 0x100>; +- clock-frequency = <1843200>; +- interrupts = <2 2 0 0>; +- }; +- +- serial5: serial@4,0 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0x4 0x0 0x100>; +- clock-frequency = <1843200>; +- interrupts = <3 2 0 0>; +- }; +- +- mram@0,0 { +- compatible = "everspin,mram", "mtd-ram"; +- reg = <0x0 0x0 0x80000>; +- bank-width = <2>; +- }; +- +- board-control@5,0 { +- compatible = "artesyn,mvme2500-fpga"; +- reg = <0x5 0x0 0x01000>; +- }; +- +- cpld@6,0 { +- compatible = "artesyn,mvme2500-cpld"; +- reg = <0x6 0x0 0x10000>; +- interrupts = <9 1 0 0>; +- }; +- }; +- +- pci0: pcie@ffe08000 { +- reg = <0 0xffe08000 0 0x1000>; +- ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x10000>; +- }; +- }; +- +- pci1: pcie@ffe09000 { +- reg = <0 0xffe09000 0 0x1000>; +- ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x10000>; +- }; +- +- }; +- +- pci2: pcie@ffe0a000 { +- reg = <0 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xc0000000 +- 0x2000000 0x0 0xc0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x10000>; +- }; +- }; +-}; +- +-/include/ "p2020si-post.dtsi" +- +-/ { +- soc@ffe00000 { +- serial@4600 { +- status = "disabled"; +- }; +- +- i2c@3100 { +- status = "disabled"; +- }; +- +- sdhc@2e000 { +- compatible = "fsl,p2020-esdhc", "fsl,esdhc"; +- non-removable; +- }; +- +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/mvme7100.dts b/scripts/dtc/include-prefixes/powerpc/fsl/mvme7100.dts +deleted file mode 100644 +index bcc9dedd630f..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/mvme7100.dts ++++ /dev/null +@@ -1,148 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Device tree source for the Emerson/Artesyn MVME7100 +- * +- * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A. +- * +- * Author: Alessio Igor Bogani +- */ +- +-/include/ "mpc8641si-pre.dtsi" +- +-/ { +- model = "MVME7100"; +- compatible = "artesyn,MVME7100"; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x80000000>; +- }; +- +- soc: soc@f1000000 { +- ranges = <0x00000000 0xf1000000 0x00100000>; +- +- i2c@3000 { +- hwmon@4c { +- compatible = "dallas,max6649"; +- reg = <0x4c>; +- }; +- +- rtc@68 { +- status = "disabled"; +- }; +- }; +- +- +- enet0: ethernet@24000 { +- phy-handle = <&phy0>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@24520 { +- phy0: ethernet-phy@1 { +- reg = <1>; +- }; +- phy1: ethernet-phy@2 { +- reg = <2>; +- }; +- phy2: ethernet-phy@3 { +- reg = <3>; +- }; +- phy3: ethernet-phy@4 { +- reg = <4>; +- }; +- }; +- +- enet1: ethernet@25000 { +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@25520 { +- status = "disabled"; +- }; +- +- enet2: ethernet@26000 { +- phy-handle = <&phy2>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@26520 { +- status = "disabled"; +- }; +- +- enet3: ethernet@27000 { +- phy-handle = <&phy3>; +- phy-connection-type = "rgmii-id"; +- }; +- +- mdio@27520 { +- status = "disabled"; +- }; +- +- serial1: serial@4600 { +- status = "disabled"; +- }; +- }; +- +- lbc: localbus@f1005000 { +- reg = <0xf1005000 0x1000>; +- +- ranges = <0 0 0xf8000000 0x08000000 // NOR Flash (128MB) +- 2 0 0xf2030000 0x00010000 // NAND Flash (8GB) +- 3 0 0xf2400000 0x00080000 // MRAM (512KB) +- 4 0 0xf2000000 0x00010000 // BCSR +- 5 0 0xf2010000 0x00010000>; // QUART +- +- bcsr@4,0 { +- compatible = "artesyn,mvme7100-bcsr"; +- reg = <4 0 0x10000>; +- }; +- +- serial@5,1000 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <5 0x1000 0x100>; +- clock-frequency = <1843200>; +- interrupts = <11 1 0 0>; +- }; +- +- serial@5,2000 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <5 0x2000 0x100>; +- clock-frequency = <1843200>; +- interrupts = <11 1 0 0>; +- }; +- +- serial@5,3000 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <5 0x3000 0x100>; +- clock-frequency = <1843200>; +- interrupts = <11 1 0 0>; +- }; +- +- serial@5,4000 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <5 0x4000 0x100>; +- clock-frequency = <1843200>; +- interrupts = <11 1 0 0>; +- }; +- }; +- +- pci0: pcie@f1008000 { +- status = "disabled"; +- }; +- +- pci1: pcie@f1009000 { +- status = "disabled"; +- }; +- +- chosen { +- stdout-path = &serial0; +- }; +-}; +- +-/include/ "mpc8641si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/oca4080.dts b/scripts/dtc/include-prefixes/powerpc/fsl/oca4080.dts +deleted file mode 100644 +index 17bc6f391248..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/oca4080.dts ++++ /dev/null +@@ -1,145 +0,0 @@ +-/* +- * OCA4080 Device Tree Source +- * +- * Copyright 2014 Prodrive Technologies B.V. +- * +- * Based on: +- * P4080DS Device Tree Source +- * Copyright 2009-2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p4080si-pre.dtsi" +- +-/ { +- model = "fsl,OCA4080"; +- compatible = "fsl,OCA4080"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- memory { +- device_type = "memory"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01008000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x200000>; +- }; +- +- qportals: qman-portals@ff4200000 { +- ranges = <0x0 0xf 0xf4200000 0x200000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- +- i2c@118000 { +- status = "disabled"; +- }; +- +- i2c@118100 { +- status = "disabled"; +- }; +- +- i2c@119000 { +- status = "disabled"; +- }; +- +- i2c@119100 { +- status = "disabled"; +- }; +- +- usb0: usb@210000 { +- status = "disabled"; +- }; +- +- usb1: usb@211000 { +- status = "disabled"; +- }; +- }; +- +- rio: rapidio@ffe0c0000 { +- reg = <0xf 0xfe0c0000 0 0x11000>; +- +- port1 { +- ranges = <0 0 0xc 0x20000000 0 0x10000000>; +- }; +- }; +- +- lbc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x1000>; +- ranges = <0 0 0xf 0xef800000 0x800000>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x00800000>; +- bank-width = <2>; +- device-width = <2>; +- }; +- }; +- +- pci0: pcie@ffe200000 { +- status = "disabled"; +- }; +- +- pci1: pcie@ffe201000 { +- status = "disabled"; +- }; +- +- pci2: pcie@ffe202000 { +- status = "disabled"; +- }; +-}; +- +-/include/ "p4080si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb-pa.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb-pa.dts +deleted file mode 100644 +index 1e33d78d8c0b..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb-pa.dts ++++ /dev/null +@@ -1,19 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * P1010 RDB Device Tree Source +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- */ +- +-/include/ "p1010si-pre.dtsi" +- +-/ { +- model = "fsl,P1010RDB"; +- compatible = "fsl,P1010RDB"; +- +- /include/ "p1010rdb_32b.dtsi" +-}; +- +-/include/ "p1010rdb.dtsi" +-/include/ "p1010rdb-pa.dtsi" +-/include/ "p1010si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb-pa.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb-pa.dtsi +deleted file mode 100644 +index 434fb2d58575..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb-pa.dtsi ++++ /dev/null +@@ -1,85 +0,0 @@ +-/* +- * P1010 RDB Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&ifc_nand { +- partition@0 { +- /* This location must not be altered */ +- /* 1MB for u-boot Bootloader Image */ +- reg = <0x0 0x00100000>; +- label = "NAND U-Boot Image"; +- read-only; +- }; +- +- partition@100000 { +- /* 1MB for DTB Image */ +- reg = <0x00100000 0x00100000>; +- label = "NAND DTB Image"; +- }; +- +- partition@200000 { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00200000 0x00400000>; +- label = "NAND Linux Kernel Image"; +- }; +- +- partition@600000 { +- /* 4MB for Compressed Root file System Image */ +- reg = <0x00600000 0x00400000>; +- label = "NAND Compressed RFS Image"; +- }; +- +- partition@a00000 { +- /* 15MB for JFFS2 based Root file System */ +- reg = <0x00a00000 0x00f00000>; +- label = "NAND JFFS2 Root File System"; +- }; +- +- partition@1900000 { +- /* 7MB for User Area */ +- reg = <0x01900000 0x00700000>; +- label = "NAND User area"; +- }; +-}; +- +-&phy0 { +- interrupts = <1 1 0 0>; +-}; +- +-&phy1 { +- interrupts = <2 1 0 0>; +-}; +- +-&phy2 { +- interrupts = <4 1 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb-pa_36b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb-pa_36b.dts +deleted file mode 100644 +index 03bd76ca8406..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb-pa_36b.dts ++++ /dev/null +@@ -1,46 +0,0 @@ +-/* +- * P1010 RDB Device Tree Source (36-bit address map) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1010si-pre.dtsi" +- +-/ { +- model = "fsl,P1010RDB"; +- compatible = "fsl,P1010RDB"; +- +- /include/ "p1010rdb_36b.dtsi" +-}; +- +-/include/ "p1010rdb.dtsi" +-/include/ "p1010rdb-pa.dtsi" +-/include/ "p1010si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb-pb.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb-pb.dts +deleted file mode 100644 +index 3a94acbb3c03..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb-pb.dts ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * P1010 RDB Device Tree Source +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- */ +- +-/include/ "p1010si-pre.dtsi" +- +-/ { +- model = "fsl,P1010RDB-PB"; +- compatible = "fsl,P1010RDB-PB"; +- +- /include/ "p1010rdb_32b.dtsi" +-}; +- +-/include/ "p1010rdb.dtsi" +- +-&phy0 { +- interrupts = <0 1 0 0>; +-}; +- +-&phy1 { +- interrupts = <2 1 0 0>; +-}; +- +-&phy2 { +- interrupts = <1 1 0 0>; +-}; +- +-/include/ "p1010si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb-pb_36b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb-pb_36b.dts +deleted file mode 100644 +index 4cf255fedc96..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb-pb_36b.dts ++++ /dev/null +@@ -1,58 +0,0 @@ +-/* +- * P1010 RDB Device Tree Source (36-bit address map) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1010si-pre.dtsi" +- +-/ { +- model = "fsl,P1010RDB-PB"; +- compatible = "fsl,P1010RDB-PB"; +- +- /include/ "p1010rdb_36b.dtsi" +-}; +- +-/include/ "p1010rdb.dtsi" +- +-&phy0 { +- interrupts = <0 1 0 0>; +-}; +- +-&phy1 { +- interrupts = <2 1 0 0>; +-}; +- +-&phy2 { +- interrupts = <1 1 0 0>; +-}; +- +-/include/ "p1010si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb.dtsi +deleted file mode 100644 +index 2ca9cee2ddeb..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb.dtsi ++++ /dev/null +@@ -1,233 +0,0 @@ +-/* +- * P1010 RDB Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&board_ifc { +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x2000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@40000 { +- /* 256KB for DTB Image */ +- reg = <0x00040000 0x00040000>; +- label = "NOR DTB Image"; +- }; +- +- partition@80000 { +- /* 7 MB for Linux Kernel Image */ +- reg = <0x00080000 0x00700000>; +- label = "NOR Linux Kernel Image"; +- }; +- +- partition@800000 { +- /* 20MB for JFFS2 based Root file System */ +- reg = <0x00800000 0x01400000>; +- label = "NOR JFFS2 Root File System"; +- }; +- +- partition@1f00000 { +- /* This location must not be altered */ +- /* 512KB for u-boot Bootloader Image */ +- /* 512KB for u-boot Environment Variables */ +- reg = <0x01f00000 0x00100000>; +- label = "NOR U-Boot Image"; +- read-only; +- }; +- }; +- +- ifc_nand: nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,ifc-nand"; +- reg = <0x1 0x0 0x10000>; +- }; +- +- cpld@3,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,p1010rdb-cpld"; +- reg = <0x3 0x0 0x0000020>; +- bank-width = <1>; +- device-width = <1>; +- }; +-}; +- +-&board_soc { +- i2c@3000 { +- eeprom@50 { +- compatible = "st,24c256", "atmel,24c256"; +- reg = <0x50>; +- }; +- +- rtc@68 { +- compatible = "pericom,pt7c4338"; +- reg = <0x68>; +- }; +- }; +- +- i2c@3100 { +- eeprom@52 { +- compatible = "atmel,24c01"; +- reg = <0x52>; +- }; +- }; +- +- spi@7000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; +- +- partition@0 { +- /* 1MB for u-boot Bootloader Image */ +- /* 1MB for Environment */ +- reg = <0x0 0x00100000>; +- label = "SPI Flash U-Boot Image"; +- read-only; +- }; +- +- partition@100000 { +- /* 512KB for DTB Image */ +- reg = <0x00100000 0x00080000>; +- label = "SPI Flash DTB Image"; +- }; +- +- partition@180000 { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00180000 0x00400000>; +- label = "SPI Flash Linux Kernel Image"; +- }; +- +- partition@580000 { +- /* 4MB for Compressed RFS Image */ +- reg = <0x00580000 0x00400000>; +- label = "SPI Flash Compressed RFSImage"; +- }; +- +- partition@980000 { +- /* 6.5MB for JFFS2 based RFS */ +- reg = <0x00980000 0x00680000>; +- label = "SPI Flash JFFS2 RFS"; +- }; +- }; +- }; +- +- usb@22000 { +- phy_type = "utmi"; +- dr_mode = "host"; +- }; +- +- mdio@24000 { +- phy0: ethernet-phy@0 { +- reg = <0x1>; +- }; +- +- phy1: ethernet-phy@1 { +- reg = <0x0>; +- }; +- +- phy2: ethernet-phy@2 { +- reg = <0x2>; +- }; +- +- tbi-phy@3 { +- device_type = "tbi-phy"; +- reg = <0x3>; +- }; +- }; +- +- mdio@25000 { +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- mdio@26000 { +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- ptp_clock@b0e00 { +- compatible = "fsl,etsec-ptp"; +- reg = <0xb0e00 0xb0>; +- interrupts = <68 2 0 0 69 2 0 0>; +- fsl,tclk-period = <10>; +- fsl,tmr-prsc = <2>; +- fsl,tmr-add = <0x80000016>; +- fsl,tmr-fiper1 = <999999990>; +- fsl,tmr-fiper2 = <99990>; +- fsl,max-adj = <199999999>; +- }; +- +- enet0: ethernet@b0000 { +- phy-handle = <&phy0>; +- phy-connection-type = "rgmii-id"; +- }; +- +- enet1: ethernet@b1000 { +- phy-handle = <&phy1>; +- tbi-handle = <&tbi0>; +- phy-connection-type = "sgmii"; +- }; +- +- enet2: ethernet@b2000 { +- phy-handle = <&phy2>; +- tbi-handle = <&tbi1>; +- phy-connection-type = "sgmii"; +- }; +-}; +- +-&pci0 { +- pcie@0 { +- interrupt-map = < +- /* IDSEL 0x0 */ +- /* +- *irq[4:5] are active-high +- *irq[6:7] are active-low +- */ +- 0000 0x0 0x0 0x1 &mpic 0x4 0x2 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x5 0x2 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb_32b.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb_32b.dtsi +deleted file mode 100644 +index fdc19aab2f70..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb_32b.dtsi ++++ /dev/null +@@ -1,79 +0,0 @@ +-/* +- * P1010 RDB Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-memory { +- device_type = "memory"; +-}; +- +-board_ifc: ifc: ifc@ffe1e000 { +- /* NOR, NAND Flashes and CPLD on board */ +- ranges = <0x0 0x0 0x0 0xee000000 0x02000000 +- 0x1 0x0 0x0 0xff800000 0x00010000 +- 0x3 0x0 0x0 0xffb00000 0x00000020>; +- reg = <0x0 0xffe1e000 0 0x2000>; +-}; +- +-board_soc: soc: soc@ffe00000 { +- ranges = <0x0 0x0 0xffe00000 0x100000>; +-}; +- +-pci0: pcie@ffe09000 { +- reg = <0 0xffe09000 0 0x1000>; +- ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +-}; +- +-pci1: pcie@ffe0a000 { +- reg = <0 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb_36b.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb_36b.dtsi +deleted file mode 100644 +index de2fceed4f79..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb_36b.dtsi ++++ /dev/null +@@ -1,79 +0,0 @@ +-/* +- * P1010 RDB Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-memory { +- device_type = "memory"; +-}; +- +-board_ifc: ifc: ifc@fffe1e000 { +- /* NOR, NAND Flashes and CPLD on board */ +- ranges = <0x0 0x0 0xf 0xee000000 0x02000000 +- 0x1 0x0 0xf 0xff800000 0x00010000 +- 0x3 0x0 0xf 0xffb00000 0x00000020>; +- reg = <0xf 0xffe1e000 0 0x2000>; +-}; +- +-board_soc: soc: soc@fffe00000 { +- ranges = <0x0 0xf 0xffe00000 0x100000>; +-}; +- +-pci0: pcie@fffe09000 { +- reg = <0xf 0xffe09000 0 0x1000>; +- ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xc0000000 +- 0x2000000 0x0 0xc0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +-}; +- +-pci1: pcie@fffe0a000 { +- reg = <0xf 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xc0000000 +- 0x2000000 0x0 0xc0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1010si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1010si-post.dtsi +deleted file mode 100644 +index ccda0a91abf0..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1010si-post.dtsi ++++ /dev/null +@@ -1,191 +0,0 @@ +-/* +- * P1010/P1014 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&ifc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,ifc", "simple-bus"; +- interrupts = <16 2 0 0 19 2 0 0>; +-}; +- +-/* controller at 0x9000 */ +-&pci0 { +- compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <16 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 +- >; +- }; +-}; +- +-/* controller at 0xa000 */ +-&pci1 { +- compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <16 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 +- >; +- }; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,p1010-immr", "simple-bus"; +- bus-frequency = <0>; // Filled out by uboot. +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <12>; +- }; +- +- ecm@1000 { +- compatible = "fsl,p1010-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <16 2 0 0>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,p1010-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-i2c-0.dtsi" +- i2c@3000 { +- fsl,i2c-erratum-a004447; +- }; +- +-/include/ "pq3-i2c-1.dtsi" +- i2c@3100 { +- fsl,i2c-erratum-a004447; +- }; +- +-/include/ "pq3-duart-0.dtsi" +-/include/ "pq3-espi-0.dtsi" +- spi0: spi@7000 { +- fsl,espi-num-chipselects = <1>; +- }; +- +-/include/ "pq3-gpio-0.dtsi" +-/include/ "pq3-sata2-0.dtsi" +-/include/ "pq3-sata2-1.dtsi" +- +- can0: can@1c000 { +- compatible = "fsl,p1010-flexcan"; +- reg = <0x1c000 0x1000>; +- interrupts = <48 0x2 0 0>; +- big-endian; +- }; +- +- can1: can@1d000 { +- compatible = "fsl,p1010-flexcan"; +- reg = <0x1d000 0x1000>; +- interrupts = <61 0x2 0 0>; +- big-endian; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,p1010-l2-cache-controller", +- "fsl,p1014-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x40000>; // L2,256K +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-dma-0.dtsi" +-/include/ "pq3-usb2-dr-0.dtsi" +- usb@22000 { +- compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; +- }; +-/include/ "pq3-esdhc-0.dtsi" +- sdhc@2e000 { +- compatible = "fsl,p1010-esdhc", "fsl,esdhc"; +- sdhci,auto-cmd12; +- }; +- +-/include/ "pq3-sec4.4-0.dtsi" +-/include/ "pq3-mpic.dtsi" +-/include/ "pq3-mpic-timer-B.dtsi" +- +-/include/ "pq3-etsec2-0.dtsi" +-/include/ "pq3-etsec2-1.dtsi" +-/include/ "pq3-etsec2-2.dtsi" +- +- global-utilities@e0000 { +- compatible = "fsl,p1010-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1010si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1010si-pre.dtsi +deleted file mode 100644 +index 6e76f9b282a1..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1010si-pre.dtsi ++++ /dev/null +@@ -1,67 +0,0 @@ +-/* +- * P1010/P1014 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e500v2_power_isa.dtsi" +- +-/ { +- compatible = "fsl,P1010"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- pci0 = &pci0; +- pci1 = &pci1; +- can0 = &can0; +- can1 = &can1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,P1010@0 { +- device_type = "cpu"; +- reg = <0x0>; +- next-level-cache = <&L2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1020mbg-pc.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1020mbg-pc.dtsi +deleted file mode 100644 +index a24699cfea9c..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1020mbg-pc.dtsi ++++ /dev/null +@@ -1,151 +0,0 @@ +-/* +- * P1020 MBG-PC Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&lbc { +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x4000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- /* 128KB for DTB Image */ +- reg = <0x0 0x00020000>; +- label = "NOR DTB Image"; +- }; +- +- partition@20000 { +- /* 3.875 MB for Linux Kernel Image */ +- reg = <0x00020000 0x003e0000>; +- label = "NOR Linux Kernel Image"; +- }; +- +- partition@400000 { +- /* 58MB for Root file System */ +- reg = <0x00400000 0x03a00000>; +- label = "NOR Root File System"; +- }; +- +- partition@3e00000 { +- /* This location must not be altered */ +- /* 1M for Vitesse 7385 Switch firmware */ +- reg = <0x3e00000 0x00100000>; +- label = "NOR Vitesse-7385 Firmware"; +- read-only; +- }; +- +- partition@3f00000 { +- /* This location must not be altered */ +- /* 512KB for u-boot Bootloader Image */ +- /* 512KB for u-boot Environment Variables */ +- reg = <0x03f00000 0x00100000>; +- label = "NOR U-Boot Image"; +- read-only; +- }; +- }; +- +- L2switch@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "vitesse-7385"; +- reg = <0x2 0x0 0x20000>; +- }; +-}; +- +-&soc { +- i2c@3000 { +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +- }; +- +- mdio@24000 { +- phy0: ethernet-phy@0 { +- interrupts = <3 1 0 0>; +- reg = <0x0>; +- }; +- phy1: ethernet-phy@1 { +- interrupts = <2 1 0 0>; +- reg = <0x1>; +- }; +- }; +- +- mdio@25000 { +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- mdio@26000 { +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet0: ethernet@b0000 { +- fixed-link = <1 1 1000 0 0>; +- phy-connection-type = "rgmii-id"; +- }; +- +- enet1: ethernet@b1000 { +- phy-handle = <&phy0>; +- tbi-handle = <&tbi1>; +- phy-connection-type = "sgmii"; +- }; +- +- enet2: ethernet@b2000 { +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +- +- usb@22000 { +- phy_type = "ulpi"; +- }; +- +- /* USB2 is shared with localbus, so it must be disabled +- by default. We can't put 'status = "disabled";' here +- since U-Boot doesn't clear the status property when +- it enables USB2. OTOH, U-Boot does create a new node +- when there isn't any. So, just comment it out. +- */ +- usb@23000 { +- status = "disabled"; +- phy_type = "ulpi"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1020mbg-pc_32b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1020mbg-pc_32b.dts +deleted file mode 100644 +index b29d1fcb5e6b..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1020mbg-pc_32b.dts ++++ /dev/null +@@ -1,89 +0,0 @@ +-/* +- * P1020 MBG-PC Device Tree Source (32-bit address map) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1020si-pre.dtsi" +-/ { +- model = "fsl,P1020MBG-PC"; +- compatible = "fsl,P1020MBG-PC"; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@ffe05000 { +- reg = <0x0 0xffe05000 0x0 0x1000>; +- +- /* NOR and L2 switch */ +- ranges = <0x0 0x0 0x0 0xec000000 0x04000000 +- 0x1 0x0 0x0 0xffa00000 0x00040000 +- 0x2 0x0 0x0 0xffb00000 0x00020000>; +- }; +- +- soc: soc@ffe00000 { +- ranges = <0x0 0x0 0xffe00000 0x100000>; +- }; +- +- pci0: pcie@ffe09000 { +- reg = <0x0 0xffe09000 0x0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@ffe0a000 { +- reg = <0x0 0xffe0a000 0x0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0x0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/include/ "p1020mbg-pc.dtsi" +-/include/ "p1020si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1020mbg-pc_36b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1020mbg-pc_36b.dts +deleted file mode 100644 +index 678d0eec24e2..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1020mbg-pc_36b.dts ++++ /dev/null +@@ -1,89 +0,0 @@ +-/* +- * P1020 MBG-PC Device Tree Source (36-bit address map) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1020si-pre.dtsi" +-/ { +- model = "fsl,P1020MBG-PC"; +- compatible = "fsl,P1020MBG-PC"; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@fffe05000 { +- reg = <0xf 0xffe05000 0x0 0x1000>; +- +- /* NOR and L2 switch */ +- ranges = <0x0 0x0 0xf 0xec000000 0x04000000 +- 0x1 0x0 0xf 0xffa00000 0x00040000 +- 0x2 0x0 0xf 0xffb00000 0x00020000>; +- }; +- +- soc: soc@fffe00000 { +- ranges = <0x0 0xf 0xffe00000 0x100000>; +- }; +- +- pci0: pcie@fffe09000 { +- reg = <0xf 0xffe09000 0x0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@fffe0a000 { +- reg = <0xf 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/include/ "p1020mbg-pc.dtsi" +-/include/ "p1020si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb-pc.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb-pc.dtsi +deleted file mode 100644 +index a13876c05c1e..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb-pc.dtsi ++++ /dev/null +@@ -1,247 +0,0 @@ +-/* +- * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&lbc { +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x1000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 256KB for Vitesse 7385 Switch firmware */ +- reg = <0x0 0x00040000>; +- label = "NOR Vitesse-7385 Firmware"; +- read-only; +- }; +- +- partition@40000 { +- /* 256KB for DTB Image */ +- reg = <0x00040000 0x00040000>; +- label = "NOR DTB Image"; +- }; +- +- partition@80000 { +- /* 3.5 MB for Linux Kernel Image */ +- reg = <0x00080000 0x00380000>; +- label = "NOR Linux Kernel Image"; +- }; +- +- partition@400000 { +- /* 11MB for JFFS2 based Root file System */ +- reg = <0x00400000 0x00b00000>; +- label = "NOR JFFS2 Root File System"; +- }; +- +- partition@f00000 { +- /* This location must not be altered */ +- /* 512KB for u-boot Bootloader Image */ +- /* 512KB for u-boot Environment Variables */ +- reg = <0x00f00000 0x00100000>; +- label = "NOR U-Boot Image"; +- read-only; +- }; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,p1020-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x1 0x0 0x40000>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 1MB for u-boot Bootloader Image */ +- reg = <0x0 0x00100000>; +- label = "NAND U-Boot Image"; +- read-only; +- }; +- +- partition@100000 { +- /* 1MB for DTB Image */ +- reg = <0x00100000 0x00100000>; +- label = "NAND DTB Image"; +- }; +- +- partition@200000 { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00200000 0x00400000>; +- label = "NAND Linux Kernel Image"; +- }; +- +- partition@600000 { +- /* 4MB for Compressed Root file System Image */ +- reg = <0x00600000 0x00400000>; +- label = "NAND Compressed RFS Image"; +- }; +- +- partition@a00000 { +- /* 7MB for JFFS2 based Root file System */ +- reg = <0x00a00000 0x00700000>; +- label = "NAND JFFS2 Root File System"; +- }; +- +- partition@1100000 { +- /* 15MB for JFFS2 based Root file System */ +- reg = <0x01100000 0x00f00000>; +- label = "NAND Writable User area"; +- }; +- }; +- +- L2switch@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "vitesse-7385"; +- reg = <0x2 0x0 0x20000>; +- }; +- +- cpld@3,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cpld"; +- reg = <0x3 0x0 0x20000>; +- read-only; +- }; +-}; +- +-&soc { +- i2c@3000 { +- rtc@68 { +- compatible = "pericom,pt7c4338"; +- reg = <0x68>; +- }; +- }; +- +- spi@7000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; /* input clock */ +- +- partition@u-boot { +- /* 512KB for u-boot Bootloader Image */ +- reg = <0x0 0x00080000>; +- label = "u-boot"; +- read-only; +- }; +- +- partition@dtb { +- /* 512KB for DTB Image*/ +- reg = <0x00080000 0x00080000>; +- label = "dtb"; +- }; +- +- partition@kernel { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00100000 0x00400000>; +- label = "kernel"; +- }; +- +- partition@fs { +- /* 4MB for Compressed RFS Image */ +- reg = <0x00500000 0x00400000>; +- label = "file system"; +- }; +- +- partition@jffs-fs { +- /* 7MB for JFFS2 based RFS */ +- reg = <0x00900000 0x00700000>; +- label = "file system jffs2"; +- }; +- }; +- }; +- +- usb@22000 { +- phy_type = "ulpi"; +- }; +- +- /* USB2 is shared with localbus, so it must be disabled +- by default. We can't put 'status = "disabled";' here +- since U-Boot doesn't clear the status property when +- it enables USB2. OTOH, U-Boot does create a new node +- when there isn't any. So, just comment it out. +- usb@23000 { +- phy_type = "ulpi"; +- }; +- */ +- +- mdio@24000 { +- phy0: ethernet-phy@0 { +- interrupt-parent = <&mpic>; +- interrupts = <3 1 0 0>; +- reg = <0x0>; +- }; +- +- phy1: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <2 1 0 0>; +- reg = <0x1>; +- }; +- +- tbi0: tbi-phy@11 { +- device_type = "tbi-phy"; +- reg = <0x11>; +- }; +- }; +- +- mdio@25000 { +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet0: ethernet@b0000 { +- fixed-link = <1 1 1000 0 0>; +- phy-connection-type = "rgmii-id"; +- +- }; +- +- enet1: ethernet@b1000 { +- phy-handle = <&phy0>; +- tbi-handle = <&tbi1>; +- phy-connection-type = "sgmii"; +- }; +- +- enet2: ethernet@b2000 { +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb-pc_32b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb-pc_32b.dts +deleted file mode 100644 +index 8175bf6f3e9c..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb-pc_32b.dts ++++ /dev/null +@@ -1,90 +0,0 @@ +-/* +- * P1020 RDB-PC Device Tree Source (32-bit address map) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1020si-pre.dtsi" +-/ { +- model = "fsl,P1020RDB-PC"; +- compatible = "fsl,P1020RDB-PC"; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@ffe05000 { +- reg = <0 0xffe05000 0 0x1000>; +- +- /* NOR, NAND Flashes and Vitesse 5 port L2 switch */ +- ranges = <0x0 0x0 0x0 0xef000000 0x01000000 +- 0x1 0x0 0x0 0xff800000 0x00040000 +- 0x2 0x0 0x0 0xffb00000 0x00020000 +- 0x3 0x0 0x0 0xffa00000 0x00020000>; +- }; +- +- soc: soc@ffe00000 { +- ranges = <0x0 0x0 0xffe00000 0x100000>; +- }; +- +- pci0: pcie@ffe09000 { +- ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; +- reg = <0 0xffe09000 0 0x1000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@ffe0a000 { +- reg = <0 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/include/ "p1020rdb-pc.dtsi" +-/include/ "p1020si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb-pc_36b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb-pc_36b.dts +deleted file mode 100644 +index 01c305795163..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb-pc_36b.dts ++++ /dev/null +@@ -1,90 +0,0 @@ +-/* +- * P1020 RDB-PC Device Tree Source (36-bit address map) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1020si-pre.dtsi" +-/ { +- model = "fsl,P1020RDB-PC"; +- compatible = "fsl,P1020RDB-PC"; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@fffe05000 { +- reg = <0xf 0xffe05000 0 0x1000>; +- +- /* NOR, NAND Flashes and Vitesse 5 port L2 switch */ +- ranges = <0x0 0x0 0xf 0xef000000 0x01000000 +- 0x1 0x0 0xf 0xff800000 0x00040000 +- 0x2 0x0 0xf 0xffb00000 0x00040000 +- 0x3 0x0 0xf 0xffa00000 0x00020000>; +- }; +- +- soc: soc@fffe00000 { +- ranges = <0x0 0xf 0xffe00000 0x100000>; +- }; +- +- pci0: pcie@fffe09000 { +- reg = <0xf 0xffe09000 0 0x1000>; +- ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xc0000000 +- 0x2000000 0x0 0xc0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@fffe0a000 { +- reg = <0xf 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/include/ "p1020rdb-pc.dtsi" +-/include/ "p1020si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb-pc_camp_core0.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb-pc_camp_core0.dts +deleted file mode 100644 +index 42e1e2fc0892..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb-pc_camp_core0.dts ++++ /dev/null +@@ -1,60 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * P1020 RDB-PC Core0 Device Tree Source in CAMP mode. +- * +- * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache +- * can be shared, all the other devices must be assigned to one core only. +- * This dts file allows core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb, +- * eth1, eth2, sdhc, crypto, global-util, message, pci0, pci1, msi. +- * +- * Please note to add "-b 0" for core0's dts compiling. +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- */ +- +-/include/ "p1020rdb-pc_32b.dts" +- +-/ { +- model = "fsl,P1020RDB-PC"; +- compatible = "fsl,P1020RDB-PC"; +- +- aliases { +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- serial0 = &serial0; +- pci0 = &pci0; +- pci1 = &pci1; +- }; +- +- cpus { +- PowerPC,P1020@1 { +- status = "disabled"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- localbus@ffe05000 { +- status = "disabled"; +- }; +- +- soc@ffe00000 { +- serial1: serial@4600 { +- status = "disabled"; +- }; +- +- enet0: ethernet@b0000 { +- status = "disabled"; +- }; +- +- mpic: pic@40000 { +- protected-sources = < +- 42 29 30 34 /* serial1, enet0-queue-group0 */ +- 17 18 24 45 /* enet0-queue-group1, crypto */ +- >; +- pic-no-reset; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb-pc_camp_core1.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb-pc_camp_core1.dts +deleted file mode 100644 +index da9a8e73b3e2..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb-pc_camp_core1.dts ++++ /dev/null +@@ -1,138 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * P1020 RDB-PC Core1 Device Tree Source in CAMP mode. +- * +- * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache +- * can be shared, all the other devices must be assigned to one core only. +- * This dts allows core1 to have l2, eth0, crypto. +- * +- * Please note to add "-b 1" for core1's dts compiling. +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- */ +- +-/include/ "p1020rdb-pc_32b.dts" +- +-/ { +- model = "fsl,P1020RDB-PC"; +- compatible = "fsl,P1020RDB-PC"; +- +- aliases { +- ethernet0 = &enet0; +- serial0 = &serial1; +- }; +- +- cpus { +- PowerPC,P1020@0 { +- status = "disabled"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- localbus@ffe05000 { +- status = "disabled"; +- }; +- +- soc@ffe00000 { +- ecm-law@0 { +- status = "disabled"; +- }; +- +- ecm@1000 { +- status = "disabled"; +- }; +- +- memory-controller@2000 { +- status = "disabled"; +- }; +- +- i2c@3000 { +- status = "disabled"; +- }; +- +- i2c@3100 { +- status = "disabled"; +- }; +- +- serial0: serial@4500 { +- status = "disabled"; +- }; +- +- spi@7000 { +- status = "disabled"; +- }; +- +- gpio: gpio-controller@f000 { +- status = "disabled"; +- }; +- +- dma@21300 { +- status = "disabled"; +- }; +- +- mdio@24000 { +- status = "disabled"; +- }; +- +- mdio@25000 { +- status = "disabled"; +- }; +- +- enet1: ethernet@b1000 { +- status = "disabled"; +- }; +- +- enet2: ethernet@b2000 { +- status = "disabled"; +- }; +- +- usb@22000 { +- status = "disabled"; +- }; +- +- sdhci@2e000 { +- status = "disabled"; +- }; +- +- mpic: pic@40000 { +- protected-sources = < +- 16 /* ecm, mem, L2, pci0, pci1 */ +- 43 42 59 /* i2c, serial0, spi */ +- 47 63 62 /* gpio, tdm */ +- 20 21 22 23 /* dma */ +- 03 02 /* mdio */ +- 35 36 40 /* enet1-queue-group0 */ +- 51 52 67 /* enet1-queue-group1 */ +- 31 32 33 /* enet2-queue-group0 */ +- 25 26 27 /* enet2-queue-group1 */ +- 28 72 58 /* usb, sdhci, crypto */ +- 0xb0 0xb1 0xb2 /* message */ +- 0xb3 0xb4 0xb5 +- 0xb6 0xb7 +- 0xe0 0xe1 0xe2 /* msi */ +- 0xe3 0xe4 0xe5 +- 0xe6 0xe7 /* sdhci, crypto , pci */ +- >; +- pic-no-reset; +- }; +- +- msi@41600 { +- status = "disabled"; +- }; +- +- global-utilities@e0000 { //global utilities block +- status = "disabled"; +- }; +- }; +- +- pci0: pcie@ffe09000 { +- status = "disabled"; +- }; +- +- pci1: pcie@ffe0a000 { +- status = "disabled"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb-pd.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb-pd.dts +deleted file mode 100644 +index f2dc6c09be52..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb-pd.dts ++++ /dev/null +@@ -1,292 +0,0 @@ +-/* +- * P1020 RDB-PD Device Tree Source (32-bit address map) +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1020si-pre.dtsi" +-/ { +- model = "fsl,P1020RDB-PD"; +- compatible = "fsl,P1020RDB-PD"; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@ffe05000 { +- reg = <0x0 0xffe05000 0x0 0x1000>; +- +- /* NOR, NAND flash, L2 switch and CPLD */ +- ranges = <0x0 0x0 0x0 0xec000000 0x04000000 +- 0x1 0x0 0x0 0xff800000 0x00040000 +- 0x2 0x0 0x0 0xffa00000 0x00020000 +- 0x3 0x0 0x0 0xffb00000 0x00020000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x4000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- /* 128KB for DTB Image */ +- reg = <0x0 0x00020000>; +- label = "NOR DTB Image"; +- }; +- +- partition@20000 { +- /* 3.875 MB for Linux Kernel Image */ +- reg = <0x00020000 0x003e0000>; +- label = "NOR Linux Kernel Image"; +- }; +- +- partition@400000 { +- /* 58MB for Root file System */ +- reg = <0x00400000 0x03a00000>; +- label = "NOR Root File System"; +- }; +- +- partition@3e00000 { +- /* This location must not be altered */ +- /* 1M for Vitesse 7385 Switch firmware */ +- reg = <0x3e00000 0x00100000>; +- label = "NOR Vitesse-7385 Firmware"; +- read-only; +- }; +- +- partition@3f00000 { +- /* This location must not be altered */ +- /* 512KB for u-boot Bootloader Image */ +- /* 512KB for u-boot Environment Variables */ +- reg = <0x03f00000 0x00100000>; +- label = "NOR U-Boot Image"; +- read-only; +- }; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,p1020-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x1 0x0 0x40000>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 1MB for u-boot Bootloader Image */ +- reg = <0x0 0x00100000>; +- label = "NAND U-Boot Image"; +- read-only; +- }; +- +- partition@100000 { +- /* 1MB for DTB Image */ +- reg = <0x00100000 0x00100000>; +- label = "NAND DTB Image"; +- }; +- +- partition@200000 { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00200000 0x00400000>; +- label = "NAND Linux Kernel Image"; +- }; +- +- partition@600000 { +- /* 122MB for File System Image */ +- reg = <0x00600000 0x07a00000>; +- label = "NAND File System Image"; +- }; +- }; +- +- cpld@2,0 { +- compatible = "fsl,p1020rdb-pd-cpld"; +- reg = <0x2 0x0 0x20000>; +- }; +- +- L2switch@3,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "vitesse-7385"; +- reg = <0x3 0x0 0x20000>; +- }; +- }; +- +- soc: soc@ffe00000 { +- ranges = <0x0 0x0 0xffe00000 0x100000>; +- +- i2c@3000 { +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +- }; +- +- spi@7000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <0>; +- /* input clock */ +- spi-max-frequency = <40000000>; +- +- partition@0 { +- /* 512KB for u-boot Bootloader Image */ +- reg = <0x0 0x00080000>; +- label = "SPI U-Boot Image"; +- read-only; +- }; +- +- partition@80000 { +- /* 512KB for DTB Image*/ +- reg = <0x00080000 0x00080000>; +- label = "SPI DTB Image"; +- }; +- +- partition@100000 { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00100000 0x00400000>; +- label = "SPI Linux Kernel Image"; +- }; +- +- partition@500000 { +- /* 11MB for FS System Image */ +- reg = <0x00500000 0x00b00000>; +- label = "SPI File System Image"; +- }; +- }; +- +- slic@0 { +- compatible = "zarlink,le88266"; +- reg = <1>; +- spi-max-frequency = <8000000>; +- }; +- +- slic@1 { +- compatible = "zarlink,le88266"; +- reg = <2>; +- spi-max-frequency = <8000000>; +- }; +- }; +- +- mdio@24000 { +- phy0: ethernet-phy@0 { +- interrupts = <3 1 0 0>; +- reg = <0x0>; +- }; +- +- phy1: ethernet-phy@1 { +- interrupts = <2 1 0 0>; +- reg = <0x1>; +- }; +- }; +- +- mdio@25000 { +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- mdio@26000 { +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- ptp_clock@b0e00 { +- compatible = "fsl,etsec-ptp"; +- reg = <0xb0e00 0xb0>; +- interrupts = <68 2 0 0 69 2 0 0>; +- fsl,tclk-period = <10>; +- fsl,tmr-prsc = <2>; +- fsl,tmr-add = <0x80000016>; +- fsl,tmr-fiper1 = <999999990>; +- fsl,tmr-fiper2 = <99990>; +- fsl,max-adj = <199999999>; +- }; +- +- enet0: ethernet@b0000 { +- fixed-link = <1 1 1000 0 0>; +- phy-connection-type = "rgmii-id"; +- }; +- +- enet1: ethernet@b1000 { +- phy-handle = <&phy0>; +- tbi-handle = <&tbi1>; +- phy-connection-type = "sgmii"; +- }; +- +- enet2: ethernet@b2000 { +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +- +- usb@22000 { +- phy_type = "ulpi"; +- }; +- }; +- +- pci0: pcie@ffe09000 { +- reg = <0x0 0xffe09000 0x0 0x1000>; +- ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@ffe0a000 { +- reg = <0x0 0xffe0a000 0x0 0x1000>; +- ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/include/ "p1020si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb.dts +deleted file mode 100644 +index 1a8d81ee4168..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb.dts ++++ /dev/null +@@ -1,62 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * P1020 RDB Device Tree Source +- * +- * Copyright 2009-2011 Freescale Semiconductor Inc. +- */ +- +-/include/ "p1020si-pre.dtsi" +-/ { +- model = "fsl,P1020RDB"; +- compatible = "fsl,P1020RDB"; +- +- memory { +- device_type = "memory"; +- }; +- +- board_lbc: lbc: localbus@ffe05000 { +- reg = <0 0xffe05000 0 0x1000>; +- +- /* NOR, NAND Flashes and Vitesse 5 port L2 switch */ +- ranges = <0x0 0x0 0x0 0xef000000 0x01000000 +- 0x1 0x0 0x0 0xffa00000 0x00040000 +- 0x2 0x0 0x0 0xffb00000 0x00020000>; +- }; +- +- board_soc: soc: soc@ffe00000 { +- ranges = <0x0 0x0 0xffe00000 0x100000>; +- }; +- +- pci0: pcie@ffe09000 { +- ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; +- reg = <0 0xffe09000 0 0x1000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@ffe0a000 { +- reg = <0 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/include/ "p1020rdb.dtsi" +-/include/ "p1020si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb.dtsi +deleted file mode 100644 +index 703142ee6627..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb.dtsi ++++ /dev/null +@@ -1,246 +0,0 @@ +-/* +- * P1020 RDB Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2011-2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&board_lbc { +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x1000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 256KB for Vitesse 7385 Switch firmware */ +- reg = <0x0 0x00040000>; +- label = "NOR (RO) Vitesse-7385 Firmware"; +- read-only; +- }; +- +- partition@40000 { +- /* 256KB for DTB Image */ +- reg = <0x00040000 0x00040000>; +- label = "NOR (RO) DTB Image"; +- read-only; +- }; +- +- partition@80000 { +- /* 3.5 MB for Linux Kernel Image */ +- reg = <0x00080000 0x00380000>; +- label = "NOR (RO) Linux Kernel Image"; +- read-only; +- }; +- +- partition@400000 { +- /* 11MB for JFFS2 based Root file System */ +- reg = <0x00400000 0x00b00000>; +- label = "NOR (RW) JFFS2 Root File System"; +- }; +- +- partition@f00000 { +- /* This location must not be altered */ +- /* 512KB for u-boot Bootloader Image */ +- /* 512KB for u-boot Environment Variables */ +- reg = <0x00f00000 0x00100000>; +- label = "NOR (RO) U-Boot Image"; +- read-only; +- }; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,p1020-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x1 0x0 0x40000>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 1MB for u-boot Bootloader Image */ +- reg = <0x0 0x00100000>; +- label = "NAND (RO) U-Boot Image"; +- read-only; +- }; +- +- partition@100000 { +- /* 1MB for DTB Image */ +- reg = <0x00100000 0x00100000>; +- label = "NAND (RO) DTB Image"; +- read-only; +- }; +- +- partition@200000 { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00200000 0x00400000>; +- label = "NAND (RO) Linux Kernel Image"; +- read-only; +- }; +- +- partition@600000 { +- /* 4MB for Compressed Root file System Image */ +- reg = <0x00600000 0x00400000>; +- label = "NAND (RO) Compressed RFS Image"; +- read-only; +- }; +- +- partition@a00000 { +- /* 7MB for JFFS2 based Root file System */ +- reg = <0x00a00000 0x00700000>; +- label = "NAND (RW) JFFS2 Root File System"; +- }; +- +- partition@1100000 { +- /* 15MB for JFFS2 based Root file System */ +- reg = <0x01100000 0x00f00000>; +- label = "NAND (RW) Writable User area"; +- }; +- }; +- +- L2switch@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "vitesse-7385"; +- reg = <0x2 0x0 0x20000>; +- }; +-}; +- +-&board_soc { +- i2c@3000 { +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +- }; +- +- spi@7000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; /* input clock */ +- +- partition@u-boot { +- /* 512KB for u-boot Bootloader Image */ +- reg = <0x0 0x00080000>; +- label = "u-boot"; +- read-only; +- }; +- +- partition@dtb { +- /* 512KB for DTB Image */ +- reg = <0x00080000 0x00080000>; +- label = "dtb"; +- read-only; +- }; +- +- partition@kernel { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00100000 0x00400000>; +- label = "kernel"; +- read-only; +- }; +- +- partition@fs { +- /* 4MB for Compressed RFS Image */ +- reg = <0x00500000 0x00400000>; +- label = "file system"; +- read-only; +- }; +- +- partition@jffs-fs { +- /* 7MB for JFFS2 based RFS */ +- reg = <0x00900000 0x00700000>; +- label = "file system jffs2"; +- }; +- }; +- }; +- +- usb@22000 { +- phy_type = "ulpi"; +- dr_mode = "host"; +- }; +- +- /* USB2 is shared with localbus. It is used +- only in case of SPI and SD boot after +- appropriate device-tree fixup done by uboot */ +- usb@23000 { +- phy_type = "ulpi"; +- dr_mode = "host"; +- }; +- +- mdio@24000 { +- phy0: ethernet-phy@0 { +- interrupt-parent = <&mpic>; +- interrupts = <3 1>; +- reg = <0x0>; +- }; +- +- phy1: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <2 1>; +- reg = <0x1>; +- }; +- +- tbi-phy@2 { +- device_type = "tbi-phy"; +- reg = <0x2>; +- }; +- }; +- +- mdio@25000 { +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet0: ethernet@b0000 { +- fixed-link = <1 1 1000 0 0>; +- phy-connection-type = "rgmii-id"; +- +- }; +- +- enet1: ethernet@b1000 { +- phy-handle = <&phy0>; +- tbi-handle = <&tbi0>; +- phy-connection-type = "sgmii"; +- }; +- +- enet2: ethernet@b2000 { +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb_36b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb_36b.dts +deleted file mode 100644 +index fd09a19789e5..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1020rdb_36b.dts ++++ /dev/null +@@ -1,62 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * P1020 RDB Device Tree Source (36-bit address map) +- * +- * Copyright 2009-2011 Freescale Semiconductor Inc. +- */ +- +-/include/ "p1020si-pre.dtsi" +-/ { +- model = "fsl,P1020RDB"; +- compatible = "fsl,P1020RDB"; +- +- memory { +- device_type = "memory"; +- }; +- +- board_lbc: lbc: localbus@fffe05000 { +- reg = <0xf 0xffe05000 0 0x1000>; +- +- /* NOR, NAND Flashes and Vitesse 5 port L2 switch */ +- ranges = <0x0 0x0 0xf 0xef000000 0x01000000 +- 0x1 0x0 0xf 0xffa00000 0x00040000 +- 0x2 0x0 0xf 0xffb00000 0x00020000>; +- }; +- +- board_soc: soc: soc@fffe00000 { +- ranges = <0x0 0xf 0xffe00000 0x100000>; +- }; +- +- pci0: pcie@fffe09000 { +- reg = <0xf 0xffe09000 0 0x1000>; +- ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xc0000000 +- 0x2000000 0x0 0xc0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@fffe0a000 { +- reg = <0xf 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/include/ "p1020rdb.dtsi" +-/include/ "p1020si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1020si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1020si-post.dtsi +deleted file mode 100644 +index 642dc3a83d0e..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1020si-post.dtsi ++++ /dev/null +@@ -1,185 +0,0 @@ +-/* +- * P1020/P1011 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&lbc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus"; +- interrupts = <19 2 0 0>, +- <16 2 0 0>; +-}; +- +-/* controller at 0x9000 */ +-&pci0 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <16 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 +- >; +- }; +-}; +- +-/* controller at 0xa000 */ +-&pci1 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <16 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 +- >; +- }; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,p1020-immr", "simple-bus"; +- bus-frequency = <0>; // Filled out by uboot. +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <12>; +- }; +- +- ecm@1000 { +- compatible = "fsl,p1020-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <16 2 0 0>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,p1020-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-i2c-0.dtsi" +-/include/ "pq3-i2c-1.dtsi" +-/include/ "pq3-duart-0.dtsi" +- +-/include/ "pq3-espi-0.dtsi" +- spi@7000 { +- fsl,espi-num-chipselects = <4>; +- }; +- +-/include/ "pq3-gpio-0.dtsi" +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,p1020-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x40000>; // L2,256K +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-dma-0.dtsi" +-/include/ "pq3-usb2-dr-0.dtsi" +- usb@22000 { +- compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; +- }; +-/include/ "pq3-usb2-dr-1.dtsi" +- usb@23000 { +- compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; +- }; +- +-/include/ "pq3-esdhc-0.dtsi" +- sdhc@2e000 { +- compatible = "fsl,p1020-esdhc", "fsl,esdhc"; +- sdhci,auto-cmd12; +- }; +-/include/ "pq3-sec3.3-0.dtsi" +- +-/include/ "pq3-mpic.dtsi" +-/include/ "pq3-mpic-timer-B.dtsi" +- +-/include/ "pq3-etsec2-0.dtsi" +- enet0: enet0_grp2: ethernet@b0000 { +- }; +- +-/include/ "pq3-etsec2-1.dtsi" +- enet1: enet1_grp2: ethernet@b1000 { +- }; +- +-/include/ "pq3-etsec2-2.dtsi" +- enet2: enet2_grp2: ethernet@b2000 { +- }; +- +- global-utilities@e0000 { +- compatible = "fsl,p1020-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +-}; +- +-/include/ "pq3-etsec2-grp2-0.dtsi" +-/include/ "pq3-etsec2-grp2-1.dtsi" +-/include/ "pq3-etsec2-grp2-2.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1020si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1020si-pre.dtsi +deleted file mode 100644 +index fed9c4c8d962..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1020si-pre.dtsi ++++ /dev/null +@@ -1,71 +0,0 @@ +-/* +- * P1020/P1011 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e500v2_power_isa.dtsi" +- +-/ { +- compatible = "fsl,P1020"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- pci0 = &pci0; +- pci1 = &pci1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,P1020@0 { +- device_type = "cpu"; +- reg = <0x0>; +- next-level-cache = <&L2>; +- }; +- +- PowerPC,P1020@1 { +- device_type = "cpu"; +- reg = <0x1>; +- next-level-cache = <&L2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1020utm-pc.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1020utm-pc.dtsi +deleted file mode 100644 +index 7ea85eabcc5c..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1020utm-pc.dtsi ++++ /dev/null +@@ -1,140 +0,0 @@ +-/* +- * P1020 UTM-PC Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&lbc { +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x2000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- /* 256KB for DTB Image */ +- reg = <0x0 0x00040000>; +- label = "NOR DTB Image"; +- }; +- +- partition@40000 { +- /* 3.75 MB for Linux Kernel Image */ +- reg = <0x00040000 0x003c0000>; +- label = "NOR Linux Kernel Image"; +- }; +- +- partition@400000 { +- /* 27MB for Root file System */ +- reg = <0x00400000 0x01b00000>; +- label = "NOR Root File System"; +- }; +- +- partition@1f00000 { +- /* This location must not be altered */ +- /* 512KB for u-boot Bootloader Image */ +- /* 512KB for u-boot Environment Variables */ +- reg = <0x01f00000 0x00100000>; +- label = "NOR U-Boot Image"; +- read-only; +- }; +- }; +-}; +- +-&soc { +- i2c@3000 { +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +- }; +- +- mdio@24000 { +- phy0: ethernet-phy@0 { +- interrupts = <3 1 0 0>; +- reg = <0x0>; +- }; +- phy1: ethernet-phy@1 { +- interrupts = <2 1 0 0>; +- reg = <0x1>; +- }; +- phy2: ethernet-phy@2 { +- interrupts = <1 1 0 0>; +- reg = <0x2>; +- }; +- }; +- +- mdio@25000 { +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- mdio@26000 { +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet0: ethernet@b0000 { +- phy-handle = <&phy2>; +- phy-connection-type = "rgmii-id"; +- }; +- +- enet1: ethernet@b1000 { +- phy-handle = <&phy0>; +- tbi-handle = <&tbi1>; +- phy-connection-type = "sgmii"; +- }; +- +- enet2: ethernet@b2000 { +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +- +- usb@22000 { +- phy_type = "ulpi"; +- }; +- +- /* USB2 is shared with localbus, so it must be disabled +- by default. We can't put 'status = "disabled";' here +- since U-Boot doesn't clear the status property when +- it enables USB2. OTOH, U-Boot does create a new node +- when there isn't any. So, just comment it out. +- */ +- usb@23000 { +- status = "disabled"; +- phy_type = "ulpi"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1020utm-pc_32b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1020utm-pc_32b.dts +deleted file mode 100644 +index bc03ef611f98..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1020utm-pc_32b.dts ++++ /dev/null +@@ -1,89 +0,0 @@ +-/* +- * P1020 UTM-PC Device Tree Source (32-bit address map) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1020si-pre.dtsi" +-/ { +- model = "fsl,P1020UTM-PC"; +- compatible = "fsl,P1020UTM-PC"; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@ffe05000 { +- reg = <0x0 0xffe05000 0x0 0x1000>; +- +- /* NOR */ +- ranges = <0x0 0x0 0x0 0xec000000 0x02000000 +- 0x1 0x0 0x0 0xffa00000 0x00040000 +- 0x2 0x0 0x0 0xffb00000 0x00020000>; +- }; +- +- soc: soc@ffe00000 { +- ranges = <0x0 0x0 0xffe00000 0x100000>; +- }; +- +- pci0: pcie@ffe09000 { +- reg = <0x0 0xffe09000 0x0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@ffe0a000 { +- reg = <0x0 0xffe0a000 0x0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0x0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/include/ "p1020utm-pc.dtsi" +-/include/ "p1020si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1020utm-pc_36b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1020utm-pc_36b.dts +deleted file mode 100644 +index 32766f6a475e..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1020utm-pc_36b.dts ++++ /dev/null +@@ -1,89 +0,0 @@ +-/* +- * P1020 UTM-PC Device Tree Source (36-bit address map) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1020si-pre.dtsi" +-/ { +- model = "fsl,P1020UTM-PC"; +- compatible = "fsl,P1020UTM-PC"; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@fffe05000 { +- reg = <0xf 0xffe05000 0x0 0x1000>; +- +- /* NOR */ +- ranges = <0x0 0x0 0xf 0xec000000 0x02000000 +- 0x1 0x0 0xf 0xffa00000 0x00040000 +- 0x2 0x0 0xf 0xffb00000 0x00020000>; +- }; +- +- soc: soc@fffe00000 { +- ranges = <0x0 0xf 0xffe00000 0x100000>; +- }; +- +- pci0: pcie@fffe09000 { +- reg = <0xf 0xffe09000 0x0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@fffe0a000 { +- reg = <0xf 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/include/ "p1020utm-pc.dtsi" +-/include/ "p1020si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1021mds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1021mds.dts +deleted file mode 100644 +index 54af8de53371..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1021mds.dts ++++ /dev/null +@@ -1,319 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * P1021 MDS Device Tree Source +- * +- * Copyright 2010,2012 Freescale Semiconductor Inc. +- */ +- +-/include/ "p1021si-pre.dtsi" +-/ { +- model = "fsl,P1021"; +- compatible = "fsl,P1021MDS"; +- +- aliases { +- ethernet3 = &enet3; +- ethernet4 = &enet4; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@ffe05000 { +- reg = <0x0 0xffe05000 0x0 0x1000>; +- +- /* NAND Flash, BCSR, PMC0/1*/ +- ranges = <0x0 0x0 0x0 0xfc000000 0x02000000 +- 0x1 0x0 0x0 0xf8000000 0x00008000 +- 0x2 0x0 0x0 0xf8010000 0x00020000 +- 0x3 0x0 0x0 0xf8020000 0x00020000>; +- +- nand@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,p1021-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x0 0x0 0x40000>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 1MB for u-boot Bootloader Image */ +- reg = <0x0 0x00100000>; +- label = "NAND (RO) U-Boot Image"; +- read-only; +- }; +- +- partition@100000 { +- /* 1MB for DTB Image */ +- reg = <0x00100000 0x00100000>; +- label = "NAND (RO) DTB Image"; +- read-only; +- }; +- +- partition@200000 { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00200000 0x00400000>; +- label = "NAND (RO) Linux Kernel Image"; +- read-only; +- }; +- +- partition@600000 { +- /* 5MB for Compressed Root file System Image */ +- reg = <0x00600000 0x00500000>; +- label = "NAND (RO) Compressed RFS Image"; +- read-only; +- }; +- +- partition@b00000 { +- /* 6MB for JFFS2 based Root file System */ +- reg = <0x00a00000 0x00600000>; +- label = "NAND (RW) JFFS2 Root File System"; +- }; +- +- partition@1100000 { +- /* 14MB for JFFS2 based Root file System */ +- reg = <0x01100000 0x00e00000>; +- label = "NAND (RW) Writable User area"; +- }; +- +- partition@1f00000 { +- /* 1MB for microcode */ +- reg = <0x01f00000 0x00100000>; +- label = "NAND (RO) QE Ucode"; +- read-only; +- }; +- }; +- +- bcsr@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,p1021mds-bcsr"; +- reg = <1 0 0x8000>; +- ranges = <0 1 0 0x8000>; +- }; +- +- pib@2,0 { +- compatible = "fsl,p1021mds-pib"; +- reg = <2 0 0x10000>; +- }; +- +- pib@3,0 { +- compatible = "fsl,p1021mds-pib"; +- reg = <3 0 0x10000>; +- }; +- }; +- +- soc: soc@ffe00000 { +- compatible = "fsl,p1021-immr", "simple-bus"; +- ranges = <0x0 0x0 0xffe00000 0x100000>; +- +- i2c@3000 { +- rtc@68 { +- compatible = "dallas,ds1374"; +- reg = <0x68>; +- }; +- }; +- +- spi@7000 { +- +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; /* input clock */ +- +- partition@u-boot { +- label = "u-boot-spi"; +- reg = <0x00000000 0x00100000>; +- read-only; +- }; +- partition@kernel { +- label = "kernel-spi"; +- reg = <0x00100000 0x00500000>; +- read-only; +- }; +- partition@dtb { +- label = "dtb-spi"; +- reg = <0x00600000 0x00100000>; +- read-only; +- }; +- partition@fs { +- label = "file system-spi"; +- reg = <0x00700000 0x00900000>; +- }; +- }; +- }; +- +- usb@22000 { +- phy_type = "ulpi"; +- dr_mode = "host"; +- }; +- +- mdio@24000 { +- phy0: ethernet-phy@0 { +- interrupts = <1 1 0 0>; +- reg = <0x0>; +- }; +- phy1: ethernet-phy@1 { +- interrupts = <2 1 0 0>; +- reg = <0x1>; +- }; +- phy4: ethernet-phy@4 { +- reg = <0x4>; +- }; +- tbi-phy@5 { +- device_type = "tbi-phy"; +- reg = <0x5>; +- }; +- }; +- +- mdio@25000 { +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- ethernet@b0000 { +- phy-handle = <&phy0>; +- phy-connection-type = "rgmii-id"; +- }; +- +- ethernet@b1000 { +- phy-handle = <&phy4>; +- tbi-handle = <&tbi0>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@b2000 { +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +- +- par_io@e0100 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xe0100 0x60>; +- ranges = <0x0 0xe0100 0x60>; +- device_type = "par_io"; +- num-ports = <3>; +- pio1: ucc_pin@1 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ +- 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ +- 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */ +- 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */ +- 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */ +- 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */ +- 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */ +- 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */ +- 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */ +- 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */ +- 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */ +- 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */ +- 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */ +- 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */ +- 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */ +- 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */ +- 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */ +- 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */ +- }; +- +- pio2: ucc_pin@2 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ +- 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ +- 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */ +- 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */ +- 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */ +- 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */ +- 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */ +- 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */ +- 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */ +- 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */ +- }; +- }; +- }; +- +- pci0: pcie@ffe09000 { +- reg = <0 0xffe09000 0 0x1000>; +- ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@ffe0a000 { +- reg = <0 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xc0000000 +- 0x2000000 0x0 0xc0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- qe: qe@ffe80000 { +- ranges = <0x0 0x0 0xffe80000 0x40000>; +- reg = <0 0xffe80000 0 0x480>; +- brg-frequency = <0>; +- bus-frequency = <0>; +- status = "disabled"; /* no firmware loaded */ +- +- enet3: ucc@2000 { +- device_type = "network"; +- compatible = "ucc_geth"; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "clk12"; +- tx-clock-name = "clk9"; +- pio-handle = <&pio1>; +- phy-handle = <&qe_phy0>; +- phy-connection-type = "mii"; +- }; +- +- mdio@2120 { +- qe_phy0: ethernet-phy@0 { +- interrupt-parent = <&mpic>; +- interrupts = <4 1 0 0>; +- reg = <0x0>; +- }; +- qe_phy1: ethernet-phy@3 { +- interrupt-parent = <&mpic>; +- interrupts = <5 1 0 0>; +- reg = <0x3>; +- }; +- tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet4: ucc@2400 { +- device_type = "network"; +- compatible = "ucc_geth"; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "none"; +- tx-clock-name = "clk13"; +- pio-handle = <&pio2>; +- phy-handle = <&qe_phy1>; +- phy-connection-type = "rmii"; +- }; +- }; +-}; +- +-/include/ "p1021si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1021rdb-pc.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1021rdb-pc.dtsi +deleted file mode 100644 +index 18f9b31602d0..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1021rdb-pc.dtsi ++++ /dev/null +@@ -1,256 +0,0 @@ +-/* +- * P1021 RDB Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&lbc { +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x1000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 256KB for Vitesse 7385 Switch firmware */ +- reg = <0x0 0x00040000>; +- label = "NOR Vitesse-7385 Firmware"; +- read-only; +- }; +- +- partition@40000 { +- /* 256KB for DTB Image */ +- reg = <0x00040000 0x00040000>; +- label = "NOR DTB Image"; +- }; +- +- partition@80000 { +- /* 3.5 MB for Linux Kernel Image */ +- reg = <0x00080000 0x00380000>; +- label = "NOR Linux Kernel Image"; +- }; +- +- partition@400000 { +- /* 10.75MB for JFFS2 based Root file System */ +- reg = <0x00400000 0x00ac0000>; +- label = "NOR JFFS2 Root File System"; +- }; +- +- partition@ec0000 { +- /* This location must not be altered */ +- /* 256KB for QE ucode firmware*/ +- reg = <0x00ec0000 0x00040000>; +- label = "NOR QE microcode firmware"; +- read-only; +- }; +- +- partition@f00000 { +- /* This location must not be altered */ +- /* 512KB for u-boot Bootloader Image */ +- /* 512KB for u-boot Environment Variables */ +- reg = <0x00f00000 0x00100000>; +- label = "NOR U-Boot Image"; +- }; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,p1021-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x1 0x0 0x40000>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 1MB for u-boot Bootloader Image */ +- reg = <0x0 0x00100000>; +- label = "NAND U-Boot Image"; +- read-only; +- }; +- +- partition@100000 { +- /* 1MB for DTB Image */ +- reg = <0x00100000 0x00100000>; +- label = "NAND DTB Image"; +- }; +- +- partition@200000 { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00200000 0x00400000>; +- label = "NAND Linux Kernel Image"; +- }; +- +- partition@600000 { +- /* 4MB for Compressed Root file System Image */ +- reg = <0x00600000 0x00400000>; +- label = "NAND Compressed RFS Image"; +- }; +- +- partition@a00000 { +- /* 7MB for JFFS2 based Root file System */ +- reg = <0x00a00000 0x00700000>; +- label = "NAND JFFS2 Root File System"; +- }; +- +- partition@1100000 { +- /* 15MB for User Writable Area */ +- reg = <0x01100000 0x00f00000>; +- label = "NAND Writable User area"; +- }; +- }; +- +- L2switch@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "vitesse-7385"; +- reg = <0x2 0x0 0x20000>; +- }; +-}; +- +-&soc { +- i2c@3000 { +- rtc@68 { +- compatible = "pericom,pt7c4338"; +- reg = <0x68>; +- }; +- }; +- +- spi@7000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; /* input clock */ +- +- partition@u-boot { +- /* 512KB for u-boot Bootloader Image */ +- reg = <0x0 0x00080000>; +- label = "SPI Flash U-Boot Image"; +- read-only; +- }; +- +- partition@dtb { +- /* 512KB for DTB Image */ +- reg = <0x00080000 0x00080000>; +- label = "SPI Flash DTB Image"; +- }; +- +- partition@kernel { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00100000 0x00400000>; +- label = "SPI Flash Linux Kernel Image"; +- }; +- +- partition@fs { +- /* 4MB for Compressed RFS Image */ +- reg = <0x00500000 0x00400000>; +- label = "SPI Flash Compressed RFSImage"; +- }; +- +- partition@jffs-fs { +- /* 7MB for JFFS2 based RFS */ +- reg = <0x00900000 0x00700000>; +- label = "SPI Flash JFFS2 RFS"; +- }; +- }; +- }; +- +- usb@22000 { +- phy_type = "ulpi"; +- }; +- +- mdio@24000 { +- phy0: ethernet-phy@0 { +- interrupt-parent = <&mpic>; +- interrupts = <3 1 0 0>; +- reg = <0x0>; +- }; +- +- phy1: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <2 1 0 0>; +- reg = <0x1>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- mdio@25000 { +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- mdio@26000 { +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- ptp_clock@b0e00 { +- compatible = "fsl,etsec-ptp"; +- reg = <0xb0e00 0xb0>; +- interrupts = <68 2 0 0 69 2 0 0>; +- fsl,tclk-period = <10>; +- fsl,tmr-prsc = <2>; +- fsl,tmr-add = <0x80000016>; +- fsl,tmr-fiper1 = <999999990>; +- fsl,tmr-fiper2 = <99990>; +- fsl,max-adj = <199999999>; +- }; +- +- enet0: ethernet@b0000 { +- fixed-link = <1 1 1000 0 0>; +- phy-connection-type = "rgmii-id"; +- +- }; +- +- enet1: ethernet@b1000 { +- phy-handle = <&phy0>; +- tbi-handle = <&tbi1>; +- phy-connection-type = "sgmii"; +- }; +- +- enet2: ethernet@b2000 { +- phy-handle = <&phy1>; +- tbi-handle = <&tbi2>; +- phy-connection-type = "rgmii-id"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1021rdb-pc_32b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1021rdb-pc_32b.dts +deleted file mode 100644 +index d2b4710357ac..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1021rdb-pc_32b.dts ++++ /dev/null +@@ -1,96 +0,0 @@ +-/* +- * P1021 RDB Device Tree Source +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1021si-pre.dtsi" +-/ { +- model = "fsl,P1021RDB"; +- compatible = "fsl,P1021RDB-PC"; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@ffe05000 { +- reg = <0 0xffe05000 0 0x1000>; +- +- /* NOR, NAND Flashes and Vitesse 5 port L2 switch */ +- ranges = <0x0 0x0 0x0 0xef000000 0x01000000 +- 0x1 0x0 0x0 0xff800000 0x00040000 +- 0x2 0x0 0x0 0xffb00000 0x00020000>; +- }; +- +- soc: soc@ffe00000 { +- ranges = <0x0 0x0 0xffe00000 0x100000>; +- }; +- +- pci0: pcie@ffe09000 { +- ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; +- reg = <0 0xffe09000 0 0x1000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@ffe0a000 { +- reg = <0 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- qe: qe@ffe80000 { +- ranges = <0x0 0x0 0xffe80000 0x40000>; +- reg = <0 0xffe80000 0 0x480>; +- brg-frequency = <0>; +- bus-frequency = <0>; +- }; +-}; +- +-/include/ "p1021rdb-pc.dtsi" +-/include/ "p1021si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1021rdb-pc_36b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1021rdb-pc_36b.dts +deleted file mode 100644 +index e298c29e5606..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1021rdb-pc_36b.dts ++++ /dev/null +@@ -1,96 +0,0 @@ +-/* +- * P1021 RDB Device Tree Source (36-bit address map) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1021si-pre.dtsi" +-/ { +- model = "fsl,P1021RDB"; +- compatible = "fsl,P1021RDB-PC"; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@fffe05000 { +- reg = <0xf 0xffe05000 0 0x1000>; +- +- /* NOR, NAND Flashes and Vitesse 5 port L2 switch */ +- ranges = <0x0 0x0 0xf 0xef000000 0x01000000 +- 0x1 0x0 0xf 0xff800000 0x00040000 +- 0x2 0x0 0xf 0xffb00000 0x00020000>; +- }; +- +- soc: soc@fffe00000 { +- ranges = <0x0 0xf 0xffe00000 0x100000>; +- }; +- +- pci0: pcie@fffe09000 { +- ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; +- reg = <0xf 0xffe09000 0 0x1000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@fffe0a000 { +- reg = <0xf 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xc0000000 +- 0x2000000 0x0 0xc0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- qe: qe@fffe80000 { +- ranges = <0x0 0xf 0xffe80000 0x40000>; +- reg = <0xf 0xffe80000 0 0x480>; +- brg-frequency = <0>; +- bus-frequency = <0>; +- }; +-}; +- +-/include/ "p1021rdb-pc.dtsi" +-/include/ "p1021si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1021si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1021si-post.dtsi +deleted file mode 100644 +index 407cb5fd0f5b..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1021si-post.dtsi ++++ /dev/null +@@ -1,247 +0,0 @@ +-/* +- * P1021/P1012 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2011-2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&lbc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus"; +- interrupts = <19 2 0 0>, +- <16 2 0 0>; +-}; +- +-/* controller at 0x9000 */ +-&pci0 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <16 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 +- >; +- }; +-}; +- +-/* controller at 0xa000 */ +-&pci1 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <16 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 +- >; +- }; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,p1021-immr", "simple-bus"; +- bus-frequency = <0>; // Filled out by uboot. +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <12>; +- }; +- +- ecm@1000 { +- compatible = "fsl,p1021-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <16 2 0 0>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,p1021-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-i2c-0.dtsi" +-/include/ "pq3-i2c-1.dtsi" +-/include/ "pq3-duart-0.dtsi" +- +-/include/ "pq3-espi-0.dtsi" +- spi@7000 { +- fsl,espi-num-chipselects = <4>; +- }; +- +-/include/ "pq3-gpio-0.dtsi" +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,p1021-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x40000>; // L2,256K +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-dma-0.dtsi" +-/include/ "pq3-usb2-dr-0.dtsi" +- usb@22000 { +- compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; +- }; +- +-/include/ "pq3-esdhc-0.dtsi" +- sdhc@2e000 { +- sdhci,auto-cmd12; +- }; +- +-/include/ "pq3-sec3.3-0.dtsi" +- +-/include/ "pq3-mpic.dtsi" +-/include/ "pq3-mpic-timer-B.dtsi" +- +-/include/ "pq3-etsec2-0.dtsi" +- enet0: enet0_grp2: ethernet@b0000 { +- }; +- +-/include/ "pq3-etsec2-1.dtsi" +- enet1: enet1_grp2: ethernet@b1000 { +- }; +- +-/include/ "pq3-etsec2-2.dtsi" +- enet2: enet2_grp2: ethernet@b2000 { +- }; +- +- global-utilities@e0000 { +- compatible = "fsl,p1021-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +-}; +- +-&qe { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "qe"; +- compatible = "fsl,qe"; +- fsl,qe-num-riscs = <1>; +- fsl,qe-num-snums = <28>; +- +- qeic: interrupt-controller@80 { +- interrupt-controller; +- compatible = "fsl,qe-ic"; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x80 0x80>; +- interrupts = <63 2 0 0 60 2 0 0>; //high:47 low:44 +- }; +- +- ucc@2000 { +- cell-index = <1>; +- reg = <0x2000 0x200>; +- interrupts = <32>; +- interrupt-parent = <&qeic>; +- }; +- +- mdio@2120 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2120 0x18>; +- compatible = "fsl,ucc-mdio"; +- }; +- +- ucc@2400 { +- cell-index = <5>; +- reg = <0x2400 0x200>; +- interrupts = <40>; +- interrupt-parent = <&qeic>; +- }; +- +- ucc@2600 { +- cell-index = <7>; +- reg = <0x2600 0x200>; +- interrupts = <42>; +- interrupt-parent = <&qeic>; +- }; +- +- ucc@2200 { +- cell-index = <3>; +- reg = <0x2200 0x200>; +- interrupts = <34>; +- interrupt-parent = <&qeic>; +- }; +- +- muram@10000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,qe-muram", "fsl,cpm-muram"; +- ranges = <0x0 0x10000 0x6000>; +- +- data-only@0 { +- compatible = "fsl,qe-muram-data", +- "fsl,cpm-muram-data"; +- reg = <0x0 0x6000>; +- }; +- }; +-}; +- +-/include/ "pq3-etsec2-grp2-0.dtsi" +-/include/ "pq3-etsec2-grp2-1.dtsi" +-/include/ "pq3-etsec2-grp2-2.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1021si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1021si-pre.dtsi +deleted file mode 100644 +index 36161b500176..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1021si-pre.dtsi ++++ /dev/null +@@ -1,71 +0,0 @@ +-/* +- * P1021/P1012 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e500v2_power_isa.dtsi" +- +-/ { +- compatible = "fsl,P1021"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- pci0 = &pci0; +- pci1 = &pci1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,P1021@0 { +- device_type = "cpu"; +- reg = <0x0>; +- next-level-cache = <&L2>; +- }; +- +- PowerPC,P1021@1 { +- device_type = "cpu"; +- reg = <0x1>; +- next-level-cache = <&L2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1022ds.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1022ds.dtsi +deleted file mode 100644 +index ddefbf64f7f8..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1022ds.dtsi ++++ /dev/null +@@ -1,239 +0,0 @@ +-/* +- * P1022 DS Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&board_lbc { +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- reg = <0x0 0x03000000>; +- label = "ramdisk-nor"; +- read-only; +- }; +- +- partition@3000000 { +- reg = <0x03000000 0x00e00000>; +- label = "diagnostic-nor"; +- read-only; +- }; +- +- partition@3e00000 { +- reg = <0x03e00000 0x00200000>; +- label = "dink-nor"; +- read-only; +- }; +- +- partition@4000000 { +- reg = <0x04000000 0x00400000>; +- label = "kernel-nor"; +- read-only; +- }; +- +- partition@4400000 { +- reg = <0x04400000 0x03b00000>; +- label = "jffs2-nor"; +- }; +- +- partition@7f00000 { +- reg = <0x07f00000 0x00080000>; +- label = "dtb-nor"; +- read-only; +- }; +- +- partition@7f80000 { +- reg = <0x07f80000 0x00080000>; +- label = "u-boot-nor"; +- read-only; +- }; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,elbc-fcm-nand"; +- reg = <0x2 0x0 0x40000>; +- +- partition@0 { +- reg = <0x0 0x02000000>; +- label = "u-boot-nand"; +- read-only; +- }; +- +- partition@2000000 { +- reg = <0x02000000 0x10000000>; +- label = "jffs2-nand"; +- }; +- +- partition@12000000 { +- reg = <0x12000000 0x10000000>; +- label = "ramdisk-nand"; +- read-only; +- }; +- +- partition@22000000 { +- reg = <0x22000000 0x04000000>; +- label = "kernel-nand"; +- }; +- +- partition@26000000 { +- reg = <0x26000000 0x01000000>; +- label = "dtb-nand"; +- read-only; +- }; +- +- partition@27000000 { +- reg = <0x27000000 0x19000000>; +- label = "reserved-nand"; +- }; +- }; +- +- board-control@3,0 { +- compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis"; +- reg = <3 0 0x30>; +- interrupt-parent = <&mpic>; +- /* +- * IRQ8 is generated if the "EVENT" switch is pressed +- * and PX_CTL[EVESEL] is set to 00. +- */ +- interrupts = <8 0 0 0>; +- }; +-}; +- +-&board_soc { +- i2c@3100 { +- wm8776:codec@1a { +- compatible = "wlf,wm8776"; +- reg = <0x1a>; +- /* +- * clock-frequency will be set by U-Boot if +- * the clock is enabled. +- */ +- }; +- rtc@68 { +- compatible = "dallas,ds3232"; +- reg = <0x68>; +- interrupts = <0x1 0x1 0 0>; +- }; +- adt7461@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- }; +- +- spi@7000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; /* input clock */ +- +- partition@0 { +- label = "u-boot-spi"; +- reg = <0x00000000 0x00100000>; +- read-only; +- }; +- partition@100000 { +- label = "kernel-spi"; +- reg = <0x00100000 0x00500000>; +- read-only; +- }; +- partition@600000 { +- label = "dtb-spi"; +- reg = <0x00600000 0x00100000>; +- read-only; +- }; +- partition@700000 { +- label = "file system-spi"; +- reg = <0x00700000 0x00900000>; +- }; +- }; +- }; +- +- ssi@15000 { +- fsl,mode = "i2s-slave"; +- codec-handle = <&wm8776>; +- fsl,ssi-asynchronous; +- }; +- +- usb@22000 { +- phy_type = "ulpi"; +- }; +- +- usb@23000 { +- status = "disabled"; +- }; +- +- mdio@24000 { +- phy0: ethernet-phy@0 { +- interrupts = <3 1 0 0>; +- reg = <0x1>; +- }; +- phy1: ethernet-phy@1 { +- interrupts = <9 1 0 0>; +- reg = <0x2>; +- }; +- tbi-phy@2 { +- device_type = "tbi-phy"; +- reg = <0x2>; +- }; +- }; +- +- ptp_clock@b0e00 { +- compatible = "fsl,etsec-ptp"; +- reg = <0xb0e00 0xb0>; +- interrupts = <68 2 0 0 69 2 0 0>; +- fsl,tclk-period = <5>; +- fsl,tmr-prsc = <2>; +- fsl,tmr-add = <0xc01ebd3d>; +- fsl,tmr-fiper1 = <999999995>; +- fsl,tmr-fiper2 = <99990>; +- fsl,max-adj = <266499999>; +- }; +- +- ethernet@b0000 { +- phy-handle = <&phy0>; +- phy-connection-type = "rgmii-id"; +- }; +- +- ethernet@b1000 { +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1022ds_32b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1022ds_32b.dts +deleted file mode 100644 +index 5a7eaceb9e8e..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1022ds_32b.dts ++++ /dev/null +@@ -1,103 +0,0 @@ +-/* +- * P1022 DS 32-bit Physical Address Map Device Tree Source +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1022si-pre.dtsi" +-/ { +- model = "fsl,P1022DS"; +- compatible = "fsl,P1022DS"; +- +- memory { +- device_type = "memory"; +- }; +- +- board_lbc: lbc: localbus@ffe05000 { +- ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 +- 0x1 0x0 0x0 0xe0000000 0x08000000 +- 0x2 0x0 0x0 0xff800000 0x00040000 +- 0x3 0x0 0x0 0xffdf0000 0x00008000>; +- reg = <0x0 0xffe05000 0 0x1000>; +- }; +- +- board_soc: soc: soc@ffe00000 { +- ranges = <0x0 0x0 0xffe00000 0x100000>; +- }; +- +- pci0: pcie@ffe09000 { +- ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; +- reg = <0x0 0xffe09000 0 0x1000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@ffe0a000 { +- ranges = <0x2000000 0x0 0xe0000000 0 0xc0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; +- reg = <0 0xffe0a000 0 0x1000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci2: pcie@ffe0b000 { +- ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; +- reg = <0 0xffe0b000 0 0x1000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/include/ "p1022si-post.dtsi" +-/include/ "p1022ds.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1022ds_36b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1022ds_36b.dts +deleted file mode 100644 +index 88063cd9e20a..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1022ds_36b.dts ++++ /dev/null +@@ -1,103 +0,0 @@ +-/* +- * P1022 DS 36-bit Physical Address Map Device Tree Source +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1022si-pre.dtsi" +-/ { +- model = "fsl,P1022DS"; +- compatible = "fsl,P1022DS"; +- +- memory { +- device_type = "memory"; +- }; +- +- board_lbc: lbc: localbus@fffe05000 { +- ranges = <0x0 0x0 0xf 0xe8000000 0x08000000 +- 0x1 0x0 0xf 0xe0000000 0x08000000 +- 0x2 0x0 0xf 0xff800000 0x00040000 +- 0x3 0x0 0xf 0xffdf0000 0x00008000>; +- reg = <0xf 0xffe05000 0 0x1000>; +- }; +- +- board_soc: soc: soc@fffe00000 { +- ranges = <0x0 0xf 0xffe00000 0x100000>; +- }; +- +- pci0: pcie@fffe09000 { +- ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; +- reg = <0xf 0xffe09000 0 0x1000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@fffe0a000 { +- ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>; +- reg = <0xf 0xffe0a000 0 0x1000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci2: pcie@fffe0b000 { +- ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; +- reg = <0xf 0xffe0b000 0 0x1000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/include/ "p1022si-post.dtsi" +-/include/ "p1022ds.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1022rdk.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1022rdk.dts +deleted file mode 100644 +index 29e8af1e3711..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1022rdk.dts ++++ /dev/null +@@ -1,188 +0,0 @@ +-/* +- * P1022 RDK 32-bit Physical Address Map Device Tree Source +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1022si-pre.dtsi" +-/ { +- model = "fsl,P1022RDK"; +- compatible = "fsl,P1022RDK"; +- +- memory { +- device_type = "memory"; +- }; +- +- board_lbc: lbc: localbus@ffe05000 { +- /* The P1022 RDK does not have any localbus devices */ +- status = "disabled"; +- }; +- +- board_soc: soc: soc@ffe00000 { +- ranges = <0x0 0x0 0xffe00000 0x100000>; +- +- i2c@3100 { +- wm8960:codec@1a { +- compatible = "wlf,wm8960"; +- reg = <0x1a>; +- /* MCLK source is a stand-alone oscillator */ +- clock-frequency = <12288000>; +- }; +- rtc@68 { +- compatible = "st,m41t62"; +- reg = <0x68>; +- }; +- adt7461@4c{ +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- zl6100@21{ +- compatible = "isil,zl6100"; +- reg = <0x21>; +- }; +- zl6100@24{ +- compatible = "isil,zl6100"; +- reg = <0x24>; +- }; +- zl6100@26{ +- compatible = "isil,zl6100"; +- reg = <0x26>; +- }; +- zl6100@29{ +- compatible = "isil,zl6100"; +- reg = <0x29>; +- }; +- }; +- +- spi@7000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,m25p80", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <1000000>; +- partition@0 { +- label = "full-spi-flash"; +- reg = <0x00000000 0x00100000>; +- }; +- }; +- }; +- +- ssi@15000 { +- fsl,mode = "i2s-slave"; +- codec-handle = <&wm8960>; +- }; +- +- usb@22000 { +- phy_type = "ulpi"; +- }; +- +- usb@23000 { +- phy_type = "ulpi"; +- }; +- +- mdio@24000 { +- phy0: ethernet-phy@0 { +- interrupts = <3 1 0 0>; +- reg = <0x1>; +- }; +- phy1: ethernet-phy@1 { +- interrupts = <9 1 0 0>; +- reg = <0x2>; +- }; +- }; +- +- mdio@25000 { +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- ethernet@b0000 { +- phy-handle = <&phy0>; +- phy-connection-type = "rgmii-id"; +- }; +- +- ethernet@b1000 { +- phy-handle = <&phy1>; +- tbi-handle = <&tbi0>; +- phy-connection-type = "sgmii"; +- }; +- }; +- +- pci0: pcie@ffe09000 { +- ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; +- reg = <0x0 0xffe09000 0 0x1000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@ffe0a000 { +- ranges = <0x2000000 0x0 0xe0000000 0 0xc0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; +- reg = <0 0xffe0a000 0 0x1000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci2: pcie@ffe0b000 { +- ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; +- reg = <0 0xffe0b000 0 0x1000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/include/ "p1022si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1022si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1022si-post.dtsi +deleted file mode 100644 +index 5f51b7bfc064..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1022si-post.dtsi ++++ /dev/null +@@ -1,249 +0,0 @@ +-/* +- * P1022/P1013 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&lbc { +- #address-cells = <2>; +- #size-cells = <1>; +- /* +- * The localbus on the P1022 is not a simple-bus because of the eLBC +- * pin muxing when the DIU is enabled. +- */ +- compatible = "fsl,p1022-elbc", "fsl,elbc"; +- interrupts = <19 2 0 0>, +- <16 2 0 0>; +-}; +- +-/* controller at 0x9000 */ +-&pci0 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <16 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 +- >; +- }; +-}; +- +-/* controller at 0xa000 */ +-&pci1 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <16 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 +- >; +- }; +-}; +- +-/* controller at 0xb000 */ +-&pci2 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <16 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0 +- >; +- }; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,p1022-immr", "simple-bus"; +- bus-frequency = <0>; // Filled out by uboot. +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <12>; +- }; +- +- ecm@1000 { +- compatible = "fsl,p1022-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <16 2 0 0>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,p1022-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-i2c-0.dtsi" +-/include/ "pq3-i2c-1.dtsi" +-/include/ "pq3-duart-0.dtsi" +-/include/ "pq3-espi-0.dtsi" +- spi@7000 { +- fsl,espi-num-chipselects = <4>; +- }; +- +-/include/ "pq3-dma-1.dtsi" +- dma@c300 { +- dma00: dma-channel@0 { +- compatible = "fsl,ssi-dma-channel"; +- }; +- dma01: dma-channel@80 { +- compatible = "fsl,ssi-dma-channel"; +- }; +- }; +- +-/include/ "pq3-gpio-0.dtsi" +- +- display: display@10000 { +- compatible = "fsl,diu", "fsl,p1022-diu"; +- reg = <0x10000 1000>; +- interrupts = <64 2 0 0>; +- }; +- +- ssi@15000 { +- compatible = "fsl,mpc8610-ssi"; +- cell-index = <0>; +- reg = <0x15000 0x100>; +- interrupts = <75 2 0 0>; +- fsl,playback-dma = <&dma00>; +- fsl,capture-dma = <&dma01>; +- fsl,fifo-depth = <15>; +- }; +- +-/include/ "pq3-sata2-0.dtsi" +-/include/ "pq3-sata2-1.dtsi" +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,p1022-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x40000>; // L2,256K +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-dma-0.dtsi" +-/include/ "pq3-usb2-dr-0.dtsi" +- usb@22000 { +- compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; +- }; +-/include/ "pq3-usb2-dr-1.dtsi" +- usb@23000 { +- compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; +- }; +- +-/include/ "pq3-esdhc-0.dtsi" +- sdhc@2e000 { +- compatible = "fsl,p1022-esdhc", "fsl,esdhc"; +- sdhci,auto-cmd12; +- }; +- +-/include/ "pq3-sec3.3-0.dtsi" +-/include/ "pq3-mpic.dtsi" +-/include/ "pq3-mpic-timer-B.dtsi" +- +-/include/ "pq3-etsec2-0.dtsi" +- enet0: enet0_grp2: ethernet@b0000 { +- fsl,wake-on-filer; +- }; +- +-/include/ "pq3-etsec2-1.dtsi" +- enet1: enet1_grp2: ethernet@b1000 { +- fsl,wake-on-filer; +- }; +- +- global-utilities@e0000 { +- compatible = "fsl,p1022-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +- +- power@e0070{ +- compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc"; +- reg = <0xe0070 0x20>; +- }; +- +-}; +- +-/include/ "pq3-etsec2-grp2-0.dtsi" +-/include/ "pq3-etsec2-grp2-1.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1022si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1022si-pre.dtsi +deleted file mode 100644 +index de76ae8992c6..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1022si-pre.dtsi ++++ /dev/null +@@ -1,73 +0,0 @@ +-/* +- * P1022/P1013 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e500v2_power_isa.dtsi" +- +-/ { +- compatible = "fsl,P1022"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- vga = &display; +- display = &display; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,P1022@0 { +- device_type = "cpu"; +- reg = <0x0>; +- next-level-cache = <&L2>; +- }; +- +- PowerPC,P1022@1 { +- device_type = "cpu"; +- reg = <0x1>; +- next-level-cache = <&L2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1023rdb.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1023rdb.dts +deleted file mode 100644 +index ead928364beb..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1023rdb.dts ++++ /dev/null +@@ -1,260 +0,0 @@ +-/* +- * P1023 RDB Device Tree Source +- * +- * Copyright 2013 - 2014 Freescale Semiconductor Inc. +- * +- * Author: Chunhe Lan +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1023si-pre.dtsi" +- +-/ { +- model = "fsl,P1023"; +- compatible = "fsl,P1023RDB"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- memory { +- device_type = "memory"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- qportals: qman-portals@ff000000 { +- ranges = <0x0 0xf 0xff000000 0x200000>; +- }; +- +- bportals: bman-portals@ff200000 { +- ranges = <0x0 0xf 0xff200000 0x200000>; +- }; +- +- soc: soc@ff600000 { +- ranges = <0x0 0x0 0xff600000 0x200000>; +- +- i2c@3000 { +- eeprom@53 { +- compatible = "atmel,24c04"; +- reg = <0x53>; +- }; +- +- rtc@6f { +- compatible = "microchip,mcp7941x"; +- reg = <0x6f>; +- }; +- }; +- +- usb@22000 { +- dr_mode = "host"; +- phy_type = "ulpi"; +- }; +- }; +- +- lbc: localbus@ff605000 { +- reg = <0 0xff605000 0 0x1000>; +- +- /* NOR, NAND Flashes */ +- ranges = <0x0 0x0 0x0 0xec000000 0x04000000 +- 0x1 0x0 0x0 0xffa00000 0x08000000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x04000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- /* 48MB for Root File System */ +- reg = <0x00000000 0x03000000>; +- label = "NOR Root File System"; +- }; +- +- partition@3000000 { +- /* 1MB for DTB Image */ +- reg = <0x03000000 0x00100000>; +- label = "NOR DTB Image"; +- }; +- +- partition@3100000 { +- /* 14MB for Linux Kernel Image */ +- reg = <0x03100000 0x00e00000>; +- label = "NOR Linux Kernel Image"; +- }; +- +- partition@3f00000 { +- /* This location must not be altered */ +- /* 512KB for u-boot Bootloader Image */ +- /* 512KB for u-boot Environment Variables */ +- reg = <0x03f00000 0x00100000>; +- label = "NOR U-Boot Image"; +- read-only; +- }; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,elbc-fcm-nand"; +- reg = <0x1 0x0 0x40000>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 1MB for u-boot Bootloader Image */ +- reg = <0x0 0x00100000>; +- label = "NAND U-Boot Image"; +- read-only; +- }; +- +- partition@100000 { +- /* 1MB for DTB Image */ +- reg = <0x00100000 0x00100000>; +- label = "NAND DTB Image"; +- }; +- +- partition@200000 { +- /* 14MB for Linux Kernel Image */ +- reg = <0x00200000 0x00e00000>; +- label = "NAND Linux Kernel Image"; +- }; +- +- partition@1000000 { +- /* 96MB for Root File System Image */ +- reg = <0x01000000 0x06000000>; +- label = "NAND Root File System"; +- }; +- +- partition@7000000 { +- /* 16MB for User Writable Area */ +- reg = <0x07000000 0x01000000>; +- label = "NAND Writable User area"; +- }; +- }; +- }; +- +- pci0: pcie@ff60a000 { +- reg = <0 0xff60a000 0 0x1000>; +- ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; +- pcie@0 { +- /* IRQ[0:3] are pulled up on board, set to active-low */ +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 0 1 0 0 +- 0000 0 0 2 &mpic 1 1 0 0 +- 0000 0 0 3 &mpic 2 1 0 0 +- 0000 0 0 4 &mpic 3 1 0 0 +- >; +- ranges = <0x2000000 0x0 0xc0000000 +- 0x2000000 0x0 0xc0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- board_pci1: pci1: pcie@ff609000 { +- reg = <0 0xff609000 0 0x1000>; +- ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; +- pcie@0 { +- /* +- * IRQ[4:6] only for PCIe, set to active-high, +- * IRQ[7] is pulled up on board, set to active-low +- */ +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 4 2 0 0 +- 0000 0 0 2 &mpic 5 2 0 0 +- 0000 0 0 3 &mpic 6 2 0 0 +- 0000 0 0 4 &mpic 7 1 0 0 +- >; +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci2: pcie@ff60b000 { +- reg = <0 0xff60b000 0 0x1000>; +- ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; +- pcie@0 { +- /* +- * IRQ[8:10] are pulled up on board, set to active-low +- * IRQ[11] only for PCIe, set to active-high, +- */ +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 8 1 0 0 +- 0000 0 0 2 &mpic 9 1 0 0 +- 0000 0 0 3 &mpic 10 1 0 0 +- 0000 0 0 4 &mpic 11 2 0 0 +- >; +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/include/ "p1023si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1023si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1023si-post.dtsi +deleted file mode 100644 +index da6d3fc6ba41..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1023si-post.dtsi ++++ /dev/null +@@ -1,307 +0,0 @@ +-/* +- * P1023/P1017 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2011 - 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&bman_fbpr { +- compatible = "fsl,bman-fbpr"; +- alloc-ranges = <0 0 0x10 0>; +-}; +- +-&qman_fqd { +- compatible = "fsl,qman-fqd"; +- alloc-ranges = <0 0 0x10 0>; +-}; +- +-&qman_pfdr { +- compatible = "fsl,qman-pfdr"; +- alloc-ranges = <0 0 0x10 0>; +-}; +- +-&lbc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus"; +- interrupts = <19 2 0 0>, +- <16 2 0 0>; +-}; +- +-/* controller at 0xa000 */ +-&pci0 { +- compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 0 0>; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 0 0>; +- }; +-}; +- +-/* controller at 0x9000 */ +-&pci1 { +- compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 0 0>; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 0 0>; +- }; +-}; +- +-/* controller at 0xb000 */ +-&pci2 { +- compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 0 0>; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 0 0>; +- }; +-}; +- +-&qportals { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- +- qportal0: qman-portal@0 { +- compatible = "fsl,qman-portal"; +- reg = <0x0 0x4000>, <0x100000 0x1000>; +- interrupts = <29 2 0 0>; +- cell-index = <0>; +- }; +- qportal1: qman-portal@4000 { +- compatible = "fsl,qman-portal"; +- reg = <0x4000 0x4000>, <0x101000 0x1000>; +- interrupts = <31 2 0 0>; +- cell-index = <1>; +- }; +- qportal2: qman-portal@8000 { +- compatible = "fsl,qman-portal"; +- reg = <0x8000 0x4000>, <0x102000 0x1000>; +- interrupts = <33 2 0 0>; +- cell-index = <2>; +- }; +-}; +- +-&bportals { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- +- bman-portal@0 { +- compatible = "fsl,bman-portal"; +- reg = <0x0 0x4000>, <0x100000 0x1000>; +- interrupts = <30 2 0 0>; +- }; +- bman-portal@4000 { +- compatible = "fsl,bman-portal"; +- reg = <0x4000 0x4000>, <0x101000 0x1000>; +- interrupts = <32 2 0 0>; +- }; +- bman-portal@8000 { +- compatible = "fsl,bman-portal"; +- reg = <0x8000 0x4000>, <0x102000 0x1000>; +- interrupts = <34 2 0 0>; +- }; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,p1023-immr", "simple-bus"; +- bus-frequency = <0>; // Filled out by uboot. +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <12>; +- }; +- +- ecm@1000 { +- compatible = "fsl,p1023-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <16 2 0 0>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,p1023-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-i2c-0.dtsi" +-/include/ "pq3-i2c-1.dtsi" +-/include/ "pq3-duart-0.dtsi" +- +-/include/ "pq3-espi-0.dtsi" +- spi@7000 { +- fsl,espi-num-chipselects = <4>; +- }; +- +-/include/ "pq3-gpio-0.dtsi" +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,p1023-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x40000>; // L2,256K +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-dma-0.dtsi" +-/include/ "pq3-usb2-dr-0.dtsi" +- usb@22000 { +- compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; +- }; +- +- crypto: crypto@300000 { +- compatible = "fsl,sec-v4.2", "fsl,sec-v4.0"; +- fsl,sec-era = <3>; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x30000 0x10000>; +- ranges = <0 0x30000 0x10000>; +- interrupts = <58 2 0 0>; +- +- sec_jr0: jr@1000 { +- compatible = "fsl,sec-v4.2-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x1000 0x1000>; +- interrupts = <45 2 0 0>; +- }; +- +- sec_jr1: jr@2000 { +- compatible = "fsl,sec-v4.2-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x2000 0x1000>; +- interrupts = <45 2 0 0>; +- }; +- +- sec_jr2: jr@3000 { +- compatible = "fsl,sec-v4.2-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x3000 0x1000>; +- interrupts = <57 2 0 0>; +- }; +- +- sec_jr3: jr@4000 { +- compatible = "fsl,sec-v4.2-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x4000 0x1000>; +- interrupts = <57 2 0 0>; +- }; +- +- rtic@6000 { +- compatible = "fsl,sec-v4.2-rtic", +- "fsl,sec-v4.0-rtic"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x6000 0x100>; +- ranges = <0x0 0x6100 0xe00>; +- +- rtic_a: rtic-a@0 { +- compatible = "fsl,sec-v4.2-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x00 0x20 0x100 0x80>; +- }; +- +- rtic_b: rtic-b@20 { +- compatible = "fsl,sec-v4.2-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x20 0x20 0x200 0x80>; +- }; +- +- rtic_c: rtic-c@40 { +- compatible = "fsl,sec-v4.2-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x40 0x20 0x300 0x80>; +- }; +- +- rtic_d: rtic-d@60 { +- compatible = "fsl,sec-v4.2-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x60 0x20 0x500 0x80>; +- }; +- }; +- }; +- +-/include/ "pq3-mpic.dtsi" +-/include/ "pq3-mpic-timer-B.dtsi" +- +- qman: qman@88000 { +- compatible = "fsl,qman"; +- reg = <0x88000 0x1000>; +- interrupts = <16 2 0 0>; +- fsl,qman-portals = <&qportals>; +- memory-region = <&qman_fqd &qman_pfdr>; +- }; +- +- bman: bman@8a000 { +- compatible = "fsl,bman"; +- reg = <0x8a000 0x1000>; +- interrupts = <16 2 0 0>; +- fsl,bman-portals = <&bportals>; +- memory-region = <&bman_fbpr>; +- }; +- +- global-utilities@e0000 { +- compatible = "fsl,p1023-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1023si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1023si-pre.dtsi +deleted file mode 100644 +index 132a1521921a..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1023si-pre.dtsi ++++ /dev/null +@@ -1,79 +0,0 @@ +-/* +- * P1023/P1017 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e500v2_power_isa.dtsi" +- +-/ { +- compatible = "fsl,P1023"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- +- crypto = &crypto; +- sec_jr0 = &sec_jr0; +- sec_jr1 = &sec_jr1; +- sec_jr2 = &sec_jr2; +- sec_jr3 = &sec_jr3; +- rtic_a = &rtic_a; +- rtic_b = &rtic_b; +- rtic_c = &rtic_c; +- rtic_d = &rtic_d; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,P1023@0 { +- device_type = "cpu"; +- reg = <0x0>; +- next-level-cache = <&L2>; +- }; +- +- PowerPC,P1023@1 { +- device_type = "cpu"; +- reg = <0x1>; +- next-level-cache = <&L2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1024rdb.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1024rdb.dtsi +deleted file mode 100644 +index b4d05867f707..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1024rdb.dtsi ++++ /dev/null +@@ -1,228 +0,0 @@ +-/* +- * P1024 RDB Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&lbc { +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x1000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 256KB for Vitesse 7385 Switch firmware */ +- reg = <0x0 0x00040000>; +- label = "NOR Vitesse-7385 Firmware"; +- read-only; +- }; +- +- partition@40000 { +- /* 256KB for DTB Image */ +- reg = <0x00040000 0x00040000>; +- label = "NOR DTB Image"; +- }; +- +- partition@80000 { +- /* 3.5 MB for Linux Kernel Image */ +- reg = <0x00080000 0x00380000>; +- label = "NOR Linux Kernel Image"; +- }; +- +- partition@400000 { +- /* 11MB for JFFS2 based Root file System */ +- reg = <0x00400000 0x00b00000>; +- label = "NOR JFFS2 Root File System"; +- }; +- +- partition@f00000 { +- /* This location must not be altered */ +- /* 512KB for u-boot Bootloader Image */ +- /* 512KB for u-boot Environment Variables */ +- reg = <0x00f00000 0x00100000>; +- label = "NOR U-Boot Image"; +- read-only; +- }; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,p1020-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x1 0x0 0x40000>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 1MB for u-boot Bootloader Image */ +- reg = <0x0 0x00100000>; +- label = "NAND U-Boot Image"; +- read-only; +- }; +- +- partition@100000 { +- /* 1MB for DTB Image */ +- reg = <0x00100000 0x00100000>; +- label = "NAND DTB Image"; +- }; +- +- partition@200000 { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00200000 0x00400000>; +- label = "NAND Linux Kernel Image"; +- }; +- +- partition@600000 { +- /* 4MB for Compressed Root file System Image */ +- reg = <0x00600000 0x00400000>; +- label = "NAND Compressed RFS Image"; +- }; +- +- partition@a00000 { +- /* 15MB for JFFS2 based Root file System */ +- reg = <0x00a00000 0x00f00000>; +- label = "NAND JFFS2 Root File System"; +- }; +- +- partition@1900000 { +- /* 7MB for User Writable Area */ +- reg = <0x01900000 0x00700000>; +- label = "NAND Writable User area"; +- }; +- }; +-}; +- +-&soc { +- spi@7000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,m25p80", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; +- +- partition@0 { +- /* 512KB for u-boot Bootloader Image */ +- reg = <0x0 0x00080000>; +- label = "SPI U-Boot Image"; +- read-only; +- }; +- +- partition@80000 { +- /* 512KB for DTB Image */ +- reg = <0x00080000 0x00080000>; +- label = "SPI DTB Image"; +- }; +- +- partition@100000 { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00100000 0x00400000>; +- label = "SPI Linux Kernel Image"; +- }; +- +- partition@500000 { +- /* 4MB for Compressed RFS Image */ +- reg = <0x00500000 0x00400000>; +- label = "SPI Compressed RFS Image"; +- }; +- +- partition@900000 { +- /* 7MB for JFFS2 based RFS */ +- reg = <0x00900000 0x00700000>; +- label = "SPI JFFS2 RFS"; +- }; +- }; +- }; +- +- i2c@3000 { +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +- }; +- +- usb@22000 { +- phy_type = "ulpi"; +- }; +- +- usb@23000 { +- status = "disabled"; +- }; +- +- mdio@24000 { +- phy0: ethernet-phy@0 { +- interrupts = <3 1 0 0>; +- reg = <0x0>; +- }; +- phy1: ethernet-phy@1 { +- interrupts = <2 1 0 0>; +- reg = <0x1>; +- }; +- phy2: ethernet-phy@2 { +- interrupts = <1 1 0 0>; +- reg = <0x2>; +- }; +- }; +- +- mdio@25000 { +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- mdio@26000 { +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- ethernet@b0000 { +- phy-handle = <&phy2>; +- phy-connection-type = "rgmii-id"; +- }; +- +- ethernet@b1000 { +- phy-handle = <&phy0>; +- tbi-handle = <&tbi0>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@b2000 { +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1024rdb_32b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1024rdb_32b.dts +deleted file mode 100644 +index 8b09b9d56ad1..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1024rdb_32b.dts ++++ /dev/null +@@ -1,87 +0,0 @@ +-/* +- * P1024 RDB 32Bit Physical Address Map Device Tree Source +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1020si-pre.dtsi" +-/ { +- model = "fsl,P1024RDB"; +- compatible = "fsl,P1024RDB"; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@ffe05000 { +- reg = <0x0 0xffe05000 0 0x1000>; +- ranges = <0x0 0x0 0x0 0xef000000 0x01000000 +- 0x1 0x0 0x0 0xff800000 0x00040000>; +- }; +- +- soc: soc@ffe00000 { +- ranges = <0x0 0x0 0xffe00000 0x100000>; +- }; +- +- pci0: pcie@ffe09000 { +- reg = <0x0 0xffe09000 0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@ffe0a000 { +- reg = <0x0 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0x0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>; +- pcie@0 { +- reg = <0x0 0x0 0x0 0x0 0x0>; +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/include/ "p1024rdb.dtsi" +-/include/ "p1020si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1024rdb_36b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1024rdb_36b.dts +deleted file mode 100644 +index e7093aef28f1..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1024rdb_36b.dts ++++ /dev/null +@@ -1,87 +0,0 @@ +-/* +- * P1024 RDB 36Bit Physical Address Map Device Tree Source +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1020si-pre.dtsi" +-/ { +- model = "fsl,P1024RDB"; +- compatible = "fsl,P1024RDB"; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@fffe05000 { +- reg = <0xf 0xffe05000 0 0x1000>; +- ranges = <0x0 0x0 0xf 0xef000000 0x01000000 +- 0x1 0x0 0xf 0xff800000 0x00040000>; +- }; +- +- soc: soc@fffe00000 { +- ranges = <0x0 0xf 0xffe00000 0x100000>; +- }; +- +- pci0: pcie@fffe09000 { +- reg = <0xf 0xffe09000 0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@fffe0a000 { +- reg = <0xf 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; +- pcie@0 { +- reg = <0x0 0x0 0x0 0x0 0x0>; +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/include/ "p1024rdb.dtsi" +-/include/ "p1020si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1025rdb.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1025rdb.dtsi +deleted file mode 100644 +index 0a5434a631c3..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1025rdb.dtsi ++++ /dev/null +@@ -1,326 +0,0 @@ +-/* +- * P1025 RDB Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&lbc { +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x1000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 256KB for Vitesse 7385 Switch firmware */ +- reg = <0x0 0x00040000>; +- label = "NOR Vitesse-7385 Firmware"; +- read-only; +- }; +- +- partition@40000 { +- /* 256KB for DTB Image */ +- reg = <0x00040000 0x00040000>; +- label = "NOR DTB Image"; +- }; +- +- partition@80000 { +- /* 3.5 MB for Linux Kernel Image */ +- reg = <0x00080000 0x00380000>; +- label = "NOR Linux Kernel Image"; +- }; +- +- partition@400000 { +- /* 11MB for JFFS2 based Root file System */ +- reg = <0x00400000 0x00b00000>; +- label = "NOR JFFS2 Root File System"; +- }; +- +- partition@f00000 { +- /* This location must not be altered */ +- /* 512KB for u-boot Bootloader Image */ +- /* 512KB for u-boot Environment Variables */ +- reg = <0x00f00000 0x00100000>; +- label = "NOR U-Boot Image"; +- read-only; +- }; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,p1025-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x1 0x0 0x40000>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 1MB for u-boot Bootloader Image */ +- reg = <0x0 0x00100000>; +- label = "NAND U-Boot Image"; +- read-only; +- }; +- +- partition@100000 { +- /* 1MB for DTB Image */ +- reg = <0x00100000 0x00100000>; +- label = "NAND DTB Image"; +- }; +- +- partition@200000 { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00200000 0x00400000>; +- label = "NAND Linux Kernel Image"; +- }; +- +- partition@600000 { +- /* 4MB for Compressed Root file System Image */ +- reg = <0x00600000 0x00400000>; +- label = "NAND Compressed RFS Image"; +- }; +- +- partition@a00000 { +- /* 7MB for JFFS2 based Root file System */ +- reg = <0x00a00000 0x00700000>; +- label = "NAND JFFS2 Root File System"; +- }; +- +- partition@1100000 { +- /* 15MB for JFFS2 based Root file System */ +- reg = <0x01100000 0x00f00000>; +- label = "NAND Writable User area"; +- }; +- }; +- +-}; +- +-&soc { +- i2c@3000 { +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +- }; +- +- spi@7000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; /* input clock */ +- +- partition@u-boot { +- /* 512KB for u-boot Bootloader Image */ +- reg = <0x0 0x00080000>; +- label = "u-boot"; +- read-only; +- }; +- +- partition@dtb { +- /* 512KB for DTB Image */ +- reg = <0x00080000 0x00080000>; +- label = "dtb"; +- }; +- +- partition@kernel { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00100000 0x00400000>; +- label = "kernel"; +- }; +- +- partition@fs { +- /* 4MB for Compressed RFS Image */ +- reg = <0x00500000 0x00400000>; +- label = "file system"; +- }; +- +- partition@jffs-fs { +- /* 7MB for JFFS2 based RFS */ +- reg = <0x00900000 0x00700000>; +- label = "file system jffs2"; +- }; +- }; +- }; +- +- usb@22000 { +- phy_type = "ulpi"; +- }; +- +- /* USB2 is shared with localbus, so it must be disabled +- by default. We can't put 'status = "disabled";' here +- since U-Boot doesn't clear the status property when +- it enables USB2. OTOH, U-Boot does create a new node +- when there isn't any. So, just comment it out. +- usb@23000 { +- phy_type = "ulpi"; +- }; +- */ +- +- mdio@24000 { +- phy0: ethernet-phy@0 { +- interrupt-parent = <&mpic>; +- interrupts = <3 1>; +- reg = <0x0>; +- }; +- +- phy1: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <2 1>; +- reg = <0x1>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- mdio@25000 { +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- mdio@26000 { +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet0: ethernet@b0000 { +- fixed-link = <1 1 1000 0 0>; +- phy-connection-type = "rgmii-id"; +- +- }; +- +- enet1: ethernet@b1000 { +- phy-handle = <&phy0>; +- tbi-handle = <&tbi1>; +- phy-connection-type = "sgmii"; +- }; +- +- enet2: ethernet@b2000 { +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +- +- par_io@e0100 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xe0100 0x60>; +- ranges = <0x0 0xe0100 0x60>; +- device_type = "par_io"; +- num-ports = <3>; +- pio1: ucc_pin@1 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ +- 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ +- 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */ +- 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */ +- 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */ +- 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */ +- 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */ +- 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */ +- 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */ +- 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */ +- 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */ +- 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */ +- 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */ +- 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */ +- 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */ +- 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */ +- 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */ +- 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */ +- }; +- +- pio2: ucc_pin@2 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ +- 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ +- 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */ +- 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */ +- 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */ +- 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */ +- 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */ +- 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */ +- 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */ +- 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */ +- }; +- +- pio3: ucc_pin@3 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0x0 0x16 0x2 0x0 0x2 0x0 /* SER7_CD_B*/ +- 0x0 0x12 0x2 0x0 0x2 0x0 /* SER7_CTS_B*/ +- 0x0 0x13 0x1 0x0 0x2 0x0 /* SER7_RTS_B*/ +- 0x0 0x14 0x2 0x0 0x2 0x0 /* SER7_RXD0*/ +- 0x0 0x15 0x1 0x0 0x2 0x0>; /* SER7_TXD0*/ +- }; +- +- pio4: ucc_pin@4 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0x1 0x0 0x2 0x0 0x2 0x0 /* SER3_CD_B*/ +- 0x0 0x1c 0x2 0x0 0x2 0x0 /* SER3_CTS_B*/ +- 0x0 0x1d 0x1 0x0 0x2 0x0 /* SER3_RTS_B*/ +- 0x0 0x1e 0x2 0x0 0x2 0x0 /* SER3_RXD0*/ +- 0x0 0x1f 0x1 0x0 0x2 0x0>; /* SER3_TXD0*/ +- }; +- }; +-}; +- +-&qe { +- serial2: ucc@2600 { +- device_type = "serial"; +- compatible = "ucc_uart"; +- port-number = <0>; +- rx-clock-name = "brg6"; +- tx-clock-name = "brg6"; +- pio-handle = <&pio3>; +- }; +- +- serial3: ucc@2200 { +- device_type = "serial"; +- compatible = "ucc_uart"; +- port-number = <1>; +- rx-clock-name = "brg2"; +- tx-clock-name = "brg2"; +- pio-handle = <&pio4>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1025rdb_32b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1025rdb_32b.dts +deleted file mode 100644 +index ea33b57f8774..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1025rdb_32b.dts ++++ /dev/null +@@ -1,133 +0,0 @@ +-/* +- * P1025 RDB Device Tree Source (32-bit address map) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1021si-pre.dtsi" +-/ { +- model = "fsl,P1025RDB"; +- compatible = "fsl,P1025RDB"; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@ffe05000 { +- reg = <0 0xffe05000 0 0x1000>; +- +- /* NOR, NAND Flashes */ +- ranges = <0x0 0x0 0x0 0xef000000 0x01000000 +- 0x1 0x0 0x0 0xff800000 0x00040000>; +- }; +- +- soc: soc@ffe00000 { +- ranges = <0x0 0x0 0xffe00000 0x100000>; +- }; +- +- pci0: pcie@ffe09000 { +- ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; +- reg = <0 0xffe09000 0 0x1000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@ffe0a000 { +- reg = <0 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- qe: qe@ffe80000 { +- ranges = <0x0 0x0 0xffe80000 0x40000>; +- reg = <0 0xffe80000 0 0x480>; +- brg-frequency = <0>; +- bus-frequency = <0>; +- status = "disabled"; /* no firmware loaded */ +- +- enet3: ucc@2000 { +- device_type = "network"; +- compatible = "ucc_geth"; +- rx-clock-name = "clk12"; +- tx-clock-name = "clk9"; +- pio-handle = <&pio1>; +- phy-handle = <&qe_phy0>; +- phy-connection-type = "mii"; +- }; +- +- mdio@2120 { +- qe_phy0: ethernet-phy@0 { +- interrupt-parent = <&mpic>; +- interrupts = <4 1 0 0>; +- reg = <0x6>; +- }; +- qe_phy1: ethernet-phy@3 { +- interrupt-parent = <&mpic>; +- interrupts = <5 1 0 0>; +- reg = <0x3>; +- }; +- tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet4: ucc@2400 { +- device_type = "network"; +- compatible = "ucc_geth"; +- rx-clock-name = "none"; +- tx-clock-name = "clk13"; +- pio-handle = <&pio2>; +- phy-handle = <&qe_phy1>; +- phy-connection-type = "rmii"; +- }; +- }; +-}; +- +-/include/ "p1025rdb.dtsi" +-/include/ "p1021si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1025rdb_36b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1025rdb_36b.dts +deleted file mode 100644 +index b0ded5e8bd0b..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1025rdb_36b.dts ++++ /dev/null +@@ -1,93 +0,0 @@ +-/* +- * P1025 RDB Device Tree Source (36-bit address map) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1021si-pre.dtsi" +-/ { +- model = "fsl,P1025RDB"; +- compatible = "fsl,P1025RDB"; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@fffe05000 { +- reg = <0xf 0xffe05000 0 0x1000>; +- +- /* NOR, NAND Flashes */ +- ranges = <0x0 0x0 0xf 0xef000000 0x01000000 +- 0x1 0x0 0xf 0xff800000 0x00040000>; +- }; +- +- soc: soc@fffe00000 { +- ranges = <0x0 0xf 0xffe00000 0x100000>; +- }; +- +- pci0: pcie@fffe09000 { +- reg = <0xf 0xffe09000 0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0xe 0x20000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@fffe0a000 { +- reg = <0xf 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- qe: qe@fffe80000 { +- status = "disabled"; /* no firmware loaded */ +- }; +- +-}; +- +-/include/ "p1025rdb.dtsi" +-/include/ "p1021si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1025twr.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p1025twr.dts +deleted file mode 100644 +index 9b8863b74b60..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1025twr.dts ++++ /dev/null +@@ -1,95 +0,0 @@ +-/* +- * P1025 TWR Device Tree Source (32-bit address map) +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p1021si-pre.dtsi" +-/ { +- model = "fsl,P1025"; +- compatible = "fsl,TWR-P1025"; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@ffe05000 { +- reg = <0 0xffe05000 0 0x1000>; +- +- /* NOR Flash and SSD1289 */ +- ranges = <0x0 0x0 0x0 0xec000000 0x04000000 +- 0x2 0x0 0x0 0xe0000000 0x00020000>; +- }; +- +- soc: soc@ffe00000 { +- ranges = <0x0 0x0 0xffe00000 0x100000>; +- }; +- +- pci0: pcie@ffe09000 { +- ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; +- reg = <0 0xffe09000 0 0x1000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci1: pcie@ffe0a000 { +- reg = <0 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- qe: qe@ffe80000 { +- ranges = <0x0 0x0 0xffe80000 0x40000>; +- reg = <0 0xffe80000 0 0x480>; +- brg-frequency = <0>; +- bus-frequency = <0>; +- }; +-}; +- +-/include/ "p1025twr.dtsi" +-/include/ "p1021si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p1025twr.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p1025twr.dtsi +deleted file mode 100644 +index ab75b8f29ae2..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p1025twr.dtsi ++++ /dev/null +@@ -1,292 +0,0 @@ +-/* +- * P1025 TWR Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/{ +- aliases { +- ethernet3 = &enet3; +- ethernet4 = &enet4; +- }; +-}; +- +-&lbc { +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x4000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 256KB for Vitesse 7385 Switch firmware */ +- reg = <0x0 0x00040000>; +- label = "NOR Vitesse-7385 Firmware"; +- read-only; +- }; +- +- partition@40000 { +- /* 256KB for DTB Image */ +- reg = <0x00040000 0x00040000>; +- label = "NOR DTB Image"; +- }; +- +- partition@80000 { +- /* 5.5 MB for Linux Kernel Image */ +- reg = <0x00080000 0x00580000>; +- label = "NOR Linux Kernel Image"; +- }; +- +- partition@400000 { +- /* 56.75MB for Root file System */ +- reg = <0x00600000 0x038c0000>; +- label = "NOR Root File System"; +- }; +- +- partition@ec0000 { +- /* This location must not be altered */ +- /* 256KB for QE ucode firmware*/ +- reg = <0x03ec0000 0x00040000>; +- label = "NOR QE microcode firmware"; +- read-only; +- }; +- +- partition@f00000 { +- /* This location must not be altered */ +- /* 512KB for u-boot Bootloader Image */ +- /* 512KB for u-boot Environment Variables */ +- reg = <0x03f00000 0x00100000>; +- label = "NOR U-Boot Image"; +- read-only; +- }; +- }; +- +- /* CS2 for Display */ +- display@2,0 { +- compatible = "solomon,ssd1289fb"; +- reg = <0x2 0x0000 0x0004>; +- }; +- +-}; +- +-&soc { +- usb@22000 { +- phy_type = "ulpi"; +- }; +- +- mdio@24000 { +- phy0: ethernet-phy@2 { +- interrupt-parent = <&mpic>; +- interrupts = <1 1 0 0>; +- reg = <0x2>; +- }; +- +- phy1: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <2 1 0 0>; +- reg = <0x1>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- mdio@25000 { +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- mdio@26000 { +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- ptp_clock@b0e00 { +- compatible = "fsl,etsec-ptp"; +- reg = <0xb0e00 0xb0>; +- interrupts = <68 2 0 0 69 2 0 0>; +- fsl,tclk-period = <10>; +- fsl,tmr-prsc = <2>; +- fsl,tmr-add = <0xc0000021>; +- fsl,tmr-fiper1 = <999999990>; +- fsl,tmr-fiper2 = <99990>; +- fsl,max-adj = <133333332>; +- }; +- +- enet0: ethernet@b0000 { +- phy-handle = <&phy0>; +- phy-connection-type = "rgmii-id"; +- +- }; +- +- enet1: ethernet@b1000 { +- status = "disabled"; +- }; +- +- enet2: ethernet@b2000 { +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +- +- par_io@e0100 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xe0100 0x60>; +- ranges = <0x0 0xe0100 0x60>; +- device_type = "par_io"; +- num-ports = <3>; +- pio1: ucc_pin@1 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ +- 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ +- 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */ +- 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */ +- 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */ +- 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */ +- 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */ +- 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */ +- 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */ +- 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */ +- 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */ +- 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */ +- 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */ +- 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */ +- 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */ +- 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */ +- 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */ +- 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */ +- }; +- +- pio2: ucc_pin@2 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ +- 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ +- 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */ +- 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */ +- 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */ +- 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */ +- 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */ +- 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */ +- 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */ +- 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */ +- }; +- +- pio3: ucc_pin@3 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0x0 0x16 0x2 0x0 0x2 0x0 /* SER7_CD_B*/ +- 0x0 0x12 0x2 0x0 0x2 0x0 /* SER7_CTS_B*/ +- 0x0 0x13 0x1 0x0 0x2 0x0 /* SER7_RTS_B*/ +- 0x0 0x14 0x2 0x0 0x2 0x0 /* SER7_RXD0*/ +- 0x0 0x15 0x1 0x0 0x2 0x0>; /* SER7_TXD0*/ +- }; +- +- pio4: ucc_pin@4 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0x1 0x0 0x2 0x0 0x2 0x0 /* SER3_CD_B*/ +- 0x0 0x1c 0x2 0x0 0x2 0x0 /* SER3_CTS_B*/ +- 0x0 0x1d 0x1 0x0 0x2 0x0 /* SER3_RTS_B*/ +- 0x0 0x1e 0x2 0x0 0x2 0x0 /* SER3_RXD0*/ +- 0x0 0x1f 0x1 0x0 0x2 0x0>; /* SER3_TXD0*/ +- }; +- }; +-}; +- +-&qe { +- enet3: ucc@2000 { +- device_type = "network"; +- compatible = "ucc_geth"; +- rx-clock-name = "clk12"; +- tx-clock-name = "clk9"; +- pio-handle = <&pio1>; +- phy-handle = <&qe_phy0>; +- phy-connection-type = "mii"; +- }; +- +- mdio@2120 { +- qe_phy0: ethernet-phy@18 { +- interrupt-parent = <&mpic>; +- interrupts = <4 1 0 0>; +- reg = <0x18>; +- device_type = "ethernet-phy"; +- }; +- qe_phy1: ethernet-phy@19 { +- interrupt-parent = <&mpic>; +- interrupts = <5 1 0 0>; +- reg = <0x19>; +- device_type = "ethernet-phy"; +- }; +- tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet4: ucc@2400 { +- device_type = "network"; +- compatible = "ucc_geth"; +- rx-clock-name = "none"; +- tx-clock-name = "clk13"; +- pio-handle = <&pio2>; +- phy-handle = <&qe_phy1>; +- phy-connection-type = "rmii"; +- }; +- +- serial2: ucc@2600 { +- device_type = "serial"; +- compatible = "ucc_uart"; +- port-number = <0>; +- rx-clock-name = "brg6"; +- tx-clock-name = "brg6"; +- pio-handle = <&pio3>; +- }; +- +- serial3: ucc@2200 { +- device_type = "serial"; +- compatible = "ucc_uart"; +- port-number = <1>; +- rx-clock-name = "brg2"; +- tx-clock-name = "brg2"; +- pio-handle = <&pio4>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p2020ds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p2020ds.dts +deleted file mode 100644 +index ae380ebe55cf..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p2020ds.dts ++++ /dev/null +@@ -1,85 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * P2020 DS Device Tree Source +- * +- * Copyright 2009-2011 Freescale Semiconductor Inc. +- */ +- +-/include/ "p2020si-pre.dtsi" +- +-/ { +- model = "fsl,P2020DS"; +- compatible = "fsl,P2020DS"; +- +- memory { +- device_type = "memory"; +- }; +- +- board_lbc: lbc: localbus@ffe05000 { +- ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 +- 0x1 0x0 0x0 0xe0000000 0x08000000 +- 0x2 0x0 0x0 0xffa00000 0x00040000 +- 0x3 0x0 0x0 0xffdf0000 0x00008000 +- 0x4 0x0 0x0 0xffa40000 0x00040000 +- 0x5 0x0 0x0 0xffa80000 0x00040000 +- 0x6 0x0 0x0 0xffac0000 0x00040000>; +- reg = <0 0xffe05000 0 0x1000>; +- }; +- +- board_soc: soc: soc@ffe00000 { +- ranges = <0x0 0x0 0xffe00000 0x100000>; +- }; +- +- pci2: pcie@ffe08000 { +- ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; +- reg = <0 0xffe08000 0 0x1000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x10000>; +- }; +- }; +- +- board_pci1: pci1: pcie@ffe09000 { +- ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; +- reg = <0 0xffe09000 0 0x1000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x10000>; +- }; +- }; +- +- pci0: pcie@ffe0a000 { +- ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; +- reg = <0 0xffe0a000 0 0x1000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xc0000000 +- 0x2000000 0x0 0xc0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x10000>; +- }; +- }; +-}; +- +-/* +- * p2020ds.dtsi must be last to ensure board_pci0 overrides pci0 settings +- * for interrupt-map & interrupt-map-mask +- */ +- +-/include/ "p2020si-post.dtsi" +-/include/ "p2020ds.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p2020ds.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p2020ds.dtsi +deleted file mode 100644 +index e699cf95b063..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p2020ds.dtsi ++++ /dev/null +@@ -1,327 +0,0 @@ +-/* +- * P2020DS Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2011-2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&board_lbc { +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- bank-width = <2>; +- device-width = <1>; +- +- ramdisk@0 { +- reg = <0x0 0x03000000>; +- read-only; +- }; +- +- diagnostic@3000000 { +- reg = <0x03000000 0x00e00000>; +- read-only; +- }; +- +- dink@3e00000 { +- reg = <0x03e00000 0x00200000>; +- read-only; +- }; +- +- kernel@4000000 { +- reg = <0x04000000 0x00400000>; +- read-only; +- }; +- +- jffs2@4400000 { +- reg = <0x04400000 0x03b00000>; +- }; +- +- dtb@7f00000 { +- reg = <0x07f00000 0x00080000>; +- read-only; +- }; +- +- u-boot@7f80000 { +- reg = <0x07f80000 0x00080000>; +- read-only; +- }; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,elbc-fcm-nand"; +- reg = <0x2 0x0 0x40000>; +- +- u-boot@0 { +- reg = <0x0 0x02000000>; +- read-only; +- }; +- +- jffs2@2000000 { +- reg = <0x02000000 0x10000000>; +- }; +- +- ramdisk@12000000 { +- reg = <0x12000000 0x08000000>; +- read-only; +- }; +- +- kernel@1a000000 { +- reg = <0x1a000000 0x04000000>; +- }; +- +- dtb@1e000000 { +- reg = <0x1e000000 0x01000000>; +- read-only; +- }; +- +- empty@1f000000 { +- reg = <0x1f000000 0x21000000>; +- }; +- }; +- +- board-control@3,0 { +- compatible = "fsl,p2020ds-fpga", "fsl,fpga-ngpixis"; +- reg = <0x3 0x0 0x30>; +- }; +- +- nand@4,0 { +- compatible = "fsl,elbc-fcm-nand"; +- reg = <0x4 0x0 0x40000>; +- }; +- +- nand@5,0 { +- compatible = "fsl,elbc-fcm-nand"; +- reg = <0x5 0x0 0x40000>; +- }; +- +- nand@6,0 { +- compatible = "fsl,elbc-fcm-nand"; +- reg = <0x6 0x0 0x40000>; +- }; +-}; +- +-&board_soc { +- usb@22000 { +- phy_type = "ulpi"; +- dr_mode = "host"; +- }; +- +- mdio@24520 { +- phy0: ethernet-phy@0 { +- interrupts = <3 1 0 0>; +- reg = <0x0>; +- }; +- phy1: ethernet-phy@1 { +- interrupts = <3 1 0 0>; +- reg = <0x1>; +- }; +- phy2: ethernet-phy@2 { +- interrupts = <3 1 0 0>; +- reg = <0x2>; +- }; +- +- sgmii_phy1: sgmii-phy@1 { +- interrupts = <5 1 0 0>; +- reg = <0x1c>; +- }; +- sgmii_phy2: sgmii-phy@2 { +- interrupts = <5 1 0 0>; +- reg = <0x1d>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- +- }; +- +- mdio@25520 { +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- mdio@26520 { +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- +- }; +- +- ptp_clock@24e00 { +- fsl,tclk-period = <5>; +- fsl,tmr-prsc = <200>; +- fsl,tmr-add = <0xCCCCCCCD>; +- fsl,tmr-fiper1 = <0x3B9AC9FB>; +- fsl,tmr-fiper2 = <0x0001869B>; +- fsl,max-adj = <249999999>; +- }; +- +- enet0: ethernet@24000 { +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- phy-connection-type = "rgmii-id"; +- }; +- +- enet1: ethernet@25000 { +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- +- }; +- +- enet2: ethernet@26000 { +- tbi-handle = <&tbi2>; +- phy-handle = <&phy2>; +- phy-connection-type = "rgmii-id"; +- }; +-}; +- +-&board_pci1 { +- pcie@0 { +- interrupt-map-mask = <0xff00 0x0 0x0 0x7>; +- interrupt-map = < +- +- // IDSEL 0x11 func 0 - PCI slot 1 +- 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2 +- 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2 +- +- // IDSEL 0x11 func 1 - PCI slot 1 +- 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2 +- 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2 +- +- // IDSEL 0x11 func 2 - PCI slot 1 +- 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2 +- 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2 +- +- // IDSEL 0x11 func 3 - PCI slot 1 +- 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2 +- 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2 +- +- // IDSEL 0x11 func 4 - PCI slot 1 +- 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2 +- 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2 +- +- // IDSEL 0x11 func 5 - PCI slot 1 +- 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2 +- 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2 +- +- // IDSEL 0x11 func 6 - PCI slot 1 +- 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2 +- 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2 +- +- // IDSEL 0x11 func 7 - PCI slot 1 +- 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2 +- 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2 +- +- // IDSEL 0x1d Audio +- 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2 +- +- // IDSEL 0x1e Legacy +- 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2 +- 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2 +- +- // IDSEL 0x1f IDE/SATA +- 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2 +- 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2 +- >; +- +- uli1575@0 { +- reg = <0x0 0x0 0x0 0x0 0x0>; +- #size-cells = <2>; +- #address-cells = <3>; +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x10000>; +- isa@1e { +- device_type = "isa"; +- #interrupt-cells = <2>; +- #size-cells = <1>; +- #address-cells = <2>; +- reg = <0xf000 0x0 0x0 0x0 0x0>; +- ranges = <0x1 0x0 0x1000000 0x0 0x0 +- 0x1000>; +- interrupt-parent = <&i8259>; +- +- i8259: interrupt-controller@20 { +- reg = <0x1 0x20 0x2 +- 0x1 0xa0 0x2 +- 0x1 0x4d0 0x2>; +- interrupt-controller; +- device_type = "interrupt-controller"; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- compatible = "chrp,iic"; +- interrupts = <4 1 0 0>; +- interrupt-parent = <&mpic>; +- }; +- +- i8042@60 { +- #size-cells = <0>; +- #address-cells = <1>; +- reg = <0x1 0x60 0x1 0x1 0x64 0x1>; +- interrupts = <1 3 12 3>; +- interrupt-parent = +- <&i8259>; +- +- keyboard@0 { +- reg = <0x0>; +- compatible = "pnpPNP,303"; +- }; +- +- mouse@1 { +- reg = <0x1>; +- compatible = "pnpPNP,f03"; +- }; +- }; +- +- rtc@70 { +- compatible = "pnpPNP,b00"; +- reg = <0x1 0x70 0x2>; +- }; +- +- gpio@400 { +- reg = <0x1 0x400 0x80>; +- }; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p2020rdb-pc.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p2020rdb-pc.dtsi +deleted file mode 100644 +index 03c9afc82436..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p2020rdb-pc.dtsi ++++ /dev/null +@@ -1,241 +0,0 @@ +-/* +- * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&lbc { +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x1000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 256KB for Vitesse 7385 Switch firmware */ +- reg = <0x0 0x00040000>; +- label = "NOR Vitesse-7385 Firmware"; +- read-only; +- }; +- +- partition@40000 { +- /* 256KB for DTB Image */ +- reg = <0x00040000 0x00040000>; +- label = "NOR DTB Image"; +- }; +- +- partition@80000 { +- /* 3.5 MB for Linux Kernel Image */ +- reg = <0x00080000 0x00380000>; +- label = "NOR Linux Kernel Image"; +- }; +- +- partition@400000 { +- /* 11MB for JFFS2 based Root file System */ +- reg = <0x00400000 0x00b00000>; +- label = "NOR JFFS2 Root File System"; +- }; +- +- partition@f00000 { +- /* This location must not be altered */ +- /* 512KB for u-boot Bootloader Image */ +- /* 512KB for u-boot Environment Variables */ +- reg = <0x00f00000 0x00100000>; +- label = "NOR U-Boot Image"; +- read-only; +- }; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,p2020-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x1 0x0 0x40000>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 1MB for u-boot Bootloader Image */ +- reg = <0x0 0x00100000>; +- label = "NAND U-Boot Image"; +- read-only; +- }; +- +- partition@100000 { +- /* 1MB for DTB Image */ +- reg = <0x00100000 0x00100000>; +- label = "NAND DTB Image"; +- }; +- +- partition@200000 { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00200000 0x00400000>; +- label = "NAND Linux Kernel Image"; +- }; +- +- partition@600000 { +- /* 4MB for Compressed Root file System Image */ +- reg = <0x00600000 0x00400000>; +- label = "NAND Compressed RFS Image"; +- }; +- +- partition@a00000 { +- /* 7MB for JFFS2 based Root file System */ +- reg = <0x00a00000 0x00700000>; +- label = "NAND JFFS2 Root File System"; +- }; +- +- partition@1100000 { +- /* 15MB for JFFS2 based Root file System */ +- reg = <0x01100000 0x00f00000>; +- label = "NAND Writable User area"; +- }; +- }; +- +- L2switch@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "vitesse-7385"; +- reg = <0x2 0x0 0x20000>; +- }; +- +- cpld@3,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cpld"; +- reg = <0x3 0x0 0x20000>; +- read-only; +- }; +-}; +- +-&soc { +- i2c@3000 { +- rtc@68 { +- compatible = "pericom,pt7c4338"; +- reg = <0x68>; +- }; +- }; +- +- spi@7000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,m25p80", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; +- +- partition@0 { +- /* 512KB for u-boot Bootloader Image */ +- reg = <0x0 0x00080000>; +- label = "SPI U-Boot Image"; +- read-only; +- }; +- +- partition@80000 { +- /* 512KB for DTB Image */ +- reg = <0x00080000 0x00080000>; +- label = "SPI DTB Image"; +- }; +- +- partition@100000 { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00100000 0x00400000>; +- label = "SPI Linux Kernel Image"; +- }; +- +- partition@500000 { +- /* 4MB for Compressed RFS Image */ +- reg = <0x00500000 0x00400000>; +- label = "SPI Compressed RFS Image"; +- }; +- +- partition@900000 { +- /* 7MB for JFFS2 based RFS */ +- reg = <0x00900000 0x00700000>; +- label = "SPI JFFS2 RFS"; +- }; +- }; +- }; +- +- usb@22000 { +- phy_type = "ulpi"; +- }; +- +- mdio@24520 { +- phy0: ethernet-phy@0 { +- interrupts = <3 1 0 0>; +- reg = <0x0>; +- }; +- phy1: ethernet-phy@1 { +- interrupts = <2 1 0 0>; +- reg = <0x1>; +- }; +- }; +- +- mdio@25520 { +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- mdio@26520 { +- status = "disabled"; +- }; +- +- ptp_clock@24e00 { +- fsl,tclk-period = <5>; +- fsl,tmr-prsc = <2>; +- fsl,tmr-add = <0xaaaaaaab>; +- fsl,tmr-fiper1 = <999999995>; +- fsl,tmr-fiper2 = <99990>; +- fsl,max-adj = <299999999>; +- }; +- +- enet0: ethernet@24000 { +- fixed-link = <1 1 1000 0 0>; +- phy-connection-type = "rgmii-id"; +- }; +- +- enet1: ethernet@25000 { +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- phy-connection-type = "sgmii"; +- }; +- +- enet2: ethernet@26000 { +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p2020rdb-pc_32b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p2020rdb-pc_32b.dts +deleted file mode 100644 +index d3295c204bbf..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p2020rdb-pc_32b.dts ++++ /dev/null +@@ -1,96 +0,0 @@ +-/* +- * P2020 RDB-PC 32Bit Physical Address Map Device Tree Source +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p2020si-pre.dtsi" +- +-/ { +- model = "fsl,P2020RDB"; +- compatible = "fsl,P2020RDB-PC"; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@ffe05000 { +- reg = <0 0xffe05000 0 0x1000>; +- +- /* NOR and NAND Flashes */ +- ranges = <0x0 0x0 0x0 0xef000000 0x01000000 +- 0x1 0x0 0x0 0xff800000 0x00040000 +- 0x2 0x0 0x0 0xffb00000 0x00020000 +- 0x3 0x0 0x0 0xffa00000 0x00020000>; +- }; +- +- soc: soc@ffe00000 { +- ranges = <0x0 0x0 0xffe00000 0x100000>; +- }; +- +- pci2: pcie@ffe08000 { +- reg = <0 0xffe08000 0 0x1000>; +- status = "disabled"; +- }; +- +- pci1: pcie@ffe09000 { +- reg = <0 0xffe09000 0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci0: pcie@ffe0a000 { +- reg = <0 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/include/ "p2020rdb-pc.dtsi" +-/include/ "p2020si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p2020rdb-pc_36b.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p2020rdb-pc_36b.dts +deleted file mode 100644 +index 9307a8f41ddb..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p2020rdb-pc_36b.dts ++++ /dev/null +@@ -1,96 +0,0 @@ +-/* +- * P2020 RDB-PC 36Bit Physical Address Map Device Tree Source +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p2020si-pre.dtsi" +- +-/ { +- model = "fsl,P2020RDB"; +- compatible = "fsl,P2020RDB-PC"; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@fffe05000 { +- reg = <0xf 0xffe05000 0 0x1000>; +- +- /* NOR and NAND Flashes */ +- ranges = <0x0 0x0 0xf 0xef000000 0x01000000 +- 0x1 0x0 0xf 0xff800000 0x00040000 +- 0x2 0x0 0xf 0xffb00000 0x00020000 +- 0x3 0x0 0xf 0xffa00000 0x00020000>; +- }; +- +- soc: soc@fffe00000 { +- ranges = <0x0 0xf 0xffe00000 0x100000>; +- }; +- +- pci2: pcie@fffe08000 { +- reg = <0xf 0xffe08000 0 0x1000>; +- status = "disabled"; +- }; +- +- pci1: pcie@fffe09000 { +- reg = <0xf 0xffe09000 0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci0: pcie@fffe0a000 { +- reg = <0xf 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xe0000000 +- 0x2000000 0x0 0xe0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/include/ "p2020rdb-pc.dtsi" +-/include/ "p2020si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p2020rdb.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p2020rdb.dts +deleted file mode 100644 +index 3acd3890b397..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p2020rdb.dts ++++ /dev/null +@@ -1,287 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * P2020 RDB Device Tree Source +- * +- * Copyright 2009-2012 Freescale Semiconductor Inc. +- */ +- +-/include/ "p2020si-pre.dtsi" +- +-/ { +- model = "fsl,P2020RDB"; +- compatible = "fsl,P2020RDB"; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- pci1 = &pci1; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- lbc: localbus@ffe05000 { +- reg = <0 0xffe05000 0 0x1000>; +- +- /* NOR and NAND Flashes */ +- ranges = <0x0 0x0 0x0 0xef000000 0x01000000 +- 0x1 0x0 0x0 0xffa00000 0x00040000 +- 0x2 0x0 0x0 0xffb00000 0x00020000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x1000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 256KB for Vitesse 7385 Switch firmware */ +- reg = <0x0 0x00040000>; +- label = "NOR (RO) Vitesse-7385 Firmware"; +- read-only; +- }; +- +- partition@40000 { +- /* 256KB for DTB Image */ +- reg = <0x00040000 0x00040000>; +- label = "NOR (RO) DTB Image"; +- read-only; +- }; +- +- partition@80000 { +- /* 3.5 MB for Linux Kernel Image */ +- reg = <0x00080000 0x00380000>; +- label = "NOR (RO) Linux Kernel Image"; +- read-only; +- }; +- +- partition@400000 { +- /* 11MB for JFFS2 based Root file System */ +- reg = <0x00400000 0x00b00000>; +- label = "NOR (RW) JFFS2 Root File System"; +- }; +- +- partition@f00000 { +- /* This location must not be altered */ +- /* 512KB for u-boot Bootloader Image */ +- /* 512KB for u-boot Environment Variables */ +- reg = <0x00f00000 0x00100000>; +- label = "NOR (RO) U-Boot Image"; +- read-only; +- }; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,p2020-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x1 0x0 0x40000>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 1MB for u-boot Bootloader Image */ +- reg = <0x0 0x00100000>; +- label = "NAND (RO) U-Boot Image"; +- read-only; +- }; +- +- partition@100000 { +- /* 1MB for DTB Image */ +- reg = <0x00100000 0x00100000>; +- label = "NAND (RO) DTB Image"; +- read-only; +- }; +- +- partition@200000 { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00200000 0x00400000>; +- label = "NAND (RO) Linux Kernel Image"; +- read-only; +- }; +- +- partition@600000 { +- /* 4MB for Compressed Root file System Image */ +- reg = <0x00600000 0x00400000>; +- label = "NAND (RO) Compressed RFS Image"; +- read-only; +- }; +- +- partition@a00000 { +- /* 7MB for JFFS2 based Root file System */ +- reg = <0x00a00000 0x00700000>; +- label = "NAND (RW) JFFS2 Root File System"; +- }; +- +- partition@1100000 { +- /* 15MB for JFFS2 based Root file System */ +- reg = <0x01100000 0x00f00000>; +- label = "NAND (RW) Writable User area"; +- }; +- }; +- +- L2switch@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "vitesse-7385"; +- reg = <0x2 0x0 0x20000>; +- }; +- +- }; +- +- soc: soc@ffe00000 { +- ranges = <0x0 0x0 0xffe00000 0x100000>; +- +- i2c@3000 { +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +- }; +- +- spi@7000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; +- +- partition@0 { +- /* 512KB for u-boot Bootloader Image */ +- reg = <0x0 0x00080000>; +- label = "SPI (RO) U-Boot Image"; +- read-only; +- }; +- +- partition@80000 { +- /* 512KB for DTB Image */ +- reg = <0x00080000 0x00080000>; +- label = "SPI (RO) DTB Image"; +- read-only; +- }; +- +- partition@100000 { +- /* 4MB for Linux Kernel Image */ +- reg = <0x00100000 0x00400000>; +- label = "SPI (RO) Linux Kernel Image"; +- read-only; +- }; +- +- partition@500000 { +- /* 4MB for Compressed RFS Image */ +- reg = <0x00500000 0x00400000>; +- label = "SPI (RO) Compressed RFS Image"; +- read-only; +- }; +- +- partition@900000 { +- /* 7MB for JFFS2 based RFS */ +- reg = <0x00900000 0x00700000>; +- label = "SPI (RW) JFFS2 RFS"; +- }; +- }; +- }; +- +- usb@22000 { +- phy_type = "ulpi"; +- dr_mode = "host"; +- }; +- +- mdio@24520 { +- phy0: ethernet-phy@0 { +- interrupts = <3 1 0 0>; +- reg = <0x0>; +- }; +- phy1: ethernet-phy@1 { +- interrupts = <3 1 0 0>; +- reg = <0x1>; +- }; +- tbi-phy@2 { +- device_type = "tbi-phy"; +- reg = <0x2>; +- }; +- }; +- +- mdio@25520 { +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- mdio@26520 { +- status = "disabled"; +- }; +- +- ptp_clock@24e00 { +- fsl,tclk-period = <5>; +- fsl,tmr-prsc = <200>; +- fsl,tmr-add = <0xCCCCCCCD>; +- fsl,tmr-fiper1 = <0x3B9AC9FB>; +- fsl,tmr-fiper2 = <0x0001869B>; +- fsl,max-adj = <249999999>; +- }; +- +- enet0: ethernet@24000 { +- fixed-link = <1 1 1000 0 0>; +- phy-connection-type = "rgmii-id"; +- }; +- +- enet1: ethernet@25000 { +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- phy-connection-type = "sgmii"; +- }; +- +- enet2: ethernet@26000 { +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- }; +- }; +- +- pci0: pcie@ffe08000 { +- reg = <0 0xffe08000 0 0x1000>; +- status = "disabled"; +- }; +- +- pci1: pcie@ffe09000 { +- reg = <0 0xffe09000 0 0x1000>; +- ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0xa0000000 +- 0x2000000 0x0 0xa0000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- pci2: pcie@ffe0a000 { +- reg = <0 0xffe0a000 0 0x1000>; +- ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; +- pcie@0 { +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x20000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +- +-/include/ "p2020si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p2020si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p2020si-post.dtsi +deleted file mode 100644 +index 884e01bcb243..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p2020si-post.dtsi ++++ /dev/null +@@ -1,201 +0,0 @@ +-/* +- * P2020/P2010 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&lbc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus"; +- interrupts = <19 2 0 0>; +-}; +- +-/* controller at 0xa000 */ +-&pci0 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <26 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <26 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 +- >; +- }; +-}; +- +-/* controller at 0x9000 */ +-&pci1 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <25 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <25 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 +- >; +- }; +-}; +- +-/* controller at 0x8000 */ +-&pci2 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupts = <24 2 0 0>; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <24 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0 +- 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0 +- 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0 +- 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0 +- >; +- }; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,p2020-immr", "simple-bus"; +- bus-frequency = <0>; // Filled out by uboot. +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <12>; +- }; +- +- ecm@1000 { +- compatible = "fsl,p2020-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2 0 0>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,p2020-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupts = <18 2 0 0>; +- }; +- +-/include/ "pq3-i2c-0.dtsi" +-/include/ "pq3-i2c-1.dtsi" +-/include/ "pq3-duart-0.dtsi" +-/include/ "pq3-espi-0.dtsi" +- spi0: spi@7000 { +- fsl,espi-num-chipselects = <4>; +- }; +- +-/include/ "pq3-dma-1.dtsi" +-/include/ "pq3-gpio-0.dtsi" +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,p2020-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x80000>; // L2,512K +- interrupts = <16 2 0 0>; +- }; +- +-/include/ "pq3-dma-0.dtsi" +-/include/ "pq3-usb2-dr-0.dtsi" +- usb@22000 { +- compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; +- }; +-/include/ "pq3-etsec1-0.dtsi" +-/include/ "pq3-etsec1-timer-0.dtsi" +- +- ptp_clock@24e00 { +- interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>; +- }; +- +- +-/include/ "pq3-etsec1-1.dtsi" +-/include/ "pq3-etsec1-2.dtsi" +-/include/ "pq3-esdhc-0.dtsi" +- sdhc@2e000 { +- compatible = "fsl,p2020-esdhc", "fsl,esdhc"; +- }; +- +-/include/ "pq3-sec3.1-0.dtsi" +-/include/ "pq3-mpic.dtsi" +-/include/ "pq3-mpic-timer-B.dtsi" +- +- global-utilities@e0000 { +- compatible = "fsl,p2020-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p2020si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p2020si-pre.dtsi +deleted file mode 100644 +index 42bf3c6d25ca..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p2020si-pre.dtsi ++++ /dev/null +@@ -1,72 +0,0 @@ +-/* +- * P2020/P2010 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e500v2_power_isa.dtsi" +- +-/ { +- compatible = "fsl,P2020"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,P2020@0 { +- device_type = "cpu"; +- reg = <0x0>; +- next-level-cache = <&L2>; +- }; +- +- PowerPC,P2020@1 { +- device_type = "cpu"; +- reg = <0x1>; +- next-level-cache = <&L2>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p2041rdb.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p2041rdb.dts +deleted file mode 100644 +index 950816b9d6e1..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p2041rdb.dts ++++ /dev/null +@@ -1,340 +0,0 @@ +-/* +- * P2041RDB Device Tree Source +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p2041si-pre.dtsi" +- +-/ { +- model = "fsl,P2041RDB"; +- compatible = "fsl,P2041RDB"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- phy_rgmii_0 = &phy_rgmii_0; +- phy_rgmii_1 = &phy_rgmii_1; +- phy_sgmii_2 = &phy_sgmii_2; +- phy_sgmii_3 = &phy_sgmii_3; +- phy_sgmii_4 = &phy_sgmii_4; +- phy_sgmii_1c = &phy_sgmii_1c; +- phy_sgmii_1d = &phy_sgmii_1d; +- phy_sgmii_1e = &phy_sgmii_1e; +- phy_sgmii_1f = &phy_sgmii_1f; +- phy_xgmii_2 = &phy_xgmii_2; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01008000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x200000>; +- }; +- +- qportals: qman-portals@ff4200000 { +- ranges = <0x0 0xf 0xf4200000 0x200000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- spi@110000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; /* input clock */ +- partition@u-boot { +- label = "u-boot"; +- reg = <0x00000000 0x00100000>; +- read-only; +- }; +- partition@kernel { +- label = "kernel"; +- reg = <0x00100000 0x00500000>; +- read-only; +- }; +- partition@dtb { +- label = "dtb"; +- reg = <0x00600000 0x00100000>; +- read-only; +- }; +- partition@fs { +- label = "file system"; +- reg = <0x00700000 0x00900000>; +- }; +- }; +- }; +- +- i2c@118000 { +- lm75b@48 { +- compatible = "nxp,lm75a"; +- reg = <0x48>; +- }; +- eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- }; +- rtc@68 { +- compatible = "pericom,pt7c4338"; +- reg = <0x68>; +- }; +- adt7461@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- }; +- +- i2c@118100 { +- eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- }; +- }; +- +- usb1: usb@211000 { +- dr_mode = "host"; +- }; +- +- fman@400000 { +- ethernet@e0000 { +- phy-handle = <&phy_sgmii_2>; +- phy-connection-type = "sgmii"; +- }; +- +- mdio@e1120 { +- phy_rgmii_0: ethernet-phy@0 { +- reg = <0x0>; +- }; +- +- phy_rgmii_1: ethernet-phy@1 { +- reg = <0x1>; +- }; +- +- phy_sgmii_2: ethernet-phy@2 { +- reg = <0x2>; +- }; +- +- phy_sgmii_3: ethernet-phy@3 { +- reg = <0x3>; +- }; +- +- phy_sgmii_4: ethernet-phy@4 { +- reg = <0x4>; +- }; +- +- phy_sgmii_1c: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy_sgmii_1d: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy_sgmii_1e: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy_sgmii_1f: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- +- ethernet@e2000 { +- phy-handle = <&phy_sgmii_3>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e4000 { +- phy-handle = <&phy_sgmii_4>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e6000 { +- phy-handle = <&phy_rgmii_1>; +- phy-connection-type = "rgmii"; +- }; +- +- ethernet@e8000 { +- phy-handle = <&phy_rgmii_0>; +- phy-connection-type = "rgmii"; +- }; +- +- ethernet@f0000 { +- phy-handle = <&phy_xgmii_2>; +- phy-connection-type = "xgmii"; +- }; +- +- mdio@f1000 { +- phy_xgmii_2: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x0>; +- }; +- }; +- }; +- }; +- +- rio: rapidio@ffe0c0000 { +- reg = <0xf 0xfe0c0000 0 0x11000>; +- +- port1 { +- ranges = <0 0 0xc 0x20000000 0 0x10000000>; +- }; +- port2 { +- ranges = <0 0 0xc 0x30000000 0 0x10000000>; +- }; +- }; +- +- lbc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x1000>; +- ranges = <0 0 0xf 0xe8000000 0x08000000 +- 1 0 0xf 0xffa00000 0x00040000>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x08000000>; +- bank-width = <2>; +- device-width = <2>; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,elbc-fcm-nand"; +- reg = <0x1 0x0 0x40000>; +- +- partition@0 { +- label = "NAND U-Boot Image"; +- reg = <0x0 0x02000000>; +- read-only; +- }; +- +- partition@2000000 { +- label = "NAND Root File System"; +- reg = <0x02000000 0x10000000>; +- }; +- +- partition@12000000 { +- label = "NAND Compressed RFS Image"; +- reg = <0x12000000 0x08000000>; +- }; +- +- partition@1a000000 { +- label = "NAND Linux Kernel Image"; +- reg = <0x1a000000 0x04000000>; +- }; +- +- partition@1e000000 { +- label = "NAND DTB Image"; +- reg = <0x1e000000 0x01000000>; +- }; +- +- partition@1f000000 { +- label = "NAND Writable User area"; +- reg = <0x1f000000 0x01000000>; +- }; +- }; +- }; +- +- pci0: pcie@ffe200000 { +- reg = <0xf 0xfe200000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci1: pcie@ffe201000 { +- reg = <0xf 0xfe201000 0 0x1000>; +- ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 +- 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci2: pcie@ffe202000 { +- reg = <0xf 0xfe202000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +-}; +- +-/include/ "p2041si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p2041si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p2041si-post.dtsi +deleted file mode 100644 +index ddc018d42252..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p2041si-post.dtsi ++++ /dev/null +@@ -1,458 +0,0 @@ +-/* +- * P2041/P2040 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&bman_fbpr { +- compatible = "fsl,bman-fbpr"; +- alloc-ranges = <0 0 0x10 0>; +-}; +- +-&qman_fqd { +- compatible = "fsl,qman-fqd"; +- alloc-ranges = <0 0 0x10 0>; +-}; +- +-&qman_pfdr { +- compatible = "fsl,qman-pfdr"; +- alloc-ranges = <0 0 0x10 0>; +-}; +- +-&lbc { +- compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus"; +- interrupts = <25 2 0 0>; +- #address-cells = <2>; +- #size-cells = <1>; +-}; +- +-/* controller at 0x200000 */ +-&pci0 { +- compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 1 15>; +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */ +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 1 15>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 40 1 0 0 +- 0000 0 0 2 &mpic 1 1 0 0 +- 0000 0 0 3 &mpic 2 1 0 0 +- 0000 0 0 4 &mpic 3 1 0 0 +- >; +- }; +-}; +- +-/* controller at 0x201000 */ +-&pci1 { +- compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 1 14>; +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */ +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 1 14>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 41 1 0 0 +- 0000 0 0 2 &mpic 5 1 0 0 +- 0000 0 0 3 &mpic 6 1 0 0 +- 0000 0 0 4 &mpic 7 1 0 0 +- >; +- }; +-}; +- +-/* controller at 0x202000 */ +-&pci2 { +- compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 1 13>; +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */ +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 1 13>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 42 1 0 0 +- 0000 0 0 2 &mpic 9 1 0 0 +- 0000 0 0 3 &mpic 10 1 0 0 +- 0000 0 0 4 &mpic 11 1 0 0 +- >; +- }; +-}; +- +-&rio { +- compatible = "fsl,srio"; +- interrupts = <16 2 1 11>; +- #address-cells = <2>; +- #size-cells = <2>; +- fsl,iommu-parent = <&pamu0>; +- ranges; +- +- port1 { +- #address-cells = <2>; +- #size-cells = <2>; +- cell-index = <1>; +- fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */ +- }; +- +- port2 { +- #address-cells = <2>; +- #size-cells = <2>; +- cell-index = <2>; +- fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */ +- }; +-}; +- +-&dcsr { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,dcsr", "simple-bus"; +- +- dcsr-epu@0 { +- compatible = "fsl,p2041-dcsr-epu", "fsl,dcsr-epu"; +- interrupts = <52 2 0 0 +- 84 2 0 0 +- 85 2 0 0>; +- reg = <0x0 0x1000>; +- }; +- dcsr-npc { +- compatible = "fsl,dcsr-npc"; +- reg = <0x1000 0x1000 0x1000000 0x8000>; +- }; +- dcsr-nxc@2000 { +- compatible = "fsl,dcsr-nxc"; +- reg = <0x2000 0x1000>; +- }; +- dcsr-corenet { +- compatible = "fsl,dcsr-corenet"; +- reg = <0x8000 0x1000 0xB0000 0x1000>; +- }; +- dcsr-dpaa@9000 { +- compatible = "fsl,p2041-dcsr-dpaa", "fsl,dcsr-dpaa"; +- reg = <0x9000 0x1000>; +- }; +- dcsr-ocn@11000 { +- compatible = "fsl,p2041-dcsr-ocn", "fsl,dcsr-ocn"; +- reg = <0x11000 0x1000>; +- }; +- dcsr-ddr@12000 { +- compatible = "fsl,dcsr-ddr"; +- dev-handle = <&ddr1>; +- reg = <0x12000 0x1000>; +- }; +- dcsr-nal@18000 { +- compatible = "fsl,p2041-dcsr-nal", "fsl,dcsr-nal"; +- reg = <0x18000 0x1000>; +- }; +- dcsr-rcpm@22000 { +- compatible = "fsl,p2041-dcsr-rcpm", "fsl,dcsr-rcpm"; +- reg = <0x22000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@40000 { +- compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu0>; +- reg = <0x40000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@41000 { +- compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu1>; +- reg = <0x41000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@42000 { +- compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu2>; +- reg = <0x42000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@43000 { +- compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu3>; +- reg = <0x43000 0x1000>; +- }; +-}; +- +-/include/ "qoriq-bman1-portals.dtsi" +- +-/include/ "qoriq-qman1-portals.dtsi" +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- +- soc-sram-error { +- compatible = "fsl,soc-sram-error"; +- interrupts = <16 2 1 29>; +- }; +- +- corenet-law@0 { +- compatible = "fsl,corenet-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <32>; +- }; +- +- ddr1: memory-controller@8000 { +- compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; +- reg = <0x8000 0x1000>; +- interrupts = <16 2 1 23>; +- }; +- +- cpc: l3-cache-controller@10000 { +- compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache"; +- reg = <0x10000 0x1000>; +- interrupts = <16 2 1 27>; +- }; +- +- corenet-cf@18000 { +- compatible = "fsl,corenet1-cf", "fsl,corenet-cf"; +- reg = <0x18000 0x1000>; +- interrupts = <16 2 1 31>; +- fsl,ccf-num-csdids = <32>; +- fsl,ccf-num-snoopids = <32>; +- }; +- +- iommu@20000 { +- compatible = "fsl,pamu-v1.0", "fsl,pamu"; +- reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */ +- ranges = <0 0x20000 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupts = < +- 24 2 0 0 +- 16 2 1 30>; +- fsl,portid-mapping = <0x0f000000>; +- +- pamu0: pamu@0 { +- reg = <0 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- +- pamu1: pamu@1000 { +- reg = <0x1000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- +- pamu2: pamu@2000 { +- reg = <0x2000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- +- pamu3: pamu@3000 { +- reg = <0x3000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- }; +- +-/include/ "qoriq-mpic.dtsi" +- +- guts: global-utilities@e0000 { +- compatible = "fsl,qoriq-device-config-1.0"; +- reg = <0xe0000 0xe00>; +- fsl,has-rstcr; +- #sleep-cells = <1>; +- fsl,liodn-bits = <12>; +- }; +- +- pins: global-utilities@e0e00 { +- compatible = "fsl,qoriq-pin-control-1.0"; +- reg = <0xe0e00 0x200>; +- #sleep-cells = <2>; +- }; +- +-/include/ "qoriq-clockgen1.dtsi" +- global-utilities@e1000 { +- compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0"; +- }; +- +- rcpm: global-utilities@e2000 { +- compatible = "fsl,qoriq-rcpm-1.0"; +- reg = <0xe2000 0x1000>; +- #sleep-cells = <1>; +- }; +- +- sfp: sfp@e8000 { +- compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0"; +- reg = <0xe8000 0x1000>; +- }; +- +- serdes: serdes@ea000 { +- compatible = "fsl,p2041-serdes"; +- reg = <0xea000 0x1000>; +- }; +- +-/include/ "qoriq-dma-0.dtsi" +- dma@100300 { +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ +- }; +- +-/include/ "qoriq-dma-1.dtsi" +- dma@101300 { +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ +- }; +- +-/include/ "qoriq-espi-0.dtsi" +- spi@110000 { +- fsl,espi-num-chipselects = <4>; +- }; +- +-/include/ "qoriq-esdhc-0.dtsi" +- sdhc@114000 { +- compatible = "fsl,p2041-esdhc", "fsl,esdhc"; +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ +- sdhci,auto-cmd12; +- }; +- +-/include/ "qoriq-i2c-0.dtsi" +- i2c@118000 { +- fsl,i2c-erratum-a004447; +- }; +- +- i2c@118100 { +- fsl,i2c-erratum-a004447; +- }; +- +-/include/ "qoriq-i2c-1.dtsi" +- i2c@119000 { +- fsl,i2c-erratum-a004447; +- }; +- +- i2c@119100 { +- fsl,i2c-erratum-a004447; +- }; +- +-/include/ "qoriq-duart-0.dtsi" +-/include/ "qoriq-duart-1.dtsi" +-/include/ "qoriq-gpio-0.dtsi" +-/include/ "qoriq-usb2-mph-0.dtsi" +- usb0: usb@210000 { +- compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; +- phy_type = "utmi"; +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ +- port0; +- }; +- +-/include/ "qoriq-usb2-dr-0.dtsi" +- usb1: usb@211000 { +- compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */ +- dr_mode = "host"; +- phy_type = "utmi"; +- }; +- +-/include/ "qoriq-sata2-0.dtsi" +- sata@220000 { +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */ +- }; +- +-/include/ "qoriq-sata2-1.dtsi" +- sata@221000 { +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */ +- }; +- +-/include/ "qoriq-sec4.2-0.dtsi" +-crypto: crypto@300000 { +- fsl,iommu-parent = <&pamu1>; +- }; +- +-/include/ "qoriq-qman1.dtsi" +-/include/ "qoriq-bman1.dtsi" +- +-/include/ "qoriq-fman-0.dtsi" +-/include/ "qoriq-fman-0-1g-0.dtsi" +-/include/ "qoriq-fman-0-1g-1.dtsi" +-/include/ "qoriq-fman-0-1g-2.dtsi" +-/include/ "qoriq-fman-0-1g-3.dtsi" +-/include/ "qoriq-fman-0-1g-4.dtsi" +-/include/ "qoriq-fman-0-10g-0.dtsi" +- fman@400000 { +- enet0: ethernet@e0000 { +- }; +- +- enet1: ethernet@e2000 { +- }; +- +- enet2: ethernet@e4000 { +- }; +- +- enet3: ethernet@e6000 { +- }; +- +- enet4: ethernet@e8000 { +- }; +- +- enet5: ethernet@f0000 { +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p2041si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p2041si-pre.dtsi +deleted file mode 100644 +index 6318962e8d14..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p2041si-pre.dtsi ++++ /dev/null +@@ -1,130 +0,0 @@ +-/* +- * P2041 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e500mc_power_isa.dtsi" +- +-/ { +- compatible = "fsl,P2041"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- ccsr = &soc; +- dcsr = &dcsr; +- +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- usb0 = &usb0; +- usb1 = &usb1; +- dma0 = &dma0; +- dma1 = &dma1; +- sdhc = &sdhc; +- msi0 = &msi0; +- msi1 = &msi1; +- msi2 = &msi2; +- +- crypto = &crypto; +- sec_jr0 = &sec_jr0; +- sec_jr1 = &sec_jr1; +- sec_jr2 = &sec_jr2; +- sec_jr3 = &sec_jr3; +- rtic_a = &rtic_a; +- rtic_b = &rtic_b; +- rtic_c = &rtic_c; +- rtic_d = &rtic_d; +- sec_mon = &sec_mon; +- +- fman0 = &fman0; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- ethernet4 = &enet4; +- ethernet5 = &enet5; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: PowerPC,e500mc@0 { +- device_type = "cpu"; +- reg = <0>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_0>; +- fsl,portid-mapping = <0x80000000>; +- L2_0: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu1: PowerPC,e500mc@1 { +- device_type = "cpu"; +- reg = <1>; +- clocks = <&clockgen 1 1>; +- next-level-cache = <&L2_1>; +- fsl,portid-mapping = <0x40000000>; +- L2_1: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu2: PowerPC,e500mc@2 { +- device_type = "cpu"; +- reg = <2>; +- clocks = <&clockgen 1 2>; +- next-level-cache = <&L2_2>; +- fsl,portid-mapping = <0x20000000>; +- L2_2: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu3: PowerPC,e500mc@3 { +- device_type = "cpu"; +- reg = <3>; +- clocks = <&clockgen 1 3>; +- next-level-cache = <&L2_3>; +- fsl,portid-mapping = <0x10000000>; +- L2_3: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p3041ds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p3041ds.dts +deleted file mode 100644 +index 6f5f7283c533..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p3041ds.dts ++++ /dev/null +@@ -1,394 +0,0 @@ +-/* +- * P3041DS Device Tree Source +- * +- * Copyright 2010 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p3041si-pre.dtsi" +- +-/ { +- model = "fsl,P3041DS"; +- compatible = "fsl,P3041DS"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases{ +- phy_rgmii_0 = &phy_rgmii_0; +- phy_rgmii_1 = &phy_rgmii_1; +- phy_sgmii_1c = &phy_sgmii_1c; +- phy_sgmii_1d = &phy_sgmii_1d; +- phy_sgmii_1e = &phy_sgmii_1e; +- phy_sgmii_1f = &phy_sgmii_1f; +- phy_xgmii_1 = &phy_xgmii_1; +- phy_xgmii_2 = &phy_xgmii_2; +- emi1_rgmii = &hydra_mdio_rgmii; +- emi1_sgmii = &hydra_mdio_sgmii; +- emi2_xgmii = &hydra_mdio_xgmii; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01008000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x200000>; +- }; +- +- qportals: qman-portals@ff4200000 { +- ranges = <0x0 0xf 0xf4200000 0x200000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- spi@110000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <35000000>; /* input clock */ +- partition@u-boot { +- label = "u-boot"; +- reg = <0x00000000 0x00100000>; +- read-only; +- }; +- partition@kernel { +- label = "kernel"; +- reg = <0x00100000 0x00500000>; +- read-only; +- }; +- partition@dtb { +- label = "dtb"; +- reg = <0x00600000 0x00100000>; +- read-only; +- }; +- partition@fs { +- label = "file system"; +- reg = <0x00700000 0x00900000>; +- }; +- }; +- }; +- +- i2c@118100 { +- eeprom@51 { +- compatible = "atmel,24c256"; +- reg = <0x51>; +- }; +- eeprom@52 { +- compatible = "atmel,24c256"; +- reg = <0x52>; +- }; +- }; +- +- i2c@119100 { +- rtc@68 { +- compatible = "dallas,ds3232"; +- reg = <0x68>; +- interrupts = <0x1 0x1 0 0>; +- }; +- ina220@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <1000>; +- }; +- ina220@41 { +- compatible = "ti,ina220"; +- reg = <0x41>; +- shunt-resistor = <1000>; +- }; +- ina220@44 { +- compatible = "ti,ina220"; +- reg = <0x44>; +- shunt-resistor = <1000>; +- }; +- ina220@45 { +- compatible = "ti,ina220"; +- reg = <0x45>; +- shunt-resistor = <1000>; +- }; +- adt7461@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- }; +- +- fman@400000{ +- ethernet@e0000 { +- phy-handle = <&phy_sgmii_1c>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e2000 { +- phy-handle = <&phy_sgmii_1d>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e4000 { +- phy-handle = <&phy_sgmii_1e>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e6000 { +- phy-handle = <&phy_sgmii_1f>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e8000 { +- phy-handle = <&phy_rgmii_1>; +- phy-connection-type = "rgmii"; +- }; +- +- ethernet@f0000 { +- phy-handle = <&phy_xgmii_1>; +- phy-connection-type = "xgmii"; +- }; +- +- hydra_mdio_xgmii: mdio@f1000 { +- status = "disabled"; +- +- phy_xgmii_1: ethernet-phy@4 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x4>; +- }; +- +- phy_xgmii_2: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x0>; +- }; +- }; +- }; +- }; +- +- rio: rapidio@ffe0c0000 { +- reg = <0xf 0xfe0c0000 0 0x11000>; +- +- port1 { +- ranges = <0 0 0xc 0x20000000 0 0x10000000>; +- }; +- port2 { +- ranges = <0 0 0xc 0x30000000 0 0x10000000>; +- }; +- }; +- +- lbc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x1000>; +- ranges = <0 0 0xf 0xe8000000 0x08000000 +- 2 0 0xf 0xffa00000 0x00040000 +- 3 0 0xf 0xffdf0000 0x00008000>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x08000000>; +- bank-width = <2>; +- device-width = <2>; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,elbc-fcm-nand"; +- reg = <0x2 0x0 0x40000>; +- +- partition@0 { +- label = "NAND U-Boot Image"; +- reg = <0x0 0x02000000>; +- read-only; +- }; +- +- partition@2000000 { +- label = "NAND Root File System"; +- reg = <0x02000000 0x10000000>; +- }; +- +- partition@12000000 { +- label = "NAND Compressed RFS Image"; +- reg = <0x12000000 0x08000000>; +- }; +- +- partition@1a000000 { +- label = "NAND Linux Kernel Image"; +- reg = <0x1a000000 0x04000000>; +- }; +- +- partition@1e000000 { +- label = "NAND DTB Image"; +- reg = <0x1e000000 0x01000000>; +- }; +- +- partition@1f000000 { +- label = "NAND Writable User area"; +- reg = <0x1f000000 0x21000000>; +- }; +- }; +- +- board-control@3,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis"; +- reg = <3 0 0x30>; +- ranges = <0 3 0 0x30>; +- +- mdio-mux-emi1 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "mdio-mux-mmioreg", "mdio-mux"; +- mdio-parent-bus = <&mdio0>; +- reg = <9 1>; +- mux-mask = <0x78>; +- +- hydra_mdio_rgmii: rgmii-mdio@8 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <8>; +- status = "disabled"; +- +- phy_rgmii_0: ethernet-phy@0 { +- reg = <0x0>; +- }; +- +- phy_rgmii_1: ethernet-phy@1 { +- reg = <0x1>; +- }; +- }; +- +- hydra_mdio_sgmii: sgmii-mdio@28 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x28>; +- status = "disabled"; +- +- phy_sgmii_1c: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy_sgmii_1d: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy_sgmii_1e: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy_sgmii_1f: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- }; +- }; +- }; +- +- pci0: pcie@ffe200000 { +- reg = <0xf 0xfe200000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci1: pcie@ffe201000 { +- reg = <0xf 0xfe201000 0 0x1000>; +- ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 +- 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci2: pcie@ffe202000 { +- reg = <0xf 0xfe202000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci3: pcie@ffe203000 { +- reg = <0xf 0xfe203000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +-}; +- +-/include/ "p3041si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p3041si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p3041si-post.dtsi +deleted file mode 100644 +index 81bc75aca2e0..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p3041si-post.dtsi ++++ /dev/null +@@ -1,469 +0,0 @@ +-/* +- * P3041 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&bman_fbpr { +- compatible = "fsl,bman-fbpr"; +- alloc-ranges = <0 0 0x10 0>; +-}; +- +-&qman_fqd { +- compatible = "fsl,qman-fqd"; +- alloc-ranges = <0 0 0x10 0>; +-}; +- +-&qman_pfdr { +- compatible = "fsl,qman-pfdr"; +- alloc-ranges = <0 0 0x10 0>; +-}; +- +-&lbc { +- compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus"; +- interrupts = <25 2 0 0>; +- #address-cells = <2>; +- #size-cells = <1>; +-}; +- +-/* controller at 0x200000 */ +-&pci0 { +- compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 1 15>; +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */ +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 1 15>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 40 1 0 0 +- 0000 0 0 2 &mpic 1 1 0 0 +- 0000 0 0 3 &mpic 2 1 0 0 +- 0000 0 0 4 &mpic 3 1 0 0 +- >; +- }; +-}; +- +-/* controller at 0x201000 */ +-&pci1 { +- compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 1 14>; +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */ +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 1 14>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 41 1 0 0 +- 0000 0 0 2 &mpic 5 1 0 0 +- 0000 0 0 3 &mpic 6 1 0 0 +- 0000 0 0 4 &mpic 7 1 0 0 +- >; +- }; +-}; +- +-/* controller at 0x202000 */ +-&pci2 { +- compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 1 13>; +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */ +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 1 13>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 42 1 0 0 +- 0000 0 0 2 &mpic 9 1 0 0 +- 0000 0 0 3 &mpic 10 1 0 0 +- 0000 0 0 4 &mpic 11 1 0 0 +- >; +- }; +-}; +- +-/* controller at 0x203000 */ +-&pci3 { +- compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 1 12>; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 1 12>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 43 1 0 0 +- 0000 0 0 2 &mpic 0 1 0 0 +- 0000 0 0 3 &mpic 4 1 0 0 +- 0000 0 0 4 &mpic 8 1 0 0 +- >; +- }; +-}; +- +-&rio { +- compatible = "fsl,srio"; +- interrupts = <16 2 1 11>; +- #address-cells = <2>; +- #size-cells = <2>; +- fsl,iommu-parent = <&pamu0>; +- ranges; +- +- port1 { +- #address-cells = <2>; +- #size-cells = <2>; +- cell-index = <1>; +- fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */ +- }; +- +- port2 { +- #address-cells = <2>; +- #size-cells = <2>; +- cell-index = <2>; +- fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */ +- }; +-}; +- +-&dcsr { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,dcsr", "simple-bus"; +- +- dcsr-epu@0 { +- compatible = "fsl,p3041-dcsr-epu", "fsl,dcsr-epu"; +- interrupts = <52 2 0 0 +- 84 2 0 0 +- 85 2 0 0>; +- reg = <0x0 0x1000>; +- }; +- dcsr-npc { +- compatible = "fsl,dcsr-npc"; +- reg = <0x1000 0x1000 0x1000000 0x8000>; +- }; +- dcsr-nxc@2000 { +- compatible = "fsl,dcsr-nxc"; +- reg = <0x2000 0x1000>; +- }; +- dcsr-corenet { +- compatible = "fsl,dcsr-corenet"; +- reg = <0x8000 0x1000 0xB0000 0x1000>; +- }; +- dcsr-dpaa@9000 { +- compatible = "fsl,p3041-dcsr-dpaa", "fsl,dcsr-dpaa"; +- reg = <0x9000 0x1000>; +- }; +- dcsr-ocn@11000 { +- compatible = "fsl,p3041-dcsr-ocn", "fsl,dcsr-ocn"; +- reg = <0x11000 0x1000>; +- }; +- dcsr-ddr@12000 { +- compatible = "fsl,dcsr-ddr"; +- dev-handle = <&ddr1>; +- reg = <0x12000 0x1000>; +- }; +- dcsr-nal@18000 { +- compatible = "fsl,p3041-dcsr-nal", "fsl,dcsr-nal"; +- reg = <0x18000 0x1000>; +- }; +- dcsr-rcpm@22000 { +- compatible = "fsl,p3041-dcsr-rcpm", "fsl,dcsr-rcpm"; +- reg = <0x22000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@40000 { +- compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu0>; +- reg = <0x40000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@41000 { +- compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu1>; +- reg = <0x41000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@42000 { +- compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu2>; +- reg = <0x42000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@43000 { +- compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu3>; +- reg = <0x43000 0x1000>; +- }; +-}; +- +-/include/ "qoriq-bman1-portals.dtsi" +- +-/include/ "qoriq-qman1-portals.dtsi" +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- +- soc-sram-error { +- compatible = "fsl,soc-sram-error"; +- interrupts = <16 2 1 29>; +- }; +- +- corenet-law@0 { +- compatible = "fsl,corenet-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <32>; +- }; +- +- ddr1: memory-controller@8000 { +- compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; +- reg = <0x8000 0x1000>; +- interrupts = <16 2 1 23>; +- }; +- +- cpc: l3-cache-controller@10000 { +- compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache"; +- reg = <0x10000 0x1000>; +- interrupts = <16 2 1 27>; +- }; +- +- corenet-cf@18000 { +- compatible = "fsl,corenet1-cf", "fsl,corenet-cf"; +- reg = <0x18000 0x1000>; +- interrupts = <16 2 1 31>; +- fsl,ccf-num-csdids = <32>; +- fsl,ccf-num-snoopids = <32>; +- }; +- +- iommu@20000 { +- compatible = "fsl,pamu-v1.0", "fsl,pamu"; +- reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */ +- ranges = <0 0x20000 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupts = < +- 24 2 0 0 +- 16 2 1 30>; +- fsl,portid-mapping = <0x0f000000>; +- +- pamu0: pamu@0 { +- reg = <0 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- +- pamu1: pamu@1000 { +- reg = <0x1000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- +- pamu2: pamu@2000 { +- reg = <0x2000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- +- pamu3: pamu@3000 { +- reg = <0x3000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- }; +- +-/include/ "qoriq-mpic.dtsi" +- +- guts: global-utilities@e0000 { +- compatible = "fsl,qoriq-device-config-1.0"; +- reg = <0xe0000 0xe00>; +- fsl,has-rstcr; +- #sleep-cells = <1>; +- fsl,liodn-bits = <12>; +- }; +- +- pins: global-utilities@e0e00 { +- compatible = "fsl,qoriq-pin-control-1.0"; +- reg = <0xe0e00 0x200>; +- #sleep-cells = <2>; +- }; +- +-/include/ "qoriq-clockgen1.dtsi" +- global-utilities@e1000 { +- compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0"; +- }; +- +- rcpm: global-utilities@e2000 { +- compatible = "fsl,qoriq-rcpm-1.0"; +- reg = <0xe2000 0x1000>; +- #sleep-cells = <1>; +- }; +- +- sfp: sfp@e8000 { +- compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0"; +- reg = <0xe8000 0x1000>; +- }; +- +- serdes: serdes@ea000 { +- compatible = "fsl,p3041-serdes"; +- reg = <0xea000 0x1000>; +- }; +- +-/include/ "qoriq-dma-0.dtsi" +- dma@100300 { +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ +- }; +- +-/include/ "qoriq-dma-1.dtsi" +- dma@101300 { +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ +- }; +- +-/include/ "qoriq-espi-0.dtsi" +- spi@110000 { +- fsl,espi-num-chipselects = <4>; +- }; +- +-/include/ "qoriq-esdhc-0.dtsi" +- sdhc@114000 { +- compatible = "fsl,p3041-esdhc", "fsl,esdhc"; +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ +- sdhci,auto-cmd12; +- }; +- +-/include/ "qoriq-i2c-0.dtsi" +-/include/ "qoriq-i2c-1.dtsi" +-/include/ "qoriq-duart-0.dtsi" +-/include/ "qoriq-duart-1.dtsi" +-/include/ "qoriq-gpio-0.dtsi" +-/include/ "qoriq-usb2-mph-0.dtsi" +- usb0: usb@210000 { +- compatible = "fsl-usb2-mph-v1.6", "fsl-usb2-mph"; +- phy_type = "utmi"; +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ +- port0; +- }; +- +-/include/ "qoriq-usb2-dr-0.dtsi" +- usb1: usb@211000 { +- compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */ +- dr_mode = "host"; +- phy_type = "utmi"; +- }; +- +-/include/ "qoriq-sata2-0.dtsi" +- sata@220000 { +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */ +- }; +- +-/include/ "qoriq-sata2-1.dtsi" +- sata@221000 { +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */ +- }; +- +-/include/ "qoriq-sec4.2-0.dtsi" +-crypto: crypto@300000 { +- fsl,iommu-parent = <&pamu1>; +- }; +- +-/include/ "qoriq-qman1.dtsi" +-/include/ "qoriq-bman1.dtsi" +- +-/include/ "qoriq-fman-0.dtsi" +-/include/ "qoriq-fman-0-1g-0.dtsi" +-/include/ "qoriq-fman-0-1g-1.dtsi" +-/include/ "qoriq-fman-0-1g-2.dtsi" +-/include/ "qoriq-fman-0-1g-3.dtsi" +-/include/ "qoriq-fman-0-1g-4.dtsi" +-/include/ "qoriq-fman-0-10g-0.dtsi" +- fman@400000 { +- enet0: ethernet@e0000 { +- }; +- +- enet1: ethernet@e2000 { +- }; +- +- enet2: ethernet@e4000 { +- }; +- +- enet3: ethernet@e6000 { +- }; +- +- enet4: ethernet@e8000 { +- }; +- +- enet5: ethernet@f0000 { +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p3041si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p3041si-pre.dtsi +deleted file mode 100644 +index db92f1151a48..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p3041si-pre.dtsi ++++ /dev/null +@@ -1,131 +0,0 @@ +-/* +- * P3041 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e500mc_power_isa.dtsi" +- +-/ { +- compatible = "fsl,P3041"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- ccsr = &soc; +- dcsr = &dcsr; +- +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- pci3 = &pci3; +- usb0 = &usb0; +- usb1 = &usb1; +- dma0 = &dma0; +- dma1 = &dma1; +- sdhc = &sdhc; +- msi0 = &msi0; +- msi1 = &msi1; +- msi2 = &msi2; +- +- crypto = &crypto; +- sec_jr0 = &sec_jr0; +- sec_jr1 = &sec_jr1; +- sec_jr2 = &sec_jr2; +- sec_jr3 = &sec_jr3; +- rtic_a = &rtic_a; +- rtic_b = &rtic_b; +- rtic_c = &rtic_c; +- rtic_d = &rtic_d; +- sec_mon = &sec_mon; +- +- fman0 = &fman0; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- ethernet4 = &enet4; +- ethernet5 = &enet5; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: PowerPC,e500mc@0 { +- device_type = "cpu"; +- reg = <0>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_0>; +- fsl,portid-mapping = <0x80000000>; +- L2_0: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu1: PowerPC,e500mc@1 { +- device_type = "cpu"; +- reg = <1>; +- clocks = <&clockgen 1 1>; +- next-level-cache = <&L2_1>; +- fsl,portid-mapping = <0x40000000>; +- L2_1: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu2: PowerPC,e500mc@2 { +- device_type = "cpu"; +- reg = <2>; +- clocks = <&clockgen 1 2>; +- next-level-cache = <&L2_2>; +- fsl,portid-mapping = <0x20000000>; +- L2_2: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu3: PowerPC,e500mc@3 { +- device_type = "cpu"; +- reg = <3>; +- clocks = <&clockgen 1 3>; +- next-level-cache = <&L2_3>; +- fsl,portid-mapping = <0x10000000>; +- L2_3: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p4080ds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p4080ds.dts +deleted file mode 100644 +index 969b32c4f2d5..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p4080ds.dts ++++ /dev/null +@@ -1,439 +0,0 @@ +-/* +- * P4080DS Device Tree Source +- * +- * Copyright 2009 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p4080si-pre.dtsi" +- +-/ { +- model = "fsl,P4080DS"; +- compatible = "fsl,P4080DS"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- phy_rgmii = &phyrgmii; +- phy5_slot3 = &phy5slot3; +- phy6_slot3 = &phy6slot3; +- phy7_slot3 = &phy7slot3; +- phy8_slot3 = &phy8slot3; +- emi1_slot3 = &p4080mdio2; +- emi1_slot4 = &p4080mdio1; +- emi1_slot5 = &p4080mdio3; +- emi1_rgmii = &p4080mdio0; +- emi2_slot4 = &p4080xmdio1; +- emi2_slot5 = &p4080xmdio3; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01008000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x200000>; +- }; +- +- qportals: qman-portals@ff4200000 { +- ranges = <0x0 0xf 0xf4200000 0x200000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- +- spi@110000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; /* input clock */ +- partition@u-boot { +- label = "u-boot"; +- reg = <0x00000000 0x00100000>; +- read-only; +- }; +- partition@kernel { +- label = "kernel"; +- reg = <0x00100000 0x00500000>; +- read-only; +- }; +- partition@dtb { +- label = "dtb"; +- reg = <0x00600000 0x00100000>; +- read-only; +- }; +- partition@fs { +- label = "file system"; +- reg = <0x00700000 0x00900000>; +- }; +- }; +- }; +- +- i2c@118100 { +- eeprom@51 { +- compatible = "atmel,spd"; +- reg = <0x51>; +- }; +- eeprom@52 { +- compatible = "atmel,spd"; +- reg = <0x52>; +- }; +- rtc@68 { +- compatible = "dallas,ds3232"; +- reg = <0x68>; +- interrupts = <0x1 0x1 0 0>; +- }; +- adt7461@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- }; +- +- i2c@118000 { +- zl2006@21 { +- compatible = "zl2006"; +- reg = <0x21>; +- }; +- zl2006@22 { +- compatible = "zl2006"; +- reg = <0x22>; +- }; +- zl2006@23 { +- compatible = "zl2006"; +- reg = <0x23>; +- }; +- zl2006@24 { +- compatible = "zl2006"; +- reg = <0x24>; +- }; +- eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- }; +- eeprom@55 { +- compatible = "atmel,24c64"; +- reg = <0x55>; +- }; +- eeprom@56 { +- compatible = "atmel,24c64"; +- reg = <0x56>; +- }; +- eeprom@57 { +- compatible = "atmel,24c02"; +- reg = <0x57>; +- }; +- }; +- +- i2c@119100 { +- /* 0x6E: ICS9FG108 */ +- }; +- +- usb0: usb@210000 { +- phy_type = "ulpi"; +- }; +- +- usb1: usb@211000 { +- dr_mode = "host"; +- phy_type = "ulpi"; +- }; +- +- fman@400000 { +- ethernet@e0000 { +- phy-handle = <&phy0>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e2000 { +- phy-handle = <&phy1>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e4000 { +- phy-handle = <&phy2>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e6000 { +- phy-handle = <&phy3>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@f0000 { +- phy-handle = <&phy10>; +- phy-connection-type = "xgmii"; +- }; +- }; +- +- fman@500000 { +- ethernet@e0000 { +- phy-handle = <&phy5>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e2000 { +- phy-handle = <&phy6>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e4000 { +- phy-handle = <&phy7>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e6000 { +- phy-handle = <&phy8>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@f0000 { +- phy-handle = <&phy11>; +- phy-connection-type = "xgmii"; +- }; +- }; +- }; +- +- rio: rapidio@ffe0c0000 { +- reg = <0xf 0xfe0c0000 0 0x11000>; +- +- port1 { +- ranges = <0 0 0xc 0x20000000 0 0x10000000>; +- }; +- port2 { +- ranges = <0 0 0xc 0x30000000 0 0x10000000>; +- }; +- }; +- +- lbc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x1000>; +- ranges = <0 0 0xf 0xe8000000 0x08000000 +- 3 0 0xf 0xffdf0000 0x00008000>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x08000000>; +- bank-width = <2>; +- device-width = <2>; +- }; +- +- board-control@3,0 { +- compatible = "fsl,p4080ds-fpga", "fsl,fpga-ngpixis"; +- reg = <3 0 0x30>; +- }; +- }; +- +- pci0: pcie@ffe200000 { +- reg = <0xf 0xfe200000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci1: pcie@ffe201000 { +- reg = <0xf 0xfe201000 0 0x1000>; +- ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 +- 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci2: pcie@ffe202000 { +- reg = <0xf 0xfe202000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- mdio-mux-emi1 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "mdio-mux-gpio", "mdio-mux"; +- mdio-parent-bus = <&mdio0>; +- gpios = <&gpio0 1 0>, <&gpio0 0 0>; +- +- p4080mdio0: mdio@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- phyrgmii: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +- +- p4080mdio1: mdio@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- phy5: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy6: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy7: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy8: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- +- p4080mdio2: mdio@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- status = "disabled"; +- +- phy5slot3: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy6slot3: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy7slot3: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy8slot3: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- +- p4080mdio3: mdio@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- phy0: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy1: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy2: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy3: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- }; +- +- mdio-mux-emi2 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "mdio-mux-gpio", "mdio-mux"; +- mdio-parent-bus = <&xmdio0>; +- gpios = <&gpio0 3 0>, <&gpio0 2 0>; +- +- p4080xmdio1: mdio@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- +- phy11: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x0>; +- }; +- }; +- +- p4080xmdio3: mdio@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- +- phy10: ethernet-phy@4 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x4>; +- }; +- }; +- }; +-}; +- +-/include/ "p4080si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p4080si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p4080si-post.dtsi +deleted file mode 100644 +index 4da49b6dd3f5..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p4080si-post.dtsi ++++ /dev/null +@@ -1,492 +0,0 @@ +-/* +- * P4080/P4040 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&bman_fbpr { +- compatible = "fsl,bman-fbpr"; +- alloc-ranges = <0 0 0x10 0>; +-}; +- +-&qman_fqd { +- compatible = "fsl,qman-fqd"; +- alloc-ranges = <0 0 0x10 0>; +-}; +- +-&qman_pfdr { +- compatible = "fsl,qman-pfdr"; +- alloc-ranges = <0 0 0x10 0>; +-}; +- +-&lbc { +- compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus"; +- interrupts = <25 2 0 0>; +- #address-cells = <2>; +- #size-cells = <1>; +-}; +- +-/* controller at 0x200000 */ +-&pci0 { +- compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 1 15>; +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */ +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 1 15>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 40 1 0 0 +- 0000 0 0 2 &mpic 1 1 0 0 +- 0000 0 0 3 &mpic 2 1 0 0 +- 0000 0 0 4 &mpic 3 1 0 0 +- >; +- }; +-}; +- +-/* controller at 0x201000 */ +-&pci1 { +- compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 1 14>; +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */ +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 1 14>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 41 1 0 0 +- 0000 0 0 2 &mpic 5 1 0 0 +- 0000 0 0 3 &mpic 6 1 0 0 +- 0000 0 0 4 &mpic 7 1 0 0 +- >; +- }; +-}; +- +-/* controller at 0x202000 */ +-&pci2 { +- compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 1 13>; +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */ +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 1 13>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 42 1 0 0 +- 0000 0 0 2 &mpic 9 1 0 0 +- 0000 0 0 3 &mpic 10 1 0 0 +- 0000 0 0 4 &mpic 11 1 0 0 +- >; +- }; +-}; +- +-&rio { +- compatible = "fsl,srio"; +- interrupts = <16 2 1 11>; +- #address-cells = <2>; +- #size-cells = <2>; +- fsl,srio-rmu-handle = <&rmu>; +- fsl,iommu-parent = <&pamu0>; +- ranges; +- +- port1 { +- #address-cells = <2>; +- #size-cells = <2>; +- cell-index = <1>; +- fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */ +- }; +- +- port2 { +- #address-cells = <2>; +- #size-cells = <2>; +- cell-index = <2>; +- fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */ +- }; +-}; +- +-&dcsr { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,dcsr", "simple-bus"; +- +- dcsr-epu@0 { +- compatible = "fsl,p4080-dcsr-epu", "fsl,dcsr-epu"; +- interrupts = <52 2 0 0 +- 84 2 0 0 +- 85 2 0 0>; +- reg = <0x0 0x1000>; +- }; +- dcsr-npc { +- compatible = "fsl,dcsr-npc"; +- reg = <0x1000 0x1000 0x1000000 0x8000>; +- }; +- dcsr-nxc@2000 { +- compatible = "fsl,dcsr-nxc"; +- reg = <0x2000 0x1000>; +- }; +- dcsr-corenet { +- compatible = "fsl,dcsr-corenet"; +- reg = <0x8000 0x1000 0xB0000 0x1000>; +- }; +- dcsr-dpaa@9000 { +- compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa"; +- reg = <0x9000 0x1000>; +- }; +- dcsr-ocn@11000 { +- compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn"; +- reg = <0x11000 0x1000>; +- }; +- dcsr-ddr@12000 { +- compatible = "fsl,dcsr-ddr"; +- dev-handle = <&ddr1>; +- reg = <0x12000 0x1000>; +- }; +- dcsr-ddr@13000 { +- compatible = "fsl,dcsr-ddr"; +- dev-handle = <&ddr2>; +- reg = <0x13000 0x1000>; +- }; +- dcsr-nal@18000 { +- compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal"; +- reg = <0x18000 0x1000>; +- }; +- dcsr-rcpm@22000 { +- compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm"; +- reg = <0x22000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@40000 { +- compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu0>; +- reg = <0x40000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@41000 { +- compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu1>; +- reg = <0x41000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@42000 { +- compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu2>; +- reg = <0x42000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@43000 { +- compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu3>; +- reg = <0x43000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@44000 { +- compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu4>; +- reg = <0x44000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@45000 { +- compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu5>; +- reg = <0x45000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@46000 { +- compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu6>; +- reg = <0x46000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@47000 { +- compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu7>; +- reg = <0x47000 0x1000>; +- }; +- +-}; +- +-/include/ "qoriq-bman1-portals.dtsi" +- +-/include/ "qoriq-qman1-portals.dtsi" +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- +- soc-sram-error { +- compatible = "fsl,soc-sram-error"; +- interrupts = <16 2 1 29>; +- }; +- +- corenet-law@0 { +- compatible = "fsl,corenet-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <32>; +- }; +- +- ddr1: memory-controller@8000 { +- compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller"; +- reg = <0x8000 0x1000>; +- interrupts = <16 2 1 23>; +- }; +- +- ddr2: memory-controller@9000 { +- compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller"; +- reg = <0x9000 0x1000>; +- interrupts = <16 2 1 22>; +- }; +- +- cpc: l3-cache-controller@10000 { +- compatible = "fsl,p4080-l3-cache-controller", "cache"; +- reg = <0x10000 0x1000 +- 0x11000 0x1000>; +- interrupts = <16 2 1 27 +- 16 2 1 26>; +- }; +- +- corenet-cf@18000 { +- compatible = "fsl,corenet1-cf", "fsl,corenet-cf"; +- reg = <0x18000 0x1000>; +- interrupts = <16 2 1 31>; +- fsl,ccf-num-csdids = <32>; +- fsl,ccf-num-snoopids = <32>; +- }; +- +- iommu@20000 { +- compatible = "fsl,pamu-v1.0", "fsl,pamu"; +- reg = <0x20000 0x5000>; /* for compatibility with older PAMU drivers */ +- ranges = <0 0x20000 0x5000>; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupts = < +- 24 2 0 0 +- 16 2 1 30>; +- fsl,portid-mapping = <0x00f80000>; +- +- pamu0: pamu@0 { +- reg = <0 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- +- pamu1: pamu@1000 { +- reg = <0x1000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- +- pamu2: pamu@2000 { +- reg = <0x2000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- +- pamu3: pamu@3000 { +- reg = <0x3000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- +- pamu4: pamu@4000 { +- reg = <0x4000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- }; +- +-/include/ "qoriq-rmu-0.dtsi" +- rmu@d3000 { +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x540>; /* RMULIODNR */ +- }; +- +-/include/ "qoriq-mpic.dtsi" +- +- guts: global-utilities@e0000 { +- compatible = "fsl,qoriq-device-config-1.0"; +- reg = <0xe0000 0xe00>; +- fsl,has-rstcr; +- #sleep-cells = <1>; +- fsl,liodn-bits = <12>; +- }; +- +- pins: global-utilities@e0e00 { +- compatible = "fsl,qoriq-pin-control-1.0"; +- reg = <0xe0e00 0x200>; +- #sleep-cells = <2>; +- }; +- +-/include/ "qoriq-clockgen1.dtsi" +- global-utilities@e1000 { +- compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0"; +- }; +- +- rcpm: global-utilities@e2000 { +- compatible = "fsl,qoriq-rcpm-1.0"; +- reg = <0xe2000 0x1000>; +- #sleep-cells = <1>; +- }; +- +- sfp: sfp@e8000 { +- compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0"; +- reg = <0xe8000 0x1000>; +- }; +- +- serdes: serdes@ea000 { +- compatible = "fsl,p4080-serdes"; +- reg = <0xea000 0x1000>; +- }; +- +-/include/ "qoriq-dma-0.dtsi" +- dma@100300 { +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ +- }; +- +-/include/ "qoriq-dma-1.dtsi" +- dma@101300 { +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ +- }; +- +-/include/ "qoriq-espi-0.dtsi" +- spi@110000 { +- fsl,espi-num-chipselects = <4>; +- }; +- +-/include/ "qoriq-esdhc-0.dtsi" +- sdhc@114000 { +- compatible = "fsl,p4080-esdhc", "fsl,esdhc"; +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ +- voltage-ranges = <3300 3300>; +- sdhci,auto-cmd12; +- }; +- +-/include/ "qoriq-i2c-0.dtsi" +-/include/ "qoriq-i2c-1.dtsi" +-/include/ "qoriq-duart-0.dtsi" +-/include/ "qoriq-duart-1.dtsi" +-/include/ "qoriq-gpio-0.dtsi" +-/include/ "qoriq-usb2-mph-0.dtsi" +- usb@210000 { +- compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ +- port0; +- }; +-/include/ "qoriq-usb2-dr-0.dtsi" +- usb@211000 { +- compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */ +- }; +-/include/ "qoriq-sec4.0-0.dtsi" +-crypto: crypto@300000 { +- fsl,iommu-parent = <&pamu1>; +- }; +- +-/include/ "qoriq-qman1.dtsi" +-/include/ "qoriq-bman1.dtsi" +- +-/include/ "qoriq-fman-0.dtsi" +-/include/ "qoriq-fman-0-1g-0.dtsi" +-/include/ "qoriq-fman-0-1g-1.dtsi" +-/include/ "qoriq-fman-0-1g-2.dtsi" +-/include/ "qoriq-fman-0-1g-3.dtsi" +-/include/ "qoriq-fman-0-10g-0.dtsi" +- fman@400000 { +- enet0: ethernet@e0000 { +- }; +- +- enet1: ethernet@e2000 { +- }; +- +- enet2: ethernet@e4000 { +- }; +- +- enet3: ethernet@e6000 { +- }; +- +- enet4: ethernet@f0000 { +- }; +- }; +- +-/include/ "qoriq-fman-1.dtsi" +-/include/ "qoriq-fman-1-1g-0.dtsi" +-/include/ "qoriq-fman-1-1g-1.dtsi" +-/include/ "qoriq-fman-1-1g-2.dtsi" +-/include/ "qoriq-fman-1-1g-3.dtsi" +-/include/ "qoriq-fman-1-10g-0.dtsi" +- fman@500000 { +- enet5: ethernet@e0000 { +- }; +- +- enet6: ethernet@e2000 { +- }; +- +- enet7: ethernet@e4000 { +- }; +- +- enet8: ethernet@e6000 { +- }; +- +- enet9: ethernet@f0000 { +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p4080si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p4080si-pre.dtsi +deleted file mode 100644 +index 0a7c65a00e5e..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p4080si-pre.dtsi ++++ /dev/null +@@ -1,175 +0,0 @@ +-/* +- * P4080/P4040 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e500mc_power_isa.dtsi" +- +-/ { +- compatible = "fsl,P4080"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- ccsr = &soc; +- dcsr = &dcsr; +- +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- usb0 = &usb0; +- usb1 = &usb1; +- dma0 = &dma0; +- dma1 = &dma1; +- sdhc = &sdhc; +- msi0 = &msi0; +- msi1 = &msi1; +- msi2 = &msi2; +- +- crypto = &crypto; +- sec_jr0 = &sec_jr0; +- sec_jr1 = &sec_jr1; +- sec_jr2 = &sec_jr2; +- sec_jr3 = &sec_jr3; +- rtic_a = &rtic_a; +- rtic_b = &rtic_b; +- rtic_c = &rtic_c; +- rtic_d = &rtic_d; +- sec_mon = &sec_mon; +- +- fman0 = &fman0; +- fman1 = &fman1; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- ethernet4 = &enet4; +- ethernet5 = &enet5; +- ethernet6 = &enet6; +- ethernet7 = &enet7; +- ethernet8 = &enet8; +- ethernet9 = &enet9; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: PowerPC,e500mc@0 { +- device_type = "cpu"; +- reg = <0>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_0>; +- fsl,portid-mapping = <0x80000000>; +- L2_0: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu1: PowerPC,e500mc@1 { +- device_type = "cpu"; +- reg = <1>; +- clocks = <&clockgen 1 1>; +- next-level-cache = <&L2_1>; +- fsl,portid-mapping = <0x40000000>; +- L2_1: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu2: PowerPC,e500mc@2 { +- device_type = "cpu"; +- reg = <2>; +- clocks = <&clockgen 1 2>; +- next-level-cache = <&L2_2>; +- fsl,portid-mapping = <0x20000000>; +- L2_2: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu3: PowerPC,e500mc@3 { +- device_type = "cpu"; +- reg = <3>; +- clocks = <&clockgen 1 3>; +- next-level-cache = <&L2_3>; +- fsl,portid-mapping = <0x10000000>; +- L2_3: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu4: PowerPC,e500mc@4 { +- device_type = "cpu"; +- reg = <4>; +- clocks = <&clockgen 1 4>; +- next-level-cache = <&L2_4>; +- fsl,portid-mapping = <0x08000000>; +- L2_4: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu5: PowerPC,e500mc@5 { +- device_type = "cpu"; +- reg = <5>; +- clocks = <&clockgen 1 5>; +- next-level-cache = <&L2_5>; +- fsl,portid-mapping = <0x04000000>; +- L2_5: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu6: PowerPC,e500mc@6 { +- device_type = "cpu"; +- reg = <6>; +- clocks = <&clockgen 1 6>; +- next-level-cache = <&L2_6>; +- fsl,portid-mapping = <0x02000000>; +- L2_6: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu7: PowerPC,e500mc@7 { +- device_type = "cpu"; +- reg = <7>; +- clocks = <&clockgen 1 7>; +- next-level-cache = <&L2_7>; +- fsl,portid-mapping = <0x01000000>; +- L2_7: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p5020ds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p5020ds.dts +deleted file mode 100644 +index b24adf902d8d..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p5020ds.dts ++++ /dev/null +@@ -1,394 +0,0 @@ +-/* +- * P5020DS Device Tree Source +- * +- * Copyright 2010 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "p5020si-pre.dtsi" +- +-/ { +- model = "fsl,P5020DS"; +- compatible = "fsl,P5020DS"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- phy_rgmii_0 = &phy_rgmii_0; +- phy_rgmii_1 = &phy_rgmii_1; +- phy_sgmii_1c = &phy_sgmii_1c; +- phy_sgmii_1d = &phy_sgmii_1d; +- phy_sgmii_1e = &phy_sgmii_1e; +- phy_sgmii_1f = &phy_sgmii_1f; +- phy_xgmii_1 = &phy_xgmii_1; +- phy_xgmii_2 = &phy_xgmii_2; +- emi1_rgmii = &hydra_mdio_rgmii; +- emi1_sgmii = &hydra_mdio_sgmii; +- emi2_xgmii = &hydra_mdio_xgmii; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01008000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x200000>; +- }; +- +- qportals: qman-portals@ff4200000 { +- ranges = <0x0 0xf 0xf4200000 0x200000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- spi@110000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; /* input clock */ +- partition@u-boot { +- label = "u-boot"; +- reg = <0x00000000 0x00100000>; +- read-only; +- }; +- partition@kernel { +- label = "kernel"; +- reg = <0x00100000 0x00500000>; +- read-only; +- }; +- partition@dtb { +- label = "dtb"; +- reg = <0x00600000 0x00100000>; +- read-only; +- }; +- partition@fs { +- label = "file system"; +- reg = <0x00700000 0x00900000>; +- }; +- }; +- }; +- +- i2c@118100 { +- eeprom@51 { +- compatible = "atmel,24c256"; +- reg = <0x51>; +- }; +- eeprom@52 { +- compatible = "atmel,24c256"; +- reg = <0x52>; +- }; +- }; +- +- i2c@119100 { +- rtc@68 { +- compatible = "dallas,ds3232"; +- reg = <0x68>; +- interrupts = <0x1 0x1 0 0>; +- }; +- ina220@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <1000>; +- }; +- ina220@41 { +- compatible = "ti,ina220"; +- reg = <0x41>; +- shunt-resistor = <1000>; +- }; +- ina220@44 { +- compatible = "ti,ina220"; +- reg = <0x44>; +- shunt-resistor = <1000>; +- }; +- ina220@45 { +- compatible = "ti,ina220"; +- reg = <0x45>; +- shunt-resistor = <1000>; +- }; +- adt7461@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- }; +- +- fman@400000 { +- ethernet@e0000 { +- phy-handle = <&phy_sgmii_1c>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e2000 { +- phy-handle = <&phy_sgmii_1d>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e4000 { +- phy-handle = <&phy_sgmii_1e>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e6000 { +- phy-handle = <&phy_sgmii_1f>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e8000 { +- phy-handle = <&phy_rgmii_1>; +- phy-connection-type = "rgmii"; +- }; +- +- ethernet@f0000 { +- phy-handle = <&phy_xgmii_1>; +- phy-connection-type = "xgmii"; +- }; +- +- hydra_mdio_xgmii: mdio@f1000 { +- status = "disabled"; +- +- phy_xgmii_1: ethernet-phy@4 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x4>; +- }; +- +- phy_xgmii_2: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x0>; +- }; +- }; +- }; +- }; +- +- rio: rapidio@ffe0c0000 { +- reg = <0xf 0xfe0c0000 0 0x11000>; +- +- port1 { +- ranges = <0 0 0xc 0x20000000 0 0x10000000>; +- }; +- port2 { +- ranges = <0 0 0xc 0x30000000 0 0x10000000>; +- }; +- }; +- +- lbc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x1000>; +- ranges = <0 0 0xf 0xe8000000 0x08000000 +- 2 0 0xf 0xffa00000 0x00040000 +- 3 0 0xf 0xffdf0000 0x00008000>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x08000000>; +- bank-width = <2>; +- device-width = <2>; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,elbc-fcm-nand"; +- reg = <0x2 0x0 0x40000>; +- +- partition@0 { +- label = "NAND U-Boot Image"; +- reg = <0x0 0x02000000>; +- read-only; +- }; +- +- partition@2000000 { +- label = "NAND Root File System"; +- reg = <0x02000000 0x10000000>; +- }; +- +- partition@12000000 { +- label = "NAND Compressed RFS Image"; +- reg = <0x12000000 0x08000000>; +- }; +- +- partition@1a000000 { +- label = "NAND Linux Kernel Image"; +- reg = <0x1a000000 0x04000000>; +- }; +- +- partition@1e000000 { +- label = "NAND DTB Image"; +- reg = <0x1e000000 0x01000000>; +- }; +- +- partition@1f000000 { +- label = "NAND Writable User area"; +- reg = <0x1f000000 0x21000000>; +- }; +- }; +- +- board-control@3,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis"; +- reg = <3 0 0x30>; +- ranges = <0 3 0 0x30>; +- +- mdio-mux-emi1 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "mdio-mux-mmioreg", "mdio-mux"; +- mdio-parent-bus = <&mdio0>; +- reg = <9 1>; +- mux-mask = <0x78>; +- +- hydra_mdio_rgmii: rgmii-mdio@8 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <8>; +- status = "disabled"; +- +- phy_rgmii_0: ethernet-phy@0 { +- reg = <0x0>; +- }; +- +- phy_rgmii_1: ethernet-phy@1 { +- reg = <0x1>; +- }; +- }; +- +- hydra_mdio_sgmii: sgmii-mdio@28 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x28>; +- status = "disabled"; +- +- phy_sgmii_1c: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy_sgmii_1d: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy_sgmii_1e: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy_sgmii_1f: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- }; +- }; +- }; +- +- pci0: pcie@ffe200000 { +- reg = <0xf 0xfe200000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci1: pcie@ffe201000 { +- reg = <0xf 0xfe201000 0 0x1000>; +- ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 +- 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci2: pcie@ffe202000 { +- reg = <0xf 0xfe202000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci3: pcie@ffe203000 { +- reg = <0xf 0xfe203000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +-}; +- +-/include/ "p5020si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p5020si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p5020si-post.dtsi +deleted file mode 100644 +index cd008cdd2889..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p5020si-post.dtsi ++++ /dev/null +@@ -1,478 +0,0 @@ +-/* +- * P5020/5010 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&bman_fbpr { +- compatible = "fsl,bman-fbpr"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&qman_fqd { +- compatible = "fsl,qman-fqd"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&qman_pfdr { +- compatible = "fsl,qman-pfdr"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&lbc { +- compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus"; +- interrupts = <25 2 0 0>; +- #address-cells = <2>; +- #size-cells = <1>; +-}; +- +-/* controller at 0x200000 */ +-&pci0 { +- compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 1 15>; +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */ +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 1 15>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 40 1 0 0 +- 0000 0 0 2 &mpic 1 1 0 0 +- 0000 0 0 3 &mpic 2 1 0 0 +- 0000 0 0 4 &mpic 3 1 0 0 +- >; +- }; +-}; +- +-/* controller at 0x201000 */ +-&pci1 { +- compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 1 14>; +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */ +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 1 14>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 41 1 0 0 +- 0000 0 0 2 &mpic 5 1 0 0 +- 0000 0 0 3 &mpic 6 1 0 0 +- 0000 0 0 4 &mpic 7 1 0 0 +- >; +- }; +-}; +- +-/* controller at 0x202000 */ +-&pci2 { +- compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 1 13>; +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */ +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 1 13>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 42 1 0 0 +- 0000 0 0 2 &mpic 9 1 0 0 +- 0000 0 0 3 &mpic 10 1 0 0 +- 0000 0 0 4 &mpic 11 1 0 0 +- >; +- }; +-}; +- +-/* controller at 0x203000 */ +-&pci3 { +- compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 1 12>; +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x50c>; /* PEX4LIODNR */ +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 1 12>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 43 1 0 0 +- 0000 0 0 2 &mpic 0 1 0 0 +- 0000 0 0 3 &mpic 4 1 0 0 +- 0000 0 0 4 &mpic 8 1 0 0 +- >; +- }; +-}; +- +-&rio { +- compatible = "fsl,srio"; +- interrupts = <16 2 1 11>; +- #address-cells = <2>; +- #size-cells = <2>; +- fsl,iommu-parent = <&pamu0>; +- ranges; +- +- port1 { +- #address-cells = <2>; +- #size-cells = <2>; +- cell-index = <1>; +- fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */ +- }; +- +- port2 { +- #address-cells = <2>; +- #size-cells = <2>; +- cell-index = <2>; +- fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */ +- }; +-}; +- +-&dcsr { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,dcsr", "simple-bus"; +- +- dcsr-epu@0 { +- compatible = "fsl,p5020-dcsr-epu", "fsl,dcsr-epu"; +- interrupts = <52 2 0 0 +- 84 2 0 0 +- 85 2 0 0>; +- reg = <0x0 0x1000>; +- }; +- dcsr-npc { +- compatible = "fsl,dcsr-npc"; +- reg = <0x1000 0x1000 0x1000000 0x8000>; +- }; +- dcsr-nxc@2000 { +- compatible = "fsl,dcsr-nxc"; +- reg = <0x2000 0x1000>; +- }; +- dcsr-corenet { +- compatible = "fsl,dcsr-corenet"; +- reg = <0x8000 0x1000 0xB0000 0x1000>; +- }; +- dcsr-dpaa@9000 { +- compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa"; +- reg = <0x9000 0x1000>; +- }; +- dcsr-ocn@11000 { +- compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn"; +- reg = <0x11000 0x1000>; +- }; +- dcsr-ddr@12000 { +- compatible = "fsl,dcsr-ddr"; +- dev-handle = <&ddr1>; +- reg = <0x12000 0x1000>; +- }; +- dcsr-ddr@13000 { +- compatible = "fsl,dcsr-ddr"; +- dev-handle = <&ddr2>; +- reg = <0x13000 0x1000>; +- }; +- dcsr-nal@18000 { +- compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal"; +- reg = <0x18000 0x1000>; +- }; +- dcsr-rcpm@22000 { +- compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm"; +- reg = <0x22000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@40000 { +- compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu0>; +- reg = <0x40000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@41000 { +- compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu1>; +- reg = <0x41000 0x1000>; +- }; +-}; +- +-/include/ "qoriq-bman1-portals.dtsi" +- +-/include/ "qoriq-qman1-portals.dtsi" +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- +- soc-sram-error { +- compatible = "fsl,soc-sram-error"; +- interrupts = <16 2 1 29>; +- }; +- +- corenet-law@0 { +- compatible = "fsl,corenet-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <32>; +- }; +- +- ddr1: memory-controller@8000 { +- compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; +- reg = <0x8000 0x1000>; +- interrupts = <16 2 1 23>; +- }; +- +- ddr2: memory-controller@9000 { +- compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller"; +- reg = <0x9000 0x1000>; +- interrupts = <16 2 1 22>; +- }; +- +- cpc: l3-cache-controller@10000 { +- compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache"; +- reg = <0x10000 0x1000 +- 0x11000 0x1000>; +- interrupts = <16 2 1 27 +- 16 2 1 26>; +- }; +- +- corenet-cf@18000 { +- compatible = "fsl,corenet1-cf", "fsl,corenet-cf"; +- reg = <0x18000 0x1000>; +- interrupts = <16 2 1 31>; +- fsl,ccf-num-csdids = <32>; +- fsl,ccf-num-snoopids = <32>; +- }; +- +- iommu@20000 { +- compatible = "fsl,pamu-v1.0", "fsl,pamu"; +- reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */ +- ranges = <0 0x20000 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupts = < +- 24 2 0 0 +- 16 2 1 30>; +- fsl,portid-mapping = <0x3c000000>; +- +- pamu0: pamu@0 { +- reg = <0 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- +- pamu1: pamu@1000 { +- reg = <0x1000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- +- pamu2: pamu@2000 { +- reg = <0x2000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- +- pamu3: pamu@3000 { +- reg = <0x3000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- }; +- +-/include/ "qoriq-mpic.dtsi" +- +- guts: global-utilities@e0000 { +- compatible = "fsl,qoriq-device-config-1.0"; +- reg = <0xe0000 0xe00>; +- fsl,has-rstcr; +- #sleep-cells = <1>; +- fsl,liodn-bits = <12>; +- }; +- +- pins: global-utilities@e0e00 { +- compatible = "fsl,qoriq-pin-control-1.0"; +- reg = <0xe0e00 0x200>; +- #sleep-cells = <2>; +- }; +- +-/include/ "qoriq-clockgen1.dtsi" +- global-utilities@e1000 { +- compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; +- }; +- +- rcpm: global-utilities@e2000 { +- compatible = "fsl,qoriq-rcpm-1.0"; +- reg = <0xe2000 0x1000>; +- #sleep-cells = <1>; +- }; +- +- sfp: sfp@e8000 { +- compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0"; +- reg = <0xe8000 0x1000>; +- }; +- +- serdes: serdes@ea000 { +- compatible = "fsl,p5020-serdes"; +- reg = <0xea000 0x1000>; +- }; +- +-/include/ "qoriq-dma-0.dtsi" +- dma@100300 { +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ +- }; +- +-/include/ "qoriq-dma-1.dtsi" +- dma@101300 { +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ +- }; +- +-/include/ "qoriq-espi-0.dtsi" +- spi@110000 { +- fsl,espi-num-chipselects = <4>; +- }; +- +-/include/ "qoriq-esdhc-0.dtsi" +- sdhc@114000 { +- compatible = "fsl,p5020-esdhc", "fsl,esdhc"; +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ +- sdhci,auto-cmd12; +- }; +- +-/include/ "qoriq-i2c-0.dtsi" +-/include/ "qoriq-i2c-1.dtsi" +-/include/ "qoriq-duart-0.dtsi" +-/include/ "qoriq-duart-1.dtsi" +-/include/ "qoriq-gpio-0.dtsi" +-/include/ "qoriq-usb2-mph-0.dtsi" +- usb0: usb@210000 { +- compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ +- phy_type = "utmi"; +- port0; +- }; +- +-/include/ "qoriq-usb2-dr-0.dtsi" +- usb1: usb@211000 { +- compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */ +- dr_mode = "host"; +- phy_type = "utmi"; +- }; +- +-/include/ "qoriq-sata2-0.dtsi" +- sata@220000 { +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */ +- }; +- +-/include/ "qoriq-sata2-1.dtsi" +- sata@221000 { +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */ +- }; +-/include/ "qoriq-sec4.2-0.dtsi" +- crypto@300000 { +- fsl,iommu-parent = <&pamu1>; +- }; +- +-/include/ "qoriq-qman1.dtsi" +-/include/ "qoriq-bman1.dtsi" +- +-/include/ "qoriq-raid1.0-0.dtsi" +- raideng@320000 { +- fsl,iommu-parent = <&pamu1>; +- }; +- +-/include/ "qoriq-fman-0.dtsi" +-/include/ "qoriq-fman-0-1g-0.dtsi" +-/include/ "qoriq-fman-0-1g-1.dtsi" +-/include/ "qoriq-fman-0-1g-2.dtsi" +-/include/ "qoriq-fman-0-1g-3.dtsi" +-/include/ "qoriq-fman-0-1g-4.dtsi" +-/include/ "qoriq-fman-0-10g-0.dtsi" +- fman@400000 { +- enet0: ethernet@e0000 { +- }; +- +- enet1: ethernet@e2000 { +- }; +- +- enet2: ethernet@e4000 { +- }; +- +- enet3: ethernet@e6000 { +- }; +- +- enet4: ethernet@e8000 { +- }; +- +- enet5: ethernet@f0000 { +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p5020si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p5020si-pre.dtsi +deleted file mode 100644 +index 2d74ea85e5df..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p5020si-pre.dtsi ++++ /dev/null +@@ -1,117 +0,0 @@ +-/* +- * P5020/P5010 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e5500_power_isa.dtsi" +- +-/ { +- compatible = "fsl,P5020"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- ccsr = &soc; +- dcsr = &dcsr; +- +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- pci3 = &pci3; +- usb0 = &usb0; +- usb1 = &usb1; +- dma0 = &dma0; +- dma1 = &dma1; +- sdhc = &sdhc; +- msi0 = &msi0; +- msi1 = &msi1; +- msi2 = &msi2; +- +- crypto = &crypto; +- sec_jr0 = &sec_jr0; +- sec_jr1 = &sec_jr1; +- sec_jr2 = &sec_jr2; +- sec_jr3 = &sec_jr3; +- rtic_a = &rtic_a; +- rtic_b = &rtic_b; +- rtic_c = &rtic_c; +- rtic_d = &rtic_d; +- sec_mon = &sec_mon; +- +- raideng = &raideng; +- raideng_jr0 = &raideng_jr0; +- raideng_jr1 = &raideng_jr1; +- raideng_jr2 = &raideng_jr2; +- raideng_jr3 = &raideng_jr3; +- +- fman0 = &fman0; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- ethernet4 = &enet4; +- ethernet5 = &enet5; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: PowerPC,e5500@0 { +- device_type = "cpu"; +- reg = <0>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_0>; +- fsl,portid-mapping = <0x80000000>; +- L2_0: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu1: PowerPC,e5500@1 { +- device_type = "cpu"; +- reg = <1>; +- clocks = <&clockgen 1 1>; +- next-level-cache = <&L2_1>; +- fsl,portid-mapping = <0x40000000>; +- L2_1: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p5040ds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/p5040ds.dts +deleted file mode 100644 +index 30850b3228e0..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p5040ds.dts ++++ /dev/null +@@ -1,486 +0,0 @@ +-/* +- * P5040DS Device Tree Source +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * This software is provided by Freescale Semiconductor "as is" and any +- * express or implied warranties, including, but not limited to, the implied +- * warranties of merchantability and fitness for a particular purpose are +- * disclaimed. In no event shall Freescale Semiconductor be liable for any +- * direct, indirect, incidental, special, exemplary, or consequential damages +- * (including, but not limited to, procurement of substitute goods or services; +- * loss of use, data, or profits; or business interruption) however caused and +- * on any theory of liability, whether in contract, strict liability, or tort +- * (including negligence or otherwise) arising in any way out of the use of this +- * software, even if advised of the possibility of such damage. +- */ +- +-/include/ "p5040si-pre.dtsi" +- +-/ { +- model = "fsl,P5040DS"; +- compatible = "fsl,P5040DS"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases{ +- phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c; +- phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d; +- phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e; +- phy_sgmii_slot2_1f = &phy_sgmii_slot2_1f; +- phy_sgmii_slot3_1c = &phy_sgmii_slot3_1c; +- phy_sgmii_slot3_1d = &phy_sgmii_slot3_1d; +- phy_sgmii_slot3_1e = &phy_sgmii_slot3_1e; +- phy_sgmii_slot3_1f = &phy_sgmii_slot3_1f; +- phy_sgmii_slot5_1c = &phy_sgmii_slot5_1c; +- phy_sgmii_slot5_1d = &phy_sgmii_slot5_1d; +- phy_sgmii_slot5_1e = &phy_sgmii_slot5_1e; +- phy_sgmii_slot5_1f = &phy_sgmii_slot5_1f; +- phy_sgmii_slot6_1c = &phy_sgmii_slot6_1c; +- phy_sgmii_slot6_1d = &phy_sgmii_slot6_1d; +- phy_sgmii_slot6_1e = &phy_sgmii_slot6_1e; +- phy_sgmii_slot6_1f = &phy_sgmii_slot6_1f; +- hydra_rg = &hydra_rg; +- hydra_sg_slot2 = &hydra_sg_slot2; +- hydra_sg_slot3 = &hydra_sg_slot3; +- hydra_sg_slot5 = &hydra_sg_slot5; +- hydra_sg_slot6 = &hydra_sg_slot6; +- hydra_xg_slot1 = &hydra_xg_slot1; +- hydra_xg_slot2 = &hydra_xg_slot2; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01008000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x200000>; +- }; +- +- qportals: qman-portals@ff4200000 { +- ranges = <0x0 0xf 0xf4200000 0x200000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- spi@110000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25sl12801", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; /* input clock */ +- partition@u-boot { +- label = "u-boot"; +- reg = <0x00000000 0x00100000>; +- }; +- partition@kernel { +- label = "kernel"; +- reg = <0x00100000 0x00500000>; +- }; +- partition@dtb { +- label = "dtb"; +- reg = <0x00600000 0x00100000>; +- }; +- partition@fs { +- label = "file system"; +- reg = <0x00700000 0x00900000>; +- }; +- }; +- }; +- +- i2c@118100 { +- eeprom@51 { +- compatible = "atmel,24c256"; +- reg = <0x51>; +- }; +- eeprom@52 { +- compatible = "atmel,24c256"; +- reg = <0x52>; +- }; +- }; +- +- i2c@119100 { +- rtc@68 { +- compatible = "dallas,ds3232"; +- reg = <0x68>; +- interrupts = <0x1 0x1 0 0>; +- }; +- ina220@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <1000>; +- }; +- ina220@41 { +- compatible = "ti,ina220"; +- reg = <0x41>; +- shunt-resistor = <1000>; +- }; +- ina220@44 { +- compatible = "ti,ina220"; +- reg = <0x44>; +- shunt-resistor = <1000>; +- }; +- ina220@45 { +- compatible = "ti,ina220"; +- reg = <0x45>; +- shunt-resistor = <1000>; +- }; +- adt7461@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- }; +- +- fman@400000 { +- ethernet@e0000 { +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e2000 { +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e4000 { +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e6000 { +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e8000 { +- phy-handle = <&phy_rgmii_0>; +- phy-connection-type = "rgmii"; +- }; +- +- ethernet@f0000 { +- phy-handle = <&phy_xgmii_slot_2>; +- phy-connection-type = "xgmii"; +- }; +- }; +- +- fman@500000 { +- ethernet@e0000 { +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e2000 { +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e4000 { +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e6000 { +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e8000 { +- phy-handle = <&phy_rgmii_1>; +- phy-connection-type = "rgmii"; +- }; +- +- ethernet@f0000 { +- phy-handle = <&phy_xgmii_slot_1>; +- phy-connection-type = "xgmii"; +- }; +- }; +- }; +- +- lbc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x1000>; +- ranges = <0 0 0xf 0xe8000000 0x08000000 +- 2 0 0xf 0xffa00000 0x00040000 +- 3 0 0xf 0xffdf0000 0x00008000>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x08000000>; +- bank-width = <2>; +- device-width = <2>; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,elbc-fcm-nand"; +- reg = <0x2 0x0 0x40000>; +- +- partition@0 { +- label = "NAND U-Boot Image"; +- reg = <0x0 0x02000000>; +- }; +- +- partition@2000000 { +- label = "NAND Root File System"; +- reg = <0x02000000 0x10000000>; +- }; +- +- partition@12000000 { +- label = "NAND Compressed RFS Image"; +- reg = <0x12000000 0x08000000>; +- }; +- +- partition@1a000000 { +- label = "NAND Linux Kernel Image"; +- reg = <0x1a000000 0x04000000>; +- }; +- +- partition@1e000000 { +- label = "NAND DTB Image"; +- reg = <0x1e000000 0x01000000>; +- }; +- +- partition@1f000000 { +- label = "NAND Writable User area"; +- reg = <0x1f000000 0x01000000>; +- }; +- }; +- +- board-control@3,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis"; +- reg = <3 0 0x40>; +- ranges = <0 3 0 0x40>; +- +- mdio-mux-emi1 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "mdio-mux-mmioreg", "mdio-mux"; +- mdio-parent-bus = <&mdio0>; +- reg = <9 1>; +- mux-mask = <0x78>; +- +- hydra_rg:rgmii-mdio@8 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <8>; +- status = "disabled"; +- +- phy_rgmii_0: ethernet-phy@0 { +- reg = <0x0>; +- }; +- +- phy_rgmii_1: ethernet-phy@1 { +- reg = <0x1>; +- }; +- }; +- +- hydra_sg_slot2: sgmii-mdio@28 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x28>; +- status = "disabled"; +- +- phy_sgmii_slot2_1c: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy_sgmii_slot2_1d: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy_sgmii_slot2_1e: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy_sgmii_slot2_1f: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- +- hydra_sg_slot3: sgmii-mdio@68 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x68>; +- status = "disabled"; +- +- phy_sgmii_slot3_1c: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy_sgmii_slot3_1d: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy_sgmii_slot3_1e: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy_sgmii_slot3_1f: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- +- hydra_sg_slot5: sgmii-mdio@38 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x38>; +- status = "disabled"; +- +- phy_sgmii_slot5_1c: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy_sgmii_slot5_1d: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy_sgmii_slot5_1e: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy_sgmii_slot5_1f: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- hydra_sg_slot6: sgmii-mdio@48 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x48>; +- status = "disabled"; +- +- phy_sgmii_slot6_1c: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy_sgmii_slot6_1d: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy_sgmii_slot6_1e: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy_sgmii_slot6_1f: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- }; +- +- mdio-mux-emi2 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "mdio-mux-mmioreg", "mdio-mux"; +- mdio-parent-bus = <&xmdio0>; +- reg = <9 1>; +- mux-mask = <0x06>; +- +- hydra_xg_slot1: hydra-xg-slot1@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- status = "disabled"; +- +- phy_xgmii_slot_1: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <4>; +- }; +- }; +- +- hydra_xg_slot2: hydra-xg-slot2@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- +- phy_xgmii_slot_2: ethernet-phy@4 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0>; +- }; +- }; +- }; +- }; +- }; +- +- pci0: pcie@ffe200000 { +- reg = <0xf 0xfe200000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci1: pcie@ffe201000 { +- reg = <0xf 0xfe201000 0 0x1000>; +- ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 +- 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci2: pcie@ffe202000 { +- reg = <0xf 0xfe202000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +-}; +- +-/include/ "p5040si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p5040si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p5040si-post.dtsi +deleted file mode 100644 +index 16b454b504e2..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p5040si-post.dtsi ++++ /dev/null +@@ -1,462 +0,0 @@ +-/* +- * P5040 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * This software is provided by Freescale Semiconductor "as is" and any +- * express or implied warranties, including, but not limited to, the implied +- * warranties of merchantability and fitness for a particular purpose are +- * disclaimed. In no event shall Freescale Semiconductor be liable for any +- * direct, indirect, incidental, special, exemplary, or consequential damages +- * (including, but not limited to, procurement of substitute goods or services; +- * loss of use, data, or profits; or business interruption) however caused and +- * on any theory of liability, whether in contract, strict liability, or tort +- * (including negligence or otherwise) arising in any way out of the use of this +- * software, even if advised of the possibility of such damage. +- */ +- +-&bman_fbpr { +- compatible = "fsl,bman-fbpr"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&qman_fqd { +- compatible = "fsl,qman-fqd"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&qman_pfdr { +- compatible = "fsl,qman-pfdr"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&lbc { +- compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus"; +- interrupts = <25 2 0 0>; +- #address-cells = <2>; +- #size-cells = <1>; +-}; +- +-/* controller at 0x200000 */ +-&pci0 { +- compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 1 15>; +- fsl,iommu-parent = <&pamu0>; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 1 15>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 40 1 0 0 +- 0000 0 0 2 &mpic 1 1 0 0 +- 0000 0 0 3 &mpic 2 1 0 0 +- 0000 0 0 4 &mpic 3 1 0 0 +- >; +- }; +-}; +- +-/* controller at 0x201000 */ +-&pci1 { +- compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 1 14>; +- fsl,iommu-parent = <&pamu0>; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 1 14>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 41 1 0 0 +- 0000 0 0 2 &mpic 5 1 0 0 +- 0000 0 0 3 &mpic 6 1 0 0 +- 0000 0 0 4 &mpic 7 1 0 0 +- >; +- }; +-}; +- +-/* controller at 0x202000 */ +-&pci2 { +- compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- clock-frequency = <33333333>; +- interrupts = <16 2 1 13>; +- fsl,iommu-parent = <&pamu0>; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <16 2 1 13>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 42 1 0 0 +- 0000 0 0 2 &mpic 9 1 0 0 +- 0000 0 0 3 &mpic 10 1 0 0 +- 0000 0 0 4 &mpic 11 1 0 0 +- >; +- }; +-}; +- +-&dcsr { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,dcsr", "simple-bus"; +- +- dcsr-epu@0 { +- compatible = "fsl,p5040-dcsr-epu", "fsl,dcsr-epu"; +- interrupts = <52 2 0 0 +- 84 2 0 0 +- 85 2 0 0>; +- reg = <0x0 0x1000>; +- }; +- dcsr-npc { +- compatible = "fsl,dcsr-npc"; +- reg = <0x1000 0x1000 0x1000000 0x8000>; +- }; +- dcsr-nxc@2000 { +- compatible = "fsl,dcsr-nxc"; +- reg = <0x2000 0x1000>; +- }; +- dcsr-corenet { +- compatible = "fsl,dcsr-corenet"; +- reg = <0x8000 0x1000 0xB0000 0x1000>; +- }; +- dcsr-dpaa@9000 { +- compatible = "fsl,p5040-dcsr-dpaa", "fsl,dcsr-dpaa"; +- reg = <0x9000 0x1000>; +- }; +- dcsr-ocn@11000 { +- compatible = "fsl,p5040-dcsr-ocn", "fsl,dcsr-ocn"; +- reg = <0x11000 0x1000>; +- }; +- dcsr-ddr@12000 { +- compatible = "fsl,dcsr-ddr"; +- dev-handle = <&ddr1>; +- reg = <0x12000 0x1000>; +- }; +- dcsr-ddr@13000 { +- compatible = "fsl,dcsr-ddr"; +- dev-handle = <&ddr2>; +- reg = <0x13000 0x1000>; +- }; +- dcsr-nal@18000 { +- compatible = "fsl,p5040-dcsr-nal", "fsl,dcsr-nal"; +- reg = <0x18000 0x1000>; +- }; +- dcsr-rcpm@22000 { +- compatible = "fsl,p5040-dcsr-rcpm", "fsl,dcsr-rcpm"; +- reg = <0x22000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@40000 { +- compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu0>; +- reg = <0x40000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@41000 { +- compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu1>; +- reg = <0x41000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@42000 { +- compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu2>; +- reg = <0x42000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@43000 { +- compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu3>; +- reg = <0x43000 0x1000>; +- }; +-}; +- +-/include/ "qoriq-bman1-portals.dtsi" +- +-/include/ "qoriq-qman1-portals.dtsi" +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- +- soc-sram-error { +- compatible = "fsl,soc-sram-error"; +- interrupts = <16 2 1 29>; +- }; +- +- corenet-law@0 { +- compatible = "fsl,corenet-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <32>; +- }; +- +- ddr1: memory-controller@8000 { +- compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; +- reg = <0x8000 0x1000>; +- interrupts = <16 2 1 23>; +- }; +- +- ddr2: memory-controller@9000 { +- compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller"; +- reg = <0x9000 0x1000>; +- interrupts = <16 2 1 22>; +- }; +- +- cpc: l3-cache-controller@10000 { +- compatible = "fsl,p5040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache"; +- reg = <0x10000 0x1000 +- 0x11000 0x1000>; +- interrupts = <16 2 1 27 +- 16 2 1 26>; +- }; +- +- corenet-cf@18000 { +- compatible = "fsl,corenet1-cf", "fsl,corenet-cf"; +- reg = <0x18000 0x1000>; +- interrupts = <16 2 1 31>; +- fsl,ccf-num-csdids = <32>; +- fsl,ccf-num-snoopids = <32>; +- }; +- +- iommu@20000 { +- compatible = "fsl,pamu-v1.0", "fsl,pamu"; +- reg = <0x20000 0x5000>; /* for compatibility with older PAMU drivers */ +- ranges = <0 0x20000 0x5000>; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupts = <24 2 0 0 +- 16 2 1 30>; +- fsl,portid-mapping = <0x0f800000>; +- +- pamu0: pamu@0 { +- reg = <0 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- +- pamu1: pamu@1000 { +- reg = <0x1000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- +- pamu2: pamu@2000 { +- reg = <0x2000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- +- pamu3: pamu@3000 { +- reg = <0x3000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- +- pamu4: pamu@4000 { +- reg = <0x4000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- }; +- +-/include/ "qoriq-mpic.dtsi" +- +- guts: global-utilities@e0000 { +- compatible = "fsl,p5040-device-config", "fsl,qoriq-device-config-1.0"; +- reg = <0xe0000 0xe00>; +- fsl,has-rstcr; +- #sleep-cells = <1>; +- fsl,liodn-bits = <12>; +- }; +- +- pins: global-utilities@e0e00 { +- compatible = "fsl,p5040-pin-control", "fsl,qoriq-pin-control-1.0"; +- reg = <0xe0e00 0x200>; +- #sleep-cells = <2>; +- }; +- +-/include/ "qoriq-clockgen1.dtsi" +- global-utilities@e1000 { +- compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0"; +- }; +- +- rcpm: global-utilities@e2000 { +- compatible = "fsl,p5040-rcpm", "fsl,qoriq-rcpm-1.0"; +- reg = <0xe2000 0x1000>; +- #sleep-cells = <1>; +- }; +- +- sfp: sfp@e8000 { +- compatible = "fsl,p5040-sfp", "fsl,qoriq-sfp-1.0"; +- reg = <0xe8000 0x1000>; +- }; +- +- serdes: serdes@ea000 { +- compatible = "fsl,p5040-serdes"; +- reg = <0xea000 0x1000>; +- }; +- +-/include/ "qoriq-dma-0.dtsi" +- dma@100300 { +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ +- }; +- +-/include/ "qoriq-dma-1.dtsi" +- dma@101300 { +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ +- }; +- +-/include/ "qoriq-espi-0.dtsi" +- spi@110000 { +- fsl,espi-num-chipselects = <4>; +- }; +- +-/include/ "qoriq-esdhc-0.dtsi" +- sdhc@114000 { +- compatible = "fsl,p5040-esdhc", "fsl,esdhc"; +- fsl,iommu-parent = <&pamu2>; +- fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ +- sdhci,auto-cmd12; +- }; +- +-/include/ "qoriq-i2c-0.dtsi" +-/include/ "qoriq-i2c-1.dtsi" +-/include/ "qoriq-duart-0.dtsi" +-/include/ "qoriq-duart-1.dtsi" +-/include/ "qoriq-gpio-0.dtsi" +-/include/ "qoriq-usb2-mph-0.dtsi" +- usb0: usb@210000 { +- compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; +- fsl,iommu-parent = <&pamu4>; +- fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ +- phy_type = "utmi"; +- port0; +- }; +- +-/include/ "qoriq-usb2-dr-0.dtsi" +- usb1: usb@211000 { +- compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; +- fsl,iommu-parent = <&pamu4>; +- fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */ +- dr_mode = "host"; +- phy_type = "utmi"; +- }; +- +-/include/ "qoriq-sata2-0.dtsi" +- sata@220000 { +- fsl,iommu-parent = <&pamu4>; +- fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */ +- }; +- +-/include/ "qoriq-sata2-1.dtsi" +- sata@221000 { +- fsl,iommu-parent = <&pamu4>; +- fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */ +- }; +- +-/include/ "qoriq-sec5.2-0.dtsi" +- crypto@300000 { +- fsl,iommu-parent = <&pamu4>; +- }; +- +-/include/ "qoriq-raid1.0-0.dtsi" +-/include/ "qoriq-qman1.dtsi" +-/include/ "qoriq-bman1.dtsi" +- +-/include/ "qoriq-fman-0.dtsi" +-/include/ "qoriq-fman-0-1g-0.dtsi" +-/include/ "qoriq-fman-0-1g-1.dtsi" +-/include/ "qoriq-fman-0-1g-2.dtsi" +-/include/ "qoriq-fman-0-1g-3.dtsi" +-/include/ "qoriq-fman-0-1g-4.dtsi" +-/include/ "qoriq-fman-0-10g-0.dtsi" +- fman@400000 { +- enet0: ethernet@e0000 { +- }; +- +- enet1: ethernet@e2000 { +- }; +- +- enet2: ethernet@e4000 { +- }; +- +- enet3: ethernet@e6000 { +- }; +- +- enet4: ethernet@e8000 { +- }; +- +- enet5: ethernet@f0000 { +- }; +- }; +- +-/include/ "qoriq-fman-1.dtsi" +-/include/ "qoriq-fman-1-1g-0.dtsi" +-/include/ "qoriq-fman-1-1g-1.dtsi" +-/include/ "qoriq-fman-1-1g-2.dtsi" +-/include/ "qoriq-fman-1-1g-3.dtsi" +-/include/ "qoriq-fman-1-1g-4.dtsi" +-/include/ "qoriq-fman-1-10g-0.dtsi" +- fman@500000 { +- enet6: ethernet@e0000 { +- }; +- +- enet7: ethernet@e2000 { +- }; +- +- enet8: ethernet@e4000 { +- }; +- +- enet9: ethernet@e6000 { +- }; +- +- enet10: ethernet@e8000 { +- }; +- +- enet11: ethernet@f0000 { +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/p5040si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/p5040si-pre.dtsi +deleted file mode 100644 +index ed89dbbdacf0..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/p5040si-pre.dtsi ++++ /dev/null +@@ -1,143 +0,0 @@ +-/* +- * P5040 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * This software is provided by Freescale Semiconductor "as is" and any +- * express or implied warranties, including, but not limited to, the implied +- * warranties of merchantability and fitness for a particular purpose are +- * disclaimed. In no event shall Freescale Semiconductor be liable for any +- * direct, indirect, incidental, special, exemplary, or consequential damages +- * (including, but not limited to, procurement of substitute goods or services; +- * loss of use, data, or profits; or business interruption) however caused and +- * on any theory of liability, whether in contract, strict liability, or tort +- * (including negligence or otherwise) arising in any way out of the use of this +- * software, even if advised of the possibility of such damage. +- */ +- +-/dts-v1/; +- +-/include/ "e5500_power_isa.dtsi" +- +-/ { +- compatible = "fsl,P5040"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- ccsr = &soc; +- dcsr = &dcsr; +- +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- usb0 = &usb0; +- usb1 = &usb1; +- dma0 = &dma0; +- dma1 = &dma1; +- sdhc = &sdhc; +- msi0 = &msi0; +- msi1 = &msi1; +- msi2 = &msi2; +- +- crypto = &crypto; +- sec_jr0 = &sec_jr0; +- sec_jr1 = &sec_jr1; +- sec_jr2 = &sec_jr2; +- sec_jr3 = &sec_jr3; +- rtic_a = &rtic_a; +- rtic_b = &rtic_b; +- rtic_c = &rtic_c; +- rtic_d = &rtic_d; +- sec_mon = &sec_mon; +- +- raideng = &raideng; +- raideng_jr0 = &raideng_jr0; +- raideng_jr1 = &raideng_jr1; +- raideng_jr2 = &raideng_jr2; +- raideng_jr3 = &raideng_jr3; +- +- fman0 = &fman0; +- fman1 = &fman1; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- ethernet4 = &enet4; +- ethernet5 = &enet5; +- ethernet6 = &enet6; +- ethernet7 = &enet7; +- ethernet8 = &enet8; +- ethernet9 = &enet9; +- ethernet10 = &enet10; +- ethernet11 = &enet11; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: PowerPC,e5500@0 { +- device_type = "cpu"; +- reg = <0>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_0>; +- fsl,portid-mapping = <0x80000000>; +- L2_0: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu1: PowerPC,e5500@1 { +- device_type = "cpu"; +- reg = <1>; +- clocks = <&clockgen 1 1>; +- next-level-cache = <&L2_1>; +- fsl,portid-mapping = <0x40000000>; +- L2_1: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu2: PowerPC,e5500@2 { +- device_type = "cpu"; +- reg = <2>; +- clocks = <&clockgen 1 2>; +- next-level-cache = <&L2_2>; +- fsl,portid-mapping = <0x20000000>; +- L2_2: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu3: PowerPC,e5500@3 { +- device_type = "cpu"; +- reg = <3>; +- clocks = <&clockgen 1 3>; +- next-level-cache = <&L2_3>; +- fsl,portid-mapping = <0x10000000>; +- L2_3: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/ppa8548.dts b/scripts/dtc/include-prefixes/powerpc/fsl/ppa8548.dts +deleted file mode 100644 +index f39838d93994..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/ppa8548.dts ++++ /dev/null +@@ -1,160 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * PPA8548 Device Tree Source (36-bit address map) +- * Copyright 2013 Prodrive B.V. +- * +- * Based on: +- * MPC8548 CDS Device Tree Source (36-bit address map) +- * Copyright 2012 Freescale Semiconductor Inc. +- */ +- +-/include/ "mpc8548si-pre.dtsi" +- +-/ { +- model = "ppa8548"; +- compatible = "ppa8548"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- memory { +- device_type = "memory"; +- reg = <0 0 0x0 0x40000000>; +- }; +- +- lbc: localbus@fe0005000 { +- reg = <0xf 0xe0005000 0 0x1000>; +- ranges = <0x0 0x0 0xf 0xff800000 0x00800000>; +- }; +- +- soc: soc8548@fe0000000 { +- ranges = <0 0xf 0xe0000000 0x100000>; +- }; +- +- pci0: pci@fe0008000 { +- /* ppa8548 board doesn't support PCI */ +- status = "disabled"; +- }; +- +- pci1: pci@fe0009000 { +- /* ppa8548 board doesn't support PCI */ +- status = "disabled"; +- }; +- +- pci2: pcie@fe000a000 { +- /* ppa8548 board doesn't support PCI */ +- status = "disabled"; +- }; +- +- rio: rapidio@fe00c0000 { +- reg = <0xf 0xe00c0000 0x0 0x11000>; +- port1 { +- ranges = <0x0 0x0 0x0 0x80000000 0x0 0x40000000>; +- }; +- }; +-}; +- +-&lbc { +- nor@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x00800000>; +- bank-width = <2>; +- device-width = <2>; +- +- partition@0 { +- reg = <0x0 0x7A0000>; +- label = "user"; +- }; +- +- partition@7A0000 { +- reg = <0x7A0000 0x20000>; +- label = "env"; +- read-only; +- }; +- +- partition@7C0000 { +- reg = <0x7C0000 0x40000>; +- label = "u-boot"; +- read-only; +- }; +- }; +-}; +- +-&soc { +- i2c@3000 { +- rtc@6f { +- compatible = "intersil,isl1208"; +- reg = <0x6f>; +- }; +- }; +- +- i2c@3100 { +- }; +- +- /* +- * Only ethernet controller @25000 and @26000 are used. +- * Use alias enet2 and enet3 for the remainig controllers, +- * to stay compatible with mpc8548si-pre.dtsi. +- */ +- enet2: ethernet@24000 { +- status = "disabled"; +- }; +- +- mdio@24520 { +- phy0: ethernet-phy@0 { +- interrupts = <7 1 0 0>; +- reg = <0x0>; +- }; +- phy1: ethernet-phy@1 { +- interrupts = <8 1 0 0>; +- reg = <0x1>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet0: ethernet@25000 { +- tbi-handle = <&tbi1>; +- phy-handle = <&phy0>; +- }; +- +- mdio@25520 { +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet1: ethernet@26000 { +- tbi-handle = <&tbi2>; +- phy-handle = <&phy1>; +- }; +- +- mdio@26520 { +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- enet3: ethernet@27000 { +- status = "disabled"; +- }; +- +- mdio@27520 { +- tbi3: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- crypto@30000 { +- status = "disabled"; +- }; +-}; +- +-/include/ "mpc8548si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-dma-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-dma-0.dtsi +deleted file mode 100644 +index b5b37ad30e75..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-dma-0.dtsi ++++ /dev/null +@@ -1,66 +0,0 @@ +-/* +- * PQ3 DMA device tree stub [ controller @ offset 0x21000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupts = <20 2 0 0>; +- }; +- dma-channel@80 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupts = <21 2 0 0>; +- }; +- dma-channel@100 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupts = <22 2 0 0>; +- }; +- dma-channel@180 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupts = <23 2 0 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-dma-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-dma-1.dtsi +deleted file mode 100644 +index 28cb8a55d807..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-dma-1.dtsi ++++ /dev/null +@@ -1,66 +0,0 @@ +-/* +- * PQ3 DMA device tree stub [ controller @ offset 0xc300 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-dma@c300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,eloplus-dma"; +- reg = <0xc300 0x4>; +- ranges = <0x0 0xc100 0x200>; +- cell-index = <1>; +- dma-channel@0 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupts = <76 2 0 0>; +- }; +- dma-channel@80 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupts = <77 2 0 0>; +- }; +- dma-channel@100 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupts = <78 2 0 0>; +- }; +- dma-channel@180 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupts = <79 2 0 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-duart-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-duart-0.dtsi +deleted file mode 100644 +index 5e268fdb9d1f..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-duart-0.dtsi ++++ /dev/null +@@ -1,51 +0,0 @@ +-/* +- * PQ3 DUART device tree stub [ controller @ offset 0x4000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- interrupts = <42 2 0 0>; +-}; +- +-serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- interrupts = <42 2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-esdhc-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-esdhc-0.dtsi +deleted file mode 100644 +index 5743433e278e..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-esdhc-0.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * PQ3 eSDHC device tree stub [ controller @ offset 0x2e000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-sdhc@2e000 { +- compatible = "fsl,esdhc"; +- reg = <0x2e000 0x1000>; +- interrupts = <72 0x2 0 0>; +- /* Filled in by U-Boot */ +- clock-frequency = <0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-espi-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-espi-0.dtsi +deleted file mode 100644 +index 75854b2e0391..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-espi-0.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * PQ3 eSPI device tree stub [ controller @ offset 0x7000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-spi@7000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc8536-espi"; +- reg = <0x7000 0x1000>; +- interrupts = <59 0x2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec1-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec1-0.dtsi +deleted file mode 100644 +index 3b0650a98478..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec1-0.dtsi ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* +- * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ] +- * +- * Copyright 2011-2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- fsl,magic-packet; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>; +-}; +- +-mdio@24520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x24520 0x20>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec1-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec1-1.dtsi +deleted file mode 100644 +index 96693b41f0f1..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec1-1.dtsi ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* +- * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ] +- * +- * Copyright 2011-2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- fsl,magic-packet; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>; +-}; +- +-mdio@25520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x25520 0x20>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec1-2.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec1-2.dtsi +deleted file mode 100644 +index 6b3fab19da1f..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec1-2.dtsi ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* +- * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ] +- * +- * Copyright 2011-2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-ethernet@26000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <2>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x26000 0x1000>; +- ranges = <0x0 0x26000 0x1000>; +- fsl,magic-packet; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>; +-}; +- +-mdio@26520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x26520 0x20>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec1-3.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec1-3.dtsi +deleted file mode 100644 +index 0da592d93ddd..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec1-3.dtsi ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* +- * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ] +- * +- * Copyright 2011-2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-ethernet@27000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <3>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x27000 0x1000>; +- ranges = <0x0 0x27000 0x1000>; +- fsl,magic-packet; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>; +-}; +- +-mdio@27520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x27520 0x20>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec1-timer-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec1-timer-0.dtsi +deleted file mode 100644 +index efe2ca04bce8..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec1-timer-0.dtsi ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* +- * PQ3 eTSEC Timer (IEEE 1588) device tree stub [ @ offsets 0x24e00 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-ptp_clock@24e00 { +- compatible = "fsl,etsec-ptp"; +- reg = <0x24e00 0xb0>; +- interrupts = <68 2 0 0 69 2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec2-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec2-0.dtsi +deleted file mode 100644 +index 7fcb1ac0f232..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec2-0.dtsi ++++ /dev/null +@@ -1,61 +0,0 @@ +-/* +- * PQ3 eTSEC2 device tree stub [ @ offsets 0x24000/0xb0000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +- +-mdio@24000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,etsec2-mdio"; +- reg = <0x24000 0x1000 0xb0030 0x4>; +-}; +- +-ethernet@b0000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "fsl,etsec2"; +- fsl,num_rx_queues = <0x8>; +- fsl,num_tx_queues = <0x8>; +- fsl,magic-packet; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- ranges; +- +- queue-group@b0000 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xb0000 0x1000>; +- interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec2-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec2-1.dtsi +deleted file mode 100644 +index 9f25427c1527..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec2-1.dtsi ++++ /dev/null +@@ -1,61 +0,0 @@ +-/* +- * PQ3 eTSEC2 device tree stub [ @ offsets 0x25000/0xb1000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +- +-mdio@25000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,etsec2-tbi"; +- reg = <0x25000 0x1000 0xb1030 0x4>; +-}; +- +-ethernet@b1000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "fsl,etsec2"; +- fsl,num_rx_queues = <0x8>; +- fsl,num_tx_queues = <0x8>; +- fsl,magic-packet; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- ranges; +- +- queue-group@b1000 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xb1000 0x1000>; +- interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec2-2.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec2-2.dtsi +deleted file mode 100644 +index cd7c318ab131..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec2-2.dtsi ++++ /dev/null +@@ -1,60 +0,0 @@ +-/* +- * PQ3 eTSEC2 device tree stub [ @ offsets 0x26000/0xb2000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-mdio@26000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,etsec2-tbi"; +- reg = <0x26000 0x1000 0xb1030 0x4>; +-}; +- +-ethernet@b2000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "fsl,etsec2"; +- fsl,num_rx_queues = <0x8>; +- fsl,num_tx_queues = <0x8>; +- fsl,magic-packet; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- ranges; +- +- queue-group@b2000 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xb2000 0x1000>; +- interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec2-grp2-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec2-grp2-0.dtsi +deleted file mode 100644 +index 034ab8fac22f..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec2-grp2-0.dtsi ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* +- * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb4000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&enet0_grp2 { +- queue-group@b4000 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xb4000 0x1000>; +- interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec2-grp2-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec2-grp2-1.dtsi +deleted file mode 100644 +index 3be9ba3b374e..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec2-grp2-1.dtsi ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* +- * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb5000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&enet1_grp2 { +- queue-group@b5000 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xb5000 0x1000>; +- interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec2-grp2-2.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec2-grp2-2.dtsi +deleted file mode 100644 +index 02a33457048c..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-etsec2-grp2-2.dtsi ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* +- * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb6000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&enet2_grp2 { +- queue-group@b6000 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0xb6000 0x1000>; +- interrupts = <25 2 0 0 26 2 0 0 27 2 0 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-gpio-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-gpio-0.dtsi +deleted file mode 100644 +index a1b48546b02d..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-gpio-0.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * PQ3 GPIO device tree stub [ controller @ offset 0xfc00 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-gpio-controller@fc00 { +- #gpio-cells = <2>; +- compatible = "fsl,pq3-gpio"; +- reg = <0xfc00 0x100>; +- interrupts = <47 0x2 0 0>; +- gpio-controller; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-i2c-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-i2c-0.dtsi +deleted file mode 100644 +index d1dd6fb82a78..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-i2c-0.dtsi ++++ /dev/null +@@ -1,43 +0,0 @@ +-/* +- * PQ3 I2C device tree stub [ controller @ offset 0x3000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2 0 0>; +- dfsrr; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-i2c-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-i2c-1.dtsi +deleted file mode 100644 +index a9bd803e2090..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-i2c-1.dtsi ++++ /dev/null +@@ -1,43 +0,0 @@ +-/* +- * PQ3 I2C device tree stub [ controller @ offset 0x3100 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <43 2 0 0>; +- dfsrr; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-mpic-message-B.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-mpic-message-B.dtsi +deleted file mode 100644 +index 1cf0b77b1efe..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-mpic-message-B.dtsi ++++ /dev/null +@@ -1,43 +0,0 @@ +-/* +- * PQ3 MPIC Message (Group B) device tree stub [ controller @ offset 0x42400 ] +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-message@42400 { +- compatible = "fsl,mpic-v3.1-msgr"; +- reg = <0x42400 0x200>; +- interrupts = < +- 0xb4 2 0 0 +- 0xb5 2 0 0 +- 0xb6 2 0 0 +- 0xb7 2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-mpic-timer-B.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-mpic-timer-B.dtsi +deleted file mode 100644 +index 8734cffae1a1..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-mpic-timer-B.dtsi ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* +- * PQ3 MPIC Timer (Group B) device tree stub [ controller @ offset 0x42100 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-timer@42100 { +- compatible = "fsl,mpic-global-timer"; +- reg = <0x42100 0x100 0x42300 4>; +- interrupts = <4 0 3 0 +- 5 0 3 0 +- 6 0 3 0 +- 7 0 3 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-mpic.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-mpic.dtsi +deleted file mode 100644 +index 71c30eb10056..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-mpic.dtsi ++++ /dev/null +@@ -1,79 +0,0 @@ +-/* +- * PQ3 MPIC device tree stub [ controller @ offset 0x40000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <4>; +- reg = <0x40000 0x40000>; +- compatible = "fsl,mpic"; +- device_type = "open-pic"; +- big-endian; +- single-cpu-affinity; +- last-interrupt-source = <255>; +-}; +- +-timer@41100 { +- compatible = "fsl,mpic-global-timer"; +- reg = <0x41100 0x100 0x41300 4>; +- interrupts = <0 0 3 0 +- 1 0 3 0 +- 2 0 3 0 +- 3 0 3 0>; +-}; +- +-message@41400 { +- compatible = "fsl,mpic-v3.1-msgr"; +- reg = <0x41400 0x200>; +- interrupts = < +- 0xb0 2 0 0 +- 0xb1 2 0 0 +- 0xb2 2 0 0 +- 0xb3 2 0 0>; +-}; +- +-msi@41600 { +- compatible = "fsl,mpic-msi"; +- reg = <0x41600 0x80>; +- msi-available-ranges = <0 0x100>; +- interrupts = < +- 0xe0 0 0 0 +- 0xe1 0 0 0 +- 0xe2 0 0 0 +- 0xe3 0 0 0 +- 0xe4 0 0 0 +- 0xe5 0 0 0 +- 0xe6 0 0 0 +- 0xe7 0 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-rmu-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-rmu-0.dtsi +deleted file mode 100644 +index 587ca9ffad7d..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-rmu-0.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * PQ3 RIO Message Unit device tree stub [ controller @ offset 0xd3000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-rmu: rmu@d3000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,srio-rmu"; +- reg = <0xd3000 0x500>; +- ranges = <0x0 0xd3000 0x500>; +- +- message-unit@0 { +- compatible = "fsl,srio-msg-unit"; +- reg = <0x0 0x100>; +- interrupts = < +- 53 2 0 0 /* msg1_tx_irq */ +- 54 2 0 0>;/* msg1_rx_irq */ +- }; +- message-unit@100 { +- compatible = "fsl,srio-msg-unit"; +- reg = <0x100 0x100>; +- interrupts = < +- 55 2 0 0 /* msg2_tx_irq */ +- 56 2 0 0>;/* msg2_rx_irq */ +- }; +- doorbell-unit@400 { +- compatible = "fsl,srio-dbell-unit"; +- reg = <0x400 0x80>; +- interrupts = < +- 49 2 0 0 /* bell_outb_irq */ +- 50 2 0 0>;/* bell_inb_irq */ +- }; +- port-write-unit@4e0 { +- compatible = "fsl,srio-port-write-unit"; +- reg = <0x4e0 0x20>; +- interrupts = <48 2 0 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sata2-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sata2-0.dtsi +deleted file mode 100644 +index 3c28dd08d38b..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sata2-0.dtsi ++++ /dev/null +@@ -1,40 +0,0 @@ +-/* +- * PQ3 SATAv2 device tree stub [ controller @ offset 0x18000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-sata@18000 { +- compatible = "fsl,pq-sata-v2"; +- reg = <0x18000 0x1000>; +- cell-index = <1>; +- interrupts = <74 0x2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sata2-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sata2-1.dtsi +deleted file mode 100644 +index eefaf2855e3b..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sata2-1.dtsi ++++ /dev/null +@@ -1,40 +0,0 @@ +-/* +- * PQ3 SATAv2 device tree stub [ controller @ offset 0x19000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-sata@19000 { +- compatible = "fsl,pq-sata-v2"; +- reg = <0x19000 0x1000>; +- cell-index = <2>; +- interrupts = <41 0x2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sec2.1-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sec2.1-0.dtsi +deleted file mode 100644 +index 02a5c7ae72d0..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sec2.1-0.dtsi ++++ /dev/null +@@ -1,43 +0,0 @@ +-/* +- * PQ3 Sec/Crypto 2.1 device tree stub [ controller @ offset 0x30000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-crypto@30000 { +- compatible = "fsl,sec2.1", "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <45 2 0 0>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0xfe>; +- fsl,descriptor-types-mask = <0x12b0ebf>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sec3.0-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sec3.0-0.dtsi +deleted file mode 100644 +index bba1ba44ccf0..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sec3.0-0.dtsi ++++ /dev/null +@@ -1,45 +0,0 @@ +-/* +- * PQ3 Sec/Crypto 3.0 device tree stub [ controller @ offset 0x30000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-crypto@30000 { +- compatible = "fsl,sec3.0", +- "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", +- "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <45 2 0 0 58 2 0 0>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x9fe>; +- fsl,descriptor-types-mask = <0x3ab0ebf>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sec3.1-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sec3.1-0.dtsi +deleted file mode 100644 +index 8f0a5669bee5..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sec3.1-0.dtsi ++++ /dev/null +@@ -1,45 +0,0 @@ +-/* +- * PQ3 Sec/Crypto 3.1 device tree stub [ controller @ offset 0x30000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-crypto@30000 { +- compatible = "fsl,sec3.1", "fsl,sec3.0", +- "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", +- "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <45 2 0 0 58 2 0 0>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0xbfe>; +- fsl,descriptor-types-mask = <0x3ab0ebf>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sec3.3-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sec3.3-0.dtsi +deleted file mode 100644 +index c227f2748a24..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sec3.3-0.dtsi ++++ /dev/null +@@ -1,45 +0,0 @@ +-/* +- * PQ3 Sec/Crypto 3.3 device tree stub [ controller @ offset 0x30000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-crypto@30000 { +- compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0", +- "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", +- "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <45 2 0 0 58 2 0 0>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x97c>; +- fsl,descriptor-types-mask = <0x3a30abf>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sec4.4-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sec4.4-0.dtsi +deleted file mode 100644 +index bb3d8266b5ce..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-sec4.4-0.dtsi ++++ /dev/null +@@ -1,67 +0,0 @@ +-/* +- * PQ3 Sec/Crypto 4.4 device tree stub [ controller @ offset 0x30000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-crypto@30000 { +- compatible = "fsl,sec-v4.4", "fsl,sec-v4.0"; +- fsl,sec-era = <3>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x30000 0x10000>; +- reg = <0x30000 0x10000>; +- interrupts = <58 2 0 0>; +- +- sec_jr0: jr@1000 { +- compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring"; +- reg = <0x1000 0x1000>; +- interrupts = <45 2 0 0>; +- }; +- +- sec_jr1: jr@2000 { +- compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring"; +- reg = <0x2000 0x1000>; +- interrupts = <45 2 0 0>; +- }; +- +- sec_jr2: jr@3000 { +- compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring"; +- reg = <0x3000 0x1000>; +- interrupts = <45 2 0 0>; +- }; +- +- sec_jr3: jr@4000 { +- compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring"; +- reg = <0x4000 0x1000>; +- interrupts = <45 2 0 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-usb2-dr-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-usb2-dr-0.dtsi +deleted file mode 100644 +index 185ab9dc3ecd..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-usb2-dr-0.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * PQ3 USB DR device tree stub [ controller @ offset 0x22000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-usb@22000 { +- compatible = "fsl-usb2-dr"; +- reg = <0x22000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <28 0x2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-usb2-dr-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/pq3-usb2-dr-1.dtsi +deleted file mode 100644 +index fe24cd612fff..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/pq3-usb2-dr-1.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * PQ3 USB DR device tree stub [ controller @ offset 0x23000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-usb@23000 { +- compatible = "fsl-usb2-dr"; +- reg = <0x23000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <46 0x2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qonverge-usb2-dr-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qonverge-usb2-dr-0.dtsi +deleted file mode 100644 +index fcc7e5b7fd47..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qonverge-usb2-dr-0.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * QorIQ Qonverge USB Host device tree stub [ controller @ offset 0x210000 ] +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-usb0: usb@210000 { +- compatible = "fsl-usb2-dr"; +- reg = <0x210000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <44 0x2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-bman1-portals.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-bman1-portals.dtsi +deleted file mode 100644 +index 5022432ebaa9..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-bman1-portals.dtsi ++++ /dev/null +@@ -1,90 +0,0 @@ +-/* +- * QorIQ BMan Portal device tree stub for 10 portals +- * +- * Copyright 2011 - 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&bportals { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- +- bman-portal@0 { +- compatible = "fsl,bman-portal"; +- reg = <0x0 0x4000>, <0x100000 0x1000>; +- interrupts = <105 2 0 0>; +- }; +- bman-portal@4000 { +- compatible = "fsl,bman-portal"; +- reg = <0x4000 0x4000>, <0x101000 0x1000>; +- interrupts = <107 2 0 0>; +- }; +- bman-portal@8000 { +- compatible = "fsl,bman-portal"; +- reg = <0x8000 0x4000>, <0x102000 0x1000>; +- interrupts = <109 2 0 0>; +- }; +- bman-portal@c000 { +- compatible = "fsl,bman-portal"; +- reg = <0xc000 0x4000>, <0x103000 0x1000>; +- interrupts = <111 2 0 0>; +- }; +- bman-portal@10000 { +- compatible = "fsl,bman-portal"; +- reg = <0x10000 0x4000>, <0x104000 0x1000>; +- interrupts = <113 2 0 0>; +- }; +- bman-portal@14000 { +- compatible = "fsl,bman-portal"; +- reg = <0x14000 0x4000>, <0x105000 0x1000>; +- interrupts = <115 2 0 0>; +- }; +- bman-portal@18000 { +- compatible = "fsl,bman-portal"; +- reg = <0x18000 0x4000>, <0x106000 0x1000>; +- interrupts = <117 2 0 0>; +- }; +- bman-portal@1c000 { +- compatible = "fsl,bman-portal"; +- reg = <0x1c000 0x4000>, <0x107000 0x1000>; +- interrupts = <119 2 0 0>; +- }; +- bman-portal@20000 { +- compatible = "fsl,bman-portal"; +- reg = <0x20000 0x4000>, <0x108000 0x1000>; +- interrupts = <121 2 0 0>; +- }; +- bman-portal@24000 { +- compatible = "fsl,bman-portal"; +- reg = <0x24000 0x4000>, <0x109000 0x1000>; +- interrupts = <123 2 0 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-bman1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-bman1.dtsi +deleted file mode 100644 +index 3b5e3504acb7..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-bman1.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * QorIQ BMan device tree stub [ controller @ offset 0x31a000 ] +- * +- * Copyright 2011 - 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-bman: bman@31a000 { +- compatible = "fsl,bman"; +- reg = <0x31a000 0x1000>; +- interrupts = <16 2 1 2>; +- fsl,bman-portals = <&bportals>; +- memory-region = <&bman_fbpr>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-clockgen1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-clockgen1.dtsi +deleted file mode 100644 +index 463c1ed9ffdd..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-clockgen1.dtsi ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* +- * QorIQ clock control device tree stub [ controller @ offset 0xe1000 ] +- * +- * Copyright 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-clockgen: global-utilities@e1000 { +- compatible = "fsl,qoriq-clockgen-1.0"; +- reg = <0xe1000 0x1000>; +- #clock-cells = <2>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-clockgen2.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-clockgen2.dtsi +deleted file mode 100644 +index 0361050bb56a..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-clockgen2.dtsi ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* +- * QorIQ clock control device tree stub [ controller @ offset 0xe1000 ] +- * +- * Copyright 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-clockgen: global-utilities@e1000 { +- compatible = "fsl,qoriq-clockgen-2.0"; +- reg = <0xe1000 0x1000>; +- #clock-cells = <2>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-dma-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-dma-0.dtsi +deleted file mode 100644 +index 1aebf3ea4ca5..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-dma-0.dtsi ++++ /dev/null +@@ -1,66 +0,0 @@ +-/* +- * QorIQ DMA device tree stub [ controller @ offset 0x100000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-dma0: dma@100300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,eloplus-dma"; +- reg = <0x100300 0x4>; +- ranges = <0x0 0x100100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupts = <28 2 0 0>; +- }; +- dma-channel@80 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupts = <29 2 0 0>; +- }; +- dma-channel@100 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupts = <30 2 0 0>; +- }; +- dma-channel@180 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupts = <31 2 0 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-dma-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-dma-1.dtsi +deleted file mode 100644 +index ecf5e180fe79..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-dma-1.dtsi ++++ /dev/null +@@ -1,66 +0,0 @@ +-/* +- * QorIQ DMA device tree stub [ controller @ offset 0x101000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-dma1: dma@101300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,eloplus-dma"; +- reg = <0x101300 0x4>; +- ranges = <0x0 0x101100 0x200>; +- cell-index = <1>; +- dma-channel@0 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupts = <32 2 0 0>; +- }; +- dma-channel@80 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupts = <33 2 0 0>; +- }; +- dma-channel@100 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupts = <34 2 0 0>; +- }; +- dma-channel@180 { +- compatible = "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupts = <35 2 0 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-duart-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-duart-0.dtsi +deleted file mode 100644 +index 225c07b4e8ab..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-duart-0.dtsi ++++ /dev/null +@@ -1,51 +0,0 @@ +-/* +- * QorIQ DUART device tree stub [ controller @ offset 0x11c000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-serial0: serial@11c500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x11c500 0x100>; +- clock-frequency = <0>; +- interrupts = <36 2 0 0>; +-}; +- +-serial1: serial@11c600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x11c600 0x100>; +- clock-frequency = <0>; +- interrupts = <36 2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-duart-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-duart-1.dtsi +deleted file mode 100644 +index d23233a56b91..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-duart-1.dtsi ++++ /dev/null +@@ -1,51 +0,0 @@ +-/* +- * QorIQ DUART device tree stub [ controller @ offset 0x11d000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-serial2: serial@11d500 { +- cell-index = <2>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x11d500 0x100>; +- clock-frequency = <0>; +- interrupts = <37 2 0 0>; +-}; +- +-serial3: serial@11d600 { +- cell-index = <3>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x11d600 0x100>; +- clock-frequency = <0>; +- interrupts = <37 2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-esdhc-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-esdhc-0.dtsi +deleted file mode 100644 +index 20835ae216c7..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-esdhc-0.dtsi ++++ /dev/null +@@ -1,40 +0,0 @@ +-/* +- * QorIQ eSDHC device tree stub [ controller @ offset 0x114000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-sdhc: sdhc@114000 { +- compatible = "fsl,esdhc"; +- reg = <0x114000 0x1000>; +- interrupts = <48 2 0 0>; +- clock-frequency = <0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-espi-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-espi-0.dtsi +deleted file mode 100644 +index 6db06975e095..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-espi-0.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * QorIQ eSPI device tree stub [ controller @ offset 0x110000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-spi@110000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc8536-espi"; +- reg = <0x110000 0x1000>; +- interrupts = <53 0x2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0-10g-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0-10g-0.dtsi +deleted file mode 100644 +index eb77675c255a..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0-10g-0.dtsi ++++ /dev/null +@@ -1,62 +0,0 @@ +-/* +- * QorIQ FMan 10g port #0 device tree stub [ controller @ offset 0x400000 ] +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@400000 { +- fman0_rx_0x10: port@90000 { +- cell-index = <0x10>; +- compatible = "fsl,fman-v2-port-rx"; +- reg = <0x90000 0x1000>; +- }; +- +- fman0_tx_0x30: port@b0000 { +- cell-index = <0x30>; +- compatible = "fsl,fman-v2-port-tx"; +- reg = <0xb0000 0x1000>; +- }; +- +- ethernet@f0000 { +- cell-index = <0x8>; +- compatible = "fsl,fman-xgec"; +- reg = <0xf0000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>; +- }; +- +- xmdio0: mdio@f1000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-xmdio"; +- reg = <0xf1000 0x1000>; +- interrupts = <101 2 0 0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0-1g-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0-1g-0.dtsi +deleted file mode 100644 +index b965bc219bae..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0-1g-0.dtsi ++++ /dev/null +@@ -1,69 +0,0 @@ +-/* +- * QorIQ FMan 1g port #0 device tree stub [ controller @ offset 0x400000 ] +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@400000 { +- fman0_rx_0x08: port@88000 { +- cell-index = <0x8>; +- compatible = "fsl,fman-v2-port-rx"; +- reg = <0x88000 0x1000>; +- }; +- +- fman0_tx_0x28: port@a8000 { +- cell-index = <0x28>; +- compatible = "fsl,fman-v2-port-tx"; +- reg = <0xa8000 0x1000>; +- }; +- +- ethernet@e0000 { +- cell-index = <0>; +- compatible = "fsl,fman-dtsec"; +- reg = <0xe0000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>; +- tbi-handle = <&tbi0>; +- ptp-timer = <&ptp_timer0>; +- }; +- +- mdio0: mdio@e1120 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-mdio"; +- reg = <0xe1120 0xee0>; +- interrupts = <100 2 0 0>; +- +- tbi0: tbi-phy@8 { +- reg = <0x8>; +- device_type = "tbi-phy"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0-1g-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0-1g-1.dtsi +deleted file mode 100644 +index 9eb6e6dd7cf9..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0-1g-1.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan 1g port #1 device tree stub [ controller @ offset 0x400000 ] +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@400000 { +- fman0_rx_0x09: port@89000 { +- cell-index = <0x9>; +- compatible = "fsl,fman-v2-port-rx"; +- reg = <0x89000 0x1000>; +- }; +- +- fman0_tx_0x29: port@a9000 { +- cell-index = <0x29>; +- compatible = "fsl,fman-v2-port-tx"; +- reg = <0xa9000 0x1000>; +- }; +- +- ethernet@e2000 { +- cell-index = <1>; +- compatible = "fsl,fman-dtsec"; +- reg = <0xe2000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>; +- tbi-handle = <&tbi1>; +- ptp-timer = <&ptp_timer0>; +- }; +- +- mdio@e3120 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-mdio"; +- reg = <0xe3120 0xee0>; +- +- tbi1: tbi-phy@8 { +- reg = <0x8>; +- device_type = "tbi-phy"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0-1g-2.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0-1g-2.dtsi +deleted file mode 100644 +index 092b89936743..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0-1g-2.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan 1g port #2 device tree stub [ controller @ offset 0x400000 ] +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@400000 { +- fman0_rx_0x0a: port@8a000 { +- cell-index = <0xa>; +- compatible = "fsl,fman-v2-port-rx"; +- reg = <0x8a000 0x1000>; +- }; +- +- fman0_tx_0x2a: port@aa000 { +- cell-index = <0x2a>; +- compatible = "fsl,fman-v2-port-tx"; +- reg = <0xaa000 0x1000>; +- }; +- +- ethernet@e4000 { +- cell-index = <2>; +- compatible = "fsl,fman-dtsec"; +- reg = <0xe4000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>; +- tbi-handle = <&tbi2>; +- ptp-timer = <&ptp_timer0>; +- }; +- +- mdio@e5120 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-mdio"; +- reg = <0xe5120 0xee0>; +- +- tbi2: tbi-phy@8 { +- reg = <0x8>; +- device_type = "tbi-phy"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0-1g-3.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0-1g-3.dtsi +deleted file mode 100644 +index 2df0dc876045..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0-1g-3.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan 1g port #3 device tree stub [ controller @ offset 0x400000 ] +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@400000 { +- fman0_rx_0x0b: port@8b000 { +- cell-index = <0xb>; +- compatible = "fsl,fman-v2-port-rx"; +- reg = <0x8b000 0x1000>; +- }; +- +- fman0_tx_0x2b: port@ab000 { +- cell-index = <0x2b>; +- compatible = "fsl,fman-v2-port-tx"; +- reg = <0xab000 0x1000>; +- }; +- +- ethernet@e6000 { +- cell-index = <3>; +- compatible = "fsl,fman-dtsec"; +- reg = <0xe6000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>; +- tbi-handle = <&tbi3>; +- ptp-timer = <&ptp_timer0>; +- }; +- +- mdio@e7120 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-mdio"; +- reg = <0xe7120 0xee0>; +- +- tbi3: tbi-phy@8 { +- reg = <0x8>; +- device_type = "tbi-phy"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0-1g-4.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0-1g-4.dtsi +deleted file mode 100644 +index 5fceb2438fdc..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0-1g-4.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan 1g port #4 device tree stub [ controller @ offset 0x400000 ] +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@400000 { +- fman0_rx_0x0c: port@8c000 { +- cell-index = <0xc>; +- compatible = "fsl,fman-v2-port-rx"; +- reg = <0x8c000 0x1000>; +- }; +- +- fman0_tx_0x2c: port@ac000 { +- cell-index = <0x2c>; +- compatible = "fsl,fman-v2-port-tx"; +- reg = <0xac000 0x1000>; +- }; +- +- ethernet@e8000 { +- cell-index = <4>; +- compatible = "fsl,fman-dtsec"; +- reg = <0xe8000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>; +- tbi-handle = <&tbi4>; +- ptp-timer = <&ptp_timer0>; +- }; +- +- mdio@e9120 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-mdio"; +- reg = <0xe9120 0xee0>; +- +- tbi4: tbi-phy@8 { +- reg = <0x8>; +- device_type = "tbi-phy"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0.dtsi +deleted file mode 100644 +index 9b6cf9149937..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-0.dtsi ++++ /dev/null +@@ -1,104 +0,0 @@ +-/* +- * QorIQ FMan device tree stub [ controller @ offset 0x400000 ] +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman0: fman@400000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- compatible = "fsl,fman"; +- ranges = <0 0x400000 0xfe000>; +- reg = <0x400000 0xfe000>; +- interrupts = <96 2 0 0>, <16 2 1 1>; +- clocks = <&clockgen 3 0>; +- clock-names = "fmanclk"; +- fsl,qman-channel-range = <0x40 0xc>; +- ptimer-handle = <&ptp_timer0>; +- +- muram@0 { +- compatible = "fsl,fman-muram"; +- reg = <0x0 0x28000>; +- }; +- +- fman0_oh_0x1: port@81000 { +- cell-index = <0x1>; +- compatible = "fsl,fman-v2-port-oh"; +- reg = <0x81000 0x1000>; +- }; +- +- fman0_oh_0x2: port@82000 { +- cell-index = <0x2>; +- compatible = "fsl,fman-v2-port-oh"; +- reg = <0x82000 0x1000>; +- }; +- +- fman0_oh_0x3: port@83000 { +- cell-index = <0x3>; +- compatible = "fsl,fman-v2-port-oh"; +- reg = <0x83000 0x1000>; +- }; +- +- fman0_oh_0x4: port@84000 { +- cell-index = <0x4>; +- compatible = "fsl,fman-v2-port-oh"; +- reg = <0x84000 0x1000>; +- }; +- +- fman0_oh_0x5: port@85000 { +- cell-index = <0x5>; +- compatible = "fsl,fman-v2-port-oh"; +- reg = <0x85000 0x1000>; +- status = "disabled"; +- }; +- +- fman0_oh_0x6: port@86000 { +- cell-index = <0x6>; +- compatible = "fsl,fman-v2-port-oh"; +- reg = <0x86000 0x1000>; +- status = "disabled"; +- }; +- +- fman0_oh_0x7: port@87000 { +- cell-index = <0x7>; +- compatible = "fsl,fman-v2-port-oh"; +- reg = <0x87000 0x1000>; +- status = "disabled"; +- }; +-}; +- +-ptp_timer0: ptp-timer@4fe000 { +- compatible = "fsl,fman-ptp-timer"; +- reg = <0x4fe000 0x1000>; +- interrupts = <96 2 0 0>; +- clocks = <&clockgen 3 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1-10g-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1-10g-0.dtsi +deleted file mode 100644 +index 83ae87b69d92..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1-10g-0.dtsi ++++ /dev/null +@@ -1,61 +0,0 @@ +-/* +- * QorIQ FMan 10g port #0 device tree stub [ controller @ offset 0x500000 ] +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@500000 { +- fman1_rx_0x10: port@90000 { +- cell-index = <0x10>; +- compatible = "fsl,fman-v2-port-rx"; +- reg = <0x90000 0x1000>; +- }; +- +- fman1_tx_0x30: port@b0000 { +- cell-index = <0x30>; +- compatible = "fsl,fman-v2-port-tx"; +- reg = <0xb0000 0x1000>; +- }; +- +- ethernet@f0000 { +- cell-index = <0x8>; +- compatible = "fsl,fman-xgec"; +- reg = <0xf0000 0x1000>; +- fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>; +- }; +- +- mdio@f1000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-xmdio"; +- reg = <0xf1000 0x1000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1-1g-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1-1g-0.dtsi +deleted file mode 100644 +index b0f0e36a4eac..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1-1g-0.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan 1g port #0 device tree stub [ controller @ offset 0x500000 ] +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@500000 { +- fman1_rx_0x08: port@88000 { +- cell-index = <0x8>; +- compatible = "fsl,fman-v2-port-rx"; +- reg = <0x88000 0x1000>; +- }; +- +- fman1_tx_0x28: port@a8000 { +- cell-index = <0x28>; +- compatible = "fsl,fman-v2-port-tx"; +- reg = <0xa8000 0x1000>; +- }; +- +- ethernet@e0000 { +- cell-index = <0>; +- compatible = "fsl,fman-dtsec"; +- reg = <0xe0000 0x1000>; +- fsl,fman-ports = <&fman1_rx_0x08 &fman1_tx_0x28>; +- tbi-handle = <&tbi5>; +- ptp-timer = <&ptp_timer1>; +- }; +- +- mdio@e1120 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-mdio"; +- reg = <0xe1120 0xee0>; +- +- tbi5: tbi-phy@8 { +- reg = <0x8>; +- device_type = "tbi-phy"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1-1g-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1-1g-1.dtsi +deleted file mode 100644 +index a3a79f8552a3..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1-1g-1.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan 1g port #1 device tree stub [ controller @ offset 0x500000 ] +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@500000 { +- fman1_rx_0x09: port@89000 { +- cell-index = <0x9>; +- compatible = "fsl,fman-v2-port-rx"; +- reg = <0x89000 0x1000>; +- }; +- +- fman1_tx_0x29: port@a9000 { +- cell-index = <0x29>; +- compatible = "fsl,fman-v2-port-tx"; +- reg = <0xa9000 0x1000>; +- }; +- +- ethernet@e2000 { +- cell-index = <1>; +- compatible = "fsl,fman-dtsec"; +- reg = <0xe2000 0x1000>; +- fsl,fman-ports = <&fman1_rx_0x09 &fman1_tx_0x29>; +- tbi-handle = <&tbi6>; +- ptp-timer = <&ptp_timer1>; +- }; +- +- mdio@e3120 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-mdio"; +- reg = <0xe3120 0xee0>; +- +- tbi6: tbi-phy@8 { +- reg = <0x8>; +- device_type = "tbi-phy"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1-1g-2.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1-1g-2.dtsi +deleted file mode 100644 +index 96a69a84b8a8..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1-1g-2.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan 1g port #2 device tree stub [ controller @ offset 0x500000 ] +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@500000 { +- fman1_rx_0x0a: port@8a000 { +- cell-index = <0xa>; +- compatible = "fsl,fman-v2-port-rx"; +- reg = <0x8a000 0x1000>; +- }; +- +- fman1_tx_0x2a: port@aa000 { +- cell-index = <0x2a>; +- compatible = "fsl,fman-v2-port-tx"; +- reg = <0xaa000 0x1000>; +- }; +- +- ethernet@e4000 { +- cell-index = <2>; +- compatible = "fsl,fman-dtsec"; +- reg = <0xe4000 0x1000>; +- fsl,fman-ports = <&fman1_rx_0x0a &fman1_tx_0x2a>; +- tbi-handle = <&tbi7>; +- ptp-timer = <&ptp_timer1>; +- }; +- +- mdio@e5120 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-mdio"; +- reg = <0xe5120 0xee0>; +- +- tbi7: tbi-phy@8 { +- reg = <0x8>; +- device_type = "tbi-phy"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1-1g-3.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1-1g-3.dtsi +deleted file mode 100644 +index 7405d1940133..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1-1g-3.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan 1g port #3 device tree stub [ controller @ offset 0x500000 ] +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@500000 { +- fman1_rx_0x0b: port@8b000 { +- cell-index = <0xb>; +- compatible = "fsl,fman-v2-port-rx"; +- reg = <0x8b000 0x1000>; +- }; +- +- fman1_tx_0x2b: port@ab000 { +- cell-index = <0x2b>; +- compatible = "fsl,fman-v2-port-tx"; +- reg = <0xab000 0x1000>; +- }; +- +- ethernet@e6000 { +- cell-index = <3>; +- compatible = "fsl,fman-dtsec"; +- reg = <0xe6000 0x1000>; +- fsl,fman-ports = <&fman1_rx_0x0b &fman1_tx_0x2b>; +- tbi-handle = <&tbi8>; +- ptp-timer = <&ptp_timer1>; +- }; +- +- mdio@e7120 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-mdio"; +- reg = <0xe7120 0xee0>; +- +- tbi8: tbi-phy@8 { +- reg = <0x8>; +- device_type = "tbi-phy"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1-1g-4.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1-1g-4.dtsi +deleted file mode 100644 +index f49ad69e5212..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1-1g-4.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan 1g port #4 device tree stub [ controller @ offset 0x500000 ] +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@500000 { +- fman1_rx_0x0c: port@8c000 { +- cell-index = <0xc>; +- compatible = "fsl,fman-v2-port-rx"; +- reg = <0x8c000 0x1000>; +- }; +- +- fman1_tx_0x2c: port@ac000 { +- cell-index = <0x2c>; +- compatible = "fsl,fman-v2-port-tx"; +- reg = <0xac000 0x1000>; +- }; +- +- ethernet@e8000 { +- cell-index = <4>; +- compatible = "fsl,fman-dtsec"; +- reg = <0xe8000 0x1000>; +- fsl,fman-ports = <&fman1_rx_0x0c &fman1_tx_0x2c>; +- tbi-handle = <&tbi9>; +- ptp-timer = <&ptp_timer1>; +- }; +- +- mdio@e9120 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-mdio"; +- reg = <0xe9120 0xee0>; +- +- tbi9: tbi-phy@8 { +- reg = <0x8>; +- device_type = "tbi-phy"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1.dtsi +deleted file mode 100644 +index e95c11ff0417..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman-1.dtsi ++++ /dev/null +@@ -1,104 +0,0 @@ +-/* +- * QorIQ FMan device tree stub [ controller @ offset 0x500000 ] +- * +- * Copyright 2011 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman1: fman@500000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- compatible = "fsl,fman"; +- ranges = <0 0x500000 0xfe000>; +- reg = <0x500000 0xfe000>; +- interrupts = <97 2 0 0>, <16 2 1 0>; +- clocks = <&clockgen 3 1>; +- clock-names = "fmanclk"; +- fsl,qman-channel-range = <0x60 0xc>; +- ptimer-handle = <&ptp_timer1>; +- +- muram@0 { +- compatible = "fsl,fman-muram"; +- reg = <0x0 0x28000>; +- }; +- +- fman1_oh_0x1: port@81000 { +- cell-index = <0x1>; +- compatible = "fsl,fman-v2-port-oh"; +- reg = <0x81000 0x1000>; +- }; +- +- fman1_oh_0x2: port@82000 { +- cell-index = <0x2>; +- compatible = "fsl,fman-v2-port-oh"; +- reg = <0x82000 0x1000>; +- }; +- +- fman1_oh_0x3: port@83000 { +- cell-index = <0x3>; +- compatible = "fsl,fman-v2-port-oh"; +- reg = <0x83000 0x1000>; +- }; +- +- fman1_oh_0x4: port@84000 { +- cell-index = <0x4>; +- compatible = "fsl,fman-v2-port-oh"; +- reg = <0x84000 0x1000>; +- }; +- +- fman1_oh_0x5: port@85000 { +- cell-index = <0x5>; +- compatible = "fsl,fman-v2-port-oh"; +- reg = <0x85000 0x1000>; +- status = "disabled"; +- }; +- +- fman1_oh_0x6: port@86000 { +- cell-index = <0x6>; +- compatible = "fsl,fman-v2-port-oh"; +- reg = <0x86000 0x1000>; +- status = "disabled"; +- }; +- +- fman1_oh_0x7: port@87000 { +- cell-index = <0x7>; +- compatible = "fsl,fman-v2-port-oh"; +- reg = <0x87000 0x1000>; +- status = "disabled"; +- }; +-}; +- +-ptp_timer1: ptp-timer@5fe000 { +- compatible = "fsl,fman-ptp-timer"; +- reg = <0x5fe000 0x1000>; +- interrupts = <97 2 0 0>; +- clocks = <&clockgen 3 1>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi +deleted file mode 100644 +index baa0c503e741..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi ++++ /dev/null +@@ -1,72 +0,0 @@ +-/* +- * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x400000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@400000 { +- fman0_rx_0x08: port@88000 { +- cell-index = <0x8>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x88000 0x1000>; +- fsl,fman-10g-port; +- fsl,fman-best-effort-port; +- }; +- +- fman0_tx_0x28: port@a8000 { +- cell-index = <0x28>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xa8000 0x1000>; +- fsl,fman-10g-port; +- fsl,fman-best-effort-port; +- }; +- +- ethernet@e0000 { +- cell-index = <0>; +- compatible = "fsl,fman-memac"; +- reg = <0xe0000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>; +- ptp-timer = <&ptp_timer0>; +- pcsphy-handle = <&pcsphy0>; +- }; +- +- mdio@e1000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xe1000 0x1000>; +- fsl,erratum-a011043; /* must ignore read errors */ +- +- pcsphy0: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-10g-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-10g-0.dtsi +deleted file mode 100644 +index 93095600e808..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-10g-0.dtsi ++++ /dev/null +@@ -1,69 +0,0 @@ +-/* +- * QorIQ FMan v3 10g port #0 device tree stub [ controller @ offset 0x400000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@400000 { +- fman0_rx_0x10: port@90000 { +- cell-index = <0x10>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x90000 0x1000>; +- fsl,fman-10g-port; +- }; +- +- fman0_tx_0x30: port@b0000 { +- cell-index = <0x30>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xb0000 0x1000>; +- fsl,fman-10g-port; +- }; +- +- ethernet@f0000 { +- cell-index = <0x8>; +- compatible = "fsl,fman-memac"; +- reg = <0xf0000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>; +- pcsphy-handle = <&pcsphy6>; +- }; +- +- mdio@f1000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xf1000 0x1000>; +- fsl,erratum-a011043; /* must ignore read errors */ +- +- pcsphy6: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi +deleted file mode 100644 +index ff4bd38f0645..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi ++++ /dev/null +@@ -1,72 +0,0 @@ +-/* +- * QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x400000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@400000 { +- fman0_rx_0x09: port@89000 { +- cell-index = <0x9>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x89000 0x1000>; +- fsl,fman-10g-port; +- fsl,fman-best-effort-port; +- }; +- +- fman0_tx_0x29: port@a9000 { +- cell-index = <0x29>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xa9000 0x1000>; +- fsl,fman-10g-port; +- fsl,fman-best-effort-port; +- }; +- +- ethernet@e2000 { +- cell-index = <1>; +- compatible = "fsl,fman-memac"; +- reg = <0xe2000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>; +- ptp-timer = <&ptp_timer0>; +- pcsphy-handle = <&pcsphy1>; +- }; +- +- mdio@e3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xe3000 0x1000>; +- fsl,erratum-a011043; /* must ignore read errors */ +- +- pcsphy1: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-10g-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-10g-1.dtsi +deleted file mode 100644 +index 1fa38ed6f59e..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-10g-1.dtsi ++++ /dev/null +@@ -1,69 +0,0 @@ +-/* +- * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@400000 { +- fman0_rx_0x11: port@91000 { +- cell-index = <0x11>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x91000 0x1000>; +- fsl,fman-10g-port; +- }; +- +- fman0_tx_0x31: port@b1000 { +- cell-index = <0x31>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xb1000 0x1000>; +- fsl,fman-10g-port; +- }; +- +- ethernet@f2000 { +- cell-index = <0x9>; +- compatible = "fsl,fman-memac"; +- reg = <0xf2000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>; +- pcsphy-handle = <&pcsphy7>; +- }; +- +- mdio@f3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xf3000 0x1000>; +- fsl,erratum-a011043; /* must ignore read errors */ +- +- pcsphy7: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-1g-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-1g-0.dtsi +deleted file mode 100644 +index a8cc9780c0c4..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-1g-0.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x400000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@400000 { +- fman0_rx_0x08: port@88000 { +- cell-index = <0x8>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x88000 0x1000>; +- }; +- +- fman0_tx_0x28: port@a8000 { +- cell-index = <0x28>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xa8000 0x1000>; +- }; +- +- ethernet@e0000 { +- cell-index = <0>; +- compatible = "fsl,fman-memac"; +- reg = <0xe0000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>; +- ptp-timer = <&ptp_timer0>; +- pcsphy-handle = <&pcsphy0>; +- }; +- +- mdio@e1000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xe1000 0x1000>; +- fsl,erratum-a011043; /* must ignore read errors */ +- +- pcsphy0: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-1g-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-1g-1.dtsi +deleted file mode 100644 +index 8b8bd70c9382..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-1g-1.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x400000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@400000 { +- fman0_rx_0x09: port@89000 { +- cell-index = <0x9>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x89000 0x1000>; +- }; +- +- fman0_tx_0x29: port@a9000 { +- cell-index = <0x29>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xa9000 0x1000>; +- }; +- +- ethernet@e2000 { +- cell-index = <1>; +- compatible = "fsl,fman-memac"; +- reg = <0xe2000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>; +- ptp-timer = <&ptp_timer0>; +- pcsphy-handle = <&pcsphy1>; +- }; +- +- mdio@e3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xe3000 0x1000>; +- fsl,erratum-a011043; /* must ignore read errors */ +- +- pcsphy1: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-1g-2.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-1g-2.dtsi +deleted file mode 100644 +index 619c880b54d8..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-1g-2.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan v3 1g port #2 device tree stub [ controller @ offset 0x400000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@400000 { +- fman0_rx_0x0a: port@8a000 { +- cell-index = <0xa>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x8a000 0x1000>; +- }; +- +- fman0_tx_0x2a: port@aa000 { +- cell-index = <0x2a>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xaa000 0x1000>; +- }; +- +- ethernet@e4000 { +- cell-index = <2>; +- compatible = "fsl,fman-memac"; +- reg = <0xe4000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>; +- ptp-timer = <&ptp_timer0>; +- pcsphy-handle = <&pcsphy2>; +- }; +- +- mdio@e5000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xe5000 0x1000>; +- fsl,erratum-a011043; /* must ignore read errors */ +- +- pcsphy2: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-1g-3.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-1g-3.dtsi +deleted file mode 100644 +index d7ebb73a400d..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-1g-3.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan v3 1g port #3 device tree stub [ controller @ offset 0x400000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@400000 { +- fman0_rx_0x0b: port@8b000 { +- cell-index = <0xb>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x8b000 0x1000>; +- }; +- +- fman0_tx_0x2b: port@ab000 { +- cell-index = <0x2b>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xab000 0x1000>; +- }; +- +- ethernet@e6000 { +- cell-index = <3>; +- compatible = "fsl,fman-memac"; +- reg = <0xe6000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>; +- ptp-timer = <&ptp_timer0>; +- pcsphy-handle = <&pcsphy3>; +- }; +- +- mdio@e7000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xe7000 0x1000>; +- fsl,erratum-a011043; /* must ignore read errors */ +- +- pcsphy3: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-1g-4.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-1g-4.dtsi +deleted file mode 100644 +index b151d696a069..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-1g-4.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan v3 1g port #4 device tree stub [ controller @ offset 0x400000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@400000 { +- fman0_rx_0x0c: port@8c000 { +- cell-index = <0xc>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x8c000 0x1000>; +- }; +- +- fman0_tx_0x2c: port@ac000 { +- cell-index = <0x2c>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xac000 0x1000>; +- }; +- +- ethernet@e8000 { +- cell-index = <4>; +- compatible = "fsl,fman-memac"; +- reg = <0xe8000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>; +- ptp-timer = <&ptp_timer0>; +- pcsphy-handle = <&pcsphy4>; +- }; +- +- mdio@e9000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xe9000 0x1000>; +- fsl,erratum-a011043; /* must ignore read errors */ +- +- pcsphy4: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-1g-5.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-1g-5.dtsi +deleted file mode 100644 +index adc0ae0013a3..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0-1g-5.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan v3 1g port #5 device tree stub [ controller @ offset 0x400000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@400000 { +- fman0_rx_0x0d: port@8d000 { +- cell-index = <0xd>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x8d000 0x1000>; +- }; +- +- fman0_tx_0x2d: port@ad000 { +- cell-index = <0x2d>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xad000 0x1000>; +- }; +- +- ethernet@ea000 { +- cell-index = <5>; +- compatible = "fsl,fman-memac"; +- reg = <0xea000 0x1000>; +- fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>; +- ptp-timer = <&ptp_timer0>; +- pcsphy-handle = <&pcsphy5>; +- }; +- +- mdio@eb000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xeb000 0x1000>; +- fsl,erratum-a011043; /* must ignore read errors */ +- +- pcsphy5: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0.dtsi +deleted file mode 100644 +index d62b36c5a329..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-0.dtsi ++++ /dev/null +@@ -1,109 +0,0 @@ +-/* +- * QorIQ FMan v3 device tree stub [ controller @ offset 0x400000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman0: fman@400000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- compatible = "fsl,fman"; +- ranges = <0 0x400000 0xfe000>; +- reg = <0x400000 0xfe000>; +- interrupts = <96 2 0 0>, <16 2 1 1>; +- clocks = <&clockgen 3 0>; +- clock-names = "fmanclk"; +- fsl,qman-channel-range = <0x800 0x10>; +- ptimer-handle = <&ptp_timer0>; +- +- muram@0 { +- compatible = "fsl,fman-muram"; +- reg = <0x0 0x60000>; +- }; +- +- fman0_oh_0x2: port@82000 { +- cell-index = <0x2>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x82000 0x1000>; +- }; +- +- fman0_oh_0x3: port@83000 { +- cell-index = <0x3>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x83000 0x1000>; +- }; +- +- fman0_oh_0x4: port@84000 { +- cell-index = <0x4>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x84000 0x1000>; +- }; +- +- fman0_oh_0x5: port@85000 { +- cell-index = <0x5>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x85000 0x1000>; +- }; +- +- fman0_oh_0x6: port@86000 { +- cell-index = <0x6>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x86000 0x1000>; +- }; +- +- fman0_oh_0x7: port@87000 { +- cell-index = <0x7>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x87000 0x1000>; +- }; +- +- mdio0: mdio@fc000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xfc000 0x1000>; +- }; +- +- xmdio0: mdio@fd000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xfd000 0x1000>; +- }; +-}; +- +-ptp_timer0: ptp-timer@4fe000 { +- compatible = "fsl,fman-ptp-timer"; +- reg = <0x4fe000 0x1000>; +- interrupts = <96 2 0 0>; +- clocks = <&clockgen 3 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-10g-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-10g-0.dtsi +deleted file mode 100644 +index 435047e0e250..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-10g-0.dtsi ++++ /dev/null +@@ -1,69 +0,0 @@ +-/* +- * QorIQ FMan v3 10g port #0 device tree stub [ controller @ offset 0x500000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@500000 { +- fman1_rx_0x10: port@90000 { +- cell-index = <0x10>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x90000 0x1000>; +- fsl,fman-10g-port; +- }; +- +- fman1_tx_0x30: port@b0000 { +- cell-index = <0x30>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xb0000 0x1000>; +- fsl,fman-10g-port; +- }; +- +- ethernet@f0000 { +- cell-index = <0x8>; +- compatible = "fsl,fman-memac"; +- reg = <0xf0000 0x1000>; +- fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>; +- pcsphy-handle = <&pcsphy14>; +- }; +- +- mdio@f1000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xf1000 0x1000>; +- fsl,erratum-a011043; /* must ignore read errors */ +- +- pcsphy14: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-10g-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-10g-1.dtsi +deleted file mode 100644 +index c098657cca0a..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-10g-1.dtsi ++++ /dev/null +@@ -1,69 +0,0 @@ +-/* +- * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x500000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@500000 { +- fman1_rx_0x11: port@91000 { +- cell-index = <0x11>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x91000 0x1000>; +- fsl,fman-10g-port; +- }; +- +- fman1_tx_0x31: port@b1000 { +- cell-index = <0x31>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xb1000 0x1000>; +- fsl,fman-10g-port; +- }; +- +- ethernet@f2000 { +- cell-index = <0x9>; +- compatible = "fsl,fman-memac"; +- reg = <0xf2000 0x1000>; +- fsl,fman-ports = <&fman1_rx_0x11 &fman1_tx_0x31>; +- pcsphy-handle = <&pcsphy15>; +- }; +- +- mdio@f3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xf3000 0x1000>; +- fsl,erratum-a011043; /* must ignore read errors */ +- +- pcsphy15: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-1g-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-1g-0.dtsi +deleted file mode 100644 +index 9d06824815f3..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-1g-0.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x500000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@500000 { +- fman1_rx_0x08: port@88000 { +- cell-index = <0x8>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x88000 0x1000>; +- }; +- +- fman1_tx_0x28: port@a8000 { +- cell-index = <0x28>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xa8000 0x1000>; +- }; +- +- ethernet@e0000 { +- cell-index = <0>; +- compatible = "fsl,fman-memac"; +- reg = <0xe0000 0x1000>; +- fsl,fman-ports = <&fman1_rx_0x08 &fman1_tx_0x28>; +- ptp-timer = <&ptp_timer1>; +- pcsphy-handle = <&pcsphy8>; +- }; +- +- mdio@e1000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xe1000 0x1000>; +- fsl,erratum-a011043; /* must ignore read errors */ +- +- pcsphy8: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-1g-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-1g-1.dtsi +deleted file mode 100644 +index 70e947730c4b..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-1g-1.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x500000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@500000 { +- fman1_rx_0x09: port@89000 { +- cell-index = <0x9>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x89000 0x1000>; +- }; +- +- fman1_tx_0x29: port@a9000 { +- cell-index = <0x29>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xa9000 0x1000>; +- }; +- +- ethernet@e2000 { +- cell-index = <1>; +- compatible = "fsl,fman-memac"; +- reg = <0xe2000 0x1000>; +- fsl,fman-ports = <&fman1_rx_0x09 &fman1_tx_0x29>; +- ptp-timer = <&ptp_timer1>; +- pcsphy-handle = <&pcsphy9>; +- }; +- +- mdio@e3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xe3000 0x1000>; +- fsl,erratum-a011043; /* must ignore read errors */ +- +- pcsphy9: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-1g-2.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-1g-2.dtsi +deleted file mode 100644 +index ad96e6529595..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-1g-2.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan v3 1g port #2 device tree stub [ controller @ offset 0x500000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@500000 { +- fman1_rx_0x0a: port@8a000 { +- cell-index = <0xa>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x8a000 0x1000>; +- }; +- +- fman1_tx_0x2a: port@aa000 { +- cell-index = <0x2a>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xaa000 0x1000>; +- }; +- +- ethernet@e4000 { +- cell-index = <2>; +- compatible = "fsl,fman-memac"; +- reg = <0xe4000 0x1000>; +- fsl,fman-ports = <&fman1_rx_0x0a &fman1_tx_0x2a>; +- ptp-timer = <&ptp_timer1>; +- pcsphy-handle = <&pcsphy10>; +- }; +- +- mdio@e5000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xe5000 0x1000>; +- fsl,erratum-a011043; /* must ignore read errors */ +- +- pcsphy10: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-1g-3.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-1g-3.dtsi +deleted file mode 100644 +index 034bc4b71f7a..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-1g-3.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan v3 1g port #3 device tree stub [ controller @ offset 0x500000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@500000 { +- fman1_rx_0x0b: port@8b000 { +- cell-index = <0xb>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x8b000 0x1000>; +- }; +- +- fman1_tx_0x2b: port@ab000 { +- cell-index = <0x2b>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xab000 0x1000>; +- }; +- +- ethernet@e6000 { +- cell-index = <3>; +- compatible = "fsl,fman-memac"; +- reg = <0xe6000 0x1000>; +- fsl,fman-ports = <&fman1_rx_0x0b &fman1_tx_0x2b>; +- ptp-timer = <&ptp_timer1>; +- pcsphy-handle = <&pcsphy11>; +- }; +- +- mdio@e7000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xe7000 0x1000>; +- fsl,erratum-a011043; /* must ignore read errors */ +- +- pcsphy11: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-1g-4.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-1g-4.dtsi +deleted file mode 100644 +index 93ca23d82b39..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-1g-4.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan v3 1g port #4 device tree stub [ controller @ offset 0x500000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@500000 { +- fman1_rx_0x0c: port@8c000 { +- cell-index = <0xc>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x8c000 0x1000>; +- }; +- +- fman1_tx_0x2c: port@ac000 { +- cell-index = <0x2c>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xac000 0x1000>; +- }; +- +- ethernet@e8000 { +- cell-index = <4>; +- compatible = "fsl,fman-memac"; +- reg = <0xe8000 0x1000>; +- fsl,fman-ports = <&fman1_rx_0x0c &fman1_tx_0x2c>; +- ptp-timer = <&ptp_timer1>; +- pcsphy-handle = <&pcsphy12>; +- }; +- +- mdio@e9000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xe9000 0x1000>; +- fsl,erratum-a011043; /* must ignore read errors */ +- +- pcsphy12: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-1g-5.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-1g-5.dtsi +deleted file mode 100644 +index 23b3117a2fd2..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1-1g-5.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ FMan v3 1g port #5 device tree stub [ controller @ offset 0x500000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman@500000 { +- fman1_rx_0x0d: port@8d000 { +- cell-index = <0xd>; +- compatible = "fsl,fman-v3-port-rx"; +- reg = <0x8d000 0x1000>; +- }; +- +- fman1_tx_0x2d: port@ad000 { +- cell-index = <0x2d>; +- compatible = "fsl,fman-v3-port-tx"; +- reg = <0xad000 0x1000>; +- }; +- +- ethernet@ea000 { +- cell-index = <5>; +- compatible = "fsl,fman-memac"; +- reg = <0xea000 0x1000>; +- fsl,fman-ports = <&fman1_rx_0x0d &fman1_tx_0x2d>; +- ptp-timer = <&ptp_timer1>; +- pcsphy-handle = <&pcsphy13>; +- }; +- +- mdio@eb000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xeb000 0x1000>; +- fsl,erratum-a011043; /* must ignore read errors */ +- +- pcsphy13: ethernet-phy@0 { +- reg = <0x0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1.dtsi +deleted file mode 100644 +index 310232460500..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3-1.dtsi ++++ /dev/null +@@ -1,109 +0,0 @@ +-/* +- * QorIQ FMan v3 device tree stub [ controller @ offset 0x500000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman1: fman@500000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- compatible = "fsl,fman"; +- ranges = <0 0x500000 0xfe000>; +- reg = <0x500000 0xfe000>; +- interrupts = <97 2 0 0>, <16 2 1 0>; +- clocks = <&clockgen 3 1>; +- clock-names = "fmanclk"; +- fsl,qman-channel-range = <0x820 0x10>; +- ptimer-handle = <&ptp_timer1>; +- +- muram@0 { +- compatible = "fsl,fman-muram"; +- reg = <0x0 0x60000>; +- }; +- +- fman1_oh_0x2: port@82000 { +- cell-index = <0x2>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x82000 0x1000>; +- }; +- +- fman1_oh_0x3: port@83000 { +- cell-index = <0x3>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x83000 0x1000>; +- }; +- +- fman1_oh_0x4: port@84000 { +- cell-index = <0x4>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x84000 0x1000>; +- }; +- +- fman1_oh_0x5: port@85000 { +- cell-index = <0x5>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x85000 0x1000>; +- }; +- +- fman1_oh_0x6: port@86000 { +- cell-index = <0x6>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x86000 0x1000>; +- }; +- +- fman1_oh_0x7: port@87000 { +- cell-index = <0x7>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x87000 0x1000>; +- }; +- +- mdio1: mdio@fc000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xfc000 0x1000>; +- }; +- +- mdio@fd000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xfd000 0x1000>; +- }; +-}; +- +-ptp_timer1: ptp-timer@5fe000 { +- compatible = "fsl,fman-ptp-timer"; +- reg = <0x5fe000 0x1000>; +- interrupts = <97 2 0 0>; +- clocks = <&clockgen 3 1>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3l-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3l-0.dtsi +deleted file mode 100644 +index 48e5cd61599c..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-fman3l-0.dtsi ++++ /dev/null +@@ -1,99 +0,0 @@ +-/* +- * QorIQ FMan v3 device tree stub [ controller @ offset 0x400000 ] +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-fman0: fman@400000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- compatible = "fsl,fman"; +- ranges = <0 0x400000 0xfe000>; +- reg = <0x400000 0xfe000>; +- interrupts = <96 2 0 0>, <16 2 1 1>; +- clocks = <&clockgen 3 0>; +- clock-names = "fmanclk"; +- fsl,qman-channel-range = <0x800 0x10>; +- ptimer-handle = <&ptp_timer0>; +- +- muram@0 { +- compatible = "fsl,fman-muram"; +- reg = <0x0 0x30000>; +- }; +- +- fman0_oh_0x2: port@82000 { +- cell-index = <0x2>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x82000 0x1000>; +- }; +- +- fman0_oh_0x3: port@83000 { +- cell-index = <0x3>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x83000 0x1000>; +- }; +- +- fman0_oh_0x4: port@84000 { +- cell-index = <0x4>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x84000 0x1000>; +- }; +- +- fman0_oh_0x5: port@85000 { +- cell-index = <0x5>; +- compatible = "fsl,fman-v3-port-oh"; +- reg = <0x85000 0x1000>; +- }; +- +- mdio0: mdio@fc000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xfc000 0x1000>; +- fsl,erratum-a009885; +- }; +- +- xmdio0: mdio@fd000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; +- reg = <0xfd000 0x1000>; +- fsl,erratum-a009885; +- }; +-}; +- +-ptp_timer0: ptp-timer@4fe000 { +- compatible = "fsl,fman-ptp-timer"; +- reg = <0x4fe000 0x1000>; +- interrupts = <96 2 0 0>; +- clocks = <&clockgen 3 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-gpio-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-gpio-0.dtsi +deleted file mode 100644 +index cf714f5f68bc..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-gpio-0.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * QorIQ GPIO device tree stub [ controller @ offset 0x130000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-gpio0: gpio@130000 { +- compatible = "fsl,qoriq-gpio"; +- reg = <0x130000 0x1000>; +- interrupts = <55 2 0 0>; +- #gpio-cells = <2>; +- gpio-controller; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-gpio-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-gpio-1.dtsi +deleted file mode 100644 +index c2f9cdadb604..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-gpio-1.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * QorIQ GPIO device tree stub [ controller @ offset 0x131000 ] +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-gpio1: gpio@131000 { +- compatible = "fsl,qoriq-gpio"; +- reg = <0x131000 0x1000>; +- interrupts = <54 2 0 0>; +- #gpio-cells = <2>; +- gpio-controller; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-gpio-2.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-gpio-2.dtsi +deleted file mode 100644 +index 33f3ccbac83f..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-gpio-2.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * QorIQ GPIO device tree stub [ controller @ offset 0x132000 ] +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-gpio2: gpio@132000 { +- compatible = "fsl,qoriq-gpio"; +- reg = <0x132000 0x1000>; +- interrupts = <86 2 0 0>; +- #gpio-cells = <2>; +- gpio-controller; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-gpio-3.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-gpio-3.dtsi +deleted file mode 100644 +index 86954e95ea02..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-gpio-3.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * QorIQ GPIO device tree stub [ controller @ offset 0x133000 ] +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-gpio3: gpio@133000 { +- compatible = "fsl,qoriq-gpio"; +- reg = <0x133000 0x1000>; +- interrupts = <87 2 0 0>; +- #gpio-cells = <2>; +- gpio-controller; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-i2c-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-i2c-0.dtsi +deleted file mode 100644 +index 5f9bf7debe4c..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-i2c-0.dtsi ++++ /dev/null +@@ -1,53 +0,0 @@ +-/* +- * QorIQ I2C device tree stub [ controller @ offset 0x118000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-i2c@118000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x118000 0x100>; +- interrupts = <38 2 0 0>; +- dfsrr; +-}; +- +-i2c@118100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x118100 0x100>; +- interrupts = <38 2 0 0>; +- dfsrr; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-i2c-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-i2c-1.dtsi +deleted file mode 100644 +index 7989bf5eeb53..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-i2c-1.dtsi ++++ /dev/null +@@ -1,53 +0,0 @@ +-/* +- * QorIQ I2C device tree stub [ controller @ offset 0x119000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-i2c@119000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <2>; +- compatible = "fsl-i2c"; +- reg = <0x119000 0x100>; +- interrupts = <39 2 0 0>; +- dfsrr; +-}; +- +-i2c@119100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <3>; +- compatible = "fsl-i2c"; +- reg = <0x119100 0x100>; +- interrupts = <39 2 0 0>; +- dfsrr; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-mpic.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-mpic.dtsi +deleted file mode 100644 +index 08f42271f86a..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-mpic.dtsi ++++ /dev/null +@@ -1,106 +0,0 @@ +-/* +- * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <4>; +- reg = <0x40000 0x40000>; +- compatible = "fsl,mpic", "chrp,open-pic"; +- device_type = "open-pic"; +- clock-frequency = <0x0>; +-}; +- +-timer@41100 { +- compatible = "fsl,mpic-global-timer"; +- reg = <0x41100 0x100 0x41300 4>; +- interrupts = <0 0 3 0 +- 1 0 3 0 +- 2 0 3 0 +- 3 0 3 0>; +-}; +- +-msi0: msi@41600 { +- compatible = "fsl,mpic-msi"; +- reg = <0x41600 0x200 0x44140 4>; +- msi-available-ranges = <0 0x100>; +- interrupts = < +- 0xe0 0 0 0 +- 0xe1 0 0 0 +- 0xe2 0 0 0 +- 0xe3 0 0 0 +- 0xe4 0 0 0 +- 0xe5 0 0 0 +- 0xe6 0 0 0 +- 0xe7 0 0 0>; +-}; +- +-msi1: msi@41800 { +- compatible = "fsl,mpic-msi"; +- reg = <0x41800 0x200 0x45140 4>; +- msi-available-ranges = <0 0x100>; +- interrupts = < +- 0xe8 0 0 0 +- 0xe9 0 0 0 +- 0xea 0 0 0 +- 0xeb 0 0 0 +- 0xec 0 0 0 +- 0xed 0 0 0 +- 0xee 0 0 0 +- 0xef 0 0 0>; +-}; +- +-msi2: msi@41a00 { +- compatible = "fsl,mpic-msi"; +- reg = <0x41a00 0x200 0x46140 4>; +- msi-available-ranges = <0 0x100>; +- interrupts = < +- 0xf0 0 0 0 +- 0xf1 0 0 0 +- 0xf2 0 0 0 +- 0xf3 0 0 0 +- 0xf4 0 0 0 +- 0xf5 0 0 0 +- 0xf6 0 0 0 +- 0xf7 0 0 0>; +-}; +- +-timer@42100 { +- compatible = "fsl,mpic-global-timer"; +- reg = <0x42100 0x100 0x42300 4>; +- interrupts = <4 0 3 0 +- 5 0 3 0 +- 6 0 3 0 +- 7 0 3 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-mpic4.3.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-mpic4.3.dtsi +deleted file mode 100644 +index 64f713c24825..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-mpic4.3.dtsi ++++ /dev/null +@@ -1,149 +0,0 @@ +-/* +- * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ] +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <4>; +- reg = <0x40000 0x40000>; +- compatible = "fsl,mpic"; +- device_type = "open-pic"; +- clock-frequency = <0x0>; +-}; +- +-timer@41100 { +- compatible = "fsl,mpic-global-timer"; +- reg = <0x41100 0x100 0x41300 4>; +- interrupts = <0 0 3 0 +- 1 0 3 0 +- 2 0 3 0 +- 3 0 3 0>; +-}; +- +-msi0: msi@41600 { +- compatible = "fsl,mpic-msi-v4.3"; +- reg = <0x41600 0x200 0x44148 4>; +- interrupts = < +- 0xe0 0 0 0 +- 0xe1 0 0 0 +- 0xe2 0 0 0 +- 0xe3 0 0 0 +- 0xe4 0 0 0 +- 0xe5 0 0 0 +- 0xe6 0 0 0 +- 0xe7 0 0 0 +- 0x100 0 0 0 +- 0x101 0 0 0 +- 0x102 0 0 0 +- 0x103 0 0 0 +- 0x104 0 0 0 +- 0x105 0 0 0 +- 0x106 0 0 0 +- 0x107 0 0 0>; +-}; +- +-msi1: msi@41800 { +- compatible = "fsl,mpic-msi-v4.3"; +- reg = <0x41800 0x200 0x45148 4>; +- interrupts = < +- 0xe8 0 0 0 +- 0xe9 0 0 0 +- 0xea 0 0 0 +- 0xeb 0 0 0 +- 0xec 0 0 0 +- 0xed 0 0 0 +- 0xee 0 0 0 +- 0xef 0 0 0 +- 0x108 0 0 0 +- 0x109 0 0 0 +- 0x10a 0 0 0 +- 0x10b 0 0 0 +- 0x10c 0 0 0 +- 0x10d 0 0 0 +- 0x10e 0 0 0 +- 0x10f 0 0 0>; +-}; +- +-msi2: msi@41a00 { +- compatible = "fsl,mpic-msi-v4.3"; +- reg = <0x41a00 0x200 0x46148 4>; +- interrupts = < +- 0xf0 0 0 0 +- 0xf1 0 0 0 +- 0xf2 0 0 0 +- 0xf3 0 0 0 +- 0xf4 0 0 0 +- 0xf5 0 0 0 +- 0xf6 0 0 0 +- 0xf7 0 0 0 +- 0x110 0 0 0 +- 0x111 0 0 0 +- 0x112 0 0 0 +- 0x113 0 0 0 +- 0x114 0 0 0 +- 0x115 0 0 0 +- 0x116 0 0 0 +- 0x117 0 0 0>; +-}; +- +-msi3: msi@41c00 { +- compatible = "fsl,mpic-msi-v4.3"; +- reg = <0x41c00 0x200 0x47148 4>; +- interrupts = < +- 0xf8 0 0 0 +- 0xf9 0 0 0 +- 0xfa 0 0 0 +- 0xfb 0 0 0 +- 0xfc 0 0 0 +- 0xfd 0 0 0 +- 0xfe 0 0 0 +- 0xff 0 0 0 +- 0x118 0 0 0 +- 0x119 0 0 0 +- 0x11a 0 0 0 +- 0x11b 0 0 0 +- 0x11c 0 0 0 +- 0x11d 0 0 0 +- 0x11e 0 0 0 +- 0x11f 0 0 0>; +-}; +- +-timer@42100 { +- compatible = "fsl,mpic-global-timer"; +- reg = <0x42100 0x100 0x42300 4>; +- interrupts = <4 0 3 0 +- 5 0 3 0 +- 6 0 3 0 +- 7 0 3 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-qman1-portals.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-qman1-portals.dtsi +deleted file mode 100644 +index e77e4b4ed53b..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-qman1-portals.dtsi ++++ /dev/null +@@ -1,101 +0,0 @@ +-/* +- * QorIQ QMan Portal device tree stub for 10 portals & 15 pool channels +- * +- * Copyright 2011 - 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&qportals { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- +- qportal0: qman-portal@0 { +- compatible = "fsl,qman-portal"; +- reg = <0x0 0x4000>, <0x100000 0x1000>; +- interrupts = <104 2 0 0>; +- cell-index = <0x0>; +- }; +- qportal1: qman-portal@4000 { +- compatible = "fsl,qman-portal"; +- reg = <0x4000 0x4000>, <0x101000 0x1000>; +- interrupts = <106 2 0 0>; +- cell-index = <1>; +- }; +- qportal2: qman-portal@8000 { +- compatible = "fsl,qman-portal"; +- reg = <0x8000 0x4000>, <0x102000 0x1000>; +- interrupts = <108 2 0 0>; +- cell-index = <2>; +- }; +- qportal3: qman-portal@c000 { +- compatible = "fsl,qman-portal"; +- reg = <0xc000 0x4000>, <0x103000 0x1000>; +- interrupts = <110 2 0 0>; +- cell-index = <3>; +- }; +- qportal4: qman-portal@10000 { +- compatible = "fsl,qman-portal"; +- reg = <0x10000 0x4000>, <0x104000 0x1000>; +- interrupts = <112 2 0 0>; +- cell-index = <4>; +- }; +- qportal5: qman-portal@14000 { +- compatible = "fsl,qman-portal"; +- reg = <0x14000 0x4000>, <0x105000 0x1000>; +- interrupts = <114 2 0 0>; +- cell-index = <5>; +- }; +- qportal6: qman-portal@18000 { +- compatible = "fsl,qman-portal"; +- reg = <0x18000 0x4000>, <0x106000 0x1000>; +- interrupts = <116 2 0 0>; +- cell-index = <6>; +- }; +- +- qportal7: qman-portal@1c000 { +- compatible = "fsl,qman-portal"; +- reg = <0x1c000 0x4000>, <0x107000 0x1000>; +- interrupts = <118 2 0 0>; +- cell-index = <7>; +- }; +- qportal8: qman-portal@20000 { +- compatible = "fsl,qman-portal"; +- reg = <0x20000 0x4000>, <0x108000 0x1000>; +- interrupts = <120 2 0 0>; +- cell-index = <8>; +- }; +- qportal9: qman-portal@24000 { +- compatible = "fsl,qman-portal"; +- reg = <0x24000 0x4000>, <0x109000 0x1000>; +- interrupts = <122 2 0 0>; +- cell-index = <9>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-qman1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-qman1.dtsi +deleted file mode 100644 +index 0695778c4386..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-qman1.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * QorIQ QMan device tree stub [ controller @ offset 0x318000 ] +- * +- * Copyright 2011 - 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-qman: qman@318000 { +- compatible = "fsl,qman"; +- reg = <0x318000 0x1000>; +- interrupts = <16 2 1 3>; +- fsl,qman-portals = <&qportals>; +- memory-region = <&qman_fqd &qman_pfdr>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-qman3.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-qman3.dtsi +deleted file mode 100644 +index b379abd1439d..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-qman3.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * QorIQ QMan rev3 device tree stub [ controller @ offset 0x318000 ] +- * +- * Copyright 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-qman: qman@318000 { +- compatible = "fsl,qman"; +- reg = <0x318000 0x2000>; +- interrupts = <16 2 1 3>; +- fsl,qman-portals = <&qportals>; +- memory-region = <&qman_fqd &qman_pfdr>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-raid1.0-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-raid1.0-0.dtsi +deleted file mode 100644 +index 8d2e8aa6cf8a..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-raid1.0-0.dtsi ++++ /dev/null +@@ -1,85 +0,0 @@ +-/* +- * QorIQ RAID 1.0 device tree stub [ controller @ offset 0x320000 ] +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-raideng: raideng@320000 { +- compatible = "fsl,raideng-v1.0"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x320000 0x10000>; +- ranges = <0 0x320000 0x10000>; +- +- raideng_jq0@1000 { +- compatible = "fsl,raideng-v1.0-job-queue"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x1000 0x1000>; +- ranges = <0x0 0x1000 0x1000>; +- +- raideng_jr0: jr@0 { +- compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring"; +- reg = <0x0 0x400>; +- interrupts = <139 2 0 0>; +- interrupt-parent = <&mpic>; +- }; +- +- raideng_jr1: jr@400 { +- compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-lp-ring"; +- reg = <0x400 0x400>; +- interrupts = <140 2 0 0>; +- interrupt-parent = <&mpic>; +- }; +- }; +- +- raideng_jq1@2000 { +- compatible = "fsl,raideng-v1.0-job-queue"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x2000 0x1000>; +- ranges = <0x0 0x2000 0x1000>; +- +- raideng_jr2: jr@0 { +- compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring"; +- reg = <0x0 0x400>; +- interrupts = <141 2 0 0>; +- interrupt-parent = <&mpic>; +- }; +- +- raideng_jr3: jr@400 { +- compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-lp-ring"; +- reg = <0x400 0x400>; +- interrupts = <142 2 0 0>; +- interrupt-parent = <&mpic>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-rmu-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-rmu-0.dtsi +deleted file mode 100644 +index ca7fec792e53..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-rmu-0.dtsi ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * QorIQ RIO Message Unit device tree stub [ controller @ offset 0xd3000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-rmu: rmu@d3000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,srio-rmu"; +- reg = <0xd3000 0x500>; +- ranges = <0x0 0xd3000 0x500>; +- +- message-unit@0 { +- compatible = "fsl,srio-msg-unit"; +- reg = <0x0 0x100>; +- interrupts = < +- 60 2 0 0 /* msg1_tx_irq */ +- 61 2 0 0>;/* msg1_rx_irq */ +- }; +- message-unit@100 { +- compatible = "fsl,srio-msg-unit"; +- reg = <0x100 0x100>; +- interrupts = < +- 62 2 0 0 /* msg2_tx_irq */ +- 63 2 0 0>;/* msg2_rx_irq */ +- }; +- doorbell-unit@400 { +- compatible = "fsl,srio-dbell-unit"; +- reg = <0x400 0x80>; +- interrupts = < +- 56 2 0 0 /* bell_outb_irq */ +- 57 2 0 0>;/* bell_inb_irq */ +- }; +- port-write-unit@4e0 { +- compatible = "fsl,srio-port-write-unit"; +- reg = <0x4e0 0x20>; +- interrupts = <16 2 1 11>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sata2-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sata2-0.dtsi +deleted file mode 100644 +index b642047fdecf..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sata2-0.dtsi ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* +- * QorIQ SATAv2 device tree stub [ controller @ offset 0x220000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-sata@220000 { +- compatible = "fsl,pq-sata-v2"; +- reg = <0x220000 0x1000>; +- interrupts = <68 0x2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sata2-1.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sata2-1.dtsi +deleted file mode 100644 +index c57370259750..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sata2-1.dtsi ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* +- * QorIQ SATAv2 device tree stub [ controller @ offset 0x221000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-sata@221000 { +- compatible = "fsl,pq-sata-v2"; +- reg = <0x221000 0x1000>; +- interrupts = <69 0x2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sec4.0-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sec4.0-0.dtsi +deleted file mode 100644 +index 02bee5fcbb9a..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sec4.0-0.dtsi ++++ /dev/null +@@ -1,101 +0,0 @@ +-/* +- * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-crypto: crypto@300000 { +- compatible = "fsl,sec-v4.0"; +- fsl,sec-era = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x300000 0x10000>; +- ranges = <0 0x300000 0x10000>; +- interrupts = <92 2 0 0>; +- +- sec_jr0: jr@1000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x1000 0x1000>; +- interrupts = <88 2 0 0>; +- }; +- +- sec_jr1: jr@2000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x2000 0x1000>; +- interrupts = <89 2 0 0>; +- }; +- +- sec_jr2: jr@3000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x3000 0x1000>; +- interrupts = <90 2 0 0>; +- }; +- +- sec_jr3: jr@4000 { +- compatible = "fsl,sec-v4.0-job-ring"; +- reg = <0x4000 0x1000>; +- interrupts = <91 2 0 0>; +- }; +- +- rtic@6000 { +- compatible = "fsl,sec-v4.0-rtic"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x6000 0x100>; +- ranges = <0x0 0x6100 0xe00>; +- +- rtic_a: rtic-a@0 { +- compatible = "fsl,sec-v4.0-rtic-memory"; +- reg = <0x00 0x20 0x100 0x80>; +- }; +- +- rtic_b: rtic-b@20 { +- compatible = "fsl,sec-v4.0-rtic-memory"; +- reg = <0x20 0x20 0x200 0x80>; +- }; +- +- rtic_c: rtic-c@40 { +- compatible = "fsl,sec-v4.0-rtic-memory"; +- reg = <0x40 0x20 0x300 0x80>; +- }; +- +- rtic_d: rtic-d@60 { +- compatible = "fsl,sec-v4.0-rtic-memory"; +- reg = <0x60 0x20 0x500 0x80>; +- }; +- }; +-}; +- +-sec_mon: sec_mon@314000 { +- compatible = "fsl,sec-v4.0-mon"; +- reg = <0x314000 0x1000>; +- interrupts = <93 2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sec4.2-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sec4.2-0.dtsi +deleted file mode 100644 +index 7f7574e53323..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sec4.2-0.dtsi ++++ /dev/null +@@ -1,110 +0,0 @@ +-/* +- * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-crypto: crypto@300000 { +- compatible = "fsl,sec-v4.2", "fsl,sec-v4.0"; +- fsl,sec-era = <3>; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x300000 0x10000>; +- ranges = <0 0x300000 0x10000>; +- interrupts = <92 2 0 0>; +- +- sec_jr0: jr@1000 { +- compatible = "fsl,sec-v4.2-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x1000 0x1000>; +- interrupts = <88 2 0 0>; +- }; +- +- sec_jr1: jr@2000 { +- compatible = "fsl,sec-v4.2-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x2000 0x1000>; +- interrupts = <89 2 0 0>; +- }; +- +- sec_jr2: jr@3000 { +- compatible = "fsl,sec-v4.2-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x3000 0x1000>; +- interrupts = <90 2 0 0>; +- }; +- +- sec_jr3: jr@4000 { +- compatible = "fsl,sec-v4.2-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x4000 0x1000>; +- interrupts = <91 2 0 0>; +- }; +- +- rtic@6000 { +- compatible = "fsl,sec-v4.2-rtic", +- "fsl,sec-v4.0-rtic"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x6000 0x100>; +- ranges = <0x0 0x6100 0xe00>; +- +- rtic_a: rtic-a@0 { +- compatible = "fsl,sec-v4.2-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x00 0x20 0x100 0x80>; +- }; +- +- rtic_b: rtic-b@20 { +- compatible = "fsl,sec-v4.2-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x20 0x20 0x200 0x80>; +- }; +- +- rtic_c: rtic-c@40 { +- compatible = "fsl,sec-v4.2-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x40 0x20 0x300 0x80>; +- }; +- +- rtic_d: rtic-d@60 { +- compatible = "fsl,sec-v4.2-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x60 0x20 0x500 0x80>; +- }; +- }; +-}; +- +-sec_mon: sec_mon@314000 { +- compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon"; +- reg = <0x314000 0x1000>; +- interrupts = <93 2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sec5.0-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sec5.0-0.dtsi +deleted file mode 100644 +index e298efbb0f3e..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sec5.0-0.dtsi ++++ /dev/null +@@ -1,110 +0,0 @@ +-/* +- * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ] +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-crypto: crypto@300000 { +- compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; +- fsl,sec-era = <5>; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x300000 0x10000>; +- ranges = <0 0x300000 0x10000>; +- interrupts = <92 2 0 0>; +- +- sec_jr0: jr@1000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x1000 0x1000>; +- interrupts = <88 2 0 0>; +- }; +- +- sec_jr1: jr@2000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x2000 0x1000>; +- interrupts = <89 2 0 0>; +- }; +- +- sec_jr2: jr@3000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x3000 0x1000>; +- interrupts = <90 2 0 0>; +- }; +- +- sec_jr3: jr@4000 { +- compatible = "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x4000 0x1000>; +- interrupts = <91 2 0 0>; +- }; +- +- rtic@6000 { +- compatible = "fsl,sec-v5.0-rtic", +- "fsl,sec-v4.0-rtic"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x6000 0x100>; +- ranges = <0x0 0x6100 0xe00>; +- +- rtic_a: rtic-a@0 { +- compatible = "fsl,sec-v5.0-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x00 0x20 0x100 0x80>; +- }; +- +- rtic_b: rtic-b@20 { +- compatible = "fsl,sec-v5.0-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x20 0x20 0x200 0x80>; +- }; +- +- rtic_c: rtic-c@40 { +- compatible = "fsl,sec-v5.0-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x40 0x20 0x300 0x80>; +- }; +- +- rtic_d: rtic-d@60 { +- compatible = "fsl,sec-v5.0-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x60 0x20 0x500 0x80>; +- }; +- }; +-}; +- +-sec_mon: sec_mon@314000 { +- compatible = "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon"; +- reg = <0x314000 0x1000>; +- interrupts = <93 2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sec5.2-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sec5.2-0.dtsi +deleted file mode 100644 +index 33ff09d52e05..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sec5.2-0.dtsi ++++ /dev/null +@@ -1,119 +0,0 @@ +-/* +- * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ] +- * +- * Copyright 2011-2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-crypto: crypto@300000 { +- compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0"; +- fsl,sec-era = <5>; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x300000 0x10000>; +- ranges = <0 0x300000 0x10000>; +- interrupts = <92 2 0 0>; +- +- sec_jr0: jr@1000 { +- compatible = "fsl,sec-v5.2-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x1000 0x1000>; +- interrupts = <88 2 0 0>; +- }; +- +- sec_jr1: jr@2000 { +- compatible = "fsl,sec-v5.2-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x2000 0x1000>; +- interrupts = <89 2 0 0>; +- }; +- +- sec_jr2: jr@3000 { +- compatible = "fsl,sec-v5.2-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x3000 0x1000>; +- interrupts = <90 2 0 0>; +- }; +- +- sec_jr3: jr@4000 { +- compatible = "fsl,sec-v5.2-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x4000 0x1000>; +- interrupts = <91 2 0 0>; +- }; +- +- rtic@6000 { +- compatible = "fsl,sec-v5.2-rtic", +- "fsl,sec-v5.0-rtic", +- "fsl,sec-v4.0-rtic"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x6000 0x100>; +- ranges = <0x0 0x6100 0xe00>; +- +- rtic_a: rtic-a@0 { +- compatible = "fsl,sec-v5.2-rtic-memory", +- "fsl,sec-v5.0-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x00 0x20 0x100 0x80>; +- }; +- +- rtic_b: rtic-b@20 { +- compatible = "fsl,sec-v5.2-rtic-memory", +- "fsl,sec-v5.0-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x20 0x20 0x200 0x80>; +- }; +- +- rtic_c: rtic-c@40 { +- compatible = "fsl,sec-v5.2-rtic-memory", +- "fsl,sec-v5.0-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x40 0x20 0x300 0x80>; +- }; +- +- rtic_d: rtic-d@60 { +- compatible = "fsl,sec-v5.2-rtic-memory", +- "fsl,sec-v5.0-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x60 0x20 0x500 0x80>; +- }; +- }; +-}; +- +-sec_mon: sec_mon@314000 { +- compatible = "fsl,sec-v5.2-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon"; +- reg = <0x314000 0x1000>; +- interrupts = <93 2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sec5.3-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sec5.3-0.dtsi +deleted file mode 100644 +index 08778221c194..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sec5.3-0.dtsi ++++ /dev/null +@@ -1,119 +0,0 @@ +-/* +- * QorIQ Sec/Crypto 5.3 device tree stub [ controller @ offset 0x300000 ] +- * +- * Copyright 2012 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-crypto: crypto@300000 { +- compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0"; +- fsl,sec-era = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x300000 0x10000>; +- ranges = <0 0x300000 0x10000>; +- interrupts = <92 2 0 0>; +- +- sec_jr0: jr@1000 { +- compatible = "fsl,sec-v5.3-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x1000 0x1000>; +- interrupts = <88 2 0 0>; +- }; +- +- sec_jr1: jr@2000 { +- compatible = "fsl,sec-v5.3-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x2000 0x1000>; +- interrupts = <89 2 0 0>; +- }; +- +- sec_jr2: jr@3000 { +- compatible = "fsl,sec-v5.3-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x3000 0x1000>; +- interrupts = <90 2 0 0>; +- }; +- +- sec_jr3: jr@4000 { +- compatible = "fsl,sec-v5.3-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x4000 0x1000>; +- interrupts = <91 2 0 0>; +- }; +- +- rtic@6000 { +- compatible = "fsl,sec-v5.3-rtic", +- "fsl,sec-v5.0-rtic", +- "fsl,sec-v4.0-rtic"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x6000 0x100>; +- ranges = <0x0 0x6100 0xe00>; +- +- rtic_a: rtic-a@0 { +- compatible = "fsl,sec-v5.3-rtic-memory", +- "fsl,sec-v5.0-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x00 0x20 0x100 0x80>; +- }; +- +- rtic_b: rtic-b@20 { +- compatible = "fsl,sec-v5.3-rtic-memory", +- "fsl,sec-v5.0-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x20 0x20 0x200 0x80>; +- }; +- +- rtic_c: rtic-c@40 { +- compatible = "fsl,sec-v5.3-rtic-memory", +- "fsl,sec-v5.0-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x40 0x20 0x300 0x80>; +- }; +- +- rtic_d: rtic-d@60 { +- compatible = "fsl,sec-v5.3-rtic-memory", +- "fsl,sec-v5.0-rtic-memory", +- "fsl,sec-v4.0-rtic-memory"; +- reg = <0x60 0x20 0x500 0x80>; +- }; +- }; +-}; +- +-sec_mon: sec_mon@314000 { +- compatible = "fsl,sec-v5.3-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon"; +- reg = <0x314000 0x1000>; +- interrupts = <93 2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sec6.0-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sec6.0-0.dtsi +deleted file mode 100644 +index 7d4a6a2354f4..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-sec6.0-0.dtsi ++++ /dev/null +@@ -1,57 +0,0 @@ +-/* +- * QorIQ Sec/Crypto 6.0 device tree stub +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +- compatible = "fsl,sec-v6.0", "fsl,sec-v5.0", +- "fsl,sec-v4.0"; +- fsl,sec-era = <6>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- jr@1000 { +- compatible = "fsl,sec-v6.0-job-ring", +- "fsl,sec-v5.2-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.4-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x1000 0x1000>; +- }; +- +- jr@2000 { +- compatible = "fsl,sec-v6.0-job-ring", +- "fsl,sec-v5.2-job-ring", +- "fsl,sec-v5.0-job-ring", +- "fsl,sec-v4.4-job-ring", +- "fsl,sec-v4.0-job-ring"; +- reg = <0x2000 0x1000>; +- }; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-usb2-dr-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-usb2-dr-0.dtsi +deleted file mode 100644 +index 4dd6f84c239c..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-usb2-dr-0.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * QorIQ USB DR device tree stub [ controller @ offset 0x211000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-usb@211000 { +- compatible = "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; +- reg = <0x211000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <45 0x2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-usb2-mph-0.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-usb2-mph-0.dtsi +deleted file mode 100644 +index f053835aa1c7..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/qoriq-usb2-mph-0.dtsi ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * QorIQ USB Host device tree stub [ controller @ offset 0x210000 ] +- * +- * Copyright 2011 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-usb@210000 { +- compatible = "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; +- reg = <0x210000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <44 0x2 0 0>; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t1023rdb.dts b/scripts/dtc/include-prefixes/powerpc/fsl/t1023rdb.dts +deleted file mode 100644 +index f82f85c65964..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t1023rdb.dts ++++ /dev/null +@@ -1,232 +0,0 @@ +-/* +- * T1023 RDB Device Tree Source +- * +- * Copyright 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "t102xsi-pre.dtsi" +- +-/ { +- model = "fsl,T1023RDB"; +- compatible = "fsl,T1023RDB"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- ifc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x2000>; +- ranges = <0 0 0xf 0xe8000000 0x08000000 +- 1 0 0xf 0xff800000 0x00010000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- status = "disabled"; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,ifc-nand"; +- reg = <0x1 0x0 0x10000>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01072000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x2000000>; +- }; +- +- qportals: qman-portals@ff6000000 { +- ranges = <0x0 0xf 0xf6000000 0x2000000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- spi@110000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spansion,s25fl512s", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <10000000>; /* input clk */ +- }; +- }; +- +- i2c@118000 { +- eeprom@50 { +- compatible = "st,m24256"; +- reg = <0x50>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- interrupts = <0x5 0x1 0 0>; +- }; +- }; +- +- i2c@118100 { +- current-sensor@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <1000>; +- }; +- +- current-sensor@41 { +- compatible = "ti,ina220"; +- reg = <0x41>; +- shunt-resistor = <1000>; +- }; +- }; +- +- fman@400000 { +- fm1mac1: ethernet@e0000 { +- phy-handle = <&sgmii_rtk_phy2>; +- phy-connection-type = "sgmii"; +- sleep = <&rcpm 0x80000000>; +- }; +- +- fm1mac2: ethernet@e2000 { +- sleep = <&rcpm 0x40000000>; +- }; +- +- fm1mac3: ethernet@e4000 { +- phy-handle = <&sgmii_aqr_phy3>; +- phy-connection-type = "2500base-x"; +- sleep = <&rcpm 0x20000000>; +- }; +- +- fm1mac4: ethernet@e6000 { +- phy-handle = <&rgmii_rtk_phy1>; +- phy-connection-type = "rgmii"; +- sleep = <&rcpm 0x10000000>; +- }; +- +- +- mdio0: mdio@fc000 { +- rgmii_rtk_phy1: ethernet-phy@1 { +- reg = <0x1>; +- }; +- sgmii_rtk_phy2: ethernet-phy@3 { +- reg = <0x3>; +- }; +- }; +- +- xmdio0: mdio@fd000 { +- sgmii_aqr_phy3: ethernet-phy@2 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x2>; +- }; +- }; +- }; +- }; +- +- pci0: pcie@ffe240000 { +- reg = <0xf 0xfe240000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8000000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci1: pcie@ffe250000 { +- reg = <0xf 0xfe250000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci2: pcie@ffe260000 { +- reg = <0xf 0xfe260000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +-}; +- +-#include "t1023si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t1023si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/t1023si-post.dtsi +deleted file mode 100644 +index d552044c5afc..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t1023si-post.dtsi ++++ /dev/null +@@ -1,522 +0,0 @@ +-/* +- * T1023 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#include +- +-&bman_fbpr { +- compatible = "fsl,bman-fbpr"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&qman_fqd { +- compatible = "fsl,qman-fqd"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&qman_pfdr { +- compatible = "fsl,qman-pfdr"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&ifc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,ifc", "simple-bus"; +- interrupts = <25 2 0 0>; +-}; +- +-&pci0 { +- compatible = "fsl,t1023-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- interrupts = <20 2 0 0>; +- fsl,iommu-parent = <&pamu0>; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <20 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 40 1 0 0 +- 0000 0 0 2 &mpic 1 1 0 0 +- 0000 0 0 3 &mpic 2 1 0 0 +- 0000 0 0 4 &mpic 3 1 0 0 +- >; +- }; +-}; +- +-&pci1 { +- compatible = "fsl,t1023-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 0xff>; +- interrupts = <21 2 0 0>; +- fsl,iommu-parent = <&pamu0>; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <21 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 41 1 0 0 +- 0000 0 0 2 &mpic 5 1 0 0 +- 0000 0 0 3 &mpic 6 1 0 0 +- 0000 0 0 4 &mpic 7 1 0 0 +- >; +- }; +-}; +- +-&pci2 { +- compatible = "fsl,t1023-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- interrupts = <22 2 0 0>; +- fsl,iommu-parent = <&pamu0>; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <22 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 42 1 0 0 +- 0000 0 0 2 &mpic 9 1 0 0 +- 0000 0 0 3 &mpic 10 1 0 0 +- 0000 0 0 4 &mpic 11 1 0 0 +- >; +- }; +-}; +- +-&dcsr { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,dcsr", "simple-bus"; +- +- dcsr-epu@0 { +- compatible = "fsl,t1023-dcsr-epu", "fsl,dcsr-epu"; +- interrupts = <52 2 0 0 +- 84 2 0 0 +- 85 2 0 0>; +- reg = <0x0 0x1000>; +- }; +- dcsr-npc { +- compatible = "fsl,t1023-dcsr-cnpc", "fsl,dcsr-cnpc"; +- reg = <0x1000 0x1000 0x1002000 0x10000>; +- }; +- dcsr-nxc@2000 { +- compatible = "fsl,dcsr-nxc"; +- reg = <0x2000 0x1000>; +- }; +- dcsr-corenet { +- compatible = "fsl,dcsr-corenet"; +- reg = <0x8000 0x1000 0x1A000 0x1000>; +- }; +- dcsr-ocn@11000 { +- compatible = "fsl,t1023-dcsr-ocn", "fsl,dcsr-ocn"; +- reg = <0x11000 0x1000>; +- }; +- dcsr-ddr@12000 { +- compatible = "fsl,dcsr-ddr"; +- dev-handle = <&ddr1>; +- reg = <0x12000 0x1000>; +- }; +- dcsr-nal@18000 { +- compatible = "fsl,t1023-dcsr-nal", "fsl,dcsr-nal"; +- reg = <0x18000 0x1000>; +- }; +- dcsr-rcpm@22000 { +- compatible = "fsl,t1023-dcsr-rcpm", "fsl,dcsr-rcpm"; +- reg = <0x22000 0x1000>; +- }; +- dcsr-snpc@30000 { +- compatible = "fsl,t1023-dcsr-snpc", "fsl,dcsr-snpc"; +- reg = <0x30000 0x1000 0x1022000 0x10000>; +- }; +- dcsr-snpc@31000 { +- compatible = "fsl,t1023-dcsr-snpc", "fsl,dcsr-snpc"; +- reg = <0x31000 0x1000 0x1042000 0x10000>; +- }; +- dcsr-cpu-sb-proxy@100000 { +- compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu0>; +- reg = <0x100000 0x1000 0x101000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@108000 { +- compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu1>; +- reg = <0x108000 0x1000 0x109000 0x1000>; +- }; +-}; +- +-&bportals { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- compatible = "simple-bus"; +- +- bman-portal@0 { +- cell-index = <0x0>; +- compatible = "fsl,bman-portal"; +- reg = <0x0 0x4000>, <0x1000000 0x1000>; +- interrupts = <105 2 0 0>; +- }; +- bman-portal@4000 { +- cell-index = <0x1>; +- compatible = "fsl,bman-portal"; +- reg = <0x4000 0x4000>, <0x1001000 0x1000>; +- interrupts = <107 2 0 0>; +- }; +- bman-portal@8000 { +- cell-index = <2>; +- compatible = "fsl,bman-portal"; +- reg = <0x8000 0x4000>, <0x1002000 0x1000>; +- interrupts = <109 2 0 0>; +- }; +- bman-portal@c000 { +- cell-index = <0x3>; +- compatible = "fsl,bman-portal"; +- reg = <0xc000 0x4000>, <0x1003000 0x1000>; +- interrupts = <111 2 0 0>; +- }; +- bman-portal@10000 { +- cell-index = <0x4>; +- compatible = "fsl,bman-portal"; +- reg = <0x10000 0x4000>, <0x1004000 0x1000>; +- interrupts = <113 2 0 0>; +- }; +- bman-portal@14000 { +- cell-index = <0x5>; +- compatible = "fsl,bman-portal"; +- reg = <0x14000 0x4000>, <0x1005000 0x1000>; +- interrupts = <115 2 0 0>; +- }; +-}; +- +-&qportals { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- compatible = "simple-bus"; +- +- qportal0: qman-portal@0 { +- compatible = "fsl,qman-portal"; +- reg = <0x0 0x4000>, <0x1000000 0x1000>; +- interrupts = <104 0x2 0 0>; +- cell-index = <0x0>; +- }; +- qportal1: qman-portal@4000 { +- compatible = "fsl,qman-portal"; +- reg = <0x4000 0x4000>, <0x1001000 0x1000>; +- interrupts = <106 0x2 0 0>; +- cell-index = <0x1>; +- }; +- qportal2: qman-portal@8000 { +- compatible = "fsl,qman-portal"; +- reg = <0x8000 0x4000>, <0x1002000 0x1000>; +- interrupts = <108 0x2 0 0>; +- cell-index = <0x2>; +- }; +- qportal3: qman-portal@c000 { +- compatible = "fsl,qman-portal"; +- reg = <0xc000 0x4000>, <0x1003000 0x1000>; +- interrupts = <110 0x2 0 0>; +- cell-index = <0x3>; +- }; +- qportal4: qman-portal@10000 { +- compatible = "fsl,qman-portal"; +- reg = <0x10000 0x4000>, <0x1004000 0x1000>; +- interrupts = <112 0x2 0 0>; +- cell-index = <0x4>; +- }; +- qportal5: qman-portal@14000 { +- compatible = "fsl,qman-portal"; +- reg = <0x14000 0x4000>, <0x1005000 0x1000>; +- interrupts = <114 0x2 0 0>; +- cell-index = <0x5>; +- }; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- +- soc-sram-error { +- compatible = "fsl,soc-sram-error"; +- interrupts = <16 2 1 29>; +- }; +- +- corenet-law@0 { +- compatible = "fsl,corenet-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <16>; +- }; +- +- ddr1: memory-controller@8000 { +- compatible = "fsl,qoriq-memory-controller-v5.0", +- "fsl,qoriq-memory-controller"; +- reg = <0x8000 0x1000>; +- interrupts = <16 2 1 23>; +- }; +- +- cpc: l3-cache-controller@10000 { +- compatible = "fsl,t1023-l3-cache-controller", "cache"; +- reg = <0x10000 0x1000>; +- interrupts = <16 2 1 27>; +- }; +- +- corenet-cf@18000 { +- compatible = "fsl,corenet2-cf"; +- reg = <0x18000 0x1000>; +- interrupts = <16 2 1 31>; +- }; +- +- iommu@20000 { +- compatible = "fsl,pamu-v1.0", "fsl,pamu"; +- reg = <0x20000 0x1000>; +- ranges = <0 0x20000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupts = < +- 24 2 0 0 +- 16 2 1 30>; +- pamu0: pamu@0 { +- reg = <0 0x1000>; +- fsl,primary-cache-geometry = <128 1>; +- fsl,secondary-cache-geometry = <32 2>; +- }; +- }; +- +-/include/ "qoriq-mpic.dtsi" +- +- guts: global-utilities@e0000 { +- compatible = "fsl,t1023-device-config", "fsl,qoriq-device-config-2.0"; +- reg = <0xe0000 0xe00>; +- fsl,has-rstcr; +- fsl,liodn-bits = <12>; +- }; +- +-/include/ "qoriq-clockgen2.dtsi" +- global-utilities@e1000 { +- compatible = "fsl,t1023-clockgen", "fsl,qoriq-clockgen-2.0"; +- }; +- +- rcpm: global-utilities@e2000 { +- compatible = "fsl,t1023-rcpm", "fsl,qoriq-rcpm-2.1"; +- reg = <0xe2000 0x1000>; +- }; +- +- sfp: sfp@e8000 { +- compatible = "fsl,t1023-sfp"; +- reg = <0xe8000 0x1000>; +- }; +- +- serdes: serdes@ea000 { +- compatible = "fsl,t1023-serdes"; +- reg = <0xea000 0x4000>; +- }; +- +- tmu: tmu@f0000 { +- compatible = "fsl,qoriq-tmu"; +- reg = <0xf0000 0x1000>; +- interrupts = <18 2 0 0>; +- fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>; +- fsl,tmu-calibration = <0x00000000 0x0000000f +- 0x00000001 0x00000017 +- 0x00000002 0x0000001e +- 0x00000003 0x00000026 +- 0x00000004 0x0000002e +- 0x00000005 0x00000035 +- 0x00000006 0x0000003d +- 0x00000007 0x00000044 +- 0x00000008 0x0000004c +- 0x00000009 0x00000053 +- 0x0000000a 0x0000005b +- 0x0000000b 0x00000064 +- +- 0x00010000 0x00000011 +- 0x00010001 0x0000001c +- 0x00010002 0x00000024 +- 0x00010003 0x0000002b +- 0x00010004 0x00000034 +- 0x00010005 0x00000039 +- 0x00010006 0x00000042 +- 0x00010007 0x0000004c +- 0x00010008 0x00000051 +- 0x00010009 0x0000005a +- 0x0001000a 0x00000063 +- +- 0x00020000 0x00000013 +- 0x00020001 0x00000019 +- 0x00020002 0x00000024 +- 0x00020003 0x0000002c +- 0x00020004 0x00000035 +- 0x00020005 0x0000003d +- 0x00020006 0x00000046 +- 0x00020007 0x00000050 +- 0x00020008 0x00000059 +- +- 0x00030000 0x00000002 +- 0x00030001 0x0000000d +- 0x00030002 0x00000019 +- 0x00030003 0x00000024>; +- #thermal-sensor-cells = <1>; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- +- thermal-sensors = <&tmu 0>; +- +- trips { +- cpu_alert: cpu-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu_crit: cpu-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert>; +- cooling-device = +- <&cpu0 THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu_alert>; +- cooling-device = +- <&cpu1 THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- scfg: global-utilities@fc000 { +- compatible = "fsl,t1023-scfg"; +- reg = <0xfc000 0x1000>; +- }; +- +-/include/ "elo3-dma-0.dtsi" +-/include/ "elo3-dma-1.dtsi" +- +-/include/ "qoriq-espi-0.dtsi" +- spi@110000 { +- fsl,espi-num-chipselects = <4>; +- }; +- +-/include/ "qoriq-esdhc-0.dtsi" +- sdhc@114000 { +- compatible = "fsl,t1023-esdhc", "fsl,esdhc"; +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ +- sdhci,auto-cmd12; +- no-1-8-v; +- }; +-/include/ "qoriq-i2c-0.dtsi" +-/include/ "qoriq-i2c-1.dtsi" +-/include/ "qoriq-duart-0.dtsi" +-/include/ "qoriq-duart-1.dtsi" +-/include/ "qoriq-gpio-0.dtsi" +-/include/ "qoriq-gpio-1.dtsi" +-/include/ "qoriq-gpio-2.dtsi" +-/include/ "qoriq-gpio-3.dtsi" +-/include/ "qoriq-usb2-mph-0.dtsi" +- usb0: usb@210000 { +- compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph"; +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ +- phy_type = "utmi"; +- port0; +- }; +-/include/ "qoriq-usb2-dr-0.dtsi" +- usb1: usb@211000 { +- compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */ +- dr_mode = "host"; +- phy_type = "utmi"; +- }; +-/include/ "qoriq-sata2-0.dtsi" +- sata@220000 { +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */ +- }; +- +-/include/ "qoriq-sec5.0-0.dtsi" +-/include/ "qoriq-qman3.dtsi" +-/include/ "qoriq-bman1.dtsi" +- +-/include/ "qoriq-fman3l-0.dtsi" +-/include/ "qoriq-fman3-0-10g-0-best-effort.dtsi" +-/include/ "qoriq-fman3-0-1g-1.dtsi" +-/include/ "qoriq-fman3-0-1g-2.dtsi" +-/include/ "qoriq-fman3-0-1g-3.dtsi" +- fman@400000 { +- enet0: ethernet@e0000 { +- }; +- +- enet1: ethernet@e2000 { +- }; +- +- enet2: ethernet@e4000 { +- }; +- +- enet3: ethernet@e6000 { +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t1024qds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/t1024qds.dts +deleted file mode 100644 +index d6858b7cd93f..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t1024qds.dts ++++ /dev/null +@@ -1,280 +0,0 @@ +-/* +- * T1024 QDS Device Tree Source +- * +- * Copyright 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "t102xsi-pre.dtsi" +- +-/ { +- model = "fsl,T1024QDS"; +- compatible = "fsl,T1024QDS"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- ifc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x2000>; +- ranges = <0 0 0xf 0xe8000000 0x08000000 +- 2 0 0xf 0xff800000 0x00010000 +- 3 0 0xf 0xffdf0000 0x00008000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,ifc-nand"; +- reg = <0x2 0x0 0x10000>; +- }; +- +- board-control@3,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,tetra-fpga", "fsl,fpga-qixis"; +- reg = <3 0 0x300>; +- ranges = <0 3 0 0x300>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01072000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x2000000>; +- }; +- +- qportals: qman-portals@ff6000000 { +- ranges = <0x0 0xf 0xf6000000 0x2000000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- spi@110000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */ +- reg = <0>; +- spi-max-frequency = <10000000>; +- }; +- +- flash@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "sst,sst25wf040", "jedec,spi-nor"; /* 512KB */ +- reg = <1>; +- spi-max-frequency = <10000000>; +- }; +- +- flash@2 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "eon,en25s64", "jedec,spi-nor"; /* 8MB */ +- reg = <2>; +- spi-max-frequency = <10000000>; +- }; +- +- slic@2 { +- compatible = "maxim,ds26522"; +- reg = <2>; +- spi-max-frequency = <2000000>; +- }; +- +- slic@3 { +- compatible = "maxim,ds26522"; +- reg = <3>; +- spi-max-frequency = <2000000>; +- }; +- }; +- +- i2c@118000 { +- pca9547@77 { +- compatible = "nxp,pca9547"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0>; +- +- eeprom@50 { +- compatible = "atmel,24c512"; +- reg = <0x50>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- }; +- +- eeprom@57 { +- compatible = "atmel,24c02"; +- reg = <0x57>; +- }; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; +- +- ina220@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <1000>; +- }; +- +- ina220@41 { +- compatible = "ti,ina220"; +- reg = <0x41>; +- shunt-resistor = <1000>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3>; +- +- adt7461@4c { +- /* Thermal Monitor */ +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- +- eeprom@55 { +- compatible = "atmel,24c02"; +- reg = <0x55>; +- }; +- +- eeprom@56 { +- compatible = "atmel,24c512"; +- reg = <0x56>; +- }; +- +- eeprom@57 { +- compatible = "atmel,24c512"; +- reg = <0x57>; +- }; +- }; +- }; +- rtc@68 { +- compatible = "dallas,ds3232"; +- reg = <0x68>; +- interrupts = <0x5 0x1 0 0>; +- }; +- }; +- }; +- +- pci0: pcie@ffe240000 { +- reg = <0xf 0xfe240000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8000000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci1: pcie@ffe250000 { +- reg = <0xf 0xfe250000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci2: pcie@ffe260000 { +- reg = <0xf 0xfe260000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +-}; +- +-#include "t1024si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t1024rdb.dts b/scripts/dtc/include-prefixes/powerpc/fsl/t1024rdb.dts +deleted file mode 100644 +index dbcd31cc35dc..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t1024rdb.dts ++++ /dev/null +@@ -1,268 +0,0 @@ +-/* +- * T1024 RDB Device Tree Source +- * +- * Copyright 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "t102xsi-pre.dtsi" +- +-/ { +- model = "fsl,T1024RDB"; +- compatible = "fsl,T1024RDB"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- sg_2500_aqr105_phy4 = &sg_2500_aqr105_phy4; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- ifc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x2000>; +- ranges = <0 0 0xf 0xe8000000 0x08000000 +- 2 0 0xf 0xff800000 0x00010000 +- 3 0 0xf 0xffdf0000 0x00008000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,ifc-nand"; +- reg = <0x2 0x0 0x10000>; +- }; +- +- board-control@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,t1024-cpld"; +- reg = <3 0 0x300>; +- ranges = <0 3 0 0x300>; +- bank-width = <1>; +- device-width = <1>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01072000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x2000000>; +- }; +- +- qportals: qman-portals@ff6000000 { +- ranges = <0x0 0xf 0xf6000000 0x2000000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- spi@110000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q512ax3", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <10000000>; /* input clk */ +- }; +- +- slic@1 { +- compatible = "maxim,ds26522"; +- reg = <1>; +- spi-max-frequency = <2000000>; +- }; +- +- slic@2 { +- compatible = "maxim,ds26522"; +- reg = <2>; +- spi-max-frequency = <2000000>; +- }; +- }; +- +- i2c@118000 { +- adt7461@4c { +- /* Thermal Monitor */ +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- +- current-sensor@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <1000>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +- }; +- +- i2c@118100 { +- pca9546@77 { +- compatible = "nxp,pca9546"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- fman@400000 { +- fm1mac1: ethernet@e0000 { +- phy-handle = <&xg_aqr105_phy3>; +- phy-connection-type = "xgmii"; +- sleep = <&rcpm 0x80000000>; +- }; +- +- fm1mac2: ethernet@e2000 { +- sleep = <&rcpm 0x40000000>; +- }; +- +- fm1mac3: ethernet@e4000 { +- phy-handle = <&rgmii_phy2>; +- phy-connection-type = "rgmii"; +- sleep = <&rcpm 0x20000000>; +- }; +- +- fm1mac4: ethernet@e6000 { +- phy-handle = <&rgmii_phy1>; +- phy-connection-type = "rgmii"; +- sleep = <&rcpm 0x10000000>; +- }; +- +- +- mdio0: mdio@fc000 { +- rgmii_phy1: ethernet-phy@2 { +- reg = <0x2>; +- }; +- rgmii_phy2: ethernet-phy@6 { +- reg = <0x6>; +- }; +- }; +- +- xmdio0: mdio@fd000 { +- xg_aqr105_phy3: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x1>; +- }; +- sg_2500_aqr105_phy4: ethernet-phy@2 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x2>; +- }; +- }; +- }; +- }; +- +- pci0: pcie@ffe240000 { +- reg = <0xf 0xfe240000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8000000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci1: pcie@ffe250000 { +- reg = <0xf 0xfe250000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci2: pcie@ffe260000 { +- reg = <0xf 0xfe260000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +-}; +- +-#include "t1024si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t1024si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/t1024si-post.dtsi +deleted file mode 100644 +index bb480346a58d..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t1024si-post.dtsi ++++ /dev/null +@@ -1,100 +0,0 @@ +-/* +- * T1024 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#include "t1023si-post.dtsi" +- +-/ { +- aliases { +- vga = &display; +- display = &display; +- }; +- +- qe:qe@ffe140000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "qe"; +- compatible = "fsl,qe"; +- ranges = <0x0 0xf 0xfe140000 0x40000>; +- reg = <0xf 0xfe140000 0 0x480>; +- fsl,qe-num-riscs = <1>; +- fsl,qe-num-snums = <28>; +- brg-frequency = <0>; +- bus-frequency = <0>; +- }; +-}; +- +-&soc { +- display:display@180000 { +- compatible = "fsl,t1024-diu", "fsl,diu"; +- reg = <0x180000 1000>; +- interrupts = <74 2 0 0>; +- }; +-}; +- +-&qe { +- qeic: interrupt-controller@80 { +- interrupt-controller; +- compatible = "fsl,qe-ic"; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x80 0x80>; +- interrupts = <95 2 0 0 94 2 0 0>; //high:79 low:78 +- }; +- +- ucc@2000 { +- cell-index = <1>; +- reg = <0x2000 0x200>; +- interrupts = <32>; +- interrupt-parent = <&qeic>; +- }; +- +- ucc@2200 { +- cell-index = <3>; +- reg = <0x2200 0x200>; +- interrupts = <34>; +- interrupt-parent = <&qeic>; +- }; +- +- muram@10000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,qe-muram", "fsl,cpm-muram"; +- ranges = <0x0 0x10000 0x6000>; +- +- data-only@0 { +- compatible = "fsl,qe-muram-data", "fsl,cpm-muram-data"; +- reg = <0x0 0x6000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t102xsi-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/t102xsi-pre.dtsi +deleted file mode 100644 +index d87ea13164f2..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t102xsi-pre.dtsi ++++ /dev/null +@@ -1,95 +0,0 @@ +-/* +- * T1024/T1023 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e5500_power_isa.dtsi" +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- ccsr = &soc; +- dcsr = &dcsr; +- +- dma0 = &dma0; +- dma1 = &dma1; +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- usb0 = &usb0; +- usb1 = &usb1; +- sdhc = &sdhc; +- +- crypto = &crypto; +- +- fman0 = &fman0; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: PowerPC,e5500@0 { +- device_type = "cpu"; +- reg = <0>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_1>; +- #cooling-cells = <2>; +- L2_1: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu1: PowerPC,e5500@1 { +- device_type = "cpu"; +- reg = <1>; +- clocks = <&clockgen 1 1>; +- next-level-cache = <&L2_2>; +- #cooling-cells = <2>; +- L2_2: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t1040d4rdb.dts b/scripts/dtc/include-prefixes/powerpc/fsl/t1040d4rdb.dts +deleted file mode 100644 +index fb6bc02ebb60..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t1040d4rdb.dts ++++ /dev/null +@@ -1,46 +0,0 @@ +-/* +- * T1040D4RDB Device Tree Source +- * +- * Copyright 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "t104xsi-pre.dtsi" +-/include/ "t104xd4rdb.dtsi" +- +-/ { +- model = "fsl,T1040D4RDB"; +- compatible = "fsl,T1040D4RDB"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +-}; +- +-#include "t1040si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t1040qds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/t1040qds.dts +deleted file mode 100644 +index 5f76edc7838c..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t1040qds.dts ++++ /dev/null +@@ -1,46 +0,0 @@ +-/* +- * T1040QDS Device Tree Source +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "t104xsi-pre.dtsi" +-/include/ "t104xqds.dtsi" +- +-/ { +- model = "fsl,T1040QDS"; +- compatible = "fsl,T1040QDS"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +-}; +- +-#include "t1040si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t1040rdb.dts b/scripts/dtc/include-prefixes/powerpc/fsl/t1040rdb.dts +deleted file mode 100644 +index af0c8a6f5613..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t1040rdb.dts ++++ /dev/null +@@ -1,185 +0,0 @@ +-/* +- * T1040RDB Device Tree Source +- * +- * Copyright 2014 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "t104xsi-pre.dtsi" +-/include/ "t104xrdb.dtsi" +- +-/ { +- model = "fsl,T1040RDB"; +- compatible = "fsl,T1040RDB"; +- +- aliases { +- phy_sgmii_2 = &phy_sgmii_2; +- }; +- +- soc@ffe000000 { +- fman@400000 { +- ethernet@e0000 { +- fixed-link = <0 1 1000 0 0>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e2000 { +- fixed-link = <1 1 1000 0 0>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e4000 { +- phy-handle = <&phy_sgmii_2>; +- phy-connection-type = "sgmii"; +- }; +- +- mdio@fc000 { +- phy_sgmii_2: ethernet-phy@3 { +- reg = <0x03>; +- }; +- +- /* VSC8514 QSGMII PHY */ +- phy_qsgmii_0: ethernet-phy@4 { +- reg = <0x4>; +- }; +- +- phy_qsgmii_1: ethernet-phy@5 { +- reg = <0x5>; +- }; +- +- phy_qsgmii_2: ethernet-phy@6 { +- reg = <0x6>; +- }; +- +- phy_qsgmii_3: ethernet-phy@7 { +- reg = <0x7>; +- }; +- +- /* VSC8514 QSGMII PHY */ +- phy_qsgmii_4: ethernet-phy@8 { +- reg = <0x8>; +- }; +- +- phy_qsgmii_5: ethernet-phy@9 { +- reg = <0x9>; +- }; +- +- phy_qsgmii_6: ethernet-phy@a { +- reg = <0xa>; +- }; +- +- phy_qsgmii_7: ethernet-phy@b { +- reg = <0xb>; +- }; +- }; +- }; +- }; +- +- ifc: localbus@ffe124000 { +- cpld@3,0 { +- compatible = "fsl,t1040rdb-cpld"; +- }; +- }; +-}; +- +-#include "t1040si-post.dtsi" +- +-&seville_switch { +- status = "okay"; +-}; +- +-&seville_port0 { +- managed = "in-band-status"; +- phy-handle = <&phy_qsgmii_0>; +- phy-mode = "qsgmii"; +- label = "ETH5"; +- status = "okay"; +-}; +- +-&seville_port1 { +- managed = "in-band-status"; +- phy-handle = <&phy_qsgmii_1>; +- phy-mode = "qsgmii"; +- label = "ETH4"; +- status = "okay"; +-}; +- +-&seville_port2 { +- managed = "in-band-status"; +- phy-handle = <&phy_qsgmii_2>; +- phy-mode = "qsgmii"; +- label = "ETH7"; +- status = "okay"; +-}; +- +-&seville_port3 { +- managed = "in-band-status"; +- phy-handle = <&phy_qsgmii_3>; +- phy-mode = "qsgmii"; +- label = "ETH6"; +- status = "okay"; +-}; +- +-&seville_port4 { +- managed = "in-band-status"; +- phy-handle = <&phy_qsgmii_4>; +- phy-mode = "qsgmii"; +- label = "ETH9"; +- status = "okay"; +-}; +- +-&seville_port5 { +- managed = "in-band-status"; +- phy-handle = <&phy_qsgmii_5>; +- phy-mode = "qsgmii"; +- label = "ETH8"; +- status = "okay"; +-}; +- +-&seville_port6 { +- managed = "in-band-status"; +- phy-handle = <&phy_qsgmii_6>; +- phy-mode = "qsgmii"; +- label = "ETH11"; +- status = "okay"; +-}; +- +-&seville_port7 { +- managed = "in-band-status"; +- phy-handle = <&phy_qsgmii_7>; +- phy-mode = "qsgmii"; +- label = "ETH10"; +- status = "okay"; +-}; +- +-&seville_port8 { +- ethernet = <&enet0>; +- status = "okay"; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t1040si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/t1040si-post.dtsi +deleted file mode 100644 +index f58eb820eb5e..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t1040si-post.dtsi ++++ /dev/null +@@ -1,754 +0,0 @@ +-/* +- * T1040 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2013 - 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#include +- +-&bman_fbpr { +- compatible = "fsl,bman-fbpr"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&qman_fqd { +- compatible = "fsl,qman-fqd"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&qman_pfdr { +- compatible = "fsl,qman-pfdr"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&ifc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,ifc", "simple-bus"; +- interrupts = <25 2 0 0>; +-}; +- +-&pci0 { +- compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- interrupts = <20 2 0 0>; +- fsl,iommu-parent = <&pamu0>; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <20 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 40 1 0 0 +- 0000 0 0 2 &mpic 1 1 0 0 +- 0000 0 0 3 &mpic 2 1 0 0 +- 0000 0 0 4 &mpic 3 1 0 0 +- >; +- }; +-}; +- +-&pci1 { +- compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 0xff>; +- interrupts = <21 2 0 0>; +- fsl,iommu-parent = <&pamu0>; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <21 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 41 1 0 0 +- 0000 0 0 2 &mpic 5 1 0 0 +- 0000 0 0 3 &mpic 6 1 0 0 +- 0000 0 0 4 &mpic 7 1 0 0 +- >; +- }; +-}; +- +-&pci2 { +- compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- interrupts = <22 2 0 0>; +- fsl,iommu-parent = <&pamu0>; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <22 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 42 1 0 0 +- 0000 0 0 2 &mpic 9 1 0 0 +- 0000 0 0 3 &mpic 10 1 0 0 +- 0000 0 0 4 &mpic 11 1 0 0 +- >; +- }; +-}; +- +-&pci3 { +- compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- interrupts = <23 2 0 0>; +- fsl,iommu-parent = <&pamu0>; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <23 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 43 1 0 0 +- 0000 0 0 2 &mpic 0 1 0 0 +- 0000 0 0 3 &mpic 4 1 0 0 +- 0000 0 0 4 &mpic 8 1 0 0 +- >; +- }; +-}; +- +-&dcsr { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,dcsr", "simple-bus"; +- +- dcsr-epu@0 { +- compatible = "fsl,t1040-dcsr-epu", "fsl,dcsr-epu"; +- interrupts = <52 2 0 0 +- 84 2 0 0 +- 85 2 0 0>; +- reg = <0x0 0x1000>; +- }; +- dcsr-npc { +- compatible = "fsl,t1040-dcsr-cnpc", "fsl,dcsr-cnpc"; +- reg = <0x1000 0x1000 0x1002000 0x10000>; +- }; +- dcsr-nxc@2000 { +- compatible = "fsl,dcsr-nxc"; +- reg = <0x2000 0x1000>; +- }; +- dcsr-corenet { +- compatible = "fsl,dcsr-corenet"; +- reg = <0x8000 0x1000 0x1A000 0x1000>; +- }; +- dcsr-dpaa@9000 { +- compatible = "fsl,t1040-dcsr-dpaa", "fsl,dcsr-dpaa"; +- reg = <0x9000 0x1000>; +- }; +- dcsr-ocn@11000 { +- compatible = "fsl,t1040-dcsr-ocn", "fsl,dcsr-ocn"; +- reg = <0x11000 0x1000>; +- }; +- dcsr-ddr@12000 { +- compatible = "fsl,dcsr-ddr"; +- dev-handle = <&ddr1>; +- reg = <0x12000 0x1000>; +- }; +- dcsr-nal@18000 { +- compatible = "fsl,t1040-dcsr-nal", "fsl,dcsr-nal"; +- reg = <0x18000 0x1000>; +- }; +- dcsr-rcpm@22000 { +- compatible = "fsl,t1040-dcsr-rcpm", "fsl,dcsr-rcpm"; +- reg = <0x22000 0x1000>; +- }; +- dcsr-snpc@30000 { +- compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc"; +- reg = <0x30000 0x1000 0x1022000 0x10000>; +- }; +- dcsr-snpc@31000 { +- compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc"; +- reg = <0x31000 0x1000 0x1042000 0x10000>; +- }; +- dcsr-cpu-sb-proxy@100000 { +- compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu0>; +- reg = <0x100000 0x1000 0x101000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@108000 { +- compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu1>; +- reg = <0x108000 0x1000 0x109000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@110000 { +- compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu2>; +- reg = <0x110000 0x1000 0x111000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@118000 { +- compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu3>; +- reg = <0x118000 0x1000 0x119000 0x1000>; +- }; +-}; +- +-&bportals { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- compatible = "simple-bus"; +- +- bman-portal@0 { +- compatible = "fsl,bman-portal"; +- reg = <0x0 0x4000>, <0x1000000 0x1000>; +- interrupts = <105 2 0 0>; +- }; +- bman-portal@4000 { +- compatible = "fsl,bman-portal"; +- reg = <0x4000 0x4000>, <0x1001000 0x1000>; +- interrupts = <107 2 0 0>; +- }; +- bman-portal@8000 { +- compatible = "fsl,bman-portal"; +- reg = <0x8000 0x4000>, <0x1002000 0x1000>; +- interrupts = <109 2 0 0>; +- }; +- bman-portal@c000 { +- compatible = "fsl,bman-portal"; +- reg = <0xc000 0x4000>, <0x1003000 0x1000>; +- interrupts = <111 2 0 0>; +- }; +- bman-portal@10000 { +- compatible = "fsl,bman-portal"; +- reg = <0x10000 0x4000>, <0x1004000 0x1000>; +- interrupts = <113 2 0 0>; +- }; +- bman-portal@14000 { +- compatible = "fsl,bman-portal"; +- reg = <0x14000 0x4000>, <0x1005000 0x1000>; +- interrupts = <115 2 0 0>; +- }; +- bman-portal@18000 { +- compatible = "fsl,bman-portal"; +- reg = <0x18000 0x4000>, <0x1006000 0x1000>; +- interrupts = <117 2 0 0>; +- }; +- bman-portal@1c000 { +- compatible = "fsl,bman-portal"; +- reg = <0x1c000 0x4000>, <0x1007000 0x1000>; +- interrupts = <119 2 0 0>; +- }; +- bman-portal@20000 { +- compatible = "fsl,bman-portal"; +- reg = <0x20000 0x4000>, <0x1008000 0x1000>; +- interrupts = <121 2 0 0>; +- }; +- bman-portal@24000 { +- compatible = "fsl,bman-portal"; +- reg = <0x24000 0x4000>, <0x1009000 0x1000>; +- interrupts = <123 2 0 0>; +- }; +-}; +- +-&qportals { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- compatible = "simple-bus"; +- +- qportal0: qman-portal@0 { +- compatible = "fsl,qman-portal"; +- reg = <0x0 0x4000>, <0x1000000 0x1000>; +- interrupts = <104 0x2 0 0>; +- cell-index = <0x0>; +- }; +- qportal1: qman-portal@4000 { +- compatible = "fsl,qman-portal"; +- reg = <0x4000 0x4000>, <0x1001000 0x1000>; +- interrupts = <106 0x2 0 0>; +- cell-index = <0x1>; +- }; +- qportal2: qman-portal@8000 { +- compatible = "fsl,qman-portal"; +- reg = <0x8000 0x4000>, <0x1002000 0x1000>; +- interrupts = <108 0x2 0 0>; +- cell-index = <0x2>; +- }; +- qportal3: qman-portal@c000 { +- compatible = "fsl,qman-portal"; +- reg = <0xc000 0x4000>, <0x1003000 0x1000>; +- interrupts = <110 0x2 0 0>; +- cell-index = <0x3>; +- }; +- qportal4: qman-portal@10000 { +- compatible = "fsl,qman-portal"; +- reg = <0x10000 0x4000>, <0x1004000 0x1000>; +- interrupts = <112 0x2 0 0>; +- cell-index = <0x4>; +- }; +- qportal5: qman-portal@14000 { +- compatible = "fsl,qman-portal"; +- reg = <0x14000 0x4000>, <0x1005000 0x1000>; +- interrupts = <114 0x2 0 0>; +- cell-index = <0x5>; +- }; +- qportal6: qman-portal@18000 { +- compatible = "fsl,qman-portal"; +- reg = <0x18000 0x4000>, <0x1006000 0x1000>; +- interrupts = <116 0x2 0 0>; +- cell-index = <0x6>; +- }; +- qportal7: qman-portal@1c000 { +- compatible = "fsl,qman-portal"; +- reg = <0x1c000 0x4000>, <0x1007000 0x1000>; +- interrupts = <118 0x2 0 0>; +- cell-index = <0x7>; +- }; +- qportal8: qman-portal@20000 { +- compatible = "fsl,qman-portal"; +- reg = <0x20000 0x4000>, <0x1008000 0x1000>; +- interrupts = <120 0x2 0 0>; +- cell-index = <0x8>; +- }; +- qportal9: qman-portal@24000 { +- compatible = "fsl,qman-portal"; +- reg = <0x24000 0x4000>, <0x1009000 0x1000>; +- interrupts = <122 0x2 0 0>; +- cell-index = <0x9>; +- }; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- +- soc-sram-error { +- compatible = "fsl,soc-sram-error"; +- interrupts = <16 2 1 29>; +- }; +- +- corenet-law@0 { +- compatible = "fsl,corenet-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <16>; +- }; +- +- ddr1: memory-controller@8000 { +- compatible = "fsl,qoriq-memory-controller-v5.0", +- "fsl,qoriq-memory-controller"; +- reg = <0x8000 0x1000>; +- interrupts = <16 2 1 23>; +- }; +- +- cpc: l3-cache-controller@10000 { +- compatible = "fsl,t1040-l3-cache-controller", "cache"; +- reg = <0x10000 0x1000>; +- interrupts = <16 2 1 27>; +- }; +- +- corenet-cf@18000 { +- compatible = "fsl,corenet2-cf", "fsl,corenet-cf"; +- reg = <0x18000 0x1000>; +- interrupts = <16 2 1 31>; +- fsl,ccf-num-csdids = <32>; +- fsl,ccf-num-snoopids = <32>; +- }; +- +- iommu@20000 { +- compatible = "fsl,pamu-v1.0", "fsl,pamu"; +- reg = <0x20000 0x1000>; +- ranges = <0 0x20000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupts = < +- 24 2 0 0 +- 16 2 1 30>; +- pamu0: pamu@0 { +- reg = <0 0x1000>; +- fsl,primary-cache-geometry = <128 1>; +- fsl,secondary-cache-geometry = <16 2>; +- }; +- }; +- +-/include/ "qoriq-mpic.dtsi" +- +- guts: global-utilities@e0000 { +- compatible = "fsl,t1040-device-config", "fsl,qoriq-device-config-2.0"; +- reg = <0xe0000 0xe00>; +- fsl,has-rstcr; +- fsl,liodn-bits = <12>; +- }; +- +-/include/ "qoriq-clockgen2.dtsi" +- global-utilities@e1000 { +- compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0"; +- }; +- +- rcpm: global-utilities@e2000 { +- compatible = "fsl,t1040-rcpm", "fsl,qoriq-rcpm-2.1"; +- reg = <0xe2000 0x1000>; +- }; +- +- sfp: sfp@e8000 { +- compatible = "fsl,t1040-sfp"; +- reg = <0xe8000 0x1000>; +- }; +- +- serdes: serdes@ea000 { +- compatible = "fsl,t1040-serdes"; +- reg = <0xea000 0x4000>; +- }; +- +- tmu: tmu@f0000 { +- compatible = "fsl,qoriq-tmu"; +- reg = <0xf0000 0x1000>; +- interrupts = <18 2 0 0>; +- fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>; +- fsl,tmu-calibration = <0x00000000 0x00000025 +- 0x00000001 0x00000028 +- 0x00000002 0x0000002d +- 0x00000003 0x00000031 +- 0x00000004 0x00000036 +- 0x00000005 0x0000003a +- 0x00000006 0x00000040 +- 0x00000007 0x00000044 +- 0x00000008 0x0000004a +- 0x00000009 0x0000004f +- 0x0000000a 0x00000054 +- +- 0x00010000 0x0000000d +- 0x00010001 0x00000013 +- 0x00010002 0x00000019 +- 0x00010003 0x0000001f +- 0x00010004 0x00000025 +- 0x00010005 0x0000002d +- 0x00010006 0x00000033 +- 0x00010007 0x00000043 +- 0x00010008 0x0000004b +- 0x00010009 0x00000053 +- +- 0x00020000 0x00000010 +- 0x00020001 0x00000017 +- 0x00020002 0x0000001f +- 0x00020003 0x00000029 +- 0x00020004 0x00000031 +- 0x00020005 0x0000003c +- 0x00020006 0x00000042 +- 0x00020007 0x0000004d +- 0x00020008 0x00000056 +- +- 0x00030000 0x00000012 +- 0x00030001 0x0000001d>; +- #thermal-sensor-cells = <1>; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <1000>; +- polling-delay = <5000>; +- +- thermal-sensors = <&tmu 2>; +- +- trips { +- cpu_alert: cpu-alert { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- cpu_crit: cpu-crit { +- temperature = <95000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&cpu_alert>; +- cooling-device = +- <&cpu0 THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>; +- }; +- map1 { +- trip = <&cpu_alert>; +- cooling-device = +- <&cpu1 THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>; +- }; +- map2 { +- trip = <&cpu_alert>; +- cooling-device = +- <&cpu2 THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>; +- }; +- map3 { +- trip = <&cpu_alert>; +- cooling-device = +- <&cpu3 THERMAL_NO_LIMIT +- THERMAL_NO_LIMIT>; +- }; +- }; +- }; +- }; +- +- scfg: global-utilities@fc000 { +- compatible = "fsl,t1040-scfg"; +- reg = <0xfc000 0x1000>; +- }; +- +-/include/ "elo3-dma-0.dtsi" +-/include/ "elo3-dma-1.dtsi" +-/include/ "qoriq-espi-0.dtsi" +- spi@110000 { +- fsl,espi-num-chipselects = <4>; +- }; +- +-/include/ "qoriq-esdhc-0.dtsi" +- sdhc@114000 { +- compatible = "fsl,t1040-esdhc", "fsl,esdhc"; +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ +- sdhci,auto-cmd12; +- }; +-/include/ "qoriq-i2c-0.dtsi" +-/include/ "qoriq-i2c-1.dtsi" +-/include/ "qoriq-duart-0.dtsi" +-/include/ "qoriq-duart-1.dtsi" +-/include/ "qoriq-gpio-0.dtsi" +-/include/ "qoriq-gpio-1.dtsi" +-/include/ "qoriq-gpio-2.dtsi" +-/include/ "qoriq-gpio-3.dtsi" +-/include/ "qoriq-usb2-mph-0.dtsi" +- usb0: usb@210000 { +- compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph"; +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ +- phy_type = "utmi"; +- port0; +- }; +-/include/ "qoriq-usb2-dr-0.dtsi" +- usb1: usb@211000 { +- compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */ +- dr_mode = "host"; +- phy_type = "utmi"; +- }; +- +- display@180000 { +- compatible = "fsl,t1040-diu", "fsl,diu"; +- reg = <0x180000 1000>; +- interrupts = <74 2 0 0>; +- }; +- +-/include/ "qoriq-sata2-0.dtsi" +- sata@220000 { +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */ +- }; +-/include/ "qoriq-sata2-1.dtsi" +- sata@221000 { +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */ +- }; +-/include/ "qoriq-sec5.0-0.dtsi" +-/include/ "qoriq-qman3.dtsi" +-/include/ "qoriq-bman1.dtsi" +- +-/include/ "qoriq-fman3l-0.dtsi" +-/include/ "qoriq-fman3-0-1g-0.dtsi" +-/include/ "qoriq-fman3-0-1g-1.dtsi" +-/include/ "qoriq-fman3-0-1g-2.dtsi" +-/include/ "qoriq-fman3-0-1g-3.dtsi" +-/include/ "qoriq-fman3-0-1g-4.dtsi" +- fman@400000 { +- enet0: ethernet@e0000 { +- }; +- +- enet1: ethernet@e2000 { +- }; +- +- enet2: ethernet@e4000 { +- }; +- +- enet3: ethernet@e6000 { +- }; +- +- enet4: ethernet@e8000 { +- }; +- +- mdio@fc000 { +- interrupts = <100 1 0 0>; +- }; +- +- mdio@fd000 { +- status = "disabled"; +- }; +- }; +- +- seville_switch: ethernet-switch@800000 { +- compatible = "mscc,vsc9953-switch"; +- reg = <0x800000 0x290000>; +- interrupts = <26 2 0 0>; +- interrupt-names = "xtr"; +- little-endian; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- seville_port0: port@0 { +- reg = <0>; +- status = "disabled"; +- }; +- +- seville_port1: port@1 { +- reg = <1>; +- status = "disabled"; +- }; +- +- seville_port2: port@2 { +- reg = <2>; +- status = "disabled"; +- }; +- +- seville_port3: port@3 { +- reg = <3>; +- status = "disabled"; +- }; +- +- seville_port4: port@4 { +- reg = <4>; +- status = "disabled"; +- }; +- +- seville_port5: port@5 { +- reg = <5>; +- status = "disabled"; +- }; +- +- seville_port6: port@6 { +- reg = <6>; +- status = "disabled"; +- }; +- +- seville_port7: port@7 { +- reg = <7>; +- status = "disabled"; +- }; +- +- seville_port8: port@8 { +- reg = <8>; +- phy-mode = "internal"; +- status = "disabled"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- }; +- }; +- +- seville_port9: port@9 { +- reg = <9>; +- phy-mode = "internal"; +- status = "disabled"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- }; +- }; +- }; +- }; +-}; +- +-&qe { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "qe"; +- compatible = "fsl,qe"; +- fsl,qe-num-riscs = <1>; +- fsl,qe-num-snums = <28>; +- +- qeic: interrupt-controller@80 { +- interrupt-controller; +- compatible = "fsl,qe-ic"; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x80 0x80>; +- interrupts = <95 2 0 0 94 2 0 0>; //high:79 low:78 +- }; +- +- ucc@2000 { +- cell-index = <1>; +- reg = <0x2000 0x200>; +- interrupts = <32>; +- interrupt-parent = <&qeic>; +- }; +- +- ucc@2200 { +- cell-index = <3>; +- reg = <0x2200 0x200>; +- interrupts = <34>; +- interrupt-parent = <&qeic>; +- }; +- +- muram@10000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,qe-muram", "fsl,cpm-muram"; +- ranges = <0x0 0x10000 0x6000>; +- +- data-only@0 { +- compatible = "fsl,qe-muram-data", +- "fsl,cpm-muram-data"; +- reg = <0x0 0x6000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t1042d4rdb.dts b/scripts/dtc/include-prefixes/powerpc/fsl/t1042d4rdb.dts +deleted file mode 100644 +index 4fa15f48a4c3..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t1042d4rdb.dts ++++ /dev/null +@@ -1,105 +0,0 @@ +-/* +- * T1042D4RDB Device Tree Source +- * +- * Copyright 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "t104xsi-pre.dtsi" +-/include/ "t104xd4rdb.dtsi" +- +-/ { +- model = "fsl,T1042D4RDB"; +- compatible = "fsl,T1042D4RDB"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- ifc: localbus@ffe124000 { +- cpld@3,0 { +- compatible = "fsl,t1040d4rdb-cpld", +- "fsl,deepsleep-cpld"; +- }; +- }; +- +- soc: soc@ffe000000 { +- fman0: fman@400000 { +- ethernet@e0000 { +- phy-handle = <&phy_sgmii_0>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e2000 { +- phy-handle = <&phy_sgmii_1>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e4000 { +- phy-handle = <&phy_sgmii_2>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e6000 { +- phy-handle = <&phy_rgmii_0>; +- phy-connection-type = "rgmii"; +- }; +- +- ethernet@e8000 { +- phy-handle = <&phy_rgmii_1>; +- phy-connection-type = "rgmii"; +- }; +- +- mdio0: mdio@fc000 { +- phy_sgmii_0: ethernet-phy@2 { +- reg = <0x02>; +- }; +- +- phy_sgmii_1: ethernet-phy@3 { +- reg = <0x03>; +- }; +- +- phy_sgmii_2: ethernet-phy@1 { +- reg = <0x01>; +- }; +- +- phy_rgmii_0: ethernet-phy@4 { +- reg = <0x04>; +- }; +- +- phy_rgmii_1: ethernet-phy@5 { +- reg = <0x05>; +- }; +- }; +- }; +- }; +- +-}; +- +-#include "t1042si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t1042qds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/t1042qds.dts +deleted file mode 100644 +index 90a4a73bb905..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t1042qds.dts ++++ /dev/null +@@ -1,46 +0,0 @@ +-/* +- * T1042QDS Device Tree Source +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "t104xsi-pre.dtsi" +-/include/ "t104xqds.dtsi" +- +-/ { +- model = "fsl,T1042QDS"; +- compatible = "fsl,T1042QDS"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +-}; +- +-#include "t1042si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t1042rdb.dts b/scripts/dtc/include-prefixes/powerpc/fsl/t1042rdb.dts +deleted file mode 100644 +index 3ebb712224cb..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t1042rdb.dts ++++ /dev/null +@@ -1,76 +0,0 @@ +-/* +- * T1042RDB Device Tree Source +- * +- * Copyright 2014 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "t104xsi-pre.dtsi" +-/include/ "t104xrdb.dtsi" +- +-/ { +- model = "fsl,T1042RDB"; +- compatible = "fsl,T1042RDB"; +- +- aliases { +- phy_sgmii_2 = &phy_sgmii_2; +- }; +- +- soc@ffe000000 { +- fman@400000 { +- ethernet@e0000 { +- status = "disabled"; +- }; +- +- ethernet@e2000 { +- status = "disabled"; +- }; +- +- ethernet@e4000 { +- phy-handle = <&phy_sgmii_2>; +- phy-connection-type = "sgmii"; +- }; +- +- mdio@fc000 { +- phy_sgmii_2: ethernet-phy@3 { +- reg = <0x03>; +- }; +- }; +- }; +- }; +- +- ifc: localbus@ffe124000 { +- cpld@3,0 { +- compatible = "fsl,t1042rdb-cpld"; +- }; +- }; +-}; +- +-#include "t1042si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t1042rdb_pi.dts b/scripts/dtc/include-prefixes/powerpc/fsl/t1042rdb_pi.dts +deleted file mode 100644 +index 8ec3ff45e6fc..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t1042rdb_pi.dts ++++ /dev/null +@@ -1,73 +0,0 @@ +-/* +- * T1042RDB_PI Device Tree Source +- * +- * Copyright 2014 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "t104xsi-pre.dtsi" +-/include/ "t104xrdb.dtsi" +- +-/ { +- model = "fsl,T1042RDB_PI"; +- compatible = "fsl,T1042RDB_PI"; +- +- ifc: localbus@ffe124000 { +- cpld@3,0 { +- compatible = "fsl,t1042rdb_pi-cpld"; +- }; +- }; +- +- soc: soc@ffe000000 { +- i2c@118000 { +- rtc@68 { +- compatible = "dallas,ds1337"; +- reg = <0x68>; +- interrupts = <0x2 0x1 0 0>; +- }; +- }; +- +- fman@400000 { +- ethernet@e0000 { +- status = "disabled"; +- }; +- +- ethernet@e2000 { +- status = "disabled"; +- }; +- +- ethernet@e4000 { +- status = "disabled"; +- }; +- }; +- }; +-}; +- +-#include "t1042si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t1042si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/t1042si-post.dtsi +deleted file mode 100644 +index a5544f93689c..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t1042si-post.dtsi ++++ /dev/null +@@ -1,37 +0,0 @@ +-/* +- * T1042 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#include "t1040si-post.dtsi" +- +-/* Place holder for ethernet related device tree nodes */ +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t104xd4rdb.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/t104xd4rdb.dtsi +deleted file mode 100644 +index 863f9431285f..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t104xd4rdb.dtsi ++++ /dev/null +@@ -1,253 +0,0 @@ +-/* +- * T1040D4RDB/T1042D4RDB Device Tree Source +- * +- * Copyright 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/ { +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- ifc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x2000>; +- ranges = <0 0 0xf 0xe8000000 0x08000000 +- 2 0 0xf 0xff800000 0x00010000 +- 3 0 0xf 0xffdf0000 0x00008000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,ifc-nand"; +- reg = <0x2 0x0 0x10000>; +- }; +- +- cpld@3,0 { +- compatible = "fsl,t1040d4rdb-cpld"; +- reg = <3 0 0x300>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01072000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x2000000>; +- }; +- +- qportals: qman-portals@ff6000000 { +- ranges = <0x0 0xf 0xf6000000 0x2000000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- +- spi@110000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q512ax3", "jedec,spi-nor"; +- reg = <0>; +- /* input clock */ +- spi-max-frequency = <10000000>; +- }; +- slic@1 { +- compatible = "maxim,ds26522"; +- reg = <1>; +- spi-max-frequency = <2000000>; /* input clock */ +- }; +- slic@2 { +- compatible = "maxim,ds26522"; +- reg = <2>; +- spi-max-frequency = <2000000>; /* input clock */ +- }; +- }; +- i2c@118000 { +- hwmon@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1337"; +- reg = <0x68>; +- interrupts = <0x2 0x1 0 0>; +- }; +- }; +- +- i2c@118100 { +- mux@77 { +- /* +- * Child nodes of mux depend on which i2c +- * devices are connected via the mini PCI +- * connector slot1, the mini PCI connector +- * slot2, the HDMI connector, and the PEX +- * slot. Systems with such devices attached +- * should provide a wrapper .dts file that +- * includes this one, and adds those nodes +- */ +- compatible = "nxp,pca9546"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- }; +- +- pci0: pcie@ffe240000 { +- reg = <0xf 0xfe240000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x0 0x0 0x10000000 +- 0x01000000 0 0x0 0xf 0xf8000000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci1: pcie@ffe250000 { +- reg = <0xf 0xfe250000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000 +- 0x01000000 0 0 0xf 0xf8010000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci2: pcie@ffe260000 { +- reg = <0xf 0xfe260000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci3: pcie@ffe270000 { +- reg = <0xf 0xfe270000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- qe: qe@ffe140000 { +- ranges = <0x0 0xf 0xfe140000 0x40000>; +- reg = <0xf 0xfe140000 0 0x480>; +- brg-frequency = <0>; +- bus-frequency = <0>; +- +- si1: si@700 { +- compatible = "fsl,t1040-qe-si"; +- reg = <0x700 0x80>; +- }; +- +- siram1: siram@1000 { +- compatible = "fsl,t1040-qe-siram"; +- reg = <0x1000 0x800>; +- }; +- +- ucc_hdlc: ucc@2000 { +- compatible = "fsl,ucc-hdlc"; +- rx-clock-name = "clk8"; +- tx-clock-name = "clk9"; +- fsl,rx-sync-clock = "rsync_pin"; +- fsl,tx-sync-clock = "tsync_pin"; +- fsl,tx-timeslot-mask = <0xfffffffe>; +- fsl,rx-timeslot-mask = <0xfffffffe>; +- fsl,tdm-framer-type = "e1"; +- fsl,tdm-id = <0>; +- fsl,siram-entry-id = <0>; +- fsl,tdm-interface; +- }; +- +- ucc_serial: ucc@2200 { +- compatible = "fsl,t1040-ucc-uart"; +- port-number = <0>; +- rx-clock-name = "brg2"; +- tx-clock-name = "brg2"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t104xqds.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/t104xqds.dtsi +deleted file mode 100644 +index 615479732252..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t104xqds.dtsi ++++ /dev/null +@@ -1,407 +0,0 @@ +-/* +- * T104xQDS Device Tree Source +- * +- * Copyright 2013 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/ { +- model = "fsl,T1040QDS"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- emi1_rgmii0 = &t1040mdio0; +- emi1_rgmii1 = &t1040mdio1; +- emi1_slot3 = &t1040mdio3; +- emi1_slot5 = &t1040mdio5; +- emi1_slot6 = &t1040mdio6; +- emi1_slot7 = &t1040mdio7; +- rgmii_phy1 = &rgmii_phy1; +- rgmii_phy2 = &rgmii_phy2; +- phy_s3_01 = &phy_s3_01; +- phy_s3_02 = &phy_s3_02; +- phy_s3_03 = &phy_s3_03; +- phy_s3_04 = &phy_s3_04; +- phy_s5_01 = &phy_s5_01; +- phy_s5_02 = &phy_s5_02; +- phy_s5_03 = &phy_s5_03; +- phy_s5_04 = &phy_s5_04; +- phy_s6_01 = &phy_s6_01; +- phy_s6_02 = &phy_s6_02; +- phy_s6_03 = &phy_s6_03; +- phy_s6_04 = &phy_s6_04; +- phy_s7_01 = &phy_s7_01; +- phy_s7_02 = &phy_s7_02; +- phy_s7_03 = &phy_s7_03; +- phy_s7_04 = &phy_s7_04; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- ifc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x2000>; +- ranges = <0 0 0xf 0xe8000000 0x08000000 +- 2 0 0xf 0xff800000 0x00010000 +- 3 0 0xf 0xffdf0000 0x00008000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,ifc-nand"; +- reg = <0x2 0x0 0x10000>; +- }; +- +- board-control@3,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,fpga-qixis"; +- reg = <3 0 0x300>; +- ranges = <0 3 0 0x300>; +- +- mdio-mux-emi1 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "mdio-mux-mmioreg", "mdio-mux"; +- mdio-parent-bus = <&mdio0>; +- reg = <0x54 1>; +- mux-mask = <0xe0>; +- +- t1040mdio0: mdio@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x00>; +- status = "disabled"; +- +- rgmii_phy1: ethernet-phy@1 { +- reg = <0x1>; +- }; +- }; +- +- t1040mdio1: mdio@20 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x20>; +- status = "disabled"; +- +- rgmii_phy2: ethernet-phy@2 { +- reg = <0x2>; +- }; +- }; +- +- t1040mdio3: mdio@60 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x60>; +- status = "disabled"; +- +- phy_s3_01: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy_s3_02: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy_s3_03: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy_s3_04: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- +- t1040mdio5: mdio@a0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xa0>; +- +- phy_s5_01: ethernet-phy@1c { +- reg = <0x14>; +- }; +- +- phy_s5_02: ethernet-phy@1d { +- reg = <0x15>; +- }; +- +- phy_s5_03: ethernet-phy@1e { +- reg = <0x16>; +- }; +- +- phy_s5_04: ethernet-phy@1f { +- reg = <0x17>; +- }; +- }; +- +- t1040mdio6: mdio@c0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xc0>; +- +- phy_s6_01: ethernet-phy@1c { +- reg = <0x18>; +- }; +- +- phy_s6_02: ethernet-phy@1d { +- reg = <0x19>; +- }; +- +- phy_s6_03: ethernet-phy@1e { +- reg = <0x1a>; +- }; +- +- phy_s6_04: ethernet-phy@1f { +- reg = <0x1b>; +- }; +- }; +- +- t1040mdio7: mdio@e0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xe0>; +- status = "disabled"; +- +- phy_s7_01: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy_s7_02: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy_s7_03: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy_s7_04: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- }; +- }; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01072000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x2000000>; +- }; +- +- qportals: qman-portals@ff6000000 { +- ranges = <0x0 0xf 0xf6000000 0x2000000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- +- spi@110000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q128a11", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <10000000>; /* input clock */ +- }; +- }; +- +- i2c@118000 { +- pca9547@77 { +- compatible = "nxp,pca9547"; +- reg = <0x77>; +- }; +- rtc@68 { +- compatible = "dallas,ds3232"; +- reg = <0x68>; +- interrupts = <0x1 0x1 0 0>; +- }; +- }; +- +- fman@400000 { +- ethernet@e0000 { +- fixed-link = <0 1 1000 0 0>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e2000 { +- fixed-link = <1 1 1000 0 0>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e4000 { +- phy-handle = <&phy_s7_03>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e6000 { +- phy-handle = <&rgmii_phy1>; +- phy-connection-type = "rgmii"; +- }; +- +- ethernet@e8000 { +- phy-handle = <&rgmii_phy2>; +- phy-connection-type = "rgmii"; +- }; +- }; +- }; +- +- pci0: pcie@ffe240000 { +- reg = <0xf 0xfe240000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci1: pcie@ffe250000 { +- reg = <0xf 0xfe250000 0 0x10000>; +- ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci2: pcie@ffe260000 { +- reg = <0xf 0xfe260000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci3: pcie@ffe270000 { +- reg = <0xf 0xfe270000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- qe: qe@ffe140000 { +- ranges = <0x0 0xf 0xfe140000 0x40000>; +- reg = <0xf 0xfe140000 0 0x480>; +- brg-frequency = <0>; +- bus-frequency = <0>; +- +- si1: si@700 { +- compatible = "fsl,t1040-qe-si"; +- reg = <0x700 0x80>; +- }; +- +- siram1: siram@1000 { +- compatible = "fsl,t1040-qe-siram"; +- reg = <0x1000 0x800>; +- }; +- +- ucc_hdlc: ucc@2000 { +- compatible = "fsl,ucc-hdlc"; +- rx-clock-name = "clk8"; +- tx-clock-name = "clk9"; +- fsl,rx-sync-clock = "rsync_pin"; +- fsl,tx-sync-clock = "tsync_pin"; +- fsl,tx-timeslot-mask = <0xfffffffe>; +- fsl,rx-timeslot-mask = <0xfffffffe>; +- fsl,tdm-framer-type = "e1"; +- fsl,tdm-id = <0>; +- fsl,siram-entry-id = <0>; +- fsl,tdm-interface; +- }; +- +- ucc_serial: ucc@2200 { +- compatible = "fsl,t1040-ucc-uart"; +- port-number = <0>; +- rx-clock-name = "brg2"; +- tx-clock-name = "brg2"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t104xrdb.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/t104xrdb.dtsi +deleted file mode 100644 +index 099a598c74c0..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t104xrdb.dtsi ++++ /dev/null +@@ -1,263 +0,0 @@ +-/* +- * T1040RDB/T1042RDB Device Tree Source +- * +- * Copyright 2014 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/ { +- aliases { +- phy_rgmii_0 = &phy_rgmii_0; +- phy_rgmii_1 = &phy_rgmii_1; +- phy_sgmii_2 = &phy_sgmii_2; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- ifc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x2000>; +- ranges = <0 0 0xf 0xe8000000 0x08000000 +- 2 0 0xf 0xff800000 0x00010000 +- 3 0 0xf 0xffdf0000 0x00008000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,ifc-nand"; +- reg = <0x2 0x0 0x10000>; +- }; +- +- cpld@3,0 { +- reg = <3 0 0x300>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01072000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x2000000>; +- }; +- +- qportals: qman-portals@ff6000000 { +- ranges = <0x0 0xf 0xf6000000 0x2000000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- +- spi@110000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q512ax3", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <10000000>; /* input clock */ +- }; +- slic@3 { +- compatible = "maxim,ds26522"; +- reg = <3>; +- spi-max-frequency = <2000000>; /* input clock */ +- }; +- }; +- +- i2c@118000 { +- adt7461@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- }; +- +- i2c@118100 { +- pca9546@77 { +- compatible = "nxp,pca9546"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- fman@400000 { +- ethernet@e6000 { +- phy-handle = <&phy_rgmii_0>; +- phy-connection-type = "rgmii"; +- }; +- +- ethernet@e8000 { +- phy-handle = <&phy_rgmii_1>; +- phy-connection-type = "rgmii"; +- }; +- +- mdio0: mdio@fc000 { +- phy_sgmii_2: ethernet-phy@3 { +- reg = <0x03>; +- }; +- +- phy_rgmii_0: ethernet-phy@1 { +- reg = <0x01>; +- }; +- +- phy_rgmii_1: ethernet-phy@2 { +- reg = <0x02>; +- }; +- }; +- }; +- }; +- +- pci0: pcie@ffe240000 { +- reg = <0xf 0xfe240000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci1: pcie@ffe250000 { +- reg = <0xf 0xfe250000 0 0x10000>; +- ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci2: pcie@ffe260000 { +- reg = <0xf 0xfe260000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci3: pcie@ffe270000 { +- reg = <0xf 0xfe270000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x10000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- qe: qe@ffe140000 { +- ranges = <0x0 0xf 0xfe140000 0x40000>; +- reg = <0xf 0xfe140000 0 0x480>; +- brg-frequency = <0>; +- bus-frequency = <0>; +- +- si1: si@700 { +- compatible = "fsl,t1040-qe-si"; +- reg = <0x700 0x80>; +- }; +- +- siram1: siram@1000 { +- compatible = "fsl,t1040-qe-siram"; +- reg = <0x1000 0x800>; +- }; +- +- ucc_hdlc: ucc@2000 { +- compatible = "fsl,ucc-hdlc"; +- rx-clock-name = "clk8"; +- tx-clock-name = "clk9"; +- fsl,rx-sync-clock = "rsync_pin"; +- fsl,tx-sync-clock = "tsync_pin"; +- fsl,tx-timeslot-mask = <0xfffffffe>; +- fsl,rx-timeslot-mask = <0xfffffffe>; +- fsl,tdm-framer-type = "e1"; +- fsl,tdm-id = <0>; +- fsl,siram-entry-id = <0>; +- fsl,tdm-interface; +- }; +- +- ucc_serial: ucc@2200 { +- compatible = "fsl,t1040-ucc-uart"; +- port-number = <0>; +- rx-clock-name = "brg2"; +- tx-clock-name = "brg2"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t104xsi-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/t104xsi-pre.dtsi +deleted file mode 100644 +index dd59e4b69480..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t104xsi-pre.dtsi ++++ /dev/null +@@ -1,115 +0,0 @@ +-/* +- * T1040/T1042 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2013-2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e5500_power_isa.dtsi" +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- ccsr = &soc; +- dcsr = &dcsr; +- +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- pci3 = &pci3; +- usb0 = &usb0; +- usb1 = &usb1; +- sdhc = &sdhc; +- +- crypto = &crypto; +- +- fman0 = &fman0; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- ethernet4 = &enet4; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: PowerPC,e5500@0 { +- device_type = "cpu"; +- reg = <0>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_1>; +- #cooling-cells = <2>; +- L2_1: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu1: PowerPC,e5500@1 { +- device_type = "cpu"; +- reg = <1>; +- clocks = <&clockgen 1 1>; +- next-level-cache = <&L2_2>; +- #cooling-cells = <2>; +- L2_2: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu2: PowerPC,e5500@2 { +- device_type = "cpu"; +- reg = <2>; +- clocks = <&clockgen 1 2>; +- next-level-cache = <&L2_3>; +- #cooling-cells = <2>; +- L2_3: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- cpu3: PowerPC,e5500@3 { +- device_type = "cpu"; +- reg = <3>; +- clocks = <&clockgen 1 3>; +- next-level-cache = <&L2_4>; +- #cooling-cells = <2>; +- L2_4: l2-cache { +- next-level-cache = <&cpc>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t2080qds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/t2080qds.dts +deleted file mode 100644 +index 8d190e8c62ce..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t2080qds.dts ++++ /dev/null +@@ -1,213 +0,0 @@ +-/* +- * T2080QDS Device Tree Source +- * +- * Copyright 2013 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "t208xsi-pre.dtsi" +-/include/ "t208xqds.dtsi" +- +-/ { +- model = "fsl,T2080QDS"; +- compatible = "fsl,T2080QDS"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- emi1_slot1 = &t2080mdio2; +- emi1_slot2 = &t2080mdio3; +- emi1_slot3 = &t2080mdio4; +- }; +- +- rio: rapidio@ffe0c0000 { +- reg = <0xf 0xfe0c0000 0 0x11000>; +- +- port1 { +- ranges = <0 0 0xc 0x20000000 0 0x10000000>; +- }; +- port2 { +- ranges = <0 0 0xc 0x30000000 0 0x10000000>; +- }; +- }; +-}; +- +-&soc { +- fman@400000 { +- ethernet@e0000 { +- phy-handle = <&phy_sgmii_s3_1e>; +- phy-connection-type = "xgmii"; +- }; +- +- ethernet@e2000 { +- phy-handle = <&phy_sgmii_s3_1f>; +- phy-connection-type = "xgmii"; +- }; +- +- ethernet@e4000 { +- phy-handle = <&rgmii_phy1>; +- phy-connection-type = "rgmii"; +- }; +- +- ethernet@e6000 { +- phy-handle = <&rgmii_phy2>; +- phy-connection-type = "rgmii"; +- }; +- +- ethernet@e8000 { +- phy-handle = <&phy_sgmii_s2_1e>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@ea000 { +- phy-handle = <&phy_sgmii_s2_1d>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@f0000 { +- phy-handle = <&phy_xaui_slot3>; +- phy-connection-type = "xgmii"; +- }; +- +- ethernet@f2000 { +- phy-handle = <&phy_sgmii_s3_1f>; +- phy-connection-type = "xgmii"; +- }; +- +- mdio@fd000 { +- phy_xaui_slot3: ethernet-phy@3 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x3>; +- }; +- }; +- }; +-}; +- +-&boardctrl { +- mdio-mux-emi1 { +- compatible = "mdio-mux-mmioreg", "mdio-mux"; +- mdio-parent-bus = <&mdio0>; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x54 1>; +- mux-mask = <0xe0>; +- +- t2080mdio0: mdio@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- rgmii_phy1: ethernet-phy@1 { +- reg = <0x1>; +- }; +- }; +- +- t2080mdio1: mdio@20 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x20>; +- +- rgmii_phy2: ethernet-phy@2 { +- reg = <0x2>; +- }; +- }; +- +- t2080mdio2: mdio@40 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x40>; +- status = "disabled"; +- +- phy_sgmii_s1_1c: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy_sgmii_s1_1d: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy_sgmii_s1_1e: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy_sgmii_s1_1f: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- +- t2080mdio3: mdio@c0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xc0>; +- +- phy_sgmii_s2_1c: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy_sgmii_s2_1d: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy_sgmii_s2_1e: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy_sgmii_s2_1f: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- +- t2080mdio4: mdio@60 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x60>; +- status = "disabled"; +- +- phy_sgmii_s3_1c: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy_sgmii_s3_1d: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy_sgmii_s3_1e: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy_sgmii_s3_1f: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- }; +-}; +- +-/include/ "t2080si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t2080rdb.dts b/scripts/dtc/include-prefixes/powerpc/fsl/t2080rdb.dts +deleted file mode 100644 +index 092a400740f8..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t2080rdb.dts ++++ /dev/null +@@ -1,122 +0,0 @@ +-/* +- * T2080PCIe-RDB Board Device Tree Source +- * +- * Copyright 2014 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "t208xsi-pre.dtsi" +-/include/ "t208xrdb.dtsi" +- +-/ { +- model = "fsl,T2080RDB"; +- compatible = "fsl,T2080RDB"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- rio: rapidio@ffe0c0000 { +- reg = <0xf 0xfe0c0000 0 0x11000>; +- +- port1 { +- ranges = <0 0 0xc 0x20000000 0 0x10000000>; +- }; +- port2 { +- ranges = <0 0 0xc 0x30000000 0 0x10000000>; +- }; +- }; +-}; +- +-&soc { +- fman@400000 { +- ethernet@e0000 { +- phy-handle = <&xg_aq1202_phy3>; +- phy-connection-type = "xgmii"; +- }; +- +- ethernet@e2000 { +- phy-handle = <&xg_aq1202_phy4>; +- phy-connection-type = "xgmii"; +- }; +- +- ethernet@e4000 { +- phy-handle = <&rgmii_phy1>; +- phy-connection-type = "rgmii"; +- }; +- +- ethernet@e6000 { +- phy-handle = <&rgmii_phy2>; +- phy-connection-type = "rgmii"; +- }; +- +- ethernet@f0000 { +- phy-handle = <&xg_cs4315_phy2>; +- phy-connection-type = "xgmii"; +- }; +- +- ethernet@f2000 { +- phy-handle = <&xg_cs4315_phy1>; +- phy-connection-type = "xgmii"; +- }; +- +- mdio@fc000 { +- rgmii_phy1: ethernet-phy@1 { +- reg = <0x1>; +- }; +- rgmii_phy2: ethernet-phy@2 { +- reg = <0x2>; +- }; +- }; +- +- mdio@fd000 { +- xg_cs4315_phy1: ethernet-phy@c { +- compatible = "ethernet-phy-id13e5.1002"; +- reg = <0xc>; +- }; +- +- xg_cs4315_phy2: ethernet-phy@d { +- compatible = "ethernet-phy-id13e5.1002"; +- reg = <0xd>; +- }; +- +- xg_aq1202_phy3: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x0>; +- }; +- +- xg_aq1202_phy4: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x1>; +- }; +- }; +- }; +-}; +- +-/include/ "t2080si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t2080si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/t2080si-post.dtsi +deleted file mode 100644 +index 082ec2044060..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t2080si-post.dtsi ++++ /dev/null +@@ -1,69 +0,0 @@ +-/* +- * T2080 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "t2081si-post.dtsi" +- +-&soc { +-/include/ "qoriq-sata2-0.dtsi" +- sata@220000 { +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */ +- }; +- +-/include/ "qoriq-sata2-1.dtsi" +- sata@221000 { +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */ +- }; +-}; +- +-&rio { +- compatible = "fsl,srio"; +- interrupts = <16 2 1 11>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- port1 { +- #address-cells = <2>; +- #size-cells = <2>; +- cell-index = <1>; +- }; +- +- port2 { +- #address-cells = <2>; +- #size-cells = <2>; +- cell-index = <2>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t2081qds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/t2081qds.dts +deleted file mode 100644 +index fc5c4a30f7ad..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t2081qds.dts ++++ /dev/null +@@ -1,265 +0,0 @@ +-/* +- * T2081QDS Device Tree Source +- * +- * Copyright 2013 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "t208xsi-pre.dtsi" +-/include/ "t208xqds.dtsi" +- +-/ { +- model = "fsl,T2081QDS"; +- compatible = "fsl,T2081QDS"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- emi1_slot1 = &t2081mdio2; +- emi1_slot2 = &t2081mdio3; +- emi1_slot3 = &t2081mdio4; +- emi1_slot5 = &t2081mdio5; +- emi1_slot6 = &t2081mdio6; +- emi1_slot7 = &t2081mdio7; +- }; +-}; +- +-&soc { +- fman@400000 { +- ethernet@e0000 { +- phy-handle = <&phy_sgmii_s7_1c>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e2000 { +- phy-handle = <&phy_sgmii_s7_1d>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e4000 { +- phy-handle = <&rgmii_phy1>; +- phy-connection-type = "rgmii"; +- }; +- +- ethernet@e6000 { +- phy-handle = <&rgmii_phy2>; +- phy-connection-type = "rgmii"; +- }; +- +- ethernet@e8000 { +- phy-handle = <&phy_sgmii_s3_1c>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@ea000 { +- phy-handle = <&phy_sgmii_s7_1f>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@f0000 { +- phy-handle = <&phy_sgmii_s2_1c>; +- phy-connection-type = "xgmii"; +- }; +- +- ethernet@f2000 { +- phy-handle = <&phy_sgmii_s7_1e>; +- phy-connection-type = "xgmii"; +- }; +- }; +-}; +- +-&boardctrl { +- mdio-mux-emi1 { +- compatible = "mdio-mux-mmioreg", "mdio-mux"; +- mdio-parent-bus = <&mdio0>; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x54 1>; +- mux-mask = <0xe0>; +- +- t2081mdio0: mdio@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- rgmii_phy1: ethernet-phy@1 { +- reg = <0x1>; +- }; +- }; +- +- t2081mdio1: mdio@20 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x20>; +- +- rgmii_phy2: ethernet-phy@2 { +- reg = <0x2>; +- }; +- }; +- +- t2081mdio2: mdio@40 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x40>; +- +- phy_sgmii_s1_1c: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy_sgmii_s1_1d: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy_sgmii_s1_1e: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy_sgmii_s1_1f: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- +- t2081mdio3: mdio@60 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x60>; +- +- phy_sgmii_s2_1c: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy_sgmii_s2_1d: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy_sgmii_s2_1e: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy_sgmii_s2_1f: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- +- t2081mdio4: mdio@80 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x80>; +- status = "disabled"; +- +- phy_sgmii_s3_1c: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy_sgmii_s3_1d: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy_sgmii_s3_1e: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy_sgmii_s3_1f: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- +- t2081mdio5: mdio@a0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xa0>; +- status = "disabled"; +- +- phy_sgmii_s5_1c: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy_sgmii_s5_1d: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy_sgmii_s5_1e: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy_sgmii_s5_1f: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- +- t2081mdio6: mdio@c0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xc0>; +- status = "disabled"; +- +- phy_sgmii_s6_1c: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy_sgmii_s6_1d: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy_sgmii_s6_1e: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy_sgmii_s6_1f: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- +- t2081mdio7: mdio@e0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0xe0>; +- +- phy_sgmii_s7_1c: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- phy_sgmii_s7_1d: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- phy_sgmii_s7_1e: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- phy_sgmii_s7_1f: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- }; +-}; +- +-/include/ "t2081si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t2081si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/t2081si-post.dtsi +deleted file mode 100644 +index ecbb447920bc..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t2081si-post.dtsi ++++ /dev/null +@@ -1,661 +0,0 @@ +-/* +- * T2081 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2013 - 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&bman_fbpr { +- compatible = "fsl,bman-fbpr"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&qman_fqd { +- compatible = "fsl,qman-fqd"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&qman_pfdr { +- compatible = "fsl,qman-pfdr"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&ifc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,ifc", "simple-bus"; +- interrupts = <25 2 0 0>; +-}; +- +-/* controller at 0x240000 */ +-&pci0 { +- compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- interrupts = <20 2 0 0>; +- fsl,iommu-parent = <&pamu0>; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <20 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 40 1 0 0 +- 0000 0 0 2 &mpic 1 1 0 0 +- 0000 0 0 3 &mpic 2 1 0 0 +- 0000 0 0 4 &mpic 3 1 0 0 +- >; +- }; +-}; +- +-/* controller at 0x250000 */ +-&pci1 { +- compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 0xff>; +- interrupts = <21 2 0 0>; +- fsl,iommu-parent = <&pamu0>; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <21 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 41 1 0 0 +- 0000 0 0 2 &mpic 5 1 0 0 +- 0000 0 0 3 &mpic 6 1 0 0 +- 0000 0 0 4 &mpic 7 1 0 0 +- >; +- }; +-}; +- +-/* controller at 0x260000 */ +-&pci2 { +- compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- interrupts = <22 2 0 0>; +- fsl,iommu-parent = <&pamu0>; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <22 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 42 1 0 0 +- 0000 0 0 2 &mpic 9 1 0 0 +- 0000 0 0 3 &mpic 10 1 0 0 +- 0000 0 0 4 &mpic 11 1 0 0 +- >; +- }; +-}; +- +-/* controller at 0x270000 */ +-&pci3 { +- compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- interrupts = <23 2 0 0>; +- fsl,iommu-parent = <&pamu0>; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- interrupts = <23 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 43 1 0 0 +- 0000 0 0 2 &mpic 0 1 0 0 +- 0000 0 0 3 &mpic 4 1 0 0 +- 0000 0 0 4 &mpic 8 1 0 0 +- >; +- }; +-}; +- +-&dcsr { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,dcsr", "simple-bus"; +- +- dcsr-epu@0 { +- compatible = "fsl,t2080-dcsr-epu", "fsl,dcsr-epu"; +- interrupts = <52 2 0 0 +- 84 2 0 0 +- 85 2 0 0 +- 94 2 0 0 +- 95 2 0 0>; +- reg = <0x0 0x1000>; +- }; +- dcsr-npc { +- compatible = "fsl,t2080-dcsr-cnpc", "fsl,dcsr-cnpc"; +- reg = <0x1000 0x1000 0x1002000 0x10000>; +- }; +- dcsr-nxc@2000 { +- compatible = "fsl,dcsr-nxc"; +- reg = <0x2000 0x1000>; +- }; +- dcsr-corenet { +- compatible = "fsl,dcsr-corenet"; +- reg = <0x8000 0x1000 0x1A000 0x1000>; +- }; +- dcsr-ocn@11000 { +- compatible = "fsl,t2080-dcsr-ocn", "fsl,dcsr-ocn"; +- reg = <0x11000 0x1000>; +- }; +- dcsr-ddr@12000 { +- compatible = "fsl,dcsr-ddr"; +- dev-handle = <&ddr1>; +- reg = <0x12000 0x1000>; +- }; +- dcsr-nal@18000 { +- compatible = "fsl,t2080-dcsr-nal", "fsl,dcsr-nal"; +- reg = <0x18000 0x1000>; +- }; +- dcsr-rcpm@22000 { +- compatible = "fsl,t2080-dcsr-rcpm", "fsl,dcsr-rcpm"; +- reg = <0x22000 0x1000>; +- }; +- dcsr-snpc@30000 { +- compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc"; +- reg = <0x30000 0x1000 0x1022000 0x10000>; +- }; +- dcsr-snpc@31000 { +- compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc"; +- reg = <0x31000 0x1000 0x1042000 0x10000>; +- }; +- dcsr-snpc@32000 { +- compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc"; +- reg = <0x32000 0x1000 0x1062000 0x10000>; +- }; +- dcsr-cpu-sb-proxy@100000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu0>; +- reg = <0x100000 0x1000 0x101000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@108000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu1>; +- reg = <0x108000 0x1000 0x109000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@110000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu2>; +- reg = <0x110000 0x1000 0x111000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@118000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu3>; +- reg = <0x118000 0x1000 0x119000 0x1000>; +- }; +-}; +- +-&bportals { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- compatible = "simple-bus"; +- +- bman-portal@0 { +- compatible = "fsl,bman-portal"; +- reg = <0x0 0x4000>, <0x1000000 0x1000>; +- interrupts = <105 2 0 0>; +- }; +- bman-portal@4000 { +- compatible = "fsl,bman-portal"; +- reg = <0x4000 0x4000>, <0x1001000 0x1000>; +- interrupts = <107 2 0 0>; +- }; +- bman-portal@8000 { +- compatible = "fsl,bman-portal"; +- reg = <0x8000 0x4000>, <0x1002000 0x1000>; +- interrupts = <109 2 0 0>; +- }; +- bman-portal@c000 { +- compatible = "fsl,bman-portal"; +- reg = <0xc000 0x4000>, <0x1003000 0x1000>; +- interrupts = <111 2 0 0>; +- }; +- bman-portal@10000 { +- compatible = "fsl,bman-portal"; +- reg = <0x10000 0x4000>, <0x1004000 0x1000>; +- interrupts = <113 2 0 0>; +- }; +- bman-portal@14000 { +- compatible = "fsl,bman-portal"; +- reg = <0x14000 0x4000>, <0x1005000 0x1000>; +- interrupts = <115 2 0 0>; +- }; +- bman-portal@18000 { +- compatible = "fsl,bman-portal"; +- reg = <0x18000 0x4000>, <0x1006000 0x1000>; +- interrupts = <117 2 0 0>; +- }; +- bman-portal@1c000 { +- compatible = "fsl,bman-portal"; +- reg = <0x1c000 0x4000>, <0x1007000 0x1000>; +- interrupts = <119 2 0 0>; +- }; +- bman-portal@20000 { +- compatible = "fsl,bman-portal"; +- reg = <0x20000 0x4000>, <0x1008000 0x1000>; +- interrupts = <121 2 0 0>; +- }; +- bman-portal@24000 { +- compatible = "fsl,bman-portal"; +- reg = <0x24000 0x4000>, <0x1009000 0x1000>; +- interrupts = <123 2 0 0>; +- }; +- bman-portal@28000 { +- compatible = "fsl,bman-portal"; +- reg = <0x28000 0x4000>, <0x100a000 0x1000>; +- interrupts = <125 2 0 0>; +- }; +- bman-portal@2c000 { +- compatible = "fsl,bman-portal"; +- reg = <0x2c000 0x4000>, <0x100b000 0x1000>; +- interrupts = <127 2 0 0>; +- }; +- bman-portal@30000 { +- compatible = "fsl,bman-portal"; +- reg = <0x30000 0x4000>, <0x100c000 0x1000>; +- interrupts = <129 2 0 0>; +- }; +- bman-portal@34000 { +- compatible = "fsl,bman-portal"; +- reg = <0x34000 0x4000>, <0x100d000 0x1000>; +- interrupts = <131 2 0 0>; +- }; +- bman-portal@38000 { +- compatible = "fsl,bman-portal"; +- reg = <0x38000 0x4000>, <0x100e000 0x1000>; +- interrupts = <133 2 0 0>; +- }; +- bman-portal@3c000 { +- compatible = "fsl,bman-portal"; +- reg = <0x3c000 0x4000>, <0x100f000 0x1000>; +- interrupts = <135 2 0 0>; +- }; +- bman-portal@40000 { +- compatible = "fsl,bman-portal"; +- reg = <0x40000 0x4000>, <0x1010000 0x1000>; +- interrupts = <137 2 0 0>; +- }; +- bman-portal@44000 { +- compatible = "fsl,bman-portal"; +- reg = <0x44000 0x4000>, <0x1011000 0x1000>; +- interrupts = <139 2 0 0>; +- }; +-}; +- +-&qportals { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- compatible = "simple-bus"; +- +- qportal0: qman-portal@0 { +- compatible = "fsl,qman-portal"; +- reg = <0x0 0x4000>, <0x1000000 0x1000>; +- interrupts = <104 0x2 0 0>; +- cell-index = <0x0>; +- }; +- qportal1: qman-portal@4000 { +- compatible = "fsl,qman-portal"; +- reg = <0x4000 0x4000>, <0x1001000 0x1000>; +- interrupts = <106 0x2 0 0>; +- cell-index = <0x1>; +- }; +- qportal2: qman-portal@8000 { +- compatible = "fsl,qman-portal"; +- reg = <0x8000 0x4000>, <0x1002000 0x1000>; +- interrupts = <108 0x2 0 0>; +- cell-index = <0x2>; +- }; +- qportal3: qman-portal@c000 { +- compatible = "fsl,qman-portal"; +- reg = <0xc000 0x4000>, <0x1003000 0x1000>; +- interrupts = <110 0x2 0 0>; +- cell-index = <0x3>; +- }; +- qportal4: qman-portal@10000 { +- compatible = "fsl,qman-portal"; +- reg = <0x10000 0x4000>, <0x1004000 0x1000>; +- interrupts = <112 0x2 0 0>; +- cell-index = <0x4>; +- }; +- qportal5: qman-portal@14000 { +- compatible = "fsl,qman-portal"; +- reg = <0x14000 0x4000>, <0x1005000 0x1000>; +- interrupts = <114 0x2 0 0>; +- cell-index = <0x5>; +- }; +- qportal6: qman-portal@18000 { +- compatible = "fsl,qman-portal"; +- reg = <0x18000 0x4000>, <0x1006000 0x1000>; +- interrupts = <116 0x2 0 0>; +- cell-index = <0x6>; +- }; +- qportal7: qman-portal@1c000 { +- compatible = "fsl,qman-portal"; +- reg = <0x1c000 0x4000>, <0x1007000 0x1000>; +- interrupts = <118 0x2 0 0>; +- cell-index = <0x7>; +- }; +- qportal8: qman-portal@20000 { +- compatible = "fsl,qman-portal"; +- reg = <0x20000 0x4000>, <0x1008000 0x1000>; +- interrupts = <120 0x2 0 0>; +- cell-index = <0x8>; +- }; +- qportal9: qman-portal@24000 { +- compatible = "fsl,qman-portal"; +- reg = <0x24000 0x4000>, <0x1009000 0x1000>; +- interrupts = <122 0x2 0 0>; +- cell-index = <0x9>; +- }; +- qportal10: qman-portal@28000 { +- compatible = "fsl,qman-portal"; +- reg = <0x28000 0x4000>, <0x100a000 0x1000>; +- interrupts = <124 0x2 0 0>; +- cell-index = <0xa>; +- }; +- qportal11: qman-portal@2c000 { +- compatible = "fsl,qman-portal"; +- reg = <0x2c000 0x4000>, <0x100b000 0x1000>; +- interrupts = <126 0x2 0 0>; +- cell-index = <0xb>; +- }; +- qportal12: qman-portal@30000 { +- compatible = "fsl,qman-portal"; +- reg = <0x30000 0x4000>, <0x100c000 0x1000>; +- interrupts = <128 0x2 0 0>; +- cell-index = <0xc>; +- }; +- qportal13: qman-portal@34000 { +- compatible = "fsl,qman-portal"; +- reg = <0x34000 0x4000>, <0x100d000 0x1000>; +- interrupts = <130 0x2 0 0>; +- cell-index = <0xd>; +- }; +- qportal14: qman-portal@38000 { +- compatible = "fsl,qman-portal"; +- reg = <0x38000 0x4000>, <0x100e000 0x1000>; +- interrupts = <132 0x2 0 0>; +- cell-index = <0xe>; +- }; +- qportal15: qman-portal@3c000 { +- compatible = "fsl,qman-portal"; +- reg = <0x3c000 0x4000>, <0x100f000 0x1000>; +- interrupts = <134 0x2 0 0>; +- cell-index = <0xf>; +- }; +- qportal16: qman-portal@40000 { +- compatible = "fsl,qman-portal"; +- reg = <0x40000 0x4000>, <0x1010000 0x1000>; +- interrupts = <136 0x2 0 0>; +- cell-index = <0x10>; +- }; +- qportal17: qman-portal@44000 { +- compatible = "fsl,qman-portal"; +- reg = <0x44000 0x4000>, <0x1011000 0x1000>; +- interrupts = <138 0x2 0 0>; +- cell-index = <0x11>; +- }; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- +- soc-sram-error { +- compatible = "fsl,soc-sram-error"; +- interrupts = <16 2 1 29>; +- }; +- +- corenet-law@0 { +- compatible = "fsl,corenet-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <32>; +- }; +- +- ddr1: memory-controller@8000 { +- compatible = "fsl,qoriq-memory-controller-v4.7", +- "fsl,qoriq-memory-controller"; +- reg = <0x8000 0x1000>; +- interrupts = <16 2 1 23>; +- }; +- +- cpc: l3-cache-controller@10000 { +- compatible = "fsl,t2080-l3-cache-controller", "cache"; +- reg = <0x10000 0x1000 +- 0x11000 0x1000 +- 0x12000 0x1000>; +- interrupts = <16 2 1 27 +- 16 2 1 26 +- 16 2 1 25>; +- }; +- +- corenet-cf@18000 { +- compatible = "fsl,corenet2-cf", "fsl,corenet-cf"; +- reg = <0x18000 0x1000>; +- interrupts = <16 2 1 31>; +- fsl,ccf-num-csdids = <32>; +- fsl,ccf-num-snoopids = <32>; +- }; +- +- iommu@20000 { +- compatible = "fsl,pamu-v1.0", "fsl,pamu"; +- reg = <0x20000 0x3000>; +- fsl,portid-mapping = <0x8000>; +- ranges = <0 0x20000 0x3000>; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupts = < +- 24 2 0 0 +- 16 2 1 30>; +- +- pamu0: pamu@0 { +- reg = <0 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- +- pamu1: pamu@1000 { +- reg = <0x1000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- +- pamu2: pamu@2000 { +- reg = <0x2000 0x1000>; +- fsl,primary-cache-geometry = <32 1>; +- fsl,secondary-cache-geometry = <128 2>; +- }; +- }; +- +-/include/ "qoriq-mpic4.3.dtsi" +- +- guts: global-utilities@e0000 { +- compatible = "fsl,t2080-device-config", "fsl,qoriq-device-config-2.0"; +- reg = <0xe0000 0xe00>; +- fsl,has-rstcr; +- fsl,liodn-bits = <12>; +- }; +- +-/include/ "qoriq-clockgen2.dtsi" +- global-utilities@e1000 { +- compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0"; +- }; +- +- rcpm: global-utilities@e2000 { +- compatible = "fsl,t2080-rcpm", "fsl,qoriq-rcpm-2.0"; +- reg = <0xe2000 0x1000>; +- }; +- +- sfp: sfp@e8000 { +- compatible = "fsl,t2080-sfp"; +- reg = <0xe8000 0x1000>; +- }; +- +- serdes: serdes@ea000 { +- compatible = "fsl,t2080-serdes"; +- reg = <0xea000 0x4000>; +- }; +- +-/include/ "elo3-dma-0.dtsi" +- dma@100300 { +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ +- }; +-/include/ "elo3-dma-1.dtsi" +- dma@101300 { +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ +- }; +-/include/ "elo3-dma-2.dtsi" +- dma@102300 { +- fsl,iommu-parent = <&pamu0>; +- fsl,liodn-reg = <&guts 0x588>; /* DMA3LIODNR */ +- }; +- +-/include/ "qoriq-espi-0.dtsi" +- spi@110000 { +- fsl,espi-num-chipselects = <4>; +- }; +- +-/include/ "qoriq-esdhc-0.dtsi" +- sdhc@114000 { +- compatible = "fsl,t2080-esdhc", "fsl,esdhc"; +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x530>; /* SDMMCLIODNR */ +- sdhci,auto-cmd12; +- }; +-/include/ "qoriq-i2c-0.dtsi" +-/include/ "qoriq-i2c-1.dtsi" +-/include/ "qoriq-duart-0.dtsi" +-/include/ "qoriq-duart-1.dtsi" +-/include/ "qoriq-gpio-0.dtsi" +-/include/ "qoriq-gpio-1.dtsi" +-/include/ "qoriq-gpio-2.dtsi" +-/include/ "qoriq-gpio-3.dtsi" +-/include/ "qoriq-usb2-mph-0.dtsi" +- usb0: usb@210000 { +- compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph"; +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ +- phy_type = "utmi"; +- port0; +- }; +-/include/ "qoriq-usb2-dr-0.dtsi" +- usb1: usb@211000 { +- compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; +- fsl,iommu-parent = <&pamu1>; +- fsl,liodn-reg = <&guts 0x524>; /* USB1LIODNR */ +- dr_mode = "host"; +- phy_type = "utmi"; +- }; +-/include/ "qoriq-sec5.2-0.dtsi" +-/include/ "qoriq-qman3.dtsi" +-/include/ "qoriq-bman1.dtsi" +- +-/include/ "qoriq-fman3-0.dtsi" +-/include/ "qoriq-fman3-0-1g-0.dtsi" +-/include/ "qoriq-fman3-0-1g-1.dtsi" +-/include/ "qoriq-fman3-0-1g-2.dtsi" +-/include/ "qoriq-fman3-0-1g-3.dtsi" +-/include/ "qoriq-fman3-0-1g-4.dtsi" +-/include/ "qoriq-fman3-0-1g-5.dtsi" +-/include/ "qoriq-fman3-0-10g-0.dtsi" +-/include/ "qoriq-fman3-0-10g-1.dtsi" +- fman@400000 { +- enet0: ethernet@e0000 { +- }; +- +- enet1: ethernet@e2000 { +- }; +- +- enet2: ethernet@e4000 { +- }; +- +- enet3: ethernet@e6000 { +- }; +- +- enet4: ethernet@e8000 { +- }; +- +- enet5: ethernet@ea000 { +- }; +- +- enet6: ethernet@f0000 { +- }; +- +- enet7: ethernet@f2000 { +- }; +- +- mdio@fc000 { +- interrupts = <100 1 0 0>; +- }; +- +- mdio@fd000 { +- interrupts = <101 1 0 0>; +- }; +- }; +- +- L2_1: l2-cache-controller@c20000 { +- /* Cluster 0 L2 cache */ +- compatible = "fsl,t2080-l2-cache-controller"; +- reg = <0xc20000 0x40000>; +- next-level-cache = <&cpc>; +- interrupts = <16 2 1 9>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t208xqds.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/t208xqds.dtsi +deleted file mode 100644 +index db4139999b28..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t208xqds.dtsi ++++ /dev/null +@@ -1,277 +0,0 @@ +-/* +- * T2080/T2081 QDS Device Tree Source +- * +- * Copyright 2013 - 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/ { +- model = "fsl,T2080QDS"; +- compatible = "fsl,T2080QDS"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- ifc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x2000>; +- ranges = <0 0 0xf 0xe8000000 0x08000000 +- 2 0 0xf 0xff800000 0x00010000 +- 3 0 0xf 0xffdf0000 0x00008000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,ifc-nand"; +- reg = <0x2 0x0 0x10000>; +- }; +- +- boardctrl: board-control@3,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,fpga-qixis"; +- reg = <3 0 0x300>; +- ranges = <0 3 0 0x300>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01072000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x2000000>; +- }; +- +- qportals: qman-portals@ff6000000 { +- ranges = <0x0 0xf 0xf6000000 0x2000000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- spi@110000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */ +- reg = <0>; +- spi-max-frequency = <40000000>; /* input clock */ +- }; +- +- flash@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "sst,sst25wf040", "jedec,spi-nor"; +- reg = <1>; +- spi-max-frequency = <35000000>; +- }; +- +- flash@2 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "eon,en25s64", "jedec,spi-nor"; +- reg = <2>; +- spi-max-frequency = <35000000>; +- }; +- }; +- +- i2c@118000 { +- pca9547@77 { +- compatible = "nxp,pca9547"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0>; +- +- eeprom@50 { +- compatible = "atmel,24c512"; +- reg = <0x50>; +- }; +- +- eeprom@51 { +- compatible = "atmel,24c02"; +- reg = <0x51>; +- }; +- +- eeprom@57 { +- compatible = "atmel,24c02"; +- reg = <0x57>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds3232"; +- reg = <0x68>; +- interrupts = <0xb 0x1 0 0>; +- }; +- }; +- +- i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x1>; +- +- eeprom@55 { +- compatible = "atmel,24c02"; +- reg = <0x55>; +- }; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; +- +- ina220@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <1000>; +- }; +- +- ina220@41 { +- compatible = "ti,ina220"; +- reg = <0x41>; +- shunt-resistor = <1000>; +- }; +- }; +- +- i2c@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3>; +- +- adt7461@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- }; +- }; +- }; +- +- sdhc@114000 { +- voltage-ranges = <1800 1800 3300 3300>; +- }; +- }; +- +- pci0: pcie@ffe240000 { +- reg = <0xf 0xfe240000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci1: pcie@ffe250000 { +- reg = <0xf 0xfe250000 0 0x10000>; +- ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci2: pcie@ffe260000 { +- reg = <0xf 0xfe260000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci3: pcie@ffe270000 { +- reg = <0xf 0xfe270000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t208xrdb.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/t208xrdb.dtsi +deleted file mode 100644 +index ff87e67c70da..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t208xrdb.dtsi ++++ /dev/null +@@ -1,211 +0,0 @@ +-/* +- * T2080PCIe-RDB Board Device Tree Source +- * +- * Copyright 2014 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/ { +- model = "fsl,T2080RDB"; +- compatible = "fsl,T2080RDB"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- ifc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x2000>; +- ranges = <0 0 0xf 0xe8000000 0x08000000 +- 2 0 0xf 0xff800000 0x00010000 +- 3 0 0xf 0xffdf0000 0x00008000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,ifc-nand"; +- reg = <0x2 0x0 0x10000>; +- }; +- +- boardctrl: board-control@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,t2080-cpld"; +- reg = <3 0 0x300>; +- ranges = <0 3 0 0x300>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01072000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x2000000>; +- }; +- +- qportals: qman-portals@ff6000000 { +- ranges = <0x0 0xf 0xf6000000 0x2000000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- spi@110000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "micron,n25q512ax3", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <10000000>; /* input clock */ +- }; +- }; +- +- i2c@118000 { +- adt7481@4c { +- compatible = "adi,adt7481"; +- reg = <0x4c>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- interrupts = <0x1 0x1 0 0>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- }; +- }; +- +- i2c@118100 { +- pca9546@77 { +- compatible = "nxp,pca9546"; +- reg = <0x77>; +- }; +- }; +- +- sdhc@114000 { +- voltage-ranges = <1800 1800 3300 3300>; +- }; +- }; +- +- pci0: pcie@ffe240000 { +- reg = <0xf 0xfe240000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci1: pcie@ffe250000 { +- reg = <0xf 0xfe250000 0 0x10000>; +- ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci2: pcie@ffe260000 { +- reg = <0xf 0xfe260000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci3: pcie@ffe270000 { +- reg = <0xf 0xfe270000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t208xsi-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/t208xsi-pre.dtsi +deleted file mode 100644 +index 3f745de44284..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t208xsi-pre.dtsi ++++ /dev/null +@@ -1,110 +0,0 @@ +-/* +- * T2080/T2081 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2013 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e6500_power_isa.dtsi" +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- ccsr = &soc; +- dcsr = &dcsr; +- +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- +- crypto = &crypto; +- +- fman0 = &fman0; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- ethernet4 = &enet4; +- ethernet5 = &enet5; +- ethernet6 = &enet6; +- ethernet7 = &enet7; +- +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- pci3 = &pci3; +- usb0 = &usb0; +- usb1 = &usb1; +- dma0 = &dma0; +- dma1 = &dma1; +- dma2 = &dma2; +- sdhc = &sdhc; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: PowerPC,e6500@0 { +- device_type = "cpu"; +- reg = <0 1>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_1>; +- fsl,portid-mapping = <0x80000000>; +- }; +- cpu1: PowerPC,e6500@2 { +- device_type = "cpu"; +- reg = <2 3>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_1>; +- fsl,portid-mapping = <0x80000000>; +- }; +- cpu2: PowerPC,e6500@4 { +- device_type = "cpu"; +- reg = <4 5>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_1>; +- fsl,portid-mapping = <0x80000000>; +- }; +- cpu3: PowerPC,e6500@6 { +- device_type = "cpu"; +- reg = <6 7>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_1>; +- fsl,portid-mapping = <0x80000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t4240qds.dts b/scripts/dtc/include-prefixes/powerpc/fsl/t4240qds.dts +deleted file mode 100644 +index c0913ac5aaad..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t4240qds.dts ++++ /dev/null +@@ -1,708 +0,0 @@ +-/* +- * T4240QDS Device Tree Source +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "t4240si-pre.dtsi" +- +-/ { +- model = "fsl,T4240QDS"; +- compatible = "fsl,T4240QDS"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases{ +- phy_rgmii1 = &phyrgmii1; +- phy_rgmii2 = &phyrgmii2; +- phy_sgmii3 = &phy3; +- phy_sgmii4 = &phy4; +- phy_sgmii11 = &phy11; +- phy_sgmii12 = &phy12; +- sgmii_phy11 = &sgmiiphy11; +- sgmii_phy12 = &sgmiiphy12; +- sgmii_phy13 = &sgmiiphy13; +- sgmii_phy14 = &sgmiiphy14; +- sgmii_phy21 = &sgmiiphy21; +- sgmii_phy22 = &sgmiiphy22; +- sgmii_phy23 = &sgmiiphy23; +- sgmii_phy24 = &sgmiiphy24; +- sgmii_phy31 = &sgmiiphy31; +- sgmii_phy32 = &sgmiiphy32; +- sgmii_phy33 = &sgmiiphy33; +- sgmii_phy34 = &sgmiiphy34; +- sgmii_phy41 = &sgmiiphy41; +- sgmii_phy42 = &sgmiiphy42; +- sgmii_phy43 = &sgmiiphy43; +- sgmii_phy44 = &sgmiiphy44; +- phy_xfi1 = &xfiphy1; +- phy_xfi2 = &xfiphy2; +- phy_xfi3 = &xfiphy3; +- phy_xfi4 = &xfiphy4; +- xfi_pcs_mdio1 = &xfimdio0; +- xfi_pcs_mdio2 = &xfimdio1; +- xfi_pcs_mdio3 = &xfimdio2; +- xfi_pcs_mdio4 = &xfimdio3; +- emi1_rgmii = &t4240mdio0; +- emi1_slot1 = &t4240mdio1; +- emi1_slot2 = &t4240mdio2; +- emi1_slot3 = &t4240mdio3; +- emi1_slot4 = &t4240mdio4; +- }; +- +- ifc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x2000>; +- ranges = <0 0 0xf 0xe8000000 0x08000000 +- 2 0 0xf 0xff800000 0x00010000 +- 3 0 0xf 0xffdf0000 0x00008000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,ifc-nand"; +- reg = <0x2 0x0 0x10000>; +- +- partition@0 { +- /* This location must not be altered */ +- /* 1MB for u-boot Bootloader Image */ +- reg = <0x0 0x00100000>; +- label = "NAND U-Boot Image"; +- read-only; +- }; +- +- partition@100000 { +- /* 1MB for DTB Image */ +- reg = <0x00100000 0x00100000>; +- label = "NAND DTB Image"; +- }; +- +- partition@200000 { +- /* 10MB for Linux Kernel Image */ +- reg = <0x00200000 0x00A00000>; +- label = "NAND Linux Kernel Image"; +- }; +- +- partition@C00000 { +- /* 500MB for Root file System Image */ +- reg = <0x00c00000 0x1F400000>; +- label = "NAND RFS Image"; +- }; +- }; +- +- board-control@3,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,t4240qds-fpga", "fsl,fpga-qixis"; +- reg = <3 0 0x300>; +- ranges = <0 3 0 0x300>; +- +- mdio-mux-emi1 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "mdio-mux-mmioreg", "mdio-mux"; +- mdio-parent-bus = <&mdio1>; +- reg = <0x54 1>; +- mux-mask = <0xe0>; +- +- t4240mdio0: mdio@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- phyrgmii1: ethernet-phy@1 { +- reg = <0x1>; +- }; +- +- phyrgmii2: ethernet-phy@2 { +- reg = <0x2>; +- }; +- }; +- +- t4240mdio1: mdio@20 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x20>; +- status = "disabled"; +- +- phy1: ethernet-phy@0 { +- reg = <0x0>; +- }; +- +- phy2: ethernet-phy@1 { +- reg = <0x1>; +- }; +- +- phy3: ethernet-phy@2 { +- reg = <0x2>; +- }; +- +- phy4: ethernet-phy@3 { +- reg = <0x3>; +- }; +- +- sgmiiphy11: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- sgmiiphy12: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- sgmiiphy13: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- sgmiiphy14: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- +- t4240mdio2: mdio@40 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x40>; +- status = "disabled"; +- +- phy5: ethernet-phy@4 { +- reg = <0x4>; +- }; +- +- phy6: ethernet-phy@5 { +- reg = <0x5>; +- }; +- +- phy7: ethernet-phy@6 { +- reg = <0x6>; +- }; +- +- phy8: ethernet-phy@7 { +- reg = <0x7>; +- }; +- +- sgmiiphy21: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- sgmiiphy22: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- sgmiiphy23: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- sgmiiphy24: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- +- t4240mdio3: mdio@60 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x60>; +- status = "disabled"; +- +- phy9: ethernet-phy@8 { +- reg = <0x8>; +- }; +- +- phy10: ethernet-phy@9 { +- reg = <0x9>; +- }; +- +- phy11: ethernet-phy@a { +- reg = <0xa>; +- }; +- +- phy12: ethernet-phy@b { +- reg = <0xb>; +- }; +- +- sgmiiphy31: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- sgmiiphy32: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- sgmiiphy33: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- sgmiiphy34: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- +- t4240mdio4: mdio@80 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x80>; +- status = "disabled"; +- +- phy13: ethernet-phy@c { +- reg = <0xc>; +- }; +- +- phy14: ethernet-phy@d { +- reg = <0xd>; +- }; +- +- phy15: ethernet-phy@e { +- reg = <0xe>; +- }; +- +- phy16: ethernet-phy@f { +- reg = <0xf>; +- }; +- +- sgmiiphy41: ethernet-phy@1c { +- reg = <0x1c>; +- }; +- +- sgmiiphy42: ethernet-phy@1d { +- reg = <0x1d>; +- }; +- +- sgmiiphy43: ethernet-phy@1e { +- reg = <0x1e>; +- }; +- +- sgmiiphy44: ethernet-phy@1f { +- reg = <0x1f>; +- }; +- }; +- }; +- }; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01072000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x2000000>; +- }; +- +- qportals: qman-portals@ff6000000 { +- ranges = <0x0 0xf 0xf6000000 0x2000000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- spi@110000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "sst,sst25wf040", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; /* input clock */ +- }; +- }; +- +- i2c@118000 { +- mux@77 { +- compatible = "nxp,pca9547"; +- reg = <0x77>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- eeprom@51 { +- compatible = "atmel,24c256"; +- reg = <0x51>; +- }; +- eeprom@52 { +- compatible = "atmel,24c256"; +- reg = <0x52>; +- }; +- eeprom@53 { +- compatible = "atmel,24c256"; +- reg = <0x53>; +- }; +- eeprom@54 { +- compatible = "atmel,24c256"; +- reg = <0x54>; +- }; +- eeprom@55 { +- compatible = "atmel,24c256"; +- reg = <0x55>; +- }; +- eeprom@56 { +- compatible = "atmel,24c256"; +- reg = <0x56>; +- }; +- rtc@68 { +- compatible = "dallas,ds3232"; +- reg = <0x68>; +- interrupts = <0x1 0x1 0 0>; +- }; +- }; +- +- i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2>; +- +- ina220@40 { +- compatible = "ti,ina220"; +- reg = <0x40>; +- shunt-resistor = <1000>; +- }; +- +- ina220@41 { +- compatible = "ti,ina220"; +- reg = <0x41>; +- shunt-resistor = <1000>; +- }; +- +- ina220@44 { +- compatible = "ti,ina220"; +- reg = <0x44>; +- shunt-resistor = <1000>; +- }; +- +- ina220@45 { +- compatible = "ti,ina220"; +- reg = <0x45>; +- shunt-resistor = <1000>; +- }; +- +- ina220@46 { +- compatible = "ti,ina220"; +- reg = <0x46>; +- shunt-resistor = <1000>; +- }; +- +- ina220@47 { +- compatible = "ti,ina220"; +- reg = <0x47>; +- shunt-resistor = <1000>; +- }; +- }; +- }; +- }; +- +- sdhc@114000 { +- voltage-ranges = <1800 1800 3300 3300>; +- }; +- +- fman@400000 { +- port@83000 { +- status = "disabled"; +- }; +- +- port@84000 { +- status = "disabled"; +- }; +- +- port@85000 { +- status = "disabled"; +- }; +- +- port@86000 { +- status = "disabled"; +- }; +- +- port@87000 { +- status = "disabled"; +- }; +- +- ethernet@e0000 { +- phy-handle = <&phy5>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e2000 { +- phy-handle = <&phy6>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e4000 { +- phy-handle = <&phy7>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e6000 { +- phy-handle = <&phy8>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e8000 { +- phy-handle = <&phyrgmii2>; +- phy-connection-type = "rgmii"; +- }; +- +- ethernet@ea000 { +- phy-handle = <&phy2>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@f0000 { +- phy-handle = <&xauiphy1>; +- phy-connection-type = "xgmii"; +- }; +- +- ethernet@f2000 { +- phy-handle = <&xauiphy2>; +- phy-connection-type = "xgmii"; +- }; +- +- xfimdio0: mdio@f1000 { +- status = "disabled"; +- +- xfiphy1: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x0>; +- }; +- }; +- +- xfimdio1: mdio@f3000 { +- status = "disabled"; +- +- xfiphy2: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x0>; +- }; +- }; +- }; +- +- fman@500000 { +- port@84000 { +- status = "disabled"; +- }; +- +- port@85000 { +- status = "disabled"; +- }; +- +- port@86000 { +- status = "disabled"; +- }; +- +- port@87000 { +- status = "disabled"; +- }; +- +- ethernet@e0000 { +- phy-handle = <&phy13>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e2000 { +- phy-handle = <&phy14>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e4000 { +- phy-handle = <&phy15>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e6000 { +- phy-handle = <&phy16>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e8000 { +- phy-handle = <&phyrgmii1>; +- phy-connection-type = "rgmii"; +- }; +- +- ethernet@ea000 { +- phy-handle = <&phy10>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@f0000 { +- phy-handle = <&xauiphy3>; +- phy-connection-type = "xgmii"; +- }; +- +- ethernet@f2000 { +- phy-handle = <&xauiphy4>; +- phy-connection-type = "xgmii"; +- }; +- +- xfimdio2: mdio@f1000 { +- status = "disabled"; +- +- xfiphy3: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x0>; +- }; +- }; +- +- xfimdio3: mdio@f3000 { +- status = "disabled"; +- +- xfiphy4: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x0>; +- }; +- }; +- +- mdio@fd000 { +- xauiphy1: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x0>; +- }; +- +- xauiphy2: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x1>; +- }; +- +- xauiphy3: ethernet-phy@2 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x2>; +- }; +- +- xauiphy4: ethernet-phy@3 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x3>; +- }; +- }; +- }; +- }; +- +- pci0: pcie@ffe240000 { +- reg = <0xf 0xfe240000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci1: pcie@ffe250000 { +- reg = <0xf 0xfe250000 0 0x10000>; +- ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 +- 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci2: pcie@ffe260000 { +- reg = <0xf 0xfe260000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci3: pcie@ffe270000 { +- reg = <0xf 0xfe270000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- rio: rapidio@ffe0c0000 { +- reg = <0xf 0xfe0c0000 0 0x11000>; +- +- port1 { +- ranges = <0 0 0xc 0x20000000 0 0x10000000>; +- }; +- port2 { +- ranges = <0 0 0xc 0x30000000 0 0x10000000>; +- }; +- }; +-}; +- +-/include/ "t4240si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t4240rdb.dts b/scripts/dtc/include-prefixes/powerpc/fsl/t4240rdb.dts +deleted file mode 100644 +index 145896f2eef6..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t4240rdb.dts ++++ /dev/null +@@ -1,363 +0,0 @@ +-/* +- * T4240RDB Device Tree Source +- * +- * Copyright 2014 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/include/ "t4240si-pre.dtsi" +- +-/ { +- model = "fsl,T4240RDB"; +- compatible = "fsl,T4240RDB"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- sgmii_phy21 = &sgmiiphy21; +- sgmii_phy22 = &sgmiiphy22; +- sgmii_phy23 = &sgmiiphy23; +- sgmii_phy24 = &sgmiiphy24; +- sgmii_phy41 = &sgmiiphy41; +- sgmii_phy42 = &sgmiiphy42; +- sgmii_phy43 = &sgmiiphy43; +- sgmii_phy44 = &sgmiiphy44; +- }; +- +- ifc: localbus@ffe124000 { +- reg = <0xf 0xfe124000 0 0x2000>; +- ranges = <0 0 0xf 0xe8000000 0x08000000 +- 2 0 0xf 0xff800000 0x00010000 +- 3 0 0xf 0xffdf0000 0x00008000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x8000000>; +- +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,ifc-nand"; +- reg = <0x2 0x0 0x10000>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- bman_fbpr: bman-fbpr { +- size = <0 0x1000000>; +- alignment = <0 0x1000000>; +- }; +- qman_fqd: qman-fqd { +- size = <0 0x400000>; +- alignment = <0 0x400000>; +- }; +- qman_pfdr: qman-pfdr { +- size = <0 0x2000000>; +- alignment = <0 0x2000000>; +- }; +- }; +- +- dcsr: dcsr@f00000000 { +- ranges = <0x00000000 0xf 0x00000000 0x01072000>; +- }; +- +- bportals: bman-portals@ff4000000 { +- ranges = <0x0 0xf 0xf4000000 0x2000000>; +- }; +- +- qportals: qman-portals@ff6000000 { +- ranges = <0x0 0xf 0xf6000000 0x2000000>; +- }; +- +- soc: soc@ffe000000 { +- ranges = <0x00000000 0xf 0xfe000000 0x1000000>; +- reg = <0xf 0xfe000000 0 0x00001000>; +- spi@110000 { +- flash@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "sst,sst25wf040", "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; /* input clock */ +- }; +- }; +- +- i2c@118000 { +- hwmon@2f { +- compatible = "winbond,w83793"; +- reg = <0x2f>; +- }; +- eeprom@52 { +- compatible = "atmel,24c256"; +- reg = <0x52>; +- }; +- eeprom@54 { +- compatible = "atmel,24c256"; +- reg = <0x54>; +- }; +- eeprom@56 { +- compatible = "atmel,24c256"; +- reg = <0x56>; +- }; +- rtc@68 { +- compatible = "dallas,ds1374"; +- reg = <0x68>; +- }; +- }; +- +- sdhc@114000 { +- voltage-ranges = <1800 1800 3300 3300>; +- }; +- +- fman@400000 { +- ethernet@e0000 { +- phy-handle = <&sgmiiphy21>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e2000 { +- phy-handle = <&sgmiiphy22>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e4000 { +- phy-handle = <&sgmiiphy23>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e6000 { +- phy-handle = <&sgmiiphy24>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e8000 { +- status = "disabled"; +- }; +- +- ethernet@ea000 { +- status = "disabled"; +- }; +- +- ethernet@f0000 { +- phy-handle = <&xfiphy1>; +- phy-connection-type = "xgmii"; +- }; +- +- ethernet@f2000 { +- phy-handle = <&xfiphy2>; +- phy-connection-type = "xgmii"; +- }; +- }; +- +- fman@500000 { +- ethernet@e0000 { +- phy-handle = <&sgmiiphy41>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e2000 { +- phy-handle = <&sgmiiphy42>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e4000 { +- phy-handle = <&sgmiiphy43>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e6000 { +- phy-handle = <&sgmiiphy44>; +- phy-connection-type = "sgmii"; +- }; +- +- ethernet@e8000 { +- status = "disabled"; +- }; +- +- ethernet@ea000 { +- status = "disabled"; +- }; +- +- ethernet@f0000 { +- phy-handle = <&xfiphy3>; +- phy-connection-type = "xgmii"; +- }; +- +- ethernet@f2000 { +- phy-handle = <&xfiphy4>; +- phy-connection-type = "xgmii"; +- }; +- +- mdio@fc000 { +- sgmiiphy21: ethernet-phy@0 { +- reg = <0x0>; +- }; +- +- sgmiiphy22: ethernet-phy@1 { +- reg = <0x1>; +- }; +- +- sgmiiphy23: ethernet-phy@2 { +- reg = <0x2>; +- }; +- +- sgmiiphy24: ethernet-phy@3 { +- reg = <0x3>; +- }; +- +- sgmiiphy41: ethernet-phy@4 { +- reg = <0x4>; +- }; +- +- sgmiiphy42: ethernet-phy@5 { +- reg = <0x5>; +- }; +- +- sgmiiphy43: ethernet-phy@6 { +- reg = <0x6>; +- }; +- +- sgmiiphy44: ethernet-phy@7 { +- reg = <0x7>; +- }; +- }; +- +- mdio@fd000 { +- xfiphy1: ethernet-phy@10 { +- compatible = "ethernet-phy-id13e5.1002"; +- reg = <0x10>; +- }; +- +- xfiphy2: ethernet-phy@11 { +- compatible = "ethernet-phy-id13e5.1002"; +- reg = <0x11>; +- }; +- +- xfiphy3: ethernet-phy@13 { +- compatible = "ethernet-phy-id13e5.1002"; +- reg = <0x13>; +- }; +- +- xfiphy4: ethernet-phy@12 { +- compatible = "ethernet-phy-id13e5.1002"; +- reg = <0x12>; +- }; +- }; +- }; +- }; +- +- pci0: pcie@ffe240000 { +- reg = <0xf 0xfe240000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci1: pcie@ffe250000 { +- reg = <0xf 0xfe250000 0 0x10000>; +- ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 +- 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci2: pcie@ffe260000 { +- reg = <0xf 0xfe260000 0 0x1000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- pci3: pcie@ffe270000 { +- reg = <0xf 0xfe270000 0 0x10000>; +- ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; +- pcie@0 { +- ranges = <0x02000000 0 0xe0000000 +- 0x02000000 0 0xe0000000 +- 0 0x20000000 +- +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00010000>; +- }; +- }; +- +- rio: rapidio@ffe0c0000 { +- reg = <0xf 0xfe0c0000 0 0x11000>; +- +- port1 { +- ranges = <0 0 0xc 0x20000000 0 0x10000000>; +- }; +- port2 { +- ranges = <0 0 0xc 0x30000000 0 0x10000000>; +- }; +- }; +-}; +- +-/include/ "t4240si-post.dtsi" +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t4240si-post.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/t4240si-post.dtsi +deleted file mode 100644 +index fcac73486d48..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t4240si-post.dtsi ++++ /dev/null +@@ -1,1111 +0,0 @@ +-/* +- * T4240 Silicon/SoC Device Tree Source (post include) +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-&bman_fbpr { +- compatible = "fsl,bman-fbpr"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&qman_fqd { +- compatible = "fsl,qman-fqd"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&qman_pfdr { +- compatible = "fsl,qman-pfdr"; +- alloc-ranges = <0 0 0x10000 0>; +-}; +- +-&ifc { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,ifc", "simple-bus"; +- interrupts = <25 2 0 0>; +-}; +- +-/* controller at 0x240000 */ +-&pci0 { +- compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- interrupts = <20 2 0 0>; +- pcie@0 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- reg = <0 0 0 0 0>; +- interrupts = <20 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 40 1 0 0 +- 0000 0 0 2 &mpic 1 1 0 0 +- 0000 0 0 3 &mpic 2 1 0 0 +- 0000 0 0 4 &mpic 3 1 0 0 +- >; +- }; +-}; +- +-/* controller at 0x250000 */ +-&pci1 { +- compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0 0xff>; +- interrupts = <21 2 0 0>; +- pcie@0 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- reg = <0 0 0 0 0>; +- interrupts = <21 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 41 1 0 0 +- 0000 0 0 2 &mpic 5 1 0 0 +- 0000 0 0 3 &mpic 6 1 0 0 +- 0000 0 0 4 &mpic 7 1 0 0 +- >; +- }; +-}; +- +-/* controller at 0x260000 */ +-&pci2 { +- compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- interrupts = <22 2 0 0>; +- pcie@0 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- reg = <0 0 0 0 0>; +- interrupts = <22 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 42 1 0 0 +- 0000 0 0 2 &mpic 9 1 0 0 +- 0000 0 0 3 &mpic 10 1 0 0 +- 0000 0 0 4 &mpic 11 1 0 0 +- >; +- }; +-}; +- +-/* controller at 0x270000 */ +-&pci3 { +- compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; +- device_type = "pci"; +- #size-cells = <2>; +- #address-cells = <3>; +- bus-range = <0x0 0xff>; +- interrupts = <23 2 0 0>; +- pcie@0 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- reg = <0 0 0 0 0>; +- interrupts = <23 2 0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0000 0 0 1 &mpic 43 1 0 0 +- 0000 0 0 2 &mpic 0 1 0 0 +- 0000 0 0 3 &mpic 4 1 0 0 +- 0000 0 0 4 &mpic 8 1 0 0 +- >; +- }; +-}; +- +-&rio { +- compatible = "fsl,srio"; +- interrupts = <16 2 1 11>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- port1 { +- #address-cells = <2>; +- #size-cells = <2>; +- cell-index = <1>; +- }; +- +- port2 { +- #address-cells = <2>; +- #size-cells = <2>; +- cell-index = <2>; +- }; +-}; +- +-&dcsr { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,dcsr", "simple-bus"; +- +- dcsr-epu@0 { +- compatible = "fsl,t4240-dcsr-epu", "fsl,dcsr-epu"; +- interrupts = <52 2 0 0 +- 84 2 0 0 +- 85 2 0 0 +- 94 2 0 0 +- 95 2 0 0>; +- reg = <0x0 0x1000>; +- }; +- dcsr-npc { +- compatible = "fsl,t4240-dcsr-cnpc", "fsl,dcsr-cnpc"; +- reg = <0x1000 0x1000 0x1002000 0x10000>; +- }; +- dcsr-nxc@2000 { +- compatible = "fsl,dcsr-nxc"; +- reg = <0x2000 0x1000>; +- }; +- dcsr-corenet { +- compatible = "fsl,dcsr-corenet"; +- reg = <0x8000 0x1000 0x1A000 0x1000>; +- }; +- dcsr-dpaa@9000 { +- compatible = "fsl,t4240-dcsr-dpaa", "fsl,dcsr-dpaa"; +- reg = <0x9000 0x1000>; +- }; +- dcsr-ocn@11000 { +- compatible = "fsl,t4240-dcsr-ocn", "fsl,dcsr-ocn"; +- reg = <0x11000 0x1000>; +- }; +- dcsr-ddr@12000 { +- compatible = "fsl,dcsr-ddr"; +- dev-handle = <&ddr1>; +- reg = <0x12000 0x1000>; +- }; +- dcsr-ddr@13000 { +- compatible = "fsl,dcsr-ddr"; +- dev-handle = <&ddr2>; +- reg = <0x13000 0x1000>; +- }; +- dcsr-ddr@14000 { +- compatible = "fsl,dcsr-ddr"; +- dev-handle = <&ddr3>; +- reg = <0x14000 0x1000>; +- }; +- dcsr-nal@18000 { +- compatible = "fsl,t4240-dcsr-nal", "fsl,dcsr-nal"; +- reg = <0x18000 0x1000>; +- }; +- dcsr-rcpm@22000 { +- compatible = "fsl,t4240-dcsr-rcpm", "fsl,dcsr-rcpm"; +- reg = <0x22000 0x1000>; +- }; +- dcsr-snpc@30000 { +- compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc"; +- reg = <0x30000 0x1000 0x1022000 0x10000>; +- }; +- dcsr-snpc@31000 { +- compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc"; +- reg = <0x31000 0x1000 0x1042000 0x10000>; +- }; +- dcsr-snpc@32000 { +- compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc"; +- reg = <0x32000 0x1000 0x1062000 0x10000>; +- }; +- dcsr-cpu-sb-proxy@100000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu0>; +- reg = <0x100000 0x1000 0x101000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@108000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu1>; +- reg = <0x108000 0x1000 0x109000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@110000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu2>; +- reg = <0x110000 0x1000 0x111000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@118000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu3>; +- reg = <0x118000 0x1000 0x119000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@120000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu4>; +- reg = <0x120000 0x1000 0x121000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@128000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu5>; +- reg = <0x128000 0x1000 0x129000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@130000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu6>; +- reg = <0x130000 0x1000 0x131000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@138000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu7>; +- reg = <0x138000 0x1000 0x139000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@140000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu8>; +- reg = <0x140000 0x1000 0x141000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@148000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu9>; +- reg = <0x148000 0x1000 0x149000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@150000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu10>; +- reg = <0x150000 0x1000 0x151000 0x1000>; +- }; +- dcsr-cpu-sb-proxy@158000 { +- compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; +- cpu-handle = <&cpu11>; +- reg = <0x158000 0x1000 0x159000 0x1000>; +- }; +-}; +- +-&bportals { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- compatible = "simple-bus"; +- +- bman-portal@0 { +- compatible = "fsl,bman-portal"; +- reg = <0x0 0x4000>, <0x1000000 0x1000>; +- interrupts = <105 2 0 0>; +- }; +- bman-portal@4000 { +- compatible = "fsl,bman-portal"; +- reg = <0x4000 0x4000>, <0x1001000 0x1000>; +- interrupts = <107 2 0 0>; +- }; +- bman-portal@8000 { +- compatible = "fsl,bman-portal"; +- reg = <0x8000 0x4000>, <0x1002000 0x1000>; +- interrupts = <109 2 0 0>; +- }; +- bman-portal@c000 { +- compatible = "fsl,bman-portal"; +- reg = <0xc000 0x4000>, <0x1003000 0x1000>; +- interrupts = <111 2 0 0>; +- }; +- bman-portal@10000 { +- compatible = "fsl,bman-portal"; +- reg = <0x10000 0x4000>, <0x1004000 0x1000>; +- interrupts = <113 2 0 0>; +- }; +- bman-portal@14000 { +- compatible = "fsl,bman-portal"; +- reg = <0x14000 0x4000>, <0x1005000 0x1000>; +- interrupts = <115 2 0 0>; +- }; +- bman-portal@18000 { +- compatible = "fsl,bman-portal"; +- reg = <0x18000 0x4000>, <0x1006000 0x1000>; +- interrupts = <117 2 0 0>; +- }; +- bman-portal@1c000 { +- compatible = "fsl,bman-portal"; +- reg = <0x1c000 0x4000>, <0x1007000 0x1000>; +- interrupts = <119 2 0 0>; +- }; +- bman-portal@20000 { +- compatible = "fsl,bman-portal"; +- reg = <0x20000 0x4000>, <0x1008000 0x1000>; +- interrupts = <121 2 0 0>; +- }; +- bman-portal@24000 { +- compatible = "fsl,bman-portal"; +- reg = <0x24000 0x4000>, <0x1009000 0x1000>; +- interrupts = <123 2 0 0>; +- }; +- bman-portal@28000 { +- compatible = "fsl,bman-portal"; +- reg = <0x28000 0x4000>, <0x100a000 0x1000>; +- interrupts = <125 2 0 0>; +- }; +- bman-portal@2c000 { +- compatible = "fsl,bman-portal"; +- reg = <0x2c000 0x4000>, <0x100b000 0x1000>; +- interrupts = <127 2 0 0>; +- }; +- bman-portal@30000 { +- compatible = "fsl,bman-portal"; +- reg = <0x30000 0x4000>, <0x100c000 0x1000>; +- interrupts = <129 2 0 0>; +- }; +- bman-portal@34000 { +- compatible = "fsl,bman-portal"; +- reg = <0x34000 0x4000>, <0x100d000 0x1000>; +- interrupts = <131 2 0 0>; +- }; +- bman-portal@38000 { +- compatible = "fsl,bman-portal"; +- reg = <0x38000 0x4000>, <0x100e000 0x1000>; +- interrupts = <133 2 0 0>; +- }; +- bman-portal@3c000 { +- compatible = "fsl,bman-portal"; +- reg = <0x3c000 0x4000>, <0x100f000 0x1000>; +- interrupts = <135 2 0 0>; +- }; +- bman-portal@40000 { +- compatible = "fsl,bman-portal"; +- reg = <0x40000 0x4000>, <0x1010000 0x1000>; +- interrupts = <137 2 0 0>; +- }; +- bman-portal@44000 { +- compatible = "fsl,bman-portal"; +- reg = <0x44000 0x4000>, <0x1011000 0x1000>; +- interrupts = <139 2 0 0>; +- }; +- bman-portal@48000 { +- compatible = "fsl,bman-portal"; +- reg = <0x48000 0x4000>, <0x1012000 0x1000>; +- interrupts = <141 2 0 0>; +- }; +- bman-portal@4c000 { +- compatible = "fsl,bman-portal"; +- reg = <0x4c000 0x4000>, <0x1013000 0x1000>; +- interrupts = <143 2 0 0>; +- }; +- bman-portal@50000 { +- compatible = "fsl,bman-portal"; +- reg = <0x50000 0x4000>, <0x1014000 0x1000>; +- interrupts = <145 2 0 0>; +- }; +- bman-portal@54000 { +- compatible = "fsl,bman-portal"; +- reg = <0x54000 0x4000>, <0x1015000 0x1000>; +- interrupts = <147 2 0 0>; +- }; +- bman-portal@58000 { +- compatible = "fsl,bman-portal"; +- reg = <0x58000 0x4000>, <0x1016000 0x1000>; +- interrupts = <149 2 0 0>; +- }; +- bman-portal@5c000 { +- compatible = "fsl,bman-portal"; +- reg = <0x5c000 0x4000>, <0x1017000 0x1000>; +- interrupts = <151 2 0 0>; +- }; +- bman-portal@60000 { +- compatible = "fsl,bman-portal"; +- reg = <0x60000 0x4000>, <0x1018000 0x1000>; +- interrupts = <153 2 0 0>; +- }; +- bman-portal@64000 { +- compatible = "fsl,bman-portal"; +- reg = <0x64000 0x4000>, <0x1019000 0x1000>; +- interrupts = <155 2 0 0>; +- }; +- bman-portal@68000 { +- compatible = "fsl,bman-portal"; +- reg = <0x68000 0x4000>, <0x101a000 0x1000>; +- interrupts = <157 2 0 0>; +- }; +- bman-portal@6c000 { +- compatible = "fsl,bman-portal"; +- reg = <0x6c000 0x4000>, <0x101b000 0x1000>; +- interrupts = <159 2 0 0>; +- }; +- bman-portal@70000 { +- compatible = "fsl,bman-portal"; +- reg = <0x70000 0x4000>, <0x101c000 0x1000>; +- interrupts = <161 2 0 0>; +- }; +- bman-portal@74000 { +- compatible = "fsl,bman-portal"; +- reg = <0x74000 0x4000>, <0x101d000 0x1000>; +- interrupts = <163 2 0 0>; +- }; +- bman-portal@78000 { +- compatible = "fsl,bman-portal"; +- reg = <0x78000 0x4000>, <0x101e000 0x1000>; +- interrupts = <165 2 0 0>; +- }; +- bman-portal@7c000 { +- compatible = "fsl,bman-portal"; +- reg = <0x7c000 0x4000>, <0x101f000 0x1000>; +- interrupts = <167 2 0 0>; +- }; +- bman-portal@80000 { +- compatible = "fsl,bman-portal"; +- reg = <0x80000 0x4000>, <0x1020000 0x1000>; +- interrupts = <169 2 0 0>; +- }; +- bman-portal@84000 { +- compatible = "fsl,bman-portal"; +- reg = <0x84000 0x4000>, <0x1021000 0x1000>; +- interrupts = <171 2 0 0>; +- }; +- bman-portal@88000 { +- compatible = "fsl,bman-portal"; +- reg = <0x88000 0x4000>, <0x1022000 0x1000>; +- interrupts = <173 2 0 0>; +- }; +- bman-portal@8c000 { +- compatible = "fsl,bman-portal"; +- reg = <0x8c000 0x4000>, <0x1023000 0x1000>; +- interrupts = <175 2 0 0>; +- }; +- bman-portal@90000 { +- compatible = "fsl,bman-portal"; +- reg = <0x90000 0x4000>, <0x1024000 0x1000>; +- interrupts = <385 2 0 0>; +- }; +- bman-portal@94000 { +- compatible = "fsl,bman-portal"; +- reg = <0x94000 0x4000>, <0x1025000 0x1000>; +- interrupts = <387 2 0 0>; +- }; +- bman-portal@98000 { +- compatible = "fsl,bman-portal"; +- reg = <0x98000 0x4000>, <0x1026000 0x1000>; +- interrupts = <389 2 0 0>; +- }; +- bman-portal@9c000 { +- compatible = "fsl,bman-portal"; +- reg = <0x9c000 0x4000>, <0x1027000 0x1000>; +- interrupts = <391 2 0 0>; +- }; +- bman-portal@a0000 { +- compatible = "fsl,bman-portal"; +- reg = <0xa0000 0x4000>, <0x1028000 0x1000>; +- interrupts = <393 2 0 0>; +- }; +- bman-portal@a4000 { +- compatible = "fsl,bman-portal"; +- reg = <0xa4000 0x4000>, <0x1029000 0x1000>; +- interrupts = <395 2 0 0>; +- }; +- bman-portal@a8000 { +- compatible = "fsl,bman-portal"; +- reg = <0xa8000 0x4000>, <0x102a000 0x1000>; +- interrupts = <397 2 0 0>; +- }; +- bman-portal@ac000 { +- compatible = "fsl,bman-portal"; +- reg = <0xac000 0x4000>, <0x102b000 0x1000>; +- interrupts = <399 2 0 0>; +- }; +- bman-portal@b0000 { +- compatible = "fsl,bman-portal"; +- reg = <0xb0000 0x4000>, <0x102c000 0x1000>; +- interrupts = <401 2 0 0>; +- }; +- bman-portal@b4000 { +- compatible = "fsl,bman-portal"; +- reg = <0xb4000 0x4000>, <0x102d000 0x1000>; +- interrupts = <403 2 0 0>; +- }; +- bman-portal@b8000 { +- compatible = "fsl,bman-portal"; +- reg = <0xb8000 0x4000>, <0x102e000 0x1000>; +- interrupts = <405 2 0 0>; +- }; +- bman-portal@bc000 { +- compatible = "fsl,bman-portal"; +- reg = <0xbc000 0x4000>, <0x102f000 0x1000>; +- interrupts = <407 2 0 0>; +- }; +- bman-portal@c0000 { +- compatible = "fsl,bman-portal"; +- reg = <0xc0000 0x4000>, <0x1030000 0x1000>; +- interrupts = <409 2 0 0>; +- }; +- bman-portal@c4000 { +- compatible = "fsl,bman-portal"; +- reg = <0xc4000 0x4000>, <0x1031000 0x1000>; +- interrupts = <411 2 0 0>; +- }; +-}; +- +-&qportals { +- #address-cells = <0x1>; +- #size-cells = <0x1>; +- compatible = "simple-bus"; +- +- qportal0: qman-portal@0 { +- compatible = "fsl,qman-portal"; +- reg = <0x0 0x4000>, <0x1000000 0x1000>; +- interrupts = <104 0x2 0 0>; +- cell-index = <0x0>; +- }; +- qportal1: qman-portal@4000 { +- compatible = "fsl,qman-portal"; +- reg = <0x4000 0x4000>, <0x1001000 0x1000>; +- interrupts = <106 0x2 0 0>; +- cell-index = <0x1>; +- }; +- qportal2: qman-portal@8000 { +- compatible = "fsl,qman-portal"; +- reg = <0x8000 0x4000>, <0x1002000 0x1000>; +- interrupts = <108 0x2 0 0>; +- cell-index = <0x2>; +- }; +- qportal3: qman-portal@c000 { +- compatible = "fsl,qman-portal"; +- reg = <0xc000 0x4000>, <0x1003000 0x1000>; +- interrupts = <110 0x2 0 0>; +- cell-index = <0x3>; +- }; +- qportal4: qman-portal@10000 { +- compatible = "fsl,qman-portal"; +- reg = <0x10000 0x4000>, <0x1004000 0x1000>; +- interrupts = <112 0x2 0 0>; +- cell-index = <0x4>; +- }; +- qportal5: qman-portal@14000 { +- compatible = "fsl,qman-portal"; +- reg = <0x14000 0x4000>, <0x1005000 0x1000>; +- interrupts = <114 0x2 0 0>; +- cell-index = <0x5>; +- }; +- qportal6: qman-portal@18000 { +- compatible = "fsl,qman-portal"; +- reg = <0x18000 0x4000>, <0x1006000 0x1000>; +- interrupts = <116 0x2 0 0>; +- cell-index = <0x6>; +- }; +- qportal7: qman-portal@1c000 { +- compatible = "fsl,qman-portal"; +- reg = <0x1c000 0x4000>, <0x1007000 0x1000>; +- interrupts = <118 0x2 0 0>; +- cell-index = <0x7>; +- }; +- qportal8: qman-portal@20000 { +- compatible = "fsl,qman-portal"; +- reg = <0x20000 0x4000>, <0x1008000 0x1000>; +- interrupts = <120 0x2 0 0>; +- cell-index = <0x8>; +- }; +- qportal9: qman-portal@24000 { +- compatible = "fsl,qman-portal"; +- reg = <0x24000 0x4000>, <0x1009000 0x1000>; +- interrupts = <122 0x2 0 0>; +- cell-index = <0x9>; +- }; +- qportal10: qman-portal@28000 { +- compatible = "fsl,qman-portal"; +- reg = <0x28000 0x4000>, <0x100a000 0x1000>; +- interrupts = <124 0x2 0 0>; +- cell-index = <0xa>; +- }; +- qportal11: qman-portal@2c000 { +- compatible = "fsl,qman-portal"; +- reg = <0x2c000 0x4000>, <0x100b000 0x1000>; +- interrupts = <126 0x2 0 0>; +- cell-index = <0xb>; +- }; +- qportal12: qman-portal@30000 { +- compatible = "fsl,qman-portal"; +- reg = <0x30000 0x4000>, <0x100c000 0x1000>; +- interrupts = <128 0x2 0 0>; +- cell-index = <0xc>; +- }; +- qportal13: qman-portal@34000 { +- compatible = "fsl,qman-portal"; +- reg = <0x34000 0x4000>, <0x100d000 0x1000>; +- interrupts = <130 0x2 0 0>; +- cell-index = <0xd>; +- }; +- qportal14: qman-portal@38000 { +- compatible = "fsl,qman-portal"; +- reg = <0x38000 0x4000>, <0x100e000 0x1000>; +- interrupts = <132 0x2 0 0>; +- cell-index = <0xe>; +- }; +- qportal15: qman-portal@3c000 { +- compatible = "fsl,qman-portal"; +- reg = <0x3c000 0x4000>, <0x100f000 0x1000>; +- interrupts = <134 0x2 0 0>; +- cell-index = <0xf>; +- }; +- qportal16: qman-portal@40000 { +- compatible = "fsl,qman-portal"; +- reg = <0x40000 0x4000>, <0x1010000 0x1000>; +- interrupts = <136 0x2 0 0>; +- cell-index = <0x10>; +- }; +- qportal17: qman-portal@44000 { +- compatible = "fsl,qman-portal"; +- reg = <0x44000 0x4000>, <0x1011000 0x1000>; +- interrupts = <138 0x2 0 0>; +- cell-index = <0x11>; +- }; +- qportal18: qman-portal@48000 { +- compatible = "fsl,qman-portal"; +- reg = <0x48000 0x4000>, <0x1012000 0x1000>; +- interrupts = <140 0x2 0 0>; +- cell-index = <0x12>; +- }; +- qportal19: qman-portal@4c000 { +- compatible = "fsl,qman-portal"; +- reg = <0x4c000 0x4000>, <0x1013000 0x1000>; +- interrupts = <142 0x2 0 0>; +- cell-index = <0x13>; +- }; +- qportal20: qman-portal@50000 { +- compatible = "fsl,qman-portal"; +- reg = <0x50000 0x4000>, <0x1014000 0x1000>; +- interrupts = <144 0x2 0 0>; +- cell-index = <0x14>; +- }; +- qportal21: qman-portal@54000 { +- compatible = "fsl,qman-portal"; +- reg = <0x54000 0x4000>, <0x1015000 0x1000>; +- interrupts = <146 0x2 0 0>; +- cell-index = <0x15>; +- }; +- qportal22: qman-portal@58000 { +- compatible = "fsl,qman-portal"; +- reg = <0x58000 0x4000>, <0x1016000 0x1000>; +- interrupts = <148 0x2 0 0>; +- cell-index = <0x16>; +- }; +- qportal23: qman-portal@5c000 { +- compatible = "fsl,qman-portal"; +- reg = <0x5c000 0x4000>, <0x1017000 0x1000>; +- interrupts = <150 0x2 0 0>; +- cell-index = <0x17>; +- }; +- qportal24: qman-portal@60000 { +- compatible = "fsl,qman-portal"; +- reg = <0x60000 0x4000>, <0x1018000 0x1000>; +- interrupts = <152 0x2 0 0>; +- cell-index = <0x18>; +- }; +- qportal25: qman-portal@64000 { +- compatible = "fsl,qman-portal"; +- reg = <0x64000 0x4000>, <0x1019000 0x1000>; +- interrupts = <154 0x2 0 0>; +- cell-index = <0x19>; +- }; +- qportal26: qman-portal@68000 { +- compatible = "fsl,qman-portal"; +- reg = <0x68000 0x4000>, <0x101a000 0x1000>; +- interrupts = <156 0x2 0 0>; +- cell-index = <0x1a>; +- }; +- qportal27: qman-portal@6c000 { +- compatible = "fsl,qman-portal"; +- reg = <0x6c000 0x4000>, <0x101b000 0x1000>; +- interrupts = <158 0x2 0 0>; +- cell-index = <0x1b>; +- }; +- qportal28: qman-portal@70000 { +- compatible = "fsl,qman-portal"; +- reg = <0x70000 0x4000>, <0x101c000 0x1000>; +- interrupts = <160 0x2 0 0>; +- cell-index = <0x1c>; +- }; +- qportal29: qman-portal@74000 { +- compatible = "fsl,qman-portal"; +- reg = <0x74000 0x4000>, <0x101d000 0x1000>; +- interrupts = <162 0x2 0 0>; +- cell-index = <0x1d>; +- }; +- qportal30: qman-portal@78000 { +- compatible = "fsl,qman-portal"; +- reg = <0x78000 0x4000>, <0x101e000 0x1000>; +- interrupts = <164 0x2 0 0>; +- cell-index = <0x1e>; +- }; +- qportal31: qman-portal@7c000 { +- compatible = "fsl,qman-portal"; +- reg = <0x7c000 0x4000>, <0x101f000 0x1000>; +- interrupts = <166 0x2 0 0>; +- cell-index = <0x1f>; +- }; +- qportal32: qman-portal@80000 { +- compatible = "fsl,qman-portal"; +- reg = <0x80000 0x4000>, <0x1020000 0x1000>; +- interrupts = <168 0x2 0 0>; +- cell-index = <0x20>; +- }; +- qportal33: qman-portal@84000 { +- compatible = "fsl,qman-portal"; +- reg = <0x84000 0x4000>, <0x1021000 0x1000>; +- interrupts = <170 0x2 0 0>; +- cell-index = <0x21>; +- }; +- qportal34: qman-portal@88000 { +- compatible = "fsl,qman-portal"; +- reg = <0x88000 0x4000>, <0x1022000 0x1000>; +- interrupts = <172 0x2 0 0>; +- cell-index = <0x22>; +- }; +- qportal35: qman-portal@8c000 { +- compatible = "fsl,qman-portal"; +- reg = <0x8c000 0x4000>, <0x1023000 0x1000>; +- interrupts = <174 0x2 0 0>; +- cell-index = <0x23>; +- }; +- qportal36: qman-portal@90000 { +- compatible = "fsl,qman-portal"; +- reg = <0x90000 0x4000>, <0x1024000 0x1000>; +- interrupts = <384 0x2 0 0>; +- cell-index = <0x24>; +- }; +- qportal37: qman-portal@94000 { +- compatible = "fsl,qman-portal"; +- reg = <0x94000 0x4000>, <0x1025000 0x1000>; +- interrupts = <386 0x2 0 0>; +- cell-index = <0x25>; +- }; +- qportal38: qman-portal@98000 { +- compatible = "fsl,qman-portal"; +- reg = <0x98000 0x4000>, <0x1026000 0x1000>; +- interrupts = <388 0x2 0 0>; +- cell-index = <0x26>; +- }; +- qportal39: qman-portal@9c000 { +- compatible = "fsl,qman-portal"; +- reg = <0x9c000 0x4000>, <0x1027000 0x1000>; +- interrupts = <390 0x2 0 0>; +- cell-index = <0x27>; +- }; +- qportal40: qman-portal@a0000 { +- compatible = "fsl,qman-portal"; +- reg = <0xa0000 0x4000>, <0x1028000 0x1000>; +- interrupts = <392 0x2 0 0>; +- cell-index = <0x28>; +- }; +- qportal41: qman-portal@a4000 { +- compatible = "fsl,qman-portal"; +- reg = <0xa4000 0x4000>, <0x1029000 0x1000>; +- interrupts = <394 0x2 0 0>; +- cell-index = <0x29>; +- }; +- qportal42: qman-portal@a8000 { +- compatible = "fsl,qman-portal"; +- reg = <0xa8000 0x4000>, <0x102a000 0x1000>; +- interrupts = <396 0x2 0 0>; +- cell-index = <0x2a>; +- }; +- qportal43: qman-portal@ac000 { +- compatible = "fsl,qman-portal"; +- reg = <0xac000 0x4000>, <0x102b000 0x1000>; +- interrupts = <398 0x2 0 0>; +- cell-index = <0x2b>; +- }; +- qportal44: qman-portal@b0000 { +- compatible = "fsl,qman-portal"; +- reg = <0xb0000 0x4000>, <0x102c000 0x1000>; +- interrupts = <400 0x2 0 0>; +- cell-index = <0x2c>; +- }; +- qportal45: qman-portal@b4000 { +- compatible = "fsl,qman-portal"; +- reg = <0xb4000 0x4000>, <0x102d000 0x1000>; +- interrupts = <402 0x2 0 0>; +- cell-index = <0x2d>; +- }; +- qportal46: qman-portal@b8000 { +- compatible = "fsl,qman-portal"; +- reg = <0xb8000 0x4000>, <0x102e000 0x1000>; +- interrupts = <404 0x2 0 0>; +- cell-index = <0x2e>; +- }; +- qportal47: qman-portal@bc000 { +- compatible = "fsl,qman-portal"; +- reg = <0xbc000 0x4000>, <0x102f000 0x1000>; +- interrupts = <406 0x2 0 0>; +- cell-index = <0x2f>; +- }; +- qportal48: qman-portal@c0000 { +- compatible = "fsl,qman-portal"; +- reg = <0xc0000 0x4000>, <0x1030000 0x1000>; +- interrupts = <408 0x2 0 0>; +- cell-index = <0x30>; +- }; +- qportal49: qman-portal@c4000 { +- compatible = "fsl,qman-portal"; +- reg = <0xc4000 0x4000>, <0x1031000 0x1000>; +- interrupts = <410 0x2 0 0>; +- cell-index = <0x31>; +- }; +-}; +- +-&soc { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- +- soc-sram-error { +- compatible = "fsl,soc-sram-error"; +- interrupts = <16 2 1 29>; +- }; +- +- corenet-law@0 { +- compatible = "fsl,corenet-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <32>; +- }; +- +- ddr1: memory-controller@8000 { +- compatible = "fsl,qoriq-memory-controller-v4.7", +- "fsl,qoriq-memory-controller"; +- reg = <0x8000 0x1000>; +- interrupts = <16 2 1 23>; +- }; +- +- ddr2: memory-controller@9000 { +- compatible = "fsl,qoriq-memory-controller-v4.7", +- "fsl,qoriq-memory-controller"; +- reg = <0x9000 0x1000>; +- interrupts = <16 2 1 22>; +- }; +- +- ddr3: memory-controller@a000 { +- compatible = "fsl,qoriq-memory-controller-v4.7", +- "fsl,qoriq-memory-controller"; +- reg = <0xa000 0x1000>; +- interrupts = <16 2 1 21>; +- }; +- +- cpc: l3-cache-controller@10000 { +- compatible = "fsl,t4240-l3-cache-controller", "cache"; +- reg = <0x10000 0x1000 +- 0x11000 0x1000 +- 0x12000 0x1000>; +- interrupts = <16 2 1 27 +- 16 2 1 26 +- 16 2 1 25>; +- }; +- +- corenet-cf@18000 { +- compatible = "fsl,corenet2-cf", "fsl,corenet-cf"; +- reg = <0x18000 0x1000>; +- interrupts = <16 2 1 31>; +- fsl,ccf-num-csdids = <32>; +- fsl,ccf-num-snoopids = <32>; +- }; +- +- iommu@20000 { +- compatible = "fsl,pamu-v1.0", "fsl,pamu"; +- reg = <0x20000 0x6000>; +- fsl,portid-mapping = <0x8000>; +- interrupts = < +- 24 2 0 0 +- 16 2 1 30>; +- }; +- +-/include/ "qoriq-mpic4.3.dtsi" +- +- guts: global-utilities@e0000 { +- compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0"; +- reg = <0xe0000 0xe00>; +- fsl,has-rstcr; +- fsl,liodn-bits = <12>; +- }; +- +-/include/ "qoriq-clockgen2.dtsi" +- global-utilities@e1000 { +- compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0"; +- }; +- +- rcpm: global-utilities@e2000 { +- compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0"; +- reg = <0xe2000 0x1000>; +- }; +- +- sfp: sfp@e8000 { +- compatible = "fsl,t4240-sfp"; +- reg = <0xe8000 0x1000>; +- }; +- +- serdes: serdes@ea000 { +- compatible = "fsl,t4240-serdes"; +- reg = <0xea000 0x4000>; +- }; +- +-/include/ "elo3-dma-0.dtsi" +-/include/ "elo3-dma-1.dtsi" +-/include/ "elo3-dma-2.dtsi" +- +-/include/ "qoriq-espi-0.dtsi" +- spi@110000 { +- fsl,espi-num-chipselects = <4>; +- }; +- +-/include/ "qoriq-esdhc-0.dtsi" +- sdhc@114000 { +- compatible = "fsl,t4240-esdhc", "fsl,esdhc"; +- sdhci,auto-cmd12; +- }; +-/include/ "qoriq-i2c-0.dtsi" +-/include/ "qoriq-i2c-1.dtsi" +-/include/ "qoriq-duart-0.dtsi" +-/include/ "qoriq-duart-1.dtsi" +-/include/ "qoriq-gpio-0.dtsi" +-/include/ "qoriq-gpio-1.dtsi" +-/include/ "qoriq-gpio-2.dtsi" +-/include/ "qoriq-gpio-3.dtsi" +-/include/ "qoriq-usb2-mph-0.dtsi" +- usb0: usb@210000 { +- compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph"; +- phy_type = "utmi"; +- port0; +- }; +-/include/ "qoriq-usb2-dr-0.dtsi" +- usb1: usb@211000 { +- compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; +- dr_mode = "host"; +- phy_type = "utmi"; +- }; +-/include/ "qoriq-sata2-0.dtsi" +-/include/ "qoriq-sata2-1.dtsi" +-/include/ "qoriq-sec5.0-0.dtsi" +-/include/ "qoriq-qman3.dtsi" +-/include/ "qoriq-bman1.dtsi" +- +-/include/ "qoriq-fman3-0.dtsi" +-/include/ "qoriq-fman3-0-1g-0.dtsi" +-/include/ "qoriq-fman3-0-1g-1.dtsi" +-/include/ "qoriq-fman3-0-1g-2.dtsi" +-/include/ "qoriq-fman3-0-1g-3.dtsi" +-/include/ "qoriq-fman3-0-1g-4.dtsi" +-/include/ "qoriq-fman3-0-1g-5.dtsi" +-/include/ "qoriq-fman3-0-10g-0.dtsi" +-/include/ "qoriq-fman3-0-10g-1.dtsi" +- fman@400000 { +- enet0: ethernet@e0000 { +- }; +- +- enet1: ethernet@e2000 { +- }; +- +- enet2: ethernet@e4000 { +- }; +- +- enet3: ethernet@e6000 { +- }; +- +- enet4: ethernet@e8000 { +- }; +- +- enet5: ethernet@ea000 { +- }; +- +- enet6: ethernet@f0000 { +- }; +- +- enet7: ethernet@f2000 { +- }; +- +- mdio@fc000 { +- status = "disabled"; +- }; +- +- mdio@fd000 { +- status = "disabled"; +- }; +- }; +- +-/include/ "qoriq-fman3-1.dtsi" +-/include/ "qoriq-fman3-1-1g-0.dtsi" +-/include/ "qoriq-fman3-1-1g-1.dtsi" +-/include/ "qoriq-fman3-1-1g-2.dtsi" +-/include/ "qoriq-fman3-1-1g-3.dtsi" +-/include/ "qoriq-fman3-1-1g-4.dtsi" +-/include/ "qoriq-fman3-1-1g-5.dtsi" +-/include/ "qoriq-fman3-1-10g-0.dtsi" +-/include/ "qoriq-fman3-1-10g-1.dtsi" +- fman@500000 { +- enet8: ethernet@e0000 { +- }; +- +- enet9: ethernet@e2000 { +- }; +- +- enet10: ethernet@e4000 { +- }; +- +- enet11: ethernet@e6000 { +- }; +- +- enet12: ethernet@e8000 { +- }; +- +- enet13: ethernet@ea000 { +- }; +- +- enet14: ethernet@f0000 { +- }; +- +- enet15: ethernet@f2000 { +- }; +- +- mdio@fc000 { +- interrupts = <100 1 0 0>; +- }; +- +- mdio@fd000 { +- interrupts = <101 1 0 0>; +- }; +- }; +- +- L2_1: l2-cache-controller@c20000 { +- compatible = "fsl,t4240-l2-cache-controller"; +- reg = <0xc20000 0x40000>; +- next-level-cache = <&cpc>; +- }; +- L2_2: l2-cache-controller@c60000 { +- compatible = "fsl,t4240-l2-cache-controller"; +- reg = <0xc60000 0x40000>; +- next-level-cache = <&cpc>; +- }; +- L2_3: l2-cache-controller@ca0000 { +- compatible = "fsl,t4240-l2-cache-controller"; +- reg = <0xca0000 0x40000>; +- next-level-cache = <&cpc>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsl/t4240si-pre.dtsi b/scripts/dtc/include-prefixes/powerpc/fsl/t4240si-pre.dtsi +deleted file mode 100644 +index 632314c6faa9..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsl/t4240si-pre.dtsi ++++ /dev/null +@@ -1,175 +0,0 @@ +-/* +- * T4240 Silicon/SoC Device Tree Source (pre include) +- * +- * Copyright 2012 - 2015 Freescale Semiconductor Inc. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions are met: +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * * Neither the name of Freescale Semiconductor nor the +- * names of its contributors may be used to endorse or promote products +- * derived from this software without specific prior written permission. +- * +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") as published by the Free Software +- * Foundation, either version 2 of that License or (at your option) any +- * later version. +- * +- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY +- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY +- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-/include/ "e6500_power_isa.dtsi" +- +-/ { +- compatible = "fsl,T4240"; +- #address-cells = <2>; +- #size-cells = <2>; +- interrupt-parent = <&mpic>; +- +- aliases { +- ccsr = &soc; +- dcsr = &dcsr; +- +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- crypto = &crypto; +- +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- pci3 = &pci3; +- usb0 = &usb0; +- usb1 = &usb1; +- dma0 = &dma0; +- dma1 = &dma1; +- dma2 = &dma2; +- sdhc = &sdhc; +- +- fman0 = &fman0; +- fman1 = &fman1; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- ethernet4 = &enet4; +- ethernet5 = &enet5; +- ethernet6 = &enet6; +- ethernet7 = &enet7; +- ethernet8 = &enet8; +- ethernet9 = &enet9; +- ethernet10 = &enet10; +- ethernet11 = &enet11; +- ethernet12 = &enet12; +- ethernet13 = &enet13; +- ethernet14 = &enet14; +- ethernet15 = &enet15; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: PowerPC,e6500@0 { +- device_type = "cpu"; +- reg = <0 1>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_1>; +- fsl,portid-mapping = <0x80000000>; +- }; +- cpu1: PowerPC,e6500@2 { +- device_type = "cpu"; +- reg = <2 3>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_1>; +- fsl,portid-mapping = <0x80000000>; +- }; +- cpu2: PowerPC,e6500@4 { +- device_type = "cpu"; +- reg = <4 5>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_1>; +- fsl,portid-mapping = <0x80000000>; +- }; +- cpu3: PowerPC,e6500@6 { +- device_type = "cpu"; +- reg = <6 7>; +- clocks = <&clockgen 1 0>; +- next-level-cache = <&L2_1>; +- fsl,portid-mapping = <0x80000000>; +- }; +- cpu4: PowerPC,e6500@8 { +- device_type = "cpu"; +- reg = <8 9>; +- clocks = <&clockgen 1 1>; +- next-level-cache = <&L2_2>; +- fsl,portid-mapping = <0x40000000>; +- }; +- cpu5: PowerPC,e6500@10 { +- device_type = "cpu"; +- reg = <10 11>; +- clocks = <&clockgen 1 1>; +- next-level-cache = <&L2_2>; +- fsl,portid-mapping = <0x40000000>; +- }; +- cpu6: PowerPC,e6500@12 { +- device_type = "cpu"; +- reg = <12 13>; +- clocks = <&clockgen 1 1>; +- next-level-cache = <&L2_2>; +- fsl,portid-mapping = <0x40000000>; +- }; +- cpu7: PowerPC,e6500@14 { +- device_type = "cpu"; +- reg = <14 15>; +- clocks = <&clockgen 1 1>; +- next-level-cache = <&L2_2>; +- fsl,portid-mapping = <0x40000000>; +- }; +- cpu8: PowerPC,e6500@16 { +- device_type = "cpu"; +- reg = <16 17>; +- clocks = <&clockgen 1 2>; +- next-level-cache = <&L2_3>; +- fsl,portid-mapping = <0x20000000>; +- }; +- cpu9: PowerPC,e6500@18 { +- device_type = "cpu"; +- reg = <18 19>; +- clocks = <&clockgen 1 2>; +- next-level-cache = <&L2_3>; +- fsl,portid-mapping = <0x20000000>; +- }; +- cpu10: PowerPC,e6500@20 { +- device_type = "cpu"; +- reg = <20 21>; +- clocks = <&clockgen 1 2>; +- next-level-cache = <&L2_3>; +- fsl,portid-mapping = <0x20000000>; +- }; +- cpu11: PowerPC,e6500@22 { +- device_type = "cpu"; +- reg = <22 23>; +- clocks = <&clockgen 1 2>; +- next-level-cache = <&L2_3>; +- fsl,portid-mapping = <0x20000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/fsp2.dts b/scripts/dtc/include-prefixes/powerpc/fsp2.dts +deleted file mode 100644 +index 9311b86b1bd9..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/fsp2.dts ++++ /dev/null +@@ -1,613 +0,0 @@ +-/* +- * Device Tree Source for FSP2 +- * +- * Copyright 2010,2012 IBM Corp. +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +- +-/dts-v1/; +- +-/ { +- #address-cells = <2>; +- #size-cells = <1>; +- model = "ibm,fsp2"; +- compatible = "ibm,fsp2"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- ethernet1 = &EMAC1; +- serial0 = &UART0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC, 476FSP2"; +- reg = <0x0>; +- clock-frequency = <0>; /* Filled in by cuboot */ +- timebase-frequency = <0>; /* Filled in by cuboot */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by +- cuboot */ +- }; +- +- clocks { +- mmc_clk: mmc_clk { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <50000000>; +- clock-output-names = "mmc_clk"; +- }; +- }; +- +- UIC0: uic0 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x2c0 0x8>; +- }; +- +- /* "interrupts" field is +- first pair is non-critical, second is critical */ +- UIC1_0: uic1_0 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x2c8 0x8>; +- interrupt-parent = <&UIC0>; +- interrupts = <21 0x4 4 0x84>; +- }; +- +- /* PSI and DMA */ +- UIC1_1: uic1_1 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <2>; +- dcr-reg = <0x350 0x8>; +- interrupt-parent = <&UIC0>; +- interrupts = <22 0x4 5 0x84>; +- }; +- +- /* Ethernet and USB */ +- UIC1_2: uic1_2 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <3>; +- dcr-reg = <0x358 0x8>; +- interrupt-parent = <&UIC0>; +- interrupts = <23 0x4 6 0x84>; +- }; +- +- /* PLB Errors */ +- UIC1_3: uic1_3 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <4>; +- dcr-reg = <0x360 0x8>; +- interrupt-parent = <&UIC0>; +- interrupts = <24 0x4 7 0x84>; +- }; +- +- UIC1_4: uic1_4 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <5>; +- dcr-reg = <0x368 0x8>; +- interrupt-parent = <&UIC0>; +- interrupts = <25 0x4 8 0x84>; +- }; +- +- UIC1_5: uic1_5 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <6>; +- dcr-reg = <0x370 0x8>; +- interrupt-parent = <&UIC0>; +- interrupts = <26 0x4 9 0x84>; +- }; +- +- /* 2nd level UICs for FSI */ +- UIC2_0: uic2_0 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <7>; +- dcr-reg = <0x2d0 0x8>; +- interrupt-parent = <&UIC1_0>; +- interrupts = <16 0x4 0 0x84>; +- }; +- +- UIC2_1: uic2_1 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <8>; +- dcr-reg = <0x2d8 0x8>; +- interrupt-parent = <&UIC1_0>; +- interrupts = <17 0x4 1 0x84>; +- }; +- +- UIC2_2: uic2_2 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <9>; +- dcr-reg = <0x2e0 0x8>; +- interrupt-parent = <&UIC1_0>; +- interrupts = <18 0x4 2 0x84>; +- }; +- +- UIC2_3: uic2_3 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <10>; +- dcr-reg = <0x2e8 0x8>; +- interrupt-parent = <&UIC1_0>; +- interrupts = <19 0x4 3 0x84>; +- }; +- +- UIC2_4: uic2_4 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <11>; +- dcr-reg = <0x2f0 0x8>; +- interrupt-parent = <&UIC1_0>; +- interrupts = <20 0x4 4 0x84>; +- }; +- +- UIC2_5: uic2_5 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <12>; +- dcr-reg = <0x2f8 0x8>; +- interrupt-parent = <&UIC1_0>; +- interrupts = <21 0x4 5 0x84>; +- }; +- +- UIC2_6: uic2_6 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <13>; +- dcr-reg = <0x300 0x8>; +- interrupt-parent = <&UIC1_0>; +- interrupts = <22 0x4 6 0x84>; +- }; +- +- UIC2_7: uic2_7 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <14>; +- dcr-reg = <0x308 0x8>; +- interrupt-parent = <&UIC1_0>; +- interrupts = <23 0x4 7 0x84>; +- }; +- +- UIC2_8: uic2_8 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <15>; +- dcr-reg = <0x310 0x8>; +- interrupt-parent = <&UIC1_0>; +- interrupts = <24 0x4 8 0x84>; +- }; +- +- UIC2_9: uic2_9 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <16>; +- dcr-reg = <0x318 0x8>; +- interrupt-parent = <&UIC1_0>; +- interrupts = <25 0x4 9 0x84>; +- }; +- +- UIC2_10: uic2_10 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <17>; +- dcr-reg = <0x320 0x8>; +- interrupt-parent = <&UIC1_0>; +- interrupts = <26 0x4 10 0x84>; +- }; +- +- UIC2_11: uic2_11 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <18>; +- dcr-reg = <0x328 0x8>; +- interrupt-parent = <&UIC1_0>; +- interrupts = <27 0x4 11 0x84>; +- }; +- +- UIC2_12: uic2_12 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <19>; +- dcr-reg = <0x330 0x8>; +- interrupt-parent = <&UIC1_0>; +- interrupts = <28 0x4 12 0x84>; +- }; +- +- UIC2_13: uic2_13 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <20>; +- dcr-reg = <0x338 0x8>; +- interrupt-parent = <&UIC1_0>; +- interrupts = <29 0x4 13 0x84>; +- }; +- +- UIC2_14: uic2_14 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <21>; +- dcr-reg = <0x340 0x8>; +- interrupt-parent = <&UIC1_0>; +- interrupts = <30 0x4 14 0x84>; +- }; +- +- UIC2_15: uic2_15 { +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <22>; +- dcr-reg = <0x348 0x8>; +- interrupt-parent = <&UIC1_0>; +- interrupts = <31 0x4 15 0x84>; +- }; +- +- plb6 { +- compatible = "ibm,plb6"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- +- MCW0: memory-controller-wrapper { +- compatible = "ibm,cw-476fsp2"; +- dcr-reg = <0x11111800 0x40>; +- }; +- +- MCIF0: memory-controller { +- compatible = "ibm,sdram-476fsp2", "ibm,sdram-4xx-ddr3"; +- dcr-reg = <0x11120000 0x10000>; +- mcer-device = <&MCW0>; +- interrupt-parent = <&UIC0>; +- interrupts = <10 0x84 /* ECC UE */ +- 11 0x84>; /* ECC CE */ +- }; +- }; +- +- plb4 { +- compatible = "ibm,plb4"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000010 0x00000000 0x80000000 +- 0x80000000 0x00000010 0x80000000 0x80000000>; +- clock-frequency = <333333334>; +- +- plb6-system-hung-irq { +- compatible = "ibm,bus-error-irq"; +- #interrupt-cells = <2>; +- interrupt-parent = <&UIC0>; +- interrupts = <0 0x84>; +- }; +- +- l2-error-irq { +- compatible = "ibm,bus-error-irq"; +- #interrupt-cells = <2>; +- interrupt-parent = <&UIC0>; +- interrupts = <20 0x84>; +- }; +- +- plb6-plb4-irq { +- compatible = "ibm,bus-error-irq"; +- #interrupt-cells = <2>; +- interrupt-parent = <&UIC0>; +- interrupts = <1 0x84>; +- }; +- +- plb4-ahb-irq { +- compatible = "ibm,bus-error-irq"; +- #interrupt-cells = <2>; +- interrupt-parent = <&UIC1_3>; +- interrupts = <20 0x84>; +- }; +- +- opbd-error-irq { +- compatible = "ibm,opbd-error-irq"; +- #interrupt-cells = <2>; +- interrupt-parent = <&UIC1_4>; +- interrupts = <5 0x84>; +- }; +- +- cmu-error-irq { +- compatible = "ibm,cmu-error-irq"; +- #interrupt-cells = <2>; +- interrupt-parent = <&UIC0>; +- interrupts = <28 0x84>; +- }; +- +- conf-error-irq { +- compatible = "ibm,conf-error-irq"; +- #interrupt-cells = <2>; +- interrupt-parent = <&UIC1_4>; +- interrupts = <11 0x84>; +- }; +- +- mc-ue-irq { +- compatible = "ibm,mc-ue-irq"; +- #interrupt-cells = <2>; +- interrupt-parent = <&UIC0>; +- interrupts = <10 0x84>; +- }; +- +- reset-warning-irq { +- compatible = "ibm,reset-warning-irq"; +- #interrupt-cells = <2>; +- interrupt-parent = <&UIC0>; +- interrupts = <17 0x84>; +- }; +- +- MAL0: mcmal0 { +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- compatible = "ibm,mcmal"; +- dcr-reg = <0x80 0x80>; +- num-tx-chans = <1>; +- num-rx-chans = <1>; +- interrupt-parent = <&MAL0>; +- interrupts = <0 1 2 3 4>; +- /* index interrupt-parent interrupt# type */ +- interrupt-map = ; +- }; +- +- MAL1: mcmal1 { +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- compatible = "ibm,mcmal"; +- dcr-reg = <0x100 0x80>; +- num-tx-chans = <1>; +- num-rx-chans = <1>; +- interrupt-parent = <&MAL1>; +- interrupts = <0 1 2 3 4>; +- /* index interrupt-parent interrupt# type */ +- interrupt-map = ; +- }; +- +- mmc0: mmc@20c0000 { +- compatible = "st,sdhci-stih407", "st,sdhci"; +- reg = <0x020c0000 0x20000>; +- reg-names = "mmc"; +- interrupts = <21 0x4>; +- interrupt-parent = <&UIC1_3>; +- interrupt-names = "mmcirq"; +- pinctrl-names = "default"; +- pinctrl-0 = <>; +- clock-names = "mmc"; +- clocks = <&mmc_clk>; +- bus-width = <4>; +- non-removable; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- sd-uhs-ddr50; +- }; +- +- opb { +- compatible = "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; // pass-thru to parent bus +- clock-frequency = <83333334>; +- +- EMAC0: ethernet@b0000000 { +- linux,network-index = <0>; +- device_type = "network"; +- compatible = "ibm,emac4sync"; +- has-inverted-stacr-oc; +- interrupt-parent = <&UIC1_2>; +- interrupts = <1 0x4 0 0x4>; +- reg = <0xb0000000 0x100>; +- local-mac-address = [000000000000]; /* Filled in by +- cuboot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <1500>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <4096>; +- rx-fifo-size-gige = <16384>; +- tx-fifo-size-gige = <8192>; +- phy-address = <1>; +- phy-mode = "rgmii"; +- phy-map = <00000003>; +- rgmii-device = <&RGMII>; +- rgmii-channel = <0>; +- }; +- +- EMAC1: ethernet@b0000100 { +- linux,network-index = <1>; +- device_type = "network"; +- compatible = "ibm,emac4sync"; +- has-inverted-stacr-oc; +- interrupt-parent = <&UIC1_2>; +- interrupts = <9 0x4 8 0x4>; +- reg = <0xb0000100 0x100>; +- local-mac-address = [000000000000]; /* Filled in by +- cuboot */ +- mal-device = <&MAL1>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <1>; +- max-frame-size = <1500>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <4096>; +- rx-fifo-size-gige = <16384>; +- tx-fifo-size-gige = <8192>; +- phy-address = <2>; +- phy-mode = "rgmii"; +- phy-map = <00000003>; +- rgmii-device = <&RGMII>; +- rgmii-channel = <1>; +- }; +- +- RGMII: rgmii@b0000600 { +- compatible = "ibm,rgmii"; +- has-mdio; +- reg = <0xb0000600 0x8>; +- }; +- +- UART0: serial@b0020000 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xb0020000 0x8>; +- virtual-reg = <0xb0020000>; +- clock-frequency = <20833333>; +- current-speed = <115200>; +- interrupt-parent = <&UIC0>; +- interrupts = <31 0x4>; +- }; +- }; +- +- OHCI1: ohci@2040000 { +- compatible = "ohci-le"; +- reg = <0x02040000 0xa0>; +- interrupt-parent = <&UIC1_3>; +- interrupts = <28 0x8 29 0x8>; +- }; +- +- OHCI2: ohci@2080000 { +- compatible = "ohci-le"; +- reg = <0x02080000 0xa0>; +- interrupt-parent = <&UIC1_3>; +- interrupts = <30 0x8 31 0x8>; +- }; +- +- EHCI: ehci@2000000 { +- compatible = "usb-ehci"; +- reg = <0x02000000 0xa4>; +- interrupt-parent = <&UIC1_3>; +- interrupts = <23 0x4>; +- }; +- +- }; +- +- chosen { +- stdout-path = "/plb/opb/serial@b0020000"; +- bootargs = "console=ttyS0,115200 rw log_buf_len=32768 debug"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/gamecube.dts b/scripts/dtc/include-prefixes/powerpc/gamecube.dts +deleted file mode 100644 +index a564cb7cb1e3..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/gamecube.dts ++++ /dev/null +@@ -1,109 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * arch/powerpc/boot/dts/gamecube.dts +- * +- * Nintendo GameCube platform device tree source +- * Copyright (C) 2007-2009 The GameCube Linux Team +- * Copyright (C) 2007,2008,2009 Albert Herranz +- */ +- +-/dts-v1/; +- +-/ { +- model = "nintendo,gamecube"; +- compatible = "nintendo,gamecube"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- chosen { +- bootargs = "root=/dev/gcnsda2 rootwait udbg-immortal"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x01800000>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,gekko@0 { +- device_type = "cpu"; +- reg = <0>; +- clock-frequency = <486000000>; /* 486MHz */ +- bus-frequency = <162000000>; /* 162MHz core-to-bus 3x */ +- timebase-frequency = <40500000>; /* 162MHz / 4 */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- }; +- }; +- +- /* devices contained int the flipper chipset */ +- flipper { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "nintendo,flipper"; +- ranges = <0x0c000000 0x0c000000 0x00010000>; +- interrupt-parent = <&PIC>; +- +- video@c002000 { +- compatible = "nintendo,flipper-vi"; +- reg = <0x0c002000 0x100>; +- interrupts = <8>; +- }; +- +- processor-interface@c003000 { +- compatible = "nintendo,flipper-pi"; +- reg = <0x0c003000 0x100>; +- +- PIC: pic { +- #interrupt-cells = <1>; +- compatible = "nintendo,flipper-pic"; +- interrupt-controller; +- }; +- }; +- +- dsp@c005000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "nintendo,flipper-dsp"; +- reg = <0x0c005000 0x200>; +- interrupts = <6>; +- +- memory@0 { +- compatible = "nintendo,flipper-aram"; +- reg = <0 0x1000000>; /* 16MB */ +- }; +- }; +- +- disk@c006000 { +- compatible = "nintendo,flipper-di"; +- reg = <0x0c006000 0x40>; +- interrupts = <2>; +- }; +- +- audio@c006c00 { +- compatible = "nintendo,flipper-ai"; +- reg = <0x0c006c00 0x20>; +- interrupts = <6>; +- }; +- +- gamepad-controller@c006400 { +- compatible = "nintendo,flipper-si"; +- reg = <0x0c006400 0x100>; +- interrupts = <3>; +- }; +- +- /* External Interface bus */ +- exi@c006800 { +- compatible = "nintendo,flipper-exi"; +- reg = <0x0c006800 0x40>; +- virtual-reg = <0x0c006800>; +- interrupts = <4>; +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/powerpc/glacier.dts b/scripts/dtc/include-prefixes/powerpc/glacier.dts +deleted file mode 100644 +index e84ff1afb58c..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/glacier.dts ++++ /dev/null +@@ -1,576 +0,0 @@ +-/* +- * Device Tree Source for AMCC Glacier (460GT) +- * +- * Copyright 2008-2010 DENX Software Engineering, Stefan Roese +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <2>; +- #size-cells = <1>; +- model = "amcc,glacier"; +- compatible = "amcc,glacier"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- ethernet1 = &EMAC1; +- ethernet2 = &EMAC2; +- ethernet3 = &EMAC3; +- serial0 = &UART0; +- serial1 = &UART1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,460GT"; +- reg = <0x00000000>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- timebase-frequency = <0>; /* Filled in by U-Boot */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- next-level-cache = <&L2C0>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ +- }; +- +- UIC0: interrupt-controller0 { +- compatible = "ibm,uic-460gt","ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-460gt","ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC2: interrupt-controller2 { +- compatible = "ibm,uic-460gt","ibm,uic"; +- interrupt-controller; +- cell-index = <2>; +- dcr-reg = <0x0e0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC3: interrupt-controller3 { +- compatible = "ibm,uic-460gt","ibm,uic"; +- interrupt-controller; +- cell-index = <3>; +- dcr-reg = <0x0f0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- SDR0: sdr { +- compatible = "ibm,sdr-460gt"; +- dcr-reg = <0x00e 0x002>; +- }; +- +- CPR0: cpr { +- compatible = "ibm,cpr-460gt"; +- dcr-reg = <0x00c 0x002>; +- }; +- +- L2C0: l2c { +- compatible = "ibm,l2-cache-460gt", "ibm,l2-cache"; +- dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ +- 0x030 0x008>; /* L2 cache DCR's */ +- cache-line-size = <32>; /* 32 bytes */ +- cache-size = <262144>; /* L2, 256K */ +- interrupt-parent = <&UIC1>; +- interrupts = <11 1>; +- }; +- +- plb { +- compatible = "ibm,plb-460gt", "ibm,plb4"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- SDRAM0: sdram { +- compatible = "ibm,sdram-460gt", "ibm,sdram-405gp"; +- dcr-reg = <0x010 0x002>; +- }; +- +- CRYPTO: crypto@180000 { +- compatible = "amcc,ppc460gt-crypto", "amcc,ppc460ex-crypto", +- "amcc,ppc4xx-crypto"; +- reg = <4 0x00180000 0x80400>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1d 0x4>; +- }; +- +- HWRNG: hwrng@110000 { +- compatible = "amcc,ppc460ex-rng", "ppc4xx-rng"; +- reg = <4 0x00110000 0x50>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <4>; +- num-rx-chans = <32>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-parent = <&UIC2>; +- interrupts = < /*TXEOB*/ 0x6 0x4 +- /*RXEOB*/ 0x7 0x4 +- /*SERR*/ 0x3 0x4 +- /*TXDE*/ 0x4 0x4 +- /*RXDE*/ 0x5 0x4>; +- desc-base-addr-high = <0x8>; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-460gt", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- EBC0: ebc { +- compatible = "ibm,ebc-460gt", "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- /* ranges property is supplied by U-Boot */ +- interrupts = <0x6 0x4>; +- interrupt-parent = <&UIC1>; +- +- nor_flash@0,0 { +- compatible = "amd,s29gl512n", "cfi-flash"; +- bank-width = <2>; +- reg = <0x00000000 0x00000000 0x04000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x001e0000>; +- }; +- partition@1e0000 { +- label = "dtb"; +- reg = <0x001e0000 0x00020000>; +- }; +- partition@200000 { +- label = "ramdisk"; +- reg = <0x00200000 0x01400000>; +- }; +- partition@1600000 { +- label = "jffs2"; +- reg = <0x01600000 0x00400000>; +- }; +- partition@1a00000 { +- label = "user"; +- reg = <0x01a00000 0x02560000>; +- }; +- partition@3f60000 { +- label = "env"; +- reg = <0x03f60000 0x00040000>; +- }; +- partition@3fa0000 { +- label = "u-boot"; +- reg = <0x03fa0000 0x00060000>; +- }; +- }; +- +- ndfc@3,0 { +- compatible = "ibm,ndfc"; +- reg = <0x00000003 0x00000000 0x00002000>; +- ccr = <0x00001000>; +- bank-settings = <0x80002222>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- nand { +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x00000000 0x00100000>; +- }; +- partition@100000 { +- label = "user"; +- reg = <0x00000000 0x03f00000>; +- }; +- }; +- }; +- }; +- +- UART0: serial@ef600300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600300 0x00000008>; +- virtual-reg = <0xef600300>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; /* Filled in by U-Boot */ +- interrupt-parent = <&UIC1>; +- interrupts = <0x1 0x4>; +- }; +- +- UART1: serial@ef600400 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600400 0x00000008>; +- virtual-reg = <0xef600400>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; /* Filled in by U-Boot */ +- interrupt-parent = <&UIC0>; +- interrupts = <0x1 0x4>; +- }; +- +- UART2: serial@ef600500 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600500 0x00000008>; +- virtual-reg = <0xef600500>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; /* Filled in by U-Boot */ +- interrupt-parent = <&UIC1>; +- interrupts = <28 0x4>; +- }; +- +- UART3: serial@ef600600 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600600 0x00000008>; +- virtual-reg = <0xef600600>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; /* Filled in by U-Boot */ +- interrupt-parent = <&UIC1>; +- interrupts = <29 0x4>; +- }; +- +- IIC0: i2c@ef600700 { +- compatible = "ibm,iic-460gt", "ibm,iic"; +- reg = <0xef600700 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x2 0x4>; +- #address-cells = <1>; +- #size-cells = <0>; +- rtc@68 { +- compatible = "st,m41t80"; +- reg = <0x68>; +- interrupt-parent = <&UIC2>; +- interrupts = <0x19 0x8>; +- }; +- sttm@48 { +- compatible = "ad,ad7414"; +- reg = <0x48>; +- interrupt-parent = <&UIC1>; +- interrupts = <0x14 0x8>; +- }; +- }; +- +- IIC1: i2c@ef600800 { +- compatible = "ibm,iic-460gt", "ibm,iic"; +- reg = <0xef600800 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x3 0x4>; +- }; +- +- ZMII0: emac-zmii@ef600d00 { +- compatible = "ibm,zmii-460gt", "ibm,zmii"; +- reg = <0xef600d00 0x0000000c>; +- }; +- +- RGMII0: emac-rgmii@ef601500 { +- compatible = "ibm,rgmii-460gt", "ibm,rgmii"; +- reg = <0xef601500 0x00000008>; +- has-mdio; +- }; +- +- RGMII1: emac-rgmii@ef601600 { +- compatible = "ibm,rgmii-460gt", "ibm,rgmii"; +- reg = <0xef601600 0x00000008>; +- has-mdio; +- }; +- +- TAH0: emac-tah@ef601350 { +- compatible = "ibm,tah-460gt", "ibm,tah"; +- reg = <0xef601350 0x00000030>; +- }; +- +- TAH1: emac-tah@ef601450 { +- compatible = "ibm,tah-460gt", "ibm,tah"; +- reg = <0xef601450 0x00000030>; +- }; +- +- EMAC0: ethernet@ef600e00 { +- device_type = "network"; +- compatible = "ibm,emac-460gt", "ibm,emac4sync"; +- interrupt-parent = <&EMAC0>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600e00 0x000000c4>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <0>; +- tah-device = <&TAH0>; +- tah-channel = <0>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- +- EMAC1: ethernet@ef600f00 { +- device_type = "network"; +- compatible = "ibm,emac-460gt", "ibm,emac4sync"; +- interrupt-parent = <&EMAC1>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600f00 0x000000c4>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <1>; +- mal-rx-channel = <8>; +- cell-index = <1>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <1>; +- tah-device = <&TAH1>; +- tah-channel = <1>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- mdio-device = <&EMAC0>; +- }; +- +- EMAC2: ethernet@ef601100 { +- device_type = "network"; +- compatible = "ibm,emac-460gt", "ibm,emac4sync"; +- interrupt-parent = <&EMAC2>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef601100 0x000000c4>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <2>; +- mal-rx-channel = <16>; +- cell-index = <2>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- tx-fifo-size-gige = <16384>; /* emac2&3 only */ +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII1>; +- rgmii-channel = <0>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- mdio-device = <&EMAC0>; +- }; +- +- EMAC3: ethernet@ef601200 { +- device_type = "network"; +- compatible = "ibm,emac-460gt", "ibm,emac4sync"; +- interrupt-parent = <&EMAC3>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef601200 0x000000c4>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <3>; +- mal-rx-channel = <24>; +- cell-index = <3>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- tx-fifo-size-gige = <16384>; /* emac2&3 only */ +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII1>; +- rgmii-channel = <1>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- mdio-device = <&EMAC0>; +- }; +- }; +- +- PCIX0: pci@c0ec00000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix"; +- primary; +- large-inbound-windows; +- enable-msi-hole; +- reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ +- 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ +- 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ +- 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ +- 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 +- 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000 +- 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; +- +- /* This drives busses 0 to 0x3f */ +- bus-range = <0x0 0x3f>; +- +- /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ +- interrupt-map-mask = <0x0 0x0 0x0 0x0>; +- interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; +- }; +- +- PCIE0: pcie@d00000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; +- primary; +- port = <0x0>; /* port number */ +- reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ +- 0x0000000c 0x08010000 0x00001000>; /* Registers */ +- dcr-reg = <0x100 0x020>; +- sdr-base = <0x300>; +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 +- 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 +- 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; +- +- /* This drives busses 40 to 0x7f */ +- bus-range = <0x40 0x7f>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ +- 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ +- 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ +- 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; +- }; +- +- PCIE1: pcie@d20000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; +- primary; +- port = <0x1>; /* port number */ +- reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ +- 0x0000000c 0x08011000 0x00001000>; /* Registers */ +- dcr-reg = <0x120 0x020>; +- sdr-base = <0x340>; +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 +- 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000 +- 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; +- +- /* This drives busses 80 to 0xbf */ +- bus-range = <0x80 0xbf>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ +- 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ +- 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ +- 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/haleakala.dts b/scripts/dtc/include-prefixes/powerpc/haleakala.dts +deleted file mode 100644 +index f81ce8786d59..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/haleakala.dts ++++ /dev/null +@@ -1,281 +0,0 @@ +-/* +- * Device Tree Source for AMCC Haleakala (405EXr) +- * +- * Copyright 2008 DENX Software Engineering, Stefan Roese +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "amcc,haleakala"; +- compatible = "amcc,haleakala", "amcc,kilauea"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- serial0 = &UART0; +- serial1 = &UART1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,405EXr"; +- reg = <0x00000000>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- timebase-frequency = <0>; /* Filled in by U-Boot */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <16384>; /* 16 kB */ +- d-cache-size = <16384>; /* 16 kB */ +- dcr-controller; +- dcr-access-method = "native"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */ +- }; +- +- UIC0: interrupt-controller { +- compatible = "ibm,uic-405exr", "ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-405exr","ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC2: interrupt-controller2 { +- compatible = "ibm,uic-405exr","ibm,uic"; +- interrupt-controller; +- cell-index = <2>; +- dcr-reg = <0x0e0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- plb { +- compatible = "ibm,plb-405exr", "ibm,plb4"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- SDRAM0: memory-controller { +- compatible = "ibm,sdram-405exr", "ibm,sdram-4xx-ddr2"; +- dcr-reg = <0x010 0x002>; +- interrupt-parent = <&UIC2>; +- interrupts = <0x5 0x4 /* ECC DED Error */ +- 0x6 0x4>; /* ECC SEC Error */ +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-405exr", "ibm,mcmal2"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <2>; +- num-rx-chans = <2>; +- interrupt-parent = <&MAL0>; +- interrupts = <0x0 0x1 0x2 0x3 0x4>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- interrupt-map-mask = <0xffffffff>; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-405exr", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x80000000 0x80000000 0x10000000 +- 0xef600000 0xef600000 0x00a00000 +- 0xf0000000 0xf0000000 0x10000000>; +- dcr-reg = <0x0a0 0x005>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- EBC0: ebc { +- compatible = "ibm,ebc-405exr", "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- /* ranges property is supplied by U-Boot */ +- interrupts = <0x5 0x1>; +- interrupt-parent = <&UIC1>; +- +- nor_flash@0,0 { +- compatible = "amd,s29gl512n", "cfi-flash"; +- bank-width = <2>; +- reg = <0x00000000 0x00000000 0x04000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x00200000>; +- }; +- partition@200000 { +- label = "root"; +- reg = <0x00200000 0x00200000>; +- }; +- partition@400000 { +- label = "user"; +- reg = <0x00400000 0x03b60000>; +- }; +- partition@3f60000 { +- label = "env"; +- reg = <0x03f60000 0x00040000>; +- }; +- partition@3fa0000 { +- label = "u-boot"; +- reg = <0x03fa0000 0x00060000>; +- }; +- }; +- }; +- +- UART0: serial@ef600200 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600200 0x00000008>; +- virtual-reg = <0xef600200>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1a 0x4>; +- }; +- +- UART1: serial@ef600300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600300 0x00000008>; +- virtual-reg = <0xef600300>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1 0x4>; +- }; +- +- IIC0: i2c@ef600400 { +- compatible = "ibm,iic-405exr", "ibm,iic"; +- reg = <0xef600400 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x2 0x4>; +- }; +- +- IIC1: i2c@ef600500 { +- compatible = "ibm,iic-405exr", "ibm,iic"; +- reg = <0xef600500 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x7 0x4>; +- }; +- +- +- RGMII0: emac-rgmii@ef600b00 { +- compatible = "ibm,rgmii-405exr", "ibm,rgmii"; +- reg = <0xef600b00 0x00000104>; +- has-mdio; +- }; +- +- EMAC0: ethernet@ef600900 { +- linux,network-index = <0x0>; +- device_type = "network"; +- compatible = "ibm,emac-405exr", "ibm,emac4sync"; +- interrupt-parent = <&EMAC0>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600900 0x000000c4>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- tx-fifo-size-gige = <16384>; +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <0>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- }; +- +- PCIE0: pcie@a0000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; +- primary; +- port = <0x0>; /* port number */ +- reg = <0xa0000000 0x20000000 /* Config space access */ +- 0xef000000 0x00001000>; /* Registers */ +- dcr-reg = <0x040 0x020>; +- sdr-base = <0x400>; +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000 +- 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; +- +- /* This drives busses 0x00 to 0x3f */ +- bus-range = <0x0 0x3f>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */ +- 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */ +- 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */ +- 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/holly.dts b/scripts/dtc/include-prefixes/powerpc/holly.dts +deleted file mode 100644 +index 02bd304c7d38..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/holly.dts ++++ /dev/null +@@ -1,196 +0,0 @@ +-/* +- * Device Tree Source for IBM Holly (PPC 750CL with TSI controller) +- * Copyright 2007, IBM Corporation +- * +- * Stephen Winiecki +- * Josh Boyer +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- model = "41K7339"; +- compatible = "ibm,holly"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells =<0>; +- PowerPC,750CL@0 { +- device_type = "cpu"; +- reg = <0x00000000>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- d-cache-sets = <128>; +- i-cache-sets = <128>; +- timebase-frequency = <50000000>; +- clock-frequency = <600000000>; +- bus-frequency = <200000000>; +- }; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; +- }; +- +- tsi109@c0000000 { +- device_type = "tsi-bridge"; +- compatible = "tsi109-bridge", "tsi108-bridge"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0xc0000000 0x00010000>; +- reg = <0xc0000000 0x00010000>; +- +- i2c@7000 { +- device_type = "i2c"; +- compatible = "tsi109-i2c", "tsi108-i2c"; +- interrupt-parent = <&MPIC>; +- interrupts = <0xe 0x2>; +- reg = <0x00007000 0x00000400>; +- }; +- +- MDIO: mdio@6000 { +- compatible = "tsi109-mdio", "tsi108-mdio"; +- reg = <0x00006000 0x00000050>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- PHY1: ethernet-phy@1 { +- compatible = "bcm5461a"; +- reg = <0x00000001>; +- txc-rxc-delay-disable; +- }; +- +- PHY2: ethernet-phy@2 { +- compatible = "bcm5461a"; +- reg = <0x00000002>; +- txc-rxc-delay-disable; +- }; +- }; +- +- ethernet@6200 { +- device_type = "network"; +- compatible = "tsi109-ethernet", "tsi108-ethernet"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x00006000 0x00000200>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupt-parent = <&MPIC>; +- interrupts = <0x10 0x2>; +- mdio-handle = <&MDIO>; +- phy-handle = <&PHY1>; +- }; +- +- ethernet@6600 { +- device_type = "network"; +- compatible = "tsi109-ethernet", "tsi108-ethernet"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x00006400 0x00000200>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupt-parent = <&MPIC>; +- interrupts = <0x11 0x2>; +- mdio-handle = <&MDIO>; +- phy-handle = <&PHY2>; +- }; +- +- serial@7808 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0x00007808 0x00000200>; +- virtual-reg = <0xc0007808>; +- clock-frequency = <1067212800>; +- current-speed = <115200>; +- interrupt-parent = <&MPIC>; +- interrupts = <0xc 0x2>; +- }; +- +- serial@7c08 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0x00007c08 0x00000200>; +- virtual-reg = <0xc0007c08>; +- clock-frequency = <1067212800>; +- current-speed = <115200>; +- interrupt-parent = <&MPIC>; +- interrupts = <0xd 0x2>; +- }; +- +- MPIC: pic@7400 { +- device_type = "open-pic"; +- compatible = "chrp,open-pic"; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x00007400 0x00000400>; +- big-endian; +- }; +- }; +- +- pci@c0001000 { +- device_type = "pci"; +- compatible = "tsi109-pci", "tsi108-pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xc0001000 0x00001000>; +- bus-range = <0x0 0x0>; +- /*----------------------------------------------------+ +- | PCI memory range. +- | 01 denotes I/O space +- | 02 denotes 32-bit memory space +- +----------------------------------------------------*/ +- ranges = <0x02000000 0x00000000 0x40000000 0x40000000 0x00000000 0x10000000 +- 0x01000000 0x00000000 0x00000000 0x7e000000 0x00000000 0x00010000>; +- clock-frequency = <133333332>; +- interrupt-parent = <&MPIC>; +- interrupts = <0x17 0x2>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- /*----------------------------------------------------+ +- | The INTA, INTB, INTC, INTD are shared. +- +----------------------------------------------------*/ +- interrupt-map = < +- 0x800 0x0 0x0 0x1 &RT0 0x24 0x0 +- 0x800 0x0 0x0 0x2 &RT0 0x25 0x0 +- 0x800 0x0 0x0 0x3 &RT0 0x26 0x0 +- 0x800 0x0 0x0 0x4 &RT0 0x27 0x0 +- +- 0x1000 0x0 0x0 0x1 &RT0 0x25 0x0 +- 0x1000 0x0 0x0 0x2 &RT0 0x26 0x0 +- 0x1000 0x0 0x0 0x3 &RT0 0x27 0x0 +- 0x1000 0x0 0x0 0x4 &RT0 0x24 0x0 +- +- 0x1800 0x0 0x0 0x1 &RT0 0x26 0x0 +- 0x1800 0x0 0x0 0x2 &RT0 0x27 0x0 +- 0x1800 0x0 0x0 0x3 &RT0 0x24 0x0 +- 0x1800 0x0 0x0 0x4 &RT0 0x25 0x0 +- +- 0x2000 0x0 0x0 0x1 &RT0 0x27 0x0 +- 0x2000 0x0 0x0 0x2 &RT0 0x24 0x0 +- 0x2000 0x0 0x0 0x3 &RT0 0x25 0x0 +- 0x2000 0x0 0x0 0x4 &RT0 0x26 0x0 +- >; +- +- RT0: router@1180 { +- device_type = "pic-router"; +- interrupt-controller; +- big-endian; +- clock-frequency = <0>; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x17 0x2>; +- interrupt-parent = <&MPIC>; +- }; +- }; +- +- chosen { +- stdout-path = "/tsi109@c0000000/serial@7808"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/hotfoot.dts b/scripts/dtc/include-prefixes/powerpc/hotfoot.dts +deleted file mode 100644 +index b93bf2d9dd5b..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/hotfoot.dts ++++ /dev/null +@@ -1,296 +0,0 @@ +-/* +- * Device Tree Source for ESTeem 195E Hotfoot +- * +- * Copyright 2009 AbsoluteValue Systems +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "est,hotfoot"; +- compatible = "est,hotfoot"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- ethernet1 = &EMAC1; +- serial0 = &UART0; +- serial1 = &UART1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,405EP"; +- reg = <0x00000000>; +- clock-frequency = <0>; /* Filled in by zImage */ +- timebase-frequency = <0>; /* Filled in by zImage */ +- i-cache-line-size = <0x20>; +- d-cache-line-size = <0x20>; +- i-cache-size = <0x4000>; +- d-cache-size = <0x4000>; +- dcr-controller; +- dcr-access-method = "native"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000>; /* Filled in by zImage */ +- }; +- +- UIC0: interrupt-controller { +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- plb { +- compatible = "ibm,plb3"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; /* Filled in by zImage */ +- +- SDRAM0: memory-controller { +- compatible = "ibm,sdram-405ep"; +- dcr-reg = <0x010 0x002>; +- }; +- +- MAL: mcmal { +- compatible = "ibm,mcmal-405ep", "ibm,mcmal"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <4>; +- num-rx-chans = <2>; +- interrupt-parent = <&UIC0>; +- interrupts = < +- 0xb 0x4 /* TXEOB */ +- 0xc 0x4 /* RXEOB */ +- 0xa 0x4 /* SERR */ +- 0xd 0x4 /* TXDE */ +- 0xe 0x4 /* RXDE */>; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-405ep", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0xef600000 0xef600000 0x00a00000>; +- dcr-reg = <0x0a0 0x005>; +- clock-frequency = <0>; /* Filled in by zImage */ +- +- /* Hotfoot has UART0/UART1 swapped */ +- +- UART0: serial@ef600400 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600400 0x00000008>; +- virtual-reg = <0xef600400>; +- clock-frequency = <0>; /* Filled in by zImage */ +- current-speed = <0x9600>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1 0x4>; +- }; +- +- UART1: serial@ef600300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600300 0x00000008>; +- virtual-reg = <0xef600300>; +- clock-frequency = <0>; /* Filled in by zImage */ +- current-speed = <0x9600>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x0 0x4>; +- }; +- +- IIC: i2c@ef600500 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "ibm,iic-405ep", "ibm,iic"; +- reg = <0xef600500 0x00000011>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x2 0x4>; +- +- rtc@68 { +- /* Actually a DS1339 */ +- compatible = "dallas,ds1307"; +- reg = <0x68>; +- }; +- +- temp@4a { +- /* Not present on all boards */ +- compatible = "national,lm75"; +- reg = <0x4a>; +- }; +- }; +- +- GPIO: gpio@ef600700 { +- #gpio-cells = <2>; +- compatible = "ibm,ppc4xx-gpio"; +- reg = <0xef600700 0x00000020>; +- gpio-controller; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- status { +- label = "Status"; +- gpios = <&GPIO 1 0>; +- }; +- radiorx { +- label = "Rx"; +- gpios = <&GPIO 0xe 0>; +- }; +- }; +- +- EMAC0: ethernet@ef600800 { +- linux,network-index = <0x0>; +- device_type = "network"; +- compatible = "ibm,emac-405ep", "ibm,emac"; +- interrupt-parent = <&UIC0>; +- interrupts = < +- 0xf 0x4 /* Ethernet */ +- 0x9 0x4 /* Ethernet Wake Up */>; +- local-mac-address = [000000000000]; /* Filled in by zImage */ +- reg = <0xef600800 0x00000070>; +- mal-device = <&MAL>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <0x5dc>; +- rx-fifo-size = <0x1000>; +- tx-fifo-size = <0x800>; +- phy-mode = "mii"; +- phy-map = <0x00000000>; +- }; +- +- EMAC1: ethernet@ef600900 { +- linux,network-index = <0x1>; +- device_type = "network"; +- compatible = "ibm,emac-405ep", "ibm,emac"; +- interrupt-parent = <&UIC0>; +- interrupts = < +- 0x11 0x4 /* Ethernet */ +- 0x9 0x4 /* Ethernet Wake Up */>; +- local-mac-address = [000000000000]; /* Filled in by zImage */ +- reg = <0xef600900 0x00000070>; +- mal-device = <&MAL>; +- mal-tx-channel = <2>; +- mal-rx-channel = <1>; +- cell-index = <1>; +- max-frame-size = <0x5dc>; +- rx-fifo-size = <0x1000>; +- tx-fifo-size = <0x800>; +- mdio-device = <&EMAC0>; +- phy-mode = "mii"; +- phy-map = <0x0000001>; +- }; +- }; +- +- EBC0: ebc { +- compatible = "ibm,ebc-405ep", "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- +- /* The ranges property is supplied by the bootwrapper +- * and is based on the firmware's configuration of the +- * EBC bridge +- */ +- clock-frequency = <0>; /* Filled in by zImage */ +- +- nor_flash@0 { +- compatible = "cfi-flash"; +- bank-width = <2>; +- reg = <0x0 0xff800000 0x00800000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* This mapping is for the 8M flash +- 4M flash has all ofssets -= 4M, +- and FeatFS partition is not present */ +- partition@0 { +- label = "Bootloader"; +- reg = <0x7c0000 0x40000>; +- /* read-only; */ +- }; +- partition@1 { +- label = "Env_and_Config_Primary"; +- reg = <0x400000 0x10000>; +- }; +- partition@2 { +- label = "Kernel"; +- reg = <0x420000 0x100000>; +- }; +- partition@3 { +- label = "Filesystem"; +- reg = <0x520000 0x2a0000>; +- }; +- partition@4 { +- label = "Env_and_Config_Secondary"; +- reg = <0x410000 0x10000>; +- }; +- partition@5 { +- label = "FeatFS"; +- reg = <0x000000 0x400000>; +- }; +- partition@6 { +- label = "Bootloader_Env"; +- reg = <0x7d0000 0x10000>; +- }; +- }; +- }; +- +- PCI0: pci@ec000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb405ep-pci", "ibm,plb-pci"; +- primary; +- reg = <0xeec00000 0x00000008 /* Config space access */ +- 0xeed80000 0x00000004 /* IACK */ +- 0xeed80000 0x00000004 /* Special cycle */ +- 0xef480000 0x00000040>; /* Internal registers */ +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed. Chip supports a second +- * IO range but we don't use it for now +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000 +- 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; +- +- interrupt-parent = <&UIC0>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 3 -- slot1 (optional) 27/29 A/B IRQ2/4 */ +- 0x1800 0x0 0x0 0x1 &UIC0 0x1b 0x8 +- 0x1800 0x0 0x0 0x2 &UIC0 0x1d 0x8 +- +- /* IDSEL 4 -- slot0, 26/28 A/B IRQ1/3 */ +- 0x2000 0x0 0x0 0x1 &UIC0 0x1a 0x8 +- 0x2000 0x0 0x0 0x2 &UIC0 0x1c 0x8 +- >; +- }; +- }; +- +- chosen { +- stdout-path = &UART0; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/icon.dts b/scripts/dtc/include-prefixes/powerpc/icon.dts +deleted file mode 100644 +index 4fd7a4fbb4fb..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/icon.dts ++++ /dev/null +@@ -1,440 +0,0 @@ +-/* +- * Device Tree Source for Mosaix Technologies, Inc. ICON board +- * +- * Copyright 2010 DENX Software Engineering, Stefan Roese +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- model = "mosaixtech,icon"; +- compatible = "mosaixtech,icon"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- serial0 = &UART0; +- serial1 = &UART1; +- serial2 = &UART2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,440SPe"; +- reg = <0x00000000>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- timebase-frequency = <0>; /* Filled in by U-Boot */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- reset-type = <2>; /* Use chip-reset */ +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */ +- }; +- +- UIC0: interrupt-controller0 { +- compatible = "ibm,uic-440spe","ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-440spe","ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC2: interrupt-controller2 { +- compatible = "ibm,uic-440spe","ibm,uic"; +- interrupt-controller; +- cell-index = <2>; +- dcr-reg = <0x0e0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC3: interrupt-controller3 { +- compatible = "ibm,uic-440spe","ibm,uic"; +- interrupt-controller; +- cell-index = <3>; +- dcr-reg = <0x0f0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- SDR0: sdr { +- compatible = "ibm,sdr-440spe"; +- dcr-reg = <0x00e 0x002>; +- }; +- +- CPR0: cpr { +- compatible = "ibm,cpr-440spe"; +- dcr-reg = <0x00c 0x002>; +- }; +- +- MQ0: mq { +- compatible = "ibm,mq-440spe"; +- dcr-reg = <0x040 0x020>; +- }; +- +- plb { +- compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4"; +- #address-cells = <2>; +- #size-cells = <1>; +- /* addr-child addr-parent size */ +- ranges = <0x4 0x00100000 0x4 0x00100000 0x00001000 +- 0x4 0x00200000 0x4 0x00200000 0x00000400 +- 0x4 0xe0000000 0x4 0xe0000000 0x20000000 +- 0xc 0x00000000 0xc 0x00000000 0x20000000 +- 0xd 0x00000000 0xd 0x00000000 0x80000000 +- 0xd 0x80000000 0xd 0x80000000 0x80000000 +- 0xe 0x00000000 0xe 0x00000000 0x80000000 +- 0xe 0x80000000 0xe 0x80000000 0x80000000 +- 0xf 0x00000000 0xf 0x00000000 0x80000000 +- 0xf 0x80000000 0xf 0x80000000 0x80000000>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- SDRAM0: sdram { +- compatible = "ibm,sdram-440spe", "ibm,sdram-405gp"; +- dcr-reg = <0x010 0x002>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-440spe", "ibm,mcmal2"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <2>; +- num-rx-chans = <1>; +- interrupt-parent = <&MAL0>; +- interrupts = <0x0 0x1 0x2 0x3 0x4>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0xe0000000 0x00000004 0xe0000000 0x20000000>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- EBC0: ebc { +- compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- /* ranges property is supplied by U-Boot */ +- interrupts = <0x5 0x1>; +- interrupt-parent = <&UIC1>; +- +- nor_flash@0,0 { +- compatible = "cfi-flash"; +- bank-width = <2>; +- reg = <0x00000000 0x00000000 0x01000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x001e0000>; +- }; +- partition@1e0000 { +- label = "dtb"; +- reg = <0x001e0000 0x00020000>; +- }; +- partition@200000 { +- label = "root"; +- reg = <0x00200000 0x00200000>; +- }; +- partition@400000 { +- label = "user"; +- reg = <0x00400000 0x00b60000>; +- }; +- partition@f60000 { +- label = "env"; +- reg = <0x00f60000 0x00040000>; +- }; +- partition@fa0000 { +- label = "u-boot"; +- reg = <0x00fa0000 0x00060000>; +- }; +- }; +- }; +- +- UART0: serial@f0000200 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xf0000200 0x00000008>; +- virtual-reg = <0xa0000200>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <115200>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x0 0x4>; +- }; +- +- UART1: serial@f0000300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xf0000300 0x00000008>; +- virtual-reg = <0xa0000300>; +- clock-frequency = <0>; +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1 0x4>; +- }; +- +- +- UART2: serial@f0000600 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xf0000600 0x00000008>; +- virtual-reg = <0xa0000600>; +- clock-frequency = <0>; +- current-speed = <0>; +- interrupt-parent = <&UIC1>; +- interrupts = <0x5 0x4>; +- }; +- +- IIC0: i2c@f0000400 { +- compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; +- reg = <0xf0000400 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x2 0x4>; +- }; +- +- IIC1: i2c@f0000500 { +- compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; +- reg = <0xf0000500 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x3 0x4>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtc@68 { +- compatible = "st,m41t00"; +- reg = <0x68>; +- }; +- }; +- +- EMAC0: ethernet@f0000800 { +- linux,network-index = <0x0>; +- device_type = "network"; +- compatible = "ibm,emac-440spe", "ibm,emac4"; +- interrupt-parent = <&UIC1>; +- interrupts = <0x1c 0x4 0x1d 0x4>; +- reg = <0xf0000800 0x00000074>; +- local-mac-address = [000000000000]; +- mal-device = <&MAL0>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "gmii"; +- phy-map = <0x00000000>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- }; +- +- PCIX0: pci@c0ec00000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix"; +- primary; +- large-inbound-windows; +- enable-msi-hole; +- reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ +- 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ +- 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ +- 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ +- 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 +- 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; +- +- /* Inbound 4GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; +- +- /* This drives busses 0 to 0xf */ +- bus-range = <0x0 0xf>; +- +- /* PCI-X interrupt (SM502) is routed to extIRQ10 (UIC1, 19) */ +- interrupt-map-mask = <0x0 0x0 0x0 0x0>; +- interrupt-map = <0x0 0x0 0x0 0x0 &UIC1 19 0x8>; +- }; +- +- PCIE0: pcie@d00000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; +- primary; +- port = <0x0>; /* port number */ +- reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ +- 0x0000000c 0x10000000 0x00001000>; /* Registers */ +- dcr-reg = <0x100 0x020>; +- sdr-base = <0x300>; +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 +- 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; +- +- /* Inbound 4GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; +- +- /* This drives busses 0x10 to 0x1f */ +- bus-range = <0x10 0x1f>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */ +- 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */ +- 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */ +- 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>; +- }; +- +- PCIE1: pcie@d20000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; +- primary; +- port = <0x1>; /* port number */ +- reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ +- 0x0000000c 0x10001000 0x00001000>; /* Registers */ +- dcr-reg = <0x120 0x020>; +- sdr-base = <0x340>; +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 +- 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; +- +- /* Inbound 4GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; +- +- /* This drives busses 0x20 to 0x2f */ +- bus-range = <0x20 0x2f>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */ +- 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */ +- 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */ +- 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>; +- }; +- +- I2O: i2o@400100000 { +- compatible = "ibm,i2o-440spe"; +- reg = <0x00000004 0x00100000 0x100>; +- dcr-reg = <0x060 0x020>; +- }; +- +- DMA0: dma0@400100100 { +- compatible = "ibm,dma-440spe"; +- cell-index = <0>; +- reg = <0x00000004 0x00100100 0x100>; +- dcr-reg = <0x060 0x020>; +- interrupt-parent = <&DMA0>; +- interrupts = <0 1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = < +- 0 &UIC0 0x14 4 +- 1 &UIC1 0x16 4>; +- }; +- +- DMA1: dma1@400100200 { +- compatible = "ibm,dma-440spe"; +- cell-index = <1>; +- reg = <0x00000004 0x00100200 0x100>; +- dcr-reg = <0x060 0x020>; +- interrupt-parent = <&DMA1>; +- interrupts = <0 1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = < +- 0 &UIC0 0x16 4 +- 1 &UIC1 0x16 4>; +- }; +- +- xor-accel@400200000 { +- compatible = "amcc,xor-accelerator"; +- reg = <0x00000004 0x00200000 0x400>; +- interrupt-parent = <&UIC1>; +- interrupts = <0x1f 4>; +- }; +- }; +- +- chosen { +- stdout-path = "/plb/opb/serial@f0000200"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/iss4xx-mpic.dts b/scripts/dtc/include-prefixes/powerpc/iss4xx-mpic.dts +deleted file mode 100644 +index c9f90f1a9c8e..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/iss4xx-mpic.dts ++++ /dev/null +@@ -1,155 +0,0 @@ +-/* +- * Device Tree Source for IBM Embedded PPC 476 Platform +- * +- * Copyright 2010 Torez Smith, IBM Corporation. +- * +- * Based on earlier code: +- * Copyright (c) 2006, 2007 IBM Corp. +- * Josh Boyer , David Gibson +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/memreserve/ 0x01f00000 0x00100000; +- +-/ { +- #address-cells = <2>; +- #size-cells = <1>; +- model = "ibm,iss-4xx"; +- compatible = "ibm,iss-4xx"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- serial0 = &UART0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,4xx"; // real CPU changed in sim +- reg = <0>; +- clock-frequency = <100000000>; // 100Mhz :-) +- timebase-frequency = <100000000>; +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- status = "okay"; +- }; +- cpu@1 { +- device_type = "cpu"; +- model = "PowerPC,4xx"; // real CPU changed in sim +- reg = <1>; +- clock-frequency = <100000000>; // 100Mhz :-) +- timebase-frequency = <100000000>; +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- status = "disabled"; +- enable-method = "spin-table"; +- cpu-release-addr = <0 0x01f00100>; +- }; +- cpu@2 { +- device_type = "cpu"; +- model = "PowerPC,4xx"; // real CPU changed in sim +- reg = <2>; +- clock-frequency = <100000000>; // 100Mhz :-) +- timebase-frequency = <100000000>; +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- status = "disabled"; +- enable-method = "spin-table"; +- cpu-release-addr = <0 0x01f00200>; +- }; +- cpu@3 { +- device_type = "cpu"; +- model = "PowerPC,4xx"; // real CPU changed in sim +- reg = <3>; +- clock-frequency = <100000000>; // 100Mhz :-) +- timebase-frequency = <100000000>; +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- status = "disabled"; +- enable-method = "spin-table"; +- cpu-release-addr = <0 0x01f00300>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage +- +- }; +- +- MPIC: interrupt-controller { +- compatible = "chrp,open-pic"; +- interrupt-controller; +- dcr-reg = <0xffc00000 0x00030000>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- }; +- +- plb { +- compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */ +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; // Filled in by zImage +- +- POB0: opb { +- compatible = "ibm,opb-4xx", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- /* Wish there was a nicer way of specifying a full 32-bit +- range */ +- ranges = <0x00000000 0x00000001 0x00000000 0x80000000 +- 0x80000000 0x00000001 0x80000000 0x80000000>; +- clock-frequency = <0>; // Filled in by zImage +- UART0: serial@40000200 { +- device_type = "serial"; +- compatible = "ns16550a"; +- reg = <0x40000200 0x00000008>; +- virtual-reg = <0xe0000200>; +- clock-frequency = <11059200>; +- current-speed = <115200>; +- interrupt-parent = <&MPIC>; +- interrupts = <0x0 0x2>; +- }; +- }; +- }; +- +- nvrtc { +- compatible = "ds1743-nvram", "ds1743", "rtc-ds1743"; +- reg = <0 0xEF703000 0x2000>; +- }; +- iss-block { +- compatible = "ibm,iss-sim-block-device"; +- reg = <0 0xEF701000 0x1000>; +- }; +- +- chosen { +- stdout-path = "/plb/opb/serial@40000200"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/iss4xx.dts b/scripts/dtc/include-prefixes/powerpc/iss4xx.dts +deleted file mode 100644 +index 5533aff25e41..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/iss4xx.dts ++++ /dev/null +@@ -1,116 +0,0 @@ +-/* +- * Device Tree Source for IBM Embedded PPC 476 Platform +- * +- * Copyright 2010 Torez Smith, IBM Corporation. +- * +- * Based on earlier code: +- * Copyright (c) 2006, 2007 IBM Corp. +- * Josh Boyer , David Gibson +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <2>; +- #size-cells = <1>; +- model = "ibm,iss-4xx"; +- compatible = "ibm,iss-4xx"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- serial0 = &UART0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,4xx"; // real CPU changed in sim +- reg = <0x00000000>; +- clock-frequency = <100000000>; // 100Mhz :-) +- timebase-frequency = <100000000>; +- i-cache-line-size = <32>; // may need fixup in sim +- d-cache-line-size = <32>; // may need fixup in sim +- i-cache-size = <32768>; /* may need fixup in sim */ +- d-cache-size = <32768>; /* may need fixup in sim */ +- dcr-controller; +- dcr-access-method = "native"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage +- }; +- +- UIC0: interrupt-controller0 { +- compatible = "ibm,uic-4xx", "ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-4xx", "ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- plb { +- compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */ +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; // Filled in by zImage +- +- POB0: opb { +- compatible = "ibm,opb-4xx", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- /* Wish there was a nicer way of specifying a full 32-bit +- range */ +- ranges = <0x00000000 0x00000001 0x00000000 0x80000000 +- 0x80000000 0x00000001 0x80000000 0x80000000>; +- clock-frequency = <0>; // Filled in by zImage +- UART0: serial@40000200 { +- device_type = "serial"; +- compatible = "ns16550a"; +- reg = <0x40000200 0x00000008>; +- virtual-reg = <0xe0000200>; +- clock-frequency = <11059200>; +- current-speed = <115200>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x0 0x4>; +- }; +- }; +- }; +- +- nvrtc { +- compatible = "ds1743-nvram", "ds1743", "rtc-ds1743"; +- reg = <0 0xEF703000 0x2000>; +- }; +- iss-block { +- compatible = "ibm,iss-sim-block-device"; +- reg = <0 0xEF701000 0x1000>; +- }; +- +- chosen { +- stdout-path = "/plb/opb/serial@40000200"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/katmai.dts b/scripts/dtc/include-prefixes/powerpc/katmai.dts +deleted file mode 100644 +index a8f353229fb7..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/katmai.dts ++++ /dev/null +@@ -1,510 +0,0 @@ +-/* +- * Device Tree Source for AMCC Katmai eval board +- * +- * Copyright (c) 2006, 2007 IBM Corp. +- * Benjamin Herrenschmidt +- * +- * Copyright (c) 2006, 2007 IBM Corp. +- * Josh Boyer +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <2>; +- #size-cells = <2>; +- model = "amcc,katmai"; +- compatible = "amcc,katmai"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- serial0 = &UART0; +- serial1 = &UART1; +- serial2 = &UART2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,440SPe"; +- reg = <0x00000000>; +- clock-frequency = <0>; /* Filled in by zImage */ +- timebase-frequency = <0>; /* Filled in by zImage */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- reset-type = <2>; /* Use chip-reset */ +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */ +- }; +- +- UIC0: interrupt-controller0 { +- compatible = "ibm,uic-440spe","ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-440spe","ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC2: interrupt-controller2 { +- compatible = "ibm,uic-440spe","ibm,uic"; +- interrupt-controller; +- cell-index = <2>; +- dcr-reg = <0x0e0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC3: interrupt-controller3 { +- compatible = "ibm,uic-440spe","ibm,uic"; +- interrupt-controller; +- cell-index = <3>; +- dcr-reg = <0x0f0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- SDR0: sdr { +- compatible = "ibm,sdr-440spe"; +- dcr-reg = <0x00e 0x002>; +- }; +- +- CPR0: cpr { +- compatible = "ibm,cpr-440spe"; +- dcr-reg = <0x00c 0x002>; +- }; +- +- MQ0: mq { +- compatible = "ibm,mq-440spe"; +- dcr-reg = <0x040 0x020>; +- }; +- +- plb { +- compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4"; +- #address-cells = <2>; +- #size-cells = <1>; +- /* addr-child addr-parent size */ +- ranges = <0x4 0x00100000 0x4 0x00100000 0x00001000 +- 0x4 0x00200000 0x4 0x00200000 0x00000400 +- 0x4 0xe0000000 0x4 0xe0000000 0x20000000 +- 0xc 0x00000000 0xc 0x00000000 0x20000000 +- 0xd 0x00000000 0xd 0x00000000 0x80000000 +- 0xd 0x80000000 0xd 0x80000000 0x80000000 +- 0xe 0x00000000 0xe 0x00000000 0x80000000 +- 0xe 0x80000000 0xe 0x80000000 0x80000000 +- 0xf 0x00000000 0xf 0x00000000 0x80000000 +- 0xf 0x80000000 0xf 0x80000000 0x80000000>; +- clock-frequency = <0>; /* Filled in by zImage */ +- +- SDRAM0: sdram { +- compatible = "ibm,sdram-440spe", "ibm,sdram-405gp"; +- dcr-reg = <0x010 0x002>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-440spe", "ibm,mcmal2"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <2>; +- num-rx-chans = <1>; +- interrupt-parent = <&MAL0>; +- interrupts = <0x0 0x1 0x2 0x3 0x4>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0xe0000000 0x00000004 0xe0000000 0x20000000>; +- clock-frequency = <0>; /* Filled in by zImage */ +- +- EBC0: ebc { +- compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; /* Filled in by zImage */ +- /* ranges property is supplied by U-Boot */ +- interrupts = <0x5 0x1>; +- interrupt-parent = <&UIC1>; +- +- nor_flash@0,0 { +- compatible = "cfi-flash"; +- bank-width = <2>; +- reg = <0x00000000 0x00000000 0x01000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x001e0000>; +- }; +- partition@1e0000 { +- label = "dtb"; +- reg = <0x001e0000 0x00020000>; +- }; +- partition@200000 { +- label = "root"; +- reg = <0x00200000 0x00200000>; +- }; +- partition@400000 { +- label = "user"; +- reg = <0x00400000 0x00b60000>; +- }; +- partition@f60000 { +- label = "env"; +- reg = <0x00f60000 0x00040000>; +- }; +- partition@fa0000 { +- label = "u-boot"; +- reg = <0x00fa0000 0x00060000>; +- }; +- }; +- }; +- +- UART0: serial@f0000200 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xf0000200 0x00000008>; +- virtual-reg = <0xa0000200>; +- clock-frequency = <0>; /* Filled in by zImage */ +- current-speed = <115200>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x0 0x4>; +- }; +- +- UART1: serial@f0000300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xf0000300 0x00000008>; +- virtual-reg = <0xa0000300>; +- clock-frequency = <0>; +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1 0x4>; +- }; +- +- +- UART2: serial@f0000600 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xf0000600 0x00000008>; +- virtual-reg = <0xa0000600>; +- clock-frequency = <0>; +- current-speed = <0>; +- interrupt-parent = <&UIC1>; +- interrupts = <0x5 0x4>; +- }; +- +- IIC0: i2c@f0000400 { +- compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; +- reg = <0xf0000400 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x2 0x4>; +- }; +- +- IIC1: i2c@f0000500 { +- compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; +- reg = <0xf0000500 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x3 0x4>; +- }; +- +- EMAC0: ethernet@f0000800 { +- linux,network-index = <0x0>; +- device_type = "network"; +- compatible = "ibm,emac-440spe", "ibm,emac4"; +- interrupt-parent = <&UIC1>; +- interrupts = <0x1c 0x4 0x1d 0x4>; +- reg = <0xf0000800 0x00000074>; +- local-mac-address = [000000000000]; +- mal-device = <&MAL0>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "gmii"; +- phy-map = <0x00000000>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- }; +- +- PCIX0: pci@c0ec00000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix"; +- primary; +- large-inbound-windows; +- enable-msi-hole; +- reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ +- 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ +- 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ +- 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ +- 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 +- 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; +- +- /* Inbound 4GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; +- +- /* This drives busses 0 to 0xf */ +- bus-range = <0x0 0xf>; +- +- /* +- * On Katmai, the following PCI-X interrupts signals +- * have to be enabled via jumpers (only INTA is +- * enabled per default): +- * +- * INTB: J3: 1-2 +- * INTC: J2: 1-2 +- * INTD: J1: 1-2 +- */ +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 1 */ +- 0x800 0x0 0x0 0x1 &UIC1 0x14 0x8 +- 0x800 0x0 0x0 0x2 &UIC1 0x13 0x8 +- 0x800 0x0 0x0 0x3 &UIC1 0x12 0x8 +- 0x800 0x0 0x0 0x4 &UIC1 0x11 0x8 +- >; +- }; +- +- PCIE0: pcie@d00000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; +- primary; +- port = <0x0>; /* port number */ +- reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ +- 0x0000000c 0x10000000 0x00001000>; /* Registers */ +- dcr-reg = <0x100 0x020>; +- sdr-base = <0x300>; +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 +- 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; +- +- /* Inbound 4GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; +- +- /* This drives busses 0x10 to 0x1f */ +- bus-range = <0x10 0x1f>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */ +- 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */ +- 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */ +- 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>; +- }; +- +- PCIE1: pcie@d20000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; +- primary; +- port = <0x1>; /* port number */ +- reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ +- 0x0000000c 0x10001000 0x00001000>; /* Registers */ +- dcr-reg = <0x120 0x020>; +- sdr-base = <0x340>; +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 +- 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; +- +- /* Inbound 4GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; +- +- /* This drives busses 0x20 to 0x2f */ +- bus-range = <0x20 0x2f>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */ +- 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */ +- 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */ +- 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>; +- }; +- +- PCIE2: pcie@d40000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; +- primary; +- port = <0x2>; /* port number */ +- reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */ +- 0x0000000c 0x10002000 0x00001000>; /* Registers */ +- dcr-reg = <0x140 0x020>; +- sdr-base = <0x370>; +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000 +- 0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>; +- +- /* Inbound 4GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; +- +- /* This drives busses 0x30 to 0x3f */ +- bus-range = <0x30 0x3f>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */ +- 0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */ +- 0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */ +- 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>; +- }; +- +- MSI: ppc4xx-msi@400300000 { +- compatible = "amcc,ppc4xx-msi", "ppc4xx-msi"; +- reg = < 0x4 0x00300000 0x100>; +- sdr-base = <0x3B0>; +- msi-data = <0x00000000>; +- msi-mask = <0x44440000>; +- interrupt-count = <3>; +- interrupts =<0 1 2 3>; +- interrupt-parent = <&UIC0>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = <0 &UIC0 0xC 1 +- 1 &UIC0 0x0D 1 +- 2 &UIC0 0x0E 1 +- 3 &UIC0 0x0F 1>; +- }; +- +- I2O: i2o@400100000 { +- compatible = "ibm,i2o-440spe"; +- reg = <0x00000004 0x00100000 0x100>; +- dcr-reg = <0x060 0x020>; +- }; +- +- DMA0: dma0@400100100 { +- compatible = "ibm,dma-440spe"; +- cell-index = <0>; +- reg = <0x00000004 0x00100100 0x100>; +- dcr-reg = <0x060 0x020>; +- interrupt-parent = <&DMA0>; +- interrupts = <0 1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = < +- 0 &UIC0 0x14 4 +- 1 &UIC1 0x16 4>; +- }; +- +- DMA1: dma1@400100200 { +- compatible = "ibm,dma-440spe"; +- cell-index = <1>; +- reg = <0x00000004 0x00100200 0x100>; +- dcr-reg = <0x060 0x020>; +- interrupt-parent = <&DMA1>; +- interrupts = <0 1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = < +- 0 &UIC0 0x16 4 +- 1 &UIC1 0x16 4>; +- }; +- +- xor-accel@400200000 { +- compatible = "amcc,xor-accelerator"; +- reg = <0x00000004 0x00200000 0x400>; +- interrupt-parent = <&UIC1>; +- interrupts = <0x1f 4>; +- }; +- }; +- +- chosen { +- stdout-path = "/plb/opb/serial@f0000200"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/kilauea.dts b/scripts/dtc/include-prefixes/powerpc/kilauea.dts +deleted file mode 100644 +index a709fb47a180..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/kilauea.dts ++++ /dev/null +@@ -1,435 +0,0 @@ +-/* +- * Device Tree Source for AMCC Kilauea (405EX) +- * +- * Copyright 2007-2009 DENX Software Engineering, Stefan Roese +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "amcc,kilauea"; +- compatible = "amcc,kilauea"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- ethernet1 = &EMAC1; +- serial0 = &UART0; +- serial1 = &UART1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,405EX"; +- reg = <0x00000000>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- timebase-frequency = <0>; /* Filled in by U-Boot */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <16384>; /* 16 kB */ +- d-cache-size = <16384>; /* 16 kB */ +- dcr-controller; +- dcr-access-method = "native"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */ +- }; +- +- UIC0: interrupt-controller { +- compatible = "ibm,uic-405ex", "ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-405ex","ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC2: interrupt-controller2 { +- compatible = "ibm,uic-405ex","ibm,uic"; +- interrupt-controller; +- cell-index = <2>; +- dcr-reg = <0x0e0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- CPM0: cpm { +- compatible = "ibm,cpm"; +- dcr-access-method = "native"; +- dcr-reg = <0x0b0 0x003>; +- unused-units = <0x00000000>; +- idle-doze = <0x02000000>; +- standby = <0xe3e74800>; +- }; +- +- plb { +- compatible = "ibm,plb-405ex", "ibm,plb4"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- SDRAM0: memory-controller { +- compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2"; +- dcr-reg = <0x010 0x002>; +- interrupt-parent = <&UIC2>; +- interrupts = <0x5 0x4 /* ECC DED Error */ +- 0x6 0x4>; /* ECC SEC Error */ +- }; +- +- CRYPTO: crypto@ef700000 { +- compatible = "amcc,ppc405ex-crypto", "amcc,ppc4xx-crypto"; +- reg = <0xef700000 0x80400>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x17 0x2>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-405ex", "ibm,mcmal2"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <2>; +- num-rx-chans = <2>; +- interrupt-parent = <&MAL0>; +- interrupts = <0x0 0x1 0x2 0x3 0x4>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- interrupt-map-mask = <0xffffffff>; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-405ex", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x80000000 0x80000000 0x10000000 +- 0xef600000 0xef600000 0x00a00000 +- 0xf0000000 0xf0000000 0x10000000>; +- dcr-reg = <0x0a0 0x005>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- EBC0: ebc { +- compatible = "ibm,ebc-405ex", "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- /* ranges property is supplied by U-Boot */ +- interrupts = <0x5 0x1>; +- interrupt-parent = <&UIC1>; +- +- nor_flash@0,0 { +- compatible = "amd,s29gl512n", "cfi-flash"; +- bank-width = <2>; +- reg = <0x00000000 0x00000000 0x04000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x001e0000>; +- }; +- partition@1e0000 { +- label = "dtb"; +- reg = <0x001e0000 0x00020000>; +- }; +- partition@200000 { +- label = "root"; +- reg = <0x00200000 0x00200000>; +- }; +- partition@400000 { +- label = "user"; +- reg = <0x00400000 0x03b60000>; +- }; +- partition@3f60000 { +- label = "env"; +- reg = <0x03f60000 0x00040000>; +- }; +- partition@3fa0000 { +- label = "u-boot"; +- reg = <0x03fa0000 0x00060000>; +- }; +- }; +- +- ndfc@1,0 { +- compatible = "ibm,ndfc"; +- reg = <0x00000001 0x00000000 0x00002000>; +- ccr = <0x00001000>; +- bank-settings = <0x80002222>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- nand { +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x00000000 0x00100000>; +- }; +- partition@100000 { +- label = "user"; +- reg = <0x00000000 0x03f00000>; +- }; +- }; +- }; +- }; +- +- UART0: serial@ef600200 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600200 0x00000008>; +- virtual-reg = <0xef600200>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1a 0x4>; +- }; +- +- UART1: serial@ef600300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600300 0x00000008>; +- virtual-reg = <0xef600300>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1 0x4>; +- }; +- +- IIC0: i2c@ef600400 { +- compatible = "ibm,iic-405ex", "ibm,iic"; +- reg = <0xef600400 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x2 0x4>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtc@68 { +- compatible = "dallas,ds1338"; +- reg = <0x68>; +- }; +- +- dtt@48 { +- compatible = "dallas,ds1775"; +- reg = <0x48>; +- }; +- }; +- +- IIC1: i2c@ef600500 { +- compatible = "ibm,iic-405ex", "ibm,iic"; +- reg = <0xef600500 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x7 0x4>; +- }; +- +- RGMII0: emac-rgmii@ef600b00 { +- compatible = "ibm,rgmii-405ex", "ibm,rgmii"; +- reg = <0xef600b00 0x00000104>; +- has-mdio; +- }; +- +- EMAC0: ethernet@ef600900 { +- linux,network-index = <0x0>; +- device_type = "network"; +- compatible = "ibm,emac-405ex", "ibm,emac4sync"; +- interrupt-parent = <&EMAC0>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600900 0x000000c4>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- tx-fifo-size-gige = <16384>; +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <0>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- +- EMAC1: ethernet@ef600a00 { +- linux,network-index = <0x1>; +- device_type = "network"; +- compatible = "ibm,emac-405ex", "ibm,emac4sync"; +- interrupt-parent = <&EMAC1>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600a00 0x000000c4>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <1>; +- mal-rx-channel = <1>; +- cell-index = <1>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- tx-fifo-size-gige = <16384>; +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <1>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- }; +- +- PCIE0: pcie@a0000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; +- primary; +- port = <0x0>; /* port number */ +- reg = <0xa0000000 0x20000000 /* Config space access */ +- 0xef000000 0x00001000>; /* Registers */ +- dcr-reg = <0x040 0x020>; +- sdr-base = <0x400>; +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000 +- 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; +- +- /* This drives busses 0x00 to 0x3f */ +- bus-range = <0x0 0x3f>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */ +- 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */ +- 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */ +- 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>; +- }; +- +- PCIE1: pcie@c0000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; +- primary; +- port = <0x1>; /* port number */ +- reg = <0xc0000000 0x20000000 /* Config space access */ +- 0xef001000 0x00001000>; /* Registers */ +- dcr-reg = <0x060 0x020>; +- sdr-base = <0x440>; +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000 +- 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; +- +- /* This drives busses 0x40 to 0x7f */ +- bus-range = <0x40 0x7f>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */ +- 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */ +- 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */ +- 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>; +- }; +- +- MSI: ppc4xx-msi@C10000000 { +- compatible = "amcc,ppc4xx-msi", "ppc4xx-msi"; +- reg = <0xEF620000 0x100>; +- sdr-base = <0x4B0>; +- msi-data = <0x00000000>; +- msi-mask = <0x44440000>; +- interrupt-count = <12>; +- interrupts = <0 1 2 3 4 5 6 7 8 9 0xA 0xB 0xC 0xD>; +- interrupt-parent = <&UIC2>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = <0 &UIC2 0x10 1 +- 1 &UIC2 0x11 1 +- 2 &UIC2 0x12 1 +- 2 &UIC2 0x13 1 +- 2 &UIC2 0x14 1 +- 2 &UIC2 0x15 1 +- 2 &UIC2 0x16 1 +- 2 &UIC2 0x17 1 +- 2 &UIC2 0x18 1 +- 2 &UIC2 0x19 1 +- 2 &UIC2 0x1A 1 +- 2 &UIC2 0x1B 1 +- 2 &UIC2 0x1C 1 +- 3 &UIC2 0x1D 1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/klondike.dts b/scripts/dtc/include-prefixes/powerpc/klondike.dts +deleted file mode 100644 +index 97432177892a..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/klondike.dts ++++ /dev/null +@@ -1,212 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Device Tree for Klondike (APM8018X) board. +- * +- * Copyright (c) 2010, Applied Micro Circuits Corporation +- * Author: Tanmay Inamdar +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "apm,klondike"; +- compatible = "apm,klondike"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- ethernet1 = &EMAC1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,apm8018x"; +- reg = <0x00000000>; +- clock-frequency = <300000000>; /* Filled in by U-Boot */ +- timebase-frequency = <300000000>; /* Filled in by U-Boot */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <16384>; /* 16 kB */ +- d-cache-size = <16384>; /* 16 kB */ +- dcr-controller; +- dcr-access-method = "native"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; /* Filled in by U-Boot */ +- }; +- +- UIC0: interrupt-controller { +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x010>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x010>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC2: interrupt-controller2 { +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <2>; +- dcr-reg = <0x0e0 0x010>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x0a 0x4 0x0b 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC3: interrupt-controller3 { +- compatible = "ibm,uic"; +- interrupt-controller; +- cell-index = <3>; +- dcr-reg = <0x0f0 0x010>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- plb { +- compatible = "ibm,plb4"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- SDRAM0: memory-controller { +- compatible = "ibm,sdram-apm8018x"; +- dcr-reg = <0x010 0x002>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal2"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <2>; +- num-rx-chans = <16>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-parent = <&UIC1>; +- interrupts = ; +- }; +- +- POB0: opb { +- compatible = "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x20000000 0x20000000 0x30000000 +- 0x50000000 0x50000000 0x10000000 +- 0x60000000 0x60000000 0x10000000 +- 0xFE000000 0xFE000000 0x00010000>; +- dcr-reg = <0x100 0x020>; +- clock-frequency = <300000000>; /* Filled in by U-Boot */ +- +- RGMII0: emac-rgmii@400a2000 { +- compatible = "ibm,rgmii"; +- reg = <0x400a2000 0x00000010>; +- has-mdio; +- }; +- +- TAH0: emac-tah@400a3000 { +- compatible = "ibm,tah"; +- reg = <0x400a3000 0x100>; +- }; +- +- TAH1: emac-tah@400a4000 { +- compatible = "ibm,tah"; +- reg = <0x400a4000 0x100>; +- }; +- +- EMAC0: ethernet@400a0000 { +- compatible = "ibm,emac4", "ibm-emac4sync"; +- interrupt-parent = <&EMAC0>; +- interrupts = <0x0>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0x400a0000 0x00000100>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <0x0>; +- mal-rx-channel = <0x0>; +- cell-index = <0>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "rgmii"; +- phy-address = <0x2>; +- turbo = "no"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <0>; +- tah-device = <&TAH0>; +- tah-channel = <0>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- +- EMAC1: ethernet@400a1000 { +- compatible = "ibm,emac4", "ibm-emac4sync"; +- status = "disabled"; +- interrupt-parent = <&EMAC1>; +- interrupts = <0x0>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0x400a1000 0x00000100>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <1>; +- mal-rx-channel = <8>; +- cell-index = <1>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "rgmii"; +- phy-address = <0x3>; +- turbo = "no"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <1>; +- tah-device = <&TAH1>; +- tah-channel = <0>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- mdio-device = <&EMAC0>; +- }; +- }; +- }; +- +- chosen { +- stdout-path = "/plb/opb/serial@50001000"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/kmeter1.dts b/scripts/dtc/include-prefixes/powerpc/kmeter1.dts +deleted file mode 100644 +index 154f5d293fd3..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/kmeter1.dts ++++ /dev/null +@@ -1,528 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Keymile KMETER1 Device Tree Source +- * +- * 2008-2011 DENX Software Engineering GmbH +- */ +- +-/dts-v1/; +- +-/ { +- model = "KMETER1"; +- compatible = "keymile,KMETER1"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet_piggy2; +- ethernet1 = &enet_estar1; +- ethernet2 = &enet_estar2; +- ethernet3 = &enet_eth1; +- ethernet4 = &enet_eth2; +- ethernet5 = &enet_eth3; +- ethernet6 = &enet_eth4; +- serial0 = &serial0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8360@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <32768>; // L1, 32K +- i-cache-size = <32768>; // L1, 32K +- timebase-frequency = <0>; /* Filled in by U-Boot */ +- bus-frequency = <0>; /* Filled in by U-Boot */ +- clock-frequency = <0>; /* Filled in by U-Boot */ +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0 0>; /* Filled in by U-Boot */ +- }; +- +- soc8360@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,mpc8360-immr", "simple-bus"; +- ranges = <0x0 0xe0000000 0x00200000>; +- reg = <0xe0000000 0x00000200>; +- bus-frequency = <0>; /* Filled in by U-Boot */ +- +- pmc: power@b00 { +- compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc"; +- reg = <0xb00 0x100 0xa00 0x100>; +- interrupts = <80 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl,mpc8313-i2c","fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 0x8>; +- interrupt-parent = <&ipic>; +- clock-frequency = <400000>; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <264000000>; +- interrupts = <9 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- dma@82a8 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8360-dma", "fsl,elo-dma"; +- reg = <0x82a8 4>; +- ranges = <0 0x8100 0x1a8>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; +- reg = <0 0x80>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x80 0x80>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x100 0x80>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x180 0x28>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- }; +- +- ipic: pic@700 { +- #address-cells = <0>; +- #interrupt-cells = <2>; +- compatible = "fsl,pq2pro-pic", "fsl,ipic"; +- interrupt-controller; +- reg = <0x700 0x100>; +- }; +- +- par_io@1400 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x1400 0x100>; +- compatible = "fsl,mpc8360-par_io"; +- num-ports = <7>; +- +- qe_pio_c: gpio-controller@30 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8360-qe-pario-bank", +- "fsl,mpc8323-qe-pario-bank"; +- reg = <0x1430 0x18>; +- gpio-controller; +- }; +- pio_ucc1: ucc_pin@0 { +- reg = <0>; +- +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0 1 3 0 2 0 /* MDIO */ +- 0 2 1 0 1 0 /* MDC */ +- +- 0 3 1 0 1 0 /* TxD0 */ +- 0 4 1 0 1 0 /* TxD1 */ +- 0 5 1 0 1 0 /* TxD2 */ +- 0 6 1 0 1 0 /* TxD3 */ +- 0 9 2 0 1 0 /* RxD0 */ +- 0 10 2 0 1 0 /* RxD1 */ +- 0 11 2 0 1 0 /* RxD2 */ +- 0 12 2 0 1 0 /* RxD3 */ +- 0 7 1 0 1 0 /* TX_EN */ +- 0 8 1 0 1 0 /* TX_ER */ +- 0 15 2 0 1 0 /* RX_DV */ +- 0 16 2 0 1 0 /* RX_ER */ +- 0 0 2 0 1 0 /* RX_CLK */ +- 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ +- 2 8 2 0 1 0 /* GTX125 - CLK9 */ +- >; +- }; +- +- pio_ucc2: ucc_pin@1 { +- reg = <1>; +- +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0 1 3 0 2 0 /* MDIO */ +- 0 2 1 0 1 0 /* MDC */ +- +- 0 17 1 0 1 0 /* TxD0 */ +- 0 18 1 0 1 0 /* TxD1 */ +- 0 19 1 0 1 0 /* TxD2 */ +- 0 20 1 0 1 0 /* TxD3 */ +- 0 23 2 0 1 0 /* RxD0 */ +- 0 24 2 0 1 0 /* RxD1 */ +- 0 25 2 0 1 0 /* RxD2 */ +- 0 26 2 0 1 0 /* RxD3 */ +- 0 21 1 0 1 0 /* TX_EN */ +- 0 22 1 0 1 0 /* TX_ER */ +- 0 29 2 0 1 0 /* RX_DV */ +- 0 30 2 0 1 0 /* RX_ER */ +- 0 31 2 0 1 0 /* RX_CLK */ +- 2 2 1 0 2 0 /* GTX_CLK - CLK3 */ +- 2 3 2 0 1 0 /* GTX125 - CLK4 */ +- >; +- }; +- +- pio_ucc4: ucc_pin@3 { +- reg = <3>; +- +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0 1 3 0 2 0 /* MDIO */ +- 0 2 1 0 1 0 /* MDC */ +- +- 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */ +- 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */ +- 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */ +- 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */ +- 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */ +- 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */ +- 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */ +- +- 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */ +- >; +- }; +- +- pio_ucc5: ucc_pin@4 { +- reg = <4>; +- +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0 1 3 0 2 0 /* MDIO */ +- 0 2 1 0 1 0 /* MDC */ +- +- 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */ +- 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */ +- 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */ +- 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */ +- 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */ +- 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */ +- 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */ +- >; +- }; +- +- pio_ucc6: ucc_pin@5 { +- reg = <5>; +- +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0 1 3 0 2 0 /* MDIO */ +- 0 2 1 0 1 0 /* MDC */ +- +- 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */ +- 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */ +- 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */ +- 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */ +- 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */ +- 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */ +- 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */ +- >; +- }; +- +- pio_ucc7: ucc_pin@6 { +- reg = <6>; +- +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0 1 3 0 2 0 /* MDIO */ +- 0 2 1 0 1 0 /* MDC */ +- +- 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */ +- 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */ +- 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */ +- 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */ +- 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */ +- 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */ +- 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */ +- >; +- }; +- +- pio_ucc8: ucc_pin@7 { +- reg = <7>; +- +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0 1 3 0 2 0 /* MDIO */ +- 0 2 1 0 1 0 /* MDC */ +- +- 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */ +- 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */ +- 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */ +- 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */ +- 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */ +- 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */ +- 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */ +- +- 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */ +- >; +- }; +- +- }; +- +- qe@100000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,qe"; +- ranges = <0x0 0x100000 0x100000>; +- reg = <0x100000 0x480>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- brg-frequency = <0>; /* Filled in by U-Boot */ +- bus-frequency = <0>; /* Filled in by U-Boot */ +- +- muram@10000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,qe-muram", "fsl,cpm-muram"; +- ranges = <0x0 0x00010000 0x0000c000>; +- +- data-only@0 { +- compatible = "fsl,qe-muram-data", +- "fsl,cpm-muram-data"; +- reg = <0x0 0xc000>; +- }; +- }; +- +- /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ +- enet_estar1: ucc@2000 { +- device_type = "network"; +- compatible = "ucc_geth"; +- cell-index = <1>; +- reg = <0x2000 0x200>; +- interrupts = <32>; +- interrupt-parent = <&qeic>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "none"; +- tx-clock-name = "clk9"; +- phy-handle = <&phy_estar1>; +- phy-connection-type = "rgmii-id"; +- pio-handle = <&pio_ucc1>; +- }; +- +- /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ +- enet_estar2: ucc@3000 { +- device_type = "network"; +- compatible = "ucc_geth"; +- cell-index = <2>; +- reg = <0x3000 0x200>; +- interrupts = <33>; +- interrupt-parent = <&qeic>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "none"; +- tx-clock-name = "clk4"; +- phy-handle = <&phy_estar2>; +- phy-connection-type = "rgmii-id"; +- pio-handle = <&pio_ucc2>; +- }; +- +- /* Piggy2 (UCC4, MDIO 0x00, RMII) */ +- enet_piggy2: ucc@3200 { +- device_type = "network"; +- compatible = "ucc_geth"; +- cell-index = <4>; +- reg = <0x3200 0x200>; +- interrupts = <35>; +- interrupt-parent = <&qeic>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "none"; +- tx-clock-name = "clk17"; +- phy-handle = <&phy_piggy2>; +- phy-connection-type = "rmii"; +- pio-handle = <&pio_ucc4>; +- }; +- +- /* Eth-1 (UCC5, MDIO 0x08, RMII) */ +- enet_eth1: ucc@2400 { +- device_type = "network"; +- compatible = "ucc_geth"; +- cell-index = <5>; +- reg = <0x2400 0x200>; +- interrupts = <40>; +- interrupt-parent = <&qeic>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "none"; +- tx-clock-name = "clk16"; +- phy-handle = <&phy_eth1>; +- phy-connection-type = "rmii"; +- pio-handle = <&pio_ucc5>; +- }; +- +- /* Eth-2 (UCC6, MDIO 0x09, RMII) */ +- enet_eth2: ucc@3400 { +- device_type = "network"; +- compatible = "ucc_geth"; +- cell-index = <6>; +- reg = <0x3400 0x200>; +- interrupts = <41>; +- interrupt-parent = <&qeic>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "none"; +- tx-clock-name = "clk16"; +- phy-handle = <&phy_eth2>; +- phy-connection-type = "rmii"; +- pio-handle = <&pio_ucc6>; +- }; +- +- /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ +- enet_eth3: ucc@2600 { +- device_type = "network"; +- compatible = "ucc_geth"; +- cell-index = <7>; +- reg = <0x2600 0x200>; +- interrupts = <42>; +- interrupt-parent = <&qeic>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "none"; +- tx-clock-name = "clk16"; +- phy-handle = <&phy_eth3>; +- phy-connection-type = "rmii"; +- pio-handle = <&pio_ucc7>; +- }; +- +- /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ +- enet_eth4: ucc@3600 { +- device_type = "network"; +- compatible = "ucc_geth"; +- cell-index = <8>; +- reg = <0x3600 0x200>; +- interrupts = <43>; +- interrupt-parent = <&qeic>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "none"; +- tx-clock-name = "clk16"; +- phy-handle = <&phy_eth4>; +- phy-connection-type = "rmii"; +- pio-handle = <&pio_ucc8>; +- }; +- +- mdio@3320 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3320 0x18>; +- compatible = "fsl,ucc-mdio"; +- +- /* Piggy2 (UCC4, MDIO 0x00, RMII) */ +- phy_piggy2: ethernet-phy@0 { +- reg = <0x0>; +- }; +- +- /* Eth-1 (UCC5, MDIO 0x08, RMII) */ +- phy_eth1: ethernet-phy@8 { +- reg = <0x08>; +- }; +- +- /* Eth-2 (UCC6, MDIO 0x09, RMII) */ +- phy_eth2: ethernet-phy@9 { +- reg = <0x09>; +- }; +- +- /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ +- phy_eth3: ethernet-phy@a { +- reg = <0x0a>; +- }; +- +- /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ +- phy_eth4: ethernet-phy@b { +- reg = <0x0b>; +- }; +- +- /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ +- phy_estar1: ethernet-phy@10 { +- interrupt-parent = <&ipic>; +- interrupts = <17 0x8>; +- reg = <0x10>; +- }; +- +- /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ +- phy_estar2: ethernet-phy@11 { +- interrupt-parent = <&ipic>; +- interrupts = <18 0x8>; +- reg = <0x11>; +- }; +- }; +- +- qeic: interrupt-controller@80 { +- interrupt-controller; +- compatible = "fsl,qe-ic"; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x80 0x80>; +- big-endian; +- interrupts = < +- 32 0x8 +- 33 0x8 +- 34 0x8 +- 35 0x8 +- 40 0x8 +- 41 0x8 +- 42 0x8 +- 43 0x8 +- >; +- interrupt-parent = <&ipic>; +- }; +- }; +- }; +- +- localbus@e0005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", +- "simple-bus"; +- reg = <0xe0005000 0xd8>; +- ranges = <0 0 0xf0000000 0x04000000 /* LB 0 */ +- 1 0 0xe8000000 0x01000000 /* LB 1 */ +- 3 0 0xa0000000 0x10000000>; /* LB 3 */ +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x04000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- bank-width = <2>; +- partition@0 { /* 768KB */ +- label = "u-boot"; +- reg = <0 0xC0000>; +- }; +- partition@c0000 { /* 128KB */ +- label = "env"; +- reg = <0xC0000 0x20000>; +- }; +- partition@e0000 { /* 128KB */ +- label = "envred"; +- reg = <0xE0000 0x20000>; +- }; +- partition@100000 { /* 64512KB */ +- label = "ubi0"; +- reg = <0x100000 0x3F00000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/ksi8560.dts b/scripts/dtc/include-prefixes/powerpc/ksi8560.dts +deleted file mode 100644 +index fe6c17c8812a..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/ksi8560.dts ++++ /dev/null +@@ -1,344 +0,0 @@ +-/* +- * Device Tree Source for Emerson KSI8560 +- * +- * Author: Alexandr Smirnov +- * +- * Based on mpc8560ads.dts +- * +- * 2008 (c) MontaVista, Software, Inc. This file is licensed under +- * the terms of the GNU General Public License version 2. This program +- * is licensed "as is" without any warranty of any kind, whether express +- * or implied. +- * +- */ +- +-/dts-v1/; +- +-/ { +- model = "KSI8560"; +- compatible = "emerson,KSI8560"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8560@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <0x8000>; /* L1, 32K */ +- i-cache-size = <0x8000>; /* L1, 32K */ +- timebase-frequency = <0>; /* From U-boot */ +- bus-frequency = <0>; /* From U-boot */ +- clock-frequency = <0>; /* From U-boot */ +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; /* Fixed by bootwrapper */ +- }; +- +- soc@fdf00000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- ranges = <0x00000000 0xfdf00000 0x00100000>; +- bus-frequency = <0>; /* Fixed by bootwrapper */ +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <8>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8560-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8540-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <0x12 0x2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8540-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <0x20>; /* 32 bytes */ +- cache-size = <0x40000>; /* L2, 256K */ +- interrupt-parent = <&mpic>; +- interrupts = <0x10 0x2>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <0x2b 0x2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8560-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8560-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8560-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8560-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- /* Mac address filled in by bootwrapper */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&PHY1>; +- +- mdio@520 { /* For TSECs */ +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- PHY1: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- reg = <0x1>; +- }; +- +- PHY2: ethernet-phy@2 { +- interrupt-parent = <&mpic>; +- reg = <0x2>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- /* Mac address filled in by bootwrapper */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&PHY2>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- mpic: pic@40000 { +- #address-cells = <0>; +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0x40000 0x40000>; +- device_type = "open-pic"; +- }; +- +- cpm@919c0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8560-cpm", "fsl,cpm2"; +- reg = <0x919c0 0x30>; +- ranges; +- +- muram@80000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x80000 0x10000>; +- +- data@0 { +- compatible = "fsl,cpm-muram-data"; +- reg = <0x0 0x4000 0x9000 0x2000>; +- }; +- }; +- +- brg@919f0 { +- compatible = "fsl,mpc8560-brg", +- "fsl,cpm2-brg", +- "fsl,cpm-brg"; +- reg = <0x919f0 0x10 0x915f0 0x10>; +- clock-frequency = <165000000>; /* 166MHz */ +- }; +- +- CPMPIC: pic@90c00 { +- #address-cells = <0>; +- #interrupt-cells = <2>; +- interrupt-controller; +- interrupts = <0x2e 0x2>; +- interrupt-parent = <&mpic>; +- reg = <0x90c00 0x80>; +- compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic"; +- }; +- +- serial@91a00 { +- device_type = "serial"; +- compatible = "fsl,mpc8560-scc-uart", +- "fsl,cpm2-scc-uart"; +- reg = <0x91a00 0x20 0x88000 0x100>; +- fsl,cpm-brg = <1>; +- fsl,cpm-command = <0x800000>; +- current-speed = <0x1c200>; +- interrupts = <0x28 0x8>; +- interrupt-parent = <&CPMPIC>; +- }; +- +- serial@91a20 { +- device_type = "serial"; +- compatible = "fsl,mpc8560-scc-uart", +- "fsl,cpm2-scc-uart"; +- reg = <0x91a20 0x20 0x88100 0x100>; +- fsl,cpm-brg = <2>; +- fsl,cpm-command = <0x4a00000>; +- current-speed = <0x1c200>; +- interrupts = <0x29 0x8>; +- interrupt-parent = <&CPMPIC>; +- }; +- +- mdio@90d00 { /* For FCCs */ +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,cpm2-mdio-bitbang"; +- reg = <0x90d00 0x14>; +- fsl,mdio-pin = <24>; +- fsl,mdc-pin = <25>; +- +- PHY0: ethernet-phy@0 { +- interrupt-parent = <&mpic>; +- reg = <0x0>; +- }; +- }; +- +- enet2: ethernet@91300 { +- device_type = "network"; +- compatible = "fsl,mpc8560-fcc-enet", +- "fsl,cpm2-fcc-enet"; +- reg = <0x91300 0x20 0x88400 0x100 0x91390 0x1>; +- /* Mac address filled in by bootwrapper */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- fsl,cpm-command = <0x12000300>; +- interrupts = <0x20 0x8>; +- interrupt-parent = <&CPMPIC>; +- phy-handle = <&PHY0>; +- }; +- }; +- }; +- +- localbus@fdf05000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8560-localbus", "simple-bus"; +- reg = <0xfdf05000 0x68>; +- +- ranges = <0x0 0x0 0xe0000000 0x00800000 +- 0x4 0x0 0xe8080000 0x00080000>; +- +- flash@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec-flash"; +- reg = <0x0 0x0 0x800000>; +- bank-width = <0x2>; +- +- partition@0 { +- label = "Primary Kernel"; +- reg = <0x0 0x180000>; +- }; +- partition@180000 { +- label = "Primary Filesystem"; +- reg = <0x180000 0x580000>; +- }; +- partition@700000 { +- label = "Monitor"; +- reg = <0x300000 0x100000>; +- read-only; +- }; +- }; +- +- cpld@4,0 { +- compatible = "emerson,KSI8560-cpld"; +- reg = <0x4 0x0 0x80000>; +- }; +- }; +- +- +- chosen { +- stdout-path = "/soc/cpm/serial@91a00"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/kuroboxHD.dts b/scripts/dtc/include-prefixes/powerpc/kuroboxHD.dts +deleted file mode 100644 +index 0a4545159e80..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/kuroboxHD.dts ++++ /dev/null +@@ -1,147 +0,0 @@ +-/* +- * Device Tree Souce for Buffalo KuroboxHD +- * +- * Choose CONFIG_LINKSTATION to build a kernel for KuroboxHD, or use +- * the default configuration linkstation_defconfig. +- * +- * Based on sandpoint.dts +- * +- * 2006 (c) G. Liakhovetski +- * Copyright 2008 Freescale Semiconductor, Inc. +- * +- * This file is licensed under +- * the terms of the GNU General Public License version 2. This program +- * is licensed "as is" without any warranty of any kind, whether express +- * or implied. +- +-XXXX add flash parts, rtc, ?? +- +- */ +- +-/dts-v1/; +- +-/ { +- model = "KuroboxHD"; +- compatible = "linkstation"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,603e { /* Really 8241 */ +- device_type = "cpu"; +- reg = <0x0>; +- clock-frequency = <200000000>; /* Fixed by bootloader */ +- timebase-frequency = <24391680>; /* Fixed by bootloader */ +- bus-frequency = <0>; /* Fixed by bootloader */ +- /* Following required by dtc but not used */ +- i-cache-size = <0x4000>; +- d-cache-size = <0x4000>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x4000000>; +- }; +- +- soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */ +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "mpc10x"; +- store-gathering = <0>; /* 0 == off, !0 == on */ +- reg = <0x80000000 0x100000>; +- ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */ +- 0xfc000000 0xfc000000 0x100000 /* EUMB */ +- 0xfe000000 0xfe000000 0xc00000 /* pci i/o space */ +- 0xfec00000 0xfec00000 0x300000 /* pci cfg regs */ +- 0xfef00000 0xfef00000 0x100000>; /* pci iack */ +- +- i2c@80003000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x80003000 0x1000>; +- interrupts = <5 2>; +- interrupt-parent = <&mpic>; +- +- rtc@32 { +- compatible = "ricoh,rs5c372a"; +- reg = <0x32>; +- }; +- }; +- +- serial0: serial@80004500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x80004500 0x8>; +- clock-frequency = <97553800>; +- current-speed = <9600>; +- interrupts = <9 0>; +- interrupt-parent = <&mpic>; +- }; +- +- serial1: serial@80004600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x80004600 0x8>; +- clock-frequency = <97553800>; +- current-speed = <57600>; +- interrupts = <10 0>; +- interrupt-parent = <&mpic>; +- }; +- +- mpic: interrupt-controller@80040000 { +- #interrupt-cells = <2>; +- #address-cells = <0>; +- device_type = "open-pic"; +- compatible = "chrp,open-pic"; +- interrupt-controller; +- reg = <0x80040000 0x40000>; +- }; +- +- pci0: pci@fec00000 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "mpc10x-pci"; +- reg = <0xfec00000 0x400000>; +- ranges = <0x1000000 0x0 0x0 0xfe000000 0x0 0xc00000 +- 0x2000000 0x0 0x80000000 0x80000000 0x0 0x70000000>; +- bus-range = <0 255>; +- clock-frequency = <133333333>; +- interrupt-parent = <&mpic>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 11 - IRQ0 ETH */ +- 0x5800 0x0 0x0 0x1 &mpic 0x0 0x1 +- 0x5800 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1 +- /* IDSEL 12 - IRQ1 IDE0 */ +- 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1 +- 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1 +- 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1 +- 0x6000 0x0 0x0 0x4 &mpic 0x0 0x1 +- /* IDSEL 14 - IRQ3 USB2.0 */ +- 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1 +- 0x7000 0x0 0x0 0x2 &mpic 0x3 0x1 +- 0x7000 0x0 0x0 0x3 &mpic 0x3 0x1 +- 0x7000 0x0 0x0 0x4 &mpic 0x3 0x1 +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/kuroboxHG.dts b/scripts/dtc/include-prefixes/powerpc/kuroboxHG.dts +deleted file mode 100644 +index 0e758b347cdb..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/kuroboxHG.dts ++++ /dev/null +@@ -1,147 +0,0 @@ +-/* +- * Device Tree Souce for Buffalo KuroboxHG +- * +- * Choose CONFIG_LINKSTATION to build a kernel for KuroboxHG, or use +- * the default configuration linkstation_defconfig. +- * +- * Based on sandpoint.dts +- * +- * 2006 (c) G. Liakhovetski +- * Copyright 2008 Freescale Semiconductor, Inc. +- * +- * This file is licensed under +- * the terms of the GNU General Public License version 2. This program +- * is licensed "as is" without any warranty of any kind, whether express +- * or implied. +- +-XXXX add flash parts, rtc, ?? +- +- */ +- +-/dts-v1/; +- +-/ { +- model = "KuroboxHG"; +- compatible = "linkstation"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,603e { /* Really 8241 */ +- device_type = "cpu"; +- reg = <0x0>; +- clock-frequency = <266000000>; /* Fixed by bootloader */ +- timebase-frequency = <32522240>; /* Fixed by bootloader */ +- bus-frequency = <0>; /* Fixed by bootloader */ +- /* Following required by dtc but not used */ +- i-cache-size = <0x4000>; +- d-cache-size = <0x4000>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x8000000>; +- }; +- +- soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */ +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "mpc10x"; +- store-gathering = <0>; /* 0 == off, !0 == on */ +- reg = <0x80000000 0x100000>; +- ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */ +- 0xfc000000 0xfc000000 0x100000 /* EUMB */ +- 0xfe000000 0xfe000000 0xc00000 /* pci i/o space */ +- 0xfec00000 0xfec00000 0x300000 /* pci cfg regs */ +- 0xfef00000 0xfef00000 0x100000>; /* pci iack */ +- +- i2c@80003000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x80003000 0x1000>; +- interrupts = <5 2>; +- interrupt-parent = <&mpic>; +- +- rtc@32 { +- compatible = "ricoh,rs5c372a"; +- reg = <0x32>; +- }; +- }; +- +- serial0: serial@80004500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x80004500 0x8>; +- clock-frequency = <130041000>; +- current-speed = <9600>; +- interrupts = <9 0>; +- interrupt-parent = <&mpic>; +- }; +- +- serial1: serial@80004600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x80004600 0x8>; +- clock-frequency = <130041000>; +- current-speed = <57600>; +- interrupts = <10 0>; +- interrupt-parent = <&mpic>; +- }; +- +- mpic: interrupt-controller@80040000 { +- #interrupt-cells = <2>; +- #address-cells = <0>; +- device_type = "open-pic"; +- compatible = "chrp,open-pic"; +- interrupt-controller; +- reg = <0x80040000 0x40000>; +- }; +- +- pci0: pci@fec00000 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "mpc10x-pci"; +- reg = <0xfec00000 0x400000>; +- ranges = <0x1000000 0x0 0x0 0xfe000000 0x0 0xc00000 +- 0x2000000 0x0 0x80000000 0x80000000 0x0 0x70000000>; +- bus-range = <0 255>; +- clock-frequency = <133333333>; +- interrupt-parent = <&mpic>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 11 - IRQ0 ETH */ +- 0x5800 0x0 0x0 0x1 &mpic 0x0 0x1 +- 0x5800 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1 +- /* IDSEL 12 - IRQ1 IDE0 */ +- 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1 +- 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1 +- 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1 +- 0x6000 0x0 0x0 0x4 &mpic 0x0 0x1 +- /* IDSEL 14 - IRQ3 USB2.0 */ +- 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1 +- 0x7000 0x0 0x0 0x2 &mpic 0x3 0x1 +- 0x7000 0x0 0x0 0x3 &mpic 0x3 0x1 +- 0x7000 0x0 0x0 0x4 &mpic 0x3 0x1 +- >; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/lite5200.dts b/scripts/dtc/include-prefixes/powerpc/lite5200.dts +deleted file mode 100644 +index e7b194775d78..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/lite5200.dts ++++ /dev/null +@@ -1,304 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Lite5200 board Device Tree Source +- * +- * Copyright 2006-2007 Secret Lab Technologies Ltd. +- * Grant Likely +- */ +- +-/dts-v1/; +- +-/ { +- model = "fsl,lite5200"; +- compatible = "fsl,lite5200"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&mpc5200_pic>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,5200@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <0x4000>; // L1, 16K +- i-cache-size = <0x4000>; // L1, 16K +- timebase-frequency = <0>; // from bootloader +- bus-frequency = <0>; // from bootloader +- clock-frequency = <0>; // from bootloader +- }; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x04000000>; // 64MB +- }; +- +- soc5200@f0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc5200-immr"; +- ranges = <0 0xf0000000 0x0000c000>; +- reg = <0xf0000000 0x00000100>; +- bus-frequency = <0>; // from bootloader +- system-frequency = <0>; // from bootloader +- +- cdm@200 { +- compatible = "fsl,mpc5200-cdm"; +- reg = <0x200 0x38>; +- }; +- +- mpc5200_pic: interrupt-controller@500 { +- // 5200 interrupts are encoded into two levels; +- interrupt-controller; +- #interrupt-cells = <3>; +- compatible = "fsl,mpc5200-pic"; +- reg = <0x500 0x80>; +- }; +- +- timer@600 { // General Purpose Timer +- compatible = "fsl,mpc5200-gpt"; +- reg = <0x600 0x10>; +- interrupts = <1 9 0>; +- fsl,has-wdt; +- }; +- +- timer@610 { // General Purpose Timer +- compatible = "fsl,mpc5200-gpt"; +- reg = <0x610 0x10>; +- interrupts = <1 10 0>; +- }; +- +- timer@620 { // General Purpose Timer +- compatible = "fsl,mpc5200-gpt"; +- reg = <0x620 0x10>; +- interrupts = <1 11 0>; +- }; +- +- timer@630 { // General Purpose Timer +- compatible = "fsl,mpc5200-gpt"; +- reg = <0x630 0x10>; +- interrupts = <1 12 0>; +- }; +- +- timer@640 { // General Purpose Timer +- compatible = "fsl,mpc5200-gpt"; +- reg = <0x640 0x10>; +- interrupts = <1 13 0>; +- }; +- +- timer@650 { // General Purpose Timer +- compatible = "fsl,mpc5200-gpt"; +- reg = <0x650 0x10>; +- interrupts = <1 14 0>; +- }; +- +- timer@660 { // General Purpose Timer +- compatible = "fsl,mpc5200-gpt"; +- reg = <0x660 0x10>; +- interrupts = <1 15 0>; +- }; +- +- timer@670 { // General Purpose Timer +- compatible = "fsl,mpc5200-gpt"; +- reg = <0x670 0x10>; +- interrupts = <1 16 0>; +- }; +- +- rtc@800 { // Real time clock +- compatible = "fsl,mpc5200-rtc"; +- reg = <0x800 0x100>; +- interrupts = <1 5 0 1 6 0>; +- }; +- +- can@900 { +- compatible = "fsl,mpc5200-mscan"; +- interrupts = <2 17 0>; +- reg = <0x900 0x80>; +- }; +- +- can@980 { +- compatible = "fsl,mpc5200-mscan"; +- interrupts = <2 18 0>; +- reg = <0x980 0x80>; +- }; +- +- gpio@b00 { +- compatible = "fsl,mpc5200-gpio"; +- reg = <0xb00 0x40>; +- interrupts = <1 7 0>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpio@c00 { +- compatible = "fsl,mpc5200-gpio-wkup"; +- reg = <0xc00 0x40>; +- interrupts = <1 8 0 0 3 0>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- spi@f00 { +- compatible = "fsl,mpc5200-spi"; +- reg = <0xf00 0x20>; +- interrupts = <2 13 0 2 14 0>; +- }; +- +- usb@1000 { +- compatible = "fsl,mpc5200-ohci","ohci-be"; +- reg = <0x1000 0xff>; +- interrupts = <2 6 0>; +- }; +- +- dma-controller@1200 { +- compatible = "fsl,mpc5200-bestcomm"; +- reg = <0x1200 0x80>; +- interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 +- 3 4 0 3 5 0 3 6 0 3 7 0 +- 3 8 0 3 9 0 3 10 0 3 11 0 +- 3 12 0 3 13 0 3 14 0 3 15 0>; +- }; +- +- xlb@1f00 { +- compatible = "fsl,mpc5200-xlb"; +- reg = <0x1f00 0x100>; +- }; +- +- serial@2000 { // PSC1 +- compatible = "fsl,mpc5200-psc-uart"; +- cell-index = <0>; +- reg = <0x2000 0x100>; +- interrupts = <2 1 0>; +- }; +- +- // PSC2 in ac97 mode example +- //ac97@2200 { // PSC2 +- // compatible = "fsl,mpc5200-psc-ac97"; +- // cell-index = <1>; +- // reg = <0x2200 0x100>; +- // interrupts = <2 2 0>; +- //}; +- +- // PSC3 in CODEC mode example +- //i2s@2400 { // PSC3 +- // compatible = "fsl,mpc5200-psc-i2s"; +- // cell-index = <2>; +- // reg = <0x2400 0x100>; +- // interrupts = <2 3 0>; +- //}; +- +- // PSC4 in uart mode example +- //serial@2600 { // PSC4 +- // compatible = "fsl,mpc5200-psc-uart"; +- // cell-index = <3>; +- // reg = <0x2600 0x100>; +- // interrupts = <2 11 0>; +- //}; +- +- // PSC5 in uart mode example +- //serial@2800 { // PSC5 +- // compatible = "fsl,mpc5200-psc-uart"; +- // cell-index = <4>; +- // reg = <0x2800 0x100>; +- // interrupts = <2 12 0>; +- //}; +- +- // PSC6 in spi mode example +- //spi@2c00 { // PSC6 +- // compatible = "fsl,mpc5200-psc-spi"; +- // cell-index = <5>; +- // reg = <0x2c00 0x100>; +- // interrupts = <2 4 0>; +- //}; +- +- ethernet@3000 { +- compatible = "fsl,mpc5200-fec"; +- reg = <0x3000 0x400>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <2 5 0>; +- phy-handle = <&phy0>; +- }; +- +- mdio@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc5200-mdio"; +- reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts +- interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- ata@3a00 { +- compatible = "fsl,mpc5200-ata"; +- reg = <0x3a00 0x100>; +- interrupts = <2 7 0>; +- }; +- +- i2c@3d00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc5200-i2c","fsl-i2c"; +- reg = <0x3d00 0x40>; +- interrupts = <2 15 0>; +- }; +- +- i2c@3d40 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc5200-i2c","fsl-i2c"; +- reg = <0x3d40 0x40>; +- interrupts = <2 16 0>; +- +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- }; +- }; +- +- sram@8000 { +- compatible = "fsl,mpc5200-sram"; +- reg = <0x8000 0x4000>; +- }; +- }; +- +- pci@f0000d00 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- compatible = "fsl,mpc5200-pci"; +- reg = <0xf0000d00 0x100>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 +- 0xc000 0 0 2 &mpc5200_pic 0 0 3 +- 0xc000 0 0 3 &mpc5200_pic 0 0 3 +- 0xc000 0 0 4 &mpc5200_pic 0 0 3>; +- clock-frequency = <0>; // From boot loader +- interrupts = <2 8 0 2 9 0 2 10 0>; +- bus-range = <0 0>; +- ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 +- 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; +- }; +- +- localbus { +- compatible = "fsl,mpc5200-lpb","simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- +- ranges = <0 0 0xff000000 0x01000000>; +- +- flash@0,0 { +- compatible = "amd,am29lv652d", "cfi-flash"; +- reg = <0 0 0x01000000>; +- bank-width = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/lite5200b.dts b/scripts/dtc/include-prefixes/powerpc/lite5200b.dts +deleted file mode 100644 +index 547cbe726ff2..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/lite5200b.dts ++++ /dev/null +@@ -1,157 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Lite5200B board Device Tree Source +- * +- * Copyright 2006-2007 Secret Lab Technologies Ltd. +- * Grant Likely +- */ +- +-/include/ "mpc5200b.dtsi" +- +-&gpt0 { fsl,has-wdt; }; +-&gpt2 { gpio-controller; }; +-&gpt3 { gpio-controller; }; +- +-/ { +- model = "fsl,lite5200b"; +- compatible = "fsl,lite5200b"; +- +- leds { +- compatible = "gpio-leds"; +- tmr2 { +- gpios = <&gpt2 0 1>; +- }; +- tmr3 { +- gpios = <&gpt3 0 1>; +- linux,default-trigger = "heartbeat"; +- }; +- led1 { gpios = <&gpio_wkup 2 1>; }; +- led2 { gpios = <&gpio_simple 3 1>; }; +- led3 { gpios = <&gpio_wkup 3 1>; }; +- led4 { gpios = <&gpio_simple 2 1>; }; +- }; +- +- memory@0 { +- reg = <0x00000000 0x10000000>; // 256MB +- }; +- +- soc5200@f0000000 { +- psc@2000 { // PSC1 +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- cell-index = <0>; +- }; +- +- psc@2200 { // PSC2 +- status = "disabled"; +- }; +- +- psc@2400 { // PSC3 +- status = "disabled"; +- }; +- +- psc@2600 { // PSC4 +- status = "disabled"; +- }; +- +- psc@2800 { // PSC5 +- status = "disabled"; +- }; +- +- psc@2c00 { // PSC6 +- status = "disabled"; +- }; +- +- // PSC2 in ac97 mode example +- //ac97@2200 { // PSC2 +- // compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; +- // cell-index = <1>; +- //}; +- +- // PSC3 in CODEC mode example +- //i2s@2400 { // PSC3 +- // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible +- // cell-index = <2>; +- //}; +- +- // PSC6 in spi mode example +- //spi@2c00 { // PSC6 +- // compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; +- // cell-index = <5>; +- //}; +- +- ethernet@3000 { +- phy-handle = <&phy0>; +- }; +- +- mdio@3000 { +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- i2c@3d40 { +- eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- }; +- }; +- +- sram@8000 { +- compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; +- reg = <0x8000 0x4000>; +- }; +- }; +- +- pci@f0000d00 { +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot +- 0xc000 0 0 2 &mpc5200_pic 1 1 3 +- 0xc000 0 0 3 &mpc5200_pic 1 2 3 +- 0xc000 0 0 4 &mpc5200_pic 1 3 3 +- +- 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot +- 0xc800 0 0 2 &mpc5200_pic 1 2 3 +- 0xc800 0 0 3 &mpc5200_pic 1 3 3 +- 0xc800 0 0 4 &mpc5200_pic 0 0 3>; +- clock-frequency = <0>; // From boot loader +- interrupts = <2 8 0 2 9 0 2 10 0>; +- bus-range = <0 0>; +- ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 +- 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; +- }; +- +- localbus { +- ranges = <0 0 0xfe000000 0x02000000>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x02000000>; +- bank-width = <1>; +- #size-cells = <1>; +- #address-cells = <1>; +- +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x00200000>; +- }; +- partition@200000 { +- label = "rootfs"; +- reg = <0x00200000 0x01d00000>; +- }; +- partition@1f00000 { +- label = "u-boot"; +- reg = <0x01f00000 0x00060000>; +- }; +- partition@1f60000 { +- label = "u-boot-env"; +- reg = <0x01f60000 0x00020000>; +- }; +- partition@1f80000 { +- label = "dtb"; +- reg = <0x01f80000 0x00080000>; +- }; +- }; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/makalu.dts b/scripts/dtc/include-prefixes/powerpc/makalu.dts +deleted file mode 100644 +index c473cd911bca..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/makalu.dts ++++ /dev/null +@@ -1,353 +0,0 @@ +-/* +- * Device Tree Source for AMCC Makalu (405EX) +- * +- * Copyright 2007 DENX Software Engineering, Stefan Roese +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "amcc,makalu"; +- compatible = "amcc,makalu"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- ethernet1 = &EMAC1; +- serial0 = &UART0; +- serial1 = &UART1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,405EX"; +- reg = <0x00000000>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- timebase-frequency = <0>; /* Filled in by U-Boot */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <16384>; /* 16 kB */ +- d-cache-size = <16384>; /* 16 kB */ +- dcr-controller; +- dcr-access-method = "native"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */ +- }; +- +- UIC0: interrupt-controller { +- compatible = "ibm,uic-405ex", "ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-405ex","ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC2: interrupt-controller2 { +- compatible = "ibm,uic-405ex","ibm,uic"; +- interrupt-controller; +- cell-index = <2>; +- dcr-reg = <0x0e0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- plb { +- compatible = "ibm,plb-405ex", "ibm,plb4"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- SDRAM0: memory-controller { +- compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2"; +- dcr-reg = <0x010 0x002>; +- interrupt-parent = <&UIC2>; +- interrupts = <0x5 0x4 /* ECC DED Error */ +- 0x6 0x4 /* ECC SEC Error */ >; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-405ex", "ibm,mcmal2"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <2>; +- num-rx-chans = <2>; +- interrupt-parent = <&MAL0>; +- interrupts = <0x0 0x1 0x2 0x3 0x4>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- interrupt-map-mask = <0xffffffff>; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-405ex", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x80000000 0x80000000 0x10000000 +- 0xef600000 0xef600000 0x00a00000 +- 0xf0000000 0xf0000000 0x10000000>; +- dcr-reg = <0x0a0 0x005>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- EBC0: ebc { +- compatible = "ibm,ebc-405ex", "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- /* ranges property is supplied by U-Boot */ +- interrupts = <0x5 0x1>; +- interrupt-parent = <&UIC1>; +- +- nor_flash@0,0 { +- compatible = "amd,s29gl512n", "cfi-flash"; +- bank-width = <2>; +- reg = <0x00000000 0x00000000 0x04000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x00200000>; +- }; +- partition@200000 { +- label = "root"; +- reg = <0x00200000 0x00200000>; +- }; +- partition@400000 { +- label = "user"; +- reg = <0x00400000 0x03b60000>; +- }; +- partition@3f60000 { +- label = "env"; +- reg = <0x03f60000 0x00040000>; +- }; +- partition@3fa0000 { +- label = "u-boot"; +- reg = <0x03fa0000 0x00060000>; +- }; +- }; +- }; +- +- UART0: serial@ef600200 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600200 0x00000008>; +- virtual-reg = <0xef600200>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1a 0x4>; +- }; +- +- UART1: serial@ef600300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600300 0x00000008>; +- virtual-reg = <0xef600300>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1 0x4>; +- }; +- +- IIC0: i2c@ef600400 { +- compatible = "ibm,iic-405ex", "ibm,iic"; +- reg = <0xef600400 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x2 0x4>; +- }; +- +- IIC1: i2c@ef600500 { +- compatible = "ibm,iic-405ex", "ibm,iic"; +- reg = <0xef600500 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x7 0x4>; +- }; +- +- +- RGMII0: emac-rgmii@ef600b00 { +- compatible = "ibm,rgmii-405ex", "ibm,rgmii"; +- reg = <0xef600b00 0x00000104>; +- has-mdio; +- }; +- +- EMAC0: ethernet@ef600900 { +- linux,network-index = <0x0>; +- device_type = "network"; +- compatible = "ibm,emac-405ex", "ibm,emac4sync"; +- interrupt-parent = <&EMAC0>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600900 0x000000c4>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- tx-fifo-size-gige = <16384>; +- phy-mode = "rgmii"; +- phy-map = <0x0000003f>; /* Start at 6 */ +- rgmii-device = <&RGMII0>; +- rgmii-channel = <0>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- +- EMAC1: ethernet@ef600a00 { +- linux,network-index = <0x1>; +- device_type = "network"; +- compatible = "ibm,emac-405ex", "ibm,emac4sync"; +- interrupt-parent = <&EMAC1>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600a00 0x000000c4>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <1>; +- mal-rx-channel = <1>; +- cell-index = <1>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- tx-fifo-size-gige = <16384>; +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <1>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- }; +- +- PCIE0: pcie@a0000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; +- primary; +- port = <0x0>; /* port number */ +- reg = <0xa0000000 0x20000000 /* Config space access */ +- 0xef000000 0x00001000>; /* Registers */ +- dcr-reg = <0x040 0x020>; +- sdr-base = <0x400>; +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000 +- 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; +- +- /* This drives busses 0x00 to 0x3f */ +- bus-range = <0x0 0x3f>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */ +- 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */ +- 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */ +- 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>; +- }; +- +- PCIE1: pcie@c0000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; +- primary; +- port = <0x1>; /* port number */ +- reg = <0xc0000000 0x20000000 /* Config space access */ +- 0xef001000 0x00001000>; /* Registers */ +- dcr-reg = <0x060 0x020>; +- sdr-base = <0x440>; +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000 +- 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; +- +- /* This drives busses 0x40 to 0x7f */ +- bus-range = <0x40 0x7f>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */ +- 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */ +- 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */ +- 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/media5200.dts b/scripts/dtc/include-prefixes/powerpc/media5200.dts +deleted file mode 100644 +index f3188018face..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/media5200.dts ++++ /dev/null +@@ -1,142 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Freescale Media5200 board Device Tree Source +- * +- * Copyright 2009 Secret Lab Technologies Ltd. +- * Grant Likely +- * Steven Cavanagh +- */ +- +-/include/ "mpc5200b.dtsi" +- +-&gpt0 { fsl,has-wdt; }; +- +-/ { +- model = "fsl,media5200"; +- compatible = "fsl,media5200"; +- +- aliases { +- console = &console; +- ethernet0 = ð0; +- }; +- +- chosen { +- stdout-path = &console; +- }; +- +- cpus { +- PowerPC,5200@0 { +- timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot +- bus-frequency = <132000000>; // 132 MHz +- clock-frequency = <396000000>; // 396 MHz +- }; +- }; +- +- memory@0 { +- reg = <0x00000000 0x08000000>; // 128MB RAM +- }; +- +- soc5200@f0000000 { +- bus-frequency = <132000000>;// 132 MHz +- +- psc@2000 { // PSC1 +- status = "disabled"; +- }; +- +- psc@2200 { // PSC2 +- status = "disabled"; +- }; +- +- psc@2400 { // PSC3 +- status = "disabled"; +- }; +- +- psc@2600 { // PSC4 +- status = "disabled"; +- }; +- +- psc@2800 { // PSC5 +- status = "disabled"; +- }; +- +- // PSC6 in uart mode +- console: psc@2c00 { // PSC6 +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- ethernet@3000 { +- phy-handle = <&phy0>; +- }; +- +- mdio@3000 { +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- usb@1000 { +- reg = <0x1000 0x100>; +- }; +- }; +- +- pci@f0000d00 { +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot +- 0xc000 0 0 2 &media5200_fpga 0 3 +- 0xc000 0 0 3 &media5200_fpga 0 4 +- 0xc000 0 0 4 &media5200_fpga 0 5 +- +- 0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot +- 0xc800 0 0 2 &media5200_fpga 0 4 +- 0xc800 0 0 3 &media5200_fpga 0 5 +- 0xc800 0 0 4 &media5200_fpga 0 2 +- +- 0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI +- 0xd000 0 0 2 &media5200_fpga 0 5 +- +- 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP +- >; +- ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 +- 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; +- interrupt-parent = <&mpc5200_pic>; +- }; +- +- localbus { +- ranges = < 0 0 0xfc000000 0x02000000 +- 1 0 0xfe000000 0x02000000 +- 2 0 0xf0010000 0x00010000 +- 3 0 0xf0020000 0x00010000 >; +- flash@0,0 { +- compatible = "amd,am29lv28ml", "cfi-flash"; +- reg = <0 0x0 0x2000000>; // 32 MB +- bank-width = <4>; // Width in bytes of the flash bank +- device-width = <2>; // Two devices on each bank +- }; +- +- flash@1,0 { +- compatible = "amd,am29lv28ml", "cfi-flash"; +- reg = <1 0 0x2000000>; // 32 MB +- bank-width = <4>; // Width in bytes of the flash bank +- device-width = <2>; // Two devices on each bank +- }; +- +- media5200_fpga: fpga@2,0 { +- compatible = "fsl,media5200-fpga"; +- interrupt-controller; +- #interrupt-cells = <2>; // 0:bank 1:id; no type field +- reg = <2 0 0x10000>; +- +- interrupt-parent = <&mpc5200_pic>; +- interrupts = <0 0 3 // IRQ bank 0 +- 1 1 3>; // IRQ bank 1 +- }; +- +- uart@3,0 { +- compatible = "ti,tl16c752bpt"; +- reg = <3 0 0x10000>; +- interrupt-parent = <&media5200_fpga>; +- interrupts = <0 0 0 1>; // 2 irqs +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mgcoge.dts b/scripts/dtc/include-prefixes/powerpc/mgcoge.dts +deleted file mode 100644 +index 7de068991bde..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mgcoge.dts ++++ /dev/null +@@ -1,260 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Device Tree for the MGCOGE plattform from keymile +- * +- * Copyright 2008 DENX Software Engineering GmbH +- * Heiko Schocher +- */ +- +-/dts-v1/; +-/ { +- model = "MGCOGE"; +- compatible = "keymile,km82xx"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = ð0; +- serial0 = &smc2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8247@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <16384>; +- i-cache-size = <16384>; +- timebase-frequency = <0>; /* Filled in by U-Boot */ +- clock-frequency = <0>; /* Filled in by U-Boot */ +- bus-frequency = <0>; /* Filled in by U-Boot */ +- }; +- }; +- +- localbus@f0010100 { +- compatible = "fsl,mpc8247-localbus", +- "fsl,pq2-localbus", +- "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- reg = <0xf0010100 0x40>; +- +- ranges = <0 0 0xfe000000 0x00400000 +- 1 0 0x30000000 0x00010000 +- 2 0 0x40000000 0x00010000 +- 5 0 0x50000000 0x04000000 +- >; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0x0 0x400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- bank-width = <1>; +- device-width = <1>; +- partition@0 { +- label = "u-boot"; +- reg = <0x00000 0xC0000>; +- }; +- partition@1 { +- label = "env"; +- reg = <0xC0000 0x20000>; +- }; +- partition@2 { +- label = "envred"; +- reg = <0xE0000 0x20000>; +- }; +- partition@3 { +- label = "free"; +- reg = <0x100000 0x300000>; +- }; +- }; +- +- flash@5,0 { +- compatible = "cfi-flash"; +- reg = <5 0x00000000 0x02000000 +- 5 0x02000000 0x02000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- bank-width = <2>; +- partition@app { /* 64 MBytes */ +- label = "ubi0"; +- reg = <0x00000000 0x04000000>; +- }; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0 0>; /* Filled in by U-Boot */ +- }; +- +- soc@f0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8247-immr", "fsl,pq2-soc", "simple-bus"; +- ranges = <0x00000000 0xf0000000 0x00053000>; +- +- // Temporary until code stops depending on it. +- device_type = "soc"; +- +- cpm@119c0 { +- #address-cells = <1>; +- #size-cells = <1>; +- #interrupt-cells = <2>; +- compatible = "fsl,mpc8247-cpm", "fsl,cpm2", +- "simple-bus"; +- reg = <0x119c0 0x30>; +- ranges; +- +- muram { +- compatible = "fsl,cpm-muram"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0x10000>; +- +- data@0 { +- compatible = "fsl,cpm-muram-data"; +- reg = <0x80 0x1f80 0x9800 0x800>; +- }; +- }; +- +- brg@119f0 { +- compatible = "fsl,mpc8247-brg", +- "fsl,cpm2-brg", +- "fsl,cpm-brg"; +- reg = <0x119f0 0x10 0x115f0 0x10>; +- }; +- +- /* Monitor port/SMC2 */ +- smc2: serial@11a90 { +- device_type = "serial"; +- compatible = "fsl,mpc8247-smc-uart", +- "fsl,cpm2-smc-uart"; +- reg = <0x11a90 0x20 0x88fc 0x02>; +- interrupts = <5 8>; +- interrupt-parent = <&PIC>; +- fsl,cpm-brg = <2>; +- fsl,cpm-command = <0x21200000>; +- current-speed = <0>; /* Filled in by U-Boot */ +- }; +- +- eth0: ethernet@11a60 { +- device_type = "network"; +- compatible = "fsl,mpc8247-scc-enet", +- "fsl,cpm2-scc-enet"; +- reg = <0x11a60 0x20 0x8300 0x100 0x11390 1>; +- local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by U-Boot */ +- interrupts = <43 8>; +- interrupt-parent = <&PIC>; +- linux,network-index = <0>; +- fsl,cpm-command = <0xce00000>; +- fixed-link = <0 0 10 0 0>; +- }; +- +- i2c@11860 { +- compatible = "fsl,mpc8272-i2c", +- "fsl,cpm2-i2c"; +- reg = <0x11860 0x20 0x8afc 0x2>; +- interrupts = <1 8>; +- interrupt-parent = <&PIC>; +- fsl,cpm-command = <0x29600000>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mdio@10d40 { +- compatible = "fsl,cpm2-mdio-bitbang"; +- reg = <0x10d00 0x14>; +- #address-cells = <1>; +- #size-cells = <0>; +- fsl,mdio-pin = <12>; +- fsl,mdc-pin = <13>; +- +- phy0: ethernet-phy@0 { +- reg = <0x0>; +- }; +- +- phy1: ethernet-phy@1 { +- reg = <0x1>; +- }; +- }; +- +- /* FCC1 management to switch */ +- ethernet@11300 { +- device_type = "network"; +- compatible = "fsl,cpm2-fcc-enet"; +- reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>; +- local-mac-address = [ 00 01 02 03 04 07 ]; +- interrupts = <32 8>; +- interrupt-parent = <&PIC>; +- phy-handle = <&phy0>; +- linux,network-index = <1>; +- fsl,cpm-command = <0x12000300>; +- }; +- +- /* FCC2 to redundant core unit over backplane */ +- ethernet@11320 { +- device_type = "network"; +- compatible = "fsl,cpm2-fcc-enet"; +- reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>; +- local-mac-address = [ 00 01 02 03 04 08 ]; +- interrupts = <33 8>; +- interrupt-parent = <&PIC>; +- phy-handle = <&phy1>; +- linux,network-index = <2>; +- fsl,cpm-command = <0x16200300>; +- }; +- +- usb@11b60 { +- compatible = "fsl,mpc8272-cpm-usb"; +- mode = "peripheral"; +- reg = <0x11b60 0x40 0x8b00 0x100>; +- interrupts = <11 8>; +- interrupt-parent = <&PIC>; +- usb-clock = <5>; +- }; +- spi@11aa0 { +- cell-index = <0>; +- compatible = "fsl,spi", "fsl,cpm2-spi"; +- reg = <0x11a80 0x40 0x89fc 0x2>; +- interrupts = <2 8>; +- interrupt-parent = <&PIC>; +- cs-gpios = < &cpm2_pio_d 19 0>; +- #address-cells = <1>; +- #size-cells = <0>; +- ds3106@1 { +- compatible = "gen,spidev"; +- reg = <0>; +- spi-max-frequency = <8000000>; +- }; +- }; +- +- }; +- +- cpm2_pio_d: gpio-controller@10d60 { +- #gpio-cells = <2>; +- compatible = "fsl,cpm2-pario-bank"; +- reg = <0x10d60 0x14>; +- gpio-controller; +- }; +- +- cpm2_pio_c: gpio-controller@10d40 { +- #gpio-cells = <2>; +- compatible = "fsl,cpm2-pario-bank"; +- reg = <0x10d40 0x14>; +- gpio-controller; +- }; +- +- PIC: interrupt-controller@10c00 { +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0x10c00 0x80>; +- compatible = "fsl,mpc8247-pic", "fsl,pq2-pic"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/microwatt.dts b/scripts/dtc/include-prefixes/powerpc/microwatt.dts +deleted file mode 100644 +index 65b270a90f94..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/microwatt.dts ++++ /dev/null +@@ -1,150 +0,0 @@ +-/dts-v1/; +- +-/ { +- #size-cells = <0x02>; +- #address-cells = <0x02>; +- model-name = "microwatt"; +- compatible = "microwatt-soc"; +- +- aliases { +- serial0 = &UART0; +- }; +- +- reserved-memory { +- #size-cells = <0x02>; +- #address-cells = <0x02>; +- ranges; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000 0x10000000>; +- }; +- +- cpus { +- #size-cells = <0x00>; +- #address-cells = <0x01>; +- +- ibm,powerpc-cpu-features { +- display-name = "Microwatt"; +- isa = <3000>; +- device_type = "cpu-features"; +- compatible = "ibm,powerpc-cpu-features"; +- +- mmu-radix { +- isa = <3000>; +- usable-privilege = <2>; +- }; +- +- little-endian { +- isa = <2050>; +- usable-privilege = <3>; +- hwcap-bit-nr = <1>; +- }; +- +- cache-inhibited-large-page { +- isa = <2040>; +- usable-privilege = <2>; +- }; +- +- fixed-point-v3 { +- isa = <3000>; +- usable-privilege = <3>; +- }; +- +- no-execute { +- isa = <2010>; +- usable-privilege = <2>; +- }; +- +- floating-point { +- hwcap-bit-nr = <27>; +- isa = <0>; +- usable-privilege = <3>; +- }; +- }; +- +- PowerPC,Microwatt@0 { +- i-cache-sets = <2>; +- ibm,dec-bits = <64>; +- reservation-granule-size = <64>; +- clock-frequency = <100000000>; +- timebase-frequency = <100000000>; +- i-tlb-sets = <1>; +- ibm,ppc-interrupt-server#s = <0>; +- i-cache-block-size = <64>; +- d-cache-block-size = <64>; +- d-cache-sets = <2>; +- i-tlb-size = <64>; +- cpu-version = <0x990000>; +- status = "okay"; +- i-cache-size = <0x1000>; +- ibm,processor-radix-AP-encodings = <0x0c 0xa0000010 0x20000015 0x4000001e>; +- tlb-size = <0>; +- tlb-sets = <0>; +- device_type = "cpu"; +- d-tlb-size = <128>; +- d-tlb-sets = <2>; +- reg = <0>; +- general-purpose; +- 64-bit; +- d-cache-size = <0x1000>; +- ibm,chip-id = <0>; +- }; +- }; +- +- soc@c0000000 { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&ICS>; +- +- ranges = <0 0 0xc0000000 0x40000000>; +- +- interrupt-controller@4000 { +- compatible = "openpower,xics-presentation", "ibm,ppc-xicp"; +- ibm,interrupt-server-ranges = <0x0 0x1>; +- reg = <0x4000 0x100>; +- }; +- +- ICS: interrupt-controller@5000 { +- compatible = "openpower,xics-sources"; +- interrupt-controller; +- interrupt-ranges = <0x10 0x10>; +- reg = <0x5000 0x100>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UART0: serial@2000 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0x2000 0x8>; +- clock-frequency = <100000000>; +- current-speed = <115200>; +- reg-shift = <2>; +- fifo-size = <16>; +- interrupts = <0x10 0x1>; +- }; +- +- ethernet@8020000 { +- compatible = "litex,liteeth"; +- reg = <0x8021000 0x100 +- 0x8020800 0x100 +- 0x8030000 0x2000>; +- reg-names = "mac", "mido", "buffer"; +- litex,rx-slots = <2>; +- litex,tx-slots = <2>; +- litex,slot-size = <0x800>; +- interrupts = <0x11 0x1>; +- }; +- }; +- +- chosen { +- bootargs = ""; +- ibm,architecture-vec-5 = [19 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 +- 00 00 00 00 00 00 00 00 40 00 40]; +- stdout-path = &UART0; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/motionpro.dts b/scripts/dtc/include-prefixes/powerpc/motionpro.dts +deleted file mode 100644 +index c23676093da8..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/motionpro.dts ++++ /dev/null +@@ -1,132 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Motion-PRO board Device Tree Source +- * +- * Copyright (C) 2007 Semihalf +- * Marian Balakowicz +- */ +- +-/include/ "mpc5200b.dtsi" +- +-&gpt0 { fsl,has-wdt; }; +-&gpt6 { // Motion-PRO status LED +- compatible = "promess,motionpro-led"; +- label = "motionpro-statusled"; +- blink-delay = <100>; // 100 msec +-}; +-&gpt7 { // Motion-PRO ready LED +- compatible = "promess,motionpro-led"; +- label = "motionpro-readyled"; +-}; +- +-/ { +- model = "promess,motionpro"; +- compatible = "promess,motionpro"; +- +- soc5200@f0000000 { +- can@900 { +- status = "disabled"; +- }; +- +- psc@2000 { // PSC1 +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- // PSC2 in spi master mode +- psc@2200 { // PSC2 +- compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; +- cell-index = <1>; +- }; +- +- psc@2400 { // PSC3 +- status = "disabled"; +- }; +- +- psc@2600 { // PSC4 +- status = "disabled"; +- }; +- +- psc@2800 { // PSC5 +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- psc@2c00 { // PSC6 +- status = "disabled"; +- }; +- +- ethernet@3000 { +- phy-handle = <&phy0>; +- }; +- +- mdio@3000 { +- phy0: ethernet-phy@2 { +- reg = <2>; +- }; +- }; +- +- i2c@3d00 { +- status = "disabled"; +- }; +- +- i2c@3d40 { +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +- }; +- +- sram@8000 { +- compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; +- reg = <0x8000 0x4000>; +- }; +- }; +- +- pci@f0000d00 { +- status = "disabled"; +- }; +- +- localbus { +- ranges = <0 0 0xff000000 0x01000000 +- 1 0 0x50000000 0x00010000 +- 2 0 0x50010000 0x00010000 +- 3 0 0x50020000 0x00010000>; +- +- // 8-bit DualPort SRAM on LocalPlus Bus CS1 +- kollmorgen@1,0 { +- compatible = "promess,motionpro-kollmorgen"; +- reg = <1 0 0x10000>; +- interrupts = <1 1 0>; +- }; +- +- // 8-bit board CPLD on LocalPlus Bus CS2 +- cpld@2,0 { +- compatible = "promess,motionpro-cpld"; +- reg = <2 0 0x10000>; +- }; +- +- // 8-bit custom Anybus Module on LocalPlus Bus CS3 +- anybus@3,0 { +- compatible = "promess,motionpro-anybus"; +- reg = <3 0 0x10000>; +- }; +- pro_module_general@3,0 { +- compatible = "promess,pro_module_general"; +- reg = <3 0 3>; +- }; +- pro_module_dio@3,800 { +- compatible = "promess,pro_module_dio"; +- reg = <3 0x800 2>; +- }; +- +- // 16-bit flash device at LocalPlus Bus CS0 +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x01000000>; +- bank-width = <2>; +- device-width = <2>; +- #size-cells = <1>; +- #address-cells = <1>; +- }; +- +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc5121.dtsi b/scripts/dtc/include-prefixes/powerpc/mpc5121.dtsi +deleted file mode 100644 +index 3f66b91a8e3c..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc5121.dtsi ++++ /dev/null +@@ -1,526 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * base MPC5121 Device Tree Source +- * +- * Copyright 2007-2008 Freescale Semiconductor Inc. +- */ +- +-#include +- +-/dts-v1/; +- +-/ { +- model = "mpc5121"; +- compatible = "fsl,mpc5121"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&ipic>; +- +- aliases { +- ethernet0 = ð0; +- pci = &pci; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,5121@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <0x20>; /* 32 bytes */ +- i-cache-line-size = <0x20>; /* 32 bytes */ +- d-cache-size = <0x8000>; /* L1, 32K */ +- i-cache-size = <0x8000>; /* L1, 32K */ +- timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */ +- bus-frequency = <198000000>; /* 198 MHz csb bus */ +- clock-frequency = <396000000>; /* 396 MHz ppc core */ +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; /* 256MB at 0 */ +- }; +- +- mbx@20000000 { +- compatible = "fsl,mpc5121-mbx"; +- reg = <0x20000000 0x4000>; +- interrupts = <66 0x8>; +- clocks = <&clks MPC512x_CLK_MBX_BUS>, +- <&clks MPC512x_CLK_MBX_3D>, +- <&clks MPC512x_CLK_MBX>; +- clock-names = "mbx-bus", "mbx-3d", "mbx"; +- }; +- +- sram@30000000 { +- compatible = "fsl,mpc5121-sram"; +- reg = <0x30000000 0x20000>; /* 128K at 0x30000000 */ +- }; +- +- nfc@40000000 { +- compatible = "fsl,mpc5121-nfc"; +- reg = <0x40000000 0x100000>; /* 1M at 0x40000000 */ +- interrupts = <6 8>; +- #address-cells = <1>; +- #size-cells = <1>; +- clocks = <&clks MPC512x_CLK_NFC>; +- clock-names = "ipg"; +- }; +- +- localbus@80000020 { +- compatible = "fsl,mpc5121-localbus"; +- #address-cells = <2>; +- #size-cells = <1>; +- reg = <0x80000020 0x40>; +- ranges = <0x0 0x0 0xfc000000 0x04000000>; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- osc: osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <33000000>; +- }; +- }; +- +- soc@80000000 { +- compatible = "fsl,mpc5121-immr"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x80000000 0x400000>; +- reg = <0x80000000 0x400000>; +- bus-frequency = <66000000>; /* 66 MHz ips bus */ +- +- +- /* +- * IPIC +- * interrupts cell = +- * sense values match linux IORESOURCE_IRQ_* defines: +- * sense == 8: Level, low assertion +- * sense == 2: Edge, high-to-low change +- */ +- ipic: interrupt-controller@c00 { +- compatible = "fsl,mpc5121-ipic", "fsl,ipic"; +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0xc00 0x100>; +- }; +- +- /* Watchdog timer */ +- wdt@900 { +- compatible = "fsl,mpc5121-wdt"; +- reg = <0x900 0x100>; +- }; +- +- /* Real time clock */ +- rtc@a00 { +- compatible = "fsl,mpc5121-rtc"; +- reg = <0xa00 0x100>; +- interrupts = <79 0x8 80 0x8>; +- }; +- +- /* Reset module */ +- reset@e00 { +- compatible = "fsl,mpc5121-reset"; +- reg = <0xe00 0x100>; +- }; +- +- /* Clock control */ +- clks: clock@f00 { +- compatible = "fsl,mpc5121-clock"; +- reg = <0xf00 0x100>; +- #clock-cells = <1>; +- clocks = <&osc>; +- clock-names = "osc"; +- }; +- +- /* Power Management Controller */ +- pmc@1000{ +- compatible = "fsl,mpc5121-pmc"; +- reg = <0x1000 0x100>; +- interrupts = <83 0x8>; +- }; +- +- gpio@1100 { +- compatible = "fsl,mpc5121-gpio"; +- reg = <0x1100 0x100>; +- interrupts = <78 0x8>; +- }; +- +- can@1300 { +- compatible = "fsl,mpc5121-mscan"; +- reg = <0x1300 0x80>; +- interrupts = <12 0x8>; +- clocks = <&clks MPC512x_CLK_BDLC>, +- <&clks MPC512x_CLK_IPS>, +- <&clks MPC512x_CLK_SYS>, +- <&clks MPC512x_CLK_REF>, +- <&clks MPC512x_CLK_MSCAN0_MCLK>; +- clock-names = "ipg", "ips", "sys", "ref", "mclk"; +- }; +- +- can@1380 { +- compatible = "fsl,mpc5121-mscan"; +- reg = <0x1380 0x80>; +- interrupts = <13 0x8>; +- clocks = <&clks MPC512x_CLK_BDLC>, +- <&clks MPC512x_CLK_IPS>, +- <&clks MPC512x_CLK_SYS>, +- <&clks MPC512x_CLK_REF>, +- <&clks MPC512x_CLK_MSCAN1_MCLK>; +- clock-names = "ipg", "ips", "sys", "ref", "mclk"; +- }; +- +- sdhc@1500 { +- compatible = "fsl,mpc5121-sdhc"; +- reg = <0x1500 0x100>; +- interrupts = <8 0x8>; +- dmas = <&dma0 30>; +- dma-names = "rx-tx"; +- clocks = <&clks MPC512x_CLK_IPS>, +- <&clks MPC512x_CLK_SDHC>; +- clock-names = "ipg", "per"; +- }; +- +- i2c@1700 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc5121-i2c", "fsl-i2c"; +- reg = <0x1700 0x20>; +- interrupts = <9 0x8>; +- clocks = <&clks MPC512x_CLK_I2C>; +- clock-names = "ipg"; +- }; +- +- i2c@1720 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc5121-i2c", "fsl-i2c"; +- reg = <0x1720 0x20>; +- interrupts = <10 0x8>; +- clocks = <&clks MPC512x_CLK_I2C>; +- clock-names = "ipg"; +- }; +- +- i2c@1740 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc5121-i2c", "fsl-i2c"; +- reg = <0x1740 0x20>; +- interrupts = <11 0x8>; +- clocks = <&clks MPC512x_CLK_I2C>; +- clock-names = "ipg"; +- }; +- +- i2ccontrol@1760 { +- compatible = "fsl,mpc5121-i2c-ctrl"; +- reg = <0x1760 0x8>; +- }; +- +- axe@2000 { +- compatible = "fsl,mpc5121-axe"; +- reg = <0x2000 0x100>; +- interrupts = <42 0x8>; +- clocks = <&clks MPC512x_CLK_AXE>; +- clock-names = "ipg"; +- }; +- +- display@2100 { +- compatible = "fsl,mpc5121-diu"; +- reg = <0x2100 0x100>; +- interrupts = <64 0x8>; +- clocks = <&clks MPC512x_CLK_DIU>; +- clock-names = "ipg"; +- }; +- +- can@2300 { +- compatible = "fsl,mpc5121-mscan"; +- reg = <0x2300 0x80>; +- interrupts = <90 0x8>; +- clocks = <&clks MPC512x_CLK_BDLC>, +- <&clks MPC512x_CLK_IPS>, +- <&clks MPC512x_CLK_SYS>, +- <&clks MPC512x_CLK_REF>, +- <&clks MPC512x_CLK_MSCAN2_MCLK>; +- clock-names = "ipg", "ips", "sys", "ref", "mclk"; +- }; +- +- can@2380 { +- compatible = "fsl,mpc5121-mscan"; +- reg = <0x2380 0x80>; +- interrupts = <91 0x8>; +- clocks = <&clks MPC512x_CLK_BDLC>, +- <&clks MPC512x_CLK_IPS>, +- <&clks MPC512x_CLK_SYS>, +- <&clks MPC512x_CLK_REF>, +- <&clks MPC512x_CLK_MSCAN3_MCLK>; +- clock-names = "ipg", "ips", "sys", "ref", "mclk"; +- }; +- +- viu@2400 { +- compatible = "fsl,mpc5121-viu"; +- reg = <0x2400 0x400>; +- interrupts = <67 0x8>; +- clocks = <&clks MPC512x_CLK_VIU>; +- clock-names = "ipg"; +- }; +- +- mdio@2800 { +- compatible = "fsl,mpc5121-fec-mdio"; +- reg = <0x2800 0x800>; +- #address-cells = <1>; +- #size-cells = <0>; +- clocks = <&clks MPC512x_CLK_FEC>; +- clock-names = "per"; +- }; +- +- eth0: ethernet@2800 { +- device_type = "network"; +- compatible = "fsl,mpc5121-fec"; +- reg = <0x2800 0x800>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <4 0x8>; +- clocks = <&clks MPC512x_CLK_FEC>; +- clock-names = "per"; +- }; +- +- /* USB1 using external ULPI PHY */ +- usb@3000 { +- compatible = "fsl,mpc5121-usb2-dr"; +- reg = <0x3000 0x600>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <43 0x8>; +- dr_mode = "otg"; +- phy_type = "ulpi"; +- clocks = <&clks MPC512x_CLK_USB1>; +- clock-names = "ipg"; +- }; +- +- /* USB0 using internal UTMI PHY */ +- usb@4000 { +- compatible = "fsl,mpc5121-usb2-dr"; +- reg = <0x4000 0x600>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <44 0x8>; +- dr_mode = "otg"; +- phy_type = "utmi_wide"; +- clocks = <&clks MPC512x_CLK_USB2>; +- clock-names = "ipg"; +- }; +- +- /* IO control */ +- ioctl@a000 { +- compatible = "fsl,mpc5121-ioctl"; +- reg = <0xA000 0x1000>; +- }; +- +- /* LocalPlus controller */ +- lpc@10000 { +- compatible = "fsl,mpc5121-lpc"; +- reg = <0x10000 0x100>; +- }; +- +- sclpc@10100 { +- compatible = "fsl,mpc512x-lpbfifo"; +- reg = <0x10100 0x50>; +- interrupts = <7 0x8>; +- dmas = <&dma0 26>; +- dma-names = "rx-tx"; +- }; +- +- pata@10200 { +- compatible = "fsl,mpc5121-pata"; +- reg = <0x10200 0x100>; +- interrupts = <5 0x8>; +- clocks = <&clks MPC512x_CLK_PATA>; +- clock-names = "ipg"; +- }; +- +- /* 512x PSCs are not 52xx PSC compatible */ +- +- /* PSC0 */ +- psc@11000 { +- compatible = "fsl,mpc5121-psc"; +- reg = <0x11000 0x100>; +- interrupts = <40 0x8>; +- fsl,rx-fifo-size = <16>; +- fsl,tx-fifo-size = <16>; +- clocks = <&clks MPC512x_CLK_PSC0>, +- <&clks MPC512x_CLK_PSC0_MCLK>; +- clock-names = "ipg", "mclk"; +- }; +- +- /* PSC1 */ +- psc@11100 { +- compatible = "fsl,mpc5121-psc"; +- reg = <0x11100 0x100>; +- interrupts = <40 0x8>; +- fsl,rx-fifo-size = <16>; +- fsl,tx-fifo-size = <16>; +- clocks = <&clks MPC512x_CLK_PSC1>, +- <&clks MPC512x_CLK_PSC1_MCLK>; +- clock-names = "ipg", "mclk"; +- }; +- +- /* PSC2 */ +- psc@11200 { +- compatible = "fsl,mpc5121-psc"; +- reg = <0x11200 0x100>; +- interrupts = <40 0x8>; +- fsl,rx-fifo-size = <16>; +- fsl,tx-fifo-size = <16>; +- clocks = <&clks MPC512x_CLK_PSC2>, +- <&clks MPC512x_CLK_PSC2_MCLK>; +- clock-names = "ipg", "mclk"; +- }; +- +- /* PSC3 */ +- psc@11300 { +- compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; +- reg = <0x11300 0x100>; +- interrupts = <40 0x8>; +- fsl,rx-fifo-size = <16>; +- fsl,tx-fifo-size = <16>; +- clocks = <&clks MPC512x_CLK_PSC3>, +- <&clks MPC512x_CLK_PSC3_MCLK>; +- clock-names = "ipg", "mclk"; +- }; +- +- /* PSC4 */ +- psc@11400 { +- compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; +- reg = <0x11400 0x100>; +- interrupts = <40 0x8>; +- fsl,rx-fifo-size = <16>; +- fsl,tx-fifo-size = <16>; +- clocks = <&clks MPC512x_CLK_PSC4>, +- <&clks MPC512x_CLK_PSC4_MCLK>; +- clock-names = "ipg", "mclk"; +- }; +- +- /* PSC5 */ +- psc@11500 { +- compatible = "fsl,mpc5121-psc"; +- reg = <0x11500 0x100>; +- interrupts = <40 0x8>; +- fsl,rx-fifo-size = <16>; +- fsl,tx-fifo-size = <16>; +- clocks = <&clks MPC512x_CLK_PSC5>, +- <&clks MPC512x_CLK_PSC5_MCLK>; +- clock-names = "ipg", "mclk"; +- }; +- +- /* PSC6 */ +- psc@11600 { +- compatible = "fsl,mpc5121-psc"; +- reg = <0x11600 0x100>; +- interrupts = <40 0x8>; +- fsl,rx-fifo-size = <16>; +- fsl,tx-fifo-size = <16>; +- clocks = <&clks MPC512x_CLK_PSC6>, +- <&clks MPC512x_CLK_PSC6_MCLK>; +- clock-names = "ipg", "mclk"; +- }; +- +- /* PSC7 */ +- psc@11700 { +- compatible = "fsl,mpc5121-psc"; +- reg = <0x11700 0x100>; +- interrupts = <40 0x8>; +- fsl,rx-fifo-size = <16>; +- fsl,tx-fifo-size = <16>; +- clocks = <&clks MPC512x_CLK_PSC7>, +- <&clks MPC512x_CLK_PSC7_MCLK>; +- clock-names = "ipg", "mclk"; +- }; +- +- /* PSC8 */ +- psc@11800 { +- compatible = "fsl,mpc5121-psc"; +- reg = <0x11800 0x100>; +- interrupts = <40 0x8>; +- fsl,rx-fifo-size = <16>; +- fsl,tx-fifo-size = <16>; +- clocks = <&clks MPC512x_CLK_PSC8>, +- <&clks MPC512x_CLK_PSC8_MCLK>; +- clock-names = "ipg", "mclk"; +- }; +- +- /* PSC9 */ +- psc@11900 { +- compatible = "fsl,mpc5121-psc"; +- reg = <0x11900 0x100>; +- interrupts = <40 0x8>; +- fsl,rx-fifo-size = <16>; +- fsl,tx-fifo-size = <16>; +- clocks = <&clks MPC512x_CLK_PSC9>, +- <&clks MPC512x_CLK_PSC9_MCLK>; +- clock-names = "ipg", "mclk"; +- }; +- +- /* PSC10 */ +- psc@11a00 { +- compatible = "fsl,mpc5121-psc"; +- reg = <0x11a00 0x100>; +- interrupts = <40 0x8>; +- fsl,rx-fifo-size = <16>; +- fsl,tx-fifo-size = <16>; +- clocks = <&clks MPC512x_CLK_PSC10>, +- <&clks MPC512x_CLK_PSC10_MCLK>; +- clock-names = "ipg", "mclk"; +- }; +- +- /* PSC11 */ +- psc@11b00 { +- compatible = "fsl,mpc5121-psc"; +- reg = <0x11b00 0x100>; +- interrupts = <40 0x8>; +- fsl,rx-fifo-size = <16>; +- fsl,tx-fifo-size = <16>; +- clocks = <&clks MPC512x_CLK_PSC11>, +- <&clks MPC512x_CLK_PSC11_MCLK>; +- clock-names = "ipg", "mclk"; +- }; +- +- pscfifo@11f00 { +- compatible = "fsl,mpc5121-psc-fifo"; +- reg = <0x11f00 0x100>; +- interrupts = <40 0x8>; +- clocks = <&clks MPC512x_CLK_PSC_FIFO>; +- clock-names = "ipg"; +- }; +- +- dma0: dma@14000 { +- compatible = "fsl,mpc5121-dma"; +- reg = <0x14000 0x1800>; +- interrupts = <65 0x8>; +- #dma-cells = <1>; +- }; +- }; +- +- pci: pci@80008500 { +- compatible = "fsl,mpc5121-pci"; +- device_type = "pci"; +- interrupts = <1 0x8>; +- clock-frequency = <0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- clocks = <&clks MPC512x_CLK_PCI>; +- clock-names = "ipg"; +- +- reg = <0x80008500 0x100 /* internal registers */ +- 0x80008300 0x8>; /* config space access registers */ +- bus-range = <0x0 0x0>; +- ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 +- 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc5121ads.dts b/scripts/dtc/include-prefixes/powerpc/mpc5121ads.dts +deleted file mode 100644 +index b407a50ee622..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc5121ads.dts ++++ /dev/null +@@ -1,174 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC5121E ADS Device Tree Source +- * +- * Copyright 2007-2008 Freescale Semiconductor Inc. +- */ +- +-#include "mpc5121.dtsi" +- +-/ { +- model = "mpc5121ads"; +- compatible = "fsl,mpc5121ads", "fsl,mpc5121"; +- +- nfc@40000000 { +- /* +- * ADS has two Hynix 512MB Nand flash chips in a single +- * stacked package. +- */ +- chips = <2>; +- +- nand@0 { +- label = "nand"; +- reg = <0x00000000 0x40000000>; /* 512MB + 512MB */ +- }; +- }; +- +- localbus@80000020 { +- ranges = <0x0 0x0 0xfc000000 0x04000000 +- 0x2 0x0 0x82000000 0x00008000>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0x0 0x4000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- bank-width = <4>; +- device-width = <2>; +- +- protected@0 { +- label = "protected"; +- reg = <0x00000000 0x00040000>; // first sector is protected +- read-only; +- }; +- filesystem@40000 { +- label = "filesystem"; +- reg = <0x00040000 0x03c00000>; // 60M for filesystem +- }; +- kernel@3c40000 { +- label = "kernel"; +- reg = <0x03c40000 0x00280000>; // 2.5M for kernel +- }; +- device-tree@3ec0000 { +- label = "device-tree"; +- reg = <0x03ec0000 0x00040000>; // one sector for device tree +- }; +- u-boot@3f00000 { +- label = "u-boot"; +- reg = <0x03f00000 0x00100000>; // 1M for u-boot +- read-only; +- }; +- }; +- +- board-control@2,0 { +- compatible = "fsl,mpc5121ads-cpld"; +- reg = <0x2 0x0 0x8000>; +- }; +- +- cpld_pic: pic@2,a { +- compatible = "fsl,mpc5121ads-cpld-pic"; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x2 0xa 0x5>; +- /* irq routing: +- * all irqs but touch screen are routed to irq0 (ipic 48) +- * touch screen is statically routed to irq1 (ipic 17) +- * so don't use it here +- */ +- interrupts = <48 0x8>; +- }; +- }; +- +- soc@80000000 { +- +- i2c@1700 { +- fsl,preserve-clocking; +- +- hwmon@4a { +- compatible = "adi,ad7414"; +- reg = <0x4a>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c32"; +- reg = <0x50>; +- }; +- +- rtc@68 { +- compatible = "st,m41t62"; +- reg = <0x68>; +- }; +- }; +- +- eth0: ethernet@2800 { +- phy-handle = <&phy0>; +- }; +- +- can@2300 { +- status = "disabled"; +- }; +- +- can@2380 { +- status = "disabled"; +- }; +- +- viu@2400 { +- status = "disabled"; +- }; +- +- mdio@2800 { +- phy0: ethernet-phy@0 { +- reg = <1>; +- }; +- }; +- +- /* mpc5121ads only uses USB0 */ +- usb@3000 { +- status = "disabled"; +- }; +- +- /* USB0 using internal UTMI PHY */ +- usb@4000 { +- dr_mode = "host"; +- fsl,invert-drvvbus; +- fsl,invert-pwr-fault; +- }; +- +- /* PSC3 serial port A aka ttyPSC0 */ +- psc@11300 { +- compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; +- }; +- +- /* PSC4 serial port B aka ttyPSC1 */ +- psc@11400 { +- compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; +- }; +- +- /* PSC5 in ac97 mode */ +- ac97: psc@11500 { +- compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc"; +- fsl,mode = "ac97-slave"; +- fsl,rx-fifo-size = <384>; +- fsl,tx-fifo-size = <384>; +- }; +- }; +- +- pci: pci@80008500 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x15 - Slot 1 PCI */ +- 0xa800 0x0 0x0 0x1 &cpld_pic 0x0 0x8 +- 0xa800 0x0 0x0 0x2 &cpld_pic 0x1 0x8 +- 0xa800 0x0 0x0 0x3 &cpld_pic 0x2 0x8 +- 0xa800 0x0 0x0 0x4 &cpld_pic 0x3 0x8 +- +- /* IDSEL 0x16 - Slot 2 MiniPCI */ +- 0xb000 0x0 0x0 0x1 &cpld_pic 0x4 0x8 +- 0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8 +- +- /* IDSEL 0x17 - Slot 3 MiniPCI */ +- 0xb800 0x0 0x0 0x1 &cpld_pic 0x6 0x8 +- 0xb800 0x0 0x0 0x2 &cpld_pic 0x7 0x8 +- >; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc5125twr.dts b/scripts/dtc/include-prefixes/powerpc/mpc5125twr.dts +deleted file mode 100644 +index 0bd2acc0401d..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc5125twr.dts ++++ /dev/null +@@ -1,293 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * STx/Freescale ADS5125 MPC5125 silicon +- * +- * Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved. +- * +- * Reworked by Matteo Facchinetti (engineering@sirius-es.it) +- * Copyright (C) 2013 Sirius Electronic Systems +- */ +- +-#include +- +-/dts-v1/; +- +-/ { +- model = "mpc5125twr"; // In BSP "mpc5125ads" +- compatible = "fsl,mpc5125ads", "fsl,mpc5125"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&ipic>; +- +- aliases { +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- ethernet0 = ð0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,5125@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <0x20>; // 32 bytes +- i-cache-line-size = <0x20>; // 32 bytes +- d-cache-size = <0x8000>; // L1, 32K +- i-cache-size = <0x8000>; // L1, 32K +- timebase-frequency = <49500000>;// 49.5 MHz (csb/4) +- bus-frequency = <198000000>; // 198 MHz csb bus +- clock-frequency = <396000000>; // 396 MHz ppc core +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; // 256MB at 0 +- }; +- +- sram@30000000 { +- compatible = "fsl,mpc5121-sram"; +- reg = <0x30000000 0x08000>; // 32K at 0x30000000 +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <0>; +- +- osc: osc { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <33000000>; +- }; +- }; +- +- soc@80000000 { +- compatible = "fsl,mpc5121-immr"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x80000000 0x400000>; +- reg = <0x80000000 0x400000>; +- bus-frequency = <66000000>; // 66 MHz ips bus +- +- // IPIC +- // interrupts cell = +- // sense values match linux IORESOURCE_IRQ_* defines: +- // sense == 8: Level, low assertion +- // sense == 2: Edge, high-to-low change +- // +- ipic: interrupt-controller@c00 { +- compatible = "fsl,mpc5121-ipic", "fsl,ipic"; +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0xc00 0x100>; +- }; +- +- rtc@a00 { // Real time clock +- compatible = "fsl,mpc5121-rtc"; +- reg = <0xa00 0x100>; +- interrupts = <79 0x8 80 0x8>; +- }; +- +- reset@e00 { // Reset module +- compatible = "fsl,mpc5125-reset"; +- reg = <0xe00 0x100>; +- }; +- +- clks: clock@f00 { // Clock control +- compatible = "fsl,mpc5121-clock"; +- reg = <0xf00 0x100>; +- #clock-cells = <1>; +- clocks = <&osc>; +- clock-names = "osc"; +- }; +- +- pmc@1000{ // Power Management Controller +- compatible = "fsl,mpc5121-pmc"; +- reg = <0x1000 0x100>; +- interrupts = <83 0x2>; +- }; +- +- gpio0: gpio@1100 { +- compatible = "fsl,mpc5125-gpio"; +- reg = <0x1100 0x080>; +- interrupts = <78 0x8>; +- }; +- +- gpio1: gpio@1180 { +- compatible = "fsl,mpc5125-gpio"; +- reg = <0x1180 0x080>; +- interrupts = <86 0x8>; +- }; +- +- can@1300 { // CAN rev.2 +- compatible = "fsl,mpc5121-mscan"; +- interrupts = <12 0x8>; +- reg = <0x1300 0x80>; +- clocks = <&clks MPC512x_CLK_BDLC>, +- <&clks MPC512x_CLK_IPS>, +- <&clks MPC512x_CLK_SYS>, +- <&clks MPC512x_CLK_REF>, +- <&clks MPC512x_CLK_MSCAN0_MCLK>; +- clock-names = "ipg", "ips", "sys", "ref", "mclk"; +- }; +- +- can@1380 { +- compatible = "fsl,mpc5121-mscan"; +- interrupts = <13 0x8>; +- reg = <0x1380 0x80>; +- clocks = <&clks MPC512x_CLK_BDLC>, +- <&clks MPC512x_CLK_IPS>, +- <&clks MPC512x_CLK_SYS>, +- <&clks MPC512x_CLK_REF>, +- <&clks MPC512x_CLK_MSCAN1_MCLK>; +- clock-names = "ipg", "ips", "sys", "ref", "mclk"; +- }; +- +- sdhc@1500 { +- compatible = "fsl,mpc5121-sdhc"; +- interrupts = <8 0x8>; +- reg = <0x1500 0x100>; +- clocks = <&clks MPC512x_CLK_IPS>, +- <&clks MPC512x_CLK_SDHC>; +- clock-names = "ipg", "per"; +- }; +- +- i2c@1700 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc5121-i2c", "fsl-i2c"; +- reg = <0x1700 0x20>; +- interrupts = <0x9 0x8>; +- clocks = <&clks MPC512x_CLK_I2C>; +- clock-names = "ipg"; +- }; +- +- i2c@1720 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc5121-i2c", "fsl-i2c"; +- reg = <0x1720 0x20>; +- interrupts = <0xa 0x8>; +- clocks = <&clks MPC512x_CLK_I2C>; +- clock-names = "ipg"; +- }; +- +- i2c@1740 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc5121-i2c", "fsl-i2c"; +- reg = <0x1740 0x20>; +- interrupts = <0xb 0x8>; +- clocks = <&clks MPC512x_CLK_I2C>; +- clock-names = "ipg"; +- }; +- +- i2ccontrol@1760 { +- compatible = "fsl,mpc5121-i2c-ctrl"; +- reg = <0x1760 0x8>; +- }; +- +- diu@2100 { +- compatible = "fsl,mpc5121-diu"; +- reg = <0x2100 0x100>; +- interrupts = <64 0x8>; +- clocks = <&clks MPC512x_CLK_DIU>; +- clock-names = "ipg"; +- }; +- +- mdio@2800 { +- compatible = "fsl,mpc5121-fec-mdio"; +- reg = <0x2800 0x800>; +- #address-cells = <1>; +- #size-cells = <0>; +- phy0: ethernet-phy@0 { +- reg = <1>; +- }; +- }; +- +- eth0: ethernet@2800 { +- compatible = "fsl,mpc5125-fec"; +- reg = <0x2800 0x800>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <4 0x8>; +- phy-handle = < &phy0 >; +- phy-connection-type = "rmii"; +- clocks = <&clks MPC512x_CLK_FEC>; +- clock-names = "per"; +- }; +- +- // IO control +- ioctl@a000 { +- compatible = "fsl,mpc5125-ioctl"; +- reg = <0xA000 0x1000>; +- }; +- +- // disable USB1 port +- // TODO: +- // correct pinmux config and fix USB3320 ulpi dependency +- // before re-enabling it +- usb@3000 { +- compatible = "fsl,mpc5121-usb2-dr"; +- reg = <0x3000 0x400>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <43 0x8>; +- dr_mode = "host"; +- phy_type = "ulpi"; +- clocks = <&clks MPC512x_CLK_USB1>; +- clock-names = "ipg"; +- status = "disabled"; +- }; +- +- sclpc@10100 { +- compatible = "fsl,mpc512x-lpbfifo"; +- reg = <0x10100 0x50>; +- interrupts = <7 0x8>; +- dmas = <&dma0 26>; +- dma-names = "rx-tx"; +- }; +- +- // 5125 PSCs are not 52xx or 5121 PSC compatible +- // PSC1 uart0 aka ttyPSC0 +- serial@11100 { +- compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc"; +- reg = <0x11100 0x100>; +- interrupts = <40 0x8>; +- fsl,rx-fifo-size = <16>; +- fsl,tx-fifo-size = <16>; +- clocks = <&clks MPC512x_CLK_PSC1>, +- <&clks MPC512x_CLK_PSC1_MCLK>; +- clock-names = "ipg", "mclk"; +- }; +- +- // PSC9 uart1 aka ttyPSC1 +- serial@11900 { +- compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc"; +- reg = <0x11900 0x100>; +- interrupts = <40 0x8>; +- fsl,rx-fifo-size = <16>; +- fsl,tx-fifo-size = <16>; +- clocks = <&clks MPC512x_CLK_PSC9>, +- <&clks MPC512x_CLK_PSC9_MCLK>; +- clock-names = "ipg", "mclk"; +- }; +- +- pscfifo@11f00 { +- compatible = "fsl,mpc5121-psc-fifo"; +- reg = <0x11f00 0x100>; +- interrupts = <40 0x8>; +- clocks = <&clks MPC512x_CLK_PSC_FIFO>; +- clock-names = "ipg"; +- }; +- +- dma0: dma@14000 { +- compatible = "fsl,mpc5121-dma"; // BSP name: "mpc512x-dma2" +- reg = <0x14000 0x1800>; +- interrupts = <65 0x8>; +- #dma-cells = <1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc5200b.dtsi b/scripts/dtc/include-prefixes/powerpc/mpc5200b.dtsi +deleted file mode 100644 +index 8b796f3b11da..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc5200b.dtsi ++++ /dev/null +@@ -1,288 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * base MPC5200b Device Tree Source +- * +- * Copyright (C) 2010 SecretLab +- * Grant Likely +- * John Bonesio +- */ +- +-/dts-v1/; +- +-/ { +- model = "fsl,mpc5200b"; +- compatible = "fsl,mpc5200b"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&mpc5200_pic>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- powerpc: PowerPC,5200@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <0x4000>; // L1, 16K +- i-cache-size = <0x4000>; // L1, 16K +- timebase-frequency = <0>; // from bootloader +- bus-frequency = <0>; // from bootloader +- clock-frequency = <0>; // from bootloader +- }; +- }; +- +- memory: memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x04000000>; // 64MB +- }; +- +- soc: soc5200@f0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc5200b-immr"; +- ranges = <0 0xf0000000 0x0000c000>; +- reg = <0xf0000000 0x00000100>; +- bus-frequency = <0>; // from bootloader +- system-frequency = <0>; // from bootloader +- +- cdm@200 { +- compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; +- reg = <0x200 0x38>; +- }; +- +- mpc5200_pic: interrupt-controller@500 { +- // 5200 interrupts are encoded into two levels; +- interrupt-controller; +- #interrupt-cells = <3>; +- compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; +- reg = <0x500 0x80>; +- }; +- +- gpt0: timer@600 { // General Purpose Timer +- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; +- #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode +- reg = <0x600 0x10>; +- interrupts = <1 9 0>; +- // add 'fsl,has-wdt' to enable watchdog +- }; +- +- gpt1: timer@610 { // General Purpose Timer +- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; +- #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode +- reg = <0x610 0x10>; +- interrupts = <1 10 0>; +- }; +- +- gpt2: timer@620 { // General Purpose Timer +- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; +- #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode +- reg = <0x620 0x10>; +- interrupts = <1 11 0>; +- }; +- +- gpt3: timer@630 { // General Purpose Timer +- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; +- #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode +- reg = <0x630 0x10>; +- interrupts = <1 12 0>; +- }; +- +- gpt4: timer@640 { // General Purpose Timer +- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; +- #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode +- reg = <0x640 0x10>; +- interrupts = <1 13 0>; +- }; +- +- gpt5: timer@650 { // General Purpose Timer +- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; +- #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode +- reg = <0x650 0x10>; +- interrupts = <1 14 0>; +- }; +- +- gpt6: timer@660 { // General Purpose Timer +- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; +- #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode +- reg = <0x660 0x10>; +- interrupts = <1 15 0>; +- }; +- +- gpt7: timer@670 { // General Purpose Timer +- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; +- #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode +- reg = <0x670 0x10>; +- interrupts = <1 16 0>; +- }; +- +- rtc@800 { // Real time clock +- compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; +- reg = <0x800 0x100>; +- interrupts = <1 5 0 1 6 0>; +- }; +- +- can@900 { +- compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; +- interrupts = <2 17 0>; +- reg = <0x900 0x80>; +- }; +- +- can@980 { +- compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; +- interrupts = <2 18 0>; +- reg = <0x980 0x80>; +- }; +- +- gpio_simple: gpio@b00 { +- compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; +- reg = <0xb00 0x40>; +- interrupts = <1 7 0>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- gpio_wkup: gpio@c00 { +- compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; +- reg = <0xc00 0x40>; +- interrupts = <1 8 0 0 3 0>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- spi@f00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; +- reg = <0xf00 0x20>; +- interrupts = <2 13 0 2 14 0>; +- }; +- +- usb: usb@1000 { +- compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; +- reg = <0x1000 0xff>; +- interrupts = <2 6 0>; +- }; +- +- dma-controller@1200 { +- compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; +- reg = <0x1200 0x80>; +- interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 +- 3 4 0 3 5 0 3 6 0 3 7 0 +- 3 8 0 3 9 0 3 10 0 3 11 0 +- 3 12 0 3 13 0 3 14 0 3 15 0>; +- }; +- +- xlb@1f00 { +- compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; +- reg = <0x1f00 0x100>; +- }; +- +- psc1: psc@2000 { // PSC1 +- compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc"; +- reg = <0x2000 0x100>; +- interrupts = <2 1 0>; +- }; +- +- psc2: psc@2200 { // PSC2 +- compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc"; +- reg = <0x2200 0x100>; +- interrupts = <2 2 0>; +- }; +- +- psc3: psc@2400 { // PSC3 +- compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc"; +- reg = <0x2400 0x100>; +- interrupts = <2 3 0>; +- }; +- +- psc4: psc@2600 { // PSC4 +- compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc"; +- reg = <0x2600 0x100>; +- interrupts = <2 11 0>; +- }; +- +- psc5: psc@2800 { // PSC5 +- compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc"; +- reg = <0x2800 0x100>; +- interrupts = <2 12 0>; +- }; +- +- psc6: psc@2c00 { // PSC6 +- compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc"; +- reg = <0x2c00 0x100>; +- interrupts = <2 4 0>; +- }; +- +- eth0: ethernet@3000 { +- compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; +- reg = <0x3000 0x400>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <2 5 0>; +- }; +- +- mdio@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; +- reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts +- interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. +- }; +- +- ata@3a00 { +- compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; +- reg = <0x3a00 0x100>; +- interrupts = <2 7 0>; +- }; +- +- sclpc@3c00 { +- compatible = "fsl,mpc5200-lpbfifo"; +- reg = <0x3c00 0x60>; +- interrupts = <2 23 0>; +- }; +- +- i2c@3d00 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; +- reg = <0x3d00 0x40>; +- interrupts = <2 15 0>; +- }; +- +- i2c@3d40 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; +- reg = <0x3d40 0x40>; +- interrupts = <2 16 0>; +- }; +- +- sram@8000 { +- compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; +- reg = <0x8000 0x4000>; +- }; +- }; +- +- pci: pci@f0000d00 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; +- reg = <0xf0000d00 0x100>; +- // interrupt-map-mask = need to add +- // interrupt-map = need to add +- clock-frequency = <0>; // From boot loader +- interrupts = <2 8 0 2 9 0 2 10 0>; +- bus-range = <0 0>; +- // ranges = need to add +- }; +- +- localbus: localbus { +- compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0 0xfc000000 0x2000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc7448hpc2.dts b/scripts/dtc/include-prefixes/powerpc/mpc7448hpc2.dts +deleted file mode 100644 +index 9494af160e95..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc7448hpc2.dts ++++ /dev/null +@@ -1,192 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC7448HPC2 (Taiga) board Device Tree Source +- * +- * Copyright 2006, 2008 Freescale Semiconductor Inc. +- * 2006 Roy Zang . +- */ +- +-/dts-v1/; +- +-/ { +- model = "mpc7448hpc2"; +- compatible = "mpc74xx"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- +- serial0 = &serial0; +- serial1 = &serial1; +- +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells =<0>; +- +- PowerPC,7448@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <0x8000>; // L1, 32K bytes +- i-cache-size = <0x8000>; // L1, 32K bytes +- timebase-frequency = <0>; // 33 MHz, from uboot +- clock-frequency = <0>; // From U-Boot +- bus-frequency = <0>; // From U-Boot +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x20000000 // DDR2 512M at 0 +- >; +- }; +- +- tsi108@c0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "tsi-bridge"; +- ranges = <0x0 0xc0000000 0x10000>; +- reg = <0xc0000000 0x10000>; +- bus-frequency = <0>; +- +- i2c@7000 { +- interrupt-parent = <&mpic>; +- interrupts = <14 0>; +- reg = <0x7000 0x400>; +- device_type = "i2c"; +- compatible = "tsi108-i2c"; +- }; +- +- MDIO: mdio@6000 { +- compatible = "tsi108-mdio"; +- reg = <0x6000 0x50>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy8: ethernet-phy@8 { +- interrupt-parent = <&mpic>; +- interrupts = <2 1>; +- reg = <0x8>; +- }; +- +- phy9: ethernet-phy@9 { +- interrupt-parent = <&mpic>; +- interrupts = <2 1>; +- reg = <0x9>; +- }; +- +- }; +- +- enet0: ethernet@6200 { +- linux,network-index = <0>; +- #size-cells = <0>; +- device_type = "network"; +- compatible = "tsi108-ethernet"; +- reg = <0x6000 0x200>; +- address = [ 00 06 D2 00 00 01 ]; +- interrupts = <16 2>; +- interrupt-parent = <&mpic>; +- mdio-handle = <&MDIO>; +- phy-handle = <&phy8>; +- }; +- +- enet1: ethernet@6600 { +- linux,network-index = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- device_type = "network"; +- compatible = "tsi108-ethernet"; +- reg = <0x6400 0x200>; +- address = [ 00 06 D2 00 00 02 ]; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- mdio-handle = <&MDIO>; +- phy-handle = <&phy9>; +- }; +- +- serial0: serial@7808 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0x7808 0x200>; +- clock-frequency = <1064000000>; +- interrupts = <12 0>; +- interrupt-parent = <&mpic>; +- }; +- +- serial1: serial@7c08 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0x7c08 0x200>; +- clock-frequency = <1064000000>; +- interrupts = <13 0>; +- interrupt-parent = <&mpic>; +- }; +- +- mpic: pic@7400 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x7400 0x400>; +- compatible = "chrp,open-pic"; +- device_type = "open-pic"; +- }; +- pci0: pci@1000 { +- compatible = "tsi108-pci"; +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0x1000 0x1000>; +- bus-range = <0 0>; +- ranges = <0x2000000 0x0 0xe0000000 0xe0000000 0x0 0x1a000000 +- 0x1000000 0x0 0x0 0xfa000000 0x0 0x10000>; +- clock-frequency = <133333332>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x11 */ +- 0x800 0x0 0x0 0x1 &RT0 0x24 0x0 +- 0x800 0x0 0x0 0x2 &RT0 0x25 0x0 +- 0x800 0x0 0x0 0x3 &RT0 0x26 0x0 +- 0x800 0x0 0x0 0x4 &RT0 0x27 0x0 +- +- /* IDSEL 0x12 */ +- 0x1000 0x0 0x0 0x1 &RT0 0x25 0x0 +- 0x1000 0x0 0x0 0x2 &RT0 0x26 0x0 +- 0x1000 0x0 0x0 0x3 &RT0 0x27 0x0 +- 0x1000 0x0 0x0 0x4 &RT0 0x24 0x0 +- +- /* IDSEL 0x13 */ +- 0x1800 0x0 0x0 0x1 &RT0 0x26 0x0 +- 0x1800 0x0 0x0 0x2 &RT0 0x27 0x0 +- 0x1800 0x0 0x0 0x3 &RT0 0x24 0x0 +- 0x1800 0x0 0x0 0x4 &RT0 0x25 0x0 +- +- /* IDSEL 0x14 */ +- 0x2000 0x0 0x0 0x1 &RT0 0x27 0x0 +- 0x2000 0x0 0x0 0x2 &RT0 0x24 0x0 +- 0x2000 0x0 0x0 0x3 &RT0 0x25 0x0 +- 0x2000 0x0 0x0 0x4 &RT0 0x26 0x0 +- >; +- +- RT0: router@1180 { +- clock-frequency = <0>; +- interrupt-controller; +- device_type = "pic-router"; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- big-endian; +- interrupts = <23 2>; +- interrupt-parent = <&mpic>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc8272ads.dts b/scripts/dtc/include-prefixes/powerpc/mpc8272ads.dts +deleted file mode 100644 +index 13ec786f6adf..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc8272ads.dts ++++ /dev/null +@@ -1,263 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8272 ADS Device Tree Source +- * +- * Copyright 2005,2008 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/ { +- model = "MPC8272ADS"; +- compatible = "fsl,mpc8272ads"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = ð0; +- ethernet1 = ð1; +- serial0 = &scc1; +- serial1 = &scc4; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8272@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <16384>; +- i-cache-size = <16384>; +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; +- }; +- +- localbus@f0010100 { +- compatible = "fsl,mpc8272-localbus", +- "fsl,pq2-localbus"; +- #address-cells = <2>; +- #size-cells = <1>; +- reg = <0xf0010100 0x40>; +- +- ranges = <0x0 0x0 0xff800000 0x00800000 +- 0x1 0x0 0xf4500000 0x8000 +- 0x3 0x0 0xf8200000 0x8000>; +- +- flash@0,0 { +- compatible = "jedec-flash"; +- reg = <0x0 0x0 0x00800000>; +- bank-width = <4>; +- device-width = <1>; +- }; +- +- board-control@1,0 { +- reg = <0x1 0x0 0x20>; +- compatible = "fsl,mpc8272ads-bcsr"; +- }; +- +- PCI_PIC: interrupt-controller@3,0 { +- compatible = "fsl,mpc8272ads-pci-pic", +- "fsl,pq2ads-pci-pic"; +- #interrupt-cells = <1>; +- interrupt-controller; +- reg = <0x3 0x0 0x8>; +- interrupt-parent = <&PIC>; +- interrupts = <20 8>; +- }; +- }; +- +- +- pci@f0010800 { +- device_type = "pci"; +- reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>; +- compatible = "fsl,mpc8272-pci", "fsl,pq2-pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- clock-frequency = <66666666>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x16 */ +- 0xb000 0x0 0x0 0x1 &PCI_PIC 0 +- 0xb000 0x0 0x0 0x2 &PCI_PIC 1 +- 0xb000 0x0 0x0 0x3 &PCI_PIC 2 +- 0xb000 0x0 0x0 0x4 &PCI_PIC 3 +- +- /* IDSEL 0x17 */ +- 0xb800 0x0 0x0 0x1 &PCI_PIC 4 +- 0xb800 0x0 0x0 0x2 &PCI_PIC 5 +- 0xb800 0x0 0x0 0x3 &PCI_PIC 6 +- 0xb800 0x0 0x0 0x4 &PCI_PIC 7 +- +- /* IDSEL 0x18 */ +- 0xc000 0x0 0x0 0x1 &PCI_PIC 8 +- 0xc000 0x0 0x0 0x2 &PCI_PIC 9 +- 0xc000 0x0 0x0 0x3 &PCI_PIC 10 +- 0xc000 0x0 0x0 0x4 &PCI_PIC 11>; +- +- interrupt-parent = <&PIC>; +- interrupts = <18 8>; +- ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000 +- 0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>; +- }; +- +- soc@f0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,mpc8272", "fsl,pq2-soc"; +- ranges = <0x0 0xf0000000 0x53000>; +- +- // Temporary -- will go away once kernel uses ranges for get_immrbase(). +- reg = <0xf0000000 0x53000>; +- +- cpm@119c0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8272-cpm", "fsl,cpm2"; +- reg = <0x119c0 0x30>; +- ranges; +- +- muram@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x10000>; +- +- data@0 { +- compatible = "fsl,cpm-muram-data"; +- reg = <0x0 0x2000 0x9800 0x800>; +- }; +- }; +- +- brg@119f0 { +- compatible = "fsl,mpc8272-brg", +- "fsl,cpm2-brg", +- "fsl,cpm-brg"; +- reg = <0x119f0 0x10 0x115f0 0x10>; +- }; +- +- scc1: serial@11a00 { +- device_type = "serial"; +- compatible = "fsl,mpc8272-scc-uart", +- "fsl,cpm2-scc-uart"; +- reg = <0x11a00 0x20 0x8000 0x100>; +- interrupts = <40 8>; +- interrupt-parent = <&PIC>; +- fsl,cpm-brg = <1>; +- fsl,cpm-command = <0x800000>; +- }; +- +- scc4: serial@11a60 { +- device_type = "serial"; +- compatible = "fsl,mpc8272-scc-uart", +- "fsl,cpm2-scc-uart"; +- reg = <0x11a60 0x20 0x8300 0x100>; +- interrupts = <43 8>; +- interrupt-parent = <&PIC>; +- fsl,cpm-brg = <4>; +- fsl,cpm-command = <0xce00000>; +- }; +- +- usb@11b60 { +- compatible = "fsl,mpc8272-cpm-usb"; +- reg = <0x11b60 0x40 0x8b00 0x100>; +- interrupts = <11 8>; +- interrupt-parent = <&PIC>; +- mode = "peripheral"; +- }; +- +- mdio@10d40 { +- compatible = "fsl,mpc8272ads-mdio-bitbang", +- "fsl,mpc8272-mdio-bitbang", +- "fsl,cpm2-mdio-bitbang"; +- reg = <0x10d40 0x14>; +- #address-cells = <1>; +- #size-cells = <0>; +- fsl,mdio-pin = <18>; +- fsl,mdc-pin = <19>; +- +- PHY0: ethernet-phy@0 { +- interrupt-parent = <&PIC>; +- interrupts = <23 8>; +- reg = <0x0>; +- }; +- +- PHY1: ethernet-phy@1 { +- interrupt-parent = <&PIC>; +- interrupts = <23 8>; +- reg = <0x3>; +- }; +- }; +- +- eth0: ethernet@11300 { +- device_type = "network"; +- compatible = "fsl,mpc8272-fcc-enet", +- "fsl,cpm2-fcc-enet"; +- reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <32 8>; +- interrupt-parent = <&PIC>; +- phy-handle = <&PHY0>; +- linux,network-index = <0>; +- fsl,cpm-command = <0x12000300>; +- }; +- +- eth1: ethernet@11320 { +- device_type = "network"; +- compatible = "fsl,mpc8272-fcc-enet", +- "fsl,cpm2-fcc-enet"; +- reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <33 8>; +- interrupt-parent = <&PIC>; +- phy-handle = <&PHY1>; +- linux,network-index = <1>; +- fsl,cpm-command = <0x16200300>; +- }; +- +- i2c@11860 { +- compatible = "fsl,mpc8272-i2c", +- "fsl,cpm2-i2c"; +- reg = <0x11860 0x20 0x8afc 0x2>; +- interrupts = <1 8>; +- interrupt-parent = <&PIC>; +- fsl,cpm-command = <0x29600000>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- PIC: interrupt-controller@10c00 { +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0x10c00 0x80>; +- compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic"; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec1.0"; +- reg = <0x40000 0x13000>; +- interrupts = <47 0x8>; +- interrupt-parent = <&PIC>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x7e>; +- fsl,descriptor-types-mask = <0x1010415>; +- }; +- }; +- +- chosen { +- stdout-path = "/soc/cpm/serial@11a00"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc8308_p1m.dts b/scripts/dtc/include-prefixes/powerpc/mpc8308_p1m.dts +deleted file mode 100644 +index 2638555afcc4..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc8308_p1m.dts ++++ /dev/null +@@ -1,334 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * mpc8308_p1m Device Tree Source +- * +- * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com +- */ +- +-/dts-v1/; +- +-/ { +- compatible = "denx,mpc8308_p1m"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8308@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <16384>; +- i-cache-size = <16384>; +- timebase-frequency = <0>; // from bootloader +- bus-frequency = <0>; // from bootloader +- clock-frequency = <0>; // from bootloader +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; // 128MB at 0 +- }; +- +- localbus@e0005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus"; +- reg = <0xe0005000 0x1000>; +- interrupts = <77 0x8>; +- interrupt-parent = <&ipic>; +- +- ranges = <0x0 0x0 0xfc000000 0x04000000 +- 0x1 0x0 0xfbff0000 0x00008000 +- 0x2 0x0 0xfbff8000 0x00008000>; +- +- flash@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x4000000>; +- bank-width = <2>; +- device-width = <1>; +- +- u-boot@0 { +- reg = <0x0 0x60000>; +- read-only; +- }; +- env@60000 { +- reg = <0x60000 0x20000>; +- }; +- env1@80000 { +- reg = <0x80000 0x20000>; +- }; +- kernel@a0000 { +- reg = <0xa0000 0x200000>; +- }; +- dtb@2a0000 { +- reg = <0x2a0000 0x20000>; +- }; +- ramdisk@2c0000 { +- reg = <0x2c0000 0x640000>; +- }; +- user@700000 { +- reg = <0x700000 0x3900000>; +- }; +- }; +- +- can@1,0 { +- compatible = "nxp,sja1000"; +- reg = <0x1 0x0 0x80>; +- interrupts = <18 0x8>; +- interrups-parent = <&ipic>; +- }; +- +- cpld@2,0 { +- compatible = "denx,mpc8308_p1m-cpld"; +- reg = <0x2 0x0 0x8>; +- interrupts = <48 0x8>; +- interrups-parent = <&ipic>; +- }; +- }; +- +- immr@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,mpc8308-immr", "simple-bus"; +- ranges = <0 0xe0000000 0x00100000>; +- reg = <0xe0000000 0x00000200>; +- bus-frequency = <0>; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- fram@50 { +- compatible = "ramtron,24c64", "atmel,24c64"; +- reg = <0x50>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <15 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- pwm@28 { +- compatible = "maxim,ds1050"; +- reg = <0x28>; +- }; +- sensor@48 { +- compatible = "maxim,max6625"; +- reg = <0x48>; +- }; +- sensor@49 { +- compatible = "maxim,max6625"; +- reg = <0x49>; +- }; +- sensor@4b { +- compatible = "maxim,max6625"; +- reg = <0x4b>; +- }; +- }; +- +- usb@23000 { +- compatible = "fsl-usb2-dr"; +- reg = <0x23000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <38 0x8>; +- dr_mode = "peripheral"; +- phy_type = "ulpi"; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x24000 0x1000>; +- +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <32 0x8 33 0x8 34 0x8>; +- interrupt-parent = <&ipic>; +- phy-handle = < &phy1 >; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- phy1: ethernet-phy@1 { +- interrupt-parent = <&ipic>; +- interrupts = <17 0x8>; +- reg = <0x1>; +- }; +- phy2: ethernet-phy@2 { +- interrupt-parent = <&ipic>; +- interrupts = <19 0x8>; +- reg = <0x2>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 0x8 36 0x8 37 0x8>; +- interrupt-parent = <&ipic>; +- phy-handle = < &phy2 >; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <133333333>; +- interrupts = <9 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <133333333>; +- interrupts = <10 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- gpio@c00 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio"; +- reg = <0xc00 0x18>; +- interrupts = <74 0x8>; +- interrupt-parent = <&ipic>; +- gpio-controller; +- }; +- +- timer@500 { +- compatible = "fsl,mpc8308-gtm", "fsl,gtm"; +- reg = <0x500 0x100>; +- interrupts = <90 8 78 8 84 8 72 8>; +- interrupt-parent = <&ipic>; +- clock-frequency = <133333333>; +- }; +- +- /* IPIC +- * interrupts cell = +- * sense values match linux IORESOURCE_IRQ_* defines: +- * sense == 8: Level, low assertion +- * sense == 2: Edge, high-to-low change +- */ +- ipic: interrupt-controller@700 { +- compatible = "fsl,ipic"; +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x700 0x100>; +- device_type = "ipic"; +- }; +- +- ipic-msi@7c0 { +- compatible = "fsl,ipic-msi"; +- reg = <0x7c0 0x40>; +- msi-available-ranges = <0x0 0x100>; +- interrupts = < 0x43 0x8 +- 0x4 0x8 +- 0x51 0x8 +- 0x52 0x8 +- 0x56 0x8 +- 0x57 0x8 +- 0x58 0x8 +- 0x59 0x8 >; +- interrupt-parent = < &ipic >; +- }; +- +- dma@2c000 { +- compatible = "fsl,mpc8308-dma"; +- reg = <0x2c000 0x1800>; +- interrupts = <3 0x8 +- 94 0x8>; +- interrupt-parent = < &ipic >; +- }; +- +- }; +- +- pci0: pcie@e0009000 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie"; +- reg = <0xe0009000 0x00001000 +- 0xb0000000 0x01000000>; +- ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; +- bus-range = <0 0>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &ipic 1 8>; +- interrupts = <0x1 0x8>; +- interrupt-parent = <&ipic>; +- clock-frequency = <0>; +- +- pcie@0 { +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- reg = <0 0 0 0 0>; +- ranges = <0x02000000 0 0xa0000000 +- 0x02000000 0 0xa0000000 +- 0 0x10000000 +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00800000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc8308rdb.dts b/scripts/dtc/include-prefixes/powerpc/mpc8308rdb.dts +deleted file mode 100644 +index af2ed8380a86..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc8308rdb.dts ++++ /dev/null +@@ -1,306 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8308RDB Device Tree Source +- * +- * Copyright 2009 Freescale Semiconductor Inc. +- * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com +- */ +- +-/dts-v1/; +- +-/ { +- compatible = "fsl,mpc8308rdb"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8308@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <16384>; +- i-cache-size = <16384>; +- timebase-frequency = <0>; // from bootloader +- bus-frequency = <0>; // from bootloader +- clock-frequency = <0>; // from bootloader +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; // 128MB at 0 +- }; +- +- localbus@e0005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus"; +- reg = <0xe0005000 0x1000>; +- interrupts = <77 0x8>; +- interrupt-parent = <&ipic>; +- +- // CS0 and CS1 are swapped when +- // booting from nand, but the +- // addresses are the same. +- ranges = <0x0 0x0 0xfe000000 0x00800000 +- 0x1 0x0 0xe0600000 0x00002000 +- 0x2 0x0 0xf0000000 0x00020000 +- 0x3 0x0 0xfa000000 0x00008000>; +- +- flash@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x800000>; +- bank-width = <2>; +- device-width = <1>; +- +- u-boot@0 { +- reg = <0x0 0x60000>; +- read-only; +- }; +- env@60000 { +- reg = <0x60000 0x10000>; +- }; +- env1@70000 { +- reg = <0x70000 0x10000>; +- }; +- kernel@80000 { +- reg = <0x80000 0x200000>; +- }; +- dtb@280000 { +- reg = <0x280000 0x10000>; +- }; +- ramdisk@290000 { +- reg = <0x290000 0x570000>; +- }; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8315-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x1 0x0 0x2000>; +- +- jffs2@0 { +- reg = <0x0 0x2000000>; +- }; +- }; +- }; +- +- immr@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,mpc8308-immr", "simple-bus"; +- ranges = <0 0xe0000000 0x00100000>; +- reg = <0xe0000000 0x00000200>; +- bus-frequency = <0>; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +- }; +- +- usb@23000 { +- compatible = "fsl-usb2-dr"; +- reg = <0x23000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <38 0x8>; +- dr_mode = "peripheral"; +- phy_type = "ulpi"; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x24000 0x1000>; +- +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <32 0x8 33 0x8 34 0x8>; +- interrupt-parent = <&ipic>; +- tbi-handle = < &tbi0 >; +- phy-handle = < &phy2 >; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- phy2: ethernet-phy@2 { +- interrupt-parent = <&ipic>; +- interrupts = <17 0x8>; +- reg = <0x2>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 0x8 36 0x8 37 0x8>; +- interrupt-parent = <&ipic>; +- tbi-handle = < &tbi1 >; +- /* Vitesse 7385 isn't on the MDIO bus */ +- fixed-link = <1 1 1000 0 0>; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <133333333>; +- interrupts = <9 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <133333333>; +- interrupts = <10 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- gpio@c00 { +- #gpio-cells = <2>; +- device_type = "gpio"; +- compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio"; +- reg = <0xc00 0x18>; +- interrupts = <74 0x8>; +- interrupt-parent = <&ipic>; +- gpio-controller; +- }; +- +- /* IPIC +- * interrupts cell = +- * sense values match linux IORESOURCE_IRQ_* defines: +- * sense == 8: Level, low assertion +- * sense == 2: Edge, high-to-low change +- */ +- ipic: interrupt-controller@700 { +- compatible = "fsl,ipic"; +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x700 0x100>; +- device_type = "ipic"; +- }; +- +- ipic-msi@7c0 { +- compatible = "fsl,ipic-msi"; +- reg = <0x7c0 0x40>; +- msi-available-ranges = <0x0 0x100>; +- interrupts = < 0x43 0x8 +- 0x4 0x8 +- 0x51 0x8 +- 0x52 0x8 +- 0x56 0x8 +- 0x57 0x8 +- 0x58 0x8 +- 0x59 0x8 >; +- interrupt-parent = < &ipic >; +- }; +- +- dma@2c000 { +- compatible = "fsl,mpc8308-dma"; +- reg = <0x2c000 0x1800>; +- interrupts = <3 0x8 +- 94 0x8>; +- interrupt-parent = < &ipic >; +- }; +- +- }; +- +- pci0: pcie@e0009000 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie"; +- reg = <0xe0009000 0x00001000 +- 0xb0000000 0x01000000>; +- ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; +- bus-range = <0 0>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0 0 0 1 &ipic 1 8 +- 0 0 0 2 &ipic 1 8 +- 0 0 0 3 &ipic 1 8 +- 0 0 0 4 &ipic 1 8>; +- interrupts = <0x1 0x8>; +- interrupt-parent = <&ipic>; +- clock-frequency = <0>; +- +- pcie@0 { +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- reg = <0 0 0 0 0>; +- ranges = <0x02000000 0 0xa0000000 +- 0x02000000 0 0xa0000000 +- 0 0x10000000 +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00800000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc8313erdb.dts b/scripts/dtc/include-prefixes/powerpc/mpc8313erdb.dts +deleted file mode 100644 +index a8315795b2c9..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc8313erdb.dts ++++ /dev/null +@@ -1,405 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8313E RDB Device Tree Source +- * +- * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/ { +- model = "MPC8313ERDB"; +- compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8313@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <16384>; +- i-cache-size = <16384>; +- timebase-frequency = <0>; // from bootloader +- bus-frequency = <0>; // from bootloader +- clock-frequency = <0>; // from bootloader +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; // 128MB at 0 +- }; +- +- localbus@e0005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus"; +- reg = <0xe0005000 0x1000>; +- interrupts = <77 0x8>; +- interrupt-parent = <&ipic>; +- +- // CS0 and CS1 are swapped when +- // booting from nand, but the +- // addresses are the same. +- ranges = <0x0 0x0 0xfe000000 0x00800000 +- 0x1 0x0 0xe2800000 0x00008000 +- 0x2 0x0 0xf0000000 0x00020000 +- 0x3 0x0 0xfa000000 0x00008000>; +- +- flash@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x800000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8313-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x1 0x0 0x2000>; +- +- u-boot@0 { +- reg = <0x0 0x100000>; +- read-only; +- }; +- +- kernel@100000 { +- reg = <0x100000 0x300000>; +- }; +- +- fs@400000 { +- reg = <0x400000 0x1c00000>; +- }; +- }; +- }; +- +- soc8313@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- ranges = <0x0 0xe0000000 0x00100000>; +- reg = <0xe0000000 0x00000200>; +- bus-frequency = <0>; +- +- wdt@200 { +- device_type = "watchdog"; +- compatible = "mpc83xx_wdt"; +- reg = <0x200 0x100>; +- }; +- +- sleep-nexus { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- sleep = <&pmc 0x03000000>; +- ranges; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec2.2", "fsl,sec2.1", +- "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <11 0x8>; +- interrupt-parent = <&ipic>; +- fsl,num-channels = <1>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x4c>; +- fsl,descriptor-types-mask = <0x0122003f>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <15 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- }; +- +- spi@7000 { +- cell-index = <0>; +- compatible = "fsl,spi"; +- reg = <0x7000 0x1000>; +- interrupts = <16 0x8>; +- interrupt-parent = <&ipic>; +- mode = "cpu"; +- }; +- +- /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ +- usb@23000 { +- compatible = "fsl-usb2-dr"; +- reg = <0x23000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <38 0x8>; +- phy_type = "utmi_wide"; +- sleep = <&pmc 0x00300000>; +- }; +- +- ptp_clock@24E00 { +- compatible = "fsl,etsec-ptp"; +- reg = <0x24E00 0xB0>; +- interrupts = <12 0x8 13 0x8>; +- interrupt-parent = < &ipic >; +- fsl,tclk-period = <10>; +- fsl,tmr-prsc = <100>; +- fsl,tmr-add = <0x999999A4>; +- fsl,tmr-fiper1 = <0x3B9AC9F6>; +- fsl,tmr-fiper2 = <0x00018696>; +- fsl,max-adj = <659999998>; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- sleep = <&pmc 0x20000000>; +- ranges = <0x0 0x24000 0x1000>; +- +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <37 0x8 36 0x8 35 0x8>; +- interrupt-parent = <&ipic>; +- tbi-handle = < &tbi0 >; +- /* Vitesse 7385 isn't on the MDIO bus */ +- fixed-link = <1 1 1000 0 0>; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- phy4: ethernet-phy@4 { +- interrupt-parent = <&ipic>; +- interrupts = <20 0x8>; +- reg = <0x4>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <34 0x8 33 0x8 32 0x8>; +- interrupt-parent = <&ipic>; +- tbi-handle = < &tbi1 >; +- phy-handle = < &phy4 >; +- sleep = <&pmc 0x10000000>; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- +- +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- interrupts = <9 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- interrupts = <10 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- /* IPIC +- * interrupts cell = +- * sense values match linux IORESOURCE_IRQ_* defines: +- * sense == 8: Level, low assertion +- * sense == 2: Edge, high-to-low change +- */ +- ipic: pic@700 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x700 0x100>; +- device_type = "ipic"; +- }; +- +- pmc: power@b00 { +- compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; +- reg = <0xb00 0x100 0xa00 0x100>; +- interrupts = <80 8>; +- interrupt-parent = <&ipic>; +- fsl,mpc8313-wakeup-timer = <>m1>; +- +- /* Remove this (or change to "okay") if you have +- * a REVA3 or later board, if you apply one of the +- * workarounds listed in section 8.5 of the board +- * manual, or if you are adapting this device tree +- * to a different board. +- */ +- status = "fail"; +- }; +- +- gtm1: timer@500 { +- compatible = "fsl,mpc8313-gtm", "fsl,gtm"; +- reg = <0x500 0x100>; +- interrupts = <90 8 78 8 84 8 72 8>; +- interrupt-parent = <&ipic>; +- }; +- +- timer@600 { +- compatible = "fsl,mpc8313-gtm", "fsl,gtm"; +- reg = <0x600 0x100>; +- interrupts = <91 8 79 8 85 8 73 8>; +- interrupt-parent = <&ipic>; +- }; +- }; +- +- sleep-nexus { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- sleep = <&pmc 0x00010000>; +- ranges; +- +- pci0: pci@e0008500 { +- cell-index = <1>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x0E -mini PCI */ +- 0x7000 0x0 0x0 0x1 &ipic 18 0x8 +- 0x7000 0x0 0x0 0x2 &ipic 18 0x8 +- 0x7000 0x0 0x0 0x3 &ipic 18 0x8 +- 0x7000 0x0 0x0 0x4 &ipic 18 0x8 +- +- /* IDSEL 0x0F - PCI slot */ +- 0x7800 0x0 0x0 0x1 &ipic 17 0x8 +- 0x7800 0x0 0x0 0x2 &ipic 18 0x8 +- 0x7800 0x0 0x0 0x3 &ipic 17 0x8 +- 0x7800 0x0 0x0 0x4 &ipic 18 0x8>; +- interrupt-parent = <&ipic>; +- interrupts = <66 0x8>; +- bus-range = <0x0 0x0>; +- ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 +- 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008500 0x100 /* internal registers */ +- 0xe0008300 0x8>; /* config space access registers */ +- compatible = "fsl,mpc8349-pci"; +- device_type = "pci"; +- }; +- +- dma@82a8 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8313-dma", "fsl,elo-dma"; +- reg = <0xe00082a8 4>; +- ranges = <0 0xe0008100 0x1a8>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- +- dma-channel@0 { +- compatible = "fsl,mpc8313-dma-channel", +- "fsl,elo-dma-channel"; +- reg = <0 0x28>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <0>; +- }; +- +- dma-channel@80 { +- compatible = "fsl,mpc8313-dma-channel", +- "fsl,elo-dma-channel"; +- reg = <0x80 0x28>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <1>; +- }; +- +- dma-channel@100 { +- compatible = "fsl,mpc8313-dma-channel", +- "fsl,elo-dma-channel"; +- reg = <0x100 0x28>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <2>; +- }; +- +- dma-channel@180 { +- compatible = "fsl,mpc8313-dma-channel", +- "fsl,elo-dma-channel"; +- reg = <0x180 0x28>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <3>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc8315erdb.dts b/scripts/dtc/include-prefixes/powerpc/mpc8315erdb.dts +deleted file mode 100644 +index e09b37d7489d..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc8315erdb.dts ++++ /dev/null +@@ -1,474 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8315E RDB Device Tree Source +- * +- * Copyright 2007 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/ { +- compatible = "fsl,mpc8315erdb"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8315@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <16384>; +- i-cache-size = <16384>; +- timebase-frequency = <0>; // from bootloader +- bus-frequency = <0>; // from bootloader +- clock-frequency = <0>; // from bootloader +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; // 128MB at 0 +- }; +- +- localbus@e0005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus"; +- reg = <0xe0005000 0x1000>; +- interrupts = <77 0x8>; +- interrupt-parent = <&ipic>; +- +- // CS0 and CS1 are swapped when +- // booting from nand, but the +- // addresses are the same. +- ranges = <0x0 0x0 0xfe000000 0x00800000 +- 0x1 0x0 0xe0600000 0x00002000 +- 0x2 0x0 0xf0000000 0x00020000 +- 0x3 0x0 0xfa000000 0x00008000>; +- +- flash@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x800000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8315-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x1 0x0 0x2000>; +- +- u-boot@0 { +- reg = <0x0 0x100000>; +- read-only; +- }; +- +- kernel@100000 { +- reg = <0x100000 0x300000>; +- }; +- fs@400000 { +- reg = <0x400000 0x1c00000>; +- }; +- }; +- }; +- +- immr@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,mpc8315-immr", "simple-bus"; +- ranges = <0 0xe0000000 0x00100000>; +- reg = <0xe0000000 0x00000200>; +- bus-frequency = <0>; +- +- wdt@200 { +- device_type = "watchdog"; +- compatible = "mpc83xx_wdt"; +- reg = <0x200 0x100>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +- +- mcu_pio: mcu@a { +- #gpio-cells = <2>; +- compatible = "fsl,mc9s08qg8-mpc8315erdb", +- "fsl,mcu-mpc8349emitx"; +- reg = <0x0a>; +- gpio-controller; +- }; +- }; +- +- spi@7000 { +- cell-index = <0>; +- compatible = "fsl,spi"; +- reg = <0x7000 0x1000>; +- interrupts = <16 0x8>; +- interrupt-parent = <&ipic>; +- mode = "cpu"; +- }; +- +- dma@82a8 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8315-dma", "fsl,elo-dma"; +- reg = <0x82a8 4>; +- ranges = <0 0x8100 0x1a8>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; +- reg = <0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x180 0x28>; +- cell-index = <3>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- }; +- +- usb@23000 { +- compatible = "fsl-usb2-dr"; +- reg = <0x23000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <38 0x8>; +- phy_type = "utmi"; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <32 0x8 33 0x8 34 0x8>; +- interrupt-parent = <&ipic>; +- tbi-handle = <&tbi0>; +- phy-handle = < &phy0 >; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy0: ethernet-phy@0 { +- interrupt-parent = <&ipic>; +- interrupts = <20 0x8>; +- reg = <0x0>; +- }; +- +- phy1: ethernet-phy@1 { +- interrupt-parent = <&ipic>; +- interrupts = <19 0x8>; +- reg = <0x1>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 0x8 36 0x8 37 0x8>; +- interrupt-parent = <&ipic>; +- tbi-handle = <&tbi1>; +- phy-handle = < &phy1 >; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <133333333>; +- interrupts = <9 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <133333333>; +- interrupts = <10 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0", +- "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", +- "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <11 0x8>; +- interrupt-parent = <&ipic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x97c>; +- fsl,descriptor-types-mask = <0x3a30abf>; +- }; +- +- sata@18000 { +- compatible = "fsl,mpc8315-sata", "fsl,pq-sata"; +- reg = <0x18000 0x1000>; +- cell-index = <1>; +- interrupts = <44 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- sata@19000 { +- compatible = "fsl,mpc8315-sata", "fsl,pq-sata"; +- reg = <0x19000 0x1000>; +- cell-index = <2>; +- interrupts = <45 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- gtm1: timer@500 { +- compatible = "fsl,mpc8315-gtm", "fsl,gtm"; +- reg = <0x500 0x100>; +- interrupts = <90 8 78 8 84 8 72 8>; +- interrupt-parent = <&ipic>; +- clock-frequency = <133333333>; +- }; +- +- timer@600 { +- compatible = "fsl,mpc8315-gtm", "fsl,gtm"; +- reg = <0x600 0x100>; +- interrupts = <91 8 79 8 85 8 73 8>; +- interrupt-parent = <&ipic>; +- clock-frequency = <133333333>; +- }; +- +- /* IPIC +- * interrupts cell = +- * sense values match linux IORESOURCE_IRQ_* defines: +- * sense == 8: Level, low assertion +- * sense == 2: Edge, high-to-low change +- */ +- ipic: interrupt-controller@700 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x700 0x100>; +- device_type = "ipic"; +- }; +- +- ipic-msi@7c0 { +- compatible = "fsl,ipic-msi"; +- reg = <0x7c0 0x40>; +- msi-available-ranges = <0 0x100>; +- interrupts = <0x43 0x8 +- 0x4 0x8 +- 0x51 0x8 +- 0x52 0x8 +- 0x56 0x8 +- 0x57 0x8 +- 0x58 0x8 +- 0x59 0x8>; +- interrupt-parent = < &ipic >; +- }; +- +- pmc: power@b00 { +- compatible = "fsl,mpc8315-pmc", "fsl,mpc8313-pmc", +- "fsl,mpc8349-pmc"; +- reg = <0xb00 0x100 0xa00 0x100>; +- interrupts = <80 8>; +- interrupt-parent = <&ipic>; +- fsl,mpc8313-wakeup-timer = <>m1>; +- }; +- }; +- +- pci0: pci@e0008500 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x0E -mini PCI */ +- 0x7000 0x0 0x0 0x1 &ipic 18 0x8 +- 0x7000 0x0 0x0 0x2 &ipic 18 0x8 +- 0x7000 0x0 0x0 0x3 &ipic 18 0x8 +- 0x7000 0x0 0x0 0x4 &ipic 18 0x8 +- +- /* IDSEL 0x0F -mini PCI */ +- 0x7800 0x0 0x0 0x1 &ipic 17 0x8 +- 0x7800 0x0 0x0 0x2 &ipic 17 0x8 +- 0x7800 0x0 0x0 0x3 &ipic 17 0x8 +- 0x7800 0x0 0x0 0x4 &ipic 17 0x8 +- +- /* IDSEL 0x10 - PCI slot */ +- 0x8000 0x0 0x0 0x1 &ipic 48 0x8 +- 0x8000 0x0 0x0 0x2 &ipic 17 0x8 +- 0x8000 0x0 0x0 0x3 &ipic 48 0x8 +- 0x8000 0x0 0x0 0x4 &ipic 17 0x8>; +- interrupt-parent = <&ipic>; +- interrupts = <66 0x8>; +- bus-range = <0x0 0x0>; +- ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 +- 0x42000000 0 0x80000000 0x80000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008500 0x100 /* internal registers */ +- 0xe0008300 0x8>; /* config space access registers */ +- compatible = "fsl,mpc8349-pci"; +- device_type = "pci"; +- }; +- +- pci1: pcie@e0009000 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; +- reg = <0xe0009000 0x00001000>; +- ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; +- bus-range = <0 255>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0 0 0 1 &ipic 1 8 +- 0 0 0 2 &ipic 1 8 +- 0 0 0 3 &ipic 1 8 +- 0 0 0 4 &ipic 1 8>; +- clock-frequency = <0>; +- +- pcie@0 { +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- reg = <0 0 0 0 0>; +- ranges = <0x02000000 0 0xa0000000 +- 0x02000000 0 0xa0000000 +- 0 0x10000000 +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00800000>; +- }; +- }; +- +- pci2: pcie@e000a000 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; +- reg = <0xe000a000 0x00001000>; +- ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xd1000000 0 0x00800000>; +- bus-range = <0 255>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0 0 0 1 &ipic 2 8 +- 0 0 0 2 &ipic 2 8 +- 0 0 0 3 &ipic 2 8 +- 0 0 0 4 &ipic 2 8>; +- clock-frequency = <0>; +- +- pcie@0 { +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- reg = <0 0 0 0 0>; +- ranges = <0x02000000 0 0xc0000000 +- 0x02000000 0 0xc0000000 +- 0 0x10000000 +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00800000>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pwr { +- gpios = <&mcu_pio 0 0>; +- default-state = "on"; +- }; +- +- hdd { +- gpios = <&mcu_pio 1 0>; +- linux,default-trigger = "disk-activity"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc832x_mds.dts b/scripts/dtc/include-prefixes/powerpc/mpc832x_mds.dts +deleted file mode 100644 +index 3af073f01e71..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc832x_mds.dts ++++ /dev/null +@@ -1,436 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8323E EMDS Device Tree Source +- * +- * Copyright 2006 Freescale Semiconductor Inc. +- * +- +- * To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do +- * this: +- * +- * 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board. +- * 2) Solder a wire from U61-21 to P19A-23. P19 is a grid of pins on the board +- * next to the serial ports. +- * 3) Solder a wire from U61-22 to P19K-22. +- * +- * Note that there's a typo in the schematic. The board labels the last column +- * of pins "P19K", but in the schematic, that column is called "P19J". So if +- * you're going by the schematic, the pin is called "P19J-K22". +- */ +- +-/dts-v1/; +- +-/ { +- model = "MPC8323EMDS"; +- compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8323@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <16384>; // L1, 16K +- i-cache-size = <16384>; // L1, 16K +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +- +- bcsr@f8000000 { +- compatible = "fsl,mpc8323mds-bcsr"; +- reg = <0xf8000000 0x8000>; +- }; +- +- soc8323@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- ranges = <0x0 0xe0000000 0x00100000>; +- reg = <0xe0000000 0x00000200>; +- bus-frequency = <132000000>; +- +- wdt@200 { +- device_type = "watchdog"; +- compatible = "mpc83xx_wdt"; +- reg = <0x200 0x100>; +- }; +- +- pmc: power@b00 { +- compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc"; +- reg = <0xb00 0x100 0xa00 0x100>; +- interrupts = <80 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- +- rtc@68 { +- compatible = "dallas,ds1374"; +- reg = <0x68>; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- interrupts = <9 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- interrupts = <10 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- dma@82a8 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8323-dma", "fsl,elo-dma"; +- reg = <0x82a8 4>; +- ranges = <0 0x8100 0x1a8>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; +- reg = <0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x180 0x28>; +- cell-index = <3>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <11 0x8>; +- interrupt-parent = <&ipic>; +- fsl,num-channels = <1>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x4c>; +- fsl,descriptor-types-mask = <0x0122003f>; +- sleep = <&pmc 0x03000000>; +- }; +- +- ipic: pic@700 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x700 0x100>; +- device_type = "ipic"; +- }; +- +- par_io@1400 { +- reg = <0x1400 0x100>; +- device_type = "par_io"; +- num-ports = <7>; +- +- pio3: ucc_pin@3 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 3 4 3 0 2 0 /* MDIO */ +- 3 5 1 0 2 0 /* MDC */ +- 0 13 2 0 1 0 /* RX_CLK (CLK9) */ +- 3 24 2 0 1 0 /* TX_CLK (CLK10) */ +- 1 0 1 0 1 0 /* TxD0 */ +- 1 1 1 0 1 0 /* TxD1 */ +- 1 2 1 0 1 0 /* TxD2 */ +- 1 3 1 0 1 0 /* TxD3 */ +- 1 4 2 0 1 0 /* RxD0 */ +- 1 5 2 0 1 0 /* RxD1 */ +- 1 6 2 0 1 0 /* RxD2 */ +- 1 7 2 0 1 0 /* RxD3 */ +- 1 8 2 0 1 0 /* RX_ER */ +- 1 9 1 0 1 0 /* TX_ER */ +- 1 10 2 0 1 0 /* RX_DV */ +- 1 11 2 0 1 0 /* COL */ +- 1 12 1 0 1 0 /* TX_EN */ +- 1 13 2 0 1 0>; /* CRS */ +- }; +- pio4: ucc_pin@4 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 3 31 2 0 1 0 /* RX_CLK (CLK7) */ +- 3 6 2 0 1 0 /* TX_CLK (CLK8) */ +- 1 18 1 0 1 0 /* TxD0 */ +- 1 19 1 0 1 0 /* TxD1 */ +- 1 20 1 0 1 0 /* TxD2 */ +- 1 21 1 0 1 0 /* TxD3 */ +- 1 22 2 0 1 0 /* RxD0 */ +- 1 23 2 0 1 0 /* RxD1 */ +- 1 24 2 0 1 0 /* RxD2 */ +- 1 25 2 0 1 0 /* RxD3 */ +- 1 26 2 0 1 0 /* RX_ER */ +- 1 27 1 0 1 0 /* TX_ER */ +- 1 28 2 0 1 0 /* RX_DV */ +- 1 29 2 0 1 0 /* COL */ +- 1 30 1 0 1 0 /* TX_EN */ +- 1 31 2 0 1 0>; /* CRS */ +- }; +- pio5: ucc_pin@5 { +- pio-map = < +- /* +- * open has +- * port pin dir drain sel irq +- */ +- 2 0 1 0 2 0 /* TxD5 */ +- 2 8 2 0 2 0 /* RxD5 */ +- +- 2 29 2 0 0 0 /* CTS5 */ +- 2 31 1 0 2 0 /* RTS5 */ +- +- 2 24 2 0 0 0 /* CD */ +- +- >; +- }; +- +- }; +- }; +- +- qe@e0100000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "qe"; +- compatible = "fsl,qe"; +- ranges = <0x0 0xe0100000 0x00100000>; +- reg = <0xe0100000 0x480>; +- brg-frequency = <0>; +- bus-frequency = <198000000>; +- fsl,qe-num-riscs = <1>; +- fsl,qe-num-snums = <28>; +- +- muram@10000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,qe-muram", "fsl,cpm-muram"; +- ranges = <0x0 0x00010000 0x00004000>; +- +- data-only@0 { +- compatible = "fsl,qe-muram-data", +- "fsl,cpm-muram-data"; +- reg = <0x0 0x4000>; +- }; +- }; +- +- spi@4c0 { +- cell-index = <0>; +- compatible = "fsl,spi"; +- reg = <0x4c0 0x40>; +- interrupts = <2>; +- interrupt-parent = <&qeic>; +- mode = "cpu"; +- }; +- +- spi@500 { +- cell-index = <1>; +- compatible = "fsl,spi"; +- reg = <0x500 0x40>; +- interrupts = <1>; +- interrupt-parent = <&qeic>; +- mode = "cpu"; +- }; +- +- usb@6c0 { +- compatible = "qe_udc"; +- reg = <0x6c0 0x40 0x8b00 0x100>; +- interrupts = <11>; +- interrupt-parent = <&qeic>; +- mode = "slave"; +- }; +- +- enet0: ucc@2200 { +- device_type = "network"; +- compatible = "ucc_geth"; +- cell-index = <3>; +- reg = <0x2200 0x200>; +- interrupts = <34>; +- interrupt-parent = <&qeic>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "clk9"; +- tx-clock-name = "clk10"; +- phy-handle = <&phy3>; +- pio-handle = <&pio3>; +- }; +- +- enet1: ucc@3200 { +- device_type = "network"; +- compatible = "ucc_geth"; +- cell-index = <4>; +- reg = <0x3200 0x200>; +- interrupts = <35>; +- interrupt-parent = <&qeic>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "clk7"; +- tx-clock-name = "clk8"; +- phy-handle = <&phy4>; +- pio-handle = <&pio4>; +- }; +- +- ucc@2400 { +- device_type = "serial"; +- compatible = "ucc_uart"; +- cell-index = <5>; /* The UCC number, 1-7*/ +- port-number = <0>; /* Which ttyQEx device */ +- soft-uart; /* We need Soft-UART */ +- reg = <0x2400 0x200>; +- interrupts = <40>; /* From Table 18-12 */ +- interrupt-parent = < &qeic >; +- /* +- * For Soft-UART, we need to set TX to 1X, which +- * means specifying separate clock sources. +- */ +- rx-clock-name = "brg5"; +- tx-clock-name = "brg6"; +- pio-handle = < &pio5 >; +- }; +- +- +- mdio@2320 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2320 0x18>; +- compatible = "fsl,ucc-mdio"; +- +- phy3: ethernet-phy@3 { +- interrupt-parent = <&ipic>; +- interrupts = <17 0x8>; +- reg = <0x3>; +- }; +- phy4: ethernet-phy@4 { +- interrupt-parent = <&ipic>; +- interrupts = <18 0x8>; +- reg = <0x4>; +- }; +- }; +- +- qeic: interrupt-controller@80 { +- interrupt-controller; +- compatible = "fsl,qe-ic"; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x80 0x80>; +- big-endian; +- interrupts = <32 0x8 33 0x8>; //high:32 low:33 +- interrupt-parent = <&ipic>; +- }; +- }; +- +- pci0: pci@e0008500 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x11 AD17 */ +- 0x8800 0x0 0x0 0x1 &ipic 20 0x8 +- 0x8800 0x0 0x0 0x2 &ipic 21 0x8 +- 0x8800 0x0 0x0 0x3 &ipic 22 0x8 +- 0x8800 0x0 0x0 0x4 &ipic 23 0x8 +- +- /* IDSEL 0x12 AD18 */ +- 0x9000 0x0 0x0 0x1 &ipic 22 0x8 +- 0x9000 0x0 0x0 0x2 &ipic 23 0x8 +- 0x9000 0x0 0x0 0x3 &ipic 20 0x8 +- 0x9000 0x0 0x0 0x4 &ipic 21 0x8 +- +- /* IDSEL 0x13 AD19 */ +- 0x9800 0x0 0x0 0x1 &ipic 23 0x8 +- 0x9800 0x0 0x0 0x2 &ipic 20 0x8 +- 0x9800 0x0 0x0 0x3 &ipic 21 0x8 +- 0x9800 0x0 0x0 0x4 &ipic 22 0x8 +- +- /* IDSEL 0x15 AD21*/ +- 0xa800 0x0 0x0 0x1 &ipic 20 0x8 +- 0xa800 0x0 0x0 0x2 &ipic 21 0x8 +- 0xa800 0x0 0x0 0x3 &ipic 22 0x8 +- 0xa800 0x0 0x0 0x4 &ipic 23 0x8 +- +- /* IDSEL 0x16 AD22*/ +- 0xb000 0x0 0x0 0x1 &ipic 23 0x8 +- 0xb000 0x0 0x0 0x2 &ipic 20 0x8 +- 0xb000 0x0 0x0 0x3 &ipic 21 0x8 +- 0xb000 0x0 0x0 0x4 &ipic 22 0x8 +- +- /* IDSEL 0x17 AD23*/ +- 0xb800 0x0 0x0 0x1 &ipic 22 0x8 +- 0xb800 0x0 0x0 0x2 &ipic 23 0x8 +- 0xb800 0x0 0x0 0x3 &ipic 20 0x8 +- 0xb800 0x0 0x0 0x4 &ipic 21 0x8 +- +- /* IDSEL 0x18 AD24*/ +- 0xc000 0x0 0x0 0x1 &ipic 21 0x8 +- 0xc000 0x0 0x0 0x2 &ipic 22 0x8 +- 0xc000 0x0 0x0 0x3 &ipic 23 0x8 +- 0xc000 0x0 0x0 0x4 &ipic 20 0x8>; +- interrupt-parent = <&ipic>; +- interrupts = <66 0x8>; +- bus-range = <0x0 0x0>; +- ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 +- 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>; +- clock-frequency = <0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008500 0x100 /* internal registers */ +- 0xe0008300 0x8>; /* config space access registers */ +- compatible = "fsl,mpc8349-pci"; +- device_type = "pci"; +- sleep = <&pmc 0x00010000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc832x_rdb.dts b/scripts/dtc/include-prefixes/powerpc/mpc832x_rdb.dts +deleted file mode 100644 +index ecebc27a2898..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc832x_rdb.dts ++++ /dev/null +@@ -1,363 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC832x RDB Device Tree Source +- * +- * Copyright 2007 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/ { +- model = "MPC8323ERDB"; +- compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet1; +- ethernet1 = &enet0; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8323@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <0x20>; // 32 bytes +- i-cache-line-size = <0x20>; // 32 bytes +- d-cache-size = <16384>; // L1, 16K +- i-cache-size = <16384>; // L1, 16K +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x04000000>; +- }; +- +- soc8323@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- ranges = <0x0 0xe0000000 0x00100000>; +- reg = <0xe0000000 0x00000200>; +- bus-frequency = <0>; +- +- wdt@200 { +- device_type = "watchdog"; +- compatible = "mpc83xx_wdt"; +- reg = <0x200 0x100>; +- }; +- +- pmc: power@b00 { +- compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc"; +- reg = <0xb00 0x100 0xa00 0x100>; +- interrupts = <80 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- interrupts = <9 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- interrupts = <10 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- dma@82a8 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8323-dma", "fsl,elo-dma"; +- reg = <0x82a8 4>; +- ranges = <0 0x8100 0x1a8>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; +- reg = <0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x180 0x28>; +- cell-index = <3>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <11 0x8>; +- interrupt-parent = <&ipic>; +- fsl,num-channels = <1>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x4c>; +- fsl,descriptor-types-mask = <0x0122003f>; +- sleep = <&pmc 0x03000000>; +- }; +- +- ipic:pic@700 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x700 0x100>; +- device_type = "ipic"; +- }; +- +- par_io@1400 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x1400 0x100>; +- ranges = <3 0x1448 0x18>; +- compatible = "fsl,mpc8323-qe-pario"; +- device_type = "par_io"; +- num-ports = <7>; +- +- qe_pio_d: gpio-controller@1448 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8323-qe-pario-bank"; +- reg = <3 0x18>; +- gpio-controller; +- }; +- +- ucc2pio:ucc_pin@2 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 3 4 3 0 2 0 /* MDIO */ +- 3 5 1 0 2 0 /* MDC */ +- 3 21 2 0 1 0 /* RX_CLK (CLK16) */ +- 3 23 2 0 1 0 /* TX_CLK (CLK3) */ +- 0 18 1 0 1 0 /* TxD0 */ +- 0 19 1 0 1 0 /* TxD1 */ +- 0 20 1 0 1 0 /* TxD2 */ +- 0 21 1 0 1 0 /* TxD3 */ +- 0 22 2 0 1 0 /* RxD0 */ +- 0 23 2 0 1 0 /* RxD1 */ +- 0 24 2 0 1 0 /* RxD2 */ +- 0 25 2 0 1 0 /* RxD3 */ +- 0 26 2 0 1 0 /* RX_ER */ +- 0 27 1 0 1 0 /* TX_ER */ +- 0 28 2 0 1 0 /* RX_DV */ +- 0 29 2 0 1 0 /* COL */ +- 0 30 1 0 1 0 /* TX_EN */ +- 0 31 2 0 1 0>; /* CRS */ +- }; +- ucc3pio:ucc_pin@3 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0 13 2 0 1 0 /* RX_CLK (CLK9) */ +- 3 24 2 0 1 0 /* TX_CLK (CLK10) */ +- 1 0 1 0 1 0 /* TxD0 */ +- 1 1 1 0 1 0 /* TxD1 */ +- 1 2 1 0 1 0 /* TxD2 */ +- 1 3 1 0 1 0 /* TxD3 */ +- 1 4 2 0 1 0 /* RxD0 */ +- 1 5 2 0 1 0 /* RxD1 */ +- 1 6 2 0 1 0 /* RxD2 */ +- 1 7 2 0 1 0 /* RxD3 */ +- 1 8 2 0 1 0 /* RX_ER */ +- 1 9 1 0 1 0 /* TX_ER */ +- 1 10 2 0 1 0 /* RX_DV */ +- 1 11 2 0 1 0 /* COL */ +- 1 12 1 0 1 0 /* TX_EN */ +- 1 13 2 0 1 0>; /* CRS */ +- }; +- }; +- }; +- +- qe@e0100000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "qe"; +- compatible = "fsl,qe"; +- ranges = <0x0 0xe0100000 0x00100000>; +- reg = <0xe0100000 0x480>; +- brg-frequency = <0>; +- bus-frequency = <198000000>; +- fsl,qe-num-riscs = <1>; +- fsl,qe-num-snums = <28>; +- +- muram@10000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,qe-muram", "fsl,cpm-muram"; +- ranges = <0x0 0x00010000 0x00004000>; +- +- data-only@0 { +- compatible = "fsl,qe-muram-data", +- "fsl,cpm-muram-data"; +- reg = <0x0 0x4000>; +- }; +- }; +- +- spi@4c0 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl,spi"; +- reg = <0x4c0 0x40>; +- interrupts = <2>; +- interrupt-parent = <&qeic>; +- cs-gpios = <&qe_pio_d 13 0>; +- mode = "cpu-qe"; +- +- mmc-slot@0 { +- compatible = "fsl,mpc8323rdb-mmc-slot", +- "mmc-spi-slot"; +- reg = <0>; +- gpios = <&qe_pio_d 14 1 +- &qe_pio_d 15 0>; +- voltage-ranges = <3300 3300>; +- spi-max-frequency = <50000000>; +- }; +- }; +- +- spi@500 { +- cell-index = <1>; +- compatible = "fsl,spi"; +- reg = <0x500 0x40>; +- interrupts = <1>; +- interrupt-parent = <&qeic>; +- mode = "cpu"; +- }; +- +- enet0: ucc@3000 { +- device_type = "network"; +- compatible = "ucc_geth"; +- cell-index = <2>; +- reg = <0x3000 0x200>; +- interrupts = <33>; +- interrupt-parent = <&qeic>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "clk16"; +- tx-clock-name = "clk3"; +- phy-handle = <&phy00>; +- pio-handle = <&ucc2pio>; +- }; +- +- enet1: ucc@2200 { +- device_type = "network"; +- compatible = "ucc_geth"; +- cell-index = <3>; +- reg = <0x2200 0x200>; +- interrupts = <34>; +- interrupt-parent = <&qeic>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "clk9"; +- tx-clock-name = "clk10"; +- phy-handle = <&phy04>; +- pio-handle = <&ucc3pio>; +- }; +- +- mdio@3120 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x3120 0x18>; +- compatible = "fsl,ucc-mdio"; +- +- phy00:ethernet-phy@0 { +- reg = <0x0>; +- }; +- phy04:ethernet-phy@4 { +- reg = <0x4>; +- }; +- }; +- +- qeic:interrupt-controller@80 { +- interrupt-controller; +- compatible = "fsl,qe-ic"; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x80 0x80>; +- big-endian; +- interrupts = <32 0x8 33 0x8>; //high:32 low:33 +- interrupt-parent = <&ipic>; +- }; +- }; +- +- pci0: pci@e0008500 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x10 AD16 (USB) */ +- 0x8000 0x0 0x0 0x1 &ipic 17 0x8 +- +- /* IDSEL 0x11 AD17 (Mini1)*/ +- 0x8800 0x0 0x0 0x1 &ipic 18 0x8 +- 0x8800 0x0 0x0 0x2 &ipic 19 0x8 +- 0x8800 0x0 0x0 0x3 &ipic 20 0x8 +- 0x8800 0x0 0x0 0x4 &ipic 48 0x8 +- +- /* IDSEL 0x12 AD18 (PCI/Mini2) */ +- 0x9000 0x0 0x0 0x1 &ipic 19 0x8 +- 0x9000 0x0 0x0 0x2 &ipic 20 0x8 +- 0x9000 0x0 0x0 0x3 &ipic 48 0x8 +- 0x9000 0x0 0x0 0x4 &ipic 17 0x8>; +- +- interrupt-parent = <&ipic>; +- interrupts = <66 0x8>; +- bus-range = <0x0 0x0>; +- ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 +- 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 +- 0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>; +- clock-frequency = <0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008500 0x100 /* internal registers */ +- 0xe0008300 0x8>; /* config space access registers */ +- compatible = "fsl,mpc8349-pci"; +- device_type = "pci"; +- sleep = <&pmc 0x00010000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc8349emitx.dts b/scripts/dtc/include-prefixes/powerpc/mpc8349emitx.dts +deleted file mode 100644 +index d4ebbb93de0b..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc8349emitx.dts ++++ /dev/null +@@ -1,421 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8349E-mITX Device Tree Source +- * +- * Copyright 2006 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/ { +- model = "MPC8349EMITX"; +- compatible = "MPC8349EMITX", "MPC834xMITX", "MPC83xxMITX"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- pci1 = &pci1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8349@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- timebase-frequency = <0>; // from bootloader +- bus-frequency = <0>; // from bootloader +- clock-frequency = <0>; // from bootloader +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- soc8349@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- ranges = <0x0 0xe0000000 0x00100000>; +- reg = <0xe0000000 0x00000200>; +- bus-frequency = <0>; // from bootloader +- +- wdt@200 { +- device_type = "watchdog"; +- compatible = "mpc83xx_wdt"; +- reg = <0x200 0x100>; +- }; +- +- gpio1: gpio-controller@c00 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8349-gpio"; +- reg = <0xc00 0x100>; +- interrupts = <74 0x8>; +- interrupt-parent = <&ipic>; +- gpio-controller; +- }; +- +- gpio2: gpio-controller@d00 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8349-gpio"; +- reg = <0xd00 0x100>; +- interrupts = <75 0x8>; +- interrupt-parent = <&ipic>; +- gpio-controller; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- +- eeprom: at24@50 { +- compatible = "st,24c256", "atmel,24c256"; +- reg = <0x50>; +- }; +- +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <15 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- interrupts = <18 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- pcf1: iexp@38 { +- #gpio-cells = <2>; +- compatible = "ti,pcf8574a"; +- reg = <0x38>; +- gpio-controller; +- }; +- +- pcf2: iexp@39 { +- #gpio-cells = <2>; +- compatible = "ti,pcf8574a"; +- reg = <0x39>; +- gpio-controller; +- }; +- +- spd: at24@51 { +- compatible = "atmel,spd"; +- reg = <0x51>; +- }; +- +- mcu_pio: mcu@a { +- #gpio-cells = <2>; +- compatible = "fsl,mc9s08qg8-mpc8349emitx", +- "fsl,mcu-mpc8349emitx"; +- reg = <0x0a>; +- gpio-controller; +- }; +- }; +- +- spi@7000 { +- cell-index = <0>; +- compatible = "fsl,spi"; +- reg = <0x7000 0x1000>; +- interrupts = <16 0x8>; +- interrupt-parent = <&ipic>; +- mode = "cpu"; +- }; +- +- dma@82a8 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; +- reg = <0x82a8 4>; +- ranges = <0 0x8100 0x1a8>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; +- reg = <0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x180 0x28>; +- cell-index = <3>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- }; +- +- usb@22000 { +- compatible = "fsl-usb2-mph"; +- reg = <0x22000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <39 0x8>; +- phy_type = "ulpi"; +- port0; +- }; +- +- usb@23000 { +- compatible = "fsl-usb2-dr"; +- reg = <0x23000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <38 0x8>; +- dr_mode = "peripheral"; +- phy_type = "ulpi"; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <32 0x8 33 0x8 34 0x8>; +- interrupt-parent = <&ipic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy1c>; +- linux,network-index = <0>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- /* Vitesse 8201 */ +- phy1c: ethernet-phy@1c { +- interrupt-parent = <&ipic>; +- interrupts = <18 0x8>; +- reg = <0x1c>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 0x8 36 0x8 37 0x8>; +- interrupt-parent = <&ipic>; +- /* Vitesse 7385 isn't on the MDIO bus */ +- fixed-link = <1 1 1000 0 0>; +- linux,network-index = <1>; +- tbi-handle = <&tbi1>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; // from bootloader +- interrupts = <9 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; // from bootloader +- interrupts = <10 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <11 0x8>; +- interrupt-parent = <&ipic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x7e>; +- fsl,descriptor-types-mask = <0x01010ebf>; +- }; +- +- ipic: pic@700 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x700 0x100>; +- device_type = "ipic"; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- green { +- label = "Green"; +- gpios = <&pcf1 0 1>; +- linux,default-trigger = "heartbeat"; +- }; +- +- yellow { +- label = "Yellow"; +- gpios = <&pcf1 1 1>; +- /* linux,default-trigger = "heartbeat"; */ +- default-state = "on"; +- }; +- }; +- +- }; +- +- pci0: pci@e0008500 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x10 - SATA */ +- 0x8000 0x0 0x0 0x1 &ipic 22 0x8 /* SATA_INTA */ +- >; +- interrupt-parent = <&ipic>; +- interrupts = <66 0x8>; +- bus-range = <0x0 0x0>; +- ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 +- 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008500 0x100 /* internal registers */ +- 0xe0008300 0x8>; /* config space access registers */ +- compatible = "fsl,mpc8349-pci"; +- device_type = "pci"; +- }; +- +- pci1: pci@e0008600 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x0E - MiniPCI Slot */ +- 0x7000 0x0 0x0 0x1 &ipic 21 0x8 /* PCI_INTA */ +- +- /* IDSEL 0x0F - PCI Slot */ +- 0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */ +- 0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */ +- >; +- interrupt-parent = <&ipic>; +- interrupts = <67 0x8>; +- bus-range = <0x0 0x0>; +- ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 +- 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008600 0x100 /* internal registers */ +- 0xe0008380 0x8>; /* config space access registers */ +- compatible = "fsl,mpc8349-pci"; +- device_type = "pci"; +- }; +- +- localbus@e0005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8349e-localbus", +- "fsl,pq2pro-localbus", +- "simple-bus"; +- reg = <0xe0005000 0xd8>; +- ranges = <0x0 0x0 0xfe000000 0x1000000 /* flash */ +- 0x1 0x0 0xf8000000 0x20000 /* VSC 7385 */ +- 0x2 0x0 0xf9000000 0x200000 /* exp slot */ +- 0x3 0x0 0xf0000000 0x210>; /* CF slot */ +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x800000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- flash@0,800000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x800000 0x800000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- pata@3,0 { +- compatible = "fsl,mpc8349emitx-pata", "ata-generic"; +- reg = <0x3 0x0 0x10 0x3 0x20c 0x4>; +- reg-shift = <1>; +- pio-mode = <6>; +- interrupts = <23 0x8>; +- interrupt-parent = <&ipic>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc8349emitxgp.dts b/scripts/dtc/include-prefixes/powerpc/mpc8349emitxgp.dts +deleted file mode 100644 +index bcf68a0a7b55..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc8349emitxgp.dts ++++ /dev/null +@@ -1,246 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8349E-mITX-GP Device Tree Source +- * +- * Copyright 2007 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/ { +- model = "MPC8349EMITXGP"; +- compatible = "MPC8349EMITXGP", "MPC834xMITX", "MPC83xxMITX"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8349@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- timebase-frequency = <0>; // from bootloader +- bus-frequency = <0>; // from bootloader +- clock-frequency = <0>; // from bootloader +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- soc8349@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- ranges = <0x0 0xe0000000 0x00100000>; +- reg = <0xe0000000 0x00000200>; +- bus-frequency = <0>; // from bootloader +- +- wdt@200 { +- device_type = "watchdog"; +- compatible = "mpc83xx_wdt"; +- reg = <0x200 0x100>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <15 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- interrupts = <18 0x8>; +- interrupt-parent = <&ipic>; +- }; +- }; +- +- spi@7000 { +- cell-index = <0>; +- compatible = "fsl,spi"; +- reg = <0x7000 0x1000>; +- interrupts = <16 0x8>; +- interrupt-parent = <&ipic>; +- mode = "cpu"; +- }; +- +- dma@82a8 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; +- reg = <0x82a8 4>; +- ranges = <0 0x8100 0x1a8>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; +- reg = <0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x180 0x28>; +- cell-index = <3>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- }; +- +- usb@23000 { +- compatible = "fsl-usb2-dr"; +- reg = <0x23000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <38 0x8>; +- dr_mode = "otg"; +- phy_type = "ulpi"; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <32 0x8 33 0x8 34 0x8>; +- interrupt-parent = <&ipic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy1c>; +- linux,network-index = <0>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- /* Vitesse 8201 */ +- phy1c: ethernet-phy@1c { +- interrupt-parent = <&ipic>; +- interrupts = <18 0x8>; +- reg = <0x1c>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; // from bootloader +- interrupts = <9 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; // from bootloader +- interrupts = <10 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <11 0x8>; +- interrupt-parent = <&ipic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x7e>; +- fsl,descriptor-types-mask = <0x01010ebf>; +- }; +- +- ipic: pic@700 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x700 0x100>; +- device_type = "ipic"; +- }; +- }; +- +- pci0: pci@e0008600 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x0F - PCI Slot */ +- 0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */ +- 0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */ +- >; +- interrupt-parent = <&ipic>; +- interrupts = <67 0x8>; +- bus-range = <0x1 0x1>; +- ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 +- 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008600 0x100 /* internal registers */ +- 0xe0008380 0x8>; /* config space access registers */ +- compatible = "fsl,mpc8349-pci"; +- device_type = "pci"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc834x_mds.dts b/scripts/dtc/include-prefixes/powerpc/mpc834x_mds.dts +deleted file mode 100644 +index 6c8cb859c55f..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc834x_mds.dts ++++ /dev/null +@@ -1,403 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8349E MDS Device Tree Source +- * +- * Copyright 2005, 2006 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/ { +- model = "MPC8349EMDS"; +- compatible = "MPC8349EMDS", "MPC834xMDS", "MPC83xxMDS"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- pci1 = &pci1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8349@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- timebase-frequency = <0>; // from bootloader +- bus-frequency = <0>; // from bootloader +- clock-frequency = <0>; // from bootloader +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; // 256MB at 0 +- }; +- +- bcsr@e2400000 { +- compatible = "fsl,mpc8349mds-bcsr"; +- reg = <0xe2400000 0x8000>; +- }; +- +- soc8349@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- ranges = <0x0 0xe0000000 0x00100000>; +- reg = <0xe0000000 0x00000200>; +- bus-frequency = <0>; +- +- wdt@200 { +- device_type = "watchdog"; +- compatible = "mpc83xx_wdt"; +- reg = <0x200 0x100>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- +- rtc@68 { +- compatible = "dallas,ds1374"; +- reg = <0x68>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <15 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- }; +- +- spi@7000 { +- cell-index = <0>; +- compatible = "fsl,spi"; +- reg = <0x7000 0x1000>; +- interrupts = <16 0x8>; +- interrupt-parent = <&ipic>; +- mode = "cpu"; +- }; +- +- dma@82a8 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; +- reg = <0x82a8 4>; +- ranges = <0 0x8100 0x1a8>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; +- reg = <0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x180 0x28>; +- cell-index = <3>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- }; +- +- /* phy type (ULPI or SERIAL) are only types supported for MPH */ +- /* port = 0 or 1 */ +- usb@22000 { +- compatible = "fsl-usb2-mph"; +- reg = <0x22000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <39 0x8>; +- phy_type = "ulpi"; +- port0; +- }; +- /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ +- usb@23000 { +- compatible = "fsl-usb2-dr"; +- reg = <0x23000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <38 0x8>; +- dr_mode = "otg"; +- phy_type = "ulpi"; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <32 0x8 33 0x8 34 0x8>; +- interrupt-parent = <&ipic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- linux,network-index = <0>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy0: ethernet-phy@0 { +- interrupt-parent = <&ipic>; +- interrupts = <17 0x8>; +- reg = <0x0>; +- }; +- +- phy1: ethernet-phy@1 { +- interrupt-parent = <&ipic>; +- interrupts = <18 0x8>; +- reg = <0x1>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 0x8 36 0x8 37 0x8>; +- interrupt-parent = <&ipic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- linux,network-index = <1>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- interrupts = <9 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- interrupts = <10 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <11 0x8>; +- interrupt-parent = <&ipic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x7e>; +- fsl,descriptor-types-mask = <0x01010ebf>; +- }; +- +- /* IPIC +- * interrupts cell = +- * sense values match linux IORESOURCE_IRQ_* defines: +- * sense == 8: Level, low assertion +- * sense == 2: Edge, high-to-low change +- */ +- ipic: pic@700 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x700 0x100>; +- device_type = "ipic"; +- }; +- }; +- +- pci0: pci@e0008500 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x11 */ +- 0x8800 0x0 0x0 0x1 &ipic 20 0x8 +- 0x8800 0x0 0x0 0x2 &ipic 21 0x8 +- 0x8800 0x0 0x0 0x3 &ipic 22 0x8 +- 0x8800 0x0 0x0 0x4 &ipic 23 0x8 +- +- /* IDSEL 0x12 */ +- 0x9000 0x0 0x0 0x1 &ipic 22 0x8 +- 0x9000 0x0 0x0 0x2 &ipic 23 0x8 +- 0x9000 0x0 0x0 0x3 &ipic 20 0x8 +- 0x9000 0x0 0x0 0x4 &ipic 21 0x8 +- +- /* IDSEL 0x13 */ +- 0x9800 0x0 0x0 0x1 &ipic 23 0x8 +- 0x9800 0x0 0x0 0x2 &ipic 20 0x8 +- 0x9800 0x0 0x0 0x3 &ipic 21 0x8 +- 0x9800 0x0 0x0 0x4 &ipic 22 0x8 +- +- /* IDSEL 0x15 */ +- 0xa800 0x0 0x0 0x1 &ipic 20 0x8 +- 0xa800 0x0 0x0 0x2 &ipic 21 0x8 +- 0xa800 0x0 0x0 0x3 &ipic 22 0x8 +- 0xa800 0x0 0x0 0x4 &ipic 23 0x8 +- +- /* IDSEL 0x16 */ +- 0xb000 0x0 0x0 0x1 &ipic 23 0x8 +- 0xb000 0x0 0x0 0x2 &ipic 20 0x8 +- 0xb000 0x0 0x0 0x3 &ipic 21 0x8 +- 0xb000 0x0 0x0 0x4 &ipic 22 0x8 +- +- /* IDSEL 0x17 */ +- 0xb800 0x0 0x0 0x1 &ipic 22 0x8 +- 0xb800 0x0 0x0 0x2 &ipic 23 0x8 +- 0xb800 0x0 0x0 0x3 &ipic 20 0x8 +- 0xb800 0x0 0x0 0x4 &ipic 21 0x8 +- +- /* IDSEL 0x18 */ +- 0xc000 0x0 0x0 0x1 &ipic 21 0x8 +- 0xc000 0x0 0x0 0x2 &ipic 22 0x8 +- 0xc000 0x0 0x0 0x3 &ipic 23 0x8 +- 0xc000 0x0 0x0 0x4 &ipic 20 0x8>; +- interrupt-parent = <&ipic>; +- interrupts = <66 0x8>; +- bus-range = <0 0>; +- ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 +- 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008500 0x100 /* internal registers */ +- 0xe0008300 0x8>; /* config space access registers */ +- compatible = "fsl,mpc8349-pci"; +- device_type = "pci"; +- }; +- +- pci1: pci@e0008600 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x11 */ +- 0x8800 0x0 0x0 0x1 &ipic 20 0x8 +- 0x8800 0x0 0x0 0x2 &ipic 21 0x8 +- 0x8800 0x0 0x0 0x3 &ipic 22 0x8 +- 0x8800 0x0 0x0 0x4 &ipic 23 0x8 +- +- /* IDSEL 0x12 */ +- 0x9000 0x0 0x0 0x1 &ipic 22 0x8 +- 0x9000 0x0 0x0 0x2 &ipic 23 0x8 +- 0x9000 0x0 0x0 0x3 &ipic 20 0x8 +- 0x9000 0x0 0x0 0x4 &ipic 21 0x8 +- +- /* IDSEL 0x13 */ +- 0x9800 0x0 0x0 0x1 &ipic 23 0x8 +- 0x9800 0x0 0x0 0x2 &ipic 20 0x8 +- 0x9800 0x0 0x0 0x3 &ipic 21 0x8 +- 0x9800 0x0 0x0 0x4 &ipic 22 0x8 +- +- /* IDSEL 0x15 */ +- 0xa800 0x0 0x0 0x1 &ipic 20 0x8 +- 0xa800 0x0 0x0 0x2 &ipic 21 0x8 +- 0xa800 0x0 0x0 0x3 &ipic 22 0x8 +- 0xa800 0x0 0x0 0x4 &ipic 23 0x8 +- +- /* IDSEL 0x16 */ +- 0xb000 0x0 0x0 0x1 &ipic 23 0x8 +- 0xb000 0x0 0x0 0x2 &ipic 20 0x8 +- 0xb000 0x0 0x0 0x3 &ipic 21 0x8 +- 0xb000 0x0 0x0 0x4 &ipic 22 0x8 +- +- /* IDSEL 0x17 */ +- 0xb800 0x0 0x0 0x1 &ipic 22 0x8 +- 0xb800 0x0 0x0 0x2 &ipic 23 0x8 +- 0xb800 0x0 0x0 0x3 &ipic 20 0x8 +- 0xb800 0x0 0x0 0x4 &ipic 21 0x8 +- +- /* IDSEL 0x18 */ +- 0xc000 0x0 0x0 0x1 &ipic 21 0x8 +- 0xc000 0x0 0x0 0x2 &ipic 22 0x8 +- 0xc000 0x0 0x0 0x3 &ipic 23 0x8 +- 0xc000 0x0 0x0 0x4 &ipic 20 0x8>; +- interrupt-parent = <&ipic>; +- interrupts = <67 0x8>; +- bus-range = <0 0>; +- ranges = <0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000 +- 0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xe2100000 0x0 0x00100000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008600 0x100 /* internal registers */ +- 0xe0008380 0x8>; /* config space access registers */ +- compatible = "fsl,mpc8349-pci"; +- device_type = "pci"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc836x_mds.dts b/scripts/dtc/include-prefixes/powerpc/mpc836x_mds.dts +deleted file mode 100644 +index f4ca12ec57f1..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc836x_mds.dts ++++ /dev/null +@@ -1,481 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8360E EMDS Device Tree Source +- * +- * Copyright 2006 Freescale Semiconductor Inc. +- */ +- +- +-/* +-/memreserve/ 00000000 1000000; +-*/ +- +-/dts-v1/; +- +-/ { +- model = "MPC8360MDS"; +- compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8360@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <32768>; // L1, 32K +- i-cache-size = <32768>; // L1, 32K +- timebase-frequency = <66000000>; +- bus-frequency = <264000000>; +- clock-frequency = <528000000>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- localbus@e0005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", +- "simple-bus"; +- reg = <0xe0005000 0xd8>; +- ranges = <0 0 0xfe000000 0x02000000 +- 1 0 0xf8000000 0x00008000>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x2000000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- bcsr@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8360mds-bcsr"; +- reg = <1 0 0x8000>; +- ranges = <0 1 0 0x8000>; +- +- bcsr13: gpio-controller@d { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8360mds-bcsr-gpio"; +- reg = <0xd 1>; +- gpio-controller; +- }; +- }; +- }; +- +- soc8360@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- ranges = <0x0 0xe0000000 0x00100000>; +- reg = <0xe0000000 0x00000200>; +- bus-frequency = <264000000>; +- +- wdt@200 { +- device_type = "watchdog"; +- compatible = "mpc83xx_wdt"; +- reg = <0x200 0x100>; +- }; +- +- pmc: power@b00 { +- compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc"; +- reg = <0xb00 0x100 0xa00 0x100>; +- interrupts = <80 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- +- rtc@68 { +- compatible = "dallas,ds1374"; +- reg = <0x68>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <15 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <264000000>; +- interrupts = <9 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <264000000>; +- interrupts = <10 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- dma@82a8 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8360-dma", "fsl,elo-dma"; +- reg = <0x82a8 4>; +- ranges = <0 0x8100 0x1a8>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; +- reg = <0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x180 0x28>; +- cell-index = <3>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <11 0x8>; +- interrupt-parent = <&ipic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x7e>; +- fsl,descriptor-types-mask = <0x01010ebf>; +- sleep = <&pmc 0x03000000>; +- }; +- +- ipic: pic@700 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x700 0x100>; +- device_type = "ipic"; +- }; +- +- par_io@1400 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x1400 0x100>; +- ranges = <0 0x1400 0x100>; +- device_type = "par_io"; +- num-ports = <7>; +- +- qe_pio_b: gpio-controller@18 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8360-qe-pario-bank", +- "fsl,mpc8323-qe-pario-bank"; +- reg = <0x18 0x18>; +- gpio-controller; +- }; +- +- pio1: ucc_pin@1 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0 3 1 0 1 0 /* TxD0 */ +- 0 4 1 0 1 0 /* TxD1 */ +- 0 5 1 0 1 0 /* TxD2 */ +- 0 6 1 0 1 0 /* TxD3 */ +- 1 6 1 0 3 0 /* TxD4 */ +- 1 7 1 0 1 0 /* TxD5 */ +- 1 9 1 0 2 0 /* TxD6 */ +- 1 10 1 0 2 0 /* TxD7 */ +- 0 9 2 0 1 0 /* RxD0 */ +- 0 10 2 0 1 0 /* RxD1 */ +- 0 11 2 0 1 0 /* RxD2 */ +- 0 12 2 0 1 0 /* RxD3 */ +- 0 13 2 0 1 0 /* RxD4 */ +- 1 1 2 0 2 0 /* RxD5 */ +- 1 0 2 0 2 0 /* RxD6 */ +- 1 4 2 0 2 0 /* RxD7 */ +- 0 7 1 0 1 0 /* TX_EN */ +- 0 8 1 0 1 0 /* TX_ER */ +- 0 15 2 0 1 0 /* RX_DV */ +- 0 16 2 0 1 0 /* RX_ER */ +- 0 0 2 0 1 0 /* RX_CLK */ +- 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ +- 2 8 2 0 1 0>; /* GTX125 - CLK9 */ +- }; +- pio2: ucc_pin@2 { +- pio-map = < +- /* port pin dir open_drain assignment has_irq */ +- 0 17 1 0 1 0 /* TxD0 */ +- 0 18 1 0 1 0 /* TxD1 */ +- 0 19 1 0 1 0 /* TxD2 */ +- 0 20 1 0 1 0 /* TxD3 */ +- 1 2 1 0 1 0 /* TxD4 */ +- 1 3 1 0 2 0 /* TxD5 */ +- 1 5 1 0 3 0 /* TxD6 */ +- 1 8 1 0 3 0 /* TxD7 */ +- 0 23 2 0 1 0 /* RxD0 */ +- 0 24 2 0 1 0 /* RxD1 */ +- 0 25 2 0 1 0 /* RxD2 */ +- 0 26 2 0 1 0 /* RxD3 */ +- 0 27 2 0 1 0 /* RxD4 */ +- 1 12 2 0 2 0 /* RxD5 */ +- 1 13 2 0 3 0 /* RxD6 */ +- 1 11 2 0 2 0 /* RxD7 */ +- 0 21 1 0 1 0 /* TX_EN */ +- 0 22 1 0 1 0 /* TX_ER */ +- 0 29 2 0 1 0 /* RX_DV */ +- 0 30 2 0 1 0 /* RX_ER */ +- 0 31 2 0 1 0 /* RX_CLK */ +- 2 2 1 0 2 0 /* GTX_CLK - CLK10 */ +- 2 3 2 0 1 0 /* GTX125 - CLK4 */ +- 0 1 3 0 2 0 /* MDIO */ +- 0 2 1 0 1 0>; /* MDC */ +- }; +- +- }; +- }; +- +- qe@e0100000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "qe"; +- compatible = "fsl,qe"; +- ranges = <0x0 0xe0100000 0x00100000>; +- reg = <0xe0100000 0x480>; +- brg-frequency = <0>; +- bus-frequency = <396000000>; +- fsl,qe-num-riscs = <2>; +- fsl,qe-num-snums = <28>; +- +- muram@10000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,qe-muram", "fsl,cpm-muram"; +- ranges = <0x0 0x00010000 0x0000c000>; +- +- data-only@0 { +- compatible = "fsl,qe-muram-data", +- "fsl,cpm-muram-data"; +- reg = <0x0 0xc000>; +- }; +- }; +- +- timer@440 { +- compatible = "fsl,mpc8360-qe-gtm", +- "fsl,qe-gtm", "fsl,gtm"; +- reg = <0x440 0x40>; +- clock-frequency = <132000000>; +- interrupts = <12 13 14 15>; +- interrupt-parent = <&qeic>; +- }; +- +- spi@4c0 { +- cell-index = <0>; +- compatible = "fsl,spi"; +- reg = <0x4c0 0x40>; +- interrupts = <2>; +- interrupt-parent = <&qeic>; +- mode = "cpu"; +- }; +- +- spi@500 { +- cell-index = <1>; +- compatible = "fsl,spi"; +- reg = <0x500 0x40>; +- interrupts = <1>; +- interrupt-parent = <&qeic>; +- mode = "cpu"; +- }; +- +- usb@6c0 { +- compatible = "fsl,mpc8360-qe-usb", +- "fsl,mpc8323-qe-usb"; +- reg = <0x6c0 0x40 0x8b00 0x100>; +- interrupts = <11>; +- interrupt-parent = <&qeic>; +- fsl,fullspeed-clock = "clk21"; +- fsl,lowspeed-clock = "brg9"; +- gpios = <&qe_pio_b 2 0 /* USBOE */ +- &qe_pio_b 3 0 /* USBTP */ +- &qe_pio_b 8 0 /* USBTN */ +- &qe_pio_b 9 0 /* USBRP */ +- &qe_pio_b 11 0 /* USBRN */ +- &bcsr13 5 0 /* SPEED */ +- &bcsr13 4 1>; /* POWER */ +- }; +- +- enet0: ucc@2000 { +- device_type = "network"; +- compatible = "ucc_geth"; +- cell-index = <1>; +- reg = <0x2000 0x200>; +- interrupts = <32>; +- interrupt-parent = <&qeic>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "none"; +- tx-clock-name = "clk9"; +- phy-handle = <&phy0>; +- phy-connection-type = "rgmii-id"; +- pio-handle = <&pio1>; +- }; +- +- enet1: ucc@3000 { +- device_type = "network"; +- compatible = "ucc_geth"; +- cell-index = <2>; +- reg = <0x3000 0x200>; +- interrupts = <33>; +- interrupt-parent = <&qeic>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- rx-clock-name = "none"; +- tx-clock-name = "clk4"; +- phy-handle = <&phy1>; +- phy-connection-type = "rgmii-id"; +- pio-handle = <&pio2>; +- }; +- +- mdio@2120 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x2120 0x18>; +- compatible = "fsl,ucc-mdio"; +- +- phy0: ethernet-phy@0 { +- interrupt-parent = <&ipic>; +- interrupts = <17 0x8>; +- reg = <0x0>; +- }; +- phy1: ethernet-phy@1 { +- interrupt-parent = <&ipic>; +- interrupts = <18 0x8>; +- reg = <0x1>; +- }; +- tbi-phy@2 { +- device_type = "tbi-phy"; +- reg = <0x2>; +- }; +- }; +- +- qeic: interrupt-controller@80 { +- interrupt-controller; +- compatible = "fsl,qe-ic"; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- reg = <0x80 0x80>; +- big-endian; +- interrupts = <32 0x8 33 0x8>; // high:32 low:33 +- interrupt-parent = <&ipic>; +- }; +- }; +- +- pci0: pci@e0008500 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x11 AD17 */ +- 0x8800 0x0 0x0 0x1 &ipic 20 0x8 +- 0x8800 0x0 0x0 0x2 &ipic 21 0x8 +- 0x8800 0x0 0x0 0x3 &ipic 22 0x8 +- 0x8800 0x0 0x0 0x4 &ipic 23 0x8 +- +- /* IDSEL 0x12 AD18 */ +- 0x9000 0x0 0x0 0x1 &ipic 22 0x8 +- 0x9000 0x0 0x0 0x2 &ipic 23 0x8 +- 0x9000 0x0 0x0 0x3 &ipic 20 0x8 +- 0x9000 0x0 0x0 0x4 &ipic 21 0x8 +- +- /* IDSEL 0x13 AD19 */ +- 0x9800 0x0 0x0 0x1 &ipic 23 0x8 +- 0x9800 0x0 0x0 0x2 &ipic 20 0x8 +- 0x9800 0x0 0x0 0x3 &ipic 21 0x8 +- 0x9800 0x0 0x0 0x4 &ipic 22 0x8 +- +- /* IDSEL 0x15 AD21*/ +- 0xa800 0x0 0x0 0x1 &ipic 20 0x8 +- 0xa800 0x0 0x0 0x2 &ipic 21 0x8 +- 0xa800 0x0 0x0 0x3 &ipic 22 0x8 +- 0xa800 0x0 0x0 0x4 &ipic 23 0x8 +- +- /* IDSEL 0x16 AD22*/ +- 0xb000 0x0 0x0 0x1 &ipic 23 0x8 +- 0xb000 0x0 0x0 0x2 &ipic 20 0x8 +- 0xb000 0x0 0x0 0x3 &ipic 21 0x8 +- 0xb000 0x0 0x0 0x4 &ipic 22 0x8 +- +- /* IDSEL 0x17 AD23*/ +- 0xb800 0x0 0x0 0x1 &ipic 22 0x8 +- 0xb800 0x0 0x0 0x2 &ipic 23 0x8 +- 0xb800 0x0 0x0 0x3 &ipic 20 0x8 +- 0xb800 0x0 0x0 0x4 &ipic 21 0x8 +- +- /* IDSEL 0x18 AD24*/ +- 0xc000 0x0 0x0 0x1 &ipic 21 0x8 +- 0xc000 0x0 0x0 0x2 &ipic 22 0x8 +- 0xc000 0x0 0x0 0x3 &ipic 23 0x8 +- 0xc000 0x0 0x0 0x4 &ipic 20 0x8>; +- interrupt-parent = <&ipic>; +- interrupts = <66 0x8>; +- bus-range = <0 0>; +- ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 +- 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008500 0x100 /* internal registers */ +- 0xe0008300 0x8>; /* config space access registers */ +- compatible = "fsl,mpc8349-pci"; +- device_type = "pci"; +- sleep = <&pmc 0x00010000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc836x_rdk.dts b/scripts/dtc/include-prefixes/powerpc/mpc836x_rdk.dts +deleted file mode 100644 +index a0cc1953484d..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc836x_rdk.dts ++++ /dev/null +@@ -1,463 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8360E RDK Device Tree Source +- * +- * Copyright 2006 Freescale Semiconductor Inc. +- * Copyright 2007-2008 MontaVista Software, Inc. +- * +- * Author: Anton Vorontsov +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8360rdk"; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- serial3 = &serial3; +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8360@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- /* filled by u-boot */ +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- /* filled by u-boot */ +- reg = <0 0>; +- }; +- +- soc@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,mpc8360-immr", "fsl,immr", "fsl,soc", +- "simple-bus"; +- ranges = <0 0xe0000000 0x200000>; +- reg = <0xe0000000 0x200>; +- /* filled by u-boot */ +- bus-frequency = <0>; +- +- wdt@200 { +- compatible = "mpc83xx_wdt"; +- reg = <0x200 0x100>; +- }; +- +- pmc: power@b00 { +- compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc"; +- reg = <0xb00 0x100 0xa00 0x100>; +- interrupts = <80 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <16 8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- }; +- +- serial0: serial@4500 { +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- interrupts = <9 8>; +- interrupt-parent = <&ipic>; +- /* filled by u-boot */ +- clock-frequency = <0>; +- }; +- +- serial1: serial@4600 { +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- interrupts = <10 8>; +- interrupt-parent = <&ipic>; +- /* filled by u-boot */ +- clock-frequency = <0>; +- }; +- +- dma@82a8 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8360-dma", "fsl,elo-dma"; +- reg = <0x82a8 4>; +- ranges = <0 0x8100 0x1a8>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; +- reg = <0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x180 0x28>; +- cell-index = <3>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <11 0x8>; +- interrupt-parent = <&ipic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x7e>; +- fsl,descriptor-types-mask = <0x01010ebf>; +- sleep = <&pmc 0x03000000>; +- }; +- +- ipic: interrupt-controller@700 { +- #address-cells = <0>; +- #interrupt-cells = <2>; +- compatible = "fsl,pq2pro-pic", "fsl,ipic"; +- interrupt-controller; +- reg = <0x700 0x100>; +- }; +- +- qe_pio_b: gpio-controller@1418 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8360-qe-pario-bank", +- "fsl,mpc8323-qe-pario-bank"; +- reg = <0x1418 0x18>; +- gpio-controller; +- }; +- +- qe_pio_e: gpio-controller@1460 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8360-qe-pario-bank", +- "fsl,mpc8323-qe-pario-bank"; +- reg = <0x1460 0x18>; +- gpio-controller; +- }; +- +- qe@100000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "qe"; +- compatible = "fsl,qe", "simple-bus"; +- ranges = <0 0x100000 0x100000>; +- reg = <0x100000 0x480>; +- /* filled by u-boot */ +- clock-frequency = <0>; +- bus-frequency = <0>; +- brg-frequency = <0>; +- fsl,qe-num-riscs = <2>; +- fsl,qe-num-snums = <28>; +- +- muram@10000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,qe-muram", "fsl,cpm-muram"; +- ranges = <0 0x10000 0xc000>; +- +- data-only@0 { +- compatible = "fsl,qe-muram-data", +- "fsl,cpm-muram-data"; +- reg = <0 0xc000>; +- }; +- }; +- +- timer@440 { +- compatible = "fsl,mpc8360-qe-gtm", +- "fsl,qe-gtm", "fsl,gtm"; +- reg = <0x440 0x40>; +- interrupts = <12 13 14 15>; +- interrupt-parent = <&qeic>; +- clock-frequency = <166666666>; +- }; +- +- usb@6c0 { +- compatible = "fsl,mpc8360-qe-usb", +- "fsl,mpc8323-qe-usb"; +- reg = <0x6c0 0x40 0x8b00 0x100>; +- interrupts = <11>; +- interrupt-parent = <&qeic>; +- fsl,fullspeed-clock = "clk21"; +- gpios = <&qe_pio_b 2 0 /* USBOE */ +- &qe_pio_b 3 0 /* USBTP */ +- &qe_pio_b 8 0 /* USBTN */ +- &qe_pio_b 9 0 /* USBRP */ +- &qe_pio_b 11 0 /* USBRN */ +- &qe_pio_e 20 0 /* SPEED */ +- &qe_pio_e 21 1 /* POWER */>; +- }; +- +- spi@4c0 { +- cell-index = <0>; +- compatible = "fsl,spi"; +- reg = <0x4c0 0x40>; +- interrupts = <2>; +- interrupt-parent = <&qeic>; +- mode = "cpu-qe"; +- }; +- +- spi@500 { +- cell-index = <1>; +- compatible = "fsl,spi"; +- reg = <0x500 0x40>; +- interrupts = <1>; +- interrupt-parent = <&qeic>; +- mode = "cpu-qe"; +- }; +- +- enet0: ucc@2000 { +- device_type = "network"; +- compatible = "ucc_geth"; +- cell-index = <1>; +- reg = <0x2000 0x200>; +- interrupts = <32>; +- interrupt-parent = <&qeic>; +- rx-clock-name = "none"; +- tx-clock-name = "clk9"; +- phy-handle = <&phy2>; +- phy-connection-type = "rgmii-rxid"; +- /* filled by u-boot */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- +- enet1: ucc@3000 { +- device_type = "network"; +- compatible = "ucc_geth"; +- cell-index = <2>; +- reg = <0x3000 0x200>; +- interrupts = <33>; +- interrupt-parent = <&qeic>; +- rx-clock-name = "none"; +- tx-clock-name = "clk4"; +- phy-handle = <&phy4>; +- phy-connection-type = "rgmii-rxid"; +- /* filled by u-boot */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- +- enet2: ucc@2600 { +- device_type = "network"; +- compatible = "ucc_geth"; +- cell-index = <7>; +- reg = <0x2600 0x200>; +- interrupts = <42>; +- interrupt-parent = <&qeic>; +- rx-clock-name = "clk20"; +- tx-clock-name = "clk19"; +- phy-handle = <&phy1>; +- phy-connection-type = "mii"; +- /* filled by u-boot */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- +- enet3: ucc@3200 { +- device_type = "network"; +- compatible = "ucc_geth"; +- cell-index = <4>; +- reg = <0x3200 0x200>; +- interrupts = <35>; +- interrupt-parent = <&qeic>; +- rx-clock-name = "clk8"; +- tx-clock-name = "clk7"; +- phy-handle = <&phy3>; +- phy-connection-type = "mii"; +- /* filled by u-boot */ +- local-mac-address = [ 00 00 00 00 00 00 ]; +- }; +- +- mdio@2120 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,ucc-mdio"; +- reg = <0x2120 0x18>; +- +- phy1: ethernet-phy@1 { +- compatible = "national,DP83848VV"; +- reg = <1>; +- }; +- +- phy2: ethernet-phy@2 { +- compatible = "broadcom,BCM5481UA2KMLG"; +- reg = <2>; +- }; +- +- phy3: ethernet-phy@3 { +- compatible = "national,DP83848VV"; +- reg = <3>; +- }; +- +- phy4: ethernet-phy@4 { +- compatible = "broadcom,BCM5481UA2KMLG"; +- reg = <4>; +- }; +- }; +- +- serial2: ucc@2400 { +- device_type = "serial"; +- compatible = "ucc_uart"; +- reg = <0x2400 0x200>; +- cell-index = <5>; +- port-number = <0>; +- rx-clock-name = "brg7"; +- tx-clock-name = "brg8"; +- interrupts = <40>; +- interrupt-parent = <&qeic>; +- soft-uart; +- }; +- +- serial3: ucc@3400 { +- device_type = "serial"; +- compatible = "ucc_uart"; +- reg = <0x3400 0x200>; +- cell-index = <6>; +- port-number = <1>; +- rx-clock-name = "brg13"; +- tx-clock-name = "brg14"; +- interrupts = <41>; +- interrupt-parent = <&qeic>; +- soft-uart; +- }; +- +- qeic: interrupt-controller@80 { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- compatible = "fsl,qe-ic"; +- interrupt-controller; +- reg = <0x80 0x80>; +- big-endian; +- interrupts = <32 8 33 8>; +- interrupt-parent = <&ipic>; +- }; +- }; +- }; +- +- localbus@e0005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", +- "simple-bus"; +- reg = <0xe0005000 0xd8>; +- ranges = <0 0 0xff800000 0x0800000 +- 1 0 0x60000000 0x0001000 +- 2 0 0x70000000 0x4000000>; +- +- flash@0,0 { +- compatible = "intel,PC28F640P30T85", "cfi-flash"; +- reg = <0 0 0x800000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- upm@1,0 { +- compatible = "fsl,upm-nand"; +- reg = <1 0 1>; +- fsl,upm-addr-offset = <16>; +- fsl,upm-cmd-offset = <8>; +- gpios = <&qe_pio_e 18 0>; +- +- flash { +- compatible = "st,nand512-a"; +- }; +- }; +- +- display@2,0 { +- device_type = "display"; +- compatible = "fujitsu,MB86277", "fujitsu,mint"; +- reg = <2 0 0x4000000>; +- fujitsu,sh3; +- little-endian; +- /* filled by u-boot */ +- address = <0>; +- depth = <0>; +- width = <0>; +- height = <0>; +- linebytes = <0>; +- /* linux,opened; - added by uboot */ +- }; +- }; +- +- pci0: pci@e0008500 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "fsl,mpc8360-pci", "fsl,mpc8349-pci"; +- reg = <0xe0008500 0x100 /* internal registers */ +- 0xe0008300 0x8>; /* config space access registers */ +- ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 +- 0x42000000 0 0x80000000 0x80000000 0 0x10000000 +- 0x01000000 0 0xe0300000 0xe0300000 0 0x00100000>; +- interrupts = <66 8>; +- interrupt-parent = <&ipic>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = ; +- sleep = <&pmc 0x00010000>; +- /* filled by u-boot */ +- bus-range = <0 0>; +- clock-frequency = <0>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc8377_mds.dts b/scripts/dtc/include-prefixes/powerpc/mpc8377_mds.dts +deleted file mode 100644 +index 9227bce0e2f5..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc8377_mds.dts ++++ /dev/null +@@ -1,505 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8377E MDS Device Tree Source +- * +- * Copyright 2007 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/ { +- model = "fsl,mpc8377emds"; +- compatible = "fsl,mpc8377emds","fsl,mpc837xmds"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8377@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; // 512MB at 0 +- }; +- +- localbus@e0005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus"; +- reg = <0xe0005000 0x1000>; +- interrupts = <77 0x8>; +- interrupt-parent = <&ipic>; +- +- // booting from NOR flash +- ranges = <0 0x0 0xfe000000 0x02000000 +- 1 0x0 0xf8000000 0x00008000 +- 3 0x0 0xe0600000 0x00008000>; +- +- flash@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0 0x0 0x2000000>; +- bank-width = <2>; +- device-width = <1>; +- +- u-boot@0 { +- reg = <0x0 0x100000>; +- read-only; +- }; +- +- fs@100000 { +- reg = <0x100000 0x800000>; +- }; +- +- kernel@1d00000 { +- reg = <0x1d00000 0x200000>; +- }; +- +- dtb@1f00000 { +- reg = <0x1f00000 0x100000>; +- }; +- }; +- +- bcsr@1,0 { +- reg = <1 0x0 0x8000>; +- compatible = "fsl,mpc837xmds-bcsr"; +- }; +- +- nand@3,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8377-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <3 0x0 0x8000>; +- +- u-boot@0 { +- reg = <0x0 0x100000>; +- read-only; +- }; +- +- kernel@100000 { +- reg = <0x100000 0x300000>; +- }; +- +- fs@400000 { +- reg = <0x400000 0x1c00000>; +- }; +- }; +- }; +- +- soc@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- ranges = <0x0 0xe0000000 0x00100000>; +- reg = <0xe0000000 0x00000200>; +- bus-frequency = <0>; +- +- wdt@200 { +- compatible = "mpc83xx_wdt"; +- reg = <0x200 0x100>; +- }; +- +- sleep-nexus { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- sleep = <&pmc 0x0c000000>; +- ranges; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- +- rtc@68 { +- compatible = "dallas,ds1374"; +- reg = <0x68>; +- interrupts = <19 0x8>; +- interrupt-parent = <&ipic>; +- }; +- }; +- +- sdhci@2e000 { +- compatible = "fsl,mpc8377-esdhc", "fsl,esdhc"; +- reg = <0x2e000 0x1000>; +- interrupts = <42 0x8>; +- interrupt-parent = <&ipic>; +- sdhci,wp-inverted; +- /* Filled in by U-Boot */ +- clock-frequency = <0>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <15 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- }; +- +- spi@7000 { +- cell-index = <0>; +- compatible = "fsl,spi"; +- reg = <0x7000 0x1000>; +- interrupts = <16 0x8>; +- interrupt-parent = <&ipic>; +- mode = "cpu"; +- }; +- +- usb@23000 { +- compatible = "fsl-usb2-dr"; +- reg = <0x23000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <38 0x8>; +- dr_mode = "host"; +- phy_type = "ulpi"; +- sleep = <&pmc 0x00c00000>; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <32 0x8 33 0x8 34 0x8>; +- phy-connection-type = "mii"; +- interrupt-parent = <&ipic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy2>; +- sleep = <&pmc 0xc0000000>; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy2: ethernet-phy@2 { +- interrupt-parent = <&ipic>; +- interrupts = <17 0x8>; +- reg = <0x2>; +- }; +- +- phy3: ethernet-phy@3 { +- interrupt-parent = <&ipic>; +- interrupts = <18 0x8>; +- reg = <0x3>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 0x8 36 0x8 37 0x8>; +- phy-connection-type = "mii"; +- interrupt-parent = <&ipic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy3>; +- sleep = <&pmc 0x30000000>; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- interrupts = <9 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- interrupts = <10 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- dma@82a8 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8377-dma", "fsl,elo-dma"; +- reg = <0x82a8 4>; +- ranges = <0 0x8100 0x1a8>; +- interrupt-parent = <&ipic>; +- interrupts = <0x47 8>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; +- reg = <0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <0x47 8>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&ipic>; +- interrupts = <0x47 8>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&ipic>; +- interrupts = <0x47 8>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x180 0x28>; +- cell-index = <3>; +- interrupt-parent = <&ipic>; +- interrupts = <0x47 8>; +- }; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", +- "fsl,sec2.1", "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <11 0x8>; +- interrupt-parent = <&ipic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x9fe>; +- fsl,descriptor-types-mask = <0x3ab0ebf>; +- sleep = <&pmc 0x03000000>; +- }; +- +- sata@18000 { +- compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; +- reg = <0x18000 0x1000>; +- interrupts = <44 0x8>; +- interrupt-parent = <&ipic>; +- sleep = <&pmc 0x000000c0>; +- }; +- +- sata@19000 { +- compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; +- reg = <0x19000 0x1000>; +- interrupts = <45 0x8>; +- interrupt-parent = <&ipic>; +- sleep = <&pmc 0x00000030>; +- }; +- +- /* IPIC +- * interrupts cell = +- * sense values match linux IORESOURCE_IRQ_* defines: +- * sense == 8: Level, low assertion +- * sense == 2: Edge, high-to-low change +- */ +- ipic: pic@700 { +- compatible = "fsl,ipic"; +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x700 0x100>; +- }; +- +- pmc: power@b00 { +- compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc"; +- reg = <0xb00 0x100 0xa00 0x100>; +- interrupts = <80 0x8>; +- interrupt-parent = <&ipic>; +- }; +- }; +- +- pci0: pci@e0008500 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x11 */ +- 0x8800 0x0 0x0 0x1 &ipic 20 0x8 +- 0x8800 0x0 0x0 0x2 &ipic 21 0x8 +- 0x8800 0x0 0x0 0x3 &ipic 22 0x8 +- 0x8800 0x0 0x0 0x4 &ipic 23 0x8 +- +- /* IDSEL 0x12 */ +- 0x9000 0x0 0x0 0x1 &ipic 22 0x8 +- 0x9000 0x0 0x0 0x2 &ipic 23 0x8 +- 0x9000 0x0 0x0 0x3 &ipic 20 0x8 +- 0x9000 0x0 0x0 0x4 &ipic 21 0x8 +- +- /* IDSEL 0x13 */ +- 0x9800 0x0 0x0 0x1 &ipic 23 0x8 +- 0x9800 0x0 0x0 0x2 &ipic 20 0x8 +- 0x9800 0x0 0x0 0x3 &ipic 21 0x8 +- 0x9800 0x0 0x0 0x4 &ipic 22 0x8 +- +- /* IDSEL 0x15 */ +- 0xa800 0x0 0x0 0x1 &ipic 20 0x8 +- 0xa800 0x0 0x0 0x2 &ipic 21 0x8 +- 0xa800 0x0 0x0 0x3 &ipic 22 0x8 +- 0xa800 0x0 0x0 0x4 &ipic 23 0x8 +- +- /* IDSEL 0x16 */ +- 0xb000 0x0 0x0 0x1 &ipic 23 0x8 +- 0xb000 0x0 0x0 0x2 &ipic 20 0x8 +- 0xb000 0x0 0x0 0x3 &ipic 21 0x8 +- 0xb000 0x0 0x0 0x4 &ipic 22 0x8 +- +- /* IDSEL 0x17 */ +- 0xb800 0x0 0x0 0x1 &ipic 22 0x8 +- 0xb800 0x0 0x0 0x2 &ipic 23 0x8 +- 0xb800 0x0 0x0 0x3 &ipic 20 0x8 +- 0xb800 0x0 0x0 0x4 &ipic 21 0x8 +- +- /* IDSEL 0x18 */ +- 0xc000 0x0 0x0 0x1 &ipic 21 0x8 +- 0xc000 0x0 0x0 0x2 &ipic 22 0x8 +- 0xc000 0x0 0x0 0x3 &ipic 23 0x8 +- 0xc000 0x0 0x0 0x4 &ipic 20 0x8>; +- interrupt-parent = <&ipic>; +- interrupts = <66 0x8>; +- bus-range = <0x0 0x0>; +- ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 +- 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; +- sleep = <&pmc 0x00010000>; +- clock-frequency = <0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008500 0x100 /* internal registers */ +- 0xe0008300 0x8>; /* config space access registers */ +- compatible = "fsl,mpc8349-pci"; +- device_type = "pci"; +- }; +- +- pci1: pcie@e0009000 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie"; +- reg = <0xe0009000 0x00001000>; +- ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>; +- bus-range = <0 255>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0 0 0 1 &ipic 1 8 +- 0 0 0 2 &ipic 1 8 +- 0 0 0 3 &ipic 1 8 +- 0 0 0 4 &ipic 1 8>; +- sleep = <&pmc 0x00300000>; +- clock-frequency = <0>; +- +- pcie@0 { +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- reg = <0 0 0 0 0>; +- ranges = <0x02000000 0 0xa8000000 +- 0x02000000 0 0xa8000000 +- 0 0x10000000 +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00800000>; +- }; +- }; +- +- pci2: pcie@e000a000 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie"; +- reg = <0xe000a000 0x00001000>; +- ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>; +- bus-range = <0 255>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0 0 0 1 &ipic 2 8 +- 0 0 0 2 &ipic 2 8 +- 0 0 0 3 &ipic 2 8 +- 0 0 0 4 &ipic 2 8>; +- sleep = <&pmc 0x000c0000>; +- clock-frequency = <0>; +- +- pcie@0 { +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- reg = <0 0 0 0 0>; +- ranges = <0x02000000 0 0xc8000000 +- 0x02000000 0 0xc8000000 +- 0 0x10000000 +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00800000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc8377_rdb.dts b/scripts/dtc/include-prefixes/powerpc/mpc8377_rdb.dts +deleted file mode 100644 +index 7df452efa957..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc8377_rdb.dts ++++ /dev/null +@@ -1,498 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8377E RDB Device Tree Source +- * +- * Copyright 2007, 2008 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/ { +- compatible = "fsl,mpc8377rdb"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8377@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; // 256MB at 0 +- }; +- +- localbus@e0005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus"; +- reg = <0xe0005000 0x1000>; +- interrupts = <77 0x8>; +- interrupt-parent = <&ipic>; +- +- // CS0 and CS1 are swapped when +- // booting from nand, but the +- // addresses are the same. +- ranges = <0x0 0x0 0xfe000000 0x00800000 +- 0x1 0x0 0xe0600000 0x00008000 +- 0x2 0x0 0xf0000000 0x00020000 +- 0x3 0x0 0xfa000000 0x00008000>; +- +- flash@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x800000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8377-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x1 0x0 0x8000>; +- +- u-boot@0 { +- reg = <0x0 0x100000>; +- read-only; +- }; +- +- kernel@100000 { +- reg = <0x100000 0x300000>; +- }; +- fs@400000 { +- reg = <0x400000 0x1c00000>; +- }; +- }; +- }; +- +- immr@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- ranges = <0x0 0xe0000000 0x00100000>; +- reg = <0xe0000000 0x00000200>; +- bus-frequency = <0>; +- +- wdt@200 { +- device_type = "watchdog"; +- compatible = "mpc83xx_wdt"; +- reg = <0x200 0x100>; +- }; +- +- gpio1: gpio-controller@c00 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio"; +- reg = <0xc00 0x100>; +- interrupts = <74 0x8>; +- interrupt-parent = <&ipic>; +- gpio-controller; +- }; +- +- gpio2: gpio-controller@d00 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio"; +- reg = <0xd00 0x100>; +- interrupts = <75 0x8>; +- interrupt-parent = <&ipic>; +- gpio-controller; +- }; +- +- sleep-nexus { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- sleep = <&pmc 0x0c000000>; +- ranges; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- +- dtt@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +- +- at24@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +- +- mcu_pio: mcu@a { +- #gpio-cells = <2>; +- compatible = "fsl,mc9s08qg8-mpc8377erdb", +- "fsl,mcu-mpc8349emitx"; +- reg = <0x0a>; +- gpio-controller; +- }; +- }; +- +- sdhci@2e000 { +- compatible = "fsl,mpc8377-esdhc", "fsl,esdhc"; +- reg = <0x2e000 0x1000>; +- interrupts = <42 0x8>; +- interrupt-parent = <&ipic>; +- sdhci,wp-inverted; +- /* Filled in by U-Boot */ +- clock-frequency = <111111111>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <15 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- }; +- +- spi@7000 { +- cell-index = <0>; +- compatible = "fsl,spi"; +- reg = <0x7000 0x1000>; +- interrupts = <16 0x8>; +- interrupt-parent = <&ipic>; +- mode = "cpu"; +- }; +- +- dma@82a8 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8377-dma", "fsl,elo-dma"; +- reg = <0x82a8 4>; +- ranges = <0 0x8100 0x1a8>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; +- reg = <0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x180 0x28>; +- cell-index = <3>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- }; +- +- usb@23000 { +- compatible = "fsl-usb2-dr"; +- reg = <0x23000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <38 0x8>; +- phy_type = "ulpi"; +- sleep = <&pmc 0x00c00000>; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <32 0x8 33 0x8 34 0x8>; +- phy-connection-type = "mii"; +- interrupt-parent = <&ipic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy2>; +- sleep = <&pmc 0xc0000000>; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy2: ethernet-phy@2 { +- interrupt-parent = <&ipic>; +- interrupts = <17 0x8>; +- reg = <0x2>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 0x8 36 0x8 37 0x8>; +- phy-connection-type = "mii"; +- interrupt-parent = <&ipic>; +- fixed-link = <1 1 1000 0 0>; +- tbi-handle = <&tbi1>; +- sleep = <&pmc 0x30000000>; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- interrupts = <9 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- interrupts = <10 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", +- "fsl,sec2.1", "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <11 0x8>; +- interrupt-parent = <&ipic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x9fe>; +- fsl,descriptor-types-mask = <0x3ab0ebf>; +- sleep = <&pmc 0x03000000>; +- }; +- +- sata@18000 { +- compatible = "fsl,mpc8377-sata", "fsl,pq-sata"; +- reg = <0x18000 0x1000>; +- interrupts = <44 0x8>; +- interrupt-parent = <&ipic>; +- sleep = <&pmc 0x000000c0>; +- }; +- +- sata@19000 { +- compatible = "fsl,mpc8377-sata", "fsl,pq-sata"; +- reg = <0x19000 0x1000>; +- interrupts = <45 0x8>; +- interrupt-parent = <&ipic>; +- sleep = <&pmc 0x00000030>; +- }; +- +- /* IPIC +- * interrupts cell = +- * sense values match linux IORESOURCE_IRQ_* defines: +- * sense == 8: Level, low assertion +- * sense == 2: Edge, high-to-low change +- */ +- ipic: interrupt-controller@700 { +- compatible = "fsl,ipic"; +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x700 0x100>; +- }; +- +- pmc: power@b00 { +- compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc"; +- reg = <0xb00 0x100 0xa00 0x100>; +- interrupts = <80 0x8>; +- interrupt-parent = <&ipic>; +- }; +- }; +- +- pci0: pci@e0008500 { +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */ +- +- /* IDSEL AD14 IRQ6 inta */ +- 0x7000 0x0 0x0 0x1 &ipic 22 0x8 +- +- /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */ +- 0x7800 0x0 0x0 0x1 &ipic 21 0x8 +- 0x7800 0x0 0x0 0x2 &ipic 22 0x8 +- 0x7800 0x0 0x0 0x4 &ipic 23 0x8 +- +- /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/ +- 0xE000 0x0 0x0 0x1 &ipic 23 0x8 +- 0xE000 0x0 0x0 0x2 &ipic 21 0x8 +- 0xE000 0x0 0x0 0x3 &ipic 22 0x8>; +- interrupt-parent = <&ipic>; +- interrupts = <66 0x8>; +- bus-range = <0 0>; +- ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 +- 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; +- sleep = <&pmc 0x00010000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008500 0x100 /* internal registers */ +- 0xe0008300 0x8>; /* config space access registers */ +- compatible = "fsl,mpc8349-pci"; +- device_type = "pci"; +- }; +- +- pci1: pcie@e0009000 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie"; +- reg = <0xe0009000 0x00001000>; +- ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>; +- bus-range = <0 255>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0 0 0 1 &ipic 1 8 +- 0 0 0 2 &ipic 1 8 +- 0 0 0 3 &ipic 1 8 +- 0 0 0 4 &ipic 1 8>; +- sleep = <&pmc 0x00300000>; +- clock-frequency = <0>; +- +- pcie@0 { +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- reg = <0 0 0 0 0>; +- ranges = <0x02000000 0 0xa8000000 +- 0x02000000 0 0xa8000000 +- 0 0x10000000 +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00800000>; +- }; +- }; +- +- pci2: pcie@e000a000 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie"; +- reg = <0xe000a000 0x00001000>; +- ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>; +- bus-range = <0 255>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0 0 0 1 &ipic 2 8 +- 0 0 0 2 &ipic 2 8 +- 0 0 0 3 &ipic 2 8 +- 0 0 0 4 &ipic 2 8>; +- sleep = <&pmc 0x000c0000>; +- clock-frequency = <0>; +- +- pcie@0 { +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- reg = <0 0 0 0 0>; +- ranges = <0x02000000 0 0xc8000000 +- 0x02000000 0 0xc8000000 +- 0 0x10000000 +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00800000>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pwr { +- gpios = <&mcu_pio 0 0>; +- default-state = "on"; +- }; +- +- hdd { +- gpios = <&mcu_pio 1 0>; +- linux,default-trigger = "disk-activity"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc8377_wlan.dts b/scripts/dtc/include-prefixes/powerpc/mpc8377_wlan.dts +deleted file mode 100644 +index d8e7d40aeae4..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc8377_wlan.dts ++++ /dev/null +@@ -1,459 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8377E WLAN Device Tree Source +- * +- * Copyright 2007-2009 Freescale Semiconductor Inc. +- * Copyright 2009 MontaVista Software, Inc. +- */ +- +-/dts-v1/; +- +-/ { +- compatible = "fsl,mpc8377wlan"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8377@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; // 512MB at 0 +- }; +- +- localbus@e0005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus"; +- reg = <0xe0005000 0x1000>; +- interrupts = <77 0x8>; +- interrupt-parent = <&ipic>; +- ranges = <0x0 0x0 0xfc000000 0x04000000>; +- +- flash@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x4000000>; +- bank-width = <2>; +- device-width = <1>; +- +- partition@0 { +- reg = <0 0x80000>; +- label = "u-boot"; +- read-only; +- }; +- +- partition@a0000 { +- reg = <0xa0000 0x300000>; +- label = "kernel"; +- }; +- +- partition@3a0000 { +- reg = <0x3a0000 0x3c60000>; +- label = "rootfs"; +- }; +- }; +- }; +- +- immr@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- ranges = <0x0 0xe0000000 0x00100000>; +- reg = <0xe0000000 0x00000200>; +- bus-frequency = <0>; +- +- wdt@200 { +- device_type = "watchdog"; +- compatible = "mpc83xx_wdt"; +- reg = <0x200 0x100>; +- }; +- +- gpio1: gpio-controller@c00 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio"; +- reg = <0xc00 0x100>; +- interrupts = <74 0x8>; +- interrupt-parent = <&ipic>; +- gpio-controller; +- }; +- +- gpio2: gpio-controller@d00 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio"; +- reg = <0xd00 0x100>; +- interrupts = <75 0x8>; +- interrupt-parent = <&ipic>; +- gpio-controller; +- }; +- +- sleep-nexus { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- sleep = <&pmc 0x0c000000>; +- ranges; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- +- at24@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +- }; +- +- sdhci@2e000 { +- compatible = "fsl,mpc8377-esdhc", "fsl,esdhc"; +- reg = <0x2e000 0x1000>; +- interrupts = <42 0x8>; +- interrupt-parent = <&ipic>; +- sdhci,wp-inverted; +- clock-frequency = <133333333>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <15 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- }; +- +- spi@7000 { +- cell-index = <0>; +- compatible = "fsl,spi"; +- reg = <0x7000 0x1000>; +- interrupts = <16 0x8>; +- interrupt-parent = <&ipic>; +- mode = "cpu"; +- }; +- +- dma@82a8 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8377-dma", "fsl,elo-dma"; +- reg = <0x82a8 4>; +- ranges = <0 0x8100 0x1a8>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; +- reg = <0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x180 0x28>; +- cell-index = <3>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- }; +- +- usb@23000 { +- compatible = "fsl-usb2-dr"; +- reg = <0x23000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <38 0x8>; +- phy_type = "ulpi"; +- sleep = <&pmc 0x00c00000>; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <32 0x8 33 0x8 34 0x8>; +- phy-connection-type = "mii"; +- interrupt-parent = <&ipic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy2>; +- sleep = <&pmc 0xc0000000>; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy2: ethernet-phy@2 { +- interrupt-parent = <&ipic>; +- interrupts = <17 0x8>; +- reg = <0x2>; +- }; +- +- phy3: ethernet-phy@3 { +- interrupt-parent = <&ipic>; +- interrupts = <18 0x8>; +- reg = <0x3>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 0x8 36 0x8 37 0x8>; +- phy-connection-type = "mii"; +- interrupt-parent = <&ipic>; +- phy-handle = <&phy3>; +- tbi-handle = <&tbi1>; +- sleep = <&pmc 0x30000000>; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- interrupts = <9 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- interrupts = <10 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", +- "fsl,sec2.1", "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <11 0x8>; +- interrupt-parent = <&ipic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x9fe>; +- fsl,descriptor-types-mask = <0x3ab0ebf>; +- sleep = <&pmc 0x03000000>; +- }; +- +- sata@18000 { +- compatible = "fsl,mpc8377-sata", "fsl,pq-sata"; +- reg = <0x18000 0x1000>; +- interrupts = <44 0x8>; +- interrupt-parent = <&ipic>; +- sleep = <&pmc 0x000000c0>; +- }; +- +- sata@19000 { +- compatible = "fsl,mpc8377-sata", "fsl,pq-sata"; +- reg = <0x19000 0x1000>; +- interrupts = <45 0x8>; +- interrupt-parent = <&ipic>; +- sleep = <&pmc 0x00000030>; +- }; +- +- /* IPIC +- * interrupts cell = +- * sense values match linux IORESOURCE_IRQ_* defines: +- * sense == 8: Level, low assertion +- * sense == 2: Edge, high-to-low change +- */ +- ipic: interrupt-controller@700 { +- compatible = "fsl,ipic"; +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x700 0x100>; +- }; +- +- pmc: power@b00 { +- compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc"; +- reg = <0xb00 0x100 0xa00 0x100>; +- interrupts = <80 0x8>; +- interrupt-parent = <&ipic>; +- }; +- }; +- +- pci0: pci@e0008500 { +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */ +- +- /* IDSEL AD14 IRQ6 inta */ +- 0x7000 0x0 0x0 0x1 &ipic 22 0x8 +- +- /* IDSEL AD15 IRQ5 inta */ +- 0x7800 0x0 0x0 0x1 &ipic 21 0x8>; +- interrupt-parent = <&ipic>; +- interrupts = <66 0x8>; +- bus-range = <0 0>; +- ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 +- 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; +- sleep = <&pmc 0x00010000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008500 0x100 /* internal registers */ +- 0xe0008300 0x8>; /* config space access registers */ +- compatible = "fsl,mpc8349-pci"; +- device_type = "pci"; +- }; +- +- pci1: pcie@e0009000 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie"; +- reg = <0xe0009000 0x00001000>; +- ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>; +- bus-range = <0 255>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0 0 0 1 &ipic 1 8 +- 0 0 0 2 &ipic 1 8 +- 0 0 0 3 &ipic 1 8 +- 0 0 0 4 &ipic 1 8>; +- sleep = <&pmc 0x00300000>; +- clock-frequency = <0>; +- +- pcie@0 { +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- reg = <0 0 0 0 0>; +- ranges = <0x02000000 0 0xa8000000 +- 0x02000000 0 0xa8000000 +- 0 0x10000000 +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00800000>; +- }; +- }; +- +- pci2: pcie@e000a000 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie"; +- reg = <0xe000a000 0x00001000>; +- ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>; +- bus-range = <0 255>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0 0 0 1 &ipic 2 8 +- 0 0 0 2 &ipic 2 8 +- 0 0 0 3 &ipic 2 8 +- 0 0 0 4 &ipic 2 8>; +- sleep = <&pmc 0x000c0000>; +- clock-frequency = <0>; +- +- pcie@0 { +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- reg = <0 0 0 0 0>; +- ranges = <0x02000000 0 0xc8000000 +- 0x02000000 0 0xc8000000 +- 0 0x10000000 +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00800000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc8378_mds.dts b/scripts/dtc/include-prefixes/powerpc/mpc8378_mds.dts +deleted file mode 100644 +index e45b25554e8c..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc8378_mds.dts ++++ /dev/null +@@ -1,489 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8378E MDS Device Tree Source +- * +- * Copyright 2007 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/ { +- model = "fsl,mpc8378emds"; +- compatible = "fsl,mpc8378emds","fsl,mpc837xmds"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8378@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; // 512MB at 0 +- }; +- +- localbus@e0005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus"; +- reg = <0xe0005000 0x1000>; +- interrupts = <77 0x8>; +- interrupt-parent = <&ipic>; +- +- // booting from NOR flash +- ranges = <0 0x0 0xfe000000 0x02000000 +- 1 0x0 0xf8000000 0x00008000 +- 3 0x0 0xe0600000 0x00008000>; +- +- flash@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0 0x0 0x2000000>; +- bank-width = <2>; +- device-width = <1>; +- +- u-boot@0 { +- reg = <0x0 0x100000>; +- read-only; +- }; +- +- fs@100000 { +- reg = <0x100000 0x800000>; +- }; +- +- kernel@1d00000 { +- reg = <0x1d00000 0x200000>; +- }; +- +- dtb@1f00000 { +- reg = <0x1f00000 0x100000>; +- }; +- }; +- +- bcsr@1,0 { +- reg = <1 0x0 0x8000>; +- compatible = "fsl,mpc837xmds-bcsr"; +- }; +- +- nand@3,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8378-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <3 0x0 0x8000>; +- +- u-boot@0 { +- reg = <0x0 0x100000>; +- read-only; +- }; +- +- kernel@100000 { +- reg = <0x100000 0x300000>; +- }; +- +- fs@400000 { +- reg = <0x400000 0x1c00000>; +- }; +- }; +- }; +- +- soc@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- ranges = <0x0 0xe0000000 0x00100000>; +- reg = <0xe0000000 0x00000200>; +- bus-frequency = <0>; +- +- wdt@200 { +- compatible = "mpc83xx_wdt"; +- reg = <0x200 0x100>; +- }; +- +- sleep-nexus { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- sleep = <&pmc 0x0c000000>; +- ranges; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- +- rtc@68 { +- compatible = "dallas,ds1374"; +- reg = <0x68>; +- interrupts = <19 0x8>; +- interrupt-parent = <&ipic>; +- }; +- }; +- +- sdhci@2e000 { +- compatible = "fsl,mpc8378-esdhc", "fsl,esdhc"; +- reg = <0x2e000 0x1000>; +- interrupts = <42 0x8>; +- interrupt-parent = <&ipic>; +- sdhci,wp-inverted; +- /* Filled in by U-Boot */ +- clock-frequency = <0>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <15 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- }; +- +- spi@7000 { +- cell-index = <0>; +- compatible = "fsl,spi"; +- reg = <0x7000 0x1000>; +- interrupts = <16 0x8>; +- interrupt-parent = <&ipic>; +- mode = "cpu"; +- }; +- +- dma@82a8 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8378-dma", "fsl,elo-dma"; +- reg = <0x82a8 4>; +- ranges = <0 0x8100 0x1a8>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; +- reg = <0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x180 0x28>; +- cell-index = <3>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- }; +- +- usb@23000 { +- compatible = "fsl-usb2-dr"; +- reg = <0x23000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <38 0x8>; +- dr_mode = "host"; +- phy_type = "ulpi"; +- sleep = <&pmc 0x00c00000>; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <32 0x8 33 0x8 34 0x8>; +- phy-connection-type = "mii"; +- interrupt-parent = <&ipic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy2>; +- sleep = <&pmc 0xc0000000>; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy2: ethernet-phy@2 { +- interrupt-parent = <&ipic>; +- interrupts = <17 0x8>; +- reg = <0x2>; +- }; +- +- phy3: ethernet-phy@3 { +- interrupt-parent = <&ipic>; +- interrupts = <18 0x8>; +- reg = <0x3>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 0x8 36 0x8 37 0x8>; +- phy-connection-type = "mii"; +- interrupt-parent = <&ipic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy3>; +- sleep = <&pmc 0x30000000>; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- interrupts = <9 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- interrupts = <10 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", +- "fsl,sec2.1", "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <11 0x8>; +- interrupt-parent = <&ipic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x9fe>; +- fsl,descriptor-types-mask = <0x3ab0ebf>; +- sleep = <&pmc 0x03000000>; +- }; +- +- /* IPIC +- * interrupts cell = +- * sense values match linux IORESOURCE_IRQ_* defines: +- * sense == 8: Level, low assertion +- * sense == 2: Edge, high-to-low change +- */ +- ipic: pic@700 { +- compatible = "fsl,ipic"; +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x700 0x100>; +- }; +- +- pmc: power@b00 { +- compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc"; +- reg = <0xb00 0x100 0xa00 0x100>; +- interrupts = <80 0x8>; +- interrupt-parent = <&ipic>; +- }; +- }; +- +- pci0: pci@e0008500 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x11 */ +- 0x8800 0x0 0x0 0x1 &ipic 20 0x8 +- 0x8800 0x0 0x0 0x2 &ipic 21 0x8 +- 0x8800 0x0 0x0 0x3 &ipic 22 0x8 +- 0x8800 0x0 0x0 0x4 &ipic 23 0x8 +- +- /* IDSEL 0x12 */ +- 0x9000 0x0 0x0 0x1 &ipic 22 0x8 +- 0x9000 0x0 0x0 0x2 &ipic 23 0x8 +- 0x9000 0x0 0x0 0x3 &ipic 20 0x8 +- 0x9000 0x0 0x0 0x4 &ipic 21 0x8 +- +- /* IDSEL 0x13 */ +- 0x9800 0x0 0x0 0x1 &ipic 23 0x8 +- 0x9800 0x0 0x0 0x2 &ipic 20 0x8 +- 0x9800 0x0 0x0 0x3 &ipic 21 0x8 +- 0x9800 0x0 0x0 0x4 &ipic 22 0x8 +- +- /* IDSEL 0x15 */ +- 0xa800 0x0 0x0 0x1 &ipic 20 0x8 +- 0xa800 0x0 0x0 0x2 &ipic 21 0x8 +- 0xa800 0x0 0x0 0x3 &ipic 22 0x8 +- 0xa800 0x0 0x0 0x4 &ipic 23 0x8 +- +- /* IDSEL 0x16 */ +- 0xb000 0x0 0x0 0x1 &ipic 23 0x8 +- 0xb000 0x0 0x0 0x2 &ipic 20 0x8 +- 0xb000 0x0 0x0 0x3 &ipic 21 0x8 +- 0xb000 0x0 0x0 0x4 &ipic 22 0x8 +- +- /* IDSEL 0x17 */ +- 0xb800 0x0 0x0 0x1 &ipic 22 0x8 +- 0xb800 0x0 0x0 0x2 &ipic 23 0x8 +- 0xb800 0x0 0x0 0x3 &ipic 20 0x8 +- 0xb800 0x0 0x0 0x4 &ipic 21 0x8 +- +- /* IDSEL 0x18 */ +- 0xc000 0x0 0x0 0x1 &ipic 21 0x8 +- 0xc000 0x0 0x0 0x2 &ipic 22 0x8 +- 0xc000 0x0 0x0 0x3 &ipic 23 0x8 +- 0xc000 0x0 0x0 0x4 &ipic 20 0x8>; +- interrupt-parent = <&ipic>; +- interrupts = <66 0x8>; +- bus-range = <0x0 0x0>; +- ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 +- 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; +- clock-frequency = <0>; +- sleep = <&pmc 0x00010000>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008500 0x100 /* internal registers */ +- 0xe0008300 0x8>; /* config space access registers */ +- compatible = "fsl,mpc8349-pci"; +- device_type = "pci"; +- }; +- +- pci1: pcie@e0009000 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie"; +- reg = <0xe0009000 0x00001000>; +- ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>; +- bus-range = <0 255>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0 0 0 1 &ipic 1 8 +- 0 0 0 2 &ipic 1 8 +- 0 0 0 3 &ipic 1 8 +- 0 0 0 4 &ipic 1 8>; +- sleep = <&pmc 0x00300000>; +- clock-frequency = <0>; +- +- pcie@0 { +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- reg = <0 0 0 0 0>; +- ranges = <0x02000000 0 0xa8000000 +- 0x02000000 0 0xa8000000 +- 0 0x10000000 +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00800000>; +- }; +- }; +- +- pci2: pcie@e000a000 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie"; +- reg = <0xe000a000 0x00001000>; +- ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>; +- bus-range = <0 255>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0 0 0 1 &ipic 2 8 +- 0 0 0 2 &ipic 2 8 +- 0 0 0 3 &ipic 2 8 +- 0 0 0 4 &ipic 2 8>; +- sleep = <&pmc 0x000c0000>; +- clock-frequency = <0>; +- +- pcie@0 { +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- reg = <0 0 0 0 0>; +- ranges = <0x02000000 0 0xc8000000 +- 0x02000000 0 0xc8000000 +- 0 0x10000000 +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00800000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc8378_rdb.dts b/scripts/dtc/include-prefixes/powerpc/mpc8378_rdb.dts +deleted file mode 100644 +index bdcfe83a561e..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc8378_rdb.dts ++++ /dev/null +@@ -1,482 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8378E RDB Device Tree Source +- * +- * Copyright 2007, 2008 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/ { +- compatible = "fsl,mpc8378rdb"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8378@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; // 256MB at 0 +- }; +- +- localbus@e0005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus"; +- reg = <0xe0005000 0x1000>; +- interrupts = <77 0x8>; +- interrupt-parent = <&ipic>; +- +- // CS0 and CS1 are swapped when +- // booting from nand, but the +- // addresses are the same. +- ranges = <0x0 0x0 0xfe000000 0x00800000 +- 0x1 0x0 0xe0600000 0x00008000 +- 0x2 0x0 0xf0000000 0x00020000 +- 0x3 0x0 0xfa000000 0x00008000>; +- +- flash@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x800000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8378-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x1 0x0 0x8000>; +- +- u-boot@0 { +- reg = <0x0 0x100000>; +- read-only; +- }; +- +- kernel@100000 { +- reg = <0x100000 0x300000>; +- }; +- fs@400000 { +- reg = <0x400000 0x1c00000>; +- }; +- }; +- }; +- +- immr@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- ranges = <0x0 0xe0000000 0x00100000>; +- reg = <0xe0000000 0x00000200>; +- bus-frequency = <0>; +- +- wdt@200 { +- device_type = "watchdog"; +- compatible = "mpc83xx_wdt"; +- reg = <0x200 0x100>; +- }; +- +- gpio1: gpio-controller@c00 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio"; +- reg = <0xc00 0x100>; +- interrupts = <74 0x8>; +- interrupt-parent = <&ipic>; +- gpio-controller; +- }; +- +- gpio2: gpio-controller@d00 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio"; +- reg = <0xd00 0x100>; +- interrupts = <75 0x8>; +- interrupt-parent = <&ipic>; +- gpio-controller; +- }; +- +- sleep-nexus { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- sleep = <&pmc 0x0c000000>; +- ranges; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- +- dtt@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +- +- at24@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +- +- mcu_pio: mcu@a { +- #gpio-cells = <2>; +- compatible = "fsl,mc9s08qg8-mpc8378erdb", +- "fsl,mcu-mpc8349emitx"; +- reg = <0x0a>; +- gpio-controller; +- }; +- }; +- +- sdhci@2e000 { +- compatible = "fsl,mpc8378-esdhc", "fsl,esdhc"; +- reg = <0x2e000 0x1000>; +- interrupts = <42 0x8>; +- interrupt-parent = <&ipic>; +- sdhci,wp-inverted; +- /* Filled in by U-Boot */ +- clock-frequency = <111111111>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <15 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- }; +- +- spi@7000 { +- cell-index = <0>; +- compatible = "fsl,spi"; +- reg = <0x7000 0x1000>; +- interrupts = <16 0x8>; +- interrupt-parent = <&ipic>; +- mode = "cpu"; +- }; +- +- dma@82a8 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8378-dma", "fsl,elo-dma"; +- reg = <0x82a8 4>; +- ranges = <0 0x8100 0x1a8>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; +- reg = <0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x180 0x28>; +- cell-index = <3>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- }; +- +- usb@23000 { +- compatible = "fsl-usb2-dr"; +- reg = <0x23000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <38 0x8>; +- phy_type = "ulpi"; +- sleep = <&pmc 0x00c00000>; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <32 0x8 33 0x8 34 0x8>; +- phy-connection-type = "mii"; +- interrupt-parent = <&ipic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy2>; +- sleep = <&pmc 0xc0000000>; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy2: ethernet-phy@2 { +- interrupt-parent = <&ipic>; +- interrupts = <17 0x8>; +- reg = <0x2>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 0x8 36 0x8 37 0x8>; +- phy-connection-type = "mii"; +- interrupt-parent = <&ipic>; +- fixed-link = <1 1 1000 0 0>; +- tbi-handle = <&tbi1>; +- sleep = <&pmc 0x30000000>; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- interrupts = <9 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- interrupts = <10 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", +- "fsl,sec2.1", "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <11 0x8>; +- interrupt-parent = <&ipic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x9fe>; +- fsl,descriptor-types-mask = <0x3ab0ebf>; +- sleep = <&pmc 0x03000000>; +- }; +- +- /* IPIC +- * interrupts cell = +- * sense values match linux IORESOURCE_IRQ_* defines: +- * sense == 8: Level, low assertion +- * sense == 2: Edge, high-to-low change +- */ +- ipic: interrupt-controller@700 { +- compatible = "fsl,ipic"; +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x700 0x100>; +- }; +- +- pmc: power@b00 { +- compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc"; +- reg = <0xb00 0x100 0xa00 0x100>; +- interrupts = <80 0x8>; +- interrupt-parent = <&ipic>; +- }; +- }; +- +- pci0: pci@e0008500 { +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */ +- +- /* IDSEL AD14 IRQ6 inta */ +- 0x7000 0x0 0x0 0x1 &ipic 22 0x8 +- +- /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */ +- 0x7800 0x0 0x0 0x1 &ipic 21 0x8 +- 0x7800 0x0 0x0 0x2 &ipic 22 0x8 +- 0x7800 0x0 0x0 0x4 &ipic 23 0x8 +- +- /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/ +- 0xE000 0x0 0x0 0x1 &ipic 23 0x8 +- 0xE000 0x0 0x0 0x2 &ipic 21 0x8 +- 0xE000 0x0 0x0 0x3 &ipic 22 0x8>; +- interrupt-parent = <&ipic>; +- interrupts = <66 0x8>; +- bus-range = <0 0>; +- ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 +- 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; +- sleep = <&pmc 0x00010000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008500 0x100 /* internal registers */ +- 0xe0008300 0x8>; /* config space access registers */ +- compatible = "fsl,mpc8349-pci"; +- device_type = "pci"; +- }; +- +- pci1: pcie@e0009000 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie"; +- reg = <0xe0009000 0x00001000>; +- ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>; +- bus-range = <0 255>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0 0 0 1 &ipic 1 8 +- 0 0 0 2 &ipic 1 8 +- 0 0 0 3 &ipic 1 8 +- 0 0 0 4 &ipic 1 8>; +- sleep = <&pmc 0x00300000>; +- clock-frequency = <0>; +- +- pcie@0 { +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- reg = <0 0 0 0 0>; +- ranges = <0x02000000 0 0xa8000000 +- 0x02000000 0 0xa8000000 +- 0 0x10000000 +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00800000>; +- }; +- }; +- +- pci2: pcie@e000a000 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie"; +- reg = <0xe000a000 0x00001000>; +- ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>; +- bus-range = <0 255>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0 0 0 1 &ipic 2 8 +- 0 0 0 2 &ipic 2 8 +- 0 0 0 3 &ipic 2 8 +- 0 0 0 4 &ipic 2 8>; +- sleep = <&pmc 0x000c0000>; +- clock-frequency = <0>; +- +- pcie@0 { +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- reg = <0 0 0 0 0>; +- ranges = <0x02000000 0 0xc8000000 +- 0x02000000 0 0xc8000000 +- 0 0x10000000 +- 0x01000000 0 0x00000000 +- 0x01000000 0 0x00000000 +- 0 0x00800000>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pwr { +- gpios = <&mcu_pio 0 0>; +- default-state = "on"; +- }; +- +- hdd { +- gpios = <&mcu_pio 1 0>; +- linux,default-trigger = "disk-activity"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc8379_mds.dts b/scripts/dtc/include-prefixes/powerpc/mpc8379_mds.dts +deleted file mode 100644 +index f7379a1cbb6c..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc8379_mds.dts ++++ /dev/null +@@ -1,455 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8379E MDS Device Tree Source +- * +- * Copyright 2007 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/ { +- model = "fsl,mpc8379emds"; +- compatible = "fsl,mpc8379emds","fsl,mpc837xmds"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8379@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; // 512MB at 0 +- }; +- +- localbus@e0005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus"; +- reg = <0xe0005000 0x1000>; +- interrupts = <77 0x8>; +- interrupt-parent = <&ipic>; +- +- // booting from NOR flash +- ranges = <0 0x0 0xfe000000 0x02000000 +- 1 0x0 0xf8000000 0x00008000 +- 3 0x0 0xe0600000 0x00008000>; +- +- flash@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0 0x0 0x2000000>; +- bank-width = <2>; +- device-width = <1>; +- +- u-boot@0 { +- reg = <0x0 0x100000>; +- read-only; +- }; +- +- fs@100000 { +- reg = <0x100000 0x800000>; +- }; +- +- kernel@1d00000 { +- reg = <0x1d00000 0x200000>; +- }; +- +- dtb@1f00000 { +- reg = <0x1f00000 0x100000>; +- }; +- }; +- +- bcsr@1,0 { +- reg = <1 0x0 0x8000>; +- compatible = "fsl,mpc837xmds-bcsr"; +- }; +- +- nand@3,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8379-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <3 0x0 0x8000>; +- +- u-boot@0 { +- reg = <0x0 0x100000>; +- read-only; +- }; +- +- kernel@100000 { +- reg = <0x100000 0x300000>; +- }; +- +- fs@400000 { +- reg = <0x400000 0x1c00000>; +- }; +- }; +- }; +- +- soc@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- ranges = <0x0 0xe0000000 0x00100000>; +- reg = <0xe0000000 0x00000200>; +- bus-frequency = <0>; +- +- wdt@200 { +- compatible = "mpc83xx_wdt"; +- reg = <0x200 0x100>; +- }; +- +- sleep-nexus { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- sleep = <&pmc 0x0c000000>; +- ranges; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- +- rtc@68 { +- compatible = "dallas,ds1374"; +- reg = <0x68>; +- interrupts = <19 0x8>; +- interrupt-parent = <&ipic>; +- }; +- }; +- +- sdhci@2e000 { +- compatible = "fsl,mpc8379-esdhc", "fsl,esdhc"; +- reg = <0x2e000 0x1000>; +- interrupts = <42 0x8>; +- interrupt-parent = <&ipic>; +- sdhci,wp-inverted; +- /* Filled in by U-Boot */ +- clock-frequency = <0>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <15 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- }; +- +- spi@7000 { +- cell-index = <0>; +- compatible = "fsl,spi"; +- reg = <0x7000 0x1000>; +- interrupts = <16 0x8>; +- interrupt-parent = <&ipic>; +- mode = "cpu"; +- }; +- +- dma@82a8 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8379-dma", "fsl,elo-dma"; +- reg = <0x82a8 4>; +- ranges = <0 0x8100 0x1a8>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; +- reg = <0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x180 0x28>; +- cell-index = <3>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- }; +- +- usb@23000 { +- compatible = "fsl-usb2-dr"; +- reg = <0x23000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <38 0x8>; +- dr_mode = "host"; +- phy_type = "ulpi"; +- sleep = <&pmc 0x00c00000>; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <32 0x8 33 0x8 34 0x8>; +- phy-connection-type = "mii"; +- interrupt-parent = <&ipic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy2>; +- sleep = <&pmc 0xc0000000>; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy2: ethernet-phy@2 { +- interrupt-parent = <&ipic>; +- interrupts = <17 0x8>; +- reg = <0x2>; +- }; +- +- phy3: ethernet-phy@3 { +- interrupt-parent = <&ipic>; +- interrupts = <18 0x8>; +- reg = <0x3>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 0x8 36 0x8 37 0x8>; +- phy-connection-type = "mii"; +- interrupt-parent = <&ipic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy3>; +- sleep = <&pmc 0x30000000>; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- interrupts = <9 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- interrupts = <10 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", +- "fsl,sec2.1", "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <11 0x8>; +- interrupt-parent = <&ipic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x9fe>; +- fsl,descriptor-types-mask = <0x3ab0ebf>; +- sleep = <&pmc 0x03000000>; +- }; +- +- sata@18000 { +- compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; +- reg = <0x18000 0x1000>; +- interrupts = <44 0x8>; +- interrupt-parent = <&ipic>; +- sleep = <&pmc 0x000000c0>; +- }; +- +- sata@19000 { +- compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; +- reg = <0x19000 0x1000>; +- interrupts = <45 0x8>; +- interrupt-parent = <&ipic>; +- sleep = <&pmc 0x00000030>; +- }; +- +- sata@1a000 { +- compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; +- reg = <0x1a000 0x1000>; +- interrupts = <46 0x8>; +- interrupt-parent = <&ipic>; +- sleep = <&pmc 0x0000000c>; +- }; +- +- sata@1b000 { +- compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; +- reg = <0x1b000 0x1000>; +- interrupts = <47 0x8>; +- interrupt-parent = <&ipic>; +- sleep = <&pmc 0x00000003>; +- }; +- +- /* IPIC +- * interrupts cell = +- * sense values match linux IORESOURCE_IRQ_* defines: +- * sense == 8: Level, low assertion +- * sense == 2: Edge, high-to-low change +- */ +- ipic: pic@700 { +- compatible = "fsl,ipic"; +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x700 0x100>; +- }; +- +- pmc: power@b00 { +- compatible = "fsl,mpc8379-pmc", "fsl,mpc8349-pmc"; +- reg = <0xb00 0x100 0xa00 0x100>; +- interrupts = <80 0x8>; +- interrupt-parent = <&ipic>; +- }; +- }; +- +- pci0: pci@e0008500 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x11 */ +- 0x8800 0x0 0x0 0x1 &ipic 20 0x8 +- 0x8800 0x0 0x0 0x2 &ipic 21 0x8 +- 0x8800 0x0 0x0 0x3 &ipic 22 0x8 +- 0x8800 0x0 0x0 0x4 &ipic 23 0x8 +- +- /* IDSEL 0x12 */ +- 0x9000 0x0 0x0 0x1 &ipic 22 0x8 +- 0x9000 0x0 0x0 0x2 &ipic 23 0x8 +- 0x9000 0x0 0x0 0x3 &ipic 20 0x8 +- 0x9000 0x0 0x0 0x4 &ipic 21 0x8 +- +- /* IDSEL 0x13 */ +- 0x9800 0x0 0x0 0x1 &ipic 23 0x8 +- 0x9800 0x0 0x0 0x2 &ipic 20 0x8 +- 0x9800 0x0 0x0 0x3 &ipic 21 0x8 +- 0x9800 0x0 0x0 0x4 &ipic 22 0x8 +- +- /* IDSEL 0x15 */ +- 0xa800 0x0 0x0 0x1 &ipic 20 0x8 +- 0xa800 0x0 0x0 0x2 &ipic 21 0x8 +- 0xa800 0x0 0x0 0x3 &ipic 22 0x8 +- 0xa800 0x0 0x0 0x4 &ipic 23 0x8 +- +- /* IDSEL 0x16 */ +- 0xb000 0x0 0x0 0x1 &ipic 23 0x8 +- 0xb000 0x0 0x0 0x2 &ipic 20 0x8 +- 0xb000 0x0 0x0 0x3 &ipic 21 0x8 +- 0xb000 0x0 0x0 0x4 &ipic 22 0x8 +- +- /* IDSEL 0x17 */ +- 0xb800 0x0 0x0 0x1 &ipic 22 0x8 +- 0xb800 0x0 0x0 0x2 &ipic 23 0x8 +- 0xb800 0x0 0x0 0x3 &ipic 20 0x8 +- 0xb800 0x0 0x0 0x4 &ipic 21 0x8 +- +- /* IDSEL 0x18 */ +- 0xc000 0x0 0x0 0x1 &ipic 21 0x8 +- 0xc000 0x0 0x0 0x2 &ipic 22 0x8 +- 0xc000 0x0 0x0 0x3 &ipic 23 0x8 +- 0xc000 0x0 0x0 0x4 &ipic 20 0x8>; +- interrupt-parent = <&ipic>; +- interrupts = <66 0x8>; +- bus-range = <0x0 0x0>; +- ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 +- 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; +- sleep = <&pmc 0x00010000>; +- clock-frequency = <0>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008500 0x100 /* internal registers */ +- 0xe0008300 0x8>; /* config space access registers */ +- compatible = "fsl,mpc8349-pci"; +- device_type = "pci"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc8379_rdb.dts b/scripts/dtc/include-prefixes/powerpc/mpc8379_rdb.dts +deleted file mode 100644 +index a5f702304a35..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc8379_rdb.dts ++++ /dev/null +@@ -1,448 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8379E RDB Device Tree Source +- * +- * Copyright 2007, 2008 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/ { +- compatible = "fsl,mpc8379rdb"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8379@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; // 256MB at 0 +- }; +- +- localbus@e0005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus"; +- reg = <0xe0005000 0x1000>; +- interrupts = <77 0x8>; +- interrupt-parent = <&ipic>; +- +- // CS0 and CS1 are swapped when +- // booting from nand, but the +- // addresses are the same. +- ranges = <0x0 0x0 0xfe000000 0x00800000 +- 0x1 0x0 0xe0600000 0x00008000 +- 0x2 0x0 0xf0000000 0x00020000 +- 0x3 0x0 0xfa000000 0x00008000>; +- +- flash@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x800000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- nand@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8379-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <0x1 0x0 0x8000>; +- +- u-boot@0 { +- reg = <0x0 0x100000>; +- read-only; +- }; +- +- kernel@100000 { +- reg = <0x100000 0x300000>; +- }; +- fs@400000 { +- reg = <0x400000 0x1c00000>; +- }; +- }; +- }; +- +- immr@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- ranges = <0x0 0xe0000000 0x00100000>; +- reg = <0xe0000000 0x00000200>; +- bus-frequency = <0>; +- +- wdt@200 { +- device_type = "watchdog"; +- compatible = "mpc83xx_wdt"; +- reg = <0x200 0x100>; +- }; +- +- gpio1: gpio-controller@c00 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio"; +- reg = <0xc00 0x100>; +- interrupts = <74 0x8>; +- interrupt-parent = <&ipic>; +- gpio-controller; +- }; +- +- gpio2: gpio-controller@d00 { +- #gpio-cells = <2>; +- compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio"; +- reg = <0xd00 0x100>; +- interrupts = <75 0x8>; +- interrupt-parent = <&ipic>; +- gpio-controller; +- }; +- +- sleep-nexus { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- sleep = <&pmc 0x0c000000>; +- ranges; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <14 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- +- dtt@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +- +- at24@50 { +- compatible = "atmel,24c256"; +- reg = <0x50>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1339"; +- reg = <0x68>; +- }; +- +- mcu_pio: mcu@a { +- #gpio-cells = <2>; +- compatible = "fsl,mc9s08qg8-mpc8379erdb", +- "fsl,mcu-mpc8349emitx"; +- reg = <0x0a>; +- gpio-controller; +- }; +- }; +- +- sdhci@2e000 { +- compatible = "fsl,mpc8379-esdhc", "fsl,esdhc"; +- reg = <0x2e000 0x1000>; +- interrupts = <42 0x8>; +- interrupt-parent = <&ipic>; +- sdhci,wp-inverted; +- /* Filled in by U-Boot */ +- clock-frequency = <111111111>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <15 0x8>; +- interrupt-parent = <&ipic>; +- dfsrr; +- }; +- +- spi@7000 { +- cell-index = <0>; +- compatible = "fsl,spi"; +- reg = <0x7000 0x1000>; +- interrupts = <16 0x8>; +- interrupt-parent = <&ipic>; +- mode = "cpu"; +- }; +- +- dma@82a8 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8379-dma", "fsl,elo-dma"; +- reg = <0x82a8 4>; +- ranges = <0 0x8100 0x1a8>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; +- reg = <0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; +- reg = <0x180 0x28>; +- cell-index = <3>; +- interrupt-parent = <&ipic>; +- interrupts = <71 8>; +- }; +- }; +- +- usb@23000 { +- compatible = "fsl-usb2-dr"; +- reg = <0x23000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupt-parent = <&ipic>; +- interrupts = <38 0x8>; +- phy_type = "ulpi"; +- sleep = <&pmc 0x00c00000>; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <32 0x8 33 0x8 34 0x8>; +- phy-connection-type = "mii"; +- interrupt-parent = <&ipic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy2>; +- sleep = <&pmc 0xc0000000>; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy2: ethernet-phy@2 { +- interrupt-parent = <&ipic>; +- interrupts = <17 0x8>; +- reg = <0x2>; +- }; +- +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 0x8 36 0x8 37 0x8>; +- phy-connection-type = "mii"; +- interrupt-parent = <&ipic>; +- fixed-link = <1 1 1000 0 0>; +- tbi-handle = <&tbi1>; +- sleep = <&pmc 0x30000000>; +- fsl,magic-packet; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- interrupts = <9 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- interrupts = <10 0x8>; +- interrupt-parent = <&ipic>; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", +- "fsl,sec2.1", "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <11 0x8>; +- interrupt-parent = <&ipic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x9fe>; +- fsl,descriptor-types-mask = <0x3ab0ebf>; +- sleep = <&pmc 0x03000000>; +- }; +- +- sata@18000 { +- compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; +- reg = <0x18000 0x1000>; +- interrupts = <44 0x8>; +- interrupt-parent = <&ipic>; +- sleep = <&pmc 0x000000c0>; +- }; +- +- sata@19000 { +- compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; +- reg = <0x19000 0x1000>; +- interrupts = <45 0x8>; +- interrupt-parent = <&ipic>; +- sleep = <&pmc 0x00000030>; +- }; +- +- sata@1a000 { +- compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; +- reg = <0x1a000 0x1000>; +- interrupts = <46 0x8>; +- interrupt-parent = <&ipic>; +- sleep = <&pmc 0x0000000c>; +- }; +- +- sata@1b000 { +- compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; +- reg = <0x1b000 0x1000>; +- interrupts = <47 0x8>; +- interrupt-parent = <&ipic>; +- sleep = <&pmc 0x00000003>; +- }; +- +- /* IPIC +- * interrupts cell = +- * sense values match linux IORESOURCE_IRQ_* defines: +- * sense == 8: Level, low assertion +- * sense == 2: Edge, high-to-low change +- */ +- ipic: interrupt-controller@700 { +- compatible = "fsl,ipic"; +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x700 0x100>; +- }; +- +- pmc: power@b00 { +- compatible = "fsl,mpc8379-pmc", "fsl,mpc8349-pmc"; +- reg = <0xb00 0x100 0xa00 0x100>; +- interrupts = <80 0x8>; +- interrupt-parent = <&ipic>; +- }; +- }; +- +- pci0: pci@e0008500 { +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */ +- +- /* IDSEL AD14 IRQ6 inta */ +- 0x7000 0x0 0x0 0x1 &ipic 22 0x8 +- +- /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */ +- 0x7800 0x0 0x0 0x1 &ipic 21 0x8 +- 0x7800 0x0 0x0 0x2 &ipic 22 0x8 +- 0x7800 0x0 0x0 0x4 &ipic 23 0x8 +- +- /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/ +- 0xE000 0x0 0x0 0x1 &ipic 23 0x8 +- 0xE000 0x0 0x0 0x2 &ipic 21 0x8 +- 0xE000 0x0 0x0 0x3 &ipic 22 0x8>; +- interrupt-parent = <&ipic>; +- interrupts = <66 0x8>; +- bus-range = <0x0 0x0>; +- ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 +- 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; +- sleep = <&pmc 0x00010000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008500 0x100 /* internal registers */ +- 0xe0008300 0x8>; /* config space access registers */ +- compatible = "fsl,mpc8349-pci"; +- device_type = "pci"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pwr { +- gpios = <&mcu_pio 0 0>; +- default-state = "on"; +- }; +- +- hdd { +- gpios = <&mcu_pio 1 0>; +- linux,default-trigger = "disk-activity"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc8610_hpcd.dts b/scripts/dtc/include-prefixes/powerpc/mpc8610_hpcd.dts +deleted file mode 100644 +index 33bbe58c1ad0..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc8610_hpcd.dts ++++ /dev/null +@@ -1,503 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * MPC8610 HPCD Device Tree Source +- * +- * Copyright 2007-2008 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/ { +- model = "MPC8610HPCD"; +- compatible = "fsl,MPC8610HPCD"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8610@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; // L1 +- i-cache-size = <32768>; // L1 +- sleep = <&pmc 0x00008000 0 // core +- &pmc 0x00004000 0>; // timebase +- timebase-frequency = <0>; // From uboot +- bus-frequency = <0>; // From uboot +- clock-frequency = <0>; // From uboot +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; // 512M at 0x0 +- }; +- +- localbus@e0005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus"; +- reg = <0xe0005000 0x1000>; +- interrupts = <19 2>; +- interrupt-parent = <&mpic>; +- ranges = <0 0 0xf8000000 0x08000000 +- 1 0 0xf0000000 0x08000000 +- 2 0 0xe8400000 0x00008000 +- 4 0 0xe8440000 0x00008000 +- 5 0 0xe8480000 0x00008000 +- 6 0 0xe84c0000 0x00008000 +- 3 0 0xe8000000 0x00000020>; +- sleep = <&pmc 0x08000000 0>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x8000000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- flash@1,0 { +- compatible = "cfi-flash"; +- reg = <1 0 0x8000000>; +- bank-width = <2>; +- device-width = <1>; +- }; +- +- flash@2,0 { +- compatible = "fsl,mpc8610-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <2 0 0x8000>; +- }; +- +- flash@4,0 { +- compatible = "fsl,mpc8610-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <4 0 0x8000>; +- }; +- +- flash@5,0 { +- compatible = "fsl,mpc8610-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <5 0 0x8000>; +- }; +- +- flash@6,0 { +- compatible = "fsl,mpc8610-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <6 0 0x8000>; +- }; +- +- board-control@3,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,fpga-pixis"; +- reg = <3 0 0x20>; +- ranges = <0 3 0 0x20>; +- interrupt-parent = <&mpic>; +- interrupts = <8 8>; +- +- sdcsr_pio: gpio-controller@a { +- #gpio-cells = <2>; +- compatible = "fsl,fpga-pixis-gpio-bank"; +- reg = <0xa 1>; +- gpio-controller; +- }; +- }; +- }; +- +- soc@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- #interrupt-cells = <2>; +- device_type = "soc"; +- compatible = "fsl,mpc8610-immr", "simple-bus"; +- ranges = <0x0 0xe0000000 0x00100000>; +- bus-frequency = <0>; +- +- mcm-law@0 { +- compatible = "fsl,mcm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <10>; +- }; +- +- mcm@1000 { +- compatible = "fsl,mpc8610-mcm", "fsl,mcm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- +- cs4270:codec@4f { +- compatible = "cirrus,cs4270"; +- reg = <0x4f>; +- /* MCLK source is a stand-alone oscillator */ +- clock-frequency = <12288000>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- sleep = <&pmc 0x00000004 0>; +- dfsrr; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- sleep = <&pmc 0x00000002 0>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- sleep = <&pmc 0x00000008 0>; +- }; +- +- spi@7000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc8610-spi", "fsl,spi"; +- reg = <0x7000 0x40>; +- cell-index = <0>; +- interrupts = <59 2>; +- interrupt-parent = <&mpic>; +- mode = "cpu"; +- cs-gpios = <&sdcsr_pio 7 0>; +- sleep = <&pmc 0x00000800 0>; +- +- mmc-slot@0 { +- compatible = "fsl,mpc8610hpcd-mmc-slot", +- "mmc-spi-slot"; +- reg = <0>; +- gpios = <&sdcsr_pio 0 1 /* nCD */ +- &sdcsr_pio 1 0>; /* WP */ +- voltage-ranges = <3300 3300>; +- spi-max-frequency = <50000000>; +- }; +- }; +- +- display@2c000 { +- compatible = "fsl,diu"; +- reg = <0x2c000 100>; +- interrupts = <72 2>; +- interrupt-parent = <&mpic>; +- sleep = <&pmc 0x04000000 0>; +- }; +- +- mpic: interrupt-controller@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- compatible = "chrp,open-pic"; +- device_type = "open-pic"; +- }; +- +- msi@41600 { +- compatible = "fsl,mpc8610-msi", "fsl,mpic-msi"; +- reg = <0x41600 0x80>; +- msi-available-ranges = <0 0x100>; +- interrupts = < +- 0xe0 0 +- 0xe1 0 +- 0xe2 0 +- 0xe3 0 +- 0xe4 0 +- 0xe5 0 +- 0xe6 0 +- 0xe7 0>; +- interrupt-parent = <&mpic>; +- }; +- +- global-utilities@e0000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8610-guts"; +- reg = <0xe0000 0x1000>; +- ranges = <0 0xe0000 0x1000>; +- fsl,has-rstcr; +- +- pmc: power@70 { +- compatible = "fsl,mpc8610-pmc", +- "fsl,mpc8641d-pmc"; +- reg = <0x70 0x20>; +- }; +- }; +- +- wdt@e4000 { +- compatible = "fsl,mpc8610-wdt"; +- reg = <0xe4000 0x100>; +- }; +- +- ssi@16000 { +- compatible = "fsl,mpc8610-ssi"; +- cell-index = <0>; +- reg = <0x16000 0x100>; +- interrupt-parent = <&mpic>; +- interrupts = <62 2>; +- fsl,mode = "i2s-slave"; +- codec-handle = <&cs4270>; +- fsl,playback-dma = <&dma00>; +- fsl,capture-dma = <&dma01>; +- fsl,fifo-depth = <8>; +- sleep = <&pmc 0 0x08000000>; +- }; +- +- ssi@16100 { +- compatible = "fsl,mpc8610-ssi"; +- status = "disabled"; +- cell-index = <1>; +- reg = <0x16100 0x100>; +- interrupt-parent = <&mpic>; +- interrupts = <63 2>; +- fsl,fifo-depth = <8>; +- sleep = <&pmc 0 0x04000000>; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma"; +- cell-index = <0>; +- reg = <0x21300 0x4>; /* DMA general status register */ +- ranges = <0x0 0x21100 0x200>; +- sleep = <&pmc 0x00000400 0>; +- +- dma00: dma-channel@0 { +- compatible = "fsl,mpc8610-dma-channel", +- "fsl,ssi-dma-channel"; +- cell-index = <0>; +- reg = <0x0 0x80>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma01: dma-channel@1 { +- compatible = "fsl,mpc8610-dma-channel", +- "fsl,ssi-dma-channel"; +- cell-index = <1>; +- reg = <0x80 0x80>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@2 { +- compatible = "fsl,mpc8610-dma-channel", +- "fsl,eloplus-dma-channel"; +- cell-index = <2>; +- reg = <0x100 0x80>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@3 { +- compatible = "fsl,mpc8610-dma-channel", +- "fsl,eloplus-dma-channel"; +- cell-index = <3>; +- reg = <0x180 0x80>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- dma@c300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma"; +- cell-index = <1>; +- reg = <0xc300 0x4>; /* DMA general status register */ +- ranges = <0x0 0xc100 0x200>; +- sleep = <&pmc 0x00000200 0>; +- +- dma-channel@0 { +- compatible = "fsl,mpc8610-dma-channel", +- "fsl,eloplus-dma-channel"; +- cell-index = <0>; +- reg = <0x0 0x80>; +- interrupt-parent = <&mpic>; +- interrupts = <76 2>; +- }; +- dma-channel@1 { +- compatible = "fsl,mpc8610-dma-channel", +- "fsl,eloplus-dma-channel"; +- cell-index = <1>; +- reg = <0x80 0x80>; +- interrupt-parent = <&mpic>; +- interrupts = <77 2>; +- }; +- dma-channel@2 { +- compatible = "fsl,mpc8610-dma-channel", +- "fsl,eloplus-dma-channel"; +- cell-index = <2>; +- reg = <0x100 0x80>; +- interrupt-parent = <&mpic>; +- interrupts = <78 2>; +- }; +- dma-channel@3 { +- compatible = "fsl,mpc8610-dma-channel", +- "fsl,eloplus-dma-channel"; +- cell-index = <3>; +- reg = <0x180 0x80>; +- interrupt-parent = <&mpic>; +- interrupts = <79 2>; +- }; +- }; +- +- }; +- +- pci0: pci@e0008000 { +- compatible = "fsl,mpc8610-pci"; +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008000 0x1000>; +- bus-range = <0 0>; +- ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>; +- sleep = <&pmc 0x80000000 0>; +- clock-frequency = <33333333>; +- interrupt-parent = <&mpic>; +- interrupts = <24 2>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x11 */ +- 0x8800 0 0 1 &mpic 4 1 +- 0x8800 0 0 2 &mpic 5 1 +- 0x8800 0 0 3 &mpic 6 1 +- 0x8800 0 0 4 &mpic 7 1 +- +- /* IDSEL 0x12 */ +- 0x9000 0 0 1 &mpic 5 1 +- 0x9000 0 0 2 &mpic 6 1 +- 0x9000 0 0 3 &mpic 7 1 +- 0x9000 0 0 4 &mpic 4 1 +- >; +- }; +- +- pci1: pcie@e000a000 { +- compatible = "fsl,mpc8641-pcie"; +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe000a000 0x1000>; +- bus-range = <1 3>; +- ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>; +- sleep = <&pmc 0x40000000 0>; +- clock-frequency = <33333333>; +- interrupt-parent = <&mpic>; +- interrupts = <26 2>; +- interrupt-map-mask = <0xf800 0 0 7>; +- +- interrupt-map = < +- /* IDSEL 0x1b */ +- 0xd800 0 0 1 &mpic 2 1 +- +- /* IDSEL 0x1c*/ +- 0xe000 0 0 1 &mpic 1 1 +- 0xe000 0 0 2 &mpic 1 1 +- 0xe000 0 0 3 &mpic 1 1 +- 0xe000 0 0 4 &mpic 1 1 +- +- /* IDSEL 0x1f */ +- 0xf800 0 0 1 &mpic 3 2 +- 0xf800 0 0 2 &mpic 0 1 +- >; +- +- pcie@0 { +- reg = <0 0 0 0 0>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- ranges = <0x02000000 0x0 0xa0000000 +- 0x02000000 0x0 0xa0000000 +- 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 +- 0x01000000 0x0 0x00000000 +- 0x0 0x00100000>; +- uli1575@0 { +- reg = <0 0 0 0 0>; +- #size-cells = <2>; +- #address-cells = <3>; +- ranges = <0x02000000 0x0 0xa0000000 +- 0x02000000 0x0 0xa0000000 +- 0x0 0x10000000 +- 0x01000000 0x0 0x00000000 +- 0x01000000 0x0 0x00000000 +- 0x0 0x00100000>; +- +- isa@1e { +- device_type = "isa"; +- #size-cells = <1>; +- #address-cells = <2>; +- reg = <0xf000 0 0 0 0>; +- ranges = <1 0 0x01000000 0 0 +- 0x00001000>; +- +- rtc@70 { +- compatible = "pnpPNP,b00"; +- reg = <1 0x70 2>; +- }; +- }; +- }; +- }; +- }; +- +- pci2: pcie@e0009000 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "fsl,mpc8641-pcie"; +- reg = <0xe0009000 0x00001000>; +- ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>; +- bus-range = <0 255>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0x0000 0 0 1 &mpic 4 1 +- 0x0000 0 0 2 &mpic 5 1 +- 0x0000 0 0 3 &mpic 6 1 +- 0x0000 0 0 4 &mpic 7 1>; +- interrupt-parent = <&mpic>; +- interrupts = <25 2>; +- sleep = <&pmc 0x20000000 0>; +- clock-frequency = <33333333>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc866ads.dts b/scripts/dtc/include-prefixes/powerpc/mpc866ads.dts +deleted file mode 100644 +index ff60d678c6a2..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc866ads.dts ++++ /dev/null +@@ -1,186 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC866 ADS Device Tree Source +- * +- * Copyright 2006 MontaVista Software, Inc. +- * Copyright 2008 Freescale Semiconductor, Inc. +- */ +- +-/dts-v1/; +- +-/ { +- model = "MPC866ADS"; +- compatible = "fsl,mpc866ads"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,866@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <16>; // 16 bytes +- i-cache-line-size = <16>; // 16 bytes +- d-cache-size = <0x2000>; // L1, 8K +- i-cache-size = <0x4000>; // L1, 16K +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- interrupts = <15 2>; // decrementer interrupt +- interrupt-parent = <&PIC>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x800000>; +- }; +- +- localbus@ff000100 { +- compatible = "fsl,mpc866-localbus", "fsl,pq1-localbus"; +- #address-cells = <2>; +- #size-cells = <1>; +- reg = <0xff000100 0x40>; +- +- ranges = < +- 0x1 0x0 0xff080000 0x8000 +- 0x5 0x0 0xff0a0000 0x8000 +- >; +- +- board-control@1,0 { +- reg = <0x1 0x0 0x20 0x5 0x300 0x4>; +- compatible = "fsl,mpc866ads-bcsr"; +- }; +- }; +- +- soc@ff000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- ranges = <0x0 0xff000000 0x100000>; +- reg = <0xff000000 0x200>; +- bus-frequency = <0>; +- +- mdio@e00 { +- compatible = "fsl,mpc866-fec-mdio", "fsl,pq1-fec-mdio"; +- reg = <0xe00 0x188>; +- #address-cells = <1>; +- #size-cells = <0>; +- PHY: ethernet-phy@f { +- reg = <0xf>; +- }; +- }; +- +- ethernet@e00 { +- device_type = "network"; +- compatible = "fsl,mpc866-fec-enet", +- "fsl,pq1-fec-enet"; +- reg = <0xe00 0x188>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <3 1>; +- interrupt-parent = <&PIC>; +- phy-handle = <&PHY>; +- linux,network-index = <0>; +- }; +- +- PIC: pic@0 { +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x0 0x24>; +- compatible = "fsl,mpc866-pic", "fsl,pq1-pic"; +- }; +- +- cpm@9c0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc866-cpm", "fsl,cpm1"; +- ranges; +- reg = <0x9c0 0x40>; +- brg-frequency = <0>; +- interrupts = <0 2>; // cpm error interrupt +- interrupt-parent = <&CPM_PIC>; +- +- muram@2000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2000 0x2000>; +- +- data@0 { +- compatible = "fsl,cpm-muram-data"; +- reg = <0x0 0x1c00>; +- }; +- }; +- +- brg@9f0 { +- compatible = "fsl,mpc866-brg", +- "fsl,cpm1-brg", +- "fsl,cpm-brg"; +- reg = <0x9f0 0x10>; +- clock-frequency = <0>; +- }; +- +- CPM_PIC: pic@930 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupts = <5 2 0 2>; +- interrupt-parent = <&PIC>; +- reg = <0x930 0x20>; +- compatible = "fsl,mpc866-cpm-pic", +- "fsl,cpm1-pic"; +- }; +- +- +- serial@a80 { +- device_type = "serial"; +- compatible = "fsl,mpc866-smc-uart", +- "fsl,cpm1-smc-uart"; +- reg = <0xa80 0x10 0x3e80 0x40>; +- interrupts = <4>; +- interrupt-parent = <&CPM_PIC>; +- fsl,cpm-brg = <1>; +- fsl,cpm-command = <0x90>; +- }; +- +- serial@a90 { +- device_type = "serial"; +- compatible = "fsl,mpc866-smc-uart", +- "fsl,cpm1-smc-uart"; +- reg = <0xa90 0x10 0x3f80 0x40>; +- interrupts = <3>; +- interrupt-parent = <&CPM_PIC>; +- fsl,cpm-brg = <2>; +- fsl,cpm-command = <0xd0>; +- }; +- +- ethernet@a00 { +- device_type = "network"; +- compatible = "fsl,mpc866-scc-enet", +- "fsl,cpm1-scc-enet"; +- reg = <0xa00 0x18 0x3c00 0x100>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <30>; +- interrupt-parent = <&CPM_PIC>; +- fsl,cpm-command = <0000>; +- linux,network-index = <1>; +- }; +- +- i2c@860 { +- compatible = "fsl,mpc866-i2c", +- "fsl,cpm1-i2c"; +- reg = <0x860 0x20 0x3c80 0x30>; +- interrupts = <16>; +- interrupt-parent = <&CPM_PIC>; +- fsl,cpm-command = <0x10>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- }; +- +- chosen { +- stdout-path = "/soc/cpm/serial@a80"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mpc885ads.dts b/scripts/dtc/include-prefixes/powerpc/mpc885ads.dts +deleted file mode 100644 +index be58e7f29c9b..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mpc885ads.dts ++++ /dev/null +@@ -1,239 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC885 ADS Device Tree Source +- * +- * Copyright 2006 MontaVista Software, Inc. +- * Copyright 2007,2008 Freescale Semiconductor, Inc. +- */ +- +-/dts-v1/; +- +-/ { +- model = "MPC885ADS"; +- compatible = "fsl,mpc885ads"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,885@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <16>; +- i-cache-line-size = <16>; +- d-cache-size = <8192>; +- i-cache-size = <8192>; +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- interrupts = <15 2>; // decrementer interrupt +- interrupt-parent = <&PIC>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; +- }; +- +- localbus@ff000100 { +- compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus"; +- #address-cells = <2>; +- #size-cells = <1>; +- reg = <0xff000100 0x40>; +- +- ranges = < +- 0x0 0x0 0xfe000000 0x800000 +- 0x1 0x0 0xff080000 0x8000 +- 0x5 0x0 0xff0a0000 0x8000 +- >; +- +- flash@0,0 { +- compatible = "jedec-flash"; +- reg = <0x0 0x0 0x800000>; +- bank-width = <4>; +- device-width = <1>; +- }; +- +- board-control@1,0 { +- reg = <0x1 0x0 0x20 0x5 0x300 0x4>; +- compatible = "fsl,mpc885ads-bcsr"; +- }; +- }; +- +- soc@ff000000 { +- compatible = "fsl,mpc885", "fsl,pq1-soc"; +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- ranges = <0x0 0xff000000 0x28000>; +- bus-frequency = <0>; +- +- // Temporary -- will go away once kernel uses ranges for get_immrbase(). +- reg = <0xff000000 0x4000>; +- +- mdio@e00 { +- compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio"; +- reg = <0xe00 0x188>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- PHY0: ethernet-phy@0 { +- reg = <0x0>; +- }; +- +- PHY1: ethernet-phy@1 { +- reg = <0x1>; +- }; +- +- PHY2: ethernet-phy@2 { +- reg = <0x2>; +- }; +- }; +- +- ethernet@e00 { +- device_type = "network"; +- compatible = "fsl,mpc885-fec-enet", +- "fsl,pq1-fec-enet"; +- reg = <0xe00 0x188>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <3 1>; +- interrupt-parent = <&PIC>; +- phy-handle = <&PHY0>; +- linux,network-index = <0>; +- }; +- +- ethernet@1e00 { +- device_type = "network"; +- compatible = "fsl,mpc885-fec-enet", +- "fsl,pq1-fec-enet"; +- reg = <0x1e00 0x188>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <7 1>; +- interrupt-parent = <&PIC>; +- phy-handle = <&PHY1>; +- linux,network-index = <1>; +- }; +- +- PIC: interrupt-controller@0 { +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x0 0x24>; +- compatible = "fsl,mpc885-pic", "fsl,pq1-pic"; +- }; +- +- pcmcia@80 { +- #address-cells = <3>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- compatible = "fsl,pq-pcmcia"; +- device_type = "pcmcia"; +- reg = <0x80 0x80>; +- interrupt-parent = <&PIC>; +- interrupts = <13 1>; +- }; +- +- cpm@9c0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc885-cpm", "fsl,cpm1"; +- command-proc = <0x9c0>; +- interrupts = <0>; // cpm error interrupt +- interrupt-parent = <&CPM_PIC>; +- reg = <0x9c0 0x40>; +- ranges; +- +- muram@2000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2000 0x2000>; +- +- data@0 { +- compatible = "fsl,cpm-muram-data"; +- reg = <0x0 0x1c00>; +- }; +- }; +- +- brg@9f0 { +- compatible = "fsl,mpc885-brg", +- "fsl,cpm1-brg", +- "fsl,cpm-brg"; +- clock-frequency = <0>; +- reg = <0x9f0 0x10>; +- }; +- +- CPM_PIC: interrupt-controller@930 { +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupts = <5 2 0 2>; +- interrupt-parent = <&PIC>; +- reg = <0x930 0x20>; +- compatible = "fsl,mpc885-cpm-pic", +- "fsl,cpm1-pic"; +- }; +- +- serial@a80 { +- device_type = "serial"; +- compatible = "fsl,mpc885-smc-uart", +- "fsl,cpm1-smc-uart"; +- reg = <0xa80 0x10 0x3e80 0x40>; +- interrupts = <4>; +- interrupt-parent = <&CPM_PIC>; +- fsl,cpm-brg = <1>; +- fsl,cpm-command = <0x90>; +- }; +- +- serial@a90 { +- device_type = "serial"; +- compatible = "fsl,mpc885-smc-uart", +- "fsl,cpm1-smc-uart"; +- reg = <0xa90 0x10 0x3f80 0x40>; +- interrupts = <3>; +- interrupt-parent = <&CPM_PIC>; +- fsl,cpm-brg = <2>; +- fsl,cpm-command = <0xd0>; +- }; +- +- ethernet@a40 { +- device_type = "network"; +- compatible = "fsl,mpc885-scc-enet", +- "fsl,cpm1-scc-enet"; +- reg = <0xa40 0x18 0x3e00 0x100>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <28>; +- interrupt-parent = <&CPM_PIC>; +- phy-handle = <&PHY2>; +- fsl,cpm-command = <0x80>; +- linux,network-index = <2>; +- }; +- +- i2c@860 { +- compatible = "fsl,mpc885-i2c", +- "fsl,cpm1-i2c"; +- reg = <0x860 0x20 0x3c80 0x30>; +- interrupts = <16>; +- interrupt-parent = <&CPM_PIC>; +- fsl,cpm-command = <0x10>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- crypto@20000 { +- compatible = "fsl,sec1.2", "fsl,sec1.0"; +- reg = <0x20000 0x8000>; +- interrupts = <1 1>; +- interrupt-parent = <&PIC>; +- fsl,num-channels = <1>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x4c>; +- fsl,descriptor-types-mask = <0x05000154>; +- }; +- }; +- +- chosen { +- stdout-path = "/soc/cpm/serial@a80"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mucmc52.dts b/scripts/dtc/include-prefixes/powerpc/mucmc52.dts +deleted file mode 100644 +index c6c66306308d..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mucmc52.dts ++++ /dev/null +@@ -1,222 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Manroland mucmc52 board Device Tree Source +- * +- * Copyright (C) 2009 DENX Software Engineering GmbH +- * Heiko Schocher +- * Copyright 2006-2007 Secret Lab Technologies Ltd. +- */ +- +-/include/ "mpc5200b.dtsi" +- +-/* Timer pins that need to be in GPIO mode */ +-&gpt0 { gpio-controller; }; +-&gpt1 { gpio-controller; }; +-&gpt2 { gpio-controller; }; +-&gpt3 { gpio-controller; }; +- +-/* Disabled timers */ +-&gpt4 { status = "disabled"; }; +-&gpt5 { status = "disabled"; }; +-&gpt6 { status = "disabled"; }; +-&gpt7 { status = "disabled"; }; +- +-/ { +- model = "manroland,mucmc52"; +- compatible = "manroland,mucmc52"; +- +- soc5200@f0000000 { +- rtc@800 { +- status = "disabled"; +- }; +- +- can@900 { +- status = "disabled"; +- }; +- +- can@980 { +- status = "disabled"; +- }; +- +- spi@f00 { +- status = "disabled"; +- }; +- +- usb@1000 { +- status = "disabled"; +- }; +- +- psc@2000 { // PSC1 +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- psc@2200 { // PSC2 +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- psc@2400 { // PSC3 +- status = "disabled"; +- }; +- +- psc@2600 { // PSC4 +- status = "disabled"; +- }; +- +- psc@2800 { // PSC5 +- status = "disabled"; +- }; +- +- psc@2c00 { // PSC6 +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- ethernet@3000 { +- phy-handle = <&phy0>; +- }; +- +- mdio@3000 { +- phy0: ethernet-phy@0 { +- compatible = "intel,lxt971"; +- reg = <0>; +- }; +- }; +- +- i2c@3d00 { +- status = "disabled"; +- }; +- +- i2c@3d40 { +- hwmon@2c { +- compatible = "ad,adm9240"; +- reg = <0x2c>; +- }; +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- }; +- }; +- +- pci@f0000d00 { +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 0x10 */ +- 0x8000 0 0 1 &mpc5200_pic 0 3 3 +- 0x8000 0 0 2 &mpc5200_pic 0 3 3 +- 0x8000 0 0 3 &mpc5200_pic 0 2 3 +- 0x8000 0 0 4 &mpc5200_pic 0 1 3 +- >; +- ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000 +- 0x02000000 0 0x90000000 0x90000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>; +- }; +- +- localbus { +- ranges = <0 0 0xff800000 0x00800000 +- 1 0 0x80000000 0x00800000 +- 3 0 0x80000000 0x00800000>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x00800000>; +- bank-width = <4>; +- device-width = <2>; +- #size-cells = <1>; +- #address-cells = <1>; +- partition@0 { +- label = "DTS"; +- reg = <0x0 0x00100000>; +- }; +- partition@100000 { +- label = "Kernel"; +- reg = <0x100000 0x00200000>; +- }; +- partition@300000 { +- label = "RootFS"; +- reg = <0x00300000 0x00200000>; +- }; +- partition@500000 { +- label = "user"; +- reg = <0x00500000 0x00200000>; +- }; +- partition@700000 { +- label = "U-Boot"; +- reg = <0x00700000 0x00040000>; +- }; +- partition@740000 { +- label = "Env"; +- reg = <0x00740000 0x00020000>; +- }; +- partition@760000 { +- label = "red. Env"; +- reg = <0x00760000 0x00020000>; +- }; +- partition@780000 { +- label = "reserve"; +- reg = <0x00780000 0x00080000>; +- }; +- }; +- +- simple100: gpio-controller-100@3,600100 { +- compatible = "manroland,mucmc52-aux-gpio"; +- reg = <3 0x00600100 0x1>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- simple104: gpio-controller-104@3,600104 { +- compatible = "manroland,mucmc52-aux-gpio"; +- reg = <3 0x00600104 0x1>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- simple200: gpio-controller-200@3,600200 { +- compatible = "manroland,mucmc52-aux-gpio"; +- reg = <3 0x00600200 0x1>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- simple201: gpio-controller-201@3,600201 { +- compatible = "manroland,mucmc52-aux-gpio"; +- reg = <3 0x00600201 0x1>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- simple202: gpio-controller-202@3,600202 { +- compatible = "manroland,mucmc52-aux-gpio"; +- reg = <3 0x00600202 0x1>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- simple203: gpio-controller-203@3,600203 { +- compatible = "manroland,mucmc52-aux-gpio"; +- reg = <3 0x00600203 0x1>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- simple204: gpio-controller-204@3,600204 { +- compatible = "manroland,mucmc52-aux-gpio"; +- reg = <3 0x00600204 0x1>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- simple206: gpio-controller-206@3,600206 { +- compatible = "manroland,mucmc52-aux-gpio"; +- reg = <3 0x00600206 0x1>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- simple207: gpio-controller-207@3,600207 { +- compatible = "manroland,mucmc52-aux-gpio"; +- reg = <3 0x00600207 0x1>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- simple20f: gpio-controller-20f@3,60020f { +- compatible = "manroland,mucmc52-aux-gpio"; +- reg = <3 0x0060020f 0x1>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/mvme5100.dts b/scripts/dtc/include-prefixes/powerpc/mvme5100.dts +deleted file mode 100644 +index a7eb6d25903d..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/mvme5100.dts ++++ /dev/null +@@ -1,185 +0,0 @@ +-/* +- * Device Tree Source for Motorola/Emerson MVME5100. +- * +- * Copyright 2013 CSC Australia Pty. Ltd. +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- model = "MVME5100"; +- compatible = "MVME5100"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- serial0 = &serial0; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,7410 { +- device_type = "cpu"; +- reg = <0x0>; +- /* Following required by dtc but not used */ +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- timebase-frequency = <25000000>; +- clock-frequency = <500000000>; +- bus-frequency = <100000000>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x20000000>; +- }; +- +- hawk@fef80000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "hawk-bridge", "simple-bus"; +- ranges = <0x0 0xfef80000 0x10000>; +- reg = <0xfef80000 0x10000>; +- +- serial0: serial@8000 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0x8000 0x80>; +- reg-shift = <4>; +- clock-frequency = <1843200>; +- current-speed = <9600>; +- interrupts = <1 1>; // IRQ1 Level Active Low. +- interrupt-parent = <&mpic>; +- }; +- +- serial1: serial@8200 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0x8200 0x80>; +- reg-shift = <4>; +- clock-frequency = <1843200>; +- current-speed = <9600>; +- interrupts = <1 1>; // IRQ1 Level Active Low. +- interrupt-parent = <&mpic>; +- }; +- +- mpic: interrupt-controller@f3f80000 { +- #interrupt-cells = <2>; +- #address-cells = <0>; +- device_type = "open-pic"; +- compatible = "chrp,open-pic"; +- interrupt-controller; +- reg = <0xf3f80000 0x40000>; +- }; +- }; +- +- pci0: pci@feff0000 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "hawk-pci"; +- reg = <0xfec00000 0x400000>; +- 8259-interrupt-acknowledge = <0xfeff0030>; +- ranges = <0x1000000 0x0 0x0 0xfe000000 0x0 0x800000 +- 0x2000000 0x0 0x80000000 0x80000000 0x0 0x74000000>; +- bus-range = <0 255>; +- clock-frequency = <33333333>; +- interrupt-parent = <&mpic>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* +- * This definition (IDSEL 11) duplicates the +- * interrupts definition in the i8259 +- * interrupt controller below. +- * +- * Do not change the interrupt sense/polarity from +- * 0x2 to anything else, doing so will cause endless +- * "spurious" i8259 interrupts to be fielded. +- */ +- // IDSEL 11 - iPMC712 PCI/ISA Bridge +- 0x5800 0x0 0x0 0x1 &mpic 0x0 0x2 +- 0x5800 0x0 0x0 0x2 &mpic 0x0 0x2 +- 0x5800 0x0 0x0 0x3 &mpic 0x0 0x2 +- 0x5800 0x0 0x0 0x4 &mpic 0x0 0x2 +- +- /* IDSEL 12 - Not Used */ +- +- /* IDSEL 13 - Universe VME Bridge */ +- 0x6800 0x0 0x0 0x1 &mpic 0x5 0x1 +- 0x6800 0x0 0x0 0x2 &mpic 0x6 0x1 +- 0x6800 0x0 0x0 0x3 &mpic 0x7 0x1 +- 0x6800 0x0 0x0 0x4 &mpic 0x8 0x1 +- +- /* IDSEL 14 - ENET 1 */ +- 0x7000 0x0 0x0 0x1 &mpic 0x2 0x1 +- +- /* IDSEL 15 - Not Used */ +- +- /* IDSEL 16 - PMC Slot 1 */ +- 0x8000 0x0 0x0 0x1 &mpic 0x9 0x1 +- 0x8000 0x0 0x0 0x2 &mpic 0xa 0x1 +- 0x8000 0x0 0x0 0x3 &mpic 0xb 0x1 +- 0x8000 0x0 0x0 0x4 &mpic 0xc 0x1 +- +- /* IDSEL 17 - PMC Slot 2 */ +- 0x8800 0x0 0x0 0x1 &mpic 0xc 0x1 +- 0x8800 0x0 0x0 0x2 &mpic 0x9 0x1 +- 0x8800 0x0 0x0 0x3 &mpic 0xa 0x1 +- 0x8800 0x0 0x0 0x4 &mpic 0xb 0x1 +- +- /* IDSEL 18 - Not Used */ +- +- /* IDSEL 19 - ENET 2 */ +- 0x9800 0x0 0x0 0x1 &mpic 0xd 0x1 +- +- /* IDSEL 20 - PMCSPAN (PCI-X) */ +- 0xa000 0x0 0x0 0x1 &mpic 0x9 0x1 +- 0xa000 0x0 0x0 0x2 &mpic 0xa 0x1 +- 0xa000 0x0 0x0 0x3 &mpic 0xb 0x1 +- 0xa000 0x0 0x0 0x4 &mpic 0xc 0x1 +- +- >; +- +- isa { +- #address-cells = <2>; +- #size-cells = <1>; +- #interrupt-cells = <2>; +- device_type = "isa"; +- compatible = "isa"; +- ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00001000>; +- interrupt-parent = <&i8259>; +- +- i8259: interrupt-controller@20 { +- #interrupt-cells = <2>; +- #address-cells = <0>; +- interrupts = <0 2>; +- device_type = "interrupt-controller"; +- compatible = "chrp,iic"; +- interrupt-controller; +- reg = <1 0x00000020 0x00000002 +- 1 0x000000a0 0x00000002 +- 1 0x000004d0 0x00000002>; +- interrupt-parent = <&mpic>; +- }; +- +- }; +- +- }; +- +- chosen { +- stdout-path = &serial0; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/o2d.dts b/scripts/dtc/include-prefixes/powerpc/o2d.dts +deleted file mode 100644 +index e0a8d3034417..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/o2d.dts ++++ /dev/null +@@ -1,43 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * O2D Device Tree Source +- * +- * Copyright (C) 2012 DENX Software Engineering +- * Anatolij Gustschin +- */ +- +-/include/ "o2d.dtsi" +- +-/ { +- model = "ifm,o2d"; +- compatible = "ifm,o2d"; +- +- memory@0 { +- reg = <0x00000000 0x08000000>; // 128MB +- }; +- +- localbus { +- ranges = <0 0 0xfc000000 0x02000000 +- 3 0 0xe3000000 0x00100000>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x02000000>; +- bank-width = <2>; +- device-width = <2>; +- #size-cells = <1>; +- #address-cells = <1>; +- +- partition@60000 { +- label = "kernel"; +- reg = <0x00060000 0x00260000>; +- read-only; +- }; +- /* o2d specific partitions */ +- partition@2c0000 { +- label = "o2d user defined"; +- reg = <0x002c0000 0x01d40000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/o2d.dtsi b/scripts/dtc/include-prefixes/powerpc/o2d.dtsi +deleted file mode 100644 +index b55a9e5bd828..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/o2d.dtsi ++++ /dev/null +@@ -1,118 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * O2D base Device Tree Source +- * +- * Copyright (C) 2012 DENX Software Engineering +- * Anatolij Gustschin +- */ +- +-/include/ "mpc5200b.dtsi" +- +-&gpt0 { +- gpio-controller; +- fsl,has-wdt; +- fsl,wdt-on-boot = <0>; +-}; +-&gpt1 { gpio-controller; }; +- +-/ { +- model = "ifm,o2d"; +- compatible = "ifm,o2d"; +- +- memory@0 { +- reg = <0x00000000 0x04000000>; // 64MB +- }; +- +- soc5200@f0000000 { +- +- rtc@800 { +- status = "disabled"; +- }; +- +- psc@2000 { // PSC1 +- compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- +- spidev@0 { +- compatible = "spidev"; +- spi-max-frequency = <250000>; +- reg = <0>; +- }; +- }; +- +- psc@2200 { // PSC2 +- status = "disabled"; +- }; +- +- psc@2400 { // PSC3 +- status = "disabled"; +- }; +- +- psc@2600 { // PSC4 +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- psc@2800 { // PSC5 +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- psc@2c00 { // PSC6 +- status = "disabled"; +- }; +- +- ethernet@3000 { +- phy-handle = <&phy0>; +- }; +- +- mdio@3000 { +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- }; +- +- localbus { +- ranges = <0 0 0xff000000 0x01000000 +- 3 0 0xe3000000 0x00100000>; +- +- // flash device at LocalPlus Bus CS0 +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x01000000>; +- bank-width = <1>; +- device-width = <2>; +- #size-cells = <1>; +- #address-cells = <1>; +- no-unaligned-direct-access; +- +- /* common layout for all machines */ +- partition@0 { +- label = "u-boot"; +- reg = <0x00000000 0x00040000>; +- read-only; +- }; +- partition@40000 { +- label = "env"; +- reg = <0x00040000 0x00020000>; +- read-only; +- }; +- }; +- +- csi@3,0 { +- compatible = "ifm,o2d-csi"; +- reg = <3 0 0x00100000>; +- ifm,csi-clk-handle = <&gpt7>; +- gpios = <&gpio_simple 23 0 /* imag_capture */ +- &gpio_simple 26 0 /* imag_reset */ +- &gpio_simple 29 0>; /* imag_master_en */ +- +- interrupts = <1 1 2>; /* IRQ1, edge falling */ +- +- ifm,csi-addr-bus-width = <24>; +- ifm,csi-data-bus-width = <8>; +- ifm,csi-wait-cycles = <0>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/o2d300.dts b/scripts/dtc/include-prefixes/powerpc/o2d300.dts +deleted file mode 100644 +index 55a25b700bed..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/o2d300.dts ++++ /dev/null +@@ -1,48 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * O2D300 Device Tree Source +- * +- * Copyright (C) 2012 DENX Software Engineering +- * Anatolij Gustschin +- */ +- +-/include/ "o2d.dtsi" +- +-/ { +- model = "ifm,o2d300"; +- compatible = "ifm,o2d"; +- +- localbus { +- ranges = <0 0 0xfc000000 0x02000000 +- 3 0 0xe3000000 0x00100000>; +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x02000000>; +- bank-width = <2>; +- device-width = <2>; +- #size-cells = <1>; +- #address-cells = <1>; +- +- partition@40000 { +- label = "env_1"; +- reg = <0x00040000 0x00020000>; +- read-only; +- }; +- partition@60000 { +- label = "env_2"; +- reg = <0x00060000 0x00020000>; +- read-only; +- }; +- partition@80000 { +- label = "kernel"; +- reg = <0x00080000 0x00260000>; +- read-only; +- }; +- /* o2d300 specific partitions */ +- partition@2e0000 { +- label = "o2d300 user defined"; +- reg = <0x002e0000 0x01d20000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/o2dnt2.dts b/scripts/dtc/include-prefixes/powerpc/o2dnt2.dts +deleted file mode 100644 +index c2eedbd1f5fc..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/o2dnt2.dts ++++ /dev/null +@@ -1,44 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * O2DNT2 Device Tree Source +- * +- * Copyright (C) 2012 DENX Software Engineering +- * Anatolij Gustschin +- */ +- +-/include/ "o2d.dtsi" +- +-/ { +- model = "ifm,o2dnt2"; +- compatible = "ifm,o2d"; +- +- memory@0 { +- reg = <0x00000000 0x08000000>; // 128MB +- }; +- +- localbus { +- ranges = <0 0 0xfc000000 0x02000000 +- 3 0 0xe3000000 0x00100000>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x02000000>; +- bank-width = <2>; +- device-width = <2>; +- #size-cells = <1>; +- #address-cells = <1>; +- +- partition@60000 { +- label = "kernel"; +- reg = <0x00060000 0x00260000>; +- read-only; +- }; +- +- /* o2dnt2 specific partitions */ +- partition@2c0000 { +- label = "o2dnt2 user defined"; +- reg = <0x002c0000 0x01d40000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/o2i.dts b/scripts/dtc/include-prefixes/powerpc/o2i.dts +deleted file mode 100644 +index 3fb2e0ad7387..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/o2i.dts ++++ /dev/null +@@ -1,29 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * O2I Device Tree Source +- * +- * Copyright (C) 2012 DENX Software Engineering +- * Anatolij Gustschin +- */ +- +-/include/ "o2d.dtsi" +- +-/ { +- model = "ifm,o2i"; +- compatible = "ifm,o2d"; +- +- localbus { +- flash@0,0 { +- partition@60000 { +- label = "kernel"; +- reg = <0x00060000 0x00260000>; +- read-only; +- }; +- /* o2i specific partitions */ +- partition@2c0000 { +- label = "o2i user defined"; +- reg = <0x002c0000 0x00d40000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/o2mnt.dts b/scripts/dtc/include-prefixes/powerpc/o2mnt.dts +deleted file mode 100644 +index c5e0ba6e8f2b..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/o2mnt.dts ++++ /dev/null +@@ -1,29 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * O2MNT Device Tree Source +- * +- * Copyright (C) 2012 DENX Software Engineering +- * Anatolij Gustschin +- */ +- +-/include/ "o2d.dtsi" +- +-/ { +- model = "ifm,o2mnt"; +- compatible = "ifm,o2d"; +- +- localbus { +- flash@0,0 { +- partition@60000 { +- label = "kernel"; +- reg = <0x00060000 0x00260000>; +- read-only; +- }; +- /* add o2mnt specific partitions */ +- partition@2c0000 { +- label = "o2mnt user defined"; +- reg = <0x002c0000 0x00d40000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/o3dnt.dts b/scripts/dtc/include-prefixes/powerpc/o3dnt.dts +deleted file mode 100644 +index e4c1bdd41271..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/o3dnt.dts ++++ /dev/null +@@ -1,44 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * O3DNT Device Tree Source +- * +- * Copyright (C) 2012 DENX Software Engineering +- * Anatolij Gustschin +- */ +- +-/include/ "o2d.dtsi" +- +-/ { +- model = "ifm,o3dnt"; +- compatible = "ifm,o2d"; +- +- memory@0 { +- reg = <0x00000000 0x04000000>; // 64MB +- }; +- +- localbus { +- ranges = <0 0 0xfc000000 0x01000000 +- 3 0 0xe3000000 0x00100000>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x01000000>; +- bank-width = <2>; +- device-width = <2>; +- #size-cells = <1>; +- #address-cells = <1>; +- +- partition@60000 { +- label = "kernel"; +- reg = <0x00060000 0x00260000>; +- read-only; +- }; +- +- /* o3dnt specific partitions */ +- partition@2c0000 { +- label = "o3dnt user defined"; +- reg = <0x002c0000 0x00d40000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/obs600.dts b/scripts/dtc/include-prefixes/powerpc/obs600.dts +deleted file mode 100644 +index d10b0411809b..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/obs600.dts ++++ /dev/null +@@ -1,314 +0,0 @@ +-/* +- * Device Tree Source for PlatHome OpenBlockS 600 (405EX) +- * +- * Copyright 2011 Ben Herrenschmidt, IBM Corp. +- * +- * Based on Kilauea by: +- * +- * Copyright 2007-2009 DENX Software Engineering, Stefan Roese +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <1>; +- #size-cells = <1>; +- model = "PlatHome,OpenBlockS 600"; +- compatible = "plathome,obs600"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- ethernet1 = &EMAC1; +- serial0 = &UART0; +- serial1 = &UART1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,405EX"; +- reg = <0x00000000>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- timebase-frequency = <0>; /* Filled in by U-Boot */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <16384>; /* 16 kB */ +- d-cache-size = <16384>; /* 16 kB */ +- dcr-controller; +- dcr-access-method = "native"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */ +- }; +- +- UIC0: interrupt-controller { +- compatible = "ibm,uic-405ex", "ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-405ex","ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC2: interrupt-controller2 { +- compatible = "ibm,uic-405ex","ibm,uic"; +- interrupt-controller; +- cell-index = <2>; +- dcr-reg = <0x0e0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- CPM0: cpm { +- compatible = "ibm,cpm"; +- dcr-access-method = "native"; +- dcr-reg = <0x0b0 0x003>; +- unused-units = <0x00000000>; +- idle-doze = <0x02000000>; +- standby = <0xe3e74800>; +- }; +- +- plb { +- compatible = "ibm,plb-405ex", "ibm,plb4"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- SDRAM0: memory-controller { +- compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2"; +- dcr-reg = <0x010 0x002>; +- interrupt-parent = <&UIC2>; +- interrupts = <0x5 0x4 /* ECC DED Error */ +- 0x6 0x4>; /* ECC SEC Error */ +- }; +- +- CRYPTO: crypto@ef700000 { +- compatible = "amcc,ppc405ex-crypto", "amcc,ppc4xx-crypto"; +- reg = <0xef700000 0x80400>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x17 0x2>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-405ex", "ibm,mcmal2"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <2>; +- num-rx-chans = <2>; +- interrupt-parent = <&MAL0>; +- interrupts = <0x0 0x1 0x2 0x3 0x4>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- interrupt-map-mask = <0xffffffff>; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-405ex", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x80000000 0x80000000 0x10000000 +- 0xef600000 0xef600000 0x00a00000 +- 0xf0000000 0xf0000000 0x10000000>; +- dcr-reg = <0x0a0 0x005>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- EBC0: ebc { +- compatible = "ibm,ebc-405ex", "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- /* ranges property is supplied by U-Boot */ +- interrupts = <0x5 0x1>; +- interrupt-parent = <&UIC1>; +- +- nor_flash@0,0 { +- compatible = "amd,s29gl512n", "cfi-flash"; +- bank-width = <2>; +- reg = <0x00000000 0x00000000 0x08000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "kernel + initrd"; +- reg = <0x00000000 0x03de0000>; +- }; +- partition@3de0000 { +- label = "user config area"; +- reg = <0x03de0000 0x00080000>; +- }; +- partition@3e60000 { +- label = "user program area"; +- reg = <0x03e60000 0x04000000>; +- }; +- partition@7e60000 { +- label = "flat device tree"; +- reg = <0x07e60000 0x00080000>; +- }; +- partition@7ee0000 { +- label = "test program"; +- reg = <0x07ee0000 0x00080000>; +- }; +- partition@7f60000 { +- label = "u-boot env"; +- reg = <0x07f60000 0x00040000>; +- }; +- partition@7fa0000 { +- label = "u-boot"; +- reg = <0x07fa0000 0x00060000>; +- }; +- }; +- }; +- +- UART0: serial@ef600200 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600200 0x00000008>; +- virtual-reg = <0xef600200>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1a 0x4>; +- }; +- +- UART1: serial@ef600300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600300 0x00000008>; +- virtual-reg = <0xef600300>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1 0x4>; +- }; +- +- IIC0: i2c@ef600400 { +- compatible = "ibm,iic-405ex", "ibm,iic"; +- reg = <0xef600400 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x2 0x4>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtc@68 { +- compatible = "dallas,ds1340"; +- reg = <0x68>; +- }; +- }; +- +- IIC1: i2c@ef600500 { +- compatible = "ibm,iic-405ex", "ibm,iic"; +- reg = <0xef600500 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x7 0x4>; +- }; +- +- RGMII0: emac-rgmii@ef600b00 { +- compatible = "ibm,rgmii-405ex", "ibm,rgmii"; +- reg = <0xef600b00 0x00000104>; +- has-mdio; +- }; +- +- EMAC0: ethernet@ef600900 { +- linux,network-index = <0x0>; +- device_type = "network"; +- compatible = "ibm,emac-405ex", "ibm,emac4sync"; +- interrupt-parent = <&EMAC0>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600900 0x000000c4>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- tx-fifo-size-gige = <16384>; +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <0>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- +- EMAC1: ethernet@ef600a00 { +- linux,network-index = <0x1>; +- device_type = "network"; +- compatible = "ibm,emac-405ex", "ibm,emac4sync"; +- interrupt-parent = <&EMAC1>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600a00 0x000000c4>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <1>; +- mal-rx-channel = <1>; +- cell-index = <1>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- tx-fifo-size-gige = <16384>; +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <1>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- +- GPIO: gpio@ef600800 { +- device_type = "gpio"; +- compatible = "ibm,gpio-405ex", "ibm,ppc4xx-gpio"; +- reg = <0xef600800 0x50>; +- }; +- }; +- }; +- chosen { +- stdout-path = "/plb/opb/serial@ef600200"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/pcm030.dts b/scripts/dtc/include-prefixes/powerpc/pcm030.dts +deleted file mode 100644 +index b1bc731f7afd..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/pcm030.dts ++++ /dev/null +@@ -1,106 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * phyCORE-MPC5200B-tiny (pcm030) board Device Tree Source +- * +- * Copyright 2006 Pengutronix +- * Sascha Hauer +- * Copyright 2007 Pengutronix +- * Juergen Beisert +- */ +- +-/include/ "mpc5200b.dtsi" +- +-&gpt0 { fsl,has-wdt; }; +-&gpt2 { gpio-controller; }; +-&gpt3 { gpio-controller; }; +-&gpt4 { gpio-controller; }; +-&gpt5 { gpio-controller; }; +-&gpt6 { gpio-controller; }; +-&gpt7 { gpio-controller; }; +- +-/ { +- model = "phytec,pcm030"; +- compatible = "phytec,pcm030"; +- +- soc5200@f0000000 { +- audioplatform: psc@2000 { /* PSC1 in ac97 mode */ +- compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97"; +- cell-index = <0>; +- }; +- +- /* PSC2 port is used by CAN1/2 */ +- psc@2200 { +- status = "disabled"; +- }; +- +- psc@2400 { /* PSC3 in UART mode */ +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- /* PSC4 is ??? */ +- psc@2600 { +- status = "disabled"; +- }; +- +- /* PSC5 is ??? */ +- psc@2800 { +- status = "disabled"; +- }; +- +- psc@2c00 { /* PSC6 in UART mode */ +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- ethernet@3000 { +- phy-handle = <&phy0>; +- }; +- +- mdio@3000 { +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- i2c@3d40 { +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- eeprom@52 { +- compatible = "catalyst,24c32", "atmel,24c32"; +- reg = <0x52>; +- pagesize = <32>; +- }; +- }; +- +- sram@8000 { +- compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; +- reg = <0x8000 0x4000>; +- }; +- }; +- +- pci@f0000d00 { +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot +- 0xc000 0 0 2 &mpc5200_pic 1 1 3 +- 0xc000 0 0 3 &mpc5200_pic 1 2 3 +- 0xc000 0 0 4 &mpc5200_pic 1 3 3 +- +- 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot +- 0xc800 0 0 2 &mpc5200_pic 1 2 3 +- 0xc800 0 0 3 &mpc5200_pic 1 3 3 +- 0xc800 0 0 4 &mpc5200_pic 0 0 3>; +- ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 +- 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; +- }; +- +- localbus { +- status = "disabled"; +- }; +- +- sound { +- compatible = "phytec,pcm030-audio-fabric"; +- asoc-platform = <&audioplatform>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/pcm032.dts b/scripts/dtc/include-prefixes/powerpc/pcm032.dts +deleted file mode 100644 +index 1895bc95900c..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/pcm032.dts ++++ /dev/null +@@ -1,183 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * phyCORE-MPC5200B-IO (pcm032) board Device Tree Source +- * +- * Copyright (C) 2006-2009 Pengutronix +- * Sascha Hauer, Juergen Beisert, Wolfram Sang +- */ +- +-/include/ "mpc5200b.dtsi" +- +-&gpt0 { fsl,has-wdt; }; +-&gpt2 { gpio-controller; }; +-&gpt3 { gpio-controller; }; +-&gpt4 { gpio-controller; }; +-&gpt5 { gpio-controller; }; +-&gpt6 { gpio-controller; }; +-&gpt7 { gpio-controller; }; +- +-/ { +- model = "phytec,pcm032"; +- compatible = "phytec,pcm032"; +- +- memory@0 { +- reg = <0x00000000 0x08000000>; // 128MB +- }; +- +- soc5200@f0000000 { +- psc@2000 { /* PSC1 is ac97 */ +- compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; +- cell-index = <0>; +- }; +- +- /* PSC2 port is used by CAN1/2 */ +- psc@2200 { +- status = "disabled"; +- }; +- +- psc@2400 { /* PSC3 in UART mode */ +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- /* PSC4 is ??? */ +- psc@2600 { +- status = "disabled"; +- }; +- +- /* PSC5 is ??? */ +- psc@2800 { +- status = "disabled"; +- }; +- +- psc@2c00 { /* PSC6 in UART mode */ +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- ethernet@3000 { +- phy-handle = <&phy0>; +- }; +- +- mdio@3000 { +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- i2c@3d40 { +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- eeprom@52 { +- compatible = "catalyst,24c32", "atmel,24c32"; +- reg = <0x52>; +- pagesize = <32>; +- }; +- }; +- }; +- +- pci@f0000d00 { +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot +- 0xc000 0 0 2 &mpc5200_pic 1 1 3 +- 0xc000 0 0 3 &mpc5200_pic 1 2 3 +- 0xc000 0 0 4 &mpc5200_pic 1 3 3 +- +- 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot +- 0xc800 0 0 2 &mpc5200_pic 1 2 3 +- 0xc800 0 0 3 &mpc5200_pic 1 3 3 +- 0xc800 0 0 4 &mpc5200_pic 0 0 3>; +- ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 +- 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; +- }; +- +- localbus { +- ranges = <0 0 0xfe000000 0x02000000 +- 1 0 0xfc000000 0x02000000 +- 2 0 0xfbe00000 0x00200000 +- 3 0 0xf9e00000 0x02000000 +- 4 0 0xf7e00000 0x02000000 +- 5 0 0xe6000000 0x02000000 +- 6 0 0xe8000000 0x02000000 +- 7 0 0xea000000 0x02000000>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x02000000>; +- bank-width = <4>; +- #size-cells = <1>; +- #address-cells = <1>; +- +- partition@0 { +- label = "ubootl"; +- reg = <0x00000000 0x00040000>; +- }; +- partition@40000 { +- label = "kernel"; +- reg = <0x00040000 0x001c0000>; +- }; +- partition@200000 { +- label = "jffs2"; +- reg = <0x00200000 0x01d00000>; +- }; +- partition@1f00000 { +- label = "uboot"; +- reg = <0x01f00000 0x00040000>; +- }; +- partition@1f40000 { +- label = "env"; +- reg = <0x01f40000 0x00040000>; +- }; +- partition@1f80000 { +- label = "oftree"; +- reg = <0x01f80000 0x00040000>; +- }; +- partition@1fc0000 { +- label = "space"; +- reg = <0x01fc0000 0x00040000>; +- }; +- }; +- +- sram@2,0 { +- compatible = "mtd-ram"; +- reg = <2 0 0x00200000>; +- bank-width = <2>; +- }; +- +- /* +- * example snippets for FPGA +- * +- * fpga@3,0 { +- * compatible = "fpga_driver"; +- * reg = <3 0 0x02000000>; +- * bank-width = <4>; +- * }; +- * +- * fpga@4,0 { +- * compatible = "fpga_driver"; +- * reg = <4 0 0x02000000>; +- * bank-width = <4>; +- * }; +- */ +- +- /* +- * example snippets for free chipselects +- * +- * device@5,0 { +- * compatible = "custom_driver"; +- * reg = <5 0 0x02000000>; +- * }; +- * +- * device@6,0 { +- * compatible = "custom_driver"; +- * reg = <6 0 0x02000000>; +- * }; +- * +- * device@7,0 { +- * compatible = "custom_driver"; +- * reg = <7 0 0x02000000>; +- * }; +- */ +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/pdm360ng.dts b/scripts/dtc/include-prefixes/powerpc/pdm360ng.dts +deleted file mode 100644 +index 67c3b9db75d7..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/pdm360ng.dts ++++ /dev/null +@@ -1,195 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Device Tree Source for IFM PDM360NG. +- * +- * Copyright 2009 - 2010 DENX Software Engineering. +- * Anatolij Gustschin +- * +- * Based on MPC5121E ADS dts. +- * Copyright 2008 Freescale Semiconductor Inc. +- */ +- +-#include "mpc5121.dtsi" +- +-/ { +- model = "pdm360ng"; +- compatible = "ifm,pdm360ng", "fsl,mpc5121"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&ipic>; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x20000000>; // 512MB at 0 +- }; +- +- nfc@40000000 { +- bank-width = <0x1>; +- chips = <0x1>; +- +- partition@0 { +- label = "nand0"; +- reg = <0x0 0x40000000>; +- }; +- }; +- +- localbus@80000020 { +- ranges = <0x0 0x0 0xf0000000 0x10000000 /* Flash */ +- 0x2 0x0 0x50040000 0x00020000>; /* CS2: MRAM */ +- +- flash@0,0 { +- compatible = "amd,s29gl01gp", "cfi-flash"; +- reg = <0 0x00000000 0x08000000 +- 0 0x08000000 0x08000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- bank-width = <4>; +- device-width = <2>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x00000000 0x00080000>; +- read-only; +- }; +- partition@80000 { +- label = "environment"; +- reg = <0x00080000 0x00080000>; +- read-only; +- }; +- partition@100000 { +- label = "splash-image"; +- reg = <0x00100000 0x00080000>; +- read-only; +- }; +- partition@180000 { +- label = "device-tree"; +- reg = <0x00180000 0x00040000>; +- }; +- partition@1c0000 { +- label = "kernel"; +- reg = <0x001c0000 0x00500000>; +- }; +- partition@6c0000 { +- label = "filesystem"; +- reg = <0x006c0000 0x07940000>; +- }; +- }; +- +- mram0@2,0 { +- compatible = "mtd-ram"; +- reg = <2 0x00000 0x10000>; +- bank-width = <2>; +- }; +- +- mram1@2,10000 { +- compatible = "mtd-ram"; +- reg = <2 0x010000 0x10000>; +- bank-width = <2>; +- }; +- }; +- +- soc@80000000 { +- +- i2c@1700 { +- fsl,preserve-clocking; +- +- eeprom@50 { +- compatible = "atmel,24c01"; +- reg = <0x50>; +- }; +- +- rtc@68 { +- compatible = "st,m41t00"; +- reg = <0x68>; +- }; +- }; +- +- i2c@1720 { +- status = "disabled"; +- }; +- +- i2c@1740 { +- fsl,preserve-clocking; +- }; +- +- ethernet@2800 { +- phy-handle = <&phy0>; +- }; +- +- mdio@2800 { +- phy0: ethernet-phy@1f { +- compatible = "smsc,lan8700"; +- reg = <0x1f>; +- }; +- }; +- +- /* USB1 using external ULPI PHY */ +- usb@3000 { +- dr_mode = "host"; +- }; +- +- /* USB0 using internal UTMI PHY */ +- usb@4000 { +- fsl,invert-pwr-fault; +- }; +- +- psc@11000 { +- compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; +- }; +- +- psc@11100 { +- compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; +- }; +- +- psc@11200 { +- compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; +- }; +- +- psc@11300 { +- compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; +- }; +- +- psc@11400 { +- compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; +- }; +- +- psc@11500 { +- status = "disabled"; +- }; +- +- psc@11600 { +- compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; +- }; +- +- psc@11700 { +- status = "disabled"; +- }; +- +- psc@11800 { +- compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; +- }; +- +- psc@11900 { +- compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- /* ADS7845 touch screen controller */ +- ts@0 { +- compatible = "ti,ads7846"; +- reg = <0x0>; +- spi-max-frequency = <3000000>; +- /* pen irq is GPIO25 */ +- interrupts = <78 0x8>; +- }; +- }; +- +- psc@11a00 { +- status = "disabled"; +- }; +- +- psc@11b00 { +- compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/pq2fads.dts b/scripts/dtc/include-prefixes/powerpc/pq2fads.dts +deleted file mode 100644 +index b6666215ed63..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/pq2fads.dts ++++ /dev/null +@@ -1,243 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Device Tree for the PQ2FADS-ZU board with an MPC8280 chip. +- * +- * Copyright 2007,2008 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/ { +- model = "pq2fads"; +- compatible = "fsl,pq2fads"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <16384>; +- i-cache-size = <16384>; +- timebase-frequency = <0>; +- clock-frequency = <0>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; +- }; +- +- localbus@f0010100 { +- compatible = "fsl,mpc8280-localbus", +- "fsl,pq2-localbus"; +- #address-cells = <2>; +- #size-cells = <1>; +- reg = <0xf0010100 0x60>; +- +- ranges = <0x0 0x0 0xff800000 0x800000 +- 0x1 0x0 0xf4500000 0x8000 +- 0x8 0x0 0xf8200000 0x8000>; +- +- flash@0,0 { +- compatible = "jedec-flash"; +- reg = <0x0 0x0 0x800000>; +- bank-width = <4>; +- device-width = <1>; +- }; +- +- bcsr@1,0 { +- reg = <0x1 0x0 0x20>; +- compatible = "fsl,pq2fads-bcsr"; +- }; +- +- PCI_PIC: pic@8,0 { +- #interrupt-cells = <1>; +- interrupt-controller; +- reg = <0x8 0x0 0x8>; +- compatible = "fsl,pq2ads-pci-pic"; +- interrupt-parent = <&PIC>; +- interrupts = <24 8>; +- }; +- }; +- +- pci0: pci@f0010800 { +- device_type = "pci"; +- reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>; +- compatible = "fsl,mpc8280-pci", "fsl,pq2-pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- clock-frequency = <66000000>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x16 */ +- 0xb000 0x0 0x0 0x1 &PCI_PIC 0 +- 0xb000 0x0 0x0 0x2 &PCI_PIC 1 +- 0xb000 0x0 0x0 0x3 &PCI_PIC 2 +- 0xb000 0x0 0x0 0x4 &PCI_PIC 3 +- +- /* IDSEL 0x17 */ +- 0xb800 0x0 0x0 0x1 &PCI_PIC 4 +- 0xb800 0x0 0x0 0x2 &PCI_PIC 5 +- 0xb800 0x0 0x0 0x3 &PCI_PIC 6 +- 0xb800 0x0 0x0 0x4 &PCI_PIC 7 +- +- /* IDSEL 0x18 */ +- 0xc000 0x0 0x0 0x1 &PCI_PIC 8 +- 0xc000 0x0 0x0 0x2 &PCI_PIC 9 +- 0xc000 0x0 0x0 0x3 &PCI_PIC 10 +- 0xc000 0x0 0x0 0x4 &PCI_PIC 11>; +- +- interrupt-parent = <&PIC>; +- interrupts = <18 8>; +- ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000 +- 0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>; +- }; +- +- soc@f0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,mpc8280", "fsl,pq2-soc"; +- ranges = <0x0 0xf0000000 0x53000>; +- +- // Temporary -- will go away once kernel uses ranges for get_immrbase(). +- reg = <0xf0000000 0x53000>; +- +- cpm@119c0 { +- #address-cells = <1>; +- #size-cells = <1>; +- #interrupt-cells = <2>; +- compatible = "fsl,mpc8280-cpm", "fsl,cpm2"; +- reg = <0x119c0 0x30>; +- ranges; +- +- muram@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x0 0x10000>; +- +- data@0 { +- compatible = "fsl,cpm-muram-data"; +- reg = <0x0 0x2000 0x9800 0x800>; +- }; +- }; +- +- brg@119f0 { +- compatible = "fsl,mpc8280-brg", +- "fsl,cpm2-brg", +- "fsl,cpm-brg"; +- reg = <0x119f0 0x10 0x115f0 0x10>; +- }; +- +- serial0: serial@11a00 { +- device_type = "serial"; +- compatible = "fsl,mpc8280-scc-uart", +- "fsl,cpm2-scc-uart"; +- reg = <0x11a00 0x20 0x8000 0x100>; +- interrupts = <40 8>; +- interrupt-parent = <&PIC>; +- fsl,cpm-brg = <1>; +- fsl,cpm-command = <0x800000>; +- }; +- +- serial1: serial@11a20 { +- device_type = "serial"; +- compatible = "fsl,mpc8280-scc-uart", +- "fsl,cpm2-scc-uart"; +- reg = <0x11a20 0x20 0x8100 0x100>; +- interrupts = <41 8>; +- interrupt-parent = <&PIC>; +- fsl,cpm-brg = <2>; +- fsl,cpm-command = <0x4a00000>; +- }; +- +- enet0: ethernet@11320 { +- device_type = "network"; +- compatible = "fsl,mpc8280-fcc-enet", +- "fsl,cpm2-fcc-enet"; +- reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>; +- interrupts = <33 8>; +- interrupt-parent = <&PIC>; +- phy-handle = <&PHY0>; +- linux,network-index = <0>; +- fsl,cpm-command = <0x16200300>; +- }; +- +- enet1: ethernet@11340 { +- device_type = "network"; +- compatible = "fsl,mpc8280-fcc-enet", +- "fsl,cpm2-fcc-enet"; +- reg = <0x11340 0x20 0x8600 0x100 0x113d0 0x1>; +- interrupts = <34 8>; +- interrupt-parent = <&PIC>; +- phy-handle = <&PHY1>; +- linux,network-index = <1>; +- fsl,cpm-command = <0x1a400300>; +- local-mac-address = [00 e0 0c 00 79 01]; +- }; +- +- mdio@10d40 { +- compatible = "fsl,pq2fads-mdio-bitbang", +- "fsl,mpc8280-mdio-bitbang", +- "fsl,cpm2-mdio-bitbang"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x10d40 0x14>; +- fsl,mdio-pin = <9>; +- fsl,mdc-pin = <10>; +- +- PHY0: ethernet-phy@0 { +- interrupt-parent = <&PIC>; +- interrupts = <25 2>; +- reg = <0x0>; +- }; +- +- PHY1: ethernet-phy@1 { +- interrupt-parent = <&PIC>; +- interrupts = <25 2>; +- reg = <0x3>; +- }; +- }; +- +- usb@11b60 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc8280-usb", +- "fsl,cpm2-usb"; +- reg = <0x11b60 0x18 0x8b00 0x100>; +- interrupt-parent = <&PIC>; +- interrupts = <11 8>; +- fsl,cpm-command = <0x2e600000>; +- }; +- }; +- +- PIC: interrupt-controller@10c00 { +- #interrupt-cells = <2>; +- interrupt-controller; +- reg = <0x10c00 0x80>; +- compatible = "fsl,mpc8280-pic", "fsl,cpm2-pic"; +- }; +- +- }; +- +- chosen { +- stdout-path = "/soc/cpm/serial@11a00"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/ps3.dts b/scripts/dtc/include-prefixes/powerpc/ps3.dts +deleted file mode 100644 +index 6bdfba6cbb30..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/ps3.dts ++++ /dev/null +@@ -1,58 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * PS3 Game Console device tree. +- * +- * Copyright (C) 2007 Sony Computer Entertainment Inc. +- * Copyright 2007 Sony Corp. +- */ +- +-/dts-v1/; +- +-/ { +- model = "SonyPS3"; +- compatible = "sony,ps3"; +- #size-cells = <2>; +- #address-cells = <2>; +- +- chosen { +- }; +- +- /* +- * We'll get the size of the bootmem block from lv1 after startup, +- * so we'll put a null entry here. +- */ +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000 0x00000000>; +- }; +- +- /* +- * The boot cpu is always zero for PS3. +- * +- * dtc expects a clock-frequency and timebase-frequency entries, so +- * we'll put a null entries here. These will be initialized after +- * startup with data from lv1. +- * +- * Seems the only way currently to indicate a processor has multiple +- * threads is with an ibm,ppc-interrupt-server#s entry. We'll put one +- * here so we can bring up both of ours. See smp_setup_cpu_maps(). +- */ +- +- cpus { +- #size-cells = <0>; +- #address-cells = <1>; +- +- cpu@0 { +- device_type = "cpu"; +- reg = <0x00000000>; +- ibm,ppc-interrupt-server#s = <0x0 0x1>; +- clock-frequency = <0>; +- timebase-frequency = <0>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- i-cache-line-size = <128>; +- d-cache-line-size = <128>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/rainier.dts b/scripts/dtc/include-prefixes/powerpc/rainier.dts +deleted file mode 100644 +index e59829cff556..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/rainier.dts ++++ /dev/null +@@ -1,350 +0,0 @@ +-/* +- * Device Tree Source for AMCC Rainier +- * +- * Based on Sequoia code +- * Copyright (c) 2007 MontaVista Software, Inc. +- * +- * FIXME: Draft only! +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- * +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <2>; +- #size-cells = <1>; +- model = "amcc,rainier"; +- compatible = "amcc,rainier"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- ethernet1 = &EMAC1; +- serial0 = &UART0; +- serial1 = &UART1; +- serial2 = &UART2; +- serial3 = &UART3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,440GRx"; +- reg = <0x00000000>; +- clock-frequency = <0>; /* Filled in by zImage */ +- timebase-frequency = <0>; /* Filled in by zImage */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */ +- }; +- +- UIC0: interrupt-controller0 { +- compatible = "ibm,uic-440grx","ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-440grx","ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC2: interrupt-controller2 { +- compatible = "ibm,uic-440grx","ibm,uic"; +- interrupt-controller; +- cell-index = <2>; +- dcr-reg = <0x0e0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- SDR0: sdr { +- compatible = "ibm,sdr-440grx", "ibm,sdr-440ep"; +- dcr-reg = <0x00e 0x002>; +- }; +- +- CPR0: cpr { +- compatible = "ibm,cpr-440grx", "ibm,cpr-440ep"; +- dcr-reg = <0x00c 0x002>; +- }; +- +- plb { +- compatible = "ibm,plb-440grx", "ibm,plb4"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; /* Filled in by zImage */ +- +- SDRAM0: sdram { +- compatible = "ibm,sdram-440grx", "ibm,sdram-44x-ddr2denali"; +- dcr-reg = <0x010 0x002>; +- }; +- +- DMA0: dma { +- compatible = "ibm,dma-440grx", "ibm,dma-4xx"; +- dcr-reg = <0x100 0x027>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-440grx", "ibm,mcmal2"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <2>; +- num-rx-chans = <2>; +- interrupt-parent = <&MAL0>; +- interrupts = <0x0 0x1 0x2 0x3 0x4>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- interrupt-map-mask = <0xffffffff>; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-440grx", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000001 0x00000000 0x80000000 +- 0x80000000 0x00000001 0x80000000 0x80000000>; +- interrupt-parent = <&UIC1>; +- interrupts = <0x7 0x4>; +- clock-frequency = <0>; /* Filled in by zImage */ +- +- EBC0: ebc { +- compatible = "ibm,ebc-440grx", "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; /* Filled in by zImage */ +- interrupts = <0x5 0x1>; +- interrupt-parent = <&UIC1>; +- +- nor_flash@0,0 { +- compatible = "amd,s29gl256n", "cfi-flash"; +- bank-width = <2>; +- reg = <0x00000000 0x00000000 0x04000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "Kernel"; +- reg = <0x00000000 0x00180000>; +- }; +- partition@180000 { +- label = "ramdisk"; +- reg = <0x00180000 0x00200000>; +- }; +- partition@380000 { +- label = "file system"; +- reg = <0x00380000 0x03aa0000>; +- }; +- partition@3e20000 { +- label = "kozio"; +- reg = <0x03e20000 0x00140000>; +- }; +- partition@3f60000 { +- label = "env"; +- reg = <0x03f60000 0x00040000>; +- }; +- partition@3fa0000 { +- label = "u-boot"; +- reg = <0x03fa0000 0x00060000>; +- }; +- }; +- +- }; +- +- UART0: serial@ef600300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600300 0x00000008>; +- virtual-reg = <0xef600300>; +- clock-frequency = <0>; /* Filled in by zImage */ +- current-speed = <115200>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x0 0x4>; +- }; +- +- UART1: serial@ef600400 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600400 0x00000008>; +- virtual-reg = <0xef600400>; +- clock-frequency = <0>; +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1 0x4>; +- }; +- +- UART2: serial@ef600500 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600500 0x00000008>; +- virtual-reg = <0xef600500>; +- clock-frequency = <0>; +- current-speed = <0>; +- interrupt-parent = <&UIC1>; +- interrupts = <0x3 0x4>; +- }; +- +- UART3: serial@ef600600 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600600 0x00000008>; +- virtual-reg = <0xef600600>; +- clock-frequency = <0>; +- current-speed = <0>; +- interrupt-parent = <&UIC1>; +- interrupts = <0x4 0x4>; +- }; +- +- IIC0: i2c@ef600700 { +- compatible = "ibm,iic-440grx", "ibm,iic"; +- reg = <0xef600700 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x2 0x4>; +- }; +- +- IIC1: i2c@ef600800 { +- compatible = "ibm,iic-440grx", "ibm,iic"; +- reg = <0xef600800 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x7 0x4>; +- }; +- +- ZMII0: emac-zmii@ef600d00 { +- compatible = "ibm,zmii-440grx", "ibm,zmii"; +- reg = <0xef600d00 0x0000000c>; +- }; +- +- RGMII0: emac-rgmii@ef601000 { +- compatible = "ibm,rgmii-440grx", "ibm,rgmii"; +- reg = <0xef601000 0x00000008>; +- has-mdio; +- }; +- +- EMAC0: ethernet@ef600e00 { +- device_type = "network"; +- compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4"; +- interrupt-parent = <&EMAC0>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600e00 0x00000074>; +- local-mac-address = [000000000000]; +- mal-device = <&MAL0>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- zmii-device = <&ZMII0>; +- zmii-channel = <0>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <0>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- +- EMAC1: ethernet@ef600f00 { +- device_type = "network"; +- compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4"; +- interrupt-parent = <&EMAC1>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600f00 0x00000074>; +- local-mac-address = [000000000000]; +- mal-device = <&MAL0>; +- mal-tx-channel = <1>; +- mal-rx-channel = <1>; +- cell-index = <1>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- zmii-device = <&ZMII0>; +- zmii-channel = <1>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <1>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- }; +- +- PCI0: pci@1ec000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb440grx-pci", "ibm,plb-pci"; +- primary; +- reg = <0x00000001 0xeec00000 0x00000008 /* Config space access */ +- 0x00000001 0xeed00000 0x00000004 /* IACK */ +- 0x00000001 0xeed00000 0x00000004 /* Special cycle */ +- 0x00000001 0xef400000 0x00000040>; /* Internal registers */ +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed. Chip supports a second +- * IO range but we don't use it for now +- */ +- ranges = <0x02000000 0x0 0x80000000 0x1 0x80000000 0x0 0x40000000 +- 0x01000000 0x0 0x00000000 0x1 0xe8000000 0x0 0x00010000 +- 0x01000000 0x0 0x00000000 0x1 0xe8800000 0x0 0x03800000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; +- +- /* All PCI interrupts are routed to IRQ 67 */ +- interrupt-map-mask = <0x0 0x0 0x0 0x0>; +- interrupt-map = < 0x0 0x0 0x0 0x0 &UIC2 0x3 0x8 >; +- }; +- }; +- +- chosen { +- stdout-path = "/plb/opb/serial@ef600300"; +- bootargs = "console=ttyS0,115200"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/redwood.dts b/scripts/dtc/include-prefixes/powerpc/redwood.dts +deleted file mode 100644 +index f38035a1f4a1..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/redwood.dts ++++ /dev/null +@@ -1,387 +0,0 @@ +-/* +- * Device Tree Source for AMCC Redwood(460SX) +- * +- * Copyright 2008 AMCC +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <2>; +- #size-cells = <1>; +- model = "amcc,redwood"; +- compatible = "amcc,redwood"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- serial0 = &UART0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,460SX"; +- reg = <0x00000000>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- timebase-frequency = <0>; /* Filled in by U-Boot */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ +- }; +- +- UIC0: interrupt-controller0 { +- compatible = "ibm,uic-460sx","ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-460sx","ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC2: interrupt-controller2 { +- compatible = "ibm,uic-460sx","ibm,uic"; +- interrupt-controller; +- cell-index = <2>; +- dcr-reg = <0x0e0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC3: interrupt-controller3 { +- compatible = "ibm,uic-460sx","ibm,uic"; +- interrupt-controller; +- cell-index = <3>; +- dcr-reg = <0x0f0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- SDR0: sdr { +- compatible = "ibm,sdr-460sx"; +- dcr-reg = <0x00e 0x002>; +- }; +- +- CPR0: cpr { +- compatible = "ibm,cpr-460sx"; +- dcr-reg = <0x00c 0x002>; +- }; +- +- plb { +- compatible = "ibm,plb-460sx", "ibm,plb4"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- SDRAM0: sdram { +- compatible = "ibm,sdram-460sx", "ibm,sdram-405gp"; +- dcr-reg = <0x010 0x002>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-460sx", "ibm,mcmal2"; +- dcr-reg = <0x180 0x62>; +- num-tx-chans = <4>; +- num-rx-chans = <32>; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&UIC1>; +- interrupts = < /*TXEOB*/ 0x6 0x4 +- /*RXEOB*/ 0x7 0x4 +- /*SERR*/ 0x1 0x4 +- /*TXDE*/ 0x2 0x4 +- /*RXDE*/ 0x3 0x4 +- /*COAL TX0*/ 0x18 0x2 +- /*COAL TX1*/ 0x19 0x2 +- /*COAL TX2*/ 0x1a 0x2 +- /*COAL TX3*/ 0x1b 0x2 +- /*COAL RX0*/ 0x1c 0x2 +- /*COAL RX1*/ 0x1d 0x2 +- /*COAL RX2*/ 0x1e 0x2 +- /*COAL RX3*/ 0x1f 0x2>; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-460sx", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- +- EBC0: ebc { +- compatible = "ibm,ebc-460sx", "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- /* ranges property is supplied by U-Boot */ +- interrupts = <0x6 0x4>; +- interrupt-parent = <&UIC1>; +- +- nor_flash@0,0 { +- compatible = "amd,s29gl512n", "cfi-flash"; +- bank-width = <2>; +- reg = <0x0000000 0x00000000 0x04000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x001e0000>; +- }; +- partition@1e0000 { +- label = "dtb"; +- reg = <0x001e0000 0x00020000>; +- }; +- partition@200000 { +- label = "ramdisk"; +- reg = <0x00200000 0x01400000>; +- }; +- partition@1600000 { +- label = "jffs2"; +- reg = <0x01600000 0x00400000>; +- }; +- partition@1a00000 { +- label = "user"; +- reg = <0x01a00000 0x02560000>; +- }; +- partition@3f60000 { +- label = "env"; +- reg = <0x03f60000 0x00040000>; +- }; +- partition@3fa0000 { +- label = "u-boot"; +- reg = <0x03fa0000 0x00060000>; +- }; +- }; +- }; +- +- UART0: serial@ef600200 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600200 0x00000008>; +- virtual-reg = <0xef600200>; +- clock-frequency = <0>; /* Filled in by U-Boot */ +- current-speed = <0>; /* Filled in by U-Boot */ +- interrupt-parent = <&UIC0>; +- interrupts = <0x0 0x4>; +- }; +- +- RGMII0: emac-rgmii@ef600900 { +- compatible = "ibm,rgmii-460sx", "ibm,rgmii"; +- reg = <0xef600900 0x00000008>; +- }; +- +- EMAC0: ethernet@ef600a00 { +- device_type = "network"; +- compatible = "ibm,emac-460sx", "ibm,emac4"; +- interrupt-parent = <&EMAC0>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600a00 0x00000070>; +- local-mac-address = [000000000000]; /* Filled in by U-Boot */ +- mal-device = <&MAL0>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- rx-fifo-size-gige = <16384>; +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <0>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- }; +- PCIE0: pcie@d00000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex"; +- primary; +- port = <0x0>; /* port number */ +- reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ +- 0x0000000c 0x10000000 0x00001000>; /* Registers */ +- dcr-reg = <0x100 0x020>; +- sdr-base = <0x300>; +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 +- 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; +- +- /* This drives busses 10 to 0x1f */ +- bus-range = <0x10 0x1f>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */ +- 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */ +- 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */ +- 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>; +- }; +- +- PCIE1: pcie@d20000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex"; +- primary; +- port = <0x1>; /* port number */ +- reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ +- 0x0000000c 0x10001000 0x00001000>; /* Registers */ +- dcr-reg = <0x120 0x020>; +- sdr-base = <0x340>; +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 +- 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; +- +- /* This drives busses 10 to 0x1f */ +- bus-range = <0x20 0x2f>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */ +- 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */ +- 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */ +- 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>; +- }; +- +- PCIE2: pcie@d40000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex"; +- primary; +- port = <0x2>; /* port number */ +- reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */ +- 0x0000000c 0x10002000 0x00001000>; /* Registers */ +- dcr-reg = <0x140 0x020>; +- sdr-base = <0x370>; +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000 +- 0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; +- +- /* This drives busses 10 to 0x1f */ +- bus-range = <0x30 0x3f>; +- +- /* Legacy interrupts (note the weird polarity, the bridge seems +- * to invert PCIe legacy interrupts). +- * We are de-swizzling here because the numbers are actually for +- * port of the root complex virtual P2P bridge. But I want +- * to avoid putting a node for it in the tree, so the numbers +- * below are basically de-swizzled numbers. +- * The real slot is on idsel 0, so the swizzling is 1:1 +- */ +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */ +- 0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */ +- 0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */ +- 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>; +- }; +- +- MSI: ppc4xx-msi@400300000 { +- compatible = "amcc,ppc4xx-msi", "ppc4xx-msi"; +- reg = < 0x4 0x00300000 0x100 +- 0x4 0x00300000 0x100>; +- sdr-base = <0x3B0>; +- msi-data = <0x00000000>; +- msi-mask = <0x44440000>; +- interrupt-count = <3>; +- interrupts =<0 1 2 3>; +- interrupt-parent = <&UIC0>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = <0 &UIC0 0xC 1 +- 1 &UIC0 0x0D 1 +- 2 &UIC0 0x0E 1 +- 3 &UIC0 0x0F 1>; +- }; +- +- }; +- +- +- chosen { +- stdout-path = "/plb/opb/serial@ef600200"; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/sam440ep.dts b/scripts/dtc/include-prefixes/powerpc/sam440ep.dts +deleted file mode 100644 +index 7d15f18e1180..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/sam440ep.dts ++++ /dev/null +@@ -1,293 +0,0 @@ +-/* +- * Device Tree Source for ACube Sam440ep based off bamboo.dts code +- * original copyrights below +- * +- * Copyright (c) 2006, 2007 IBM Corp. +- * Josh Boyer +- * +- * Modified from bamboo.dts for sam440ep: +- * Copyright 2008 Giuseppe Coviello +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <2>; +- #size-cells = <1>; +- model = "acube,sam440ep"; +- compatible = "acube,sam440ep"; +- +- aliases { +- ethernet0 = &EMAC0; +- ethernet1 = &EMAC1; +- serial0 = &UART0; +- serial1 = &UART1; +- serial2 = &UART2; +- serial3 = &UART3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,440EP"; +- reg = <0>; +- clock-frequency = <0>; /* Filled in by zImage */ +- timebase-frequency = <0>; /* Filled in by zImage */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0 0 0>; /* Filled in by zImage */ +- }; +- +- UIC0: interrupt-controller0 { +- compatible = "ibm,uic-440ep","ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 9>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-440ep","ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 9>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 4 0x1f 4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- SDR0: sdr { +- compatible = "ibm,sdr-440ep"; +- dcr-reg = <0x00e 2>; +- }; +- +- CPR0: cpr { +- compatible = "ibm,cpr-440ep"; +- dcr-reg = <0x00c 2>; +- }; +- +- plb { +- compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; /* Filled in by zImage */ +- +- SDRAM0: sdram { +- compatible = "ibm,sdram-440ep", "ibm,sdram-405gp"; +- dcr-reg = <0x010 2>; +- }; +- +- DMA0: dma { +- compatible = "ibm,dma-440ep", "ibm,dma-440gp"; +- dcr-reg = <0x100 0x027>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <4>; +- num-rx-chans = <2>; +- interrupt-parent = <&MAL0>; +- interrupts = <0 1 2 3 4>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- /* Bamboo is oddball in the 44x world and doesn't use the ERPN +- * bits. +- */ +- ranges = <0x00000000 0 0x00000000 0x80000000 +- 0x80000000 0 0x80000000 0x80000000>; +- interrupt-parent = <&UIC1>; +- interrupts = <7 4>; +- clock-frequency = <0>; /* Filled in by zImage */ +- +- EBC0: ebc { +- compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc"; +- dcr-reg = <0x012 2>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; /* Filled in by zImage */ +- interrupts = <5 1>; +- interrupt-parent = <&UIC1>; +- }; +- +- UART0: serial@ef600300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600300 8>; +- virtual-reg = <0xef600300>; +- clock-frequency = <0>; /* Filled in by zImage */ +- current-speed = <0x1c200>; +- interrupt-parent = <&UIC0>; +- interrupts = <0 4>; +- }; +- +- UART1: serial@ef600400 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600400 8>; +- virtual-reg = <0xef600400>; +- clock-frequency = <0>; +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <1 4>; +- }; +- +- UART2: serial@ef600500 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600500 8>; +- virtual-reg = <0xef600500>; +- clock-frequency = <0>; +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <3 4>; +- }; +- +- UART3: serial@ef600600 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600600 8>; +- virtual-reg = <0xef600600>; +- clock-frequency = <0>; +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <4 4>; +- }; +- +- IIC0: i2c@ef600700 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; +- index = <0>; +- reg = <0xef600700 0x14>; +- interrupt-parent = <&UIC0>; +- interrupts = <2 4>; +- rtc@68 { +- compatible = "st,m41t80"; +- reg = <0x68>; +- }; +- }; +- +- IIC1: i2c@ef600800 { +- compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; +- index = <5>; +- reg = <0xef600800 0x14>; +- interrupt-parent = <&UIC0>; +- interrupts = <7 4>; +- }; +- +- ZMII0: emac-zmii@ef600d00 { +- compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii"; +- reg = <0xef600d00 0xc>; +- }; +- +- EMAC0: ethernet@ef600e00 { +- linux,network-index = <0>; +- device_type = "network"; +- compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; +- interrupt-parent = <&UIC1>; +- interrupts = <0x1c 4 0x1d 4>; +- reg = <0xef600e00 0x70>; +- local-mac-address = [000000000000]; +- mal-device = <&MAL0>; +- mal-tx-channel = <0 1>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <0x5dc>; +- rx-fifo-size = <0x1000>; +- tx-fifo-size = <0x800>; +- phy-mode = "rmii"; +- phy-map = <00000000>; +- zmii-device = <&ZMII0>; +- zmii-channel = <0>; +- }; +- +- EMAC1: ethernet@ef600f00 { +- linux,network-index = <1>; +- device_type = "network"; +- compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; +- interrupt-parent = <&UIC1>; +- interrupts = <0x1e 4 0x1f 4>; +- reg = <0xef600f00 0x70>; +- local-mac-address = [000000000000]; +- mal-device = <&MAL0>; +- mal-tx-channel = <2 3>; +- mal-rx-channel = <1>; +- cell-index = <1>; +- max-frame-size = <0x5dc>; +- rx-fifo-size = <0x1000>; +- tx-fifo-size = <0x800>; +- phy-mode = "rmii"; +- phy-map = <00000000>; +- zmii-device = <&ZMII0>; +- zmii-channel = <1>; +- }; +- usb@ef601000 { +- compatible = "ohci-be"; +- reg = <0xef601000 0x80>; +- interrupts = <8 4 9 4>; +- interrupt-parent = <&UIC1>; +- }; +- }; +- +- PCI0: pci@ec000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb440ep-pci", "ibm,plb-pci"; +- primary; +- reg = <0 0xeec00000 8 /* Config space access */ +- 0 0xeed00000 4 /* IACK */ +- 0 0xeed00000 4 /* Special cycle */ +- 0 0xef400000 0x40>; /* Internal registers */ +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed. Chip supports a second +- * IO range but we don't use it for now +- */ +- ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000 +- 0x01000000 0 0x00000000 0 0xe8000000 0 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0 0 0 0 0 0x80000000>; +- }; +- }; +- +- chosen { +- stdout-path = "/plb/opb/serial@ef600300"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/sequoia.dts b/scripts/dtc/include-prefixes/powerpc/sequoia.dts +deleted file mode 100644 +index 60d211da9593..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/sequoia.dts ++++ /dev/null +@@ -1,412 +0,0 @@ +-/* +- * Device Tree Source for AMCC Sequoia +- * +- * Based on Bamboo code by Josh Boyer +- * Copyright (c) 2006, 2007 IBM Corp. +- * +- * FIXME: Draft only! +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- * +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <2>; +- #size-cells = <1>; +- model = "amcc,sequoia"; +- compatible = "amcc,sequoia"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- ethernet1 = &EMAC1; +- serial0 = &UART0; +- serial1 = &UART1; +- serial2 = &UART2; +- serial3 = &UART3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,440EPx"; +- reg = <0x00000000>; +- clock-frequency = <0>; /* Filled in by zImage */ +- timebase-frequency = <0>; /* Filled in by zImage */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */ +- }; +- +- UIC0: interrupt-controller0 { +- compatible = "ibm,uic-440epx","ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-440epx","ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- UIC2: interrupt-controller2 { +- compatible = "ibm,uic-440epx","ibm,uic"; +- interrupt-controller; +- cell-index = <2>; +- dcr-reg = <0x0e0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- SDR0: sdr { +- compatible = "ibm,sdr-440epx", "ibm,sdr-440ep"; +- dcr-reg = <0x00e 0x002>; +- }; +- +- CPR0: cpr { +- compatible = "ibm,cpr-440epx", "ibm,cpr-440ep"; +- dcr-reg = <0x00c 0x002>; +- }; +- +- plb { +- compatible = "ibm,plb-440epx", "ibm,plb4"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; /* Filled in by zImage */ +- +- SDRAM0: sdram { +- compatible = "ibm,sdram-440epx", "ibm,sdram-44x-ddr2denali"; +- dcr-reg = <0x010 0x002>; +- }; +- +- CRYPTO: crypto@e0100000 { +- compatible = "amcc,ppc440epx-crypto","amcc,ppc4xx-crypto"; +- reg = <0 0xE0100000 0x80400>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x17 0x4>; +- }; +- +- rng@e0120000 { +- compatible = "amcc,ppc440epx-rng","amcc,ppc4xx-rng"; +- reg = <0 0xE0120000 0x150>; +- }; +- +- DMA0: dma { +- compatible = "ibm,dma-440epx", "ibm,dma-4xx"; +- dcr-reg = <0x100 0x027>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-440epx", "ibm,mcmal2"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <2>; +- num-rx-chans = <2>; +- interrupt-parent = <&MAL0>; +- interrupts = <0x0 0x1 0x2 0x3 0x4>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- interrupt-map-mask = <0xffffffff>; +- }; +- +- USB1: usb@e0000400 { +- compatible = "ibm,usb-ohci-440epx", "ohci-be"; +- reg = <0x00000000 0xe0000400 0x00000060>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x15 0x8>; +- }; +- +- USB0: ehci@e0000300 { +- compatible = "ibm,usb-ehci-440epx", "usb-ehci"; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1a 0x4>; +- reg = <0x00000000 0xe0000300 0x00000090 0x00000000 0xe0000390 0x00000070>; +- big-endian; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-440epx", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000001 0x00000000 0x80000000 +- 0x80000000 0x00000001 0x80000000 0x80000000>; +- interrupt-parent = <&UIC1>; +- interrupts = <0x7 0x4>; +- clock-frequency = <0>; /* Filled in by zImage */ +- +- EBC0: ebc { +- compatible = "ibm,ebc-440epx", "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; /* Filled in by zImage */ +- interrupts = <0x5 0x1>; +- interrupt-parent = <&UIC1>; +- +- nor_flash@0,0 { +- compatible = "amd,s29gl256n", "cfi-flash"; +- bank-width = <2>; +- reg = <0x00000000 0x00000000 0x04000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "Kernel"; +- reg = <0x00000000 0x00180000>; +- }; +- partition@180000 { +- label = "ramdisk"; +- reg = <0x00180000 0x00200000>; +- }; +- partition@380000 { +- label = "file system"; +- reg = <0x00380000 0x03aa0000>; +- }; +- partition@3e20000 { +- label = "kozio"; +- reg = <0x03e20000 0x00140000>; +- }; +- partition@3f60000 { +- label = "env"; +- reg = <0x03f60000 0x00040000>; +- }; +- partition@3fa0000 { +- label = "u-boot"; +- reg = <0x03fa0000 0x00060000>; +- }; +- }; +- +- ndfc@3,0 { +- compatible = "ibm,ndfc"; +- reg = <0x00000003 0x00000000 0x00002000>; +- ccr = <0x00001000>; +- bank-settings = <0x80002222>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- nand { +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x00000000 0x00084000>; +- }; +- partition@84000 { +- label = "user"; +- reg = <0x00084000 0x01f7c000>; +- }; +- }; +- }; +- }; +- +- UART0: serial@ef600300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600300 0x00000008>; +- virtual-reg = <0xef600300>; +- clock-frequency = <0>; /* Filled in by zImage */ +- current-speed = <115200>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x0 0x4>; +- }; +- +- UART1: serial@ef600400 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600400 0x00000008>; +- virtual-reg = <0xef600400>; +- clock-frequency = <0>; +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1 0x4>; +- }; +- +- UART2: serial@ef600500 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600500 0x00000008>; +- virtual-reg = <0xef600500>; +- clock-frequency = <0>; +- current-speed = <0>; +- interrupt-parent = <&UIC1>; +- interrupts = <0x3 0x4>; +- }; +- +- UART3: serial@ef600600 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600600 0x00000008>; +- virtual-reg = <0xef600600>; +- clock-frequency = <0>; +- current-speed = <0>; +- interrupt-parent = <&UIC1>; +- interrupts = <0x4 0x4>; +- }; +- +- IIC0: i2c@ef600700 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "ibm,iic-440epx", "ibm,iic"; +- reg = <0xef600700 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x2 0x4>; +- +- hwmon@48 { +- compatible = "adi,ad7414"; +- reg = <0x48>; +- }; +- }; +- +- IIC1: i2c@ef600800 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "ibm,iic-440epx", "ibm,iic"; +- reg = <0xef600800 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x7 0x4>; +- }; +- +- ZMII0: emac-zmii@ef600d00 { +- compatible = "ibm,zmii-440epx", "ibm,zmii"; +- reg = <0xef600d00 0x0000000c>; +- }; +- +- RGMII0: emac-rgmii@ef601000 { +- compatible = "ibm,rgmii-440epx", "ibm,rgmii"; +- reg = <0xef601000 0x00000008>; +- has-mdio; +- }; +- +- EMAC0: ethernet@ef600e00 { +- device_type = "network"; +- compatible = "ibm,emac-440epx", "ibm,emac4"; +- interrupt-parent = <&EMAC0>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600e00 0x00000074>; +- local-mac-address = [000000000000]; +- mal-device = <&MAL0>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- zmii-device = <&ZMII0>; +- zmii-channel = <0>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <0>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- +- EMAC1: ethernet@ef600f00 { +- device_type = "network"; +- compatible = "ibm,emac-440epx", "ibm,emac4"; +- interrupt-parent = <&EMAC1>; +- interrupts = <0x0 0x1>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- reg = <0xef600f00 0x00000074>; +- local-mac-address = [000000000000]; +- mal-device = <&MAL0>; +- mal-tx-channel = <1>; +- mal-rx-channel = <1>; +- cell-index = <1>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "rgmii"; +- phy-map = <0x00000000>; +- zmii-device = <&ZMII0>; +- zmii-channel = <1>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <1>; +- has-inverted-stacr-oc; +- has-new-stacr-staopc; +- }; +- }; +- +- PCI0: pci@1ec000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb440epx-pci", "ibm,plb-pci"; +- primary; +- reg = <0x00000001 0xeec00000 0x00000008 /* Config space access */ +- 0x00000001 0xeed00000 0x00000004 /* IACK */ +- 0x00000001 0xeed00000 0x00000004 /* Special cycle */ +- 0x00000001 0xef400000 0x00000040>; /* Internal registers */ +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed. Chip supports a second +- * IO range but we don't use it for now +- * From the 440EPx user manual: +- * PCI 1 Memory 1 8000 0000 1 BFFF FFFF 1GB +- * I/O 1 E800 0000 1 E800 FFFF 64KB +- * I/O 1 E880 0000 1 EBFF FFFF 56MB +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x00000001 0x80000000 0x00000000 0x40000000 +- 0x01000000 0x00000000 0x00000000 0x00000001 0xe8000000 0x00000000 0x00010000 +- 0x01000000 0x00000000 0x00000000 0x00000001 0xe8800000 0x00000000 0x03800000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; +- +- /* All PCI interrupts are routed to IRQ 67 */ +- interrupt-map-mask = <0x0 0x0 0x0 0x0>; +- interrupt-map = < 0x0 0x0 0x0 0x0 &UIC2 0x3 0x8 >; +- }; +- }; +- +- chosen { +- stdout-path = "/plb/opb/serial@ef600300"; +- bootargs = "console=ttyS0,115200"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/socrates.dts b/scripts/dtc/include-prefixes/powerpc/socrates.dts +deleted file mode 100644 +index 00a56e8e367c..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/socrates.dts ++++ /dev/null +@@ -1,348 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Device Tree Source for the Socrates board (MPC8544). +- * +- * Copyright (c) 2008 Emcraft Systems. +- * Sergei Poselenov, +- */ +- +-/dts-v1/; +- +-/ { +- model = "abb,socrates"; +- compatible = "abb,socrates"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8544@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <0x8000>; // L1, 32K +- i-cache-size = <0x8000>; // L1, 32K +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000>; // Filled in by U-Boot +- }; +- +- soc8544@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- +- ranges = <0x00000000 0xe0000000 0x00100000>; +- bus-frequency = <0>; // Filled in by U-Boot +- compatible = "fsl,mpc8544-immr", "simple-bus"; +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <10>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8544-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8544-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8544-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; +- cache-size = <0x40000>; // L2, 256K +- interrupt-parent = <&mpic>; +- interrupts = <16 2>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl,mpc8544-i2c", "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- fsl,preserve-clocking; +- +- dtt@28 { +- compatible = "winbond,w83782d"; +- reg = <0x28>; +- }; +- rtc@32 { +- compatible = "epson,rx8025"; +- reg = <0x32>; +- interrupts = <7 1>; +- interrupt-parent = <&mpic>; +- }; +- dtt@4c { +- compatible = "dallas,ds75"; +- reg = <0x4c>; +- }; +- ts@4a { +- compatible = "ti,tsc2003"; +- reg = <0x4a>; +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl,mpc8544-i2c", "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- fsl,preserve-clocking; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 30 2 34 2>; +- interrupt-parent = <&mpic>; +- phy-handle = <&phy0>; +- tbi-handle = <&tbi0>; +- phy-connection-type = "rgmii-id"; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy0: ethernet-phy@0 { +- interrupt-parent = <&mpic>; +- interrupts = <0 1>; +- reg = <0>; +- }; +- phy1: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <0 1>; +- reg = <1>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- }; +- }; +- }; +- +- enet1: ethernet@26000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x26000 0x1000>; +- ranges = <0x0 0x26000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <31 2 32 2 33 2>; +- interrupt-parent = <&mpic>; +- phy-handle = <&phy1>; +- tbi-handle = <&tbi1>; +- phy-connection-type = "rgmii-id"; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- global-utilities@e0000 { //global utilities block +- compatible = "fsl,mpc8548-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +- +- mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- compatible = "chrp,open-pic"; +- device_type = "open-pic"; +- }; +- }; +- +- +- localbus { +- compatible = "fsl,mpc8544-localbus", +- "fsl,pq3-localbus", +- "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- reg = <0xe0005000 0x40>; +- interrupt-parent = <&mpic>; +- interrupts = <19 2>; +- +- ranges = <0 0 0xfc000000 0x04000000 +- 2 0 0xc8000000 0x04000000 +- 3 0 0xc0000000 0x00100000 +- >; /* Overwritten by U-Boot */ +- +- nor_flash@0,0 { +- compatible = "amd,s29gl256n", "cfi-flash"; +- bank-width = <2>; +- reg = <0x0 0x000000 0x4000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "kernel"; +- reg = <0x0 0x1e0000>; +- read-only; +- }; +- partition@1e0000 { +- label = "dtb"; +- reg = <0x1e0000 0x20000>; +- }; +- partition@200000 { +- label = "root"; +- reg = <0x200000 0x200000>; +- }; +- partition@400000 { +- label = "user"; +- reg = <0x400000 0x3b80000>; +- }; +- partition@3f80000 { +- label = "env"; +- reg = <0x3f80000 0x40000>; +- read-only; +- }; +- partition@3fc0000 { +- label = "u-boot"; +- reg = <0x3fc0000 0x40000>; +- read-only; +- }; +- }; +- +- display@2,0 { +- compatible = "fujitsu,lime"; +- reg = <2 0x0 0x4000000>; +- interrupt-parent = <&mpic>; +- interrupts = <6 1>; +- }; +- +- fpga_pic: fpga-pic@3,10 { +- compatible = "abb,socrates-fpga-pic"; +- reg = <3 0x10 0x10>; +- interrupt-controller; +- /* IRQs 2, 10, 11, active low, level-sensitive */ +- interrupts = <2 1 10 1 11 1>; +- interrupt-parent = <&mpic>; +- #interrupt-cells = <3>; +- }; +- +- spi@3,60 { +- compatible = "abb,socrates-spi"; +- reg = <3 0x60 0x10>; +- interrupts = <8 4 0>; // number, type, routing +- interrupt-parent = <&fpga_pic>; +- }; +- +- nand@3,70 { +- compatible = "abb,socrates-nand"; +- reg = <3 0x70 0x04>; +- bank-width = <1>; +- #address-cells = <1>; +- #size-cells = <1>; +- data@0 { +- label = "data"; +- reg = <0x0 0x40000000>; +- }; +- }; +- +- can@3,100 { +- compatible = "philips,sja1000"; +- reg = <3 0x100 0x80>; +- interrupts = <2 8 1>; // number, type, routing +- interrupt-parent = <&fpga_pic>; +- }; +- }; +- +- pci0: pci@e0008000 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "fsl,mpc8540-pci"; +- device_type = "pci"; +- reg = <0xe0008000 0x1000>; +- clock-frequency = <66666666>; +- +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x11 */ +- 0x8800 0x0 0x0 1 &mpic 5 1 +- /* IDSEL 0x12 */ +- 0x9000 0x0 0x0 1 &mpic 4 1>; +- interrupt-parent = <&mpic>; +- interrupts = <24 2>; +- bus-range = <0x0 0x0>; +- ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000 +- 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>; +- }; +- +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/storcenter.dts b/scripts/dtc/include-prefixes/powerpc/storcenter.dts +deleted file mode 100644 +index 99f6f544dc5f..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/storcenter.dts ++++ /dev/null +@@ -1,142 +0,0 @@ +-/* +- * Device Tree Source for IOMEGA StorCenter +- * +- * Copyright 2007 Oyvind Repvik +- * Copyright 2007 Jon Loeliger +- * +- * Based on the Kurobox DTS by G. Liakhovetski +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without any +- * warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- model = "StorCenter"; +- compatible = "iomega,storcenter"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8241@0 { +- device_type = "cpu"; +- reg = <0>; +- clock-frequency = <200000000>; +- timebase-frequency = <25000000>; +- bus-frequency = <0>; /* from bootwrapper */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <16384>; +- d-cache-size = <16384>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x04000000>; /* 64MB @ 0x0 */ +- }; +- +- soc@fc000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,mpc8241", "mpc10x"; +- store-gathering = <0>; /* 0 == off, !0 == on */ +- ranges = <0x0 0xfc000000 0x100000>; +- reg = <0xfc000000 0x100000>; /* EUMB */ +- bus-frequency = <0>; /* fixed by loader */ +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- +- rtc@68 { +- compatible = "dallas,ds1337"; +- reg = <0x68>; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x20>; +- clock-frequency = <97553800>; /* Hz */ +- current-speed = <115200>; +- interrupts = <25 2>; +- interrupt-parent = <&mpic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x20>; +- clock-frequency = <97553800>; /* Hz */ +- current-speed = <9600>; +- interrupts = <26 2>; +- interrupt-parent = <&mpic>; +- }; +- +- mpic: interrupt-controller@40000 { +- #interrupt-cells = <2>; +- #address-cells = <0>; +- device_type = "open-pic"; +- compatible = "chrp,open-pic"; +- interrupt-controller; +- reg = <0x40000 0x40000>; +- }; +- +- }; +- +- pci0: pci@fe800000 { +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- device_type = "pci"; +- compatible = "mpc10x-pci"; +- reg = <0xfe800000 0x1000>; +- ranges = <0x01000000 0x0 0x0 0xfe000000 0x0 0x00c00000 +- 0x02000000 0x0 0x80000000 0x80000000 0x0 0x70000000>; +- bus-range = <0 0xff>; +- clock-frequency = <97553800>; +- interrupt-parent = <&mpic>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = < +- /* IDSEL 13 - IDE */ +- 0x6800 0 0 1 &mpic 0 1 +- 0x6800 0 0 2 &mpic 0 1 +- 0x6800 0 0 3 &mpic 0 1 +- 0x6800 0 0 4 &mpic 0 1 +- /* IDSEL 14 - USB */ +- 0x7000 0 0 1 &mpic 0 1 +- 0x7000 0 0 2 &mpic 0 1 +- 0x7000 0 0 3 &mpic 0 1 +- 0x7000 0 0 4 &mpic 0 1 +- /* IDSEL 15 - ETH */ +- 0x7800 0 0 1 &mpic 0 1 +- 0x7800 0 0 2 &mpic 0 1 +- 0x7800 0 0 3 &mpic 0 1 +- 0x7800 0 0 4 &mpic 0 1 +- >; +- }; +- +- chosen { +- stdout-path = &serial0; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/stx_gp3_8560.dts b/scripts/dtc/include-prefixes/powerpc/stx_gp3_8560.dts +deleted file mode 100644 +index d1ab698eef36..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/stx_gp3_8560.dts ++++ /dev/null +@@ -1,300 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * STX GP3 - 8560 ADS Device Tree Source +- * +- * Copyright 2008 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/ { +- model = "stx,gp3"; +- compatible = "stx,gp3-8560", "stx,gp3"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8560@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- soc@fdf00000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- ranges = <0 0xfdf00000 0x100000>; +- bus-frequency = <0>; +- compatible = "fsl,mpc8560-immr", "simple-bus"; +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <8>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8560-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8540-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8540-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; +- cache-size = <0x40000>; // L2, 256K +- interrupt-parent = <&mpic>; +- interrupts = <16 2>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8560-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8560-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8560-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8560-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 30 2 34 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy2>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy2: ethernet-phy@2 { +- interrupt-parent = <&mpic>; +- interrupts = <5 4>; +- reg = <2>; +- }; +- phy4: ethernet-phy@4 { +- interrupt-parent = <&mpic>; +- interrupts = <5 4>; +- reg = <4>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 2 36 2 40 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy4>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- compatible = "chrp,open-pic"; +- device_type = "open-pic"; +- }; +- +- cpm@919c0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus"; +- reg = <0x919c0 0x30>; +- ranges; +- +- muram@80000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x80000 0x10000>; +- +- data@0 { +- compatible = "fsl,cpm-muram-data"; +- reg = <0 0x4000 0x9000 0x2000>; +- }; +- }; +- +- brg@919f0 { +- compatible = "fsl,mpc8560-brg", +- "fsl,cpm2-brg", +- "fsl,cpm-brg"; +- reg = <0x919f0 0x10 0x915f0 0x10>; +- clock-frequency = <0>; +- }; +- +- cpmpic: pic@90c00 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <46 2>; +- interrupt-parent = <&mpic>; +- reg = <0x90c00 0x80>; +- compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic"; +- }; +- +- serial0: serial@91a20 { +- device_type = "serial"; +- compatible = "fsl,mpc8560-scc-uart", +- "fsl,cpm2-scc-uart"; +- reg = <0x91a20 0x20 0x88100 0x100>; +- fsl,cpm-brg = <2>; +- fsl,cpm-command = <0x4a00000>; +- interrupts = <41 8>; +- interrupt-parent = <&cpmpic>; +- }; +- }; +- }; +- +- pci0: pci@fdf08000 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x0c */ +- 0x6000 0 0 1 &mpic 1 1 +- 0x6000 0 0 2 &mpic 2 1 +- 0x6000 0 0 3 &mpic 3 1 +- 0x6000 0 0 4 &mpic 4 1 +- +- /* IDSEL 0x0d */ +- 0x6800 0 0 1 &mpic 4 1 +- 0x6800 0 0 2 &mpic 1 1 +- 0x6800 0 0 3 &mpic 2 1 +- 0x6800 0 0 4 &mpic 3 1 +- +- /* IDSEL 0x0e */ +- 0x7000 0 0 1 &mpic 3 1 +- 0x7000 0 0 2 &mpic 4 1 +- 0x7000 0 0 3 &mpic 1 1 +- 0x7000 0 0 4 &mpic 2 1 +- +- /* IDSEL 0x0f */ +- 0x7800 0 0 1 &mpic 2 1 +- 0x7800 0 0 2 &mpic 3 1 +- 0x7800 0 0 3 &mpic 4 1 +- 0x7800 0 0 4 &mpic 1 1>; +- +- interrupt-parent = <&mpic>; +- interrupts = <24 2>; +- bus-range = <0 0>; +- ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xfdf08000 0x1000>; +- compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; +- device_type = "pci"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/stxssa8555.dts b/scripts/dtc/include-prefixes/powerpc/stxssa8555.dts +deleted file mode 100644 +index 5dca2a91c41f..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/stxssa8555.dts ++++ /dev/null +@@ -1,374 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * MPC8555-based STx GP3 Device Tree Source +- * +- * Copyright 2006, 2008 Freescale Semiconductor Inc. +- * +- * Copyright 2010 Silicon Turnkey Express LLC. +- */ +- +-/dts-v1/; +- +-/ { +- model = "stx,gp3"; +- compatible = "stx,gp3-8560", "stx,gp3"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8555@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <0x8000>; // L1, 32K +- i-cache-size = <0x8000>; // L1, 32K +- timebase-frequency = <0>; // 33 MHz, from uboot +- bus-frequency = <0>; // 166 MHz +- clock-frequency = <0>; // 825 MHz, from uboot +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- soc8555@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "simple-bus"; +- ranges = <0x0 0xe0000000 0x100000>; +- bus-frequency = <0>; +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <8>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8555-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8555-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8555-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x40000>; // L2, 256K +- interrupt-parent = <&mpic>; +- interrupts = <16 2>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8555-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8555-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8555-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8555-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 30 2 34 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy0: ethernet-phy@2 { +- interrupt-parent = <&mpic>; +- interrupts = <5 1>; +- reg = <0x2>; +- }; +- phy1: ethernet-phy@4 { +- interrupt-parent = <&mpic>; +- interrupts = <5 1>; +- reg = <0x4>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 2 36 2 40 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; // reg base, size +- clock-frequency = <0>; // should we fill in in uboot? +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; // reg base, size +- clock-frequency = <0>; // should we fill in in uboot? +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <45 2>; +- interrupt-parent = <&mpic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x7e>; +- fsl,descriptor-types-mask = <0x01010ebf>; +- }; +- +- mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- compatible = "chrp,open-pic"; +- device_type = "open-pic"; +- }; +- +- cpm@919c0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8555-cpm", "fsl,cpm2"; +- reg = <0x919c0 0x30>; +- ranges; +- +- muram@80000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x80000 0x10000>; +- +- data@0 { +- compatible = "fsl,cpm-muram-data"; +- reg = <0x0 0x2000 0x9000 0x1000>; +- }; +- }; +- +- brg@919f0 { +- compatible = "fsl,mpc8555-brg", +- "fsl,cpm2-brg", +- "fsl,cpm-brg"; +- reg = <0x919f0 0x10 0x915f0 0x10>; +- }; +- +- cpmpic: pic@90c00 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <46 2>; +- interrupt-parent = <&mpic>; +- reg = <0x90c00 0x80>; +- compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic"; +- }; +- }; +- }; +- +- pci0: pci@e0008000 { +- interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x10 */ +- 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1 +- 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1 +- +- /* IDSEL 0x11 */ +- 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1 +- 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1 +- +- /* IDSEL 0x12 (Slot 1) */ +- 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1 +- 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1 +- +- /* IDSEL 0x13 (Slot 2) */ +- 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1 +- 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1 +- 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1 +- 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1 +- +- /* IDSEL 0x14 (Slot 3) */ +- 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1 +- 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1 +- 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1 +- 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1 +- +- /* IDSEL 0x15 (Slot 4) */ +- 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1 +- 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1 +- 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1 +- 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1 +- +- /* Bus 1 (Tundra Bridge) */ +- /* IDSEL 0x12 (ISA bridge) */ +- 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1 +- 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>; +- interrupt-parent = <&mpic>; +- interrupts = <24 2>; +- bus-range = <0 0>; +- ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 +- 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0008000 0x1000>; +- compatible = "fsl,mpc8540-pci"; +- device_type = "pci"; +- +- i8259@19000 { +- interrupt-controller; +- device_type = "interrupt-controller"; +- reg = <0x19000 0x0 0x0 0x0 0x1>; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- compatible = "chrp,iic"; +- interrupts = <1>; +- interrupt-parent = <&pci0>; +- }; +- }; +- +- pci1: pci@e0009000 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- +- /* IDSEL 0x15 */ +- 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 +- 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1 +- 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1 +- 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>; +- interrupt-parent = <&mpic>; +- interrupts = <25 2>; +- bus-range = <0 0>; +- ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 +- 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>; +- clock-frequency = <66666666>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe0009000 0x1000>; +- compatible = "fsl,mpc8540-pci"; +- device_type = "pci"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/taishan.dts b/scripts/dtc/include-prefixes/powerpc/taishan.dts +deleted file mode 100644 +index 803f1bff7fa8..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/taishan.dts ++++ /dev/null +@@ -1,427 +0,0 @@ +-/* +- * Device Tree Source for IBM/AMCC Taishan +- * +- * Copyright 2007 IBM Corp. +- * Hugh Blemings based off code by +- * Josh Boyer , David Gibson +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <2>; +- #size-cells = <1>; +- model = "amcc,taishan"; +- compatible = "amcc,taishan"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC2; +- ethernet1 = &EMAC3; +- serial0 = &UART0; +- serial1 = &UART1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,440GX"; +- reg = <0x00000000>; +- clock-frequency = <800000000>; // 800MHz +- timebase-frequency = <0>; // Filled in by zImage +- i-cache-line-size = <50>; +- d-cache-line-size = <50>; +- i-cache-size = <32768>; /* 32 kB */ +- d-cache-size = <32768>; /* 32 kB */ +- dcr-controller; +- dcr-access-method = "native"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage +- }; +- +- +- UICB0: interrupt-controller-base { +- compatible = "ibm,uic-440gx", "ibm,uic"; +- interrupt-controller; +- cell-index = <3>; +- dcr-reg = <0x200 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- +- UIC0: interrupt-controller0 { +- compatible = "ibm,uic-440gx", "ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1 0x4 0x0 0x4>; /* cascade - first non-critical */ +- interrupt-parent = <&UICB0>; +- +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-440gx", "ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x3 0x4 0x2 0x4>; /* cascade */ +- interrupt-parent = <&UICB0>; +- }; +- +- UIC2: interrupt-controller2 { +- compatible = "ibm,uic-440gx", "ibm,uic"; +- interrupt-controller; +- cell-index = <2>; /* was 1 */ +- dcr-reg = <0x210 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x5 0x4 0x4 0x4>; /* cascade */ +- interrupt-parent = <&UICB0>; +- }; +- +- +- CPC0: cpc { +- compatible = "ibm,cpc-440gp"; +- dcr-reg = <0x0b0 0x003 0x0e0 0x010>; +- // FIXME: anything else? +- }; +- +- L2C0: l2c { +- compatible = "ibm,l2-cache-440gx", "ibm,l2-cache"; +- dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ +- 0x030 0x008>; /* L2 cache DCR's */ +- cache-line-size = <32>; /* 32 bytes */ +- cache-size = <262144>; /* L2, 256K */ +- interrupt-parent = <&UIC2>; +- interrupts = <0x17 0x1>; +- }; +- +- plb { +- compatible = "ibm,plb-440gx", "ibm,plb4"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <160000000>; // 160MHz +- +- SDRAM0: memory-controller { +- compatible = "ibm,sdram-440gp"; +- dcr-reg = <0x010 0x002>; +- // FIXME: anything else? +- }; +- +- SRAM0: sram { +- compatible = "ibm,sram-440gp"; +- dcr-reg = <0x020 0x008 0x00a 0x001>; +- }; +- +- DMA0: dma { +- // FIXME: ??? +- compatible = "ibm,dma-440gp"; +- dcr-reg = <0x100 0x027>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-440gx", "ibm,mcmal2"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <4>; +- num-rx-chans = <4>; +- interrupt-parent = <&MAL0>; +- interrupts = <0x0 0x1 0x2 0x3 0x4>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- interrupt-map-mask = <0xffffffff>; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-440gx", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- /* Wish there was a nicer way of specifying a full 32-bit +- range */ +- ranges = <0x00000000 0x00000001 0x00000000 0x80000000 +- 0x80000000 0x00000001 0x80000000 0x80000000>; +- dcr-reg = <0x090 0x00b>; +- interrupt-parent = <&UIC1>; +- interrupts = <0x7 0x4>; +- clock-frequency = <80000000>; // 80MHz +- +- +- EBC0: ebc { +- compatible = "ibm,ebc-440gx", "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <80000000>; // 80MHz +- +- /* ranges property is supplied by zImage +- * based on firmware's configuration of the +- * EBC bridge */ +- +- interrupts = <0x5 0x4>; +- interrupt-parent = <&UIC1>; +- +- nor_flash@0,0 { +- compatible = "cfi-flash"; +- bank-width = <4>; +- device-width = <2>; +- reg = <0x0 0x0 0x4000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "kernel"; +- reg = <0x0 0x180000>; +- }; +- partition@180000 { +- label = "root"; +- reg = <0x180000 0x200000>; +- }; +- partition@380000 { +- label = "user"; +- reg = <0x380000 0x3bc0000>; +- }; +- partition@3f40000 { +- label = "env"; +- reg = <0x3f40000 0x80000>; +- }; +- partition@3fc0000 { +- label = "u-boot"; +- reg = <0x3fc0000 0x40000>; +- }; +- }; +- }; +- +- +- +- UART0: serial@40000200 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0x40000200 0x00000008>; +- virtual-reg = <0xe0000200>; +- clock-frequency = <11059200>; +- current-speed = <115200>; /* 115200 */ +- interrupt-parent = <&UIC0>; +- interrupts = <0x0 0x4>; +- }; +- +- UART1: serial@40000300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0x40000300 0x00000008>; +- virtual-reg = <0xe0000300>; +- clock-frequency = <11059200>; +- current-speed = <115200>; /* 115200 */ +- interrupt-parent = <&UIC0>; +- interrupts = <0x1 0x4>; +- }; +- +- IIC0: i2c@40000400 { +- /* FIXME */ +- compatible = "ibm,iic-440gp", "ibm,iic"; +- reg = <0x40000400 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x2 0x4>; +- }; +- IIC1: i2c@40000500 { +- /* FIXME */ +- compatible = "ibm,iic-440gp", "ibm,iic"; +- reg = <0x40000500 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x3 0x4>; +- }; +- +- GPIO0: gpio@40000700 { +- /* FIXME */ +- compatible = "ibm,gpio-440gp"; +- reg = <0x40000700 0x00000020>; +- }; +- +- ZMII0: emac-zmii@40000780 { +- compatible = "ibm,zmii-440gx", "ibm,zmii"; +- reg = <0x40000780 0x0000000c>; +- }; +- +- RGMII0: emac-rgmii@40000790 { +- compatible = "ibm,rgmii"; +- reg = <0x40000790 0x00000008>; +- }; +- +- TAH0: emac-tah@40000b50 { +- compatible = "ibm,tah-440gx", "ibm,tah"; +- reg = <0x40000b50 0x00000030>; +- }; +- +- TAH1: emac-tah@40000d50 { +- compatible = "ibm,tah-440gx", "ibm,tah"; +- reg = <0x40000d50 0x00000030>; +- }; +- +- EMAC0: ethernet@40000800 { +- unused = <0x1>; +- device_type = "network"; +- compatible = "ibm,emac-440gx", "ibm,emac4"; +- interrupt-parent = <&UIC1>; +- interrupts = <0x1c 0x4 0x1d 0x4>; +- reg = <0x40000800 0x00000074>; +- local-mac-address = [000000000000]; // Filled in by zImage +- mal-device = <&MAL0>; +- mal-tx-channel = <0>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <1500>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "rmii"; +- phy-map = <0x00000001>; +- zmii-device = <&ZMII0>; +- zmii-channel = <0>; +- }; +- EMAC1: ethernet@40000900 { +- unused = <0x1>; +- device_type = "network"; +- compatible = "ibm,emac-440gx", "ibm,emac4"; +- interrupt-parent = <&UIC1>; +- interrupts = <0x1e 0x4 0x1f 0x4>; +- reg = <0x40000900 0x00000074>; +- local-mac-address = [000000000000]; // Filled in by zImage +- mal-device = <&MAL0>; +- mal-tx-channel = <1>; +- mal-rx-channel = <1>; +- cell-index = <1>; +- max-frame-size = <1500>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "rmii"; +- phy-map = <0x00000001>; +- zmii-device = <&ZMII0>; +- zmii-channel = <1>; +- }; +- +- EMAC2: ethernet@40000c00 { +- device_type = "network"; +- compatible = "ibm,emac-440gx", "ibm,emac4"; +- interrupt-parent = <&UIC2>; +- interrupts = <0x0 0x4 0x1 0x4>; +- reg = <0x40000c00 0x00000074>; +- local-mac-address = [000000000000]; // Filled in by zImage +- mal-device = <&MAL0>; +- mal-tx-channel = <2>; +- mal-rx-channel = <2>; +- cell-index = <2>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "rgmii"; +- phy-address = <1>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <0>; +- zmii-device = <&ZMII0>; +- zmii-channel = <2>; +- tah-device = <&TAH0>; +- tah-channel = <0>; +- }; +- +- EMAC3: ethernet@40000e00 { +- device_type = "network"; +- compatible = "ibm,emac-440gx", "ibm,emac4"; +- interrupt-parent = <&UIC2>; +- interrupts = <0x2 0x4 0x3 0x4>; +- reg = <0x40000e00 0x00000074>; +- local-mac-address = [000000000000]; // Filled in by zImage +- mal-device = <&MAL0>; +- mal-tx-channel = <3>; +- mal-rx-channel = <3>; +- cell-index = <3>; +- max-frame-size = <9000>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "rgmii"; +- phy-address = <3>; +- rgmii-device = <&RGMII0>; +- rgmii-channel = <1>; +- zmii-device = <&ZMII0>; +- zmii-channel = <3>; +- tah-device = <&TAH1>; +- tah-channel = <0>; +- }; +- +- +- GPT0: gpt@40000a00 { +- /* FIXME */ +- reg = <0x40000a00 0x000000d4>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>; +- }; +- +- }; +- +- PCIX0: pci@20ec00000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix"; +- primary; +- large-inbound-windows; +- enable-msi-hole; +- reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */ +- 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ +- 0x00000002 0x0ed00000 0x00000004 /* Special cycles */ +- 0x00000002 0x0ec80000 0x00000100 /* Internal registers */ +- 0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */ +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed +- */ +- ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000 +- 0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; +- +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 1 */ +- 0x800 0x0 0x0 0x1 &UIC0 0x17 0x8 +- 0x800 0x0 0x0 0x2 &UIC0 0x18 0x8 +- 0x800 0x0 0x0 0x3 &UIC0 0x19 0x8 +- 0x800 0x0 0x0 0x4 &UIC0 0x1a 0x8 +- +- /* IDSEL 2 */ +- 0x1000 0x0 0x0 0x1 &UIC0 0x18 0x8 +- 0x1000 0x0 0x0 0x2 &UIC0 0x19 0x8 +- 0x1000 0x0 0x0 0x3 &UIC0 0x1a 0x8 +- 0x1000 0x0 0x0 0x4 &UIC0 0x17 0x8 +- >; +- }; +- }; +- +- chosen { +- stdout-path = "/plb/opb/serial@40000300"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/tqm5200.dts b/scripts/dtc/include-prefixes/powerpc/tqm5200.dts +deleted file mode 100644 +index 5bb25a9e40a0..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/tqm5200.dts ++++ /dev/null +@@ -1,207 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * TQM5200 board Device Tree Source +- * +- * Copyright (C) 2007 Semihalf +- * Marian Balakowicz +- */ +- +-/dts-v1/; +- +-/ { +- model = "tqc,tqm5200"; +- compatible = "tqc,tqm5200"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&mpc5200_pic>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,5200@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <0x4000>; // L1, 16K +- i-cache-size = <0x4000>; // L1, 16K +- timebase-frequency = <0>; // from bootloader +- bus-frequency = <0>; // from bootloader +- clock-frequency = <0>; // from bootloader +- }; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x04000000>; // 64MB +- }; +- +- soc5200@f0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc5200-immr"; +- ranges = <0 0xf0000000 0x0000c000>; +- reg = <0xf0000000 0x00000100>; +- bus-frequency = <0>; // from bootloader +- system-frequency = <0>; // from bootloader +- +- cdm@200 { +- compatible = "fsl,mpc5200-cdm"; +- reg = <0x200 0x38>; +- }; +- +- mpc5200_pic: interrupt-controller@500 { +- // 5200 interrupts are encoded into two levels; +- interrupt-controller; +- #interrupt-cells = <3>; +- compatible = "fsl,mpc5200-pic"; +- reg = <0x500 0x80>; +- }; +- +- timer@600 { // General Purpose Timer +- compatible = "fsl,mpc5200-gpt"; +- reg = <0x600 0x10>; +- interrupts = <1 9 0>; +- fsl,has-wdt; +- }; +- +- can@900 { +- compatible = "fsl,mpc5200-mscan"; +- interrupts = <2 17 0>; +- reg = <0x900 0x80>; +- }; +- +- can@980 { +- compatible = "fsl,mpc5200-mscan"; +- interrupts = <2 18 0>; +- reg = <0x980 0x80>; +- }; +- +- gpio_simple: gpio@b00 { +- compatible = "fsl,mpc5200-gpio"; +- reg = <0xb00 0x40>; +- interrupts = <1 7 0>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- usb@1000 { +- compatible = "fsl,mpc5200-ohci","ohci-be"; +- reg = <0x1000 0xff>; +- interrupts = <2 6 0>; +- }; +- +- dma-controller@1200 { +- compatible = "fsl,mpc5200-bestcomm"; +- reg = <0x1200 0x80>; +- interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 +- 3 4 0 3 5 0 3 6 0 3 7 0 +- 3 8 0 3 9 0 3 10 0 3 11 0 +- 3 12 0 3 13 0 3 14 0 3 15 0>; +- }; +- +- xlb@1f00 { +- compatible = "fsl,mpc5200-xlb"; +- reg = <0x1f00 0x100>; +- }; +- +- serial@2000 { // PSC1 +- compatible = "fsl,mpc5200-psc-uart"; +- reg = <0x2000 0x100>; +- interrupts = <2 1 0>; +- }; +- +- serial@2200 { // PSC2 +- compatible = "fsl,mpc5200-psc-uart"; +- reg = <0x2200 0x100>; +- interrupts = <2 2 0>; +- }; +- +- serial@2400 { // PSC3 +- compatible = "fsl,mpc5200-psc-uart"; +- reg = <0x2400 0x100>; +- interrupts = <2 3 0>; +- }; +- +- ethernet@3000 { +- compatible = "fsl,mpc5200-fec"; +- reg = <0x3000 0x400>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <2 5 0>; +- phy-handle = <&phy0>; +- }; +- +- mdio@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc5200-mdio"; +- reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts +- interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +- +- ata@3a00 { +- compatible = "fsl,mpc5200-ata"; +- reg = <0x3a00 0x100>; +- interrupts = <2 7 0>; +- }; +- +- i2c@3d40 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,mpc5200-i2c","fsl-i2c"; +- reg = <0x3d40 0x40>; +- interrupts = <2 16 0>; +- +- rtc@68 { +- compatible = "dallas,ds1307"; +- reg = <0x68>; +- }; +- }; +- +- sram@8000 { +- compatible = "fsl,mpc5200-sram"; +- reg = <0x8000 0x4000>; +- }; +- }; +- +- localbus { +- compatible = "fsl,mpc5200-lpb","simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges = <0 0 0xfc000000 0x02000000>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x02000000>; +- bank-width = <4>; +- device-width = <2>; +- #size-cells = <1>; +- #address-cells = <1>; +- }; +- }; +- +- pci@f0000d00 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- compatible = "fsl,mpc5200-pci"; +- reg = <0xf0000d00 0x100>; +- interrupt-map-mask = <0xf800 0 0 7>; +- interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 +- 0xc000 0 0 2 &mpc5200_pic 0 0 3 +- 0xc000 0 0 3 &mpc5200_pic 0 0 3 +- 0xc000 0 0 4 &mpc5200_pic 0 0 3>; +- clock-frequency = <0>; // From boot loader +- interrupts = <2 8 0 2 9 0 2 10 0>; +- bus-range = <0 0>; +- ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000 +- 0x02000000 0 0x90000000 0x90000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/tqm8540.dts b/scripts/dtc/include-prefixes/powerpc/tqm8540.dts +deleted file mode 100644 +index 9c1eb9779108..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/tqm8540.dts ++++ /dev/null +@@ -1,342 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * TQM 8540 Device Tree Source +- * +- * Copyright 2008 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/ { +- model = "tqc,tqm8540"; +- compatible = "tqc,tqm8540"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8540@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- soc@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- ranges = <0x0 0xe0000000 0x100000>; +- bus-frequency = <0>; +- compatible = "fsl,mpc8540-immr", "simple-bus"; +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <8>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8540-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8540-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8540-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; +- cache-size = <0x40000>; // L2, 256K +- interrupt-parent = <&mpic>; +- interrupts = <16 2>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- +- dtt@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1337"; +- reg = <0x68>; +- }; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8540-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8540-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8540-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8540-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 30 2 34 2>; +- interrupt-parent = <&mpic>; +- phy-handle = <&phy2>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy1: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <1>; +- }; +- phy2: ethernet-phy@2 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <2>; +- }; +- phy3: ethernet-phy@3 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <3>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 2 36 2 40 2>; +- interrupt-parent = <&mpic>; +- phy-handle = <&phy1>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet2: ethernet@26000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <2>; +- device_type = "network"; +- model = "FEC"; +- compatible = "gianfar"; +- reg = <0x26000 0x1000>; +- ranges = <0x0 0x26000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <41 2>; +- interrupt-parent = <&mpic>; +- phy-handle = <&phy3>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; // reg base, size +- clock-frequency = <0>; // should we fill in in uboot? +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; // reg base, size +- clock-frequency = <0>; // should we fill in in uboot? +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- device_type = "open-pic"; +- compatible = "chrp,open-pic"; +- }; +- }; +- +- localbus@e0005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8540-localbus", "fsl,pq3-localbus", +- "simple-bus"; +- reg = <0xe0005000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <19 2>; +- +- ranges = <0x0 0x0 0xfe000000 0x02000000>; +- +- nor@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x0 0x0 0x02000000>; +- bank-width = <4>; +- device-width = <2>; +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x00180000>; +- }; +- partition@180000 { +- label = "root"; +- reg = <0x00180000 0x01dc0000>; +- }; +- partition@1f40000 { +- label = "env1"; +- reg = <0x01f40000 0x00040000>; +- }; +- partition@1f80000 { +- label = "env2"; +- reg = <0x01f80000 0x00040000>; +- }; +- partition@1fc0000 { +- label = "u-boot"; +- reg = <0x01fc0000 0x00040000>; +- read-only; +- }; +- }; +- }; +- +- pci0: pci@e0008000 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; +- device_type = "pci"; +- reg = <0xe0008000 0x1000>; +- clock-frequency = <66666666>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 28 */ +- 0xe000 0 0 1 &mpic 2 1 +- 0xe000 0 0 2 &mpic 3 1 +- 0xe000 0 0 3 &mpic 6 1 +- 0xe000 0 0 4 &mpic 5 1 +- +- /* IDSEL 11 */ +- 0x5800 0 0 1 &mpic 6 1 +- 0x5800 0 0 2 &mpic 5 1 +- >; +- +- interrupt-parent = <&mpic>; +- interrupts = <24 2>; +- bus-range = <0 0>; +- ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/tqm8541.dts b/scripts/dtc/include-prefixes/powerpc/tqm8541.dts +deleted file mode 100644 +index 44595cf675d0..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/tqm8541.dts ++++ /dev/null +@@ -1,322 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * TQM 8541 Device Tree Source +- * +- * Copyright 2008 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/ { +- model = "tqc,tqm8541"; +- compatible = "tqc,tqm8541"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8541@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- soc@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- ranges = <0x0 0xe0000000 0x100000>; +- bus-frequency = <0>; +- compatible = "fsl,mpc8541-immr", "simple-bus"; +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <8>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8541-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8540-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8540-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; +- cache-size = <0x40000>; // L2, 256K +- interrupt-parent = <&mpic>; +- interrupts = <16 2>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- +- dtt@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1337"; +- reg = <0x68>; +- }; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8541-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8541-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8541-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8541-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 30 2 34 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy2>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy1: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <1>; +- }; +- phy2: ethernet-phy@2 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <2>; +- }; +- phy3: ethernet-phy@3 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <3>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 2 36 2 40 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; // reg base, size +- clock-frequency = <0>; // should we fill in in uboot? +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; // reg base, size +- clock-frequency = <0>; // should we fill in in uboot? +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <45 2>; +- interrupt-parent = <&mpic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x7e>; +- fsl,descriptor-types-mask = <0x01010ebf>; +- }; +- +- mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- device_type = "open-pic"; +- compatible = "chrp,open-pic"; +- }; +- +- cpm@919c0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8541-cpm", "fsl,cpm2", "simple-bus"; +- reg = <0x919c0 0x30>; +- ranges; +- +- muram@80000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x80000 0x10000>; +- +- data@0 { +- compatible = "fsl,cpm-muram-data"; +- reg = <0 0x2000 0x9000 0x1000>; +- }; +- }; +- +- brg@919f0 { +- compatible = "fsl,mpc8541-brg", +- "fsl,cpm2-brg", +- "fsl,cpm-brg"; +- reg = <0x919f0 0x10 0x915f0 0x10>; +- clock-frequency = <0>; +- }; +- +- cpmpic: pic@90c00 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <46 2>; +- interrupt-parent = <&mpic>; +- reg = <0x90c00 0x80>; +- compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; +- }; +- }; +- }; +- +- pci0: pci@e0008000 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; +- device_type = "pci"; +- reg = <0xe0008000 0x1000>; +- clock-frequency = <66666666>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 28 */ +- 0xe000 0 0 1 &mpic 2 1 +- 0xe000 0 0 2 &mpic 3 1 +- 0xe000 0 0 3 &mpic 6 1 +- 0xe000 0 0 4 &mpic 5 1 +- +- /* IDSEL 11 */ +- 0x5800 0 0 1 &mpic 6 1 +- 0x5800 0 0 2 &mpic 5 1 +- >; +- +- interrupt-parent = <&mpic>; +- interrupts = <24 2>; +- bus-range = <0 0>; +- ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/tqm8548-bigflash.dts b/scripts/dtc/include-prefixes/powerpc/tqm8548-bigflash.dts +deleted file mode 100644 +index caa36c5ef115..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/tqm8548-bigflash.dts ++++ /dev/null +@@ -1,495 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * TQM8548 Device Tree Source +- * +- * Copyright 2006 Freescale Semiconductor Inc. +- * Copyright 2008 Wolfgang Grandegger +- */ +- +-/dts-v1/; +- +-/ { +- model = "tqc,tqm8548"; +- compatible = "tqc,tqm8548"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- pci1 = &pci1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8548@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <0x8000>; // L1, 32K +- i-cache-size = <0x8000>; // L1, 32K +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000>; // Filled in by U-Boot +- }; +- +- soc@a0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- ranges = <0x0 0xa0000000 0x100000>; +- bus-frequency = <0>; +- compatible = "fsl,mpc8548-immr", "simple-bus"; +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <10>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8548-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8548-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8548-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x80000>; // L2, 512K +- interrupt-parent = <&mpic>; +- interrupts = <16 2>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- +- dtt@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1337"; +- reg = <0x68>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8548-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8548-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8548-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8548-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 30 2 34 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy2>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy1: ethernet-phy@0 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <1>; +- }; +- phy2: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <2>; +- }; +- phy3: ethernet-phy@3 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <3>; +- }; +- phy4: ethernet-phy@4 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <4>; +- }; +- phy5: ethernet-phy@5 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <5>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 2 36 2 40 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet2: ethernet@26000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <2>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x26000 0x1000>; +- ranges = <0x0 0x26000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <31 2 32 2 33 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi2>; +- phy-handle = <&phy4>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet3: ethernet@27000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <3>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x27000 0x1000>; +- ranges = <0x0 0x27000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <37 2 38 2 39 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi3>; +- phy-handle = <&phy5>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi3: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; // reg base, size +- clock-frequency = <0>; // should we fill in in uboot? +- current-speed = <115200>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; // reg base, size +- clock-frequency = <0>; // should we fill in in uboot? +- current-speed = <115200>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- global-utilities@e0000 { // global utilities reg +- compatible = "fsl,mpc8548-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +- +- mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- compatible = "chrp,open-pic"; +- device_type = "open-pic"; +- }; +- }; +- +- localbus@a0005000 { +- compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", +- "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- reg = <0xa0005000 0x100>; // BRx, ORx, etc. +- interrupt-parent = <&mpic>; +- interrupts = <19 2>; +- +- ranges = < +- 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 +- 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 +- 2 0x0 0xa3000000 0x00008000 // CAN (2 x CC770) +- 3 0x0 0xa3010000 0x00008000 // NAND FLASH +- +- >; +- +- flash@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <1 0x0 0x8000000>; +- bank-width = <4>; +- device-width = <1>; +- +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x00200000>; +- }; +- partition@200000 { +- label = "root"; +- reg = <0x00200000 0x00300000>; +- }; +- partition@500000 { +- label = "user"; +- reg = <0x00500000 0x07a00000>; +- }; +- partition@7f00000 { +- label = "env1"; +- reg = <0x07f00000 0x00040000>; +- }; +- partition@7f40000 { +- label = "env2"; +- reg = <0x07f40000 0x00040000>; +- }; +- partition@7f80000 { +- label = "u-boot"; +- reg = <0x07f80000 0x00080000>; +- read-only; +- }; +- }; +- +- /* Note: CAN support needs be enabled in U-Boot */ +- can@2,0 { +- compatible = "bosch,cc770"; // Bosch CC770 +- reg = <2 0x0 0x100>; +- interrupts = <4 1>; +- interrupt-parent = <&mpic>; +- bosch,external-clock-frequency = <16000000>; +- bosch,disconnect-rx1-input; +- bosch,disconnect-tx1-output; +- bosch,iso-low-speed-mux; +- bosch,clock-out-frequency = <16000000>; +- }; +- +- can@2,100 { +- compatible = "bosch,cc770"; // Bosch CC770 +- reg = <2 0x100 0x100>; +- interrupts = <4 1>; +- interrupt-parent = <&mpic>; +- bosch,external-clock-frequency = <16000000>; +- bosch,disconnect-rx1-input; +- bosch,disconnect-tx1-output; +- bosch,iso-low-speed-mux; +- }; +- +- /* Note: NAND support needs to be enabled in U-Boot */ +- upm@3,0 { +- #address-cells = <0>; +- #size-cells = <0>; +- compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand"; +- reg = <3 0x0 0x800>; +- fsl,upm-addr-offset = <0x10>; +- fsl,upm-cmd-offset = <0x08>; +- /* Micron MT29F8G08FAB multi-chip device */ +- fsl,upm-addr-line-cs-offsets = <0x0 0x200>; +- fsl,upm-wait-flags = <0x5>; +- chip-delay = <25>; // in micro-seconds +- +- nand@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "fs"; +- reg = <0x00000000 0x10000000>; +- }; +- }; +- }; +- }; +- +- pci0: pci@a0008000 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; +- device_type = "pci"; +- reg = <0xa0008000 0x1000>; +- clock-frequency = <33333333>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 28 */ +- 0xe000 0 0 1 &mpic 2 1 +- 0xe000 0 0 2 &mpic 3 1 +- 0xe000 0 0 3 &mpic 6 1 +- 0xe000 0 0 4 &mpic 5 1 +- +- /* IDSEL 11 */ +- 0x5800 0 0 1 &mpic 6 1 +- 0x5800 0 0 2 &mpic 5 1 +- >; +- +- interrupt-parent = <&mpic>; +- interrupts = <24 2>; +- bus-range = <0 0>; +- ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xa2000000 0 0x01000000>; +- }; +- +- pci1: pcie@a000a000 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x0 (PEX) */ +- 0x00000 0 0 1 &mpic 0 1 +- 0x00000 0 0 2 &mpic 1 1 +- 0x00000 0 0 3 &mpic 2 1 +- 0x00000 0 0 4 &mpic 3 1>; +- +- interrupt-parent = <&mpic>; +- interrupts = <26 2>; +- bus-range = <0 0xff>; +- ranges = <0x02000000 0 0xb0000000 0xb0000000 0 0x10000000 +- 0x01000000 0 0x00000000 0xaf000000 0 0x08000000>; +- clock-frequency = <33333333>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xa000a000 0x1000>; +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- ranges = <0x02000000 0 0xb0000000 0x02000000 0 +- 0xb0000000 0 0x10000000 +- 0x01000000 0 0x00000000 0x01000000 0 +- 0x00000000 0 0x08000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/tqm8548.dts b/scripts/dtc/include-prefixes/powerpc/tqm8548.dts +deleted file mode 100644 +index 12a64410f349..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/tqm8548.dts ++++ /dev/null +@@ -1,495 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * TQM8548 Device Tree Source +- * +- * Copyright 2006 Freescale Semiconductor Inc. +- * Copyright 2008 Wolfgang Grandegger +- */ +- +-/dts-v1/; +- +-/ { +- model = "tqc,tqm8548"; +- compatible = "tqc,tqm8548"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- pci1 = &pci1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8548@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <0x8000>; // L1, 32K +- i-cache-size = <0x8000>; // L1, 32K +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000>; // Filled in by U-Boot +- }; +- +- soc@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- ranges = <0x0 0xe0000000 0x100000>; +- bus-frequency = <0>; +- compatible = "fsl,mpc8548-immr", "simple-bus"; +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <10>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8548-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8548-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8548-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x80000>; // L2, 512K +- interrupt-parent = <&mpic>; +- interrupts = <16 2>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- +- dtt@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1337"; +- reg = <0x68>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8548-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8548-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8548-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8548-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 30 2 34 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy2>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy1: ethernet-phy@0 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <1>; +- }; +- phy2: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <2>; +- }; +- phy3: ethernet-phy@3 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <3>; +- }; +- phy4: ethernet-phy@4 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <4>; +- }; +- phy5: ethernet-phy@5 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <5>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 2 36 2 40 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet2: ethernet@26000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <2>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x26000 0x1000>; +- ranges = <0x0 0x26000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <31 2 32 2 33 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi2>; +- phy-handle = <&phy4>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet3: ethernet@27000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <3>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x27000 0x1000>; +- ranges = <0x0 0x27000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <37 2 38 2 39 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi3>; +- phy-handle = <&phy5>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi3: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; // reg base, size +- clock-frequency = <0>; // should we fill in in uboot? +- current-speed = <115200>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; // reg base, size +- clock-frequency = <0>; // should we fill in in uboot? +- current-speed = <115200>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- global-utilities@e0000 { // global utilities reg +- compatible = "fsl,mpc8548-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +- +- mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- compatible = "chrp,open-pic"; +- device_type = "open-pic"; +- }; +- }; +- +- localbus@e0005000 { +- compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", +- "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- reg = <0xe0005000 0x100>; // BRx, ORx, etc. +- interrupt-parent = <&mpic>; +- interrupts = <19 2>; +- +- ranges = < +- 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 +- 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 +- 2 0x0 0xe3000000 0x00008000 // CAN (2 x CC770) +- 3 0x0 0xe3010000 0x00008000 // NAND FLASH +- +- >; +- +- flash@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <1 0x0 0x8000000>; +- bank-width = <4>; +- device-width = <1>; +- +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x00200000>; +- }; +- partition@200000 { +- label = "root"; +- reg = <0x00200000 0x00300000>; +- }; +- partition@500000 { +- label = "user"; +- reg = <0x00500000 0x07a00000>; +- }; +- partition@7f00000 { +- label = "env1"; +- reg = <0x07f00000 0x00040000>; +- }; +- partition@7f40000 { +- label = "env2"; +- reg = <0x07f40000 0x00040000>; +- }; +- partition@7f80000 { +- label = "u-boot"; +- reg = <0x07f80000 0x00080000>; +- read-only; +- }; +- }; +- +- /* Note: CAN support needs be enabled in U-Boot */ +- can@2,0 { +- compatible = "bosch,cc770"; // Bosch CC770 +- reg = <2 0x0 0x100>; +- interrupts = <4 1>; +- interrupt-parent = <&mpic>; +- bosch,external-clock-frequency = <16000000>; +- bosch,disconnect-rx1-input; +- bosch,disconnect-tx1-output; +- bosch,iso-low-speed-mux; +- bosch,clock-out-frequency = <16000000>; +- }; +- +- can@2,100 { +- compatible = "bosch,cc770"; // Bosch CC770 +- reg = <2 0x100 0x100>; +- interrupts = <4 1>; +- interrupt-parent = <&mpic>; +- bosch,external-clock-frequency = <16000000>; +- bosch,disconnect-rx1-input; +- bosch,disconnect-tx1-output; +- bosch,iso-low-speed-mux; +- }; +- +- /* Note: NAND support needs to be enabled in U-Boot */ +- upm@3,0 { +- #address-cells = <0>; +- #size-cells = <0>; +- compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand"; +- reg = <3 0x0 0x800>; +- fsl,upm-addr-offset = <0x10>; +- fsl,upm-cmd-offset = <0x08>; +- /* Micron MT29F8G08FAB multi-chip device */ +- fsl,upm-addr-line-cs-offsets = <0x0 0x200>; +- fsl,upm-wait-flags = <0x5>; +- chip-delay = <25>; // in micro-seconds +- +- nand@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "fs"; +- reg = <0x00000000 0x10000000>; +- }; +- }; +- }; +- }; +- +- pci0: pci@e0008000 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; +- device_type = "pci"; +- reg = <0xe0008000 0x1000>; +- clock-frequency = <33333333>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 28 */ +- 0xe000 0 0 1 &mpic 2 1 +- 0xe000 0 0 2 &mpic 3 1 +- 0xe000 0 0 3 &mpic 6 1 +- 0xe000 0 0 4 &mpic 5 1 +- +- /* IDSEL 11 */ +- 0x5800 0 0 1 &mpic 6 1 +- 0x5800 0 0 2 &mpic 5 1 +- >; +- +- interrupt-parent = <&mpic>; +- interrupts = <24 2>; +- bus-range = <0 0>; +- ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; +- }; +- +- pci1: pcie@e000a000 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x0 (PEX) */ +- 0x00000 0 0 1 &mpic 0 1 +- 0x00000 0 0 2 &mpic 1 1 +- 0x00000 0 0 3 &mpic 2 1 +- 0x00000 0 0 4 &mpic 3 1>; +- +- interrupt-parent = <&mpic>; +- interrupts = <26 2>; +- bus-range = <0 0xff>; +- ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xef000000 0 0x08000000>; +- clock-frequency = <33333333>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xe000a000 0x1000>; +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- ranges = <0x02000000 0 0xc0000000 0x02000000 0 +- 0xc0000000 0 0x20000000 +- 0x01000000 0 0x00000000 0x01000000 0 +- 0x00000000 0 0x08000000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/tqm8555.dts b/scripts/dtc/include-prefixes/powerpc/tqm8555.dts +deleted file mode 100644 +index 54f3e82907d6..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/tqm8555.dts ++++ /dev/null +@@ -1,322 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * TQM 8555 Device Tree Source +- * +- * Copyright 2008 Freescale Semiconductor Inc. +- */ +- +-/dts-v1/; +- +-/ { +- model = "tqc,tqm8555"; +- compatible = "tqc,tqm8555"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8555@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- soc@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- ranges = <0x0 0xe0000000 0x100000>; +- bus-frequency = <0>; +- compatible = "fsl,mpc8555-immr", "simple-bus"; +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <8>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8555-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8540-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8540-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; +- cache-size = <0x40000>; // L2, 256K +- interrupt-parent = <&mpic>; +- interrupts = <16 2>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- +- dtt@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1337"; +- reg = <0x68>; +- }; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8555-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8555-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8555-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8555-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 30 2 34 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy2>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy1: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <1>; +- }; +- phy2: ethernet-phy@2 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <2>; +- }; +- phy3: ethernet-phy@3 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <3>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 2 36 2 40 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; // reg base, size +- clock-frequency = <0>; // should we fill in in uboot? +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; // reg base, size +- clock-frequency = <0>; // should we fill in in uboot? +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <45 2>; +- interrupt-parent = <&mpic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x7e>; +- fsl,descriptor-types-mask = <0x01010ebf>; +- }; +- +- mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- device_type = "open-pic"; +- compatible = "chrp,open-pic"; +- }; +- +- cpm@919c0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8555-cpm", "fsl,cpm2", "simple-bus"; +- reg = <0x919c0 0x30>; +- ranges; +- +- muram@80000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x80000 0x10000>; +- +- data@0 { +- compatible = "fsl,cpm-muram-data"; +- reg = <0 0x2000 0x9000 0x1000>; +- }; +- }; +- +- brg@919f0 { +- compatible = "fsl,mpc8555-brg", +- "fsl,cpm2-brg", +- "fsl,cpm-brg"; +- reg = <0x919f0 0x10 0x915f0 0x10>; +- clock-frequency = <0>; +- }; +- +- cpmpic: pic@90c00 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <46 2>; +- interrupt-parent = <&mpic>; +- reg = <0x90c00 0x80>; +- compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic"; +- }; +- }; +- }; +- +- pci0: pci@e0008000 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; +- device_type = "pci"; +- reg = <0xe0008000 0x1000>; +- clock-frequency = <66666666>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 28 */ +- 0xe000 0 0 1 &mpic 2 1 +- 0xe000 0 0 2 &mpic 3 1 +- 0xe000 0 0 3 &mpic 6 1 +- 0xe000 0 0 4 &mpic 5 1 +- +- /* IDSEL 11 */ +- 0x5800 0 0 1 &mpic 6 1 +- 0x5800 0 0 2 &mpic 5 1 +- >; +- +- interrupt-parent = <&mpic>; +- interrupts = <24 2>; +- bus-range = <0 0>; +- ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/tqm8560.dts b/scripts/dtc/include-prefixes/powerpc/tqm8560.dts +deleted file mode 100644 +index 7415cb69f60d..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/tqm8560.dts ++++ /dev/null +@@ -1,395 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * TQM 8560 Device Tree Source +- * +- * Copyright 2008 Freescale Semiconductor Inc. +- * Copyright 2008 Wolfgang Grandegger +- */ +- +-/dts-v1/; +- +-/ { +- model = "tqc,tqm8560"; +- compatible = "tqc,tqm8560"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8560@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; +- i-cache-line-size = <32>; +- d-cache-size = <32768>; +- i-cache-size = <32768>; +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x10000000>; +- }; +- +- soc@e0000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- ranges = <0x0 0xe0000000 0x100000>; +- bus-frequency = <0>; +- compatible = "fsl,mpc8560-immr", "simple-bus"; +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <8>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8560-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8540-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8540-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; +- cache-size = <0x40000>; // L2, 256K +- interrupt-parent = <&mpic>; +- interrupts = <16 2>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- +- dtt@48 { +- compatible = "national,lm75"; +- reg = <0x48>; +- }; +- +- rtc@68 { +- compatible = "dallas,ds1337"; +- reg = <0x68>; +- }; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8560-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8560-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8560-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8560-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 30 2 34 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy2>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy1: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <1>; +- }; +- phy2: ethernet-phy@2 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <2>; +- }; +- phy3: ethernet-phy@3 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <3>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "TSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 2 36 2 40 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- device_type = "open-pic"; +- compatible = "chrp,open-pic"; +- }; +- +- cpm@919c0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus"; +- reg = <0x919c0 0x30>; +- ranges; +- +- muram@80000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x80000 0x10000>; +- +- data@0 { +- compatible = "fsl,cpm-muram-data"; +- reg = <0 0x4000 0x9000 0x2000>; +- }; +- }; +- +- brg@919f0 { +- compatible = "fsl,mpc8560-brg", +- "fsl,cpm2-brg", +- "fsl,cpm-brg"; +- reg = <0x919f0 0x10 0x915f0 0x10>; +- clock-frequency = <0>; +- }; +- +- cpmpic: pic@90c00 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <46 2>; +- interrupt-parent = <&mpic>; +- reg = <0x90c00 0x80>; +- compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic"; +- }; +- +- serial0: serial@91a00 { +- device_type = "serial"; +- compatible = "fsl,mpc8560-scc-uart", +- "fsl,cpm2-scc-uart"; +- reg = <0x91a00 0x20 0x88000 0x100>; +- fsl,cpm-brg = <1>; +- fsl,cpm-command = <0x800000>; +- current-speed = <115200>; +- interrupts = <40 8>; +- interrupt-parent = <&cpmpic>; +- }; +- +- serial1: serial@91a20 { +- device_type = "serial"; +- compatible = "fsl,mpc8560-scc-uart", +- "fsl,cpm2-scc-uart"; +- reg = <0x91a20 0x20 0x88100 0x100>; +- fsl,cpm-brg = <2>; +- fsl,cpm-command = <0x4a00000>; +- current-speed = <115200>; +- interrupts = <41 8>; +- interrupt-parent = <&cpmpic>; +- }; +- +- enet2: ethernet@91340 { +- device_type = "network"; +- compatible = "fsl,mpc8560-fcc-enet", +- "fsl,cpm2-fcc-enet"; +- reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- fsl,cpm-command = <0x1a400300>; +- interrupts = <34 8>; +- interrupt-parent = <&cpmpic>; +- phy-handle = <&phy3>; +- }; +- }; +- }; +- +- localbus@e0005000 { +- compatible = "fsl,mpc8560-localbus", "fsl,pq3-localbus", +- "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- reg = <0xe0005000 0x100>; // BRx, ORx, etc. +- interrupt-parent = <&mpic>; +- interrupts = <19 2>; +- +- ranges = < +- 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 +- 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 +- 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527) +- >; +- +- flash@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <1 0x0 0x8000000>; +- bank-width = <4>; +- device-width = <1>; +- +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x00200000>; +- }; +- partition@200000 { +- label = "root"; +- reg = <0x00200000 0x00300000>; +- }; +- partition@500000 { +- label = "user"; +- reg = <0x00500000 0x07a00000>; +- }; +- partition@7f00000 { +- label = "env1"; +- reg = <0x07f00000 0x00040000>; +- }; +- partition@7f40000 { +- label = "env2"; +- reg = <0x07f40000 0x00040000>; +- }; +- partition@7f80000 { +- label = "u-boot"; +- reg = <0x07f80000 0x00080000>; +- read-only; +- }; +- }; +- +- /* Note: CAN support needs be enabled in U-Boot */ +- can0@2,0 { +- compatible = "intel,82527"; // Bosch CC770 +- reg = <2 0x0 0x100>; +- interrupts = <4 1>; +- interrupt-parent = <&mpic>; +- }; +- +- can1@2,100 { +- compatible = "intel,82527"; // Bosch CC770 +- reg = <2 0x100 0x100>; +- interrupts = <4 1>; +- interrupt-parent = <&mpic>; +- }; +- }; +- +- pci0: pci@e0008000 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; +- device_type = "pci"; +- reg = <0xe0008000 0x1000>; +- clock-frequency = <66666666>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 28 */ +- 0xe000 0 0 1 &mpic 2 1 +- 0xe000 0 0 2 &mpic 3 1 +- 0xe000 0 0 3 &mpic 6 1 +- 0xe000 0 0 4 &mpic 5 1 +- +- /* IDSEL 11 */ +- 0x5800 0 0 1 &mpic 6 1 +- 0x5800 0 0 2 &mpic 5 1 +- >; +- +- interrupt-parent = <&mpic>; +- interrupts = <24 2>; +- bus-range = <0 0>; +- ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/tqm8xx.dts b/scripts/dtc/include-prefixes/powerpc/tqm8xx.dts +deleted file mode 100644 +index d16cdfd81205..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/tqm8xx.dts ++++ /dev/null +@@ -1,192 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * TQM8XX Device Tree Source +- * +- * Heiko Schocher +- * 2010 DENX Software Engineering GmbH +- */ +- +-/dts-v1/; +- +-/ { +- model = "TQM8xx"; +- compatible = "tqc,tqm8xx"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = ð0; +- ethernet1 = ð1; +- mdio1 = &phy1; +- serial0 = &smc1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,860@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <16>; // 16 bytes +- i-cache-line-size = <16>; // 16 bytes +- d-cache-size = <0x1000>; // L1, 4K +- i-cache-size = <0x1000>; // L1, 4K +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- interrupts = <15 2>; // decrementer interrupt +- interrupt-parent = <&PIC>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x2000000>; +- }; +- +- localbus@fff00100 { +- compatible = "fsl,mpc860-localbus", "fsl,pq1-localbus"; +- #address-cells = <2>; +- #size-cells = <1>; +- reg = <0xfff00100 0x40>; +- +- ranges = < +- 0x0 0x0 0x40000000 0x800000 +- 0x3 0x0 0xc0000000 0x200 +- >; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x800000>; +- #address-cells = <1>; +- #size-cells = <1>; +- bank-width = <4>; +- device-width = <2>; +- }; +- +- /* Note: CAN support needs be enabled in U-Boot */ +- can@3,0 { +- compatible = "intc,82527"; +- reg = <3 0x0 0x80>; +- interrupts = <8 1>; +- interrupt-parent = <&PIC>; +- bosch,external-clock-frequency = <16000000>; +- bosch,disconnect-rx1-input; +- bosch,disconnect-tx1-output; +- bosch,iso-low-speed-mux; +- bosch,clock-out-frequency = <16000000>; +- }; +- +- can@3,100 { +- compatible = "intc,82527"; +- reg = <3 0x100 0x80>; +- interrupts = <8 1>; +- interrupt-parent = <&PIC>; +- bosch,external-clock-frequency = <16000000>; +- bosch,disconnect-rx1-input; +- bosch,disconnect-tx1-output; +- bosch,iso-low-speed-mux; +- }; +- }; +- +- soc@fff00000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- ranges = <0x0 0xfff00000 0x00004000>; +- +- phy1: mdio@e00 { +- compatible = "fsl,mpc866-fec-mdio", "fsl,pq1-fec-mdio"; +- reg = <0xe00 0x188>; +- #address-cells = <1>; +- #size-cells = <0>; +- PHY: ethernet-phy@f { +- reg = <0xf>; +- }; +- }; +- +- eth1: ethernet@e00 { +- device_type = "network"; +- compatible = "fsl,mpc866-fec-enet", +- "fsl,pq1-fec-enet"; +- reg = <0xe00 0x188>; +- interrupts = <3 1>; +- interrupt-parent = <&PIC>; +- phy-handle = <&PHY>; +- linux,network-index = <1>; +- }; +- +- PIC: pic@0 { +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x0 0x24>; +- compatible = "fsl,mpc860-pic", "fsl,pq1-pic"; +- }; +- +- cpm@9c0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc860-cpm", "fsl,cpm1"; +- ranges; +- reg = <0x9c0 0x40>; +- brg-frequency = <0>; +- interrupts = <0 2>; // cpm error interrupt +- interrupt-parent = <&CPM_PIC>; +- +- muram@2000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x0 0x2000 0x2000>; +- +- data@0 { +- compatible = "fsl,cpm-muram-data"; +- reg = <0x0 0x2000>; +- }; +- }; +- +- brg@9f0 { +- compatible = "fsl,mpc860-brg", +- "fsl,cpm1-brg", +- "fsl,cpm-brg"; +- reg = <0x9f0 0x10>; +- clock-frequency = <0>; +- }; +- +- CPM_PIC: pic@930 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupts = <5 2 0 2>; +- interrupt-parent = <&PIC>; +- reg = <0x930 0x20>; +- compatible = "fsl,mpc860-cpm-pic", +- "fsl,cpm1-pic"; +- }; +- +- +- smc1: serial@a80 { +- device_type = "serial"; +- compatible = "fsl,mpc860-smc-uart", +- "fsl,cpm1-smc-uart"; +- reg = <0xa80 0x10 0x3e80 0x40>; +- interrupts = <4>; +- interrupt-parent = <&CPM_PIC>; +- fsl,cpm-brg = <1>; +- fsl,cpm-command = <0x90>; +- }; +- +- eth0: ethernet@a00 { +- device_type = "network"; +- compatible = "fsl,mpc860-scc-enet", +- "fsl,cpm1-scc-enet"; +- reg = <0xa00 0x18 0x3c00 0x100>; +- interrupts = <30>; +- interrupt-parent = <&CPM_PIC>; +- fsl,cpm-command = <0000>; +- linux,network-index = <0>; +- fixed-link = <0 0 10 0 0>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/uc101.dts b/scripts/dtc/include-prefixes/powerpc/uc101.dts +deleted file mode 100644 +index 2e34d019178b..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/uc101.dts ++++ /dev/null +@@ -1,152 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * Manroland uc101 board Device Tree Source +- * +- * Copyright (C) 2009 DENX Software Engineering GmbH +- * Heiko Schocher +- * Copyright 2006-2007 Secret Lab Technologies Ltd. +- */ +- +-/include/ "mpc5200b.dtsi" +- +-&gpt0 { gpio-controller; }; +-&gpt1 { gpio-controller; }; +-&gpt2 { gpio-controller; }; +-&gpt3 { gpio-controller; }; +-&gpt4 { gpio-controller; }; +-&gpt5 { gpio-controller; }; +-&gpt6 { gpio-controller; }; +-&gpt7 { gpio-controller; }; +- +-/ { +- model = "manroland,uc101"; +- compatible = "manroland,uc101"; +- +- soc5200@f0000000 { +- rtc@800 { +- status = "disabled"; +- }; +- +- can@900 { +- status = "disabled"; +- }; +- +- can@980 { +- status = "disabled"; +- }; +- +- spi@f00 { +- status = "disabled"; +- }; +- +- usb@1000 { +- status = "disabled"; +- }; +- +- psc@2000 { // PSC1 +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- psc@2200 { // PSC2 +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- psc@2400 { // PSC3 +- status = "disabled"; +- }; +- +- psc@2600 { // PSC4 +- status = "disabled"; +- }; +- +- psc@2800 { // PSC5 +- status = "disabled"; +- }; +- +- psc@2c00 { // PSC6 +- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; +- }; +- +- ethernet@3000 { +- phy-handle = <&phy0>; +- }; +- +- mdio@3000 { +- phy0: ethernet-phy@0 { +- compatible = "intel,lxt971"; +- reg = <0>; +- }; +- }; +- +- i2c@3d00 { +- status = "disabled"; +- }; +- +- i2c@3d40 { +- fsl,preserve-clocking; +- clock-frequency = <400000>; +- +- hwmon@2c { +- compatible = "ad,adm9240"; +- reg = <0x2c>; +- }; +- rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- }; +- }; +- }; +- +- pci@f0000d00 { +- status = "disabled"; +- }; +- +- localbus { +- ranges = <0 0 0xff800000 0x00800000 +- 1 0 0x80000000 0x00800000 +- 3 0 0x80000000 0x00800000>; +- +- flash@0,0 { +- compatible = "cfi-flash"; +- reg = <0 0 0x00800000>; +- bank-width = <2>; +- device-width = <2>; +- #size-cells = <1>; +- #address-cells = <1>; +- +- partition@0 { +- label = "DTS"; +- reg = <0x0 0x00100000>; +- }; +- partition@100000 { +- label = "Kernel"; +- reg = <0x100000 0x00200000>; +- }; +- partition@300000 { +- label = "RootFS"; +- reg = <0x00300000 0x00200000>; +- }; +- partition@500000 { +- label = "user"; +- reg = <0x00500000 0x00200000>; +- }; +- partition@700000 { +- label = "U-Boot"; +- reg = <0x00700000 0x00040000>; +- }; +- partition@740000 { +- label = "Env"; +- reg = <0x00740000 0x00010000>; +- }; +- partition@750000 { +- label = "red. Env"; +- reg = <0x00750000 0x00010000>; +- }; +- partition@760000 { +- label = "reserve"; +- reg = <0x00760000 0x000a0000>; +- }; +- }; +- +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/warp.dts b/scripts/dtc/include-prefixes/powerpc/warp.dts +deleted file mode 100644 +index b4f32740870e..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/warp.dts ++++ /dev/null +@@ -1,309 +0,0 @@ +-/* +- * Device Tree Source for PIKA Warp +- * +- * Copyright (c) 2008-2009 PIKA Technologies +- * Sean MacLennan +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <2>; +- #size-cells = <1>; +- model = "pika,warp"; +- compatible = "pika,warp"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- serial0 = &UART0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,440EP"; +- reg = <0x00000000>; +- clock-frequency = <0>; /* Filled in by zImage */ +- timebase-frequency = <0>; /* Filled in by zImage */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */ +- }; +- +- UIC0: interrupt-controller0 { +- compatible = "ibm,uic-440ep","ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-440ep","ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- SDR0: sdr { +- compatible = "ibm,sdr-440ep"; +- dcr-reg = <0x00e 0x002>; +- }; +- +- CPR0: cpr { +- compatible = "ibm,cpr-440ep"; +- dcr-reg = <0x00c 0x002>; +- }; +- +- plb { +- compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; /* Filled in by zImage */ +- +- SDRAM0: sdram { +- compatible = "ibm,sdram-440ep", "ibm,sdram-405gp"; +- dcr-reg = <0x010 0x002>; +- }; +- +- DMA0: dma { +- compatible = "ibm,dma-440ep", "ibm,dma-440gp"; +- dcr-reg = <0x100 0x027>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <4>; +- num-rx-chans = <2>; +- interrupt-parent = <&MAL0>; +- interrupts = <0x0 0x1 0x2 0x3 0x4>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x00000000 0x00000000 0x00000000 0x80000000 +- 0x80000000 0x00000000 0x80000000 0x80000000>; +- interrupt-parent = <&UIC1>; +- interrupts = <0x7 0x4>; +- clock-frequency = <0>; /* Filled in by zImage */ +- +- EBC0: ebc { +- compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; /* Filled in by zImage */ +- interrupts = <0x5 0x1>; +- interrupt-parent = <&UIC1>; +- +- fpga@2,0 { +- compatible = "pika,fpga"; +- reg = <0x00000002 0x00000000 0x00001000>; +- interrupts = <0x18 0x8>; +- interrupt-parent = <&UIC0>; +- }; +- +- fpga@2,2000 { +- compatible = "pika,fpga-sgl"; +- reg = <0x00000002 0x00002000 0x00000200>; +- }; +- +- fpga@2,4000 { +- compatible = "pika,fpga-sd"; +- reg = <0x00000002 0x00004000 0x00004000>; +- }; +- +- nor@0,0 { +- compatible = "amd,s29gl032a", "cfi-flash"; +- bank-width = <2>; +- reg = <0x00000000 0x00000000 0x00400000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "splash"; +- reg = <0x00000000 0x00010000>; +- }; +- partition@300000 { +- label = "fpga"; +- reg = <0x0300000 0x00040000>; +- }; +- partition@340000 { +- label = "env"; +- reg = <0x0340000 0x00040000>; +- }; +- partition@380000 { +- label = "u-boot"; +- reg = <0x0380000 0x00080000>; +- }; +- }; +- +- ndfc@1,0 { +- compatible = "ibm,ndfc"; +- reg = <0x00000001 0x00000000 0x00002000>; +- ccr = <0x00001000>; +- bank-settings = <0x80002222>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- nand { +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x00200000>; +- }; +- partition@200000 { +- label = "root"; +- reg = <0x00200000 0x03E00000>; +- }; +- partition@40000000 { +- label = "persistent"; +- reg = <0x04000000 0x04000000>; +- }; +- partition@80000000 { +- label = "persistent1"; +- reg = <0x08000000 0x04000000>; +- }; +- partition@C0000000 { +- label = "persistent2"; +- reg = <0x0C000000 0x04000000>; +- }; +- }; +- }; +- }; +- +- UART0: serial@ef600300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600300 0x00000008>; +- virtual-reg = <0xef600300>; +- clock-frequency = <0>; /* Filled in by zImage */ +- current-speed = <115200>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x0 0x4>; +- }; +- +- IIC0: i2c@ef600700 { +- compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; +- reg = <0xef600700 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x2 0x4>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- ad7414@4a { +- compatible = "adi,ad7414"; +- reg = <0x4a>; +- interrupts = <0x19 0x8>; +- interrupt-parent = <&UIC0>; +- }; +- +- /* This will create 52 and 53 */ +- at24@52 { +- compatible = "atmel,24c04"; +- reg = <0x52>; +- }; +- }; +- +- GPIO0: gpio@ef600b00 { +- compatible = "ibm,ppc4xx-gpio"; +- reg = <0xef600b00 0x00000048>; +- #gpio-cells = <2>; +- gpio-controller; +- }; +- +- GPIO1: gpio@ef600c00 { +- compatible = "ibm,ppc4xx-gpio"; +- reg = <0xef600c00 0x00000048>; +- #gpio-cells = <2>; +- gpio-controller; +- }; +- +- power-leds { +- compatible = "gpio-leds"; +- green { +- gpios = <&GPIO1 0 0>; +- default-state = "keep"; +- }; +- red { +- gpios = <&GPIO1 1 0>; +- default-state = "keep"; +- }; +- }; +- +- ZMII0: emac-zmii@ef600d00 { +- compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii"; +- reg = <0xef600d00 0x0000000c>; +- }; +- +- EMAC0: ethernet@ef600e00 { +- device_type = "network"; +- compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; +- interrupt-parent = <&UIC1>; +- interrupts = <0x1c 0x4 0x1d 0x4>; +- reg = <0xef600e00 0x00000070>; +- local-mac-address = [000000000000]; +- mal-device = <&MAL0>; +- mal-tx-channel = <0 1>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <1500>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "rmii"; +- phy-map = <0x00000000>; +- zmii-device = <&ZMII0>; +- zmii-channel = <0>; +- }; +- +- usb@ef601000 { +- compatible = "ohci-be"; +- reg = <0xef601000 0x00000080>; +- interrupts = <0x8 0x1 0x9 0x1>; +- interrupt-parent = < &UIC1 >; +- }; +- }; +- }; +- +- chosen { +- stdout-path = "/plb/opb/serial@ef600300"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/wii.dts b/scripts/dtc/include-prefixes/powerpc/wii.dts +deleted file mode 100644 +index e9c945b123c6..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/wii.dts ++++ /dev/null +@@ -1,267 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later +-/* +- * arch/powerpc/boot/dts/wii.dts +- * +- * Nintendo Wii platform device tree source +- * Copyright (C) 2008-2009 The GameCube Linux Team +- * Copyright (C) 2008,2009 Albert Herranz +- */ +- +-/dts-v1/; +-#include +-#include +- +-/* +- * This is commented-out for now. +- * Until a later patch is merged, the kernel can use only the first +- * contiguous RAM range and will BUG() if the memreserve is outside +- * that range. +- */ +-/*/memreserve/ 0x10000000 0x0004000;*/ /* DSP RAM */ +- +-/ { +- model = "nintendo,wii"; +- compatible = "nintendo,wii"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- chosen { +- bootargs = "root=/dev/mmcblk0p2 rootwait udbg-immortal"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */ +- 0x10000000 0x04000000>; /* MEM2 64MB GDDR3 */ +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,broadway@0 { +- device_type = "cpu"; +- reg = <0>; +- clock-frequency = <729000000>; /* 729MHz */ +- bus-frequency = <243000000>; /* 243MHz core-to-bus 3x */ +- timebase-frequency = <60750000>; /* 243MHz / 4 */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- }; +- }; +- +- /* devices contained in the hollywood chipset */ +- hollywood { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "nintendo,hollywood"; +- ranges = <0x0c000000 0x0c000000 0x01000000 +- 0x0d000000 0x0d000000 0x00800000 +- 0x0d800000 0x0d800000 0x00800000>; +- interrupt-parent = <&PIC0>; +- +- video@c002000 { +- compatible = "nintendo,hollywood-vi", +- "nintendo,flipper-vi"; +- reg = <0x0c002000 0x100>; +- interrupts = <8>; +- }; +- +- processor-interface@c003000 { +- compatible = "nintendo,hollywood-pi", +- "nintendo,flipper-pi"; +- reg = <0x0c003000 0x100>; +- +- PIC0: pic0 { +- #interrupt-cells = <1>; +- compatible = "nintendo,flipper-pic"; +- interrupt-controller; +- }; +- }; +- +- dsp@c005000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "nintendo,hollywood-dsp", +- "nintendo,flipper-dsp"; +- reg = <0x0c005000 0x200>; +- interrupts = <6>; +- }; +- +- gamepad-controller@d006400 { +- compatible = "nintendo,hollywood-si", +- "nintendo,flipper-si"; +- reg = <0x0d006400 0x100>; +- interrupts = <3>; +- }; +- +- audio@c006c00 { +- compatible = "nintendo,hollywood-ai", +- "nintendo,flipper-ai"; +- reg = <0x0d006c00 0x20>; +- interrupts = <6>; +- }; +- +- /* External Interface bus */ +- exi@d006800 { +- compatible = "nintendo,hollywood-exi", +- "nintendo,flipper-exi"; +- reg = <0x0d006800 0x40>; +- virtual-reg = <0x0d006800>; +- interrupts = <4>; +- }; +- +- usb@d040000 { +- compatible = "nintendo,hollywood-usb-ehci", +- "usb-ehci"; +- reg = <0x0d040000 0x100>; +- interrupts = <4>; +- interrupt-parent = <&PIC1>; +- }; +- +- usb@d050000 { +- compatible = "nintendo,hollywood-usb-ohci", +- "usb-ohci"; +- reg = <0x0d050000 0x100>; +- interrupts = <5>; +- interrupt-parent = <&PIC1>; +- }; +- +- usb@d060000 { +- compatible = "nintendo,hollywood-usb-ohci", +- "usb-ohci"; +- reg = <0x0d060000 0x100>; +- interrupts = <6>; +- interrupt-parent = <&PIC1>; +- }; +- +- sd@d070000 { +- compatible = "nintendo,hollywood-sdhci", +- "sdhci"; +- reg = <0x0d070000 0x200>; +- interrupts = <7>; +- interrupt-parent = <&PIC1>; +- }; +- +- sdio@d080000 { +- compatible = "nintendo,hollywood-sdhci", +- "sdhci"; +- reg = <0x0d080000 0x200>; +- interrupts = <8>; +- interrupt-parent = <&PIC1>; +- }; +- +- ipc@d000000 { +- compatible = "nintendo,hollywood-ipc"; +- reg = <0x0d000000 0x10>; +- interrupts = <30>; +- interrupt-parent = <&PIC1>; +- }; +- +- PIC1: pic1@d800030 { +- #interrupt-cells = <1>; +- compatible = "nintendo,hollywood-pic"; +- reg = <0x0d800030 0x10>; +- interrupt-controller; +- interrupts = <14>; +- }; +- +- GPIO: gpio@d8000c0 { +- #gpio-cells = <2>; +- compatible = "nintendo,hollywood-gpio"; +- reg = <0x0d8000c0 0x40>; +- gpio-controller; +- ngpios = <24>; +- +- gpio-line-names = +- "POWER", "SHUTDOWN", "FAN", "DC_DC", +- "DI_SPIN", "SLOT_LED", "EJECT_BTN", "SLOT_IN", +- "SENSOR_BAR", "DO_EJECT", "EEP_CS", "EEP_CLK", +- "EEP_MOSI", "EEP_MISO", "AVE_SCL", "AVE_SDA", +- "DEBUG0", "DEBUG1", "DEBUG2", "DEBUG3", +- "DEBUG4", "DEBUG5", "DEBUG6", "DEBUG7"; +- +- interrupt-controller; +- #interrupt-cells = <2>; +- interrupts = <10>; +- interrupt-parent = <&PIC1>; +- +- /* +- * This is commented out while a standard binding +- * for i2c over gpio is defined. +- */ +- /* +- i2c-video { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "i2c-gpio"; +- +- gpios = <&GPIO 15 0 +- &GPIO 14 0>; +- clock-frequency = <250000>; +- no-clock-stretching; +- scl-is-open-drain; +- sda-is-open-drain; +- sda-enforce-dir; +- +- AVE: audio-video-encoder@70 { +- compatible = "nintendo,wii-audio-video-encoder"; +- reg = <0x70>; +- }; +- }; +- */ +- }; +- +- control@d800100 { +- compatible = "nintendo,hollywood-control"; +- /* +- * Both the address and length are wrong, according to +- * Wiibrew this should be <0x0d800000 0x400>, but it +- * requires refactoring the PIC1, GPIO and OTP nodes +- * before changing that. +- */ +- reg = <0x0d800100 0xa0>; +- }; +- +- otp@d8001ec { +- compatible = "nintendo,hollywood-otp"; +- reg = <0x0d8001ec 0x8>; +- }; +- +- disk@d806000 { +- compatible = "nintendo,hollywood-di"; +- reg = <0x0d806000 0x40>; +- interrupts = <2>; +- }; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- /* This is the blue LED in the disk drive slot */ +- drive-slot { +- label = "wii:blue:drive_slot"; +- gpios = <&GPIO 5 GPIO_ACTIVE_HIGH>; +- panic-indicator; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- power { +- label = "Power Button"; +- gpios = <&GPIO 0 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- }; +- +- eject { +- label = "Eject Button"; +- gpios = <&GPIO 6 GPIO_ACTIVE_HIGH>; +- linux,code = ; +- }; +- }; +-}; +- +diff --git a/scripts/dtc/include-prefixes/powerpc/xcalibur1501.dts b/scripts/dtc/include-prefixes/powerpc/xcalibur1501.dts +deleted file mode 100644 +index 46c25bda9515..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/xcalibur1501.dts ++++ /dev/null +@@ -1,693 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2008 Extreme Engineering Solutions, Inc. +- * Based on MPC8572DS device tree from Freescale Semiconductor, Inc. +- * +- * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E +- */ +- +-/dts-v1/; +-/ { +- model = "xes,xcalibur1501"; +- compatible = "xes,xcalibur1501", "xes,MPC8572"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- serial0 = &serial0; +- serial1 = &serial1; +- pci2 = &pci2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8572@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <0x8000>; // L1, 32K +- i-cache-size = <0x8000>; // L1, 32K +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- next-level-cache = <&L2>; +- }; +- +- PowerPC,8572@1 { +- device_type = "cpu"; +- reg = <0x1>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <0x8000>; // L1, 32K +- i-cache-size = <0x8000>; // L1, 32K +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot +- }; +- +- localbus@ef005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; +- reg = <0 0xef005000 0 0x1000>; +- interrupts = <19 2>; +- interrupt-parent = <&mpic>; +- /* Local bus region mappings */ +- ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Flash 1 */ +- 1 0 0 0xf0000000 0x8000000 /* CS1: Flash 2 */ +- 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */ +- 3 0 0 0xef840000 0x40000 /* CS3: NAND CE2 */ +- 4 0 0 0xe9000000 0x100000>; /* CS4: USB */ +- +- nor-boot@0,0 { +- compatible = "amd,s29gl01gp", "cfi-flash"; +- bank-width = <2>; +- reg = <0 0 0x8000000>; /* 128MB */ +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "Primary user space"; +- reg = <0x00000000 0x6f00000>; /* 111 MB */ +- }; +- partition@6f00000 { +- label = "Primary kernel"; +- reg = <0x6f00000 0x1000000>; /* 16 MB */ +- }; +- partition@7f00000 { +- label = "Primary DTB"; +- reg = <0x7f00000 0x40000>; /* 256 KB */ +- }; +- partition@7f40000 { +- label = "Primary U-Boot environment"; +- reg = <0x7f40000 0x40000>; /* 256 KB */ +- }; +- partition@7f80000 { +- label = "Primary U-Boot"; +- reg = <0x7f80000 0x80000>; /* 512 KB */ +- read-only; +- }; +- }; +- +- nor-alternate@1,0 { +- compatible = "amd,s29gl01gp", "cfi-flash"; +- bank-width = <2>; +- //reg = <0xf0000000 0x08000000>; /* 128MB */ +- reg = <1 0 0x8000000>; /* 128MB */ +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "Secondary user space"; +- reg = <0x00000000 0x6f00000>; /* 111 MB */ +- }; +- partition@6f00000 { +- label = "Secondary kernel"; +- reg = <0x6f00000 0x1000000>; /* 16 MB */ +- }; +- partition@7f00000 { +- label = "Secondary DTB"; +- reg = <0x7f00000 0x40000>; /* 256 KB */ +- }; +- partition@7f40000 { +- label = "Secondary U-Boot environment"; +- reg = <0x7f40000 0x40000>; /* 256 KB */ +- }; +- partition@7f80000 { +- label = "Secondary U-Boot"; +- reg = <0x7f80000 0x80000>; /* 512 KB */ +- read-only; +- }; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * Actual part could be ST Micro NAND08GW3B2A (1 GB), +- * Micron MT29F8G08DAA (2x 512 MB), or Micron +- * MT29F16G08FAA (2x 1 GB), depending on the build +- * configuration +- */ +- compatible = "fsl,mpc8572-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <2 0 0x40000>; +- /* U-Boot should fix this up if chip size > 1 GB */ +- partition@0 { +- label = "NAND Filesystem"; +- reg = <0 0x40000000>; +- }; +- }; +- +- usb@4,0 { +- compatible = "nxp,usb-isp1761"; +- reg = <4 0 0x100000>; +- bus-width = <32>; +- interrupt-parent = <&mpic>; +- interrupts = <10 1>; +- }; +- }; +- +- soc8572@ef000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,mpc8572-immr", "simple-bus"; +- ranges = <0x0 0 0xef000000 0x100000>; +- bus-frequency = <0>; // Filled out by uboot. +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <12>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8572-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8572-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- memory-controller@6000 { +- compatible = "fsl,mpc8572-memory-controller"; +- reg = <0x6000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8572-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x100000>; // L2, 1M +- interrupt-parent = <&mpic>; +- interrupts = <16 2>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- +- temp-sensor@48 { +- compatible = "dallas,ds1631", "dallas,ds1621"; +- reg = <0x48>; +- }; +- +- temp-sensor@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- +- cpu-supervisor@51 { +- compatible = "dallas,ds4510"; +- reg = <0x51>; +- }; +- +- eeprom@54 { +- compatible = "atmel,at24c128b"; +- reg = <0x54>; +- }; +- +- rtc@68 { +- compatible = "st,m41t00", +- "dallas,ds1338"; +- reg = <0x68>; +- }; +- +- pcie-switch@6a { +- compatible = "plx,pex8648"; +- reg = <0x6a>; +- }; +- +- /* On-board signals for VID, flash, serial */ +- gpio1: gpio@18 { +- compatible = "nxp,pca9557"; +- reg = <0x18>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- +- /* PMC0/XMC0 signals */ +- gpio2: gpio@1c { +- compatible = "nxp,pca9557"; +- reg = <0x1c>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- +- /* PMC1/XMC1 signals */ +- gpio3: gpio@1d { +- compatible = "nxp,pca9557"; +- reg = <0x1d>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- +- /* CompactPCI signals (sysen, GA[4:0]) */ +- gpio4: gpio@1e { +- compatible = "nxp,pca9557"; +- reg = <0x1e>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- +- /* CompactPCI J5 GPIO and FAL/DEG/PRST */ +- gpio5: gpio@1f { +- compatible = "nxp,pca9557"; +- reg = <0x1f>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- }; +- +- dma@c300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; +- reg = <0xc300 0x4>; +- ranges = <0x0 0xc100 0x200>; +- cell-index = <1>; +- dma-channel@0 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <76 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <77 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <78 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <79 2>; +- }; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- /* eTSEC 1 front panel 0 */ +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 30 2 34 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- phy-connection-type = "sgmii"; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy0: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <4 1>; +- reg = <0x1>; +- }; +- phy1: ethernet-phy@2 { +- interrupt-parent = <&mpic>; +- interrupts = <4 1>; +- reg = <0x2>; +- }; +- phy2: ethernet-phy@3 { +- interrupt-parent = <&mpic>; +- interrupts = <5 1>; +- reg = <0x3>; +- }; +- phy3: ethernet-phy@4 { +- interrupt-parent = <&mpic>; +- interrupts = <5 1>; +- reg = <0x4>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- /* eTSEC 2 front panel 1 */ +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 2 36 2 40 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- phy-connection-type = "sgmii"; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- /* eTSEC 3 PICMG2.16 backplane port 0 */ +- enet2: ethernet@26000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <2>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x26000 0x1000>; +- ranges = <0x0 0x26000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <31 2 32 2 33 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi2>; +- phy-handle = <&phy2>; +- phy-connection-type = "sgmii"; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- /* eTSEC 4 PICMG2.16 backplane port 1 */ +- enet3: ethernet@27000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <3>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x27000 0x1000>; +- ranges = <0x0 0x27000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <37 2 38 2 39 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi3>; +- phy-handle = <&phy3>; +- phy-connection-type = "sgmii"; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi3: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- /* UART0 */ +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- /* UART1 */ +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- global-utilities@e0000 { //global utilities block +- compatible = "fsl,mpc8572-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +- +- msi@41600 { +- compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; +- reg = <0x41600 0x80>; +- msi-available-ranges = <0 0x100>; +- interrupts = < +- 0xe0 0 +- 0xe1 0 +- 0xe2 0 +- 0xe3 0 +- 0xe4 0 +- 0xe5 0 +- 0xe6 0 +- 0xe7 0>; +- interrupt-parent = <&mpic>; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", +- "fsl,sec2.1", "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <45 2 58 2>; +- interrupt-parent = <&mpic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x9fe>; +- fsl,descriptor-types-mask = <0x3ab0ebf>; +- }; +- +- mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- compatible = "chrp,open-pic"; +- device_type = "open-pic"; +- }; +- +- gpio0: gpio@f000 { +- compatible = "fsl,mpc8572-gpio"; +- reg = <0xf000 0x1000>; +- interrupts = <47 2>; +- interrupt-parent = <&mpic>; +- #gpio-cells = <2>; +- gpio-controller; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- heartbeat { +- label = "Heartbeat"; +- gpios = <&gpio0 4 1>; +- linux,default-trigger = "heartbeat"; +- }; +- +- yellow { +- label = "Yellow"; +- gpios = <&gpio0 5 1>; +- }; +- +- red { +- label = "Red"; +- gpios = <&gpio0 6 1>; +- }; +- +- green { +- label = "Green"; +- gpios = <&gpio0 7 1>; +- }; +- }; +- +- /* PME (pattern-matcher) */ +- pme@10000 { +- compatible = "fsl,mpc8572-pme", "pme8572"; +- reg = <0x10000 0x5000>; +- interrupts = <57 2 64 2 65 2 66 2 67 2>; +- interrupt-parent = <&mpic>; +- }; +- +- tlu@2f000 { +- compatible = "fsl,mpc8572-tlu", "fsl_tlu"; +- reg = <0x2f000 0x1000>; +- interrupts = <61 2>; +- interrupt-parent = <&mpic>; +- }; +- +- tlu@15000 { +- compatible = "fsl,mpc8572-tlu", "fsl_tlu"; +- reg = <0x15000 0x1000>; +- interrupts = <75 2>; +- interrupt-parent = <&mpic>; +- }; +- }; +- +- /* +- * PCI Express controller 3 @ ef008000 is not used. +- * This would have been pci0 on other mpc85xx platforms. +- * +- * PCI Express controller 2 @ ef009000 is not used. +- * This would have been pci1 on other mpc85xx platforms. +- */ +- +- /* PCI Express controller 1, wired to PEX8648 PCIe switch */ +- pci2: pcie@ef00a000 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0 0xef00a000 0 0x1000>; +- bus-range = <0 255>; +- ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000 +- 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>; +- clock-frequency = <33333333>; +- interrupt-parent = <&mpic>; +- interrupts = <26 2>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 +- 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 +- >; +- pcie@0 { +- reg = <0x0 0x0 0x0 0x0 0x0>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x40000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/xpedite5200.dts b/scripts/dtc/include-prefixes/powerpc/xpedite5200.dts +deleted file mode 100644 +index 840ea84bbb59..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/xpedite5200.dts ++++ /dev/null +@@ -1,465 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2009 Extreme Engineering Solutions, Inc. +- * Based on TQM8548 device tree +- * +- * XPedite5200 PrPMC/XMC module based on MPC8548E +- */ +- +-/dts-v1/; +- +-/ { +- model = "xes,xpedite5200"; +- compatible = "xes,xpedite5200", "xes,MPC8548"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8548@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <0x8000>; // L1, 32K +- i-cache-size = <0x8000>; // L1, 32K +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; // Filled in by U-Boot +- }; +- +- soc@ef000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- ranges = <0x0 0xef000000 0x100000>; +- bus-frequency = <0>; +- compatible = "fsl,mpc8548-immr", "simple-bus"; +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <12>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8548-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8548-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8548-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x80000>; // L2, 512K +- interrupt-parent = <&mpic>; +- interrupts = <16 2>; +- }; +- +- /* On-card I2C */ +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- +- /* +- * Board GPIO: +- * 0: BRD_CFG0 (1: P14 IO present) +- * 1: BRD_CFG1 (1: FP ethernet present) +- * 2: BRD_CFG2 (1: XMC IO present) +- * 3: XMC root complex indicator +- * 4: Flash boot device indicator +- * 5: Flash write protect enable +- * 6: PMC monarch indicator +- * 7: PMC EREADY +- */ +- gpio1: gpio@18 { +- compatible = "nxp,pca9556"; +- reg = <0x18>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- +- /* P14 GPIO */ +- gpio2: gpio@19 { +- compatible = "nxp,pca9556"; +- reg = <0x19>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- +- eeprom@50 { +- compatible = "atmel,at24c16"; +- reg = <0x50>; +- }; +- +- rtc@68 { +- compatible = "st,m41t00", +- "dallas,ds1338"; +- reg = <0x68>; +- }; +- +- dtt@48 { +- compatible = "maxim,max1237"; +- reg = <0x34>; +- }; +- }; +- +- /* Off-card I2C */ +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8548-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8548-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8548-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8548-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- /* eTSEC1: Front panel port 0 */ +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 30 2 34 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy0: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <0x1>; +- }; +- phy1: ethernet-phy@2 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <0x2>; +- }; +- phy2: ethernet-phy@3 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <0x3>; +- }; +- phy3: ethernet-phy@4 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <0x4>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- /* eTSEC2: Front panel port 1 */ +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 2 36 2 40 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- /* eTSEC3: Rear panel port 2 */ +- enet2: ethernet@26000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <2>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x26000 0x1000>; +- ranges = <0x0 0x26000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <31 2 32 2 33 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi2>; +- phy-handle = <&phy2>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- /* eTSEC4: Rear panel port 3 */ +- enet3: ethernet@27000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <3>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x27000 0x1000>; +- ranges = <0x0 0x27000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <37 2 38 2 39 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi3>; +- phy-handle = <&phy3>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi3: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- current-speed = <115200>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- current-speed = <115200>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- global-utilities@e0000 { // global utilities reg +- compatible = "fsl,mpc8548-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +- +- mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- compatible = "chrp,open-pic"; +- device_type = "open-pic"; +- }; +- }; +- +- localbus@ef005000 { +- compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", +- "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- reg = <0xef005000 0x100>; // BRx, ORx, etc. +- interrupt-parent = <&mpic>; +- interrupts = <19 2>; +- +- ranges = < +- 0 0x0 0xfc000000 0x04000000 // NOR boot flash +- 1 0x0 0xf8000000 0x04000000 // NOR expansion flash +- 2 0x0 0xef800000 0x00010000 // NAND CE1 +- 3 0x0 0xef840000 0x00010000 // NAND CE2 +- >; +- +- nor-boot@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0 0x0 0x4000000>; +- bank-width = <2>; +- +- partition@0 { +- label = "Primary OS"; +- reg = <0x00000000 0x180000>; +- }; +- partition@180000 { +- label = "Secondary OS"; +- reg = <0x00180000 0x180000>; +- }; +- partition@300000 { +- label = "User"; +- reg = <0x00300000 0x3c80000>; +- }; +- partition@3f80000 { +- label = "Boot firmware"; +- reg = <0x03f80000 0x80000>; +- }; +- }; +- +- nor-alternate@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <1 0x0 0x4000000>; +- bank-width = <2>; +- +- partition@0 { +- label = "Filesystem"; +- reg = <0x00000000 0x3f80000>; +- }; +- partition@3f80000 { +- label = "Alternate boot firmware"; +- reg = <0x03f80000 0x80000>; +- }; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "xes,address-ctl-nand"; +- reg = <2 0x0 0x10000>; +- cle-line = <0x8>; /* CLE tied to A3 */ +- ale-line = <0x10>; /* ALE tied to A4 */ +- +- /* U-Boot should fix this up */ +- partition@0 { +- label = "NAND Filesystem"; +- reg = <0 0x40000000>; +- }; +- }; +- }; +- +- /* PMC interface */ +- pci0: pci@ef008000 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; +- device_type = "pci"; +- reg = <0xef008000 0x1000>; +- clock-frequency = <33333333>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL */ +- 0xe000 0 0 1 &mpic 2 1 +- 0xe000 0 0 2 &mpic 3 1>; +- +- interrupt-parent = <&mpic>; +- interrupts = <24 2>; +- bus-range = <0 0>; +- ranges = <0x02000000 0 0x80000000 0x80000000 0 0x40000000 +- 0x01000000 0 0x00000000 0xe8000000 0 0x00800000>; +- }; +- +- /* XMC PCIe is not yet enabled in U-Boot on XPedite5200 */ +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/xpedite5200_xmon.dts b/scripts/dtc/include-prefixes/powerpc/xpedite5200_xmon.dts +deleted file mode 100644 +index 449fc1b5dc23..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/xpedite5200_xmon.dts ++++ /dev/null +@@ -1,505 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2009 Extreme Engineering Solutions, Inc. +- * Based on TQM8548 device tree +- * +- * XPedite5200 PrPMC/XMC module based on MPC8548E. This dts is for the +- * xMon boot loader memory map which differs from U-Boot's. +- */ +- +-/dts-v1/; +- +-/ { +- model = "xes,xpedite5200"; +- compatible = "xes,xpedite5200", "xes,MPC8548"; +- #address-cells = <1>; +- #size-cells = <1>; +- form-factor = "PMC/XMC"; +- boot-bank = <0x0>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- ethernet2 = &enet2; +- ethernet3 = &enet3; +- +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- pci1 = &pci1; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8548@0 { +- device_type = "cpu"; +- reg = <0>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <0x8000>; // L1, 32K +- i-cache-size = <0x8000>; // L1, 32K +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0>; // Filled in by boot loader +- }; +- +- soc@ef000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- ranges = <0x0 0xef000000 0x100000>; +- bus-frequency = <0>; +- compatible = "fsl,mpc8548-immr", "simple-bus"; +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <12>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8548-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8548-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8548-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x80000>; // L2, 512K +- interrupt-parent = <&mpic>; +- interrupts = <16 2>; +- }; +- +- /* On-card I2C */ +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- +- /* +- * Board GPIO: +- * 0: BRD_CFG0 (1: P14 IO present) +- * 1: BRD_CFG1 (1: FP ethernet present) +- * 2: BRD_CFG2 (1: XMC IO present) +- * 3: XMC root complex indicator +- * 4: Flash boot device indicator +- * 5: Flash write protect enable +- * 6: PMC monarch indicator +- * 7: PMC EREADY +- */ +- gpio1: gpio@18 { +- compatible = "nxp,pca9556"; +- reg = <0x18>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- +- /* P14 GPIO */ +- gpio2: gpio@19 { +- compatible = "nxp,pca9556"; +- reg = <0x19>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- +- eeprom@50 { +- compatible = "atmel,at24c16"; +- reg = <0x50>; +- }; +- +- rtc@68 { +- compatible = "st,m41t00", +- "dallas,ds1338"; +- reg = <0x68>; +- }; +- +- dtt@48 { +- compatible = "maxim,max1237"; +- reg = <0x34>; +- }; +- }; +- +- /* Off-card I2C */ +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8548-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8548-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8548-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8548-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- /* eTSEC1: Front panel port 0 */ +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 30 2 34 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy0: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <0x1>; +- }; +- phy1: ethernet-phy@2 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <0x2>; +- }; +- phy2: ethernet-phy@3 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <0x3>; +- }; +- phy3: ethernet-phy@4 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <0x4>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- /* eTSEC2: Front panel port 1 */ +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 2 36 2 40 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- /* eTSEC3: Rear panel port 2 */ +- enet2: ethernet@26000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <2>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x26000 0x1000>; +- ranges = <0x0 0x26000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <31 2 32 2 33 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi2>; +- phy-handle = <&phy2>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi2: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- /* eTSEC4: Rear panel port 3 */ +- enet3: ethernet@27000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <3>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x27000 0x1000>; +- ranges = <0x0 0x27000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <37 2 38 2 39 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi3>; +- phy-handle = <&phy3>; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi3: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- current-speed = <9600>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- current-speed = <9600>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- global-utilities@e0000 { // global utilities reg +- compatible = "fsl,mpc8548-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +- +- mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- compatible = "chrp,open-pic"; +- device_type = "open-pic"; +- }; +- }; +- +- localbus@ef005000 { +- compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", +- "simple-bus"; +- #address-cells = <2>; +- #size-cells = <1>; +- reg = <0xef005000 0x100>; // BRx, ORx, etc. +- interrupt-parent = <&mpic>; +- interrupts = <19 2>; +- +- ranges = < +- 0 0x0 0xf8000000 0x08000000 // NOR boot flash +- 1 0x0 0xf0000000 0x08000000 // NOR expansion flash +- 2 0x0 0xe8000000 0x00010000 // NAND CE1 +- 3 0x0 0xe8010000 0x00010000 // NAND CE2 +- >; +- +- nor-boot@0,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0 0x0 0x4000000>; +- bank-width = <2>; +- +- partition@0 { +- label = "Primary OS"; +- reg = <0x00000000 0x180000>; +- }; +- partition@180000 { +- label = "Secondary OS"; +- reg = <0x00180000 0x180000>; +- }; +- partition@300000 { +- label = "User"; +- reg = <0x00300000 0x3c80000>; +- }; +- partition@3f80000 { +- label = "Boot firmware"; +- reg = <0x03f80000 0x80000>; +- }; +- }; +- +- nor-alternate@1,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <1 0x0 0x4000000>; +- bank-width = <2>; +- +- partition@0 { +- label = "Filesystem"; +- reg = <0x00000000 0x3f80000>; +- }; +- partition@3f80000 { +- label = "Alternate boot firmware"; +- reg = <0x03f80000 0x80000>; +- }; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "xes,address-ctl-nand"; +- reg = <2 0x0 0x10000>; +- cle-line = <0x8>; /* CLE tied to A3 */ +- ale-line = <0x10>; /* ALE tied to A4 */ +- +- partition@0 { +- label = "NAND Filesystem"; +- reg = <0 0x40000000>; +- }; +- }; +- }; +- +- /* PMC interface */ +- pci0: pci@ef008000 { +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; +- device_type = "pci"; +- reg = <0xef008000 0x1000>; +- clock-frequency = <33333333>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL */ +- 0xe000 0 0 1 &mpic 2 1 +- 0xe000 0 0 2 &mpic 3 1>; +- +- interrupt-parent = <&mpic>; +- interrupts = <24 2>; +- bus-range = <0 0>; +- ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xd0000000 0 0x01000000>; +- }; +- +- /* XMC PCIe */ +- pci1: pcie@ef00a000 { +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0x00000 0 0 1 &mpic 0 1 +- 0x00000 0 0 2 &mpic 1 1 +- 0x00000 0 0 3 &mpic 2 1 +- 0x00000 0 0 4 &mpic 3 1>; +- +- interrupt-parent = <&mpic>; +- interrupts = <26 2>; +- bus-range = <0 0xff>; +- ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000 +- 0x01000000 0 0x00000000 0xd1000000 0 0x01000000>; +- clock-frequency = <33333333>; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0xef00a000 0x1000>; +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- pcie@0 { +- reg = <0 0 0 0 0>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- ranges = <0x02000000 0 0xc0000000 0x02000000 0 +- 0xc0000000 0 0x20000000 +- 0x01000000 0 0x00000000 0x01000000 0 +- 0x00000000 0 0x08000000>; +- }; +- }; +- +- /* Needed for dtbImage boot wrapper compatibility */ +- chosen { +- stdout-path = &serial0; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/xpedite5301.dts b/scripts/dtc/include-prefixes/powerpc/xpedite5301.dts +deleted file mode 100644 +index 12184e179638..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/xpedite5301.dts ++++ /dev/null +@@ -1,637 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2008 Extreme Engineering Solutions, Inc. +- * Based on MPC8572DS device tree from Freescale Semiconductor, Inc. +- * +- * XPedite5301 PMC/XMC module based on MPC8572E +- */ +- +-/dts-v1/; +-/ { +- model = "xes,xpedite5301"; +- compatible = "xes,xpedite5301", "xes,MPC8572"; +- #address-cells = <2>; +- #size-cells = <2>; +- form-factor = "PMC/XMC"; +- boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */ +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci1 = &pci1; +- pci2 = &pci2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8572@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <0x8000>; // L1, 32K +- i-cache-size = <0x8000>; // L1, 32K +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- next-level-cache = <&L2>; +- }; +- +- PowerPC,8572@1 { +- device_type = "cpu"; +- reg = <0x1>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <0x8000>; // L1, 32K +- i-cache-size = <0x8000>; // L1, 32K +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot +- }; +- +- localbus@ef005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; +- reg = <0 0xef005000 0 0x1000>; +- interrupts = <19 2>; +- interrupt-parent = <&mpic>; +- /* Local bus region mappings */ +- ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */ +- 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */ +- 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */ +- 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */ +- +- nor-boot@0,0 { +- compatible = "amd,s29gl01gp", "cfi-flash"; +- bank-width = <2>; +- reg = <0 0 0x8000000>; /* 128MB */ +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "Primary user space"; +- reg = <0x00000000 0x6f00000>; /* 111 MB */ +- }; +- partition@6f00000 { +- label = "Primary kernel"; +- reg = <0x6f00000 0x1000000>; /* 16 MB */ +- }; +- partition@7f00000 { +- label = "Primary DTB"; +- reg = <0x7f00000 0x40000>; /* 256 KB */ +- }; +- partition@7f40000 { +- label = "Primary U-Boot environment"; +- reg = <0x7f40000 0x40000>; /* 256 KB */ +- }; +- partition@7f80000 { +- label = "Primary U-Boot"; +- reg = <0x7f80000 0x80000>; /* 512 KB */ +- read-only; +- }; +- }; +- +- nor-alternate@1,0 { +- compatible = "amd,s29gl01gp", "cfi-flash"; +- bank-width = <2>; +- //reg = <0xf0000000 0x08000000>; /* 128MB */ +- reg = <1 0 0x8000000>; /* 128MB */ +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "Secondary user space"; +- reg = <0x00000000 0x6f00000>; /* 111 MB */ +- }; +- partition@6f00000 { +- label = "Secondary kernel"; +- reg = <0x6f00000 0x1000000>; /* 16 MB */ +- }; +- partition@7f00000 { +- label = "Secondary DTB"; +- reg = <0x7f00000 0x40000>; /* 256 KB */ +- }; +- partition@7f40000 { +- label = "Secondary U-Boot environment"; +- reg = <0x7f40000 0x40000>; /* 256 KB */ +- }; +- partition@7f80000 { +- label = "Secondary U-Boot"; +- reg = <0x7f80000 0x80000>; /* 512 KB */ +- read-only; +- }; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * Actual part could be ST Micro NAND08GW3B2A (1 GB), +- * Micron MT29F8G08DAA (2x 512 MB), or Micron +- * MT29F16G08FAA (2x 1 GB), depending on the build +- * configuration +- */ +- compatible = "fsl,mpc8572-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <2 0 0x40000>; +- /* U-Boot should fix this up if chip size > 1 GB */ +- partition@0 { +- label = "NAND Filesystem"; +- reg = <0 0x40000000>; +- }; +- }; +- +- }; +- +- soc8572@ef000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,mpc8572-immr", "simple-bus"; +- ranges = <0x0 0 0xef000000 0x100000>; +- bus-frequency = <0>; // Filled out by uboot. +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <12>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8572-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8572-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- memory-controller@6000 { +- compatible = "fsl,mpc8572-memory-controller"; +- reg = <0x6000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8572-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x100000>; // L2, 1M +- interrupt-parent = <&mpic>; +- interrupts = <16 2>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- +- temp-sensor@48 { +- compatible = "dallas,ds1631", "dallas,ds1621"; +- reg = <0x48>; +- }; +- +- temp-sensor@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- +- cpu-supervisor@51 { +- compatible = "dallas,ds4510"; +- reg = <0x51>; +- }; +- +- eeprom@54 { +- compatible = "atmel,at24c128b"; +- reg = <0x54>; +- }; +- +- rtc@68 { +- compatible = "st,m41t00", +- "dallas,ds1338"; +- reg = <0x68>; +- }; +- +- pcie-switch@70 { +- compatible = "plx,pex8518"; +- reg = <0x70>; +- }; +- +- gpio1: gpio@18 { +- compatible = "nxp,pca9557"; +- reg = <0x18>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- +- gpio2: gpio@1c { +- compatible = "nxp,pca9557"; +- reg = <0x1c>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- +- gpio3: gpio@1e { +- compatible = "nxp,pca9557"; +- reg = <0x1e>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- +- gpio4: gpio@1f { +- compatible = "nxp,pca9557"; +- reg = <0x1f>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- }; +- +- dma@c300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; +- reg = <0xc300 0x4>; +- ranges = <0x0 0xc100 0x200>; +- cell-index = <1>; +- dma-channel@0 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <76 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <77 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <78 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <79 2>; +- }; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- /* eTSEC 1 */ +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 30 2 34 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- phy-connection-type = "sgmii"; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy0: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <0x1>; +- }; +- phy1: ethernet-phy@2 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <0x2>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- /* eTSEC 2 */ +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 2 36 2 40 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- phy-connection-type = "sgmii"; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- /* UART0 */ +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- /* UART1 */ +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- global-utilities@e0000 { //global utilities block +- compatible = "fsl,mpc8572-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +- +- msi@41600 { +- compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; +- reg = <0x41600 0x80>; +- msi-available-ranges = <0 0x100>; +- interrupts = < +- 0xe0 0 +- 0xe1 0 +- 0xe2 0 +- 0xe3 0 +- 0xe4 0 +- 0xe5 0 +- 0xe6 0 +- 0xe7 0>; +- interrupt-parent = <&mpic>; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", +- "fsl,sec2.1", "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <45 2 58 2>; +- interrupt-parent = <&mpic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x9fe>; +- fsl,descriptor-types-mask = <0x3ab0ebf>; +- }; +- +- mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- compatible = "chrp,open-pic"; +- device_type = "open-pic"; +- }; +- +- gpio0: gpio@f000 { +- compatible = "fsl,mpc8572-gpio"; +- reg = <0xf000 0x1000>; +- interrupts = <47 2>; +- interrupt-parent = <&mpic>; +- #gpio-cells = <2>; +- gpio-controller; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- heartbeat { +- label = "Heartbeat"; +- gpios = <&gpio0 4 1>; +- linux,default-trigger = "heartbeat"; +- }; +- +- yellow { +- label = "Yellow"; +- gpios = <&gpio0 5 1>; +- }; +- +- red { +- label = "Red"; +- gpios = <&gpio0 6 1>; +- }; +- +- green { +- label = "Green"; +- gpios = <&gpio0 7 1>; +- }; +- }; +- +- /* PME (pattern-matcher) */ +- pme@10000 { +- compatible = "fsl,mpc8572-pme", "pme8572"; +- reg = <0x10000 0x5000>; +- interrupts = <57 2 64 2 65 2 66 2 67 2>; +- interrupt-parent = <&mpic>; +- }; +- +- tlu@2f000 { +- compatible = "fsl,mpc8572-tlu", "fsl_tlu"; +- reg = <0x2f000 0x1000>; +- interrupts = <61 2>; +- interrupt-parent = <&mpic>; +- }; +- +- tlu@15000 { +- compatible = "fsl,mpc8572-tlu", "fsl_tlu"; +- reg = <0x15000 0x1000>; +- interrupts = <75 2>; +- interrupt-parent = <&mpic>; +- }; +- }; +- +- /* +- * PCI Express controller 3 @ ef008000 is not used. +- * This would have been pci0 on other mpc85xx platforms. +- */ +- +- /* PCI Express controller 2, wired to XMC P15 connector */ +- pci1: pcie@ef009000 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0 0xef009000 0 0x1000>; +- bus-range = <0 255>; +- ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000 +- 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>; +- clock-frequency = <33333333>; +- interrupt-parent = <&mpic>; +- interrupts = <25 2>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0x0 0x0 0x0 0x1 &mpic 0x4 0x1 +- 0x0 0x0 0x0 0x2 &mpic 0x5 0x1 +- 0x0 0x0 0x0 0x3 &mpic 0x6 0x1 +- 0x0 0x0 0x0 0x4 &mpic 0x7 0x1 +- >; +- pcie@0 { +- reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- ranges = <0x2000000 0x0 0xc0000000 +- 0x2000000 0x0 0xc0000000 +- 0x0 0x10000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- /* PCI Express controller 1, wired to PEX8112 for PMC interface */ +- pci2: pcie@ef00a000 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0 0xef00a000 0 0x1000>; +- bus-range = <0 255>; +- ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000 +- 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>; +- clock-frequency = <33333333>; +- interrupt-parent = <&mpic>; +- interrupts = <26 2>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 +- 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 +- >; +- pcie@0 { +- reg = <0x0 0x0 0x0 0x0 0x0>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x40000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/xpedite5330.dts b/scripts/dtc/include-prefixes/powerpc/xpedite5330.dts +deleted file mode 100644 +index e8fc90c52ad6..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/xpedite5330.dts ++++ /dev/null +@@ -1,704 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2008 Extreme Engineering Solutions, Inc. +- * Based on MPC8572DS device tree from Freescale Semiconductor, Inc. +- * +- * XPedite5330 3U CompactPCI module based on MPC8572E +- */ +- +-/dts-v1/; +-/ { +- model = "xes,xpedite5330"; +- compatible = "xes,xpedite5330", "xes,MPC8572"; +- #address-cells = <2>; +- #size-cells = <2>; +- form-factor = "3U CompactPCI"; +- boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */ +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci0 = &pci0; +- pci1 = &pci1; +- pci2 = &pci2; +- }; +- +- pmcslots { +- #address-cells = <1>; +- #size-cells = <0>; +- +- pmcslot@0 { +- cell-index = <0>; +- /* +- * boolean properties (true if defined): +- * monarch; +- * module-present; +- */ +- }; +- }; +- +- xmcslots { +- #address-cells = <1>; +- #size-cells = <0>; +- +- xmcslot@0 { +- cell-index = <0>; +- /* +- * boolean properties (true if defined): +- * module-present; +- */ +- }; +- }; +- +- cpci { +- /* +- * boolean properties (true if defined): +- * system-controller; +- */ +- system-controller; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8572@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <0x8000>; // L1, 32K +- i-cache-size = <0x8000>; // L1, 32K +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- next-level-cache = <&L2>; +- }; +- +- PowerPC,8572@1 { +- device_type = "cpu"; +- reg = <0x1>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <0x8000>; // L1, 32K +- i-cache-size = <0x8000>; // L1, 32K +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot +- }; +- +- localbus@ef005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; +- reg = <0 0xef005000 0 0x1000>; +- interrupts = <19 2>; +- interrupt-parent = <&mpic>; +- /* Local bus region mappings */ +- ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */ +- 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */ +- 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */ +- 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */ +- +- nor-boot@0,0 { +- compatible = "amd,s29gl01gp", "cfi-flash"; +- bank-width = <2>; +- reg = <0 0 0x8000000>; /* 128MB */ +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "Primary user space"; +- reg = <0x00000000 0x6f00000>; /* 111 MB */ +- }; +- partition@6f00000 { +- label = "Primary kernel"; +- reg = <0x6f00000 0x1000000>; /* 16 MB */ +- }; +- partition@7f00000 { +- label = "Primary DTB"; +- reg = <0x7f00000 0x40000>; /* 256 KB */ +- }; +- partition@7f40000 { +- label = "Primary U-Boot environment"; +- reg = <0x7f40000 0x40000>; /* 256 KB */ +- }; +- partition@7f80000 { +- label = "Primary U-Boot"; +- reg = <0x7f80000 0x80000>; /* 512 KB */ +- read-only; +- }; +- }; +- +- nor-alternate@1,0 { +- compatible = "amd,s29gl01gp", "cfi-flash"; +- bank-width = <2>; +- //reg = <0xf0000000 0x08000000>; /* 128MB */ +- reg = <1 0 0x8000000>; /* 128MB */ +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "Secondary user space"; +- reg = <0x00000000 0x6f00000>; /* 111 MB */ +- }; +- partition@6f00000 { +- label = "Secondary kernel"; +- reg = <0x6f00000 0x1000000>; /* 16 MB */ +- }; +- partition@7f00000 { +- label = "Secondary DTB"; +- reg = <0x7f00000 0x40000>; /* 256 KB */ +- }; +- partition@7f40000 { +- label = "Secondary U-Boot environment"; +- reg = <0x7f40000 0x40000>; /* 256 KB */ +- }; +- partition@7f80000 { +- label = "Secondary U-Boot"; +- reg = <0x7f80000 0x80000>; /* 512 KB */ +- read-only; +- }; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * Actual part could be ST Micro NAND08GW3B2A (1 GB), +- * Micron MT29F8G08DAA (2x 512 MB), or Micron +- * MT29F16G08FAA (2x 1 GB), depending on the build +- * configuration +- */ +- compatible = "fsl,mpc8572-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <2 0 0x40000>; +- /* U-Boot should fix this up if chip size > 1 GB */ +- partition@0 { +- label = "NAND Filesystem"; +- reg = <0 0x40000000>; +- }; +- }; +- +- }; +- +- soc8572@ef000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,mpc8572-immr", "simple-bus"; +- ranges = <0x0 0 0xef000000 0x100000>; +- bus-frequency = <0>; // Filled out by uboot. +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <12>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8572-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8572-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- memory-controller@6000 { +- compatible = "fsl,mpc8572-memory-controller"; +- reg = <0x6000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8572-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x100000>; // L2, 1M +- interrupt-parent = <&mpic>; +- interrupts = <16 2>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- +- temp-sensor@48 { +- compatible = "dallas,ds1631", "dallas,ds1621"; +- reg = <0x48>; +- }; +- +- temp-sensor@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- +- cpu-supervisor@51 { +- compatible = "dallas,ds4510"; +- reg = <0x51>; +- }; +- +- eeprom@54 { +- compatible = "atmel,at24c128b"; +- reg = <0x54>; +- }; +- +- rtc@68 { +- compatible = "st,m41t00", +- "dallas,ds1338"; +- reg = <0x68>; +- }; +- +- pcie-switch@70 { +- compatible = "plx,pex8518"; +- reg = <0x70>; +- }; +- +- gpio1: gpio@18 { +- compatible = "nxp,pca9557"; +- reg = <0x18>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- +- gpio2: gpio@1c { +- compatible = "nxp,pca9557"; +- reg = <0x1c>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- +- gpio3: gpio@1e { +- compatible = "nxp,pca9557"; +- reg = <0x1e>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- +- gpio4: gpio@1f { +- compatible = "nxp,pca9557"; +- reg = <0x1f>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- }; +- +- dma@c300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; +- reg = <0xc300 0x4>; +- ranges = <0x0 0xc100 0x200>; +- cell-index = <1>; +- dma-channel@0 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <76 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <77 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <78 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <79 2>; +- }; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- /* eTSEC 1 */ +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 30 2 34 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- phy-connection-type = "sgmii"; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy0: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <0x1>; +- }; +- phy1: ethernet-phy@2 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <0x2>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- /* eTSEC 2 */ +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 2 36 2 40 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- phy-connection-type = "sgmii"; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- /* UART0 */ +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- /* UART1 */ +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- global-utilities@e0000 { //global utilities block +- compatible = "fsl,mpc8572-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +- +- msi@41600 { +- compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; +- reg = <0x41600 0x80>; +- msi-available-ranges = <0 0x100>; +- interrupts = < +- 0xe0 0 +- 0xe1 0 +- 0xe2 0 +- 0xe3 0 +- 0xe4 0 +- 0xe5 0 +- 0xe6 0 +- 0xe7 0>; +- interrupt-parent = <&mpic>; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", +- "fsl,sec2.1", "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <45 2 58 2>; +- interrupt-parent = <&mpic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x9fe>; +- fsl,descriptor-types-mask = <0x3ab0ebf>; +- }; +- +- mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- compatible = "chrp,open-pic"; +- device_type = "open-pic"; +- }; +- +- gpio0: gpio@f000 { +- compatible = "fsl,mpc8572-gpio"; +- reg = <0xf000 0x1000>; +- interrupts = <47 2>; +- interrupt-parent = <&mpic>; +- #gpio-cells = <2>; +- gpio-controller; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- heartbeat { +- label = "Heartbeat"; +- gpios = <&gpio0 4 1>; +- linux,default-trigger = "heartbeat"; +- }; +- +- yellow { +- label = "Yellow"; +- gpios = <&gpio0 5 1>; +- }; +- +- red { +- label = "Red"; +- gpios = <&gpio0 6 1>; +- }; +- +- green { +- label = "Green"; +- gpios = <&gpio0 7 1>; +- }; +- }; +- +- /* PME (pattern-matcher) */ +- pme@10000 { +- compatible = "fsl,mpc8572-pme", "pme8572"; +- reg = <0x10000 0x5000>; +- interrupts = <57 2 64 2 65 2 66 2 67 2>; +- interrupt-parent = <&mpic>; +- }; +- +- tlu@2f000 { +- compatible = "fsl,mpc8572-tlu", "fsl_tlu"; +- reg = <0x2f000 0x1000>; +- interrupts = <61 2>; +- interrupt-parent = <&mpic>; +- }; +- +- tlu@15000 { +- compatible = "fsl,mpc8572-tlu", "fsl_tlu"; +- reg = <0x15000 0x1000>; +- interrupts = <75 2>; +- interrupt-parent = <&mpic>; +- }; +- }; +- +- /* PCI Express controller 3 - CompactPCI bus via PEX8112 bridge */ +- pci0: pcie@ef008000 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0 0xef008000 0 0x1000>; +- bus-range = <0 255>; +- ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x10000000 +- 0x1000000 0x0 0x00000000 0 0xe9000000 0x0 0x10000>; +- clock-frequency = <33333333>; +- interrupt-parent = <&mpic>; +- interrupts = <24 2>; +- interrupt-map-mask = <0xff00 0x0 0x0 0x7>; +- interrupt-map = < +- 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 +- 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 +- >; +- pcie@0 { +- reg = <0x0 0x0 0x0 0x0 0x0>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- ranges = <0x02000000 0x0 0xe0000000 +- 0x02000000 0x0 0xe0000000 +- 0x0 0x10000000 +- +- 0x01000000 0x0 0x0 +- 0x01000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- /* PCI Express controller 2, PMC module via PEX8112 bridge */ +- pci1: pcie@ef009000 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0 0xef009000 0 0x1000>; +- bus-range = <0 255>; +- ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000 +- 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x10000>; +- clock-frequency = <33333333>; +- interrupt-parent = <&mpic>; +- interrupts = <25 2>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0x0 0x0 0x0 0x1 &mpic 0x4 0x1 +- 0x0 0x0 0x0 0x2 &mpic 0x5 0x1 +- 0x0 0x0 0x0 0x3 &mpic 0x6 0x1 +- 0x0 0x0 0x0 0x4 &mpic 0x7 0x1 +- >; +- pcie@0 { +- reg = <0x0 0x0 0x0 0x0 0x0>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- ranges = <0x2000000 0x0 0xc0000000 +- 0x2000000 0x0 0xc0000000 +- 0x0 0x10000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- /* PCI Express controller 1, XMC P15 */ +- pci2: pcie@ef00a000 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0 0xef00a000 0 0x1000>; +- bus-range = <0 255>; +- ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000 +- 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>; +- clock-frequency = <33333333>; +- interrupt-parent = <&mpic>; +- interrupts = <26 2>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 +- 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 +- >; +- pcie@0 { +- reg = <0x0 0x0 0x0 0x0 0x0>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x40000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/xpedite5370.dts b/scripts/dtc/include-prefixes/powerpc/xpedite5370.dts +deleted file mode 100644 +index 2b5aa2f3a709..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/xpedite5370.dts ++++ /dev/null +@@ -1,635 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (C) 2008 Extreme Engineering Solutions, Inc. +- * Based on MPC8572DS device tree from Freescale Semiconductor, Inc. +- * +- * XPedite5370 3U VPX single-board computer based on MPC8572E +- */ +- +-/dts-v1/; +-/ { +- model = "xes,xpedite5370"; +- compatible = "xes,xpedite5370", "xes,MPC8572"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- ethernet0 = &enet0; +- ethernet1 = &enet1; +- serial0 = &serial0; +- serial1 = &serial1; +- pci1 = &pci1; +- pci2 = &pci2; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- PowerPC,8572@0 { +- device_type = "cpu"; +- reg = <0x0>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <0x8000>; // L1, 32K +- i-cache-size = <0x8000>; // L1, 32K +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- next-level-cache = <&L2>; +- }; +- +- PowerPC,8572@1 { +- device_type = "cpu"; +- reg = <0x1>; +- d-cache-line-size = <32>; // 32 bytes +- i-cache-line-size = <32>; // 32 bytes +- d-cache-size = <0x8000>; // L1, 32K +- i-cache-size = <0x8000>; // L1, 32K +- timebase-frequency = <0>; +- bus-frequency = <0>; +- clock-frequency = <0>; +- next-level-cache = <&L2>; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot +- }; +- +- localbus@ef005000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; +- reg = <0 0xef005000 0 0x1000>; +- interrupts = <19 2>; +- interrupt-parent = <&mpic>; +- /* Local bus region mappings */ +- ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */ +- 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */ +- 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */ +- 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */ +- +- nor-boot@0,0 { +- compatible = "amd,s29gl01gp", "cfi-flash"; +- bank-width = <2>; +- reg = <0 0 0x8000000>; /* 128MB */ +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "Primary user space"; +- reg = <0x00000000 0x6f00000>; /* 111 MB */ +- }; +- partition@6f00000 { +- label = "Primary kernel"; +- reg = <0x6f00000 0x1000000>; /* 16 MB */ +- }; +- partition@7f00000 { +- label = "Primary DTB"; +- reg = <0x7f00000 0x40000>; /* 256 KB */ +- }; +- partition@7f40000 { +- label = "Primary U-Boot environment"; +- reg = <0x7f40000 0x40000>; /* 256 KB */ +- }; +- partition@7f80000 { +- label = "Primary U-Boot"; +- reg = <0x7f80000 0x80000>; /* 512 KB */ +- read-only; +- }; +- }; +- +- nor-alternate@1,0 { +- compatible = "amd,s29gl01gp", "cfi-flash"; +- bank-width = <2>; +- //reg = <0xf0000000 0x08000000>; /* 128MB */ +- reg = <1 0 0x8000000>; /* 128MB */ +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "Secondary user space"; +- reg = <0x00000000 0x6f00000>; /* 111 MB */ +- }; +- partition@6f00000 { +- label = "Secondary kernel"; +- reg = <0x6f00000 0x1000000>; /* 16 MB */ +- }; +- partition@7f00000 { +- label = "Secondary DTB"; +- reg = <0x7f00000 0x40000>; /* 256 KB */ +- }; +- partition@7f40000 { +- label = "Secondary U-Boot environment"; +- reg = <0x7f40000 0x40000>; /* 256 KB */ +- }; +- partition@7f80000 { +- label = "Secondary U-Boot"; +- reg = <0x7f80000 0x80000>; /* 512 KB */ +- read-only; +- }; +- }; +- +- nand@2,0 { +- #address-cells = <1>; +- #size-cells = <1>; +- /* +- * Actual part could be ST Micro NAND08GW3B2A (1 GB), +- * Micron MT29F8G08DAA (2x 512 MB), or Micron +- * MT29F16G08FAA (2x 1 GB), depending on the build +- * configuration +- */ +- compatible = "fsl,mpc8572-fcm-nand", +- "fsl,elbc-fcm-nand"; +- reg = <2 0 0x40000>; +- /* U-Boot should fix this up if chip size > 1 GB */ +- partition@0 { +- label = "NAND Filesystem"; +- reg = <0 0x40000000>; +- }; +- }; +- +- }; +- +- soc8572@ef000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- device_type = "soc"; +- compatible = "fsl,mpc8572-immr", "simple-bus"; +- ranges = <0x0 0 0xef000000 0x100000>; +- bus-frequency = <0>; // Filled out by uboot. +- +- ecm-law@0 { +- compatible = "fsl,ecm-law"; +- reg = <0x0 0x1000>; +- fsl,num-laws = <12>; +- }; +- +- ecm@1000 { +- compatible = "fsl,mpc8572-ecm", "fsl,ecm"; +- reg = <0x1000 0x1000>; +- interrupts = <17 2>; +- interrupt-parent = <&mpic>; +- }; +- +- memory-controller@2000 { +- compatible = "fsl,mpc8572-memory-controller"; +- reg = <0x2000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- memory-controller@6000 { +- compatible = "fsl,mpc8572-memory-controller"; +- reg = <0x6000 0x1000>; +- interrupt-parent = <&mpic>; +- interrupts = <18 2>; +- }; +- +- L2: l2-cache-controller@20000 { +- compatible = "fsl,mpc8572-l2-cache-controller"; +- reg = <0x20000 0x1000>; +- cache-line-size = <32>; // 32 bytes +- cache-size = <0x100000>; // L2, 1M +- interrupt-parent = <&mpic>; +- interrupts = <16 2>; +- }; +- +- i2c@3000 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <0>; +- compatible = "fsl-i2c"; +- reg = <0x3000 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- +- temp-sensor@48 { +- compatible = "dallas,ds1631", "dallas,ds1621"; +- reg = <0x48>; +- }; +- +- temp-sensor@4c { +- compatible = "adi,adt7461"; +- reg = <0x4c>; +- }; +- +- cpu-supervisor@51 { +- compatible = "dallas,ds4510"; +- reg = <0x51>; +- }; +- +- eeprom@54 { +- compatible = "atmel,at24c128b"; +- reg = <0x54>; +- }; +- +- rtc@68 { +- compatible = "st,m41t00", +- "dallas,ds1338"; +- reg = <0x68>; +- }; +- +- pcie-switch@70 { +- compatible = "plx,pex8518"; +- reg = <0x70>; +- }; +- +- gpio1: gpio@18 { +- compatible = "nxp,pca9557"; +- reg = <0x18>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- +- gpio2: gpio@1c { +- compatible = "nxp,pca9557"; +- reg = <0x1c>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- +- gpio3: gpio@1e { +- compatible = "nxp,pca9557"; +- reg = <0x1e>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- +- gpio4: gpio@1f { +- compatible = "nxp,pca9557"; +- reg = <0x1f>; +- #gpio-cells = <2>; +- gpio-controller; +- polarity = <0x00>; +- }; +- }; +- +- i2c@3100 { +- #address-cells = <1>; +- #size-cells = <0>; +- cell-index = <1>; +- compatible = "fsl-i2c"; +- reg = <0x3100 0x100>; +- interrupts = <43 2>; +- interrupt-parent = <&mpic>; +- dfsrr; +- }; +- +- dma@c300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; +- reg = <0xc300 0x4>; +- ranges = <0x0 0xc100 0x200>; +- cell-index = <1>; +- dma-channel@0 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <76 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <77 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <78 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <79 2>; +- }; +- }; +- +- dma@21300 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; +- reg = <0x21300 0x4>; +- ranges = <0x0 0x21100 0x200>; +- cell-index = <0>; +- dma-channel@0 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x0 0x80>; +- cell-index = <0>; +- interrupt-parent = <&mpic>; +- interrupts = <20 2>; +- }; +- dma-channel@80 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x80 0x80>; +- cell-index = <1>; +- interrupt-parent = <&mpic>; +- interrupts = <21 2>; +- }; +- dma-channel@100 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x100 0x80>; +- cell-index = <2>; +- interrupt-parent = <&mpic>; +- interrupts = <22 2>; +- }; +- dma-channel@180 { +- compatible = "fsl,mpc8572-dma-channel", +- "fsl,eloplus-dma-channel"; +- reg = <0x180 0x80>; +- cell-index = <3>; +- interrupt-parent = <&mpic>; +- interrupts = <23 2>; +- }; +- }; +- +- /* eTSEC 1 */ +- enet0: ethernet@24000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <0>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x24000 0x1000>; +- ranges = <0x0 0x24000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <29 2 30 2 34 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi0>; +- phy-handle = <&phy0>; +- phy-connection-type = "sgmii"; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-mdio"; +- reg = <0x520 0x20>; +- +- phy0: ethernet-phy@1 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <0x1>; +- }; +- phy1: ethernet-phy@2 { +- interrupt-parent = <&mpic>; +- interrupts = <8 1>; +- reg = <0x2>; +- }; +- tbi0: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- /* eTSEC 2 */ +- enet1: ethernet@25000 { +- #address-cells = <1>; +- #size-cells = <1>; +- cell-index = <1>; +- device_type = "network"; +- model = "eTSEC"; +- compatible = "gianfar"; +- reg = <0x25000 0x1000>; +- ranges = <0x0 0x25000 0x1000>; +- local-mac-address = [ 00 00 00 00 00 00 ]; +- interrupts = <35 2 36 2 40 2>; +- interrupt-parent = <&mpic>; +- tbi-handle = <&tbi1>; +- phy-handle = <&phy1>; +- phy-connection-type = "sgmii"; +- +- mdio@520 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "fsl,gianfar-tbi"; +- reg = <0x520 0x20>; +- +- tbi1: tbi-phy@11 { +- reg = <0x11>; +- device_type = "tbi-phy"; +- }; +- }; +- }; +- +- /* UART0 */ +- serial0: serial@4500 { +- cell-index = <0>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4500 0x100>; +- clock-frequency = <0>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- /* UART1 */ +- serial1: serial@4600 { +- cell-index = <1>; +- device_type = "serial"; +- compatible = "fsl,ns16550", "ns16550"; +- reg = <0x4600 0x100>; +- clock-frequency = <0>; +- interrupts = <42 2>; +- interrupt-parent = <&mpic>; +- }; +- +- global-utilities@e0000 { //global utilities block +- compatible = "fsl,mpc8572-guts"; +- reg = <0xe0000 0x1000>; +- fsl,has-rstcr; +- }; +- +- msi@41600 { +- compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; +- reg = <0x41600 0x80>; +- msi-available-ranges = <0 0x100>; +- interrupts = < +- 0xe0 0 +- 0xe1 0 +- 0xe2 0 +- 0xe3 0 +- 0xe4 0 +- 0xe5 0 +- 0xe6 0 +- 0xe7 0>; +- interrupt-parent = <&mpic>; +- }; +- +- crypto@30000 { +- compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", +- "fsl,sec2.1", "fsl,sec2.0"; +- reg = <0x30000 0x10000>; +- interrupts = <45 2 58 2>; +- interrupt-parent = <&mpic>; +- fsl,num-channels = <4>; +- fsl,channel-fifo-len = <24>; +- fsl,exec-units-mask = <0x9fe>; +- fsl,descriptor-types-mask = <0x3ab0ebf>; +- }; +- +- mpic: pic@40000 { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x40000 0x40000>; +- compatible = "chrp,open-pic"; +- device_type = "open-pic"; +- }; +- +- gpio0: gpio@f000 { +- compatible = "fsl,mpc8572-gpio"; +- reg = <0xf000 0x1000>; +- interrupts = <47 2>; +- interrupt-parent = <&mpic>; +- #gpio-cells = <2>; +- gpio-controller; +- }; +- +- gpio-leds { +- compatible = "gpio-leds"; +- +- heartbeat { +- label = "Heartbeat"; +- gpios = <&gpio0 4 1>; +- linux,default-trigger = "heartbeat"; +- }; +- +- yellow { +- label = "Yellow"; +- gpios = <&gpio0 5 1>; +- }; +- +- red { +- label = "Red"; +- gpios = <&gpio0 6 1>; +- }; +- +- green { +- label = "Green"; +- gpios = <&gpio0 7 1>; +- }; +- }; +- +- /* PME (pattern-matcher) */ +- pme@10000 { +- compatible = "fsl,mpc8572-pme", "pme8572"; +- reg = <0x10000 0x5000>; +- interrupts = <57 2 64 2 65 2 66 2 67 2>; +- interrupt-parent = <&mpic>; +- }; +- +- tlu@2f000 { +- compatible = "fsl,mpc8572-tlu", "fsl_tlu"; +- reg = <0x2f000 0x1000>; +- interrupts = <61 2>; +- interrupt-parent = <&mpic>; +- }; +- +- tlu@15000 { +- compatible = "fsl,mpc8572-tlu", "fsl_tlu"; +- reg = <0x15000 0x1000>; +- interrupts = <75 2>; +- interrupt-parent = <&mpic>; +- }; +- }; +- +- /* +- * PCI Express controller 3 @ ef008000 is not used. +- * This would have been pci0 on other mpc85xx platforms. +- */ +- +- /* PCI Express controller 2, wired to VPX P1,P2 backplane */ +- pci1: pcie@ef009000 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0 0xef009000 0 0x1000>; +- bus-range = <0 255>; +- ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000 +- 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>; +- clock-frequency = <33333333>; +- interrupt-parent = <&mpic>; +- interrupts = <25 2>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0x0 0x0 0x0 0x1 &mpic 0x4 0x1 +- 0x0 0x0 0x0 0x2 &mpic 0x5 0x1 +- 0x0 0x0 0x0 0x3 &mpic 0x6 0x1 +- 0x0 0x0 0x0 0x4 &mpic 0x7 0x1 +- >; +- pcie@0 { +- reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- ranges = <0x2000000 0x0 0xc0000000 +- 0x2000000 0x0 0xc0000000 +- 0x0 0x10000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +- +- /* PCI Express controller 1, wired to PEX8518 PCIe switch */ +- pci2: pcie@ef00a000 { +- compatible = "fsl,mpc8548-pcie"; +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- reg = <0 0xef00a000 0 0x1000>; +- bus-range = <0 255>; +- ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000 +- 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>; +- clock-frequency = <33333333>; +- interrupt-parent = <&mpic>; +- interrupts = <26 2>; +- interrupt-map-mask = <0xf800 0x0 0x0 0x7>; +- interrupt-map = < +- /* IDSEL 0x0 */ +- 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 +- 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 +- 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 +- 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 +- >; +- pcie@0 { +- reg = <0x0 0x0 0x0 0x0 0x0>; +- #size-cells = <2>; +- #address-cells = <3>; +- device_type = "pci"; +- ranges = <0x2000000 0x0 0x80000000 +- 0x2000000 0x0 0x80000000 +- 0x0 0x40000000 +- +- 0x1000000 0x0 0x0 +- 0x1000000 0x0 0x0 +- 0x0 0x100000>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/powerpc/yosemite.dts b/scripts/dtc/include-prefixes/powerpc/yosemite.dts +deleted file mode 100644 +index 56508785ce13..000000000000 +--- a/scripts/dtc/include-prefixes/powerpc/yosemite.dts ++++ /dev/null +@@ -1,332 +0,0 @@ +-/* +- * Device Tree Source for AMCC Yosemite +- * +- * Copyright 2008 IBM Corp. +- * Josh Boyer +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without +- * any warranty of any kind, whether express or implied. +- */ +- +-/dts-v1/; +- +-/ { +- #address-cells = <2>; +- #size-cells = <1>; +- model = "amcc,yosemite"; +- compatible = "amcc,yosemite"; +- dcr-parent = <&{/cpus/cpu@0}>; +- +- aliases { +- ethernet0 = &EMAC0; +- ethernet1 = &EMAC1; +- serial0 = &UART0; +- serial1 = &UART1; +- serial2 = &UART2; +- serial3 = &UART3; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- model = "PowerPC,440EP"; +- reg = <0x00000000>; +- clock-frequency = <0>; /* Filled in by zImage */ +- timebase-frequency = <0>; /* Filled in by zImage */ +- i-cache-line-size = <32>; +- d-cache-line-size = <32>; +- i-cache-size = <32768>; +- d-cache-size = <32768>; +- dcr-controller; +- dcr-access-method = "native"; +- }; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */ +- }; +- +- UIC0: interrupt-controller0 { +- compatible = "ibm,uic-440ep","ibm,uic"; +- interrupt-controller; +- cell-index = <0>; +- dcr-reg = <0x0c0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- }; +- +- UIC1: interrupt-controller1 { +- compatible = "ibm,uic-440ep","ibm,uic"; +- interrupt-controller; +- cell-index = <1>; +- dcr-reg = <0x0d0 0x009>; +- #address-cells = <0>; +- #size-cells = <0>; +- #interrupt-cells = <2>; +- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ +- interrupt-parent = <&UIC0>; +- }; +- +- SDR0: sdr { +- compatible = "ibm,sdr-440ep"; +- dcr-reg = <0x00e 0x002>; +- }; +- +- CPR0: cpr { +- compatible = "ibm,cpr-440ep"; +- dcr-reg = <0x00c 0x002>; +- }; +- +- plb { +- compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4"; +- #address-cells = <2>; +- #size-cells = <1>; +- ranges; +- clock-frequency = <0>; /* Filled in by zImage */ +- +- SDRAM0: sdram { +- compatible = "ibm,sdram-440ep", "ibm,sdram-405gp"; +- dcr-reg = <0x010 0x002>; +- }; +- +- DMA0: dma { +- compatible = "ibm,dma-440ep", "ibm,dma-440gp"; +- dcr-reg = <0x100 0x027>; +- }; +- +- MAL0: mcmal { +- compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal"; +- dcr-reg = <0x180 0x062>; +- num-tx-chans = <4>; +- num-rx-chans = <2>; +- interrupt-parent = <&MAL0>; +- interrupts = <0x0 0x1 0x2 0x3 0x4>; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- #size-cells = <0>; +- interrupt-map = ; +- }; +- +- POB0: opb { +- compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb"; +- #address-cells = <1>; +- #size-cells = <1>; +- /* Bamboo is oddball in the 44x world and doesn't use the ERPN +- * bits. +- */ +- ranges = <0x00000000 0x00000000 0x00000000 0x80000000 +- 0x80000000 0x00000000 0x80000000 0x80000000>; +- interrupt-parent = <&UIC1>; +- interrupts = <0x7 0x4>; +- clock-frequency = <0>; /* Filled in by zImage */ +- +- EBC0: ebc { +- compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc"; +- dcr-reg = <0x012 0x002>; +- #address-cells = <2>; +- #size-cells = <1>; +- clock-frequency = <0>; /* Filled in by zImage */ +- interrupts = <0x5 0x1>; +- interrupt-parent = <&UIC1>; +- +- nor_flash@0,0 { +- compatible = "amd,s29gl256n", "cfi-flash"; +- bank-width = <2>; +- reg = <0x00000000 0x00000000 0x04000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- partition@0 { +- label = "kernel"; +- reg = <0x00000000 0x001e0000>; +- }; +- partition@1e0000 { +- label = "dtb"; +- reg = <0x001e0000 0x00020000>; +- }; +- partition@200000 { +- label = "ramdisk"; +- reg = <0x00200000 0x01400000>; +- }; +- partition@1600000 { +- label = "jffs2"; +- reg = <0x01600000 0x00400000>; +- }; +- partition@1a00000 { +- label = "user"; +- reg = <0x01a00000 0x02540000>; +- }; +- partition@3f40000 { +- label = "env"; +- reg = <0x03f40000 0x00040000>; +- }; +- partition@3f80000 { +- label = "u-boot"; +- reg = <0x03f80000 0x00080000>; +- }; +- }; +- }; +- +- UART0: serial@ef600300 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600300 0x00000008>; +- virtual-reg = <0xef600300>; +- clock-frequency = <0>; /* Filled in by zImage */ +- current-speed = <115200>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x0 0x4>; +- }; +- +- UART1: serial@ef600400 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600400 0x00000008>; +- virtual-reg = <0xef600400>; +- clock-frequency = <0>; +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x1 0x4>; +- }; +- +- UART2: serial@ef600500 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600500 0x00000008>; +- virtual-reg = <0xef600500>; +- clock-frequency = <0>; +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x3 0x4>; +- status = "disabled"; +- }; +- +- UART3: serial@ef600600 { +- device_type = "serial"; +- compatible = "ns16550"; +- reg = <0xef600600 0x00000008>; +- virtual-reg = <0xef600600>; +- clock-frequency = <0>; +- current-speed = <0>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x4 0x4>; +- status = "disabled"; +- }; +- +- IIC0: i2c@ef600700 { +- compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; +- reg = <0xef600700 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x2 0x4>; +- }; +- +- IIC1: i2c@ef600800 { +- compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; +- reg = <0xef600800 0x00000014>; +- interrupt-parent = <&UIC0>; +- interrupts = <0x7 0x4>; +- }; +- +- spi@ef600900 { +- compatible = "amcc,spi-440ep"; +- reg = <0xef600900 0x00000006>; +- interrupts = <0x8 0x4>; +- interrupt-parent = <&UIC0>; +- }; +- +- ZMII0: emac-zmii@ef600d00 { +- compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii"; +- reg = <0xef600d00 0x0000000c>; +- }; +- +- EMAC0: ethernet@ef600e00 { +- device_type = "network"; +- compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; +- interrupt-parent = <&UIC1>; +- interrupts = <0x1c 0x4 0x1d 0x4>; +- reg = <0xef600e00 0x00000070>; +- local-mac-address = [000000000000]; +- mal-device = <&MAL0>; +- mal-tx-channel = <0 1>; +- mal-rx-channel = <0>; +- cell-index = <0>; +- max-frame-size = <1500>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "rmii"; +- phy-map = <0x00000000>; +- zmii-device = <&ZMII0>; +- zmii-channel = <0>; +- }; +- +- EMAC1: ethernet@ef600f00 { +- device_type = "network"; +- compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; +- interrupt-parent = <&UIC1>; +- interrupts = <0x1e 0x4 0x1f 0x4>; +- reg = <0xef600f00 0x00000070>; +- local-mac-address = [000000000000]; +- mal-device = <&MAL0>; +- mal-tx-channel = <2 3>; +- mal-rx-channel = <1>; +- cell-index = <1>; +- max-frame-size = <1500>; +- rx-fifo-size = <4096>; +- tx-fifo-size = <2048>; +- phy-mode = "rmii"; +- phy-map = <0x00000000>; +- zmii-device = <&ZMII0>; +- zmii-channel = <1>; +- }; +- +- usb@ef601000 { +- compatible = "ohci-be"; +- reg = <0xef601000 0x00000080>; +- interrupts = <0x8 0x4 0x9 0x4>; +- interrupt-parent = < &UIC1 >; +- }; +- }; +- +- PCI0: pci@ec000000 { +- device_type = "pci"; +- #interrupt-cells = <1>; +- #size-cells = <2>; +- #address-cells = <3>; +- compatible = "ibm,plb440ep-pci", "ibm,plb-pci"; +- primary; +- reg = <0x00000000 0xeec00000 0x00000008 /* Config space access */ +- 0x00000000 0xeed00000 0x00000004 /* IACK */ +- 0x00000000 0xeed00000 0x00000004 /* Special cycle */ +- 0x00000000 0xef400000 0x00000040>; /* Internal registers */ +- +- /* Outbound ranges, one memory and one IO, +- * later cannot be changed. Chip supports a second +- * IO range but we don't use it for now +- */ +- ranges = <0x02000000 0x00000000 0xa0000000 0x00000000 0xa0000000 0x00000000 0x20000000 +- 0x01000000 0x00000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>; +- +- /* Inbound 2GB range starting at 0 */ +- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; +- +- interrupt-map-mask = <0xf800 0x0 0x0 0x0>; +- interrupt-map = < +- /* IDSEL 12 */ +- 0x6000 0x0 0x0 0x0 &UIC0 0x19 0x8 +- >; +- }; +- }; +- +- chosen { +- stdout-path = "/plb/opb/serial@ef600300"; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/sh b/scripts/dtc/include-prefixes/sh +new file mode 120000 +index 000000000000..67d37808c599 +--- /dev/null ++++ b/scripts/dtc/include-prefixes/sh +@@ -0,0 +1 @@ ++../../../arch/sh/boot/dts +\ No newline at end of file +diff --git a/scripts/dtc/include-prefixes/sh/Makefile b/scripts/dtc/include-prefixes/sh/Makefile +deleted file mode 100644 +index c17d65b82abe..000000000000 +--- a/scripts/dtc/include-prefixes/sh/Makefile ++++ /dev/null +@@ -1,4 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0-only +-ifneq ($(CONFIG_BUILTIN_DTB_SOURCE),"") +-obj-$(CONFIG_USE_BUILTIN_DTB) += $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_SOURCE)).dtb.o +-endif +diff --git a/scripts/dtc/include-prefixes/sh/j2_mimas_v2.dts b/scripts/dtc/include-prefixes/sh/j2_mimas_v2.dts +deleted file mode 100644 +index 9f4742fab329..000000000000 +--- a/scripts/dtc/include-prefixes/sh/j2_mimas_v2.dts ++++ /dev/null +@@ -1,97 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-/ { +- compatible = "jcore,j2-soc"; +- model = "J2 FPGA SoC on Mimas v2 board"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- interrupt-parent = <&aic>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "jcore,j2"; +- reg = <0>; +- clock-frequency = <50000000>; +- d-cache-size = <8192>; +- i-cache-size = <8192>; +- d-cache-block-size = <16>; +- i-cache-block-size = <16>; +- }; +- }; +- +- memory@10000000 { +- device_type = "memory"; +- reg = <0x10000000 0x4000000>; +- }; +- +- aliases { +- serial0 = &uart0; +- spi0 = &spi0; +- }; +- +- chosen { +- stdout-path = "serial0"; +- }; +- +- soc@abcd0000 { +- compatible = "simple-bus"; +- ranges = <0 0xabcd0000 0x100000>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- aic: interrupt-controller@200 { +- compatible = "jcore,aic1"; +- reg = <0x200 0x10>; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- +- cache-controller@c0 { +- compatible = "jcore,cache"; +- reg = <0xc0 4>; +- }; +- +- timer@200 { +- compatible = "jcore,pit"; +- reg = <0x200 0x30>; +- interrupts = <0x48>; +- }; +- +- spi0: spi@40 { +- compatible = "jcore,spi2"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- spi-max-frequency = <25000000>; +- +- reg = <0x40 0x8>; +- +- sdcard@0 { +- compatible = "mmc-spi-slot"; +- reg = <0>; +- spi-max-frequency = <25000000>; +- voltage-ranges = <3200 3400>; +- mode = <0>; +- }; +- }; +- +- uart0: serial@100 { +- clock-frequency = <125000000>; +- compatible = "xlnx,xps-uartlite-1.00.a"; +- current-speed = <19200>; +- device_type = "serial"; +- interrupts = <0x12>; +- port-number = <0>; +- reg = <0x100 0x10>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/xtensa b/scripts/dtc/include-prefixes/xtensa +new file mode 120000 +index 000000000000..d1eaf6ec7a2b +--- /dev/null ++++ b/scripts/dtc/include-prefixes/xtensa +@@ -0,0 +1 @@ ++../../../arch/xtensa/boot/dts +\ No newline at end of file +diff --git a/scripts/dtc/include-prefixes/xtensa/Makefile b/scripts/dtc/include-prefixes/xtensa/Makefile +deleted file mode 100644 +index 0b8d00cdae7c..000000000000 +--- a/scripts/dtc/include-prefixes/xtensa/Makefile ++++ /dev/null +@@ -1,17 +0,0 @@ +-# +-# arch/xtensa/boot/dts/Makefile +-# +-# This file is subject to the terms and conditions of the GNU General Public +-# License. See the file "COPYING" in the main directory of this archive +-# for more details. +-# +-# +- +-BUILTIN_DTB_SOURCE := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_SOURCE)).dtb.o +-ifneq ($(CONFIG_BUILTIN_DTB_SOURCE),"") +-obj-$(CONFIG_OF) += $(BUILTIN_DTB_SOURCE) +-endif +- +-# for CONFIG_OF_ALL_DTBS test +-dtstree := $(srctree)/$(src) +-dtb- := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts)) +diff --git a/scripts/dtc/include-prefixes/xtensa/csp.dts b/scripts/dtc/include-prefixes/xtensa/csp.dts +deleted file mode 100644 +index 885495460f7e..000000000000 +--- a/scripts/dtc/include-prefixes/xtensa/csp.dts ++++ /dev/null +@@ -1,55 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-/ { +- compatible = "cdns,xtensa-xtfpga"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&pic>; +- +- chosen { +- bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk xilinx_uartps.rx_trigger_level=32 loglevel=8 nohz=off ignore_loglevel"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x40000000>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- compatible = "cdns,xtensa-cpu"; +- reg = <0>; +- }; +- }; +- +- pic: pic { +- compatible = "cdns,xtensa-pic"; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- clocks { +- osc: main-oscillator { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- }; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0x00000000 0xf0000000 0x10000000>; +- +- uart0: serial@0d000000 { +- compatible = "xlnx,xuartps", "cdns,uart-r1p8"; +- clocks = <&osc>, <&osc>; +- clock-names = "uart_clk", "pclk"; +- reg = <0x0d000000 0x1000>; +- interrupts = <0 1>; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/xtensa/kc705.dts b/scripts/dtc/include-prefixes/xtensa/kc705.dts +deleted file mode 100644 +index 6887ff090fce..000000000000 +--- a/scripts/dtc/include-prefixes/xtensa/kc705.dts ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-/include/ "xtfpga.dtsi" +-/include/ "xtfpga-flash-128m.dtsi" +- +-/ { +- compatible = "cdns,xtensa-kc705"; +- chosen { +- bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=0x38000000"; +- }; +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x38000000>; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- /* global autoconfigured region for contiguous allocations */ +- linux,cma { +- compatible = "shared-dma-pool"; +- reusable; +- size = <0x04000000>; +- alignment = <0x2000>; +- alloc-ranges = <0x00000000 0x20000000>; +- linux,cma-default; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/xtensa/kc705_nommu.dts b/scripts/dtc/include-prefixes/xtensa/kc705_nommu.dts +deleted file mode 100644 +index d8e194a0f64e..000000000000 +--- a/scripts/dtc/include-prefixes/xtensa/kc705_nommu.dts ++++ /dev/null +@@ -1,18 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-/include/ "xtfpga.dtsi" +-/include/ "xtfpga-flash-128m.dtsi" +- +-/ { +- compatible = "cdns,xtensa-kc705"; +- chosen { +- bootargs = "earlycon=uart8250,mmio32,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug"; +- }; +- memory@0 { +- device_type = "memory"; +- reg = <0x60000000 0x10000000>; +- }; +- soc { +- ranges = <0x00000000 0x90000000 0x10000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/xtensa/lx200mx.dts b/scripts/dtc/include-prefixes/xtensa/lx200mx.dts +deleted file mode 100644 +index 974a8d9041b3..000000000000 +--- a/scripts/dtc/include-prefixes/xtensa/lx200mx.dts ++++ /dev/null +@@ -1,17 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-/include/ "xtfpga.dtsi" +-/include/ "xtfpga-flash-16m.dtsi" +- +-/ { +- compatible = "cdns,xtensa-lx200"; +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x06000000>; +- }; +- pic: pic { +- compatible = "cdns,xtensa-mx"; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/xtensa/lx60.dts b/scripts/dtc/include-prefixes/xtensa/lx60.dts +deleted file mode 100644 +index 7c203c1c746a..000000000000 +--- a/scripts/dtc/include-prefixes/xtensa/lx60.dts ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-/include/ "xtfpga.dtsi" +-/include/ "xtfpga-flash-4m.dtsi" +- +-/ { +- compatible = "cdns,xtensa-lx60"; +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x04000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/xtensa/ml605.dts b/scripts/dtc/include-prefixes/xtensa/ml605.dts +deleted file mode 100644 +index 08e5c8d47197..000000000000 +--- a/scripts/dtc/include-prefixes/xtensa/ml605.dts ++++ /dev/null +@@ -1,12 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +-/include/ "xtfpga.dtsi" +-/include/ "xtfpga-flash-16m.dtsi" +- +-/ { +- compatible = "cdns,xtensa-ml605"; +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x08000000>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/xtensa/virt.dts b/scripts/dtc/include-prefixes/xtensa/virt.dts +deleted file mode 100644 +index 611b98a02a65..000000000000 +--- a/scripts/dtc/include-prefixes/xtensa/virt.dts ++++ /dev/null +@@ -1,72 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/dts-v1/; +- +-/ { +- compatible = "cdns,xtensa-iss"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&pic>; +- +- chosen { +- bootargs = "console=ttyS0,115200n8 debug"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x80000000>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- compatible = "cdns,xtensa-cpu"; +- reg = <0>; +- clocks = <&osc>; +- }; +- }; +- +- clocks { +- osc: osc { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <40000000>; +- }; +- }; +- +- pic: pic { +- compatible = "cdns,xtensa-pic"; +- /* one cell: internal irq number, +- * two cells: second cell == 0: internal irq number +- * second cell == 1: external irq number +- */ +- #address-cells = <0>; +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- pci { +- compatible = "pci-host-ecam-generic"; +- device_type = "pci"; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <0x1>; +- +- bus-range = <0x0 0x3e>; +- reg = <0xf0100000 0x03f00000>; +- +- // BUS_ADDRESS(3) CPU_PHYSICAL(1) SIZE(2) +- ranges = <0x01000000 0x0 0x00000000 0xf0000000 0x0 0x00010000>, +- <0x02000000 0x0 0xf4000000 0xf4000000 0x0 0x08000000>; +- +- // PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(2) +- interrupt-map = < +- 0x0000 0x0 0x0 0x1 &pic 0x0 0x1 +- 0x0800 0x0 0x0 0x1 &pic 0x1 0x1 +- 0x1000 0x0 0x0 0x1 &pic 0x2 0x1 +- 0x1800 0x0 0x0 0x1 &pic 0x3 0x1 +- >; +- +- interrupt-map-mask = <0x1800 0x0 0x0 0x7>; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/xtensa/xtfpga-flash-128m.dtsi b/scripts/dtc/include-prefixes/xtensa/xtfpga-flash-128m.dtsi +deleted file mode 100644 +index 9bf8bad1dd18..000000000000 +--- a/scripts/dtc/include-prefixes/xtensa/xtfpga-flash-128m.dtsi ++++ /dev/null +@@ -1,29 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- soc { +- flash: flash@00000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x00000000 0x08000000>; +- bank-width = <2>; +- device-width = <2>; +- partition@0x0 { +- label = "data"; +- reg = <0x00000000 0x06000000>; +- }; +- partition@0x6000000 { +- label = "boot loader area"; +- reg = <0x06000000 0x00800000>; +- }; +- partition@0x6800000 { +- label = "kernel image"; +- reg = <0x06800000 0x017e0000>; +- }; +- partition@0x7fe0000 { +- label = "boot environment"; +- reg = <0x07fe0000 0x00020000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/xtensa/xtfpga-flash-16m.dtsi b/scripts/dtc/include-prefixes/xtensa/xtfpga-flash-16m.dtsi +deleted file mode 100644 +index 40c2f81f7cb6..000000000000 +--- a/scripts/dtc/include-prefixes/xtensa/xtfpga-flash-16m.dtsi ++++ /dev/null +@@ -1,29 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- soc { +- flash: flash@08000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x08000000 0x01000000>; +- bank-width = <2>; +- device-width = <2>; +- partition@0x0 { +- label = "boot loader area"; +- reg = <0x00000000 0x00400000>; +- }; +- partition@0x400000 { +- label = "kernel image"; +- reg = <0x00400000 0x00600000>; +- }; +- partition@0xa00000 { +- label = "data"; +- reg = <0x00a00000 0x005e0000>; +- }; +- partition@0xfe0000 { +- label = "boot environment"; +- reg = <0x00fe0000 0x00020000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/xtensa/xtfpga-flash-4m.dtsi b/scripts/dtc/include-prefixes/xtensa/xtfpga-flash-4m.dtsi +deleted file mode 100644 +index fb8d3a9f33c2..000000000000 +--- a/scripts/dtc/include-prefixes/xtensa/xtfpga-flash-4m.dtsi ++++ /dev/null +@@ -1,21 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- soc { +- flash: flash@08000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "cfi-flash"; +- reg = <0x08000000 0x00400000>; +- bank-width = <2>; +- device-width = <2>; +- partition@0x0 { +- label = "boot loader area"; +- reg = <0x00000000 0x003f0000>; +- }; +- partition@0x3f0000 { +- label = "boot environment"; +- reg = <0x003f0000 0x00010000>; +- }; +- }; +- }; +-}; +diff --git a/scripts/dtc/include-prefixes/xtensa/xtfpga.dtsi b/scripts/dtc/include-prefixes/xtensa/xtfpga.dtsi +deleted file mode 100644 +index e46ae07bab05..000000000000 +--- a/scripts/dtc/include-prefixes/xtensa/xtfpga.dtsi ++++ /dev/null +@@ -1,137 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/ { +- compatible = "cdns,xtensa-xtfpga"; +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&pic>; +- +- chosen { +- bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x00000000 0x06000000>; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- compatible = "cdns,xtensa-cpu"; +- reg = <0>; +- clocks = <&osc>; +- }; +- }; +- +- pic: pic { +- compatible = "cdns,xtensa-pic"; +- /* one cell: internal irq number, +- * two cells: second cell == 0: internal irq number +- * second cell == 1: external irq number +- */ +- #interrupt-cells = <2>; +- interrupt-controller; +- }; +- +- clocks { +- clk54: clk54 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <54000000>; +- }; +- }; +- +- soc { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- ranges = <0x00000000 0xf0000000 0x10000000>; +- +- osc: main-oscillator { +- #clock-cells = <0>; +- compatible = "cdns,xtfpga-clock"; +- reg = <0x0d020004 0x4>; +- }; +- +- serial0: serial@0d050020 { +- device_type = "serial"; +- compatible = "ns16550a"; +- no-loopback-test; +- reg = <0x0d050020 0x20>; +- reg-shift = <2>; +- reg-io-width = <4>; +- native-endian; +- interrupts = <0 1>; /* external irq 0 */ +- clocks = <&osc>; +- }; +- +- enet0: ethoc@0d030000 { +- compatible = "opencores,ethoc"; +- reg = <0x0d030000 0x4000 0x0d800000 0x4000>; +- native-endian; +- interrupts = <1 1>; /* external irq 1 */ +- local-mac-address = [00 50 c2 13 6f 00]; +- clocks = <&osc>; +- }; +- +- i2s0: xtfpga-i2s@0d080000 { +- #sound-dai-cells = <0>; +- compatible = "cdns,xtfpga-i2s"; +- reg = <0x0d080000 0x40>; +- interrupts = <2 1>; /* external irq 2 */ +- clocks = <&cdce706 4>; +- }; +- +- i2c0: i2c-master@0d090000 { +- compatible = "opencores,i2c-ocores"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0d090000 0x20>; +- reg-shift = <2>; +- reg-io-width = <4>; +- native-endian; +- interrupts = <4 1>; +- clocks = <&osc>; +- +- cdce706: clock-synth@69 { +- compatible = "ti,cdce706"; +- #clock-cells = <1>; +- reg = <0x69>; +- clocks = <&clk54>; +- clock-names = "clk_in0"; +- }; +- }; +- +- spi0: spi@0d0a0000 { +- compatible = "cdns,xtfpga-spi"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0d0a0000 0xc>; +- +- tlv320aic23: sound-codec@0 { +- #sound-dai-cells = <0>; +- compatible = "tlv320aic23"; +- reg = <0>; +- spi-max-frequency = <12500000>; +- }; +- }; +- }; +- +- sound { +- compatible = "simple-audio-card"; +- simple-audio-card,format = "i2s"; +- simple-audio-card,mclk-fs = <256>; +- +- simple-audio-card,cpu { +- sound-dai = <&i2s0>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&tlv320aic23>; +- simple-audio-card,bitclock-master = <0>; +- simple-audio-card,frame-master = <0>; +- clocks = <&cdce706 4>; +- }; +- }; +-}; +-- +2.45.2 + diff --git a/recipes-kernel/linux/linux-yocto-hailo/0002-Hailo-15-SolidRun-initial-support.patch b/recipes-kernel/linux/linux-yocto-hailo/0002-Hailo-15-SolidRun-initial-support.patch deleted file mode 100644 index 3137d41..0000000 --- a/recipes-kernel/linux/linux-yocto-hailo/0002-Hailo-15-SolidRun-initial-support.patch +++ /dev/null @@ -1,308 +0,0 @@ -From 50a8c34f7031d583f1691fc8b2bdea83e691c7c8 Mon Sep 17 00:00:00 2001 -From: Mikhail Anikin -Date: Sun, 14 Apr 2024 15:47:35 +0300 -Subject: [PATCH] Hailo-15 SolidRun initial support - ---- - arch/arm64/boot/dts/hailo/Makefile | 1 + - .../arm64/boot/dts/hailo/hailo15-solidrun.dts | 8 + - arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi | 262 ++++++++++++++++++ - 3 files changed, 271 insertions(+) - create mode 100644 arch/arm64/boot/dts/hailo/hailo15-solidrun.dts - create mode 100644 arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi - -diff --git a/arch/arm64/boot/dts/hailo/Makefile b/arch/arm64/boot/dts/hailo/Makefile -index fac88a37a10a..7dda982e172d 100644 ---- a/arch/arm64/boot/dts/hailo/Makefile -+++ b/arch/arm64/boot/dts/hailo/Makefile -@@ -1,4 +1,5 @@ - # SPDX-License-Identifier: GPL-2.0 -+dtb-$(CONFIG_ARCH_HAILO15) += hailo15-solidrun.dtb - dtb-$(CONFIG_ARCH_HAILO15) += hailo15-evb-2-camera-vpu.dtb - dtb-$(CONFIG_ARCH_HAILO15) += hailo15-evb-security-camera.dtb - dtb-$(CONFIG_ARCH_HAILO15) += hailo15-ginger-imaging-imx334.dtb -diff --git a/arch/arm64/boot/dts/hailo/hailo15-solidrun.dts b/arch/arm64/boot/dts/hailo/hailo15-solidrun.dts -new file mode 100644 -index 000000000000..930480cb6e5a ---- /dev/null -+++ b/arch/arm64/boot/dts/hailo/hailo15-solidrun.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2024 SolidRun Ltd. -+ */ -+ -+/dts-v1/; -+ -+#include "hailo15-sr-som.dtsi" -diff --git a/arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi b/arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi -new file mode 100644 -index 000000000000..cb3b29c9d39c ---- /dev/null -+++ b/arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi -@@ -0,0 +1,262 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2024 SolidRun Ltd. -+ */ -+ -+/dts-v1/; -+ -+#include -+#include "hailo15-base.dtsi" -+#include "hailo15-camera-sensor.h" -+ -+/ { -+ aliases { -+ ethernet0 = ð -+ }; -+ -+ memory { -+ device_type = "memory"; -+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; -+ }; -+ -+ sensor_clk: sensor_clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ }; -+}; -+ -+&csi2rx0 { -+ status = "okay"; -+ ports { -+ port@0 { -+ csi2rx_in_sensor: endpoint { -+ remote-endpoint = <&sensor_out_csi2rx>; -+ }; -+ }; -+ }; -+}; -+ -+ -+&i2c_0 { -+ status = "okay"; -+ gpio_pca: gpio@74 { -+ compatible = "nxp,pca9539"; -+ reg = <0x74>; -+ #gpio-cells = <2>; -+ gpio-controller; -+ gpio-line-names = -+ "pca_0_WL_REG_ON", -+ "pca_1_BT_REG_ON", -+ "pca_2_ETH_RST", -+ "pca_3_ENET_nINT", -+ "pca_4", -+ "pca_5_QSPI_SEL", -+ "pca_6_NC", -+ "pca_7_CAMERA_RST_N", -+ "pca_8_H_PCIE_PERST_N", -+ "pca_9_H_PCIE_CLKREQ_N", -+ "pca_10_H_PCIE_WAKE_N", -+ "pca_11_PCIE_nCLK_N", -+ "pca_12", -+ "pca_13", -+ "pca_14", -+ "pca_15"; -+ // interrupts-extended = <&gpio0 6 IRQ_TYPE_LEVEL_LOW>; -+ reset-gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; -+ }; -+ -+#ifdef SENSOR_IMX678 -+ imx678: camera-sensor@1a { -+ status = "okay"; -+ compatible = "sony,imx678"; -+#else -+ imx334: camera-sensor@1a { -+ status = "okay"; -+ compatible = "sony,imx334"; -+#endif -+ reg = <0x1a>; -+ clocks = <&sensor_clk>; -+ clock-names = "inclk"; -+ clock-frequency = <24000000>; -+ csi-id = <0>; -+ reset-gpios = <&gpio_pca 7 GPIO_ACTIVE_HIGH>; -+ port { -+ sensor_out_csi2rx: endpoint { -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&csi2rx_in_sensor>; -+ link-frequencies = /bits/ 64 <891000000>; -+ }; -+ }; -+ }; -+ -+ eeprom: eeprom@50 { -+ compatible = "atmel,24c02"; -+ reg = <0x50>; -+ pagesize = <16>; -+ }; -+}; -+ -+&i2c_1 { -+ status = "okay"; -+}; -+ -+&i2c_2 { -+ status = "ok"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ -+}; -+ -+&sdio1 { -+ status = "okay"; -+ non-removable; -+ bus-width = <4>; -+ -+ phy-config { -+ card-is-emmc = <0x1>; -+ cmd-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel -+ dat-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel -+ rst-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel -+ clk-pad-values = <0x2 0x2 0x0 0x0>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel -+ sdclkdl-cnfg = <0x0 0x32>; //extdly_en, cckdl_dc -+ drive-strength = <0xC 0xC>; //pad_sp, pad_sn -+ }; -+}; -+ -+ð { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_eth>; -+ // reset-gpios = <&gpio_pca 2 GPIO_ACTIVE_HIGH>; -+ phy1: ethernet-phy@0 { -+ reg = <0>; -+ mxl-8611x,led0_cfg = <( -+ MXL8611X_LEDX_CFG_LINK_UP_TX_ACT_ON | -+ MXL8611X_LEDX_CFG_LINK_UP_RX_ACT_ON | -+ MXL8611X_LEDX_CFG_LINK_UP_1GB_ON | -+ MXL8611X_LEDX_CFG_LINK_UP_100MB_ON | -+ MXL8611X_LEDX_CFG_LINK_UP_10MB_ON -+ )>; -+ mxl-8611x,rx-internal-delay-ps = <1650>; -+ mxl-8611x,tx-internal-delay-ps-100m = <2250>; -+ mxl-8611x,tx-internal-delay-ps-1g = <1200>; -+ }; -+}; -+ -+&pinctrl { -+ pinctrl_eth: eth { -+ pins = "eth_rgmii_tx_clk", -+ "eth_rgmii_tx_ctl", -+ "eth_rgmii_txd_0", -+ "eth_rgmii_txd_1", -+ "eth_rgmii_txd_2", -+ "eth_rgmii_txd_3"; -+ drive-strength = <2>; -+ }; -+}; -+ -+&qspi { -+ status = "okay"; -+ -+ spi0_flash0: flash@0 { -+ /* values for MT25QU01G */ -+ spi-max-frequency = <6250000>; /* 90Mhz in DTR, 166Mhz in STR */ -+ cdns,read-delay = <7>; -+ cdns,tshsl-ns = <30>; -+ cdns,tsd2d-ns = <30>; -+ cdns,tchsh-ns = <5>; -+ cdns,tslch-ns = <3>; -+ }; -+}; -+ -+&hailo_vid_cap { -+ status = "okay"; -+}; -+ -+&hailo_isp { -+ status = "okay"; -+}; -+ -+&hailo_pixel_mux { -+ status = "okay"; -+}; -+ -+&rxwrapper0 { -+ status = "okay"; -+}; -+ -+&hailo_vc8000e { -+ status = "okay"; -+}; -+ -+&vc8000e_reserved { -+ status = "okay"; -+}; -+ -+&xrp { -+ status = "okay"; -+}; -+ -+&xrp_reserved { -+ status = "okay"; -+}; -+ -+ -+&pinctrl { -+ pinctrl_i2c2: i2c2 { -+ function = "i2c2"; -+ groups = "i2c2_1_grp"; -+ }; -+}; -+ -+&gpio0 { -+ gpio-ranges = <&pinctrl 0 0 16>; -+ -+ gpio-line-names = -+ "gpio_in_out_0", -+ "gpio_in_out_1", -+ "DSI_RST", -+ "CAM_TRIG", -+ "M2_RST", -+ "H_GPIO_5", -+ "pca9539_int", -+ "M2_W_RST", -+ "pca9539_reset", -+ "M2_WAKE_N", -+ "M2_CD_N", -+ "H_GPIO_11", -+ "uart3_rxd_pad_in", -+ "uart3_txd_pad_out", -+ "H_GPIO_14", -+ "H_GPIO_15"; -+ -+ pin_CAM_TRIG { -+ gpio-hog; -+ gpios = <3 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "CAM_TRIG"; -+ }; -+}; -+ -+&gpio1 { -+ gpio-ranges = <&pinctrl 0 16 16>; -+ -+ gpio-line-names = -+ "uart2_rxd_pad_in", -+ "uart2_txd_pad_out", -+ "H_GPIO_18", -+ "H_GPIO_19", -+ "H_GPIO_20", -+ "H_GPIO_21", -+ "i2c2_sda_in_out", -+ "i2c2_scl_out", -+ "H_GPIO_24", -+ "H_GPIO_25", -+ "H_GPIO_26", -+ "H_GPIO_27", -+ "uart2_cts_pad_in", -+ "uart2_rts_pad_out", -+ "uart0_cts_pad_in", -+ "uart0_rts_pad_out"; -+}; --- -2.45.0 - diff --git a/recipes-kernel/linux/linux-yocto-hailo/0002-Hailo-15-SolidRun-support.patch b/recipes-kernel/linux/linux-yocto-hailo/0002-Hailo-15-SolidRun-support.patch new file mode 100644 index 0000000..b6bd49f --- /dev/null +++ b/recipes-kernel/linux/linux-yocto-hailo/0002-Hailo-15-SolidRun-support.patch @@ -0,0 +1,1079 @@ +From 29d7ed381117a2ca28e5ed885898bd5b4fefd42a Mon Sep 17 00:00:00 2001 +From: Mikhail Anikin +Date: Sun, 14 Apr 2024 15:47:35 +0300 +Subject: [PATCH 1/3] Hailo-15 SolidRun initial support + +--- + arch/arm64/boot/dts/hailo/Makefile | 1 + + .../arm64/boot/dts/hailo/hailo15-solidrun.dts | 8 + + arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi | 262 ++++++++++++++++++ + 3 files changed, 271 insertions(+) + create mode 100644 arch/arm64/boot/dts/hailo/hailo15-solidrun.dts + create mode 100644 arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi + +diff --git a/arch/arm64/boot/dts/hailo/Makefile b/arch/arm64/boot/dts/hailo/Makefile +index fac88a37a10a..7dda982e172d 100644 +--- a/arch/arm64/boot/dts/hailo/Makefile ++++ b/arch/arm64/boot/dts/hailo/Makefile +@@ -1,4 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0 ++dtb-$(CONFIG_ARCH_HAILO15) += hailo15-solidrun.dtb + dtb-$(CONFIG_ARCH_HAILO15) += hailo15-evb-2-camera-vpu.dtb + dtb-$(CONFIG_ARCH_HAILO15) += hailo15-evb-security-camera.dtb + dtb-$(CONFIG_ARCH_HAILO15) += hailo15-ginger-imaging-imx334.dtb +diff --git a/arch/arm64/boot/dts/hailo/hailo15-solidrun.dts b/arch/arm64/boot/dts/hailo/hailo15-solidrun.dts +new file mode 100644 +index 000000000000..930480cb6e5a +--- /dev/null ++++ b/arch/arm64/boot/dts/hailo/hailo15-solidrun.dts +@@ -0,0 +1,8 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2024 SolidRun Ltd. ++ */ ++ ++/dts-v1/; ++ ++#include "hailo15-sr-som.dtsi" +diff --git a/arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi b/arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi +new file mode 100644 +index 000000000000..cb3b29c9d39c +--- /dev/null ++++ b/arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi +@@ -0,0 +1,262 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2024 SolidRun Ltd. ++ */ ++ ++/dts-v1/; ++ ++#include ++#include "hailo15-base.dtsi" ++#include "hailo15-camera-sensor.h" ++ ++/ { ++ aliases { ++ ethernet0 = ð ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; ++ }; ++ ++ sensor_clk: sensor_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24000000>; ++ }; ++}; ++ ++&csi2rx0 { ++ status = "okay"; ++ ports { ++ port@0 { ++ csi2rx_in_sensor: endpoint { ++ remote-endpoint = <&sensor_out_csi2rx>; ++ }; ++ }; ++ }; ++}; ++ ++ ++&i2c_0 { ++ status = "okay"; ++ gpio_pca: gpio@74 { ++ compatible = "nxp,pca9539"; ++ reg = <0x74>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-line-names = ++ "pca_0_WL_REG_ON", ++ "pca_1_BT_REG_ON", ++ "pca_2_ETH_RST", ++ "pca_3_ENET_nINT", ++ "pca_4", ++ "pca_5_QSPI_SEL", ++ "pca_6_NC", ++ "pca_7_CAMERA_RST_N", ++ "pca_8_H_PCIE_PERST_N", ++ "pca_9_H_PCIE_CLKREQ_N", ++ "pca_10_H_PCIE_WAKE_N", ++ "pca_11_PCIE_nCLK_N", ++ "pca_12", ++ "pca_13", ++ "pca_14", ++ "pca_15"; ++ // interrupts-extended = <&gpio0 6 IRQ_TYPE_LEVEL_LOW>; ++ reset-gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; ++ }; ++ ++#ifdef SENSOR_IMX678 ++ imx678: camera-sensor@1a { ++ status = "okay"; ++ compatible = "sony,imx678"; ++#else ++ imx334: camera-sensor@1a { ++ status = "okay"; ++ compatible = "sony,imx334"; ++#endif ++ reg = <0x1a>; ++ clocks = <&sensor_clk>; ++ clock-names = "inclk"; ++ clock-frequency = <24000000>; ++ csi-id = <0>; ++ reset-gpios = <&gpio_pca 7 GPIO_ACTIVE_HIGH>; ++ port { ++ sensor_out_csi2rx: endpoint { ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&csi2rx_in_sensor>; ++ link-frequencies = /bits/ 64 <891000000>; ++ }; ++ }; ++ }; ++ ++ eeprom: eeprom@50 { ++ compatible = "atmel,24c02"; ++ reg = <0x50>; ++ pagesize = <16>; ++ }; ++}; ++ ++&i2c_1 { ++ status = "okay"; ++}; ++ ++&i2c_2 { ++ status = "ok"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2>; ++ ++}; ++ ++&sdio1 { ++ status = "okay"; ++ non-removable; ++ bus-width = <4>; ++ ++ phy-config { ++ card-is-emmc = <0x1>; ++ cmd-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel ++ dat-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel ++ rst-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel ++ clk-pad-values = <0x2 0x2 0x0 0x0>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel ++ sdclkdl-cnfg = <0x0 0x32>; //extdly_en, cckdl_dc ++ drive-strength = <0xC 0xC>; //pad_sp, pad_sn ++ }; ++}; ++ ++ð { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_eth>; ++ // reset-gpios = <&gpio_pca 2 GPIO_ACTIVE_HIGH>; ++ phy1: ethernet-phy@0 { ++ reg = <0>; ++ mxl-8611x,led0_cfg = <( ++ MXL8611X_LEDX_CFG_LINK_UP_TX_ACT_ON | ++ MXL8611X_LEDX_CFG_LINK_UP_RX_ACT_ON | ++ MXL8611X_LEDX_CFG_LINK_UP_1GB_ON | ++ MXL8611X_LEDX_CFG_LINK_UP_100MB_ON | ++ MXL8611X_LEDX_CFG_LINK_UP_10MB_ON ++ )>; ++ mxl-8611x,rx-internal-delay-ps = <1650>; ++ mxl-8611x,tx-internal-delay-ps-100m = <2250>; ++ mxl-8611x,tx-internal-delay-ps-1g = <1200>; ++ }; ++}; ++ ++&pinctrl { ++ pinctrl_eth: eth { ++ pins = "eth_rgmii_tx_clk", ++ "eth_rgmii_tx_ctl", ++ "eth_rgmii_txd_0", ++ "eth_rgmii_txd_1", ++ "eth_rgmii_txd_2", ++ "eth_rgmii_txd_3"; ++ drive-strength = <2>; ++ }; ++}; ++ ++&qspi { ++ status = "okay"; ++ ++ spi0_flash0: flash@0 { ++ /* values for MT25QU01G */ ++ spi-max-frequency = <6250000>; /* 90Mhz in DTR, 166Mhz in STR */ ++ cdns,read-delay = <7>; ++ cdns,tshsl-ns = <30>; ++ cdns,tsd2d-ns = <30>; ++ cdns,tchsh-ns = <5>; ++ cdns,tslch-ns = <3>; ++ }; ++}; ++ ++&hailo_vid_cap { ++ status = "okay"; ++}; ++ ++&hailo_isp { ++ status = "okay"; ++}; ++ ++&hailo_pixel_mux { ++ status = "okay"; ++}; ++ ++&rxwrapper0 { ++ status = "okay"; ++}; ++ ++&hailo_vc8000e { ++ status = "okay"; ++}; ++ ++&vc8000e_reserved { ++ status = "okay"; ++}; ++ ++&xrp { ++ status = "okay"; ++}; ++ ++&xrp_reserved { ++ status = "okay"; ++}; ++ ++ ++&pinctrl { ++ pinctrl_i2c2: i2c2 { ++ function = "i2c2"; ++ groups = "i2c2_1_grp"; ++ }; ++}; ++ ++&gpio0 { ++ gpio-ranges = <&pinctrl 0 0 16>; ++ ++ gpio-line-names = ++ "gpio_in_out_0", ++ "gpio_in_out_1", ++ "DSI_RST", ++ "CAM_TRIG", ++ "M2_RST", ++ "H_GPIO_5", ++ "pca9539_int", ++ "M2_W_RST", ++ "pca9539_reset", ++ "M2_WAKE_N", ++ "M2_CD_N", ++ "H_GPIO_11", ++ "uart3_rxd_pad_in", ++ "uart3_txd_pad_out", ++ "H_GPIO_14", ++ "H_GPIO_15"; ++ ++ pin_CAM_TRIG { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "CAM_TRIG"; ++ }; ++}; ++ ++&gpio1 { ++ gpio-ranges = <&pinctrl 0 16 16>; ++ ++ gpio-line-names = ++ "uart2_rxd_pad_in", ++ "uart2_txd_pad_out", ++ "H_GPIO_18", ++ "H_GPIO_19", ++ "H_GPIO_20", ++ "H_GPIO_21", ++ "i2c2_sda_in_out", ++ "i2c2_scl_out", ++ "H_GPIO_24", ++ "H_GPIO_25", ++ "H_GPIO_26", ++ "H_GPIO_27", ++ "uart2_cts_pad_in", ++ "uart2_rts_pad_out", ++ "uart0_cts_pad_in", ++ "uart0_rts_pad_out"; ++}; +-- +2.45.2 + + +From 29e23ee8cb7421d870916d6c6fb5fab75ab4f7fd Mon Sep 17 00:00:00 2001 +From: Mikhail Anikin +Date: Wed, 22 May 2024 17:22:39 +0300 +Subject: [PATCH 2/3] Unified camera node + +--- + arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi | 15 ++++----------- + 1 file changed, 4 insertions(+), 11 deletions(-) + +diff --git a/arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi b/arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi +index cb3b29c9d39c..771f093925e8 100644 +--- a/arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi ++++ b/arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi +@@ -7,7 +7,6 @@ + + #include + #include "hailo15-base.dtsi" +-#include "hailo15-camera-sensor.h" + + / { + aliases { +@@ -66,26 +65,20 @@ gpio_pca: gpio@74 { + reset-gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + }; + +-#ifdef SENSOR_IMX678 +- imx678: camera-sensor@1a { ++ sensor_0: camera-sensor@1a { + status = "okay"; +- compatible = "sony,imx678"; +-#else +- imx334: camera-sensor@1a { +- status = "okay"; +- compatible = "sony,imx334"; +-#endif ++ compatible = "sony,imx334", "sony,imx678"; + reg = <0x1a>; + clocks = <&sensor_clk>; + clock-names = "inclk"; + clock-frequency = <24000000>; + csi-id = <0>; +- reset-gpios = <&gpio_pca 7 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + port { + sensor_out_csi2rx: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi2rx_in_sensor>; +- link-frequencies = /bits/ 64 <891000000>; ++ link-frequencies = /bits/ 64 <891000000 1440000000 1782000000>; + }; + }; + }; +-- +2.45.2 + + +From 8519fbc6352b1d4d140c291e55dfcb32f437149c Mon Sep 17 00:00:00 2001 +From: Mikhail Anikin +Date: Mon, 12 Aug 2024 14:48:43 +0300 +Subject: [PATCH 3/3] Split carrier boards + +--- + arch/arm64/boot/dts/hailo/Makefile | 1 + + .../dts/hailo/hailo15-solidrun-hb-pro.dts | 14 + + .../arm64/boot/dts/hailo/hailo15-solidrun.dts | 6 + + arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi | 224 ++++++++++--- + .../boot/dts/hailo/hummingboard-iiot.dtsi | 298 ++++++++++++++++++ + .../boot/dts/hailo/hummingboard-pro.dtsi | 13 + + 6 files changed, 516 insertions(+), 40 deletions(-) + create mode 100644 arch/arm64/boot/dts/hailo/hailo15-solidrun-hb-pro.dts + create mode 100644 arch/arm64/boot/dts/hailo/hummingboard-iiot.dtsi + create mode 100644 arch/arm64/boot/dts/hailo/hummingboard-pro.dtsi + +diff --git a/arch/arm64/boot/dts/hailo/Makefile b/arch/arm64/boot/dts/hailo/Makefile +index 7dda982e172d..2cdceac7c10f 100644 +--- a/arch/arm64/boot/dts/hailo/Makefile ++++ b/arch/arm64/boot/dts/hailo/Makefile +@@ -1,5 +1,6 @@ + # SPDX-License-Identifier: GPL-2.0 + dtb-$(CONFIG_ARCH_HAILO15) += hailo15-solidrun.dtb ++dtb-$(CONFIG_ARCH_HAILO15) += hailo15-solidrun-hb-pro.dtb + dtb-$(CONFIG_ARCH_HAILO15) += hailo15-evb-2-camera-vpu.dtb + dtb-$(CONFIG_ARCH_HAILO15) += hailo15-evb-security-camera.dtb + dtb-$(CONFIG_ARCH_HAILO15) += hailo15-ginger-imaging-imx334.dtb +diff --git a/arch/arm64/boot/dts/hailo/hailo15-solidrun-hb-pro.dts b/arch/arm64/boot/dts/hailo/hailo15-solidrun-hb-pro.dts +new file mode 100644 +index 000000000000..51780d83a990 +--- /dev/null ++++ b/arch/arm64/boot/dts/hailo/hailo15-solidrun-hb-pro.dts +@@ -0,0 +1,14 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2024 SolidRun Ltd. ++ */ ++ ++/dts-v1/; ++ ++#include "hailo15-sr-som.dtsi" ++#include "hummingboard-pro.dtsi" ++ ++/ { ++ model = "SolidRun HummingBoard Pro"; ++ compatible = "hailo,hailo15", "solidrun,hummingboard_pro"; ++}; +diff --git a/arch/arm64/boot/dts/hailo/hailo15-solidrun.dts b/arch/arm64/boot/dts/hailo/hailo15-solidrun.dts +index 930480cb6e5a..9e35aa4ffd40 100644 +--- a/arch/arm64/boot/dts/hailo/hailo15-solidrun.dts ++++ b/arch/arm64/boot/dts/hailo/hailo15-solidrun.dts +@@ -6,3 +6,9 @@ + /dts-v1/; + + #include "hailo15-sr-som.dtsi" ++#include "hummingboard-iiot.dtsi" ++ ++/ { ++ model = "SolidRun HummingBoard IIoT"; ++ compatible = "hailo,hailo15", "solidrun,hummingboard_iiot"; ++}; +diff --git a/arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi b/arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi +index 771f093925e8..645fd6882d1a 100644 +--- a/arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi ++++ b/arch/arm64/boot/dts/hailo/hailo15-sr-som.dtsi +@@ -3,15 +3,15 @@ + * Copyright (c) 2024 SolidRun Ltd. + */ + +-/dts-v1/; ++// /dts-v1/; + + #include + #include "hailo15-base.dtsi" + + / { + aliases { +- ethernet0 = ð +- }; ++ ethernet0 = ð ++ }; + + memory { + device_type = "memory"; +@@ -23,6 +23,23 @@ sensor_clk: sensor_clk { + #clock-cells = <0>; + clock-frequency = <24000000>; + }; ++ ++ wl_reg_on: voltage-regulator-0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "wl_reg_on"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ gpio = <&gpio_pca 0 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ som_qspi_mux: som_qspi_mux { ++ compatible = "gpio-mux"; ++ #mux-control-cells = <0>; ++ mux-gpios = <&gpio_pca 5 GPIO_ACTIVE_HIGH>; ++ idle-state = <0>; ++ }; + }; + + &csi2rx0 { +@@ -36,14 +53,16 @@ csi2rx_in_sensor: endpoint { + }; + }; + +- + &i2c_0 { + status = "okay"; + gpio_pca: gpio@74 { +- compatible = "nxp,pca9539"; +- reg = <0x74>; +- #gpio-cells = <2>; +- gpio-controller; ++ compatible = "nxp,pca9539"; ++ reg = <0x74>; ++ #gpio-cells = <2>; ++ // interrupt-parent = <&gpio0>; ++ // interrupts = <6 IRQ_TYPE_LEVEL_LOW>; ++ reset-gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; ++ gpio-controller; + gpio-line-names = + "pca_0_WL_REG_ON", + "pca_1_BT_REG_ON", +@@ -61,9 +80,7 @@ gpio_pca: gpio@74 { + "pca_13", + "pca_14", + "pca_15"; +- // interrupts-extended = <&gpio0 6 IRQ_TYPE_LEVEL_LOW>; +- reset-gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; +- }; ++ }; + + sensor_0: camera-sensor@1a { + status = "okay"; +@@ -73,21 +90,21 @@ sensor_0: camera-sensor@1a { + clock-names = "inclk"; + clock-frequency = <24000000>; + csi-id = <0>; +- reset-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&gpio_pca 7 GPIO_ACTIVE_HIGH>; + port { + sensor_out_csi2rx: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi2rx_in_sensor>; +- link-frequencies = /bits/ 64 <891000000 1440000000 1782000000>; ++ link-frequencies = /bits/ 64 <891000000 1440000000 1782000000>; + }; + }; + }; + + eeprom: eeprom@50 { +- compatible = "atmel,24c02"; +- reg = <0x50>; +- pagesize = <16>; +- }; ++ compatible = "atmel,24c02"; ++ reg = <0x50>; ++ pagesize = <16>; ++ }; + }; + + &i2c_1 { +@@ -95,19 +112,18 @@ &i2c_1 { + }; + + &i2c_2 { +- status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +- + }; + + &sdio1 { + status = "okay"; + non-removable; + bus-width = <4>; ++ /delete-property/ cap-mmc-hw-reset; + + phy-config { +- card-is-emmc = <0x1>; ++ card-is-emmc = <0x1>; + cmd-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel + dat-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel + rst-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel +@@ -118,7 +134,6 @@ phy-config { + }; + + ð { +- status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth>; + // reset-gpios = <&gpio_pca 2 GPIO_ACTIVE_HIGH>; +@@ -147,20 +162,42 @@ pinctrl_eth: eth { + "eth_rgmii_txd_3"; + drive-strength = <2>; + }; +-}; + +-&qspi { +- status = "okay"; ++ pinctrl_i2c2: i2c2 { ++ function = "i2c2"; ++ groups = "i2c2_1_grp"; ++ }; + +- spi0_flash0: flash@0 { +- /* values for MT25QU01G */ +- spi-max-frequency = <6250000>; /* 90Mhz in DTR, 166Mhz in STR */ +- cdns,read-delay = <7>; +- cdns,tshsl-ns = <30>; +- cdns,tsd2d-ns = <30>; +- cdns,tchsh-ns = <5>; +- cdns,tslch-ns = <3>; ++ pinctrl_uart0_cts_rts: uart0_cts_rts { ++ function = "uart0_cts_rts"; ++ groups = "uart0_cts_rts_1_grp"; + }; ++ ++ pinctrl_usb_overcurrent_n_in: pinctrl_usb_overcurrent_n_in { ++ function = "usb_overcurrent_in"; ++ groups = "usb_overcurrent_in_grp"; ++ }; ++ ++ pinctrl_usb_drive_vbus_out: pinctrl_usb_drive_vbus_out { ++ function = "usb_drive_vbus_out"; ++ groups = "usb_drive_vbus_out_2_grp"; ++ }; ++ ++ pinctrl_uart2: serial2 { ++ function = "uart2"; ++ groups = "uart2_4_grp"; ++ }; ++ ++ // Conflict with USB overcurrent ++ // pinctrl_uart3: serial3 { ++ // function = "uart3"; ++ // groups = "uart3_3_grp"; ++ // }; ++ ++}; ++ ++&vision_subsys { ++ status = "okay"; + }; + + &hailo_vid_cap { +@@ -195,14 +232,6 @@ &xrp_reserved { + status = "okay"; + }; + +- +-&pinctrl { +- pinctrl_i2c2: i2c2 { +- function = "i2c2"; +- groups = "i2c2_1_grp"; +- }; +-}; +- + &gpio0 { + gpio-ranges = <&pinctrl 0 0 16>; + +@@ -253,3 +282,118 @@ &gpio1 { + "uart0_cts_pad_in", + "uart0_rts_pad_out"; + }; ++ ++ ++&serial0 { ++ pinctrl-0 = <&pinctrl_uart0_cts_rts>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ status = "okay"; ++ ++ // bluetooth { ++ // max-speed = <115200>; ++ // compatible = "brcm,bcm4330-bt"; ++ // shutdown-gpios = <&gpio_pca 1 GPIO_ACTIVE_HIGH>; ++ // }; ++}; ++ ++&serial2 { ++ // status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart2>; ++}; ++ ++// Conflict with USB overcurrent ++// &serial3 { ++// status = "okay"; ++// pinctrl-names = "default"; ++// pinctrl-0 = <&pinctrl_uart3>; ++// }; ++ ++&sdio0 { ++ status = "okay"; ++ vqmmc-supply = <&wl_reg_on>; ++ non-removable; ++ phy-config { ++ card-is-emmc = <0x1>; ++ cmd-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel ++ dat-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel ++ rst-pad-values = <0x2 0x2 0x1 0x1>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel ++ clk-pad-values = <0x2 0x2 0x0 0x0>; // txslew_ctrl_n, txslew_ctrl_p, weakpull_enable, rxsel ++ sdclkdl-cnfg = <0x0 0x32>; //extdly_en, cckdl_dc ++ drive-strength = <0xC 0xC>; //pad_sp, pad_sn ++ }; ++ ++ brcmf: wifi@1 { ++ status = "okay"; ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ }; ++}; ++ ++&sdio0_reserved { ++ status = "okay"; ++}; ++ ++ ++&torrent_phy { ++ status = "okay"; ++ torrent_phy_pcie: phy@0 { ++ reg = <0>; ++ resets = <&scmi_reset HAILO15_SCMI_RESET_IDX_PCIE_PHY_LANE_0>, <&scmi_reset HAILO15_SCMI_RESET_IDX_PCIE_PHY_LANE_1>; ++ #phy-cells = <0>; ++ cdns,phy-type = ; ++ cdns,num-lanes = <2>; ++ }; ++ torrent_phy_usb3: phy@3 { ++ reg = <3>; ++ resets = <&scmi_reset HAILO15_SCMI_RESET_IDX_PCIE_PHY_LANE_3>; ++ #phy-cells = <0>; ++ cdns,phy-type = ; ++ cdns,num-lanes = <1>; ++ cdns,ssc-mode = ; ++ }; ++}; ++ ++&usb3 { ++ dr_mode = "host"; ++ phys = <&torrent_phy_usb3>; ++ phy-names = "cdns3,usb3-phy"; ++ pinctrl-names = "default"; ++ // pinctrl-0 = <&pinctrl_usb_overcurrent_n_in>, <&pinctrl_usb_drive_vbus_out>; ++ pinctrl-0 = <&pinctrl_usb_overcurrent_n_in>; ++}; ++ ++/* NOTE: Frequency can't go below 6250000 for the Cadence QSPI IP */ ++&qspi { ++ status = "okay"; ++ spi-max-frequency = <6250000>; ++ /delete-node/ flash@0; ++ hailo_spi_muxed: hailo_spi_muxed@0 { ++ compatible = "spi-mux"; ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <6250000>; ++ mux-controls = <&som_qspi_mux>; ++ hailo,non-flash-device; ++ ++ qspi_firmware_flash: flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "jedec,spi-nor"; ++ reg = <0>; /* chip select */ ++ spi-max-frequency = <6250000>; ++ hailo,non-flash-device; ++ }; ++ ++ b2b_spi: b2b_spi@1 { ++ status = "disabled"; ++ compatible = "hailo,hailo-spi-slave-test"; ++ reg = <1>; ++ spi-max-frequency = <1000000>; ++ hailo,non-flash-device; ++ }; ++ }; ++}; ++ +diff --git a/arch/arm64/boot/dts/hailo/hummingboard-iiot.dtsi b/arch/arm64/boot/dts/hailo/hummingboard-iiot.dtsi +new file mode 100644 +index 000000000000..b90de6697453 +--- /dev/null ++++ b/arch/arm64/boot/dts/hailo/hummingboard-iiot.dtsi +@@ -0,0 +1,298 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2024 SolidRun Ltd. ++ */ ++ ++#include ++ ++/ { ++ carrier_spi_mux: carrier_spi_mux { ++ compatible = "gpio-mux"; ++ #mux-control-cells = <0>; ++ mux-gpios = <&tca6416_21 0 GPIO_ACTIVE_HIGH>; ++ idle-state = <0>; ++ }; ++ ++ lcd_i2c_rst: lcd_i2c_rst { ++ compatible = "regulator-fixed"; ++ regulator-name = "lcd_i2c_rst"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ gpio = <&tca6416_21 4 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++}; ++ ++&i2c_2 { ++ status = "okay"; ++ ++ tca6416_20: gpio@20 { ++ compatible = "ti,tca6416"; ++ reg = <0x20>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-line-names = ++ "TCA_INT/EXT_UART", ++ "TCA_UARTA_232/485", ++ "TCA_UARTB_232/485", ++ "TCA_INT/EXT_CAN", ++ "TCA_NXP/REN", ++ "TCA_M.2B_3V3_EN", ++ "TCA_M.2M_3V3_EN", ++ "TCA_M.2M_RESET#", ++ "TCA_M.2B_RESET#", ++ "TCA_M.2B_W_DIS#", ++ "TCA_M.2B_GPS_EN#", ++ "TCA_USB-HUB_RST#", ++ "TCA_USB_HUB3_PWR_EN", ++ "TCA_USB_HUB4_PWR_EN", ++ "TCA_USB1_PWR_EN", ++ "TCA_VIDEO_PWR_EN"; ++ ++ // TCA_VIDEO_PWR_EN { ++ // gpio-hog; ++ // gpios = <15 GPIO_ACTIVE_HIGH>; ++ // output-high; ++ // line-name = "TCA_VIDEO_PWR_EN"; ++ // }; ++ }; ++ ++ tca6416_21: gpio@21 { ++ compatible = "ti,tca6416"; ++ reg = <0x21>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ // interrupt-parent = <&gpio1>; ++ // interrupts = <9 IRQ_TYPE_LEVEL_LOW>; ++ gpio-line-names = ++ "TCA_SPI_TPM/EXT", ++ "TCA_TPM_RST#", ++ "TCA_I2C_RST", ++ "TCA_RS232_SHTD#", ++ "TCA_LCD_I2C_RST", ++ "TCA_DIG_OUT1", ++ "TCA_bDIG_IN1", ++ "TCA_SENS_INT", ++ "TCA_ALERT#", ++ "TCA_TPM_PIRQ#", ++ "TCA_RTC_INT", ++ "TCA_M.2M_WAKW_ON_LAN", ++ "TCA_M.2M_CLKREQ#", ++ "TCA_LVDS_INT#", ++ "TCA_NC", ++ "TCA_POE_AT"; ++ }; ++ ++ carrier_eeprom: at24c02@57 { ++ compatible = "atmel,24c02"; ++ reg = <0x57>; ++ pagesize = <16>; ++ }; ++ ++ leds: led-controller@30 { ++ compatible = "ti,lp5562"; ++ reg = <0x30>; ++ clock-mode = /bits/ 8 <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pwr-sel = <0>; ++ ++ chan@0 { ++ chan-name = "R"; ++ led-cur = /bits/ 8 <0x20>; ++ max-cur = /bits/ 8 <0x60>; ++ reg = <0>; ++ color = ; ++ }; ++ ++ chan@1 { ++ chan-name = "G"; ++ led-cur = /bits/ 8 <0x20>; ++ max-cur = /bits/ 8 <0x60>; ++ reg = <1>; ++ color = ; ++ }; ++ ++ chan@2 { ++ chan-name = "B"; ++ led-cur = /bits/ 8 <0x20>; ++ max-cur = /bits/ 8 <0x60>; ++ reg = <2>; ++ color = ; ++ }; ++ ++ chan@3 { ++ chan-name = "D8"; ++ led-cur = /bits/ 8 <0x20>; ++ max-cur = /bits/ 8 <0x60>; ++ reg = <3>; ++ color = ; ++ }; ++ }; ++ ++ rtc: am1805@69 { ++ compatible = "abracon,ab1805"; ++ reg = <0x69>; ++ abracon,tc-diode = "schottky"; ++ abracon,tc-resistor = <3>; ++ }; ++ ++ charger: battery-charger@68 { ++ // Not assembled ++ status = "disabled"; ++ compatible = "lltc,ltc4162-l"; ++ reg = <0x68>; ++ // lltc,rsnsb-micro-ohms = <10000>; ++ // lltc,rsnsi-micro-ohms = <16000>; ++ // lltc,cell-count = <2>; ++ }; ++ ++ accelerometer: accelerometer@2a { ++ // Not assembled ++ status = "disabled"; ++ compatible = "adi,adxl345"; ++ reg = <0x53>; ++ // interrupt-parent = <&tca6416_21>; ++ // interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ ambient_light: ambient_light@44 { ++ // Not assembled ++ status = "disabled"; ++ compatible = "isil,isl29023"; ++ reg = <0x44>; ++ // interrupt-parent = <&tca6416_21>; ++ // interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++}; ++ ++&i2c_1 { ++ i2c-switch@70 { ++ compatible = "nxp,pca9546"; ++ reg = <0x70>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reset-gpios = <&tca6416_21 2 GPIO_ACTIVE_LOW>; ++ ++ i2c_ext: i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ }; ++ ++ i2c_csi: i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ ++ // sensor_1: imx219@10 { ++ // compatible = "sony,imx219"; ++ // reg = <0x10>; ++ // clocks = <&sensor_clk>; ++ // // VANA-supply = <&imx219_vana_2v8>; ++ // // VDIG-supply = <&imx219_vdig_1v8>; ++ // // VDDL-supply = <&imx219_vddl_1v2>; ++ ++ // port { ++ // imx219_0: endpoint { ++ // remote-endpoint = <&csi2_in>; ++ // clock-lanes = <0>; ++ // data-lanes = <1 2>; ++ // link-frequencies = /bits/ 64 <456000000>; ++ // }; ++ // }; ++ // }; ++ }; ++ ++ i2c_dsi: i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ }; ++ ++ i2c_lvds: i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ ++ gpio_lvds_expander: tca6408@20 { ++ compatible = "ti,tca6408"; ++ reg = <0x20>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ vcc-supply = <&lcd_i2c_rst>; ++ gpio-line-names = ++ "SELB", ++ "LVDS_RESET", ++ "LVDS_STBYB", ++ "LVDS_PWM_BL", ++ "LVDS_L/R", ++ "LVDS_U/D", ++ "LVDS_CTP_/RST", ++ "NC"; ++ }; ++ ++ gpio_dsi_expander: tca6408@21 { ++ compatible = "ti,tca6408"; ++ reg = <0x21>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ vcc-supply = <&lcd_i2c_rst>; ++ gpio-line-names = ++ "NC", ++ "DSI_RESET", ++ "DSI_STBYB", ++ "DSI_PWM_BL", ++ "DSI_L/R", ++ "DSI_U/D", ++ "DSI_CTP_/RST", ++ "NC"; ++ ++ // DSI_PWM_BL { ++ // gpio-hog; ++ // gpios = <3 GPIO_ACTIVE_HIGH>; ++ // output-low; ++ // line-name = "DSI_PWM_BL"; ++ // }; ++ }; ++ }; ++ }; ++ ++ /* usb_hub: CYUSB3304@60 {}; */ ++}; ++ ++/* NOTE: Frequency can't go below 6250000 for hailo unit */ ++&hailo_spi_muxed { ++ /delete-node/ b2b_spi@1; ++ ++ carrier_spi_muxed: carrier_spi_muxed@1 { ++ compatible = "spi-mux"; ++ reg = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <6250000>; ++ mux-controls = <&carrier_spi_mux>; ++ ++ carrier_tpm: tpm@0 { ++ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; ++ reg = <0>; ++ spi-max-frequency = <6250000>; ++ }; ++ ++ carrier_conn: carrier_conn_spi@1 { ++ status = "disabled"; ++ compatible = "hailo,hailo-spi-slave-test"; ++ reg = <1>; ++ spi-max-frequency = <6250000>; ++ }; ++ }; ++}; ++ ++&usb3 { ++ status = "okay"; ++}; ++ ++ð { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/hailo/hummingboard-pro.dtsi b/arch/arm64/boot/dts/hailo/hummingboard-pro.dtsi +new file mode 100644 +index 000000000000..b55fcf8cd0cd +--- /dev/null ++++ b/arch/arm64/boot/dts/hailo/hummingboard-pro.dtsi +@@ -0,0 +1,13 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2024 SolidRun Ltd. ++ */ ++ ++ ++ð { ++ status = "okay"; ++}; ++ ++&b2b_spi { ++ status = "okay"; ++}; +-- +2.45.2 + diff --git a/recipes-kernel/linux/linux-yocto-hailo/solidrun-H15-SOM.cfg b/recipes-kernel/linux/linux-yocto-hailo/solidrun-H15-SOM.cfg index f1ca33f..3a7675b 100644 --- a/recipes-kernel/linux/linux-yocto-hailo/solidrun-H15-SOM.cfg +++ b/recipes-kernel/linux/linux-yocto-hailo/solidrun-H15-SOM.cfg @@ -1,3 +1,19 @@ CONFIG_MAXLINEAR_8611X_PHY=y CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT25=y +CONFIG_MULTIPLXER=y +CONFIG_MUX_GPIO=y +CONFIG_SPI_MUX=y + +CONFIG_I2C_MUX_GPIO=m +CONFIG_I2C_MUX_GPMUX=m +CONFIG_I2C_MUX_PCA954x=m +CONFIG_SPI_MUX=y +CONFIG_BACKLIGHT_LED=m +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_LP55XX_COMMON=m +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_LP5562 is not set +# CONFIG_LEDS_LP8501 is not set +CONFIG_RTC_DRV_ABX80X=m